Patent Publication Number: US-2023146060-A1

Title: Three-dimensional semiconductor devices

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This U.S. non-provisional patent application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2021-0152930, filed on Nov. 9, 2021, in the Korean Intellectual Property Office, the entire contents of which are hereby incorporated by reference. 
     BACKGROUND OF THE INVENTION 
     The present disclosure relates to a three-dimensional semiconductor device and a method of fabricating the same, and in particular, to a three-dimensional semiconductor device including a field effect transistor and a method of fabricating the same. 
     A semiconductor device includes an integrated circuit (e.g., metal-oxide-semiconductor field-effect transistors (MOS-FETs)). To meet an increasing demand for a semiconductor device with a small pattern size and a reduced design rule, the MOS-FETs are being aggressively scaled down. The scale-down of the MOS-FETs may lead to deterioration in operational properties of the semiconductor device. A variety of studies are being conducted to overcome technical limitations associated with the scale-down of the semiconductor device and to realize the semiconductor devices with high performance. 
     SUMMARY 
     Some embodiments of the inventive concept provide three-dimensional semiconductor devices with improved reliability. 
     Some embodiments of the inventive concept provide methods of fabricating a three-dimensional semiconductor device with improved reliability. 
     According to some embodiments of the inventive concept, a three-dimensional (3D) semiconductor device may include a first active region on a substrate, the first active region including a lower channel pattern and a pair of lower source/drain patterns, respectively on side surfaces of the lower channel pattern, a second active region on (e.g., stacked on) the first active region, the second active region including an upper channel pattern and a pair of upper source/drain patterns, respectively on opposing side surfaces of the upper channel pattern, a dummy channel pattern between the lower channel pattern and the upper channel pattern, a pair of liner layers, respectively on opposing side surfaces of the dummy channel pattern, and a gate electrode on the lower channel pattern, the dummy channel pattern, and the upper channel pattern. The gate electrode may include a lower gate electrode on the lower channel pattern and an upper gate electrode on the upper channel pattern. 
     According to some embodiments of the inventive concept, a three-dimensional (3D) semiconductor device include a first active region on a substrate, the first active region including a lower channel pattern and a lower source/drain pattern connected to (e.g., electrically connected) the lower channel pattern, a second active region on (e.g., stacked on) the first active region, the second active region including an upper channel pattern and an upper source/drain pattern connected to (e.g., electrically connected) the upper channel pattern, a dummy channel pattern between the lower channel pattern and the upper channel pattern, and a gate electrode on the lower channel pattern, the dummy channel pattern, and the upper channel pattern. The gate electrode may include a first portion between the lower channel pattern and the dummy channel pattern and a second portion between the dummy channel pattern and the upper channel pattern. The first portion may include a first metal pattern including a first work function metal and a second metal pattern including a second work function metal, and the second portion may include a third metal pattern including the first work function metal. A thickness of the third metal pattern (e.g., a thickness in a vertical direction) may be different from a thickness of the first metal pattern (e.g., a thickness in the vertical direction). 
     According to some embodiments of the inventive concept, a three-dimensional (3D) semiconductor device include a lower channel pattern on a substrate, the lower channel pattern including a first semiconductor pattern and a second semiconductor pattern, which are stacked to be spaced apart from each other, an upper channel pattern on the lower channel pattern, the upper channel pattern including a third semiconductor pattern and a fourth semiconductor pattern, which are stacked to be spaced apart from each other, a dummy channel pattern between the second semiconductor pattern and the third semiconductor pattern, and a gate electrode in which the first, second, third and fourth semiconductor patterns and the dummy channel pattern are provided. In some embodiments, the gate electrode may enclose the first to fourth semiconductor patterns and the dummy channel pattern. The first to fourth semiconductor patterns and the dummy channel pattern may be vertically overlapped with each other. A thickness of the dummy channel pattern in a vertical direction may be larger than respective thicknesses of the first to fourth semiconductor patterns in the vertical direction. 
    
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         FIG.  1    is a conceptual diagram illustrating a logic cell of a semiconductor device according to a comparative example. 
         FIG.  2    is a conceptual diagram illustrating a logic cell of a semiconductor device according to an embodiment of the inventive concept. 
         FIG.  3    is a plan view illustrating a three-dimensional semiconductor device according to an embodiment of the inventive concept. 
         FIGS.  4 A to  4 D  are sectional views, which are respectively taken along lines A-A′, B-B′, C-C′, and D-D′ of  FIG.  3   . 
         FIGS.  5  to  7    are enlarged sectional views, each of which illustrates a portion ‘M’ of  FIG.  4 A , according to embodiments of the inventive concept. 
         FIGS.  8 A,  8 B,  9 A,  9 B,  10 A,  10 B,  11 A,  11 B,  12 A,  12 B,  13 A,  13 B,  14 A,  14 B,  15 A,  15 B,  16 A,  16 B,  17 A and  17 B  are sectional views illustrating a method of fabricating a semiconductor device, according to an embodiment of the inventive concept. 
         FIGS.  18  to  23    are sectional views, which are respectively taken along a line D-D′ of  FIG.  3    to illustrate a method of forming a gate electrode according to an embodiment of the inventive concept. 
         FIG.  24    is a plan view illustrating a three-dimensional semiconductor device according to an embodiment of the inventive concept. 
         FIGS.  25 A to  25 D  are sectional views, which are respectively taken along lines A-A′, B-B′, C-C′, and D-D′ of  FIG.  24   . 
     
    
    
     DETAILED DESCRIPTION 
       FIG.  1    is a conceptual diagram illustrating a logic cell of a semiconductor device according to a comparative example. In detail,  FIG.  1    illustrates a logic cell of a two-dimensional device according to the comparative example. 
     Referring to  FIG.  1   , a single height cell SHC′ may be provided. In detail, a first power line POR 1  and a second power line POR 2  may be provided on a substrate  100 . A drain voltage VDD (i.e., a power voltage) may be applied to one of the first and second power lines POR 1  and POR 2 . A source voltage VSS (i.e., a ground voltage) may be applied to the other of the first and second power lines POR 1  and POR 2 . In an embodiment, the source voltage VSS may be applied to the first power line POR 1 , and the drain voltage VDD may be applied to the second power line POR 2 . 
     The single height cell SHC′ may be defined between the first power line POR 1  and the second power line POR 2 . The single height cell SHC′ may include a first active region AR 1  and a second active region AR 2 . One of the first and second active regions AR 1  and AR 2  may be a PMOSFET region, and the other of the first and second active regions AR 1  and AR 2  may be an NMOSFET region. As an example, the first active region AR 1  may be the NMOSFET region, and the second active region AR 2  may be the PMOSFET region. In other words, the single height cell SHC′ may have a CMOS structure provided between the first power line POR 1  and the second power line POR 2 . 
     The semiconductor device according to the comparative example may be a two-dimensional device, in which transistors of a front-end-of-line (FEOL) layer are two-dimensionally arranged. For example, NMOSFETs of the first active region AR 1  and PMOSFETs of the second active region AR 2  may be formed to be spaced apart from each other in a first direction D 1 . 
     Each of the first and second active regions AR 1  and AR 2  may have a first width W 1  in the first direction D 1 . In the comparative example, a length of the single height cell SHC′ in the first direction D 1  may be defined as a first height HE 1 . The first height HE 1  may be substantially equal to a distance (e.g., pitch) between the first and second power lines POR 1  and POR 2  (e.g., a distance between centers of the first and second power lines POR 1  and POR 2 ). 
     The single height cell SHC′ may constitute a single logic cell. In the present specification, the logic cell may mean a logic device (e.g., AND, OR, XOR, XNOR, inverter, and so forth), which is configured to execute a specific function. For example, the logic cell may include transistors constituting the logic device and interconnection lines connecting the transistors to each other. 
     Since the single height cell SHC′ according to the comparative example includes a two-dimensional device, the first active region AR 1  and the second active region AR 2  may not be overlapped with each other but may be arranged to be spaced apart from each other in the first direction D 1 . Thus, the first height HE 1  should be defined in such a way that both of the first and second active regions AR 1  and AR 2 , which are spaced apart from each other in the first direction D 1 , are included in the single height cell SHC′. As a result, the first height HE 1  of the single height cell SHC′ according to the comparative example should be a relatively large value. In other words, the single height cell SHC′ according to the comparative example may have a relatively large area. 
       FIG.  2    is a conceptual diagram illustrating a logic cell of a semiconductor device according to an embodiment of the inventive concept.  FIG.  2    illustrates a logic cell of a three-dimensional device according to an embodiment of the inventive concept. 
     Referring to  FIG.  2   , a single height cell SHC including a three-dimensional device (e.g., stacked transistors) may be provided. In detail, a first power line POR 1  and a second power line POR 2  may be provided on a substrate  100 . The single height cell SHC may be defined between the first power line POR 1  and the second power line POR 2 . 
     The single height cell SHC may include first and second active regions AR 1  and AR 2 . One of the first and second active regions AR 1  and AR 2  may be a PMOSFET region, and the other of the first and second active regions AR 1  and AR 2  may be an NMOSFET region. 
     The semiconductor device according to the present embodiment may be a three-dimensional device, in which transistors of an FEOL layer are vertically stacked. The first active region AR 1  as a bottom tier may be provided on the substrate  100 , and the second active region AR 2  as a top tier may be stacked on the first active region AR 1 . For example, NMOSFETs of the first active region AR 1  may be provided on the substrate  100 , and PMOSFETs of the second active region AR 2  may be stacked on the NMOSFETs. The first active region AR 1  and the second active region AR 2  may be spaced apart from each other in a vertical direction (i.e., a third direction D 3 ). 
     Each of the first and second active regions AR 1  and AR 2  may have a first width W 1  in a first direction D 1 . In the present embodiment, a length of the single height cell SHC in the first direction D 1  may be defined as a second height HE 2 . 
     Since the single height cell SHC according to the present embodiment includes the three-dimensional device (i.e., the stacked transistors), the first active region AR 1  may be overlapped with the second active region AR 2 . Thus, the second height HE 2  of the single height cell SHC may be designed to be slightly larger than a width of a single active region (i.e., the first width W 1 ). As a result, the second height HE 2  of the single height cell SHC according to the present embodiment may be smaller than the first height HE 1  of the single height cell SHC′ described with reference to  FIG.  1   . In other words, the single height cell SHC according to the present embodiment may have a relatively small area. In the three-dimensional semiconductor device according to the present embodiment, it may be possible to reduce an area for the logic cell and thereby to increase an integration density of the semiconductor device. 
       FIG.  3    is a plan view illustrating a three-dimensional semiconductor device according to an embodiment of the inventive concept.  FIGS.  4 A to  4 D  are sectional views, which are respectively taken along lines A-A′, B-B′, C-C′, and D-D′ of  FIG.  3   . The three-dimensional semiconductor device illustrated in  FIGS.  3  and  4 A to  4 D  is provided as an example of the single height cell SHC of  FIG.  2   , and the inventive concept is not limited to this example. 
     Referring to  FIGS.  3  and  4 A to  4 D , a logic cell LC may be provided on the substrate  100 . The substrate  100  may be a semiconductor substrate, which is formed of or include silicon, germanium, silicon germanium, or compound semiconductor materials. In an embodiment, the substrate  100  may be a silicon wafer. 
     The logic cell LC may include the first and second active regions AR 1  and AR 2  sequentially stacked on the substrate  100 . One of the first and second active regions AR 1  and AR 2  may be a PMOSFET region, and the other of the first and second active regions AR 1  and AR 2  may be an NMOSFET region. The first active region AR 1  may be provided as a bottom tier of the FEOL layer, and the second active region AR 2  may be provided as a top tier of the FEOL layer. The NMOS- and PMOS-FETs of the first and second active regions AR 1  and AR 2  may be vertically stacked to form a three-dimensional stack transistor (3DS FET). In the present embodiment, the first active region AR 1  may be an NMOSFET region, and the second active region AR 2  may be a PMOSFET region. When viewed in a plan view, the first and second active regions AR 1  and AR 2  stacked may be located between the first power line POR 1  and the second power line POR 2 . 
     An active pattern AP may be defined by a trench TR, which is formed in an upper portion of the substrate  100 . The active pattern AP may be a vertically-protruding portion of the substrate  100 . When viewed in a plan view, the active pattern AP may have a bar shape extending in a second direction D 2 . The first and second active regions AR 1  and AR 2  may be sequentially stacked on the active pattern AP. 
     A device isolation layer ST may be provided to fill the trench TR. The device isolation layer ST may include a silicon oxide layer. A top surface of the device isolation layer ST may be coplanar with or lower than a top surface of the active pattern AP. The device isolation layer ST may not cover lower and upper channel patterns CH 1  and CH 2 , which will be described below. As used herein, a bottom surface of an element may refer to a surface facing the substrate  100 , and a top surface may be opposite the bottom surface. 
     The first active region AR 1 , which includes lower channel patterns CH 1  and lower source/drain patterns SD 1 , may be provided on the active pattern AP. Each of the lower channel patterns CH 1  may be interposed between a pair of the lower source/drain patterns SD 1 . The lower channel pattern CH 1  may connect the pair of the lower source/drain patterns SD 1  to each other. 
     The lower channel pattern CH 1  may include a first semiconductor pattern SP 1  and a second semiconductor pattern SP 2 , which are sequentially stacked. The first and second semiconductor patterns SP 1  and SP 2  may be spaced apart from each other in a vertical direction (i.e., the third direction D 3 ). Each of the first and second semiconductor patterns SP 1  and SP 2  may be formed of or include at least one of silicon (Si), germanium (Ge), or silicon germanium (SiGe). In an embodiment, each of the first and second semiconductor patterns SP 1  and SP 2  may be formed of or include crystalline silicon. 
     The lower source/drain patterns SD 1  may be provided on the top surface of the active pattern AP. Each of the lower source/drain patterns SD 1  may be an epitaxial pattern, which is formed by a selective epitaxial growth (SEG) process. As an example, a top surface of the lower source/drain pattern SD 1  may be higher than a top surface of the second semiconductor pattern SP 2  of the lower channel pattern CH 1 . 
     The lower source/drain patterns SD 1  may be doped to have a first conductivity type. The first conductivity type may be a p- or n-type. In the present embodiment, the first conductivity type may be an n-type. The lower source/drain patterns SD 1  may be formed of or include silicon (Si) and/or silicon germanium (SiGe). 
     A first interlayer insulating layer  110  may be provided on the lower source/drain patterns SD 1 . The first interlayer insulating layer  110  may cover the lower source/drain patterns SD 1 . A second interlayer insulating layer  120  and the second active region AR 2  may be provided on the first interlayer insulating layer  110 . 
     The second active region AR 2  may include upper channel patterns CH 2  and upper source/drain patterns SD 2 . The upper channel patterns CH 2  may be vertically overlapped with the lower channel patterns CH 1 , respectively. The upper source/drain patterns SD 2  may be vertically overlapped with the lower source/drain patterns SD 1 , respectively. Each of the upper channel patterns CH 2  may be interposed between a pair of the upper source/drain patterns SD 2 . The upper channel pattern CH 2  may connect the pair of the upper source/drain patterns SD 2  to each other. 
     The upper channel pattern CH 2  may include a third semiconductor pattern SP 3  and a fourth semiconductor pattern SP 4 , which are sequentially stacked. The third and fourth semiconductor patterns SP 3  and SP 4  may be spaced apart from each other in the third direction D 3 . The third and fourth semiconductor patterns SP 3  and SP 4  of the upper channel pattern CH 2  may be formed of or include the same semiconductor materials as the first and second semiconductor patterns SP 1  and SP 2  of the lower channel pattern CH 1  described above. 
     At least one dummy channel pattern DSP may be interposed between the lower channel pattern CH 1  and the upper channel pattern CH 2  thereon. The dummy channel pattern DSP may be spaced apart from the lower source/drain patterns SD 1 . The dummy channel pattern DSP may be spaced apart from the upper source/drain patterns SD 2 . In other words, the dummy channel pattern DSP may not be connected to (e.g., electrically connected to) any source/drain pattern. The dummy channel pattern DSP may be formed of or include at least one of semiconductor materials (e.g., silicon (Si), germanium (Ge), or silicon germanium (SiGe)) or silicon-based insulating materials (e.g., silicon oxide or silicon nitride). In an embodiment, the dummy channel pattern DSP may be formed of or include at least one of the silicon-based insulating materials. As used herein, a silicon-based insulating material may refer to an insulating material including silicon. In some embodiments, the dummy channel pattern DSP and the lower and upper channel patterns CH 1  and CH 2  may have an equal width (e.g., an equal width in the first direction D 1  or the second direction D 2 ), and side surfaces of the dummy channel pattern DSP and the lower and upper channel patterns CH 1  and CH 2  may be coplanar with each other as illustrated in  FIG.  4 A . 
     The upper source/drain patterns SD 2  may be provided on a top surface of the first interlayer insulating layer  110 . Each of the upper source/drain patterns SD 2  may be an epitaxial pattern, which is formed by a selective epitaxial growth (SEG) process. In an embodiment, a top surface of the upper source/drain pattern SD 2  may be higher than a top surface of the fourth semiconductor pattern SP 4  of the upper channel pattern CH 2 . 
     The upper source/drain patterns SD 2  may be doped to have a second conductivity type. The second conductivity type may be different from the first conductivity type of the lower source/drain pattern SD 1 . For example, the second conductivity type may be a p-type. The upper source/drain patterns SD 2  may be formed of or include silicon germanium (SiGe) and/or silicon (Si). 
     The second interlayer insulating layer  120  may cover the upper source/drain patterns SD 2 . A top surface of the second interlayer insulating layer  120  may be coplanar with a top surface of each of first and second active contacts AC 1  and AC 2 , which will be described below. 
     A gate electrode GE may be provided on the lower and upper channel patterns CH 1  and CH 2 , which are sequentially stacked. When viewed in a plan view, the gate electrode GE may have a bar shape extending in the first direction D 1 . In an embodiment, a plurality of gate electrodes GE may be provided on the substrate  100 . The gate electrodes GE may be arranged in the second direction D 2  with a first pitch. Each of the gate electrodes GE may be vertically overlapped with the lower and upper channel patterns CH 1  and CH 2  which are stacked. 
     The gate electrode GE may be extended from the top surface of the device isolation layer ST (or the top surface of the active pattern AP) to a gate capping pattern GP in a vertical direction (i.e., the third direction D 3 ). The gate electrode GE may be extended from the lower channel pattern CH 1  of the first active region AR 1  to the upper channel pattern CH 2  of the second active region AR 2  in the third direction D 3 . The gate electrode GE may be extended from the lowermost one of the first semiconductor patterns SP 1  to the uppermost one of the fourth semiconductor patterns SP 4  in the third direction D 3 . 
     The gate electrode GE may be provided on a top surface, a bottom surface, and opposite side surfaces of each of the first to fourth semiconductor patterns SP 1  to SP 4 . That is, the transistor according to the present embodiment may include a three-dimensional field effect transistor (e.g., MBCFET or GAAFET) in which the gate electrode GE is provided to three-dimensionally surround the channel pattern. 
     The gate electrode GE may include a lower gate electrode LGE, which is provided in the bottom tier (i.e., the first active region AR 1 ) of the FEOL layer, and an upper gate electrode UGE, which is provided in the top tier (i.e., the second active region AR 2 ) of the FEOL layer. The lower gate electrode LGE and the upper gate electrode UGE may be vertically overlapped with each other. The lower gate electrode LGE and the upper gate electrode UGE may be connected to each other. In other words, the gate electrode GE according to the present embodiment may be a common gate electrode, which is realized by connecting the lower gate electrode LGE on the lower channel pattern CH 1  to the upper gate electrode UGE on the upper channel pattern CH 2 . 
     The lower gate electrode LGE may include a first portion PO 1  interposed between the active pattern AP and the first semiconductor pattern SP 1 , a second portion PO 2  interposed between the first semiconductor pattern SP 1  and the second semiconductor pattern SP 2 , and a third portion PO 3  interposed between the second semiconductor pattern SP 2  and the dummy channel pattern DSP. A top surface of the lower gate electrode LGE may be located at a level between a top surface and a bottom surface of the dummy channel pattern DSP. 
     The upper gate electrode UGE may include a fourth portion PO 4  interposed between the dummy channel pattern DSP and the third semiconductor pattern SP 3 , a fifth portion PO 5  interposed between the third semiconductor pattern SP 3  and the fourth semiconductor pattern SP 4 , and a sixth portion PO 6  on the fourth semiconductor pattern SP 4 . A bottom surface of the upper gate electrode UGE may be in direct contact with the top surface of the lower gate electrode LGE. 
     A pair of gate spacers GS may be respectively disposed on opposite side surfaces of the gate electrode GE. Referring to  FIG.  4 A , a pair of the gate spacers GS may be respectively disposed on opposite side surfaces of the sixth portion PO 6 . The gate spacers GS may be extended along the gate electrode GE and in the first direction D 1 . Top surfaces of the gate spacers GS may be higher than a top surface of the gate electrode GE. The top surfaces of the gate spacers GS may be coplanar with the top surface of the second interlayer insulating layer  120 . The gate spacers GS may be formed of or include at least one of SiCN, SiCON, or SiN. As another example, the gate spacers GS may include a multi-layer containing at least two of SiCN, SiCON, or SiN. A pair of liner layers LIN may be respectively provided on opposite side surfaces of each of the third and fourth portions PO 3  and PO 4  of the gate electrode GE. 
     The gate capping pattern GP may be provided on the top surface of the gate electrode GE. The gate capping pattern GP may be extended along the gate electrode GE and in the first direction D 1 . For example, the gate capping pattern GP may be formed of or include at least one of SiON, SiCN, SiCON, or SiN. 
     A gate insulating layer UGI or LGI may be interposed between the gate electrode GE and the first to fourth semiconductor patterns SP 1  to SP 4 . More specifically, a lower gate insulating layer LGI may be interposed between the lower gate electrode LGE and the first and second semiconductor patterns SP 1  and SP 2 . An upper gate insulating layer UGI may be interposed between the upper gate electrode UGE and the third and fourth semiconductor patterns SP 3  and SP 4 . 
     Each of the lower and upper gate insulating layers UGI and LGI may include a silicon oxide layer, a silicon oxynitride layer, and/or a high-k dielectric layer. In an embodiment, each of the lower and upper gate insulating layers UGI and LGI may include a silicon oxide layer, which is provided to directly cover a surface of at least one of the first to fourth semiconductor pattern SP 1  to SP 4 , and a high-k dielectric layer, which is provided on the silicon oxide layer. In other words, each of the lower and upper gate insulating layers UGI and LGI may have a multi-layered structure. 
     The high-k dielectric layer may be formed of or include at least one of high-k dielectric materials whose dielectric constants are higher than that of silicon oxide. For example, the high-k dielectric material may include at least one of hafnium oxide, hafnium silicon oxide, hafnium zirconium oxide, hafnium tantalum oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, or lead zinc niobate. 
     In an embodiment, the lower gate insulating layer LGI may include a first dipole element. The first dipole element may include lanthanum (La), aluminum (Al), or a combination thereof. That is, the lower gate insulating layer LGI may contain at least one of lanthanum (La) or aluminum (Al) as an impurity. The lower gate insulating layer LGI may include a dipole-interface, which is formed between the high-k dielectric layer and the silicon oxide layer by the dipole element. 
     As an example, in the case where the lower gate insulating layer LGI contains lanthanum (La), an effective work function of the lower gate electrode LGE may be lowered. As a result, a threshold voltage of an NMOS transistor in the first active region AR 1  may be lowered. As another example, in the case where the lower gate insulating layer LGI contains aluminum (Al), the effective work function of the lower gate electrode LGE may be increased. As a result, the threshold voltage of the NMOS transistor in the first active region AR 1  may be increased. 
     In an embodiment, the upper gate insulating layer UGI may not include the dipole element. For example, the highest concentration of the dipole element in the upper gate insulating layer UGI may be lower than the highest concentration of the dipole element in the lower gate insulating layer LGI. 
     In another embodiment, the upper gate insulating layer UGI may include a second dipole element. The second dipole element may be the same as or different from the first dipole element. The highest concentration of the second dipole element in the upper gate insulating layer UGI may be equal to or different from the highest concentration of the first dipole element in the lower gate insulating layer LGI. 
     The lower gate electrode LGE may include a first metal pattern MP 1  on the first and second semiconductor patterns SP 1  and SP 2  and a second metal pattern MP 2  on the first metal pattern MP 1 . The first metal pattern MP 1  may include a first work function metal, and the second metal pattern MP 2  may include a second work function metal. By adjusting compositions of the first and second work function metals, the transistor of the first active region AR 1  may be formed to have a desired threshold voltage. 
     The first work function metal of the first metal pattern MP 1  may be a p-type work function metal having a relatively high work function. The first metal pattern MP 1  may be formed of or include at least one of metal nitrides. The first metal pattern MP 1  may include at least one metallic element, which is selected from the group consisting of titanium (Ti), tantalum (Ta), aluminum (Al), tungsten (W), and molybdenum (Mo), and nitrogen (N). For example, the first metal pattern MP 1  may be formed of or include at least one of titanium nitride (TiN), tantalum nitride (TaN), titanium oxynitride (TiON), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), tungsten carbon nitride (WCN), or molybdenum nitride (MoN). 
     The second work function metal of the second metal pattern MP 2  may be an n-type work function metal having a relatively low work function. The second metal pattern MP 2  may be formed of or include at least one of metal carbides. The second metal pattern MP 2  may be formed of or include at least one of metal carbides that are doped with silicon and/or aluminum and contain silicon and/or aluminum. As an example, the second metal pattern MP 2  may be formed of or include aluminum-doped titanium carbide (TiAlC), aluminum-doped tantalum carbide (TaAlC), aluminum-doped vanadium carbide (VAlC), silicon-doped titanium carbide (TiSiC), or silicon-doped tantalum carbide (TaSiC). As another example, the second metal pattern MP 2  may be formed of or include titanium carbide (TiAlSiC), which is doped with aluminum and silicon, or tantalum carbide (TaAlSiC), which is doped with aluminum and silicon. As other example, the second metal pattern MP 2  may be formed of or include aluminum-doped titanium (TiAl). As still other example, the second metal pattern MP 2  may be formed of or include a metal nitride doped with silicon and/or aluminum (e.g., aluminum-doped titanium nitride (TiAlN)). 
     A work function of the second metal pattern MP 2  may be controlled by adjusting a doping concentration of dopants or impurities (e.g., silicon or aluminum) contained in the second metal pattern MP 2 . As an example, the concentration of the impurity (e.g., silicon or aluminum) in the second metal pattern MP 2  may range from 0.1 at % to 25 at %. 
     Each of the first, second and third portions PO 1 , PO 2 , and PO 3  of the lower gate electrode LGE may be composed of the second metal pattern MP 2  and the first metal pattern MP 1  enclosing the second metal pattern MP 2 . In an embodiment, a thickness of the second metal pattern MP 2  may be larger than a thickness of the first metal pattern MP 1 . 
     The lower gate electrode LGE may further include a sixth metal pattern MP 6 , which is provided as a remaining portion of the lower gate electrode LGE, in addition to the first, second and third portions PO 1 , PO 2 , and PO 3  and the first and second metal patterns MP 1  and MP 2  (e.g., see  FIG.  4 D ). The sixth metal pattern MP 6  may have a lower resistance than the first and second metal patterns MP 1  and MP 2 . As an example, the sixth metal pattern MP 6  may be formed of or include at least one of low resistance metallic materials (e.g., tungsten (W), ruthenium (Ru), aluminum (Al), titanium (Ti), and tantalum (Ta)). 
     Referring to  FIG.  4 D , a top surface of the sixth metal pattern MP 6  of the gate electrode GE may be in contact with a bottom surface of the upper gate electrode UGE. The top surface of the sixth metal pattern MP 6  may be located at a level between the top and bottom surfaces of the dummy channel pattern DSP. 
     The upper gate electrode UGE of the gate electrode GE may include a third metal pattern MP 3  on the third and fourth semiconductor patterns SP 3  and SP 4 . The third metal pattern MP 3  may be provided to enclose the third and fourth semiconductor patterns SP 3  and SP 4 . The upper gate electrode UGE may further include a fourth metal pattern MP 4  and a fifth metal pattern MP 5  on the third metal pattern MP 3 . 
     The third metal pattern MP 3  may include the first work function metal, and the fourth metal pattern MP 4  may include the second work function metal. By adjusting compositions of the first and second work function metals, the transistor of the second active region AR 2  may be formed to have a desired threshold voltage. 
     The first work function metal of the third metal pattern MP 3  may be a p-type work function metal having a relatively high work function, similar to the first metal pattern MP 1  described above. The third metal pattern MP 3  may be formed of or include at least one of metal nitrides. The third metal pattern MP 3  may be formed of or include a metal nitride, which is the same as or different from that in the first metal pattern MP 1 . A thickness, in the third direction D 3 , of the third metal pattern MP 3  in the fourth and fifth portions PO 4  and PO 5  may be larger than a thickness, in the third direction D 3 , of the first metal pattern MP 1  in the first to third portions PO 1 , PO 2 , and PO 3 . 
     The second work function metal of the fourth metal pattern MP 4  may be a n-type work function metal having a relatively low work function, similar to the second metal pattern MP 2  described above. The fourth metal pattern MP 4  may be formed of or include at least one of metal carbides that are doped with silicon and/or aluminum and contain silicon and/or aluminum. The fourth metal pattern MP 4  may be formed of or include a material, which is the same as or different from the second metal pattern MP 2 . A thickness of the fourth metal pattern MP 4  may be different from a thickness of the second metal pattern MP 2 . For example, the thickness of the fourth metal pattern MP 4  may be larger than the thickness of the second metal pattern MP 2 . 
     The fourth and fifth portions PO 4  and PO 5  of the upper gate electrode UGE may be composed of the third metal pattern MP 3 . The sixth portion PO 6  of the upper gate electrode UGE may include the third metal pattern MP 3 , the fourth metal pattern MP 4 , and the fifth metal pattern MP 5 , which are sequentially stacked. 
     In an embodiment, the fifth metal pattern MP 5  may include the first work function metal. For example, the fifth metal pattern MP 5  may be formed of or include the same metal nitride material as the third metal pattern MP 3 . In another embodiment, the fifth metal pattern MP 5  may be formed of or include at least one of low resistance metallic materials. For example, the fifth metal pattern MP 5  may be formed of or include the same metallic material as the sixth metal pattern MP 6 . 
     Referring back to  FIG.  3   , the logic cell LC according to the present embodiment may include a first cell boundary CB 1 , which is defined to extend in the second direction D 2 . A second cell boundary CB 2 , which is extended in the second direction D 2 , may be defined at an opposite side of the first cell boundary CB 1 . Gate cutting patterns CT may be disposed on the first and second cell boundaries CB 1  and CB 2 . When viewed in a plan view, the gate cutting patterns CT may be arranged with the first pitch along the first cell boundary CB 1 . The gate cutting patterns CT may be arranged with the first pitch along the second cell boundary CB 2 . When viewed in a plan view, the gate cutting patterns CT on the first and second cell boundaries CB 1  and CB 2  may be disposed to be overlapped with gate electrodes GE, respectively. 
     The gate cutting pattern CT may be provided to penetrate the gate electrode GE 1  or GE 2 . The gate electrode GE 1  or GE 2  may be separated from another gate electrode, which is adjacent thereto in the first direction D 1 , by the gate cutting pattern CT. For example, referring to  FIG.  4 D , a pair of the gate cutting patterns CT may be respectively provided at opposite end portions of the gate electrode GE. The gate cutting patterns CT may be formed of or include at least one of insulating materials (e.g., silicon oxide, silicon nitride, or combinations thereof). 
     In the present embodiment, a third cell boundary CB 3 , which is extended in the first direction D 1 , may be defined in the logic cell LC. A fourth cell boundary CB 4 , which is extended in the first direction D 1 , may be defined at an opposite side of the third cell boundary CB 3 . Cell division structures DB may be disposed on the third and fourth cell boundaries CB 3  and CB 4 , respectively. The cell division structures DB may be extended in the first direction D 1  to separate the logic cell LC of  FIG.  3    from another logic cell adjacent thereto. 
     A gate contact GC may be provided to penetrate a third interlayer insulating layer  130  and the gate capping pattern GP and to be electrically connected to the gate electrode GE. In detail, the gate contact GC may be coupled to (e.g., may contact) the upper gate electrode UGE of the gate electrode GE. The gate contact GC may have a pillar shape extending in the third direction D 3 . The gate contact GC may be formed of or include at least one of metallic materials (e.g., copper (Cu), aluminum (Al), ruthenium (Ru), cobalt (Co), tungsten (W), and molybdenum (Mo)). 
     A first active contact AC 1  may be provided on at least one of the lower source/drain patterns SD 1  (e.g., see  FIG.  4 C ). The first active contact AC 1  may include a vertical extended portion VEP and a horizontal extended portion HEP. The vertical extended portion VEP may be provided to penetrate the first to third interlayer insulating layers  110 ,  120 , and  130  and may have a vertically-extending pillar shape. The vertical extended portion VEP of the first active contact AC 1  may be horizontally offset from the lower and upper source/drain patterns SD 1  and SD 2  which are stacked. The horizontal extended portion HEP may be provided in the bottom tier of the FEOL layer. The horizontal extended portion HEP may be extended from the vertical extended portion VEP in the first direction D 1  and may be coupled to (e.g., may contact) the lower source/drain pattern SD 1 . 
     The horizontal extended portion HEP and the vertical extended portion VEP may be connected to each other to form each of the first active contacts AC 1 . The first active contact AC 1  may be formed of or include at least one of doped semiconductor materials and/or metallic materials. In an embodiment, the metallic materials may include copper (Cu), aluminum (Al), ruthenium (Ru), cobalt (Co), tungsten (W), and molybdenum (Mo). 
     The second active contact AC 2  may be provided on at least one of the upper source/drain patterns SD 2  (e.g., see  FIG.  4 C ). The second active contact AC 2  may be disposed spaced apart from the first active contact AC 1  in the first direction D 1 . The second active contact AC 2  may be vertically overlapped with the upper source/drain pattern SD 2 . As used herein, “an element A vertically overlapping an element B” (or similar language) means that at least one vertical line intersecting both the elements A and B exists. 
     The second active contact AC 2  may be provided in the top tier of the FEOL layer. The second active contact AC 2  may have a vertically-extending pillar shape. The second active contact AC 2  may be directly coupled to the upper source/drain pattern SD 2 . In an embodiment, the second active contact AC 2  may be formed of or include the same material as the first active contact AC 1 . 
     A fourth interlayer insulating layer  140  may be provided on the third interlayer insulating layer  130 . A first metal layer M 1  may be provided in the fourth interlayer insulating layer  140 . The first metal layer M 1  may include the first power line POR 1 , the second power line POR 2 , and first to fourth interconnection lines MI 1  to MI 4 . 
     When viewed in a plan view, the first power line POR 1  may be provided on the first cell boundary CB 1 , and the second power line POR 2  may be provided on the second cell boundary CB 2 . The gate cutting patterns CT may be vertically overlapped with the first and second power lines POR 1  and POR 2 . A drain voltage VDD may be applied to one of the first and second power lines POR 1  and POR 2 , and a source voltage VSS may be applied to the other of the first and second power lines POR 1  and POR 2 . In an embodiment, the source voltage VSS may be applied to the first power line POR 1 , and the drain voltage VDD may be applied to the second power line POR 2 . 
     The first to fourth interconnection lines MI 1  to MI 4  may be disposed between the first and second power lines POR 1  and POR 2 . The first to fourth interconnection lines MI 1  to MI 4  may be line- or bar-shaped patterns extended in the second direction D 2 . The first and second power lines POR 1  and POR 2  and the first to fourth interconnection lines MI 1  to MI 4  may be formed of or include at least one metallic material that is selected from the group consisting of copper (Cu), aluminum (Al), ruthenium (Ru), cobalt (Co), tungsten (W), and molybdenum (Mo). As used herein, “an element A extends in a direction X” (or similar language) may mean that the element A extends longitudinally in the direction X, 
     The first metal layer M 1  may further include vias VI, which are provided in a lower portion of the fourth interlayer insulating layer  140 . One of the vias VI may be used to connect the active contact AC 1  or AC 2  to the power line POR 1  or POR 2 . One of the vias VI may be used to connect the first and second active contacts AC 1  and AC 2 , which are adjacent to each other (e.g., see  FIG.  4 C ). One of the vias VI may be used to connect the gate contact GC to at least one of the interconnection lines MI 1  to MI 4 . 
     Additional metal layers (e.g., M 2 , M 3 , M 4 , and so forth) may be stacked on the first metal layer M 1 . The first metal layer M 1  and the additional metal layers (e.g., M 2 , M 3 , M 4 , and so forth) thereon may constitute a back-end-of-line (BEOL) layer of the semiconductor device. The additional metal layers (e.g., M 2 , M 3 , M 4 , and so forth) on the first metal layer M 1  may include routing lines, which are used to connect the logic cells to each other. 
       FIGS.  5  to  7    are enlarged sectional views, each of which illustrates a portion ‘M’ of  FIG.  4 A , according to an embodiment of the inventive concept. In the following description, an element previously described with reference to  FIGS.  3  and  4 A to  4 D  may be identified by the same reference number without repeating an overlapping description thereof, for the sake of brevity. 
     Referring to  FIG.  5   , each of the first to fourth semiconductor patterns SP 1  to SP 4  may have a first thickness TK 1  in the third direction D 3 . The dummy channel pattern DSP may be formed of or include at least one of silicon-based insulating materials. The dummy channel pattern DSP may have a second thickness TK 2  in the third direction D 3 . The second thickness TK 2  may be equal to or larger than the first thickness TK 1 . For example, the second thickness TK 2  may be larger than the first thickness TK 1 . 
     The fourth portion PO 4  of the upper gate electrode UGE may have a third thickness TK 3  in the third direction D 3 . The fifth portion PO 5  of the upper gate electrode UGE may have a fourth thickness TK 4  in the third direction D 3 . The third thickness TK 3  may be equal to or larger than the fourth thickness TK 4 . For example, the third thickness TK 3  may be larger than the fourth thickness TK 4 . 
     Since the third thickness TK 3  of the fourth portion PO 4  has a relatively large thickness, a distance between the third semiconductor pattern SP 3  and the dummy channel pattern DSP may be increased. Thus, it may be possible to stably form the fourth portion PO 4  during the process of forming the upper gate electrode UGE, and thereby to stably realize the lower and upper gate electrodes LGE and UGE, which have different structures in each gate electrode GE. As a result, it may be possible to improve reliability of the three-dimensional device according to an embodiment of the inventive concept. 
     Referring to  FIG.  6   , the dummy channel pattern DSP may be formed of or include at least one of semiconductor materials (e.g., silicon (Si), germanium (Ge), or silicon germanium (SiGe)). In an embodiment, the dummy channel pattern DSP may contain the same element (e.g., silicon (Si)) as the first to fourth semiconductor patterns SP 1  to SP 4 . For example, a content of silicon (Si) in the dummy channel pattern DSP may be higher than 98 at %. 
     Referring to  FIG.  7   , the dummy channel pattern DSP may include a first dummy channel pattern DSP 1  and a second dummy channel pattern DSP 2 . The second dummy channel pattern DSP 2  may be provided on the first dummy channel pattern DSP 1  and may be vertically spaced apart from the first dummy channel pattern DSP 1 . Opposite side surface of each of the first and second dummy channel patterns DSP 1  and DSP 2  may be covered with a pair of the liner layers LIN. 
     The first and second dummy channel patterns DSP 1  and DSP 2  may be formed of or include the same material as each other. In an embodiment, the first and second dummy channel patterns DSP 1  and DSP 2  may be formed of or include a semiconductor material. In another embodiment, the first and second dummy channel patterns DSP 1  and DSP 2  may be formed of or include a silicon-containing insulating material. 
     The upper gate electrode UGE may include a seventh portion PO 7  interposed between the first and second dummy channel patterns DSP 1  and DSP 2 . The seventh portion PO 7  may be composed of the third metal pattern MP 3 . 
       FIGS.  8 A to  17 B  are sectional views illustrating a method of fabricating a semiconductor device, according to an embodiment of the inventive concept. In detail,  FIGS.  8 A,  9 A,  10 A,  11 A,  12 A,  13 A,  14 A,  15 A,  16 A, and  17 A  are sectional views corresponding to a line A-A′ of  FIG.  3   .  FIGS.  10 B,  11 B,  12 B, and  13 B  are sectional views corresponding to a line C-C′ of  FIG.  5   .  FIGS.  8 B,  9 B,  14 B,  15 B,  16 B, and  17 B  are sectional views corresponding to a line D-D′ of  FIG.  3   . 
     Referring to  FIGS.  8 A and  8 B , first sacrificial layers SAL 1  and first active layers ACL 1  may be alternately stacked on the substrate  100 . The first sacrificial layers SAL 1  may be formed of or include one of silicon (Si), germanium (Ge), and silicon germanium (SiGe), and the first active layers ACL 1  may be formed of or include another of silicon (Si), germanium (Ge), and silicon germanium (SiGe). For example, the first sacrificial layers SAL 1  may be formed of or include silicon germanium (SiGe), and the first active layers ACL 1  may be formed of or include silicon (Si). For example, a concentration of germanium (Ge) in each of the first sacrificial layers SAL 1  may range from about 10 at % to about 30 at %. 
     A second sacrificial layer SAL 2  may be formed on the uppermost one of the first active layers ACL 1 . In an embodiment, a thickness of the second sacrificial layer SAL 2  may be substantially equal to a thickness of the first sacrificial layer SAL 1 . In some embodiments, the thickness of the second sacrificial layer SAL 2  may be larger than a thickness of each of the first active layer ACL 1  and the first sacrificial layer SAL 1 . The second sacrificial layer SAL 2  may be formed of or include silicon (Si) or silicon germanium (SiGe). In the case where the second sacrificial layer SAL 2  includes silicon germanium (SiGe), a concentration of germanium (Ge) in the second sacrificial layer SAL 2  may be higher than that in the first sacrificial layer SAL 1 . For example, the germanium concentration of the second sacrificial layer SAL 2  may range from about 40 at % to about 90 at %. 
     Third sacrificial layers SAL 3  and second active layers ACL 2  may be alternately stacked on the second sacrificial layer SAL 2 . Each of the third sacrificial layers SAL 3  may be formed of or include the same material as the first sacrificial layer SAL 1 , and each of the second active layers ACL 2  may be formed of or include the same material as the first active layer ACL 1 . The second sacrificial layer SAL 2  may be interposed between the first sacrificial layer SAL 1  and the third sacrificial layer SAL 3 . 
     A stacking pattern STP may be formed by patterning the stack of the first to third sacrificial layers SAL 1 , SAL 2 , and SAL 3  and the first and second active layers ACL 1  and ACL 2 . The formation of the stacking pattern STP may include forming a hard mask pattern on the uppermost one of the second active layers ACL 2  and etching the layers (e.g., SAL 1 , SAL 2 , SAL 3 , ACL 1 , and ACL 2 ), which are stacked on the substrate  100 , using the hard mask pattern as an etch mask. During the formation of the stacking pattern STP, an upper portion of the substrate  100  may be patterned to form the trench TR defining the active pattern AP. The stacking pattern STP may be a bar-shaped pattern extended in the second direction D 2 . 
     The stacking pattern STP may include a lower stacking pattern STP 1  on the active pattern AP, an upper stacking pattern STP 2  on the lower stacking pattern STP 1 , and the second sacrificial layer SAL 2  between the lower and upper stacking patterns STP 1  and STP 2 . The lower stacking pattern STP 1  may include the first sacrificial layers SAL 1  and the first active layers ACL 1 , which are alternately stacked. The upper stacking pattern STP 2  may include the third sacrificial layers SAL 3  and the second active layers ACL 2 , which are alternately stacked. 
     The device isolation layer ST may be formed on the substrate  100  to fill the trench TR. In detail, an insulating layer may be formed on the substrate  100  to cover the active pattern AP and the stacking pattern STP. The device isolation layer ST may be formed by recessing the insulating layer until the stacking pattern STP is exposed. 
     Referring to  FIGS.  9 A and  9 B , sacrificial patterns PP may be formed to cross the stacking pattern STP. Each of the sacrificial patterns PP may be formed to have a line shape extending in the first direction D 1 . The sacrificial patterns PP may be arranged in the second direction D 2  with a first pitch. 
     In detail, the formation of the sacrificial patterns PP may include forming a sacrificial layer on the substrate  100 , forming hard mask patterns MP on the sacrificial layer, and patterning the sacrificial layer using the hard mask patterns MP as an etch mask. The sacrificial layer may be formed of or include amorphous silicon and/or polysilicon. As used herein the term “and/or” includes any and all combinations of one or more of the associated listed items. 
     A spacer layer GSL may be conformally formed on the substrate  100 . The spacer layer GSL may cover the sacrificial patterns PP and the hard mask patterns MP. For example, the spacer layer GSL may be formed of or include at least one of SiCN, SiCON, or SiN. 
     Referring to  FIGS.  10 A and  10 B , a first etching process using the spacer layer GSL and the hard mask patterns MP as an etch mask may be performed on the stacking pattern STP. As a result of the first etching process, a first recess RS 1  may be formed in the stacking pattern STP between the sacrificial patterns PP. The first recess RS 1  may be formed between a pair of the sacrificial patterns PP. 
     The first etching process may be an anisotropic etching process. As a result of the first etching process, the gate spacer GS covering a side surface of the sacrificial pattern PP may be formed from the spacer layer GSL. The first etching process may be performed to expose the uppermost one of the first sacrificial layers SAL 1  of the lower stacking pattern STP 1 . In other words, the first recess RS 1  may be formed to expose the lower stacking pattern STP 1  (e.g., see  FIG.  10 B ). 
     The liner layer LIN may be conformally formed on the substrate  100 . The liner layer LIN may cover the gate spacers GS and the hard mask patterns MP. The liner layer LIN may cover an inner surface of the first recess RS 1 . The liner layer LIN may cover the exposed portions of the lower stacking pattern STP 1 . In an embodiment, the liner layer LIN may be formed of or include, for example, silicon nitride. 
     Referring to  FIGS.  11 A and  11 B , a second etching process using the liner layer LIN, the gate spacers GS, and the hard mask patterns MP as an etch mask may be performed on the stacking pattern STP. As a result of the second etching process, the lower stacking pattern STP 1  between the sacrificial patterns PP may be removed to form a second recess RS 2 . The second recess RS 2  may be further extended from the first recess RS 1  in a downward direction. 
     The second etching process may be an anisotropic etching process. The second etching process may be performed to expose the top surface of the active pattern AP. In other words, the second recess RS 2  may be formed to expose the top surface of the active pattern AP. 
     Referring to  FIGS.  12 A and  12 B , the lower source/drain patterns SD 1  may be formed in the second recesses RS 2 , respectively. In detail, the lower source/drain pattern SD 1  may be formed by performing a first SEG process using an inner surface of the second recess RS 2  as a seed layer. The lower source/drain pattern SD 1  may be grown using the first active layers ACL 1  and the substrate  100 , which are exposed through the second recess RS 2 , as a seed layer. In an embodiment, the first SEG process may include a chemical vapor deposition (CVD) process and/or a molecular beam epitaxy (MBE) process. 
     During the first SEG process, impurities or dopants may be injected into the lower source/drain pattern SD 1  in an in-situ manner. In some embodiments, the impurities may be injected into the lower source/drain pattern SD 1  by an ion-implantation process performed after the formation of the lower source/drain pattern SD 1 . The lower source/drain pattern SD 1  may be doped to have a first conductivity type (e.g., n-type). 
     The first active layers ACL 1 , which are interposed between a pair of the lower source/drain patterns SD 1 , may constitute the lower channel pattern CH 1 . In other words, the first and second semiconductor patterns SP 1  and SP 2  of the lower channel pattern CH 1  may be formed from the first active layers ACL 1 . The lower channel patterns CH 1  and the lower source/drain patterns SD 1  may constitute the first active region AR 1 , which is the bottom tier of the three-dimensional device. 
     The inner surface of the first recess RS 1  may be covered with the liner layer LIN. That is, due to the liner layer LIN, the second active layers ACL 2  of the upper stacking pattern STP 2  may not be exposed to the outside during the first SEG process. Thus, it may be possible to hinder or prevent growth of an additional semiconductor layer in the first recess RS 1 , during the first SEG process. 
     Referring to  FIGS.  13 A and  13 B , the first interlayer insulating layer  110  may be formed to cover the lower source/drain patterns SD 1 . A top surface of the first interlayer insulating layer  110  may be recessed to a level lower than a bottom surface of the lowermost one of the second active layers ACL 2 . 
     The liner layer LIN exposed by the first recess RS 1  may be partially removed. A portion of the liner layer LIN, which is covered with the first interlayer insulating layer  110 , may be left to cover a portion of a side surface of the second sacrificial layer SAL 2 . As a result of the partial removal of the liner layer LIN, the second active layers ACL 2  may be exposed to the outside through the first recess RS 1 . 
     The upper source/drain patterns SD 2  may be formed in the first recesses RS 1 , respectively. In detail, a second SEG process, in which the inner surface of the first recess RS 1  is used as a seed layer, may be performed to form the upper source/drain pattern SD 2 . The upper source/drain pattern SD 2  may be grown using the second active layers ACL 2 , which are exposed through the first recess RS 1 , as a seed layer. The upper source/drain patterns SD 2  may be doped to have a second conductivity type (e.g., p-type) different from the first conductivity type. 
     The second active layers ACL 2 , which are interposed between a pair of the upper source/drain patterns SD 2 , may constitute the upper channel pattern CH 2 . That is, the third and fourth semiconductor patterns SP 3  and SP 4  of the upper channel pattern CH 2  may be formed from the second active layers ACL 2 . The upper channel patterns CH 2  and the upper source/drain patterns SD 2  may constitute the second active region AR 2 , which is the top tier of the three-dimensional device. 
     Referring to  FIGS.  14 A and  14 B , the second interlayer insulating layer  120  may be formed to cover the hard mask patterns MP, the gate spacers GS, and the upper source/drain patterns SD 2 . As an example, the second interlayer insulating layer  120  may include a silicon oxide layer. 
     The second interlayer insulating layer  120  may be planarized to expose top surfaces of the sacrificial patterns PP. The planarization of the third interlayer insulating layer  130  may be performed using an etch-back process or a chemical mechanical polishing (CMP) process. In an embodiment, the planarization process may be performed to remove all of the hard mask patterns MP. In this case, a top surface of the third interlayer insulating layer  130  may be coplanar with the top surfaces of the sacrificial patterns PP and the top surfaces of the gate spacers GS. 
     The gate cutting pattern CT may be formed to penetrate the sacrificial pattern PP. The gate cutting patterns CT may be formed on the first and second cell boundaries CB 1  and CB 2  of the logic cell. The gate cutting patterns CT may be formed of or include, for example, silicon oxide and/or silicon nitride. 
     The exposed sacrificial patterns PP may be selectively removed. As a result of the removal of the sacrificial patterns PP, an outer region ORG may be formed to expose the lower and upper channel patterns CH 1  and CH 2  (e.g., see  FIG.  14 B ). The removal of the sacrificial patterns PP may include, for example, a wet etching process, which is performed using etching solution capable of selectively etching polysilicon. 
     The second sacrificial layer SAL 2 , which is exposed through the outer region ORG, may be selectively removed. In an embodiment, a concentration of germanium (Ge) in the second sacrificial layer SAL 2  may be much higher than a concentration of germanium (Ge) in other layers SAL 1 , SAL 3 , ACL 1 , and ACL 2 , and this may make it possible to selectively etch only the second sacrificial layer SAL 2 . As a result of the selective removal of the second sacrificial layer SAL 2 , an empty space EMT may be formed between the lower stacking pattern STP 1  and the upper stacking pattern STP 2 . 
     In some embodiments, the second sacrificial layer SAL 2  may be a semiconductor layer that is made of or contains only silicon (Si). In this case, the second sacrificial layer SAL 2  may not be removed and may be left along with the first and second active layers ACL 1  and ACL 2 . The second sacrificial layer SAL 2  may constitute the dummy channel pattern DSP of  FIG.  6   . 
     Referring to  FIGS.  15 A and  15 B , the dummy channel pattern DSP may be formed by filling the empty space EMT with a silicon-based insulating material (e.g., silicon oxide or silicon nitride). For example, the second sacrificial layer SAL 2 , which is exposed through the outer region ORG, may be replaced with the dummy channel pattern DSP. 
     In some embodiments, an insulating material may be formed in the outer region ORG to cover the stacking pattern STP. The insulating material may be deposited to completely fill the empty space EMT. Thereafter, a wet etching process on the insulating material may be performed to expose the stacking pattern STP. The dummy channel pattern DSP may be a portion of the insulating material, which is left in the empty space EMT. 
     Referring to  FIGS.  16 A and  16 B , the first and third sacrificial layers SAL 1  and SAL 3 , which are exposed through the outer region ORG, may be selectively removed to form first to fifth inner regions IRG 1  to IRG 5 , respectively (e.g., see  FIG.  16 B ). In detail, an etching process of selectively etching the first and third sacrificial layers SAL 1  and SAL 3  may be performed to leave the first to fourth semiconductor patterns SP 1  to SP 4  and the dummy channel pattern DSP and to remove only the first and third sacrificial layers SAL 1  and SAL 3 . An etch recipe for the etching process may be chosen to etch a layer (e.g., a silicon germanium layer) having a relatively high germanium concentration at a high etch rate. For example, in the etching process, a silicon germanium layer, in which germanium concentration is higher than 10 at %, may be etched at a high etch rate. 
     Since the first and third sacrificial layers SAL 1  and SAL 3  are selectively removed, the first and second semiconductor patterns SP 1  and SP 2  may be left in the first active region AR 1 , and the third and fourth semiconductor patterns SP 3  and SP 4  may be left in the second active region AR 2 . The dummy channel pattern DSP may be left between the second semiconductor pattern SP 2  and the third semiconductor pattern SP 3 . 
     An empty space between the active pattern AP and the first semiconductor pattern SP 1  may be defined as the first inner region IRG 1 , an empty space between the first semiconductor pattern SP 1  and the second semiconductor pattern SP 2  may be defined as the second inner region IRG 2 , and an empty space between the second semiconductor pattern SP 2  and the dummy channel pattern DSP may be defined as the third inner region IRG 3 . An empty space between the dummy channel pattern DSP and the third semiconductor pattern SP 3  may be defined as the fourth inner region IRG 4 , and an empty space between the third semiconductor pattern SP 3  and the fourth semiconductor pattern SP 4  may be defined as the fifth inner region IRG 5 . 
     Referring to  FIGS.  17 A and  17 B , the gate insulating layer UGI or LGI may be conformally formed on at least one of the exposed surfaces of the first to fourth semiconductor patterns SP 1  to SP 4 . In an embodiment, the lower gate insulating layer LGI may be formed on the first and second semiconductor patterns SP 1  and SP 2 , and the upper gate insulating layer UGI may be formed on the third and fourth semiconductor patterns SP 3  and SP 4 . 
     The lower gate electrode LGE may be formed on the lower gate insulating layer LGI. The formation of the lower gate electrode LGE may include forming the first to third portions PO 1  to PO 3  in the first to third inner regions IRG 1 , IRG 2 , and IRG 3 , respectively. 
     The upper gate electrode UGE may be formed on the upper gate insulating layer UGI. The formation of the upper gate electrode UGE may include forming the fourth and fifth portions PO 4  and PO 5  in the fourth and fifth inner regions IRG 4  and IRG 5 , respectively, and forming the sixth portion PO 6  in the outer region ORG. The lower gate electrode LGE and the upper gate electrode UGE may be connected to each other to form a single gate electrode GE. 
     The gate electrode GE may be recessed to have a reduced height. The gate capping pattern GP may be formed on the recessed gate electrode GE. A planarization process may be performed on the gate capping pattern GP such that a top surface of the gate capping pattern GP is coplanar with a top surface of the second interlayer insulating layer  120 . 
     Referring back to  FIGS.  3  and  4 A to  4 D , the third interlayer insulating layer  130  may be formed on the second interlayer insulating layer  120 . The first active contact AC 1  may be formed to penetrate the first to third interlayer insulating layers  110 ,  120 , and  130  and to be coupled to the lower source/drain pattern SD 1 . The second active contact AC 2  may be formed to penetrate the second and third interlayer insulating layers  120  and  130  and to be coupled to the upper source/drain pattern SD 2 . The gate contact GC may be formed to penetrate the third interlayer insulating layer  130  and the gate capping pattern GP and to be coupled to the gate electrode GE. 
     The fourth interlayer insulating layer  140  may be formed on the third interlayer insulating layer  130 . The first metal layer M 1  may be formed in the fourth interlayer insulating layer  140 . The formation of the first metal layer M 1  may include forming the first and second power lines POR 1  and POR 2  and the first to fourth interconnection lines MI 1  to MI 4  in an upper portion of the fourth interlayer insulating layer  140 . 
     The via VI may be formed below each of the first and second power lines POR 1  and POR 2  and the first to fourth interconnection lines MI 1  to MI 4 . The first and second active contacts AC 1  and AC 2  and gate contacts GC may be electrically connected to the first metal layer M 1  through the vias VI. 
     As an example, the vias VI may be formed in advance before forming the first and second power lines POR 1  and POR 2  and the first to fourth interconnection lines MI 1  to MI 4 . In some embodiments, the vias VI may be formed through a dual damascene process, and in this case, the vias VI may be formed together when the first and second power lines POR 1  and POR 2  and the first to fourth interconnection lines MI 1  to MI 4  are formed. 
     Although not shown, a plurality of additional metal layers (e.g., M 2 , M 3 , M 4 , and so forth) may be further formed on the first metal layer M 1 . The first metal layer M 1  and the additional metal layers (e.g., M 2 , M 3 , M 4 , and so forth) may constitute a BEOL layer of the semiconductor device. 
       FIGS.  18  to  23    are sectional views, which are respectively taken along a line D-D′ of  FIG.  3    to illustrate a method of forming a gate electrode according to an embodiment of the inventive concept. 
     Referring to  FIG.  18   , the gate insulating layer UGI or LGI may be conformally formed on the structure of  FIG.  16 B . The gate insulating layer UGI or LGI may include the lower gate insulating layer LGI, which is provided on the first and second semiconductor patterns SP 1  and SP 2  and the dummy channel pattern DSP, and the upper gate insulating layer UGI, which is provided on the third and fourth semiconductor patterns SP 3  and SP 4 . 
     The formation of the lower and upper gate insulating layers LGI and UGI may include forming a silicon oxide layer on surfaces of the first to fourth semiconductor patterns SP 1  to SP 4  and forming a high-k dielectric layer on the silicon oxide layer. 
     A dipole-containing layer DPL may be conformally formed on the lower and upper gate insulating layers LGI and UGI. The dipole-containing layer DPL may contain a dipole element. The dipole element may include lanthanum (La), aluminum (Al), or a combination thereof. For example, the dipole-containing layer DPL may include at least one of a lanthanum oxide layer, an aluminum oxide layer, or combinations thereof. 
     Referring to  FIG.  19   , a mask layer MA may be formed to cover the lower gate insulating layer LGI and to expose the upper gate insulating layer UGI. In detail, the mask layer MA may be formed to cover the lower channel pattern CH 1 , the dummy channel pattern DSP, and the upper channel pattern CH 2 . The mask layer MA may fill the first to fifth inner regions IRG 1  to IRG 5 . In an embodiment, the mask layer MA may be formed of or include an organic polymer material. 
     The mask layer MA may be selectively recessed such that a top surface of the mask layer MA is located at a level similar to a top surface of the dummy channel pattern DSP. As a result of the recessing of the mask layer MA, the fourth and fifth inner regions IRG 4  and IRG 5  may be exposed to the outside again. In an embodiment, as a result of the recessing of the mask layer MA, the upper gate insulating layer UGI may be exposed to the outside. 
     The dipole-containing layer DPL on the upper gate insulating layer UGI may be selectively removed using the mask layer MA as an etch mask. Thus, the dipole-containing layer DPL may be locally left on only the lower gate insulating layer LGI, but not on the upper gate insulating layer UGI. 
     Next, the mask layer MA may be removed, and then, a thermal treatment process performed on the dipole-containing layer DPL to diffuse the dipole element in the dipole-containing layer DPL into the lower gate insulating layer LGI. Accordingly, a dipole-interface may be formed between the high-k dielectric layer and the silicon oxide layer of the lower gate insulating layer LGI. The dipole element, which is diffused into the lower gate insulating layer LGI, may be used to adjust an effective work function of the lower gate electrode LGE to be formed in a subsequent step. 
     During the thermal treatment process, the dipole-containing layer DPL may be removed, while emitting the dipole element. In an embodiment, the dipole-containing layer DPL may be formed to have an exceedingly small thickness (e.g., less than 1 nm), and in this case, the dipole-containing layer DPL may be easily removed. 
     According to an embodiment of the inventive concept, by using the dummy channel pattern DSP, it may be possible to completely remove the mask layer MA from the fourth and fifth inner regions IRG 4  and IRG 5 . Since the dummy channel pattern DSP is located on the lower channel pattern CH 1 , the dummy channel pattern DSP may serve as a buffer protecting the lower channel pattern CH 1 . Thus, the mask layer MA may be completely etched such that the mask layer MA is not left in the fourth and fifth inner regions IRG 4  and IRG 5 . As a result, the dipole element may be selectively diffused into only the lower gate insulating layer LGI, not into the upper gate insulating layer UGI. 
     Furthermore, the dummy channel pattern DSP according to an embodiment of the inventive concept may serve as a boundary of the lower gate electrode LGE and the upper gate electrode UGE, and thus, it may be possible to compose the lower gate electrode LGE and the upper gate electrode UGE using different layers or materials. As a result, according to an embodiment of the inventive concept, it may be possible to realize a three-dimensional device, in which NMOS- and PMOS-FETs are vertically stacked, with high reliability. 
     Referring to  FIG.  20   , the first metal pattern MP 1  may be conformally formed on the lower and upper gate insulating layers LGI and UGI. The first metal pattern MP 1  may be provided to enclose each of the first to fourth semiconductor patterns SP 1  to SP 4 . 
     The first metal pattern MP 1  may include a first work function metal (e.g., p-type work function metal). The formation of the first metal pattern MP 1  may include conformally depositing a metal nitride layer on the lower and upper gate insulating layers LGI and UGI. For example, the first metal pattern MP 1  may be formed of or include at least one of titanium nitride (TiN), tantalum nitride (TaN), titanium oxynitride (TiON), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), tungsten carbon nitride (WCN), or molybdenum nitride (MoN). 
     The second metal pattern MP 2  may be formed on the first metal pattern MP 1 . The second metal pattern MP 2  may be formed to fully fill remaining regions of the first to fifth inner regions IRG 1  to IRG 5 . The second metal pattern MP 2  may also be formed in the outer region ORG. 
     The second metal pattern MP 2  may include a second work function metal (e.g., n-type work function metal). The formation of the second metal pattern MP 2  may include depositing at least one of metal carbides, which are doped with silicon and/or aluminum and contain silicon and/or aluminum, on the first metal pattern MP 1 . For example, the second metal pattern MP 2  may be formed of or include at least one of aluminum-doped titanium carbide (TiAlC), aluminum-doped tantalum carbide (TaAlC), aluminum-doped vanadium carbide (VAlC), silicon-doped titanium carbide (TiSiC), or silicon-doped tantalum carbide (TaSiC). 
     Referring to  FIG.  21   , an etching process may be performed on the second metal pattern MP 2  to remove the second metal pattern MP 2  from the outer region ORG. The etching process may include a wet etching process of selectively removing only the second metal pattern MP 2 . A portion of the second metal pattern MP 2  in the outer region ORG may be removed, and other portions of the second metal pattern MP 2  in the first to fifth inner regions IRG 1  to IRG 5  may remain. 
     Referring to  FIG.  22   , a first work function metal layer may be deposited to conformally cover the first metal pattern MP 1 , and thus, the first metal pattern MP 1  may have an increased thickness. The sixth metal pattern MP 6  may be formed in a lower portion of the outer region ORG. In detail, the sixth metal pattern MP 6  may be formed on the first and second metal patterns MP 1  and MP 2  to fill the outer region ORG. Next, the sixth metal pattern MP 6  may be recessed to have a top surface located at a first level LV 1 . For example, the first level LV 1  may be positioned between top and bottom surfaces of the dummy channel pattern DSP. The sixth metal pattern MP 6  may be formed of or include at least one of low-resistance metals (e.g., tungsten (W), ruthenium (Ru), aluminum (Al), titanium (Ti), and tantalum (Ta)). 
     Referring to  FIG.  23   , an exposed portion of the first metal pattern MP 1  may be selectively removed by an etching process using the sixth metal pattern MP 6  as an etch mask. Since the second metal pattern MP 2  is not removed, a portion of the first metal pattern MP 1 , which is located between the second metal pattern MP 2  and the semiconductor pattern SP 1  to SP 4 , may not be removed. Furthermore, the second metal pattern MP 2 , which is placed below the top surface of the sixth metal pattern MP 6 , may also be left as it is. 
     The first and second metal patterns MP 1  and MP 2 , which are located below the top surface of the sixth metal pattern MP 6 , may be left to form the lower gate electrode LGE. The lower gate electrode LGE may include the first to third portions PO 1 , PO 2 , and PO 3 , which are respectively formed in the first to third inner regions IRG 1 , IRG 2 , and IRG 3 . Each of the first to third portions POL PO 2 , and PO 3  may include the first metal pattern MP 1  and the second metal pattern MP 2 . The lower gate electrode LGE may further include the sixth metal pattern MP 6 , which is formed in a lower portion of the outer region ORG. 
     Exposed portions of the first and second metal patterns MP 1  and MP 2  may be removed using the sixth metal pattern MP 6  as an etch mask. Thus, the upper gate insulating layer UGI may be exposed to the outside. 
     Referring back to  FIG.  17 B , the third metal pattern MP 3  may be formed on the upper gate insulating layer UGI. The third metal pattern MP 3  may be formed to have a thickness that is large enough to fully fill the fourth and fifth inner regions IRG 4  and IRG 5 . The third metal pattern MP 3  may be the first work function metal and may be formed of or include a metal nitride layer which is the same as or different from the first metal pattern MP 1 . 
     The fourth metal pattern MP 4  may be formed on the third metal pattern MP 3  to partially fill the outer region ORG. The fourth metal pattern MP 4  may be the second work function metal and may be formed of or include a metal carbide layer which is the same as or different from the second metal pattern MP 2 . 
     The fifth metal pattern MP 5  may be formed on the fourth metal pattern MP 4  to fill a remaining region of the outer region ORG. The fifth metal pattern MP 5  may be formed of or include the first work function metal (e.g., titanium nitride) or a low resistance metallic material (e.g., tungsten). 
     The third to fifth metal patterns MP 3  to MP 5 , which are formed on the lower gate electrode LGE, may constitute the upper gate electrode UGE. The upper gate electrode UGE may include the fourth and fifth portions PO 4  and PO 5 , which are formed in the fourth and fifth inner regions IRG 4  and IRG 5 , respectively. Each of the fourth and fifth portions PO 4  and PO 5  may include the third metal pattern MP 3 . The upper gate electrode UGE may further include the sixth portion PO 6  formed in the outer region ORG. The sixth portion PO 6  may include the third to fifth metal patterns MP 3 , MP 4 , and MP 5 , which are sequentially stacked. 
       FIG.  24    is a plan view illustrating a three-dimensional semiconductor device according to an embodiment of the inventive concept.  FIGS.  25 A to  25 D  are sectional views, which are respectively taken along lines A-A′, B-B′, C-C′, and D-D′ of  FIG.  24   . The three-dimensional semiconductor device illustrated in  FIGS.  24  and  25 A to  25 D  is provided as an example of the single height cell SHC of  FIG.  2   , and the inventive concept is not limited to this example. In the following description, an element previously described with reference to  FIGS.  3  and  4 A to  4 D  may be identified by the same reference number without repeating an overlapping description thereof, for the sake of brevity. 
     Referring to  FIGS.  24  and  25 A to  25 D , the logic cell LC may be provided on the substrate  100 . The logic cell LC according to the present embodiment may be an inverter cell. The logic cell LC may include the first and second active regions AR 1  and AR 2 , which are sequentially stacked. In the present embodiment, the first active region AR 1  may be an NMOSFET region, and the second active region AR 2  may be a PMOSFET region. 
     The first active region AR 1  may include the lower channel pattern CH 1  and the lower source/drain patterns SD 1 , which are disposed at both sides of the lower channel pattern CH 1 . The second active region AR 2  may include the upper channel pattern CH 2  and the upper source/drain patterns SD 2 , which are disposed at both sides of the upper channel pattern CH 2 . At least one dummy channel pattern DSP may be interposed between the lower channel pattern CH 1  and the upper channel pattern CH 2  thereon. 
     The gate electrode GE may be provided on the lower and upper channel patterns CH 1  and CH 2 , which are sequentially stacked. The gate electrode GE may include the lower gate electrode LGE, which is provided in the bottom tier (i.e., the first active region AR 1 ) of the FEOL layer, and the upper gate electrode UGE, which is provided in the top tier (i.e., the second active region AR 2 ) of the FEOL layer. 
     Referring to  FIG.  25 D , the gate contact GC, which is electrically connected to the gate electrode GE, may be provided. The gate contact GC may be disposed to be overlapped with the second interconnection line MI 2  of the first metal layer M 1 . 
     Referring to  FIG.  25 B , the first active contact AC 1  may be provided on the lower source/drain pattern SD 1  adjacent to a first side of the gate electrode GE. The first active contact AC 1  may include the vertical extended portion VEP and the horizontal extended portion HEP. The horizontal extended portion HEP may be extended in the first direction D 1 , and this may allow the vertical extended portion VEP to be overlapped with the first power line POR 1 . 
     The second active contact AC 2  may be provided on the upper source/drain pattern SD 2  adjacent to the first side of the gate electrode GE. The second active contact AC 2  may be spaced apart from the first active contact AC 1  in the first direction D 1 . A first portion of the second active contact AC 2  may be overlapped with the upper source/drain pattern SD 2 . A second portion of the second active contact AC 2  may be overlapped with the second power line POR 2 . 
     Referring to  FIG.  25 C , a third active contact AC 3  may be provided on the lower and upper source/drain patterns SD 1  and SD 2 , which are adjacent to a second side of the gate electrode GE opposite to the first side. The third active contact AC 3  may be vertically extended to be in contact with both of the lower and upper source/drain patterns SD 1  and SD 2 . In other words, the third active contact AC 3  may be a common contact, which is connected in common to the lower and upper source/drain patterns SD 1  and SD 2 . A first portion of the third active contact AC 3  may be overlapped with the lower and upper source/drain patterns SD 1  and SD 2 , and a second portion of the third active contact AC 3  may be overlapped with the first interconnection line MI 1  of the first metal layer M 1 . 
     The first metal layer M 1  and the active and gate contacts GC and AC 1  to AC 3  may be connected to each other through the vias VI. For example, the first power line POR 1  may be connected to the first active contact AC 1  through the via VI, and the second power line POR 2  may be connected to the second active contact AC 2  through the via VI. The first interconnection line MI 1  may be connected to the third active contact AC 3  through the via VI. The second interconnection line MI 2  may be connected to the gate contact GC through the via VI. 
     In a three-dimensional semiconductor device according to an embodiment of the inventive concept, a dummy channel pattern placed between a lower channel pattern and an upper channel pattern may be used to stably form a lower gate electrode and an upper gate electrode which are made of different materials. As a result, according to an embodiment of the inventive concept, it may be possible to realize a three-dimensional device, in which NMOS- and PMOS-FETs are vertically stacked, with high reliability. 
     While example embodiments of the inventive concept have been particularly shown and described, it will be understood by one of ordinary skill in the art that variations in form and detail may be made therein without departing from the scope of the present inventive concept.