Patent Publication Number: US-2023163942-A1

Title: Method and apparatus for carrying constant bit rate (CBR) client signals

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     The present application claims priority to U.S. Provisional Patent Application Ser. No. 63/282,292 filed on Nov. 23, 2021, the contents of which are incorporated by reference herein in their entirety. 
    
    
     BACKGROUND OF THE INVENTION 
     There are three primary classes of methods to transport a Constant Bit Rate (CBR) client over a cell/packet transport network. The first is purely adaptive where the sink node monitors the rate of arrival of cells/packets carrying the CBR client and adjusts its transmit phase lock loop (TxPLL) accordingly, to speed up or slow down. The sink node often implements a FIFO buffer to hold the CBR client and uses its depth to control the transmit phase locked loop. This scheme is susceptible to delay variations encountered by the CBR client in the transport network. For example, a decrease in delay would appear to the sink node as a faster arrival rate, and therefore the transmit phase locked loop may speed up spuriously. 
     In the second class of methods, the source node inserts a timestamp based on the arrival times of certain key bits of the CBR client. The timestamps and the CBR client data are bound into a carrier stream. The bit rate of the CBR client is computed by dividing the number of CBR client bits between successive timestamps and the change in timestamp values. This method is exemplified by IETF RFC 4553 SAToP which requires that the source and sink nodes share a common clock reference. However, requiring a common clock reference at source and sink nodes increases the deployment cost of the transport network. Moreover, the addition of a common clock reference is not feasible in some situations. 
     The third class of methods, exemplified by the International Telecommunication Union (ITU) Generic Mapping Procedure (GMP), introduces low jitter and wander into the CBR client and does not require a common reference clock. It involves inserting a client rate report, such as a GMP overhead, periodically into the carrier stream of the CBR client at the source node. At the input of an intermediate switching node, the rate report is processed to recover the bit rate of each CBR client. At the output of the intermediate node, the bit rate of respective ones of the CBR clients is re-encoded into a new rate report in relation to the bit rate of the egress carrier stream of the intermediate node. This scheme can be expensive and complex to implement when the number of CBR clients at an intermediates node is very large, because respective ones of the CBR clients requires its own rate report digital signal processor (DSP) engine. 
     Accordingly, there is a need for a method and apparatus that will allow for conveying CBR client signals without requiring processing and re-generating a new rate report for respective ones of the CBR clients at intermediate nodes. Furthermore, there is a need for a method and apparatus that does not require that source and sink nodes share a common reference clock. 
     SUMMARY OF THE INVENTION 
     A method is disclosed that includes receiving, at respective ones of a plurality of intermediate-network-nodes, a respective data stream generated by a previous network node. The respective data stream includes a constant bit rate (CBR) carrier stream corresponding to constant bit rate (CBR) signals received at a source node. A counter accumulating a PHY-scaled stream clock (IPSCk) is sampled at a nominal sampling period (Tps) of a local reference clock of the intermediate-network-node to obtain a cumulative PHY-scaled count (CPSC) of the received respective data stream. IPSCk is generated by scaling a clock recovered from the received respective data stream to a predetermined nominal frequency (Fipsck_nom). The method includes calculating a PHY-scaled stream phase offset (PSPO) that indicates the phase difference between a PHY-scaled stream nominal bit count (LPSD) and an incoming PHY-scaled count delta (IPSD), where the IPSD represents an increment between successive CPSCs. 
     The received respective data stream is demultiplexed to obtain the CBR carrier streams. Respective ones of the CBR carrier streams include a previous network node cumulative phase offset report (CPOR-P) that indicates a previous network node cumulative phase offset (CPO-P) and a client rate report (CRR) that indicates a measured bit count of the respective CBR client at the source node. A cumulative phase offset (CPO) is calculated for respective ones of the CBR carrier streams. The calculated CPO is a function of the CPO-P for the respective CBR carrier stream and the calculated PSPO. CPO-P in respective ones of the CBR carrier streams is replaced with the calculated CPO for the respective CBR carrier stream, or a function of the calculated CPO for the respective CBR carrier stream to generate an updated cumulative phase offset report (CPOR) in place of the CPOR-P in the respective CBR carrier stream. The respective CBR carrier streams are multiplexed into the intermediate-network-node data streams. The intermediate-network-node data streams are then transmitted from the particular intermediate-network-node. 
     An integrated circuit (IC) device includes a PHY link input to receive a data stream generated by a previous network node that includes a plurality of CBR carrier streams, respective ones of the CBR carrier streams including a CPOR-P that indicates a CPO-P and a CRR that indicates a measured bit count of the respective CBR client at the source node. A clock offset circuit is coupled to the PHY link input to sample a counter accumulating IPSCk at a Tps of a local reference clock of the intermediate-network-node to obtain a CPSC of the received respective data stream, the IPSCk generated by scaling a clock recovered from the received respective data stream to Fipsck_nom, and calculate a PSPO that indicates the phase difference between an LPSD and an IPSD, where the IPSD indicates the CPSC increment between successive CPSC samples. A demultiplexer is coupled to the PHY link input to demultiplex the received data stream to obtain the plurality of CBR carrier streams. Cumulative phase offset report (CPOR) update logic is coupled to the demultiplexer and the clock offset circuit to calculate a CPO for respective ones of the CBR carrier streams, wherein the calculated CPO is a function of the CPO-P and the calculated PSPO, and to replace the CPO-P with the calculated CPO for the respective CBR carrier stream, or a function of the calculated CPO for the respective CBR carrier stream, and to generate an updated CPOR for the respective CBR carrier stream in place of the CPOR-P in the respective CBR carrier stream. A multiplexer is coupled to the demultiplexer and the CPOR update logic to multiplex the CBR carrier streams into a plurality of intermediate-network-node data streams. Encoders are coupled to the multiplexer to encode the plurality of intermediate-network-node data streams. PHY link outputs are coupled to the encoders to transmit the plurality of intermediate-network-node data streams from the IC device. 
     A network includes a source node that includes: an input to receive a plurality of CBR signals, a CPOR generating circuit to generate a CPOR that indicates an initial CPO, a CRR generating circuit to generate a CRR that indicates the measured bit rate of the respective CBR client, a CBR mapper coupled to the input to generate for respective ones of the CBR signals a corresponding CBR carrier stream and to insert the CRR and CBR client data into the respective CBR carrier stream, and a source output processing circuit to insert the CPOR into the respective CBR carrier stream and multiplex the CBR carrier streams to generate a plurality of source data streams. 
     The network includes a plurality of intermediate-network-nodes coupled to the source node, respective ones of the intermediate-network-nodes including an IC device that includes: a PHY link input to receive a data stream generated by a previous network node that includes a plurality of CBR carrier streams, respective ones of the CBR carrier streams including a CPOR-P that indicates a CPO-P and the CRR. 
     The intermediate-network-nodes include a clock offset circuit coupled to the PHY link input to: sample a counter accumulating an IPSCk at a Tps of a local reference clock of the intermediate-network-node to obtain a CPSC of the received respective data stream, the IPSCk generated by scaling a clock recovered from the received respective data stream to a Fipsck_nom, and calculate a PHY-scaled stream phase offset (PSPO) that indicates the phase difference between an LPSD and an IPSD, where the IPSD indicates the increment between successive CPSCs. 
     The intermediate-network-nodes include a demultiplexer coupled to the PHY link input to demultiplex the received data stream to obtain the individual CBR carrier streams, and a CPOR update logic coupled to the demultiplexer and the clock offset circuit. The CPOR update logic is to calculate a CPO for respective ones of the CBR carrier streams, wherein the calculated CPO is a function of the CPO-P for the particular CBR carrier stream and the calculated PSPO, and to replace the CPO-P for the particular CBR carrier stream with the calculated CPO for the respective CBR carrier stream to generate an updated CPOR for the respective CBR carrier stream in place of the CPOR-P for the particular CBR carrier stream. 
     The intermediate-network-nodes include a multiplexer coupled to the demultiplexer and the CPOR update logic to multiplex the CBR carrier streams into a plurality of intermediate-network-node data streams, encoders coupled to the multiplexer to encode the plurality of intermediate-network-node data streams, and PHY link outputs coupled to the encoders to transmit the plurality of intermediate-network-node data streams from the IC device. 
     The network includes a sink node coupled to a last one of the intermediate-network-nodes to receive an intermediate-network-node data stream from a last one of the intermediate-network-nodes, recover CBR client signals; and output from the sink node a CBR signal that includes the recovered CBR client signals. 
     The disclosed method and apparatus allows for conveying CBR client signals without requiring processing and re-generating a new rate report for respective ones of the CBR clients at intermediate-network-nodes. Furthermore, the present method and apparatus does not require that source and sink nodes share a common reference clock. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in, and constitute a part of, this specification. The drawings illustrate various examples. The drawings referred to in this brief description are not drawn to scale. 
         FIG.  1    is a diagram illustrating a network that includes a source node, a sink node and a plurality of intermediate-network-nodes. 
         FIG.  2    is a diagram illustrating circuits of a source node. 
         FIG.  3    is a block diagram illustrating a CPOR. 
         FIG.  4    is a block diagram illustrating a data stream. 
         FIG.  5    is a block diagram illustrating an intermediate-network-node switch of the network of  FIG.  1   . 
         FIG.  6    is a diagram illustrating an IC device (switch) of the intermediate-network-node switch shown in  FIG.  5   . 
         FIG.  7    is a diagram showing an example of CPOR update logic that calculates CPO by adding CPO-P to the calculated PSPO. 
         FIG.  8    is a diagram showing an example of CPOR update logic that calculates CPO, where the calculated CPO is a function of all CPO-Ps received by the intermediate-network-node since a last initialization of the intermediate-network-node and all PSPOs calculated by the intermediate-network-node since a last initialization of the intermediate-network-node. 
         FIG.  9    is a diagram illustrating circuits of the sink node. 
         FIG.  10 A  is a flow diagram illustrating a method for coupling CBR signals over a network. 
         FIG.  10 B- 10 I  are block diagrams illustrating examples for performing portions of the method of  FIG.  10 A . 
     
    
    
     DETAILED DESCRIPTION 
       FIG.  1    shows an example of a network  4  that includes a source node  1 , a sink node  2  and a plurality of intermediate-network-nodes  3 , illustrated in  FIG.  1    as first intermediate-network-node  3   a , second intermediate-network-node  3   b  and last intermediate-network-node  3   c , which intermediate-network-nodes  3  extend logically between source node  1  and sink node  2  to couple source node  1  to sink node  2 . The respective intermediate-network-nodes may be implemented as switches. The relative parts per million frequency offset (RPPM) between the reference clock of the source and sink nodes (RPPMpath) can be represented by the equation: 
       RPPMpath=RPPMsw1+RPPMsw2+ . . . RPPMswn+RPPMsk 
     where RPPMsw1 is the RPPM between the reference clocks of intermediate-network-node  3   a  and source node  1  and is measured at the first intermediate-network-node  3   a , RPPMsw2 is the RPPM between the reference clocks of intermediate-network-node  3   b  and intermediate-network-node  3   a  and is measured at the second intermediate-network-node  3   b , RPPMswn is the RPPM between the reference clocks of intermediate-network-node node  3   c  and its upstream node and is measured at the n th  intermediate-network-node  3   c , and RPPMsk is the RPPM between the reference clocks of the immediate preceding intermediate-network-node (e.g. intermediate-network-node  3   c ) and the sink node  2 , measured at sink node  2 . 
       FIG.  2    shows an example source node  1  that includes local reference clock  20 , reference clock input  27 , a plurality of CBR processing circuits  29   a - 29   c , source output processing circuit  22  that includes a transmit PLL  28 , CBR signal inputs  30  and PHY link outputs  7 . Respective ones of CBR processing circuits  29   a - 29   c  includes a CRR timer circuit  23 , a CRR generating circuit  24 , a CPOR timer circuit  25 , a CPOR generating circuit  26  and a CBR mapper  21 . The CRR generating circuit  24  may be implemented using a Digital Signal Processor (DSP). 
     Respective ones of CPOR processing circuits  29   a - 29   c  are coupled to reference clock input  27 , respective CBR signal inputs  30  for receiving respective CBR signals, e.g., CBR signals  30   a ,  30   b ,  30   c , and to source output processing circuit  22 . CRR generating circuit  24  is coupled to CRR timer circuit  23  and to CBR mapper  21 . CPOR generating circuit  26  is coupled to CPOR timer circuit  25  and source output processing circuit  22 . Respective ones of CBR mappers  21  are coupled to a respective CBR signal input (e.g., one of CBR signal inputs  30 ) and to source output processing circuit  22 . Source output processing circuit  22  is coupled to PHY link outputs  7 . 
     Reference clock input  27  is coupled to local reference clock  20  of source node  1  to supply a reference clock signal  27   a  to CRR timer circuit  23  of the respective CBR processing circuits  29 , CPOR timer circuit  25  of the respective CBR processing circuits  29  and transmit phase locked loop  28 . 
     CPOR timer circuit  25  receives the reference clock signal  27   a  on reference clock input  27  and generates a timing signal Tcpor. CPOR generating circuit  26  receives timing signal Tcpor and generates a CPOR responsive to the received timing signal Tcpor. CRR timer circuit  23  receives the reference clock signal  27   a  and generates a timing signal Tcrr. CRR generating circuit  24  receives the respective CBR signal  30   a - 30   c  at a respective CBR signal input  30  and uses the received CBR signal  30   a - 30   c  and received timing signal Tcrr to generate a CRR that indicates the measured clock rate of the respective CBR client. The generation period of CRR (responsive to timing signal Tcrr) and CPOR (responsive to timing signal Tcpor) can be independent. 
       FIG.  3    shows an example of a CPOR  40  generated by CPOR generating circuit  26  that includes a CPOR header  31  and a CPO  5 . The term “CPO” as used in the present application is one or more value or word that indicates a cumulative phase offset. In the present example, it is a single numerical value indicated in bits, bytes or words of phase offset. The term “CPOR” as used in the present application is a sequence of characters that indicates a CPO. The CPO output by CPOR generating circuit  26  can be referred to as an “initial CPO.” In the present example, the initial CPO is not calculated at the source node, but rather is set to a predetermined value such as, for example, “0”, responsive to the received timing signal Tcpor. 
     CBR mapper  21  of  FIG.  2    receives a respective CBR signal  30   a - 30   c  and CRRs from CRR generating circuit  24  and generates a corresponding CBR carrier stream that is coupled to source output processing circuit  22 . CBR mapper  21  uses the information in the CRRs to format CBR client data into the CBR carrier stream and inserts the CRR and CBR client data into the respective CBR carrier stream. Source output processing circuit  22  inserts the CPOR into the respective CBR carrier stream and multiplexes the CBR carrier streams to generate a plurality of source data streams  7   a - 7   d  that are respectively output over PHY link outputs  7 . Transmit phase locked loop (PLL)  28  receives as input the reference clock signal  27   a  and generates timing signals that control the timing of the output of source data streams  7   a - 7   d . PHY link outputs  7  are phase locked to the local reference clock  20  by transmit PLL  28 . 
       FIG.  4    shows an example of a data stream cell or packet  6  that includes cell/packet overhead  32 , carrier overhead  33 , CPOR overhead  34 , CRR overhead  35  and CBR client payload  36 . CRR overhead  35  consists of CRRs generated by CRR generating circuit  24  (e.g. the CRR&#39;s generated for the particular data stream). When data stream cell or packet  6  exits as the source data stream  7   a - 7   d  of  FIG.  2   , CPOR overhead  34  consists of CPORs  40  generated by CPOR generating circuit  26  such that the CRR and CPOR are carried inband with the CBR client payload in the source data streams  7   a - 7   d  that are output. In the present example, to be robust against burst errors, CRR and CPOR in data stream cell or packet  6  can be distributed over multiple cells/packets. 
       FIG.  5    illustrates an example intermediate-network-node  3  that includes an integrated circuit (IC) device  10  and a local reference clock  37 . IC device  10  is coupled to local reference clock  37  by a reference clock input  39 , and includes PHY link inputs  8  and PHY link outputs  9 . IC device  10  may implement a switch, and in that example intermediate-network-node  3  may be an intermediate-network-node switch. There is no requirement for local reference clock  37  of intermediate-network-node  3  to be phase locked to the local reference clock of other intermediate network nodes  3 , to the local reference clock  20  of source node  1 , or to the local reference clock  39   a - 1  of the sink node. 
       FIG.  6    shows an example of an IC device  10  (e.g., a “switch”) that includes reference clock input  39 , PHY link inputs  8  for receiving a respective data stream, clock offset circuit  11 , demultiplexer  12 , multiplexer  13 , CPOR update logic  14 , FIFO registers  52   a - 52   f , other intermediate-network-node circuits  53 , encoders  15  and PHY link outputs  9 . Clock offset circuit  11  is coupled to CPOR update logic  14 , reference clock input  39  and a PHY link input  8 . Demultiplexer  12  is coupled to a PHY link input  8  and CPOR update logic  14 . CPOR update logic  14  is coupled to first-in-first-out (FIFO) registers  52   a - 52   c  such that respective ones of the CBR carrier streams is coupled to a respective one of FIFO&#39;s  52   a - 52   c . More particularly, first CBR carrier stream  50   a  is coupled to FIFO  52   a , second CBR carrier stream  50   b  is coupled to FIFO  52   b  and 3rd CBR carrier stream  50   c  is coupled to FIFO  52   c , it being understood that there may be n CBR carrier streams with n respective FIFOs. Multiplexer  13  includes one or more transmit PLL  16  and is coupled to FIFO&#39;s  52   a - 52   f  and encoders  15 . Respective ones of encoders  15  couple to a respective one of PHY link outputs  9 . Transmit PLL  16  receives as input a local reference clock signal  39   a  at reference clock input  39  and generates timing signals that control the timing of the output of Intermediate-network-node (INN) data streams  9   a - 9   d . Clock offset circuit  11  includes sample pulse generator  41 , cumulative phase counter circuit  42 , clock recovery circuit  43 , clock scaler circuit  44 , current count register  45 , previous count register  46 , first subtraction logic  48 , second subtraction logic  49  and LPSD register  47 . Sample pulse generator  41  is coupled to reference clock input  39  and cumulative phase counter circuit  42 . Clock recovery circuit  43  is coupled to a respective PHY link input  8 , and to clock scaler circuit  44 . Cumulative phase counter circuit  42  is coupled to current count register  45  and clock scaler circuit  44 . Current count register  45  is coupled to previous count register  46 . First subtraction logic  48  is coupled to current count register  45 , previous count register  46  and to second subtraction logic  49 . Second subtraction logic  49  is coupled to LPSD register  47  and to CPOR update logic  14 . First subtraction logic  48  and second subtraction logic  49  may be implemented as respective subtraction circuits. 
     In the present example IC device  10  is formed on a single integrated circuit die and does not include a respective DSP engine for each CBR client. PHY link inputs  8 , the clock offset circuit  11 , the demultiplexer  12 , the CPOR update logic  14 , the encoders  15  and the PHY link outputs  9  can be disposed in the single integrated circuit die. 
     The circuits for demultiplexing and updating CPOR for a data stream received at a first PHY link input  8  are shown in dashed line  54  in  FIG.  6   . Other intermediate-network-node circuits  53  can include the same circuits  54  for demultiplexing and updating CPOR for data streams  8   b - 8   d  received at other PHY link inputs  8 , and for coupling other carrier streams having updated CPORs to respective FIFOs  52   d - 52   f.    
     Respective ones (e.g., each) of PHY link inputs  8  receive a data stream generated by a previous network node, illustrated as data streams  8   a - 8   d  (e.g. one of source data streams  7   a - 7   d  or an INN data stream  9   a - 9   d  from a previous intermediate-network-node). Sample pulse generator  41  receives the local reference clock signal  39   a  at reference clock input  39  and generates sample pulses at a sampling period Tps using the local reference clock signal  39   a . The nominal period of the sample pulses is a constant across all nodes in network  4 , with the actual deviation in period dependent on the actual ppm offset of the respective local reference clock signal  39   a . The sampling period of the cumulative phase counter circuit  42  (i.e., Tps) is chosen to be longer than Tcpor of  FIG.  2   . In one example, Tps&gt;2*Tcpor. 
     Clock recovery circuit  43  receives the data stream  8   a  from the previous network node at the respective PHY link input  8  and recovers the PHY link clock signal (i.e., the clock of data stream  8   a ). The recovered PHY-link clock signal (Rclk) is output to clock scaler circuit  44 . The sequence of data bits in data stream  8   a  received at clock recovery circuit  43  is not relevant to the operation of clock offset circuit  11  and can be discarded at clock offset circuit  11 . 
     Clock scalar circuit  44  scales the Rclk to generate a PHY-scaled stream clock (IPSCk). In one example, the nominal clock rate of the PHY link (PHYck-nom) is used to determine the scaling factor. The term “nominal clock rate of the PHY link” as used in the present application is a value, and may be a value that indicates the clock rate, i.e., the bit rate, that PHY-link inputs  8  are designed to operate at, or a value that indicates the rate that a PHY-link (not shown) that couples to a PHY link inputs  8  is designed to operate at such as 10 Gbit/second or 25 Gbit/second. In one example, the scaling factor in  44  is set to (PHYck-nom/Fipsck_nom), where Fipsck_nom is a predetermined nominal frequency. Accordingly, the rate of IPSCk=Rclk * (Fipsck_nom/PHYck-nom). Thus, the nominal clock rate of IPSCk is constant over the entire network  4  (all intermediate-network-nodes and the sink node). Fipsck_nom is a constant, defined across all nodes in the transport network, and is chosen to provide a simple scalar ratio between PHY link clock rates in the network  4 . For example, the Fipsck_nom in network  4  may be set to 1.0 MHz or 10 MHz. In one example Fipsck_nom represents the nominal rate of IPSCk and is the nominal clock frequency of all “PHY-scaled stream clocks” in the network, where the clock recovery circuit  43  and clock scaler circuit  44  of each clock offset circuit  11  in the network  4  is considered to constitute a “PHY-scaled stream clock” of the network, without limitation. In one example a value 1 MHz is used as Fipsck_nom to perform the scaling in all intermediate-network-nodes of the network and in the sink node. In this example, the Rclk is divided by the scaling factor in  44  to generate IPSCk. It is appreciated that the present use of 1 MHz as the nominal Fipsck_nom is only a single example, and that other values could also be used. 
     A counter (i.e., a cumulative phase counter) of cumulative phase counter circuit  42  accumulating IPSCk is sampled by cumulative phase counter circuit  42  based on the local reference clock signal  39   a  provided by local reference clock  37  at a period of Tps to obtain a CPSC of the received respective data stream. In one example, cumulative phase counter circuit  42  accumulate the edges of IPSCk into a free running counter to generate CPSC. Logically, the counter can go to infinity. In this example the counter of cumulative phase counter circuit  42  is sampled at every pulse (once per Tps) received from sample pulse generator  41  to obtain the CPSC of the received respective data stream. In one example cumulative phase counter circuit  42  increments by 1 at every IPSCk clock edge and the value of the counter in cumulative phase counter circuit  44  is sampled once at each Tps to identify the current bit count that comprises CPSC. The current CPSC output by cumulative phase counter circuit  42  at Tps is stored in current count register  45 . When a new CPSC is output, responsive to the next pulse from sample pulse generator  41 , i.e. after Tps, the previous CPSC is stored in previous count register  46  prior to storing the new CPSC in current count register  45  (e.g., by moving the CPSC stored in current count register  45  to previous count register  46 ). Thereby the current CPSC and the previous CPSC output from cumulative phase counter circuit  42  are stored in registers  45 - 46 . 
     In one example the counter in cumulative phase counter circuit  42  is not cleared. It is merely sampled at Tps instances. The previous sampled value is subtracted from the current sampled value to produce an effect similar to clearing at every Tps, but it is not sensitive to a clearing signal lining up closely with IPSCk which increments the counter. 
     In the present example, the CPSC generated by cumulative phase counter circuit  42  indicates phase using bits (bit count). Bits (bit count) is a convenient unit of measurement, with the amount of phase delivered by an upstream node being a monotonically rising value that goes on to infinity, in terms of bits, bytes, or radians, without limitation. In alternate embodiments bytes, radians or other measurements could be used by cumulative phase counter circuit  42  to identify the actual delivery of phase, against Tps, as determined by the local reference clock signal  39   a . In an alternate example, the bit rate could be used. However, that may involve one or more division step, and therefore may not as efficient as staying in the count domain. 
     The clock offset circuit  11  calculates a PSPO that indicates the phase difference between a PHY-scaled stream nominal bit count (LPSD) and an incoming PHY-scaled count delta (IPSD). The term “PHY-scaled stream nominal bit count,” as used in the present application, that may also be referred to as a “local PHY-stream delta” or “LPSD” is a value that indicates a local constant increment in phase count over a period of time, and may be a function Tps and Fipsck_nom. LPSD represents the expected amount of increment at the intermediate-network-node based on Fipsck_nom and Tps. In the present example, an LPSD that is a function of Fipsck_nom and Tps is stored in LPSD register  47 . In one example, LPSD is computed from the product of Fipsck_nom and the Tps, using the equation: LPSD=Fipsck_nom* Tps. As indicated above, the LPSD is stored in LPSD register  47 . Logically, Tcrr of  FIG.  2    can be expressed in terms of the number of PHY-scaled stream bits (Ncrr) using the relation Ncrr=Tcrr * Fipsck_nom. 
     First subtraction logic  48  subtracts the previous CPSC in register  46  from the current CPSC in register  45  to obtain IPSD. Since IPSD represents a CPSC increment between successive CPSCs as sampled by cumulative phase counter circuit  42  (i.e. indicates the increment in the CPSC count within a Tps period) it indicates the increment in accumulated phase (bit count) within a Tps. 
     Second subtraction logic  49  subtracts LPSD from IPSD to calculate the PHY-scaled stream phase offset (PSPO). Accordingly, PSPO=(IPSD−LPSD) such that PSPO captures the relative parts-per-million (PPM) offset (RPPM) between the reference clock at the upstream node used to generate the data stream  8   a  and the local reference clock  37 , encoded in units of phase. Using units of phase is superior to units of frequency as it allows the sink node to be phase locked to the source node more easily. Using units of frequency would only allow frequency lock. 
     In one example PHY link is a 10 Gbit/s link such that its clock rate is nominally 10,000,000,000 cycles/second and Fipsck_nom is 1 MHz giving an IPSCk=Rclk* (1,000,000/10,000,000,000)=Rclk/10,000 that is sampled at Tps and LPSD=1,000,000*Tps. Accordingly, the resulting PSPO will capture the difference between what is expected (LPSD) and what is calculated/measured (IPSD) in units of phase. 
     Demultiplexer  12  demultiplexes the received data stream  8   a  to obtain the individual CBR carrier streams  50   a - 50   c , and outputs a first CBR carrier stream  50   a  at a respective demultiplexer output  50  that couples to CPOR update logic  14 , outputs a second CBR carrier stream  50   b  at a respective demultiplexer output  50  that couples to CPOR update logic  14  and so forth to a 3rd CBR carrier stream  50   c  output at a respective demultiplexer output  50  that couples to CPOR update logic  14 . While 3 CBR carrier stream outputs are shown, n CBR carrier streams may be output at n respective demultiplexer outputs  50 . 
     Respective ones of the CBR carrier streams  50   a - 50   c  (e.g., each of CBR carrier streams  50   a - 50   c ) include a CRR that indicates a measured bit count of the respective CBR client at the source node and a CPOR-P that indicates a CPO-P, i.e. a CPO of a previous node. A CPO is calculated for respective ones of the CBR carrier streams (e.g., each of CBR carrier streams  50   a - 50   c ) and CPO-P for respective ones of the CBR carrier streams  50   a - 50   c  is replaced with the calculated CPO for the respective CBR carrier stream, where the calculated CPO is a function of the CPO-P for the particular carrier stream and the calculated PSPO. 
     In  FIG.  7   , an example of CPOR update logic  14  is shown as CPOR update logic  14   a , that includes a CPOR-P register  55 , PSPO register  95  (e.g., a self-clearing register), an adder circuit  57 , CPO replacement logic  58  and an output  59  coupled to a respective one of FIFO&#39;s  52   a - 52   c . CPOR-P register  55  is coupled to a demultiplexer output  50 , which carries a respective CBR carrier stream. Adder circuit  57  is coupled to CPOR-P register  55  and to PSPO register  95 . PSPO register  95  is coupled to clock offset circuit  11  by CPOR update logic input  56  ( FIG.  6   ), where CPOR update logic input  56  is coupled to second subtraction logic  49 . CPO replacement logic  58  is coupled to PSPO register  95 , an output of adder circuit  57  and output  59  that is coupled to the respective one of FIFO&#39;s  52   a - 52   c . In one example CPO replacement logic  58  indicates that a CPO has been replaced using an CPRO_Updated signal to trigger the PSPO register  95  to clear to value 0. 
     Continuing with  FIG.  7   , CPOR-P is received at CPOR-P register  55  that is indicative of a CPO-P. Adder circuit  57  obtains the calculated PSPO from PSPO register  95  and calculates CPO for respective ones of the CBR carrier streams by adding the calculated PSPO to the CPO-P for the respective CBR carrier stream. CPOR update logic  14   a  replaces CPO-P in CPOR-P with the calculated CPO for the respective CBR carrier stream to generate an updated CPOR for the respective CBR carrier stream that is output to a corresponding FIFO  52   a - 52   f . Upon replacing the CPOR-P with the calculated CPO, PSPO register  55  is reset to a value of “0.” In the present example, there is a single PSPO calculated from the PHY link and the calculated PSPO is shared by all the CBR carriers demultiplexed from the particular PHY link. Alternatively, CPO-P is replaced with a function of the calculated CPO such as an offset to the calculated CPO or an encoding of the calculated CPO. 
     In the example shown in  FIG.  7   , source node  1  generates a CPOR placeholder and respective ones of the intermediate nodes update the CPOR it by adding a calculated PSPO that indicates the “phase delta” (e.g., the relative change in phase) of the logical PHY-scaled stream derived from an ingress PHY link and what the node expects to see using its own local reference clock signal  39   a  (i.e., LPSD). The PSPO (e.g., “phase delta”) can be positive or negative, e.g. +3, -7, +6, without limitation. Whatever that value is, the node adds it to the received CPOR  40  embedded within the respective CBR carrier stream by adding the calculated PSPO to CPO-P, and replacing CPOR  40  with the resultant value. If the PSPO is negative, the addition will cause the calculated CPO in the outgoing CPOR to be smaller than the CPO-P from the previous network node. If the calculated PSPO is positive, the addition will cause the calculated CPO in the outgoing CPOR to be larger than the CPO-P from the previous network node. In any case, the CPOR update has the effect of accumulating PSPO (e.g., “phase delta”) as it traverses the network. It is possible for the CPOR to be lost in transit. If that were to happen, the sink will be missing one set of phase deltas from the intermediate nodes between the source and the sink. The method and apparatus shown in  FIG.  8    is intended to address that problem. 
     In the alternate example that is shown at  FIG.  8    the calculated CPO is a function of all of CPO-P received by the intermediate-network-node  3  since a last initialization of the intermediate-network-node  3  and a function of all PSPO calculated by the intermediate-network-node  3  since the last initialization of the intermediate-network-node  3 . In this example, a CPOR update logic  14   b  is shown that includes CPOR-P register  55 , accumulator  60 , previous CPOR-P register  61 , subtraction logic  62 , accumulator  63 , adder logic  64 , CPO replacement logic  58  and an output  59  coupled to a respective one of FIFO&#39;s  52   a - 52   c . Subtraction logic  62  may be implemented by a subtraction circuit and adder logic  64  may be implemented by an adder circuit. CPOR-P register  55  is coupled to a demultiplexer output  50 , which carries a respective CBR carrier stream, and to previous CPOR-P register  61 . Subtraction logic  62  is coupled to CPOR-P register  55 , to previous CPOR-P register  61  and to accumulator  63 . Adder logic  64  is coupled to accumulator  63 , accumulator  60  and CPO replacement logic  58 . Accumulator  60  is coupled to clock offset circuit  11  by CPOR update logic input  56  ( FIG.  6   ). CPO replacement logic  58  is coupled to demultiplexer output  50  and output  59  that is coupled to a respective one of FIFO&#39;s  52   a - 52   c.    
     CPOR update logic  14   b  receives CPOR-P at CPOR-P register  55  from the respective CBR carrier stream. When a next CPOR-P is received the previous CPOR-P is moved to previous CPOR-P register  61 , becoming the “previous CPOR-P” and the received CPOR-P is stored in CPOR-P register  55 . Subtraction logic  62  subtracts the CPO-P in the previous CPOR-P, stored in previous CPOR-P register  61 , from the present CPO-P in CPOR-P register  55  to obtain a delta cumulative phase offset (D-CPO). Accumulator  63  calculates an accumulated delta cumulative phase offset (ADCPO) by accumulating all of the D-CPO calculated by the particular intermediate-network-node since a last initialization of the particular intermediate-network-node. Accumulator  60  calculates an accumulated PSPO (APSPO) by accumulating all of the calculated PSPO received at input  56  since a last initialization of the particular intermediate-network-node  3 . Adder logic  64  adds the ADCPO to APSPO to calculate the CPO, which may also be referred to as an accumulated CPO (ACPO). CPO replacement logic  58  receives the CBR carrier stream and replaces CPO-P in CPOR-P with ACPO to generate an updated CPOR for the respective CBR carrier stream that is output at output  59  to a respective one of FIFO&#39;s  52   a - 52   f.    
     In applications where the PHY links may experience high bit error rates, cells and packets carrying the CPOR may be dropped due to CRC verification failures. The example shown in  FIG.  8    is tolerant of dropped CPOR cells and packets. More particularly, instead of calculating CPO by adding PSPO to CPO-P as in the embodiment of  FIG.  7   , the current incoming CPOR-P and the previous CPOR-P are used to make sure the calculated CPO is correct. If a CPOR is missing, the received CPOR-P would not actually be the previous one but is actually the previous, previous CPOR-P. In the example in which there is a sequence of CPORs, the newest to oldest may be labelled as: CPOR5, CPOR4, CPOR3, CPOR2, CPOR1. CPRO1 is the first to arrive at the last intermediate-network-node  3   c . CPOR2 is next to arrive and CPOR5 is the most recent one to arrive. Accumulator  63  accumulates the differences as reflected by every incoming CPOR. Consider the case where CPOR3 is missing due to corruption. The previous CPOR-P register  61  in  FIG.  8    would contain CPOR2 and the current CPOR-P register  55  would contain CPOR4. The difference between CPOR4-CPOR2 would be equal to (CPRO3−CPOR2)+(CPOR4−CPOR3). Thus, the value in the accumulator (ADCPO) will catch up to the same value as the scenario where no CPOR has gone missing. Accordingly, the missing CPOR does no lasting damage. 
     The CBR carrier streams are multiplexed into intermediate-network-node data streams and the intermediate-network-node data streams are transmitted from the respective intermediate-network-node. In  FIG.  6   , multiplexer  13  receives the output of FIFOs  52   a - 52   f  and multiplexes the output of FIFOs  52   a - 52   f  (the CBR carrier streams) into intermediate-network-node data streams that are coupled to respective ones of encoders  15 , that encode the received intermediate-network-node data stream to output a corresponding INN data stream over respective PHY link outputs  9 . The clocks of the PHY link outputs are phase locked to the local reference clock signal  39   a  received at the local reference clock input  39  via transmit PLL  16 . Respective ones of the intermediate-network-node data streams include the CRRs generated by source node  1  and the intermediate-network-nodes  3  are not required to change the content of any of the CRRs. In one example, none of the intermediate-network-nodes  3  change the content of any of the CRRs. 
       FIG.  9    illustrates a sink node  2 . In the following discussion many of the operations of sink node  2  are performed in the same way as they are performed at intermediate-network-nodes. To distinguish the calculations at the sink node and the resulting values from those that are performed at intermediate-network-nodes, the corresponding values are indicated as “Sink” values and by adding an “S” to the end of relevant terms, and other terms are distinguished from those of intermediate-network-nodes by adding the phrase “of the sink node” after the respective term, where the numbers of some of the like elements in the sink node are distinguished from those of  FIG.  6    by adding “−1” to the respective number of the particular element in  FIG.  6   . 
     Sink node  2  includes PHY link inputs  8 - 1 , local reference clock input  39 - 1  for receiving a local reference clock signal  39   a - 1 , clock offset circuit  11 - 1 , demultiplexer  12 - 1 , CPOR update logic  14 - 1 , sink output processing circuit  79 , other sink node circuits  70  and outputs  78   a - 78   d . Demultiplexer  12 - 1  is coupled to PHY link input  8 - 1  and CPOR update logic  14 - 1 . Clock offset circuit  11 - 1  is coupled to local reference clock input  39 - 1 , a PHY link input  8 - 1  and CPOR update logic  14 - 1 . Sink output processing circuit  79  is coupled to CPOR update logic  14 - 1  and to output  78 . Clock offset circuit  11  includes sample pulse generator  41 - 1 , cumulative phase counter circuit  42 - 1 , clock recovery circuit  43 - 1 , clock scaler circuit  44 - 1 , current count register  45 - 1 , previous count register  46 - 1 , first subtraction logic  48 - 1 , second subtraction logic  49 - 1  and LPSD register  47 - 1 . First subtraction logic  48 - 1  and second subtraction logic  49 - 1  may be implemented as respective subtraction circuits. Sample pulse generator  41 - 1  is coupled to reference clock input  39 - 1  and cumulative phase counter circuit  42 - 1 . Clock recovery circuit  43 - 1  is coupled to a respective PHY link input  8 - 1 , and to clock scaler circuit  44 - 1 . Cumulative phase counter circuit  42 - 1  is coupled to current count register  45 - 1  and clock scaler circuit  44 - 1 . Current count register  45 - 1  is coupled to previous count register  46 - 1 . First subtraction logic  48 - 1  is coupled to current count register  45 - 1 , previous count register  46 - 1  and to second subtraction logic  49 - 1 . Second subtraction logic  49 - 1  is coupled to LPSD register  47 - 1  and to CPOR update logic  14 - 1 . 
     Sink output processing circuit  79  includes CPO extraction logic  71 , read modulator  72 , CRR extraction logic  73 , CBR extraction logic  74 , CRR FIFO  75 , CBR payload FIFO  76  and transmit PLL  77 . CPO extraction logic  71  is coupled to the output  59 - 1  of CPOR update logic  14 - 1  that outputs CBR carrier stream  50   d  with an updated CPOR and is coupled to read modulator  72 . CRR extraction logic  73  and CBR extraction logic  74  are coupled to an output  50 - 1  of demultiplexer  12 - 1  to receive one of CBR carrier streams  50   a - 50   c . CRR FIFO  75  is coupled to read modulator  72 , CRR extraction logic  73  and transmit PLL  77 . Transmit PLL  77  is coupled to local reference clock input  39 - 1 . CBR payload FIFO  76  is coupled to CBR extraction logic  74  and transmit PLL  77 . Other sink node circuits  70  are coupled to local reference clock input  39 - 1 , PHY link inputs  8  and outputs  78   b - 78   d.    
     Intermediate-network-node data streams  8   e - 8   h  are received at the sink node  2 . In  FIG.  9    clock offset circuit  11 - 1  of the sink node receives an INN data stream at a PHY link input  8 - 1  and clock offset circuit  11 - 1  measures a bit count of the received INN data stream based on a local reference clock signal  39   a - 1  of the sink node and calculates PSPO-S for the received intermediate-network-node data stream. In the present example PSPO-S is calculated in the same manner as the PSPO calculated at intermediate-network-nodes and indicates the difference between the CPSC increment in the particular INN data stream received at the sink node and LPSD. 
     Following is an example that illustrates processing of a single INN data streams  8   e  to obtain the CBR signal with recovered client signals  78   a . The processing of the other INN data streams  8   f - 8   h  can be performed in the same manner as that of INN data stream  8   e  and some or all of the apparatus shown in  FIG.  9    for processing INN data stream  8   e  may be included in other sink node circuits  70  for processing INN data streams  8   f - 8   h  (e.g., other sink node circuits  70  can include an identical set of circuits for processing each of INN data streams  8   f - 8   h ). PHY link input  8 - 1  of the sink node receives intermediate-network-node data stream  8   e  from the last intermediate-network-node. Clock offset circuit  11 - 1  of the sink node is coupled to the PHY link input  8 - 1  of the sink node to: sample a counter accumulating an IPSCk at the sink node at Tps of a local reference clock of the sink node to obtain a CPSC at the sink node, the IPSCk generated by scaling a clock recovered from the received intermediate-network-node data stream of the last intermediate-network node  8   e  to Fipsck_nom, and calculate a PSPO at the sink node (PSPO-S) that indicates the phase difference between a LPSD at the sink node and an IPSD at the sink node, where the IPSD at the sink node indicates the CPSC increment between successive CPSC samples at the sink node. Demultiplexer of the sink node  12 - 1  is coupled to the PHY link input of the sink node  8 - 1  to demultiplex the intermediate-network-node data stream received from the last intermediate-network-node  8   e  to obtain the individual CBR carrier streams at the sink node  50   d - 50   f . CPOR update logic of the sink node  14 - 1  is coupled to the clock offset circuit  11 - 1  to calculate a CPO at the sink node (CPO-S) for respective ones of the CBR carrier streams  50   d - 50   f  by adding the PSPO-S to a CPO-P received at the sink node (i.e., received from the last intermediate-network-node) for the respective CBR data stream  50   d - 50   f . Sink output processing circuit  79  is coupled to demultiplexer of the sink node  12 - 1  and the CPOR update logic of the sink node  14 - 1  to recover the CBR client signals using the CPO-S and the CRR corresponding to the particular CBR signal. PHY link output of the sink node  78  is coupled to sink output processing circuit  78  to output from the sink node CBR signals that include the recovered CBR client signals. 
     In one example CPO-S is calculated in the same manner as illustrated with regard to  FIG.  7   , where calculating the CPO-S includes adding the calculated PSPO-S to a CPO-P received at the sink node for the respective CBR data stream (e.g., the CPO-P from the last-intermediate-network-node). In one example intermediate-network-node data stream  8   e  includes a CPOR-P that indicates a CPO-P from the last intermediate-network-node that is demultiplexed to obtain the individual CBR carrier streams  50   d - 50   f  that are output at respective demultiplexer outputs  50 - 1 . CPOR update logic  14 - 1  calculates a CPO-S for carrier stream  50   d  that replaces the CPO-P in CBR carrier stream  50   d  to form a first updated CPOR at the sink node  91   a . CPOR update logic  14 - 1  calculates a CPO-S for carrier stream  50   e  that replaces the CPO-P in CBR carrier stream  50   e  to form a second updated CPOR at the sink node  91   b  and so forth to the n th  CPO-S  91   c  for the n th  CBR carrier stream  50   f.    
     In another example CPO-S is calculated in the same manner as illustrated with regard to  FIG.  8   , where CPOR update logic  14   b  receives CPOR-P at CPOR-P register  55  from the respective CBR carrier stream  50   d - 50   f  that is a CPOR-P from the last intermediate-network-node. When a next CPOR-P is received the previous CPOR-P is moved to previous CPOR-P register  61 , becoming the “previous CPOR-P” at the sink node and the received CPOR-P is stored in CPOR-P register  55 . Subtraction logic  62  subtracts the CPO-P in the previous CPOR-P, stored in previous CPOR-P register  61  from the present CPO-P in CPOR-P register  55  to obtain a delta cumulative phase offset (D-CPO) at the sink node. Accumulator  63  calculates a sink accumulated delta cumulative phase offset (ADCPO-S) by accumulating all of the D-CPO calculated by the sink node since a last initialization of the sink node. Accumulator  60  calculates a sink accumulated PSPO (APSPO-S) by accumulating all of the calculated PSPO received at input  56  since a last initialization of the sink node. Adder logic  64  adds the ADCPO-S to APSPO-S to calculate the CPO-S. CPO replacement logic  58  receives the CBR carrier stream  50   d - 50   f  and replaces CPO-P in CPOR-P with the calculated CPO-S to generate an updated CPOR for the respective CBR carrier stream  50   d - 50   f  that is output at output  59  to CRR extraction logic  71 . 
     Optionally the CPO-P received at the sink node is replaced with the CPO-S for the respective CBR carrier stream (e.g., so that the circuits of CPOR update logic  14  is the same as CPOR update logic  14 - 1  for simplified design and manufacture). Sink output processing circuit  79  recovers the CBR client signals using the CPO-S and the CRR corresponding to the particular CBR signal. PHY link output  78  is coupled to the sink output processing circuit  79  to output from the sink node CBR signals  78   a  that include the recovered CBR client signals. 
     In  FIG.  9    a single sink output processing circuit  79  is illustrated to show the processing of the  91   a  and CBR carrier stream  50   d . However, in one example, a sink output processing circuit  79  includes similar or identical circuits that are coupled to each output  59  that operate in the same manner as the sink output processing circuit  79  that is illustrated for processing the first updated CPOR at the sink node  91   a  and the first carrier stream  50   d.    
     In one example, CRR extraction logic  73  extracts the incoming CRR from CBR carrier stream  50   d  and stores it in CRR FIFO  75 . CRR FIFO  75  is read out nominally at Tcrr as measured by the local reference clock and the phase value in the CRR is sent to transmit PLL  77  as the reference input phase. In one example CPOR update logic  14 - 1  generates a new CPOR at first updated CPOR at the sink node  91   a . The new CPOR is coupled to CPO extraction logic  71  that extracts CPO-S and indicates a corresponding CPO-S to read modulator  72 . In the example shown in  FIG.  7   , CPO-S can be taken from CPOR update logic  14 - 1  directly and used by read modulator  72  to modulate the instance at which a CRR is read out of CRR FIFO  75 . However, in the example shown in  FIG.  8   , since the CPO is a cumulative value, the previous CPO-S is subtracted from the new CPO-S to identify a CPO-S to be used by read modulator  72  to modulate the instance at which a CRR is read out of CRR FIFO  75 . If CPO-S indicates that there is a positive ppm offset between the reference clock at the source node relative to the sink node (RPPMpath is positive), the CRR FIFO is read more frequently than Tcrr. Conversely, if CPO-S indicates that there is a negative ppm offset between the reference clock relative to the sink node (if RPPMpath is negative), the CRR FIFO is read less frequently than Tcrr. CBR extraction logic  74  receives CBR carrier stream  50   d  and extracts the CBR client signals, coupling them to CBR payload FIFO  76 . Transmit PLL  77  is coupled to local reference clock input  39 - 1  and receives the reference clock signals  39   a - 1  and provides transmit clock signals to CBR payload FIFO  76  to re-generate a phase-locked copy of the client stream of the source node. Implementation alternatives to modulating CRR FIFO read instances are described in U.S. Pat. Nos. 8,542,708 and 9,019,997, that are incorporated herein by reference in their entirety. 
       FIG.  10 A  illustrates blocks of a method  100  in which a data stream generated by a previous network node is received ( 101 ). The received data stream includes a CBR carrier stream corresponding to CBR signals received at a source node. A counter accumulating IPSCk is sampled ( 102 ) at a Tps of a local reference clock of the intermediate-network-node to obtain a CPSC of the received respective data stream, the IPSCk generated by scaling a clock recovered from the received respective data stream to Fipsck_nom. A PSPO is calculated ( 103 ) that indicates the phase difference between a LPSD and an IPSD, where the IPSD represents an increment between successive CPSCs. In one example, LPSD represents the expected amount of increment at the intermediate-network-node based on the Fipck_nom and the Tps. In one example that is illustrated in block  103 - 1  of  FIG.  10 B  PSPO is calculated by: by calculating an IPSD that indicates the increase in bit count within the Tps (e.g., by subtracting the previous CPSC from the current CPSC); and subtracting the LPSD from the IPSD), where the calculated PSPO is in units of phase and LPSD is a function of the Fipsck_nom and the Tps. 
     The received data stream is demultiplexed ( 104 ) to obtain the CBR carrier streams, respective ones of the CBR carrier streams including a CPOR-P that indicates a CPO-P. In an example that is illustrated in block  104 - 1  of  FIG.  10 C  each of the CBR carrier streams also include a CRR that indicates a measured bit count of the respective CBR client at the source node. In one example the intermediate-network-nodes  3 - 3   c  do not change the content of CRRs. In one example the intermediate-network-nodes are not required to terminate any of the CRRs, generate new CRRs or change the content of any of the CRRs. In one example the intermediate-network-nodes  3 - 3   c  do not terminate any of the CRRs, generate new CRRs or change the content of any of the CRRs. 
     A CPO is calculated ( 105 ) for respective ones of the CBR carrier streams (e.g., each of the CBR carrier streams) and CPO-P for respective ones of the CBR carrier streams (e.g., each of the CBR carrier streams) is replaced ( 106 ) with the calculated CPO for the respective CBR carrier stream, where the calculated CPO is a function of the CPO-P for the particular carrier stream and the calculated PSPO. In an example that is illustrated in block  105 - 1  of  FIG.  10 D  CPO is calculated by adding the calculated PSPO to the CPO-P. In an example that is illustrated in block  105 - 2  of  FIG.  10 E  CPO is a function of all CPO-Ps received by the intermediate-network-node since a last initialization of the intermediate-network-node. In an example that is illustrated in block  105 - 3  of  FIG.  10 F  the CPO is an accumulated PSPO (ACPO) calculated by: calculating delta cumulative phase offset (D-CPO) by subtracting a previously received CPO-P from the CPO-P; calculating an accumulated D-CPO (ADCPO) by accumulating all D-CPO calculated by the intermediate network node since a last initialization of the intermediate-network-node; calculating an accumulated PSPO (APSPO) by accumulating all of the PSPO calculated by the intermediate-network-node since the last initialization of the intermediate-network-node; and adding APSPO to ADCPO). 
     The CBR carrier streams are multiplexed into intermediate-network-node data streams ( 107 ) and the intermediate-network-node data streams are transmitted ( 108 ) from the respective intermediate-network-node. 
       FIG.  10 G  illustrates blocks of method  100  that are performed at a sink node. Intermediate-network-node data streams are received ( 100 - 1 ) from a last intermediate-network-node at a sink node. A counter accumulating a PHY-scaled stream clock at the sink node (IPSCk-S) is sampled ( 100 - 2 ) at Tps based on a local reference clock of the sink node to obtain a cumulative PHY-scaled count at the sink node (CPSC-S), the IPSCk-S generated by scaling a clock recovered from the received intermediate-network-node data stream of the last intermediate-network node to Fipsck_nom. A PHY-scaled stream phase offset at the sink node (PSPO-S) is calculated ( 100 - 3 ) by subtracting the LPSD at the sink node from the incoming PHY-scaled count delta at the sink node (IPSD-S), where the IPSD-S represents increments between successive CPSC-Ss, which may termed a CPSC-S increment. The received intermediate-network-node data stream from the last intermediate-network-node is demultiplexed ( 100 - 4 ) to obtain the individual CBR carrier streams. 
     A CPO is calculated ( 100 - 5 ) at the sink node (CPO-S) for respective ones of the CBR carrier streams. In an example that is illustrated in block  100 - 5 - 1  of  FIG.  10 H  calculating the CPO-S includes adding the calculated PSPO-S to a CPO-P received at the sink node for the respective CBR data stream. In an example that is illustrated in block  100 - 5 - 2  of  FIG.  10 I  the calculated CPO-S is an ACPO calculated by: calculating a delta cumulative phase offset (D-CPO) at the sink node by subtracting a previously received CPO-P received at the sink node from a CPO-P received at the sink node; calculating a sink accumulated D-CPO (ADCPO-S) by accumulating all of the D-CPO calculated by the sink node since a last initialization of the sink node; calculating a sink accumulated PSPO (APSPO-S) by accumulating all of the PSPO calculated by the sink node since a last initialization of the sink node; and adding the APSPO-S to the ADCPO-S. 
     CBR client signals are recovered ( 100 - 6 ) using the calculated CPO-S and the CRR corresponding to the particular CBR signal. CBR signals that include the recovered CBR client signals are output ( 100 - 7 ) from the sink node. 
     In accordance with the methods and apparatus of the present invention, the ppm offset of respective ones of the nodes is represented in the CPOR produced by the respective one of the nodes. At the sink node, the CPOR received is generated by the last switching node and thus, only need to be biased by the relative ppm offset between the last switching node and the sink node (RPPMsk). The CRR is generated by the source node and is forwarded verbatim to the sink node. The ppm offset of the source node is represented in the CRR, which can be based on ITU GMP or similar schemes. The sink node uses the relative ppm offset between the source and sink nodes (RPPMpath) to bias the processing of the received CRR. 
     The present method and apparatus measure the ppm offset between pairs of nodes and then sums the measured ppm offsets together to get the source to sink ppm offset. In source node  1 , there are actually two ppm offsets at play. One is the ppm offset of the CBR client from its nominal value. This is what the CRR encodes. Unfortunately, while doing so, the measurement is tainted by the ppm offset of the local reference clock at the source node  1 . This is the second ppm offset. For example, when the CBR client is 10 ppm faster than its nominal value, the CRR will only indicates such a 10 ppm value if the local reference clock  20  is perfectly nominal. If the source local reference clock  20  is also 10 ppm fast, the CRR would spuriously report a nominal value. 
     The present method and apparatus convey RPPMpath to sink output processing circuit  79  using CPOR&#39;s, thereby avoiding the problem of the measurement being tainted by the reference clock at source node  1 . Because the present method and apparatus shares a common mathematical basis with the ITU GMP scheme, both are expected to have similar jitter and wander performance. 
     Following is an example in which network  4  of  FIG.  1    includes intermediate-network-node switches  3   a - 3   c . In this example, the PHY-scaled stream phase offset measured at the first intermediate-network-node switch  3   a  is indicated by PSPO 1 , the PHY-scaled stream phase offset measured at the second intermediate-network-node switch  3   b  is indicated by PSPO 2 , the PHY-scaled stream phase offset measured at the third intermediate-network-node switch  3   c  is indicated by PSPO 3 , the PHY-scaled stream phase offset measured at the sink node switch  2  is indicated by PSPO-S. In this example, CPO 0  transmitted to the first intermediate-network-node switch  3   a  will have an initial value of zero. At the output of intermediate-network-node switch  3   a , the CPO in the intermediate-network-node data stream will have a calculated CPO (CPO 1 ) that reflects the sum of 0 (the initial CPO value) and PSPO 1 . At the output of intermediate-network-node switch  3   b  the CPO in the intermediate-network-node data stream will have a calculated CPO (CPO 2 ) that is PSPO 1 +PSPO 2 . At the output of intermediate-network-node switch  3   c  the CPO in the intermediate-network-node data stream will have a calculated CPO (CPO 3 ) that is PSPO 1 +PSPO 2 +PSPO 3 . The corresponding CPO-S calculated at sink node  2  will be PSPO 1 +PSPO 2 , +PSPO 3 +PSPO-S. Thereby the CPO-S will be the accumulation of all of the relative PPM offsets in the path and will indicate the relative parts per million of the entire path (RPPMpath). 
     In one example, the ppm offset of the local reference clock in the source node is PPMsrc from nominal. The measured rate of the CBR client at the source node is encoded into a periodic CRR. The nominal period between CRR is Tcrr, as measured by the local reference clock at source node  1 . The CPOR of the carrier stream is nominally generated once per period of Tcpor as measured by the local reference clock of the source node  1 . CPOR may be initialized to 0, or some other predetermined value. 
     In this example, respective ones of intermediate-network-node switches  3   a - 3   c  demultiplex respective ones of the data streams (e.g., each of the data streams) into a set of n CBR carrier streams, one for respective ones of CBR signals and monitors respective ones of the carrier streams for the presence of the CPOR. The PSPO, which is common to all CBR carriers sharing the same PHY link, is then summed into the incoming CPOR by CPOR update logic  14 . Because CPORs are generated more frequently than PSPO (Tps&gt;Tcpor), there are more CPOR values than PSPO values over any given time period. In one example, once a PSPO has been summed into the CPOR of a CBR carrier, subsequent CPOR of that CBR carrier will be left unmodified until a new PSPO is available. In another example, once a PSPO has been summed into the CPOR of a CBR carrier, a subsequent CPOR of that CBR carrier will be updated using the same PSPO until a new PSPO is available. 
     In one example the calculated CPO can be either a positive number (when the measured bit count is greater than the PHY-scaled stream nominal bit count value) or a negative number (when the measured bit count is less than the PHY-scaled stream nominal bit count value). In one example, when the measured bit count is greater than the PHY-scaled stream nominal bit count value, CPOR update logic  14  calculates CPO by adding the PSPO to P-CPO; and when the measured bit count is less than the PHY-scaled stream nominal bit count value, CPOR update logic  14  calculates CPO by adding the calculated PSPO (a negative value) to CPO-P. 
     For clarity and brevity, as well as to avoid unnecessary or unhelpful cluttering, obfuscating, obscuring, obstructing, or occluding features or elements of an example of the disclosure, certain intricacies and details, which are known generally to artisans of ordinary skill in related technologies, have been omitted or discussed in less than exhaustive detail. Any such omissions or discussions are deemed unnecessary for describing examples of the disclosure, and/or not particularly relevant to achieving an understanding of significant features, functions, elements and/or aspects of the examples of the disclosure described herein. 
     In the specification and figures herein, examples implementations are thus described in relation to the claims set forth below. The present disclosure is not limited to such examples however, and the specification and figures herein are thus intended to enlighten artisans of ordinary skill in technologies related to integrated circuits in relation to appreciation, apprehension and suggestion of alternatives and equivalents thereto.