Patent Publication Number: US-2002000582-A1

Title: Semiconductor device including voltage down converter allowing tuning in short period of time and reduction of chip area

Description:
BACKGROUND OF THE INVENTION  
       [0001] 1. Field of the Invention  
       [0002] The present invention relates to a semiconductor device and, more specifically, to a semiconductor device mounting an internal power supply generating circuit.  
       [0003] 2. Description of the Background Art  
       [0004] Recently, as the semiconductor devices have been developed to operate at ever lower voltages, driving of a transistor in a semiconductor device with a power supply voltage lower than the power supply voltage applied from outside of the semiconductor device has been strongly desired. The requirement of reduced power consumption of the semiconductor device and of higher reliability of the transistor are underlying factors of such trend.  
       [0005] In a dynamic random access memory (DRAM), it is also an important problem to ensure reliability of a dielectric film of a capacitor holding charges in a memory cell.  
       [0006] Upper limit of an internal power supply voltage of a semiconductor device has been made lower generation by generation due to the requirements described above, resulting in ever larger difference from the power supply voltage used in the system. Thus, a voltage down converter is provided, which is a circuit for down converting the power supply voltage used in the system to generate a stable internal power supply voltage. The voltage down converter closes a gap between the power supply voltage used in the system and the internal power supply voltage used in the semiconductor device, so as to ensure the reliability inside the semiconductor device.  
       [0007]FIG. 15 is a circuit diagram representing a configuration of a typical conventional voltage down converter.  
       [0008] Referring to FIG. 15, the voltage down converter includes a reference potential generating circuit  300  for generating a reference potential as a reference for an internal power supply potential generated in a chip, and a voltage converting unit  302  receiving a reference potential Vref generated by reference potential generating circuit  300  and generating an internal power supply potential int.Vcc.  
       [0009] Voltage converting unit  302  includes a differential amplifier circuit  304  comparing levels of reference potential Vref and internal power supply potential int.Vcc, and a P channel MOS transistor  306  receiving an output of differential amplifier circuit  304  at its gate, and connected between an external power supply node receiving an external power supply potential Ext.Vcc and an internal power supply node outputting the internal power supply potential int.Vcc.  
       [0010] Differential amplifier circuit  304  has a negative input node connected to the reference potential Vref and a positive input node receiving the internal power supply potential int.Vcc. Differential amplifier circuit  304  controls switching of P channel MOS transistor  306  to stabilize the internal power supply potential int.Vcc to the same level as the reference potential Vref.  
       [0011]FIG. 16 is a circuit diagram representing a configuration of reference potential generating circuit  300  of FIG. 15.  
       [0012] Referring to FIG. 16, reference potential generating circuit  300  includes a constant current source  312  and a resistance circuit  313  connected in series between a power supply node to which the external power supply potential Ext.Vcc is applied and the ground node. A connection node between constant current source  312  and resistance circuit  313  is an output node of reference potential generating circuit  300 , from which reference potential Vref is output.  
       [0013] Reference potential generating circuit  300  further includes a capacitor  324  for stabilizing potential, connected between the output node outputting the reference potential Vref and the ground node.  
       [0014] Resistance circuit  313  includes P channel MOS transistors  314  to  322  connected in series between the output node outputting the reference potential Vref and the ground node. P channel MOS transistors  314  to  322  receive at their gates the ground potential.  
       [0015] Resistance circuit  313  further includes a switch circuit  326  connected in parallel with P channel MOS transistor  314 , a switch circuit  328  connected in parallel with P channel MOS transistor  316 , a switch circuit  330  connected in parallel with P channel MOS transistor  318 , and a switch circuit  332  connected in parallel with P channel MOS transistor  320 .  
       [0016] As a constant current applied from constant current source  212  flows against the channel resistances of P channel MOS transistors  314  to  322 , reference potential Vref is determined. In order to prevent fluctuation of reference potential Vref due to the variation of channel resistances of P channel MOS transistors, switch circuits  316  to  332  include fuse elements. The configuration allows adjustment of reference potential Vref by changing the state of conduction of each fuse element. By switching the switch circuits between the conduction and non-conduction states in accordance with the setting of the fuses, tuning to 2 4  different values, that is, 16 values is possible.  
       [0017] Determination of fuse setting will be described in the following.  
       [0018]FIG. 17 is a circuit diagram showing detailed configuration of switch circuit  326 .  
       [0019] Referring to FIG. 17, switch circuit  326  includes a pad  390  receiving a tuning signal TSIGn, an inverter  392  receiving and inverting the tuning signal TSIGn, an N channel MOS transistor  396  connected in series between nodes NAn and NBn, a fuse element  398 , and a P channel MOS transistor  394  connected in parallel with N channel MOS transistor  396  and receiving tuning signal TSIGn.  
       [0020] An output of inverter  392  is applied to the gate of N channel MOS transistor  396 . Node NAn is connected to the source of P channel MOS transistor  314  of FIG. 15, and node NBn is connected to the drain of P channel MOS transistor  314 .  
       [0021] In a default state where the fuse is not blown off and the tuning signal TSIGn is at an L (low) level, nodes NAn and NBn of switch circuits  326  are conducted. When the tuning signal TSIGn is set to an H (high) level, conduction is lost between nodes NAn and NBn, and thus a state is established which is equivalent to the state where fuse element  398  is blown off.  
       [0022] Switch circuits  328  and  330  shown in FIG. 16 have similar structures as switch circuit  326 , and therefore, description thereof is not repeated.  
       [0023]FIG. 18 is a circuit diagram representing a configuration of switch circuit  332  shown in FIG. 16.  
       [0024] Referring to FIG. 18, switch circuit  332  includes a P channel MOS transistor  402  having its gate connected to the ground node and its source coupled to the external power supply potential Ext.Vcc, an N channel MOS transistor  406  having its gate connected to the ground node and connected between node N 31  and the ground node, a fuse element  404  connected between the drain of P channel MOS transistor  402  and node N 31 , N channel MOS transistors  420  and  422  connected in parallel between node N 31  and the ground node, and an inverter  410  having an input node connected to node N 31 .  
       [0025] A signal BIAS of which level is constant is applied to the gate of N channel MOS transistor  420 , and an output of inverter  410  is applied to the gate of N channel MOS transistor  422 .  
       [0026] Switch circuit  332  further includes a pad  408  receiving the tuning signal TSIGn, an OR circuit  412  receiving the tuning signal TSIGn and an output of inverter  410 , an inverter  414  receiving and inverting an output of OR circuit  412 , and a P channel MOS transistor  418  and an N channel MOS transistor  416  connected in parallel between nodes NAn and NBn.  
       [0027] An output of OR circuit  412  is applied to the gate of N channel MOS transistor  416 , and an output of inverter  414  is applied to the gate of P channel MOS transistor  418 .  
       [0028] In the default state where tuning signal TSIGn is at the L level and fuse element  404  is not blown off, conduction is not established between nodes NAn and NBn in switch circuit  332 . Node NAn of switch circuit  332  is connected to the source of P channel MOS transistor  320  of FIG. 15, and node NBn is connected to the drain of P channel MOS transistor  320 .  
       [0029] A constant current flows through N channel MOS transistor  420  because of the potential BIAS. When fuse element  404  is blown off, the potential of node N 31  attains to the L level, and in response, conduction is established between nodes NAn and NBn. When the tuning signal TSIGn is set to the H level, conduction is established.between nodes NAn and NBn, attaining an equivalent state as the state where fuse  404  is blown off.  
       [0030]FIG. 19 is a block diagram illustrating a configuration of a conventional boosted power supply circuit generating a boosted potential provided in a semiconductor device.  
       [0031] Referring to FIG. 19, in the conventional semiconductor device, when the reference potential Vref to be applied to the voltage down converter is to be tuned, the boosted power supply circuit is inactivated. More specifically, a ring oscillator  332  generating fundamental clock of the boosted power supply circuit stops its operation in response to the tuning signal, so that application of a clock signal φ 0  to a frequency division counter  336  is stopped, and input of clock signals φ and φ to a charge pump  344  is stopped. Thus, operation of charge pump  334  is stopped.  
       [0032] Frequency division counter  336  divides frequency of clock signal φ 0  output from the ring oscillator to provide a clock signal φ for the charge pump  344 . A lower bit of a counter value, however, is generally not used. Such a counter is often not used while an operation related to setting of the fuses is in progress.  
       [0033] As described above, at the time of a test, a control signal is applied to establish a state equivalent to a state where the fuse is blown off, and internal power supply potential at that time is monitored, so that an optimal combination of fuse elements to be blown off can be found. Generally, the fuse element is blown off by a laser beam, using a test apparatus used exclusively therefor.  
       [0034] When such a laser trimming method is adopted, the fuse element is protected by a guard ring or the like so that polysilicon or the like blown off by the laser beam does not affect other circuitry. Therefore, it is impossible in a semiconductor device having a laser trimming type redundancy circuit to attain uniform shrink around the fuse element.  
       [0035] Shrink refers to use of design data of a semiconductor device designed in accordance with the design rule which is dominant presently or in the past with magnification modified to satisfy a corresponding new design rule to address development of new, more miniaturized semiconductor process. Shrink allows production of the semiconductor device with smaller chip area while making use of the design assets of the past.  
       [0036] As the design rule develops, the ratio of the chip area occupied by the fuse elements which cannot be shrunk attains relatively high, which presents a problem to be solved.  
       [0037] Further, the signal input pad provided in the semiconductor device also requires handling different from other regions at the time of shrinkage. Generally, in order to tune the reference potential Vref, signal input pads for receiving tuning signals TSIG 1  to TSIG 4  as inputs and a monitor pad for monitoring the reference potential Vref or the internal power supply potential int.Vcc are necessary, which means that the number of pads is disadvantageously large.  
       SUMMARY OF THE INVENTION  
       [0038] An object of the present invention is to provide a semiconductor device which can reduce the number of pads necessary for tuning the reference potential Vref, the chip area and the time necessary for tuning.  
       [0039] Briefly stated, the present invention provides a semiconductor device including a tuning signal generating circuit and a reference potential generating circuit. The tuning signal generating circuit outputs, in accordance with time change of a control signal of a single bit, a tuning signal having a plurality of signal bits. The reference potential generating circuit receives a first power supply potential and a second power supply potential lower than the first power supply potential, and outputs a reference potential in accordance with the tuning signal.  
       [0040] Therefore, an advantage of the present invention is that the number of pads necessary for tuning the reference potential Vref can be reduced and hence, the chip area of the semiconductor device can be reduced.  
       [0041] The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.  
     
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
     [0042]FIG. 1 is a schematic block diagram representing a configuration of a semiconductor device  1  in accordance with a first embodiment of the present invention.  
     [0043]FIG. 2 is a circuit diagram representing a configuration of the voltage down converter  38  shown in FIG. 1.  
     [0044]FIG. 3 is a circuit diagram representing a configuration of a reference potential generating circuit  52  shown in FIG. 2.  
     [0045]FIG. 4 is a circuit diagram representing a configuration of a tuning circuit  70  shown in FIG. 3.  
     [0046]FIG. 5 is a circuit diagram representing a configuration of a tuning circuit  64  of FIG. 3.  
     [0047]FIG. 6 is a circuit diagram representing a configuration of a voltage down converter  130 .  
     [0048]FIG. 7 is an illustration of a switch circuit  18  for externally outputting tuning signals TSIG 1  to TSIG 4 .  
     [0049]FIG. 8 is a diagram of waveforms related to the operation of voltage down converter  130  in accordance with a second embodiment.  
     [0050]FIG. 9 is a circuit diagram representing a configuration of a tuning circuit  200 .  
     [0051]FIG. 10 is a circuit diagram representing a configuration of a tuning circuit  240 .  
     [0052]FIG. 11 is a diagram of waveforms related to the operation of the semiconductor device in accordance with a third embodiment.  
     [0053]FIG. 12 is a schematic diagram representing a configuration of a refresh address counter  25   a.    
     [0054]FIG. 13 is a circuit diagram representing a configuration using a counter of a boosted power supply generating circuit.  
     [0055]FIG. 14 is a circuit diagram representing a configuration of a voltage down converter  38   a.    
     [0056]FIG. 15 is a circuit diagram representing a conventional general voltage down converter.  
     [0057]FIG. 16 is a circuit diagram representing a configuration of a reference potential generating circuit  300  of FIG. 15.  
     [0058]FIG. 17 is a circuit diagram representing a detailed configuration of switch circuit  326 .  
     [0059]FIG. 18 is a circuit diagram representing a configuration of a switch circuit  332  of FIG. 16.  
     [0060]FIG. 19 is a block diagram representing a configuration of a boosted power supply circuit generating a boosted potential provided in a conventional semiconductor device. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
     [0061] In the following, embodiments of the present invention will be described in detail with reference to the drawings. Throughout the figures, the same reference character denote the same or corresponding portions.  
     [0062] First Embodiment  
     [0063]FIG. 1 is a schematic block diagram representing a semiconductor device  1  in accordance with a first embodiment of the present invention.  
     [0064] Referring to FIG. 1, semiconductor device  1  includes control signal input terminals  2  to  6  receiving control signals ext./RAS, ext./CAS and ext./WE, respectively, an address input terminal group  8 , an input terminal group  14  receiving as an input data signal Din, an output terminal group  16  outputting data signal Dout, a ground terminal  12  receiving a ground potential Vss, a power supply terminal  10  receiving a power supply potential Ext.Vcc, and an input terminal  13  receiving as an input a test control clock signal TCLK.  
     [0065] Semiconductor device  1  further includes a clock generating circuit  22 , a row and column address buffer  24 , a row decoder  26 , a column decoder  28 , a sense amplifier +input/output control circuit  30 , a memory cell array  32 , a gate circuit  18 , a data input buffer  20  and a data output buffer  34 .  
     [0066] Clock generating circuit  22  generates a control clock corresponding to a prescribed operation mode in accordance with an external row address strobe signal ext./RAS and an external column address strobe signal ext./CAS externally applied through control signal input terminals  2  and  4 , and controls overall operation of the semiconductor device.  
     [0067] Row and column address buffer  24  applies an address signal generated from externally applied address signals AO to Ai (i is a natural number) to row decoder  26  and column decoder  28 .  
     [0068] A memory cell array  32  designated by row decoder  26  and column decoder  28  communicates data to and from the outside through sense amplifier+input/output control circuit  30  and data input buffer  20  or data output buffer  34 , through input terminal Din or output terminal Dout.  
     [0069] Semiconductor device  1  further includes a boosted power supply circuit  36  boosting the external power supply potential Ext.Vcc to generate an internal boosted potential Vpp, and a voltage down converter  38  receiving external power supply potential Ext.Vcc, and down converting the received potential to a voltage in accordance with the setting of control clock signal TCLK to generate an internal power supply potential int.Vcc. The boosted power supply potential Vpp will be a driving potential of a word line driven by row decoder  26 . Internal power supply potential int.Vcc is applied to internal circuitry including memory cell array  32 .  
     [0070] Semiconductor device  1  further includes a refresh address counter  25  generating and applying to row decoder  26  a refresh address in a prescribed period in a refresh mode, under control by clock generating circuit  22 .  
     [0071] Semiconductor device  1  shown in FIG. 1 is a representative example, and the present invention is also applicable to a synchronous semiconductor memory device (SDRAM), for example. Further, the present invention is also applicable to various semiconductor devices provided that a voltage down converter is included.  
     [0072]FIG. 2 is a circuit diagram representing a configuration of voltage down converter  38  shown in FIG. 1.  
     [0073] Referring to FIG. 2, voltage down converter  38  includes a reference potential generating circuit  52  generating a reference potential Vref as a reference for internal power supply potential int.Vcc, and a voltage converting unit  54  receiving reference potential Vref and outputting internal power supply potential int.Vcc.  
     [0074] Voltage converting unit  54  includes a differential amplifier  56  receiving and comparing reference potential Vref and internal power supply potential int.Vcc, and a P channel MOS transistor  58  receiving at its gate an output of differential amplifier circuit  56  and connected between a power supply node receiving external power supply potential Ext.Vcc and a power supply node receiving internal power supply potential int.Vcc.  
     [0075]FIG. 3 is a circuit diagram representing a configuration of reference potential generating circuit  52  shown in FIG. 2.  
     [0076] Referring to FIG. 3, reference potential generating circuit  52  includes a counter  62  outputting tuning signals TSIG 1  to TSIG 4  in accordance with a control clock signal TCLK, a constant current source  72  connected between a power supply node receiving the external power supply potential Ext.Vcc and a node N 1 , a resistance circuit  73  connected between node N 1  and the ground node, and a capacitor  84  for stabilizing potential connected between node N 1  and the ground node. Reference potential Vref is output from node N 1 .  
     [0077] Reference potential generating circuit  52  further includes a tuning circuit  64  establishing conduction between nodes N 1  and N 2  at the time of tuning in response to tuning signal TSIG 1 , a tuning circuit  56  connecting nodes N 2  and N 3  at the time of tuning in response to tuning signal TSIG 2 , a tuning circuit  68  connecting nodes N 3  and N 4  at the time of tuning in response to tuning signal TSIG 3 , and a tuning circuit  70  connecting nodes N 4  and N 5  at the time of tuning in response to tuning signal TSIG 4 .  
     [0078] Resistance circuit  73  includes a P channel MOS transistor  74  connected between nodes N 1  and N 2  and having its gate connected to the ground node, a P channel MOS transistor  76  connected between nodes N 2  and N 3  and having its gate connected to the ground node, a P channel MOS transistor  78  connected between nodes N 3  and N 4  and having its gate connected to the ground node, a P channel MOS transistor  80  connected between nodes N 4  and N 5  and having its gate connected to the ground node, and a P channel MOS transistor  82  having its source connected to node N 5  and drain and gate connected to the ground node.  
     [0079]FIG. 4 is a circuit diagram representing tuning circuit  70  shown in FIG. 3.  
     [0080] Referring to FIG. 4, tuning circuit  70  includes an inverter  92  receiving and inverting tuning signal TSIGn, an N channel MOS transistor  96  and a fuse element  98  connected in series between nodes NAn and NBn, and a P channel MOS transistor  94  connected in parallel with N channel MOS transistor  96  and having its gate connected to tuning signal TSIGn. To the gate of N channel MOS transistor  96 , an output of inverter  92  is applied.  
     [0081] Tuning signal TSIGn corresponds to tuning signal TSIG 4  of FIG. 3. Node NAn corresponds to node N 4  of FIG. 3, and node NBn corresponds to node N 5  of FIG. 3.  
     [0082] In a state where the fuse is not yet blown off and the tuning signal is at the L level, nodes NAn and NBn are conducted in tuning circuit  70 . Namely, this circuit is rendered conductive in the default state.  
     [0083]FIG. 5 is a circuit diagram representing a configuration of tuning circuit  64  of FIG. 4.  
     [0084] Referring to FIG. 5, tuning circuit  64  includes a P channel MOS transistor  102  having its gate connected to the ground node and its source coupled to external power supply potential Ext.Vcc, a fuse element  104  connected between the drain of P channel MOS transistor  102  and a node N 6 , an N channel MOS transistor  106  having its gate and source connected to the ground node and its drain connected to node N 6 , N channel MOS transistors  120  and  122  connected in parallel between node N 6  and the ground node, and an inverter  110  having an input node connected to node N 6 . The signal BIAS is applied to the gate of N channel MOS transistor  120 , and an output of inverter  110  is applied to the gate of N channel MOS transistor  122 .  
     [0085] Tuning circuit  64  further includes an OR circuit  122  receiving tuning signal TSIGn and an output of inverter  110 , an inverter  114  receiving and inverting an output of OR circuit  112 , and an N channel MOS transistor  116  and a P channel MOS transistor  118  connected in parallel between nodes NAn and NBn. An output of OR circuit  112  is applied to the gate of N channel MOS transistor  116 , and an output of inverter  114  is applied to the gate of P channel MOS transistor  118 .  
     [0086] Tuning signal TSIGn of FIG. 5 corresponds to tuning signal TSIG 1  of FIG. 3, and nodes NAn and NBn correspond to nodes N 1  and N 2  of FIG. 3, respectively.  
     [0087] The tuning circuits  66  and  68  shown in FIG. 3 have similar structure as tuning circuit  64 , and therefore description thereof is not repeated. It is noted, however, that in tuning circuit  66 , tuning signal TSIGn of FIG. 5 corresponds to tuning signal TSIG 2 , node NAn corresponds to node N 2  and node NBn corresponds to node N 3 .  
     [0088] In tuning circuit  68  of FIG. 3, tuning signal TSIGn and nodes NAn and NBn of FIG. 5 correspond to tuning signal TSIG 3  and nodes N 3  and N 4 , respectively.  
     [0089] The tuning circuits  64  to  68  are circuits in which conduction between nodes NAn and NBn is lost when the tuning signals TSIG 1  to TSIG 3  are at the L level, that is, in the default state.  
     [0090] As tuning circuits  64 ,  66  and  68  are implemented as circuits which are non-conductive in the default state and tuning circuit  70  is implemented as a circuit which is conductive in the default state, it becomes possible to set channel resistance value before laser trimming at a central value of the tuning range. This is because the channel resistance values of P channel MOS transistors  74 ,  76 ,  78  and  80  are set to satisfy the ratio of (1:2:4:8). By the tuning operation in which tuning signals TSIG 1  to TSIG 4  are changed, sum of channel resistance values can be increased/decreased, so that the potential of reference potential Vref can be set to a desired value.  
     [0091] Again referring to FIG. 3, the process of tuning the reference potential Vref will be described.  
     [0092] First, control clock signal TCLK is input from the outside of the device to counter  62 . Control clock signal TCLK is a pulse signal, and receiving control clock signal TCLK, counter  62  operates.  
     [0093] Every time the pulse of control clock signal TCLK is input, combination of tuning signals TSIG 1  to TSIG 4  changes to any of sixteen different combinations. More specifically, when the signals TSIG 1  to TSIG 4  are all at the L level, tuning circuits  64 ,  66  and  68  are rendered non-conductive, and tuning circuit  70  is rendered conductive. When the tuning signals TSIG 1  to SIG 4  are all at the H level, tuning circuits  64 ,  66  and  68  are rendered conductive and tuning circuit  70  is rendered non-conductive.  
     [0094] In this manner, as counter output value counts from 0000 to 1111, it is possible to realize sixteen different combinations of tuning signals TSIG 1  to TSIG 4 , and therefore it is possible to adjust resistance value of resistance circuit  73  to sixteen different values.  
     [0095] Determination of the optimal tuning condition is made by monitoring either the reference potential Vref or the internal power supply potential int.Vcc which is an output of the voltage down converter.  
     [0096] In the conventional circuit structure, four pads are provided for controlling the tuning signals TSIG 1  to TSIG 4  in accordance with input signals from outside of the chip.  
     [0097] In the semiconductor device  1  in accordance with the first embodiment, tuning signals TSIG 1  to TSIG 4  can be changed by the input of the control clock signal TCLK through an input pad for inputting the control clock signal TCLK, and therefore it is possible to reduce the number of pads and hence to reduce the chip area of the semiconductor device.  
     [0098] Second Embodiment  
     [0099] In the second embodiment, a voltage down converter  130  is provided in place of the voltage down converter  38  shown in FIG. 2.  
     [0100]FIG. 6 is a circuit diagram representing the configuration of voltage down converter  130 .  
     [0101] Referring to FIG. 6, voltage down converter  130  includes an oscillator  134  outputting the control clock signal TCLK in accordance with a tuning mode signal VTUNE and a comparison signal VCOMP, a reference potential generating circuit  136  receiving the control clock signal TCLK and outputting the reference potential Vref, and a voltage converting unit  132  receiving the reference potential Vref and generating internal power supply potential int.Vcc and the comparison signal VCOMP. The tuning mode signal VTUNE is set to the H level when the reference potential Vref is to be tuned.  
     [0102] Reference potential generating circuit  136  includes a counter  152  outputting tuning signals TSIG 1  to TSIG 4  in accordance with the control clock signal TCLK, an inverter  159  receiving and inverting the signal TSIG 4 , a constant current source  162  connected between a power supply node to which the external power supply potential Ext.Vcc is applied and a node Nil, a resistance circuit  163  connected between node N 11  and the ground node, and a capacitor  174  for stabilizing potential connected between N 11  and the ground node. Reference potential Vref is output from node N 11 .  
     [0103] Reference potential generating circuit  136  further includes a tuning circuit  154  establishing conduction between nodes N 11  and N 12  at the time of tuning in response to tuning signal TSIG 1 , a tuning circuit  156  connecting nodes N 12  and N 13  at the time of tuning in response to tuning signal TSIG 2 , a tuning circuit  158  connecting nodes N 13  and N 14  at the time of tuning in response to tuning signal TSIG 3 , and a tuning circuit  160  connecting nodes N 14  and N 15  at the time of tuning in response to an output of inverter  159 .  
     [0104] Resistance circuit  163  includes a P channel MOS transistor  164  connected between nodes N 11  and N 12  and having its gate connected to the ground node, a P channel MOS transistor  166  connected between nodes N 12  and N 13  and having its gate connected to the ground node, a P channel MOS transistor  168  connected between nodes N 13  and N 14  and having its gate connected to the ground node, a P channel MOS transistor  170  connected between nodes N 14  and N 15  and having its gate connected to the ground node, and a P channel MOS transistor  172  having its source connected to node N 15  and its drain and gate connected to the ground node.  
     [0105] Voltage converting unit  132  includes a selection switch  138  outputting either the reference potential Ext.Vref applied in the tuning mode from the outside or the internal power supply potential int.Vcc in accordance with the tuning mode signal VTUBE, a differential amplifier circuit  140  receiving at a negative input node the reference potential Vref and at the positive input node an output of selection switch circuit  138 , a selection switch circuit  142  providing the output of differential amplifier circuit  140  either to an output node A or an output node B in accordance with a tuning mode signal VTUNE, and a P channel MOS transistor  144  having its gate connected to the output node B of selection switch circuit  142  and connected between the power supply node to which the external power supply potential Ext.Vcc is applied and the power supply node to which the internal power supply potential int.Vcc is applied.  
     [0106] In selection switches  138  and  142 , in the normal operation, the tuning mode signal VTUNE is set to L level and the B side is used. At this time, voltage converting unit  132  outputs the internal power supply potential int.Vcc in accordance with the reference potential Vref. When tuning is to be performed, tuning mode signal VTUNE is set to the H level, and the switch is switched to the A side in selection switch circuit  138  and  142 . Differential amplifier  140  is used as a comparing circuit comparing the tuning level.  
     [0107] A circuit such as shown in FIG. 5 which is rendered non-conductive in the default state is used as tuning circuits  154 ,  156  and  158 . A circuit such as shown in FIG. 4 which is rendered conductive in the default state is used as tuning circuit  160 .  
     [0108] The tuning signal TSIG 4  output from counter  152  is inverted by inverter  159 , and inverted signal/TSIG 4  is applied to tuning circuit  160 . Accordingly, when tuning signals TSIG 1  to TSIG 4  are all at the L level, tuning circuits  154 ,  156 ,  158  and  160  are rendered non-conductive, and resistance value at the opposing ends of resistance circuit  163  is maximized. As a constant current is caused to flow through resistance circuit  163  by constant current source  162 , reference potential Vref assumes the maximum value at this time. When tuning signals TSIG 1  to TSIG 4  are all at the H level, tuning circuits  154 ,  156 ,  158  and  160  are rendered conductive, so that resistance value at the opposing ends of resistance circuit  163  is minimized and reference potential Vref assumes the minimum value.  
     [0109] When the tuning mode signal VTUNE is at the H level, the A side of the switch is used in selection switch circuits  138  and  142 . At this time, the external reference potential Ext.Vref applied from the outside is set to that potential level which is to be set as the reference potential Vref. Differential amplifier  140  compares difference of input two potentials, amplifies the difference and provides the result as the comparison signal VCOMP. When the reference potential Vref is higher than the external reference potential Ext.Vref, the comparison signal VCOMP attains to the L level, and when the reference potential Vref becomes lower than the external reference potential Ext.Vref, the comparison signal VCOMP attains to the H level. When the tuning signals TSIG 1  to TSIG 4  at this time are output externally, it can be recognized how the fuses contained in tuning circuits  154  to  160  are to be set.  
     [0110] The values of tuning signals TSIG 1  to TSIG 4  at this time are output utilizing a pad through which data output signal Dout is output.  
     [0111]FIG. 7 is an illustration representing switching circuit  18  for externally outputting tuning signals TSIG 1  to TSIG 4 .  
     [0112] Referring to FIG. 7, switching circuit  182  includes a selection switch  184  outputting either the tuning signal TSIG 1  or the internal data signal IDP 1  as output signal Doutl, a selection switch circuit  186  outputting either the tuning signal TSIG 2  or the internal data signal IDP 2  as output signal Dout 2 , a selection switch circuit  188  outputting either the tuning signal TSIG 3  or the internal data signal IDP 3  as output signal Dout 3 , and a selection switch circuit  190  outputting either the tuning signal TSIG 4  or the internal data signal IDP 4  as output signal Dout 4 .  
     [0113] Tuning signals TSIG 1  to TSIG 4  are signals output from counter  152  of FIG. 6, and IDP 1  to IDP 4  are internal data signals input to data output buffer  34  in FIG. 1. Switching circuit  182  selectively outputs either one of the two signals input to output buffer  34  of FIG. 1.  
     [0114] In a normal operation, that is, when comparison signal VCOMP is at L level, B side of selection switch circuits  184  to  190  is used. Thus internal data signals IDP 1  to IDP 4  are output as data output signals Dout 1  to Dout 4 . When the comparison signal VCOMP attains to the H level, selection switch circuits  184  to  190  are switched to the A side. At that time, tuning signals TSIG 1  to TSIG 4  are output as data output signals Dout 1  to Dout 4 .  
     [0115]FIG. 8 is a diagram of waveforms representing the operation of voltage down converter  130  in accordance with the second embodiment.  
     [0116] Referring to FIGS. 6 and 8, at time t 1 , tuning mode signal VTUNE is set from L to H level. In response, oscillator  134  starts output of the control clock signal TCLK. After time t 2 , counter  152  starts counting in synchronization with a rising edge of control clock signal TCLK. The signal TSIG of FIG. 8 represents a 4 bit signal including tuning signals TSIG 1  to TSIG 4 , where tuning signal TSIG 1  is the least. significant bit and the tuning signal TSIG 4  is the most significant bit. At time points t 3 , t 4 , t 5 , t 6  and t 7 , the value of tuning signal TSIG is counted from 0 to 5, in response to the rise of the control clock signal TCLK. As the resistance value of resistance circuit  163  decreases in accordance with the count value, reference potential Vref gradually lowers.  
     [0117] At time t 7 , when the reference potential Vref generated inside becomes lower than the externally applied external reference potential Ext.Vref, the output of differential amplifier circuit  140  attains to the H level and the comparison signal VCOMP attains to the H level. In response, oscillation of oscillator  134  stops, and counter circuit  152  stops counting up. More specifically, the tuning signals TSIG 1  to TSIG 4  at the time point when comparison signal VCOMP attains to H level are maintained.  
     [0118] By externally outputting the signals by using such a circuit as shown in FIG. 7, it is possible to recognize how the fuses contained in tuning circuits  154  to  160  are to be set. When the fuses are blown off using a laser trimming apparatus in accordance with the output data, a desired reference potential can be obtained even in the normal operation.  
     [0119] When the tuning signal is output by switching after the end of tuning, using the circuit of FIG. 7, the data output pin can be set to the normal operation state while the tuning condition is determined. It is desired that tuning is performed under the same condition as the actual operation. When the data output pin is set in the normal operation state, undesirable influence of fluctuation in power consumed by the voltage down converter or the like on tuning can be prevented.  
     [0120] In the conventional semiconductor device, tuning signals TSIG 1  to TSIG 4  are applied from the outside of the semiconductor device and the tuning level is compared by a tester. Therefore, a total of five pads, that is, input pads for tuning signals TSIG 1  to TSIG 4  and a pad for monitoring the reference potential Vref are necessary. Further, the tuning level was measured and determined by a tester connected to the semiconductor device. As the tester monitors the reference potential Vref while varying the tuning signals TSIG 1  to TSIG 4 , determination has been a time consuming operation.  
     [0121] By contrast, in the semiconductor device in accordance with the second embodiment, tuning is possible using only one pad for reference potential Ext.Vref applied from the outside as a reference, and therefore it is possible to reduce the number of pads provided for the semiconductor device. Further, it is possible to compare the external reference potential Ext.Vref and the reference potential Vref, determine tuning condition when the reference potentials match, and thereafter output the result of determination to the data output pin. The tuning signal may be output not to the data output pin but to any other control pin on the semiconductor device. In the tuning mode, tuning condition is determined by operating a counter in the semiconductor device, and therefore a separate tester or the like for comparing voltage is unnecessary. Therefore, the time for testing required for tuning can be reduced.  
     [0122] Third Embodiment  
     [0123] The periphery of a fuse element which can be blown off by a laser beam cannot be uniformly shrunk. As the design rule develops, the ratio of the fuse element occupying the chip area attains relatively high, which is a problem to be solved.  
     [0124] U.S. Pat. No. 5,631,862 proposes, as means to solve this problem, an insulation film braking type electric fuse. Such an electric fuse is referred to as an antifuse. When such a fuse is used, it is unnecessary to use an apparatus exclusively provided for blowing off, and the fuse can be blown off during wafer test. Therefore, time and cost for testing can be reduced.  
     [0125] In the semiconductor device in accordance with the third embodiment, the electric fuse is used in the structure of tuning circuits  154  to  160  of the voltage down converter  130  of the semiconductor device shown in the second embodiment. An antifuse which breaks an insulating layer between electrodes by applying a high voltage is used as the electric fuse.  
     [0126] In the third embodiment, a tuning circuit  200  is used in place of tuning circuits  154 ,  156  and  158  shown in FIG. 6. Further, a tuning circuit  240  is used in place of tuning circuit  160 .  
     [0127]FIG. 9 is a circuit diagram representing a combination of tuning circuit  200 .  
     [0128] Referring to FIG. 9, tuning circuit  200  includes a latch  202  taking and holding a tuning signal TSIGn at an edge of control clock signal TCLK, an AND circuit  204  receiving tuning mode signal VTUNE and an output of latch  202 , a latch circuit  206  outputting a signal FR which corresponds to information set in an antifuse, a latch control unit  208  controlling latch circuit  206 , an NOR circuit  210  receiving an output of AND circuit  204  and the signal FR, and a switch circuit  212  receiving an output of NOR circuit  210  and controlling connection between nodes NAn and NBn.  
     [0129] Latch control unit  208  includes an N channel MOS transistor  226  connected between a node N 23  and the ground node and receiving at its gate a reset signal RST, N channel MOS transistors  228  and  230  connected in series between node N 23  and the ground node, an N channel MOS transistor  232  connected between nodes N 23  and N 24  and having its gate coupled to external power supply potential Ext.Vcc, an antifuse  234  connected between nodes N 24  and CGND, and an N channel MOS transistor  222  connected between nodes N 22  and N 23  and receiving at its gate the signal DV 2 E.  
     [0130] Latch control unit  208  further includes an AND circuit  224  receiving an output of latch circuit  202  and a signal VCUT. An output of AND circuit  224  is applied to the gate of N channel MOS transistor  228 . The signal FR, which is an output of latch circuit  206 , is applied to the gate of N channel MOS transistor  230 .  
     [0131] Latch circuit  206  includes P channel MOS transistors  214  and  218  having their sources coupled together to external power supply potential Ext.Vcc and their drains connected together to node N 2   1 , a P channel MOS transistor  216  connected between nodes N 21  and N 22  and having its gate connected to the ground node, and an inverter  220  having an input node connected to node N 22 . P channel MOS transistor  214  has its gate connected to the ground node. Inverter  220  outputs the signal FR. The signal FR is applied to the gate of P channel MOS transistor  218 .  
     [0132] Switch circuit  212  includes an inverter  236  receiving and inverting an output of NOR circuit  210 , and a P channel MOS transistor  238  and an N channel MOS transistor  240  connected in parallel between nodes NAn and NBn. An output of NOR circuit  210  is applied to the gate of P channel MOS transistor  238 . An output of inverter  236  is applied to the gate of N channel MOS transistor  240 .  
     [0133] In tuning circuit  200 , when antifuse  234  is not blown off in the normal operation, conduction is not established between nodes NAn and NBn, as the default state. When antifuse  234  is blown off and conduction between nodes N 24  and CGND is established in the normal operation, switch circuit  214  establishes conduction between nodes NAn and NBn.  
     [0134]FIG. 10 is a circuit diagram representing a configuration of tuning circuit  240 . Referring to FIG. 10, tuning circuit  240  includes the configuration of tuning circuit  200  shown in FIG. 9, with switch circuit  242  used in place of switch circuit  212 .  
     [0135] Switch circuit  242  includes an inverter  246  receiving and inverting an output of NOR circuit  210 , an N channel MOS transistor  248  receiving at its gate an output of NOR circuit  210  and connected between nodes NAn and NBn, and a P channel MOS transistor  250  receiving at its gate an output of inverter  246  and connected between nodes NAn and NBn.  
     [0136] Except this point, the configuration is the same as that of tuning circuit  200  shown in FIG. 9. Therefore, description thereof is not repeated.  
     [0137] In tuning circuit  240 , nodes NAn and NBn are conducted in the default state where antifuse  234  is not blown off.  
     [0138]FIG. 14 is a diagram of waveforms representing the operation of the semiconductor device in accordance with the third embodiment.  
     [0139] Referring to FIGS. 9 and 11, from time t 1  to t 7 , control signal TCLK is generated in the tuning mode, the level of internally generated reference potential Vref is compared with external reference potential Ext.Vref and the level is determined.  
     [0140] In this state, the potential of node N 22  is at H level because of P channel MOS transistors  214  and  216 , and therefore, the signal FR is at the L level. When tuning ends, the tuning mode signal VTUNE falls to the L level.  
     [0141] Thereafter, at time t 8 , an operation of blowing off the antifuse starts. First, reset signal RST is activated to the H level, node N 23  is set to the L level, and through the N channel MOS transistor  222  which is conductive, node N 22  attains to the L level. In response, the signal FR attains to the H level.  
     [0142] Thereafter, the signal VCUT for blowing off the antifuse is activated. At this time, when the corresponding tuning signal TSIGn is held in the state of H level, then H level is applied to the gate of N channel MOS transistor  228 , and N channel MOS transistors  228  and  230  are both rendered conductive. Thereafter, even after reset signal RST falls at time t 9 , node N 23  is kept at the L level, and hence the signal FR is kept at the H level.  
     [0143] Then, at time t 10 , in order to blow off antifuse  234 , a high voltage of about 10 V is applied to node CGND, which is in normal operation, at the ground potential. Then, the high voltage is applied only to that antifuse of which corresponding tuning signal TSIG is at the H level.  
     [0144] When insulation of antifuse  234  is lost, node N 23  rises from the L level to the H level, and in response, the signal FR attains to the L level. Therefore, N channel MOS transistor  230  is rendered non-conductive, and therefore flow of current from node CGND to the ground node stops.  
     [0145] Thereafter, at time t 11 , the potential of node CGND is lowered to OV and, in response, the potential of node N 3  attains to the L level. Therefore, the signal FR returns to the H level. Blowing of the fuse ends, and the signal VCUT falls to the L level.  
     [0146] After time t 11 , as the corresponding antifuse has been blown off, the reference potential Vref set by the tuning signals TSIG 1  to TSIG 4  will be continuously output.  
     [0147] As the voltage level is tuned in this manner, it is unnecessary to monitor the reference potential Vref and the tuning signals TSIG 1  to TSIG 4 . Therefore, the number of pads of the semiconductor device can be reduced. Further, as the antifuse is used, provision of a guard ring or the like is unnecessary, and hence the area of the fuse can be reduced. Further, the laser trimming apparatus is also unnecessary, and the step of tuning can be incorporated in the step of monitoring by the tester. As the tuning determination and the trimming can be performed collectively in the semiconductor device, the time for testing can be reduced.  
     [0148] Fourth Embodiment  
     [0149] Generally, a DRAM includes a refresh address counter. The DRAM has an operation mode in which a row address is applied from the refresh address counter contained therein.  
     [0150] In the fourth embodiment, the refresh address counter is used at the time of tuning. In the fourth embodiment, in place of refresh address counter  25  of semiconductor device  1  shown in FIG. 1, a refresh address counter  25   a  is provided.  
     [0151]FIG. 12 is a schematic diagram representing configuration of the refresh address counter  25   a.    
     [0152] Referring to FIG. 12, refresh address counter  25   a  includes a selection switch circuit  262  applying either a refresh signal or the control clock signal TCLK to refresh address counter  264  in response to tuning mode signal VTUNE. More specifically, refresh address counter  264  is used both at the time of refreshing and at the time of tuning.  
     [0153] In the normal operation, that is, when tuning mode signal VTUNE is at the L level, refresh address counter  264  operates as an n bit counter, receiving the refresh signal. Here, n represents the number of bits of the row address.  
     [0154] When the tuning mode signal VTUNE is at the H level, refresh address counter  264  counts the control clock signal TCLK. Refresh address counter  264  operates as a 4 bit counter. Least significant 4 bits of the output from refresh address counter  264  are taken out as tuning signals TSIG 1  to TSIG 4 , and output to the reference potential generating circuit.  
     [0155] In the tuning mode, generally, the refresh counter does not operate. Therefore, the refresh counter can be used for tuning. Further, a counter circuit other than the refresh counter is included in the DRAM. For example, a counter circuit is used at a portion for inputting a signal to a charge pump circuit in the boosted power supply circuit, as described with reference to FIG. 19.  
     [0156]FIG. 13 is a circuit diagram representing a configuration in which the counter of the boosted power supply generating circuit is used.  
     [0157] Referring to FIG. 13, the boosted power supply circuit includes a ring oscillator  272  which is activated in a normal mode where tuning mode signal VTUNE is at the L level and outputting clock signal φ 0 , a selection switch circuit  274  selecting and outputting either the clock signal φ 0  or the control clock signal TCLK in response to the tuning mode signal VTUNE, a frequency division counter  276  counting an output of selection switch circuit  274 , an inverter  278  receiving and inverting the tuning mode signal VTUNE, an AND circuit  280  receiving the most significant bit of frequency division counter  276  and an output of inverter  278  and outputting a clock signal φ, an inverter  282  receiving an output of AND circuit  280  and outputting the clock signal/φ, and a charge pump  284  generating a high potential by clock signals φ and/φ.  
     [0158] Here, least significant  4  bits of frequency division circuit  276  are normally not used. In the tuning mode, these bits are provided as 4-bit outputs of a frequency division counter counting the control clock signal TCLK, providing tuning signals TSIG 1  to TSIG 4  for the reference potential generating circuit.  
     [0159] As the counter circuit not used at the time of tuning reference potential Vref is switched and used, it becomes unnecessary to provide a separate counter circuit for tuning the reference potential Vref. Therefore, the number of circuit elements can be reduced and the area of the semiconductor device can be reduced.  
     [0160] Fifth Embodiment  
     [0161] In the fifth embodiment, in the structure of semiconductor device  1  shown in FIG. 1, a voltage down converter  38   a  is provided in place of voltage down converter  38 .  
     [0162]FIG. 14 is a circuit diagram representing configuration of voltage down converter  38   a.    
     [0163] Referring to FIG. 14, voltage down converter  38  includes a reference potential generating circuit  52  generating the reference potential Vref, a voltage converting unit  54  receiving the reference potential Vref, and converting external power supply potential Ext.Vcc to a corresponding internal power supply potential int.Vcc, and a potential stabilizing circuit  290  connected to an output of reference potential generating circuit  52 . Voltage converting unit  54  includes a differential amplifier circuit  56  receiving at a positive input the internal power supply potential int.Vcc and receiving at a negative input the reference potential Vref, and a P channel MOS transistor  58  receiving at its gate an output of differential amplifier circuit  56  and connected between a power supply node to which external power supply potential Ext.Vcc is applied and a power supply node to which internal power supply potential int.Vcc is applied.  
     [0164] Voltage stabilizing circuit  290  includes a P channel MOS transistor  292  and a capacitor  294  connected in series between an output node of reference potential generating circuit  52  outputting the reference potential Vref and the ground node. The tuning mode signal VTUNE is applied to the gate of P channel MOS transistor  292 .  
     [0165] Reference potential generating circuit  52 , which handles very small current, is thus very sensitive to noise. Therefore, in the normal operation state where the semiconductor device operates at a high speed and a large current flows, a capacitor  294  which is a stabilizing capacitance, is necessary to prevent coupling noise from adjacent interconnections.  
     [0166] At the time of tuning the level of the reference potential Vref, however, the time becomes necessary to charge the capacitor  294 , which is the stabilizing capacitor, for changing the level of reference potential Vref. This means that the period of the control clock signal TCLK must be made longer, resulting in longer test time. In the tuning mode, it is possible to stop operations of unnecessary circuits, so as to prevent consumption of large current by the semiconductor device, and hence capacitor  294  is unnecessary. Therefore, by the configuration shown in FIG. 14, in the tuning mode, that is, when the tuning mode signal VTUNE attains to the H level, the capacitor  294  can be disconnected from the reference potential generating circuit  52 . Accordingly, the time for charging capacitor  294  becomes unnecessary, and the level of the reference potential Vref can be changed quickly. Therefore, the period of the control clock signal TCLK can be made shorter, and hence the test time can be made shorter.  
     [0167] Although the present invention has been described and illustrated in detail, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the spirit and scope of the present invention being limited only by the terms of the appended claims.