Patent Publication Number: US-8526265-B2

Title: Three state word line driver for a DRAM memory device

Description:
FIELD OF THE INVENTION 
     The present invention relates to a word line driver that provides an output signal having three different states. 
     RELATED ART 
     U.S. Pat. No. 7,277,315 to Yuan et al., describes a method and circuit to reduce power consumption of DRAM word line drivers by using a dual driver control circuit to control the build-up of a word line voltage from the VDD supply voltage to higher voltage VPP. A first charge pump generates the voltage VPP 1  and a second charge pump generates the voltage VPP, wherein VPP&gt;VPP 1 ≧VDD. The voltage VPP 1  is initially driven on the word line driver from the first charge pump. After the voltage on the word line driver reaches VPP 1 , then the voltage VPP is driven on the word line driver from the second charge pump. In this manner, the dual driver control circuit generates the word line voltage level VPP in two stages. Because VPP 1  is less than VPP, the pumping efficiency of both charge pumps is higher than the efficiency of a single charge pump that generates VPP. 
     It would be desirable to have word line driver circuitry that further improves the efficiency and reliability of a DRAM array. 
     SUMMARY 
     A tri-state word line driver for a memory system having one or more memory banks selectively applies one of three word line driver voltages to a corresponding word line. The word line is coupled to a corresponding row of memory cells. More specifically, the word line is coupled to the gates of access transistors of the memory cells in the row. 
     The tri-state word line driver applies a first word line driver voltage (V−) to the word line when the corresponding memory bank is in an active state, and the row associated with the word line is selected for access. The first word line driver voltage is selected to turn on the access transistors of the memory cells coupled to the word line. 
     The tri-state word line driver applies a second word line driver voltage (V 1 +) to the word line when the corresponding memory bank is in an active state, and the row associated with the word line is not selected for access. The second word line driver voltage is selected to prevent charge leakage through the access transistors of the memory cells coupled to the word line, taking into consideration the fact that bit lines coupled to the access transistors are pulled to full supply voltages (e.g., V DD  and ground supply voltages). 
     The tri-state word line driver applies a third word line driver voltage (V 2 +) to the word line when the corresponding memory bank is in an inactive state. The third word line driver voltage is selected to prevent charge leakage through the access transistors of the memory cells coupled to the word line, taking into consideration the fact that bit lines coupled to the access transistors are maintained at an intermediate pre-charge voltage (e.g., V DD /2) when the memory bank is in the inactive state. 
     The second word line driver voltage biases the access transistors coupled to the word line into a deeper off state than the third word line driver voltage. That is, the second word line driver voltage turns off the access transistors harder than the third word line driver voltage. As a result, the largest off state gate drive only exists within memory banks in the active state. Memory banks in the inactive state (which typically outnumber memory banks in the active state) advantageously exhibit a smaller off state gate drive (and therefore less voltage stress). As a result, the tri-state word line driver enhances the reliability of the memory cell access transistors, as well as the reliability of transistors located within the tri-state word line driver. In addition, the reduced off state gate drive associated with the third word line driver voltage advantageously improves memory cell retention time by reducing gate-induced-drain-leakage (GIDL). 
     The present invention will be more fully understood in view of the following description and drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a block diagram of a multi-bank memory system in accordance with one embodiment of the present invention. 
         FIG. 2  is a circuit diagram of a portion of a memory bank of the multi-bank memory of  FIG. 1 , including word line drivers, in accordance with one embodiment of the present invention. 
         FIG. 3  is a block diagram of a control circuit that generates bank select signals, which control the voltage applied to the word line drivers of  FIG. 2 , in accordance with one embodiment of the present invention. 
         FIG. 4  is a waveform diagram illustrating signals associated with the word line drivers of  FIG. 2 , in accordance with one embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION 
       FIG. 1  is a block diagram of a multi-bank memory system  100  in accordance with one embodiment of the present invention. System  100  includes a plurality of memory banks M 0 -M N , each of which is coupled to address bus  111 , data bus  112  and control bus  113 . Memory banks M 0 -M N  are individually accessed in response a bank address transmitted on address bus  111 . More specifically, each of memory banks M 0 -M N  is assigned a unique bank address. Each of the memory banks M 0 -M N  compares its assigned bank address with the bank address provided on address bus  111 . Upon detecting that its assigned bank address matches the bank address on address bus  111 , a memory bank will implement an access specified by signals on the control bus  113 . These accesses may include read, write and refresh accesses, which are well known to those of ordinary skill in the art. A memory bank that is currently implementing such an access will hereinafter be referred to as an active memory bank. Memory banks that are not currently implementing an access will hereinafter be referred to as inactive memory banks. 
     As illustrated in  FIG. 1 , voltage sources  101 ,  102  and  103  provide corresponding word line driver supply voltages, V 1 +, V 2 + and V− to each of the memory banks M 0 -M N . As described in more detail below, word line driver circuits within memory banks M 0 -M N  are selectively coupled to receive either word line driver supply voltage V 1 + or word line driver supply voltage V 2 +, depending upon whether the associated memory bank is currently an active memory bank or an inactive memory bank. 
       FIG. 2  is a circuit diagram of a portion of memory bank M 0  in accordance with one embodiment of the present invention. The illustrated portion of memory bank M 0  includes word line driver supply circuit  201 , word line drivers  211 - 212 , row decoder circuitry  213 - 214 , memory bank decoder  215  and memory cell array  220 . Memory cell array  220  includes memory cells MC 1  and MC 2 , wherein memory cell MC 1  is located in a first row of array  220  and memory cell MC 2  is located in a second row of array  220 . Memory cells MC 1  and MC 2  are located in the same column of array  220 , and therefore share a common bit line BL[n]. Although only two rows and one column of memory cell array  220  are illustrated in  FIG. 2 , it is understood that memory cell array  220  typically includes many more rows and columns of memory cells (wherein each row includes a plurality of memory cells coupled to a common word line, and each column includes a plurality of memory cells coupled to a common bit line.) 
     Each row of memory cell array  220  is coupled to a corresponding word line. Thus, memory cell MC 1  is coupled to word line WL[i], and memory cell MC 2  is coupled to word line WL[j]. In the described examples, memory cells MC 1  and MC 2  are DRAM cells, which include PMOS access transistors AT 1  and AT 2 , respectively, and charge storage structures (e.g., capacitors) CS 1  and CS 2 , respectively. 
     Each word line is coupled to a corresponding word line driver. Thus, word line WL[i] is coupled to word line driver  211  and word line WL[j] is coupled to word line driver  212 . Word line drivers  211  and  212  include series-connected inverters I 1 -I 2  and I 3 -I 4 , respectively. The inputs of inverters I 2  and I 4  are coupled to outputs of row decoder circuits  213  and  214 , respectively. The outputs of inverters I 2  and I 4  are coupled to the inputs of inverters I 1  and I 3 , respectively. The outputs of inverters I 1  and I 3  are coupled to word lines WL[i] and WL[j], respectively. Although each of the word line drivers  211 - 212  includes two series-connected inverters in the described examples, it is understood that the word line drivers  211 - 212  may have other numbers of series-connected inverters (including a single inverter), in other embodiments. 
     Inverters I 1 -I 4  include PMOS driver transistors P 1 -P 4 , respectively, and NMOS driver transistors N 1 -N 4 , respectively. The sources of PMOS driver transistors P 1 -P 4  are coupled to a first word line driver supply terminal  204 , which is configured to receive a word line driver voltage V W+  from word line driver supply circuit  201 . The sources of NMOS driver transistors N 1 -N 4  are coupled to a second word line driver supply terminal  205 , which is configured to receive a word line driver voltage V. In the described embodiments, the word line driver voltage V W−  is equal to the word line driver supply voltage V− (See,  FIG. 1 ). The word line driver voltage V− may be a negative voltage or the ground supply voltage (0 Volts). The word line driver supply voltage V− is selected such that the PMOS access transistors AT 1 -AT 2  are adequately turned on when the voltage V− is applied to the gates of these PMOS access transistors during read, write and refresh accesses. 
     Word line driver supply circuit  201  includes PMOS transistors  202 - 203 . PMOS transistor  203  has a source coupled to receive the word line driver supply voltage V 1 +, a drain coupled to word line driver supply terminal  204 , and a gate coupled to receive an active-low bank select signal BS#. PMOS transistor  202  has a source coupled to receive the word line driver supply voltage V 2 +, a drain coupled to word line driver supply terminal  204 , and a gate coupled to receive an active-high bank select signal BS. 
       FIG. 3  is a block diagram illustrating bank decoder  215  in more detail. As described below, bank decoder  215  generates the bank select signals BS and BS# in accordance with one embodiment of the present invention. Bank decoder  215  includes decoder logic  301 , level shifter  302  and inverter  303 . Decoder logic  301  stores a unique bank address BA 0  assigned to memory bank M 0 . Decoder logic  301  receives the bank address (B_ADDR) associated with a current access of memory system  100  on address bus  111 . If decoder logic  301  determines that bank addresses BA 0  and B_ADDR match, decoder logic  301  activates a MATCH signal to a logic ‘1’ state, thereby indicating that the current access of memory system  100  targets memory bank M 0 . Conversely, if decoder logic  301  determines that the bank address B_ADDR on address bus  111  does not match the local bank address BA 0 , then decoder logic de-activates the MATCH signal to a logic ‘0’ state, thereby indicating that the current access of memory system  100  does not target memory bank M 0 . A MATCH signal having a logic ‘1’ state therefore indicates that memory bank M 0  is an active memory bank, while a MATCH signal having a logic ‘0’ state indicates that memory bank M 0  is an inactive memory bank. 
     Level shifter  302  receives the MATCH signal from decoder logic  301 , and in response, performs a voltage level shifting function on the MATCH signal. More specifically, when the MATCH signal is activated to a logic ‘1’ state, level shifter  302  provides a bank select voltage BS voltage equal to the word line driver supply voltage V 1 +. Under these conditions, inverter  303  provides a complementary bank select voltage BS# equal to the ground supply voltage (0 Volts). 
     Conversely, when the MATCH signal is de-activated to a logic ‘0’ state, level shifter  302  provides a bank select voltage BS voltage equal to the ground supply voltage. Under these conditions, inverter  303  provides a complementary bank select voltage BS# equal to the word line driver supply voltage V 1 +. 
     Thus, the bank select signal BS will have a logic ‘1’ state (and the bank select signal BS# will have a logic ‘0’ state) when memory bank M 0  is an active memory bank. Conversely, the bank select signal BS will have a logic ‘0’ state (and the bank select signal BS# will have a logic ‘1’ state) when memory bank M 0  is an inactive memory bank. 
     The operation of the portion of memory bank M 0  illustrated in  FIG. 2  will now be described.  FIG. 4  is a waveform diagram  400  illustrating the operation of memory bank M 0 , in accordance with one embodiment of the present invention. 
     Memory bank M 0  is an inactive memory bank between time T 0  and T 1  in  FIG. 4 . When memory bank M 0  is an inactive memory bank, the bank select signals BS and BS# have logic ‘0’ and logic ‘1’ states, respectively. Under these conditions, PMOS transistor  202  is turned on (conductive) and PMOS transistor  203  is turned off (non-conductive). As a result, the word line driver supply voltage V 2 + is routed through PMOS transistor  202  to word line driver supply terminal  204 . Under these conditions, the word line driver voltage V W+  is equal to V 2 +. The word line driver supply voltage V 2 + is less than the word line driver supply voltage V 1 +. For example, the word line driver supply voltage V 2 + may be equal to the VDD supply voltage, while the word line driver supply voltage V 1 + may be equal to VDD+V T , wherein V T  is the threshold voltage of the access transistors AT 1 -AT 2 . The exact values of the word line driver supply voltages V 1 + and V 2 + are selected in view of the design considerations described below. 
     While memory bank M 0  is inactive, row decoders  213  and  214  provide logic ‘1’ values to word line drivers  211  and  212 , respectively. Under these conditions, word lines WL[i] and WL[j] are pulled up to the word line driver supply voltage V 2 + through turned on PMOS transistors P 1  and P 3 , respectively. The word line driver supply voltage V 2 + is sufficiently high (positive) to turn off PMOS access transistors AT 1  and AT 2  in memory cells MC 1  and MC 2 , thereby retaining any charges previously stored in charge storage structures CS 1  and CS 2 . 
     When memory bank M 0  is inactive, bit line BL[n] is maintained at a pre-charge voltage level of V DD /2, thereby limiting the maximum voltage difference between bit line BL[n] and charge storage structures CS 1 -CS 2  to V DD /2. The word line driver supply voltage V 2 + is selected to be high enough to prevent charge leakage between bit line BL[n] and charge storage structures CS 1 -CS 2 , taking into consideration that the maximum voltage difference between the bit line BL[n] and the charge storage structures CS 1 -CS 2  is limited to V DD /2. 
     As will become apparent in view of the following description, the word line driver voltage V W+  is relatively low (i.e., V W+ =V 2 +) when memory bank M 0  is an inactive memory bank. As a result, the access transistors AT 1 -AT 2  in memory cells MC 1 -MC 2  and the transistors P 1 -P 4  and N 1 -N 4  in word line drivers  211 - 212  experience a relatively low voltage stress when memory bank M 0  is an inactive memory bank. The reliability of the memory cell access transistors AT 1 -AT 2  and the word line driver transistors P 1 -P 4  and N 1 -N 4  is thereby enhanced. In addition, applying the relatively low voltage V 2 + to the word lines of an inactive memory bank advantageously reduces the gate-induced-drain-leakage (GIDL) through the memory cell access transistors, thereby improving the memory cell retention time. A majority of the memory banks M 0 -M N  will be in the inactive state most of the time. 
     At time T 1 , memory bank M 0  starts the transition from an inactive memory bank to an active memory bank, in response to a new read/write/refresh access. When memory bank M 0  becomes an active memory bank, the bank select signals BS and BS# transition to logic ‘1’ and logic ‘0’ states, respectively. Under these conditions, PMOS transistor  203  is turned on (conductive) and PMOS transistor  202  is turned off (non-conductive). As a result, the word line driver supply voltage V 1 + is routed through PMOS transistor  203  to word line driver supply terminal  204 , and is therefore provided as the word line driver voltage V W+ . 
     Also at time T 1 , row decoders  213 - 214  decode the row address of the read/write/refresh access that caused memory bank M 0  to enter the active state. In the described example, this row address specifies word line WL[i], such that row decoder  213  provides a logic ‘0’ output, and row decoder  214  provides a logic ‘1’ output. The logic ‘0’ output provided by row decoder  213  causes transistors P 2  and N 1  turn on (and transistors P 1  and N 2  to turn off), such that the word line driver voltage V− is applied to the selected word line WL[i] (through transistor N 1 ). The word line driver voltage V− applied to word line WL[i] turns on PMOS access transistor AT 1 , thereby coupling charge storage structure CS 1  to bit line BL[n]. Data is read from charge storage structure CS 1  to bit line BL[n] if the access is a read or refresh access. Conversely, data is written to charge storage structure CS 1  from bit line BL[n] if the access is a write access. During these accesses, the bit line BL[n] will either be pulled up to the V DD  supply voltage, or pulled down to the V SS  (ground) supply voltage (depending on the state of the data being read or written). 
     The logic ‘1’ output provided by row decoder  214  causes transistors P 3  and N 4  turn on (and transistors P 4  and N 3  to turn off), such that the word line driver supply voltage V 1 + is applied to the non-selected word line WL[j]. The word line driver supply voltage V 1 + is sufficiently high (positive) to turn off PMOS access transistor AT 2  in memory cell MC 2 , thereby retaining any charge previously stored in charge storage structure CS 2 . 
     As described above, when memory bank M 0  is in the active state, the bit line BL[n] may be pulled up to the V DD  supply voltage or pulled down to the V SS  supply voltage. The maximum voltage difference between the bit line BL[n] and the charge storage structure CS 2  in a non-selected row is therefore equal to V DD . The word line driver supply voltage V 1 + is selected to be high enough to prevent charge leakage between bit line BL[n] and the charge storage structure CS 2  in the non-selected row, taking into consideration that the maximum voltage difference between the bit line BL[n] and the charge storage structure CS 2  is V DD . In view of this requirement, the word line driver supply voltage V 1 + is selected to be greater than the word line driver supply voltage V 2 + in the described embodiments. As a result, word line driver supply voltage V 1 + turns off access transistor AT 2  harder than word line driver supply voltage V 2 + would turn off this access transistor AT 2 . As a result, memory cell MC 2  is less susceptible to the disturb conditions introduced by the voltages present on bit line BL[n]. 
     As illustrated in  FIG. 4 , the selected word line WL[i] is pulled down (through NMOS transistor N 1 ) from an initial voltage of V 2 + to a final voltage of V− when memory bank M 0  becomes an active memory bank. This word line voltage transition is relatively small (compared to a voltage transition from V 1 + to V−). As a result, the maximum drain-to-source voltage of the NMOS transistor N 1  that pulls the selected word line WL[i] down to V− is relatively small, thereby advantageously reducing hot-carrier injection into the gate dielectric of this NMOS transistor N 1 . 
     As also illustrated in  FIG. 4 , the non-selected word line WL[j] is pulled up from an initial voltage of V 2 + to a voltage of V 1 + when memory bank M 0  becomes an active memory bank. As described above, the higher voltage V 1 + advantageously reduces charge leakage within the memory cell MC 2  in the non-selected row. 
     Although the invention has been described in connection with several embodiments, it is understood that this invention is not limited to the embodiments disclosed, but is capable of various modifications, which would be apparent to a person skilled in the art. For example, although the present invention has been described in connection with a multi-bank memory system, it is understood that the present invention could also be applied to a single-bank memory system. Moreover, although the invention has been described in connection with memory cells having PMOS access transistors, it is understood that these memory cells could be modified to have NMOS access transistors in other embodiments. In this embodiment, the word line driver supply voltages would have to be modified in accordance with the teachings of the present specification. In addition, although the described embodiments assume that all accesses are initiated on a system bus (represented by address bus  111 , data bus  112 , and control bus  113 ) it is understood that in other embodiments, refresh accesses may be initiated internally within the individual memory banks. In these embodiments, a memory bank implementing an internally initiated refresh access will still be treated as an active memory bank. Accordingly, the present invention is limited only by the following claims.