Patent Publication Number: US-6668358-B2

Title: Dual threshold gate array or standard cell power saving library circuits

Description:
FIELD OF THE INVENTION 
     This invention relates to Complimentary Metal Oxide Semiconductor (CMOS) Application Specific Integrated Circuit (ASIC) libraries, and in particular to reduction of power dissipated in such libraries where multiple threshold options are available for the Field Effect Transistors (FETs) used in the libraries. 
     BACKGROUND OF THE INVENTION 
     The history of computer and related electronic circuitry has seen a constant movement to faster and lower powered circuits. In computers of the early 1950&#39;s, vacuum tubes were used as the switching elements. Vacuum tubes operated by heating a cathode with a filament, causing thermionic emission of electrons, which were then attracted to an anode biased positively relative to the cathode. Applying a low voltage on a control grid placed between the cathode and the anode could halt flow of the electrons. The heating requirement caused large amounts of static power to be dissipated. Static power is power dissipated independent of switching activity, and occurs whether the vacuum tube is in a conducting or a nonconducting state, or both. 
     Vacuum tubes were replaced in time by circuits comprising bipolar transistors. The dominant logic circuit families were Transistor Transistor Logic (TTL) and Emitter Coupled Logic (ECL). Both of these types of circuits also dissipated static power. ECL, in particular, was known for high power requirements. Computers implemented in TTL or ECL logic families dominated the 1960 to 1990 time frame. Increasingly elaborate cooling techniques were created to cool the computers of that era. Computers such as the IBM 3081 used pistons pressed against the semiconductor logic chips to remove heat from the chips. The heat was then transferred from the pistons to a heat sink. The heat sink was water-cooled. 
     CMOS logic circuits came into wide use in computer systems in the 1990s. CMOS in the 1990s was characterized by relatively high supply voltage. 5.0 volts, 3.3 volts, 2.5 volts, and 1.8 volts were commonly used for the supply voltage. These supply voltages allowed for the FET thresholds to be relatively high while still supporting relatively high performance. The amount of current an FET conducts, and therefore the performance, is strongly dependent on the supply voltage minus the FET threshold voltage. If the supply voltage is reduced, it is advantageous, therefore, to also reduce the FET threshold. 
     FETs with high thresholds have negligible leakage when the FET is “off”, that is, the FET gate voltage is set such that the FET does not conduct. In the “off” case of an N-channel FET (NFET), the gate voltage would be set at a low voltage, usually ground. In the case of a P-channel FET (PFET), the gate voltage would be set at a high voltage, usually the supply voltage. CMOS logic circuits constructed of such FETs dissipate very little static power. Properly designed CMOS logic circuits have either a conducting path to ground through an NFET network, or a conducting path to the supply voltage through a PFET network. During a switch, CMOS circuits do have a brief time when both the NFET network and the PFET network are partially conducting. Current flowing from the supply voltage to ground during this time is called shoot-through current. Except for power associated with shoot-through current, power in such CMOS logic is almost totally dynamic power, which charges and discharges capacitances of gates, wiring, and parasitic device capacitances. Dynamic power in CMOS is usually calculated with the equation, P=½*C*V*V*f, where P is the dynamic power, C is the amount of capacitance switched, V is the supply voltage, and f is the frequency at which the capacitance is switched. 
     It is immediately apparent from the equation that lowering the supply voltage can dramatically reduce the dynamic power. Supply voltage has indeed been lowered over the years, from 5 volts to 3.3 volts to 2.5 volts, to 1.8 volts. Although in a given technology, performance will degrade with reduced supply voltage, performance has been maintained or improved by advancing the FET technology. Some of the advances have included making the FET channels shorter, making the FET gate oxides thinner, and reducing the FET thresholds. 
     A problem has recently arisen as decreasing supply voltage approaches 1.0 volt. Maintaining performance has required reduction of FET thresholds to the point that, even when the device is “off”, substantial subthreshold leakage occurs. This leakage causes power dissipation that has become a significant percentage of the total power of a logic chip. 
     A number of CMOS processes have begun to offer multiple, usually two, FET threshold options. This is called Dual VT technology. FET threshold voltage is called VT. The FETs with higher thresholds (high VT) are slower than the FETs with lower thresholds (low VT). FET threshold differences can be accomplished in several ways, such as varying the doping in the silicon, or lengthening the channels of FETS where a higher threshold is desired. Previous work has led to methods that use Dual VT technology in custom integrated circuits to reduce the subthreshold leakage. “Static Power Optimization of Deep Submicron CMOS Circuits for Dual VT Technology”, by Qi Wang and Sarma B. K. Vrudula, of the Center for Low Power Electronics, ECE Department, University of Arizona, Tucson, Ariz. 85721, describes an algorithm for assignment of an FET with a higher VT in places where performance will not be compromised. Another previous effort applicable in custom circuit design is “An Enhanced Dual Threshold Voltage Leakage Control Technique for a Sub-500PS 64-bit Adder”, by Lizhi Charlie Zhong and Hongjing Zou. Yet a third previous effort applicable in custom circuit design is “A Static Power Model for Architects”, by J. Adam Butts and Gurindar S. Sohi. 
     All of the above efforts apply higher VT FET devices in a custom circuit design to reduce static power. 
     Much of the logic used in today&#39;s computers and related equipment use ASICs. An ASIC design system provides a designer with a predesigned set, or library, of logic blocks. The designer builds the desired logic function on the chip by selecting from the library and specifying the interconnection of the blocks. The design system further provides rules governing valid interconnection topologies, delay computation, system timing, and other control or checking information needed to guarantee functionality of the logic function of the chip. Since all of the blocks in the library are predesigned, the ASIC designer has no ability to change the circuit design of any of the blocks. Therefore, the algorithmic selection of FET thresholds available to the custom circuit designers as referenced above is not available to the ASIC designer. 
     Therefore, a need exists to give the ASIC designer the capability to reduce static power in a Dual VT technology ASIC design system by providing appropriate Dual VT circuit logic blocks in the ASIC library, and a method to select and use those blocks effectively. 
     SUMMARY OF THE INVENTION 
     A principal object of the present invention is to reduce the average subthreshold leakage current on ASIC chips by providing a set of low leakage logic blocks that are functionally equivalent to other logic blocks that are faster, but which have significant leakage currents, and substituting the low leakage logic blocks where timing margin permits. 
     In brief, a method and a set of low leakage logic blocks are provided. The method initializes all instantiations of logic blocks on the chip to the faster, but leaky, versions of the logic blocks. All delays on the chip are computed. All timing margins (slacks) are computed for all inputs and outputs of each instantiation. 
     Each inverter logic block is then considered for replacement by a low leakage version of the inverter function. The replacement will be done and made permanent if timing margin permits. 
     After all inverters on the chip are considered, two input NANDs, and, optionally, two input NORs, are considered. In this part of the method, an attempt is made to replace each faster, but more leaky, usage of two input NANDs and NORs with a low leakage version. Functionally equivalent inputs can be swapped based on timing considerations. If a replacement violates timing constraints, the original logic block is restored, along with the input assignments and timings that existed prior to the replacement. 
     After all two input NANDs and NORs have been considered, the method makes an attempt to replace to replace each faster, but more leaky, usage of three input NANDs and, optionally, three input NORs, with a low leakage version of that logic function. Again, functionally equivalent inputs can be swapped based on timing considerations. If a replacement violates timing constraints, the original logic block is restored, along with the input assignments and timings that existed prior to the replacement. 
     The low leakage version of the inverters, NANDs, and NORs discussed above are designed with some of the FET devices implemented with high threshold devices in a dual VT technology. Alternatively, some of the FET devices can be designed with channel lengths longer than a minimum length specified for a particular technology. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIGS. 1A-1E show conventional CMOS NAND, NOR, and inverter circuits that use only low VT FET devices. Low VT FET devices are identified with hash marks in these, and subsequent, figures. 
     FIGS. 2A-2D show a conventional two input NAND circuit that uses only low VT FET devices, with devices subject to subthreshold leakage identified for different input voltage cases. 
     FIGS. 3A-3E show CMOS NAND, NOR, and inverter circuits using high VT devices in a preferred embodiment of the invention. 
     FIG. 4A shows another embodiment of the invention applied to a two input NAND. 
     FIG. 4B shows another embodiment of the invention applied to a two input NAND. 
     FIG. 4C shows another embodiment of the invention applied to a two input NOR. 
     FIG. 4D shows another embodiment of the invention applied to a two input NOR. 
     FIGS. 5A-5C together show a flow chart that details the method by which low VT blocks are replaced by high VT blocks. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     In the following discussion, a “0” logic level is substantially ground voltage and will be referred to as “0”. Similarly, a “1” logic level is substantially at VDD voltage, and will be referred to as VDD. 
     Having reference now to the figures, FIGS. 1A-1E show conventional, low VT, CMOS logic blocks for NAND and NOR circuits. Blocks having up to three inputs are shown, however, more inputs can be implemented. In particular, in CMOS, practical NAND circuits can have more than three inputs. CMOS NOR circuits are generally limited to two or three inputs for performance reasons, although CMOS NOR circuits with more than three inputs can be built. 
     FIG. 1A shows a conventional CMOS three input NAND circuit, constructed with low VT FET devices, comprising three NFET devices, N 104 , N 105 , and N 106 , and complimentary PFET devices, P 101 , P 102 , and P 103 . NFET N 104  and PFET P 101  have gates electrically coupled to an input A; NFET N 105  and PFET P 102  have gates electrically coupled to an input B; NFET N 106  and PFET P 103  have gates electrically coupled to an input C. The NFETs are stacked in a conventional manner such that if all of the NFETs are conducting, a low resistance path from an output node, OUT, to ground is established. If any of the NFETs are nonconducting, the low resistance path to ground will be broken, and the complimentary PFET will create a low resistance path from the VDD supply to the output node, OUT. Nodes  108  and  109  are intermediate nodes in the stack of NFETs. 
     FIG. 1B shows a conventional two input NAND, comprising NFETs N 114  and N 115  and their corresponding complimentary PFETs, P 111  and P 112 . FIG. 1C shows a conventional inverter, comprising NFET N 124  and PFET P 121 . FIG. 1D shows a conventional three input NOR, comprising stacked PFETs P 134 , P 135 , and P 136 , and their corresponding complimentary NFETs N 131 , N 132 , and N 133 . FIG. 1E shows a conventional two input NOR, comprising stacked PFETs P 144  and P 145 , and their complimentary NFETs N 141  and N 142 . 
     CMOS technology has seen a steady improvement in performance over time. FET channel lengths are becoming shorter. FET gate oxides are becoming thinner. Performance of the FET devices is very dependent upon the channel lengths, the gate oxides, and gate to source voltage minus a FET device threshold voltage. In normal CMOS logic design, logic signals are at the lower supply (normally ground) for logic “low”, and at the positive supply (normally VDD) for logic “high”. Supply voltage (VDD) used with the CMOS logic has been dropping dramatically over time from 5.0 volts, to 3.3 volts, to 2.5 volts, and is currently approaching 1.0 volt. Since logic inputs are applied to FET gates in normal CMOS designs, the gate to source voltage is lower as VDD supply voltage is lowered. Technology developers have lowered FET threshold voltages to make the gate to drain minus the FET threshold (VT) as high as possible to enhance performance. FET thresholds have been lowered to the point that significant subthreshold leakage occurs. That is, even though the gate voltage is at ground for an NFET, or when the gate voltage is at VDD for a PFET, a significant current can still flow through the FET. Therefore, the circuits depicted in FIGS. 1A-1E will exhibit significant leakage. 
     FIGS. 2A-2D show leakage current, ILEAK, under the four input logic states possible for a two input NAND. ILEAK is drawn next to the leaking FET in all cases. 
     FIG. 2A shows a two input NAND wherein a “0” is applied to a gate on NFET  204 , a gate on NFET  205 , and their corresponding complimentary PFETs, P 201  and P 202 . Both NFET N 204  and NFET N 205  in the stack should be “off”, however a small leakage current flows through NFETs N 204  and N 205 , shown by ILEAK passing through both NFET N 204  and NFET N 205 . Both PFET devices, P 201  and P 202  are “on”, pulling an output node, OUT, to VDD. Neither NFET N 204  nor NFET N 205  has the full VDD voltage from a drain to a source on each NFET, since the voltage is split in a complex way, and node  208  is at an intermediate voltage between the VDD voltage and ground. VDS is used to describe the voltage on an FET&#39;s drain measured relative to a source on that FET. The gate voltage on NFET N 204  is less than the source voltage on NFET N 204 , greatly reducing ILEAK in this case. VGS is used to describe the voltage on an FET&#39;s gate measured relative to a source on that FET. 
     FIG. 2B shows a two input NAND wherein a “0” is applied to a gate of a top NFET N 214 , and a “1” is applied to a gate of a bottom NFET N 215 . In this case, NFET N 215  is in a conducting state, and node  218  is discharged to “0”. A source of NFET N 214  is electrically coupled to node  218 . A gate on PFET P 211  has the same “0” applied that was applied to the gate of NFET N 214 . PFET P 211  is therefore conducting, and pulls an output node, OUT, to a “1”. NFET N 214  therefore has a VDS equal to VDD, and substantial leakage will occur from a drain of NFET N 214  to the source of NFET N 214 , as shown by ILEAK. 
     FIG. 2C shows a two input NAND wherein a “1” is applied to a gate of NFET N 224 , a top NFET in the stack, and a “0” applied to a gate of NFET N 225 , a bottom NFET in the stack. PFET P 222  is the complimentary PFET of NFET N 225 , and thus has the “0” applied to its gate, causing PFET P 222  to conduct and pull a node OUT to a “1”. PFET P 221 , the PFET compliment of NFET N 224 , has a “1” applied to a gate, making PFET P 221  nonconducting. Since node OUT is “1”, and since NFET N 224  is made conducting by the “1” on its gate, NFET N 225  has a VDS of VDD and substantial leakage will occur from a drain of NFET N 225  to the source of NFET N 225 . 
     FIG. 2D shows a two input NAND wherein a “1” is applied to a gate of NFET N 234  and a gate of NFET N 235 , causing both NFETs to conduct, and pull a node OUT to a “0”. Both PFET P 231  and P 232  have a gate voltage of “1” and are therefore nonconducting. Both PFETs P 231  and P 232  have a VDS of VDD, which causes substantial leakage to occur from a drain of PFET P 231  to a source of PFET P 231 , and from a drain of PFET P 232  to a source of PFET P 232 , as shown by ILEAK in the figure. 
     The above examples illustrate leakage situations for a two input NAND circuit. Similar leakage situations apply to inverters, NORs, and other CMOS logic blocks wherein a full VDD is applied across an FET. 
     FIGS. 3A-3E show preferred embodiments of the invention for a set of ASIC logic blocks, which, when added to the ASIC library, and used where timing margin allows, will reduce the average power of the ASIC logic chip. 
     FIG. 3A shows a three input NAND that is similar to the three input NAND shown in FIG. 1A with the exception that the bottom NFET in the stack, NFET N 306 , and its PFET compliment, PFET P 303 , have been replaced by high VT FETs. This invention includes FETs designed with longer channels as high VT devices. Longer channel FETs will have slightly higher VT&#39;s than devices that are made of the minimum FET channel length in a given technology. Under process variations in which channel lengths are shorter than nominal, the VT of longer channel FETs will remain relatively constant; the VT of FET devices designed with minimum channel length will decrease significantly. NFET N 306  has a high enough VT such that when a gate voltage on NFET N 306  is “0”, no significant leakage occurs, even when the VDS of NFET N 306  is VDD. When the gate voltage on NFET N 306  is “1”, some leakage will occur, dependent upon the logic state of the other two inputs, A and B. Leakage will also be significantly reduced over the conventional three input NAND in the case where inputs A, B, and C are all “1”, in which a node OUT will be pulled to “0” and all three PFET FETs will have VDS=VDD from a drain to a source. Although, in this case, PFET P 301  and PFET P 302  will have subthreshold leakage equal to their equivalents in the conventional three input NAND as shown in FIG. 1A, PFET P 303  will not contribute significant leakage. In this state, total leakage will be reduced by approximately ⅓. Table 1 shows a representative three input NAND leakage values for the eight different input states of inputs A, B, and C as shown in FIG.  1 A and FIG.  3 A. Table 1 shows that almost a third of the leakage can be eliminated by using a three input NAND that has the bottom NFET and its complimentary PFET implemented with high VT devices. An average savings of 46 uA will result from replacing the low VT block with a functionally equivalent high VT block. 
     
       
         
           
               
             
               
                 TABLE 1 
               
             
            
               
                   
               
               
                 Three Input NAND (46 μA savings) 
               
            
           
           
               
               
               
            
               
                 Inputs 
                 Leakage of Low 
                 Leakage of High 
               
               
                 ABC 
                 VT block 
                 VT block 
               
               
                   
               
               
                 000 
                 0.673 μA 
                 0.0414 μA 
               
               
                 001 
                  1.69 μA 
                  1.68 μA 
               
               
                 010 
                  1.68 μA 
                  0.161 μA 
               
               
                 011 
                  86.3 μA 
                  86.3 μA 
               
               
                 100 
                  1.64 μA 
                  0.158 μA 
               
               
                 101 
                  57.8 μA 
                  57.8 μA 
               
               
                 110 
                  52.6 μA 
                  3.42 μA 
               
               
                 111 
                   973 μA 
                   656 μA 
               
               
                 Average 
                   147 μA 
                   101 μA 
               
               
                   
               
            
           
         
       
     
     FIG. 3B shows a two input NAND that is similar to the conventional two input NAND of FIG. 1B, however, the lower NFET in the stack, NFET N 315  is a high VT NFET, and the complimentary PFET, P 312 , is a high VT PFET. When a gate of NFET N 315  is low, NFET N 315  has insignificant leakage. If NFET N 315  is “1” and a gate of NFET N 314  is low, node  318  will be at “0”, PFET P 311  will be conducting, and the VDS of NFET N 314  will be VDD. Significant leakage will occur through NFET N 314 . When both the gate of NFET N 315  and NFET  314  are “1”, node OUT will be at “0”, and both complimentary PFET devices P 311  and P 312  will be nonconducting. PFET P 311  will have substantial leakage. PFET P 312  will have insignificant leakage. Table 2 shows representative two input NAND leakage values for the four different input states, with inputs A and B as shown in FIGS. 1B and 3B. Table 2 shows that almost half of the leakage can be eliminated by using a two input NAND that has the bottom NFET and its complimentary PFET implemented with high VT devices. An average leakage reduction of 84 uA will result from replacing the low VT two input NAND with a functionally equivalent high VT two input NAND. 
     
       
         
           
               
             
               
                 TABLE 2 
               
             
            
               
                   
               
               
                 Two Input NAND (84 μA savings) 
               
            
           
           
               
               
               
            
               
                 Inputs 
                 Leakage of Low 
                 Leakage of High 
               
               
                 AB 
                 VT block 
                 VT block 
               
               
                   
               
               
                 00 
                  1.29 μA 
                 0.125 μA 
               
               
                 01 
                  64.8 μA 
                  64.8 μA 
               
               
                 10 
                  43.5 μA 
                  3.00 μA 
               
               
                 11 
                 602.0 μA 
                 308.0 μA 
               
               
                 Average 
                   178 μA 
                  94.0 μA 
               
               
                   
               
            
           
         
       
     
     FIG. 3C shows a CMOS inverter comprising PFET P 321  and NFET N 324 . A gate of PFET P 321  and a gate of NFET N 324  are electrically coupled to input A. Node OUT is the output node. Both FETs are built using high VT FET devices. Insignificant leakage occurs whether input A is “0” or “1” because in each case one of the FETs is nonconducting, and, being a high VT device, has very low leakage when nonconducting. Table 3 shows leakage comparison of such an inverter compared to a conventional inverter. Table 3 shows that using high VT devices for the NFET and the PFET can eliminate almost all of the leakage. An average leakage reduction of 157 uA will result from replacement of the low VT inverter with a high VT inverter. 
     
       
         
           
               
             
               
                 TABLE 3 
               
             
            
               
                   
               
               
                 Inverter (157 μA savings) 
               
            
           
           
               
               
               
            
               
                   
                 Leakage of Low 
                 Leakage of High 
               
               
                 Input A 
                 VT block 
                 VT block 
               
               
                   
               
               
                 0 
                  43.3 μA 
                 2.97 μA 
               
               
                 1 
                 278.0 μA 
                 5.75 μA 
               
               
                 Average 
                   161 μA 
                 4.36 μA 
               
               
                   
               
            
           
         
       
     
     FIG.  3 D and FIG. 3E show schematics of a three input NOR block and a two input NOR block. Exemplary leakage currents are not shown in tables for these blocks, but they exhibit leakage characteristics similar to their NAND counterparts. 
     A drawback in use of high VT FETs is that performance of a high VT FET is slower than performance of a low VT device. Referring to FIG. 3B, delay from a rising signal on input A to the fall of node OUT will be faster than a delay from a rising signal on input B to the fall of node OUT. Similarly, a delay from a falling signal on input A to the rise of node OUT will be faster than a delay from a falling signal on input B to the rise of node OUT. An exemplary delay difference is 30%, although that number would vary with technology. A method will be disclosed shortly explaining how high VT blocks can be used in an ASIC design flow. 
     Specialized variants of the new low leakage blocks are shown in FIGS. 4A-4D. 
     FIG. 4A shows a two input NAND wherein only PFET P 402  is a high VT device. Such a block could be used if a timing margin were to exist for input B falling to output OUT rising, but little or no timing margin were to exist for other delay paths. 
     FIG. 4B shows a two input NAND wherein only NFET N 415  is a high VT device. Such a block could be used if timing margin were to exist for delays from either input A or input B rising to output OUT falling, but little or no timing margin were to exist for either input A or input B falling to output OUT rising. 
     FIG. 4C shows a two input NOR wherein only NFET N 422  is a high VT device. Such a block could be used if timing margin were to exist for input B rising to output OUT falling, but little or no timing margin for other delay paths. 
     FIG. 4D shows a two input NOR wherein only PFET P 435  is a high VT device. Such a block could be used if timing margin were to exist for delays from either input A or input B falling to output OUT rising, but little or no timing margin were to exist for input A or B rising to output OUT falling. 
     Other variants of these specialized books are contemplated, such as a block wherein both of the NFET devices are high VT or both of the PFET devices are high VT devices. Performance would suffer even more if such books were added to the ASIC library, and even more care would be required in using such blocks. 
     ASIC libraries generally consist of a large number of blocks, including such complex logic elements as exclusive-or functions (XOR), latches, AND-OR-INVERT (AOI). Versions of such blocks could be created with high VT devices to further save leakage current. However, the inverter, the two and three way NAND blocks, and the two and three way NOR blocks are normally the most used blocks, often making up well over half the area on the ASIC chip. Creating high VT versions of seldom-used blocks would greatly expand the ASIC library size for a relatively small payback in power savings. Expansion of the ASIC library is expensive in design resource, ASIC design maintenance, and library storage requirements. In addition, a process for use of such complex logic elements would be difficult to develop. Although the current invention contemplates complex versions of such blocks the focus is on the limited set of logic primitives comprising an inverter, a two input NOR, a two input NAND, a three input NOR, and a three input NAND. 
     FIGS. 5A-5C collectively show the process flow that replaces low VT blocks with high VT blocks. 
     Tables 1-3 above show that the first set of blocks to be considered for replacement is the set of inverters on the ASIC chip. Every time an inverter implemented with low VT FETs is replaced by an inverter implemented with high VT FETs, almost all leakage is eliminated for that instantiation of the inverter. The second set of blocks to be considered for replacement is the set of two input blocks, comprising two input NANDs and NORs on the ASIC chip. Every time a two input NAND implemented with low VT FETs is replaced by a two input NAND implemented with high VT FETs, approximately half the leakage is eliminated for that instantiation. The third set of blocks to be considered for replacement is the set of three input blocks comprising three input NANDs and three input NORs. Each time a low VT version of such a block is replaced by a high VT version, approximately one third of the leakage is eliminated for that instantiation. 
     The process flowchart description for replacement of low VT blocks with high VT blocks begins on FIG.  5 A. Step  501  is the starting point. In step  502 , all blocks are initialized to low VT blocks from the ASIC library. This provides for the fastest delays and therefore the maximum timing margin, or slack, that the ASIC library will allow. In step  503 , all delays and slacks are computed for the ASIC chip. Positive slack means timing margin exists. For example, a two input NAND might have 100 picoseconds (ps) slack on a first input, but only 40 ps on a second input. ASIC design systems typically provide timing margin information for each transition direction for each pin. This information can be used by the design system for pin swapping (reconnecting signals to logically equivalent inputs) or choosing different, but functionally equivalent, logic blocks. 
     Step  504  in FIG. 5A begins a loop in which each inverter in the ASIC chip is checked for slack and is replaced by a high VT version of the inverter if timing margin allows. Step  504  selects an inverter from the set of all inverters on the ASIC chip. Step  505  does an initial check for positive slack. If slack is negative, the path does not meet timing requirements and no attempt will be made to replace the instant low VT inverter with a high VT inverter. If slack is positive, step  506  replaces the instant low VT inverter with a high VT version from the ASIC library. Delays and timing margins are recomputed in step  507  for the logic paths affected by the replacement. Block  508  checks slack after the replacement. If slack is positive, the replacement is a valid replacement, and control passes to step  510 . If slack is negative, the timing requirements have been violated by the block replacement, and control passes to step  509 , which restores the low VT block, the original delays, and the original slacks as they existed prior to the block replacement. Step  510  passes control to step  511  if all inverters on the ASIC chip have been considered for replacement. If not all inverters have been considered for replacement, step  510  passes control to step  504 , which repeats the loop for another inverter. 
     Step  511  is simply a connector, which transfers control to step  513  on FIG.  5 B. 
     Referring now to FIG. 5B, we see the replacement steps for the two input NANDs and two input NORs. 
     Step  514  is similar to step  504  of FIG.  5 A. Step  514  is the start of a loop which iterates through all two input NAND and two input NOR blocks on the ASIC chip. In this loop, the instant low VT two input block is considered for replacement by a high VT two input block to reduce leakage current. 
     Step  515  checks for positive slack on the instant two input block. If slack is negative, timing requirements are not met with the current blocks, and no attempt to use a high VT block is made. Control passes to step  520 . However, if positive slack exists, control is passed to step  516 . 
     Step  516  replaces the instant low VT block with a high VT block. Both inputs on a two input NAND or a two input NOR are logically equivalent. The signal with the largest positive slack is coupled to the input that drives the high VT FETs, input B in FIG. 3B or FIG.  3 E. The signal with the smaller positive slack is coupled to the input that drives the remaining low VT FETs, as shown as input A in FIG. 3B or FIG.  3 E. 
     Step  517  recomputes delays and slacks on all affected logic. 
     Step  518  checks timing margins after the trial replacement of the block as performed in step  516 . If timing margin exists, the replacement is made permanent, and control is passed to step  520 . If timing margin does not exist, control passes to step  519 . Step  519  restores the block, the delays, the timing margins, and the assignment of signals to pins on the block to what they were prior to step  516 . After this restoration, control is passed to step  520 . 
     Step  520  is the end of the loop begun in step  514 . If more two input blocks are to be considered, control passes to step  514 ; otherwise, control passes to step  521 , which is a connector to step  523  on FIG.  5 C. 
     The steps in FIG. 5C are the same as those of FIG. 5B, only here the three input NANDs and the three input NORs are considered. 
     Step  524  is the start of a loop which iterates through all three input NAND and three input NOR blocks on the ASIC chip. In this loop, the instant low VT three input block is considered for replacement by a high VT three input block to reduce leakage current. 
     Step  525  checks for positive slack on the instant three input block. If slack is negative, timing requirements are not met with the current blocks, and no attempt to use a high VT block is made. Control passes to step  530 . If positive slack exists, control is passed to step  526 . 
     Step  526  replaces the instant low VT block with a high VT block. The inputs on a three input NAND or a three input NOR are logically equivalent. The signal with the largest positive slack is coupled to the input that drives the gates of the high VT FETs, input C in FIG. 3A or FIG.  3 D. The signal with the smallest positive slack is coupled to the input which drives the gates of the low VT FETs, input A in FIG. 3A or FIG.  3 D. The signal with intermediate slack is coupled electrically to the remaining input of the NAND or NOR. 
     Step  527  recomputes delays and slacks on all affected logic. 
     Step  528  checks timing margins after the trial replacement of the block as done in step  526 . If timing margin exists, the replacement is made permanent, and control is passed to step  530 . If timing margin does not exist, control passes to step  529 . Step  529  restores the block, the delays, the timing margins, and the assignment of signals to pins on the block to what they were prior to step  526 . After this restoration, control is passed to step  530 . 
     Step  530  is the end of the loop begun in step  524 . If more three input blocks are to be considered, control passes to step  524 ; otherwise, control passes to step  531 , which shows the completion of the process. 
     Obviously, if only a subset of the exemplary ASIC library extensions have been implemented, non-implemented blocks would not be considered in the process. For example, NOR logic blocks are used far less often in usual ASIC CMOS designs than are NAND logic blocks. Power savings gained from creation of high VT NOR blocks in the ASIC library would not be very large, and the ASIC library designer may choose not to implement high VT NOR blocks. 
     Clock signals are finely tuned in high performance designs, and logic blocks on clock signals would not normally be candidates for replacement. Therefore, blocks on clock signal paths are not considered part of the process taught by this invention. 
     While the present invention has been described with reference to the details of the embodiments of the invention shown in the drawings, these details are not intended to limit the scope of the invention as claimed in the appended claims.