Patent Publication Number: US-6992526-B2

Title: Apparatus and method for DC offset reduction

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     Embodiments of the present invention relate to DC offset reduction techniques and, in particular, to DC offset reduction techniques that provide improved settling time. 
     2. Description of Related Art 
     The performance of electronic devices such as cellular telephones, personal digital assistants and other wireless and wired devices is often related directly to the performance of the components making up the devices. For example, the performance of many wireless devices is often related to the device&#39;s receiver that receives and processes transmitted signals. A receiver in a wireless device can be critical to the performance of the device. The receiver is often the first component in the device to see a transmitted signal incident on the device&#39;s antenna and, thus, is often the first component to influence the signal. Consequently, the quality of the receiver can be critical to the quality of the performance of the device in general. 
     A direct conversion receiver circuit typically includes a mixer module for down converting a received signal to a baseband signal, a variable gain amplifier for amplifying the baseband signal, and a signal processing module for processing the baseband signal. Many receivers of this type suffer from inherent inefficiencies. For example, many receivers of this type produce a DC offset in the output of the amplifier that degrades the performance of subsequent processing stages and increases power consumption. 
       FIG. 1  shows the amplifier stage of a receiver circuit disclosed in U.S. Pat. No. 6,290,226. This amplifier stage is designed to compensate for DC offset in the output signal. The amplifier stage is comprised of a variable gain amplifier  10  that receives the input signal of the amplifier stage, an adder  12 , a low pass filter  14 , and a variable gain amplifier  16  that provides the output signal of the amplifier stage. A feedback path is provided between the output of the fixed gain amplifier  16  and the adder  12 . The feedback path is comprised of a first fixed gain feedback amplifier  18 , a capacitor  20 , and a second fixed gain feedback amplifier  22 . The amount of charge stored in the capacitor controls the output of the fixed gain amplifier  22 , which supplies a DC signal to the mixer  12  for compensating DC offset in the output signal. The amount of charge stored in the capacitor for compensating a given DC offset is a function of the DC offset and depends on the gains of the various elements in the loop. 
     While the circuit of  FIG. 1  exhibits an improved settling time, the circuit has certain drawbacks. The circuit of  FIG. 1  is essentially a high pass filter that passes high frequency components of the input signal and blocks low frequency components of the signal. The rate of DC offset cancellation provided by this circuit depends on the corner frequency of the high pass pole established by the feedback path. The corner frequency depends on the loop gain of the forward amplification elements and the feedback path elements. Because the gain of the feedback path amplifiers  18 ,  22  is constant while the gain of the variable gain amplifier  16  is not, the corner frequency of the high pass circuit varies with changes in the gain of the variable gain amplifier  16 . In particular, the −3 dB high pass corner frequency of the feedback path is lowered when the gain of the variable gain amplifier  16  decreases, making the settling time of the system longer. Thus the settling time varies inversely with the forward gain of the variable gain amplifier  16 . This causes undesirable circuit performance. 
     SUMMARY OF THE INVENTION 
     Amplifier stages in accordance with a preferred embodiment of the invention improve over the conventional circuit by making the settling time independent of the forward gain of the amplifier stage, and by making the feedback path responsive to the magnitude of DC offset in the output signal. 
     Settling time may be made independent of the forward gain of the amplifier stage by providing a constant loop gain in the amplifier stage through active gain control of both the forward and linear feedback amplifier elements. 
     The feedback path may be made responsive to the magnitude of DC offset in the output signal by providing a non-linear transconductance in the feedback path. As a result, the −3 dB high pass corner frequency and hence the DC offset reduction time of the system is responsive to the magnitude of DC offset in the output signal. 
    
    
     
       DESCRIPTION OF THE DRAWINGS 
       A detailed description of embodiments of the invention will be made with reference to the accompanying drawings, wherein like numerals designate corresponding parts in the several figures. 
         FIG. 1  shows a generalized schematic diagram of the amplifier stage of a conventional receiver device. 
         FIG. 2  shows a generalized schematic diagram of a circuit for reducing DC offset according to a preferred embodiment of the present invention. 
         FIG. 3  shows the status of the feedback path elements of  FIG. 2  during different time periods in the operation of a time-slotted receiver circuit in accordance with the preferred embodiment. 
         FIG. 4  shows a more detailed schematic diagram of a preferred embodiment of an amplifier stage of a receiver circuit. 
         FIG. 5  shows a graph of the transfer function in the frequency domain of the circuit of  FIG. 4 . 
     
    
    
     DETAILED DESCRIPTION 
     In the following description of preferred embodiments, reference is made to the accompanying drawings which form a part hereof, and in which are shown by way of illustration specific embodiments in which the invention may be practiced. It is to be understood that other embodiments may be utilized and structural changes may be made without departing from the scope of the preferred embodiments of the present invention. 
       FIG. 2  shows a generalized schematic diagram of an amplifier circuit having improved DC offset reduction according to a preferred embodiment of the invention. In this circuit an input signal is received by a forward amplifier section  30 . DC offset in the output of the forward amplifier section  30  is corrected by a feedback path that includes a linear feedback amplifier section  32  that senses and compensates for any DC offset in the signal amplified by the forward amplifier section  30 . The forward amplifier section  30  and the linear feedback amplifier section  32  are controlled by a common gain control section  34 . Gain control is typically utilized in the forward amplifier section of an amplifier stage to provide a relatively constant signal level at the output. In accordance with the preferred embodiment, gain control is provided to the forward amplifier section  30  and to the linear feedback amplifier section  32 . When the gain of the forward amplifier section  30  is increased, the gain of the linear feedback amplifier section  32  is decreased proportionally by an amount that maintains the loop gain at a constant level. Similarly, when the gain of the forward amplifier section  30  is decreased, the gain of the linear feedback amplifier section  32  is increased. By maintaining an essentially constant loop gain in this manner, the −3 dB high pass corner frequency of the system becomes independent of the amplifier stage forward gain, thus making the DC offset settling time independent from the gain of the forward amplifier components. 
     The feedback path of the amplifier stage of the preferred embodiment also includes a non-linear feedback amplifier section  36 . During a transient condition, the charging and discharging current that can be provided by the linear feedback amplifier section  32  to a storage capacitor (not shown) in the linear feedback amplifier section is limited by the bias current provided to the linear feedback amplifier section  32 . Therefore the amount of offset that can be corrected by the linear feedback amplifier section  32  is limited by the bias current. The use of a non-linear feedback amplifier section  36  in conjunction with the linear feedback amplifier section  32  overcomes this limitation. The amplification provided by the non-linear feedback amplifier increases as a function of the magnitude of the DC offset in the output signal. Essentially, the non-linear feedback amplifier section  36  varies the −3 dB high pass corner frequency in response to the magnitude of DC offset in the output signal so that a higher corner frequency and therefore a more rapid settling time is provided corresponding to the magnitude of the DC offset in the output signal. Thus the settling time is significantly reduced even in the event of large DC transients. 
     Consequently, amplifier stages in accordance with the preferred embodiment improve over the conventional circuit by making the settling time independent of the forward gain of the amplifier stage, and by making the settling time responsive to the magnitude of DC offset in the output signal. 
       FIG. 3  shows the status of the linear and non-linear feedback amplifier sections during various phases of data reception in a time-slotted, implementation. During an idle phase  40  when no data is being received, the linear feedback amplifier section is on to cancel any device induced DC offset, and the non-linear feedback amplifier section is also on to set a high corner frequency to provide fast settling time. 
     During the reception of a preamble phase  42  of a receive timeslot, the linear feedback amplifier section remains on to cancel DC offset. Typically automatic gain control is applied at this time to both the forward amplifier section and the linear feedback amplifier section, causing the loop gain to remain essentially constant. The non-linear feedback amplifier section is also on during the preamble phase  42  of the receive timeslot to increase DC offset correction. 
     During a receive data phase  44  of the receive timeslot, the linear feedback amplifier section is in hold mode to hold a DC offset compensation charge that was stored during the preamble phase  42 . The non-linear feedback amplifier section is turned off at this time to maintain the high pass corner frequency at approximately 30 kHz so that received signals are not corrupted. The linear feedback amplifier section and the non-linear feedback amplifier section are turned on again in the next idle or preamble phase to provide further DC offset cancellation. 
       FIG. 4  shows a schematic diagram of a circuit in accordance with the preferred embodiment of  FIG. 2 . The circuit of  FIG. 4  is a down conversion circuit that converts a received signal to baseband by mixing with a radio frequency and amplifies the baseband signal. An input signal is received by a mixer  50 . The input signal is a differential signal comprised of an input current and a complementary input current. The input currents are passed a through programmable gain amplifiers  52  that provide forward amplification of the baseband signal to generate differential output voltage signals. Feedback for purposes of DC offset cancellation is provided by programmable gain linear feedback amplifiers  54 . The gains of the amplifiers  52  of the forward section and the linear amplifiers  54  of the feedback path are controlled by a gain control section  56 . The gain control section  56  controls the gain of the forward amplifiers  52  to provide an essentially constant magnitude in the output signal. The gain control section  56  controls the gain of the linear feedback path amplifiers  54  to provide a constant loop gain in light of gain changes in the forward amplifiers  52 . Consequently, an increase in the gain of the forward amplifiers  52  is balanced by a corresponding decrease in the gain of the linear feedback amplifiers  54 . 
     The feedback path in the circuit of  FIG. 4  also includes a capacitor  58  and a resistor  60  for storage of a charge that is used to provide a feedback signal to the mixer  50  for compensating DC offset in the output signal. The capacitor  58  is charged by the first of the linear feedback path amplifiers  54 . 
     A nonlinear feedback amplifier  62  is provided in parallel with the first linear feedback path amplifier  54 . The nonlinear feedback amplifier  62  may be implemented as a class A/B amplifier. The capacitor  58  is also charged by the nonlinear feedback amplifier  62  to decrease the time required to store charge in the capacitor. 
     Control of the nonlinear feedback amplifier  62  may be implemented in several manners. In the preferred embodiment, the amount of gain of the nonlinear feedback amplifier  62  is controlled within the amplifier  62  itself in response to the amount of DC offset in the output signal of the amplifier stage, which is sensed at the inputs to the nonlinear feedback amplifier  62 . In alternative embodiments, the gain of the nonlinear feedback amplifier  62  may be controlled externally, such as by the gain control section  56 , in response to DC offset in the output signal. In further alternative embodiments, the gain of the nonlinear feedback amplifier  62  may be set to a high value, and the nonlinear feedback amplifier  62  may be selectively turned on and off to control its effect on the settling time. 
     A graph of the transfer function in the frequency domain of the circuit of  FIG. 4  is shown in  FIG. 5 . For a circuit in which the gain of the forward amplifiers  52  is A, the transconductance of the linear feedback amplifiers  54  are g m1  and g m2 , respectively, the value of the resistor is R, and the value of the capacitor is C, the gain V out /I in  of the circuit is approximately:
 
 A /(1 +A   ×g   m1   ×R   ×g   m2 )/(1 +sRC )  (1)
 
The −3 dB high pass corner frequency of the circuit is approximately:
 
 g   m1   ×g   m2   ×A /(2 1/2   ×C )  (2)
 
The lower +3 dB high pass corner is approximately:
 
1/( R×C )  (3)
 
The floor of the stop band is approximately:
 
1/( g   m1   ×g   m2   ×R )  (4)
 
     Embodiments of the present invention may be used in any type of circuit that requires DC offset reduction. For example, embodiments of the present invention may be used in wireless and wired receivers. More generally, embodiments of the present invention may used in a variety of wireless technologies such as wireless LAN applications and cellular telephone technologies, and in a variety of hand-held technologies such as personal digital assistants. 
     Embodiments in accordance with the invention may be implemented in a variety of ways. For example, according to an embodiment of the present invention, the circuit may be implemented as an integrated circuit on a single substrate, as a hybrid device, or as a discrete circuit. The circuit may be implemented on silicon, gallium arsenide or other semiconductor. 
     The circuits, devices, features and processes described herein are not exclusive of other circuits, devices, features and processes, and variations and additions may be implemented in accordance with the particular objectives to be achieved. For example, circuits as described herein may be integrated with other circuits not described herein to provide further combinations of features, to operate concurrently within the same devices, or to serve other types of purposes. Thus, while the embodiments illustrated in the figures and described above are presently preferred for various reasons as described herein, it should be understood that these embodiments are offered by way of example only. The invention is not limited to a particular embodiment, but extends to various modifications, combinations, and permutations that fall within the scope of the claims and their equivalents.