Patent Publication Number: US-10312110-B2

Title: Method for manufacturing an SGT-including semiconductor device

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is a divisional of copending application Ser. No. 14/511,215, filed Oct. 10, 2014, which is a continuation, under 35 U.S.C. § 120, of international application No. PCT/JP2013/080009, filed Nov. 6, 2013, the contents of the prior applications are incorporated herein by reference in their entirety. 
    
    
     BACKGROUND OF THE INVENTION 
     Field of the Invention 
     The present invention relates to a semiconductor device that includes a surrounding gate MOS transistor (SGT) and a method for manufacturing the semiconductor device. 
     In recent years, SGTs have gathered much attention as semiconductor elements that can be used to form highly integrated semiconductor devices. A further increase in the degree of integration of SGT-including semiconductor devices is highly anticipated. 
     A typical planar MOS transistor has a channel extending in a horizontal direction along a surface of a semiconductor substrate. In contrast, the channel of an SGT extends in a direction perpendicular to the surface of the semiconductor substrate (for example, refer to Patent Literature 1 and Non Patent Literature 1). Thus, compared to planar MOS transistors, SGTs help increase the density of semiconductor devices. 
       FIG. 8  is a schematic diagram of an N-channel SGT. An N +  region  101   a  and an N +  region  101   b  (hereinafter a semiconductor region having a high donor impurity concentration is referred to as an “N +  region”) are respectively formed in an upper portion and a lower portion of a Si pillar  100  having a P-type or i(intrinsic)-type conductivity (hereinafter a silicon semiconductor pillar is referred to as “Si pillar”). When the N +  region  101   a  serves as a source, the N +  region  101   b  serves as a drain and when the N +  region  101   a  serves as a drain, the N +  region  101   b  serves as a source. The Si pillar  100  that lies between the N +  region  101   a  and N +  region  101   b  serving as a source and a drain is a channel region  102 . A gate insulating layer  103  is formed so as to surround the channel region  102  and a gate conductor layer  104  is formed so as to surround the gate insulating layer  103 . In the SGT, the N +  regions  101   a  and  101   b  serving as a source and a drain, the channel region  102 , the gate insulating layer  103 , and the gate conductor layer  104  are formed within a single Si pillar  100 . Accordingly, the area of the SGT in plan view corresponds to the area of a single source or drain N +  region of a planar MOS transistor. Thus, a circuit chip that includes SGTs is smaller than a circuit chip that includes planar MOS transistors. 
     Attempts are now being made to further decrease the size of SGT-including circuit chips. For example, it has been anticipated that the circuit area can be reduced by forming two SGTs  116   a  and  116   b  in the upper portion and the lower portion of one Si pillar  115  as illustrated in a schematic diagram of  FIG. 9  (for example, refer to Non Patent Literature 2). 
       FIG. 9  is a schematic diagram of a CMOS inverter circuit in which an N channel SGT  116   a  is formed in a lower portion of the Si pillar  115  and a P channel SGT  116   b  is formed above the N channel SGT  116   a . The Si pillar  115  is formed on a P layer substrate  117  (hereinafter, a semiconductor layer containing an acceptor impurity is referred to as a “P layer”). A SiO 2  layer  118  is formed at the outer periphery of the Si pillar  115  and on the P layer substrate  117 . A gate insulating layer  119   a  of the N channel SGT  116   a  and a gate insulating layer  119   b  of the P channel SGT  116   b  are formed so as to surround the Si pillar  115 . A gate conductor layer  120   a  of the N channel SGT  116   a  and a gate conductor layer  120   b  of the P channel SGT  116   b  are formed at the outer periphery of the Si pillar  115  so as to surround the gate insulating layers  119   a  and  119   b . An N +  region  121   a  is formed in a surface layer portion of the P layer substrate  117  connected to the bottom portion of the Si pillar  115 , an N +  region  121   b  is formed at the center of the Si pillar  115 , a P +  region  122   a  (hereinafter a semiconductor region having a high acceptor impurity concentration is referred to as a “P +  region”) is formed within the Si pillar  115  connected to the N +  region  121   b , and a P +  region  122   b  is formed in a top portion of the Si pillar  115 . The N +  region  121   a  is a source of the N channel SGT  116   a  and the N +  region  121   b  is a drain of the N channel SGT  116   a . The Si pillar  115  that lies between the N +  regions  121   a  and  121   b  is a channel region  123   a  of the N channel SGT  116   a . The P +  region  122   b  is a source of the P channel SGT  116   b  and the P +  region  122   a  is a drain of the P channel SGT  116   b . The Si pillar  115  that lies between the P +  regions  122   a  and  122   b  is a channel region  123   b  of the P channel SGT  116   b . A nickel silicide layer (NiSi layer)  125   a  is formed in the surface layer portion of the N +  region  121   a  connected to the bottom portion of the Si pillar  115 , a NiSi layer  125   b  is formed at the outer peripheries of the N +  region  121   b  and the P +  region  122   a  located in the center portion of the Si pillar  115 , and a NiSi layer  125   c  is formed in an upper surface layer of the P +  region  122   b  in the top portion of the Si pillar  115 . A ground wiring metal layer  126   a  is formed so as to connect to the NiSi layer  125   a  in the N +  region  121   a . The ground wiring metal layer  126   a  is connected to a ground terminal VSS. Similarly, an output wiring metal layer  126   b  is formed so as to connect to the NiSi layer  125   b . The output wiring metal layer  126   b  is connected to an output terminal Vo. Similarly, a power supply wiring metal layer  126   c  is formed so as to connect to the NiSi layer  125   c . The power supply wiring metal layer  126   c  is connected to a power supply terminal VDD. Input wiring metal layers  127   a  and  127   b  are formed so as to connect to the gate conductor layers  120   a  and  120   b . The input wiring metal layers  127   a  and  127   b  are each connected to an input terminal Vi. 
     In the schematic diagram of  FIG. 9 , the NiSi layer  125   b  connected to the N +  region  121   b  and the P +  region  122   a  located at the center portion of the Si pillar  115  is formed by coating outer peripheral surfaces of the N +  region  121   b  and the P +  region  122   a  with a nickel (Ni) film, performing a heat treatment at about 450° C., and removing the Ni film remaining on the surfaces. As a result, the NiSi layer  125   b  is formed so as to extend from the outer peripheries of the N +  region  121   b  and the P +  region  122   a  toward the interior. For example, when the Si pillar  115  has a diameter of 20 nm, the NiSi layer  125   b  is preferably formed to have a thickness of about 5 nm to 10 nm. When the NiSi layer  125   b  has a thickness of 10 nm, the NiSi layer  125   b  occupies the entire cross section of the Si pillar  115 . The linear thermal expansion coefficient of NiSi is 12×10 −6 /K, which is five times the linear thermal expansion coefficient of Si which is 2.4×10 −6 /K. Thus, large stress-induced strain is generated inside the Si pillar  115  due to the NiSi layer  125   b . As a result, failures such as bending or collapsing of the Si pillar  115  may readily occur. More failures would occur when the diameter of the Si pillar is decreased in order to increase the degree of circuit integration. 
     The following citations are referenced in this application. They are herewith incorporated by reference: 
     PATENT LITERATURE 
     
         
         PTL 1: Japanese Unexamined Patent Application Publication No. 2-188966 
       
    
     NON PATENT LITERATURE 
     
         
         NPL 1: Hiroshi Takato, Kazumasa Sunouchi, Naoko Okabe, Akihiro Nitayama, Katsuhiko Hieda, Fumio Horiguchi, and Fujio Masuoka: IEEE Transaction on Electron Devices, Vol. 38, No. 3, pp. 573-578 (1991) 
         NPL 2: Hyoungiun Na and Tetsuo Endoh: “A New Compact SRAM cell by Vertical MOSFET for Low-power and Stable Operation”, Memory Workshop, 201 3 rd  IEEE International Digest, pp. 1 to 4 (2011) 
         NPL 3: Tadashi Shibata, Susumu Kohyama and Hisakazu Iizuka: “A New Field Isolation Technology for High Density MOS LSI”, Japanese Journal of Applied Physics, Vol. 18, pp. 263-267 (1979) 
       
    
     According to an SGT-including semiconductor device illustrated in  FIG. 9 , during formation of the NiSi layer  125   b  connected to the N +  region  121   b  and the P +  region  122   a  located at the center portion of the single Si pillar  115 , the difference in linear thermal expansion coefficient between Si and NiSi causes stress-induced strain in the Si pillar  115 , leading to bending or collapsing of the Si pillar  115 . Due to these failures, it becomes difficult to obtain a circuit that includes an SGT and operates normally. There is also a problem in which decreasing the diameter of the Si pillar  115  to increase the degree of circuit integration increases the likelihood of bending and collapsing of the Si pillar  115 . To address this, formation of a NiSi layer  125   b  that connects to the N +  region  121   b  and the P +  region  122   a  without causing bending or collapsing of the Si pillar  115  is desired. 
     SUMMARY OF THE INVENTION 
     A first aspect of the present invention provides a surrounding gate MOS transistor (SGT)-including semiconductor device that includes: 
     a first semiconductor pillar formed on a semiconductor substrate; 
     a first impurity region containing a donor impurity or an acceptor impurity and being formed in a lower portion of the first semiconductor pillar; 
     a second impurity region formed in the first semiconductor pillar at a position above and remote from the first impurity region, the second impurity region having the same conductivity type as the first impurity region; 
     a first gate insulating layer formed to surround an outer periphery of the first semiconductor pillar that lies between the first impurity region and the second impurity region; 
     a first gate conductor layer formed to surround an outer periphery of the first gate insulating layer; 
     a wiring semiconductor layer in contact with an outer peripheral side surface of the first impurity region, the second impurity region, or the first gate conductor layer; 
     a first alloy layer formed in a side surface of the wiring semiconductor layer; 
     a second alloy layer formed in an upper surface and the side surface of the wiring semiconductor layer and connected to the first alloy layer; 
     a contact hole formed on an upper surface of the second alloy layer; and 
     a wiring metal layer electrically connected to the first impurity region, the second impurity region, or the first gate conductor layer through the contact hole, 
     wherein the semiconductor device includes a first SGT in which when one of the first impurity region and the second impurity region serves as a source, the other serves as a drain, the first semiconductor pillar that lies between the first impurity region and the second impurity region serves as a channel, and the first gate conductor layer surrounding the outer periphery of the first gate insulating layer serves as a gate. 
     Preferably, the SGT-including semiconductor device includes: 
     a third impurity region located above the second impurity region and formed in an upper portion of the first semiconductor pillar; 
     a fourth impurity region formed in the first semiconductor pillar at a position above and remote from the third impurity region, the fourth impurity region having the same conductivity type as the third impurity region; 
     a second gate insulating layer formed to surround an outer periphery of the first semiconductor pillar that lies between the third impurity region and the fourth impurity region; 
     a second gate conductor layer formed to surround an outer periphery of the second gate insulating layer; 
     the wiring semiconductor layer that is in contact with the second impurity region and the third impurity region and that is formed to connect the second impurity region to the third impurity region; 
     a fifth impurity region that is formed in the wiring semiconductor layer, is connected to the second impurity region, contains a donor or acceptor impurity contained in the second impurity region so as to have the same conductivity type as the second impurity region, and is in contact with the first alloy layer; 
     a sixth impurity region that is formed in the wiring semiconductor layer, is connected to the third impurity region, contains a donor or acceptor impurity contained in the third impurity region so as to have the same conductivity type as the third impurity region, and is in contact with the first alloy layer; 
     the second alloy layer formed in the upper surface and the side surface of the wiring semiconductor layer and connected to the first alloy layer; and 
     the wiring metal layer electrically connected to the second impurity region and the third impurity region through the contact hole formed on the upper surface of the second alloy layer, 
     wherein the semiconductor device includes a second SGT in which one of the third impurity region in contact with the second impurity region of the first SGT and the fourth impurity region serves as a source and the other serves as a drain, the first semiconductor pillar that lies between the third impurity region and the fourth impurity region serves as a channel, and the second gate conductor layer surrounding the outer periphery of the second gate insulating layer serves as a gate. 
     Preferably, the wiring semiconductor layer contains a donor or acceptor impurity contained in the impurity region having the lower concentration out of the second impurity region and the third impurity region, and 
     the impurity region having the lower impurity concentration is formed by thermal diffusion of the donor or acceptor impurity contained in the wiring semiconductor layer. 
     Preferably, the contact hole is formed on the upper surface of the second alloy layer and formed so as to contain the second alloy layer in a portion connected to the side surface of the wiring semiconductor layer. 
     Preferably, the first wiring semiconductor layer has a thickness larger than a half of a length of one side of the contact hole in plan view. 
     Preferably, the SGT-including semiconductor device includes: 
     a second semiconductor pillar formed near the first semiconductor pillar; 
     a third SGT formed in the second semiconductor pillar; 
     a third gate conductor layer formed to surround an outer periphery of the second semiconductor pillar; 
     the wiring semiconductor layer in contact with the first gate conductor layer and the third gate conductor layer and formed so as to connect the first gate conductor layer to the third gate conductor layer; 
     the first alloy layer positioned at a side surface of the wiring semiconductor layer surrounding the outer periphery of the first semiconductor pillar and in contact with the first gate conductor layer; 
     a third alloy layer positioned at the side surface of the wiring semiconductor layer surrounding an outer periphery of the second semiconductor pillar and in contact with the third gate conductor layer; 
     a second alloy layer positioned in an upper surface portion of the wiring semiconductor layer and the side surface of the wiring semiconductor layer surrounding the outer peripheries of the first semiconductor pillar and the second semiconductor pillar; and 
     the wiring metal layer electrically connected to the first gate conductor layer and the third gate conductor layer through the contact hole, the first alloy layer, the second alloy layer, and the third alloy layer. 
     Preferably, the second alloy layer is in contact with the fifth impurity region and the sixth impurity region. 
     Preferably, the wiring semiconductor layer contains a donor or acceptor impurity; 
     the donor or acceptor impurity of the wiring semiconductor layer thermally diffuses into the first semiconductor pillar by performing a heat treatment so as to form a seventh impurity region in the first semiconductor pillar; and 
     SGTs of the same conductivity type are respectively formed above and below the seventh impurity region. 
     A second aspect of the present invention provides a method for manufacturing an SGT-including semiconductor device, the method including: 
     a first semiconductor pillar forming step of forming a first semiconductor pillar on a semiconductor substrate; 
     a first impurity region forming step of forming a first impurity region in a lower portion of the first semiconductor pillar, the first impurity region containing a donor or acceptor impurity; 
     a second impurity region forming step of forming a second impurity region in the first semiconductor pillar at a position above and remote from the first impurity region, the second impurity region having the same conductivity type as the first impurity region; 
     a first gate insulating layer forming step of forming a first gate insulating layer so as to surround an outer periphery of the first semiconductor pillar that lies between the first impurity region and the second impurity region; 
     a first gate conductor layer forming step of forming a first gate conductor layer so as to surround an outer periphery of the first gate insulating layer; 
     a wiring semiconductor layer forming step of forming a wiring semiconductor layer in contact with an outer peripheral side surface of the first impurity region, the second impurity region, or the first gate conductor layer; 
     a first and second alloy layers forming step of forming a first alloy layer in a side surface of the wiring semiconductor layer and forming a second alloy layer in an upper surface and the side surface of the wiring semiconductor layer so that the second alloy layer is connected to the first alloy layer; 
     a contact hole forming step of forming a contact hole on an upper surface of the second alloy layer; and 
     a wiring metal layer forming step of forming a wiring metal layer electrically connected to the first impurity region, the second impurity region, or the first gate conductor layer through the contact hole, 
     wherein a first SGT is formed in which when one of the first impurity region and the second impurity region serves as a source, the other serves as a drain, the first semiconductor pillar that lies between the first impurity region and the second impurity region serves as a channel, and the first gate conductor layer surrounding the outer periphery of the first gate insulating layer serves as a gate. 
     Preferably, the method includes: 
     a third impurity region forming step of forming a third impurity region in an upper portion of the first semiconductor pillar, the third impurity region being located above the second impurity region; 
     a fourth impurity region forming step of forming a fourth impurity region in the first semiconductor pillar at a position above and remote from the third impurity region, the fourth impurity region having the same conductivity type as the third impurity region; 
     a second gate insulating layer forming step of forming a second gate insulating layer so as to surround an outer periphery of the first semiconductor pillar that lies between the third impurity region and the fourth impurity region; 
     a second gate conductor layer forming step of forming a second gate conductor layer so as to surround an outer periphery of the second gate insulating layer; 
     the wiring semiconductor layer forming step of forming the wiring semiconductor layer in contact with the second impurity region and the third impurity region so that the wiring semiconductor layer connects the second impurity region to the third impurity region; 
     a fifth impurity region forming step of forming a fifth impurity region in the wiring semiconductor layer, the fifth impurity region being connected to the second impurity region, containing a donor or acceptor impurity contained in the second impurity region so as to have the same conductivity type as the second impurity region, and being in contact with the first alloy layer; 
     a sixth impurity region forming step of forming a sixth impurity region in the wiring semiconductor layer, the sixth impurity region being connected to the third impurity region, containing a donor or acceptor impurity contained in the third impurity region so as to have the same conductivity type as the third impurity region, and being in contact with the first alloy layer; 
     the second alloy layer forming step of forming the second alloy layer in the upper surface and the side surface of the wiring semiconductor layer, the second alloy layer being connected to the first alloy layer; 
     the contact hole forming step of forming the contact hole on the upper surface of the second alloy layer; and 
     the wiring metal layer forming step of forming the wiring metal layer electrically connected to the second impurity region and the third impurity region through the contact hole, 
     wherein a second SGT is formed in which when one of the third impurity region in contact with the second impurity region of the first SGT and the fourth impurity region serves as a source, the other serves as a drain, the first semiconductor pillar that lies between the third impurity region and the fourth impurity region serves as a channel, and the second gate conductor layer surrounding the outer periphery of the second gate insulating layer serves as a gate. 
     Preferably, the wiring semiconductor layer is caused to contain a donor or acceptor impurity contained in the impurity region having the lower impurity concentration out of the second impurity region and the third impurity region; 
     the donor or acceptor impurity contained in the wiring semiconductor layer is thermally diffused into the first semiconductor pillar from the first wiring semiconductor layer; and 
     the second impurity region and the third impurity region are formed in the first semiconductor pillar. 
     Preferably, the contact hole is formed on the upper surface of the second alloy layer so as to contain the upper surface and the side surface of the second alloy layer in a portion of the first contact hole. 
     Preferably, the wiring semiconductor layer is formed to have a thickness larger than a half of a length of one side of the contact hole in plan view. 
     Preferably, the method includes: 
     a second semiconductor pillar forming step of forming a second semiconductor pillar near the first semiconductor pillar; 
     a third SGT forming step of forming a third SGT in the second semiconductor pillar; 
     a third gate conductor layer forming step of forming a third gate conductor layer so as to surround an outer periphery of the second semiconductor pillar; 
     the wiring semiconductor layer forming step of forming the wiring semiconductor layer in contact with the first gate conductor layer and the third gate conductor layer and connecting the first gate conductor layer to the third gate conductor layer; 
     the first alloy layer forming step of forming the first alloy layer so as to be positioned in a side surface of the wiring semiconductor layer surrounding the outer periphery of the first semiconductor pillar and in contact with the first gate conductor layer; 
     a third alloy layer forming step of forming a third alloy layer that is positioned in a side surface of the wiring semiconductor layer surrounding the outer periphery of the second semiconductor pillar and in contact with the third gate conductor layer; 
     the second alloy layer forming step of forming the second alloy layer that is positioned in an upper surface layer portion of the wiring semiconductor layer and the side surface of the wiring semiconductor surrounding the outer peripheries of the first semiconductor pillar and the second semiconductor pillar and that connects the first alloy layer to the third alloy layer; 
     the contact hole forming step of forming the contact hole on an upper surface of the second alloy layer; and 
     the wiring metal layer forming step of forming the wiring metal layer so as to be electrically connected to the first gate conductor layer and the third gate conductor layer through the contact hole, the first alloy layer, the second alloy layer, and the third alloy layer. 
     Preferably, the second alloy layer is formed so as to contact the fifth impurity region and the sixth impurity region. 
     Preferably, the method includes: 
     causing the wiring semiconductor layer to contain a donor or acceptor impurity; 
     forming a seventh impurity region in the first semiconductor pillar by thermally diffusing the donor or acceptor impurity of the wiring semiconductor layer into the first semiconductor pillar through a heat treatment; and 
     forming SGTs of the same conductivity type above and below the seventh impurity region. 
     Advantageous Effects of Invention 
     According to the present invention, in an SGT-including semiconductor device, bending or collapsing of a semiconductor pillar that would occur when an alloy layer is formed in a metal wiring layer electrically connected to a semiconductor region or gate conductor region in the center portion of the semiconductor pillar is suppressed. Thus, the connection between semiconductor region or gate conductor region and a wiring metal layer connected to the alloy layer can be reliably established. 
     Other features which are considered as characteristic for the invention are set forth in the appended claims. 
     Although the invention is illustrated and described herein as embodied in sgt-including semiconductor device and method for manufacturing the same, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims. 
     The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
         FIG. 1A  includes a plan view (a) and cross-sectional views (b) and (c) of a CMOS inverter circuit illustrating a method for manufacturing an SGT-including semiconductor device according to a first embodiment of the present invention. 
         FIG. 1B  includes a plan view (a) and cross-sectional views (b) and (c) of a CMOS inverter circuit illustrating the method for manufacturing an SGT-including semiconductor device according to the first embodiment of the present invention. 
         FIG. 1C  includes a plan view (a) and cross-sectional views (b) and (c) of a CMOS inverter circuit illustrating the method for manufacturing an SGT-including semiconductor device according to the first embodiment of the present invention. 
         FIG. 1D  includes a plan view (a) and cross-sectional views (b) and (c) of a CMOS inverter circuit illustrating the method for manufacturing an SGT-including semiconductor device according to the first embodiment of the present invention. 
         FIG. 1E  includes a plan view (a) and cross-sectional views (b) and (c) of a CMOS inverter circuit illustrating the method for manufacturing an SGT-including semiconductor device according to the first embodiment of the present invention. 
         FIG. 1F  includes a plan view (a) and cross-sectional views (b) and (c) of a CMOS inverter circuit illustrating the method for manufacturing an SGT-including semiconductor device according to the first embodiment of the present invention. 
         FIG. 1G  includes a plan view (a) and cross-sectional views (b) and (c) of a CMOS inverter circuit illustrating the method for manufacturing an SGT-including semiconductor device according to the first embodiment of the present invention. 
         FIG. 1H  includes a plan view (a) and cross-sectional views (b) and (c) of a CMOS inverter circuit illustrating the method for manufacturing an SGT-including semiconductor device according to the first embodiment of the present invention. 
         FIG. 1I  includes a plan view (a) and cross-sectional views (b) and (c) of a CMOS inverter circuit illustrating the method for manufacturing an SGT-including semiconductor device according to the first embodiment of the present invention. 
         FIG. 1J  includes a plan view (a) and cross-sectional views (b) and (c) of a CMOS inverter circuit illustrating the method for manufacturing an SGT-including semiconductor device according to the first embodiment of the present invention. 
         FIG. 1K  includes a plan view (a) and cross-sectional views (b) and (c) of a CMOS inverter circuit illustrating the method for manufacturing an SGT-including semiconductor device according to the first embodiment of the present invention. 
         FIG. 1L  includes a plan view (a) and cross-sectional views (b) and (c) of a CMOS inverter circuit illustrating the method for manufacturing an SGT-including semiconductor device according to the first embodiment of the present invention. 
         FIG. 1M  includes a plan view (a) and cross-sectional views (b) and (c) of a CMOS inverter circuit illustrating the method for manufacturing an SGT-including semiconductor device according to the first embodiment of the present invention. 
         FIG. 2A  includes a plan view (a) and cross-sectional views (b) and (c) of a CMOS inverter circuit illustrating a method for manufacturing an SGT-including semiconductor device according to a second embodiment of the present invention. 
         FIG. 2B  includes a plan view (a) and cross-sectional views (b) and (c) of a CMOS inverter circuit illustrating the method for manufacturing an SGT-including semiconductor device according to the second embodiment of the present invention. 
         FIG. 2C  includes a plan view (a) and cross-sectional views (b) and (c) of a CMOS inverter circuit illustrating the method for manufacturing an SGT-including semiconductor device according to the second embodiment of the present invention. 
         FIG. 2D  includes a plan view (a) and cross-sectional views (b) and (c) of a CMOS inverter circuit illustrating the method for manufacturing an SGT-including semiconductor device according to the second embodiment of the present invention. 
         FIG. 2E  includes a plan view (a) and cross-sectional views (b) and (c) of a CMOS inverter circuit illustrating the method for manufacturing an SGT-including semiconductor device according to the second embodiment of the present invention. 
         FIG. 3  includes a plan view (a) and cross-sectional views (b) and (c) of a CMOS inverter circuit illustrating a method for manufacturing an SGT-including semiconductor device according to a third embodiment of the present invention. 
         FIG. 4  includes a plan view (a) and cross-sectional views (b) and (c) of a CMOS inverter circuit illustrating a method for manufacturing an SGT-including semiconductor device according to a fourth embodiment of the present invention. 
         FIG. 5  includes a plan view (a) and cross-sectional views (b) and (c) of a CMOS inverter circuit illustrating a method for manufacturing an SGT-including semiconductor device according to a fifth embodiment of the present invention. 
         FIG. 6A  includes a plan view (a) and cross-sectional views (b) and (c) of a CMOS inverter circuit illustrating a method for manufacturing an SGT-including semiconductor device according to a sixth embodiment of the present invention. 
         FIG. 6B  includes a plan view (a) and cross-sectional views (b) and (c) of a CMOS inverter circuit illustrating the method for manufacturing an SGT-including semiconductor device according to the sixth embodiment of the present invention. 
         FIG. 7A  includes a plan view (a) and cross-sectional views (b) and (c) of a CMOS inverter circuit illustrating a method for manufacturing an SGT-including semiconductor device according to a seventh embodiment of the present invention. 
         FIG. 7B  includes a plan view (a) and cross-sectional views (b) and (c) of a CMOS inverter circuit illustrating the method for manufacturing an SGT-including semiconductor device according to the seventh embodiment of the present invention. 
         FIG. 8  is a schematic diagram of an SGT of related art. 
         FIG. 9  is a schematic diagram of a CMOS inverter circuit of related art, in which an N-channel SGT is formed in a lower portion of a single Si pillar and a P-channel SGT is formed in an upper portion of the single Si pillar. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     An SGT-including semiconductor device and a manufacturing method therefor according to embodiments of the present invention will now be described with reference to the drawings. 
     First Embodiment 
     A method for manufacturing a CMOS inverter circuit, which is an SGT-including semiconductor device, according to a first embodiment of the present invention will now be described with reference to  FIGS. 1A to 1M . 
       FIG. 1A  includes a plan view and cross-sectional views illustrating a first step of an SGT-including CMOS inverter circuit. Part (a) is a plan view, part (b) is a cross-sectional view taken along line X-X′ in (a), and part (c) is a cross-sectional view taken along line Y-Y′ in (a). The relationship between the diagrams in part (a), part (b), and part (c) is the same for other drawings referred in the description below. 
     As illustrated in  FIG. 1A , an N +  region  2  containing a donor impurity such as arsenic (As) is formed on an i-layer substrate  1  by an ion implantation method or an epitaxial growth method. Next, a P +  region  3  containing an acceptor impurity such as boron (B) is formed on the N +  region  2  by an ion implantation method or an epitaxial growth method. An i-region  4  is formed on the P +  region  3  by an epitaxial growth method. Then a SiO 2  layer  5  is formed on the i-region  4  by a thermal oxidation method. 
     Next, as illustrated in  FIG. 1B , the SiO 2  layer  5  is etched by performing a lithographic method and a reactive ion etching (RIE) method so as to form a SiO 2  layer  5   a . The i-region  4 , the P +  region  3 , the N +  region  2 , and the i-layer substrate  1  are then etched by a RIE method using the SiO 2  layer  5   a  as a mask so as to form a Si pillar  6  that includes an i-region  4   a , a P +  region  3   a , a N +  region  2   a , and an i-region  1   a . The cross-sectional shape of the Si pillar  6  is preferably round as illustrated in (a). 
     Next, as illustrated in  FIG. 10 , an N +  region  7  is formed in the surface of the i-layer substrate  1  at the outer periphery of the Si pillar  6  by an ion implantation method. Then a SiO 2  film is deposited by a chemical vapor deposition (CVD) method, the surface is planarized by a mechanical chemical polishing (MCP) method, and the SiO 2  film is etched by an etch back method so as to have a SiO 2  layer  8  remain on the i-layer substrate  1  at the outer periphery of the Si pillar  6 . Then atomic layer deposition (ALD) is employed to coat the entire Si pillar  6  and SiO 2  layer  8  with a hafnium oxide (HfO 2 ) layer  9  and a titanium nitride (TiN) layer  10 . Then the Si pillar  6  and the entire peripheral area of the Si pillar  6  are coated with a SiO 2  layer  11  by a CVD method. 
     Next, as illustrated in  FIG. 1D , the SiO 2  layer  11  and the titanium nitride (TiN) layer  10  are etched by a RIE method using a mask formed of a resist formed by a lithographic method so as to form a SiO 2  layer  11   a  and a TiN layer  10   a  that cover the Si pillar  6  and connect to the upper part of the SiO 2  layer  8 . 
     Next, as illustrated in  FIG. 1E , a silicon nitride (SiN) layer  12  is formed at the outer periphery of the Si pillar  6 . The SiN layer  12  is formed so that the position of its surface is at the same height as the lower end of the N +  region  2   a  formed in the Si pillar  6 . Then a resist layer  13  is formed on the SiN layer  12 . The resist layer  13  is formed so that the position of its surface is at the same height as the upper end of the P +  region  3   a . The resist layer  13  is formed by applying a resist material over the entire i-layer substrate  1  and performing a heat treatment at 200° C., for example, so as to increase the flowability of the resist material and to allow the resist material to evenly collect on the SiN layer  12  on the outer side of the Si pillar  6 . Then hydrogen fluoride gas (hereinafter referred to as “HF gas”) is supplied to all parts. Subsequently, a heating environment of 180° C. is created so as to thermally diffuse the HF gas into the resist layer  13  and ionize the HF gas by the moisture contained in the resist layer  13 . As a result, hydrogen fluoride ions (hereinafter referred to as “HF ions”) (HF 2   + ) are formed. The HF ions thermally diffuse into the resist layer  13  and etch the SiO 2  layer  11   a  in contact with the resist layer  13  (refer to Non Patent Literature 3 for the mechanism of etching). In contrast, the SiO 2  layer  11   a  not in contact with the resist layer  13  remains substantially unetched. Then the resist layer  13  is removed. 
     As illustrated in  FIG. 1F , the SiO 2  layer  11   a  is divided into a SiO 2  layer  11   b  in a region covered with the SiN layer  12  and a SiO 2  layer  11   c  in an upper region of the Si pillar  6 . Then the TiN layer  10   a  is etched by using the SiO 2  layers  11   b  and  11   c  as a mask. As a result, the TiN layer  10   a  is divided into a TiN layer  10   b  covered with the SiO 2  layer  11   b  and a TiN layer  10   c  covered with the SiO 2  layer  11   c  in the upper region of the Si pillar  6 . Then the HfO 2  layer  9  is etched by using the TiN layers  10   b  and  10   c  as a mask so as to divide the HfO 2  layer  9  into a HfO 2  layer  9   a  covered with the TiN layer  10   b  and a HfO 2  layer  9   b  in the upper region of the Si pillar  6 . A SiO 2  film is then deposited over the entire Si pillar  6  and SiN layer  12 . Application of a resist layer, a heat treatment at 200° C., supplying of HF gas, etching of the SiO 2  film by a heat treatment at 180° C., and removal of the resist layer are performed as in the method indicated in  FIG. 1E  so as to form an opening  21   a  that exposes the outer peripheries of the N +  region  2   a  and the P +  region  3   a . In forming the opening  21   a , a SiO 2  layer  14   a  remains on the HfO 2  layer  9   a , the TiN layer  10   b , the SiO 2  layer  11   b , and the SiN layer  12  and a SiO 2  layer  14   b  remains so as to surround the HfO 2  layer  9   b , the TiN layer  10   c , and the SiO 2  layer  11   c  at the upper portion of the Si pillar  6 . 
     As illustrated in  FIG. 1G , a polycrystalline silicon (hereinafter referred to as “poly Si”) film is deposited by a CVD method so that the surface position thereof is higher than the Si pillar  6  and then the surface is planarized by a CMP method. The poly Si film is etched by an etch back method so that the height of the surface of the poly Si film is close to the upper end of the opening  21   a . Then poly Si etching is performed by a lithographic method and RIE so as to form a poly Si layer  15  that is in contact with the N +  region  2   a  and the P +  region  3   a  and is connected to the outer periphery of the Si pillar  6 . 
     Then, as illustrated in  FIG. 1H , a heat treatment at, for example, 850° C. is performed so as to have the donor impurity (As) in the N +  region  2   a  and the acceptor impurity (B) in the P +  region  3   a  to thermally diffuse into the poly Si layer  15 . As a result, an N +  region  16  and a P +  region  17  are formed in the poly Si layer  15 . The diffusion coefficient of As atoms into Si (5×10 −16  cm 2 /sec) is smaller than the diffusion coefficient of B (1×10 −14  cm 2 /sec) and the solubility limit of As atoms in Si (2×10 21 /cm 3 ) is larger than the solubility limit of B atoms in Si (4×10 20 /cm 3 ). Thus, when As is contained in the N +  region  2   a  and B in the P +  region  3   a  up to their solubility limits, the outer peripheral end of the P +  region  17  in the poly Si layer  15  comes to be located on the outer side of the N +  region  16 . Moreover, impurities contained in the N +  region  2   a , the N +  region  7 , and the P +  region  3   a  diffuse into the Si pillar  6  and the i-layer substrate  1 . As a result, the N +  region  2   a  turns into an N +  region  2   b , the P +  region  3   a  turns into a P +  region  3   b , and the N +  region  7  turns into an N +  region  7   a . The shape of the portion where the N +  region  16  comes into contact with the P +  region  17  is determined by the diffusion pattern of N +  region  16  having a high donor impurity concentration. Then a nickel (Ni) layer  18  is deposited on all parts by an ALD method. 
     Next, as illustrated in  FIG. 1I , a heat treatment is performed at 650° C., for example, so as to form nickel silicide (NiSi) layers  19   a  and  19   b  in the upper surface layer of the poly Si layer  15 . The NiSi layer  19   a  is formed in a side surface of the poly Si layer  15  and the NiSi layer  19   b  is formed in the surface layer and the side surface of the poly Si layer  15 . The NiSi layers  19   a  and  19   b  are formed so as to be connected to each other and the NiSi layer  19   a  comes into contact with the N +  region  16  and the P +  region  17 . As illustrated in  FIG. 1I (c), the NiSi layer  19   a  formed in the side surface of the poly Si layer  15  is formed so as to be in contact with the N +  region  16  and the P +  region  17  even in the Y-Y′ direction in plan view. Then the Ni layer  18  is removed. 
     As illustrated in  FIG. 1J , a SiN layer  20  having a surface position located in the middle position in the height direction of the TiN layer  10   c  is formed by the same method as the method for forming the SiN layer  12 . Then an opening  21   b  is formed at the outer periphery of the TiN layer  10   c  by the same method as the method for forming the opening  21   a . A poly Si layer  22  is then formed by the same method as the method for forming the poly Si layer  15 . Then a NiSi layer  23   a  is formed in the side surface of the poly Si layer  22  and a NiSi layer  23   b  is formed in the upper surface layer and the side surface of the poly Si layer  22  by the same method as the method for forming the NiSi layers  19   a  and  19   b . The NiSi layers  23   a  and  23   b  are connected to each other. The NiSi layer  23   a  is in contact with the TiN layer  10   c . As illustrated in  FIG. 1J (c), the NiSi layer  23   a  formed in the side surface of the poly Si layer  22  is formed to contact the TiN layer  10   c  also in the Y-Y′ direction in plan view. 
     Next, as illustrated in  FIG. 1K , a resist film is applied to all parts and the entire resist film is etched back evenly from the surface so as to form a resist layer  25  having a surface positioned to be higher than the surface of the poly Si layer  22  and lower than the top portion of the Si pillar  6 . The SiO 2  layer  14   b , the SiO 2  layer  11   c , the TiN layer  10   c , and the HfO 2  layer  9   b  are etched by using the resist layer  25  as a mask to form a SiO 2  layer  14   c , a SiO 2  layer  11   d , a TiN layer  10   d , and a HfO 2  layer  9   c . Then the resist layer  25  is removed. 
     As illustrated in  FIG. 1L , a P +  region  26  is formed in the top portion of the Si pillar  6  by performing a boron (B) ion implantation method by using the SiO 2  layer  14   c , the SiO 2  layer  11   d , the TiN layer  10   d , and the HfO 2  layer  9   c  as a mask. Subsequently, a SiO 2  layer  27  is formed on all parts by a CVD method. A contact hole  28   b  is formed on the top portion of the Si pillar  6  by a lithographic method and a RIE method and a contact hole  28   d  is formed on an N +  region  7   b . A NiSi layer  30   a  is formed in the top portion of the Si pillar  6  at the bottom of the contact hole  28   b  and a NiSi layer  30   b  is formed in the surface layer of the N +  region  7   b  at the bottom of the contact hole  28   d . A contact hole  28   a  is formed on the TiN layer  10   b  so as to penetrate the poly Si layer  22  and a contact hole  28   c  is formed on the NiSi layer  19   b  in the upper surface layer of the poly Si layer  15 . 
     Next, as illustrated in  FIG. 1M , an input wiring metal layer Vin electrically connected to the NiSi layer  23   b , the poly Si layer  22 , and the TiN layer  10   b  through the contact hole  28   a  is formed and a power supply wiring metal layer Vdd electrically connected to the NiSi layer  30   a  and the P +  region  26  in the top portion of the Si pillar through the contact hole  28   b  is formed. An output wiring metal layer Vout electrically connected to the NiSi layer  19   a , the NiSi layer  19   b , the N +  region  2   b , the N +  region  16 , the P +  region  3   b , the P +  region  17 , and the poly Si layer  15  through the contact hole  28   c  is formed. A ground wiring metal layer Vss electrically connected to the NiSi layer  30   b  and the N +  region  7   b  through the contact hole  28   d  is formed. 
     By using the manufacturing method described above, a CMOS inverter circuit having an N-channel SGT and a P-channel SGT is formed, in which the N-channel SGT includes the i-region  1   a  serving as a channel in the lower portion of the Si pillar  6 , the HfO 2  layer  9   a  surrounding the outer periphery of the i-region  1   a  and serving as a gate insulating layer, the TiN layer  10   b  surrounding the outer periphery of the HfO 2  layer  9   a  and serving as a gate conductor layer, the N +  region  7   b  serving as a source located in the lower portion of the i-region  1   a , and the N +  region  2   b  serving as a drain located on the i-region  1   a  and in which the P-channel SGT includes the i-region  4   a  serving as a channel in the upper portion of the Si pillar  6 , the HfO 2  layer  9   c  surrounding the outer periphery of the i-region  4   a  and serving as a gate insulating layer, the TiN layer  10   d  surrounding the outer periphery of the HfO 2  layer  9   c  and serving as a gate conductor layer, the P +  region  3   b  serving as a source located in the lower portion of the i-region  4   a , and the P +  region  26  serving as a drain located on the i-region  4   a.    
     The CMOS inverter circuit of the first embodiment exhibits the following effects. 
     1. The N +  region  2   b  and the P +  region  3   b  in the central portion of the Si pillar  6  are connected to the NiSi layers  19   a  and  19   b  through the N +  region  16  and the P +  region  17  formed so as to spread inside the poly Si layer  15  on the outer side of the N +  region  2   b  and the P +  region  3   b . As such, the NiSi layers  19   a  and  19   b , which cause bending and collapsing of the Si pillar  6  due to large stress-induced strain in the Si pillar  6  generated by a difference in thermal expansion coefficient from Si, are formed within the poly Si layer  15  formed so as to surround the outer periphery of the Si pillar  6 . Accordingly, bending and collapsing of the Si pillar  6  are prevented.
 
2. Since the poly Si layer  15  is formed to surround the Si pillar  6 , the poly Si layer  15  serves as a material layer for preventing bending and collapsing of the Si pillar  6 . Thus, bending and collapsing of the Si pillar  6  can be more effectively prevented.
 
3. The NiSi layer  19   a  formed in the side surface of the poly Si layer  15  contributes to establishing a low-resistance connection between the N +  region  2   b  and the P +  region  3   b  and the NiSi layer  19   b  formed in the upper surface layer of the poly Si layer  15  contributes to establishing a low-resistance connection to the output wiring metal layer Vout connected to the contact hole  28   c  formed on the NiSi layer  19   b . Since the NiSi layers  19   a  and  19   b  are connected to each other, the N +  region  2   b  and the P +  region  3   b  are connected to the output wiring metal layer Vout at low resistance. Accordingly, even when the NiSi layer  19   b  in the upper surface layer of the poly Si layer  15  is not directly connected to the P +  region  17  and the N +  region  16 , a low-resistance connection between the N +  region  2   b  and the output wiring metal layer Vout and between the P +  region  3   b  and the output wiring metal layer Vout can be securely established.
 
4. In the poly Si layer  15  on the left side of the Si pillar  6  illustrated in  FIG. 1I (b), the NiSi layer  19   a  is in contact with the N +  region  16  and the P +  region  17  and is formed to spread inward from the side surface of the poly Si layer  15 . Since the N +  region  16  and the P +  region  17  are surrounded by the NiSi layer  19   a , the effect of sweeping the impurity contained in the NiSi layer  19   a  is accelerated and the donor and acceptor impurities gather around the border between the NiSi layer  19   a  and the N +  region  16  and the border between the NiSi layer  19   a  and the P +  region  17 . As a result, the contact resistance between the NiSi layer  19   a  and the N +  region  16  and between the NiSi layer  19   a  and the P +  region  17  can be further decreased.
 
5. The poly Si layer  22  connected to the TiN layer  10   d  is formed so as to surround the Si pillar  6  and thus serves as a material layer that prevents bending or collapsing of the Si pillar  6 . Accordingly, bending and collapsing of the Si pillar  6  can be prevented.
 
6. The NiSi layer  23   a  formed in the side surface of the poly Si layer  22  is connected to the TiN layer  10   d  at low resistance and the NiSi layer  23   b  formed in the upper surface layer and the side surface of the poly Si layer  22  is connected at low resistance to the input wiring metal layer Vin connected to the contact hole  28   a  penetrating the NiSi layer  23   b . Since the NiSi layer  23   a  and the NiSi layer  23   b  are connected to each other, the TiN layer  10   d  is connected to the input wiring metal layer Vin at low resistance. Accordingly, even when the NiSi layer  23   b  in the upper surface layer of the poly Si layer  22  is not directly connected to the TiN layer  10   d , a low-resistance connection between the TiN layer  10   d  and the input wiring metal layer Vin can be securely established.
 
7. As illustrated in  FIG. 1M (c), the NiSi layer  19   a  formed in the side surface of the poly Si layer  15  is formed so as to contact the N +  region  16  and the P +  region  17  also in the Y-Y′ direction when viewed in plan. Accordingly, the low-resistance connection between the NiSi layer  19   a  and the P +  region  17  and the low-resistance connection between the NiSi layer  19   a  and the N +  region  16  are established in three directions when viewed in plan. Similarly, the NiSi layer  23   a  formed in the side surface of the poly Si layer  22  is formed to contact the TiN layer  10   c  even in the Y-Y′ direction when viewed in plan. Accordingly, a low-resistance connection between the NiSi layer  23   a  and the TiN layer  10   d  is established in three directions when viewed in plan.
 
     Second Embodiment 
     A method for manufacturing a CMOS inverter circuit, which is an SGT-including semiconductor device, according to a second embodiment of the present invention will now be described with reference to  FIGS. 2A to 2E . 
     As illustrated in  FIG. 2A , a N +  region  2  containing a donor impurity such as arsenic (As), for example, is formed on an i-layer substrate  1  by an ion implantation method or an epitaxial growth method. An i-region  4  is then formed on the N +  region  2  by an epitaxial growth method. A SiO 2  layer  5  is then formed on the i-region  4  by a thermal oxidation method. 
     Next, as illustrated in  FIG. 2B , the SiO 2  layer  5  is etched by performing a lithographic method and a reactive ion etching (RIE) method to form a SiO 2  layer  5   a . The i-region  4 , the N +  region  2 , and the i-layer substrate  1  are etched by a RIE method using the SiO 2  layer  5   a  as a mask so as to form a Si pillar  6  constituted by an i-region  4   a , an N +  region  2   a , and an i-region  1   a . The cross-sectional shape of the Si pillar is preferably round as illustrated in  FIG. 2B (a). Then the same steps as the steps of the method for manufacturing a semiconductor device illustrated in  FIGS. 10 to 1F  are performed. 
     Then, as illustrated in  FIG. 2C , a P +  poly Si layer  15   a  is formed instead of the poly Si layer  15  in  FIG. 1G . The P +  poly Si layer  15   a  contains, for example, a large amount of boron (B) acceptor impurity. 
     Next, as illustrated in  FIG. 2D , a heat treatment is performed at, for example, 850° C. so as to thermally diffuse the donor impurity (As) contained in the N +  region  2   a  into the P +  poly Si layer  15   a  and to form an N +  region  16   a  in the P +  poly Si layer  15   a . At the same time, the acceptor impurity (B) contained in the P +  poly Si layer  15   a  is thermally diffused into the Si pillar  6  so as to form a P +  region  3   c  in the Si pillar  6  so that the P +  region  3   c  comes into contact with the N +  region  2   b . The solubility limit of As atoms in Si (2×10 21 /cm 3 ) is larger than the solubility limit of B atoms in Si (4×10 20 /cm 3 ). Thus, when As is contained in the N +  region  2   a  and B in P +  poly Si layer  15   a  up to their solubility limits, the shape of the portion where the N +  region  16   a  comes into contact with the P +  poly Si layer  15   a  is determined by the diffusion pattern of the N +  region  16   a  having a high donor impurity concentration. Moreover, when the acceptor impurity concentration in the P +  poly Si layer  15   a  is lower than the donor impurity concentration in the N +  region  2   a , the shape of the portion where the N +  region  16   a  comes into contact with the P +  poly Si layer  15   a  is determined by the diffusion pattern of the N +  region  16   a  having a high donor impurity concentration. Next, a nickel (Ni) layer  18  is deposited on all parts by an ALD method. Then the same steps as those illustrated in  FIGS. 11 to 1M  are performed. 
     As a result, as illustrated in  FIG. 2E , the NiSi layer  19   a  formed in the side surface of the P +  poly Si layer  15   a  connects to the P +  poly Si layer  15   a  and the N +  region  16   a . Then the NiSi layer  19   a  electrically connects to the N +  region  2   b  and the P +  region  3   c  in the Si pillar  6 . The NiSi layer  19   b  formed in the upper surface layer and the side surface of the P +  poly Si layer  15   a  is connected to the output wiring metal layer Vout through the contact hole  28   c . The NiSi layers  19   a  and  19   b  are connected to each other. Accordingly, a low-resistance connection is established between the N +  region  2   b  and the output wiring metal layer Vout and between the P +  region  3   c  and the output wiring metal layer Vout. As a result, a CMOS inverter circuit that includes an SGT similar to the CMOS inverter circuit according to the first embodiment is obtained. 
     The CMOS inverter circuit of the second embodiment exhibits the following effects. 
     1. Whereas the P +  region  3  is formed first in the step illustrated in  FIG. 1A  in the first embodiment, there is no need to form the P +  region  3  in the second embodiment, as illustrated in  FIG. 2A . The manufacturing method of the second embodiment is simpler than that of the first embodiment.
 
2. In the first embodiment, as illustrated in  FIG. 1M (b), the P +  region  17  is distanced from the NiSi layer  19   b  in the poly Si layer  15  on the right side of the Si pillar  6 . In contrast, in the second embodiment, the P +  poly Si layer  15   a , which is a P +  region as a whole, is electrically connected to the output wiring metal layer Vout through the NiSi layer  19   b  formed in the upper surface layer of the P +  poly Si layer  15   a  and the contact hole  28   c . Accordingly, according to the second embodiment, the connection resistance between the P +  region  3   c  and the output wiring metal layer Vout can be made lower than that in the first embodiment.
 
     In order to manufacture a circuit in which the N +  region  2   b  and the P +  region  3   b  are constituted by impurity regions of the same conductivity type, there is no need to form the N +  region  2  in  FIG. 2A . In this case, the P +  poly Si layer  15   a  illustrated in  FIG. 2C  can form a particular impurity region in the Si pillar  6  by thermal diffusion from the poly Si layer containing an impurity, which is either a donor or an acceptor, into the Si pillar  6 . 
     Third Embodiment 
     A CMOS inverter circuit, which is an SGT-including semiconductor device, according to a third embodiment of the present invention will now be described with reference to  FIG. 3 . 
       FIG. 3  includes a plan view and cross-sectional views of the third embodiment. The CMOS inverter circuit according to the third embodiment is obtained by the same steps as those of the first embodiment illustrated in  FIGS. 1A to 1M  but has the following structural differences. In the third embodiment, the contact hole  28   c  includes a NiSi layer  19   c  formed in the upper surface layer of a poly Si layer  15   b  and the side surface connected to the upper surface layer. The NiSi layer  19   c  is connected to the output wiring metal layer Vout through the contact hole  28   c . The contact hole  28   a  penetrates a NiSi layer  23   c  formed on the upper surface layer and side surface of a poly Si layer  22   a  and is connected to the TiN layer  10   b . The TiN layer  10   b  and the NiSi layer  23   c  are connected to the input wiring metal layer Vin through the contact hole  28   a . The NiSi layer  23   a  formed in the side surface of the poly Si layer  22   a  is connected to the TiN layer  10   d  and the NiSi layers  23   a  and  23   c  are connected to each other. As a result, the input wiring metal layer Vin is electrically connected to the TiN layer  10   d  through the NiSi layers  23   c  and  23   a . Here, the thickness of the poly Si layer  15   b  and the thickness of the poly Si layer  22   a  are preferably larger than ½ of a length of one side of the contact holes  28   a  and  28   c.    
     The CMOS inverter circuit of the third embodiment exhibits the following effects. 
     1. In the first embodiment, as illustrated in  FIG. 1M (a), the contact hole  28   c  is formed on the inner side of the outer periphery of the poly Si layer  15   b . In contrast, in the third embodiment, the outer periphery of the poly Si layer  15   b  lies within the cross-section of the contact hole  28   c  in plan view. Thus, the length of the poly Si layer  15   b  in the X-X′ direction can be decreased. Similarly, when the outer periphery of the poly Si layer  22   a  is arranged to lie within to cross section of the contact hole  28   a  in plan view, the length of the poly Si layer  22   a  in the X-X′ direction can be decreased. As a result, the area occupied by the CMOS inverter circuit in plan view can be decreased and the degree of circuit integration can be increased.
 
2. Since the thickness of the poly Si layer  15   b  is more than ½ of the length (width) of the contact hole  28   c  in the X-X′ direction, the contact area between the output wiring metal layer Vout and the NiSi layer  19   c  is increased and the contact resistance between the output wiring metal layer Vout and the NiSi layer  19   c  can be decreased. Similarly, since the thickness of the poly Si layer  22   a  is larger than ½ of the length of the contact hole  28   a  in the X-X′ direction, the contact area between the input wiring metal layer Vin and the NiSi layer  23   c  can be increased and the contact resistance between the input wiring metal layer Vin and the NiSi layer  23   c  can be decreased. Increasing the thickness of the poly Si layers  15   b  and  22   a  will not decrease the degree of integration of the CMOS inverter circuit. Thus, the contact resistance between the output wiring metal layer Vout and the NiSi layer  19   c  and the contact resistance between the input wiring metal layer Vin and the NiSi layer  23   c  can be decreased without decreasing the degree of integration of the CMOS inverter circuit.
 
     Fourth Embodiment 
     An SGT-including CMOS inverter circuit, which is a semiconductor device according to a fourth embodiment of the present invention, will now be described with reference to  FIG. 4 . 
       FIG. 4  includes a plan view ( FIG. 4( a ) ), a cross-sectional view ( FIG. 4( b ) ), and another cross-sectional view ( FIG. 4( c ) ) of a CMOS inverter circuit in which a P-channel SGT is formed in a Si pillar  32   a  and an N-channel SGT is formed in a Si pillar  32   b.    
     As illustrated in  FIG. 4 , the Si pillars  32   a  and  32   b  are formed on an i-layer substrate  31 . A P +  region  33   a  is formed in the bottom portion of the Si pillar  32   a  and the surface layer portion of the i-layer substrate  31  connected to the bottom portion and an N +  region  34   a  is formed in the bottom portion of the Si pillar  32   a  and the surface layer portion of the i-layer substrate  31  connected to the bottom portion. A SiO 2  layer  35  is formed on the i-layer substrate  31  at the outer peripheries of the Si pillars  32   a  and  32   b . A P +  region  33   b  is formed in the top portion of the Si pillar  32   a  and an N +  region  34   b  is formed in the top portion of the Si pillar  32   b . A H f O 2  layer  36   a  is formed so as to surround an i-region  45   a  between the P +  regions  33   a  and  33   b . A H f O 2  layer  36   b  is formed so as to surround an i-region  45   b  between the N +  regions  34   a  and  34   b . A TiN layer  37   a  is formed so as to surround the H f O 2  layer  36   a  and a TiN layer  37   b  is formed so as to surround the H f O 2  layer  36   b.    
     SiO 2  layers  38   a  and  38   b  are formed so as to surround the TiN layers  37   a  and  37   b . By the same method as the method for forming the opening  21   b  in the first embodiment (refer to  FIG. 1J ), an opening  46   a  of the SiO 2  layer  38   a  is formed at the outer periphery of the TiN layer  37   a  and an opening  46   b  of the SiO 2  layer  38   b  is formed at the outer periphery of the TiN layer  37   b . By the same method as the method for forming the poly Si layer  22  in the first embodiment (refer to  FIG. 1 j   ), a poly Si layer  40  connected between the Si pillars  32   a  and  32   b  and in contact with the TiN layers  37   a  and  37   b  is formed. By the same method as the method for forming the NiSi layers  19   a  and  19   b  in the first embodiment (refer to  FIG. 1J ), a NiSi layer  41   a  and a NiSi layer  41   b  are formed in the side surfaces of the poly Si layer  40  and a NiSi layer  41   c  is formed in the upper surface layer and side surfaces of the poly Si layer  40 . The NiSi layer  41   a  is in contact with the TiN layer  37   a  and the NiSi layer  41   b  is in contact with the TiN layer  37   b . The NiSi layers  41   a ,  41   b , and  41   c  are connected to one another. A SiO 2  layer  42  is formed to cover the entirety and contact holes  43   a ,  43   b ,  43   c , and  43   d  are formed in the SiO 2  layer  42 . The NiSi layer  41   e  is formed in the upper surface layer of the P +  region  33   b , a NiSi layer  41   d  is formed in the upper surface layer of an N +  region  34   b , and the NiSi layer  41   f  is formed on the border between the P +  region  33   a  and the N +  region  34   a . A power supply wiring metal layer Vdd connected to the NiSi layer  41   a  through the contact hole  43   a , an input wiring metal layer Vin connected to the NiSi layer  41   c  through the contact hole  43   b , a ground wiring metal layer Vss connected to the NiSi layer  43   c  through the contact hole  43   c , and an output wiring metal layer Vout connected to the NiSi layer  41   f  through the contact hole  43   d  are formed. 
     As illustrated in  FIG. 4 , a P-channel SGT in which the P +  region  33   b  serves as a source, the P +  region  33   a  serves as a drain, the H f O 2  layer  36   a  serves as a gate insulating layer, the TiN layer  37   a  serves as a gate conductor layer, and the i-region  45   a  serves as a channel is formed in the Si pillar  32   a . An N-channel SGT in which the N +  region  34   a  serves as a source, the N +  region  34   b  serves as a drain, the H f O 2  layer  36   b  serves as a gate insulating layer, the TiN layer  37   b  serves as a gate conductor layer, and the i-region  45   b  serves as a channel is formed in the Si pillar  32   b.    
     In the fourth embodiment, the TiN layer  37   a  serving as the gate conductor layer of the P-channel SGT and the NiSi layer  41   a  formed in the side surface of the poly Si layer  40  are connected to each other at low resistance and the TiN layer  37   b  serving as the gate conductor layer of the N-channel SGT and the NiSi layer  41   b  formed in the side surface of the poly Si layer  40  are connected to each other at low resistance. Moreover, the NiSi layers  41   a  and  41   b  are connected to the NiSi layer  41   c  formed in the surface layer of the poly Si layer  40 . Since the contact hole  43   c  is formed on the NiSi layer  41   c , the input wiring metal layer Vin and the TiN layers  37   a  and  37   b  serving as the gate conductor layers of the P-channel SGT and the N-channel SGT are connected to one another at low resistance. 
     As discussed above, in the fourth embodiment, the poly Si layer  40  and the NiSi layer  41   c  formed in the surface layer of the poly Si layer  40  prevent bending and collapsing of the Si pillars  32   a  and  32   b , serve as a region for forming the contact hole  43   b  connected to the input wiring metal layer Vin, and also serve as a wiring layer that electrically connects the TiN layers  37   a  and  37   b  to each other. 
     Fifth Embodiment 
     An SGT-including CMOS inverter circuit, which is a semiconductor device according to a fifth embodiment of the present invention, will now be described with reference to  FIG. 5 . 
     The steps of manufacturing the semiconductor device according to the fifth embodiment are the same as those steps illustrated in  FIGS. 1A to 1M  in the first embodiment but the following structural differences arise. As illustrated in  FIG. 5 , a NiSi layer  48   a  is formed in the side surface of the poly Si layer  15  and a NiSi layer  48   b  is formed in the upper surface layer and the side surface of the poly Si layer. The NiSi layers  48   a  and  48   b  are each in contact with the N +  region  16  and the P +  region  17 . A NiSi layer  49   a  is formed in the side surface of the poly Si layer  22  and a NiSi layer  49   b  is formed in the upper surface layer and the side surface of the poly Si layer  22 . The NiSi layers  49   a  and  49   b  are each connected to the TiN layer  10   d.    
     Unlike in the first embodiment, in the fifth embodiment, each of the NiSi layers  48   a  and  48   b  is formed so as to contact the N +  region  16  and the P +  region  17  and each of the NiSi layers  49   a  and  49   b  is connected to the TiN layer  10   d . As a result, the N +  region  2   b , the P +  region  3   b , and the output wiring metal layer Vout are connected to one another at low resistance and the TiN layer  10   d  and the input wiring metal layer Vin are connected to each other at low resistance. 
     Sixth Embodiment 
     A CMOS inverter circuit, which is an SGT-including semiconductor device according to a sixth embodiment of the present invention, will now be described with reference to  FIGS. 6A and 6B . 
     As illustrated in  FIG. 6A , the same steps as those illustrated in  FIGS. 1A to 11  are performed to form an N +  region  16   b  and a P +  region  17   b  in the poly Si layer  15  by thermal diffusion from the N +  region  2   b  and the P +  region  3   b  in the Si pillar  6 . Then a NiSi layer  50   a  is formed in the side surface of the poly Si layer  15  and a NiSi layer  50   b  connected to the upper surface layer and the side surface of the poly Si layer  15  is formed. 
     Next, as illustrated in  FIG. 6B , the same steps as those illustrated in  FIGS. 1J to 1M  are performed to end manufacturing of a CMOS inverter circuit. At this stage, the NiSi layer  50   a  formed in the side surface of the poly Si layer  15  spreads to form a NiSi layer  50   c  and comes into contact with the N +  region  2   b  and the P +  region  3   b  in the Si pillar  6 . The impurity contained in the NiSi layer  50   b  spreads into the poly Si layer  15 , thereby forming a NiSi layer  50   d , a contact hole  28   c  is formed on the upper surface of the NiSi layer  50   d , and an output wiring metal layer Vout connected to the NiSi layer  50   d  through the contact hole  28   c  is formed. 
     Seventh Embodiment 
     An SGT-including semiconductor device according to a seventh embodiment of the present invention will now be described with reference to  FIGS. 7A and 7B . 
     In  FIG. 7A , the N +  region  2   a  illustrated in  FIG. 2C  is not formed in the Si pillar  6 . Instead of the P +  poly Si layer  15   a , an N +  poly Si layer  51  is formed. 
     A semiconductor device of this embodiment is obtained from the structure illustrated in  FIG. 7A  by the following method. That is, as illustrated in  FIG. 7B , an N +  region  52  is formed in the Si pillar  6  by thermal diffusion of the donor impurity from the N +  poly Si layer  51 . An N +  region  53  is formed in the top portion of the Si pillar  6 . Then the contact hole  28   c  is formed on the NiSi layer  19   b  formed in the side surface and the upper portion of the N +  poly Si layer  51 . A wiring metal layer V 2  is formed on the SiO 2  layer  27  so as to connect to the contact hole  28   c . A wiring metal layer V 1  electrically connected to the NiSi layer  23   b , the poly Si layer  22 , and the TiN layer  10   d  through the contact hole  28   a  is formed on the SiO 2  layer  27 . As a result, an N-channel SGT connected to the N +  region  52  is formed above the N +  region  52  and another N-channel SGT connected to the N +  region  52  is formed below the N +  region  52 . The gate TiN layers  10   b  and  10   d  of the two SGTs are electrically connected to the wiring metal layer V 1  through the contact hole  28   a . The N +  region  52  is electrically connected to a wiring metal layer V 2  through the N +  poly Si layer  51 , the NiSi layer  19   b , and the contact hole  28   c.    
     The seventh embodiment exhibits the following effects. 
     1. The N +  regions corresponding to the N +  region  2  and the P +  region  3  illustrated in  FIG. 1A  in the first embodiment can be formed by thermal diffusion from the N +  poly Si layer  51  in the seventh embodiment. Thus, the manufacturing process can be simplified.
 
2. In the first embodiment, as illustrated in  FIG. 1F , the opening  21   a  formed at the side surface of the Si pillar  6  needs to be aligned with the N +  region  2   a  and the P +  region  3   a . Since the N +  region  52  is formed by thermal diffusion from the N +  poly Si layer  51  after formation of the opening  21   a  in the seventh embodiment, there is no need to align the opening  21   a  and the N +  region  52  and thus the manufacturing process can be simplified.
 
     In  FIG. 1M  of the first embodiment, the NiSi layer  19   a  formed in the side surface of the poly Si layer  15  is electrically connected to the N +  region  2   b  and the P +  region  3   b  through the N +  region  16  and the P +  region  17 . In contrast, in the sixth embodiment, the N +  region  16   b  and the P +  region  17   b  are located between the NiSi layer  50   a  and the N +  region  2   b  and between the NiSi layer  50   a  and the P +  region  3   b  in the step illustrated in  FIG. 6A ; however, at the final stage of the manufacturing process, the NiSi layer  50   c  comes into direct contact with the N +  region  2   b  and the P +  region  3   b . In such a case, the donor and acceptor impurities in the N +  region  16   b  and the P +  region  17   b  in the poly Si layer  15  return to the interior of the Si pillar  6  by the impurity sweeping effect of the NiSi layer  50   a.    
     In the fifth embodiment also, the NiSi layers  50   a  and  50   b  are formed in the poly Si layer  15  formed at the outer peripheries of the N +  region  2   a  and the P +  region  3   a . Thus, bending and collapsing of the Si pillar  6  can be prevented. For example, in the case of forming a circuit that includes, on the same semiconductor substrate, a single-layer gate structure SGT having TiN layers  10   b  and  10   d  as illustrated in  FIG. 6B  and a nonvolatile memory SGT having a double-layer gate structure constituted by a floating gate and a control gate, the first embodiment can be applied to the single-layer gate structure SGT and the fifth embodiment can be applied to the double-layer gate structure SGT. In this manner, the electrical connections between impurity regions formed in the central portion of the Si pillar  6  and the wiring metal layers (output wiring metal layer Vout, input wiring metal layer Vin, etc.) formed in the circuit can be more reliably established. The technical idea of the present invention can also be applied to formation of a circuit that includes a nonvolatile memory SGT that uses a SiN layer as a charge storage layer instead of the floating gate. This applies to other embodiments of the present invention also. 
     In the embodiments described above, examples in which Si (silicon) pillars are used as the semiconductor pillars are described. However, this is not limiting. The technical idea of the present invention can also be applied to semiconductor devices with SGTs in which semiconductor pillars are composed of semiconductor materials other than silicon. 
     In the embodiments described above, a method for manufacturing a semiconductor device in which one or two SGTs are formed in one Si pillar is described. However, this is not limiting. The technical idea of the present invention can also be applied to a method for manufacturing a semiconductor device having three or more SGTs in one semiconductor pillar. 
     In the first embodiment, a semiconductor device in which an N-channel SGT is formed in the lower portion of the Si pillar  6  and a P-channel SGT is formed in the upper portion of the Si pillar  6  is described. However, the technical idea of the present invention can also be applied to a semiconductor device in which a P-channel SGT is formed in the lower portion of the Si pillar  6  and an N-channel SGT is formed in the upper portion of the Si pillar  6 . This applies to other embodiments of the present invention also. 
     The poly Si layer  15  of the first embodiment may be any material layer in which the N +  region  16  and the P +  region  17  are formed by thermal diffusion of the N +  region  2   a  and the P +  region  3   a  in the Si pillar  6  into the poly Si layer  15 . For example, the poly Si layer  15  may be a SiGe material layer or other material layer. This applies to other embodiments of the present invention also. 
     The poly Si layers  15  and  22  in the first embodiment may each be a single-crystal layer formed by an ALD method, a material layer close to a single crystal, or an amorphous layer, for example. This applies to other embodiments of the present invention also. 
     In the first embodiment, the case in which the donor impurity and the acceptor impurity are contained in the N +  region  2   a  and the P +  region  3   a  up to their solubility limits in silicon is described. However, the solubility limits in silicon need not be reached and the donor impurity concentration and the acceptor impurity concentration in the N +  region  2   a  and the P +  region  3   a  may be any impurity concentration that can realize the state in which the N +  region  2   b  is connected to the NiSi layer  19   a  through the N +  region  16  and the P +  region  3   b  is connected to the NiSi layer  19   a  through the P +  region  17 . This applies to other embodiments of the present invention also. 
     In the first embodiment, the NiSi layers  19   a  and  19   b  are all formed within the poly Si layer  15 . Alternatively, a portion of the NiSi layer  19   a  and a portion of the NiSi layer  19   b  may reach the Si pillar  6  through crystal grain boundaries between small single crystals of the poly Si layer  15  so that the NiSi layers  19   a  and  19  partly penetrate the Si pillar  6 . The effects of the present invention are still obtained in this case. Moreover, according to the present invention, even when the NiSi layers  19   a  and  19   b  partly penetrate the Si pillar  6 , the poly Si layer  15  surrounding the outer peripheries of the N +  region  2   a  and the P +  region  3   b  serve as material layers that prevent bending and collapsing of the Si pillar  6 . Thus, bending and collapsing of the Si pillar  6  are prevented. This applies to other embodiments of the present invention also. 
     In the first embodiment, at least the NiSi layer  19   a  formed in the side surface of the poly Si layer  15  needs to be in contact with the N +  region  16  and the P +  region  17 . Thus, as illustrated in  FIG. 1M (b), the NiSi layer  19   b  need not be in contact the N +  region  16  and the P +  region  17  but may make contact with the N +  region  16  and the P +  region  17 . This applies to other embodiments of the present invention also. 
     The NiSi layers  19   a ,  19   b ,  23   a , and  23   b  in the first embodiment may be other alloy layers as long as they can connect to the poly Si layer  15 , the poly Si layer  22 , the input wiring metal layer Vin, and the output wiring metal layer Vout at low resistance. For example, tantalum silicide (TaSi), tungsten silicide (WSi), titanium silicon (TiSi), cobalt silicon (CoSi), or the like may be used. This applies to other embodiments of the present invention also. 
     In the second embodiment, the N +  region  2   b  is formed in the Si pillar  6  and the P +  region  3   c  is formed by thermal diffusion of the donor impurity in the N +  region  2   b  into the P +  poly Si layer  15   a . However, this is not limiting. Alternatively, a P +  region  3   c  may be formed in the Si pillar  6 , an N+ poly Si layer having a lower donor impurity concentration than the P +  region  3   c  may be formed instead of the P +  poly Si layer  15   a , and the acceptor impurity of the P +  poly Si layer  15   a  may be thermally diffused into the N +  poly Si layer. 
     In the second embodiment, the N-channel SGT is formed in the lower portion of the Si pillar  6  and the P-channel SGT is formed in the upper portion of the Si pillar  6 . In the case where a P-channel SGT is formed in the lower portion of the Si pillar  6  and an N-channel SGT is formed in the upper portion of the Si pillar  6 , all needed is to change the conductivity type of each of the N +  regions  2   b  and  7   b , the P +  regions  3   c  and  26 , and the P +  poly Si layer  15   a  to a different conductivity type. Thus, the technical idea of the present invention can be applied. 
     In the second embodiment, the case in which the P +  region  3   c  is formed on the N +  region  2   b  is described. This vertical positional arrangement may be reversed; in other words, the technical idea of the present invention can be applied to the case in which an N +  region is formed on a P +  region. 
     In the second embodiment, the case in which the N +  region  2   b  and the P +  region  3   c  are formed in the Si pillar  6  is described. When these two regions have the same conductivity type, there is no need to form the N +  region  2  in  FIG. 2A . 
     In the first embodiment, the case in which the technical idea of the present invention is applied to the electrical connection between the N +  region  2   b  and the output wiring metal layer Vout and the P +  region  3   b  and the output wiring metal layer Vout and the electrical connection between the TiN layer  10   d  serving as a gate conductor layer and the input wiring metal layer Vin. Alternatively, the technical idea of the present invention can be applied to only one of these. The same applies to other embodiments of the present invention. 
     In the seventh embodiment, two N-channel SGTs are formed in the upper and lower portions of the Si pillar  6 , respectively. The technical idea of the present invention can also be applied to the case in which two P-channel SGTs are formed in the upper and lower portions of the Si pillar  6  respectively by using a P +  poly Si layer instead of the N +  poly Si layer  51 . 
     The P +  regions  26  and  33   b  and the N +  region  34   b  formed in the top portions of the Si pillars  6 ,  32   a , and  32   b  may be metal layers that form Schottky diodes with the i-regions  4   a ,  45   a , and  45   b . In this case, the NiSi layers  30   a ,  41   c , and  41   d  are not needed. 
     In the first to third embodiments, the cases in which the technical idea of the present invention is applied to CMOS inverter circuits are described. The technical idea of the present invention can also be applied to other semiconductor devices such as circuits, apparatuses, and elements. 
     As illustrated by each embodiment, an SGT has a structure in which a HfO 2  layer (gate insulating layer)  9   c  is formed at the outer periphery of a semiconductor pillar such as a Si pillar  6  and a TiN layer (gate conductor layer)  10   d  is formed at the outer periphery of the HfO 2  layer  9   c . A flash memory element which has a charge storing layer or a conductor layer electrically floating between the HfO 2  layer  9   c  and the TiN layer  10   d  is also a type of SGTs and thus the technical idea of the present invention can be applied to a method for manufacturing a flash memory element. For example, the technical idea of the present invention can be applied to a NAND flash memory element having plural gate conductor layers that are isolated from each other, the gate conductor layers being formed in one semiconductor pillar. 
     In the first embodiment, an N-channel SGT is formed in the lower portion of the Si pillar  6  and a P-channel SGT is formed in the upper portion of the Si pillar  6 . It is possible to apply the technical idea of the present invention to a circuit in which a P-channel SGT is formed in the lower portion and an N-channel SGT is formed in the upper portion. The technical idea of the present invention can also be applied to formation of a circuit in which both SGTs in upper and lower portions are N-channel or P-channel. This applies to other embodiments of the present invention also. 
     In the embodiments described above, examples in which only SGTs are formed in semiconductor pillars (Si pillar  6 ) are described but this is not limiting. The technical idea of the present invention can also be applied to a method for manufacturing a semiconductor device in which an SGT and other elements (for example, a photodiode) are mounted. 
     In the first embodiment, an example in which the TiN layers  10   b  and  10   d  serve as gate conductor layers is described but this is not limiting. The gate conductor layers may be composed of other metal materials. Alternatively, the gate conductor layer may have a multilayered structure constituted by a metal layer and a poly Si layer, for example. This structure can also be applied to other embodiments of the present invention. 
       FIG. 1E  of the first embodiment illustrates the case in which the SiN layer  12 , which has a low etching rate for HF ions, is formed below the resist layer  13  but this is not limiting. The SiN layer  12  may be composed of any other material with a low etching rate for HF ions. This applies to the SiN layer  20  also. This structure can also be applied to other embodiments of the present invention. 
     In the embodiments described above, a SOI substrate can be used instead of the i-layer substrate  1 . 
       FIGS. 2A to 2E  of the first embodiment illustrate the cases in which the i-layer substrate  1  and other layers are composed of Si but this is not limiting. The technical idea of the present invention is applicable to the cases in which other semiconductor material layers are used. This structure applies to other embodiments of the present invention also. 
     In the first embodiment, the N +  region  2   b  and the P +  region  3   b  are in contact with each other. However, the technical idea of the present invention can be applied to the case in which an insulating layer is formed between the N +  region  2   b  and the P +  region  3   b . This structure applies to other embodiments of the present invention also. 
     The resist layer  13  of the first embodiment need not be a resist material layer used in optical, X-ray, or electron beam lithography as long as it is a material layer from which a shape desired for the opening can be obtained. This also applies to other embodiments of the present invention. 
     The present invention allows various other embodiments and modifications without departing from the spirit and scope of the present invention in a broad sense. The embodiments described above merely illustrate examples of the present invention and do not limit the scope of the present invention. The embodiments and modifications can be freely combined. Some feature of the embodiment described above may be omitted as needed and such an embodiment is still within the technical scope of the present invention. 
     INDUSTRIAL APPLICABILITY 
     According to an SGT-including semiconductor device and a manufacturing method therefor according to the present invention, a highly integrated semiconductor device can be obtained. 
     The following is a summary list of reference numerals and the corresponding structure used in the above description of the invention: 
     
       
         
           
               
               
             
               
                   
               
             
            
               
                 1, 31 
                 i-layer substrate 
               
               
                 2, 2a, 7, 16, 16a, 34a, 34b, 52, 53 
                 N +  region 
               
               
                 3, 3a, 3b, 3c, 17, 26, 33a, 33b 
                 P +  region 
               
               
                 4, 4a, 1a, 45a, 45b 
                 i-region 
               
               
                 5, 5a, 8, 11, 11a, 11b, 11c, 11d, 14a, 
                 SiO 2  layer 
               
               
                 14b, 14c, 25, 38a, 38b, 42 
               
               
                 6, 32a, 32b 
                 Si pillar 
               
               
                 9, 9a, 9b, 9c, 36a, 36b 
                 HfO 2  layer 
               
               
                 10, 10a, 10b, 10c, 10d, 37a, 37b 
                 TiN layer 
               
               
                 12, 20, 39 
                 SiN layer 
               
               
                 13 
                 resist layer 
               
               
                 21a, 21b 
                 opening 
               
               
                 15, 40 
                 poly Si layer 
               
               
                 15a 
                 P +  poly Si layer 
               
               
                 51 
                 N +  poly Si layer 
               
               
                 18 
                 Ni layer 
               
               
                 19a, 19b, 19c, 23a, 23b, 23c, 30a, 30b, 
                 NiSi layer 
               
               
                 41a, 41b, 41c, 41d, 50a, 50b, 50c, 50d 
               
               
                 28a, 28b, 28c, 28d, 43a, 43b, 43c, 43d 
                 contact hole 
               
               
                 Vin 
                 input wiring metal layer 
               
               
                 Vdd 
                 power supply wiring metal layer 
               
               
                 Vout 
                 output wiring metal layer 
               
               
                 Vss 
                 ground wiring metal layer 
               
               
                 V1, V2 
                 wiring metal layer