Patent Publication Number: US-2023161366-A1

Title: Power supply with intergrated voltage regulator and current limiter and method

Description:
BACKGROUND 
     Field of the Invention 
     The present invention relates to power supply and, more particularly, to embodiments of a power supply with integrated voltage regulator and current limiter and an associated method. 
     Description of Related Art 
     A power supply is a device that supplies power to an electrical load. A voltage-regulated power supply automatically maintains an output voltage at a desired voltage level, as long as a maximum output current limit is not exceeded. A current limiter (also referred to herein as a current limiting circuit or over current protection circuit) can be employed to avoid exceeding the maximum output current limit. Typically, such a current limiter is configured to create a copy of the actual output current, to compare the copied current to a reference current, and to subsequently limit the output current based on the difference between the copied current and the reference current. Unfortunately, current limiters with this configuration are not ideal because, for example, they tend to exhibit higher quiescent currents and higher losses with increasing load currents, and they often require fast loop correction to create the copied current. 
     SUMMARY 
     Disclosed herein are embodiments of a power supply configured to automatically switch between operating in a voltage regulation mode and an over current protection mode, as needed. The power supply can include an input voltage node and an output voltage node. The pass transistor can have an input terminal connected to the input voltage node for receiving an input voltage; an output terminal connected to the output voltage node for outputting an output voltage; and a control terminal. The power supply can further include a voltage regulator, which is configured to generate and output a first control voltage for applying to the control terminal of the pass transistor during a voltage regulation mode in order to maintain the output voltage at the output voltage node at a desired voltage level. This first control voltage can be variable and specifically generated based on the output voltage at the output voltage node. The power supply can further include a current limiter, which is configured to generate and output a second control voltage for applying to the control terminal of the pass transistor during an over current protection mode to prevent an output current from rising above a maximum output current limit of the pass transistor. 
     The power supply can further include additional circuitry for detecting when over current protection is required (e.g., due to excess load) and for automatically switching operation between the voltage regulation mode and the over current protection mode (i.e., for automatically switching the control voltage applied to the control terminal from the first control voltage to the second control voltage or vice versa), as necessary. More specifically, the power supply can further include a comparator, which is configured to compare the first control voltage to the second control voltage and to output a select signal with a logic value that depends on the difference between the first control voltage and the second control voltage. The power supply can further include a switching circuit, which is configured to selectively and automatically apply either the first control voltage or the second control voltage to the control terminal of the pass transistor depending upon the logic value of the select signal. For example, the comparator can output a select signal with a first logic value indicating that over current protection is not required. In this case, the switching circuit can apply the first control voltage from the voltage regulator to the control terminal of the pass transistor, either maintaining the power supply in or switching the power supply to the voltage regulation mode. Alternatively, the comparator can output a select signal with a second logic value indicating that over current protection is required. In this case, the switching circuit can apply the second control voltage from the current limiter to the control terminal of the pass transistor, maintaining the power supply in or switching the power supply to the over current protection mode. 
     As discussed further in the detailed description section below, optionally, the current limiter can also be configured to automatically adjust the second control voltage so that it is at a first voltage level during the voltage regulation mode and so that it is at a slightly different second voltage level during the over current protection mode in order to prevent continuous oscillation between the two modes. 
     Also disclosed herein are embodiments of a power supply method. The method can include supplying, by a pass transistor of a power supply, power to an electrical load. supplying, by a pass transistor of a power supply, power to an electric load. The pass transistor can have an input terminal that is connected to an input voltage node; an output terminal connected to an output voltage node; and a control terminal. The method can further include generating and outputting, by a voltage regulator of the power supply, a first control voltage for applying to the control terminal of the pass transistor during a voltage regulation mode in order to maintain an output voltage at the output voltage node at a desired voltage level. This first control voltage can be variable and specifically generated based on the output voltage at the output voltage node. The method can further include generating and outputting, by a current limiter of the power supply, a second control voltage for applying to the control terminal of the pass transistor during an over current protection mode to prevent an output current from rising above a maximum output current limit of the pass transistor. 
     The method can further include detecting when over current protection is required (e.g., due to excess load) and automatically switching operation between the voltage regulation mode and the over current protection mode (i.e., for automatically switching the control voltage applied to the control terminal from the first control voltage to the second control voltage or vice versa), as necessary. More specifically, the method can include comparing, by a comparator of the power supply, the first control voltage to the second control voltage and outputting, by the comparator, a select signal with a logic value that depends on the difference between the first control voltage and the second control voltage. The method can further include selectively and automatically applying, by a switching circuit of the power supply, either the first control voltage or the second control voltage to the control terminal of the pass transistor depending upon the logic value of the select signal. For example, if the select signal has a first logic value indicating that over current protection is not required, then the method can include applying the first control voltage from the voltage regulator to the control terminal of the pass transistor, either maintaining the power supply in or switching the power supply to the voltage regulation mode. Alternatively, if the select signal has a second logic value indicating that over current protection is required, then the method can include applying the second control voltage from the current limiter to the control terminal of the pass transistor, maintaining the power supply in or switching the power supply to the over current protection mode. 
     As discussed further in the detailed description section below, optionally, the method can include automatically adjusting the second control voltage so that it is at a first voltage level during the voltage regulation mode and so that it is at a slightly different second voltage level during the over current protection mode in order to prevent continuous oscillation between the two modes. 
    
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
       The present invention will be better understood from the following detailed description with reference to the drawings, which are not necessarily drawn to scale and in which: 
         FIG.  1    is a schematic diagram illustrating generally embodiments of a power supply, as disclosed herein, with both an integrated voltage regulator and an integrated current limiter; 
         FIG.  2    is a schematic diagram illustrating, more specifically, an exemplary embodiment of the disclosed power supply; 
         FIG.  3    is a schematic diagram illustrating, more specifically, another exemplary embodiment of the disclosed power supply; 
         FIG.  4    is a schematic diagram illustrating an exemplary reference voltage generation circuit for generating the second reference voltage (Vref 2 ) for use in the disclosed power supply; 
         FIGS.  5  and  6    are schematic diagrams illustrating exemplary switches that can be incorporated into the disclosed power supply; and 
         FIG.  7    is a flow diagram illustrating disclosed power supply method embodiments. 
     
    
    
     DETAILED DESCRIPTION 
     As mentioned above, a power supply is a device that supplies power to an electrical load. A voltage-regulated power supply automatically maintains the output voltage at a desired voltage level, as long as a maximum output current limit is not exceeded. A current limiter (also referred to herein as a current limiting circuit or over current protection circuit) can be employed to avoid exceeding the maximum output current limit. Typically, such a current limiter is configured to create a copy of the actual output current, to compare the copied current to a reference current, and to subsequently limit the output current based on the difference between the copied current and the reference current. Unfortunately, current limiters with this configuration are not ideal because, for example, they tend to exhibit higher quiescent currents and higher losses with increasing load currents, and they often require fast loop correction to create the copied current. 
     In view of the foregoing, disclosed herein are embodiments of a power supply, which has both an integrated voltage regulator and an integrated current limiter and which is configured to automatically switch between operating in a voltage regulation mode and an over current protection mode, as needed. Specifically, the power supply includes a voltage regulator, which generates a first control voltage for applying to the control terminal of a pass transistor during a voltage regulation mode in order to maintain an output voltage at an output voltage node at a desired voltage level. The power supply also includes a current limiter, which generates a second control voltage for applying to the control terminal of the pass transistor during an over current protection mode to prevent the output current from rising above the maximum output current limit of the pass transistor. Finally, the power supply includes additional circuitry for detecting when over current protection is required (e.g., due to excess load) and for automatically switching between the voltage regulation mode and the over current protection mode (i.e., for automatically switching the control voltage applied to the control terminal from the first control voltage to the second control voltage or vice versa), as necessary. Also disclosed herein are associated power supply method embodiments. 
     As illustrated in  FIG.  1   , each of the power supply  100  embodiments disclosed herein can include an input voltage node  115 ; an output voltage node  116 ; and a pass transistor  110  connected between the input voltage node  115  and the output voltage node  116 . Specifically, pass transistor  110  can have an input terminal  111  connected to the input voltage node  115  for receiving a fixed input voltage (Vin); an output terminal  112  connected to the output voltage node  116  for outputting an output voltage (Vout); and a control terminal for receiving a control voltage that controls current flow through the pass transistor  110 . 
     The power supply  100  can further include a voltage regulator  120 , which generates and outputs (i.e., is configured to generate and output) a first control voltage (Vc 1 ) for applying to the control terminal  113  of the pass transistor  110  during a voltage regulation mode, thereby controlling the current flow through the pass transistor  110  so that Vout at the output voltage node  116  is maintained at a desired voltage level. Vc 1  can be generated by the voltage regulator  120  given the fixed Vin and based on the actual Vout at the output terminal  112 . Vc 1  can further be variable and continuously adjusted by the voltage regulator  120 , changing with any changes in the actual Vout (e.g., changing with temperature-dependent changes in Vout) so that the voltage level of Vout is continuously brought back to the desired voltage level. However, those skilled in the art will recognize that at output currents (Tout) (also referred to herein as load currents (Iload)) above a maximum output current limit (Iout-max) (also referred to herein as Iload-max) for the pass transistor  110 , the voltage regulator  120  may not be able to maintain the desired output voltage. That is, if Iout-max is exceeded, then the Vc 1  generated by the voltage regulator  120  may not be sufficient to maintain Vout at the desired voltage level. 
     Therefore, the power supply  100  can further include a current limiter  130 , which generates and outputs (i.e., is configured to generate and output) a second control voltage (Vc 2 ) for applying to the control terminal  113  of the pass transistor  110  during an over current protection mode in order to prevent the output current (Tout) from rising above Iout-max. Vc 2  can be generated and output by the current limiter  130  so that, for example, it is approximately equal to what Vc 1  would be if generated by the voltage regulator  120  when Tout is just at, but not exceeding, Iout-max. 
     The power supply  100  can also include additional circuitry for detecting when over current protection is required (e.g., due to excess load) and for automatically switching between the voltage regulation mode and the over current protection mode (i.e., for automatically switching the control voltage applied to the control terminal  113  of pass transistor  110  from Vc 1  to Vc 2  or vice versa), as necessary. Specifically, the power supply  100  can further include a comparator  141 , which compares (i.e., is configured or adapted to compare) Vc 1  to Vc 2  and generates and outputs (i.e., is configured to generate and output) a select signal (SEL) having a logic value that is based on the difference between Vc 1  and Vc 2 . The power supply  100  can further include a switching circuit  140 , which selectively and automatically applies (i.e., is configured to selectively and automatically apply) either Vc 1  or Vc 2  to the control terminal  113  of the pass transistor  110  depending upon the logic value of SEL. For example, the comparator  141  can generate and output SEL with a first logic value indicating that over current protection is not required. In this case, the switching circuit  140  can apply Vc 1  from the voltage regulator  120  to the control terminal  113  of the pass transistor  110 , either maintaining the power supply  100  in or switching the power supply  100  to the voltage regulation mode. Alternatively, the comparator  141  can generate and output SEL with a second logic value indicating that over current protection is required. In this case, the switching circuit  140  can apply Vc 2  from the current limiter  130  to the control terminal  113  of the pass transistor  110 , maintaining the power supply  100  in or switching the power supply  100  to the over current protection mode. 
       FIGS.  2  and  3    are schematic diagrams illustrating, in greater detail, two exemplary embodiments of such a power supply  100 A and  100 B, respectively. 
     Referring to  FIGS.  2  and  3   , the power supply  100 A,  100 B can include a pass transistor  110 , which supplies power to an electrical load  125  (e.g., a variable electrical load). That is, the power supply  100 A,  100 B can include an input voltage node  115 ; an output voltage node  116  connected to the electric load  125 ; and a pass transistor  110  connected between the input voltage node  115  and the output voltage node  116 . The pass transistor  110  can have an input terminal  111 , which receives a fixed input voltage (Vin). The pass transistor  110  can further have a control terminal  113 , which receives a control voltage (Vc) (see discussion below). The pass transistor  110  can further have an output terminal  112 , which outputs an output voltage (Vout) the voltage level of which is dependent upon both Vin and Vc. 
     The pass transistor  110  can be, for example, a p-type transistor. The p-type transistor can be a p-type field effect transistor (PFET), as illustrated. Such a power supply PFET can include a channel region between a source region (i.e., the input terminal) and a drain region (i.e., the output terminal) and a gate (i.e., the control terminal) adjacent to the channel region. Alternatively, the p-type transistor can be a pnp bipolar junction transistor (pnp-BJT). Such a power supply pnp-BJT can include a base region (i.e., the control terminal) between an emitter region (i.e., the input terminal) and a collector region (i.e., the output terminal). Alternatively, the pass transistor  110  can be any other suitable type of pass transistor. 
     The power supply  100 A,  100 B can further include a voltage regulator  120 . The voltage regulator  120  can be a low-dropout voltage regulator and, particularly, a DC linear voltage regulator that regulates (i.e., that is configured to regulate) Vout at the output voltage node  116  even when the fixed Vin at the input voltage node  115  is very close to Vout. More specifically, the voltage regulator  120  generates (i.e., is configured to generate) a first control voltage (Vc 1 ) for automatically maintaining Vout at a desired voltage level during a voltage regulation mode, as long Vin remains fixed and the maximum output current limit (Iout-max) of the pass transistor  110  is not exceeded. 
     In some embodiments, this voltage regulator  120  can include a pair of resistors  121  and  122  and an error amplifier  123  (also referred to herein as a differential amplifier). The pair of resistors  121 - 122  can be connected in series between the output voltage node  116  and ground (Vss)  199 . The error amplifier  123  can include an inverting input (−) that receives a first reference voltage (Vref 1 ). Vref 1  can be a constant reference voltage (i.e., a temperature-independent reference voltage set at a predetermined voltage level). Vref 1  can, for example, be generated by and received from a bandgap reference circuit. Such bandgap reference circuits are well known in the art and, thus, the details have been omitted from this specification in order to allow the reader to focus on the salient aspects of the disclosed embodiments. The error amplifier  123  can also include a non-inverting input (+) connected to a feedback voltage node  126  at an interface between the pair of series-connected resistors  121 - 122 . Thus, the non-inverting input (+) can monitor, at the feedback voltage node  126 , a fraction of Vout (referred to herein as the feedback voltage (Vfb)). Vfb can be determined by the resistor ratio of the two resistors  121 - 122  as follows: 
         V out= Vfb *(1 +R 1 /R 2),  (1)
 
     where R 1  is a first resistance of the first resistor  121  and R 2  is a second resistance of the second resistor  122 . The error amplifier  123  can further have an output and can be generate and output (i.e., can be configured to generate and output) Vc 1  at the output based on the difference between Vfb and Vref 1 . Specifically, the generated and output Vc 1  will be equal to the difference between Vref 1  and Vfb times any gain. Additionally, it should be noted that as Vfb rises above Vref 1 , Vc 1  will become increasingly more positive until a positive saturation voltage is reached, whereas as Vfb drops below Vref 1 , Vc 1  will become increasingly more negative until a negative saturation voltage is reached. As mentioned above and discussed in greater detail below, Vc 1  can be selectively applied to the control terminal  113  of the pass transistor  110  during a voltage regulation mode in order to maintain Vout at the output voltage node  116  at a desired voltage level. However, as discussed above, when Tout rises above Iout-max for the pass transistor  110 , the voltage regulator  120  may not be able to maintain Vout at the desired voltage level. That is, the Vc 1  generated by the voltage regulator  120  may not be sufficient to maintain Vout at the desired voltage level. 
     Therefore, the power supply  100 A,  100 B can further include a current limiter  130 , which generates and outputs (i.e., is configured to generate and output) a second control voltage (Vc 2 ) for applying to the control terminal  113  of the pass transistor  110  during an over current protection mode in order to prevent the output current (Tout) from rising above Iout-max. Vc 2  can be generated and output by the current limiter  130  so that, for example, it is approximately equal to what the Vc 1  would be if generated by the voltage regulator  120  when Tout is just at, but not exceeding, the Iout-max. 
     In some embodiments, the current limiter  130  can include at least a mimicking transistor  160  and a feedback amplifier  131 , and a reference current generation circuit (e.g.,  150 A or  150 B, as discussed in greater detail below). 
     The mimicking transistor  160  can be a p-type mimicking transistor and can specifically be an additional instance of the same transistor used for the pass transistor  110 . Alternatively, the mimicking transistor  160  could be a scaled down version of the pass transistor  110 . For example, for PFET pass and mimicking transistors, the PFET mimicking transistor can have a channel length (L) and a channel width (W), whereas the PFET pass transistor can have the same channel length (L), but a channel width of (K*W). Since, for purposes of illustration, the pass transistor  110  is shown as being a PFET, the mimicking transistor  160  is similarly shown as being a PFET. In any case, the mimicking transistor  160 , an output terminal  162  and a control terminal  163 . The input terminal  161  of the mimicking transistor  160  can be connected to the voltage input node  115  such that it too receives the input voltage (Vin). The output terminal  162  of the mimicking transistor  160  can be connected to a mimic output voltage node  134 . 
     The reference current (Tref) generation circuit can be connected between the mimic output voltage node  134  and ground. The Tref generation circuit can generate (i.e., can be configured to generate) a specific Tref across the mimic output voltage node  134  and, thereby setting the mimic output voltage (Vout-m) at the mimic output voltage node  134 . 
     The feedback amplifier  131  can include a non-inverting (+) input, which is connected to the mimic output voltage node  134 . The feedback amplifier  131  can also include an inverting (−) input that receives a second reference voltage (Vref 2 ). This Vref 2  can be received, for example, from a reference voltage generation circuit that is configured to generate Vref 2  based on Vref 1  and such that it is independent of Vout but mimics Vout of the pass transistor  110  at Iout-max.  FIG.  4    is a schematic diagram illustrating an exemplary reference voltage generation circuit that can be employed to generate Vref 2 , as described. Specifically, the reference voltage generation circuit can include an amplifier  401  with a pair of inputs and an output. A pair of reference resistors  411 - 412  can be connected in series between the output of the amplifier  401  and ground (Vss)  199  (e.g., a ground rail). The reference resistors  411 - 412  can be essentially the same as the resistors  121 - 122  used in voltage regulator  120  with the first reference resistor  411  having the same first resistance (R 1 ) as the first resistor  121  and with the second reference resistor  412  having the same second resistance (R 2 ) as the second resistor  122 . One input of the amplifier  401  can receive Vref 1  and the other input of the amplifier  401  can receive a reference feedback voltage (Vref-fb) from a reference feedback voltage node  415  at an interface between the two reference resistors  411 - 412 . It should be noted that Vref-fb can be essentially the same as Vfb on the feedback voltage node  126  of the voltage regulator  120 . Based on the difference between Vref 1  and Vref-fb and further on any gain, the amplifier  401  can output Vref 2 . Given equation (1) above, given that the reference resistors  411 - 412  are the same as the resistors  121 - 122 , given that Vref-fb is essentially the same as Vfb, and further given the following equations that define Vref 2 , it should be understood that the relationship of Vout to Vref 1  will be essentially the same as the relationship of Vref 2  to Vref 1  and, thus, Vref 2  will be essentially the same as but independent from Vout as long as the maximum output current limit (Iout-max) of the pass transistor  110  has not been exceeded. 
         V ref2 =V ref- fb *(1 +R 1 /R 2),  (2)
 
         V ref2 =V ref1*(1 +R 1 /R 2),  and (3)
 
         V ref2 =V out when  I out&lt; I out-max.  (4)
 
     Referring again to  FIGS.  2  and  3   , the feedback amplifier  131  of the current limiter  130  can further have an output and can generate and output (i.e., can be configured to generate and output) Vc 2  at the output based on the difference between Vref 2  and the mimic output voltage (Vout-m) at the mimic output voltage node  134 . With this configuration, Vc 2  can be set, for example, so that it is approximately equal to what the Vc 1  would be if generated by the voltage regulator  120  when Iout is just at, but not exceeding, Iout-max. This Vc 2  can be continuously applied to the control terminal  163  of the mimicking transistor  160  so that the current density through the mimicking transistor  160  is essentially the same as the current density through the pass transistor  110  at Iout-max. Additionally, during an over current protection mode, Vc 2  can be selectively applied to the control terminal  113  of the pass transistor  110  to prevent the output current at the output terminal  112  from rising above Iout-max. 
     The power supply  100 A,  100 B can also include additional circuitry for detecting when over current protection is required (e.g., due to excess load) and for automatically switching between the voltage regulation mode and the over current protection mode (i.e., for automatically switching the Vc applied to the control terminal  113  of pass transistor  110  from Vc 1  to Vc 2  or vice versa), as necessary. Specifically, the power supply  100 A,  100 B can further include a comparator  141 , which continuously compares (i.e., is configured to continuously compare) Vc 1  from the voltage regulator  120  to Vc 2  from the current limiter  130  and which outputs (i.e., is configured to output) a select signal (SEL) having a logic value that is based on the difference between Vc 1  and Vc 2 . 
     The power supply  100 A,  100 B can further include a switching circuit  140 , which selectively and automatically applies (i.e., is configured to selectively and automatically apply) either Vc 1  or Vc 2  to the control terminal  113  of the pass transistor  110  depending upon the logic value of SEL. In some embodiments, the switching circuit  140  can include a pair of series-connected inverters (i.e., a first inverter  143  and a second inverter  145  connect in series). The first inverter  143  can receive, as an input, SEL from the comparator  141 . The switching circuit can further include a pair of switches (i.e., a first switch  147  and a second switch  148 ). The second switch  148  can receive and be controlled by an inverted select signal (SELb) output from the first inverter  143  and, depending upon the logic value of SELb, can connect the output of the feedback amplifier  131  of the current limiter  130  to a control node  149  and thereby to the control terminal  113  of the pass transistor  110  (i.e., can cause Vc 2  to be applied to the control terminal  113 ) or, alternatively, can disconnect the output of the feedback amplifier  131  from the control node  149 . The first switch  147  can receive and be controlled by a twice-inverted select signal (SEL 2 ) from the second inverter  145  and, based on SEL 2 , can connect the output of the error amplifier  123  of the voltage regulator  120  to the control node  149  and thereby to the control terminal  113  of the pass transistor  110  (i.e., can cause Vc 1  to be applied to the control terminal  113 ) or, alternatively, can disconnect the output of the error amplifier  123  from the control node  149 . With this configuration, either Vc 1  or Vc 2  is applied to the control terminal  113  of the pass transistor  110  at any given time but not both. 
       FIGS.  5  and  6    are schematic diagrams illustrating an exemplary first switch  147  and an exemplary second switch  148 , respectively, that can be incorporated into the switching circuit  140  for selectively and alternatively applying either Vc 1  or Vc 2  to the control terminal  113  of the pass transistor  110 . Each of these switches  147  and  148  can include a p-type field effect transistor and an n-type field effect transistor connected in parallel between an input node (which receives a control voltage, for example, Vc 1  in the case of the first switch  147  and Vc 2  in the case of the second switch  148 ) and the control node  149 . Each of these switches  147  and  148  can further include an additional inverter with an output connected to the gate of the p-type field effect transistor. In the first switch  147 , the twice-inverted select signal (SEL 2 ) is applied to the gate of the n-type field effect transistor and also to the input of the additional inverter such that a thrice-inverted select signal is applied to the gate of the p-type field effect transistor. In the second switch  148 , the inverted select signal (SELb) is applied to the gate of the n-type field effect transistor and also to the input of the additional inverter such that another twice-inverted select signal is applied to the gate of the p-type field effect transistor. 
     With this configuration, if the logic value of SEL from the comparator  141  is a 1 (i.e., indicating that Vc 1  is greater than Vc 2  and over current protection is not needed), then both the p-type field effect transistor and the n-type field effect transistor of the first switch  147  will be turned on and Vc 1  will be applied to the control terminal  113  of the pass transistor  110 , whereas both the p-type field effect transistor and the n-type field effect transistor of the second switch  148  will be turned off and Vc 2  will not be applied to the control terminal  113  of the pass transistor  110 . As a result, the power supply  100 A,  100 B either continues to operate in the voltage regulation mode (if already operating in the voltage regulation mode) or switches back to operating in the voltage regulation mode. However, if the logic value of the SEL from the comparator  141  is a 0 (i.e., indicating that Vc 1  is less than Vc 2  and over current protection is needed), both the p-type field effect transistor and the n-type field effect transistor of the first switch  147  will be turned off and Vc 1  will not be applied to the control terminal  113  of the pass transistor  110 , whereas both the p-type field effect transistor and the n-type field effect transistor of the second switch  148  will be turned on and Vc 2  will be applied to the control terminal  113  of the pass transistor  110 . Thus, the power supply  100 A,  100 B either switches to operating in the current protection mode or continues operating in the over current protection mode (if already operating in the over current protection mode). 
     As mentioned above, the Iref generation circuit can optionally be a variable Tref generation circuit (e.g., see the variable Tref generation circuit  150 A of the current limiter  130  in the power supply  100 A of  FIG.  2   , see also the variable Tref generation circuit  150 B of the current limiter  130  in the power supply  100 B of  FIG.  3   ). Such a variable Tref generation circuit  150 A,  150 B automatically adjust (i.e., can be configured to automatically adjust) Tref across the mimic output voltage node  134  so that, during operation in a voltage regulation mode, Tref is at a first current level (Iref-vrm) causing Vc 2  to be at a first voltage level (Vc 2 -vrm) and so that, during operation in an over current protection mode, the Tref is at a second current level (Iref-ocpm) causing Vc 2  to be at a second voltage level (Vc 2 -ocpm) that is different from the first voltage level. Specifically, the Tref generation circuit automatically adjust (i.e., can be configured to automatically adjust) Iref so that when the power supply  100 A,  100 B is operating in the voltage regulation mode Vc 2  is set at a first voltage level (Vc 2 -vrm) that is approximately equal to what the Vc 1  would be if generated by the voltage regulator  120  when Tout is just at, but not exceeding, the Iout-max. Thus, in the voltage regulation mode Vc 1  will be greater than Vc 2 . However, as mentioned above, Vc 1  is variable, and it will decrease as Tout increases until the load reaches Iout_max. As soon as Vc 1  drops below Vc 2 , the comparator  141  will cause SEL to switch from a logic value of 1 to a logic value of 0, thereby switching operation of the power supply  100 A,  100 B to the over current protection mode. During the over current protection mode, Vc 2  will be applied to the control terminal  113  of the pass transistor as long as Vc 1  is below Vc 2 . However, if Vc 2  is kept at the same voltage level during both the voltage regulation mode and the over current protection mode, the power supply  100 A,  100 B could automatically switch back to the voltage regulation mode as soon as Vc 2  is applied to the control terminal  113  of the pass transistor  110 , automatically switch back to the over current protection mode as soon as Vc 1  is applied to the control terminal  113 , and so on. To prevent this continuous oscillation between the two modes, the variable Tref generation circuit  150 A,  150 B can be used to automatically adjust the current level of Tref so that it is less in the over current protection mode (i.e., so that, during operation in the voltage regulation mode, Iref is at a first current level (Tref-vrm) and so that, during operation in the over current protection mode, Tref is at a second current level (Iref-ocpm) that is less than the first current level). Thus, during operation in the voltage regulation mode, Vc 2  will be at a first voltage level (Vc 2 -vrm) and, during operation in the overcurrent protection mode, Vc 2  will be at a second voltage level (Vc 2 -ocpm) that is higher than the first voltage level. As a result, before the power supply  100 A,  100 B can switch from the over current protection mode back to the voltage regulation mode, Vc 1  will have to be pulled up higher than it otherwise would. That is, Vc 1  only has to drop below Vc 2 -vrm to cause the switch to operation in the over current protection mode, but it will have to rise to at least Vc 2 -ocpm (i.e., Vc 1 ≥Vc 2 -ocpm) to trigger a switch back to operation in the voltage regulation mode. 
     For example, as illustrated in  FIG.  2   , in some embodiments the variable Tref generation circuit  150 A can include a resistor  152  (e.g., a variable resistor) connected to the mimic output voltage node  134 . The variable Tref generation circuit  150 A can further include an additional resistor  153  (also referred to herein as a hysteresis resistor) connected in series between the resistor  152  and ground (Vss)  199 . The variable Tref generation circuit  150 A can further including an NFET  151 , which is connected in parallel with the additional resistor  153  and further connected in series between the resistor  152  and ground (Vss)  199 . The NFET  151  can have a gate connected to the output of the comparator  141  such that it is controlled by SEL. In this case, when SEL has a logic value of 1 (i.e., indicating that over current protection is not needed), then the NFET  151  will be in an on-state and current will flow through the resistor  152  and the NFET  151  to ground (e.g., effectively bypassing the additional resistor  153 ) such that, during operation in the voltage regulation mode, Tref is at the first current level (Iref-vrm) and Vc 2  is at the first voltage level (Vc 2 -vrm). However, when SEL has a logic value of 0 (i.e., indicating that over current protection is needed), then the NFET  151  will be switched to an off-state preventing current flow through the NFET  151 . Thus, during the operation in the over current protection mode, current will have to flow through both the resistor  152  and the additional resistor  153  to ground and Tref will drop to the second current level (Iref-ocpm), thereby causing Vc 2  to rise to the second voltage level (Vc 2 -ocpm). It should be noted that for the variable Tref generation circuit  150 A, the following equations apply. 
         I ref- vrm=V out- m/R ref, and  (5)
 
         I ref- ocpm=V out- m /( R ref+ R hyst),  (6)
 
     where Vout-m is the is the mimic output voltage on the mimic output voltage node  134 , Rref is the resistance of the resistor  152 , and Rhyst is the resistance of the additional resistor  153 . 
     In other embodiments, as illustrated in  FIG.  3   , the variable Tref generation circuit  150 B can include a current source  155  (e.g., a variable current source) connected between the mimic output voltage node  134  and ground (Vss)  199 . The variable Tref generation circuit  150 B can further include an additional current source  154  (also referred to herein as a hysteresis current source) that is also connected to the mimic output voltage node  134  and that is smaller than the current source  155 . The variable Tref generation circuit  150 B can further include an n-type field effect transistor (NFET)  151  (also referred to herein as a hysteresis on/off switch) connected in series between the additional current source  154  and ground (Vss)  199 . The NFET  151  can have a gate connected to the output of the comparator  141  such that it is controlled by SEL. In this case, when SEL has a logic value of 1 (i.e., indicating that over current protection is not needed), then the NFET  151  will be in an on-state and current will flow through the additional current source  154  and the NFET  151  to ground such that Iref in the voltage regulation mode (Iref-vrm) is at the first current level and Vc 2  is at the first voltage level (Vc 2 -vrm). However, when SEL has a logic value of 0 (i.e., indicating that over current protection is needed), then the NFET  151  will be switched to an off-state preventing current flow from the additional current source  154  through the NFET  151 . Thus, current will flow only through the current source  155  to ground and Iref in the overcurrent protection mode (Iref-ocpm) will drop to the second current level, thereby causing Vc 2  to rise to the second voltage level (Vc 2 -ocpm). It should be noted that for the variable Iref generation circuit  150 B, the following equations apply. 
         I ref- vrm=I var+ I hyst,  and (7)
 
         I ref- ocpm=I var,  (8)
 
     where Ivar is current through the current source  155  and Ihyst is the current through the additional current source  154 . 
     It should be noted that the variable Iref generation circuit  150 A,  150 B can be configured so that the difference between the first voltage level of Vc 2  during the voltage regulation mode (i.e., Vc 2 -vrm) and the second voltage level of Vc 2  during the over current protection mode (i.e., Vc 2 -ocpm) is relatively small. For example, Vc 2 -vrm can be on the order of a few millivolts (mV) or even less than 1 mV less than Vc 2 -ocpm. It should further be noted that this relatively small increase in Vc 2  that occurs upon entry into the over current protection mode will result in a corresponding relatively small drop in Iout. 
     Referring again to  FIGS.  2  and  3   , optionally, the switching circuit  140  can further include at least one status monitor (e.g., at least one buffer). Each status monitor can monitor (i.e., can be configured to monitor) the on/off state of a corresponding one of the switches  147  and  148  and can output (i.e., can be configured to output) a status signal indicating the state of the switch and, thereby the mode of operation of the power supply  100 A,  100 B. For purposes of illustration, a single status monitor  170  is shown as being connected to the output of the first inverter  143 . This status monitor  170  can, for example, receive (i.e., can be configured to receive) SELB from the first inverter  143  and can output (i.e., can be configured to output) a mode status signal (MS) with a logic value that indicates whether or not the second switch  148  is on or off and, thereby whether or not the power supply  100 A,  100 B is operating in the over current protection mode. It should be understood that, additionally or alternatively, such a status monitor could be connected to the output of the second inverter  145  and can receive (i.e., can be configured to receive) SEL 2  from the second inverter  145  and can output (i.e., can be configured to output) a mode status signal with a logic value that indicates whether or not the first switch  147  is on or off and, thereby whether or not the power supply  100 A,  100 B is operating in the voltage regulation mode. As discussed above, the power supply  100 A,  100 B can only operate in one of these two modes at any given time. 
     Referring to the flow diagram of  FIG.  7   , also disclosed herein are embodiments of a power supply method associated with the power supply structures described in detail above and illustrated generally in  FIG.  1    and more specifically in  FIGS.  2  and  3   . The method can include supplying, by a pass transistor  110  of a power supply  100 , power to an electrical load  125  (e.g., a variable electrical load) (see process step  702 ). As discussed above, the pass transistor  110  can have an input terminal  111  that is connected to an input voltage node  115  that receives an input voltage (Vin); an output terminal  112  connected to an output voltage node  116  that outputs an output voltage (Vout); and a control terminal  113 . 
     The method can further include generating and outputting, by a voltage regulator  120  of the power supply  100 , a first control voltage (Vc 1 ) for applying to the control terminal  113  of the pass transistor  110  during a voltage regulation mode in order to maintain an output voltage (Vout) Vout at the output voltage node  116  at a desired voltage level (see process step  704 ). Vc 1  can be variable and specifically generated given Vin and based on Vout. 
     The method can further include generating and outputting, by a current limiter  130  of the power supply  100 , a second control voltage (Vc 2 ) for applying to the control terminal  113  of the pass transistor  110  during an over current protection mode to prevent an output current (Iout) from rising above a maximum output current limit (Iout-max) of the pass transistor  110  (see process step  706 ). 
     The method can further include detecting when over current protection is required (e.g., due to excess load) and automatically switching operation between the voltage regulation mode and the over current protection mode (i.e., for automatically switching the control voltage applied to the control terminal from the first control voltage to the second control voltage or vice versa), as necessary (see process steps  708 - 712 ). 
     More specifically, the method can include comparing, by a comparator  141  of the power supply  100 , Vc 1  to Vc 2  and outputting, by the comparator  141 , a select signal (SEL) with a logic value that depends on the difference between Vc 1  and Vc 2  (see process step  708 ). The method can include further include, depending upon the logic value of SEL, selectively and automatically applying, by a switching circuit  140  of the power supply  100 , either Vc 1  to the control terminal  113  of the pass transistor  110  to initiate or maintain operation in the voltage regulation mode (see process step  710 ) or Vc 2  to the control terminal  113  of the pass transistor  110  to initiate or maintain operation in the overcurrent protection mode (see process step  712 ). For example, if the SEL has a first logic value (e.g., a logic value of 1) indicating that over current protection is not required, then the method can include applying Vc 1  from the voltage regulator  120  to the control terminal  113  of the pass transistor  110 , either maintaining the power supply  100  in or switching the power supply  100  to the voltage regulation mode. Alternatively, if SEL has a second logic value (e.g., a logic value of 0) indicating that over current protection is required, then the method can include applying Vc 2  from the current limiter  130  to the control terminal  113  of the pass transistor  110 , maintaining the power supply  100  in or switching the power supply  100  to the over current protection mode. 
     Optionally, the method can include automatically adjusting Vc 2  so that it is at a first voltage level during the voltage regulation mode and so that it is at a slightly different second voltage level during the over current protection mode in order to prevent continuous oscillation between the two modes. More specifically, as discussed above, Vc 2  is generated and output at process step  706 . However, if it is determined at process step  708  that Vc 1  has dropped below Vc 2 , then the over current protection mode will be initiated at process step  712  and Vc 2  will be applied to the control terminal  113  of the pass transistor. Vc 1  will be repeatedly compared to Vc 2  and Vc 2  will continue to be applied to the control terminal of the pass transistor as long as Vc 1  remains below Vc 2 . However, if Vc 1  and Vc 2  are approximately the same, the power supply could automatically switch back to the voltage regulation mode as soon as Vc 2  is applied to the control terminal  113  of the pass transistor  110 , automatically switch back to the over current protection mode as soon as Vc 1  is applied to the control terminal  113 , and so on. To prevent this continuous oscillation between the two modes (i.e., between process steps  710  and  712 ), the current level of Tref can be automatically decreased slightly from a first current level (Iref-vrm) to a second current level (Iref-ocpm) upon switching from the voltage regulation mode to the over current protection mode so that the voltage level of Vc 2  is automatically increased slightly from a first voltage level (Vc 2 -vrm) to a second voltage level (Vc 2 -ocpm) (see process step  714 ). As a result, before switching from operation in the over current protection mode back to operation in the voltage regulation mode, for hysteresis Vc 1  will have to be pulled up higher than it otherwise would. That is, Vc 1  only has to drop below Vc 2 -vrm to cause the switch to operation in the over current protection mode, but it will have to rise to at least equal to Vc 2 -ocpm (i.e., Vc 1 ≥Vc 2 -ocpm) to trigger the switch back to operation in the voltage regulation mode. Furthermore, the current level of Tref can be automatically increased slightly from Iref-ocpm back up to Iref-vrm upon switching from operation in the over current protection mode back to operation in the voltage regulation mode so that the voltage level of Vc 2  is automatically decreased slightly from Vc 2 -ocpm back down to Vc 2 -vrm (see process step  716 ). See the detailed discussion above regarding operation of the variable Tref generation circuit  150 A of the current limiter  130  of the power supply  100 A of  FIG.  2    or the variable Tref generation circuit  150 A of the current limiter  130  of the power supply  100 B of  FIG.  3   . 
     It should be understood that the terminology used herein is for the purpose of describing the disclosed structures and methods and is not intended to be limiting. For example, as used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. Additionally, as used herein, the terms “comprises” “comprising”, “includes” and/or “including” specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Furthermore, as used herein, terms such as “right”, “left”, “vertical”, “horizontal”, “top”, “bottom”, “upper”, “lower”, “under”, “below”, “underlying”, “over”, “overlying”, “parallel”, “perpendicular”, etc., are intended to describe relative locations as they are oriented and illustrated in the drawings (unless otherwise indicated) and terms such as “touching”, “in direct contact”, “abutting”, “directly adjacent to”, “immediately adjacent to”, etc., are intended to indicate that at least one element physically contacts another element (without other elements separating the described elements). The term “laterally” is used herein to describe the relative locations of elements and, more particularly, to indicate that an element is positioned to the side of another element as opposed to above or below the other element, as those elements are oriented and illustrated in the drawings. For example, an element that is positioned laterally adjacent to another element will be beside the other element, an element that is positioned laterally immediately adjacent to another element will be directly beside the other element, and an element that laterally surrounds another element will be adjacent to and border the outer sidewalls of the other element. The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. 
     The descriptions of the various embodiments of the present invention have been presented for purposes of illustration but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein. 
     Therefore, disclosed above are embodiments of a power supply, which has both an integrated voltage regulator and an integrated current limiter and which is configured to automatically switch between operating in a voltage regulation mode and an over current protection mode, as needed. These embodiments do not require the generation of a copy of Tout for over current protection, instead they employ a reference voltage and a mimicking transistor with the same current density as the pass transistor to generate to a mode-specific control voltage for applying to the control terminal of the pass transistor. As a result, matching is relatively easy, the quiescent current is constant across all electrical loads, there is low loss, and there is no need for fast loop correction. Furthermore, the configuration of the disclosed power supply offers a fast recovery from the over current protection mode back to the voltage regulation mode because start-up of the voltage regulator is not required. Instead, the voltage regulator continuously generates Vc 1 , and the current limiter continuously generates Vc 2  and switching between the two modes (i.e., switching between application of Vc 1  to the control terminal of the pass transistor and application of Vc 2  to the control terminal of the pass transistor) is dynamic, simply dependent upon on the relationship between Vc 1  and Vc 2 .