Patent Publication Number: US-8116321-B2

Title: System and method for routing asynchronous signals

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application claims the benefit, under 35 U.S.C. §365 of International Application PCT/US05/19115 filed Jun. 1, 2005, which was published in accordance with PCT Article 21(2) on Jan. 26, 2006 in English and which claims the benefit of U.S. provisional patent application Nos. 60/580,188, 60/580,189, filed Jun. 16, 2004. 
    
    
     FIELD OF THE INVENTION 
     This invention relates to routers and more specifically to broadcast routers that route asynchronous signals. 
     BACKGROUND OF THE INVENTION 
     A router comprises a device that routes one or more signals appearing at the router input(s) to one or more outputs. Routers used in the broadcast industry typically employ at least a first router portion with a plurality of router modules (also referred to as matrix cards) coupled to at least one expansion module. The expansion module couples the first router chassis to one or more second router portion to allow further routing of signals. Many broadcast routers, and especially those that are linearly expandable, route asynchronous signals. Asynchronous signal routing by such linearly expandable routers requires an accurate clock signal throughout the entire route to preserve the integrity of routed data. For an asynchronous signal, a difference in clock frequency from one location to another can cause corruption of the signal and loss of the data represented by that signal. Even a difference in clock frequencies as small as 1 part per million (PPM) can have an undesirable effect on data. Typical examples of data corruption include repeated or dropped signal samples. 
     As linearly expandable routers increase in complexity, the problem of supplying an accurate and synchronized clock signal to various elements becomes more difficult. For purposes of discussion, a clock signal constitutes a signal that oscillates between a high and a low state at defined intervals. Typical clock signals oscillate with a 50% duty cycle. However, clocks having other duty cycles are also commonly employed. Circuits using clock signals for synchronization become active upon one of the rising or falling edge of the clock signal. 
     A so-called, “clock multiplexer” refers to a circuit, as typically exists within a linearly expandable router, for selecting at least one clock signal from a plurality of available clock signals. The selected clock signal(s) serve to trigger other elements. When selecting among available clock signals, the output signal selected by the clock multiplexer should not include any undefined pluses. Undefined pulses occur, for example, when a selected clock signal undergoes a disruption. Such a disruption can include a missing clock signal as well as a clock signal that fails to switch states as expected. Some times, an input clock signal will remain “stuck” indefinitely at one logic state or the other. Such disruptions frequently produce undefined pulses including runt pulses, short pulses, pulses of indefinite duration, glitches, spikes and the like. 
     Prior art attempts to avoid undefined pulses at the output of a clock multiplexer include so-called “safe” clock multiplexers. A typical safe clock multiplexer switches from a presently selected input to a next selected input in an orderly manner. Thus, a safe multiplexer does not switch until the selected input clock signal transitions to a known state and the subsequently selected clock signal transitions to the same state as the previously selected clock signal. 
     However, prior art safe clock multiplexers have drawbacks. For example, when a presently selected clock signal fails to transition to a known state, a safe clock multiplexer will often lack the ability to switch to another clock signal. Prior art safe clock multiplexers have not tolerated these and other types of clock disruptions. 
     Thus, a need exists for a technique for providing a selected one of a set of clock signals, such as within a linearly expandable router, that overcomes the aforementioned disadvantages 
     SUMMARY OF THE INVENTION 
     Briefly in accordance with a preferred embodiment of the present principles, there is provided a method for selecting a clock signal from among at least first and second clock signals. The method commences by detecting a failure of a first clock signal to change state and by detecting a failure of a second clock signal to change state. A selection occurs from among the first and second clock signals and an oscillator signal, based in part on whether at least one of the first and second clock signals has toggled 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  illustrates a block schematic diagram of a router according to an illustrative embodiment of the present principles: 
         FIG. 2  illustrates a first alternate arrangement of input and output modules for the router of  FIG. 1   
         FIG. 3  illustrates a second alternate arrangement of input and output modules for the router of  FIG. 1 ; 
         FIG. 4  illustrates a third alternate arrangement of input and output modules for the router of  FIG. 1   
         FIG. 5  illustrates a first network of clock selector circuits for use in the router of  FIG. 1 ; 
         FIG. 6  depicts a second network of clock selector circuits for use in the router of  FIG. 1   
         FIG. 7  depicts a block schematic diagram of an illustrative embodiment of a clock selector circuit within the networks of  FIGS. 5 and 6 ; and 
         FIG. 8  depicts a safe clock multiplexer system of for use in the selector circuit of  FIG. 4 . 
     
    
    
     DETAILED DESCRIPTION 
       FIG. 1  depicts a block schematic of a broadcast router  100  in accordance with a preferred embodiment of the present principles. In a preferred embodiment, the router  100  comprises at least one, and preferably a plurality input modules  402   1 ,  402   2  . . .  402   x  where x is an integer greater than zero, and at least one, and preferably, a plurality of output modules  404   1  . . .  404   y , where y is an integer. Each input module, such as input module  402   1 , comprises at least one, and preferably a plurality of input cards  406   1 ,  406   2  . . .  406   z  where z is an integer greater than zero. Each input card has at least one, and preferably, a plurality of inputs for receiving signals for multiplexing into an output signal. Different input cards typically have different signal receiving capabilities to afford the ability to receive signals from a variety of sources. An expansion card  408  within each input module, such as module  402   1 , multiplexes the output signals from the input cards  406   1 - 406   z  into an output signal. 
     Each second module, such as second module  404   1 , has a matrix  410  card which de-multiplexes the input signals from one or more of the input modules for delivery to at least one, and preferably a plurality of output cards  412   1 ,  412   2  . . .  412   p , where p is an integer greater than zero. Each output card delivers one or more output signals to one or more external devices (not shown). A control card  414  controls the matrix card  410  in response to an external control signal C to cause the matrix card to route its output signal among various of the output cards  412   1 - 412   p . In this way, the matrix card  410  can effectuate routing based on the external control signal C. 
     The router  100  of  FIG. 1  has each of its input modules  402   1 ,  402   2  . . .  402   x  coupled to each of the output modules  404   1 ,  402   2  . . .  404   y . Other arrangements are possible.  FIG. 2  illustrates a first alternate arrangement of input and output cards for the router  100  of  FIG. 1  wherein the input and output modules are arranged to provide the same number of inputs and outputs.  FIG. 3  illustrates a second alternate arrangement of input and output modules for the router  100  of  FIG. 1  in which there are more inputs than outputs.  FIG. 4  illustrates a third alternate arrangement of input and output modules for the router  100  of  FIG. 1  in which there are more outputs than inputs. 
     The input modules  402   1 - 402   x  and the output modules  404   1 - 404   y  of  FIG. 1  typically each include at least one of clock modules  500   1 - 500   n  where n≧x+y, with each clock module having a structure as described in greater detail with respect to  FIG. 5 . In practice, separate clock modules can exist in within one or more the elements within each input and output module of  FIG. 1 . Moreover, one or more clock module  500   1 - 500   n  could exist as separate modular elements in the router  100 , much like one of the input or output modules. 
     Referring to  FIG. 5 , the clock modules  500   1 - 500   n  can interconnect with each other in a daisy chain fashion to yield a network  600  of clock modules. In the embodiment of  FIG. 5 , the clock module  500   1  supplies its clock signal to the clock module  500   2  as well as each of clock modules  500   3 ,  500   i+1  and  500   i+3 , where i≦n, whereas the clock module  500   2  supplies its clock signal to each of modules  500   i ,  500   i+2  and  500   j+4 . Each of the clock modules  500   1 ,  500   2  . . .  500   n  also receives the clock signal from a preceding one of clock modules  500   2  . . .  500   i  . . .  500   n-1 , respectively. 
       FIG. 6  depicts an alternate arrangement of clock modules wherein the modules are arranged in first and second networks  600   1  and  600   2 , with each of the networks  600   1  and  600   2  configured similarly to the clock module network  600  of  FIG. 2 . As seen in  FIG. 6 , one or more of the individual clock modules  500   1 - 500   n  of network  600   1  provide clock signals to one or more of the clock modules  500   1 - 500   n  of network  600   2 . 
       FIG. 7  depicts a block schematic diagram of an exemplary clock module  500   i . The clock module  500   i  of  FIG. 4  includes first and second clock inputs that receive first and second clock signals Clock_ 1  and Clock_ 2 , respectively. Each of the external clock signals Clock_ 1  and Clock_ 2  can comprise clock signals from a separate upstream clock selector circuit in the network of  FIG. 2  or a clock signal from a reference clock circuit formed by an oscillator  508 . 
     The clock selector circuit  500   i  includes a pair of toggle detectors  502  and  504  which each receive a separate one of the Clock_ 1  and Clock_ 2  signals. Each toggle detector provides an output signal indicative of whether its respective input clock signal has toggled, i.e., a changed from one state to another. A logic block  506  receives the output signals of the toggle detectors  502  and  504 , along with the output of an oscillator circuit  508  that generates a clock signal useful for meeting the timing requirements of various circuit elements. The logic block  506  also receives two external status signals; (1) A_not B and (2) Master_not Slave. The state of the status signal A_not B indicates whether or not the clock circuit  500   i  will provide the primary clock signal. The state of the Master_not Slave signal determines the clock circuit  500   i  operates as its own master, or as a slave to another clock signal. 
     The logic block  506  generates an output control for controlling a safe clock multiplexer system  510  to select among the clock signals Clock_ 1 , Clock_ 2  and the output signal of the oscillator  508 , to provide a single clock signal to downstream elements (not shown). The output control signal of the logic block  506  has a prescribed relationship to the logic circuit input signals as shown in Table 1, with the “x” entries constituting “don&#39;t care” values. (In other words, the value of the particular input signal has no effect on the output of the logic block  506 .) 
     
       
         
           
               
               
               
               
               
             
               
                 TABLE I 
               
               
                   
               
               
                   
                   
                 Toggle 
                 Toggle 
                 Safe clock 
               
               
                   
                 Master_Not 
                 Detector 
                 Detector 
                 multiplexer 
               
               
                 A_not B 
                 Slave 
                 504 
                 502 
                 system 510 Output 
               
               
                   
               
             
            
               
                 1 
                 1 
                 x 
                 x 
                 Oscillator 508 
               
               
                 0 
                 1 
                 x 
                 1 
                 Clock_2 
               
               
                 0 
                 1 
                 x 
                 0 
                 Oscillator 508 
               
               
                 x 
                 0 
                 1 
                 x 
                 Clock_1 
               
               
                 x 
                 0 
                 0 
                 1 
                 Clock_2 
               
               
                 x 
                 0 
                 0 
                 0 
                 Oscillator 508 
               
               
                   
               
            
           
         
       
     
     As seen from Table 1, for so long as the Master_Not Slave signal remains at a logic “1” level, the clock circuit  500   i  only selects between Clock_ 2  and Oscillator  508 . Under such conditions, the toggling of the Clock_ 1  signal, and hence the output signal of the toggle detector  504  has no effect. Conversely, when the clock circuit  500   i  serves as a slave (i.e., the Master_Not Slave signal remains at a logic “0” level), the output states of the toggle detector  504 , and the output state of the toggle detector  502 , determine which of the Clock_ 1 , Clock_ 2 , and oscillator  508  signals appear at the output of the safe clock multiplexer system  510 . The clock signal selected by the safe clock multiplexer system  510  provides a timing signal for local use as well as for input to elements within the router  100  of  FIG. 1 . 
     In a preferred embodiment, the safe clock multiplexer system  510  of  FIG. 4  has the structure shown in  FIG. 5  to afford the clock module  500   i  of  FIG. 3  the ability to tolerate an input clock pulse that has become stuck. Within the safe clock multiplexer system  510  of  FIG. 5 , first and second toggle detectors  701   1  and  701   2  receive the Clock_ 1  and Clock_ 2  signals, respectively, as do each of a pair of multiplexers  702   1  and  702   2 , respectively. Each of the multiplexers  702   1  and  702   2  receives a signal and a logic “0” level at its second input. 
     The toggle detectors  701   1  and  701   2  control the multiplexers  702   1  and  702   1  in accordance with the state of Clock_ 1  and Clock_ 2  signals, respectively, as measured against the output signal of the oscillator  508 . In other words, each of the toggle detectors  701   1  and  701   2  determines whether a respective one of the Clock_ 1  and Clock_ 2  signals has changed state (i.e., toggled) relative to the output signal of the oscillator  508 . If a respective one of the toggle detectors  701   1  and  701   2  determines that a corresponding one of the Clock_ 1  and Clock_ 2  signals has toggled relative to the oscillator  508  output signal, then that toggle detector gates a corresponding one of the multiplexers  702   1  and  702   2 . When gated, each of the multiplexers  702   1  and  702   2  passes and associated one of the Clock_ 1  and Clock  2  signals. Should a respective one of the clock signals Clock_ 1  and Clock_ 2  not toggle relative to the oscillator  508  output signal, then the corresponding one of the multiplexers  702   1  and  702   2  will output a logic zero level signal. 
     A multiplexer  704  receives at its first and second inputs the output signals of the multiplexers  702   1  and  702   2 , respectively. In accordance with a signal from the logic block  506  of  FIG. 4 , the multiplexer passes the output signal of one of the multiplexers  702   1  and  702   2  to a first input of a multiplexer  706   1  and to the input of a toggle detector  708   1 . The multiplexer  706   1  has its second input supplied with a signal at a logic zero level. 
     The toggle detector  708   1  controls the multiplexer  706   1  in accordance with the relationship between the output signal of the multiplexer  704  and the output signal of the oscillator  508 . In other words, the toggle detector  708   1  determines whether the output signal of the multiplexer  704  has changed state relative to the output signal of the oscillator  508 . If the output signal of the multiplexer  704  toggles relative to the oscillator  508  output signal, then the toggle detector  708   1  causes the multiplexers  706   1  to pass the output signal of the multiplexer  704 . Otherwise, should the output signal of the multiplexer  704  not toggle relative to the output signal of the oscillator  508 , the multiplexer  706   1  will output a logic zero level signal. 
     A multiplexer  706   2  receives at its first and second inputs the output signal of the oscillator  508  and a logic zero level signal, respectively. A toggle detector  708   2  controls the multiplexer  706   2  in accordance with the oscillator  508  output signal. In other words, the toggle detector  708   2  determines whether the output signal of the oscillator  508  periodically changes state. If the oscillator  508  output signal does toggle, then the toggle detector  708   2  gates the multiplexer  706   2  to pass the output signal of the oscillator  508 . Otherwise, should the output signal of the oscillator  508  not toggle, then the multiplexer  706   2  will output a logic zero level signal. 
     A multiplexer  710  receives at its first and second inputs the output signals of the multiplexers  706   1  and  706   2 , respectively. Like the multiplexer  704 , the multiplexer  710  operates under the control of the logic block  506  of  FIG. 4 . Thus, depending on output signal of the logic block  506 , the multiplexer  710  will either output a selected one of the Clock_ 1  and Clock_ 2  signals (assuming at least one has toggled relative to the oscillator  508  output signal) or the output signal of the oscillator  508  (assuming it has toggled.) 
     An important distinction exists between the multiplexers  702   1  and  702   2  and the multiplexers  704  and  710 . The multiplexers  704  and  710  serve as clock multiplexers as described earlier. Advantageously, described, the safe clock multiplexer system  510  of  FIG. 5  precludes the possibility of a missing clock pulse. By controlling the passage of the Clock_ 1  and Clock_ 2  signals relative to the oscillator  508  output signal and by controlling the passage of the oscillator  508  output only if it has toggled, the safe clock multiplexer system  510  avoids a situation in which any or all of the clocks become stuck in a no-clock state. 
     The foregoing describes a clock selector circuit  500   i , including a safe multiplexer system  510 , for distributing clock pulses so as to provide for redundancy while assuring clock synchronism.