Patent Publication Number: US-10789197-B2

Title: Methods and system for providing software defined microcontroller unit (MCU)

Description:
PRIORITY 
     This application claims the benefit of priority based upon U.S. Provisional Patent Application Ser. No. 62/505,554, filed on May 12, 2017 in the name of the same inventor and entitled “Method and System for Providing Software Defined Microcontroller Unit,” the disclosure of which is hereby incorporated into the present application by reference. 
    
    
     FIELD 
     The exemplary embodiment(s) of the present invention relates to the field of computer hardware and software. More specifically, the exemplary embodiment(s) of the present invention relates to on-chip processor and/or microcontroller unit (“MCU”). 
     BACKGROUND 
     With increasing popularity of network communication, artificial intelligence (AI), IoT (Internet of Things), and/or robotic control, the demand for more and faster data is constantly growing. To handle and facilitate voluminous data between electronic systems or computers, high speed interfaces components are typically required. To properly handle various different types of interface standards or protocols, various different types of microcontrollers (“MCUs”) are generally employed. 
     A typical microcontroller (“MCU”) contains one or more processors integrated in a single integrated circuit (“IC”). A conventional MCU includes memory devices and logical circuits used for embedded applications such as input/output (“IO”) management. In application, MCU can be used in managing products and devices, such as automobile control systems, computer network systems, medical systems, remote controls, vehicle controls, robotic applications, machinery controls, office machines, appliances, power tools, toys and the like. Various different types of peripherals require diverse types of MCUs to handle various digital computing and/or network industry(s). Different peripherals may require MCUs in different environments, sensing and/or controlling electrical systems, industry control, automobile, network communications, and so on. 
     A drawback associated with typical MCUs is that, in general, a specific MCU configuration is required for a specific type of interface communication. 
     SUMMARY 
     One embodiment of the present invention discloses a configurable microcontroller unit (“CMU”) capable of providing one or more programmable input and output (“I/O”) interfaces. The CMU includes a processor, I/O ports, and programmable microcontroller (“PM”). The processor is configured to communicate with a host central processing unit (“CPU”) based on a set of predefined instruction code. The I/O ports are used to transmit information between the processor and an external device. The PM facilitates communication interfaces between the I/O ports and one or more external devices via one or more configurable communication standards selected by the PM in accordance with interface programming microcode. 
     Alternatively, an embodiment discloses a process for providing a configurable microcontroller unit (“CMU”) for identifying at least one embedded function. For example, after searching a bit map or software via a communication network for enabling the CMU to perform the embedded function, the bit map is downloaded via the communication network once the bit map is located. Once the CMU is programmed in response to the bit map, the embedded function performed by the CMU is verified in accordance with the downloaded bit map. 
     Additional features and benefits of the exemplary embodiment(s) of the present invention will become apparent from the detailed description, figures and claims set forth below. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The exemplary embodiment(s) of the present invention will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the invention, which, however, should not be taken to limit the invention to the specific embodiments, but are for explanation and understanding only. 
         FIG. 1  is a diagram illustrating a configurable microcontroller unit (“CMU”) capable of providing communication interface based on programmable microcode in accordance with one embodiment of the present invention; 
         FIG. 2  is a block diagram illustrating a programmable processor used in CMU in accordance with one embodiment of the present invention; 
         FIG. 3  is a block diagram illustrating a CMU with programmable ports in accordance with one embodiment of the present invention; 
         FIGS. 4-6  are block diagrams illustrating a CMU containing a programmable microcontroller (“PM”) in accordance with one embodiment of the present invention; 
         FIG. 7  is a block diagram illustrating a memory structure used in CMU in accordance with one embodiment of the present invention; 
         FIG. 8  is a block diagram illustrating configurable switchers for programming PM in accordance with one embodiment of the present invention; 
         FIGS. 9-10  are block diagrams illustrating a process of programming a CMU via a cloud in accordance with one embodiment of the present invention; 
         FIG. 11  is a flowchart illustrating a process of programming a CMU using downloaded bit map in accordance with one embodiment of the present invention; 
         FIG. 12  is a diagram illustrating a computer network capable of providing embedded function via CMU in accordance with one embodiment of the present invention; and 
         FIG. 13  is a block diagram illustrating a digital processing system or component capable of processing and/or executing instruction used in CMU in accordance with one embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION 
     Embodiments of the present invention are described herein with context of a method and/or apparatus for providing selectable interface managements via one or more configurable MCU(s). 
     The purpose of the following detailed description is to provide an understanding of one or more embodiments of the present invention. Those of ordinary skills in the art will realize that the following detailed description is illustrative only and is not intended to be in any way limiting. Other embodiments will readily suggest themselves to such skilled persons having the benefit of this disclosure and/or description. 
     In the interest of clarity, not all of the routine features of the implementations described herein are shown and described. It will, of course, be understood that in the development of any such actual implementation, numerous implementation-specific decisions may be made in order to achieve the developer&#39;s specific goals, such as compliance with application- and business-related constraints, and that these specific goals will vary from one implementation to another and from one developer to another. Moreover, it will be understood that such a development effort might be complex and time-consuming but would nevertheless be a routine undertaking of engineering for those of ordinary skills in the art having the benefit of embodiment(s) of this disclosure. 
     Various embodiments of the present invention illustrated in the drawings may not be drawn to scale. Rather, the dimensions of the various features may be expanded or reduced for clarity. In addition, some of the drawings may be simplified for clarity. Thus, the drawings may not depict all of the components of a given apparatus (e.g., device) or method. The same reference indicators will be used throughout the drawings and the following detailed description to refer to the same or like parts. 
     In accordance with the embodiment(s) of present invention, the components, process steps, and/or data structures described herein may be implemented using various types of operating systems, computing platforms, computer programs, and/or general-purpose machines. In addition, those of ordinary skills in the art will recognize that devices of a less general-purpose nature, such as hardware devices, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), or the like, may also be used without departing from the scope and spirit of the inventive concepts disclosed herein. Where a method comprising a series of process steps is implemented by a computer or a machine and those process steps can be stored as a series of instructions readable by the machine, they may be stored on a tangible medium such as a computer memory device (e.g., ROM (Read Only Memory), PROM (Programmable Read Only Memory), EEPROM (Electrically Erasable Programmable Read Only Memory), FLASH Memory, Jump Drive, and the like), magnetic storage medium (e.g., tape, magnetic disk drive, and the like), optical storage medium (e.g., CD-ROM, DVD-ROM, paper card and paper tape, and the like) and other known types of program memory. 
     The term “system” or “device” is used generically herein to describe any number of components, elements, sub-systems, devices, packet switch elements, packet switches, access switches, routers, networks, computer and/or communication devices or mechanisms, or combinations of components thereof. The term “computer” includes a processor, memory, and buses capable of executing instruction wherein the computer refers to one or a cluster of computers, personal computers, workstations, mainframes, or combinations of computers thereof. 
     One embodiment of the present invention discloses a configurable microcontroller unit (“CMU”) capable of providing one or more programmable input and output (“I/O”) interfaces. The CMU includes a processor, I/O ports, and programmable microcontroller (“PM”). The processor is configured to communicate with a host central processing unit (“CPU”) based on a set of predefined instruction code. The I/O ports are used to transmit information between the processor and an external device. The PM facilitates communication interfaces between the I/O ports and one or more external devices via one or more configurable communication standards selected by the PM in accordance with interface programming microcode. 
     Alternatively, an embodiment discloses a process for providing a configurable microcontroller unit (“CMU”) for identifying at least one embedded function. For example, after searching a bit map or software via a communication network for enabling the CMU to perform the embedded function, the bit map is downloaded via the communication network once the bit map is located. Once the CMU is programmed in response to the bit map, the embedded function performed by the CMU is verified in accordance with the downloaded bit map. 
       FIG. 1  is a diagram  100  illustrating a configurable microcontroller unit (“CMU”)  102  capable of providing communication interface based on programmable microcode in accordance with one embodiment of the present invention. In one aspect, CMU  102  includes a programmable processor  110 , programmable memory, programmable I/O component  116 , and programming code storage  106 . Programmable code storage  106 , in one aspect, stores processor configuration code  120 , memory configuration code  122 , and I/O configuration code  126 . It should be noted that the underlying concept of the exemplary embodiment(s) of the present invention would not change if one or more blocks (circuit or elements) were added to or removed from diagram  100 . 
     Processor  110 , in one aspect, is configurable based on the applications. For example, processor  110  can be programmed via programmable microcode stored in programmable code storage  106  to be able to execute ARM based instruction code. For instance, a programmable processor can be programmed or configured to be able to execute instructions in accordance with ARM, MIPS, X86, or PowerPC microcode. In an alternative embodiment, processor  110  is a regular processor or fixed processor (nonprogrammable) capable of managing programmable I/O component  116  and/or programmable memory  112 . A benefit of having a programmable processor is that the programmable processor can provide additional flexibility to end users. 
     Memory  112  can be a configurable or static memory devices depending on the applications. In one embodiment, memory  112  is a programmable memory capable of being programmed based on the memory configuration code  122  stored in programmable code storage  106 . For example, memory  112  can be programmed into multiple different storage capacities for handling different I/O ports. Alternatively, memory  112  can be programmed to use onboard flash memory, SRAM (Static random-access memory), and/or RAM depending on the applications as well as user&#39;s preferences. In an alternative embodiment, memory  112  can be a static or regular memory devices which can be conventional flash memory, SRAM, RAM, or a combination of flash, SRAM, and RAM storage device. 
     I/O component  116 , in one embodiment, includes a set of I/O ports and interface microcontroller. In one aspect, the interface microcontroller is a programmable microcontroller (“PM”) based on I/O configuration code  126  in programmable code storage  106 . A function of PM is to facilitate data communication or peripheral interface between external device(s) and processor  110  via the set of I/O ports. For example, the peripheral interfaces include, but not limited to, Inter-Integrated Circuit (“I 2 C”), Serial Peripheral Interface (“SPI”), universal asynchronous receiver/transmitter (“UART”), and the like. A benefit for employing the PM is that PM provides flexibility to CMU to handle multiple interface standards. 
     I 2 C, in one example, contains a multi-master, multi-slave, single-ended, and serial computer bus. An exemplary application of I 2 C is that it can be used for attaching lower-speed peripheral for short-distance and intra-board communication. The SPI bus is a synchronous serial communication interface specification used for short distance communication, such as in embedded systems. In one example, SPI devices communicate in full duplex mode using a master-slave architecture with a single master. The master device originates the frame for reading and writing. It should be noted that SPI can also be referred to as a four-wire serial bus, as oppose to three-, two-, and one-wire serial buses. UART is a computer hardware device for asynchronous serial communication in which the data format and transmission speeds may be configurable. In one example, some electric signaling levels and methods are handled by a driver circuit external to the UART. 
     Programmable code storage  106 , in one embodiment, is used to store programming microcode for programming programmable devices such as programmable processor  110 , programmable memory  112 , and/or programmable I/O component  116 . In one aspect, storage  106  divides its memory space into three portions for storing processor configuration code  120 , memory configuration code  122 , and I/O configuration code  126 . Alternatively, storage  106  contains processor configuration memory for storing processor configuration code  120 , memory configuration memory for storing memory configuration code  122 , and/or I/O configuration memory for storing I/O configuration code  1126 . 
     It should be noted that configuration codes such as code  120 - 126  can be obtained from a user, cloud, and/or providers. 
     A function of CMU  102 , in one embodiment, is to provide programmable I/O interfaces using a processor  110 , I/O ports  118 , and PM. The processor is configured to communicate with a host central processing unit (“CPU”), not shown if  FIG. 1 , based on a set of predefined instruction code. Processor  110 , in one aspect, is a programmable processor capable of including hard macro or macrocode operable to selectively execute instruction sets based on Advanced RISC (reduced instruction set computing) Machine (“ARM”), Million Instructions Per Second (“MIPS”), Argonaut RISC Core (“ARC”), X86, or Power in accordance with processor programmable code. 
     The I/O ports  118  are used to transmit information between the processor and an external (or peripheral) device. For example, one or more I/O ports are configured to couple to multiple external devices via one or more buses. Different bus operates under different bus or interface standards. For instance, the standards include, but not limited to, analog comparator protocol, A/D converter protocol, LCD interface protocol, USART protocol, SPI protocol, and/or TWI protocol. 
     The PM which is coupled to the processor facilitates communication interfaces between I/O ports  118  and one or more external devices via at least one of several configurable communication standards selected by the PM in accordance with interface programming microcode such as I/O configuration code  126 . In one embodiment, the PM includes multiple programmable interfaces configured to facilitate communication between I/O ports  118  and one or more external devices in accordance with the interface programming microcode. The programmable interfaces, in one example, are configured to utilize inter-integrated circuit (“I2C”) to facilitate communication between I/O ports  118  and external device(s) in accordance with the set of predefined programming microcode. The programmable interfaces can also be configured to employ serial peripheral interface (“SPI”) bus protocol to facilitate communication between I/O ports  118  and external device(s). The programmable interfaces, in another example, are configured to utilize universal asynchronous receiver-transmitter (“UART”) interface protocol to facilitate communication between I/O ports  118  and external devices. Alternatively, the programmable interfaces can also be configured to utilize Integer (“Int”) interface protocol to facilitate communication between I/O ports  118  and an external device(s) based on predefined programming microcode. Furthermore, the programmable interfaces are configured to utilize two-wire interface (“TWI”) protocol to facilitate communication between I/O ports  118  and one or more external devices according to programming microcode. Also, the programmable interfaces are configured to utilize Timer interface protocol to facilitate communication between the I/O ports and one or more external devices in response to a set of predefined programming microcode. 
     CMU  102 , in one aspect, further includes a memory coupled to the processor and configured to store the predefined programming microcode downloadable from a cloud system. The memory, in one example, includes a flash memory for storing downloaded bitmaps from a remote location via a communication network. The memory may include a static random-access memory (“SRAM”) for storing data. The SRAM, for example, is a configurable storage device capable of setting a programmable bandwidth in accordance with memory programmable-code. In one aspect, a portion of the memory is configurable capable of being configured to one of a single port and dual port in accordance with memory programmable-code. 
     An advantage of employing a CMU over a traditional MCU is that CMU provides programmability thereby CMU can facilitate multiple different peripheral interface protocols based on the microcode. 
       FIG. 2  is a block diagram  200  illustrating a programmable processor  202  used in CMU in accordance with one embodiment of the present invention. Processor  202 , in one embodiment, includes programmable processor  222 , selecting logic  220 , ARM core  210 , MIPS core  212 , X86 core, PowerPC core  216 , and FPGA core  218 . It should be noted that core refers to software or firmware microcode capable of programming programmable processor  222  into one of ARM, MIPS, X86, PowerPC, or other FPGA logic depending on which one of cores  210 - 218  is selected. It should be noted that the underlying concept of the exemplary embodiment(s) of the present invention would not change if one or more blocks (circuit or elements) were added to or removed from diagram  200 . 
       FIG. 3  is a block diagram  300  illustrating a memory device  308  with programmable ports in accordance with one embodiment of the present invention. Memory device  308 , in one embodiment, can be a programmable memory or static nonprogrammable memory such as a regular flash memory or SRAM. In one aspect, device  308  includes a set of ports  302 - 304 , memory array  310  with n bits and m rows, and configurable logic  306 . Configurable logic  306 , in one embodiment, manages or controls size of storage capacity for a single port as well as dual port. It should be noted that the underlying concept of the exemplary embodiment(s) of the present invention would not change if one or more blocks (circuit or elements) were added to or removed from diagram  300 . 
     It should be noted that memory  308  can be SRAM using hard macro while, in some cases, it is configurable. For example, memory  308  can be configured with a single port or dual port. Alternatively, data width can be programmed to 8, 16, and/or 32 bits wide. In addition, the depth of array can also be configurable to a range of 1K, 2K, 16K, 32K and the like. Memory  308  can also be flash memory with hard macro having access behavior just as SRAM. In one example, FLASH and/or SRAM can be accessed by CPU in one memory addressing scheme which makes it just like ordinary MCU&#39;s SRAM and/or FLASH scheme. 
       FIG. 4  is a block diagram  400  illustrating a CMU containing a programmable microcontroller (“PM”) in accordance with one embodiment of the present invention. Diagram  400  includes a processor or CPU  110 , memory  112 , I/O ports  118 , programming code storage  106 , and PM  402 . Programmable code storage  106  also known as configuration component stores processor configuration code for programming PM, processor  110 , and/or memory  112 . It should be noted that the underlying concept of the exemplary embodiment(s) of the present invention would not change if one or more blocks (circuit or elements) were added to or removed from diagram  400 . 
     PM  402 , in one embodiment, is configured to provide peripheral data communication between external or peripheral devices and a host computer using a software defined matrix and logic (“SDML”). In one aspect, SDML is a programmable logic capable of performing certain tasks based on microcode. An exemplary SDML is similar to a field-programmable gate array (“FPGA”) or programmable logic device (“PLD”) in which the logic or integrated circuit (“IC”) is required to be programmed before it can be used. For example, PM  402  can be programmed to facilitate communication using I 2 C bus standard. Alternatively, PM  402  is programmed to allow a portion of I/O ports to operate SPI bus standard while another portion of I/O ports to operate UART interface protocol. PM  402 , in one aspect, can be programmed to facilitate communication using I2C, SPI, UART, integer another integer (“Int”), two-wire interface (“TWI”), and/or timer interface. 
     An advantage of using PM  402  is that PM  402  is flexible and it can be programmed to handle various interfaces for an MCU. Another advantage of using PM  402  is that it allows a user to update, delete, and/or added interface protocols after the CMU is installed in a system. 
       FIG. 5  is a block diagram  500  illustrating a CMU containing a programmable microcontroller (“PM”) in accordance with one embodiment of the present invention. Diagram  500  which is similar to diagram  400  shown in  FIG. 4  includes a processor or CPU  110 , memory  112 , I/O ports  118 , programming code storage  106 , and PM  502 . Programmable code storage  106  also known as configuration component stores processor configuration code for programming PM, processor  110 , and/or memory  112 . It should be noted that the underlying concept of the exemplary embodiment(s) of the present invention would not change if one or more blocks (circuit or elements) were added to or removed from diagram  500 . 
     PM  502 , in one embodiment, is a configurable device capable of providing peripheral data communication between external or peripheral devices and a host computer using one of I 2 C, SPI, UART, and Int. PM  502  is organized with some fixed core such as block  506  plus some software defined logic or core. In one aspect, PM  502  is capable of selecting an interface block to be used for data communication. The microcode, in one example, can be provided by the user or provider via a remote location. For example, PM  502  can program block  506  to handle communication between I/O point  508  and processor  110 . 
     An advantage of using PM  502  is that it provides flexibility while reducing the complexity of programmable logic. 
       FIG. 6  is a block diagram  600  illustrating a CMU containing a programmable microcontroller (“PM”) in accordance with one embodiment of the present invention. Diagram  600  which is similar to diagram  500  shown in  FIG. 5  includes a processor or CPU  110 , memory  112 , I/O ports  118 , programming code storage  106 , and PM  602 . Programmable code storage  106  also known as configuration component stores processor configuration code for programming PM, processor  110 , and/or memory  112 . It should be noted that the underlying concept of the exemplary embodiment(s) of the present invention would not change if one or more blocks (circuit or elements) were added to or removed from diagram  600 . 
     PM  602 , which is similar to PM  502  shown in  FIG. 5 , is a configurable device capable of providing peripheral data communication between external or peripheral devices and a host computer using one of Timer, TWI, I 2 C, LCD, and/or other X logic(s). PM  602  is organized with some fixed core such as block  610  plus some software defined logic or core. In one aspect, PM  602  is capable of selecting an interface block to be used for data communication. The microcode, in one example, can be provided by the user or provider via a remote location. For example, PM  602  can program block  610  to handle communication between I/O ports  606 - 608  and processor  110 . 
     An advantage of using PM  602  is that it provides flexibility using hard macro and programmable logic. 
     In one aspect, CMU essentially offers an MCU hardware platform with one main stream CPUs, such as ARM, MIPS, x86, etc. wherein the components are defined by a downloadable configuration file. When user choose certain configuration such as different sizes of SRAM, FLASH Memory, different peripheral or different number of ports, the specific configuration file can be downloaded from a cloud. A benefit is to allow users to make their product decision with flexibility of hardware design. Another benefit is that the configurable MCU or CMU is upgradable even after the CMU is shipped. Also, by offering a common platform, the hardware fabrication and/or resources are reduced. 
     For SW Defined MCU components, CMU can have a programmable CPU and programmable I/O component. CPU or processor can be Hard Macro which can be ARM, MIPS, ARC, X86, and Power PC, et cetera. A reason to choose the Hard Macro is because the MCU architectures are converging. Hard Macro giving most efficiency on performance and power balance which is a cost-effective approach. I/O component can also be a hard Macro to provide input and output of CMU. In one example, the IO standard can be configurable to support different IO standard such as LVCMOS3.3, SSTL2.5, SSTL1.8, etc. 
       FIG. 7  is a block diagram illustrating a memory structure used in CMU in accordance with one embodiment of the present invention. Diagram  700  illustrates a configurable MCU or CMU capable of receiving programming or configuration code from outside of CMU via a port  730 . Upon receipt of the configuration code or microcode, the code is stored in a memory cell group  732 . It should be noted that the underlying concept of the exemplary embodiment(s) of the present invention would not change if one or more blocks (circuit or elements) were added to or removed from diagram  700 . 
     Diagram  700  further includes a configuration engine  736  which is used to program the programmable devices based on received code. In one aspect, configure engine  736  is coupled to memory cells  732 . Interface port  730  to outside programmer, PC, or ATE (automatic test equipment) is connected to data buses with one or more bus protocols, such as Jtag, I 2 C, SPI, and/or data bus connecting to a CPU. It should be noted that configure engine  736  receives data from an interface and transmits data to memory cell. 
     Diagram  702  illustrates one-dimensional memory cells organized in a series wherein the data within the series is shifted from one to next based on clock cycles. In one example, memory cells can be 6T SRAM cells or Non-volatile Memory cells. Diagram  706  illustrates two-dimensional memory cells as a normal SRAM array. In one example, each memory cell can send out one control signal with value as either “0” or “1”. The data is shifted from one to next. 
     It should be noted that SW Defined Matrix and Logic or SDML refers to a matrix which can be formed with both connections and logics. The outputs of memory cells determine the formed connection and logic. The logic can be predefined in Hard Macro and subsequently the memory cell selects user desired logic. More advanced method can use programmable logic such as GAL, CPLD&#39;s Macro or FPGA&#39;s Look Up Table and Registers. 
       FIG. 8  is a block diagram  800  illustrating a configurable switcher for programming PM in accordance with one embodiment of the present invention. Diagram  800  includes three cells  802 - 808 , three switches  812 - 818 , three input lines A, B, C, and one output line  810 . Switch  812  controls whether the data on input line A should go through to output line  810  and switch  816  controls whether the data on input line B should go through to output line  810 . Also, switch  818  controls whether the data on input line C should go to output line  810 . To determine which data on input line should be the output line  810 , the values in cells  802 - 808  determine which switch should be on. For example, if cell  2   806  has an on-logic value, switch  816  should be on and the data on input line B should pass through to output line  810 . In one aspect, cells such as cells  802 - 808  and switches  812 - 818  are used to form connections and logics in PM. 
     For example, if cell output is 1, the switch will be on. Otherwise, it will be off. Assume A is an I 2 C output, B is a timer output, and C is SPI output. By make Cell value as “0” or “1”, user can choose which Hard Macro will be used and output to O. 
       FIG. 9  is a block diagram illustrating a process of programming a CMU via a cloud in accordance with one embodiment of the present invention. Diagram  900  includes a laptop  902 , CMU  906 , cloud  908 , and server  910 . In one embodiment, server  910  stores configuration file(s) wherein server  910  can be a vendor server. Laptop computer  902  which is controlled by a user is able to download a configuration file from server  910  via cloud  908 . The configuration file is subsequently used to program MCU  906  which is connected to laptop computer  902 . In one aspect, laptop computer  902  is able to search a configuration file via online providers for configuring CMU  906  to the user&#39;s desire. 
     Diagram  920  includes an automatic test equipment (“ATE”)  922 , cloud  908 , and server  910  wherein ATE houses multiple CMUs. ATE  922  is used to facilitate volume production in which it can program multiple CMUs simultaneously. Upon downloading configuration files or configuration microcode from vendor server  910 , ATE is able to program CMUs based on the downloaded configuration file concurrently. 
       FIG. 10  is a block diagram illustrating a process of programming a CMU via a cloud in accordance with one embodiment of the present invention. Diagram  1000  includes a laptop computer  902 , cloud  908 , and CMU  906  wherein laptop computer  902  is coupled to CMU  906  via cloud  908 . In one aspect, laptop computer  902  is capable of configuring CMU  906  via cloud  908  through a process of configuration operation remotely. It should be noted that the underlying concept of the exemplary embodiment(s) of the present invention would not change if one or more blocks (circuit or elements) were added to or removed from diagram  1000 . 
     The exemplary embodiment of the present invention includes various processing steps, which will be described below. The steps of the embodiment may be embodied in machine or computer executable instructions. The instructions can be used to cause a general purpose or special purpose system, which is programmed with the instructions, to perform the steps of the exemplary embodiment of the present invention. Alternatively, the steps of the exemplary embodiment of the present invention may be performed by specific hardware components that contain hard-wired logic for performing the steps, or by any combination of programmed computer components and custom hardware components. 
       FIG. 11  is a flowchart  1100  illustrating a process of programming a CMU using downloaded bit map in accordance with one embodiment of the present invention. At block  1102 , a process or method capable of providing a CMU identifies a first embedded function of a configurable MCU for facilitating network interface between a host and an external device based on a first interface protocol. For example, an I 2 C interface function is determined for communicating with at least one external device. Alternatively, a universal asynchronous receiver-transmitter (“UART”) interface function is determined for communicating with at least one external device. 
     At block  1104 , after searching a first bit map via a communication network for programming the configurable MCU to perform the first embedded function, the first bit map, at block  1106 , is downloaded from a cloud system via the communication network once the first bit map is located. It should be noted that the configurable MCU is the same or similar to CMU. 
     At block  1108 , upon programming the configurable MCU in response to the first bit map, the first embedded function at block  1110  is verified once the configurable MCU is programmed. In one embodiment, the first bit map is stored in a local storage memory. The process is further able to search a new bit map associated with the first embedded function for programming the configurable CMU if the first bit map fails to verify the first embedded function performed by the configurable CMU. In one aspect, after identifying a second embedded function of the configurable CMU for facilitating network interface between a host and an external device based on a second interface protocol, the second bit map is downloaded from the cloud system via the communication network. The process programs or configures the configurable MCU in response to the second bit map. 
     It should be noted that inter-integrated circuit (“I 2 C”) is a multi-master, multi-slave, single-ended, serial computer bus. It is usually employed for attaching lower-speed peripheral ICs to processors and microcontrollers in short-distance, intra-board communication. 
     Alternatively, a Serial Peripheral Interface (“SPI”) bus is a synchronous serial communication interface specification used for short distance communication, primarily in embedded systems. SPI bus can be used in digital cards and/or liquid crystal displays. SPI devices can communicate in dual mode using the master-slave architecture with a master. For example, the master device provides the frame for reading and writing while several slave devices can be supported via selections with individual slave select (SS) lines. 
       FIG. 12  is a diagram illustrating a computer network capable of providing embedded function via configurable MCU in accordance with one embodiment of the present invention. In this network environment, a system  1201  is coupled to a wide-area network  1202 , LAN  1206 , Network  1201 , and server  1204 . Wide-area network  1202  includes the Internet, or other proprietary networks including America On-Line™, SBC™, Microsoft Network™, and Prodigy™. Wide-area network  1202  may further include network backbones, long-haul telephone lines, Internet service providers, various levels of network routers, and other means for routing data between computers. 
     Server  1204  is coupled to wide-area network  1202  and is, in one aspect, used to route data to clients  1210 - 1212  through a local-area network (“LAN”)  1206 . Server  1204  is coupled to storage device  1222  to enhance overall memory efficiency. 
     The LAN connection allows client systems  1210 - 1212  to communicate with each other through LAN  1206 . Using conventional network protocols, USB portable system  1230  may communicate through wide-area network  1202  to client computer systems  1210 - 1212 , supplier system  1220  and storage device  1222 . For example, client system  1210  is connected directly to wide-area network  1202  through direct or dial-up telephone or other network transmission lines. Alternatively, clients  1210 - 1212  may be connected through wide-area network  1202  using a modem pool. 
     Having briefly described one embodiment of the computer network in which the embodiment(s) of the present invention operates,  FIG. 12  illustrates an example of a computer system, which uses one or more configurable and/or programmable MCUs. 
       FIG. 13  is a block diagram illustrating a digital processing system capable of using the configurable CMU in accordance with one embodiment of the present invention. Computer system  500  can include a processing unit  1301 , an interface bus  1312 , and an input/output (“IO”) unit  1320 . Processing unit  1301  includes a processor  1302 , a main memory  1304 , a system bus  1311 , a static memory device  1306 , a bus control unit  1305 , an I/O element  1330 , and an NVM controller  1385 . It should be noted that the underlying concept of the exemplary embodiment(s) of the present invention would not change if one or more blocks (circuit or elements) were added to or removed from  FIG. 12 . 
     Bus  1311  is used to transmit information between various components and processor  1302  for data processing. Processor  1302  may be any of a wide variety of general-purpose processors, embedded processors, or microprocessors such as ARM® embedded processors, Intel® Core™ Duo, Core™ Quad, Xeon®, Pentium™ microprocessor, Motorola™ 68040, AMD® family processors, or Power PC™ microprocessor. 
     Main memory  1304 , which may include multiple levels of cache memories, stores frequently used data and instructions. Main memory  1304  may be RAM (random access memory), MRAM (magnetic RAM), or flash memory. Static memory  1306  may be a ROM (read-only memory), which is coupled to bus  1311 , for storing static information and/or instructions. Bus control unit  1305  is coupled to buses  1311 - 1312  and controls which component, such as main memory  1304  or processor  1302 , can use the bus. Bus control unit  1305  manages the communications between bus  1311  and bus  1312 . Mass storage memory or SSD  106 , which may be a magnetic disk, an optical disk, hard disk drive, floppy disk, CD-ROM, and/or flash memories are used for storing large amounts of data. 
     I/O unit  1320 , in one embodiment, includes a display  1321 , keyboard  1322 , cursor control device  1323 , and communication device  1325 . Display device  1321  may be a liquid crystal device, cathode ray tube (“CRT”), touch-screen display, or other suitable display device. Display  1321  projects or displays images of a graphical planning board. Keyboard  1322  may be a conventional alphanumeric input device for communicating information between computer system  500  and computer operator(s). Another type of user input device is cursor control device  1323 , such as a conventional mouse, touch mouse, trackball, or other type of cursor for communicating information between system  1300  and user(s). 
     Communication device  1325  is coupled to bus  1311  for accessing information from remote computers or servers, such as server  1004  or other computers, through wide-area network  1202 . Communication device  1325  may include a modem or a network interface device, or other similar devices that facilitate communication between computer  1300  and the network. Computer system  1300  may be coupled to a number of servers  1204  via a network infrastructure such as the infrastructure illustrated in  FIG. 12 . 
     While particular embodiments of the present invention have been shown and described, it will be obvious to those of ordinary skills in the art that based upon the teachings herein, changes and modifications may be made without departing from this exemplary embodiment(s) of the present invention and its broader aspects. Therefore, the appended claims are intended to encompass within their scope all such changes and modifications as are within the true spirit and scope of this exemplary embodiment(s) of the present invention.