Patent Publication Number: US-2023138089-A1

Title: Method for fabricating contact structure and contact structure

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application is a continuation of PCT/CN2022/098105, filed on Jun. 10, 2022, which claims priority to Chinese Patent Application No. 202111286549.8 titled “METHOD FOR FABRICATING CONTACT STRUCTURE AND CONTACT STRUCTURE” and filed on Nov. 2, 2021, the entire contents of which are incorporated herein by reference. 
    
    
     TECHNICAL FIELD 
     The present disclosure relates to the field of semiconductors, and more particularly, to a method for fabricating a contact structure and a contact structure. 
     BACKGROUND 
     In the existing technologies, in the process of manufacturing integrated circuits and electronic components, a method for improving defects in process steps of the integrated circuits is an important topic. In semiconductor processes, especially in the production of dynamic random access memory, occurrence of voids and holes in a polysilicon layer has become an important problem having a negative effect on performance and service life of semiconductor devices. 
     SUMMARY 
     The present disclosure provides a method for fabricating a contact structure, including: providing a substrate, and sequentially arranging a first polysilicon layer and a first mask layer on a surface of the substrate; performing a first etching process on the first polysilicon layer and the first mask layer to form a stepped structure where a width of the first mask layer is smaller than a width of the first polysilicon layer; performing a second etching process on the substrate by using the first polysilicon layer as a mask to form a trench; depositing a second polysilicon layer in the trench, a top of the second polysilicon layer being not higher than a bottom of the first mask layer; and performing an annealing process to form the contact structure. 
     The present disclosure also provides a contact structure fabricated by the above method. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG.  1    is a schematic diagram showing steps of a method for fabricating a contact structure according to an embodiment of the present disclosure; 
         FIGS.  2 A- 2 D  are schematic process diagrams of Steps S 10 -S 13  in  FIG.  1    according to an embodiment of the present disclosure; 
         FIG.  3    is a schematic diagram showing a step of forming a second polysilicon layer in the method for fabricating a contact structure according to an embodiment of the present disclosure; 
         FIGS.  4 A- 4 C  are schematic process diagrams of Steps S 31 -S 33  in  FIG.  3    according to an embodiment of the present disclosure; 
         FIG.  5    is a schematic diagram showing steps before sequentially arranging a first polysilicon layer and a first mask layer on a surface of the substrate in the method for fabricating a contact structure according to an embodiment of the present disclosure; 
         FIGS.  6 A- 6 G  are schematic process diagrams of Steps S 50 -S 56  in  FIG.  5    according to an embodiment of the present disclosure; 
         FIGS.  7 A- 7 C  are schematic process diagrams of Steps S 31 -S 33  in  FIG.  3    according to an embodiment of the present disclosure; 
         FIGS.  8 A- 8 C  are schematic diagrams showing an effect of the annealing process according to an embodiment of the present disclosure; 
         FIGS.  9 A- 9 D  are schematic process diagrams of Steps S 10 -S 13  in  FIG.  1    according to an embodiment of the present disclosure; and 
         FIGS.  10 A- 10 C  are schematic process diagrams of Steps S 31 -S 33  in  FIG.  3    according to an embodiment of the present disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     Embodiments of a method for fabricating a contact structure and a contact structure provided by the present disclosure will be described in detail below with reference to the accompanying drawings. 
       FIG.  1    is a schematic diagram showing steps of a method for fabricating a contact structure according to an embodiment of the present disclosure. The method includes: Step S 10 , providing a substrate, and sequentially arranging a first polysilicon layer and a first mask layer on a surface of the substrate; Step S 11 , performing a first etching process on the first polysilicon layer and the first mask layer to form a stepped structure where a width of the first mask layer is smaller than a width of the first polysilicon layer; Step S 12 , performing a second etching process on the substrate by using the first polysilicon layer as a mask to form a trench; Step S 13 , depositing a second polysilicon layer in the trench, a top of the second polysilicon layer being not higher than a bottom of the first mask layer; and Step S 14 , performing an annealing process to form the contact structure. 
       FIGS.  2 A- 2 D  are schematic process diagrams of Steps S 10 -S 13  in  FIG.  1    according to an embodiment of the present disclosure. 
     As shown in  FIG.  2 A , referring to Step S 10 , a substrate  20  is provided, and a first polysilicon layer  211  and a first mask layer  212  are sequentially arranged on the surface of the substrate  20 . In an embodiment of the present disclosure, the substrate  20  includes a shallow trench isolation structure  202 , which includes one or more of silicon oxide, silicon nitride, and silicon oxynitride. That is, a material used for the shallow trench isolation structure  202  includes one or more of silicon oxide, silicon nitride, and silicon oxynitride. In this embodiment, the shallow trench isolation structure  202  is made from silicon oxide, and the substrate  20  further includes a silicon substrate  201 . In an embodiment of the present disclosure, the surface of the substrate  20  includes an insulating layer  203 , which is positioned below the first polysilicon layer  211 . The insulating layer  203  is made from SiN. 
       FIG.  5    is a schematic diagram showing steps before sequentially arranging the first polysilicon layer  211  and the first mask layer  212  on the surface of the substrate  20  in the method for fabricating a contact structure according to an embodiment of the present disclosure. These steps include: Step S 50 , providing a substrate, forming a stacked layer on the surface of the substrate, the stacked layer comprising an insulating layer, a third polysilicon preparation layer, a first sacrificial layer, a second mask layer, a second sacrificial layer and a third mask layer from bottom to top; Step S 51 , etching the second sacrificial layer and the third mask layer to form a first groove; Step S 52 , forming a third sacrificial layer in the first groove to cover the second mask layer, the second sacrificial layer, and the third mask layer; Step S 53 , removing a part of the third sacrificial layer until the third sacrificial layer is flush with a top of the third mask layer; Step S 54 , removing the second sacrificial layer and the third mask layer; Step S 55 , etching the second mask layer, the first sacrificial layer and the third polysilicon preparation layer by using the third sacrificial layer as a mask to form a second groove, the first mask layer, and the first polysilicon layer; and Step S 56 , removing the third sacrificial layer and the second mask layer. 
       FIGS.  6 A- 6 G  are schematic process diagrams of Steps S 50 -S 56  in  FIG.  5    according to an embodiment of the present disclosure. 
     As shown in  FIG.  6 A , referring to Step S 50 , a substrate  20  is provided, and a stacked layer is formed on the surface of the substrate  20 , where the stacked layer includes an insulating layer  203 , a third polysilicon preparation layer  601 , a first sacrificial layer  602 , a second mask layer  603 , a second sacrificial layer  604 , and a third mask layer  605  from bottom to top. In an embodiment of the present disclosure, materials used for the first sacrificial layer  602  and the second sacrificial layer  604  include SOH and/or SOC. Materials of the second mask layer  603  and the third mask layer  605  include one or more of SiN, SiON, and SiCN. In an embodiment of the present disclosure, the substrate  20  includes a shallow trench isolation structure, and materials used for the shallow trench isolation structure  202  include one or more of silicon oxide, silicon nitride, and silicon oxynitride. In this embodiment, the shallow trench isolation structure  202  is made from silicon oxide, and the substrate  20  further includes a silicon substrate  201 . In an embodiment of the present disclosure, the surface of the substrate  20  includes an insulating layer  203 , and the insulating layer  203  is positioned below the third polysilicon preparation layer  601 . The insulating layer  203  is made from SiN, and the third polysilicon preparation layer  601  is made from polysilicon. 
     As shown in  FIG.  6 B , referring to Step S 51 , the second sacrificial layer  604  and the third mask layer  605  are etched to form a first groove  61 . Precise positioning and etching are keys to the technology in this step, and the second sacrificial layer  604  and the third mask layer  605  will also be removed in subsequent steps. 
     As shown in  FIG.  6 C , referring to Step S 52 , a third sacrificial layer  606  is formed in the first groove  61  to cover the second mask layer  603 , the second sacrificial layer  604 , and the third mask layer  605 . In an embodiment of the present disclosure, the third sacrificial layer  606  is made from oxide, including but not limited to silicon oxide. 
     As shown in  FIG.  6 D , referring to Step S 53 , a part of the third sacrificial layer  606  is removed until the third sacrificial layer  606  is flush with the top of the third mask layer  605 . The third mask layer  605  is exposed such that the second sacrificial layer  604  and the third mask layer  605  can be removed in subsequent steps. 
     As shown in  FIG.  6 E , referring to Step S 54 , the second sacrificial layer  604  and the third mask layer  605  are removed. In an embodiment of the present disclosure, the removing the second sacrificial layer  604  and the third mask layer  605  adopts one or more of dry removal or wet removal. 
     As shown in  FIG.  6 F , referring to Step S 55 , the second mask layer  603 , the first sacrificial layer  602  and the third polysilicon preparation layer  601  are etched by using the third sacrificial layer  606  as a mask to form a second groove  62 , the first mask layer  212 , and the first polysilicon layer  211 . 
     As shown in  FIG.  6 G , referring to Step S 56 , the third sacrificial layer  606  and the second mask layer  603  are removed. In this embodiment, the insulating layer  203 , the first polysilicon layer  211  and the first mask layer  212  are retained on the substrate  20 . 
     According to the above technical solution, by using the stepped structure in the process of fabricating the contact structure, a problem of formation of voids and holes in a bitline contact structure hole caused by a fact that a growth rate of a top of the bitline contact structure hole is greater than a growth rate of a middle of the bitline contact structure hole can be improved in a deposition process for fabrication of the bitline contact structure. Voids in the polysilicon layer of the contact structure are reduced, such that quality of the contact structure is improved, and the problem of defects in the contact structure is improved. 
     After the above steps are completed, the structure as shown in  FIG.  2 A  is obtained, including: a substrate  20 , where a first polysilicon layer  211  and a first mask layer  212  are sequentially arranged on the surface of the substrate  20 . In an embodiment of the present disclosure, the substrate  20  includes a shallow trench isolation structure, and materials used for the shallow trench isolation structure  202  include one or more of silicon oxide, silicon nitride, and silicon oxynitride. In this embodiment, the shallow trench isolation structure  202  is made from silicon oxide, and the substrate  20  further includes a silicon substrate  201 . In an embodiment of the present disclosure, the surface of the substrate  20  includes an insulating layer  203 , which is positioned below the first polysilicon layer  211 . The insulating layer  203  is made from SiN. On the basis of the structure as shown in  FIG.  2 A , the following steps are continued to be performed. 
     As shown in  FIG.  2 B , referring to Step S 11 , a first etching process is performed on the first polysilicon layer  211  and the first mask layer  212  to form a stepped structure where a width of the first mask layer  212  is smaller than a width of the first polysilicon layer  211 . In an embodiment of the present disclosure, an etching rate of the first polysilicon layer  211  in the first etching process is lower than that of the first mask layer  212 . Because the material used for the first mask layer  212  includes SOH and/or SOC and the material used for the first polysilicon layer  211  is polysilicon, a higher selectivity ratio is provided when a wet etching process is used, and it can be achieved that the etching rate of the first polysilicon layer  211  in the first etching process is lower than that of the first mask layer  212 , such that a big-end-down stepped structure may be formed. In this embodiment, a ZIVIS machine is used in the first etching process to form the stepped structure where the width of the first mask layer  212  is smaller than the width of the first polysilicon layer  211 , where the first etching process adopts a wet etching process, and an etching gas includes H 2  and/or N 2 . The stepped structure formed by etching using the ZIVIS machine can leave a larger window on the top of the contact structure in the subsequent deposition process of the contact structure, to alleviate the problem of voids and holes. 
     As shown in  FIG.  2 C , referring to Step S 12 , a second etching process is performed on the substrate  20  by using the first polysilicon layer  211  as a mask to form a trench  22 . In an embodiment of the present disclosure, the second etching process includes: etching the insulating layer  203  and the substrate  20  to form the trench  22 . 
     As shown in  FIG.  2 D , referring to Step S 13 , a second polysilicon layer  219  is deposited in the trench  22 , where a top of the second polysilicon layer  219  is not higher than a bottom of the first mask layer  212 . In this embodiment, the top of the second polysilicon layer  219  is flush with that of the original first polysilicon layer  211 . In other embodiments of the present disclosure, the top of the second polysilicon layer  219  may also be lower than that of the original first polysilicon layer  211 . 
     According to the above technical solution, by using the stepped structure in the process of fabricating the contact structure, a problem of formation of voids and holes in a bitline contact structure hole caused by a fact that a growth rate of a top of the bitline contact structure hole is greater than a growth rate of a middle of the bitline contact structure hole can be improved in a deposition process for fabrication of the bitline contact structure. Voids in the polysilicon layer of the contact structure are reduced, such that quality of the contact structure is improved, and the problem of defects in the contact structure is improved. 
     In other embodiments of the present disclosure,  FIGS.  9 A- 9 D  are schematic process diagrams of Steps S 10 -S 13  in  FIG.  1   . 
     As shown in  FIG.  9 A , referring to Step S 10 , a substrate  20  is provided, and a first polysilicon layer  211  and a first mask layer  212  are sequentially arranged on the surface of the substrate  20 . In an embodiment of the present disclosure, the substrate  20  includes a shallow trench isolation structure, and materials used for the shallow trench isolation structure  202  include one or more of silicon oxide, silicon nitride, and silicon oxynitride. In this embodiment, the shallow trench isolation structure  202  is made from silicon oxide, and the substrate  20  further includes a silicon substrate  201 . In an embodiment of the present disclosure, the surface of the substrate  20  includes an insulating layer  203 , which is positioned below the first polysilicon layer  211 . The insulating layer  203  is made from SiN. 
     As shown in  FIG.  9 B , referring to Step S 11 , a first etching process is performed on the first polysilicon layer  211  and the first mask layer  212  to form a stepped structure where a width of the first mask layer  212  is smaller than a width of the first polysilicon layer  211 . In an embodiment of the present disclosure, an etching rate of the first polysilicon layer  211  in the first etching process is lower than that of the first mask layer  212 . Because the material used for the first mask layer  212  includes SOH and/or SOC and the material used for the first polysilicon layer  211  is polysilicon, a higher selectivity ratio is provided when a wet etching process is used, and it can be achieved that the etching rate of the first polysilicon layer  211  in the first etching process is lower than that of the first mask layer  212 , such that a big-end-down stepped structure may be formed. In this embodiment, a ZIVIS machine is used in the first etching process to form the stepped structure where the width of the first mask layer  212  is smaller than the width of the first polysilicon layer  211 , where the first etching process adopts a wet etching process, and an etching gas includes H 2  and/or N 2 . The stepped structure formed by etching using the ZIVIS machine can leave a larger window on the top of the contact structure in the subsequent deposition process of the contact structure, to alleviate the problem of voids and holes. 
     As shown in  FIG.  9 C , referring to Step S 12 , a second etching process is performed on the substrate  20  by using the first polysilicon layer  211  as a mask to form the trench  22 . In an embodiment of the present disclosure, the second etching process includes: etching the insulating layer  203  and the substrate  20  to form the trench  22 . 
     As shown in  FIG.  9 D , referring to Step S 13 , a second polysilicon layer  219  is deposited in the trench  22 , where a top of the second polysilicon layer  219  is not higher than a bottom of the first mask layer  212 . In this embodiment, the top of the second polysilicon layer  219  is lower than that of the original first polysilicon layer  211 . This may expose possible holes and voids and facilitate removal of these holes and voids during subsequent annealing steps. 
     According to the above technical solution, by using the stepped structure in the process of fabricating the contact structure, a problem of formation of voids and holes in a bitline contact structure hole caused by a fact that a growth rate of a top of the bitline contact structure hole is greater than a growth rate of a middle of the bitline contact structure hole can be improved in a deposition process for fabrication of the bitline contact structure. Voids in the polysilicon layer of the contact structure are reduced, such that quality of the contact structure is improved, and the problem of defects in the contact structure is improved. 
     The step of forming the second polysilicon layer  219  in the above steps is further described as follows. 
       FIG.  3    is a schematic diagram showing a step of forming the second polysilicon layer  219  in the method for fabricating a contact structure according to an embodiment of the present disclosure. The step of forming the second polysilicon layer further includes: Step S 31 , depositing polysilicon on a surface of the stepped structure and a surface of the trench to form a first polysilicon preparation layer; Step S 32 , depositing polysilicon on a surface of the first polysilicon preparation layer to form a second polysilicon preparation layer filling a gap between the trench and the stepped structure; and Step S 33 , etching the second polysilicon preparation layer to form the second polysilicon layer. 
       FIGS.  4 A- 4 C  are schematic process diagrams of Steps S 31 -S 33  in  FIG.  3    according to an embodiment of the present disclosure. 
     As shown in  FIG.  4 A , referring to Step S 31 , polysilicon is deposited on the surface of the stepped structure and the surface of the trench  22  to form a first polysilicon preparation layer  217 . In an embodiment of the present disclosure, the first polysilicon preparation layer  217  and the second polysilicon layer  219  are made from different polysilicon materials. 
     As shown in  FIG.  4 B , referring to Step S 32 , polysilicon is deposited on a surface of the first polysilicon preparation layer  217  to form a second polysilicon preparation layer  218  filling a gap between the trench  22  and the stepped structure. In an embodiment of the present disclosure, the second polysilicon preparation layer  218  and the first polysilicon preparation layer  217  are made from different polysilicon materials. 
     As shown in  FIG.  4 C , referring to Step S 33 , the second polysilicon preparation layer  218  is etched to form a second polysilicon layer  219 . Atop of the second polysilicon layer  219  is not higher than a bottom of the first mask layer  212 . In this embodiment, the top of the second polysilicon layer  219  is flush with that of the original first polysilicon layer  211 . In other embodiments of the present disclosure, the top of the second polysilicon layer  219  may also be lower than that of the original first polysilicon layer  211 . 
       FIGS.  7 A- 7 C  are schematic process diagrams of Steps S 31 -S 33  in  FIG.  3    according to an embodiment of the present disclosure. 
     As shown in  FIG.  7 A , referring to Step S 31 , polysilicon is deposited on the surface of the stepped structure and the surface of the trench  22  to form the first polysilicon preparation layer  217 . In an embodiment of the present disclosure, the first polysilicon preparation layer  217  and the second polysilicon layer  219  are made from the same polysilicon material. The deposited polysilicon and the second polysilicon layer  219  jointly form the first polysilicon preparation layer  217 . 
     As shown in  FIG.  7 B , referring to Step S 32 , polysilicon is deposited on a surface of the first polysilicon preparation layer  217  to form a second polysilicon preparation layer  218  filling a gap between the trench  22  and the stepped structure. In an embodiment of the present disclosure, the second polysilicon preparation layer  218  and the first polysilicon preparation layer  217  are made from the same polysilicon material. The deposited polysilicon and the first polysilicon preparation layer  217  jointly form the second polysilicon preparation layer  218 . 
     As shown in  FIG.  7 C , referring to Step S 33 , the second polysilicon preparation layer  218  is etched to form the second polysilicon layer  219 . The top of the second polysilicon layer  219  is not higher than the bottom of the first mask layer  212 . In this embodiment, the top of the second polysilicon layer  219  is flush with that of the original first polysilicon layer  211 . In other embodiments of the present disclosure, the top of the second polysilicon layer  219  may also be lower than that of the original first polysilicon layer  211 . 
     According to the above technical solution, by using the stepped structure in the process of fabricating the contact structure, a problem of formation of voids and holes in a bitline contact structure hole caused by a fact that a growth rate of a top of the bitline contact structure hole is greater than a growth rate of a middle of the bitline contact structure hole can be improved in a deposition process for fabrication of the bitline contact structure. Voids in the polysilicon layer of the contact structure are reduced, such that quality of the contact structure is improved, and the problem of defects in the contact structure is improved. 
     In other embodiments of the present disclosure,  FIGS.  10 A- 10 C  are schematic process diagrams of Steps S 31 -S 33  in  FIG.  3   . 
     As shown in  FIG.  10 A , referring to Step S 31 , polysilicon is deposited on the surface of the stepped structure and the surface of the trench  22  to form the first polysilicon preparation layer  217 . In an embodiment of the present disclosure, the first polysilicon preparation layer  217  and the second polysilicon layer  219  are made from the same polysilicon material. The deposited polysilicon and the second polysilicon layer  219  jointly form the first polysilicon preparation layer  217 . 
     As shown in  FIG.  10 B , referring to Step S 32 , polysilicon is deposited on a surface of the first polysilicon preparation layer  217  to form a second polysilicon preparation layer  218  filling a gap between the trench  22  and the stepped structure. In an embodiment of the present disclosure, the second polysilicon preparation layer  218  and the first polysilicon preparation layer  217  are made from the same polysilicon material. The deposited polysilicon and the first polysilicon preparation layer  217  jointly form the second polysilicon preparation layer  218 . 
     As shown in  FIG.  10 C , referring to Step S 33 , the second polysilicon preparation layer  218  is etched to form the second polysilicon layer  219 . The top of the second polysilicon layer  219  is not higher than the bottom of the first mask layer  212 . In this embodiment, the top of the second polysilicon layer  219  is lower than that of the original first polysilicon layer  211 . 
     According to the above technical solution, by using the stepped structure in the process of fabricating the contact structure, the problem of formation of voids and holes in a bitline contact structure hole caused by a fact that a growth rate of a top of the bitline contact structure hole is greater than a growth rate of a middle of the bitline contact structure hole can be improved in a deposition process for fabrication of the bitline contact structure. Voids in the polysilicon layer of the contact structure are reduced, such that quality of the contact structure is improved, and the problem of defects in the contact structure is improved. 
     After the above steps are completed, an annealing process is performed to form the contact structure. In an embodiment of the present disclosure, the annealing process includes ion implantation. A temperature of the annealing process includes 600° C. to 800° C., and time of the annealing process includes 3h to 6h. The annealing process includes an ion implantation process configured for performing ion implantation on the first polysilicon layer and/or second polysilicon layer. After the annealing process is completed, the method further includes a rapid thermal annealing process, and a temperature of the rapid thermal annealing process is higher than the temperature of the annealing process. 
     In this embodiment, the ion implantation adopts Ge. Annealing polysilicon at a high temperature for a long time may activate thermal activation energy of Si, such that diffusing atoms may transition in crystal. Because a concentration of Si in the holes is relatively low, high-concentration Si diffuses to low-concentration Si due to downhill diffusion, such that the concentration of Si tends to be uniform, thereby improving the problem of voids and holes. In the process of decreasing from the high temperature to a low temperature, the diffusion process will be frozen, such that a structure and a state of dynamic recovery or dynamic recrystallization may be maintained. In this way, the problem of voids and holes in the first polysilicon layer  211  is eliminated. 
       FIGS.  8 A- 8 C  are schematic diagrams showing an effect of the annealing process according to an embodiment of the present disclosure.  FIG.  8 A  is a schematic diagram illustrating formation of the voids  80  in the first polysilicon layer  211  in the preceding steps;  FIG.  8 B  is a schematic diagram illustrating the voids  80  exposed after a part of the second polysilicon layer  219  is removed; and  FIG.  8 C  is a schematic diagram showing disappearance of the voids  80  after the annealing process is completed. The stepped structure in the above technical solution has already reduced the voids and the holes generated during the deposition of polysilicon. If there are still a small number of voids and holes generated, the small number of voids and holes can also be eliminated in subsequent annealing process. 
     After the annealing process is completed, the method further includes a rapid thermal annealing process, and a temperature of the rapid thermal annealing process is higher than the temperature of the annealing process. Time of the rapid thermal annealing process is within 10 seconds, and activity of ion implanted elements is activated by means of a rapid annealing process at a high temperature within a short time. In this embodiment, activity of Ge is activated by means of the rapid annealing process at a high temperature within a short time. 
     According to the above technical solution, by using the stepped structure in the process of fabricating the contact structure, the problem of formation of voids and holes in a bitline contact structure hole caused by a fact that a growth rate of a top of the bitline contact structure hole is greater than a growth rate of a middle of the bitline contact structure hole can be improved in a deposition process for fabrication of the bitline contact structure. By means of the annealing process, the voids and the holes generated during growth of polysilicon are further reduced, such that the quality of the contact structure is improved, and the problem of defects in the contact structure is improved. 
     After the above steps are completed, the contact structure described in the present disclosure is obtained, and the contact structure is formed by any one of the above methods. In the above technical solution, by using the stepped structure in the process of fabricating the contact structure, the problem of excessive voids in the polysilicon layer is improved, and the voids and the holes generated during the growth of polysilicon are further reduced by means of the annealing process, such that the quality of the contact structure is improved, and the problem of defects in the contact structure is improved. 
     The above merely are embodiments of the present disclosure. It is to be pointed out that to those of ordinary skill in the art, various improvements and embellishments may be made without departing from the principles of the present disclosure, and these improvements and embellishments are also deemed to be within the scope of protection of the present disclosure.