Patent Publication Number: US-8975113-B2

Title: Method for manufacturing semiconductor device and method for growing graphene

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is a Divisional Application of prior application Ser. No. 13/756,815 filed on Feb. 1, 2013, which is a continuation application of International Application PCT/JP2010/063250 filed on Aug. 5, 2010 and designated the U.S., the entire contents of which are incorporated herein by reference. 
    
    
     FIELD 
     The present invention relates to a method for manufacturing a semiconductor device and a method for growing a graphene. 
     BACKGROUND 
     A graphene recently attracts attention as a material of a channel of a field-effect transistor. Further, the graphene also attracts attention as a material of a wiring of a semiconductor device. This is because the graphene has electron mobility higher than silicon by several digits and also has high current density resistance. Thus, a method for manufacturing a semiconductor device which includes a channel and/or a wiring where the graphene is partly used is variously studied. 
     For example, there is known a method in which a graphene is stripped off from graphite with an adhesive tape or the like and is attached to a desired position. However, it is quite difficult to manufacture a minute semiconductor device by this method. Further, such a processing requires a great deal of time. 
     Further, there is also a method in which a graphene is fabricated by subliming silicon from a silicon carbide (SiC) substrate. However, since sublimation of silicon requires application of heat of 1200° C. or more, such a method cannot be adopted for manufacturing a semiconductor device which includes a silicon oxide film and so on. 
     Further, there is also known a method in which a graphene is grown on a catalytic metal by a chemical vapor deposition method or the like. However, since the catalytic metal being a conductor and the graphene are in contact in this method, the graphene cannot be used as a channel. 
     Patent Literature 1: Japanese Laid-open Patent Publication No. 7-2508 
     Patent Literature 2: Japanese Laid-open Patent Publication No. 8-260150 
     Patent Literature 3: Japanese Laid-open Patent Publication No. 9-31757 
     Non Patent LITERATURE 1: Appl. Phys. Lett. (2000) 531 
     Non Patent LITERATURE 2: IEEE Electron Device Lett. 28, 282 (2007) 
     SUMMARY 
     In an embodiment of a method for manufacturing a semiconductor device, a catalyst film is formed over a substrate, and a graphene is grown on the catalyst film. Further, a gap is formed through which a lower surface of the catalyst film is exposed, and the catalyst film is removed through the gap. 
     In another embodiment of a method for manufacturing a semiconductor device, a catalyst film is formed over a substrate, a protective film is formed through which an upper surface of the catalyst film is exposed, and a graphene is grown on the upper surface of the catalyst film. 
     Incidentally, a graphene may be a base unit of graphite and the graphite may be composed of graphenes stacked on each other. 
     The object and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the appended claims. 
     It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed. 
    
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         FIG. 1A  is a cross-sectional view illustrating a referential example of a method for manufacturing a semiconductor device; 
         FIG. 1B , continued from  FIG. 1A , is a cross-sectional view illustrating the referential example; 
         FIG. 1C , continued from  FIG. 1B , is a cross-sectional view illustrating the referential example; 
         FIG. 1D , continued from  FIG. 1C , is a cross-sectional view illustrating the referential example; 
         FIG. 1E , continued from  FIG. 1D , is a cross-sectional view illustrating the referential example; 
         FIG. 1F , continued from  FIG. 1E , is a cross-sectional view illustrating the referential example; 
         FIG. 1G , continued from  FIG. 1F , is a cross-sectional view illustrating the referential example; 
         FIG. 2A  is a cross-sectional view illustrating a problem which occurs in the referential example; 
         FIG. 2B  is a perspective view illustrating the problem which occurs in the referential example; 
         FIG. 3A  is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a first embodiment; 
         FIG. 3B , continued from  FIG. 3A , is a cross-sectional view illustrating the method for manufacturing the semiconductor device; 
         FIG. 3C , continued from  FIG. 3B , is a cross-sectional view illustrating the method for manufacturing the semiconductor device; 
         FIG. 3D , continued from  FIG. 3C , is a cross-sectional view illustrating the method for manufacturing the semiconductor device; 
         FIG. 3E , continued from  FIG. 3D , is a cross-sectional view illustrating the method for manufacturing the semiconductor device; 
         FIG. 3F , continued from  FIG. 3E , is a cross-sectional view illustrating the method for manufacturing the semiconductor device; 
         FIG. 3G , continued from  FIG. 3F , is a cross-sectional view illustrating the method for manufacturing the semiconductor device; 
         FIG. 4A  is a perspective view illustrating the method for manufacturing the semiconductor device according to the first embodiment; 
         FIG. 4B , continued from  FIG. 4A , is a perspective view illustrating the method for manufacturing the semiconductor device; 
         FIG. 4C , continued from  FIG. 4B , is a perspective view illustrating the method for manufacturing the semiconductor device; 
         FIG. 5A  is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a second embodiment; 
         FIG. 5B , continued from  FIG. 5A , is a cross-sectional view illustrating the method for manufacturing the semiconductor device; 
         FIG. 5C , continued from  FIG. 5B , is a cross-sectional view illustrating the method for manufacturing the semiconductor device; 
         FIG. 5D , continued from  FIG. 5C , is a cross-sectional view illustrating the method for manufacturing the semiconductor device; 
         FIG. 5E , continued from  FIG. 5D , is a cross-sectional view illustrating the method for manufacturing the semiconductor device; 
         FIG. 5F , continued from  FIG. 5E , is a cross-sectional view illustrating the method for manufacturing the semiconductor device; 
         FIG. 5G , continued from  FIG. 5F , is a cross-sectional view illustrating the method for manufacturing the semiconductor device; 
         FIG. 6A  is a perspective view illustrating the method for manufacturing the semiconductor device according to the second embodiment; 
         FIG. 6B , continued from  FIG. 6A , is a perspective view illustrating the method for manufacturing the semiconductor device; 
         FIG. 7A  is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a third embodiment; 
         FIG. 7B , continued from  FIG. 7A , is a cross-sectional view illustrating the method for manufacturing the semiconductor device; 
         FIG. 7C , continued from  FIG. 7B , is a cross-sectional view illustrating the method for manufacturing the semiconductor device; 
         FIG. 7D , continued from  FIG. 7C , is a cross-sectional view illustrating the method for manufacturing the semiconductor device; 
         FIG. 7E , continued from  FIG. 7D , is a cross-sectional view illustrating the method for manufacturing the semiconductor device; 
         FIG. 7F , continued from  FIG. 7E , is a cross-sectional view illustrating the method for manufacturing the semiconductor device; 
         FIG. 7G , continued from  FIG. 7F , is a cross-sectional view illustrating the method for manufacturing the semiconductor device; 
         FIG. 8A  is a perspective view illustrating the method for manufacturing the semiconductor device according to the third embodiment; 
         FIG. 8B , continued from  FIG. 8A , is a perspective view illustrating the method for manufacturing the semiconductor device; 
         FIG. 8C , continued from  FIG. 8B , is a perspective view illustrating the method for manufacturing the semiconductor device; 
         FIG. 9A  is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a fourth embodiment; 
         FIG. 9B , continued from  FIG. 9A , is a cross-sectional view illustrating the method for manufacturing the semiconductor device; 
         FIG. 9C , continued from  FIG. 9B , is a cross-sectional view illustrating the method for manufacturing the semiconductor device; 
         FIG. 9D , continued from  FIG. 9C , is a cross-sectional view illustrating the method for manufacturing the semiconductor device; 
         FIG. 9E , continued from  FIG. 9D , is a cross-sectional view illustrating the method for manufacturing the semiconductor device; 
         FIG. 10A  is a perspective view illustrating the method for manufacturing the semiconductor device according to the fourth embodiment: 
         FIG. 10B , continued from  FIG. 10A , is a perspective view illustrating the method for manufacturing the semiconductor device; 
         FIG. 10C , continued from  FIG. 10B , is a perspective view illustrating the method for manufacturing the semiconductor device; 
         FIG. 10D , continued from  FIG. 10C , is a perspective view illustrating the method for manufacturing the semiconductor device; 
         FIG. 10E , continued from  FIG. 10D , is a perspective view illustrating the method for manufacturing the semiconductor device; 
         FIG. 11A  is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a fifth embodiment; 
         FIG. 11B , continued from  FIG. 11A , is a cross-sectional view illustrating the method for manufacturing the semiconductor device; 
         FIG. 11C , continued from  FIG. 11B , is a cross-sectional view illustrating the method for manufacturing the semiconductor device; 
         FIG. 11D , continued from  FIG. 11C , is a cross-sectional view illustrating the method for manufacturing the semiconductor device; 
         FIG. 11E , continued from  FIG. 11D , is a cross-sectional view illustrating the method for manufacturing the semiconductor device; 
         FIG. 11F , continued from  FIG. 11E , is a cross-sectional view illustrating the method for manufacturing the semiconductor device; 
         FIG. 12A  is a perspective view illustrating the method for manufacturing the semiconductor device according to the fifth embodiment; 
         FIG. 12B , continued from  FIG. 12A , is a perspective view illustrating the method for manufacturing the semiconductor device; and 
         FIG. 12C , continued from  FIG. 12B , is a perspective view illustrating the method for manufacturing the semiconductor device. 
     
    
    
     DESCRIPTION OF EMBODIMENTS 
     (Referential Example) 
     First, a referential example will be described. 
       FIG. 1A  to  FIG. 1G  are cross-sectional views illustrating the referential example of a method for manufacturing a semiconductor device, in sequence of processes. 
     First, as illustrated in  FIG. 1A , a catalyst film  2  is formed on a substrate  1 . Then, as illustrated in  FIG. 1B , a graphene  3  is formed on the catalyst film  2 . Thereafter, as illustrated in  FIG. 1C , two electrodes  4  which cover end portions of the graphene  3  are formed on a silicon oxide film  1   b . Subsequently, as illustrated in  FIG. 1D , the catalyst film  2  is removed. Since both end portions of the graphene  3  are held by the electrodes  4  from sides, the graphene  3  is suspended between the electrodes  4 . Then, as illustrated in  FIG. 1E , an insulation film  5  which covers an exposed surface of the graphene  3  is formed. Thereafter, as illustrated in  FIG. 1F , the silicon oxide film  1   c  is removed. Subsequently, a back gate electrode  6  is formed on a rear surface of a silicon layer  1   a . Subsequently, as illustrated in  FIG. 1G , a gate electrode  7  is formed on a part of the insulation film  5 , the part covering an upper surface of the graphene  3 . 
     In the semiconductor device manufactured as above, a Fermi level of the graphene  3  changes in correspondence with an electric potential of the back gate electrode  6  and an electric potential of the gate electrode  7 . Further, the graphene  3  is covered with the insulation film  5  and a path of an electric current flowing between the two electrodes  4  is the graphene  3  only. Therefore, the graphene  3  functions as a channel and the two electrodes  4  function as a source electrode and a drain electrode. Incidentally, in order to make a field effect by a gate voltage work effectively, it is preferable that the number of graphene layers included in the graphene  3  is about 1 to 10. 
     In this manufacturing method, though the graphene  3  is formed on the catalyst film  2 , the catalyst film  2  is removed and thus it is possible to make the graphene  3  function as a channel. 
     However, as illustrated in  FIG. 2A  and  FIG. 2B , the graphene  3  sometimes covers side surfaces of the catalyst film  2 . In such a case, it is difficult to remove the catalyst film  2  after the electrodes  4  are formed. When the catalyst film  2  remains below the graphene  3 , an electric current flowing between the electrodes  4  or the like is influenced. Further, formation of the insulation film  5  is also influenced. 
     Hereinafter, embodiments are concretely described with reference to the attached drawings. These embodiments enable surer removal of the catalyst film  2 . 
     (First Embodiment) 
     First, a first embodiment will be described.  FIG. 3A  to  FIG. 3G  are cross-sectional views illustrating a method for manufacturing a semiconductor device according to the first embodiment, in sequence of processes. Further,  FIG. 4A  to  FIG. 4C  are perspective views illustrating the method for manufacturing the semiconductor device according to the first embodiment, in sequence of processes. 
     In the first embodiment, first, as illustrated in  FIG. 3A , a base  11  is formed on a substrate  1 , and a catalyst film  2  is formed thereon. As the substrate  1 , one in which a silicon oxide film  1   b  is formed on a front surface of a silicon layer  1   a  and a silicon oxide film  1   c  is formed on a rear surface, for example, may be used. The silicon oxide films  1   b  and  1   c  may be formed by thermal oxidation, for example. 
     As the catalyst film  2 , an iron (Fe) film of a thickness of about 200 nm, for example, is formed by a lift-off method. That is, a resist film which has an opening at a region on which the catalyst film  2  is to be formed is formed on the silicon oxide film  1   b , and a catalyst film is deposited by a sputtering method, for example. In forming the resist film, a photolithography technique or an electronic beam lithography technique, for example, may be adopted. 
     Then, the resist film is removed together with the catalyst film thereon. Consequently, the catalyst film  2  remains on the silicon oxide film  1   b . A forming condition of the catalyst film by the sputtering method is not limited to a particular one, and an output power may be 100 W and a sputtering rate may be 1 Å/sec, for example. Further, instead of the sputtering method, an electron beam evaporation method or a molecular beam epitaxy (MBE) method may be adapted. As the catalyst film  2 , a film of a compound or an alloy containing iron such as an iron oxide (FeO and Fe 2 O 3 ), an iron chloride (Fe 2 Cl 3 ), and ferrocobalt (CoFe) may be formed. Further, as the catalyst film  2 , a film of nickel (Ni), cobalt (Co), platinum (Pt), gold (Au), or copper (Cu) may be formed, and a film of a compound or an alloy containing Ni, Co, Pt, Au, or Cu may be formed. A thickness of the catalyst film  2  is not limited to a particular one, and it is preferable that the thickness is 50 nm to 1000 nm and it is more preferable that the thickness is 100 nm to 500 nm. 
     A thickness of the base  11  is not limited to a particular one. Further, the base  11  may be formed together with the catalyst film  2  by a lift-off method, for example. That is, after the resist film is formed, a film to be the base  11  and a film to be the catalyst film  2  are formed by a sputtering method, an electron beam evaporation method, an MBE method, or the like, and the resist film may removed together with the films thereon. As a material of the base  11 , it is preferable to use one satisfying the following five conditions, for example. (a) Not having a catalyst ability for formation of a graphene  3 . (b) Having a melting point equal to or more than a temperature for forming the graphene  3 . (c) Hard to be made into carbide. (d) Removable by dissolution or decomposition. (e) Having etching selectivity with the electrode  4 . 
     Then, as illustrated in  FIG. 3B  and  FIG. 4A , the graphene  3  is formed on an upper surface of the catalyst film  2 . At this time, even if the graphene  3  is grown on a side surface of the catalyst film  2 , the graphene  3  is not grown on the side surface of the base  11 , since the base  11  does not function as a catalyst. Formation of the graphene  3  may be performed by a thermal CVD (chemical vapor deposition) method in a vacuum chamber, for example. In this case, a temperature of the substrate  1  may be set to be about 650° C., and a total pressure of mixed gas of acetylene and argon being source gas may be set to be about 1 kPa, for example. A proportion of the partial pressure of acetylene in relation to the total pressure may be about 0.001% to 10%, for example, and it is preferable that the proportion is adjusted in correspondence with a thickness, a growth condition or the like of the graphene  3  to be grown. Further, formation of the graphene  3  may be performed by a hot filament CVD method, a remote plasma CVD method, a plasma CVD method, or the like. Further, as the source gas, hydrocarbon gas such as ethylene, methane, and ethane, or alcohol such as ethanol may be used, and a small amount of oxidation gas such as water and oxygen may be added to the source gas. Further, the temperature of the substrate  1  may be set to 300° C. to 800° C., for example, and it is preferable that the temperature of the substrate  1  is adjusted in correspondence with variety and a thickness of the catalyst film  2  and variety the source gas or the like of. When an Fe film is used as the catalyst film  2  and acetylene is used as the source gas, it is preferable that the temperature of the substrate  1  is about 550° C. to 700° C. 
     Thereafter, as illustrated in  FIG. 3C  and  FIG. 4B , two electrodes  4  which cover end portions of the graphene  3  are formed on the silicon oxide film  1   b . As the electrode  4 , a stacked body of a titanium (Ti) film of a thickness of about 10 nm and an Au film of a thickness of about 200 nm positioned thereon, for example, may be formed by a lift-off method. Incidentally, in forming a resist film, a photolithography technique or an electron beam lithography technique, for example, may be adopted. 
     Subsequently, as illustrated in  FIG. 3D  and  FIG. 4C , the base  11  is removed and the catalyst film  2  is removed. As a result of removal of the base  11 , a gap through which a lower surface of the catalyst film  2  is exposed is formed. Since both end portions of the graphene  3  are held by the electrodes  4  from sides, the graphene  3  is suspended between the electrodes  4 . Incidentally, the base  11  may be removed by dissolution or decomposition with a solvent or the like corresponding to its material. Further, the catalyst film  2  may be removed by wet processing with hydrochloric acid, aqueous iron chloride solution, fluorine, or the like. When an Fe film of a thickness of about 10 nm to 500 nm is formed as the catalyst film  2 , removal of the catalyst  2  may be completed in about 30 minutes with hydrochloric acid of a density of 9 vol %. The base  11  and the catalyst film  2  may be removed collectively depending on materials of the base  11  and the catalyst  2 . In the present embodiment, since a gap exists between the graphene  3  and the substrate  1 , the whole of the base  11  and the catalyst  2  can be removed easily. 
     Then, as illustrated in  FIG. 3E , an insulation film  5  which covers an exposed surface of the graphene  3  is formed. When a hafnium oxide or an aluminum oxide is used as a material of the insulation film  5 , the insulation film  5  may be deposited in a manner to cover the graphene  3  by an atomic layer deposition method (ALD method), for example. When the hafnium oxide is used as the material of the insulation film  5 , the insulation film  5  may be formed at a temperature of 250° C. with tetrakisdimethylamino hafnium (TDMAH) as a raw material, for example. When the aluminum oxide is used as the material of the insulation film  5 , the insulation film  5  may be formed at a temperature of 300° C. with trimethylaluminum as a raw material. When a silicon oxide is used as the material of the insulation film  5 , the insulation film  5  may be formed by applying SOG (spin on glass) solution by a spin coat method, and annealing at about 500° C. in a nitride atmosphere, for example. A titanium oxide or the like may be also used as the material of the insulation film  5 . 
     Thereafter, as illustrated in  FIG. 3F , the silicon oxide film  1   c  is removed. The silicon oxide film  1   c  may be removed with buffered hydrofluoric acid or the like, with an upper part of the silicon layer  1   a  being protected by a resist film (for example, “TSMR-V50” of TOKYO OHKA KOGYO CO., LTD.), for example. A processing time thereof may be about 5 minutes. Subsequently, a back gate electrode  6  is formed on a rear surface of the silicon layer  1   a . As the back gate electrode  6 , a stacked body of a Ti film of a thickness of about 10 nm and an Au film of a thickness of about 100 nm positioned thereon, for example, is formed by an electron beam deposition method. 
     Then, as illustrated in  FIG. 3G , a gate electrode  7  is formed on a part of the insulation film  5 , the part covering an upper surface of the graphene  3 . The part positioned between the gate electrode  7  and the graphene  3  of the insulation film  5  functions as a gate insulation film. As the gate electrode  7 , a stacked body of a Ti film of a thickness of about 10 nm and an Au film of a thickness of about 100 nm positioned thereon, for example, may be formed by a lift-off method. Incidentally, in forming a resist film, a photolithography technique or an electron beam lithography technique, for example, can be adopted. Deposition of the Ti film and the Au film may be performed by an electron beam deposition method, for example. 
     According to the first embodiment, since the base  11 , on a side surface of which the graphene  3  is not grown, is formed between the catalyst film  2  and the substrate  1 , even if the graphene  3  covers the side surface of the catalyst film  2 , the catalyst film  2  can be easily removed without processing of the graphene  3  or the like. Therefore, the graphene  3  can be surely made to function as a channel. 
     Here, a concrete example of the material of the base  11  will be described. As the material of the base  11 , metals and compounds (oxides, nitrides, carbides, and the like) may be cited. As for the metal, it is preferable to use a transition metal with a high melting point, and Ti, Cr, W, Hf, Nb, and the like are favorable, for example. As for the compound, ZnO, MgO, Al 2 O 3 , Si 3 N 4 , and the like may be cited, for example. Further, regarding the above-described conditions (d) and (e), it is preferable to consider a material of the electrode  4 . For example, if the material of the electrode  4  is Ti, it is preferable to select a material which can be removed without usage of hydrofluoric acid, nitric hydrofluoric acid, or heated hydrochloric acid, since Ti is soluble to the solutions. Mo, which is soluble to ammonia, Al 2 O 3 , which is soluble to NaOH, ZnO, which is soluble to almost all the acids and alkaline solutions, and so on may be selected, for example. 
     Further, if the base  11  is removed by wet etching, it is preferable to use a solvent, considering an ionization tendency. Further, if the base  11  and the catalyst film  2  are removed by wet etching, it is preferable to use a solvent which does not affect the silicon oxide film  1   b . That is, since the silicon oxide film  1   b  is soluble to the hydrofluoric acid, it is preferable to use a solvent other than the hydrofluoric acid. Removal of the base  11  and the catalyst film  2  may be performed by dry etching. 
     Incidentally, regarding the above-described condition (c), if the base  11  is easy to be made into carbide, the base  11  may be made into carbide during forming the graphene  3 , making dissolution and removal of the base  11  difficult. 
     Incidentally, a hafnium oxide film, an aluminum oxide film or the like may be used instead of the silicon oxide films  1   a ,  1   b.    
     (Second Embodiment) 
     Next, a second embodiment will be described.  FIG. 5A  to  FIG. 5G  are cross-sectional views illustrating a method for manufacturing a semiconductor device according to the second embodiment, in sequence of processes. Further,  FIG. 6A  to  FIG. 6B  are perspective views illustrating the method for manufacturing the semiconductor device according to the second embodiment, in sequence of processes. 
     In the second embodiment, first, as illustrated in  FIG. 5A , similarly to in the referential example, a catalyst film  2  is formed on a substrate  1 . Then, a graphene  3  is formed on an upper surface of the catalyst film  2 . At this time, the graphene  3  is sometimes grown on a side surface of the catalyst film  2 . 
     Thereafter, as illustrated in  FIG. 5B  and  FIG. 6A , etching of a silicon oxide film  1   b  is performed so that a recessed portion  21  extending beneath an outer portion of the catalyst film  2  is formed in the silicon oxide film  1   b . At this time, a protruding portion  22  is left in the silicon oxide film  1   b  under the center portion of the catalyst film  2 , and contact between the upper surface of the protruding portion  22  and the lower surface of the catalyst film  2  is kept. Consequently, a gap is generated between the graphene  3  and the substrate  1 , and further, partially, a gap is generated between the catalyst film  2  and the substrate  1 . Etching of the silicon oxide film  1   b  may be performed with gas or solution of hydrogen fluoride (HF), for example. 
     Subsequently, as illustrated in  FIG. 5C , two electrodes  4  which cover end portions of the graphene  3  are formed on the silicon oxide film  1   b . Also after the electrodes  4  are formed, the gap exists between the graphene  3  and the substrate  1 , and the gap partially exists between the catalyst film  2  and the substrate  1 . 
     Then, as illustrated in  FIG. 5D  and  FIG. 6B , the catalyst film  2  is removed. Since both end portions of the graphene  3  are held by the electrodes  4  from sides, the graphene  3  is suspended between the electrodes  4 . 
     Thereafter, as illustrated in  FIG. 5E , an insulation film  5  which covers an exposed surface of the graphene  3  is formed. Subsequently, as illustrated in  FIG. 5F , a silicon oxide film  1   c  is removed. Then, a back gate electrode  6  is formed on a rear surface of a silicon layer  1   a . Then, as illustrated in  FIG. 5G , a gate electrode  7  is formed on a part of the insulation film  5 , the part covering an upper surface of the graphene  3 . 
     According to the second embodiment, since the recessed portion  21  is formed by etching of the silicon oxide film  1   b , even if the graphene  3  covers the side surface of the catalyst film  2 , the catalyst film  2  can be easily removed without processing of the graphene  3  or the like. Therefore, the graphene  3  can be surely made to function as a channel. 
     Incidentally, a hafnium oxide film, an aluminum oxide film or the like may be used instead of the silicon oxide films  1   a ,  1   b . When the hafnium oxide film is used, etching thereof may be performed with etching solution of hydrofluoric acid system, for example. When the aluminum oxide film is used, etching thereof may be performed with NaOH or hydrofluoric acid, for example. 
     (Third Embodiment) 
     Next, a third embodiment will be described.  FIG. 7A  to  FIG. 7G  are cross-sectional views illustrating a method for manufacturing a semiconductor device according to the third embodiment, in sequence of processes. Further,  FIG. 8A  to  FIG. 8C  are perspective views illustrating the method for manufacturing the semiconductor device according to the third embodiment, in sequence of processes. 
     In the third embodiment, first, as illustrated in  FIG. 7A , similarly to in the referential example, a catalyst film  2  is formed on a substrate  1 . Then, a protective film  31  which covers the catalyst film  2  is formed on the substrate  1 . As a material of the protective film  31 , it is preferable to use one satisfying the following five conditions, for example. (f) Not having a catalyst ability for formation of a graphene  3 . (g) Having a melting point equal to or more than a temperature for forming the graphene  3 . (h) Hard to be made into carbide. (i) Removable by dissolution or decomposition. (j) Having etching selectivity with the catalyst film  2 . 
     Thereafter, as illustrated in  FIG. 7B  and  FIG. 8A , the protective film  31  is polished until an upper surface of the catalyst film  2  is exposed. It may be said that the protective film  31  before the polishing is a material film for the protective film  31 . 
     Subsequently, as illustrated in  FIG. 7C  and  FIG. 8B , the graphene  3  is formed on the upper surface of the catalyst film  2 . At this time, since a side surface of the catalyst film  2  is covered with the protective film  31 , the graphene  3  is not grown on the side surface of the catalyst film  2 . 
     Then, as illustrated in  FIG. 7D  and  FIG. 8C , the protective film  31  is removed. Thereafter, as illustrated in  FIG. 7E , two electrodes  4  which cover end portions of the graphene  3  are formed on a silicon oxide film  1   b . Subsequently, as illustrated in  FIG. 7F , the catalyst film  2  is removed. Since both end portions of the graphene  3  are held by the electrodes  4  from sides, the graphene  3  is suspended between the electrodes  4 . Then, as illustrated in  FIG. 7G , an insulation film  5  which covers an exposed surface of the graphene  3  is formed. Thereafter, a silicone oxide film  1   c  is removed. Subsequently, a back gate electrode  6  is formed on a rear surface of a silicon layer  1   a . Then, a gate electrode  7  is formed on a part of the insulation film  5 , the part covering an upper surface of the graphene  3 . 
     According to the third embodiment, since the side surface of the catalyst film  2  is covered with the protective film  31  during forming the graphene  3 , the graphene  3  does not come into contact with the substrate  1 . Thus, the catalyst film  2  can be removed easily. Therefore, the graphene  3  can be surely made to function as a channel. Further, compared with the first embodiment and the second embodiment, a property of the graphene  3  is easy to be stabilized. This is because control of a thickness or the like of the graphene grown on the upper surface of the catalyst  2  is easier than that of the graphene grown on a side surface. 
     Here, a concrete example of the material of the protective film  31  will be described. As the material of the protective film  31 , metals and compounds (oxides, nitrides, carbides, and the like) may be cited. As for the metal, it is preferable to use a transition metal with a high melting point, and Ti, Cr, W, Hf, Nb, and the like are favorable, for example. As for the compound, ZnO, MgO, Al 2 O 3 , Si 3 N 4 , and the like may be cited, for example. That is, the similar material to that of the base  11  may be used. Further, regarding the above-described conditions (i) and (j), it is preferable to consider a material of the catalyst film  2 , too. The protective film  31  may be formed by a sputtering method, an electron beam evaporation method, a molecular beam epitaxy method, an ALD method, or the like, for example. Further, when a silicon oxide is used as the material of the protective film  31 , the protective film  31  may be formed by applying SOG solution by a spin coat method, and annealing, for example. 
     Further, in the third embodiment, though the protective film  31  is formed so as to cover the upper surface and the side surface of the catalyst film  2 , the protective film  31  may be formed so as to expose the upper surface of the catalyst film  2 . In other words, the protective film  31  may be thinner than the catalyst film  2 . In this case, the catalyst film  2  may be polished after forming the protective film  31  to make the thickness of the catalyst film  2  similar to the thickness of the protective film  31 , for example. Further, if a part of the side surface of the catalyst film  2  is covered with the protective film  31  during forming the graphene  3 , an effect may be obtained that the catalyst film  2  can be removed easily. 
     (Fourth Embodiment) 
     Next, a fourth embodiment will be described.  FIG. 9A  to  FIG. 9E  are cross-sectional views illustrating a method for manufacturing a semiconductor device according to the fourth embodiment, in sequence of processes. Further, FIG.  10 A to  FIG. 10E  are perspective views illustrating the method for manufacturing the semiconductor device according to the fourth embodiment, in sequence of processes. 
     In the fourth embodiment, first, as illustrated in  FIG. 9A  and  FIG. 10A , a catalyst film  2  and a protective film  41  are formed in this sequence on a substrate  1 . The catalyst film  2  and the protective film  41  may be formed by a lift-off method using a single resist film, for example. A material of the protective film  41  (sacrifice film) will be described later. 
     Then, as illustrated in  FIG. 9B  and  FIG. 10B , a protective film  42  is formed on the protective film  41  and a silicon oxide film  1   b  so that at least a part of a side surface of the protective film  41  is exposed. At this time, a height d 2  of a front surface of the protective film  42  on the silicon oxide film  1   b  in reference to the interface between the catalyst film  2  and the protective film  41  is made smaller than a height d 1  of a front surface of the protective film  41  in reference to the interface between the catalyst film  2  and the protective film  41 . As the material of the protective film  41 , it is preferable to use one satisfying the following three conditions, for example. (k) Removable by dissolution or decomposition. (l) Having etching selectivity with the protective film  42 . (m) Having etching selectivity with the catalyst film  2 . Further, as a material of the protective film  42 , it is preferable to use one satisfying the following five conditions, for example. (n) Not having a catalyst ability for formation of a graphene  3 . (o) Having a melting point equal to or more than a temperature for forming the graphene  3 . (p) Hard to be made into carbide. (q) Removable by dissolution or decomposition. (r) Having etching selectivity with the catalyst film  2 . 
     Thereafter, as illustrated in  FIG. 9C  and  FIG. 10C , the protective film  41  is removed together with the protective film  42  positioned thereon, while the protective film  42  on the silicon oxide film  1   b  is made to remain. Consequently, an opening  43  through which the catalyst film  2  is exposed is formed in the remaining protective film  42 . The whole of the protective film  42  before removing the protective film  41  (sacrifice film) may be a material film for the protective film  42 . 
     Subsequently, as illustrated in  FIG. 9D  and  FIG. 10D , the graphene  3  is formed on the upper surface of the catalyst film  2  exposed through the opening  43 . At this time, since the side surface of the catalyst film  2  is covered with the protective film  42 , the graphene  3  is not grown on the side surface of the catalyst film  2 . 
     Then, as illustrated in  FIG. 9E  and  FIG. 10E , the protective film  42  is removed. Consequently, a structure similar to that after removing the protective film  31  in the third embodiment may be obtained. Thereafter, similarly to in the third embodiment, processings from forming the electrodes  4  to forming the gate electrode  7  are performed. 
     According to the fourth embodiment, since the side surface of the catalyst film  2  is covered with the protective film  42  during forming the graphene  3 , the graphene  3  does not come into contact with the substrate  1 . Thus, the catalyst film  2  can be removed easily. Therefore, the graphene  3  can be surely made to function as a channel. Further, similarly to in the third embodiment, a property of the graphene  3  is easy to be stabilized compared with the first embodiment and the second embodiment. 
     Incidentally, as the materials of the protective films  41 ,  42 , metals and compounds (oxides, nitrides, carbides, etc.) may be cited. For example, ZnO or MgO, which is soluble to hydrochloric acid, may be used as the material of the protective film  41  and SiO 2 , which is insoluble to hydrochloric acid and soluble to hydrofluoric acid, may be used as the material of the protective film  42 . The protective films  41  and  42  may be formed by a sputtering method, an electron beam deposition method, a molecular beam epitaxy method, an ALD method, or the like, for example. Further, photo resist solution may be also used as the protective film  41 . 
     (Fifth Embodiment) 
     Next, a fifth embodiment will be described. FIG.  11 A to  FIG. 11F  are cross-sectional views illustrating a method for manufacturing a semiconductor device according to the fifth embodiment, in sequence of processes. Further,  FIG. 12A  to  FIG. 12C  are perspective views illustrating the method for manufacturing the semiconductor device according to the fifth embodiment, in sequence of processes. 
     In the fifth embodiment, first, as illustrated in  FIG. 11A , a catalyst film  2  and a protective film  51  are formed in this sequence on a substrate  1 . The catalyst film  2  and the protective film  51  may be formed by a lift-off method using a single resist film, for example. A material of the protective film  51  (sacrifice film) will be described later. 
     Then, as illustrated in  FIG. 11B , while the protective film  51  is made to remain, the catalyst film  2  is etched so that a side surface of the catalyst film  2  are made to recede toward an inner side of a side surface of the protective film  51 . That is, the catalyst film  2  is reduced in plan view. Consequently, the protective film  51  becomes something like an eave to the catalyst film  2 . 
     Thereafter, as illustrated in  FIG. 11C , a protective film  52  is formed on an upper surface of the protective film  51  and on a side surface of the catalyst film  2  so that at least a part of a side surface of the protective film  51  is exposed. The protective film  52  may be formed by deposition from a direction inclined from a direction perpendicular to a front surface of the substrate  1 , for example. As a material of the protective film  51 , it is preferable to use one satisfying the following three conditions, for example. (s) Removable by dissolution or decomposition. (t) Having etching selectivity with the protective film  52 . (u) Having an etching selectivity with the catalyst film  2 . Further, as a material of the protective film  52 , it is possible to use one satisfying the following five conditions, for example. (v) Not having a catalyst ability for formation of a graphene  3 . (w) Having a melting point equal to or more than a temperature for forming the graphene  3 . (x) Hard to be made into carbide. (y) Removable by dissolution or decomposition. (z) Having etching selectivity with the catalyst film  2 . 
     Subsequently, as illustrated in  FIG. 11D  and  FIG. 12A , the protective film  51  is removed together with the protective film  52  positioned thereon, while the protective film  52  on the side surface of the catalyst film  2  is made to remain. The whole of the protective film  52  before removing the protective film  51  (sacrifice film) may be said to be a material film for the protective film  52 . 
     Then, as illustrated in  FIG. 11E  and  FIG. 12B , the graphene  3  is formed on an upper surface of the catalyst film  2 . At this time, since the side surface of the catalyst film  2  is covered with the protective film  52 , the graphene  3  is not grown on the side surface of the catalyst film  2 . 
     Thereafter, as illustrated in  FIG. 11F  and  FIG. 12C , the protective film  52  is removed. Consequently, a structure similar to that after removing the protective film  31  in the third embodiment may be obtained. Thereafter, similarly to in the third embodiment, processings from forming the electrodes  4  to forming the gate electrode  7  are performed. 
     According to the fifth embodiment, since the side surface of the catalyst film  2  is covered with the protective film  52  during forming the graphene  3 , the graphene  3  does not come into contact with the substrate  1 . Thus, the catalyst film  2  can be removed easily. Therefore, the graphene  3  can be surely made to function as a channel. Further, similarly to in the third embodiment, a property of the graphene  3  is easy to be stabilized compared with the first embodiment and the second embodiment. 
     Incidentally, as the materials of the protective films  51 ,  52 , metals and compounds (oxides, nitrides, carbides, and the like) may be cited. For example, when Fe is used as the material of the catalyst film  2 , photo resist solution which is soluble to organic solvent such as acetone may be used as the material of the protective film  51 , and ZnO, which is soluble to NaOH aqueous solution, may be used as the material of the protective film  52 . The protective films  51  and  52  may be formed by a sputtering method, an electron beam deposition method, a molecular beam epitaxy method, an ALD method, or the like, for example. 
     Further, usage of the semiconductor device is not limited to particular one, and the semiconductor device may be used as a high-power amplifier for a wireless base station, a high-power amplifier for a mobile phone base station, a semiconductor element for a server, a semiconductor element for a personal computer, an on-vehicle integral circuit (IC), and a transistor for driving a motor of an electric vehicle, for example. 
     The present invention may be suitable to an industry related to a semiconductor device which includes graphene and a method for manufacturing the same. 
     All examples and conditional language provided herein are intended for the pedagogical purposes of aiding the reader in understanding the invention and the concepts contributed by the inventor to further the art, and are not to be construed as limitations to such specifically recited examples and conditions, nor does the organization of such examples in the specification relate to a showing of the superiority and inferiority of the invention. Although one or more embodiments of the present invention have been described in detail, it should be understood that the various changes, substitutions, and alterations could be made hereto without departing from the spirit and scope of the invention.