Patent Publication Number: US-2022224217-A1

Title: Adaptive gate drive for a power switch transistor in a switching power converter

Description:
TECHNICAL FIELD 
     This application relates to switching power converters, and more particularly to a switching power converter with an adaptive gate drive for a power switch transistor. 
     BACKGROUND 
     During operation of a flyback converter, a primary-side controller controls the switching of a power switch metal-oxide-semiconductor field-effect transistor (MOSFET) connected to a primary winding of a transformer. The power switch transistor is typically an NMOS transistor having a drain connected to the primary winding and a source coupled to ground. Prior to the power switch being switched on, the drain is charged to (or above) the input voltage to the primary winding. The input voltage is rectified from the AC mains and can thus be more than 100 V depending upon the AC mains cycling. With the power switch transistor being fully switched on, the drain is grounded. The drain of the power switch transistor is thus subjected to a relatively high rate of voltage change (dV/dt) during the power switch transistor turn on. This rapid change in the drain voltage of the power switch transistor may lead to an undesirable level of electromagnetic interference (EMI). 
     To reduce the EMI from the power switch cycling, it is conventional to drive the power switch transistor on through a relatively complicated drive circuit that includes a high-voltage Miller capacitor, a bipolar junction transistor, a diode, and external resistors. These drive circuit components increase cost and occupy circuit board space. To avoid this cost and complication, it is known to drive the power switch transistor with a simplified gate driver having a turn-on period or procedure divided into two sections having different drive resistances. During a first section of the turn-on period, the gate driver drives the gate of the power switch transistor through a relatively-high drive resistance to reduce the dV/dt rate of change of the drain-to-source voltage across the power switch transistor. Once the drain voltage has dropped sufficiently, the gate driver then drives the gate of the power switch transistor through a relatively-low drive resistance to quickly increase the gate voltage and fully switch on the power switch transistor. 
     A timing between the high-resistance drive and the low-resistance drive of the power switch transistor gate occurs according to an output signal from a comparator. The comparator may compare the drain-to-source voltage or the gate-to-source voltage of the power switch transistor to threshold voltage. An example gate driver  100  is shown in  FIG. 1 . Gate driver  100  charges and discharges the gate of a power switch transistor M 1  connected to a primary winding L 1  of a transformer to control the cycling of the power switch transistor M 1 . A gate driver control circuit  105  adjusts the drive resistance used to drive the gate voltage of power switch transistor M 1  responsive to a comparator  110  that compares the gate voltage of the power switch transistor M 1  to a threshold voltage. The gate driver control circuit  105  begins the on-time period for the power switch transistor M 1  by charging its gate through a relatively-high drive impedance. The gate voltage of the power switch transistor eventually rises above the threshold voltage to comparator  110  so that an output signal from comparator  110  is asserted. As used herein, a binary signal is deemed to be “asserted” when the signal is logically true, regardless of whether the logical convention is logic high or logic low. In response to the assertion of the comparator output signal, gate driver control circuit  105  charges the gate of the power switch transistor through a relatively-low drive impedance. This low drive impedance is used for the remainder of the on-time period for the power switch transistor. 
     Although gate driver  100  avoids the complexities and cost of the Miller capacitor approach, the use of such a gate driver results in an undesirable delay or duration for the turn-on portion of the power switch transistor on-time period. This long turn-on time reduces the effective duty cycle, which lowers efficiency under heavy loads. In addition, the transition time between the high-impedance drive portion and the low-impedance drive portion is not optimal, which again undesirably lengthens the turn-on time. 
     Accordingly, there is a need in the art for switching power converter drive circuits with reduced turn-on times for the power switch transistor yet still providing a sufficiently-low level of EMI. 
     SUMMARY 
     In accordance with a first aspect of the disclosure, a drive control circuit for a power switch transistor in a switching power converter is provided that includes: a gate drive circuit configured to drive a gate voltage of the power switch transistor through a variable gate drive resistance; and an adaptive drive control circuit configured to command the gate drive circuit to use a first gate drive resistance during a first portion of a power switch transistor on-time period, a second gate drive resistance during a second portion of the power switch transistor on-time period, and a third gate drive resistance during a third portion of the power switch transistor on-time period. 
     In accordance with a second aspect of the disclosure, a method of adapting the gate drive resistance for a power switch transistor in a switching power converter is provided that includes: during an initial portion of a power switch transistor on-time period while a gate voltage of the power switch transistor is less than a first threshold voltage, charging a gate of the power switch transistor through a first resistance; initiating a timing of a maximum delay period responsive to the gate voltage of the power switch transistor being greater than the first threshold voltage; during a second portion of the power switch transistor on-time period prior to an expiration of the maximum delay period, charging the gate of the power switch transistor through a second resistance. 
     In accordance with a third aspect of the disclosure, a switching power converter is provided that includes: an inductor; a power switch transistor coupled to the inductor; and a gate drive control circuit configured to: charge a gate of the power switch transistor through a first resistance during an first portion of an on-time period, charge the gate of the power switch transistor through a second resistance during a second portion of the on-time period, and charge the gate of the power switch transistor through a third resistance during a third portion of the on-time period. 
     These and other aspects of the invention will become more fully understood upon a review of the detailed description, which follows. Other aspects, features, and embodiments will become apparent to those of ordinary skill in the art, upon reviewing the following description of specific, exemplary embodiments in conjunction with the accompanying figures. While features may be discussed relative to certain embodiments and figures below, all embodiments can include one or more of the advantageous features discussed herein. In other words, while one or more embodiments may be discussed as having certain advantageous features, one or more of such features may also be used in accordance with the various embodiments discussed herein. In similar fashion, while exemplary embodiments may be discussed below as device, system, or method embodiments it should be understood that such exemplary embodiments can be implemented in various devices, systems, and methods. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  illustrates a conventional drive circuit for a power switch transistor in a switching power converter. 
         FIG. 2  illustrates a flyback converter with an improved drive circuit in accordance with an aspect of the disclosure. 
         FIG. 3  illustrates an improved drive circuit in accordance with an aspect of the disclosure. 
         FIG. 4  illustrates additional details for the improved drive circuit of  FIG. 3  in accordance with an aspect of the disclosure. 
         FIG. 5  illustrates some operating waveforms for the improved drive circuit of  FIG. 4 . 
     
    
    
     Embodiments of the present disclosure and their advantages are best understood by referring to the detailed description that follows. It should be appreciated that like reference numerals are used to identify like elements illustrated in one or more of the figures. 
     DETAILED DESCRIPTION 
     An improved drive control circuit is provided for a switching power converter. The following discussion will be directed to flyback converter implementations, but it will be appreciated that the improved drive control circuit disclosed herein may be advantageously employed for the driving of any suitable power switch transistor such as in a buck or a boost converter. An example flyback converter  200  is shown in  FIG. 2  that includes an improved drive control circuit  205 . Flyback converter  200  includes a transformer T having a primary winding W 1  and a secondary winding W 2 . During operation, drive control circuit  205  charges the gate of a power switch transistor M 1  connected to the primary winding W 1  to switch on the power switch transistor M 1  for an on-time period. The primary winding W 1  also connects to an input voltage rail carrying a rectified input voltage (V_IN). When the power switch transistor M 1  is cycled on, a primary winding current begins to flow through the primary winding W 1  and the power switch transistor M 1  into ground. Once a desired peak winding current has been reached, a primary-side controller (not illustrated) may then control the drive control circuit  205  to cycle off the power switch transistor M 1 . As used herein, “connected” refers to a direct electrical connection such as through a conducting lead whereas “coupled” refers to an electrical connection in which the connection may be through an intervening element such as a resistor or a diode. 
     A secondary-side controller U 2  controls a synchronous rectifier (SR) switch transistor that couples between a return output terminal and the secondary winding W 2 . This SR control is in response to monitoring a drain-to-source voltage (VDS) across the SR switch transistor. Based upon the drain-to-source voltage VDS, the SR controller detects whether the power switch transistor M 1  has cycled off so that the SR switch transistor may be switched on to allow the secondary winding current to flow and charge an output voltage Vout that is supported by an output capacitor C 1 . 
     Gate drive control circuit  205  is shown in more detail in  FIG. 3 . For illustration clarity, the corresponding flyback converter is represented by just the primary winding L 1 , power switch transistor M 1 , and an input capacitor C 1  that supports the input voltage. A modulation control circuit  300  controls gate drive control circuit  205  such as with a pulse width modulation (PWM) control signal to produce the desired on-time period for power switch transistor M 1 . Modulation control circuit  300  may be part of a primary-side controller or part of a secondary-side controller. If modulation control circuit  300  is located on the secondary-side of the transformer, the PWM control signal would be transmitted across a ground-isolating channel such as an opto-isolator. Regardless of where the modulation control circuit  300  is located, it generates the PWM control signal responsive to a feedback on the various operating signals such as the output voltage Vout or the input voltage Vin. 
     Gate drive control circuit  205  includes an adaptive drive control circuit  305 , a gate drive circuit  315 , and a gate voltage monitor  310 . Gate voltage monitor  310  includes at least two comparators that compare the gate voltage (Vgate) of the power switch transistor to respective threshold voltages. In particular, one comparator uses a relatively low first threshold voltage Vth 1  so as to assert a comparator output signal Vcomp 1  when the gate voltage has risen to equal Vth 1 . Similarly, a second comparator uses a relatively-larger second threshold voltage Vth 2  so as to assert a comparator output signal Vcomp 2  when the gate voltage has risen to equal Vth 2 . There are thus at least three periods during the power switch transistor turn-on time delay and the remaining on-time period as will be explained further herein. A first period T 1  extends from the start of the turn-on time delay until the gate voltage has risen to equal Vth 1 . A second period T 2  extends from the end of period T 1  until the gate voltage has risen to equal Vth 2  (Vth 2  being greater than Vth 1 ). A final period T 3  extends from when the gate voltage has risen above Vth 2  until the end of the on-time period. In alternative embodiments, the transition between periods T 2  and T 3  may be responsive to the expiration of a timer. The timer may begin timing at the initiation of period T 2 . Alternatively, the transition between periods T 2  and T 3  may be responsive to whatever event happens first: either the gate voltage rising above Vth 2  or the expiration of the timer. 
     Gate drive circuit  315  drives the gate voltage with a drive impedance that varies depending upon which of the periods T 1 , T 2 , and T 3  is active. During period T 1 , gate drive circuit  315  charges the gate through a relatively-low drive impedance. But during period T 2 , gate drive circuit  315  charges the gate through a relatively-high drive impedance. Finally, during period T 3 , gate drive circuit  315  charges the gate through another relatively-low drive impedance. In some embodiments, the drive impedance during period T 1  may be greater than the drive impedance during period T 3 . However, the drive impedance used during periods T 1  and T 2  may be the same in alternative embodiments. Regardless of whether the drive impedance during period T 3  is less than or equal to that used during period T 1 , the drive impedance during period T 2  may be greater than that used for either of periods T 1  and T 3 . But note that it would be undesirable to increase the drive impedance during a critical conduction mode of operation in which a relatively-large amount of power must be delivered to the load. The drive impedance in period T 2  may thus be the same or even lower than that used during period T 1  in such a mode of operation. 
     Based upon the duration of the periods T 1  and T 2 , adaptive drive control circuit  305  adapts at least the threshold voltage Vth 1  so that the turn-on period extending across periods T 1  and T 2  is neither too long nor too short. If the turn-on period is too long, the effective duty cycle suffers such that a power supply to a heavy load may be insufficient. Conversely, if the turn-on period is too short, the dV/dt voltage rate of change at the drain of the power switch transistor M 1  is too large such that an excessive EMI is produced. In some embodiments, adaptive drive control circuit  305  may adjust the threshold voltages Vth 1  and Vth 2  based upon a ratio of T 1 /T 2  and T 2 /T 3 . For example, adaptive drive control circuit  305  may include a counter that is clocked by a clock signal to provide a count in each period T 1  and T 2  that represents a duration of the period. The ratio T 1 /T 2  may thus be the ratio of the count determined in period T 1  to the count determined in period T 2 . Similarly, the ratio T 2 /T 3  may be the ratio of the count determined in period T 2  to a count determined in period T 3 . In addition, the threshold voltages may also be adapted responsive to a ratio T 1 /T 3 . 
     Gate drive control circuit  205  is shown in more detail in  FIG. 4 . Gate drive circuit  315  includes a plurality of n PMOS transistors ranging from a first PMOS transistor P 1  to an nth transistor Pn, n being a positive plural integer. Each PMOS transistor has its source connected to a power supply voltage rail and a drain connected through a corresponding resistance to the gate of the power switch transistor M 1 . For example, transistor P 1  has its drain couple to the power switch transistor gate through a resistance Z 1 , transistor P 2  has its drain couple to the power switch transistor gate through a resistance Z 2 , and so on such that the nth transistor Pn has its drain couple through a resistance Zn to the power switch transistor gate. In some embodiments, the resistors may be conceptual in that they would be provided by the on-resistance of the respective transistor. Alternatively, the resistors may be external to the transistors. 
     To produce a low drive impedance, adaptive drive control circuit  305  may switch on each (or most) of the transistors P 1  through Pn. The drive impedance increases as fewer and fewer of the transistors P 1  through Pn are switched on. To control the drive impedance depending upon whether period T 1 , T 2 , or T 3  is active, adaptive drive control circuit  305  may include a logic circuit  400 . Logic circuit  400  may comprise a state machine, a microcontroller, or a microprocessor. During operation, logic circuit  400  responds to the PWM control signal to then switch on the power switch transistor M 1  for the desired on-time period. For a large pulse width, the on-time period is relatively long whereas it is shorter for smaller pulse widths. The beginning of the on-time period may be coordinated by a clock signal from a clock  405 . Logic circuit  400  controls which of the transistors P 1  through Pn is switched on through a corresponding gate drive signal g 1  through gn. If a gate drive signal is charged to a power supply voltage, the corresponding transistor is off. When logic circuit  400  grounds a drive signal, the corresponding transistor is switched on. In alternative embodiments, current sources may be used to control the impedance drive level during the on-time period for the power switch transistor M 1 . 
     To detect the end of period T 1 , gate voltage monitor  310  includes a first comparator C 1  that compares the power switch transistor gate voltage to the first threshold voltage Vth 1 . When the gate voltage has risen to equal Vth 1 , comparator C 1  asserts an output signal Vcomp 1 . Logic circuit  400  may also be configured to form a timer such as timed by the clock signal from clock source  405  to time a maximum duration period. An expiration of the maximum duration period triggers an end to period T 2  so that once the maximum duration period is timed-out by this timing, logic circuit  400  commands for a transition from period T 2  to period T 3 . Alternatively (or in conjunction with the timer), a second comparator C 2  compares the power switch transistor gate voltage to the second threshold voltage Vth 2  to determine an end to period T 2 . In some embodiments, the end of period T 2  may be determined by the expiration of the maximum duration period set by the timer or by the gate voltage exceeding Vth 2 , whichever event occurs first. When the gate voltage has risen to equal Vth 2 , comparator C 2  asserts an output signal Vcomp 2 . To add additional characterization of the gate voltage waveform, gate voltage monitor  310  may include additional comparators. For example, gate voltage monitor  310  may include a plurality of n comparators ranging from comparator C 1  to an nth comparator Cn producing an nth comparator output signal Vcompn. Each comparator compares the gate voltage to its own threshold voltage to then assert its own comparator output signal. In this fashion, logic circuit  400  may more finely sample the gate voltage waveform for the power switch transistor M 1  to then adjust the durations of the T 1  and T 2  periods or portions accordingly. To make the adjustment, logic circuit  400  may include a counter that counts responsive to a clock signal such as from clock  405 . The count in each period is thus representative of the duration of each period. Logic circuit  400  may then calculate a ratio T 1 /T 2 , T 2 /T 3 , and/or T 1 /T 3  as discussed previously. Based upon the durations of the periods T 1 , T 2 , and Te 4 , logic circuit  400  commands an adjustable voltage reference  410  to adjust the threshold voltages to the comparators. 
     As known in the MOSFET arts, a Miller plateau period occurs after the gate-to-source voltage for the power switch transistor M 1  has reached the transistor threshold voltage. The drain voltage then begins to fall due to the channel conduction, which tends to pull the gate voltage lower due to the gate-to-drain parasitic capacitance of the power switch transistor M 1 . The gate-to-drain parasitic capacitance is highly non-linear such that it is relatively small as the drain voltage begins to fall and increases in magnitude as the drain voltage approaches ground. The net result is that the gate voltage is relatively constant during the Miller plateau period, which ends once the gate-to-drain capacitance is discharged. However, due to the non-linearity of the gate-to-drain parasitic capacitance, the drain voltage may be substantially discharged well before the end of the Miller plateau period. It is thus beneficial to transition from period T 2  to period T 3  before the end of the Miller plateau period. The use of a timer to trigger the end of the period T 2  is thus advantageous in increasing the switching speed. 
     Consider the advantages of the improved gate drive control disclosed herein as compared to the conventional use of a comparison of the gate voltage to a threshold voltage to trigger the transition from an initial period of relatively-high drive resistance to a final period of relatively-low drive resistance. Such a comparison must wait until the Miller plateau period has ended as the gate voltage is relatively constant during the Miller plateau period and thus will not rise above the conventional fixed threshold voltage until the Miller plateau period has ended. But as noted earlier, the bulk of the drain voltage drop occurs during an initial portion of the Miller plateau period due to the non-linearity of the gate-to-drain parasitic capacitance. It is this portion of rapid change of the drain voltage that should be controlled so that excessive EMI is not generated. But the drain voltage is changing relatively slowly during the final portion of the Miller plateau period since the drain voltage has already been substantially discharged during the initial portion. The use of a timer is thus quite advantageous in triggering a transition from period T 2  to period T 3  with regard to increasing switching speed yet still reducing EMI. 
     Some operating waveforms for an example gate drive control circuit are shown in  FIG. 5 . Prior to the beginning of period T 1 , the gate voltage Vgate of the power switch transistor M 1  is grounded so that the power switch transistor M 1  is off. The drain voltage Vdrain of the power switch transistor is equal to the input voltage at this time (assuming a discontinuous conduction mode of operation in which the power switch transistor cycling is sufficiently slow such that the resonant oscillation of the drain voltage has subsided prior to the start of the period T 1 ). To initiate the period T 1 , the pulse width modulation command PWM is asserted. The gate voltage Vgate then begins to rise relatively rapidly during the period T 1  as the drive resistance Rg 1  is relatively low. The gate voltage then rises to the first threshold voltage Vth 1  such that the output signal Vcomp 1  of first comparator C 1  is asserted. The crossing of the first threshold voltage Vth 1  initiates the start of period T 2  during which the drive resistance Rg 2  may be relatively high. As discussed previously, the adaptation of the first threshold voltage is such that the Miller plateau (Vplateau) begins during period T 2 . The timer then expires which triggers an end to period T 2  before the end of the Miller plateau period. In period T 3 , the gate voltage then begins to rise rapidly again to cross the second threshold voltage Vth 2  once the Miller plateau period has ended. During period T 3 , a drive resistance Rg 3  is relatively low. Period T 3  continues until the power switch transistor on-time period ends. Referring again to  FIG. 4 , it will be appreciated that gate drive circuit  315  may include a pull-down transistor (not illustrated) that is switched on to discharge the power switch transistor gate to end the power switch transistor on-time period. 
     As shown in  FIG. 5 , the three drive resistances Rg 1 , Rg 2 , and Rg 3  may all be different. During some modes of operation such as during a discontinuous conduction mode, Rg 2  may be higher than Rg 1  and Rg 3 . In some embodiments, Rg 1  may be greater than Rg 3  but less than Rg 2 . The resulting adaptive control of the gate drive of the power switch transistor M 1  is quite advantageous as the effective duty cycle is increased due to the use of period T 1  to get the channel opened relatively. In addition, the period T 2  need not extend over the entire Miller plateau period yet reduced EMI is still achieved. Moreover, the threshold adaption ensures that various process corners and operating conditions will all have an optimized gate drive. 
     Those of some skill in this art will by now appreciate that many modifications, substitutions and variations can be made in and to the materials, apparatus, configurations and methods of use of the devices of the present disclosure without departing from the scope thereof. In light of this, the scope of the present disclosure should not be limited to that of the particular embodiments illustrated and described herein, as they are merely by way of some examples thereof, but rather, should be fully commensurate with that of the claims appended hereafter and their functional equivalents.