Patent Publication Number: US-2010117242-A1

Title: Technique for packaging multiple integrated circuits

Description:
RELATED APPLICATION 
     This application is related to U.S. application docket number AC50050HH, titled “Technique for Interconnecting integrated circuits,” by Gary L. Miller and Ronald W. Stence,” filed on even date herewith, and assigned to the assignee hereof. 
    
    
     BACKGROUND 
     1. Field 
     This application relates to integrated circuits, and more particularly to interconnecting integrated circuits. 
     2. Related Art 
     There have been many reasons for interconnecting more than one integrated circuit die to form a single packaged device. One use has been to increase memory for a given package. Another has been to combine two die that are commonly used together but are difficult to make using a process that is effective for both. One example is a logic circuit and an RF circuit used for mobile phones. Sometimes there are interconnect issues or interference issues that must be addressed. In any case there are sometimes issues that are addressed because of the particular combination of die being implemented. Regardless of the reason for the combination of the multiple die, there are issues that arise in order to overcome the fact that there is a need to have multiple die. The ability to combine various functionalities on a single die remains limited so the issues associated with multiple die continue. 
     Accordingly there is a need for improved techniques for interconnecting multiple die. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The present invention is illustrated by way of example and is not limited by the accompanying figures, in which like references indicate similar elements. Elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. 
         FIG. 1  is a block diagram of a multiple die device according to an embodiment; 
         FIG. 2  is a block diagram showing more detail of a portion of the device of  FIG. 1 ; 
         FIG. 3  shows address mapping relevant to the operation of the multiple die device; and 
         FIG. 4  is a cross section of the device according to a first packaging embodiment; 
         FIG. 5  is a top view of two die useful in making the device of  FIG. 4 . 
         FIG. 6  is a cross section of the device according to a second packaging embodiment; 
         FIG. 7  is a cross section of the device according to a third packaging embodiment; 
         FIG. 8  is a cross section of the device according to a fourth packaging embodiment; and 
         FIG. 9  is a cross section of the device according to a fifth packaging embodiment. 
     
    
    
     DETAILED DESCRIPTION 
     In one aspect, two integrated circuit die form a device using an intermediate substrate for electrical contact and physical support. The active sides of the die face the intermediate substrate. The intermediate substrate then provides contact externally through conductive contacts or through a package substrate. This is better understood by reference to the following description and the drawings. 
     Shown in  FIG. 1  is a packaged device  10  comprising an integrated circuit die  12 , an integrated circuit die  14 , and an intermediate substrate  16 . Integrated circuit  12  comprises a system interconnect  18 , a core  20 , a DMA  22 , a master circuit  24 , a configuration register  26 , a peripheral  28 , a non-volatile memory (NVM)  30 , a static random access memory (SRAM)  32 , a slave circuit  34 , a decoder  36 , an external terminal  38 , an external terminal  40 , an external terminal  42 , and an external terminal  44 . Integrated circuit  14  comprises a system interconnect  46 , a core  48 , a DMA  50 , a master circuit  52 , a decoder  54 , a configuration register  56 , a peripheral  58 , an NVM  60 , an SRAM  62 , a slave circuit  64 , an external terminal  66 , an external terminal  68 , an external terminal  70 , and an external terminal  72 . In this example integrated circuit die  12  and  14  are the same design. Although it is not essential that they be the same, it is preferable that system interconnects  18  and  46  be of the same protocol. One example of such a system interconnect is the crossbar system interconnect. The crossbar system is a good example because adding resources to such a system is achieved relatively easily. Cores  20  and  48  function as processing units and are connected to system interconnects  18  and  46 , respectively. In this example, die  12  is the primary die functioning as a master and die  14  is the secondary die functioning as a slave. Peripherals  28  and  58  may be a wide variety of functional circuits. One example is an analog to digital converter. The external terminals are for directly connecting externally to the die of which they are a part. 
     With regard to die  12 , system interconnect  18  is connected to core  20  at a master port  21  of system interconnect  18 , to DMA  22  at a master port  23  of system interconnect  18 , to master circuit  24  at a master port  25  of system interconnect  18 , to configuration register  26  at a master port  27  of system interconnect  18 , to peripheral  28  at a slave port  29  of system interconnect  18 , to NVM  30  at a slave port  31  of system interconnect  18 , to SRAM  32  at a slave port  33  of system interconnect  18 , and to slave circuit  34  at a slave port  35  of system interconnect  18 . Master circuit  52  is connected to external terminals  66  and  68  which in this example are not connected externally to die  12 . Configuration register  26  is shown connected directly to decoder  36  for clarity of function but is actually connected to decoder  36  through system interconnect  18 . External terminal  42  is connected to slave circuit  34  and to intermediate substrate  16 . External terminal  44  is connected to configuration register  26  and intermediate substrate  16 . Slave circuit  34  is for connecting to the secondary die. Master circuit  24  is connected to core  20 . Intermediate substrate  16  is for connecting die  12  and  14  together both electrically and structurally. The resources connected to what is shown as the upper portion of system interconnect  18  are connected to master ports and those resources on the lower portion of system interconnect  18  are connected to slave ports. Thus, core  20 , DMA  22 , and master circuit  24  are communicatively coupled to system interconnect  18  at master ports. Peripheral  28 , NVM  30 , SRAM  32 , slave circuit  34 , and configuration register  26  are communicatively coupled to system interconnect  18  at slave ports. Having a microcontroller with a system interconnect divided having slave ports and master ports is well known in the art. 
     With regard to die  14 , system interconnect  46  is connected to core  48 , DMA  50 , master circuit  52 , decoder  54 , configuration register  56 , peripheral  58 , NVM  60 , SRAM  62 , slave circuit  64 . Master circuit  52  is connected to external terminals  66  and  68 . External terminals  66  and  68  are connected to intermediate substrate  16 . Decoder  54  is shown being directly connected to configuration register  56  for clarity of function but is actually connected to configuration register  56  through system interconnect  46 . Configuration register  56  is connected to external terminal  70 . Slave circuit  64  is connected to external terminal  72 . External terminals  70  and  72  are not connected to circuitry external to die  14 . Slave circuit  34  and configuration register  26  being connected to master circuit  52  through intermediate substrate  16  establish die  12  as the primary and die  14  as the secondary. Core  48 , DMA  50 , master circuit  52  are communicatively coupled to system interconnect  18  at master ports. Peripheral  58 , NVM  60 , SRAM  62 , slave circuit  64 , and configuration register  56  are communicatively coupled to system interconnect  18  at slave ports. 
     In operation, core  20  can access resources connected to system interconnect  18  as well as peripheral  58 , NVM  60 , and SRAM  62  connected to system interconnect  46 . Decoder  36  decodes the system interconnect to load configuration register with the control information that external terminal  44  will provide information that die  12  is the primary. This is received by external terminal  68  and thus master circuit  52  as a configuration signal C through intermediate substrate  16 . Master circuit  52  is for receiving transaction requests from the primary die acting as the master. Slave circuit  34  controls transactions T with master circuit  52  through intermediate substrate  16  and external terminal  66 . For example, if core  20  chooses to access SRAM  62 , this is communicated to slave circuit  34  through system interconnect  18 . Slave circuit communicates the transaction T to master circuit  52 . Master circuit  52  then performs the transaction regarding SRAM  62  through system interconnect  46 . The transaction is communicated back from master circuit  52  to slave circuit  34  and from slave circuit  34  to core  20  using system interconnect  18 . This is further explained with reference to  FIG. 2 . 
     Shown in  FIG. 2  is a portion of device  10  in more detail. Shown in  FIG. 2  and also shown in  FIG. 1  are system interconnect  18 , slave circuit  34 , configuration register  26 , intermediate substrate  16 , master circuit  52 , system interconnect  46 , core  48 , and external terminals  42 ,  44 ,  66 , and  68 . Slave circuit  34  comprises slave logic  74  and a communication handshake circuit  76 . Slave logic  74  is connected to system interconnect  18  through a first interface and to communication handshake circuit  76  through a second interface. Master circuit  52  comprises a communication handshake circuit  78 , an address translation circuit  80 , and master logic  82 . Communication handshake circuit  78  is connected to external terminal  66  through a first interface and to address translation circuit  80  through a second interface. Master logic  82  is connected to address translation circuit  80  through a first interface and to system interconnect through a second interface. Address translation circuit and core  48  are connected to configuration register  26  through external terminals  68  and  44 . Slave logic  74  interfaces with system interconnect  18  in order to know what transactions to perform with die  14  and couples the necessary information such as addresses and data when a transaction is being performed. Communication handshake circuit  76  communicates with communication handshake circuit  78  so that signals between them are timely and synchronized. 
     Core  20  has access to the resources connected to system interconnect  46  and thus has doubled the resources at its disposal. In the case of adding memory such as NVM  60  and SRAM  62 , integrated circuit  12  must also be able to add corresponding address space compared to what is required for just using the memory connected to system interconnect  18 . This is rarely a problem because the amount of system memory onboard a microcontroller is far less than the addressing capability of the core. Core  20  would be expected to have addressing capability of at least 32 bits and perhaps 64 or even 128. Even with the low addressing capability of only 32 bits, the number of memory locations being able to be addressed is in excess of 4 billion. If there was a byte in each location that would be a capability of addressing in excess of 4 gigabytes of memory. At the same time, however, the address space for the memory in integrated circuit  14  is the same as that for integrated circuit  12 . Thus, in order to treat the memory of integrated circuit  14  as additional memory, there must be an address translation when core  20  is addressing the memory of integrated circuit  14 . This is shown in  FIG. 3 . Thus the primary memory, which is the memory in the primary microcontroller that is integrated circuit  12  in this example, occupies a first address range within an address map and the secondary memory, which is the memory in the secondary microcontroller that is integrated circuit  14  in this example, occupies a second address range within the address map. As shown in  FIG. 3 , this same methodology applies to using the peripherals as well. In the case where a resource of integrated circuit  14  is treated as duplicate resource to that of integrated circuit  12 , then no translation is required. 
     When a resource on the secondary die, such as SRAM  62 , is treated as a duplicate resource, it replaces the identical resource SRAM  32  on the primary die. In operation, core  20  would access the address space associated with SRAM  32  across system interconnect  18 , yet the access would be diverted to SRAM  62  via slave  1  circuit  34 , intermediate substrate  16 , master  2  circuit  52 , and system interconnect  46 . In this operation no address translation is required, however, the address decoding logic associated with SRAM  32  is disabled. 
     For an operational example, if an address for a write is to be communicated ultimately to SRAM  62 , then communication handshake circuit  78  must be ready to receive it. Address translation  80 , under the control of configuration register  26 , performs necessary translations. In this example of die  12  and die  14  being the same design, the memory space allocated by decoder  36  for the memory, such as NVM  60  or SRAM  62 , of die  14  is different than that recognized by die  14 . Thus a translation is required. Configuration register  26  thus communicates what translation is needed. Address translation circuit  80  thus performs the translation that is commanded by configuration register  26 . Master logic  82  receives the translated address from address translation circuit  80  and negotiates with system interconnect  46  to perform the commanded transaction. Core  48  is placed into a lower power mode under the command of configuration register  26 . Core  48  may be active during start-up, but after start-up has been completed, core  48  may be powered down to save power. In this example, translation is performed by the secondary die, but the translation could instead be performed by the primary die. As shown in  FIG. 2 , address translation circuit  80  could be moved between slave logic  74  and communication handshake  76 . 
     In case of die  14  providing information back to die  12 , master logic  82  receives the information from system interconnect  46  and couples the information to address translation circuit  80 . Address translation circuit  80  performs any needed translation under the command of configuration register  26 . Communication handshake circuit coordinates with handshake circuit  76  to properly communicate the information to logic  74 . Logic  74  then negotiates with system interconnect to get the information through system interconnect to core  20 . 
     This operation allows for core  20  to use resources of die  14  that are connected to system interconnect  46 . Thus, a variety of experiments may be run to determine the optimum combination of resources for a next generation of integrated circuits. Because the experiments are being run with existing integrated circuits from which there is already, and probably improving, manufacturing capability, the time to market for an integrated circuit with a new combination of such resources is expected to be short. 
     Shown in  FIG. 4  is a completed device  10  in pictorial form as a cross section showing die  12  and die  14  coupled to each other through intermediate substrate  16  and encapsulated with an encapsulant such as a mold compound like epoxy novolac. Representative contacts, which may also be called terminals, are shown for simplicity and ease of understanding, but many more contacts would be present for an actual device. Die terminals may be, for example, solder, gold, or a conductive organic material such as silver filled epoxy or an epoxy sphere coated with a conductor. Also shown is a heat spreader  86  for coupling heat from die  12  to a package substrate  84 . Intermediate substrate  16  connects terminals of die  12  and  14  to each other as well as to a top surface of package substrate  84 . An example of a die to die connection is a terminal  104  of die  12  connected to a terminal  102  of die  14  through a via  98 . Another example is terminal  106  of die  14  connected to terminal  108  of die  12  through a via  100 . Vias  98  and  100  may be plated holes through intermediate substrate  16 . An example of a connection between die  14  and intermediate substrate  16  is a terminal  110  connected to a pad  118  of intermediate substrate  16  through a conductive line  120 . Die  14  similarly has a terminal  114  connected to an intermediate substrate pad of intermediate substrate  16 . In the same way, die  12  has connections  112  and  116  connected to pads of intermediate substrate  16 . In this example, pads on intermediate substrate  16  that are connected to pads of die  12  or die  14  are connected to package substrate  84  by wire bonding such as by wire bond  111  which connects pad  118  of intermediate substrate  16  to solder ball  90 . The wire bond landings are connected to solder balls on the bottom of package substrate  84 . Other exemplary solder balls that are on the bottom of package substrate  84  shown in  FIG. 4  are solder balls  92 ,  94 , and  96 . Intermediate substrate  16  may be made of silicon or some other material such as a ceramic such as aluminum nitride. Heat spreader  86  may be made of a metal such as copper or another type of material with good heat transfer. Good heat transfer and matching the coefficient of thermal expansion are desired objectives for heat spreader  86 . 
     Shown in  FIG. 5  is a top view of die  12  and  14  and also die  136  and  138  as shown on a wafer  140 . Die  12  and  14  are shown having contacts that are arranged so as to be convenient in attaching to intermediate substrate  16  in a desired manner. In this example, die  12  and  14  should be the same but have somewhat different functions. Die  12  functions as the primary or master, and die  14  functions as the secondary or slave. Some contacts are for use when the particular die is primary and others for use when functioning as the slave. Shown on die  14  are contacts  102 ,  106 ,  110 ,  114 ,  120 ,  122 ,  124 ,  126 ,  154 , and  156 . Shown on die  12  are contacts  104 ,  108 ,  112 ,  116 ,  128 ,  130 ,  132 ,  134 ,  158 , and  160 . With the secondary being die  14 , contacts associated with it being the secondary include contacts  102 ,  106 , and  154 . The unused master contacts are  122 ,  124 , and  156 . Master contacts  122 ,  124 , and  156  are symmetric about center line  142  with slave contacts  106 ,  102 , and  154 , respectively. For example, a distance  146  from center line  142  to contact  124  is the same as a distance  148  from center line  142  to contact  102 . Similarly for die  12 , contacts associated with it being a master are contacts  108 ,  104 , and  160 . The unused slave contacts associated with die  12  being a master are contacts  130 ,  132 , and  158 . Slave contacts  130 ,  132 , and  158  are symmetric about center line  144  with master contacts  108 ,  104 , and  160 , respectively. For example, a distance  150  from center line  144  to contact  104  is the same as a distance  152  from center line  144  to contact  132 . This symmetry allows for die  12  and  14  to be the same but also to have the slave contacts align to the master contacts and the master contacts align to the slave contacts. This allows for the active regions of die  12  and  14  to face each other while contacting intermediate substrate aligned so that the slave contacts of one die are electrically connected to the master contacts of the other die. Because the die are the same and any one can be either a slave or a master, each other contact also has a corresponding symmetrical contact. 
     In other applications where the die can be different, the symmetry may not be of concern and the approach shown in  FIG. 4  could be used without requiring the symmetry. 
     Shown in  FIG. 6  is a completed device  168  as an alternative to completed device  10  of  FIG. 4 . Device  168  has die  12  and  14  contacting an intermediate substrate  170  in similar fashion to how they contacted intermediate substrate  16  in  FIG. 4 . Terminal  114  as an exemplary terminal is coupled to an contact of intermediate substrate  170  through a conductor  182 . Device  168  differs from device  10  by intermediate substrate  170  contacting a package substrate  172  using solder balls such as solder ball  174  to contact package substrate  172 , and by die  12 , the primary, being over the die  14 . Die  12  has a backside opposite from the active side exposed so that a heat spreader may be applied to it. The primary integrated circuit has the greater need for a heat spreader than the secondary integrated circuit. This also shows solder balls such as solder ball  176  as the external connection of device  168  and that the solder balls may be under the die. An exemplary conductor  180  connects solder ball  174  to solder ball  176  through package substrate  172 . Encapsulant  178  covers all but the backside of die  12  and  14  and intermediate substrate  170 . This type of package with an array of solder balls is sometimes referenced as a ball grid array (BGA) package. The active sides of die  12  and  14  face intermediate substrate  170  and no wire bonds are required. 
     Shown in  FIG. 7  is a completed device  190  as another alternative. Die  12  and  14  are attached to an intermediate substrate with their active sides facing the intermediate substrate as described previously for devices  10  and  168 . In this case, a package substrate  191  has an opening in which resides die  14 . The package substrate has selected portions, such as conductive portions  194  and  196  that are for providing the electrical contact outside the package. Conductive portions  194  and  196  are an integral part of the structure of package substrate  191  which may be, for example, part of a lead frame of copper, a conductor commonly known as alloy  42 , or another lead frame material useful in a lead frame known as quad flat no-lead (QFN) package. Electrical contacts from the intermediate substrate to the conductive portions are through terminals such as terminal  195  similar to the previously described terminals. An exemplary conductor  193  connects die  12  to terminal  195  through the intermediate substrate. Encapsulant  192 , in this example, extends only to the top of die  12  so that the backside of die  12  is exposed and a heat spreader may be applied. 
     Shown in  FIG. 8  is a completed device  200  that is the same as completed device  190  except die  14  is on top and die  12  is on the bottom and an encapsulant  202  covers die  14 . In this case, a heat spreader would need to be applied on the bottom side of completed device  200  because that is where die  12  has its backside exposed. 
     Shown in  FIG. 9  is a completed device  210  similar as yet another alternative that has die  12  and  14  attached to an intermediate substrate with their active sides facing the intermediate substrate as described previously for devices  10 ,  168 ,  190 , and  200 . In this case solder balls, such as solder ball  212 , are used to provide electrical connection to device  210 . Die  12  is shown as being on the bottom so its backside is exposed there for application of a heat spreader. Die  14  has its backside exposed on the top. Die  12  and  14  may be switched so that die  112  would have its backside exposed on the top of device  210 . Solder balls, such as solder ball  214 , are shown attached to device  210  showing that a BGA can also be made in this fashion. 
     Thus, a variety of variations for packaging die  12  and  14  are available as shown in  FIGS. 4-9 . The packaging is particularly beneficial for this situation where the die are the same, but these packages potentially have applicability outside of this particular context. The two die could be very diverse such as a die optimized for RF performance and a die designed for logic. Further the two die could be different sizes. 
     By now it should be appreciated that there has been provided a semiconductor device. The semiconductor device includes an intermediate substrate having a first surface and a second surface. The semiconductor device further includes a first die attached to the first surface of the intermediate substrate in which the first die has a first active surface and the first active surface faces the intermediate substrate, a second die attached to the second surface of the intermediate substrate in which the second die has a second active surface, the second active surface faces the intermediate substrate, and the second die is coupled to the first die through an electrically conductive material in the intermediate substrate. The semiconductor device further includes an organic material encapsulating at least an edge of the intermediate substrate and an edge the second die. The semiconductor device may be further characterized by the first die further including a master circuit and a master port, in which the master circuit is coupled to the master port, the second die further including a slave circuit and a slave port in which the slave circuit is coupled to the slave port. The semiconductor device may be further characterized by the second die being over the first die. The semiconductor device may further comprise a substrate in which the first die is closer to the substrate than the second die and the intermediate substrate is wirebonded to the substrate. The semiconductor device may further comprise solder balls attached to the substrate, wherein the intermediate substrate is coupled to the solder balls. The semiconductor device may further comprise a heat spreader over the substrate and in contact with a non-active surface of the first die, wherein the non-active surface is parallel to the first active surface. The semiconductor device may be further characterized by the organic material being over a non-active surface of the second die wherein the non-active surface is parallel to the second active surface. The semiconductor device may be further characterized by at least a portion of the second die being exposed. The semiconductor device may be further characterized by the first die being over the second die. The semiconductor device may be further characterized by at least a portion of the first die being exposed. The semiconductor device may be further characterized by at least a portion of the second die being exposed. The semiconductor device may be further characterized by the second die being attached to a leadframe. The semiconductor device may further include a substrate, wherein the second die is closer to the substrate than the first die. The semiconductor device may further comprise a via, wherein the via comprises the electrically conductive material. The semiconductor device of claim may be further characterized by the first die further comprising a first master port and a first slave port, the first master port and the first slave port being symmetrically located around a line of symmetry of the first die, the second die further comprising a second master port and a second slave port, the second master port and the second slave port being symmetrically located around a line of symmetry of the second die, and the first master port being coupled to the second slave port. 
     Also described is a semiconductor device. The semiconductor device includes a first die having a first die active surface and a first die non-active surface, wherein the first die active surface and the first die non-active surface are parallel to each other. The semiconductor device further includes a second die over the first die, wherein the second die has a second die active surface and a second die non-active surface, wherein the second die active surface and the second die non-active surface are parallel to each other. The semiconductor device further includes an intermediate substrate between the first die and the second die in which the first die active surface is closer to the intermediate substrate than the first die non-active surface and the second die active surface is closer to the intermediate substrate than the second die non-active surface. The semiconductor device further includes an organic material encapsulating an edge of the intermediate substrate. The semiconductor device may further comprise plurality of vias in the intermediate substrate, wherein the plurality of vias couple the first die to the second die. The semiconductor may be further characterized by the first die further comprising a first master port and a first slave port, the first master port and the first slave port being symmetrically located around a line of symmetry of the first die, the second die further comprising a second master port and a second slave port, the second master port and the second slave port being symmetrically located around a line of symmetry of the second die, and the first master port being coupled to the second slave port through the plurality of vias. The semiconductor device may be further characterized by the first die being closer to a substrate than the second die and the intermediate substrate being wirebonded to the substrate. 
     Described also is a method of forming a semiconductor device. The method includes attaching a first die to an intermediate substrate, wherein a first die active surface is facing the intermediate substrate. The method further includes attaching a second die to the intermediate substrate in which a second die active surface is facing the intermediate substrate and the second die is coupled to the first die via the intermediate substrate. The method further includes encapsulating at least a portion of the intermediate substrate with an organic material after attaching the second die to the intermediate substrate. 
     Moreover, the terms “front,” “back,” “top,” “bottom,” “over,” “under” and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions. It is understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in other orientations than those illustrated or otherwise described herein. 
     Although the invention is described herein with reference to specific embodiments, various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. For example, the materials used may differ from those described. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the present invention. Any benefits, advantages, or solutions to problems that are described herein with regard to specific embodiments are not intended to be construed as a critical, required, or essential feature or element of any or all the claims. 
     The term “coupled,” as used herein, is not intended to be limited to a direct coupling or a mechanical coupling. 
     Furthermore, the terms “a” or “an,” as used herein, are defined as one or more than one. Also, the use of introductory phrases such as “at least one” and “one or more” in the claims should not be construed to imply that the introduction of another claim element by the indefinite articles “a” or “an” limits any particular claim containing such introduced claim element to inventions containing only one such element, even when the same claim includes the introductory phrases “one or more” or “at least one” and indefinite articles such as “a” or “an.” The same holds true for the use of definite articles. 
     Unless stated otherwise, terms such as “first” and “second” are used to arbitrarily distinguish between the elements such terms describe. Thus, these terms are not necessarily intended to indicate temporal or other prioritization of such elements.