Patent Publication Number: US-9899260-B2

Title: Method for fabricating a semiconductor device

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates generally to a semiconductor device, and more particularly to a TSV interposer and a fabrication method thereof. 
     2. Description of the Prior Art 
     A through substrate via (TSV) interposer is a device with electrical through vias that is inserted between one or more integrated circuit chips and a mounting substrate. The electrical through vias allow the integrated circuit chips to be electrically connected to the mounting substrate. 
     As known in the art, the electrical through vias are formed by providing holes in a front side of a silicon substrate, insulating the sidewall of the through holes, filling a conductor metal, such as copper, in the through holes by plating or the like, and then grinding the silicon substrate on its rear side to expose the other ends of the electrical through vias for further connection. 
     However, the prior art method has some drawbacks, for example, copper extrusion on the exposed ends of the electrical through vias on the rear side of the silicon substrate. Accordingly, there exists a need in the art to overcome the deficiencies described hereinabove. 
     SUMMARY OF THE INVENTION 
     In one aspect, the present invention provides a method of fabricating a semiconductor device. A wafer having a front side and a back side opposite to the front side is prepared. A plurality of through substrate vias (TSVs) is formed on the front side. A redistribution layer (RDL) is then formed on the TSVs. The wafer is bonded to a carrier. A wafer back side grinding process is performed to thin the wafer on the back side. An anneal process is performed to recrystallize the TSVs. A chemical-mechanical polishing (CMP) process is performed to polish the back side. 
     These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The accompanying drawings are included to provide a further understanding of the embodiments, and are incorporated in and constitute apart of this specification. The drawings illustrate some of the embodiments and, together with the description, serve to explain their principles. In the drawings: 
         FIG. 1  through  FIG. 6  are schematic, cross-sectional diagrams showing an exemplary method for fabricating a semiconductor device according to one embodiment of the invention. 
     
    
    
     DETAILED DESCRIPTION 
     In the following detailed description of the invention, reference is made to the accompanying drawings, which form a part hereof, and in which is shown, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural changes may be made without departing from the scope of the present invention. 
     The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims, along with the full scope of equivalents to which such claims are entitled. One or more implementations of the present invention will now be described with reference to the accompanying drawings, wherein like reference numerals are used to refer to like elements throughout, and wherein the illustrated structures are not necessarily drawn to scale. 
     The terms “wafer” and “substrate” used herein include any structure having an exposed surface onto which a layer is deposited according to the present invention, for example, to form a circuit structure such as a redistribution layer (RDL). The term “substrate” is understood to include semiconductor wafers, but not limited thereto. The term “substrate” is also used to refer to semiconductor structures during processing, and may include other layers that have been fabricated thereupon. 
       FIG. 1  through  FIG. 6  are schematic, cross-sectional diagrams showing an exemplary method for fabricating a semiconductor device according to one embodiment of the invention. 
     As shown in  FIG. 1 , first, a wafer  100  is provided. The wafer  100  may comprise a silicon interposer wafer, but not limited thereto. The wafer  100  may have an initial thickness that may range between 600 and 800 micrometers, for example, 770 micrometers. The wafer  100  has a front side  100   a  and a back side  100   b.    
     A plurality of through substrate vias (TSVs)  101  may be formed in the wafer  100  on the front side  100   a  of the wafer  100 . The method for making of the TSVs  101  is well known in the art. For example, to form the TSVs  101 , TSV holes are formed on the front side  100   a  of the wafer  100  to a predetermined depth below a major surface of the wafer  100 . An interior surface of each TSV hole may be insulated by a dielectric layer, such as a silicon oxide layer  103 . Metals including, but not limited to, diffusion barrier metals and copper  102  are deposited into the TSV holes. The front side  100   a  of the wafer  100  may be subjected to a polishing process and an anneal process. 
     As shown in  FIG. 2 , according to the illustrated embodiment, a redistribution layer (RDL)  110  may be formed on the front side  100   a  of the wafer  100 . The RDL  110  may comprise at least one dielectric layer  112  and at least one metal layer  114 . The TSVs  101  may be connected with the metal layer  114 . A plurality of bumps  116  such as micro-bumps may be formed on the RDL  110  for further connections. The bumps  116  may be directly formed on respective contact pads formed in the metal layer  114 . 
     It is to be understood that the RDL structure as shown in the figures is for illustration purposes only. In some embodiments, the RDL  110  may comprise multiple dielectric layers and multiple metal interconnection features or traces in the multiple dielectric layers. In still another embodiment, semiconductor dies may be mounted on the front side  100   a  and sealed by a molding compound (not shown). 
     As subsequently shown in  FIG. 3 , wafer  100  is adhered to a carrier  200 . For example, the carrier  200  may be a glass carrier, a silicon carrier, or the like, but is not limited thereto. The bumps  116  face toward, and may contact, the carrier  200 . Optionally, an adhesive layer (not explicitly shown) may be used when bonding the carrier  200  with the wafer  100 . 
     As subsequently shown in  FIG. 4 , after forming the carrier  200 , the back side  100   b  of the wafer  100  is subjected to a wafer back side grinding process to thin the wafer  100 . A portion of the wafer  100  is removed from the back side  100   b  of the wafer  100 . Optionally, chemical-mechanical polishing (CMP) process may be performed to reveal the TSVs  101  from the back side  100   b  of the wafer  100 . 
     As shown in  FIG. 5 , the back side  100   b  of the wafer  100  is then subjected to an anneal process  300  to recrystallize the copper  102  of the TSVs  101  near the back side  100   b  of the wafer  100 . According to the illustrated embodiment, the anneal process  300  is preferably carried out at a temperature of about 200° C. According to the illustrated embodiment, copper extrusion  130  may occur on the exposed ends of the TSVs  101 . 
     As shown in  FIG. 6 , the back side  100   b  of the wafer  100  is then subjected to another CMP process to polish away the copper extrusion  130  from the back side  100   b  of the wafer  100 . Subsequently, a passivation layer (not shown) may be formed on the back side  100   b  of the wafer  100 . Optionally, a redistribution layer may be formed on the back side  100   b  of the wafer  100 . Subsequently, the carrier  200  may be de-bonded. 
     Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.