Patent Publication Number: US-RE48209-E

Title: Display apparatus and method for driving display panel thereof

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application is a reissue of U.S. Pat. No. 8,253,651, filed on Aug. 22, 2007 and issued on Aug. 28, 2012, which claims the priority benefit of Taiwan application serial no. 96123780, filed Jun. 29, 2007. All disclosure of the Taiwan application The entirety of each of the above-mentioned applications and patents is incorporated herein by reference and made a part of this specification. 
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a display apparatus and a method for driving a display panel thereof. More particularly, the present invention relates to an LCD display apparatus and a method for driving a display panel thereof. 
     2. Description of Related Art 
     In order to satisfy the demands for display quality of LCD TV market, liquid crystal display panels are developed gradually towards specifications of high resolution, impulse systems, and high frame rates. However, the above specifications will influence charging time which is already at the margin, and the details are described as follows. 
       FIG. 1  is a schematic view of the architecture of a conventional display system of double frame-rate. A display panel  101  of the system is divided into an upper half part and a lower half part, and gate drivers  102  and  103  at left and right sides of the display panel  101  are used to drive scan lines (not shown) of the display panel  101 , so as to further turn on pixels coupled to the scan lines. Meanwhile, source drivers  104  and  105  on upper and lower sides of the display panel  101  are also used to provide display data required by pixels that have been turned on in the upper half and the lower half parts, respectively. 
     The above system also adopts the impulse system technology, and the signal timing in the system is as shown in  FIG. 2 .  FIG. 2  is a timing diagram of signals of the system of  FIG. 1 . STV 1 -STV 4  are gate start driving signals, VCLK is a clock signal, OE is an output enable signal, /OE is an inverted signal of OE, and VG 1 -VGn are gate pulse signals. As shown in  FIG. 2 , the impulse system technology adopts a time-division driving method of each scan line to separate the writing time of image data and reset signal (for inserting black frames). In addition, it would be known from  FIG. 2  that if the writing time of the image data and the reset signal is averaged, the effective charging time of the two is H/2-Trc. Here, H is scan time of the scan lines, and Trc is delay time of RC. If the writing time of the image data and the reset signal is not averaged, for example, the image data is written for the time of 2H/3 and the reset signal is written for the time of H/3, the effective charging time of the image data and the reset signal is 2H/3-Trc and H/3-Trc, respectively. 
     The reset signal for inserting black frames is originally used to solve the problem of motion blur generated by hold-type display. However, under the condition of improving the frame rate, the charging time will be at the margin. Even if the charging time of the image data is extended, the charging time of the reset signal will be insufficient, which results in ineffective charging, and the target value of the reset signal cannot be obtained. Therefore, the performance of the analog impulse type display will be degraded, and the problem of motion blur cannot be solved effectively. 
     SUMMARY OF THE INVENTION 
     The present invention is directed to a display apparatus, which can provide double frame rate, and effectively eliminate motion blur. 
     The present invention is also directed to a method for driving a display panel, which can provide double frame rate, and effectively eliminate motion blur. 
     As embodied and broadly described herein, the present invention provides a display apparatus, which includes a display panel, a gate driver, a first source driver, and a second source driver. The display panel includes M rows of scan lines, N columns of data lines, and M×N pixels. Each column of the data line includes a first sub-data line and a second sub-data line. The pixels are arranged in a matrix, in which the pixel of an (i)th row and a (j)th column is denoted by P(i, j), where 1≤i≤M, and 1≤j≤N. The first sub-data line of the (j)th column and an (i)th scan line are coupled to the pixel P(i, j). The second sub-data line of the (j)th column and an (i+1)th scan line are coupled to a pixel P(i+1, j). Here, N, M, i, and j are positive integers. The gate driver drives the scan lines, and the first source driver and the second source driver control the first sub-data lines and the second sub-data lines respectively, and output an image signal. The image signal has a plurality of image segments, and each of the image segments has display data of pixels coupled to two adjacent scan lines. Every K image segments are defined as a group, where K is a positive integer. Each group of image segments includes a reset data. The gate driver drives the scan lines corresponding to a first group in K batches according to a first start wave, and drives two adjacent scan lines each time. When the two adjacent scan lines are driven, the first source driver outputs the display data corresponding to the pixels coupled to the (i)th scan line among the scan lines that have been driven, and the second source driver outputs the display data corresponding to the pixels coupled to the (i+1)th scan line among the scan lines that have been driven. After receiving the first start wave for a predetermined time, the gate driver drives the scan lines corresponding to the first group at the same time according to a second start wave, and the first source driver and the second source driver output the reset data to the first sub-data lines and the second sub-data lines, respectively. 
     As embodied and broadly described herein, the present invention further provides a display apparatus, which includes a display panel, a gate driver, a first source driver, and a second source driver. The display panel includes M rows of scan lines, N columns of data lines, and M×N pixels. Each column of the data line includes a first sub-data line and a second sub-data line. The pixels are arranged in a matrix, in which the pixel at an (i)th row and a (j)th column is denoted by P(i, j), where 1≤i≤M, and 1≤j≤N. The first sub-data line of the (j)th column is coupled to the pixel P(i, j) at a coupling point of an (i)th scan line, a pixel P(i+1, j) at a coupling point of an (i+1)th scan line, till a pixel P(i+n, j) at a coupling point of an (i+n)th scan line. The second sub-data line of the (j)th column is coupled to a pixel P(i+n+1, j) at a coupling point of an (i+n+1)th scan line, a pixel P(i+n+2, j) at a coupling point of an (i+n+2)th scan line, till a pixel P(i+2n+1, j) at a coupling point of an (i+2n+1)th scan line. Here, N, M, i, j, and n are positive integers. The gate driver drives the scan lines, and the first source driver and the second source driver control the first sub-data lines and the second sub-data lines respectively, and output an image signal. The image signal has a plurality of image segments, and each of the image segments has display data of pixels coupled to two adjacent scan lines. Every K image segments are defined as a group, where K is a positive integer. Each group of image segments includes a reset data. The gate driver drives the scan lines corresponding to a first group in K batches according to a first start wave, and drives two adjacent scan lines each time. When the two adjacent scan lines are driven, the first source driver outputs the display data corresponding to the pixels coupled to the (i+n)th scan line among the scan lines that have been driven, and the second source driver outputs the display data corresponding to the pixels coupled to the (i+n+1)th scan line among the scan lines that have been driven. After receiving the first start wave for a predetermined time, the gate driver drives the scan lines corresponding to the first group at the same time according to a second start wave, and the first source driver and the second source driver output the reset data to the first sub-data lines and the second sub-data lines respectively. 
     As embodied and broadly described herein, the present invention further provides a display apparatus, which includes a display panel, a gate driver, and a source driver. The display panel includes M rows of scan lines, N columns of data lines, and M×N pixels. Each column of the data line includes a first sub-data line and a second sub-data line. The pixels are arranged in a matrix, in which the pixel at an (i)th row and a (j)th column is denoted by P(i, j), where 1≤i≤M, and 1≤j≤N. The first sub-data line of the (j)th column and an (i)th scan line are coupled to the pixel P(i, j). The second sub-data line of the (j)th column and an (i+1)th scan line are coupled to a pixel P(i+1, j). Here, N, M, i, and j are positive integers. The gate driver drives the scan lines, and the source driver controls the first sub-data lines and the second sub-data lines, and outputs an image signal. The image signal has a plurality of image segments, and each of the image segments has display data of pixels coupled to two adjacent scan lines. Every K image segments are defined as a group, where K is a positive integer. Each group of image segments includes a reset data. The gate driver drives the scan lines corresponding to a first group in K batches according to a first start wave, and drives two adjacent scan lines each time. When the two adjacent scan lines are driven, the source driver outputs the display data corresponding to the pixels coupled to the (i)th scan line among the scan lines that have been driven to the first sub-data lines, and outputs the display data corresponding to the pixels coupled to the (i+1)th scan line among the scan lines that have been driven to the second sub-data lines. After receiving the first start wave for a predetermined time, the gate driver drives the scan lines corresponding to the first group at the same time according to a second start wave, and the source driver outputs the reset data to the first sub-data lines and the second sub-data lines. 
     As embodied and broadly described herein, the present invention further provides a display apparatus, which includes a display panel, a gate driver, and a source driver. The display panel includes M rows of scan lines, N columns of data lines, and M×N pixels. Each column of the data line includes a first sub-data line and a second sub-data line. The pixels are arranged in a matrix, in which the pixel at an (i)th row and a (j)th column is denoted by P(i, j), where 1≤i≤M, and 1≤j≤N. The first sub-data line of the (j)th column is coupled to the pixel P(i, j) at a coupling point of an (i)th scan line, a pixel P(i+1, j) at a coupling point of an (i+1)th scan line, till a pixel P(i+n, j) at a coupling point of an (i+n)th scan line. The second sub-data line of the (j)th column is coupled to a pixel P(i+n+1, j) at a coupling point of an (i+n+1)th scan line, a pixel P(i+n+2, j) at a coupling point of an (i+n+2)th scan line, till a pixel P(i+2n+1, j) at a coupling point of an (i+2n+1)th scan line. Here, N, M, i, j, and n are positive integers. The gate driver drives the scan lines, and the source driver controls the first sub-data lines and the second sub-data lines, and outputs an image signal. The image signal has a plurality of image segments, and each of the image segments has display data of pixels coupled to two adjacent scan lines. Every K image segments are defined as a group, where K is a positive integer. Each group of image segments includes a reset data. The gate driver drives the scan lines corresponding to a first group in K batches according to a first start wave, and drives two adjacent scan lines each time. When the two adjacent scan lines are driven, the source driver outputs the display data corresponding to the pixels coupled to the (i i+n)th scan line among the scan lines that have been driven to the first sub-data lines, and outputs the display data corresponding to the pixels coupled to the (i+n+1)th scan line among the scan lines that have been driven to the second sub-data lines. After receiving the first start wave for a predetermined time, the gate driver drives the scan lines corresponding to the first group at the same time according to a second start wave, and the source driver outputs the reset data to the first sub-data lines and the second sub-data lines. 
     As embodied and broadly described herein, the present invention provides a method for driving a display panel. The display panel includes M rows of scan lines, N columns of data lines, and M×N pixels. Each column of the data line includes a first sub-data line and a second sub-data line. The pixels are arranged in a matrix, in which the pixel at an (i) h row and a (j)th column is denoted by P(i, j), where 1≤i≤M, and 1≤j≤N. The first sub-data line of the (j)th column and an (i)th scan line are coupled to the pixel P(i, j). The second sub-data line of the (j)th column and an (i+1)th scan line are coupled to a pixel P(i+1, j). Here, N, M, i, and j are positive integers. The driving method includes the following steps. First, an input image signal is provided. Then, the input image signal is divided into a plurality of image segments, and each of the image segments has display data of pixels coupled to two adjacent scan lines. Next, every K image segments are defined as a group, where K is a positive integer. Next, a reset data is inserted into each group of image segments. Then, the scan lines corresponding to a first group are driven in K batches according to a first start wave, and two adjacent scan lines are driven each time. When the two adjacent scan lines are driven, display data of the pixels coupled to the (i)th scan line among the scan lines that have been driven is provided to the first sub-data lines, and display data of the pixels coupled to the (i+1)th scan line among the scan lines that have been driven is provided to the second sub-data lines. Then, after a predetermined time from the first start wave, the scan lines corresponding to the first group are driven at the same time according to a second start wave, and the reset data is output to the first sub-data lines and the second sub-data lines. 
     As embodied and broadly described herein, the present invention further provides a method for driving a display panel. The display panel includes M rows of scan lines, N columns of data lines, and M×N pixels. Each column of the data line includes a first sub-data line and a second sub-data line. The pixels are arranged in a matrix, in which the pixel at so an (i)th row and a (j)th column is denoted by P(i, j), where 1≤i≤M, and 1≤j≤N. The first sub-data line of the (j)th column is coupled to the pixel P(i, j) at a coupling point of an (i)th scan line, a pixel P(i+1, j) at a coupling point of an (i+1)th scan line, till a pixel P(i+n, j) at a coupling point of an (i+n)th scan line. The second sub-data line of the (j)th column is coupled to a pixel P(i+n+1, j) at a coupling point of an (i+n+1)th scan line, a pixel P(i+n+2, j) at a coupling point of an (i+n+2)th scan line, till a pixel P(i+2n+1, j) at a coupling point of an (i+2n+1)th scan line. Here, N, M, i, j, and n are positive integers. The driving method includes the following steps. First, an input image signal is provided. Then, the input image signal is divided into a plurality of image segments, and each of the image segments has display data of pixels coupled to two adjacent scan lines. Next, every K image segments are defined as a group, where K is a positive integer. Then, a reset data is inserted into each group of image segments. Afterwards, the scan lines corresponding to a first group are driven in K batches according to a first start wave, and two adjacent scan lines are driven each time. When the two adjacent scan lines are driven, display data of the pixels coupled to the (i i+n)th scan line among the scan lines that have been driven is provided to the first sub-data lines, and display data of the pixels coupled to the (i+i+n+1)th scan line among the scan lines that have been driven is provided to the second sub-data lines. Then, after a predetermined time from the first start wave, the scan lines corresponding to the first group are driven at the same time according to a second start wave, and the reset data is output to the first sub-data lines and the second sub-data lines. 
     The present invention adopts a special display panel, in which each column of the data line includes two sub-data lines. Moreover, in the present invention, an input image signal is divided into a plurality of image segments, and each of the image segments has display data of pixels coupled to two adjacent scan lines. Every K image segments are defined as a group. Then, an image signal is formed by inserting a reset data in each group of image segments. Thereafter, display data of a first group are written in K batches according to a first start wave. After a predetermined time from the first start wave, the scan lines corresponding to the first group are driven at the same time according to a second start wave, and the reset data is output to the first sub-data lines and the second sub-data lines. Thus, the present invention can provide double frame rate, and can effectively eliminate motion blur. In addition, as the polarities of the sub-data lines do not change in a frame, the present invention can reset the data of the pixels of several adjacent scan lines at the same time. 
     In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, preferred embodiments accompanied with figures are described in detail below. 
     It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a schematic view of the architecture of a conventional display system of double frame rate. 
         FIG. 2  is a timing diagram of signals of the system of  FIG. 1 . 
         FIG. 3  is a schematic view of the architecture of a display apparatus according to an embodiment of the present invention. 
         FIG. 4  is a schematic view of another implemented architecture of the display panel of  FIG. 3 . 
         FIG. 5  is a schematic view of a data reorganization method according to the embodiment of  FIGS. 3 and 4 . 
         FIG. 6  is a timing diagram of a part of the signals of the circuit in  FIG. 4 . 
         FIG. 7  is a schematic view of a scan line control method according to an embodiment of the present invention. 
         FIG. 8  is a schematic view of a method for controlling polarities of data when the circuit of  FIG. 4  is operated. 
         FIG. 9  is a schematic view of the architecture of the display panel of  FIG. 3  according to another embodiment. 
         FIG. 10  is a schematic view of the data reorganization method according to the embodiment of  FIGS. 3 and 9 . 
         FIG. 11  is a timing diagram of a part of signals of the circuit in  FIG. 9 . 
         FIG. 12  is a schematic view of a method for controlling polarities of data when the circuit of  FIG. 9  is operated. 
         FIG. 13  is a schematic view of the architecture of the display panel of  FIG. 3  according to yet another embodiment. 
         FIG. 14  is a schematic view of processes of a method for driving a display panel according to an embodiment of the present invention. 
     
    
    
     DESCRIPTION OF EMBODIMENTS 
       FIG. 3  shows a display apparatus according to an embodiment of the present invention. The display apparatus includes an arithmetic unit  301 , a data reorganization unit  302 , a timing controller  303 , and a display panel  304 . The operations of the above components will be briefly described as follows. The arithmetic unit  301  generates a reset data RD according to an input image signal DATA 1  and a counting relation that is related to a plurality of image segments (which will be described later). The reset data RD may be a black or a white image data, or an image data of any single grayscale. The data reorganization unit  302  receives the input image signal DATA 1  and the reset data RD, and reorganizes the input signal DATA 1  and the reset data RD, so as to generate an image signal DATA 2 . The timing controller  303  receives the image signal DATA 2 , so as to generate a plurality of control signals CS according to the image signal DATA 2 . Moreover, the timing controller  303  sends the plurality of control signals CS and the image signal DATA 2  to the display panel  304 , so as to control the display of the image signal DATA 2  on the display panel  304 . 
       FIG. 4  is an embodiment of the display panel of  FIG. 3 , and shows the coupling relationship between the internal components of the display panel  304  and the timing controller  303 , and the image signal DATA 2  and the plurality of control signals CS sent to the display panel  304  by the timing controller  303 . The plurality of control signals CS includes a gate clock signal CPV, a gate start driving signal STV, and output enable signals OE 1 -OE 4 . The display panel  304  includes a gate driver  401 , source drivers  402  and  403 , 16 rows of scan lines, N columns of data lines, and 16×N pixels. The 16 rows of scan lines are denoted by G 53   1 -G 53   4 , G 54   1 -G 54   4 , G 55   1 -G 55   4 , and G 56   1 -G 56   4  respectively. Each column of the data line includes a first sub-data line and a second sub-data line. The first sub-data lines are denoted by D 1 -D N  respectively, and the second sub-data lines are denoted by D 1 -D N , respectively. The 16×N pixels are arranged in a matrix, and the coupling relationship of a column of pixels in the pixel matrix is shown in this figure. For example, the pixel  404  is coupled to the scan line G 53   1  and the sub-data line D 1 , and the pixel  405  is coupled to the scan line G 53   2  and the sub-data line D 1′ . 
     The gate driver  401  further includes four scan units, which are denoted by  53 - 56  respectively. Each of the scan units drives four rows of scan lines. For example, the scan unit  53  drives the scan lines G 53   1 -G 53   4  according to the gate clock signal CPV, the gate start driving signal STV, and the output enable signal OE 1 . After the gate driver  401  receives the gate start driving signal STV, the gate start driving signal STV is transferred inside the scan unit  53  first, and is gradually transferred to the scan unit  56 . When a scan unit receives the gate start driving signal STV, the scan unit drives the scan lines coupled thereto according to the position where the gate start driving signal STV is transferred to, and the source drivers  402  and  403  send the image data corresponding to the image signal DATA 2  at the same time. 
     The data reorganization method of the input image signal DATA 1  and the reset data RD is illustrated, and then the operation of the circuit in  FIG. 4  will be described in detail.  FIG. 5  is a schematic view of a data reorganization method according to the embodiment of  FIGS. 3 and 4 . Referring to  FIG. 5 , DE 1  is a data enable signal corresponding to the input image signal DATA 1 , DE 2  is a data enable signal corresponding to the image signal DATA 2 , CPV is the above gate clock signal, and OED and OEB are two signal forms of each of the output enable signals (OE 1 -OE 4 ). The input image signal DATA 1  has a plurality of image segments. Each of the image segments has the display data of the pixels coupled to two adjacent scan lines. For example, the image segment  501  has the display data of the pixels coupled to the scan lines G 53   1  and G 53   2 , and the image segment  502  has the display data of the pixels coupled to the scan lines G 53   3  and G 53   4 . 
     In this embodiment, every two image segments are defined as one group, and a reset data RST is inserted into each group of image segments. Thus, a time segment Tcycle originally having two batches of data have three batches of data, and the reset data RST is arranged after the image segments of each group. Therefore, the arithmetic unit  301  must generate the positions to arrange the reset data RST according to such a counting relation. In addition, as the image signal DATA 2  is obtained through data reorganization, the image signal DATA 2  is naturally delayed for a time of Tdelay compared with the input image signal DATA 1 . After the image signal DATA 2  is obtained, the signal form of the output enable signal received by each of the scan units must be controlled properly, so as to control the corresponding scan lines properly according to the data timing of the image signal DATA 2 , so as to allow the pixels to receive correct loading data. That is to say, when the output enable signals assume the OED form, and are at a low level (represented by T 1 ), the display data are loaded into the corresponding pixels. When the output enable signals assume the OEB form, and are at a low level (represented by T 2 ), the reset data are loaded into the corresponding pixels. 
       FIG. 6  is a timing diagram of a part of signals of the circuit in  FIG. 4 , and shows the timing of the gate clock signal CPV, the two forms of output enable signals (OED and OEB), the gate start driving signal STV, and gate pulse signals between the scan lines. The gate start driving signals STV has two start waves, which are denoted by STVD and STVB, respectively. Referring to  FIGS. 4 and 6  together, the operation of the circuit of  FIG. 4  is described in more detail. When the timing controller  303  sends the start wave STVD to the scan unit  53 , and provides the output enable signal OE 1  in the OED form to the scan unit  53  and provides the output enable signal OE 3  in the OEB form to the scan unit  55 , the scan unit  53  will operate according to the start wave STVD, the gate clock signal CPV, and the output enable signal OE 1  in the OED form. 
     With the transfer of the start wave STVD in the scan unit  53 , the scan unit  53  drives the scan lines corresponding to the first group of the image signal DATA 2  in two batches, and drives two adjacent scan lines each time. That is to say, when the output enable signal OE 1  in the OED form is at a logic low level, the scan unit  53  will drive two scan lines at the same time. For example, the scan unit  53  first drives the scan lines G 53   1  and G 53   2  at the same time, and then drives the scan lines G 53   3  and G 53   4  at the same time. At the same time when the scan unit  53  drives the scan lines G 53   1  and G 53   2 , the source driver  402  outputs the display data of the pixel coupled to the scan line G 53   1 , and the source driver  403  outputs the display data of the pixel coupled to the scan line G 53   2 . At the same time when the scan unit  53  drives the scan lines G 53   3  and G 53   4 , the source driver  402  outputs the display data of the pixel coupled to the scan line G 53   3 , and the source driver  403  outputs the display data of the pixel coupled to the scan line G 53   4 . 
     After a short period of time, the start wave STVD is transmitted to the scan unit  54 . At this time, the timing controller  303  provides the output enable signal OE 2  in the OED form to the scan unit  54 , and provides the output enable signal OE 4  in the OEB form to the scan unit  56 . After the scan unit  54  receives the start wave STVD, the scan unit  54  also drives the scan lines corresponding to the second group in the image signal in two batches, i.e., drives the scan lines G 54   1  and G 54   2  at the same time first, and then drives the scan lines G 54   3  and G 54   4  at the same time. At the same time when the scan lines G 54   1  and G 54   2  are driven, the source driver  402  outputs the display data of the pixel coupled to the scan line G 54   1  correspondingly, and the source driver  403  outputs the display data of the pixel coupled to the scan line G 54   2  correspondingly. At the same time when the scan lines G 54   3  and G 54   4  are driven, the source driver  402  outputs the display data of the pixel coupled to the scan line G 54   3  correspondingly, and the source driver  403  outputs the display data of the pixel coupled to the scan line G 54   4  correspondingly. More generally, at the same time when two adjacent scan lines are driven, the source driver  402  outputs the display data of the pixels coupled to the (i)th scan line among the scan lines that have been driven correspondingly, and the source driver  403  outputs the display data of the pixels coupled to the (i+1)th scan line among the scan lines that have been driven correspondingly. 
     Then, the timing controller  303  sends the start wave STVB to the scan unit  53 . That is, after a predetermined time since the start wave STVD is output, the timing controller  303  outputs the start wave STVB. Meanwhile, the timing controller  303  provides the output enable signal OE 3  in the OED form to the scan unit  55 , and provides the output enable signal OE 1  in the OEB form to the scan unit  53 . Then, the start wave STVD is also transmitted to the scan unit  55 . Therefore, the scan unit  53  starts to operate according to the start wave STVB, the gate clock signal CPV, and the output enable signal OE 1  in the OEB form. The scan unit  55  also starts to operate according to the start wave STVD, the gate clock signal CPV, and the output enable signal OE 3  in the OED form. Definitely, the above predetermined time may be set according to actual requirements, and is not limited to this embodiment. 
     The output enable signals in either the OED form or the OEB form must be at the logic low level to enable the scan lines. Therefore, when the scan unit  55  drives the scan lines (G 55   1 -G 55   4 ) corresponding to the third group in the image signal according to the start wave STVD, the gate clock signal CPV, and the output enable signal OE 3  in the OED form, as the output enable signal OE 1  in the OEB form is at a logic high level, the scan unit  53  will not drive the scan lines coupled thereto. Moreover, since no start wave is transmitted in the scan units  54  and  56  at this time, the scan units  54  and  56  will not drive the scan lines coupled thereto as well. 
     At the same time when the scan unit  55  drives the scan lines coupled thereto, the source driver  402  will output the display data of the pixels coupled to the (i)th scan line among the scan lines that have been driven correspondingly, and the source driver  403  will output the display data of the pixels coupled to the (i+1)th scan line among the scan lines that have been driven correspondingly. Then, the output enable signal OE 3  in the OED form assumes the logic high level, and the output enable signal OE 1  in the OEB form assumes the logic low level. Therefore, during this period of time, the scan unit  53  drives the scan lines G 53   1 -G 53   4  at the same time, and meanwhile the source drivers  402  and  403  output the reset data as well, so as to reset the display data of the pixels coupled to the scan lines G 53   1 -G 53   4 . Thus, the problem of motion blur of these pixels is avoided, and the effect of an impulse system is realized. 
     Then, the start waves STVD and STVB will be transmitted to the scan units  56  and  54  respectively, and the timing controller  303  provides the output enable signal OE 4  in the OED form to the scan unit  56 , and provides the output enable signal OE 2  in the OEB form to the scan unit  54 . Therefore, the scan unit  54  starts to operate according to the start wave STVB, the gate clock signal CPV, and the output enable signal OE 2  in the OEB form. The scan unit  56  also starts to operate according to the start wave STVD, the gate clock signal CPV, and the output enable signal OE 4  in the OED form. 
     As the start waves STVD and STVB will be transferred in the gate driver  401 , the pixels indirectly coupled to each scan line will reset data after a predetermined time from starting to load the display data. Moreover, it can be known from the aforementioned new panel architecture and new driving method that each sub-data line is not required to change the polarity in a same frame, and only needs to write the reset data once in a period T (as shown in  FIG. 6 ). Therefore, both the image data and the reset data can effectively utilize the limited charging time. In addition, as the output enable signals in the OED form and the OEB form assume the logic low level at different time points, the problem of loading wrong data into the pixels will not occur. In other words, the pixels that receive the display data will not receive the reset data RST, and the pixels that receive the reset data RST will not receive the display data. 
     Then,  FIG. 7  will be described below to illustrate the method for controlling the scan lines of the present invention more clearly.  FIG. 7  is a schematic view of the method for controlling the scan lines according to an embodiment of the present invention, showing the signal forms of the output enable signals received by the scan units  53 - 56  in a frame A. It is shown clearly in this figure that after the gate driver  401  receives the start wave STVD, the scan units  53 - 56  will receive the output enable signals in the OED form in a period of time, and each of the scan units will receive the start wave STVB after receiving the start wave STVD for a predetermined time Tbk. 
     The polarity control timing of  FIG. 8  may be obtained according to the operation method of  FIG. 6 .  FIG. 8  is a schematic view of a method for controlling polarities of data during the operation of the circuit of  FIG. 4 , in which POL 1  and POL 2  are polarity control signals of the source drivers  402  and  403 , respectively. In this figure, the polarity is changed at two positions, namely, the time point when an (n−1)th frame is shifted to an (n)th frame, marked by  801 , indicating that the polarity of the display data must be changed at this time point, and the time point when an (n−1)th reset frame is shifted to an (n)th reset frame, marked by  802 , indicating that the polarity of the reset data must be changed at this time. As the output polarities of the sub-data lines have been designed and planned when the panel architecture is established, the impulse system can be realized as long as a column inversion operation is performed on the display data or the reset data in the time of a same frame, and the scan line control method shown in  FIG. 7  is used as well. Thus, both the display data and the reset data can achieve the best image quality of dot inversion. 
     In view of the spirit of the embodiment described above, another display panel architecture can also be used to implement the driving method of the present invention, which is shown in  FIG. 9 .  FIG. 9  shows another embodiment of the display panel of  FIG. 3 , and shows the coupling relationship between the internal components of another display panel  304  and the timing controller  303 , and the image signal DATA 2  and the plurality of control signals CS sent to the display panel  304  by the timing controller  303 . Referring to  FIGS. 4 and 9 , the difference between the architecture of the two display panels is that the pixels are coupled in a 2-line inversion manner in  FIG. 9 . Taking the first four pixels in the column as shown in  FIG. 9  for example, the pixel  904  is coupled to the sub-data line D 1  and the scan line G 63   1 , the pixel  905  is coupled to the sub-data line D 1′  and the scan line G 63   2 , the pixel  906  is coupled to the sub-data line D 1  and the scan line G 63   3 , and the pixel  907  is coupled to the sub-data line D 1  and the scan line G 63   4 . The coupling relationship of other pixels is similar to the above description. Moreover, in the gate driver  901 , each scan unit is responsible for driving 8 rows of scan lines. For example, the scan unit  63  is responsible for driving the scan lines G 63   1 -G 63   8 . 
       FIG. 10  is a schematic view of the data reorganization method according to the embodiment of  FIGS. 3 and 9 . In  FIG. 10 , DE 1  is a data enable signal corresponding to the input image signal DATA 1 , DE 2  is a data enable signal corresponding to the image signal DATA 2 , CPV is the above gate clock signal, and OED and OEB are two signal forms of each of the output enable signals (OE 1 -OE 4 ). The input image signal DATA 1  has a plurality of image segments. Each of the image segments has the display data of the pixels coupled to two adjacent scan lines. For example, the image segment  1001  has the display data of the pixels coupled to the scan lines G 63   1  and G 63   2 , and the image segment  1002  has the display data of the pixels coupled to the scan lines G 63   3  and G 63   4 . 
     Referring to  FIGS. 5 and 10  together, it is known from the comparison between the figures that the data reorganization method of  FIG. 10  defines four image segments as one group, and inserts a reset data RST into each group of image segments. Thus, a time segment Tcycle originally having four batches of data is changed to have five batches of data, and the reset data RST is arranged after the image segments of each group. Therefore, the aforementioned arithmetic unit  301  must generate the positions to arrange the reset data RST according to such a counting relation. 
       FIG. 11  is a timing diagram of a part of signals of the circuit in  FIG. 9 , and shows the timing of the gate clock signal CPV, the two forms of output enable signals (OED and OEB), the gate start driving signal STV, and gate pulse signals between the scan lines. The gate start driving signals STV also has two start waves, which are denoted by STVD and STVB, respectively. Referring to  FIGS. 6 and 11  together, it is known from the comparison between the two figures that the timing of  FIG. 11  is to drive the scan lines coupled to each of the scan units in four batches, and drives  8  rows of scan lines at the same time when the reset data is written. 
     The polarity control timing of  FIG. 12  may be obtained according to the operation method of  FIG. 11 .  FIG. 12  is a schematic view of the method for controlling of polarities of data during the operation of the circuit of  FIG. 9 , in which POL 1  and POL 2  are polarity control signals of the source drivers  402  and  403  respectively. In this figure, the polarity is also changed at two positions, namely the time point when an (n−1)th frame is shifted to an (n)th frame, marked by  1201 , indicating that the polarity of the display data must be changed at this time, and the time point when an (n−1)th reset frame is shifted to an (n)th reset frame, marked by  1202 , indicating that the polarity of the reset data must be changed at this time. 
     Persons skilled in the art should understand that a single source driver can also be used to drive the data lines as shown in  FIG. 13 , in addition to using two source drivers to drive the data lines with as described in the above embodiments.  FIG. 13  shows yet another embodiment of the display panel of  FIG. 3 . The coupling manner of the pixels in a pixel matrix  1301  can be the same as the architecture of  FIG. 4  or  FIG. 9 . Likewise, each scan unit of the gate driver  1302  is responsible for driving B scan lines, where B is a positive integer. However, the source driver  1303  is responsible for driving all of the sub-data lines, i.e., D 1 -D N  and D 1′ -D N′ . No matter the coupling manner of the pixels of  FIG. 13  uses the architecture of  FIG. 4  or  FIG. 9  or not, the above driving method can be utilized, which will not be described herein again. 
     Though the display panel having 16×N, 32×N or B×N pixels is taken as an example in the above embodiments, users should understand that the present invention can also be implemented if the display panel includes M×N pixels. Here, M is also a positive integer, and B&lt;M. In addition, it is not limited to define every two or every four image segments as one group, users can define every K image segments as a group freely, where K is a positive integer. 
     Basic processes of the operation can be concluded according to the teaching of the above embodiments, as shown in  FIG. 14 .  FIG. 14  is a schematic view of the processes of the method for driving a display panel according to an embodiment of the present invention. First, an input image signal is provided (Step  1401 ). Next, the input image signal is divided into a plurality of image segments, and each of the image segments has display data of pixels coupled to two adjacent scan lines (Step  1402 ). Then, every K image segments are defined as a group (Step  1403 ). After that, a reset data is inserted into each group of the image segments (Step  1404 ). Then, the scan lines corresponding to a first group are driven in K batches according to the first start wave, and the two adjacent scan lines are driven each time. When the two adjacent scan lines are driven, display data of the pixels coupled to the (i)th scan line among the scan lines that have been driven is provided to the first sub-data lines, and display data of the pixels coupled to the (i+1)th scan line among the scan lines that have been driven is provided to the second sub-data lines (Step  1405 ). Afterwards, after a predetermined time from the first start wave, the scan lines corresponding to the first group are driven at the same time according to a second start wave, and the reset data is output to the first sub-data lines and the second sub-data lines (Step  1406 ). 
     To sum up, the present invention adopts a special display panel, in which each column of the data line includes two sub-data lines. Moreover, the present invention divides the input image signal into a plurality of image segments, and each of the image segments has display data of pixels coupled to two adjacent scan lines. Next, every K image segments are defined as a group, and a reset data is inserted into each group of the image segments, so as to form an image signal. After that, display data of a first group are written in K batches according to the first start wave. After a predetermined time from the first start wave, the scan lines corresponding to the first group are driven at the same time according to a second start wave, and the reset data is output to the first sub-data lines and the second sub-data lines. Thus, the present invention can provide double frame rate, and can effectively eliminate motion blur. In addition, as the polarities of the sub-data lines do not change in a frame, the present invention can reset the data of the pixels of several adjacent scan lines at the same time. 
     It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.