Patent Publication Number: US-2023145678-A1

Title: Semiconductor memory device and manufacturing method of semiconductor memory device

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application claims priority to PCT/JP2021/041085, filed Nov. 9, 2021, the entire content of which is incorporated herein by reference. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a semiconductor memory device and a manufacturing method of the semiconductor memory device. 
     2. Description of the Related Art 
     In recent years, there has been a demand for a memory element having a higher degree of integration and a higher performance in the development of the large scale integration (LSI) technology. 
     Typical planar metal-oxide-semiconductor (MOS) transistors have a channel that extends in a horizontal direction along the upper surface of a semiconductor substrate. In contrast, surrounding gate transistors (SGTs) have a channel that extends in a direction perpendicular to the upper surface of a semiconductor substrate (refer to, for example, Japanese Unexamined Patent Application Publication No. 2-188966 and Hiroshi Takato, Kazumasa Sunouchi, Naoko Okabe, Akihiro Nitayama, Katsuhiko Hieda, Fumio Horiguchi, and Fujio Masuoka: IEEE Transaction on Electron Devices, Vol. 38, No. 3, pp. 573-578 (1991)). For this reason, SGTs enable an increase in the density of semiconductor devices compared with planar MOS transistors. Such SGTs can be used as selection transistors to achieve a higher degree of integration of a dynamic random access memory (DRAM) (refer to, for example, H. Chung, H. Kim, H. Kim, K. Kim, S. Kim, K. W. Song, J. Kim, Y. C. Oh, Y. Hwang, H. Hong, G. Jin, and C. Chung: “4F2 DRAM Cell with Vertical Pillar Transistor (VPT),” 2011 Proceeding of the European Solid-State Device Research Conference, (2011)) to which a capacitor is connected, a phase change memory (PCM) (refer to, for example, H. S. Philip Wong, S. Raoux, S. Kim, Jiale Liang, J. R. Reifenberg, B. Rajendran, M. Asheghi and K. E. Goodson: “Phase Change Memory,” Proceeding of IEEE, Vol. 98, No. 12, December, pp. 2201-2227 (2010)) to which a resistance-change element is connected, a resistive random access memory (RRAM) (refer to, for example, K. Tsunoda, K. Kinoshita, H. Noshiro, Y. Yamazaki, T. Iizuka, Y. Ito, A. Takahashi, A. Okano, Y. Sato, T. Fukano, M. Aoki, and Y. Sugiyama: “Low Power and High Speed Switching of Ti-doped NiO ReRAM under the Unipolar Voltage Source of less than 3V,” IEDM (2007)), a magneto-resistive random access memory (MRAM) (refer to, for example, W. Kang, L. Zhang, J. Klein, Y. Zhang, D. Ravelosona, and W. Zhao: “Reconfigurable Codesign of STT-MRAM Under Process Variations in Deeply Scaled Technology,” IEEE Transaction on Electron Devices, pp. 1-9 (2015)) in which the orientation of magnetic spins is changed with a current to change the resistance, and the like. Furthermore, there is a DRAM memory cell (refer to M. G. Ertosun, K. Lim, C. Park, J. Oh, P. Kirsch, and K. C. Saraswat: “Novel Capacitorless Single-Transistor Charge-Trap DRAM (1T CT DRAM) Utilizing Electron,” IEEE Electron Device Letter, Vol. 31, No. 5, pp. 405-407 (2010)) that is constituted by a single MOS transistor and that includes no capacitor. The present application relates to a dynamic flash memory that can be constituted only by a MOS transistor and that includes neither a resistance-change element nor a capacitor. 
       FIGS.  8 A to  8 D  illustrate a write operation of the above-mentioned DRAM memory cell constituted by a single MOS transistor and including no capacitor,  FIGS.  9 A and  9 B  illustrate a problem in the operation thereof, and  FIGS.  10 A to  10 C  illustrate a read operation thereof. 
       FIGS.  8 A to  8 D  illustrate the write operation of the DRAM memory cell.  FIG.  8 A  illustrates a “1” write state. Here, the memory cell is formed in a silicon on insulator (SOI) substrate  100  and constituted by a source N+ layer  103  (hereinafter, a semiconductor region including a donor impurity at a high concentration will be referred to as “N+ layer”) to which a source line SL is connected, a drain N+ layer  104  to which a bit line BL is connected, a gate conductor layer  105  to which a word line WL is connected, and a floating body  102  of a memory cell  100   a , which is a MOS transistor. The DRAM memory cell is constituted by the single memory cell  110   a  and includes no capacitor. Note that a SiO 2  layer  101  of the SOI substrate is in contact with the floating body  102  directly under the floating body  102 . At the time of writing “1” in the memory cell constituted by the single memory cell  110   a , the memory cell  110   a  is operated in the saturation region. That is, a channel  107  for electrons extending from the source N+ layer  103  has a pinch-off point P and does not reach the drain N+ layer  104  to which the bit line BL is connected. In this manner, when both the bit line BL connected to the drain N+ layer  104  and the word line WL connected to the gate conductor layer  105  are set at high voltages, and the memory cell  110   a  is operated at a gate voltage that is about ½ of the drain voltage, the electric field strength becomes maximum at the pinch-off point P near the drain N+ layer  104 . As a result, accelerated electrons flowing from the source N+ layer  103  toward the drain N+ layer  104  collide with the lattice of Si, and electron-hole pairs are generated by the kinetic energy lost at this time (impact ionization phenomenon). Most of the generated electrons (not illustrated) reach the drain N+ layer  104 . Only a small number of very hot electrons jump over a gate oxide film  109  and reach the gate conductor layer  105 . Holes  106  that have been generated at the same time charge the floating body  102 . In this case, the generated holes contribute to an increment of the majority carrier because the floating body  102  is P-type Si. When the floating body  102  is filled with the generated holes  106  and the voltage of the floating body  102  becomes higher than that of the source N+ layer  103  by Vb or more, holes that are further generated are discharged to the source N+ layer  103 . Here, Vb is a built-in voltage of the PN junction between the floating body  102  of a P layer and the source N+ layer  103 , and is about 0.7 V.  FIG.  8 B  illustrates a state in which the floating body  102  is charged to saturation with the generated holes  106 . 
     Next, a “0” write operation of a memory cell  110   b  will be described with reference to  FIG.  8 C . The memory cell  110   a  in which “1” is written and the memory cell  110   b  in which “0” is written are present at random with respect to a common selected word line WL.  FIG.  8 C  illustrates a state in which a “1” write state is rewritten to a “0” write state. At the time of writing “0”, the voltage of the bit line BL is set to a negative bias, and the PN junction between the floating body  102  of the P layer and the drain N+ layer  104  is forward biased. As a result, the holes  106  that are generated in advance in the floating body  102  in the previous cycle flow into the drain N+ layer  104  connected to the bit line BL. Upon completion of the write operation, a state of two memory cells, which are the memory cell  110   a  filled with the generated holes  106  ( FIG.  8 B ) and the memory cell  110   b  in which the generated holes are discharged ( FIG.  8 C ), is obtained. The potential of the floating body  102  of the memory cell  110   a  filled with the holes  106  becomes higher than that of the floating body  102  in which the generated holes are not present. Accordingly, the threshold voltage of the memory cell  110   a  becomes lower than the threshold voltage of the memory cell  110   b . This state is illustrated in  FIG.  8 D . 
     Next, a problem in the operation of the memory cell constituted by the single MOS transistor will be described with reference to  FIGS.  9 A and  9 B . As illustrated in  FIG.  9 A , a capacitance C FB  of the floating body  102  is the sum of a capacitance C WL  between the gate to which the word line is connected and the floating body  102 , a junction capacitance C SL  of the PN junction between the floating body  102  and the source N+ layer  103  to which the source line is connected, and a junction capacitance C BL  of the PN junction between the floating body  102  and the drain N+ layer  104  to which the bit line is connected, and is expressed as follows. 
         C   FB   =C   WL   +C   BL   +C   SL   (1)
 
     Accordingly, when a word line voltage V WL  swings at the time of reading or at the time of writing, the voltage of the floating body  102  serving as a storage node (contact point) of the memory cell is also affected by this swing. This state is illustrated in  FIG.  9 B . When the word line voltage V WL  increases from 0 V to V ProgWL  at the time of writing, a voltage V FB  of the floating body  102  is increased from a voltage V FB1  in the initial state before the change in the word line voltage to V FB2  by a capacitive coupling with the word line. A voltage change amount ΔV FB  is expressed as follows. 
     
       
         
           
             
               
                 
                   
                     
                       
                         
                           Δ 
                           ⁢ 
                           
                             V 
                             FB 
                           
                         
                         = 
                           
                         
                           
                             V 
                             
                               FB 
                               ⁢ 
                               2 
                             
                           
                           - 
                           
                             V 
                             
                               FB 
                               ⁢ 
                               1 
                             
                           
                         
                       
                     
                   
                   
                     
                       
                         = 
                           
                         
                           
                             C 
                             WL 
                           
                           / 
                           
                             ( 
                             
                               
                                 C 
                                 WL 
                               
                               + 
                               
                                 C 
                                 BL 
                               
                               + 
                               
                                 C 
                                 
                                   S 
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                                   L 
                                 
                               
                             
                             ) 
                           
                           × 
                           
                             V 
                             ProgWL 
                           
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   2 
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     Here, β is a coupling ratio. 
       β= C   WL /( C   WL   +C   BL   +C   SL )  (3)
 
     In such a memory cell, C WL  has a large contribution ratio, and, for example, C WL :C BL :C SL =8:1:1. In this case, β=0.8. When the word line changes, for example, from 5 V at the time of writing to 0 V after completion of writing, the floating body  102  is subjected to an amplitude noise of as large as 5 V×β=4 V due to the capacitive coupling between the word line and the floating body  102 . 
     Accordingly, there has been a problem in that a potential difference margin is not provided sufficiently between the “1” potential and the “0” potential of the floating body  102  at the time of writing. 
       FIGS.  10 A to  10 C  illustrate a read operation.  FIG.  10 A  illustrates the “1” write state, and  FIG.  10 B  illustrates the “0” write state. Actually, however, even if Vb is written in the floating body  102  in “1” writing, when the word line returns to 0 V upon the completion of writing, the floating body  102  is lowered to a negative bias. Since writing of “0” brings a deeper negative bias, as illustrated in  FIG.  10 C , it is not possible to make the potential difference margin between “1” and “0” sufficiently large at the time of writing. This small operation margin is a major problem for the DRAM memory cell. In addition, the density of the DRAM memory cell needs to be increased. 
     SUMMARY OF THE INVENTION 
     In a capacitor-less single-transistor DRAM (gain cell), which is a memory device using an SGT, the capacitive coupling between a word line and an SGT body in the floating state is large, and there has been a problem in that, when the potential of the word line is made to swing at the time of reading or writing of data, the swing is directly transmitted as noise to the SGT body. This results in a problem of reading error or rewriting error of storage data and makes it difficult to put a capacitor-less single-transistor DRAM (gain cell) into practical use. It is necessary not only to solve the above problem but also to achieve a higher performance and density of the DRAM memory cell. 
     To solve the above problem, an aspect of the present invention is a manufacturing method of a semiconductor memory device that performs a data retention operation and a data erase operation, the data retention operation being an operation in which voltages to be applied to a first gate conductor layer, a second gate conductor layer, a third gate conductor layer, a first impurity layer, and a second impurity layer are controlled to retain, inside a semiconductor pillar, a group of holes or electrons that are generated by an impact ionization phenomenon or a gate induced drain leakage current and that serve as majority carriers in the semiconductor pillar, and the data erase operation being an operation in which the voltages to be applied to the first gate conductor layer, the second gate conductor layer, the third gate conductor layer, the first impurity layer, and the second impurity layer are controlled to remove, from the semiconductor pillar, the group of holes or electrons that serve as majority carriers in the semiconductor pillar, the manufacturing method comprising: 
     a step of stacking, on a substrate, from a bottom in a vertical direction, the first impurity layer, a first insulating layer, a first material layer, a second insulating layer, a second material layer, a third insulating layer, a third material layer, and a fourth material layer; 
     a step of forming a first hole whose bottom portion is on an upper surface or in an inside of the first impurity layer and that penetrates the first insulating layer, the first material layer, the second insulating layer, the second material layer, the third insulating layer, the third material layer, and the fourth material layer; 
     a step of forming the semiconductor pillar to be embedded in the first hole; 
     a step of removing the first material layer to form a second hole, removing the second material layer to form a third hole, and removing the third material layer to form a fourth hole; 
     a step of oxidizing an outermost surface of the semiconductor pillar exposed in the second hole to form a first gate insulating layer, oxidizing an outermost surface of the semiconductor pillar exposed in the third hole to form a second gate insulating layer, and oxidizing an outermost surface of the semiconductor pillar exposed in the fourth hole to form a third gate insulating layer; 
     a step of forming the first gate conductor layer embedded in the second hole and covering the first gate insulating layer, forming the second gate conductor layer embedded in the third hole and covering the second gate insulating layer, and forming the third gate conductor layer embedded in the fourth hole and covering the third gate insulating layer; and 
     a step of forming the second impurity layer connected to a top portion of the semiconductor pillar (first invention). 
     In the first invention, if one of the first impurity layer and the second impurity layer is connected to a source line, an other of the first impurity layer and the second impurity layer is connected to a bit line, and if one or two of the first gate conductor layer, the second gate conductor layer, and the third gate conductor layer are connected to a plate line, two others or an other of the first gate conductor layer, the second gate conductor layer, and the third gate conductor layer is connected to a word line, and a wiring conductor layer of the bit line is formed to extend in a direction orthogonal to a wiring conductor layer of the word line in plan view (second invention). 
     In the first invention, the manufacturing method further includes: 
     a step of removing part of the fourth material layer to expose the top portion of the semiconductor pillar; and 
     a step of forming a third impurity layer covering the exposed top portion of the semiconductor pillar, in which 
     the third impurity layer serves as the second impurity layer (third invention). 
     In the third invention, the manufacturing method further includes 
     a step of forming a fourth impurity layer on the top portion of the semiconductor pillar, in which 
     the third impurity layer and the fourth impurity layer form the second impurity layer (fourth invention). 
     In the first invention, the manufacturing method further includes a step of forming, on inner walls of the first hole, the second hole, and the third hole, a fourth gate insulating layer covering the first gate insulating layer, the second gate insulating layer, and the third gate insulating layer after the first gate insulating layer, the second gate insulating layer, and the third gate insulating layer are formed (fifth invention). 
     In the first invention, the fourth material layer includes at least one insulating layer (sixth invention). 
     In the first invention, the manufacturing method further includes: 
     a step of forming dummy semiconductor pillars in an outer side of a block region in which semiconductor pillars, each of which is the semiconductor pillar, are arranged two-dimensionally in plan view; and 
     a step of removing part of the first insulating layer, the first material layer, the second insulating layer, the second material layer, the third insulating layer, the third material layer, and the fourth material layer, the part sticking out to the outer side of the block region in plan view (seventh invention). 
     In the first invention, the fourth material layer is formed of a fourth insulating layer and a fifth material layer from the bottom, and the manufacturing method further includes a step of etching part or all of a periphery of the fifth material layer to expose the top portion of the semiconductor pillar (eighth invention). 
     In the first invention, the manufacturing method further includes a step of leaving the first gate conductor layer, the first gate conductor layer being continuous with a first gate conductor layer of a semiconductor pillar that is substantially identical with the semiconductor pillar and is formed adjacent to the semiconductor pillar (ninth invention). 
     In the ninth invention, the manufacturing method further includes a step of leaving the second gate conductor layer, the second gate conductor layer being continuous with a second gate conductor layer of the adjacent semiconductor pillar (tenth invention). 
     In the first invention, at least one of the first gate conductor layer, the second gate conductor layer, and the third gate conductor layer is formed to be divided into a plurality of parts in the vertical direction (eleventh invention). 
     In the first invention, at least one of the first gate conductor layer, the second gate conductor layer, and the third gate conductor layer is formed to be divided into a plurality of parts on a horizontal cross section (twelfth invention). 
     In the first invention, vertical-direction lengths of the first gate conductor layer, the second gate conductor layer, and the third gate conductor layer are formed to be equal (thirteenth invention). 
     To solve the above problem, a semiconductor memory device according to another aspect of the present invention includes: 
     a semiconductor base on a substrate, the semiconductor base standing vertically or extending horizontally to the substrate; 
     a first impurity layer and a second impurity layer at both ends of the semiconductor base; 
     a first gate insulating layer, a second gate insulating layer, and a third gate insulating layer surrounding part or all of a side surface of the semiconductor base between the first impurity layer and the second impurity layer sequentially from the first impurity layer toward the second impurity layer, the first gate insulating layer being in contact with or in proximity to the first impurity layer, the second gate insulating layer surrounding part or all of the side surface of the semiconductor base and being connected to the first gate insulating layer, and the third gate insulating layer surrounding part or all of the side surface of the semiconductor base, being connected to the second gate insulating layer, and being in contact with or in proximity to the second impurity layer; 
     a first gate conductor layer covering the first gate insulating layer; 
     a second gate conductor layer covering the second gate insulating layer; 
     a third gate conductor layer covering the third gate insulating layer; 
     a second insulating layer between the first gate conductor layer and the second gate conductor layer; and 
     a third insulating layer between the second gate conductor layer and the third gate conductor layer, wherein 
     the semiconductor memory device performs a memory write operation by performing an operation in which voltages to be applied to the first impurity layer, the second impurity layer, the first gate conductor layer, the second gate conductor layer, and the third gate conductor layer are controlled to cause an impact ionization phenomenon in the semiconductor base with a current flowing between the first impurity layer and the second impurity layer, an operation in which, out of a group of electrons or holes that are generated, the group of electrons is removed from the first impurity layer or the second impurity layer, and an operation in which part or all of the group of holes is left in the semiconductor base, and 
     the semiconductor memory device performs a memory erase operation in which the voltages to be applied to the first impurity layer, the second impurity layer, the first gate conductor layer, the second gate conductor layer, and the third gate conductor layer are controlled to discharge a left group of holes of the group of holes from one or both of the first impurity layer and the second impurity layer (fourteenth invention). 
     In the fourteenth invention, in the memory erase operation, a first PN junction between the semiconductor base and the first impurity layer and a second PN junction between the semiconductor base and the second impurity layer are kept in a reverse bias state, and a voltage of the first gate conductor layer is lower than a voltage of the second gate conductor layer (fifteenth invention). 
     In the fourteenth invention, if one of the first impurity layer and the second impurity layer is connected to a source line, an other of the first impurity layer and the second impurity layer is connected to a bit line, and 
     if one or two of the first gate conductor layer, the second gate conductor layer, and the third gate conductor layer are connected to a plate line, two others or an other of the first gate conductor layer, the second gate conductor layer, and the third gate conductor layer is connected to a word line (sixteenth invention). 
     In the sixteenth invention, a first gate capacitance is greater than a second gate capacitance, the first gate capacitance being a gate capacitance between the semiconductor base and one or more of the first gate conductor layer, the second gate conductor layer, and the third gate conductor layer connected to the plate line, and the second gate capacitance being a gate capacitance between the semiconductor base and one or more of the first gate conductor layer, the second gate conductor layer, and the third gate conductor layer connected to the word line (seventeenth invention). 
     In the fourteenth invention, at least one of the first gate conductor layer, the second gate conductor layer, and the third gate conductor layer is formed to be divided into a plurality of parts in a vertical direction (eighteenth invention). 
     In the fourteenth invention, at least one of the first gate conductor layer, the second gate conductor layer, and the third gate conductor layer is formed to be divided into a plurality of parts on a horizontal cross section (nineteenth invention). 
     In the fourteenth invention, vertical-direction lengths of the first gate conductor layer, the second gate conductor layer, and the third gate conductor layer are formed to be equal (twentieth invention). 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG.  1    is a structure diagram of a semiconductor memory device according to a first embodiment. 
         FIGS.  2 A to  2 C  are diagrams for describing an erase operation mechanism of the semiconductor memory device according to the first embodiment. 
         FIGS.  3 A to  3 C  are diagrams for describing a write operation mechanism of the semiconductor memory device according to the first embodiment. 
         FIGS.  4 AA to  4 AC  are diagrams for describing a read operation mechanism of the semiconductor memory device according to the first embodiment. 
         FIGS.  4 BA to  4 BC  are diagrams for describing the read operation mechanism of the semiconductor memory device according to the first embodiment. 
         FIGS.  5 AA to  5 AC  are structure diagrams for describing a manufacturing method of the semiconductor memory device according to the first embodiment. 
         FIGS.  5 BA to  5 BC  are diagrams for describing the manufacturing method of the semiconductor memory device according to the first embodiment. 
         FIGS.  5 CA to  5 CC  are diagrams for describing the manufacturing method of the semiconductor memory device according to the first embodiment. 
         FIGS.  5 DA to  5 DC  are diagrams for describing the manufacturing method of the semiconductor memory device according to the first embodiment. 
         FIGS.  5 EA to  5 EC  are diagrams for describing the manufacturing method of the semiconductor memory device according to the first embodiment. 
         FIGS.  5 FA to  5 FC  are diagrams for describing the manufacturing method of the semiconductor memory device according to the first embodiment. 
         FIGS.  5 GA to  5 GC  are diagrams for describing the manufacturing method of the semiconductor memory device according to the first embodiment. 
         FIGS.  5 HA to  5 HC  are diagrams for describing the manufacturing method of the semiconductor memory device according to the first embodiment. 
         FIGS.  5 IA to  5 IC  are diagrams for describing the manufacturing method of the semiconductor memory device according to the first embodiment. 
         FIGS.  5 JA to  5 JC  are diagrams for describing the manufacturing method of the semiconductor memory device according to the first embodiment. 
         FIGS.  5 KA to  5 KC  are diagrams for describing the manufacturing method of the semiconductor memory device according to the first embodiment. 
         FIGS.  5 LA to  5 LC  are diagrams for describing the manufacturing method of the semiconductor memory device according to the first embodiment. 
         FIGS.  5 MA to  5 MC  are diagrams for describing the manufacturing method of the semiconductor memory device according to the first embodiment. 
         FIGS.  6 A to  6 C  are diagrams for describing a manufacturing method of a semiconductor memory device according to a second embodiment. 
         FIGS.  7 AA to  7 AC  are diagrams for describing a manufacturing method of a semiconductor memory device according to a third embodiment. 
         FIGS.  7 BA to  7 BC  are diagrams for describing the manufacturing method of the semiconductor memory device according to the third embodiment. 
         FIGS.  8 A to  8 D  are diagrams for describing a write operation of a DRAM memory cell including no capacitor in the related art. 
         FIGS.  9 A and  9 B  are diagrams for describing a problem of the operation of the DRAM memory cell including no capacitor in the related art. 
         FIGS.  10 A to  10 C  are diagrams for describing a read operation of the DRAM memory cell including no capacitor in the related art. 
     
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Hereinafter, a structure, operation mechanisms, and a manufacturing method of a semiconductor memory device (hereinafter referred to as dynamic flash memory) according to embodiments of the present invention will be described with reference to the drawings. 
     First Embodiment 
     A structure, operation mechanisms, and a manufacturing method of a dynamic flash memory cell according to a first embodiment of the present invention will be described with reference to  FIGS.  1  to  5 MC . The structure of the dynamic flash memory cell will be described with reference to  FIG.  1   . In addition, a data erase mechanism, a data write mechanism, and a data read mechanism will be described with reference to  FIGS.  2 A to  2 C ,  FIGS.  3 A  to  3 C, and  FIGS.  4 AA to  4 BC , respectively. Furthermore, the manufacturing method of the dynamic flash memory will be described with reference to  FIGS.  5 AA to  5 MC . 
       FIG.  1    illustrates a structure of the dynamic flash memory cell according to the first embodiment of the present invention. On a substrate  1  (which is an example of “substrate” in the claims), there is a silicon semiconductor pillar  2  (which is an example of “semiconductor pillar” in the claims) (hereinafter the silicon semiconductor pillar will be referred to as “Si pillar”). In the Si pillar  2 , from the bottom, there are an N+ layer  3   a  (which is an example of “first impurity layer” in the claims), a P layer  7  (hereinafter, a semiconductor region containing an acceptor impurity is referred to as “P layer”), and an N+ layer  3   b  (which is an example of “second impurity layer” in the claims). The P layer  7  between the N+ layers  3   a  and  3   b  serves a channel region  7   a . To surround a lower portion of the Si pillar  2 , from the bottom, there are a first gate insulating layer  4   a  (which is an example of “first gate insulating layer” in the claims), a second gate insulating layer  4   b  (which is an example of “second gate insulating layer” in the claims), and a third gate insulating layer  4   c  (which is an example of “third gate insulating layer” in the claims). In addition, there are a first gate conductor layer  5   a  (which is an example of “first gate conductor layer” in the claims) to surround the first gate insulating layer  4   a , a second gate conductor layer  5   b  (which is an example of “second gate conductor layer” in the claims) to surround the second gate insulating layer  4   b , and a third gate conductor layer  5   c  (which is an example of “third gate conductor layer” in the claims) to surround the third gate insulating layer  4   c . Furthermore, the first gate conductor layer  5   a  and the second gate conductor layer  5   b  are isolated from each other by an insulating layer  6   a , and the second gate conductor layer  5   b  and the third gate conductor layer  5   c  are isolated from each other by an insulating layer  6   b . Thus, the dynamic flash memory cell is constituted by the N+ layers  3   a  and  3   b , the P layer  7 , the first gate insulating layer  4   a , the second gate insulating layer  4   b , the third gate insulating layer  4   c , the first gate conductor layer  5   a , the second gate conductor layer  5   b , and the third gate conductor layer  5   c.    
     As illustrated in  FIG.  1   , the N+ layer  3   a , the N+ layer  3   b , the first gate conductor layer  5   a , the second gate conductor layer  5   b , and the third gate conductor layer  5   c  are respectively connected to a source line SL (which is an example of “source line” in the claims), a bit line BL (which is an example of “bit line” in the claims), a first plate line PL 1 , a second plate line PL 2  (the first plate line PL 1  and the second plate line PL 2  are examples of “plate line” in the claims), and a word line WL (which is an example of “word line” in the claims). 
     Note that gate capacitances of the first gate conductor layer  5   a  connected to the first plate line PL 1  and the second gate conductor layer  5   b  connected to the second plate line PL 2  are desirably configured to be greater than a gate capacitance of the third gate conductor layer  5   c  connected to the word line WL. 
     Any or all of the first gate conductor layer  5   a , the second gate conductor layer  5   b , and the third gate conductor layer  5   c  may be divided into two or more in plan view, and may be operated synchronously or asynchronously each as conductive electrodes of the plate line or the word line. Any or all of the first gate conductor layer  5   a , the second gate conductor layer  5   b , and the third gate conductor layer  5   c  may be divided into two or more in a vertical direction, and divided plate lines and word lines may be operated synchronously or asynchronously. In these manners, dynamic flash memory operations may also be performed. 
     Alternatively, the N+ layer  3   a  may be connected to the bit line BL, and the N+ layer  3   b  may be connected to the source line SL. Alternatively, any two of the first gate conductor layer  5   a , the second gate conductor layer  5   b , and the third gate conductor layer  5   c  may be connected to the first plate line PL 1  and the second plate line PL 2 . Alternatively, any one or two of the first gate conductor layer  5   a , the second gate conductor layer  5   b , and the third gate conductor layer  5   c  may be connected to different word lines WL. 
     In addition to the first gate conductor layer  5   a  and the second gate conductor layer  5   b , a gate conductor layer connected to at least one of the first plate line PL 1  and the second plate lines PL 2  may be provided. The gate conductor layers may be operated synchronously or asynchronously each as conductive electrodes of the plate line. In these manners, dynamic flash memory operations may also be performed. 
     An erase operation mechanism will be described with reference to  FIGS.  2 A to  2 C . The channel region  7   a  between the N+ layers  3   a  and  3   b  is electrically isolated from the substrate  1  and serves as a floating body.  FIG.  2 A  illustrates a state in which a group of holes  10  generated by impact ionization in a previous cycle are stored in the channel region  7   a  before an erase operation. Then, as illustrated in  FIG.  2 B , at the time of the erase operation, the voltage of the source line SL is set to a negative voltage V ERA . Here, V ERA  is −3 V, for example. Accordingly, regardless of the value of the initial potential of the channel region  7   a , the PN junction between the channel region  7   a  and the N+ layer  3   a  serving as a source and connected to the source line SL becomes forward biased. As a result, the group of holes  10  stored in the channel region  7   a , generated by impact ionization in the previous cycle, are sucked into the N+ layer  3   a  of the source portion, and a potential V FB  of the channel region  7   a  becomes substantially V FB =V ERA +Vb. Here, Vb is the built-in voltage of the PN junction and is about 0.7 V. Therefore, if V ERA =−3 V, the potential of the channel region  7   a  is −2.3 V. This value corresponds to the potential state of the channel region  7   a  in the erase state. Therefore, if the potential of the channel region  7   a  of the floating body becomes negative, the threshold voltage of the N-channel MOS transistor of the dynamic flash memory cell is increased due to a substrate biasing effect. This results in a higher threshold voltage for the third gate conductor layer  5   c  connected to this word line WL, as illustrated in  FIG.  2 C . The erase state of this channel region  7   a  is logic storage data “0”. Note that the above-described conditions of voltages applied to the bit line BL, the source line SL, the word line WL, the first plate line PL 1 , and the second plate line PL 2  and the potential of the floating body are examples for performing the erase operation, and any other operation conditions may be employed by which the erase operation can be performed. 
       FIGS.  3 A to  3 C  illustrate a write operation of the dynamic flash memory cell. In  FIG.  3 A , for example, 0 V is input to the N+ layer  3   a  connected to the source line SL, 3 V is input to the N+ layer  3   b  connected to the bit line BL, 2 V is input to the first gate conductor layer  5   a  connected to the first plate line PL 1 , 2 V is input to the second gate conductor layer  5   b  connected to the second plate line PL 2 , and, 5 V is input to the third gate conductor layer  5   c  connected to the word line WL. As a result, as illustrated in  FIG.  3 A , a ring-shaped inverted layer Ra is formed in the channel region  7   a  inside the first gate conductor layer  5   a  connected to the first plate line PL 1  and the second gate conductor layer  5   b  connected to the second plate line PL 2 , and a dual-gate structure first N-channel MOS transistor region including the first gate conductor layer  5   a  and the second gate conductor layer  5   b  is operated in the saturation region. Accordingly, there is a pinch-off point P in the inverted layer Ra. On the other hand, a second N-channel MOS transistor region including the third gate conductor layer  5   c  connected to the word line WL is operated in the linear region. Accordingly, the channel region  7   a  inside the third gate conductor layer  5   c  connected to the word line WL does not include a pinch-off point, and an inverted layer Rb is entirely formed. In this case, the inverted layer Rb formed entirely inside the third gate conductor layer  5   c  connected to the word line WL substantially serves as a drain of the first N-channel MOS transistor region including the first gate conductor layer  5   a  and the second gate conductor layer  5   b.    
     As a result, the electric field becomes maximum in a first boundary region of the channel region  7   a  between the first N-channel MOS transistor region and the second N-channel MOS transistor region that are connected in series, and an impact ionization phenomenon occurs in this region. This region is a region on the source side when viewed from the second N-channel MOS transistor region including the third gate conductor layer  5   c  connected to the word line WL, and thus, this phenomenon is referred to as a source-side impact ionization phenomenon. As a result of this source-side impact ionization phenomenon, electrons flow from the N+ layer  3   a  connected to the source line SL toward the N+ layer  3   b  connected to the bit line BL. The accelerated electrons collide with lattice Si atoms, and electron-hole pairs are generated by the kinetic energy. Although some of the generated electrons flow into the first gate conductor layer  5   a , the second gate conductor layer  5   b , and the third gate conductor layer  5   c , most of the generated electrons flow into the N+ layer  3   b  connected to the bit line BL. At the time of writing “1”, electron-hole pairs may be generated by a gate induced drain leakage (GIDL) current, and the floating body (denoted by “FB” in  FIG.  4 BA ) may be charged with the generated group of holes (see, for example, E. Yoshida, and T. Tanaka: “A Capacitorless 1T-DRAM Technology Using Gate-Induced Drain-Leakage (GIDL) Current for Low-Power and High-Speed Embedded Memory,” IEEE Transactions on Electron Devices, Vol. 53, No. 4, pp. 692-697, Apr. 2006). Alternatively, the N-channel MOS transistor region of the first gate conductor layer  5   a  connected to the first plate line PL 1  may be operated in the linear region, the N-channel MOS transistor region of the second gate conductor layer  5   b  may be operated in the saturation region, and the N-channel MOS transistor region of the third gate conductor layer  5   c  may be operated in the linear region. In this case, the N-channel MOS transistor region of the first gate conductor layer  5   a  appears to be the source. Thus, the electric field intensity at the boundary between the first N-channel MOS transistor region and the second N-channel MOS transistor region can be further increased, and the impact ionization phenomenon can be made to occur at a low voltage. 
     As illustrated in  FIG.  3 B , the generated group of holes  10  serve as majority carriers in the channel region  7   a  and charge the channel region  7   a  to a positive bias. Since the N+ layer  3   a  connected to the source line SL is at 0 V, the channel region  7   a  is charged up to near the built-in voltage Vb (about 0.7 V) of the PN junction between the channel region  7   a  and the N+ layer  3   a  connected to the source line SL. If the channel region  7   a  is charged to a positive bias, the threshold voltages of the first N-channel MOS transistor region and the second N-channel MOS transistor region decrease due to the substrate bias effect. Accordingly, as illustrated in  FIG.  3 C , the threshold voltage of the second N-channel MOS transistor region connected to the word line WL decreases. This write state of the channel region  7   a  is assigned to logical storage data “1”. 
     At the time of the write operation, instead of the first boundary region, in a boundary region between the N+ layer  3   a  and the channel region  7   a  or a boundary region between the N+ layer  3   b  and the channel region  7   a , electron-hole pairs may be generated by the impact ionization phenomenon or the GIDL current, and the generated group of holes  10  may charge the channel region  7   a . Note that the above-described conditions of voltages applied to the bit line BL, the source line SL, the word line WL, the first plate line PL 1 , and the second plate line PL 2  are examples for performing the write operation, and any other voltage conditions may be employed by which the write operation can be performed. 
     A read operation of the dynamic flash memory cell will be described with reference to  FIGS.  4 AA to  4 BC . A read operation of the dynamic flash memory cell will be described with reference to  FIGS.  4 AA to  4 AC . As illustrated in  FIG.  4 AA , if the channel region  7   a  is charged up to the built-in voltage Vb (about 0.7 V), the threshold voltage decreases due to the substrate bias effect. This state is assigned to logical storage data “1”. As illustrated in  FIG.  4 AB , if a memory block selected before writing is in an erase state “0” in advance, the floating voltage V FB  of the channel region  7   a  is V ERA +Vb. A write state “1” is stored at random by the write operation. As a result, logical storage data of logical “0” and “1” is created for the word line WL. As illustrated in  FIG.  4 AC , the level difference between the two threshold voltages for the word line WL is utilized to perform reading by a sense amplifier. 
     With reference to  FIGS.  4 BA to  4 BC , a relationship among the gate capacitances of the first gate conductor layer  5   a , the second gate conductor layer  5   b , and the third gate conductor layer  5   c  at the time of the read operation of the dynamic flash memory cell and an operation related thereto will be described. The gate capacitance of the third gate conductor layer  5   c  is desirably designed to be smaller than the gate capacitances of the first gate conductor layer  5   a  and the second gate conductor layer  5   b . As illustrated in  FIG.  4 BA , vertical-direction lengths of the first gate conductor layer  5   a  and the second gate conductor layer  5   b  are set to be longer than a vertical-direction length of the third gate conductor layer  5   c  connected to the word line WL so as to make the gate capacitance of the third gate conductor layer  5   c  connected to the word line WL smaller than the gate capacitances of the first gate conductor layer  5   a  and the second gate conductor layer  5   b , connected to the first plate line PL 1  and the second plate line PL 2 , respectively.  FIG.  4 BB  illustrates an equivalent circuit of the single dynamic flash memory cell. 
       FIG.  4 BC  illustrates a relationship among coupling capacitances in the dynamic flash memory. Here, C WL  denotes a capacitance of the second gate conductor layer  5   b , C PL1  denotes a capacitance of the first gate conductor layer  5   a , C PL2  denotes a capacitance of the second gate conductor layer  5   b , C BL  denotes a capacitance of the PN junction between the channel region  7   a  and the N+ layer  3   b  serving as the drain, and C SL  denotes a capacitance of the PN junction between the channel region  7   a  and the N+ layer  3   a  serving as the source. As illustrated in  FIG.  4 BC , if the voltage of the word line WL swings, the change affects the channel region  7   a  as noise. A potential change ΔV FB  of the channel region  7   a  at this time is denoted by 
       Δ V   FB   =C   WL /( C   PL   +C   WL   +C   BL   +C   SL )× V   ReadWL   (4)
 
         C   PL   =C   PL1   +C   PL2 . 
     Here, V ReadWL  denotes the potential at the word line WL changed at the time of reading. As is apparent from Equation (4), if the contribution ratio of C WL  is made smaller than that of the total capacitance C PL +C WL +C BL +C SL  of the channel region  7   a , ΔV FB  decreases. If the vertical-direction lengths of the first and second gate conductor layers  5   a  and  5   b  connected to the plate lines PL 1  and PL 2 , respectively, are made longer than an vertical-direction length of the third gate conductor layer  5   c  connected to the word line WL, ΔV FB  can further decrease without reducing the degree of integration of the memory cell in plan view. Note that the above-described conditions of voltages applied to the bit line BL, the source line SL, the word line WL, the first plate line PL 1 , and the second plate line PL 2  and the potential of the floating body are examples for performing the read operation, and any other operation conditions may be employed by which the read operation can be performed. 
     The manufacturing method of the semiconductor memory device according to the first embodiment will be described with reference to  FIGS.  5 AA to  5 MC .  FIGS.  5 AA,  5 BA,  5 CA,  5 DA,  5 EA,  5 FA,  5 GA,  5 HA,  5 IA,  5 JA,  5 KA,  5 LA, and  5 MA  are plan views of a single memory cell of the semiconductor memory device.  FIGS.  5 AB,  5 BB,  5 CB,  5 DB,  5 EB,  5 FB,  5 GB,  5 HB,  5 IB,  5 JB,  5 KB,  5 LB, and  5 MB  are sectional views taken along line X-X′ in  FIGS.  5 AA,  5 BA,  5 CA,  5 DA,  5 EA,  5 FA,  5 GA,  5 HA,  51 A,  5 JA,  5 KA,  5 LA, and  5 MA , respectively.  FIGS.  5 AC,  5 BC,  5 CC,  5 DC,  5 EC,  5 FC,  5 GC,  5 HC,  51 C,  5 JC,  5 KC,  5 LC, and  5 MC  are sectional views taken along line Y-Y′ in  FIGS.  5 AA,  5 BA,  5 CA,  5 DA,  5 EA,  5 FA,  5 GA,  5 HA,  51 A,  5 JA,  5 KA,  5 LA, and  5 MA , respectively. A large number of such memory cells are arranged two-dimensionally in an actual memory device. 
     As illustrated in  5 AA to  5 AC, on a P-layer substrate  11  (which is an example of “substrate” in the claims), the following layers are formed from the bottom: an N+ layer  12  (which is an example of “first impurity layer” in the claims), a first insulating layer  13  (which is an example of “first insulating layer” in the claims), a silicon nitride (SiN) layer  14   a  (which is an example of “first material layer” in the claims), a second insulating layer  15   a  (which is an example of “second insulating layer” in the claims), a SiN layer  14   b  (which is an example of “second material layer” in the claims), a third insulating layer  15   b  (which is an example of “third insulating layer” in the claims), a SiN layer  14   c  (which is an example of “third material layer” in the claims), a fourth insulating layer  17 , a material layer  18  (the fourth insulating layer  17  and the material layer  18  are an example of “fourth material layer” in the claims). Note that the SiN layers  14   a ,  14   b , and  14   c  desirably have the same length in the vertical direction. 
     Subsequently, as illustrated in  FIGS.  5 BA to  5 BC , the first insulating layer  13 , the SiN layer  14   a , the second insulating layer  15   a , the SiN layer  14   b , the third insulating layer  15   b , the SiN layer  14   c , the fourth insulating layer  17 , and the material layer  18  are etched by photolithography and reactive ion etching (RIE) to form a hole  20  (which is an example of “first hole” in the claims) whose bottom portion is on the upper surface of the N+ layer  12  or inside thereof. 
     Subsequently, as illustrated in  FIGS.  5 CA to  5 CC , a Si pillar  22  (which is an example of “semiconductor pillar” in the claims) is formed in the hole  20  by epitaxial crystal growth. In this case, the Si pillar  22  is formed in the following manner: Si is grown by epitaxial crystal growth such that the upper surface position of Si protrudes from the upper surface position of the material layer  18 , and then the upper surface position of Si is polished by chemical mechanical polishing (CMP) such that Si is flush with the material layer  18 . 
     Subsequently, as illustrated in  FIGS.  5 DA to  5 DC , a donor impurity in the N+ layer  12  is made to diffuse into the Si pillar  22  by heat treatment to form an N+ layer  12   a.    
     Subsequently, as illustrated in  FIGS.  5 EA to  5 EC , the SiN layers  14   a ,  14   b , and  14   c  are removed to form a hole  23   a  (which is an example of “second hole” in the claims), a hole  23   b  (which is an example of “third hole” in the claims), and a hole  23   c  (which is an example of “fourth hole” in the claims). Note that a large number of Si pillars are arranged two-dimensionally in an actual memory device, and thus, these Si pillars are support bodies connected to the first insulating layer  13 , the second insulating layer  15   a , the third insulating layer  15   b , the fourth insulating layer  17 , and the material layer  18 . Thus, at the time of forming the holes  23   a ,  23   b , and  23   c , the second insulating layer  15   a , the third insulating layer  15   b , the fourth insulating layer  17 , and the material layer  18  are prevented from being bent or broken. In addition, by forming dummy Si pillars in an outer side of a block region in which the Si pillars are arranged two-dimensionally so as to prevent the second insulating layer  15   a , the third insulating layer  15   b , the fourth insulating layer  17 , and the material layer  18  from partly sticking out to an outer side of the dummy Si pillars in plan view, it is possible to prevent the second insulating layer  15   a , the third insulating layer  15   b , the fourth insulating layer  17 , and the material layer  18  from being damaged in a cleaning step or at the time of etching the SiN layers  14   a ,  14   b , and  14   c.    
     Subsequently, as illustrated in  FIGS.  5 FA to  5 FC , the exposed Si pillar  22  is oxidized to form a SiO 2  layer  25   a  (which is an example of “first gate insulating layer” in the claims), a SiO 2  layer  25   b  (which is an example of “second gate insulating layer” in the claims), a SiO 2  layer  25   c  (which is an example of “third gate insulating layer” in the claims), and a SiO 2  layer  25   d.    
     Subsequently, as illustrated in  FIGS.  5 GA to  5 GC , the SiO 2  layer  25   d  is removed by CMP. Then, a fifth insulating layer  28  is formed on the upper surface. In the holes  23   a ,  23   b , and  23   c , doped poly-Si layers  26   a ,  26   b , and  26   c  containing a large amount of donor or acceptor impurity are formed. In the formation of the doped poly-Si layers  26   a ,  26   b , and  26   c , a doped poly-Si layer is formed also on the fifth insulating layer  28 . This doped poly-Si layer is removed by CMP. Note that the doped poly-Si layers  26   a ,  26   b , and  26   c  are uniformly formed by making the lengths of the SiN layers  14   a ,  14   b , and  14   c  in the vertical direction equal in  FIGS.  5 AA to  5 AC . 
     Subsequently, as illustrated in  FIGS.  5 HA to  5 HC , a material layer  18   a  and a fifth insulating layer  28   a  that surround the Si pillar  22  and extend in the line X-X′ direction in plan view are formed by photolithography and RIE. 
     Subsequently, as illustrated in  FIGS.  5 IA to  5 IC , by using the material layer  18   a  and the fifth insulating layer  28   a  as etching masks, the fourth insulating layer  17 , the doped poly-Si layer  26   c , the third insulating layer  15   b , the doped poly-Si layer  26   b , the second insulating layer  15   a , and the doped poly-Si layer  26   a  are etched to form a fourth insulating layer  17   a , a doped poly-Si layer  26   aa  (which is an example of “first gate conductor layer” in the claims), a second insulating layer  15   aa , a doped poly-Si layer  26   ba  (which is an example of “second gate conductor layer” in the claims), a third insulating layer  15   ba , and a doped poly-Si layer  26   ca  (which is an example of “third gate conductor layer” in the claims). 
     Subsequently, as illustrated in  FIGS.  5 JA to  5 JC , a SiO 2  layer (not illustrated) is deposited entirely by chemical vapor deposition (CVD). Then, a SiO 2  layer  30  flush with the fifth insulating layer  28   a  is formed by CMP. 
     Subsequently, as illustrated in  FIGS.  5 KA to  5 KC , a portion of the material layer  18   a  and the fifth insulating layer  28   a  above the fourth insulating layer  17   a  is removed. Then, an upper portion of the SiO 2  layer  30  is removed to form a SiO 2  layer  30   a . Thus, a top portion of the Si pillar  22  is exposed. 
     Subsequently, as illustrated in  FIGS.  5 LA to  5 LC , an N+ layer  32  (which is an example of “second impurity layer” and “third impurity layer” in the claims) is formed by selective epitaxial crystal growth. 
     Subsequently, as illustrated in  FIGS.  5 MA to  5 MC , a SiO 2  layer  34  is formed on the N+ layer  32  and the fourth insulating layer  17   a . Then, a contact hole  35  is formed in the SiO 2  layer  34  on the N+ layer  32 . Then, a metal wiring layer  36  connected to the N+ layer  32  through the contact hole  35  and extending in the line Y-Y′ direction is formed. The N+ layer  12   a  is connected to the source line SL, the doped poly-Si layer  26   aa  is connected to the first plate line PL 1 , the doped poly-Si layer  26   ba  is connected to the second plate line PL 2 , the doped poly-Si layer  26   ca  is connected to the word line WL, and the metal wiring layer  36  is connected to the bit line BL. In this manner, the dynamic flash memory is formed on the P-layer substrate  11 . 
     Note that the Si pillar  22  may also be formed of another semiconductor layer. In addition, the doped poly-Si layers  26   a  and  26   b  may be formed of a conductor layer of another metal or alloy. 
     The first insulating layer  13 , the second insulating layer  15   a , the third insulating layer  15   b , and the fourth insulating layer  17  may be formed of an insulating layer of a single layer or a multi-layer of a SiO 2  layer, a SiN layer, or an alumina (Al 2 O 3 ) layer. In addition, since the fifth insulating layer  28  has a function of protecting the top portion of the Si pillar  22  from RIE as illustrated in  FIGS.  5 GA to  5 GC , another material layer, not only the insulating layer, may also be used. 
     Furthermore, the fourth insulating layer  17  and the material layer  18  may also be formed of a single insulating layer. In this case, in the step of exposing the top portion of the Si pillar  22  in  FIGS.  5 KA to  5 KC , an insulating layer with a thickness corresponding to the thickness of the fourth insulating layer  17  needs to be left. 
     The N+ layer  12   a  is formed by heat treatment in the step in  FIGS.  5 DA to  5 DC . However, the N+ layer  12   a  may also be formed in any of steps after the formation of the Si pillar  22 . In addition, although an N+ layer is not formed on the top portion of the Si pillar  22  in the step in  FIGS.  5 LA to  5 LC , an N+ layer may be formed on the top portion of the Si pillar  22  by, for example, additional heat treatment, ion implantation, low-temperature plasma doping, or the like. Furthermore, if the N+ layer is formed on the top portion of the Si pillar  22 , the N+ layer  32  may or may not be formed by selective epitaxial crystal growth. 
     Although the Si pillar  22  is formed by epitaxial crystal growth in  FIGS.  5 EA to  5 EC , but may also be formed by another method such as molecular beam epitaxy, atomic layer deposition (ALD), metal induced lateral crystallization (MILC), or metal-assisted solid-phase crystallization process (MSCP), or by some methods in combination. 
     In  FIGS.  5 GA to  5 GC , the doped poly-Si layers  26   a ,  26   b , and  26   c  are formed to surround the entire Si pillar  22  in plan view. However, each of the doped poly-Si layers  26   a ,  26   b , and  26   c  may also be formed to be divided into two parts in plan view. For example, the hole  20  is formed close to an adjacent hole (not illustrated) in the line X-X′ direction. Then, in the formation of the SiO 2  layers  25   a ,  25   b , and  25   c  in  FIGS.  5 FA to  5 FC , the SiO 2  layers  25   a ,  25   b , and  25   c  are formed to be in contact with a SiO 2  layer (not illustrated) surrounding an adjacent Si pillar  22  (not illustrated). Thus, the doped poly-Si layers  26   a ,  26   b , and  26   c  can be isolated in the line Y-Y′ direction and can extend in the line X-X′ direction. In this case, dynamic flash memory operations can be performed by driving, synchronously or asynchronously, divided conductor layers connected to the first plate line PL 1 , the second plate line PL 2 , or the word line WL. In addition, in  FIGS.  5 IA to  5 IC , a slit extending in the line X-X′ direction may be formed in the fifth insulating layer  28   a , the material layer  18   a , and the fourth insulating layer  17   a , and then, the doped poly-Si layers  26   aa ,  26   ba , and  26   ca  may be etched to divide the conductor layers to be connected to the first plate line PL 1 , the second plate line PL 2 , and the word line WL. 
     An embedded conductor layer such as a W layer may also be provided on the periphery of the N+ layer  12   a  in  FIGS.  5 AA to  5 MC . In addition, a metal wiring layer connected to the N+ layer  12   a  may be provided on the periphery of the block region of memory cells arranged two-dimensionally, and may be connected to the source line SL. 
     In addition, the dynamic flash memory operations are performed also in a structure in which the polarities of the conductivity types of the N+ layers  3   a  and  3   b  and the P layer  7  in  FIG.  1    are reversed. In this case, the majority carriers in the Si pillar  2  are electrons. Therefore, a group of electrons generated by impact ionization is stored in the channel region  7   a , and the “1” state is set. The same applies to  FIGS.  5 AA to  5 MC . 
     The dynamic flash memory element may have any structure that satisfies the condition that the group of holes  10  generated by the impact ionization phenomenon are retained in the channel region  7   a . For this, the channel region  7   a  may have a floating body structure isolated from the substrate  1 . Thus, the above-mentioned dynamic flash memory operations can be performed if, for example, the semiconductor base of the channel region is formed horizontally to the substrate  1  by using a GAA (Gate All Around: refer to, for example, J. Y. Song, W. Y. Choi, J. H. Park, J. D. Lee, and B-G. Park: “Design Optimization of Gate-All-Around (GAA) MOSFETs,” IEEE Transactions on Nanotechnology, vol. 5, no. 3, pp. 186-191, May 2006) technology and a Nanosheet technology (refer to, for example, N. Loubet, et al.: “Stacked Nanosheet Gate-All-Around Transistor to Enable Scaling Beyond FinFET,” 2017 IEEE Symposium on VLSI Technology Digest of Technical Papers, T17-5, T230-T231, June 2017), which types of SGTs. In addition, a device structure (refer to, for example, M. G. Ertosun, K. Lim, C. Park, J. Oh, P. Kirsch, and K. C. Saraswat: “Novel Capacitorless Single-Transistor Charge-Trap DRAM (1T CT DRAM) Utilizing Electron,” IEEE Electron Device Letter, Vol. 31, No. 5, pp. 405-407 (2010)) using an SOI may also be used. In this device structure, the bottom portion of the channel region is in contact with the insulating layer of the SOI substrate, and other portions of the channel region are surrounded by a gate insulating layer and an element isolation insulating layer. Also in this structure, the channel region has a floating body structure. In this manner, in the dynamic flash memory element provided by the present embodiment, the condition that the channel region has a floating body structure may be satisfied. Furthermore, also with a structure in which a Fin transistor (refer to, for example, H. Jiang, N. Xu, B. Chen, L. Zeng, Y. He, G. Du, X. Liu and X. Zhang: “Experimental investigation of self heating effect (SHE) in multiple-fin SOI FinFETs,” Semicond. Sci. Technol. 29 (2014) 115021 (7pp)) is formed on the SOI substrate, as long as the channel region has a floating body structure, the dynamic flash operations can be performed. Alternatively, GAA or Nanosheet elements can be stacked in multiple stages to form a dynamic flash memory element. Alternatively, dynamic flash memory cells, each of which is the dynamic flash memory cell illustrated in  FIG.  1   , can be stacked in multiple stages to form a dynamic flash memory element. 
     In the memory erase operation, a first PN junction between the channel region  7   a  and the N+ layer  3   a  and a second PN junction between the channel region  7   a  and the N+ layer  3   b  can be kept in a reverse bias state, and the voltage of the first gate conductor layer  5   a  can be lower than the voltage of the second gate conductor layer  5   b . Accordingly, a drift electric field that moves the group of holes  10  toward the N+ layer  3   a  occurs in the channel region  7   a  near the boundary between the first gate conductor layer  5   a  and the second gate conductor layer  5   b . The memory erase operation may be performed by using this operation. 
     In  FIGS.  5 MA to  5 MC , the N+ layer  12   a  is connected to the source line SL, the doped poly-Si layer  26   aa  is connected to the first plate line PL 1 , the doped poly-Si layer  26   ba  is connected to the second plate line PL 2 , and the doped poly-Si layer  26   ca  is connected to the word line WL. However, the N+ layer  12   a  may be connected to the source line SL, the doped poly-Si layer  26   aa  may be connected to the first plate line PL 1 , the doped poly-Si layer  26   ba  may be connected to the word line WL, and the doped poly-Si layer  26   ca  may be connected to the second plate line PL 2 . In this case, the coupling capacitance between the doped poly-Si layer  26   ba  connected to the word line WL and the metal wiring layer  36  connected to the bit line BL can be reduced. Similarly, the coupling capacitance between the doped poly-Si layer  26   ba  connected to the word line WL and the N+ layer  12   a  connected to the source line SL can be reduced. In addition, in the erase operation, for example, by making the voltage of the word line WL higher than that of the first plate line PL 1  and the second plate line PL 2 , the group of holes can be discharged to the source line SL and the bit line BL at a high speed. 
     In  FIG.  1   , any or all of the first gate conductor layer  5   a , the second gate conductor layer  5   b , and the third gate conductor layer  5   c  may be further divided in the vertical direction. In this case, the vertical-direction lengths of the first gate conductor layer  5   a , the second gate conductor layer  5   b , and the third gate conductor layer  5   c , any or all of which are divided, may be equal or different in accordance with operational optimization or manufacturing requirements. 
     The present embodiment offers the following features. 
     First Feature 
     When the dynamic flash memory cell performs a write or read operation, the voltage of the word line WL swings. At this time, the first and second plate lines PL 1  and PL 2  have a function of decreasing the capacitive coupling ratio between the word line WL and the channel region  7   a . As a result, the influence of a change in the voltage of the channel region  7   a  when the voltage of the word line WL swings can be significantly suppressed. Thus, the difference between the threshold voltages of the MOS transistor region of the word line WL indicating logical “0” and “1” can be increased. In addition, this leads to an improvement in retention characteristics and disturbance characteristics. This leads to an increase in the operation margin of the dynamic flash memory cell. 
     Second Feature 
     By connecting the second gate conductor layer  5   b  to the word line WL, the first gate conductor layer  5   a  to the first plate line PL 1 , and the third gate conductor layer  5   c  to the second plate line PL 2 , the word line WL is sandwiched between the upper second plate line PL 2  and the lower first plate line PL 1 . Thus, the second gate conductor layer  5   b  connected to the word line WL can be separated away from the N+ layer  3   a  connected to the source line SL and the N+ layer  3   b  connected to the bit line BL. This can reduce the coupling capacitance between the word line WL and the bit line BL and between the word line WL and the source line SL. Thus, the dynamic flash memory cell operations can be stabilized. In addition, in the erase operation, for example, by making the voltage of the word line WL higher than that of the first plate line PL 1  and the second plate line PL 2 , the group of holes can be discharged to the source line SL and the bit line BL at a high speed. 
     Third Feature 
     In this embodiment, the doped poly-Si layers  26   aa  and  26   ba  connected to the two first and second plate lines PL 1  and PL 2  are formed to be isolated from each other by the second insulating layer  15   aa . If the doped poly-Si layers  26   a ,  26   b , and  26   c  have equal thicknesses, the capacitance between the Si pillar  22  serving as a channel and the doped poly-Si layer  26   ca  connected to the word line WL is half the capacitance between the Si pillar  22  serving as a channel and the doped poly-Si layers  26   aa  and  26   ba  connected to the first and second plate lines PL 1  and PL 2 . As a result, the influence of a change in the voltage of the channel region  7   a  when the voltage of the word line WL swings can be significantly suppressed. In addition, in the step of embedding the doped poly-Si layers  26   a ,  26   b , and  26   c  in the holes  23   a ,  23   b , and  23   c  in  FIGS.  5 FA to  5 GC , by making the vertical-direction lengths of the holes  23   a ,  23   b , and  23   c  substantially equal, the uniform doped poly-Si layers  26   a ,  26   b , and  26   c  can be embedded. For example, if the second insulating layer  15   a  is omitted and the doped poly-Si layers  26   a  and  26   b  are formed of a single doped poly-Si layer, the hole  23   c  for the word line WL and a hole (not illustrated) for the plate line have different volumes. Thus, if the doped poly-Si layer is embedded in one of the holes optimally, voids may be generated in the doped poly-Si layer embedded in the other hole. This embodiment can prevent occurrence of such a problem more easily. Thus, in addition to the increase in the operation margin of the dynamic flash memory cell, manufacture is easier. 
     Fourth Feature 
     In the manufacturing method of the dynamic flash memory, the doped poly-Si layers  26   a  and  26   b  to be connected to the first and second plate lines PL 1  and PL 2  and the doped poly-Si layer  26   c  to be connected to the word line WL are defined by the thicknesses of the SiN layers  14   a ,  14   b , and  14   c  as illustrated in  FIGS.  5 AA to  5 AC . For example, if the SiN layers  14   a ,  14   b , and  14   c  are formed by CVD, the thicknesses thereof can be controlled with high precision by controlling the deposition time. Thus, variations of change in the voltage of the channel region  7   a  can be reduced, and as a result, the operation margin can be increased. 
     Second Embodiment 
     A manufacturing method of a semiconductor memory device according to a second embodiment will be described with reference to  FIGS.  6 A to  6 C .  FIG.  6 A  is a plan view of a single memory cell of the semiconductor memory device.  FIG.  6 B  is a sectional view taken along line X-X′ in  FIG.  6 A .  FIG.  6 C  is a sectional view taken along line Y-Y′ in  FIG.  6 A . A large number of such memory cells are arranged two-dimensionally in an actual memory device. 
     Substantially the same steps as those in  FIGS.  5 AA to  5 FC  are performed. Then, after the SiO 2  layers  25   a ,  25   b , and  25   c  are formed, as illustrated in  FIGS.  6 A to  6 C , in the holes  23   a ,  23   b , and  23   c , for example, hafnium oxide (HfO 2 ) layers  40   a ,  40   b , and  40   c  (which are each an example of “fourth gate insulating layer” in the claims) are formed by ALD. Subsequently, the doped poly-Si layers  26   a ,  26   b , and  26   c  are formed. Subsequently, substantially the same steps as those in  FIGS.  5 HA to  5 MC  are performed. In this manner, the dynamic flash memory is formed on the P-layer substrate  11 . Note that the HfO 2  layers  40   a ,  40   b , and  40   c  may be formed of another insulating material layer of a single layer or a multi-layer as long as the function of the gate insulating layer is implemented. In addition, the doped poly-Si layers  26   a ,  26   b , and  26   c  may be formed of a conductor layer of another metal or alloy. 
     The present embodiment offers the following features. 
     As illustrated in  FIGS.  5 AA to  5 MC , if the gate insulating layers are formed only of the SiO 2  layers  25   a ,  25   b , and  25   c , the SiO 2  layers  25   a ,  25   b , and  25   c  are thick, and an effective diameter of the Si pillar  22  serving as a channel is small. Thus, the volume of the channel storing the group of holes, which are a signal, decreases, which leads to a decrease in the operation margin. In contrast, in this embodiment, by forming the HfO 2  layers  40   a ,  40   b , and  40   c  in the outer sides of the SiO 2  layers  25   a ,  25   b , and  25   c , the decrease in the diameter of the Si pillar  22  can be suppressed, and a predetermined capacitance of the gate insulating layers can be formed. 
     Third Embodiment 
     A manufacturing method of a semiconductor memory device according to a third embodiment will be described with reference to  FIGS.  7 AA to  7 BC .  FIGS.  7 AA and  7 BA  are plan views of a single memory cell of the semiconductor memory device.  FIGS.  7 AB and  7 BB  are sectional views taken along line X-X′ in  FIGS.  7 AA and  7 BA .  FIGS.  7 AC and  7 BC  are sectional views taken along line Y-Y′ in  FIGS.  7 AA and  7 BA . A large number of such memory cells are arranged two-dimensionally in a memory cell region in an actual memory device. 
     Substantially the same steps as those in  FIGS.  5 AA  to  5 HC are performed. Subsequently, as illustrated in  FIGS.  7 AA to  7 AC , by using the material layer  18   a  and the fifth insulating layer  28   a  as etching masks, the fourth insulating layer  17  and the doped poly-Si layers  26   b  and  26   c  are etched to form the fourth insulating layer  17   a , the doped poly-Si layer  26   ba  (which is an example of “second gate conductor layer” in the claims), and the doped poly-Si layer  26   ca . In this case, the doped poly-Si layer  26   a  is not etched and is left to be continuous with the doped poly-Si layer  26   a  of an adjacent Si pillar (not illustrated). 
     Subsequently, substantially the same steps as those in  FIGS.  5 JA to  5 KC  are performed. Subsequently, as illustrated in  FIGS.  7 BA to  7 BC , an N+ layer  41  is formed on the top portion of the Si pillar  22  by, for example, plasma doping. Subsequently, substantially the same steps as those in  FIGS.  5 LA to  5 MC  are performed. Thus, while the doped poly-Si layer  26   aa  connected to the first plate line PL 1  in  FIGS.  5 MA to  5 MC  in the first embodiment has the same shape as the doped poly-Si layer  26   ca  connected to the word line WL in plan view, in this embodiment, as illustrated in  FIGS.  5 BA to  7 BC , the doped poly-Si layer  26   a  connected to the first plate line PL 1  is not etched and is left to be continuous with the doped poly-Si layer  26   a  of an adjacent Si pillar (not illustrated). In this manner, the dynamic flash memory is formed on the P-layer substrate  11 . 
     Note that the doped poly-Si layer  26   a  connected to the first plate line PL 1  is externally connected in a peripheral portion of the memory cell region. In this case, although it is necessary to form a contact hole, a wiring metal layer, and the like, they can be formed more easily than in the memory cell region. 
     The present embodiment offers the following features. 
     First Feature 
     In this embodiment, an etching process for the doped poly-Si layer  26   a  connected to the first plate line PL 1  is unnecessary in the memory cell region. Thus, the dynamic flash memory can be manufactured more easily. 
     Second Feature 
     In  FIGS.  7 AA to  7 AC , the doped poly-Si layer  26   ba  connected to the second plate line PL 2  has the same shape as the doped poly-Si layer  26   ca  connected to the word line WL in plan view. However, in the etching process using the material layer  18   a  and the fifth insulating layer  28   a  as etching masks, the doped poly-Si layer  26   b  is not necessarily etched. In this case, the doped poly-Si layer  26   b  connected to the second plate line PL 2  has the same shape as the doped poly-Si layer  26   a  connected to the first plate line PL 1 . Also in this manner, the dynamic flash memory is formed on the P-layer substrate  11 . In this case, an etching process for the doped poly-Si layers  26   a  and  26   b  is unnecessary in the memory cell region. Thus, the dynamic flash memory can be manufactured more easily. 
     Other Embodiments 
     In  FIG.  1   , the gate lengths of the first gate conductor layer  5   a  and the second gate conductor layer  5   b  are made greater than the gate length of the third gate conductor layer  5   c  so that the gate capacitances of the first gate conductor layer  5   a  connected to the first plate line PL 1  and the second gate conductor layer  5   b  connected to the second plate line PL 2  can be greater than the gate capacitance of the third gate conductor layer  5   c  connected to the word line WL. However, instead of making the gate lengths of the first gate conductor layer  5   a  and the second gate conductor layer  5   b  greater than the gate length of the third gate conductor layer  5   c , the thicknesses of the first gate insulating layer  4   a  and the second gate insulating layer  4   b  may be made smaller than the thickness of the third gate insulating layer  4   c . Alternatively, the permittivity of the first gate insulating layer  4   a  and the second gate insulating layer  4   b  may be made higher than the permittivity of the third gate insulating layer  4   c . Furthermore, by using any of the lengths of the first gate conductor layer  5   a , the second gate conductor layer  5   b , and the third gate conductor layer  5   c , and the thicknesses and permittivity of the first gate insulating layer  4   a , the second gate insulating layer  4   b , and the third gate insulating layer  4   c  in combination, the gate capacitances of the first gate conductor layer  5   a  and the second gate conductor layer  5   b  may be made greater than the gate capacitance of the third gate conductor layer  5   c . The same applies to the other embodiments. 
     In  FIG.  1   , the vertical-direction lengths of the first gate conductor layer  5   a  and the second gate conductor layer  5   b  are made greater than the vertical-direction length of the third gate conductor layer  5   c  connected to the word line WL so that C PL &gt;C WL  can be satisfied. However, addition of the first gate conductor layer  5   a  and the second gate conductor layer  5   b  suffices to decrease the capacitive coupling ratio (C WL (C PL +C WL +C BL +C SL )) of the word line WL to the channel region  7   a . As a result, the potential change ΔV FB  of the channel region  7   a  of the floating body decreases. The same applies to the other embodiments. 
     As the voltage of the first plate line PL 1  and the voltage of the second plate line PL 2  in the description of the embodiments, for example, a fixed voltage may be applied to both or one of the first plate line PL 1  and the second plate line PL 2  regardless of the operation mode. In addition, as the voltage of the first plate line PL 1  and the voltage of the second plate line PL 2 , for example, 0 V may be applied only at the time of an erase operation. Furthermore, as the voltage of the first plate line PL 1  and the voltage of the second plate line PL 2 , a fixed voltage or a temporally changing voltage may be applied as long as the voltage satisfies conditions for the dynamic flash memory operations. 
     The Si pillar  2  has a round shape in plan view in  FIG.  1   . However, the Si pillar  2  may have, for example, an elliptic shape or a shape elongated in one direction instead of a round shape. The same applies to the other embodiments. 
     A negative bias is applied to the source line SL at the time of the erase operation to discharge the group of holes in the channel region  7   a , which is a floating body, as described in the embodiments. However, the erase operation may be performed on the basis of other voltage conditions. 
     In  FIG.  1   , an N-type impurity layer or a P-type impurity layer having a different acceptor impurity concentration may be disposed between the N+ layer  3   a  and the P layer  7 . In addition, an N-type impurity layer or a P-type impurity layer may be disposed between the N+ layer  3   b  and the P layer  7 . The same applies to the other embodiments. 
     The N+ layers  3   a  and  3   b  in  FIG.  1    may be formed of Si or other semiconductor material layers containing a donor impurity. The N+ layer  3   a  and the N+ layer  3   b  may be formed of different semiconductor material layers. The same applies to the other embodiments. 
     The N+ layer  41  is formed by plasma doping on the top portion of the Si pillar  22  in  FIG.  7 BA to  7 BC . However, the N+ layer  41  may also be formed by, for example, ion implantation, heat diffusion from the N+ layer  32 , another method using a push-out effect of a donor impurity from a silicide layer containing the donor impurity, or the like. The same applies to the other embodiments. Furthermore, if the N+ layer  41  is formed, the N+ layer  32  may be omitted. 
     Si pillars  22 , each of which is the Si pillar  22  illustrated in  FIGS.  5 CA to  5 MC , may be arranged two-dimensionally in a square lattice, a diagonal lattice, a honeycomb pattern, a zigzag pattern, or a serrated pattern. The same applies to the other embodiments. 
     Instead of the P-layer substrate  11  in  FIG.  5 AA to  5 MC , SOI or a multilayer well may be used. The same applies to the other embodiments. 
       FIG.  1    illustrates an example in which each of the first gate conductor layer  5   a , the second gate conductor layer  5   b , and the third gate conductor layer  5   c  is formed of a single conductor material layer. However, each of the first gate conductor layer  5   a , the second gate conductor layer  5   b , and the third gate conductor layer  5   c  may be formed of a plurality of conductor layers. The same applies to the other embodiments. 
     Dynamic flash memory cells, each of which is the dynamic flash memory cell illustrated in  FIG.  1   , may be stacked in multiple stages in the vertical direction. The same applies to the other embodiments. 
     Various embodiments and modifications of the present invention are possible without departing from the broad spirit and scope of the present invention. The embodiments described above are illustrative examples of the present invention and do not limit the scope of the present invention. The embodiments and modifications can be appropriately combined. Furthermore, some of constituent features of the above embodiments may be omitted as required, and such embodiments still fall within the technical idea of the present invention. 
     According to the semiconductor memory device and the manufacturing method thereof according to the present invention, a high-density and high-performance dynamic flash memory can be obtained.