Patent Publication Number: US-8122328-B2

Title: Bose-Chaudhuri-Hocquenghem error correction method and circuit for checking error using error correction encoder

Description:
CROSS-REFERENCE TO RELATED PATENT APPLICATIONS 
     This application claims the benefit of Korean Patent Application No. 10-2007-0031929, filed on Mar. 30, 2007, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. 
     BACKGROUND 
     1. Technical Field 
     This disclosure relates to a semiconductor device, and more particularly, to a Bose-Chaudhuri-Hocquenghem (BCH) error correction method and circuit capable of correcting an error by using an encoder, thereby reducing a time, power, and the chip layout size required for error correction. 
     2. Description of the Related Art 
       FIG. 1  is a block diagram of a conventional semiconductor chip  100  having an error correcting circuit and a flash memory. Referring to  FIG. 1 , the semiconductor chip  100  includes a flash memory  120  and an error correcting circuit  140 . The semiconductor chip  100  may be connected to an external circuit (not shown) via a bus  200 . The error correcting circuit  140  includes a control circuit  141 , an error correction encoding circuit  142 , and an error correction decoding circuit  143 . 
     The error correction encoding circuit  142  receives normal data NDTA that is to be stored in flash memory cell array  120 , and generates corresponding parity data PDTA. The normal data NDTA and the parity data PDTA are respectively stored in a normal data region (not shown) and a parity data region (not shown) of the flash memory cell array  120 . 
     The error correction decoding circuit  143  detects and corrects an error in the normal data NDTA when reading the normal data NDTA from the memory cell array  120 . 
     In this case, error correction may be performed using the BCH (Bose-Chaudhuri-Hocquenghem) error correction algorithm. The BCH error correction algorithm is capable of correcting multiple bits of error in a data block, and thus has been widely applied to error correction of communication systems and memory systems. 
     In particular, in the case of a multi-level cell flash memory device that stores multiple bits in a cell, bit errors are likely to occur. Thus, error correction can be performed using the BCH error correction algorithm capable of correcting multiple bits of error. 
     Error correction using the BCH algorithm, and particularly, error correction using binary BCH 4148, 4096 code data (hereinafter referred to as “BCH code data”) will be described in detail. Such data is referred to as “BCH code data” or “BCH encoded data”; however, BCH encoded data may have a different length than BCH 4148, 4096 code data. 
     In general, in error correction using the BCH algorithm, BCH code data is generated using an error correcting encoder, and decoded using an error correcting decoder. Specifically, the BCH code data is decoded by calculating syndromes, constructing an error locator polynomial using the syndromes, and calculating the locations of error bits by obtaining the root of the error locator polynomial. In particular, in order to decode binary BCH code data, an error is corrected by inverting the bit value of an error bit. 
       FIG. 2  is a conceptual diagram illustrating the format of BCH code data CDATA. Referring to  FIG. 2 , the BCH code data CDTA consists of 512-byte normal data NDTA and 7-byte parity data PDTA. The parity data PDTA may consist of 48-bit parity and 4-bit dummy data. 
       FIG. 3  is a diagram illustrating the format of a plurality of pieces of normal data and a plurality of pieces of normal data that are stored within one page of a NAND flash memory. In particular,  FIG. 3  illustrates a page PAGE# with a 2K byte normal data region NStorage and 64 byte parity data region PStorage. Accordingly, four pieces of 512-byte normal data NDTA 0  through NDTA 3  and four pieces of parity data P 0  through P 3  that are respectively correspond to the normal data NDTA 0  through NDTA 3 , are stored in the page PAGE#. 
     The BCH code data CDTA is calculated by the error correction encoding circuit  143  of  FIG. 1 , using an operation on a Galois Field. The BCH code data CDTA consist of the elements of the following primitive polynomial on a Galois Field (GF) 2 13 :
 
 P ( x )= x   13   +x   4   +x   3   +x +1   (1)
 
     A generation polynomial for generating 4-bit BCH code data on the GF 2 13  is given by: 
     
       
         
           
             
               
                 
                   
                     
                       
                         
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     Random 512-byte normal data NDTA# [d 4095 , d 4094 , . . . , d 1 , d 0 ] may be expressed as the following polynomial:
 
 NDTA#=d   4095   x   4095   +d   4094   x+   4094   + . . . +d   1   x+d   0    (3)
 
     In this case, remainder bits [R 51 , R 50 , . . . , R 1 , R 0 ] are obtained as parity data by dividing the normal data NDTA# expressed in Equation (3) by the generation polynomial expressed in Equation (2). 
     A multiplication on the Galois Field may be performed using shift registers. A scheme for generating BCH code data using shift registers is illustrated in  FIG. 4 . 
       FIG. 4  is a diagram illustrating an example of the error correction encoding circuit  142 , illustrated in  FIG. 1 , which uses shift registers. Referring to  FIG. 4 , the error correction encoding circuit  142  includes a plurality of registers r 0  through r 51 , a plurality of XOR gates, and a switch SW. If 4096-bit normal data NDTA [4095:0] are sequentially input to the error correction encoding circuit  142 , the bits of parity data are respectively stored in the corresponding registers r 0  through r 51 . The error correction encoding circuit  142  generates 52-bit parity data PDTA[51:0], and parity data PDTA[51:0]) with the input 4096-bit normal data NDTA[4095:0] (that is, it opens a switch SW), and outputs 4148-bit BCH code data CDTA[4147:0]. 
     The error correction encoding circuit as illustrated in  FIG. 4  can be embodied in parallel. If the error correction encoding circuit has a parallel structure in which 8 bits are processed at a time, it is possible to produce BCH code data for 4096-bit normal data just within 512 cycles of time. 
     Referring to  FIGS. 1 and 3 , the error correction encoding circuit  142  may further include flag registers  145  for error correction, and an RAM block  144  that temporarily stores an “OK” flag, a “FAIL” flag, and data. 
     The error correction encoding circuit  142  stores first parity data P 1  for first normal data NDTA 1  in the RAM block  144 , and generates second parity data P 2  for second normal data NDTA 2 . If all the first parity data P 1  to fourth parity data are generated, 4 pieces of normal data NDTA 1  through NDTA 4  and the 4 pieces of the parity data P 1  through P 4  are stored in the flash memory cell array  120 . 
     After the BCH code data is stored, when a read command is received, it is determined whether an error is contained in data that is to be read. If an error exists, the error is corrected, and then, the data is output. Next, a BCH error correction method that uses an error correction decoding circuit when reading data from a memory cell array, will be described. 
       FIG. 5  is a schematic block diagram of the conventional error correction decoding circuit  143  of  FIG. 1 .  FIG. 6  is a flowchart illustrating a BCH error correction method  600  using the error correction decoding circuit  143  illustrated in  FIG. 5 . 
     Referring to  FIGS. 5 and 6 , the conventional error correction decoding circuit  143  includes a syndrome generator  143   a , a Berlekamp-Massey executing unit  143   b  a Chien search unit  143   c , and an error corrector  143   d . First, BCH code data CDTA′ stored is input to the syndrome generator  143   a  of the error correction decoding circuit  143  (operation S 610 ). For convenience of explanation, the BCH code data CDTA′ input to the error correction decoding circuit  143  will now be referred to as “received code data”. 
     Assuming that the received code data R(x) is [rn-1, rn-2, . . . , r1, r0], the received code data R(x) may be expressed as follows:
 
 R ( x )= r   n-1   x   n-1   +r   n-2   x   n-2   + . . . +r   1   x+r   0   ,r   j   εGF (2)   (4)
 
     The syndrome generator  143   a  produces syndromes, for error checking, from the received code data R(x) expressed in Equation (4) (operation S 620 ). The syndrome generator  143   a  may produce the syndrome using the following equation: 
     
       
         
           
             
               
                 
                   
                     
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     It is determined whether an error occurs based on the syndrome S j  illustrated in Equation (5) (operation S 630 ). If an error does not occur, the syndrome S j  has a value of 0. If an error occurs, the syndrome S j  has a value other than 0. 
     The syndrome generator  143   a  continuously performs a GF multiplication for calculating Equation (5). However, the syndrome generator  143   a  applies Equation (5) to each bit of the received code data R(x) expressed in Equation (4). Thus, in order to calculate syndromes for 4148-bit BCH code data, the syndrome generator  143   a  must perform the GF multiplication 4148 times. 
     Referring to  FIGS. 5 and 6 , when an error is detected, the Berlekamp-Massey executing unit  143   b  calculates an error locator polynomial Λ(α −i ) (operation S 640 ). The error locator polynomial Λ(α −i ) may be calculated using the Berlekamp-Massey algorithm. 
     Next, the Chien search unit  143   c  detects the location of an error bit (operation S 650 ). The location of the error bit may be detected using the Chien search algorithm. The Chien search algorithm detects the location of the error bit, based on whether the error locator polynomial Λ(α −i ) has a value of 0. In this case, i represents the location of the error bit. That is, if the error locator polynomial Λ(α −i ) has a value of 0, an error occurs in a bit ri of the received code data R(x) expressed in Equation (4). 
     Similarly to the syndrome generator  143   a , the Chien search unit  143   c  also performs a GF multiplication. Also, for a Chien search for 4148-bit BCH code data, the Chien search unit  143   c  performs the GF multiplication 4148 times. 
     If the Chien search reveals the location of the error bit, the error corrector  143   d  corrects the error (operation S 660 ). As described above, the BCH error correction method  600  using binary BCH code data corrects an error by inverting the bit value of an error bit. In the BCH error correction method  600 , if error correction is successfully performed, “OK” flag indicating this fact is output (operation S 670 ). If error correction fails, “FAIL” flag indicating this fact is output (operation S 680 ). 
       FIG. 7  is a timing diagram of the operation of the error correction decoding circuit  143  of  FIG. 5 . Referring to  FIGS. 5 and 7 , although only a short latency with 4 cycles is required to perform the SiBM (Simplified inverse-free Berlekamp-Massey) algorithm, each of syndrome generation and Chien search requires much time due to a 4148-bit long latency. As described above, according to a conventional BCH error correcting circuit and method, for syndrome generation and Chien search, a GF multiplication is needed to be performed a number of times corresponding to the bits of BCH code data. 
     That is, according to a conventional BCH error correcting circuit and method, a large amount of time and power are required to perform decoding for BCH error correction, thereby degrading the performance of a semiconductor memory device. 
     SUMMARY 
     An embodiment includes a Bose-Chaudhuri-Hocquenghem (BCH) error correction method capable of simplifying a BCH error correction process, thereby reducing a time and power necessary for error correction. 
     Another embodiment includes a BCH error correction circuit capable of simplifying a BCH error correction process, thereby reducing a time and power necessary for error correction. 
     Another embodiment includes a data storage system and a communication system capable of capable of simplifying a BCH error correction process, thereby reducing a time and power necessary for error correction. 
     Another embodiment includes a BCH error correction method including storing normal data and first parity data in a memory cell array, the normal data and first parity data forming BCH encoded data; generating second parity data from the stored normal data; comparing the first parity data with the second parity data; and checking for an error in the normal data in response to the comparing. 
     Another embodiment includes a BCH error correction method including encoding at least a portion of BCH encoded data; determining if an error exists in the BCH encoded data in response to the encoding; generating syndromes when it is determined that an error exists; detecting a location of the error using the syndromes; and inverting a bit value at the location of the error. 
     Another embodiment includes a BCH error correcting circuit including a memory cell array; an error correcting encoder coupled to the memory cell array configured to encode first normal data to generate first parity data, store the first normal data and the first parity data in the memory cell array, encode second normal data read from the memory cell array to generate second parity data, and generate a comparison signal by comparing the first parity data to the second parity data; and an error corrector coupled to the error correcting encoder and configured to correct an error in the second normal data in response to the comparison signal. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The above and other features and advantages will become more apparent by describing in detail embodiments with reference to the attached drawings in which: 
         FIG. 1  is a schematic block diagram of a semiconductor chip having an error correcting circuit and a flash memory; 
         FIG. 2  is a conceptual diagram illustrating the format of Bose-Chaudhuri-Hocquenghem (BCH) code data; 
         FIG. 3  is a diagram illustrating the format of a plurality of pieces of normal data and a plurality of pieces of parity data stored in one page of a NAND flash memory; 
         FIG. 4  is a diagram illustrating an example of an error correction encoding circuit, of  FIG. 1 , which uses shift registers; 
         FIG. 5  is a schematic block diagram of a conventional error correction decoding circuit illustrated in  FIG. 1 ; 
         FIG. 6  is a flowchart illustrating a BCH error correction method using the error correction decoding circuit of  FIG. 5 ; 
         FIG. 7  is a timing diagram of the operation of the error correction decoding circuit of  FIG. 5 ; 
         FIG. 8  is a flowchart illustrating a BCH error correction method, according to an embodiment; 
         FIG. 9  is a flowchart illustrating in detail an operation of error correcting illustrated in  FIG. 8 , according to an embodiment; 
         FIG. 10  is a flowchart illustrating a BCH error correction method, according to another embodiment; 
         FIG. 11  is a schematic block diagram of a BCH error correcting circuit according to an embodiment; 
         FIG. 12  is a block diagram illustrating in detail an error correcting encoder of  FIG. 11 , according to an embodiment; 
         FIG. 13  is a block diagram of an example of an error corrector of  FIG. 11 ; 
         FIG. 14  is a block diagram of another example of an error corrector of  FIG. 11 ; 
         FIG. 15  is a circuit diagram of a parallel syndrome generator according to an embodiment; 
         FIG. 16  is a circuit diagram of a parallel Chien search block according to an embodiment; 
         FIG. 17  is a circuit diagram of a syndrome generation and Chien search unit, of  FIG. 14 , which is a combination of the parallel syndrome generator of  FIG. 15  and the parallel Chien search unit of  FIG. 16 , according to an embodiment; and 
         FIG. 18  is a timing diagram illustrating a BCH error correcting operation of the syndrome generation and Chien search unit of  FIG. 17 , according to an embodiment. 
     
    
    
     DETAILED DESCRIPTION 
     Embodiments will now be described more fully with reference to the accompanying drawings. Like reference numerals denote like elements throughout the drawings. 
       FIG. 8  is a flowchart illustrating a Bose-Chaudhuri-Hocquenghem (BCH) error correction method  800  according to an embodiment.  FIG. 11  is a schematic block diagram of a BCH error correcting circuit  1100  according to an embodiment. 
     Referring to  FIGS. 8 and 11 , the BCH error correcting circuit  1100  includes an error correcting encoder  1120  and an error corrector  1140 . The error correcting encoder  1120  is configured to receive normal data NDTA that is to be written to a memory cell array  1160 , and generate first parity data PDTA 1  (operation S 810 ). The error correcting encoder  1120  is configured to write the normal data NDTA and the first parity data PDTA 1  to the memory cell array  1160  (operation S 820 ). In this case, the memory cell array  1160  may be a flash memory, and particularly, a multi-level cell NAND flash memory cell array. 
       FIG. 12  is a block diagram illustrating in detail the error correcting encoder  1120  of  FIG. 11 . Referring to  FIGS. 8 ,  11 , and  12 , the error correcting encoder  1120  includes an encoding unit  1122 , a comparing unit  1124 , and a checking unit  1126 . In the BCH error correction method  800  according to an embodiment, second parity data PDAT 2  is generated from normal data NDTA′ that was read from the memory cell array  1160  (operation S 830 ). 
     The encoding unit  1122  is capable of producing the second parity data PDTA 2  by encoding the normal data NDTA′ stored in the memory cell array  1160 . For example, the normal data NDTA′[d 4095 ′, d 4094 ′, . . . , d 1 ′, d 0  ′] input to the encoding unit  1122  is encoded again so as to produce the second parity data PDTA 2  [R 51 ′, R 50 ′, . . . , R 1 ′, R 0 ′]. 
     The comparing unit  1124  is configured to compare the first parity data PDTA 1  with the second parity data PDTA 2  (operation S 840 ). The checking unit  1126  is configured to check an error using the result of comparison XCOM (operation S 850 ). 
     That is, according to an embodiment, in the BCH error correction method  800  and the BCH error correcting circuit  1100 , the error correcting encoder  1120  can be used to determine whether an error is contained in the normal data NDTA′ written to the memory cell array  1160  (operation S 850 ). 
     In an example, in the BCH error correction method  800  and the BCH error correcting circuit  1100 , it is determined whether the first parity data PDTA 1  is identical to the second parity data PDTA 2 . When PDTA 1  and PDTA 2  are not the same, it is determined that no error occurs in the normal data NDTA′. In detail, the result of comparison XCOM of the first parity data PDTA 1  with the second parity data PDTA 2  may be represented as the difference [R 51 −R 51 ′, R 50 −R 50 ′, . . . , R 1 −R 1 ′, R 0 −R 0 ′] between the first parity data PDTA 1  [R 51 , R 50 , . . . , R 1 , R 0 ] and the second parity data [R 51 ′, R 50 ′, . . . , R 1 ′, R 0 ′]. 
     If the result of comparison XCOM has a value other than 0, that is, when an error occurs, the checking unit  1126  transmits an error signal XERR to the error corrector  1140 . The error corrector  1140  corrects the error in the normal data NDTA′ written to the memory cell array  1160 , in response to the error signal XERR (S 860 ). 
       FIG. 9  is a flowchart illustrating in detail of operation S 860  of correcting an error, of  FIG. 8 , according to an embodiment.  FIG. 13  is a block diagram of an error corrector  1140   a  that is an example of the error corrector  1140  of  FIG. 11 . Referring to  FIGS. 9 and 13 , the error corrector  1140   a  includes a syndrome generator  1141 , an error location search unit  1143 , and an error bit correcting unit  1145 . The syndrome generator  1141  is configured to generate a syndrome SYND from the result of comparison XCOM, in response to the error signal XERR (operation S 861 ). A formula for generating a syndrome is as illustrated in Equation (5) but the total number of syndromes generated according to the formula is different from when using Equation (5). 
     As described above, the result of comparison XCOM is [R 51 −R 51  ′, R 50  −R 50  ′, . . . , R 1 −R 1 ′, R 0 −R 0 ′], that is, it is just a 52 bit long. Thus, in a BCH error correction method according to an embodiment, syndromes for only 52 bits are generated. In contrast, a conventional BCH error correction method, syndromes are generated by applying Equation (5) to all the bits of 4148-bit BCH code data CDTA (see  FIGS. 1 and 6 ). Accordingly, an amount of time required for error correction (see  FIGS. 8 and 11 ) in a BCH error correction method according to an embodiment is reduced relative to the conventional BCH error correction method. 
     A BCH error correction method and circuit according to an embodiment are also capable of generating in parallel a plurality of syndromes for multiple bits. A parallel syndrome generator according to an embodiment is illustrated in  FIG. 15 . 
     A BCH error correction method and circuit according to an embodiment are capable of generating a plurality of syndromes in parallel since the presence of an error is checked using an error correcting encoder with shift registers (see  FIG. 4 ). As described above, an encoder using shift registers makes it easy to perform parallel processing, thereby allowing an error to be detected in units of bytes. 
     Accordingly, the BCH error correction method and circuit according to the current embodiment are capable of performing parallel processing for syndrome generation, thereby increasing the performance of error correcting and the efficiency of power. 
     Referring to  FIGS. 9 and 13 , the error location search unit  1143  is configured to calculate the location of an error bit using syndromes SYND (S 862 ). In this case, the location of the error bit may be calculated using the Berlekamp-Massey algorithm and the Chien search algorithm. A method of searching for the location of an error bit using the Berlekamp-Massey algorithm and the Chien search algorithm has been described above. 
     Further, the BCH error correction method and circuit according to an embodiment are capable of performing in parallel the Chien search algorithm for multiple bits. An example of a parallel Chien search block is illustrated in  FIG. 16 . 
     Similarly to the parallel syndrome generator of  FIG. 15 , the parallel Chien search block illustrated in  FIG. 16  is also capable of performing a Chien search in parallel, thereby increasing the performance of error correcting and the efficiency of power. 
       FIG. 14  is a block diagram of an error corrector  1140   b  that is another example of the error corrector  1140  of  FIG. 11 . Referring to  FIG. 14 , according to an embodiment, the error corrector  1140   b  includes a syndrome generation-Chien search unit  1142  that is a combination of the syndrome generator  1141  of  FIG. 13  and a Chien search unit (not shown). An example of the syndrome generation and Chien search unit  1142 , of  FIG. 16 , which is a combination of the parallel syndrome generator  1141  of  FIG. 15  and the parallel Chien search unit  1143  of  FIG. 16 , is illustrated in  FIG. 17 . 
     As described above, both a syndrome generator and a Chien search unit perform a multiplication on a GF. However, according to a BCH error correcting method and circuit according to an embodiment a reduced number of cycles of time is required to generate syndromes, and therefore, it is possible to generate syndromes by time-sharing with the Chien search unit without additional hardware for syndrome generation. Accordingly, it is possible to reduce the layout size of the chip. 
       FIG. 18  is a timing diagram illustrating BCH error correcting using the syndrome generation and Chien search unit  1142  of  FIG. 17 , according to an embodiment. Referring to  FIG. 18 , when BCH error correcting is processed in parallel with respect to 8 bits, that is, when BCH error correcting is performed in units of bytes, only 519 cycles of time is required. Also, a latency required for syndrome generation is still shorter than as illustrated in  FIG. 7 . 
     As described above, in a BCH error correcting method and circuit according to an embodiment, since the presence of an error is detected using an encoder, it is easy to simplify the construction of a circuit for generating syndromes, a latency required for syndrome generation is short, and it is possible to process in parallel multiple bits. Accordingly, it is possible to reduce a time, power, and the chip layout size for error correction. 
     Referring to  FIGS. 9 and 13 , the error bit correcting unit  1145  is configured to correct an error by inverting the bit value of the bit of error (operation S 863 ). The error bit correcting unit  1145  is configured to output an “OK” flag and corrected normal data NDTA″ when the error is corrected (operation S 865 ), and output a “FAIL” flag when the error is not corrected (operation S 866 ). 
     Referring to  FIGS. 8 and 11 , if the result of comparison XCOM of first parity data PDTA 1  and second parity data PDTA 2  has a value of 0, that is, if an error does not exist, the error corrector  1140  outputs normal data NDTA′ stored in memory cell array  1160 . 
       FIG. 10  is a flowchart illustrating a BCH error correction method  1000  according to another embodiment. Referring to  FIG. 10 , the BCH error correction method  1000  includes checking the presence of an error using an encoder (operation Sl 010 ), generating syndromes when the error exists (operation S 1030 ), detecting the location of the bit of error using the syndromes (operation S 1040 ), and correcting the error by inverting the bit value of the error bit (operation S 1050 ). Operation S 1010  can be similar to operations S 810  through S 850  of  FIG. 8 . 
     As described above, according to an embodiment, in a BCH error correction method and circuit, the presence of an error is checked using an encoder, thereby simplifying the construction of a circuit for syndrome generation, reducing a latency required for syndrome generation, and allowing multiple bits to be processed in parallel. Accordingly, it is possible to reduce a time, power, and the chip layout size for error correction. 
     While embodiments have been particularly shown and described with reference to the drawings, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the following claims.