Patent Publication Number: US-2009231004-A1

Title: Digital cycle controlled oscillator and method for controlling the same

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The invention relates to an oscillator, and more particularly to a digital controlled oscillator. 
     2. Description of the Related Art 
     With advances in deep-submicron technologies, the demand for high-performance and short time-to-market integrated circuits has dramatically grown recently. Scalable microprocessor and graphic-processor systems could cost-effectively port to advanced technologies to increase the clocking rate, lower the power dissipations, and reduce design turn-around time. The synchronization among IC modules is an important issue. Thus, considerable efforts have been focused on high-performance digital interface circuits to communicate with these digital systems. Phase-locked loops (PLLs) have been widely used in many high-speed microprocessors and memories. The traditional analog PLL generally has better jitter and skew performances, but it is process-dependent and needs a long design time. Conversely, the digital PLL can be migrated over different processes. Moreover, with benefits from scaling CMOS technologies, the digital PLL has a lower supply voltage and the potential for good power management. To apply a digital PLL in various clock-generation circuits or phase-alignment circuits, the operating frequency range should be as large as possible to meet different product&#39;s specifications. Furthermore, the wide-range PLL should tolerate wide variations of clock frequency, process, and temperature. 
       FIG. 1  is a schematic diagram of a conventional DCO (digital-controlled-oscillator). The conventional oscillator  10  comprises a delay line  12  and a phase selector  14 . Phase selector  14  controls delay units  121 ˜ 12   n.    
     The highest operating frequency of a PLL is limited by the bandwidth of a single delay unit ( 121 - 12   n ) used in the DCO (digital-controlled-oscillator) while the lowest operating frequency is restricted by total delay of the delay line  12 . The maximum operating frequency range of this DCO could be expressed as 
     
       
         
           
             
               
                 
                   
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     where T is the total delay of delay line  12 , T l  is the intrinsic delay when the value of all control bits are low, and Cmax is the maximum number of delay units  121 - 12   n  used in the delay line  12 . As indicated from Eq. (1), the operating frequency range trades off the hardware complexity and the timing resolution. One may either increase C or td to extend the operating frequency range. However, the former will increase the hardware complexity and the later will decrease the timing resolution. In order to meet the maximum and the minimum speed requirement at the same time, a conventional digital PLL demands a DCO composed of high-bandwidth delay units  121 - 12   n . However, to realize such a DCO by a reasonable chip area, the tradeoff between bandwidth of a single delay unit and length of the delay line  12  will substantially limit the ratio of maximum to minimum operating frequency. 
     BRIEF SUMMARY OF THE INVENTION 
     According to one embodiment of the present invention, an oscillator is disclosed. The oscillator comprises a cycle controller and a re-cycle delay line module. The cycle controller generates a cycle control signal. The re-cycle delay line module produces a periodic signal. The re-cycling delay line module performs a re-cycling operation. The number of re-cycling in the re-cycling operation is determined based on the cycle control signal. 
     According to another embodiment of the present invention, an oscillator is disclosed. The oscillator comprises a re-cycle delay line module and a second delay line. The re-cycle delay line module performs a re-cycling operation. The number of re-cycling in the re-cycling operation is determined based on a cycle control signal. The re-cycle delay line module comprises a first delay line. 
     According to another embodiment of the present invention, a method for producing a periodic signal is disclosed. The method comprises the following steps. A recycling operation is performed on a first close loop of a first delay line when a re-cycling mode is enabled. A second delay line is connected to the first delay line and a second close loop is formed when the re-cycling mode is disabled. The periodic signal is outputted from the second close loop. 
     A detailed description is given in the following embodiments with reference to the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein: 
         FIG. 1  is a schematic diagram of a conventional oscillator; 
         FIG. 2  shows a block diagram of an exemplary DCCO (digital-cycle-controlled oscillator); 
         FIG. 3  shows an embodiment of a DCCO; 
         FIG. 4  shows the simulated results when M=5; and 
         FIG. 5  shows the simulated results when M=100. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims. 
       FIG. 2  shows a block diagram of an exemplary DCCO (digital-cycle-controlled oscillator). The DCCO  20  comprises a cycle controller  202 , a re-cycle delay line module  204 , a fine delay line  206 , and a delay adjustment unit  208 . The re-cycle delay line module  204  is used to increase the ratio of maximum to minimum operating range of the DCCO  20 . The fine delay line  206  is used to fine-tune or make an interpolation of the operating frequency of the DCCO  20 . In one embodiment, the fine delay line  206  and the delay adjustment unit  208  can be omitted if a fine resolution is not desired. 
       FIG. 3  shows an embodiment of a DCCO. The DCCO  30  is an embodiment of the block diagram of the DCCO  20  shown in  FIG. 2 . In this embodiment, the re-cycle delay line module  204  ( FIG. 2 ) is implemented by a re-cycle delay line  302 , a first selection unit  308 , and a second selection unit  310  ( FIG. 3 ). The fine delay line  206  ( FIG. 2 ) is the same as the fine delay line  304  ( FIG. 3 ). The delay adjustment unit  208  ( FIG. 2 ) is implemented by a delta-sigma interpolator  306 . The delay unit in the re-cycle delay line  302  can be re-used to increase the operating frequency range with small hardware overhead. The re-use process is a re-cycling operation. The re-cycling operation is performed on a first close loop formed by the re-cycle delay line  302  and the path  316 . Thus, the bandwidth of the delay unit in the re-cycle delay line can be as large as possible to achieve the maximum operating frequency requirement while the lowest operating frequency requirement can be accomplished by increasing the times of re-use. The times of re-use are the number of re-cycling. The number of re-cycling is determined by the cycle controller  202 . After the re-cycling operation, the re-cycle delay line  302  is connected to the fine delay line  304 . The re-cycling delay line  302 , the fine delay line  304 , and the path  318  form a second close loop. The fine delay line  304  can compensate the residue delay compared with the desired operating period. The interpolator  306  can further increase timing resolution. Output signal of the DCCO  30  is provided on the node O 2 . The operating frequency range of the proposed DCCO  30  can be expressed by 
     
       
         
           
             
               
                 
                   
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     where T is the total delay of delay line (including the re-cycle delay line  302  and the fine delay line  304 ), T l  is the intrinsic delay when the value of all control bits are low, M is times of re-use, C max  is the number of delay units used in the re-cycle delay line  302 , C 1  is number of delay units used in the fine delay line  304 , and C 2  is the interpolating factor. The ratio of the maximum operating frequency range of the proposed DCCO  30  to that of a conventional digital DCO (digital-controlled-oscillator) could be approximated as 
     
       
         
           
             
               
                 
                   
                     
                       
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     Since the hardware complexity of the controller is proportional to the operating frequency range, the overall hardware complexity of the proposed DCCO  30  could be significantly reduced compared with a conventional digital DCO at a given operating frequency range and timing resolution. 
     In this embodiment, the first selection unit  308  is implemented by a first multiplexer and the second selection unit  310  is implemented by a second multiplexer. The DCCO  30  can further include a D flip-flop  312 . The re-cycle delay includes the delays introduced by two multiplexers ( 308  and  310 ), Cmax delay units ( 302 ), and one DFF  312 . The bandwidth of the delay unit can be designed to be as large as possible to achieve the maximum operating frequency requirement. In this embodiment, the cycle controller  202  ( FIG. 2 ) can be implemented by a counter  314 . The counter  314  generates a cycle control signal B. The cycle control signal B controls the multiplexers ( 308 , and  310 ) to select the signal on nodes O 1  or O 2  into the re-cycle delay line  302 . For example, when B=1, a re-cycle mode is enabled. The signal on the node O 1  enters the re-cycle delay line  302 , and the node O is connected to the node O 1 . When B=0, the re-cycle mode is disabled. The signal on the node O 2  enters the re-cycle delay line  302  and the node O is connected to be node C. It allows the clock to circulate in the re-cycle delay line  302  according to different operating frequencies. The delay time of the re-cycle delay line  302  could be increased by reusing the delay units rather than cascading extra delay units. The counter  314  sets the optimal cycles of the re-cycle delay line  302 . The undesired duty cycle distortion of the delay line  302  may cause the disappearance of the output signal on the node O in a low frequency operation due to mismatches of the driving capability of NMOS and PMOS in the re-cycle delay line  302 . To solve the problem, an edge-triggered D flip-flop  312  is placed in the front of the delay line  302  to respond for edge recovery. If a very high output frequency is desired, the signal on the node O 2  can directly bypass the re-cycle delay line  302 , and only the fine delay line  304  is used. In this situation, the path  320 , the path  318 , and the fine delay line  304  form a close loop to achieve the maximum output frequency. In this embodiment, the interpolator  306  chooses two successive phases in fine delay line as an interpolating phase according to C 1 . Then, the interpolating phase is interpolated to generate the final phase according to C 2 . The control codes, C 2 , can be further modulated with high speed dithering to improve the timing resolution. 
     Simulated Results 
     The simulated conditions are listed as followings: 
     Δt=2 ns 
     C max =4 
     C 1 =2 
     C 2 =0.25 
       FIG. 4  shows the simulated results when M=5. The delay units in the re-cycle delay line  302  are re-used five times. The total delay time is given by 
         T= 5*4*2 ns+2*2 ns+0.25*2 ns=44.5 ns 
       FIG. 5  shows the simulated results when M=100. The delay units in the re-cycle delay line  302  are re-used 100 times. The total delay time is given by 
         T= 100*4*2 ns+2*2 ns+0.25*2 ns=804.5 ns 
     While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.