Patent Publication Number: US-2021181778-A1

Title: Method of smoothing a current consumed by an integrated circuit, and corresponding device

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application claims the benefit of French Application No. 1914244, filed on Dec. 12, 2019, which application is hereby incorporated herein by reference. 
     TECHNICAL FIELD 
     Various embodiments and methods for implementing the invention relate to integrated circuits, and more particularly to integrated circuits comprising secure modules, and notably the protection of these modules against external attacks of the Simple Power Analysis (SPA) type. 
     BACKGROUND 
     An integrated circuit comprising a module can be the target of attacks aimed at recovering secure information, and in particular attacks by analysis of power consumption or SPA. 
     In operation, an integrated circuit consumes more or less power depending on the operations that it is carrying out. The SPA attack includes analyzing these variations in power consumption in particular to deduce indications regarding the operations carried out and/or their occurrences. 
     In secure applications, it is therefore recommended to smooth the power consumption seen from the power supply as much as possible so that it is difficult for a potential attacker to determine the activity of the various components of the circuit by SPA attacks. 
     Means exist for protecting against SPA attacks, comprising, for example, current copying and amplifying means implementing two MOS transistors, in particular MOS transistors configured as a mirror, a first transistor comprising a W 1 /L 1  ratio of less than the W 2 /L 2  ratio of a second transistor, for example a W 1 /L 1  ratio that is one hundred times smaller than the W 2 /L 2  ratio to amplify a current so as to create an additional current to complete the current consumed by the integrated circuit such that the overall current consumed by the integrated circuit is constant, independently of the operations carried out by the integrated circuit. 
     However, since the W 2 /L 2  ratio is much higher than the W 1 /L 1  ratio of the first transistor, the second transistor comprises a stray capacitance greater than that of the first transistor such that the dynamic response of the second transistor during the transient phase is degraded relative to that of the first transistor, slowing the operation of the protection means. 
     Slowing of the protection means can result in a time delay in the generation of the additional current such that the overall current consumed by the integrated circuit is no longer constant, providing power consumption information during SPA attacks. 
     Slowing of the protection means is especially significant when the currents consumed by the integrated circuit to carry out operations are high, for example in the order of 30 to 50 mA. 
     There is a need to improve the dynamic response of the protection means against SPA attacks during the transient phase. 
     SUMMARY 
     Embodiments and methods for implementing the invention advantageously reduce the size of the transistors of the current copying and amplifying means. 
     According to one aspect, a method smooths the current consumed by a power supply for an electronic circuit, the electronic including at least one module, for example a microprocessor, a memory, etc., powered directly or indirectly, for example via a voltage regulator, by the power supply and consuming a module current. 
     The method according to this aspect includes 
     generating, for each module, a module auxiliary current equal to a first fraction of the corresponding module current, 
     generating by a first stage, powered by the power supply, including at least one current source, a stage current higher than the sum of the maximum values of each module auxiliary current, 
     generating an intermediate current equal to the difference between the stage current and a secondary current equal to the sum of each module auxiliary current, 
     generating a reference potential by multiplying, in a first branch of a regulating stage powered by the power supply, the intermediate current by an impedance equal to one, and 
     controlling the voltage of a regulating means of a second branch of the regulating stage such that a potential of the second branch is equal to the reference potential, the potential being obtained by multiplying a current circulating in the branch by a multiplication factor equal to the first fraction. 
     Thus, in the method according to this aspect, a plurality of currents consumed by the power supply are generated in a simple manner, the sum whereof does not depend on the current consumed by each module but only in theory on the current supplied by the current source stage. 
     The power consumption of the integrated circuit is thus smoothed, and this overall smoothed power consumption as externally viewed is higher than the sum of the maximum power consumptions of each module. 
     In order to smooth the power consumption, the regulating means is voltage-controlled such that the dynamic response of the electronic circuit in the transient phase is improved. 
     The value of the first fraction can be chosen from a set of values. 
     The first stage can further include at least one additional activatable current source supplying an additional current and the stage current is equal to the sum of the main current and of each additional current supplied by each activated additional current source. 
     Thus, by activating successively and/or simultaneously the various current sources, the current consumed by the power supply varies, which renders the detection of the variations of the module current even more difficult. 
     In this regard, it is also possible to add capacitive noise within the device, for example, at the output of the first stage. 
     According to another aspect, an electronic device comprises 
     a power supply terminal, 
     and at least one module connected to the power supply terminal and configured so as to consume a module current, 
     first generation means connected to the power supply terminal and configured so as to generate, for each module, a module auxiliary current equal to a first fraction of the corresponding module current, 
     a first stage, connected to the power supply terminal, including at least one current source configured so as to supply a stage current higher than the sum of the maximum values of each module auxiliary current, 
     second generation means configured so as to generate an intermediate current equal to the difference between the stage current and a secondary current equal to the sum of each module auxiliary current, 
     a regulating stage connected to the power supply terminal comprising a first branch configured so as to generate a reference potential from the intermediate current, a second branch comprising a regulating means and comparison means configured so as to control the voltage of the regulating means such that a potential of the second branch is equal to the reference potential, the potential being obtained by multiplying a current circulating in the branch by an impedance equal to the first fraction, and 
     a terminal stage connected to the power supply terminal and configured so as to multiply the intermediate current by a multiplication factor equal to one. 
     According to one embodiment, the first branch of the regulating stage comprises a first resistive impedance having a unit value and comprising an input connected to the power supply and an output connected to the terminal stage and to a first input of the comparison means, the second branch of the regulating stage comprising a second resistive impedance having a value equal to the first fraction and comprising a first terminal connected to the power supply and a second terminal connected to a second input of the comparison means and to the regulating means. 
     According to another embodiment, the first impedance circuit comprises a first resistor and the second impedance circuit comprises a second resistor, the comparison means comprising an operational amplifier, an inverting input whereof is connected between the first resistor and the second terminal and a non-inverting input is connected between the second resistor and the regulating means. 
     The use of resistors improves the dynamics of the device in the transient phase. 
     According to yet another embodiment, the device can further comprise a cascode transistor and a bias voltage source connected to the first terminal and to the gate so as to bias the cascode transistor, the drain of the transistor being connected to the non-inverting input of the operational amplifier and the source of the transistor being connected to the regulating means. 
     The cascode transistor protects the drain of the regulating transistor against a rise in potential. 
     According to yet another embodiment, the first impedance circuit comprises a first NMOS transistor and the second impedance circuit comprises a second NMOS transistor, the comparison means comprising an operational amplifier, an inverting input whereof is connected to the source of the first transistor and a non-inverting input is connected between the source of the second transistor, the drain of the first and second transistors being connected to the input, the device further comprising a biasing source connected to the input and to the gates of the first and second transistors to bias the transistors. 
     The production of resistive impedance circuits from transistors allows the components of the device to be equalized. 
     According to yet another embodiment, the first impedance circuit comprises a first NMOS transistor and the second impedance circuit comprises a second NMOS transistor, the comparison means comprising a first operational amplifier, an inverting input whereof is connected to the source of the first transistor and a non-inverting input is connected between the source of the second transistor, the drain of the first and second transistors being connected to the input, the device further comprising a second operational amplifier, an output whereof is connected to the gate of the first and second transistors, an inverting input is connected to the source of the first transistor and the non-inverting input is connected to the terminal stage. 
     According to yet another embodiment,
         the first generation means include, for each module, a first current mirror having a copy factor equal to the first fraction, having a first output supplying the corresponding module current and a second output supplying the corresponding module auxiliary current,   the second generation means include a second current mirror having a copy factor equal to one, and   the second output of the first current mirror is connected to the input of the second current mirror and the output of the second current mirror is connected to the output of the first stage.       

     According to yet another embodiment, the terminal stage includes a current copying means having a copy factor equal to one, the input whereof is connected to the output of the second generation means and the output whereof is connected to the first branch. 
     According to yet another embodiment, the terminal stage includes a first MOS transistor connected to the output of the second current mirror, and at least one second MOS transistor connected between the power supply terminal and the ground, the gates of the MOS transistors being connected together, and the device further comprises an intermediate operational amplifier, the non-inverting input whereof is connected to the output of the second current mirror, the inverting input whereof is connected to the input of the second current mirror, and the output whereof is connected to the gates of the MOS transistors. 
     In order to improve the current copying by the second generation means, in particular when the module auxiliary current or the sum of the module auxiliary currents is close to the stage current, an intermediate operational amplifier can also be added, the non-inverting input whereof is connected to the output of the second current mirror, the inverting input whereof is connected to the input of the second current mirror, and the output whereof is connected to the gates of the MOS transistors of the terminal stage. 
     According to yet another embodiment, the first generation means comprise, for each module, a cascode stage connected between the second output of the corresponding first current mirror and the input of the second current mirror, the cascode stage comprising a second PMOS transistor and a second operational amplifier, the non-inverting input whereof is connected between the power supply terminal and the corresponding module, the inverting input whereof is connected to the source of the second PMOS transistor and the output whereof is connected to the gate of the second PMOS transistor. 
     Moreover, in order to improve the current copying, the first generation means can comprise, for each module, a first cascode stage connected between the second output of the corresponding first current mirror and the input of the second current mirror, the first cascode stage comprising a first PMOS transistor and a first operational amplifier, the non-inverting input whereof is connected between the power supply terminal and the corresponding module, the inverting input whereof is connected to the source of the first PMOS transistor and the output whereof is connected to the gate of the first PMOS transistor. 
     According to yet another embodiment, the device further comprises a capacitive noise generator. 
     According to yet another embodiment, the device comprises at least one regulator connected between the power supply terminal and the at least one module, configured so as to supply a regulated voltage to the at least one module. 
     According to yet another embodiment, the regulator includes the first generation means. 
     According to yet another embodiment, the device includes a plurality of modules, and in which the first generation means include a plurality of first outputs respectively connected to the modules so as to supply the respective module currents and a plurality of second outputs jointly connected to the input of the second generation means so as to supply the secondary current. 
     According to another aspect, an appliance incorporates an integrated circuit as defined hereinabove. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Other advantages and features of the invention will become apparent upon examining the detailed description of non-limiting embodiments, and from the accompanying drawings in which: 
         FIG. 1  shows an example of a first embodiment of an electronic device; 
         FIG. 2  shows an embodiment in which the third NMOS transistor of the terminal stage is no longer configured as a diode; 
         FIG. 3  shows another embodiment in which the regulating stage comprises a third operational amplifier replacing the voltage source controlling the gates of the NMOS transistors, and a second input connected to the input of the terminal stage; 
         FIG. 4  shows an embodiment method in which the first stage is modified with respect to the device shown in  FIG. 1 ; 
         FIG. 5  shows an alternative embodiment that adds a capacitive noise generator at the output of the first stage; 
         FIG. 6  shows an embodiment in which the device comprises a second module that consumes a second module current and a second regulator coupled between the power supply terminal and the second module; 
         FIG. 7  shows a third embodiment of the regulating stage; and 
         FIG. 8  shows a fourth embodiment of the regulating stage. 
     
    
    
     DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS 
     In the following description, the terms “coupled” and “connected” denote an electrical connection which is either direct, or indirect via other devices or means of connection. 
     Reference is now made to  FIG. 1 , which shows an example of a first embodiment of an electronic device DIS. 
     The device DIS comprises a module  1 , for example, a microprocessor of a smart card. The device can be situated within the integrated circuit of the smart card. 
     The device DIS further comprises a power supply terminal  2  intended to receive a power supply voltage V cc , for example, a voltage of 5 Volts. 
     The device further comprises first generation means  4  including a first input E 31  and a second input E 32  connected to the power supply terminal  2 , in addition to a first output S 31  and a second output S 32 . 
     The device further comprises second generation means  5  including an input E 5  and an output S 5 , a first stage  6  of one or more current sources including an input E 6  connected to the power supply terminal  2  and an output S 6 , a terminal stage  7  including an input E 7  and an output S 7 , and a second regulating stage  8  including an input E 8  connected to the power supply terminal  2  and an output S 8 . 
     The respective connections and features thereof will be described in more detail hereinbelow. 
     A regulator  3  is connected between the power supply terminal  2  and the microprocessor  1  so as to supply a regulated voltage V dd  to the microprocessor, for example in this case, a voltage of 2.5 Volts. 
     The microprocessor  1  consumes a current I vdd , the value whereof depends on the operations that it carries out. 
     In this example, the regulator  3  comprises the first generation means  4 , in this case a first current mirror which supplies, at the input E 5  of the second generation means  5 , an auxiliary current I aux  equal to a first fraction of the current consumed I vdd . In this example, the current mirror has a copy factor equal to 1/100, i.e. it supplies a module auxiliary current I aux  equal to one hundredth of the current consumed I vdd  (the first fraction is equal to 1/100). 
     The first current mirror conventionally comprises two transistors  41  and  42  coupled together via the gates G 41 , G 42  thereof. 
     The first transistor  41 , for example a PMOS transistor, is configured as a diode (i.e. the gate G and the drain D thereof are connected). The source S 41  thereof, which forms the first input E 31  of the first generation means, is connected to the first power supply terminal, and the drain D 41  thereof, which forms the first output S 31  of the first generation means, is connected to the module  1 . 
     The source S 42  of the second transistor  42 , for example a second PMOS transistor, which source forms the second input E 32  of the first generation means  4 , is connected to the power supply terminal  2 , and the drain D 42  thereof, which forms the second output S 32  of the first generation means, is connected to the input E 5  of the second generation means  5 . 
     To obtain the first fraction of the consumed current I vdd , the second PMOS transistor can be chosen having a ratio W 42 /L 42  between the width W 42  and the length L 42  of its channel that is 100 times smaller than the ratio W 41 /L 41  between the width W 41  and the length L 41  of the channel of the first transistor  41 . 
     An alternative approach would be to have a plurality of first transistors  41  mounted in parallel and one or more second transistors  42  identical to the first transistors  41  and mounted in parallel, such that the number of first transistors is 100 times greater than the number of second transistors. 
     In this example, the second generation means  5  comprise a second current mirror with a copy factor equal to one, which conventionally includes two identical transistors  51  and  52 , for example NMOS transistors, coupled together by the gates G 51  and G 52  thereof. 
     The first NMOS transistor  51  is configured as a diode. The drain D 51  thereof, which forms the input E 5  of the second generation means  5 , is connected to the drain D 42  of the second PMOS transistor  42  of the first current mirror, and the source S 51  thereof is connected to the ground GND. 
     The source S 52  of the second NMOS transistor  52  is connected to the ground, and the drain D 52  thereof, which forms the output S 5  of the second generation means  5 , is connected to the input E 7  of the terminal stage  7  and to the output S 6  of the first stage  6 . 
     Thus, the second generation means receive the module auxiliary current I aux  at the input E 5  and copy this same module auxiliary current I aux  at the output S 5 . 
     In this case, the first stage  6  comprises a main current source  61  connected between the power supply terminal  2  and the input E 7  of the terminal stage. 
     This main current source  61  is configured so as to supply a stage current I stage , equal to the first fraction of a reference current I set . 
     Thus, in this example where the module auxiliary current I aux  is equal to 
     
       
         
           
             
               Ivdd 
               
                 1 
                  
                 0 
                  
                 0 
               
             
             , 
           
         
       
     
     the stage current I stage  is equal to 
     
       
         
           
             
               Iset 
               
                 1 
                  
                 0 
                  
                 0 
               
             
             . 
           
         
       
     
     The reference current I set  is chosen to be higher than the maximum value of the module current I vdd . 
     This maximum value is, for example, determined by simulation during the design of the integrated circuit taking into account the foreseeable activity of the module  1 . 
     Since the reference current I set  is higher than the maximum value of the maximum module current, the stage current I stage  is higher than the maximum value of the module auxiliary current I aux . 
     The value of the first fraction is chosen from among a set of values. 
     For example, the set of values can be 
     
       
         
           
             
               { 
               
                 
                   1 
                   
                     1 
                      
                     0 
                      
                     0 
                   
                 
                 ; 
                 
                   1 
                   
                     6 
                      
                     0 
                   
                 
                 ; 
                 
                   1 
                   
                     5 
                      
                     0 
                   
                 
                 ; 
                 
                   1 
                   
                     4 
                      
                     0 
                   
                 
               
               } 
             
             , 
           
         
       
     
     and the stage current I stage  supplied can thus be equal to 
     
       
         
           
             
               Iset 
               
                 1 
                  
                 0 
                  
                 0 
               
             
             , 
             
               or 
                
               
                   
               
                
               
                 Iset 
                 
                   6 
                    
                   0 
                 
               
             
             , 
           
         
       
     
     etc. 
     Since the first stage  6  supplies a stage current I stage  equal to 
     
       
         
           
             
               Iset 
               
                 1 
                  
                 0 
                  
                 0 
               
             
             , 
           
         
       
     
     the terminal stage  7  thus receives a positive intermediate current I int  equal to 
     
       
         
           
             
               Iset 
               
                 1 
                  
                 0 
                  
                 0 
               
             
             - 
             
               Ivdd 
               
                 1 
                  
                 0 
                  
                 0 
               
             
           
         
       
     
     at the input E 7  thereof. 
     The second generation means  5  are configured so as to generate an intermediate current equal to the difference between the stage current and a secondary current I sec  equal to the sum of each module auxiliary current I aux . 
     The terminal stage  7  includes, in this example, a third current mirror having a copy factor equal to 1, configured so as to copy the current I int . 
     This third current mirror conventionally comprises a third and a fourth transistor  71  and  72 , for example in this case NMOS transistors, coupled together via the gates G 71  and G 72  thereof. 
     The third NMOS transistor  71  is configured as a diode. The source S 71  thereof is connected to the ground, and the drain D 71  thereof, which forms the input E 7  of the terminal stage, is connected to the output S 5  of the second generation means and to the output S 6  of the first stage. 
     The source S 72  of the fourth NMOS transistor  72  is connected to the ground GND and the drain D 72  thereof is connected to the output S 8  of the second regulating stage  8 . 
     Thus, the terminal stage receives, at the input E 7 , an intermediate current I int  equal to the difference between the stage current I stage  and the auxiliary current I aux , and copies this intermediate current I int  at the output S 7 . 
     The second regulating state  8  comprises a first branch BR 1  configured so as to generate a reference potential from the intermediate current, a second branch BR 2  comprising a regulating means comprising, for example, a regulating transistor  81  and comparison means configured so as to control the gate G 81  of the transistor such that a potential of the second branch BR 2  is equal to the reference potential, the potential of the second branch BR 2  is obtained by multiplying a current equal to the inverse of the first fraction of the intermediate current I int  circulating in the branch by an impedance equal to the first fraction. 
     The reference potential is obtained by multiplying a current circulating in the first branch BR 1  by a unit impedance. 
     The first branch BR 1  comprises a fifth transistor  82 , the drain D 82  whereof is connected to the input E 8 , the source S 82  is connected to the output S 8 . 
     The second branch BR 2  comprises a sixth transistor  83 , the drain D 83  whereof is connected to the input E 8 , the source S 83  is connected to the drain D 81  of the transistor  81 , the source S 81  of the transistor  81  being connected to the ground GND. A current I R  circulates in the second branch BR 2 . 
     The second stage  8  further comprises a bias voltage source  84  powered by the input E 8  and supplying a bias voltage over each of the gates G 82  and G 83  of the fifth and sixth MOS transistors  82  and  83 . 
     The transistors  82  and  83 , in addition to the bias voltage, are chosen such that the resistive impedance of the transistor  82  is equal to R (unit impedance) and the resistive impedance of the transistor  83  is equal, for example, to the first fraction multiplied by the unit impedance, i.e. R/100 such that the current I R  is one hundred times greater than the current Iint. 
     To obtain the consumed current IR, the sixth MOS transistor  83  can be chosen having a ratio W 83 /L 83  between the width W 83  and the length L 83  of its channel that is one hundred times greater than the ratio W 82 /L 82  between the width W 82  and the length L 82  of the channel of the fifth transistor  82 . 
     The comparison means comprise, for example, an operational amplifier  85 , the inverting input whereof is connected to the source of the transistor  82  and the non-inverting input is connected to the source of the transistor  83 . 
     In operation, the device DIS thus configured therefore consumes 
     the first current I vdd , 
     the module auxiliary current 
     
       
         
           
             
               
                 I 
                 aux 
               
               = 
               
                 Ivdd 
                 
                   1 
                    
                   0 
                    
                   0 
                 
               
             
             , 
           
         
       
     
     the stage current 
     
       
         
           
             
               
                 I 
                 stage 
               
               = 
               
                 Iset 
                 
                   1 
                    
                   0 
                    
                   0 
                 
               
             
             , 
           
         
       
     
     and 
     the terminal current I int =I stage −I aux , and 
     since the potentials at the two inputs of the operational amplifier  82  are equal, the device further consumes the current I R =I set −I vdd    
     The current I vcc  consumed by the power supply is thus equal to the sum of these currents, i.e. 1.02*I set  (obtained by adding I vdd , I aux , I stage , I int  and I R ) and thus does not depend on the module current I vdd , but only on the reference current I set , which is constant and in this case higher than the maximum value of the module current I vdd . 
     The transistors  71 ,  72  and  81  comprise, for example, low-voltage transistors such that they comprise a very low stray capacitance. The transistors  82  and  83  comprise transistors having a high W/L ratio such that they comprise a high stray capacitance. 
     However, since the transistors  82  and  83  are biased by the voltage source  84  at a fixed voltage, and since the transistors  71 ,  72  and  81  comprise low-voltage transistors, the dynamic response of the device DIS in the transient phase is improved. 
       FIG. 2  shows a second embodiment. In this embodiment, the device DIS as previously described has been modified in such a manner that the third NMOS transistor  71  of the terminal stage is no longer configured as a diode. 
     An operational amplifier  9  has been added between the second generation means  5  and the terminal stage  7 . 
     The non-inverting input thereof is connected to the input E 7  of the terminal stage, and the inverting input thereof is connected to the mutually-coupled gates G 51  and G 52  of the first and of the second NMOS transistors  51  and  52 , i.e. to the first input E 5  of the second generation means  5  since the first NMOS transistor  51  is configured as a diode. 
     The output of the amplifier  9  is connected to the mutually-coupled gates G 71  and G 72  of the third NMOS transistor  71  and of the fourth NMOS transistor  72 . 
     Thus, by controlling the gate G 71  of the third NMOS transistor  71  in such a manner as to equalise the potentials of the drains D 51  and D 52  of the first and second NMOS transistors  51  and  52 , the operational amplifier allows an intermediate current I int  to be obtained at the input E 7  of the terminal stage which is precisely equal to the difference between the stage current I stage  and the module auxiliary current I aux , even if the module auxiliary current I aux  has a value close to the stage current I stage . 
     According to another embodiment shown in  FIG. 3 , the regulating stage  8  can comprise a third operational amplifier  86  replacing the voltage source  84  controlling the gates G 82  and G 83  of the NMOS transistors  82  and  83 , and a second input E 81  connected to the input E 7  of the terminal stage  7 . 
     The non-inverting input of the amplifier  86  is connected to the second input E 81  and the inverting input of the amplifier  86  is connected to the source S 82  of the transistor  82 . 
     Thus, the second amplifier  86  allows the voltages at the input E 7  and at the output S 7  of the terminal stage to be equalized, thus improving the precision of the current copying carried out by the terminal stage  7 . 
     The device DIS can further comprise a cascode stage  10  comprising a seventh PMOS transistor  101 , the source S 101  whereof is connected to the second output S 32  of the first generation means, and the drain D 101  whereof is coupled to the input E 5  of the second generation means  5 . 
     The cascode stage  10  further comprises a fourth operational amplifier  102 , the non-inverting input whereof is coupled to the first output S 31  of the first generation means  4 , and the inverting input whereof is coupled to the second output S 32  of the first generation means  4 . The output of the second operational amplifier  102  is coupled to the gate G 101  of the third PMOS transistor  101 . 
     Thus, the first cascode stage  10  allows the voltages at the first and second outputs S 31  and S 32  of the first generation means to be equalized, which contributes to obtaining the desired ratio of 1/100 between the current I vdd  and the auxiliary current 
     
       
         
           
             
               I 
               
                 aux 
                 = 
               
             
              
             
               
                 
                   I 
                   
                     v 
                      
                     d 
                      
                     d 
                   
                 
                 
                   1 
                    
                   0 
                    
                   0 
                 
               
               . 
             
           
         
       
     
     The cascode stage  10  thus improves the precision of the current copying respectively carried out by the first generation means  4 . 
       FIG. 4  shows one embodiment method, in which the first stage  6  has been modified with respect to the device DIS previously described and shown in  FIG. 1 . 
     In this embodiment, the first stage comprises, in addition to the main current source  61  supplying the second fraction of the reference current I set , a first additional current source  63  supplying a first additional current L and a second additional current source  64  supplying a second additional current I 2 . 
     The three current sources,  61 ,  63 , and  64  are configured in parallel between the power supply terminal  2  and the output S 6  of the first stage  6 , and the first and the second additional sources  63  and  64  are furthermore activatable independently of the main current source  61 . 
     The stage current I stage  supplied by the first stage  6  is thus a current equal to the sum of a main current I p , of a first additional current I 1  and of a second additional current I 2  when the two additional current sources  63  and  64  are activated. 
     The total current I vcc  consumed by the power supply is thus I vcc =1,02*Iset+102*I 1 +102*I 2 . 
     Since the first and second additional current sources  63  and  64  can be independently activated, the current I vcc  consumed by the power supply can successively take various values from among the following set of values: 
         I   vcc =1,02*Iset+102* I   1 +102* I   2 , 
         I   vcc =1,02*Iset+102* I   1 , 
         I   vcc =1,02*Iset+102* I   2 , 
         I   vcc =1,02*Iset. 
     Thus, the detection of the variations of the module current I vdd  are even more difficult to detect by attacks based on analysis of power consumption (SPA). 
     It should be noted that this modification of the first stage is compatible with the embodiments shown in  FIGS. 2 and 3 . It is presented here based on the embodiment shown in  FIG. 1  for simplification purposes only. 
     According to an alternative embodiment shown in  FIG. 5 , it is also possible to add a capacitive noise generator at the output S 6  of the first stage. 
     For example, in this case, the capacitive noise generator  11  comprises a capacitor  110 , an inverter  111  and control means  112 . 
     The capacitor no is connected via a first terminal to the output S 6  of the first stage and via a second terminal to the inverter  111 . The inverter  111  is powered between the power supply terminal  2  and the ground GND. The control means  112  are connected to the inverter  111  so as to, depending on the output of the inverter, charge or discharge the capacitor  110 . 
     This embodiment is also compatible with the embodiments shown in  FIGS. 1, 2, 3 and 4 . 
     According to an alternative embodiment, the device can comprise a plurality of modules. 
     For example, in the embodiment shown in  FIG. 6 , the device DIS comprises a second module  12 , for example a second microprocessor, which consumes a second module current I vdd2 , and a second regulator  13  coupled between the power supply terminal  2  and the second module, further comprising first generation means  14 . 
     The first generation means  14  thus supply a second module auxiliary current I aux2  equal to the first fraction of the second module current I vdd2  at the input E 5  of the second generation means  5 . In this example, 
     
       
         
           
             
               I 
               
                 aux 
                  
                 
                     
                 
                  
                 2 
               
             
             = 
             
               
                 
                   I 
                   
                     vdd 
                      
                     
                         
                     
                      
                     2 
                   
                 
                 
                   1 
                    
                   0 
                    
                   0 
                 
               
               . 
             
           
         
       
     
     Thus, the second generation means  5  receive a secondary current I see  at the input E 5  thereof equal to the sum of the auxiliary module currents I aux  and I aux2 . 
     The stage current I stage  is, in this example, slightly higher than the maximum value of the secondary current I sec . 
     This embodiment is compatible with all of the embodiments described hereinabove and shown in  FIGS. 1 to 5 . 
     It should be noted that although embodiments have been described in which the current regulators  3  and  13  comprise the first generation means  4  and  14 , an embodiment in which the regulators  3  and  13  are separate from the first generation means  4  and  14  can be considered. 
     Furthermore, the regulators are not indispensable. More specifically, each module could be powered by the power supply voltage V cc  via a current mirror. 
     Moreover, although an efficient injection of capacitive noise at the output S 6  of the first stage  6  has been described, capacitive noise could also be injected at other nodes, for example at the input E 5  of the second generation means  5 , or at the output of the operational amplifier  8 . 
       FIG. 7  shows a third embodiment of the regulating stage  8 . 
     This embodiment of the regulating stage differs from the embodiment shown in  FIG. 1  in that the transistors  82  and  83  are respectively replaced with resistive impedance circuits comprising resistors R 1  and R 2  of respective impedances R and R/100. 
     The replacement of the transistors with resistors further allows the dynamics of the device DIS to be improved in the transient phase. 
       FIG. 8  shows a fourth embodiment of the regulating stage  8 . 
     This embodiment differs from the embodiment shown in  FIG. 7  in that the regulating stage  8  further comprises a cascode transistor  87  and a second bias voltage source  88  connected to the input E 8  and to the gate G 88  so as to bias the cascode transistor  87 . 
     The drain D 87  of the transistor  87  is connected to the resistor R 2  and the source S 87  of the transistor  87  is connected to the drain D 81  of the regulating transistor  81 . 
     The transistor  87  protects the low-voltage regulating transistor  81  against the voltage fluctuations capable of causing deterioration thereto.