Patent Publication Number: US-11646868-B2

Title: Autonomous driving controller encrypted communications

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     The present U.S. Utility Patent Application is a continuation of, and claims priority to, U.S. patent application Ser. No. 16/388,352 titled “AUTONOMOUS DRIVING CONTROLLER ENCRYPTED COMMUNICATIONS” and filed on Apr. 18, 2019. U.S. patent application Ser. No. 16/388,352 claims priority pursuant to 35 U.S.C. § 119(e) to U.S. Provisional Application No. 62/663,408, entitled “AUTONOMOUS DRIVING CONTROLLER ENCRYPTED COMMUNICATIONS”, filed Apr. 27, 2018. Each of the above-recited applications are hereby incorporated herein by reference in their entirety and made part of the present U.S. Utility Patent Application for all purposes. 
    
    
     BACKGROUND 
     Technical Field 
     The present disclosure relates to the autonomous driving of a vehicle; and more particularly to an autonomous driving controller. 
     Description of Related Art 
     Self-driving vehicles are generally known to include a plurality of sensors, e.g., RADAR sensors, and LIDOR sensors, cameras, and sonic proximity detectors, among other types of data capturing components. The data captured by these sensors is communicated to a central processor, which processes the data to assist in making autonomous driving decisions, e.g., braking, accelerating, steering changes, etc. Such autonomous driving decisions may be performed while the vehicle is self-driving or when the driver of the vehicle is being assisted, e.g., emergency braking, driver notification, etc. 
     In order to ensure that the autonomous driving system is fault tolerant, an autonomous driving controller typically includes multiple processors that operate in parallel on common input data, e.g., data received from the sensors, driver input data, extra-vehicular input data, etc., to support autonomous driving operations. The parallel processors should be fully functional and in agreement to support autonomous driving functions. When one (or more) of the parallel processors is compromised, autonomous driving operations are typically terminated. However, because the autonomous driving system is part of a larger communication system, e.g., intra-vehicular, extra-vehicular, and inter-vehicular, for example, there is a risk that the parallel processors could be operationally modified or controlled in an undesirable manner. 
     SUMMARY 
     According to a first embodiment of the present disclosure, an autonomous driving controller for a vehicular autonomous driving system that has a plurality of autonomous driving sensors includes a plurality of parallel processors operating on common input data received from the plurality of autonomous driving sensors. Each of the plurality of parallel processors includes at least one general processor and a security processor subsystem (SCS). The autonomous driving controller also includes communication circuitry configured to support communications between the plurality of parallel processors, including communications between the general processors of the plurality of parallel processors and communications between the SCSs of the plurality of parallel processors that are protected by SCS cryptography. 
     By protecting communications among the SCSs using the SCS cryptography, which is very important because the SCSs are responsible for the security of the plurality of parallel processors, which includes, for example, software update permission and verification and system booting, among other security responsibilities. 
     According to a second embodiment, each of the plurality of parallel processors further includes a safety subsystem (SMS) and the communication circuitry is further configured to support communications between the SMSs of the plurality of parallel processors protected by SMS cryptography, the SMS cryptography differing from the SCS cryptography. The SMSs are responsible for the safety of the autonomous driving system, e.g., whether to initiate and/or to continue autonomous driving operations. By protecting the SMS communications, the safety of the vehicular autonomous driving system is further enhanced. 
     According to an aspect of the first and/or second embodiments, each of the plurality of parallel processors is configured to store a SCS private key corresponding to the SCS cryptography in a local memory dedicated to its SCS, which precludes the general processors from accessing the SCS private key. According to another aspect of the first and/or second embodiments, the SCS of each of the plurality of parallel processors includes dedicated SCS cryptography hardware, which isolates the SCS communications cryptography from the general processors. These SMSs may also have dedicated local SMS memory and dedicated SMS cryptography hardware. 
     According to another aspect of the first and/or second embodiments, a first SCS of a first parallel processor of the plurality of parallel processors may be configured to establish a private communication link with a second SCS of a second parallel processor of the plurality of parallel processors and use the private communication link to transmit a SCS private key to the second SCS of the second parallel processor for subsequent use in communications protected by the SCS cryptography. With this aspect, in establishing the private communication link with the second SCS of the second parallel processor of the plurality of parallel processors, the first SCS of the first parallel processor may use dedicated SCS cryptography hardware of the first SCS and the second SCS of the second parallel processor may use dedicated SCS cryptography hardware of the second SCS. Further, with this aspect, in establishing the private communication link with the second SCS of the second parallel processor of the plurality of parallel processors, the first SCS may use one of a Diffie-Hellman algorithm or a Rivest-Shamir-Adleman (RSA) algorithm. Same/similar operations may be performed by the SMSs. 
     The plurality of parallel processors may be formed on a single System on a Chip integrated circuit, formed on differing respective integrated circuits, or a first group of the plurality of parallel processors may be formed on a first integrated circuit and a second group of the plurality of parallel processors may be formed on a second integrated circuit. 
     The communication circuitry may further support intra-vehicle communications among the plurality of autonomous driving sensors and the autonomous driving controller using intra-vehicle cryptography that differs from both the SCS cryptography and the SMS cryptography. Further, the communication circuitry may support extra-vehicle communications using extra-vehicle cryptography that differs from the intra-vehicle cryptography, the SCS cryptography, and/or the SMS cryptography. 
     A third embodiment of the present disclosure considers a method for operating an autonomous driving controller that includes a plurality of parallel processors. The method first includes a first SCS of a first parallel processor of the plurality of parallel processors acquiring an SCS private key. The method next includes the first SCS securely distributing the SCS private key to other SCSs of other parallel processors of the plurality of parallel processors. Next, the method includes a first SMS of the first parallel processor of the plurality of parallel processors acquiring an SMS private key, wherein the SMS private key differs from the SCS private key. The method continues with the first SMS securely distributing the SMS private key to other SMSs of other parallel processors of the plurality of parallel processors. The method then includes the first SCS communicating with the other SCSs of the other parallel processors of the plurality of parallel processors using SCS cryptography based on the SCS private key. The method concludes with the first SMS communicating with the other SMSs of the other parallel processors of the plurality of parallel processors using SMS cryptography based on the SMS private key. 
     The third embodiment provides the advantages of protecting both the SCS and the SMS communications so that they may not be easily read or altered by the general processors, which enhances the security of the autonomous driving controller and also enhances the safety of the autonomous driving controller. 
     According to various aspects of the third embodiment, the first SCS, in acquiring the SCS private key, may retrieve the SCS private key from dedicated memory. Further, the first SCS, in acquiring the SCS private key and/or in securing distributing the SCS private key to other SCS of the other parallel processes may use dedicated SCS cryptography hardware. Moreover, in acquiring the SMS private key, the SMS may retrieve the SMS private key from dedicated memory. Still further, the first SMS, in acquiring the SMS private key and/or in securing distributing the SMS private key to other SMS of the other parallel processes may use dedicated SMS cryptography hardware. The other aspects described above with reference to the first and/or second embodiments may be applied to the third embodiment as well. 
     Benefits of the disclosed embodiments will become apparent from reading the detailed description below with reference to the drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
         FIG.  1 A  is a diagram illustrating a group of vehicles, at least one of which is constructed and operates according to a described embodiment to support autonomous driving. 
         FIG.  1 B  is a diagram illustrating a vehicle that is constructed and operates according to a described embodiment to support autonomous driving. 
         FIG.  2    is a block diagram illustrating an autonomous driving controller constructed and operating according to a first described embodiment. 
         FIG.  3 A  is a block diagram illustrating an autonomous driving sensor constructed according to a described embodiment. 
         FIG.  3 B  is a block diagram illustrating an autonomous driving controller constructed according to a described embodiment. 
         FIG.  4 A  is a block diagram illustrating a first embodiment of an autonomous driving parallel processing system constructed and operating according to the present disclosure. 
         FIG.  4 B  is a block diagram illustrating a second embodiment of an autonomous driving parallel processing system constructed and operating according to the present disclosure. 
         FIG.  5 A  is a block diagram illustrating communications among components of the autonomous driving parallel processors of  FIGS.  4 A and/or  4 B . 
         FIG.  5 B  is a block diagram illustrating components of a parallel processor of the autonomous driving parallel processors of  FIGS.  4 A and/or  4 B  according to one or more aspects of the described embodiments. 
         FIG.  6 A  is a flow diagram illustrating operations of an autonomous driving controller to establish secure communications among a plurality of Security Processor Subsystems (SCSs) according to one or more described embodiments. 
         FIG.  6 B  is a flow diagram illustrating differing operations of an autonomous driving controller to establish secure communications among a plurality of SCSs according to one or more described embodiments. 
         FIG.  6 C  is a flow diagram illustrating operations of an autonomous driving controller to establish secure communications among a plurality of SCSs and among a plurality of Safety Processor Subsystems (SMSs) according to one or more described embodiments. 
         FIG.  7    is a flow diagram illustrating operations of an autonomous driving controller to distribute an SCS private key according to one or more described embodiments. 
         FIG.  8    is a flow diagram illustrating second operations of an autonomous driving controller to distribute an SCS private key according to one or more described embodiments. 
         FIG.  9    is a flow diagram illustrating operations of an autonomous driving controller to distribute and validate SCSs private key according to one or more described embodiments. 
     
    
    
     DETAILED DESCRIPTION OF THE DISCLOSURE 
       FIG.  1 A  is a diagram illustrating a group of vehicles, at least one of which is constructed and operates according to a described embodiment to support autonomous driving. Vehicles  100 A- 110 D are traveling in a first direction and vehicles  100 E- 110 H are traveling in a second direction. At least some of these vehicles  100 A- 100 H support autonomous driving according to one or more embodiments described subsequently herein. The vehicles  100 A- 100 H support intra-vehicular communications, extra-vehicular communications, and inter-vehicular communications. Intra-vehicular communications occur within a particular vehicle. Extra-vehicular communications occur between a vehicle and one or more devices external to the vehicle, e.g., between vehicle  100 A and wireless access point  12 , e.g., cellular base station, WiFi access point, or another wireless device. An example of such extra-vehicular communications is those between the vehicle  100 A and an autonomous driving server  16  via communication network  14 . These communications may relate to current autonomous driving data/situations or may include data gathered by the vehicle  100 A for subsequent use by the autonomous driving server  16 . 
     Inter-vehicular communications are a sub-set of extra-vehicular communications and are communications between two or more vehicles, e.g.,  100 A,  100 B,  100 C and  100 F. These communications may relate to autonomous driving, e.g., identifying other vehicle, data exchange, vehicle driving warnings, etc. The inter-vehicular communications may be direct communications between vehicles, e.g., between vehicles  100 A and  100 C, or indirect communications that are relayed by wireless access point  12 , either directly or via the communication network  14 , the autonomous driving server, or another server. Because the vehicles  100 A- 110 H support a wide variety of operations, they are potentially susceptible to unwanted and undesirable communications. In a particularly bad scenario, while a vehicle, e.g.,  100 F, is driving autonomously, it may receive a malicious communication from another vehicle, e.g.,  100 E or via the wireless access point  12 , falsely notifying the vehicle  100 F of an impending crash or other autonomous driving event. In response to this malicious communication, the vehicle  100 E may automatically take a defensive maneuver that does cause a crash or near crash. Of course, this type of event is very undesirable. While it is desirable, from an autonomous driving standpoint, to receive as much input data as possible to make good autonomous driving decisions, there must be a safeguard in place to protect the vehicle  100 E from malicious communications. 
     Thus, according to the present disclosure, a vehicle, e.g.,  100 E, includes an autonomous driving controller having a plurality of parallel processors that operate in parallel on common input data received from a plurality of autonomous driving sensors. Each of the plurality of parallel processors includes a general processor and a security processor subsystem (SCS), and communication circuitry configured to support communications between the plurality of parallel processors, including communications between the general processors of the plurality of parallel processors and communications between the SCSs of the plurality of parallel processors that are protected by SCS cryptography. Each of the plurality of parallel processors may each also include a safety processor subsystem (SMS), with the communication circuitry also configured to support communications between the SMSs of the plurality of parallel processors that are protected by SMS cryptography that differs from the SCS cryptography. This communication cryptography supported by the SCS, the SMS, and the communication circuitry resists malicious communications that would otherwise compromise the autonomous driving system. The autonomous driving controller may include dedicated hardware and/or storage of the SCS and/or SMS to service the communication cryptography. This structure and various aspects of this structure will be described further herein with reference to the subsequent FIGS. 
       FIG.  1 B  is a diagram illustrating a vehicle that is constructed and operates according to a described embodiment to support autonomous driving. The vehicle  100  includes an autonomous driving controller  108  has a body  102  and a wiring system  104  for connecting a plurality of autonomous driving sensors  106  having individual sensors  106   a - 106   d  to an autonomous driving controller  108 . The wiring system  104  of  FIG.  1 B  is a structural cable  112 . The autonomous driving controller  108  may reside on or in or be co-located with an infotainment device  110 . The infotainment device  110  may be used to control functions of various components present in the vehicle  100 , e.g., to take over control of a steering function associated with a steering system (not shown) of the vehicle  100 , a braking function, an acceleration function, or another function of the vehicle  100  related to autonomous driving or collision prevention. These operations of the infotainment device  110  are performed based upon interaction with the autonomous driving controller  108 . 
     The autonomous driving sensors  106   a - 106   d  include cameras, RADAR sensors, LIDAR sensors, sonic proximity sensors, or other sensors that collect information relevant to the operation of the vehicle  100 . For example, autonomous driving sensors  106   a ,  106   b  could be cameras while autonomous driving sensors  106   c ,  106   d  could be RADAR sensors. The autonomous driving sensors  106   a - 106   d  are communicatively connected to the autonomous driving controller  108  via the structural cable  112 . The structural cable  112  may include a single conductor or a pair of conductors and may be twisted pair wiring, coaxial wiring, single conductor wiring, a power bus or wiring, strip wiring, or other wiring. 
       FIG.  2    is a block diagram illustrating an autonomous driving system  200  constructed and operating according to a described embodiment. The autonomous driving system  200  includes a bus, an autonomous driving controller  108  coupled to the bus, and a plurality of autonomous driving sensors  212 A- 212 F coupled to the bus. In the embodiment of  FIG.  2   , the bus includes two primary sections  204 A and  204 B intercoupled by section  205 . The bus may be a twisted pair of conductors, a pair of strip conductors, a coaxial conductor, a two conductor power bus that carries DC power, or another structure having one or two conductors to support communications. 
     A plurality of devices communicates via the bus. These devices include the autonomous driving controller  108 , the plurality of autonomous driving sensors  212 A- 212 F, an infotainment device  214 , memory  216 , a climate control device  218 , a battery controller  220  (when the vehicle is an electric vehicle or hybrid vehicle), an engine/motor controller  222 , a steering controller  224 , a braking controller  226 , and a wireless interface  228  that includes multiple wireless interfaces, e.g., cellular, WiFi, Bluetooth, and/or other standards. The plurality of autonomous driving sensors  212 A- 212 F may include one or more RADAR units, one or more LIDAR units, one or more cameras, and/or one or more proximity sensors. The plurality of autonomous driving sensors  212 A- 212 F collect autonomous driving data and transmit the collected autonomous driving data to the autonomous driving controller  108  via the bus. The autonomous driving controller  108  then processes the data and, based on the processing, controls the driving of the vehicle, either fully or driver assisted, via controllers  222 ,  224 , and  226 . 
       FIG.  3 A  is a block diagram illustrating an autonomous driving sensor constructed according to a described embodiment. The autonomous driving sensor  300  includes data collection component  306  configured to collect autonomous driving data. The data collection component  306  may be a RADAR sensor, a LIDAR sensor, a sonic proximity sensor, or another type of sensor. The autonomous driving sensor  300  further includes processing circuitry  302 , memory  304 , and a transceiver  311  coupled to the processing circuitry  302 , to the memory  304 , and to the data collection component  306  via a bus. The processing circuitry  302  executes programs stored in memory  304 , e.g., autonomous driving emergency operations, reads and writes data from/to memory, e.g., data and instructions to support autonomous driving operations, to interact with the data collection component  306  to control the collection of autonomous driving data, to process the autonomous driving data, and to interact with the transceiver  311  to communicate via the bus, among other operations. 
     By way of example and not limitation, processing circuitry  302  may be a central processing unit, a microcontroller, a digital signal processor, an application specific integrated circuit, a Judging unit, a Determining Unit, an Executing unit, combinations of any of the foregoing, or any other device suitable for execution of computer programs. By way of example, memory  304  may be dynamic memory, static memory, disk drive(s), flash drive(s), combinations of any of the foregoing, or any other form of computer memory. The memory  304  stores computer programs for operations of the present disclosure, may also store other computer programs, configuration information, and other short-term and long-term data necessary for implementation of the embodiments of the present disclosure. 
     The transceiver  311  includes a transmitter  308 , a receiver  310 , and a media I/F  312 . The media I/F  312  may be a transmit/receive (T/R) switch, a duplexer, or other device that supports the illustrated coupling. In other embodiments, both the transmitter  308  and receiver  310  couple directly to the bus or couple to the bus other than via the media I/F  312 . The transceiver  311  supports communications via the bus. The processing circuitry  302  and the transceiver  311  are configured to transmit autonomous driving data to the autonomous driving controller  108  on the bus. 
       FIG.  3 B  is a block diagram illustrating an autonomous driving controller constructed according to a described embodiment. The autonomous driving controller  108  includes general processing circuitry  352 , memory  354 , and a transceiver  361  coupled to the general processing circuitry  352  and configured to communicate with a plurality of autonomous driving sensors via the bus. The autonomous driving controller  108  also includes an autonomous driving parallel processing system  364  that operates on autonomous driving data received from the autonomous driving sensors and supports autonomous driving operations. The transceiver  361  includes a transmitter  358 , a receiver  360 , and a media I/F  362  that in combination support communications via the bus. 
     The construct of the general processing circuitry  352  may be similar to the construct of the processing circuitry  302  of the autonomous driving sensor  300 . The autonomous driving parallel processing system  364  will be described further herein with reference to  FIGS.  4 - 9   . The memory  354  may be of similar structure as the memory  304  of the autonomous driving sensor  300  but with capacity as required to support the functions of the autonomous driving controller  108 . 
       FIG.  4 A  is a block diagram illustrating a first embodiment of an autonomous driving parallel processing system  400  constructed and operating according to the present disclosure. The parallel processing system  400  may be the parallel processing system  364  of  FIG.  3 B . Alternately, the parallel processing system  400  may a separate construct that services the autonomous driving needs of a vehicle. The parallel processing system  400  includes a plurality of parallel processors  402 A,  402 B, . . . ,  402 N, operating on common input data received from the plurality of autonomous driving sensors  212 A- 212 N. Each of the plurality of parallel processors  402 A- 402 N includes a plurality of components, some of which but not all are illustrated in  FIG.  4 A . Further components not illustrated in  FIG.  4 A  (and  FIG.  4 B ) may include internal communication circuitry, e.g., Network on a Chip (NoC) communication circuitry, memory controllers, parallel processor General Interface Channel (GIC) circuitry, one or more network interfaces, Read Only Memory (ROM), e.g., system ROM and secure ROM, Random Access Memory (RAM), e.g., general RAM, cache memory RAM, and secure RAM, watchdog timers, and other communication interfaces, for example. 
     A first parallel processor  402 A includes one or more general processors  404 A, one or more Convolutional Neural Network (CNN) engines  406 A, a Security Processor Subsystem (SCS)  408 A, and a Safety Processor Subsystem (SMS)  410 A. Likewise, a second parallel processor  402 B includes one or more general processors  404 B, one or more CNN engines  406 B, a SCS  408 B, and a SMS  410 B. Finally, an Nth parallel processor  402 N includes one or more general processors  404 N, one or more CNN engines  406 N, a SCS  408 N, and a SMS  410 N. 
     Generally, the SCSs  408 A- 408 N are responsible for the security of the respective plurality of parallel processors  402 A- 402 N. Security functions performed by the SCSs  408 A- 408 N may include authorizing firmware updates, limiting access to memory, authorizing/deauthorizing rights of communication with components external to the plurality of processing systems  402 A- 402 N, and other security functions. The security operations may be performed as a group to secure the operation of the plurality of parallel processors  402 A- 402 N, i.e., startup operations, validating software/firmware updates, monitoring access of the plurality of parallel processors, etc. The group of SCSs  408 A- 408 N may work together to first independently determine whether to authorize an operation and, second, make a group decision that requires agreement of all SCSs  408 A- 408 N before authorization is given. 
     The SMSs  410 A- 410 C are responsible for the safety of autonomous driving by the autonomous driving controller. Because the plurality of parallel processors  402 A- 402 N operate substantially on common input data and produce respective outputs, it is the role of the SMSs  410 A- 410 N to determine whether the respective outputs of the parallel processors  402 A- 402 N are in agreement, and if so, whether to authorize initiation or continuation of autonomous driving. 
     The autonomous driving parallel processing system  364  further includes communication circuitry  412  configured to support communications between the plurality of parallel processors  402 A- 402 N, including communications between the general processors  404 A- 404 N of the plurality of parallel processors  402 A- 402 N and communications between the SCSs  408 A- 408 N of the plurality of parallel processors  402 A- 402 N that are protected by SCS cryptography. Further, the communication circuitry  412  is further configured to support communications between the SMSs  410 A- 410 N of the plurality of parallel processors  402 A- 402 N protected by SMS cryptography, the SMS cryptography differing from the SCS cryptography. With various aspects of the communication circuitry  412 , the communication circuitry  412  may be partially formed in the plurality of parallel processors  402 A- 402 N. 
     The SCS and the SMS cryptography may be any number of differing cryptographies, e.g., public key cryptography, secret key cryptography, or hash key cryptography, for example. The reader will understand that the principles of the present disclosure may be accomplished using many differing types of cryptography. Because the structure and operation of differing cryptographies is generally known, these structures and operations will not be described further herein except as they relate to the principles and teachings of the present disclosure. The SCS and SMS cryptography (and other cryptography) described herein will be done with reference to public key cryptography in which an SCS private key is used to encrypt communications between the SCSs and in which an SMS private key is used to encrypt communications between the SMSs. Private key cryptography may also be used to protect communications between general processors  404 A- 404 N of the plurality of parallel processors  402 A- 402 N, between components of a vehicle  100 A, between vehicles, e.g., between vehicle  100 A and  100 D, and between a vehicle, e.g.,  100 A and the autonomous driving server  16 . 
     The SCS private key may be retrieved from a local memory dedicated to the first SCS  408 A, e.g., ROM, or from the Resistor Transistor Logic (RTL) of the first SCS  408 A. Alternately, the SCS private key may be generated by the first SCS  408 A based upon data retrieved from local memory dedicated to the first SCS. Generation of the SCS private key or retrieval of the SCS private key may be performed by dedicated hardware of the first SCS  408 A. 
     Likewise, the SMS private key may be retrieved from a local memory dedicated to the first SMS  410 A, e.g., ROM or from the RTL of the first SMS  410 A. Alternately, the SMS private key may be generated by the first SMS  410 A based upon data retrieved from the local memory dedicated to the first SMS  410 A. Generation of the SMS private key or retrieval of the SMS private key may be performed by dedicated hardware of the first SMS  410 A. 
     According to an aspect of the present disclosure, the plurality of parallel processors  402 A- 402 N may be configured such that a second SCS  408 B is configured to store a SCS private key received from another SCS  408 A in local memory dedicated to the SCS  408 A. Likewise, a second SMS  410 B may be configured to store a SMS private key received from another SMS  410 A in local memory dedicated to the SMS  410 B. 
     According to another aspect of the present disclosure, each of the plurality of parallel processors  402 A- 402 N includes dedicated SCS cryptography hardware corresponding to their SCSs  408 A-N. According to still another aspect of the present disclosure, each of the plurality of parallel processors  402 A- 402 N includes dedicated SMS cryptography hardware corresponding to their SMSs  410 A- 410 N. 
     According to a slightly different aspect, a first parallel processor  402 A may include an SCS  408 A that includes dedicated SCS memory and/or SCS cryptography hardware. In such case, the SCS  408 A retrieves the SCS private key from its dedicated memory or generates the SCS private key and distributes the SCS private key to the other SCSs  408 B- 408 N. In such case, one or more of the other SCSs  408 - 408 N do not have dedicated SCS memory or SCS cryptography hardware. These same aspects may be applied to the SMSs  410 A- 410 N of the plurality of parallel processors  402 A- 402 N. 
     In establishing the SCS cryptography, a first SCS, e.g.,  408 A, of a first parallel processor  402 A of the plurality of parallel processors  402 A- 402 N may be configured to establish a private communication link with a second SCS  408 B of a second parallel processor  402 B of the plurality of parallel processors  402 A- 402 N and use the private communication link to transmit a SCS private key to the second SCS  408 B of the second parallel processor  402 B for subsequent use in communications protected by the SCS cryptography. In establishing the private communication link with the second SCS  408 B of the second parallel processor  402 B of the plurality of parallel processors, the first SCS  408 A of the first parallel processor  402 A may use dedicated SCS cryptography hardware of the first SCS  408 A and the second SCS  408 B of the second parallel processor  402 B may use dedicated SCS cryptography hardware of the second SCS  408 B. These operations will be described further herein with reference to  FIGS.  6 A,  6 B,  6 C,  7  and  8   . As will be described therewith, in establishing the private communication link with the second SCS of the second parallel processor of the plurality of parallel processors, the first SCS may use one or more of the Diffie-Hellman algorithm and/or a Rivest-Shamir-Adleman (RSA) algorithm. 
     The autonomous driving parallel processing system  400  may have a number of differing physical constructs. According to one construct, the plurality of parallel processors  402 A- 402 B is formed on a single System on a Chip integrated circuit (SOC). With this construct, the communication circuitry  412  may also be formed on the SOC. With another construct, the plurality of parallel processors is formed on differing respective integrated circuits. Further, with still another construct, a first group of the plurality of parallel processors  402 A- 402 N is formed on a first integrated circuit and a second group of the plurality of parallel processors  402 A- 402 N is formed on a second integrated circuit. Of course, other physical constructs may be formed without departing from the scope of the present disclosure. 
     According to another aspect of the present disclosure, the communication circuitry supports intra-vehicle communications among the plurality of autonomous driving sensors  212 A- 212 N and the autonomous driving controller  202  using intra-vehicle cryptography that differs from the SCS cryptography and the SMS cryptography. Further, according to still another aspect of the present disclosure, wherein the communication circuitry supports extra-vehicle communications using extra-vehicle cryptography that differs from both the intra-vehicle cryptography and the SCS cryptography and the SMS cryptography. 
       FIG.  4 B  is a block diagram illustrating a second embodiment of an autonomous driving parallel processing system  450  constructed and operating according to the present disclosure. The autonomous driving parallel processing system  450  may be the autonomous driving parallel processing system  364  of  FIG.  3 B  or may be a separate construct. As contrasted to the structure of  FIG.  4 A , the autonomous driving parallel processing system  450  of  FIG.  4 B  includes a SOC for each parallel processor  452 A- 452 N. Further, the communication circuitry  453 A- 453 N resides, respectively, in the plurality of parallel processors  452 A- 452 N. The parallel processing system may service all autonomous driving needs of a vehicle. 
     The parallel processing system  450  includes a plurality of parallel processors  452 A,  452 B, . . . ,  452 N, operating on common input data received from the plurality of autonomous driving sensors  212 A- 212 N. The parallel processing system  450  also provides output data to vehicle controllers  220 ,  222 ,  226 , and  224 . This output data may be provided by agreement among the plurality of parallel processors  452 A- 452 N or by a designated parallel processor of the plurality of parallel processors  452 A- 452 N. 
     Each of the plurality of parallel processors  452 A- 452 N may include components not illustrated in  FIG.  4 A  and which may include internal communication circuitry, e.g., Network on a Chip (NoC) communication circuitry, memory controllers, parallel processor General Interface Channel (GIC) circuitry, one or more network interfaces, Read Only Memory (ROM), e.g., system ROM and secure ROM, Random Access Memory (RAM), e.g., general RAM, cache memory RAM, and secure RAM, watchdog timers, and other communication interfaces, for example. 
     A first parallel processor  452 A includes communication circuitry  453 A, one or more general processors  454 A, one or more CNN engines  456 A, a SCS  458 A, and a SMS  460 A. Likewise, a second parallel processor  452 B includes communication circuitry  453 B, one or more general processors  454 B, one or more CNN engines  456 B, a SCS  458 B, and a SMS  460 B. Finally, an Nth parallel processor  452 N includes communication circuitry  453 N, one or more general processors  454 N, one or more CNN engines  456 N, a SCS  458 N, and a SMS  460 N. 
     The communication circuitry  453 A- 453 N is configured to support communications between the plurality of parallel processors  452 A- 452 N, including communications between the general processors  454 A- 454 N of the plurality of parallel processors  452 A- 452 N and communications between the SCSs  458 A- 458 N of the plurality of parallel processors  452 A- 452 N that are protected by SCS cryptography. Further, the communication circuitry  453 A- 453 N is further configured to support communications between the SMSs  460 A- 460 N of the plurality of parallel processors  452 A- 452 N protected by SMS cryptography, the SMS cryptography differing from the SCS cryptography. With various aspects of the communication circuitry  462 , the communication circuitry  453 A- 453 N may be partially formed external to the plurality of parallel processors  452 A- 452 N. 
     The SCS and the SMS cryptography of the parallel processing system  450  of  FIG.  4 B  may be same similar as the SCS and SMS cryptography described with reference to  FIG.  4 A . Further, the particular structures and operations of the SCS and SMS of the parallel processing system  450  of  FIG.  4 B  may be same or similar to those of  FIG.  4 A . Moreover, public key cryptography may also be used to protect communications between general processors  454 A- 454 N of the plurality of parallel processors  452 A- 452 N, between components of a vehicle  100 A, between vehicles, e.g., between vehicle  100 A and  100 D, and between a vehicle, e.g.,  100 A and the autonomous driving server  16 . 
     The SCS private key may be retrieved from a local memory dedicated to the first SCS  458 A, e.g., ROM, or from the Resistor Transistor Logic (RTL) of the first SCS  458 A. Alternately, the SCS private key may be generated by the first SCS  458 A based upon data retrieved from local memory dedicated to the first SCS. Generation of the SCS private key or retrieval of the SCS private key may be performed by dedicated hardware of the first SCS  458 A. 
     Likewise, the SMS private key may be retrieved from a local memory dedicated to the first SMS  460 A, e.g., ROM or from the RTL of the first SMS  460 A. Alternately, the SMS private key may be generated by the first SMS  460 A based upon data retrieved from the local memory dedicated to the first SMS  460 A. Generation of the SMS private key or retrieval of the SMS private key may be performed by dedicated hardware of the first SMS  460 A. 
     According to an aspect of the present disclosure, the plurality of parallel processors  452 A- 452 N may be configured such that a second SCS  458 B is configured to store a SCS private key received from another SCS  458 A in local memory dedicated to the SCS  458 A. Likewise, a second SMS  460 B may be configured to store a SMS private key received from another SMS  460 A in local memory dedicated to the SMS  460 B. 
     In establishing the SCS cryptography, a first SCS, e.g.,  458 A, of a first parallel processor  452 A of the plurality of parallel processors  452 A- 452 N may be configured to establish a private communication link with a second SCS  458 B of a second parallel processor  452 B of the plurality of parallel processors  452 A- 452 N and use the private communication link to transmit a SCS private key to the second SCS  458 B of the second parallel processor  452 B for subsequent use in communications protected by the SCS cryptography. In establishing the private communication link with the second SCS  458 B of the second parallel processor  452 B of the plurality of parallel processors, the first SCS  458 B of the first parallel processor  452 A may use dedicated SCS cryptography hardware of the first SCS  458 B and the second SCS  458 B of the second parallel processor  452 B may use dedicated SCS cryptography hardware of the second SCS  458 B. These operations will be described further herein with reference to  FIGS.  6 A,  6 B,  6 C,  7  and  8   . As will be described therewith, in establishing the private communication link with the second SCS of the second parallel processor of the plurality of parallel processors, the first SCS may use one or more of the Diffie-Hellman algorithm and/or the RSA algorithm. 
     With the construct of  FIG.  4 B , the plurality of parallel processors  452 A- 452 N are formed as a plurality of SOCs. According to another aspect of the present disclosure, the communication circuitry supports intra-vehicle communications among the plurality of autonomous driving sensors  212 A- 212 N and the autonomous driving controller  450  using intra-vehicle cryptography that differs from the SCS cryptography. Further, according to still another aspect of the present disclosure, wherein the communication circuitry supports extra-vehicle communications using extra-vehicle cryptography that differs from both the intra-vehicle cryptography and the SCS cryptography. 
       FIG.  5 A  is a block diagram illustrating communications among components of the autonomous driving parallel processors of  FIGS.  4 A and/or  4 B  ( 400  and  450 ). Shown are three parallel processors  402 A,  402 B, and  402 C that service communications among their general processors  404 A- 404 C, among their SCSs  408 A- 408 C, and among their SMSs  410 A- 410 C in differing manners. From one viewpoint, different roots of trust are established between differing sets of components. A first root of trust is established among the general processors  404 A,  404 B, and  404 C of the parallel processors  402 A,  402 B, and  402 C. This root of trust among the general processors  404 A,  404 B, and  404 C may be established so that communications therebetween are not encrypted. Alternately, the root of trust among the general processors  404 A,  404 B, and  404 C may be established on a vehicle wide basis such that a shared public key/private key pair is used by all components within the vehicle to protect intra-vehicle communications, e.g., between the general processors  404 A,  404 B, and  404 C and the autonomous driving sensors  212 A- 212 N. The first root of trust is then used to support general processor communications  502  between the general processors  404 A,  404 B, and  404 C. 
     Further, another root of trust is established among the SCSs  408 A,  408 B, and  408 C that uses an SCS public/private key pair. The SCS private key (and SCS public key) may be hard wired, e.g., ROM or RTL, in one of the SCSs  408 A,  408 B, or  408 C. The SCS private key is then distributed among the other SCSs  408 B and  408 C of the parallel processing system, which is subsequently used for all SCS communications  504  between the SCSs  408 A- 408 C. 
     Additionally, another root of trust is established among the SMSs  410 A,  410 B, and  410 C that uses an SMS public/private key pair that is different from the SCS public/private key pair. The SMS private key (and SMS public key) may be hard wired, e.g., ROM or RTL, in one of the SMSs  410 A,  410 B, or  410 C. The SMS private key is then distributed among the other SMSs  410 B and  410 C of the parallel processing system, which is subsequently used for all SMS communications  506  between the SMSs  410 A- 410 C. 
     The same or differing encryption types may be used for the differing roots of trust. For example, a weak encryption may be used for the general processor communications  502  with stronger encryption used for the SCS communications  504  and the SMS communications  506 . Further, with some aspects, a strongest encryption is used for the SCS communications  504  because the SCSs are the most secure components of the parallel processing system. 
       FIG.  5 B  is a block diagram illustrating components of a parallel processor of the autonomous driving parallel processors of  FIGS.  4 A and/or  4 B  according to one or more aspects of the described embodiments. A parallel processor  550  includes one or more general processors  552 , communication circuitry  558 , one or more CNN engines  560 , a SCS  562 , and a SMS  576 . The general processors include local RAM  554  and local ROM  556 . The communication circuitry  558  is configured to support communications between the parallel processor  550  and other parallel processors and between the parallel processor  550  and other components external to the parallel processor  550 . RAM  590  services the parallel processor  550  and stores data that may include public/private keys  592 . The ROM  594  services the parallel processor  550  and stores data that may include public/private keys  596 . 
     The parallel processor  550  further includes CNN engine(s)  506 , a SCS  562  and a SMS  576 . The SCS  562  includes dedicated RAM  564  that may be used to store public/private keys  566 . Further, the SCS  562  further includes dedicated ROM  568  and RTL  572  that may store public/private keys  570  and  574 , respectively. The SCS  562  may further include dedicated SCS cryptography hardware  573  that supports the SCS cryptography operations according to the present disclosure, and which may include key generation, communication encryption, and communication decryption operations. 
     Likewise, the SMS  576  further includes dedicated RAM  578  that may be used to store public/private keys  580 . Further, the SMS  576  further includes dedicated ROM  582  and RTL  586  that may store public/private keys  584  and  588 , respectively. The RTL  572  and  586  are hard programmed during manufacture of the parallel processor  550  and the ROM  568  and  582  may be programmed during provisioning of the parallel processor  550 . The SMS  576  may further include dedicated SMS cryptography hardware  577  that supports the SMS cryptography operations according to the present disclosure, and which may include key generation, communication encryption, and communication decryption operations. 
     The parallel processor  550  supports SCS and the SMS cryptography that may be same/similar as the SCS and SMS cryptography described with reference to  FIGS.  4 A,  4 B and  5 A . Further, the parallel processor  550  also supports general processor  552  communications as were previously described herein with reference to other structure(s). 
     Consistent with the previously described operations, the SCS private key may be retrieved from the ROM  568  or the RTL  572 . Alternately, the SCS private key may be generated by the SCS  562  based upon data retrieved from the ROM  568  or RTL  572 . Generation of the SCS private key or retrieval of the SCS private key may be performed by dedicated hardware  573  of the SCS  562 . 
     Likewise, the SMS private key may be retrieved from the ROM  582  or the RTL  586 . Alternately, the SMS private key may be generated by the SMS  576  based upon data retrieved from the ROM  582  or RTL  586 . Generation of the SMS private key or retrieval of the SMS private key may be performed by dedicated SMS circuitry  577  of the SMS  576 . 
       FIG.  6 A  is a flow diagram illustrating operations of an autonomous driving controller to establish secure communications among a plurality of SCSs according to one or more described embodiments. According to the operations  600  of  FIG.  6 A , a first SCS of a corresponding parallel processor of a parallel processing system of the autonomous driving controller accesses an SCS private key from ROM or RTL (Step  602 ). The first SCS may use its dedicated SCS hardware to access the SCS private key. Operations  600  continue with the first SCS establishing secure communication paths with the other SCSs of the parallel processing system (Step  604 ). The operations of Step  604  may also be performed using dedicated hardware of the SCSs. Operations  600  continue with the first SCS transmitting the SCS private key to the other SCSs using the established secure communication paths (Step  606 ). Step  606  may also be performed using dedicated hardware of the SCSs. With the SCS private key distributed, operations conclude with the SCSs communicating with one another using the SCS private key (Step  608 ). Step  608  as well may be performed by the SCSs using dedicated hardware. 
       FIG.  6 B  is a flow diagram illustrating differing operations of an autonomous driving controller to establish secure communications among a plurality of Security Processor Subsystems (SCSs) according to one or more described embodiments. According to the operations  620  of  FIG.  6 B , a first SCS of a corresponding parallel processor of a parallel processing system of the autonomous driving controller generates an SCS private key (Step  622 ). The SCS private key may be generated based upon data retrieved from ROM or RTL. Further, the first SCS may use its dedicated SCS hardware to generate the SCS private key. 
     Operations  620  continue with the first SCS establishing secure communication paths with the other SCSs of the parallel processing system (Step  624 ). The operations of Step  624  may also be performed using dedicated hardware of the SCSs. Operations  620  continue with the first SCS transmitting the SCS private key to the other SCSs using the established secure communication paths (Step  626 ). Step  626  may also be performed using dedicated hardware of the SCSs. With the SCS private key distributed, operations conclude with the SCSs communicating with one another using the SCS private key (Step  628 ). Step  628  as well may be performed by the SCSs using dedicated hardware. 
     The operations  600  of  FIG.  6 A  and the operations  620  of  FIG.  6 B  may be performed also for the SMSs. In such case, the SMSs would perform operations the same as, similar to, or equivalent to the operations  600  and  620  of  FIGS.  6 A and  6 B , respectively. 
       FIG.  6 C  is a flow diagram illustrating operations of an autonomous driving controller to establish secure communications among a plurality of SCSs and a plurality of SMSs according to one or more described embodiments. The operations  650  commence with a first SCS of a first parallel processor of the plurality of parallel processors acquiring an SCS private key (Step  654 ). The SCS private key may be retrieved from memory, e.g., ROM, or from RTL, for example. Alternately, the SCS may generate the SCS private key using data retrieved from memory or from RTL. Operations  650  continue with the first SCS securely distributing the SCS private key to other SCSs of other parallel processors of the plurality of parallel processors (Step  656 ). Steps  654  and  656  may be performed using dedicated hardware and/or dedicated memory of the first SMS. 
     The operations  650  continue with a first SMS of the first parallel processor of the plurality of parallel processors acquiring an SMS private key, wherein the SMS private key differs from the SCS private key (Step  658 ). The SMS private key may be retrieved from memory, e.g., ROM, or from RTL, for example. Alternately, the SMS may generate the SMS private key using data retrieved from memory or from RTL. Operations  650  continue with the first SMS securely distributing the SMS private key to other SMSs of other parallel processors of the plurality of parallel processors (Step  660 ). Steps  656  and  658  may be performed using dedicated hardware and/or dedicated memory of the first SMS. 
     Operations  650  continue with the first SCS communicating with the other SCSs of the other parallel processors of the plurality of parallel processors using SCS cryptography based on the SCS private key (Step  662 ) and conclude with the first SMS communicating with the other SMSs of the other parallel processors of the plurality of parallel processors using SMS cryptography based on the SMS private key (Step  664 ). The operations  650  of  FIG.  6 C  may be performed using dedicated hardware and/or dedicated memory of the first SCS and/or the first SMS. 
       FIG.  7    is a flow diagram illustrating operations of an autonomous driving controller to distribute an SCS private key according to one or more described embodiments. Operations  700  begin at startup or reset and commence with each SCS of parallel processors of the autonomous driving controller generating a public/private key pair (Step  704 ). Thus, after the conclusion of Step  704 , each SCS has respective public/private key pairs, which may be generated using dedicated hardware and/or dedicated memory. The SCSs then share their public keys with one another (Step  706 ). Then, a first SCS establishes private communication links with the other SCSs using a privacy algorithm (Step  708 ). Step  708  may implement the Diffie-Hellman algorithm, which uses public/private key pairs of differing SCSs to establish a shared secret word between SCSs that is used to encrypt communications there between. 
     Operations  700  continue with the first SCS accessing or generating a SCS private key (Step  710 ). As was previously discussed, the SCS private key may be accessed from ROM or the RTL if programmed. Alternately, the SCS may generate the SCS private key using data accessed from ROM or RTL. The first SCS then distributes the SCS private key to each other of the SCSs using the private communication links (Step  712 ). The SCSs then use the SCS private key to encrypt communications between one another (Step  714 ). The SMSs may use a technique that is the same, similar, or equivalent to the operations  700  of  FIG.  7    to establish encrypted communications there between. 
       FIG.  8    is a flow diagram illustrating second operations of an autonomous driving controller to distribute an SCS private key according to one or more described embodiments. Operations  800  begin at startup or reset and commence with each SCS of parallel processors of the autonomous driving controller generating RSA public keys (and corresponding decryption keys) using an RSA algorithm (Step  804 ). Thus, after the conclusion of Step  804 , each SCS has a respective public key, which may be generated using dedicated hardware and/or dedicated memory. The SCSs then share their RSA public keys with one another (Step  806 ). 
     Operations  800  continue with the first SCS accessing or generating a SCS private key (Step  808 ). As was previously discussed, the SCS private key may be accessed from ROM or the RTL if programmed. Alternately, the SCS may generate the SCS private key using data accessed from ROM or RTL. The first SCS then distributes the SCS private key to each other of the SCSs by encrypting the SCS private key with the respective RSA key of each other SCS and transmits the respectively encrypted SCS private keys (Step  810 ). The other SCSs receive and decrypt the SCS private keys using respective data that was used to create their private keys of using an RSA decryption key that they generated (Step  812 ). The SCSs then use the SCS private key to encrypt communications between one another (Step  814 ). The SMSs may use a technique that is the same, similar, or equivalent to the operations  800  of  FIG.  8    to establish encrypted communications there between. 
       FIG.  9    is a flow diagram illustrating operations of an autonomous driving controller to distribute and validate SCSs private key according to one or more described embodiments. The operations  900  of  FIG.  9    support validation of an SCS private key. Operations  900  begin with multiple SCSs accessing SCS private keys from ROM/RTL (Step  902 ). Step  902  may be performed using dedicated hardware of the SCSs. Operations continue with multiple SCSs establishing secure communication paths with other SCSs (step  904 ). Step  904  may be performed consistently with the operations  700  of  FIG.  7    and/or use dedicated hardware. Then, the multiple SCSs transmit their respectively accessed SCS private keys to all other of the SCSs using the secure communication paths (Step  906 ). The other SCSs receive the SCS keys via the secure communication paths (Step  908 ). The other SCSs then validate the received SCS private keys by comparing all of the SCS private keys they receive to one another (Step  910 ). With the validation complete, the SCSs communicate with one another using the SCS private key (Step  912 ). All of these steps  902 - 912  may be performed using hardware dedicate to the SCS 
     In a simplest implementation, a first and a second SCS access respective SCS private keys that are presumably identical. However, whether these SCS private keys are identical is not known to the SCSs. Thus, each of the first and second SCSs distribute the SCS private key they access to all of the other SCSs. The first SCS receives a SCS private key from the second SCS and compares the received SCS private key to the private key it accessed locally. Likewise, the second SCS receives a SCS private key from the first SCS and compares the received SCS private key to the private key it accessed locally. The other SCSs receive private SCS keys from each of the first SCS and the second SCS and compare the keys they receive to each other. If the SCS private keys compare favorably to one another, the SCS private key distribution is deemed successful. These same techniques may be employed with the SMS private key. 
     In the foregoing specification, the disclosure has been described with reference to specific embodiments. However, as one skilled in the art will appreciate, various embodiments disclosed herein can be modified or otherwise implemented in various other ways without departing from the spirit and scope of the disclosure. Accordingly, this description is to be considered as illustrative and is for the purpose of teaching those skilled in the art the manner of making and using various embodiments of the disclosed system, method, and computer program product. It is to be understood that the forms of disclosure herein shown and described are to be taken as representative embodiments. Equivalent elements, materials, processes or steps may be substituted for those representatively illustrated and described herein. Moreover, certain features of the disclosure may be utilized independently of the use of other features, all as would be apparent to one skilled in the art after having the benefit of this description of the disclosure. 
     Routines, methods, steps, operations, or portions thereof described herein may be implemented through electronics, e.g., one or more processors, using software and firmware instructions. A “processor” or “processing circuitry” includes any hardware system, hardware mechanism or hardware component that processes data, signals or other information. A processor can include a system with a central processing unit, multiple processing units, dedicated circuitry for achieving functionality, or other systems. Some embodiments may be implemented by using software programming or code in one or more digital computers or processors, by using application specific integrated circuits (ASICs), programmable logic devices, field programmable gate arrays (FPGAs), optical, chemical, biological, quantum or nano-engineered systems, components and mechanisms. Based on the disclosure and teachings representatively provided herein, a person skilled in the art will appreciate other ways or methods to implement the invention. 
     As used herein, the terms “comprises,” “comprising,” “includes,” “including,” “has,” “having” or any contextual variants thereof, are intended to cover a non-exclusive inclusion. For example, a process, product, article, or apparatus that comprises a list of elements is not necessarily limited to only those elements, but may include other elements not expressly listed or inherent to such process, product, article, or apparatus. Further, unless expressly stated to the contrary, “or” refers to an inclusive or and not to an exclusive or. For example, a condition “A or B” is satisfied by any one of the following: A is true (or present) and B is false (or not present), A is false (or not present) and B is true (or present), and both A and B is true (or present). 
     Although the steps, operations, or computations may be presented in a specific order, this order may be changed in different embodiments. In some embodiments, to the extent multiple steps are shown as sequential in this specification, some combination of such steps in alternative embodiments may be performed at the same time. The sequence of operations described herein can be interrupted, suspended, reversed, or otherwise controlled by another process. 
     It will also be appreciated that one or more of the elements depicted in the drawings/figures can also be implemented in a more separated or integrated manner, or even removed or rendered as inoperable in certain cases, as is useful in accordance with a particular application. Additionally, any signal arrows in the drawings/figures should be considered only as exemplary, and not limiting, unless otherwise specifically noted.