Patent Publication Number: US-2023154954-A1

Title: Semiconductor package

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This is a Continuation Application of U.S. application Ser. No. 16/996,058 filed on Aug. 18, 2020, which claims priority from Korean Patent Application No. 10-2019-0172320 filed on Dec. 20, 2019 in the Korean Intellectual Property Office, the disclosures of which are hereby incorporated by reference in their entireties. 
    
    
     BACKGROUND 
     1. Field 
     Apparatuses and methods consistent with example embodiments relate to a semiconductor package, and more particularly, to a semiconductor package including a complementary metal oxide semiconductor (CMOS) image sensor. 
     2. Related Art 
     An image sensor is a semiconductor device that converts optical images into electrical signals. The image sensor may be broadly classified as a charge coupled device (CCD) type image sensor and a complementary metal oxide semiconductor (CMOS) type image sensor (also referred to as CIS). The image sensor is used for cameras, camcorders, multimedia personal computers, and surveillance cameras, and its usage has dramatically increased. 
     Reliability of electronic devices is increasingly important. Therefore, there is a need for an image sensor with improved structural stability and improved sensitivity. 
     SUMMARY 
     One or more example embodiments provide a semiconductor package with improved structural stability. 
     One or more example embodiments provide a semiconductor package with increased sensitivity. 
     Example embodiments are not limited to the mentioned above, and other objects which have not been mentioned above will be clearly understood to those skilled in the art from the following description. 
     According to an aspect of an example embodiment, there is provided a semiconductor package. The semiconductor package includes: a semiconductor chip that includes a plurality of photoelectric conversion elements provided on an active array region of the semiconductor chip; a transparent member on the semiconductor chip; and a spacer between the semiconductor chip and the transparent member, and horizontally spaced apart from the active array region. The spacer includes: a supporter that extends from a top surface of the semiconductor chip toward a bottom surface of the transparent member; a first adhesive pattern that is between the semiconductor chip and a bottom surface of the supporter; and a second adhesive pattern that is between the transparent member a top surface of the supporter. The spacer protrudes outwardly from a lateral surface of the semiconductor chip, and a lateral surface of the spacer is offset from the lateral surface of the semiconductor chip. 
     According to an aspect of an example embodiment, there is provided a semiconductor package. The semiconductor package includes: a semiconductor chip that includes a plurality of photoelectric conversion elements provided on an active array region of the semiconductor chip; a transparent member on the semiconductor chip; and a spacer between the semiconductor chip and the transparent member, and horizontally spaced apart from the active array region. The spacer includes: a supporter that extends from a top surface of the semiconductor chip toward a bottom surface of the transparent member; and an adhesive layer on a lateral surface of the supporter. A first end of the adhesive layer extends from the lateral surface of the supporter to contact a lateral surface of the semiconductor chip, a second end of the adhesive layer contacts the bottom surface of the transparent member, the second end being opposite to the first end, and the spacer protrudes outwardly from the lateral surface of the semiconductor chip, and a lateral surface of the spacer is offset from the lateral surface of the semiconductor chip. 
     According to an aspect of an example embodiment there is provided a semiconductor package that includes: a first semiconductor chip; a second semiconductor chip on the first semiconductor chip, the second semiconductor chip including a through electrode and a plurality of photoelectric conversion elements; a plurality of color filters on a top surface of the second semiconductor chip and arranged to correspond to the plurality of photoelectric conversion elements; a plurality of micro-lenses on the color filters; a transparent member spaced apart from the top surface of the second semiconductor chip; and a spacer that connects the second semiconductor chip to the transparent member. The spacer includes: a supporter along an outer edge of the second semiconductor chip, the supporter surrounding the plurality of micro-lenses; a first adhesive pattern between the supporter and the second semiconductor chip; and a second adhesive pattern between the supporter and the transparent member. A lateral surface of the spacer is spaced apart from a lateral surface of the second semiconductor chip, and a modulus of the supporter is greater than a modulus of the second semiconductor chip. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIGS.  1  and  2    illustrate cross-sectional views showing a semiconductor package according to some example embodiments. 
         FIG.  3    illustrates a plan view showing a semiconductor package according to some example embodiments. 
         FIGS.  4  and  5    illustrate cross-sectional views showing a semiconductor package according to some example embodiments. 
         FIG.  6    illustrates a plan view showing a semiconductor package according to some example embodiments. 
         FIG.  7    illustrates a cross-sectional view showing a semiconductor package according to some example embodiments. 
         FIGS.  8  and  9    illustrate cross-sectional views showing a semiconductor package according to some example embodiments. 
         FIGS.  10  to  15    illustrate diagrams showing a method of fabricating a semiconductor package according to some example embodiments. 
         FIGS.  16  to  20    illustrate diagrams showing a method of fabricating a semiconductor package according to some example embodiments. 
     
    
    
     DETAILED DESCRIPTION 
     The above and other aspects and features will become more apparent by describing in detail example embodiments with reference to the accompanying drawings. It will be understood that when an element or layer is referred to as being “over,” “above,” “on,” “connected to” or “coupled to” another element or layer, it can be directly over, above, on, connected or coupled to the other element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly over,” “directly above,” “directly on,” “directly connected to” or “directly coupled to” another element or layer, there are no intervening elements or layers present. Like numerals refer to like elements throughout. 
       FIGS.  1  and  2    illustrate cross-sectional views showing a semiconductor package according to some example embodiments.  FIG.  3    illustrates a plan view showing a semiconductor package according to some example embodiments, and  FIG.  1    corresponds to a cross-section taken along line I-I′ of  FIG.  3   .  FIG.  4    illustrates a cross-sectional view showing a semiconductor package according to some example embodiments. 
     Referring to  FIGS.  1  and  3   , an image sensor part IS may include a first semiconductor chip  100  and a second semiconductor chip  200 . The second semiconductor chip  200  may be a sensing chip. For example, the second semiconductor chip  200  may include a photodiode that detects light. The first semiconductor chip  100  may include a logic chip that converts the light detected by the second semiconductor chip  200  into an electrical signal. 
     The first semiconductor chip  100  may be disposed below the second semiconductor chip  200 . The first semiconductor chip  100  may include a first semiconductor layer  110 , a first circuit layer  120 , a first via  130 , and a first bonding pad  140 . The first semiconductor layer  110  may include a semiconductor material, for example, silicon (Si), silicon germanium (SiGe), or impurity-doped semiconductor. The first semiconductor layer  110  may be provided therein with integrated circuits. For example, the integrated circuits may be logic devices. The first circuit layer  120  may be provided on the first semiconductor layer  110 . The first circuit layer  120  may include a wiring pattern. The first circuit layer  120  may be electrically connected to the integrated circuits in the first semiconductor layer  110 . The first via  130  may penetrate the first semiconductor layer  110  and have electrical connection with the first circuit layer  120 . In this description, the phrase “electrically connected/coupled to” may include “directly or indirectly electrically connected/coupled to.” The first bonding pad  140  may be disposed on a top surface of the first semiconductor chip  100 . For example, the top surface of the first semiconductor chip  100  may be an active surface. The first circuit layer  120 , the first via  130 , and the first bonding pad  140  may include a metallic material, such as copper (Cu), aluminum (Al), nickel (Ni), or tungsten (W). 
     A redistribution layer  150  may be provided below the first semiconductor chip  100 . The redistribution layer  150  may include dielectric layers  152  and a redistribution pattern  154 . The redistribution pattern  154  may include a conductive layer and conductive vias. The redistribution pattern  154  may be electrically connected to the first semiconductor chip  100 . Portions of the redistribution pattern  154  may be exposed on surfaces of the dielectric layers  152 , thereby serving as pads on which external terminals  156  are disposed. 
     The external terminals  156  may be provided on a bottom surface of the redistribution layer  150 . The external terminals  156  may each have a solder ball shape or a solder bump shape. The external terminal  156  may be electrically connected through the redistribution layer  150  to the first semiconductor chip  100 . 
     The second semiconductor chip  200  may be disposed on the first semiconductor chip  100 . The second semiconductor chip  200  may include a second semiconductor layer  210 , a second circuit layer  220 , a second via  230 , a second bonding pad  240 , color filters CF, and micro-lenses ML. The second semiconductor layer  210  may include a semiconductor material, such as silicon, silicon germanium, or impurity-doped semiconductor. The second semiconductor layer  210  may be provided therein with photoelectric conversion elements PD. Each of the photoelectric conversion elements PD may independently receive light irradiated from a top surface of the second semiconductor chip  200 . The photoelectric conversion elements PD may each have a conductivity type different from that of the second semiconductor layer  210 . The second circuit layer  220  may be disposed below the second semiconductor chip  200 , thereby being adjacent to the first semiconductor chip  100 . The second circuit layer  220  may include wiring patterns and integrated circuits such as transistors for driving the photoelectric conversion elements PD. The second circuit layer  220  may be electrically connected to the photoelectric conversion elements PD in the second semiconductor layer  210 . The second via  230  may penetrate the second semiconductor layer  210  and have electrical connection with the second circuit layer  220 . The second bonding pad  240  may be disposed on a bottom surface of the second semiconductor chip  200 . For example, the bottom surface of the second semiconductor chip  200  may be an active surface. The second circuit layer  220 , the second via  230 , and the second bonding pad  240  may include a metallic material, such as copper (Cu), aluminum (Al), nickel (Ni), or tungsten (W). 
     The second bonding pad  240  may be in contact with the first bonding pad  140 . Therefore, the second semiconductor chip  200  may be electrically connected to the first semiconductor chip  100  through the first bonding pad  140  and the second bonding pad  240 . The second via  230  may penetrate at least a portion of the second semiconductor chip  200 . The second via  230  may penetrate the second semiconductor chip  200  and have electrical connection with the first semiconductor chip  100 . Alternatively, the second via  230  may penetrate a portion of the second semiconductor chip  200  and have electrical connection with the second semiconductor chip  200 . 
     The color filters CF may be disposed on a top surface of the second semiconductor layer  210 . The color filters CF may be disposed to correspond to the photoelectric conversion elements PD. The color filters CF may include one or more of red, green, blue, and white colors. The micro-lenses ML may be disposed on the color filters CF. A unit pixel P may be defined by a single color filter CF, a single micro-lens ML that corresponds to the single color filter CF, and at least one photoelectric conversion element PD that corresponds to the single color filter CF and the single micro-lens ML. A plurality of unit pixels P may be two-dimensionally arranged on the top surface of the second semiconductor layer  210 . The second semiconductor layer  210  may include the unit pixels P at its central portion that is defined as an active array region AAR. For example, when viewed in plan, the active array region AAR may be a section where the micro-lenses ML are exposed by a transparent member  500  which will be discussed below. The active array region AAR may have a planar area of about 5.350 mm×4.045 mm. The second semiconductor layer  210  may not include the unit pixels P along its outer edge that is defined as an adhesive region to which is adhered a spacer which will be discussed below. 
     In other example embodiments, the image sensor part IS may further include third semiconductor chips  300 . As shown in  FIG.  2   , the image sensor part IS may include at least one third semiconductor chip  300  provided below the first semiconductor chip  100 . The third semiconductor chips  300  may be spaced apart from each other. 
     The third semiconductor chips  300  may include a memory chip, such as dynamic random access memory (DRAM), static random access memory (SRAM), magnetic random access memory (MRAM), or Flash memory. The third semiconductor chips  300  may include a semiconductor material, such as silicon (Si) or germanium (Ge). The third semiconductor chips  300  may include integrated circuits. For example, the integrated circuits may be a memory device, a logic device, or a passive device (e.g., capacitor). Top surfaces of the third semiconductor chips  300  may be active surfaces. For example, the third semiconductor chips  300  may each include a third circuit layer  310  and a third bonding pad  320  on an upper portion thereof. The third circuit layers  310  may include wiring patterns. The third bonding pads  320  may be electrically connected to the integrated circuits in the third semiconductor chips  300 . The third semiconductor chips  300  may be the same chip. Alternatively, one of the third semiconductor chips  300  may be a memory chip, and another of the third semiconductor chips  300  may be a dummy chip. For example, the another third semiconductor chip  300  that constitutes the dummy chip may have either a single-layered structure made of a single material or a multi-layered structure made of a plurality of different materials. The dummy chip may include polysilicon or bulk metal. Alternatively, the third semiconductor chips  300  may each include a memory chip, a logic chip, a passive device, a dummy chip, or a combination thereof. 
     The third semiconductor chips  300  may each be electrically connected to the redistribution layer  150  through a connection terminal  330 . For example, the connection terminal  330  may be provided between the redistribution pattern  154  of the redistribution layer  150  and the third bonding pad  320  of the third semiconductor chip  300 . 
     A molding layer  400  may be provided between the redistribution layer  150  and the third semiconductor chips  300 . The molding layer  400  may cover the third semiconductor chips  300 . The molding layer  400  may fill a space between the third semiconductor chips  300 . The molding layer  400  may not cover bottom surfaces of the third semiconductor chips  300 . The molding layer  400  may prevent the third semiconductor chips  300  from being damaged due to external impact, moisture, and the like. The molding layer  400  may include a dielectric polymer, such as an epoxy molding compound (EMC). The following will discuss the example embodiment shown in  FIG.  1   . 
     Referring again to  FIGS.  1  and  3   , a transparent member  500  may be disposed on the image sensor part IS. The transparent member  500  may have a plate shape that covers the image sensor part IS. The transparent member  500  may be disposed on the second semiconductor chip  200 , and may filter a specific range of incident light that is introduced into the second semiconductor chip  200 . For example, the transparent member  500  may include a polymer or glass that is coated by an optical material for filtering or improving optical sensitivity at desired wavelength ranges. The transparent member  500  may be spaced apart from the micro-lenses ML. For example, the transparent member  500  may be spaced apart at about 300 μm to about 500 μm from the second semiconductor chip  200 . The transparent member  500  may have a width substantially the same as that of the first semiconductor chip  100  or that of the second semiconductor chip  200 . 
     A spacer  600  may be provided between the image sensor part IS and the transparent member  500 . The spacer  600  may be disposed between the second semiconductor chip  200  and the transparent member  500 . The transparent member  500  may be directly attached through the spacer  600  to the top surface of the second semiconductor chip  200 . The transparent member  500  may have a top surface at a higher level than that of top surfaces of the micro-lenses ML. An interval between the transparent member  500  and the second semiconductor chip  200  may correspond to a height h of the spacer  600 . For example, the height h of the spacer  600  may range from about 300 μm to about 500 μm. The spacer  600  may be placed on an outer edge (e.g., the adhesive region of the second semiconductor layer  210 ) of the second semiconductor chip  200 . In some example embodiments, the spacer  600  may have an annular shape when viewed in plan. For example, the spacer  600  may have a tetragonal ring shape. The spacer  600  may define an inner space between the transparent member  500  and the second semiconductor chip  200 . The spacer  600  may expose the active array region AAR on the second semiconductor chip  200 . For example, the spacer  600  may be spaced apart from the active array region AAR, and when viewed in plan, may surround the active array region AAR. The spacer  600  may have a sidewall with a width w that ranges from about 50 μm to about 200 μm. 
     The spacer  600  may have an outer surface  600   a  aligned with a lateral surface  500   a  of the transparent member  500 . For example, the spacer  600  may have an overall width d that is the same as the width of the transparent member  500 , and the outer surface  600   a  of the spacer  600  may be coplanar with the lateral surface  500   a  of the transparent member  500 . The overall width d of the spacer  600  may indicate a distance from the outer surface  600   a  to an opposite outer surface of the spacer  600 . 
     In other example embodiments, the outer surface  600   a  of the spacer  600  may be spaced apart from the lateral surface  500   a  of the transparent member  500 . For example, as shown in  FIG.  4   , the spacer  600  may have an overall width greater than the width of the transparent member  500 , and the spacer  600  may protrude from the lateral surface  500   a  of the transparent member  500 . Therefore, the spacer  600  may have a top surface  600   c  that includes a portion that is exposed and another portion that is in contact with the transparent member  500 . In this case, a step difference may be provided between the outer surface  600   a  of the spacer  600  and the lateral surface  500   a  of the transparent member  500 . 
     Referring back to  FIGS.  1  and  3   , the outer surface  600   a  of the spacer  600  may be spaced apart from a lateral surface  200   a  of the second semiconductor chip  200 . For example, the overall width d of the spacer  600  may be greater than the width of the second semiconductor chip  200 , and the spacer  600  may protrude from the lateral surface  200   a  of the second semiconductor chip  200 . Therefore, the spacer  600  may have a bottom surface  600   b  that includes a portion that is exposed and another portion that is in contact with the second semiconductor chip  200 . In this case, a step difference may be provided between the outer surface  600   a  of the spacer  600  and the lateral surface  200   a  of the second semiconductor chip  200 . 
     The spacer  600  may include a supporter  610 , a first adhesive pattern  620 , and a second adhesive pattern  630 . 
     The supporter  610  may be disposed between the second semiconductor chip  200  and the transparent member  500 . The supporter  610  may separate the transparent member  500  from the second semiconductor chip  200 , and may support the transparent member  500  on the second semiconductor chip  200 . The supporter  610  may have an annular shape when viewed in plan. The supporter  610  may have a modulus the same as or greater than that of the second semiconductor chip  200 . In this description, the language “modulus” may indicate Yong&#39;s modulus. The modulus of the supporter  610  may range from about 10 GPa to about 200 GPa. The supporter  610  may have a thermal expansion coefficient less than that of the second semiconductor chip  200 . The thermal expansion coefficient of the supporter  610  may range from about 1 ppm/K to about 10 ppm/K. For example, the supporter  610  may include silicon (Si), glass, or metal. Therefore, the transparent member  500  may be rigidly supported on the second semiconductor chip  200 . In addition, because the supporter  610  has a low thermal expansion coefficient, the supporter  610  may be less deformed due to heat generated from fabrication processes or produced during the operation of a semiconductor package. As a result, a semiconductor package may increase in thermal stability. 
     The first and second adhesive patterns  620  and  630  may be respectively disposed on top and bottom surfaces of the supporter  610 . On the bottom surface of the supporter  610 , the first adhesive pattern  620  may attach the supporter  610  to the second semiconductor chip  200 . On the top surface of the supporter  610 , the second adhesive pattern  630  may attach the supporter  610  to the transparent member  500 . The first and second adhesive patterns  620  and  630  may include a film-shaped adhesive member. For example, the first and second adhesive patterns  620  and  630  may include a die attach film (DAF), a non-conductive film (NCF), an anisotropic film (ACF), or an ultraviolet (UV) film. Therefore, without overflow of the first adhesive pattern  620  or the second adhesive pattern  630 , the supporter  610  may be attached to the second semiconductor chip  200  and the transparent member  500 . 
       FIG.  5    illustrates a cross-sectional view showing a semiconductor package according to some example embodiments.  FIG.  6    illustrates a plan view showing a semiconductor package according to some example embodiments, and  FIG.  5    corresponds to a cross-section taken along line II-IF of  FIG.  6   . For brevity of description, components the same as those of the example embodiments discussed with reference to  FIGS.  1  to  4    are allocated the same reference numerals thereto, and a repetitive explanation thereof will be omitted or abridged below. 
     Referring to  FIGS.  5  and  6   , the spacer  600  may include a supporter  610 , a first adhesive pattern  620 , a second adhesive pattern  630 , and an additional adhesive layer  640 . 
     The supporter  610  may be disposed between the second semiconductor chip  200  and the transparent member  500 . The supporter  610  may separate the transparent member  500  from the second semiconductor chip  200 , and may support the transparent member  500  on the second semiconductor chip  200 . The supporter  610  may have an annular shape when viewed in plan. The supporter  610  may have a small width. For example, the supporter  610  may have a sidewall that has a width that ranges from about 20 μm to about 100 μm. The small width of the supporter  610  may cause incident light from the transparent member  500  to have small amounts of reflection, flare, scattering, and absorption at the supporter  610 . As a result, a semiconductor package may increase in optical sensitivity. The outer surface  610   a  of the supporter  610  may be aligned with the lateral surface  200   a  of the second semiconductor chip  200 . For example, the supporter  610  may have an overall width the same as the width of the second semiconductor chip  200 , and the outer surface  610   a  of the supporter  610  may be coplanar with the lateral surface  200   a  of the second semiconductor chip  200 . The supporter  610  may have a stiffness the same as or greater than that of the second semiconductor chip  200 . 
     The first and second adhesive patterns  620  and  630  may be respectively disposed on top and bottom surfaces of the supporter  610 . On the bottom surface of the supporter  610 , the first adhesive pattern  620  may attach the supporter  610  to the second semiconductor chip  200 . On the top surface of the supporter  610 , the second adhesive pattern  630  may attach the supporter  610  to the transparent member  500 . The first and second adhesive patterns  620  and  630  may include a film-shaped adhesive member. 
     The additional adhesive layer  640  may be disposed on the outer surface  610   a  of the supporter  610 . When viewed in plan, the additional adhesive layer  640  may surround the supporter  610 . The additional adhesive layer  640  may upwardly extend from the outer surface  610   a  of the supporter  610 , and may contact the bottom surface  500   b  of the transparent member  500 . The additional adhesive layer  640  may extend from the outer surface  610   a  of the supporter  610 , and may extend onto the lateral surface  200   a  of the second semiconductor chip  200 . The additional adhesive layer  640  may have an outer surface  640   a  aligned with a lateral surface  500   a  of the transparent member  500 . The outer surface  610   a  of the supporter  610  may correspond to the outer surface  640   a  of the additional adhesive layer  640 . The additional adhesive layer  640  may have a bottom surface  640   b  at a level that is lower than that of the top surface of the second semiconductor chip  200  and is higher than that of the bottom surface of the second semiconductor chip  200 . The additional adhesive layer  640  may be in contact with the bottom surface  500   b  of the transparent member  500 , the outer surface  610   a  of the supporter  610 , and the lateral surface  200   a  of the second semiconductor chip  200 . Therefore, the additional adhesive layer  640  may stably attach the supporter  610  to the transparent member  500  and the second semiconductor chip  200 . The additional adhesive layer  640  may include an adhesive member. For example, the additional adhesive layer  640  may include an adhesive polymer, a non-conductive paste (NCP), an instant adhesive, a thermosetting adhesive, a laser-curable adhesive, or an ultrasonic-curable adhesive. The additional adhesive layer  640  may include various adhesive members other than those mentioned above. 
     Because not only the first and second adhesive patterns  620  and  630  but also the additional adhesive layer  640  is used to attach the spacer  600  to the transparent member  500  and the second semiconductor chip  200 , a semiconductor package may increase in structural stability. In addition, because the spacer  600  is attached not only to the top surface of the second semiconductor chip  200  but also to the lateral surface  200   a  of the second semiconductor chip  200 , the spacer  600  may be more rigidly attached to the second semiconductor chip  200 . 
       FIG.  7    illustrates a cross-sectional view showing a semiconductor package according to some example embodiments.  FIGS.  8  and  9    illustrate plan views showing a semiconductor package according to some example embodiments, and  FIG.  7    corresponds to a cross-section taken along line of  FIG.  8  or  9   . 
     Referring to  FIGS.  7  and  8   , the spacer  600  may include a supporter  610  and an additional adhesive layer  640 . 
     The supporter  610  may be disposed between the second semiconductor chip  200  and the transparent member  500 . The supporter  610  may separate the transparent member  500  from the second semiconductor chip  200 , and simultaneously may attach the transparent member  500  to the second semiconductor chip  200 . The supporter  610  may separate the transparent member  500  from the second semiconductor chip  200 , and may support the transparent member  500  on the second semiconductor chip  200 . The supporter  610  may have an annular shape when viewed in plan. The supporter  610  may have a small width. For example, the supporter  610  may have a sidewall that has a width from about 20 μm to about 100 μm. The small width of the supporter  610  may cause incident light from the transparent member  500  to have small amounts of reflection, flare, scattering, and absorption at the supporter  610 . As a result, a semiconductor package may increase in optical sensitivity. The outer surface  610   a  of the supporter  610  may be aligned with the lateral surface  200   a  of the second semiconductor chip  200 . For example, the supporter  610  may have an overall width the same as the width of the second semiconductor chip  200 , and the outer surface  610   a  of the supporter  610  may be coplanar with the lateral surface  200   a  of the second semiconductor chip  200 . The supporter  610  may include a non-conductive adhesive material. For example, the supporter  610  may include a dry film resist (DFR) or a photo-imageable dielectric (PID). 
     The additional adhesive layer  640  may be disposed on the outer surface  610   a  of the supporter  610 . When viewed in plan, the additional adhesive layer  640  may surround the supporter  610 . Alternatively, the additional adhesive layer  640  may partially cover the outer surface  610   a  of the supporter  610 . As shown in  FIG.  9   , the additional adhesive layer  640  may cover a portion of the outer surface  610   a  of the supporter  610 , and may expose another portion of the outer surface  610   a  of the supporter  610 .  FIG.  9    shows that the additional adhesive layer  640  covers only oppositely facing sides of the outer surface  610   a  of the supporter  610 , but example embodiments are not limited thereto. The following will again the example embodiment of  FIGS.  7  and  8   . 
     The additional adhesive layer  640  may upwardly extend from the outer surface  610   a  of the supporter  610 , and may contact the bottom surface  500   b  of the transparent member  500 . The additional adhesive layer  640  may extend from the outer surface  610   a  of the supporter  610 , and may extend onto the lateral surface  200   a  of the second semiconductor chip  200 . The additional adhesive layer  640  may have a bottom surface  640   b  at a level that is lower than that of the top surface of the second semiconductor chip  200  and is higher than that of the bottom surface of the second semiconductor chip  200 . The additional adhesive layer  640  may be in contact with the bottom surface  500   b  of the transparent member  500 , the outer surface  610   a  of the supporter  610 , and the lateral surface  200   a  of the second semiconductor chip  200 . Therefore, the additional adhesive layer  640  may stably attach the supporter  610  to the transparent member  500  and the second semiconductor chip  200 . The additional adhesive layer  640  may include an adhesive member. For example, the additional adhesive layer  640  may include an adhesive polymer, a non-conductive paste (NCP), an instant adhesive, a thermosetting adhesive, a laser-curable adhesive, or an ultrasonic-curable adhesive. The additional adhesive layer  640  may include various adhesive members other than those mentioned above. 
     Because not only the supporter  610  but also the additional adhesive layer  640  is used to attach the spacer  600  to the transparent member  500  and the second semiconductor chip  200 , a semiconductor package may increase in structural stability. In addition, because the spacer  600  is attached not only to the top surface of the second semiconductor chip  200  but also to the lateral surface  200   a  of the second semiconductor chip  200 , the spacer  600  may be more rigidly attached to the second semiconductor chip  200 . 
       FIGS.  10  to  15    illustrate diagrams showing a method of fabricating a semiconductor package according to some example embodiments.  FIGS.  10 ,  11 , and  13  to  15    are cross-sectional views,  FIG.  12    is a plan view of  FIG.  11   , and  FIG.  11    corresponds to a cross-section taken along line IV-IV′ of  FIG.  12   . 
     Referring to  FIG.  10   , a first substrate  1610  may be provided. The first substrate  1610  may include a material with a high stiffness. For example, the first substrate  1610  may have a modulus ranging from about 10 GPa to about 200 GPa. The first substrate  1610  may include a material with a low thermal expansion coefficient. For example, the thermal expansion coefficient of the first substrate  1610  may range from about 1 ppm/K to about 10 ppm/K. The first substrate  1610  may include silicon (Si), glass, or metal. 
     A first adhesive layer  1620  may be formed below the first substrate  1610 . A second adhesive layer  1630  may be formed on the first substrate  1610 . For example, an adhesive film may be attached to each of top and bottom surfaces of the first substrate  1610 . The adhesive film may include a film-shaped adhesive member. For example, the adhesive film may include a die attach film (DAF), a non-conductive film (NCF), an anisotropic film (ACF), or an ultraviolet (UV) film. 
     Referring to  FIGS.  11  and  12   , a first etching process may be performed on the first substrate  1610 . For example, a laser drilling process may be employed as the first etching process that etches the first substrate  1610 . The first substrate  1610  may be etched to form one or more cavities CA. The cavities CA may be spaced apart from each other.  FIG.  12    shows the first substrate  1610  in which are formed two cavities CA that are spaced apart from each other in one direction, but example embodiments are not limited thereto. When viewed in plan, the first substrate  1610  may have therein the cavities CA that are arranged in one direction or in two intersecting directions. For example, the first substrate  1610  may be etched to have a grid shape when viewed in plan. 
     The first and second adhesive layers  1620  and  1630  may also be etched when the first substrate  1610  is etched in the first etching process. At this stage, the etched first and second adhesive layers  1620  and  1630  may have a planar shape that is the same as that of the etched first substrate  1610 . The cavities CA may be formed to penetrate the first adhesive layer  1620 , the first substrate  1610 , and the second adhesive layer  1630 . 
     Referring to  FIG.  13   , image sensor parts IS may be provided. The image sensor parts IS may be the same as or similar to the image sensor part IS discussed with reference to  FIG.  1   . For example, the image sensor parts IS may each include a first semiconductor chip  100  as a logic chip and a second semiconductor chip  200  as a sensing chip. Pixel elements P may be arranged on the top surface of the second semiconductor chip  200 . 
     The first semiconductor chip  100  may include a first semiconductor layer  110 , a first circuit layer  120  provided on the first semiconductor layer  110 , a first via  130  that penetrates the first semiconductor layer  110  and has electrical connection with the first circuit layer  120 , and a first bonding pad  140  disposed on a top surface of the first semiconductor chip  100 . A logic transistor may be provided in the first semiconductor layer  110 . A redistribution layer  150  may be provided below the first semiconductor chip  100 . The redistribution layer  150  may include dielectric layers  152  and a redistribution pattern  154 . 
     The second semiconductor chip  200  may include a second semiconductor layer  210 , a second circuit layer  220  that is disposed on one surface of the second semiconductor chip  200  and is adjacent to the first semiconductor chip  100 , a second via  230  that penetrates the second semiconductor layer  210  and has electrical connection with the second circuit layer  220 , a second bonding pad  240  disposed on the one surface of the second semiconductor chip  200 , and color filters CF and micro-lenses ML disposed on the second semiconductor layer  210 . Photoelectric conversion elements PD may be provided in the second semiconductor layer  210 . The second circuit layer  220  may include wiring patterns and transistors for driving the photoelectric conversion elements PD. The second bonding pad  240  may be in contact with the first bonding pad  140 .) 
     The image sensor parts IS may be attached to the first substrate  1610 . The image sensor parts IS may be adhered to the first substrate  1610  so as to cause the second semiconductor chip  200  to face the first substrate  1610 . For example, the first adhesive layer  1620  may be used to attach the image sensor parts IS to the first substrate  1610 . The first adhesive layer  1620  may be in contact with an outer edge of the image sensor IS, or with the adhesive region of the second semiconductor layer  210  discussed with reference to  FIGS.  1  and  3   . At this stage, when viewed in plan, each of the image sensor parts IS may be attached to cause its active array region AAR to rest inside the cavity CA. The first substrate  1610  may have inner surfaces that are toward the cavities CA and are spaced apart from the active array regions AAR of the image sensor parts IC. The image sensor parts IS may be spaced apart from each other while being attached to the first substrate  1610 . For example, when the first substrate  1610  experiences the etching process discussed with reference to  FIG.  11   , an arrangement period in which the cavities CA are formed, or a pitch of the cavities CA, may be greater than a width of the image sensor parts IS. 
     Referring to  FIG.  14   , a transparent substrate  1500  may be attached to the first substrate  1610 . The first substrate  1610  may be attached with the image sensor parts IS on one side, and may also be attached with the transparent substrate  1500  on another side opposite to the one side. For example, the second adhesive layer  1630  may be used to attach the transparent substrate  1500  to the first substrate  1610 . The transparent substrate  1500  may be fixedly spaced apart from the image sensor parts IS across the first substrate  1610 . The transparent substrate  1500  may include a polymer or glass that is coated by an optical material for filtering or improving the sensitivity of light at desired wavelength ranges. 
     Afterwards, the first substrate  1610  and the transparent substrate  1500  may be cut into spacers (see the spacer  600  of  FIG.  1   ) and transparent members (see the transparent member  500  of  FIG.  1   ). For example, the transparent substrate  1500  and the first substrate  1610  may undergo a singulation process performed along a sawing line SL. Thus, the first substrate  1610  and the transparent substrate  1500  may be diced into semiconductor packages that are divided from each other. The image sensor parts IS may be spaced apart from each other, and the sawing line SL may be positioned between and spaced apart from the image sensor parts IS. 
     Referring back to  FIG.  1   , external terminals  156  may be provided on a bottom surface of a redistribution layer  150  of each image sensor part IS. As a result, a semiconductor package may be fabricated as shown in  FIG.  1   . 
     In some example embodiments, the first and second adhesive layers  1620  and  1630  may include a film-shaped adhesive member. Therefore, when the first substrate  1610  is attached with the image sensor parts IS and the transparent substrate  1500 , the first and second adhesive layers  1620  and  1630  may be free of overflow. In conclusion, there is less possibility of occurrence of defects in fabricating a semiconductor package. 
       FIG.  14    shows that the transparent substrate  1500  is attached to the first substrate  1610 , but example embodiments are not limited thereto. Alternatively, the transparent members  500  may be attached to the first substrate  1610 . The transparent members  500  may be spaced apart while being attached to the first substrate  1610 . For example, when the first substrate  1610  experiences the etching process discussed with reference to  FIG.  11   , an arrangement period in which the cavities CA are formed may be greater than a width of the transparent members  500 . 
     Thereafter, the first substrate  1610  may be cut into spacers (see the spacer  600  of  FIG.  1   ). For example, the first substrate  1610  may undergo a singulation process performed along a sawing line SL. Thus, the first substrate  1610  may be diced into semiconductor packages that are divided from each other. The transparent members  500  may be spaced apart from each other, and the sawing line SL may be positioned between and spaced apart from the transparent members  500 . As such, a semiconductor package may be fabricated as shown in  FIG.  4   . 
       FIGS.  16  to  20    illustrate diagrams showing a method of fabricating a semiconductor package according to some example embodiments.  FIGS.  16 ,  17 , and  19    are cross-sectional views,  FIG.  18    is a plan view of  FIG.  17   , and  FIG.  17    corresponds to a cross-section taken along line V-V′ of  FIG.  18   . 
     Referring to  FIG.  16   , a second substrate  1610 ′ may be provided. The second substrate  1610 ′ may include a non-conductive adhesive material. For example, the second substrate  1610 ′ may include a dry film resist (DFR) or a photo-imageable dielectric (PID). 
     The second substrate  1610 ′ may be attached to a transparent substrate  1500 . The transparent substrate  1500  may include a polymer or glass that is coated by an optical material for filtering or improving the sensitivity of light at desired wavelength ranges. 
     Referring to  FIGS.  17  and  18   , the second substrate  1610 ′ may experience a second etching process. For example, a laser drilling process may be employed as the second etching process that etches the second substrate  1610 ′. The second substrate  1610 ′ may be etched to form a plurality of supporters  610 . For example, the second substrate  1610 ′ may be etched to form one or more cavities CA. The cavities CA may be spaced apart from each other.  FIG.  18    shows the second substrate  1610 ′ in which are formed two cavities CA that are spaced apart from each other in one direction, but example embodiments are not limited thereto. When viewed in plan, the second substrate  1610 ′ may have therein the cavities CA that are arranged in one direction or in two intersecting directions. 
     In performing the second etching process on the second substrate  1610 ′, the second substrate  1610 ′ may be etched to also form a trench T. The trench T may be formed between the cavities CA. When viewed in plan, the trench T may be formed to have a grid shape and also to surround each of the cavities CA. Therefore, the second substrate  1610 ′ may be etched to separate the supporters  610  from each other. For example, the trench T may separate the supporters  610  from each other, and the cavities CA formed inside the supporters  610  may cause the supporters  610  to each have a tetragonal ring shape. 
     Referring to  FIG.  19   , image sensor parts IS may be provided. The image sensor parts IS may be the same as or similar to the image sensor part IS discussed with reference to  FIG.  1   . For example, the image sensor parts IS may each include a first semiconductor chip  100  as a logic chip and a second semiconductor chip  200  as a sensing chip. 
     The image sensor parts IS may be attached to the supporters  610 . The image sensor parts IS may be adhered to the supporters  610  so as to cause the second semiconductor chip  200  to face the supporters  610 . The images sensor parts IS may be positioned above the cavities CA, and the supporter  610  may be in contact with an outer edge of the image sensor part IS, or with the adhesive region of the second semiconductor layer  210  discussed with reference to  FIGS.  1  and  3   . At this stage, when viewed in plan, each of the image sensor parts IS may be attached to cause its active array region AAR to rest inside the cavity CA. The first substrate  1610  may have inner surfaces that are toward the cavities CA and are spaced apart from the active array regions AAR of the image sensor parts IC. The image sensor parts IS may be spaced apart from each other while being attached to the supporters  610 . For example, the image sensors IS may be provided on the cavities CA, but not on the trench T. The supporters  610  may have outer surfaces  610   a  that are aligned with a lateral surface  200   a  of the second semiconductor chip  200 . 
     Referring to  FIG.  20   , an adhesive member  1640  may be formed on the transparent substrate  1500 . For example, the adhesive member  1640  may be formed by filling an adhesive material into the trench T that is a space between the supporters  610 . The adhesive material may include an adhesive polymer, a non-conductive paste (NCP), an instant adhesive, a thermosetting adhesive, a laser-curable adhesive, or an ultrasonic-curable adhesive. The filling of the adhesive material may continue until a top surface  1640   a  of the adhesive member  1640  reaches the lateral surface  200   a  of the second semiconductor chip  200 . For example, the top surface  1640   a  of the adhesive member  1640  may be located between top and bottom surfaces of the second semiconductor chip  200 . After the trench T is filled with the adhesive material, a curing process may be performed on the adhesive material, if necessary. 
     Afterwards, the adhesive member  1640  and the transparent substrate  1500  may be cut into spacers (see the spacer  600  of  FIG.  7   ) and transparent members (see the transparent member  500  of  FIG.  7   ). For example, the transparent substrate  1500  and the adhesive member  1640  may undergo a singulation process performed along a sawing line SL. Thus, the adhesive member  1640  and the transparent substrate  1500  may be diced into semiconductor packages that are divided from each other. 
     Referring back to  FIG.  7   , external terminals  156  may be provided on a bottom surface of a redistribution layer  150  of each image sensor part IS. As such, a semiconductor package may be fabricated as shown in  FIG.  7   . 
     According to some example embodiments, a semiconductor package may be configured such that a transparent member is rigidly supported on a semiconductor chip. In addition, because a supporter has a low thermal expansion coefficient, the supporter may be less deformed due to heat generated from fabrication processes or produced during the operation of the semiconductor package. As a result, the semiconductor package may increase in thermal stability. 
     In addition, because not only adhesive patterns but also an additional adhesive layer is used to attach a spacer to the transparent member and the semiconductor chip, the semiconductor package may have increased structural stability. Moreover, the spacer may be attached not only to a top surface of the semiconductor chip but also to a lateral surface of the semiconductor chip, and thus the spacer may be more rigidly attached to the semiconductor chip. 
     Furthermore, a small width of the supporter may cause incident light from the transparent member to have small amounts of reflection, flare, scattering, and absorption at the supporter. As a result, the semiconductor package may have increased optical sensitivity. 
     Although example embodiments have been described with reference to the accompanying drawings, it will be understood by one of ordinary skill in the art that variations in form and detail may be made therein without departing from the spirit and essential feature of the present disclosure. The above disclosed example embodiments should thus be considered illustrative and not restrictive.