Patent Publication Number: US-7595627-B1

Title: Voltage reference circuit with complementary PTAT voltage generators and method

Description:
TECHNICAL FIELD 
   This disclosure is generally directed to voltage reference circuits and, more specifically, to a voltage reference circuit with complementary PTAT voltage generators. 
   BACKGROUND 
   The rapid proliferation of local area network (LANs) in the corporate environment and the increased demand for time-sensitive delivery of messages and data between users has spurred development of high-speed (gigabit) Ethernet LANs. The 100BASE-TX Ethernet LANs using category-5 (CAT-5) copper wire and the 1000BASE-T Ethernet LANs capable of one gigabit per second (1 Gbps) data rates over CAT-5 data grade wire use new techniques for the transfer of high-speed data symbols. 
   Conventional 1000BASE-T Ethernet LAN drivers, in addition to nearly all other signal processing/communication chips and systems, use voltage reference circuits. These voltage reference circuits are able to generate relatively constant reference voltages that have a well-defined magnitude, as well as minimal process variation, temperature variation, and voltage variation. 
   However, conventional CMOS-based band-gap voltage reference circuits are highly prone to variations as a result of noise, power supply rejection problems, and other accuracy issues. In addition, voltage reference circuits preferably should be capable of operating at relatively low voltages with minimal current consumption, which provides yet another design challenge. 
   Before undertaking the DETAILED DESCRIPTION OF THE INVENTION below, it may be advantageous to set forth definitions of certain words and phrases used throughout this patent document: the terms “include” and “comprise,” as well as derivatives thereof, mean inclusion without limitation; the term “or,” is inclusive, meaning and/or; the term “each” means every one of at least a subset of the identified items; the phrases “associated with” and “associated therewith,” as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, be bound to or with, have, have a property of, or the like; and the term “controller” means any device, system or part thereof that controls at least one operation, such a device may be implemented in hardware, firmware or software, or some combination of at least two of the same. It should be noted that the functionality associated with any particular controller may be centralized or distributed, whether locally or remotely. Definitions for certain words and phrases are provided throughout this patent document, those of ordinary skill in the art should understand that in many, if not most instances, such definitions apply to prior as well as future uses of such defined words and phrases. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     For a more complete understanding of this disclosure and its features, reference is now made to the following description, taken in conjunction with the accompanying drawings, in which: 
       FIG. 1  is a block diagram illustrating a transceiver including a voltage reference circuit with complementary PTAT voltage generators in accordance with one embodiment of the present disclosure; 
       FIG. 2  illustrates the voltage reference circuit of  FIG. 1  in accordance with one embodiment of the present disclosure; 
       FIG. 3  illustrates details of the voltage reference circuit of  FIG. 2  in accordance with one embodiment of the present disclosure; 
       FIG. 4  illustrates the voltage reference circuit of  FIG. 3  in greater detail in accordance with one particular embodiment of the present disclosure; 
       FIG. 5  illustrates a portion of the voltage reference circuit of  FIG. 4  with post-production trimming provided in accordance with an alternate embodiment of the present disclosure; and 
       FIG. 6  illustrates a portion of the voltage reference circuit of  FIG. 4  with the potential stabilizer provided in accordance with an alternate embodiment of the present disclosure. 
   

   DETAILED DESCRIPTION 
     FIGS. 1 through 6 , discussed below, and the various embodiments used to describe the principles of the present disclosure in this patent document are by way of illustration only and should not be construed in any way to limit the scope of the disclosure. Those skilled in the art will understand that the principles of the present disclosure may be implemented in any suitably arranged reference circuit. 
     FIG. 1  is a block diagram illustrating a transceiver  100  in accordance with one embodiment of the present disclosure. According to one embodiment, the transceiver  100  comprises a gigabit Ethernet transceiver. However, it will be understood that the transceiver  100  may comprise any suitable transceiver operable to receive and transmit data. 
   The transceiver  100  comprises a voltage reference circuit  102  that is operable to generate a reference voltage  104  for the transceiver  100 . As described in more detail below, the voltage reference circuit  102  is operable to generate the reference voltage  104  using two complementary proportional-to-absolute-temperature (PTAT) voltage generators, which improves accuracy and reduces noise as compared to a reference voltage generated using a single PTAT voltage generator. However, one of the two PTAT voltages is generated by an existing differential error amplifier. Because of this, an additional device is not needed to generate the complementary PTAT voltage and current consumption is not increased as compared to a voltage reference circuit that generates a reference voltage using a single PTAT voltage generator. 
   According to one embodiment, the voltage reference circuit  102  of the transceiver  100  combines a pair of PNP transistors with a pair of NPN transistors in order to form a low-voltage double-ΔV BE  topology for high precision and low noise. The NPN transistors also operate as an input differential stage to a low-voltage folded-cascode error amplifier, which reduces the circuit complexity and current consumption, as previously described. In addition, a high power supply rejection ratio (PSRR) may be obtained by means of a fully-cascoded ground-referred architecture and by deriving critical digital control signals from the reference voltage  104 . 
   The transceiver  100  also comprises an analog-to-digital converter (ADC)  106 , a voltage-to-current (V-I) converter  108 , and a digital-to-analog converter (DAC)  110 , in addition to any other suitable circuitry. The ADC  106 , which is coupled to the voltage reference circuit  102 , is operable to receive an analog input signal (I A )  120  and the reference voltage  104  and to generate a digital input signal (I D )  122  based on the analog input signal  120  and the reference voltage  104 . 
   The V-I converter  108 , which is also coupled to the voltage reference circuit  102 , is operable to receive the reference voltage  104  and to convert the reference voltage  104  into a specified current based on the reference voltage  104 . The DAC  110  is coupled to the V-I converter  108  and is operable to transmit an analog output signal (O A )  124  based on the specified current from the V-I converter  108 . 
   In operation, for one embodiment, the voltage reference circuit  102  generates the reference voltage  104  and provides the reference voltage  104  to both the ADC  106  and the V-I converter  108 . The ADC  106  may also receive an analog input signal  120  and may convert that signal  120  into a digital input signal  122  based on the reference voltage  104 . The V-I converter  108  converts the reference voltage  104  into a specified current and provides the specified current to the DAC  110 . The DAC  110  may generate an analog output signal  124  based on the specified current and transmit the analog output signal  124  from the transceiver  100  to any other suitable component. 
     FIG. 2  illustrates a voltage reference circuit  200  in accordance with one embodiment of the present disclosure. It will be understood that, in addition to being included in the transceiver  100  as the voltage reference circuit  102 , the voltage reference circuit  200  may be included in any other suitable component with a use for a relatively constant reference voltage without departing from the scope of the present disclosure. 
   The voltage reference circuit  200  comprises an amplifier  202 , an input transistor  204 , a resistive network  206 , and a voltage source  212 . The amplifier  202 , which may comprise an operational transconductance amplifier or other suitable type of amplifier, is operable to generate a reference voltage  216  based on complementary PTAT voltages. The voltage source  212  is operable to provide a first PTAT voltage, P PTAT , while the second PTAT voltage, N PTAT , is generated within the amplifier  202 . The reference voltage  216  is generated at the base of the input transistor  204  based on the combination of the two PTAT voltages. Thus, a PTAT voltage  214 , which is the voltage across the resistor  206   a , may be defined as follows:
 
 V   PTAT   =P   PTAT   +N   PTAT .
 
   In operation, for one embodiment, the voltage source  212 , which comprises a first PTAT voltage generator made up of a pair of PNP transistors, generates a first PTAT voltage. The voltage source  212  then provides that first PTAT voltage to the amplifier  202 , which comprises a second PTAT voltage generator made up of a pair of NPN transistors. The second PTAT voltage generator generates a second PTAT voltage. The amplifier  202  then generates the reference voltage  216  based on the first PTAT voltage and the second PTAT voltage. 
     FIG. 3  illustrates details of the voltage reference circuit  200  in accordance with one embodiment of the present disclosure. For this embodiment, the voltage reference circuit  200  comprises a resistive divider  302 , a potential stabilizer  304 , a plurality of current sources  308 ,  310 ,  312  and  314 , a transistor  316  and a start-up circuit  318 , in addition to the amplifier  202 , input transistor  204 , resistive network  206  and voltage source  212 . 
   The resistive divider  302  is coupled to the input transistor  204  and is operable to generate an adjustable voltage  320  based on the reference voltage  216 . For example, for a particular embodiment, the reference voltage  216  may be about 1.2 V and the resistive divider  302  may comprise about 2.4 MΩ. For this embodiment, the resistive divider  302  may have about twenty taps around the 500 mV level in order to provide an adjustable, temperature-compensated 500 mV output for the adjustable voltage  320 . For example, twenty 3-kΩ resistors may be coupled in series with taps between them. Using a bias current of 500 nA, the adjustable voltage  320  may be adjusted in 1.5-mV increments. 
   The potential stabilizer  304  is coupled to the input transistor  204 . The potential stabilizer  304  is operable to stabilize the potential at the collector of the input transistor  204 . For example, the potential stabilizer  304  may comprise a parallel cascode device and a current source, a voltage regulator, or any other suitable device capable of stabilizing the potential at the collector of the input transistor  204 . 
   The voltage source  212  comprises a level shifter made up of two PNP transistors  330  and  332 . The amplifier  202  comprises a differential amplifier  202   a  made up of two NPN transistors  334  and  336 , a folded-cascode stage  202   b  made up of two PMOS transistors  340  and  342  and two NMOS transistors  344  and  346 , and a diode-load gain stage  202   c  made up of two PMOS transistors  350  and  352  and two NMOS transistors  354  and  356 . 
   The level-shifting voltage source  212  is operable to generate a first PTAT voltage (P PTAT ), and the differential amplifier  202   a  is operable to generate a second PTAT voltage (N PTAT ). Thus, the level-shifting voltage source  212  comprises a PTAT voltage generator, while the differential amplifier  202   a  comprises a complementary PTAT voltage generator with respect to the voltage source  212 . 
   The PTAT voltage  214 , which appears across the resistor  206   a , is determined by the sum of the two PTAT voltages (P PTAT  and N PTAT ), which are actually two ΔV BE  terms. The first term is the ΔV BE  of the PNP transistors  330  and  332 , while the second term is the ΔV BE  of the NPN transistors  334  and  336 . For one embodiment, transistor  332  is operated at 16 times the current density of transistor  330 , and transistor  334  is operated at eight times the current density of transistor  336 . For this embodiment, the PTAT voltage  214  (V PTAT ) may be calculated as follows: 
               V     R   ⁢           ⁢   206   ⁢   a       =       V   PTAT     =         V     BE   ⁢           ⁢   330       +     V     BE   ⁢           ⁢   334       +     V     EB   ⁢           ⁢   336       +     V     EB   ⁢           ⁢   332         =         V     BE   ⁢           ⁢   330       -     V     BE   ⁢           ⁢   332       +     V     BE   ⁢           ⁢   334       -     V     BE   ⁢           ⁢   3336         =           V   TH     ·     ln   ⁡     (   16   )         +       V   TH     ·     ln   ⁡     (   8   )           =       V   TH     ·     ln   ⁡     (   128   )                   ,         
where V TH  is the thermal voltage (i.e., kT/q). Therefore, at room temperature, the PTAT voltage  214  for this embodiment is approximately 126 mV.
 
   For one embodiment, the resistive network  206  may comprise three polysilicon resistors  206   a ,  206   b  and  206   c , each of which may comprise a number of unity devices. For example, the unity devices may comprise 18-kΩ resistors. The resistor  206   a  and the PTAT voltage  214  define the bias current in the resistive network  206 . Thus, with 126 mV at 126 kΩ, the current through the resistors  206   a - c  and the input transistor  204  would be 1 μA under nominal conditions. 
   The resistors  206   b  and  206   c  may be of essentially equal size in order to cancel the effects of the base currents of transistors  330  and  332 . This results from the following equation provided that the two base currents are equal: 
                 V   REF     =         V     BE   ⁢           ⁢   204       +       (       I     R   ⁢           ⁢   206   ⁢   a       -     I     B   ⁢           ⁢   332         )     ⁢     R     206   ⁢   c         +       I     R   ⁢           ⁢   2   ⁢           ⁢   06   ⁢   a       ⁢     R     206   ⁢   a         +       (       I     R   ⁢           ⁢   206   ⁢   a       +     I   B330       )     ⁢     R     206   ⁢   b   ⁢                       =         V     BE   ⁢           ⁢   204       +       I     R   ⁢           ⁢   206   ⁢   a       ⁡     (       R     206   ⁢   a       +     R     206   ⁢   b       +     R     206   ⁢   c         )       +       I   B330     ⁢     R     206   ⁢   b         -       I   B332     ⁢     R     206   ⁢   c           =       V     BE   ⁢           ⁢   204       +       V   PTAT     ⁡     (     1   +       (       R     206   ⁢   b       +     R     206   ⁢   c         )     /     R     206   ⁢   a           )               )     +       I   B330     ⁢     R     206   ⁢   b         -       I   B332     ⁢     R     206   ⁢   c               
In order to achieve a temperature-compensated reference voltage  214  under nominal operating conditions, resistors  206   b  and  206   c  may each comprise a nominal value of 208 kΩ for a particular embodiment.
 
   For one embodiment, resistor  206   c  may be made programmable to allow post-production trimming of the temperature coefficient. For a particular embodiment, resistor  206   c  may be programmable from 184 kΩ to 231.25 kΩ in steps of 0.75 kΩ, which translates to a PTAT voltage adjustment resolution of 0.75 mV at the nominal current of 1 μA. For this particular embodiment, the programmable section of resistor  206   c  may be binary weighted, i.e., a series connection of six blocks from 0.75 kΩ to 24 kΩ (2 n ×0.75 kΩ, with n=0, 1, 2, 3, 4, 5) connected in series. Each block may be shorted by an NMOS pass transistor (50 μm/0.5 μm). 
   For one embodiment, a bias voltage  348  for the folded-cascode stage  202   b  comprises a PTAT voltage, which partially compensates for the cascode device&#39;s gate-source voltage variation with temperature. The biasing of the voltage reference circuit  200  is self-regulating. The reference current level is defined by the reference voltage  216  and the total resistance between the output node providing the reference voltage  216  and ground. With 1.2 V at 2.4 MΩ, the current would be 500 nA. 
   A common mode feedback  360  is provided from the diode-load gain stage  202   c  to the current sources  308 ,  310 ,  312  and  314  in order to provide a self-biasing feedback loop. This self-biasing feedback loop, along with an output voltage regulation feedback loop provided by the application of the reference voltage  216  to the base of the input transistor  204 , allows optimization of accuracy and the use of a low supply voltage simultaneously. The accuracy may be primarily determined by the precision of the self-biasing current sources  308 ,  310 ,  312  and  314 , while the low supply voltage may be potentially limited by the V D,SAT  of the transistor  316 , which feeds the resistive divider  302 . 
     FIG. 4  illustrates the voltage reference circuit  200  as shown in  FIG. 3  in even greater detail in accordance with one particular embodiment of the present disclosure. For this embodiment, the resistors  206   a ,  206   b  and  206   c  are labeled as R 0 , R 1  and R 2 , respectively. The input transistor  204  is labeled as Q 15 . The reference voltage  216  is labeled as vbgp. The potential stabilizer  304  is provided by the current source M 31  and the parallel cascode device M 97 . The current sources  308 ,  310 ,  312  and  314  are labeled as M 22 , M 23 , M 54  and M 55 , respectively. The transistor  316  is labeled as M 7 . The transistors  330 ,  332 ,  334  and  336  are labeled as Q 1 , Q 0 , Q 13  and Q 12 , respectively. The transistors  340 ,  342 ,  344  and  346  are labeled as M 96 , M 95 , M 12  and M 15 , respectively. The transistors  350 ,  352 ,  354  and  356  are labeled as M 21 , M 67 , M 68  and M 61 , respectively. The start-up circuit  318  is provided by M 104 , M 103 , M 122 , M 123 , M 0 , M 132 , M 125 , M 88 , M 85 , M 113 , M 114 , M 115  and M 116 . For one embodiment, the start-up circuit  318  may use an externally-generated supply-voltage-independent current of a few hundred nano-amps. For example, for a particular embodiment, the current may vary with temperature but remain within a range of about 100 to 300 nA. 
   The circuit  200  illustrated in  FIG. 4  is based on a pair of substrate PNP transistors Q 0  and Q 1  (available in standard CMOS technology) operating at different current densities, a resistive network R 0 , R 1  and R 2 , and a vertical NPN transistor Q 15  (available in triple-well CMOS technology) that are arranged in a bandgap reference circuit configuration. The circuit  200  of  FIG. 4  is further based on a low-voltage folded-cascode differential error amplifier with vertical-NPN input stage. These NPN devices Q 12  and Q 13  also operate at different current densities, thereby forming with the PNP transistor pair Q 0  and Q 1  a double-ΔV BE  architecture. This improves accuracy and noise while retaining low-voltage capability without adding devices or increasing current consumption. In addition, high PSRR is provided by means of a fully-cascoded ground-referred architecture that exploits conventional cascode devices, as well as a PTAT-voltage-controlled parallel cascode device. The PSRR is further improved by deriving the logical high level of certain digital control signals from the reference voltage  216  instead of from the positive power supply. Finally, for the embodiment of  FIG. 4 , the following transistor pairs are mathed: Q 1  and Q 0 , Q 13  and Q 12 , M 22  and M 23 , MS 4  and MS 5 , M 12  and M 15 , and M 68  and M 61  (which are also matched to M 12  and M 15 ). 
   The potential (csin) at the input of the common source stages is derived from the nominal current in the output branch via the current mirror M 7 /M 21  and the common source device M 61 . A copy of the current through M 61 /M 21  is created in the second common source stage M 68 /M 67 . This current is mirrored into all remaining branches biased by PMOS current sources. Through the NMOS current mirror M 81 /M 5 , the current is also used to bias the differential pair. Thus, for this embodiment, all bias currents are derived from the regulated reference current in the output branch. 
   The voltage reference circuit  200  of  FIG. 4  has been optimized for high PSRR. Thus, the circuit  200  has a ground-referred architecture and substantially perfect symmetry. All relevant node voltages in the circuit  200  are referred to ground as a result of the folded-cascode differential stage and the additional cascode devices M 97 , M 98 , M 99  and M 127 . 
   The low-frequency PSRR, which is in fact the line regulation, would depend largely on the Early voltage of Q 15  if the parallel cascode device M 97  (and the current source M 31 ) were not present. Any variation of the positive supply voltage would modulate the collector-emitter voltage of Q 15 , which at a constant collector current would change its base-emitter voltage and, hence, the reference voltage  216 . The parallel cascode device M 97  acts to keep the collector of Q 15  at a fixed potential, essentially eliminating the impact of the Early effect on the PSRR. 
   The current source M 31  decouples the collector of Q 15  from the supply and provides the bias current for M 97 . The gate of M 97  is controlled by a PTAT bias voltage, which partially compensates for the complementary-to-absolute-temperature (CTAT) characteristic of the gate-source voltage of M 97 . Without this compensation, the temperature coefficient at the source node of M 97  would be too large to ensure both the NPN device Q 15  and the current source M 31  would operate in the proper region under all possible operating conditions. 
   For symmetry, the PMOS current sources M 22  and M 23  are matched. Besides matching of the device structures, this also means that the drain-source voltages are to be the same, which is a condition provided by the cascode transistors. This also holds for the current sources M 54  and M 55 . The NMOS current mirror M 12 /M 15 , which acts as a load in the folded-cascode differential stage, has a same drain-source voltage for the two transistors. These voltages are kept equal by proper matching with the common source devices M 68  and M 61 . 
   Also for high PSRR, the signals controlling the temperature-compensated (TC) trimming are decoupled from supply variations. Thus, for this embodiment, the preceding driver stage may be coupled to the reference voltage  216  instead of to the positive supply, V DD . In addition, the high-frequency PSRR may be even further improved by providing RC filtering at the output node providing the reference voltage  216 . 
   For the illustrated embodiment, the dominant high-impedance node in the circuit  200  is the input of the common source stages. The capacitance at this node can be expected to create the dominant pole. However, if a large capacitance were present at the drain of M 61 , additional poles and zeroes would appear at relatively low frequencies, making frequency compensation difficult or impossible. Thus, for this reason the common source stage is duplicated in the circuit  200 . Separating the regulating and biasing common source stages minimizes the capacitance at the drain node of M 61  at the cost of 250 nA additional bias current for the embodiment described above. 
   Sufficient phase and gain margins are achieved by means of a feedforward capacitor coupled between the reference voltage  216  and the base of Q 1  and an RC network coupled between the reference voltage  216  and the input of the common source stages M 61 /M 68 . A small capacitor from the base of Q 12  to ground also helps to improve the margins. 
   As described above, the circuit  200  is operable to provide low-voltage operation. For a particular embodiment, the circuit  200  is specified to operate at supply voltages down to 1.6 V. The folded-cascode differential stage is one element that enables this low-voltage operation. Another feature is the way the PTAT voltage  214  is generated based on both NPN and PNP transistors. Unlike other double-ΔV BE  approaches, this circuit  200  does not use stacked base-emitter diodes and, thus, does not restrict low-voltage operation. 
     FIG. 5  illustrates a portion of the voltage reference circuit  200  of  FIG. 4  with post-production trimming provided in accordance with an alternate embodiment of the present disclosure. For this embodiment, the trimming is performed at the base of the NPN device Q 15  regardless of the voltage level provided by the reference voltage  216 . The resistive divider  302  comprises a plurality of taps at the bandgap voltage level, where analog switches (e.g., pass transistors, transmission gates or other suitable devices) may couple the base of the device Q 15  to any of the taps. 
     FIG. 6  illustrates a portion of the voltage reference circuit  200  of  FIG. 4  with the potential stabilizer  304  provided in accordance with an alternate embodiment of the present disclosure. For this embodiment, the potential stabilizer  304  comprises a linear voltage regulator. 
   Although the present disclosure has been described with an exemplary embodiment, various changes and modifications may be suggested to one skilled in the art. For example, although the embodiments described above refer to PNP transistors and NPN transistors in a particular arrangement, it will be understood that a complementary topology implementing NPN transistors instead of PNP transistors and vice versa, along with any suitable accompanying alterations, may be used without departing from the scope of the present disclosure. It is intended that the present disclosure encompass such changes and modifications as fall within the scope of the appended claims.