Patent Publication Number: US-7710096-B2

Title: Reference circuit

Description:
FIELD OF THE INVENTION 
     The present invention relates to voltage and current reference circuits. The invention is applicable to, but not limited to a reference circuit and arrangement for providing temperature-independent, curvature-compensated sub-bandgap voltage and current references. 
     BACKGROUND OF THE INVENTION 
     Voltage reference circuits are required in a wide variety of electronic circuits to provide a reliable voltage value. In particular, such circuits are often designed to ensure that the reliable voltage value is made substantially independent of any temperature variations within the electronic circuit or temperature variation effects on components within the electronic circuit. Notably, the temperature stability of the voltage reference is therefore a key factor. This is particularly critical in some electronic circuits, for example for future communication products and technologies such as system-on-chip technologies, where accuracy of all data acquisition functions is required. 
     In the field of the present invention, a bandgap voltage reference is known to produce an output voltage very close to a semiconductor bandgap voltage. For Silicon, this value is about 1.2V. Thus, a sub-bandgap voltage is understood to be below 1.2V for Silicon. 
     Generally, there are two known basic components that are used to generate a bandgap voltage reference output. A first component of such electronic circuits is usually a directly-biased diode, for example a base-emitter voltage of a bi-polar junction transistor (BJT) device, with a negative temperature coefficient. A second component of such electronic circuits is a voltage difference of directly biased diodes that is configured as providing an output proportional to absolute temperature voltage. Thus, by arranging the outputs of these components in an appropriate ratio, the sum of the outputs is able to provide a voltage reference that is almost independent of temperature. Notably, in current electronic circuits, the output voltage of a bandgap voltage reference under such conditions is approximately 1.2V. 
     Unfortunately, the base-emitter voltage of a bipolar transistor does not change linearly with transistor temperature. Hence, it is known that a simple bandgap circuit that sums only two components in the above manner has an output parabolic curvature response and a second-order temperature dependence. Therefore, in order to increase the temperature stability of the voltage reference, a second-order compensation circuit is generally applied. 
     The temperature dependence of a voltage reference can be seen in the temperature dependence of the base-emitter voltage of a forward-biased bipolar transistor, as illustrated in equation [1]: 
                     Vbe   =       Vg   ⁢           ⁢   0     -       (       Vg   ⁢           ⁢   0     -     Vbe   R       )     ⁢     T     T   R         -       (     n   -   x     )     ·       k   ·   T     q     ·     ln   ⁡     (     T     T   R       )             ,           (   1   )               
where:
 
     Vgo: is the bandgap voltage of silicon, extrapolated to ‘0’ degrees Kelvin, 
     VbeR is the base-emitter voltage at temperature Tr, 
     T: is the operation temperature, 
     T R : is a reference temperature, 
     n: is a process dependent, but temperature 
     independent, parameter, 
     x: is equal to 1 if the bias current is PTAT and goes to ‘0’ when the current is temperature-independent, i.e. if a current, flowing through a diode is not temperature-dependent, then Vbe changes in accordance with its own temperature parameters. In a case where a current flowing through a diode is temperature-dependent, then Vbe changes in accordance with its own and current temperature parameters. Thus, x=1 if a bias current is linearly proportional to temperature, and x=0,if it is temperature independent. 
     k: is Boltzmann&#39;s constant, and 
     q: is the electrical charge of an electron. 
     It can be seen, that the first term in [1] is a constant, the second term is a linear function of temperature, and the last term is a non-linear function. In first order bandgap reference circuits, only the linear (second) term from [1] is usually compensated. The non-linear term from [1] stays uncompensated, thereby producing the output parabolic curvature. 
       FIG. 1  illustrates a schematic diagram  100  of a conventional first order bandgap reference circuit, where the output voltage Vref  125  is assumed to have exact first order temperature compensation. The circuit comprises of positive and negative temperature dependant current generators, based on Q 1   120 , Q 2   122 , m 4   124 , r 1   126  and current mirrors  110 ,  112 . The circuit further comprises an output stage  130 , which is based on resistor r 2  and Q 3  as a diode. Q 1   120  produces a negative temperature-dependant current. The Vbe difference between Q 1   120  and Q 2   122  is applied to resistor r 1   126 . As a result the Q 2  emitter current is proportional to delta Vbe, divided by r 1   126 , and has positive temperature-dependence. 
     Current mirror m 1   110 , m 2   112  and transistors Q 1   120 , Q 2   122  and m 4   124  produce negative feedback to compensate for the collector current of Q 1   120  and the drain current of m 1   110 . Current mirror m 2   112  and m 3   114  produce an m 3  drain current proportional to the collector current of Q 2   122 . Transistor m 4   124  and current mirror m 5   116  and m 6   118  form an m 6  drain current that is proportional to the base currents of Q 1   120  and Q 2   122 . Both drain currents of m 3   114  and m 6   118  flow through the output stage, thereby producing a voltage drop on diode Q 3  with negative temperature-dependence and a resistor r 2  with positive temperature-dependence. In a case where their temperature coefficients are equal to each other, then the output voltage ( 125 ) will be temperature compensated. 
     The exact first order temperature compensation is expressed by: 
                       V   refBG     =       Vg   ⁢           ⁢   0     -       (     n   -   x     )     ·       k   ·   T     q     ·     ln   ⁡     (     T     T   R       )             ,           (   2   )               
where:
 
     VrefBG: is an output voltage of the bandgap reference. 
     Hence, the output voltage  125  of a conventional bandgap reference is around Vgo, which is approx. 1.2V with several millivolts (mV) of parabolic curvature caused by the non-linear term from [2]. 
     However, the trend in high performance electrical equipment, particularly portable communication equipment, is that a supply voltage of 1.5V or less needs to be used. Thus, in the context of the present invention, with battery-powered portable equipment such as an audio player or a camera, 1.5V is an initial voltage for battery voltage source, for example an ‘A’-size. If a battery is ‘discharged’ then the voltage falls below 1V. 
     U.S. Pat. No. 6,157,245,describes a circuit that uses the generation of three currents with different temperature dependencies together and employs a method of exact curvature compensation. A significant disadvantage of the circuit proposed in U.S. Pat. No. 6,157,245 is that it proposes five ‘critically-matched’ kohm resistors −22.35, 244.0, 319.08, 937.1 and 99.9. The large resistance ratio (up to 1:42) and the large spread of the ratios (from 1:4.5 up to 1:42) will be problematic and excessive mismatching of the resistors would be expected. 
     Furthermore, the trimming procedure to attempt to accurately and critically match the five resistors becomes too expensive for the circuit to be used in practice. Therefore, such a circuit is highly impractical for mass-produced devices. 
     The paper by P. Malcovati et al, titled “Curvature-Compensated BiCMOS Bandgap with 1-V Supply Voltage”, published in the IEEE Journal of Solid-State Circuits, vol. 36, No. 7, July 2001, pp. 1076-1081, also proposes a complicated circuit that includes an operational amplifier, five critically-matched resistors as well as three critically matched bipolar transistor groups. 
     Thus, there exists a need in the field of the present invention for a sub-bandgap voltage reference that is able to generate a fraction of 1.2V, notably with temperature stability comparable to current sub-bandgap voltage references. 
     STATEMENT OF INVENTION 
     Accordingly, the preferred embodiment of the present invention seeks to preferably mitigate, alleviate or eliminate one or more of the above-mentioned disadvantages, singly or in any combination. 
     In accordance with the present invention, there is provided a reference circuit as claimed in the appended Claims. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  illustrates a known schematic diagram of a conventional first order bandgap voltage reference circuit. 
       Exemplary embodiments of the present invention will now be described, with reference to the accompanying drawings, in which: 
         FIG. 2  illustrates schematic diagram of a first order sub-bandgap voltage reference circuit employing the inventive concepts in accordance with an embodiment of the present invention; 
         FIG. 3  illustrates a schematic diagram of a second order (exact curvature compensated) sub-bandgap voltage reference circuit employing the inventive concepts in accordance with an enhanced embodiment of the present invention; 
         FIG. 4  illustrates a typical plot of a first order sub-bandgap voltage reference versus an exact curvature compensated sub-bandgap voltage reference; 
         FIG. 5  illustrates a reference voltage distribution diagram using a circuit according to the present invention; 
         FIG. 6  illustrates a graph of reference voltage versus temperature for two different samples measured using the circuit according to the present invention; and 
         FIG. 7  illustrates graphs of trimmed reference voltages versus temperature for two different samples measured using the circuit according to the present invention. 
     
    
    
     DESCRIPTION OF PREFERRED EMBODIMENTS 
     The preferred embodiment of the present invention is described with reference to improving a design and operation of a sub-bandgap voltage reference circuit. However, it is within the contemplation of the present invention that the inventive concepts described herein are equally applicable to sub-bandgap current reference circuits. 
     Notably, in the prior art circuit of  FIG. 1 , the output voltage is limited by the voltage drop across diode Q 3 , which can not be reduced below a value dependent upon the diode size and flowing current (ordinarily 0.6V-0.8V). However, the preferred embodiment of the present invention proposes a circuit that provides an output voltage that is proportional to resistor r 2  and the current values I 1  and I 2 . In this manner, it is possible to adjust the output voltage below 0.6V, by selecting appropriate values for r 2 , I 1  and I 2 . 
     The preferred embodiment of the present invention consists of bipolar and CMOS transistor circuits arranged to obtain a straightforward curvature compensation for a sub-bandgap reference. Notably, these sub-circuits are combined in such a manner that the output voltage of the reference becomes substantially linear and independent of the operating temperature. It is envisaged that the inventive concepts herein described are equally applicable to a purely bi-polar circuit arrangement, as it is based substantially on the exponential temperature-dependence Vbe of a bipolar diode. 
     The preferred embodiments of the present invention propose respective sub-circuits that generate three currents. A first current is proportional to absolute temperature. A second current is proportional to a bipolar transistor&#39;s base-emitter voltage. A third current is proportional to a non-linear term in a base-emitter voltage and is temperature dependent. Notably, the currents are provided in such a ratio that their sum is independent of temperature in both a first order manner as well as in a second order manner. The sum of three currents are arranged to provide a temperature independent output voltage by means of an output resistor. 
       FIG. 2  illustrates a simplified topology of a proposed sub-bandgap voltage reference circuit  200 . The circuit illustrated in  FIG. 2  comprises the PTAT current generator and Vbe/R current generator  220 ,  222 , current mirrors  210 - 218  and the output stage with resistor r 2   230 , connected to ground. The PTAT current generator comprises NPN transistors Q 1   220  and Q 2   222 , resistor r 1   226 , NMOS transistor m 4   224  and an active current mirror circuit CM 1   210 ,  212  and  214 . 
     Resistor r 3   228  produces a current proportional to the Vbe of Q 1   220  divided by the value of resistor r 3   228 . As a result the drain current I 2  of m 4   224  is a sum of the base of Q 1   220 , Q 2   222  and resistor r 3   228 . Currents I 1  and I 2  are with positive and negative temperature dependence accordingly. Both currents I 1  and I 2 , flowing through resistor r 2   230  generate an output voltage  225  proportional in a bandgap range. 
     The current mirror circuit CM 1  forces the collector currents of transistors Q 1  and Q 2  to be equal (in general, collector currents of Q 1  and Q 2  can relate as M:K). The expression for the PTAT current follows from the collector current dependence on the base-emitter voltage. 
     Notably, the circuit topology in  FIG. 2  provides a number of new and enhanced features over the known circuit of  FIG. 1 : 
     (i) The reference voltage can be freely adjusted to any convenient value from zero (ground potential) up to Vcc (supply voltage potential), by changing the value of r 2  resistor without affecting the temperature stability of the circuit. 
     (ii) The simple temperature-compensated current reference can be easily obtained. The source current is available at the output terminal of the circuit if the r 2  resistor is removed. Advantageously, the sink current can be produced with a use of either an NPN or an NMOS current mirror. 
     (iii) The sub-bandgap voltage reference of  FIG. 2  can be easily “upgraded” with an exact curvature compensation network, as described below. Temperature stability of the circuit is thus improved substantially. 
     A description of the exact curvature compensation that is applied in the preferred embodiment of the present invention is presented below. 
     The output voltage of the conventional first order bandgap reference can be expressed as: 
                       Ic   =       Ics   ·     (       [     exp   ⁢     Vbe     m   ·   Vt         ]     -   1     )       ≈       Ics   ·   exp     ⁢     Vbe     m   ·   Vt             ;     (     Vbe   ⪢     Vt   .       )       ,           (   3   )               
where:
 
     Ics is a saturation current of collector, 
     ‘m’ is a non-ideality factor, and 
     Vt is a thermal voltage, Vt=kT/q, and can be expressed as (assuming Icqi=IcQ 2 =I 1 ): 
                       I   ⁢           ⁢   1     =         1     r   ⁢           ⁢   1       ·       k   ·   T     q     ·   ln     ⁢           ⁢   N       ,           (   4   )               
where:
 
     I 1  is a PTAT current, and 
     N is an emitter area ratio of Q 2  and Q 1 . 
     From  FIG. 2 , the Vbe/R current generator comprises NPN transistors Q 1   220  and Q 2   222  with resistor r 1   226 , resistor r 3   228 , NMOS transistor m 4   224  and a current mirror circuit CM 2   216 ,  218 . Thus, the Vbe/R current generator produces an output current of: 
                       I   ⁢           ⁢   2     =         Vbe     Q   ⁢           ⁢   1         r   ⁢           ⁢   3       +     Ib     Q   ⁢           ⁢   1       +     Ib     Q   ⁢           ⁢   2           ,           (   5   )               
where:
 
     I 2  is the Vbe/R current, 
     VbeQ 1  is a base-emitter voltage of transistor Q 1   220 , and 
     IbQ 1  and IbQ 2  are the base currents of Q 1   220  and Q 2   222  transistors respectively. 
     Comparing the circuits in  FIG. 1  and  FIG. 2  it can be seen that transistor m 4   124  from  FIG. 1  is used only as a “beta helper”, providing a base drive to Q 1   120  and Q 2   122 . However, and advantageously, the m 4  transistor  224  in the circuit of  FIG. 2  provides an additional function, namely Vbe/R current generation. Thus, transistor m 4   224  in  FIG. 2  performs two functions:
         (i) It generates negative temperature current; and   (ii) It provides Q 1 , Q 2  base currents to concurrently compensate for non-linearity.       

     Hence, the functional integration, i.e. the increased functionality of m 4  in the preferred embodiment, is a key factor for producing a new quality of the device performance without excessive complication of the circuit design. Notably, the I 1  and I 2  currents in  FIG. 2  are added in such a proportion that their sum is independent of temperature, in a first order. Assuming that:
 
( VbeQ 1 /r 3)&gt;&gt;( IbQ 1 +IbQ 2),
 
     then the condition of the temperature independence can be derived from equations [1], [4] and [5], as shown in equation [6]: 
                       r   ⁢           ⁢   3     =       r   ⁢           ⁢     1   ·   e   ·   q           k   ·   ln     ⁢           ⁢   N         ,     e   =         Vg   ⁢           ⁢   0     -     Vbe     Q   ⁢           ⁢   1   ⁢   R           T   R         ,           (   6   )               
where:
 
     ‘e’ is a linearised temperature coefficient of a base-emitter voltage, and 
     VbeQ 1 R is a base-emitter voltage of transistor Q 1  at temperature T R . 
     The sum of I 1  and I 2  currents flow through the output resistor r 2 , producing the temperature independent voltage drop (in the first order): 
                       V   refSBG     =         r   ⁢           ⁢   2       r   ⁢           ⁢   3       ·     (       Vg   ⁢           ⁢   0     -       (     n   -   x     )     ⁢       k   ·   T     q     ⁢     ln   ⁡     (     T     T   R       )           )         ,           (   7   )               
where:
 
     VrefsBG is an output voltage of the sub-bandgap reference. 
     Thus, the output voltage of the proposed first order sub-bandgap reference is VrefBG*r 2 /r 3 , with similar parabolic curvature caused by the nonlinear term from equation [7]. The typical temperature dependence of an output voltage of the first order sub-bandgap reference is depicted in  FIG. 4 . 
     Referring now to  FIG. 3 , a simplified schematic diagram of an enhanced embodiment of a second order compensation circuit of the present invention is illustrated. In summary, the circuit presented in  FIG. 3  is similar to the circuit depicted in  FIG. 2 , but with an additional compensation network. The additional network comprises PMOS transistors m 7  and m 8   340 , a diode-connected bipolar transistor Q 3   330  and a resistor r 4   350 . All these additional elements combine in a manner shown in  FIG. 3  in order to achieve the exact curvature compensation, as hereinbefore described. 
     Following from equation [1], the base-emitter voltage of the Q 1  transistor of  FIG. 2 , biased by the PTAT current I 1  of equation [4], can be given as: 
                       Vbe     Q   ⁢           ⁢   1       =       V   A     =       Vg   ⁢           ⁢   0     -       (       Vg   ⁢           ⁢   0     -     Vbe     Q   ⁢           ⁢   1   ⁢   R         )     ·     T     T   R         -       (     n   -   1     )     ·       k   ·   T     q     ·     ln   ⁡     (     T     T   R       )               ,           (   8   )               
where:
 
     ‘x’ is equal to ‘1’, since the bias current is PTAT. 
     The diode-connected bipolar transistor Q 3  is biased, in the enhanced embodiment, by the sum of three currents I 1 , I 2  and I 3 . The sum of I 1  and I 2  is independent of temperature in a first order (as shown in equations [4], [5] and [6]). As illustrated below, the I 3  current increases the temperature independence of the sum of the three currents I 1 , I 2  and I 3 . Thus, the base-emitter voltage of Q 3  transistor can be given as: 
                       Vbe   Q3     =       V   B     =       Vg   ⁢           ⁢   0     -       (       Vg   ⁢           ⁢   0     -     Vbe     Q   ⁢           ⁢   3   ⁢   R         )     ·     T     T   R         -     n   ·       k   ·   T     q     ·     ln   ⁡     (     T     T   R       )               ,           (   9   )               
where:
 
     ‘x’ is equal to ‘0’ since the bias current is temperature-independent. 
     The difference between the base-emitter voltages of Q 1  and Q 3  can be derived from equations [8] and [9]: 
                         V   A     -     V   B       =       Vg   ⁢           ⁢   0     -       (       Vbe     Q   ⁢           ⁢   1   ⁢   R       -     Vbe     Q   ⁢           ⁢   3   ⁢   R         )     ·     T     T   R         +         k   ·   T     q     ·     ln   ⁡     (     T     T   R       )             ,           (   10   )               
where:
 
     VbeQ 1 R is a base-emitter voltage of transistor Q 1  at temperature T R , and 
     VbeQ 3 R is a base-emitter voltage of transistor Q 3  at temperature T R . 
     If the first term in equation [10] is made equal to zero, the difference between the base-emitter voltages of Q 1  and Q 3  are proportional only to a curvature voltage that has to be compensated for. 
     In order to equalize VbeQ 1 R and VbeQ 3 R values, the emitter current densities of Q 1  and Q 3  at the reference temperature must be equalized. The current flowing through Q 1  is I 1 . The current flowing through Q 3  is I 1 +I 2  (in a first order). However, I 2 =I 1  at T=T R . Thus, the simplest way to equalize VbeQ 1 R and VbeQ 3 R values is to use Q 3  as two Q 1  transistors that are connected in parallel, as shown in  FIG. 3 . 
     Thus, 
     
       
         
           
             
               
                 
                   
                     
                       
                         V 
                         A 
                       
                       - 
                       
                         V 
                         B 
                       
                     
                     = 
                     
                       
                         
                           k 
                           · 
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                         q 
                       
                       · 
                       
                         ln 
                         ⁡ 
                         
                           ( 
                           
                             T 
                             
                               T 
                               R 
                             
                           
                           ) 
                         
                       
                     
                   
                   , 
                 
               
               
                 
                   ( 
                   11 
                   ) 
                 
               
             
           
         
       
     
     The voltage difference expressed in equation [11] is applied to resistor r 4  pins, thereby producing a non-linear current I 3 : 
     
       
         
           
             
               
                 
                   
                     
                       I 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       3 
                     
                     = 
                     
                       
                         1 
                         
                           r 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           4 
                         
                       
                       · 
                       
                         
                           k 
                           · 
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                         q 
                       
                       · 
                       
                         ln 
                         ⁡ 
                         
                           ( 
                           
                             T 
                             
                               T 
                               R 
                             
                           
                           ) 
                         
                       
                     
                   
                   , 
                 
               
               
                 
                   ( 
                   12 
                   ) 
                 
               
             
           
         
       
     
     In  FIG. 2 , the sum of the non-linear current I 3  and the Vbe/R current I 2  flows through both the m 4  transistor and the output resistor r 2 , due to the current mirror circuit CM 2 . Thus, transistor m 4  produces a new additional function, as it also takes part in the non-linear current generation. 
     Now the expression for reference voltage, using equations [1], [4], [5], [6] and [12], can be derived: 
     
       
         
           
             
               
                 
                   
                     
                       
                         
                           V 
                           ref 
                         
                         = 
                         
                           r 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           
                             2 
                             · 
                             
                               ( 
                               
                                 
                                   I 
                                   ⁢ 
                                   
                                       
                                   
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                                   · 
                                   
                                     ( 
                                     
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                                   · 
                                   
                                     
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                                       · 
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                                   · 
                                   
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                                     ⁡ 
                                     
                                       ( 
                                       
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                                       ⁢ 
                                       
                                           
                                       
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                                   · 
                                   
                                     
                                       k 
                                       · 
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                                   · 
                                   
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                                     ⁡ 
                                     
                                       ( 
                                       
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                               ) 
                             
                           
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   13 
                   ) 
                 
               
             
           
         
       
     
     Notably, there are two non-linear terms in equation [13]. In accordance with the preferred embodiment of the present invention, the exact curvature compensation can be achieved when both non-linear terms in [13] are eliminated: 
     
       
         
           
             
               
                 
                   
                     
                       1 
                       
                         r 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         3 
                       
                     
                     · 
                     
                       ( 
                       
                         n 
                         - 
                         1 
                       
                       ) 
                     
                     · 
                     
                       
                         k 
                         · 
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                     · 
                     
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                       ⁡ 
                       
                         ( 
                         
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                   = 
                   
                     
                       
                         
                           1 
                           
                             r 
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                       → 
                       
                         
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                             ⁢ 
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                         · 
                         
                           ( 
                           
                             n 
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                           ) 
                         
                       
                     
                     = 
                     
                       
                         
                           1 
                           
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                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             4 
                           
                         
                         → 
                         
                           r 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           4 
                         
                       
                       = 
                       
                         
                           r 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           3 
                         
                         
                           ( 
                           
                             n 
                             - 
                             1 
                           
                           ) 
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   14 
                   ) 
                 
               
             
           
         
       
     
     The expression in equation [14] describes the condition of exact and straightforward curvature compensation for the sub-bandgap voltage reference depicted in  FIG. 3 . As mentioned previously, ‘n’ is a temperature-independent process parameter and typically has a value in the range of ‘3.6’ to ‘4.0’. 
     The expression for the reference voltage under the condition defined in equation [14] therefore becomes: 
                       V   ref     =           r   ⁢           ⁢   2       r   ⁢           ⁢   3       ·   Vg     ⁢           ⁢   0       ,           (   15   )               
where:
 
     Vref is an output voltage of the curvature compensated sub-bandgap reference. 
     Thus, it can be seen from equation [15] that an exact curvature compensation technique, as proposed in the present invention, substantially eliminates all temperature-dependent and logarithmic terms at a theoretical level. The reference voltage is determined by the resistor ratio, and is advantageously minimally influenced by the actual value of the resistance. 
     Referring now to  FIG. 4  to  FIG. 7 , experimental results were taken from the circuit that realizes the proposed method of exact curvature compensation. The results were taken from a circuit implemented in a submicron BiCMOS technology (SmartMOS 5HV+). Advantageously, the practical realization of the proposed circuit achieves 2.9 ppm/K of temperature coefficient and −76 dB power supply rejection ratio, without requiring operational amplifiers or complex circuits for the curvature compensation. In order to achieve such a low temperature coefficient, 4-bit linear and 2-bit logarithmic (non-linear) trimming circuits were used. 
     Referring now to  FIG. 4 , a plot  400  illustrates reference voltages of a first order sub-bandgap voltage reference  410  versus an exact curvature compensated sub-bandgap voltage reference  420  that employs the inventive concepts according to the preferred embodiment of the present invention. 
     In  FIG. 4 , the plot  400  of the exact curvature compensated sub-bandgap voltage reference illustrates that the temperature stability of a curvature compensated voltage reference  420  exceeds the stability of an uncompensated one  410  by a significant amount. 
     Notably, the non-predicted curvature  410  has a non-parabolic character, which can be caused by thermal leakage currents, (which a skilled artisan will appreciate may be included in the models of real transistors). Hence, a skilled artisan will also appreciate that different errors and non-idealities, such as voltage or area mismatches in the current mirrors or in transistor emitter areas or resistor mismatches or temperature coefficients, may also cause other unpredictable curvature errors. 
     Referring now to  FIG. 5 , a distribution diagram  500  illustrates a count of reference voltage using a circuit that employs a method of exact curvature compensation according to the present invention. The distribution diagram  500  of  FIG. 5  illustrates twenty samples measured at room temperature for a default trimming state, where the samples were taken from the same wafer. In effect, the distribution diagram  500  illustrates that inventive concepts work and that a sub-bandgap reference voltage can be generated that is very accurate. The average value and the standard deviation of the reference distribution were then evaluated. 
     Referring now to  FIG. 6 , a graph  600  illustrates experimental results for reference voltage versus temperature before trimming. The graph illustrates three trimming options, measured over temperature range. A first graph comprises an additional four trimming steps over a default number  610 , a second graph with a default number of trimming steps  620  and a third with four less trimming steps than the default number  630 . 
     It can be seen from  FIG. 6  that the curvature is still not completely compensated under the default non-linear trimming condition  620 . Hence, a non-linear trimming procedure is preferably implemented to achieve a minimal temperature coefficient of the reference voltage. After employing an exact trimming method according to the inventive concepts hereinbefore described, the graphs illustrate that for both non-linear and linear components of the reference voltage, a minimal temperature coefficient was achieved. 
     Referring now to  FIG. 7 , graphs  700  of trimmed reference voltages versus temperature, for two different measured samples, are illustrated using the circuit according to the present invention. Three sets of samples  710 ,  720 ,  730  are illustrated, representing linear trimming steps ‘N+1’, ‘N’ and ‘N−1’, around the minimal Temperature Compensation (TC) point, respectively. It can be seen from  FIG. 7 , that parabolic curvature of the reference voltage is completely eliminated. 
     It will be appreciated by a skilled artisan that although the above description has been described with reference to positive metal oxide semiconductor (PMOS) transistor technology, the PMOS devices may be replaced by PNP bi-polar transistor technology with appropriate characteristics. Similarly, a skilled artisan will appreciate that NPN bi-polar transistors (or indeed HBT NPN transistors) may replace the negative metal oxide semiconductor (NMOS) transistors in the above description. 
     Thus, in summary, the known prior art reference circuit comprises the generation of a single current having a positive temperature-dependence and arranged to flow through an output stage. In contrast, the preferred embodiments of the present invention propose the generation of two currents (one having positive temperature-dependence and one having negative temperature-dependence, per  FIG. 2 ) or three currents (with an additional curvature-compensated current) to generate a temperature-independent (and preferably curvature-compensated) output voltage. 
     It will be understood that the reference circuit and operation thereof described above aims to provide one or more of the following advantages:
         (i) The preferred circuit only uses three critically matched resistors, related in a preferred 1:3:10 ratio, due to a certain functional integration achieved;   (ii) The preferred circuit does not use operational amplifiers or other complex circuits to achieve straightforward curvature compensation;   (iii) The preferred circuit to generate a sum of the second current and base currents (IbQ 1 , IbQ 2 ) of the first current generator provides an output voltage of the reference circuit that is substantially independent of the operating temperature of the circuit;   (iv) The output voltage can be freely adjusted to any convenient value from a ground potential to supply voltage potential, without changing the temperature stability of the circuit;   (v) The provision of the curvature compensated network enables the output voltage of the reference circuit to compensate for non-linearity in the output voltage as well as be substantially independent of the operating temperature of the circuit   (vi) The minimal supply voltage is not limited to just an output voltage value, as it can be below 1.2V.       

     Whilst the specific and preferred implementations of the embodiments of the present invention are described above, it is clear that one skilled in the art could readily apply variations and modifications of such inventive concepts. 
     In particular, it will be appreciated that the above description for clarity has described embodiments of the invention with reference to different functional units of the processing system. However, it will be apparent that any suitable distribution of functionality between different functional units may be used without detracting from the invention. Hence, references to specific functional units are only to be seen as references to suitable means for providing the described functionality rather than indicative of a strict logical or physical structure, organization or partitioning.