Patent Publication Number: US-2021182056-A1

Title: Apparatuses, methods, and systems for instructions to multiply values of one

Description:
TECHNICAL FIELD 
     The disclosure relates generally to electronics, and, more specifically, an embodiment of the disclosure relates to circuitry to implement an instruction to multiply values of one. 
     BACKGROUND 
     A processor, or set of processors, executes instructions from an instruction set, e.g., the instruction set architecture (ISA). The instruction set is the part of the computer architecture related to programming, and generally includes the native data types, instructions, register architecture, addressing modes, memory architecture, interrupt and exception handling, and external input and output (I/O). It should be noted that the term instruction herein may refer to a macro-instruction, e.g., an instruction that is provided to the processor for execution, or to a micro-instruction, e.g., an instruction that results from a processor&#39;s decoder decoding macro-instructions. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The present disclosure is illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements and in which: 
         FIG. 1  illustrates a hardware processor coupled to a memory according to embodiments of the disclosure. 
         FIG. 2A  illustrates a circuit in floating-point mode and comprising a “ones” detector circuit coupled to a “ones” multiplier circuit according to embodiments of the disclosure. 
         FIG. 2B  illustrates a circuit in integer mode and comprising a “ones” detector circuit coupled to a “ones” multiplier circuit according to embodiments of the disclosure. 
         FIG. 3  illustrates matrix operations circuitry including a “ones” mode according to embodiments of the disclosure. 
         FIG. 4  illustrates circuitry including a plurality of parallel “ones” multiplier circuits coupled to an adder circuit according to embodiments of the disclosure. 
         FIG. 5  illustrates circuitry including a plurality of parallel “ones” multiplier circuits according to embodiments of the disclosure. 
         FIG. 6  illustrates a hardware processor, coupled to storage that includes one or more “ones” multiplication instructions, having a “ones” detector circuit coupled to an execution circuit according to embodiments of the disclosure. 
         FIG. 7  illustrates a hardware processor, coupled to storage that includes one or more “ones” multiplication instructions, having a “ones” detector circuit of an execution circuit according to embodiments of the disclosure. 
         FIG. 8  illustrates a method of processing a “ones” multiplication instruction according to embodiments of the disclosure. 
         FIG. 9A  is a block diagram illustrating a generic vector friendly instruction format and class A instruction templates thereof according to embodiments of the disclosure. 
         FIG. 9B  is a block diagram illustrating the generic vector friendly instruction format and class B instruction templates thereof according to embodiments of the disclosure. 
         FIG. 10A  is a block diagram illustrating fields for the generic vector friendly instruction formats in  FIGS. 9A and 9B  according to embodiments of the disclosure. 
         FIG. 10B  is a block diagram illustrating the fields of the specific vector friendly instruction format in  FIG. 10A  that make up a full opcode field according to one embodiment of the disclosure. 
         FIG. 10C  is a block diagram illustrating the fields of the specific vector friendly instruction format in  FIG. 10A  that make up a register index field according to one embodiment of the disclosure. 
         FIG. 10D  is a block diagram illustrating the fields of the specific vector friendly instruction format in  FIG. 10A  that make up the augmentation operation field  950  according to one embodiment of the disclosure. 
         FIG. 11  is a block diagram of a register architecture according to one embodiment of the disclosure 
         FIG. 12A  is a block diagram illustrating both an exemplary in-order pipeline and an exemplary register renaming, out-of-order issue/execution pipeline according to embodiments of the disclosure. 
         FIG. 12B  is a block diagram illustrating both an exemplary embodiment of an in-order architecture core and an exemplary register renaming, out-of-order issue/execution architecture core to be included in a processor according to embodiments of the disclosure. 
         FIG. 13A  is a block diagram of a single processor core, along with its connection to the on-die interconnect network and with its local subset of the Level 2 (L2) cache, according to embodiments of the disclosure. 
         FIG. 13B  is an expanded view of part of the processor core in  FIG. 13A  according to embodiments of the disclosure. 
         FIG. 14  is a block diagram of a processor that may have more than one core, may have an integrated memory controller, and may have integrated graphics according to embodiments of the disclosure. 
         FIG. 15  is a block diagram of a system in accordance with one embodiment of the present disclosure. 
         FIG. 16  is a block diagram of a more specific exemplary system in accordance with an embodiment of the present disclosure. 
         FIG. 17 , shown is a block diagram of a second more specific exemplary system in accordance with an embodiment of the present disclosure. 
         FIG. 18 , shown is a block diagram of a system on a chip (SoC) in accordance with an embodiment of the present disclosure. 
         FIG. 19  is a block diagram contrasting the use of a software instruction converter to convert binary instructions in a source instruction set to binary instructions in a target instruction set according to embodiments of the disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     In the following description, numerous specific details are set forth. However, it is understood that embodiments of the disclosure may be practiced without these specific details. In other instances, well-known circuits, structures and techniques have not been shown in detail in order not to obscure the understanding of this description. 
     References in the specification to “one embodiment,” “an embodiment,” “an example embodiment,” etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to affect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described. 
     A (e.g., hardware) processor (e.g., having one or more cores) may execute instructions (e.g., a thread of instructions) to operate on data, for example, to perform arithmetic, logic, or other functions. For example, software may request an operation and a hardware processor (e.g., a core or cores thereof) may perform the operation in response to the request. One non-limiting example of an operation is a multiplication operation. For example, a computing system forming a neural network may include numerous multiplication operands where the multiplier value is one and/or the multiplicand value is one. Certain embodiments herein allow for the skipping of certain multiplication operations of values of one. These embodiments thus allow hardware performance and power optimizations from the skipping by those multiplication operations. 
     The operations may be performed on numerical data having different formats (e.g., representations) in a computing system (e.g., accelerator and/or processor). In certain embodiments, a number is in fixed-point format or a floating-point format. An integer may be represented in a binary format. A signed integer may be represented in a two&#39;s (2&#39;s) complement format (e.g., where the leading being zero indicates a positive integer and a leading one indicates a negative integer). A (e.g., real) number may be represented in floating-point format, e.g., to represent, with a fixed number of digits, numbers of different orders of magnitude. 
     One example of a numerical format is where a number is generally approximated to a fixed number of significant digits (the significand) and scaled using an exponent in some fixed base (e.g., a base of two, ten, or sixteen). An example of a numerical format where S represents a sign bit, M a mantissa, and E an exponent is as follows: 
         x =significand×base exponent   (1)
 
     An example of a floating-point format is as follows: 
         x =(−1) s ×1· M× 2 E-bias   (2)
 
     In accordance with the IEEE 754 standard for binary FP arithmetic, the mantissa is an unsigned number (e.g., a binary fraction) and a normalized floating-point number has a single one in the most-significant-bit (MSB) position. In certain embodiments, this bit (e.g., to the left of the decimal point) is implicit and therefore the mantissa does not need to store it. In certain embodiments, the exponent is represented here as a non-negative integer from which a constant bias is subtracted. Examples of floating-point formats are floating point 16 (e.g., binary16), floating point 32 (e.g., binary32), floating point 64 (e.g., binary64), floating point 128 (e.g., binary128), and floating point 256 (e.g., binary256), although any number of sign, significand (e.g., mantissa thereof), or exponent bits may be used in certain embodiments. In one embodiment, binary16 format has one bit for the sign bit, 5 bits for the exponent, and 11 bits implicit (10 explicitly stored) for the significand. In one embodiment, binary32 format has one bit for the sign bit, 8 bits for the exponent, and 24 bits implicit (23 explicitly stored) for the significand. In one embodiment, binary64 format has one bit for the sign bit, 11 bits for the exponent, and 53 bits implicit (52 explicitly stored) for the significand. In one embodiment, binary128 format has one bit for the sign bit, 15 bits for the exponent, and 113 bits implicit (112 bits explicitly stored) for the significand. In one embodiment, binary256 format has one bit for the sign bit, 19 bits for the exponent, and 237 bits implicit (236 bits explicitly stored) for the significand. 
     Certain embodiments of neural networks (e.g., an integer network or a floating-point network) have numerous operations that include at least one input value of one. Thus, for these neural networks (e.g., circuitry implementing the neural network), hardware performance (e.g., and power) optimizations are achieved by effectively skipping “by one” multiplications. 
     An instruction format may include an opcode (e.g., a proper subset of the opcode) or other field (e.g., operand or immediate) to indicate a multiplication of values that include one or more “ones” is to not be performed. An instruction format may include an opcode (e.g., a proper subset of the opcode) or other field (e.g., operand or immediate) to indicate that a resultant of a requested multiplication of a plurality of inputs values that are either a one is the other value that is not one (e.g., or the resultant of the requested multiplication of a plurality of inputs values that are each one is output as exactly one). In certain embodiments, a number format of the instruction indicates when a value that is “one” is included in the instruction (e.g., as an opcode or other field). In certain embodiments, a multiplier that was to be used for the multiplication operation is instead off (e.g., is turned off or not turned on) and thus saves power. As the number of multiplications may be great (e.g., 10s, 100s, 1000s, etc.), this power savings scales accordingly with a plurality of multipliers that include circuitry to provide a resultant of a multiplication of a pair of inputs values that are either one. An instruction may include one or more (e.g., any) of the fields discussed herein. 
     The instructions disclosed herein are improvements to the functioning of a processor (e.g., of a computer) itself. Instruction decode circuitry (e.g., a decoder) not having such an instruction as a part of its instruction set would not decode as discussed herein. An execution circuit not having such an instruction as a part of its instruction set would not execute as discussed herein. For example, a single instruction that, when a processor decodes the single instruction into a decoded instruction and that decoded instruction is executed by the processor, causes a first comparison of the first number to a one value in the number format of the first number, causes a second comparison of the second number to a one value in the number format of the second number, provides as a resultant of the single instruction the first floating-point number when the second comparison indicates the second number equals the one value in the number format of the second number, provides as the resultant of the single instruction the second number when the first comparison indicates the first number equals the one value in the number format of the first number, and provides as the resultant of the single instruction a product of a multiplication of the first number and the second number when the first comparison indicates the first number does not equal the one value in the number format of the first number and the second comparison indicates the second number does not equal the one value in the number format of the second number, is an improvement to the functioning of the processor (e.g., of a computer) itself. 
       FIG. 1  illustrates a hardware processor  100  coupled to a memory  110  according to embodiments of the disclosure. Depicted hardware processor  100  includes a hardware decoder  102  (e.g., decode unit or decode circuit) and a hardware execution circuit  104  (e.g., execution unit). Depicted hardware processor  100  includes register(s)  106 . Registers may include one or more of registers to access (e.g., load and/or store) data in, e.g., additionally or alternatively to access (e.g., load or store) of data in memory  110 . Depicted hardware processor  100  includes cache  108 . Cache may include one or more cache banks to access (e.g., load and/or store) data in, e.g., additionally or alternatively to access (e.g., load or store) of data in memory  110  and/or register(s)  106 . 
     Depicted execution circuit  104  includes matrix operations circuitry  112 , scalar circuitry  114 , and/or vector/single instruction, multiple data (SIMD) circuitry  116 . In certain embodiments, only one or any combination of matrix operations circuitry  112 , scalar circuitry  114 , and/or vector/single instruction, multiple data (SIMD) circuitry  116  may be present (e.g., utilized). In certain embodiments, matrix operations circuitry  112  operates on one or more matrices. In one embodiment, matrix operations circuitry  112  is an instance of matrix operations circuitry depicted in  FIG. 3 . Matrix operations circuitry  112  may be included in a core or as an (e.g., external) accelerator. In certain embodiments, scalar circuitry  114  operates on scalar values (e.g., single numbers). In certain embodiments, vector/SIMD circuitry  116  operates on vector or packed data values. 
     Note that the figures herein may not depict all data communication connections. One of ordinary skill in the art will appreciate that this is to not obscure certain details in the figures. Note that a double headed arrow in the figures may not require two-way communication, for example, it may indicate one-way communication (e.g., to or from that component or device). Any or all combinations of communications paths may be utilized in certain embodiments herein. 
     Hardware decoder  102  may receive an (e.g., single) instruction (e.g., macro-instruction) and decode the instruction, e.g., into micro-instructions and/or micro-operations. Hardware execution circuit  104  may execute the decoded instruction (e.g., macro-instruction) to perform an operation or operations. For example, an instruction to be decoded by decoder  102  and for the decoded instruction to be executed by execution circuit  104  may be any instruction discussed herein, e.g., in  FIGS. 6-8 . 
     Multiplier circuit(s) may be any of the multiplier circuits in  FIGS. 2-7 . Certain embodiments herein are directed to a processor that includes an instruction in its instruction set that performs an operation in respond to a multiplication request. For example, a single instruction that, when a processor decodes the single instruction into a decoded instruction and that decoded instruction is executed by the processor, causes a first comparison of the first number to a one value in the number format of the first number, causes a second comparison of the second number to a one value in the number format of the second number, provides as a resultant of the single instruction the first floating-point number when the second comparison indicates the second number equals the one value in the number format of the second number, provides as the resultant of the single instruction the second number when the first comparison indicates the first number equals the one value in the number format of the first number, and provides as the resultant of the single instruction a product of a multiplication of the first number and the second number when the first comparison indicates the first number does not equal the one value in the number format of the first number and the second comparison indicates the second number does not equal the one value in the number format of the second number. 
     The decoder  102 , execution circuit  104 , registers  106 , and/or cache  108  may be of a single core of the processor, e.g., and multiple cores each with an instance of the circuitry may be included. The processor (e.g., and core thereof) may be a processor and/or core according to any of the disclosure herein. 
       FIG. 2A  illustrates a circuit  200  comprising a “ones” detector circuit  201  coupled to a “ones” multiplier circuit  228  according to embodiments of the disclosure. In  FIG. 2A , a number format stores a value that indicates number format of the first input number  202  and/or second input number  204 . In one embodiment, the number format indicates to the comparison circuits  220 ,  222  how (e.g., exactly) one is represented in that particular number format  218 . 
     Depicted circuit  200  includes storage (e.g., flops) for a first floating-point number  202  and a second floating-point number  204 . Depicted format for first floating-point number  202  is a single bit sign field  206 , a plurality of bits for an exponent field  208  (e.g., eight bits or eleven bits), and a plurality of bits for a fraction field  210  (e.g., twenty-three bits or fifty-two bits). Depicted format for second floating-point number  204  is a single bit sign field  212 , a plurality of bits for an exponent field  214  (e.g., eight bits or eleven bits), and a plurality of bits for a fraction field  216  (e.g., twenty-three bits or fifty-two bits). In one embodiment, sign bit is a zero when the number represented in floating-point format is zero or positive, and a one when the number represented in floating-point format is negative. 
     In certain embodiments, number format  218  indicates to comparison circuit  220  that a floating-point value of one includes a zero value in sign bit field  206  of the first number  202 , a leading zero followed by ones value (e.g., 01111111 for an eight bit exponent width) in an exponent field  208  of the first number  202 , and a zero value (e.g., a plurality of zeros in each bit position of the full bit width of the fraction field) in a fraction field  210  of the first number  202  and/or indicates to comparison circuit  222  that a floating-point value of one includes a zero value in sign bit field  212  of the second number  204 , a leading zero followed by ones value (e.g., 01111111 for an eight bit exponent width) in an exponent field  214  of the second number  204 , and a zero value (e.g., a plurality of zeros in each bit position of the full bit width of the fraction field) in a fraction field  216  of the second number  204 . In certain embodiments, number format controls the circuit  200  (e.g., comparison circuits  220 ,  224 ) to switch it between different number formats (e.g., modes), e.g., for floating-point numbers as shown in  FIG. 2A  and for integer numbers as shown in  FIG. 2B . 
     In certain embodiments, in response to a request caused by a decoded instruction, (i) comparison circuit  220  is to compare the value of one as specified by the number format  218  for the first number  202 , and, in one embodiment, a plurality of comparisons by the comparison circuit  220  that includes a comparison of a zero value to a sign bit  206  of the first number  202 , a comparison of a leading zero followed by ones value to an exponent field  208  of the first number  202 , and a comparison of a zero value to a fraction field  210  of the first number  202 , for example, and output a first value (e.g., zero) when the first number  202  is a one value (e.g., when all of the comparison of a zero value to the sign bit  206  of the first number  202 , the comparison of a leading zero followed by ones value to the exponent field  208  of the first number  202 , and the comparison of the zero value to the fraction field  210  of the first number  202  by the comparison circuit  220  are true (not false)) and a second, different value (e.g., one) when the first value  202  is not a one value (e.g., when any of: the comparison of a zero value to the sign bit  206  of the first number  202 , the comparison of a leading zero followed by ones value to the exponent field  208  of the first number  202 , or the comparison of the zero value to the fraction field  210  of the first number  202  by the comparison circuit  220  are false (not true)), and (ii) comparison circuit  222  is to compare the value of one as specified by the number format  218  for the second number  204 , and, in one embodiment, a plurality of comparisons by the comparison circuit  222  that includes a comparison of a zero value to a sign bit  212  of the second number  204 , a comparison of a leading zero followed by ones value to an exponent field  214  of the second number  204 , and a comparison of a zero value to a fraction field  216  of the second number  204 , for example, and output a first value (e.g., zero) when the second number  204  is a one value (e.g., when all of the comparison of a zero value to the sign bit  212  of the second number  204 , the comparison of a leading zero followed by ones value to the exponent field  214  of the second number  204 , and the comparison of the zero value to the fraction field  216  of the second number  204  by the comparison circuit  222  are true (not false)) and a second, different value (e.g., one) when the second number  204  is not a one value (e.g., when any of: comparison of a zero value to the sign bit  212  of the second number  204 , the comparison of a leading zero followed by ones value to the exponent field  214  of the second number  204 , or the comparison of the zero value to the fraction field  216  of the second number  204  by the comparison circuit  222  are false (not true)). In  FIG. 2A , the output from each of comparison circuit  220  and comparison circuit  220  are input to logic gate  224  (e.g., such that an OR logic gate  224  asserts on its output  226  a one when either or both of the inputs are one, or an AND logic gate  224  asserts on its output  226  a one only when both of the inputs are one). For example, with OR logic gate  224  asserting a value (e.g., one) when the first number  202  is a one value or when the second number  204  is a one value. As another example, with AND logic gate  224  asserting a value (e.g., one) when the first number  202  is a one value concurrently with the second number  204  being a one value. 
     In one of such embodiments, output  226  from OR logic gate  224  to “ones” detector circuit  201  is input into “ones” multiplier circuit  228  such that (i) the first number  202  or second number  204  that is not a one value is output from bypass output  234  and provided as output  236  when the first number  202  is a one value or when the second number  204  is a one value, respectively, and (ii) the product output from multiplication of first number  202  and second number  204  by multiplier  230  is provided as output  236  when both the first number  202  is not a one value and the second number  204  is not a one value (e.g., and an exact one from bypass output storage  234  (e.g., constant of one) is provided as output  236  when the first number  202  is a one value concurrently with the second number  204  being a one value). In certain embodiments, a different number format is provided to each comparison circuit. 
     In one embodiment, multiplier  230  is turned off (e.g., via power control switch  232 ) when the first number  202  is a one value or when the second number  204  is a one value, e.g., to conserve power for a multiplication that is not to be performed on first number  202  and second number  204 . 
     In another of such embodiments, output  226  from AND logic gate  224  to “ones” detector circuit  201  is input into “ones” multiplier circuit  228  such that (i) an exact one from bypass output storage  234  (e.g., constant of one) is provided as output  236  when the first number  202  is a one value concurrently with the second number  204  being a one value and (ii) the product output from multiplication of first number  202  and second number  204  by multiplier  230  otherwise. In certain embodiments, a different number format is provided to each comparison circuit. 
     In one embodiment, multiplier  230  is turned off (e.g., via power control switch  232 ) when the first number  202  is a one value concurrently with the second number  204  being a one value, e.g., to conserve power for a multiplication that is not to be performed on first floating-point number  202  and second floating-point number  204 . 
       FIG. 2B  illustrates a circuit  200  in integer mode and comprising a “ones” detector circuit  201  coupled to a “ones” multiplier circuit  228  according to embodiments of the disclosure. In  FIG. 2B , a number format stores a value that indicates number format of the first input number  252  and/or second input number  254  (e.g., numbers  252  and  254  in the same storage as used in  FIG. 2A  for numbers  202  and  204 ). In one embodiment, the number format indicates to the comparison circuits  220 ,  222  how (e.g., exactly) one is represented in that particular number format  218 . 
     Depicted circuit  200  includes storage (e.g., flops) for a first integer number  252  and a second integer number  254 . Depicted format for first integer number  252  is a single field of bits (e.g., thirty-two bits or sixty-four bits, or more). Depicted format for second integer number  254  is a single field of bits (e.g., thirty-two bits or sixty-four bits, or more). 
     In certain embodiments, number format  218  indicates to comparison circuit  220  that an integer value of one includes a one value in the least significant bit preceded by zero values (e.g., 00000001 for an eight bit integer width) of the first number  252  and/or indicates to comparison circuit  222  that an integer value of one includes a one value in the least significant bit preceded by zero values (e.g., 00000001 for an eight bit integer width) of the second number  254 . In certain embodiments, number format controls the circuit  200  (e.g., comparison circuits  220 ,  224 ) to switch it between different number formats, e.g., for floating-point numbers as shown in  FIG. 2A  and for integer numbers as shown in  FIG. 2B . 
     In certain embodiments, in response to a request caused by a decoded instruction, (i) comparison circuit  220  is to compare the value of one as specified by the number format  218  for the first number  252 , for example, and output a first value (e.g., zero) when the first number  252  is a one value and a second, different value (e.g., one) when the first value  202  is not a one value, and (ii) comparison circuit  222  is to compare the value of one as specified by the number format  218  for the second number  254 , for example, and output a first value (e.g., zero) when the second number  254  is a one value and a second, different value (e.g., one) when the second number  254  is not a one value. In  FIG. 2B , the output from each of comparison circuit  220  and comparison circuit  220  are input to logic gate  224  (e.g., such that an OR logic gate  224  asserts on its output  226  a one when either or both of the inputs are one, or an AND logic gate  224  asserts on its output  226  a one only when both of the inputs are one). For example, with OR logic gate  224  asserting a value (e.g., one) when the first number  252  is a one value or when the second number  254  is a one value. As another example, with AND logic gate  224  asserting a value (e.g., one) when the first number  252  is a one value concurrently with the second number  254  being a one value. 
     In one of such embodiments, output  226  from OR logic gate  224  to “ones” detector circuit  201  is input into “ones” multiplier circuit  228  such that (i) the first number  252  or second number  254  that is not a one value is output from bypass output  234  and provided as output  236  when the first number  252  is a one value or when the second number  254  is a one value, respectively, and (ii) the product output from multiplication of first number  252  and second number  254  by multiplier  230  is provided as output  236  when both the first number  252  is not a one value and the second number  254  is not a one value (e.g., and an exact one from bypass output storage  234  (e.g., constant of one) is provided as output  236  when the first number  252  is a one value concurrently with the second number  254  being a one value). In certain embodiments, a different number format is provided to each comparison circuit. 
     In one embodiment, multiplier  230  is turned off (e.g., via power control switch  232 ) when the first number  252  is a one value or when the second number  254  is a one value, e.g., to conserve power for a multiplication that is not to be performed on first number  252  and second number  254 . 
     In another of such embodiments, output  226  from AND logic gate  224  to “ones” detector circuit  201  is input into “ones” multiplier circuit  228  such that (i) an exact one from bypass output storage  234  (e.g., constant of one) is provided as output  236  when the first number  252  is a one value concurrently with the second number  254  being a one value and (ii) the product output from multiplication of first number  252  and second number  254  by multiplier  230  otherwise. In certain embodiments, a different number format is provided to each comparison circuit. 
     In one embodiment, multiplier  230  is turned off (e.g., via power control switch  232 ) when the first number  252  is a one value concurrently with the second number  254  being a one value, e.g., to conserve power for a multiplication that is not to be performed on first integer number  252  and second integer number  254 . 
     In  FIG. 1 , matrix operations circuitry  112  includes one or more multiplier circuits  112 A, scalar circuitry  114  includes one or more multiplier circuits  114 A, and vector/SIMD circuitry  116  includes one or more multiplier circuits  116 A. In certain embodiments, one or more of any of multiplier circuit(s)  112 A, multiplier circuit(s)  114 A, or multiplier circuit(s)  116 A is an instance of multiplier circuit  228  from  FIGS. 2A-2B , for example, with the respective matrix operations circuitry  112 , scalar circuitry  114 , and vector/SIMD circuitry  116  including an instance of “ones” detector circuit  201  from  FIGS. 2A-2B . 
       FIG. 3  illustrates matrix operations circuitry  300  including a “ones” mode  350  according to embodiments of the disclosure. Depicted matrix operations circuitry  300  includes a plurality of fused multiply accumulate circuits (FMAs)  302  that are coupled together such that outputs from certain FMAs are passed as inputs to other FMAs in certain embodiments. 
     As one example, the number of rows in the matrix (tile A  304 ) matches the number of serial (chained) fused multiply accumulate circuits (FMAs) comprising the computation&#39;s latency in certain embodiments. In certain embodiments, each multiplier circuit is an instance of “ones” multiplier circuit”  228  from  FIGS. 2A-2B , for example, with “ones” detector circuit  201  also included. Optionally, the mode selection  350  may include storage for the “ones” number format. 
     An implementation is free to recirculate on a grid of smaller height, but the computation remains the same. In one embodiment, the source/destination vector comes from a tile of N rows (tile C  306 ) and the grid of FMAs  302  performs N vector-matrix operations resulting in a complete instruction performing a matrix multiplication of tiles, e.g., and tile B  308  is the other vector source and supplies “broadcast” terms to the FMAs in each stage. 
     In operation, in some embodiments, the elements of matrix B (stored in a tile B  603 ) are spread across the rectangular grid of FMAs. Matrix B (stored in tile A  601 ) has its elements of a row transformed to match up with the columnar dimension of the rectangular grid of FMAs. At each FMA in the grid, an element of A and B are multiplied and added to the incoming summand (e.g., from a FMA above) and the outgoing sum is passed to the next row of FMAs (or the final output). 
     By including a “ones” mode  350 , matrix operations circuitry  300  is controllable to either allow a “ones” mode to be utilized or to not. In certain embodiments, number format  352  defines when a value is a “one”. In one embodiment, when matrix operations circuitry  300  is in “ones” mode, a resultant of a requested multiplication of a plurality of inputs values that are each one is output as exactly one, and otherwise the resultant is the actual resultant of the multiplication (e.g., the resultant as will fit into the provided storage for the resultant). In certain embodiments, a particular multiplier that was to be used for a respective multiplication operation is instead off (e.g., is turned off or not turned on) for a set of inputs values that are each one, and thus saves power. In certain embodiments, when matrix operations circuitry  300  is not in “ones” mode, a resultant of a requested multiplication of a plurality of inputs values is only the actual resultant of the multiplication (e.g., the resultant as will fit into the provided storage for the resultant). 
       FIG. 4  illustrates circuitry  400  including a plurality of parallel “ones” multiplier circuits  406 ,  408 ,  410 ,  412  coupled to an adder circuit  414  according to embodiments of the disclosure. As depicted, a first packed data (e.g., vector) source  402  A 3 -A 0  and a second packed data (e.g., vector) source  404  B 3 -B 0  each have four packed data elements. It should be understood that a single element or any plurality of elements may be present in circuitry  400 . In one embodiment, each of these elements is a floating-point number. Packed data elements may be processed in parallel. 
     Each multiplier circuit  406 ,  408 ,  410 ,  412  may be an instance of “ones” multiplier circuit  228  in  FIGS. 2A-2B . Each multiplier circuit may include a “ones” detector circuit  201  in  FIGS. 2A-2B . In certain embodiments, number format  452  defines when a value is a “one”, for example, where number format  452  is set by execution of an instruction as disclosed herein. 
     As depicted, first “ones” multiplier circuit  406  takes as inputs (i) element A 3  from first packed data source  402  and (ii) element B 3  from second packed data source  404 . As depicted, second “ones” multiplier circuit  408  takes as inputs (i) element A 2  from first packed data source  402  and (ii) element B 2  from second packed data source  404 . As depicted, third “ones” multiplier circuit  408  takes as inputs (i) element A 1  from first packed data source  402  and (ii) element B 1  from second packed data source  404 . As depicted, fourth “ones” multiplier circuit  412  takes as inputs (i) element A 0  from first packed data source  402  and (ii) element B 0  from second packed data source  404 . 
     When circuitry  400  is in “ones” mode (e.g., as set in storage  450  by execution of an instruction as disclosed herein), a resultant of a requested multiplication on a pair of inputs values that are both not ones is the actual resultant of the multiplication (e.g., the resultant as will fit into the provided storage for the resultant), the resultant is a first input value of the pair when the second input value of the pair is one, and the resultant is the second input value of the pair when the first input value of the pair is one (e.g., and the resultant is an output of an (e.g., exact) one when the first input value of the pair and the second input value of the pair are both ones). 
     In certain embodiments, a particular multiplier that was to be used for a respective multiplication operation is instead off (e.g., is turned off or not turned on) for a set of inputs values that are either a one, and thus saves power. In certain embodiments, when circuitry  400  is not in “ones” mode, a resultant of a requested multiplication of a pair of inputs values is only the actual resultant of the multiplication (e.g., the resultant as will fit into the provided storage for the resultant). 
     In one embodiment, setting “ones” mode in storage  450  causes all (e.g., or a proper subset of all) multiplier circuits  406 ,  408 ,  410 ,  412  to be in “ones” mode. As discussed herein, multiplier circuits  406 ,  408 ,  410 ,  412  may (e.g., each) include an instance of “ones” detector circuit  201  in  FIGS. 2A-2B . 
     As one example, when each multiplier circuit  406 ,  408 ,  410 ,  412  is in “ones” mode: multiplier circuit  406  is to output one of A 3  or B 3  when the other of A 3  or B 3  is a one (e.g., as determined by an instance of “ones” detector circuit  201  in  FIGS. 2A-2B  coupled between multiplier circuit  406  and its inputs from first packed data source  402  and second packed data source  404 ), and output the actual resultant of the multiplication of A 3  and B 3  when both A 3  and B 3  are not “ones” (e.g., and output an exact one when A 3  and B 3  are both a “one” value); multiplier circuit  408  is to output one of A 2  or B 2  when the other of A 2  or B 2  is a one (e.g., as determined by an instance of “ones” detector circuit  201  in  FIGS. 2A-2B  coupled between multiplier circuit  406  and its inputs from first packed data source  402  and second packed data source  404 ), and output the actual resultant of the multiplication of A 2  and B 2  when both A 2  and B 2  are not a “one” value (e.g., and output an exact one when A 2  and B 2  are both “ones”); multiplier circuit  410  is to output one of A 1  or B 1  when the other of A 1  or B 1  is a one (e.g., as determined by an instance of “ones” detector circuit  201  in  FIGS. 2A-2B  coupled between multiplier circuit  406  and its inputs from first packed data source  402  and second packed data source  404 ), and output the actual resultant of the multiplication of A 1  and B 1  when both A 1  and B 1  are not “ones” (e.g., and output an exact one when A 1  and B 1  are both a “one” value); and multiplier circuit  412  is to output one of A 0  or B 0  when the other of A 0  or B 0  is a one (e.g., as determined by an instance of “ones” detector circuit  201  in  FIGS. 2A-2B  coupled between multiplier circuit  406  and its inputs from first packed data source  402  and second packed data source  404 ), and output the actual resultant of the multiplication of A 0  and B 0  when both A 0  and B 0  are not “ones” (e.g., and output an exact one when A 0  and B 0  are both a “one” value). 
     In the depicted embodiment, the outputs of multiplier circuits  406 ,  408 ,  410 ,  412  are added together into a single (e.g., floating-point) number by adder circuit  414 , and that single number is added to an initial value (or intermediate result)  416  by adder circuit  418  to produce result  420 . In one embodiment, multiple iterations of multiplications are performed by multiplier circuits  406 ,  408 ,  410 ,  412  with the intermediate results from adder circuit  414  stored (e.g., accumulated) into intermediate result  416  storage, and added to the next result from adder circuit  414 . 
       FIG. 5  illustrates circuitry  500  including a plurality of parallel “ones” multiplier circuits  506 ,  508 ,  510 ,  512  according to embodiments of the disclosure. As depicted, a first packed data (e.g., vector) source  502  A 3 -A 0  and a second packed data (e.g., vector) source  504  B 3 -B 0  each have four packed data elements. It should be understood that a single element or any plurality of elements may be present in circuitry  500 . In one embodiment, each of these elements is a floating-point number. Packed data elements may be processed in parallel. 
     Each multiplier circuit  506 ,  508 ,  510 ,  512  may be an instance of “ones” multiplier circuit  228  in  FIGS. 2A-2B . Each multiplier circuit may include a “ones” detector circuit  201  in  FIGS. 2A-2B . In certain embodiments, number format  552  defines when a value is a “one”, for example, where number format  452  is set by execution of an instruction as disclosed herein. 
     As depicted, first “ones” multiplier circuit  506  takes as inputs (i) element A 3  from first packed data source  502  and (ii) element B 3  from second packed data source  504 . As depicted, second “ones” multiplier circuit  508  takes as inputs (i) element A 2  from first packed data source  502  and (ii) element B 2  from second packed data source  504 . As depicted, third “ones” multiplier circuit  508  takes as inputs (i) element A 1  from first packed data source  502  and (ii) element B 1  from second packed data source  504 . As depicted, fourth “ones” multiplier circuit  512  takes as inputs (i) element A 0  from first packed data source  502  and (ii) element B 0  from second packed data source  504 . 
     When circuitry  500  is in “ones” mode (e.g., as set in storage  550  by execution of an instruction as disclosed herein), a resultant of a requested multiplication on a pair of inputs values that are both not ones is the actual resultant of the multiplication (e.g., the resultant as will fit into the provided storage for the resultant), the resultant is a first input value of the pair when the second input value of the pair is one, and the resultant is the second input value of the pair when the first input value of the pair is one (e.g., and the resultant is an output of an exact one when the first input value of the pair and the second input value of the pair are both ones). 
     In certain embodiments, a particular multiplier that was to be used for a respective multiplication operation is instead off (e.g., is turned off or not turned on) for a set of inputs values that are either a one, and thus saves power. In certain embodiments, when circuitry  500  is not in “ones” mode, a resultant of a requested multiplication of a pair of inputs values is only the actual resultant of the multiplication (e.g., the resultant as will fit into the provided storage for the resultant). 
     In one embodiment, setting “ones” mode in storage  550  causes all (e.g., or a proper subset of all) multiplier circuits  506 ,  508 ,  510 ,  512  to be in “ones” mode. As discussed herein, multiplier circuits  506 ,  508 ,  510 ,  512  may (e.g., each) include an instance of “ones” detector circuit  201  in  FIGS. 2A-2B . As one example, when each multiplier circuit  506 ,  508 ,  510 ,  512  is in “ones” mode: multiplier circuit  506  is to output one of A 3  or B 3  when the other of A 3  or B 3  is a one (e.g., as determined by an instance of “ones” detector circuit  201  in  FIGS. 2A-2B  coupled between multiplier circuit  506  and its inputs from first packed data source  502  and second packed data source  504 ), and output the actual resultant of the multiplication of A 3  and B 3  when both A 3  and B 3  are not “ones” (e.g., and output an exact one when A 3  and B 3  are both “ones”); multiplier circuit  508  is to output one of A 2  or B 2  when the other of A 2  or B 2  is a one (e.g., as determined by an instance of “ones” detector circuit  201  in  FIGS. 2A-2B  coupled between multiplier circuit  506  and its inputs from first packed data source  502  and second packed data source  504 ), and output the actual resultant of the multiplication of A 2  and B 2  when both A 2  and B 2  are not “ones” (e.g., and output an exact one when A 2  and B 2  are both “ones”); multiplier circuit  510  is to output one of A 1  or B 1  when the other of A 1  or B 1  is a one (e.g., as determined by an instance of “ones” detector circuit  201  in  FIGS. 2A-2B  coupled between multiplier circuit  506  and its inputs from first packed data source  502  and second packed data source  504 ), and output the actual resultant of the multiplication of A 1  and B 1  when both A 1  and B 1  are not “ones” (e.g., and output an exact one when A 1  and B 1  are both “ones”); and multiplier circuit  512  is to output one of A 0  or B 0  when the other of A 0  or B 0  is a one (e.g., as determined by an instance of “ones” detector circuit  201  in  FIGS. 2A-2B  coupled between multiplier circuit  506  and its inputs from first packed data source  502  and second packed data source  504 ), and output the actual resultant of the multiplication of A 0  and B 0  when both A 0  and B 0  are not “ones” (e.g., and output an exact one when A 0  and B 0  are both “ones”). 
     In the depicted embodiment, the outputs of multiplier circuits  506 ,  508 ,  510 ,  512  are output together as a single (e.g., floating-point) packed data result  514 . 
       FIG. 6  illustrates a hardware processor  600 , coupled to storage  602  that includes one or more “ones” multiplication instructions  604 , having a “ones” detector circuit  614  coupled to an execution circuit  616  according to embodiments of the disclosure. In certain embodiments, a “ones” multiplication instruction is according to any of the disclosure herein. In one embodiment, the “ones” multiplication instruction  604  includes a number format field  606  to indicate the number format as discussed herein. 
     In one embodiment, e.g., in response to a request to perform an operation, the instruction (e.g., macro-instruction) is fetched from storage  602  and sent to decoder  608 . In the depicted embodiment, the decoder  608  (e.g., decoder circuit) decodes the instruction into a decoded instruction (e.g., one or more micro-instructions or micro-operations). The decoded instruction is then sent for execution, e.g., via scheduler circuit  610  to schedule the decoded instruction for execution. 
     In certain embodiments, (e.g., where the processor/core supports out-of-order (OoO) execution), the processor includes a register rename/allocator circuit  610  coupled to register file/memory circuit  612  (e.g., unit) to allocate resources and perform register renaming on registers (e.g., registers associated with the initial sources and final destination of the instruction). In certain embodiments, (e.g., for out-of-order execution), the processor includes one or more scheduler circuits  610  coupled to the decoder  608 . The scheduler circuit(s) may schedule one or more operations associated with decoded instructions, including one or more operations decoded from a “ones” multiplication instruction  604 , e.g., for execution on the execution circuit  616 . In the depicted embodiment, “ones” detector circuit  614  is separate from the execution circuit, for example, where the “ones” detector circuit is in a front end (e.g., front end unit  1230  in  FIG. 12B ) of a core or is between a register read/memory read stage (e.g., stage  1214  in  FIG. 12A ) and an execution stage (e.g., stage  1216  in  FIG. 12A ), e.g., after retrieving the operands but before execution on the operands). In certain embodiments, “ones” detector circuit  614  is an instance of “ones” detector circuit  201  in  FIGS. 2A-2B . 
     As one example, a decoded “ones” multiplication instruction  604  is to cause a first input operand and a second input operand (e.g., a respective pair of input operands from packed data sources) to each be compared to a value of one (e.g., as indicated by number format  606 ) by “ones” detector circuit  614 , and is to cause (i) a resultant of a requested multiplication on a pair of inputs values is output as a single value of the pair of input values that is not a one (e.g., via sending the single value that is not a one via bypass  622 ), and (ii) otherwise the resultant is the actual resultant of the multiplication by multiplier circuit  618  (e.g., the resultant as will fit into the provided storage for the resultant). In certain embodiments, a particular multiplier circuit  618  that was to be used for a multiplication operation is off (e.g., is turned off or not turned on) for a set of inputs values that includes at least one (e.g., only one) value that is a “one”, and thus saves power. In another embodiment, instead of turning off an execution circuit  616  (e.g., multiplier circuit  618 ) that is determined not to be used for the multiplication including one or more “one” input values, it is instead used for a calculation for a different operation. 
     As another example, a decoded “ones” multiplication instruction  604  is to cause a first input operand and a second input operand (e.g., a respective pair of input operands from packed data sources) to each be compared to a value of one (e.g., as indicated by number format  606 ) by “ones” detector circuit  614 , and is to cause (i) a resultant of a requested multiplication on a pair of inputs values that are each ones is output as exactly one (e.g., via sending a value of exactly one via bypass  622 ), and (ii) otherwise the resultant is the actual resultant of the multiplication by multiplier circuit  618  (e.g., the resultant as will fit into the provided storage for the resultant). In certain embodiments, a particular multiplier circuit  618  that was to be used for a multiplication operation is off (e.g., is turned off or not turned on) for a set of inputs values that are each ones, and thus saves power. In another embodiment, instead of turning off an execution circuit  616  (e.g., multiplier circuit  618 ) that is determined not to be used for the ones input values, it is instead used for a calculation for a different operation. 
     Each multiplier circuit  618  may be an instance of “ones” multiplier circuit  228  in  FIGS. 2A-2B . In certain embodiments, number format  606  defines when a value is one, for example, where number format  606  is set by the instruction  604 . 
     In certain embodiments, a write back circuit  620  is included to write back results of an instruction to a destination (e.g., write them to a register(s) and/or memory), for example, so those results are visible within a processor (e.g., visible outside of the execution circuit that produced those results). In one embodiment, the actual resultant is determined (e.g., by execution unit  616 ) during the execution of instruction  604 , but that resultant is replaced with a value of exactly one (e.g., for the width of the resultant) after execution (e.g., after the execute stage), for example, in write back circuit  620  (e.g., in the write back stage). 
     One or more of these components (e.g., decoder  608 , register rename/register allocator/scheduler  610 , execution circuit  616 , registers (e.g., register file)/memory  612 , or write back circuit  620 ) may be in a single core of a hardware processor (e.g., and multiple cores each with an instance of these components). 
       FIG. 7  illustrates a hardware processor  700 , coupled to storage that includes one or more “ones” multiplication instructions  704 , having a “ones” detector circuit  716  of an execution circuit  714  according to embodiments of the disclosure. In certain embodiments, a “ones” multiplication instruction is according to any of the disclosure herein. In one embodiment, the “ones” multiplication instruction  704  includes a number format field  706  to indicate the number format as discussed herein. 
     In one embodiment, e.g., in response to a request to perform an operation, the instruction (e.g., macro-instruction) is fetched from storage  702  and sent to decoder  708 . In the depicted embodiment, the decoder  708  (e.g., decoder circuit) decodes the instruction into a decoded instruction (e.g., one or more micro-instructions or micro-operations). The decoded instruction is then sent for execution, e.g., via scheduler circuit  710  to schedule the decoded instruction for execution. 
     In certain embodiments, (e.g., where the processor/core supports out-of-order (OoO) execution), the processor includes a register rename/allocator circuit  710  coupled to register file/memory circuit  712  (e.g., unit) to allocate resources and perform register renaming on registers (e.g., registers associated with the initial sources and final destination of the instruction). In certain embodiments, (e.g., for out-of-order execution), the processor includes one or more scheduler circuits  710  coupled to the decoder  708 . The scheduler circuit(s) may schedule one or more operations associated with decoded instructions, including one or more operations decoded from a “ones” multiplication instruction  704 , e.g., for execution on the execution circuit  714 . In the depicted embodiment, “ones” detector circuit  716  is within the execution circuit  714 , for example, in execution clusters  1260  in  FIG. 12B . In certain embodiments, “ones” detector circuit  716  is an instance of “ones” detector circuit  201  in  FIGS. 2A-2B . 
     As one example, a decoded “ones” multiplication instruction  704  is to cause a first input operand and a second input operand (e.g., a respective pair of input operands from packed data sources) to each be compared to a “ones” value (e.g., as indicated by number format  706 ) by “ones” detector circuit  716  of execution circuit  714 , and is to cause (i) a resultant of a requested multiplication on a pair of inputs values is output as a single value of the pair of input values that is not “ones” (e.g., via sending the single value that is not “ones” as an output without being input into multiplier circuit  718 ), and (ii) otherwise the resultant is the actual resultant of the multiplication by multiplier circuit  718  (e.g., the resultant as will fit into the provided storage for the resultant). In certain embodiments, a particular multiplier circuit  718  that was to be used for a multiplication operation is off (e.g., is turned off or not turned on) for a set of inputs values that includes at least one (e.g., only one) value that is “ones”, and thus saves power. In another embodiment, instead of turning off an execution circuit multiplier circuit  718  that is determined not to be used for the multiplication including at least one “ones” input value, it is instead used for a calculation for a different operation. 
     As another example, a decoded “ones” multiplication instruction  704  is to cause a first input operand and a second input operand (e.g., a respective pair of input operands from packed data sources) to each be compared to a “ones” value (e.g., as indicated by number format  706 ) by “ones” detector circuit  716 , and is to cause (i) a resultant of a requested multiplication on a pair of inputs values that are each ones is output as exactly one (e.g., via sending a value of exactly one via bypass  722 ), and (ii) otherwise the resultant is the actual resultant of the multiplication by multiplier circuit  718  (e.g., the resultant as will fit into the provided storage for the resultant). In certain embodiments, a particular multiplier circuit  718  that was to be used for a multiplication operation is off (e.g., is turned off or not turned on) for a set of inputs values that are each “ones”, and thus saves power. In another embodiment, instead of turning off the multiplier circuit  718  that is determined not to be used for the “ones” input values, it is instead used for a calculation for a different operation. 
     Each multiplier circuit  718  may be an instance of “ones” multiplier circuit  228  in  FIGS. 2A-2B . In certain embodiments, number format  706  defines when a value is a one, for example, where number format  706  is set by the instruction  704 . 
     In certain embodiments, a write back circuit  720  is included to write back results of an instruction to a destination (e.g., write them to a register(s) and/or memory), for example, so those results are visible within a processor (e.g., visible outside of the execution circuit that produced those results). In one embodiment, the actual resultant is determined (e.g., by multiplier circuit  718 ) during the execution of instruction  704 , but that resultant is replaced with a value of exactly one (e.g., for the width of the resultant) after execution (e.g., after the execute stage), for example, in write back circuit  720  (e.g., in the write back stage). 
     One or more of these components (e.g., decoder  708 , register rename/register allocator/scheduler  710 , execution circuit  714 , registers (e.g., register file)/memory  712 , or write back circuit  720 ) may be in a single core of a hardware processor (e.g., and multiple cores each with an instance of these components). 
     In certain embodiments, a “ones” multiplication instruction has no prior knowledge or indication that any of its input values are one. 
       FIG. 8  illustrates a method of processing a “ones” multiplication instruction according to embodiments of the disclosure. A processor (e.g., or processor core) may perform method  800 , e.g., in response to receiving a request to execute an instruction from software. Depicted method  800  includes processing a “ones” multiplication instruction by: fetch an instruction having a first field that identifies a first number, a second field that identifies a second number, and a third field that indicates a number format for the first number and the second number  802 , decode the instruction into a decoded instruction  804 , retrieve data associated with the first field, the second field, and the third field  806 , (optionally) schedule the decoded instruction for execution  808 , execute the decoded instruction to cause a first comparison of the first number to a one value in the number format of the first number, cause a second comparison of the second number to a one value in the number format of the second number, provide as a resultant of the single instruction the first number when the second comparison indicates the second number equals the one value in the number format of the second number, provide as the resultant of the single instruction the second number when the first comparison indicates the first number equals the one value in the number format of the first number, and provide as the resultant of the single instruction a product of a multiplication of the first number and the second number when the first comparison indicates the first number does not equal the one value in the number format of the first number and the second comparison indicates the second number does not equal the one value in the number format of the second number  810 , and commit a result of the executed instruction  812 . 
     In one embodiment, the instruction is a packed data (e.g., vector) instruction wherein the first field identifies a first vector of numbers, the second field identifies a second vector of numbers, and the execution circuit executes the decoded single instruction to: cause a plurality of first comparisons of each number of the first vector of numbers to a one value in the number format of the first vector of numbers, cause a plurality of second comparisons of each number of the second vector of numbers to a one value in the number format of the second vector of numbers, provide as a resultant of the single instruction a first number of the first vector of numbers for each of the plurality of second comparisons that indicates a corresponding second number of the second vector of numbers equals the one value in the number format of the second vector of numbers, provide as the resultant of the single instruction a second number of the second vector of numbers for each of the plurality of first comparisons that indicates a corresponding first number of the first vector of numbers equals the one value in the number format of the first vector of numbers, and provide as the resultant of the single instruction a product of a multiplication of a first number of the first vector of numbers and a corresponding second number of the second vector of numbers when a first comparison indicates the first number does not equal the one value in the number format of the first number and a corresponding second comparison indicates the second number does not equal the one value in the number format of the second number. 
     In the Figures herein, e.g.,  FIGS. 2-8 , data may be loaded from a register/memory and or stored in a register or memory (e.g., only at the end of execution of the instruction). In certain embodiments, the data sources (inputs) and the data destination (output) each have the same number of bits (e.g., and/or elements for packed data sources/destination). In certain embodiments, some or all of the data may be accessed in (e.g., system) memory. The input and output vector values and sizes herein are also examples, and other values and sizes may be utilized. The data may be according to big-endian or little-endian order. 
     Exemplary architectures, systems, etc. that the above may be used in are detailed below. 
     At least some embodiments of the disclosed technologies can be described in view of the following examples:
     Example 1. A hardware processor comprising:   a decoder to decode a single instruction into a decoded single instruction, the single instruction having a first field that identifies a first number, a second field that identifies a second number, and a third field that indicates a number format for the first number and the second number; and   an execution circuit to execute the decoded single instruction to:
       cause a first comparison of the first number to a one value in the number format of the first number,   cause a second comparison of the second number to a one value in the number format of the second number,   provide as a resultant of the single instruction the first number when the second comparison indicates the second number equals the one value in the number format of the second number,   provide as the resultant of the single instruction the second number when the first comparison indicates the first number equals the one value in the number format of the first number, and   provide as the resultant of the single instruction a product of a multiplication of the first number and the second number when the first comparison indicates the first number does not equal the one value in the number format of the first number and the second comparison indicates the second number does not equal the one value in the number format of the second number.   
       Example 2. The hardware processor of example 1, wherein the execution circuit does not perform the multiplication of the first number and the second number when the first comparison indicates the first number equals the one value in the number format of the first number or the second comparison indicates the second number equals the one value in the number format of the second number.   Example 3. The hardware processor of example 2, wherein a multiplier to perform the multiplication is powered off in response to the first comparison indicating the first number equals the one value in the number format of the first number or the second comparison indicating the second number equals the one value in the number format of the second number.   Example 4. The hardware processor of example 1, wherein the number format is provided as an immediate of the single instruction.   Example 5. The hardware processor of example 1, wherein the number format is indicated by an opcode of the single instruction.   Example 6. The hardware processor of example 1, wherein the first field identifies a first vector of numbers, the second field identifies a second vector of numbers, and the execution circuit executes the decoded single instruction to:
       cause a plurality of first comparisons of each number of the first vector of numbers to a one value in the number format of the first vector of numbers,   cause a plurality of second comparisons of each number of the second vector of numbers to a one value in the number format of the second vector of numbers,   provide as a resultant of the single instruction a first number of the first vector of numbers for each of the plurality of second comparisons that indicates a corresponding second number of the second vector of numbers equals the one value in the number format of the second vector of numbers,   provide as the resultant of the single instruction a second number of the second vector of numbers for each of the plurality of first comparisons that indicates a corresponding first number of the first vector of numbers equals the one value in the number format of the first vector of numbers, and   provide as the resultant of the single instruction a product of a multiplication of a first number of the first vector of numbers and a corresponding second number of the second vector of numbers when a first comparison indicates the first number does not equal the one value in the number format of the first number and a corresponding second comparison indicates the second number does not equal the one value in the number format of the second number.   
       Example 7. The hardware processor of example 1, wherein when the number format is a floating-point number format for the first value and the second value, the first comparison compares a zero value to a sign bit of the first number, a leading zero followed by ones value to an exponent field of the first number, and a zero value to a fraction field of the first number, and the second comparison compares the zero value to a sign bit of the second number, the leading zero followed by ones value to an exponent field of the second number, and the zero value to a fraction field of the second number.   Example 8. The hardware processor of example 1, wherein the first comparison and the second comparison are performed separately from the execution circuit.   Example 9. A method comprising:   decoding a single instruction into a decoded single instruction with a decoder of a hardware processor, the single instruction having a first field that identifies a first number, a second field that identifies a second number, and a third field that indicates a number format for the first number and the second number; and   executing the decoded single instruction with an execution circuit of the hardware processor to:
       cause a first comparison of the first number to a one value in the number format of the first number,   cause a second comparison of the second number to a one value in the number format of the second number,   provide as a resultant of the single instruction the first number when the second comparison indicates the second number equals the one value in the number format of the second number,   provide as the resultant of the single instruction the second number when the first comparison indicates the first number equals the one value in the number format of the first number, and   provide as the resultant of the single instruction a product of a multiplication of the first number and the second number when the first comparison indicates the first number does not equal the one value in the number format of the first number and the second comparison indicates the second number does not equal the one value in the number format of the second number.   
       Example 10. The method of example 9, wherein the execution circuit does not perform the multiplication of the first number and the second number when the first comparison indicates the first number equals the one value in the number format of the first number or the second comparison indicates the second number equals the one value in the number format of the second number.   Example 11. The method of example 10, wherein a multiplier to perform the multiplication is powered off in response to the first comparison indicating the first number equals the one value in the number format of the first number or the second comparison indicating the second number equals the one value in the number format of the second number.   Example 12. The method of example 9, further comprising reading the number format from an immediate of the single instruction.   Example 13. The method of example 9, further comprising determining the number format from an opcode of the single instruction.   Example 14. The method of example 9, wherein the first field identifies a first vector of numbers, the second field identifies a second vector of numbers, and the execution circuit executes the decoded single instruction to:
       cause a plurality of first comparisons of each number of the first vector of numbers to a one value in the number format of the first vector of numbers,   cause a plurality of second comparisons of each number of the second vector of numbers to a one value in the number format of the second vector of numbers,   provide as a resultant of the single instruction a first number of the first vector of numbers for each of the plurality of second comparisons that indicates a corresponding second number of the second vector of numbers equals the one value in the number format of the second vector of numbers,   provide as the resultant of the single instruction a second number of the second vector of numbers for each of the plurality of first comparisons that indicates a corresponding first number of the first vector of numbers equals the one value in the number format of the first vector of numbers, and   provide as the resultant of the single instruction a product of a multiplication of a first number of the first vector of numbers and a corresponding second number of the second vector of numbers when a first comparison indicates the first number does not equal the one value in the number format of the first number and a corresponding second comparison indicates the second number does not equal the one value in the number format of the second number.   
       Example 15. The method of example 9, wherein when the number format is a floating-point number format for the first value and the second value, the first comparison compares a zero value to a sign bit of the first number, a leading zero followed by ones value to an exponent field of the first number, and a zero value to a fraction field of the first number, and the second comparison compares the zero value to a sign bit of the second number, the leading zero followed by ones value to an exponent field of the second number, and the zero value to a fraction field of the second number.   Example 16. The method of example 9, wherein the first comparison and the second comparison are performed separately from the execution circuit.   Example 17. A non-transitory machine readable medium that stores code that when executed by a machine causes the machine to perform a method comprising:   decoding a single instruction into a decoded single instruction with a decoder of a hardware processor, the single instruction having a first field that identifies a first number, a second field that identifies a second number, and a third field that indicates a number format for the first number and the second number; and   executing the decoded single instruction with an execution circuit of the hardware processor to:
       cause a first comparison of the first number to a one value in the number format of the first number,   cause a second comparison of the second number to a one value in the number format of the second number,   provide as a resultant of the single instruction the first number when the second comparison indicates the second number equals the one value in the number format of the second number,   provide as the resultant of the single instruction the second number when the first comparison indicates the first number equals the one value in the number format of the first number, and   provide as the resultant of the single instruction a product of a multiplication of the first number and the second number when the first comparison indicates the first number does not equal the one value in the number format of the first number and the second comparison indicates the second number does not equal the one value in the number format of the second number.   
       Example 18. The non-transitory machine readable medium of example 17, wherein the execution circuit does not perform the multiplication of the first number and the second number when the first comparison indicates the first number equals the one value in the number format of the first number or the second comparison indicates the second number equals the one value in the number format of the second number.   Example 19. The non-transitory machine readable medium of example 18, wherein a multiplier to perform the multiplication is powered off in response to the first comparison indicating the first number equals the one value in the number format of the first number or the second comparison indicating the second number equals the one value in the number format of the second number.   Example 20. The non-transitory machine readable medium of example 17, further comprising reading the number format from an immediate of the single instruction.   Example 21. The non-transitory machine readable medium of example 17, further comprising determining the number format from an opcode of the single instruction.   Example 22. The non-transitory machine readable medium of example 17, wherein the first field identifies a first vector of numbers, the second field identifies a second vector of numbers, and the execution circuit executes the decoded single instruction to:
       cause a plurality of first comparisons of each number of the first vector of numbers to a one value in the number format of the first vector of numbers,   cause a plurality of second comparisons of each number of the second vector of numbers to a one value in the number format of the second vector of numbers,   provide as a resultant of the single instruction a first number of the first vector of numbers for each of the plurality of second comparisons that indicates a corresponding second number of the second vector of numbers equals the one value in the number format of the second vector of numbers,   provide as the resultant of the single instruction a second number of the second vector of numbers for each of the plurality of first comparisons that indicates a corresponding first number of the first vector of numbers equals the one value in the number format of the first vector of numbers, and   provide as the resultant of the single instruction a product of a multiplication of a first number of the first vector of numbers and a corresponding second number of the second vector of numbers when a first comparison indicates the first number does not equal the one value in the number format of the first number and a corresponding second comparison indicates the second number does not equal the one value in the number format of the second number.   
       Example 23. The non-transitory machine readable medium of example 22, wherein when the number format is a floating-point number format for the first value and the second value, the first comparison compares a zero value to a sign bit of the first number, a leading zero followed by ones value to an exponent field of the first number, and a zero value to a fraction field of the first number, and the second comparison compares the zero value to a sign bit of the second number, the leading zero followed by ones value to an exponent field of the second number, and the zero value to a fraction field of the second number.   Example 24. The non-transitory machine readable medium of example 17, wherein the first comparison and the second comparison are performed separately from the execution circuit.   

     In yet another embodiment, an apparatus comprises a data storage device that stores code that when executed by a hardware processor causes the hardware processor to perform any method disclosed herein. An apparatus may be as described in the detailed description. A method may be as described in the detailed description. 
     An instruction set may include one or more instruction formats. A given instruction format may define various fields (e.g., number of bits, location of bits) to specify, among other things, the operation to be performed (e.g., opcode) and the operand(s) on which that operation is to be performed and/or other data field(s) (e.g., mask). Some instruction formats are further broken down though the definition of instruction templates (or subformats). For example, the instruction templates of a given instruction format may be defined to have different subsets of the instruction format&#39;s fields (the included fields are typically in the same order, but at least some have different bit positions because there are less fields included) and/or defined to have a given field interpreted differently. Thus, each instruction of an ISA is expressed using a given instruction format (and, if defined, in a given one of the instruction templates of that instruction format) and includes fields for specifying the operation and the operands. For example, an exemplary ADD instruction has a specific opcode and an instruction format that includes an opcode field to specify that opcode and operand fields to select operands (source1/destination and source2); and an occurrence of this ADD instruction in an instruction stream will have specific contents in the operand fields that select specific operands. A set of SIMD extensions referred to as the Advanced Vector Extensions (AVX) (AVX1 and AVX2) and using the Vector Extensions (VEX) coding scheme has been released and/or published (e.g., see Intel® 64 and IA-32 Architectures Software Developer&#39;s Manual, November 2018; and see Intel® Architecture Instruction Set Extensions Programming Reference, October 2018). 
     Exemplary Instruction Formats 
     Embodiments of the instruction(s) described herein may be embodied in different formats. Additionally, exemplary systems, architectures, and pipelines are detailed below. Embodiments of the instruction(s) may be executed on such systems, architectures, and pipelines, but are not limited to those detailed. 
     Generic Vector Friendly Instruction Format 
     A vector friendly instruction format is an instruction format that is suited for vector instructions (e.g., there are certain fields specific to vector operations). While embodiments are described in which both vector and scalar operations are supported through the vector friendly instruction format, alternative embodiments use only vector operations the vector friendly instruction format. 
       FIGS. 9A-9B  are block diagrams illustrating a generic vector friendly instruction format and instruction templates thereof according to embodiments of the disclosure.  FIG. 9A  is a block diagram illustrating a generic vector friendly instruction format and class A instruction templates thereof according to embodiments of the disclosure; while  FIG. 9B  is a block diagram illustrating the generic vector friendly instruction format and class B instruction templates thereof according to embodiments of the disclosure. Specifically, a generic vector friendly instruction format  900  for which are defined class A and class B instruction templates, both of which include no memory access  905  instruction templates and memory access  920  instruction templates. The term generic in the context of the vector friendly instruction format refers to the instruction format not being tied to any specific instruction set. 
     While embodiments of the disclosure will be described in which the vector friendly instruction format supports the following: a 64 byte vector operand length (or size) with 32 bit (4 byte) or 64 bit (8 byte) data element widths (or sizes) (and thus, a 64 byte vector consists of either 16 doubleword-size elements or alternatively, 8 quadword-size elements); a 64 byte vector operand length (or size) with 16 bit (2 byte) or 8 bit (1 byte) data element widths (or sizes); a 32 byte vector operand length (or size) with 32 bit (4 byte), 64 bit (8 byte), 16 bit (2 byte), or 8 bit (1 byte) data element widths (or sizes); and a 16 byte vector operand length (or size) with 32 bit (4 byte), 64 bit (8 byte), 16 bit (2 byte), or 8 bit (1 byte) data element widths (or sizes); alternative embodiments may support more, less and/or different vector operand sizes (e.g., 256 byte vector operands) with more, less, or different data element widths (e.g., 128 bit (16 byte) data element widths). 
     The class A instruction templates in  FIG. 9A  include: 1) within the no memory access  905  instruction templates there is shown a no memory access, full round control type operation  910  instruction template and a no memory access, data transform type operation  915  instruction template; and 2) within the memory access  920  instruction templates there is shown a memory access, temporal  925  instruction template and a memory access, non-temporal  930  instruction template. The class B instruction templates in  FIG. 9B  include: 1) within the no memory access  905  instruction templates there is shown a no memory access, write mask control, partial round control type operation  912  instruction template and a no memory access, write mask control, vsize type operation  917  instruction template; and 2) within the memory access  920  instruction templates there is shown a memory access, write mask control  927  instruction template. 
     The generic vector friendly instruction format  900  includes the following fields listed below in the order illustrated in  FIGS. 9A-9B . 
     Format field  940 —a specific value (an instruction format identifier value) in this field uniquely identifies the vector friendly instruction format, and thus occurrences of instructions in the vector friendly instruction format in instruction streams. As such, this field is optional in the sense that it is not needed for an instruction set that has only the generic vector friendly instruction format. 
     Base operation field  942 —its content distinguishes different base operations. 
     Register index field  944 —its content, directly or through address generation, specifies the locations of the source and destination operands, be they in registers or in memory. These include a sufficient number of bits to select N registers from a PxQ (e.g. 32×512, 16×128, 32×1024, 64×1024) register file. While in one embodiment N may be up to three sources and one destination register, alternative embodiments may support more or less sources and destination registers (e.g., may support up to two sources where one of these sources also acts as the destination, may support up to three sources where one of these sources also acts as the destination, may support up to two sources and one destination). 
     Modifier field  946 —its content distinguishes occurrences of instructions in the generic vector instruction format that specify memory access from those that do not; that is, between no memory access  905  instruction templates and memory access  920  instruction templates. Memory access operations read and/or write to the memory hierarchy (in some cases specifying the source and/or destination addresses using values in registers), while non-memory access operations do not (e.g., the source and destinations are registers). While in one embodiment this field also selects between three different ways to perform memory address calculations, alternative embodiments may support more, less, or different ways to perform memory address calculations. 
     Augmentation operation field  950 —its content distinguishes which one of a variety of different operations to be performed in addition to the base operation. This field is context specific. In one embodiment of the disclosure, this field is divided into a class field  968 , an alpha field  952 , and a beta field  954 . The augmentation operation field  950  allows common groups of operations to be performed in a single instruction rather than 2, 3, or 4 instructions. 
     Scale field  960 —its content allows for the scaling of the index field&#39;s content for memory address generation (e.g., for address generation that uses 2 scale *index+base). 
     Displacement Field  962 A—its content is used as part of memory address generation (e.g., for address generation that uses 2 scale *index+base+displacement). 
     Displacement Factor Field  962 B (note that the juxtaposition of displacement field  962 A directly over displacement factor field  962 B indicates one or the other is used)—its content is used as part of address generation; it specifies a displacement factor that is to be scaled by the size of a memory access (N)—where N is the number of bytes in the memory access (e.g., for address generation that uses 2 scale *index+base+scaled displacement). Redundant low-order bits are ignored and hence, the displacement factor field&#39;s content is multiplied by the memory operands total size (N) in order to generate the final displacement to be used in calculating an effective address. The value of N is determined by the processor hardware at runtime based on the full opcode field  974  (described later herein) and the data manipulation field  954 C. The displacement field  962 A and the displacement factor field  962 B are optional in the sense that they are not used for the no memory access  905  instruction templates and/or different embodiments may implement only one or none of the two. 
     Data element width field  964 —its content distinguishes which one of a number of data element widths is to be used (in some embodiments for all instructions; in other embodiments for only some of the instructions). This field is optional in the sense that it is not needed if only one data element width is supported and/or data element widths are supported using some aspect of the opcodes. 
     Write mask field  970 —its content controls, on a per data element position basis, whether that data element position in the destination vector operand reflects the result of the base operation and augmentation operation. Class A instruction templates support merging-writemasking, while class B instruction templates support both merging- and zeroing-writemasking. When merging, vector masks allow any set of elements in the destination to be protected from updates during the execution of any operation (specified by the base operation and the augmentation operation); in other one embodiment, preserving the old value of each element of the destination where the corresponding mask bit has a 0. In contrast, when zeroing vector masks allow any set of elements in the destination to be zeroed during the execution of any operation (specified by the base operation and the augmentation operation); in one embodiment, an element of the destination is set to 0 when the corresponding mask bit has a 0 value. A subset of this functionality is the ability to control the vector length of the operation being performed (that is, the span of elements being modified, from the first to the last one); however, it is not necessary that the elements that are modified be consecutive. Thus, the write mask field  970  allows for partial vector operations, including loads, stores, arithmetic, logical, etc. While embodiments of the disclosure are described in which the write mask field&#39;s  970  content selects one of a number of write mask registers that contains the write mask to be used (and thus the write mask field&#39;s  970  content indirectly identifies that masking to be performed), alternative embodiments instead or additional allow the mask write field&#39;s  970  content to directly specify the masking to be performed. 
     Immediate field  972 —its content allows for the specification of an immediate. This field is optional in the sense that is it not present in an implementation of the generic vector friendly format that does not support immediate and it is not present in instructions that do not use an immediate. 
     Class field  968 —its content distinguishes between different classes of instructions. With reference to  FIGS. 9A-B , the contents of this field select between class A and class B instructions. In  FIGS. 9A-B , rounded corner squares are used to indicate a specific value is present in a field (e.g., class A  968 A and class B  968 B for the class field  968  respectively in  FIGS. 9A-B ). 
     Instruction Templates of Class A 
     In the case of the non-memory access  905  instruction templates of class A, the alpha field  952  is interpreted as an RS field  952 A, whose content distinguishes which one of the different augmentation operation types are to be performed (e.g., round  952 A. 1  and data transform  952 A. 2  are respectively specified for the no memory access, round type operation  910  and the no memory access, data transform type operation  915  instruction templates), while the beta field  954  distinguishes which of the operations of the specified type is to be performed. In the no memory access  905  instruction templates, the scale field  960 , the displacement field  962 A, and the displacement scale filed  962 B are not present. 
     No-Memory Access Instruction Templates—Full Round Control Type Operation 
     In the no memory access full round control type operation  910  instruction template, the beta field  954  is interpreted as a round control field  954 A, whose content(s) provide static rounding. While in the described embodiments of the disclosure the round control field  954 A includes a suppress all floating point exceptions (SAE) field  956  and a round operation control field  958 , alternative embodiments may support may encode both these concepts into the same field or only have one or the other of these concepts/fields (e.g., may have only the round operation control field  958 ). 
     SAE field  956 —its content distinguishes whether or not to disable the exception event reporting; when the SAE field&#39;s  956  content indicates suppression is enabled, a given instruction does not report any kind of floating-point exception flag and does not raise any floating point exception handler. 
     Round operation control field  958 —its content distinguishes which one of a group of rounding operations to perform (e.g., Round-up, Round-down, Round-towards-zero and Round-to-nearest). Thus, the round operation control field  958  allows for the changing of the rounding mode on a per instruction basis. In one embodiment of the disclosure where a processor includes a control register for specifying rounding modes, the round operation control field&#39;s  950  content overrides that register value. 
     No Memory Access Instruction Templates—Data Transform Type Operation 
     In the no memory access data transform type operation  915  instruction template, the beta field  954  is interpreted as a data transform field  954 B, whose content distinguishes which one of a number of data transforms is to be performed (e.g., no data transform, swizzle, broadcast). 
     In the case of a memory access  920  instruction template of class A, the alpha field  952  is interpreted as an eviction hint field  952 B, whose content distinguishes which one of the eviction hints is to be used (in  FIG. 9A , temporal  952 B. 1  and non-temporal  952 B. 2  are respectively specified for the memory access, temporal  925  instruction template and the memory access, non-temporal  930  instruction template), while the beta field  954  is interpreted as a data manipulation field  954 C, whose content distinguishes which one of a number of data manipulation operations (also known as primitives) is to be performed (e.g., no manipulation; broadcast; up conversion of a source; and down conversion of a destination). The memory access  920  instruction templates include the scale field  960 , and optionally the displacement field  962 A or the displacement scale field  962 B. 
     Vector memory instructions perform vector loads from and vector stores to memory, with conversion support. As with regular vector instructions, vector memory instructions transfer data from/to memory in a data element-wise fashion, with the elements that are actually transferred is dictated by the contents of the vector mask that is selected as the write mask. 
     Memory Access Instruction Templates—Temporal 
     Temporal data is data likely to be reused soon enough to benefit from caching. This is, however, a hint, and different processors may implement it in different ways, including ignoring the hint entirely. 
     Memory Access Instruction Templates—Non-Temporal 
     Non-temporal data is data unlikely to be reused soon enough to benefit from caching in the 1st-level cache and should be given priority for eviction. This is, however, a hint, and different processors may implement it in different ways, including ignoring the hint entirely. 
     Instruction Templates of Class B 
     In the case of the instruction templates of class B, the alpha field  952  is interpreted as a write mask control (Z) field  952 C, whose content distinguishes whether the write masking controlled by the write mask field  970  should be a merging or a zeroing. 
     In the case of the non-memory access  905  instruction templates of class B, part of the beta field  954  is interpreted as an RL field  957 A, whose content distinguishes which one of the different augmentation operation types are to be performed (e.g., round  957 A. 1  and vector length (VSIZE)  957 A. 2  are respectively specified for the no memory access, write mask control, partial round control type operation  912  instruction template and the no memory access, write mask control, VSIZE type operation  917  instruction template), while the rest of the beta field  954  distinguishes which of the operations of the specified type is to be performed. In the no memory access  905  instruction templates, the scale field  960 , the displacement field  962 A, and the displacement scale filed  962 B are not present. 
     In the no memory access, write mask control, partial round control type operation  910  instruction template, the rest of the beta field  954  is interpreted as a round operation field  959 A and exception event reporting is disabled (a given instruction does not report any kind of floating-point exception flag and does not raise any floating point exception handler). 
     Round operation control field  959 A—just as round operation control field  958 , its content distinguishes which one of a group of rounding operations to perform (e.g., Round-up, Round-down, Round-towards-zero and Round-to-nearest). Thus, the round operation control field  959 A allows for the changing of the rounding mode on a per instruction basis. In one embodiment of the disclosure where a processor includes a control register for specifying rounding modes, the round operation control field&#39;s  950  content overrides that register value. 
     In the no memory access, write mask control, VSIZE type operation  917  instruction template, the rest of the beta field  954  is interpreted as a vector length field  959 B, whose content distinguishes which one of a number of data vector lengths is to be performed on (e.g., 128, 256, or 512 byte). 
     In the case of a memory access  920  instruction template of class B, part of the beta field  954  is interpreted as a broadcast field  957 B, whose content distinguishes whether or not the broadcast type data manipulation operation is to be performed, while the rest of the beta field  954  is interpreted the vector length field  959 B. The memory access  920  instruction templates include the scale field  960 , and optionally the displacement field  962 A or the displacement scale field  962 B. 
     With regard to the generic vector friendly instruction format  900 , a full opcode field  974  is shown including the format field  940 , the base operation field  942 , and the data element width field  964 . While one embodiment is shown where the full opcode field  974  includes all of these fields, the full opcode field  974  includes less than all of these fields in embodiments that do not support all of them. The full opcode field  974  provides the operation code (opcode). 
     The augmentation operation field  950 , the data element width field  964 , and the write mask field  970  allow these features to be specified on a per instruction basis in the generic vector friendly instruction format. 
     The combination of write mask field and data element width field create typed instructions in that they allow the mask to be applied based on different data element widths. 
     The various instruction templates found within class A and class B are beneficial in different situations. In some embodiments of the disclosure, different processors or different cores within a processor may support only class A, only class B, or both classes. For instance, a high performance general purpose out-of-order core intended for general-purpose computing may support only class B, a core intended primarily for graphics and/or scientific (throughput) computing may support only class A, and a core intended for both may support both (of course, a core that has some mix of templates and instructions from both classes but not all templates and instructions from both classes is within the purview of the disclosure). Also, a single processor may include multiple cores, all of which support the same class or in which different cores support different class. For instance, in a processor with separate graphics and general purpose cores, one of the graphics cores intended primarily for graphics and/or scientific computing may support only class A, while one or more of the general purpose cores may be high performance general purpose cores with out of order execution and register renaming intended for general-purpose computing that support only class B. Another processor that does not have a separate graphics core, may include one more general purpose in-order or out-of-order cores that support both class A and class B. Of course, features from one class may also be implement in the other class in different embodiments of the disclosure. Programs written in a high level language would be put (e.g., just in time compiled or statically compiled) into an variety of different executable forms, including: 1) a form having only instructions of the class(es) supported by the target processor for execution; or 2) a form having alternative routines written using different combinations of the instructions of all classes and having control flow code that selects the routines to execute based on the instructions supported by the processor which is currently executing the code. 
     Exemplary Specific Vector Friendly Instruction Format 
       FIG. 10  is a block diagram illustrating an exemplary specific vector friendly instruction format according to embodiments of the disclosure.  FIG. 10  shows a specific vector friendly instruction format  1000  that is specific in the sense that it specifies the location, size, interpretation, and order of the fields, as well as values for some of those fields. The specific vector friendly instruction format  1000  may be used to extend the x86 instruction set, and thus some of the fields are similar or the same as those used in the existing x86 instruction set and extension thereof (e.g., AVX). This format remains consistent with the prefix encoding field, real opcode byte field, MOD R/M field, SIB field, displacement field, and immediate fields of the existing x86 instruction set with extensions. The fields from  FIG. 9  into which the fields from  FIG. 10  map are illustrated. 
     It should be understood that, although embodiments of the disclosure are described with reference to the specific vector friendly instruction format  1000  in the context of the generic vector friendly instruction format  900  for illustrative purposes, the disclosure is not limited to the specific vector friendly instruction format  1000  except where claimed. For example, the generic vector friendly instruction format  900  contemplates a variety of possible sizes for the various fields, while the specific vector friendly instruction format  1000  is shown as having fields of specific sizes. By way of specific example, while the data element width field  964  is illustrated as a one bit field in the specific vector friendly instruction format  1000 , the disclosure is not so limited (that is, the generic vector friendly instruction format  900  contemplates other sizes of the data element width field  964 ). 
     The generic vector friendly instruction format  900  includes the following fields listed below in the order illustrated in  FIG. 10A . 
     EVEX Prefix (Bytes 0-3)  1002 —is encoded in a four-byte form. 
     Format Field  940  (EVEX Byte 0, bits [ 7 : 0 ])—the first byte (EVEX Byte 0) is the format field  940  and it contains 0x62 (the unique value used for distinguishing the vector friendly instruction format in one embodiment of the disclosure). 
     The second-fourth bytes (EVEX Bytes 1-3) include a number of bit fields providing specific capability. 
     REX field  1005  (EVEX Byte 1, bits [ 7 - 5 ])—consists of a EVEX.R bit field (EVEX Byte 1, bit [ 7 ]−R), EVEX.X bit field (EVEX byte 1, bit [ 6 ]−X), and  957 BEX byte 1, bit[ 5 ]−B). The EVEX.R, EVEX.X, and EVEX.B bit fields provide the same functionality as the corresponding VEX bit fields, and are encoded using is complement form, i.e. ZMM0 is encoded as 1111B, ZMM15 is encoded as 0000B. Other fields of the instructions encode the lower three bits of the register indexes as is known in the art (rrr, xxx, and bbb), so that Rrrr, Xxxx, and Bbbb may be formed by adding EVEX.R, EVEX.X, and EVEX.B. 
     REX′ field  910 —this is the first part of the REX′ field  910  and is the EVEX.R′ bit field (EVEX Byte 1, bit [ 4 ]−R′) that is used to encode either the upper 16 or lower 16 of the extended 32 register set. In one embodiment of the disclosure, this bit, along with others as indicated below, is stored in bit inverted format to distinguish (in the well-known x86 32-bit mode) from the BOUND instruction, whose real opcode byte is 62, but does not accept in the MOD RIM field (described below) the value of 11 in the MOD field; alternative embodiments of the disclosure do not store this and the other indicated bits below in the inverted format. A value of 1 is used to encode the lower 16 registers. In other words, R′Rrrr is formed by combining EVEX.R′, EVEX.R, and the other RRR from other fields. 
     Opcode map field  1015  (EVEX byte 1, bits [ 3 : 0 ]−mmmm)—its content encodes an implied leading opcode byte (0F, 0F 38, or 0F 3). 
     Data element width field  964  (EVEX byte 2, bit [ 7 ]−W)—is represented by the notation EVEX.W. EVEX.W is used to define the granularity (size) of the datatype (either 32-bit data elements or 64-bit data elements). 
     EVEX.vvvv  1020  (EVEX Byte 2, bits [ 6 : 3 ]−vvvv)—the role of EVEX.vvvv may include the following: 1) EVEX.vvvv encodes the first source register operand, specified in inverted (1s complement) form and is valid for instructions with 2 or more source operands; 2) EVEX.vvvv encodes the destination register operand, specified in is complement form for certain vector shifts; or 3) EVEX.vvvv does not encode any operand, the field is reserved and should contain 1111b. Thus, EVEX.vvvv field  1020  encodes the 4 low-order bits of the first source register specifier stored in inverted (1s complement) form. Depending on the instruction, an extra different EVEX bit field is used to extend the specifier size to 32 registers. 
     EVEX.0  968  Class field (EVEX byte 2, bit [ 2 ]−U)—If EVEX.0=0, it indicates class A or EVEX.U0; if EVEX.0=1, it indicates class B or EVEX.U1. 
     Prefix encoding field  1025  (EVEX byte 2, bits [ 1 : 0 ]−pp)—provides additional bits for the base operation field. In addition to providing support for the legacy SSE instructions in the EVEX prefix format, this also has the benefit of compacting the SIMD prefix (rather than requiring a byte to express the SIMD prefix, the EVEX prefix requires only 2 bits). In one embodiment, to support legacy SSE instructions that use a SIMD prefix (66H, F2H, F3H) in both the legacy format and in the EVEX prefix format, these legacy SIMD prefixes are encoded into the SIMD prefix encoding field; and at runtime are expanded into the legacy SIMD prefix prior to being provided to the decoder&#39;s PLA (so the PLA can execute both the legacy and EVEX format of these legacy instructions without modification). Although newer instructions could use the EVEX prefix encoding field&#39;s content directly as an opcode extension, certain embodiments expand in a similar fashion for consistency but allow for different meanings to be specified by these legacy SIMD prefixes. An alternative embodiment may redesign the PLA to support the 2 bit SIMD prefix encodings, and thus not require the expansion. 
     Alpha field  952  (EVEX byte 3, bit [ 7 ]−EH; also known as EVEX.EH, EVEX.rs, EVEX.RL, EVEX.write mask control, and EVEX.N; also illustrated with a)—as previously described, this field is context specific. 
     Beta field  954  (EVEX byte 3, bits [ 6 : 4 ]-SSS, also known as EVEX.s 2-0 , EVEX.r 2-0 , EVEX.rr1, EVEX.LL0, EVEX.LLB; also illustrated with PP(3)—as previously described, this field is context specific. 
     REX′ field  910 —this is the remainder of the REX′ field and is the EVEX.V′ bit field (EVEX Byte 3, bit [ 3 ]−V′) that may be used to encode either the upper 16 or lower 16 of the extended 32 register set. This bit is stored in bit inverted format. A value of 1 is used to encode the lower 16 registers. In other words, V′VVVV is formed by combining EVEX.V′, EVEX.vvvv. 
     Write mask field  970  (EVEX byte 3, bits [ 2 : 0 ]−kkk)—its content specifies the index of a register in the write mask registers as previously described. In one embodiment of the disclosure, the specific value EVEX kkk=000 has a special behavior implying no write mask is used for the particular instruction (this may be implemented in a variety of ways including the use of a write mask hardwired to all ones or hardware that bypasses the masking hardware). 
     Real Opcode Field  1030  (Byte 4) is also known as the opcode byte. Part of the opcode is specified in this field. 
     MOD R/M Field  1040  (Byte 5) includes MOD field  1042 , Reg field  1044 , and R/M field  1046 . As previously described, the MOD field&#39;s  1042  content distinguishes between memory access and non-memory access operations. The role of Reg field  1044  can be summarized to two situations: encoding either the destination register operand or a source register operand, or be treated as an opcode extension and not used to encode any instruction operand. The role of R/M field  1046  may include the following: encoding the instruction operand that references a memory address, or encoding either the destination register operand or a source register operand. 
     Scale, Index, Base (SIB) Byte (Byte 6)—As previously described, the scale field&#39;s  950  content is used for memory address generation. SIB.xxx  1054  and SIB.bbb  1056 —the contents of these fields have been previously referred to with regard to the register indexes Xxxx and Bbbb. 
     Displacement field  962 A (Bytes 7-10)—when MOD field  1042  contains 10, bytes 7-10 are the displacement field  962 A, and it works the same as the legacy 32-bit displacement (disp32) and works at byte granularity. 
     Displacement factor field  962 B (Byte 7)—when MOD field  1042  contains 01, byte 7 is the displacement factor field  962 B. The location of this field is that same as that of the legacy x86 instruction set 8-bit displacement (disp8), which works at byte granularity. Since disp8 is sign extended, it can only address between −128 and 127 bytes offsets; in terms of 64 byte cache lines, disp8 uses 8 bits that can be set to only four really useful values −128, −64, 0, and 64; since a greater range is often needed, disp32 is used; however, disp32 requires 4 bytes. In contrast to disp8 and disp32, the displacement factor field  962 B is a reinterpretation of disp8; when using displacement factor field  962 B, the actual displacement is determined by the content of the displacement factor field multiplied by the size of the memory operand access (N). This type of displacement is referred to as disp8*N. This reduces the average instruction length (a single byte of used for the displacement but with a much greater range). Such compressed displacement is based on the assumption that the effective displacement is multiple of the granularity of the memory access, and hence, the redundant low-order bits of the address offset do not need to be encoded. In other words, the displacement factor field  962 B substitutes the legacy x86 instruction set 8-bit displacement. Thus, the displacement factor field  962 B is encoded the same way as an x86 instruction set 8-bit displacement (so no changes in the ModRM/SIB encoding rules) with the only exception that disp8 is overloaded to disp8*N. In other words, there are no changes in the encoding rules or encoding lengths but only in the interpretation of the displacement value by hardware (which needs to scale the displacement by the size of the memory operand to obtain a byte-wise address offset). Immediate field  972  operates as previously described. 
     Full Opcode Field 
       FIG. 10B  is a block diagram illustrating the fields of the specific vector friendly instruction format  1000  that make up the full opcode field  974  according to one embodiment of the disclosure. Specifically, the full opcode field  974  includes the format field  940 , the base operation field  942 , and the data element width (W) field  964 . The base operation field  942  includes the prefix encoding field  1025 , the opcode map field  1015 , and the real opcode field  1030 . 
     Register Index Field 
       FIG. 10C  is a block diagram illustrating the fields of the specific vector friendly instruction format  1000  that make up the register index field  944  according to one embodiment of the disclosure. Specifically, the register index field  944  includes the REX field  1005 , the REX′ field  1010 , the MODR/M.reg field  1044 , the MODR/M.r/m field  1046 , the VVVV field  1020 , xxx field  1054 , and the bbb field  1056 . 
     Augmentation Operation Field 
       FIG. 10D  is a block diagram illustrating the fields of the specific vector friendly instruction format  1000  that make up the augmentation operation field  950  according to one embodiment of the disclosure. When the class (U) field  968  contains 0, it signifies EVEX.U0 (class A  968 A); when it contains 1, it signifies EVEX.U1 (class B  968 B). When U=0 and the MOD field  1042  contains 11 (signifying a no memory access operation), the alpha field  952  (EVEX byte 3, bit [ 7 ]−EH) is interpreted as the rs field  952 A. When the rs field  952 A contains a 1 (round  952 A. 1 ), the beta field  954  (EVEX byte 3, bits [ 6 : 4 ]−SSS) is interpreted as the round control field  954 A. The round control field  954 A includes a one bit SAE field  956  and a two bit round operation field  958 . When the rs field  952 A contains a 0 (data transform  952 A. 2 ), the beta field  954  (EVEX byte 3, bits [ 6 : 4 ]−SSS) is interpreted as a three bit data transform field  954 B. When U=0 and the MOD field  1042  contains 00, 01, or 10 (signifying a memory access operation), the alpha field  952  (EVEX byte 3, bit [ 7 ]−EH) is interpreted as the eviction hint (EH) field  952 B and the beta field  954  (EVEX byte 3, bits [ 6 : 4 ]−SSS) is interpreted as a three bit data manipulation field  954 C. 
     When U=1, the alpha field  952  (EVEX byte 3, bit [ 7 ]−EH) is interpreted as the write mask control (Z) field  952 C. When U=1 and the MOD field  1042  contains 11 (signifying a no memory access operation), part of the beta field  954  (EVEX byte 3, bit [ 4 ]−S 0 ) is interpreted as the RL field  957 A; when it contains a 1 (round  957 A. 1 ) the rest of the beta field  954  (EVEX byte 3, bit [ 6 - 5 ]−S 2-1 ) is interpreted as the round operation field  959 A, while when the RL field  957 A contains a 0 (VSIZE  957 .A 2 ) the rest of the beta field  954  (EVEX byte 3, bit [ 6 - 5 ]−S 2-1 ) is interpreted as the vector length field  959 B (EVEX byte 3, bit [ 6 - 5 ]−L 1-0 ). When U=1 and the MOD field  1042  contains 00, 01, or 10 (signifying a memory access operation), the beta field  954  (EVEX byte 3, bits [ 6 : 4 ]−SSS) is interpreted as the vector length field  959 B (EVEX byte 3, bit [ 6 - 5 ]−L 1-0 ) and the broadcast field  957 B (EVEX byte 3, bit [ 4 ]−B). 
     Exemplary Register Architecture 
       FIG. 11  is a block diagram of a register architecture  1100  according to one embodiment of the disclosure. In the embodiment illustrated, there are 32 vector registers  1110  that are 512 bits wide; these registers are referenced as zmm0 through zmm31. The lower order 256 bits of the lower 16 zmm registers are overlaid on registers ymm0-16. The lower order 128 bits of the lower 16 zmm registers (the lower order 128 bits of the ymm registers) are overlaid on registers xmm0-15. The specific vector friendly instruction format  1000  operates on these overlaid register file as illustrated in the below tables. 
     
       
         
           
               
               
               
               
             
               
                   
               
               
                 Adjustable Vector 
                   
                   
                   
               
               
                 Length 
                 Class 
                 Operations 
                 Registers 
               
               
                   
               
             
            
               
                 Instruction Templates 
                 A (FIG. 
                 910, 915, 
                 zmm registers (the vector 
               
               
                 that do not include the 
                 9A; U = 
                 925, 930 
                 length is 64 byte) 
               
               
                 vector length field 
                 0) 
               
               
                 959B 
                 B (FIG. 
                 912 
                 zmm registers (the vector 
               
               
                   
                 9B; U = 
                   
                 length is 64 byte) 
               
               
                   
                 1) 
               
               
                 Instruction templates 
                 B (FIG. 
                 917, 927 
                 zmm, ymm, or xmm 
               
               
                 that do include the 
                 9B; U = 
                   
                 registers (the vector 
               
               
                 vector length field 
                 1) 
                   
                 length is 64 byte, 32 
               
               
                 959B 
                   
                   
                 byte, or 16 byte) 
               
               
                   
                   
                   
                 depending on the vector 
               
               
                   
                   
                   
                 length field 959B 
               
               
                   
               
            
           
         
       
     
     In other words, the vector length field  959 B selects between a maximum length and one or more other shorter lengths, where each such shorter length is half the length of the preceding length; and instructions templates without the vector length field  959 B operate on the maximum vector length. Further, in one embodiment, the class B instruction templates of the specific vector friendly instruction format  1000  operate on packed or scalar single/double-precision floating point data and packed or scalar integer data. Scalar operations are operations performed on the lowest order data element position in an zmm/ymm/xmm register; the higher order data element positions are either left the same as they were prior to the instruction or zeroed depending on the embodiment. 
     Write mask registers  1115 —in the embodiment illustrated, there are 8 write mask registers (k 0  through k 7 ), each 64 bits in size. In an alternate embodiment, the write mask registers  1115  are 16 bits in size. As previously described, in one embodiment of the disclosure, the vector mask register k 0  cannot be used as a write mask; when the encoding that would normally indicate k 0  is used for a write mask, it selects a hardwired write mask of 0xFFFF, effectively disabling write masking for that instruction. 
     General-purpose registers  1125 —in the embodiment illustrated, there are sixteen 64-bit general-purpose registers that are used along with the existing x86 addressing modes to address memory operands. These registers are referenced by the names RAX, RBX, RCX, RDX, RBP, RSI, RDI, RSP, and R 8  through R 15 . 
     Scalar floating point stack register file (x87 stack)  1145 , on which is aliased the MMX packed integer flat register file  1150 —in the embodiment illustrated, the x87 stack is an eight-element stack used to perform scalar floating-point operations on 32/64/80-bit floating point data using the x87 instruction set extension; while the MMX registers are used to perform operations on 64-bit packed integer data, as well as to hold operands for some operations performed between the MMX and XMM registers. 
     Alternative embodiments of the disclosure may use wider or narrower registers. Additionally, alternative embodiments of the disclosure may use more, less, or different register files and registers. 
     Exemplary Core Architectures, Processors, and Computer Architectures 
     Processor cores may be implemented in different ways, for different purposes, and in different processors. For instance, implementations of such cores may include: 1) a general purpose in-order core intended for general-purpose computing; 2) a high performance general purpose out-of-order core intended for general-purpose computing; 3) a special purpose core intended primarily for graphics and/or scientific (throughput) computing. Implementations of different processors may include: 1) a CPU including one or more general purpose in-order cores intended for general-purpose computing and/or one or more general purpose out-of-order cores intended for general-purpose computing; and 2) a coprocessor including one or more special purpose cores intended primarily for graphics and/or scientific (throughput). Such different processors lead to different computer system architectures, which may include: 1) the coprocessor on a separate chip from the CPU; 2) the coprocessor on a separate die in the same package as a CPU; 3) the coprocessor on the same die as a CPU (in which case, such a coprocessor is sometimes referred to as special purpose logic, such as integrated graphics and/or scientific (throughput) logic, or as special purpose cores); and 4) a system on a chip that may include on the same die the described CPU (sometimes referred to as the application core(s) or application processor(s)), the above described coprocessor, and additional functionality. Exemplary core architectures are described next, followed by descriptions of exemplary processors and computer architectures. 
     Exemplary Core Architectures 
     In-Order and Out-of-Order Core Block Diagram 
       FIG. 12A  is a block diagram illustrating both an exemplary in-order pipeline and an exemplary register renaming, out-of-order issue/execution pipeline according to embodiments of the disclosure.  FIG. 12B  is a block diagram illustrating both an exemplary embodiment of an in-order architecture core and an exemplary register renaming, out-of-order issue/execution architecture core to be included in a processor according to embodiments of the disclosure. The solid lined boxes in  FIGS. 12A-B  illustrate the in-order pipeline and in-order core, while the optional addition of the dashed lined boxes illustrates the register renaming, out-of-order issue/execution pipeline and core. Given that the in-order aspect is a subset of the out-of-order aspect, the out-of-order aspect will be described. 
     In  FIG. 12A , a processor pipeline  1200  includes a fetch stage  1202 , a length decode stage  1204 , a decode stage  1206 , an allocation stage  1208 , a renaming stage  1210 , a scheduling (also known as a dispatch or issue) stage  1212 , a register read/memory read stage  1214 , an execute stage  1216 , a write back/memory write stage  1218 , an exception handling stage  1222 , and a commit stage  1224 . 
       FIG. 12B  shows processor core  1290  including a front end unit  1230  coupled to an execution engine unit  1250 , and both are coupled to a memory unit  1270 . The core  1290  may be a reduced instruction set computing (RISC) core, a complex instruction set computing (CISC) core, a very long instruction word (VLIW) core, or a hybrid or alternative core type. As yet another option, the core  1290  may be a special-purpose core, such as, for example, a network or communication core, compression engine, coprocessor core, general purpose computing graphics processing unit (GPGPU) core, graphics core, or the like. 
     The front end unit  1230  includes a branch prediction unit  1232  coupled to an instruction cache unit  1234 , which is coupled to an instruction translation lookaside buffer (TLB)  1236 , which is coupled to an instruction fetch unit  1238 , which is coupled to a decode unit  1240 . The decode unit  1240  (or decoder or decoder unit) may decode instructions (e.g., macro-instructions), and generate as an output one or more micro-operations, micro-code entry points, micro-instructions, other instructions, or other control signals, which are decoded from, or which otherwise reflect, or are derived from, the original instructions. The decode unit  1240  may be implemented using various different mechanisms. Examples of suitable mechanisms include, but are not limited to, look-up tables, hardware implementations, programmable logic arrays (PLAs), microcode read only memories (ROMs), etc. In one embodiment, the core  1290  includes a microcode ROM or other medium that stores microcode for certain macro-instructions (e.g., in decode unit  1240  or otherwise within the front end unit  1230 ). The decode unit  1240  is coupled to a rename/allocator unit  1252  in the execution engine unit  1250 . 
     The execution engine unit  1250  includes the rename/allocator unit  1252  coupled to a retirement unit  1254  and a set of one or more scheduler unit(s)  1256 . The scheduler unit(s)  1256  represents any number of different schedulers, including reservations stations, central instruction window, etc. The scheduler unit(s)  1256  is coupled to the physical register file(s) unit(s)  1258 . Each of the physical register file(s) units  1258  represents one or more physical register files, different ones of which store one or more different data types, such as scalar integer, scalar floating point, packed integer, packed floating point, vector integer, vector floating point—status (e.g., an instruction pointer that is the address of the next instruction to be executed), etc. In one embodiment, the physical register file(s) unit  1258  comprises a vector registers unit, a write mask registers unit, and a scalar registers unit. These register units may provide architectural vector registers, vector mask registers, and general purpose registers. The physical register file(s) unit(s)  1258  is overlapped by the retirement unit  1254  to illustrate various ways in which register renaming and out-of-order execution may be implemented (e.g., using a reorder buffer(s) and a retirement register file(s); using a future file(s), a history buffer(s), and a retirement register file(s); using a register maps and a pool of registers; etc.). The retirement unit  1254  and the physical register file(s) unit(s)  1258  are coupled to the execution cluster(s)  1260 . The execution cluster(s)  1260  includes a set of one or more execution units  1262  and a set of one or more memory access units  1264 . The execution units  1262  may perform various operations (e.g., shifts, addition, subtraction, multiplication) and on various types of data (e.g., scalar floating point, packed integer, packed floating point, vector integer, vector floating point). While some embodiments may include a number of execution units dedicated to specific functions or sets of functions, other embodiments may include only one execution unit or multiple execution units that all perform all functions. The scheduler unit(s)  1256 , physical register file(s) unit(s)  1258 , and execution cluster(s)  1260  are shown as being possibly plural because certain embodiments create separate pipelines for certain types of data/operations (e.g., a scalar integer pipeline, a scalar floating point/packed integer/packed floating point/vector integer/vector floating point pipeline, and/or a memory access pipeline that each have their own scheduler unit, physical register file(s) unit, and/or execution cluster—and in the case of a separate memory access pipeline, certain embodiments are implemented in which only the execution cluster of this pipeline has the memory access unit(s)  1264 ). It should also be understood that where separate pipelines are used, one or more of these pipelines may be out-of-order issue/execution and the rest in-order. 
     The set of memory access units  1264  is coupled to the memory unit  1270 , which includes a data TLB unit  1272  coupled to a data cache unit  1274  coupled to a level 2 (L2) cache unit  1276 . In one exemplary embodiment, the memory access units  1264  may include a load unit, a store address unit, and a store data unit, each of which is coupled to the data TLB unit  1272  in the memory unit  1270 . The instruction cache unit  1234  is further coupled to a level 2 (L2) cache unit  1276  in the memory unit  1270 . The L2 cache unit  1276  is coupled to one or more other levels of cache and eventually to a main memory. 
     By way of example, the exemplary register renaming, out-of-order issue/execution core architecture may implement the pipeline  1200  as follows: 1) the instruction fetch  1238  performs the fetch and length decoding stages  1202  and  1204 ; 2) the decode unit  1240  performs the decode stage  1206 ; 3) the rename/allocator unit  1252  performs the allocation stage  1208  and renaming stage  1210 ; 4) the scheduler unit(s)  1256  performs the schedule stage  1212 ; 5) the physical register file(s) unit(s)  1258  and the memory unit  1270  perform the register read/memory read stage  1214 ; the execution cluster  1260  perform the execute stage  1216 ; 6) the memory unit  1270  and the physical register file(s) unit(s)  1258  perform the write back/memory write stage  1218 ; 7) various units may be involved in the exception handling stage  1222 ; and 8) the retirement unit  1254  and the physical register file(s) unit(s)  1258  perform the commit stage  1224 . 
     The core  1290  may support one or more instructions sets (e.g., the x86 instruction set (with some extensions that have been added with newer versions); the MIPS instruction set of MIPS Technologies of Sunnyvale, Calif.; the ARM instruction set (with optional additional extensions such as NEON) of ARM Holdings of Sunnyvale, Calif.), including the instruction(s) described herein. In one embodiment, the core  1290  includes logic to support a packed data instruction set extension (e.g., AVX1, AVX2), thereby allowing the operations used by many multimedia applications to be performed using packed data. 
     It should be understood that the core may support multithreading (executing two or more parallel sets of operations or threads), and may do so in a variety of ways including time sliced multithreading, simultaneous multithreading (where a single physical core provides a logical core for each of the threads that physical core is simultaneously multithreading), or a combination thereof (e.g., time sliced fetching and decoding and simultaneous multithreading thereafter such as in the Intel® Hyper-Threading technology). 
     While register renaming is described in the context of out-of-order execution, it should be understood that register renaming may be used in an in-order architecture. While the illustrated embodiment of the processor also includes separate instruction and data cache units  1234 / 1274  and a shared L2 cache unit  1276 , alternative embodiments may have a single internal cache for both instructions and data, such as, for example, a Level 1 (L1) internal cache, or multiple levels of internal cache. In some embodiments, the system may include a combination of an internal cache and an external cache that is external to the core and/or the processor. Alternatively, all of the cache may be external to the core and/or the processor. 
     Specific Exemplary In-Order Core Architecture 
       FIGS. 13A-B  illustrate a block diagram of a more specific exemplary in-order core architecture, which core would be one of several logic blocks (including other cores of the same type and/or different types) in a chip. The logic blocks communicate through a high-bandwidth interconnect network (e.g., a ring network) with some fixed function logic, memory I/O interfaces, and other necessary I/O logic, depending on the application. 
       FIG. 13A  is a block diagram of a single processor core, along with its connection to the on-die interconnect network  1302  and with its local subset of the Level 2 (L2) cache  1304 , according to embodiments of the disclosure. In one embodiment, an instruction decode unit  1300  supports the x86 instruction set with a packed data instruction set extension. An L1 cache  1306  allows low-latency accesses to cache memory into the scalar and vector units. While in one embodiment (to simplify the design), a scalar unit  1308  and a vector unit  1310  use separate register sets (respectively, scalar registers  1312  and vector registers  1314 ) and data transferred between them is written to memory and then read back in from a level 1 (L1) cache  1306 , alternative embodiments of the disclosure may use a different approach (e.g., use a single register set or include a communication path that allow data to be transferred between the two register files without being written and read back). 
     The local subset of the L2 cache  1304  is part of a global L2 cache that is divided into separate local subsets, one per processor core. Each processor core has a direct access path to its own local subset of the L2 cache  1304 . Data read by a processor core is stored in its L2 cache subset  1304  and can be accessed quickly, in parallel with other processor cores accessing their own local L2 cache subsets. Data written by a processor core is stored in its own L2 cache subset  1304  and is flushed from other subsets, if necessary. The ring network ensures coherency for shared data. The ring network is bi-directional to allow agents such as processor cores, L2 caches and other logic blocks to communicate with each other within the chip. Each ring data-path is 1012-bits wide per direction. 
       FIG. 13B  is an expanded view of part of the processor core in  FIG. 13A  according to embodiments of the disclosure.  FIG. 13B  includes an L1 data cache  1306 A part of the L1 cache  1304 , as well as more detail regarding the vector unit  1310  and the vector registers  1314 . Specifically, the vector unit  1310  is a 16-wide vector processing unit (VPU) (see the 16-wide ALU  1328 ), which executes one or more of integer, single-precision float, and double-precision float instructions. The VPU supports swizzling the register inputs with swizzle unit  1320 , numeric conversion with numeric convert units  1322 A-B, and replication with replication unit  1324  on the memory input. Write mask registers  1326  allow predicating resulting vector writes. 
       FIG. 14  is a block diagram of a processor  1400  that may have more than one core, may have an integrated memory controller, and may have integrated graphics according to embodiments of the disclosure. The solid lined boxes in  FIG. 14  illustrate a processor  1400  with a single core  1402 A, a system agent  1410 , a set of one or more bus controller units  1416 , while the optional addition of the dashed lined boxes illustrates an alternative processor  1400  with multiple cores  1402 A-N, a set of one or more integrated memory controller unit(s)  1414  in the system agent unit  1410 , and special purpose logic  1408 . 
     Thus, different implementations of the processor  1400  may include: 1) a CPU with the special purpose logic  1408  being integrated graphics and/or scientific (throughput) logic (which may include one or more cores), and the cores  1402 A-N being one or more general purpose cores (e.g., general purpose in-order cores, general purpose out-of-order cores, a combination of the two); 2) a coprocessor with the cores  1402 A-N being a large number of special purpose cores intended primarily for graphics and/or scientific (throughput); and 3) a coprocessor with the cores  1402 A-N being a large number of general purpose in-order cores. Thus, the processor  1400  may be a general-purpose processor, coprocessor or special-purpose processor, such as, for example, a network or communication processor, compression engine, graphics processor, GPGPU (general purpose graphics processing unit), a high-throughput many integrated core (MIC) coprocessor (including 30 or more cores), embedded processor, or the like. The processor may be implemented on one or more chips. The processor  1400  may be a part of and/or may be implemented on one or more substrates using any of a number of process technologies, such as, for example, BiCMOS, CMOS, or NMOS. 
     The memory hierarchy includes one or more levels of cache within the cores, a set or one or more shared cache units  1406 , and external memory (not shown) coupled to the set of integrated memory controller units  1414 . The set of shared cache units  1406  may include one or more mid-level caches, such as level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache, a last level cache (LLC), and/or combinations thereof. While in one embodiment a ring based interconnect unit  1412  interconnects the integrated graphics logic  1408 , the set of shared cache units  1406 , and the system agent unit  1410 /integrated memory controller unit(s)  1414 , alternative embodiments may use any number of well-known techniques for interconnecting such units. In one embodiment, coherency is maintained between one or more cache units  1406  and cores  1402 -A-N. 
     In some embodiments, one or more of the cores  1402 A-N are capable of multi-threading. The system agent  1410  includes those components coordinating and operating cores  1402 A-N. The system agent unit  1410  may include for example a power control unit (PCU) and a display unit. The PCU may be or include logic and components needed for regulating the power state of the cores  1402 A-N and the integrated graphics logic  1408 . The display unit is for driving one or more externally connected displays. 
     The cores  1402 A-N may be homogenous or heterogeneous in terms of architecture instruction set; that is, two or more of the cores  1402 A-N may be capable of execution the same instruction set, while others may be capable of executing only a subset of that instruction set or a different instruction set. 
     Exemplary Computer Architectures 
       FIGS. 15-18  are block diagrams of exemplary computer architectures. Other system designs and configurations known in the arts for laptops, desktops, handheld PCs, personal digital assistants, engineering workstations, servers, network devices, network hubs, switches, embedded processors, digital signal processors (DSPs), graphics devices, video game devices, set-top boxes, micro controllers, cell phones, portable media players, hand held devices, and various other electronic devices, are also suitable. In general, a huge variety of systems or electronic devices capable of incorporating a processor and/or other execution logic as disclosed herein are generally suitable. 
     Referring now to  FIG. 15 , shown is a block diagram of a system  1500  in accordance with one embodiment of the present disclosure. The system  1500  may include one or more processors  1510 ,  1515 , which are coupled to a controller hub  1520 . In one embodiment the controller hub  1520  includes a graphics memory controller hub (GMCH)  1590  and an Input/Output Hub (IOH)  1550  (which may be on separate chips); the GMCH  1590  includes memory and graphics controllers to which are coupled memory  1540  and a coprocessor  1545 ; the IOH  1550  is couples input/output (I/O) devices  1560  to the GMCH  1590 . Alternatively, one or both of the memory and graphics controllers are integrated within the processor (as described herein), the memory  1540  and the coprocessor  1545  are coupled directly to the processor  1510 , and the controller hub  1520  in a single chip with the IOH  1550 . Memory  1540  may include “ones” multiplication code  1540 A, for example, to store code that when executed causes a processor to perform any method of this disclosure. 
     The optional nature of additional processors  1515  is denoted in  FIG. 15  with broken lines. Each processor  1510 ,  1515  may include one or more of the processing cores described herein and may be some version of the processor  1400 . 
     The memory  1540  may be, for example, dynamic random access memory (DRAM), phase change memory (PCM), or a combination of the two. For at least one embodiment, the controller hub  1520  communicates with the processor(s)  1510 ,  1515  via a multi-drop bus, such as a frontside bus (FSB), point-to-point interface such as Quickpath Interconnect (QPI), or similar connection  1595 . 
     In one embodiment, the coprocessor  1545  is a special-purpose processor, such as, for example, a high-throughput MIC processor, a network or communication processor, compression engine, graphics processor, GPGPU, embedded processor, or the like. In one embodiment, controller hub  1520  may include an integrated graphics accelerator. 
     There can be a variety of differences between the physical resources  1510 ,  1515  in terms of a spectrum of metrics of merit including architectural, microarchitectural, thermal, power consumption characteristics, and the like. 
     In one embodiment, the processor  1510  executes instructions that control data processing operations of a general type. Embedded within the instructions may be coprocessor instructions. The processor  1510  recognizes these coprocessor instructions as being of a type that should be executed by the attached coprocessor  1545 . Accordingly, the processor  1510  issues these coprocessor instructions (or control signals representing coprocessor instructions) on a coprocessor bus or other interconnect, to coprocessor  1545 . Coprocessor(s)  1545  accept and execute the received coprocessor instructions. 
     Referring now to  FIG. 16 , shown is a block diagram of a first more specific exemplary system  1600  in accordance with an embodiment of the present disclosure. As shown in  FIG. 16 , multiprocessor system  1600  is a point-to-point interconnect system, and includes a first processor  1670  and a second processor  1680  coupled via a point-to-point interconnect  1650 . Each of processors  1670  and  1680  may be some version of the processor  1400 . In one embodiment of the disclosure, processors  1670  and  1680  are respectively processors  1510  and  1515 , while coprocessor  1638  is coprocessor  1545 . In another embodiment, processors  1670  and  1680  are respectively processor  1510  coprocessor  1545 . 
     Processors  1670  and  1680  are shown including integrated memory controller (IMC) units  1672  and  1682 , respectively. Processor  1670  also includes as part of its bus controller units point-to-point (P-P) interfaces  1676  and  1678 ; similarly, second processor  1680  includes P-P interfaces  1686  and  1688 . Processors  1670 ,  1680  may exchange information via a point-to-point (P-P) interface  1650  using P-P interface circuits  1678 ,  1688 . As shown in  FIG. 16 , IMCs  1672  and  1682  couple the processors to respective memories, namely a memory  1632  and a memory  1634 , which may be portions of main memory locally attached to the respective processors. 
     Processors  1670 ,  1680  may each exchange information with a chipset  1690  via individual P-P interfaces  1652 ,  1654  using point to point interface circuits  1676 ,  1694 ,  1686 ,  1698 . Chipset  1690  may optionally exchange information with the coprocessor  1638  via a high-performance interface  1639 . In one embodiment, the coprocessor  1638  is a special-purpose processor, such as, for example, a high-throughput MIC processor, a network or communication processor, compression engine, graphics processor, GPGPU, embedded processor, or the like. 
     A shared cache (not shown) may be included in either processor or outside of both processors, yet connected with the processors via P-P interconnect, such that either or both processors&#39; local cache information may be stored in the shared cache if a processor is placed into a low power mode. 
     Chipset  1690  may be coupled to a first bus  1616  via an interface  1696 . In one embodiment, first bus  1616  may be a Peripheral Component Interconnect (PCI) bus, or a bus such as a PCI Express bus or another third generation I/O interconnect bus, although the scope of the present disclosure is not so limited. 
     As shown in  FIG. 16 , various I/O devices  1614  may be coupled to first bus  1616 , along with a bus bridge  1618  which couples first bus  1616  to a second bus  1620 . In one embodiment, one or more additional processor(s)  1615 , such as coprocessors, high-throughput MIC processors, GPGPU&#39;s, accelerators (such as, e.g., graphics accelerators or digital signal processing (DSP) units), field programmable gate arrays, or any other processor, are coupled to first bus  1616 . In one embodiment, second bus  1620  may be a low pin count (LPC) bus. Various devices may be coupled to a second bus  1620  including, for example, a keyboard and/or mouse  1622 , communication devices  1627  and a storage unit  1628  such as a disk drive or other mass storage device which may include instructions/code and data  1630 , in one embodiment. Further, an audio I/O  1624  may be coupled to the second bus  1620 . Note that other architectures are possible. For example, instead of the point-to-point architecture of  FIG. 16 , a system may implement a multi-drop bus or other such architecture. 
     Referring now to  FIG. 17 , shown is a block diagram of a second more specific exemplary system  1700  in accordance with an embodiment of the present disclosure Like elements in  FIGS. 16 and 17  bear like reference numerals, and certain aspects of  FIG. 16  have been omitted from  FIG. 17  in order to avoid obscuring other aspects of  FIG. 17 . 
       FIG. 17  illustrates that the processors  1670 ,  1680  may include integrated memory and I/O control logic (“CL”)  1672  and  1682 , respectively. Thus, the CL  1672 ,  1682  include integrated memory controller units and include I/O control logic.  FIG. 17  illustrates that not only are the memories  1632 ,  1634  coupled to the CL  1672 ,  1682 , but also that I/O devices  1714  are also coupled to the control logic  1672 ,  1682 . Legacy I/O devices  1715  are coupled to the chipset  1690 . 
     Referring now to  FIG. 18 , shown is a block diagram of a SoC  1800  in accordance with an embodiment of the present disclosure. Similar elements in  FIG. 14  bear like reference numerals. Also, dashed lined boxes are optional features on more advanced SoCs. In  FIG. 18 , an interconnect unit(s)  1802  is coupled to: an application processor  1810  which includes a set of one or more cores  202 A-N and shared cache unit(s)  1406 ; a system agent unit  1410 ; a bus controller unit(s)  1416 ; an integrated memory controller unit(s)  1414 ; a set or one or more coprocessors  1820  which may include integrated graphics logic, an image processor, an audio processor, and a video processor; an static random access memory (SRAM) unit  1830 ; a direct memory access (DMA) unit  1832 ; and a display unit  1840  for coupling to one or more external displays. In one embodiment, the coprocessor(s)  1820  include a special-purpose processor, such as, for example, a network or communication processor, compression engine, GPGPU, a high-throughput MIC processor, embedded processor, or the like. 
     Embodiments (e.g., of the mechanisms) disclosed herein may be implemented in hardware, software, firmware, or a combination of such implementation approaches. Embodiments of the disclosure may be implemented as computer programs or program code executing on programmable systems comprising at least one processor, a storage system (including volatile and non-volatile memory and/or storage elements), at least one input device, and at least one output device. 
     Program code, such as code  1630  illustrated in  FIG. 16 , may be applied to input instructions to perform the functions described herein and generate output information. The output information may be applied to one or more output devices, in known fashion. For purposes of this application, a processing system includes any system that has a processor, such as, for example; a digital signal processor (DSP), a microcontroller, an application specific integrated circuit (ASIC), or a microprocessor. 
     The program code may be implemented in a high level procedural or object oriented programming language to communicate with a processing system. The program code may also be implemented in assembly or machine language, if desired. In fact, the mechanisms described herein are not limited in scope to any particular programming language. In any case, the language may be a compiled or interpreted language. 
     One or more aspects of at least one embodiment may be implemented by representative instructions stored on a machine-readable medium which represents various logic within the processor, which when read by a machine causes the machine to fabricate logic to perform the techniques described herein. Such representations, known as “IP cores” may be stored on a tangible, machine readable medium and supplied to various customers or manufacturing facilities to load into the fabrication machines that actually make the logic or processor. 
     Such machine-readable storage media may include, without limitation, non-transitory, tangible arrangements of articles manufactured or formed by a machine or device, including storage media such as hard disks, any other type of disk including floppy disks, optical disks, compact disk read-only memories (CD-ROMs), compact disk rewritable&#39;s (CD-RWs), and magneto-optical disks, semiconductor devices such as read-only memories (ROMs), random access memories (RAMs) such as dynamic random access memories (DRAMs), static random access memories (SRAMs), erasable programmable read-only memories (EPROMs), flash memories, electrically erasable programmable read-only memories (EEPROMs), phase change memory (PCM), magnetic or optical cards, or any other type of media suitable for storing electronic instructions. 
     Accordingly, embodiments of the disclosure also include non-transitory, tangible machine-readable media containing instructions or containing design data, such as Hardware Description Language (HDL), which defines structures, circuits, apparatuses, processors and/or system features described herein. Such embodiments may also be referred to as program products. 
     Emulation (Including Binary Translation, Code Morphing, Etc.) 
     In some cases, an instruction converter may be used to convert an instruction from a source instruction set to a target instruction set. For example, the instruction converter may translate (e.g., using static binary translation, dynamic binary translation including dynamic compilation), morph, emulate, or otherwise convert an instruction to one or more other instructions to be processed by the core. The instruction converter may be implemented in software, hardware, firmware, or a combination thereof. The instruction converter may be on processor, off processor, or part on and part off processor. 
       FIG. 19  is a block diagram contrasting the use of a software instruction converter to convert binary instructions in a source instruction set to binary instructions in a target instruction set according to embodiments of the disclosure. In the illustrated embodiment, the instruction converter is a software instruction converter, although alternatively the instruction converter may be implemented in software, firmware, hardware, or various combinations thereof.  FIG. 19  shows a program in a high level language  1902  may be compiled using an x86 compiler  1904  to generate x86 binary code  1906  that may be natively executed by a processor with at least one x86 instruction set core  1916 . The processor with at least one x86 instruction set core  1916  represents any processor that can perform substantially the same functions as an Intel® processor with at least one x86 instruction set core by compatibly executing or otherwise processing (1) a substantial portion of the instruction set of the Intel® x86 instruction set core or (2) object code versions of applications or other software targeted to run on an Intel® processor with at least one x86 instruction set core, in order to achieve substantially the same result as an Intel® processor with at least one x86 instruction set core. The x86 compiler  1904  represents a compiler that is operable to generate x86 binary code  1906  (e.g., object code) that can, with or without additional linkage processing, be executed on the processor with at least one x86 instruction set core  1916 . Similarly,  FIG. 19  shows the program in the high level language  1902  may be compiled using an alternative instruction set compiler  1908  to generate alternative instruction set binary code  1910  that may be natively executed by a processor without at least one x86 instruction set core  1914  (e.g., a processor with cores that execute the MIPS instruction set of MIPS Technologies of Sunnyvale, Calif. and/or that execute the ARM instruction set of ARM Holdings of Sunnyvale, Calif.). The instruction converter  1912  is used to convert the x86 binary code  1906  into code that may be natively executed by the processor without an x86 instruction set core  1914 . This converted code is not likely to be the same as the alternative instruction set binary code  1910  because an instruction converter capable of this is difficult to make; however, the converted code will accomplish the general operation and be made up of instructions from the alternative instruction set. Thus, the instruction converter  1912  represents software, firmware, hardware, or a combination thereof that, through emulation, simulation or any other process, allows a processor or other electronic device that does not have an x86 instruction set processor or core to execute the x86 binary code  1906 .