Patent Publication Number: US-2018029561-A1

Title: Pattern detection

Description:
The present disclosure relates to the field of pattern detection, and in particular, although not exclusively, to a pattern detection unit for a transceiver in an automotive access system. 
     Passive keyless entry (PKE) and passive keyless go (PKG) systems have gained popularity in recent years. In operation, when a car user has a key apparatus that is equipped with a PKE chip and the user approaches a car and attempts to opens the door, a low frequency (LF) communication sequence is sent from the car to the key, and an ultra-high frequency (UHF) communication is sent from the key to the car via a different physical link, and the door is unlocked. Cryptology is involved in both communications to make sure the correct key and car are identified. The same interaction can work with a start button for a vehicle using PKG. When the user presses the start button, an LF communication is sent to the key, which returns a UHF signal to the vehicle to enable the user to start the car. 
     According to a first aspect of the present disclosure there is provided a pattern detection unit comprising:
         a shift register configured to over-sample a multi-bit input signal such that each bit of the input signal is represented by a plurality of samples in the shift register; and   a correlator configured to compare a target pattern with two or more of the plurality of samples of each bit from the shift register in order to determine whether the input signal matches the target pattern.       

     In one or more embodiments the correlator is configured to determine a match in response to each bit of the target pattern matching all of the two or more samples of a corresponding bit-value from the shift register. 
     In one or more embodiments the correlator is configured to compare the target pattern to consecutive samples from the shift register of each bit of the input signal. 
     In one or more embodiments the correlator is configured to compare the target pattern with one of the plurality of samples of each bit and, optionally in parallel, to compare the target pattern with another of the plurality of samples of each bit in order to compare the target pattern to the two or more samples of each bit. 
     In one or more embodiments the correlator comprises one or more of:
         a first plurality of bit comparison units, each bit comparison unit configured to compare one sample of a particular bit from the shift register with a corresponding bit-value of the target pattern and determine a first bit-comparison value based on the comparison;   a second plurality of bit comparison units, each bit comparison unit configured to compare another sample of the particular bit from the shift register with a corresponding bit-value of the target pattern and determine a second bit-comparison value based on the comparison; and   a code comparison unit, wherein the code comparison unit is configured to process the first and second bit-comparison values in order to determine a match indication signal that is representative of whether or not the input signal matches the target pattern for a single clock cycle.       

     In one or more embodiments the correlator is configured to compare the target pattern with one of the plurality of samples of each bit and, subsequently or separately, to compare the target pattern to another of the plurality of samples of each bit in order to compare the target pattern to the two or more samples of each bit. 
     In one or more embodiments the correlator comprises one or more of:
         a plurality of bit comparison units, each bit comparison unit configured to compare one sample of a particular bit from the shift register with a corresponding bit-value of the target pattern and determine a bit-comparison value based on the comparison;   a code comparison unit, wherein the code comparison unit is configured to process the bit-comparison values in order to determine a match indication signal that is representative of whether or not the input signal matches the target pattern for a single clock cycle; and   a sequence detector configured to determine whether the input signal matches the target pattern based on two or more match indication signals provided by the code comparison unit for different clock cycles.       

     In one or more embodiments the two or more match indication signals are provided by the code comparison unit for consecutive clock cycles. 
     In one or more embodiments the sequence detector comprises:
         a buffer configured to receive the match indication signal of the code comparison unit and provide a buffered match indication signal; and   an AND unit having a first input terminal, a second input terminal and an output terminal, in which the first input terminal is configured to receive the match indication signal of the code comparison unit, the second input terminal is configured to receive the buffered match indication signal from the buffer.       

     In one or more embodiments the sequence detector is configured to
         provide an output signal;   set the output signal as a matching-value in response to two consecutive match indication signals being indicative of the input signal matching the target pattern; and   maintain the output signal as the matching-value for the same number of consecutive clock cycles that the match indication signals are indicative of the input signal matching the target pattern.       

     In one or more embodiments the sequence detector is configured to
         provide an output signal;   set the output signal as a matching-value in response to two or more match indication signals from a group-of-match-indication-signals being indicative of the input signal matching the target pattern; and   maintain the output signal as the matching-value for the number of clock cycles that are represented by the group-of-match-indication-signals.       

     In one or more embodiments the pattern detection is configured to be operable in a first-mode-of-operation and a second-mode-of-operation, wherein:
         in the first-mode-of-operation:
           the correlator is configured to compare the target pattern with two or more of the plurality of samples of each bit from the shift register in order to determine whether or not the input signal matches the target pattern; and   
           in the second-mode-of-operation:
           the correlator is configured to compare the target pattern with only one of the plurality of samples of each bit from the shift register in order to determine whether or not the input signal matches the target pattern; and   
           the pattern detection unit may further comprise a controller configured to set the mode of operation of the pattern detection unit based on user input or automatically.       

     In one or more embodiments the pattern detection comprises a memory for storing the target pattern, in which the memory may be operatively connected to the correlator for providing the target pattern to the correlator. 
     There may be provided a key fob for a vehicle comprising a receiver, wherein the receiver comprises any pattern detection disclosed herein. 
     There may be provided a method of detecting a pattern in an input signal, comprising
         receiving a multi-bit input signal at a shift register;   over-sampling the multi-bit input signal using the shift register such that each bit of the input signal is represented by a plurality of samples from the shift register;   comparing the target pattern with two or more of the plurality of samples of each bit of the input signal from the shift register;   determining whether or not the input signal matches the target pattern based on the comparison.       

     There may be provided a computer program, which when run on a computer, causes the computer to configure any apparatus, including a pattern detection unit, detector, circuit, controller, or device disclosed herein or to perform any method disclosed herein. 
     While the disclosure is amenable to various modifications and alternative forms, specifics thereof have been shown by way of example in the drawings and will be described in detail. It should be understood, however, that other embodiments, beyond the particular embodiments described, are possible as well. All modifications, equivalents, and alternative embodiments falling within the spirit and scope of the appended claims are covered as well. 
    
    
     
       The above discussion is not intended to represent every example embodiment or every implementation within the scope of the current or future Claim sets. The figures and Detailed Description that follow also exemplify various example embodiments. Various example embodiments may be more completely understood in consideration of the following Detailed Description in connection with the accompanying Drawings. 
       One or more embodiments will now be described by way of example only with reference to the accompanying drawings in which: 
         FIG. 1  shows an apparatus for communicating with a remote transceiver; 
         FIG. 2  illustrates a pattern detection unit for the remote transceiver circuit of  FIG. 1 . 
         FIG. 3  illustrates an improved pattern detection unit; 
         FIG. 4  illustrates another improved pattern detection unit; 
         FIGS. 5 a  to 5 c    illustrate three example implementations of sequence detectors for use in the pattern detection unit of  FIG. 4 ; 
         FIG. 6  illustrates example contents of a shift register and corresponding match indication signals from the sequence detectors of  FIGS. 5 a  to 5 c   ; and 
         FIG. 7  illustrates a method of detecting a pattern in an input signal. 
     
    
    
     The system described herein is related but not limited to the wireless communication link between a vehicle and a key for the vehicle. By way of example, the system described herein is related to a wireless communication link between a car and the car key thereof. A car (base station) transmits protocol frames in the low frequency (LF) band and a receiver in the car key receives and decodes the frames. The LF transmission is unidirectional from the car to the keys and it may be complemented with an ultra-high frequency (UHF) transmission from the keys to the car. The LF band (at 125 kHz, for example) which can be useful in a metal environment (as with automobiles) and is relatively insensitive to body de-tuning (e.g., by touching). The LF receiver in the car key may stay active all of the time, or in a polling mode. Thus current consumption is a concern. 
       FIG. 1  illustrates apparatuses and a system  100  to communicate with remote transceiver circuit  120 . The system  100  may include a vehicle base station  110  and a remote transceiver circuit  120 . Each of the base station  110 , and remote transceiver circuit  120  can be implemented separately. The system  100  can be implemented with the base station  110  and the remote transceiver circuit  120  while the base station  110  is also interacting with another remote transceiver circuit. In these contexts, the remote transceiver circuit  120  may be a PKE and/or PKG type of hand-held device that can be carried by an operator (e.g., in a pocket or handbag). 
     The vehicle base station  110  includes a transmitter  155 , receiver  165  and a controller circuit  160 . The transmitter  155  of the vehicle base station  110  may be a low-frequency transmitter, and the receiver  165  of the vehicle base station  110  may be an ultra-high-frequency receiver. 
     The vehicle base station  110  may utilize a controller circuit  160  to control the transmitter  155  and receiver  165  to communicate signals with remote transceiver circuit  120 . Accordingly, the controller circuit  160  may be implemented to facilitate data transmission via the transmitter  155  to communicate with the remote transceiver circuit  120 . 
     The controller circuit  160  of the vehicle base station  110  may delegate authentication of the remote transceiver circuit  120  to an authentication module  185 . Accordingly, the controller circuit  160  may generate an output to the interface module  175  containing the response data of the remote transceiver circuit  120  as received by the receiver  165  of the vehicle base station  110 . The interface module  175  then communicates the response data to an authentication module  185  via a bus  180 . The authentication module  185  processes the response data received from the remote transceiver circuit  120  with stored authentication data. If the remote transceiver circuit  120  is authenticated, the authentication module  185  communicates activation data over the vehicle bus  180 , and the activation data allows for the operation of a vehicle drive circuit  170  that facilitates operation of a vehicle drive system in the vehicle. 
     The remote transceiver circuit  120  may include a receiver  125 , a transmitter  150 , a controller circuit  145  and a data-receiving circuit  135 . The remote transceiver circuit  120  may further include a state machine  140 . The receiver  125  of the remote transceiver circuit  120  may be a low-frequency receiver that corresponds to the transmitter  155  of the vehicle base station  110 . The transmitter  150  of the remote transceiver circuit  120  may be an ultra-high-frequency transmitter that corresponds to the receiver  165  of the vehicle base station  110 . 
     The remote transceiver circuit  120  utilizes the controller circuit  145  to control the transmitter  150  and receiver  125  for communicating signals with vehicle base station  110 . 
     In use, the controller circuit  160  and transmitter  155  of the vehicle base station  110  poll for the presence of the remote transceiver circuit  120  by periodically transmitting a LF signal. The receiver  125  of the remote transceiver circuit  120  monitors for the presence of the LF signal comprising a particular data pattern. The data-receiving circuit  135  of the remote transceiver circuit  120  comprises a pattern detection unit (not shown). The pattern detection unit is configured to compare a signal from the data-receiving circuit  135  with a target pattern, or a number of target patterns. Each vehicle base station  110  is associated with one or more target patterns that are individual to that vehicle base station  110 . When the remote transceiver circuit  120  is within range of the vehicle base station  110 , the receiver  125  and data-receiving circuit  135  of the remote transceiver circuit  120  provide the LF signal to the controller circuit  145 , which determines whether or not the data pattern in the LF signal matches the target pattern. In response to finding a match, the controller circuit  145  operates the transmitter  150  of the remote transceiver circuit  120  to send an authorisation signal back to the vehicle base station  110 . 
     The state machine  140  of the remote transceiver circuit  120  facilitates on and off modes of the data-receiving circuit  135 . 
     The embodiment shown in  FIG. 1  may be implemented to conserve power using one or more approaches as described herein. In addition, one or more embodiments may be implemented with transceiver circuits used in vehicle applications, such as PKE applications, such as with single chip keyless entry transceivers employing a RISC controller. The RISC controller may be powered with an ISO 14443 type A interface. In other embodiments, the remote transceiver circuit may implement a controller with a built-in UHF transmitter or a transmitter with a separate controller. 
     A passive keyless entry (PKE)/passive keyless go (PKG) receiver described herein may make use of several integrated circuit devices that include a fully integrated single-chip solution combining remote keyless entry (RKE), PKE and immobilizer (IMMO) functionality designed for use in automotive environments. 
       FIG. 2  illustrates a pattern detection unit  200  for the data-receiving circuit of the remote transceiver circuit described above with reference to  FIG. 1 . The pattern detection unit  200  comprises a shift register  202  and a correlator  204 . 
     The shift register  202  has a data input terminal  206  and a plurality of sample registers (not shown). The shift register  202  is configured to over-sample an n-bit input signal such that each bit of the input signal is loaded into the shift register  202  a plurality of (m) times. In this way, each bit can be represented by a plurality of m-samples as it passes through the shift register. Each bit may be considered to provide a separate symbol. 
     The sample registers operate in a conventional manner such that the n-bit input signal is received as a serial communication at the data input terminal  206 . During operation, the input signal received at the data input terminal  206  is sequentially shifted through the sample registers in the shift register  202  in response to each pulse in a clock cycle. The shift register  202  has a clock frequency  210  that is m times the sample frequency of the input signal at the data input terminal  206  in order to oversample the input signal. A train of m-samples is therefore generated for each bit of the input signal as it enters the shift register. The train of m-samples therefore progresses sequentially through the sample registers in the shift register. 
     The sample registers can be considered to be grouped together in sample-register-groups, with each sample-register-group comprising one or more sample registers. The first sample-register-group  213   a  to the n-1 th  sample-register-group  213   n -1 contain m sample registers such that the full batch of m samples can be passed on to the next sample-register-group in the shift register  202 . The n th  (last) sample-register-group  213   n  includes at least one sample register. In this example, the n th  (last) sample-register-group  213   n  includes a single sample register because only one signal from the n th  sample-register-group  213   n  needs to be processed by the correlator  204 , and because there are no subsequent sample-register-groups for the samples to be passed on to. The shift register  202  therefore comprises (n-1)*m+1 sample registers. The sample registers in each sample-register-group are contiguous with the sample registers in neighbouring sample-register-groups. Each sample register has a separate output terminal  208  in this example. 
     The correlator  204  comprises a plurality of bit comparison units  212   a - n  and a code comparison unit  214 . An output terminal from one sample register in each sample-register-group is connected to a first input terminal of an associated bit comparison unit  212   a - n.  The selected sample registers are spaced apart by m-samples, in this example. For instance, the output terminal of the first sample register of each sample-register-group is connected to the first input terminal of a respective bit comparison unit  212   a - n.  A second input terminal of each bit comparison unit  212   a - n  is configured to receive a bit-value of an n-bit target pattern corresponding to the respective sample-register-group associated with the bit comparison unit  212   a - n.  For example, the first bit of the target pattern is compared with a sample from the first sample-register-group, and the n th  bit of the target pattern is compared with a sample from the n th  sample-register-group. In this way, each bit comparison unit  212   a - n  is able to compare one sample of a particular bit-value in the shift register with a corresponding bit-value of the target pattern and provide a bit-comparison value at an output terminal of the bit comparison unit  212   a - n.  The bit-comparison value indicates whether or not a particular sample matches a corresponding bit-value of the target pattern. 
     The code comparison unit  214  has an output terminal and a plurality of input terminals connected to respective output terminals of the plurality of bit comparison units  212   a - n . The code comparison unit  214  is configured to receive the bit-comparison values from each of the bit comparison units  212   a - n  and determine whether, overall, the plurality of samples (from one in every sample-register-group in the shift register) matches the target pattern. The code comparison unit  214  may be implemented by a multi-input AND gate and each bit comparison unit  212   a - n  may be implemented by an XNOR gate. An alternative implementation can use an adder instead of the AND gate. The adder output is compared against a threshold of a minimum number of samples that should match. If the adder output is greater than or equal this threshold a match is reported. This mechanism can be used to support error tolerance, e.g. to allow a successful match, even if one or two samples are destroyed by an interferer or by noise. As a further alternative, the code comparison unit  214  may be implemented by a multi-input NOR gate and each bit comparison unit  212   a - n  may be implemented by an XOR gate. 
     The effect of over-sampling the data is that the correlator has m attempts to determine a match for each bit. In this way, the failure to identify a match due to corruption of a sample can be avoided or reduced and so the sensitivity of the system is improved. 
     In this way, the correlator  204  is configured, using the bit comparison units  212   a - n,  to compare a target pattern to a sample of each bit of the input signal in the shift register  202 , and, using the code comparison unit  214 , to determine whether the input signal matches the target pattern based on the comparison. 
     If a data stream is presented at the data input terminal  206  by a data receiving circuit, the correlator  204  indicates a match only if the incoming data stream is equal to the target pattern (a wanted bit pattern or wake-up pattern). In all other cases it does not signal a match. 
     If no input signal is present, the correlator  204  is fed with noise samples from the receiver front-end. These noise samples are uncorrelated. Due to counting statistics, it is possible that the noise from the receiver front end exactly matches the wanted bit pattern, which results in the correlator  204  signalling a match. Such an event is called a false alarm, as the correlator  204  signals a match even though there was no wanted input signal. 
     Returning to  FIG. 1 , when a target pattern is identified in the received input signal, the data receiving circuit  135  of the remote transceiver circuit  120  may start the controller circuit  145  to process the received data stream to, for example, check encryption information. The micro-controller system requires much more current than the LF active receiver  125  alone. If the device is woken up by a false alarm, the remote transceiver circuit  120  consumes energy unnecessarily. This is undesirable, especially for a car key, in which excellent energy management is required because the device is ideally operated with a single battery for many years. 
     The average false alarm rate (FAR) for a correlator such as that described with reference to  FIG. 2  with n-bits can be calculated according to the following equation (assumption: binary input values with normal distribution, equi-probable 1&#39;s &amp; 0&#39;s, uncorrelated samples, and 1 sample per bit): 
     
       
         
           
             
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     One option for improving (reducing) the false alarm rate is therefore to increase the number of bits (n) in the target pattern. However, in order to minimize power consumption by the vehicle base station, and so maintain the battery of the vehicle, there is a conflicting requirement to minimize the number of bits in the target pattern and so decrease the length of the LF polling signal that is periodically transmitted by the vehicle. A polling system transmitting 24-32 bit patterns typically drains a car battery in 2 weeks, but produces acceptable performance at the car key. It is desirable for the target pattern to be reduced to 8, 10 or 12 bits, or fewer, for example, in order for the duration of the car battery to be improved. However, in one example, 100 false alarms per hour were detected by a car key using the pattern detection unit of  FIG. 2  when the target pattern was reduced to a 7 bit pattern. Such a rate of false alarms causes unacceptably high power loss by the key. 
     Another way to improve (reduce) the false alarm rate of the pattern matching unit is to increase the number of samples for a target pattern with a given number of bits. This means a significant reduction for the false alarm rate as can be seen in the following equation (assumption: binary input values with normal distribution, equi-probable 1&#39;s &amp; 0&#39;s, uncorrelated samples, and 2 samples per bit): 
     
       
         
           
             
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     This improvement in false alarm rate comes at the cost of a higher required signal to noise ratio for the LF-receiver  125 , which reduces the effective sensitivity. However, if this sensitivity reduction is acceptable for the application, then this method may be used to reduce the false alarm rate. The loss in sensitivity is proportional to the number of samples used per bit. 
       FIGS. 3 and 4  illustrate improved pattern detection units  300 ,  400  in which the numbers of samples per bit is increased. The pattern detection units  300 ,  400  differ from that described above with respect to  FIG. 2  in that they each comprise a correlator that is configured to compare a target pattern and two or more of the plurality of samples of each bit of the input signal from the shift register, and to determine whether the input signal matches the target pattern based on the comparison. 
     The specific arrangements of the pattern detection units  300 ,  400  are discussed separately below with respect to  FIGS. 3 and 4 . 
     Regarding  FIG. 3 , the pattern detection unit  300  differs from that described previously with reference to  FIG. 2  in that the correlator  304  comprises a first plurality of bit comparison units  312   a - n  and a second plurality of bit comparison units  316   a - n.  The first and second bit comparison units  312   a - n,    316   a - n  are arranged in pairs such that each first bit comparison unit  312   a - n  is associated with a corresponding second bit comparison unit  316   a - n.  Each pair of bit comparison units  312   a - n,    316   a - n  compares, in parallel, two different samples in a particular sample-register-group  313   a - n  in the shift register  302  with a particular bit-value of the target pattern. The effect of the arrangement is that, for the majority of the time (a factor of (m-1)/m), the pair of bit comparison units  312   a - n,    316   a - n  processes, in parallel, two different samples associated with the same bit. In this way, the two different samples are compared with a particular bit-value of the target pattern. 
     In this example, a first set of samples comprises a sample taken from every sample-register-group. The first set of samples is provided to first input terminals of respective first bit comparison units  312   a - n.  A second input terminal of each first bit comparison unit  312   a - n  is configured to receive a respective bit-value of the n-bit target pattern. In this way, each one of the first bit comparison units  312   a - n  is able to compare one sample of a particular sample-register-group in the shift register with a corresponding bit-value of the target pattern and provide a bit-comparison value at an output terminal. A second set of samples comprises another sample taken from every sample-register-group. The second set of samples is provided to first input terminals of respective second bit comparison units  316   a - n.  The first and second sets of samples provide pairs of samples from each sample-register-group. The first set of samples comprises different samples to the second set of samples. A second input terminal of each second bit comparison unit  316   a - n  is configured to receive a respective bit-bit value of the n-bit target pattern. In this way, each one of the second bit comparison units  312   a - n  is also able to compare one sample from a particular sample-register-group in the shift register with a corresponding bit-value of the target pattern and provide a bit-comparison value at an output. The bit-comparison values indicate whether a sample matches a corresponding bit-value of the target pattern. 
     The code comparison unit  314  has an output terminal and a plurality of input terminals connected to outputs of the respective first and second pluralities of bit comparison units  312   a - n,    316   a - n.  The code comparison unit  314  is configured to receive the bit-comparison values from each of the bit comparison units  312   a - n,    316   a - n  and determine a match indication signal that is indicative of whether, overall, the first and second sets of samples (two samples in every sample-register-group) match the target pattern. 
     In this way, the correlator is configured to compare the target pattern to one of the plurality of samples from each sample-register-group and, also, to compare the target pattern to another of the plurality of samples from each sample-register-group in order to compare the target pattern and two of the plurality of samples of each bit in the shift register. For example, the first bit of the target pattern is compared with the first and second samples from the first sample-register-group  313   a,  and the n th  bit of the target pattern is compared with the first and second samples from the n th  sample-register-group  313   n,  etc. The shift register  302  and correlator  304  may operate with a synchronised clock cycle. The correlator is therefore able to, in one clock cycle, compare a target pattern with two or more of the plurality of samples of each bit. As the input signal is shifted through the shift register  302 , the samples compared by the correlator  304  evolve from cycle to cycle. 
     In this example, the two samples compared by each pair of bit comparison units  312   a - n ,  316   a - n  are consecutive samples in a sample-register-group. This can provide particularly good performance in the presence of interference or a noise signal. Alternatively, the two samples compared by each pair of bit comparison units  312   a - n,    316   a - n  could be non-consecutive samples. 
     The shift register  302  of the pattern detection unit  300  differs from that described previously with reference to  FIG. 2  in that the n th  (last) sample-register-group  313   n  includes two sample registers instead of the one that is in  FIG. 2 . Therefore, the shift register  302  of  FIG. 3  comprises (n-1)*m+2 sample registers in order to hold (n-1)*m+2 samples of n-bits. Again, each bit of the input signal is oversampled by a factor m. 
     The pairs of bit comparison units  312   a - n,    316   a - n  of  FIG. 3  are examples of a set of bit comparison units that comprises a plurality of bit comparison units. In other examples, the set of bit comparison units may comprise three or more bit comparison units for each sample-register-group  313 . Each bit comparison unit in a set may compare respective samples from a sample-register-group with a particular bit-value of the target pattern. 
     Regarding  FIG. 4 , the pattern detection unit  400  comprises a shift register  402 , bit comparison units  412   a - n  and a code comparison unit  414  that are similar to those described previously with reference to  FIG. 2 . The n th  (last) sample-register-group  313   n  includes a single sample register. The pattern detection unit  400  differs from that described with reference to  FIG. 2  in that the correlator  404  further comprises a sequence detector  420 , which may also be referred to as a run-length detector. Example implementations of the sequence detector are discussed below with reference to  FIGS. 5 a    to  5   c.    
     Returning to  FIG. 4 , the sequence detector  420  is configured to determine whether the input signal matches the target pattern based on a plurality of match indication signals from the code comparison unit  414 . The plurality of match indication signals may be determined for consecutive, or different, clock cycles. 
     In this way, the correlator  404  is configured to compare the target pattern with one of the plurality of samples of each bit and, subsequently, to compare the target pattern to another of the plurality of samples of each bit. Therefore, the correlator  404  can compare the target pattern with two of the plurality of samples of each bit from the shift register. The shift register  402  and correlator  404  may operate with a synchronised clock cycle. The correlator is therefore able to, in one clock cycle, compare the target pattern with a first of the plurality of samples that is representative of each bit and, in a subsequent clock cycle, to compare the target pattern with a second of the plurality of samples that is representative of each bit. In this way, the correlator  404  can determine whether or not the input signal matches the target pattern based on such comparisons for two or more clock cycles. 
     The pattern detection unit  400  of  FIG. 4  provides an efficient way to achieve the same or similar effect to the pattern detection unit of  FIG. 3 , but with almost no additional hardware effort when compared with  FIG. 2 . Instead of duplicating the number of bit comparison units in the correlator  404 , the match indication signal that is provided as an output signal of the code comparison unit  414  is processed multiple times with a sequence, or run-length, detector  420 . In this example, a pattern match is only signalled if the match indication signal that is provided by the code comparison unit correlator determines a match for 2 consecutive cycles. 
     In both the examples described above with reference to  FIGS. 3 and 4 , a match may be determined by the correlator  304 ;  404  in response to each bit of the target pattern matching all of the plurality of samples of a corresponding bit-value of the input signal from the shift register. In  FIG. 3 , the plurality of sample-values are processed in parallel using information stored in a plurality of sample registers in each sample-register-group. In  FIG. 4 , the plurality of sample-values are processed sequentially, over time, using information stored in a single sample register in each sample-register-group. 
     The correlator  304 ;  404  may be configured to compare the target pattern to consecutive samples in the shift register of each bit of the input signal. This can simplify operation of the device. 
     The correlator  304 ;  404  may be configured to compare the target pattern to only two (rather than more than two) of the plurality of samples of each bit of the input signal in the shift register. This has been found to provide a good trade-off between reduced sensitivity and a decrease in false wake-up events for some car key applications. 
     The pattern detection unit  300 ;  400  may optionally comprise a memory for storing the target pattern. In such examples, the memory is operatively connected to the correlator  304 ;  404  for providing the target pattern to the correlator  304 ;  404 . 
     A further advantage of the pattern detection units  300 ;  400  of  FIGS. 3 and 4  is the possibility to switch between a first-mode-of-operation and a second-mode-of-operation. The first-mode-of-operation may be a reduced-false-alarm-rate mode of operation, which can provide the functionality described with reference to  FIG. 3 or 4 . The second-mode-of-operation may be a standard mode of operation, which can provide the functionality described with reference to  FIG. 2 . In this way, in the first-mode-of-operation, the correlator is configured to compare the target pattern with two or more of the plurality of samples of each bit of the input signal from the shift register in order to determine whether the input signal matches the target pattern. In the second-mode-of-operation, the correlator is configured to compare a target pattern with only one of the plurality of samples of each bit of the input signal from the shift register in order to determine whether the input signal matches the target pattern. 
     The pattern detection units  300 ;  400  of  FIGS. 3 and 4  may include a controller (not shown) that can set the mode of operation. The controller can set the mode of operation based on user input, for example when configuring the pattern detection unit, or can be set automatically based on pattern length, as discussed below. The controller may also be configured to select one of a plurality of target patterns for matching. For example, if multiple target patterns are to be used, then the pattern detection unit  300 ,  400  can include one correlator  304 ,  404  per pattern, such that the multiple correlators share a common shift register  302 ,  402 . The controller (not shown) can enable one or more of the multiple different target patterns based on a use case (e.g. one pattern for PKE and one for PKG). 
     This functionality can allow a device that includes the pattern detection unit of  FIG. 3 or 4  to be configured according to its particular requirements, either in: (i) the standard mode-of-operation with a higher false wake-up rate but excellent sensitivity, or (ii) the reduced-false-alarm-rate mode of operation with improved false wake-up rate and moderate sensitivity loss. This functionality can be particularly beneficial if the wake-up pattern length is configurable, and multiple wake-up patterns are supported simultaneously by the pattern detection unit. In this way it can be possible to activate the false wake-up improvement only for one very short wake-up pattern, while at the same, another longer wake-up pattern can be searched with full sensitivity. That is, a pattern detection unit can apply the first-mode-of-operation for a first instance of a wake-up pattern, and can apply the second-mode-of-operation for a second instance of a wake-up pattern 
     Another method for reducing false wake up events is to use a signal monitor to assess whether a reasonably strong signal is available before a wake-up pattern matching process is started, for example by a pattern detection unit. However, such kind of signal strength indicators may result in a loss in sensitivity and they are prone to interferers. Furthermore, such a signal strength indicator might require a specific protocol (e.g. an unmodulated burst signal in front of the protocol) for reliable detection, and can consume a large amount of current. Advantageously, the use of a pattern detection unit such as that described with reference to  FIG. 3  or  FIG. 4  results in improved implementation simplicity, configurability and sensitivity loss compared to a system that uses a signal monitor. 
       FIGS. 5 a  to 5 c    illustrate three example implementations of sequence detectors for use in the pattern detection unit of  FIG. 4 . Each sequence detector  520   a;    520   b;    520   c  has an input terminal  521   a;    521   b;    521   c  and an output terminal  523   a;    523   b;    523   c.  The input terminal  521   a;    521   b;    521   c  of each sequence detector  520   a;    520   b;    520   c  is configured to receive a match indication signal from the code comparison unit. An output signal at the output terminal  523   a;    523   b;    523   c  of each sequence detector  520   a;    520   b;    520   c  is indicative of whether the input signal matches the target pattern. 
       FIG. 5 a    illustrates a sequence detector  520   a  that comprises a delay buffer  522  and an AND gate. The delay buffer  522  is configured to receive the match indication signal from the code comparison unit and to provide a buffered match indication signal  525 . In this example, the delay buffer  522  applies a time delay that corresponds to the over-sampling frequency that is applied by the shift register (not shown). Therefore, the buffered match indication signal  525  is a delayed version of the match indication signal received at the input terminal  521   a.    
     The AND gate has a first input terminal, a second input terminal and an output terminal. The first input terminal of the AND gate is configured to receive the match indication signal from the code comparison unit. The second input terminal of the AND gate unit is configured to receive the buffered match indication signal from the delay buffer  522 . The output terminal of the AND gate is connected to the output terminal  523   a  of the sequence detector  520   a.  The effect of the sequence detector  520   a  is that the output signal  523   a  is only set to a value that is indicative of a match if the pattern is successfully matched for two consecutive samples. In this way, false alarm signals, in which a single set of samples matches, are ignored. 
       FIG. 5 b    illustrates a sequence detector  520   b  that comprises first and second sequence detector blocks  526 ,  528 . The first sequence detector block  526  is similar to the sequence detector  520   a  described with reference to  FIG. 5 a    such that a first-block-output-signal  527  of the first sequence detector block  526  is only set to a ‘1’ if the pattern is successfully matched for two consecutive samples. 
     An input terminal of the second sequence detector block  528  is connected to the first sequence detector block  526  such that it receives the first-block-output-signal  527 . The second sequence detector block  528  comprises a delay buffer  529  and an OR gate  530 . The delay buffer  529  is configured to receive the first-block-output-signal  527  and to provide a buffered-first-block-output-signal  531 . In this example, the delay buffer  529  applies a time delay that corresponds to the over-sampling frequency that is applied by the shift register (not shown). Therefore, the buffered-first-block-output-signal  531  is a delayed version of the first-block-output-signal  527 . The OR gate  530  receives the buffered-first-block-output-signal  531  and the first-block-output-signal  527  as input signals. An output terminal of the OR gate  530  is connected to the output terminal  523   b  of the sequence detector  520   b.    
     The sequence detector  520   b  of  FIG. 5 b    filters out single matches but maintains the “match count” (or “width”) of multiple matches so that the signal provided at the output terminal  523   b  matches the number of cycles that would be obtained for a positive identification using the pattern detection unit of  FIG. 2 . This can be important in receivers where the shape of the post-processed match signal (or “wakeup decision”) is important in the subsequent signal processing. 
     In this way, the sequence detector  520   b  sets an output signal (provided at the output terminal  523   b ) as a matching-value (‘1’) in response to two consecutive match indication signals being indicative of the input signal matching the target pattern. The sequence detector  520   b  maintains the output signal as the matching-value (‘1’) for the same number of consecutive clock cycles that the match indication signals are indicative of the input signal matching the target pattern. 
       FIG. 5 c    illustrates a sequence detector  520   c  that comprises a first delay buffer  532 , a second delay buffer  534 , a third delay buffer  538 , a first OR gate  540 , a second OR gate  542 , an AND gate  544  and a multiplexor  546 . 
     The multiplexor  546  has a first input terminal  548 , which receives a first input signal indicative of the result of: (a match for the earliest comparison) AND (a match for one or more of a plurality of later comparisons). In this example, the plurality of later comparisons comprise two later comparisons. For an n th  comparison, this can be expressed as: (n-2) AND ((n-1) OR n). The multiplexor  546  also has a second input terminal  550 , which receives a second input signal indicative of whether or not a match has been identified for at least one of: a current comparison, and one of a plurality of earlier comparisons). In this example, the plurality of earlier comparisons again comprises two earlier comparisons. For an n th  comparison, this can be expressed as: n OR (n-1) OR (n-2). 
     The output signal of the multiplexor  546  is provided as a feedback signal to a control terminal  552  of the multiplexor  546  via the third delay buffer  538 . In this way, the output signal of the sequence detector  520   c  controls which of the input signals provided to the multiplexor  546  is provided as an output signal of the multiplexor, and in turn an output signal of the sequence detector  520   c.  When the output signal of the multiplexor  546  is low, the first input terminal  548  is connected to the output terminal of the multiplexor  546 . In this way, the signal at the first input terminal  548  is used to trigger the start of an identified match. When the output signal of the multiplexor  546  is high following the identification of a match, the second input terminal  550  is connected to the output terminal of the multiplexor  546 . In this way, the signal at the second input terminal  550  is used to control the duration with which the output signal of the sequence detector  520   c  is maintained high. 
     The sequence detector  520   c  can therefore recognize, or compensate for, a “gap in the middle” situation in which a sequence of matching samples appears to contain a sample in which a match is not present due to corruption of the signal. 
     It will be appreciated that other approaches also possible, for example to provide a minimum (yet variable) latency. 
     In this way, the sequence detector  520   c  sets an output signal (provided at the output terminal  523   c ) as a matching-value (‘1’) in response to two or more match indication signals from a group-of-match-indication-signals being indicative of the input signal matching the target pattern. The group-of-match-indication-signals includes a plurality of, or three or more, match indication signals. In the example of  FIG. 5 c   , the group-of-match-indication-signals includes three match indication signals. The sequence detector  520   c  then maintains the output signal as the matching-value (‘1’) for the number of clock cycles that are represented by the group-of-match-indication-signals. 
       FIG. 6  illustrates, on the left hand side, a timing diagram table representative of example sample-values that pass through a shift register  600 . The example sample-values are based on input signals that are indicative of one of 3 different scenarios, as discussed below. A truth table illustrating respective output values  660 ,  662 ,  664 ,  666  for the sequence detectors discussed above with reference to  FIGS. 5 a  to 5 c    is also illustrated in  FIG. 6 , on the right-hand side. An output value  660 ,  662 ,  664 ,  666  is set as ‘1’ if a match is found, and set as ‘0’ if a match is not found. 
     The input signals relate to: (i) a normal alarm condition  640 , in which a train of samples correctly match a target pattern  602 , (ii) a false alarm condition  642 , in which a single sample happens to match the target pattern  602  due to statistical noise, and (iii) an alarm condition that is partly corrupted by noise  644 , in which an input signal is received that matches the target pattern  602 , although some samples are corrupted. 
     For each respective scenario  640 ,  642 ,  644 , each row of the table illustrates the contents of the shift register  600  at a particular clock cycle. An oversampling ratio of 4 is used, and the wake-up pattern has a reduced length of three bits (sequence A,B,C) for brevity. A dot in the signal represents any random/unknown bit value. Subsequent clock cycles are illustrated as subsequent rows. As can be seen by comparing the data in the rows, the contents of the shift register  600  are shifted from left to right incrementally with each clock cycle for each scenario  640 ,  642 ,  644 . 
     Three active-sample-registers  652   a - c  are identified at spaced apart locations in the shift register  600 . Each of these active-sample-registers  652   a - c  represent a sample register in a sample-register-group that provides an output for processing by a code comparison unit. As will be appreciated from the description of  FIGS. 2 and 5   a  to  5   c , the information in these active-sample-registers  652   a - c  is used to determine the respective output values  660 ,  662 ,  664 ,  666 . 
     The output values  660 ,  662 ,  664 ,  666  shown in  FIG. 6  are as follows:
         the first column of output values  660  are representative of the output of the match detection unit of  FIG. 2 ;   the second column of output values  662  are representative of the output of the match detection unit of  FIG. 4  using the sequence detector of  FIG. 5   a;      the third column of output values  664  are representative of the output of the match detection unit of  FIG. 4  using the sequence detector of  FIG. 5 b   ; and   the fourth column of output values  666  are representative of the output of the match detection unit of  FIG. 4  using the sequence detector of  FIG. 5   c.          

     Normal Alarm Condition 
     For the input signal indicative of a normal alarm condition  640 , the input signal progresses through the shift register with multiple successive samples indicative of each bit. The state of the shift register  600  for four sequential clock cycles, or time steps  671 - 674 , of the normal alarm condition  640  are illustrated. 
     In the second time step  672 , the sample-values in the active-sample-registers  652   a - c  match the target pattern  602 . Therefore, the output of the match detection unit of  FIG. 2  is set as a ‘1’ to indicate a match, as shown in column  660 . 
     In the third time step  673 , the sample-values in the active-sample-registers  652   a - c  again match the target pattern  602 . Therefore, the output of the match detection unit of  FIG. 2  is still set as a ‘1’ to indicate a match, as shown in column  660 . Also, since this is the second immediately consecutive time step in which the contents of the active-sample-registers  652   a - c  matches the target pattern  602 , the outputs of the sequence detectors of  FIGS. 5 a , 5 b  and 5 c    are also set as a ‘1’ to indicate a match, as shown in columns  662 ,  664 ,  666 . 
     In the fourth time step  674 , the sample-values in the active-sample-registers  652   a - c  no longer match the target pattern  602 . Therefore, the output of the match detection unit of  FIG. 2  and the sequence detector of  FIG. 5  are set as a ‘0’ to indicate that there is not a match, as shown in columns  660  and  662 . However, the outputs of the match detection units of  FIGS. 5 b  and 5 c    are maintained as a ‘1’ to indicate a match, as shown in columns  664 ,  666 . In this way, the length of time that the outputs of the match detection units of  FIGS. 5 b  and 5 c    are kept as ‘1’ corresponds to the number of consecutive clock cycles for which a match between the values in the active-sample-registers  652   a - c  and the target pattern  602  was detected. 
     False Alarm Condition 
     For the input signal indicative of a false alarm condition  642 , a single instance of a matching code passing through the shift register  600 . This matching code may be present in the shift register  600  due to statistical effects. The state of the shift register  600  for four sequential clock cycles, or time steps  681 - 684 , of the false alarm condition  640  are illustrated. 
     The pattern matching unit of  FIG. 2  identifies a match at a third time step  683  when the contents of the active-sample-registers  652   a - c  in the shift register  600  matches the target pattern  602 , as shown in column  660 . None of the sequence detectors of  FIGS. 5 a  to 5 c    detect a match because there are not two successive time steps in which the contents of the active-sample-registers  652   a - c  match the target pattern  652 . This is shown in columns  662 ,  664  and  666 . Therefore, in contrast to the processing by the match detection unit of  FIG. 2  (column  660 ), the match detection units of  FIGS. 5 a  to 5 c    (columns  662 ,  664 ,  666 ) do not raise a false alarm for the set of signals identified with reference  642 . 
     Corrupted Alarm Condition 
     For the input signal indicative of an alarm condition partly corrupted by noise  644 , the input signal progresses through the shift register  600  with four successive samples indicative of each bit, in which one of the samples has been effected by noise ‘x’. The state of the shift register  600  for six sequential time steps  691 - 696  of the alarm condition partly corrupted by noise  644  are illustrated. This is a case where a valid wakeup should be determined because the input signal nearly matches the target pattern  602  for three consecutive time steps, expect one sample is corrupted due to noise. 
     The pattern matching unit of  FIG. 2  identifies that the contents of the set of sample registers  652   a - c  in the shift register  600  matches the target pattern  602  in the second and fourth time steps  692 ,  694 , but not the third time step  693 , in which the sample-value in one of the active-sample-registers  652   a - c  is corrupted. This is shown in column  660  of  FIG. 6 . 
     The sequence detectors of  FIGS. 5 a  and 5 b    fail to detect a match due to the noise present in the signal in the third time step  693 , as shown in columns  662  and  664 . This is because a match is not detected for two consecutive time steps. 
     The sequence detector of  FIG. 5 c    indicates a match condition in the third to sixth time steps  693 - 696  in response to the contents of the active-sample-registers  652   a - c  in the shift register  600  matching the target pattern  602  in the second and fourth time steps  692 ,  694 , which are separated by the third time step  693  in which the samples in the active-sample-registers  652   a - c  are corrupted by noise. This is shown in column  666 . The match detection unit of  FIG. 5 c    can correctly identify a match in a noisy input signal because the processing for two out of three consecutive time steps identify a match. Also, the match detection unit of  FIG. 5 c    can set the length of time that the output of the match detection units is kept as ‘1’ such that it corresponds to the number of consecutive clock cycles for which a match between the values in the active-sample-registers  652   a - c  and the target pattern  602  is likely to have occurred. 
       FIG. 7  illustrates a method  700  of detecting a pattern in an input signal, which can be performed using the pattern match detector described previously with reference to  FIG. 3  and  FIG. 4 . The method  700  comprises receiving  702  a multi-bit input signal at a shift register. The received multi-bit input signal is over-sampled  704  using the shift register such that each bit of the input signal is represented by a plurality of samples in the shift register. A target pattern is compared  706  with two or more of the plurality of samples of each bit of the input signal in the shift register. The two or more of the plurality of samples can be processed in the same clock cycle, using two sample registers within each group of sample registers, as discussed with reference to  FIG. 3 . Alternatively, the two or more of the plurality of samples can be processed using the output of a single sample register within each group of sample registers, over two clock cycles, as discussed with reference to  FIG. 4 . Based on the comparison, the method determines  708  whether the input signal matches the target pattern. 
     The systems and methods described above may, in general, be applied to all wired or wireless communication protocols, including biphase code. Biphase coding adds a level of complexity to the coding process but in return includes a way to transfer a frame data clock that can be used in decoding to increase accuracy. In biphase coding there may be a state transition in the message signal of every bit frame. This allows a demodulation system to recover the data rate and also synchronize to bit edge periods. With this clock information, the data stream can be recreated. 
     Manchester coding, which is a type of biphase coding, provides a means of adding the data rate clock to the message to be used on the receiving end. Manchester coding provides the added benefit of yielding an average DC level of 50%. This has positive implications in the demodulators circuit design as well as managing transmitted RF spectrum after modulation. This means that in modulation types where the power output is a function of the message such as amplitude modulation (AM), the average power is constant and independent of the data stream being encoded. 
     Manchester coding states that there will be a transition of the message signal at the mid-point of the data bit frame. What occurs at the bit edges depends on the state of the previous bit frame and does not have to produce a transition. A logical “1” is defined as a mid-point transition from low to high and a “0” is a mid-point transition from high to low. 
     The instructions and/or flowchart steps in the above figures can be executed in any order, unless a specific order is explicitly stated. Also, those skilled in the art will recognize that while one example set of instructions/method has been discussed, the material in this specification can be combined in a variety of ways to yield other examples as well, and are to be understood within a context provided by this detailed description. 
     In some example embodiments the set of instructions/method steps described above are implemented as functional and software instructions embodied as a set of executable instructions which are effected on a computer or machine which is programmed with and controlled by said executable instructions. Such instructions are loaded for execution on a processor (such as one or more CPUs). The term processor includes microprocessors, microcontrollers, processor modules or subsystems (including one or more microprocessors or microcontrollers), or other control or computing devices. A processor can refer to a single component or to plural components. 
     In other examples, the set of instructions/methods illustrated herein and data and instructions associated therewith are stored in respective storage devices, which are implemented as one or more non-transient machine or computer-readable or computer-usable storage media or mediums. Such computer-readable or computer usable storage medium or media is (are) considered to be part of an article (or article of manufacture). An article or article of manufacture can refer to any manufactured single component or multiple components. The non-transient machine or computer usable media or mediums as defined herein excludes signals, but such media or mediums may be capable of receiving and processing information from signals and/or other transient mediums. 
     Example embodiments of the material discussed in this specification can be implemented in whole or in part through network, computer, or data based devices and/or services. These may include cloud, internet, intranet, mobile, desktop, processor, look-up table, microcontroller, consumer equipment, infrastructure, or other enabling devices and services. As may be used herein and in the claims, the following non-exclusive definitions are provided. 
     In one example, one or more instructions or steps discussed herein are automated. The terms automated or automatically (and like variations thereof) mean controlled operation of an apparatus, system, and/or process using computers and/or mechanical/electrical devices without the necessity of human intervention, observation, effort and/or decision. 
     It will be appreciated that any components said to be coupled may be coupled or connected either directly or indirectly. In the case of indirect coupling, additional components may be located between the two components that are said to be coupled. 
     In this specification, example embodiments have been presented in terms of a selected set of details. However, a person of ordinary skill in the art would understand that many other example embodiments may be practiced which include a different selected set of these details. It is intended that the following claims cover all possible example embodiments.