Patent Publication Number: US-2023163940-A1

Title: Method for measuring and correcting multi-wire skew

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is a continuation of U.S. application Ser. No. 17/672,410 filed Feb. 15, 2022, naming Roger Ulrich, entitled “Method for Measuring and Correcting Multi-Wire Skew”, which is a continuation of U.S. application Ser. No. 16/903,001, filed Jun. 16, 2020, naming Roger Ulrich, entitled “Method for Measuring and Correcting Multi-Wire Skew”, which is a continuation of U.S. application Ser. No. 15/641,313, filed Jul. 4, 2017, naming Roger Ulrich, entitled “Method for Measuring and Correcting Multi-Wire Skew”, all of which are hereby incorporated herein by reference in their entirety for all purposes. 
    
    
     REFERENCES 
     The following prior applications are herein incorporated by reference in their entirety for all purposes: 
     U.S. Patent Publication 2011/0268225 of application Ser. No. 12/784,414, filed May 20, 2010, naming Harm Cronie and Amin Shokrollahi, entitled “Orthogonal Differential Vector Signaling” (hereinafter “Cronie I”). 
     U.S. Pat. No. 9,300,503, granted Mar. 29, 2016, of application Ser. No. 13/842,740, filed Mar. 15, 2013, naming Brian Holden, Amin Shokrollahi and Anant Singh, entitled “Methods and for Skew Tolerance in and Advanced Detectors for Vector Signaling Codes for Chip-to-Chip Communication”, hereinafter identified as [Holden I]; 
     U.S. Pat. No. 9,577,815, granted Feb. 21, 2017 ,of application Ser. No. 14/926,958, filed Oct. 29, 2015, naming Richard Simpson, Andrew Stewart, and Ali Hormati, entitled “Clock Data Alignment System for Vector Signaling Code Communications Link”, hereinafter identified as [Simpson I]. 
     U.S. Pat. No. 9,450,744, granted Sep. 20, 2016, of application Ser. No. 14/717,717, filed May 20, 2015, naming Richard Simpson and Roger Ulrich, entitled “Control Loop Management and Differential Delay Detection and Correction for Vector Signaling Code Communications Links”, hereinafter identified as [Simpson II]. 
     U.S. Pat. No. 9,596,109, granted Mar. 41, 2017, of application Ser. No. 14/253,584, filed Apr. 15, 2014, naming John Fox, Brian Holden, Ali Hormati, Peter Hunt, John D Keay, Amin Shokrollahi, Anant Singh, Andrew Kevin John Stewart, Giuseppe Surace, and Roger Ulrich, entitled “Methods and Systems for High Bandwidth Communications Interface” (hereinafter called “Fox I”) 
     U.S. Pat. No. 9,112,550, granted Aug. 18, 2015, of application Ser. No. 14/315,306, filed Jun. 25, 2014, naming Roger Ulrich, entitled “Multilevel Driver for High Speed Chip-to-Chip Communications” (hereinafter called “Ulrich I”); 
     U.S. Pat. No. 9,288,085, granted Mar. 15, 2016, of application Ser. No. 13/895,206, filed May 15, 2013, naming Roger Ulrich and Peter Hunt, entitled “Circuits for Efficient Detection of Vector Signaling Codes for Chip-to-Chip Communications using Sums of Differences”, hereinafter identified as [Ulrich II]. 
     U.S. Pat. No. 10,193,716, granted Jan. 29, 2019, of application Ser. No. 15/582,545, filed Apr. 28, 2017, 2014, naming Ali Hormati and Richard Simpson, entitled “Clock Data Recovery Utilizing Decision Feedback Equalization” (hereinafter called “Hormati I”); 
     U.S. Provisional Patent Application No. 62/464,597, filed Feb. 28, 2017, naming Ali Hormati and Kiarash Gharibdoust, entitled “Method for Measuring and Correcting Multiwire Skew” (hereinafter called “Hormati II”). 
     U.S. Provisional Patent Application No. 62/509,714, filed May 22, 2017, naming Armin Tajalli and Ali Hormati, entitled “Multi-modal Data-driven Clock Recovery Circuit” (hereinafter called “Taj alli I”). 
     U.S. Pat. No. 9,100,232, issued Aug. 4, 2015, naming Amin Shokrollahi, Ali Hormati, and Roger Ulrich, entitled “Method and Apparatus for Low Power Chip-to-Chip Communications with Constrained ISI Ratio”, hereinafter identified as [Shokrollahi 1]. 
     FIELD OF THE INVENTION 
     The present embodiments relate to communications systems circuits generally, and more particularly to measurement and reduction of differential signal arrival times for a received communications signal transmitted over a high-speed multi-wire interface used for chip-to-chip communication. 
     BACKGROUND 
     In modern digital systems, digital information is processed in a reliable and efficient way. In this context, digital information is to be understood as information available in discrete, i.e., discontinuous values. Bits, collection of bits, but also numbers from a finite set can be used to represent digital information. 
     In most chip-to-chip, or device-to-device communication systems, communication takes place over a plurality of wires to increase the aggregate bandwidth. A single or pair of these wires may be referred to as a channel or link and multiple channels create a communication bus between the electronic components. At the physical circuitry level, in chip-to-chip communication systems, buses are typically made of electrical conductors in the package between chips and motherboards, on printed circuit boards (“PCBs”) boards or in cables and connectors between PCBs. In high frequency applications, microstrip or stripline PCB traces may be used. 
     Common methods for transmitting signals over bus wires include single-ended and differential signaling methods. In applications requiring high speed communications, those methods can be further optimized in terms of power consumption and pin-efficiency, especially in high-speed communications. More recently, vector signaling methods have been proposed to further optimize the trade-offs between power consumption, pin efficiency and noise robustness of chip-to-chip communication systems. In those vector signaling systems, digital information at the transmitter is transformed into a different representation space in the form of a vector codeword that is chosen in order to optimize the power consumption, pin-efficiency and speed trade-offs based on the transmission channel properties and communication system design constraints. Herein, this process is referred to as “encoding”. The encoded codeword is communicated as a group of signals, typically communicated essentially in parallel over multiple wires or communications channels, from the transmitter to one or more receivers. At a receiver, the received signals corresponding to the codeword are transformed back into the original digital information representation space. Herein, this process is referred to as “decoding”. 
     Regardless of the encoding method used, the received signals presented to the receiving device are sampled (or their signal value otherwise recorded) at intervals best representing the original transmitted values, regardless of transmission channel delays, interference, and noise. The timing of this sampling or slicing operation is controlled by an associated Clock and Data Alignment (CDA) timing system, which determines the appropriate sample timing. Where the group of signals is communicated essentially in parallel over multiple wires or communications channels, variations in propagation delay over the multiple wires or channels can cause elements comprising one group of signals or codeword to be received at different times. This “skew” may, if uncorrected, prevent codewords from being received as coherent entities, and thus thwart decoding. 
     BRIEF DESCRIPTION 
     To reliably detect the data values transmitted over a communications system, a receiver accurately measures the received signal value amplitudes at carefully selected times. For vector signaling codes communicated essentially in parallel, this timing selection is comprised of two parts: accurate sampling of individual codeword elements received on individual wires or communications channels, and accurate interpretation of the entire received codeword, regardless of timing variations in reception of its component elements. 
     These differential propagation times across the vector signaling code codeword may be caused by variations in transmission path length or propagation velocity, and may be constant or vary over time. Identifying and correcting such differential arrival times or “skew” will increase the timing window for proper reception, thus improving received signal quality. Accurately measuring skew at the receiver is essential to subsequent skew correction, which as one example may be performed by introducing variable delays into the individual wire or symbol data paths prior to codeword decoding. 
    
    
     
       BRIEF DESCRIPTION OF FIGURES 
         FIG.  1    shows a system with a transmitter  110  communicating over channel  120  comprising a multi-wire bus having multiple wires  125  to receiver  130 . 
         FIG.  2    illustrates one embodiment of a receiver for the ENRZ code utilizing receive clocks derived from received data transitions. 
         FIG.  3    illustrates one embodiment of a Clock Recovery subsystem as used in the receiver of  FIG.  2   . 
         FIG.  4    is a block diagram of a skew detection system, in accordance with some embodiments. 
         FIG.  5    shows one embodiment of an adjustable delay element for a wire of the multi-wire bus, as used in the receiver of  FIG.  2   . 
         FIG.  6    is a block diagram of an exemplary sampler that may be used to provide data decisions and early/late indications, in accordance with some embodiments. 
         FIG.  7    is a block diagram of an alternative sampler that may be used to provide data decisions and early/late indications, in accordance with some embodiments. 
         FIG.  8    is a block diagram of a code sequence detection circuit, in accordance with some embodiments. 
         FIG.  9    is a block diagram of a logic circuit for generating wire delay adjustment enable signals, in accordance with some embodiments 
         FIG.  10    is a block diagram of a circuit for aggregating wire delays, in accordance with some embodiments. 
         FIG.  11    is a diagram of a receiver eye plot illustrating center-of-the-eye sampling. 
         FIG.  12    is a state diagram associating particular code transitions with wire transitions. 
         FIG.  13    is a block diagram of a method in accordance with some embodiments. 
     
    
    
     DETAILED DESCRIPTION 
     As described in [Cronie I], vector signaling codes may be used to produce extremely high bandwidth data communications links, such as between two integrated circuit devices in a system. Multiple data communications channels transmit symbols of the vector signaling code, acting together to communicate codewords of the vector signaling code. Depending on the particular vector signaling code used, the number of channels comprising a communications link may range from two to eight or more. Individual symbols, e.g. transmissions on any single communications channel, may utilize multiple signal levels, often three or more. 
     Embodiments may also apply to any communication or storage methods requiring coordination of multiple channels or elements of the channel to produce a coherent aggregate result. 
     Input Sampling Circuits 
     Conventional practice for a high-speed integrated circuit receiver includes terminating each data line (after any relevant front end processing such as amplification and frequency equalization) in a sampling device. This sampling device performs a measurement constrained in both time and amplitude dimensions; in one example embodiment, it may be comprised of a sample-and-hold circuit that constrains the time interval being measured, followed by a threshold detector or digital comparator that determines whether the signal within that interval falls above or below (or in some embodiments, within bounds set by) a reference value. In another embodiment, it may be comparable to an edge-triggered flip-flop, sampling the state of its input in response to a clock transition. Subsequently, this document will use the term sampling device, or more simply “sampler” to describe this receiver input measurement function as it implies both the time and amplitude measurement constraints, rather than the equivalent but less descriptive term “slicer” synonymously used in the art. 
     The receiver “eye plot” as illustrated in  FIG.  11    graphically illustrates input signal values that will or will not provide accurate and reliable detected results from such measurement, and thus the allowable boundaries of the time and amplitude measurement windows imposed on the sampler. 
     A Clock Data Alignment or CDA circuit supports such sampling measurements by extracting timing information, either from the data lines themselves or from dedicated clock signal inputs, and utilize that extracted information to generate clock signals to control the time interval used by the data line sampling device(s). The actual clock extraction may be performed using well known circuits such as a Phase Locked Loop (PLL) or Delay Locked Loop (DLL), which in their operation may also generate higher frequency internal clocks, multiple clock phases, etc. in support of receiver operation. These sampling clocks are “aligned” with the data to be sampled to optimize the quality and accuracy of the sampled results, typically by configuring the CDA so that sampling occurs when the signal to be sampled is stable, the so-called “center of eye” timing intervals identified by A and D in  FIG.  11   . 
     System Environment 
       FIG.  1    illustrates an exemplary system, in accordance with some embodiments. As shown,  FIG.  1    includes a transmitter  110  that receives source data S 0 -S 2    100  and Clk  105 , and an encoder  112  that encodes the information for transmission over a channel  120  including a multi-wire bus having multiple wires  125  via line driver  118 .  FIG.  1    further includes a receiver  130  including a detector  132  and in some embodiments includes a decoder  138 , if needed, for producing receive data R 0 -R 2    140  and a receive clock Rclk  145 . 
     For purposes of description and without implying limitation, the following examples assume a communications system environment comprising interconnection of one transmitting and one receiving integrated circuit device via four wires of essentially equal path length and transmission line characteristics, at a signaling rate of 25 Gigabit/second/wire, equivalent to a transmission unit interval of 40 picoseconds. The Hadamard 4×4 vector signaling code of [Cronie I], also called [Fox I] the Enhanced NRZ or ENRZ code, is used to communicate three data values (each carried by a sub-channel of the vector signaling code, as subsequently described) over four wires, with a receive clock derived from transitions of the received data values. Other embodiments may include interconnection of one transmitting and one receiving integrated circuit device via six wires of essentially equal path length and transmission line characteristics, at a signaling rate of 25 Gigabit/second/wire, equivalent to a transmission unit interval of 40 picoseconds. The Glasswing vector signaling code of [Shokrollahi I], also called the 5b6w, Chord NRZ or CNRZ code, is used to communicate five data values (each carried by a sub-channel of the vector signaling code, as subsequently described) over six wires, with a receive clock derived from transitions of the received data values. 
     It is assumed known methods for transmission pre-emphasis such as using Finite Impulse Response filtering, and receiver Continuous Time Linear Equalization (CTLE) and Decision Feedback Equalization (DFE) will be incorporated to provide adequate receiver signal quality. 
     Example communications channels may include skew, such as might be induced by variations in printed circuit board composition or wire routing, but for descriptive purposes the magnitude of this skew is assumed to be less than one unit interval. Embodiments correcting that amount of skew will in general address maximization of horizontal eye opening in a system in which the eyes are already partially open. Other embodiments may utilize the training sequences and methods described in [Hormati II] to achieve open eyes in a channel with larger amounts of skew, and further embodiments combining the described skew corrections with other known skew correction methods may be applied to environments with substantially greater amounts of skew, thus no limitation is implied. 
     One example embodiment of a communications receiver for vector signaling code is shown in  FIG.  2   . In that block diagram, four data wire inputs W 0  through W 3  from the multi-wire bus are each processed by a delay element  200 , the resulting signals then passed to Continuous Time Linear Equalizers (CTLE)  210  for optional amplification and/or frequency compensation. It is also common for CTLE circuits to be configured to provide additional high-frequency gain (also known as high frequency “peaking”) to compensate for frequency-dependent transmission medium losses. The resulting processed wire signals are presented to Multi-input comparators (MICs)  220 , which decode the sub-channels of the vector signaling code MIC 0 -MIC 2 . These sub-channel outputs are sampled via sampling circuits  230  at time intervals determined by Clock Recovery (CDA) subsystem  300 , producing sub-channel  1 - 3  data outputs. As shown in  FIG.  2   , the receiver may operate in multiple phases and may include multiplexors  240  to sequentially output the sampled data for each phase. In an alternative embodiment, processing by delay element  200  occurs after CTLE  210  and before MIC  220 . 
     In some embodiments, additional samplers are provided for some or all sub-channel outputs, to facilitate timing analysis and/or management. As one example, such an additional sampler may be triggered using an earlier or later clock to detect signal transitions and thus optimize CDA operation. As another example, such an additional sampler may be configured with an adjustable offset slicer voltage, to facilitate measurement of vertical eye opening. The slicer offset voltages may additionally incorporate DFE correction factors to provide both data and clock edge information, as described in [Hormati I] and in  FIG.  6   .  FIG.  6    includes at least one stage of speculative DFE  650  supported by two data samplers performing concurrent time-sampling operations at two different amplitude thresholds. As shown, the data samplers include comparators  620  generating comparator output slicing the signal received from CTLE  210  and sampling the comparator output according to the sampling clock. One comparator output is chosen as the data value D and the other is chosen as an error signal in the form of an early late indicator, according to the most recent data decision. This signal is referred to herein as a signal skew characteristic. Using data value history  640 , a pattern detection block  670  may identify patterns having transitions, and responsively use the skew measurement signal (shown as an early/late indication E/L) to identify wires involved in the transition and to responsively increment or decrement a corresponding wire-specific counter. Such selections of the data signal and early/late skew measurement signal may be performed using multiplexors  630  and  660 . [Tajalli I] additionally describes how clock edge information from two or more sub-channels may be combined, and how skew measurement information from sub-channels not experiencing a transition may be filtered from such combined results, providing improved timing feedback to the CDA subsystem. 
       FIG.  7    illustrates an alternative sampling mechanism that may be used in some embodiments. As shown, the output of MIC 0   610  is processed by CTLE  210  as above, the output of which is sampled according to data sampler  702  and transition sampler  704 . In such embodiments, the data signal from CTLE  210  may be sampled at a double rate. In at least one embodiment, the data may be sampled twice according to sampling clocks ck_ 000  and ck_ 180  provided by sampling clock block  706 . In some embodiments, the 180 degree out-of-phase clocks may be used in which one clock samples “middle of the eye” (see  FIG.  11   ), while the other is used to sample the transition regions to obtain an early/late indication as a skew measurement signal. Alternatively, a full rate clock may be used while data is transmitted twice, effectively halving the data rate. In such embodiments, only one sampler may be used, the output of which alternates between a data sample and an edge sample. In such embodiments, a full-rate data transmission may be initiated or resumed after the half-rate skew training period has been completed. Further measurements and adjustments made then be performed using the full-rate methods and circuits described herein. 
     Differential arrival times or “skew” of the various wire signals may delay or interfere with proper detection of the vector signaling code. This skew may be caused by variations in transmission path element length or propagation velocity, and may be constant or vary over time. Thus, accurately measuring skew at the receiver is helpful for subsequent skew correction, which as one example may be performed by introducing variable delays into the individual symbol data paths prior to codeword decoding. In another example, measured skew values may be conveyed back to the transmitter where wire-specific timing adjustments may be made to pre-compensate for skew as seen by the receiver. 
     Skew Adjustment and Compensation 
     Skew elimination includes incrementally offsetting individual wire signals in time to compensate for arrival time variations. Some methods for skew measurement, as one example, that of [Hormati II], also uses interactive adjustment of wire delays as part of their test and analysis procedure. 
     At the receiver, wire delay embodiments may incorporate known art methods in either the analog or digital domain utilizing variable delay elements, time adjustable sample-and-hold elements, adjustable FIFO buffers, etc. 
     [Hormati II] describes a low insertion loss Resistor/Capacitor filter inserted into each received wire signal, which is configurable for introducing small amounts of adjustable delay with minimal impact on signal amplitude. One such embodiment of a delay element  200  is shown in  FIG.  5   . Shown in the figure is a controllable delay circuit for a single wire, and each wire of the multi-wire bus may be configured with a similar circuit  200  to provide an adjustable amount of signal skew. Transistors  501 ,  502 , and  503  may be enabled respectively by Skew control inputs B 0 , B 1 , B 2  to increase the Wire Input nodes&#39;s capacitance to ground by amounts determined by capacitors C 0 , C 1 , C 2 . This added node capacitance, in association with the source and termination impedances of the incoming transmission line, introduces an increased delay into the wire signal. An alternative embodiment introduces the delay element  200  elsewhere in the wire signal path; as a non-limiting example, at the output of each CTLE stage rather than at the wire inputs of the receiver. 
     In one particular embodiment, C 0 , C 1 , C 2  values of 5 fF, 10 fF, 20 fF allows use of a binary skew control codeword that specifies binary increments of capacitance to be added, up to an additional aggregate capacitive value of 35 femtoFarads, corresponding to approximately 5 picoseconds of additional delay. In another embodiment, capacitors of equal value may be used, and the control word is implemented as a thermometer codeword rather than a binary codeword. As a side effect, the added capacitance also slightly degrades high frequency response, with the same embodiment experiencing 1.5 dB degradation in return loss (also generally known as Si&#39;) at 12.5 GHz, when configured to introduce the maximum 5 psec delay. 
     Another embodiment capable of greater skew correction samples the wire signals using an analog track-and-hold or sample-and-hold circuit acting as Delay element  200 , at skew-modified times during which the individual wire signals are stable, with sampling  140  of the resulting MIC sub-channel outputs using Sampling Clock being deferred by Clock Recovery system  150  until at least the latest of those skew-modified times. Some embodiments may utilize a series of such sampled delay elements per wire to provide increased delay time or reduced sampling signal artifacts. 
     Skew may also be eliminated by adjusting individual wire transmission times, as described by [Ulrich I]. Such an approach communicates information gathered by the receiver, e.g. relative receive times on the various wires, to the transmitter so that the transmitter may adjust its wire transmission times accordingly. In some embodiments, additional information is communicated permitting variations in communication wire mapping, including transpositions and order reversals, to be identified and corrected. This communication may be driven by the receiver, or may be distributed by a separate command/control processor, in either case communicating over a return data channel, out of band command/control channel, or other communication interface using known art protocols and methods outside the scope of this document. 
     Receiver Data Detection 
     As described in [Holden I], vector signaling codes may be efficiently detected by linearly combining sets of input signals using Multi-Input comparators or mixers (MIC). Three instances of such multi-input comparator circuits operating on permutations of the same four input signals are sufficient to detect all code words of ENRZ. That is, given a multi-input comparator that performs the operation 
         R =( J+L )−( K+M )  (Eqn. 1)
 
     where J, K, L, M are variables representing the four input signals values, then as one example and without limitation, the input permutations producing the three results R 0 , R 1 , R 2  based on the equations 
         R   0 =( W+Y )−( X+Z )  (Eqn. 2)
 
         R   1 =( Y+Z )−( W+X )  (Eqn. 3)
 
         R   2 ( Y+X )−( Z+W )  (Eqn. 4)
 
     are sufficient to unambiguously identify each code word of the ENRZ code as represented by receive signal input values W, X, Y, Z. The results R 0 , R 1 , R 2  are commonly described as sub-channels of ENRZ, in this example each being modulated by one bit of data. 
     As taught by [Ulrich II], functionally equivalent MIC configurations may be obtained by refactoring Eqns. 1-4 so that they represent the summation of two differences. 
     Various methods and systems described herein obtain skew measurements, such as early/late indications, from an aggregate data signal that is formed from a linear combination of data signals on the wires of a multi-wire bus. The aggregate data signals are referred to herein as sub-channel data signals, and are formed using a type of multi-input comparator circuit, or MIC  220 ,  610 . The MIC forms the linear combination by combining the input signals according to the decoder coefficients, or decoder weights, as specified by rows of an orthogonal matrix, such as a Hadamard matrix or other orthogonal matrix as described herein. Thus, each row of the orthogonal matrix defines the elements of the sub-channel codeword, which are then summed to obtain the orthogonal codeword, each element of the orthogonal codeword being a sum of the respective elements of the sub-channel codewords. Depending on the code being used (ENRZ, CNRZ, or another orthogonal code having a plurality of orthogonal sub-channels), all of the wires may be used for each sub-channel data signal (e.g., ENRZ), or the sub-channel data signals may be based on a subset of the wires. In some embodiments, all of the wires may be used for only some of the sub-channel data signals while other sub-channel data signals use a subset of the wires (e.g., CNRZ). 
     In each type of MIC used to decode a sub-channel by combining wire signals, any signal skew that is present on the wires of the particular sub-channel data signal under consideration will be present to one degree or another in the aggregate sub-channel data signal itself. The degree to which the wire-specific skew affects the given MIC sub-channel output depends on a number of factors, including at least the signal level transition occurring on the corresponding wire, and the relative magnitude that is applied to the signal on that wire (as specified by the sub-channel row of the matrix, and hence the MIC circuit structure). While the MIC is a voltage domain linear combiner, it acts as a phase interpolator when used to extract timing information. The measured skew of the sub-channel output of the MIC, often in the form of an “early/late” determination relative to the receive clock from the CDR subsystem, may then be converted to a skew measurement signal that is attributed to the wires involved in the transition and may even be apportioned among the wires according to each wire&#39;s relative contribution by taking into account the wire-specific level transitions as well as the corresponding sub-channel decoder coefficients of the MIC. Wire-specific skew offset values may then be generated by accumulating the results of a plurality of skew indicator signals. In some embodiments, the wire specific skew offset values may be generated by determined according to whether the accumulated skew measurement signals exceed a threshold, or the specific threshold that was exceeded in a given time period. 
     Because the measured skew is attributed to signal level variations on specific wires, and wire-specific MIC coefficients, either a training pattern with known signal level transitions on known wires may be sent, or the receiver may include a codeword detection circuit to identify what the signal level transitions would have been and the corresponding wires involved in the identified codeword transition(s). Pattern detection circuit  670  may be used to identify specific transitions and the wires involved in the corresponding identified transitions. Thus, the pattern detection circuit  670  may also identify the magnitude of the signal level transitions on the specific wires (according to the codes identified), and may accordingly adjust counter increment values to reflect the relative amount of skew contribution from the respective wires. 
     In some embodiments, a method comprises: generating, during a first and second signaling interval, an aggregated data signal by forming a linear combination of wire signals received in parallel from wires of a multi-wire bus, wherein at least some of the wire signals undergo a signal level transition during the first and second signaling interval; measuring a signal skew of the aggregated data signal; and, generating wire-specific skew offset values, each wire-specific skew offset value based on the signal skew measurement. That is, if the signal skew measurement is in the form of an early indication, then a counter for a wire involved in the transition may be decremented to decrease the wire-specific skew offset value, and if the signal skew measurement is a late indication, then the counter may be incremented. The final count value may be used as the wire-specific skew offset value(s), or the number of times the count value exceeded a threshold may be used as the wire-specific skew offset value(s). In some embodiments, these wire-specific skew offset values may be used directly as a delay adjustment control signal by adjusting a capacitive loading of the corresponding wire at the receiver. In other embodiments, the values may be sent across a reverse channel to the transmitter, thereby allowing the transmitter to pre-compensate for the skew. In some embodiments, skew offset values may be sent to the transmitter only after a receiver&#39;s ability to correct for skew has been reached. That is, once a capacitive loading or other delay mechanism at the receiver has been exhausted, the receiver may communicate a specific wire skew correction to the transmitter. The receiver may then compensate to the adjusted signal from the transmitter, thereby bringing the wire skew back within the range which the receiver may compensate for. The receiver may send specific values of wire-specific skew control signals, or may simply send wire-specific up and down indicators indicating an incremental correction. 
     In a general characterization of the skew observed from forming linear combinations of wire signals of the wired-line multi-wire bus systems with m MICs, MIC i , i=0, . . . , m−1, each MIC can be described by: 
       MICi={ a   ij   , r   i }, j=0, . . . , n−1  (Eqn. 5)
 
     where n is the number of wires. Here, a ij  are the corresponding decoder coefficients, and r i  is the comparison reference level (often set to zero for simplicity). This description can be rewritten as: 
       VMICi=Σ j=0   n−1   a   i,j   w   j   −r   j   (Eqn. 6)
 
     where VMIC stands for the voltage domain operation of a MIC forming a linear combination of inputs. Here, a i,j  are real numbers representing MIC coefficients, and w j  are real values corresponding to the instantaneous signal value on each wire. Now if the input wires each have a specific skew, Δt w(j) , with respect to an arbitrary reference time, then the skew of the signal s(i) at the output of MICi can be estimated by: 
     
       
         
           
             
               
                 
                   
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     where the signal level transition of wire j is given by Δw j =w j [now]−w j [old], and wherein in some embodiments −1&lt;Δw i &lt;+1 indicates the normalized magnitude of the transition experienced by signals w j  on wire j (w j =0 if there is no transition). The voltage swing may be normalized according to the maximum value. As can be seen, the skew at the output of a MIC depends on the data pattern. Hence, it can potentially change between max(t j ) and min(t j ), depending on the input data pattern. The data dependent skew at the output of each sub-channel means that even in an ideal system without any ISI, the eye will be closed by max(t j )−min(t j ), due to skew. Skew dependent eye closure does not occur in MICs described by a linear encoding/decoding scheme, such as NRZ, or ENRZ. In some coding schemes such as in CNRZ, skew can close the eye at the output of MIC due to its sensitivity to deterministic or random CM noise. 
     Here it is assumed that |t j |&lt;&lt;T (T is the data period or signaling interval, corresponding to 1× UI). Close to the transition time, the signal value on each wire at time t&lt;&lt;T can be approximated by: 
         w   j   =bj ( t+tj )  (Eqn. 8)
 
     From (Eqn. 8) and (Eqn. 6), the transition time at the output of sub-channel can be approximated by (Eqn. 7). 
     Indeed, (Eqn. 7) implies that each MIC is operating as a phase interpolator in the time domain. In other words, the transition time at the output of a MIC stage is a weighted interpolation of the transition times of the input signals. Hence, if a multi-wire receiver can be described with [a ij , r i ], then the cross times at the output of MIC can be described by [a ij  b ij ]. If this matrix is invertible, then one can precisely estimate the skew at the input of receiver. Otherwise, if [a ij , b i ] is not invertible, then it is not possible to calculate the input skew values and an alternative algorithm may be used to make the estimation. 
     In some embodiments using a GW code, some transmitter implementations exhibit a skew pattern T=[0, 0, t 1 , t 1 , t 2 , t 2 ], corresponding to wires W=[w0, . . . , w5]. This skew pattern is due to floor-plan of the transmitter. Using Eqn. 7, it can be shown that the expected skew at the output of receiver sub-channels is: 
         T   subch =[( t   1   +t   2 )/3 , t   1 /2, 0 , t   1 /2 +t   2 /2 , t   2 ].  (Eqn. 9)
 
     Based on this calculation, the output of sub-channel five has the maximum skew, while the transition at the output of sub-channel two occurs as the earliest. The experimental data matches very well with the estimation made in Eqn.  9 . Hence, Eqn.  9  can be used to estimate the skew between wires (t 1  and t 2 ). 
     In one embodiment, an algorithm to compensate for skew in a system using the GW code may include:
         (1) measuring the phase interpolator code (or an alternative signal that can be used to measure the skew between sub-channels) that identifies the crossing point of sub-channel, based on eye of sub-channel (4) (which involves only wires 4 and 5);   (2) make a similar measurement for other sub-channels;   (3) use eq. (9) to estimate the skew corresponding to each wire.       

     In some embodiments, the measurement algorithm includes measuring the zero crossing points at the output of each Rx sub-channel. The receiver in Rx includes five sub-channels (five MICs). The output of each MIC is sampled by four slicers corresponding to the quarter rate architecture of the receiver (i.e., each slicer operates at one quarter rate, taking turns in processing the full rate aggregate data signal of a given MIC). The procedure of measurement of some embodiments is as follows:
         (1) Produce a periodic (e.g., 16 UI data, 8 UI high and 8 UI low) on one of the phases of the transmitter (this assumes a transmitter having multiple phases also).   (2) Measure cross point at the output of the 5 MICs, each one observed by 4 slicers. This gives 20 independent measurements.   (3) Go back to step (1) and transmit a new set of periodic data on a different phase of the transmitter. Repeat this flow until data is collected for all the four phases of the transmitter.       

     Suppose M0 is measurements that have been carried out corresponding to sub-channel 0. Here, a periodic data sequence has been sent on the transmitter and measured by the receiver slicers. The cross point of the received signal at the output of Rx MICs can be measured. This is done by rotating the sampling clock using a phase interpolator of the four slicers that are connected to each MIC. 
     
       
         
           
             
               M 
               ⁢ 
               0 
             
             = 
             
               
                 
                   
                     [ 
                     
                       
                         x 
                         ⁢ 
                         0 
                       
                       + 
                       
                         y 
                         ⁢ 
                         0 
                       
                       + 
                       
                         z 
                         ⁢ 
                         0 
                       
                     
                   
                 
                 
                   
                     
                       x 
                       ⁢ 
                       1 
                     
                     + 
                     
                       y 
                       ⁢ 
                       0 
                     
                     + 
                     
                       z 
                       ⁢ 
                       1 
                     
                   
                 
                 
                   
                     
                       x 
                       ⁢ 
                       2 
                     
                     + 
                     
                       y 
                       ⁢ 
                       0 
                     
                     + 
                     
                       z 
                       ⁢ 
                       2 
                     
                   
                 
                 
                   
                     
                       x 
                       ⁢ 
                       3 
                     
                     + 
                     
                       y 
                       ⁢ 
                       0 
                     
                     + 
                     
                       z 
                       ⁢ 
                       3 
                     
                   
                 
               
               
                 
                   
                     
                       x 
                       ⁢ 
                       0 
                     
                     + 
                     
                       y 
                       ⁢ 
                       1 
                     
                     + 
                     
                       z 
                       ⁢ 
                       3 
                     
                   
                 
                 
                   
                     
                       x 
                       ⁢ 
                       1 
                     
                     + 
                     
                       y 
                       ⁢ 
                       1 
                     
                     + 
                     
                       z 
                       ⁢ 
                       2 
                     
                   
                 
                 
                   
                     
                       x 
                       ⁢ 
                       2 
                     
                     + 
                     
                       y 
                       ⁢ 
                       1 
                     
                     + 
                     
                       z 
                       ⁢ 
                       3 
                     
                   
                 
                 
                   
                     
                       x 
                       ⁢ 
                       3 
                     
                     + 
                     
                       y 
                       ⁢ 
                       1 
                     
                     + 
                     
                       z 
                       ⁢ 
                       0 
                     
                   
                 
               
               
                 
                   
                     
                       x 
                       ⁢ 
                       0 
                     
                     + 
                     
                       y 
                       ⁢ 
                       2 
                     
                     + 
                     
                       z 
                       ⁢ 
                       2 
                     
                   
                 
                 
                   
                     
                       x 
                       ⁢ 
                       1 
                     
                     + 
                     
                       y 
                       ⁢ 
                       2 
                     
                     + 
                     
                       z 
                       ⁢ 
                       3 
                     
                   
                 
                 
                   
                     
                       x 
                       ⁢ 
                       2 
                     
                     + 
                     
                       y 
                       ⁢ 
                       2 
                     
                     + 
                     
                       z 
                       ⁢ 
                       0 
                     
                   
                 
                 
                   
                     
                       x 
                       ⁢ 
                       3 
                     
                     + 
                     
                       y 
                       ⁢ 
                       2 
                     
                     + 
                     
                       z 
                       ⁢ 
                       1 
                     
                   
                 
               
               
                 
                   
                     
                       x 
                       ⁢ 
                       0 
                     
                     + 
                     
                       y 
                       ⁢ 
                       3 
                     
                     + 
                     
                       z 
                       ⁢ 
                       1 
                     
                   
                 
                 
                   
                     
                       x 
                       ⁢ 
                       1 
                     
                     + 
                     
                       y 
                       ⁢ 
                       3 
                     
                     + 
                     
                       z 
                       ⁢ 
                       0 
                     
                   
                 
                 
                   
                     
                       x 
                       ⁢ 
                       2 
                     
                     + 
                     
                       y 
                       ⁢ 
                       3 
                     
                     + 
                     
                       z 
                       ⁢ 
                       1 
                     
                   
                 
                 
                   
                     
                       
                         x 
                         ⁢ 
                         3 
                       
                       + 
                       
                         y 
                         ⁢ 
                         3 
                       
                       + 
                       
                         z 
                         ⁢ 
                         2 
                       
                     
                     ] 
                   
                 
               
             
           
         
       
     
     The columns are measurements that have been done for different phases of the receive clock. For example, the column 0 shows four independent measurements coming out from the slicer of sub-channel zero, which is controlled with phase 000 (0-degree) receive clock. The rows however, refer to four different sets of data that have been transmitted from the transmitter. The row 0, for example, is the periodic data that has been produced by Tx phase 000. 
     Meanwhile, here:
         x: refers to error or skew on Rx sampling clock   y: refers to the error or the skew on the Tx clock that produces the output signal. For example, y0 refers to the timing error on the Tx clock phase 000.       

     z: is referring to the non-linearity effect coming from PI (phase interpolator). 
     As can be seen, the 16 measurements done at the output of MIC corresponding to sub-channel 0, may be used to calculate (or estimate) 12 independent parameters. 
     Considering all sub-channels, there will be five sets of measurements for the five MICs, each including 16 measurements, producing 80 individual measurements. Comparing measurements M0, M1, M2, and M3 helps to measure wire to wire skew. In some embodiments, a maximum likelihood approach may be used to extract the following items:
         (a) Five inter-wire skew numbers   (b) Inter-phase clock skew numbers for Rx   (c) Inter-phase clock skew numbers for Tx   (d) Four numbers describing nonlinearity of the phase interpolator. Note that the non-linearity numbers for PI can be measured in only few data points.       

     ENRZ Coding: In some embodiments of an ENRZ scheme, |a ij |=0.25, for all i and j values. In some embodiments, the circuit is configured to select specific patterns in order to make measurements for wire skew. Additional embodiments using subsets of transitions in an ENRZ transceiver will be described. 
     Relationship Between Wires and Codes in ENRZ 
     As discussed above, and in view of the detection equations Eqns. 2-4, there are difficulties inherent in performing measurements of received sub-channel signals and attempting to map that information back to variations in the received wire signals. Each sub-channel is dependent on all four received wire signals, thus there is no obvious mathematical process to partition, factor out, or otherwise determine information about individual wire signals. 
     
       
         
           
               
               
               
               
               
               
               
               
             
               
                 TABLE I 
               
               
                   
               
               
                 Code 
                 Wire0 
                 Wire1 
                 Wire2 
                 Wire3 
                 R 0   
                 R 1   
                 R 2   
               
               
                   
               
             
            
               
                   
               
            
           
           
               
               
               
               
               
               
               
               
            
               
                 7 
                 +1 
                 −1/3 
                 −1/3 
                 −1/3 
                 1 
                 1 
                 1 
               
               
                 1 
                 −1/3 
                 +1 
                 −1/3 
                 −1/3 
                 0 
                 0 
                 1 
               
               
                 2 
                 −1/3 
                 −1/3 
                 +1 
                 −1/3 
                 0 
                 1 
                 0 
               
               
                 4 
                 −1/3 
                 −1/3 
                 −1/3 
                 +1 
                 1 
                 0 
                 0 
               
               
                 0 
                 −1 
                 +1/3 
                 +1/3 
                 +1/3 
                 0 
                 0 
                 0 
               
               
                 6 
                 +1/3 
                 −1 
                 +1/3 
                 +1/3 
                 1 
                 1 
                 0 
               
               
                 5 
                 +1/3 
                 +1/3 
                 −1 
                 +1/3 
                 1 
                 0 
                 0 
               
               
                 3 
                 +1/3 
                 +1/3 
                 +1/3 
                 −1 
                 0 
                 1 
                 1 
               
               
                   
               
            
           
         
       
     
     As shown in Table I, the wire signals used to encode codes 7, 1, 2, 4 utilize a single “+1” signal value and three “−1/3” signal values. (As ENRZ is a balanced vector signaling code, all signal values in a given codeword sum to zero.) Similarly, the wire signals used to encode codes 0, 6, 5, 3 utilize a single “−1” signal and three “+1/3” signals. More significantly, transitions between any of codes 7, 1, 2, 4 or between codes 0, 6, 5, 3 only change the signals on two wires. Thus, if any of, for example, codes 7, 1, 2, 4 is received followed by a different code from that same set, the transition between codes is associated with exactly two wires changing, and which two wires changed may be determined using the information in Table I. Identical conditions apply to consecutive occurrences of codes drawn from the set 0, 6, 5, 3. 
     These known two-wire transitions are associated with exactly two values changing in the received data “word” R 0 , R 1 , R 2 . Such criterion is not by itself sufficient to identifying which two wires changed, however, as for example a transition between code 7 and code 1 due to changes in Wire0 and Wire1 cause only R 0 , R 1  to change, but so do transitions between codes 0 and 6; Contrariwise, changes of only R 0 , R 1  may also be caused by transitions between codes 2 and 4, or between codes 3 and 5, due to changes in Wire2 and Wire3. Thus, an algorithm or circuit may be used to identify wire pairs associated with sub-channel transitions may identify particular sequential sets of codes. The particular wire order and codeword values used in this example were chosen for descriptive convenience, and in no way imply limitation. 
     Determining Transition Times 
     As previously mentioned, the system environment for these descriptions utilizes receiver clock recovery derived from transitions of the detected sub-channel data. To maximize the amount of information available to maintain proper clock alignment, it is common to monitor all received sub-channels. [Tajalli I] describes such a clock recovery system, in which individual phase detectors sensitive to transitions in each sub-channel produce phase error results, which are then summed to produce an aggregate error signal used to update the clock PLL phase. In one such embodiment, only results from sub-channels with valid transitions within the time interval of interest are summed; in an alternative embodiment, simple “bang/bang” phase comparators are used and summed without such filtration, with any anomalous error results produced by non-transitioning sub-channels being averaged out over time. Known art embodiments utilizing either baud-rate clock edge detection methods or double-rate clock edge sampling methods may also be used. 
       FIG.  3    illustrates a clock recovery circuit  300 , for use in some embodiments. As shown,  FIG.  3    includes multiple partial phase comparators  310 , reach receiving a respective sub-channel output. In such embodiments, each partial phase comparator only outputs a partial phase-error result if a transition has occurred on the respective sub-channel. A summation circuit  320  receives each partial phase error signal and generates a composite phase error signal that is filtered by the loop filter  330  (which may be a low-pass filter (LPF) to provide a low-frequency error signal) to the voltage controlled oscillator (VCO)  340 . The clock recovery circuit  300  may further include a frequency divider  350  that receives the outputs of the VCO  340 , divides the frequency down, and provides the signals to the phase interpolator  360 , which provides interpolated signals to the phase comparators  310 . As shown, the phase interpolator also receives a phase offset correction signal from clock/data phase control logic  370 . Such a correction signal may account for process variations in the system. The outputs of the VCO  340  may be used as sampling clocks in a multi-phase system, one phase being shown in  FIG.  4   . 
     In the two-wire transitions of interest, two sub-channel results change, essentially simultaneously except for random circuit variations. Thus, two essentially identical phase error results are incorporated into the aggregate error signal during such transitions. The following algorithm captures the overall “early or late” status of the aggregate error signal, for use in correcting wire skew. 
     Skew Correction Algorithm 
     Inputs to this algorithm include the received data, i.e. the detected sub-channel results R 0 , R 1 , R 2 . For purposes of explanation, they are described herein as identifying “codes”, i.e. particular wire and result combinations, as previously described relative to Table I. Information from at least two consecutively received unit intervals is obtained, here called code(N) and code(N+1), along with the detected or measured skew in the form of a clock phase error associated with that time interval, which may be a signed magnitude indicating the amount that the received transitions were earlier or later than the expected clock time, or as little as a simple binary sign indicating “early/late”. 
     The information may be obtained by continuous observation of the received data stream (as one example, using a finite state machine,) or may be obtained by statistically valid sampling of the data stream (as one example, by a software process running on a control or management processor periodically requesting and receiving sequences of received data, such samples spanning at minimum two consecutively received unit intervals and the associated clock phase error information. 
     Outputs from this algorithm are running estimates of the relative arrival times of signals on the four wires, which may be used to immediately or periodically adjust wire signal delay elements, or request or indicate comparable per-wire timing adjustments be made by the transmitter. In one embodiment, said running estimates are immediately used to adjust receiver wire delays. In another embodiment, running estimates are maintained as variables in memory, with adjustments initiated when the absolute positive or negative magnitude of the variable exceeds a predetermined threshold, thus filtering out small perturbations. 
     Another embodiment of the algorithm in Verilog is provided as Appendix I. 
     
       
         
           
               
             
               
                   
               
             
            
               
                 Static signed integer Wire0, Wire1, Wire2, Wire3 
               
               
                 Calculate_skew( Data(N), Data(N+1), signed integer Error) 
               
               
                 { 
               
               
                 if Data(N) == 7 &amp;&amp; Data(N+1) == 1 || Data(N) == 1 &amp;&amp; Data(N+1) == 7 
               
               
                  Wire0 += Error 
               
               
                  Wire1 += Error 
               
               
                  break; 
               
               
                 else if Data(N) == 0 &amp;&amp; Data(N+1) == 6 || Data(N) == 6 &amp;&amp; Data(N+1) == 0 
               
               
                  Wire0 += Error 
               
               
                  Wire1 += Error 
               
               
                  break; 
               
               
                 else if Data(N) == 7 &amp;&amp; Data(N+1) == 2 || Data(N) == 2 &amp;&amp; Data(N+1) == 7 
               
               
                  Wire0 += Error 
               
               
                  Wire2 += Error 
               
               
                  break; 
               
               
                 else if Data(N) == 0 &amp;&amp; Data(N+1) == 5 || Data(N) == 5 &amp;&amp; Data(N+1) == 0 
               
               
                  Wire0 += Error 
               
               
                  Wire2 += Error 
               
               
                  break; 
               
               
                 else if Data(N) == 2 &amp;&amp; Data(N+1) == 4 || Data(N) == 4 &amp;&amp; Data(N+1) == 2 
               
               
                  Wire2 += Error 
               
               
                  Wire3 += Error 
               
               
                  break; 
               
               
                 else if Data(N) == 5 &amp;&amp; Data(N+1) == 3 || Data(N) == 3 &amp;&amp; Data(N+1) == 5 
               
               
                  Wire2 += Error 
               
               
                  Wire3 += Error 
               
               
                  break; 
               
               
                 else if Data(N) == 1 &amp;&amp; Data(N+1) == 4 || Data(N) == 4 &amp;&amp; Data(N+1) == 1 
               
               
                  Wire1 += Error 
               
               
                  Wire3 += Error 
               
               
                  break; 
               
               
                 else if Data(N) == 6 &amp;&amp; Data(N+1) == 3 || Data(N) == 3 &amp;&amp; Data(N+1) == 6 
               
               
                  Wire1 += Error 
               
               
                  Wire3 += Error 
               
               
                  break; 
               
               
                 else if Data(N) == 1 &amp;&amp; Data(N+1) == 2 || Data(N) == 2 &amp;&amp; Data(N+1) == 1 
               
               
                  Wire1 += Error 
               
               
                  Wire2 += Error 
               
               
                  break; 
               
               
                 else if Data(N) == 6 &amp;&amp; Data(N+1) == 5 || Data(N) == 5 &amp;&amp; Data(N+1) == 6 
               
               
                  Wire1 += Error 
               
               
                  Wire2 += Error 
               
               
                  break; 
               
               
                 else if Data(N) == 7 &amp;&amp; Data(N+1) == 4 || Data(N) == 4 &amp;&amp; Data(N+1) == 7 
               
               
                  Wire0 += Error 
               
               
                  Wire3 += Error 
               
               
                  break; 
               
               
                 else if Data(N) == 0 &amp;&amp; Data(N+1) == 3 || Data(N) == 3 &amp;&amp; Data(N+1) == 0 
               
               
                  Wire0 += Error 
               
               
                  Wire3 += Error 
               
               
                  break; 
               
               
                 } 
               
               
                   
               
            
           
         
       
     
     The ‘if’ statements correspond exactly to the transition conditions shown in the state diagram of  FIG.  12   , where consecutive codes of 7 followed by 1, or of 1 followed by 7 are associated with wire0 and wire1, as are code transitions between 0 and 6. 
     As there is no way of determining which of the two transitioning wires is the source of the early or late timing, the variables representing skew offset metrics for both wires are updated equally. If, for example, subsequent transitions associated with codes 0 and 5 also update wire0 and wire2 in the same direction, it is likely that wire0, common to both measurements, is the source of the timing error. Thus, the algorithm may be run over a number of different samples to provide a reasonable estimate of individual wire timing errors. As previously mentioned, at least one embodiment introduces an absolute magnitude threshold before accumulated timing error values cause actual timing modifications, so as to reduce random timing adjustments associated with these measurement artifacts. Other embodiments adjust wire timings immediately, presuming that small adjustments even in the wrong direction will introduce minimal error, while continued adjustments in the same direction will eventually produce an optimized eye opening. 
       FIG.  4    is a block diagram of a receiver configurable for performing the skew detection algorithm described above. As shown,  FIG.  4    includes MICs  220  as described above for receiving the signals on the wires and responsively generating aggregated data signals representing the sub-channel outputs R 0 -R 2 . The sub-channel outputs are sampled  430 , the samplers configured to provide data outputs D 0-2  for each sub-channel, as well as early/late indication signals E/L 0.2  for each sub-channel. In some embodiments, samplers  430  may take the form of the samplers shown in  FIG.  6    or  FIG.  7    as described above.  FIG.  4    includes a code sequence detection block  440  for detecting valid sets of sequentially received bits (each set representing a code 0 through 7 as described above). Such sequences are illustrated in the state diagram of  FIG.  12   . In some embodiments, DFE may be provided by the code sequence detection block  440 , which may be used by the samplers  430  in embodiments using e.g., the samplers shown in  FIG.  6   . 
       FIG.  8    illustrates a block diagram of a code sequence detection block, in accordance with some embodiments. In some embodiments, the code sequence detection block may be implemented through the use of D flip flops  805  and  810  being sampled by a delayed  815  version of the sampling clock to allow time for buffering. Current detected bits b 0 -b 2  and previously detected bits prev_b0-b2 are analyzed by a logic circuit  820  to see if a valid code sequence is detected. If a valid code sequence is detected, wire delay adjustment enable signals w 0 -w 3 _enable are provided to the aggregate wire delay block  460  shown in  FIG.  4   . As described above, in the embodiment of the H4 code, two wires are involved in any valid code sequence detected by logic circuit  820 . In such embodiments, only two of the wire delay adjustment enable signals w 0 -w 3 _enable will be ‘1s’, while the other two are ‘0’ (thus not updating delay values in aggregate wire delay block  460 ). 
     In alternative embodiments, other sequences may be used, in addition to or instead of the ones involving only two wires. For example, the code sequence detection circuit  670  may identify transitions where each wire changes sign, but maintains the same magnitude, such as the codeword [−1, ⅓, ⅓, ⅓] changes to [1, −⅓, −⅓, −⅓] or [−⅓, 1, −⅓, ⅓] changes to [⅓, −1, ⅓, ⅓], and so on. This set of transitions includes 8 sets of codeword sequences. In these transitions, the magnitudes of the wire-specific transitions are considered and the skew metrics are updated accordingly. In particular, skew observed or measured at the MIC output for a codeword change from [−1, ⅓, ⅓, ⅓] to [1, −⅓, −⅓, −⅓] may be weighted according to the transition magnitudes given by: abs((wire(code1, i)−wire(code2, i)*mic(wire(i)), or in this case, [2, ⅔, ⅔, ⅔]. That is, skew on wire W0 will have 3 times the impact on observed MIC output skew relative to skew on any other wire. The counter increments may be adjusted according to the identified transition magnitudes to properly reflect the relative contribution of skew from each of the wires. 
       FIG.  9    illustrates a block diagram  900  of a logic circuit  820 , in accordance with some embodiments. The example of  FIG.  9    illustrates the valid code sequence from code ‘1’ in Table 1 to code ‘7’. Such a logic circuit may be implemented as an AND gate  905 , in which the output of gate  905  is high if bits b0-b2 corresponding to code ‘1’=‘001’ and if previously received bits prev_b0-b2 corresponding to code ‘7’=‘111’. A control circuit  910  may analyze the outputs of all such detection gates, and may output wire delay adjustment enable signals w 0 -w 3  enable to the aggregate wire delay block  460 . The enable signals indicate which counters should be adjusted (incremented or decremented according to the signal skew characteristic). In addition, the count increment may also be weighted as described herein according to the relative magnitudes of the wire signal level transitions. In some embodiments, the control circuit  910  may implement control logic that implements Table II below: 
     
       
         
           
               
               
               
             
               
                 TABLE II 
               
               
                   
               
               
                   
                   
                 Wire Delay 
               
               
                   
                   
                 Adjustment 
               
               
                 Previous Bits 
                 Current Bits 
                 Enable Signals 
               
               
                   
               
             
            
               
                   
               
            
           
           
               
               
               
               
               
               
               
            
               
                 1 
                 1 
                 1 
                 0 
                 0 
                 1 
                 w0_enable = ‘1’ 
               
               
                 0 
                 0 
                 1 
                 1 
                 1 
                 1 
                 w1_enable = ‘1’ 
               
               
                 0 
                 0 
                 0 
                 1 
                 1 
                 0 
                 w2_enable = ‘0’ 
               
               
                 1 
                 1 
                 0 
                 0 
                 0 
                 0 
                 w3_enable = ‘0’ 
               
               
                 1 
                 1 
                 1 
                 0 
                 1 
                 0 
                 w0_enable = ‘1’ 
               
               
                 0 
                 1 
                 0 
                 1 
                 1 
                 1 
                 w1_enable = ‘0’ 
               
               
                 0 
                 0 
                 0 
                 1 
                 0 
                 1 
                 w2_enable = ‘1’ 
               
               
                 1 
                 0 
                 1 
                 0 
                 0 
                 0 
                 w3_enable = ‘0’ 
               
            
           
           
               
            
               
                 . 
               
               
                 . 
               
               
                 . 
               
            
           
           
               
               
               
               
               
               
               
            
               
                 0 
                 1 
                 0 
                 1 
                 0 
                 0 
                 w0_enable = ‘0’ 
               
               
                 1 
                 0 
                 0 
                 0 
                 1 
                 0 
                 w1_enable = ‘0’ 
               
               
                 1 
                 0 
                 1 
                 0 
                 1 
                 1 
                 w2_enable = ‘1’ 
               
               
                 0 
                 1 
                 1 
                 1 
                 0 
                 1 
                 w3_enable = ‘1’ 
               
               
                   
               
            
           
         
       
     
       FIG.  4    further includes a matrix error combiner  450  configured to receive the early/late indication signals from the plurality of sub-channels E/L 0-2 , and to generate a final early/late decision to provide to aggregate wire delay block  460  to increment or decrement the stored delay values accordingly. As noted above and illustrated in Table I, in any given valid code sequence for some embodiments, only two sub-channels R 0 -R 2  change. Thus, the E/L signal provided by the sub-channel that does not change is not useful, and logic may be included to omit the effects of such an indication. Nevertheless, the two sub-channels that do change will both provide E/L indications that are early or late, and thus the combination of such E/L indications will overcome the E/L indication of the non-transitioning sub-channel, and the final E/L indication provided by matrix error combiner  450  will remain valid. 
       FIG.  10    illustrates an exemplary block diagram of aggregate wire delay block  460 , in accordance with some embodiments. as shown, aggregate wire delay block includes four blocks  1005 ,  1010 ,  1015 , and  1020 ; one for each wire of the multi-wire bus. In some embodiments, each block corresponds to a counter that may be selectably enabled according to the corresponding received wire delay adjustment enable signals w 0 -w 3 _enable. Each counter may also be configured to receive the E/L indication signal from the matrix error combiner  450 , which may be used to control each counter to either count up or down (U/D), depending on the E/L indication signal. Each counter may increment according to a delayed  470  version of the sampling clock. In some embodiments, the values stored in each counter may be provided (e.g., as binary bits) to a respective wire delay adjustment circuit, as shown for example in  FIG.  5   . 
       FIG.  13    illustrates a flowchart of a method  1300 , in accordance with some embodiments. As shown, method  1300  incudes obtaining consecutive received data values  1302 . The received data values are analyzed  1304  to determine if the data corresponds to a set of single-wire-pair transitions. If the determination is “No”, then the process starts again from the beginning for the next set of received data. If the determination is “Yes,” the wires associated with the code transition are identified  1306 , for example using control logic  910  described above with respect to Table II. Based on the identified wires, the running wire counts representing the aggregate delay values are updated  1308  based on the received E/L information. Once the running error counts reach an action threshold  1310 , the wire delays are adjusted according to the stored error count  1312 . 
     
       
         
           
               
               
             
               
                   
                 APPENDIX I 
               
               
                   
                   
               
             
            
               
                   
                 // VerilogA for sk, x_skewrec_avg, veriloga 
               
               
                   
                 ‘include “constants.vams” 
               
               
                   
                 ‘include “disciplines.vams” 
               
               
                   
                 module x_skewrec_avg(dm1, d0, cdrearly, cdrlate, clk, t0, t1, t2, 
               
               
                   
                 t3, vdda, vssa); 
               
               
                   
                 electrical [2:0] dm1; 
               
               
                   
                 input [2:0] dm1; 
               
               
                   
                 electrical [2:0] d0; 
               
               
                   
                 input [2:0] d0; 
               
               
                   
                 electrical [2:0] cdrearly; 
               
               
                   
                 input [2:0] cdrearly; 
               
               
                   
                 electrical [2:0] cdrlate; 
               
               
                   
                 input [2:0] cdrlate; 
               
               
                   
                 electrical clk; 
               
               
                   
                 input clk; 
               
               
                   
                 electrical t0, t1,t2, t3; // outputs to control skew elements 
               
               
                   
                 output t0, t1, t2, t3; 
               
               
                   
                 electrical vdda, vssa; 
               
               
                   
                 inout vdda, vssa; 
               
               
                   
                 real t0i, t1i, t2i, t3i, vth, vote, tavg,incdecval; 
               
               
                   
                 integer id0, idm1; 
               
               
                   
                 analog begin 
               
               
                   
                  vth = V(vdda, vssa) / 2.0; // digital slicer level for the 
               
               
                   
                  votes 
               
               
                   
                  @(initial_step) begin // just set the value to default (like 
               
               
                   
                 a reset) at beginning of simulation 
               
               
                   
                   t0i = 0.0; 
               
               
                   
                   t1i = 0.0; 
               
               
                   
                   t2i = 0.0; 
               
               
                   
                   t3i = 0.0; 
               
               
                   
                  end 
               
               
                   
                  // for every clock cycle we update the skew values; this can 
               
               
                   
                 be dutycycled as the drift is slow in mission mode. this loop was 
               
               
                   
                 missing 
               
               
                   
                  @(cross(V(clk,vssa),1)) begin 
               
               
                   
                   // Actual bits from the three bits 
               
               
                   
                   id0 = (V(d0[0], vssa) &gt; vth) &lt;&lt; 2 | (V(d0[1], vssa) &gt; 
               
               
                   
                 vth) &lt;&lt; 1 | (V(d0[2], vssa) &gt; vth) &lt;&lt; 0; 
               
               
                   
                   // History bits D(n−1) across the three sub-channels 
               
               
                   
                   idm1 = (V(dm1[0], vssa) &gt; vth) &lt;&lt; 2 | (V(dm1[1], vssa) &gt; 
               
               
                   
                 vth) &lt;&lt; 1 | (V(dm1[2], vssa) &gt; vth) &lt;&lt; 0; 
               
               
                   
                   // increment/decrement value, defines time constant 
               
               
                   
                   incdecval = 0.001p/10; 
               
               
                   
                   // collect all the votes across sub-channels. Two sub- 
               
               
                   
                 channels are always toggling, one sub-channel is static and 
               
               
                   
                 should not contribute to votes (might need to enforce to ignore 
               
               
                   
                 the static channel. To be investigated) 
               
               
                   
                   vote = 0.0; 
               
               
                   
                   if(V(cdrearly[0],vssa) &gt; vth) vote = vote + incdecval; 
               
               
                   
                   else vote = vote − incdecval; 
               
               
                   
                   if(V(cdrlate[0],vssa) &gt; vth) vote = vote − incdecval; 
               
               
                   
                   else vote = vote + incdecval; 
               
               
                   
                   if(V(cdrearly[1],vssa) &gt; vth) vote = vote + incdecval; 
               
               
                   
                   else vote = vote − incdecval; 
               
               
                   
                   if(V(cdrlate[1],vssa) &gt; vth) vote = vote − incdecval; 
               
               
                   
                   else vote = vote + incdecval; 
               
               
                   
                   if(V(cdrearly[2],vssa) &gt; vth) vote = vote + incdecval; 
               
               
                   
                   else vote = vote − incdecval; 
               
               
                   
                   if(V(cdrlate[2],vssa) &gt; vth) vote = vote − incdecval; 
               
               
                   
                   else vote = vote + incdecval; 
               
               
                   
                   vote = −vote; 
               
               
                   
                  // looking for patterns where the 1 moves from one wire to an 
               
               
                   
                 other one. −&gt; id0 != idm1 has not been explicit defined but it is 
               
               
                   
                 implicit as for this the votes are zero sum (to be investigated 
               
               
                   
                 if it makes sense to add this statement for robustness). 
               
               
                   
                   if((id0 == 7 || id0 == 1 || id0 == 2 || id0 == 4) &amp;&amp; 
               
               
                   
                 (idm1 == 7 || idm1 == 1 || idm1 == 2 || idm1 == 4)) begin 
               
               
                   
                    case (id0) // update where the 1 has ended up 
               
               
                   
                     7: t0i = t0i + vote; 
               
               
                   
                     1: t1i = t1i + vote; 
               
               
                   
                     2: t2i = t2i + vote; 
               
               
                   
                     4: t3i = t3i + vote; 
               
               
                   
                     default: id0 = id0; // fake assignement 
               
               
                   
                    endcase 
               
               
                   
                    case (idm1) // update where the 1 initially was 
               
               
                   
                     7: t0i = t0i + vote; 
               
               
                   
                     1: t1i = t1i + vote; 
               
               
                   
                     2: t2i = t2i + vote; 
               
               
                   
                     4: t3i = t3i + vote; 
               
               
                   
                     default: idm1 = idm1;// fake assignement 
               
               
                   
                    endcase 
               
               
                   
                   end 
               
               
                   
                  // looking for patterns where the −1 moves from one wire to 
               
               
                   
                 an other one. −&gt; id0 != idm1 has not been explicit defined but it 
               
               
                   
                 is implicit as for this the votes are zero sum (to be 
               
               
                   
                 investigated if it makes sense to add this statement for 
               
               
                   
                 robustness). 
               
               
                   
                   if((id0 == 0 || id0 == 6 || id0 == 5 || id0 == 3) &amp;&amp; 
               
               
                   
                 (idm1 == 0 || idm1 == 6 | | idm1 == 5 || idm1 == 3)) begin 
               
               
                   
                    case (id0) // update where the −1 has ended up 
               
               
                   
                     0: t0i = t0i + vote; 
               
               
                   
                     6: t1i = t1i + vote; 
               
               
                   
                     5: t2i = t2i + vote; 
               
               
                   
                     3: t3i = t3i + vote; 
               
               
                   
                     default: id0 = id0; // fake assignement 
               
               
                   
                    endcase 
               
               
                   
                    case (idm1) // update where the −1 initially was 
               
               
                   
                     0: t0i = t0i + vote; 
               
               
                   
                     6: t1i = t1i + vote; 
               
               
                   
                     5: t2i = t2i + vote; 
               
               
                   
                     3: t3i = t3i + vote; 
               
               
                   
                     default: idm1 = idm1; // fake assignement 
               
               
                   
                    endcase 
               
               
                   
                   end 
               
               
                   
                   // figuring out the absolute value 
               
               
                   
                   tavg = ( t0i + t1i + t2i + t3i ) / 4; 
               
               
                   
                   // and subtraction it (enforcing it to zero) 
               
               
                   
                   t0i = t0i − tavg; 
               
               
                   
                   t1i = t1i − tavg; 
               
               
                   
                   t2i = t2i − tavg; 
               
               
                   
                   t3i = t3i − tavg; 
               
               
                   
                   // saturation logic 
               
               
                   
                   if(t0i &gt; 12.5p) t0i = 12.5p; 
               
               
                   
                   if(t0i &lt; −12.5p) t0i = −12.5p; 
               
               
                   
                   if(t1i &gt; 12.5p) t1i = 12.5p; 
               
               
                   
                   if(t1i &lt; −12.5p) t1i = −12.5p; 
               
               
                   
                   if(t2i &gt; 12.5p) t2i = 12.5p; 
               
               
                   
                   if(t2i &lt; −12.5p) t2i = −12.5p; 
               
               
                   
                   if(t3i &gt; 12.5p) t3i = 12.5p; 
               
               
                   
                   if(t3i &lt; −12.5p) t3i = −12.5p; 
               
               
                   
                  end // end of the cross function resp. clk 
               
               
                   
                  // assignement to the output. Will be feed into veriloga skew 
               
               
                   
                 elements (e.g. absdelay is used to shift/delay the signal in 
               
               
                   
                 time) 
               
               
                   
                  V(t0, vssa) &lt;+ laplace_nd(t0i + 12.5p + 5p, {1, 0}, 
               
               
                   
                 {1, 2e−12}); 
               
               
                   
                  V(t1, vssa) &lt;+ laplace_nd(t1i + 12.5p + 5p, {1, 0}, 
               
               
                   
                 {1, 2e−12}); 
               
               
                   
                  V(t2, vssa) &lt;+ laplace_nd(t2i + 12.5p + 5p, {1, 0}, 
               
               
                   
                 {1, 2e−12}); 
               
               
                   
                  V(t3, vssa) &lt;+ laplace_nd(t3i + 12.5p + 5p, {1, 0}, 
               
               
                   
                 {1, 2e−12}); 
               
               
                   
                 end 
               
               
                   
                 endmodule