Patent Publication Number: US-2022238829-A1

Title: Display device

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2021-008990, filed Jan. 22, 2021, the entire contents of which are incorporated herein by reference. 
     FIELD 
     Embodiments described herein relate generally to a display device. 
     BACKGROUND 
     In recent years, a display device to which an organic light emitting diode (OLED) is applied as a display element has been put into practical use. This display element includes a pair of electrodes and an organic layer interposed between these electrodes. Such organic layer is formed, for example, by a vacuum vapor deposition method. 
     For example, when an organic layer in which a plurality of functional layers are stacked is formed, edge portions of the functional layers may not be aligned at a peripheral portion of the organic layer, which may lead to degradation in performance of the display element. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a diagram illustrating a configuration example of a display device according to a first embodiment. 
         FIG. 2  is a diagram illustrating an example of a layout of sub-pixels according to the first embodiment. 
         FIG. 3  is a schematic cross-sectional view of the display device along line of  FIG. 2 . 
         FIG. 4  is a cross-sectional view illustrating an example of a layer structure applicable to an organic layer according to the first embodiment. 
         FIG. 5  is a schematic plan view of the organic layer according to the first embodiment. 
         FIG. 6  is a schematic cross-sectional view of the display device along line VI-VI in  FIG. 5 . 
         FIG. 7  is a diagram schematically illustrating an example of a method for forming an organic layer according to the first embodiment. 
         FIG. 8  is a diagram illustrating an example of parameters related to vapor deposition. 
         FIG. 9  is a diagram schematically illustrating another example of the method for forming an organic layer according to the first embodiment. 
         FIG. 10  is a schematic cross-sectional view illustrating a configuration of a display device according to a comparative example. 
         FIG. 11  is an enlarged schematic cross-sectional view of a vicinity of an edge portion of the organic layer according to the first embodiment. 
         FIG. 12  is a diagram illustrating energy levels of each layer in a first path A 1 -A 2  illustrated in  FIG. 11 . 
         FIG. 13  is a diagram illustrating energy levels of each layer in a second path B 1 -B 2  illustrated in  FIG. 11 . 
         FIG. 14  is a diagram illustrating energy levels of each layer in a third path C 1 -C 2  illustrated in  FIG. 11 . 
         FIG. 15  is a schematic plan view of an organic layer according to a second embodiment. 
         FIG. 16  is a schematic cross-sectional view of the display device along XVI-XVI line in  FIG. 15 . 
         FIG. 17  is a schematic cross-sectional view of a display device according to a third embodiment. 
         FIG. 18  is a schematic cross-sectional view of a display device according to a fourth embodiment. 
         FIG. 19  is a schematic cross-sectional view of a display device according to a fifth embodiment. 
         FIG. 20  is a schematic cross-sectional view of a display device according to a sixth embodiment. 
         FIG. 21  is a schematic cross-sectional view of a display device according to a seventh embodiment. 
         FIG. 22  is a diagram schematically illustrating an example of the method for forming an organic layer according to the seventh embodiment. 
         FIG. 23  is a diagram illustrating an example of sub-pixels and organic layers according to an eighth embodiment. 
         FIG. 24  is a diagram for explaining an example of the effect of the eighth embodiment. 
         FIG. 25  is a schematic cross-sectional view of a display device according to a ninth embodiment. 
         FIG. 26  is a diagram illustrating energy levels of each layer included in an organic layer according to the ninth embodiment. 
         FIG. 27  is a schematic cross-sectional view of a display device according to a tenth embodiment. 
         FIG. 28  is a schematic plan view of a first carrier injection layer according to the tenth embodiment. 
         FIG. 29  is a diagram illustrating an example of a method for forming the first carrier injection layer according to the tenth embodiment. 
         FIG. 30  is a plan view illustrating another example of a first region and a second region according to the tenth embodiment. 
     
    
    
     DETAILED DESCRIPTION 
     In general, according to one embodiment, a display device comprising a first electrode, an organic layer disposed on the first electrode, and a second electrode covering the organic layer. The organic layer includes a first layer having a first edge portion and a second layer between the first layer and the second electrode. The second layer covers the first edge portion. 
     According to another embodiment, a display device comprising a first electrode, a rib having an opening overlapping with the first electrode and covering a peripheral portion of the first electrode, an organic layer that is in contact with the first electrode through the opening and has an edge portion located on the rib, and a second electrode covering the organic layer. At least one of a plurality of layers constituting the organic layer includes a first region that overlaps with the opening and in which a dopant is distributed at a first concentration, and a second region located on the rib and in which the dopant is distributed at a second concentration lower than the first concentration. 
     According to these structures, it is possible to provide a display device capable of suppressing performance degradation of a display element. 
     Embodiments will be described hereinafter with reference to the accompanying drawings. 
     The disclosure is merely an example, and proper changes within the spirit of the invention, which are easily conceivable by a skilled person, are included in the scope of the invention as a matter of course. In addition, in some cases, in order to make the description clearer, the widths, thicknesses, shapes, etc., of the respective parts are schematically illustrated in the drawings, compared to the actual modes. However, the schematic illustration is merely an example, and adds no restrictions to the interpretation of the invention. Besides, in the specification and drawings, the same or similar elements as or to those described in connection with preceding drawings or those exhibiting similar functions are denoted by like reference numerals, and a detailed description thereof is omitted unless otherwise necessary. 
     Note that, in order to make the descriptions more easily understandable, some of the drawings illustrate an X axis, a Y axis and a Z axis orthogonal to each other. A direction along the X axis is referred to as an X direction or a first direction, a direction along the Y axis is referred to as a Y direction or a second direction and direction along the Z axis is referred to as a Z direction or a third direction. A plane defined by the X axis and the Y axis is referred to as an X-Y plane, and a plane defined by the X axis and the Z axis is referred to as an X-Z plane. Further, viewing towards the X-Y plane is referred to as planar view. 
     A display device DSP according to a present embodiment is an organic electroluminescence display device including an organic light emitting diode (OLED) as a display element, and can be mounted on a television, a personal computer, an in-vehicle device, a tablet terminal, a smartphone, or a mobile phone terminal, as examples. 
     First Embodiment 
       FIG. 1  is a diagram illustrating a configuration example of a display device DSP according to a first embodiment. The display device DSP has a display region DA for displaying an image and a peripheral region SA outside the display region DA on an insulating base material  10 . The base material  10  may be glass or a flexible resin film. 
     The display region DA includes a plurality of pixels PX arrayed in a matrix in a first direction X and a second direction Y. Each of the pixels PX includes a plurality of sub-pixels SP. In one example, a pixel PX comprises a red sub-pixel SP 1 , a green sub-pixel SP 2 , and a blue sub-pixel SP 3 . The pixel PX may include four or more sub-pixels in which sub-pixel of other colors such as white are added in addition to the sub-pixels of the above three colors. 
     The sub-pixel SP includes a pixel circuit  1  and a display element  20  driven by the pixel circuit  1 . The pixel circuit  1  includes a pixel switch  2 , a drive transistor  3 , and a capacitor  4 . The pixel switch  2  and the drive transistor  3  are switching elements including, for example, a thin-film transistor. 
     In the pixel switch  2 , a gate electrode is connected to a scanning line GL. One of a source electrode and a drain electrode of the pixel switch  2  is connected to a signal line SL, and the other is connected to a gate electrode of the drive transistor  3  and the capacitor  4 . In the drive transistor  3 , one of a source electrode and a drain electrode is connected to a power supply line PL and the capacitor  4 , and the other is connected to an anode of the display element  20 . The configuration of the pixel circuit  1  is not limited to the illustrated example. 
     The display element  20  is an organic light emitting diode (OLED) as a light emitting element. For example, the sub-pixel SP 1  has a display element that emits light corresponding to a red wavelength, the sub-pixel SP 2  has a display element that emits light corresponding to a green wavelength, and the sub-pixel SP 3  has a display element that emits light corresponding to a blue wavelength. The configuration of the display element  20  will be described later. 
       FIG. 2  is a diagram illustrating an example of a layout of the sub-pixels SP 1 , SP 2 , and SP 3 . Here, attention is paid on four pixels PX. In each pixel PX, the sub-pixels SP 1 , SP 2 , and SP 3  are arranged in the first direction X in this order. That is, in the display region DA, a column including a plurality of the sub-pixels SP 1  arranged in the second direction Y, a column including a plurality of the sub-pixels SP 2  arranged in the second direction Y, and a column including a plurality of the sub-pixels SP 3  are alternately disposed in the first direction X. 
     A rib  14  is disposed at boundaries of the sub-pixels SP 1 , SP 2 , and SP 3 . In the example of  FIG. 2 , the rib  14  has a grid pattern having portions located between the sub-pixels adjacent to each other in the first direction X and portions located between the sub-pixels adjacent to each other in the second direction Y. The rib  14  forms an opening OP over each of the sub-pixels SP 1 , SP 2 , and SP 3 . 
     The outer shapes of the sub-pixels SP 1 , SP 2 , and SP 3  illustrated in  FIG. 2  correspond to, for example, an outer shape of a light emitting region of the display element  20 , but they are illustrated in a simplified manner and do not necessarily reflect the actual shape. 
       FIG. 3  is a schematic cross-sectional view of the display device DSP along line of  FIG. 2 . In  FIG. 3 , the drive transistor  3  and the display elements  20  are illustrated as elements disposed in the sub-pixels SP 1 , SP 2 , and SP 3 , and other elements are omitted. 
     The display device DSP includes the above-mentioned base material  10 , insulating layers  11 ,  12 , and  13 , the above-mentioned rib  14 , and a sealing layer  15 . The insulating layers  11 ,  12 , and  13  are stacked in a third direction Z on the base material  10 . For example, the insulating layers  11  and  12  are made of an inorganic material, and the insulating layer  13 , rib  14  and sealing layer  15  are made from organic materials. 
     Each of the drive transistors  3  includes a semiconductor layer  30  and electrodes  31 ,  32 ,  33 . The electrode  31  corresponds to a gate electrode. One of the electrodes  32  and  33  corresponds to a source electrode, and the other corresponds to a drain electrode. The semiconductor layer  30  is interposed between the base material  10  and the insulating layer  11 . The electrode  31  is interposed between the insulating layers  11  and  12 . The electrodes  32  and  33  are interposed between the insulating layers  12  and  13  and are in contact with the semiconductor layer  30  through contact holes penetrating the insulating layers  11  and  12 . 
     Each of the display elements  20  includes a first electrode E 1 , an organic layer OR, and a second electrode E 2 . The first electrode E 1  is an electrode disposed for each sub-pixel SP or for each display element  20 , and may be referred to as a pixel electrode, a lower electrode, or an anode. The second electrode E 2  is an electrode commonly disposed for a plurality of sub-pixels SP or a plurality of display elements  20 , and may be referred to as a common electrode, an upper electrode, or a cathode. 
     The rib  14  is disposed on the insulating layer  13 . Each first electrode E 1  is disposed on the insulating layer  13  and overlaps with each opening OP. A peripheral portion of the first electrode E 1  is covered with the rib  14 . Each first electrode E 1  is electrically connected to each electrode  33  through a contact hole CH penetrating the insulating layer  13 . For example, the first electrode E 1  is formed of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). The first electrode E 1  may be a metal electrode (reflecting electrode) formed of a metal material such as silver or aluminum. Further, the first electrode E 1  may be a stacked layer body of a transparent electrode and a metal electrode. For example, the first electrode E 1  may be configured as a stacked layer body in which a transparent electrode, a metal electrode, and a transparent electrode are stacked in this order, or may be configured as a stacked layer body having three or more layers. 
     The organic layer OR is disposed over the rib  14  and is in contact with the first electrode E 1  through the opening OP. A peripheral portion of each organic layer OR is located above the rib  14 . 
     The second electrode E 2  covers the organic layer OR. In the example of  FIG. 3 , the second electrode E 2  is continuously provided over the sub-pixels SP 1 , SP 2 , and SP 3 . The second electrode E 2  is formed of a transparent conductive material such as indium tin oxide or indium zinc oxide. The sealing layer  15  is disposed on the second electrode E 2 . The sealing layer  15  is formed to be thicker than, for example, the insulating layers  11 ,  12 ,  13  or the rib  14 , protects the organic layers OR from moisture and the like, and flattens unevenness generated by the rib  14 . 
       FIG. 4  is a cross-sectional view illustrating an example of a layer structure applicable to each of the organic layers OR. For example, the organic layer OR includes a first carrier injection layer  51 , a first carrier transport layer  52 , a first carrier blocking layer  53 , and an emitting layer  54  (EML), a second carrier blocking layer  55 , a second carrier transport layer  56  and a second carrier injection layer  57  stacked in this order from the first electrode E 1  to the second electrode E 2 . 
     In this embodiment, it is assumed that the first electrode E 1  is the anode and the second electrode E 2  is the cathode. For example, in this case, the first carrier injection layer  51  is a hole-injection layer (HIL) that generates holes, and the first carrier transport layer  52  is a hole-transport layer (HTL) that transports the holes toward the emitting layer  54 , the first carrier blocking layer  53  is an electron-blocking layer (EBL) that blocks the movement of electrons, and the second carrier blocking layer  55  is a hole-blocking layer (HBL) that blocks the movement of holes. The second carrier transport layer  56  is an electron-transport layer (ETL) that transports the electrons toward the emitting layer  54 , and the second carrier injection layer  57  is an electron-injection layer (EIL) that generates the electrons. 
       FIG. 5  is a schematic plan view of the organic layer OR.  FIG. 6  is a schematic cross-sectional view of the display device DSP along line VI-VI in  FIG. 5 . In  FIG. 5 , the shape of the organic layer OR in planar view is illustrated in a region on a left side of a center line CL in a first direction X of a sub-pixel SP (display element  20 ), and the outer shapes of each layer  51  to  57  of the organic layer OR and the opening OP are illustrated in a region on a right side of the center line CL. 
     The first carrier injection layer  51  has an edge portion S 1 , the first carrier transport layer  52  has an edge portion S 2 , the first carrier blocking layer  53  has an edge portion S 3 , and the emitting layer  54  has an edge portion S 4 . The second carrier blocking layer  55  has an edge portion S 5 , the second carrier transport layer  56  has an edge portion S 6 , and the second carrier injection layer  57  has an edge portion S 7 . The edge portions S 1  to S 7  can be restated as, for example, an edge, an outer circumference, or an outer shape. In the example of  FIG. 5 , the edge portions S 1  and S 2  are represented by a single line for simplification of the illustration. Similarly, the edge portions S 6  and S 7  are also represented by a single line. 
     In the example of  FIG. 5 , each layer  51  to  57  and the opening OP are rectangle. That is, the edge portions S 1  to S 7  and the opening OP each have two sides parallel to the first direction X and two sides parallel to the second direction Y. 
     In planar view, the edge portions S 1  and S 2  are located between the edge portion S 4  and the edge portion S 5 , the edge portion S 4  is located between the edge portions S 1 , S 2  and the edge portions S 6 , S 7 , and the edge portion S 5  is located between the edge portions S 1 , S 2  and the edge portion S 3 , and the edge portions S 6 , S 7  are located between the edge portion S 4  and the opening OP. The edge portion S 3  corresponds to the outermost circumference of the organic layer OR. 
     From another point of view, the area of the second carrier blocking layer  55  is greater than the areas of the first carrier injection layer  51 , the first carrier transport layer  52 , the emitting layer  54 , the second carrier transport layer  56 , and the second carrier injection layer  57 . Further, the area of the first carrier blocking layer  53  is larger than the area of the second carrier blocking layer  55 . 
     As shown in  FIG. 6 , the edge portions S 1  to S 7  are all located on the rib  14 . The first carrier injection layer  51  is in contact with the first electrode E 1  through the opening OP. The first carrier transport layer  52  is generally located above the first carrier injection layer  51 . 
     Most of the first carrier blocking layer  53  is located above the first carrier transport layer  52 , and a portion near the edge portion S 3  is in contact with the rib  14 . That is, the first carrier blocking layer  53  covers the edge portion S 1  of the first carrier injection layer  51  and the edge portion S 2  of the first carrier transport layer  52 . 
     The emitting layer  54  is generally located on the first carrier blocking layer  53 . Most of the second carrier blocking layer  55  is located above the emitting layer  54 , and a portion near the edge portion S 5  is in contact with the first carrier blocking layer  53 . That is, the second carrier blocking layer  55  covers the edge portion S 4  of the emitting layer  54 . 
     The second carrier transport layer  56  is generally located above the second carrier blocking layer  55 . The second carrier injection layer  57  is generally located above the second carrier transport layer  56 . 
     The edge portions S 1  and S 2  are not in contact with the second electrode E 2  because they are covered with the first carrier blocking layer  53 . Further, the edge portion S 4  is not in contact with the second electrode E 2  because it is covered with the second carrier blocking layer  55 . 
     The edge portion S 3  of the first carrier blocking layer  53  and its vicinity are in contact with the second electrode E 2 . The edge portion S 5  of the second carrier blocking layer  55  and its vicinity are in contact with the second electrode E 2 . 
     The edge portion S 6  is in contact with the second electrode E 2 . The second carrier injection layer  57  is in contact with the second electrode E 2  on the upper surface and the edge portion S 7  thereof. In  FIG. 6 , the cross-section in an X-Z plane defined by the first direction X and the third direction Z is illustrated, but a cross section of a Y-Z plane defined by the second direction Y and the third direction Z also has a same structure. 
     Next, an example of a method for manufacturing the display device DSP will be described focusing on a step of forming an organic layer OR. Each layer constituting the organic layer OR can be formed, for example, by vacuum vapor deposition using a point vapor deposition source. 
       FIG. 7  is a diagram schematically illustrating an example of a method for forming the organic layer OR. This forming method includes a first step P 11  and a second step P 12 . A layer having a relatively small area in the organic layer OR, such as the first carrier injection layer  51 , the first carrier transport layer  52 , the emitting layer  54 , the second carrier transport layer  56 , and the second carrier injection layer  57 , is formed by the first step P 11 . A layer having a relatively large area in the organic layer OR, such as the first carrier blocking layer  53  and the second carrier blocking layer  55 , is formed by the second step P 12 . 
     In each of the first step P 11  and the second step P 12 , masks MSK each having an opening corresponding to each organic layer OR are opposed on the substrate SUB in which a lower layer portion of the display device DSP is formed below the organic layers OR. The masks MSK used in the first step P 11  and the second step P 12  are the same. In the first step P 11 , the substrate SUB moves relative to a vapor deposition source DS 1  arranged below the masks MSK at a speed V 1 . In the second step P 12 , the substrate SUB moves relative to a vapor deposition source DS 2  arranged below the masks MSK at a speed of V 2 . 
     The range in which molecules from the vapor deposition source DS 2  reach the substrate SUB through the opening of each mask MSK in the second step P 12  is larger than the range in which molecules from the vapor deposition source DS 1  reach the substrate SUB through the opening of each mask MSK in the first step P 11 . As a result, an area difference ΔS is generated between the layers formed in the first step P 11  and the second step P 12 , respectively. The first step P 11  may be referred to as narrow-angle vapor deposition, and the second step P 12  may be referred to as wide-angle vapor deposition. 
     The first step P 11  and the second step P 12  that generate such an area difference ΔS can be realized by adjusting various parameters related to vapor deposition. Examples of the parameters include a distance d 1  between the substrate SUB and the vapor deposition sources DS 1  or DS 2 , a distance d 2  between the substrate SUB and the mask MSK, a size of holes provided in the vapor deposition sources DS 1  and DS 2 , and the speeds V 1  and V 2 , an angle θ of the vapor deposition sources with respect to a vertical direction of the substrate SUB, the number of each of the vapor deposition sources DS 1  and DS 2 , and a density at which the vapor deposition sources DS 1  and DS 2  are arranged. 
       FIG. 8  is a diagram illustrating other examples (a), (b), and (c) of the above parameters. In Examples (a), (b), and (c), three vapor deposition source DSs are illustrated, and the angles of these vapor deposition source DSs are different. In Example (a), the three vapor deposition sources DS are parallel to each other. In Example (b), each vapor deposition source DS is tilted so that a distance between the vapor deposition sources DS increases toward a distal part side where molecules are released. In Example (c), each vapor deposition source DS is tilted so that a distance between the vapor deposition source DSs decreases toward a distal part side where molecules are released. 
     In the first step P 11  and the second step P 12 , the arrangement mode of the vapor deposition sources DS 1  and DS 2  may be changed as in the vapor deposition sources DS of Examples (a), (b), and (c). For example, by applying Example (c) to the vapor deposition source DS 1  in the first step P 11  and applying any of Examples (a) and (b) to the vapor deposition source DS 2  in the second step P 12 , it is possible to generate an area difference ΔS. 
       FIG. 9  is a diagram schematically illustrating another example of the method of forming an organic layer OR. This forming method includes a first step P 21  and a second step P 22 . A layer having a relatively small area in the organic layer OR, such as the first carrier injection layer  51 , the first carrier transport layer  52 , the emitting layer  54 , the second carrier transport layer  56 , and the second carrier injection layer  57 , is formed by the first step P 21 . A layer having a relatively large area in the organic layer OR, such as the first carrier blocking layer  53  and the second carrier blocking layer  55 , is formed by the second step P 22 . 
     In the first step P 21 , masks MSK 1  each having an opening corresponding to each organic layer OR are used. In the second step P 22 , masks MSK 2  each having an opening larger than the opening of the masks MSK 1  is used. In  FIG. 9 , vapor deposition sources are omitted. 
     Due to a difference in size of the openings of the masks MSK 1  and MSK 2 , molecules from the vapor deposition sources reach a wider area of the substrate SUB in the second step P 22  than in the first step P 21 . As a result, an area difference ΔS is generated between the layers formed in the first step P 11  and the second step P 12 , respectively. 
     According to the forming methods described with reference to  FIGS. 7 and 9 , it is possible to form a layer having an area difference ΔS. Further, for example, in the forming method of  FIG. 7 , three or more layers having an area difference from each other can be formed by going through three or more steps having different parameters related to vapor deposition. Similarly, in the forming method of  FIG. 9 , even when three or more steps using masks having different opening sizes are performed, three or more layers having an area difference from each other can be formed. By appropriately using such a method, it is possible to form the organic layer OR illustrated in  FIGS. 5 and 6 . 
     Subsequently, an example of the effect exerted by this embodiment will be described. 
       FIG. 10  is a schematic cross-sectional view illustrating a configuration of a display device DSPa according to a comparative example. This cross section corresponds to a cross section of a sub-pixel SP (display element  20 ) similar to that in  FIG. 6 . In  FIG. 10 , elements that are the same as or similar to the elements illustrated in  FIG. 6  are designated by the same reference numerals. 
     In the display device DSPa, the smaller the layers  51  to  57  constituting an organic layer OR are located above. As a result, each of edge portions S 1  to S 7  is in contact with a second electrode E 2 . Therefore, unlike an original current path that passes through each layer  51  to  57  in order between the first electrode E 1  and the second electrode E 2 , a leak path where the first electrode E 1  reaches the second electrode E 2  through a part of each layer  51  to  57 , can be formed. The leak path causes an increase in energy consumption due to an off-leak current or an electric leakage, and degradation in the drive performance of a display element  20 . 
     In particular, when each layer  51  to  57  of the organic layer OR is formed by using a single mask, the material of each layer is also deposited on the edge of the opening of the mask, so that an area formed becomes smaller as the layer is formed later. Therefore, as shown in  FIG. 10 , a structure in which each of the edge portions S 1  to S 7  is in contact with the second electrode E 2  is likely to be formed. 
       FIG. 11  is a schematic cross-sectional view of the display device DSP according to the present embodiment in which a vicinity of an edge portion of the organic layer OR is enlarged. As described above, in the present embodiment, the edge portion S 1  of the first carrier injection layer  51  and the edge portion S 2  of the first carrier transport layer  52  are covered with the first carrier blocking layer  53 . Further, the edge portion S 4  of the emitting layer  54  is covered with the second carrier blocking layer  55 . 
     Here, attention is paid to a first path A 1 -A 2 , a second path B 1 -B 2 , and a third path C 1 -C 2  in  FIG. 11 . The first path A 1 -A 2  passes through the first electrode E 1 , each layer  51  to  57  and the second electrode E 2 . The second path B 1 -B 2  passes through the first electrode E 1 , the first carrier injection layer  51 , the first carrier blocking layer  53 , the second carrier blocking layer  55 , and the second electrode E 2 . The third path C 1 -C 2  passes through the first electrode E 1 , the first carrier injection layer  51 , the first carrier blocking layer  53 , and the second electrode E 2 . 
       FIG. 12  is a diagram illustrating energy levels of each layer in the first path A 1 -A 2 .  FIG. 13  is a diagram illustrating energy levels of each layer in the second path B 1 -B 2 .  FIG. 14  is a diagram illustrating the energy levels of each layer in the third path C 1 -C 2 . 
     As shown in  FIG. 12 , in the first path A 1 -A 2 , electrons are shielded by the first carrier blocking layer  53  and holes are shielded by the second carrier blocking layer  55 . Similarly, in the second path B 1 -B 2  illustrated in  FIG. 13 , electrons are shielded by the first carrier blocking layer  53  and holes are shielded by the second carrier blocking layer  55 . Therefore, a leakage current is suppressed in the second path B 1 -B 2 . 
     On the other hand, in the third path C 1 -C 2  illustrated in  FIG. 14 , electrons are shielded by the first carrier blocking layer  53 , but holes can flow to the second electrode E 2 . Even in this case, the leakage current is suppressed at least by shielding the electrons. Further, in the third path C 1 -C 2 , the absence of the first carrier transport layer  52  acts as an energy barrier. 
     Not limited to the first path A 1 -A 2 , the second path B 1 -B 2 , and the third path C 1 -C 2 , in this embodiment, there is at least one of the first carrier blocking layer  53  with the lowest unoccupied molecular orbital (LUMO) and the second carrier blocking layer  55  with the deep highest occupied molecular orbital (HOMO) in any of the paths passing through the first electrode E 1 , the organic layer OR, and the second electrode E 2 . This enables effective leak countermeasures. 
     In addition to the above, various suitable effects can be obtained from the present embodiment. 
     Hereinafter, a second to tenth embodiments will be disclosed as other examples applicable to the display device DSP. The same configuration as in the first embodiment can be applied to the configurations not mentioned in each embodiment. Elements that are the same as or similar to the elements disclosed in the first embodiment are designated by the same reference numerals, and the description thereof may be omitted. 
     Second Embodiment 
       FIG. 15  is a schematic plan view of an organic layer OR according to a second embodiment.  FIG. 16  is a schematic cross-sectional view of a display device DSP along line XVI-XVI in  FIG. 15 . In  FIG. 15 , similarly to  FIG. 5 , the shape in which the organic layer OR is viewed in planar view is illustrated in a region on a left side of a center line CL in a first direction X of a sub-pixel SP (display element  20 ), and the outer shapes of each layer  51  to  57  of the organic layer OR and an opening OP are illustrated in a region on a right side of the center line CL. 
     The organic layer OR illustrated in  FIG. 15  differs from the organic layer OR illustrated in  FIG. 5  in that the area of a second carrier blocking layer  55  is larger than the area of a first carrier blocking layer  53 . In planar view, edge portions S 1  and S 2  are located between edge portions S 3  and S 4 , the edge portion S 3  is located between the edge portions S 1 , S 2  and an edge portion S 5 , and the edge portion S 4  is located between the edge portions S 1 , S 2  and edge portions S 6 , S 7 , and the edge portions S 6 , S 7  are located between the edge portion S 4  and the opening OP. The edge portion S 5  corresponds to the outermost circumference of the organic layer OR. 
     As shown in  FIG. 16 , the second carrier blocking layer  55  is mostly located above an emitting layer  54 , and a portion near the edge portion S 5  is in contact with the first carrier blocking layer  53  and a rib  14 . That is, the second carrier blocking layer  55  covers the edge portion S 4  of the emitting layer  54  and the edge portion S 3  of the first carrier blocking layer  53 . The edge portions S 1  to S 4  are not in contact with a second electrode E 2 . The edge portion S 5  of the second carrier blocking layer  55  and a portion in the vicinity thereof are in contact with the second electrode E 2 . Although the cross section in an X-Z plane is illustrated in  FIG. 16 , a cross section in a Y-Z plane has a similar structure. In forming the organic layer OR, for example, the forming method disclosed in the first embodiment can be appropriately used. 
     In the configuration of the present embodiment, a path between a first electrode E 1  and the second electrode E 2  passes through the first carrier blocking layer  53  and the second carrier blocking layer  55  at any position of the organic layer OR. Therefore, a leakage current can be suppressed more effectively. 
     Third Embodiment 
       FIG. 17  is a schematic cross-sectional view of a display device DSP according to a third embodiment. In the example of  FIG. 17 , a first carrier transport layer  52  covers an edge portion S 1  of a first carrier injection layer  51 , a first carrier blocking layer  53  covers an edge portion S 2  of the first carrier transport layer  52 , and an emitting layer  54  covers an edge portion S 3  of the first carrier blocking layer  53 , a second carrier blocking layer  55  covers an edge portion S 4  of the emitting layer  54 , a second carrier transport layer  56  covers an edge portion S 5  of the second carrier blocking layer  55 , and a second carrier injection layer  57  covers an edge portion S 6  of the second carrier transport layer  56 . In each layer  51  to  57 , a portion near the edge portions S 1  to S 7  is in contact with a rib  14 . The second carrier injection layer  57  is in contact with a second electrode E 2  as a whole, but the other layers  51  to  56  are not in contact with the second electrode E 2 . 
     Although the cross section in an X-Z plane is illustrated in  FIG. 17 , a cross section in a Y-Z plane has a similar structure. That is, the area of each layer  51  to  57  is larger as the layer is closer to the second electrode E 2 . In forming the organic layer OR, for example, the forming method disclosed in the first embodiment can be appropriately used. 
     In the configuration of the present embodiment, the second carrier injection layer  57  is in contact with the second electrode E 2 , and the other layers  51  to  56  are out of contact with the second electrode E 2 . Further, the path between the first electrode E 1  and the second electrode E 2  passes through all the layers  51  to  57  at any position of the organic layer OR. Thereby, a leakage current can be suppressed more effectively. 
     The second carrier injection layer  57  is located at the top of the organic layer OR. Therefore, when the second carrier injection layer  57  is expanded as in the present embodiment, it is possible to cover all the edge portions S 1  to S 6  of the other layers  51  to  56 . 
     The edge portions S 1  to S 6  may have the same positional relationship as in  FIG. 6  or  FIG. 16 . Even in this case, since at least the second carrier injection layer  57  is interposed between these edge portions S 1  to S 6  and the second electrode E 2 , the effect of suppressing the leak current can be expected. 
     Fourth Embodiment 
       FIG. 18  is a schematic cross-sectional view of a display device DSP according to a fourth embodiment. In the example of  FIG. 18 , a first carrier transport layer  52  covers an edge portion S 1  of a first carrier injection layer  51 . As a result, the first carrier injection layer  51  is not in contact with a second electrode E 2 . 
     On the other hand, an edge portion S 2  of the first carrier transport layer  52 , an edge portion S 3  of a first carrier blocking layer  53 , an edge portion S 4  of an emitting layer  54 , an edge portion S 5  of a second carrier blocking layer  55  and an edge portion S 6  of a second carrier transport layer  56  are in contact with the second electrode E 2 . 
     Although the cross section in an X-Z plane is illustrated in  FIG. 18 , a cross section in a Y-Z plane has a similar structure. That is, the area of the first carrier transport layer  52  is larger than the area of the other layers  51  to  57 . In forming the organic layer OR, for example, the forming method disclosed in the first embodiment can be appropriately used. 
     In the present embodiment, a first electrode E 1  is a reflecting electrode that reflects light emitted by the emitting layer  54 . Further, the first carrier transport layer  52  also has a role as an optical adjustment layer. Specifically, in order to adjust a relationship between the wavelength of light emitted upward by the emitting layer  54  and the wavelength of light reflected upward by the first electrode E 1 , the first carrier transport layer  52  is provided with a thickness T greater than that of the other layers  51 , and  53  to  57 . 
     With such a configuration, a path between the first electrode E 1  and the second electrode E 2  passes through the first carrier transport layer  52  which is thick at any position of the organic layer OR. Thereby, a leakage current can be effectively suppressed. 
     Fifth Embodiment 
       FIG. 19  is a schematic cross-sectional view of a display device DSP according to a fifth embodiment. In the example of  FIG. 19 , a second carrier transport layer  56  covers an edge portion S 1  of a first carrier injection layer  51 , an edge portion S 2  of a first carrier transport layer  52 , an edge portion S 3  of a first carrier blocking layer  53 , an edge portion S 4  of an emitting layer  54 , and an edge portion S 5  of a second carrier blocking layer  55 . The edge portion S 6  of the second carrier transport layer  56  is not covered by the second carrier injection layer  57 . In the second carrier transport layer  56 , the edge portion S 6  and a portion in the vicinity thereof are in contact with a rib  14  and a second electrode E 2 . Each layer  51  to  55  below the second carrier transport layer  56  is not in contact with the second electrode E 2 . 
     Although the cross section in an X-Z plane is illustrated in  FIG. 19 , a cross section in a Y-Z plane has a similar structure. That is, the area of the second carrier transport layer  56  is larger than the area of the other layers  51  to  55 , and  57 . In forming the organic layer OR, for example, the forming method disclosed in the first embodiment can be appropriately used. 
     As the second carrier injection layer  57 , a thin film of a metal compound is generally used. Therefore, when the second carrier injection layer  57  located at the uppermost position in the organic layer OR is expanded, the edge portions S 1  to S 6  of the other layers  51  to  56  may not be covered well. On the other hand, the second carrier transport layer  56  is formed thicker than the second carrier injection layer  57  by an inorganic material or an organic material. Therefore, the second carrier transport layer  56  is suitable for covering the edge portions S 1  to S 5 . 
     Sixth Embodiment 
     In the first to fifth embodiments, it is assumed that the edge portions S 1  to S 7  of each layer  51  to  57  have the same relationship over the entire outer circumference of the organic layer OR. However, the relationship between the edge portions S 1  to S 7  in a part of the outer shape of the organic layer OR and the relationship between the edge portions S 1  to S 7  in the other part may be different. 
       FIG. 20  is a schematic cross-sectional view of a display device DSP according to a sixth embodiment, and illustrates an example of a configuration in which the relationship between edge portions S 1  to S 7  is partially different in the outer shape of an organic layer OR. The edge portion S 1  has a first side S 1   a  and a second side S 1   b.  The edge portion S 2  has a first side S 2   a  and a second side S 2   b.  The edge portion S 3  has a first side S 3   a  and a second side S 1   b.  The edge portion S 4  has a first side S 4   a  and a second side S 4   b.  The edge portion S 5  has a first side S 5   a  and a second side S 5   b.  The edge portion S 6  has a first side S 6   a  and a second side S 6   b.  The edge portion S 7  has a first side S 7   a  and a second side S 7   b.  All of these sides are parallel to the second direction Y. 
     In the example of  FIG. 20 , the first sides S 1   a  to S 7   a  have the same relationship as that of the edge portions S 1  to S 7  illustrated in  FIG. 6 , and the second sides S 1   b  to S 7   b  have the same relationship as that of the edge portions S 1  to S 7  illustrated in  FIG. 16 . The first side S 3   a  is not covered with a second carrier blocking layer  55 . The second side S 3   b  is covered with the second carrier blocking layer  55 . Not limited to this example, the relationships illustrated in each embodiment can be selectively applied to the first sides S 1   a  to S 7   a  and the second sides S 1   b  to S 7   b.    
     Although the cross section in an X-Z plane is illustrated in  FIG. 20 , the same structure can be applied to a cross section in a Y-Z plane. That is, the relationships illustrated in each embodiment may be selectively applied to each of the pair of sides parallel to the first direction X among the edge portions S 1  to S 7 . 
     Seventh Embodiment 
     The first to sixth embodiments illustrates examples of a configuration in which among the layers  51  to  57  constituting the organic layer OR, a layer other than the first carrier injection layer  51  located at the bottom is expanded to cover the edge portion of a layer below the expanded layer. In the present embodiment, a configuration of an organic layer OR and a method for forming the organic layer OR are exemplified from a viewpoint of suppressing a contact between a specific layer and a second electrode E 2  by reducing the specific layer. 
       FIG. 21  is a schematic cross-sectional view of a display device DSP according to a seventh embodiment. 
     In the example of  FIG. 21 , an emitting layer  54  is smaller than other layers  51  to  53 , and  55  to  57 . An edge portion S 4  of the emitting layer  54  is covered with a second carrier blocking layer  55  and is not in contact with a second electrode E 2 . Edge portions S 1  to S 3  and S 5  to S 7  of the other layers  51  to  53 , and  55  to  57  are in contact with the second electrode E 2 . 
       FIG. 22  is a diagram schematically illustrating an example of the method for forming the organic layer OR. In this forming method, each layer  51  to  57  is formed by using polymer masks PMSK and metal masks MMSK on a substrate SUB in which a lower layer portion below the organic layer OR is formed in the display device DSP. Each polymer mask PMSK is opposed on a base layer BL formed on the substrate SUB and has an opening corresponding to the organic layer OR. Each metal mask MMSK has an opening smaller than that of the polymer mask PMSK, and there is an area difference ΔS between the openings of both masks. 
     A first carrier injection layer  51 , a first carrier transport layer  52 , and a first carrier blocking layer  53  below an emitting layer  54  are formed through the opening of the polymer mask PMSK by vapor deposition in a state where the metal mask MMSK is not opposed. Subsequently, the metal mask MMSK is opposed on top of the polymer mask PMSK. The emitting layer  54  is formed by vapor deposition through the opening of the metal mask MMSK. After that, the metal mask MMSK is removed. A second carrier blocking layer  55 , a second carrier transport layer  56 , and a second carrier injection layer  57  above the emitting layer  54  are formed by vapor deposition through the opening of the polymer mask PMSK. By forming each of the layers  51  to  57  in this way, the emitting layer  54  can be made smaller than the other layers  51  to  53 , and  55  to  57 . 
     The organic layer OR illustrated in  FIG. 21  can also be formed by the method illustrated in  FIG. 7 . That is, the emitting layer  54  may be formed by the first step P 11 , and the other layers  51  to  53 ,  55  to  57  may be formed by the second step P 12 . 
     The organic layer OR illustrated in  FIG. 21  can also be formed by the method illustrated in  FIG. 9 . That is, the emitting layer  54  may be formed by the first step P 21 , and the other layers  51  to  53 , and  55  to  57  may be formed by the second step P 22 . 
     Eighth Embodiment 
     In the first embodiment, it is assumed that each sub-pixel SP has a rectangular organic layer OR as illustrated in  FIG. 5 . In this embodiment, another example of an organic layer OR disposed in a display region DA is disclosed. 
       FIG. 23  is a diagram illustrating an example of sub-pixels SP and an organic layer OR according to the present embodiment. Similar to the example of  FIG. 2 , in the display region, a plurality of sub-pixels SP 1  are arranged in the second direction Y, a plurality of sub-pixels SP 2  are arranged in the second direction Y, and a plurality of sub-pixels SP 3  are arranged in the second direction Y. 
     Further, dummy sub-pixels DP 1 , DP 2 , and DP 3  are disposed in a peripheral region SA. The dummy sub-pixels DP 1 , DP 2 , and DP 3  are arranged in the second direction Y with the sub-pixels SP 1 , SP 2 , and SP 3  disposed at the end of the display region DA in the second direction Y, respectively. The dummy sub-pixels DP 1 , DP 2 , and DP 3  are pixels that do not contribute to image display. For example, the dummy sub-pixels DP 1 , DP 2 , and DP 3  include a first electrode E 1  and do not include a pixel circuit  1 . Alternatively, the dummy sub-pixels DP 1 , DP 2 , and DP 3  include the first electrode E 1  and the pixel circuit  1 , but the first electrode E 1  and the pixel circuit  1  are not connected to each other. In the example of  FIG. 23 , the organic layer OR is continuously disposed over the plurality of sub-pixels SP. Specifically, an organic layer OR 1  that emits red light is disposed over the plurality of sub-pixels SP 1  and the dummy sub-pixel DPI that are arranged in the second direction Y, an organic layer OR 2  that emits green light is disposed over the plurality of sub-pixels SP 2  and the dummy sub-pixel DP 2  that are arranged in the second direction Y, and an organic layer OR 3  that emits blue light is disposed over the plurality of sub-pixels SP 3  and the dummy sub-pixel DP 3  arranged in the second direction Y. The organic layers OR 1 , OR 2 , and OR 3  are arranged at intervals in the first direction X. 
     The organic layers OR 1 , OR 2 , and OR 3  have a pair of sides Sa and Sb parallel to the second direction Y and a pair of sides Sc and Sd parallel to the first direction X. The sides Sa and Sb are located in both the display region DA and the peripheral region SA. The sides Sc and Sd are located in the peripheral region SA and not in the display region DA. 
       FIG. 24  is a diagram for explaining an example of the effect of the present embodiment.  FIG. 24  illustrates a process of forming an organic layer OR using a linear vapor deposition source LDS on a substrate SUB in which a lower layer portion than the organic layer OR (OR 1 , OR 2 , OR 3 ) of the display device DSP is formed. A mask used for the vapor deposition is not illustrated. 
     The linear vapor deposition source LDS has a plurality of holes arranged in the second direction Y, and molecules for forming each layer  51  to  57  are emitted from these holes. The substrate SUB moves in a sweep direction D, which exposes the entire substrate SUB to the molecules emitted from the linear vapor deposition source LDS. The sweep direction D is parallel to the first direction X. 
     For example, when the first step P 11  and the second step P 12  illustrated in  FIG. 7  are carried out in the manner illustrated in  FIG. 24  to form an island-shaped organic layer OR similar to that in  FIG. 5 , a difference in the outer shape of the formed layers between the first step P 11  and the second step P 12  mainly appears on a side intersecting the sweep direction D, that is, a pair of sides parallel to the second direction Y. Regarding a side parallel to the sweep direction D, that is, a pair of sides parallel to the first direction X, a difference in position may not appear sufficiently. 
     In this regard, in the configuration illustrated in  FIG. 23 , the organic layer OR does not have sides Sc and Sd parallel to the first direction X in the display region DA. Regarding the sides Sa and Sb parallel to the second direction Y, for example, as illustrated in  FIGS. 6, 16 and 17 to 21 , shapes in which the edge portions S 1  to S 7  of each layer  51  to  57  have different positions can be preferably realized. 
     The sides Sc and Sd are located in the peripheral region SA, and dummy sub-pixels DP 1 , DP 2  and DP 3  are interposed between the sides Sc and Sd and the display region DA. As a result, even if shape defects of the layers  51  to  57  of the organic layer OR occur on the sides Sc and Sd, the influence is unlikely to affect the sub-pixels SP 1 , SP 2 , and SP 3 . 
     Ninth Embodiment 
     The layer structure of an organic layer OR is not limited to that illustrated in  FIG. 4 . In the organic layer OR, any one of each layer  51  to  57  may be omitted. Further, the organic layer OR may include layers having other functions in addition to the layers  51  to  57 . Further, the organic layer OR may have a tandem structure including two emitting layers. 
       FIG. 25  is a schematic cross-sectional view of a display device DSP provided with an organic layer OR having a tandem structure. The organic layer OR has a first organic layer  100  in contact with a first electrode E 1 , a second organic layer  200  in contact with a second electrode E 2 , and a middle layer  300  located between the first organic layer  100  and the second organic layer  200 . 
     An edge portion S 100  of the first organic layer  100 , an edge portion S 200  of the second organic layer  200 , and an edge portion S 300  of the middle layer  300  are all located on a rib  14 . In the example of  FIG. 25 , the edge portion S 300  is covered with the second organic layer  200 . As a result, the middle layer  300  is not in contact with the second electrode E 2 . 
       FIG. 26  is a diagram illustrating energy levels of each layer included in the organic layer OR according to the present embodiment. The first organic layer  100  includes a first carrier injection layer  101 , a first carrier transport layer  102 , a first carrier blocking layer  103 , a first emitting layer  104  (EML), a second carrier blocking layer  105 , and a second carrier transport layer  106 . The second organic layer  200  includes a third carrier transport layer  201 , a third carrier blocking layer  202 , a second emitting layer  203  (EML), a fourth carrier blocking layer  204 , a fourth carrier transport layer  205 , and a second carrier injection layer  206 . The middle layer  300  is located between the second carrier transport layer  106  and the third carrier transport layer  201 . 
     In this embodiment, it is assumed that the first electrode E 1  is the anode and the second electrode E 2  is the cathode. For example, in this case, the first carrier injection layer  101  is a hole-injection layer (HIL), the first carrier transport layer  102  and the third carrier transport layer  201  are hole-transport layers (HTL), and the first carrier blocking layer  103  and the third carrier blocking layer  202  are electron-blocking layers (EBL), the second carrier blocking layer  105  and the fourth carrier blocking layer  204  are hole-blocking layers (HBL), the second carrier transport layer  106  and the fourth carrier transport layer  205  are electron-transport layers (ETL), and the second carrier injection layer  206  is an electron-injection layer (EIL). Further, the middle layer  300  is, for example, a charge generation layer (CGL) that generates electrons and holes according to a voltage. 
     The middle layer  300 , which is the charge generation layer, is formed of, for example, a metal material, and when it comes into contact with the second electrode E 2 , a leakage current is likely to occur. Further, when a leak current is generated via the middle layer  300 , only one of the first emitting layer  104  and the second emitting layer  203  can emit light. Therefore, as illustrated in  FIG. 25 , it is preferable that the edge portion S 300  of the middle layer  300  is covered with any of the layers constituting the second organic layer  200 . 
     The layer covering the edge portion S 300  is, for example, one, multiple or all of the third carrier transport layer  201 , the third carrier blocking layer  202 , the fourth carrier blocking layer  204 , the fourth carrier transport layer  205 , and the second carrier injection layer  206 . Further, the same configuration as the organic layer OR exemplified in each of the above-described embodiments may be applied to either or both of the first organic layer  100  and the second organic layer  200 . 
     The organic layer OR may include three or more organic layers including an emitting layer, and a middle layer interposed between the organic layers. Also in this case, the same effect as that of the present embodiment can be obtained by covering the edge portion of each middle layer with the upper layer. 
     Tenth Embodiment 
       FIG. 27  is a schematic cross-sectional view of a display device DSP according to a tenth embodiment. In the example of  FIG. 27 , each of layers  51  to  57  constituting an organic layer OR has the same shape as the example of  FIG. 6 . 
     A first carrier injection layer  51  has a first region  51   a  and a second region  51   b  located between the first region  51   a  and an edge portion S 1 . In the first region  51   a,  a dopant (for example, a p-type dopant) is distributed at a first concentration with respect to a host (main material). In the second region  51   b,  a dopant is distributed to the host at a second concentration lower than the first concentration. The first region  51   a  overlaps an opening OP and is in contact with a first electrode E 1 . The second region  51   b  is located above the rib  14 . 
       FIG. 28  is a schematic plan view of the first carrier injection layer  51 . Here, it is assumed that the first carrier injection layer  51  is rectangle as in the example of  FIG. 5 . In the example of  FIG. 28 , the first region  51   a  is, for example, a rectangle that overlaps the entire opening OP. The second region  51   b  has a frame shape surrounding the first region  51   a.    
       FIG. 29  is a diagram illustrating an example of a method for forming the first carrier injection layer  51 . A mask MSK having an opening corresponding to the organic layer OR is opposed on a substrate SUB in which a lower layer portion of the display device DSP is formed below the organic layer OR. 
     The host of the first carrier injection layer  51  is formed by a vapor deposition source DS 1 . The host is doped with a dopant by a vapor deposition source DS 2 . Similar to the first step P 11  and the second step P 12  illustrated in  FIG. 7 , a range in which molecules from the vapor deposition source DS 2  reach the substrate SUB through the opening of the mask MSK is larger than a range in which molecules from the vapor deposition source DS 1  reach the substrate SUB through the opening. This makes it possible to form a first carrier injection layer  51  having a first region  51   a  and a second region  51   b  around it. 
     Since the concentration of the dopant in the second region  51   b  is lower than the concentration of the dopant in the first region  51   a,  the second region  51   b  has a higher resistance than that of the first region  51   a.  Therefore, in the configuration of the present embodiment, a leakage current in a path from the first carrier injection layer  51  through the edge portion S 1  and a portion in the vicinity thereof to the second electrode E 2  is suppressed. 
     Generally, the dopant material is active, and there is a concern that it may be deteriorated by the atmosphere. Such deterioration is likely to occur in the vicinity of the edge portion S 1 . With the configuration of the present embodiment, since the concentration of the dopant in the second region  51   b  is low, such deterioration can be suppressed. 
     In this embodiment, in a case where each layer  51  to  57  has the same shape as the example of  FIG. 6 , an example of forming a first region  51   a  and a second region  51   b  in the first carrier injection layer  51  is illustrated. The first region and the second region do not necessarily have to be formed in the first carrier injection layer  51 , and may be formed in any of the other layers  52  to  57 . Further, the first region and the second region may be formed in two or more layers out of the layers  51  to  57 . Further, the first region and the second region may be provided for the organic layer OR having the shape illustrated in  FIG. 10 ,  FIGS. 16 to 21 , or  FIG. 25 . 
     Each layer  51  to  57  may be provided with not only two regions of a first region and a second region, but also more regions having different dopant concentrations. In this case, for example, the concentration of the dopant may be lowered in a region closer to an edge portion of the layer. 
     The shapes of the first region and the second region are not limited to those illustrated in  FIG. 28 .  FIG. 30  is a plan view illustrating another example of the first region and the second region. In this figure, sub-pixels SP 1 , SP 2 , SP 3 , dummy sub-pixels DP 1 , DP 2 , DP 3  and organic layers OR 1 , OR 2 , OR 3  similar to those in  FIG. 23  are disposed. 
     Each of the first carrier injection layers  51  of the organic layers OR 1 , OR 2 , and OR 3  has a first region  51   a  and a second region  51   b.  In each of the organic layers OR 1 , OR 2 , and OR 3 , the second region  51   b  is annularly formed along the sides Sa, Sb, Sc, and Sd. That is, the first region  51   a  of the organic layer OR 1  is formed over both the sub-pixel SP 1  and the dummy sub-pixel DP 1 , the first region  51   a  of the organic layer OR 2  is formed over both the sub-pixel SP 2  and the dummy sub-pixel DP 2 , and the first region  51   a  of the organic layer OR 3  is formed over both the sub-pixel SP 3  and the dummy sub-pixel DP 3 . Note that the first region and the second region may be formed in a layer other than the first carrier injection layer  51  among the organic layers OR 1 , OR 2 , and OR 3 . 
     The organic layers OR 1 , OR 2 , and OR 3  illustrated in  FIG. 30  can be formed using a linear vapor deposition source as illustrated in  FIG. 24 . At this time, the first region and the second region can be formed in a specific layer of the organic layers OR 1 , OR 2 , and OR 3  by selectively using a linear vapor deposition source for the host and a linear vapor deposition source for the dopant as in  FIG. 29 . 
     In the first to tenth embodiments described above, a configuration has been disclosed in which an organic layer OR includes a first layer having a first edge portion and a second layer located between the first layer and a second electrode E 2  and having a second edge portion, and the second layer covers the first edge portion. The first layer is any layer other than an uppermost layer among layers constituting the organic layer OR, and is, for example, the first carrier injection layer  51 , the first carrier transport layer  52 , or the emitting layer  54  in the first embodiment. The second layer is any layer other than a lowermost layer among the layers constituting the organic layer OR, and is, for example, the first carrier blocking layer  53  or the second carrier blocking layer  55  in the first embodiment. 
     In the second embodiment ( FIG. 16 ) and the third embodiment ( FIG. 17 ), in addition to the first layer and the second layer, the organic layer OR further includes a third layer located between the second layer and the second electrode E 2  and having a third edge portion, and the third layer covers the second edge portion. For example, in the second embodiment, the first layer is the first carrier injection layer  51  or the first carrier transport layer  52 , the second layer is the first carrier blocking layer  53 , and the third layer is the second carrier blocking layer  55 . 
     The layer configuration of the organic layer OR disclosed in each embodiment is an example. Even in a case where the layer configuration of the organic layer OR is different from those of each embodiment, by providing the first layer and the second layer, and further additionally the third layer, the same effects as those of each embodiment can be obtained. 
     In each embodiment, a case where the first electrode E 1  corresponds to an anode and the second electrode E 2  corresponds to a cathode has been exemplified. However, even in a case where the second electrode E 2  corresponds to an anode and the first electrode E 1  corresponds to a cathode, by applying the same configuration as the organic layer OR disclosed in each embodiment, the same effect as each embodiment can be obtained. 
     Based on the display device which has been described in the above-described embodiments, a person having ordinary skill in the art may achieve a display device with an arbitral design change; however, as long as they fall within the scope and spirit of the present invention, such a display device is encompassed by the scope of the present invention. 
     A skilled person would conceive various changes and modifications of the present invention within the scope of the technical concept of the invention, and naturally, such changes and modifications are encompassed by the scope of the present invention. For example, if a skilled person adds/deletes/alters a structural element or design to/from/in the above-described embodiments, or adds/deletes/alters a step or a condition to/from/in the above-described embodiment, as long as they fall within the scope and spirit of the present invention, such addition, deletion, and altercation are encompassed by the scope of the present invention. 
     Furthermore, regarding the present embodiments, any advantage and effect those will be obvious from the description of the specification or arbitrarily conceived by a skilled person are naturally considered achievable by the present invention.