Patent Publication Number: US-6340883-B1

Title: Wide band IQ splitting apparatus and calibration method therefor with balanced amplitude and phase between I and Q

Description:
FIELD OF THE INVENTION 
     The present invention relates to a wide band I (Inphase) and Q (Quadrature) splitting apparatus, especially, to a wide band IQ splitting apparatus suitable for application in frequency domain analysis, and to a calibration method for the wide band IQ splitting apparatus. 
     BACKGROUND OF THE INVENTION 
     A spectrum analyzer is used for analyzing the frequency domain of a signal under test. The spectrum analyzer often has an IQ splitter for getting the frequency domain data. There are two types of IQ splitters, i.e., digital and analog types. 
     FIG. 1 shows a block diagram of a conventional digital IQ splitter. A frequency converter (not shown) which has a mixer and a local oscillator etc. converts an input signal under test to an intermediate frequency (IF) signal. An analog to digital converter (ADC)  10  converts the analog IF signal into a digital signal. A digital IQ splitter  12  splits the digital signal from the ADC  10  into a digital I (In-phase) signal and a digital Q (Quadrature) signal. The I and Q signals are the components of the IF signal having a phase difference of 90 degrees. A digital signal processor (DSP)  14  transforms the digital I and Q signals into the frequency domain data by the FFT (Fast Fourier Transform) process. A memory  16  stores the data from the DSP  14 , which are used to display the signal analysis result in the frequency domain on a suitable display (not shown), such as a CRT or a liquid crystal display. 
     The conventional configuration described above is satisfactory for relatively narrow band signal analysis but causes some problems if it is used for a wider band signal analysis. The sampling theorem states that the sampling frequency in the analog to digital conversion must be at least twice the maximum frequency of the analog input signal. In the case of wider band analysis, the maximum frequency of the IF signal is higher than in the case of narrow band analysis so that the sampling theorem requires that the sampling frequency of the ADC should be higher. Besides, the frequency domain analysis generally requires higher dynamic range, such as 12 or more bits, than the time domain analysis does, such as 8 bits at most. This also makes it difficult to make the sampling frequency of the ADC higher in the frequency domain analysis. The higher sampling frequency of the ADC leads to a higher data transfer rate and a need for higher operation speeds of the following devices, such as the DSP and the memory. As described, the wider band signal analysis brings technical and economical problems. 
     One solution of the above problem is to use an analog IQ splitter as shown in FIG. 2. A quadrature oscillator  17  generates a pair of quadrature signals, or sine and cosine signals which have the same frequency and amplitude and a phase difference of 90°. An analog IQ splitter  18  mixes an analog IF signal with the quadrature signals to split the analog IF signal into analog I and Q signals. The I signal is Input(t)*cos(bt) and the Q signal is Input(t)*sin(bt) where Input(t) is the input signal. ADCs  11  and  13  convert the analog I and Q signals into the digital I and Q signals, respectively. 
     FIG. 3 shows a schematic block diagram of the analog IQ splitter. A quadrature mixer  21  mixes the pair of quadrature signals with the analog IF signal to produce the analog I and Q signals. The frequency of the quadrature signals from the quadrature oscillator  17  is the same as the center frequency of the band of the analog signal. For example, if the band of the analog IF signal is from 35 MHz to 65 MHz (the bandwidth is 30 MHz, the center frequency is 50 MHz), the frequency of the quadrature signals from the quadrature oscillator  17  is 50 MHz. The analog I and Q signals pass low pass filters (LPFs)  23  and  25  to have suitable bandwidths, respectively. In this operation, the bandwidths of the analog I and Q signals are reduced to approximately half, respectively. This is, for example, shown as the following equations: 
     
       
         Input(t)=C*sin(at) 
       
     
     Input(t) is a simple example of an analog IF signal, C is a constant and a varies from 35 MHz to 65 MHz                I        (   t   )       =       Input        (   t   )       *     cos        (   bt   )                     =     C   *     sin        (   at   )            cos        (   bt   )                     =       (     C   /   2     )     *     [       sin        {       (     a   +   b     )        t     }       +     sin        {       (     a   -   b     )        t     }         ]                   =       (     C   /   2     )     *   sin        {       (     a   -   b     )        t     }                             
     I(t) is the analog IF signal and b is 50 MHz. The term in sin(a+b)t is deleted by the low pass filter.                Q        (   t   )       =       Input        (   t   )       *     sin        (   bt   )                     =     C   *     sin        (   at   )            sin        (   bt   )                     =       (     C   /   2     )     *     [       cos        {       (     a   -   b     )        t     }       +     cos        {       (     a   +   b     )        t     }         ]                   =       (     C   /   2     )     *   cos        {       (     a   -   b     )        t     }                             
     Q(t) is the analog Q signal. The term in cos(a+b)t is deleted by the low pass filter. 
     As shown in the above equations, the LPFs pass the components having “a-b” which varies from −15 MHz to 15 MHz. This means that the frequencies of the output signals of the mixer  21  are from about 0 Hz to about 15 MHz. Therefore the cut-off frequencies of the LPFs  23  and  25  can be about 16 MHz. This reduces the demands of the higher sampling frequency of the ADC and the higher operation speeds of the following devices, such as the DSP  14  and the memory  16 . 
     The use of the analog IQ splitter, however, introduces another problem, namely that it is difficult to keep the amplitude and the phase of the analog I and Q signals in balance. It comes from the difficulty of making the characteristics of the analog I and Q signal paths the same, especially the LPFs. This problem becomes worse when the bandwidth of the analog IF signal is wider. One of the factors is the group delay as shown in FIG.  4 . In other words, the propagation speed of the signal in the signal path is different according to the frequency. Generally speaking, the propagation delay increases as frequency increases and the increase of delay with frequency is non-linear. Therefore the digital IQ splitter is better only from the viewpoint of keeping the amplitude and the phase of the I and Q signals in balance. Therefore what is desired is to provide a wide band IQ splitting apparatus suitable for splitting a wide band analog input signal into I and Q signals with balanced amplitude and phase between them. What is further desired is to provide a calibration method for the wide band IQ splitting apparatus. 
     SUMMARY OF THE INVENTION 
     The present invention provides a wide band IQ splitting apparatus for splitting an analog input signal into analog I (In-phase) and Q (Quadrature) signals while keeping the amplitude and the phase of the I and Q signals in balance. A quadrature oscillator generates a pair of quadrature signals. An amplitude and phase adjuster receives the quadrature signals and adjusts the balances of the amplitude and the phase between them. An analog splitter mixes an analog input signal with the pair of quadrature signals for splitting the analog input signal into analog I and Q signals. First and second analog to digital converters convert the analog I and Q signals into digital I and Q signals, respectively. A processor detects imbalance of the amplitude and phase between the digital I and Q signals and controls the amplitude and phase adjuster. 
     The amplitude and phase adjuster is previously calibrated. For this first calibration, the analog splitter receives a first calibration signal instead of the analog input signal. The first calibration signal has a known amplitude and a known frequency slightly different from the frequency of the quadrature signals. Then the processor detects imbalance of the amplitude and/or the phase between the digital I and Q signals for controlling the amplitude and phase adjuster properly. The frequency difference between the frequency of the first calibration signal and that of the quadrature signal is small enough that the group delay can be neglected and large enough that the processor can detect the frequency difference. 
     The processor according to the present invention produces compensation data in a second calibration. For the second calibration, the analog splitter receives a second calibration signal instead of the analog input signal. The frequency of the second calibration signal varies within the band of the analog input signal and the processor calculates compensation data at a plurality of frequencies of the calibration signal and a memory stores the compensation data. The frequency of the second calibration signal can vary step by step, or by a increment or a decrement. The amount by which the frequency changes in each step is small enough that the group delay can be neglected and large enough that the processor can detect the difference. The processor can calculate compensated frequency domain data from the digital I and Q data by using the compensation data and can calculate time domain data from the compensated frequency domain data. 
     The amplitude and phase adjuster can include a variable phase controller and a gain variable amplifier. The variable phase controller controls the phase of one of the quadrature signals. The gain variable amplifier controls the gain of one of the quadrature signals. The analog IQ splitter can have a mixer and a pair of low pass filters. The mixer mixes the analog input signal with the pair of quadrature signals. The low pass filters receive the output signals of the mixer and suitably limit the bandwidths of the analog I and Q signals. In this case, the frequency of the quadrature signals is approximately equal to the center frequency of the band of the analog input signal. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 shows a schematic block diagram of a conventional digital IQ splitter. 
     FIG. 2 shows a schematic diagram of a conventional analog IQ splitter. 
     FIG. 3 shows a schematic diagram of one embodiment of an analog IQ splitter. 
     FIG. 4 is a graph of showing characteristics of the group delay. 
     FIG. 5 shows a schematic diagram of one embodiment of a wide band IQ splitting apparatus according to the present invention. 
     FIG. 6 shows a schematic diagram of one embodiment of an amplitude and phase adjuster according to the present invention. 
     FIG. 7 is a graph explaining a side band generation in the first calibration according to the present invention. 
     FIG. 8 shows a flow chart of one embodiment of the second calibration according to the present invention. 
     FIG. 9 shows a phase shift of P radian from the ideal relationship between the I and Q signals. 
    
    
     DESCRIPTION OF PREFERRED EMBODIMENTS OF THE INVENTION 
     FIG. 5 shows a schematic block diagram of one preferred embodiment according to the present invention. A frequency converter (not shown) which has a mixer and a local oscillator etc. converts a signal under test to an intermediate frequency (IF) signal. For example, the input signal might have a frequency of 3 GHz and the frequency converter down converts the frequency of the input signal to generate an IF signal having a frequency within a predetermined band (e.g. from 35 MHz to 65 MHz). A quadrature oscillator  30  supplies a pair of quadrature signals, or sine and cosine signals of which the phase and amplitude are adjusted as described below, and an analog IQ splitter  20  multiplies the analog IF signal by the pair of quadrature signals and provides analog I (In-phase) and Q (Quadrature) signals. Analog to digital converters (ADCs)  22  and  24  convert the analog I and Q signals into digital I and Q signals, respectively. A control and processing circuit  26  transforms the digital I and Q signals into frequency domain data by the FFT process. The digital I and Q signals constitute the real and imaginary components respectively of the frequency domain data. A memory  28  stores the frequency domain data. The memory  28  is connected to a bus of a microprocessor system (not shown) including a CPU, a hard disk (magnetic disk) etc. The data in the memory  28  are used for displaying the measurement result on a CRT etc. or for other analysis. 
     An amplitude and phase adjuster  32  adjusts the balances of the amplitude and the phase between the pair of quadrature signals from the quadrature oscillator  30 . FIG. 6 shows a schematic block diagram of one preferred embodiment of the amplitude and phase adjuster  32 . An amplifier  34  amplifies one of the quadrature signals from the quadrature oscillator  30 . The other of the quadrature signals passes through a variable phase controller  33  and a variable gain amplifier  35  which are controlled respectively by a phase control signal and gain control signal from the control and processing circuit  26 . The amplitude and phase adjuster  32  provides the adjusted quadrature signals to the analog IQ splitter  20  for producing the analog I and Q signals of which balances of the amplitude and the phase are adjusted. 
     For the suitable adjustment, the amplitude and phase adjuster  32  is previously calibrated. This calibration (called the first calibration below) is based on the center frequency of the analog IF signal band. For the first calibration, the analog IQ splitter  20  receives a first calibration signal of which amplitude, phase and frequency are known. The first calibration signal may be provided by a signal generator (not shown). The frequency of the first calibration signal is slightly different from the center frequency of the analog IF signal band. For example, if the band of the analog IF signal is from 35 MHz to 65 MHz (the center frequency 50 MHz), the frequency of the calibration signal might be 50.2 MHz (200 kHz difference). The analog IQ splitter  20  multiplies the first calibration signal by the quadrature signals of which the frequencies are 50 MHz. Referring to FIG. 7, if the amplitude and phase adjuster  32  is not properly adjusted, and the quadrature signals supplied to the analog IQ splitter are not balanced in phase and amplitude, the I and Q signals received by the control and processing circuit  26  are not balanced and a side band appears at 49.8 MHz after the FFT process. Then the control and processing circuit  26  adjusts the gain and phase control signals in order to eliminate the side band. When the gain and phase control signals are such that the side band is eliminated, the first calibration is complete. 
     The difference dF between the center frequency of the band and the frequency of the first calibration signal should be small enough that the group delay of the signal paths from the analog IQ splitter  20  to the control and processing circuit  26  can be neglected. The frequency difference dF, however, should be large enough that the control and processing circuit  26  can detect the side band. Though the example described above uses a frequency difference dF of 200 kHz, it can be another value according to the measurement resolution. 
     The first calibration concerning the amplitude and phase adjuster  32  makes the amplitude and phase balances of the analog I and Q signals suitable if the frequency of the input analog IF signal is approximately equal to the center frequency of the band. The analog IF signal, however, has a wider band. Therefore another calibration is necessary for the control and processing circuit  26  to get balance compensated data of the analog I and Q signals throughout the band. This second calibration is usually conducted following the first calibration. However, if the adjuster  32  has no problem and the I and Q signals received by the control and processing circuit  26  are balanced in amplitude and phase when the analog IQ splitter receives the first calibration signal, the second calibration can be done without the first calibration. 
     FIG. 8 shows a flow chart of one preferred embodiment according to the second calibration of the present invention. The second calibration produces a compensation table recording compensation data throughout the band. The analog IQ splitter  20  receives a second calibration signal which has known amplitude, phase and single frequency instead of the analog IF signal. The second calibration signal may be provided by a signal generator (not shown). In the second calibration, the second calibration signal is set to the minimum frequency of the analog IF signal band at first (step  100 ). For example, if the band of the analog IF signal is from 35 MHz to 65 MHz, the frequency of the calibration signal is set to 35 MHz at first. At step  102 , the control and processing circuit  26  receives the digital I and Q signals. The digital I and Q signals are represented as data sequences a(n) and b(n), respectively, wherein the “n” means a sampling number in the ADCs  22  and  24 . The control and processing circuit  26  calculates amplitudes Ma and Mb of the digital I and Q signals from the data sequences and produces an amplitude compensation coefficient K=Ma/Mb. At the same time, a phase compensation coefficient P at the minimum frequency is calculated by the following equation: 
     
       
         P=−0.001953*S/(Ma*Mb) 
       
     
     wherein S={(a(n)−Da)*(b(n)−Db)} 
     Da: average of a(n) 
     Db: average of b(n) 
     Unit of P is radian 
     The P means a phase shift from the ideal relationship between the I and Q signals, or 90 degrees as shown in FIG.  9 . The memory  28  stores the amplitude and phase coefficients K and P of the compensation table at the minimum frequency (step  104 ). After the step  104 , the frequency of the second calibration signal is increased by some amount (step  106 ). This increment of the frequency of the calibration signal is, for example, 200 kHz. The amount of the increment should be small enough that the group delay can be neglected and large enough for the control and processing circuit  26  to detect the difference. The control and processing circuit  26  repetitively calculates the amplitude and phase compensation coefficients K and P at each frequency until it reaches the maximum frequency (e.g. 65 MHz) of the analog IF signal band (step  108 ). At this point, the compensation table is complete. 
     The control and processing circuit  26  compensates the frequency domain data derived from the I and Q signals using the compensation table. For compensating the amplitude and phase shift, it uses the following equations: 
     
       
         Ac=K*(A*cos(P)−B*sin(P)) 
       
     
     
       
         Bc=K*(B*cos(P)+A*sin(P)) 
       
     
     wherein A: Real part of the frequency data 
     B: Imaginary part of the frequency data 
     Ac: Compensated real part of the frequency data 
     Bc: Compensated imaginary part of the frequency data 
     The above equations apply an angular rotation or phase shift to the frequency domain data according to the value of P and an amplitude compensation according to the value of K for each frequency of the input analog IF signal. By the way, the A and B are calculated from the digital I and Q signals by the FFT process of the control and processing circuit  26 , or they are actual and non-compensated frequency domain data. If the time domain data are necessary, they are calculated from the corresponding compensated frequency domain data by the inverse-FFT process so that the time domain data are also compensated concerning the amplitude and phase balances. The memory  28  stores the frequency domain data and the time domain data and records the time correspondence between them. The data in the memory  28  are transferred via a bus of a microprocessor system including a CPU, a hard disk etc. and used for displaying the data or another analysis. 
     It will also be apparent to those skilled in the art that there are additional embodiments which are not described above but which are clearly within the scope and principle of the present invention. For example, in the second calibration, the initial frequency of the calibration signal need not be the minimum frequency and could instead be the maximum frequency. Further, the frequency of the second calibration signal need not vary in increments or decrements (or step by step), but may be at random or interlaced. It is important to obtain compensation data at a sufficient number of frequencies of the second calibration signal. Though the analog IQ splitter  20  receives the analog IF signal in the above embodiment, it can be any analog input signal with a predetermined band. The control and processing circuit could detect imbalance of amplitude and phase in the first calibration using the same equations as in the second calibration, but it is better for fine calibration of the amplitude and phase adjuster to use frequency domain data, for example by detecting a side band as described with reference to FIG.  7 .