Patent Publication Number: US-2021193688-A1

Title: Transparent display device

Description:
BACKGROUND 
     Technical Field 
     The present disclosure relates to a transparent display device. 
     Description of the Related Art 
     With advancement in information-oriented societies, demands for display devices that display an image have increased in various forms. Recently, various types of display devices such as a liquid crystal display (LCD) device, a plasma display panel (PDP) device, and an organic light emitting display (OLED) device, a quantum dot light emitting display (QLED) device have been widely utilized. 
     Recent, studies for transparent display devices for allowing a user to look at objects or image arranged on an opposite side of a display device after transmitting the display device are actively ongoing. 
     BRIEF SUMMARY 
     The inventors of the present disclosure have recognized a reduction of yield of display devices in the related art. When a transparent display device is manufactured, a process of testing a defect of a driving transistor is performed after an anode electrode is formed. If a defect is present in the driving transistor, a repair process is performed. However, if the repair process is performed after the anode electrode is formed, due to an organic film and the anode electrode, which are provided on a source electrode and a drain electrode, repair yield is reduced, and tact time is increased. Having recognized one or more problems in the related art including the above identified problem, the present disclosure provides a transparent display device that may improve yield and reduce a tact time. 
     One or more embodiments of the present disclosure provides a transparent display device that may reduce resistance of a power line. 
     In addition to the technical benefits of the present disclosure as mentioned above, additional benefits and features of the present disclosure will be clearly understood by those skilled in the art from the following description of the present disclosure. 
     In accordance with an aspect of the present disclosure, the above and other benefits can be accomplished by the provision of a transparent display device comprising a substrate provided with a display area, in which a plurality of subpixels are disposed, and a non-display area adjacent to the display area, first and second pads provided on the substrate, a first pixel power line extended between a pad area in which the first pad and the second pad are disposed and the display area in a first direction, a first common power line extended between the first pixel power line and the display area in the first direction, a first common power connection electrode electrically connecting the second pad with the first common power line, and a second common power connection electrode disposed on a layer different from the first common power connection electrode, electrically connecting the second pad with the first common power line. 
     In accordance with another aspect of the present disclosure, the above and other benefits can be accomplished by the provision of a transparent display device comprising a substrate provided with a display area, in which a plurality of subpixels are disposed, and a non-display area adjacent to the display area, a pad provided on the substrate, a first metal line extended between the pad and the non-display area in a first direction, a second metal line disposed in the same layer as the first metal line and extended between the first metal line and the display area in the first direction, a first connection electrode disposed below the second metal line, electrically connecting the pad with the second metal line, and a second connection electrode disposed on the second metal line, electrically connecting the pad with the second metal line. In one embodiment, the non-display area is positioned surrounding the display area, but this is not required. 
     According to the present invention, the metal lines provided between the pad area and the display area, for example, the common power line and a reference line may electrically be connected with the pad by using two connection electrodes disposed on their respective layers different from each other. Therefore, according to the present disclosure, a total area of the common power line and the reference line may be increased, and resistance thereof may be reduced. 
     Also, according to the present disclosure, even though a defect occurs in any one of the two connection electrodes, the metal line and the pad may be connected with each other by the other one. Therefore, since the voltage may stably be supplied to the subpixels, panel yield may be improved. 
     Also, according to the present disclosure, a defect of a driving transistor may be tested before the anode electrode is deposited. Since a repair process may be performed before the anode electrode is deposited, repair yield may be prevented from being reduced by the anode electrode. Also, a tact time may be reduced. 
     Also, even though the pixel power line, the common power line and the reference line are provided in only the first non-display area including the pad area and the second non-display area facing the first non-display area, it is possible to make sure of a sufficient area of each of the pixel power line, the common power line and the reference line. In the present disclosure, the pixel power line, the common power line and the reference line may not be provided in the third non-display area and the fourth non-display area, which are disposed between the first non-display area and the second non-display area. Therefore, transmittance in the non-display area may be improved. 
     In addition to the effects of the present disclosure as mentioned above, additional advantages and features of the present disclosure will be clearly understood by those skilled in the art from the above description of the present disclosure. 
    
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
       The above and other features and other advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which: 
         FIG. 1  is a perspective view illustrating a transparent display device according to one embodiment of the present disclosure; 
         FIG. 2  is a schematic plane view illustrating a transparent display panel; 
         FIG. 3  is an enlarged view of an area A in  FIG. 2 ; 
         FIG. 4  is a cross-sectional view taken along line I-I of  FIG. 3 ; 
         FIG. 5  is an enlarged view of an area B in  FIG. 2 ; 
         FIG. 6  is a cross-sectional view taken along line II-II of  FIG. 5 ; 
         FIG. 7  is a cross-sectional view taken along line of  FIG. 5 ; and 
         FIG. 8  is a cross-sectional view taken along line IV-IV of  FIG. 5 . 
     
    
    
     DETAILED DESCRIPTION 
     Advantages and features of the present disclosure, and implementation methods thereof will be clarified through following embodiments described with reference to the accompanying drawings. The present disclosure may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art. 
     A shape, a size, a ratio, an angle, and a number disclosed in the drawings for describing embodiments of the present disclosure are merely an example, and thus, the present disclosure is not limited to the illustrated details. Like reference numerals refer to like elements throughout the specification. In the following description, when the detailed description of the relevant known function or configuration is determined to unnecessarily obscure the important point of the present disclosure, the detailed description will be omitted. In a case where ‘comprise’, ‘have’, and ‘include’ described in the present specification are used, another part may be added unless ‘only˜’ is used. The terms of a singular form may include plural forms unless referred to the contrary. 
     In construing an element, the element is construed as including an error range although there is no explicit description. 
     In describing a position relationship, for example, when the position relationship is described as ‘upon˜’, ‘above˜’, ‘below˜’ and ‘next to˜’, one or more portions may be arranged between two other portions unless ‘just’ or ‘direct’ is used. 
     It will be understood that, although the terms “first”, “second”, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. 
     In describing elements of the present disclosure, the terms “first”, “second”, etc., may be used. These terms are intended to identify the corresponding elements from the other elements, and basis, order, or number of the corresponding elements are not limited by these terms. The expression that an element is “connected” or “coupled” to another element should be understood that the element may directly be connected or coupled to another element but may directly be connected or coupled to another element unless specially mentioned, or a third element may be interposed between the corresponding elements. 
     Features of various embodiments of the present disclosure may be partially or overall coupled to or combined with each other, and may be variously inter-operated with each other and driven technically as those skilled in the art can sufficiently understand. The embodiments of the present disclosure may be carried out independently from each other, or may be carried out together in co-dependent relationship. 
     Hereinafter, an example of a transparent display device according to the present disclosure will be described in detail with reference to the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts. 
       FIG. 1  is a perspective view illustrating a transparent display device according to one embodiment of the present disclosure. 
     Hereinafter, X axis indicates a line parallel with a gate line, Y axis indicates a line parallel with a data line, and Z axis indicates a height direction of a transparent display device  100 . 
     Although a description has been described based on that the transparent display device  100  according to one embodiment of the present disclosure is embodied as an organic light emitting display device, the transparent display device  100  may be embodied as a liquid crystal display device, a plasma display panel (PDP), a Quantum dot Light Emitting Display (QLED) or an Electrophoresis display device. 
     Referring to  FIG. 1 , the transparent display device  100  according to one embodiment of the present disclosure includes a transparent display panel  110 , a source drive integrated circuit (IC)  210 , a flexible film  220 , a circuit board  230 , and a timing controller  240 . 
     The transparent display panel  110  includes a first substrate  111  and a second substrate  112 , which face each other. The second substrate  112  may be an encapsulation substrate. The first substrate  111  may be a plastic film, a glass substrate, or a silicon wafer substrate formed using a semiconductor process. The second substrate  112  may be a plastic film, a glass substrate, or an encapsulation film. The first substrate  111  and the second substrate  112  may be made of a transparent material. 
     On one surface of the first substrate  111  confronting the second substrate  112 , there are gate lines, data lines, and pixels. The pixels are prepared in respective areas adjacent to the overlapping locations between the gate lines and the data lines. 
     Each of the pixels may include a TFT, and a light emitting device including an anode electrode, an emission layer, and a cathode electrode. If a gate signal is supplied from the gate line to each pixel through the use of TFT, a predetermined current is supplied to the light emitting device in accordance with a data voltage of the data line. Accordingly, when a high potential voltage is applied to the anode electrode, and a low potential voltage is applied to the cathode electrode, the light emitting device for each of the pixels may emit light with a predetermined brightness in accordance with the predetermined current. 
     The transparent display panel  110  may include a display area provided with the sub pixels for displaying an image, and a non-display area in which an image is not displayed. The gate lines, the data lines, and the pixels may be provided in the display area, and a gate driver and pads may be provided in the non-display area. 
     The gate driver supplies gate signals to the gate lines in accordance with a gate control signal which is provided from the timing controller  240 . The gate driver may be provided in one side of the display area of the transparent display panel  110 , or the non-display area of both peripheral sides of the transparent display panel  110  by a gate driver in panel (GIP) method. In another way, the gate driver may be manufactured in a driving chip, may be mounted on the flexible film, and may be attached to one side of the display area of the transparent display panel  110 , or the non-display area of both peripheral sides of the transparent display panel  110  by a tape automated bonding (TAB) method. 
     The source drive IC  210  receives digital video data and source control signals from the timing controller  240 . The source drive IC  210  converts the digital video data into analog data voltages in accordance with the source control signal, and supplies the analog data voltages to the data lines. If the source drive IC  210  is manufactured in a driving chip, the source drive IC  210  may be mounted on the flexible film  220  by a chip on film (COF) method or a chip on plastic (COP) method. 
     Pads, such as power pads and data pads, may be formed in a non-display area of the transparent display panel  110 . Lines connecting the pads with the source drive IC  210  and lines connecting the pads with lines of the circuit board  230  may be formed in the flexible film  220 . The flexible film  220  may be attached onto the pads using an anisotropic conducting film, whereby the pads may be connected with the lines of the flexible film  220 . 
     The circuit board  230  may be attached to the flexible film  220 . A plurality of circuits, which are realized in a plurality of driving chips, may be mounted on the circuit board  230 . For example, the timing controller  240  may be mounted on the circuit board  230 . The circuit board  230  may be a printed circuit board or a flexible printed circuit board. 
     The timing controller  240  receives digital video data and a timing signal from an external system board via a cable of the circuit board  230 . The timing controller  240  generates the gate control signal for controlling an operation timing of the gate driver and the source control signal for controlling the source drive IC  210  on the basis of the timing signal. The timing controller  240  supplies the gate control signal to the gate driver, and supplies the source control signal to the source drive IC  210 . 
       FIG. 2  is a schematic plane view illustrating a transparent display panel,  FIG. 3  is an enlarged view of an area A in  FIG. 2 ,  FIG. 4  is a cross-sectional view taken along line I-I of  FIG. 3 ,  FIG. 5  is an enlarged view of an area B in  FIG. 2 ,  FIG. 6  is a cross-sectional view taken along line II-II of  FIG. 5 ,  FIG. 7  is a cross-sectional view taken along line of  FIG. 5 , and  FIG. 8  is a cross-sectional view taken along line IV-IV of  FIG. 5 . 
     Referring to  FIGS. 2 to 8 , the substrate  111  may be categorized into a display area DA where pixels P are formed to display an image, and a non-display area NDA that does not display an image. 
     The display area DA, as shown in  FIG. 3 , includes a transmissive area TA and a non-transmissive area NTA. The transmissive area TA is an area through which externally incident light passes as it is, and the non-transmissive area NTA is an area through which a significant amount of externally incident light fails to transmit. A user may view an object or background arranged on a rear surface of the transparent display panel  110  due to the transmissive area TA. 
     The non-transmissive area NTA may be provided with pixel power lines VDDL, common power lines VSSL, reference lines, data lines, gate lines GL, and pixels P. 
     The gate lines GL may be extended in a first direction (for example, X axis direction), and may cross (or overlap) the pixel power lines VDDL, the common power lines VSSL and the data lines in the display area DA. The pixel power lines VDDL, the common power lines VSSL, and the data lines may be extended in a second direction (for example, Y axis direction). 
     The pixels P emit predetermined light to display an image. An emission area EA may correspond to an area, from which light emits, in the pixel P. 
     Each of the pixels P may include a first subpixel P 1 , a second subpixel P 2 , and a third subpixel P 3 . The first subpixel P 1  may be provided to include a first emission area EA 1  emitting green light, the second subpixel P 2  may be provided to include a second emission area EA 2  emitting red light, and the third subpixel P 3  may be provided to include a third emission area EA 3  emitting blue light, but these subpixel are not limited thereto. Each of the pixels P may further include a subpixel emitting white light W. An arrangement sequence of the subpixel P 1 , P 2 , and P 3  may be changed in various ways. 
     Hereinafter, for convenience of description, a description will be given based on that the first subpixel P 1  is a green subpixel emitting green light, the second subpixel P 2  is a red subpixel emitting red light, and the third subpixel P 3  is a blue subpixel emitting blue light. 
     Each of the first subpixel P 1 , the second subpixel P 2 , and the third subpixel P 3 , as shown in  FIG. 4 , may include a circuit element that includes a capacitor, a thin film transistor, and a light emitting diode. The thin film transistor may include a switching transistor, a sensing transistor, and a driving transistor T. 
     The switching transistor is switched in accordance with a gate signal supplied to the gate line GL and serves to supply a data voltage supplied from the data line to the driving transistor T. 
     The sensing transistor serves to sense a threshold voltage deviation of the driving transistor T, which is a cause of image quality degradation. 
     The driving transistor T is switched in accordance with the data voltage supplied from the switching transistor to generate a data current from a power source supplied from the pixel power line VDDL, and serves to supply the generated data current to the anode electrode  120  of the subpixel. 
     The driving transistor T includes an active layer ACT, a gate electrode GE, a source electrode SE, and a drain electrode DE. 
     In detail, the active layer ACT may be provided over the first substrate  111 . The active layer ACT may be formed of a silicon based semiconductor material or an oxide based semiconductor material. A buffer layer (not shown) may be provided between the active layer ACT and the first substrate  111 . 
     A gate insulating layer GI may be provided over the active layer ACT. The gate insulating layer GI may be formed an inorganic film, for example, a silicon oxide (SiOx) film, a silicon nitride (SiNx) film, or a multi-layered film of SiOx and SiNx. 
     A gate electrode GE may be provided over the gate insulating layer GI. The gate electrode GE may be formed of a single layer or a multi-layer made of any one of Mo, Al, Cr, Au, Ti, Ni, Nd, and Cu or their alloy. 
     A first inter-layer insulating layer ILD 1  and a second inter-layer insulating layer ILD 2  may be provided over the gate electrode GE. The first inter-layer insulating layer ILD 1  and the second inter-layer insulating layer ILD 2  may be formed an inorganic layer, for example, a silicon oxide (SiOx) layer, a silicon nitride (SiNx) layer, or a multi-layered layer of SiOx and SiNx. 
     Source and drain electrodes SE and DE may be provided over the second inter-layer insulating layer ILD 2 . One of the source and drain electrodes SE and DE may be connected to the active layer ACT through a second contact hole CH 2  that passes through the gate insulating layer GI and the first and second inter-layer insulating layers ILD 1  and ILD 2 . For example, the drain electrode DE may be connected to the active layer ACT through the second contact hole CH 2  that passes through the gate insulating layer GI and the first and second inter-layer insulating layers ILD 1  and ILD 2 . 
     The source and drain electrodes SE and DE may be formed of a single layer or a multi-layer made of any one of Mo, Al, Cr, Au, Ti, Ni, Nd, and Cu or their alloy. 
     A first planarization layer PLN 1  may be provided over the source and drain electrodes SE and DE to planarize a step difference caused by the driving transistor T. The first planarization layer PLN 1  may be formed of an organic layer, for example, acryl resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, etc. 
     An anode auxiliary electrode  115  may be provided over the first planarization layer PLN 1 . The anode auxiliary electrode  115  may be connected to one of the source and drain electrodes SE and DE through a third contact hole CH 3  that passes through the first planarization layer PLN 1 . For example, the anode auxiliary electrode  115  may be connected to the drain electrode DE through the third contact hole CH 3  that passes through the first planarization layer PLN 1 . 
     The anode auxiliary electrode  115  may be formed of a single layer or a multi-layer made of any one of Mo, Al, Cr, Au, Ti, Ni, Nd, and Cu or their alloy. 
     A second planarization layer PLN 2  may be formed over the anode auxiliary electrode  115 . The second planarization layer PLN 2  may be formed of an organic layer, for example, acryl resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, etc. 
     Light emitting diodes, which are comprised of the anode electrode  120 , a light emitting layer  130 , and a cathode electrode  140 , and a bank  125  are provided over the second planarization layer PLN 2 . 
     The anode electrode  120  may be provided over the second planarization layer PLN 2  for each of the subpixels P 1 , P 2 , and P 3 . The anode electrode  120  is not provided in the transmissive area TA. 
     The anode electrode  120  may be connected with the driving transistor T. In detail, the anode electrode  120  may be connected to the anode auxiliary electrode  115  through a first contact hole CH 1  that passes through the second planarization layer PLN 2 . Since the anode auxiliary electrode  115  is connected to the source electrode SE or the drain electrode DE of the driving transistor T through the third contact hole CH 3 , the anode electrode  120  may electrically be connected with the driving transistor T. 
     The anode electrode  120  may be formed of a metal material of high reflectivity such as a deposited structure (Ti/Al/Ti) of aluminum and titanium, a deposited structure (ITO/Al/ITO) of aluminum and ITO, an Ag alloy and a deposited structure (ITO/Ag alloy/ITO) of Ag alloy and ITO. The Ag alloy may be an alloy of silver (Ag), palladium (Pb), and Copper (Cu). 
     The bank  125  may be provided over the second planarization layer PLN 2 . Also, the bank  125  may be formed to cover edges of the anode electrode  120  and partially expose the anode electrode  120 . Therefore, the bank  125  may prevent light emitting efficiency from being deteriorated due to a current concentrated on the ends of the anode electrode  120 . 
     The bank  125  may respectively define emission areas EA 1 , EA 2 , and EA 3  of the subpixels P 1 , P 2 , and P 3 . Each of the emission areas EA 1 , EA 2 , and EA 3  of the subpixels P 1 , P 2 , and P 3  indicates an area where the anode electrode  120 , the light emitting layer  130  and the cathode electrode  140  are sequentially deposited and then holes from the anode electrode  120  and electrons from the cathode electrode  140  are combined with each other in the light emitting layer  130  to emit light. In this case, since the area where the bank  125  is formed does not light emit, the area may be a non-emission area NEA, and the area where the bank  125  is not formed and the anode electrode  120  is exposed may be the emission area EA. 
     The bank  125  may be formed of an organic layer, for example, acryl resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, etc. 
     The organic light emitting layer  130  may be provided over the anode electrode  120 . The organic light emitting layer  130  may include a hole transporting layer, a light emitting layer, and an electron transporting layer. In this case, if a voltage is applied to the anode electrode  120  and the cathode electrode  140 , holes and electrons move to the light emitting layer through the hole transporting layer and the electron transporting layer, respectively, and are combined with each other in the light emitting layer to emit light. 
     The organic light emitting layer  130 , as shown in  FIG. 4 , may include light emitting layers each of which is formed for each of the subpixels P 1 , P 2 , and P 3 . For example, a green light emitting layer  131  emitting green light may be formed in the first subpixel P 1 , a red light emitting layer  132  emitting red light may be formed in the second subpixel P 2 , and a blue light emitting layer  133  emitting blue light may be formed in the third subpixel P 3 . In this case, the light emitting layers of the organic light emitting layer  130  are not formed in the transmissive area TA. 
     The cathode electrode  140  may be provided over the organic light emitting layer  130  and the bank  125 . The cathode electrode  140  may be provided in the transmissive area TA as well as the non-transmissive area NTA that includes the emission area EA, but is not limited thereto. The cathode electrode  140  may be provided in only the non-transmissive area NTA that includes the emission area EA, and may not be provided in the transmissive area TA to improve transmittance. 
     The cathode electrode  140  may be a common layer commonly formed for the subpixels P 1 , P 2 , and P 3  to apply the same voltage to the subpixels P 1 , P 2 , and P 3 . The cathode electrode  140  may be formed of a transparent conductive material (TCO) such as ITO and IZO, which can transmit light, or may be formed of a semi-transmissive conductive material such as Mg, Ag, or alloy of Mg and Ag. If the cathode electrode  140  is formed of a semi-transmissive conductive material, emission efficiency may be enhanced by micro cavity. 
     An encapsulation film  150  may be provided over the light emitting diodes. The encapsulation film  150  may be formed over the cathode electrode  140  to overlay the cathode electrode  140 . The encapsulation film  150  serves to prevent oxygen or water from being permeated into the organic light emitting layer  130  and the cathode electrode  140 . Accordingly, in some embodiments, the encapsulation film  150  may include at least one inorganic film and at least one organic film. 
     Meanwhile, although not shown in  FIG. 4 , a capping layer may additionally be formed between the cathode electrode  140  and the encapsulation film  150 . 
     A color filter layer  170  may be provided over the encapsulation layer  150 . The color filter layer  170  may be provided over one surface of the second substrate  112  that faces the first substrate  111 . In this case, the first substrate  111  provided with the encapsulation layer  150  and the second substrate  112  provided with the color filter layer  170  may be bonded to each other by an adhesive layer  160 . In some embodiments, the adhesive layer  160  may be an optically clear resin (OCR) layer or an optically clear adhesive (OCA) film. 
     The color filter layer  170  may be formed to be patterned for each of the subpixels P 1 , P 2 , and P 3 . In detail, the color filter layer  170  may include a first color filter CF 1 , a second color filter CF 2 , and a third color filter CF 3 . The first color filter CF 1  may be disposed to correspond to the emission area EA 1  of the first subpixel P 1 , and may be a green color filter that transmits green light. The second color filter CF 2  may be disposed to correspond to the emission area EA 2  of the second subpixel P 2 , and may be a red color filter that transmits red light. The third color filter CF 3  may be disposed to correspond to the emission area EA 3  of the third subpixel P 3 , and may be a blue color filter that transmits blue light. 
     The transparent display panel  110  according to one embodiment of the present disclosure is characterized in that a polarizer is not used, and the color filter layer  170  is formed in the second substrate  112 . If the polarizer is attached to the transparent display panel  110 , transmittance of the transparent display panel  110  is reduced by the polarizer. Meanwhile, if the polarizer is not attached to the transparent display panel  110 , a problem occurs in that externally incident light is reflected towards the electrodes. 
     Since a polarizer is not attached to the transparent display panel  110  according to one embodiment of the present disclosure, transmittance may be prevented from being reduced. Also, in the transparent display panel  110  according to one embodiment of the present disclosure, the color filter layer  170  may be formed in the second substrate  112  to partially absorb externally incident light, thereby preventing the incident light from being reflected toward the electrodes. That is, the transparent display panel  110  according to one embodiment of the present disclosure may reduce external light reflectivity without reducing transmittance. 
     Meanwhile, a black matrix BM may be provided among the color filters CF 1 , CF 2 , and CF 3 . The black matrix BM may be provided among the subpixels P 1 , P 2 , and P 3  to prevent color mixture among the adjacent subpixels P 1 , P 2 , and P 3  from occurring. Also, the black matrix BM may prevent externally incident light from being reflected toward a plurality of lines provided among the subpixels P 1 , P 2 , and P 3 , for example, the gate lines, the data lines, the pixel power lines, the common power lines, the reference lines, etc. 
     The black matrix BM may include a material that absorbs light, for example, a black dye that absorbs light of a visible light wavelength range. 
     Referring to  FIG. 2  again, the non-display area NDA may be provided with a pad area PA in which pads PAD are disposed, and at least one gate driver  205 . 
     In detail, the non-display area NDA may include a first non-display area NDA 1  in which the pads PAD are disposed, a second non-display area NDA 2  disposed in parallel with the first non-display area NDA 1  by interposing the display area DA, and third and fourth non-display areas NDA 3  and NDA 4  connecting the first non-display area NDA 1  with the second non-display area NDA 2 . 
     The gate driver  205  is connected to the gate lines GL and supplies gate signals to the gate lines GL. The gate driver  205  may be disposed in at least one of the third non-display area NDA 3  and the fourth non-display area NDA 4  in a gate drive in panel (GIP) type. For example, as shown in  FIG. 2 , the gate driver  205  may be formed in the fourth non-display area NDA 4 , and another gate driver  205  may be formed in the third non-display area NDA 3 , but is not limited thereto. The gate driver  205  may be formed in any one of the fourth non-display area NDA 4  and the third non-display area NDA 3 . 
     The pads PAD may include a first pad VDDP, a second pad VSSP, a third pad VREFP, and a fourth pad DP, and may be provided in the first non-display area NDA 1 . That is, the first non-display area NDA 1  may include a pad area PA. 
     In the transparent display panel  110  according to one embodiment of the present disclosure, a plurality of circuits and a plurality of metal lines may be disposed in the non-display area NDA, particularly the first non-display area NDA 1  and the second non-display area NDA 2 . The plurality of circuits may include electrostatic prevention circuits and multiplex circuits disposed in the first non-display area NDA 1 . 
     For example, the electrostatic prevention circuits may be circuits for preventing static electricity from entering the transparent display panel  110  or occurring in the transparent display panel  110 . The electrostatic prevention circuits may be provided in the first non-display area NDA 1 . In detail, the electrostatic prevention circuits, as shown in  FIG. 5 , may be disposed in an area ESDA between the reference line VREF 1  and the common power line VSS 1  provided in the first non-display area NDA 1 . 
     For example, each of the multiplex circuits may be a circuit for driving the plurality of data lines time-divisionally. The multiplex circuits may be disposed in the first non-display area NDA 1 . In detail, the multiplex circuits, as shown in  FIG. 5 , may be disposed in an area MUXA between the common power line VSS 1  and the display area DA provided in the first non-display area NDA 1 . 
     The plurality of metal lines may be a plurality of signal lines connected with the subpixels P 1 , P 2 , and P 3  provided in the display area DA. 
     For example, the plurality of metal lines may include a first metal line and a second metal line. In some embodiments, the first metal line may be, but not limited to, a pixel power line VDD for supplying a first power source to the subpixels P 1 , P 2 , and P 3  provided in the display area DA, and the second metal line may be, but not limited to, a common power line VSS for supplying a second power source to the subpixels P 1 , P 2 , and P 3  provided in the display area DA. The first metal line may be the common power line VSS, and the second metal line may be the pixel power line VDD. Meanwhile, the plurality of metal lines may further include a third metal line, wherein the third metal line may be, but not limited to, a reference line VREF. 
     The first metal line may be provided to be extended in the non-display area NDA in a first direction (X axis direction). For example, the first metal line provided in the non-display area NDA may be the pixel power line VDD. Hereinafter, for convenience of description, a description will be given based on that the first metal line is the pixel power line VDD. 
     Referring to  FIGS. 2, 5 and 6 , the pixel power line VDD may supply the first power source to the driving transistor T of each of the subpixels P 1 , P 2 , and P 3  provided in the display area DA. 
     Accordingly, in some embodiments, the pixel power line VDD may include a first pixel power line VDD 1  provided in the first non-display area NDA 1 , a second pixel power line VDD 2  provided in the second non-display area NDA 2 , and a plurality of third pixel power lines VDDL connecting the first pixel power line VDD 1  with the second pixel power line VDD 2 . 
     The first pixel power line VDD 1  may be provided to be extended in the first non-display area NDA 1 , specifically between the pad area PA and the display area DA in a first direction (X axis direction). The first pixel power line VDD 1  may be connected with the first pad VDDP in the first non-display area NDA 1 , and may be supplied with a first power source from the first pad VDDP. The first pad VDDP may be extended in a second direction (Y axis direction), and may be connected with the first pixel power line VDD 1 . For example, the first pixel power line VDD 1  and the first pad VDDP may be provided in the same layer as shown in  FIG. 6 , and may be connected with each other without being spaced apart from each other. 
     Also, the first pixel power line VDD 1  may be connected with a plurality of third pixel power lines VDDL disposed in the display area DA, and may supply the first power source to the driving transistor T of each of the subpixels P 1 , P 2 , and P 3  through the plurality of third pixel power lines VDDL. 
     The first pixel power line VDD 1  may be made of a plurality of metal layers. For example, the first pixel power line VDD 1 , as shown in  FIG. 6 , may include a first metal layer VDD 1 - 1  and a second metal layer VDD 1 - 2  provided over the first metal layer VDD 1 - 1 . The first metal layer VDD 1 - 1  and the second metal layer VDD 1 - 2  may be overlapped with each other, and may be connected with each other through a fourth contact hole CH 4 . 
     In some embodiments, the first metal layer VDD 1 - 1  of the first pixel power line VDD 1  may be provided in the same layer as the source electrode SE and the drain electrode DE of the driving transistor T provided in the display area DA. The first metal layer VDD 1 - 1  may be made of the same material as that of the source electrode SE and the drain electrode DE of the driving transistor T and may be formed simultaneously with them. 
     The second metal layer VDD 1 - 2  of the first pixel power line VDD 1  may be provided in the same layer as the anode auxiliary electrode  115  provided in the display area DA. The second metal layer VDD 1 - 2  may be made of the same material as that of the anode auxiliary electrode  115  and may be formed simultaneously with the anode auxiliary electrode  115 . In this case, the second metal layer VDD 1 - 2  of the first pixel power line VDD 1  may be connected to the first metal layer VDD 1 - 1  through a plurality of fourth contact holes CH 4  that pass through the first planarization layer PLN 1 . 
     In the transparent display panel  110  according to one embodiment of the present disclosure, as the first pixel power line VDD 1  provided in the non-display area NDA is provided as a double layer, a total area of the first pixel power line VDD 1  may be increased, whereby resistance of the first pixel power line VDD 1  may be reduced. 
     Also, in the transparent display panel  110  according to one embodiment of the present disclosure, as the second metal layer VDD 1 - 2  of the first pixel power line VDD 1  may be connected to the first metal layer VDD 1 - 1  through the plurality of fourth contact holes CH 4 , the first metal layer VDD 1 - 1  and the second metal layer VDD 1 - 2  may stably be connected with each other. 
     Meanwhile, in the transparent display panel  110  according to one embodiment of the present disclosure, the first metal layer VDD 1 - 1  and the second metal layer VDD 1 - 2  of the first pixel power line VDD 1  are not in entire contact with each other. If the first metal layer VDD 1 - 1  and the second metal layer VDD 1 - 2  of the first pixel power line VDD 1  are in entire contact with each other, even though the second planarization layer PLN 2  is deposited on the second metal layer VDD 1 - 2 , an upper surface of the area where the first metal layer VDD 1 - 1  and the second metal layer VDD 1 - 2  are in contact with each other may be formed to be recessed toward the first substrate  111  without being planarized. For this reason, a problem may occur in that the layers formed over the first metal layer VDD 1 - 1  and the second metal layer VDD 1 - 2  of the first pixel power line VDD 1 , for example, a second common power connection electrode  185 , the cathode electrode  140 , the encapsulation layer  150  are not deposited stably. 
     In the transparent display panel  110  according to one embodiment of the present disclosure, the first metal layer VDD 1 - 1  and the second metal layer VDD 1 - 2  of the first pixel power line VDD 1  may be in contact with each other through the plurality of fourth contact holes CH 4  without entire contact. In the transparent display panel  110  according to one embodiment of the present disclosure, if the second planarization layer PLN 2  is formed over the second metal layer VDD 1 - 2 , a planarized upper surface may be provided even in the area where the first metal layer VDD 1 - 1  and the second metal layer VDD 1 - 2  are in contact with each other. Therefore, in the transparent display panel  110  according to one embodiment of the present disclosure, the layers formed over the first metal layer VDD 1 - 1  and the second metal layer VDD 1 - 2  of the first pixel power line VDD 1 , for example, the second common power connection electrode  185 , the cathode electrode  140 , the encapsulation layer  150  may be deposited stably. 
     The second pixel power line VDD 2  may be provided to be extended in the second non-display area NDA 2  in a first direction (X axis direction). The second pixel power line VDD 2  may electrically be connected with the first pixel power line VDD 1  through the third pixel power line VDDL. 
     The second pixel power line VDD 2  may be made of a plurality of metal layers like the first pixel power line VDD 1 . For example, the second pixel power line VDD 2  may include a first metal layer and a second metal layer provided over the first metal layer like the first pixel power line VDD 1 . 
     The third pixel power line VDDL may be provided between the transmissive areas TA in the display area DA, and thus may be connected with the driving transistor T of each of the subpixels P 1 , P 2 , and P 3 . The third pixel power line VDDL may be extended in the display area DA in a second direction (Y axis direction), and thus its one end may be connected with the first pixel power line VDD 1  and its other end may be connected with the second pixel power line VDD 2 . 
     In some embodiments, the third pixel power line VDDL may be connected with the first pixel power line VDD 1  or the second pixel power line VDD 2  as one layer but may be connected with the first pixel power line VDD 1  or the second pixel power line VDD 2  as a plurality of layers as shown in  FIG. 6 . 
     For example, the third pixel power line VDDL may include a second metal layer VDDL- 2  and a third metal layer VDDL- 3  provided below the second metal layer VDDL- 2 . The second metal layer VDDL- 2  of the third pixel power line VDDL may be extended from the display area DA to the first non-display area NDA 1  in a second direction (Y axis direction). The second metal layer VDDL- 2  may be provided in the same layer as the anode auxiliary electrode  115  provided in the display area DA. The second metal layer VDDL- 2  may be made of the same material as that of the anode auxiliary electrode  115  and may be formed simultaneously with the anode auxiliary electrode  115 . 
     One end of the third metal layer VDDL- 3  of the third pixel power line VDDL may be connected to the second metal layer VDDL- 2  of the third pixel power line VDDL in the first non-display area NDA 1 , and the other end thereof may be connected to the first pixel power line VDD 1 . The third metal layer VDDL- 3  may be provided in the same layer as the gate electrode GE of the driving transistor T provided in the display area DA. The third metal layer VDDL- 3  may be made of the same material as that of the gate electrode GE of the driving transistor T and may be formed simultaneously with the gate electrode GE. 
     The third metal layer VDDL- 3  of the third pixel power line VDDL may be connected to the second metal layer VDDL- 2  of the third pixel power line VDDL at one end through the first metal layer VDDL- 1 . In this case, the third metal layer VDDL- 3  of the third pixel power line VDDL may be connected to the first metal layer VDDL- 1  through a fifth contact hole CH 5  that passes through the first and second inter-layer insulating layers ILD 1  and ILD 2 . The first metal layer VDDL- 1  may be connected to the second metal layer VDDL- 2  of the third pixel power line VDDL through a sixth contact hole CH 6  that passes through the first planarization layer PLN 1 . Therefore, the third metal layer VDDL- 3  of the third pixel power line VDDL may electrically be connected with the second metal layer VDDL- 2  of the third pixel power line VDDL. 
     Also, the third metal layer VDDL- 3  of the third pixel power line VDDL may be connected to the first metal layer VDD 1 - 1  of the first pixel power line VDD 1  at the other end through a seventh contact hole CH 7  that passes through the first and second inter-layer insulating layers ILD 1  and ILD 2 . 
     Meanwhile, the third metal layer VDDL- 3  of the third pixel power line VDDL may be formed as one line pattern between the second metal layer VDDL- 2  and the first pixel power line VDD 1  but is not limited thereto. The third metal layer VDDL- 3  of the third pixel power line VDDL may include a plurality of line patterns provided between the second metal layer VDDL- 2  and the first pixel power line VDD 1 . In this case, the third metal layer VDDL- 3  of the third pixel power line VDDL may electrically be connected with the plurality of line patterns through the metal layer provided on another layer, for example, the first metal layer VDDL- 1 . 
     Meanwhile, the second metal line may be provided to be extended in the non-display area NDA in a first direction (X axis direction). For example, the second metal line provided in the non-display area NDA may be the common power line VSS. Hereinafter, for convenience of description, a description will be given based on that the second metal line is the common power line VSS. 
     Referring to  FIGS. 2, 5 and 7 , the common power line VSS may supply the second power source to the cathode electrode  140  of the subpixels P 1 , P 2  and P 3  provided in the display area DA. In some embodiments, the second power source may be a common power source commonly supplied to the subpixels P 1 , P 2  and P 3 . 
     Accordingly, in some embodiments, the common power line VSS may include a first common power line VSS 1  provided in the first non-display area NDA 1 , a second common power line VSS 2  provided in the second non-display area NDA 2 , and a plurality of third common power lines VSSL connecting the first common power line VSS 1  with the second common power line VSS 2 . 
     The first common power line VSS 1  may be provided to be extended in the first non-display area NDA 1 , specifically between the first pixel power line VDD 1  and the display area DA in a first direction (X axis direction). The first common power line VSS 1  may be connected with the second pad VSSP in the first non-display area NDA 1 , and may be supplied with a second power source from the second pad VSSP. Also, the first common power line VSS 1  may be connected with the plurality of third common power lines VSSL disposed in the display area DA, and may supply the second power source to the cathode electrode  140  of the subpixels P 1 , P 2 , and P 3  through the plurality of third common power lines VSSL. 
     The first common power line VSS 1  may be made of a plurality of metal layers. For example, the first common power line VSS 1 , as shown in  FIG. 7 , may include a first metal layer VSS 1 - 1  and a second metal layer VSS 1 - 2  provided over the first metal layer VSS 1 - 1 . The first metal layer VSS 1 - 1  and the second metal layer VSS 1 - 2  may be partially overlapped with each other, and may be connected with each other through a fifth contact part CT 5 . 
     In some embodiments, the first metal layer VSS 1 - 1  of the first common power line VSS 1  may be provided in the same layer as the source electrode SE and the drain electrode DE of the driving transistor T provided in the display area DA. The first metal layer VSS 1 - 1  may be made of the same material as that of the source electrode SE and the drain electrode DE of the driving transistor T and may be formed simultaneously with them. 
     The second metal layer VSS 1 - 2  of the first common power line VSS 1  may be provided in the same layer as the anode auxiliary electrode  115  provided in the display area DA. The second metal layer VSS 1 - 2  may be made of the same material as that of the anode auxiliary electrode  115  and may be formed simultaneously with the anode auxiliary electrode  115 . In this case, the second metal layer VSS 1 - 2  of the first common power line VSS 1  may be connected to the first metal layer VSS 1 - 1  through the fifth contact part CT 5  that passes through the first planarization layer PLN 1 . The fifth contact part CT 5  may partially remove the first planarization layer PLN 1  and partially expose the upper surface of the first metal layer VSS 1 - 1  of the first common power line VSS 1 . In some embodiments, the fifth contact part CT 5  may longitudinally expose the upper surface of the first metal layer VSS 1 - 1  of the first common power line VSS 1  along the first direction (X axis direction). The second metal layer VSS 1 - 2  of the first common power line VSS 1  may directly in contact with the exposed upper surface of the first metal layer VSS 1 - 1  of the first common power line VSS 1 . As a result, the second metal layer VSS 1 - 2  of the first common power line VSS 1  may have a wide contact area with the first metal layer VSS 1 - 1  of the first common power line VSS 1 , thereby being stably connected to the first metal layer VSS 1 - 1 . 
     In the transparent display panel  110  according to one embodiment of the present disclosure, as the first common power line VSS 1  provided in the non-display area NDA is provided as a double layer, a total area of the first common power line VSS 1  may be increased, whereby resistance of the first common power line VSS 1  may be reduced. 
     Meanwhile, the first common power line VSS 1  may electrically be connected with the second pad VSSP provided in the pad area PA. In some embodiments, the first pixel power line VDD 1  and the first reference line VREF 1  may be provided between the first common power line VSS 1  and the second pad VSSP. If the first common power line VSS 1  is formed in the same layer as the first pixel power line VDD 1  and the first reference line VREF 1 , the first common power line VSS 1  and the second pad VSSP cannot be formed in the same layer in a single body. 
     The transparent display panel  110  according to one embodiment of the present disclosure may electrically connect the first common power line VSS 1  with the second pad VSSP by using a plurality of connection electrodes disposed on different layers. 
     In detail, the transparent display panel  110  according to one embodiment of the present disclosure may electrically connect the first common power line VSS 1  with the second pad VSSP by using a first common power connection electrode  180  and a second common power connection electrode  185 , which are disposed on their respective layers different from each other. 
     The first common power connection electrode  180  is provided in the first non-display area NDA 1 . The first common power connection electrode  180  is provided between the first common power line VSS 1  and the first substrate  111 , and electrically connects the first common power line VSS 1  with the second pad VSSP. 
     For example, the first common power connection electrode  180  may be provided in the same layer as the gate electrode GE of the driving transistor T provided in the display area DA. Also, the first common power connection electrode  180  may be made of the same material as that of the gate electrode GE of the driving transistor T and may be formed simultaneously with the gate electrode GE. 
     One end of the first common power connection electrode  180  may be connected to the first common power line VSS 1  and the other end of the first common power connection electrode  180  may be connected to the second pad VSSP. In detail, the first common power connection electrode  180  may be connected to the first metal layer VSS 1 - 1  of the first common power line VSS 1  at one end through an eighth contact hole CH 8  that passes through the first and second inter-layer insulating layers ILD 1  and ILD 2 . Also, the first common power connection electrode  180  may be connected to the second pad VSSP at the other end through a ninth contact hole CH 9  that passes through the first and second inter-layer insulating layers ILD 1  and ILD 2 . 
     Meanwhile, the first common power connection electrode  180  may be formed between the second pad VSSP and the first common power line VSS 1  as one electrode but is not limited thereto. The first common power connection electrode  180  may include a plurality of electrodes. 
     For example, the first common power connection electrode  180 , as shown in  FIG. 7 , may include one first common power connection electrode  181 , another first common power connection electrode  182 , and other first common power connection electrode  183 . 
     One first common power connection electrode  181  may be connected to the first common power line VSS 1  through the eighth contact hole CH 8 , and another first common power connection electrode  182  may be connected to the second pad VSSP through the ninth contact hole CH 9 . One first common power connection electrode  181  and another first common power connection electrode  182  may be provided in the same layer as the gate electrode GE of the driving transistor T. 
     One end of the other first common power connection electrode  183  provided over a layer different from one first common power connection electrode  181  and another first common power connection electrode  182  may be connected to the first common power connection electrode  181  through a tenth contact hole CH 10 , and the other end thereof may be connected to the first common power connection electrode  182  through an eleventh contact hole CH 11 . In some embodiments, the other first common power connection electrode  183  may be provided in the same layer as the source electrode SE and the drain electrode DE of the driving transistor T. 
     The second common power connection electrode  185  may be provided in the first non-display area NDA 1 , and may be partially overlapped with the first common power connection electrode  180 . Also, the second common power connection electrode  185  is provided over the first common power line VSS 1 , and electrically connects the first common power line VSS 1  with the second pad VSSP. 
     For example, the second common power connection electrode  185  may be provided in the same layer as the anode electrode  120  of the light emitting diode provided in the display area DA. Also, the second common power connection electrode  185  may be made of the same material as that of the anode electrode  120  of the light emitting diode and may be formed simultaneously with the anode electrode  120 . 
     One end of the second common power connection electrode  185  may be connected to the first common power line VSS 1 , and the other end of the second common power connection electrode  185  may be connected to the second pad VSSP. In detail, the second common power connection electrode  185  may be connected to the second metal layer VSS 1 - 2  of the first common power line VSS 1  at one end through a first contact part CT 1 . The first contact portion CT 1  may partially remove the second planarization layer PLN 2  and partially expose the upper surface of the second metal layer VSS 1 - 2  of the first common power line VSS 1 . In some embodiments, the first contact part CT 1  may longitudinally expose the upper surface of the second metal layer VSS 1 - 2  of the first common power line VSS 1  along the first direction (X axis direction). The second common power connection electrode  185  may directly in contact with the exposed upper surface of the first common power line VSS 1 . As a result, the second common power connection electrode  185  may have a wide contact area with the first common power line VSS 1 , thereby being stably connected to the first common power line VSS 1 . Meanwhile, at least a part of the first contact part CT 1  may be formed to overlap the fifth contact part CT 5 . 
     The second common power connection electrode  185  may be connected to the second pad VSSP at the other end through a second contact part CT 2 . The second contact part CT 2  may partially remove the first planarization layer PLN 1  and partially expose the upper surface of the second pad VSSP. The second pad VSSP, as shown in  FIG. 2 , may include a plurality of pad parts. In some embodiments, two pad parts disposed to adjoin each other may be connected with each other through a pad connection electrode PC. The second contact part CT 2  may expose the upper surface of the second pad VSSP connected by the pad connection electrode PC along the first direction (X axis direction). The second common power connection electrode  185  may directly in contact with the exposed upper surface of the second pad VSSP. As a result, the second common power connection electrode  185  may have a wide contact area with the second pad VSSP, thereby being stably connected to the second pad VSSP. 
     Also, the second common power connection electrode  185  may electrically be connected with the cathode electrode  140  through a cathode contact part CCT in the first non-display area NDA 1 . The cathode contact part CCT may partially remove the bank  125  and partially expose the upper surface of the second common power connection electrode  185 . The cathode contact part CCT may expose the upper surface of the second common power connection electrode  185  along the first direction (X axis direction). As a result, the second common power connection electrode  185  may have a wide contact area with the cathode electrode  140 , thereby being stably connected to the cathode electrode  140 . 
     Consequently, the first common power line VSS 1  may electrically be connected with the cathode electrode  140  through the second common power connection electrode  185 . Therefore, the first common power line VSS 1  may supply the second power source forwarded from the second pad VSSP to the cathode electrode  140 . 
     The second common power line VSS 2  may be extended in the second non-display area NDA 2  in a first direction (X axis direction). The second common power line VSS 2  may electrically be connected with the first common power line VSS 1  through the third common power line VSSL. 
     The second common power line VSS 2  may be made of a plurality of metal layers like the first common power line VSS 1 . For example, the second common power line VSS 2  may include a first metal layer and a second metal layer provided over the first metal layer like the first common power line VSS 1 . 
     The third common power line VSSL is provided between the transmissive areas TA in the display area DA. In some embodiments, the transparent display panel  110  according to one embodiment of the present disclosure may reduce or minimize the non-transmissive area NTA in the display area DA by alternately disposing the third common power line VSSL and the third pixel power line VDDL between the transmissive areas TA. Therefore, the transparent display panel  110  according to one embodiment of the present disclosure may enhance transmittance by increasing the transmissive area TA. 
     Meanwhile, the third common power line VSSL may be extended in the display area DA in a second direction (Y axis direction), and thus its one end may be connected with the first common power line VSS 1  and its other end may be connected with the second common power line VSS 2 . For example, the third common power line VSSL and the first common power line VSS 1 , as shown in  FIG. 7 , may be provided in the same layer, and may be connected with each other without being spaced apart from each other. 
     The transparent display panel  110  according to one embodiment of the present disclosure may electrically connect the first common power line VSS 1  and the second pad VSSP, which are disposed in the first non-display area NDA 1 , with each other by using the first common power connection electrode  180  and the second common power connection electrode  185  disposed on their respective layers different from each other. In some embodiments, the first common power connection electrode may be provided below the first common power line VSS 1  and the second pad VSSP, and the second common power connection electrode may be provided over the first common power line VSS 1  and the second pad VSSP. 
     Therefore, the transparent display panel  110  according to one embodiment of the present disclosure may increase a total area of the common power line VSS, whereby resistance of the common power line VSS may be reduced. 
     Also, in the transparent display panel  110  according to one embodiment of the present disclosure, even though a defect occurs in any one of the first common power connection electrode  180  and the second common power connection electrode  185 , the first common power line VSS 1  and the second pad VSSP may be connected with each other by the other one. Therefore, since the transparent display panel  110  according to one embodiment of the present disclosure may stably supply the second power source to the subpixels P 1 , P 2  and P 3 , panel yield may be improved. 
     The third metal line may be provided to be extended in the non-display area NDA in a first direction (X axis direction). For example, the third metal line provided in the non-display area NDA may be the reference line VREF. Hereinafter, for convenience of description, a description will be given based on that the third metal line is the reference line VREF. 
     Referring to  FIGS. 2, 5, and 8 , the reference line VREF may supply an initialization voltage (or sensing voltage) to the driving transistor T of each of the subpixels P 1 , P 2 , and P 3  provided in the display area DA. 
     Accordingly, in some embodiments, the reference line VREF may include a first reference line VREF 1  provided in the first non-display area NDA 1 , and a plurality of second reference lines VREFL disposed in the display area DA. 
     The first reference line VREF 1  may be provided to be extended in the first non-display area NDA 1 , specifically between the first pixel power line VDD 1  and the first common power line VSS 1  in a first direction (X axis direction). The first reference line VREF 1  may be connected with the third pad VREFP in the first non-display area NDA 1 , and may be supplied with the initialization voltage (or sensing voltage) from the third pad VREFP. Also, the first reference line VREF 1  may be connected with the plurality of second reference lines VREFL disposed in the display area DA, and may supply the initialization voltage (or sensing voltage) to the transistor T of each of the subpixels P 1 , P 2  and P 3  through the plurality of second reference lines VREFL. 
     The first reference line VREF 1  may be made of a plurality of metal layers. For example, the first reference line VREF 1 , as shown in  FIG. 8 , may include a first metal layer VREF 1 - 1  and a second metal layer VREF 1 - 2  provided over the first metal layer VREF 1 - 1 . The first metal layer VREF 1 - 1  and the second metal layer VREF 1 - 2  may be partially overlapped with each other, and may be connected with each other through a twelfth contact hole CH 12 . 
     In some embodiments, the first metal layer VREF 1 - 1  of the first reference line VREF 1  may be provided in the same layer as the source electrode SE and the drain electrode DE of the driving transistor T provided in the display area DA. The first metal layer VREF 1 - 1  may be made of the same material as that of the source electrode SE and the drain electrode DE of the driving transistor T and may be formed simultaneously with them. 
     The second metal layer VREF 1 - 2  of the first reference line VREF 1  may be provided in the same layer as the anode auxiliary electrode  115  provided in the display area DA. The second metal layer VREF 1 - 2  may be made of the same material as the anode auxiliary electrode  115  and may be formed simultaneously with the anode auxiliary electrode  115 . In this case, the second metal layer VREF 1 - 2  of the first reference line VREF 1  may be connected to the first metal layer VREF 1 - 1  through the twelfth contact hole CH 12  that passes through the first planarization layer PLN 1 . 
     In the transparent display panel  110  according to one embodiment of the present disclosure, as the first reference line VREF 1  provided in the non-display area NDA is provided as a double layer, a total area of the first reference line VREF 1  may be increased, whereby resistance of the first reference line VREF 1  may be reduced. 
     Meanwhile, the first reference line VREF 1  may electrically be connected with the third pad VREFP provided in the pad area PA. In some embodiments, the first pixel power line VDD 1  may be provided between the first reference line VREF 1  and the third pad VREFP. If the first reference line VREF 1  is formed in the same layer as the first pixel power line VDD 1 , the first reference line VREF 1  and the third pad VREFP cannot be formed in the same layer in a single body. 
     The transparent display panel  110  according to one embodiment of the present disclosure may electrically connect the first reference line VREF 1  with the third pad VREFP by using a plurality of connection electrodes disposed over different layers. 
     In detail, the transparent display panel  110  according to one embodiment of the present disclosure may electrically connect the first reference line VREF 1  with the third pad VREFP by using a first reference connection electrode  190  and a second reference connection electrode  195 , which are disposed on their respective layers different from each other. 
     The first reference connection electrode  190  is provided in the first non-display area NDA 1 . The first reference connection electrode  190  is provided between the first reference line VREF 1  and the first substrate  111 , and electrically connects the first reference line VREF 1  with the third pad VREFP. 
     For example, the first reference connection electrode  190  may be provided in the same layer as the gate electrode GE of the driving transistor T provided in the display area DA. Also, the first reference connection electrode  190  may be made of the same material as that of the gate electrode GE of the driving transistor T and may be formed simultaneously with the gate electrode GE. 
     One end of the first reference connection electrode  190  may be connected to the first reference line VREF 1  and the other end of the first reference connection electrode  190  may be connected to the third pad VREFP. In detail, the first reference connection electrode  190  may be connected to the first metal layer VREF 1 - 1  of the first reference line VREF 1  at one end through a thirteenth contact hole CH 13  that passes through the first and second inter-layer dielectric films ILD 1  and ILD 2 . Also, the first reference connection electrode  190  may be connected to the third pad VREFP at the other end through a fourteenth contact hole CH 14  that passes through the first and second inter-layer dielectric films ILD 1  and ILD 2 . 
     Meanwhile, the first reference connection electrode  190  may be formed between the first reference line VREF 1  and the third pad VREFP as one electrode but is not limited thereto. The first reference connection electrode  190  may include a plurality of electrodes. 
     The second reference connection electrode  195  may be provided in the first non-display area NDA 1 . At least a part of the second reference connection electrode  195  may be overlapped with the first reference connection electrode  190 . The second reference connection electrode  195  is provided over the first reference line VREF 1 , and electrically connects the first reference line VREF 1  with the third pad VREFP. 
     For example, the second reference connection electrode  195  may be provided in the same layer as the anode electrode  120  of the light emitting diode provided in the display area DA. Also, the second reference connection electrode  195  may be made of the same material as that of the anode electrode  120  of the light emitting diode and may be formed simultaneously with the anode electrode  120 . 
     One end of the second reference connection electrode  195  may be connected to the first reference line VREF 1  and the other end thereof may be connected to the third pad VREFP. In detail, the second reference connection electrode  195  may be connected to the second metal layer VREF 1 - 2  of the first reference line VREF 1  at one end through a third contact part CT 3 . The third contact part CT 3  may partially remove the second planarization layer PLN 2  and partially expose the upper surface of the second metal layer VREF 1 - 2  of the first reference line VREF 1 . In some embodiments, the third contact part CT 3  may expose the upper surface of the second metal layer VREF 1 - 2  of the first reference line VREF 1  along the first direction (X axis direction). As a result, the second reference connection electrode  195  may have a wide contact area with the first reference line VREF 1 , thereby being stably connected to the first reference line VREF 1 . 
     The second reference connection electrode  195  may be connected to the third pad VREFP at the other end through a fourth contact part CT 4 . The fourth contact part CT 4  may partially remove the first planarization layer PLN 1  and partially expose the upper surface of the third pad VREFP. In some embodiments, the fourth contact portion CT 4  may expose the upper surface of the third pad VREFP along the first direction (X axis direction). The second reference connection electrode  195  may directly in contact with the exposed upper surface of the third pad VREFP. As a result, the second reference connection electrode  195  may have a wide contact area with the third pad VREFP, thereby being stably connected to the third pad VREFP. 
     The second reference connection electrode  195  is formed in the same layer as the second common power connection electrode  185  but is spaced apart from the second common power connection electrode  185 . Therefore, the second reference connection electrode  195  is not electrically connected with the second common power connection electrode  185 . 
     The transparent display panel  110  according to one embodiment of the present disclosure may connect the first reference line VREF 1  and the third pad VREFP, which are disposed in the first non-display area NDA 1 , with each other by using the first reference connection electrode  190  and the second reference connection electrode  195  disposed on their respective layers different from each other. In some embodiments, the first reference connection electrode  190  may be provided below the first reference line VREF 1  and the third pad VREFP, and the second reference connection electrode  195  may be provided over the first reference line VREF 1  and the third pad VREFP. 
     Therefore, the transparent display panel  110  according to one embodiment of the present disclosure may increase a total area of the first reference line VREF 1 , whereby resistance of the first reference line VREF 1  may be reduced. 
     Also, in the transparent display panel  110  according to one embodiment of the present disclosure, even though a defect occurs in any one of the first reference connection electrode  190  and the second reference connection electrode  195 , the first reference line VREF 1  and the third pad VREFP may be connected with each other by the other one. Therefore, since the transparent display panel  110  according to one embodiment of the present disclosure may stably supply the initialization voltage (or sensing voltage) to the subpixels P 1 , P 2  and P 3 , panel yield may be improved. 
     Also, the transparent display panel  110  according to one embodiment of the present disclosure may test a defect of the driving transistor T before the anode electrode  120  is deposited. 
     The transparent display panel  110  may connect the first common power line VSS 1  with the second pad VSSP by using only the second common power connection electrode  185  provided in the same layer as the anode electrode  120 . Also, the transparent display panel  110  may connect the first reference line VREF 1  with the third pad VREFP by using only the second reference connection electrode  195  provided in the same layer as the anode electrode  120 . 
     In this case, a process of testing a defect of the driving transistor T has no choice but to be performed after the anode electrode  120  is deposited. If a defect occurs in the driving transistor T, a repair process may be performed to repair a portion where the defect has occurred. In some embodiments, the layers deposited on the layer where the defect has occurred should be removed to perform the repair process. For example, if the defect occurs in the layer provided with the anode auxiliary electrode  115 , the second planarization layer PLN 2  and the anode electrode  120  should be removed for the repair process. In some embodiments, luminescence may not be performed in the corresponding area. 
     In this way, if the repair process is performed after the anode electrode  120  is formed, repair yield is reduced due to the anode electrode  120  and the organic layer PLN 2  provided over the anode auxiliary electrode  115 , and a tact time is increased. 
     The transparent display panel  110  according to one embodiment of the present disclosure may connect the first common power line VSS 1  with the second pad VSSP by using the first common power connection electrode  180  and the second common power connection electrode  185 . Also, the transparent display panel  110  according to one embodiment of the present disclosure may connect the first common power line VSS 1  with the second pad VSSP through the first common power connection electrode  180  even though the second common power connection electrode  185  is not formed. 
     The transparent display panel  110  according to one embodiment of the present disclosure may connect the first reference line VREF 1  with the third pad VREFP by using the first reference connection electrode  190  and the second reference connection electrode  195 . Also, the transparent display panel  110  according to one embodiment of the present disclosure may connect the first reference line VREF 1  with the third pad VREFP through the first reference connection electrode  190  even though the second reference connection electrode  195  is not formed. 
     Therefore, the transparent display panel  110  according to one embodiment of the present disclosure may test a defect of the driving transistor T before the anode electrode  120  is deposited. That is, since the repair process is performed before the second planarization layer PLN 2  and the anode electrode  120  are deposited, the transparent display panel  110  according to one embodiment of the present disclosure may prevent repair yield from being reduced due to the second planarization layer PLN 2  and the anode electrode  120 . In addition, the transparent display panel  110  according to one embodiment of the present disclosure may reduce a tact time. 
     Meanwhile, in the transparent display panel  110  according to one embodiment of the present disclosure, the pixel power line VDD, the common power line VSS and the first reference line VREF 1  may be provided in only the first non-display area NDA 1  and the second non-display area NDA 2  of the non-display area NDA. In the transparent display panel  110  according to one embodiment of the present disclosure, each of the pixel power line VDD, the common power line VSS and the first reference line VREF 1  may be formed in a double layered structure, and the common power line VSS and the first reference line VREF 1  may respectively be connected with the plurality of connection electrodes. Therefore, even though the pixel power line VDD, the common power line VSS and the first reference line VREF 1  are provided in only the first non-display area NDA 1  and the second non-display area NDA 2 , the transparent display panel  110  according to one embodiment of the present disclosure may make sure of a sufficient area of each of the pixel power line VDD, the common power line VSS and the first reference line VREF 1  and reduce or minimize resistance. 
     In the transparent display panel  110  according to one embodiment of the present disclosure, as the pixel power line VDD, the common power line VSS and the first reference line VREF 1  are not provided in the third non-display area NDA 3  and the fourth non-display area NDA 4 , transmittance in the third non-display area NDA 3  and the fourth non-display area NDA 4  may be improved. That is, the transparent display panel  110  according to one embodiment of the present disclosure may have transmittance even in the third non-display area NDA 3  and the fourth non-display area NDA 4 , which is similar to that of the display area DA. 
     It will be apparent to those skilled in the art that the present disclosure described above is not limited by the above-described embodiments and the accompanying drawings and that various substitutions, modifications, and variations can be made in the present disclosure without departing from the spirit or scope of the disclosures. Consequently, the scope of the present disclosure is intended to cover all variations or modifications derived from the meaning, scope, and equivalent concept of the present disclosure. 
     The various embodiments described above can be combined to provide further embodiments. All of the U.S. patents, U.S. patent application publications, U.S. patent applications, foreign patents, foreign patent applications and non-patent publications referred to in this specification and/or listed in the Application Data Sheet are incorporated herein by reference, in their entirety. Aspects of the embodiments can be modified, if necessary to employ concepts of the various patents, applications and publications to provide yet further embodiments. 
     These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.