Patent Publication Number: US-7915158-B2

Title: Method for forming an on-chip high frequency electro-static discharge device

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This patent application relates to commonly-assigned U.S. patent application Ser. No. 12/144,081 entitled “DESIGN STRUCTURE FOR AN ON-CHIP HIGH FREQUENCY ELECTRO-STATIC DISCHARGE DEVICE”, Ser. No. 12/144,089 entitled “METHOD FOR FORMING AN ON-CHIP HIGH FREQUENCY ELECTRO-STATIC DISCHARGE DEVICE”, and Ser. No. 12/144,095 entitled “DESIGN STRUCTURE FOR AN ON-CHIP HIGH FREQUENCY ELECTRO-STATIC DISCHARGE DEVICE”, all filed concurrently with this application. 
     FIELD OF THE INVENTION 
     This disclosure relates generally to integrated circuit design, and more specifically to a method for forming an on-chip high frequency electro-static discharge device. 
     BACKGROUND 
     As electronic components get smaller and smaller along with the internal structures in integrated circuits, it is becoming easier to either completely destroy or otherwise impair electronic components. In particular, many integrated circuits are highly susceptible to damage from the discharge of static electricity. Electro-static discharge (ESD) is the transfer of an electro-static charge between bodies at different electro-static potentials (voltages), caused by direct contact or induced by an electro-static field. The discharge of static electricity, or ESD, has become a critical problem for the electronics industry. 
     Device failures that result from ESD events are not always immediately catastrophic or apparent. Often, the device is only slightly weakened but is less able to withstand normal operating stresses and hence, may result in a reliability problem. Therefore, various ESD protection circuits must be included in the device to protect the various components. 
     Typical ESD protection circuits use an on-chip diode based ESD protection. These on-chip diode ESD devices work well for lower frequency currents but at higher frequency circuits such as millimeter wave circuits, these ESD protection circuits severely impair the performance of the millimeter wave circuits because of its inability to ameliorate the large parasitic capacitance that arises during the high operating frequency. 
     One approach that has been contemplated for overcoming the problems associated with using an on-chip diode ESD device for millimeter wave circuits is to use a matching circuit for ESD protection. However, the use of a matching circuit for ESD protection is a high risk solution because almost all matching circuits comprise inductances. Problems can arise when a high ESD current flows through the circuit. In particular, when a high ESD current flows through the circuit, the inductance generates high voltage which can damage input and output circuits. 
     SUMMARY 
     In one embodiment, there is a method for forming an electro-static discharge protection device on an integrated circuit. In this embodiment, the method comprises: providing a wafer including a first dielectric layer with more than one electrode formed therein, a second dielectric layer disposed over the first dielectric layer with more than one electrode formed therein and more than one via connecting the more than one electrode in the first dielectric layer to a respective more than one electrode in the second dielectric layer, wherein the more than one via is misaligned a predetermined amount with the more than one electrodes in the first dielectric layer and the second dielectric layer, and wherein at least one of the misaligned vias forms a narrow gap with another misaligned via; forming a cavity trench through the second dielectric layer, wherein the cavity trench is formed in the second dielectric layer between the narrow gap that separates the misaligned vias; depositing a pinching layer over an opening in the second dielectric layer created by the formation of the cavity trench, wherein the pinching layer pinches off the opening creating a high aspect ratio; and depositing a third dielectric layer over the second dielectric layer, wherein the third dielectric layer hermetically seals the pinching layer and the cavity trench to provide electro-static discharge protection. 
     In a second embodiment, there is a method for forming an electro-static discharge protection device on an integrated circuit. In this embodiment, the method comprises: providing a wafer with metal wiring, wherein the metal wiring includes multiple metal level layers disposed therein with each metal level comprising more than one electrode formed therein and more than one via connecting some of the electrodes in adjacent metal levels, an interlevel dielectric layer disposed over the multiple metal level layers and at least two last metal electrodes separated by a minimum gap therebetween that extend through the interlevel dielectric layer to a top level of the multiple metal layers; depositing a passivation layer over the interlevel dielectric layer and the at least two last metal electrodes and in the gap formed therebetween; and removing a portion of the passivation layer from the gap separating the at least two last metal electrodes to form an air gap that provides electro-static discharge protection. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  shows a top-down view of an electro-static discharge device according to one embodiment of the disclosure; 
         FIG. 2  shows a top-down view of an electro-static discharge device according to a second embodiment of the disclosure; 
         FIGS. 3-8  show the general process flow of forming an electro-static discharge device depicted in  FIGS. 1 and 2  according to one embodiment of this disclosure; and 
         FIGS. 9-10  show the general process flow of forming an electro-static discharge device depicted in  FIGS. 1 and 2  according to a second embodiment of this disclosure. 
     
    
    
     DETAILED DESCRIPTION 
       FIG. 1  shows a top-down view of an electro-static discharge (ESD) device  10  according to one embodiment of the disclosure. As shown in  FIG. 1 , the ESD device  10  comprises a pad  12  which connects to components of a circuit such as a high frequency (e.g., a millimeter wave) circuit (not shown). A metal wire  14 , separated by a gap  16 , is adjacent to the pad  12 . The metal wire  14  is a wire in the high frequency circuit (not shown) that is grounded by a substrate in the circuit (not shown). The gap  16  can be a vacuum gap or an air gap. Tips  18   a  and  18   b  protrude from the pad  12  and the metal wire  14 , respectively, into the gap  16 . Tips  18   a  and  18   b  can be made of copper, aluminum, tungsten or the like. As shown in  FIG. 1 , tips  18   a  and  18   b  have sharp tips and are separated from each other in the gap  16  by a distance denoted by d. Because the size of tips  18   a  and  18   b  can be designed to be as small as a minimum metal line width defined by a design rule, the parasitic capacitance can be ignored. Those skilled in the art will recognize that tips  18   a  and  18   b  can take on different shapes and that the distance d can vary depending on the amount of protection desired to ameliorate high voltage events (i.e., the distance d determines the ESD clamping voltage). 
     An ESD event (e.g., a high voltage) will enter the device  10  through the pad  12  (the pad is connected to the outside world) towards tips  18   a  and  18   b . When the voltage applied to tips  18   a  and  18   b  exceeds the clamping voltage, a discharge occurs in the tips through the air gap such that the high voltage event is grounded through the metal wire  14  to the substrate. During the discharge, resistance is very low which keeps the voltage between the tips very low so that the underlying circuit can be protected. When the voltage is lower than the clamping voltage, then the discharge is over and tips  18   a  and  18   b  are resumed isolated. 
     Those skilled in the art will recognize that the ESD device  10  shown in  FIG. 1  is only one possible embodiment of implementing this concept and that other implementations are possible. For example,  FIG. 2  shows a top-down view of an ESD device  19  according to a second embodiment of the disclosure. In particular, the ESD device  19  includes multiple tips  18   a ,  18   b ,  18   c , and  18   d . The ESD device  19  operates in a manner similar to the ESD device  10 , except that multiple tips are used to discharge high voltage events. Although four tips are shown in  FIG. 2 , those skilled in the art will recognize that this only illustrative and that any reasonable number of tips can be used. 
       FIGS. 3-8  show the general process flow of forming an ESD device depicted in  FIGS. 1 and 2  according to one embodiment of this disclosure. In particular,  FIGS. 3-8  generally pertain to a process of forming ESD device  10  depicted in  FIG. 1 , however, the description is suitable for fabricating ESD device  19 . Those skilled in the art will recognize that forming ESD device  19  will require additional steps to produce the extra tips. 
     The process starts with an incoming wafer having metal wiring. As shown in  FIGS. 3A-3C , the metal wiring in the incoming wafer includes two metal levels. In one metal level there is a first inter-level dielectric (ILD) layer  20  having more than one electrode  22  formed therein and a capping layer  24  deposited on the ILD layer. In the second metal level, there is a second ILD layer  26  with more than one electrode  28  formed therein. A via  30  connects the electrodes  22  in the first ILD layer  20  to the electrodes  28  in the second ILD layer  26 . The ILD layers  20  and  26  are any suitable dielectric film that may include organosilicate glass (SiCOH), fluoride silicate glass (FSG) or undoped silicate glass (USG). The electrodes  22  and  28  are a metal such as copper, however, other possible metals such as aluminum or tungsten can be used. The capping layer  24  is a dielectric film that is generally used to prevent oxidation and improve electro-migration. A non-exhaustive listing of materials used for the capping layer  24  may include silicon nitride, silicon carbide, silicon carbon nitride, or other suitable dielectric materials. 
       FIGS. 3A-3C  differ in that the via  30  in each figure is located in a different position with respect to the electrodes  22  and  28 .  FIG. 3A  shows that the via  30  is misaligned to the right of the electrodes. In one embodiment, the misalignment of the via  30  can be about +40 nm.  FIG. 3B  shows that the via  30  has zero alignment with the electrodes.  FIG. 3C  shows that the via  30  is misaligned to the left of the electrodes. In one embodiment, the misalignment of the via  30  can be about −40 nm. 
     In  FIG. 4 , a capping layer  32  is deposited on second ILD layer  26  such that this layer covers the electrodes  28 . The capping layer  32  may include material such as Si 3 N 4 , SiC, or SiCN. The capping layer  32  is deposited on the second ILD layer  26  using any suitable deposition technique that may include plasma enhanced chemical vapor deposition (PECVD), molecular CVD, atomic layer deposition. Note that in  FIG. 4 , the two vias  30  in the center of the figure are misaligned with respect to their corresponding electrodes in the first metal level and the second metal level such that a narrow gap  33  is formed therebetween. 
     In  FIG. 5 , a photoresist film  34  is deposited over the capping layer  32 . The photoresist film is exposed and developed to form an opening  35  above the narrow gap  33  that separates the misaligned vias. 
     In  FIG. 6 , the formation of a cavity trench  36  continues through the capping layer  32  and the second ILD layer  26  through the gap  33  to the top surface of capping layer  24 . The cavity trench formed through the gap is performed by using a conventional etch. In one embodiment, the etch may include a reactive ion etching (RIE) operation such as a non-selective RIE (non-oxidizing) in conjunction with a reactive resist strip (e.g., H 2  or N 2 ) and a defluorination plasma clean operation to remove the remainder of the photoresist film  34 . 
     In  FIG. 7 , a capping layer  38  is deposited over the capping layer  32 . As shown in  FIG. 7 , the capping layer  38  is deposited over the opening in the cavity trench  36 . This deposition forms a pinching layer  40  over the opening in the cavity trench  36  with the second ILD  26 . As a result, the pinching layer  40  pinches off the opening and creates a high aspect ratio. The capping layer  38  and pinching layer  40  may include material such as Si 3 N 4 , SiC, or SiCN. The capping layer  38  and pinching layer  40  are deposited using any suitable deposition technique that may include plasma enhanced chemical vapor deposition (PECVD), chemical vapor deposition (CVD), molecular CVD, or atomic layer deposition. 
     In  FIG. 8 , a third ILD layer  42  is deposited over the capping layer  38 , the pinching layer  40  and the second ILD layer  26 . The ILD layer  42  includes an electrode  44  and a via  30  that connects this electrode to electrodes  28  and  22  in the second ILD layer  26  and the first ILD layer  20 , respectively. In this implementation, the ILD layer  42  hermetically seals the pinching layer and the cavity trench  36  to provide ESD protection. The ILD layer  42 , electrode  44  and connecting via  30  in this level are formed by plasma enhanced chemical vapor deposition (PECVD), or spin-on technique. As with the other metal levels, the third ILD layer  42  may include any suitable dielectric film such as organosilicate glass (SiCOH), fluoride silicate glass (FSG) or undoped silicate glass (USG) and the electrode  44  is a metal that may include copper, aluminum, or tungsten. After forming the ESD device shown in  FIG. 8 , it is integrated with an integrated circuit by coupling it to the pad of the circuit to provide ESD protection against ESD events. 
       FIGS. 9-10  show the general process flow of forming an ESD device depicted in  FIGS. 1 and 2  according to a second embodiment of this disclosure. In particular,  FIGS. 9-10  generally pertain to a process of forming ESD device  10  depicted in  FIG. 1 , however, the description is suitable for fabricating ESD device  19 . Those skilled in the art will recognize that forming ESD device  19  will require additional steps to produce the extra tips. 
     The process starts with an incoming wafer having metal wiring. As shown in  FIG. 9 , the metal wiring in the incoming wafer includes multiple metal levels. For ease of illustration,  FIG. 9  discloses three metal levels, however, those skilled in the art will recognize that more or less metal levels can be used. In one metal level there is a first inter-level dielectric (ILD) layer  46  having more than one electrode  48  formed therein and a capping layer  50  deposited on the ILD layer  46 . In a second metal level, there is a second ILD layer  52  with more than one electrode  54  formed therein and a capping layer  56  deposited on the ILD layer  52 . In a third metal level, there is a third ILD layer  58  with more than one electrode  60  formed therein and a capping layer  62  deposited on the ILD layer  58 . Vias  64  connect some of the electrodes  48  in the first ILD layer  46  to some of the electrodes  54  in the second ILD layer  52  and some of the electrodes  54  in the second ILD layer  52  to electrodes  60  in the third ILD layer  58 . As shown in  FIG. 9 , a fourth ILD layer  66  is deposited over capping layer  62  in  FIG. 9 . The ILD layers  46 ,  52 ,  58  and  66  are any suitable dielectric film that may include organosilicate glass (SiCOH), fluoride silicate glass (FSG) or undoped silicate glass (USG). The electrodes  48 ,  54  and  60  are a metal such as copper, however, other possible metals such as aluminum, or tungsten can be used. The capping layers  50 ,  56  and  62  can by any dielectric film as silicon nitride, silicon carbide, or silicon carbon nitride. 
       FIG. 9  also shows that the incoming wafer includes at least two last metal electrodes  68  deposited over electrodes  60  in the third ILD layer  58  through the fourth ILD layer  66  and the capping layer  62 . The two last metal electrodes  68  are separated by a minimum gap  70  that extends to a top level of the multiple metal layers (i.e., the ILD layer  66 ). The last metal electrodes  68  comprise an aluminum wire. 
     In  FIG. 10 , a passivation layer  72  (e.g., another ILD layer) is deposited over the ILD layer  66  and the two last metal electrodes  68  and in the gap formed therebetween. The passivation layer  72  may include an oxide material, a nitride material, or a combination of SiO 2  and Si 3 N 4 . The passivation layer  72  is deposited on the ILD layer  66  using any suitable deposition technique that may include plasma enhanced chemical vapor deposition (PECVD), chemical vapor deposition (CVD), or molecular CVD. 
       FIG. 10  also shows that a portion of the passivation layer has been removed from the gap  70  separating the two last metal electrodes  68  to form a gap (air-filled or vacuum filled)  74  that provides ESD protection. In one embodiment, the gap  74  is formed by an etching operation such as a wet etch. In another embodiment, a RIE operation can be used to form the gap  74 . The formed gap  74  results in a high aspect ratio that in one embodiment is greater than 2:1.  FIG. 10  also shows that the etching operation removes a portion of passivation film  72  from underneath each of the last metal electrodes  68  at locations  76 , which are also air-filled or vacuum filled. After forming the ESD device shown in  FIG. 10 , it is integrated with an integrated circuit by coupling it to the pad of the circuit to provide ESD protection against ESD events. 
     The foregoing processes described in  FIGS. 3-10  shows some of the processing functions associated with fabricating the ESD device according to different embodiments. In this regard, each figure represents a process act associated with forming the ESD device according to one of these embodiments. It should also be noted that in some alternative implementations, the acts noted in the figures may occur out of the order noted in the figures or, for example, may in fact be executed in different order, depending upon the acts involved. Also, one of ordinary skill in the art will recognize that additional figures that describe the formation of the ESD device may be added for each of these embodiments. 
     The integrated circuit chips that are integrated with the ESD devices described herein can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor. 
     It is apparent that there has been provided by this disclosure a method for forming an on-chip high frequency electro-static discharge device. While the disclosure has been particularly shown and described in conjunction with a preferred embodiment thereof, it will be appreciated that variations and modifications will occur to those skilled in the art. Therefore, it is to be understood that the appended claims are intended to cover all such modifications and changes as fall within the true spirit of the disclosure.