Patent Publication Number: US-7906951-B2

Title: Switching regulator having reverse current detector

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a switching regulator, and particularly to a synchronous rectification switching regulator. 
     2. Description of Related Art 
     Power supply voltage to be applied to a semiconductor device has been decreasing with the reduction in size of semiconductor devices. To supply power to such semiconductor devices, synchronous rectification switching regulators are often used. A switching regulator steps down or steps up voltage from a power supply, such as a battery, to apply the resultant voltage, as power, to a semiconductor device. When the load current decreases in such a switching regulator under light load conditions, the direction of the current flowing through an output inductor is inverted, so that the current flows from the output inductor to ground through a synchronous rectifier transistor, in some cases. Since the current is supplied from an output capacitor without being supplied to the load, the power is wasted. To solve this, Patent documents 1, 2 and 3 each disclose a technique to detect an inversion of the direction of current flowing through an inductor under light load conditions, and to perform, upon detection, control such that a synchronous rectifier transistor can be turned off. 
     For example, the DC-DC converter described in Patent document 1 includes: a first potential; a pair of power transistors, which are disposed in series between the first potential and a second potential, the second potential being lower than the first potential, and which convert direct current voltage of the potential difference between the first and second potentials into alternating current voltage; detection means, which outputs a detection signal when the alternating current voltage is lower than the second potential by a predetermined value; and a control circuit, which is provided for controlling the pair of power transistors, and which turns off the power transistor (a synchronous rectifier transistor) disposed on the second potential side, in response to the detection signal. 
     In the above DC-DC converter, the detection means outputs a detection signal when the alternating current voltage is lower than the second potential by the predetermined value. Thus, a detection signal is outputted before the alternating current voltage becomes equal to the second potential. This makes it possible to compensate for the effect of delay time caused by the detection means, thereby to highly accurately turn off the power transistor (a synchronous rectifier transistor) around an operation range in which the alternating current becomes 0. 
     [Patent document 1] Japanese Patent Laid Open Application No. 2006-333689 
     [Patent document 2] Japanese Patent Laid Open Application No. 2007-20315 
     [Patent document 3] Japanese Patent Laid Open Application No. 2007-6555 
     As the above detection means, a comparator is generally used. A comparator compares the voltages of a non-inverting (+) input terminal and an inverting (−) input terminal, and sets an output (OUT) at high level when the voltage of the + input terminal (CP+) is higher than the voltage of the − input terminal (CP−) while setting an output (OUT) at low level when the voltage of the + input terminal (CP+) is lower than the voltage of the − input terminal (CP−). 
       FIG. 8  is charts schematically showing operation waveforms of the comparator. As shown in  FIG. 8  (A), when the voltage of the + input terminal (CP+) decreases to a voltage lower than the voltage of the − input terminal (CP−), the output (OUT) is switched from high level to low level with a delay of a time period Td 1 . By contrast, when the voltage (CP+) increases to a voltage higher than the voltage (CP−), the output (OUT) is switched from low level to high level with a delay of a time period Td 2 . 
     Assume that the voltage (CP+) decreases to a voltage lower than the voltage (CP−) by ΔV. When ΔV is small, the time periods Td 1  and Td 2  increase as shown in  FIG. 8  (B), in other words, reaction of comparison operation is slower. Moreover, when ΔV is even smaller, the output (OUT) is kept at high level without being switched to low level, as shown in  FIG. 8  (C). Thus, the comparator has characteristics of not outputting any comparison result of comparison operation in a case where a difference between levels of input comparison signals is extremely small and where the duration time of such condition is shorter than a time duration called dead zone width. 
     When load current decreases under light load conditions, the above-mentioned alternating current voltage becomes slightly lower than the second potential by a predetermined value. In this case, there is a possibility that the comparator does not output any comparison result because of the above-described characteristics of the comparator, so that the synchronous rectifier transistor is not turned off. Accordingly, the comparator cannot carry out comparison operation with high accuracy under light load conditions and hence the synchronous rectifier transistor is not turned off. This may possibly reduce efficiency in power conversion under light load conditions. 
     SUMMARY OF THE INVENTION 
     A switching regulator according to an aspect of the present invention is a switching regulator. The switching regulator includes first and second transistors, which are provided in series between power sources respectively having first and second potentials, and which convert a direct current voltage of a potential difference between the first and the second potentials into an alternating current voltage; and a control circuit. 
     The control circuit includes a comparator which compares the alternating current voltage and a threshold voltage in a period when the second transistor is to be on, and receives a predetermined voltage, in at least immediately before the period in which the second transistor is to be on, the predetermined voltage being farther than a midpoint potential of the first and second potentials from the threshold voltage. 
     The control circuit performs control such that the second transistor becomes turned off, when the comparator judges that the alternating current voltage has exceeded the threshold voltage toward the midpoint potential direction, in the period when the second transistor is to be on. 
     According to the present invention, the predetermined voltage, instead of the alternating current voltage, is applied to the comparison input terminal of the comparator at least immediately before the period in which the first transistor is to be on. Such configuration makes it possible to perform control such that the first transistor can be certainly turned off even in a case where the comparator cannot carry out comparison operation with high accuracy under light load conditions. As a result, efficiency in power conversion under light load conditions can be improved. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The above and other exemplary aspects, advantages and features of the present invention will be more apparent from the following description of certain exemplary embodiments taken in conjunction with the accompanying drawings, in which: 
         FIG. 1  is a block diagram showing a configuration of a switching regulator according to a first example of the present invention; 
         FIG. 2  is a circuit diagram showing an example of a reverse current detection unit according to the first example of the present invention; 
         FIG. 3  is a circuit diagram showing an example of a comparator; 
         FIG. 4  is a timing chart showing waveforms of the units of the switching regulator according to the first example of the present invention; 
         FIG. 5  is a block diagram showing a configuration of a switching regulator according to a second example of the present invention; 
         FIG. 6  is a circuit diagram showing an example of a reverse current detection unit according to the second example of the present invention; 
         FIG. 7  is a timing chart showing waveforms of the units of the switching regulator according to the second example of the present invention; and 
         FIGS. 8A to 8C  are charts schematically showing operation waveforms of a comparator. 
     
    
    
     DETAILED DESCRIPTION OF THE EXEMPLARY EMBODIMENTS 
     A switching regulator according to an exemplary embodiment of the present invention is a synchronous rectification switching regulator that includes a switching transistor, a synchronous rectifier transistor, and a control circuit. The switching transistor and the synchronous rectifier transistor are provided in series between power sources respectively having first and second potentials, and convert direct current voltage of the potential difference between the first and the second potentials into alternating current voltage. The control circuit includes a comparator for comparing the alternating current voltage with a threshold voltage in a period when the synchronous rectifier transistor is to be on. The control circuit applies a predetermined voltage, instead of the alternating current voltage, to a comparison input terminal of the comparator at least immediately before a period in which the synchronous rectifier transistor is to be on, the predetermined voltage being farther than the midpoint potential of the first and second potentials from the threshold voltage. Moreover, the control circuit performs control such that the synchronous rectifier transistor can be turned off, when the comparator judges that the alternating current voltage has exceeded the threshold voltage in the midpoint potential direction, in the period when the synchronous rectifier transistor is to be on. 
     Alternatively, the control circuit may switch, to the predetermined voltage, the alternating current voltage to be applied to the comparison input terminal of the comparator, and may perform control such that the thus-switched state can be maintained until immediately before the period in which the synchronous rectifier transistor is to be on, when the comparator judges that the alternating current voltage has exceeded the threshold voltage in the midpoint potential direction. 
     In addition, the comparator may compare the voltages of first and second input terminals, thereby outputting a reverse current detection signal indicating the comparison result. Moreover, the control circuit may further include a voltage generation circuit, a switching circuit and a logical circuit. The voltage generation circuit generates a first comparison voltage based on the alternating current voltage, and a second comparison voltage corresponding to the second potential, the second comparison voltage being the predetermined voltage, and also generates a threshold voltage corresponding to the second potential thereby applying the threshold voltage to the second comparison input terminal. The switching circuit which selects one of the first and second comparison voltages, and which then applies the selected voltage to the first comparison input terminal. The logical circuit outputs, to the gate of the synchronous rectifier transistor and the switching circuit, a switching signal for controlling the synchronous rectifier transistor. The synchronous rectifier transistor is turned on in response to a control signal indicating a period in which the synchronous rectifier transistor is to be on, and is turned off in response to the reverse current detection signal. 
     Furthermore, the voltage generation circuit may include a first resistance element, a first MOS transistor, a second MOS transistor, a third MOS transistor, and a current source circuit. The first MOS transistor applies the second potential to its drain, is connected to a first switching terminal of the switching circuit at its source through the first resistance element, and applies the alternating current voltage to its gate. The second MOS transistor applies the second potential to its drain and gate, and is connected to a second switching terminal of the switching circuit at its source. The third MOS transistor applies the second potential to its drain and the gate, and is connected to the second comparison input terminal of the comparator at its source. The current source circuit supplies current to the source of the first MOS transistor through the first resistance element, and also supplies current to the source of each of the second and third MOS transistors. Here, the current source circuit may supply each of the first and third MOS transistors with current larger than that to be supplied to the second MOS transistor, and may supply the first and third MOS transistors respectively with currents of the same amount. 
     Furthermore, the current source circuit may be constituted of first, second and third current mirror circuits, the first current mirror circuit using a second resistance element as a load. Here, the first, second and third current mirror circuits may supply current to the first, second and third MOS transistors, respectively. 
     Hereinbelow, this embodiment will be described in detail on the basis of examples with reference to the drawings. 
     Example 1 
       FIG. 1  is a block diagram showing a configuration of a switching regulator according to a first example of the present invention. In  FIG. 1 , the switching regulator includes a switching transistor (main power transistor) P 1 , a synchronous rectifier transistor (rectifier power transistor) N 1 , a reverse current prevention circuit  10   a , an inductor L, and a capacitor C. The switching regulator steps down the voltage from a power source VDD to apply resultant voltage to a load Z. 
     The switching transistor P 1  is connected to the power source VDD at its source, and is connected to one end of the inductor L at its drain. Moreover, the gate of the switching transistor P 1  is provided with a pulse-width or pulse-density modulated control signal CNT 1  for controlling output voltage to the load Z. 
     The synchronous rectifier transistor N 1  is connected to ground at its source, and is connected to the one end of the inductor L at its drain. Moreover, the reverse current prevention circuit  10   a  is connected to the gate of the synchronous rectifier transistor N 1 . The reverse current prevention circuit  10   a  detects reverse current in the inductor L, and then performs control to turn on or off the synchronous rectifier transistor N  1 . 
     The switching transistor P 1  and the synchronous rectifier transistor N 1  convert the voltage from the power source VDD to the voltage of an alternating current signal Sa. The alternating current signal Sa is smoothed by the inductor L and the capacitor C, and is then provided, as direct current voltage, to the load Z connected to an output terminal OUT. 
     The reverse current prevention circuit  10   a  includes a reverse current detection unit  12   a , a flip-flop circuit FF, and a 2 input AND circuit AND. The reverse current detection unit  12   a  receives inputs of the alternating current signal Sa and a control signal S 0  for the gate of the synchronous rectifier transistor N 1 , and then outputs a reverse current detection signal S 1  to a clock input terminal CLK of the flip-flop circuit FF. In the flip-flop circuit FF, a data input terminal DATA is connected to a power source VDD, a reset terminal RESETB receives an input of a control signal CNT 2  synchronized with the control signal CTN 1 , and an output terminal QB is connected to one of the input terminals of the 2 input AND circuit AND. The 2 input AND circuit AND receives an input of the control signal CNT 2  at the other input terminal, and then outputs the control signal S 0  from an output terminal to the gate of the synchronous rectifier transistor N 1  and the reverse current detection unit  12   a.    
     Next, the reverse current detection unit  12   a  will be described in detail.  FIG. 2  is a circuit diagram showing an example of the reverse current detection unit  12   a . The reverse current detection unit  12   a  includes a comparator CMP, a voltage generation circuit  14   a , and a switching circuit  16   a.    
     The voltage generation circuit  14   a  includes Pch transistors M 1  to M 7 , and resistance elements R 1  and R 2 . In the voltage generation circuit  14   a , the sizes (W/L) of the Pch transistors M 1 , M 3  to M 5 , and M 7  are identical, while the size (2W/L) of each of the Pch transistors M 2  and M 6  is twice as large as that of the Pch transistors M 1 , M 3  to M 5 , and M 7 . 
     The Pch transistor M 1  is connected to the power source VDD at its source, and to ground at its diode-connected drain through the resistance element R 1 . The Pch transistor M 2  forms a current mirror circuit together with the Pch transistor M 1 , and is connected to ground at its drain through the resistance element R 2  and the Pch transistor M 3 . The Pch transistor M 4  forms a current mirror circuit together with the Pch transistor M 1 , and is connected to ground at its drain through the Pch transistor M 5 . The Pch transistor M 6  forms a current mirror circuit together with the Pch transistor M 1 , and is connected to ground at its drain through the Pch transistor M 7 . 
     The Pch transistor M 3  is connected to one end of the resistance element R 2  at its source, and to ground at its drain, and its gate is provided with the alternating current signal Sa. The other end of the resistance element R 2  is connected to the drain of the Pch transistor M 2 . The Pch transistors M 5  and M 7  are connected to ground at their gates and drains, and are connected to the drains of the Pch transistors M 4  and M 6  respectively at their sources. 
     In the voltage generation circuit  14   a  having the above-described configuration, the Pch transistors M 2 , M 4  and M 6  function as current source circuits that supply current to the Pch transistors M 3 , M 5  and M 7 , respectively. The current source circuits supply each of the Pch transistors M 3  and M 7  with current larger than (for example, twice as large as) that for the Pch transistor M 5 , and the currents supplied to the Pch transistors M 3  and M 7  are equal in amount. 
     The switching circuit  16   a  includes Nch transistors M 8  and M 10 , Pch transistors M 9  and M 11 , and an inverter circuit INV. The Nch transistor M 8  and the Pch transistor M 9  form a transfer gate, and are turned on when the control signal S 0  is in high level, so that a signal Sb from the drain of the Pch transistor M 2  is provided to a non-inverting (+) terminal of the comparator CMP. Moreover, the Nch transistor M 10  and the Pch transistor M 11  form a transfer gate, and are turned on when the control signal S 0  is in low level, so that a signal Sc from the drain of the Pch transistor M 4  is provided to a non-inverting (+) terminal of the comparator CMP. Furthermore, the drain of the Pch transistor M 6  is constantly connected to an inverting (−) terminal of the comparator CMP. Thereby, the reverse current detection signal S 1  is outputted from an output terminal of the comparator CMP. 
       FIG. 3  is a circuit diagram showing an example of the comparator CMP. The comparator CMP includes Pch transistors M 13 , M 15 , M 17 , M 20  and M 22 , Nch transistors M 12 , M 14 , M 16 , M 18 , M 19 , M 21  and M 23 , and a resistance element R 3 . The Nch transistors M 16  and M 18  are connected respectively to the non-inverting (+) terminal and the inverting (−) terminal at their gates, and form a differential pair in the input stage. The diode-connected Nch transistor M 12  is connected to the power supply VDD at its drain through the resistance element R 3 , and forms a current mirror circuit together with the Nch transistor M 19 . The Nch transistor M 19  functions as a current source of the Nch transistors M 16  and M 18 , which are the differential pair. 
     The Pch transistor M 15 , which forms a current mirror circuit together with the Pch transistor M 13 , is connected, as a load, to the drain of the Nch transistor M 16 . The Pch transistor M 17 , which forms a current mirror circuit together with the Pch transistor M 20 , is connected, as a load, to the drain of the Nch transistor M 18 . The Nch transistor M 14 , which forms a current mirror circuit together with the Nch transistor M 21 , is connected, as a load, to the drain of the Pch transistor M 13 . The Pch transistor M 20  and the Nch transistor M 21  form an inverting amplifier, and its output terminal outputs the reverse current detection signal S 1  through the Pch transistor M 22  and the Nch transistor M 23 , which form an inverting amplifier. 
     The comparator CMP having the above-described configuration compares a voltage of a signal CP+ from the non-inverting (+) terminal (a first comparison input terminal) and a voltage of a signal CP− from the inverting (−) terminal (a second comparison input terminal), and then outputs the reverse current detection signal S 1  indicating the comparison result. 
     The reverse current prevention circuit  10   a  having the above-described configuration includes the comparator CMP that compares the alternating current voltage Sa with a threshold voltage, in a period when the rectifier power transistor N 1  is to be on. Thereby, the reverse current prevention circuit  10   a  operates as follows. First, the reverse current prevention circuit  10   a  applies, to the comparison input terminal of the comparator CMP, a predetermined voltage instead of the alternating current voltage Sa, at least immediately before the period in which the rectifier power transistor N 1  is to be on. Note that the predetermined voltage applied here is lower than the threshold voltage. Then, when the comparator CMP judges that the alternating current voltage Sa has exceeded the threshold voltage, in the period when the rectifier power transistor N 1  is to be on, the reverse current prevention circuit  10   a  performs control such that the rectifier power transistor N 1  can be turned off. 
     Furthermore, when the comparator CMP judges that the voltage of the alternating current signal Sa has increased (in the direction toward the midpoint potential) to exceed the threshold voltage, the reverse current prevention circuit  10   a  may operate as follows. Specifically, the reverse current prevention circuit  10   a  may switch, to the predetermined voltage, the alternating current voltage Sa to be applied to the comparison input terminal of the comparator CMP, and may perform control such that the thus-switched state can be maintained until immediately before the period in which the synchronous rectifier transistor N 1  is to be on. 
     The voltage generation circuit  14   a  generates a first comparison voltage (signal Sb) based on the voltage of the alternating current signal Sa, and a second comparison voltage (signal Sc) corresponding to the second potential, and also generates a third comparison voltage (signal CP−) corresponding to the second potential, thereby applying the third comparison voltage to the second comparison input terminal (−terminal of the comparator CMP). The switching circuit  16   a  selects one of the first and second comparison voltages, and then applies the selected comparison voltage to the first comparison input terminal (+ terminal of the comparator CMP). 
     The logical circuit, includes the flip-flop circuit FF and the 2 input AND circuit AND, outputs the control signal S 0  (a switching signal) to the gate of the synchronous rectifier transistor N 1  and the switching circuit  16   a . The synchronous rectifier transistor N 1  is turned on in response to the control signal CNT 2  indicating a period in which the synchronous rectifier transistor N  1  is to be on, and is turned off in response to the reverse current detection signal S 1 . 
     Next, operation of each of the units of the switching regulator will be described.  FIG. 4  is a timing chart showing waveforms of the units of the switching regulator according to the first example. 
     Before Time t 0 , the control signal CNT 1  is in low level, and thus the switching transistor P 1  is in the ON state. Accordingly, power is supplied from the power source VDD to the load Z through the switching transistor P 1  in the ON state. 
     At Time t 0 , the control signal CNT 1  rises to turn off the switching transistor P 1 , thereby stopping the power supply from the power supply VDD to the load Z. As a result, the voltage of the alternating current signal Sa decreases rapidly. 
     At Time t 1 , with a small time lag after Time t 0 , the control signal CNT 2  rises to set, to high level, the control signal S 0 , which is an output from the 2 input AND circuit AND. Consequently, the synchronous rectifier transistor N 1  is turned on, and hence, current flows from ground to the inductor L. In addition, the voltage of the alternating current signal Sa falls below a detection level which is lower than the GND (ground) level. Moreover, the Nch transistor M 8  and the Pch transistor M 9 , which form a transfer gate, are turned on, so that the signal Sb from the drain of the Pch transistor M 2  is provided to the non-inverting (+) terminal of the comparator CMP. Incidentally, the short time lags between Time t 0  and Time t 1  as well as between Time t 4  and Time t 5  are provided for preventing the switching transistor P 1  and the synchronous rectifier transistor N 1  from being in an ON state at the same time. 
     After Time t 1 , the current flowing through the inductor L is consumed by the load Z, and hence, the current value decreases. Accordingly, the voltage of the alternating signal Sa increases toward the GND (ground) level. Then, at Time t 2 , the voltage of the alternating current signal Sa exceeds the detection level. Specifically, in the comparator CMP, the voltage of a comparator + side signal CP+ (here, the signal Sb) exceeds the voltage of a comparator + side signal CP−. The comparator + side signal CP+ is obtained by adding, to the voltage of the alternating current signal Sa, the voltage equivalent to the amount of voltage drop in the Pch transistor M 3  and the resistance element R 2 , and the comparator + side signal CP− is obtained by adding, to the GND level, the voltage equivalent to the amount of voltage drop in the Pch transistor M 7 . 
     As mentioned above as a problem, in the comparator CMP, there is a detection delay in outputting a comparison result. Accordingly, the comparator CMP switches the level of the reverse current detection signal S 1  to high level at Time t 3 , with a detection delay Td after Time t 2 . When the reverse current detection signal S 1  becomes high level, a clock input terminal CLK of the flip-flop circuit also becomes high level. Since the clock input terminal CLK becomes high level, the flip-flop circuit FF, which is connected to the power supply VDD at its data input terminal DATA (i.e. the data input terminal DATA is in high level) switches the output terminal QB to low level. Consequently, the control signal S 0  becomes low level. As a result, the synchronous rectifier transistor N 1  is turned off to stop the current flowing into the inductor L. In sum, even in a case where the comparator CMP involves the detection delay Td, the synchronous rectifier transistor N 1  can be turned off before the voltage of the alternating current signal Sa exceeds the GND level, by setting the detection level at a level lower than the GND level by a predetermined amount. Thereby, it is possible to prevent reverse current from flowing into the synchronous rectifier transistor N 1 . 
     At Time t 3 , the control signal S 0  becomes low level, and consequently, the Nch transistor M 10  and the Pch transistor M 11 , which form a transfer gate, are turned on. Accordingly, the signal Sc from the source of the Pch transistor M 5  is provided to the non-inverting (+) terminal of the comparator CMP. Since the voltage of the comparator + side signal CP+ (here, here the signal Sc) falls below the voltage of the comparator + side signal CP− by a certain value, the comparator CMP switches the level of the reverse current detection signal S 1  to low level. 
     In the time period from this point to Time t 1 , the voltage of the comparator +side signal CP+ (here, the signal Sc) continues to be a voltage lower than the voltage of the comparator + side signal CP− by the certain value, and hence, the comparator CMP stably keeps the reverse current detection signal S 1  at low level. 
     After Time t 3  until Time t 5  when the control signal CNT 1  falls and the switching transistor P 1  is turned on, the switching transistor P 1  and the synchronous rectifier transistor N 1  are in a OFF state. Accordingly, the alternating current signal Sa has an oscillatory waveform that is generated by a resonant circuit comprised of stray capacitance, the inductor L and the like. The comparator CMP stably keeps the reverse current detection signal S 1  at low level, and hence, the level of the reverse current detection signal S 1  is not affected even though the alternating current signal Sa has an oscillatory waveform. 
     At Time t 4 , the control signal CNT 2  falls, and the flip-flop circuit FF switches the level of the output terminal QB to high level. 
     In the above-described timing chart, a time period T 0  from Time t 1  to Time t 4  corresponds to the period in which the synchronous rectifier transistor (rectifier power transistor) N 1  is to be on. Moreover, a time period T 1  from Time t 1  to Time t 3  corresponds to the time in which the synchronous rectifier transistor (rectifier power transistor) N 1  is on, while a time period T 2  from Time t 3  to Time t 1  corresponds to the period in which the synchronous rectifier transistor (rectifier power transistor) N is off. 
     In the switching regulator that performs the above-described operations, the comparator − side signal CP− is constantly inputted into the inverting (−) terminal of the comparator CMP. The comparator − side signal CP− has a voltage with a level shifted from the GND level by the Pch transistor M 7  forming a source follower. Moreover, the signal Sb is inputted into the non-inverting (+) terminal of the comparator CMP in the time period T 1 . The signal Sb has a voltage with a level shifted from the alternating current signal Sa by the resistance element R 2  and the Pch transistor M 3  forming a source follower. Here, the voltage generated by both constant current from the Pch transistor M 2 , which is a current source, and the resistance element R 2  is to be a voltage that is enough to compensate for detection delay of the comparator CMP, and a concrete example of such voltage can be the voltage of approximately 10 mV. In the case where the voltage generated by the constant current and the resistance element R 2  is 10 mV, the voltage of the alternating signal Sa results in being equal to the GND level when the voltage is set lower than the GND level by 10 mV. Accordingly, the detection level is to be potential corresponding to −10 mV. 
     When the voltage of the alternating current signal Sa becomes higher than −10 mV, which is the detection level, in the time period T 0  when the control signal CNT 2  is in high level, the reverse current detection signal S 1  becomes high level with detection delay Td, and the output terminal QB becomes in low level. Thereby, the synchronous transistor N 1  is turned off. 
     In the time period T 2  when the synchronous transistor N 1  is off, the switching circuit  16   a  inputs the signal Sc, which is to be reference voltage, into the non-inverting (+) terminal of the comparator CMP. Here, the reference voltage is set at voltage which is lower than the detection voltage (−10 mV), and which can certainly set the output from the comparator CMP to be in low level. A concrete example of such voltage is approximately −50 mV. In the time period T 2 , the voltage of the non-inverting (+) terminal of the comparator CMP is lower than the voltage of the inverting (−) terminal (reference voltage −50 mV&lt;detection voltage −10 mV), and the output of the comparator CMP is certainly reset to be in low level. 
     With the switching regulator that performs the above-described operations, the synchronous rectifier transistor N 1  can certainly be turned off even in a case where the comparator CMP has a dead zone width making the comparator CMP unable to perform comparison operation with high accuracy under light load conditions. Hence, efficiency in power conversion under light load conditions can be improved. 
     Moreover, the voltages with levels respectively shifted by the Pch transistors M 3 , M 5  and M 7 , each of which has a source follower configuration, are inputted into the comparator CMP. With such a circuit configuration, an Nch transistor can be used for a differential pair in the input stage of the comparator CMP even when the voltage of the alternating current signal Sa that is the target of monitoring is extremely small, near 0V. The comparator CMP using an Nch transistor for the differential pair in the input stage is generally capable of carrying out comparison judgment at high speed. 
     Furthermore, voltage for compensating for the detection delay in the comparator CMP is generated on the basis of output current of the Pch transistor M 2  and the resistance value of the resistance element R 2 . Accordingly, detection voltage can be generated with high accuracy. In addition, by employing the same material for the resistance element R 2  and the resistance element R 1 , which is provided to generate current, in the current source circuits, voltage drifts due to the temperature characteristic of the resistance values can be canceled out, and hence, accuracy in detecting voltage can be improved against temperature fluctuation. 
     Reference voltage used for resetting the reverse current signal S 1 , which is the output of the comparator CMP, to low level can be set appropriately by choosing a current value of the output current of each current source circuit and the size of each Pch transistor having a source follower configuration. Moreover, the reference voltage is determined relative to the voltage that reaches a detection level. Accordingly, reference voltage that is capable of accurately resetting the reverse current detection signal S 1  to low level, and that does not depend on the absolute accuracy of an element, can be generated. 
     In addition, in the time period T 2 , when the load current is extremely small, the alternating current signal Sa has an oscillatory waveform that is generated by a resonant circuit comprised of stray capacitance, the inductor L and the like. Moreover, the alternating current signal Sa is also set at high level by the switching transistor P 1  in an ON state. In the time period T 2 , the comparator CMP stably outputs the reverse current detection signal S 1  in low level. This demonstrates that the comparison operation is not affected even when the alternating current signal Sa varies a great deal in the level. 
     Example 2 
       FIG. 5  is a block diagram showing a configuration of a switching regulator according to a second example of the present invention. In  FIG. 5 , the same symbols as those used in  FIG. 1  are used for denoting the same constituents. The switching regulator in  FIG. 5  includes a switching transistor (main power transistor) N 2 , a synchronous rectifier transistor (rectifier power transistor) P 2 , a reverse current prevention circuit  10   b , a diode D, the inductor L, and the capacitor C. The switching regulator steps up the voltage from the power source VDD to apply the resultant voltage to the load Z connected to the output terminal OUT. 
     The switching transistor N 2  is connected to ground at its source, and to one end of the inductor L at its drain, and the gate of the switching transistor N 2  is provided with a pulse-width or pulse-density modulated control signal CNT 1   a  for controlling output voltage to the load Z. 
     The synchronous rectifier transistor P 2  is connected, at its source, to the output terminal OUT, the cathode of the diode D, one end of the capacitor C, and one end of the load Z, and is connected, at its drain, to the one end of the inductor L and the anode of the diode D. Moreover, the synchronous rectifier transistor P 2  is connected, at its gate, to the reverse current prevention circuit  10   b , which performs control, by detecting reverse current in the inductor L, to turn on or off the synchronous rectifier transistor P 2 . 
     The other end of the inductor L is connected to the power supply VDD, and the other ends of the capacitor C and the load Z are connected to ground. 
     The switching transistor N 2  and the synchronous rectifier transistor P 2  convert the voltage from the power supply VDD to the voltage of the voltage of an alternating current signal Sd. The alternating current signal Sd is smoothed by the inductor L and the capacitor C, and is then provided, as direct current voltage, to the load Z. 
     The reverse current prevention circuit  10   b  includes a reverse current detection unit  12   b , the flip-flop circuit FF, a 2-input NAND circuit NAND. The reverse current detection unit  12   b  receives, as inputs, the alternating current signal Sd and a control signal S 0   a  for the gate of the synchronous rectifier transistor P 2 , and then outputs the reverse current detection signal S 1  to the clock input terminal CLK of the flip-flop circuit FF. In the flip-flop circuit FF, the data input terminal DATA is connected to the power supply VDD, the reset terminal RESETB receives an input of the control CNT 2  synchronized with the control signal CNT 1   a , and the output terminal QB is connected to one of the input terminals of the 2-input NAND circuit NAND. The 2-input AND circuit NAND receives an input of the control signal CNT 2  at the other input terminal, and then outputs the control signal S 0   a  from the output terminal to the gate of the synchronous rectifier transistor P 2  and the reverse current detection unit  12   b.    
     Next, the reverse current detection unit  12   b  will be described in detail.  FIG. 6  is a circuit diagram showing an example of the reverse current detection unit  12   b . The reverse current detection unit  12   b  includes the comparator CMP, a voltage generation circuit  14   b , and the switching circuit  16   b.    
     The voltage generation circuit  14   b  includes Nch transistors M 31  to M 37 , and resistance elements R 4  and R 5 . In the voltage generation circuit  14   b , the sizes (W/L) of the Nch transistors M 31 , M 33  to M 35 , and M 37  are identical, while the size (2W/L) of each of the Nch transistors M 32  and M 36  is twice as large as that of the Nch transistors M 31 , M 33  to M 35 , and M 37 . 
     The Nch transistor M 31  is connected to ground at its source, and to the power source VDD at its diode-connected drain through the resistance element R 4 . The Nch transistor M 32  forms a current mirror circuit together with the Nch transistor M 31 , and is connected to the power supply VDD at its drain through the resistance element R 5  and the Nch transistor M 33 . The Nch transistor M 34  forms a current mirror circuit together with the Nch transistor M 31 , and is connected to the power supply VDD at its drain through the Nch transistor M 35 . The Nch transistor M 36  forms a current mirror circuit together with the Nch transistor M 31 , and is connected to the power supply VDD at its drain through the Nch transistor M 37 . 
     The Nch transistor M 33  is connected to one end of the resistance element R 5  at its source, and to the power supply VDD at its drain. The gate of the Nch transistor M 33  is provided with the alternating current signal Sd. The Nch transistors M 35  and M 37  are connected to the power supply VDD at their gates and drains, and to the drains of the M 35  and M 37  respectively at their sources. 
     The switching circuit  16   b  includes Nch transistors M 39  and M 41 , Pch transistors M 38  and M 40 , and the inverter circuit INV. The Pch transistor M 38  and the Nch transistor M 39  form a transfer gate, and are turned on, when the control signal S 0   a  is low level, to provide a signal Se from the drain of the Nch transistor M 32  to the inverting (−) terminal of the comparator CMP. The Pch transistor M 40  and the Nch transistor M 41  form a transfer gate, and are turned on, when the control signal S 0   a  is high level, to provide a signal Sf from the drain of the Nch transistor M 34  to the inverting (−) terminal of the comparator CMP. The Nch transistor M 36  is connected to the non-inverting (+) terminal of the comparator CMP at its drain. The reverse current detection signal S 1  is outputted from the output terminal of the comparator CMP. 
     The reverse current prevention circuit  10   b  having the above-described configuration includes the comparator CMP that compares the alternating voltage Sd with a threshold voltage, in a period when the rectifier power transistor P 2  is to be on. Thereby, the reverse current prevention circuit  10   b  operates as follows. First, the reverse current prevention circuit  10   b  applies, to the comparison input terminal of the comparator CMP, a predetermined voltage instead of the alternating current voltage Sd, at least immediately before the period in which the rectifier power transistor P 2  is to be on. Note that the predetermined voltage applied here is higher than the threshold voltage. Then, when the comparator CMP judges that the alternating current voltage Sd has fallen below the threshold voltage, in a period when the rectifier power transistor P 2  is on, the reverse current prevention circuit  10   b  performs control such that the rectifier power transistor P 2  can be turned off. 
     Furthermore, when the comparator CMP judges that the voltage of the alternating current signal Sd has decreased (in the direction toward the midpoint potential) to fall below the threshold value, the reverse current prevention circuit  10   b  may operate as follows. Specifically, the reverse current prevention circuit  10   b  may switch, to a predetermined voltage, the alternating current voltage Sb to be applied to the comparison input terminal of the comparator CMP, and may perform control such that the thus-switched state can be maintained until immediately before a period in which the synchronous rectifier transistor P 2  is to be on. 
     Next, operation of each of the units of the switching regulator will be described.  FIG. 7  is a timing chart showing waveforms of the units of the switching regulator according to the second example. The followings are characteristics in  FIG. 7  that are different from those in  FIG. 4 . 
     (1) The alternating current signal Sd has a waveform that is the inversion of the waveform of the alternating current signal Sa. Moreover, the detection level is set higher than the OUT level in the comparator CMP. 
     (2) The control signal CNT 1   a  has a logical level that is the inversion of the control CNT 1 . 
     (3) The control signal S 0   a  has a logical level that is the inversion of the control signal S 0 . 
     (4) The signal Se has a waveform that is the inversion of the waveform of the signal Sb. 
     (5) The signal Sf is set slightly lower than the potential level of the power supply VDD. 
     (6) The comparator CMP detects that the comparator − side signal CP− (the signal Se, here) has fallen below the comparator + side signal CP+, in the time period T 1 . Moreover, the comparator − side signal CP− (the signal Sf, here) is fixed at a level higher than that of the comparator − side CP+. 
     Since the switching regulator according to the second example is a step-up type, some of the signal levels of the switching regulator are different from the corresponding signal levels of the switching regulator according to the first example. However, the fundamental operations are same as those of the first example, and the same effects as those of the first example are brought about. 
     It should be noted that the disclosure of the above-mentioned patent documents are included in this specification by reference. Changes and adjustments can be made to the embodiment and the examples within the entire disclosure (including the scope of claims) of the present invention on the basis of the fundamental technical ideas. Moreover, a wide variety of combinations of, and selections from, the various disclosed components are possible within the scope of the present invention. In other words, it is obvious that the present invention includes various changes and modifications possible to be made by those skilled in the art on the basis of the entire disclosure including the scope of the claims and the technical ideas. 
     Further, it is noted that, Applicant&#39;s intent is to encompass equivalents of all claim elements, even if amended later during prosecution.