Patent Publication Number: US-8543884-B2

Title: Communications channel parallel interleaver and de-interleaver

Description:
BACKGROUND 
     1. Field 
     The present invention relates generally to digital communications systems, and more specifically to a method and hardware architecture for parallel channel interleaving and de-interleaving. 
     2. Background 
     Digital communication systems use numerous techniques to increase the amount of information transferred while minimizing transmission errors. In these communication systems, the information is typically represented as a sequence of binary bits or blocks of bits called frames. The binary information is modulated to signal waveforms and transmitted over a communication channel. Communication channels tend to introduce noise and interference that corrupt the transmitted signal. At a receiver, the received information may be corrupted and is an estimate of the transmitted binary information. The number of bit errors or frame errors depends on the amount of noise and interference in the communication channel. 
     To counter the effects of transmission channel corruption, channel interleaving error correction coding is often used in digital communication systems to protect the digital information from noise and interference and reduce the number of bit/frame errors. Channel interleaving is employed in most modern wireless communications systems to protect against burst errors. A channel interleaver reshuffles encoded symbols in such a way that consecutive symbols are spread apart from each other as far as possible in order to break the temporal correlation between successive symbols involved in a burst of errors. A reverse de-interleaving operation is performed at the receiver side before feeding the symbols to a channel decoder. Typically, this interleaving, and subsequent de-interleaving are performed in an inefficient serial manner. 
     There is therefore a need in the art for a faster and more efficient parallel method of interleaving and de-interleaving having improved performance. Moreover, there is a need for the improved parallel interleaving and de-interleaving to have an easily implemented hardware architecture that can be constructed using basic logic gates with a short critical path delay. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  shows an exemplary high level parallel interleaver coding and interleaving structure; 
         FIG. 2(   a ) is a block diagram of an exemplary convolutional encoder that can be used for parallel interleaving; 
         FIG. 2(   b ) is a block diagram of a parallel interleaver for convolutionally encoded sub-packets; 
         FIG. 3(   a ) is a block diagram of an exemplary turbo encoder that can be used for parallel interleaving; 
         FIG. 3(   b ) is a block diagram of a parallel interleaver for turbo encoded sub-packets; 
         FIG. 4  shows the puncturing patterns for rate-1/5, 1/3, 1/2, and 2/3 turbo code; 
         FIG. 5  shows an exemplary top-level architecture of a deinterleaver/decoder block that can be used for parallel deinterleaving; 
         FIG. 6(   a ) shows a block diagram of an exemplary convolutional channel deinterleaver datapath; 
         FIG. 6(   b ) details exemplary functionality of the PBRI block illustrated in  FIG. 6(   a ); 
         FIG. 7  shows a block diagram of an exemplary turbo channel deinterleaver datapath; 
         FIG. 8(   a ) further details exemplary operations of the turbo codeword splitter and the PBRI blocks; and 
         FIG. 8(   b ) details exemplary deinterleaved/depunctured rate-1/5 and rate-1/3 turbo packet structures. 
     
    
    
     DETAILED DESCRIPTION 
     The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments. 
     The word “packet” is used herein to mean formatted unit of data. The word “subpacket” is used herein to mean a portion of a packet. The words “packet” and “subpacket” may be used interchangeably herein. 
       FIG. 1  shows an exemplary parallel interleaver coding and interleaving structure  100 . Packet Splitter  102  applies packet splitting to incoming data channel packets (as well as forward broadcast and multicast services channels), where a packet is divided into one or more smaller subpackets of maximum length defined by a constant in the physical (PHY) layer protocol. Subpackets can be configured to have bit-lengths ranging from 32 to 16,384 in multiples of 8. A sequence of operations consisting of Cyclic Redundancy Check (CRC) insertion performed by CRC inserter  104 , convolutional or turbo encoding performed by encoder  106  detailed in  FIG. 2(   a ) and  3 ( a ), channel interleaving performed by channel interleaver  108 , sequence repetition performed by sequence repeater  110 , and data scrambling performed by data scrambler  112 , is performed independently on each subpacket (−Subpacket  0  . . . Subpacket NSUBPKT-1 ). Multiplexing and symbol modulation mapping is performed by Multiplexer 114 to produce output modulation symbols. Other non-data channel packets are not subject to subpacketization, and the sequence of aforementioned operations is applied on the complete packet. The terms “packet” and “subpacket” may be used interchangeably herein. At a receiver, a packet is declared in error if any of its constituent subpackets are in error. 
     CRC bits are appended by CRC inserter  104  to the incoming information bits of a subpacket for the purpose of error detection at a receiver. The CRC bits are generated by clocking a 24-stage shift-register with a generator function. In one embodiment, the generator function is 0x1864CFB. The shift-register is initialized to logic one, and then clocked a number of times equal to the number of input bits in the subpacket. Next, the register is clocked an additional number of times equal to the number of CRC bits to be generated (≦24) with the input disconnected. These output bits generated from the shift-register constitute the CRC bits and are appended to the incoming information bits in the order they are generated. For data channel packets, the number of CRC bits is 24. For other channels some of the CRC bits may be truncated. 
     Forward Error Correction 
       FIG. 2(   a ) is a block diagram of an exemplary embodiment of the encoder  106  component of the parallel interleaver coding and interleaving structure  100 , for performing convolutional encoding. A rate-1/3 convolutional code is used to encode CRC-padded control channel subpackets as well as CRC-padded data channel packets of length (N v ) 128 bits or less. The constraint length of the rate-1/3 code is nine for generator functions g 0    106   a , g 1    106   b , and g 2    106   c . In one exemplary embodiment, the generator functions are g 0 =557 (8) , g 1 =663 (8)  and g 2 =711 (8)  for memory elements D 1 , D 2  D 3 , D 4 , D 5 , D 6 , D 7  and D 8 . The input bits to the encoder consist of the CRC-padded subpacket appended with eight all-zero tail bits to reset the encoder state when encoding of a packet is complete. The length of an encoded packet in this exemplary embodiment is 3(N v +8). 
       FIG. 3(   a ) is a block diagram of another embodiment of encoder  106  for a rate-1/5 turbo code encoder used to encode CRC-padded data channel subpackets of length 128 bits or more. The constituent codes of the turbo code are two ( 302  and  304 ) rate-1/3, contraint-length-4, systematic, recursive convolutional encoders with identical transfer functions of G(D)=[1 n 0 (D)/d(D) n 1 (D)/d(D)], where d(D)=1+D 2 +D 3 , n 0 (D)=1+D+D 3 , and n 1 (D)=1+D+D 2 +D 3 . 
     The turbo encoder  106  generates 5N T +18 encoded output bits, where N T  is the number of encoder input bits. The first 5N T  output bits are the encoder output data bits, which are generated by clocking the constituent encoders ( 302  and  304 ) once for every input bit with the switches in the upwards position, and puncturing out the systematic output bits X′ from the second constituent encoder  304  with symbol puncturing component  306 . The sequence of constituent encoder ( 302  and  304 ) output bits for each input bit is XY 0 Y 1 Y′ 0 Y′ 1 . The last 18 tail bits are generated after the constituent encoder ( 302  and  304 ) has been clocked for N T  cycles with the switches held in the upwards position. The first 9 tail bits are generated by clocking the first constituent encoder  302  three times with the switch held in the downwards position, with the sequence of output bits being XY 0 Y 1 . The last nine tail bits are generated by clocking the second constituent encoder  304  three times with the switch held in the downwards position while constituent encoder  1   302  is not clocked. The sequence of output bits from constituent encoder  2   304  in this case is X′Y′ 0 Y′ 1 . The 18 tail bits ensure that both constituent encoders ( 302  and  304 ) are reset to the all-zero state after encoding a subpacket. 
     The exemplary turbo channel interleaver  308  is based on Linear Congruential Sequences (LCS). It interleaves subpackets of length between 128 bits and 16,384 bits, but can be applied to any arbitrary length. The sequence of interleaver output addresses generated by an LCS turbo interleaver  308  is equivalent to the sequence obtained by the following process. A 2D R×C array is filled with a sequence of linear addresses row by row from top to bottom, the entries of the array are shuffled according to a procedure to be described next, and the resulting shuffled entries are read column by column from left to right. The shuffling of the array entries is based on applying an independent permutation to the column entries in every row, and then permuting the order of the rows. First, a small positive integer r is chosen depending on the memory bank architecture of the interleaver. In one embodiment, r is set to 5 so that the interleaver memory is composed of 32 banks. 
     Next, the smallest positive integer n such that N T ≦2 r+n  is determined. This is equivalent to finding the smallest sized 2 r ×2 n  array that can hold the N T  entries. The 2 n  entries of each row are interleaved independently using a linear congruential sequence recursion whose parameters are determined using a 2D look-up table (LUT) based on the row index and n. The result of this operation is a set of new interleaved column indices. Next, the 2 r  rows are shuffled in bit-reversed order. The result of this operation is a set of new interleaved row indices. 
     Finally, the interleaved addresses are formed by concatenating the corresponding interleaved column and row indices in opposite order with respect to their order in the linear address. The last step is equivalent to reading the interleaved array entries in the opposite order (i.e., column by column) to which it was filled in (i.e., row by row). If the resulting interleaved address is greater than or equal to N T   1 , then it is pruned away and the same operations are repeated on the next consecutive address in linear order. 
     Let x be an (r+n)-bit linear address, and y=ρ r,n (x) be the corresponding (r+n)-bit turbo-interleaved address. Then, ρ r,n (x) is given by: 
     
       
         
           
             
               
                 
                   
                     
                       
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     With π being indicative of an interleaver, π r  is the r-bit reversal function and the LUT is a 2D look-up table that stores the moduli of the 2 r  LCS recursions for n=2, 3, . . . , 9. 
     Channel Interleaving 
     Channel interleaving is applied to encoded subpackets by channel interleaver  108  as shown in  FIG. 1 , and consists of a bit-demultiplexing operation followed by a bit-permuting operation.  FIG. 2(   b ) is a block diagram of a parallel interleaver  108  for convolutionally encoded sub-packets, while  FIG. 3(   b ) is a block diagram of a parallel interleaver  108  for turbo encoded sub-packets. 
     Referring to  FIG. 2(   b ) for convolutionally encoded subpackets, the encoder output bits are demultiplexed into three sequences V 0 , V 1 , V 2 , by demultiplexer  220  with the first bit going to V 0 , the second bit going to V 1 , the third going to V 2 , and the fourth to V 0 , etc. Next, each of the three sequences is bit-permuted independently using pruned bit-reversal interleavers (PBRIs) ( 222   a - 222   c ) to generate the sequences π(V 0 ), π(V 1 ), π(V 2 ). A bit-reversal interleaver maps an n-bit number x into another n-bit number y according to a simple bit-reversal rule such that the bits of y appear in the reverse order with respect to x. A bit-reversal mapping on n bits is designated by the function y=π n (x). The values taken by x and y range from 0 to 2 n −1, where M=2 n  is the size of the interleaver. A pruned bit-reversal interleaver maps an n-bit number x less than the (sub)packet length N, where N≦M, into another n-bit number y less than N according to the bit-reversal rule. The size of the pruned interleaver is N, while the size of mother interleaver is M. The numbers from N to M−1 are pruned out of the interleaver mappings and are not considered valid mappings. The bit-permuted sequences π(V 0 ), π(V 1 ), π(V 2 ), multiplexed by multiplexer  224 , are abutted to generate the interleaved output. 
       FIG. 3(   b ) is a block diagram of a channel interleaver  108  for turbo encoded sub-packets. For turbo encoded subpackets, the encoder  106  5N T  output data bits are demultiplexed by demultiplexer  302  into five sequences U, V 0 , V 1 , V′ 0 , V′ 1 . The first encoder  106  output bit goes to the U sequence, the second to the V 0  sequence, the third to the V 1  sequence, the fourth to the V′ 0  sequence, the fifth to the V′ 1  sequence, the sixth to the U sequence, etc. The last 18 tail bits, numbered from  0  to  17 , are demultiplexed as follows: Tail bits  0 ,  3 ,  6 ,  9 ,  12 , and  15  go to sequence U, tail bits  1 ,  4 , and  7  go to sequence V 0 , tail bits  2 ,  5 , and  8  go to sequence V 1 , tail bits  10 ,  13 , and  16  go to sequence V′ 0 , and tail bits  11 ,  14 , and  17  go to sequence V′ 1 . As a result, sequence U has length N T +6, while the other four sequences have length N T +3. 
     Next, the demultiplexed sequences are bit-permuted using five Pruned Bit Reversal Interleavers (PBRIs) ( 304   a - 304   e ) into three separate interleaved blocks, denoted as π(U), π(V 0 /V′ 0 ), and π(V 1 /V′ 1 ), as follows. The sequence U is permuted into the block π(U) using a length N T +6 PBRI. Sequences V 0  and V′ 0  are each permuted independently using a length N T +6 PBRI into sequences π(V 0 ) and π(V′ 0 ), respectively. The two sequences π(V 0 ) and π(V′ 0 ) are then combined into the block π(V 0 /V′ 0 ) by selecting bits from the two sequences in an alternating fashion, starting with π(V 0 ). The length of the resulting π(V 0 /V′ 0 ) block is 2N T +6. Similarly, the block π(V 1 /V′ 1 ) is generated from the two sequences V 1  and V′ 1 . The three output blocks are then concatenated by Multiplexer  306  into the sequence π(U)/π(V 0 /V′ 0 )/π(V 1 /V′ 1 ) and generated as the channel interleaver  108  output. 
     Depending on the channel type and the hybrid automatic repeat-request (HARQ) interlacing structure determined by the Medium Access Control (MAC) protocol, four code rates of 1/5, 1/3, 1/2 and 2/3 are supported by puncturing bits from the blocks π(V 0 /V′ 0 ) and π(V 1 /V′ 1 ) as detailed below in  FIG. 4 . The resulting interleaved sequences are repeated by sequence repeater  110  and scrambled by data scrambler before being multiplexed and modulated by the Multiplexer and Modulation Symbol Mapper  114 . 
       FIG. 4  shows the codeword structure of turbo-encoded subpackets  400  for four different codes rates: rate-1/5  402 , rate-1/3  404 , rate-1/2  406 , and rate-2/3  408 . The structure of the rate-1/3 codeword  404  is similar to that of the rate-1/5 codeword  402  with the exception that the last symbols designated by π(V 1 /V′ 1 ) symbols are pruned away. Similarly, for the rate-1/2 codeword  406 , half of the π(V 0 /V′ 0 ) symbols are additionally pruned. For the rate-2/3 codeword  408 , three-fourths of the π(V 0 /V′ 0 ) symbols and all π(V 1 /V′ 1 ) symbols are pruned away. 
     Channel Deinterleaver Architecture 
     The functions described above used to generate the interleaver addresses are invertible. Thus, their inverse interleaver functions can be used to generate deinterleaver addresses. 
       FIG. 5  shows the top-level architecture of an exemplary deinterleaver/decoder block  500 . The block has two independent datapaths for separately deinterleaving and decoding convolutionally encoded and turbo encoded subpackets. Data Path  1   506  deinterleaves and decodes convolutionally encoded subpackets. Data path  2   508  deinterleaves and decodes turbo encoded subpackets. A buffer manager  502  maintains symbol log likelihood ratio (LLR) values written into symbol LLR memory  504  by an external LLR slicer. An external Digital Signal Processor (DSP) issues commands to the buffer manager  502  to decode received packets. The buffer manager  502  requests the LLR symbols of all subpackets of the corresponding packet to be decoded from the LLR slicer and writes them into LLR memory  504 . Depending on the packet type, the buffer manager  502  dispatches the constituent subpackets to either the turbo datapath (data path  2 ,  508 ) or the Viterbi convolutional code datapath (data path  1 ,  506 ). The Viterbi convolutional code datapath (data path  1 ,  506 ) is further detailed in  FIG. 6(   a ). The Turbo code datapath (data path  2 ,  508 ) is further detailed in  FIG. 7 . 
     Subpackets can be dispatched in parallel to both datapaths ( 506  and  508 ). After decoding is complete, information bits of decoded subpackets from both datapaths ( 506  and  508 ) are formatted and written into an external packet memory  512  via an arbiter  510 . Due to requirements of the system under consideration, the architecture of the symbol LLR memory  504 , its bandwidth, and the way symbols are stored were designed to be standard-independent, with support for subpacket specifications for other standards such as LTE and WiMAX. Hence, the interface to LLR memory  504  can be made generic by employing a codeword reader from LLR memory  504  through the buffer manager  502 , and by providing internal buffering of subpackets to be decoded inside the deinterleaver. 
     Deinterleaving for the Viterbi Convolutional Code Datapath 
       FIG. 6(   a ) shows a more detailed block diagram of the exemplary convolutional channel deinterleaver datapath  506 . The codeword reader  602  copies a packet length of LLR symbols into internal codeword buffer  604  where symbols are stored in sequential order. The subpacket length, puncturing length, and packet destination address are propagated along with the packet through each block of  FIG. 6(   a ). Where less than 3(N v +8) LLR symbols are available in LLR memory when a packet is output for decoding, the codeword reader  602  fills in zeros in the remaining punctured positions as it copies the subpacket LLRs into the codeword buffer  604 . 
     The interleaving structure shown in  FIG. 2(   b ) first requires splitting the packet into three sequences π(V 0 ), π(V 1 ), π(V 2 ). These three sequences are interleaved by the PBRI block  606 . Because the three sequences have the same length, the interleaving can be performed by a single PBRI block  606 . The actual PBRI mapping, described in  FIGS. 3(   b ) and  4 , is the same operation for interleaving and deinterleaving 
     The PBRI block  606  must generate a valid interleaved address every clock cycle. However, due to the pruning operation, the bit-reversed address of a linear address x might not be a valid address, i.e. π(x)≧N T +8. The property is used that two consecutive linear addresses cannot both have invalid interleaved addresses in generating a valid interleaved address every clock cycle as shown using the sequential PBRI in  FIG. 6(   b ). This follows from the fact that the length of the mother interleaver (2 n ) cannot exceed twice the length of the sequence to be interleaved, and that if π(x)≧N T +8, then the least significant bit of the n-bit address x must be 1, which implies that the least-significant bit of address x+1 must be 0, which implies that π(x+1)&lt;N T +8, and hence π(x+1) is valid. The deinterleaving buffer  608 , Viterbi decoder  610  and packet writer  612  complete the deinterleaving operation for convoltionally encoded subpackets. 
       FIG. 6(   b ) details the functionality of the PBRI block illustrated in  FIG. 6(   a ). A counter  652  maintains the number of invalid bit-reversed addresses starting from zero. The count is added to the current linear address x, which is then bit-reversed by bit reverse elements  654  and  656  together with x+1. If π(x)≦N T +8, then the counter  652  is not updated and π(x) is the resulting interleaved address. Otherwise, the counter  652  is advanced and π(x+1) is the resulting valid interleaved address. In other embodiments, this method can be generalized to generate more than one valid interleaved address every clock cycle, at the expense of increased complexity. A low-complexity parallel look ahead scheme that interleaves an address x in O(log(x)) complexity as opposed to O(x) complexity for the sequential PBRI was proposed in U.S. patent application Ser. No. 12/264,880, filed Nov. 4, 2008 and it is incorporated by reference herein. However, for the throughput requirements of the system under consideration, generating only one valid interleaved address every clock cycle using a sequential PBRI is sufficient. 
     With reference to  FIG. 6(   a ) the PRBI block  606  uses the same or similar interleaver as that shown in  FIG. 2(   a ). However the PRBI block  606  operates such that output addresses are mapped to input addresses according to the inverse interleaver function π 1 . Data is likewise deinterleaved. The resulting deinterleaved sequences are written into a deinterleaver buffer  608 . A Viterbi decoder  610  then reads the deinterleaved symbols of a packet from this buffer  608  and passes the decoded hard decision bits to a packet writer  612 , which stores the bits into external decoded packet memory. In one embodiment, the packet writer  612  is coupled to a high-priority cycle-stealing port on the arbiter  510 , which grants quick access to the external bus to the packet memory to write the 112 (=128−24) decoded bits in two cycles. Therefore, output buffering is not necessary to store the decoded output bits from the Viterbi decoder  610 . In cases where the packet writer  612  is not granted bus access, the Viterbi decoder  610  is stalled. All buffers utilized in  FIG. 6(   a ) are double-buffers, which allow simultaneous operation of adjacent blocks on back-to-back packets. 
     Deinterleaving for the Turbo Code Datapath 
       FIG. 7  shows a block diagram of the turbo channel deinterleaver datapath  508 . Similar to the Viterbi channel deinterleaver datapath shown in  FIG. 6(   a ), a codeword reader block  702  copies a packet length of LLR symbols into internal codeword buffer  704 , where symbols are stored in sequential order. Depending on a Hybrid Automatic Repeat Request (HARQ) interlacing structure, the codeword reader  702  inserts zero LLRs in punctured positions when copying the subpacket LLRs into the codeword buffer  704 . The symbol interleaving scheme shown in  FIG. 3(   b ), first requires splitting the subpacket on the input side of the interleaver into three sequences π(U), π(V 0 /V′ 0 ), π(V 1 /V′ 1 ), then splitting π(V 0 /V′ 0 ) into π(V 0 ) and π(V′ 0 ), and splitting π(V 1 /V′ 1 ) into π(V 1 ) and π(V′ 1 ). The inverse of this is accomplished, for instance at the receiver, with the interleaver operating to produce an inverse interleaving function π 1 . As such, still with reference to  FIG. 6(   a ), the deinterleaving of the five sequences π(U), π(V 0 ), π(V′ 0 ), π(V 1 ) and π(V′ 1 ) is accomplished using a pruned bit-reversal interleaver  710 . A codeword splitter  706  performs the splitting task and writes the resulting LLR symbols to a symbol buffer  708 , which is composed of five memory banks (U/V 0 /V′ 0 /V 1 /V′ 1 ). The length of π(U) is N T +6, while the length of the remaining four sequences is N T +3. The PBRI block  710  performs deinterleaving of the five sequences in parallel using two PBRI blocks similar to that shown in  FIG. 6(   b ), one with mother length N T +6, and one with mother length N T +8. 
       FIG. 8(   a ) further details exemplary operations  800  of the codeword splitter  706  and the PBRI blocks  710 .  FIG. 8(   a ) also shows depuncturing operations performed on the tail bits of the five deinterleaved sequences before passing them to the turbo decoder  714 . The turbo decoder  714  expects five LLR symbols corresponding to the five turbo encoder output bits generated for every input bit when decoding a rate-1/5 code. The first three symbols are passed to the first constituent decoder  302 , while the first and last two symbols are passed to the second constituent decoder  304 . Hence for the six tail bits, a total of 30 LLR symbols are required. However, the five deinterleaved sequences generate only 6+4×3=18 tail symbols. The remaining 12 LLR symbols are inserted by extending the four sequences V 0 , V′ 0 , V 1  and V′ 1  into N T +6 symbols and filling in zeros. For compatibility issues with earlier EV-DO Rev. A data rates and puncturing patterns, the tail bits of V 0  are moved to the third sequence, and those for V′ 1  are moved to the fourth sequence. The depuncturing patterns for the rate-1/3 code are also shown. 
     The input demux  802  decomposes the incoming stream of symbols into πι(U), πι(V 0 /V 0 ′), and πι(V 1 /V 1 ′). A splitter  804  further splits πι(V 0 /V 0 ′) into πι(V 0 )and πι(V 0 ′), and πι(V 1 /V 1 ′) into πι(V 1 ) and πι(V 1 ′). The five streams πι(U), πι(V 0 ), πι(V 0 ′), πι(V 1 ), pi(V 1 ′) are then independently permuted using a PBRI  806  to generate the streams U, V 0 , V 0 ′, V 1 , V 1 ′. The structure of these streams is shown at the output of the PBRI blocks  806  in the figure: U contains N T  data symbols and 6 tail symbols, while the remaining 4 streams each contain N T  data symbols and 3 tails symbols. A switch  808  then performs depuncturing operations on these streams to produce the outputs, sym 0 -sym 4 . For rate-1/5 depuncturing, five streams are produced (U, V 0 , V 1 , V 0 ′, V 1 ′ in this order), while for rate-1/3 depuncturing only 3 streams are produced (U, V 0 , V 0 ′ in this order). Zeros are inserted in the tail symbols. 
     Depuncturing operations performed on the tail bits are further detailed below. Note that these streams must be passed to the turbo decoder  714 , which expects five symbols corresponding to the five turbo encoder output bits generated for every input bit when decoding a rate-1/5 code. The first three symbols are passed to the first constituent decoder  302 , while the first and last two symbols are passed to the second constituent decoder  304 . Hence for the six tail bits, a total of 30 symbols are required. However, the five deinterleaved sequences generate only 6+4*3=18 tail symbols. The remaining 12 symbols are inserted by extending the four sequences V 0 , V′ 0 , V 1  and V′ 1  into N T +6 symbols and filling in zeros as shown. For compatibility issues with earlier EV-DO Rev-A data rates and puncturing patterns, the tail bits of V 0  are moved to the third sequence, and those for V′ 1  are moved to the fourth sequence. The depuncturing patterns for the rate-1/3 code are also shown. The resulting deinterleaved/depunctured rate-1/5 and rate-1/3 subpacket structure of the operations are further detailed in  FIG. 8(   b ). 
     The deinterleaved symbols output by the PBRI block  806  are written into a deinterleaver buffer  712 , which controls the operation of the turbo decoder  714 . For each decoding iteration, the turbo decoder  714  reads forward and back LLR symbols in parallel from the deinterleaver buffer  712 . Upon completion, it writes the decoded output decision bits into an output buffer  716  together with other decoding statistics about the decoded subpacket. In one embodiment, the output buffer  716  is a circular buffer than can hold up to eight decoded subpackets. The packet writer block  718  removes the CRC bits and writes the information bits of all decoded subpackets corresponding to the same packet into the external packet memory through an arbiter  510 . Subpackets belonging to the same packet are abutted to each other in packet memory. Where any subpacket fails to decode, the turbo decoder  714  flushes the internal buffers ( 704 ,  708 ,  712 ,  716 ) in the turbo code datapath. If the output buffer  716  is full, then the turbo decoder is stalled until the packet writer  718  is granted access to the external bus to empty subpackets from the output buffer  716 . 
       FIG. 8(   b ) shows the deinterleaved/depunctured rate-1/5 and rate-1/3 packet structures  850  resulting from the operations detailed in  FIG. 8(   a ). Deinterleaved packet  852  is the final deinterleaved sub-packet before depuncturing. 1/5-rate packets  854   a  and  854   b  show the resulting structure after depuncturing and tail adjustment for the rate-1/5 case. 1/3-rate packets  856   a  and  856   b  likewise correspond to the rate-1/3 case. These packets ( 854   a ,  854   b ,  856   a ,  856   b ) are known in the art as “codewords”. By comparing the depunctured codeword  854   a  to the deinterleaved packet  852 , the construction of a rate-1/5 codeword is determined, where X&#39;s designate punctured symbols. Rate-1/5 packet  854   b  illustrates zeros inserted tail symbols. By comparing the depunctured codeword  856   a  to the deinterleaved packet  852 , the construction of a rate-1/3 codeword is determined, where X&#39;s designate punctured symbols. Rate-1/3 packet  856   b  illustrates zeros inserted tail symbols. 
     Those of skill in the art would understand that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. 
     Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention. 
     The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.