Patent Publication Number: US-2022223682-A1

Title: Semiconductor element

Description:
CROSS REFERENCE TO RELATED APPLICATION 
     This application is a continuation-in-part application of International Patent Application No. PCT/JP2020/037781 (Filed on Oct. 5, 2020), which claims the benefit of priority from Japanese Patent Application No. 2019-182970 (filed on Oct. 3, 2019), No. 2019-182971 (filed on Oct. 3, 2019) and No. 2019-182972 (filed on Oct. 3, 2019). 
     The entire contents of the above applications, which the present application is based on, are incorporated herein by reference. 
    
    
     1. FIELD OF THE INVENTION 
     The present disclosure relates to a semiconductor element that is useful as, e.g., a power device. 
     2. DESCRIPTION OF THE RELATED ART 
     Gallium oxide (Ga 2 O 3 ) is a transparent semiconductor that has a wide bandgap of 4.8-5.3 eV at room temperature and that absorbs little visible and ultraviolet light. Therefore, in particular, gallium oxide is a promising material for use in optical/electronic devices that operate in a deep ultraviolet range and transparent electronics, and in recent years, development of photodetectors, light-emitting diodes (LED) and transistors based on gallium oxide (Ga 2 O 3 ) has been underway. 
     There are five, α, β, γ, σ and ε, crystal structures of gallium oxide (Ga 2 O 3 ), and generally, the most stable structure is β-Ga 2 O 3 . However, β-Ga 2 O 3  has a β-gallia structure, and unlike crystalline systems and the like generally used in electronic materials, is not necessarily suitable for use in semiconductor devices. Also, growth of a β-Ga 2 O 3  thin film needs a high substrate temperature and a high degree of vacuum, causing a problem of an increase in manufacturing cost. In addition, in the case of β-Ga 2 O 3 , even a high concentration (for example, no less than 1×10 19 /cm 3 ) of a dopant (Si) needs to be subjected to annealing treatment at a high temperature of 800° C. to 1100° C. after ion implantation, to use the dopant as a doner. 
     On the other hand, α-Ga 2 O 3  has a crystal structure that is the same as that of a sapphire substrate, which has already been widely used, and thus, is suitable for use in optical and electronic devices. Furthermore, α-Ga 2 O 3  has a bandgap that is wider than that of β-Ga 2 O 3 , and thus, is particularly useful for power devices. Therefore, semiconductor devices using α-Ga 2 O 3  as a semiconductor have been anticipated. 
     Semiconductor devices using β-Ga 2 O 3  as a semiconductor and using two layers of a Ti layer and an Au layer, three layers of a Ti layer, an Al layer and an Au layer or four layers of a Ti layer, an Al layer, an Ni layer and an Au layer as an electrode providing ohmic characteristics meeting the semiconductor have been known. 
     Also, semiconductor devices using β-Ga 2 O 3  as a semiconductor and using any of Au, Pt and a stack of Ni and Au as an electrode providing Schottky characteristics meeting the semiconductor have been known. 
     However, if any of the above-described electrodes is applied to a semiconductor device using α-Ga 2 O 3  as a semiconductor, there are problems such as failure of the electrode to function as a Schottky electrode or an ohmic electrode, failure of the electrode to be bonded to a film and impairment of semiconductor characteristics. Furthermore, the above-described electrode configurations each have provided no practically satisfactory semiconductor device because of, e.g., occurrence of leak current from an electrode end portion. 
     Also, for bonding, use of an electrically conductive adhesive sheet is conceivable, which, however, causes problems such as deterioration in flatness and occurrence of strain due to stress, etc., being easily concentrated, and thus, it is difficult to apply these electrodes to a semiconductor element itself. 
     SUMMARY OF THE INVENTION 
     According to an example of the present disclosure, there is provided a semiconductor element including; a semiconductor film; and a porous layer disposed on a first surface side of the semiconductor film or a second surface side opposite from the first surface side, a porosity of the porous layer being no more than 10%. 
     According to an example of the present disclosure, there is provided a semiconductor element including; a semiconductor film; and a porous layer disposed on a first surface side of the semiconductor film or a second surface side opposite from the first surface side, the porous layer containing a precious metal. 
     Thus, in the semiconductor element of the present disclosure, the semiconductor element may have porous layer that enables provision of favorable semiconductor characteristics providing excellent flatness and stress relaxation and causing less strain, and the semiconductor element may have excellent structure stability. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a sectional view schematically illustrating a preferable mode of a semiconductor element of the present disclosure; 
         FIG. 2  is a diagram illustrating a mode of a preferable method of manufacturing the semiconductor element in  FIG. 1 ; 
         FIG. 3  is a diagram illustrating a mode of a preferable method of manufacturing the semiconductor element in  FIG. 1 ; 
         FIG. 4  is a diagram illustrating a mode of a preferable method of manufacturing the semiconductor element in  FIG. 1 ; 
         FIG. 5  is a diagram illustrating a mode of a preferable method of manufacturing the semiconductor element in  FIG. 1 ; 
         FIG. 6  is a sectional view schematically illustrating a preferable mode of the semiconductor element of the present disclosure; 
         FIG. 7  is a sectional view schematically illustrating a preferable mode of a semiconductor element of the present disclosure; 
         FIG. 8  includes diagrams each illustrating a sectional SEM image as a result of a test example:  FIG. 8( a )  illustrates a case where a porous layer formed of silver was formed by normal annealing; and  FIG. 8( b )  illustrates a porous layer further subjected to thermal compression bonding to have a porosity of no more than 10%; 
         FIG. 9  is a diagram schematically illustrating a preferable example of a power supply system; 
         FIG. 10  is a diagram schematically illustrating a preferable example of a system device; 
         FIG. 11  is a diagram schematically illustrating a preferable example of a power supply circuit diagram of a power supply device. 
         FIG. 12  is a diagram schematically illustrating a preferable example of a semiconductor device; and 
         FIG. 13  is a diagram schematically illustrating a preferable example of a power card. 
     
    
    
     DETAILED DESCRIPTION 
     Embodiments of the present disclosure will be described below with reference to the accompanying drawings. In the following description, the same parts and components are designated by the same reference numerals. The present embodiment includes, for example, the following disclosures. 
     In the semiconductor element of the present disclosure, the semiconductor element may have porous layer that enables provision of favorable semiconductor characteristics providing excellent flatness and stress relaxation and causing less strain, and the semiconductor element may have excellent structure stability. 
     [Structure  1 ] 
     A semiconductor element including; a semiconductor film; and a porous layer disposed on a first surface side of the semiconductor film or a second surface side opposite from the first surface side, a porosity of the porous layer being no more than 10%. 
     [Structure  2 ] 
     A semiconductor element including; a semiconductor film; and a porous layer disposed on a first surface side of the semiconductor film or a second surface side opposite from the first surface side, the porous layer containing a precious metal. 
     [Structure  3 ] 
     The semiconductor element according to [Structure  1 ] or [Structure  2 ], wherein the semiconductor film is an oxide semiconductor film. 
     [Structure  4 ] 
     The semiconductor element according to any of [Structure  1 ] to [Structure  3 ], wherein the semiconductor film has a corundum structure. 
     [Structure  5 ] 
     The semiconductor element according to any of [Structure  1 ] to [Structure  4 ], wherein a principal plane of the semiconductor film is an m-plane. 
     [Structure  6 ] 
     The semiconductor element according to any of [Structure  1 ] to [Structure  5 ], wherein the semiconductor film contains gallium oxide and/or iridium oxide. 
     [Structure  7 ] 
     The semiconductor element according to any of [Structure  1 ] to [Structure  6 ], wherein the semiconductor film contains a dopant. 
     [Structure  8 ] 
     The semiconductor element according to any of [Structure  1 ] to [Structure  7 ], wherein the porous layer is a porous layer of silver. 
     [Structure  9 ] 
     The semiconductor element according to any of [Structure  1 ] to [Structure  8 ], further including a substrate, wherein the substrate is bonded to the porous layer. 
     [Structure  10 ] 
     The semiconductor element according to [Structure  9 ], wherein at least a part of a surface of the substrate contains nickel. 
     [Structure  11 ] 
     The semiconductor element according to [Structure  9 ], wherein at least a part of the substrate contains gold. 
     [Structure  12 ] 
     The semiconductor element according to [Structure  3 ], further including a dielectric film covering at least a side surface of the oxide semiconductor film. 
     [Structure  13 ] 
     The semiconductor element according to [Structure  12 ], wherein the dielectric film covers an entirety of the side surface of the oxide semiconductor film. 
     [Structure  14 ] 
     The semiconductor element according to [Structure  12 ] or [Structure  13 ], wherein the dielectric film covers at least a part of a first surface of the oxide semiconductor film. 
     [Structure  15 ] 
     The semiconductor element according to any of [Structure  12 ] to [Structure  14 ], wherein the side surface of the oxide semiconductor film is tapered. 
     [Structure  16 ] 
     The semiconductor element according to [Structure  15 ], wherein the tapered side surface of the oxide semiconductor film is inclined in such a manner in that an area of the oxide semiconductor film expands from a first surface of the oxide semiconductor film toward a second surface of the oxide semiconductor film. 
     [Structure  17 ] 
     A semiconductor element including at least; a semiconductor film; a first electrode disposed on a first surface side of the semiconductor film; and a second electrode disposed on a second surface side opposite from the first surface side, the semiconductor element further including a porous layer disposed in contact with the second electrode, and a porosity of the porous layer being no more than 10%. 
     [Structure  18 ] 
     The semiconductor element according to [Structure  17 ], wherein the second electrode includes at least a first metal layer, a second metal layer and a third metal layer. 
     [Structure  19 ] 
     The semiconductor element according to [Structure  18 ], wherein the second metal layer is disposed between the first metal layer and the third metal layer, and the second metal layer is an Pt layer or a Pd layer. 
     [Structure  20 ] 
     The semiconductor element according to [Structure  18 ] or [Structure  19 ], wherein the first metal layer is a Ti layer or an In layer. 
     [Structure  21 ] 
     The semiconductor element according to any of [Structure  18 ] to [Structure  20 ], wherein the third metal layer includes at least one metal layer selected from an Au layer, an Ag layer and a Cu layer. 
     [Structure  22 ] 
     The semiconductor element according to any of [Structure  17 ] to [Structure  21 ], wherein the second electrode is an ohmic electrode. 
     [Structure  23 ] 
     The semiconductor element according to any of [Structure  1 ] to [Structure  22 ], wherein the semiconductor element is a vertical device. 
     [Structure  24 ] 
     The semiconductor element according to any of [Structure  1 ] to [Structure  23 ], wherein the semiconductor element is a power device. 
     [Structure  25 ] 
     A semiconductor device including at least a semiconductor element bonded to a lead frame, a circuit substrate or a heat dissipation substrate with a bonding member, wherein the semiconductor element is the semiconductor element according to any of [Structure  1 ] to [Structure  24 ] 
     [Structure  26 ] 
     The semiconductor device according to [Structure  25 ], wherein the semiconductor device is a power module, an inverter or a converter. 
     [Structure  27 ] 
     The semiconductor device according to [Structure  25 ] or [Structure  26 ], wherein the semiconductor device is a power card. 
     [Structure  28 ] 
     A semiconductor system including a semiconductor element or a semiconductor device, wherein the semiconductor element is the semiconductor element according to any of [Structure  1 ] to [Structure  24 ] and the semiconductor device is the semiconductor device according to any of [Structure  25 ] to [Structure  27 ]. 
     A semiconductor element of the present disclosure includes a semiconductor film (hereinafter also simply referred to a “semiconductor layer”), and a porous layer disposed on a first surface side of the semiconductor film or a second surface side opposite from the first surface side, and a porosity of the porous layer is no more than 10%. Here, the “porosity” refers to a proportion of a volume of space generated by voids in a volume of a porous layer (volume including the voids). It is possible to obtain a porosity of a porous layer based on, for example, a sectional photograph taken using a scanning electron microscope (SEM). More specifically, a sectional photograph (SEM image) of a porous layer is taken from a plurality of positions. Next, the taken SEM images are binarized using commercially available image analysis software to obtain a proportion of parts (for example, black parts) corresponding to holes (voids) in each of the SEM images. The proportions of the black parts obtained from the SEM images taken from the plurality of positions are averaged to determine the resulting proportion as the porosity of the porous layer. Note that the “porous layer” includes not only one in the form of a porous film, which is a continuous film-like structure but also one in the form of a porous aggregate. 
     The porous layer is not specifically limited, but preferably contains a metal, more preferably contains a precious metal, for example, gold (Au), silver (Ag), platinum (Pt), palladium (Pd), rhodium (Rh), iridium (Ir) or ruthenium (Ru), and most preferably contains silver (Ag). The porous layer may be a porous substrate coated with a metal film of, e.g., the precious metal, but in the present disclosure, is preferably a porous layer of the metal, more preferably a porous layer of the precious metal, and most preferably a porous layer of silver (Ag). Also, the porous layer may be single-layered or multi-layered. Also, a thickness of the porous layer is not specifically limited as long as the thickness does not hinder the present disclosure, but is preferably approximately 10 nm to approximately 1 mm, preferably 10 nm to 200 μm, and more preferably 30 nm to 50 μm. 
     It is possible to favorably obtain the porous layer by sintering a metal (preferably a precious metal). Note that a method of making the porosity of the porous layer 10% is not specifically limited and may be a publicly known method. It is possible to easily set the porosity of the porous layer to 10% by appropriately setting sintering conditions such as sintering time, pressure and a sintering temperature. Examples of the method include, e.g., a method in which the porosity is adjusted to no more than 10% by, e.g., compression bonding with heating (thermal compression bonding). More specific examples of the method include, e.g., sintering for sintering time that is longer than normal sintering time, under a fixed pressure.  FIG. 8( a )  illustrates a porosity where a porous layer formed of Ag was bonded by normal annealing as a test example. As illustrated in  FIG. 8( a ) , the porosity of the porous layer normally exceeds 10%, but as illustrated in  FIG. 8( b ) , compressing bonding under pressure of, for example, 0.2 to 10 MPa with heating at, for example, 300° C. to 500° C. for another hour makes the porosity no more than 10%, and use of such porous layer having a porosity of no more than 10% for a semiconductor element enables relaxing, e.g., warpage and concentration of thermal stress without impairing semiconductor characteristics. 
     Also, a semiconductor element of the present disclosure includes a semiconductor film, and a porous layer disposed on a first surface side of the semiconductor film or a second surface side opposite from the first surface side, and the porous layer contains a precious metal. In this case, also, it is more preferably that a porosity of the porous layer be no more than 10%. 
     In the present disclosure, the semiconductor element is preferably a semiconductor element including at least a semiconductor film, a first electrode disposed on a first surface side of the semiconductor film, and a second electrode disposed on a second surface side opposite from the first surface side, wherein the semiconductor element further includes a porous layer disposed in contact with the second electrode and a porosity of the porous layer is no more than 10%, and more preferably a semiconductor element including at least a semiconductor film, a first electrode disposed on a first surface side of the semiconductor film, and a second electrode disposed on a second surface side opposite from the first surface side, wherein the semiconductor film further includes a porous layer disposed in contact with the second electrode, a substrate disposed on the porous layer, and the second electrode includes at least a first metal layer, a second metal layer and a third metal layer, and a porosity of the porous layer is no more than 10%. 
     The substrate is not specifically limited but is preferably a conductive substrate. The conductive substrate is not specifically limited as long as the conductive substrate has electrical conductivity and is capable of supporting the semiconductor layer. A material of the conductive substrate is also not specifically limited as long as such material does not hinder the present disclosure. Examples of the material of the conductive substrate include, e.g., metals (for example, aluminum, nickel, chromium, nichrome, copper, gold, silver, platinum, rhodium, indium, molybdenum and tungsten), electrically conductive metal oxides (for example, ITO (InSnO compound) and FTO (tin oxide with, e.g., fluorine doped) and zinc oxide), silicon (Si) and electrically conductive carbon. In the present disclosure, the conductive substrate preferably contains a transition metal, more preferably contains at least one metal selected from groups 6 and 11 of the periodic table, and preferably contains a metal in group 6 of the periodic table. Examples of a metal in group 6 of the periodic table include, e.g., at least one or more metals selected from chromium (Cr), molybdenum (Mo) and tungsten (W). In the present disclosure, the metal in group 6 of the periodic table includes molybdenum. Examples of a metal in group 11 of the periodic table include, e.g., at least one metal selected from copper (Cu), silver (Au) and gold (Au). Also, in the present disclosure, it is preferable that the conductive substrate contain two or more metals, and examples of a combination of such two or more metals include, e.g., copper (Cu)-silver (Ag), copper (Cu)-tin (Sn), copper (Cu)-iron (Fe), copper (Cu)-tungsten (W), copper (Cu)-molybdenum (Mo), copper (Cu)-titanium (Ti), molybdenum (Mo)-lanthanum (La), molybdenum (Mo)-yttrium (Y), molybdenum (Mo)-rhenium (Re), molybdenum (Mo)-tungsten (W), molybdenum (Mo)-niobium (Nb) and molybdenum (Mo)-tantalum (Ta). In the present disclosure, the conductive substrate preferably contains molybdenum as a major component and more preferably contains molybdenum and copper. Here, the “major component” means that, for example, where the conductive substrate contains Mo as a major component, Mo is contained at an atom ratio of preferably no less than 50%, more preferably no less than 70%, and still more preferably no less than 90% to all components of the conductive substrate, and the atom ratio may be 100%. Use of a combination of the preferable material of the conductive substrate, the preferable electrically conductive adhesive layer and the preferable semiconductor layer enables more favorably providing semiconductor characteristics of the preferable semiconductor layer in the semiconductor element. In the present disclosure, it is preferable that at least a part of a surface of the substrate contain nickel and it is also preferable that at least a part of the surface of the substrate contain gold. 
     Note that the substrate may be bonded to the porous layer with one or more other layers in between such as an adhesive layer (for example, an electrically conductive adhesive layer or an adhesive layer formed of a metal). 
     The semiconductor film is not specifically limited as long as the semiconductor film is a film containing a semiconductor, and may be an oxide semiconductor film, preferably contains a crystalline oxide semiconductor, and more preferably contains a crystalline oxide semiconductor as a major component. Also, in the present disclosure, the crystalline oxide semiconductor contains preferably one or two or more metals selected from group 9 (for example, cobalt, rhodium or iridium) and group 13 (for example, aluminum, gallium or indium) of the periodic table, more preferably at least one metal selected from aluminum, indium, gallium and iridium, and most preferably at least gallium or iridium. A crystal structure of the crystalline oxide semiconductor is not specifically limited. Examples of the crystal structure of the crystalline oxide semiconductor include, e.g., a corundum structure, a β-gallia structure and a hexagonal crystal structure (for example, an ε-structure). In the present disclosure, it is preferable that the crystalline oxide semiconductor have a corundum structure and it is more preferable that the crystalline oxide semiconductor have a corundum structure and a principal plane is an m-plane. Also, the crystalline oxide semiconductor may have an off angle. In the present disclosure, the semiconductor film preferably contains gallium oxide and/or iridium oxide and more preferably contains α-Ga 2 O 3  and/or α-Ir 2 O 3 . Here, the “major component” means that the crystalline oxide semiconductor is contained at an atom ratio of preferably no less than 50%, more preferably no less than 70%, still more preferably no less than 90% to all components of the semiconductor layer and means that the atom ratio may be 100%. Also, a thickness of the semiconductor layer is not specifically limited and may be no more than 1 μm or may be no less than 1 μm; however, in the present disclosure, the thickness of the semiconductor layer is preferably no less than 1 μm, and more preferably no less than 10 μm. A surface area of the semiconductor film is not specifically limited and may be no less than 1 mm 2  or may be no more than 1 mm 2 , but is preferably 10 mm 2  to 300 cm 2 , and more preferably 100 mm 2  to 100 cm 2 . Also, the semiconductor layer is normally a single crystal but may be a polycrystal. Also, it is preferable that the semiconductor layer be a multi-layer film including at least a first semiconductor layer and a second semiconductor layer, wherein where a Schottky electrode is provided on the first semiconductor layer, a carrier density of the first semiconductor layer is smaller than a carrier density of the second semiconductor layer. In this case, the second semiconductor layer normally contains a dopant and it is possible to arbitrarily set a carrier density of the semiconductor layer by adjusting a doping amount. 
     The semiconductor layer preferably contains a dopant. The dopant is not specifically limited and may be a publicly known one. Example of the dopant include, e.g., n-type dopants such as tin, germanium, silicon, titanium, zirconium, vanadium and niobium and p-type dopants such as magnesium, calcium and zinc. In the present disclosure, it is preferable that the n-type dopant be Sn, Ge or Si. An amount of the dopant contained is preferably no less than 0.00001 atom %, more preferably 0.00001 atom % to 20 atom %, and most preferably 0.00001 atom % to 10 atom % in a composition of the semiconductor layer. More specifically, a concentration of the dopant may normally approximately 1×10 16 /cm 3  to 1×10 22 /cm 3  or the concentration of the dopant may be set to be a low concentration of, for example, approximately no more than 1×10 17 /cm 3 . Also, according to an aspect of the present disclosure, the dopant may be contained in a high concentration of approximately 1×10 20 /cm 3 . Furthermore, a concentration of fixed charge in the semiconductor layer is not specifically limited; however, in the present disclosure, it is preferable that the concentration of fixed charge in the semiconductor layer be no more than 1×10 17 /cm 3  because such concentration enables more favorably forming a depletion layer with the semiconductor layer. 
     The semiconductor layer may be formed using a publicly known method. Examples of a method of forming the semiconductor layer include, e.g., a CVD method, an MOCVD method, an MOVPE method, a mist CVD method, a mist epitaxy method, an MBE method, an HVPE method, a pulse growth method and an ALD method. In the present disclosure, it is preferable that the method of forming the semiconductor layer be the mist CVD method or the mist epitaxy method. In the mist CVD method or the mist epitaxy method, the semiconductor layer is formed by, for example, atomizing a raw material solution (atomization step) to make droplets be suspended, and after the atomization, carrying the resulting atomized droplets above a base with a carrier gas (carrying step), and subsequently stacking a semiconductor film containing a crystalline oxide semiconductor as a major component on the base through thermal reaction of the atomized droplets in the vicinity of the base (film forming step). 
     (Atomization Step) 
     In the atomization step, the raw material solution is atomized. A method of atomization of the raw material solution is not specifically limited as long as such method enables atomization of the raw material solution and may be a publicly known method; however, in the present disclosure, an atomization method using ultrasound is preferable. Atomized droplets obtained using ultrasound are preferable because of having an initial velocity of zero and being suspended in air. The atomized droplets (including mist) are very preferable because the atomized droplets are not, for example, those sprayed with a sprayer but are suspended in space and are carried as gas, and thus, are not damaged by collision energy. A size of each of the droplets is not specifically limited and may be around several millimeters, but preferably no more than 50 μm, more preferably 100 nm to 10 μm. 
     (Raw Material Solution) 
     The raw material solution is not specifically limited as long as the raw material solution is capable of being atomized or being made into droplets and contains a raw material that enables forming of a semiconductor film, and the material may be inorganic or organic. In the present disclosure, the raw material is preferably a metal or a metal compound, more preferably one or two or more metals selected from aluminum, gallium, indium, iron, chromium, vanadium, titanium, rhodium, nickel, cobalt and iridium. 
     In the present disclosure, as the raw material solution, one obtained by dissolving or dispersing the metals in an organic solvent or water in the form of a complex or a salt may be preferably used. Examples of the form of a complex include, e.g., acetylacetonate complexes, carbonyl complexes, ammine complexes and hydride complexes. Examples of the form of a salt include, e.g., organic metal salts (for example, metal acetates, metal oxalates, metal citrates, etc.), metal sulfide salts, metal nitrate salts, metal phosphate salts and metal halide salts (for example, metal chloride salts, metal bromide salts, metal iodide salts, etc.). 
     Also, it is preferable that additive agents such as a hydrohalic acid and an oxidizing agent be mixed in the raw material solution. Examples of the hydrohalic acid include, e.g., a hydrobromic acid, a hydrochloric acid and a hydroiodic acid, and among others, a hydrobromic acid or a hydroiodic acid is preferable because of being capable of more efficiently curbing generation of abnormal grains. Examples of the oxidizing agent include, e.g., peroxides such as hydrogen peroxide (H 2 O 2 ), sodium peroxide (Na 2 O 2 ), barium peroxide (BaO 2 ) and benzoyl peroxide (C 6 H 5 CO) 2 O 2  and organic peroxides such as a hypochlorous acid (HClO), a perchloric acid, a nitric acid, ozone water, acetyl hydroperoxide and nitrobenzene. 
     The raw material solution may contain a dopant. A dopant being contained in the raw material solution enables doping to be performed favorably. The dopant is not specifically limited as long as such dopant does not hinder the present disclosure. Examples of the dopant include, e.g., n-type dopants such as tin, germanium, silicon, titanium, zirconium, vanadium and niobium and p-type dopants such as Mg, H, Li, Na, K, Rb, Cs, Fr, Be, Ca, Sr, Ba, Ra, Mn, Fe, Co, Ni, Pd, Cu, Ag, Au, Zn, Cd, Hg, Ti, Pb, N and P. An amount of the dopant contained is appropriately set using a calibration curve indicating a relationship of a concentration of a dopant in a raw material with a desired carrier density. 
     A solvent of the raw material solution is not specifically limited and may be an inorganic solvent such as water or may be an organic solvent such as alcohol or may be a mixed solvent of an inorganic solvent and an organic solvent. In the present disclosure, the solvent preferably contains water, and more preferably is a mixed solvent of water and alcohol. 
     (Carrying Step) 
     In the carrying step, the atomized droplets are carried into a film forming chamber by the carrier gas. The carrier gas is not specifically limited as long as the carrier gas does not hinder the present disclosure, and preferable examples of the carrier gas include, e.g., inert gases such as oxygen, ozone, nitrogen and argon and reducing gases such as hydrogen gas and forming gas. Also, for a type of the carrier gas, a single type or two or more types of the carrier gas may be used, and, e.g., a dilute gas with a flow rate lowered (for example, a 10-fold diluted gas) may further be used as a second carrier gas. Also, the number of locations for supply of the carrier gas is not limited to one but may be two or more. A flow rate of the carrier gas is not specifically limited but is preferably 0.01 to 20 L/minute, and more preferably 1 to 10 L/minute. In the case of a dilute gas, a flow rate of the dilute gas is preferably 0.001 to 2 L/minute, and more preferably 0.1 to 1 L/minute. 
     (Film Forming Step) 
     In the film forming step, the semiconductor film is formed on the base through thermal reaction of the atomized droplets in the vicinity of the base. It is only necessary that the atomized droplets react with heat, and conditions, etc., of the thermal reaction are not specifically limited as long as such conditions, etc., do not hinder the present disclosure. In the present step, the thermal reaction is normally performed at a temperature that is equal to or exceeds an evaporation temperature of the solvent but preferably no more than a temperature that is not too high (for example, 1000° C.), more preferably no more than 650° C., and most preferably no more than 300° C. to 650° C. Also, the thermal reaction may be performed under any atmosphere of vacuum, a non-oxygen atmosphere (for example, an inert gas atmosphere, etc.), a reducing gas atmosphere and an oxygen atmosphere as long as such atmosphere does not hinder the present disclosure; however, it is preferable that the thermal reaction be performed under an inert gas atmosphere or an oxygen atmosphere. Also, the thermal reaction may be performed under any condition of atmospheric pressure, increased pressure and reduced pressure; however, in the present disclosure, it is preferable that the thermal reaction be performed under atmospheric pressure. Note that it is possible to set a film thickness of the semiconductor film by adjusting film forming time. 
     (Base) 
     The base is not specifically limited as long as the base is capable of supporting the semiconductor film. A material of the base is also not specifically limited as long as the material does not hinder the present disclosure, and may be a publicly known base, and may be an organic compound or may be an inorganic compound. A shape of the base may be any shape and the base is effective in any and all shapes including, for example, plate-like shapes such as a flat plate and a circular plate, a fibrous shape, a rod-like shapes, a columnar shape, a prism shape, a tubular shape, a helical shape, a spherical shape and a ring-like shape; however, in the present disclosure, a substrate is preferable. A thickness of the substrate is not specifically limited in the present disclosure. 
     The substrate is not specifically limited as long as the substrate has a plate-like shape and serves as a support for the semiconductor film. The substrate may be an insulator substrate, may be a semiconductor substrate or may be a metal substrate or an electrically conductive substrate; however, the substrate is preferably an insulator substrate and is also preferably a substrate including a metal film on a surface. Examples of the substrate include, e.g., a base substrate containing a substrate material having a corundum structure as a major component, a base substrate containing a substrate material having a β-gallia structure as a major component and a base substrate containing a substrate material having a hexagonal crystal structure as a major component. Here, the “major component” means that any of the substrate materials each having a particular crystal structure is contained at an atom ratio of preferably no less than 50%, more preferably no less than 70%, still more preferably no less than 90% to all components of the substrate material, and the atom ratio may be 100%. 
     The substrate material is not specifically limited as long as the substrate material does not hinder the present disclosure, and may be a publicly known one. Preferable examples of the substrate material having a corundum structure include α-Al 2 O 3  (sapphire substrate) and α-Ga 2 O 3 , and more preferable examples of the same include, e.g., an a-plane sapphire substrate, an m-plane sapphire substrate, an r-plane sapphire substrate, a c-plane sapphire substrate and an α-gallium oxide substrate (a-plane, m-plane or r-plane). Examples of the base substrate containing a substrate material having a β-gallia structure as a major component include, e.g., a β-Ga 2 O 3  substrate and a mixed crystal substrate containing Ga 2 O 3  and Al 2 O 3  in which Al 2 O 3  is contained at no less than 0 wt % and no more than 60 wt %. Also, examples of the base substrate containing a substrate material having a hexagonal crystal structure as a major component include, e.g., an SiC substrate, a ZnO substrate and a GaN substrate. 
     In the present disclosure, after the film forming step, annealing treatment may be performed. A temperature of the annealing treatment is not specifically limited as long as such temperature does not hinder the present disclosure, and is normally 300° C. to 650° C., and preferably 350° C. to 550° C. Also, a length of time of the annealing treatment is normally 1 minute to 48 hours, preferably 10 minutes to 24 hours, and more preferably 30 minutes to 12 hours. Note that the annealing treatment may be performed under any atmosphere as long as such atmosphere does not hinder the present disclosure. The atmosphere may be a non-oxygen atmosphere or an oxygen atmosphere. Examples of the non-oxygen atmosphere include, e.g., inert gas atmospheres (for example, a nitrogen atmosphere) and reducing gas atmospheres, and in the present disclosure, an inert gas atmosphere is preferable and a nitrogen atmosphere is more preferable. 
     Also, in the present disclosure, the semiconductor film may be provided directly on the base or the semiconductor film may be provided on the base with other layers in between such as a stress relaxation layer (for example, a buffer layer or an ELO layer) and a removal sacrificial layer. Methods for forming the respective layers are not specifically limited and may be publicly known methods, but in the present disclosure, a mist CVD method is preferable. 
     In the present disclosure, the semiconductor film may be used in a semiconductor element as the semiconductor layer after use of a publicly known method of, e.g., removal of the semiconductor film from, e.g., the base or may be used as it is in a semiconductor element as the semiconductor layer. 
     In the present disclosure, it is preferable that the second electrode be an ohmic electrode. 
     It is preferable that the ohmic electrode include at least a first metal layer, a second metal layer and a third metal layer, the second metal layer be disposed between the first metal layer and the third metal layer and the second metal layer be a Pt layer or a Pd layer. Note that the first metal layer, the second metal layer and the third metal layer normally include respective one or two or more different metals. In the present disclosure, it is preferable that the first metal layer of the ohmic electrode be a Ti layer or an In layer. Also, it is preferable that the third metal layer of the ohmic electrode include at least one metal layer selected from an Au layer, an Ag layer and a Cu layer. A thickness of each of the metal layers of the ohmic electrode is not specifically limited but is preferably 0.1 nm to 10 μm, more preferably 5 nm to 500 nm, and most preferably 10 nm to 200 nm. 
     In the present disclosure, it is preferable that the first electrode be a Schottky electrode. 
     The Schottky electrode (hereinafter, simply referred to as an “electrode layer”) is not specifically limited as long as the Schottky electrode has electrical conductivity and is usable as a Schottky electrode and does not hinder the present disclosure. A component material of the electrode layer may be an electrically conductive inorganic material or may be an electrically conductive organic material. In the present disclosure, it is preferable that the material of the electrode be a metal. Preferable examples of the metal include, e.g., at least one metal selected from groups 4 to 11 of the periodic table. Examples of a metal in group 4 of the periodic table include, e.g., titanium (Ti), zirconium (Zr) and hafnium (Hf). Examples of a metal in group 5 of the periodic table include, e.g., vanadium (V), niobium (Nb) and tantalum (Ta). Examples of a metal in group 6 of the periodic table include, e.g., chromium (Cr), molybdenum (Mo) and tungsten (W). Examples of a metal in group 7 of the periodic table include, e.g., manganese (Mn), technetium (Tc) and rhenium (Re). Examples of a metal in group 8 of the periodic table include, e.g., iron (Fe), ruthenium (Ru) and osmium (Os). Examples of a metal in group 9 of the periodic table include, e.g., cobalt (Co), rhodium (Rh) and iridium (Ir). Examples of a metal in group 10 of the periodic table include, e.g., nickel (Ni), palladium (Pd) and platinum (Pt). Examples of a metal in group 11 of the periodic table include, e.g., copper (Cu), silver (Ag) and gold (Au). In the present disclosure, it is preferable that the Schottky electrode contain molybdenum and/or cobalt. A layer thickness of the electrode layer is not specifically limited, but is preferably 0.1 nm to 10 μm, more preferably 5 nm to 500 nm, and most preferably 10 nm to 200 nm. Also, in the present disclosure, it is preferable that the electrode layer be one including two or more layers having different compositions. The electrode layer having such preferable configuration enables not only providing a semiconductor element having more excellent Schottky characteristics but also more favorably exerting a leak current curbing effect. 
     In the present disclosure, it is preferable that the Schottky electrode include at least a first metal layer, a second metal layer and a third metal layer. The first metal layer of the Schottky electrode is preferably a transition metal layer, more preferably an Mo and/or Co layer, and most preferably a Co layer or an Mo layer. Also, the second metal layer of the Schottky electrode is preferably a Ti layer and the third metal layer of the Schottky electrode is preferably an Al layer. 
     A method of forming the electrode layer is not specifically limited and may be a publicly known method. Specific examples of the method of forming the electrode layer include, e.g., a dry method and a wet method. Example of the dry method include, e.g., sputtering, vacuum vapor deposition and CVD. Examples of the wet method include, e.g., screen printing and die coating. 
     Also, in an aspect of the present disclosure, it is preferable that the Schottky electrode have a structure in which a film thickness decreases toward the outer side of the semiconductor element. In this case, the Schottky electrode may include a tapered region in each side surface and the Schottky electrode may include two or more layers including a first electrode layer and a second electrode layer, and an outer end portion of the first electrode layer may be located outside of an outer end portion of the second electrode layer. In an aspect of the present disclosure, if the Schottky electrode includes a tapered region, a taper angle of the tapered region is not specifically limited as long as the taper angle does not hinder the present disclosure, but is preferably no more than 80°, more preferably no more than 60°, and most preferably no more than 40°. A lower limit of the taper angle is not also specifically determined, but is preferably 0.2°, and more preferably 1°. Also, in an aspect of the present disclosure, if the outer end portion of the first electrode layer of the Schottky electrode is located outside of the outer end portion of the second electrode layer, it is preferable that a distance between the outer end portion of the first electrode layer and the outer end portion of the second electrode layer be no less than 1 μm because such distance enables more curbing leak current. Also, in an aspect of the present disclosure, a part of the first electrode layer of the Schottky electrode, the part extending outward of the outer end portion of the second electrode layer (hereinafter also referred to an “extension part”), at least partially has a structure in which a film thickness decreases toward the outer side of the semiconductor element is preferable because such configuration enables providing more excellent voltage resistance of the semiconductor element. Also, combination of such preferable electrode configuration and the above-described preferable component materials of the semiconductor layer enables provision of a lower-loss semiconductor element with leak current more favorably curbed. 
     Embodiment 
     Preferable embodiments of the present disclosure will be described in more detail below with reference to the drawing, but the present disclosure is not limited to these embodiments. 
       FIG. 1  illustrates a major part of a Schottky barrier diode (SBD) as a semiconductor element that is a preferable embodiment of the present disclosure. The semiconductor element includes at least a semiconductor layer  101 , and a porous layer  108  disposed on a first surface side of the semiconductor layer  101  or a second surface side opposite from the first surface side, the porous layer  108  having a porosity of no more than 10%. The SBD in  FIG. 1  further includes an ohmic electrode  102 , a Schottky electrode  103  and a dielectric film  104 . The ohmic electrode  102  includes a metal layer  102   a , a metal layer  102   b  and a metal layer  102   c . The semiconductor layer  101  includes a first semiconductor layer  101   a  and a second semiconductor layer  101   b . The Schottky electrode  103  includes a metal layer  103   a , a metal layer  103   b  and a metal layer  103   c . The first semiconductor layer  101   a  includes, for example, an n−-type semiconductor layer and the second semiconductor layer  101   b  is, for example, an n+-type semiconductor layer. Also, the dielectric film  104  (hereinafter may be referred to as an “insulator film”) covers side surfaces of the semiconductor layer  101  (side surfaces of the first semiconductor layer  101   a  and side surfaces of the second semiconductor layer  101   b ) and includes an opening portion located on an upper surface of the semiconductor layer  101  (first semiconductor layer  101   a ). The opening portion is provided between a part of the first semiconductor layer  101   a  and the metal layer  103   c  of the Schottky electrode  103 . Also, in the preset embodiment, side surfaces of the semiconductor layer  101  are tapered. The dielectric film  104  may be provided in such a manner as to cover the tapered side surfaces of the semiconductor layer  101  and further cover a part of an upper surface of the semiconductor layer  101  (first semiconductor layer  101   a ). Note that the tapered side surfaces of the semiconductor layer  101  are inclined in such a manner as to extend from the first surface of the semiconductor layer  101  toward the second surface opposite from the first surface. In the semiconductor element in  FIG. 1 , the dielectric film  104  enables improvement of a crystal defect in an end portion, more favorable formation of a depletion layer, further enhancement of electric field relaxation and more favorable curbing of leak current. Note that in the present embodiment, the porous layer  108  is disposed on the ohmic electrode  102  (metal layer  102   c ), and the semiconductor element further includes a substrate  109  disposed on the porous layer  108 . 
     It is preferable that the dielectric film have a taper angle. A method of forming the taper angle is not specifically limited, and in the present disclosure, it is possible to form the taper angle with a publicly known method. Examples of a preferable method of forming the taper angle include, e.g., a method in which a thin film having an etching rate that is higher than that of the dielectric film is formed on the dielectric film, a resist is then applied to the thin film and the taper angle is formed by photolithography or etching. 
     Also, the taper angle of the dielectric film is preferably no more than 20°, and more preferably no more than 10°. In the present disclosure, a lower limit of the taper angle is not specifically determined, but is preferably 0.2°, more preferably 1.0°, and most preferably 2.2°. 
     In the present disclosure, it is preferable that the dielectric film cover entire side surfaces of an oxide semiconductor layer, enabling more favorable curbing of, e.g., diffusion of, e.g., oxygen. Also, in the present disclosure, it is preferable that the dielectric film cover at least a part of a first surface of the oxide semiconductor layer, enabling providing more favorable semiconductor characteristics such as voltage resistance. 
       FIG. 6  illustrates a major portion of a Schottky barrier diode (SBD) as a semiconductor element, which is a preferable embodiment of the present disclosure. The SBD in  FIG. 6  is different from the SBD in  FIG. 1  in including a tapered region in each side surface of the Schottky electrode  103 . In the semiconductor element in  FIG. 6 , outer end portions of a metal layer  103   b  and/or a metal layer  103   c , which correspond to a first metal layer, are located outside of an outer end portion of a metal layer  103   a , which corresponds to a second metal layer, enabling more favorably curbing leak current. Furthermore, parts of the metal layer  103   b  and/or the metal layer  103   c , the parts extending outside of the outer end portion of the metal layer  103   a , each include a tapered region having a film thickness decreasing toward the outer side of the semiconductor element, providing a configuration having more excellent voltage resistance. 
     Examples of a component material of the metal layer  103   a  include, e.g., the metals illustrated above as examples of the component material of the second electrode layer. Also, examples of component materials of the metal layer  103   b  and the metal layer  103   c  include, e.g., the metals illustrated above as examples of the component material of the first electrode layer. A method of forming each of the layers in  FIG. 1  is not specifically limited as long as such method does not hinder the present disclosure, and may be a publicly known method. Examples of the method include, e.g., a vacuum vapor deposition method, a CVD method, a sputtering method, a method in which a film is formed by any of various coating techniques and then patterned in a photolithography method and a method in which patterning is directly performed using, e.g., a printing technique. 
     A preferable process of manufacturing the SBD in  FIG. 1  will be described below; however, the present disclosure is not limited to these preferable manufacturing methods.  FIGS. 2 to 5  are diagram illustrating a mode of a preferable method of manufacturing a semiconductor element according to the present disclosure.  FIG. 2  provides illustration from a start with a stack  100   a  to obtainment of a stack  100   c .  FIG. 3  provides illustration from the stack  100   c  to obtainment of a stack  100   d .  FIG. 4  provides illustration from the stack  100   d  to obtainment of a stack  100   f .  FIG. 5  provides illustration from the stack  100   f  to obtainment of a stack  100   g . The stack  100   a  illustrated in  FIG. 2  is formed by stacking a first semiconductor layer  101   a  and a second semiconductor layer  101   b  above a crystal growth substrate (sapphire substrate)  110  with a stress relaxation layer  111  in between using the mist CVD method. A stack  100   b  is obtained by forming a metal layer  102   a , a metal layer  102   b  and a metal layer  102   c  as an ohmic electrode above the second semiconductor layer  101   b  of the stack  100   a  using the dry method or the wet method. The first semiconductor layer  101   a  is, for example, an n−-type semiconductor layer and the second semiconductor layer  101   b  is, for example, an n+-type semiconductor layer  101   b . Also, the stack  100   c  illustrated in  FIG. 2  is obtained by stacking a substrate  109  on the stack  100   b  with a porous layer  108  formed of a precious metal in between. Then, as illustrated in  FIG. 3 , the crystal growth substrate  110  and the stress relaxation layer  111  of the stack  100   c  are removed using a known removal method to obtain the stack  100   d . Then, as illustrated in  FIG. 4 , side surfaces of the semiconductor layer of the stack  100   d  are tapered by etching to obtain a stack  100   e , and then, an insulator film  104  is stacked on the tapered side surfaces and an upper surface, except a part corresponding to an opening portion, of the semiconductor layer to obtain a stack  100   f . Note that in the process of fabrication, an outer end portion of the insulator film  104  and an outer end portion of the metal layer  102   a  are formed in such a manner as to be stepped relative to outer end portions of layers below the insulator film  104  and the metal layer  102   a  (the metal layer  102   b , the metal layer  102   c , the porous layer  108  and the substrate  109 ); however, like the stack  100   e , the insulator film  104  may be stacked in such a manner as to form almost no step. Next, as illustrated in  FIG. 5 , metal layers  103   a ,  103   b  and  103   c  are formed as a Schottky electrode on a part of the upper surface of the semiconductor layer of the stack  100   f , the part corresponding to the opening portion, using the dry method or the wet method to obtain the stack  100   g . The semiconductor element obtained as described above has a configuration that enables favorable curbing of diffusion of, e.g., oxygen in the semiconductor layer, provision of excellent ohmic characteristics and improvement of a crystal defect at an end portion, more favorable forming of a depletion layer, further enhancement of electric field relaxation and more favorable curbing of leak current. When a prototype of the SBD of the above-described preferable embodiment was produced, it was confirmed with, e.g., a microscope that the dielectric film was stacked in a favorable manner on the semiconductor layer, there were no significant cracks, irregularities and the like, excellent flatness was achieved and there was no strain. Then, when a power cycle test of the prototype of the product of the present embodiment was conducted for performance evaluation, after completion of 3000 cycles in five minutes, a favorable evaluation result was obtained. Also, a confirmation with, e.g., SEM-EDS showed that, e.g., diffusion of, e.g., oxygen was curbed. Note that in the product of the present embodiment, as illustrated in  FIG. 8( b ) , a porous layer having a porosity of no more than 10% was used. 
     Also, as in the above description, in an SBD using a semiconductor layer  101  formed of an oxide semiconductor and a porous layer  108  formed of silver, also, no significant cracks, irregularities and the like occur, warpage is curbed and stress relaxation works favorably. 
     Also, at least the side surfaces of the oxide semiconductor layer being covered by the insulator film (dielectric film)  104  enables curbing, e.g., diffusion of oxygen by the oxide semiconductor, moisture absorption and an inflow of, e.g., oxygen in, e.g., air, enabling provision of favorable semiconductor characteristics. 
       FIG. 7  illustrates a major portion of a Schottky barrier diode (SBD) as a semiconductor element that is a preferable embodiment of the present disclosure. (Note that illustration of a porous layer  108  and a substrate  109  is omitted because the porous layer  108  and the substrate  109  are the same as those in  FIG. 6 .) Unlike the SBD in  FIG. 6 , in the SBD in  FIG. 7 , no tapered region is provided in each of side surfaces of a Schottky electrode  103  in  FIG. 1 , and an outer end portion of an insulator film  104  covering a semiconductor layer  101  and an outer end portion of an ohmic electrode  102  form no step and form a same end. Such configuration also enables expecting the advantageous effect of the present disclosure. 
     It is preferable that the semiconductor element be a vertical device, and among others, the semiconductor element is useful for a power device. Examples of the semiconductor element include, e.g., diodes (for example, a P-N diode, a Schottky barrier diode and a junction barrier Schottky diode) and transistors (for example, a MOSFET and a MESFET), and among others, diodes are preferable and a Schottky barrier diode (SBD) is more preferable. 
     In addition to the above matters, the semiconductor element of the present disclosure is further suitable for use as a semiconductor device by being bonded to, e.g., a lead frame, a circuit substrate or a heat dissipation substrate by a publicly known method, and particularly, is suitable for use as a power module, an inverter or a converter, and furthermore, is suitable for use in, for example, a semiconductor system using a power supply device.  FIG. 12  illustrates a preferable example of the semiconductor device. In the semiconductor device in  FIG. 12 , each of opposite surfaces of a semiconductor element  500  is bonded to a lead frame, circuit substrate or heat dissipation substrate  502  with a solder  501 . Such configuration enables provision of a semiconductor device having excellent heat dissipation performance. Note that in the present disclosure, it is preferable that the peripheries of the bonding members such as solders be encapsulated by resin. Such semiconductor device is also embraced in the present disclosure. 
     Also, it is possible to fabricate the power supply device from the semiconductor device or as the semiconductor device by connecting the semiconductor device to, e.g., a wiring pattern using a publicly known method. In  FIG. 9 , a power supply system  170  is configured using a plurality of the power supply devices  171 ,  172  and a control circuit  173 . As illustrated in  FIG. 10 , the power supply system is usable for a system device  180  in combination of an electronic circuit  181  and a power supply system  182 . Note that  FIG. 11  illustrates an example of a power supply circuit diagram of a power supply device.  FIG. 11  illustrates a power supply circuit of a power supply device formed of a power circuit and a control circuit, and a DC voltage is converted into an AC voltage by being switched at a high frequency by an inverter  192  (formed of MOSFETs A to D) and then, the AC voltage is subjected to insulation and transformation with a transformer  193  and rectified by rectifying MOSFETs  194  (A to B′), and then smoothed by a DCL  195  (smoothing coils L 1 , L 2 ) and a capacitor to output a direct-current voltage. At this time, the output voltage is compared with a reference voltage in a voltage comparator  197  and a PWM control circuit  196  controls the inverter  192  and the rectifying MOSFETs  194  so that the output voltage becomes a desired output voltage. 
     In the present disclosure, the semiconductor device is preferably a power card, more preferably includes coolers and insulating members, the coolers being provided on opposite sides of the semiconductor layer with at least the insulating members in between, respectively, and most preferably includes heat dissipation layers provided on the opposite sides of the semiconductor layer, respectively, the coolers being provided on respective outer sides of the heat dissipation layers with the insulating members in between, respectively.  FIG. 13  illustrates a power card, which is a preferable embodiment of the present disclosure. The power card in  FIG. 13  is a double-sided cooling-type power card  201  and includes refrigerant tubes  202 , spacers  203 , insulating plates (insulating spacers)  208 , a resin encapsulating portion  209 , a semiconductor chip  301   a , a metal heat transfer plate (projecting terminal portion)  302   b , a heatsink and electrode  303 , a metal heat transfer plate (projecting terminal portion)  303   b , solder layers  304 , a control electrode terminal  305  and a bonding wire  308 . A section in a thickness direction of the refrigerant tube  202  includes a multitude of flow channels  222  defined by a multitude of partitioning walls  221  extending in a flow channel direction in such a manner as to be spaced a predetermined distance from one another. Such preferable power card enables provision of higher heat dissipation performance and enables provision of higher reliability. 
     The semiconductor chip  301   a  is bonded to a principal surface on the inner side of the metal heat transfer plate  302   b  with a solder layer  304  and the metal heat transfer plate (projecting terminal portion)  302   b  is bonded to a remaining principal surface of the semiconductor chip  301   a  with a solder layer  304 . Consequently, an anode electrode surface and a cathode electrode surface of a flywheel diode are connected in what is called inverse-parallel to a collector electrode surface and an emitter electrode surface of an IGBT. Examples of materials of the metal heat transfer plates (projecting terminal portions)  302   b  and  303   b  include, e.g., Mo and W. The metal heat transfer plates (projecting terminal portions)  302   b  and  303   b  each have thickness variations that absorb thickness variations of the semiconductor chip  301   a , and consequently, each of respective outer surfaces of the metal heat transfer plates  302   b  and  303   b  is a flat surface. 
     The resin encapsulating portion  209  is formed of, for example, an epoxy resin and molded in such a manner as to cover side surfaces of the metal heat transfer plates  302   b  and  303   b , and the semiconductor chip  301   a  is molded by the resin encapsulating portion  209 . However, outer principal surfaces, that is, contact/heat receiving surfaces, of the metal heat transfer plate  302   b  and  303   b  are completely exposed. The metal heat transfer plates (projecting terminal portions)  302   b  and  303   b  project rightward from the resin encapsulating portion  209  in  FIG. 13 , and the control electrode terminal  305 , which is what is called a lead frame terminal, connects, for example, a gate (control) electrode surface of the semiconductor chip  301   a  with the IGBT formed therein and the control electrode terminal  305 . 
     The insulating plate  208 , which is an insulating spacer, is formed of, for example, an aluminum nitride film but may be formed of another insulating film. The insulating plates  208  are in close contact with the metal heat transfer plates  302   b  and  303   b  in such a manner as to completely cover the metal heat transfer plates  302   b  and  303   b , respectively; however, the insulating plates  208  and the metal heat transfer plates  302   b  and  303   b  may simply be in contact with each other, may be coated with a high thermally conductive material such as silicon grease or may be bonded by any of various methods, respectively. Also, insulating layers may be formed by ceramic spraying, for example, or the insulating plates  208  may be bonded to the metal heat transfer plates or may be bonded to or formed on refrigerant tubes, respectively. 
     The refrigerant tubes  202  are each fabricated by cutting a plate material into necessary lengths, the plate material being formed by molding an aluminum alloy by a pultrusion molding method or an extrusion molding method. A section in a thickness direction of each refrigerant tube  202  includes a multitude of flow channels  222  defined by a multitude of partitioning walls  221  extending in a flow channel direction in such a manner as to be spaced a predetermined distance from one another. Each of the spacers  203  may be, for example, a flexible metal plate of, e.g., a solder alloy or may be a film formed by, e.g., coating of contact surfaces of the metal heat transfer plates  302   b  and  303   b . A surface of each flexible spacer  203  easily deforms, and fits in minute bumps and dips and warpage of the corresponding insulating plate  208  and minute bumps and dips and warpage of the corresponding refrigerant tube  202 , resulting in decrease in thermal resistance. Note that, e.g., known high thermally conductive grease may be applied to, e.g., the surfaces of the spacers  203  or the spacers  203  may be omitted. 
     The semiconductor element of the present disclosure is usable in various fields of semiconductors (for example, compound semiconductor electronic devices, etc.), electronic components and electrical equipment components, optical and electronic photography-related devices, industrial members, etc., and particularly, is useful for a power device. 
     The embodiments of the present invention are exemplified in all respects, and the scope of the present invention includes all modifications within the meaning and scope equivalent to the scope of claims. 
     REFERENCE SIGNS LIST 
     
         
           101  Semiconductor layer 
           101   a  First semiconductor layer 
           101   b  Second semiconductor layer 
           102  Ohmic electrode 
           102   a  Metal layer 
           102   b  Metal layer 
           102   c  Metal layer 
           103  Schottky electrode 
           103   a  Metal layer 
           103   b  Metal layer 
           103   c  Metal layer 
           104  Insulator film (dielectric film) 
           108  Porous layer 
           109  Substrate 
           110  Crystal growth substrate 
           170  Power supply system 
           171  Power supply device 
           172  Power supply device 
           173  Control circuit 
           180  System device 
           181  Electronic circuit 
           182  Power supply system 
           192  Inverter 
           193  Transformer 
           194  Rectifying MOSFET 
           195  DCL 
           196  PWM control circuit 
           197  Voltage comparator 
           201  Double-sided cooling-type power card 
           202  Refrigerant tube 
           203  Spacer 
           208  Insulating plate (insulating spacer) 
           209  Resin encapsulating portion 
           221  Partitioning wall 
           222  Flow channel 
           301   a  Semiconductor chip 
           302   b  Metal heat transfer plate (projecting terminal portion) 
           303  Heatsink and electrode 
           303   b  Metal heat transfer plate (projecting terminal portion) 
           304  Solder layer 
           305  Control electrode terminal 
           308  Bonding wire 
           500  Semiconductor element 
           501  Solder 
           502  Lead frame, circuit substrate or heat dissipation substrate