Patent Publication Number: US-2021174179-A1

Title: Arithmetic apparatus, operating method thereof, and neural network processor

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application claims the benefit of Korean Patent Application No. 10-2019-0161679, filed on Dec. 6, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety. 
     BACKGROUND 
     1. Field 
     The application relates to an arithmetic apparatus, an operating method thereof, and a neural network processor. More particularly, embodiments of the application relate to an arithmetic circuit performing an operation, such as a convolution operation, using operands, an operating method thereof, and a neural network processor performing the same. 
     2. Description of Related Art 
     A neural network refers to a computational architecture modeled after a biological brain. As neural network technology has recently developed, research has increasingly analyzed using a neural network device, which implements one neural network model, in various kinds of electronic systems. 
     A neural network device needs to perform a large amount of computations on complex input data, which requires significant power consumption. Therefore, a technique for allowing an arithmetic apparatus, like a neural network device, to efficiently and quickly perform computations with reduced power consumption when analyzing input data in real time and extracting information is desirable. 
     SUMMARY 
     Embodiments of the application relate to a method for reducing power consumption of operations of an arithmetic apparatus using operands. 
     According to an aspect of an embodiment, there is provided an arithmetic apparatus including a first operand holding circuit configured to generate an indicator signal based on bit values of high-order bit data of a first operand input to the first operand holding circuit, the high-order bit data of the first operand including a most significant bit of the first operand, gate a clock signal input to the first operand holding circuit based on the indicator signal, to generate a gated clock signal, generate latched high-order bit data of the first operand based on the gated clock signal being applied to a flip-flop latching the high-order bit data of the first operand, and output bit data of the first operand, the bit data of the first operand comprising the latched high-order bit data of the first operand and low-order bit data of the first operand; a second operand holding circuit configured to output a second operand input to the second operand holding circuit based on the clock signal; and an arithmetic circuit configured to perform data gating on the latched high-order bit data of the first operand based on the indicator signal, to generate data-gated high-order bit data of the first operand and output an operation result by performing an operation using a modified first operand comprising the data-gated high-order bit data of the first operand and the low-order bit data of the first operand and the second operand. 
     According to another aspect of an embodiment, there is provided an arithmetic apparatus including a first operand holding circuit configured to output a first operand holding circuit configured to output a modified first operand based on a clock signal, the first modified first operand comprising high-order bit data of a first operand input to the first operand holding circuit and low-order bit data of the first operand; a second operand holding circuit configured to output a second operand input to the second holding circuit based on the clock signal; and an arithmetic circuit configured to output an operation result by performing an operation using the modified first operand and the second operand, wherein the arithmetic circuit includes a first clock gating circuit configured to generate a first gated clock signal by selectively passing the clock signal based on values of the high-order bit data of the first operand; a first flip-flop configured to latch the high-order bit data of the first operand based on the first gated clock signal; and a second flip-flop configured to latch the low-order bit data of the first operand based on the clock signal. 
     According to an aspect of an embodiment, there is provided a neural network processor for accelerating a neural network. The neural network processor includes an input feature holding circuit configured to output an input feature value based on a clock signal, to generate an indicator signal based on input feature high-order bit data corresponding to high-order bit values of a predetermined number of bits in the input feature value, and to gate the clock signal according to a logic level of the indicator signal, the clock signal being applied to a first flip-flop latching the input feature high-order bit data; a weight holding circuit configured to output a weight value according to the clock signal; and an arithmetic circuit configured to perform data gating on the input feature high-order bit data according to a logic level of the indicator signal and output an operation result by performing multiplication and accumulation using a modified input feature value resulting from the data gating and the weight value. 
     According to an aspect of an embodiment, there is provided a neural network processor for accelerating a neural network. The neural network processor includes a weight holding circuit configured to output a weight value based on a clock signal, generate an indicator signal based on weighted high-order bit data corresponding to high-order bit values of a predetermined number of bits in the weight value, and gate the clock signal according to a logic level of the indicator signal, the clock signal being applied to a first flip-flop latching the weighted high-order bit data; an input feature holding circuit configured to output an input feature value based on the clock signal; and an arithmetic circuit configured to perform data gating on the weight high-order bit data based on the logic level of the indicator signal and output an operation result by performing multiplication and accumulation using a modified weighted value resulting from the data gating and the input feature value. 
     According to an aspect of an embodiment, there is provided an operating method of an arithmetic apparatus. The operating method includes generating an indicator signal based on bit values of high-order bit data of a first operand; gating a clock signal based on a logic level of the indicator signal, the clock signal being applied to a flip-flop corresponding to the high-order bit data of the first operand; performing data gating on the high-order bit data of the first operand based on the logic level of the indicator signal; and outputting an operation result by performing an operation using a modified first operand resulting from the data gating and a second operand. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Embodiments of the application will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings in which: 
         FIG. 1  illustrates an arithmetic apparatus according to an embodiment; 
         FIG. 2  illustrates a first operand holding circuit according to an embodiment; 
         FIG. 3  illustrates an arithmetic circuit according to an embodiment; 
         FIG. 4  illustrates an arithmetic circuit according to an embodiment; 
         FIG. 5  illustrates a clock gating circuit according to an embodiment; 
         FIG. 6  illustrates a data gating circuit according to an embodiment; 
         FIG. 7  illustrates a calculation circuit according to an embodiment; 
         FIGS. 8A and 8B  illustrate multiplication circuits, respectively, according to embodiments; 
         FIG. 9  is a flowchart of an operating method of an arithmetic apparatus, according to an embodiment; 
         FIG. 10  illustrates an arithmetic apparatus according to an embodiment; 
         FIGS. 11A and 11B  illustrate multiplication circuits, respectively, according to embodiments; 
         FIG. 12  illustrates an electronic system according to an embodiment; 
         FIG. 13  illustrates a neural network processor according to an embodiment; 
         FIG. 14  illustrates a neural network processor according to an embodiment; and 
         FIG. 15  illustrates a neural network processor according to an embodiment. 
     
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
     Hereinafter, embodiments will be described in detail with reference to the attached drawings. 
       FIG. 1  illustrates an arithmetic apparatus  10  according to an embodiment. The arithmetic apparatus  10  may be implemented in any device that performs a computational operation using an operand. The operation may include at least one of various operations. For example, the operation may include a mathematical operation such as multiplication, addition, or convolution, at least one logical operation, or a combination of a mathematical operation and a logical operation. In an embodiment, the arithmetic apparatus  10  may be applied to a neural network processor that performs convolution. 
     The arithmetic apparatus  10  may include a first operand holding circuit  100 , a second operand holding circuit  200 , and an arithmetic circuit  300 . 
     The first operand holding circuit  100  may store a first operand and may output the first operand according to a clock signal CK. For example, the first operand holding circuit  100  may output the first operand at a rising edge and/or a falling edge of the clock signal CK. In other words, the first operand holding circuit  100  may output the first operand synchronized with a rising edge and/or a falling edge of the clock signal CK. 
     The first operand may include first high-order bit data OP 1 _HO and first low-order bit data OP 1 _LO. For example, the first high-order bit data OP 1 _HO may include a predetermined number of high-order bit values of the first operand expressed as a binary number, and the first low-order bit data OP 1 _LO may include the other bit values of the first operand, excluding the first high-order bit data OP 1 _HO. As a non-limiting example for convenience of description, the first operand may be 8-bit data, the first high-order bit data OP 1 _HO may be high-order 4-bit data of the first operand, and the first low-order bit data OP 1 _LO may be low-order 4-bit data. 
     In an embodiment, the first operand holding circuit  100  may generate an indicator signal HZI based on the bit values of the first high-order bit data OP 1 _HO and may provide the indicator signal HZI to the arithmetic circuit  300 . The indicator signal HZI may indicate whether all bit values of the first high-order bit data are “0.” For example, when all bit values of the first high-order bit data are “0,” the indicator signal HZI may have a first logic level (e.g., “0”), and when at least one of the bit values of the first high-order bit data is not “0,” the indicator signal HZI may have a second logic level (e.g., “1”), which is different from the first logic level. In other words, the first operand holding circuit  100  may monitor the high-order bit values of the first operand to output the indicator signal HZI. 
     In an embodiment, the first operand holding circuit  100  may include a first flip-flop, which latches the first high-order bit data OP 1 _HO, and a second flip-flop, which latches the first low-order bit data OP 1 _LO. The first operand holding circuit  100  may perform clock gating on the clock signal CK, which is applied to the first flip-flop, according to the logic level of the indicator signal HZI. In other words, the first operand holding circuit  100  may generate a gated clock signal by selectively passing the clock signal CK based on the logic level of the indicator signal HZI and may provide the gated clock signal to the first flip-flop. The first flip-flop may latch the first high-order bit data OP 1 _HO according to the gated clock signal and output latched first high-order bit data OP 1 _HO_L. The first operand holding circuit  100  may provide the latched first high-order bit data OP 1 _HO_L, the indicator signal HZI, and the first low-order bit data OP 1 _LO to the arithmetic circuit  300 . 
     The second operand holding circuit  200  may store a second operand OP 2  and may output the second operand OP 2  according to the clock signal CK. For example, the second operand holding circuit  200  may output the second operand OP 2  at a rising edge and/or a falling edge of the clock signal CK. In other words, the second operand holding circuit  200  may output the second operand OP 2  synchronized with the rising edge and/or the falling edge of the clock signal CK. 
     The arithmetic circuit  300  may perform an operation taking the first operand and the second operand OP 2  as input values, and output an operation result RES. 
     In an embodiment, the arithmetic circuit  300  may perform data gating on the latched first high-order bit data OP 1 _HO_L according to the logic level of the indicator signal HZI. For example, the arithmetic circuit  300  may selectively pass the latched first high-order bit data OP 1 _HO_L based on the logic level of the indicator signal HZI to be used in an operation. To implement such functionality, the arithmetic circuit  300  may include a data gating circuit, which will be described in detail with reference to  FIG. 3 . 
     In an embodiment, the arithmetic circuit  300  may include a third flip-flop, which latches the latched first high-order bit data OP 1 _HO_L, and a fourth flip-flop, which latches the first low-order bit data OP 1 _LO. The arithmetic circuit  300  may also perform clock gating on the clock signal CK, which is applied to the third flip-flop, according to the logic level of the indicator signal HZI. In other words, the arithmetic circuit  300  may generate a gated clock signal by selectively passing the clock signal CK based on the logic level of the indicator signal HZI and may provide the gated clock signal to the third flip-flop. The third flip-flop may latch the latched first high-order bit data OP 1 _HO_L according to the gated clock signal. 
     The arithmetic circuit  300  may perform an operation using the second operand OP 2  and a modified first operand, which results from at least one selected from the clock gating of the first operand holding circuit  100 , the clock gating of the arithmetic circuit  300 , and the data gating of the arithmetic circuit  300 . The arithmetic circuit  300  may output the operation result RES. In an embodiment, the operation may include convolution, and more specifically multiplication and accumulation. In an embodiment, the arithmetic circuit  300  may include a calculation circuit including a multiplication circuit and an accumulation circuit. The arithmetic circuit  300  will be described in detail with reference to  FIGS. 3, 4, 7, 8A and 8B . 
     According to an embodiment, the arithmetic apparatus  10  may perform clock gating on a clock signal, which is applied to a flip-flop related to first high-order bit data of a first operand. For example, when all bit values of the first high-order bit data are “0,” the arithmetic apparatus  10  may perform clock gating such that the clock signal is not applied to the flip-flop that latches the first high-order bit data, thereby eliminating unnecessary transition of a signal in a signal line that transmits the first high-order bit data. As the amount of unnecessary signal transitions decreases, the power consumption of the arithmetic apparatus  10  may be decreased. 
     In addition, the arithmetic apparatus  10  may perform data gating on the first high-order bit data of the first operand. For example, when the bit values of the first high-order bit data are all “0,” the arithmetic apparatus  10  may perform data gating such that the first high-order bit data is not transmitted to a calculation circuit, thereby eliminating unnecessary transition of a signal in a signal line that transmits the first high-order bit data. As the amount of unnecessary signal transitions decreases, the power consumption of the arithmetic apparatus  10  may be decreased. 
       FIG. 2  illustrates the first operand holding circuit  100  according to an embodiment.  FIG. 2  will be described with reference to  FIG. 1 . 
     The first operand holding circuit  100  may include a first operand buffer  110 , a high-order bit zero determination circuit  120 , a clock gating circuit  130 , a low-order bit flip-flop  140 , and a high-order bit flip-flop  150 . 
     The first operand buffer  110  may store a first operand OP 1 . The first operand buffer  110  may provide the first operand OP 1  to the high-order bit zero determination circuit  120 . The first operand OP 1  may include first high-order bit data OP 1 _HO and the first low-order bit data OP 1 _LO according to the expression of a binary number. The first high-order bit data OP 1 _HO may include a predetermined number of high-order bit values of the first operand OP 1 , and the first low-order bit data OP 1 _LO may include the other bit values of the first operand OP 1 , excluding the first high-order bit data OP 1 _HO. The first operand buffer  110  may provide the first low-order bit data OP 1 _LO to the low-order bit flip-flop  140  and the first high-order bit data OP 1 _HO to the high-order bit flip-flop  150 . 
     The high-order bit zero determination circuit  120  may analyze the high-order bit values of the first operand OP 1  to output the indicator signal HZI. In an embodiment, the high-order bit zero determination circuit  120  may monitor the first high-order bit data OP 1 _HO included in the first operand OP 1 . For example, when all bit values of the first high-order bit data OP 1 _HO are “0,” the high-order bit zero determination circuit  120  may generate the indicator signal HZI having a first logic level (e.g., “0”). Similarly, when at least one of the bit values of the first high-order bit data OP 1 _HO is not “0,” the high-order bit zero determination circuit  120  may generate the indicator signal HZI having a second logic level (e.g., “1”). The high-order bit zero determination circuit  120  may provide the indicator signal HZI to the clock gating circuit  130  and output the indicator signal HZI to the first operand holding circuit  100 . 
     The clock gating circuit  130  may perform clock gating on the clock signal CK. The gated clock signal GCK is applied to the high-order bit flip-flop  150 , based on the indicator signal HZI. For example, the clock gating circuit  130  may perform clock gating on the clock signal CK using the indicator signal HZI as an enable (EN) signal. For example, the clock gating circuit  130  may generate a gated clock signal GCK by selectively passing the clock signal CK according to the logic level of the indicator signal HZI. For example, the clock gating circuit  130  may not pass the clock signal CK in response to the first logic level of the indicator signal HZI and may output the clock signal CK as the gated clock signal GCK in response to the second logic level of the indicator signal HZI. As a non-limited example, when the clock signal CK is not passed, the gated clock signal GCK may continuously have a value of “0.” The clock gating circuit  130  may provide the gated clock signal GCK to the high-order bit flip-flop  150 . An example of the clock gating circuit  130  will be described with reference to  FIG. 5 . 
     The low-order bit flip-flop  140  may latch the first low-order bit data OP 1 _LO according to the clock signal CK. To implement such functionality, the low-order bit flip-flop  140  may include various kinds and configurations of flip-flops or latches. However, embodiments are not limited thereto. The low-order bit flip-flop  140  may be replaced by various kinds of memory, registers, or other mechanisms storing a plurality of bits. 
     The high-order bit flip-flop  150  may latch the first high-order bit data OP 1 _HO according to the gated clock signal GCK. In other words, the high-order bit flip-flop  150  may output the first high-order bit data OP 1 _HO at a rising edge and/or a falling edge of the gated clock signal GCK. The high-order bit flip-flop  150  may output the latched first high-order bit data OP 1 _HO_L. To implement such functionality, the high-order bit flip-flop  150  may include various kinds and configurations of flip-flops or latches. However, embodiments are not limited thereto. The high-order bit flip-flop  150  may be replaced by various kinds of memory storing a plurality of bits. 
     When the gated clock signal GCK has a value of “0” according to the second logic level of the indicator signal HZI, the latched first high-order bit data OP 1 _HO_L output from the high-order bit flip-flop  150  may remain at a same or constant value without being updated to a new value. 
     According to an embodiment, the first operand holding circuit  100  may perform clock gating on the clock signal CK, which is applied to the high-order bit flip-flop  150  related to the first high-order bit data OP 1 _HO of the first operand OP 1 . For example, when all bit values of the first high-order bit data OP 1 _HO are “0,” the clock gating circuit  130  may perform clock gating such that the clock signal CK is not applied to the high-order bit flip-flop  150 , thereby eliminating unnecessary transition of a signal in a signal line that transmits the first high-order bit data. As the amount of unnecessary signal transitions decreases, the power consumption of the first operand holding circuit  100  and the arithmetic apparatus  10  may be decreased. 
       FIG. 3  illustrates the arithmetic circuit  300  according to an embodiment.  FIG. 3  will be described with reference to  FIG. 1 . 
     The arithmetic circuit  300  may include a data gating circuit  320  and a calculation circuit  340 . 
     The data gating circuit  320  may perform data gating on the latched first high-order bit data OP 1 _HO_L based on the indicator signal HZI. In other words, the data gating circuit  320  may selectively pass the latched first high-order bit data OP 1 _HO_L according to the logic level of the indicator signal HZI. For example, the data gating circuit  320  may output the latched first high-order bit data OP 1 _HO_L as data-gated first high-order bit data OP 1 _HO_DG in response to the first logic level of the indicator signal HZI, and may output “0” as the data-gated first high-order bit data OP 1 _HO_DG in response to the second logic level of the indicator signal HZI. To implement such functionality, the data gating circuit  320  may include an AND gate performing a logical AND operation using the indicator signal HZI and the latched first high-order bit data OP 1 _HO_L. This will be described in detail with reference to  FIG. 6 . The data gating circuit  320  may provide the data-gated first high-order bit data OP 1 _HO_DG to the calculation circuit  340 . 
     The calculation circuit  340  may perform an operation using a modified first operand, which results from the clock gating of the first operand holding circuit  100  and/or the data gating of the arithmetic circuit  300 , and a second operand, and may output the operation result RES. For example, the calculation circuit  340  may perform an operation using the second operand OP 2  and the modified first operand including the data-gated first high-order bit data OP 1 _HO_DG and the first low-order bit data OP 1 _LO, and may output the operation result RES. Various examples of the calculation circuit  340  will be described in detail with reference to  FIGS. 7 through 8B . 
     According to an embodiment, the arithmetic circuit  300  may perform data gating on the latched first high-order bit data OP 1 _HO_L. For example, when all bit values of first high-order bit data are “0,” the data gating circuit  320  may perform data gating such that the latched first high-order bit data OP 1 _HO_L is not transmitted to the calculation circuit  340 , thereby eliminating unnecessary transition of a signal in a signal line that transmits the first high-order bit data. As the amount of unnecessary signal transitions decreases, the power consumption of the arithmetic circuit  300  and the arithmetic apparatus  10  may be decreased. 
       FIG. 4  illustrates the arithmetic circuit  300  according to an embodiment.  FIG. 4  will be described with reference to  FIG. 1 . 
     The arithmetic circuit  300  may include a clock gating circuit  305 , a high-order bit flip-flop  310 , a low-order bit flip-flop  315 , the data gating circuit  320 , and the calculation circuit  340 . The data gating circuit  320  may operate substantially in a manner similar to the data gating circuit  320  in  FIG. 3 , and the calculation circuit  340  may operate substantially a manner similar to the calculation circuit  340  in  FIG. 3 . Accordingly, redundant descriptions thereof will be omitted. 
     The clock gating circuit  305  may perform clock gating on the clock signal CK, which is applied to the high-order bit flip-flop  310 , based on the indicator signal HZI. For example, the clock gating circuit  305  may perform clock gating on the clock signal CK using the indicator signal HZI as an enable (EN) signal. For example, the clock gating circuit  305  may generate a gated clock signal GCK 2  by selectively passing the clock signal CK according to the logic level of the indicator signal HZI. For example, the clock gating circuit  305  may not pass the clock signal CK in response to the first logic level of the indicator signal HZI and may output the clock signal CK as the gated clock signal GCK 2  in response to the second logic level of the indicator signal HZI. As a non-limited example, when the clock signal CK is not passed, the gated clock signal GCK 2  may continuously have a value of “0.” The clock gating circuit  305  may provide the gated clock signal GCK 2  to the high-order bit flip-flop  310 . An example of the clock gating circuit  305  will be described with reference to  FIG. 5 . 
     The high-order bit flip-flop  310  may latch the latched first high-order bit data OP 1 _HO_L according to the gated clock signal GCK 2 . In other words, the high-order bit flip-flop  310  may output the latched first high-order bit data OP 1 _HO_L at a rising edge and/or a falling edge of the gated clock signal GCK 2 . The high-order bit flip-flop  310  may provide latched first high-order bit data OP 1 _HO_L to the data gating circuit  320 . To implement such functionality, the high-order bit flip-flop  310  may include various kinds and configurations of flip-flops or latches. However, embodiments are not limited thereto. The high-order bit flip-flop  310  may be replaced by various kinds of memory storing a plurality of bits. 
     The low-order bit flip-flop  315  may latch the first low-order bit data OP 1 _LO according to the clock signal CK. To implement such functionality, the low-order bit flip-flop  315  may include various kinds of flip-flops or latches. However, embodiments are not limited thereto. The low-order bit flip-flop  315  may be replaced by various kinds of memory storing a plurality of bits. 
     When the gated clock signal GCK 2  has a value of “0” according to the second logic level of the indicator signal HZI, the latched first high-order bit data OP 1 _HO_L output from the high-order bit flip-flop  310  may remain at a constant value without being updated to a new value. 
     According to an embodiment, the arithmetic circuit  300  may perform clock gating on the clock signal CK applied to the high-order bit flip-flop  310 . For example, when all bit values of the first high-order bit data OP 1 _HO are “0,” the clock gating circuit  305  may perform clock gating such that the clock signal CK is not applied to the high-order bit flip-flop  310 , thereby eliminating unnecessary transition of a signal in a signal line that transmits the latched first high-order bit data OP 1 _HO_L. As the amount of unnecessary signal transitions decreases, the power consumption of the arithmetic circuit  300  and the arithmetic apparatus  10  may be correspondingly decreased. 
       FIG. 5  illustrates a clock gating circuit  50  according to an embodiment. The clock gating circuit  50  may correspond to the clock gating circuit  130  in  FIG. 2  and the clock gating circuit  305  in  FIG. 4 . 
     The clock gating circuit  50  may include a latch circuit  51  and an AND gate  52 . 
     The latch circuit  51  may latch the clock signal CK according to an enable signal EN. The latch circuit  51  may receive the indicator signal HZI as the enable signal HZI(EN). The latch circuit  51  may provide a latched clock signal to a first input terminal of the AND gate  52  according to the indicator signal HZI. 
     The AND gate  52  may output the gated clock signal GCK by performing a logical AND operation using the clock signal CK and the latched clock signal received from the latch circuit  51 . To implement such functionality, the latched clock signal may be input to the first input terminal of the AND gate  52  and the clock signal CK may be input to a second input terminal of the AND gate  52 . 
     Although  FIG. 5  illustrates an example of the clock gating circuit  50 , embodiments are not limited thereto. The clock gating circuit  50  may include various types of circuits that perform the same function (i.e., a function of selectively passing the clock signal CK according to the indicator signal HZI). 
       FIG. 6  illustrates the data gating circuit  320  according to an embodiment. The data gating circuit  320  may correspond to the data gating circuit  320  in  FIGS. 3 and 4 . 
     The data gating circuit  320  may include at least one AND gate. For example, the data gating circuit  320  may include first through m-th AND gates  322 _ 1 , and  322 _ 2  through  322 _ m . Here, “m” may be the number of bits in the latched first high-order bit data OP 1 _HO_L. In other words, at least one AND gate may perform a logical AND operation using the indicator signal HZI and a value of each bit in the latched first high-order bit data OP 1 _HO_L. 
     At least one AND gate may output the data-gated first high-order bit data OP 1 _HO_DG by performing a logical AND operation using the indicator signal HZI and the latched first high-order bit data OP 1 _HO_L. For example, when the indicator signal HZI indicates a first logic level (e.g., “0”), the AND gate may output “0.” Similarly, when the indicator signal HZI indicates a second logic level (e.g., “1”), the AND gate may output the latched first high-order bit data OP 1 _HO_L as the data-gated first high-order bit data OP 1 _HO_DG. 
     Although  FIG. 6  illustrates an example of the data gating circuit  320 , embodiments are not limited thereto. The data gating circuit  320  may include various types of circuits that perform the same function (i.e., a function of selectively passing the latched first high-order bit data OP 1 _HO_L according to the indicator signal HZI). 
       FIG. 7  illustrates the calculation circuit  340  according to an embodiment. In particular, the calculation circuit  340  may correspond to an embodiment in which the arithmetic circuit  300  in  FIG. 1  performs convolution using a first operand or a first operand set including the first operand and a second operand or a second operand set including the second operand OP 2 . The convolution may be implemented by multiplication and accumulation (adding up, summation) of operands.  FIG. 7  will be described with reference to  FIGS. 1 and 3 . 
     The calculation circuit  340  may include a multiplication circuit  342  and an accumulation circuit  349 . 
     The multiplication circuit  342  may perform multiplication using the second operand OP 2  and a modified first operand including the data-gated first high-order bit data OP 1 _HO_DG and the first low-order bit data OP 1 _LO. The multiplication circuit  342  may output a multiplication result RES_M. The multiplication circuit  342  may provide the multiplication result RES_M to the accumulation circuit  349 . The multiplication circuit  342  may be implemented by examples described with respect to  FIGS. 8A and 8B . 
     The accumulation circuit  349  may accumulate a plurality of values of the multiplication result RES_M output by the multiplication circuit  342 . The accumulation circuit  349  may output the operation result RES by adding up the plurality of accumulated multiplication results RES_M with respect to a first operand set including a first operand and a second operand set including a second operand. To implement such functionality, the accumulation circuit  349  may include a memory, such as a buffer or register, which stores the multiplication result RES_M, and an adder, which adds up a plurality of multiplication results. The accumulation circuit  349  may individually store a plurality of multiplication results and then generate the operation result RES by adding up the multiplication results, but embodiments are not limited thereto. The accumulation circuit  349  may update a temporary sum value each time the multiplication result RES_M is received and may output a lastly updated sum value as the operation result RES. 
       FIGS. 8A and 8B  illustrate multiplication circuits  342   a  and  342   b , respectively, according to embodiments. The multiplication circuits  342   a  and  342   b  may correspond to the multiplication circuit  342  in  FIG. 7 . Additionally,  FIGS. 8A and 8B  will be described with reference to  FIGS. 1 through 3  and  FIG. 7 . 
     Referring to  FIG. 8A , the multiplication circuit  342   a  may include a first operand register  343   a , a second operand register  345   a , a multiplier  346   a , and an output register  348   a.    
     The first operand register  343   a  may temporarily store and output a modified first operand OP 1 _M. The modified first operand OP 1 _M may include the data-gated first high-order bit data OP 1 _HO_DG and the first low-order bit data OP 1 _LO. For example, the modified first operand OP 1 _M may be formed by adding, as a high-order bit, the data-gated first high-order bit data OP 1 _HO_DG to the first low-order bit data OP 1 _LO. 
     In detail, for example, when the indicator signal HZI has the first logic level, the data-gated first high-order bit data OP 1 _HO_DG may be “0,” and accordingly, the modified first operand OP 1 _M may be formed by adding “0” as a high-order bit to the first low-order bit data OP 1 _LO. For example, when each of the first high-order bit data OP 1 _HO and the first low-order bit data OP 1 _HO_DG is 4-bit data and the indicator signal HZI has the first logic level, the modified first operand OP 1 _M may be formed by adding “0000” as high-order bits to the first low-order bit data OP 1 _LO. 
     When the indicator signal HZI has the second logic level, the data-gated first high-order bit data OP 1 _HO_DG may be the same as the first high-order bit data OP 1 _HO. Accordingly, the modified first operand OP 1 _M may be the same as data, i.e., the first operand OP 1 , formed by adding the first high-order bit data OP 1 _HO to the first low-order bit data OP 1 _LO. 
     The second operand register  345   a  may temporarily store and output the second operand OP 2 . 
     The multiplier  346   a  may generate the multiplication result RES_M by performing multiplication using the modified first operand OP 1 _M and the second operand OP 2 . For example, when each of the first operand OP 1  and the second operand OP 2  is 8-bit data, the multiplier  346   a  may include an 8×8-bit multiplier or a 9×9-bit multiplier. 
     The output register  348   a  may temporarily store the multiplication result RES_M and may output the multiplication result RES_M as output (e.g., to the accumulation circuit  349 ) of the multiplication circuit  342   a.    
     Referring to  FIG. 8B , the multiplication circuit  342   b  may include a first operand low-order bit register  343 _ 1   b , a first operand high-order bit register  343 _ 2   b , a second operand register  345   b , a first multiplier  346 _ 1   b , a second multiplier  346 _ 2   b , an adder  346 _ 3   b , a shifter  347   b , and an output register  348   b.    
     The first operand low-order bit register  343 _ 1   b  may temporarily store the first low-order bit data OP 1 _LO. The first operand high-order bit register  343 _ 2   b  may temporarily store the data-gated first high-order bit data OP 1 _HO_DG. The second operand register  345   b  may temporarily store the second operand OP 2 . 
     The first multiplier  346 _ 1   b  may output a first multiplication result M 1  by multiplying the first low-order bit data OP 1 _LO by the second operand OP 2 . For example, when the first low-order bit data OP 1 _LO is 4-bit data and the second operand OP 2  is 8-bit data, the first multiplier  346 _ 1   b  may include a 4×8-bit multiplier or a 5×9-bit multiplier. 
     The second multiplier  346 _ 2   b  may output a second multiplication result M 2  by multiplying the data-gated first high-order bit data OP 1 _HO_DG by the second operand OP 2 . For example, when the first high-order bit data OP 1 _HO is 4-bit data and the second operand OP 2  is 8-bit data, the second multiplier  346 _ 2   b  may include a 4×8-bit multiplier or a 5×9-bit multiplier. 
     The shifter  347   b  may output a shifted second multiplication result M 2 _S by shifting the second multiplication result M 2  by the number of bits in the first low-order bit data OP 1 _LO. 
     The adder  346 _ 3   b  may output the multiplication result RES_M by adding the multiplication result M 1  to the shifted second multiplication result M 2 _S. 
     The output register  348   b  may temporarily store the multiplication result RES_M and output the multiplication result RES_M as output (e.g., to the accumulation circuit  349 ) of the multiplication circuit  342   b.    
       FIG. 9  is a flowchart of an operating method of an arithmetic apparatus, according to an embodiment.  FIG. 9  will be described with reference to  FIGS. 1 through 8 . 
     The arithmetic apparatus  10  may generate the indicator signal HZI based on high-bit values of the first operand OP 1  in operation SI 20 . For example, the high-order bit zero determination circuit  120  of the first operand holding circuit  100  may monitor the first high-order bit data OP 1 _HO including high-order bit values included in the first operand OP 1  and may generate the indicator signal HZI indicating whether all bit values of the first high-order bit data OP 1 _HO are a same value (e.g., “0”). 
     The arithmetic apparatus  10  may gate the clock signal CK, which is applied to a flip-flop related to the first high-order bit data OP 1 _HO, based on the indicator signal HZI in operation S 140 . For example, the clock gating circuit  130  of the first operand holding circuit  100  may gate the clock signal CK, which is applied to the high-order bit flip-flop  150 , based on the logic level of the indicator signal HZI. Similarly, for example, the clock gating circuit  305  of the arithmetic circuit  300  may gate the clock signal CK, which is applied to the high-order bit flip-flop  310 , based on the logic level of the indicator signal HZI. 
     The arithmetic apparatus  10  may perform data gating on the first high-order bit data OP 1 _HO based on the indicator signal HZI in operation S 160 . For example, the data gating circuit  320  of the arithmetic circuit  300  may generate the data-gated first high-order bit data OP 1 _HO_DG by gating the latched first high-order bit data OP 1 _HO_L based on the logic level of the indicator signal HZI. 
     The arithmetic apparatus  10  may output the operation result RES by performing an operation using the modified first operand OP 1 _M and the second operand OP 2  in operation S 180 . The modified first operand OP 1 _M may include the data-gated first high-order bit data OP 1 _HO_DG and the first low-order bit data OP 1 _LO. 
       FIG. 10  illustrates an arithmetic apparatus  20  according to an embodiment. The arithmetic apparatus  20  may include the first operand holding circuit  100 , the second operand holding circuit  200 , and the arithmetic circuit  300 .  FIG. 10  will be described focusing on the differences between the arithmetic apparatus  20  and the arithmetic apparatus  10  described with reference to  FIGS. 1 through 9 . 
     The first operand holding circuit  100  may be substantially the same as the first operand holding circuit  100  described with reference to  FIGS. 1 through 9 . However, the indicator signal HZI in  FIGS. 1 through 9  is renamed a first indicator signal HZI_ 1 . 
     Unlike the second operand holding circuit  200  outputting the second operand OP 2  in  FIGS. 1 through 9 , the second operand holding circuit  200  in  FIG. 10  may output a second indicator signal HZI_ 2 , latched second high-order bit data OP 2 _HO_L, and second low-order bit data OP 2 _LO, like the first operand holding circuit  100  in  FIGS. 1 through 9 . 
     In other words, a second operand may include second high-order bit data and the second low-order bit data OP 2 _LO. For example, the second high-order bit data may include a predetermined number of high-order bit values of the second operand expressed as a binary number, and the second low-order bit data OP 2 _LO may include the other bit values of the second operand, excluding the second high-order bit data. 
     In an embodiment, the second operand holding circuit  200  may generate the second indicator signal HZI_ 2  based on the bit values of the second high-order bit data OP 2 _HO and may provide the second indicator signal HZI_ 2  to the arithmetic circuit  300 . The second indicator signal HZI_ 2  may indicate whether all bit values of the second high-order bit data are the same value (e.g., “0”). For example, when all bit values of the second high-order bit data are “0,” the second indicator signal HZI_ 2  may have a first logic level (e.g., “0”), and when at least one of the bit values of the second high-order bit data is not “0,” the second indicator signal HZI_ 2  may have a second logic level (e.g., “1”), which is different from the first logic level. In other words, the second operand holding circuit  200  may monitor the high-order bit values of the second operand to output the second indicator signal HZI_ 2 . 
     In an embodiment, the second operand holding circuit  200  may include a high-order bit flip-flop, which latches the second high-order bit data OP 2 _HO to generate the latched second high-order bit data OP 2 _HO_L, and a low-order bit flip-flop, which latches the second low-order bit data OP 2 _LO. The second operand holding circuit  200  may perform clock gating on the clock signal CK, which is applied to the high-order bit flip-flop, according to the logic level of the second indicator signal HZI_ 2 . In other words, the second operand holding circuit  200  may generate a gated clock signal by selectively passing the clock signal CK based on the logic level of the second indicator signal HZI_ 2  and may provide the gated clock signal to the high-order bit flip-flop. The high-order bit flip-flop may latch the second high-order bit data OP 2 _HO according to the gated clock signal and output the latched second high-order bit data OP 2 _HO_L. The second operand holding circuit  200  may provide the latched second high-order bit data OP 2 _HO_L, the second indicator signal HZI_ 2 , and the second low-order bit data OP 2 _LO to the arithmetic circuit  300 . 
     The operation of the arithmetic circuit  300  may be substantially the same as or similar to those of the arithmetic circuit  300  described with reference to  FIGS. 1 through 9 . Additionally, the arithmetic circuit  300  may perform data gating on the latched second high-order bit data OP 2 _HO_L based on the second indicator signal HZI_ 2 . The arithmetic circuit  300  may also gate a clock signal, which is applied to a flip-flop related to the latched second high-order bit data OP 2 _HO_L, based on the second indicator signal HZI_ 2 , and may perform an operation based on a modified second operand, which results from the clock gating and/or the data gating. In other words, the arithmetic circuit  300  may output the operation result RES by performing an operation using the modified first operand and the modified second operand. 
       FIGS. 11A and 11B  illustrate multiplication circuits  342   c  and  342   d , respectively, according to embodiments. In particular,  FIGS. 11A and 11B  may illustrate examples of a multiplication circuit included in the arithmetic circuit  300  of the arithmetic apparatus  20  when the arithmetic circuit  300  performs convolution. 
     Referring to  FIG. 11A , the multiplication circuit  342   c  may include a first operand register  343   c , a second operand register  345   c , a multiplier  346   c , and an output register  348   c.    
     The first operand register  343   c  may temporarily store and output the modified first operand OP 1 _M. The modified first operand OP 1 _M may include the data-gated first high-order bit data OP 1 _HO_DG and the first low-order bit data OP 1 _LO. For example, the modified first operand OP 1 _M may be formed by adding, as a high-order bit, the data-gated first high-order bit data OP 1 _HO_DG to the first low-order bit data OP 1 _LO. 
     The second operand register  345   c  may temporarily store and output a modified second operand OP 2 _M. The modified second operand OP 2 _M may include data-gated second high-order bit data OP 2 _HO_DG and the second low-order bit data OP 2 _LO. For example, the modified second operand OP 2 _M may be formed by adding, as a high-order bit, the data-gated second high-order bit data OP 2 _HO_DG to the second low-order bit data OP 2 _LO. 
     The multiplier  346   c  may generate the multiplication result RES_M by performing multiplication using the modified first operand OP 1 _M and the modified second operand OP 2 _M. For example, when each of the first operand OP 1  and the second operand OP 2  is 8-bit data, the multiplier  346   c  may include an 8×8-bit multiplier or a 9×9-bit multiplier. 
     The output register  348   c  may temporarily store the multiplication result RES_M and may output the multiplication result RES_M as output of the multiplication circuit  342   c.    
     Referring to  FIG. 11B , the multiplication circuit  342   d  may include a first operand low-order bit register  343 _ 1   d , a first operand high-order bit register  343 _ 2   d , a second operand low-order bit register  345 _ 1   d , a second operand high-order bit register  345 _ 2   d , a first multiplier  346 _ 1   d , a second multiplier  346 _ 2   d , a third multiplier  346 _ 3   d , a fourth multiplier  346 _ 4   d , a first shifter  347 _ 1   d , a second shifter  347 _ 2   d , a third shifter  347 _ 3   d , an adder  346 _ 5   d , and an output register  348   d.    
     The first operand low-order bit register  343 _ 1   d  may temporarily store and output the first low-order bit data OP 1 _LO. The first operand high-order bit register  343 _ 2   d  may temporarily store and output the data-gated first high-order bit data OP 1 _HO_DG. The second operand low-order bit register  345 _ 1   d  may temporarily store and output the second low-order bit data OP 2 _LO. The second operand high-order bit register  345 _ 2   d  may temporarily store and output the data-gated second high-order bit data OP 2 _HO_DG. 
     The first multiplier  346 _ 1   d  may output the first multiplication result M 1  by multiplying the first low-order bit data OP 1 _LO by the second low-order bit data OP 2 _LO. For example, when the first low-order bit data OP 1 _LO is 4-bit data and the second low-order bit data OP 2 _LO is 4-bit data, the first multiplier  346 _ 1   d  may include a 4×4-bit multiplier or a 5×5-bit multiplier. 
     The second multiplier  346 _ 2   d  may output the second multiplication result M 2  by multiplying the data-gated first high-order bit data OP 1 _HO_DG by the data-gated second high-order bit data OP 2 _HO_DG. For example, when first high-order bit data is 4-bit data and second high-order bit data is 4-bit data, the second multiplier  346 _ 2   d may include a 4×4-bit multiplier or a 5×5-bit multiplier. 
     The third multiplier  346 _ 3   d  may output a third multiplication result M 3  by multiplying the data-gated first high-order bit data OP 1 _HO_DG by the second low-order bit data OP 2 _LO. For example, when the first high-order bit data is 4-bit data and the second low-order bit data OP 2 _LO is 4-bit data, the third multiplier  346 _ 3   d  may include a 4×4-bit multiplier or a 5×5-bit multiplier. 
     The fourth multiplier  346 _ 4   d  may output a fourth multiplication result M 4  by multiplying the first low-order bit data OP 1 _LO by the data-gated second high-order bit data OP 2 _HO_DG. For example, when the first low-order bit data OP 1 _LO is 4-bit data and the second high-order bit data is 4-bit data, the fourth multiplier  346 _ 4   d  may include a 4×4-bit multiplier or a 5×5-bit multiplier. 
     The first shifter  347 _ 1   d  may output the shifted second multiplication result M 2 _S by shifting the second multiplication result M 2  by the sum of the number of bits in the first low-order bit data OP 1 _LO and the number of bits in the second low-order bit data OP 2 _LO. 
     The second shifter  347 _ 2   d  may output a shifted third multiplication result M 3 _S by shifting the third multiplication result M 3  by the number of bits in the first low-order bit data OP 1 _LO. 
     The third shifter  347 _ 3   d  may output a shifted fourth multiplication result M 4 _S by shifting the fourth multiplication result M 4  by the number of bits in the second low-order bit data OP 2 _LO. 
     The adder  346 _ 5   d  may output the multiplication result RES_M by adding up the first multiplication result M 1 , the shifted second multiplication result M 2 _S, the shifted third multiplication result M 3 _S, and the shifted fourth multiplication result M 4 _S. 
     The output register  348   d  may temporarily store the multiplication result RES_M and output the multiplication result RES_M to the outside of the multiplication circuit  342   d.    
       FIG. 12  illustrates an electronic system  30  according to an embodiment. The electronic system  30  may analyze input data in real time based on a neural network, obtain valid information, and identify a situation or control elements of an electronic device equipped with the electronic system  30  based on the valid information. For example, the electronic system  30  may be applied to a drone, a robot device like an advanced driver assistance system (ADAS), a smart television (TV), a smart phone, a medical device, a mobile device, an image display, a measuring device, an Internet of things (loT) device, etc. The electronic system  30  may be implemented in any one of other various kinds of electronic devices. Hereinafter, a device using the electronic system  30  accelerating a neural network is referred to as a neural network device. 
     The electronic system  30  may include a neural network processing unit (NPU)  1000 , random access memory (RAM)  2000 , a processor  3000 , memory  4000 , and a sensor module  5000 . The components of the electronic system  30  may be connected to each other through one or more communication lines or busses. The NPU  1000  may be referred to as a neural network processor  1000 . 
     The NPU  1000  may generate a neural network, train or learn a neural network, perform an operation based on input data and generate an information signal based on an operation result, or retrain a neural network. Neural network models may include various kinds of models, such as a convolutional neural network (CNN) like GoogleNet, AlexNet, or VGG network, a region with CNN (R-CNN), a region proposal network (RPN), a recurrent neural network (RNN), a stacking-based deep neural network (S-DNN), a state-space dynamic neural network (S-SDNN), a deconvolution network, a deep belief network (DBN), a restricted Boltzmann machine (RBM), a fully convolutional network, a long short-term memory (LSTM) network, and a classification network, but are not limited thereto. The NPU  1000  may include at least one processor that performs operations according to neural network models. The NPU  1000  may include separate memory that stores programs corresponding to respective neural network models. 
     The NPU  1000  may receive various kinds of input data through a system bus and may generate an information signal based on the input data. For example, the NPU  1000  may generate an information signal by performing a neural network operation on input data, and the neural network operation may include convolution. The information signal generated by the NPU  1000  may include at least one selected from various kinds of recognition signals such as a voice recognition signal, a thing recognition signal, an image recognition signal, and a biometric recognition signal. For example, the NPU  1000  may receive frame data included in a video stream as input data and may generate a recognition signal with respect to a thing, which is included in an image represented by the frame data, from the frame data. However, embodiments are not limited thereto. The NPU  1000  may receive various kinds of input data and generate a recognition signal based on the input data. 
     The RAM  2000  may temporarily store programs, data, or instructions. Programs and/or data stored in the memory  4000  may be temporarily loaded to the RAM  2000  according to the control of the processor  3000  or booting code. The RAM  2000  may be implemented using memory such as dynamic RAM (DRAM) or static RAM (SRAM). 
     The processor  3000  may control all operations of the electronic system  30 . For example, the processor  3000  may be implemented as a central processing unit (CPU). The processor  3000  may include a single core or multiple cores. The processor  3000  may process or execute programs and/or data, which are stored in the RAM  2000  and the memory  4000 . For example, the processor  3000  may control functions of the electronic system  30  by executing programs stored in the memory  4000 . 
     The memory  4000  is storage for storing data and may store, for example, an operating system (OS), various programs, and various data. The memory  4000  may include DRAM but is not limited thereto. The memory  4000  may include at least one selected from volatile memory and non-volatile memory. The non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), and ferroelectric RAM (FRAM). The volatile memory may include DRAM, SRAM, and synchronous DRAM (SDRAM). In an embodiment, the memory  4000  may include at least one selected from a hard disk drive (HDD), a solid state drive (SSD), compact flash (CF) memory, secure digital (SD) memory, micro-SD memory, mini-SD memory, extreme digital (xD) memory, and a memory stick. 
     The sensor module  5000  may collect surrounding information of the electronic system  30 . The sensor module  5000  may sense or receive an image signal from outside the electronic system  30  and may convert the image signal into image data, e.g., an image frame. For this operation, the sensor module  5000  may include at least one sensing device selected from various sensing devices, such as an image pickup device, an image sensor, a light detection and ranging (LIDAR) sensor, an ultrasonic sensor, and an infrared sensor, or may receive a sensing signal from the sensing device. In an embodiment, the sensor module  5000  may provide the image frame to the NPU  1000 . For example, the sensor module  5000  may include an image sensor and may generate a video stream by capturing surroundings of the electronic system  30  and sequentially provide consecutive image frames in the video stream to the NPU  1000 . 
     According to an embodiment, the NPU  1000  of the electronic system  30  may be implemented as the arithmetic apparatus  10  described with reference to  FIGS. 1 through 9  or the arithmetic apparatus  20  described with reference to  FIGS. 10 through 11B . This will be described in detail with reference to  FIGS. 13 through 15 . 
       FIG. 13  illustrates a neural network processor  1000  according to an embodiment. The neural network processor  1000  of  FIG. 13  may correspond to the NPU  1000  of  FIG. 12 . 
     The neural network processor  1000  of  FIG. 13  may include an input feature holding circuit  1100 , a weight holding circuit  1200 , and an arithmetic circuit  1300 . 
     In particular,  FIG. 13  may illustrate an example in which the arithmetic apparatus  10  described with reference to  FIGS. 1 through 9  is applied to the neural network processor  1000 . 
     The input feature holding circuit  1100  may correspond to the first operand holding circuit  100  in  FIG. 1 , the weight holding circuit  1200  may correspond to the second operand holding circuit  200  in  FIG. 1 , and the arithmetic circuit  1300  may correspond to the arithmetic circuit  300  in  FIG. 1 . An input feature value may correspond to a first operand, and a weight value WV may correspond to a second operand. The input feature value may be a value that is included in an input feature map used in the convolution operation of the neural network processor  1000 . The weight value WV may be a value that is included in a weight matrix used in the convolution operation of the neural network processor  1000 . Latched input feature high-order bit data IFV_HO_L may correspond to the latched first high-order bit data OP 1 _HO_L in  FIG. 1 . Input feature low-order bit data IFV_LO may correspond to the first low-order bit data OP 1 _LO in  FIG. 1 . An output feature value OFV may correspond to the operation result RES. 
       FIG. 14  illustrates the neural network processor  1000  according to an embodiment. The neural network processor  1000  of  FIG. 14  may correspond to the NPU  1000  of  FIG. 12 . 
     The neural network processor  1000  of  FIG. 14  may include the input feature holding circuit  1100 , the weight holding circuit  1200 , and the arithmetic circuit  1300 . 
     In particular,  FIG. 14  may illustrate an example in which the arithmetic apparatus  10  described with reference to  FIGS. 1 through 9  is applied to the neural network processor  1000 . 
     The weight holding circuit  1200  may correspond to the first operand holding circuit  100  in  FIG. 1 , the input feature holding circuit  1100  may correspond to the second operand holding circuit  200  in  FIG. 1 , and the arithmetic circuit  1300  may correspond to the arithmetic circuit  300  in  FIG. 1 . A weight value may correspond to a first operand and an input feature value IFV may correspond to a second operand. Latched weight high-order bit data WV_HO_L may correspond to the latched first high-order bit data OP 1 _HO_L in  FIG. 1 . Weight low-order bit data WV LO may correspond to the first low-order bit data OP 1 _LO in  FIG. 1 . The output feature value OFV may correspond to the operation result RES. 
       FIG. 15  illustrates the neural network processor  1000  according to an embodiment. The neural network processor  1000  of  FIG. 15  may correspond to the NPU  1000  of  FIG. 12 . 
     The neural network processor  1000  of  FIG. 15  may include the input feature holding circuit  1100 , the weight holding circuit  1200 , and the arithmetic circuit  1300 . 
     In particular,  FIG. 15  may illustrate an example in which the arithmetic apparatus  20  described with reference to  FIGS. 10 through 11B  is applied to the neural network processor  1000 . 
     The input feature holding circuit  1100  may correspond to the first operand holding circuit  100  in  FIG. 10 , the weight holding circuit  1200  may correspond to the second operand holding circuit  200  in  FIG. 10 , and the arithmetic circuit  1300  may correspond to the arithmetic circuit  300  in  FIG. 10 . An input feature value may correspond to a first operand and a weight value may correspond to a second operand. The latched input feature high-order bit data IFV_HO_L may correspond to the latched first high-order bit data OP 1 _HO_L in  FIG. 10 . The input feature low-order bit data IFV_LO may correspond to the first low-order bit data OP 1 _LO in  FIG. 10 . The latched weighted high-order bit data WV_HO_L may correspond to the latched second high-order bit data OP 2 _HO_L in  FIG. 10 . The weighted low-order bit data WV_LO may correspond to the second low-order bit data OP 2 _LO in  FIG. 10 . The output feature value OFV may correspond to the operation result RES. 
     While aspects have been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the following claims.