Patent Publication Number: US-11379149-B2

Title: Memory device including a processing circuit, memory controller controlling the memory device and memory system including the memory device

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     The present application claims priority under 35 U.S.C. § 119(a) to a Korean Patent Application No. 10-2019-0054844, filed on May 10, 2019, which are incorporated herein by reference in its entirety. 
     BACKGROUND 
     1. Technical Field 
     Embodiments relate to a memory device including a processing circuit, a memory controller for controlling the memory device, and a memory system including the memory device. More particularly, embodiments include a memory device capable of performing a general memory read or write operation during a processing operation, a memory controller for controlling the memory device, and a memory system including the memory device. 
     2. Related Art 
     Processing-in-memory (PIM) technology is being developed to perform processing operations within a memory device. 
     Conventional PIM technology is limited to a specific application based on a 3D stacked memory device such as a Hyper Memory Cube (HMC) or a High Bandwidth Memory (HBM), or has been developed as an accelerator in a Dynamic Random Access Memory (DRAM) device. 
     In a memory device adopting conventional PIM technology, a general memory read and write operations cannot be performed during a processing operation, and accordingly the performance of the memory system deteriorates. 
     SUMMARY 
     In accordance with the present teachings, a memory controller according to an embodiment may include a request queue storing a memory request including a read request to a memory device and a write request to the memory device and a process in memory (PIM) request to require a processing operation in the memory device; a command generator configured to generate a memory command from a memory request output from the request queue and to generate a PIM command from a PIM request output from the request queue; a command queue storing a memory command and a PIM command output from the command generator; and a command scheduler configured to control output order or output timing of a memory command and a PIM command stored in the command queue. 
     In accordance with the present teachings, a memory device according to an embodiment may include a command decoder configured to decode a memory command representing a read or a write operation in the memory device and decode a PIM command representing a processing operation in the memory device; a bank to store data; an input/output (IO) buffer configured to input or output data; a shared bus configured to transfer data between the bank and the IO buffer; and a processing circuit configured to be connected with the shared bus and the bank and to perform a processing operation according to a control by the command decoder, wherein the bank is controlled by the command decoder to perform a memory command while the processing circuit performs a processing operation by a PIM command. 
     In accordance with the present teachings, a memory system according to an embodiment may include a memory device and a memory controller. The memory controller may be configured to generate a memory command from a memory request including a read request and a write request for the memory device, to generate a PIM command from a PIM request requiring a processing operation in the memory device, and to schedule the PIM command together with the memory command, wherein the memory device performs data read or data write operation according to a memory command from the memory controller and performs a processing operation according to a PIM command from the memory controller, and wherein the memory device performs the data read or data write operation while the memory device performs the processing operation. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The accompanying figures, where like reference numerals refer to identical or functionally similar elements throughout the separate views, together with the detailed description below, are incorporated in and form part of the specification, and serve to further illustrate embodiments of concepts that include the claimed novelty, and explain various principles and advantages of those embodiments. 
         FIG. 1  illustrates a memory system according to an embodiment of the present disclosure. 
         FIG. 2  illustrates a memory controller according to an embodiment of the present disclosure. 
         FIG. 3  illustrates a memory controller according to another embodiment of the present disclosure. 
         FIGS. 4A and 4B  show data structures of a memory command and a PIM command, respectively, according to an embodiment of the present disclosure. 
         FIG. 5  shows a table illustrating PIM commands according to an embodiment of the present disclosure. 
         FIG. 6  shows a state diagram illustrating operation of a memory device according to an embodiment of the present disclosure. 
         FIG. 7  illustrates a memory device according to an embodiment of the present disclosure. 
         FIG. 8  illustrates a portion of a memory device according to an embodiment of the present disclosure. 
         FIG. 9  illustrates a processing circuit according to an embodiment of the present disclosure. 
         FIGS. 10, 11, and 12  illustrate respective PIM operations according to an embodiment of the present disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     The following detailed description references the accompanying figures in describing illustrative embodiments consistent with this disclosure. The embodiments are provided for illustrative purposes and are not exhaustive. Additional embodiments not explicitly illustrated or described are possible. Further, modifications can be made to presented embodiments within the scope of the present teachings. The detailed description is not meant to limit this disclosure. Rather, the scope of the present disclosure is defined in accordance with the presented claims and equivalents thereof. 
       FIG. 1  shows a block diagram illustrating a memory system according to an embodiment of the present disclosure. 
     The memory system according to an embodiment of the present disclosure includes a memory controller  100  and a memory device  200 . 
     The memory controller  100  receives memory requests and process-in-memory (PIM) requests from the host  10 . The memory requests and the PIM requests may be communicated to the memory controller  100  via a common interface. The memory controller may also receive other information associated with the memory requests and PIM requests (such as addresses) via the common interface. 
     The memory system according to the present embodiment can be connected to the host  10  via a memory bus. 
     The memory system according to the present embodiment may be provided separately from a main memory device connected to a memory bus, and the memory system may be connected to the host  10  via a separate interface such as a PCI Express (PCIe) interface. 
     In this way, the host  10  can provide the memory requests and the PIM requests to the memory system via a common interface. 
     Memory controller  100  generates memory commands and PIM commands from memory requests and PIM requests, and provides the memory commands and PIM commands to the memory device  200  via the same controller-to-memory interface. In an embodiment, the controller-to-memory interface may be an interface according to a memory standard, such as the JEDEC JESD79-4 Double Data Rate 4 Synchronous DRAM (DDR4 SDRAM) standard, JEDEC JESD235B HIGH BANDWIDTH MEMORY (HBM) DRAM standard, and the like. 
     The memory controller  100  schedules a memory command and a PIM command together and provides them to the memory device  200 , which operates such that a memory command and a PIM command can be processed using the same states and transitions of a state machine controlling the memory device  200 , as detailed below. 
     Accordingly, the memory system according to an embodiment does not require a separate interface for a PIM command. 
     In an embodiment, the host  10  may provide a PIM Instruction to the memory controller  100  instead of a PIM request. A PIM instruction corresponds to an operation that may be performed via one or more PIM requests. 
     The PIM instruction may be generated in response to a specific software code requiring a PIM operation and may be provided from the host  10 . 
     In an embodiment, a PIM instruction may be preprocessed through a software library into one or more PIM requests, and the host  10  may provide the one or more PIM requests to the memory controller  100  instead of the PIM instruction. 
     In an embodiment wherein the host  10  provides a PIM Instruction directly to the memory controller  100 , rather than a PIM request, the memory system receives the PIM instruction and internally decodes the PIM instruction into one or more PIM requests. 
       FIG. 2  shows a block diagram illustrating the memory controller  100  according to an embodiment of the present disclosure. 
       FIG. 2  corresponds to an embodiment wherein the host  10  provides requests to the memory controller  100 . The requests include memory requests and PIM requests. 
     The memory controller  100  includes a request queue  110 , a request scheduler  120 , a command generator  130 , a command queue  140 , and a command scheduler  150 . 
     Memory requests and PIM requests provided by the host  10  are stored as requests in the request queue  110 . Other information associated with a request (e.g., an address and/or data associated with a request) may be stored with the request in the request queue  110 . 
     The request scheduler  120  determines the processing order of the requests stored in the request queue  110 . 
     A memory request may include a memory read request or a memory write request. A memory read request may have an associated address, and a memory write request may have an associated address and associated data. 
     A PIM request is a request requiring a processing operation, and in an embodiment may include a PIM read request or a PIM write request. 
     A request may include a special bit (a PIM bit) to distinguish a memory request from a PIM request. 
     For example, a request may be determined to be a memory request if the PIM bit is 0 and may be determined to be a PIM request if the PIM bit is 1. 
     The memory controller  100  may also insert a PIM bit in a corresponding command generated from a memory request or a PIM request and provide the corresponding command to the memory device  200 . 
     The request scheduler  120  may apply various scheduling techniques such as First-Come-First-Served (FCFS) and First-Read-First-Come-First-Served (FR-FCFS) to schedule requests stored in the request queue  110  and may provide a selected request to the command generator  130 . 
     The command generator  130  receives a request from the request queue  110 . When the request is a memory request, the command generator  130  converts the memory request into one or more memory commands and stores the memory commands into the command queue  140 . When the request is a PIM request, the command generator  130  converts the PIM request into one or more PIM commands and stores the PIM commands into the command queue  140 . 
     The command scheduler  150  selects and outputs memory commands and PIM commands stored in the command queue  140  to the memory device  200  in consideration of timing constraints necessary for operation of the memory device  200 . 
     The timing constraint is predefined through standards or the like, and a detailed description thereof will be omitted. 
     In an embodiment, the command scheduler  150  may consider additional constraints in addition to the timing constraints. 
     As will be described in detail below, the memory device  200  according to an embodiment includes a plurality of banks and a plurality of processing circuits, and the plurality of banks and the plurality of processing circuits may exchange data via a shared bus (SBUS). 
     Thus, in an embodiment, the command scheduler  150  may schedule memory commands and PIM commands by further considering the state of the shared bus to prevent data conflicts on the shared bus. 
     In an embodiment, the command scheduler  150  may schedule memory commands and PIM commands per each bank and provide them to the memory device  200 . 
       FIG. 3  illustrates a memory controller  101  according to another embodiment of the present disclosure. 
       FIG. 3  corresponds to an embodiment where the host  10  provides a PIM instruction instead of a PIM request to the memory controller  101 . 
     Accordingly, in addition to the components included in the memory controller  100  of  FIG. 2 , the memory controller  101  further includes a PIM instruction queue  160  for storing PIM instructions and a PIM decoder  170  for converting a PIM instruction into one or more PIM requests. 
     The host  10  may generate a write request including contents of a PIM instruction in write data and send the write request and the write data to the memory controller  101 . 
     For convenience, a write request with write data that includes contents of the PIM Instruction may be referred to as a PIM instruction. 
     In embodiments, a PIM bit is included in the write request to distinguish a write request including a PIM instruction from a general write request. 
     In such an embodiment, write data included in a write request whose PIM bit is set to 1 may be regarded as a PIM instruction and stored in the PIM instruction queue  160 . 
     A memory request with a PIM bit set to 0 may be regarded as a general memory request and stored directly in the request queue  110 . 
     For this purpose, a path selection circuit  180  to determine an output direction for requests according to the PIM bit of the request may be included in the memory controller  101 . 
     The PIM decoder  170  generates one or more of PIM requests corresponding to a PIM instruction. The PIM requests generated by the PIM decoder  170  are queued in the request queue  110 . 
     The PIM decoder  170  may perform a part or all of the operations performed by above-described software library. Specific decoding rules may be predetermined according to embodiments and therefore description about specific decoding operations will be omitted. 
     Operations of the request queue  110 , the request scheduler  120 , the command generator  130 , the command scheduler  150  and the command queue  140  are substantially the same as described with reference to  FIG. 2 . 
       FIG. 4A  shows data structure of a memory command according to an embodiment, and  FIG. 4B  shows data structure of a PIM command according to an embodiment. The memory command and PIM command may be communicated from a memory controller to a memory device via a common interface. In an embodiment, the interface may be signals according to a memory standard; for example, the memory command and PIM command may both be communicated over the CKE, CKE1/C0, CS_n, ACT, RAS_n, CAS_n, WE, and CS1_n/C1 signals of the JESD79-4 DDR4 SDRAM standard, but embodiments are not limited thereto. 
     The memory command shown in  FIG. 4A  further includes a PIM bit to a conventional memory command. 
     In this embodiment, a PIM bit corresponding to a memory command is set to zero. 
     The conventional memory command includes a total of 7 bits including a 2-bit Clock Enable (CKE) field, a 1-bit Chip Select (CS) field, a 1-bit Activate Command Input (ACT) field, a 1-bit Row Address Strobe (RAS) field, a 1-bit Column Address Strobe (CAS) field, and a 1-bit Write Enable (WE) field. 
     The command decoder in the memory device  200  decodes a memory command in accordance with predetermined rules to control the internal elements of the memory device  200 . 
     The meaning of each field of the memory command and the technique of decoding them are well-known, and a detailed description thereof will be omitted. 
     A PIM command shown in  FIG. 4B  has as same number of bits as a memory command, and a PIM bit of a PIM command is set to 1. 
     In this embodiment, a PIM command includes a 3-bit OPCODE field, and a 2-bit SRC field and a 2-bit DST field. 
     The OPCODE field is used to distinguish types of a PIM command and a specific operation of each type. 
     The SRC field and the DST field can be used to indicate the source and destination of data during a PIM operation. 
     The memory device  200  may further refer to an address provided to the memory device  200  in association with a PIM command in the same manner as the memory device  200  refers to an address provided to the memory device  200  in association with a memory command. The address may be provided to the memory device over different signals than those used to communicate the memory or PIM command, over the same signals as those used to communicate the memory or PIM command by using time multiplexing, or a combination thereof. For example, in an embodiment, addresses may be provided to the memory device as prescribed by a memory standard such as the JESD79-4 DDR4 SDRAM standard, but embodiments are not limited thereto. 
     In this embodiment, a PIM command is generated so as to have the same number of bits as a memory command. 
     In this embodiment, the 7-bit signal except the PIM bit in a memory command and a PIM command can be transmitted to the memory device  200  via a command bus in a conventional manner. 
     In such an embodiment, the PIM bit may be transmitted between the memory controller  100  and the memory device  200  using a pad unused during transmission of a command signal. 
     For example, a PIM bit can be transmitted via a data pad or an address pad that would otherwise be unused during transmission of a command. 
     In another embodiment, a separate pad may be added to the memory controller  100  and memory device  200  to communicate the PIM bit. 
     In another embodiment, a total of 8 bits including a PIM bit may be encoded into a signal of less than or equal to 7 bits, and the signal of less than or equal to 7 bits transmitted through a conventional command bus. 
     The memory device  200  receiving the encoded command signal can decode the encoded command signal and generate a memory command or a PIM command, and then decode each command and control internal elements accordingly. 
     The controller-to-memory interface for transmitting memory commands and PIM commands to the memory device can be variously modified. 
     Generally, a memory command corresponds to an operation of transmitting or receiving data between a bank and an Input/Output (IO) buffer. 
     In an embodiment, a PIM command corresponds to an operation of transmitting or receiving data between a bank or the shared bus and a processing circuit. 
     In such an embodiment, a PIM command may designate a specific operation which may be performed by a processing circuit. 
     In an embodiment, a first PIM operation includes a memory read operation, and accordingly, the first PIM operation may be handled by the memory device  200  in a manner similar to a memory read operation with a longer latency. A second PIM operation includes a memory write operation, and the second PIM operation may be handled by the memory device  200  in a manner similar to a memory write operation. 
       FIG. 5  shows a table illustrating PIM commands according to an embodiment of the present disclosure. In  FIG. 5 , a value of “X” indicates a reserved or “don&#39;t care” value. 
     Types of PIM commands shown in the table of  FIG. 5  may be defined pursuant to the design and internal structure of the processing circuit  300  included in the memory device  200 . The internal structure of the processing circuit  300  will be described later in detail. 
     The PIM commands include PIM read commands (PIM RD) and PIM write commands (PIM WR). A specific PIM command is indicated by the opcode field. 
     In an embodiment, the PIM read commands include four operation commands: a PIM read operation command PRD, a PIM clear operation command CLR, a PIM processing operation command MAC, and a PIM reduction operation command RADD. 
     The PIM read operation command PRD is indicated by “010” in the OPCODE field, and stores data of the bank or from the shared bus (SBUS) into either a 0th buffer (BUF 0 ) or a 1st buffer (BUF 1 ). 
     Storing data from the a bank is indicated by “00” in the SRC field, and storing data from the shared busby “01” in the SRC field. Storing the data into the BUF 0  is indicated by “10” in the DST field, and storing the data into the BUF 1  is indicated by “11” in the DST field. 
     The BUF 0  and the BUF 1  are included in the processing circuit  300 , the bank is a bank respectively associated with the processing circuit performing the command, and the shared bus is a data bus commonly connected to a plurality of banks and an IO buffer, and these are specifically described below. 
     The PIM clear operation command CLR is indicated by “000” in the OPCODE field, and each bit in the following four bits correspond to BUF 0 , BUF 1 , vACC, and rACC respectively. Elements corresponding to activated bits in those four bits are reset by the clear operation. 
     vACC is an accumulator that accumulates a result of a vector operation and rACC is an accumulator that accumulates a result of a scalar operation. Hereinafter, vACC may be referred to as a first accumulator, and rACC may be referred to as a second accumulator. 
     The PIM processing operation command MAC is indicated by “100” In the OPCODE field, and information corresponding to the SRC field and the DST field is not used. 
     In the PIM processing operation, each value of an element of the vACC is accumulated with a multiplication of corresponding elements of BUF 0  and BUF 1 . For example, in an embodiment vACC, BUF 0 , and BUF 1  way each include 16 8-bit data elements, the PIM processing operation may perform, for i=1 to 16, vACC[i]←vACC[i]+BUF 0 [i]×BUF 1 [i], wherein vACC[i], BUF 0 [i], and BUF 1 [i] respectively indicate i th  bytes of vACC, BUF 0 , and BUF 1 . 
     The PIM reduction operation command RADD is indicated by “110” in the OPCODE field and the information in the DST field is not used. 
     The reduction operation is subdivided into two operations according to information of the SRC field. The first reduction operation is performed when the SRC field is “0X”, which corresponds to adding all the elements of vACC and storing the result in the rACC. For example, in the embodiment above where vACC includes 16 8-bit data elements, the PIM reduction operation may perform rACC[i]←vACC[ 1 ]+vACC[ 2 ]+ . . . +vACC[ 15 ]+vACC[ 16 ] when the SRC field is “0X”, wherein rACC[i] indicates a value within the rACC selected using address information associated with the PIM reduction operation command RADD. 
     The second reduction operation is performed when the SRC field is “1X”, which corresponds to accumulating a value of rACC with a value provided to the shared bus. For example, in an embodiment wherein the SBUS includes 128 bits conceptually divided into 16 8-bit data elements, the second reduction operation may select a j th  byte SBUS[j] of the SBUS according to address information associated with the PIM reduction operation command RADD, and may perform rACC[i]←rACC[i]+SBUS[j], wherein rACC[i] indicates a value within the rACC selected using address information associated with the PIM reduction operation command RADD. 
     In an embodiment, PIM write commands are indicated by “001” in the OPCODE field and includes a PIM write operation command PWR. 
     The PIM write operation is an operation of copying data of the vACC or rACC to a bank or onto the shared bus. 
     Copying data to a bank is indicated by “00” in the DST field, and to the shared bus indicated by “01” in the DST field. Copying data from the vACC is indicated by “10” in the SRC field, and from the rACC indicated by “11” in the SRC field. 
       FIG. 6  shows a state diagram  600  illustrating an operation of a state machine in a memory device  200  according to an embodiment of the present disclosure. 
     The state diagram  600  of  FIG. 6  is in many respects the same as a corresponding state diagram for a conventional Dynamic Random Access Memory (DRAM). 
     In an embodiment, the state machine corresponding to the state machine  600  changes states in response to a PIM read command (PIM RD) and a PIM write command (PIM WR), which are PIM commands, as well as changing states in response to a read command (RD), a write command (RD), an Activate command (AC), a Precharge command (PRE), and a Refresh command (REF) which are conventional DRAM commands. 
     States of the state diagram  600  include an idle state S 10 , a bank active state S 20 , a write state S 30 , a read state S 40 , a precharge state S 50 , and a refresh state S 60 . 
     When the Activate command ACT is input in the idle state S 10 , the state transitions to the bank active state S 20 , and in an embodiment a row of a bank determined according to an address associated with the Activate command is placed in the activated state, so that data can be read from and written to that row. When the refresh command REF is input in the idle state S 10 , the state transitions to the refresh state S 60 . 
     When the write command WR or PIM write command PIM WR is input in the bank active state S 20 , the state transitions to the write state S 30 . When the read command RD or the PIM read command PIM RD is input in the bank active state S 20 , the state transitions to the read state S 40 . When the precharge command PRE is input in the bank active state S 20 , the state transitions to the precharge state S 50 . 
     When the write command WR or PIM write command PIM WR is input in the write state S 30 , the write state S 30  is maintained. When the read command RD or the PIM read command is input in the write state S 30 , the state transitions to the read state S 40 . When the precharge command PRE is input in the write state S 30 , the state transitions to the precharge state S 50 . When the write operation is completed without receiving another command in the write state S 30 , the state transitions to the bank active state S 20 . Whenever the state machine transitions to or remains in the write state S 30  in response to a command, data may be written to the active row in the bank, to the shared bus SBUS, or neither, depending on the command. 
     When the write command WR or PIM write command PIM WR is input in the read state S 40 , the state transitions to the write state S 30 . When the read command RD or PIM read command PIM RD is input in the read state S 40 , the read state S 40  is maintained. When the precharge command PRE is input in the read state S 40 , the state transitions to the precharge state S 50 . When the write operation is completed without receiving another command in the read state S 40 , the state transitions to the bank active state S 20 . Whenever the state machine transitions to or remains in the read state S 40  in response to a command, data may be read from the active row in the bank, from the shared bus SBUS, or neither, depending on the command. 
     When the precharge operation terminates in the precharge state S 50 , the state transitions to the idle state S 10 . When the refresh operation terminates in the refresh state S 60 , the state transitions to the idle state S 10 . Whenever the state machine transitions to the precharge state S 50 , the active row in the bank is deactivated. 
     As shown in  FIG. 6 , memory commands and PIM commands are processed by the state machine corresponding to the state diagram  600  in the same way, which has the following advantages. 
     First, it is possible to prevent the processing of a memory command from being unconditionally interrupted by the processing of a PIM command. Accordingly, since a memory command can be scheduled and processed while a collision does not occur during processing of a PIM command, performance degradation of a memory system can be prevented. 
     Second, since a common state diagram is used, memory commands and PIM commands can be processed in a single command queue. Accordingly, further elements required for processing a PIM command separate from a memory command may not be included in a memory controller and a memory device, thereby simplifying a memory system. 
       FIG. 7  show a block diagram illustrating portions of a memory device  200  according to an embodiment of the present disclosure. 
     The memory device  200  according to the present embodiment includes a plurality of banks  210 , a plurality of processing circuits  300 , a shared bus  220 , and an IO buffer  230 . In an embodiment, the memory device  200  may further include one or more command decoder circuits (not shown) as described with respect to  FIG. 8 . A command decoder may be included for and associated with each combination of a bank  210  and a processing circuit  300 . 
     In an embodiment, the number of banks and processing circuits may be 16 and one bank  210  corresponds to one processing circuit  300 , but embodiments are not limited thereto. 
     The relationship between banks  210  and processing circuits  300  can be variously changed in consideration of address mapping or parallel processing. For example, in an embodiment, each processing circuit  300  may be provided with and coupled to a corresponding plurality of banks  210 . 
     The shared bus  220  transfers data between the bank  210 , the processing circuit  300  and the IO buffer  230 . 
     The processing circuit  300  can perform a processing operation using data of a corresponding bank  210  or using data of another bank or another processing circuit transferred through the shared bus  220 . In an embodiment, each processing circuit  300  and its associated bank  210  receive and process commands independently, the commands including PIM commands and memory commands. In an embodiment, each processing circuit  300  and its associated bank  210  may simultaneously receive and process commands different from the commands being received and processed by other processing circuits  300  and its associated banks  210 . 
       FIG. 8  shows a block diagram illustrating a memory device  200  according to another embodiment of the present disclosure. 
     As described above, the memory device  200  includes a bank  210 , a shared bus  220 , and an IO buffer  230 . 
     The bank  210  includes a memory cell array  211 , a sense amplifier  212  and a row buffer  213 , whose detailed configuration and operation are substantially as same as those in the conventional memory device, and are therefore omitted in the interest of brevity. 
     Although one bank  210  is shown in  FIG. 8 , the memory device  200  may Include a plurality of banks each having the same structure. 
     The memory device  200  further includes a command decoder  240 , a row decoder  250 , and a column decoder  260 . 
     The basic operations of the command decoder  240 , the row decoder  250  and the column decoder  260  are the same as those of a conventional memory device, except as noted below. 
     The command decoder  240  further decodes a PIM command provided through the command signal, as well as decoding a memory command provided through the command signal, and controls the bank  210 , the row decoder  250 , the column decoder  260 , the shared bus  220 , the processing circuit  300 , and the IO buffer  230 . 
     In  FIG. 8 , a command includes a memory command or a PIM command. 
     The command decoder  240  refers to a PIM bit to identify whether a command is a memory command or a PIM command and to control other elements included in the memory device  200 . 
     When the Identified command is a memory command, it may use a conventional decoding technique to control other elements included in the memory device  200 . 
     If the identified command is a PIM command, it further controls other elements included in the memory device  200  to perform operations as illustrated in the table of  FIG. 5 . 
     The state transitions of the memory device  200  according to a memory command and a PIM command have been described above with reference to the state diagram of  FIG. 6 . 
     The processing circuit  300  reads information of the bank  210  or the shared bus  220  to perform a specified operation and writes result of the operation to the bank  210  or the shared bus  220 . 
     In the present embodiment, it is assumed that the processing circuit  300  performs a multiplication operation of a matrix and a vector, but the specific processing operation and the detailed structure of the processing circuit  300  may be variously changed according to embodiments. 
       FIG. 9  shows a block diagram illustrating a processing circuit  300  according to an embodiment of the present disclosure. 
     In this embodiment, data output from each bank  210  is represented by a 128-bit signal, each element of a matrix or a vector is represented by an 8-bit signal, and each row of a matrix or a vector includes 16 elements. 
     The processing circuit  300  includes a BUF 0   310  and a BUF 1   311  each storing 128-bit data transferred from the bank  210  or from the shared bus  220 . 
     The processing circuit  300  may further include latches for storing data of BUF 0   310  and BUF 1   311  for pipeline operation. 
     128-bit data includes 16 8-bit data elements each corresponding to an element of a vector or a matrix. 
     The processing circuit  300  further includes an ALU  320  and a vACC  330 . 
     The ALU  320  and vACC  330  perform element-by-element multiplication operations on 16 8-bit data elements stored in the BUF 0   310  and the BUF 1   311 , and accumulates results of the multiplication operations to data stored in the vACC  330 . 
     That is, the ALU  320  performs multiplication operation on elements stored in the BUF 0   310  and the BUF 1   311  and accumulates multiplication result to a value stored in the vACC  330 . 
     For example, the i-th element among the 16 elements stored in the BUF 0   310  is multiplied by the i-th element stored in the BUF 1   311  and the multiplication result is accumulated in the i-th element of the vACC  330 . 
     The processing circuit  300  further includes a reducer  360 . The reducer  360  adds all 16 8-bit data elements stored in the vACC  330  to generate an 8-bit value. 
     The processing circuit  300  further includes a first selector  340 . The first selector  340  outputs one 8-bit data element among 16 8-bit data elements from the 128-bit data transmitted from a bank  210  or from the shared bus  220 . 
     The first selector  340  can select any one of the data elements using address information that may be provided with the PIM read command from the memory controller  100 . 
     The processing circuit  300  further includes an adder  350  and a rACC  380 . 
     The adder  350  adds the output of the first selector  340  and the value stored in the rACC  380  to update the value of the rACC  380 . 
     The processing circuit  300  further includes a second selector  370 . The second selector  370  may be controlled in response to the first bit of the DST field to select the output of the reducer  360  or the output of the adder  350  and provides the selected output of the second selector  370  to the rACC  380 . 
     In this embodiment, the rACC  380  stores 512-bit data. The rACC  380  may store up to four 128-bit data to support burst write function. 
     For example, in  FIG. 5 , the output of the reducer  360  is selected when the DST field is “0X” and the output of the adder  250  is selected when the DST field is “1X” during the reduction operation. 
     The processing circuit  300  further includes a third selector  390  and the third selector  390  selects one of four 128-bit data among the 512-bit data stored in the rACC  380 . 
     At this time, the third selector  390  can select one of the four 128-bit data from the address that may be provided with the PIM write command. 
     The four 128-bit data stored in the rACC  380  may be sequentially selected in the burst write operation and sequentially stored from an address of the destination. 
     The processing circuit  300  further Includes a first tri-state buffer  301  connected to the bank  210  and a second tri-state buffer  302  connected to the shared bus  220  to prevent data collision. The first tri-state buffer  301  and the second tri-state buffer  302  may be bidirectional, so that data may be transferred to or from the bank through the first tri-state buffer  301 , and to or from the shared bus SBUS through the second tri-state buffer  302 . 
       FIG. 10  shows a diagram illustrating a PIM operation according to an embodiment of the present disclosure. 
     The first operation corresponds to a PIM RD command and specifically to a clear operation command CLR which clears BUF 0   310 , BUF 1   311 , vACC  330 , and rACC  380  according to bit information specified in the SRC and DST fields. 
     The second operation corresponds to a PIM RD command and specifically to a read operation command PRD for reading a first operand from a bank  210  and for storing the first operand to BUF 0   310 . An ACT command (not shown) may have preceded the PIM operation shown in  FIG. 10  to permit data to be read from and written to an activated row of the bank  210 . 
     The third operation corresponds to a PIM RD command and specifically to a read operation command PRD for reading a second operand from a bank  210  and for storing the second operand to BUF 1   311 . 
     The fourth operation corresponds to a PIM RD command and specifically to a processing operation command MAC for multiplying corresponding elements of BUF 0   310  and BUF 1   311  and for accumulating into elements of vACC  330  the corresponding multiplication results. 
     In the present embodiment, the memory controller  100  may not send a command for the fourth operation. Instead, the command decoder  240  of the memory device  200  may control elements of the memory device  200  to automatically perform the fourth operation after the second and the third operations are performed. 
     For example, if it is assumed that the second to the fourth operations are repeatedly performed, the fourth operation may be parallelly performed while the second operation and the third operation for the next loop are performed, thereby improving processing performance. 
     The fifth operation corresponds to a PIM RD command and specifically to a reduction operation command RADD for adding elements of the vACC  330  and for storing the result to the rACC  380 . 
     The operation of adding elements of the vACC  330  may be performed in the reducer  360  and the result is stored in the rACC  380  via the second selector  370 . 
     The sixth operation corresponds to a PIM WR command and specifically to a write operation command PWR for storing data from rACC  380  to the shared bus  220 . 
     The sixth operation may be performed to provide data output from a processing circuit  300  to another processing circuit  300  or another bank  210 . 
       FIG. 11  shows a diagram illustrating another PIM operation according to an embodiment of the present disclosure. 
       FIG. 11  further includes seventh operation between the fifth operation and the sixth operation in  FIG. 10 . 
     The seventh operation corresponds to a PIM RD command and specifically to a reduction operation command RADD which selects data from the shared bus  220  to update data of rACC  380 . 
     The data on the shared bus  220  may be data provided from another bank or another processing circuits that are not associated with the current processing circuit  300 . 
       FIG. 12  shows a diagram illustrating another PIM operation according to an embodiment of the present disclosure. 
       FIG. 12  includes the eighth operation instead of the sixth operation of  FIG. 11 . 
     The eighth operation corresponds to a PIM WR command and specifically to a write operation command PWR for writing data of rACC  380  to a bank  210 . 
     Although various embodiments have been described for illustrative purposes, it will be apparent to those skilled in the art that various changes and modifications may be made to the described embodiments without departing from the spirit and scope of the disclosure as defined by the following claims.