Patent Publication Number: US-2023136049-A1

Title: Semiconductor device package and method of manufacturing the same

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application is a continuation of U.S. patent application Ser. No. 17/151,066 filed Jan. 15, 2021, now issued as U.S. Pat. No. 11,545,426, the contents of which is incorporated herein by reference in its entirety. 
    
    
     BACKGROUND 
     1. Technical Field 
     The present disclosure generally relates to a semiconductor device package and a method of manufacturing the same, and to a semiconductor device package including an interconnection layer. 
     2. Description of the Related Art 
     Semiconductor device package(s) may have two or more substrates with different functions or pitches connected to each other. To enhance the performance of the semiconductor device package, the electrical connection for signal transmission between the substrates is a critical issue. 
     SUMMARY 
     In one or more embodiments, a semiconductor device package includes a first substrate and an adhesive layer. The first substrate has a first surface and a conductive pad adjacent to the first surface. The conductive pad has a first surface exposed from the first substrate. The adhesive layer is disposed on the first surface of the first substrate. The adhesive layer has a first surface facing the first substrate. The first surface of the adhesive layer is spaced apart from the first surface of the conductive pad in a first direction substantially perpendicular to the first surface of the first substrate. The conductive pad and the adhesive layer are partially overlapping in the first direction. 
     In one or more embodiments, a semiconductor device package includes a first substrate and a conductive via. The first substrate has a first surface and a conductive pad adjacent to the first surface. The conductive pad has a first surface exposed from the first substrate. The conductive via is electrically connected with the first surface of the conductive pad. The first surface of the conductive pad includes a trace substantially aligned with a lateral surface of the conductive pad. 
     In one or more embodiments, a method of manufacturing a semiconductor device package includes (a) providing a device including a first substrate and an adhesive layer disposed on the first substrate, the first substrate having a first surface and a conductive pad adjacent to the first surface, the conductive pad having a first surface exposed from the first substrate; and (b) removing a portion of the adhesive layer along a periphery of an upper surface of the conductive pad and within the upper surface of the conductive pad. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Aspects of the present disclosure are readily understood from the following detailed description when read with the accompanying figures. It should be noted that various features may not be drawn to scale. The dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. 
         FIG.  1 A  illustrates a cross-sectional view of a semiconductor device package, in accordance with some embodiments of the present disclosure. 
         FIG.  1 B  illustrates an enlarged view of a portion of the semiconductor device package as shown in  FIG.  1 A , in accordance with some embodiments of the present disclosure. 
         FIG.  1 B ′ illustrates an enlarged view of a portion of the semiconductor device package as shown in  FIG.  1 A , in accordance with some embodiments of the present disclosure. 
         FIG.  1 B ″ illustrates an enlarged view of a portion of the structure as shown in  FIG.  1 B ′, in accordance with some embodiments of the present disclosure. 
         FIG.  1 C  illustrates an enlarged view of a portion of the semiconductor device package as shown in  FIG.  1 A , in accordance with some embodiments of the present disclosure. 
         FIG.  1 C ′ illustrates an enlarged view of a portion of the semiconductor device package as shown in  FIG.  1 A , in accordance with some embodiments of the present disclosure. 
         FIG.  1 D  illustrates an enlarged view of a portion of the semiconductor device package as shown in  FIG.  1 A , in accordance with some embodiments of the present disclosure. 
         FIG.  1 D ′ illustrates an enlarged view of a portion of the semiconductor device package as shown in  FIG.  1 A , in accordance with some embodiments of the present disclosure. 
         FIG.  1 D ″ illustrates an enlarged view of a portion of the structure as shown in  FIG.  1 D ′, in accordance with some embodiments of the present disclosure. 
         FIG.  1 D ′″ illustrates an enlarged view of a portion of the structure as shown in  FIG.  1 D ″, in accordance with some embodiments of the present disclosure. 
         FIG.  2 A ,  FIG.  2 A ′,  FIG.  2 B ,  FIG.  2 B ′,  FIG.  2 B ″,  FIG.  2 C ,  FIG.  2 C ′,  FIG.  2 D ,  FIG.  2 E , and  FIG.  2 F  illustrate one or more stages of a method of manufacturing a semiconductor device package in accordance with some embodiments of the present disclosure. 
     
    
    
     Common reference numerals are used throughout the drawings and the detailed description to indicate the same or similar elements. The present disclosure will be more apparent from the following detailed description taken in conjunction with the accompanying drawings. 
     DETAILED DESCRIPTION 
     The following disclosure provides for many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below. These are, of course, merely examples and are not intended to be limiting. In the present disclosure, reference to the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Besides, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. 
     Embodiments of the present disclosure are discussed in detail below. It should be appreciated, however, that the present disclosure provides many applicable concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative and do not limit the scope of the disclosure. 
       FIG.  1 A  illustrates a cross-sectional view of a semiconductor device package  1 , in accordance with some embodiments of the present disclosure. The semiconductor device package  1  includes substrates  10 ,  12 , an adhesive layer  11 , electronic components  13   a ,  13   b ,  13   c , a package body  14 , and a shielding layer  15 . 
     In some embodiments, the substrate  10  may include an antenna substrate. The substrate  10  may include one or more conductive layers  10   a ,  10   b ,  10   p  and one or more dielectric layers  10   d . The conductive layers  10   p ,  10   b  are covered or encapsulated by the dielectric layer  10   d . The conductive layer  10   a  is exposed from the dielectric layer  10   d . For example, the conductive layer  10   a  is disposed on a surface  102  of the substrate  10 . In some embodiments, the conductive layers  10   a ,  10   b  define or include antenna patterns. For example, the conductive layer  10   b  may function as a radiator. For example, the conductive layer  10   a  may function as a director. The conductive layer  10   b  may be electromagnetically coupled to the conductive layer  10   a  for signal transmission. One or more conductive vias  10   f  may be electrically connected between conductive layers to provide electrical connections therebetween. In some embodiments, the conductive via  10   f  may function as a feeding line for the antenna (e.g., the conductive layer  10   b ). 
     In some embodiments, the dielectric layer  10   d  may include pre-impregnated composite fibers (e.g., pre-preg), Borophosphosilicate Glass (BPSG), silicon oxide, silicon nitride, silicon oxynitride, Undoped Silicate Glass (USG), any combination of two or more thereof, or the like. Examples of a pre-preg may include, but are not limited to, a multi-layer structure formed by stacking or laminating a number of pre-impregnated materials/sheets. In some embodiments, the conductive layers  10   a ,  10   b ,  10   p  and the conductive via  10   f  are, or include, a conductive material such as a metal or metal alloy. Examples of the conductive material include gold (Au), silver (Ag), copper (Cu), platinum (Pt), Palladium (Pd), other metal(s) or alloy(s), or a combination of two or more thereof. The substrate  10  may include any number of the dielectric layers and conductive layers depending on different design specifications. 
     The substrate  12  is disposed on a surface  101  of the substrate  10 . The substrate  12  is connected to the substrate  10  through the adhesive layer  11  (e.g., a tape, glue, or a die attach film (DAF)). For example, the adhesive layer  11  is disposed between a surface  122  of the substrate  12  and the surface  101  of the substrate  10  and connects the substrate  12  with the substrate  10 . The substrate  12  is electrically connected to the substrate  10  through one or more conductive vias  11   v . For example, the conductive via  11   v  penetrating the adhesive layer  11  and electrically connects the substrate  12  (e.g., a conductive pad  12   p ) with the substrate (e.g., the conductive layer  10   p ). In some embodiments, the adhesive layer  11  may be replaced by a dielectric layer or a molding compound. 
     The substrate  12  may be, for example, a printed circuit board, such as a paper-based copper foil laminate, a composite copper foil laminate, or a polymer-impregnated glass-fiber-based copper foil laminate. The substrate  12  may include an interconnection structure, such as a redistribution layer (RDL) or a grounding element. In some embodiments, the substrate  12  may be a single-layer substrate or multi-layer substrate. The substrate  12  may include one or more conductive pads  12   p  in proximity to, adjacent to, or embedded in and exposed at the surface  122  of the substrate  12 . 
       FIG.  1 B  illustrates an enlarged view of a portion of the semiconductor device package  1  encircled by a dotted-line box A 1 , in accordance with some embodiments of the present disclosure. As shown in  FIG.  1 B , the substrate  12  may include a solder resist  12   r  (or solder mask) on the surface  122  of the substrate  12  to cover a portion of the conductive pad  12   p  and to expose the rest portion of the conductive pad  12   p  for electrical connections. 
     As shown in  FIG.  1 B , the adhesive layer  11  is vertically spaced apart from the conductive pad  12   p  by the solder resist  12   r . For example, there is a gap between the surface  111  of the adhesive layer  11  and the surface  12   p   2  of the conductive pad  12   p . For example, the conductive pad  12  and the adhesive layer  11  are not overlapping in a direction substantially parallel to the surface  122  of the substrate  12 . 
     The adhesive layer  11  and the solder resist  12   r  define openings filled with the conductive via  11   v . For example, the conductive via  11   v  includes a portion  11   v   1  disposed within the opening defined by the adhesive layer  11  and a portion  11   v   2  (which can be referred to as a conductive element) disposed within the opening defined by the solder resist  11 r. The portion  11   v   1  of the conductive via  11   v  is tapered from the substrate  10  toward the substrate  12 . For example, a width of a part of the portion  11   v   1  of the conductive via  11   v  adjacent to the substrate  10  is greater than a width of a part of the portion  11   v   1  of the conductive via  11   v  adjacent to the substrate  12 . In some embodiments, the maximum width of the portion  11   v   1  of the conductive via  11   v  (e.g., the part of the portion  11   v   1  of the conductive via  11   v  adjacent to the substrate  10 ) is less than a width of the portion  11   v   2  of the conductive via  11   v  or a width of the conductive pad  12   p.    
     In some embodiments, the conductive via  11   v  is in contact with the conductive layer  10   p , the adhesive layer  11 , the solder resist  12   r , and the surface  12   p   2  of the conductive pad  12   p . The conductive via  11   v  provides electrical connections between the conductive layer  10   p  and the conductive pad  12   p . In some embodiments, the conductive via  11   v  may include a conductive material. For example, the conductive via  11   v  may include a flowable conductive material (e.g., soldering material). For example, the conductive via  11   v  may include a conductive paste or glue (e.g., Ag paste, Cu paste, Al paste, or the like). 
       FIG.  1 B ′ illustrates an enlarged view of a portion of the semiconductor device package  1  encircled by a dotted-line box A 1 , in accordance with some embodiments of the present disclosure. The structure illustrated in  FIG.  1 B ′ is similar to the structure as shown in  FIG.  1 B , and some of the differences therebetween are described below. 
     The conductive layer  10   p  is disposed on the surface  101  of the substrate  10 . The conductive layer  10   p  is not embedded within the substrate  10 . At least a portion of the conductive layer  10   p  is embedded within the adhesive layer  11 . The conductive layer  10   p  is in contact with the adhesive layer  11  and the conductive via  11   v.    
       FIG.  1 B ″ illustrates an enlarged view of a portion of the structure as shown in  FIG.  1 B ′ encircled by the dotted-line box B  1 , in accordance with some embodiments of the present disclosure. As shown in  FIG.  1 B ″, the adhesive layer  11  has a surface  113  and a surface  114  connected between the surface  112  and the surface  111  of the adhesive layer  11 . In some embodiments, the substrate  10  is disposed (or laminated) on the adhesive layer  11  to press the conductive layer  10   p  into the adhesive layer  11 . Duo to the stress applied by the substrate  10  and/or the conductive layer  10   p , the surface  113  has a curved surface, and a space may be defined among the conducive layer  10   p , the substrate  10 , and the adhesive layer  11 . The surface  113  is connected between the surface  112  and the surface  114 . The surface  114  is inclined. For example, the surface  114  is not perpendicular to the surface  111 . The surface  114  is connected between the surface  113  and the surface  111 . 
       FIG.  1 C  illustrates an enlarged view of a portion of the semiconductor device package  1  encircled by the dotted-line box A 1 , in accordance with some embodiments of the present disclosure. The structure illustrated in  FIG.  1 C  is similar to the structure illustrated in  FIG.  1 B , and the differences therebetween are described below. 
     As shown in  FIG.  1 C , the conductive pad  12   p  is fully exposed from the solder resist  12   r . For example, the conductive pad  12   p  is spaced apart from the solder resist  12   r . There is a gap between a lateral surface  12   p   3  of the conductive pad  12   p  and the solder resist  12   r . In the case that the conductive via  11   v  includes a soldering material (e.g., Sn) (which has a relatively higher fluidity after a reflow operation), the portion  11   v   2  of the conductive via  11   v  is further disposed within the gap between a lateral surface  12   p   3  of the conductive pad  12   p  and the solder resist  12   r  as shown in  FIG.  1 C . The portion  11   v   2  of the conductive via  11   v  is in contact with the surface  12   p   2  and the lateral surface  12   p   3  of the conductive pad  12   p . In the case that the conductive via  11   v  includes a conductive paste (which has a relatively lower fluidity after a reflow operation), the conductive via  11   v  may not be disposed within the gap between a lateral surface  12   p   3  of the conductive pad  12   p  and the solder resist  12   r . Hence, the gap between a lateral surface  12   p   3  of the conductive pad  12   p  and the solder resist  12   r  may be filled with air. 
       FIG.  1 C ′ illustrates an enlarged view of a portion of the semiconductor device package  1  encircled by a dotted-line box A 1 , in accordance with some embodiments of the present disclosure. The structure illustrated in  FIG.  1 C ′ is similar to the structure as shown in  FIG.  1 C , and some of the differences therebetween are described below. 
     The conductive layer  10   p  is disposed on the surface  101  of the substrate  10 . The conductive layer  10   p  is not embedded within the substrate  10 . At least a portion of the conductive layer  10   p  is embedded within the adhesive layer  11 . The conductive layer  10   p  is in contact with the adhesive layer  11  and the conductive via  11   v . In some embodiments, an enlarged view of a portion of the structure as shown in  FIG.  1 C ′ encircled by the dotted-line box B 1  is the same as or similar to the structure as shown in  FIG.  1 B ″. 
       FIG.  1 D  illustrates an enlarged view of a portion of the semiconductor device package  1  encircled by the dotted-line box A 1 , in accordance with some embodiments of the present disclosure. The structure illustrated in  FIG.  1 D  is similar to the structure illustrated in  FIG.  1 C , except that a portion of the adhesive layer  11  may bend downwardly by the stress applied by the substrate  10 . In some embodiments, the bended portion of the adhesive layer  11  is in contact with the conductive pad  12   p . In some embodiments, the bended portion of the adhesive layer  11  does not contact the conductive pad  12   p , and thus there is a channel (or gap) between the adhesive layer  11  and the conductive pad  12   p , which allows the conductive material flowing through the channel to fill the space defined by the solder resist  12   r  and the conductive pad  12   p.    
       FIG.  1 D ′ illustrates an enlarged view of a portion of the semiconductor device package  1  encircled by a dotted-line box A 1 , in accordance with some embodiments of the present disclosure. The structure illustrated in  FIG.  1 D ′ is similar to the structure as shown in  FIG.  1 D , and some of the differences therebetween are described below. 
     The conductive layer  10   p  is disposed on the surface  101  of the substrate  10 . The conductive layer  10   p  is not fully embedded within the substrate  10 . For example, the conductive layer  10   p  may fully protrude from the surface  101  of the substrate  10 . For example, the conductive layer  10   p  may have a portion protruding from the surface  101  of the substrate  10  and the other portion embedded within the substrate  10 . At least a portion of the conductive layer  10   p  is embedded within the adhesive layer  11 . The conductive layer  10   p  is in contact with the adhesive layer  11  and the conductive via  11   v.    
       FIG.  1 D ″ illustrates an enlarged view of a portion of the structure as shown in  FIG.  1 D ′ encircled by the dotted-line box D 1 , in accordance with some embodiments of the present disclosure. As shown in  FIG.  1 D ″, the adhesive layer  11  has a surface  113  and a surface  114  connected between the surface  112  and the surface  111  of the adhesive layer  11 . The surface  113  has a curved surface. The surface  113  is connected between the surface  112  and the surface  114 . The surface  114  is inclined. The surface  114  is connected between the surface  113  and the surface  111 . 
     In some embodiments, the conductive layer  10   p  is in contact with the conductive via  11   v  and a surface  115  of the adhesive layer  11 . The conductive layer  10   p  does not contact the surface  112  of the adhesive layer  11 . Therefore, the surface  115  is lower than the surface  112  due to the stress applied by the conductive layer  10   p . For example, the surface  115  and the surface  112  have different elevations with respect to the substrate  12 . 
       FIG.  1 D ′″ illustrates an enlarged view of a portion of the structure as shown in  FIG.  1 D ″ encircled by the dotted-line box El, in accordance with some embodiments of the present disclosure. As shown in  FIG.  1 D ′″, due to the manufacturing process (which will be described in detail below), the conductive pad  12   p  may include a recess (e.g.,  1   p  and  1   q ). In some embodiments, a depth of a portion of the recess (e.g.,  1   p ) is greater than a depth of another portion of the recess (e.g.,  1   q ). In some embodiments, a portion of the conductive material (e.g., the conductive via  11   v ) is disposed within the recesses (e.g.,  1   p  and  1   q ). 
     Referring to  FIG.  1 A , the electronic components  13   a ,  13   b , and  13   c  are disposed on the surface  121  of the substrate  12 . The electronic components  13   a ,  13   b , and  13   c  are electrically connected to the substrate  12 . The electronic component  13   a  may include a connector or socket to provide electrical connections between the semiconductor device package  1  and other circuits or circuit boards. The electrical component  13   c  may be an active component, such as an integrated circuit (IC) chip or a die. The electrical component  13   b  may be a passive electrical component, such as a capacitor, a resistor or an inductor. Each electrical component  13   a ,  13   b ,  13   c  may be electrically connected to one or more of another electrical component  13   a ,  13   b ,  13   c  and to the substrate  11  (e.g., to the RDL), and electrical connection may be attained by way of flip-chip or wire-bond techniques. 
     The package body  14  is disposed on a portion of the surface  121  of the substrate  12 . The package body  14  covers or encapsulates the electronic components  13   b  and  13   c . The package body  14  exposes the electronic component  13   a . In some embodiments, the package body  14  includes an epoxy resin having fillers, a molding compound (e.g., an epoxy molding compound or other molding compound), a polyimide, a phenolic compound or material, a material with a silicone dispersed therein, or a combination thereof. 
     The shielding layer  15  is disposed on an external surface of the package body  14  and covers the package body  14 , electronic components  13   b ,  13   c  and a portion of a lateral surface the substrate  12 . The shielding layer  15  may b 3  electrically connected to a grounding element of the substrate  12 . In some embodiments, the shielding layer  15  is a conformal shield. In some embodiments, the shielding layer  15  is a conductive thin film, and may include, for example, Al, Cu, Cr, Sn, Au, Ag, Ni or stainless steel, or a mixture, an alloy, or other combination thereof. The shielding layer  15  may include a single conductive layer or multiple conductive layers. 
       FIG.  2 A ,  FIG.  2 A ′,  FIG.  2 B ,  FIG.  2 B ′,  FIG.  2 B ″,  FIG.  2 C ,  FIG.  2 C ′,  FIG.  2 D ,  FIG.  2 E , and  FIG.  2 F  are cross-sectional views of a semiconductor device package at various stages of fabrication, in accordance with some embodiments of the present disclosure. At least some of these figures have been simplified for a better understanding of the aspects of the present disclosure. In some embodiments, the method illustrated in  FIG.  2 A ,  FIG.  2 A ′,  FIG.  2 B ,  FIG.  2 B ′,  FIG.  2 B ″,  FIG.  2 C ,  FIG.  2 C ′,  FIG.  2 D ,  FIG.  2 E , and  FIG.  2 F  may be used to manufacture the semiconductor device package  1  as shown in  FIG.  1 A . 
     Referring to  FIG.  2 A , a strip of substrates including a substrate  12  is provided. The substrate  12  has one or more conductive pads  12   p  adjacent to a surface  122  of the substrate  12 . An adhesive layer  11  is disposed on the surface  122  of the substrate  12  by, for example, lamination. 
       FIG.  2 A ′ illustrates an enlarged view of a portion of the structure encircled by a dotted-line box A 2  as shown in  FIG.  2 A , in accordance with some embodiments of the present disclosure. As shown in  FIG.  2 A ′, the substrate  12  includes a solder resist  12   r  covering a portion of the conductive pad  12   p . For example, the solder resist  12   r  may cover a lateral surface and a portion of a surface  12   p   2  of the conductive pad  12   p . The adhesive layer  11  is in contact with the solder resist  12   r . Hence, the conductive pad  12   p  is spaced apart from the adhesive layer  11  by the solder resist  12   r . For example, a space  12   s  is defined between the adhesive layer  11  and the conductive pad  12   p . For example, the conductive pad  12  and the adhesive layer  11  are not overlapping in a direction substantially parallel to the surface  122  of the substrate  12 . In some embodiments, a width of the space  12   s  is less than a width of the conductive pad  12   p.    
     In some embodiments, the solder resist  12   r  may not cover the conductive pad  12   p . For example, similar to the structure as shown in  FIG.  1 C , the solder resist  12   r  is spaced apart from the lateral surface and the surface  12   p   2  of the conductive pad  12   p . However, the solder resist  12   r  is thicker than the conductive pad  12   p , and thus the conductive pad  12   p  is still spaced apart from the adhesive layer  11 . 
     Referring to  FIG.  2 B , an opening  11   h  is formed to fully penetrate the adhesive layer  11  to expose the space  12   s.    
       FIG.  2 B ′ illustrates an enlarged view of a portion of the structure encircled by a dotted-line box B 2  as shown in  FIG.  2 B , in accordance with some embodiments of the present disclosure. As shown in  FIG.  2 B ′, the opening  11   h  is formed over the conductive pad  12   p  or the space  12   s . In some embodiments, the opening  11   h  is tapered from a surface  112  of the adhesive layer  11  toward the solder resist  12   r . For example, a width of the opening  11   h  adjacent to the surface  112  of the adhesive layer  11  is less than a width of the opening  11   h  adjacent to the solder resist  12   r . In some embodiments, the width of the opening  11   h  adjacent to the surface  112  of the adhesive layer  11  is less than the width of the space  12   s.    
     In some embodiments, the opening  11   h  can be formed by laser drill, mechanical drill, etching or any other suitable processes. In the case that the opening  11   h  is formed by laser drill, a laser beam is applied to the surface  112  of the adhesive layer  11  to cut through the adhesive layer  11 . In some embodiments, the laser beam would also radiated on the surface  12   p   2  of the conductive pad  12   p  after the adhesive layer  11  has been cut through. For example, as shown in  FIG.  2 B ″, which illustrates a top view of the conductive pad  12  (the cross-sectional view of the structure in  FIG.  2 B ″ taken along the line L 2 B is as shown in  FIG.  1 D ′″), a laser trace  1   g  may be formed on the surface  12   p   2  of the conductive pad  12   p . The laser trace  1   g  may define a groove or trench. The laser trace  1   g  may be circular or other shapes depending on design specifications. The laser trace  1   g  may be a closed-loop trace. For example, the starting point of the laser trace  1   g  and the ending point are substantially the same point (e.g, the point  1   p ). In some embodiments, a depth of the point  1   p  of the laser trace  1   g  is greater than a depth of the other portion of the laser trace  1   g . In some embodiments, a length of the point  1   p  of the laser trace  1   g  is less than a length of the other portion of the laser trace  1   g . In some embodiments, the laser trace  1   g  is substantially aligned with the sidewall of the opening  11   h  in a vertical direction. 
     In some embodiments, a central portion of the surface  12   p   2  surrounded by the laser trace  1   g  and an outer portion of the surface  12   p   2  surrounding the laser trace  1   g  are not suffered from laser beam. Hence, a roughness of the central portion of the surface  12   p   2  of the conductive pad  12   p  is less than a roughness of the laser trace  1   g . A roughness of the outer portion of the surface  12   p   2  of the conductive pad  12   p  is less than a roughness of the laser trace  1   g . The roughness of the central portion of the surface  12   p   2  of the conductive pad  12   p  is substantially the same as the roughness of the outer portion of the surface  12   p   2  of the conductive pad  12   p . In some embodiments, a roughness of the point  1   p  of the laser trace  1   g  is larger than a roughness of other portions of the laser trace  1   g . The central portion and the outer portion of the surface  12   p   2  may be separated from each other by the laser trace  1   g.    
     Referring to  FIG.  2 C , a conductive material may be disposed within the opening  11   h  and to form a conductive via  11   v .  FIG.  2 C ′ illustrates an enlarged view of a portion of the structure encircled by a dotted-line box C 2  as shown in  FIG.  2 C , in accordance with some embodiments of the present disclosure. As shown in  FIG.  2 C ′, the conductive material is disposed within the space  12   s  to form the portion  11   v   2  of the conductive via  11   v , and the conductive material is disposed within the opening  11   v   1  to form the portion  11   v   2  of the conductive via  11   v . The conductive via  11   v  is in contact with the surface  12   p   2  of the conductive pad  12   p . The conductive via  11   v  is in contact with the solder resist  12   r  and the adhesive layer  11 . In some embodiments, the conductive via  11   v  may include a flowable conductive material (e.g., soldering material). In some embodiments, the conductive via  11   v  may include a conductive paste or glue (e.g., Ag paste, Cu paste, Al paste, or the like). 
     In some embodiments, the solder resist  12   r  can be omitted, and the adhesive layer  11  (or a molding compound) is in direct contact with the conductive pad  12   p . After a portion of the adhesive layer  11  (or molding compound) is removed by a laser drilling to form via holes, a portion of the adhesive layer  11  (or molding compound) may remain on the surface  12   p   2  of the conductive pad  12 . An additional operation (e.g., laser polish, etching or the like) should be carried out to remove the remaining adhesive layer (or molding compound) on the surface  12   p   2  of the conductive pad  12   p . However, said additional operation may increase the roughness of the surface  12   p   2  of the conductive pad  12   p , which adversely affects the electrical performance between the conductive via  11   v  and the conductive pad  12   p . In addition, said additional operation may increase the cost and time for manufacturing the conductive via  11   v.    
     In accordance with the embodiments as shown in  FIGS.  2 A,  2 A ′,  2 B,  2 B′,  2 B″,  2 C, and  2 C′, the adhesive layer  11  is vertically spaced apart from the conductive pad  12   p , and thus no residue remains on the surface  12   p   2  of the conductive pad  12   p  after a portion of the adhesive layer  11  is removed to form the opening  11   h . Therefore, no additional operation (e.g., laser polish, etching or the like) is required to be carried out on the surface  12   p   2  of the conductive pad  12   p  to increase the roughness of the surface  12   p   2  of the conductive pad  12   p . The electrical connection between the conductive pad  12   p  and the conductive via  11   v  can be improved. In addition, the cost and time for manufacturing the conductive via  11   v  can be reduced. 
     Referring to  FIG.  2 D , a substrate  10  is disposed on a surface  112  of the adhesive layer  11  facing away from the substrate  12 . A surface  101  of the substrate  10  is connected to the adhesive layer  11 . The substrate  10  may include one or more conductive layers  10   a ,  10   b ,  10   p  and one or more dielectric layers  10   d . The conductive layer  10   p  is electrically connected with the conductive pad  12   p  through the conductive via  11   v . In some embodiments, the conductive layers  10   a ,  10   b  define or include antenna patterns. For example, the conductive layer  10   b  may function as a radiator. For example, the conductive layer  10   a  may function as a director. The conductive layer  10   b  may be electromagnetically coupled to the conductive layer  10   a  for signal transmission. One or more conductive vias  10   f  may be electrically connected between conductive layers to provide electrical connections therebetween. In some embodiments, the conductive via  10   f  may function as a feeding line for the antenna (e.g., the conductive layer  10   b ). 
     Referring to  FIG.  2 E , electronic components  13   b  and  13   c  are disposed on the surface  121  of the substrate  12  and electrically connected to the substrate  12  by, for example, surface-mount-technology (SMT). 
     A package body  14  is formed on a portion of the surface  121  of the substrate  12  and covers the electronic component  13   b ,  13   c . In some embodiments, the package body  14  may be formed by, for example, selective molding or other techniques. For example, the package  14  may be formed by the following operations: (i) forming a protection layer (e.g., water cleaning glue) on a portion of the surface  121  of the substrate  12  on which the package body will not be formed (or the electronic components  13   b ,  13   c  are not located); (ii) forming a molding compound to cover the surface  121  of the substrate  12 , the protection layer, and the electronic components  13   b ,  13   c ; (iii) forming one or more openings to fully penetrate the molding compound to expose the protection layer by, for example, laser ablation; and (iv) applying water on the exposed protection layer to remove the protection layer along with the molding compound on the protection layer and to remain the package body  14  that covers the electronic components  13   b ,  13   c  as shown in  FIG.  2 E . 
     In some embodiments, singulation may be performed to separate out individual semiconductor package devices including the structure as shown in  FIG.  2 E . That is, the singulation is performed through the package body  14 , the substrate strip including the substrates  12 , the adhesive layer  11 , and the substrate  10 . The singulation may be performed, for example, by using a dicing saw, laser or other appropriate cutting techniques. 
     After singulation, a shielding layer  15  is formed on an external surface of the package body  14 . The shielding layer  15  further extends along at least a portion of a lateral surface of the substrate  12 . In some embodiments, the shielding layer  15  may be formed by, for example, selective sputtering or any other suitable processes. 
     Referring to  FIG.  2 F , an electronic component  13   a  (e.g., a connector or a socket) is disposed on a portion of the surface  121  of the substrate  12  on which the package body  14  is not disposed. The electronic component  13   a  may be disposed on the substrate  12  and electrically connected to the substrate  12  by, for example, SMT or any other suitable operations. 
     Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper,” “left,” “right” and the like, may be used herein for ease of description to describe one element or feature&#39;s relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. It should be understood that when an element is referred to as being “connected to” or “coupled to” another element, it may be directly connected to or coupled to the other element, or intervening elements may be present. 
     As used herein, the terms “approximately”, “substantially”, “substantial” and “about” are used to describe and account for small variations. When used in conduction with an event or circumstance, the terms can refer to instances in which the event or circumstance occurs precisely as well as instances in which the event or circumstance occurs to a close approximation. As used herein with respect to a given value or range, the term “about” generally means within ±10%, ±5%, ±1%, or ±0.5% of the given value or range. Ranges can be expressed herein as from one endpoint to another endpoint or between two endpoints. All ranges disclosed herein are inclusive of the endpoints unless specified otherwise. The term “substantially coplanar” can refer to two surfaces within micrometers (μm) of lying along the same plane, such as within 10 μm, within 5 μm, within 1 μm, or within 0.5 μm of lying along the same plane. When referring to numerical values or characteristics as “substantially” the same, the term can refer to the values lying within ±10%, ±5%, ±1%, or ±0.5% of an average of the values. 
     The foregoing outlines features of several embodiments and detailed aspects of the present disclosure. The embodiments described in the present disclosure may be readily used as a basis for designing or modifying other processes and structures for carrying out the same or similar purposes and/or achieving the same or similar advantages of the embodiments introduced herein. Such equivalent constructions do not depart from the spirit and scope of the present disclosure, and various changes, substitutions, and alterations may be made without departing from the spirit and scope of the present disclosure.