Patent Publication Number: US-6714450-B2

Title: Word programmable EEPROM memory comprising column selection latches with two functions

Description:
FIELD OF THE INVENTION 
     The present invention relates to integrated circuits, and more particularly, to an electrically erasable and programmable and memory (EEPROM). 
     BACKGROUND OF THE INVENTION 
     EEPROM devices belong to two categories: page programmable memories and word programmable memories. A word generally represents a byte (8 bits), and a page generally represents a set of words belonging to a same word line. Page programmable memories require a high number of programming latches. More particularly, they require as many programming latches as there are bit lines to ensure a simultaneous programming of all the words of a page. In contrast, word programmable memories require a reduced number of latches, for example, eight programming latches for a byte programmable memory. 
     FIG. 1 schematically illustrates the conventional architecture of a memory MEM 1  of the second type, i.e., one that is programmable by word. The memory comprises word lines WL i , bit lines BL j  arranged in columns COL k , with each illustrated column comprising eight bit lines BL 0  to BL 7 , and memory cells CE i,j . The memory cells CE i,j  are arranged in an array and are connected to the word lines WL i  and the bit lines BL j . 
     Each cell CE i,j  comprises a floating gate transistor FGT and an access transistor TA. The access transistor TA has its gate G connected to a word line WL i , its drain D connected to a bit line BL j , and its source S connected to the drain D of transistor FGT. Transistor FGT has its gate G coupled to a column selection line CL k  by a gate control transistor CGT i,k , and its source S is connected to a source line SL i . The gate of transistor CGT i,k  is connected to word line WL i . 
     Thus, each group of eight cells CE i,j  connected to a word line WL i  and to the bit lines BL 0  to BL 7  of a column COL k  forms a word W i,k  that may be selected by the corresponding column selection line CL k  and word line WL i . To this effect, the word lines WL i  are connected to the outputs of a line decoder RDEC. The column selection lines CL k  are connected to latches LSC k  delivering a gate control signal CGS k  which depends on a column selection signal SEL k  received as an input. The selection signal SEL k  is delivered by a column decoder CDEC. Line decoder RDEC and column decoder CDEC receive respectively the most significant bits and the less significant bits of an address AD applied to the memory. Source line SL i  may be brought to a floating potential or may be connected to ground by a transistor SLT driven by a signal SLS. 
     Memory MEM 1  also comprises eight programming latches LP 0  to LP 7 , the outputs of which are connected to lines L 0  to L 7 , and eight sense amplifiers SA 0  to SA 7 , the inputs of which are connected to the lines L 0  to L 7  by read transistors TR 0  to TR 7  driven by a signal READ. The outputs of amplifiers SA 0  to SA 7  and the inputs of latches LP 0  to LP 7  are connected to a data bus DTB, allowing data read in the memory to be delivered by amplifiers SA 0  to SA 7  or data to be programmed in the memory to be loaded into programming latches LP 0  to LP 7 . 
     Lines L 0  to L 7  are coupled to the bit lines BL 0  to BL 7  of each column COL k  by a multiplex bus DMB. Each programming latch LP j  of rank j is thus connected to the bit lines of the same rank j present in the columns. To ensure a selective connection of the output of a latch or of the input of a sense amplifier to a predetermined bit line, each bit line BL 0 -BL 7  of each column COL k  is provided with a selection amplifier or transistor TSBL 0  to TSBL 7 . Selection transistors TSBL 0  to TSBL 7  of the bit lines of a same column COL k  are driven by a common selection signal BLS k , delivered by a latch LSBL k  receiving as an input a column selection signal SEL k  coming from column decoder CDEC. 
     There can thus be found in each column of rank k of memory MEM 1  a column selection latch LSC k  and a bit lines selection latch LSBL k  which are driven by a common column selection signal SEL k  coming from column decoder CDEC. These latches deliver a gate control signal CGS k  and a bit line selection signal BLS k . The values of these signals depend on the current operating phase, that is, erasure, programming or reading of a cell. 
     An erasing or programming operation of a memory cell includes injecting or extracting electrical charges by the Fowler Nordheim effect in the floating gate of the transistor FGT of the cell. An erased transistor FGT has a positive threshold voltage VT 1 , and a programmed transistor FGT has a negative threshold voltage VT 2 . 
     When a reading voltage Vread between VT 1  and VT 2  is applied to its gate, an erased transistor remains turned OFF, which corresponds by convention to a logic 1, and a programmed transistor is turned ON, which corresponds by convention to a logic 0. The erasing operation is performed by applying an erasing voltage Vpp on the order of 12 to 20 V to the gate G of transistor FGT while source line SL i  is brought to ground. The programming operation is performed by applying a programming voltage Vpp to the drain D of transistor FGT by an access transistor TA, while its gate is brought to ground. 
     During an erasing phase of the memory cells of a word W i,k , the latch LSC k  and the latch LSBL k  of the concerned column are activated by signal SEL k . Latch LSC k  delivers a gate control signal CGS k  equal to Vpp, and latch LSBL k  delivers a voltage equal to zero (ground). During a programming phase of the memory cells of word W i,k , latch LSC k  delivers a voltage equal to zero (ground) and latch LSBL k  delivers voltage Vpp so that the transistors TSBL 0  to TSBL 7  of the column are turned ON and couple the outputs of the programming latches LP j  to the bit lines of the column. During a reading phase of word W i,k , latch LSC k  delivers a reading voltage Vread and latch LSBL k  delivers a voltage Vcc so that the transistors TSBL 0  to TSBL 7  of the column are turned ON and couple the inputs of the sense amplifiers SA j  to the bit lines of the column. Read transistors TR j  are also turned ON and signal READ is at 1. 
     As mentioned above, the advantage of such a memory is to have a small number of programming latches, such as the eight latches LP 0  to LP 7 , for example, when a page programmable memory comprises as many programming latches as bit lines. The providing of transistors TSBL 0  to TSBL 7  is necessary to ensure the connection of a programming latch to a predetermined bit line. The providing of transistors TSBL 0  to TSBL 7  implies the providing of the latches LSBL k  to drive such transistors. 
     In other words, the bit line selection latches LSBL k  make it difficult to reduce the number of programming latches, and complicates the structure of the memory. Thus, for example, a word programmable memory comprising 2048 bit lines arranged in 256 columns must be provided with 256 column selection latches and 256 bit lines selection latches. The latches each comprise a locking element of the selection signal SEL k  so that the delivered signals CGS k  and BLS k  remain stable until a reset signal is applied to the latches. 
     SUMMARY OF THE INVENTION 
     In view of the foregoing background, an object of the present invention is to simplify the architecture of a EEPROM device. The present invention is based on the observation that the locking element comprised in a column selection latch can be used to generate and/or control the selection signal of the bit lines of the column, in addition to the gate control signal provided for the floating gate transistors. 
     This and other objects, advantages and features according to the present invention are provided by integrating, in a same latch comprising one locking element only, the column selection function and the bit lines selection function. The latch includes two outputs, one for delivering the gate control signal and the other for delivering the bit lines selection signal. 
     More particularly, the present invention provides an electrically programmable and erasable memory comprising memory cells connected to word lines and bit lines arranged in columns, bit lines selection transistors driven by bit lines selection signals, and column selection latches comprising each a locking element for a column selection signal and means for delivering a gate control signal which depends on the output of the locking element. Each column selection latch comprises means for delivering, in addition to a gate control signal, a bit lines selection signal which depends on the output of the locking element, at least during programming and reading phases of memory cells. 
     The column selection latch in the active state may deliver, during programming periods of the memory cells, a gate control signal equal to zero and a bit lines selection signal equal or substantially equal to a programming high voltage. 
     The column selection latch in the active state may deliver, during erasing periods of the memory cells, a gate control signal equal to an erasing high voltage and a bit lines selection signal equal to zero. Alternatively, the column selection latch in the active state may deliver, during erasing periods of memory cells, a gate control signal equal to an erasing high voltage and a bit lines selection signal equal or substantially equal to the erasing high voltage. 
     The memory may comprise insulating transistors disposed between the bit lines and outputs of the programming latches. The column selection latch may comprise a switching means having a control terminal connected to the output of the locking element, an input terminal receiving a gate control voltage and an output terminal delivering the gate control signal. 
     The column selection latch may comprise a conductive track, an end of which is connected to the output of the locking element, and the other end of which delivers the bit lines selection signal. The column selection latch may also comprise a second switching means having a control terminal connected to the output of the locking element, an input terminal receiving a predetermined voltage, and an output terminal delivering the bit lines selection signal. 
     The column selection latch may comprise an inverting gate electrically supplied with a predetermined voltage, the input of which is connected to a node of the locking element and the output of which delivers the bit lines selection signal. The predetermined voltage may be identical to a supply voltage applied to the locking element. Alternatively, the predetermined voltage may be a voltage equal to zero during erasing phases of memory cells. 
     The present invention also relates to a method of selecting bit lines in an electrically programmable and erasable memory comprising memory cells connected to word lines and bit lines arranged in columns, bit lines selection transistors driven by bit lines selection signals, and column selection latches. Each column selection latch comprises a locking element of a column selection signal, and means for delivering a gate control signal which depends on the output of the locking element. Each column selection latch, in addition to delivering a gate control signal, includes means for delivering a bit lines selection signal which depends on the output of the locking element, at least during programming and reading phases of the memory cells. 
     The method may comprise providing, in a column selection latch, a switching means having a control terminal connected to the output of the locking element, an input terminal receiving a predetermined voltage, and an output terminal delivering the bit lines selection signal. 
     The method may comprise providing, in a column selection latch, an inverting gate electrically supplied with a predetermined voltage, the input of and the output of which delivers the bit lines which is connected to a node of the locking element, selection signal. The predetermined voltage may be chosen identical to a supply voltage applied to the locking element. Alternatively, the predetermined voltage may be a voltage equal to zero during erasing phases of memory cells. 
     The method further comprises providing insulating transistors disposed between the bit lines and outputs of the programming latches. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     These objects, characteristics and advantages as well as others of the present invention will be described with more details in the following description of an embodiment of a memory according to the invention, done in a non limiting way, in conjunction with the accompanying drawings, among which: 
     FIG. 1 shows an architecture of a word programmable EEPROM device according to the prior art, 
     FIG. 2 shows a column selection latch in a word programmable EEPROM device according to the prior art, 
     FIG. 3 shows a bit lines selection latch in a word programmable EEPROM memory according to the prior art, 
     FIG. 4 shows a column selection latch according to the present invention, 
     FIG. 5 shows an architecture of a word programmable EEPROM device comprising column selection latches according to the present invention, 
     FIGS. 6A,  6 B and  6 C respectively show electrical voltages appearing in the memory according to the present invention during erasing, programming and reading phases; and 
     FIGS. 7 and 8 respectively show alternative embodiments of column selection latches according to the present invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 2 shows a conventional embodiment of a column selection latch LSC k  and FIG. 3 shows a conventional embodiment of a bit lines selection latch LSBLk. These two elements are used in the memory MEM 1  described above in relation with FIG.  1 . 
     Column select latch LSC k  comprises a locking element ME 1  in the form of an inverting memory cell, formed by two inverting gates connected top to bottom and supplied with a voltage Vpol. The input of cell ME 1  is coupled to ground by a NMOS transistor T 1 , the gate of which is driven by the column selection signal SEL k  delivered by column decoder CDEC (FIG.  1 ). The output of memory cell ME 1  is coupled to ground by a NMOS transistor T 2 , the gate of which is driven by a reset signal RLAT 1  (Reset Latch). The output of memory cell ME 1  drives the gate of a NMOS transistor T 3  receiving on its drain a gate control voltage Vcg, and delivers on its source the gate control signal CGS k  described above. This signal is applied to floating gate transistors FGT by a gate control transistor CGT i,k  (FIG.  1 ). 
     Bit lines selection latch LSBL k  comprises a locking element ME 2 . Locking element ME 2  is an inverting memory cell formed by two inverting gates connected top to bottom and supplied with a voltage Vpol. The input of cell ME 2  is coupled to ground by a NMOS transistor T 4 , the gate of which is driven by column selection signal SEL k . The output of memory cell ME 2  is coupled to ground by a NMOS transistor T 5 , the gate of which is driven by a reset signal RLAT 2 . The output of memory cell ME 2  drives the gate of a NMOS transistor T 6  receiving on its drain a voltage Vsel. Transistor T 6  delivers on its source a bit lines selection signal BLS k  applied to bit lines selection transistors TSBL 0  to TSBL 7  (FIG.  1 ). 
     During erasing phases of memory cells, voltages Vpol and Vcg are equal to Vpp, and voltage Vsel is equal to zero. During programming phases, voltages Vpol and Vsel are equal to Vpp, and voltage Vcg is equal to zero. During reading phases, voltages Vpol and Vsel are equal to a voltage Vcc, which is generally the memory supply voltage, and voltage Vcg is chosen substantially equal to a reading voltage Vread. 
     To simplify the architecture of a word programmable EEPROM memory, the present invention provides the integration of the two latches LSC k  and LSBL k  into one latch comprising an input for receiving selection signal SEL k  and two outputs for respectively delivering the gate control signal CGS k  and the bit lines selection signal BLS k . 
     FIG. 4 shows an embodiment of a latch LSCI k  according to the invention. Latch LSCI k  comprises a locking element ME k  having, for example, the form of an inverting memory cell formed by two inverting gates INV 1 , INV 2  connected top to bottom and supplied with a voltage Vpol. The input of cell ME k  is coupled to ground by a NMOS transistor T 10 , the gate of which is driven by column selection signal SEL k . Thus, when signal SEL k  passes to 1, the output of cell ME k  passes also to 1. The output of cell ME k  is coupled to ground of a NMOS transistor T 11 , the gate of which is driven by a reset signal RLAT. Furthermore, the output of memory cell ME k  drives the gate of a NMOS transistor T 12  receiving on its drain the gate control voltage Vcg. Transistor T 12  delivers on its source the gate control signal CGS k . According to the invention, the input of cell ME k  is connected to the input of an inverting gate INV 3  supplied with voltage Vpol, the output of which delivers the bit lines selection signal BLS k . 
     Optionally, latch LSCI k  comprises also a NMOS transistor T 13  arranged in parallel with transistor T 11  and driven by a signal INC. This signal INC, different from signal RLAT, allows a cascade reset of latches arranged in various columns during a sequential reading of a whole page of the memory, with a scanning of the column addresses. 
     FIG. 5 shows a memory MEM 2  incorporating latches LSCI k  according to the invention. Memory MEM 2  has in a general way the same structure as the memory MEM 1  of FIG.  1  and will not be described again, with the various elements being designated by the same references. 
     Memory MEM 2  distinguishes from the conventional memory MEM 1  by the fact that the column selection latches LSC k  as well as the bit lines selection latches LSBL k  are suppressed and replaced by latches LSCI k  according to the invention. Latches LSCI k  deliver in each column the gate control signal CGS k  and the bit lines selection signal BLS k . 
     Memory MEM 2  also comprises eight insulating transistors TI 0  to TI 7  arranged on the lines L 0  to L 7  downstream from the outputs of programming latches LP 0  to LP 7  and upstream from the demultiplex bus DMB. The gates of the insulating transistors are driven by the voltage Vsel mentioned above in relation to FIG.  3 . 
     FIGS. 6A,  6 B and  6 C respectively show the values of the voltages Vpol, Vcg and Vsel during the erasing (1), programming (2) and reading (3) phases. During the erasing phases, voltages Vpol and Vcg are equal to the high voltage Vpp and voltage Vsel is at zero (ground). During the programming phases (2), voltages Vpol and Vsel are equal to the high voltage Vpp, and voltage Vcg is at zero. During the reading phases (3), voltages Vpol and Vsel are equal to the memory supply voltage Vcc, and voltage Vcg is equal to the reading voltage Vread. 
     Memory MEM 2  operates as follows. During an erasing phase of the memory cells of a word W i,k , the corresponding word line WL i  is brought to voltage Vpp by decoder RDEC. The latch LSCI k  of the column COL k  is activated by the signal SEL k  delivered by decoder CDEC, and delivers a gate control signal CGS k  and a bit lines selection signal BLS k  equal to Vpp. When the selection transistors TSBL k  is turned ON, the insulation of the bit lines BL j  in relation to the outputs of programming latches LP j  is ensured by the insulating transistors TI j  because voltage Vsel is equal to zero. In parallel, source line SL i  is connected to ground by transistor SLT. The floating gate transistors FGT of word W i,k  receive the erasing voltage Vpp on their gate by the gate control transistor CGT i,k  and their source is brought to ground, causing an extraction of the charges trapped in the floating gates and the erasing of transistors FGT. 
     During a programming phase of the memory cells of a word W i,k , the programming latches LP 0  to LP 7  deliver a programming high voltage Vpp or a voltage equal to zero, according to the value of the bits which have been loaded before therein by the data bus DTB. Word line WL i  is brought to voltage Vpp by decoder RDEC. Latch LSCI k  is activated by signal SEL k  and delivers again a gate control signal CGS k  and a bit lines selection signal BLS k  equal to Vpp. The transistors TSBL j  of the column and insulating transistors TI j  let pass the voltage Vpp delivered by the programming latches in the bit lines of the column. The floating gate transistors FGT have their gates brought to ground by the gate control transistor CGT i,k  of the word W i,k , (Vcg=0). Source line SL i  is brought to a floating potential. Transistors FGT receive thus on their drain the voltage Vpp or the zero voltage delivered by a programming latch, and those which receive voltage Vpp are programmed by the Fowler-Nordheim effect and injection of charges in their floating gate. 
     During a reading phase of the memory cells of a word W i,k , latch LSCI k  is activated by selection signal SEL k  and delivers a gate control signal CGS k  equal to Vread (Vcg=Vread) and a bit lines selection signal BLS k  equal to Vcc (Vpol=Vcc). The transistors TSBL j  of the column are thus turned ON and let pass the voltage Vcc delivered by the sense amplifiers SA 0  to SA 7  in the concerned bit lines. Word line WL i  is brought to voltage Vcc by decoder RDEC. Source line SL i  is brought to ground. The floating gate transistors of word W i,k  have their gate brought to voltage Vread by gate control transistor CGT i,k  and their state ON or OFF is detected by the sense amplifiers SA 0  to SA 7 . 
     The present invention is of course likely to have various alternative embodiments. First, as illustrated in FIG. 4, a node N at the output of inverting gate INV 3  shows the same logic value  1  (Vpol) or  0  (ground) as a node M at the output of inverting cell ME k . Thus, in an alternative embodiment, signal BLS k  can be taken directly at node M by a conductive track. However, since signal BLS k  is applied to eight transistors TSBL 0  to TSBL 7 , the taking of this signal at the output of cell ME k  requires an increase in the size of the transistors forming the gates INV 1  and INV 2  (not represented), so that cell ME k  is capable of delivering enough current for simultaneously and rapidly charging the gate stray capacities of all the transistors. It has appeared simpler to the inventors to provide inverting gate INV 3  connected to a node L located at the input of cell ME k , as described above, without modifying the structure of cell ME k  in relation to the conventional column selection latch. 
     In one embodiment of the memory according to the invention, the insulating transistors TI 0  to TI 7  are integrated in the programming latches LP 0  to LP 7  and are no more located on the path linking the bit lines to the inputs of the sense amplifiers. It is then no longer necessary, in the mode reading, to turn ON the insulating transistors. 
     In an embodiment of a latch LSCI′ k  according to the invention, represented in FIG. 7, the output of cell ME k  drives, in addition to transistor T 12  delivering the gate control signal CGS k , a NMOS transistor T 14  which receives, on its drain, voltage Vsel and delivers the bit lines selection signal BLS k . In this embodiment, the bit lines selection signal BLS k  is at zero (ground) during the erasing phases and the insulating transistors TI 0  to TI 7  are no longer necessary. 
     The latch LSCI k  represented in FIG. 4 has, however, the advantage, when compared to the one of FIG. 7, of not receiving the voltage Vsel which is thus not used for generating the signal BLS k  delivered by the latch. Signal BLS k  is thus equal to Vpp during the erasing periods, and the bit lines selection transistors TSBL j  are turned ON. This is compensated by the providing of the insulating transistors TI 0  to TI 7  driven by voltage Vsel, which are turned OFF during the erasing periods when voltage Vsel is equal to 0. The column selection latch LSCI k  of FIG. 4 thus does not comprise a voltage Vsel switching transistor like the transistor T 14  of the latch of FIG.  7 . 
     This feature is advantageous when the number of latches LSCI k  is greater than eight, which is generally the case, and allows the suppression of as much voltage Vsel switching transistors as latches LSCI k  present in the memory. For example, there are 256 suppressed transistors (one for each latch LSCI k ) in a memory with 256 columns and 256 latches LSCI k . However, the main advantage of the present invention lies in the suppression of the bit lines selection latches and of the locking elements that they comprise, and the embodiment of FIG. 7 is within the scope of the present invention. 
     As another possible alternative, FIG. 8 shows a latch LSCI″ k  according to the invention, in which the inverting gate INV 3  is supplied with voltage Vsel and has its output connected to ground by a pull-down resistor of high value. In this embodiment, the bit lines selection signal BLS k  is also grounded during the erasing periods, because signal Vsel is at zero and gate INV 3  is not electrically supplied. The insulating transistors TI 0  to TI 7  are also not necessary in this embodiment. 
     It will be clearly apparent to one skilled in the art that various other embodiments are possible to design a column latch according to the invention, the main characteristic of which is to deliver a gate control signal CGS k  and a bit lines selection signal BLS k  which are controlled by the output of one element ME k  only, ensuring the locking of the column selection signal SEL k .