Patent Publication Number: US-2013241524-A1

Title: Band gap reference circuit

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention generally relates to a band gap reference circuit, such as a band gap reference circuit for outputting a reference voltage based on thermal voltage. 
     2. Description of the Related Art 
       FIG. 1  is a schematic diagram illustrating a configuration of a band gap reference circuit  10  according to a related art example. With the configuration illustrated in  FIG. 1 , the current density of a transistor Q 12  becomes 1/(m·n) in a case where the proportion (ratio) of the number of transistors between Q 11  and Q 12  (Q 11 :Q 12 ) is set to 1:n, and the proportion (ratio) of the resistance between R 11  and R 12  (R 11 :R 12 ) is set to 1:m. As a result, the following Formula (1) is obtained. 
         VBE 1− VBE 2= Vt· 1 n  ( m·n )   (1)
 
     In Formula (1), “VBE 1 ” indicates the voltage between the base and the emitter of the transistor Q 11 , “VBE 2 ” indicates the voltage between the base and the emitter of the transistor Q 12 , and “Vt” (=k·T/q) indicates the thermal voltage of the transistors Q 11 , Q 12 . “k” (=1.38×10 −23 ) indicates the Boltzmann constant, “T” indicates the absolute temperature, and “q” (=1.602×10 −19 ). For example, the thermal voltage is approximately 25.7 mV when the temperature is 25° C. 
     In a case where a resistor R 10  receives VBE 1 −VBE 2 , a current I 12  flowing in the transistor Q 12  is expressed with the following Formula (2), and a current I 11  flowing in the transistor Q 11  is expressed with the following Formula (3). 
         I 12= Vt· 1 n  ( m·n )/ R 10   (2)
 
         I 11= m·I 12   (3)
 
     VBE 1 −VBE 2  is a voltage having a positive (+) thermal coefficient, and a voltage having a positive thermal characteristic is generated in the resistors R 11 , R 12  that receive the current generated by the VBE 1 −VBE 2  and the resistor R 10 . The thermal characteristic of the forward voltage of a diode (i.e. the forward voltage of a PN junction between the base and the emitter of the transistors Q 11 , Q 12  that are connected to a diode) is negative, and the thermal characteristic of the voltage generated at the resistors R 11 , R 12  is positive. Accordingly, a band gap reference voltage that exhibits little thermal dependency can be output from an operational amplifier  11  by selecting the resistors R 11 , R 12  having the same absolute temperature coefficient. 
     However, there may be a case where the thermal dependency of the band gap reference voltage increases due to inconsistency of the resistance value of a resistor or the saturation current of a transistor caused by inconsistent manufacturing. In this case where the thermal dependency of the band gap reference voltage increases, Japanese Laid-Open Patent Publication No. 11-121694 discloses a technology for minimizing the thermal dependency of the band gap reference voltage VBG. This technology can change the current value of the current flowing in the resistor by cutting off a fuse element by laser radiation, so that the thermal dependency of the band gap reference voltage VBG can be minimized. 
     However, only the current flowing in the resistor connected to the fuse element can be reduced with the above-described technology of cutting the fuse element. Therefore, it is difficult to make slight adjustments for the size of the band gap reference voltage. 
     SUMMARY OF THE INVENTION 
     The present invention may provide a band gap reference circuit that substantially obviates one or more of the problems caused by the limitations and disadvantages of the related art. 
     Features and advantages of the present invention will be set forth in the description which follows, and in part will become apparent from the description and the accompanying drawings, or may be learned by practice of the invention according to the teachings provided in the description. Objects as well as other features and advantages of the present invention will be realized and attained by a band gap reference circuit particularly pointed out in the specification in such full, clear, concise, and exact terms as to enable a person having ordinary skill in the art to practice the invention. 
     To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, an embodiment of the present invention provides a band gap reference circuit including an output circuit configured to output a reference voltage based on a reference current generated by a voltage difference between a forward voltage of a PN junction of a first semiconductor device and a forward voltage of a PN junction of a second semiconductor device; and a adder/subtractor circuit configured to add or subtract a correction current with respect to the reference current. 
     Other objects and further features of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a schematic diagram illustrating a configuration of a band gap reference circuit  10  according to a related art example; 
         FIG. 2  is a schematic diagram illustrating a configuration of a band gap reference circuit according to the first embodiment of the present invention; 
         FIG. 3  is a schematic diagram illustrating a configuration of a band gap reference circuit according to the second embodiment of the present invention; 
         FIG. 4  is a schematic diagram illustrating a configuration of an operational amplifier according to an embodiment of the present invention; 
         FIG. 5  is a schematic diagram illustrating an example of a configuration of a reference voltage generation circuit according to an embodiment of the present invention; 
         FIG. 6  is a schematic diagram illustrating an example of a configuration of a correction circuit according to an embodiment of the present invention; and 
         FIG. 7  is a schematic diagram illustrating an example of a configuration of a startup circuit according to an embodiment of the present invention. 
     
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     In the following, embodiments of the present invention will be described with reference to the accompanying drawings. In the accompanying drawings, a transistor having a gate marked with a circle is a P channel type MOSFET whereas a transistor having a gate without a circle is a N channel type MOSFET. 
       FIG. 2  is a schematic diagram illustrating a configuration of a band gap reference circuit  20  according to the first embodiment of the present invention. As described below, the band gap reference circuit  20  utilizes a positive temperature characteristic exhibited by a voltage difference between a forward voltage of a PN junction of a first semiconductor device and a forward voltage of a PN junction of a second semiconductor device and a negative temperature characteristic exhibited by a forward voltage of a PN junction in which a reference current is generated by the aforementioned voltage difference. By utilizing the positive and negative temperature characteristics, the band gap reference circuit  20  can generate a band gap reference voltage VBG as a reference voltage which does not depend on temperature. 
     The band gap reference circuit  20  includes a reference voltage generation circuit  23  and a correction current adder/subtractor circuit  22  (hereinafter also referred to as “correction circuit  22 ”). It is to be noted that the term “correction” may also be referred to as “trimming”. 
     The reference voltage generation circuit  23  includes first and second semiconductor devices that are operated with current densities that are different from each other. In this embodiment, the first and second semiconductor devices are transistors Q 1  and Q 2 . The reference voltage generation circuit  23  is a circuit that outputs a band gap reference voltage VBG based on a reference current I 0 . The reference current I 0  is generated by the voltage difference between a forward voltage of a PN junction between the base and the emitter of the transistor Q 1  and a forward voltage of a PN junction between the base and the emitter of the transistor Q 2 . The correction circuit  22  is a circuit that adds or subtracts a correction current It with respect to the reference current I 0 . 
     Accordingly, with the reference voltage generation circuit  23  having the above-described configuration, the correction current It not only can be subtracted from the reference current I 0  but can also be added to the reference current I 0 . Therefore, slight adjustments for increasing or reducing the current I 1 , I 2  flowing in the resistors R 1 , R 2  can be performed. Thus, slight adjustments for increasing or decreasing the amount of the band gap reference voltage VBG can be easily performed. As a result, even if there is a variance of the band gap reference voltage VBG due to, for example, inconsistent manufacturing, the band gap reference voltage VBG can be easily corrected with high precision. Further, variance of the band gap reference voltage due to temperature can also be easily corrected with high precision. 
     Next, the configuration of the band gap reference circuit  20  is described in further detail. 
     The reference voltage generation circuit  23  includes an operational amplifier  21 , a first series circuit having the resistor R 1  and the transistor Q 1  connected in series between an output terminal of the operation amplifier  21  and a first voltage for substrate and source (hereinafter referred to as “VSS 1 ”), and a second series circuit having the resistor R 2  and the transistor Q 2  connected in series between the output terminal of the operational amplifier  21  and a second voltage for substrate and source (hereinafter referred to as “VSS 2 ”). The first and second series circuits are connected to each other in parallel. 
     The transistors Q 1 , Q 2  are diode-connected NPN bipolar transistors. The P-type region (base) of the transistor Q 1  is connected to one end part of the resistor R 1  toward a low potential side of the resistor R 1  (hereinafter referred to as “low potential end part of the resistor R 1 ”) whereas the P-type region (base) of the transistor Q 2  is connected to one end part of the resistor R 0  toward a low potential side of the resistor R 0  (hereinafter referred to as “low potential end part of the resistor R 0 ”). A forward bias voltage is applied to the PN junction between the base and the emitter of each of the transistors Q 1  and Q 2 . Alternatively, the transistors Q 1 , Q 2  may be diode-connected PNP bipolar transistors. 
     Further, the low potential end part of the resistor R 1  and the P-type region (base) of the transistor Q 1  are connected to a node n 1 . The node n 1  is connected to a noninverting input terminal of the operational amplifier  21 . Further, one end part of the resistor R 2  toward a low potential side of the resistor R 2  (hereinafter referred to as “low potential end part of the resistor R 2 ”) and another end part of the resistor RO toward a high potential side of the resistor R 0  (hereinafter referred to as “high potential end part of the resistor R 0 ”) are connected to a node n 2 . The node n 2  is connected to an inverting input terminal of the operational amplifier  21 . 
     In this embodiment, a forward voltage of the PN junction between the base and the emitter of the transistor Q 1  is indicated as “VBE 1 ”, and a forward voltage of the PN junction between the base and the emitter of the transistor Q 2  is indicated as “VBE 2 ”. Accordingly, a voltage difference VBE 1 −VBE 2  is applied to the resistor R 0 . By applying the voltage difference VBE 1 −VBE 2  to the resistor R 0 , a constant reference current I 0  which flows in the resistor R 0  becomes set (defined). The currents I 1 , I 2  flow in the resistors R 1 , R 2  in correspondence with the reference current I 0 . Accordingly, a voltage having a positive temperature characteristic is generated in the resistors R 1 , R 2 . Therefore, a resistance value of the resistors R 1 , R 2  can be selected, so that the negative temperature characteristics of the forward voltages VBE 1 , VBE 2  of the transistors Q 1 , Q 2  is set off (canceled) by the positive temperature characteristic of the voltage generated in the resistors R 1 , R 2 . By selecting the resistance values of the resistors R 1 , R 2  that set off the negative temperature characteristics of the forward voltages VBE 1 , VBE 2  of the transistors Q 1 , Q 2  with respect to the positive temperature characteristic of the voltage generated in the resistors R 1 , R 2 , the band gap reference voltage VBG, exhibiting only a small amount of temperature dependency, can be output to the operational amplifier  21 . 
     On the other hand, the correction current It generated by the correction circuit  22  is input and output at the node n 2 . Accordingly, the current I 2 , which flows through the resistor R 2 , can be expressed with the following Formula (4). 
         I 2= I 0− It    (4)
 
     The reference current I 0  flowing in the resistor R 0  and the PN junction between the base and the emitter of the transistor Q 2  are maintained at a constant current by a negative feedback of the operational amplifier  21 . Accordingly, by supplying the correction current It from the correction circuit  22  to the node n 2 , the current I 2  is controlled to become the equivalent of subtracting the supplied correction current It from the reference current I 0 . Thus, the correction circuit  22  can allow the controlled current I 2  to flow in the resistor R 2 . Therefore, the correction circuit  22  can reduce the current I 2  by increasing the amount of correction current It supplied to the node n 2  and increase the current I 2  by reducing the amount of correction current It supplied to the node n 2 . Further, by absorbing the correction current It from the node n 2 , the current I 2  is controlled to become the equivalent of adding the absorbed correction current It to the reference current I 0 . Thus, the correction circuit  22  can allow the controlled current I 2  to flow in the resistor R 2 . Therefore, the correction circuit  22  can increase the current I 2  by increasing the amount of correction current It absorbed from the node n 2  and reduce the current I 2  by reducing the amount of correction current It absorbed from the node n 2 . Hence, the current I 2  is a correction reference current in which the correction current It is added/subtracted with respect to the reference current I 0 . 
     The current I 1  flowing in the resistor R 1  and the transistor Q 1  can also be increased/reduced in correspondence with the increase/reduction of the current I 2 . Because the voltages generated in the resistors R 1 , R 2  become larger as the currents I 1 , I 2  increase, the band gap reference voltage VBG can be adjusted to a large degree. On the other hand, because the voltages generated in the resistors R 1 , R 2  become smaller as the currents I 1 , I 2  are reduced, the band gap reference voltage VBG can be adjusted to a small degree. Hence, the correction circuit  22 , which can switch between supplying and absorbing of the correction current It, can easily correct the band gap reference voltage VBG with high precision by adjusting the amount of supplying the correction current It or the amount of absorbing the correction current It. 
       FIG. 3  is a schematic diagram illustrating a configuration of a band gap reference circuit  30  according to the second embodiment of the present invention. In the second embodiment, like components are denoted with like reference numerals as those of the first embodiment and are not further explained. 
     The band gap reference circuit  30  includes a reference voltage generation circuit  33  and a correction current adder/subtractor circuit (correction circuit)  22 . The reference voltage generation circuit  33  includes an operational amplifier  31 . 
       FIG. 4  is a schematic diagram illustrating a configuration of the operational amplifier  31 . 
     The operational amplifier  31  includes a differential pair such as a pair of differential inputs operated with current densities that are different from each other. In this embodiment, the differential pair of differential inputs of the operational amplifier  31  is constituted by transistors Q 31  and Q 32 . The base of the p-type region of the transistor Q 31  is connected to an inverting input terminal of the operational amplifier  31 . The base of the p-type region of the transistor Q 32  is connected to a noninverting input terminal of the operational amplifier  31 . The emitters of the n-type regions of the transistors Q 31  and Q 32  share a current source  35  and are connected to a voltage for substrate and source (VSS) by way of the shared current source  35 . The transistors (differential pair) Q 31 , Q 32  are connected to an output terminal of the operational amplifier  31  by way of a load circuit  32 . 
     With the configuration illustrated in  FIGS. 3 and 4 , an input referred offset (VBE 31 −VBE 32 ) of the operational amplifier  31  is generated in a case where the proportion (ratio) of the number of differential inputs between Q 31  and Q 32  (Q 11 :Q 12 ) is set to 1:n, and the proportion (ratio) between the current of the differential input Q 31  and the current of the differential input Q 32  is set to m:1. As a result, the following Formula (5) is obtained. 
         VBE 31− VBE 32= Vt· 1 n  ( m·n )   (5)
 
     As illustrated in  FIGS. 3 and 4 , a voltage having a positive thermal characteristic is generated in the resistors R 3 , R 4  by applying the input referred offset (VBE 31 −VBE 32 ) to the resistor R 5  interposed between the differential inputs Q 31 , Q 32  of the operational amplifier  31 . Therefore, a resistance value of the resistors R 3 , R 4  can be selected, so that the negative temperature characteristics of the forward voltages VBE 3  of the PN junction between the base and the emitter of the transistor Q 3  is set off (canceled) by the positive temperature characteristic of the voltage generated in the resistors R 3 , R 4 , and R 5 . By selecting the resistance values of the resistors R 3 , R 4  that set off the negative temperature characteristics of the forward voltages VBE 3  of the PN junction between the base and the emitter of the transistor Q 3  with respect to the positive temperature characteristic of the voltage generated in the resistors R 3 , R 4 , and R 5 , the band gap reference voltage VBG exhibiting only a small amount of temperature dependency can be output to the operational amplifier  31 . 
     Accordingly, the reference voltage generation circuit  33  is a circuit that outputs the band gap reference voltage VBG based on a reference current I 5  generated by the input referred offset (VBE 31 −VBE 32 ). Further, the correction circuit  22  is a circuit that adds/subtracts the correction current It with respect to the reference current I 5 . 
     Hence, with the configuration illustrated in  FIGS. 3 and 4 , the correction current It not only can be subtracted from the reference current I 5  but can also be added to the reference current I 5 . Therefore, slight adjustments for increasing or reducing the current I 3  flowing in the resistor R 3  can be performed. Accordingly, slight adjustments for increasing or reducing the amount of the band gap reference voltage VBG can be easily performed. As a result, even if there is a variance of the band gap reference voltage VBG due to, for example, inconsistent manufacturing, the band gap reference voltage VBG can be easily corrected with high precision. Further, variance of the band gap reference voltage due to temperature can also be easily corrected with high precision. 
     Next, the configuration of the band gap reference circuit  30  is described in further detail. 
     The band gap reference circuit  33  is a series circuit having the resistor R 4 , the resistor R 5 , and the resistor R 3 , and the transistor Q 3  connected in series between the operational amplifier  31 , an output terminal of the operational amplifier  31 , and a voltage for substrate and source (VSS). 
     The transistor Q 3  is a diode-connected NPN bipolar transistor. The p-type region (base) of the transistor Q 3  is connected to one end part of the resistor R 3  toward a low potential side of the resistor R 3  (hereinafter referred to as “low potential end part of the resistor R 3 ”). A forward bias voltage is applied to the PN junction between the base and the emitter of the transistor Q 3 . Alternatively, the transistor Q 3  may be a diode-connected PNP bipolar transistor. 
     Further, one end part of the resistor R 4  toward a low potential side of the resistor R 4  (hereinafter referred to as “low potential end part of the resistor R 4 ”) and one end part of the resistor R 5  toward a high potential side of the resistor R 5  (hereinafter referred to as “high potential end part of the resistor R 5 ”) are connected to a node N 3 . The node N 3  is connected to an inverting input terminal of the operational amplifier  31 . The other end part of the resistor R 5  toward a low potential side of the resistor R 5  (hereinafter referred to as “low potential end part of the resistor R 5 ”) and the other end part of the resistor R 3  toward a high potential side of the resistor R 3  (hereinafter referred to as “high potential end part of the resistor R 3 ”) are connected to a node N 2 . The node N 2  is connected to a noninverting input terminal of the operational amplifier  31 . 
     The input referred offset (VBE 31 −VBE 32 ) of the operational amplifier  31  is applied to the resistor R 5 . By applying the input referred offset (VBE 31 −VBE 32 ) to the resistor R 5 , a constant reference current I 5  which flows in the resistor R 5  becomes set (defined). The currents I 3 , I 4  flow in the resistors R 3 , R 4  in correspondence with the reference current I 5 . Accordingly, a voltage having a positive temperature characteristic is generated in the resistors R 3 , R 4 . Therefore, a resistance value of the resistors R 3 , R 4  can be selected, so that the negative temperature characteristic of the forward voltage VBE 3  of the transistor Q 3  is set off (canceled) by the positive temperature characteristic of the voltage generated in the resistors R 3 , R 4 . By selecting the resistance value of the resistors R 3 , R 4  that sets off the negative temperature characteristic of the forward voltage VBE 3  of the transistor Q 3  with respect to the positive temperature characteristic of the voltage generated in the resistors R 3 , R 4 , the band gap reference voltage VBG, exhibiting only a small amount of temperature dependency, can be output from the operational amplifier  31 . 
     On the other hand, the correction current It generated by the correction circuit  22  is input and output at the node N 2 . Accordingly, the current I 3 , which flows through the resistor R 3 , can be expressed with the following Formula (6). 
         I 3= I 5+ It    (6)
 
     The current I 3  flows through the resistor R 3  and the PN junction between the base and the emitter of the transistor Q 3 . 
     The reference current I 5  flowing in the resistor R 5  is maintained at a constant current by a negative feedback of the operational amplifier  31 . Accordingly, by supplying the correction current It from the correction circuit  22  to the node N 2 , the current I 5  is controlled to become the equivalent of adding the supplied correction current It to the reference current I 5 . Thus, the correction circuit  22  can allow the controlled current I 3  to flow in the resistor R 3 . Therefore, the correction circuit  22  can increase the current I 3  by increasing the amount of correction current It supplied to the node N 2  and reduce the current I 3  by reducing the amount of correction current It supplied to the node N 2 . Further, by absorbing the correction current It from the node N 2 , the current I 3  is controlled to become the equivalent of subtracting the absorbed correction current It from the reference current I 5 . Thus, the correction circuit  22  can allow the controlled current I 3  to flow in the resistor R 3 . Therefore, the correction circuit  22  can reduce the current I 3  by increasing the amount of correction current It absorbed from the node N 2  and increase the current I 3  by reducing the amount of correction current It absorbed from the node N 2 . Hence, the current I 3  is a correction reference current in which the correction current It is added/subtracted with respect to the reference current I 5 . 
     The current flowing in the transistor Q 3  can also be increased/reduced in correspondence with the increase/reduction of the current I 3 . Because the voltages generated in the resistor R 3  becomes larger as the current I 3  increases, the band gap reference voltage VBG can be adjusted to a large degree: On the other hand, because the voltage generated in the resistor R 3  become smaller as the current I 3  is reduced, the band gap reference voltage VBG can be adjusted to a small degree. Hence, the correction circuit  22 , which can switch between supplying and absorbing of the correction current It, can easily correct the band gap reference voltage VBG with high precision by adjusting the amount of supplying the correction current It or the amount of absorbing the correction current It. 
     As described above, the band gap reference circuit  30  of the second embodiment has the reference voltage generation circuit  33  serving as a first circuit (first system) including a combination of transistors and resistors for generating the band gap reference voltage VBG, and the correction circuit  22  for adding/subtracting the correction current It with respect to the reference voltage I 0  flowing in the first circuit. With this configuration, the sensitivity for adjusting the band gap reference voltage VBG to increase matches with the sensitivity for adjusting the band gap reference voltage VBG to decrease. Therefore, the amount of current for correcting the band gap reference voltage VBG can easily be obtained (calculated) based on the band gap reference voltage VBG which is measured prior to the current correction using the correction current It. 
     Further, by setting the combination of transistors and resistors for generating the band gap reference voltage VBG as the first circuit, current consumption can be reduced and noise can be lowered. 
     Further, the changes (variance) of the output band gap reference voltage VBG can be stabilized with the correction circuit  22 . For example, in a case of calculating the amount of voltage change of the band gap reference voltage VBG where the unit of adjusting the correction current Vt in each adjustment step is assumed as a % with respect to the reference current I 5  and the correction current Vt is adjusted in b step(s), the results obtained when the correction current It is supplied to the node N 2  are as follows: 
     Voltage VR 5  generated in the resistor R 5 : 
         VR 5= VBE 31− VBE  32= Vt· 1 n ( m·n );
 
     Voltage VR 3  generated in the resistor R 3 : 
         VR 3= VR 5·( R 3/ R 5);
 
     Amount of voltage change ΔVR 3  of voltage VR 3  when the correction current It of +a %×b step(s) is added to the resistor R 3 : 
         ΔVR 3= VR 5·( R 3/ R 5)· a/ 100· b;  
 
     Amount of voltage change ΔVQ 3  between the base and the emitter of the transistor Q 3  when the correction current It of +a %×b step(s) is added to the transistor Q 3 : 
       Δ VQ 3= Vt· 1 n  (1+ a/ 100× b )
 
     (for example, ΔVQ 3  becomes 0.00995·Vt in a case where b=1 and a=1%, and ΔVQ 3  becomes 0.0198·Vt in a case where b=1 and a=2%); and
 
Amount of voltage change ΔVBGR of the band gap reference voltage VBG:
 
       Δ VBGR=ΔVR 3+ ΔVQ 3= VR 5·( R 3/ R 5)· a/ 100· b+Vt· 1 n  (1+ a/   100×b ).
 
       FIG. 5  is a schematic diagram illustrating an example of a configuration of the reference voltage generation circuit  33 . It is to be noted that the load circuit  32  of  FIG. 4  corresponds to the area illustrated with broken lines in  FIG. 5 . 
     In  FIG. 5 , by setting a proportion (ratio) of the current between the pair of differential inputs Q 31  and Q 32  to m:1, it is preferable for the proportion (ratio) of the current between the transistors to be Q 31 :Q 32 :Q 4 :Q 5 :Q 6 :M 1 :M 2 =m:1:(m+1):1:m:2:2m. 
     The transistors M 6 , M 7 , and M 8  are added to the reference voltage generation circuit  33  for improving the output resistance of the operational amplifier  31 . However, the transistors M 6 , M 7 , and M 8  may be omitted from the reference voltage generation circuit  33 . In an alterative configuration, the transistors M 4 , M 5 , M 6 , M 7 , M 8 , M 9 , and Q 7  may be omitted from the reference voltage generation circuit  33 , the load circuit of the pair of differential inputs Q 31  and Q 32  may be used as transistors M 1 , M 2 , and the transistor M 3  may be used as an output buffer. 
     The input/output point of the correction current It for correcting the band gap reference voltage VBG may be the node N 3 , the node N 2 , or the node N 1 . Further, in a case where the resistors R 3  and R 4  are divided into multiple resistor elements, an intermediate point(s) between the multiple resistor elements may be the input/output point of the correction current It for correcting the band gap reference voltage VBG. 
       FIG. 6  is a schematic diagram illustrating an example of a configuration of the correction circuit  22 . In a case where the correction circuit  22  is used in the band gap reference circuit  20  illustrated in  FIG. 2 , the correction circuit  22  includes a current absorbing circuit  27  for generating an absorbing current Itb and a current supplying circuit  26  for generating a supplying current Ita. In this case, the current absorbing circuit  27  serves as a first generation circuit of the correction circuit  22  for generating a first correction current that is to be added to the reference current I 0 , and the current supplying circuit  26  serves as a second generation circuit of the correction circuit  22  for generating a second correction current that is to be subtracted from the reference current I 0 . In a case where the correction circuit  22  is used in the band gap reference circuit  30  illustrated in  FIG. 3 , the correction circuit  22  includes the current supplying circuit  26  for generating a supplying current Ita and the current absorbing circuit  27  for generating an absorbing current Itb. In this case, the current supplying circuit  26  serves as a first generation circuit of the correction circuit  22  for generating a first correction current that is to be added to the reference current I 0 , and the current absorbing circuit  27  serves as a second generation circuit of the correction circuit  22  for generating a second correction current that is to be subtracted from the reference current I 0 . The correction current It is a combined current obtained by combining the supplying current Ita and the absorbing current Itb. 
     That is, the current supplying circuit  26  is an upstream current source for generating the correction current It and the current absorbing circuit  27  is a downstream current source for generating the correction current It. 
     The correction circuit  22  includes a control circuit  25  for outputting correction control signals Sta, Stb to the current supplying circuit  26  and the current absorbing circuit  27  in correspondence with adjustment data for adjusting the amount of increasing/reducing the correction current It. The control circuit  25  controls the amount in which the correction current It is increased or reduced by outputting the correction control signals Sta, Stb to the current supplying circuit  26  and the current absorbing circuit  27 . The control circuit  25  may be configured as a logical circuit or as a microcomputer. 
     The adjustment data of the correction current It is stored in, for example, a non-volatile memory  24 . The non-volatile memory  24  may be, for example, an EEPROM (Electrically Erasable Programmable Read Only Memory), a flash ROM (Read Only Memory), or a OTPROM (One Time Programmable Read Only Memory). 
     By changing the adjustment data of the correction current It, the unit of adjusting the amount of the correction current It (unit adjustment range) can be adjusted. For example, the control circuit  25  can use the correction control signals Sta, Stb to increase or reduce the correction current It by weighting in binary. Accordingly, even in a case where the number of transistors M*, S* included in the current supplying circuit  26  and the current absorbing circuit  27  is small, the unit of adjusting the amount of the correction current It can be reduced. The smaller the unit of adjusting the amount of the correction current It, the smaller the unit adjustment range of the band gap reference voltage VBG can be reduced. Therefore, the band gap reference voltage VBG can be adjusted with high precision. Further, the control circuit  25  may control the increasing or reduction of the correction current It in accordance with a thermometer code. 
     Further, the correction circuit  22  can generate the correction current It based on a bias current Ib (see, for example,  FIG. 5 ) that is supplied for generating the band gap reference voltage VBG. The bias current Ib is supplied from output buffers (transistors) M 3  and M 6 . The output buffers M 3  and M 6  are positioned upstream of a node N 4  from which the band gap reference voltage VBG is output. In  FIG. 5 , bias  1  and bias  2  are connected to transistors M 3  and M 6 , and a generation reference voltage Ia of the correction current It is generated by copying the bias current Ib with the transistors M 3  and M 6 . Likewise, in  FIG. 6 , bias  1  and bias  2  are connected to transistors M 10  and M 20 , and a generation reference voltage Ia of the correction current It is generated by copying the bias current Ib with the transistors M 10  and M 20 . In order to attain a precise unit adjustment amount of the correction current It, the bias current Ib is copied so that the generation reference current Ia is a value lower than the bias current Ib. 
     By copying the bias current Ib (which is supplied for obtaining the band gap reference voltage VBG) and correcting the bias voltage Ib, the amount of adjusting the correction voltage per unit correction step can easily be obtained. Therefore, by measuring the band gap reference voltage VBG, the number of steps for adjusting voltage can easily be obtained, and the number of steps performed in the voltage adjustment can be reduced. 
     Further, unlike correcting the resistance value, there is no need to use transistors M* or switches S* (see, for example,  FIG. 6 ) exhibiting a sufficiently small amount of on-resistance with respect to the resistors R 3 , R 4 , and R 5  (see, for example,  FIG. 5 ) because correction is performed by applying current. Therefore, size reduction (area reduction) of the band gap reference circuit  20 , 30  can be achieved. Because the power source voltage VDD has little influence on the on-resistance of the transistors M* and the switches S* constituting the current supplying circuit  26  or the current absorbing circuit  27 , changes of the band gap reference voltage VBG due to the power source voltage VDD can be reduced. 
       FIG. 7  is a schematic diagram illustrating an example of a configuration of a startup circuit  34  for activating (starting up) a band gap reference circuit according to an embodiment of the present invention. The startup circuit  34  turns on/off the output of a startup current Is in correspondence with the band gap reference voltage VBG. In a case where the band gap reference voltage VBG is less than a predetermined value, the startup circuit  34  switches on the startup current Is. In a case where the band gap reference voltage VBG is greater than the predetermined value, the startup circuit  34  switches off the startup current Is. 
     In a case of the configuration illustrated in  FIG. 2 , it is preferable to supply the startup current Is to a given node interposed between the node n 1  and the node n 4 . In a case of the configuration illustrated in  FIG. 3 , it is preferable to supply the startup current Is to a given node interposed between the node N 4  and the node N 1 . 
     In  FIG. 7 , when the band gap reference voltage VBG is less than a gate threshold voltage of an NMOS transistor M 44  of a source follower, the transistor M 44  switches off the output of a current source M 46  toward a N-channel MOS. Thereby, the startup current Is is output because the gate voltage of an NMOS transistor M 43  toward the N-channel MOS of a startup source follower increases. On the other hand, when the band gap reference voltage VBG is greater than the gate threshold voltage of the NMOS transistor M 44 , the transistor M 44  switches on the output of the current source M 46 . Thereby, the startup current Is is automatically switched off because the gate voltage of the NMOS transistor M 43  decreases. Therefore, it is preferable for the size of the transistors M 41 , M 42 , M 45 , and M 46  to be adjusted beforehand, so that a current performance (ability) of the current source M 46  is greater than the current source M 42  toward the PMOS. With the configuration of the circuit of  FIG. 7 , a startup circuit having a simple configuration including a source follower for detecting voltage and a source follower for applying current can be obtained and size reduction of the band gap reference circuit  20 , 30  can be achieved. 
     Further, the present invention is not limited to these embodiments, but variations and modifications may be made without departing from the scope of the present invention. 
     For example, a fuse element may be used instead of the switch S* of the correction circuit  22  of  FIG. 6 . 
     The present application is based on Japanese Priority Application No. 2012-057886 filed on Mar. 14, 2012, with the Japanese Patent Office, the entire contents of which are hereby incorporated by reference.