Patent Publication Number: US-6703951-B2

Title: Analog to digital converter with encoder circuit and testing method therefor

Description:
This application is a divisional of application Ser. No. 09/034,219, filed Mar. 4, 1998, now allowed. 
    
    
     BACKGROUND OF THE INVENTION 
     The present invention relates to an analog to digital (A/D) converter, and, more particularly, to an A/D converter including an encoder. 
     A/D converters are often used with microprocessors to convert an analog signal to a corresponding digital signal which is processed by the microprocessor. Due to the increased speed of microprocessors, for example, from 50 MHZ to 300 MHZ, there is a need for faster A/D converters. A/D converters of the parallel type and the serial and parallel type are advantageous for high speed operation. Such A/D converters generally comprise a plurality of comparators for comparing an analog input signal with analog reference voltages and an encoder for converting output signals of the comparators to a multibit digital signal. The speed and accuracy of the A/D converter can be improved by increasing the speed and accuracy of the encoder. 
     A conventional, parallel-type A/D converter comprises a comparator section, a logical boundary detection section for detecting a logical boundary of comparator output signals and an encoder section. The encoder section often includes a wired-OR type ROM. Referring to FIG. 1, a first example of a conventional parallel-type A/D converter which outputs a five (5) bit digital signal is shown. The A/D converter comprises a comparator section  1  having comparators CM 1  to CM 31  and associated resistors R, a logical boundary detection section  2  having NOR circuits DE 0  to DE 31 , and an encoder section  3   a  having ROM cells  4 . 
     Between a high potential side reference voltage V RH  and a low potential side reference voltage V RL , thirty two resistors are connected in series. The two resistors R positioned on opposite ends of the series connection have a resistance value equal to half that of the other resistors R. A junction between each adjacent one of the resistors R is connected to a first input terminal of a corresponding one of 31 comparators CM 1  to CM 31 . A voltage difference between the reference voltages V RH  and V RL  is divided by the resistors R, and reference voltages V R1  to V R31  obtained by the division are input to the comparators CM 1  to CM 31 , respectively. An analog input signal Ain is input to second terminals of the comparators CM 1  to CM 31 . The comparators CM 1  to CM 31  compare the analog input signal Ain with the reference voltages V R1  to VR 31 , in response to a control signal output from a control circuit (not shown). 
     Each of the comparators CM 1  to CM 31  outputs an output signal S 1  to S 31  high and an output signal /S 1  to /S 31  low when the potential of the analog input signal Ain is lower than the reference voltage V R1  to V R31 . On the other hand, when the potential of the analog input signal Ain is higher than the reference voltage V R1  to V R31 , each of the comparators CM 1  to CM 31  outputs an output signal S 1  to S 31  low and an output signal /S 1  to /S 31  high. 
     For example, if the potential of the analog input signal Ain is higher than the reference voltage V R4  but lower than the reference voltage V R5 , then the comparators CM 1  to CM 4  output thermometer code bits wherein the output signals S 1  to S 4  have L levels and the output signals /S 1  to /S 4  have H levels. Meanwhile, the comparators CM 5  to CM 31  output thermometer code bits wherein the output signals S 5  to S 31  have H levels and the output signals /S 5  to /S 31  have L levels. 
     Each of the output signals S 1  to S 31  of the comparators CM 1  to CM 31  is input to a first terminal of a corresponding one of the NOR circuits DE 1  to DE 31  while each of the output signals /S 1  to /S 31  of the comparators CM 1  to CM 31  is input to a second input terminal of a corresponding one of the NOR circuits DE 0  to DE 30 . Further, one of a pair of terminals of each of the NOR circuits DE 0  and DE 31  is connected to the ground GND. Each of the NOR circuits DE 0  to DE 31  outputs a signal high if both of the input signals thereto have L levels, and only one of the NOR circuits DE 0  to DE 31  outputs a signal high by operation of the comparators CM 1  to CM 31 . The output signals of the NOR circuits DE 0  to DE 31  are output to word lines WL 0  to WL 31 , respectively. 
     The encoder section  3   a  includes five bit lines BL 0  to BL 4  corresponding to a 5-bit digital output signal B 0  to B 4 . ROM cells  4  for outputting the output signal B 0  to B 4  in the form of a binary code are connected at predetermined locations between the word lines WL 0  to WL 31  and the bit lines BL 0  to BL 4 . Each of the ROM cells  4  comprises an N-channel MOS transistor, shown in FIG.  2 . The gate of the transistor is connected to one of the word lines WL and the drain is connected to one of the bit lines BL while the source is connected to the ground GND. 
     The bit lines BL 0  to BL 4  are connected to a power supply V DD  through switch circuits SW 0  to SW 4 , respectively, such that, when the switch circuits SW 0  to SW 4  are closed, the bit lines BL 0  to BL 4  are precharged. Each of the switch circuits SW 0  to SW 4  preferably comprises a P-channel MOS transistor. 
     If the level of one of the word lines changes to an H level after the switch circuits SW 0  to SW 4  are opened, then ROM cells connected to the activated word line are turned on and the levels of the bit lines which are connected to the ROM cells are changed to an L level. For example, if the level of the word line WL 0  is changed to an H level, then the output signals B 0  to B 4  are “00000”; and if the level of the word line WL 2  is changed to an H level, then the output signals B 0  to B 4  are “01000”. 
     Since the encoder section  3   a  employs a ROM circuit which requires a precharging operation, the operation speed of the comparator section  1  is lower than the operation speed of the encoder section  3   a . Accordingly, the conversion speed is determined by the comparator section  1 . 
     The output signals of the comparator section  1  in normal operation either are a thermometer code which exhibits only one logical boundary or exhibit the same logic value. However, a babble error sometimes occurs with a thermometer code. The babble error which occurs probabilistically most frequently is reversal of one output logic value in the output signals /S 1  to /S 31  of the comparators CM 1  to CM 31 . If such a babble error is input to the NOR circuits DE 0  to DE 31 , then two word lines exhibit H levels simultaneously, and an incorrect output signal B 0  to B 4  is output. 
     Particularly, the encoder section  3   a  constructed to output a binary code, sometimes has a large error due to a babble error. In particular, if the word lines WL 14  and WL 16  shown in FIG. 3 exhibit H levels simultaneously due to a babble error, then the output signal B 0  to B 4  are all zero and a large error occurs with the output signal B 0  to B 4 . 
     In order to solve such a problem, an A/D converter having a modified logical boundary detection section  2 , as shown in FIG. 4, has been proposed. Referring to FIG. 4, the A/D converter is constructed such that the NOR circuits DE 0  to DE 31  have 3-input terminals. If an nth NOR circuit is represented as NOR circuit DEn, an output signal Sn of the comparators CMn and output signals /S(n+1) and /S(n+2) of two higher order comparators CM(n+1) and CM(n+2) are input to the NOR circuit DEn. When a babble error (a different logic value is included in a thermometer code) occurs, the babble error location is not discriminated as a logical boundary, and only one of the word lines WL exhibits H levels and an output signals B 0  to B 4  having correct values or values near to correct values are output. 
     However, even where the NOR circuits DE 0  to DE 31  have 3-inputs, if, for example, such a babble error that an output logic value spaced by a two or more logic value distance is reversed, then two word lines spaced by a two word line distance exhibit an H level simultaneously. If, for example, the word lines WL 14  and WL 17  shown in FIG. 3 simultaneously exhibit H levels, then the output signals B 0  to B 4  are all zero, which is a large error. 
     In order to solve the disadvantage, an A/D converter which includes an encoding section  3   b  which outputs a Gray code (reflected binary code) in place of a binary code has been proposed. 
     Referring to FIG. 5, the encoding section  3   b  is different from the encoder section  3   a  which outputs a binary code in terms of the positions of the ROM cells  4 . That is, the encoding section  3   b  outputs signals G 0  to G 4  of a Gray code wherein one of the word lines WL exhibits an H level. Where a thermometer code is recognized as a decimal number (Decimal), a corresponding relationship between the output signals B 0  to B 4  of a binary code (Binary) and the output signals G 0  to G 4  of a Gray code (Gray) corresponding to a thermometer code is illustrated in FIG.  9 . The output signals G 0  to G 4  are output to a next stage circuit through a conversion circuit which converts a Gray code into a binary code. 
     In such an A/D converter, even if a babble error is output from the comparator section  1  and the logical boundary detection section  2  outputs an H level, for example, to the word lines WL 14  and WL 17  in FIG. 6 simultaneously, the encoding section  3   b  outputs the output signals G 0  to G 4  same as that only when the word line WL 14  exhibits an H level. Accordingly, even if a most likely value is provided when the word line WL 15  or the word line WL 16  exhibits an H level, the encoder section  3   b  does not output signals having large errors. 
     Thus, if a babble error occurs with an output signal of the comparator section  1 , an error is suppressed, as shown in FIGS. 12 to  14 . 
     FIG. 12 illustrates operation when a babble error “. . . 11101000. . . ” (type b 1 ), wherein an output logic value of a thermometer code spaced by a one logic value distance is reversed, is input to the logical boundary detection section  2  having 2-input NOR circuits, and output signals of the logical boundary detection section  2  are converted into a Gray code by the encoding section  3   b . The abscissa indicates a decimal value of a normal thermometer code while the ordinate is a value obtained by converting an output signal of a Gray code output from the encoding section  3   b  to a decimal number. 
     FIG. 13 illustrates operation when a babble error “. . . 111001000. . . ” (type b 2 H), wherein an output logic value of a thermometer code spaced by a two logic value distance is reversed, is input to the logical boundary detection section  2  having 3-input NOR circuits, and output signals of the logical boundary detection section  2  are converted into a Gray code by the encoding section  3   b . The abscissa and the ordinate are the same as FIG.  12 . 
     FIG. 14 illustrates operation when a babble error “. . .  111011000 . . . ” (type b 2 L), wherein an output logic value of “1” of a thermometer code spaced by a two logic value distance is reversed to “0”, is input to the logical boundary detection section  2  having 3-input NOR circuits, and output signals of the logical boundary detection section  2  are converted into a Gray code by the encoding section  3   b . The abscissa and the ordinate are the same as FIG.  12 . 
     Since the encoding section which outputs a Gray code suppresses an error, as opposed to the encoding section which outputs a binary code, it is advantageous. However, conversion circuit for converting a Gray code to a binary code is required. However, an error is still generated with respect to a value which is considered to be most likely. 
     Accordingly, yet another A/D converter has been proposed wherein logical processing by a majority decision circuit is performed for a thermometer code output from the comparator section. However, employment of the majority decision circuit increases the circuit scale of the A/D converter. Therefore, in order to suppress an increase in circuit scale, it has been proposed to form the majority decision circuit from an analog circuit (J. van de Valburg and R. J. van de Plassche, “An 8-bit 650-MHZ folding ADC”,  IEEE Journal of Solid - State Circuits,  Vol. 27, pp.1662-1666, December 1992). However, even an analog majority decision circuit does not exhibit a sufficient effect against a babble error of the type b2H or the type b2L wherein an output logic value spaced by a two logic value distance is inverted. 
     An A/D converter having an irregular decoding logic for the logic boundary detection section is also been proposed, so that, even if a babble error occurs, a most likely digital output signal is output (C. W. Mangelsdorf, “A 400-MHZ Input Flash Converter with Error Correction”,  Journal of Solid - State Circuits,  Vol. 25, pp.184-191, February 1990). Another A/D converter wherein logical boundary detection is performed for upper bits and lower bits into which the thermometer code is divided instead of performing logical boundary detection between adjacent outputs of a thermometer code (Y. Gendai et al., “An 8b 500-MHZ ADC”,  Digest of International Solid - State Circuit Conference,  TPM 10.5, pp.29-35, February 1991), has been proposed, and a further A/D converter wherein the logical boundary detection section performs logical comparison of a thermometer code for every other bit to suppress production of a babble error (A. Matsuzawa et al., “An 8b 600-MHZ Flash A/D with multistage duplex gray coding”,  Symp. VLSI Circ. Dig. Tech. Papers,  pp.37-42, May 1991) has been proposed. These A/D converters eliminate or correct a babble error produced in a thermometer code by the logical boundary detection section. 
     In contrast, an A/D converter of the twin encoder type is available wherein a babble error is corrected by the encoder section. In the A/D converter, an average of output signals of an encoder comprising P-channel MOS transistors and another encoder comprising N-channel MOS transistors is calculated (M. Ito et al., “A 10-bit 20 MS/s 3 V Supply CMOS AD Converter”, 1994  Journal of Solid - State Circuits,  Vol. 25, pp.1531-1536, February 1990). However, using the design, the circuit scale of the encoder is doubled. 
     Also an A/D converter having a reduced number of logic stages of a conversion circuit for converting a Gray code into a binary code is available, in which an encoder outputs a Quasi Gray code so that the operation speed of the encoder is improved (Y. Akazawa, “A 400 MSPS 8b Flash A/D Conversion LSI”,  ISSCC Digest of Technical Papers,  pp.98-99, February 1987). 
     The encoding sections of the A/D converters of the parallel type are all constructed in the form of a ROM using wired OR gates. In this construction, a precharging operation is required for each operation cycle, and the precharging operation requires approximately half of one cycle. Thus, the precharge time requirement makes it difficult to improve the operation speed of the encoding section. 
     Further, since the encoding section does not function to correct an error caused by a babble error which occurs in a thermometer code, correction of a babble error is performed principally by the logical boundary detection section. However, even if an encoding section which outputs a Gray code which has a comparatively low degree in error is used, an error of an output signal by a babble error is not fully removed. 
     High speed A/D converters having conversion speeds exceeding 10 MS/s (Mega Sample/sec) are used not only for image processing, but recently, for data reading apparatus, such as a hard disk drive, and also for high speed data communication devices using QPSK (Quadrature Phase Shift Keying) or QAM (Quadrature Amplitude Modulation). Accordingly, conversion speeds exceeding 100 MS/s and an error rate exceeding 10 −10  are required. Consequently, a performing test of an A/D converter which operates at a high speed must performed with certainty. 
     An A/D converter is performance tested by connecting the A/D converter to a testing apparatus. Then, a clock signal and an analog input signal are input from the testing apparatus to the A/D converter. The A/D converter samples the analog input signal in response to the clock signal, converts the sampled analog signal into a digital signal and outputs the digital signal to the testing apparatus. The testing apparatus evaluates the digital signal output from the A/D converter to determine whether it meets its performance specifications. 
     With an increase in operation speed of an A/D converter, an increase in frequency of a clock signal and an analog input signal input from the testing apparatus is required. In a performance test, the clock signal supplied from the testing apparatus is required to have a frequency two or three times as high as that in ordinary use, and the analog input signal is required to be input with a frequency higher than ¼ that of the clock signal. 
     Although, the testing apparatus can supply such a high frequency, it is difficult to produce a corresponding high speed analog signal. Also it is difficult to deliver a digital signal output in a high speed cycle from an A/D converter to a testing apparatus to evaluate it, such that present testing apparatus do not perform adequately. 
     It is a first object of the present invention to provide an encoder which has a function of correcting a babble error included in a thermometer code input thereto and also has an improved operation speed. 
     It is a second object of the present invention to provide a testing method which adequately performs a performance test of a high speed A/D converter. 
     SUMMARY OF THE INVENTION 
     Briefly stated, the present invention provides a semiconductor device including: an analog signal production circuit for receiving a sampling clock signal and producing an analog signal having a phase which varies successively with respect to the sampling clock signal; and an A/D converter for sampling the analog signal in accordance with the sampling clock signal to generate a digital signal. The A/D converter includes: a comparator section for receiving the analog signal and generating a corresponding thermometer code; an encoder section for receiving the thermometer code, detecting a logical boundary of the thermometer code, and producing a corresponding gray code digital signal therefrom; and a gray code to binary code conversion section for converting the gray code to a binary code. 
     The present invention provides an encoder for encoding a thermometer code including: an encoder circuit for detecting a logical boundary of the thermometer code to produce a Gray code signal, wherein the Gray code signal comprises a lower order bit and an upper order bit, and a particular relationship is set between the lower order bit and the upper order bit when the Gray code signal is error free; an error detector circuit, coupled to the encoder circuit, for detecting whether the particular relationship is satisfied and generating an error bit signal when the particular relationship is not satisfied; an error correction circuit, coupled to the encoder circuit and the error detector circuit, for correcting an error bit of the Gray code signal in response to the error bit signal and generating a corrected bit signal; and a Gray to binary converter circuit connected to the error correction circuit for converting the Gray code signal including the corrected bit signal into a binary code signal. 
     The present invention provides an encoder for encoding a thermometer code including: an encoder circuit for detecting a logical boundary of the thermometer code to produce a Gray code signal including an upper bit and decomposed lower order bits regarding a lower order bit of the Gray code, wherein a particular relationship is set between the upper bit and the decomposed lower order bits when the Gray code in error free; an error detector circuit, coupled to the encoder circuit, for detecting whether the particular relationship between the lower order and upper order bits is satisfied and generating an error bit signal when the particular relationship is not satisfied; and a Gray to binary converter circuit, coupled to the encoder circuit and the error detector circuit, for correcting an error bit of the Gray code signal in response to the error bit signal and converting the Gray code signal including corrected bit signal into a binary code signal. 
     The present invention provides a method of converting a Gray code to a binary code, the Gray code including a plurality of decomposed Gray code bits. The method includes the steps of: logically processing the plurality of decomposed Gray code bits to produce a plurality of binary code bits for one bit of the binary code; and logically processing the plurality of binary code bits to produce one bit of the binary code. 
     The present invention provides an apparatus for converting a Gray code to a binary code, the Gray code including decomposed Gray code bits. The apparatus includes: a first logic circuit for logically processing the plurality of decomposed Gray code bits to produce a plurality of binary code bits for one bit of the binary code; and a second logic circuit for logically processing the plurality of binary code bits to produce one bit of the binary code. 
     The present invention provide an A/D converter including: a plurality of comparators for receiving and comparing an analog input voltage with reference voltages different from each other and producing a thermometer code based upon the comparison results; a logical boundary detector, coupled to the comparators, for detecting a logical boundary of the thermometer code and outputting a logical boundary detection signal; and an encoder coupled to the logical boundary detector for receiving the logical boundary detection signal and generating a binary code signal. The encoder includes: an encoder circuit for receiving the logical boundary detection signal to produce a Gray code signal, wherein the Gray code signal comprises a lower order bit and an upper order bit, and a particular relationship is set between the lower order bit and the upper order bit when an error code bit is not included in the Gray code; an error detector circuit coupled to the encoder circuit for detecting whether the particular relationship between the lower order and upper order bits is set and generating an error bit signal when the particular relationship is not satisfied; an error correction circuit, coupled to the encoder circuit and the error detector circuit, for correcting an error bit of the Gray code signal in response to the error bit signal and generating a corrected bit signal; and a Gray to binary converter circuit for converting the Gray code signal including the corrected bit signal into a binary code signal. 
     The present invention provides an error correction method for an encoded signal including a thermometer code. The method includes the steps of: detecting a logical boundary of the thermometer code; producing, based on the detected logical boundary, a Gray code including a lower order bit and an upper order bit, wherein a particular relationship is set between the lower order bit and the upper order bit when an error code bit is not included in the Gray code; determining whether the particular relationship is satisfied; and correcting an error code bit included in the Gray code using a predetermined error code processing procedure when the particular relationship is not satisfied. 
     The present invention provides an error correction method for an encoded signal including a thermometer code. The method includes the steps of: detecting a logical boundary of the thermometer code; producing, based on the detected logical boundary, a Gray code including a lower order bit and an upper order bit; dividing the lower order bit into a front lower order bit of a logical target and a back lower order bit of a non-logical target; decomposing the front lower order bit into decomposed front lower order bits and decomposing the back lower order bit into decomposed back lower bits, so that a particular relationship is set between the decomposed front and back lower order bits and the upper order bit when an error code bit is not included in the Gray code; determining whether the particular relationship is satisfied; and correcting an error code bit included in the Gray code using a predetermined error code processing procedure when the particular relationship is not satisfied. 
     The present invention provides a recording medium having recorded thereon a computer readable program code for correcting an error code included in a Gray code. The Gray code includes a lower order bit and an upper order bit, which have a particular relationship set therebetween. The computer readable program performs the steps of: detecting whether the particular relationship is satisfied; and correcting an error code bit included in the Gray code when the particular relationship is not satisfied. 
     The present invention provides a recording medium having recorded thereon a computer readable program code for correcting an error code included in a Gray code. The Gray code has a lower order bit and an upper order bit. The lower order bit includes a logical target lower order bit and a non-logical target lower order bit. The computer readable program performs the steps of: decomposing at least one of the logical and non-logical target lower order bits to generate decomposed Gray code; comparing the decomposed Gray code with the upper order bit to detect an error code bit; and correcting the error code bit included in the Gray code. 
     The present invention provides a recording medium having recorded thereon a computer readable program code for correcting an error code included in a Gray code. The Gray code has a lower order bit and an upper order bit. The lower order bit includes a logical target lower order bit and a non-logical target lower order bit. The computer readable program performs the steps of: decomposing at least one of the logical and non-logical target lower order bits to generate decomposed lower order bits; comparing the decomposed lower order bits with the upper order bit to detect an error code bit; and correcting the error code bit included in the Gray code. 
     The present invention provides a recording medium having recorded thereon a computer readable program code for correcting an error code included in a Gray code. The Gray code has a lower order bit and an upper order bit. The lower order bit includes a logical target lower order bit and a non-logical target lower order bit. The computer readable program performs the steps of: decomposing at least one of the logical and non-logical target lower order bits to generate decomposed lower order bits; comparing the decomposed lower order bits with the upper order bit to detect an error code bit; correcting the error code bit included in the Gray code by inverting the error code bit; and converting the Gray code including the corrected code bit into a binary code. 
     The present invention provides a recording medium having recorded thereon a computer readable program code for detecting a logical boundary of a thermometer code. The computer readable program performs the steps of: inputting three or more every other bits of a thermometer code; and successively comparing the three or more every other bits of the thermometer code to detect the logical boundary of the thermometer code. 
     The present invention provides a testing method for an A/D converter including the steps of: detecting a logical boundary of a thermometer code to produce a Gray code including a lower order bit and an upper order bit which have a particular relationship; determining whether the particular relationship is satisfied; generating an error signal when the particular relationship is not satisfied; detecting whether an error code is included in the thermometer code based on the error signal. 
     The present invention provides a testing method for an A/D converter operating in accordance with a sampling clock signal. The method includes the steps of: producing an analog signal having a phase which varies successively with respect to the sampling clock signal; sampling the analog signal in accordance with the sampling clock signal to generate a digital signal using the A/D convertor; and evaluating the digital signal. 
     The present invention provides a testing method for an A/D converter operating in accordance with a sampling clock signal. The method includes the steps of: producing an analog signal having one of a DC level and amplitude which varies successively with respect to the sampling clock signal; sampling the analog signal in accordance with the sampling clock signal to generate a digital signal using the A/D converter; and evaluating the digital signal. 
     The present invention provides a testing method for an A/D converter converting an analog signal to a digital signal. The method includes the steps of: producing a sampling clock signal having a phase which varies successively with respect to the analog signal; sampling the analog signal in accordance with the sampling clock signal to generate the digital signal using the A/D converter; and evaluating the digital signal. 
     The present invention provides a testing method for an A/D converter including the steps of: producing a sampling clock signal having one of a DC level and amplitude which varies successively with respect to an analog signal; sampling the analog signal in accordance with the sampling clock signal to generate a digital signal using the A/D converter; and evaluating the digital signal. 
     The present invention provides a testing method for an A/D converter operating in accordance with a sampling clock signal. The method includes the steps of: producing an analog signal from the sampling clock signal; producing a comparison reference voltage which successively varies; providing the analog signal and the comparison reference voltage to the A/D converter; sampling the analog signal in accordance with the sampling clock signal to generate a digital signal based on the sampled analog signal and the comparison reference voltage using the A/D converter; and evaluating the digital signal. 
     The present invention provides a semiconductor device including: an analog signal production circuit for receiving a sampling clock signal and producing an analog signal having a phase which varies successively with respect to the sampling clock signal; and an A/D converter for sampling the analog signal in accordance with the sampling clock signal to generate a digital signal. 
     The present invention provides a semiconductor device including: an analog signal production circuit for receiving a sampling clock signal and producing an analog signal having one of a DC level and amplitude which varies successively with respect to the sampling clock signal; and an A/D converter for receiving the analog signal and sampling the analog signal in accordance with the sampling clock signal to generate a digital signal. 
     The present invention provides a semiconductor device including: a clock signal production circuit for receiving an analog signal and producing a sampling clock signal having a phase which varies successively with respect to the analog signal; and an A/D converter for receiving the analog signal and sampling the analog signal in accordance with the sampling clock signal to generate a digital signal. 
     The present invention provides a semiconductor device including: a clock signal production circuit for receiving an analog signal and producing a sampling clock signal having one of a DC level and amplitude which varies successively with respect to the analog signal; and an A/D converter for receiving the analog signal and sampling the analog signal in accordance with the sampling clock signal to generate a digital signal. 
     The present invention provides a semiconductor device including: an analog signal production circuit for receiving a sampling clock signal and producing an analog signal; a comparison reference voltage production circuit for producing a comparison reference voltage which successively varies; and an A/D converter for receiving the analog signal and the comparison reference voltage and sampling the analog signal in accordance with the sampling clock signal, the A/D converter further generating a digital signal based on the sampled analog signal and the comparison reference voltage. 
    
    
     Other aspects and advantages of the invention will become apparent from the following description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention. 
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The invention, together with objects and advantages thereof, may best be understood by reference to the following description of the presently preferred embodiments together with the accompanying drawings. 
     FIG. 1 is a circuit diagram of a first conventional A/D converter; 
     FIG. 2 is a circuit diagram showing a ROM cell of the A/D converter of FIG. 1; 
     FIG. 3 is a diagrammatic view illustrating a connection of ROM cells in an encoding section of the A/D converter of FIG. 1; 
     FIG. 4 is a circuit diagram of a second conventional A/D converter; 
     FIG. 5 is a circuit diagram showing another conventional A/D converter; 
     FIG. 6 is a circuit diagram showing a connection of ROM cells in an encoding section of the A/D converter of FIG. 5; 
     FIG. 7 is a circuit diagram of a prior art encoder which outputs a Gray code; 
     FIG. 8 is a circuit diagram of a logical boundary detection circuit and a ROM cell of the encoder of FIG. 7; 
     FIG. 9 is a diagrammatic view illustrating a relationship between a Gray code and a binary code; 
     FIG. 10 is a diagrammatic view illustrating a relationship between a Gray code and a binary code where a thermometer code including a babble error of the b 1  type is encoded; 
     FIG. 11 is a diagrammatic view illustrating a relationship between a Gray code and a binary code when an error is corrected; 
     FIG. 12 is a diagram illustrating input/output values when a thermometer code including a babble error of the b 1  type is encoded by a Gray code system; 
     FIG. 13 is a diagram illustrating input/output values when a thermometer code including a babble error of the b 2 H type is encoded by a Gray code system; 
     FIG. 14 is a diagram illustrating input/output values when a thermometer code including a babble error of the b 2 L type is encoded by a Gray code system; 
     FIG. 15 is a diagram illustrating input/output values when a thermometer code including a babble error of the b 1  type is corrected with a front code of a Gray code; 
     FIG. 16 is a diagram illustrating input/output values when a thermometer code including a babble error of the b 1  type is corrected with a front code and a back code of a Gray code; 
     FIG. 17 is a block diagram of an encoder of the present invention; 
     FIG. 18 is a more detailed block diagram showing a first embodiment of the present invention; 
     FIG. 19 is a circuit diagram showing a first encoding section of the first embodiment of the present invention; 
     FIG. 20 is a circuit diagram showing a second encoding section of the first embodiment of the present invention; 
     FIG. 21 is a circuit diagram showing a third encoding section of the first embodiment of the present invention; 
     FIG. 22 is a circuit diagram showing a fourth encoding section of the first embodiment of the present invention; 
     FIG. 23 is a circuit diagram showing an error signal production section of the first embodiment of the present invention; 
     FIG. 24 is a circuit diagram showing an error correction section of the first embodiment of the present invention; 
     FIG. 25 is a circuit diagram showing a Gray to binary conversion section of the first embodiment of the present invention; 
     FIG. 26 is a circuit diagram showing a logical boundary detection circuit of the present invention; 
     FIG. 27 is a circuit diagram showing a ROM cell of the present invention; 
     FIG. 28 is a circuit diagram showing a precharge circuit of the present invention; 
     FIG. 29 is a waveform diagram illustrating operation of the precharge circuit of FIG. 28; 
     FIG. 30 is a circuit diagram showing another precharge circuit in accordance with the present invention; 
     FIG. 31 is a waveform diagram illustrating operation of the precharge circuit of FIG. 30 in accordance with the present invention; 
     FIG. 32 is a circuit diagram showing a further precharge circuit in accordance with the present invention; 
     FIG. 33 is a waveform diagram illustrating operation (when no babble error is present) of the first embodiment of the present invention; 
     FIG. 34 is a waveform diagram illustrating operation of the present invention when a babble error of the b 1  type is input; 
     FIG. 35 is a waveform diagram illustrating operation of the present invention when a babble error of the b 2 H type is input; 
     FIG. 36 is a waveform diagram illustrating operation of the present invention when a babble error of the b 2 L type is input; 
     FIG. 37 is a block diagram showing a second embodiment of an A/D converter in accordance with the present invention; 
     FIG. 38 is a circuit diagram showing a Gray to binary conversion section of the A/D converter of FIG. 37; 
     FIG. 39 is a circuit diagram showing a fourth encoding section of the A/D converter of FIG. 37; 
     FIG. 40 is a waveform diagram illustrating operation (when no babble error is present) of the second embodiment of the present invention; 
     FIG. 41 is a waveform diagram illustrating operation of the present invention when a babble error of the b 1  type is input; 
     FIG. 42 is a waveform diagram illustrating operation of the present invention when a babble error of the b 2 H type is input; 
     FIG. 43 is a waveform diagram illustrating operation of the present invention when a babble error of the b 2 L type is input; 
     FIG. 44 is a circuit diagram showing a precharge circuit of the A/D converter of FIG. 37; 
     FIG. 45 is a block diagram showing an encoder of a third embodiment of the present invention; 
     FIG. 46 is a flow chart illustrating a first operation of the third embodiment; 
     FIG. 47 is a diagrammatic view illustrating a decomposition Gray code of the first operation; 
     FIG. 48 is a diagrammatic view illustrating a code produced in a process of the first operation; 
     FIG. 49 is a flow chart illustrating a second operation of the third embodiment; 
     FIG. 50 is a diagrammatic view illustrating a decomposition Gray code of the second operation; 
     FIG. 51 is a diagrammatic view illustrating a code produced in a process of the second operation; 
     FIG. 52 is a flow chart illustrating a third operation of the third embodiment; 
     FIG. 53 is a diagrammatic view illustrating a decomposition Gray code of the third operation; 
     FIG. 54 is a diagrammatic view illustrating a code produced in a process of the third operation; 
     FIG. 55 is a block diagram showing a semiconductor device including an A/D converter connected to a testing apparatus for high speed performance testing of a first example according to the present invention; 
     FIG. 56 is a circuit diagram showing an analog signal production circuit of the semiconductor device of FIG. 55; 
     FIG. 57 is a diagram illustrating a sampling operation with an analog signal having a varied phase; 
     FIG. 58 is a circuit diagram showing a second example of an analog signal production circuit of the semiconductor device of FIG. 55; 
     FIG. 59 is a diagram illustrating a sampling operation with an analog signal having a varied DC level; 
     FIG. 60 is a block diagram showing a second embodiment of a semiconductor device according to the present invention; 
     FIG. 61 is a diagram illustrating a sampling operation when a comparison reference voltage is varied; 
     FIG. 62 is a block diagram showing a third embodiment of a semiconductor device according to the present invention; and 
     FIG. 63 is a circuit diagram showing a control signal production circuit of the semiconductor device of FIG.  62 . 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     First, the principle of error correction in an encoder of the present invention is described. FIG. 9 illustrates code values when each decimal value (Decimal) is normally converted into a 5-bit binary code B 0  to B 4  and a 5-bit Gray code G 0  to G 4 . 
     The Gray code G 0  to G 4  is produced, for example, by an encoder of the bit independent decoding type, as shown in FIG. 7, which detects a logical boundary of a thermometer code as a decimal value in the form of a Gray code. A detailed design of a prior art ROM cell CE used with the encoder of FIG. 7 is illustrated in FIG. 8, in which the thermometer code changes its bits to “1” in order from the least significant bit. 
     Of the Gray code G 0  to G 4 , G 0  is the least significant bit and G 4  is the most significant bit. The Gray code G 0  to G 4  is a reflected binary code wherein only one bit in codes corresponding to two adjacent decimal values exhibit inversion bits. B 0  to B 4  are a binary code corresponding to the Gray code G 0  to G 4 . B 0  is the least significant bit and B 4  is the most significant bit. 
     In the prior art encoder shown in FIG. 7, the Gray code bits G 0  to G 4  are output from wired OR circuits comprising bit lines BL 0  to BL 4  provided in a one-by-one corresponding relationship thereto. For example, for bits G 0  and G 1 , all of the combinations of “00”, “10”, “01” and “11” are present. Therefore, even if at least one of G 0  and G 1  is in error, presence or absence of the error cannot be detected from a combination of G 0  and G 1 . 
     Bit G 0  is produced by logically ORing output signals of nine ROM cells CE connected to the bit line BL 0 , and is decomposed into output signals Z 1  to Z 8  of the nine ROM cells CE (FIG.  9 ). If G 1  and G 2  are decomposed similarly, then G 1 =Y 1 +Y 2 +Y 3 +Y 4  and G 2 =X 1 +X 2 . Then, G 3 =W 1  and G 4 =V 1 . 
     Referring to FIG. 9, the relationship between X 1  and Z 2  is shown, such that when Z 2 =1, X 1 =1. Accordingly, when Z 2 =1, if X 1 =0, then an error is detected, signifying a thermometer code which includes a babble error. Similarly, when Z 3 =1, X 1 =1; when Z 4 =1, W 1 =1; when Z 5 =1, W 1 =V 1 =1; when Z 6 =1, X 2 =W 1 =V 1 =1; when Z 7 =1, X 2 =V 1 =1; and when Z 8 =1, V 1 =1. If any of the conditions just mentioned are not satisfied, then the presence of a babble error in the thermometer code can be detected. 
     Meanwhile, in codes corresponding, for example, to decimal values “3” and “4”, Z 1  to Z 8  exhibit “0” simultaneously, and such a particular relationship cannot be determined. In other words, when Z 1  to Z 8  are on the target logic of “1”, a particular relationship can be determined, but when Z 1  to Z 8  are on the non-target logic of “0”, the particular relationship cannot be determined. 
     Therefore, in order to expand such a principle to the entire area of decimal values including the non-target logic, where Z 1  to Z 8  are regarded as a front code, a back code P 1  to P 7  to the front code Z 1  to Z 8  is set. As shown in FIG. 7, the back code P 1  to P 7  is a code output from ROM cells CEb connected between adjacent ROM cells CE connected to the bit line BL 0  of the least significant bit. Accordingly, the back code P 1  to P 7  is a code generated using the ROM cells CEb by detecting a logic boundary of a thermometer code which is not detected by the ROM cells CE. From such a back code, when P 1 =1, Y 1 =1; when P 2 =1, X 1 =1; when P 3 =1, Y 2 =W 1 =1; when P 4 =1; W 1 =1; when P 5 =1, Y 3 =W 1 =V 1 =1; when P 6 =1, X 2 =V 1 =1; and when P 7 =1, Y 4 =V 1 =1. By setting a such front code and back code, the presence of a babble error can be detected over an entire area of thermometer codes. 
     FIG. 10 illustrates values of codes including “. . . 110100. . . ”. That is, a babble error of the type b1, is included in thermometer codes corresponding to different decimal values. The values in the shaded boxes are values in which an error only from a front code of a Gray code is detected. Non-corrected Dout represents decimal values obtained by conversion of the encoder output whose error is not corrected. If the values in shaded boxes are inverted, then the detected errors are corrected to most likely values. The output of the encoder including such a correction is illustrated in FIG.  15 . Referring to FIG. 15, the abscissa indicates an analog value input to the A/D converter, and the ordinate indicates an analog value obtained by conversion of the encoder output. 
     FIG. 11 illustrates corrected codes obtained by performing error correction for the codes illustrated in FIG. 10, using front codes and back codes and inverting the values. As a result, the Gray codes after the correction have most likely values and coincide with the correct Gray codes illustrated in FIG.  9 . FIG. 16 illustrates the output of the encoder based on the codes after the correction illustrated in FIG.  11 . 
     FIG. 17 shows an outline of an encoder in accordance with the present invention. Referring to FIG. 17, an encoding section  101  detects a logic boundary of a thermometer code and produces a digital signal of a Gray code G. A Gray to binary conversion section  104  converts the Gray code G output from the encoding section  101  to a digital signal of a binary code B. The encoding section  101  includes an error detection section  102  for detecting whether or not values of upper order bits and lower order bits of the Gray code G have a particular relationship to detect an error code included in the Gray code G, and an error correction section  103  for correcting the error code detected by the error detection section  102 . 
     Thus, the encoder functions to correct a babble error included in a thermometer code. 
     FIG. 18 shows a general construction of an encoder  100  according to the first embodiment which produces and outputs digital signals B 0 Z to B 4 Z of a 5-bit binary code based on an input of a thermometer code e 1  to e 31  output from a comparator section similar to that in the conventional examples. 
     The encoder  100  includes first to fourth encoding sections  11  to  14  for producing a 5-bit Gray code based on the thermometer code e 1  to e 31 , an error signal production section  15  for detecting, based on the produced Gray code, whether or not a babble error is present in the thermometer code e 1  to e 31  and outputting, when a babble error is present, an error signal, an error correction section  16  for correcting the error in the Gray code in response to the error signal, and a Gray to binary conversion section  17  for producing a binary code B 0 Z to B 4 Z from the corrected Gray code. 
     A detailed construction of the first encoding section  11  is shown in FIG.  19 . Referring to FIG. 19, each of seventeen logical boundary detection circuits  18   a  to  18   q  has three input terminals IB, IA and IX. To the input terminals IA of the logical boundary detection circuits  18   a  to  18   p , the odd-numbered thermometer code bits e 1 , e 3 , . . . , e 31  of the thermometer code e 1  to e 31  are input, respectively. Meanwhile, the ground GND level is input to the input terminals IA and IB of the highest order logical boundary detection circuit  18   q . To the input terminals IX of the logical boundary detection circuits  18   b  to  18   q , the odd-numbered thermometer code bits e 1 , e 3 , . . . , e 31  are input. A power supply signal V CC  is supplied to the input terminal IX of the lowest order logical boundary detection circuit  18   a.    
     A detailed construction of the logical boundary detection circuits  18   a  to  18   p  is shown in FIG.  26 . Input terminals IB and IA are connected to a NOR circuit  19 . The input terminal IX is connected to an inverter circuit  20 , and an output terminal of the inverter circuit  20  is connected to the NOR circuit  19 . 
     Referring again to FIG. 19, in each of the logical boundary detection circuits  18   b  to  18   q , only when an L level is input to the input terminals IB and IA and an H level is input to the input terminal IX, an output signal O having an H level is output. The output signals O of the logical boundary detection circuits  18   a  to  18   q  are input to terminals A of ROM cells  21   a  to  21   q , respectively. Terminals C of the ROM cells  21   a  to  21   q  are each connected to one of bit lines BL 0   a  to BL 0 Xb. Terminals B of the ROM cells  21   a  to  21   q  are connected to the ground GND. 
     Each of the ROM cells  21   a  to  21   q  comprises an N-channel MOS transistor CT as shown in FIG.  27 . The terminal A is connected to the gate of the N-channel MOS transistor CT, the terminal C is connected to the drain, and the terminal B is connected to the source. Accordingly, if any of the output signals O of the logical boundary detection circuits  18   a  to  18   q  has an H level, the N-channel MOS transistor CT of that one of the ROM cells  21   a  to  21   q  is turned on, and the Gray code bits G 0   a , g 0   b , g 0 Xa or g 0 Xb are output from the bit lines BL 0   a , BL 0   b , BL 0 Xa or BL 0 Xb. At this time, the bit lines BL 0   a , BL 0   b , BL 0 Xa or BL 0 Xb to which the one of the ROM cells  21   a  to  21   q  is connected has the ground GND level. 
     To the bit line BL 0   a , every fourth ROM cells  21   e ,  21   i ,  21   m  and  21   q  beginning with the ROM cell  21   a  at the lowest order are connected. To the bit line BL 0   b , every fourth ROM cells  21   g ,  21   k  and  21   o  beginning with the ROM cell  21   c  at the lowest order are connected. To the bit line BL 0 Xa, every fourth ROM cells  21   f ,  21   j  and  21   n  beginning with the ROM cell  21   b  at the lowest order are connected. To the bit line BL 0 Xb, every fourth ROM cells  21   h ,  21   l  and  21   p  beginning with the ROM cell  21   d  at the lowest order are connected. 
     A detailed construction of the second encoding section  12  is shown in FIG.  20 . The second encoding section  12  has nine logical boundary detection circuits  22   a  to  22   i  which have the same construction as the logical boundary detection circuits  18   a  to  18   q  of the first encoding section  11 . Input terminals IA of the logical boundary detection circuits  22   a  to  22   h  receive even-numbered thermometer code bits e 2 , e 6 , e 10 , e 14 , e 18 , e 22 , e 26  and e 30 , respectively. The ground GND level is supplied to the input terminals IA and IB of the logical boundary detection circuit  22   i . Input terminals IB of the logical boundary detection circuits  22   a  to  22   g  receive the even-numbered thermometer code bits e 2 , e 6 , e 10 , e 14 , e 18 , e 22 , e 26  and e 30 , respectively. Input terminal IX of the logical boundary detection circuit  22   b  is connected to an inverted signal of logical NORing. That is, a logically ORed signal of the thermometer code bits e 2  and e 4 , is input. Similarly, input terminals IX of the logical boundary detection circuits  22   c  to  22   h  receive logically ORed signals of the thermometer code bits e 6 , e 8 , e 10 , e 12 , e 14 , e 16 , e 18 , e 20 , e 22 , e 24 , e 26  and e 28 , respectively. 
     A power supply signal V CC  is input to an input terminal IX of the logical boundary detection circuit  22   a , and the thermometer code bit e 30  is input to an input terminal IX of the logical boundary detection circuit  22   i.    
     Output signals O of the logical boundary detection circuits  22   a  to  22   i  are input to the terminals A of ROM cells  23   a  to  23   i . Terminals C of the ROM cells  23   a  to  23   i  are each connected to one of bit lines BL 1  to BL 1   x.  Terminals B of the ROM cells  23   a  to  23   i  are connected to the ground GND. The ROM cells  23   a  to  23   i  are constructed similarly to the ROM cells  21   a  to  21   q  (FIG.  27 ). 
     If the output signal O of any of the logical boundary detection circuits  22   a  to  22   i  has an H level, then the N-channel MOS transistor CT of that one of the ROM cells  23   a  to  23   i  is turned on, and the Gray code signal g 1  or g 1   x  is output from the bit line BL 1  or BL 1 x. At this time, the bit line BL 1  or BL 1   x  to which the one of the ROM cells  23   a  to  23   i  is connected has the ground GND level. 
     To the bit line BL 1 , every other ROM cells  23   c ,  23   e ,  23   g  and  23   i  beginning with the ROM cell  23   a  in the lowest order are connected. To the bit line BL 1 X, every other ROM cells  23   d ,  23   f  and  23   h  beginning with the ROM cell  23   b  in the lowest order are connected. 
     A detailed construction of the third encoding section  13  is show in FIG.  21 . The third encoding section  13  has eight logical boundary detection circuits  24   a  to  24   h  which have the same construction as the logical boundary detection circuits  18   a  to  18   q  of the first encoding section  11 . 
     Input terminals IA of the logical boundary detection circuits  24   a  to  24   g  receive the even-numbered thermometer code bits e 4 , e 8 , e 12 , e 1 G, e 20 , e 24  and e 28 , respectively. The ground GND level is supplied to the input terminals IA and IB of the logical boundary detection circuit  24   h  in the highest order. Input terminals IB of the logical boundary detection circuits  24   a  to  24   g  receive the even-numbered thermometer code bits e 4 , e 8 , e 12 , e 16 , e 20 , e 24  and e 28 , respectively. Input terminal IX of the logical boundary detection circuit  24   b  receives an inverted signal of logical NORing. That is, a logically ORed signal of the thermometer code bits e 4  and e 6 , is input thereto. Similarly, input terminals IX of the logical boundary detection circuits  24   c  to  24   h  receive logically ORed signals of the thermometer code bits e 8 , e 10 , e 12 , e 14 , e 16 , e 18 , e 20 , e 22 , e 24 , e 26 , e 28  and e 30 , respectively. The power supply signal V CC  is input to an input terminal IX of the logical boundary detection circuit  24   a.    
     Output signals O of the logical boundary detection circuits  24   a  to  24   h  are output as signals ga to gh and substantially simultaneously input to terminals A of ROM cells  25   a  to  25   h , respectively. Terminals C of the ROM cells  25   a  to  25   h  are each connected to one of bit lines BL 2   a  and BL 2   b . Terminals B of the ROM cells  25   a  to  25   h  are connected to the ground GND. The ROM cells  25   a  to  25   h  are constructed similarly to the ROM cells  21   a  to  21   q  (FIG.  27 ). 
     If the level of the output signal O of any of the logical boundary detection circuits  24   a  to  24   h  has an H level, then the N-channel MOS transistor CT of that one of the ROM cells  25   a  to  25   h  is turned on, and the binary code signal g 2   a  or g 2   b  is output from the bit line BL 2   a  or BL 2   b . At this time, the bit line BL 2   a  or BL 2   b  to which the one of the ROM cells  25   a  to  25   h  is connected has the ground GND level. 
     To the bit line BL 2   a , every other ROM cells  25   c ,  25   e  and  25   g  beginning with the ROM cell  25   a  in the lowest order are connected. To the bit line BL 2   b , every other ROM cells  25   d ,  25   f  and  25   h  beginning with the ROM cell  25   b  in the lowest order are connected. 
     The fourth encoding section  14  is described with reference to FIG.  22 . Output signals g 0 Xa and g 0 Xb of the bit lines BL 0 Xa and BL 0 Xb are input to a NAND circuit  27   a , and an output signal of the NAND circuit  27   a  is inverted by an inverter circuit  28   a  to produce a Gray code bit g 0 X. Output signals g 0   a  and g 0   b  of the bit lines BL 0   a  and BL 0   b  are input to a NAND circuit  27   b , and an output signal of the NAND circuit  27   b  is inverted by an inverter circuit  28   b  to produce a Gray code bit g 0 . 
     Output signals gb and gc of the logical boundary detection circuits  24   b  and  24   c  are input to a NOR circuit  26   a , and output signals gf and gg of the logical boundary detection circuits  24   f  and  24   g  are input to a NOR circuit  26   b . Output signals of the NOR circuit  26   a  and  26   b  are input to a NAND circuit  27   c , and a Gray code bit g 2  is output from the NAND circuit  27   c.    
     Output signals gc and gd of the logical boundary detection circuits  24   c  and  24   d  are input to a NOR circuit  26   c ; output signals ge and gf of the logical boundary detection circuits  24   e  and  24   f  are input to a NOR circuit  26   d ; and output signals gg and gh of the logical boundary detection circuits  24   g  and  24   h  are input to a NOR circuit  26   e . An output signal of the NOR circuit  26   c  is input to a NAND circuit  27   d ; an output signal of the NOR circuit  26   d  is input to NAND circuits  27   d  and  27   e ; and an output signal of the NOR circuit  26   e  is input to the NAND circuit  27   e . Then, a Gray code bit g 3  is output from the NAND circuit  27   d , and a Gray code bit g 4  is output from the NAND circuit  27   e.    
     A detailed construction of the error signal production section  15  is described with reference to FIG.  23 . The output signal g 1  of the bit line BL 1  is input to a NAND circuit  29   a . The output signal g 0   a  of the bit line BL 0   a  is inverted by an inverter circuit  28   c  and input to the NAND circuit  29   a . The output signal g 1 X of the bit line BL 1 X is input to a NAND circuit  29   b . The output signal g 0   b  of the bit line BL 0   b  is inverted by an inverter circuit  28   d  and input to the NAND circuit  29   b . An output signal ER 1 A of the NAND circuit  29   a  and an output signal ER 1 B of the NAND circuit  29   b  are input to a NAND circuit  29   e , and an error signal er 1  is output from the NAND circuit  29   e.    
     An output signal g 2   a  of the bit line BL 2   a  is input to a NAND circuit  29   c , and an output signal g 0 Xa of the bit line BL 0 Xa is inverted by an inverter circuit  28   e  and input to the NAND circuit  29   c . An output signal g 2   b  of the bit line BL 2   a  is input to a NAND circuit  29   d , and an output signal g 0 Xb of the bit line BL 0 Xb is inverted by an inverter circuit  28   f  and input to the NAND circuit  29   d . An output signal ER 2 A of the NAND circuit  29   c  and an output signal ER 2 B of the NAND circuit  29   d  are input to a NAND circuit  29   f , and an error signal er 2  is output from the NAND circuit  29   f . The error signals er 1  and er 2  are provided to the error correction section  16  and, as shown in FIG. 18, and are output from output terminals of the error signal production section  15 . 
     A detailed construction of the error correction section  16  is described with reference to FIG.  24 . The error signal er 2  and the signal g 1 X are input to a NAND circuit  30   a , and the Gray code bit g 2  is inverted by an inverter circuit  33   a  and input to the NAND circuit  30   a . An output signal of the NAND circuit  30   a  and the Gray code bit g 4  are input to an XOR circuit  32   a , and an output signal of the XOR circuit  32   a  is inverted by an inverter circuit  33   c  and output as a correction Gray code bit g 4 Z. The error signal er 2 , the signal g 1 X and the Gray code bit g 2  are input to a NAND circuit  30   b . An output signal of the NAND circuit  30   b  and the Gray code bit g 3  are input to an XOR circuit  32   b , and an output signal of the XOR circuit  32   b  is inverted by an inverter circuit  33   d  and output as a correction Gray code bit g 3 Z. The error signal er 2  and the Gray code bit g 1  are input to a NAND circuit  30   c . An output signal of the NAND circuit  30   c  and the Gray code bit g 2  are input to an XOR circuit  32   c , and an output signal of the XOR circuit  32  is inverted by an inverter circuit  33   e  and input as a correction Gray code bit g 2 Z. 
     The error signal er 1  is inverted by an inverter circuit  33   b  and input to an XOR circuit  32   d , and the Gray code signal g 1  is input to the XOR circuit  32   d . An output signal is of the XOR circuit  32   d  is inverted by an inverter circuit  33   f  and output as a correction Gray code bit g 1 Z. 
     The error signals er 2  and er 1  are input to a NOR circuit  31 , and an output signal of the NOR circuit  31  and the Gray code signal g 0  are input to an XOR circuit  32   e . An output signal of the XOR circuit  32   e  is inverted by an inverter circuit  33   g  and output as a correction Gray code bit g 0 Z. 
     A detailed construction of the Gray to binary conversion section  17  is shown in FIG.  25 . The Gray code bit g 4 Z is input to an XOR circuit  35   a  and output as a binary code bit B 4 Z through two stages of inverter circuits  34   a  and  34   b . The correction Gray code bits g 3 Z and g 4   z  are input to the XOR circuit  35   a , and an output signal of the XOR circuit  35   a  is output as a binary code bit B 3 Z and input to an XOR circuit  35   b . The correction Gray code bit g 2 Z is input to the XOR circuit  35   b , and an output signal of the XOR circuit  35   b  is output as a binary code bit B 2 Z and input to an XOR circuit  35   c . The correction Gray code bit g 1 Z is input to the XOR circuit  35   c , and an output signal of the XOR circuit  35   c  is output as a binary code bit B 1 Z and is input to an XOR circuit  35   d . The correction Gray code bit g 0 Z is input to the XOR circuit  35   d , and an output signal of the XOR circuit  35   d  is output as a binary code bit B 0 Z. 
     One of precharge circuits  36  and  37 , shown in FIGS. 28 and 30, is connected between the bit lines BL 1  and BL 1 X. A similar precharge circuit is connected between the bit lines BL 2   a  and BL 2   b . The precharge circuit  36  includes a pair of P-channel MOS transistors T rp1  and T rp2  whose sources are connected to the power supply V CC  and whose gates are connected to the drains of the other transistors relative to each other. A plurality of N-channel MOS transistors T rn  are connected in parallel between the drain of the transistor T rp1  and a power supply Vss (GND), and output signals of the logical boundary detection circuits  22   a ,  22   c ,  22   e ,  22   g  and  22   i  which control the bit line BL 1  through the ROM cells  23   a ,  23   c ,  23   e ,  23   g  and  23   i  are input as gate signals, V 1  to the gates of the transistors T rn . 
     A plurality of N-channel MOS transistors T rnx  are connected in parallel between the drain of the transistor T rp2  and the power supply Vss, and output signals of the logical boundary detection circuits  22   b ,  22   d ,  22   f  and  22   h  which control the bit line BL 1 X through the ROM cells  23   b ,  23   d ,  23   f  and  23   h  are input as gate signals V 1 X to the gates of the transistors T rnx . The drain of the transistor T rp1  is connected to the bit line BL 1 , and the drain of the P-channel MOS transistor T rp2  is connected to the bit line BL 1 X. 
     In the precharge circuit  36 , as shown in FIG. 29, if, the level of one of the gate signals V 1  goes high to turn on a corresponding one of the transistors T rn  and all of the gate signals V 1 X go low, then the transistor T rp1  is turned off and the transistor T rp2  is turned on. Consequently, the level of the bit line BL 1  is changed to an L level while the level of the bit line BL 1 X is changed to an H level, and the bit line BL 1 X is precharged to the power supply V CC  level. 
     On the other hand, if the level of one of the gate signals V 1 X to the transistors T rnx  goes high to turn on a corresponding one of the transistors T rnx  and all of the gate signals V 1  to the transistors T rn  go low, then the transistor T rp1  is turned on while the transistor T rp2  is turned off. Consequently, the level of the bit line BL 1  is changed to an H level while the level of the bit line BL 1 X is changed to an L level, and the bit lines BL 1  is precharged to the power supply V CC . In the precharge circuit  36 , one of the bit lines BL 1  and BL 1 X is precharged after the level of the other falls. 
     The precharge circuit  37  shown in FIG. 30 is different from the precharge circuit  36  in that the gates of the transistors T rp1  and T rp2  are connected to each other and connected also to the drain of the transistor T rp1 . In the precharge circuit  37 , one of the bit lines BL 1  and BL 1 X is precharged simultaneously as the level of the other falls, as shown in FIG. 31, and consequently, the speed in precharging operation is higher. 
     Precharge circuits  38   a  to  38   d  shown in FIG. 32 are connected to the bit lines BL 0   a , BL 0   b , BL 0 Xa and BL 0 Xb of the first encoding section  11 , respectively. The precharge circuit  38   a  includes three P-channel MOS transistors connected in parallel between the bit line BL 0   a  and the power supply V CC . The Gray code bits g 0   b , g 0 Xa and g 0 Xb are provided to the gates of the transistors. When the Gray code bit g 0   a  does not have an L level, one of the Gray code bits g 0   b , g 0 Xa and g 0 Xb has an L level, and consequently, the bit line BL 0   a  is precharged to the power supply V CC  level. 
     The precharge circuit  38   b  includes three P-channel MOS transistors connected in parallel between the bit line BL 0   b  and the power supply V CC . The Gray code bits g 0   a , g 0 Xa and g 0 Xb are provided to the gates of the transistors. When the Gray code bit g 0   b  does not have an L level, one of the Gray code bits g 0   a , g 0 Xa and g 0 Xb has an L level, and consequently, the bit line BL 0   b  is precharged to the power supply V CC  level. 
     The precharge circuit  38   c  includes three P-channel MOS transistors connected in parallel between the bit line BL 0 Xa and the power supply V CC . The Gray code bits g 0   a , g 0   b  and g 0 Xb are provided to the gates of the transistors. When the Gray code bit g 0 Xa does not have an L level, one of the Gray code bits g 0   a , g 0   b  and g 0 Xb has an L level, and consequently, the bit line BL 0 Xa is precharged to the power supply V CC  level. 
     The precharge circuit  38   d  includes three P-channel MOS transistors connected in parallel between the bit line BL 0 Xb and the power supply V CC . The Gray code bits g 0   a , g 0   b  and g 0 Xa are provided to the gates of the transistors. When the Gray code bit g 0 Xb does not have an L level, one of the Gray code bits g 0   a , g 0   b  and g 0 Xa has an L level, and consequently, the bit line BL 0 Xb is precharged to the power supply V CC  level. 
     Operation of the encoder of the first embodiment is described below. When a 5-bit Gray code g 0  to g 4  is produced from a thermometer code e 1  to e 31 , the first encoding section  11  produces Gray code bits g 0   a , g 0   b , g 0 Xa and g 0 Xb for production of the Gray code bit go of the lowest order, in accordance with a bit independent decoding system. The Gray code bit g 0 Xa is a back code of the Gray code bit g 0   a , and the Gray code bit g 0 Xb is a back code of the Gray code bit g 0   b.    
     Three successive ones of the odd-numbered bits of the thermometer code e 1  to e 31  from the lower order side are input to each of the logical boundary detection circuits  18   a  to  18   q . When a regular thermometer code e 1  to e 31  is input to the logical boundary detection circuits  18   a  to  18   q , such Gray code bits g 0   a , g 0   b , g 0 Xa and g 0 Xb as illustrated in FIG. 33 are output from the bit lines BL 0   a , BL 0   b , BL 0 Xa and BL 0 Xb of the first encoding section  11 , respectively. 
     The Gray code bit g 0 Xa corresponds to a signal obtained by logically ORing the signals Z 1 , Z 3 , Z 5  and Z 7  illustrated in FIG. 9 while the Gray code bit g 0 Xb corresponds to another signal obtained by logically ORing the signals Z 2 , Z 4 , Z 6  and Z 8  illustrated in FIG.  9 . One of the Gray code bits g 0   a , g 0   b , g 0 Xa and g 0 Xb exhibits an L level based on the thermometer code e 1  to e 31 . 
     The ROM cells  21   a  to  21   q , which are driven by the logical boundary detection circuits  18   a  to  18   q , respectively are successively connected to the bit lines BL 0   a , BL 0 Xa, BL 0   b  and BL 0 Xb. In particular, every fourth logical boundary detection circuit is connected to each of the bit lines BL 0   a , BL 0 Xa, BL 0   b  and BL 0 Xb through a ROM cell, and where four logical boundary detection circuits connected successively to the bit lines BL 0   a , BL 0 Xa, BL 0   b  and BL 0 Xb make one cycle, the logical boundary detection circuits  18   a  to  19   b  are connected at one-cycle intervals to the bit lines BL 0   a , BL 0 Xa, BL 0   b  and BL 0 Xb. 
     If “. . . 110100. . . ”, that is, a thermometer code e 1  to e 31  which includes a babble error of the b1 type, is input to the first encoding section  11 , then an error originating from the babble error is included in the Gray code bits g 0   a , g 0   b , g 0 Xa and g 0 Xb as shown in FIG.  34 . 
     If “. . . 1100100. . . ”, that is, a thermometer code e 1  to e 31  including a babble error of the b2H type, is input to the first encoding section  11 , then the Gray code bits g 0   a , g 0   b , g 0 Xa and g 0 Xb are corrected to a signal which includes an error similar to that originating from a babble error of the b1 type as shown in FIG. 35 because three successive ones of the odd-numbered bits of the thermometer code e 1  to e 31  from the lowest order side are input to each of the logical boundary detection circuits  18   a  to  18   q . 
     If “. . . 11011000. . . ”, that is, a thermometer code e 1  to e 31  including a babble error of the b2L type, is input to the first encoding section  11 , then the Gray code bits g 0   a , g 0   b , g 0 Xa and g 0 Xb are corrected as shown in FIG. 36 so that they may be equal to the Gray code bits g 0   a , g 0   b , g 0 Xa and g 0 Xb which originate from the thermometer code e 1  to e 31  which includes no babble error illustrated in FIG.  33 . 
     In any of the cases, one of the Gray code bits g 0   a , g 0   b , g 0 Xa and g 0 Xb has an L level while the others have an H level. Accordingly, that one of the bit lines BL 0   a , BL 0 Xa, BL 0   b  and BL 0 Xb which does not output a Gray code bit having an L level is precharged to the power supply V CC  by the operation of the precharge circuit  38   a  to  38   d  in parallel to the encoding operation. 
     The second encoding section  12  produces, when the 5-bit Gray code g 0  to g 4  is produced from the thermometer code e 1  to e 31 , the second Gray code bit g 1  from the lowest order side and the code bit g 1 X which is complementary signal to the Gray code bit g 1  in accordance with a bit independent decoding system. 
     To each of the logical boundary detection circuits  22   a  to  22   i , three signals based on even-numbered ones of the thermometer codes e 2  to e 30  from the lowest order side are successively input. When regular thermometer code bits e 2  to e 30  are input to the logical boundary detection circuits  22   a  to  22   i , such Gray code bits g 1  and g 1 X as illustrated in FIG. 33 are output from the bit lines BL 1  and BL 1 X of the second encoding section  12 , respectively. 
     The Gray code bit g 1  corresponds to the Gray code bit G 1  illustrated in FIG.  9 . The Gray code bit g 1 X is a back code to the Gray code bit g 1 . The Gray code bits G 1  and g 1 X have a mutually complementary relationship. 
     Such logic as just described is produced by connecting the ROM cells  23   a  to  23   i , which are driven by the logical boundary detection circuits  22   a  to  22   i , respectively, alternately to the bit lines BL 1  and BL 1 X. In particular, every other logical boundary detection circuit is connected to each of the bit lines BL 1  and BL 1 X through a ROM cell, and where two logical boundary detection circuits connected successively to the bit lines BL 1  and BL 1 X make one cycle, the logical boundary detection circuits  22   a  to  22   i  are connected at one-cycle intervals to the bit lines BL 1  and BL 1 X. 
     If “. . . 110100. . . ”, that is, the b 1  type babble error is input to the second encoding section  12 , then an error originating from the babble error is included in the Gray code bits g 1  and g 1 X, as shown in FIG.  34 . 
     If “. . . 1100100. . . ”, that is, the b2H type babble error is input to the second encoding section  12 , then the Gray code bits g 1  and g 1 X are corrected to a signal which includes an error similar to that originating from a babble error of the b 1  type as illustrated in FIG. 35 because three signals based on even-numbered ones of the thermometer code bits e 2  to e 30  from the lowest order side are successively input to each of the logical boundary detection circuits  22   a  to  22   i.    
     If “. . . 1101100. . . ”, that is, the b 2 L type babble error is input to the second encoding section  12 , then the Gray code bits g 1  and g 1 X are corrected, as shown in FIG. 33, so that they may be equal to the Gray code bits g 1  and g 1 X originating from the thermometer code bits e 2  to e 30  which include no babble error shown in FIG.  33 . 
     In all cases, the Gray code bits g 1  and g 1 X are complementary signals. Accordingly, that one of the bit lines BL 1  and BL 1 X which does not output a Gray code bit having an L level is precharged to the power supply V CC  level in parallel to the encoding operation. 
     The third encoding section  13  produces, when the 5-bit Gray code g 0  to g 4  is produced from the thermometer code bits e 1  to e 31 , logical boundary detection signals ga to gh for production of the third to fifth Gray code bits g 2  to g 4  from the lowest order side and the binary code bits g 2   a  and g 2   b  in accordance with a bit independent decoding system. 
     To each of the logical boundary detection circuits  24   a  to  24   h , three signals based on even-numbered ones of the thermometer code bits e 4  to e 30  from the lowest order side are successively input. When normal thermometer code bits e 4  to e 30  are input to the logical boundary detection circuits  24   a  to  24   h , such binary code bits g 2   a  and g 2   b  as illustrated in FIG. 33 are output from the bit lines BL 2   a  and BL 2   b  of the third encoding section  13 . 
     The binary code bits g 2   a  and g 2   b  have a mutually complementary relationship to each other and are equal to values obtained by shifting the Gray code bits g 1  and g 1 X in a decimal value in FIG. 9 to the upper order side by a two-digit distance. 
     Such logic is produced by connecting the ROM cells  25   a  to  25   h , which are driven by the logical boundary detection circuits  24   a  to  24   h , respectively, alternately to the bit lines BL 2   a  and BL 2   b . In other words, every other logical boundary detection circuit is connected to each of the bit lines BL 2   a  and BL 2   b  through a ROM cell, and if the two logical boundary detection circuits connected alternately to the bit lines BL 2   a  and BL 2   b  make one cycle, then the logical boundary detection circuits  24   a  to  24   h  are connected at one-cycle intervals to the bit lines BL 2   a  and BL 2   b . The logical boundary detection signals ga to gh are output from the logical boundary detection circuits  24   a  to  24   h , respectively. 
     If “. . . 110100. . . ”, that is, the b1 type babble error is input to the third encoding section  13 , then an error originating from the babble error is included in the binary code bits g 2   a  and g 2   b , as shown in FIG.  34 . 
     If “. . . 1100100. . . ”, that is, the b2H type babble error is input to the third encoding section  13 , then the binary code bits g 2   a  and g 2   b  are corrected to a signal which includes an error similar to that originating from the babble error of the b 1  type as illustrated in FIG. 35 because three signals based on even-numbered ones of the thermometer code bits e 4  to e 30  from the lowest order side are successively input to each of the logical boundary detection circuits  24   a  to  24   h.    
     If “. . . 1101100. . . ”, that is, the b2L type babble error is input to the third encoding section  13 , then the binary code bits g 2   a  and g 2   b  are corrected, as shown in FIG. 36, so that they may be equal to the binary code bits g 2   a  and g 2   b  originating from the thermometer code bits e 4  to e 30  which include no babble error shown in FIG.  33 . 
     In all cases, the binary code bits g 2   a  and g 2   b  are complementary signals. Accordingly, that one of the bit lines BL 2   a  and BL 2   b  which does not output a Gray code bit having an L level is precharged to the power supply V CC  level in parallel with the encoding-operation. 
     The fourth encoding section  14  produces the Gray code bits g 0  and g 0 X of the lowest order by logical processing of the Gray code signals g 0   a , g 0   b , g 0 Xa and g 0 Xb and produces the third to fifth Gray code bits g 2  to g 4  from the lowest order side by logical processing of the logical boundary detection signals gb to gh. 
     If regular Gray code signals g 0   a , g 0   b , g 0 Xa and g 0 Xb and logical boundary detection signals gb to gh originating from a regular thermometer code e 1  to e 32  are input to the fourth encoding section  14 , then Gray code bits g 0  and g 2  to g 4  which do not include an error are produced as shown in FIG.  33 . The second Gray code bit g 1  from the lowest order side is produced by the second encoding section  12 . 
     If Gray code signals g 0   a , g 0   b , g 0 Xa and g 0 Xb and logical boundary detection signals gb to gh originating from “. . . 110100. . . ”, that is, the b 1  type babble error are input, then an error originating from the babble error is included in the Gray code g 0  to g 4  as shown in FIG.  34 . 
     If the Gray code signals g 0   a , g 0   b , g 0 Xa and g 0 Xb and the logical boundary detection signals gb to gh originating from “. . . 1100100. . . ”, that is, the b2H type babble error are input, then the Gray code g 0  to g 4  makes a signal which includes an error similar to that originating from the babble error of the b1 type. 
     If the Gray code signals g 0   a , g 0   b , g 0 Xa and g 0 Xb and the logical boundary detection signals gb to gh originating from “. . . 1101100. . . ”, that is, the b 2 L type babble error, then the Gray code g 0  to g 4  makes, as shown in FIG. 36, a signal which includes no error similarly as in FIG.  33 . 
     The error signal production section  15  is a circuit which detects whether or not the Gray code signals g 0   a , g 0   b , g 0 Xa, g 0 Xb, g 1  and g 1 X and the binary code bits g 2   a  and g 2   b  satisfy the relationship of the Gray code illustrated in FIG. 9, and outputs, if the relationship is not satisfied, error signals er 1  and er 2  having an H level. 
     In particular, when regular Gray code bits g 1  and g 0   a  are input to the NAND circuit  29   a , the Gray code bit g 0   a  has an L level, and the Gray code bit g 1  has an L level, so that the output signal ER 1 A having an H level is output. When regular Gray code bits g 1 X and g 0   b  are input to the NAND circuit  29   b , the Gray code bit g 0   b  has an L level, and the Gray code bit g 1 X has an L level, so that the output signal ER 1 B having an H level is output. Accordingly, when normal Gray code bits g 1 , g 1 X, g 0   a  and g 0   b  are input, the output signals ER 1 A and ER 1 B both have an H level, and the error signal er 1  output from the NAND circuit  29   e  has an L level. 
     Similarly, when a normal binary code bit g 2   a  and a normal Gray code bit g 0 Xa are input to the NAND circuit  29   c , the Gray code bit g 0 Xa has an L level, and the binary code bit g 2   a  has an L level, so that the output signal ER 2 A having an H level is output. When a normal binary code bit g 2   b  and a normal Gray code bit g 0 Xb are input to the NAND circuit  29   d , the Gray code bit g 0 Xb has an L level, the binary code bit g 2   b  has an L level, so that the output signal ER 2   b  having an H level is output. Accordingly, when normal Gray code bits g 2   a , g 2   b , g 0 Xa and g 0 Xb are input, the output signals ER 2 A and ER 2 B both have an H level, and the error signal er 2  output from the NAND circuit  29   f  has an L level. 
     When the Gray code signals g 0   a , g 0   b , g 0 Xa, g 0 Xb, g 1  and g 1 X and the binary code bits g 2   a  and g 2   b  include an error as shown in FIGS. 34 and 35, it sometimes occurs that the condition in a regular case becomes not satisfied and the output signals ER 1 A to ER 2 B having an L level is output. In this instance, the error signals er 1  and er 2  have H levels. 
     The error correction section  16  shown in FIG. 24 corrects the Gray code bits g 0  to g 4 , which include an error, to likely values based on the error signals er 1  and er 2 . The correcting operation inverts that one of the Gray code bits g 0  to g 4  from which the error has been detected in connection with the correction principle. In particular, as shown in FIGS. 34 and 35, when the Gray code bit g 4  exhibits an error, the error signal er 2  and the Gray code signal g 1 X have an H level and the Gray code signal g 2  has an L level, and the output signal of the NAND circuit  30   a  has an L level. Consequently, by operation of the XOR circuit  32   a  and the inverter circuit  33   c , a correction Gray code bit g 4 Z inverted from the Gray code bit g 4  is output. On the other hand, when the error signal er 2  and the Gray code bits g 1 X and g 2  have the other values than those described above, the Gray code bit g 4  is normal and the output signal of the NAND circuit  30   a  has an H level, and consequently, the correction Gray code bit g 4 Z has the same phase as that of the Gray code bit g 4 . 
     When the Gray code bit g 3  exhibits an error, the error signal er 2  and the Gray code signals g 1 X and g 2  have an H level and the output signal of the NAND circuit  30   a  has an L level. Consequently, the correction Gray code bit g 3 Z inverted from the Gray code bit g 3  is output by operation of the XOR circuit  32   b  and the inverter circuit  33   d . On the other hand, when the error signal er 2  and the Gray code signals g 1 X and g 2  have any other values than those described above, the Gray code bit g 3  is normal, and the output signal of the NAND circuit  30   b  has an H level. Consequently, the correction Gray code bit g 3 Z has a phase same as that of the Gray code bit g 3 . 
     When the Gray code bit g 2  exhibits an error, the error signal er 2  and the Gray code signal g 1  have an H level, and the output of the NAND circuit  30   c  has an L level. Consequently, the correction Gray code bit g 2 Z inverted from the Gray code bit g 2  is output by operation of the XOR circuit  32   c  and the inverter circuit  33   e . On the other hand, when the error signal er 2  and the Gray code signal g 1  have values other than those described above, the Gray code bit g 2  is normal, and the output signal of the NAND circuit  30   c  has an H level. Consequently, the correction Gray code bit g 2 Z has a phase same as that of the Gray code bit g 2 . 
     When the Gray code bit g 1  exhibits an error, the error signal er 1  has an H level, and the output signal of the inverter circuit  33   b  has an L level. Consequently, the correction Gray code bit g 1 Z inverted from the Gray code bit g 1  is output by operation of the XOR circuit  32   d  and the inverter circuit  33   f . On the other hand, when the error signal er 2  has an L level, the Gray code bit g 1  is normal, and the output signal of the inverter circuit  33   b  has an H level. Consequently, the phase of the correction Gray code bit g 1 Z becomes same as that of the Gray code bit g 1 . 
     When the Gray code bit g 0  exhibits an error, at least one of the error signals er 1  and er 2  has an H level, and the output signal of the NOR circuit  31  has an L level. Consequently, the correction Gray code bit g 0 Z inverted from the Gray code bit g 0  is output by operation of the XOR circuit  32   e  and the inverter circuit  33   g . On the other hand, when both of the error signals er 1  and er 2  have L levels, the output signal of the NOR circuit  31  has an H level, and consequently, the correction Gray code bit g 0 Z has a phase same as that of the Gray code bit g 0 . 
     The Gray to binary conversion section  17  shown in FIG. outputs the correction Gray code bit g 4 Z as a binary code bit B 4 Z, outputs a value obtained by logically ORing the correction Gray code bits g 4 Z and g 3 Z as a binary code bit B 3 Z, outputs a value obtained by logically ORing the binary code bit B 3 Z and the correction Gray code bit g 2 Z as a binary code bit B 2 Z, outputs a value obtained by logically ORing the binary code bit B 2 Z and the correction Gray code bit g 1 Z as a binary code bit B 1 Z, and outputs a value obtained by logically ORing the binary code bit B 1 Z and the correction Gray code bit g 0 Z as a binary code bit B 0 Z. By such operation, the correction Gray code bits g 0 Z to g 4 Z is converted into binary code bits B 0 Z to B 4 Z. 
     The encoder  100  of the present invention provides the following advantages: 
     (1) Even if the B 1  type, the b 2 H type or the b 2 L type babble error is included in a thermometer code e 1  to e 31 , the encoder produces a binary code B 0 Z to B 4 Z in which the babble error has been corrected; 
     (2) Since each of the logical boundary detection circuits of the first encoding section  11  is a 3-input circuit receiving odd-numbered ones of thermometer codes, the b 1  type babble error is not corrected, but the b2H type babble error is corrected so as to become an error equivalent to that when the b 1  type babble error is input, and the b 2 L type babble error is corrected to a likely value; 
     (3) Since each of the logical boundary detection circuits of the second and third encoding sections  12  and  13  is a 3-input circuit receiving the odd-numbered thermometer code bits of the thermometer code e 1  to e 31  and logically ORed values of the thermometer code, the b 1  type babble error is not corrected, but the b 2 H type babble error is corrected so as to become equivalent to that when the b 1  type babble error is input whereas the b 2 L type babble error is corrected to a likely value; 
     (4) Since the first encoding section  11  successively connects the ROM cells  21   a  to  21   q , which operate in response to the output signals of the logical boundary detection circuits  18   a  to  18   q , respectively, to the bit lines BL 0   a , BL 0   b , BL 0 Xa and BL 0 Xb, the front code bits g 0   a  and g 0   b  and the back code bits g 0 Xa and g 0 Xb decomposed from the Gray code bit g 0  of the lowest order are produced; 
     (5) Since the second encoding section  12  successively connects the ROM cells  23   a  to  23   i , which operate in response to the output signals of the logical boundary detection circuits  22   a  to  22   i , respectively, to the bit lines BL 1  and BL 1 X, the second Gray code bit g 1  from the lowest order side and the back code bit g 1 X to the Gray code bit g 1  are produced; 
     (6) Since the third encoding section  13  successively connects the ROM cells  23   a  to  23   i , which operate in response to the output signals of the logical boundary detection circuits  24   a  to  24   h , respectively, to the bit lines BL 1  and BL 1 X, a signal equivalent to the binary code bit B 2  obtained by shifting the second Gray code bit g 1  and the back code g 1 X to the upper order side by a two-position distance in decimal value. Further, the logical boundary detection signals ga to gh are output from the logical boundary detection circuits  24   a  to  24   h , respectively; 
     (7) The fourth encoding section  14  logically processes the logical boundary detection signals gb to gh produced by the third encoding section  13  to produce the third to fifth Gray code bits g 2  to g 4  from the lowest order side. Further, the fourth encoding section  14  produces the Gray code bit g 0  of the lowest order by logically processing the Gray code bits g 0   a , g 0   b , g 0 Xa and g 0 Xb produced by the first encoding section  11 ; 
     (8) By logically processing the output signals of the first to third encoding sections  11 ,  12  and  13 , the error signal production section  15  performs error detection based on the error detection principle illustrated in FIG. 9, and when an error is present, the error signal production section  15  produces the error signals er 1  and er 2  having an H level; 
     (9) The error correction section  16  performs correction for the Gray code go to g 4  which includes the b 1  type error based on the error signals er 1  and er 2  and the Gray code bits g 1 , g 1 X and g 2  to produce a correction Gray code bit g 0 Z to g 4 Z; 
     (10) The Gray to binary conversion section  17  converts the correction Gray code g 0 Z to g 4 Z into a binary code B 0 Z to B 4 Z; 
     (11) The precharge circuits  38   a  to  38   d  are connected to the four bit lines BL 0   a , BL 0   b , BL 0 Xa and BL 0 Xb of the first encoding section  11 , and by a Gray code bit having an L level output from one of the bit lines, the other three bit lines are precharged to the power supply V CC  level. Accordingly, a precharging operation of the bit lines is performed in parallel to the encoding operation of the thermometer code bits e 1  to e 31  into the Gray code bits g 0   a , g 0   b , g 0 Xa and g 0 Xb; 
     (12) One of the precharge circuits  36  and  37  is connected to each of the bit lines BL 1 , BL 1 X, BL 2   a  and BL 2   b  of the second and third encoding sections  12  and  13 , and the other bit lines are precharged based on a signal having an L level output from the one bit line. Accordingly, a precharging operation of the bit lines is performed in parallel to the encoding operation of the thermometer code bits e 2  to e 30  into the Gray code bits g 1  and g 1 X and the binary cod bits g 2   a  and g 2   b;    
     (13) Since the encoding operation of a thermometer code and the precharging operation of the bit lines are performed in parallel, there is no need of performing precharging in one cycle of the encoding operation. Accordingly, an increased encoding speed is achieved; 
     (14) Since, in the first encoding section  11 , a bit line is divided into four lines and numbers of ROM cells equal to each other are connected to the individual bit lines, the number of ROM cells connected to each bit line is reduced. Accordingly, since the load to each ROM cell is reduced, the speed of the encoding operation is increased. Further, since, different from the encoding section shown in FIGS. 4 and 5, in the first embodiment of the present invention, ROM cells are connected one by one to the individual logical boundary detection circuits, the loads to the logical boundary detection circuits are equal to each other. Accordingly, occurrence of an error which arises from a difference in load condition among the logical boundary detection circuits is prevented; 
     (15) Comparing with the conventional encoder of the Gray code system shown in FIG. 7, the encoder of the first embodiment does not increase the number of elements and the circuit area because the numbers of logical boundary detection circuits and ROM cells are decreased comparing with the conventional encoder; and 
     (16) The error signals er 1  and er 2  produced by the error signal production section  15  are output from the error signal output terminals to the outside. Then, when a performance test of the A/D converter is performed, whether or not an error is included in thermometer code bits e 1  to e 31  is detected readily by detecting the error signals er 1  and er 2  using a testing apparatus. In a conventional performance test for an A/D converter, presence or absence of an error in a thermometer code is detected based on a digital output signal of a binary code. In other words, an error of a thermometer code is detected from a digital output signal by detecting a deterioration in linearity or S/N ratio of the digital output signal caused by an error of the thermometer code by performing fast Fourier transform processing for calculating a spectrum of frequency components or the like. Accordingly, in the present embodiment, the cost for a test is decreased because a performance test for an A/D converter is performed without performing complicated processing such as fast Fourier transform processing. 
     (Second Embodiment) 
     FIG. 37 shows a second embodiment of an encoder embodying the present invention. The encoder of the second embodiment includes first to fourth encoding sections  41  to  44 , an error signal production section  45 , and a Gray to binary conversion section  46 . 
     The first to third encoding sections  41  to  43  and the error signal production section  45  have similar constructions to those of the first embodiment, and accordingly, description of them is omitted here. The fourth encoding section  44  shown in FIG. 39 logically processes logical boundary detection signals gb, gc, gf and gg output from the third encoding operation  43  by means of NOR circuits  47   a  and  47   b  and a NAND circuit  48  to produce a Gray code bit g 2 . 
     The Gray to binary conversion section  46  has functions of the error correction section  16  and the Gray to binary conversion section  17  of the first embodiment and produces binary code bits B 0 Z to B 4 Z based on signals produced by the first to fourth encoding sections  41  to  44  and the error signal production section  45 . 
     As shown in FIG. 38, the Gray code bit g 2  is inverted by an inverter circuit  49   a  and input to a NAND circuit  50   a , and a Gray code bit g 1 X and an error signal er 2  are input to the NAND circuit  50   a . An output signal of the NAND circuit  50   a  is input to an XOR circuit  52   a.    
     The logical boundary detection signals gf and ge are input to a NOR circuit  51   a  while the logical boundary detection signals gh and gg are input to a NOR circuit  51   b , and the logical boundary detection signals gd and gc are input to a NOR circuit  51   c . Output signals of the NOR circuits  51   a  and  51   b  are input to a NAND circuit  50   b , and an output signal of the NAND circuit  50   b  is input to the XOR circuit  52   a . An output signal of the XOR circuit  52   a  is inverted by an inverter circuit  49   b  and output as a binary code bit B 4 Z. The NAND circuits  50   a  and  50   b  output binary code bits for production of the binary code bit B 4 Z whose error is corrected. 
     Output signals of the NOR circuits  51   b  and  51   c  are input to a NAND circuit  50   c , and an output signal of the NAND circuit  50   c  is input to an XOR circuit  52   b . The Gray code bit g 1 X and the error signal er 2  are input to a NAND circuit  50   d , and an output signal of the NAND circuit  50   d  is input to the XOR circuit  52   b . An output signal of the XOR circuit  52   b  is inverted by an inverter circuit  49   c  and output as a binary code bit B 3 Z. The NAND circuits  50   c  and  50   d  output binary code bits for production of the binary code bit B 3 Z whose error is corrected. 
     The binary code bit g 2   a  produced by the third encoding operation  43  is input to an XOR circuit  52   c , and the error signal er 2  is inverted by an inverter circuit  49   d  and input to the XOR circuit  52   c . An output signal of the XOR circuit  52   c  is inverted by an inverter circuit  49   f  and is output as a binary code bit B 2 Z and also input to an XOR circuit  52   e . The Gray code bit g 1  is input to an XOR circuit  52   d  while the error signal er 1  is inverted by an inverter circuit  49   e  and input to the XOR circuit  52   d . An output signal of the XOR circuit  52   d  is inverted by an inverter circuit  49   g  and input to the XOR circuit  52   e . A binary code bit B 1 Z is output from the XOR circuit  52   e . Output signals of the inverter circuits  49   f  and  49   g  output binary code bits for production of the binary code bit B 1 Z. 
     The Gray code bits g 0   a  and g 0   b  produced by the first encoding section  41  are input to a NAND circuit  50   e , and an output signal of the NAND circuit  50   e  is input to an XOR circuit  52   g . The binary code bit g 2   a  and the Gray code bit g 1  are input to an XOR circuit  52   f , and an output signal of the XOR circuit  52   f  is inverted by an inverter circuit  49   h  and input to the XOR circuit  52   g . A binary code bit B 0 Z is output from the XOR circuit  52   g . The NAND circuit  50   e  and the inverter circuit  49   h  output binary code bits for production of the binary code bit B 0 Z. 
     A binary code bit B 0  is output based on the Gray code bits g 0   b , g 0   a , g 0 Xa, g 0 Xb and g 1  and the binary code bit g 2   a  by logical processing of inverter circuits  49   i  and  49   j  using NOR circuits  51   d  to  51   i  and a NAND circuit  50   f . Even if signals produced by the first to third encoding sections  41  to  43  include an error originating from a babble error, the error is not corrected with the binary code bit B 0 . 
     Operation of the encoder according to the second embodiment will now be described. Similar to in the operation of the first to fourth encoding sections  11  to  14  of the first embodiment, if a thermometer code e 1  to e 31  which includes a babble error of the type b 2 H, as shown in FIG. 42, is input, then the first to fourth encoder sections  41  to  44  output signals the same as those when a thermometer code including a babble error of the type b 1  shown in FIG. 41 is input. However, if a thermometer code e 1  to e 31  which includes a babble error of the b 2 L type as shown in FIG. 43, then the first to fourth encoder sections  41  to  44  output signals whose error has been corrected completely. On the other hand, if a thermometer code e 1  to e 31  which includes a babble error of the type b 1  as shown in FIG. 41, then the first to fourth encoder sections  41  to  44  output signals which include the error. 
     The error signal production section  45  produces error signals er 1  and er 2  similar to those produced by the error signal production section  15  of the first embodiment. 
     The Gray to binary conversion section  46  produces a binary code by logical processing of the NOR circuits  51   a  and  51   b  and the NAND circuit  50   b  based on logical boundary detection signals gf, ge, gh and gg. As shown in FIG. 40, since the error signal er 2  exhibits an L level if the thermometer code e 1  to e 31  input includes no babble error, the output signal of the NAND circuit  50   a  exhibits an H level. Consequently, a signal having a same phase as that of an output signal of the NAND circuit  50   b  is output as the binary code bit B 4 Z. 
     However, as shown in FIGS. 38 and 41, if the error signal er 2  exhibits an H level and the Gray code bit g 2  exhibits an L level while the Gray code bit g 1 X exhibits an H level, then the output signal of the NAND circuit  50   b  is inverted and output as the binary code bit B 4 Z. When the Gray code bits g 2  and g 1 X and the error signal er 2  have any other conditions than those described above, a signal having a phase same as that of the output signal of the NAND circuit  50   b  is output as the binary code bit B 4 Z. 
     A binary code is produced by logical processing of the NOR circuits  51   b  and  51   c  and the NAND circuit  50   c  based on the logical boundary detection signals gh, gg, gd and gc, and if the error signal er 2  has an L level, then a signal having a phase same as that of the output signal of the NAND circuit  50   c  is output as the binary code bit B 3 Z. 
     However, as shown in FIGS. 38 and 41, if the error signal er 2  and the Gray code bit g 1 X both exhibit H levels, then the output signal of the NAND circuit  50   c  is inverted and output as the binary code bit B 3 Z. 
     The binary code bit B 2 Z is output as a signal having a same phase as that of the binary code bit g 2   a  when the error signal er 2  has an L level, but when the error signal er 2  has an H level, an inverted signal of the binary code bit g 2   a  is output. 
     The binary code bit B 1 Z is an inverted signal of the Gray code bit b 1  when the binary code bit B 2 Z has an H level and the error signal er 1  has an L level, but when the error signal er 1  has an L level, the binary code bit B 1 Z is a signal having a phase same as that of the Gray code bit g 1 . On the other hand, when the binary code bit B 2 Z has an L level and the error signal er 1  has an L level, the binary code bit B 1 Z is a signal having a phase same as that of the Gray code bit g 1 , but when the error signal er 1  has an H level, the binary code bit B 1 Z is an inverted signal of the Gray code bit g 1 . 
     The binary code bit B 0 Z has an H level if the Gray code bits g 0   a  and g 0   b  both have H levels while both of the Gray code bit g 1  and the binary code bit g 2   a  have H levels or L levels but has an L level if at least one of the Gray code bits g 0   a  and g 0   b  has an L level. 
     When one of the Gray code bit g 1  and the binary code bit g 2   a  has an H level and the other has an L level, if the Gray code bits g 0   a  and g 0   b  both have H levels, then the binary code bit B 0 Z has an L level, but if at least one of the Gray code bits g 0   a  and g 0   b  has an L level, then the binary code bit B 0 Z has an H level. 
     By such operation, even if the thermometer code e 1  to e 31  includes a babble error, binary code bits B 0 Z to B 4 Z in which the error has been corrected are output as shown in FIGS. 40 to  43 . 
     A precharge circuit  53  shown in FIG. 44 is connected to bit lines BL 1  and BL 1 X and bit lines BL 2   a  and BL 2   b  of the second and third encoding sections  42  and  43 . The precharge circuit  53  includes N-channel MOS transistors  54  to  57  in addition to the precharge circuit  36 . The drain and the gate of the transistor  54  are connected to the bit line BL 1  while the drain and the gate of the transistor  56  are connected to the bit line BL 1 X. The source of the transistor  57  is connected to the bit line BL 1  while the source of the transistor  55  is connected to the bit line BL 1 X. The sources of the transistors  54  and  56  and the drains of the transistors  55  and  57  are connected to each other and connected also to the gates of the transistors  55  and  57 . 
     In the precharge circuit  53 , when an H level is provided to the bit line BL 1  and an L level is provided to the bit line BL 1 X, then the transistors  54  and  55  are turned on while the transistor  56  and  57  are turned off. In this instance, since the drains and the gates of the transistors  54  and  55  are connected to each other, the transistors  54  and  55  operate as diodes, and the potential difference between the bit lines BL 1  and BL 1 X is clamped to a threshold value of the transistors  54  and  55 . 
     On the other hand, if the bit line BL 1  has an L level and the bit line BL 1 X has an H level, then the transistors  54  and  55  are turned off while the transistors  56  and  57  are turned on. In this instance, since the drains and the gates of the transistor  56  and  57  are connected to each other, the transistor  56  and  57  operate as diodes, and the potential difference between the bit lines BL 1  and BL 1 X is clamped to the threshold value of the transistor  56  and  57 . The precharge circuit  53  may be used also as a precharge circuit for the bit lines of the second and third encoding sections  12  and  13  of the first embodiment of the present invention. 
     The second embodiment of the encoder achieves, in addition to the effects achieved by the encoder of the first embodiment, the following effects: 
     (1) Binary code bits B 0 Z to B 4 Z are produced in parallel to error correction based on signals produced by the first to fourth encoding sections  41  to  44  without producing correction Gray code bits G 0 Z to G 4 Z which are produced in the first embodiment. Accordingly, since the binary code bits B 0 Z to B 4 Z are produced without the necessity for such a Gray to binary conversion section  17 , as shown in FIG. 25, the circuit scale is reduced; 
     (2) While, in the Gray to binary conversion section  17  shown in FIG. 25, the number of stages of logic circuits increases toward the lower bit side of the binary code bits B 0 Z to B 4 Z to decrease the outputting speed and the operation speed of the encoder is determined by the outputting speed of the least significant bit, in the second embodiment, since the binary code bits B 0 Z to B 4 Z are produced without using the Gray to binary conversion section  17 , the operation speed of the encoder is increased; 
     (3) The Gray to binary conversion section  46  produces binary code bits B 0 Z to B 4 Z based on three or less decomposed Gray code bits and decomposed binary code bits from a decomposed Gray code and a decomposed binary code produced by the first to fourth encoding sections  41  to  44 . Accordingly, since lower order binary code bits are produced in parallel to production of upper order binary code bits, the operation speed of the encoder is increased; and 
     (4) Since the amplitude of a bit line precharged by the precharge circuit  53  is clamped to a value equal to or lower than a threshold value of two N-channel MOS transistors, the lowering speed of the bit line potential by a ROM cell is improved. Accordingly, the operation speed of the encoder is improved. 
     The clamp level of each bit line is adjusted by varying the number of stages of N-channel MOS transistors to be connected in diode connection. Further, PN junction diodes may be used in place of the N-channel MOS transistors. 
     (Third Embodiment) 
     The third embodiment is constructed such that the error correction operation of the first embodiment is performed using a computer which operates in accordance with a program, and is described as an encoder which produces digital signals bit B 0 Z to B 3 Z of a binary code of 3 bits for convenience of description. 
     FIG. 45 shows an outline of the encoder of the third embodiment. A thermometer code e 1  to e 7  is input to an encoding section  61 . The encoding section  61  produces and outputs digital signals G 0  to G 2  of a Gray code of 3 bits based on the thermometer code e 1  to e 7 . The encoding section  61  is a modification, for example, to the encoder shown in FIGS. 5 or  7  such that it has a 3-bit construction, and does not have the function of correcting a babble error included in the thermometer code e 1  to e 7 . 
     The Gray code bits G 0  to G 3  output from the encoding section  61  is input to an arithmetic processing section  62  in the form of a computer. A program storage section  63  in which a processing program is stored is connected to the arithmetic processing section  62 . 
     The arithmetic processing section  62  operates in accordance with the processing program and operates to: decompose lower order bits of the Gray code bits G 0  to G 2 ; determine whether or not the decomposed lower order bits and the upper order bits have a particular relationship to detect whether or not the Gray code bits produced have some error; correct the detected error; and convert the corrected Gray code to digital signals B 0  to B 2  of a binary code. 
     The arithmetic processing section  62  performs error correction operation by one of the following first to third operations in accordance with the program stored in the program storage section  63 . 
     &lt;First Operation&gt; 
     FIGS. 46 to  48  illustrate a first operation of the arithmetic processing section  62 . When a Gray code G 0  to G 2  is input from the encoding section  61  to the arithmetic processing section  62 , the arithmetic processing section  62  decomposes the Gray code bit G 0  of the lowest order into decomposed Gray codes g 0   a  and g 0   b  of a front code similar to that in the first embodiment (step  1 ). 
     In the program storage section  63 , codes when the Gray code bit G 0  of the lowest order of a normal Gray code bit G 0  to G 2  is decomposed into decomposed Gray code bits g 0   a  and g 0   b  and binary codes corresponding to the Gray codes are stored in advance as shown in FIG.  47 . 
     When the decomposed Gray code bit g 0   b  is “1” in FIG. 47, the Gray code bit G 2  is “0” without fail, but when the decomposed Gray code bit g 0   a  is “1”, the Gray code bit G 2  is “1” without fail. Consequently, presence or absence of an error is detected depending upon whether or not the conditions are satisfied. 
     If a normal Gray code G 0  to G 2  is input, decomposed Gray code bits g 0   a  and g 0   b  and Gray code bits G 1  and G 2  in a normal case illustrated in FIG. 48 are obtained. Then, the arithmetic processing section  62  produces error signals based on the decomposed Gray code bits g 0   a  and g 0   b  and the Gray code bit G 2  (step  2 ). In the error signal production processing, error signals Ea and Eb are calculated in accordance with the following expressions: 
     
       
           Ea=g 0 a×/G 2 
       
     
     
       
           Eb=G 0 b×G 2 
       
     
     where x denotes logical ANDing. 
     In particular, the error signal Ea “1” is generated by logically ANDing the decomposed Gray code bit g 0   a  “1” and the Gray code bit /G 2  “1”, and the error signal Eb “1” is generated by logically ANDing the decomposed Gray code bit g 0   b  “1” and the Gray code bit G 2  “0”. Then, if the Gray code bits obtained are normal, then the error signals Ea and Eb are both “0”, but if an error is present, then one of the error signals Ea and Eb exhibits “1”. 
     Thereafter, the arithmetic processing section  62  discriminates whether or not at least one of the error signals Ea and Eb is “1” to discriminate presence or absence of an error (step  3 ). 
     If both of the error signals Ea and Eb are “0” and it is discriminated that there is no error, then the arithmetic processing section  62  determines the input Gray code G 0  to G 2  as a correction Gray code g 0 Z to g 2 Z (step  4 ). 
     Then, the arithmetic processing section  62  performs Gray to binary conversion of the correction Gray code g 0 Z to g 2 Z to produce a correction binary code B 0 Z to B 2 Z (step  5 ) and ends its error correction processing. This Gray to binary conversion is performed by the arithmetic processing section  62  performing the logical processing which is performed by the logic circuit shown in FIG. 25 in the first embodiment of the present invention. 
     On the other hand, if it is discriminated in step  3  that at least one of the error signals Ea and Eb is “1” and there is an error, then the arithmetic processing section  62  performs correction of the error bit (step  6 ). 
     In this correction operation, processing represented by the following expressions is performed for the decomposed Gray code bits g 0   a , g 0   b  and G 2  with which the error signal Ea or Eb is “1” as shown in FIG. 48 to produce correction Gray code bits g 0 Z and g 2 Z: 
     
       
           g 2 Z= ( Ea+Eb )@ G 2 
       
     
     
       
           g 0 Z= ( Ea+Eb )@( g 0 a+g 0 b ) 
       
     
     where + represents logical ORing and @ represents logical exclusive ORing. 
     In particular, if at least one of the error signals Ea and Eb is “1”, then Gray code bit G 2  is inverted to produce the correction Gray code bit g 2 Z, and the decomposed Gray code g 0   a  or g 0   b  which exhibits “1” is inverted to produce the correction Gray code bit g 0 Z. In other words, any bit which is discriminated to be an error is inverted to produce correction Gray code bits g 0 Z and g 2 Z. 
     Then, the Gray code bit G 1  is determined as it is as the correction Gray code bit g 1 Z, thereby completing production of the correction Gray code g 0 Z to g 2 Z, and then Gray to binary conversion is performed to produce a binary code B 0 Z to B 2 Z (steps  4  and  5 ). 
     By such operations, the binary code bits B 0 Z to B 2 Z have values more likely than those of the non-corrected binary code bits B 0  to B 2  which are produced based on the non-corrected Gray code bits G 0  to G 2 . 
     &lt;Second Operation&gt; 
     FIGS. 49 to  51  illustrate second operation of the arithmetic processing section  62 . When a Gray code G 0  to G 2  is input from the encoding section  61  to the arithmetic processing section  62 , the arithmetic processing section  62  decomposes the Gray code bit G 0  of the lowest order into decomposed Gray code bits g 0 Xa and g 0 Xb of a back code similar to that in the first embodiment (step  11 ). 
     In the program storage section  63 , codes when the Gray code bit G 0  of the lowest order of each of normal Gray code bits G 0  to G 2  is decomposed into decomposed Gray codes g 0 Xa and g 0 Xb and binary codes corresponding to the Gray codes are stored in advance as shown in FIG.  50 . 
     When the decomposed Gray code bit g 0 Xa is “1” in FIG. 50, the Gray code bit G 1  is “0” without fail, and when the decomposed Gray code bit g 0 Xb is “1”, the Gray code bit G 1  is “1” without fail. Consequently, presence or absence of an error is detected depending upon whether or not the conditions thus described are satisfied. 
     If the Gray code G 0  to G 2  input is normal, then decomposed Gray code bits g 0 Xa and g 0 Xb and Gray code bits G 1  and G 2  in an ordinary case illustrated in FIG. 51 are obtained. 
     Then, the arithmetic processing section  62  performs production processing for an error signal based on the decomposed Gray code bits g 0 Xa and g 0 Xb and the Gray code bit G 1  (step  12 ). In this error signal production processing, error signals EXa and EXb are calculated in accordance with the following expressions: 
     
       
         
           EXa=g 
           0 
           Xa×G 
           1 
         
       
     
     
       
         
           EXb=g 
           0 
           Xb×/G 
           1 
         
       
     
     where x represents logical ANDing. 
     In particular, the error signal EXa “1” is generated by logically ANDing the decomposed Gray code bit g 0 Xa “1” and the Gray code bit G 1  “1” while the error signal EXb “1” is generated by logically ANDing the decomposed Gray code bit g 0 Xb “1” and the Gray code bit /G 1  “1”. If both of the Gray code bits are normal, then the error signals EXa and EXb both exhibit “0”, but if an error is present, then one of the error signal EXa and EXb exhibits “1”. 
     Then, the arithmetic processing section  62  discriminates whether or not at least one of the error signals EXa and EXb is “1” to discriminate presence or absence of an error (step  13 ). 
     If both of the error signals EXa and EXb are “0” and it is discriminated that there is no error, then the arithmetic processing section  62  determines the Gray code bits G 0  to G 2  as correction Gray code bits G 0 Z to g 2 Z (step  14 ). 
     Thereafter, the arithmetic processing section  62  performs Gray to binary conversion of the correction Gray code bits g 0 Z to g 2 Z to produce binary code bits B 0 Z to B 2 Z (step  15 ), thereby ending the error correction processing. 
     On the other hand, if it is discriminated in step  13  that at least one of the error signals EXa and EXb is “1” and there is an error, then the arithmetic processing section  62  performs correction of the error bit (step  16 ). 
     In this correction processing, processing represented by the following expressions is performed for the decomposed Gray code bits g 0 Xa, g 0 Xb and G 1  with which the error signal EX 1  or EXb is “1” to produce correction Gray code bits g 0   z  and g 1 Z as shown in FIG.  51 . 
     
       
           g 1 Z= ( EXa+EXb )@ G 1 
       
     
     
       
           g 0 Z=/[ ( EXa+EXb )@( g 0 Xa+g 0 Xb )] 
       
     
     where + represents logical ORing, @ represents logical exclusive ORing, and/(bar) represents logical inversion. 
     In particular, if at least one of the error signals EXa and EXb is “1”, then the Gray code bit G 1  is inverted to produce the correction Gray code bit g 1 Z, and the decomposed Gray code bit g 0 Xa or g 0 Xb which is “1” is inverted to produce the correction Gray code bit g 0 Z. In other words, any bit which is an error is inverted to produce correction Gray code bits g 0 Z and g 1 Z. Then, the Gray code bit G 2  is determined as it is as a correction Gray code bit g 2 Z, thereby completing production of the correction Gray code g 0 Z to g 2 Z, and Gray to binary conversion is performed to produce the binary code B 0 Z to B 2 Z (steps  14  and  15 ). 
     By such operation, as shown from FIG. 51, the binary code bits B 0 Z to B 2 Z have values more likely than those of the non-corrected binary code bits B 0  to B 2  which are produced based on the non-corrected Gray code bits G 0  to G 2 . 
     &lt;Third Operation&gt; 
     FIGS. 52 to  54  illustrate third operation of the arithmetic processing section  62 . When a Gray code G 0  to G 2  is input from the encoding section  61  to the arithmetic processing section  62 , the arithmetic processing section  62  decomposes the Gray code bit G 0  of the lowest order into decomposed Gray code bits g 0   a  and g 0   b  of a front code and decomposed Gray code bits g 0 Xa and g 0 Xb of a back code similar to those in the first embodiment (step  21 ). 
     In the program storage section  63 , codes when the Gray code bit G 0  of the lowest order of each of normal Gray code bits G 0  to G 2  is decomposed into decomposed Gray code bits g 0   a , g 0   b , g 0 Xa and g 0 Xb and binary codes corresponding to the Gray codes are stored in advance as shown in FIG.  53 . 
     When the decomposed Gray code bit g 0   b  is “1” in FIG.  53 , the Gray code bit G 2  is “1” without fail, and when the decomposed Gray code bit g 0   a  is “1”, the Gray code bit G 2  is “1” without fail. Further, when the decomposed Gray code bit g 0 Xa is “1”, the Gray code bit G 1  is “0” without fail, and when the decomposed Gray code bit g 0 Xb is “1”, the Gray code bit G 1  is “1” without fail. Consequently, presence or absence of an error is detected depending upon whether or not those conditions are satisfied. 
     If a normal Gray code G 0  to G 2  is input, then decomposed Gray code bits g 0   a , g 0   b , g 0 Xa and g 0 Xb and Gray code bits G 1  and G 2  in a normal case illustrated in FIG. 54 are obtained. Then, the arithmetic processing section  62  produces an error signal based on the decomposed Gray codes g 0 Xa and g 0 Xb and the Gray code bits G 1  and G 2  (step  22 ). In this error signal production processing, error signals Er and ErX are calculated in accordance with the following expressions: 
     
       
           Er= ( g 0 a×/G 2)+( g 0 b×G 2=1) 
       
     
     
       
           ErX= ( g 0 Xa×G 1)+( g 0 Xb×/G 1) 
       
     
     where x represents logical ANDing, + represents logical ORing, and/(bar) represents logical inversion. 
     If all of the Gray code bits are normal, then both of the error signals Er and ErX exhibit “0”, but if an error is present, one of the error signals Er and ErX exhibits “1”. 
     Then, the arithmetic processing section  62  discriminates presence or absence of an error depending upon whether or not at least one of the error signals Er and ErX is “1” (step  23 ). 
     If it is discriminated that both of the error signals Er and ErX are “0” and there is no error, then the arithmetic processing section  62  determines the input Gray code G 0  to G 2  as a correction Gray code g 0 Z to g 2 Z (step  24 ). 
     Then, the arithmetic processing section  62  performs Gray to binary conversion of the correction Gray code g 0 Z to g 2 Z to produce a binary code B 0 Z to B 2 Z (step  25 ), thereby ending the error correction operation. 
     On the other hand, if it is discriminated in step  23  that at least one of the error signals Er and ErX is “1” and there is an error, then the arithmetic processing section  62  performs correction of the error bit (step  26 ). 
     In this correction operation, processing represented by the following expressions is performed for the decomposed Gray code bits g 0   a , g 0   b , g 0 Xa and g 0 Xb and the Gray code bits G 1  and G 2  with which the error signals Er and ErX are “1” to produce correction Gray code bits g 0 Z to g 2 Z as shown in FIG.  54 : 
     
       
           g 2 Z= /( Er@G 2) 
       
     
     
       
           g 1 Z= /( ErX@G 1) 
       
     
     
       
           g 0 Z= ( Er+ErX )@ ( g 0 a+g 0 b ) 
       
     
     where + represents logical ORing, @ represents logical exclusive ORing, and/(bar) represents logical inversion. 
     In particular, any bit which is an error is inverted to a produce correction Gray code bits g 0 Z to g 2 Z. 
     Thereafter, Gray to binary conversion is performed for the correction Gray code g 0 Z to g 2 Z to produce a correction binary code B 0 Z to B 2 Z (steps  24  and  25 ). By such operation, as shown in FIG. 54, the binary code bits B 0 Z to B 2 Z have values more likely than those of the non-corrected binary code bits B 0 Z to B 2 Z produced based on the non-corrected Gray code bits G 0  to G 2  and have values more likely than those of the non-corrected binary code bits B 0 Z to B 2 Z obtained by the first and second operations. 
     With the encoder, a binary code with a babble error included in an input thermometer code has been corrected at a high speed by the arithmetic processing section  62 , which operates in accordance with the program stored in the program storage section  63 . 
     FIG. 55 shows a semiconductor device for which a high speed performance test of a first example in accordance with the present invention is performed. A testing apparatus  201  outputs an original clock signal CLK and a control signal CNTL to a semiconductor device  202  which includes a high speed A/D converter  205 . The original clock signal CLK is a signal of approximately 50 MHZ which is produced sufficiently by the testing apparatus  201  which is similar to a conventional testing apparatus, and the control signal CNTL is produced as an analog signal whose voltage is gradually varied by a time constant circuit or the like provided in the testing apparatus  201 . 
     The original clock signal CLK is input to a PLL circuit  203  in the semiconductor device  202 . The PLL circuit  203  produces an internal clock signal CK of, for example, 200 MHZ based on the original clock signal CLK and outputs the internal clock signal CK to an analog signal production circuit  204   a , an A/D converter  205 , an interleave circuit  206  and other internal circuits (not shown). 
     The control signal CNTL is input to the analog signal production circuit  204   a . The analog signal production circuit  204   a  produces, is a performance test mode, an analog signal Ain, which has an equal frequency to but having a different phase from those of the internal clock signal CK, based on the internal clock signal CK and the control signal CNTL and outputs the analog signal Ain to the A/D converter  205 . 
     While the internal clock signal CK is output as a pulse signal of a rectangular wave from the PLL circuit  203 , actually it is input as a signal of a sine wave by an action of a parasitic capacitance or the like to the analog signal production circuit  204   a  and the A/D converter  205 , and the analog signal production circuit  204   a  outputs the analog signal Ain, which has a phase delayed relative to the internal clock signal CK. 
     A detailed construction of the analog signal production circuit  204   a  is shown in FIG.  56 . The internal clock signal CK is input to an inverter circuit  207   a , and an output signal of the inverter circuit  207   a  is input to another inverter circuit  207   b  through an N-channel MOS transistor  208 . The control signal CNTL is input to the gate of the transistor  208 , and an input terminal of the inverter circuit  207   b  is connected to the ground GND through a capacitor  209 . The analog signal Ain is output from the inverter circuit  207   b.    
     In the analog signal production circuit  204   a , if the voltage level of the control signal CNTL varies, then the on-resistance of the transistor  208  varies to vary the time constant of the transistor  208  and the capacitor  209 . Consequently, the phase difference between the internal clock signal CK and the analog signal Ain is varied by the variation of the control signal CNTL. The analog signal Ain is input to the A/D converter  205 . The A/D converter  205  operates using the internal clock signal CK as a sampling clock signal to sample the analog signal Ain output from the analog signal production circuit  204   a , converts the sampled analog value into a digital signal and outputs the digital signal to the interleave circuit  206 . Except when a performance test is performed, the A/D converter  205  converts another analog signal into a digital signal and outputs the digital signal to the internal circuit or an external circuit. 
     The interleave circuit  206  operates, in a performance test mode, to output a digital signal output from the A/D converter  205  at a rate of once per n times to the testing apparatus  201 . 
     When a performance test of the A/D converter  205  of the semiconductor device  202  is performed, the original clock signal CLK and the control signal CNTL are supplied from the testing apparatus  201  to the semiconductor device  202 . The phase difference between the internal clock signal CK and the analog signal varies as time passes. 
     As shown in FIG. 57, if the phase of the analog signal Ain is gradually displaced from an analog signal Ain 1  to another analog signal Ain 2  with respect to a sampling timing ST of the A/D converter  205  by the internal clock signal CK, then the analog level sampled gradually varies within the range of predetermined comparison reference voltages V RH  to V RL  of the A/D converter  205 . As a result, the analog value sampled by the A/D converter  205  successively varies within the range of the reference voltages V RH  to V RL , and the analog value is converted into a digital value and output to the testing apparatus  201  through the interleave circuit  206 . The testing apparatus  201  detects whether or not the digital value of the digital signal output from the interleave circuit  206  successively varies to detect whether or not the A/D converter  205  is operating normally. 
     With the semiconductor device  202 , the following effects are achieved: 
     (1) Since an analog signal need not be supplied from the testing apparatus  201  to the semiconductor device  202 , a performance test of the A/D converter  205  installed in the semiconductor device  202  is performed with certainty irrespective of the operation speed of the testing apparatus  201 ; 
     (2) Based on the original clock signal CLK supplied from the testing apparatus  201 , the internal clock signal CK of a high frequency is produced in the semiconductor device  202 , and the analog signal Ain having a frequency equal to that of the internal clock signal CK is produced readily by the analog signal production circuit  204   a  based on the internal clock signal CK; 
     (3) The analog signal Ain is produced by the analog signal production circuit  204   a  successively displacing the phase of the internal clock signal CK, and by inputting the analog signal Ain to the A/D converter  205  to sample the internal clock signal CK, so that the sampled analog value is varied finely. Accordingly, by evaluating the digital value obtained by A/D conversion of the analog value, a performance test of the A/D converter  205  is performed with certainty; and 
     (4) Since the digital output signal of the A/D converter  205  which operates at a high speed is output to the testing apparatus  201  through the interleave circuit  206  at a predetermined rate, even the testing apparatus  201  having an operation speed lower than that of the A/D converter  205  fetches and evaluates the digital output signal of the A/D converter  205  with certainty. 
     Where the analog signal Ain has a frequency equal to that of the internal clock signal CK, the internal clock signal CK should be divided by two by a divider and input to the analog signal production circuit  204   a.    
     Further, the PLL circuit  203  may be provided in the testing apparatus  201  such that the internal clock signal CK may be supplied from the testing apparatus  201  to the analog signal production circuit  204   a.    
     The internal clock signal CK may alternatively be input as an analog signal to the A/D converter  205  while the output signal of the analog signal production circuit  204   a  is input as a sampling clock signal to the A/D converter  205 . In this instance, the analog signal production circuit  204   a  operates as a clock signal production circuit. 
     (Second Example) 
     In place of the analog signal production circuit  204   a  installed in the semiconductor device  202  of the first example, an analog signal production circuit  204   b  shown in FIG. 58 may be installed, in which the internal clock signal CK is input to an inverter circuit  210 , and an output signal of the inverter circuit  210  is output as an analog signal Ain through a capacitor  211 . 
     An output side terminal of the capacitor  211  is connected to a power supply V DD  through a P-channel MOS transistor  212  and is connected to the ground GND through a current source  213 . The control signal CNTL is input to the gate of the transistor  212 . 
     From such an analog signal production circuit  204   b , an analog signal Ain of a frequency equal to that of the internal clock signal CK is output based on an input of the internal clock signal CK. 
     In this instance, if the voltage level of the control signal CNTL rises, then since drain current of the transistor  212  decreases, the DC level of the analog signal Ain drops. However, if the voltage level of the control signal CNTL drops, then the drain current of the transistor  212  increases. Consequently, the DC level of the analog signal Ain rises. 
     When a performance test of the A/D converter  205  of the semiconductor device  202  which includes such an analog signal production circuit  204   b  is performed, the original clock signal CLK and the control signal CNTL are supplied from the testing apparatus  201  to the semiconductor device  202 . The control signal CNTL is a signal whose voltage level varies as time passes in a similar manner as in the first example. 
     As shown in FIG. 59, the DC level of the analog signal Ain varies as time passes. Then, if the DC level of the analog signal Ain is displaced gradually from an analog signal Ain 3  to another analog signal Ain 4  with respect to a sampling timing ST of the A/D converter  205  by the internal clock signal CK, then the analog level sampled gradually varies within the range of predetermined comparison reference voltages V RH  to V RL  of the A/D converter  205 . As a result, the analog value sampled by the A/D converter  205  gradually varies within the range of the reference voltages V RH  to V RL , and the analog value is converted into a digital signal and output to the testing apparatus  201  through the interleave circuit  206 . The testing apparatus  201  detects whether or not the digital value of the digital signal output from the interleave circuit  206  successively varies to determinate whether or not the A/D converter  205  is operating normally. 
     With such a semiconductor device  202 , the following effect is achieved in addition to the effects (1), (2) and (4) achieved by the first example. 
     In particular, by successively displacing the DC level of the internal clock signal CK by means of the analog signal production circuit  204   b  to produce an analog signal Ain and inputting the analog signal Ain to the A/D converter  205  so that the analog signal Ain is sampled with the internal clock signal CK, the sampled analog value is varied finely. Accordingly, by evaluating the digital signal obtained by A/D conversion of the analog value, a performance test of the A/D converter  205  is performed with certainty. 
     The analog value to be sampled may be varied finely by varying the amplitude of the analog signal. Further, the DC level of the analog signal may be fixed while the DC level or the amplitude of the sampling clock signal may be varied. 
     Further, a construction wherein the output signal of the analog signal production circuit  204   b  is input as the clock signal CLK to the A/D converter  205  and the internal clock signal CK is input as an analog signal to the A/D converter  205  example may be employed alternatively. 
     (Second Embodiment) 
     FIG. 60 shows a second embodiment of a semiconductor device  22  in accordance with the present invention. The second embodiment produces the analog signal Ain to be input to the A/D converter  205  not by varying the phase or the DC level of the internal clock signal CK, but by varying the comparison reference voltage for the A/D converter  205 . 
     As shown in FIG. 60, the control signal CNTL output from the testing apparatus  201  is input to a comparison reference voltage production circuit  214 . The comparison reference voltage production circuit  214  varies, in response the control signal CNTL, comparison reference voltages to be supplied to the A/D converter  205  moderately within the ranges of V RH1  and V RL1  to V RH2  and V RL2  illustrated in FIG.  61 . 
     The internal clock signal CK output from the PLL circuit  203  is input as a sampling clock signal and also as the analog signal Ain to the A/D converter  205 . 
     In order to perform a performance test of the A/D converter  205  of the semiconductor device  202  which includes the comparison reference voltage production circuit  214 , the original clock signal CLK and the control signal CNTL are supplied from the testing apparatus  201  to the semiconductor device  202 . 
     As shown in FIG. 61, the comparison reference voltages to be supplied vary within the ranges of V RH1  and V RL1  to V RH2  to V RL2  as time passes. If the comparison reference voltages are displaced moderately from a sampling timing ST of the A/D converter  205  by the internal clock signal CK, then the comparison reference voltages vary moderately with respect to the analog level to be sampled. As a result, the comparison reference voltages successively vary within the ranges of V RH1  and V RL1  to V RH2  and V RL2  with respect to the analog value sampled by the A/D converter  205 , and the analog value is converted into a digital signal and output to the testing apparatus  201  through the interleave circuit  206 . The testing apparatus  201  detects whether or not the digital value of the digital signal output from the interleave circuit  206  successively varies to determinate whether or not the A/D converter  205  is operating normally. 
     In the semiconductor device  202 , the following effect is achieved, in addition to the effects (1), (2) and (4) achieved by the first example. 
     In particular, since the comparison reference voltage production circuit  214  successively displaces and inputs the comparison reference voltages to the A/D converter  205  so that the comparison reference voltages and an analog value obtained by sampling of the analog signal Ain are compared with each other, the comparison reference voltages are varied finely with respect to the analog value to be sampled. Accordingly, by evaluating a digital signal obtained by A/D conversion of the analog value, a performance test of the A/D converter  205  is performed with certainty. 
     (Third Embodiment) 
     FIGS. 62 and 63 show a third embodiment of a semiconductor device in accordance with the present invention. The third embodiment includes an output determination circuit  215  and a control signal production circuit  216  in addition to the first example so that it has a self diagnosis circuit which performs self diagnosis of operation of the A/D converter  205 . 
     The analog signal production circuit  204   a  delays the phase of the internal clock signal CK in response to the control signal CNTL to obtain an analog signal Ain and outputs the analog signal Ain to the A/D converter  205 . 
     An output signal of the interleave circuit  206  is input to the output determination circuit  215 . The output determination circuit  215  comprises a magnitude comparator and successively compares a digital signal successively input thereto from the interleave circuit  206 . Thus, for example, if a digital value input later is higher, that is, when the digital signal exhibits a monotonous increase, the output determination circuit  215  outputs an L level, but if the digital value input later is lower, that is, when the digital value does not exhibit a monotonous increase, the output determination circuit  215  outputs an H level. 
     An output signal of the output determination circuit  215  is input to the control signal production circuit  216 . A detailed construction of the control signal production circuit  216  is described with reference to FIG.  63 . 
     An input signal IN is input to an inverter circuit  217 , and an output signal of the inverter circuit  217  is output as the control signal CNTL to the analog signal production circuit  204   a  through a resistor  218 . An output side terminal of the resistor  218  is connected to the ground GND through a capacitor  219 . The time constant set by the resistor  218  and the capacitor  219  is sufficiently large with respect to an output signal frequency of the interleave circuit  206 . 
     Thus, if the input signal IN has an L level, then the control signal production circuit  216  gradually raises the voltage level of the control signal CNTL, but if the input signal IN has an H level, then the control signal production circuit  216  gradually lowers the voltage level of the control signal CNTL. 
     In the self diagnosis circuit, when the internal clock signal CK is supplied to the analog signal production circuit  204   a , A/D converter  205  and interleave circuit  206  to start a performance test of the A/D converter  205 , if the digital value of the digital signal output from the interleave circuit  206  increases, then the voltage level of the control signal CNTL rises. Consequently, the phase of the analog signal Ain advances and the analog value to be sampled becomes larger, and the digital value of the digital signal to be output from the A/D converter  205  increases. As a result, the output signal of the output determination circuit  215  is maintained at an L level while the output signal of the inverter circuit  217  of the output determination circuit  215  is maintained at an H level, and the voltage level of the control signal CNTL to be output from the control signal production circuit  216  further rises. 
     By such operation, a positive feedback loop is formed by the analog signal production circuit  204   a , A/D converter  205 , interleave circuit  206 , output determination circuit  215  and control signal production circuit  216 , and if the monotony of the A/D converter  205  is normal, then the digital signal output from the A/D converter  205  rises up to its maximum value. 
     However, if the monotony of the A/D converter  205  is abnormal, then operation of the positive feedback loop stops at a time when a malfunction occurs stops and the rise of the voltage level of the control signal CNTL stops, and consequently, the rise of the digital signal output from the A/D converter  205  stops without reaching the maximum value. 
     Accordingly, by confirming, after a predetermined time passes after starting of a performance test, whether or not the maximum value of the digital signal output from the A/D converter  205  is reached, it is detected whether or not the A/D converter  205  is normal. 
     Further, such an A/D converter  205  is constructed such that it converts an analog signal Ain once into a digital signal of a Gray code and then converts the digital signal of the Gray code into a digital signal of a binary code. From the characteristic of the Gray code, when the digital value successively varies by “1”, the Gray code varies at only one bit thereof. Making use of this characteristic, the output determination circuit  215  may includes a logic circuit for logically exclusively ORing output signals of is individual bits of two successive cycles from among digital signals of successive cycles of the Gray code, the monotony of the output signal of the A/D converter  205  is determinated. 
     Further, in the present example, the positive feedback loop may alternatively be formed using the analog signal production circuit  204   b  of the second example or the comparison reference voltage production circuit  214  of the second embodiment of the semiconductor device. 
     It should be apparent to those skilled in the art that the present invention may be embodied in many other specific forms without departing from the spirit or scope of the invention. Moreover, although the invention is shown as generating a 5-bit binary code, it will be understood that the disclosed embodiment may be modified to generate binary codes having a different number of bits Therefore, the present examples and embodiments are to be considered as illustrative and not restrictive and the invention is not to be limited to the details give herein, but may be modified without the scope and equivalence of the appended claims.