Patent Publication Number: US-2017358462-A1

Title: Manufacturing  method of semiconductor  package

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2016-118251 filed on Jun. 14, 2016, the entire contents of which are incorporated herein by reference. 
     FIELD 
     The present invention relates to a manufacturing method of a semiconductor device, and specifically, to a technology for mounting a semiconductor device on a substrate. 
     BACKGROUND 
     Conventionally, an electronic device such as a mobile phone, a smartphone or the like includes a semiconductor package structure including a support substrate and a semiconductor device such as an IC chip or the like mounted thereon (see, for example, Japanese Laid-Open Patent Publication No. 2010-278334). Generally in such a semiconductor package, a semiconductor device such as an IC chip, a memory or the like is bonded on a support substrate with an adhesive layer being provided therebetween, and the semiconductor device is covered with a sealing member (formed of a resin material for sealing), so that the semiconductor device is protected. 
     The support substrate used for such a semiconductor device may be any of various substrates including a printed substrate, a ceramic substrate and the like. Especially recently, a semiconductor package including a metal substrate has been progressively developed. A semiconductor package including a metal substrate and a semiconductor device mounted thereon and fanned out by re-wiring has an advantage of being superb in electromagnetic shielding characteristics and thermal characteristics and now is a target of attention as a highly reliable semiconductor package. Such a semiconductor package also has an advantage of having a high degree of designing freedom. 
     In the case of a structure including a support substrate and a semiconductor device mounted thereon, a plurality of semiconductor devices may be mounted on a large support substrate, so that a plurality of semiconductor packages may be manufactured in one manufacturing process. In this case, the plurality of semiconductor packages formed on the support substrate are separated into individual pieces after the manufacturing process is finished, and thus individual semiconductor packages are provided. As can be seen from this, the semiconductor package structure including a support substrate and a semiconductor package mounted thereon also has an advantage of being high in mass-productivity. 
     The mass production using a large metal support substrate as a support substrate as described above requires high alignment precision of the semiconductor devices with respect to the metal substrate, good contact between the semiconductor devices and lines, high yield separation into individual semiconductor packages, or the like. 
     SUMMARY 
     A manufacturing method of a semiconductor package in an embodiment according to the present invention includes disposing one or more semiconductor devices on a base substrate, each of the one or more semiconductor devices having an external terminal; forming a frame on the base substrate, the frame surrounding the one or more semiconductor devices; and forming a resin insulating layer sealing the one or more semiconductor devices, the resin insulating layer including a resin insulating material; wherein a surface of each of the one or more semiconductor devices on which the external terminal is not provided faces the base substrate. 
     The manufacturing method of a semiconductor package in an embodiment according to the present invention may include forming one or more alignment markers on the base substrate before disposing the one or more semiconductor devices; and separating each of the one or more semiconductor devices after forming the resin insulating layer, wherein each of the one or more semiconductor devices are disposed based on corresponding an alignment marker; the frame is formed outside the alignment marker; and separating each of the one or more semiconductor devices includes cutting the base substrate and the resin insulating layer between the frame and the alignment marker corresponding each of the one or more semiconductor devices. 
     The manufacturing method of a semiconductor package in an embodiment according to the present invention may include etching surfaces of the base substrate excluding the surface on which the semiconductor device is disposed, and precipitating a metal on the etched surface of the base substrate before forming the frame on the base substrate; and forming a first conductive layer on the resin insulating layer, forming an opening in the resin insulating layer and the first conductive layer, and forming a plating layer on surfaces of the base substrate and the first conductive layer, and in the opening after forming the resin insulating layer, the surfaces of the base substrate including side surfaces and a surface on which the semiconductor device is not disposed; wherein the opening exposes the external terminal. 
     In the manufacturing method of a semiconductor package in an embodiment according to the present invention, disposing the one or more semiconductor devices may include disposing a plurality of semiconductor devices on the base substrate; and the frame may surround each of the plurality of semiconductor devices. 
     In the manufacturing method of a semiconductor package in an embodiment according to the present invention, disposing the one or more semiconductor devices may include disposing a plurality of semiconductor devices on the base substrate; and the frame may surround the plurality of semiconductor devices. 
     In the manufacturing method of a semiconductor package in an embodiment according to the present invention, forming the resin insulating layer may include pouring a solution, in which the resin insulating material is dissolved, into the inside of the frame; and heat-treating the solution. 
     In the manufacturing method of a semiconductor package in an embodiment according to the present invention, the thickness of the frame may be thicker or thinner than the thickness of the semiconductor device. 
     In the manufacturing method of a semiconductor package in an embodiment according to the present invention, the frame may include epoxy resin. 
    
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         FIG. 1  is a schematic cross-sectional view of a semiconductor package in an embodiment according to the present invention; 
         FIG. 2  shows a step of forming alignment markers in a support substrate in a manufacturing method of the semiconductor package in an embodiment according to the present invention; 
         FIG. 3  shows a step of forming an adhesive layer on the support substrate in the manufacturing method of the semiconductor package in an embodiment according to the present invention; 
         FIG. 4  shows a step of roughening a bottom surface and a side surface of the support substrate in the manufacturing method of the semiconductor package in an embodiment according to the present invention; 
         FIG. 5  shows a step of partially removing the adhesive layer in the manufacturing method of the semiconductor package in an embodiment according to the present invention; 
         FIG. 6  shows a step of locating a semiconductor device on the support substrate in the manufacturing method of the semiconductor package in an embodiment according to the present invention; 
         FIG. 7  shows a step of forming a frame on the support substrate in the manufacturing method of the semiconductor package in an embodiment according to the present invention; 
         FIG. 8  shows a step of forming a frame on the support substrate in the manufacturing method of the semiconductor package in an embodiment according to the present invention; 
         FIG. 9  shows a step of forming a first resin insulating layer in the manufacturing method of the semiconductor package in an embodiment according to the present invention; 
         FIG. 10  shows a step of forming a first conductive layer on the first resin insulating layer in the manufacturing method of the semiconductor package in an embodiment according to the present invention; 
         FIG. 11  shows a step of roughening a top surface of the first conductive layer in the manufacturing method of the semiconductor package in an embodiment according to the present invention; 
         FIG. 12  shows a step of forming openings in the first resin insulating layer in the manufacturing method of the semiconductor package in an embodiment according to the present invention; 
         FIG. 13  shows a step of removing a roughened region of the first conductive layer and also removing residue on a bottom surface of each of the openings in the manufacturing method of the semiconductor package in an embodiment according to the present invention; 
         FIG. 14  shows a step of forming a conductive plating layer by electroless plating in the manufacturing method of the semiconductor package in an embodiment according to the present invention; 
         FIG. 15  shows a step of forming a photosensitive photoresist in the manufacturing method of the semiconductor package in an embodiment according to the present invention; 
         FIG. 16  shows a step of partially removing the photosensitive photoresist by photolithography in the manufacturing method of the semiconductor package in an embodiment according to the present invention; 
         FIG. 17  shows a step of forming a second conductive layer by electroplating in the manufacturing method of the semiconductor package in an embodiment according to the present invention; 
         FIG. 18  shows a step of removing a resist pattern formed of the photoresist in the manufacturing method of the semiconductor package in an embodiment according to the present invention; 
         FIG. 19  shows a step of partially removing the second conductive layer to form lines in the manufacturing method of the semiconductor package in an embodiment according to the present invention; 
         FIG. 20  shows a step of forming a second resin insulating layer covering the lines in the manufacturing method of the semiconductor package in an embodiment according to the present invention; 
         FIG. 21  shows a step of forming openings, exposing the lines, in the second resin insulating layer in the manufacturing method of the semiconductor package in an embodiment according to the present invention; 
         FIG. 22  shows a step of locating solder balls at positions corresponding to the exposed lines in the manufacturing method of the semiconductor package in an embodiment according to the present invention; 
         FIG. 23  shows a step of reflowing the solder balls in the manufacturing method of the semiconductor package in an embodiment according to the present invention; 
         FIG. 24  shows a step of forming cuts (grooves) in the second resin insulating layer, the first resin insulating layer and the adhesive layer, so that the cuts reach the support substrate, in the manufacturing method of the semiconductor package in an embodiment according to the present invention; 
         FIG. 25  shows a step of cutting the resultant assembly to form individual semiconductor packages in the manufacturing method of the semiconductor package in an embodiment according to the present invention; 
         FIG. 26  is a schematic cross-sectional view of a semiconductor package in an embodiment according to the present invention; 
         FIG. 27  shows a step of preparing a support substrate in the manufacturing method of the semiconductor package in an embodiment according to the present invention; 
         FIG. 28  shows a step of forming an adhesive layer on the support substrate in the manufacturing method of the semiconductor package in an embodiment according to the present invention; 
         FIG. 29  shows a step of roughening a bottom surface and a side surface of the support substrate in the manufacturing method of the semiconductor package in an embodiment according to the present invention; 
         FIG. 30  shows a step of forming alignment markers in the adhesive layer in the manufacturing method of the semiconductor package in an embodiment according to the present invention; 
         FIG. 31  shows a step of locating a semiconductor device on the support substrate in the manufacturing method of the semiconductor package in an embodiment according to the present invention; 
         FIG. 32  shows a step of forming a frame on the support substrate in the manufacturing method of the semiconductor package in an embodiment according to the present invention; and 
         FIG. 33  shows a step of forming a frame on the support substrate in the manufacturing method of the semiconductor package in an embodiment according to the present invention. 
     
    
    
     DESCRIPTION OF EMBODIMENTS 
     Hereinafter, a structure of a semiconductor package and a manufacturing method of the same in embodiments according to the present invention will be described with reference to the drawings. The following embodiments are examples of the present invention, and the present invention is not construed as being limited to any of the embodiments. In the drawings referred to in this specification, components that are the same or have substantially the same functions as those shown in a previous drawing(s) bear the identical or similar reference signs thereto, and descriptions thereof may not be repeated. In the drawings, for the sake of illustration, the relative sizes may be different from the actual relative sizes, or a part of the structure may be omitted. For the sake of illustration, terms “above” and “below” may be used, but in the case where, for example, it is described that a first member is above a second member, the second member may be above the first member. In the following description, the phrase “first surface” or “second surface” used for a substrate does not refer to any specific surface of the substrate. The phrases “first surface” and the “second surface” are respectively used to specify the side of a top surface of the substrate and the side of a bottom surface of the substrate, namely, are used to specify the up-down direction with respect to the substrate. 
     Embodiment 1 
     With reference to  FIG. 1 , an overview of a semiconductor package  10  in embodiment 1 according to the present invention will be described in detail.  FIG. 1  is a schematic cross-sectional view of the semiconductor package  10  in embodiment 1 according to the present invention. 
     (Structure of the Semiconductor Package  10 ) 
     As shown in  FIG. 1 , the semiconductor package  10  includes a support substrate  100 , an adhesive layer  110 , a semiconductor device  120 , a first resin insulating layer  130 , lines  140 , a second resin insulating layer  150 , and solder balls  160 . 
     The support substrate  100  is partially recessed to form the alignment markers  102 . The adhesive layer  110  is located on a top surface of the support substrate  100 , and the adhesive layer  110  is partially opened to expose the alignment markers  102 . The adhesive layer  110  has openings  112  formed therein, which are larger than the alignment markers  102 . The openings  112  expose the alignment markers  102  and parts of the top surface of the support substrate  100  that are around the alignment markers  102 . The semiconductor device  120  is located on the adhesive layer  110 . On the semiconductor  120 , external terminals  122  connected with an electronic circuit included in the semiconductor device  120  are located. In the example shown in  FIG. 1 , the adhesive layer  110  is a single film layer. The adhesive layer  110  is not limited to having such a structure and may include a plurality of films. 
     The first resin insulating layer  130  is located on the support substrate  100  so as to cover the semiconductor device  120 . The first resin insulating layer  130  has openings  132  formed therein. The openings  132  reach the external terminals  122 . In other words, the openings  132  are provided so as to expose the external terminals  122 . 
     The lines  140  include a first conductive layer  142  and a second conductive layer  144 . The first conductive layer  142  is located on a top surface of the first resin insulating layer  130 . The second conductive layer  144  is located on the first conductive layer  142  and in the openings  132 , and is connected with the external terminals  122 . In the example shown in  FIG. 1 , the first conductive layer  142  is located only on the first resin insulating layer  130 , and is not located in the openings  132  at all. The semiconductor package  10  is not limited to having such a structure. For example, the first conductive layer  142  may be partially located in the openings  132 . The first conductive layer  142  and the second conductive layer  144  may each be a single film layer as shown in  FIG. 1 , or alternatively, one of, or both of, the first conductive layer  142  and the second conductive layer  144  may include a plurality of films. 
     The second resin insulating layer  150  is located on the first resin insulating layer  130  so as to cover the lines  140 . The second resin insulating layer  150  has openings  152  formed therein. The openings  152  reach the lines  140 . In other words, the openings  152  are located so as to expose the lines  140 . 
     The solder balls  160  are located in the openings  152  and on a top surface of the second resin insulating layer  150 , and are connected with the lines  140 . A surface of each of the solder balls  160  protrudes upward from the top surface of the second resin insulating layer  150 . The protruding portion of each solder ball  160  is curved upward. The curved shape of each solder ball  160  may be arcked or parabolic as seen in a cross-sectional view. 
     (Materials of Components of the Semiconductor Package  10 ) 
     The materials of each of components (layers) included in the semiconductor package  10  shown in  FIG. 1  will be described in detail. 
     A metal material containing at least one kind of metal can be used as the support substrate  100 . The metal material may be stainless steel (SUS), aluminum (Al), titanium (Ti), copper (Cu) or the like. Alternatively, the support substrate  100  may be a semiconductor material such as silicon, silicon carbide, compound semiconductor or an insulating material such as glass, quartz, sapphire, resin or the like. It is preferable to use stainless steel for the support substrate  100  because stainless steel has a low coefficient of thermal expansion and costs low. 
     The adhesive layer  110  may be formed of an adhesive material containing an epoxy-based resin or an acrylic resin. 
     The semiconductor device  120  may be a central processing unit (CPU), a memory, a microelectromechanical system (MEMS) device, a semiconductor element for power (power device), or the like. 
     The first resin insulating layer  130  and the second resin insulating layer  150  may each be formed of polyimide, epoxy-based resin, polyimide resin, benzocyclobutene resin, polyamide, phenol resin, silicone resin, fluorocarbon resin, liquid crystal polymer, polyamideimide, polybenzoxazole, cyanate resin, aramid, polyolefin, polyester, BT resin, FR-4, FR-5, polyacetal, polybutyleneterephthalate, syndiotactic polystyrene, polyphenylenesulfide, polyetheretherketone, polyethernitrile, polycarbonate, polyphenyleneetherpolysulfone, polyethersulfone, polyarylate, polyetherimide, or the like. It is preferable to use an epoxy-based resin for the first resin insulating layer  130  and the second resin insulating layer  150  because the epoxy-based resin is superb in electric characteristics and processability. 
     The first resin insulating layer  130  used in this embodiment contains a filler. The filler may be an inorganic filler such as glass, talc, mica, silica, alumina or the like. The filler may be an organic filler such as a fluorocarbon resin filler or the like. The first resin insulating layer  130  does not need to contain a filler. In this embodiment, the second resin insulating layer  150  contains a filler. Alternatively, the second resin insulating layer  150  may not contain a filler. 
     The first conductive layer  142  and the second conductive layer  144  may be formed of a metal material selected from copper (Cu), gold (Au), silver (Ag), platinum (Pt), rhodium (Rh), tin (Sn), aluminum (Al), nickel (Ni), palladium (Pd), chromium (Cr) and the like, and an alloy thereof. The first conductive layer  142  and the second conductive layer  144  may be formed of the same material or different materials. 
     The solder balls  160  may each of a spherical body formed of, for example, an Sn alloy containing a small amount of Ag, Cu, Ni, bismuth (Bi) or zinc (Zn) incorporated into Sn. Instead of the solder balls, general conductive particles may be used. For example, a particle formed of a resin and wrapped with a conductive film may be used as a conductive particle. Instead of the solder balls, a solder paste may be used. The solder paste may be formed of Sn, Ag, Cu, Ni, Bi, phosphorus (P), germanium (Ge), indium (In), antimony (Sb), cobalt (Co), lead (Pb) or the like. 
     (Manufacturing Method of the Semiconductor Package  10 ) 
     With reference to  FIG. 2  through  FIG. 25 , a manufacturing method of the semiconductor package  10  in embodiment 1 according to the present invention will be described. In  FIG. 2  through  FIG. 25 , the components that are the same as those shown in  FIG. 1  bear the same reference signs. In the following description, a manufacturing method of the semiconductor package  10  using the support substrate  100  formed of stainless steel, the first resin insulating layer  130  formed of an epoxy-based resin, the first conductive layer  142  and the second conductive layer  144  formed of Cu, and the solder balls  160  formed of an Sn alloy described above will be described. 
       FIG. 2  shows a step of forming the alignment markers  102  in the support substrate  100  in the manufacturing method of the semiconductor package  10  in embodiment 1 according to the present invention. The alignment markers  102  are formed on the top surface of the support substrate  100  by photolithography and etching. The positions and the planar shape of the alignment markers  102  may be determined appropriately in accordance with the purpose of the semiconductor package  10 . The alignment markers  102  may each have a stepped portion visually recognizable when the support substrate  100  is observed from above by an optical microscope or the like. 
       FIG. 3  shows a step of forming the adhesive layer  110  on the support substrate  100  in the manufacturing method of the semiconductor package  10  in embodiment 1 according to the present invention. The adhesive layer  110  is formed on the top surface of the support substrate  100  having the alignment markers  102  formed therein. As the adhesive layer  110 , a sheet-like adhesive layer is bonded. Alternatively, a solution containing an adhesive material dissolved therein may be applied on the support substrate  100  to form the adhesive layer  110 . In the example shown in  FIG. 3 , recessed portions acting as the alignment markers  102  are hollow. Alternatively, the adhesive layer  110  may be formed to fill the recessed portions because such parts of the adhesive layer  110  that are in the alignment markers  102  will be removed in a later step. 
       FIG. 4  shows a step of roughening a bottom surface and a side surface of the support substrate  100  in the manufacturing method of the semiconductor package  10  in embodiment 1 according to the present invention. The bottom surface and the side surface of the support substrate  100  are roughened for the purpose of suppressing a plating layer formed by electroless plating in a later step from being delaminated. Then, a metal is attached to the roughened bottom surface and the roughened side surface of the support substrate  100 . Roughening the bottom surface and the side surface of the support substrate  100  and attaching the metal to the roughened bottom surface and the roughened side surface may be realized by wet etching by use of a chemical (etchant) containing ions of a metal desired to be attached to the roughened surfaces of the supporting substrate  100 . In  FIG. 4 , a region  104  that is roughened (roughened region  104 ) is represented by the dashed line. 
     Roughening of the support substrate  100  will be described in more detail. A passive state film is formed on a surface of the stainless steel substrate which is the support material  100 . The etchant used for roughening contains metal ions having a lower ionization tendency than that of the metal contained in the stainless steel substrate. For example, ferric chloride (FeCl 3 ) solution containing copper (Cu) ions may be used as an etchant. When the stainless steel substrate is wet-etched using ferric chloride (FeCl 3 ) solution containing copper (Cu) ions as an etchant, the surface of the stainless base substrate is etched and roughened. At this time, the etching of the stainless steel substrate proceeds locally. Therefore, the surface of the stainless steel substrate is etched nonuniformly, and the irregularity of the surface of the stainless steel substrate increases after the etching. Copper is precipitated on the roughened surface, due to the difference between the ionization tendency of the metal contained in the stainless steel substrate and the ionization tendency of copper contained in the etchant, together with the roughening of the surface of the stainless steel substrate. That is, by immersing the stainless steel substrate shown in  FIG. 4  in the etchant, it is possible to roughen a back surface and side surface of the stainless steel substrate by the same treatment and to attach copper to the roughened surface. The metal ions contained in the etchant are not limited to copper ions, and appropriate metal ions can be contained in consideration of adhesion to a plating layer formed by an electroless plating method described later. For example, when the plating layer contains copper (Cu), copper ions are preferable as the metal ions contained in the etchant and having a low ionization tendency. 
     In this example, the stainless steel substrate is roughened after the adhesive layer  110  is bonded. The present invention is not limited to such a manufacturing method. For example, the stainless steel substrate may be roughened before the adhesive layer  110  is bonded, or before the alignment markers  102  are formed. 
       FIG. 5  shows a step of partially removing the adhesive layer  110  in the manufacturing method of the semiconductor package  10  in embodiment 1 according to the present invention. In order to read the alignment markers  102  more precisely, parts of the adhesive layer  110  that are above the alignment markers  102  are removed to form the openings  112 . The parts of the adhesive layer  110  may be removed by, for example, sublimation or ablation by laser irradiation. Alternatively, the openings  112  may be formed by photolithography and etching. The openings  112  are formed in regions larger than the alignment markers  102  in order to expose the alignment markers  102  with certainty. More specifically, the openings  112  expose parts of the top surface of the support substrate  100  (surface in which the alignment markers  102  are formed). In other words, the openings  112  are each formed such that an outer edge thereof encloses an outer circumference of the corresponding alignment marker  102  as seen in a plan view. 
       FIG. 6  shows a step of locating the semiconductor device  120  on the support substrate  100  in the manufacturing method of the semiconductor package  10  in embodiment 1 according to the present invention. The semiconductor device  120  is positionally aligned with respect to the support substrate  100  by use of the alignment markers  102  exposed as described above, and the semiconductor device  120  having the external terminals  122  provided on a top surface thereof is located on the support substrate  100  with the adhesive layer  110  being provided between the semiconductor device  120  and the support substrate  100 . The semiconductor device  120  is disposed on the support base  100  inwardly of a position where the alignment marker  102  is formed. The alignment markers  102  may be read by, for example, an optical microscope, a CCD camera, an electron microscope or the like. The semiconductor device  120  is mounted on the support substrate  100  with high alignment precision by this method. 
       FIG. 7  and  FIG. 8  show a step of forming a frame  106  on the support substrate  100  in the manufacturing method of the semiconductor package  10  in embodiment 1 according to the present invention.  FIG. 7  is a top view of the support substrate  100 , and  FIG. 8  shows a part of a cross-sectional view of  FIG. 7 . The frame  106  is formed on the support substrate  100  in order to allow the thickness of the first resin insulating layer, to be formed in a later step, to be equalized. In  FIG. 7  and  FIG. 8 , as an example, the frame  106  is formed on the support substrate  100  via the adhesive layer  110  so as to surround the periphery of each semiconductor device  120  disposed on the support substrate  100 . The frame  106  is formed so as to surround the alignment markers  102 . The frame  106  may be formed before the semiconductor device  120  is disposed on the support substrate  100 . 
     The material of the frame  106  is not particularly limited, but it may be an insulating resin such as an epoxy resin. For example, the frame  106  may be formed by processing sheet-like epoxy resin into a desired shape. The thickness of the frame  106  (the thickness in the thickness direction of the support substrate  100 ) may be equal to or greater than the thickness of the semiconductor device described later, or may be thinner than the thickness of the semiconductor device, since the first resin insulating layer  130  is set to have an appropriate thickness with respect to the thickness of the semiconductor device. By forming the frame  106  on the support substrate  100  so as to surround the periphery of each semiconductor device, it is possible to make the thickness of the first resin insulation layer, which is described later, uniform within each chip region  101 . In addition, since the frame  106  is disposed on the support substrate  100 , it is possible to prevent the solution, in which the material of the first resin insulating layer  130  to coat the support substrate  100  is dissolved, from flowing out to the roughened side surface, on which the metal is precipitated, of the support substrate  100 . Thus, the adhesion between the conductive layer formed by the electroless plating method described later and the support substrate  100  can be maintained. 
       FIG. 9  shows a step of forming the first resin insulating layer  130  in the manufacturing method of the semiconductor package  10  in embodiment 1 according to the present invention. As shown in  FIG. 9 , a solution, in which the material of the first resin insulating layer  130  is dissolved, is poured and the solvent is removed by heat treatment, whereby the first resin insulating layer  130  can be obtained. Alternatively, the first resin insulating layer  130  may be formed by bonding a sheet-like insulating film. Specifically, the sheet-like film is bonded to the support substrate  100  having the semiconductor device  120  mounted thereon, and then is melted by heating. The melted sheet-like film is caused to fill the recessed portions acting as the alignment markers  102  by pressurization. The first resin insulating layer  130  shown in  FIG. 9  may be formed of the sheet-like film by the heating and the pressurization. The first resin insulating layer  130  can also be obtained by pouring the molten material of the first resin insulating layer  130  and curing the material using a molding technique. The first resin insulating layer  130  is set to have a thickness sufficient for the first insulating layer  130  to cover the semiconductor device  120 . Namely, the thickness of the first insulating layer  130  is greater than the thickness (height) of the semiconductor device  120 . The first resin insulating layer  130  prevents the semiconductor device  120  and the external terminal  122  from being electrically connected to the line  140 . In the region surrounded by the frame  106 , the thickness of the first resin insulating layer  130  is uniform. The first resin insulating layer  130  alleviates (flattens) the stepped portions formed by the semiconductor device  120 , the adhesive layer  110  and the like, and thus the yield of the semiconductor package is improved. 
     In the example shown in  FIG. 9 , the manufacturing method in which the first resin insulating layer  130  is formed by spin coating is explained. The method of forming the first resin insulating layer  130  is not limited to this method. For example, the first resin insulating layer  130  can be formed by any of various methods such as dip coating, ink jetting, vapor deposition and the like. 
       FIG. 10  shows a step of forming the first conductive layer  142  on the first resin insulating layer  130  in the manufacturing method of the semiconductor package  10  in embodiment 1 according to the present invention. A sheet-like conductive film is bonded to the top surface of the first resin insulating layer  130 . In other words, the conductive film is used as the first conductive layer  142 . In this example, the first conductive layer  142  is formed by bonding a film. The first conductive layer  142  is not limited to being formed by this method. For example, the first conductive layer  142  may be formed by plating or physical vapor deposition (PVD). The PVD may be sputtering, vacuum vapor deposition, electron beam deposition, molecular beam epitaxy, or the like. Alternatively, a solution containing a conductive resin material dissolved therein may be applied to form the first conductive layer  142 . 
       FIG. 11  shows a step of roughening a top surface of the first conductive layer  142  in the manufacturing method of the semiconductor package  10  in embodiment 1 according to the present invention. As shown in  FIG. 11 , the top surface of the first conductive layer  142  formed on the first resin insulating layer  130  is roughened. The top surface of the first conductive layer  142  may be roughened by etching using a ferric chloride-containing etchant. In  FIG. 11 , a region  146  that is roughened (roughened region  146 ) is represented by the dashed line. 
       FIG. 12  shows a step of forming the openings  132  in the first resin insulating layer  130  in the manufacturing method of the semiconductor package  10  in embodiment 1 according to the present invention. As shown in  FIG. 12 , parts of the roughened region  146  in the top surface of the first conductive layer  142  that correspond to the external terminals  122  are irradiated with laser light to form the openings  132  exposing the external terminals  122 . The openings  132  may be formed in the first conductive layer  142  and in the first resin insulating layer  130  in the same step. An example of the laser used to form the openings  132  is a CO 2  laser. The light generated by the CO 2  laser has the spot diameter and the energy amount thereof adjusted in accordance with the size of each opening  132 , and is used to perform pulse irradiation a plurality of times. Since the top surface of the first conductive layer  142  has the roughened region  146 , the energy of the laser light directed thereto is absorbed into the first conductive layer  142  efficiently. The laser light is directed toward a position inner to each of the external terminals  122 . Namely, the laser light is directed so as not to expand beyond the pattern of the external terminals  122 . In the case where a part of the semiconductor device  120  is to be processed, the laser light may be directed so as to partially expand beyond the external terminals  122  intentionally. 
     In the example shown in  FIG. 12 , a side wall of the first conductive layer  142  and a side wall of the first resin insulating layer  130  that are in each of the openings  132  are continuous to each other. The semiconductor package  10  is not limited to having such a structure. For example, in the case where the openings  132  are formed by laser irradiation, the first resin insulating layer  130  may retract in a planar direction of the support substrate  100  (direction in which the diameter of the openings  132  is enlarged) more than the first conductive layer  142 . Namely, an end of the first conductive layer  142  may protrude into each opening  132  more than an end of the first resin insulating layer  130 . In other words, the first conductive layer  142  may protrude like a canopy. In still other words, at the time when the openings  132  are formed, a bottom surface of the first conductive layer  142  may be partially exposed to the openings  132 . In this case, the protruded portions of the first conductive layer  142  may be bent toward the outer terminals  122  in the openings  132 . 
       FIG. 13  shows a step of removing the roughened region  146  of the first conductive layer  142  and also removing residue on a bottom surface of each of the openings  132  in the manufacturing method of the semiconductor package  10  in embodiment 1 according to the present invention. After the openings  132  are formed, the roughened region  146  at the top surface of the first conductive layer  142  is first removed. The roughened region  146  may be removed by an acid treatment. After the roughened region  146  is removed, residue (smear) on the bottom surface of each opening  132  is removed. The removal of the residue (desmearing) is performed in two stages. 
     A method for removing the residue on the bottom surface of each opening  132  will be described in detail. First, the bottom surface of each opening  132  is subjected to a plasma treatment. The plasma treatment may be performed with plasma containing fluorine (CF 4 ) gas and oxygen (O 2 ) gas. The plasma treatment mainly removes parts of the first resin insulating layer  130  in the openings  132  that have not been removed by the formation of the opening  132 . The plasma treatment also removes a quality-changed layer of the first resin insulating layer  130  generated by the formation of the openings  132 . For example, in the case where the openings  132  are formed by laser irradiation, a layer of the first resin insulating layer  130  that is changed in quality by the energy of the laser light may remain on the bottom surfaces of the openings  132 . The above-described plasma treatment removes such a quality-changed layer efficiently. 
     After the plasma treatment, a chemical treatment is performed. The chemical treatment may be performed with sodium permanganate or potassium permanganate. The chemical treatment removes the residue that has not been removed by the plasma treatment. For example, the filler contained in the first resin insulating layer  130  and has not been removed by the plasma treatment is removed. Sodium permanganate or potassium permanganate is an etchant having a role of etching the residue away. Before the treatment with the etchant, a swelling solution swelling the first resin insulating layer  130  may be used. After the treatment with the etchant, a neutralizing solution neutralizing the etchant may be used. 
     The use of the swelling solution expands a ring of resin and thus increases the wettability. This suppresses formation of a non-etched region. The use of the neutralizing solution allows the etchant to be removed efficiently, and thus suppresses an unintended progress of etching. For example, in the case where an alkaline chemical is used as the etchant, the etching may progress excessively in an unintended manner because the alkaline chemical is not easily removed by washing with water. Even in this case, the use of the neutralizing solution after the etching suppresses such an unintended progress of etching. 
     The swelling solution may be an organic solvent containing, for example, diethylene glycol monobutyl ether and ethylene glycol. The neutralizing solution may be a sulfuric acid-based chemical such as hydroxylamine sulfate or the like. 
     For example, in the case where an inorganic filler is contained in the first resin insulating layer  130 , the filler may not be removed by the plasma treatment and remain as residue. Even in such a case, the chemical treatment performed after the plasma treatment removes the residue caused by the filler. 
       FIG. 14  shows a step of forming a conductive plating layer  200  by electroless plating in the manufacturing method of the semiconductor package  10  in embodiment 1 according to the present invention. The plating layer  200  (conductive body) to be connected with the external terminals  122  exposed after the above-described desmearing step is formed by electroless plating. As the electroless plating, electroless copper plating is usable for forming the plating layer. According to the electroless copper plating, palladium colloid is adsorbed to a resin and immersed in a chemical solution containing Cu to replace Pd and Cu with each other, so that Cu is deposited. Since the plating layer  200  is formed by electroless plating after the roughened region  146  is removed, the adhesiveness of the plating layer  200  to the first conductive layer  142  is increased. 
       FIG. 15  shows a step of forming a photosensitive photoresist  210  in the manufacturing method of the semiconductor package  10  in embodiment 1 according to the present invention. As shown in  FIG. 15 , the photosensitive photoresist  210  is formed on the plating layer  200 . The photosensitive photoresist  210  is formed by an application method such as spin-coating or the like. Before the photosensitive photoresist  210  is formed, a treatment to increase the adhesiveness between the plating layer  200  and the photosensitive photoresist  210  (hydrophobization surface treatment such as HMDS treatment or the like) may be performed. The photosensitive photoresist  210  may be of a negative type, in which case a region exposed to light is difficult to be etched by a developer, or may be of a positive type, in which case a region exposed to light is easily etched by a developer. 
       FIG. 16  shows a step of partially removing the photosensitive photoresist  210  by photolithography in the manufacturing method of the semiconductor package  10  in embodiment 1 according to the present invention. As shown in  FIG. 16 , the photosensitive photoresist  210  applied in the previous step is exposed and developed, so that parts of the photosensitive photoresist  210  that correspond to regions where the lines  140  ( FIG. 1 ) are to be formed are removed. As a result, a resist pattern  220  is formed. Before the photosensitive photoresist  210  is exposed to form the resist pattern  220 , positional alignment is performed by use of the alignment markers  102  formed in the support substrate  100 . 
       FIG. 17  shows a step of forming the second conductive layer  144  by electroplating in the manufacturing method of the semiconductor package  10  in embodiment 1 according to the present invention. After the resist pattern  220  is formed, the plating layer  200  formed by electroless plating is supplied with an electric current to perform electroplating, so that a part of the plating layer  200  that is exposed from the resist pattern  220  is grown to be thicker to form the second conductive layer  144 . A part of the first conductive layer  142  and a part of the plating layer  200  that are below the resist pattern  220  will be removed when the entire surface is etched in a later step, and therefore, the thickness of the second conductive layer  144  will be also decreased. Thus, the thickness of the second conductive layer  144  is adjusted in consideration of the amount of the thickness that will be decreased in the later step. 
       FIG. 18  shows a step of removing the resist pattern  220  formed of the photoresist in the manufacturing method of the semiconductor package  10  in embodiment 1 according to the present invention. As shown in  FIG. 18 , after the plating layer  200  is made thicker to form the second conductive layer  144 , the photoresist forming the resist pattern  220  is removed by an organic solvent. The photoresist may be removed by ashing with oxygen plasma instead of by the organic solvent. As a result of the removal of the photoresist, a thick film region  230  including the second conductive layer  144  and a thin film region  240  including the plating layer  200  but not including the second conductive layer  144  are obtained. The thick film region  230  includes a thick plating layer generated as a result of the thickness of the plating layer  200  being increased by electroplating. Therefore, the second conductive layer  144  strictly includes two layers. However,  FIG. 16  does not distinguish these two layers. 
       FIG. 19  shows a step of partially removing the second conductive layer  144  to form the lines  140  in the manufacturing method of the semiconductor package  10  in embodiment 1 according to the present invention. As shown in  FIG. 19 , the part of the plating layer  200  and the part of the first conductive layer  142  that have not been thickened as a result of being covered with the resist pattern  220  are removed (etched away), so that the assembly of the first conductive layer  142  and the second conductive layer  144  is electrically divided into lines  140 . The etching performed on the plating layer  200  and the first conductive layer  142  results in the second conductive layer  142  in the thick film region  230  being also etched from a top surface thereof and thus thinned. Therefore, it is preferable to set the original thickness of the second conductive layer  144  in consideration of the amount of thickness that is decreased in this step. The etching in this step may be wet etching or dry etching. In the example shown in  FIG. 19 , the lines  140 , which have a one-layer structure, are formed. The semiconductor package  10  is not limited to being formed by this method. An insulating layer and a conductive layer may be stacked on the lines  140 , so that a multiple-layer line including a plurality of line layers may be formed. In this case, each time a line layer is to be formed, an alignment marker may be formed to be used for positional alignment of the layers above the layers already formed. 
       FIG. 20  shows a step of forming a second resin insulating layer  150  covering the lines  140  in the manufacturing method of the semiconductor package  10  in embodiment 1 according to the present invention. For example, the second resin insulating layer  150  is formed by bonding a sheet-like insulating film and performing pressurization and heating on the sheet-like insulating film. The second resin insulating layer  150  is set to have a thickness sufficient for the second insulating layer  150  to cover the lines  140 . Namely, the thickness of the second insulating layer  150  is greater than the thickness of the lines  140 . The second resin insulating layer  150  alleviates (flattens) the stepped portions formed by the lines  140  and the like, and thus may be referred to as a “flattening film”. 
     The second resin insulating layer  150  prevents connection of the line  140  with the solder ball  160  at the region other than the contact portion. Namely, there is a gap between the line  140  and the solder ball  160 . As long as the second insulating layer  150  is located on at least a top surface and a side surface of each of the lines  140 , the thickness of the second resin insulating layer  150  may be smaller than the thickness of the lines  140 . In the example shown in  FIG. 20 , the second insulating layer  150  is formed by bonding a sheet-like film. The second resin insulating layer  150  is not limited to being formed by this method. For example, the second resin insulating layer  150  may be formed by any of various methods including spin-coating, dipping, ink-jetting, vapor deposition and the like. 
       FIG. 21  shows a step of forming the openings  152 , exposing the lines  140 , in the second resin insulating layer  150  in the manufacturing method of the semiconductor package  10  in embodiment 1 according to the present invention. As shown in  FIG. 21 , the openings  152  exposing the lines  150  are formed in the second resin insulating layer  150 . The openings  152  may be formed by photolithography and etching. In the case where the second resin insulating layer  150  is formed of a photosensitive resin, the openings  152  may be formed by exposure and development. Positional alignment may be performed to form the openings  152  by use of the alignment marker formed in the step of forming the lines  140 . 
       FIG. 22  shows a step of locating the solder balls  160  at positions corresponding to the exposed lines  140  in the manufacturing method of the semiconductor package  10  in embodiment 1 according to the present invention. As shown in  FIG. 22 , the solder balls  160  are located in the openings  152 . In the example shown in  FIG. 22 , one solder ball  160  is located in one opening  152 . The solder balls  160  are not limited to being located by this method. For example, a plurality of solder balls  160  may be located in one opening  152 . In the example shown in  FIG. 22 , the solder balls  160  are in contact with the lines  140  on the stage where the solder balls  160  are located in the openings  152 . The solder balls  160  are not limited to being located by this method. For example, the solder balls  160  may not be in contact with the lines  140  on the stage shown in  FIG. 22 . Positional alignment may be performed to locate the solder balls  160  by use of the alignment marker formed in the step of forming the lines  140 . 
       FIG. 23  shows a step of reflowing the solder balls  160  in the manufacturing method of the semiconductor package  10  in embodiment 1 according to the present invention. Thermal treatment is performed in the state shown in  FIG. 22  to reflow the solder balls  160 . “Reflow” refers to liquefying at least a part of a solid target so as to fluidize the solid target and supplying the fluid target to a recessed portion. As a result of reflowing the solder balls  160 , top surfaces of the lines  140  are entirely put into contact with the solder balls  160 . 
       FIG. 24  shows a step of forming cuts (grooves)  250  in the second resin insulating layer  150 , the first resin insulating layer  130  and the adhesive layer  110 , so that the cuts  250  reach the support substrate  100 , in the manufacturing method of the semiconductor package  10  in embodiment 1 according to the present invention. In this example, the cuts  250  are formed by use of a dicing blade (e.g., circular rotatable blade formed of diamond) in the adhesive layer  110 , the first resin insulating layer  130  and the second resin insulating layer  150 . For forming the cuts  250 , the above-described layers are cut by the dicing blade while the dicing blade is rotated at high speed and cooled with pure water and chips generated by the cutting is washed away with pure water. In the example shown in  FIG. 24 , the cuts  250  are formed in the adhesive layer  110 , the first resin insulating layer  130  and the second resin insulating layer  150  outside the alignment marker  102  and inside the frame  106 . The cuts  250  may be formed to reach the support substrate  100  by dicing. Namely, recessed portions may be formed at the top surface of the support substrate  100  by dicing. Alternatively, dicing may be performed such that a part of the adhesive layer  110 , or the adhesive layer  110  and a part of the first resin insulating layer  130 , remain. 
       FIG. 25  shows a step of cutting the resultant assembly to form individual semiconductor packages  10  in the manufacturing method of the semiconductor package  10  in embodiment 1 according to the present invention. As shown in  FIG. 25 , the bottom surface of the support substrate  100  (surface opposite to the surface on which the semiconductor device  120  is located) is irradiated with laser light to provide the individual semiconductor packages  10 . The laser light is directed to a position outside of the alignment marker  102  and inside the frame  106  on the bottom surface of the support substrate  100 . The laser used to irradiate the support substrate  100  with laser light may be a CO 2  laser. Positional alignment may be performed for laser irradiation by use of the alignment markers  102  formed in the support substrate  100 . The laser light is directed to a region smaller than each of the cuts  250  as seen in a plan view. In this way, the support substrate  100  is divided into a plurality of semiconductor packages. At this time, the frame  106  arranged so as to surround the semiconductor device  120  is removed. 
     In this example, the bottom surface of the support substrate  100  is irradiated with laser light. The individual semiconductor packages  10  are not limited to being provided by this method. For example, the laser light may be directed from the side of the top surface of the support substrate  100  through the cuts  250 . In this example, the laser light is directed to a region smaller than each cut  250  as seen in a plan view. The individual semiconductor packages  10  are not limited to being provided by this method. For example, the laser light may be directed to a region of an equal size to that of each cut  250  as seen in a plan view. Alternatively, the laser light may be directed to a region larger than each cut  250  as seen in a plan view. 
     In the case where the support substrate  100  is formed of a metal material, if the cuts are formed throughout the assembly of the adhesive layer  110 , the first resin insulating layer  130 , the second resin insulating layer  150  and the support substrate  100  to divide the assembly into the semiconductor packages  10 , the dicing blade is significantly abraded and thus the life of the dicing blade is shortened. If the support substrate  100  formed of a metal material is mechanically processed by the dicing blade, edges of the post-processing support substrate  100  may have burr having a sharp angle, which has a risk of injuring the worker at the time of dicing. In this embodiment, the cuts  250  are mechanically formed with the dicing blade through the layers above the support substrate  100  and the support substrate is processed with laser light. Therefore, the abrasion of the dicing blade is suppressed, and the edges of the post-processing support substrate  100  are smoothed. For such a reason, especially in the case where the support substrate  100  is formed of a metal material, it is preferable that the layers above the support substrate  100  are processed by a dicing blade and the support substrate  100  is processed with laser light. 
     As described above, according to the manufacturing method of the semiconductor package  10  in embodiment 1, the thickness of the first resin insulating layer  130  can be uniformized in the region surrounded by the frame  106  by disposing the frame  106  on the support substrate  100  via the adhesive layer  110  so as to surround the periphery of the semiconductor device  120  on the support substrate  100 . Thereby, the first resin insulating layer  130  can reduce (flatten) unevenness caused by the semiconductor device  120 , the adhesive layer  110 , and the like, and can prevent position displacement of the wiring  140  and the like. Additionally, since the frame  106  is disposed on the support substrate  100 , it is possible to prevent the solvent, in which the material of the first resin insulating layer  130  coating the support substrate  100  is dissolved, from flowing out to the roughened side surface, on which the metal is precipitated, of the support substrate  100 . Thus, the adhesion between the conductive layer formed by the electroless plating and the support substrate  100  can be maintained. Therefore, the yield of semiconductor package can be improved. 
     Embodiment 2 
     With reference to  FIG. 26 , an overview of a semiconductor package  20  in embodiment 2 according to the present invention will be described in detail.  FIG. 26  is a schematic cross-sectional view of the semiconductor package  20  in embodiment 2 according to the present invention. 
     (Structure of the Semiconductor Package  20 ). 
     The semiconductor package  20  in embodiment 2 is similar to the semiconductor package  10  in embodiment 1, but includes alignment markers  114  as openings formed in the adhesive layer  110  unlike the semiconductor package  10 . In the semiconductor package  20 , the support substrate  10  does not have any recessed portion formed therein. Alternatively, like the semiconductor package  10 , the semiconductor package  20  may have a recessed portion formed in the support substrate  100  as an assisting alignment marker. The other components of the semiconductor package  20  are substantially the same as those of the semiconductor package  10 , and thus will not be described in detail. 
     (Manufacturing Method of the Semiconductor Package  20 ) 
     With reference to  FIG. 27  through  FIG. 32 , a manufacturing method of the semiconductor package  20  in embodiment 2 according to the present invention will be described. In  FIG. 27  through  FIG. 32 , the same components as those shown in  FIG. 26  bear the same reference signs. Like in embodiment 1, a manufacturing method of the semiconductor package  20  using the support substrate  100  formed of stainless steel, the first resin insulating layer  130  formed of an epoxy-based resin, the first conductive layer  142  and the second conductive layer  144  formed of Cu, and the solder balls  160  formed of an Sn alloy described above. 
       FIG. 27  shows a step of preparing the support substrate  100  in the manufacturing method of the semiconductor package  20  in embodiment 2 according to the present invention. In the manufacturing method of the semiconductor package  20 , no alignment marker is formed in the support substrate  100 . Alternatively, alignment markers may be formed like in the step shown in  FIG. 2 . 
       FIG. 28  shows a step of forming the adhesive layer  110  on the support substrate  100  in the manufacturing method of the semiconductor package  20  in embodiment 2 according to the present invention. As shown in  FIG. 28 , the adhesive layer  110  is formed on a top surface of the support substrate  100 . As the adhesive layer  110 , a sheet-like adhesive layer is bonded. Alternatively, an adhesive material dissolved in a solvent may be applied as the adhesive layer  110  on the support substrate  100 . 
       FIG. 29  shows a step of roughening a bottom surface and a side surface of the support substrate  100  in the manufacturing method of the semiconductor package  20  in embodiment 2 according to the present invention. The bottom surface and the side surface of the support substrate  100  are roughened for the purpose of suppressing a plating layer formed by electroless plating in a later step from being delaminated. Then, a metal is attached to the roughened bottom surface and the roughened side surface of the support substrate  100 . Roughening the bottom surface and the side surface of the support substrate  100  and attaching the metal to the roughened bottom surface and the roughened side surface may be realized by wet etching by use of a chemical (etchant) containing ions of a metal desired to be attached to the roughened surfaces of the support substrate  100 . In  FIG. 29 , a region  104  that is roughened (roughened region  104 ) is represented by the dashed line. 
     In this example, the support substrate  100  formed of stainless steel is roughened after the adhesive layer  110  is bonded. The present invention is not limited to such a manufacturing method. For example, the support substrate  100  formed of SUS may be roughened before the adhesive layer  110  is bonded. 
       FIG. 30  shows a step of forming the alignment markers  114  in the adhesive layer  110  in the manufacturing method of the semiconductor package  20  in embodiment 2 according to the present invention. The alignment markers  114  are formed by sublimation or ablation by laser radiation on the adhesive layer  110 . The positions and the planar shape of the alignment markers  114  may be determined appropriately in accordance with the purpose of the semiconductor package  20 . The alignment markers  114  may each have a stepped portion visually recognizable when the support substrate  100  is observed from above by an optical microscope or the like. More specifically, in the example shown in  FIG. 30 , the alignment markers  114  are openings formed in the adhesive layer  110 . Alternatively, the alignment markers  114  may be recessed portions formed in the adhesive layer  110 . In this step, an opening or a recessed portion different from the alignment markers  114  may be formed in the adhesive layer  110 . The opening or the recessed portion different from the alignment markers  114  may be formed by sublimation or ablation by laser irradiation. Alternatively, the opening or the recessed portion may be formed by photolithography and etching. 
       FIG. 31  shows a step of locating the semiconductor device  120  on the support substrate  100  in the manufacturing method of the semiconductor package  20  in embodiment 2 according to the present invention. The semiconductor device  120  is positionally aligned with respect to the support substrate  100  by use of the alignment markers  114  formed in the adhesive layer  110  as described above, and the semiconductor device  120  having the external terminals  122  provided on a top surface thereof is located on the support substrate  100  with the adhesive layer  110  being provided between the semiconductor device  120  and the support substrate  100 . The semiconductor device  120  is disposed on the support base  100  inwardly of a position where the alignment marker  114  is formed. The alignment markers  114  may be read by, for example, an optical microscope, a CCD camera, an electron microscope or the like. The semiconductor device  120  is mounted on the support substrate  100  with high alignment precision by this method. 
       FIG. 32  shows a step of forming a frame  106  on the support substrate  100  in the manufacturing method of the semiconductor package  10  in embodiment 2 according to the present invention. In  FIG. 32 , as an example, the frame  106  is formed on the support substrate  100  via the adhesive layer  110  so as to surround the periphery of each semiconductor device disposed on the support substrate  100 . The frame  106  may be formed before the semiconductor device  120  is disposed on the support substrate  100 . 
     The steps after the above step may be performed in substantially the same manner as shown in  FIG. 9  through  FIG. 25 , and thus will not be described. 
     As described above, according to the manufacturing method of the semiconductor package in embodiment 2, the thickness of the first resin insulating layer  130  can be uniformized in the region surrounded by the frame  106  by disposing the frame  106  on the support substrate  100  via the adhesive layer  110  so as to surround the periphery of the semiconductor device  120  on the support substrate  100 . Thereby, the first resin insulating layer  130  can reduce (flatten) unevenness caused by the semiconductor device  120 , the adhesive layer  110 , and the like, and the yield of semiconductor chips can be improved. Additionally, since the frame  106  is disposed on the support substrate  100 , it is possible to prevent the solvent, in which the material of the first resin insulating layer  130  coating the support substrate  100  is dissolved, from flowing out to the roughened side surface, on which the metal is precipitated, of the support substrate  100 . Thus, the adhesion between the conductive layer formed by the electroless plating and the support substrate  100  can be maintained. 
     In embodiments 1 and 2 described above, the thickness of the first resin insulating layer  130  can be uniformized in the region surrounded by the frame  106  by disposing the frame  106  on the support substrate  100  via the adhesive layer  110  so as to surround the periphery of the semiconductor device  120  on the support substrate  100 . However, aspects of the present invention are not limited to embodiment 1 and embodiment 2. 
     For example, as shown in  FIG. 33 , in the case where a plurality of semiconductor devices  120  are disposed on the support substrate  100 , a frame  106   a  may be formed on the support substrate  100  so as to surround the plurality of semiconductor devices  120 . Configurations other than the arrangement of the frame  106   a  are the same as those of embodiment 1 or embodiment 2. The frame  106   a  is formed so as to surround the plurality of semiconductor devices  120 . Because of this structure, in a step of forming the first resin insulating layer  130 , it is possible to prevent the solvent, in which the material of the first resin insulating layer  130  coating the support substrate  100  is dissolved, from flowing out from the frame  106   a  before the first resin insulating layer  130  is cured. Therefore, it is possible to make the thickness of the first resin insulating layer  130  uniform in the region surrounded by the frame  106   a  on the support substrate  100 , and the first resin insulating layer  130  can reduce (flatten) unevenness caused by the semiconductor device  120 , the adhesive layer  110 , and the like. In addition, the frame  106   a  is formed on the support substrate  100 . Therefore, the solvent, in which the material of the first resin insulating layer  130  coating the support substrate  100  is dissolved, is prevented from flowing out from the frame  106   a  to the roughened side surface, on which the metal is precipitated, of the support substrate  100 . As a result, The adhesion between the conductive layer formed by electroless plating and the support substrate  100  can be maintained. Therefore, the yield of the semiconductor package can be improved. 
     The present invention is not limited to any of the above-described embodiments, and may be modified appropriately without departing from the gist of the present invention.