Patent Publication Number: US-2003222719-A1

Title: Asymmetric, voltage optimized, wideband common-gate bi-directional mmic amplifier

Description:
BACKGROUND OF THE INVENTION  
       [0001] 1. Field of the Invention  
       [0002] This invention relates generally to a bi-directional amplifier and, more particularly, to an asymmetric, voltage optimized, wideband common-gate bi-directional amplifier for a transceiver, where the amplifier is optimized for both low noise amplification and high power amplification.  
       [0003] 2. Discussion of the Related Art  
       [0004] Spacecraft-based surveillance and communications systems, such as satellite based radar systems, generally employ phased antenna arrays that require large apertures, on the order of 100 square meters or greater, to achieve the high spatial resolution necessary to support various communications protocols, such as GMTI, AMTI and SAR, known to those skilled in the art. Current technology and design approaches that support this large of a space-based phased array are generally impractical and expensive. For example, a phased antenna array operating at X-band (6-12 GHz) having a square aperture with side dimensions of ten meters, and taking into account the mutual coupling between adjacent radiation elements, can include up to 300,000 circuit elements. A typical spacecraft allocation of 20 kW of power and 10,000 pounds of payload would require each circuit element to consume no more than 50-100 mW of DC power and weigh less this 10-20 grams. Hence, the power and weight requirements are severe at the component level.  
       [0005] Each channel of a phased antenna array for these types of applications typically employs a transceiver module that processes both the signals received by the system and the signals transmitted by the system at different frequency bands. Each transceiver module generally has two separate signal amplification paths, one including a high power amplifier (HPA) for the transmit signal and one including a low noise amplifier (LNA) for the receive signal. The LNA typically has higher gain than the HPA because the receive signal has a very low intensity that is close to the noise floor. Four separate monolithic millimeter integrated chips (MMIC) are generally required to accommodate the amplification paths in each channel, one for the LNA, one for the HPA, and two for routing switches to switch the signal path between the transmit signal and the receive signal. The routing switches may be relays for low frequency applications or semiconductor switches, such as high electron mobility transistors (HEMT) or heterojunction bipolar transistors (HBT), for high frequency applications.  
       [0006] In a volume production environment, the high part count of the phased array complicates the manufacturing process and usually leads to undesired module rework. Further, the signal routing switches in the RF path incur losses that degrade the output power and the noise figure of the system affecting its performance. For example, the routing switch in front of the LNA may cause the noise to grow, which may not allow the system to detect the receive signal above the noise. Switch losses of this type may be on the order of 1-1.5 dB.  
       [0007] It is desirable to minimize the number of parts in a transceiver module, especially in spacecraft-based applications. To attain this goal, it has heretofore been known in the art to employ bi-directional amplifiers in each channel of a transceiver module, where the bi-directional amplifier amplifies both the transmit signals and the receive signals propagating in opposite directions. Because a bi-directional amplifier is used in this application, the routing switches normally required to route the receive signal to the LNA and the transmit signal to the HPA can be eliminated.  
       [0008] U.S. Pat. No. 5,821,813 issued to Batchelor et al. Oct. 13, 1998 discloses a bi-directional amplifier for this purpose. The &#39;813 bi-directional amplifier employs a field effect transistor that is connected in a common gate mode with the common terminal of each port of the amplifier and with the gate of the transistor. The source and drain terminals of the transistor are connected to a corresponding one of the ports through an impedance matching device. However, the &#39;813 bi-directional amplifier provides the same level of signal gain for the transmit signal and the receive signal. Thus, this bi-directional amplifier is not separately optimized for the transmit signals and the receive signals, and thus does not provide the best performance.  
       SUMMARY OF THE INVENTION  
       [0009] In accordance with the teachings of the present invention, a bi-directional amplifier is disclosed that has particular application for use in a transceiver module for amplifying both transmit signals and receive signals propagating in opposite directions. The amplifier includes first and second common gate field effect transistors (FETs) electrically coupled along a common transmission line. A first variable matching network is electrically coupled to the transmission line between a transmit signal input port and the first FET, and a second variable matching network is electrically coupled to the transmission line between a receive signal input port and the second FET. An interstage variable matching network is electrically coupled to the transmission line between the first and second FETs. A DC voltage regulator provides a DC bias signal to the matching networks and the FETs so that different signal amplifications and different impedance matching characteristics can be provided for the transmit signal and the receive signal.  
       [0010] Additional objects, advantages and features of the present invention will become apparent from the following description and appended claims, taken in conjunction with the accompanying drawings. 
     
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
     [0011]FIG. 1 is a schematic block diagram of a bi-directional amplifier for a transceiver, according to an embodiment of the present invention;  
     [0012]FIG. 2 is a schematic diagram of a variable matching network, including a tunable capacitor and inductor network, for the bi-directional amplifier shown in FIG. 1, according to an embodiment of the present invention; and  
     [0013]FIG. 3 is a schematic diagram of a variable matching network including a quarter-wave transform and diode coupled to ground for the bi-directional amplifier shown in FIG. 1, according to another embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS  
     [0014] The following discussion of the embodiments of the invention directed to a bi-directional amplifier is merely exemplary in nature, and is in no way intended to limit the invention or its applications or uses. For example, the bi-directional amplifier of the invention is described for use in a transceiver module. However, as will be appreciated by those skilled in the art, the bi-directional amplifier of the invention may have application in other circuits and systems for amplifying signals propagating in opposite directions.  
     [0015]FIG. 1 is a schematic block diagram of a bi-directional amplifier  10 , according to an embodiment of the present invention, that as application for use in a transceiver module. The various components of the amplifier  10  discussed below are all patterned and defined on a common MMIC. The transceiver module can be employed in each channel of a phased array antenna on a satellite used for radar applications. The bi-directional amplifier  10  provides suitable amplification and signal gain to a transmit signal applied to an input port  12  at one end of the amplifier  10  and a receive signal applied to an input port  14  at an opposite end of the amplifier  10 . As would be appreciated by those skilled in the art, the ports  12  and would be electrically coupled to suitable external digital processing circuitry (not shown). Since mode of operation for amplifier  10  is controlled via variation in DC bias voltages, a DC blocking capacitor  16  is implemented to isolate external circuits that are connected to input port  12 . DC blocking capacitor  18  next to the output port  14  is implemented for the same reason.  
     [0016] The bi-directional amplifier  10  includes a first field effect transistor (FET)  22  and a second FET  24  coupled to a transmission line  20  for amplifying the receive signals and transmit signals. In one embodiment, the transmission line  20  is a microstrip patterned on a substrate to have a width suitable for the various RF and DC bias signals discussed herein. The FETs  22  and  24  are common gate FETs, where the gate terminals are coupled to an RF ground. In an alternate embodiment, the FETs  22  and  24  can be other suitable amplifying devices, such as HEMTs. Two amplifying stages are employed to provide the desired noise figure and gain for the amplifier  10 , as would be well understood with those skilled in the art.  
     [0017] As will be discussed in more detail below, the amplifying characteristics of the FETs  22  and  24  are changed between the transmit mode and the receive mode by providing a different drain/source DC bias (V DS ) for the transmit mode and the receive mode. When the amplifier  10  is in the transmit mode and is amplifying the transmit signal, the FET  22  acts as a high gain stage to provide most of the amplification of the transmit signal, and the FET  24  acts as a power stage to achieve the required high power transmit signal. When the amplifier  10  is in the receive mode and is amplifying the receive signal, the FET  24  acts a low noise stage followed by the FET  22  which act as a gain stage. A DC voltage regulator  34  selectively provides the different V DS  bias signals to the FETs  22  and  24  for the transmit mode and the receive mode.  
     [0018] One of the source terminal or the drain terminal of the FET  22  is coupled to the input port  12  through a variable external matching network  28 , and one of the source terminal or the drain terminal of the FET  24  is electrically coupled to the input port  14  through a variable external matching network  30 . The other of the source terminal or the drain terminal of the FET  22  is coupled to the other of the source terminal or the drain terminal of the FET  24  through a variable interstage matching network  32 . As will be discussed in more detail below, the voltage regulator  34  selectively provides different DC bias voltages to the matching networks  28 ,  30  and  32  to allow them to be optimized for the desired impedance matching for both the transmit mode and the receive mode.  
     [0019] In the transmit mode, the variable matching network  28  matches the impedance of the transmitter circuitry coupled to the input port  12 , such as 50 ohms, to the low impedance of the input at the source terminal of the FET  22 . The variable matching network  32  matches the high impedance of the output at the drain terminal of the FET  22  to the low impedance at the input of the source terminal of the FET  24 . The variable matching network  30  matches the high impedance of the output at the drain terminal of the FET  28  to the impedance of the transmitter circuitry coupled to the port  14 .  
     [0020] In the receive mode, the variable matching network  30  matches the impedance of the receiver circuitry coupled to the input port  14 , such as 50 ohms, to the low impedance of the input at the source terminal of the FET  24 . The variable matching network  32  matches the high impedance of the output at the drain terminal of the FET  24  to the low impedance of the input at the source terminal of the FET  22 . The variable matching network  28  matches the high impedance of the output at the drain terminal of the FET  22  to the impedance of the receiver circuitry coupled to the port  12 .  
     [0021] In one embodiment, the voltage regulator  34  provides a set of DC bias signals to the FETs  22  and  24  and the matching networks  28 ,  30  and  32  when the amplifier  10  is in the transmit mode. The polarity and level of the DC bias signals to the FETs  22  and  24  and the matching networks  28 ,  30  and  32  are reversed and varied when the amplifier  10  is in the receive mode. The difference in polarity and level of bias signal voltages makes the amplifier  10  asymmetric. The polarity reversal of the bias signals causes the source terminal and the drain terminal of the FETs  22  and  24  to alternate for the transmit mode and the receive mode and thus change the directional of amplification. The voltage regulator  34  can be any voltage regulator design suitable for the purposes described herein. In this embodiment, the voltage regulator  34  converts a transistor-transistor logic (TTL) control signal to the required DC bias signals. Particularly, for a high TTL signal, the voltage regulator  34  provides the high level positive DC bias voltage for the transmit mode, and for a low TTL signal the voltage regulator  34  provides the low level negative DC bias voltage for the receive mode.  
     [0022] In one embodiment, the amplifier  10  is patterned on a single MMIC that is about 4 mm 2 . The transmission line  20  is a microstrip transmission line having suitable width and thickness for RF signals. DC bias lines are also microstrips having a suitable thickness and width for DC signals. In a particular transceiver module application in a phase array antenna, the amplifier  10  is positioned after the phase shifters in each channel to minimize excessive loss which may degrade transmit power output and receive noise figure. The amplifier  10  provides an asymmetric match to insure maximum power output in the transmit direction while enhancing low noise performance in the receive direction. The changing DC bias signal is varied to enhance amplifier performance, i.e., high voltage for power in the transmit mode, and low voltage for low noise operations in the receive mode.  
     [0023] The variable matching networks  28 ,  30  and  32  can be any suitable matching network for the purposes described herein, as long as they are variable to switch between the transmit mode and the receive mode. FIG. 2 is a schematic diagram of a matching network  40  that can be used for any or all of the matching networks  28 ,  30  and  32 . The matching network  40  includes an LC circuit  42  having a tunable capacitor  44  and a tunable inductor  46  electrically coupled together as shown. The RF transmit signal or the RF receive signal is applied to one of the network ports  48  or  50  in the matching network  40 , depending on its orientation in the amplifier  10 . The DC bias signal from the voltage regulator  34  controls the capacitance of the capacitor  44  and the inductance of the inductor  46  so that they can be changed for the transmit mode and the receive mode as discussed above.  
     [0024] The variable capacitor  44  and the variable inductor  46  can be any suitable device for the purposes described herein. In one embodiment, the capacitor  44  includes a piezoelectric substrate provided between the capacitor plates whose thickness changes when different voltage potentials are applied thereto, which changes the capacitance of the capacitor  44 . Likewise, the inductor  46  can be an element wound through a piezoelectric material, where a voltage potential applied to the piezoelectric material causes it to expand or contract, changing the mutual inductance of the inductor  46 .  
     [0025]FIG. 3 is a schematic diagram of a matching network  54  that also has application for the matching networks  28 ,  30  and  32  discussed above. The matching network  54  is a quarter wave transform matching network that includes a diode  56  coupled to ground through a resistor  58 . The resistor  58  is a current limiting resistor that limits the current through the diode  56 . The diode  56  is also coupled to a DC bias port  60  between a matching section  62  and a quarter wavelength matching section  64 . When a DC bias signal is applied to the port  60 , the diode  56  conducts, creating an open circuit to RF. Therefore, an RF signal applied to an input port  66  sees an open circuit, and is prevented from propagating through the matching sections  62  and  64  to an output port  68 . When no DC bias signal is applied to the port  60 , the width and length of the section  62  and  64  determine the impedance of the network  54 , which sets the impedance matching between the ports  66  and  68 . Thus, by setting the RF signal propagation characteristics of the sections  62  and  64 , the impedance of the matching network  54  can be provided. In one embodiment, the sections  62  and  64  are stepped sections that increase or decrease the impedance of the section with every step to provide the impedance matching.  
     [0026] The network  54  will be used in combination with another identical network  54  in each of the matching networks  28 ,  30  and  32 . When a DC bias signal is applied to one port  60  of the networks  54 , that network  54  will prevent the RF signal from propagating therethrough. The RF signal will propagate through the other network  54 . Therefore, by selectively providing the impedance matching characteristics of the sections  62  and  64 , the desired impedance matching can be provided by selecting which of the networks  54  the RF signals will propagate through. Thus, the DC bias signal is applied to one of the bias ports  60  when the amplifier  10  is in the transmit mode, and is applied to the other bias port  60  when the amplifier  10  is in the receive mode, so that the RF signal propagates through the matching network  54  that provides the desired impedance for the particular mode.  
     [0027] The foregoing discussion discloses and describes merely exemplary embodiments of the present invention. One skilled in the art will readily recognize from such discussion and from the accompanying drawings and claims, that various changes, modifications and variations can be made therein without departing from the spirit and scope of the invention as defined in the following claims.