Patent Publication Number: US-2023163090-A1

Title: Memory device

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application is based on and claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2021-0162600, filed on Nov. 23, 2021, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety. 
     FIELD 
     The inventive concept relates to a memory device. More particularly, the inventive concept relates to a three-dimensional memory device. 
     BACKGROUND 
     An electronic system requiring data storage may need a memory device capable of storing high-capacity data. Accordingly, methods capable of increasing data storage capacity of a memory device have been researched. For example, as one method of increasing data storage capacity of a memory device, a three-dimensional memory device having three-dimensionally arranged memory cells instead of two-dimensionally arranged memory cells has been proposed. 
     SUMMARY 
     The inventive concept provides a memory device having an increased storage capacity or yield. 
     According to an aspect of the inventive concept, there is provided a memory device including: a first structure and a second structure stacked on the first structure in a vertical direction, wherein the first structure includes: a first substrate; peripheral circuitry on the first substrate; an auxiliary memory cell array on the first substrate; a first insulating layer on the first substrate, the peripheral circuitry, and the auxiliary memory cell array; and a plurality of first bonding pads on the first insulating layer and electrically connected to the peripheral circuitry. The second structure includes: a second substrate; a main memory cell array on the second substrate; a second insulating layer on the second substrate and the main memory cell array; and a plurality of second bonding pads on the second insulating layer and electrically connected to the main memory cell array, wherein the plurality of first bonding pads are in contact with the plurality of second bonding pads, respectively. 
     According to another aspect of the inventive concept, there is provided a memory device including: a first structure and a second structure stacked on the first structure in a vertical direction, wherein the first structure includes: a first substrate; peripheral circuitry on the first substrate; at least one auxiliary memory cell array on the first substrate; a first insulating layer on the first substrate, the peripheral circuitry, and the at least one auxiliary memory cell array; and a plurality of first bonding pads on the first insulating layer and electrically connected to the peripheral circuitry. The second structure includes: a second substrate; a plurality of main memory cell arrays on the second substrate; a second insulating layer on the second substrate and the plurality of main memory cell arrays; and a plurality of second bonding pads on the second insulating layer and electrically connected to the plurality of main memory cell arrays, wherein the plurality of first bonding pads are in contact with the plurality of second bonding pads, respectively, and a number of the at least one auxiliary memory cell array is fewer than a number of the main memory cell arrays. 
     According to another aspect of the inventive concept, there is provided a memory device including: a first structure and a second structure stacked on the first structure in a vertical direction, wherein the first structure includes: a first substrate; peripheral circuitry on the first substrate; a first insulating layer on the first substrate and the peripheral circuitry; a second substrate on the first insulating layer; an auxiliary memory cell array on the second substrate; a second insulating layer on the second substrate and the auxiliary memory cell array; and a plurality of first bonding pads on the second insulating layer and electrically connected to the peripheral circuitry. The second structure includes: a third substrate; a main memory cell array on the third substrate; a third insulating layer on the third substrate and the main memory cell array; and a plurality of second bonding pads on the third insulating layer and electrically connected to the main memory cell array, wherein the plurality of first bonding pads are in contact with the plurality of second bonding pads, respectively. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Embodiments of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings in which: 
         FIG.  1    is a cross-sectional view illustrating a memory device according to an embodiment of the inventive concept; 
         FIG.  2    is a cross-sectional view illustrating a memory device according to an embodiment of the inventive concept; 
         FIG.  3    is a cross-sectional view illustrating a memory device according to an embodiment of the inventive concept; 
         FIG.  4    is a cross-sectional view illustrating a memory device according to an embodiment of the inventive concept; 
         FIG.  5    is a cross-sectional view illustrating a memory device according to an embodiment of the inventive concept; 
         FIG.  6    is a block diagram of an electronic system including a memory device, according to an embodiment of the inventive concept; 
         FIG.  7    is a perspective view of an electronic system including a memory device, according to an embodiment of the inventive concept; and 
         FIG.  8    is a cross-sectional view of a semiconductor package including a memory device, according to an embodiment of the inventive concept, taken along line II-IF of  FIG.  7   . 
     
    
    
     DETAILED DESCRIPTION OF EMBODIMENTS 
       FIG.  1    is a cross-sectional view illustrating a memory device  100  according to an embodiment of the inventive concept. 
     Referring to  FIG.  1   , the memory device  100  may include a first structure S 1  and a second structure S 2  stacked on the first structure S 1  in a vertical direction (e.g., in the Z-direction). That is, an upper surface of the first structure S 1  may be in contact with a lower surface of the second structure S 2 . Elements or structures that are described as “in contact” or “in contact with” other elements or structures may refer to direct physical contact, with no intervening elements or structures therebetween. The terms first, second, etc., may be used herein merely to distinguish one element or layer from another. 
     The first structure S 1  may include a first substrate  111 , peripheral circuitry (also referred to herein as a peripheral circuit(s)) PC, an auxiliary memory cell array MCA 1 , a first insulating layer  121 , and a plurality of first bonding pads  161 . The first structure S 1  may further include a second insulating layer  131 , a first interconnect structure  151 , and a plurality of first contacts  141 . 
     The first substrate  111  may include a semiconductor material such as a group IV semiconductor material, a group III-V semiconductor material, or a group II-VI semiconductor material. The group IV semiconductor material may include, for example, silicon (S 1 ), germanium (Ge), or SiGe. The group III-V semiconductor material may include, for example, gallium arsenide (GaAs), indium phosphide (InP), gallium phosphide (GaP), indium arsenide (InAs), indium antimonide (InSb), or indium gallium arsenide (InGaAs). The group II-VI semiconductor material may include, for example, zinc telluride (ZnTe) or cadmium Sulfide (CdS). 
     The peripheral circuit PC may be on the first substrate  111 . The peripheral circuit PC may include a plurality of transistors. The peripheral circuit PC may include, for example, a row decoder, a page buffer, a data input/output circuit, and a control logic. The peripheral circuit PC may further include various circuits such as a voltage generation circuit and an error correction circuit. 
     The auxiliary memory cell array MCA 1  may be on the first substrate  111 , for example, laterally adjacent the peripheral circuit PC. The auxiliary memory cell array MCA 1  may be a three-dimensional memory cell array. The auxiliary memory cell array MCA 1  may include a first stack structure SS 1  and a plurality of first channel structures CH 1  on the first substrate  111 . Although  FIG.  1    shows that the auxiliary memory cell array MCA 1  includes two first channel structures CH 1 , the number of first channel structures CH 1  included in the auxiliary memory cell array MCA 1  is not limited thereto. 
     The first stack structure SS 1  may include parts having a staircase shape. The first stack structure S S 1  may include a plurality of first interlayer insulating layers IL 1  and a plurality of first gate layers G 1  alternately stacked with each other on the first substrate  111 . That is, the first gate layers G 1  may be separated from each other by the first interlayer insulating layers IL 1 . Although  FIG.  1    shows that the first stack structure SS 1  includes four first gate layers G 1  and five first interlayer insulating layers ILL the numbers of first gate layers G 1  and first interlayer insulating layers IL 1  included in the first stack structure SS 1  are not limited thereto. 
     The first interlayer insulating layer IL 1  may include a silicon oxide (SiO 2 ), a silicon nitride (SiN), or a combination thereof. The first gate layer G 1  may include a conductive material such as tungsten (W), nickel (Ni), cobalt (Co), tantalum (Ta), a tungsten nitride (WN), a titanium nitride (TiN), a tantalum nitride (TaN), or a combination thereof. 
     Each first channel structure CH 1  may pass through the first stack structure SS 1  in the vertical direction (Z direction). Each first channel structure CH 1  may include a first channel layer CH 1   b , a first buried insulating layer CH 1   a , a first pad CH 1   d , and a first gate dielectric layer CH 1   c.    
     The first channel layer CH 1   b  may be in contact with the first substrate  111  and pass through the first stack structure SS 1  in the vertical direction (Z direction). The first channel layer CH 1   b  may have a hollow cylindrical shape. The first channel layer CH 1   b  may include polysilicon or polygermanium. 
     A space surrounded by the first channel layer CH 1   b  may be filled with the first buried insulating layer CH 1   a . The first buried insulating layer CH 1   a  may include, for example, an insulating material such as SiO 2 , SiN, or a combination thereof. In some embodiments, the first buried insulating layer CH 1   a  may be omitted. In this case, the first channel layer CH 1   b  may have a pillar shape. 
     The first pad CH 1   d  may be on the first buried insulating layer CH 1   a  and in contact with the first channel layer CH 1   b . The first pad CH 1   d  may include polysilicon, a metal, a metal nitride, or a combination thereof. The metal may include, for example, W, Ni, Co, Ta, or the like. 
     The first gate dielectric layer CH 1   c  may extend between the first channel layer CH 1   b  and the first stack structure SS 1 . The first gate dielectric layer CH 1   c  may include a tunneling dielectric layer, a charge storage layer, and a blocking dielectric layer sequentially stacked on the first channel layer CH 1   b . The tunneling dielectric layer may include SiO 2 , a hafnium oxide (HfO 2 ), an aluminum oxide (Al 2 O 3 ), a zirconium oxide (ZrO 2 ), a tantalum oxide (Ta 2 O 5 ), or a combination thereof. The charge storage layer may include SiN, a boron nitride (BN), or polysilicon. The blocking dielectric layer may include SiO 2 , SiN, HfO 2 , Al 2 O 3 , ZrO 2 , Ta 2 O 5 , or a combination thereof. 
     The first insulating layer  121  may cover the first substrate  111 , the peripheral circuit PC, and a side surface of the auxiliary memory cell array MCA 1 . The first insulating layer  121  may include SiO 2 , SiN, a low-k material, or a combination thereof. The low-k material may include, for example, fluorinated tetraethylorthosilicate (FTEOS), hydrogen silsesquioxane (HSQ), bis-benzocyclobutene (BCB), tetramethylorthosilicate (TMOS), octamethyleyclotetrasiloxane (OMCTS), hexamethyldisiloxane (HMDS), trimethylsilyl borate (TMSB), diacetoxyditertiarybutosiloxane (DADBS), trimethylsilil phosphate (TMSP), polytetrafluoroethylene (PTFE), tonen silazen (TOSZ), fluoride silicate glass (FSG), polypropylene oxide, carbon doped silicon oxide (CDO), organo silicate glass (OSG), silicon low-k (SiLK), amorphous fluorinated carbon, silica aerogel, silica xerogel, mesoporous silica, or a combination thereof. 
     The second insulating layer  131  may be on the first insulating layer  121  and cover an upper surface of the auxiliary memory cell array MCA 1 . The second insulating layer  131  may include SiO 2 , SiN, a low-k material, or a combination thereof. The first insulating layer  121  and the second insulating layer  131  of  FIG.  1    may be collectively referred to as a first insulating layer. 
     The plurality of first bonding pads  161  may be on the second insulating layer  131 . The plurality of first bonding pads  161  may include copper (Cu), Ni, W, aluminum (Al), gold (Au), titanium (Ti), TiN, or a combination thereof. 
     The first interconnect structure  151  may electrically connect the plurality of first bonding pads  161  to the peripheral circuit PC and electrically connect the peripheral circuit PC to the auxiliary memory cell array MCA 1 . The first interconnect structure  151  may include a plurality of conductive lines and a plurality of conductive vias. The plurality of conductive lines and the plurality of conductive vias may include, for example, Cu, W, Al, Au, silver (Ag), Ni, Ta, Ti, TaN, TiN, or a combination thereof. 
     The plurality of first contacts  141  nay electrically connect the peripheral circuit PC and the auxiliary memory cell array MCA 1  to the first interconnect structure  151 . The plurality of first contacts  141  may be surrounded by the first insulating layer  121 . The plurality of first contacts  141  may include, for example, Cu, W, Al, Au, Ag, Ni, Ta, Ti, TaN, TiN, or a combination thereof. 
     The second structure S 2  may include a second substrate  112 , a main memory cell array MCA 2 , a third insulating layer  122 , and a plurality of second bonding pads  162 . The second structure S 2  may further include a fourth insulating layer  132 , a second interconnect structure  152 , and a plurality of second contacts  142 . 
     The second substrate  112  may include a semiconductor material such as a group IV semiconductor material, a group III-V semiconductor material, or a group II-VI semiconductor material. The group IV semiconductor material may include, for example, S 1 , Ge, or SiGe. The group III-V semiconductor material may include, for example, GaAs, InP, GaP, InAs, InSb, or InGaAs. The group II-VI semiconductor material may include, for example, ZnTe or CdS. 
     The main memory cell array MCA 2  may be on the second substrate  112 . The main memory cell array MCA 2  may be a three-dimensional memory cell array. The main memory cell array MCA 2  may include a second stack structure SS 2  and a plurality of second channel structures CH 2  on the second substrate  112 . Although  FIG.  1    shows that the main memory cell array MCA 2  includes two second channel structures CH 2 , the number of second channel structures CH 2  included in the main memory cell array MCA 2  is not limited thereto. 
     The second stack structure SS 2  may include parts having a staircase shape. The second stack structure SS 2  may include a plurality of second interlayer insulating layers IL 2  and a plurality of second gate layers G 2  alternately stacked with each other on the second substrate  112 . That is, the second gate layers G 2  may be separated from each other by the second interlayer insulating layers IL 2 . Although  FIG.  1    shows that the second stack structure SS 2  includes eight second gate layers G 2  and nine second interlayer insulating layers IL 2 , the numbers of second gate layers G 2  and second interlayer insulating layers IL 2  included in the second stack structure SS 2  are not limited thereto. 
     The second interlayer insulating layer IL 2  may include SiO 2 , SiN, or a combination thereof. The second gate layer G 2  may include a conductive material such as W, Ni, Co, Ta, WN, TiN, TaN, or a combination thereof. 
     Each second channel structure CH 2  may pass through the second stack structure SS 2  in the vertical direction (Z direction). Each second channel structure CH 2  may include a second channel layer CH 2   b , a second buried insulating layer CH 2   a , a second pad CH 2   d , and a second gate dielectric layer CH 2   c.    
     The second channel layer CH 2   b  may be in contact with the second substrate  112  and pass through the second stack structure SS 2  in the vertical direction (Z direction). The second channel layer CH 2   b  may have a hollow cylindrical shape. The second channel layer CH 2   b  may include polysilicon or polygermanium. 
     A space surrounded by the second channel layer CH 2   b  may be filled with the second buried insulating layer CH 2   a . The second buried insulating layer CH 2   a  may include, for example, an insulating material such as SiO 2 , SiN, or a combination thereof. In some embodiments, the second buried insulating layer CH 2   a  may be omitted. In this case, the second channel layer CH 2   b  may have a pillar shape. 
     The second pad CH 2   d  may be on the second buried insulating layer CH 2   a  and in contact with the second channel layer CH 2   b . The second pad CH 2   d  may include polysilicon, a metal, a metal nitride, or a combination thereof. The metal may include, for example, W, Ni, Co, Ta, or the like. 
     The second gate dielectric layer CH 2   c  may extend between the second channel layer CH 2   b  and the second stack structure SS 2 . The second gate dielectric layer CH 2   c  may include a tunneling dielectric layer, a charge storage layer, and a blocking dielectric layer sequentially stacked on the second channel layer CH 2   b . The tunneling dielectric layer may include SiO 2 , HfO 2 , Al 2 O 3 , ZrO 2 , Ta 2 O 5 , or a combination thereof. The charge storage layer may include SiN, BN, or polysilicon. The blocking dielectric layer may include SiO 2 , SiN, HfO 2 , Al 2 O 3 , ZrO 2 , Ta 2 O 5 , or a combination thereof. 
     A volume of the auxiliary memory cell array MCA 1  may be less than a volume of the main memory cell array MCA 2 . For example, the auxiliary memory cell array MCA 1  may be physically smaller than the main memory cell array MCA 2  in one or more dimensions (e.g., along the X, Y, and/or Z directions). In some embodiments, a planar area of the auxiliary memory cell array MCA 1  (e.g., along a plane that is perpendicular to the vertical direction (Z direction)) may be less than a planar area of the main memory cell array MCA 2  perpendicular to the vertical direction (Z direction). In some embodiments, the number of memory cells in the auxiliary memory cell array MCA 1  may be fewer than the number of memory cells in the main memory cell array MCA 2 . A memory cell in the auxiliary memory cell array MCA 1  may be defined by the first gate layer G 1  and the first channel structure CH 1 . A memory cell in the main memory cell array MCA 2  may be defined by the second gate layer G 2  and the second channel structure CH 2 . In some embodiments, the number of first gate layers G 1  may be fewer than the number of second gate layers G 2 . 
     The third insulating layer  122  may cover a lower surface of the second substrate  112  and a side surface of the main memory cell array MCA 2 . The third insulating layer  122  may include SiO 2 , SiN, a low-k material, or a combination thereof. 
     The fourth insulating layer  132  may be on the third insulating layer  122  and cover a lower surface of the main memory cell array MCA 2 . The fourth insulating layer  132  may include SiO 2 , SiN, a low-k material, or a combination thereof. The third insulating layer  122  and the fourth insulating layer  132  of  FIG.  1    may be collectively referred to as a second insulating layer. 
     The plurality of second bonding pads  162  may be on the fourth insulating layer  132 . The plurality of second bonding pads  162  may include Cu, Ni, W, Al, Au, Ti, TiN, or a combination thereof. The plurality of first bonding pads  161  may be in contact with the plurality of second bonding pads  162 , respectively. By bonding the plurality of first bonding pads  161  with the plurality of second bonding pads  162 , the first structure S 1  and the second structure S 2  may be electrically and mechanically connected to each other. 
     The second interconnect structure  152  may electrically connect the plurality of second bonding pads  162  to the main memory cell array MCA 2 . The second interconnect structure  152  may include a plurality of conductive lines and a plurality of conductive vias. The plurality of conductive lines and the plurality of conductive vias may include, for example, Cu, W, Al, Au, Ag, Ni, Ta, Ti, TaN, TiN, or a combination thereof. 
     The plurality of second contacts  142  may electrically connect the main memory cell array MCA 2  to the second interconnect structure  152 . The plurality of second contacts  142  may be surrounded by the third insulating layer  122 . The plurality of second contacts  142  may include, for example, Cu, W, Al, Au, Ag, Ni, Ta, Ti, TaN, TiN, or a combination thereof. 
     In some embodiments, the auxiliary memory cell array MCA 1  may provide an additional storage capacity in addition to a storage capacity of the main memory cell array MCA 2 . Therefore, the memory device  100  may have an increased storage capacity provided by the collective storage capacity of the main memory cell array MCA 2  in combination with the auxiliary memory cell array MCA 1 . In some embodiments, the auxiliary memory cell array MCA 1  may be used to repair the main memory cell array MCA 2 , for example, by using one or more of the auxiliary memory cells to replace one or more of the main memory cells. Therefore, a yield of the memory device  100  may be improved. 
       FIG.  2    is a cross-sectional view illustrating a memory device  100 - 1  according to an embodiment of the inventive concept. Hereinafter, differences between the memory device  100  shown in  FIG.  1    and the memory device  100 - 1  shown in  FIG.  2    are described. 
     Referring to  FIG.  2   , the memory device  100 - 1  may include a first structure S 1 - 1  and a second structure S 2 - 1 . The first structure S 1 - 1  may include the first substrate  111 , the peripheral circuit PC, at least one auxiliary memory cell array MCA 1 , the first insulating layer  121 , and the plurality of first bonding pads  161 . The first structure S 1 - 1  may further include the second insulating layer  131 , the first interconnect structure  151 , and the plurality of first contacts  141 . 
     The second structure S 2 - 1  may include the second substrate  112 , a plurality of main memory cell arrays MCA 2 , the third insulating layer  122 , and the plurality of second bonding pads  162 . The second structure S 2 - 1  may further include the fourth insulating layer  132 , the second interconnect structure  152 , and the plurality of second contacts  142 . 
     The number of auxiliary memory cell arrays MCA 1  may be fewer than the number of main memory cell arrays MCA 2 . Although  FIG.  2    shows that the first structure S 1 - 1  includes one auxiliary memory cell array MCA 1  and the second structure S 2 - 1  includes two main memory cell arrays MCA 2 , the number of auxiliary memory cell arrays MCA 1  included in the first structure S 1 - 1  and the number of main memory cell arrays MCA 2  included in the second structure S 2 - 1  are not limited thereto. 
       FIG.  3    is a cross-sectional view illustrating a memory device  100 - 2  according to an embodiment of the inventive concept. Hereinafter, differences between the memory device  100  shown in  FIG.  1    and the memory device  100 - 2  shown in  FIG.  3    are described. 
     Referring to  FIG.  3   , the memory device  100 - 2  may include a first structure S 1 - 2  and a second structure S 2 - 2 . The first structure S 1 - 2  may include the first substrate  111 , the peripheral circuit PC, at least one auxiliary memory cell array MCA 1 , the first insulating layer  121 , and the plurality of first bonding pads  161 . The first structure S 1 - 2  may further include the second insulating layer  131 , the first interconnect structure  151 , and the plurality of first contacts  141 . 
     The second structure S 2 - 2  may include the second substrate  112 , a plurality of main memory cell arrays MCA 2 , the third insulating layer  122 , and the plurality of second bonding pads  162 . The second structure S 2 - 2  may further include the fourth insulating layer  132 , the second interconnect structure  152 , and the plurality of second contacts  142 . 
     The number of auxiliary memory cell arrays MCA 1  may be fewer than the number of main memory cell arrays MCA 2 . Although  FIG.  3    shows that the first structure S 1 - 2  includes one auxiliary memory cell array MCA 1  and the second structure S 2 - 2  includes two main memory cell arrays MCA 2 , the number of auxiliary memory cell arrays MCA 1  included in the first structure S 1 - 2  and the number of main memory cell arrays MCA 2  included in the second structure S 2 - 2  are not limited thereto. 
     In some embodiments, a planar area of each auxiliary memory cell array MCA 1  perpendicular to the vertical direction (Z direction) may be equal to a planar area of each main memory cell array MCA 2  perpendicular to the vertical direction (Z direction). In some embodiments, a volume of each auxiliary memory cell array MCA 1  may be equal to a volume of each main memory cell array MCA 2 . In some embodiments, the number of memory cells in each auxiliary memory cell array MCA 1  may be equal to the number of memory cells in each main memory cell array MCA 2 . In some embodiments, the number of first gate layers G 1  in each auxiliary memory cell array MCA 1  may be equal to the number of second gate layers G 2  in each main memory cell array MCA 2 . 
       FIG.  4    is a cross-sectional view illustrating a memory device  100 - 3  according to an embodiment of the inventive concept. Hereinafter, differences between the memory device  100  shown in  FIG.  1    and the memory device  100 - 3  shown in  FIG.  4    are described. 
     Referring to  FIG.  4   , the memory device  100 - 3  may include a first structure S 1 - 3  and a second structure S 2 - 3 . 
     The first structure S 1 - 3  may include a first substrate  111 - 1 , the peripheral circuit PC, a first insulating layer  121 - 1 , a second substrate  111 - 2 , the auxiliary memory cell array MCA 1 , a second insulating layer  121 - 2 , and the plurality of first bonding pads  161 . The first structure S 1 - 3  may further include a plurality of first contacts  141 - 1 , a first interconnect structure  151 - 1 , a third insulating layer  131 - 2 , a second interconnect structure  151 - 2 , and a plurality of second contacts  141 - 2 . 
     The first substrate  111 - 1  may include a semiconductor material such as a group IV semiconductor material, a group III-V semiconductor material, or a group II-VI semiconductor material. The group IV semiconductor material may include, for example, S 1 , Ge, or SiGe. The group III-V semiconductor material may include, for example, GaAs, InP, GaP, InAs, InSb, or InGaAs. The group II-VI semiconductor material may include, for example, ZnTe or CdS. The peripheral circuit PC may be on the first substrate  111 - 1 . 
     The first insulating layer  121 - 1  may cover the first substrate  111 - 1  and the peripheral circuit PC. The first insulating layer  121 - 1  may include SiO 2 , SiN, a low-k material, or a combination thereof. 
     The first interconnect structure  151 - 1  may be inside the first insulating layer  121 - 1 . The first interconnect structure  151 - 1  may include a plurality of conductive lines and a plurality of conductive vias. The plurality of conductive lines and the plurality of conductive vias may include, for example, Cu, W, Al, Au, Ag, Ni, Ta, Ti, TaN, TiN, or a combination thereof. 
     The plurality of first contacts  141 - 1  may connect the first interconnect structure  151 - 1  to the peripheral circuit PC. The plurality of first contacts  141 - 1  may be surrounded by the first insulating layer  121 - 1 . The plurality of first contacts  141 - 1  may include, for example, Cu, W, Al, Au, Ag, Ni, Ta, Ti, TaN, TiN, or a combination thereof. 
     The second substrate  111 - 2  may be on the first insulating layer  121 - 1 , for example, opposite to and stacked on the first substrate  111 - 1  in the vertical direction (Z-direction). The second substrate  111 - 2  may include a semiconductor material such as a group IV semiconductor material, a group III-V semiconductor material, or a group II-VI semiconductor material. The group IV semiconductor material may include, for example, S 1 , Ge, or SiGe. The group III-V semiconductor material may include, for example, GaAs, InP, GaP, InAs, InSb, or InGaAs. The group II-VI semiconductor material may include, for example, ZnTe or CdS. The auxiliary memory cell array MCA 1  may be on the second substrate  111 - 2 , for example, stacked on the peripheral circuit PC in the vertical direction (Z direction). 
     The second insulating layer  121 - 2  may cover an upper surface of the second substrate  111 - 2  and a side surface of the auxiliary memory cell array MCA 1 . The second insulating layer  121 - 2  may include SiO 2 , SiN, a low-k material, or a combination thereof. 
     The third insulating layer  131 - 2  may be on the second insulating layer  121 - 2  and cover a lower surface of the auxiliary memory cell array MCA 1 . The third insulating layer  131 - 2  may include SiO 2 , SiN, a low-k material, or a combination thereof. The second insulating layer  121 - 2  and the third insulating layer  131 - 2  of  FIG.  4    may be collectively referred to as a second insulating layer. 
     The second interconnect structure  151 - 2  may electrically connect the plurality of first bonding pads  161  to the peripheral circuit PC and electrically connect the peripheral circuit PC to the auxiliary memory cell array MCA 1 . The second interconnect structure  151 - 2  may include a plurality of conductive lines and a plurality of conductive vias. The plurality of conductive lines and the plurality of conductive vias may include, for example, Cu, W, Al, Au, Ag, Ni, Ta, Ti, TaN, TiN, or a combination thereof. 
     The plurality of second contacts  141 - 2  may electrically connect the first interconnect structure  151 - 1  and the auxiliary memory cell array MCA 1  to the second interconnect structure  151 - 2 . The plurality of second contacts  141 - 2  may be surrounded by the second insulating layer  121 - 2 . The plurality of second contacts  141 - 2  may include, for example, Cu, W, Al, Au, Ag, Ni, Ta, Ti, TaN, TiN, or a combination thereof. 
     The plurality of first bonding pads  161  may be on the third insulating layer  131 - 2 . The plurality of first bonding pads  161  may include Cu, Ni, W, Al, Au, Ti, TiN, or a combination thereof. 
     The second structure S 2 - 3  may include a third substrate  112 - 3 , the main memory cell array MCA 2 , a fourth insulating layer  122 - 3 , and the plurality of second bonding pads  162 . The second structure S 2 - 3  may further include a fifth insulating layer  132 - 3 , a third interconnect structure  152 - 3 , and a plurality of third contacts  142 - 3 . 
     The third substrate  112 - 3  may include a semiconductor material such as a group IV semiconductor material, a group III-V semiconductor material, or a group II-VI semiconductor material. The group IV semiconductor material may include, for example, S 1 , Ge, or SiGe. The group III-V semiconductor material may include, for example, GaAs, InP, GaP, InAs, InSb, or InGaAs. The group II-VI semiconductor material may include, for example, ZnTe or CdS. The main memory cell array MCA 2  may be on the third substrate  112 - 3 . 
     The fourth insulating layer  122 - 3  may cover a lower surface of the third substrate  112 - 3  and the side surface of the main memory cell array MCA 2 . The fourth insulating layer  122 - 3  may include SiO 2 , SiN, a low-k material, or a combination thereof. 
     The fifth insulating layer  132 - 3  may be on the fourth insulating layer  122 - 3 . The fifth insulating layer  132 - 3  may cover the lower surface of the main memory cell array MCA 2 . The fifth insulating layer  132 - 3  may include SiO 2 , SiN, a low-k material, or a combination thereof. The fourth insulating layer  122 - 3  and the fifth insulating layer  132 - 3  of  FIG.  4    may be collectively referred to as a third insulating layer. 
     The third interconnect structure  152 - 3  may electrically connect the main memory cell array MCA 2  to the plurality of second bonding pads  162 . The third interconnect structure  151 - 3  may include a plurality of conductive lines and a plurality of conductive vias. The plurality of conductive lines and the plurality of conductive vias may include, for example, Cu, W, Al, Au, Ag, Ni, Ta, Ti, TaN, TiN, or a combination thereof. 
     The plurality of third contacts  142 - 3  may electrically connect the third interconnect structure  152 - 3  to the main memory cell array MCA 2 . The plurality of third contacts  142 - 3  may be surrounded by the fourth insulating layer  122 - 3 . 
     The plurality of second bonding pads  162  may be on the fifth insulating layer  132 - 3 . The plurality of second bonding pads  162  may include Cu, Ni, W, Al, Au, Ti, TiN, or a combination thereof. The plurality of first bonding pads  161  may be in contact with the plurality of second bonding pads  162 , respectively. By bonding the plurality of first bonding pads  161  with the plurality of second bonding pads  162 , the first structure S 1 - 3  and the second structure S 2 - 3  may be electrically and mechanically connected to each other. 
       FIG.  5    is a cross-sectional view illustrating a memory device  100 - 4  according to an embodiment of the inventive concept. Hereinafter, differences between the memory device  100 - 3  shown in  FIG.  4    and the memory device  100 - 4  shown in  FIG.  5    are described. 
     Referring to  FIG.  5   , the memory device  100 - 4  may include a first structure S 1 - 4  and a second structure S 2 - 4 . 
     The first structure S 1 - 4  may include the first substrate  111 - 1 , the peripheral circuit PC, the first insulating layer  121 - 1 , the second substrate  111 - 2 , at least one auxiliary memory cell array MCA 1 , the second insulating layer  121 - 2 , and the plurality of first bonding pads  161 . The first structure S 1 - 4  may further include the plurality of first contacts  141 - 1 , the first interconnect structure  151 - 1 , the third insulating layer  131 - 2 , the second interconnect structure  151 - 2 , and the plurality of second contacts  141 - 2 . 
     The second structure S 2 - 4  may include the third substrate  112 - 3 , a plurality of main memory cell arrays MCA 2 , the fourth insulating layer  122 - 3 , and the plurality of second bonding pads  162 . The second structure S 2 - 4  may further include the fifth insulating layer  132 - 3 , the third interconnect structure  152 - 3 , and the plurality of third contacts  142 - 3 . 
     The number of auxiliary memory cell arrays MCA 1  may be fewer than the number of main memory cell arrays MCA 2 . Although  FIG.  5    shows that the first structure S 1 - 4  includes one auxiliary memory cell array MCA 1  and the second structure S 2 - 4  includes two main memory cell arrays MCA 2 , the number of auxiliary memory cell arrays MCA 1  included in the first structure S 1 - 4  and the number of main memory cell arrays MCA 2  included in the second structure S 2 - 4  are not limited thereto. 
     In some embodiments, a planar area of each auxiliary memory cell array MCA 1  perpendicular to the vertical direction (Z direction) may be equal to a planar area of each main memory cell array MCA 2  perpendicular to the vertical direction (Z direction). In some embodiments, a volume of each auxiliary memory cell array MCA 1  may be equal to a volume of each main memory cell array MCA 2 . In some embodiments, the number of memory cells in each auxiliary memory cell array MCA 1  may be equal to the number of memory cells in each main memory cell array MCA 2 . In some embodiments, the number of first gate layers G 1  in each auxiliary memory cell array MCA 1  may be equal to the number of second gate layers G 2  in each main memory cell array MCA 2 . 
       FIG.  6    is a block diagram of an electronic system  1000  including a memory device  1100 , according to an embodiment of the inventive concept. 
     Referring to  FIG.  6   , the electronic system  1000  according to embodiments of the inventive concept may include the memory device  1100  and a controller  1200  connected to the memory device  1100 . The electronic system  1000  may be a storage device including one or more memory devices  1100 , or an electronic device including a storage device. For example, the electronic system  1000  may be a solid state drive (SSD) device, a universal serial bus (USB) device, a computing system, a medical device, or a communication device including at least one memory device  1100 . 
     The memory device  1100  may be a three-dimensional NAND flash memory device. For example, the memory device  1100  may include at least one of the memory devices  100 ,  100 - 1 ,  100 - 2 ,  100 - 3 , and  100 - 4  shown in  FIGS.  1  to  5   . The memory device  1100  may communicate with the controller  1200  through input-output pads  1101  electrically connected to a control logic in the peripheral circuit PC (see  FIGS.  1  to  5   ). 
     The controller  1200  may include a processor  1210 , a NAND controller  1220 , and a host interface  1230 . According to embodiments, the electronic system  1000  may include a plurality of memory devices  1100 , and in this case, the controller  1200  may control the plurality of memory devices  1100 . 
     The processor  1210  may control a general operation of the electronic system  1000  including the controller  1200 . The processor  1210  may operate according to certain firmware and control the NAND controller  1220  to access the memory device  1100 . The NAND controller  1220  may include a NAND interface  1221  configured to process communication with the memory device  1100 . Through the NAND interface  1221 , a control command for controlling the memory device  1100 , data to be written in the memory device  1100 , data read from the memory device  1100 , and the like may be transferred. The host interface  1230  may provide a communication function between the electronic system  1000  and an external host. When a control command is received from the external host through the host interface  1230 , the processor  1210  may control the memory device  1100  in response to the control command. 
       FIG.  7    is a perspective view of the electronic system  1000  including a memory device, according to an embodiment of the inventive concept. 
     Referring to  FIG.  7   , the electronic system  1000  may include a main substrate  2001  and a controller  2002 , a semiconductor package  2003 , and dynamic random access memory (DRAM)  2004  on the main substrate  2001 . The semiconductor package  2003  and the DRAM  2004  may be connected to the controller  2002  by a plurality of wiring patterns  2005  formed on the main substrate  2001 . 
     The main substrate  2001  may include a connector  2006  including a plurality of pins coupled to an external host. The number of pins and the arrangement of the pins in the connector  2006  may vary according to a communication interface between the electronic system  1000  and the external host. In example embodiments, the electronic system  1000  may communicate with the external host according to any one of interfaces such as a USB interface, a peripheral component interconnect express (PCI-Express) interface, a serial advanced technology attachment (SATA) interface, and an M-Phy interface for a universal flash storage (UFS). In example embodiments, the electronic system  1000  may operate by power received from the external host through the connector  2006 . The electronic system  1000  may further include a power management integrated circuit (PMIC) configured to distribute the power received from the external host to the controller  2002  and the semiconductor package  2003 . 
     The controller  2002  may write or read data in or from the semiconductor package  2003  and improve an operating speed of the electronic system  1000 . 
     The DRAM  2004  may be a buffer memory configured to mitigate a speed difference between the semiconductor package  2003 , which is a data storage space, and the external host. The DRAM  2004  included in the electronic system  1000  may operate as a kind of cache memory and provide a space in which data is temporarily stored in a control operation performed on the semiconductor package  2003 . When the DRAM  2004  is included in the electronic system  1000 , the controller  2002  may further include a DRAM controller configured to control the DRAM  2004  in addition to a NAND controller configured to control the semiconductor package  2003 . 
     The semiconductor package  2003  may include first and second semiconductor packages  2003   a  and  2003   b  separated from each other. Each of the first and second semiconductor packages  2003   a  and  2003   b  may include a plurality of semiconductor chips  2200 . Each of the first and second semiconductor packages  2003   a  and  2003   b  may include a package substrate  2100 , the plurality of semiconductor chips  2200  on the package substrate  2100 , an adhesive layer  2300  beneath each of the plurality of semiconductor chips  2200 , a plurality of connection structures  2400  electrically connecting the plurality of semiconductor chips  2200  to the package substrate  2100 , and a molding layer  2500  covering the plurality of semiconductor chips  2200  and the plurality of connection structures  2400  on the package substrate  2100 . 
     The package substrate  2100  may be a printed circuit board including a plurality of package upper pads  2130 . Each of the plurality of semiconductor chips  2200  may include input-output pads  2210 . The input-output pads  2210  may correspond to the input-output pads  1101  of  FIG.  6   . Each of the plurality of semiconductor chips  2200  may include at least one of the memory devices  100 ,  100 - 1 ,  100 - 2 ,  100 - 3 , and  100 - 4  shown in  FIGS.  1  to  5   . 
     In example embodiments, the plurality of connection structures  2400  may be bonding wires electrically connecting the input-output pads  2210  to the plurality of package upper pads  2130 . Therefore, in the first and second semiconductor packages  2003   a  and  2003   b , the plurality of semiconductor chips  2200  may be electrically connected to each other by a bonding wire scheme and electrically connected to the plurality of package upper pads  2130  of the package substrate  2100 . According to embodiments, in the first and second semiconductor packages  2003   a  and  2003   b , the plurality of semiconductor chips  2200  may be electrically connected to each other through a connection structure including through silicon vias (TSVs) instead of the plurality of connection structures  2400  of the bonding wire scheme. 
     In example embodiments, the controller  2002  and the plurality of semiconductor chips  2200  may be included in one package. In example embodiments, the controller  2002  and the plurality of semiconductor chips  2200  may be mounted on a separate interposer substrate other than the main substrate  2001 , and the controller  2002  and the plurality of semiconductor chips  2200  may be connected to each other through wirings formed on the interposer substrate. 
       FIG.  8    is a cross-sectional view of the semiconductor package  2003  including a memory device, according to an embodiment of the inventive concept, taken along line of  FIG.  7   . 
     Referring to  FIG.  8   , in the semiconductor package  2003 , the package substrate  2100  may be a printed circuit board. The package substrate  2100  may include a package substrate body part  2120 , the plurality of package upper pads  2130  (see  FIG.  7   ) on an upper surface of the package substrate body part  2120 , a plurality of lower pads  2125  arranged on or exposed through a lower surface of the package substrate body part  2120 , and a plurality of internal wirings  2135  inside the package substrate body part  2120  to electrically connect the plurality of package upper pads  2130  to the plurality of lower pads  2125 . The plurality of lower pads  2125  may be connected, through a plurality of conductive connection parts  2800 , to the plurality of wiring patterns  2005  on the main substrate  2001  of the electronic system  1000  shown in  FIG.  7   . Each of the plurality of semiconductor chips  2200  may include at least one of the memory devices  100 ,  100 - 1 ,  100 - 2 ,  100 - 3 , and  100 - 4  shown in  FIGS.  1  to  5   . 
     While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the scope of the following claims.