Patent Publication Number: US-11640785-B1

Title: Pixel driving device

Description:
RELATED APPLICATION 
     This application claims priority to Taiwan Application Serial Number 111100471, filed on Jan. 5, 2022, which is herein incorporated by reference in its entirety. 
     BACKGROUND 
     Field of Invention 
     The present disclosure relates to an electronic device. More particularly, the present disclosure relates to a pixel driving device. 
     Description of Related Art 
     In conventional pixel driving devices, threshold voltages of driving transistors are different, resulting in current differences, which in turn lead to brightness differences and uneven display images of pixel driving devices. 
     In addition, a driving current required for micro light emitting devices (μ LED) in conventional pixel driving devices to emit light is relatively large. When a driving current flows through a path between two power supply voltages, a voltage difference is too large to generate a driving current difference, which in turn lead to differences in brightness and increased power consumption of a pixel driving device. 
     Furthermore, based on a structure of conventional pixel driving device, if an optical sensor is added to a pixel driving device, a pixel driving device will be too complicated and difficult to implement. 
     For the foregoing reason, there is a need to provide some other circuits to solve the problems of the prior art. 
     SUMMARY 
     One aspect of the present disclosure provides a pixel driving device. The pixel driving device includes a driving transistor, a pixel driving circuit, an optical sensor circuit, and a reset and reading circuit. A first end of the driving transistor is connected to a first node. A control end of the driving transistor is connected to a second node. The driving transistor is configured to control a light emitting device. The pixel driving circuit is connected to the driving transistor, the first node, and the second node, and is configured to receive a first sweep signal, a second sweep signal, and a driving signal. The pixel driving circuit is configured to reset the first node and the second node according to the first sweep signal. The pixel driving circuit is configured to compensate the second node according to the second sweep signal. The pixel driving circuit is configured to control the driving transistor so as to drive the light emitting device according to the driving signal. The optical sensor circuit includes a third node. The optical sensor circuit is configured to receive the driving signal to reset the third node to a voltage level of the driving signal. The optical sensor circuit is configured to perform a sensing process to generate a light sensing signal. The reset and reading circuit is connected to the pixel driving circuit, the optical sensor circuit, and the control end of the driving transistor. The reset and reading circuit is configured to receive a reset and reading signal so as to reset the pixel driving circuit and read out the light sensing signal of the optical sensor circuit at the same time. 
     Another aspect of the present disclosure provides a pixel driving device. The pixel driving device includes a driving transistor, a pixel driving circuit, and an optical sensor circuit. A first end of the driving transistor is connected to a first node. A control end of the driving transistor is connected to a second node. The driving transistor is configured to control a light emitting device. The pixel driving circuit is configured to receive a first sweep signal, a second sweep signal, a driving signal, and a reset and reading signal. The pixel driving circuit is configured to reset the first node and the second node according to the first sweep signal. The pixel driving circuit is configured to compensate the second node according to the second sweep signal. The pixel driving circuit is configured to control the driving transistor so as to drive the light emitting device according to the driving signal. The pixel driving circuit is configured to turn off the driving transistor according to the reset and reading signal. The optical sensor circuit is connected to the pixel driving circuit. The optical sensor circuit is configured to receive the driving signal and the reset and reading signal. The optical sensor circuit is configured to perform a sensing process so as to a light sensing signal. The optical sensor circuit is configured to output the light sensing signal to a readout line of the pixel driving device according to the reset and reading signal. 
     These and other aspects of the present disclosure will become apparent from the following description of the preferred embodiment taken in conjunction with the following drawings, although variations and modifications therein may be effected without departing from the spirit and scope of the novel concepts of the disclosure. 
     It is to be understood that both the foregoing general description and the following detailed description are by examples, and are intended to provide further explanation of the present disclosure as claimed. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The present disclosure can be more fully understood by reading the following detailed description of the embodiment, with reference made to the accompanying drawings as follows: 
         FIG.  1    depicts a schematic diagram of a pixel driving device according to some embodiments of the present disclosure; 
         FIG.  2    depicts a schematic diagram of a signal timing of a pixel driving device according to some embodiments of the present disclosure; 
         FIG.  3    depicts a schematic diagram of a circuit state of a pixel driving device according to some embodiments of the present disclosure; 
         FIG.  4    depicts a schematic diagram of a circuit state of a pixel driving device according to some embodiments of the present disclosure; 
         FIG.  5    depicts a schematic diagram of a circuit state of a pixel driving device according to some embodiments of the present disclosure; 
         FIG.  6    depicts a schematic diagram of a circuit state of a pixel driving device according to some embodiments of the present disclosure; 
         FIG.  7    depicts a schematic diagram of a pixel driving device according to some embodiments of the present disclosure; 
         FIG.  8    depicts a schematic diagram of a pixel driving device according to some embodiments of the present disclosure; and 
         FIG.  9    depicts a schematic diagram of a pixel driving device according to some embodiments of the present disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     Reference will now be made in detail to the present embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts. 
     The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present disclosure. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. 
     Furthermore, it should be understood that the terms, “comprising”, “including”, “having”, “containing”, “involving” and the like, used herein are open-ended, that is, including but not limited to. 
     The terms used in this specification and claims, unless otherwise stated, generally have their ordinary meanings in the art, within the context of the disclosure, and in the specific context where each term is used. Certain terms that are used to describe the disclosure are discussed below, or elsewhere in the specification, to provide additional guidance to the practitioner skilled in the art regarding the description of the disclosure. 
       FIG.  1    depicts a schematic diagram of a pixel driving device  100  according to some embodiments of the present disclosure. In some embodiments, please refer to  FIG.  1   , the pixel driving device  100  includes a driving transistor DT 1 , a pixel driving circuit  110 , an optical sensor circuit  120 , and a reset and reading circuit  130 . 
     In some embodiments, please start form a top end and a right end of each of an element shown in the figure as a first end. A first end of the driving transistor DT 1  is connected to a first node N 1 . A control end driving transistor DT 1  is connected to a second node N 2 . The driving transistor DT 1  is configured to control a light emitting device LED. The pixel driving circuit  110  is connected to driving transistor DT 1 , the first node N 1 , the second node N 2 , and is configured to receive first sweep signal S 1 , a second sweep signal S 2 , and a driving signal EM. 
     Then, the pixel driving circuit  110  is configured to reset the first node N 1  and the second node N 2  according to the first sweep signal S 1 . The pixel driving circuit  110  is configured to compensate the second node N 2  according to the second sweep signal S 2 . The pixel driving circuit  110  is configured to control the driving transistor DT 1  so as to drive the light emitting device LED according to the driving signal EM. 
     Furthermore, the optical sensor circuit  120  includes a third node N 3 . The optical sensor circuit  120  is configured to receive the driving signal EM to reset the third node N 3  to a voltage level of the driving signal EM. 
     The reset and reading circuit  130  is connected to the pixel driving circuit  110 , the optical sensor circuit  120 , and the control end of the driving transistor DT 1 . Then, the reset and reading circuit  130  is configured to receive a reset and reading signal RR so as to reset the pixel driving circuit  110  and read out the light sensing signal of the optical sensor circuit  120  at the same time. 
     In some embodiments, the pixel driving circuit  110  includes a reset circuit  111 , a compensation circuit  112 , and a driving circuit  113 . The reset circuit  111  is configured to receive the first sweep signal S 1 . The reset circuit  111  is configured to reset the first node N 1  and the second node N 2  according to the first sweep signal S 1 . 
     Furthermore, the compensation circuit  112  is connected to the reset circuit  111 . The compensation circuit  112  is configured to receive the second sweep signal S 2 . The compensation circuit  112  is configured to compensate the second node N 2  so as to control the driving transistor DT 1  to compensate the first node N 1  according to the second sweep signal S 2 . 
     Then, the driving circuit  113  is connected to the reset circuit  111  and the compensation circuit  112 . The driving circuit  113  is configured to receive the EM. The driving circuit  113  is configured to control the driving transistor DT 1  so as to drive the light emitting device LED according to the driving signal EM. 
     In some embodiments, the driving transistor DT 1  includes a first end, a second end, and a control end (e.g. a gate terminal of the driving transistor DT 1 ). The first end of the driving transistor DT 1  is connected to the first node N 1 , the second end of the driving transistor DT 1  is configured to receive a power supply voltage VSS. The control end of the driving transistor DT 1  is connected to the second node N 2 . 
     In some embodiments, in order to facilitate the understanding of an operation of the pixel driving device  100  shown in  FIG.  1   , please refer to  FIG.  2    together,  FIG.  2    depicts a schematic diagram of a signal timing of a pixel driving device  100  according to some embodiments of the present disclosure. The reset circuit  111  is configured to receive the first sweep signal S 1  to reset the first node N 1  and the second node N 2  in a first stage I 1 . The compensation circuit  112  is configured to compensate the second node N 2  so as to control the driving transistor DT 1  to compensate the first node N 1  according to the second sweep signal S 2  in a second stage I 2 . The driving circuit  113  is configured to control the driving transistor DT 1  so as to drive the light emitting device LED according to the driving signal EM in a third stage I 3 . 
     In some embodiments, the optical sensor circuit  120  is configured to reset the third node N 3  of the optical sensor circuit  120  according to the second sweep signal S 2  in the second stage I 2 . The optical sensor circuit  120  is configured to perform a sensing process so as to generate the light sensing signal in the third stage I 3 . 
     In some embodiments, the reset and reading circuit  130  is configured to reset the pixel driving circuit  110  and read out the light sensing signal sensed by the optical sensor circuit  120  in the third stage I 3  according to the reset and reading signal RR in a fourth stage I 4 . 
     In some embodiments, please refer to  FIG.  1   , the reset circuit  111  includes the first node N 1 , a first capacitor C 1 , a first transistor T 1 , a second transistor T 2 , and a third transistor T 3 . The first capacitor C 1  includes a first end and a second end. The first end of the first capacitor C 1  is connected to the first node N 1 . 
     In addition, please refer to  FIG.  1    and  FIG.  2   , the first transistor T 1  includes a first end, a second end, and a control end (e.g. a gate terminal of the first transistor T 1 ). The first end of the first transistor T 1  is connected to the second node N 2 . The second end of the first transistor T 1  is configured to receive a first high reference voltage source V REFH . The control end of the first transistor T 1  is configured to receive the first sweep signal S 1  in the first stage I 1 . The first transistor T 1  is configured to reset the second node N 2  in response to the first sweep signal S 1 . 
     Additionally, the second transistor T 2  includes a first end, a second end, and a control end (e.g. a gate terminal of the second transistor T 2 ). The first end of the second transistor T 2  is configured to receive a first low reference voltage source V REFH . The second end of the second transistor T 2  is connected to the second end of the first capacitor C 1 . The control end of the second transistor T 2  is configured to receive the first sweep signal S 1  in the first stage I 1 . The second transistor T 2  is configured to reset the second end of the first capacitor C 1  in response to the first sweep signal S 1 . 
     Furthermore, the third transistor T 3  includes a first end, a second end, and a control end (e.g. a gate terminal of the third transistor T 3 ). The first end of the third transistor T 3  is configured to receive the first high reference voltage source V REFH . The second end of the third transistor T 3  is connected to the first node N 1 . The control end of the third transistor T 3  is configured to receive the first sweep signal S 1  in the first stage I 1 . The third transistor T 3  is configured to reset the first node N 1  in response to the first sweep signal S 1 . 
     In some embodiments, please refer to  FIG.  1   , the compensation circuit  112  includes a fourth node N 4 , a fourth transistor T 4 , and a fifth transistor T 5 . The second end of the first capacitor C 1  of the reset circuit  111  is connected to the fourth node N 4 . 
     In addition, please refer to  FIG.  1    and  FIG.  2   , the fourth transistor T 4  includes a first end, a second end, and a control end (e.g. a gate terminal of the fourth transistor T 4 ). The first end of the fourth transistor T 4  is configured to receive a data voltage source V DATA . The second end of the fourth transistor T 4  is connected to the fourth node N 4 . The control end of the fourth transistor T 4  is configured to receive the second sweep signal S 2  in the second stage I 2 . The fourth transistor T 4  is configured to compensate the fourth node N 4  in response to the second sweep signal S 2 . It should be noted that the data voltage source V DATA  represents a voltage delivered by a data line of the pixel driving device  100 . 
     Additionally, the fifth transistor T 5  includes a first end, a second end, and a control end (e.g. a gate terminal of the fifth transistor T 5 ). The first end of the fifth transistor T 5  is configured to receive a first reference voltage source V REF . The second end of the fifth transistor T 5  is connected to the second node N 2 . The control end of the fifth transistor T 5  is configured to receive the second sweep signal S 2  in the second stage I 2  The fifth transistor T 5  is configured to compensate the second node N 2  in response to the second sweep signal S 2  in the second stage I 2 . 
     In some embodiments, please refer to  FIG.  1    and  FIG.  2   , the driving circuit  113  includes the second node N 2  and a sixth transistor T 6 . The sixth transistor T 6  includes a first end, a second end, and a control end (e.g. a gate terminal of the sixth transistor T 6 ). The first end of the sixth transistor T 6  is connected to the fourth node N 4 . The second end of the sixth transistor T 6  is connected to second node N 2 . The control end of the sixth transistor T 6  is configured to receive the driving signal EM in the third stage I 3 . The sixth transistor T 6  is configured to control the driving transistor DT 1  to drive the light emitting device LED in response to the driving signal EM. 
     In some embodiments, please refer to  FIG.  1    and  FIG.  2   , the reset and reading circuit  130  includes a first reset transistor T 7  and a read transistor T 8 . 
     Then, the first reset transistor T 7  includes a first end, a second end, and a control end (e.g. a gate terminal of the first reset transistor T 7 ). The first end of the first reset transistor T 7  is connected to the second node N 2  of the driving circuit  113  of the pixel driving circuit  110 . The second end of the first reset transistor T 7  is configured to receive the first high reference voltage source V REFH . The control end of the first reset transistor T 7  is configured to receive the reset and reading signal RR in the fourth stage I 4 . The first reset transistor T 7  is configured to reset the second node N 2  of the driving circuit  113  of the pixel driving circuit  110  in response to the reset and reading signal RR. 
     Furthermore, please refer to  FIG.  1    and  FIG.  2   , the read transistor T 8  includes a first end, a second end, and a control end (e.g. a gate terminal of the read transistor T 8 ). The first end of the read transistor T 8  is connected to the third node N 3  of the optical sensor circuit  120 . The second end of the read transistor T 8  is connected to a readout line O. The control end of the read transistor T 8  is configured to receive the reset and reading signal RR in the fourth stage I 4 . The read transistor T 8  is configured to read out the light sensing signal of the optical sensor circuit  120  in response to the reset and reading signal RR. 
     In some embodiments, please refer to  FIG.  1   , the optical sensor circuit  120  is further configured to receive the second sweep signal S 2 . The optical sensor circuit  120  includes the third node N 3 , an optical sensor SRO, and a second reset transistor T 9 . 
     Then, please refer to  FIG.  1    and  FIG.  2   , the optical sensor SRO includes a first end and a second end. The first end of the optical sensor SRO is connected to the third node N 3 . The second end of the optical sensor SRO is configured to receive a second reference voltage source V REF_SRO . The optical sensor SRO is configured to perform a sensing process so as to generate the light sensing signal in the third stage I 3 . 
     Furthermore, the second reset transistor T 9  includes a first end, a second end, and a control end (e.g. a gate terminal of the second reset transistor T 9 ). The first end of the second reset transistor T 9  is configured to receive the driving signal EM. The second end of the second reset transistor T 9  is connected to the third node N 3 . The control end of the second reset transistor T 9  is configured to receive the second sweep signal S 2  in the second stage I 2 . The second reset transistor T 9  is configured to reset the third node N 3  to a voltage level V GH  of the driving signal EM in response to the second sweep signal S 2 . 
     In some embodiments, the aforementioned driving transistor DT 1 , and transistors T 1  to T 9  includes P-type Metal-Oxide-Semiconductor Field-Effect Transistor (PMOS). 
       FIG.  3    depicts a schematic diagram of a circuit state of a pixel driving device  100  according to some embodiments of the present disclosure. In some embodiments, please refer to  FIG.  2    and  FIG.  3   , in the first stage I 1 , the first sweep signal S 1  is at a low level, and its voltage level is V GA . The second sweep signal S 2 , the driving signal EM, and the reset and reading signal RR is at a high level, and each of their voltage level is V GH . 
     In some embodiments, the first sweep signal S 1  writes the voltage level of the first high reference voltage source V REFH  to the second node N 2  through the first transistor T 1  of the reset circuit  111 . The control end of the driving transistor DT 1  is configured to receive the voltage level of the second node N 2 . The driving transistor DT 1  is turned off in response to the voltage level. The first sweep signal S 1  writes the voltage level of a first low reference voltage source V REFL  to the second end of the first capacitor C 1  (La the fourth node N 4 ) through the second transistor T 2 . The first sweep signal S 1  writes the voltage level of the first high reference voltage source V REFH  to the first end of the first capacitor C 1  through the third transistor T 3 . 
     At this time, a voltage level of the first node N 1  is the voltage level of first high reference voltage source V REFH . A voltage level of the second node N 2  is the voltage level of the first high reference voltage source V REFH . A voltage level of the fourth node N 4  is the voltage level of the first low reference voltage source V REFL . 
       FIG.  4    depicts a schematic diagram of a circuit state of a pixel driving device  100  according to some embodiments of the present disclosure. In some embodiments, please refer to  FIG.  2    and  FIG.  4   , in the second stage I 2 , the second sweep signal S 2  is at a low level, and its voltage level is V GL . The first sweep signal S 1 , the driving signal EM, and the reset and reading signal RR is at a high level, and each of their voltage level is V GH . 
     In some embodiments, the second sweep signal S 2  writes the voltage level of the data voltage source V DATA  to the fourth node N 4  through the fourth transistor T 4  of the compensation circuit  112 . The second sweep signal S 2  writes the voltage level of the first reference voltage source V REF  to the second node N 2  through the fifth transistor T 5 . Since the voltage level of the second node N 2  is discharged to the voltage level of the first reference voltage source V REF , the driving transistor DT 1  is configure to compensate the first node N 1  in response the voltage level of the second node N 2 . 
     At the same time, the second sweep signal S 2  resets the third node N 3  to the voltage level V GH  of the driving signal EM through the second reset transistor T 9  of the optical sensor circuit  120 . 
     At this time, a voltage level of the first node N 1  is the voltage level of the first reference voltage source V REF  plus a threshold voltage V TH_DT1  of the driving transistor DT 1 . A voltage level of the second node N 2  is the voltage level of reference voltage source V REF . A voltage level of the third node N 3  is the voltage level V GH  of the driving signal EM. A voltage level of the fourth node N 4  is the voltage level of the data voltage source V DATA . 
       FIG.  5    depicts a schematic diagram of a circuit state of a pixel driving device  100  according to some embodiments of the present disclosure. In some embodiments, please refer to  FIG.  2    and  FIG.  5   , the driving signal EM is at a low level, and its voltage level is V GA . The first sweep signal S 1 , the second sweep signal S, and the reset and reading signal RR is at a high level, and each of their voltage level is V GH . 
     In some embodiments, the driving signal EM connects the second node N 2  and the fourth node N 4  through the sixth transistor T 6  and indirectly connects the first node N 1  and the second node N 2 . 
     In some embodiments, the driving transistor DT 1  is turned on according to a voltage difference between the first end and the control end of the driving transistor DT 1 . The first end of the driving transistor DT 1  is equivalent to the first node N 1 . The control end of the driving transistor DT 1  is equivalent to the second node N 2 . After the sixth transistor T 6  is turned on, the driving transistor DT 1  is turned on, so that a voltage level of the second node N 2  becomes (V REF +|V TH_DT1 |−VSS). The first end of the first capacitor C 1  responds to a change of the voltage level of the second node N 2 , and the second end of the first capacitor C 1  senses the first end of the first capacitor C 1  to change the fourth node N 4  to (V DATA +VSS−V REF −|V TH_DT1 |). 
     In addition, a driving current Id is output according to the voltage difference between the first end and the control end of the driving transistor DT 1 . The voltage difference between the first end and the control end of the driving transistor DT 1  is equivalent to a voltage difference between the fourth node N 4  and the second node N 2 . A formula of the above driving current Id is listed below: 
     
       
         
           
             
               
                 
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     In the formula 1, Id is the driving current, VSG is the voltage difference between the first end and the control end of the driving transistor DT 1 , and Vth is a threshold voltage. In the third stage I 3 , the voltage level of the control end of the driving transistor DT 1  is (V DATA +VSS−V REF −)|V TH_DT1 |), and the voltage level of the second end of the driving transistor DT 1  is VSS. Substitute the voltage level of the control end and the second end of the driving transistor DT 1  into the formula 1, a following formula can be obtained: 
     
       
         
           
             
               
                 
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     In aforementioned formula 2, the same voltage levels cancel each other out, and the formula 2 is rewritten as below: 
     
       
         
           
             
               
                 
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     At the same time, please refer to  FIG.  2    and  FIG.  5   , the optical sensor SRO of the optical sensor circuit  120  is configured to perform a sensing process in the third stage I 3  to sense a light L 1  so as to generate the light sensing signal. It should be noted that a photocurrent Ip 1  will generated when the optical sensor SRO generate the light sensing signal. An intensity of the photocurrent Ip 1  will affect the voltage level of the third node N 3  of the optical sensor circuit  120 . The light L 1  includes at least one of a specific spectrum and a visible spectrum. 
     It is further explained that, in the third stage I 3 , a voltage level of the third node N 3  is determined by the intensity of the photocurrent Ip 1 . Therefore, the voltage level of the third node N 3  has various situations. The voltage level of the third node N 3  shown in  FIG.  2    shows four cases corresponding to four dotted lines respectively. The four dotted lines from top to bottom represent a result of the intensity of the photocurrent Ip 1  from weak to strong. When the intensity of the photocurrent Ip 1  is stronger, the voltage level of the third node N 3  reaches a low voltage lever faster. 
       FIG.  6    depicts a schematic diagram of a circuit state of a pixel driving device  100  according to some embodiments of the present disclosure. Please refer to  FIG.  2    and  FIG.  6   , the reset and reading signal RR is at a low level, and its voltage level is V GA . The first sweep signal S 1 , the second sweep signal S 2 , and the driving signal EM is at a high level, and each of their voltage level is V GH . 
     In some embodiments, the reset and reading signal RR writes the voltage level of the first high reference voltage source V REFH  to the second node N 2  through the first reset transistor T 7 , and the driving transistor DT 1  is turned off in response to the voltage level of the second node N 2 . The reset and reading signal RR reads out the light sensing signal sensed by the optical sensor SRO of the optical sensor circuit  120  in the third stage I 3  through the read transistor T 8 , and outputs the light sensing signal to the readout line O. 
       FIG.  7    depicts a schematic diagram of a pixel driving device  100 A according to some embodiments of the present disclosure. In some embodiments, please refer to  FIG.  1    and  FIG.  7   , compared with  FIG.  1   , a difference between the embodiment of  FIG.  7    and the embodiment of  FIG.  1    is that components used in the optical sensor circuit are different, and other circuit structures are the same. 
     In some embodiments, the optical sensor circuit  120 A is further configured to receive the second sweep signal S 2 . The optical sensor circuit  120 A includes the third node N 3 , a second capacitor C 2 , and a light sensing transistor T 10 . 
     Then, the second capacitor C 2  includes a first end and a second end. The first end of the second capacitor C 2  is connected to the third node N 3 . The second end of the second capacitor C 2  is configured to receive the first reference voltage source V REF . 
     Furthermore, please refer to  FIG.  2    and  FIG.  7   , the light sensing transistor T 10  includes a first end, a second end, and a control end. The first end of the light sensing transistor T 10  is configured to receive the driving signal EM. The second end of the light sensing transistor T 10  is connected to the third node N 3 . The control end of the light sensing transistor T 10  is configured to receive the second sweep signal S 2  in the second stage I 2 . The light sensing transistor T 10  is configured to reset the third node N 3  in response to the second sweep signal S 2 , and the light sensing transistor T 10  is configured to perform a sensing process a light L 2  in the third stage I 3  so as to generate the light sensing signal. While generating the light sensing signal, the light sensing transistor T 10  will generate a photocurrent  1   p   2 . The light L 2  includes at least one of a specific spectrum and a visible spectrum. 
     In some embodiments, please refer to  FIG.  1   , the optical sensor circuit  120  includes a first end (e.g. a right side of the optical sensor circuit  120 ) and a second end (e.g. an underside of the optical sensor circuit  120 ). The first end of the optical sensor circuit  120  and one end of the pixel driving circuit  110  are connected to a signal source of the second sweep signal S 2 . The second end of the optical sensor circuit  120  is connected to the reset and reading circuit  130 . The reset and reading circuit  130  and another end of the pixel driving circuit  110  are connected to a signal source of the reset and reading signal RR. 
     In some embodiments, please refer to  FIG.  7   , the optical sensor circuit  120 A includes a first end (e.g. a right side of the optical sensor circuit  120 A) and a second end (e.g. an underside of the optical sensor circuit  120 A). The first end of the optical sensor circuit  120 A and one end of the pixel driving circuit  110 A are connected to a signal source of the second sweep signal S 2 . The second end of the optical sensor circuit  120  is connected to the reset and reading circuit  130 . The reset and reading circuit  130 A and another end of the pixel driving circuit  110 A are connected to a signal source of the reset and reading signal RR. 
       FIG.  8    depicts a schematic diagram of a pixel driving device  100 B according to some embodiments of the present disclosure. In some embodiments, please refer to  FIG.  1    and  FIG.  8   , compared with  FIG.  1   , a difference between the embodiment of  FIG.  8    and the embodiment of  1  is that components used in the optical sensor circuit are different, the optical sensor circuit  1308  is not connected to a signal source of the second sweep signal S 2 , and other circuit structures are the same. 
     In some embodiments, the optical sensor circuit  120 B includes the third node N 3 , a capacitor C 3 , and a light sensing diode PIN. 
     Then, the capacitor C 3  includes a first end and a second end. The first end of the capacitor C 3  is connected to the third node N 3 . The second end of the capacitor C 3  is configured to receive the first reference voltage source V REF . 
     Furthermore, the light sensing diode PIN includes an anode terminal and a cathode terminal. The anode terminal of the light sensing diode PIN is configured to receive the driving signal EM. The cathode terminal of the light sensing diode PIN is connected to the third node N 3 . The light sensing diode PIN is configured to perform a sensing process a light L 3  to generate the light sensing signal. While generating the light sensing signal, the light sensing diode PIN will generate a photocurrent Ip 3 . The light L 3  includes at least one of a specific spectrum and a visible spectrum. 
       FIG.  9    depicts a schematic diagram of a pixel driving device  200  according to some embodiments of the present disclosure. In some embodiments, please refer to  FIG.  1   , the pixel driving device  200  includes a driving transistor DT 1 , a pixel driving circuit  210 , and optical sensor circuit  220 . 
     In some embodiments, the first end of the driving transistor DT 1  is connected to the first node N 1 . The control end of the driving transistor DT 1  is connected to the second node N 2 . The driving transistor DT 1  is configured to control the light emitting device LED. 
     Then, the pixel driving circuit  210  is configured to receive the first sweep signal S 1 , the second sweep signal S 2 , the driving signal EM, and the reset and reading signal RR. The pixel driving circuit  210  is configured to reset the first node N 1  and the second node N 2  according to the first sweep signal S 1 . The pixel driving circuit  210  is configured to compensate the second node N 2  according to the second sweep signal S 2 . The pixel driving circuit  210  is configured to control the driving transistor DT 1  so as to drive the light emitting device LED according to the driving signal EM. The pixel driving circuit  210  is configured to turn off the driving transistor DT 1  according to the reset and reading signal RR. 
     Furthermore, the optical sensor circuit  220  is connected to the pixel driving circuit  210 . The optical sensor circuit  220  is configured to receive the driving signal EM and the reset and reading signal RR. The optical sensor circuit  220  is configured to perform a sensing process so as to generate the light sensing signal. The optical sensor circuit  220  is configured to output the light sensing signal to the readout line O of the pixel driving device  200  according to the reset and reading signal RR. 
     It should be note that, please refer to  FIG.  1   ,  FIG.  7   ,  FIG.  8   , and  FIG.  9   , a difference between the embodiment of  FIG.  8    and the embodiment of  FIG.  9    is that the transistor T 7  in  FIG.  9    is divided into the pixel driving circuit  210  and transistor T 8  in  FIG.  9    is divided into the optical sensor circuit  220 , and a rest of structures and circuit operations are similar to the embodiments shown in  FIG.  1    and  FIG.  8   , and omitted herein. 
     In some embodiments, the pixel driving circuit  210  includes a reset circuit  211 , a compensation circuit  212 , and a driving circuit  213 . The transistor T 7  in  FIG.  9    is divided into the reset circuit  211  of the pixel driving circuit  210 , and a rest of structures and circuit operations are similar to the embodiments shown in  8 . 
     It is further explained that, the embodiment of  FIG.  1    and the embodiment of  FIG.  7    can also be divided into the pixel driving circuit  210  and the optical sensor circuit  220  as shown in  FIG.  9   . However, a circuit division method of the present disclosure is not limited to the embodiment of the present disclosure. 
     Then, please refer to  FIG.  2    and  FIG.  9   , since the transistor T 7  is divided into the pixel driving circuit  210 , the pixel driving circuit  210  performs additional operations in the fourth stage I 4  to reset the second node N 2 , thereby turning off the driving transistor DT 1 . 
     Furthermore, please refer to  FIG.  2    and  FIG.  9   , since the transistor T 8  is divided into the optical sensor circuit  220 , the optical sensor circuit  220  performs additional operations in the fourth stage I 4  to read out the light sensing signal sensed by the optical sensor circuit  220  in the third stage I 3 . 
     In some embodiments, the optical sensor circuit  220  and the pixel driving circuit  210  are connected to a signal source of the reset and reading signal RR. 
     In some embodiments, please refer to  FIG.  1   ,  FIG.  3    to  FIG.  9   , each of the compensation circuits in the aforementioned embodiments is connected to a data line of the pixel driving device (e.g. a location of the data voltage source V DATA ). Each of the compensation circuits in the aforementioned embodiments is configured to receive a voltage of the data line. Each of the compensation circuits in the aforementioned embodiments is configured to compensate the second node N 2  to the voltage of the first reference voltage source V REF  according to the second sweep signal S 2 . 
     In some embodiments, a direction of the signal transmitted by the data line (e.g. a location of the data voltage source V DATA ) and a direction of the signal transmitted by the readout line O are the same direction. 
     Based on the above embodiments, the present disclosure provides a pixel driving device to reduce a voltage difference between two power supply voltages so as to reduce power consumption, and an optical sensor is added so that a pixel driving device can sense and display at the same time. 
     Although the present disclosure has been described in considerable detail with reference to certain embodiments thereof, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein. 
     It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present disclosure without departing from the scope or spirit of the present disclosure. In view of the foregoing, it is intended that the present disclosure cover modifications and variations of the present disclosure provided they fall within the scope of the following claims.