Patent Publication Number: US-2018032457-A1

Title: Slave initiated interrupts for a communication bus

Description:
BACKGROUND 
     I. Field of the Disclosure 
     The technology of the disclosure relates generally to interrupt signaling on a communication bus. 
     II. Background 
     Computing devices have become increasingly common in modern society. Mobile phones are among the more common computing devices. While such devices may initially have started out as simple devices that allowed audio communication through the Public Land Mobile Network (PLMN) to the Public Standard Telephone Network (PSTN), they have evolved into smart phones capable of supporting full multimedia experiences as well as supporting multiple wireless protocols. Even within the cellular wireless protocols, mobile phone radios have developed into highly complex, multi-band, and multi-standard designs that often have multiple radio frequency (RF) signal chains. Every component in the RF signal chain has to be in the desired configuration at any given time, or the system will fail. Therefore, accurate timing, triggers, and speed are all necessary. 
     As further explained on the MIPI Alliance® website, “[t]he MIPI Alliance Specification for RF Front-End Control Interface (RFFE) was developed to offer a common and widespread method for controlling RF front-end devices. There are a variety of front-end devices, including Power Amplifiers (PA), Low-Noise Amplifiers (LNA), filters, switches, power management modules, antenna tuners and sensors. These functions may be located either in separate devices or integrated into a single device, depending on the application. The trend in mobile radio communications is towards complex multi-radio systems comprised of several parallel transceivers. This implies a leap in complexity of the RF front-end design. Thus, the RFFE bus must be able to operate efficiently in configurations from the simplest one Master and one Slave configuration to, potentially, multi-Master configurations with tens of Slaves.” 
     In devices having an RFFE bus, the RFFE protocol dictates that the master periodically polls the slaves on the RFFE bus to determine if the slaves have an interrupt condition. Exemplary slaves include antenna switches and low noise amplifiers. In a typical implementation, this polling occurs once per millisecond. Cellular protocols are becoming increasingly stringent with latency issues and the mobile device may not be compliant with a particular cellular protocol if the master waits a full millisecond to poll an antenna switch. If the polling merely occurs more frequently, the polling may create an unwanted power drain as numerous polling cycles result in negative acknowledgments from the slaves. Accordingly, cellular protocol compliance and power savings may be effectuated with a better interrupt techniques for RFFE buses. 
     SUMMARY OF THE DISCLOSURE 
     Aspects disclosed in the detailed description include slave initiated interrupts for a communication bus. In an exemplary aspect, the communication bus is a radio frequency front end (RFFE) bus, and a slave is allowed to indicate to a master on the RFFE bus that the slave has an interrupt condition. On receipt of a slave initiated interrupt, the master may initiate a polling sequence to determine which of a plurality of slaves associated with the RFFE bus initiated the interrupt and process the interrupt accordingly. Continuing the exemplary aspect, the slave may indicate the interrupt condition to the master by driving a clock line of the RFFE bus to a non-idle state. The master may detect this manipulation of the clock line and initiate the polling sequence. By relying on the slave to initiate an indication of an interrupt, polling may begin before a periodic polling activity, which in turn may reduce latency and allow compliance with increasingly strict cellular protocols. Further, as unneeded periodic polling may be eliminated or a period increased, power savings may be effectuated. 
     In this regard in one aspect, a method for detecting an interrupt from a slave on an RFFE bus is disclosed. The method includes holding a clock line within an RFFE bus at a logical low when the RFFE bus is idle. The method also includes detecting, while the RFFE bus is idle, with detection circuitry at a master associated with the RFFE bus, a logical high on the clock line. The method also includes initiating an interrupt inquiry from the master. 
     In another aspect, a master is disclosed. The master includes an RFFE interface configured to be coupled to an RFFE bus. The master also includes a clock source coupled to the RFFE interface. The master also includes a transceiver coupled to the RFFE interface. The master also includes a detection circuit coupled to the RFFE interface. The detection circuit is configured to detect when a clock line of the RFFE bus is pulled high by a slave associated with the RFFE bus. The detection circuit is also configured to initiate an interrupt inquiry through the transceiver. 
     In another aspect, a method for a slave signaling an interrupt on an RFFE bus is disclosed. The method includes, at a slave coupled to an RFFE bus, detecting an interrupt condition within the slave. The method also includes, at the slave, driving a clock line of the RFFE bus from an idle state to a modified state to indicate the interrupt condition at the slave to a master. The method also includes subsequently responding to an interrupt inquiry from the master. 
     In another aspect, a slave is disclosed. The slave includes an RFFE interface configured to couple to an RFFE bus. The slave also includes a transceiver coupled to the RFFE interface. The slave also includes an interrupt circuit coupled to the RFFE interface. The interrupt circuit is configured to receive an indication that the slave has an interrupt condition. The interrupt circuit is also configured to drive a clock line in the RFFE bus from an idle state to a modified state. 
    
    
     
       BRIEF DESCRIPTION OF THE FIGURES 
         FIG. 1  is system-level block diagram of an exemplary mobile terminal configured to communicate based on MIPI Alliance® (MIPI) defined architecture; 
         FIG. 2  is a simplified block diagram of a master and a slave on a radio frequency front end (RFFE) bus capable of slave initiated interrupts according to an exemplary aspect of the present disclosure; 
         FIG. 3  is a flowchart illustrating an exemplary process conducted by a slave for initiating an interrupt on an RFFE bus; and 
         FIG. 4  is a flowchart illustrating an exemplary process conducted by a master for detecting a slave initiated interrupt on an RFFE bus. 
     
    
    
     DETAILED DESCRIPTION 
     With reference now to the drawing figures, several exemplary aspects of the present disclosure are described. The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects. 
     Aspects disclosed in the detailed description include slave initiated interrupts for a communication bus. In an exemplary aspect, the communication bus is a radio frequency front end (RFFE) bus, and a slave is allowed to indicate to a master on the RFFE bus that the slave has an interrupt condition. On receipt of a slave initiated interrupt, the master may initiate a polling sequence to determine which of a plurality of slaves associated with the RFFE bus initiated the interrupt and process the interrupt accordingly. Continuing the exemplary aspect, the slave may indicate the interrupt condition to the master by driving a clock line of the RFFE bus to a non-idle state. The master may detect this manipulation of the clock line and initiate the polling sequence. By relying on the slave to initiate an indication of an interrupt, polling may begin before a periodic polling activity, which in turn may reduce latency and allow compliance with increasingly strict cellular protocols. Further, as unneeded periodic polling may be eliminated or a period increased, power savings may be effectuated. 
     Before discussing exemplary aspects of slave initiated interrupts for a communication bus that include specific aspects of the present disclosure, a brief overview of a mobile terminal configured based on MIPI Alliance® (MIPI) defined architecture is first provided in  FIG. 1 . The discussion of specific exemplary aspects of slave initiated interrupts for a communication bus starts with reference to  FIG. 2 . 
     In this regard,  FIG. 1  is system-level block diagram of an exemplary mobile terminal  100  such as a smart phone, mobile computing device tablet, or the like. While a mobile terminal is particularly contemplated as being capable of benefiting from exemplary aspects of the present disclosure, it should be appreciated that the present disclosure is not so limited and may be useful in any system having a bus that has multiple masters and needing priority-based bus access with minimal latency. For the sake of illustration, it is assumed that an RFFE bus  102  within the mobile terminal  100  is among multiple communication buses configured to support slave initiated interrupts according to the present disclosure. 
     With continued reference to  FIG. 1 , the mobile terminal  100  includes an application processor  104  (sometimes referred to as a host) that communicates with a mass storage element  106  through a universal flash storage (UFS) bus  108 . The application processor  104  may further be connected to a display  110  through a display serial interface (DSI) bus  112  and a camera  114  through a camera serial interface (CSI) bus  116 . Various audio elements such as a microphone  118 , a speaker  120 , and an audio codec  122  may be coupled to the application processor  104  through a serial low power interchip multimedia bus (SLIMbus)  124 . Additionally, the audio elements may communicate with each other through a SOUNDWIRE™ bus  126 . A modem  128  may also be coupled to the SLIMbus  124 . The modem  128  may further be connected to the application processor  104  through a peripheral component interconnect (PCI) or PCI express (PCIe) bus  130  and/or a system power management interface (SPMI) bus  132 . 
     With continued reference to  FIG. 1 , the SPMI bus  132  may also be coupled to a wireless local area network (WLAN) integrated circuit (IC) (WLAN IC)  134 , a power management integrated circuit (PMIC)  136 , a companion integrated circuit (sometimes referred to as a bridge chip)  138 , and a radio frequency integrated circuit (RFIC)  140 . It should be appreciated that separate PCI buses  142  and  144  may also couple the application processor  104  to the companion integrated circuit  138  and the WLAN IC  134 . The application processor  104  may further be connected to sensors  146  through a sensor bus  148 . The modem  128  and the RFIC  140  may communicate using a bus  150 . 
     With continued reference to  FIG. 1 , and of particular interest for the present disclosure, the RFIC  140  may couple to one or more RFFE elements, such as an antenna tuner  152 , a switch  154 , and a power amplifier  156  through the RFFE bus  102 . Additionally, the RFIC  140  may couple to an envelope tracking power supply (ETPS)  158  through a bus  160 , and the ETPS  158  may communicate with the power amplifier  156 . Collectively, the RFFE elements, including the RFIC  140 , may be considered an RFFE system  162 . 
     Within the RFFE system  162  there is at least one master and typically at least one slave. The RFFE protocol contemplates a master with up to fifteen slaves. In the absence of the present disclosure, the master will periodically poll the slaves to see if any of the slaves have interrupt conditions that need to be addressed. The period between polling events adds latency to the system. Further, if the master polls and there are no interrupt conditions, then power may have been consumed needlessly. While there may be devices that are not concerned with power consumption because such devices may have access to a wall outlet and continuous power, other devices, such as battery powered mobile terminals, try to limit power consumption as much as possible so as to extend battery life. To alleviate such latency and power consumption, exemplary aspects of the present disclosure allow the slaves to initiate an interrupt indication to the master over the RFFE bus  102 . In this regard, the master and slave are modified as better illustrated in  FIG. 2 . 
       FIG. 2  illustrates the RFFE system  162  of  FIG. 1  with a master  200  and a slave  202  communicatively coupled by the RFFE bus  102 . In exemplary aspects, a typical master is a modem baseband processor containing largely digital logic or a modem radio frequency integrated circuit. Additionally, typical slaves may include antenna tuners, power amplifiers, low noise amplifiers, or the like. While only one slave is illustrated, it should be appreciated that up to fifteen slaves may be coupled to the RFFE bus  102 . It should be appreciated that there may be multiple masters in an RFFE system and slaves may be controlled by multiple masters as determined by a bus arbitration mechanism. The RFFE bus  102  is a two-wire bus with a data line  204  and a clock line  206 . The master  200  may include a transceiver  208  that sends and receives data on the data line  204 . The master  200  may further include a clock source  210  that selectively provides a clock signal  212  on the clock line  206 . The master  200  may further include a detection circuit  214  that detects signals on the clock line  206 . The master  200  may further include an interface  216  that is configured to be coupled to the RFFE bus  102 . Similarly, the slave  202  may include a transceiver  218  that sends and receives data on the data line  204 . The slave  202  may further include a delay locked loop (DLL)  220  that receives the clock signal  212  and generates a local clock signal for the slave  202 . The slave  202  may also have an interrupt circuit  222  that is designed to provide an interrupt signal  224  on the clock line  206  as better explained in greater detail below. The slave  202  is coupled to the RFFE bus  102  through an interface  226 . According to the RFFE protocol, the data line  204  and the clock line  206  are maintained at a logical low when the lines  204  and  206  are idle. When the interrupt circuit  222  detects that the slave  202  has an interrupt condition, the interrupt circuit  222  pulls the clock line  206  to a logical high with the interrupt signal  224 . In an exemplary aspect, interrupt conditions may arise when a slave determines an error condition of data received at the slave or the slave desiring master support, such as updating a configuration register to change the gain of a low noise amplifier (LNA) (e.g., the slave determines the signal level required and has an interrupt condition for the master to issue an LNA gain change) or the like. The detection circuit  214  detects the logical high from the interrupt signal  224  and determines that one of the slaves (e.g., the slave  202 ) has an interrupt condition and may then initiate polling the slaves to determine which slave has the interrupt condition. 
     In this regard,  FIG. 3  illustrates a process  300  whereby the slave  202  initiates the interrupt rather than reacting to interrupt polling from the master  200 . Initially, the slave  202  detects an interrupt condition within the slave  202  (block  302 ). For example, if the slave  202  is an antenna switch, the interrupt condition may be an error condition in a nominal data transfer or changing RF conditions which require master resolution. The slave  202  verifies that the clock line  206  of the RFFE bus  102  is idle (block  304 ). Once the clock line  206  is idle, the slave  202  uses the interrupt circuit  222  to drive the clock line  206  from an idle state to a modified state (block  306 ). In an exemplary aspect, the idle state is a logical low and the modified state is a logical high. After signaling the interrupt condition to the master in this fashion, the master  200  will begin an interrupt inquiry which will cause the slave  202  to receive the interrupt inquiry from the master  200  (block  308 ). The slave  202  will then respond to the interrupt inquiry (block  310 ), indicating a slave identity and a nature of the interrupt so that the interrupt may be handled appropriately by the master  200 . 
     While  FIG. 3  is set up to show the process  300  for the slave  202 ,  FIG. 4  provides a flowchart of process  400  for the master  200 . In this regard, the master  200  conducts normal operations (block  402 ). When operations reach a lull, the master  200  puts the clock line  206  into an idle state (block  404 ). As noted above, in an exemplary aspect, the idle state of the clock line  206  is a logical low. When the slave  202  has an interrupt condition, the slave  202  pulls the clock line  206  to a modified state, and the detection circuit  214  detects that the clock line  206  has been pulled to the modified state (block  406 ). In an exemplary aspect, the modified state is a logical high. The detection circuit  214  reports this slave initiated interrupt and the master  200  initiates an interrupt inquiry (block  408 ). 
     The master  200  may perform the interrupt inquiry in many different forms. In an exemplary aspect, the interrupt inquiry is a simple polling of the slaves on the RFFE bus  102 . This polling may be done in ascending order by address or descending order by address. In still another exemplary aspect, the polling may step through the addresses using odd addresses first, then even addresses or vice versa such that the even addresses are polled first, then the odd addresses. In still another exemplary aspect, the master  200  may know that only a subset of the slaves associated with the RFFE bus  102  are authorized to request an interrupt, and the master  200  may poll only those authorized slaves. In still another exemplary aspect, the master  200  may have a look-up table that indicates an order in which the slaves are polled. In still another exemplary aspect, the master  200  may poll the slaves using a weighted order where slaves that are more likely to have an interrupt are polled before slaves that are less likely to have an interrupt. Likewise, the weighting may be based on quality of service requirements. For example certain slaves  202  may have a higher priority in getting services. As a specific example, an antenna tuner may be serviced before an antenna switch. Such weighting and ordering of service may have a discernable and detectable impact on the radio quality and thus the user experience. 
     The slave initiated interrupts for a communication bus according to aspects disclosed herein may be provided in or integrated into any processor-based device. Examples, without limitation, include a set top box, an entertainment unit, a navigation device, a communications device, a fixed location data unit, a mobile location data unit, a mobile phone, a cellular phone, a smart phone, a tablet, a phablet, a server, a computer, a portable computer, a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, a portable digital video player, and an automobile. 
     Those of skill in the art will further appreciate that the various illustrative logical blocks, modules, circuits, and algorithms described in connection with the aspects disclosed herein may be implemented as electronic hardware, instructions stored in memory or in another computer readable medium and executed by a processor or other processing device, or combinations of both. The master devices, and slave devices described herein may be employed in any circuit, hardware component, integrated circuit (IC), or IC chip, as examples. Memory disclosed herein may be any type and size of memory and may be configured to store any type of information desired. To clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. How such functionality is implemented depends upon the particular application, design choices, and/or design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure. 
     The various illustrative logical blocks, modules, and circuits described in connection with the aspects disclosed herein may be implemented or performed with a processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration). 
     The aspects disclosed herein may be embodied in hardware and in instructions that are stored in hardware, and may reside, for example, in Random Access Memory (RAM), flash memory, Read Only Memory (ROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), registers, a hard disk, a removable disk, a CD-ROM, or any other form of computer readable medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a remote station. In the alternative, the processor and the storage medium may reside as discrete components in a remote station, base station, or server. 
     It is also noted that the operational steps described in any of the exemplary aspects herein are described to provide examples and discussion. The operations described may be performed in numerous different sequences other than the illustrated sequences. Furthermore, operations described in a single operational step may actually be performed in a number of different steps. Additionally, one or more operational steps discussed in the exemplary aspects may be combined. It is to be understood that the operational steps illustrated in the flowchart diagrams may be subject to numerous different modifications as will be readily apparent to one of skill in the art. Those of skill in the art will also understand that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. 
     The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.