Patent Publication Number: US-2018054192-A1

Title: Phase interpolator

Description:
RELATED APPLICATIONS 
     This application claims priority to Taiwan Application Serial Number, 105126416, filed Aug. 18, 2016, which is herein incorporated by reference. 
     BACKGROUND 
     Technical Field 
     The present disclosure relates to an integrated circuit. More particularly, the present disclosure relates to a correction circuit for a phase interpolator. 
     Description of Related Art 
     Phase interpolators are commonly utilized in communication systems for synchronizing operational signals in the communication systems. With growing demands, which include, for example, higher speed, for communication systems, requirements for accuracy and a speed of the phase interpolators become higher. In current approaches, the driving abilities for a rising current and a falling current in the phase interpolators cannot be consistent with each other. As such, the accuracy of the phase interpolators cannot be improved. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a schematic diagram of a phase interpolator according to one embodiment of the present disclosure. 
         FIG. 2A  is a circuit diagram of the correction circuit in  FIG. 1 , according to one embodiment of the present disclosure. 
         FIG. 2B  is a circuit diagram of the correction circuit in  FIG. 1 , according to another embodiment of the present disclosure. 
         FIG. 3  is a schematic diagram of a part of a phase interpolator according to one embodiment of the present disclosure. 
         FIG. 4  is a schematic diagram of a part of a phase interpolator according to one embodiment of the present disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     Referring to  FIG. 1 , a phase interpolator  100  includes an input stage  110 , a switching circuit  120 , current source circuits  130 - 1 - 130 -N, and an output stage  140 . 
     The input stage generates a signal I 1  and a signal I 2  according to a group of input signals (AIP, AIPB) and a group of input signals (AIN, AINB). In this embodiment, the input stage  110  includes differential pairs  112  and  114 . The differential pair  112  includes transistors M 1  and M 2 . The transistor M 1  and the transistor M 2  are configured to generate the signal I 1  at a node N 1  according to the input signal AIP and the signal AIPB, respectively. As shown in  FIG. 1 , a first terminal, i.e., node N 3 , of the transistor M 1  is coupled to the output stage  140 , a second terminal of the transistor M 2  is coupled to the node N 1 , and a control terminal of the transistor M 1  receives the input signal AIP. A first terminal, i.e., node N 4 , of the transistor M 2  is coupled to the output stage  140 , a second terminal of the transistor M 2  is coupled to the node N 1 , and a control terminal of the transistor M 2  receives the input signal AIPB. 
     Furthermore, the differential pair  114  includes transistors M 3  and M 4 . A first terminal of the transistor M 3  is coupled to the node N 3 , a second terminal of the transistor M 3  is coupled to the node N 2 , and a control terminal of the transistor M 3  receives the input signal AIN. A first terminal of the transistor M 4  is couple to the node N 4 , a second terminal of the transistor M 4  is coupled to the node N 2 , and a control terminal of the transistor M 4  receives the input signal AINB. With the above arrangements, the differential pair  112  and the differential pair  144  can generate different values of the signals I 1  and I 2  according to the corresponding input signals AIP, AIPB, AIN, and AINB. As a result, the output stage  140  can generate output signals VOUTP and VOUN that have corresponding phases based on different values of the signals I 1  and I 2 . 
     The switching circuit  120  is configured to be selectively turned on or turned off according to control signals (not shown), in order to transmit the signals I 1  and I 2  to at least corresponding one of the current source circuits  130 - 1 - 130 -N. In this embodiment, the current source circuits  130 - 1 - 130 -N can be implemented with current mirror circuits, but the present disclosure is not limited thereto. 
     The switching circuit  120  includes groups of switches SW 1 -SWN. Taking the groups of switches SW 1  as an example, the group of switches SW 1  includes a switch S 11  and a switch S 12 . A first terminal of the switch S 11  is coupled to the node N 1 , a second terminal of the switch S 11  is coupled to the current source circuit  130 - 1 , and a control terminal of the switch S 11  is configured to receive a first control signal (not shown). A first terminal of the switch S 12  is coupled to the node N 2 , a second terminal of the switch S 12  is coupled to the current source circuit  130 - 1 , and a control terminal of the switch S 12  is configured to receive a second control signal (not shown). Arrangements between the rest groups of switches SW 2 -SWN and the current source circuits  130 - 2 - 130 -N are the same as the arrangement of the group of switches SW 1  and the current source circuit  130 - 1 , and thus the repetitious descriptions are not given herein. 
     Internal switches (e.g., switches S 11 -S 12 ) of the groups of switches SW 1 -SWN can be turned on or turned off via control signals. With such the arrangements, the signals I 1  and I 2  can be transmitted to at least one corresponding one of the current source circuits  130 - 1 - 130 -N via the turn-on switch in the groups of switches SW 1 -SWN. In this embodiment, the values of the signals I 1  and I 2  can be controlled by the internal switches of the groups of switches SW 1 -SWN. Taking the group of switches SW 1  as an example, the current source circuit  130 - 1  pulls corresponding currents from the node N 1  and the node N 2  based on the turn-on statuses of the switches S 11  and S 12 . As the nodes N 1  and N 2  are coupled to at least corresponding one of the groups of the switches SW 1 -SWN, the values of the signals I 1  and I 2  are adjusted to different values according to the corresponding currents. Effectively, by determining the turn-on statuses of the switches in the groups of switches SW 1 -SWN, a conducting path is formed between the current source circuits  130 - 1 - 130 -N and the node N 1 /N 2 . Accordingly, the values of the signals I 1  and I 2  are adjusted. As a result, the phase interpolator  100  can generate the output signals VOUTP and VOUTN that have different phases according to the signals I 1  and I 2 . 
     The output stage  140  provides at least one active load to generate the output signals VOUTP and VOUTN according to the signals I 1  and I 2 . In the example of  FIG. 1 , in this embodiment, the output stage  140  includes transistors M 5 -M 14 . A first terminal of the transistor M 5  receives a voltage VDD, and both of a second terminal and a control terminal of the transistor M 5  are coupled to the node N 3 . A first terminal of the transistor M 6  receives the voltage VDD, and both of a second terminal and a control terminal of the transistor M 6  are coupled to the node N 4 . A first terminal of the transistor M 7  receives the voltage VDD, a second terminal (i.e., node NP) of the transistor M 7  generates the output signal VOUTP, and a control terminal of the transistor M 7  is coupled to the node N 3 . A first terminal of the transistor M 8  receives the voltage VDD, a second terminal (i.e., node NN) of the transistor M 8  generates the output signal VOUTN, and a control terminal of the transistor M 8  is coupled to the control terminal of the transistor M 6 . 
     A first terminal of the transistor M 9  is coupled to the node NN, a second terminal of the transistor M 9  is coupled to ground, and a control terminal of the transistor M 9  is coupled to a control terminal of the transistor M 13 . A first terminal of the transistor M 10  is coupled to the node NP, a second terminal of the transistor M 10  is coupled to ground, and a control terminal of the transistor M 10  is coupled to a control terminal of the transistor M 14 . 
     A first terminal of the transistor M 11  receives the voltage VDD, a second terminal of the transistor M 11  is coupled to a first terminal of the transistor M 13 , and a control terminal of the transistor M 11  is coupled to the node N 3 . A first terminal of the transistor M 12  receives the voltage VDD, a second terminal of the transistor M 12  is coupled to a first terminal of the transistor M 14 , and a control terminal of the transistor M 12  is coupled to the node N 4 . A second terminal of the transistor M 13  is coupled to ground, and a control terminal of the transistor M 13  is coupled to the first terminal of the transistor M 13 . A second terminal of the transistor M 14  is coupled to ground, and a control terminal of the transistor M 14  is coupled to the first terminal of the transistor M 14 . 
     With such the arrangement, when the input stage  110  generates the signals I 1 -I 2  according to the input signals AIP, AIPB, AIN, and AINB, the transistors M 5  and M 6  thus mirror the corresponding currents to the switches M 7  and M 8 , in order to generate the output signals VOUTP and VOUTN. Moreover, as shown in  FIG. 1 , the transistors M 1 -M 10  form differential circuit architecture that is fully symmetrical. With the differential circuit architecture, the values of the current at rising or falling of the output signals VOUTP and VOUTN can be identical with one another. As a result, the output accuracy of the phase interpolator  100  can be improved. 
     In this embodiment, the phase interpolator  100  further includes a correction circuit  150 . The correction circuit  150  provides and stabilizes a common mode voltage of the output signal VOUTP according to the output signal VOUTP, and provides and stabilizes a common mode voltage of the output signal VOUTN according to the output signal VOUTN. With the correction circuit  150 , the common mode voltages of the output signals VOUTN and VOUTP can be corrected to a stabilized voltage level. As a result, the accuracy of both of the output signals VOUTN and VOUTP, which are generated from an interpolation of the phase interpolator  100 , can be improved. 
     Referring to  FIG. 2A , in this embodiment, the correction circuit  150  can be implemented with a negative feedback circuit. In this embodiment, the correction circuit  150  includes an amplifier  201  and an amplifier  202 . The amplifier  201  generates a common mode voltage of the output signal VOUTP according to the output signal VOUTP. For example, a positive input terminal of the amplifier  201  receives a predetermined voltage VCM, and a negative terminal of the amplifier  201  is coupled to the node NP to receive the output signal VOUTP. An output terminal of the amplifier  201  generates the common mode voltage of the output signal VOUTP. With such an arrangement, the amplifier  201  can output a voltage that is substantially the same as the predetermined voltage VCM according to the output signal VOUTP and the predetermined voltage VCM, and configure the voltage as the common mode voltage of the output signal VOUTP. 
     Similarly, the amplifier  202  generates a common mode voltage of the output signal VOUTN according to the output signal VOUTN. For example, a positive input terminal of the amplifier  202  receives the predetermined voltage VCM, and a negative terminal of the amplifier  202  is coupled to the node NN to receive the output signal VOUTN. An output terminal of the amplifier  202  generates the common mode voltage of the output signal VOUTN. With such an arrangement, the amplifier  202  can output a voltage that is substantially the same as the predetermined voltage VCM according to the output signal VOUTN and the predetermined voltage VCM, and configure it as the common mode voltage of the output signal VOUTN. Effectively, the amplifiers  201  and  202  are arranged as a negative feedback circuit of the output stage  140 , in order to converge levels of the two nodes (i.e., nodes NN and NP) of the output stage  140  toward to the predetermined voltage VCM. 
     Referring to  FIG. 2B , in this embodiment, the correction circuit  150  can be implemented with an AC-coupled circuit. In the example of  FIG. 2B , in this embodiment, the AC-coupled circuit includes capacitors C 1 -C 2 , resistors R 1 -R 2 , buffers B 1 -B 2 , and a buffering output circuit  203 . The capacitor C 1  is coupled to the second terminal of the transistor M 7  to receive the output signal VOUTP. The capacitor C 1  filters a DC-component of the output signal VOUTP to output an AC signal IA 1 , and provides the common mode voltage of the output signal VOUTP. The resistor R 1  generates a DC voltage (not shown) according to the AC signal IA 1 . The buffer B 1  generates the output signal VO 1  based on the AC signal IA 1 . The buffering output circuit  203  generates the output signal VO 2  based on the common mode voltage generated from the resistor R 1  and the output signal VO 1 . 
     Similarly, the capacitor C 2  filters a DC-component of the output signal VOUTN to output an AC signal IA 2 . The resistor R 2  generates a DC voltage (not shown) according to the AC signal IA 2 , and provides the common mode voltage of the output signal VOUTN. The buffer B 2  generates the output signal VO 3  based on the AC signal IA 2 . The buffering output circuit  203  generates the output signal VO 4  based on the common mode voltage generated from the resistor R 2  and the output signal VO 3 . In this embodiment, the resistance values of the resistor R 1 -R 2  can be determined according to gain and bandwidth. An expected common mode voltage value is determined by resistor self-bias definition. In this embodiment, the buffering output circuit  203  can be implemented by buffers and/or latches. 
     Reference is made to  FIG. 3 .  FIG. 3  only shows a part of the main circuit diagram of the phase interpolator  300 . The rest circuits in the phase interpolator  300  can be understood with reference to  FIG. 1 . 
     Compared with  FIG. 1 , the phase interpolator  300  further includes a regulation circuit  320 . In this embodiment, the regulation circuit  320  is configured to increase equivalent impedances to which the current source circuits  130 - 1 - 130 -N correspond, in order to improve the operational stability and accuracy of the current source circuits  130 - 1 - 130 -N. 
     In the example of  FIG. 3 , in this embodiment, the current source circuits  130 - 1 - 130 -N include transistors M 15 -M 16  and amplifiers  321 - 322 . A first terminal of the transistor M 15  is coupled to the node N 1  to receive the signal I 1 , and a second terminal of the transistor M 15  is coupled to one terminal of the switching circuit (i.e., first terminals of the switch S 11 -SN 1 ) to transmit the signal I 1 . A control terminal of the transistor M 15  receives a bias voltage VB 1 . A first terminal of the transistor M 16  is coupled to the node N 2  to receive the signal I 2 , and a second terminal of the transistor M 16  is coupled to another terminal of the switching circuit (i.e., first terminals of the switches S 12 -SN 2 ) to transmit the signal I 2 . A control terminal of the transistor M 16  receives a bias voltage VB 2 . 
     Furthermore, the amplifier  321  generates the bias voltage VB 1  according to a voltage level of the second terminal of the transistor M 15  and a reference voltage VREF. The amplifier  322  generates the bias voltage VB 2  according to a voltage level of the second terminal of the transistor M 16  and the reference voltage VREF. 
     With such the arrangement, the amplifier  321  is configured as a negative feedback circuit for the transistor M 15 , in order to stable the voltage variation across two terminals of the transistor M 15 . Effectively, the output impedances of the current source circuits  130 - 1 - 130 -N are increased, such that the operations of the current source circuits  130 - 1 - 130 -N can be more stable, and the accuracy of the current of those circuits are also improved. Similarly, the amplifier  322  is also configured to as a negative feedback circuit for the transistor M 16 . The operations of the amplifier  322  are similar with the operations of the amplifier  321 , and thus the repetitious descriptions are not given here. 
     Reference is made to  FIG. 4 .  FIG. 4  only shows a part of the main circuit diagram of the phase interpolator  400 . The rest circuits in the phase interpolator  300  can be understood with reference to  FIG. 1 . 
     Compared with  FIG. 1 , the output stage  140  of the phase interpolator  400  employs two resistors RB 1  and RB 2  as load of the input stage  110 . In this embodiment, a resistance value of the resistor RB 1  is set to be less than an output impedance of the transistor M 5 , and a resistance value of the resistor RB 2  is set to be less than an output impedance of the transistor M 6 . As a result, the resistors RB 1  and RB 2  will be considered as main loads of the input stage  110 . Compared with the output stage  140  in  FIG. 1 , the impacts, which are introduced from nonlinear signal components, on the linearity of the output stage  140  in  FIG. 4  can be much lower. Accordingly, the linearity of the gain or the bandwidth of the phase interpolator  400  can be improved. 
     In this embodiment, capacitors CB 1  and CB 2  are configured as capacitors, which have a filtering function and a voltage stabilization function, of an interpolative filtering circuit. As shown in  FIG. 4 , a first terminal of the capacitor CB 1  receives the voltage VDD, and a second terminal of the capacitor CB 1  is coupled to the second terminal of the switch M 5 . A first terminal of the capacitor CB 2  receives the voltage VDD, and a second terminal of the capacitor CB 2  is coupled to the second terminal of the switch M 6 . In this embodiment, the capacitors CB 1  and CB 2  can be implemented with transistors, in which first terminals and the second terminals of the transistors receive the voltage VDD, and control terminals of the transistors are coupled to the node N 3  and/or the node N 4 . 
     In various embodiments, the capacitors CB 1  and CB 2  can be selectively employed according to practical requirements. 
     The correction circuit  150 , the regulation circuit  320 , and the output stage  140  in various embodiments above can be selectively employed in the phase interpolator  100  according to practical applications. For example, when the accuracy of a signal outputted from the phase interpolator  100  is critical, all of the correction circuit  150 , the regulation circuit  320 , and the output stage  140  can be employed. Alternatively, when the requirement of the accuracy of a signal outputted from the phase interpolator  100  is relatively lower, only one of the correction circuit  150 , the regulation circuit  320 , and the output stage  140  can be employed. Therefore, various phase interpolators that employs at least one of the correction circuit  150 , the regulation circuit  320 , and the output stage  140  in the embodiments above are also within the contemplated scope of the present disclosure. 
     As discussed above, the phase interpolator provided in the present disclosure can employ correction mechanisms to improve an accuracy of the phase interpolator, in order to obtain an output signal having a high accuracy. 
     It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present disclosure without departing from the scope or spirit of the disclosure. In view of the foregoing, it is intended that the present disclosure cover modifications and variations of this disclosure provided they fall within the scope of the following claims.