Patent Publication Number: US-2013243368-A1

Title: Optoelectronic interconnects using l-shaped fixture

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is related to a U.S. patent application entitled “Integrated Optoelectronic Interconnects with Side-Mounted Transducers,” Attorney docket no. 1058-1051, filed on even date, whose disclosure is incorporated herein by reference. 
    
    
     FIELD OF THE INVENTION 
     The present invention relates generally to optical communication, and particularly to integrated optical interconnects. 
     BACKGROUND OF THE INVENTION 
     Optoelectronic interconnects typically integrate a control chip with optoelectronic transducers, such as semiconductor lasers and photodiodes, which are utilized, for example, in high data rate, high bandwidth communication systems. Typically, optoelectronic interconnects are used in optical modules, which are fabricated using a variety of hybrid assembly techniques, and sometimes require high precision alignment processes when directing light between the optical fiber core to the optoelectronic transducer. 
     SUMMARY OF THE INVENTION 
     An embodiment of the present invention described herein provides an apparatus including an L-shaped fixture, a first semiconductor die, and a second semiconductor die. The L-shaped fixture includes first and second perpendicular faces. The first semiconductor die includes an array of optoelectronic transducers and is attached onto the first face. The second semiconductor die, which is mounted parallel to the second face, includes ancillary circuitry connected to the optoelectronic transducers by electronic interconnects configured within the fixture. 
     In some embodiments, the fixture includes a flexible printed circuit board that is folded to form the first and second perpendicular faces. In other embodiments, the apparatus includes optical lenses formed within respective holes in the first face. In yet other embodiments, the apparatus also includes respective optical fibers that are coupled to the optoelectronic transducers on the first face, so as to direct light between the fibers and the transducers. 
     In some embodiments, the apparatus includes a ferrule, which is attached to the first face and is configured to hold respective optical fibers opposite the transducers. In other embodiments, the second die is mounted on the second face. In yet other embodiments, the second die is mounted alongside and parallel with the second face. 
     There is additionally provided, in accordance with an embodiment of the present invention, a method including providing an L-shaped fixture having first and second perpendicular faces. A first semiconductor die including an array of optoelectronic transducers is attached onto the first face of the L-shaped fixture. A second semiconductor die, which includes ancillary circuitry that is connected to the optoelectronic transducers by electronic interconnects configured within the fixture, is mounted parallel to the second face of the L-shaped fixture. 
     The present invention will be more fully understood from the following detailed description of the embodiments thereof, taken together with the drawings in which: 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIGS. 1A and 1B  are an isometric view and cross-sectional view of an optoelectronic interconnect, respectively, in accordance with an embodiment of the present invention; 
         FIG. 2  is a flow chart that schematically illustrates a method for forming an optoelectronic interconnect, in accordance with an embodiment of the present invention; 
         FIG. 3  shows an isometric view of an optical circuit assembly, in accordance with an embodiment of the present invention; 
         FIGS. 4A and 4B  show a side view and a back-side view of an optical engine, respectively, in accordance with an embodiment of the present invention; 
         FIGS. 5A and 5B  are isometric views illustrating the structure of an optical engine, in accordance with an embodiment of the present invention; and 
         FIG. 6  is a flow chart that schematically illustrates a method for fabricating an optical engine, in accordance with an embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF EMBODIMENTS 
     Overview 
     Network communication systems, such as Infiniband, can comprise optoelectronic-based connectivity or switching components, such Enhanced Data Rate (EDR) active optical cables, EDR optical module switches, and EDR Host Channel Adapter (HCA) optical modules. These optical components comprise optical engines, which are often regarded as the lowest hierarchical optical building blocks, comprising an optical fiber array which is interfaced to an optoelectronic transducer array. 
     Optoelectronic transducers may comprise, for example, lasers to generate light and photodetectors to detect light, which is routed in optical fibers between the elements of the communication system. Optical modules may also comprise optoelectronic interconnects which couple the control and processing signals from one integrated circuit chip to another chip comprising the optoelectronic transducers. 
     Embodiments of the present invention that are described herein provide improved methods for fabricating optoelectronic interconnects and optical engines. In some embodiments, a semiconductor die comprises an array of optoelectronic transducers such as Vertical Cavity Surface Emitting Lasers (VCSEL) and/or photodetectors (PD). Another semiconductor die comprises ancillary circuitry such as transimpedance amplifiers (TIA) and/or laser drivers. 
     The die comprising the optoelectronic transducers is connected to the die comprising the ancillary circuitry using a novel interconnection mechanism: An edge of the ancillary circuitry die comprises a row of vertical metal-filled conductive via holes (“vias”), whose vertical cross sections become exposed when the die is diced from a semiconductor wafer. The exposed vias form contact pads along the die edge. The die comprising the optoelectronic transducers is connected (e.g., bonded) to these contact pads. 
     This interconnection approach reduces the overall interconnect length between the ancillary circuitry and the optoelectronic transducers, and therefore increases performance and bandwidth. Interconnection of this sort also reduces component count, and simplifies both the optical and mechanical configurations of the optical interconnect, thus reducing cost. 
     In other disclosed embodiments, a die comprising an array of optoelectronic transducers is attached to a vertical face of an L-shaped fixture. A die comprising ancillary circuitry is mounted parallel to the horizontal face of the L-shaped fixture. The L-shaped fixture comprises electrical interconnects coupling the ancillary circuitry on one die to the optoelectronic transducers on the other die. This approach significantly reduces the interconnect length between the ancillary circuitry and the optoelectronic transducers, thus significantly improving performance and bandwidth. The L-shaped fixture also provides a simple and direct coupling of optical fibers to the optoelectronic transducers on the other die. 
     Optoelectronic Interconnect Fabrication 
       FIGS. 1A and 1B  are an isometric view and a cross-sectional view, respectively, of a optoelectronic interconnect, in accordance with an embodiment of the present invention. The optical interconnect is fabricated on a semiconductor die, in the present example a silicon complementary metal oxide semiconductor (CMOS) logic chip  10 . A VCSEL chip  16  and a photodetector (PD) chip  22  are bonded to a side wall edge  28  of chip  10 . Chip  10  comprises ancillary circuitry (not shown in the figure) such as integrated drivers that drive VCSELs  40  with electrical signals, TIAs that amplify electrical signals produced by PDs  41 , and/or any other suitable circuitry. Chip  10  has a typical dimension of 20 mm×20 mm with a thickness of 500-700 μm and is oriented as shown relative to the Cartesian coordinate axes (X,Y,Z). 
     In a typical manufacturing process, multiple dies such as chip  10  are diced from a semiconductor wafer. The internal metallization of chip  10  was configured whereupon dicing the wafer exposes an array of conductive contact vias  34  on the X-Z side wall  28  as shown in  FIG. 1A  as will be described later. Gold contact pads  38  are then formed on exposed vias  34 . VCSEL chip  16  and PD chip  22  are bonded onto contact pads  38 . 
     The VCSEL and PD chips shown in  FIG. 1A  each comprise four individual VCSEL devices  40  and four individual PD devices  41 , respectively, purely for conceptual clarity and not by limitation of the embodiments of the present invention. Both VCSEL chip  16  and PD chip  22  have a device-to-device pitch  42  of about 250 μm. From VCSEL chip  16 , light rays  48  exit the chip as shown in  FIG. 1A  perpendicular to the X-Z plane. Similarly, light rays  56  enter photodiode chip  22  are shown in  FIG. 1A  perpendicular to the X-Z plane. 
     The optical interconnect configuration of  FIG. 1  is an example configuration that is chosen purely for the sake of conceptual clarity. In alternative embodiments, any other suitable configuration can be used. For example, in the present example chip  10  comprises a silicon chip and chips  16  and  22  comprise Gallium Arsenide (GaAs) chips. Alternatively, chips  10 ,  16  and  22  may be fabricated using any other suitable substrate material. In the present example, the VCSEL array and PD array are fabricated in separate chips. Alternatively, VCSELs and PDs may be intermixed in the same chip. Any desired number of chips carrying optoelectronic transducers can be attached to chip  10  in the disclosed manner. The VCSELs and PDs are examples of optoelectronic transducers. In alternative embodiments, any other suitable transducer types can be used. 
       FIG. 1B  is a cross-sectional cut of silicon chip  10  (shown as the region bounded by the dotted lines in  FIG. 1A ) along a front line  100  on the Y-Z plane to a back line  160  on the Y-Z plane according to the Cartesian coordinate axes shown. The semiconductor process used to fabricate the CMOS chips was intentionally reconfigured to allow for a line of vias  34  to be exposed along the edge  28  of die  10  after dicing. 
     In a conventional CMOS process, a multilevel stack  110  of metal layers is shown in  FIG. 1B . Approaching the sides of the intended die fabricated in the wafer prior to dicing, saw rings  115  are placed around the die region where the saw blade cuts the wafer. Saw ring  115  region shown in  FIG. 1B  defines the region where the saw blade cuts the chip during the dicing process and typically does not exist on the final die. 
     The die from a conventional CMOS process would normally terminate with a sealing ring  130  region in which no vertical vias are permitted. However, to accommodate the formation of the exposed side vias, in accordance with the embodiments of the present invention, the CMOS process was reconfigured to add a via side contact ring  150  adjacent to saw ring  115 . The via side contact ring comprises a region in which no metallization is permitted except for one metal feedthrough layer  120  that enables contact between inner metal stack  115  and via  34  within via side contact ring  150 . In this manner, when the die is cut from the wafer along saw ring  115  by a saw, laser etching, or other appropriate cutting procedure, along face  28 , an array of vias  34  is exposed on face  28 . In some embodiments, a gold metal layer is disposed onto vias  34  by methods such as gold deposition or gold plating to form gold metal pads  38 . 
     In other embodiments, vias  34  comprise gold-filled through-silicon vias (TSV), which are utilized in the process and oriented as the vias  34  shown in  FIG. 1B . The gold filled TSV structures traverse die  10  completely from top to bottom side of the wafer (not shown in  FIG. 1A  or  FIG. 1B ). However, upon dicing the wafer along the array of gold filled TSV structures on face  28 , the exposed contacts require no additional disposition of a gold layer to form the gold contact pads. Further alternatively, vias  34  may be fabricated using any other suitable structure or process. 
     VCSEL chip  16  and PD chip  22  can be attached to Si chip  10  by a number of methods. In some embodiments, chips  16  and  22  are attached to chip  10  using a flip-chip process. In an example of such a process, transducers  40  and  41  are located on the side of chips  16  and  22  in contact with face  28 . Chips  16  and  22  comprise backside openings, e.g., thinned regions in the GaAs around each optoelectronic transducer (not shown in  FIG. 1A ), which are configured to provide a more efficient back illumination of the transducers perpendicular to the X-Z plane. The flip chip attachment process uses ball bumps comprising gold-based alloys that are first attached either to the optoelectronic transducer chip contacts or to Si pads  38 . Heating is then used to melt the ball bumps and to attach the optoelectronic transducer chip to the Si both electrically and mechanically. The gold bumps also absorb differences in the temperature expansion coefficients between the Si chip and the GaAs optoelectronic transducer chips during fabrication or normal operation of the device. 
     In other embodiments, VCSEL chip  16  and PD chip  22  can be bonded to Si chip  10  by conducting glues or pastes. The methods for attaching the optoelectronic transducer chips to the side wall of the Si chip described above are for conceptual clarity and not by way of limitation of the embodiments of the present invention. Any appropriate method for attaching the optoelectronic transducer chips to the side wall of the Si chip can be utilized. 
     In some embodiments of the present invention, the VCSEL array and/or PD array can comprise an integrated lens array to couple light rays into 48 or couple light rays  56  out of the die and into fibers that are coupled to these devices (not shown in  FIG. 1A ). In other embodiments, any appropriate configuration of optical interconnects can be formed which directly couples light between optical fibers and the side-mounted optoelectronic transducers. Yet in other embodiments, the top surface of the silicon die can be connected mechanically to a heat sink.  FIG. 2  is a flow chart that schematically illustrates a method for forming the optoelectronic interconnect described above, in accordance with an embodiment of the present invention. In a wafer fabrication step  180 , the Si wafer is fabricated with via side contact rings  150 . In a dicing step  182 , the wafer is diced along saw ring  115  and through the middle of the array of vias  34  on face  28 . In a deposition step  184 , gold metal pads  38  are deposited onto the exposed vias  34  along diced edge face  28  of chip  10 . In an attachment step  186 , gold based flip chip bumps are attached to the gold metal pads  38 . In a bonding step  188 , the VCSEL die  16  and/or PD die  22  are bonded to the bumps and gold metal pads  38 . 
     L-Shaped Optical Engine Fabrication 
       FIG. 3  shows an isometric view of an optical circuit assembly  195 , in accordance with an embodiment of the present invention. Optical Circuit assembly  195  comprises an L-shaped optical engine  200  on which a ferrule  210  is mechanically mounted. The ferrule is mounted on one face of the vertical face of the L-shaped carrier, and directs light between optical fibers  220  from an optical ribbon and optoelectronic transducers that are mounted on the opposite side of the vertical face of the optical engine. (The structure of engine  200  is shown in detail in  FIGS. 4A ,  4 B,  5 A and  5 B below.) 
     A main semiconductor die  230  is mounted parallel to the second face of L-shaped engine  200 . The design of optical circuit assembly  195  shown in the embodiments presented herein significantly reduces the interconnect length between ancillary circuits on main die  230  (typically Si CMOS components, not shown in the figure) and the optoelectronic transducers (typically GaAs) that will be described later. Main die  230  in the present example has a dimension of 20 mm by 20 mm. The ancillary circuits may comprise, for example, TIA and/or driver circuits for the optoelectronic transducers (i.e. VCSEL or photodiodes), or any other suitable transducer type. 
     Main die  230  and optical engine  200  comprising ferrule  210  and fibers  220  are mounted onto a substrate  240 . In the present implementation, up to six optical engines  200  can be mounted on substrate  240  to interface with one main die  230 . With this approach, the distance from optical engine  200  to main die  230  as mounted on substrate  240  is about 100 μm and ensures short interconnect lengths. Substrate  240  may comprise an appropriate printed circuit board material, a large Silicon die, or any other appropriate material. The dimensions given above are chosen by way of example, and any other suitable dimensions can be used in alternative embodiments, 
       FIGS. 4A and 4B  show a side view and a back-side view of optical engine  200 , respectively, in accordance with an embodiment of the present invention. Optical engine  200  comprises an L-shaped fixture comprising a vertical carrier plate  300  and a base carrier plate  310  as shown in  FIG. 4A . 
     The vertical and base carrier plates may each be formed from a two-sided printed circuit board, a silicon die, thin plastic, or any other appropriate material. Vertical carrier plate  300  comprises holes that are etched or drilled through the material. The holes are configured to allow both ferrule  210  to be mounted on one side of vertical carrier plate  300 , and a GaAs die  320  comprising optoelectronic transducers to be mounted on the opposite side. Solder bumps  325  provide support for mounting the optical engine onto corresponding bond pads on the surface of substrate  240 , and allow for electrical connections in the optical engine between the ancillary circuits in main die  230  and GaAs chip  320  through interconnects in substrate  240 . 
     Ferrule  210  has small microtunnels  328  drilled into the body of the ferrule, which allow for thin optical fibers  220  from an optical fiber ribbon (not shown in  FIG. 4A ) to be inserted into the microtunnels and mechanically supported by the ferrule. Ferrule microtunnels  328  also align fibers  220  with fiber holes  330  in vertical carrier plate  300 . Once the fibers from the fiber ribbon are inserted and bonded into the microtunnels, the ferrule can be bonded to the vertical carrier plate by gluing or by spring attachment, for example. Examples of ferrules are MT Ferrules produced by Connected Fibers, Inc. (Roswell, Ga.). A datasheet entitled “MT ferrules,” January, 2009, is incorporated herein by reference. 
     In some embodiments, vertical carrier plate  300  and base carrier plate  310  may be formed from the same flexible printed circuit board that is mechanically folded directly into the L-shaped fixture. In other embodiments as shown in  FIG. 4A , main die  230  may be attached directly to the base carrier plate  310 , which is configured to be large enough to support the main die, and wherein interconnect routing within the fixture is configured to provide an electrical connection to interconnect routing within substrate  240 . In some embodiments, main die  230  is not mounted on base carrier plate  230 , but mounted directly to substrate  240  as shown in  FIG. 3 . 
       FIG. 4B  shows a back-side view of optical engine  200 , in accordance with an embodiment of the present invention. Optoelectronic transducer chip  320  is attached to vertical carrier plate  300  of the L-shaped fixture. Vertical carrier plate  300  comprises a number of holes which are chemically etched or mechanically drilled through vertical carrier plate  300 . The holes through vertical carrier plate  300  are shown in  FIG. 4B  for conceptual clarity as superimposed onto optoelectronic transducer chip  320 , but these holes terminate at an interface  327  between the attached chip  320  to vertical carrier plate  300 . 
     Fiber holes  330  hold the ends of optical fibers  220  extending from the ferrule assembly mounted on the side opposite to chip  320  (not shown in this figure). Holes  330  are configured to align the cleaved fiber ends at interface  327  with optoelectronic transducers  360  (shown as the dotted circles in  FIG. 4B ) on chip  320 . L-shaped optical engine  200  also comprises ferrule guide pin holes  350  which mechanically support guide pins  340  attached to the ferrule housing  210  (not shown in  FIG. 4B ) and terminate at interface  327 , which will be described later. 
     The base and vertical carrier plates comprise interconnect traces  370 , e.g., double-sided printed circuit board and flip chip pads (not shown). Traces  370  route the electrical signals between the base and vertical carrier plates. The optoelectronic transducers  360  on chip  320  are configured in this example in a two-dimensional (2-D) array in order to increase the input/output (I/O) density from chip  320  to main die  230 . 
     In some embodiments, thin interconnect traces  370  have a width of 200 μm to connect the chip  320  to the ancillary circuitry on main die  230 . In other embodiments, traces  370  may comprise microbumps on the base carrier plate to allow for the main die to be mounted directly onto base carrier plate  310  as shown in  FIG. 4A . Yet in other embodiments, chip  320  is connected to main die  230  via traces  370  and bumps  325  on the bottom side of the base plate, and into interconnects on substrate  240  configured to route into the main die. 
       FIGS. 5A and 5B  are isometric views illustrating the structure of the optical engine, in accordance with an embodiment of the present invention.  FIG. 5A  shows a right-sided isometric view of the unassembled L-shaped optical engine comprising holes that are formed through vertical carrier plate  300 , which is attached to the base carrier plate  310 . Ferrule  210  comprises eight fibers  220  from a fiber ribbon (not shown), which are fed through eight holes in the ferrule, and inserted into fiber holes  330  in vertical carrier plate  300 . 
     Ferrule  210  also comprises guide pins  340 , which are fed through guide pin holes  350 , and provide mechanical support for the ferrule within vertical carrier plate  300  after attachment. The length of the fibers  220  and guide pins  340  extending from the ferrule housing are configured so as not to extend past edge  327  after insertion and mounting into vertical carrier plate  300 . The configuration of  FIG. 5A  is shown purely for conceptual clarity and not by way of limitation whatsoever of the embodiments of the present invention. In alternative embodiments, any other suitable configuration can be used. 
       FIG. 5B  shows a left-sided isometric view of the unassembled L-shaped optical engine. Since the placement of fibers  220  and guide pins  340  do not extend past edge  327 , the 2-D pitch of optoelectronic transducers  360  on chip  320  are configured to self-align transducers  360  precisely with the cleaved edge of fibers  220  in fiber holes  330  after the attachment of chip  320 . 
     The height of the vertical carrier plate is determined by the array size of the optoelectronic transducers on chip  320 . Chip  320  comprising a row of VCSEL devices above a row of photodetector devices has a height of 500 μm. In VCSEL/PD array of 12 devices (not shown), the length of the chip is about 3200 μm. For the VCSEL/PD array comprising four devices shown in  FIG. 5B , the length of the chip is about 1200 μm. Typically, the vertical carrier plate thickness is about 0.1 mm. 
     This configuration allows for self-aligned coupling of light between the optoelectronic transducers and the fibers fed through the microtunnels of the ferrule mounted on vertical carrier plate  300 . The dimensions above are given purely by way of example, and any other suitable dimensions can be used in alternative embodiments. 
     In some embodiments, the optoelectronic transducers comprise respective integrated lenses formed in the GaAs chip  320 . In other embodiments, optical fibers  220  comprise lenses that are formed on the edge of each fiber prior to insertion and assembly within the ferrule and vertical carrier plates. In some embodiments, lenses are integrated into fiber holes  330  and embedded within the vertical carrier plate. In other embodiments, the height of the vertical carrier plate can be configured to allow mounting for both the optoelectronic transducer die and the main die on the vertical carrier plate e.g., the same face. 
     The mechanical configuration shown in  FIGS. 4A ,  4 B,  5 A and  5 B is an example configuration that is shown purely for the sake of conceptual clarity. In alternative embodiments, any other configuration, in which a transducer die is mounted on one face of an L-shaped fixture and an ancillary circuitry die is mounted parallel to the other face of the fixture, can be used. 
       FIG. 6  is a flow chart that schematically illustrates a method for fabricating the optical engine, in accordance with an embodiment of the present invention. In a fabrication step  400 , base carrier plate  310  and vertical carrier plate  300  are fabricated, which are utilized to form optical engine  200 . In an attachment step  410 , the fiber ribbon is attached to ferrule  210  wherein fibers  220  are fed through and mounted in microtunnels  328  preformed in the housing of the ferrule. In a bonding step  420 , ferrule  210  and fibers  220  from the fiber ribbon are bonded to vertical carrier plate  300  using guide pins  340  to hold the ferrule in place. 
     In a first bonding step  430 , optoelectronic transducer chip  320  is bonded to vertical carrier plate  300  on the side opposite to ferrule  210  completing the assembly of optical engine  200 . In a second bonding step  440 , main die  230  is bonded to substrate  240 . In a third bonding step  450 , optical engine  200  is then bonded to substrate  240  to complete optical circuit assembly  195 . 
     Although the embodiments described herein mainly relate to the fabrication of optoelectronic interconnects and optical engines, the methods described herein can also be used in other applications, wherein integrated optoelectronic interconnects or integrated optical engines comprising self-aligned fibers with optoelectronic transducer chips are required for different optical system applications. 
     It will thus be appreciated that the embodiments described above are cited by way of example, and that the present invention is not limited to what has been particularly shown and described hereinabove. Rather, the scope of the present invention includes both combinations and sub-combinations of the various features described hereinabove, as well as variations and modifications thereof which would occur to persons skilled in the art upon reading the foregoing description and which are not disclosed in the prior art. Documents incorporated by reference in the present patent application are to be considered an integral part of the application except that to the extent any terms are defined in these incorporated documents in a manner that conflicts with the definitions made explicitly or implicitly in the present specification, only the definitions in the present specification should be considered.