Patent Publication Number: US-11640118-B2

Title: Method of pattern alignment for field stitching

Description:
INCORPORATION BY REFERENCE 
     This present disclosure claims the benefit of U.S. Provisional Application No. 63/066,779, filed on Aug. 17, 2020, the entire content of which is incorporated herein by reference. 
    
    
     FIELD OF THE INVENTION 
     This disclosure relates generally to methods of fabricating semiconductor devices and specifically to overlay error and pattern alignment. 
     BACKGROUND 
     Semiconductor fabrication involves multiple varied steps and processes. One typical fabrication process is known as photolithography (also called microlithography). Photolithography uses radiation, such as ultraviolet or visible light, to generate fine patterns in a semiconductor device design. Many types of semiconductor devices, such as diodes, transistors, and integrated circuits, can be constructed using semiconductor fabrication techniques including photolithography, etching, film deposition, surface cleaning, metallization, and so forth. 
     Microfabrication involves forming and processing multiple films and layers on a wafer. This can include dozens or more films stacked on a wafer. Patterns applied to the wafer for various films and layers need to be aligned to previously-formed patterns. Conventionally, such alignment is realized by using part of the wafer to form alignment marks and scribe lines. However, the present inventors have recognized that the various film deposition, etching, and treatment techniques at times cover the alignment marks and even completely remove the alignment marks. With alignment marks at times covered or missing, there can be errors applying subsequent patterns on the wafer. The term overlay or overlay error refers to the difference between placement of given pattern relative to a previously-placed pattern. With alignment marks routinely destroyed, overlay error can accumulate with additional layers, which can cause poor performance and device error. 
     Extreme ultraviolet (EUV) lithography (also known as EUVL) is a state-of-the-art microfabrication technique that uses a range of EUV wavelengths, e.g. 13.5 nm. Because of the short wavelength of EUV light, EUV lithography allows exposure of fine patterns with a half pitch (HP) smaller than 20 nm. An EUV tool can include a radiation system for supplying a beam of EUV light, a mask stage for holding an EUV photomask, a wafer stage for holding a wafer, and projection optics for imaging an irradiated portion of the EUV photomask onto a target portion of the wafer. 
     SUMMARY 
     The present disclosure relates to a method of pattern alignment. 
     An aspect (1) includes a method of pattern alignment. The method includes identifying a reference pattern positioned below a working surface of a wafer. The wafer is exposed to a first pattern of actinic radiation. The first pattern is a first component of a composite pattern. The first pattern of actinic radiation is aligned using the reference pattern. The wafer is exposed to a second pattern of actinic radiation. The second pattern is a second component of the composite pattern and exposed adjacent to the first pattern. The second pattern of actinic radiation is aligned with the first pattern of actinic radiation using the reference pattern. 
     An aspect (2) includes the method of the aspect (1), further including measuring a first overlay value between the first pattern and the reference pattern to align the first pattern. A second overlay value between the second pattern and the reference pattern is measured. A third overlay value between the first pattern and the second pattern is calculated based on the first overlay value and the second overlay value. The second pattern is aligned with the first pattern using the third overlay value. 
     An aspect (3) includes the method of the aspect (2), further including capturing an image of the reference pattern, an image of the first pattern and an image of the second pattern. The first overlay value is measured by analyzing the image of the reference pattern and the image of the first pattern. The second overlay value is measured by analyzing the image of the reference pattern and the image of the second pattern. 
     An aspect (4) includes the method of the aspect (1), further including identifying first coordinate locations of the first pattern relative to the reference pattern. Second coordinate locations of the second pattern relative to the reference pattern are identified. An overlay value is calculated using the first coordinate locations and the second coordinate locations. The second pattern is aligned with the first pattern using the overlay value. 
     An aspect (5) includes the method of the aspect (1), further including forming a resist layer on the working surface of the wafer. The resist layer includes a photo-reactive species that is configured to form the composite pattern. 
     An aspect (6) includes the method of the aspect (5), further including forming an intrafield alignment mark outside a device area or below the resist layer in the device area. The first pattern is aligned with the intrafield alignment mark using the reference pattern. The second pattern is aligned with the intrafield alignment mark using the reference pattern. 
     An aspect (7) includes the method of the aspect (5), further including developing the resist layer so that first features of the first pattern connect with second features of the second pattern. 
     An aspect (8) includes the method of the aspect (1), further including exposing the wafer to one or more additional patterns of actinic radiation. The one or more additional patterns are additional components of the composite pattern. The one or more additional patterns of actinic radiation are aligned using the reference pattern. 
     An aspect (9) includes the method of the aspect (1), further including exposing a plurality of wafers to the first pattern of actinic radiation in a first pass when the plurality of wafers is placed on a wafer stage of a lithography tool. The wafers are transferred from the wafer stage to a wafer stocker of the lithography tool. Masks are switched for a mask stage of the lithography tool. The wafers are transferred from the wafer stocker to the wafer stage. The wafers are exposed to the second pattern of actinic radiation in a second pass. 
     An aspect (10) includes the method of the aspect (1), further including exposing a plurality of wafers to the first pattern of actinic radiation in a first pass when the plurality of wafers is placed on a wafer stage of a lithography tool. Masks are switched for a mask stage of the lithography tool when the wafers are on the wafer stage. The wafers are exposed to the second pattern of actinic radiation in a second pass when the wafers are on the wafer stage. 
     An aspect (11) includes the method of the aspect (1), further including exposing the wafer to the first pattern of actinic radiation through a first mask having the first pattern to print a first latent image on the wafer such that the first latent image is de-magnified compared to the first pattern on the first mask. The wafer is exposed to the second pattern of actinic radiation through a second mask having the second pattern to print a second latent image on the wafer such that the second latent image is de-magnified compared to the second pattern on the second mask. 
     An aspect (12) includes the method of the aspect (1), wherein the first pattern of actinic radiation includes an extreme ultraviolet (EUV) wavelength or a deep ultraviolet (DUV) wavelength. The second pattern of actinic radiation includes an EUV wavelength or a DUV wavelength. 
     An aspect (13) includes the method of the aspect (1), wherein the reference pattern is incorporated in a reference plate positioned on or adhered to a backside of the wafer. 
     An aspect (14) includes the method of the aspect (1), wherein the reference pattern is incorporated in a reference plate incorporated in a substrate holder of a lithography scanner or stepper. 
     An aspect (15) includes the method of the aspect (1), wherein the reference pattern is formed on a backside of the wafer or embedded within the wafer. 
     An aspect (16) includes the method of the aspect (1), wherein the reference pattern includes a radioactive or fluorescent material. 
     An aspect (17) includes the method of the aspect (1), wherein the reference pattern includes at least one of a point, a line, a corner, a box, a triangle, a number or a mark. 
     An aspect (18) includes the method of the aspect (1), further including identifying the reference pattern positioned below the working surface of the wafer via quantum tunneling imaging or infrared (IR) transmission imaging. 
     An aspect (19) includes the method of the aspect (1), wherein the reference pattern is projected on a surface of the wafer. 
     An aspect (20) includes a method of pattern alignment. The method includes imaging a reference plate positioned below a wafer via quantum tunneling imaging or infrared (IR) transmission imaging. The reference plate includes a reference pattern. A first pattern of actinic radiation is aligned using the reference pattern. The first pattern is a first component of a composite pattern. A first field of the wafer is exposed to the first pattern of actinic radiation. A second pattern of actinic radiation is aligned using the reference pattern. The second pattern is a second component of the composite pattern. A second field of the wafer is exposed to the second pattern of actinic radiation. The second field is adjacent to the first field. 
     Note that this summary section does not specify every embodiment and/or incrementally novel aspect of the present disclosure or claimed invention. Instead, this summary only provides a preliminary discussion of different embodiments and corresponding points of novelty. For additional details and/or possible perspectives of the invention and embodiments, the reader is directed to the Detailed Description section and corresponding figures of the present disclosure as further discussed below. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be increased or reduced for clarity of discussion. 
         FIG.  1 A  shows an exemplary diagram of an extreme ultraviolet (EUV) tool. 
         FIG.  1 B  illustrates examples of de-magnification in a projection printing system. 
         FIG.  1 C  shows a simplified schematic of stitching in a projection printing system. 
         FIG.  2 A  shows an industrial problem of overlay. 
         FIG.  2 B  shows overlay alleviation using a reference pattern, in accordance with exemplary embodiments of the present disclosure. 
         FIG.  3 A  shows a schematic of aligning a wafer using a reference pattern, in accordance with exemplary embodiments of the present disclosure. 
         FIG.  3 B  shows a reference plate, in accordance with exemplary embodiments of the present disclosure. 
         FIGS.  4 A and  4 B  show image analysis without and with a reference pattern, respectively, in accordance with exemplary embodiments of the present disclosure. 
         FIG.  4 C  shows a detailed view of the rectangle  400 C in  FIG.  4 B , in accordance with exemplary embodiments of the present disclosure. 
         FIG.  4 D  shows overlay calculation using a reference pattern as shown in  FIG.  4 C , in accordance with exemplary embodiments of the present disclosure. 
         FIGS.  5 A,  5 B and  5 C  show top-down views of a wafer stage at intermediate steps of stitching, in accordance with embodiments of the present disclosure. 
         FIG.  5 D  shows an expanded view of the dotted rectangle  500 D in  FIG.  5 C , in accordance with embodiments of the present disclosure. 
         FIG.  6    shows a flow chart of an exemplary process for processing a wafer, in accordance with exemplary embodiments of the present disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “top,” “bottom,” “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature&#39;s relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. 
     The order of discussion of the different steps as described herein has been presented for clarity sake. In general, these steps can be performed in any suitable order. Additionally, although each of the different features, techniques, configurations, etc. herein may be discussed in different places of this disclosure, it is intended that each of the concepts can be executed independently of each other or in combination with each other. Accordingly, the present invention can be embodied and viewed in many different ways. 
     As noted in the Background, extreme ultraviolet (EUV) lithography is an important technique for microfabrication. US patents (e.g. U.S. Pat. Nos. 6,459,472B1 and 6,232,615B1, each of which is incorporated herein by reference in its entirety) by Advanced Semiconductor Materials Lithography (ASML), Netherlands include examples of EUV tools. “EUV tool” as used herein generically refers to any lithography tool including an EUV light source. The EUV tool may include an EUV tool having a numerical aperture (NA) smaller than 0.5 (e.g. NA=0.33), a high-NA EUV tool (NA&gt;0.5, e.g. NA=0.55) or the like. 
       FIG.  1 A  shows an exemplary diagram of an EUV tool  100 . As shown, the EUV tool  100  includes a radiation system  110  for supplying a beam of EUV light which is represented by arrows. The radiation system  110  includes an EUV light source  111 , such as a laser-driven tin (Sn) plasma light source, which produces the beam of EUV light. While not shown, the radiation system  110  can also include optical components, such as a condenser lens, selective mirrors, an intensity integrator and/or the like. The optical components are configured such that the beam of EUV light going out of the radiation system  110  can be substantially collimated, uniform and monochromatic. 
     The EUV tool  100  also includes a mask stage  120  for holding an EUV mask  121 . The EUV mask  121  can reflect the beam of EUV light by using multiple (e.g. forty) alternating layers of molybdenum (Mo) and silicon (Si), in contrast to conventional photomasks which use a single chromium layer on a quartz substrate to block light. The multiple alternating layers function to reflect the beam of EUV light by Bragg diffraction. Therefore, the EUV mask  121  is a reflective mask. A pattern can be defined in a tantalum-based absorbing layer over the multiple alternating layers. Because nearly everything absorbs EUV radiation, EUV lithography is executed in a vacuum environment. Moreover, many optical elements, including the EUV mask  121 , may need to use defect-free Mo/Si multilayers to reflect EUV light by means of interlayer interference. 
     The EUV tool  100  further includes optics  130  having projection optics  131 , and a wafer stage  140  for holding a wafer  141 . The projection optics  131  are configured for imaging an irradiated portion of the EUV mask  121  onto a target portion (e.g. a field or a die) of the wafer  141 . The projection optics  131  can include a lens, a mirror group, a catadioptric system, a particle focusing system and/or the like. 
     Still referring to  FIG.  1   , the EUV mask  121  is placed away from the wafer  141  and a pattern of the EUV mask  121  is focused onto the wafer  141  through the projection optics  131 . The projection optics  131  can be configured such that an image printed on the wafer  141  is de-magnified compared to the original pattern of the EUV mask  121 , thus enhancing resolution. Unlike conventional contact printing or proximity printing systems in which a photomask (also known as a mask) usually covers an entire wafer, a projection photomask (also known as a reticle) usually shows only one die (also known as a field) or an array of dies because of de-magnification. 
     Higher demagnification is pursued in next-generation EUV tools, particularly when a high numerical aperture (NA) lens system is used. Nevertheless, higher demagnification may necessitate the use of larger mask sizes or lead to a reduced size of the printed field. On the one hand, fabricating a larger mask to compensate is not desirable due to manufacturing complexity, but on the other hand, smaller fields may result in a need for “stitching” or acceptance of substantially reduced throughput, aggravating an already existing problem in EUV lithography. Specifically, reducing the field size can divide a full-sized chip pattern (e.g. 26 mm×33 mm) among two or more conventional 6-inch EUV photomasks. Large chips, such as chips used for graphics processing units (GPUs), may thus need to be stitched together from two or more component patterns to form a complete, composite pattern. The two or more component patterns often require two or more photomasks, and changing photomasks during lithography can undesirably reduce EUVL throughput. Furthermore, features that are located near or across field boundaries can have alignment errors. 
       FIG.  1 B  illustrates examples of de-magnification in a projection printing system, for example in an EUV tool. As shown, a projection photomask  160  (e.g. an EUV mask) can be de-magnified by projection optics  170 , isomorphically or anamorphically, to various degrees. In a non-limiting example, the projection photomask  160  has lateral dimensions of 104 mm and 132 mm in the x and y directions, respectively. In one embodiment, the projection photomask  160  has a 4× isomorphical de-magnification. As a result, a first image  161  printed on a wafer has lateral dimensions of 26 mm and 33 mm in the x and y directions, respectively. Note that 26 mm×33 mm can be the lateral dimensions of a chip pattern. In another embodiment, the projection photomask  160  has an 8× isomorphical de-magnification. Accordingly, a second image  163  printed on the wafer has lateral dimensions of 13 mm and 16.5 mm in the x and y directions, respectively. In another embodiment, the projection photomask  160  has an anamorphical de-magnification, with a 4× de-magnification in the x direction and an 8× de-magnification in the y direction. Consequently, a third image  165  printed on the wafer has lateral dimensions of 26 mm and 16.5 mm in the x and y directions, respectively. 
     As a matter of fact, in today&#39;s 0.33 NA EUV tool (e.g. TWINSCAN NXE:3400B by Advanced Semiconductor Materials Lithography (ASML), Netherlands), the isomorphic lens can support 4× de-magnification with a maximum scanned exposure field size of 26 mm×33 mm. In a high-NA EVU tool (e.g. NA=0.55, EXE:5000, ASML, Netherlands), however, the anamorphic lens can support 8× de-magnification in a scanning direction and 4× de-magnification in a perpendicular direction. As  FIG.  1 B  illustrates, such size reduction or de-magnification provides distinct scaling advantage for improving resolution but also limits the size of exposure by shrinking the image field size. That is, a larger than usual mask would be required if a complete image of the entire wafer were formed in one exposure or printing. However, fabricating such a large mask to compensate is not desirable due to manufacturing complexity. As a result, repeated projection and/or projection of multiple masks onto different areas of the wafer is often required to create a complete pattern. For instance, this can involve a process of exposing one part of a composite pattern with one mask and then exposing another part of the composite pattern with another mask. Then, patterns of the two masks are developed and stitched together. 
       FIG.  1 C  shows a simplified schematic of stitching in projection printing, for example in an EUV tool. Herein, a projection printing system  180  prints a photomask (not shown) on a first area  191  of a wafer  190 . The first area  191  can, for instance, include a first die or field. The wafer  190  also includes a second area  192  (e.g. a second die or field) adjacent to the first area  191 . Note that while the wafer  190  only has two areas (i.e.  191  and  192 ) in the example of  FIG.  1 C , the wafer  190  can have any number of areas in other embodiments, as dictated by a size of the wafer  190 , a size of the photomask, degree of de-magnification, etc. In one embodiment, the projection printing system  180  prints a same image on the second area  192  as on the first area  191  using a same photomask. In another embodiment, the projection printing system  180  prints a different image on the second area  192  using a different photomask so that images on the first area  191  and the second area  192  form a composite pattern. This process is an example of stitching or field stitching. 
     Field stitching is important to overcome reticle size limitations for high-NA EUV lithography. Without field stitching, die size is likely to be limited. In actuality, high-NA EUV lithography often requires stitching of multiple fields to create a die size that is commensurate with high volume manufacturing (HVM) chip design. During the process of field stitching, photomasks may need to be well aligned to minimize overlay error. Large overlay error can lead to faulty electric connections between component patterns or neighboring layers, and therefore cause device malfunction or even chip failure. 
     Techniques herein include a method of “stitching” patterns together. In lithographic patterning, it is sometimes the case that a given desired pattern size for a chip is larger than the exposure capability of a given system. To pattern the desired chip size, a composite pattern is needed. In other words, two or more exposures (using two or more masks) may be needed to combine component patterns together. Because of overlay issues, aligning the component images to connect properly can be challenging. 
     Techniques herein include a method of complementary stitching between different lithography techniques or tools. A first pattern of actinic radiation and a second pattern of actinic radiation may include a same light or two different lights. For example, the first pattern of actinic radiation and the second pattern of actinic radiation can independently include an extreme ultraviolet (EUV) wavelength (e.g. 13.5 nm) or a deep ultraviolet (DUV) wavelength (e.g. 193 nm). 
     Techniques herein use see-through wafer technology and an independent reference pattern or plate to properly stitch together (align and expose) two or more component patterns. A reference plate positioned under a wafer provides constant and accurate reference points. A quantum tunneling imaging system combined with a surface imaging system is used to capture an image of a reference pattern in coordinate relation to a first component pattern. Coordinate placement of a second component pattern can then be executed knowing many points on the first pattern to make sure features are properly aligned and connected. 
     Techniques herein use a reference pattern to align a pattern, as disclosed in our patent applications titled “Method for Producing Overlay Results with Absolute Reference for Semiconductor Manufacturing” (U.S. patent application Ser. Nos. 17/404,566 and 17/404,591), each of which is incorporated herein by reference in its entirety). Techniques herein use a coaxial see-through alignment imaging system, as disclosed in our patent applications titled “Coaxial See-Through Alignment Imaging System and Method” (U.S. patent application Ser. Nos. 17/404,669 and 17/404,687), each of which is incorporated herein by reference in its entirety). 
     This disclosure reveals some embodiments in which an apparatus or tool to see through a semiconductor wafer to image a pattern within or below the wafer. This see-through technology can be used to compare a pattern or reference below or within the wafer with a pattern on a working surface (e.g., a top surface or a front side) of the wafer. 
     Techniques herein include an imaging system that can coaxially align two light beams of different wavelengths, focus the two coaxially aligned light beams onto a first pattern located on a top surface of a substrate and a second pattern positioned below the first pattern, and capture images of the first and second patterns. For example, the imaging system can include a first light source, a second light source, an alignment module, a coaxial module, a first image capturing device, and a second image capturing device. 
     Techniques include a coaxial imaging system. In some embodiments, a first wavelength light such as ultraviolet (UV) wavelength light is directed at a target on a wafer coaxially with a second wavelength light such as infrared (IR) light. Image sensors capture images resulting from both the UV light and the IR light. With images captured in a same axis and superimposed, a comparison can be made for exposure, inspection, alignment or other processing. Although the UV and IR images are captured coaxially, transmission to an image detector may or may not be coaxial. For example, the coaxially captured images may be optically separated and transmitted to separate image detectors as discussed below. 
     This present disclosure discloses a method for wafer alignment and see-through wafer alignment detection. Techniques herein use a light source with a wavelength and power sufficient to tunnel through wafer material to image alignment marks within the wafer or beneath the wafer. This see-through imaging provides an accurate and precise alignment mechanism that does not rely on conventional alignment marks formed on a working surface (e.g., top surface or a front side) of a wafer. Instead, with reference to a pattern or grid within/below the wafer, a reliable reference can be repeatedly accessed for precise and accurate registration and alignment of subsequent patterns. 
     Techniques herein use see-through wafer technology for wafer inspection and detection. Systems and methods herein can identify overlay error and defects in wafers including inspection relative to a reference pattern and inspection of intermediate layers. In some embodiments, intermediate layers may be inspected by use a light source with a wavelength and power sufficient to tunnel through wafer material and focus on a patterned layer formed in the wafer but covered by subsequent wafer processing. 
     With techniques herein, it is no longer necessary to create and re-create alignment marks. Conventionally there is no independent grid or plate reference. All overlay corrections then must account for different tools and corrections signatures. Also, there is no independent reference point for an initial pattern placed on a fresh wafer. Instead, an initial pattern is placed on a new wafer and assumed to be perfect, as if it were formed using a golden tool. In reality, however, this foundation on blind trust is flawed. There are many factors that can affect the initial pattern, such as drive motor precision and calibration curve errors among others. As such, distortion maps are used from the outset. And then moving from mark A to mark B or from layer to layer creates and compounds overlay error. 
       FIG.  2 A  illustrates an industrial problem of overlay. Each arrow herein has a starting point (e.g.  211   a ), which corresponds to a position of a preceding pattern, and an endpoint or arrowhead (e.g.  211   a ′), which corresponds to a position of a subsequent pattern. As a result, each arrow represents an overlay value or overlay error when the subsequent pattern is formed over or side by side with the corresponding preceding pattern. In a process  210 A for example, there is no grid or plate reference when placing an initial pattern. Thus, a starting point  211   a  of a first arrow is likely to be misaligned, that is, the initial pattern can have placement error, for example relative to an edge of the wafer. Then subsequent patterns try to align based on the corresponding last pattern. As illustrated in  FIG.  2 A , a starting point (e.g.  211   b ) of a subsequent arrow overlaps with an arrowhead (e.g.  211   a ′) of a corresponding last or preceding arrow. In some examples, deterioration of alignment marks can cause alignment error for subsequent patterns placed by using such deteriorated alignment marks. Note that even in a theoretically perfect system, walkout can still occur. For example, if a system pattern placement tolerance is +/−4 nm and each level references a previous level. Take a reference level to be 0 error. A first layer then could be +4 nm off. A second layer alignment to the first layer could be +4 nm off, meaning the second layer is now +8 nm off the reference level. There are also process factors that induce or relieve stress throughout fabrication that can induce walkout/alignment shift even with pristine alignment marks visible that can add to accumulated error. 
     Further, alignment marks may be destroyed at a step S 220  in a process, and placement again happens without a reference mark. Similar to the starting point  211   a , a starting point  221   a  of a new arrow is likely to be misaligned. In the example of  FIG.  2 A , the starting point  221   a  deviates from an arrowhead  211   n ′. The process proceeds by aligning subsequent patterns based on the corresponding last pattern until alignment marks are destroyed again at a step S 230 . Similarly, placement happens without a reference mark, and a starting point  231   a  deviates from an arrowhead  221   n ′. As can be seen in  FIG.  2 A , as layers increase, the overlay error can accumulate, leading to poor manufacturing yields, device error, etc. Note that the process  210 A is a non-limiting example. Other processes (e.g.  210 B and  210 C) may have different overlay values (different arrows) and/or different steps. 
       FIG.  2 B  shows overlay alleviation using a reference pattern, in accordance with exemplary embodiments of the present disclosure. While not shown, with techniques herein, all patterns placed on a wafer are based on a same reference pattern. In some embodiments, a reference grid can be used and considered absolute, or rather, independent of any patterns on the wafer. In one embodiment, the (independent) reference grid is compared to the wafer when placing a new pattern. For an initial pattern, this means that the pattern can be fitted to the reference grid. For subsequent patterns, this means that one or more patterns can be compared to the reference grid to calculate overlay correction to return to same alignment. 
     For example, in a process  240 , a reference pattern (not shown) is used to align an initial pattern on a wafer. In one embodiment, the reference pattern can be provided in a fixed position relative to the wafer surface such as by bonding the reference to a backside of the wafer or embedding the pattern within the wafer. Consequently, a starting point  241   a  of a first arrow is aligned to the fixed reference pattern, whose position is demonstrated as a line  250 . Subsequent patterns are also aligned using the reference pattern. A new photoresist layer may be formed for each subsequent pattern, but no alignment marks need to be formed and/or destroyed on the wafer because of the reference pattern. As a result, arrows center around the line  250 , meaning that the subsequent patterns are aligned to the reference pattern. Overlay error is therefore unlikely to accumulate as more and more layers are formed. Note that in some embodiments, the reference pattern is positioned below a working surface (e.g., a top surface or a front side) of the wafer, on which the subsequent patterns are formed. Hence, the reference pattern is independent of the working surface of the wafer. In other words, the reference pattern is not affected by lithographic processes, such as etching, deposition, chemical mechanical polishing and the like, which are performed on the working surface of the wafer in order to form patterns. 
       FIG.  3 A  shows a schematic  300 A of aligning a wafer using a reference pattern, in accordance with exemplary embodiments of the present disclosure. As shown, a wafer  310  has a front side  311  (also referred to as a working surface) and a backside  319 . In the example of  FIG.  3 A , an imaging system  380  is used to image a resist layer  320  formed on the front side  311  and a reference pattern  351  positioned on the backside  319 . 
     As illustrated in  FIG.  3 A , the imaging system  380  includes a first beam of light  330  that is used to image a topside pattern (e.g.  321   a ) on the front side  311  of the wafer  310 . The imaging system  380  also includes a second beam of light  340  that is configured to tunnel through the wafer  310  in order to image the reference pattern  351 . The first beam of light  330  and the second beam of light  340  are configured to be co-axially aligned so that an image of the topside pattern captured by the first beam of light  330  and an image of the reference pattern  351  captured by the second beam of light  340  can be analyzed to determine where the topside pattern is positioned, relative to the reference pattern  351 . 
     In some embodiments, the image of a pattern and the image of the reference pattern  351  are analyzed so that coordinate locations of the pattern relative to the reference pattern  351  can be determined. For example, the images may be superimposed in the same physical space, or effectively superimposed by comparing coordinate location data collected from the reference pattern  351  and the pattern to perform vector analysis for determining gross offset. As a result, the pattern can be aligned using the reference pattern  351 . Alignment may occur, for example, by moving a mask of the pattern image or moving the wafer relative to a fixed mask. In some embodiments, the resist layer  320  is exposed and a latent pattern  321   a  is formed in the resist layer  320 . In one embodiment, the latent pattern  321   a  is then developed, and a physical pattern is thus formed in the resist layer  320 . In another embodiment, in a “step-and-repeat” or “step-and-scan” system, the two beams of light and the photomask may move to another area of the wafer  310  as indicated by the hollow arrow in  FIG.  3 A , and the process is repeated to form one or more latent patterns (e.g.  321   n ) in the resist layer  320 . Under this circumstance, latent patterns are exposed separately but will be developed together. 
     While not shown in  FIG.  3 A , the imaging system  380  may further include alignment optics in addition to sensors or cameras for capturing images resulting from the first beam of light  330  and the second beam of light  340 . The alignment optics are configured such that the first beam of light  330  and the second beam of light  340  are coaxially aligned for imaging different planes. In other words, the imaging system  380  can coaxially align two light beams of different wavelengths (e.g.  330  and  340 ), focus the two coaxially aligned light beams onto a topside pattern (e.g.  321   a ) located on the front side  311  of the wafer  310  and a reference pattern (e.g.  351 ) positioned below the topside pattern (e.g.  321   a ), and capture images of the topside pattern (e.g.  321   a ) and the reference pattern (e.g.  351 ). 
     Still referring to  FIG.  3 A , the reference pattern  351  is positioned on the backside  319  of the wafer  310 . In one embodiment, the reference pattern  351  is formed on the backside  319  of the wafer  310  and thus fixed to the wafer throughout processing of that wafer. In another embodiment, the reference pattern  351  is incorporated in a reference plate, such as a reference plate  300 B as demonstrated in  FIG.  3 B . In the example of  FIG.  3 B , the reference plate  300 B is a grid plate with 20 micron by 20 micron squares (e.g.  353 ), nearly perfectly aligned. In this embodiment, the precision of the grid plate will determine the alignment capabilities of a patterning or inspection system. Accordingly, the grid plate should be obtained from a manufacturer capable of forming the grid plate within predetermined degree of manufacturing tolerance. Alternatively, the reference plate  300 B may include at least one of a point, a line, a corner, a box, a number, a mark or any other pattern that is suitable for alignment purposes. The reference plate  300 B may be adhered to the backside  319  of the wafer  310  or incorporated in a substrate holder of a photolithography tool such as a scanner or stepper. 
     While the reference pattern  351  is positioned on the backside  319  of the wafer  310  in the  FIG.  3 A  example, the reference pattern  351  may be placed within the wafer  310  in another example. That is, the reference pattern  351  is placed below the front side  311  of the wafer  310 , whether below or within the wafer  310 , such that the reference pattern  351  is independent of the front side  311  of the wafer  310  and the resist layer  320 . Moreover, the reference pattern  351  is independent of any pattern (e.g.  321   a ) formed or to be formed on the front side  311  of the wafer  310 . 
     In a non-limiting example, a photomask (not shown) that includes a pattern is positioned on the front side  311  of the wafer  310 . The photomask may be placed in direct contact with the wafer  310  in a contact printing system. The photomask may be placed away from the wafer  310  in a proximity printing system or in a projection printing system. Before printing the pattern on the wafer  310 , the photomask, or rather, the pattern is aligned using image analysis that is enabled by the reference pattern  351  and the imaging system  380 . 
     In one embodiment, the pattern is an initial pattern and can therefore be aligned to the reference pattern. For example, the reference pattern may include grids of lines such that the pattern is aligned to the grids of lines. In another embodiment, the pattern is a subsequent pattern which is placed over or side by side with a preceding pattern. In some embodiments, in order to align the subsequent pattern, the preceding pattern is imaged relative to the reference pattern using the imaging system  380 , and the subsequent pattern is also imaged relative to the reference pattern using the imaging system  380 . An overlay value of the second pattern relative to the first pattern may then be determined. Further details regarding image analysis and overlay calculation will be explained in  FIGS.  4 A- 4 D . 
       FIGS.  4 A and  4 B  show image analysis without and with a reference pattern, respectively, in accordance with exemplary embodiments of the present disclosure. In  FIG.  4 A , images of two patterns are superimposed on each other, resulting in an image  400 A. In this example, the image  400 A includes a plurality of lines and dots from a first pattern represented in black (e.g.  410 ), as well as lines and dots of a second pattern represented in gray (e.g.  420 ). This figure demonstrates that it can be difficult to accurately align the lines and the dots of one pattern to the lines and the dots of the other pattern without a reference pattern. 
     The embodiment of an image  400 B in  FIG.  4 B  is similar to the embodiment of the image  400 A in  FIG.  4 A , except that the image  400 B further includes a superimposed image of a reference pattern. In a non-limiting example, the reference pattern includes an array of boxes (e.g.  430 ). This figure demonstrates that the array of boxes can be used to guide alignment of the two patterns. In other embodiments, the reference pattern can include at least one of a point, a line, a corner, a box, a number, a mark or any other pattern that is suitable for alignment purposes. 
     As noted above, the reference pattern may be fixed to the wafer (e.g., by bonding to a backside or embedding within the wafer) or separate from the wafer (e.g., by use of a grid plate or incorporating the reference into a substrate holder). The fixed reference provides an advantage in that each individual pattern can be aligned on the wafer by using only the fixed reference pattern without considering the relative placement of other patterns previously formed on the wafer. However, special processing of the wafer to provide the fixed reference may be undesirable, in which case a separate reference such as a grid plate can be used. Where a separate grid plate is used, the overlay between two patterns may be calculated to account for changes in the position of the wafer relative to the grid plate when the wafer is moved between tools or processes. 
       FIG.  4 C  shows a detailed view of the rectangle  400 C in  FIG.  4 B , and  FIG.  4 D  further demonstrates overlay calculation using the reference pattern in  FIG.  4 C , in accordance with exemplary embodiments of the present disclosure.  FIGS.  4 C and  4 D  show how an independent reference pattern can be used to calculate an overlay value of two patterns. This is done by knowing each common reference to a co-ordinate system and using that reference to know “where” each pattern is in that co-ordinate system. Once that is known, for example the distance between each layer, the vector calculation required to extract the overlay value is done with simple vector algebra. One can think of it as mix-match overlay (MMO) with a golden tool always there for oneself under the stage. 
     In a non-limiting example, a reference point M of the reference pattern is used to calculate an overlay value between a point N of a first pattern and a point P of a second pattern. Herein, boxes (e.g.  430 ) or lines (e.g. AA′, BB′, CC′, DD′, EE′ and FF′) are grid lines of a reference pattern. The point M is a corner of the box  430  as well as an intersection point of the lines AA′ and DD′. The point N is an intersection point of the lines BB′ and EE′. The point P is an intersection point of the lines CC′ and FF′. This reference pattern can be imaged and precisely superimposed on an image of one or more patterns (e.g. the first pattern and the second pattern). Accordingly, by analyzing superimposed images, coordinate locations of patterns can be identified and then overlay calculated. 
     In a non-limiting example, the box  430  provides a reference point M that is absolute or wafer-independent. By superimposing a first pattern on the reference pattern, a coordinate difference or vector {right arrow over (MN)} from the reference point M to the point N of the first pattern is determined. Likewise, by superimposing a second pattern on the reference pattern, a coordinate difference or vector {right arrow over (MP)} from reference point M to the point P of the second pattern is determined. Then, an overlay value {right arrow over (NP)} between the point N and the point P can be calculated: {right arrow over (NP)}={right arrow over (MP)}−{right arrow over (MN)}. This overlay value may be useful for determining placement of the second pattern relative to the reference grid while also taking into account process deviations which affected placement of the first pattern. 
     Further, with coordinate locations of points (e.g. N) from the first pattern known and coordinate locations of points (e.g. P) from the second pattern known, an overlay value or shift from the first pattern to the second pattern can be determined. This overlay value can then be used to place the second or subsequent pattern to correct overlay relative to the independent reference grid. In some embodiments, having a reference image that is uniform for every image comparison enables correcting adjacent patterns as well as keeping overlay corrections based on an initial line or absolute reference. Note that in some embodiments, superimposing images is not necessary. Coordinate location data can be collected from the reference plate and the working surface of the wafer, and then vector analysis can be used to determine a gross offset or an overlay value. 
       FIGS.  5 A,  5 B and  5 C  show top-down views of a wafer stage  510  at intermediate steps of stitching, in accordance with embodiments of the present disclosure.  FIG.  5 D  shows an expanded view of the dotted rectangle  500 D in  FIG.  5 C , in accordance with embodiments of the present disclosure. While not shown, the wafer stage  510  can be part of a lithography tool, such as the EVU tool  100  in  FIG.  1 A . The lithography tool can also include a mask stage for holding a mask. 
     In  FIG.  5 A , at least one wafer  520  is loaded on the wafer stage  510 . The at least one wafer  520  has a backside facing the wafer stage  510  and a working surface to be patterned. In some embodiments, a resist layer is deposited on the working surface of the wafer  520 . The resist layer includes a photo-reactive species that is configured to form a composite pattern. 
     While not shown in  FIG.  5 A , a reference pattern is placed below the working surface of the wafer  520 . The reference pattern herein corresponds to the reference pattern in  FIGS.  3 A- 3 B and  4 A- 4 D . Descriptions have been provided above and will be omitted here for simplicity purposes. Note that a shape of the wafer stage  510 , a size of the wafer stage  510 , a shape of the wafer  520 , a size of the wafer  520 , a relative position of the wafer  520 , etc. are flexible and can be tailored to meet specific manufacturing requirements. 
       FIG.  5 B  shows the wafer stage  510  after the wafer  520  is exposed to a first pattern of actinic radiation. In some embodiments, the first pattern of actinic radiation is aligned with a first area (also known as a first die or a first field)  521  of the wafer  520  using the reference pattern. Then, the first area  521  is exposed to the first pattern of actinic radiation through a first mask (not shown) held on the mask stage. Consequently, a first latent image is printed in the resist layer in the first area  521 . 
     In some embodiments, a plurality of wafers  520  (e.g. twenty-five wafers) is loaded in a plurality of slots (e.g. twenty-five slots) on the wafer stage  510 . First areas  521  of the plurality of wafers  520  can be exposed to the first pattern of actinic radiation in a first pass. In a non-limiting example, in a “step-and-repeat” or “step-and-scan” system, the first mask is configured to print the first latent image in the resist layer on one wafer at a time. A reference pattern can be placed below the working surface of each wafer  520  and utilized to align the first mask before exposure. 
     In the examples of  FIGS.  5 A- 5 D , the first pattern of the first mask is a first component of a composite pattern. A second mask may include a second pattern which is a second component of the composite pattern. The first pattern and the second pattern are adjacent to each other. In a non-limiting example, the first pattern and the second pattern combined complete the composite pattern. Accordingly, the wafer  520  has a second area (also known as a second die or a second field)  522  adjacent to the first area  521 . The resist layer is configured to form the second pattern in the second area  522 . 
     In some embodiments, a plurality of wafers  520  may be removed from the wafer stage  510  and transferred to a wafer stocker of the lithography tool (not shown). When the plurality of wafers  520  is temporarily held in the wafer stocker, the mask stage can switch from the first mask to the second mask. Then, the plurality of wafers  520  is transferred back to the wafer stage  510 . In some embodiments, the wafer stocker may not be necessary. The plurality of wafers  520  can be on the wafer stage  510  when the mask stage switches from the first mask to the second mask. Further, in some embodiments, the wafer stage  510  may be moved to a different optical system for the second mask. In a non-limiting example, an EUV light is exposed through the first mask, and a DUV light is exposed through the second mask. 
       FIG.  5 C  shows the wafer stage  510  after the wafer  520  is exposed to a second pattern of actinic radiation through the second mask. In some embodiments, the second pattern of actinic radiation is aligned with the second area  522  of the wafer  520  using the reference pattern. Then, the second area  522  is exposed to the second pattern of actinic radiation through the second mask held on the mask stage. Consequently, a second latent image is printed in the resist layer in the second area  522 . Similar to the first pass, in some embodiments, second areas  522  of a plurality of wafers  520  can be exposed to the second pattern of actinic radiation in a second pass. 
     In some embodiments, a first overlay value is measured between the first pattern and the reference pattern to align the first pattern and update the first overlay value. Then, a second overlay value between the second pattern and the reference pattern is measured. Subsequently, a third overlay value between the first pattern and the second pattern is calculated based on the first overlay value and the second overlay value. Next, the second pattern is aligned with the first pattern using the third overlay value. 
     In some embodiments, an image of the reference pattern, an image of the first pattern and an image of the second pattern are captured. The image of the reference pattern and the image of the first pattern are superimposed on each other to form a first superimposed image to measure the first overlay value. The image of the reference pattern and the image of the second pattern are superimposed on each other to form a second superimposed image to measure the second overlay value. Alternatively, the image of the second pattern may be superimposed on the first superimposed image to measure the second overlay value. Note that in some embodiments, superimposing images may be not necessary. Coordinate location data can be collected from the reference plate and the working surface of the wafer, and then vector analysis can be used to determine a corresponding gross offset or an overlay value. 
     In some embodiments, first coordinate locations of the first pattern relative to the reference pattern are identified. Second coordinate locations of the second pattern relative to the reference pattern are also identified. An overlay value is then calculated using the first coordinate locations and the second coordinate locations. The second pattern is aligned with the first pattern using the overlay value. 
     Further, the first pattern of actinic radiation and the second pattern of actinic radiation can independently include an EUV wavelength (e.g. 13.5 nm) or a DUV wavelength (e.g. 193 nm). In one example, the first pattern of actinic radiation and the second pattern of actinic radiation both include an EUV wavelength. In another example, the first pattern of actinic radiation includes an EUV wavelength while the second pattern of actinic radiation includes a DUV wavelength. Accordingly, the wafer stage  510  may be moved to a different optical system for the second mask. 
       FIG.  5 D  shows an expanded view of the dotted rectangle  500 D in  FIG.  5 C . In one embodiment,  FIGS.  5 C and  5 D  show latent images of the first pattern and the second pattern. In another embodiment,  FIGS.  5 C and  5 D  show the first pattern and the second pattern after the resist layer is developed. 
     In a non-limiting example, the first pattern in the first area  521  includes first lines  541  (e.g.  541   a  and  541   b ). The second pattern in the second area  522  includes second lines  551  (e.g.  551   a  and  551   b ). A boundary line  530  is positioned between the first area  521  and the second area  522 . The boundary line  530  is also known as a field boundary. 
     In stitching, a first feature of the first pattern may need to connect with a second feature of the second pattern at the boundary line  530  to form a composite feature. In other words, when the composite pattern is split into two fields (or two patterns), an original feature across the field boundary may be split into two features. When the two fields are stitched together, the two features may need to connect with each other to form the original feature. However, alignment error or overlay error can lead to continuity issue. For example in  FIG.  5 D , the first line  541   a  and the second line  551   a  are not connected; the first line  541   b  and the second line  551   b  are not connected. 
     Further, in some embodiments, an intrafield alignment mark may be optionally formed outside a device area or below the resist layer in the device area. In a non-limiting example, the intrafield mark includes a plus sign  531  across the boundary line  530 . Both the first pattern and the second pattern can be aligned with the intrafield alignment mark using the reference pattern. Note that in some embodiments, the intrafield alignment mark is not needed, whether outside the device area or below the resist layer in the device area. 
     While in the examples of  FIGS.  5 A- 5 D , only two fields are involved in the stitching process, the wafer  520  may include more than two fields in other examples. As a result, more masks may be needed. Latent images can be printed separately, but developed together to form a corresponding composite pattern. 
       FIG.  6    shows a flow chart of a process  600  for processing a wafer, in accordance with exemplary embodiments of the present disclosure. The process  600  begins with Step S 610  where a reference pattern positioned below a working surface (e.g. a front side or a top surface) of a wafer is identified, for example via quantum tunneling imaging, IR transmission imaging or the like. 
     Because the reference pattern is positioned below the working surface of the wafer, the reference pattern can be independent of the working surface of the wafer. Herein, the reference pattern being independent of the working surface of the wafer means that the reference pattern is not affected by any manufacturing process performed on the working surface of the wafer. Such manufacturing processes typically include lithographic processes, such as etching, deposition, chemical mechanical polishing and the like. As a result, the reference pattern is also independent of one or more patterns formed on the working surface of the wafer. 
     The reference pattern includes at least one of a point, a line, a corner, a box, a triangle, a number, a mark or any other pattern that is suitable for alignment purposes. One embodiment includes using a grid plate under a wafer, though this is not a limitation. A grid plate may have grid lines and boxes formed by the grid lines. Intersection points of the grid lines or corners of the boxes can be used as reference points for overlay calculation as explicated in  FIG.  4 D . For example, a grid plate, manufactured by precision machining with 20 micron by 20 micron squares nearly perfectly aligned can be used. 
     In some embodiments, the reference pattern is incorporated in a reference plate positioned on a backside of the wafer. In one example, the reference plate is adhered to the backside of the wafer. Accordingly, the reference plate and the wafer can function as one module. In another example, the reference plate is incorporated in a substrate holder of a photolithography scanner or stepper. When a wafer having no pattern is placed over the reference plate, the wafer will be roughly aligned to the reference plate. When a wafer having an existing pattern is placed over the reference plate, the existing pattern and the reference plate can be co-axially aligned. In a conventional lithography process, measurement errors caused by wafer backside scratches, backside dust and/or substrate distortion due to heat, may impact overlay, but conventional overlay systems are often blind to these problems. Techniques herein include an independent reference plate and high spatial resolution to overcome these problems. 
     In some embodiments, the reference pattern is formed on a backside of the wafer. Other techniques can include embedding the reference pattern (e.g. grid lines) in a wafer such as using a radioactive or fluorescent material. In one example, a reference pattern is formed on a surface of a wafer, and then a layer of silicon and/or silicon oxide is deposited thereon. For instance, the layer of silicon and/or silicon oxide can have a thickness of 1-5 micrometers so that the reference pattern is effectively “embedded” in the wafer and patterns can be formed on the layer of silicon and/or silicon oxide. In another example, a reference pattern is formed on a backside of a wafer before a protection layer, such as silicon or silicon oxide is formed on the backside of the wafer. Consequently, the reference pattern is embedded in the wafer. In another example, the reference pattern may be formed on a front side of a carrier wafer before the front side of the carrier wafer is bonded to a backside of a target wafer. As a result, the reference pattern is sandwiched between the carrier wafer and the target wafer, which together function as one wafer. 
     The process  600  then proceeds to Step S 620  by exposing the wafer to a first pattern of actinic radiation. The first pattern is a first component of a composite pattern, and the first pattern of actinic radiation is aligned using the reference pattern. At Step S 630 , the wafer is exposed to a second pattern of actinic radiation. The second pattern is a second component of the composite pattern and exposed adjacent to the first pattern. The second pattern of actinic radiation is aligned with the first pattern of actinic radiation using the reference pattern. 
     In some embodiments, a first overlay value is measured between the first pattern and the reference pattern to align the first pattern and update the first overlay value. A second overlay value is measured between the second pattern and the reference pattern. A third overlay value is calculated between the first pattern and the second pattern based on the first overlay value and the second overlay value. The second pattern is aligned with the first pattern using the third overlay value. 
     In some embodiments, an image of the reference pattern and an image of the first pattern are captured. Image analysis is performed to measure the first overlay value to determine placement of the first pattern. For example, the image analysis can be accomplished by superimposing the image of the reference pattern and the image of the first pattern on each other, and identifying coordinate locations of the first pattern relative to the reference pattern. In some embodiments, superimposing images may be not necessary. Coordinate location data can be collected from the reference plate and the working surface of the wafer, and then vector analysis can be used to determine a gross offset or an overlay value. In some embodiments, the image analysis is performed in real time so that the placement of the first pattern can be adjusted in real time. In addition, the second overlay value can be measured similarly. 
     In some embodiments, first coordinate locations of the first pattern relative to the reference pattern are identified. Second coordinate locations of the second pattern relative to the reference pattern are also identified. An overlay value is then using the first coordinate locations and the second coordinate locations. The second pattern is thus aligned with the first pattern using the overlay value. 
     In some embodiments, a resist layer is formed on the working surface of the wafer. The resist layer includes a photo-reactive species that is configured to form the composite pattern. The resist layer may be inactive to the quantum tunneling imaging or the IR transmission imaging. In some embodiments, the resist layer is developed so that features of the first pattern connect with features of the second pattern. 
     In some embodiments, an intrafield alignment mark is optionally formed outside a device area or below the resist layer in the device area. The first pattern is aligned with the intrafield alignment mark using the reference pattern, and the second pattern is also aligned with the intrafield alignment mark using the reference pattern. 
     In some embodiments, the wafer is exposed to one or more additional patterns of actinic radiation. The one or more additional patterns are additional components of the composite pattern. The one or more additional patterns of actinic radiation are aligned using the reference pattern. 
     In some embodiments, the first pattern of actinic radiation includes an EUV wavelength (e.g. 13.5 nm) or a DUV wavelength (e.g. 193 nm). The second pattern of actinic radiation includes an EUV wavelength (e.g. 13.5 nm) or a DUV wavelength (e.g. 193 nm). As a result, the first pattern of actinic radiation and the second pattern of actinic radiation may include a same light or two different lights. 
     In some embodiments, a plurality of wafers is exposed to the first pattern of actinic radiation in a first pass when the plurality of wafers is placed on a wafer stage of a lithography tool. The wafers are subsequently transferred from the wafer stage to a wafer stocker of the lithography tool. Masks are switched for a mask stage of the lithography tool. The wafers are transferred from the wafer stocker back to the wafer stage. Then, the wafers are exposed to the second pattern of actinic radiation in a second pass. In some embodiments, the wafer stocker may not be necessary. The plurality of wafers can be on the wafer stage when the mask stage switches from the first mask to the second mask. Further, in some embodiments, the wafer stage may be moved to a different optical system for the second mask. In a non-limiting example, the first pattern of actinic radiation includes an EUV light, and the second pattern of actinic radiation includes a DUV light. 
     In some embodiments, the wafer is exposed to the first pattern of actinic radiation through a first mask having the first pattern to print a first latent image on the wafer. The first latent image is de-magnified compared to the first pattern on the first mask, for example in  FIGS.  1 B- 1 C . Similarly, the wafer is exposed to the second pattern of actinic radiation through a second mask having the second pattern to print a second latent image on the wafer. The second latent image is de-magnified compared to the second pattern on the second mask. 
     In a non-limiting example, a reference plate positioned below a wafer is imaged via quantum tunneling imaging, IR transmission imaging or the like. The reference plate includes a reference pattern. A first pattern of actinic radiation is aligned using the reference pattern. The first pattern is a first component of a composite pattern. A first field of the wafer is exposed to the first pattern of actinic radiation. A second pattern of actinic radiation is aligned using the reference pattern. The second pattern is a second component of the composite pattern. A second field of the wafer is exposed to the second pattern of actinic radiation, wherein the second field is adjacent to the first field. 
     In some embodiments, light projection can also be used. For example, the reference can be a projected grid that does not physically exist in the wafer, on substrate holder or as a grid plate under the substrate holder. In some embodiments, the reference pattern may be a combination of physical marks and light projection. For example, physical reference marks may be provided on a peripheral region of a substrate holder that is not covered by a wafer placed on the substrate holder, and light projections can complete the reference pattern in the area of the wafer such that tunneling may not be necessary. 
     For a reference plate positioned under the wafer, embedded marks within the wafer, or embedded marks on a backside surface of the wafer, quantum tunneling imaging, IR transmission imaging or the like is used to image the reference pattern which is then compared with patterns formed on the working surface of the wafer. 
     Accordingly, an independent reference pattern can be used for patterning. The reference pattern can be considered as absolute in one way, and relative in another. For example, the reference pattern may keep or maintain fixed grid lines (or points or corners or boxes or any other suitable shapes) and is not changed from various deposition and etch steps on the wafer. In one embodiment, this can be a grid plate integrated with a stage or wafer holder. In this way the grid plate is absolute because the same physical grid plate is used throughout processing of the wafer, but relative because the physical grid plate is not fixed to the wafer itself and may be moved relative to the wafer throughout wafer processing. Although each time a given wafer is placed on the stage, it may be in a different location or orientation as compared to a previous placement; this does not matter. For a given new pattern to be placed or exposed, the wafer is imaged with the reference grid. The reference grid can then provide a relative reference point for identifying vectors to two or more points, from which vector analysis can be used to calculate an overlay correction adjustment in a next exposure. That is, the process of  FIGS.  4 C- 4 D  can be used to mathematically correct for a change in relative position of the wafer and grid plate such that the grid plate can function in the same way as a fixed reference that is embedded in the wafer for example. 
     IR and UV sensors and sources are conventionally available and can be adapted for use with embodiments herein. In a non-limiting example, FLIR X8500 MWIR (Teledyne FLIR LLC, Oregon, USA) is a high-speed, high definition MWIR camera that can be used herein. For sensors, DataRay (DataRay Inc., California, USA) camera sensors can be used. An Optowaves (Optowares Inc., Massachusetts, USA) solid state lasers can be used, such as pumped nanosecond laser for surface imaging. For an IR source, IR tunable quantum cascade lasers from Pranalytica, Inc. (California, USA) can be used. These are example components. Others available systems can be substituted. 
     Techniques can include periodic calibration of relative positions of IR and UV, which is also referred to as relative position of red and blue calibration. It is beneficial to keep the relative position of IR and UV within a sensor dynamic range which is a few decades and as such quite forgiving. Normalization, however, can be done with a stage artifact of known relative transmission being imaged as needed. For example, once a day so that any relative intensity normalization can be conducted easily. Relative position or TIS tool induced shift calibrations are common to metrology stations. Relative position is re-calibrated against the grid plate in real time as measurements are made. A significant advantage of this system is always having a real time absolute reference. Digital image capture and regression can be used. 
     With deep ultra-violet (DUV) light, photoresist damage is negligible. For example, a 250 um field of view herein corresponds with about a 60 nm per pixel in the case of 4K resolution, which is sufficient for resolution of 0.1 nm registration error measurement. Having sufficient intensity of light source can mitigate any shadowing of metal layers. 
     Regarding possible concerns about CD variation effects for resist layers, techniques herein can extract coordinates of the patterns without pattern CD variation effects for a resist layer and an under-layer thereof (Metal resist patterns cover most of via patterns). Note that CD variation effects for resist layers are always an issue for alignment and is always ignored by overlay measurement teams as negligible in related examples. Techniques herein are far improved as the pattern itself is a far better indication of pattern placement than an alignment mark that suffers from CD&#39;s astigmatism and Zernike induced offset from pattern. 
     Techniques here include an inspection system and method. Techniques herein can see through a wafer as designed. A wafer scanning and imaging system is used that includes imaging through a wafer to a pattern below the wafer or a pattern within the wafer. This includes using light at a wavelength and intensity sufficient to quantum tunnel through or transmit through the wafer. Techniques herein can provide less than nanometer registration using both quantum cascade laser and visible light inspection. Inspection techniques herein can image and analyze overlay and defect without using conventional overlay and alignment marks. As scaling continues, on-wafer alignment marks are becoming too area hungry and they have inherent different optical distortion sensitivity from the main pattern making them unstable. 
     Techniques herein will wipe out the need for conventional overlay marks. The upper box is now the pattern and the lower box is just under the wafer. Techniques herein provide a totally different paradigm of overlay which requires no clear outs, no loss in real-estate, no complex scribe line design making silicon area utilization improved and not complex integrations for alignment marks. The best part is that your reference mark is not being impacted and wiped out by unfavorable processes that are making devices instead of the alignment marks, as they often are conventionally. Overlay placement accuracy can also now be measured from the very first layer, as your first reference layer is now not only near perfect every time but hidden right under the stage there always. 
     By way of a non-limiting embodiment, a highly accurate and precise grid plate can be used. One example can be a grid plate with 20 micron by 20 micron squares, nearly perfectly aligned. Techniques then resolve 20 um grid fiducials with QCL optical system using a few um wavelength. The infrared resolution capability is sufficient for this because resolution is a function of wavelength. 2-3 um features with a “k” resolution factor of 1.0 which is considered very easy and thus is able to image grid marks on the order of 2-3 um. With the example grid marks being ten times larger at 20 um, they are accurately resolved. 
     Techniques herein provide high positional accuracy of the reference plate. For example, the grid plate with 20 micron by 20 micron squares can be placed with sub-nm positional accuracy or uncertainty. It is not the size of the mark that makes the grid special, but instead it is the knowledge of accuracy or uncertainty of the reference mark placement to sub nm that is important. That is, while the squares of the reference pattern are on the order of 20 microns and the feature size of a pattern to be formed on the wafer may be on the order of a few nanometers, a reference point of a square (e.g. the point M in  FIG.  4 C ) rather than an entire square (e.g. the box  430  in  FIG.  4 C ) can be used for overlay calculation. Because the overlay value between the point N and the point P is calculated by using the point M as a reference point, the positional uncertainty of the point M is integrated into the calculated overlay value. When the calculated overlay value is on the order of a few nanometers or more, a sub-nm positional uncertainty of the point M is negligible. Hence, it is important and advantageous to ensure the positional accuracy of the reference pattern. A sub-nm positional accuracy is highly desirable but may also be unnecessary, depending on specific patterns to be formed in various applications. 
     Techniques herein provide real-time imaging, overlay calculation and pattern alignment. A position of the wafer can be actively determined using the reference pattern. Positions of any previously formed patterns on the working surface of the wafer can also be actively determined using the reference pattern. Calculations can then be used to adjust a position of a pending exposure. In related examples, when moving from one area of the wafer to another area of the wafer (e.g. stepping), one needs to search for alignment marks and stop moving when finding the alignment marks. Images are usually acquired so as to adjust focus, and the stage may be settled. This series of operations can be time-consuming, particularly for a “step-and-repeat” or “step-and-scan” system in projection printing. Nevertheless, in the present disclosure, images are taken and analyzed in real time to constantly determine where the relative location is. As a matter of fact, every image taken is a snapshot of overlay. One needs only to track positional data from the reference pattern and re-create the high spatial terms of the overlay map digitally from the image analysis. Therefore, there is no “step”, “search”, “acquire”, “stop”, “settle” or “focus” in contrast to related examples. Techniques herein enable high-speed measurement. 
     In some embodiments a color filter can be used to only detect fluorescence of the resist resin to enhance the pattern from the resist. 
     In the preceding description, specific details have been set forth, such as a particular geometry of a processing system and descriptions of various components and processes used therein. It should be understood, however, that techniques herein may be practiced in other embodiments that depart from these specific details, and that such details are for purposes of explanation and not limitation. Embodiments disclosed herein have been described with reference to the accompanying drawings. Similarly, for purposes of explanation, specific numbers, materials, and configurations have been set forth in order to provide a thorough understanding. Nevertheless, embodiments may be practiced without such specific details. Components having substantially the same functional constructions are denoted by like reference characters, and thus any redundant descriptions may be omitted. 
     Various techniques have been described as multiple discrete operations to assist in understanding the various embodiments. The order of description should not be construed as to imply that these operations are necessarily order dependent. Indeed, these operations need not be performed in the order of presentation. Operations described may be performed in a different order than the described embodiment. Various additional operations may be performed and/or described operations may be omitted in additional embodiments. 
     “Substrate” or “wafer” as used herein generically refers to an object being processed in accordance with the invention. The substrate may include any material portion or structure of a device, particularly a semiconductor or other electronics device, and may, for example, be a base substrate structure, such as a semiconductor wafer, reticle, or a layer on or overlying a base substrate structure such as a thin film. Thus, substrate is not limited to any particular base structure, underlying layer or overlying layer, patterned or un-patterned, but rather, is contemplated to include any such layer or base structure, and any combination of layers and/or base structures. The description may reference particular types of substrates, but this is for illustrative purposes only. 
     Those skilled in the art will also understand that there can be many variations made to the operations of the techniques explained above while still achieving the same objectives of the invention. Such variations are intended to be covered by the scope of this disclosure. As such, the foregoing descriptions of embodiments of the invention are not intended to be limiting. Rather, any limitations to embodiments of the invention are presented in the following claims.