Patent Publication Number: US-9842539-B2

Title: Pixel control circuit

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates to a pixel control circuit, and especially relates to a pixel control circuit that is able to avoid a brightness of the pixel from being affected by characteristics of transistors. 
     2. Description of the Prior Art 
       FIG. 1  shows a pixel control circuit  100  according to prior art. The pixel control circuit  100  includes a switch T 1 A, a driving transistor T 1 B, a capacitor C 1 , and an organic light emitting diode  110 . The switch T 1 A has a first terminal for receiving a data signal S data , a second terminal, and a control terminal for receiving a scan signal S scan . The driving transistor T 1 B has a first terminal for receiving a system voltage OVDD, a second terminal coupled to a first terminal of the organic light emitting diode  110 , and a control terminal coupled to the second terminal of the switch T 1 A. The capacitor C 1  has a first terminal for receiving the system voltage OVDD, and a second terminal coupled to the control terminal of the driving transistor T 1 B. 
     When the switch T 1 A is turned on by the scan signal S scan , the driving transistor T 1 B can conduct a current I OLED  according a voltage of the data signal S data  to turn on the organic light emitting diode  110 . The current I OLED  can be represented as I OLED =K(V SG −|V TH |) 2  according to characteristics of the transistors, where K represents a manufacturing parameter of the driving transistor T 1 B, V SG  represents a source-to-gate voltage of the driving transistor T 1 B, and V TH  represents the threshold voltage of the driving transistor T 1 B. In  FIG. 1 , the driving transistor T 1 B is a P-type metal-oxide-semiconductor transistor, and the source-to-gate voltage V SG  is the system voltage OVDD minus the voltage of the data signal S data . 
     Consequently, although the pixel control circuit  100  may control the strength of the current I OLED  flowing through the organic light emitting diode  110  according to the voltage of the data signal S data , each of the pixels in a display may still have different brightness even if each of the pixels shows a brightness according to the same data signal S data , due to different characteristics of transistors in each of the pixels, which may cause luminance nonuniformity. This is because the threshold voltage V TH  of the driving transistor T 1 B may be affected by the manufacturing process or may be changed after being used for a long time. Thus, the image quality may also drop as the time goes by. 
     Furthermore, since the pixels are disposed in different positions of the display, the system voltage OVDD received by each of the pixels may also be different due to different levels of resistance of the OVDD transmission line, which makes it even more difficult to control the luminance uniformity. 
     In addition, since the pixel control circuit  100  does not provide the organic light emitting diode  110  with any discharge path, there may be some charges remaining in the organic light emitting diode  110  after a previous image is over. Therefore, if the following image is a black image, the display may have the issue of not being dark enough while displaying the black image. 
     SUMMARY OF THE INVENTION 
     One embodiment of the present disclosure discloses a pixel control circuit. The pixel control circuit comprises an organic light emitting diode, a first switch, a driving transistor, a driving circuit, a compensation circuit and a discharge circuit. The organic light emitting diode has a first terminal, and a second terminal configured to receive a first default voltage. The first switch has a first terminal configured to receive a data signal, a second terminal, and a control terminal configured to receive a first control signal. The driving transistor has a first terminal coupled to the second terminal of the first switch, a second terminal coupled to the first terminal of the organic light emitting diode, and a control terminal. The driving circuit is coupled to the first terminal of the driving transistor, and configured to receive a second default voltage and control an electrical connection between the second default voltage and the driving transistor according to an emission control signal. The compensation circuit is coupled to the driving circuit and the control terminal of the driving transistor, and configured to receive a reference voltage and control an electrical connection between the control terminal of the driving transistor and the second terminal of the driving transistor according to a second control signal. The discharge circuit is coupled to the first terminal of the organic light emitting diode and an initial voltage, and configured to control the electrical connection between the first terminal of the organic light emitting diode and the initial voltage according to a third control signal. 
     These and other objectives of the present disclosure will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  shows a pixel control circuit according to prior art. 
         FIG. 2  shows a pixel control circuit according to one embodiment of the present disclosure. 
         FIG. 3  shows a timing diagram of the pixel control circuit in  FIG. 2 . 
         FIG. 4  shows a pixel control circuit according to another embodiment of the present disclosure. 
         FIG. 5  shows a pixel control circuit according to another embodiment of the present disclosure. 
         FIG. 6  shows a pixel control circuit according to another embodiment of the present disclosure. 
         FIG. 7  shows a pixel array control circuit according to one embodiment of the present disclosure. 
         FIG. 8  shows a pixel control circuit according to another embodiment of the present disclosure. 
         FIG. 9  shows a pixel array control circuit according to another embodiment of the present disclosure. 
         FIG. 10  shows a curve diagram of the data signal to current error according to the pixel control circuit in  FIG. 1 . 
         FIG. 11  shows a curve diagram of the data signal to current error according to the pixel control circuit in  FIG. 7 . 
     
    
    
     DETAILED DESCRIPTION 
       FIG. 2  shows a pixel control circuit  200  according to one embodiment of the present disclosure. The pixel control circuit includes an organic light emitting diode  210 , a switch T 2 A, a driving transistor T 2 B, a driving circuit  220 , a compensation circuit  230 , and a discharge circuit  240 . The organic light emitting diode  210  has a first terminal, and a second terminal for receiving a default voltage OVSS. 
     The switch T 2 A has a first terminal for receiving a data signal S data , a second terminal, and a control terminal for receiving a first control signal SN 1 . The driving transistor T 2 B has a first terminal S coupled to the second terminal of the switch T 2 A, a second terminal D coupled to the first terminal of the organic light emitting diode  210 , and a control terminal G. 
     The driving circuit  220  is coupled to the first terminal S of the driving transistor T 2 B, and for receiving a default voltage OVDD and control an electrical connection between the default voltage OVDD and the driving transistor T 2 B according to an emission control signal EM. The compensation circuit  230  is coupled to the driving circuit  220  and the control terminal G of the driving transistor T 2 B, and for receiving a reference voltage Vref and control an electrical connection between the control terminal G of the driving transistor T 2 B and the second terminal D of the driving transistor T 2 B according to a second control signal SN 2 . The discharge circuit  240  is coupled to the first terminal of the organic light emitting diode  210  and an initial voltage Vini, and configured to control the electrical connection between the first terminal of the organic light emitting diode  210  and the initial voltage Vini according to a third control signal SN 3 . 
     In some embodiments of the present disclosure, the driving circuit  220  includes a switch T 2 C and a switch T 2 D. The switch T 2 C has a first terminal for receiving the default voltage OVDD, a second terminal coupled to the first terminal S of the driving transistor T 2 B, and a control terminal for receiving the emission control signal EM. The switch T 2 D has a first terminal for receiving the default voltage OVDD, a second terminal coupled to the compensation circuit  230 , and a control terminal for receiving the emission control signal EM. 
     In some embodiments of the present disclosure, the compensation circuit comprises a capacitor C 2 , a switch T 2 E, and a switch T 2 F. The capacitor C 2  has a first terminal coupled to the second terminal of the switch T 2 D, and a second terminal coupled to the control terminal G of the driving transistor T 2 B. The switch T 2 E has a first terminal for receiving the reference voltage Vref, a second terminal coupled to the first terminal of the capacitor C 2  and the second terminal of the switch T 2 D, and a control terminal for receiving the second control signal SN 2 . The switch T 2 F has a first terminal coupled to the second terminal of the capacitor C 2 , a second terminal coupled to the second terminal D of the driving transistor T 2 B, and a control terminal for receiving the second control signal SN 2 . 
     The discharge circuit comprises a switch T 2 G. The switch T 2 G has a first terminal for receiving the initial voltage Vini, a second terminal coupled to the second terminal D of the driving transistor T 2 B, and a control terminal for receiving the third control signal SN 3 . 
     In some embodiments of the present disclosure, the switches T 2 A and T 2 C to T 2 G and the driving transistor T 2 B can be P type transistors, the default voltage OVSS is smaller than the default voltage OVDD, and the second terminal of the organic light emitting diode  210  is a cathode of the organic light emitting diode  210 . However, the present disclosure is not limited to use P type transistors; in other embodiments of the present disclosure, switches T 2 A and T 2 C to T 2 G and the driving transistor T 2 B can also be N type transistors. 
       FIG. 8  shows a pixel control circuit  800  according to one embodiment of the present disclosure. The structure of the pixel control circuit  800  is similar to the structure of the pixel control circuit  200 . The switches T 8 A and T 8 C to T 8 G can be corresponding to the switches T 2 A and T 2 C to T 2 G respectively, the driving transistor T 8 B can be corresponding to the driving transistor T 2 B, and the capacitor C 8  can be corresponding to the capacitor C 2 . The difference between these two pixel control circuits is that the switches T 8 A and T 8 C to T 8 G and the driving transistor T 8 B are N type transistors, the first terminal of the switch T 8 C receives the default voltage OVSS, the first terminal of the switch T 8 D receives the default voltage OVSS, and the second terminal of the organic light emitting diode  810  receives the default voltage OVDD, namely, in the embodiment in  FIG. 8 , the second terminal of the organic light emitting diode  810  is the anode of the organic light emitting diode  810 . The pixel control circuit  800  may have the same operational timing as the pixel control circuit  200 . However, the control signals for the pixel control circuit  800  are complementary to the control signals for the pixel control circuit  200 . 
       FIG. 3  shows a timing diagram of the pixel control circuit  200 . For the purpose of convenience, the timing diagram in  FIG. 3  shows the timing with the switches T 2 A and T 2 C to T 2 G and the driving transistor T 2 B to be P type transistors exemplarily. 
     Since the first control signal SN 1 , the emission control signal EM, the second control signal SN 2 , and the third control signal SN 3  that control the switches T 2 A, T 2 C, T 2 D, T 2 E, T 2 F, and T 2 G are all digital signals, these signals are able to fully turn on and fully turn off the switches T 2 A, T 2 C, T 2 D, T 2 E, T 2 F, and T 2 G, and, thus, variation of the threshold voltages of the switches T 2 A, T 2 C, T 2 D, T 2 E, T 2 F, and T 2 G may have smaller influences on the amount of current. Contrarily, since the driving transistor T 2 B is controlled by the data signal S data , which is an analog signal, for conducting different amounts of current according to the voltage level of the data signal S data . Therefore, in some embodiments of the present disclosure, the adjustment for the influences caused by the threshold voltage of the driving transistor T 2 B is considered firstly. 
     During the first duration t 1 , the emission control signal EM is at a high voltage VGH, the first control signal SN 1  is at the high voltage VGH, the second control signal SN 2  is at a low voltage VGL, and the third control signal SN 3  is at the low voltage VGL. In this duration, the switches T 2 A, T 2 C and T 2 D are turned off. The switch T 2 G is turned on so a voltage V D  of the second terminal D of the driving transistor T 2 B, that is, a voltage of the first terminal of the organic light emitting diode  210 , is pulled down to the initial voltage Vini. In some embodiments of the present disclosure, the initial voltage Vini is smaller than a sum of the default voltage OVSS and a threshold voltage V TH-210  of the organic light emitting diode  210 . Consequently, the switch T 2 G of the discharge circuit  240  is able to conduct a path connecting to the initial voltage Vini according to the third control signal SN 3  for providing the organic light emitting diode  210  with a discharge path to discharge the remaining charges stored in the previous operation, and to turn off the organic light emitting diode  210  effectively. The remaining charges stored at the first terminal S of the driving transistor T 2 B stored in the previous operation can also be discharged through the path provided by the switch T 2 G so that the voltage V S  of the first terminal S of the driving transistor T 2 B can also be pulled down to a low voltage V low  lower than the previous voltage. The switches T 2 E and T 2 F are both turned on so a voltage of the first terminal of the capacitor C 2  is at the reference voltage Vref, and a voltage of second terminal of the capacitor C 2 , that is, the voltage V G  of the control terminal G of the driving transistor T 2 B, can be controlled at the initial voltage Vini by the switches T 2 F and T 2 G. 
     During a second duration t 2  after the first duration t 1 , the emission control signal EM is at the high voltage VGH, the first control signal SN 1  is at the low voltage VGL, the second control signal SN 2  is at the low voltage VGL, and the third control signal SN 3  is at the high voltage VGH. In this duration, the switches T 2 C, T 2 D, and T 2 G are turned off. The switch T 2 A is turned on so the voltage V S  of the first terminal of the driving transistor T 2 B is at the voltage V data  of the data signal S data . The switch T 2 E is turned on so that the voltage of the first terminal of the capacitor C 2  remains at the reference voltage Vref, and the voltage of the second terminal of the capacitor C 2 , that is, the voltage V G  of the control terminal G of the driving transistor T 2 B, is at a lower voltage firstly. In some embodiments of the present disclosure, the initial voltage Vini in the first duration t 1  is not greater than a difference between a minimum voltage V datamin  of the data signal S data  (ex., the voltage of the data signal S data  when the image data is white) and an absolute value of the threshold voltage V TH-T2B  of the driving transistor T 2 B, that is, V datamin −|V TH-T2B |. Therefore, the driving transistor T 2 B is turned on, making the voltage V D  of the second terminal D of the driving transistor T 2 B at the voltage V data  of the data signal S data  minus the absolute value of the threshold voltage V TH-T2B  of the driving transistor T 2 B, that is, V data −|V TH-T2B |. Since the switch T 2 F is turned on, the voltage V G  of the control terminal G of the driving transistor T 2 B is kept at the same voltage as the voltage of the second terminal D of the driving transistor T 2 B, that is, V data −|V TH-T2B |. 
     During a third duration t 3  after the second duration t 2 , the emission control signal EM is at the low voltage VGL, the first control signal SN 1  is at the high voltage VGH, the second control signal SN 2  is at the high voltage VGH, and the third control signal SN 3  is at the high voltage VGH. In this duration, the switches T 2 A, T 2 E, T 2 F, and T 2 G are all turned off. Since the switch T 2 D is turned on, the voltage of the first terminal of the capacitor C 2  is changed from the reference voltage Vref to the default voltage OVDD. Since there is no discharging path around the capacitor C 2 , the voltage of the second terminal of the capacitor C 2 , that is the voltage V G  of the control terminal G of the driving transistor T 2 B, is coupled as shown in equation (1):
 
 V   G =( V   data   −|V   TH-T2B |)+( OVDD−V ref)  (1)
 
     Since the switch T 2 C is turned on, the voltage V S  of the first terminal S of the driving transistor T 2 B is pulled up to the default voltage OVDD. Since the turned-on switch T 2 C and the driving transistor T 2 B can turn on the organic light emitting diode  210 , the voltage V D  of the second terminal D of the driving transistor T 2 B is substantially equal to a sum of the default voltage OVSS and the threshold voltage V TH-210  of the organic light emitting diode  210 . In this case, the source to gate voltage V SG  of the driving transistor T 2 B is represented as equation (2):
 
 V   SG   =V   S   −V   G   =OVDD −[( V   data   −|V   TH-T2B |)+( OVDD−V ref)]= V ref−( V   data   −V   TH-T2B )   (2)
 
     If equation (2) is substituted in the transistor current equation, then the current I T2B  flowing through the driving transistor T 2 B can be represented as equation (3):
 
 I   T2B   =K ( V   SG   −|V   TH-T2B |) 2   =K[V ref−( V   data   −|V   TH-T2B |)−| V   TH-T2B |] 2   =K ( V ref− V   data )   (3)
 
     K represents the manufacturing parameter of the driving transistor T 2 B. Since the reference voltage Vref is a default fixed value, the current I T2B  flowing through the driving transistor T 2 B can be independent from the threshold voltage V TH-T2B  of the driving transistor T 2 B and the default voltage OVDD. In some embodiments of the present disclosure, to turn off the transistor T 2 B effectively when the data signal S data  has a maximum voltage V datamax  (ex., the voltage of the data signal S data  when the image data is black), the reference voltage Vref should be able to satisfy equation (4):
 
 V   gate-T2B ≦( V   datamax   −|V   TH-T2B |)+( OVDD−V ref)  (4)
 
     V gate-T2B  represents a turn off voltage of the driving transistor T 2 B, that is, when the gate voltage V G  of the driving transistor T 2 B is greater than the turn off voltage V gate-T2B  of the driving transistor T 2 B, the driving transistor T 2 B will be turned off. According to equation (4), equation (5) can be derived as:
 
 V ref≦( V   datamax   −|V   TH-T2B |)+( OVDD−V   gate-T2B )  (5)
 
     According to equation (5), the reference voltage Vref is not greater than a sum of a difference between the maximum voltage V datamax  of the data signal S data  and the absolute value of the threshold voltage |V TH-T2B | of the driving transistor T 2 B and a difference between the default voltage OVDD and the turn off voltage V gate-T2B  of the driving transistor T 2 B. Consequently, when using the pixel control circuit  200  to control pixels in a display, the nonuniformity of brightness of the image caused by different characteristics of transistors in each of the pixels and different default voltages OVDD received by each of the pixels can be avoided, and the image quality of the display can be improved. In addition, since the discharge circuit  240  can provide a discharging path in the second duration t 2 , the issue of the black image being not dark enough, which caused by the remaining charges in the pixels, can also be solved. 
     In some embodiments of the present disclosure, during a fourth duration t 4  before the first duration t 1 , the emission control signal EM is at the high voltage VGH, the first control signal SN 1  is at the high voltage VGH, the second control signal SN 2  is at the low voltage VGL, and the third control signal SN 3  is at the high voltage VGH. When the third control signal SN 3  changes from the high voltage VGH to the low voltage VGL, it will enter into the first duration t 1  from the fourth duration t 4 . 
     In some embodiments of the present disclosure, during a fifth duration t 5  between the first duration t 1  and the second duration t 2 , the emission control signal EM is at the high voltage VGH, the first control signal SN 1  is at the high voltage VGH, the second control signal SN 2  is at the low voltage VGL, and the third control signal SN 3  is at the high voltage VGH. When the first control signal SN 1  changes from the high voltage VGH to the low voltage VGL, it will enter into the second duration t 2  from the fifth duration t 5 . 
     In some embodiments of the present disclosure, during a sixth duration t 6  between the second duration t 2  and the third duration t 3 , the emission control signal EM is at the high voltage VGH, the first control signal SN 1  is at the high voltage VGH, the second control signal SN 2  is at the low voltage VGL, and the third control signal SN 3  is at the high voltage VGH. When the emission control signal EM changes from the high voltage VGH to the low voltage VGL, it will enter into the third duration t 3  from the sixth duration t 6 . 
       FIG. 4  shows a pixel control circuit  400  according to one embodiment of the present disclosure. The pixel control circuit  400  and the pixel control circuit  200  have similar structures and operation principles. The difference between these two pixel control circuits is that the driving circuit  420  of the pixel control circuit  400  includes the switches T 4 C and T 4 D. The switch T 4 C has a first terminal for receiving the default voltage OVDD, a second terminal coupled to the first terminal S of the driving transistor T 2 B, and a control terminal for receiving the emission control signal EM. The switch T 4 D has a first terminal coupled to the second terminal of the switch T 4 C, a second terminal coupled to first terminal of the capacitor C 2  of the compensation circuit  230 , and a control terminal for receiving the emission control signal EM. 
     Since the operation principles of the pixel control circuits  400  and  200  are similar, the timing diagram of the pixel control circuit  400  is same as  FIG. 3 . Since the switches T 4 C and T 4 D are turned off during the first duration t 1  and the second duration t 2 , the pixel control circuit  400  has the same operations as the aforesaid operations. As in the third duration t 3 , the switches T 4 C and T 4 D are both turned on so the voltage of the second terminal of the switch T 4 D is pulled up to the default voltage OVDD and the voltage of the first terminal of the capacitor C 2  changes from the reference voltage Vref to the default voltage OVDD. Therefore, the voltage V G  of the control terminal G of the driving transistor T 2 B in the pixel control circuit  400  can still be represented as (V data −V TH-T2B )+(OVDD−Vref) as shown in  FIG. 3 , and the voltage V S  of the first terminal S of the driving transistor T 2 B is at the default voltage OVDD so that the current I T2B  flowing through the driving transistor T 2 B is still independent from the threshold voltage V TH-T2B  of the driving transistor T 2 B and the default voltage OVDD. 
     Consequently, when using the pixel control circuit  400  to control pixels in a display, the nonuniformity of brightness of the image caused by different characteristics of transistors in each of the pixels and different default voltages OVDD received by each of the pixels can be avoided, and the image quality of the display can be improved. 
       FIG. 5  shows a pixel control circuit  500  according to one embodiment of the present disclosure. The pixel control circuit  500  and the pixel control circuit  200  have similar structures and operation principles. The difference between these two pixel control circuits is in the compensation circuit  530  and the discharge circuit  540  of the pixel control circuit  500 . The compensation circuit  530  includes a capacitor C 5 , a switch T 5 E, a switch T 5 F, and a switch T 5 G. The capacitor C 5  has a first terminal coupled to the second terminal of the switch T 2 D, and a second terminal coupled to the control terminal G of the driving transistor T 2 B. The switch T 5 E has a first terminal for receiving the reference voltage Vref, a second terminal coupled to the first terminal of the capacitor C 5 , and a control terminal for receiving the second control signal SN 2 . The switch T 5 F has a first terminal coupled to the second terminal of the capacitor C 5 , a second terminal, and a control terminal for receiving the second control signal SN 2 . The switch T 5 G has a first terminal coupled to the second terminal of the switch T 5 F, a second terminal coupled to the second terminal D of the driving transistor T 2 B, and a control terminal for receiving the second control signal SN 2 . 
     The discharge circuit  540  includes a switch T 5 H. The switch T 5 H has a first terminal for receiving the initial voltage Vini, a second terminal coupled to the first terminal of the switch T 5 G, and a control terminal for receiving the third control signal SN 3 . 
     Since the operation principles of the pixel control circuits  500  and  200  are similar, the timing diagram of the pixel control circuit  500  is same as  FIG. 3 . 
     During the first duration t 1  in  FIG. 3 , the switches T 2 A, T 2 C and T 2 D are turned off. The switches T 5 G and T 5 H are turned on so the voltage V D  of the second terminal D of the driving transistor T 2 B is pulled down to the initial voltage Vini. Consequently, the switch T 5 H of the discharge circuit  540  is able to conduct a path connecting to the initial voltage Vini according to the third control signal SN 3  for providing the organic light emitting diode  210  with a discharge path to discharge the remaining charges stored in the previous operation, and to turn off the organic light emitting diode  210  effectively. The remaining charges stored at the first terminal S of the driving transistor T 2 B stored in the previous operation can also be discharged through the path provided by the switches T 5 G and T 5 H so that the voltage V S  of the first terminal S of the driving transistor T 2 B can also be pulled down to the low voltage V low  lower than the previous voltage. The switches T 5 E and T 5 F are both turned on so a voltage of the first terminal of the capacitor C 5  is at the reference voltage Vref, and a voltage of second terminal of the capacitor C 5 , that is, the voltage V G  of the control terminal G of the driving transistor T 2 B, can be controlled at the initial voltage Vini by the switches T 5 F and T 5 H. 
     During a second duration t 2 , the switches T 2 C, T 2 D, and T 5 H are turned off. The switch T 2 A is turned on so the voltage V S  of the first terminal of the driving transistor T 2 B is at the voltage V data  of the data signal S data . The switch T 5 E is turned on so that the voltage of the first terminal of the capacitor C 5  remains at the reference voltage Vref, and the voltage of the second terminal of the capacitor C 5 , that is, the voltage V G  of the control terminal G of the driving transistor T 2 B, is at a lower voltage firstly so the driving transistor T 2 B is turned on and the voltage V D  of the second terminal D of the driving transistor T 2 B is at the voltage V data  of the data signal S data  minus the absolute value of the threshold voltage V TH-T2B  of the driving transistor T 2 B, that is, V data −|V TH-T2B |. Since the switches T 5 F and T 5 G are turned on, the voltage V G  of the control terminal of the driving transistor T 2 B remains at the same voltage as the voltage V D  of the second terminal D of the driving transistor T 2 B, that is, V data −|V TH-T2B |. 
     During a third duration t 3  the switches T 2 A, T 5 E, T 5 F, T 5 G, and T 5 H are all turned off. Since the driving transistor T 2 B and the switches T 2 C and T 2 D are all turned on, the voltage of the first terminal of the capacitor C 5  is changed from the reference voltage Vref to the default voltage OVDD. Consequently, the voltage V G  of the control terminal G of the driving transistor T 2 B in pixel control circuit  500  is at (V data −V TH-T2B )+(OVDD−Vref) as shown in  FIG. 3 , and the voltage V S  of the first terminal S of the driving transistor T 2 B is at the default voltage OVDD so that the current I T2B  flowing through the driving transistor T 2 B is still independent from the threshold voltage V TH-T2B  of the driving transistor T 2 B and the default voltage OVDD. 
     Consequently, when using the pixel control circuit  500  to control pixels in a display, the nonuniformity of brightness of the image caused by different characteristics of transistors in each of the pixels and different default voltages OVDD received by each of the pixels can be avoided, and the image quality of the display can be improved. 
     In some embodiments of the present disclosure, the driving circuit  220  of the pixel control circuit  500  can also be replaced by the driving circuit  420  of the pixel control circuit  400  and can still achieve the same effect. 
       FIG. 6  shows a pixel control circuit  600  according to one embodiment of the present disclosure. The pixel control circuit  600  and the pixel control circuit  200  have similar structures and operation principles. The difference between these two pixel control circuits is in the compensation circuit  630  and the discharge circuit  640  of the pixel control circuit  600 . Since the operation principles of the pixel control circuits  600  and  200  are similar, the timing diagram of the pixel control circuit  600  is same as  FIG. 3 . 
     The compensation circuit  630  includes a capacitor C 6 , and switches T 6 E and T 6 F. The capacitor C 6  has a first terminal coupled to the second terminal of the switch T 2 D, and a second terminal coupled to the control terminal G of the driving transistor T 2 B. The switch T 6 E has a first terminal for receiving the initial voltage Vini during the first duration t 1  in  FIG. 3  and receiving the reference voltage Vref during the second duration t 2  and the third duration t 3 , a second terminal coupled to the first terminal of the capacitor C 6 , and a control terminal for receiving the second control signal SN 2 . The switch T 6 F has a first terminal coupled to the second terminal of the capacitor C 6 , a second terminal coupled to the second terminal D of the driving transistor T 2 B, and a control terminal for receiving the second control signal SN 2 . 
     The discharge circuit  640  includes a switch T 6 G. The switch T 6 G has a first terminal coupled to the second terminal of the switch T 6 E, a second terminal coupled to the first terminal of the switch T 6 F, and a control terminal for receiving the third control signal SN 3 . 
     During the first duration t 1  in  FIG. 3 , the switches T 2 A, T 2 C and T 2 D of the pixel control circuit  600  are turned off. The switches T 6 E, T 6 F and T 6 G are turned on and the first terminal of the switch T 6 E receives the initial voltage Vini so the voltage V D  of the second terminal D of the driving transistor T 2 B is pulled down to the initial voltage Vini. Consequently, the switch T 6 G of the discharge circuit  640  is able to conduct a path connecting to the initial voltage Vini according to the third control signal SN 3  for providing the organic light emitting diode  210  with a discharge path to discharge the remaining charges stored in the previous operation, and to turn off the organic light emitting diode  210  effectively. The remaining charges stored at the first terminal S of the driving transistor T 2 B stored in the previous operation can also be discharged through the path provided by the switches T 6 E, T 6 F and T 6 G so that the voltage V S  of the first terminal S of the driving transistor T 2 B can also be pulled down to the low voltage V low  lower than the previous voltage. A voltage of the first terminal of the capacitor C 6  and a voltage of the second terminal of the capacitor C 6  are controlled at the initial voltage Vini by the switches T 6 E and T 6 G so the voltage V G  of the control terminal G of the driving transistor T 2 B is also at the initial voltage Vini. 
     During a second duration t 2 , the switches T 2 C, T 2 D, and T 6 G are turned off. The switch T 2 A is turned on so the voltage V S  of the first terminal of the driving transistor T 2 B is at the voltage V data  of the data signal S data . The switch T 6 E is turned on and the first terminal of the switch T 6 E receives the reference voltage Vref so that the voltage of the first terminal of the capacitor C 6  is at the reference voltage Vref, and the voltage of the second terminal of the capacitor C 6 , that is, the voltage V G  of the control terminal G of the driving transistor T 2 B, is at a lower voltage firstly so the driving transistor T 2 B is turned on and the voltage V D  of the second terminal D of the driving transistor T 2 B is at the voltage V data  of the data signal S data  minus the absolute value of the threshold voltage V TH-T2B  of the driving transistor T 2 B, that is, V data −|V TH-T2B |. Since the switches T 6 F is turned on, the voltage V G  of the control terminal G of the driving transistor T 2 B remains at the same voltage as the voltage V D  of the second terminal D of the driving transistor T 2 B, that is, V data −|V TH-T2B |. 
     During a third duration t 3 , the switches T 2 A, T 6 E, T 6 F, and T 6 G are all turned off. Since the driving transistor T 2 B and the switches T 2 C and T 2 D are all turned on, the voltage of the first terminal of the capacitor C 6  is changed from the reference voltage Vref to the default voltage OVDD. Consequently, the voltage V G  of the control terminal G of the driving transistor T 2 B in pixel control circuit  600  is at (V data −V TH-T2B )+(OVDD−Vref) as shown in  FIG. 3 , and the voltage V S  of the first terminal S of the driving transistor T 2 B is at the default voltage OVDD so that the current I T2B  flowing through the driving transistor T 2 B is still independent from the threshold voltage V TH-T2B  of the driving transistor T 2 B and the default voltage OVDD. 
     Consequently, when using the pixel control circuit  600  to control pixels in a display, the nonuniformity of brightness of the image caused by different characteristics of transistors in each of the pixels and different default voltages OVDD received by each of the pixels can be avoided, and the image quality of the display can be improved. 
     In some embodiments of the present disclosure, the driving circuit  220  of the pixel control circuit  600  can also be replaced by the driving circuit  420  of the pixel control circuit  400  and can still achieve the same effect. 
     When using the pixel control circuit  200  to control pixels, since pixels in the same row have the same operation timing, it is possible to adopt a share circuit to save the number of switches and to reduce the area of the pixel array control circuit.  FIG. 7  shows a pixel array control circuit  700 . The pixel array control circuit  700  includes at least one row pixel control circuit  700 . Each of the row pixel control circuit  700  includes a plurality of pixel control circuits  712  and a share circuit  714 . Each pixel control circuit  712  includes an organic light emitting diode  7120 , a capacitor C 7 , a driving transistor T 7 B, and switches T 7 A, T 7 C, T 7 D, and T 7 E. The organic light emitting diode  7120  has a first terminal, and a second terminal for receiving a default voltage OVSS. The switch T 7 A has a first terminal for receiving the data signal S data , a second terminal, and a control terminal for receiving the first control signal SN 1 . The driving transistor T 7 B has a first terminal coupled to the second terminal of the switch T 7 A, a second terminal coupled to the first terminal of the organic light emitting diode  7120 , and a control terminal. The switch T 7 C has a first terminal, a second terminal coupled to the first terminal of the driving transistor T 7 B, and a control terminal for receiving the emission control signal EM. The capacitor C 7  has a first terminal coupled to the first terminal of the switch T 7 C, and a second terminal coupled to the control terminal of the driving transistor T 7 B. The switch T 7 D has a first terminal coupled to the second terminal of the capacitor C 7 , a second terminal coupled to the second terminal of the driving transistor T 7 B, and a control terminal for receiving the second control signal SN 2 . The switch T 7 E has a first terminal for receiving the initial voltage Vini, a second terminal coupled to the second terminal of the driving transistor T 7 B, and a control terminal for receiving the third control signal SN 3 . 
     The share circuit  714  includes switches T 7 F and T 7 G. The switch T 7 F has a first terminal for receiving the default voltage OVDD, a second terminal coupled to the first terminal of the switch T 7 C, and a control terminal for receiving the emission control signal EM. The switch T 7 G has a first terminal for receiving the reference voltage Vref, a second terminal coupled to the first terminal of the switch T 7 C, and a control terminal for receiving the second control signal SN 2 . The combination of the pixel control circuit  712  and the share circuit  714  can have the same operation principles as the pixel control circuit  200  in  FIG. 2  does. That is, the switch T 7 A can be corresponding to the switch T 2 A, the driving transistor T 7 B can be corresponding to the driving transistor T 7 B, the switch T 7 C can be corresponding to the switch T 2 C, the switch T 7 D can be corresponding to the switch T 2 F, the switch T 7 E can be corresponding to the switch T 2 G, the switch T 7 F can be corresponding to the switch T 2 D, the switch T 7 G can be corresponding to the switch T 2 E. Although the first terminal of the switch T 2 C receives the default voltage OVDD directly while the first terminal of the switch T 7 C receives the default voltage OVDD through the switch T 7 F, since both the switches T 7 C and T 7 F are controlled by the emission control signal EM, the turned on switch T 7 F will allow the switch T 7 C to receive the default voltage OVDD when the switch T 7 C is also turned on. Therefore, by using the pixel control circuit  712  and the share circuit  714 , the nonuniformity of brightness of the image caused by different characteristics of transistors in each of the pixels and different default voltages OVDD received by each of the pixels can be avoided, and the image quality of the display can be improved. Since the pixels in the same row have the same operation timing, pixels in the same row can share the same share circuit. Consequently, the pixel control circuit  712  of the pixel array control circuit  700  can be achieved by only five transistors, which can further save the area of the pixel control circuit. The area and cost saved by the pixel array control circuit  700  is even more significant especially when the resolution of the display grows or the number of pixels increases. 
     In some embodiments of the present disclosure, the pixel array control  700  may further include another share circuit  716 . The share circuit  716  has the same structure and operation principles as the share circuit  714  does. The share circuit  716  includes switches T 7 H, and T 7 I. The switch T 7 H has a first terminal for receiving the default voltage OVDD, a second terminal coupled to the first terminal of the switch T 7 C, and a control terminal for receiving the emission control signal EM. The switch T 7 I has a first terminal for receiving the reference voltage Vref, a second terminal coupled to the first terminal of the switch T 7 C, and a control terminal for receiving the second control signal SN 2 . The share circuits  714  and  716  can be disposed at two different sides of a non-display region of the display so that the issue that the pixel control circuits  712  disposed at two different sides of the display receive the default voltage OVDD and reference voltage Vref differently caused by the line loss can be solved while the area of a display region of the display can be saved. 
     In some embodiments of the present disclosure, the switches T 7 A and T 7 C to T 7 G and the driving transistor T 7 B can be P type transistors, the default voltage OVSS is smaller than the default voltage OVDD, and the second terminal of the organic light emitting diode  7120  is a cathode of the organic light emitting diode  7120 . However, the present disclosure is not limited to use P type transistors; in other embodiments of the present disclosure, switches T 7 A and T 7 C to T 7 G and the driving transistor T 7 B can also be N type transistors. 
       FIG. 9  shows a pixel array control circuit  900 . The pixel array control circuit  900  has similar structure as the structure of the pixel array control circuit  700 . The pixel array control circuit  900  includes at least one row pixel control circuit  910 . Each of the row pixel control circuit  910  includes a plurality of pixel control circuit  912  and share circuits  914  and  916 . Each pixel control circuit  912  includes an organic light emitting diode  9120 , a capacitor C 9 , a driving transistor T 9 B, and switches T 9 A, T 9 C, T 9 D, and T 9 E. The share circuit  914  includes switches T 9 F and T 9 G, and the share circuit  916  includes the switches T 9 H and T 9 I. The driving transistor T 9 B can be corresponding to the driving transistor T 7 B, and the switches T 9 A and T 9 C to T 9 I can be corresponding to the switches T 7 A and T 7 C to T 7 I respectively. The difference between these two pixel array control circuits is that the driving transistor T 9 B and the switches T 9 A and T 9 C to T 9 I of the pixel array control circuit  900  are N type transistors. Since the control operation of N type transistors is complementary to the control operation of P type transistors, the first terminals of the switches T 9 F and T 9 H receive the default voltage OVSS, and the second terminal of the organic light emitting diode  9120  receives the default voltage OVDD, that is, in the embodiment of  FIG. 9 , the second terminal of the organic light emitting diode  9120  is the anode of the organic light emitting diode  9120 . 
       FIG. 10  shows a curve diagram of the data signal to current error according to the pixel control circuit  100  in  FIG. 1 . The horizontal axis of the curve diagram shows the data signal S data  represented by grey scale, and the vertical axis of the curve diagram shows the current error I SD Err in percentages (%). The curve  1001  shows the current error I SD Err when the driving transistor T 1 B receives different values of the data signal S data  with the threshold voltageV TH-T2B  of the driving transistor T 1 B increasing by 0.2V due to parameter variation. The curve  1002  shows the current error I SD Err when the driving transistor T 1 B receives different values of the data signal S data  with the threshold voltageV TH-T1B  of the driving transistor T 1 B decreasing by 0.2V due to parameter variation. 
       FIG. 11  shows a curve diagram of the data signal to current error according to the pixel control circuit  712  in  FIG. 7 . The horizontal axis of the curve diagram shows the data signal S data  represented by grey scale, and the vertical axis of the curve diagram shows the current error I SD Err in percentages (%). The curve  1101  shows the current error I SD Err when the driving transistor T 7 B receives different values of the data signal S data  with the threshold voltageV TH-T7B  of the driving transistor T 7 B increasing by 0.2V due to parameter variation. The curve  1102  shows the current error I SD Err when the driving transistor T 7 B receives different values of the data signal S data  with the threshold voltageV TH-T7B  of the driving transistor T 7 B decreasing by 0.2V due to parameter variation. 
     According to the comparison between  FIG. 10  and  FIG. 11 , when receiving the data signals S data  of same grey scale, the current error caused by the variation of the threshold voltage V TH-T7B  of the driving transistor T 7 B in the pixel control circuit  712  is obviously smaller than the current error caused by the variation of the threshold voltage V TH-T1B  of the driving transistor T 1 B in the pixel control circuit  100 . For example, when the grey scale of the data signals S data  is 64 and both of the threshold voltages of the driving transistors T 1 B and T 7 B are increasing by 0.2V due to parameter variation, the current error of the pixel control circuit  100  is over 400% while the current error of the pixel control circuit  712  is only about 5%. In addition, the maximum current error of the pixel control circuit can reach up to 500%, but the current error of the pixel control circuit  712  can be controlled within 10%. Therefore, according to the pixel control circuit and the pixel array control circuit in the embodiments of the present disclosure, the nonuniformity of brightness of the image caused by different characteristics of transistors in each of the pixels can be significantly eased and both the yield of the display and the image quality of the display can be improved. 
     In summary, the pixel control circuit and the pixel array control circuit can avoid the nonuniformity of brightness of the image caused by different characteristics of transistors in each of the pixels and different default voltages OVDD received by each of the pixels can be avoided, and the image quality of the display can be improved. Also, since the discharge circuits of the pixel control circuits in the aforesaid embodiments can provide discharging paths, the issue of the black image being not dark enough, which caused by the remaining charges in the pixels, can also be solved. The pixel control circuits can further combined with the share circuit to be a pixel array pixel control circuit according to the embodiments of the present disclosure to save the circuit area. 
     Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.