Patent Publication Number: US-2022230689-A1

Title: Array of electrically erasable programmable read only memory (eeprom) and forming method thereof

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates generally to an array of memory cells and forming method thereof, and more specifically to an array of electrically erasable programmable read only memory (EEPROM) and forming method thereof. 
     2. Description of the Prior Art 
     An electrically programmable read only memory (EPROM) utilizes a floating (unconnected) conductive gate, in a field effect transistor structure, positioned over but insulated from a channel region in a semi-conductor substrate, between source and drain regions. A control gate is then provided over the floating gate, but also insulated therefrom. The threshold voltage characteristic of the transistor is controlled by the amount of charge that is retained on the floating gate. That is, the minimum amount of voltage (threshold) that must be applied to the control gate before the transistor is turned “on” to permit conduction between its source and drain regions is controlled by the level of charge on the floating gate. A transistor is programmed to one of two states by accelerating electrons from the substrate channel region, through a thin gate dielectric and onto the floating gate. 
     The memory cell transistor&#39;s state is read by placing an operating voltage across its source and drain and on its control gate, and then detecting the level of current flowing between the source and drain as to whether the device is programmed to be “on” or “off” at the control gate voltage selected. 
     SUMMARY OF THE INVENTION 
     The present invention provides an array of electrically erasable programmable read only memory (EEPROM) and forming method thereof, which forms rows of floating gates having staggered islands to reduce the cross talk capacitance and keep the macro size of the array of erasably programmable read only memory cells. 
     The present invention provides an array of electrically erasable programmable read only memory (EEPROM) including a substrate, bit lines, a row of erase gate and a row of floating gates. The bit lines are defined in the substrate to extend in a first direction. The row of erase gate having a wave shape is disposed across the bit lines. The row of floating gates having staggered islands is disposed parallel to the row of erase gate. 
     The present invention provides a method of forming an array of electrically erasable programmable read only memory (EEPROM) including the following steps. A row of floating gates having staggered islands is formed on a substrate. A row of erase gate having a wave shape is formed on the substrate at a first side of the row of floating gates. A row of word line having the wave shape is formed on the substrate at a second side of the row of floating gates opposite to the first side. 
     According to the above, the present invention provides an array of electrically erasable programmable read only memory (EEPROM) and forming method thereof, which includes a row of erase gate having a wave shape disposed across bit lines, a row of floating gates having staggered islands disposed parallel to the row of erase gate, and a row of word line having the wave shape disposed parallel to the row of erase gate and at a side of the row of floating gates opposite to the row of erase gate. By doing this, the spacings of the adjacent floating gates of the row of floating gates increase. This reduces the cross talk capacitance, and there is no impact on the macro size of the array of erasably programmable read only memory cells. 
     These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  schematically depicts a top view of an array of electrically erasable programmable read only memory (EEPROM) according to an embodiment of the present invention. 
         FIG. 2  schematically depicts a top view of rows of floating gates according to an embodiment of the present invention. 
         FIG. 3  schematically depicts a cross-sectional view of a method of forming an array of electrically erasable programmable read only memory (EEPROM) according to an embodiment of the present invention. 
         FIG. 4  schematically depicts a cross-sectional view of a method of forming an array of electrically erasable programmable read only memory (EEPROM) according to an embodiment of the present invention. 
         FIG. 5  schematically depicts a cross-sectional view of a method of forming an array of electrically erasable programmable read only memory (EEPROM) according to an embodiment of the present invention. 
         FIG. 6  schematically depicts a cross-sectional view of a method of forming an array of electrically erasable programmable read only memory (EEPROM) according to an embodiment of the present invention. 
         FIG. 7  schematically depicts a cross-sectional view of a method of forming an array of electrically erasable programmable read only memory (EEPROM) according to an embodiment of the present invention. 
         FIG. 8  schematically depicts a cross-sectional view of a method of forming an array of electrically erasable programmable read only memory (EEPROM) according to an embodiment of the present invention. 
         FIG. 9  schematically depicts a cross-sectional view of a method of forming an array of electrically erasable programmable read only memory (EEPROM) according to an embodiment of the present invention. 
         FIG. 10  schematically depicts a cross-sectional view of a method of forming an array of electrically erasable programmable read only memory (EEPROM) according to an embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION 
       FIG. 1  schematically depicts a top view of an array of electrically erasable programmable read only memory (EEPROM) according to an embodiment of the present invention. As shown in  FIG. 1 , a substrate  110  is provided. Bit lines  120  are defined in the substrate  110 , wherein the bit lines  120  extend in a first direction D 1 . Isolation structures  12  separate and isolate the bit lines  120  from each other. Rows of erase gates  20  are disposed across the bit lines  120 . In this present invention, the rows of erase gates  20  have wave shapes. 
     Rows of floating gates  30  are disposed parallel to the row of erase gate  20 , but the row of floating gates  30  are only disposed on and vertically overlap the bit lines  120 , and therefore the row of floating gates  30  are staggered islands.  FIG. 2  schematically depicts a top view of rows of floating gates according to an embodiment of the present invention. The rows of floating gates  30  are staggered islands, and vertically overlap the bit lines  120  completely. The adjacent floating gates of the rows of floating gates  30  are dislocated. Therefore, the spacings P of the adjacent floating gates of the rows of floating gates  30  increase, and thus the cross talk capacitance is reduced, and there is no impact on the macro size of the array of erasably programmable read only memory cells  100 . In a preferred embodiment, a ratio of a gap g between the adjacent floating gates and a shifting s between the adjacent floating gates is 63:45-45:63, thereby the cross talk capacitance can being reduced more than 20% while the macro size of the array of erasably programmable read only memory cells  100  only increases less than 0.4%. 
     Please refer to  FIG. 1 , rows of word lines  40  are also disposed parallel to the rows of erase gates  20  and at sides of the row of floating gates  30  opposite to the rows of erase gates  20 , wherein the rows of word lines  40  have the wave shapes common to the wave shapes of the rows of erase gates  20  in a preferred embodiment to improve the layout of the array of erasably programmable read only memory cells  100 . In this embodiment, there is no control gate disposed in the array of electrically erasable programmable read only memory (EEPROM). 
     The rows of erase gates  20  have the wave shapes constituted by first parts  22  and second parts  24 . The first parts  22  connect to the second parts  24 , and the first parts  22  and the second parts  24  are alternatively arranged. The first parts  22  overlap the bit lines  120  completely, and the second parts  24  are disposed between the bit lines  120 . Furthermore, the second parts  24  may include second-one parts  24   a  and second-two parts  24   b , wherein the second-one parts  24   a  and the second-two parts  24   b  connect to the first parts  22  alternatively. In this embodiment, the second-one parts  24   a  and the second-two parts  24   b  extend along different directions to constitute the wave shapes of the rows of erase gates  20 . Hence, the adjacent first parts  22  are also dislocated and are distributed right next to the adjacent floating gates of the rows of floating gates  30 . 
     More precisely, the first parts  22  extend along a second direction D 2 , the second-one parts  24   a  extend along a third direction D 3  and the second-two parts  24   b  extend along a fourth direction D 4 . In a preferred embodiment, the second direction D 2  is orthogonal to the first direction D 1 , and the third direction D 3  and the fourth direction D 4  have common absolute values of slope for improving the layout and the macro size of the array of erasably programmable read only memory cells  100 . 
     A method of forming said array of electrically erasable programmable read only memory (EEPROM)  100  is presented as follows.  FIG. 3-10  schematically depict cross-sectional views of a method of forming an array of electrically erasable programmable read only memory (EEPROM) according to an embodiment of the present invention for illustrating the present invention, wherein same symbols of  FIGS. 3-10  represent same components corresponding to  FIGS. 1-2 . 
       FIGS. 3-5  are the cross-sectional views along line AA′ of  FIG. 1 , and  FIGS. 6-10  are the cross-sectional views along line BB′ of  FIG. 1 . 
     Please refer to  FIG. 3 , which is the cross-sectional view along the line AA′ of  FIG. 1 , the substrate  110  is provided. The substrate is a silicon substrate in this embodiment. Please refer to  FIGS. 4-6 , the row of floating gates  30  having staggered islands are formed on the substrate  110 . The row of floating gates  30  include an ONO layer (silicon oxide/silicon nitride/silicon oxide layer)  32 , a polysilicon layer  34  and a cap layer  36  stacked from bottom to top, but it is not limited thereto. As shown in  FIG. 4 , which is the cross-sectional view along the line AA′ of  FIG. 1 , a floating gate film stack  30   a  is deposited on the substrate  110  blanketly, wherein the floating gate film stack  30   a  may include an ONO layer  32   a , a polysilicon layer  34   a  and a cap layer  36   a , but it is not limited thereto. As shown in  FIG. 5 , the isolation structures  12  are formed in the substrate  110 , and therefore the bit line  120  is defined in the substrate  110  and is sandwiched by the isolation structures  12 , and a floating gate film stack  30   b  covering the bit line  120  and sandwiched by the isolation structures  12  is also formed. As shown in  FIG. 6 , which is the cross-sectional view along the line BB′ of  FIG. 1 , the floating gate film stack  30   b  is patterned to form the row of floating gates  30  having staggered islands. 
     As shown in  FIG. 7 , which is the cross-sectional view along the line BB′ of  FIG. 1 , spacers  32  are formed beside the row of floating gates  30 . A source line  50  is implanted in the substrate  110  beside a side S 1  of the row of floating gates  30 . 
     As shown in  FIG. 8 , which is the cross-sectional view along the line BB′ of  FIG. 1 , a word line well  60  is doped in the substrate  110  at a side S 2  of the row of floating gates  30 . 
     As shown in  FIG. 9 , which is the cross-sectional view along the line BB′ of  FIG. 1 , the row of erase gate  20  having the wave shape is formed on the substrate  110  at the side S 1  of the row of floating gates  30 , and the row of word line  40  having the wave shape is formed on the substrate  110  at the side S 2  of the row of floating gate  30  opposite to the side S 1 . In this case, the row of erase gate  20  and the row of word line  40  are formed at a same time, but the present invention is not restricted thereto. Thus, the source line  50  is located right below the row of erase gate  20 . 
     As shown in  FIG. 10 , which is the cross-sectional view along the line BB′ of  FIG. 1 , a halo implantation region  72  and a lightly doped region  76  are formed in the word line well  60  beside the row of word line  40  and a heavily doped region  78  is formed in the lightly doped region  76  beside the row of word line  40 . Above all, methods of forming said components are well known in the art, and are not described. 
     To summarize, the present invention provides an array of electrically erasable programmable read only memory (EEPROM) and forming method thereof, which includes bit lines defined in a substrate, a row of erase gate having a wave shape disposed across the bit lines, a row of floating gates having staggered islands disposed parallel to the row of erase gate, and a row of word line having the wave shape disposed parallel to the row of erase gate and at a side of the row of floating gates opposite to the row of erase gate. By doing this, floating gates of the row of floating gates are dislocated and thus the spacings of the adjacent floating gates of the rows of floating gates increase. Hence, the cross talk capacitance is reduced, and there is no impact on the macro size of the array of erasably programmable read only memory cells. 
     Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.