Patent Publication Number: US-10784906-B2

Title: Transmitting device, transmitting method, and communication system

Description:
TECHNICAL FIELD 
     The present disclosure relates to a transmitting device that transmits a signal, a transmitting method employed in such a transmitting device, and a communication system including such a transmitting device. 
     BACKGROUND ART 
     With high functionalization and multi-functionalization of electronic apparatuses in recent years, electronic apparatuses are equipped with various devices such as a semiconductor chip, a sensor, and a display device. These devices exchange a lot of data between them, and the data amount has increased in accordance with the high functionalization and multi-functionalization of electronic apparatuses. Accordingly, a high-speed interface that is able to transmit and receive data, for example, at a few Gbps (gigabits per second) is often used to perform data exchange. 
     In such a communication system, a single-phase signal or a differential signal is often used to perform data exchange. Furthermore, there is a communication system that uses a signal having multiple voltage levels to perform data exchange. For example, PTLs 1 and 2 disclose a communication system that uses three voltage levels to perform data exchange. 
     CITATION LIST 
     Patent Literatures 
     PTL 1: Japanese Unexamined Patent Application Publication (Published Japanese Translation of PCT Application) No. JP2011-517159 
     PTL 2: Japanese Unexamined Patent Application Publication (Published Japanese Translation of PCT Application) No. JP2010-520715 
     SUMMARY OF THE INVENTION 
     Incidentally, an electronic apparatus is often equipped with various devices supplied from vendors. Such devices may include an interface different from one another. Therefore, a device that exchanges data with such devices is desirably able to implement various interfaces. 
     It is desirable to provide a transmitting device, a transmitting method, and a communication system that make it possible to implement various interfaces. 
     A transmitting device of an embodiment of the present disclosure includes a first driver and a controller. The first driver includes a first sub-driver unit that operates on a basis of a first control signal and a second sub-driver unit that operates on a basis of, out of the first control signal and a second control signal, a signal selected through a first selecting operation, and is able to set a voltage at a first output terminal. The controller controls the first selecting operation. 
     A transmitting method of an embodiment of the present disclosure includes: preparing a first control signal and a second control signal; and causing a first sub-driver unit to operate on the basis of the first control signal and a second sub-driver unit to operate on the basis of, out of the first control signal and the second control signal, a signal selected through a first selecting operation, thereby setting a voltage at a first output terminal. 
     A communication system of an embodiment of the present disclosure includes a transmitting device and a receiving device. The transmitting device includes a first driver and a controller. The first driver includes a first sub-driver unit that operates on the basis of a first control signal and a second sub-driver unit that operates on the basis of, out of the first control signal and a second control signal, a signal selected through a first selecting operation, and is able to set a voltage at a first output terminal. The controller controls the first selecting operation. 
     In the transmitting device, the transmitting method, and the communication system of the embodiments of the present disclosure, one of the first control signal and the second control signal is selected through the first selecting operation. Then, the first sub-driver unit operates on the basis of the first control signal, and the second sub-driver unit operates on the basis of, out of the first control signal and the second control signal, a signal selected through the first selecting operation, thereby the voltage at the first output terminal is set. 
     According to the transmitting device, the transmitting method, and the communication system of the embodiments of the present disclosure, the first sub-driver unit operates on the basis of the first control signal, and the second sub-driver unit operates on the basis of, out of the first control signal and the second control signal, a signal selected through the first selecting operation; therefore, it is possible to implement various interfaces. It is to be noted that the effects described here are not necessarily limited, and any effect described in the present disclosure may be provided. 
    
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         FIG. 1A  is a block diagram illustrating a configuration example of a communication system to which a transmitting device according to a first embodiment of the present disclosure is applied. 
         FIG. 1B  is a block diagram illustrating a configuration example of another communication system to which the transmitting device according to the first embodiment is applied. 
         FIG. 2  is a block diagram illustrating a configuration example of a transmitter according to the first embodiment. 
         FIG. 3  is a circuit diagram illustrating a configuration example of a serializer illustrated in  FIG. 2 . 
         FIG. 4  is a timing waveform diagram illustrating an operation example of the serializer illustrated in  FIG. 2 . 
         FIG. 5  is another timing waveform diagram illustrating an operation example of the serializer illustrated in  FIG. 2 . 
         FIG. 6  is a timing waveform diagram illustrating an operation example of a multiplexer illustrated in  FIG. 2 . 
         FIG. 7  is a timing waveform diagram illustrating another operation example of the multiplexer illustrated in  FIG. 2 . 
         FIG. 8  is a circuit diagram illustrating a configuration example of drivers illustrated in  FIG. 2 . 
         FIG. 9  is a circuit diagram illustrating a configuration example of a receiver illustrated in  FIG. 1A . 
         FIG. 10  is a circuit diagram illustrating a configuration example of a receiver illustrated in  FIG. 1B . 
         FIG. 11  is a diagram that describes an operation example of the transmitter illustrated in  FIG. 2 . 
         FIG. 12  is a diagram that describes another operation example of the transmitter illustrated in  FIG. 2 . 
         FIG. 13  is a diagram that describes another operation example of the transmitter illustrated in  FIG. 2 . 
         FIG. 14  is a diagram that describes another operation example of the transmitter illustrated in  FIG. 2 . 
         FIG. 15  is a diagram that describes another operation example of the transmitter illustrated in  FIG. 2 . 
         FIG. 16  is a timing waveform diagram illustrating an operation example of the transmitter illustrated in  FIG. 2 . 
         FIG. 17  is a block diagram illustrating a configuration example of a transmitter according to a comparative example. 
         FIG. 18  is a diagram that describes an operation example of the transmitter illustrated in  FIG. 17 . 
         FIG. 19  is a diagram that describes another operation example of the transmitter illustrated in  FIG. 17 . 
         FIG. 20  is a block diagram illustrating a configuration example of another transmitter according to a comparative example. 
         FIG. 21  is a diagram that describes an operation example of the transmitter illustrated in  FIG. 20 . 
         FIG. 22  is a diagram that describes another operation example of the transmitter illustrated in  FIG. 20 . 
         FIG. 23  is a circuit diagram illustrating a configuration example of a serializer according to a modification example. 
         FIG. 24  is a circuit diagram illustrating a configuration example of a serializer according to another modification example. 
         FIG. 25  is a timing waveform diagram illustrating an operation example of the serializer illustrated in  FIG. 24 . 
         FIG. 26  is a timing waveform diagram illustrating an operation example of a serializer according to another modification example. 
         FIG. 27  is a circuit diagram illustrating a configuration example of a serializer according to another modification example. 
         FIG. 28  is a timing waveform diagram illustrating an operation example of the serializer illustrated in  FIG. 27 . 
         FIG. 29  is a block diagram illustrating a configuration example of a transmitter according to another modification example. 
         FIG. 30  is a circuit diagram illustrating a configuration example of drivers illustrated in  FIG. 29 . 
         FIG. 31  is a circuit diagram illustrating a configuration example of another driver illustrated in  FIG. 29 . 
         FIG. 32  is a diagram that describes an operation example of the transmitter illustrated in  FIG. 29 . 
         FIG. 33  is a diagram that describes another operation example of the transmitter illustrated in  FIG. 29 . 
         FIG. 34  is a block diagram illustrating a configuration example of a transmitter according to another modification example. 
         FIG. 35  is a diagram that describes an operation example of the transmitter illustrated in  FIG. 34 . 
         FIG. 36  is a diagram that describes another operation example of the transmitter illustrated in  FIG. 34 . 
         FIG. 37A  is a block diagram illustrating a configuration example of a communication system to which a transmitting device according to a second embodiment is applied. 
         FIG. 37B  is a block diagram illustrating a configuration example of another communication system to which the transmitting device according to the second embodiment is applied. 
         FIG. 37C  is a block diagram illustrating a configuration example of another communication system to which the transmitting device according to the second embodiment is applied. 
         FIG. 38  is a diagram that describes an example of signals used in the communication system illustrated in  FIG. 37C . 
         FIG. 39  is a block diagram illustrating a configuration example of a transmitter according to the second embodiment  FIG. 40A  is a block diagram illustrating a configuration example of a transmitting circuit unit illustrated in  FIG. 39 . 
         FIG. 40B  is a block diagram illustrating a configuration example of another transmitting circuit unit illustrated in  FIG. 39 . 
         FIG. 41  is a diagram that describes an example of signal paths in the transmitting circuit units illustrated in  FIGS. 40A and 40B . 
         FIG. 42  is a circuit diagram illustrating a configuration example of an encoder illustrated in  FIGS. 40A and 40B . 
         FIG. 43  is a truth table illustrating an operation example of the encoder illustrated in  FIG. 42 . 
         FIG. 44  is a circuit diagram illustrating a configuration example of another encoder. 
         FIG. 45  is a circuit diagram illustrating a configuration example of a receiver illustrated in  FIG. 37C . 
         FIG. 46  is a diagram that describes an operation example of the receiver illustrated in  FIG. 45 . 
         FIG. 47A  is a diagram that describes an operation example of the transmitting circuit unit illustrated in  FIG. 40A . 
         FIG. 47B  is a diagram that describes an operation example of the other transmitting circuit unit illustrated in  FIG. 40B . 
         FIG. 48  is a table illustrating an operation example of the transmitting circuit units illustrated in  FIGS. 40A and 40B . 
         FIG. 49A  is a diagram that describes another operation example of the transmitting circuit unit illustrated in  FIG. 40A . 
         FIG. 49B  is a diagram that describes another operation example of the other transmitting circuit unit illustrated in  FIG. 40B . 
         FIG. 50A  is a block diagram illustrating a configuration example of a transmitting circuit unit according to a modification example. 
         FIG. 50B  is a block diagram illustrating a configuration example of another transmitting circuit unit according to the modification example. 
         FIG. 51  is a diagram that describes an example of signal paths in the transmitting circuit units illustrated in  FIGS. 50A and 50B . 
         FIG. 52  is a circuit diagram illustrating a configuration example of an encoder illustrated in  FIGS. 50A and 50B . 
         FIG. 53  is a truth table illustrating an operation example of the encoder illustrated in  FIG. 52 . 
         FIG. 54  is a circuit diagram illustrating a configuration example of another encoder. 
         FIG. 55  is a block diagram illustrating a configuration example of a transmitter according to another modification example. 
         FIG. 56A  is a block diagram illustrating a configuration example of a transmitting circuit units illustrated in  FIG. 55 . 
         FIG. 56B  is a block diagram illustrating a configuration example of another transmitting circuit unit illustrated in  FIG. 55 . 
         FIG. 57  is a circuit diagram illustrating a configuration example of a serializer illustrated in  FIGS. 56A and 56B . 
         FIG. 58  is a diagram that describes an example of signal paths in the transmitting circuit units illustrated in  FIGS. 56A and 56B . 
         FIG. 59A  is a block diagram illustrating a configuration example of a transmitting circuit unit according to another modification example. 
         FIG. 59B  is a block diagram illustrating a configuration example of another transmitting circuit unit according to another modification example. 
         FIG. 60A  is a block diagram illustrating a configuration example of a transmitting circuit unit according to a third embodiment. 
         FIG. 60B  is a block diagram illustrating a configuration example of another transmitting circuit unit according to the third embodiment. 
         FIG. 61  is a circuit diagram illustrating a configuration example of drivers illustrated in  FIGS. 60A and 60B . 
         FIG. 62  is a diagram that describes an operation example of the transmitting circuit unit illustrated in  FIG. 60A . 
         FIG. 63  is a diagram that describes another operation example of the transmitting circuit unit illustrated in  FIG. 60A . 
         FIG. 64A  is a diagram that describes another operation example of the transmitting circuit unit illustrated in  FIG. 60A . 
         FIG. 64B  is a diagram that describes another operation example of the transmitting circuit unit illustrated in  FIG. 60B . 
         FIG. 65A  is a block diagram illustrating a configuration example of a transmitting circuit unit according to a modification example. 
         FIG. 65B  is a block diagram illustrating a configuration example of another transmitting circuit unit according to the modification example. 
         FIG. 66  is a diagram that describes an operation example of the transmitting circuit unit illustrated in  FIG. 65A . 
         FIG. 67  is a diagram that describes another operation example of the transmitting circuit unit illustrated in  FIG. 65A . 
         FIG. 68A  is a diagram that describes another operation example of the transmitting circuit unit illustrated in  FIG. 65A . 
         FIG. 68B  is a diagram that describes another operation example of the transmitting circuit unit illustrated in  FIG. 65B . 
         FIG. 69A  is a block diagram illustrating a configuration example of a transmitting circuit unit according to another modification example. 
         FIG. 69B  is a block diagram illustrating a configuration example of another transmitting circuit unit according to another modification example. 
         FIG. 70A  is a block diagram illustrating a configuration example of a transmitting circuit unit according to another modification example. 
         FIG. 70B  is a block diagram illustrating a configuration example of another transmitting circuit unit according to another modification example. 
         FIG. 71A  is a block diagram illustrating a configuration example of a transmitting circuit unit according to another modification example. 
         FIG. 71B  is a block diagram illustrating a configuration example of another transmitting circuit unit according to another modification example. 
         FIG. 72  is a perspective view illustrating an external appearance configuration of a smartphone to which the transmitting device according to the embodiments is applied. 
         FIG. 73  is a block diagram illustrating a configuration example of an application processor to which the transmitting device according to the embodiments is applied. 
         FIG. 74  is a block diagram illustrating a configuration example of an image sensor to which the transmitting device according to the embodiments is applied. 
         FIG. 75  is a block diagram illustrating a configuration example of a vehicle control system to which the communication system according to one of the embodiments is applied. 
     
    
    
     MODES FOR CARRYING OUT THE INVENTION 
     In the following, some embodiments of the present disclosure are described in detail with reference to drawings. It is to be noted that description is made in the following order. 
     1. First Embodiment 
     2. Second Embodiment 
     3. Third Embodiment 
     4. Application Example 
     1. First Embodiment 
     [Configuration] 
       FIGS. 1A and 1B  illustrate respective configuration examples of communication systems to which a transmitting device (a transmitting device  10 ) according to a first embodiment is applied;  FIG. 1A  illustrates a communication system  1 A, and  FIG. 1B  illustrates a communication system  1 B. The communication system  1 A performs communication using a single-phase signal, and the communication system  1 B performs communication using a differential signal. 
     As illustrated in  FIG. 1A , the communication system  1 A includes the transmitting device  10  and a receiving device  30 . The transmitting device  10  has two output terminals Tout 1  and Tout 2 , and the receiving device  30  has two input terminals Tin 1  and Tin 2 . The output terminal Tout 1  of the transmitting device  10  and the input terminal Tin 1  of the receiving device  30  are coupled to each other through a line  101 , and the output terminal Tout 2  of the transmitting device  10  and the input terminal Tin 2  of the receiving device  30  are coupled to each other through a line  102 . Respective characteristic impedances of the lines  101  and  102  are about 50[Ω] in this example. The transmitting device  10  uses the line  101  to transmit a signal SIG 1 , and uses the line  102  to transmit a signal SIG 2 . The signals SIG 1  and SIG 2  are both a single-phase signal. 
     As illustrated in  FIG. 1B , the communication system  1 B includes the transmitting device  10  and a receiving device  40 . The receiving device  40  has two input terminals TinP and TinN. The output terminal Tout 1  of the transmitting device  10  and the input terminal TinP of the receiving device  40  are coupled to each other through a line  111 , and the output terminal Tout 2  of the transmitting device  10  and the input terminal TinN of the receiving device  40  are coupled to each other through a line  112 . Respective characteristic impedances of the lines  111  and  112  are about 50[Ω] in this example. The transmitting device  10  uses the line  111  to transmit a signal SIGP, and uses the line  112  to transmit a signal SIGN. The signals SIGP and SIGN compose a differential signal. In the communication system  1 B, as will be described later, the transmitting device  10  performs a so-called emphasis operation (pre-emphasis, de-emphasis), thereby transmitting signals SIGP and SIGN. 
     The transmitting device  10  has two operation modes MA and MB. In a case where the transmitting device  10  is applied to the communication system  1 A, the transmitting device  10  operates in the operation mode MA (single-phase mode); in a case where the transmitting device  10  is applied to the communication system  1 B, the transmitting device  10  operates in the operation mode MB (differential mode). 
     (Transmitting Device  10 ) 
     The transmitting device  10  includes a processor  11  and a transmitter  12  as illustrated in  FIGS. 1A and 1B . 
     The processor  11  generates data to be transmitted by performing a predetermined process. Furthermore, the processor  11  selects one of the two operation modes MA and MB, and notifies the transmitter  12  of the selected operation mode by using a mode signal Smode. Specifically, in a case where the transmitting device  10  is applied to the communication system  1 A, the processor  11  selects the operation mode MA (single-phase mode), and instructs the transmitter  12  to perform the operation in the operation mode MA by using a mode signal Smode. Furthermore, in a case where the transmitting device  10  is applied to the communication system  1 B, the transmitter  12  selects the operation mode MB (differential mode), and instructs the transmitter  12  to perform the operation in the operation mode MB by using a mode signal Smode. 
     The transmitter  12  transmits data generated by the processor  11  on the basis of a mode signal Smode. Specifically, in a case where the operation mode indicated by the mode signal Smode is the operation mode MA (single-phase mode), the transmitter  12  transmits data generated by the processor  11  by using signals SIG 1  and SIG 2 . Furthermore, in a case where the operation mode indicated by the mode signal Smode is the operation mode MB, the transmitter  12  transmits data generated by the processor  11  by using signals SIGP and SIGN. 
       FIG. 2  illustrates a configuration example of the transmitter  12 . The transmitter  12  includes four serializers  21  (serializers  21 A,  21 B,  21 C, and  21 D), four multiplexers (MUXs)  22  (multiplexers  22 A,  22 B,  22 C, and  22 D), four selectors (SELs)  23  (selectors  23 A,  23 B,  23 C, and  23 D), two drivers  24  (drivers  24 A and  24 B), and a controller  25 . 
     The serializer  21 A serializes signals DI 10 , DI 12 , DI 14 , and DI 16  on the basis of clock signals P 0 , P 2 , P 4 , and P 6 , thereby generating signals S 21 AP and S 21 AN. The signals S 21 AP and S 21 AN are signals that are inverted from each other. Likewise, the serializer  21 B serializes signals DI 20 , DI 22 , DI 24 , and DI 26  on the basis of clock signals P 0 , P 2 , P 4 , and P 6 , thereby generating signals S 21 BP and S 21 BN. The signals S 21 BP and S 21 BN are signals that are inverted from each other. The serializer  21 C serializes signals DI 11 , DI 13 , DI 15 , and DI 17  on the basis of clock signals P 1 , P 3 , P 5 , and P 7 , thereby generating signals S 21 CP and S 21 CN. The signals S 21 CP and S 21 CN are signals that are inverted from each other. The serializer  21 D serializes signals DI 21 , DI 23 , DI 25 , and DI 27  on the basis of clock signals P 1 , P 3 , P 5 , and P 7 , thereby generating signals S 21 DP and S 21 DN. The signals S 21 DP and S 21 DN are signals that are inverted from each other. 
     In the operation mode MA (single-phase mode), the signals DI 10 , SI 11 , DI 12 , DI 13 , DI 14 , DI 15 , DI 16 , and DI 17  are transmitted by using a signal SIG 1 , and the signals DI 20 , S 121 , DI 22 , DI 23 , DI 24 , DI 25 , DI 26 , and DI 27  are transmitted by using a signal SIG 2 . 
     Furthermore, in the operation mode MB (differential mode), the signals DI 10 , SI 11 , DI 12 , DI 13 , DI 14 , DI 15 , DI 16 , and DI 17  are transmitted by using signals SIGP and SIGN. Moreover, in this operation mode MB, the signals DI 20 , SI 21 , DI 22 , DI 23 , DI 24 , DI 25 , DI 26 , and DI 27  are used to perform an emphasis operation. As described below, data indicated by these signals DI 20  to DI 27  is set to be shifted by one bit from data indicated by the signals DI 10  to DI 17 . 
       FIG. 3  illustrates a configuration example of the serializer  21 A. It is to be noted that the same applies to the serializers  21 B,  21 C, and  21 D. The serializer  21 A is a so-called selector type serializer. The serializer  21 A includes transistors M 1  to M 12 . The transistors M 1  to M 10  are N-channel MOS (metal oxide semiconductor) type FETs (field effect transistors), and the transistors M 11  and M 12  are P-channel MOS type FETs. The signal DI 10  includes signals DI 10 P and DI 10 N that are inverted from each other; the signal DI 12  includes signals DI 12 P and DI 12 N that are inverted from each other; the signal DI 14  includes signals DI 14 P and DI 14 N that are inverted from each other; the signal DI 16  includes signals DI 16 P and DI 16 N that are inverted from each other. 
     A source of the transistor M 1  is supplied with the signal DI 10 P, and a gate is supplied with the clock signal P 0 , and a drain is coupled to drains of the transistors M 3 , M 5 , and M 7  and a source of the transistor M 9 . A source of the transistor M 2  is supplied with the signal DI 10 N, and a gate is supplied with the clock signal P 0 , and a drain is coupled to drains of the transistors M 4 , M 6 , and M 8  and a source of the transistor M 10 . A source of the transistor M 3  is supplied with the signal DI 12 P, and a gate is supplied with the clock signal P 2 , and the drain is coupled to the drains of the transistors M 1 , M 5 , and M 7  and the source of the transistor M 9 . A source of the transistor M 4  is supplied with the signal DI 12 N, and a gate is supplied with the clock signal P 2 , and the drain is coupled to the drains of the transistors M 2 , M 6 , and M 8  and the source of the transistor M 10 . A source of the transistor M 5  is supplied with the signal DI 14 P, and a gate is supplied with the clock signal P 4 , and the drain is coupled to the drains of the transistors M 1 , M 3 , and M 7  and the source of the transistor M 9 . A source of the transistor M 6  is supplied with the signal DI 14 N, and a gate is supplied with the clock signal P 4 , and the drain is coupled to the drains of the transistors M 2 , M 4 , and M 8  and the source of the transistor M 10 . A source of the transistor M 7  is supplied with the signal DI 16 P, and a gate is supplied with the clock signal P 6 , and the drain is coupled to the drains of the transistors M 1 , M 3 , and M 5  and the source of the transistor M 9 . A source of the transistor M 8  is supplied with the signal DI 16 N, and a gate is supplied with the clock signal P 6 , and the drain is coupled to the drains of the transistors M 2 , M 4 , and M 6  and the source of the transistor M 10 . The source of the transistor M 9  is coupled to the drains of the transistors M 1 , M 3 , M 5 , and M 7 , and a gate is supplied with a power supply voltage VDD, and a drain is coupled to a drain of the transistor M 11  and a gate of the transistor M 12 . The source of the transistor M 10  is coupled to the drains of the transistors M 2 , M 4 , M 6 , and M 8 , and a gate is supplied with the power supply voltage VDD, and a drain is coupled to a drain of the transistor M 12  and a gate of the transistor M 11 . A source of the transistor M 11  is supplied with the power supply voltage VDD, and the gate is coupled to the drains of the transistors M 10  and M 12 , and the drain is coupled to the drain of the transistor M 9  and the gate of the transistor M 12 . A source of the transistor M 12  is supplied with the power supply voltage VDD, and the gate is coupled to the drains of the transistors M 9  and M 11 , and the drain is coupled to the drain of the transistor M 10  and the gate of the transistor M 11 . The serializer  21 A outputs the signal S 21 AP from the drains of the transistors M 9  and M 11 , and outputs the signal S 21 AN from the drains of the transistors M 10  and M 12 . 
     In  FIG. 4 , (A) to (I) illustrate an operation example of the serializer  21 A; (A) to (D) illustrate respective waveforms of the signals DI 10 , DI 12 , DI 14 , and DI 16 , and (E) to (H) illustrate respective waveforms of the clock signals P 0 , P 2 , P 4 , and P 6 , and (I) illustrates waveforms of the signals S 21 AP and S 21 AN. In  FIG. 4 , (J) to (R) illustrate an operation example of the serializer  21 C; (J) to (M) illustrate respective waveforms of the signals DI 11 , DI 13 , DI 15 , and DI 17 , (N) to (Q) illustrate respective waveforms of the clock signals P 1 , P 3 , P 5 , and P 7 , and (R) illustrates waveforms of the signals S 21 CP and S 21 CN. 
     In this example, at timing t 11 , the signal DI 10  is set to data “D 0 ( n )”, and the signal DI 12  is set to data “D 2 ( n )” ((A) and (B) in  FIG. 4 ). Furthermore, at timing t 12 , the signal DI 11  is set to data “D 1 ( n )”, and the signal DI 13  is set to data “D 3 ( n )” ((J) and (K) in  FIG. 4 ). At timing t 15 , the signal DI 14  is set to data “D 4 ( n )”, and the signal DI 16  is set to data “D 6 ( n )” ((C) and (D) in  FIG. 4 ). At timing t 16 , the signal DI 15  is set to data “D 5 ( n )”, and the signal DI 17  is set to data “D 7 ( n )” ((L) and (M) in  FIG. 4 ). 
     The clock signal P 0  makes a transition from low level to high level at timing t 13 , and makes a transition from high level to low level at timing t 15  ((E) in  FIG. 4 ). Accordingly, in a period from timing t 13  to timing t 15 , the serializer  21 A selects the signal DI 10  (the data “D 2 ( n )”) and outputs it as signals S 21 AP and S 21 AN ((I) in  FIG. 4 ). The clock signal P 2  makes a transition from low level to high level at timing t 15 , and makes a transition from high level to low level at timing t 17  ((F) in  FIG. 4 ). Accordingly, in a period from timing t 15  to timing t 17 , the serializer  21 A selects the signal DI 12  (the data “D 2 ( n )”) and outputs it as signals S 21 AP and S 21 AN ((I) in  FIG. 4 ). The clock signal P 4  makes a transition from low level to high level at timing t 17 , and makes a transition from high level to low level at timing t 19  ((G) in  FIG. 4 ). Accordingly, in a period from timing t 17  to timing t 19 , the serializer  21 A selects the signal DI 14  (the data “D 4 ( n )”) and outputs it as signals S 21 AP and S 21 AN ((I) in  FIG. 4 ). The clock signal P 6  makes a transition from low level to high level at timing t 19 , and makes a transition from high level to low level at timing t 21  ((H) in  FIG. 4 ). Accordingly, in a period from timing t 19  to timing t 21 , the serializer  21 A selects the signal DI 16  (the data “D 6 ( n )”) and outputs it as signals S 21 AP and S 21 AN ((I) in FIG.  4 ). 
     The clock signal P 1  makes a transition from low level to high level at timing t 14 , and makes a transition from high level to low level at timing t 16  ((N) in  FIG. 4 ). Accordingly, in a period from timing t 14  to timing t 16 , the serializer  21 C selects the signal DI 11  (the data “D 1 ( n )”) and outputs it as the signals S 21 CP and S 21 CN ((R) in  FIG. 4 ). The clock signal P 3  makes a transition from low level to high level at timing t 16 , and makes a transition from high level to low level at timing t 18  ((O) in  FIG. 4 ). Accordingly, in a period from timing t 16  to timing t 18 , the serializer  21 C selects the signal DI 13  (the data “D 3 ( n )”) and outputs it as the signals S 21 CP and S 21 CN ((R) in  FIG. 4 ). The clock signal P 5  makes a transition from low level to high level at timing t 18 , and makes a transition from high level to low level at timing t 20  ((P) in  FIG. 4 ). Accordingly, in a period from timing t 18  to timing t 20 , the serializer  21 C selects the signal DI 15  (the data “D 5 ( n )”) and outputs it as the signals S 21 CP and S 21 CN ((R) in  FIG. 4 ). The clock signal P 7  makes a transition from low level to high level at timing t 20 , and makes a transition from high level to low level at timing t 22  ((Q) in  FIG. 4 ). Accordingly, in a period from timing t 20  to timing t 22 , the serializer  21 C selects the signal DI 17  (the data “D 7 ( n )”) and outputs it as the signals S 21 CP and S 21 CN ((R) in  FIG. 4 ). 
     In this way, the serializer  21 A serializes the signals DI 10 , DI 12 , DI 14 , and DI 16 , thereby outputting the data “D 0 ( n )”, “D 2 ( n )”, “D 4 ( n )”, and “D 6 ( n )” in this order ((I) in  FIG. 4 ), and the serializer  21 C serializes the signals DI 11 , DI 13 , DI 15 , and DI 17 , thereby outputting the data “D 1 ( n )”, “D 3 ( n )”, “D 5 ( n )”, and “D 7 ( n )” in this order ((R) in  FIG. 4 ). Likewise, the serializer  21 B serializes the signals DI 20 , DI 22 , DI 24 , and DI 26 , and the serializer  21 D serializes the signals DI 21 , DI 23 , DI 25 , and DI 27 . 
     In the operation mode MB (differential mode), because of an emphasis operation, data indicated by the signals DI 20  to DI 27  is set to be shifted by one bit from data indicated by the signals DI 10  to DI 17  as described below. 
     In  FIG. 5 , (A) to (I) illustrate an operation example of the serializer  21 B in the operation mode MB; (J) to (R) in  FIG. 5  illustrate an operation example of the serializer  21 D in the operation mode MB. 
     In this example, at timing t 11 , the signal DI 20  is set to data “D 7 ( n −1)”, and the signal DI 22  is set to data “D 1 ( n )” ((A) and (B) in  FIG. 5 ). The data “D 7 ( n −1)” here is included in data “D 0 ( n −1)” to “D 7 ( n −1)” that is one before data “D 0 ( n )” to “D 7 ( n )”. Furthermore, at timing t 12 , the signal DI 21  is set to data “D 0 ( n )”, and the signal DI 23  is set to data “D 2 ( n )” ((J) and (K) in  FIG. 5 ). At timing t 15 , the signal DI 24  is set to data “D 3 ( n )”, and the signal DI 26  is set to data “D 5 ( n )” ((C) and (D) in  FIG. 5 ). At timing t 16 , the signal DI 25  is set to data “D 4 ( n )”, and the signal DI 27  is set to data “D 6 ( n )” ((L) and (M) in  FIG. 5 ). 
     Accordingly, the serializer  21 B serializes the signals DI 20 , DI 22 , DI 24 , and DI 26 , thereby outputting the data “D 7 ( n −1)”, “D 1 ( n )”, “D 3 ( n )”, and “D 5 ( n )” in this order ((I) in  FIG. 5 ), and the serializer  21 D serializes the signals DI 21 , DI 23 , DI 25 , and DI 27 , thereby outputting the data “D 0 ( n )”, “D 2 ( n )”, “D 4 ( n )”, and “D 6 ( n )” in this order ((R) in  FIG. 5 ). 
     The multiplexer  22 A ( FIG. 2 ) alternately selects one of the signals S 21 AP and S 21 CP on the basis of a clock signal CLK, and outputs the selected signal as a signal S 22 A. The multiplexer  22 B alternately selects one of the signals S 21 AN and S 21 CN on the basis of a clock signal CLK, and outputs the selected signal as a signal S 22 B. The multiplexer  22 C alternately selects one of the signals S 21 BP and S 21 DP on the basis of a clock signal CLK, and outputs the selected signal as a signal S 22 C. The multiplexer  22 D alternately selects one of the signals S 21 BN and S 21 DN on the basis of a clock signal CLK, and outputs the selected signal as a signal S 22 D. 
       FIG. 6  illustrates an operation example of the multiplexer  22 A; (A) illustrates a waveform of the signal S 21 AP, (B) illustrates a waveform of the signal S 21 CP, (C) illustrates a waveform of the clock signal CLK, and (D) illustrates a waveform of the signal S 22 A. 
     The signal S 21 AP is set to data “D 0 ( n )” in a period from timing t 13  to timing t 15 , and is set to data “D 2 ( n )” in a period from timing t 15  to timing t 17 , and is set to data “D 4 ( n )” in a period from timing t 17  to timing t 19 , and then is set to data “D 6 ( n )” in a period from timing t 19  to timing t 21  ((A) in  FIG. 6 ). Furthermore, the signal S 21 CP is set to data “D 1 ( n )” in a period from timing t 14  to timing t 16 , and is set to data “D 3 ( n )” in a period from timing t 16  to timing t 18 , and is set to data “D 5 ( n )” in a period from timing t 18  to timing t 20 , and then is set to data “D 7 ( n )” in a period from timing t 20  to timing t 22  ((B) in  FIG. 6 ). 
     The multiplexer  22 A selects the signal S 21 AP in a period in which the clock signal CLK is high level, and selects the signal S 21 CP in a period in which the clock signal CLK is low level. Specifically, the multiplexer  22 A selects the signal S 21 AP (the data “D 0 ( n )”) in a period from timing t 31  to timing t 32 , and selects the signal S 21 CP (the data “D 1 ( n )”) in a period from timing t 32  to timing t 33 , and selects the signal S 21 AP (the data “D 2 ( n )”) in a period from timing t 33  to timing t 34 , and selects the signal S 21 CP (the data “D 3 ( n )”) in a period from timing t 34  to timing t 35 , and selects the signal S 21 AP (the data “D 4 ( n )”) in a period from timing t 35  to timing t 36 , and selects the signal S 21 CP (the data “D 5 ( n )”) in a period from timing t 36  to timing t 37 , and selects the signal S 21 AP (the data “D 6 ( n )”) in a period from timing t 37  to timing t 38 , and then selects the signal S 21 CP (the data “D 7 ( n )”) in a period from timing t 38  to timing t 39 . Accordingly, the multiplexer  22 A outputs the data “D 0 ( n )”, “D 1 ( n )”, “D 2 ( n )”, “D 3 ( n )”, “D 4 ( n )”, “D 5 ( n )”, “D 6 ( n )”, and “D 7 ( n )” in this order as illustrated in (D) in  FIG. 6 . 
     In this way, the multiplexer  22 A selects the signal S 21 AP in a period in which the clock signal CLK is high level, and selects the signal S 21 CP in a period in which the clock signal CLK is low level. Furthermore, the multiplexer  22 B selects the signal S 21 AN in a period in which the clock signal CLK is high level, and selects the signal S 21 CN in a period in which the clock signal CLK is low level. As described above, the signals S 21 AP and S 21 AN are signals that are inverted from each other, and the signals S 21 CP and S 21 CN are signals that are inverted from each other, and therefore, the output signal S 22 A of the multiplexer  22 A and the output signal S 22 B of the multiplexer  22 B are signals that are inverted from each other. 
     Likewise, the multiplexer  22 C selects the signal S 21 BP in a period in which the clock signal CLK is high level, and selects the signal S 21 DP in a period in which the clock signal CLK is low level. Furthermore, the multiplexer  22 D selects the signal S 21 BN in a period in which the clock signal CLK is high level, and selects the signal S 21 DN in a period in which the clock signal CLK is low level. As described above, the signals S 21 BP and S 21 BN are signals that are inverted from each other, and the signals S 21 DP and S 21 DN are signals that are inverted from each other, and therefore, the output signal S 22 C of the multiplexer  22 C and the output signal S 22 D of the multiplexer  22 D are signals that are inverted from each other. 
       FIG. 7  illustrates an operation example of the multiplexers  22 A and  22 C in the operation mode MB; (A) illustrates a waveform of the signal S 21 AP, (B) illustrates a waveform of the signal S 21 CP, (C) illustrates a waveform of the signal S 21 BP, (D) illustrates a waveform of the signal S 21 DP, (E) illustrates a waveform of the clock signal CLK, (F) illustrates a waveform of the signal S 22 A, and (G) illustrates a waveform of the signal S 22 C. The operation of the multiplexer  22 A is the same as in the case of  FIG. 6 . 
     The signal S 21 BP is set to data “D 7 ( n −1)” in a period from timing t 13  to timing t 15 , and is set to data “D 1 ( n )” in a period from timing t 15  to timing t 17 , and is set to data “D 3 ( n )” in a period from timing t 17  to timing t 19 , and then is set to data “D 5 ( n )” in a period from timing t 19  to timing t 21  ((C) in  FIG. 7 ). Furthermore, the signal S 21 DP is set to data “D 0 ( n )” in a period from timing t 14  to timing t 16 , and is set to data “D 2 ( n )” in a period from timing t 16  to timing t 18 , and is set to data “D 4 ( n )” in a period from timing t 18  to timing t 20 , and then is set to data “D 6 ( n )” in a period from timing t 20  to timing t 22  ((D) in  FIG. 7 ). 
     The multiplexer  22 C selects the signal S 21 BP in a period in which the clock signal CLK is high level, and selects the signal S 21 DP in a period in which the clock signal CLK is low level. Accordingly, the multiplexer  22 C outputs the data “D 7 ( n −1)”, “D 0 ( n )”, “D 1 ( n )”, “D 2 ( n )”, “D 3 ( n )”, “D 4 ( n )”, “D 5 ( n )”, and “D 6 ( n )” in this order as illustrated in (G) in  FIG. 7 . 
     On the basis of a signal Ssel, the selector  23 A ( FIG. 2 ) selects the signal S 22 A in a case where the operation mode is the operation mode MA (single-phase mode) or the signal S 22 D in a case where the operation mode is the operation mode MB (differential mode), and outputs the selected signal as a signal S 23 A. On the basis of a signal Ssel, the selector  23 B selects the signal S 22 B in a case where the operation mode is the operation mode MA or the signal S 22 C in a case where the operation mode is the operation mode MB, and outputs the selected signal as a signal S 23 B. On the basis of a signal Ssel, the selector  23 C selects the signal S 22 C in a case where the operation mode is the operation mode MA or the signal S 22 B in a case where the operation mode is the operation mode MB, and outputs the selected signal as a signal S 23 C. On the basis of a signal Ssel, the selector  23 D selects the signal S 22 D in a case where the operation mode is the operation mode MA or the signal S 22 A in a case where the operation mode is the operation mode MB, and outputs the selected signal as a signal S 23 D. 
     The driver  24 A sets a voltage at the output terminal Tout 1  on the basis of the signals S 22 A, S 22 B, S 23 A, and S 23 B and a signal CTL. The driver  24 B sets a voltage at the output terminal Tout 2  on the basis of the signals S 23 C, S 23 D, S 22 C, and S 22 D and a signal CTL. 
       FIG. 8  illustrates a configuration example of the drivers  24 A and  24 B. It is to be noted that the selectors  23 A to  23 D are also depicted in this  FIG. 8 . The driver  24 A includes M sub-drivers AA (sub-drivers AA 1  to AAM) and N sub-drivers AB (sub-drivers AB 1  to ABN). The driver  24 B includes M sub-drivers BA (sub-drivers BA 1  to BAM) and N sub-drivers BB (sub-drivers BB 1  to BBN). The numbers “M” and “N” are configured to be able to be changed by the signal CTL. 
     The sub-drivers AA 1  to AAM, AB 1  to ABN, BA 1  to BAM, and BB 1  to BBN each include resistance elements  91  and  94  and transistors  92  and  93 . The transistors  92  and  93  are N-channel MOS type FETs. It is to be noted that in  FIG. 2 , these transistors  92  and  93  are depicted in the drivers  24 A and  24 B. Furthermore, in  FIG. 2 , an illustration of the resistance elements  91  and  94  is omitted. 
     In the following, the driver  24 A is described as an example. In each of the sub-drivers AA 1  to AAM of the driver  24 A, one end of the resistance element  91  is supplied with a voltage V 1 , and the other end is coupled to a drain of the transistor  92 . A gate of the transistor  92  is supplied with the signal S 22 A, and the drain is coupled to the other end of the resistance element  91 , and a source is coupled to a drain of the transistor  93  and the output terminal Tout 1 . A gate of the transistor  93  is supplied with the signal S 22 B, and the drain is coupled to the source of the transistor  92  and the output terminal Tout 1 , and a source is coupled to one end of the resistance element  94 . The one end of the resistance element  94  is coupled to the source of the transistor  93 , and the other end is grounded. 
     In each of the sub-drivers AB 1  to ABN of the driver  24 A, one end of the resistance element  91  is supplied with the voltage V 1 , and the other end is coupled to the drain of the transistor  92 . The gate of the transistor  92  is supplied with the signal S 23 A, and the drain is coupled to the other end of the resistance element  91 , and the source is coupled to the drain of the transistor  93  and the output terminal Tout 1 . The gate of the transistor  93  is supplied with the signal S 23 B, and the drain is coupled to the source of the transistor  92  and the output terminal Tout 1 , and the source is coupled to one end of the resistance element  94 . The one end of the resistance element  94  is coupled to the source of the transistor  93 , and the other end is grounded. 
     In each of the sub-drivers AA 1  to AAM and AB 1  to ABN of the driver  24 A, the sum of a resistance value of the resistance element  91  and an on-state resistance value of the transistor  92  is “50×(M+N)” [Ω] in this example. Likewise, the sum of an on-state resistance value of the transistor  93  and a resistance value of the resistance element  94  is “50×(M+N)” [Ω] in this example. 
     The driver  24 A is described above as an example; however, the same applies to the driver  24 B. In each of the sub-drivers BA 1  to BAM of the driver  24 B, the gate of the transistor  92  is supplied with the signal S 23 C, and the drain is coupled to the other end of the resistance element  91 , and the source is coupled to the drain of the transistor  93  and the output terminal Tout 2 . The gate of the transistor  93  is supplied with the signal S 23 D, and the drain is coupled to the source of the transistor  92  and the output terminal Tout 2 , and the source is coupled to one end of the resistance element  94 . Furthermore, in each of the sub-drivers BB 1  to BBN, the gate of the transistor  92  is supplied with the signal S 22 C, and the drain is coupled to the other end of the resistance element  91 , and the source is coupled to the drain of the transistor  93  and the output terminal Tout 2 . The gate of the transistor  93  is supplied with the signal S 22 D, and the drain is coupled to the source of the transistor  92  and the output terminal Tout 2 , and the source is coupled to one end of the resistance element  94 . 
     With this configuration, for example, in a case where in the operation mode MA (single-phase mode), the signal S 22 A is set to high level, and the signal S 22 B is set to low level, the signal S 23 A becomes high level, and the signal S 23 B becomes low level. Therefore, the transistors  92  in the sub-drivers AA 1  to AAM and AB 1  to ABN of the driver  24 A go into on state, and the transistors  93  in the sub-drivers AA 1  to AAM and AB 1  to ABN go into off state. As a result, the driver  24 A is able to set the voltage at the output terminal Tout 1  to a high-level voltage VH and the output impedance to about 50[Ω]. 
     Furthermore, for example, in a case where in the operation mode MA, the signal S 22 B is set to high level, and the signal S 22 A is set to low level, the signal S 23 B becomes high level, and the signal S 23 A becomes low level. Therefore, the transistors  93  in the sub-drivers AA 1  to AAM and AB 1  to ABN of the driver  24 A go into on state, and the transistors  92  in the sub-drivers AA 1  to AAM and AB 1  to ABN go into off state. As a result, the driver  24 A is able to set the voltage at the output terminal Tout 1  to a low-level voltage VL and the output impedance to about 50[Ω]. 
     Moreover, for example, in a case where in the operation mode MB (differential mode), the signals S 22 A and S 22 D are both set to high level, and the signals S 22 B and S 22 C are both set to low level, the signals S 23 A and S 23 D both become high level, and the signals S 23 B and S 23 C both become low level. Therefore, in the driver  24 A, the transistors  92  in the sub-drivers AA 1  to AAM and AB 1  to ABN go into on state, and the transistors  93  in the sub-drivers AA 1  to AAM and AB 1  to ABN go into off state. As a result, the driver  24 A is able to set the voltage at the output terminal Tout 1  to the high-level voltage VH and the output impedance to about 50[Ω]. Likewise, in the driver  24 B, the transistors  93  in the sub-drivers BA 1  to BAM and BB 1  to BBN go into on state, and the transistors  92  in the sub-drivers BA 1  to BAM and BB 1  to BBN go into off state. As a result, the driver  24 B is able to set the voltage at the output terminal Tout 2  to the low-level voltage VL and the output impedance to about 50[Ω]. 
     Furthermore, for example, in a case where in the operation mode MB, the signals S 22 B and S 22 C are both set to high level, and the signals S 22 A and S 22 D are both set to low level, the signals S 23 B and S 23 C both become high level, and the signals S 23 A and S 23 D both become low level. Therefore, in the driver  24 A, the transistors  93  in the sub-drivers AA 1  to AAM and AB 1  to ABN go into on state, and the transistors  92  in the sub-drivers AA 1  to AAM and AB 1  to ABN go into off state. As a result, the driver  24 A is able to set the voltage at the output terminal Tout 1  to the low-level voltage VL and the output impedance to about 50[Ω]. Likewise, in the driver  24 B, the transistors  92  in the sub-drivers BA 1  to BAM and BB 1  to BBN go into on state, and the transistors  93  in the sub-drivers BA 1  to BAM and BB 1  to BBN go into off state. As a result, the driver  24 B is able to set the voltage at the output terminal Tout 2  to the high-level voltage VH and the output impedance to about 50[Ω]. 
     Moreover, for example, in a case where in the operation mode MB, the signals S 22 A and S 22 C are both set to high level, and the signals S 22 B and S 22 D are both set to low level, the signals S 23 B and S 23 D both become high level, and the signals S 23 A and S 23 C both become low level. Therefore, in the driver  24 A, the transistors  92  in the sub-drivers AA 1  to AAM and the transistors  93  in the sub-drivers AB 1  to ABN go into on state, and the transistors  93  in the sub-drivers AA 1  to AAM and the transistors  92  in the sub-drivers AB 1  to ABN go into off state. As a result, the driver  24 A is able to set the voltage at the output terminal Tout 1  to a voltage (VH−ΔV), which is lower by a voltage ΔV than the high-level voltage VH, and the output impedance to about 50[Ω]. Likewise, in the driver  24 B, the transistors  93  in the sub-drivers BA 1  to BAM and the transistors  92  in the sub-drivers BB 1  to BBN go into on state, and the transistors  92  in the sub-drivers BA 1  to BAM and the transistors  93  in the sub-drivers BB 1  to BBN go into off state. As a result, the driver  24 B is able to set the voltage at the output terminal Tout 2  to a voltage (VL+ΔV), which is higher by the voltage ΔV than the low-level voltage VL, and the output impedance to about 50[Ω]. 
     Furthermore, for example, in a case where in the operation mode MB, the signals S 22 B and S 22 D are both set to high level, and the signals S 22 A and S 22 C are both set to low level, the signals S 23 A and S 23 C both become high level, and the signals S 23 B and S 23 D both become low level. Therefore, in the driver  24 A, the transistors  93  in the sub-drivers AA 1  to AAM and the transistors  92  in the sub-drivers AB 1  to ABN go into on state, and the transistors  92  in the sub-drivers AA 1  to AAM and the transistors  93  in the sub-drivers AB 1  to ABN go into off state. As a result, the driver  24 A is able to set the voltage at the output terminal Tout 1  to the voltage (VL+ΔV), which is higher by the voltage ΔV than the low-level voltage VL, and the output impedance to about 50[Ω]. Likewise, in the driver  24 B, the transistors  92  in the sub-drivers BA 1  to BAM and the transistors  93  in the sub-drivers BB 1  to BBN go into on state, and the transistors  93  in the sub-drivers BA 1  to BAM and the transistors  92  in the sub-drivers BB 1  to BBN go into off state. As a result, the driver  24 B is able to set the voltage at the output terminal Tout 2  to the voltage (VH−ΔV), which is lower by the voltage ΔV than the high-level voltage VH, and the output impedance to about 50[Ω]. 
     This voltage ΔV varies depending on “M” and “N”. That is, for example, increasing “M” and reducing “N” make it possible to reduce the voltage ΔV. Furthermore, for example, reducing “M” and increasing “N” make it possible to increase the voltage ΔV. 
     The controller  25  ( FIG. 2 ) generates clock signals P 0  to P 7  and CLK and signals Ssel and CTL on the basis of a mode signal Smode supplied from the processor  11 . 
     (Receiving Device  30 ) 
     The receiving device  30  includes receivers  31  and  32  and a processor  33  as illustrated in  FIG. 1A . 
     The receiver  31  receives a signal SIG 1 , and the receiver  32  receives a signal SIG 2 . 
       FIG. 9  illustrates a configuration example of the receiver  31 . It is to be noted that the same applies to the receiver  32 . The receiver  31  includes a resistance element  36  and an amplifier  37 . 
     The resistance element  36  serves as a receiving-side terminating resistance in the communication system  1 A. One end of the resistance element  36  is supplied with a bias voltage Vbias, and the other end is coupled to the input terminal Tin 1  of the receiver  31  and an input terminal of the amplifier  37 . A resistance value of this resistance element  36  is about 50[Ω] in this example. 
     The input terminal of the amplifier  37  is coupled to the input terminal Tin 1  of the receiver  31  and the other end of the resistance element  36 . Further, the amplifier  37  supplies its output signal to the processor  33 . 
     The processor  33  performs a predetermined process on the basis of received results of the receivers  31  and  32 . 
     (Receiving Device  40 ) 
     The receiving device  40  includes a receiver  41  and a processor  42  as illustrated in  FIG. 1B . 
     The receiver  41  receives signals SIGP and SIGN. 
       FIG. 10  illustrates a configuration example of the receiver  41 . The receiver  41  includes a resistance element  46  and an amplifier  47 . 
     The resistance element  46  serves as a receiving-side terminating resistance in the communication system  1 B. One end of the resistance element  46  is coupled to the input terminal TinP of the receiver  41  and a positive input terminal of the amplifier  47 , and the other end is coupled to the input terminal TinN of the receiver  41  and a negative input terminal of the amplifier  47 . A resistance value of this resistance element  46  is about 100[Ω] in this example. 
     The positive input terminal of the amplifier  47  is coupled to the input terminal TinP of the receiver  41  and one end of the resistance element  46 , and the negative input terminal of the amplifier  47  is coupled to the input terminal TinN of the receiver  41  and the other end of the resistance element  46 . Further, the amplifier  47  supplies its output signal to the processor  42 . 
     The processor  42  performs a predetermined process on the basis of a received result of the receiver  41 . 
     Here, the driver  24 A corresponds to a specific example of a “first driver” in the present disclosure. The plurality of sub-drivers AA 1  to AAM correspond to a specific example of a “first sub-driver unit” in the present disclosure, and the plurality of sub-drivers AB 1  to ABN correspond to a specific example of a “second sub-driver unit” in the present disclosure. The driver  24 B corresponds to a specific example of a “second driver” in the present disclosure. The plurality of sub-drivers BA 1  to BAM correspond to a specific example of a “third sub-driver unit” in the present disclosure, and the plurality of sub-drivers BB 1  to BBN correspond to a specific example of a “fourth sub-driver unit” in the present disclosure. The plurality of selectors  23 A to  23 D correspond to a specific example of a “selector unit” in the present disclosure. The plurality of multiplexers  22 A to  22 D correspond to a specific example of a “multiplexer unit” in the present disclosure. The plurality of serializers  21 A to  21 D correspond to a specific example of a “serializer unit” in the present disclosure. The operation mode MA corresponds to a specific example of a “first operation mode” in the present disclosure, and the operation mode MB corresponds to a specific example of a “second operation mode” in the present disclosure. 
     [Operation and Working] 
     Subsequently, the operation and working of each of the communication systems  1 A and  1 B in the present embodiment are described. 
     (Outline of Overall Operation) 
     First, an outline of the overall operation of each of the communication systems  1 A and  1 B is described with reference to  FIGS. 1A and 1B . The processor  11  of the transmitting device  10  generates data to be transmitted by performing a predetermined process, and selects one of the two operation modes MA and MB and generates a mode signal Smode on the basis of the selected operation mode. Specifically, in a case where the transmitting device  10  is applied to the communication system  1 A, the processor  11  selects the operation mode MA (single-phase mode), and instructs the transmitter  12  to perform the operation in the operation mode MA by using a mode signal Smode. Furthermore, in a case where the transmitting device  10  is applied to the communication system  1 B, the transmitter  12  selects the operation mode MB (differential mode), and instructs the transmitter  12  to perform the operation in the operation mode MB by using a mode signal Smode. In a case where the operation mode indicated by the mode signal Smode is the operation mode MA, the transmitter  12  transmits the data generated by the processor  11  by using signals SIG 1  and SIG 2 . Furthermore, in a case where the operation mode indicated by the mode signal Smode is the operation mode MB, the transmitter  12  transmits the data generated by the processor  11  by using signals SIGP and SIGN. 
     In the communication system  1 A, the receiver  31  of the receiving device  30  receives a signal SIG 1 , and the receiver  32  receives a signal SIG 2 . The processor  33  performs a predetermined process on the basis of received results of the receivers  31  and  32 . 
     In the communication system  1 B, the receiver  41  of the receiving device  40  receives signals SIGP and SIGN. The processor  42  performs a predetermined process on the basis of a received result of the receiver  41 . 
     (Operation Mode MA) 
     In a case where the transmitting device  10  is applied to the communication system  1 A ( FIG. 1A ), the transmitting device  10  operates in the operation mode MA (single-phase mode). In the operation mode MA, the transmitting device  10  transmits data to the receiving device  30  by using signals SIG 1  and SIG 2 . Detailed operation in the operation mode MA is described below. 
       FIG. 11  illustrates the flow of signals in the operation mode MA. In  FIG. 11 , bold solid lines indicate the flow of signals related to signals DI 10  to DI 17 , and bold dashed lines indicate the flow of signals related to signals DI 20  to DI 27 . The transmitter  12  generates a signal SIG 1  on the basis of the signals DI 10  to DI 17 , and generates a signal SIG 2  on the basis of the signals DI 20  to DI 27 . This operation is described in detail below. 
     First, the flow of signals related to signals DI 10  to DI 17  is described. The processor  11  generates signals DI 10  to DI 17 . Here, for example, the signal DI 10  includes signals DI 10 P and DI 10 N. Further, the processor  11  supplies, of the signals DI 10  to DI 17 , the signals DI 10 , DI 12 , DI 14 , and DI 16  to the serializer  21 A and the signals DI 11 , DI 13 , DI 15 , and DI 17  to the serializer  21 C. 
     As illustrated in (A) to (I) of  FIG. 4 , the serializer  21 A serializes the signals DI 10 , DI 12 , DI 14 , and DI 16 , thereby generating signals S 21 AP and S 21 AN. Furthermore, as illustrated in (J) to (R) of  FIG. 4 , the serializer  21 C serializes the signals DI 11 , DI 13 , DI 15 , and DI 17 , thereby generating signals S 21 CP and S 21 CN. 
     As illustrated in  FIG. 6 , the multiplexer  22 A alternately selects one of the signals S 21 AP and S 21 CP on the basis of a clock signal CLK, and outputs the selected signal as a signal S 22 A. Likewise, the multiplexer  22 B alternately selects one of the signals S 21 AN and S 21 CN on the basis of a clock signal CLK, and outputs the selected signal as a signal S 22 B. 
     In the operation mode MA, the selector  23 A selects the signal S 22 A on the basis of a signal Ssel, and outputs the signal S 22 A as a signal S 23 A. In the operation mode MA, the selector  23 B selects the signal S 22 B on the basis of a signal Ssel, and outputs the signal S 22 B as a signal S 23 B. As a result, the driver  24 A operates on the basis of the signals S 22 A and S 22 B. Specifically, the sub-drivers AA 1  to AAM of the driver  24 A operate on the basis of the signals S 22 A and S 22 B, and the sub-drivers AB 1  to ABN of the driver  24 A operate on the basis of the signals S 22 A and S 22 B. Then, the driver  24 A generates a signal SIG 1 . 
     Next, the flow of signals related to signals DI 20  to DI 27  is described. The processor  11  generates signals DI 20  to DI 27 . Here, for example, the signal DI 20  includes signals DI 20 P and DI 20 N. Further, the processor  11  supplies, of the signals DI 20  to DI 27 , the signals DI 20 , DI 22 , DI 24 , and DI 26  to the serializer  21 B and the signals DI 21 , DI 23 , DI 25 , and DI 27  to the serializer  21 D. 
     As with the case of the serializer  21 A ((A) to (I) of  FIG. 4 ), the serializer  21 B serializes the signals DI 20 , DI 22 , DI 24 , and DI 26 , thereby generating signals S 21 BP and S 21 BN. Furthermore, as with the case of the serializer  21 C ((J) to (R) of  FIG. 4 ), the serializer  21 D serializes the signals DI 21 , DI 23 , DI 25 , and DI 27 , thereby generating signals S 21 DP and S 21 DN. 
     As with the case of the multiplexer  22 A ( FIG. 6 ), the multiplexer  22 C selects one of the signals S 21 BP and S 21 DP on the basis of a clock signal CLK, and outputs the selected signal as a signal S 22 C. Likewise, the multiplexer  22 D selects one of the signals S 21 BN and S 21 DN on the basis of a clock signal CLK, and outputs the selected signal as a signal S 22 D. 
     In the operation mode MA, the selector  23 C selects the signal S 22 C on the basis of a signal Ssel, and outputs the signal S 22 C as a signal S 23 C. In the operation mode MA, the selector  23 D selects the signal S 22 D on the basis of a signal Ssel, and outputs the signal S 22 D as a signal S 23 D. As a result, the driver  24 B operates on the basis of the signals S 22 C and S 22 D. Specifically, the sub-drivers BA 1  to BAM of the driver  24 B operate on the basis of the signals S 22 C and S 22 D, and the sub-drivers BB 1  to BBN of the driver  24 B operate on the basis of the signals S 22 C and S 22 D. Then, the driver  24 B generates a signal SIG 2 . 
     In this way, in the operation mode MA, the driver  24 A generates the signal SIG 1  on the basis of the signals S 22 A and S 22 B, and the driver  24 B generates the signal SIG 2  on the basis of the signals S 23 C and S 23 D. 
       FIG. 12  illustrates an operation to generate the signal SIG 1 . In  FIG. 12 , a bold solid line indicates the flow of a signal related to the multiplexer  22 A, and a bold dashed line indicates the flow of a signal related to the multiplexer  22 B. It is to be noted that the same applies to an operation to generate the signal SIG 2 . 
     The output signals S 21 AP and S 21 AN of the serializer  21 A are signals that are inverted from each other, and the output signals S 21 CP and S 21 CN of the serializer  21 C are signals that are inverted from each other. Therefore, the output signal S 22 A of the multiplexer  22 A and the output signal S 22 B of the multiplexer  22 B are signals that are inverted from each other. 
     For example, in a case where the signal S 22 A is high level, and the signal S 22 B is low level, the signal S 23 A becomes high level, and the signal S 23 B becomes low level. In this case, in the driver  24 A, the transistors  92  in the sub-drivers AA 1  to AAM and AB 1  to ABN go into on state, and the transistors  93  in the sub-drivers AA 1  to AAM and AB 1  to ABN go into off state. As a result, the driver  24 A sets the voltage at the output terminal Tout 1  to the high-level voltage VH and the output impedance to about 50[Ω]. 
     Furthermore, for example, in a case where the signal S 22 B is high level, and the signal S 22 A is low level, the signal S 23 B becomes high level, and the signal S 23 A becomes low level. In this case, in the driver  24 A, the transistors  93  in the sub-drivers AA 1  to AAM and AB 1  to ABN go into on state, and the transistors  92  in the sub-drivers AA 1  to AAM and AB 1  to ABN go into off state. Therefore, the driver  24 A sets the voltage at the output terminal Tout 1  to the low-level voltage VL and the output impedance to about 50[Ω]. 
     In this way, in the operation mode MA, the transmitting device  10  transmits data to the receiving device  30  by using a single-phase signal. 
     (Operation Mode MB) 
     In a case where the transmitting device  10  is applied to the communication system  1 B ( FIG. 1B ), the transmitting device  10  operates in the operation mode MB (differential mode). In the operation mode MB, the transmitting device  10  transmits data to the receiving device  40  by using signals SIGP and SIGN. Detailed operation in the operation mode MB is described below. 
       FIG. 13  illustrates the flow of signals in the operation mode MB. In  FIG. 13 , bold solid lines indicate the flow of signals related to signals DI 10  to DI 17 , and bold dashed lines indicate the flow of signals related to signals DI 20  to DI 27 . The transmitter  12  generates signals SIGP and SIGN on the basis of the signals DI 10  to DI 17  and DI 20  to DI 27 . At this time, the transmitter  12  performs an emphasis operation on the basis of the signals DI 20  to DI 27 . This operation is described in detail below. 
     First, the flow of signals related to signals DI 10  to DI 17  is described. The processor  11  generates signals DI 10  to DI 17 , and supplies, of the signals DI 10  to DI 17 , the signals DI 10 , DI 12 , DI 14 , and DI 16  to the serializer  21 A and the signals DI 11 , DI 13 , DI 15 , and DI 17  to the serializer  21 C. The serializers  21 A and  21 C and the multiplexers  22 A and  22 B operate as with the case of the operation mode MA. 
     In the operation mode MB, the selector  23 C selects a signal S 22 B on the basis of a signal Ssel, and outputs the signal S 22 B as a signal S 23 C. In the operation mode MB, the selector  23 D selects a signal S 22 A on the basis of a signal Ssel, and outputs the signal S 22 A as a signal S 23 D. As a result, the sub-drivers AA 1  to AAM of the driver  24 A operate on the basis of the signals S 22 A and S 22 B, and the sub-drivers BA 1  to BAM of the driver  24 B operate on the basis of the signals S 22 B and S 22 A. 
     Next, the flow of signals related to signals DI 20  to DI 27  is described. The processor  11  generates signals DI 20  to DI 27 . In the operation mode MB, data indicated by these signals DI 20  to DI 27  is set to be shifted by one bit from data indicated by the signals DI 10  to DI 17 . Further, the processor  11  supplies, of the signals DI 20  to DI 27 , the signals DI 20 , DI 22 , DI 24 , and DI 26  to the serializer  21 B and the signals DI 21 , DI 23 , DI 25 , and DI 27  to the serializer  21 D. The serializers  21 B and  21 D and the multiplexers  22 C and  22 D operate as with the case of the operation mode MA. 
     In the operation mode MB, the selector  23 A selects a signal S 22 D on the basis of a signal Ssel, and outputs the signal S 22 D as a signal S 23 A. In the operation mode MB, the selector  23 B selects a signal S 22 C on the basis of a signal Ssel, and outputs the signal S 22 C as a signal S 23 B. As a result, the sub-drivers AB 1  to ABN of the driver  24 A operate on the basis of the signals S 22 D and S 22 C, and the sub-drivers BB 1  to BBN of the driver  24 B operate on the basis of the signals S 22 C and S 22 D. 
     In this way, the driver  24 A generates the signal SIGP on the basis of the signals S 22 A, S 22 B, S 22 C, and S 22 D. Furthermore, the driver  24 B generates the signal SIGN on the basis of the signals S 22 A, S 22 B, S 22 C, and S 22 D. 
       FIG. 14  illustrates the operation based on signals DI 10  to DI 17 . In  FIG. 14 , a bold solid line indicates the flow of a signal related to the multiplexer  22 A, and a bold dashed line indicates the flow of a signal related to the multiplexer  22 B. Also in the operation mode MB, the output signal S 22 A of the multiplexer  22 A and the output signal S 22 B of the multiplexer  22 B are signals that are inverted from each other. 
     For example, in a case where the signal S 22 A is high level, and the signal S 22 B is low level, the signal S 23 D becomes high level, and the signal S 23 C becomes low level. In this case, in the sub-drivers AA 1  to AAM of the driver  24 A, the transistors  92  go into on state, and the transistors  93  go into off state; in the sub-drivers BA 1  to BAM of the driver  24 B, the transistors  93  go into on state, and the transistors  92  go into off state. 
     Furthermore, for example, in a case where the signal S 22 B is high level, and the signal S 22 A is low level, the signal S 23 C becomes high level, and the signal S 23 D becomes low level. In this case, in the sub-drivers AA 1  to AAM of the driver  24 A, the transistors  93  go into on state, and the transistors  92  go into off state; in the sub-drivers BA 1  to BAM of the driver  24 B, the transistors  92  go into on state, and the transistors  93  go into off state. 
       FIG. 15  illustrates the operation based on signals DI 20  to DI 27 . In  FIG. 15 , a bold solid line indicates the flow of a signal related to the multiplexer  22 C, and a bold dashed line indicates the flow of a signal related to the multiplexer  22 D. The output signal S 22 C of the multiplexer  22 C and the output signal S 22 D of the multiplexer  22 D are signals that are inverted from each other. 
     For example, in a case where the signal S 22 C is high level, and the signal S 22 D is low level, the signal S 23 B becomes high level, and the signal S 23 A becomes low level. In this case, in the sub-drivers AB 1  to ABM of the driver  24 A, the transistors  93  go into on state, and the transistors  92  go into off state; in the sub-drivers BB 1  to BBM of the driver  24 B, the transistors  92  go into on state, and the transistors  93  go into off state. 
     Furthermore, for example, in a case where the signal S 22 D is high level, and the signal S 22 C is low level, the signal S 23 A becomes high level, and the signal S 23 B becomes low level. In this case, in the sub-drivers AB 1  to ABM of the driver  24 A, the transistors  92  go into on state, and the transistors  93  go into off state; in the sub-drivers BB 1  to BBM of the driver  24 B, the transistors  93  go into on state, and the transistors  92  go into off state. 
     In the transmitting device  10 , the number “M” of sub-drivers AA is larger than the number “N” of sub-drivers AB in the driver  24 A; and the number “M” of sub-drivers BA is larger than the number “N” of sub-drivers BB in the driver  24 B. This makes it possible for an influence of the signals S 22 A and S 22 B on the signals SIGP and SIGN to be larger than an influence of the signals S 22 C and S 22 D on the signals SIGP and SIGN. Using this, the transmitting device  10  performs an emphasis operation as follows. 
       FIG. 16  illustrates an emphasis operation in the transmitter  12 ; (A) illustrates a waveform of the clock signal CLK, (B) illustrates a waveform of the signal S 22 A, (C) illustrates a waveform of the signal S 22 B, (D) illustrates a waveform of the signal S 22 C, (E) illustrates a waveform of the signal S 22 D, and (F) illustrates a waveform of the signal SIGP−the signal SIGN. 
     In this example, in a period from timing t 41  to timing t 42 , the signals S 22 A and S 22 D are set to high level, and the signals S 22 B and S 22 C are set to low level. In this case, in the driver  24 A, in the sub-drivers AA 1  to AAM and AB 1  to ABN, the transistors  92  go into on state, and the transistors  93  go into off state. Therefore, the driver  24 A sets the voltage at the output terminal Tout 1  to the high-level voltage VH and the output impedance to about 50[Ω]. Furthermore, in the driver  24 B, in the sub-drivers BA 1  to BAM and BB 1  to BBN, the transistors  93  go into on state, and the transistors  92  go into off state. Therefore, the driver  24 B sets the voltage at the output terminal Tout 2  to the low-level voltage VL and the output impedance to about 50[Ω]. As a result, the signal SIGP−the signal SIGN becomes the high-level voltage VH−the low-level voltage VL (VH−VL) as illustrated in (F) of  FIG. 16 . 
     Furthermore, in a period from timing t 42  to timing t 44 , the signals S 22 A and S 22 C are set to high level, and the signals S 22 B and S 22 D are set to low level. In this case, in the driver  24 A, the transistors  92  in the sub-drivers AA 1  to AAM and the transistors  93  in the sub-drivers AB 1  to ABN go into on state, and the transistors  93  in the sub-drivers AA 1  to AAM and the transistors  92  in the sub-drivers AB 1  to ABN go into off state. Therefore, the driver  24 A sets the voltage at the output terminal Tout 1  to a voltage that is lower by a voltage ΔV than the high-level voltage VH, and sets the output impedance to about 50[Ω]. Furthermore, in the driver  24 B, the transistors  93  in the sub-drivers BA 1  to BAM and the transistors  92  in the sub-drivers BB 1  to BBN go into on state, and the transistors  92  in the sub-drivers BA 1  to BAM and the transistors  93  in the sub-drivers BB 1  to BBN go into off state. Therefore, the driver  24 B sets the voltage at the output terminal Tout 2  to a voltage that is higher by the voltage ΔV than the low-level voltage VL, and sets the output impedance to about 50[Ω]. As a result, the signal SIGP−the signal SIGN becomes a voltage (VH−VL−2ΔV) that is lower by a voltage  2 ΔV than the high-level voltage VH−the low-level voltage VL (VH−VL) as illustrated in (F) of  FIG. 16 . 
     Moreover, in a period from timing t 44  to timing t 45 , the signals S 22 B and S 22 C are set to high level, and the signals S 22 A and S 22 D are set to low level. In this case, in the driver  24 A, in the sub-drivers AA 1  to AAM and AB 1  to ABN, the transistors  93  go into on state, and the transistors  92  go into off state. Therefore, the driver  24 A sets the voltage at the output terminal Tout 1  to the low-level voltage VL and the output impedance to about 50[Ω]. Furthermore, in the driver  24 B, in the sub-drivers BA 1  to BAM and BB 1  to BBN, the transistors  92  go into on state, and the transistors  93  go into off state; therefore, the driver  24 B sets the voltage at the output terminal Tout 2  to the high-level voltage VH and the output impedance to about 50[Ω]. As a result, the signal SIGP−the signal SIGN becomes the low-level voltage VL−the high-level voltage VH (VL−VH) as illustrated in (F) of  FIG. 16 . 
     Furthermore, the operation in a period from timing t 45  to timing t 46  is the same as the operation in a period from timing t 41  to timing t 42 . As a result, the signal SIGP−the signal SIGN becomes the high-level voltage VH−the low-level voltage VL (VH−VL) as illustrated in (F) of  FIG. 16 . 
     Moreover, the operation in a period from timing t 46  to timing t 47  is the same as the operation in a period from timing t 44  to timing t 45 . As a result, the signal SIGP−the signal SIGN becomes the low-level voltage VL−the high-level voltage VH (VL−VH) as illustrated in (F) of  FIG. 16 . 
     Furthermore, in a period from timing t 47  to timing t 49 , the signals S 22 B and S 22 D are set to high level, and the signals S 22 A and S 22 C are set to low level. In this case, in the driver  24 A, the transistors  93  in the sub-drivers AA 1  to AAM and the transistors  92  in the sub-drivers AB 1  to ABN go into on state, and the transistors  92  in the sub-drivers AA 1  to AAM and the transistors  93  in the sub-drivers AB 1  to ABN go into off state. Therefore, the driver  24 A sets the voltage at the output terminal Tout 1  to the voltage that is higher by the voltage ΔV than the low-level voltage VL, and sets the output impedance to about 50[Ω]. Furthermore, in the driver  24 B, the transistors  92  in the sub-drivers BA 1  to BAM and the transistors  93  in the sub-drivers BB 1  to BBN go into on state, and the transistors  93  in the sub-drivers BA 1  to BAM and the transistors  92  in the sub-drivers BB 1  to BBN go into off state. Therefore, the driver  24 B sets the voltage at the output terminal Tout 2  to the voltage that is lower by the voltage ΔV than the high-level voltage VH, and sets the output impedance to about 50 [Ω]. As a result, the signal SIGP−the signal SIGN becomes a voltage (VL−VH+2ΔV) that is higher by the voltage  2 ΔV than the low-level voltage VL−the high-level voltage VH (VL−VH) as illustrated in (F) of  FIG. 16 . 
     In this way, using a differential signal in the operation mode MB, the transmitting device  10  transmits data to the receiving device  40 . 
     As described above, the transmitting device  10  is provided with the two operation modes MA and MB so as to be able to transmit data to a receiving device by using a single-phase signal or a differential signal; therefore, it is possible to implement various interfaces. 
     Accordingly, it is possible to increase the degree of freedom in, for example, system design of an electronic apparatus. Specifically, for example, in a case where this transmitting device  10  is installed in a processor, an electronic apparatus is able to include a peripheral device corresponding to a single-phase signal, or is able to include a peripheral device corresponding to a differential signal. Furthermore, for example, one processor makes it possible to implement various interfaces, and therefore, it is not necessary to prepare a processor for each interface. Therefore, it is possible to narrow down the number of varieties of processors and reduce the cost. Moreover, the four serializers  21 , the four multiplexers  22 , the four selectors  23 , and the two drivers  24  are shared in the operation modes MA and MB; therefore, it is possible to suppress the area necessary for circuit layout as compared with a case where separate circuits are provided for respective interfaces. 
     Furthermore, in a case where the transmitting device  10  is applied to the communication system  1 B, the transmitting device  10  is configured to perform an emphasis operation; therefore, for example, in a case where the lines  111  and  112  are long, it is possible to increase the communication performance. 
     Subsequently, working of the present embodiment is described by comparison with some comparative examples. 
     (Comparative Example R) 
       FIG. 17  illustrates a configuration example of a main part of a transmitter  12 R in a transmitting device  10 R according to Comparative example R. The transmitter  12 R includes serializers  21 RA and  21 RB, a selector  23 R, multiplexers  22 RA and  22 RB, and drivers  24 RA and  24 RB. The serializer  21 RA serializes signals DI 10  to DI 17 , thereby generating signals S 21 RAP and S 21 RAN. The signals S 21 RAP and S 21 RAN are signals that are inverted from each other. The serializer  21 RB serializes signals DI 20  to DI 27 , thereby generating signals S 21 RBP and S 21 RBN. The signals S 21 RBP and S 21 RBN are signals that are inverted from each other. On the basis of a signal Ssel, the selector  23 R selects the signal S 21 RBP in a case where the operation mode is the operation mode MA (single-phase mode), and selects the signal S 21 RBN in a case where the operation mode is the operation mode MB (differential mode), and then outputs the selected signal as a signal S 23 R. The multiplexer  22 RA selects one of the signals S 21 RAP and S 21 RBP on the basis of a clock signal CLK, and outputs the selected signal. The multiplexer  22 RB selects one of the signals S 21 RAN and S 23 R on the basis of a clock signal CLK, and outputs the selected signal. The driver  24 RA sets a voltage at the output terminal Tout 1  on the basis of the output signal of the multiplexer  22 RA. The driver  24 RB sets a voltage at the output terminal Tout 2  on the basis of the output signal of the multiplexer  22 RB. 
       FIG. 18  illustrates an operation example of the flow of signals in the operation mode MA (single-phase mode). In  FIG. 18 , a bold solid line indicates the flow of a signal related to a signal SIG 1 , and a bold dashed line indicates the flow of a signal related to a signal SIG 2 . In the operation mode MA, the selector  23 R selects a signal S 21 RBP on the basis of a signal Ssel, and outputs the signal S 21 RBP as a signal S 23 R. In the operation mode MA, a clock signal CLK is stopped. Accordingly, the multiplexer  22 RA selects a signal S 21 RAP, and outputs the signal S 21 RAP. Furthermore, the multiplexer  22 RB selects the signal S 23 R, and outputs the signal S 23 R. The driver  24 RA generates a signal SIG 1  on the basis of the output signal of the multiplexer  22 RA, and the driver  24 RB generates a signal SIG 2  on the basis of the output signal of the multiplexer  22 RB. 
       FIG. 19  illustrates the flow of signals in the operation mode MB (differential mode). In  FIG. 19 , a bold solid line indicates the flow of a signal related to a signal SIGP, and a bold dashed line indicates the flow of a signal related to a signal SIGN. In the operation mode MB, the selector  23 R selects a signal S 21 RBN on the basis of a signal Ssel, and outputs the signal S 21 RBN as a signal S 23 R. In the operation mode MB, a clock signal CLK is toggled. Accordingly, the multiplexer  22 RA alternately selects one of signals S 21 RAP and S 21 RBP, and outputs the selected signal. Furthermore, the multiplexer  22 RB alternately selects one of signals S 21 RAN and S 23 R, and outputs the selected signal. The driver  24 RA generates a signal SIGP on the basis of the output signal of the multiplexer  22 RA, and the driver  24 RB generates a signal SIGN on the basis of the output signal of the multiplexer  22 RB. 
     In this way, in the transmitting device  10 R according to Comparative example R, a clock signal CLK is stopped in the operation mode MA (single-phase mode), and a clock signal CLK is toggled in the operation mode MB (differential mode). Accordingly, in the transmitting device  10 R, the data rate of signals SIG 1  and SIG 2  in the operation mode MA is reduced to half of the data rate of signals SIGP and SIGN in the operation mode MB. 
     On the other hand, in the transmitting device  10  according to the present embodiment, a clock signal CLK is toggled in both of the operation modes MA and MB. Accordingly, in the transmitting device  10 , it is possible to cause the data rate of signals SIG 1  and SIG 2  in the operation mode MA to be the same as the data rate of signals SIGP and SIGN in the operation mode MB, and therefore, it is possible to suppress reduction of the data rate in the operation mode MA. 
     (Comparative Example S) 
       FIG. 20  illustrates a configuration example of a main part of a transmitter  12 S in a transmitting device  10 S according to Comparative example S. The transmitter  12 S includes serializers  21 SA and  21 SB and a selector  23 S. The serializer  21 SA serializes signals DI 10  to DI 17 , thereby generating signals S 21 SAP and S 21 SAN. The signals S 21 SAP and S 21 SAN are signals that are inverted from each other. The serializer  21 SB serializes signals DI 20  to DI 27 , thereby generating a signal S 21 SBP. On the basis of a signal Ssel, the selector  23 S selects the signal S 21 SBP in a case where the operation mode is the operation mode MA (single-phase mode), and selects the signal S 21 SAN in a case where the operation mode is the operation mode MB (differential mode), and then outputs the selected signal. 
       FIG. 21  illustrates the flow of signals in the operation mode MA (single-phase mode). In  FIG. 21 , a bold solid line indicates the flow of a signal related to a signal SIG 1 , and a bold dashed line indicates the flow of a signal related to a signal SIG 2 . In the operation mode MA, the selector  23 S selects a signal S 21 SBP on the basis of a signal Ssel, and outputs the signal S 21 SBP. The driver  24 RA generates a signal SIG 1  on the basis of a signal S 21 SAP, and the driver  24 RB generates a signal SIG 2  on the basis of the output signal of the selector  23 S. 
       FIG. 22  illustrates the flow of signals in the operation mode MB (differential mode). In  FIG. 22 , a bold solid line indicates the flow of a signal related to a signal SIGP, and a bold dashed line indicates the flow of a signal related to a signal SIGN. In the operation mode MB, the selector  23 S selects a signal S 21 SAN on the basis of a signal Ssel, and outputs the signal S 21 SAN. The driver  24 RA generates a signal SIGP on the basis of a signal S 21 SAP, and the driver  24 RB generates a signal SIGN on the basis of the output signal of the selector  23 S. 
     In this way, in the transmitting device  10 S according to Comparative example S, despite the fact that the serializer  21 SB is provided, the serializer  21 SB is not put into operation in the operation mode MB; therefore, in a case where the transmitting device  10 S is applied to the communication system  1 B, the serializer  21 SB is useless. Furthermore, in the transmitting device  10 S, no multiplexers are provided in the subsequent stage of the serializers  21 SA and  21 SB; therefore, the data rate is reduced. 
     On the other hand, in the transmitting device  10  according to the present embodiment, all the four serializers  21  are put into operation in both of the operation modes MA and MB; therefore, it is possible to make efficient use of circuits. Furthermore, in the transmitting device  10 , the four multiplexers  22  are provided in the subsequent stage of the four serializers  21 ; therefore, it is possible to increase the data rate. 
     [Effects] 
     As described above, in the present embodiment, the two operation modes MA and MB are provided, which makes it possible to transmit data to a receiving device by using a single-phase signal or a differential signal; therefore, it is possible to implement various interfaces. 
     In the present embodiment, an emphasis operation is performed in the operation mode MB; therefore, it is possible to increase the communication performance. 
     Modification Example 1-1 
     In the above-described embodiment, the four serializers  21  are configured as illustrated in  FIG. 3 ; however, it is not limited to this. A modification example is described in detail below. 
       FIG. 23  illustrates a configuration example of a serializer  121 A according to the present modification example. This serializer  121 A corresponds to the serializer  21 A according to the above-described embodiment. The serializer  121 A serializes signals DI 10 , DI 12 , DI 14 , and DI 16  on the basis of clock signals P 0 , P 2 , P 4 , and P 6 , thereby generating signals S 21 AP and S 21 AN. This serializer  121 A includes inverters IV 1  to IV 6  and clocked inverters CIV 1  to CIV 4 . 
     The inverter IV 1  generates an inverted clock signal P 0 B by inverting the clock signal P 0 . The inverter IV 2  generates an inverted clock signal P 2 B by inverting the clock signal P 2 . The inverter IV 3  generates an inverted clock signal P 4 B by inverting the clock signal P 4 . The inverter IV 4  generates an inverted clock signal P 6 B by inverting the clock signal P 6 . 
     The clocked inverter CIV 1  applies an inverted signal of the signal DI 10  to a node N 1  in a case where the clock signal P 0  is high level, and the inverted clock signal P 0 B is low level; and the clocked inverter CIV 1  sets the output impedance to high impedance in a case where the clock signal P 0  is low level, and the inverted clock signal P 0 B is high level. The clocked inverter CIV 2  applies an inverted signal of the signal DI 12  to the node N 1  in a case where the clock signal P 2  is high level, and the inverted clock signal P 2 B is low level; and the clocked inverter CIV 2  sets the output impedance to high impedance in a case where the clock signal P 2  is low level, and the inverted clock signal P 2 B is high level. The clocked inverter CIV 3  applies an inverted signal of the signal DI 14  to the node N 1  in a case where the clock signal P 4  is high level, and the inverted clock signal P 4 B is low level; and the clocked inverter CIV 3  sets the output impedance to high impedance in a case where the clock signal P 4  is low level, and the inverted clock signal P 4 B is high level. The clocked inverter CIV 4  applies an inverted signal of the signal DI 16  to the node N 1  in a case where the clock signal P 6  is high level, and the inverted clock signal P 6 B is low level; and the clocked inverter CIV 4  sets the output impedance to high impedance in a case where the clock signal P 6  is low level, and the inverted clock signal P 6 B is high level. 
     The inverter IV 5  inverts the voltage at the node N 1 , thereby generating a signal S 21 AP. The inverter IV 6  inverts the signal S 21 AP, thereby generating a signal S 2  IAN. 
     This serializer  121 A is able to operate in the same manner as the serializer  21 A according to the above-described embodiment ((A) to (I) in  FIG. 4 ). 
       FIG. 24  illustrates a configuration example of another serializer  122 A according to the present modification example. This serializer  122 A corresponds to the serializer  21 A according to the above-described embodiment. This serializer  122 A serializes signals DI 10 , DI 12 , DI 14 , and DI 16  on the basis of clock signals P 10 , P 12 , P 14 , and P 16 , thereby generating signals S 21 AP and S 21 AN. The clock signals P 10 , P 12 , P 14 , and P 16  are a so-called four-phase clock. The serializer  122 A includes transistors M 21  to M 48 . The transistors M 21  to M 46  are N-channel MOS type FETs, and the transistors M 47  and M 48  are P-channel MOS type FETs. 
     A source of the transistor M 21  is grounded, and a gate is supplied with a signal DI 10 P, and a drain is coupled to a source of the transistor M 23 . A source of the transistor M 22  is grounded, and a gate is supplied with a signal DI 10 N, and a drain is coupled to a source of the transistor M 24 . The source of the transistor M 23  is coupled to the drain of the transistor M 21 , a gate is supplied with the clock signal P 16 , and a drain is coupled to a source of the transistor M 25 . The source of the transistor M 24  is coupled to the drain of the transistor M 22 , a gate is supplied with the clock signal P 16 , and a drain is coupled to a source of the transistor M 26 . The source of the transistor M 25  is coupled to the drain of the transistor M 23 , a gate is supplied with the clock signal P 10 , and a drain is coupled to drains of the transistors M 31 , M 37 , and M 43  and a source of the transistor M 45 . The source of the transistor M 26  is coupled to the drain of the transistor M 24 , a gate is supplied with the clock signal P 10 , and a drain is coupled to drains of the transistors M 32 , M 38 , and M 44  and a source of the transistor M 46 . 
     A source of the transistor M 27  is grounded, and a gate is supplied with a signal DI 12 P, and a drain is coupled to a source of the transistor M 29 . A source of the transistor M 28  is grounded, and a gate is supplied with a signal DI 12 N, and a drain is coupled to a source of the transistor M 30 . The source of the transistor M 29  is coupled to the drain of the transistor M 27 , a gate is supplied with the clock signal P 10 , and the drain is coupled to a source of the transistor M 31 . The source of the transistor M 30  is coupled to the drain of the transistor M 28 , a gate is supplied with the clock signal P 10 , and a drain is coupled to a source of the transistor M 32 . The source of the transistor M 31  is coupled to the drain of the transistor M 29 , a gate is supplied with the clock signal P 12 , and the drain is coupled to the drains of the transistors M 25 , M 37 , and M 43  and the source of the transistor M 45 . The source of the transistor M 32  is coupled to the drain of the transistor M 30 , a gate is supplied with the clock signal P 12 , and the drain is coupled to the drains of the transistors M 26 , M 38 , and M 44  and the source of the transistor M 46 . 
     A source of the transistor M 33  is grounded, and a gate is supplied with a signal DI 14 P, and a drain is coupled to a source of the transistor M 35 . A source of the transistor M 34  is grounded, and a gate is supplied with a signal DI 14 N, and a drain is coupled to a source of the transistor M 36 . The source of the transistor M 35  is coupled to the drain of the transistor M 33 , a gate is supplied with the clock signal P 12 , and the drain is coupled to a source of the transistor M 37 . The source of the transistor M 36  is coupled to the drain of the transistor M 34 , a gate is supplied with the clock signal P 12 , and a drain is coupled to a source of the transistor M 38 . The source of the transistor M 37  is coupled to the drain of the transistor M 35 , a gate is supplied with the clock signal P 14 , and the drain is coupled to the drains of the transistors M 25 , M 31 , and M 43  and the source of the transistor M 45 . The source of the transistor M 38  is coupled to the drain of the transistor M 36 , a gate is supplied with the clock signal P 14 , and the drain is coupled to the drains of the transistors M 26 , M 32 , and M 44  and the source of the transistor M 46 . 
     A source of the transistor M 39  is grounded, and a gate is supplied with a signal DI 16 P, and a drain is coupled to a source of the transistor M 41 . A source of the transistor M 40  is grounded, and a gate is supplied with a signal DI 16 N, and a drain is coupled to a source of the transistor M 42 . The source of the transistor M 41  is coupled to the drain of the transistor M 39 , a gate is supplied with the clock signal P 14 , and the drain is coupled to a source of the transistor M 43 . The source of the transistor M 42  is coupled to the drain of the transistor M 40 , a gate is supplied with the clock signal P 14 , and a drain is coupled to a source of the transistor M 44 . The source of the transistor M 43  is coupled to the drain of the transistor M 41 , a gate is supplied with the clock signal P 16 , and the drain is coupled to the drains of the transistors M 25 , M 31 , and M 37  and the source of the transistor M 45 . The source of the transistor M 44  is coupled to the drain of the transistor M 42 , a gate is supplied with the clock signal P 16 , and the drain is coupled to the drains of the transistors M 26 , M 32 , and M 38  and the source of the transistor M 46 . 
     The source of the transistor M 45  is coupled to the drains of the transistors M 25 , M 31 , M 37 , and M 43 , and a gate is supplied with the power supply voltage VDD, and a drain is coupled to a drain of the transistor M 47  and a gate of the transistor M 48 . The source of the transistor M 46  is coupled to the drains of the transistors M 26 , M 32 , M 38 , and M 44 , and a gate is supplied with the power supply voltage VDD, and a drain is coupled to a drain of the transistor M 48  and a gate of the transistor M 47 . A source of the transistor M 47  is supplied with the power supply voltage VDD, and the gate is coupled to the drains of the transistors M 46  and M 48 , and the drain is coupled to the drain of the transistor M 45  and the gate of the transistor M 48 . A source of the transistor M 48  is supplied with the power supply voltage VDD, and the gate is coupled to the drains of the transistors M 45  and M 47 , and the drain is coupled to the drain of the transistor M 46  and the gate of the transistor M 47 . The serializer  122 A outputs a signal S 21 AP from the drains of the transistors M 46  and M 48 , and outputs a signal S 21 AN from the drains of the transistors M 45  and M 47 . 
       FIG. 25  illustrates an operation example of the serializer  122 A; (A) to (D) illustrate respective waveforms of the signals DUO, DI 12 , DI 14 , and DI 16 , and (E) to (H) illustrate respective waveforms of the clock signals P 10 , P 12 , P 14 , and P 16 , and (I) illustrates waveforms of the signals S 21 AP and S 21 AN. The clock signal P 10  makes a transition from low level to high level at timing t 13 , and makes a transition from high level to low level at timing t 17  ((E) in  FIG. 25 ). The clock signal P 12  makes a transition from low level to high level at timing t 15 , and makes a transition from high level to low level at timing t 19  ((F) in  FIG. 25 ). The clock signal P 14  makes a transition from high level to low level at timing t 13 , and makes a transition from low level to high level at timing t 17  ((G) in  FIG. 25 ). The clock signal P 16  makes a transition from high level to low level at timing t 15 , and makes a transition from low level to high level at timing t 19  ((H) in  FIG. 25 ). 
     Accordingly, in a period from timing t 13  to timing t 15  in which the clock signals P 10  and P 16  are both high level, the serializer  122 A selects the signal DI 10  (data “D 0 ( n )”) and outputs it as signals S 21 AP and S 21 AN ((I) in  FIG. 25 ). Furthermore, in a period from timing t 15  to timing t 17  in which the clock signals P 10  and P 12  are both high level, the serializer  122 A selects the signal DI 12  (data “D 2 ( n )”) and outputs it as signals S 21 AP and S 21 AN. Moreover, in a period from timing t 17  to timing t 19  in which the clock signals P 12  and P 14  are both high level, the serializer  122 A selects the signal DI 14  (data “D 4 ( n )”) and outputs it as signals S 21 AP and S 21 AN. Furthermore, in a period from timing t 19  to timing t 21  in which the clock signals P 14  and P 16  are both high level, the serializer  122 A selects the signal DI 16  (data “D 6 ( n )”) and outputs it as signals S 21 AP and S 21 AN. 
     Modification Example 1-2 
     In the above-described embodiment, the transition timing of the signals DI 10  and DI 12  and the transition timing of the signals DI 14  and DI 16  are staggered as illustrated in  FIG. 4 ; however, they are not limited to this. Instead of this, the transition timings of the signals DI 10 , DI 12 , DI 14 , and DI 16  may coincide with one another as illustrated in  FIG. 26 . 
     In this example, at timing t 13 , the signal DI 10  is set to data “D 0 ( n )”, the signal DI 12  is set to data “D 2 ( n )”, the signal DI 14  is set to data “D 4 ( n )”, and the signal DI 16  is set to data “D 6 ( n )” ((A) to (D) in  FIG. 26 ). 
     In a period from timing t 13  to timing t 15  in which the lock signal P 0  is high level, the serializer  21 A selects the signal DI 10  (the data “D 0 ( n )”), and outputs it as signals S 21 AP and S 21 AN ((I) in  FIG. 26 ). Likewise, in a period from timing t 15  to timing t 17  in which the lock signal P 2  is high level, the serializer  21 A selects the signal DI 12  (the data “D 2 ( n )”), and outputs it as signals S 21 AP and S 21 AN. In a period from timing t 17  to timing t 19  in which the lock signal P 4  is high level, the serializer  21 A selects the signal DI 14  (the data “D 4 ( n )”), and outputs it as signals S 21 AP and S 21 AN. In a period from timing t 19  to timing t 21  in which the lock signal P 6  is high level, the serializer  21 A selects the signal DI 16  (the data “D 6 ( n )”), and outputs it as signals S 21 AP and S 21 AN. 
     Modification Example 1-3 
     In the above-described embodiment, the selector type serializers  21  are used; however, it is not limited to this. A modification example is described in detail below. 
       FIG. 27  illustrates a configuration example of a serializer  123 A according to the present modification example. The serializer  123 A corresponds to the serializer  21 A according to the above-described embodiment. The serializer  123 A is a shift register type serializer. The serializer  123 A serializes signals DI 10 , DI 12 , DI 14 , and DI 16  on the basis of a clock signal CLK 2 , thereby generating signals S 21 AP and S 21 AN. The serializer  123 A includes selectors  51 ,  53 ,  55 , and  57  and flip-flops (F/Fs)  52 ,  54 ,  56 , and  58 . 
     The selector  51  selects the signal DI 16  in a case where the clock signal CLK 2  is high level, and selects a ground level in a case where the clock signal CLK 2  is low level, and outputs the selected signal. The flip-flop  52  samples and outputs the output signal of the selector  51  on the basis of the rising edge of the clock signal CLK 2 . The selector  53  selects the signal DI 14  in a case where the clock signal CLK 2  is high level, and selects the output signal of the flip-flop  52  in a case where the clock signal CLK 2  is low level, and outputs the selected signal. The flip-flop  54  samples and outputs the output signal of the selector  53  on the basis of the rising edge of the clock signal CLK 2 . The selector  55  selects the signal DI 12  in a case where the clock signal CLK 2  is high level, and selects the output signal of the flip-flop  54  in a case where the clock signal CLK 2  is low level, and outputs the selected signal. The flip-flop  56  samples and outputs the output signal of the selector  55  on the basis of the rising edge of the clock signal CLK 2 . The selector  57  selects the signal DI 10  in a case where the clock signal CLK 2  is high level, and selects the output signal of the flip-flop  56  in a case where the clock signal CLK 2  is low level, and outputs the selected signal. The flip-flop  58  samples the output signal of the selector  57  on the basis of the rising edge of the clock signal CLK 2  and outputs the sampled signal as a signal S 21 AP, and outputs an inverted signal of the signal S 21 AP as a signal S 21 AN. 
       FIG. 28  illustrates an operation example of the serializer  123 A; (A) to (D) illustrate respective waveforms of signals DI 10 , DI 12 , DI 14 , and DI 16 , and (E) illustrates a waveform of a clock signal CLK 2 , and (F) illustrates a waveform of a signal CTL 2 , and (G) illustrates waveforms of signals S 21 AP and S 21 AN. 
     In this example, at timing t 51 , the signal DI 10  is set to data “D 0 ( n )”, the signal DI 12  is set to data “D 2 ( n )”, the signal DI 14  is set to data “D 4 ( n )”, and the signal DI 16  is set to data “D 6 ( n )” ((A) to (D) in  FIG. 28 ). 
     Further, the signal CTL 2  makes a transition from low level to high level at timing t 53 , and makes a transition from high level to low level at timing t 55  ((F) in  FIG. 28 ). In a period from timing t 53  to timing t 55  in which the signal CTL 2  is high level, the selector  51  selects the signal DI 16  (the data “D 6 ( n )”), the selector  53  selects the signal DI 14  (the data “D 4 ( n )”), the selector  55  selects the signal DI 12  (the data “D 2 ( n )”), and the selector  57  selects the signal DI 10  (the data “D 0 ( n )”). Then, on the basis of the rising edge of the clock signal CLK 2  at timing t 54 , the flip-flop  52  samples the output signal (the data “D 6 ( n )”) of the selector  51 , the flip-flop  54  samples the output signal (the data “D 4 ( n )”) of the selector  53 , the flip-flop  56  samples the output signal (the data “D 2 ( n )”) of the selector  55 , and the flip-flop  58  samples the output signal (the data “D 0 ( n )”) of the selector  57 . Then, after the signal CTL 2  becomes low level at timing t 55 , the serializer  123 A operates as a shift register on the basis of the clock signal CLK 2 . 
     In this way, the serializer  123 A outputs the data “D 0 ( n )” in a period from timing t 54  to timing t 56 , and outputs the data “D 2 ( n )” in a period from timing t 56  to timing t 57 , and outputs the data “D 4 ( n )” in a period from timing t 57  to timing t 58 , and outputs the data “D 6 ( n )” in a period from timing t 58  to timing t 59  ((G) in  FIG. 28 ). 
     Modification Example 1-4 
     In the above-described embodiment, the selectors  23  are provided; however, it is not limited to this. A modification example is described in detail below. 
       FIG. 29  illustrates a configuration example of a main part of a transmitter  12 D according to the present modification example.  FIG. 29  depicts a circuit subsequent to the serializers  21 A to  21 D in  FIG. 2 . The transmitter  12 D includes four serializers  21  (the serializers  21 A,  21 B,  21 C, and  21 D), four multiplexers  22  (the multiplexers  22 A,  22 B,  22 C, and  22 D), two drivers  39  (drivers  39 A and  39 B), and a controller  25 D. 
     The driver  39 A sets a voltage at the output terminal Tout 1  on the basis of signals S 22 A, S 22 B, S 22 C, and S 22 D, signals Ssel 1 , Ssel 2 , and Ssel 3 , and a signal CTL. The driver  39 B sets a voltage at the output terminal Tout 2  on the basis of the signals S 22 A, S 22 B, S 22 C, and S 22 D, the signals Ssel 1 , Ssel 2 , and Ssel 3 , and the signal CTL. The signals Ssel 1 , Ssel 2 , and Ssel 3  are set in accordance with the operation mode. Specifically, in the operation mode MA, the signals Ssel 1  and Ssel 2  are both set to high level, and the signal Ssel 3  is set to low level. Furthermore, in the operation mode MB, the signals Ssel 1  and Ssel 3  are both set to high level, and the signal Ssel 2  is set to low level. 
       FIG. 30  illustrates a configuration example of the driver  39 A.  FIG. 31  illustrates a configuration example of the driver  39 B. The driver  39 A includes the M sub-drivers AA (the sub-drivers AA 1  to AAM), the N sub-drivers AB (the sub-drivers AB 1  to ABN), and N sub-drivers AC (sub-drivers AC 1  to ACN). The driver  39 B includes the M sub-drivers BA (the sub-drivers BA 1  to BAM), M sub-drivers BB (sub-drivers BB 1  to BBM), and N sub-drivers BC (sub-drivers BC 1  to BCN). 
     The sub-drivers AA 1  to AAM, AB 1  to ABN, AC 1  to ACN, BA 1  to BAM, and BB 1  to BBM, and BC 1  to BCN each include the resistance elements  91  and  94  and transistors  92 ,  93 ,  95 , and  96 . The transistors  92 ,  93 ,  95 , and  96  are N-channel MOS type FETs. It is to be noted that in  FIG. 29 , these transistors  92 ,  93 ,  95 , and  96  are depicted in the drivers  39 A and  39 B. Furthermore, in  FIG. 29 , an illustration of the resistance elements  91  and  94  is omitted. 
     In each of the sub-drivers AA 1  to AAM of the driver  39 A ( FIG. 30 ), one end of the resistance element  91  is supplied with a voltage V 1 , and the other end is coupled to a drain of the transistor  95 . A gate of the transistor  95  is supplied with a signal Ssel 1 , and the drain is coupled to the other end of the resistance element  91 , and a source is coupled to a drain of the transistor  92 . A gate of the transistor  92  is supplied with a signal S 22 A, and the drain is coupled to a source of the transistor  95 , and a source is coupled to a drain of the transistor  93  and the output terminal Tout 1 . A gate of the transistor  93  is supplied with a signal S 22 B, and the drain is coupled to the source of the transistor  92  and the output terminal Tout 1 , and a source is coupled to a drain of the transistor  96 . A gate of the transistor  96  is supplied with the signal Ssel 1 , and the drain is coupled to the source of the transistor  93 , and a source is coupled to one end of the resistance element  94 . The one end of the resistance element  94  is coupled to the source of the transistor  96 , and the other end is grounded. 
     In each of the sub-drivers AB 1  to ABN of the driver  39 A, one end of the resistance element  91  is supplied with the voltage V 1 , and the other end is coupled to the drain of the transistor  95 . The gate of the transistor  95  is supplied with a signal Ssel 2 , and the drain is coupled to the other end of the resistance element  91 , and the source is coupled to the drain of the transistor  92 . The gate of the transistor  92  is supplied with a signal S 22 A, and the drain is coupled to the source of the transistor  95 , and the source is coupled to the drain of the transistor  93  and the output terminal Tout 1 . The gate of the transistor  93  is supplied with a signal S 22 B, and the drain is coupled to the source of the transistor  92  and the output terminal Tout 1 , and the source is coupled to the drain of the transistor  96 . The gate of the transistor  96  is supplied with the signal Ssel 2 , and the drain is coupled to the source of the transistor  93 , and the source is coupled to one end of the resistance element  94 . The one end of the resistance element  94  is coupled to the source of the transistor  96 , and the other end is grounded. 
     In each of the sub-drivers AC 1  to ACN of the driver  39 A, one end of the resistance element  91  is supplied with the voltage V 1 , and the other end is coupled to the drain of the transistor  95 . The gate of the transistor  95  is supplied with a signal Ssel 3 , and the drain is coupled to the other end of the resistance element  91 , and the source is coupled to the drain of the transistor  92 . The gate of the transistor  92  is supplied with a signal S 22 D, and the drain is coupled to the source of the transistor  95 , and the source is coupled to the drain of the transistor  93  and the output terminal Tout 1 . The gate of the transistor  93  is supplied with a signal S 22 C, and the drain is coupled to the source of the transistor  92  and the output terminal Tout 1 , and the source is coupled to the drain of the transistor  96 . The gate of the transistor  96  is supplied with the signal Ssel 3 , and the drain is coupled to the source of the transistor  93 , and the source is coupled to one end of the resistance element  94 . The one end of the resistance element  94  is coupled to the source of the transistor  96 , and the other end is grounded. 
     In each of the sub-drivers BA 1  to BAM of the driver  39 B ( FIG. 31 ), one end of the resistance element  91  is supplied with the voltage V 1 , and the other end is coupled to the drain of the transistor  95 . The gate of the transistor  95  is supplied with a signal Ssel 3 , and the drain is coupled to the other end of the resistance element  91 , and the source is coupled to the drain of the transistor  92 . The gate of the transistor  92  is supplied with a signal S 22 B, and the drain is coupled to the source of the transistor  95 , and the source is coupled to the drain of the transistor  93  and the output terminal Tout 2 . The gate of the transistor  93  is supplied with a signal S 22 A, and the drain is coupled to the source of the transistor  92  and the output terminal Tout 2 , and the source is coupled to the drain of the transistor  96 . The gate of the transistor  96  is supplied with the signal Ssel 3 , and the drain is coupled to the source of the transistor  93 , and the source is coupled to one end of the resistance element  94 . The one end of the resistance element  94  is coupled to the source of the transistor  96 , and the other end is grounded. 
     In each of the sub-drivers BB 1  to BBM of the driver  39 B, one end of the resistance element  91  is supplied with the voltage V 1 , and the other end is coupled to the drain of the transistor  95 . The gate of the transistor  95  is supplied with a signal Ssel 2 , and the drain is coupled to the other end of the resistance element  91 , and the source is coupled to the drain of the transistor  92 . The gate of the transistor  92  is supplied with a signal S 22 C, and the drain is coupled to the source of the transistor  95 , and the source is coupled to the drain of the transistor  93  and the output terminal Tout 2 . The gate of the transistor  93  is supplied with a signal S 22 D, and the drain is coupled to the source of the transistor  92  and the output terminal Tout 2 , and the source is coupled to the drain of the transistor  96 . The gate of the transistor  96  is supplied with the signal Ssel 2 , and the drain is coupled to the source of the transistor  93 , and the source is coupled to one end of the resistance element  94 . The one end of the resistance element  94  is coupled to the source of the transistor  96 , and the other end is grounded. 
     In each of the sub-drivers BC 1  to BCN of the driver  39 B, one end of the resistance element  91  is supplied with the voltage V 1 , and the other end is coupled to the drain of the transistor  95 . The gate of the transistor  95  is supplied with a signal Ssel 1 , and the drain is coupled to the other end of the resistance element  91 , and the source is coupled to the drain of the transistor  92 . The gate of the transistor  92  is supplied with a signal S 22 C, and the drain is coupled to the source of the transistor  95 , and the source is coupled to the drain of the transistor  93  and the output terminal Tout 2 . The gate of the transistor  93  is supplied with a signal S 22 D, and the drain is coupled to the source of the transistor  92  and the output terminal Tout 2 , and the source is coupled to the drain of the transistor  96 . The gate of the transistor  96  is supplied with the signal Ssel 1 , and the drain is coupled to the source of the transistor  93 , and the source is coupled to one end of the resistance element  94 . The one end of the resistance element  94  is coupled to the source of the transistor  96 , and the other end is grounded. 
     For example, in the operation mode MA (single-phase mode), the signals Ssel 1  and Ssel 2  are both set to high level, and the signal Ssel 3  is set to low level. Accordingly, in the driver  39 A ( FIG. 30 ), the sub-drivers AA 1  to AAM and AB 1  to ABN are enabled, and the sub-drivers AC 1  to ACN are disabled. Furthermore, in the driver  39 B ( FIG. 31 ), the sub-drivers BB 1  to BBM and BC 1  to BCN are enabled, and the sub-drivers BA 1  to BAM are disabled. 
     Furthermore, for example, in the operation mode MB (differential mode), the signals Ssel 1  and Ssel 3  are both set to high level, and the signal Ssel 2  is set to low level. Accordingly, in the driver  39 A ( FIG. 30 ), the sub-drivers AA 1  to AAM and AC 1  to ACN are enabled, and the sub-drivers AB 1  to ABN are disabled. Furthermore, in the driver  39 B ( FIG. 31 ), the sub-drivers BA 1  to BAM and BC 1  to BCN are enabled, and the sub-drivers BB 1  to BBM are disabled. 
     The controller  25 D ( FIG. 29 ) generates clock signals P 0  to P 7  and CLK and signals Ssel 1 , Ssel 2 , Ssel 3 , and CTL on the basis of a mode signal Smode supplied from the processor  11 . 
     Here, the driver  39 A corresponds to a specific example of the “first driver” in the present disclosure. The plurality of sub-drivers AA 1  to AAM correspond to a specific example of the “first sub-driver unit” in the present disclosure; the plurality of sub-drivers AB 1  to ABN correspond to a specific example of a “fifth sub-driver unit” in the present disclosure; and the plurality of sub-drivers AC 1  to ACN correspond to a specific example of a “sixth sub-driver unit” in the present disclosure. The driver  39 B corresponds to a specific example of the “second driver” in the present disclosure. 
       FIG. 32  illustrates the flow of signals in the operation mode MA. In  FIG. 32 , bold solid lines indicate the flow of signals related to signals DI 10  to DI 17 , and bold dashed lines indicate the flow of signals related to signals DI 20  to DI 27 . The sub-drivers AA 1  to AAM of the driver  39 A operate on the basis of signals S 22 A and S 22 B, and the sub-drivers AB 1  to ABN of the driver  39 A operate on the basis of the signals S 22 A and S 22 B. Furthermore, the sub-drivers BB 1  to BBM of the driver  39 B operate on the basis of signals S 22 C and S 22 D, and the sub-drivers BC 1  to BCN of the driver  39 B operate on the basis of the signals S 22 C and S 22 D. 
       FIG. 33  illustrates the flow of signals in the operation mode MB. In  FIG. 33 , bold solid lines indicate the flow of signals related to signals DI 10  to DI 17 , and bold dashed lines indicate the flow of signals related to signals DI 20  to DI 27 . The sub-drivers AA 1  to AAM of the driver  39 A operate on the basis of signals S 22 A and S 22 B, and the sub-drivers BA 1  to BAM of the driver  39 B operate on the basis of the signals S 22 B and S 22 A. The sub-drivers AC 1  to ACN of the driver  39 A operate on the basis of signals S 22 C and S 22 D, and the sub-drivers BC 1  to BCM of the driver  39 B operate on the basis of the signals S 22 D and S 22 C. 
     Modification Example 1-5 
     In the above-described embodiment, the selectors  23  are provided in the subsequent stage of the multiplexers  22 ; however, it is not limited to this. A modification example is described in detail below. 
       FIG. 34  illustrates a configuration example of a transmitter  12 E according to the present modification example. The transmitter  12 E includes eight selectors  26  (selectors  26 A to  26 H) and eight multiplexers  27  (multiplexers  27 A to  27 H). 
     On the basis of a signal Ssel, the selector  26 A selects a signal S 21 AP in a case where the operation mode is the operation mode MA (single-phase mode), and selects a signal S 21 BN in a case where the operation mode is the operation mode MB (differential mode), and then outputs the selected signal. On the basis of a signal Ssel, the selector  26 B selects a signal S 21 CP in a case where the operation mode is the operation mode MA, and selects a signal S 21 DN in a case where the operation mode is the operation mode MB, and then outputs the selected signal. On the basis of a signal Ssel, the selector  26 C selects a signal S 21 AN in a case where the operation mode is the operation mode MA, and selects a signal S 21 BP in a case where the operation mode is the operation mode MB, and then outputs the selected signal. On the basis of a signal Ssel, the selector  26 D selects a signal S 21 CN in a case where the operation mode is the operation mode MA, and selects a signal S 21 DP in a case where the operation mode is the operation mode MB, and then outputs the selected signal. On the basis of a signal Ssel, the selector  26 E selects a signal S 21 BP in a case where the operation mode is the operation mode MA, and selects a signal S 21 AN in a case where the operation mode is the operation mode MB, and then outputs the selected signal. On the basis of a signal Ssel, the selector  26 F selects a signal S 21 DP in a case where the operation mode is the operation mode MA, and selects a signal S 21 CN in a case where the operation mode is the operation mode MB, and then outputs the selected signal. On the basis of a signal Ssel, the selector  26 G selects a signal S 21 BN in a case where the operation mode is the operation mode MA, and selects a signal S 21 AP in a case where the operation mode is the operation mode MB, and then outputs the selected signal. On the basis of a signal Ssel, the selector  26 H selects a signal S 21 DN in a case where the operation mode is the operation mode MA, and selects a signal S 21 CP in a case where the operation mode is the operation mode MB, and then outputs the selected signal. 
     The multiplexer  27 A alternately selects one of the signals S 21 AP and S 21 CP on the basis of a clock signal CLK, and outputs the selected signal. The multiplexer  27 B alternately selects one of the signals S 21 AN and S 21 CN on the basis of a clock signal CLK, and outputs the selected signal. The multiplexer  27 C alternately selects one of the output signals of the selectors  26 A and  26 B on the basis of a clock signal CLK, and outputs the selected signal. The multiplexer  27 D alternately selects one of the output signals of the selectors  26 C and  26 D on the basis of a clock signal CLK, and outputs the selected signal. The multiplexer  27 E alternately selects one of the output signals of the selectors  26 E and  26 F on the basis of a clock signal CLK, and outputs the selected signal. The multiplexer  27 F alternately selects one of the output signals of the selectors  26 G and  26 H on the basis of a clock signal CLK, and outputs the selected signal. The multiplexer  27 G alternately selects one of the signals S 21 BP and S 21 DP on the basis of a clock signal CLK, and outputs the selected signal. The multiplexer  27 H alternately selects one of the signals S 21 BN and S 21 DN on the basis of a clock signal CLK, and outputs the selected signal. 
     Here, the plurality of multiplexers  27 A to  27 H correspond to a specific example of the “multiplexer unit” in the present disclosure. 
     With this configuration, in the driver  24 A, the sub-drivers AA 1  to AAM operate on the basis of the output signal of the multiplexer  27 A and the output signal of the multiplexer  27 B, and the sub-drivers AB 1  to ABN operate on the basis of the output signal of the multiplexer  27 C and the output signal of the multiplexer  27 D. Furthermore, in the driver  24 B, the sub-drivers BA 1  to BAM operate on the basis of the output signal of the multiplexer  27 E and the output signal of the multiplexer  27 F, and the sub-drivers BB 1  to BBN operate on the basis of the output signal of the multiplexer  27 G and the output signal of the multiplexer  27 H. 
       FIG. 35  illustrates the flow of signals in the operation mode MA (single-phase mode). In  FIG. 35 , bold solid lines indicate the flow of signals related to DI 10  to DI 17 , and bold dashed lines indicate the flow of signals related to signals DI 20  to DI 27 . 
     First, the flow of signals related to DI 10  to DI 17  is described. In the operation mode MA, the selector  26 A selects a signal S 21 AP on the basis of a signal Ssel, and outputs the signal S 21 AP. The selector  26 B selects a signal S 21 CP on the basis of a signal Ssel, and outputs the signal S 21 CP. The selector  26 C selects a signal S 21 AN on the basis of a signal Ssel, and outputs the signal S 21 AN. The selector  26 D selects a signal S 21 CN on the basis of a signal Ssel, and outputs the signal S 21 CN. 
     The multiplexer  27 A alternately selects one of the signals S 21 AP and S 21 CP on the basis of a clock signal CLK, and outputs the selected signal. The multiplexer  27 B alternately selects one of the signals S 21 AN and S 21 CN on the basis of a clock signal CLK, and outputs the selected signal. The multiplexer  27 C alternately selects one of the output signal (the signal S 21 AP) of the selector  26 A and the output signal (the signal S 21 CP) of the selector  26 B on the basis of a clock signal CLK, and outputs the selected signal. The multiplexer  27 D alternately selects one of the output signal (the signal S 21 AN) of the selector  26 C and the output signal (the signal S 21 CN) of the selector  26 D on the basis of a clock signal CLK, and outputs the selected signal. 
     Next, the flow of signals related to DI 20  to DI 27  is described. In the operation mode MA, the selector  26 E selects a signal S 21 BP on the basis of a signal Ssel, and outputs the signal S 21 BP. The selector  26 F selects a signal S 21 DP on the basis of a signal Ssel, and outputs the signal S 21 DP. The selector  26 G selects a signal S 21 BN on the basis of a signal Ssel, and outputs the signal S 21 BN. The selector  26 H selects a signal S 21 DN on the basis of a signal Ssel, and outputs the signal S 21 DN. 
     The multiplexer  27 E alternately selects one of the output signal (the signal S 21 BP) of the selector  26 E and the output signal (the signal S 21 DP) of the selector  26 F on the basis of a clock signal CLK, and outputs the selected signal. The multiplexer  27 F alternately selects one of the output signal (the signal S 21 BN) of the selector  26 G and the output signal (the signal S 21 DN) of the selector  26 H on the basis of a clock signal CLK, and outputs the selected signal. The multiplexer  27 G alternately selects one of the signals S 21 BP and S 21 DP on the basis of a clock signal CLK, and outputs the selected signal. The multiplexer  27 H alternately selects one of the signals S 21 BN and S 21 DN on the basis of a clock signal CLK, and outputs the selected signal. 
       FIG. 36  illustrates the flow of signals in the operation mode MB (differential mode). In  FIG. 36 , bold solid lines indicate the flow of signals related to DI 10  to DI 17 , and bold dashed lines indicate the flow of signals related to signals DI 20  to DI 27 . 
     First, the flow of signals related to DI 10  to DI 17  is described. In the operation mode MB, the selector  26 E selects a signal S 21 AN on the basis of a signal Ssel, and outputs the signal S 21 AN. The selector  26 F selects a signal S 21 CN on the basis of a signal Ssel, and outputs the signal S 21 CN. The selector  26 G selects a signal S 21 AP on the basis of a signal Ssel, and outputs the signal S 21 AP. The selector  26 H selects a signal S 21 CP on the basis of a signal Ssel, and outputs the signal S 21 CP. 
     The multiplexer  27 A alternately selects one of the signals S 21 AP and S 21 CP on the basis of a clock signal CLK, and outputs the selected signal. The multiplexer  27 B alternately selects one of the signals S 21 AN and S 21 CN on the basis of a clock signal CLK, and outputs the selected signal. The multiplexer  27 E alternately selects one of the output signal (the signal S 21 AN) of the selector  26 E and the output signal (the signal S 21 CN) of the selector  26 F on the basis of a clock signal CLK, and outputs the selected signal. The multiplexer  27 F alternately selects one of the output signal (the signal S 21 AP) of the selector  26 G and the output signal (the signal S 21 CP) of the selector  26 H on the basis of a clock signal CLK, and outputs the selected signal. 
     Next, the flow of signals related to DI 20  to DI 27  is described. In the operation mode MB, the selector  26 A selects a signal S 21 BN on the basis of a signal Ssel, and outputs the signal S 21 BN. The selector  26 B selects a signal S 21 DN on the basis of a signal Ssel, and outputs the signal S 21 DN. The selector  26 C selects a signal S 21 BP on the basis of a signal Ssel, and outputs the signal S 21 BP. The selector  26 D selects a signal S 21 DP on the basis of a signal Ssel, and outputs the signal S 21 DP. 
     The multiplexer  27 C alternately selects and outputs one of the output signal (the signal S 21 BN) of the selector  26 A and the output signal (the signal S 21 DN) of the selector  26 B on the basis of a clock signal CLK. The multiplexer  27 D alternately selects and outputs one of the output signal (the signal S 21 BP) of the selector  26 C and the output signal (the signal S 21 DP) of the selector  26 D on the basis of a clock signal CLK. The multiplexer  27 G alternately selects and outputs one of the signals S 21 BP and S 21 DP on the basis of a clock signal CLK. The multiplexer  27 H alternately selects and outputs one of the signals S 21 BN and S 21 DN on the basis of a clock signal CLK. 
     2. Second Embodiment 
     Subsequently, communication systems  2 A to  2 C according to a second embodiment are described. In the present embodiment, there is provided a transmitting device configured to be able to perform communication using a signal having three voltage levels in addition to a single-phase signal and a differential signal. It is to be noted that a component substantially identical to that of the communication systems  1 A and  1 B according to the above-described first embodiment is assigned the same reference numeral, and description of the component is omitted accordingly. 
       FIGS. 37A, 37B, and 37C  illustrate respective configuration example of communication systems to which a transmitting device (a transmitting device  60 ) according to the second embodiment is applied;  FIG. 37A  illustrates the communication system  2 A,  FIG. 37B  illustrates the communication system  2 B, and  FIG. 37C  illustrates the communication system  2 C. The communication system  2 A performs communication using a single-phase signal, as with the communication system  1 A according to the first embodiment. The communication system  2 B performs communication using a differential signal, as with the communication system  1 B according to the first embodiment. The communication system  2 C performs communication using a signal having three voltage levels (hereinafter, also referred to as a “three-phase signal”). 
     As illustrated in  FIG. 37A , the communication system  2 A includes the transmitting device  60  and a receiving device  130 . The transmitting device  60  has four output terminals Tout 1  to Tout 4 , and the receiving device  130  has four input terminals Tin 1  to Tin 4 . The output terminal Tout 1  of the transmitting device  60  and the input terminal Tin 1  of the receiving device  130  are coupled to each other through the line  101 ; the output terminal Tout 2  of the transmitting device  60  and the input terminal Tin 2  of the receiving device  130  are coupled to each other through the line  102 ; the output terminal Tout 3  of the transmitting device  60  and the input terminal Tin 3  of the receiving device  130  are coupled to each other through a line  103 ; and the output terminal Tout 4  of the transmitting device  60  and the input terminal Tin 4  of the receiving device  130  are coupled to each other through a line  104 . Respective characteristic impedances of the lines  101  to  104  are about 50[Ω] in this example. The transmitting device  60  uses the line  101  to transmit a signal SIG 1 , and uses the line  102  to transmit a signal SIG 2 , and uses the line  103  to transmit a signal SIG 3 , and uses the line  104  to transmit a signal SIG 4 . The signals SIG 1  to SIG 4  are each a single-phase signal. 
     As illustrated in  FIG. 37B , the communication system  2 B includes the transmitting device  60  and a receiving device  140 . The receiving device  140  has four input terminals Tin 1 P, Tin 1 N, Tin 2 P, and Tin 2 N. The output terminal Tout 1  of the transmitting device  60  and the input terminal Tin 1 P of the receiving device  140  are coupled to each other through the line  111 ; the output terminal Tout 2  of the transmitting device  60  and the input terminal Tin 1 N of the receiving device  140  are coupled to each other through the line  112 ; the output terminal Tout 3  of the transmitting device  60  and the input terminal Tin 2 P of the receiving device  140  are coupled to each other through a line  113 ; and the output terminal Tout 4  of the transmitting device  60  and the input terminal Tin 2 N of the receiving device  140  are coupled to each other through a line  114 . Respective characteristic impedances of the lines  111  to  114  are about 50[Ω] in this example. The transmitting device  60  uses the line  111  to transmit a signal SIG 1 P, and uses the line  112  to transmit a signal SIG 1 N. The signals SIG 1 P and SIG 1 N compose a differential signal. Furthermore, the transmitting device  60  uses the line  113  to transmit a signal SIG 2 P, and uses the line  114  to transmit a signal SIG 2 N. The signals SIG 2 P and SIG 2 N compose a differential signal. In the communication system  2 B, the transmitting device  60  performs an emphasis operation, thereby transmitting signals SIG 1 P and SIG 1 N and signals SIG 2 P and SIG 2 N, as with the transmitting device  10  according to the first embodiment. 
     As illustrated in  FIG. 37C , the communication system  2 C includes the transmitting device  60  and a receiving device  150 . The receiving device  150  has three input terminals TinA, TinB, and TinC. The output terminal Tout 1  of the transmitting device  60  and the input terminal TinA of the receiving device  150  are coupled to each other through a line  121 ; the output terminal Tout 2  of the transmitting device  60  and the input terminal TinB of the receiving device  150  are coupled to each other through a line  122 ; and the output terminal Tout 3  of the transmitting device  60  and the input terminal TinC of the receiving device  150  are coupled to each other through a line  123 . Respective characteristic impedances of the lines  121  to  123  are about 50[Ω] in this example. The transmitting device  60  uses the line  121  to transmit a signal SIGA, and uses the line  122  to transmit a signal SIGB, and uses the line  123  to transmit a signal SIGC. The signals SIGA, SIGB, and SIGC compose a three-phase signal. 
       FIG. 38  illustrates respective voltages of the signals SIGA, SIGB, and SIGC. In the communication system  2 C, the transmitting device  60  uses three signals SIGA, SIGB, and SIGC to transmit six symbols “+x”, “−x”, “+y”, “−y”, “+z”, and “−z”. For example, in a case of transmitting the symbol “+x”, the transmitting device  60  sets the signal SIGA to the high-level voltage VH, and sets the signal SIGB to the low-level voltage VL, and sets the signal SIGC to a medium-level voltage VM. In a case of transmitting the symbol “−x”, the transmitting device  60  sets the signal SIGA to the low-level voltage VL, and sets the signal SIGB to the high-level voltage VH, and sets the signal SIGC to the medium-level voltage VM. In a case of transmitting the symbol “+y”, the transmitting device  60  sets the signal SIGA to the medium-level voltage VM, and sets the signal SIGB to the high-level voltage VH, and sets the signal SIGC to the low-level voltage VL. In a case of transmitting the symbol “−y”, the transmitting device  60  sets the signal SIGA to the medium-level voltage VM, and sets the signal SIGB to the low-level voltage VL, and sets the signal SIGC to the high-level voltage VH. In a case of transmitting the symbol “+z”, the transmitting device  60  sets the signal SIGA to the low-level voltage VL, and sets the signal SIGB to the medium-level voltage VM, and sets the signal SIGC to the high-level voltage VH. In a case of transmitting the symbol “−z”, the transmitting device  60  sets the signal SIGA to the high-level voltage VH, and sets the signal SIGB to the medium-level voltage VM, and sets the signal SIGC to the low-level voltage VL. 
     The transmitting device  60  has three operation modes MA, MB, and MC. In a case where the transmitting device  60  is applied to the communication system  2 A, the transmitting device  60  operates in the operation mode MA (single-phase mode); in a case where the transmitting device  60  is applied to the communication system  2 B, the transmitting device  60  operates in the operation mode MB (differential mode); in a case where the transmitting device  60  is applied to the communication system  2 C, the transmitting device  60  operates in the operation mode MC (three-phase mode). 
     (Transmitting Device  60 ) 
     The transmitting device  60  includes a processor  61  and a transmitter  62  as illustrated in  FIGS. 37A to 37C . 
     The processor  61  generates data to be transmitted by performing a predetermined process. Furthermore, the processor  61  selects one of the three operation modes MA, MB, and MC, and notifies the transmitter  62  of the selected operation mode by using a mode signal Smode. Specifically, in a case where the transmitting device  60  is applied to the communication system  2 A, the processor  61  selects the operation mode MA (single-phase mode), and instructs the transmitter  62  to perform the operation in the operation mode MA by using a mode signal Smode. Furthermore, in a case where the transmitting device  60  is applied to the communication system  2 B, the transmitter  62  selects the operation mode MB (differential mode), and instructs the transmitter  62  to perform the operation in the operation mode MB by using a mode signal Smode. Moreover, in a case where the transmitting device  60  is applied to the communication system  2 C, the transmitter  62  selects the operation mode MC (three-phase mode), and instructs the transmitter  62  to perform the operation in the operation mode MC by using a mode signal Smode. 
     The transmitter  62  transmits data generated by the processor  61  on the basis of a mode signal Smode. Specifically, in a case where the operation mode indicated by the mode signal Smode is the operation mode MA (single-phase mode), the transmitter  62  transmits data generated by the processor  61  by using signals SIG 1  to SIG 4 . Furthermore, in a case where the operation mode indicated by the mode signal Smode is the operation mode MB, the transmitter  62  transmits data generated by the processor  61  by using signals SIG 1 P and SIG 1 N and signals SIG 2 P and SIG 2 N. Moreover, in a case where the operation mode indicated by the mode signal Smode is the operation mode MC, the transmitter  62  transmits data generated by the processor  61  by using signals SIGA, SIGB, and SIGC. 
       FIG. 39  illustrates a configuration example of the transmitter  62 . The transmitter  62  includes transmitting circuit units  62 A and  62 B and a controller  65 .  FIG. 40A  illustrates a configuration example of the transmitting circuit unit  62 A, and  FIG. 40B  illustrates a configuration example of the transmitting circuit unit  62 B. The transmitting circuit unit  62 A includes four serializers  28  (serializers  28 A,  28 B,  28 C, and  28 D), four encoders  29  (encoders  29 A,  29 B,  29 C, and  29 D), four multiplexers  22  (the multiplexers  22 A,  22 B,  22 C, and  22 D), four selectors  23  (the selectors  23 A,  23 B,  23 C, and  23 D), and two drivers  24  (the drivers  24 A and  24 B). The transmitting circuit unit  62 B includes four serializers  28  (serializers  28 E,  28 F,  28 G, and  28 H), four encoders  29  (encoders  29 E,  29 F,  29 G, and  29 H), four multiplexers  22  (multiplexers  22 E,  22 F,  22 G, and  22 H), four selectors  23  (selectors  23 E,  23 F,  23 G, and  23 H), and two drivers  24  (drivers  24 C and  24 D). 
     The serializer  28 A ( FIG. 40A ) serializes signals DI 10 , DI 12 , DI 14 , and DI 16  on the basis of clock signals P 0 , P 2 , P 4 , and P 6 , thereby generating a signal S 28 A, as with the serializer  21 A according to the first embodiment. The serializer  28 B serializes signals DI 20 , DI 22 , DI 24 , and DI 26  on the basis of clock signals P 0 , P 2 , P 4 , and P 6 , thereby generating a signal S 28 B, as with the serializer  21 B according to the first embodiment. The serializer  28 C serializes signals DI 11 , DI 13 , DI 15 , and DI 17  on the basis of clock signals P 1 , P 3 , P 5 , and P 7 , thereby generating a signal S 28 C, as with the serializer  21 C according to the first embodiment. The serializer  28 D serializes signals DI 21 , DI 23 , DI 25 , and DI 27  on the basis of clock signals P 1 , P 3 , P 5 , and P 7 , thereby generating a signal S 28 D, as with the serializer  21 D according to the first embodiment. Likewise, serializer  28 E ( FIG. 40B ) serializes signals DI 30 , DI 32 , DI 34 , and DI 36  on the basis of clock signals P 0 , P 2 , P 4 , and P 6 , thereby generating a signal S 28 E. The serializer  28 F serializes signals DI 40 , DI 42 , DI 44 , and DI 46  on the basis of clock signals P 0 , P 2 , P 4 , and P 6 , thereby generating a signal S 28 F. The serializer  28 G serializes signals DI 31 , DI 33 , DI 35 , and DI 37  on the basis of clock signals P 1 , P 3 , P 5 , and P 7 , thereby generating a signal S 28 G. The serializer  28 H serializes signals DI 41 , DI 43 , DI 45 , and DI 47  on the basis of clock signals P 1 , P 3 , P 5 , and P 7 , thereby generating a signal S 28 H. The serializers  28 A to  28 H have the same configuration as the serializer  21 A ( FIG. 3 ) according to the first embodiment. 
       FIG. 41  illustrates respective signal paths of the signals S 28 A to S 28 H generated by the serializers  28 A to  28 H. The serializer  28 A supplies the signal S 28 A to the encoders  29 A and  29 B. The serializer  28 B supplies the signal S 28 B to the encoders  29 B and  29 E. The serializer  28 C supplies the signal S 28 C to the encoders  29 C and  29 D. The serializer  28 D supplies the signal S 28 D to the encoders  29 D and  29 G. The serializer  28 E supplies the signal S 28 E to the encoders  29 A and  29 E. The serializer  28 F supplies the signal S 28 F to the encoder  29 F. The serializer  28 G supplies the signal S 28 G to the encoders  29 C and  29 G. The serializer  28 H supplies the signal S 28 H to the encoder  29 H. 
     The encoder  29 A ( FIG. 40A ) generates signals S 29 AP and S 29 AN on the basis of the signals S 28 A and S 28 E and a signal EN. The encoder  29 A has input terminals in 1 , in 2 , and CEN and output terminals out 1  and out 2 . The input terminal in 1  of the encoder  29 A is supplied with the signal S 28 A, and the input terminal in 2  is supplied with the signal S 28 E, and the input terminal CEN is supplied with the signal EN. The signal EN is a signal that becomes low level “0” in the operation modes MA and MB, and becomes high level “1” in the operation mode MC. Then, the encoder  29 A outputs the signal S 29 AP from the output terminal out 1 , and outputs the signal S 29 AN from the output terminal out 2 . 
     Likewise, the encoder  29 B generates signals S 29 BP and S 29 BN on the basis of the signals S 28 B and S 28 A and a signal EN. The encoder  29 C generates signals S 29 CP and S 29 CN on the basis of the signals S 28 C and S 28 G and a signal EN. The encoder  29 D generates signals S 29 DP and S 29 DN on the basis of the signals S 28 D and S 28 C and a signal EN. The encoder  29 E ( FIG. 40B ) generates signals S 29 EP and S 29 EN on the basis of the signals S 28 E and S 28 B and a signal EN. The encoder  29 F generates signals S 29 FP and S 29 FN on the basis of the signal S 28 F and a signal EN. The encoder  29 G generates signals S 29 GP and S 29 GN on the basis of the signals S 28 G and S 28 D and a signal EN. The encoder  29 H generates signals S 29 HP and S 29 HN on the basis of the signal S 28 H and a signal EN. 
       FIG. 42  illustrates a configuration example of the encoder  29 . The encoder  29  includes a selector  201 , an exclusive OR circuit (EX-OR)  202 , and AND circuits (ANDs)  203  and  204 . The selector  201  selects an inverted signal of a signal at the input terminal in 1  in a case where the signal EN at the input terminal CEN is low level, and selects a signal at the input terminal in 2  in a case where the signal EN at the input terminal CEN is high level, and outputs the selected signal. The exclusive OR circuit  202  finds an exclusive logical sum of the signal at the input terminal in 1  and the output signal of the selector  201 , and outputs its result. The AND circuit  203  finds a logical product of the signal at the input terminal in 1  and the output signal of the exclusive OR circuit  202 , and outputs its result from the output terminal out 1 . The AND circuit  204  finds a logical product of the output signal of the selector  201  and the output signal of the exclusive OR circuit  202 , and outputs its result from the output terminal out 2 . 
       FIG. 43  illustrates an operation example of the encoder  29 . In the operation modes MA and MB, the signal EN at the input terminal CEN becomes low level “0”. In this case, the encoder  29  outputs the same signal as the signal at the input terminal in 1  from the output terminal out 1 , and outputs an inverted signal of the signal at the input terminal in 1  from the output terminal out 2 . On the other hand, in the operation mode MC, the signal EN at the input terminal CEN becomes high level “1”. In this case, in a case where the signals at the input terminals in 1  and in 2  are “1” and “0”, respectively, the encoder  29  sets the signals at the output terminals out 1  and out 2  to “1” and “0”, respectively; in a case where the signals at the input terminals in 1  and in 2  are “0” and “1”, respectively, the encoder  29  sets the signals at the output terminals out 1  and out 2  to “0” and “1”, respectively; and in a case where the signals at the input terminals in 1  and in 2  are equal to each other, the encoder  29  sets both of the signals at the output terminals out 1  and out 2  to “0”. 
     It is to be noted that in this example, the encoder  29  is configured as illustrated in  FIG. 42 ; however, it is not limited to this. For example, an encoder (an encoder  127 ) may be configured as illustrated in  FIG. 44 . This encoder  127  includes an OR circuit  221 , inverted AND circuits  222  and  223 , and AND circuits  224  and  225 . The OR circuit  221  finds a logical sum of an inverted signal of the signal EN at the input terminal CEN and the signal at the input terminal in 2 , and outputs its result. The inverted AND circuit  222  finds an inverted logical product of the signal at the input terminal in 1 , the signal EN at the input terminal CEN, and the output signal of the OR circuit  221 , and outputs its result. The inverted AND circuit  223  finds an inverted logical product of the signal at the input terminal in 1  and the output signal of the OR circuit  221 , and outputs its result. The AND circuit  224  finds a logical product of the signal at the input terminal in 1  and the output signal of the inverted AND circuit  222 , and outputs its result from the output terminal out 1 . The AND circuit  225  finds a logical product of the output signal of the OR circuit  221  and the output signal of the inverted AND circuit  223 , and outputs its result from the output terminal out 2 . The operation of this encoder  127  is the same as the operation of the encoder  29  ( FIG. 43 ). 
     The multiplexer  22 A ( FIG. 40A ) alternately selects one of the signals S 29 AP and S 29 CP on the basis of a clock signal CLK, and outputs the selected signal as a signal S 22 A, as with the multiplexer  22 A according to the first embodiment. The multiplexer  22 B alternately selects one of the signals S 29 AN and S 29 CN on the basis of a clock signal CLK, and outputs the selected signal as a signal S 22 B, as with the multiplexer  22 B according to the first embodiment. The multiplexer  22 C alternately selects one of the signals S 29 BP and S 29 DP on the basis of a clock signal CLK, and outputs the selected signal as a signal S 22 C, as with the multiplexer  22 C according to the first embodiment. The multiplexer  22 D alternately selects one of the signals S 29 BN and S 29 DN on the basis of a clock signal CLK, and outputs the selected signal as a signal S 22 D, as with the multiplexer  22 D according to the first embodiment. Likewise, the multiplexer  22 E ( FIG. 40B ) alternately selects one of the signals S 29 EP and S 29 GP on the basis of a clock signal CLK, and outputs the selected signal as a signal S 22 E. The multiplexer  22 F alternately selects one of the signals S 29 EN and S 29 GN on the basis of a clock signal CLK, and outputs the selected signal as a signal S 22 F. The multiplexer  22 G alternately selects one of the signals S 29 FP and S 29 HP on the basis of a clock signal CLK, and outputs the selected signal as a signal S 22 G. The multiplexer  22 H alternately selects one of the signals S 29 FN and S 29 HN on the basis of a clock signal CLK, and outputs the selected signal as a signal S 22 H. 
     On the basis of a signal Ssel, the selector  23 A ( FIG. 40A ) selects the signal S 22 A in a case where the operation mode is the operation mode MA (single-phase mode) or the operation mode MC (three-phase mode), or selects the signal S 22 D in a case where the operation mode is the operation mode MB (differential mode), and outputs the selected signal as a signal S 23 A, as with the selector  23 A according to the first embodiment. On the basis of a signal Ssel, the selector  23 B selects the signal S 22 B in a case where the operation mode is the operation mode MA or the operation mode MC, or selects the signal S 22 C in a case where the operation mode is the operation mode MB, and outputs the selected signal as a signal S 23 B, as with the selector  23 B according to the first embodiment. On the basis of a signal Ssel, the selector  23 C selects the signal S 22 C in a case where the operation mode is the operation mode MA or the operation mode MC, or selects the signal S 22 B in a case where the operation mode is the operation mode MB, and outputs the selected signal as a signal S 23 C, as with the selector  23 C according to the first embodiment. On the basis of a signal Ssel, the selector  23 D selects the signal S 22 D in a case where the operation mode is the operation mode MA or the operation mode MC, or selects the signal S 22 A in a case where the operation mode is the operation mode MB, and outputs the selected signal as a signal S 23 D, as with the selector  23 D according to the first embodiment. Likewise, on the basis of a signal Ssel, the selector  23 E ( FIG. 40B ) selects the signal S 22 E in a case where the operation mode is the operation mode MA or the operation mode MC, or selects the signal S 22 H in a case where the operation mode is the operation mode MB, and outputs the selected signal as a signal S 23 E. On the basis of a signal Ssel, the selector  23 F selects the signal S 22 F in a case where the operation mode is the operation mode MA or the operation mode MC, or selects the signal S 22 G in a case where the operation mode is the operation mode MB, and outputs the selected signal as a signal S 23 F. On the basis of a signal Ssel, the selector  23 G selects the signal S 22 G in a case where the operation mode is the operation mode MA or the operation mode MC, or selects the signal S 22 F in a case where the operation mode is the operation mode MB, and outputs the selected signal as a signal S 23 G. On the basis of a signal Ssel, the selector  23 H selects the signal S 22 H in a case where the operation mode is the operation mode MA or the operation mode MC, or selects the signal S 22 E in a case where the operation mode is the operation mode MB, and outputs the selected signal as a signal S 23 H. 
     The driver  24 A ( FIG. 40A ) sets a voltage at the output terminal Tout 1  on the basis of the signals S 22 A, S 22 B, S 23 A, and S 23 B and a signal CTL, as with the driver  24 A according to the first embodiment. The driver  24 B sets a voltage at the output terminal Tout 2  on the basis of the signals S 23 C, S 23 D, S 22 C, and S 22 D and the signal CTL, as with the driver  24 B according to the first embodiment. Likewise, the driver  24 C ( FIG. 40B ) sets a voltage at the output terminal Tout 3  on the basis of the signals S 22 E, S 22 F, S 23 E, and S 23 F and a signal CTL. The driver  24 D sets a voltage at the output terminal Tout 4  on the basis of the signals S 23 G, S 23 H, S 22 G, and S 22 H and the signal CTL. 
     The drivers  24 C and  24 D have the same configuration as the drivers  24 A and  24 B ( FIG. 8 ). The driver  24 C includes M sub-drivers CA (sub-drivers CA 1  to CAM) and N sub-drivers CB (sub-drivers CB 1  to CBN). The driver  24 D includes M sub-drivers DA (sub-drivers DA 1  to DAM) and N sub-drivers DB (sub-drivers DB 1  to DBN). 
     In the driver  24 C, in each of the sub-drivers CA 1  to CAM, the gate of the transistor  92  is supplied with the signal S 22 E, and the drain is coupled to the other end of the resistance element  91 , and the source is coupled to the drain of the transistor  93  and the output terminal Tout 3 . The gate of the transistor  93  is supplied with the signal S 22 F, and the drain is coupled to the source of the transistor  92  and the output terminal Tout 3 , and the source is coupled to one end of the resistance element  94 . Furthermore, in each of the sub-drivers CB 1  to CBN, the gate of the transistor  92  is supplied with the signal S 23 E, and the drain is coupled to the other end of the resistance element  91 , and the source is coupled to the drain of the transistor  93  and the output terminal Tout 3 . The gate of the transistor  93  is supplied with the signal S 23 F, and the drain is coupled to the source of the transistor  92  and the output terminal Tout 3 , and the source is coupled to one end of the resistance element  94 . 
     In the driver  24 D, in each of the sub-drivers DA 1  to DAM, the gate of the transistor  92  is supplied with the signal S 23 G, and the drain is coupled to the other end of the resistance element  91 , and the source is coupled to the drain of the transistor  93  and the output terminal Tout 4 . The gate of the transistor  93  is supplied with the signal S 23 H, and the drain is coupled to the source of the transistor  92  and the output terminal Tout 4 , and the source is coupled to one end of the resistance element  94 . Furthermore, in each of the sub-drivers DB 1  to DBN, the gate of the transistor  92  is supplied with the signal S 22 G, and the drain is coupled to the other end of the resistance element  91 , and the source is coupled to the drain of the transistor  93  and the output terminal Tout 4 . The gate of the transistor  93  is supplied with the signal S 22 H, and the drain is coupled to the source of the transistor  92  and the output terminal Tout 4 , and the source is coupled to one end of the resistance element  94 . 
     With this configuration, for example, in a case where in the operation mode MC, the signals S 22 A and S 22 B are both set to low level, the signals S 23 A and  23 B both become low level. Therefore, the transistors  92  and  93  in the sub-drivers AA 1  to AAM and AB 1  to ABN of the driver  24 A go into off state. As a result, the driver  24 A sets the output impedance to high impedance. 
     The controller  65  ( FIG. 39 ) generates clock signals P 0  to P 7  and CLK and signals EN, Ssel, and CTL on the basis of a mode signal Smode supplied from the processor  61 . 
     (Receiving Device  130 ) 
     The receiving device  130  includes receivers  131  to  134  and a processor  135  as illustrated in  FIG. 37A . The receiver  131  receives a signal SIG 1 ; the receiver  132  receives a signal SIG 2 ; the receiver  133  receives a signal SIG 3 ; and the receiver  134  receives a signal SIG 4 . The receivers  131  to  134  have the same configuration as the receiver  31  ( FIG. 9 ) according to the first embodiment. The processor  135  performs a predetermined process on the basis of received results of the receivers  131  to  134 . 
     (Receiving Device  140 ) 
     The receiving device  140  includes receivers  141  and  142  and a processor  143  as illustrated in  FIG. 37B . The receiver  141  receives signals SIG 1 P and SIG 1 N; and the receiver  142  receives signals SIG 2 P and SIG 2 N. The receivers  141  and  142  have the same configuration as the receiver  41  ( FIG. 10 ) according to the first embodiment. The processor  143  performs a predetermined process on the basis of received results of the receivers  141  and  142 . 
     (Receiving Device  150 ) 
     The receiving device  150  includes a receiver  151  and a processor  152  as illustrated in  FIG. 37C . 
     The receiver  151  receives signals SIGA, SIGB, and SIGC. 
       FIG. 45  illustrates a configuration example of the receiver  151 . The receiver  151  includes resistance elements  154  to  156  and amplifiers  157  to  159 . 
     The resistance elements  154  to  156  serve as a terminating resistance in the communication system  2 C. One end of the resistance element  154  is coupled to the input terminal TinA, a positive input terminal of the amplifier  157 , and a negative input terminal of the amplifier  159 , and the other end is coupled to the other ends of the resistance elements  155  and  156 . One end of the resistance element  155  is coupled to the input terminal TinB, a positive input terminal of the amplifier  158 , and a negative input terminal of the amplifier  157 , and the other end is coupled to the other ends of the resistance elements  154  and  156 . One end of the resistance element  156  is coupled to the input terminal TinC, a positive input terminal of the amplifier  159 , and a negative input terminal of the amplifier  158 , and the other end is coupled to the other ends of the resistance elements  154  and  155 . Respective resistance values of the resistance elements  154  to  156  are about 50[Ω] in this example. 
     The positive input terminal of the amplifier  157  is coupled to the negative input terminal of the amplifier  159 , one end of the resistance element  154 , and the input terminal TinA, and the negative input terminal is coupled to the positive input terminal of the amplifier  158 , one end of the resistance element  155 , and the input terminal TinB. The positive input terminal of the amplifier  158  is coupled to the negative input terminal of the amplifier  157 , one end of the resistance element  155 , and the input terminal TinB, and the negative input terminal is coupled to the positive input terminal of the amplifier  159 , one end of the resistance element  156 , and the input terminal TinC. The positive input terminal of the amplifier  159  is coupled to the negative input terminal of the amplifier  158 , one end of the resistance element  156 , and the input terminal TinC, and the negative input terminal is coupled to the positive input terminal of the amplifier  157 , one end of the resistance element  154 , and the input terminal TinA. Further, the amplifiers  157  to  159  supply their output signal to the processor  152 . 
       FIG. 46  illustrates an operation example of the receiver  151 . In this example, a signal SIGA is the high-level voltage VH, and a signal SIGB is the low-level voltage VL. In this case, a current Iin flows into the input terminal TinA, the resistance element  154 , the resistance element  155 , and the input terminal TinB in this order. As a result, a signal SIGC at the input terminal TinC becomes the medium-level voltage VM. Further, the positive input terminal of the amplifier  157  is supplied the high-level voltage VH, and the negative input terminal is supplied the low-level voltage VL, and then the amplifier  157  outputs “1”. Furthermore, the positive input terminal of the amplifier  158  is supplied the low-level voltage VL, and the negative input terminal is supplied the medium-level voltage VM, and then the amplifier  158  outputs “0”. Moreover, the positive input terminal of the amplifier  159  is supplied the medium-level voltage VM, and the negative input terminal is supplied the high-level voltage VH, and then the amplifier  159  outputs “0”. 
     The processor  152  performs a predetermined process on the basis of a received result of the receiver  151 . 
     Here, the plurality of encoders  29 A to  29 H correspond to a specific example of an “encoder unit” in the present disclosure. The plurality of serializers  28 A to  28 H correspond to a specific example of the “serializer unit” in the present disclosure. The operation mode MC corresponds to a specific example of a “third operation mode” in the present disclosure. 
     (Operation Mode MA) 
     In a case where the transmitting device  60  is applied to the communication system  2 A ( FIG. 37A ), the transmitting device  60  operates in the operation mode MA (single-phase mode). In the operation mode MA, the transmitting device  60  transmits data to the receiving device  130  by using signals SIG 1  to SIG 4 . 
     The processor  61  generates signals DI 10  to DI 17 , DI 20  to DI 27 , DI 30  to DI 37 , and DI 40  to DI 47 . Here, for example, the signal DI 10  includes signals DI 10 P and DI 10 N. Further, the processor  61  supplies the signals DI 10 , DI 12 , DI 14 , and DI 16  to the serializer  28 A and the signals DI 11 , DI 13 , DI 15 , and DI 17  to the serializer  28 C. Furthermore, the processor  61  supplies the signals DI 20 , DI 22 , DI 24 , and DI 26  to the serializer  28 B and the signals DI 21 , DI 23 , DI 25 , and DI 27  to the serializer  28 D. Moreover, the processor  61  supplies the signals DI 30 , DI 32 , DI 34 , and DI 36  to the serializer  28 E and the signals DI 31 , DI 33 , DI 35 , and DI 37  to the serializer  28 G. Furthermore, the processor  61  supplies the signals DI 40 , DI 42 , DI 44 , and DI 46  to the serializer  28 F and the signals DI 41 , DI 43 , DI 45 , and DI 47  to the serializer  28 H. The operations of the serializers  28 A to  28 H are the same as in the case of the first embodiment. 
     In the operation mode MA, the controller  65  sets a signal EN to low-level “0” on the basis of a mode signal Smode. Accordingly, as illustrated in  FIG. 43 , each encoder  29  outputs the same signal as a signal at the input terminal in 1  from the output terminal out 1 , and outputs an inverted signal of the signal at the input terminal in 1  from the output terminal out 2 . Specifically, for example, the encoder  29 A outputs the same signal as the signal S 28 A as a signal S 29 AP, and outputs an inverted signal of the signal S 28 A as a signal S 29 AN. The same applies to the encoders  29 B to  29 H. The operations of the multiplexers  22 A to  22 H, the selectors  23 A to  23 H, and the drivers  24 A to  24 D are the same as in the case of the first embodiment. 
     In this way, in the operation mode MA, the transmitting device  60  transmits data to the receiving device  130  by using signals SIG 1  to SIG 4 , as with the transmitting device  10  according to the first embodiment. 
     (Operation Mode MB) 
     In a case where the transmitting device  60  is applied to the communication system  2 B ( FIG. 37B ), the transmitting device  60  operates in the operation mode MB (differential mode). In the operation mode MB, the transmitting device  60  transmits data to the receiving device  140  by using signals SIG 1 P and SIG 1 N and signals SIG 2 P and SIG 2 N. 
     In the same manner as in the operation mode MA, the processor  61  generates signals DI 10  to DI 17 , DI 20  to DI 27 , DI 30  to DI 37 , and DI 40  to DI 47 , and supplies these signals to the serializers  28 A to  28 H. The operations of the serializers  28 A to  28 H are the same as in the case of the first embodiment. 
     In the operation mode MB, the controller  65  sets a signal EN to low-level “0” on the basis of a mode signal Smode. Accordingly, as illustrated in  FIG. 43 , each encoder  29  outputs the same signal as a signal at the input terminal in 1  from the output terminal out 1 , and outputs an inverted signal of the signal at the input terminal in 1  from the output terminal out 2 . Specifically, for example, the encoder  29 A outputs the same signal as the signal S 28 A as a signal S 29 AP, and outputs an inverted signal of the signal S 28 A as a signal S 29 AN. The same applies to the encoders  29 B to  29 H. The operations of the multiplexers  22 A to  22 H, the selectors  23 A to  23 H, and the drivers  24 A to  24 D are the same as in the case of the first embodiment. 
     In this way, in the operation mode MB, the transmitting device  60  transmits data to the receiving device  140  by using signals SIG 1 P and SIG 1 N and signals SIG 2 P and SIG 2 N, as with the transmitting device  10  according to the first embodiment. 
     (Operation Mode MC) 
     In a case where the transmitting device  60  is applied to the communication system  2 C ( FIG. 37C ), the transmitting device  60  operates in the operation mode MC (three-phase mode). In the operation mode MC, the transmitting device  60  transmits data to the receiving device  150  by using signals SIGA to SIGC. 
     In the operation mode MC, the processor  61  generates signals DI 10  to DI 17 , DI 20  to DI 27 , and DI 30  to DI 37 . Here, for example, the signal DI 10  includes signals DI 10 P and DI 10 N. Further, the processor  61  supplies the signals DI 10 , DI 12 , DI 14 , and DI 16  to the serializer  28 A and the signals DI 11 , DI 13 , DI 15 , and DI 17  to the serializer  28 C. Furthermore, the processor  61  supplies the signals DI 20 , DI 22 , DI 24 , and DI 26  to the serializer  28 B and the signals DI 21 , DI 23 , DI 25 , and DI 27  to the serializer  28 D. Moreover, the processor  61  supplies the signals DI 30 , DI 32 , DI 34 , and DI 36  to the serializer  28 E and the signals DI 31 , DI 33 , DI 35 , and DI 37  to the serializer  28 G. The operations of the serializers  28 A to  28 H are the same as in the case of the operation modes MA and MB. 
     In the operation mode MC, the controller  65  sets a signal EN to high-level “1” on the basis of a mode signal Smode. Accordingly, each encoder  29  operates as illustrated in  FIG. 43 . Specifically, for example, in a case where the signals S 28 A and S 28 E are “1” and “0”, respectively, the encoder  29 A sets the signal S 29 AP to “1” and the signal S 29 AN to “0”; in a case where the signals S 28 A and S 28 E are “0” and “1”, respectively, the encoder  29 A sets the signal S 29 AP to “0” and the signal S 29 AN to “1”; and in a case where the signals S 28 A and S 28 E are equal to each other, the encoder  29 A sets both of the signals S 29 AP and S 29 AN to “0”. The same applies to the encoders  29 B to  29 H. 
       FIGS. 47A and 47B  illustrate the flow of signals in the operation mode MC. In  FIG. 47A , bold solid lines indicate the flow of signals related to a signal SIGA, and bold dashed lines indicate the flow of signals related to a signal SIGB. In  FIG. 47B , bold dashed-dotted lines indicate the flow of signals related to a signal SIGC. 
     The multiplexer  22 A ( FIG. 47A ) alternately selects one of the signals S 29 AP and S 29 CP on the basis of a clock signal CLK, and outputs the selected signal as a signal S 22 A. The multiplexer  22 B alternately selects one of the signals S 29 AN and S 29 CN on the basis of a clock signal CLK, and outputs the selected signal as a signal S 22 B. On the basis of a signal Ssel, the selector  23 A selects the signal S 22 A in the operation mode MC, and outputs the selected signal S 22 A as a signal S 23 A. On the basis of a signal Ssel, the selector  23 B selects the signal S 22 B in the operation mode MC, and outputs the selected signal S 22 B as a signal S 23 B. As a result, the driver  24 A operates on the basis of the signals S 22 A and S 22 B. 
     Likewise, the multiplexer  22 C alternately selects one of the signals S 29 BP and S 29 DP on the basis of a clock signal CLK, and outputs the selected signal as a signal S 22 C. The multiplexer  22 D alternately selects one of the signals S 29 BN and S 29 DN on the basis of a clock signal CLK, and outputs the selected signal as a signal S 22 D. On the basis of a signal Ssel, the selector  23 C selects the signal S 22 C in the operation mode MC, and outputs the selected signal S 22 C as a signal S 23 C. On the basis of a signal Ssel, the selector  23 D selects the signal S 22 D in the operation mode MC, and outputs the selected signal S 22 D as a signal S 23 D. As a result, the driver  24 B operates on the basis of the signals S 22 C and S 22 D. 
     Likewise, the multiplexer  22 E ( FIG. 47B ) alternately selects one of the signals S 29 EP and S 29 GP on the basis of a clock signal CLK, and outputs the selected signal as a signal S 22 E. The multiplexer  22 F alternately selects one of the signals S 29 EN and S 29 GN on the basis of a clock signal CLK, and outputs the selected signal as a signal S 22 F. On the basis of a signal Ssel, the selector  23 E selects the signal S 22 E in the operation mode MC, and outputs the selected signal S 22 E as a signal S 23 E. On the basis of a signal Ssel, the selector  23 F selects the signal S 22 F in the operation mode MC, and outputs the selected signal S 22 F as a signal S 23 F. As a result, the driver  24 C operates on the basis of the signals S 22 E and S 22 F. 
       FIG. 48  illustrates an operation example of the transmitter  62  in the operation mode MC.  FIGS. 49A and 49B  illustrate the flow of signals in a certain operation state in the operation mode MC. In examples of  FIGS. 49A and 49B , the multiplexer  22 A selects the signal S 29 AP; the multiplexer  22 B selects the signal S 29 AN; the multiplexer  22 C selects the signal S 29 BP; the multiplexer  22 D selects the signal S 29 BN; the multiplexer  22 E selects the signal S 29 EP; and the multiplexer  22 F selects the signal S 29 EN. 
     The encoder  29 A ( FIG. 49A ) generates signals S 29 AP and S 29 AN on the basis of the signals S 28 A and S 28 E and a signal EN. The encoder  29 B generates signals S 29 BP and S 29 BN on the basis of the signals S 28 B and S 28 A and a signal EN. The encoder  29 E ( FIG. 49B ) generates signals S 29 EP and S 29 EN on the basis of the signals S 28 E and S 28 B and a signal EN. 
     For example, in a case where the signals S 28 A, S 28 B, and S 28 E are “1”, “0”, and “0”, respectively, as illustrated in  FIG. 43 , the encoder  29 A sets the signals S 29 AP and S 29 AN to “1” and “0”, respectively; the encoder  29 B sets the signals S 29 BP and S 29 BN to “0” and “1”, respectively; and the encoder  29 E sets the signals S 29 EP and S 29 EN to “0” and “0”, respectively. As a result, as illustrated in  FIG. 48 , the output signal S 22 A of the multiplexer  22 A becomes “1”; the output signal S 22 B of the multiplexer  22 B becomes “0”; the output signal S 22 C of the multiplexer  22 C becomes “0”; the output signal S 22 D of the multiplexer  22 D becomes “1”; the output signal S 22 E of the multiplexer  22 E becomes “0”; and the output signal S 22 F of the multiplexer  22 F becomes “0”. 
     At this time, in the driver  24 A ( FIG. 49A ), the transistors  92  in the sub-drivers AA 1  to AAM and AB 1  to ABN go into on state, and the transistors  93  in the sub-drivers AA 1  to AAM and AB 1  to ABN go into off state. As a result, the driver  24 A sets the voltage at the output terminal Tout 1  to the high-level voltage VH and the output impedance to about 50[Ω]. 
     Furthermore, in the driver  24 B, the transistors  93  in the sub-drivers BA 1  to BAM and BB 1  to BBN go into on state, and the transistors  92  in the sub-drivers BA 1  to BAM and BB 1  to BBN go into off state. As a result, the driver  24 B sets the voltage at the output terminal Tout 2  to the low-level voltage VL and the output impedance to about 50[Ω]. 
     Moreover, in the driver  24 C ( FIG. 49B ), the transistors  92  and  93  in the sub-drivers CA 1  to CAM and CB 1  to CBN go into off state. As a result, the driver  24 C sets the output impedance to high impedance. At this time, in the receiver  151  of the receiving device  150 , the voltage at the input terminal TinC becomes the medium-level voltage VM as illustrated in  FIG. 46 . 
     In this way, the transmitter  62  sets the signal SIGA to the high-level voltage VH, the signal SIGB to the low-level voltage VL, and the signal SIGC to the medium-level voltage VM. As a result, the transmitting device  60  transmits the symbol “+x” to the receiving device  150 . It is to be noted that the in this example, there is described a case where the transmitting device  60  transmits the symbol “+x”; however, the same applies to a case of transmitting other symbols. 
     In this way, in the operation mode MC, the transmitting device  60  transmits data to the receiving device  150  by using signals SIGA, SIGB, and SIGC. 
     As described above, in the present embodiment, the three operation modes MA, MB, and MC are provided, which makes it possible to transmit data to a receiving device by using a single-phase signal, a differential signal, or a three-phase signal; therefore, it is possible to implement various interfaces. 
     Modification Example 2-1 
     In the above-described embodiment, the encoders  29  are provided in the preceding stage of the multiplexers  22 ; however, it is not limited to this. Instead of this, for example, encoders may be provided in the subsequent stage of the multiplexers  22 . This modification example is described in detail below. 
       FIGS. 50A and 50B  illustrate respective configuration examples of transmitting circuit units  63 A and  63 B of a transmitter  63  according to the present modification example. The transmitting circuit unit  63 A includes four serializers  21  (the serializers  21 A,  21 B,  21 C, and  21 D), four multiplexers  22  (the multiplexers  22 A,  22 B,  22 C, and  22 D), four encoders  64  (encoders  64 A,  64 B,  64 C, and  64 D), four selectors  23  (the selectors  23 A,  23 B,  23 C, and  23 D), and two drivers  24  (the drivers  24 A and  24 B). The transmitting circuit unit  63 B includes four serializers  21  (serializers  21 E,  21 F,  21 G, and  21 H), four multiplexers  22  (the multiplexers  22 E,  22 F,  22 G, and  22 H), four encoders  64  (encoders  64 E,  64 F,  64 G, and  64 H), four selectors  23  (the selectors  23 E,  23 F,  23 G, and  23 H), and two drivers  24  (the drivers  24 C and  24 D). 
       FIG. 51  illustrates respective signal paths of signals S 22 A to S 22 H generated by the multiplexers  22 A to  22 H. The multiplexer  22 A supplies the signal S 22 A to the encoders  64 A and  64 C. The multiplexer  22 B supplies the signal S 22 B to the encoders  64 B and  64 D. The multiplexer  22 C supplies the signal S 22 C to the encoders  64 C and  64 E. The multiplexer  22 D supplies the signal S 22 D to the encoders  64 D and  64 F. The multiplexer  22 E supplies the signal S 22 E to the encoders  64 A and  64 E. The multiplexer  22 F supplies the signal S 22 F to the encoders  64 B and  64 F. The multiplexer  22 G supplies the signal S 22 G to the encoder  64 G. The multiplexer  22 H supplies the signal S 22 H to the encoder  64 H. 
     The encoder  64 A ( FIG. 50A ) generates a signal S 64 A on the basis of the signals S 22 A and S 22 E and a signal EN. The encoder  64 A has the input terminals in 1 , in 2 , and CEN and the output terminal out 1 . The input terminal in 1  of the encoder  64 A is supplied with the signal S 22 A, and the input terminal in 2  is supplied with the signal S 22 E, and the input terminal CEN is supplied with the signal EN. Then, the encoder  64 A outputs the signal S 64 A from the output terminal out 1 . 
     Likewise, the encoder  64 B generates a signal S 64 B on the basis of the signals S 22 B and S 22 F and a signal EN. The encoder  64 C generates a signal S 64 C on the basis of the signals S 22 C and S 22 A and a signal EN. The encoder  64 D generates a signal S 64 D on the basis of the signals S 22 D and S 22 B and a signal EN. The encoder  64 E ( FIG. 50B ) generates a signal S 64 E on the basis of the signals S 22 E and S 22 C and a signal EN. The encoder  64 F generates a signal S 64 F on the basis of the signals S 22 F and S 22 D and a signal EN. The encoder  64 G generates a signal S 64 G on the basis of the signal S 22 G and a signal EN. The encoder  64 H generates a signal S 64 H on the basis of the signal S 22 H and a signal EN. 
       FIG. 52  illustrates a configuration example of the encoder  64 . The encoder  64  includes a selector  205 , an exclusive OR circuit  206 , and an AND circuit  207 . The selector  205  selects an inverted signal of a signal at the input terminal in 1  in a case where the signal EN at the input terminal CEN is low level, and selects a signal at the input terminal in 2  in a case where the signal EN at the input terminal CEN is high level, and outputs the selected signal. The exclusive OR circuit  206  finds an exclusive logical sum of the signal at the input terminal in 1  and the output signal of the selector  205 , and outputs its result. The AND circuit  207  finds a logical product of the signal at the input terminal in 1  and the output signal of the exclusive OR circuit  206 , and outputs its result from the output terminal out 1 . 
       FIG. 53  illustrates an operation example of the encoder  64 . In the operation modes MA and MB, the signal EN at the input terminal CEN becomes low level “0”. In this case, the encoder  64  outputs the same signal as the signal at the input terminal in 1  from the output terminal out 1 . On the other hand, in the operation mode MC, the signal EN at the input terminal CEN becomes high level “1”. In this case, in a case where the signals at the input terminals in 1  and in 2  are “1” and “0”, respectively, the encoder  64  sets the signals at the output terminal out 1  to high level “1”; in other cases, the encoder  64  sets the signal at the output terminal out 1  to low level “0”. 
     It is to be noted that in this example, the encoder  64  is configured as illustrated in  FIG. 52 ; however, it is not limited to this. For example, an encoder (an encoder  129 ) may be configured as illustrated in  FIG. 54 . This encoder  129  includes an inverted AND circuit  226  and an AND circuit  227 . The inverted AND circuit  226  finds an inverted logical product of the signal at the input terminal in 1 , the signal EN at the input terminal CEN, and the signal at the input terminal in 2 , and outputs its result. The AND circuit  227  finds a logical product of the signal at the input terminal in 1  and the output signal of the inverted AND circuit  226 , and outputs its result from the output terminal out 1 . The operation of this encoder  127  is the same as the operation of the encoder  64  ( FIG. 53 ). 
     Here, the encoders  64 A to  64 H correspond to a specific example of the “encoder unit” in the present disclosure. 
     On the basis of a signal Ssel, the selector  23 A ( FIG. 50A ) selects the signal S 64 A in a case where the operation mode is the operation mode MA (single-phase mode) or the operation mode MC (three-phase mode), or selects the signal S 64 D in a case where the operation mode is the operation mode MB (differential mode), and outputs the selected signal as a signal S 23 A. On the basis of a signal Ssel, the selector  23 B selects the signal S 64 B in a case where the operation mode is the operation mode MA or the operation mode MC, or selects the signal S 64 C in a case where the operation mode is the operation mode MB, and outputs the selected signal as a signal S 23 B. On the basis of a signal Ssel, the selector  23 C selects the signal S 64 C in a case where the operation mode is the operation mode MA or the operation mode MC, or selects the signal S 64 B in a case where the operation mode is the operation mode MB, and outputs the selected signal as a signal S 23 C. On the basis of a signal Ssel, the selector  23 D selects the signal S 64 D in a case where the operation mode is the operation mode MA or the operation mode MC, or selects the signal S 64 A in a case where the operation mode is the operation mode MB, and outputs the selected signal as a signal S 23 D. On the basis of a signal Ssel, the selector  23 E ( FIG. 50B ) selects the signal S 64 E in a case where the operation mode is the operation mode MA or the operation mode MC, or selects the signal S 64 H in a case where the operation mode is the operation mode MB, and outputs the selected signal as a signal S 23 E. On the basis of a signal Ssel, the selector  23 F selects the signal S 64 F in a case where the operation mode is the operation mode MA or the operation mode MC, or selects the signal S 64 G in a case where the operation mode is the operation mode MB, and outputs the selected signal as a signal S 23 F. On the basis of a signal Ssel, the selector  23 G selects the signal S 64 G in a case where the operation mode is the operation mode MA or the operation mode MC, or selects the signal S 64 F in a case where the operation mode is the operation mode MB, and outputs the selected signal as a signal S 23 G. On the basis of a signal Ssel, the selector  23 H selects the signal S 64 H in a case where the operation mode is the operation mode MA or the operation mode MC, or selects the signal S 64 E in a case where the operation mode is the operation mode MB, and outputs the selected signal as a signal S 23 H. 
     The driver  24 A ( FIG. 50A ) sets a voltage at the output terminal Tout 1  on the basis of the signals S 64 A, S 64 B, S 23 A, and S 23 B and a signal CTL. The driver  24 B sets a voltage at the output terminal Tout 2  on the basis of the signals S 23 C, S 23 D, S 64 C, and S 64 D and a signal CTL. The driver  24 C ( FIG. 50B ) sets a voltage at the output terminal Tout 3  on the basis of the signals S 64 E, S 64 F, S 23 E, and S 23 F and a signal CTL. The driver  24 D sets a voltage at the output terminal Tout 4  on the basis of the signals S 23 G, S 23 H, S 64 G, and S 64 H and a signal CTL. 
     For example, in a case where the signals S 22 A, S 22 B, S 22 C, S 22 D, S 22 E, and S 22 F are “1”, “0”, “0”, “1”, “0”, and “1”, respectively, as illustrated in  FIG. 53 , the encoder  64 A sets the signal S 64 A to “1”; the encoder  64 B sets the signal S 64 B to “0”; the encoder  64 C sets the signal S 64 C to “0”; the encoder  64 D sets the signal S 64 D to “1”; the encoder  64 E sets the signal S 64 E to “0”; and the encoder  64 F sets the signal S 64 F to “0”. 
     At this time, in the driver  24 A ( FIG. 50A ), the transistors  92  in the sub-drivers AA 1  to AAM and AB 1  to ABN go into on state, and the transistors  93  in the sub-drivers AA 1  to AAM and AB 1  to ABN go into off state. As a result, the driver  24 A sets the voltage at the output terminal Tout 1  to the high-level voltage VH and the output impedance to about 50[Ω]. 
     Furthermore, in the driver  24 B, the transistors  93  in the sub-drivers BA 1  to AAM and BB 1  to BBN go into on state, and the transistors  92  in the sub-drivers BA 1  to BAM and BB 1  to BBN go into off state. As a result, the driver  24 B sets the voltage at the output terminal Tout 2  to the low-level voltage VL and the output impedance to about 50[Ω]. 
     Moreover, in the driver  24 C ( FIG. 50B ), the transistors  92  and  93  in the sub-drivers CA 1  to CAM and CB 1  to CBN go into off state. As a result, the driver  24 C sets the output impedance to high impedance. At this time, in the receiver  151  of the receiving device  150 , the voltage at the input terminal TinC becomes the medium-level voltage VM as illustrated in  FIG. 46 . 
     Modification Example 2-2 
     In the above-described embodiment, the serializers  28 A to  28 H having the same configuration as those in  FIG. 3  are used; however, it is not limited to this. A modification example is described in detail below. 
       FIG. 55  illustrates a configuration example of a transmitter  67  according to the present modification example. The transmitter  67  includes transmitting circuit units  67 A and  67 B and the controller  65 .  FIG. 56A  illustrates a configuration example of the transmitting circuit unit  67 A, and  FIG. 56B  illustrates a configuration example of the transmitting circuit unit  67 B. The transmitting circuit unit  67 A includes four serializers  68  (serializers  68 A,  68 B,  68 C, and  68 D), four encoders  29  (the encoders  29 A,  29 B,  29 C, and  29 D), four multiplexers  22  (the multiplexers  22 A,  22 B,  22 C, and  22 D), four selectors  23  (the selectors  23 A,  23 B,  23 C, and  23 D), and two drivers  24  (the drivers  24 A and  24 B). The transmitting circuit unit  67 B includes four serializers  68  (serializers  68 E,  68 F,  68 G, and  68 H), four encoders  29  (the encoders  29 E,  29 F,  29 G, and  29 H), four multiplexers  22  (the multiplexers  22 E,  22 F,  22 G, and  22 H), four selectors  23  (the selectors  23 E,  23 F,  23 G, and  23 H), and two drivers  24  (the drivers  24 C and  24 D). 
     The serializer  68 A ( FIG. 56A ) generates signals S 68 AP and S 68 AN on the basis of clock signals P 0 , P 2 , P 4 , and P 6  and signals DI 10 P, DI 10 N, DI 12 P, DI 12 N, DI 14 P, DI 14 N, DI 16 P, and DI 16 N. The serializer  68 B generates signals S 68 BP and S 68 BN on the basis of clock signals P 0 , P 2 , P 4 , and P 6  and signals DI 20 P, DI 20 N, DI 22 P, DI 22 N, DI 24 P, DI 24 N, DI 26 P, and DI 26 N. The serializer  68 C generates signals S 68 CP and S 68 CN on the basis of clock signals P 1 , P 3 , P 5 , and P 7  and signals DI 11 P, DI 11 N, DI 13 P, DI 13 N, DI 15 P, DI 15 N, DI 17 P, and DI 17 N. The serializer  68 D generates signals S 68 DP and S 68 DN on the basis of clock signals P 1 , P 3 , P 5 , and P 7  and signals DI 21 P, DI 21 N, DI 23 P, DI 23 N, DI 25 P, DI 25 N, DI 27 P, and DI 27 N. The serializer  68 E ( FIG. 56B ) generates signals S 68 EP and S 68 EN on the basis of clock signals P 0 , P 2 , P 4 , and P 6  and signals DI 30 P, DI 30 N, DI 32 P, DI 32 N, DI 34 P, DI 34 N, DI 36 P, and DI 36 N. The serializer  68 F generates signals S 68 FP and S 68 FN on the basis of clock signals P 0 , P 2 , P 4 , and P 6  and signals DI 40 P, DI 40 N, DI 42 P, DI 42 N, DI 44 P, DI 44 N, DI 46 P, and DI 46 N. The serializer  68 G generates signals S 68 GP and S 68 GN on the basis of clock signals P 1 , P 3 , P 5 , and P 7  and signals DI 31 P, DI 31 N, DI 33 P, DI 33 N, DI 35 P, DI 35 N, DI 37 P, and DI 37 N. The serializer  68 H generates signals S 68 HP and S 68 HN on the basis of clock signals P 1 , P 3 , P 5 , and P 7  and signals DI 41 P, DI 41 N, DI 43 P, DI 43 N, DI 45 P, DI 45 N, DI 47 P, and DI 47 N. 
       FIG. 57  illustrates a configuration example of the serializer  68 A. The serializer  68 A includes transistors M 1  to M 18  and inverted AND circuits  231  to  234 . The transistors M 1  to M 10  and M 13  to M 16  are N-channel MOS type FETs, and the transistors M 11 , M 12 , M 17 , and M 18  are P-channel MOS type FETs. The serializer  68 A is the one that the inverted AND circuits  231  to  234  and the transistors M 13  to M 18  are added to the serializer  21 A ( FIG. 3 ). 
     The inverted AND circuit  231  finds an inverted logical product of the signals DI 10 P and DI 10 N, and outputs its result. The inverted AND circuit  232  finds an inverted logical product of the signals DI 12 P and DI 12 N, and outputs its result. The inverted AND circuit  233  finds an inverted logical product of the signals DI 14 P and DI 14 N, and outputs its result. The inverted AND circuit  234  finds an inverted logical product of the signals DI 16 P and DI 16 N, and outputs its result. 
     A source of the transistor M 13  is supplied with the output signal of the inverted AND circuit  231 , and a gate is supplied with the clock signal P 0 , and a drain is coupled to drains of the transistors M 14  to M 16  and gates of the transistors M 17  and M 18 . A source of the transistor M 14  is supplied with the output signal of the inverted AND circuit  232 , and a gate is supplied with the clock signal P 2 , and the drain is coupled to the drains of the transistors M 13 , M 15 , and M 16  and the gates of the transistors M 17  and M 18 . A source of the transistor M 15  is supplied with the output signal of the inverted AND circuit  233 , and a gate is supplied with the clock signal P 4 , and the drain is coupled to the drains of the transistors M 13 , M 14 , and M 16  and the gates of the transistors M 17  and M 18 . A source of the transistor M 16  is supplied with the output signal of the inverted AND circuit  234 , and a gate is supplied with the clock signal P 6 , and the drain is coupled to the drains of the transistors M 13  to M 15  and the gates of the transistors M 17  and M 18 . A source of the transistor M 17  is supplied with the power supply voltage VDD, and the gate is coupled to the drains of the transistors M 13  to M 16  and the gate of the transistor M 18 , and the drain is coupled to the drains of the transistors M 9  and M 11  and the gate of the transistor M 12 . A source of the transistor M 18  is supplied with the power supply voltage VDD, and the gate is coupled to the drains of the transistors M 13  to M 16  and the gate of the transistor M 17 , and the drain is coupled to the drains of the transistors M 10  and M 12  and the gate of the transistor M 11 . The serializer  68 A outputs the signal S 68 AP from the drains of the transistors M 9 , M 11 , and M 17 , and outputs the signal S 68 AN from the drains of the transistors M 10 , M 12 , and M 18 . 
     With this configuration, for example, in a period in which the clock signal P 0  is high level, in a case where the signals DI 10 P and DI 10 N are different from each other, the serializer  68 A operates as with the serializer  21 A; in a case where the signals DI 10 P and DI 10 N are both high level, the serializer  68 A sets both of the signals S 68 AP and S 68 AN to high level. Likewise, in a period in which the clock signal P 2  is high level, in a case where the signals DI 12 P and DI 12 N are different from each other, the serializer  68 A operates as with the serializer  21 A; in a case where the signals DI 12 P and DI 12 N are both high level, the serializer  68 A sets both of the signals S 68 AP and S 68 AN to high level. Furthermore, in a period in which the clock signal P 4  is high level, in a case where the signals DI 14 P and DI 14 N are different from each other, the serializer  68 A operates as with the serializer  21 A; in a case where the signals DI 14 P and DI 14 N are both high level, the serializer  68 A sets both of the signals S 68 AP and S 68 AN to high level. Moreover, in a period in which the clock signal P 6  is high level, in a case where the signals DI 16 P and DI 16 N are different from each other, the serializer  68 A operates as with the serializer  21 A; in a case where the signals DI 16 P and DI 16 N are both high level, the serializer  68 A sets both of the signals S 68 AP and S 68 AN to high level. 
     In the operation modes MA and MB, the processor  61  generates signals DI 10  to DI 17 , DI 20  to DI 27 , DI 30  to DI 37 , and DI 40  to DI 47 . Here, for example, the signal DI 10  includes signals DI 10 P and DI 10 N. Further, the processor  61  supplies the signals DI 10 , DI 12 , DI 14 , and DI 16  to the serializer  68 A and the signals DI 11 , DI 13 , DI 15 , and DI 17  to the serializer  68 C. Furthermore, the processor  61  supplies the signals DI 20 , DI 22 , DI 24 , and DI 26  to the serializer  68 B and the signals DI 21 , DI 23 , DI 25 , and DI 27  to the serializer  68 D. Moreover, the processor  61  supplies the signals DI 30 , DI 32 , DI 34 , and DI 36  to the serializer  68 E and the signals DI 31 , DI 33 , DI 35 , and DI 37  to the serializer  68 G. Furthermore, the processor  61  supplies the signals DI 40 , DI 42 , DI 44 , and DI 46  to the serializer  68 F and the signals DI 41 , DI 43 , DI 45 , and DI 47  to the serializer  68 H. 
     Furthermore, in the operation mode MC, the processor  61  generates data D 10  to D 17 , D 20  to D 27 , and D 30  to D 37 . Further, the processor  61  supplies the generated data D 10  to D 17 , D 20  to D 27 , and D 30  to D 37  to the serializers  68 A to  68 E and  68 G as follows. 
       FIG. 58  illustrates an operation of supplying the data D 10  to D 17 , D 20  to D 27 , and D 30  to D 37  generated by the processor  61  to the serializers  68 A to  68 E and  68 G. The processor  61  supplies the data D 10 , D 12 , D 14 , and D 16  to the serializer  68 A by using signals DI 10 P, DI 12 P, DI 14 P, and DI 16 P, and also supplies the data D 10 , D 12 , D 14 , and D 16  to the serializer  68 B by using signals DI 20 N, DI 22 N, DI 24 N, and DI 26 N. Furthermore, the processor  61  supplies the data D 11 , D 13 , D 15 , and D 17  to the serializer  68 C by using signals DI 11 P, DI 13 P, DI 15 P, and DI 17 P, and also supplies the data D 11 , D 13 , D 15 , and D 17  to the serializer  68 D by using signals DI 21 N, DI 23 N, DI 25 N, and DI 27 N. Moreover, the processor  61  supplies the data D 20 , D 22 , D 24 , and D 26  to the serializer  68 B by using signals DI 20 P, DI 22 P, DI 24 P, and DI 26 P, and also supplies the data D 20 , D 22 , D 24 , and D 26  to the serializer  68 E by using signals DI 30 N, DI 32 N, DI 34 N, and DI 36 N. Furthermore, the processor  61  supplies the data D 21 , D 23 , D 25 , and D 27  to the serializer  68 D by using signals DI 21 P, DI 23 P, DI 25 P, and DI 27 P, and also supplies the data D 21 , D 23 , D 25 , and D 27  to the serializer  68 G by using signals DI 31 N, DI 33 N, DI 35 N, and DI 37 N. Moreover, the processor  61  supplies the data D 30 , D 32 , D 34 , and D 36  to the serializer  68 E by using signals DI 30 P, DI 32 P, DI 34 P, and DI 36 P, and also supplies the data D 30 , D 32 , D 34 , and D 36  to the serializer  68 A by using signals DI 10 N, DI 12 N, DI 14 N, and DI 16 N. Furthermore, the processor  61  supplies the data D 31 , D 33 , D 35 , and D 37  to the serializer  68 G by using signals DI 31 P, DI 33 P, DI 35 P, and DI 37 P, and also supplies the data D 31 , D 33 , D 35 , and D 37  to the serializer  68 C by using signals DI 11 N, DI 13 N, DI 15 N, and DI 17 N. 
     Accordingly, for example, the signals DI 10 P, DI 12 P, DI 14 P, and DI 16 P and the signals SI 10 N, DI 12 N, DI 14 N, and DI 16 N that are supplied to the serializer  68 A may become uncorrelated signals. Specifically, the signals DI 10 P and DI 10 N do not necessarily become signals that are inverted from each other; the signals DI 12 P and DI 12 N do not necessarily become signals that are inverted from each other; the signals DI 14 P and DI 14 N do not necessarily become signals that are inverted from each other; and the signals DI 16 P and DI 16 N do not necessarily become signals that are inverted from each other. The same applies to the serializers  68 B to  68 H. 
     The operations of supplying the data D 10  to D 17 , D 20  to D 27 , and D 30  to D 37  to the serializers  68 A to  68 E and  68 G illustrated in  FIG. 58  corresponds to the signal paths ( FIG. 41 ) of the signals S 28 A to S 28 H generated by the serializers  28 A to  28 H. That is, in the above-described embodiment, a three-phase signal is generated by providing the encoders  29 A to  29 H and modifying the signal paths from the serializers  28 A to  28 H to the encoders  29 A to  29 H; however, in the present modification example, a three-phase signal is generated by providing the encoders  29 A to  29 H and modifying the way to supply data to the serializers  68 A to  68 H. 
     The plurality of serializers  68 A to  68 H here correspond to a specific example of the “serializer unit” in the present disclosure. 
     The encoder  29 A ( FIG. 56A ) generates signals S 29 AP and S 29 AN on the basis of the signals S 68 AP and S 68 AN and a signal EN. The input terminal in 1  of the encoder  29 A is supplied with the signal S 68 AP, and the input terminal in 2  is supplied with the signal S 68 AN, and the input terminal CEN is supplied with the signal EN. Then, the encoder  29 A outputs the signal S 29 AP from the output terminal out 1 , and outputs the signal S 29 AN from the output terminal out 2 . 
     Likewise, the encoder  29 B generates signals S 29 BP and S 29 BN on the basis of the signals S 68 BP and S 68 BN and a signal EN. The encoder  29 C generates signals S 29 CP and S 29 CN on the basis of the signals S 68 CP and S 68 CN and a signal EN. The encoder  29 D generates signals S 29 DP and S 29 DN on the basis of the signals S 68 DP and S 68 DN and a signal EN. The encoder  29 E ( FIG. 56B ) generates signals S 29 EP and S 29 EN on the basis of the signals S 68 EP and S 68 EN and a signal EN. The encoder  29 F generates signals S 29 FP and S 29 FN on the basis of the signals S 68 FP and S 68 FN and a signal EN. The encoder  29 G generates signals S 29 GP and S 29 GN on the basis of the signals S 68 GP and S 68 GN and a signal EN. The encoder  29 H generates signals S 29 HP and S 29 HN on the basis of the signals S 68 HP and S 68 HN and a signal EN. 
     In the transmitter  67  according to the present modification example, the encoders  29  are provided in the preceding stage of the multiplexers  22 ; however, it is not limited to this. Instead of this, for example, encoders may be provided in the subsequent stage of the multiplexers  22 . A transmitter  69  according to this modification example is described in detail below. 
       FIGS. 59A and 59B  illustrate respective configuration examples of transmitting circuit units  69 A and  69 B of the transmitter  69  according to the present modification example. The transmitting circuit unit  69 A includes four serializers  68  (the serializers  68 A,  68 B,  68 C, and  68 D), four multiplexers  22  (the multiplexers  22 A,  22 B,  22 C, and  22 D), two encoders  29  (encoders  29 A and  29 B), four selectors  23  (the selectors  23 A,  23 B,  23 C, and  23 D), and two drivers  24  (the drivers  24 A and  24 B). The transmitting circuit unit  69 B includes four serializers  68  (serializers  68 E,  68 F,  68 G, and  68 H), four multiplexers  22  (the multiplexers  22 E,  22 F,  22 G, and  22 H), two encoders  29  (the encoders  29 C and  29 D), four selectors  23  (the selectors  23 E,  23 F,  23 G, and  23 H), and two drivers  24  (the drivers  24 C and  24 D). 
     The encoder  29 A ( FIG. 59A ) generates signals S 29 AP and S 29 AN on the basis of the signals S 22 A and S 22 B and a signal EN. The encoder  29 B generates signals S 29 BP and S 29 BN on the basis of the signals S 22 C and S 22 D and a signal EN. The encoder  29 C ( FIG. 59B ) generates signals S 29 CP and S 29 CN on the basis of the signals S 22 E and S 22 F and a signal EN. The encoder  29 D generates signals S 29 DP and S 29 DN on the basis of the signals S 22 G and S 22 H and a signal EN. 
     On the basis of a signal Ssel, the selector  23 A ( FIG. 59A ) selects the signal S 29 AP in a case where the operation mode is the operation mode MA (single-phase mode) or the operation mode MC (three-phase mode), or selects the signal S 29 BN in a case where the operation mode is the operation mode MB (differential mode), and outputs the selected signal as a signal S 23 A. On the basis of a signal Ssel, the selector  23 B selects the signal S 29 AN in a case where the operation mode is the operation mode MA or the operation mode MC, or selects the signal S 29 BP in a case where the operation mode is the operation mode MB, and outputs the selected signal as a signal S 23 B. On the basis of a signal Ssel, the selector  23 C selects the signal S 29 BP in a case where the operation mode is the operation mode MA or the operation mode MC, or selects the signal S 29 AN in a case where the operation mode is the operation mode MB, and outputs the selected signal as a signal S 23 C. On the basis of a signal Ssel, the selector  23 D selects the signal S 29 BN in a case where the operation mode is the operation mode MA or the operation mode MC, or selects the signal S 29 AP in a case where the operation mode is the operation mode MB, and outputs the selected signal as a signal S 23 D. On the basis of a signal Ssel, the selector  23 E ( FIG. 59B ) selects the signal S 29 CP in a case where the operation mode is the operation mode MA or the operation mode MC, or selects the signal S 29 DN in a case where the operation mode is the operation mode MB, and outputs the selected signal as a signal S 23 E. On the basis of a signal Ssel, the selector  23 F selects the signal S 29 CN in a case where the operation mode is the operation mode MA or the operation mode MC, or selects the signal S 29 DP in a case where the operation mode is the operation mode MB, and outputs the selected signal as a signal S 23 F. On the basis of a signal Ssel, the selector  23 G selects the signal S 29 DP in a case where the operation mode is the operation mode MA or the operation mode MC, or selects the signal S 29 CN in a case where the operation mode is the operation mode MB, and outputs the selected signal as a signal S 23 G. On the basis of a signal Ssel, the selector  23 H selects the signal S 29 DN in a case where the operation mode is the operation mode MA or the operation mode MC, or selects the signal S 29 CP in a case where the operation mode is the operation mode MB, and outputs the selected signal as a signal S 23 H. 
     The driver  24 A ( FIG. 59A ) sets a voltage at the output terminal Tout 1  on the basis of the signals S 29 AP, S 29 AN, S 23 A, and S 23 B and a signal CTL. The driver  24 B sets a voltage at the output terminal Tout 2  on the basis of the signals S 23 C, S 23 D, S 29 BP, and S 29 BN and a signal CTL. The driver  24 C ( FIG. 59B ) sets a voltage at the output terminal Tout 3  on the basis of the signals S 29 CP, S 29 CN, S 23 E, and S 23 F and a signal CTL. The driver  24 D sets a voltage at the output terminal Tout 4  on the basis of the signals S 23 G, S 23 H, S 29 DP, and S 29 DN and a signal CTL. 
     3. Third Embodiment 
     Subsequently, communication systems  3 A to  3 C according to a third embodiment are described. The present embodiment describes a different method in which an output terminal is set to the medium-level voltage VM in a case where communication is performed by using a signal having three voltage levels. It is to be noted that a component substantially identical to that of the communication systems  2 A to  2 C according to the above-described second embodiment is assigned the same reference numeral, and description of the component is omitted accordingly. 
     As illustrated in  FIG. 37A , the communication system  3 A includes a transmitting device  70  and the receiving device  130 . In the communication system  3 A, the transmitting device  70  uses the line  101  to transmit a signal SIG 1 , and uses the line  102  to transmit a signal SIG 2 , and uses the line  103  to transmit a signal SIG 3 , and uses the line  104  to transmit a signal SIG 4 . 
     As illustrated in  FIG. 37B , the communication system  3 B includes the transmitting device  70  and the receiving device  140 . In the communication system  3 B, the transmitting device  70  uses the lines  111  and  112  to transmit signals SIG 1 P and SIG 1 N, and uses the lines  113  and  114  to transmit signals SIG 2 P and SIG 2 N. 
     As illustrated in  FIG. 37C , the communication system  3 C includes the transmitting device  70  and the receiving device  150 . In the communication system  3 C, the transmitting device  70  uses the lines  121 ,  122 , and  123  to transmit signals SIGA, SIGB, and SIGC. 
     (Transmitting Device  70 ) 
     The transmitting device  70  includes a transmitter  72  as illustrated in  FIGS. 37A to 37C . 
     The transmitter  72  transmits data generated by the processor  61  on the basis of a mode signal Smode. Specifically, in a case where the operation mode indicated by the mode signal Smode is the operation mode MA (single-phase mode), the transmitter  72  transmits data generated by the processor  61  by using signals SIG 1  to SIG 4 . Furthermore, in a case where the operation mode indicated by the mode signal Smode is the operation mode MB, the transmitter  72  transmits data generated by the processor  61  by using signals SIG 1 P and SIG 1 N and signals SIG 2 P and SIG 2 N. Moreover, in a case where the operation mode indicated by the mode signal Smode is the operation mode MC, the transmitter  72  transmits data generated by the processor  61  by using signals SIGA, SIGB, and SIGC. The transmitter  72  includes transmitting circuit units  72 A and  72 B and a controller  75  as illustrated in  FIG. 39 . 
       FIG. 60A  illustrates a configuration example of the transmitting circuit unit  72 A, and  FIG. 60B  illustrates a configuration example of the transmitting circuit unit  72 B. The transmitting circuit unit  62 A includes four serializers  28  (the serializers  28 A,  28 B,  28 C, and  28 D), four encoders  29  (the encoders  29 A,  29 B,  29 C, and  29 D), four multiplexers  22  (the multiplexers  22 A,  22 B,  22 C, and  22 D), four inverters  73  (inverters  73 A,  73 B,  73 C, and  73 D), four selectors  23  (the selectors  23 A,  23 B,  23 C, and  23 D), and two drivers  24  (the drivers  24 A and  24 B). The transmitting circuit unit  62 B includes four serializers  28  (the serializers  28 E,  28 F,  28 G, and  28 H), four encoders  29  (the encoders  29 E,  29 F,  29 G, and  29 H), four multiplexers  22  (the multiplexers  22 E,  22 F,  22 G, and  22 H), four selectors  23  (the selectors  23 E,  23 F,  23 G, and  23 H), four inverters  73  (inverters  73 E,  73 F,  73 G, and  73 H), and two drivers  24  (the drivers  24 C and  24 D). 
     The inverter  73 A generates an inverted signal of the signal S 22 B. The inverter  73 B generates an inverted signal of the signal S 22 A. The inverter  73 C generates an inverted signal of the signal S 22 D. The inverter  73 D generates an inverted signal of the signal S 22 C. The inverter  73 E generates an inverted signal of the signal S 22 F. The inverter  73 F generates an inverted signal of the signal S 22 E. The inverter  73 G generates an inverted signal of the signal S 22 H. The inverter  73 H generates an inverted signal of the signal S 22 G. 
     On the basis of a signal Ssel, the selector  23 A ( FIG. 60A ) selects the output signal of the inverter  73 A in a case where the operation mode is the operation mode MA (single-phase mode) or the operation mode MC (three-phase mode), or selects the signal S 22 D in a case where the operation mode is the operation mode MB (differential mode), and outputs the selected signal as a signal S 23 A. On the basis of a signal Ssel, the selector  23 B selects the output signal of the inverter  73 B in a case where the operation mode is the operation mode MA or the operation mode MC, or selects the signal S 22 C in a case where the operation mode is the operation mode MB, and outputs the selected signal as a signal S 23 B. On the basis of a signal Ssel, the selector  23 C selects the output signal of the inverter  73 C in a case where the operation mode is the operation mode MA or the operation mode MC, or selects the signal S 22 B in a case where the operation mode is the operation mode MB, and outputs the selected signal as a signal S 23 C. On the basis of a signal Ssel, the selector  23 D selects the output signal of the inverter  73 D in a case where the operation mode is the operation mode MA or the operation mode MC, or selects the signal S 22 A in a case where the operation mode is the operation mode MB, and outputs the selected signal as a signal S 23 D. On the basis of a signal Ssel, the selector  23 E ( FIG. 60B ) selects the output signal of the inverter  73 E in a case where the operation mode is the operation mode MA or the operation mode MC, or selects the signal S 22 H in a case where the operation mode is the operation mode MB, and outputs the selected signal as a signal S 23 E. On the basis of a signal Ssel, the selector  23 F selects the output signal of the inverter  73 F in a case where the operation mode is the operation mode MA or the operation mode MC, or selects the signal S 22 G in a case where the operation mode is the operation mode MB, and outputs the selected signal as a signal S 23 F. On the basis of a signal Ssel, the selector  23 G selects the output signal of the inverter  73 G in a case where the operation mode is the operation mode MA or the operation mode MC, or selects the signal S 22 F in a case where the operation mode is the operation mode MB, and outputs the selected signal as a signal S 23 G. On the basis of a signal Ssel, the selector  23 H selects the output signal of the inverter  73 H in a case where the operation mode is the operation mode MA or the operation mode MC, or selects the signal S 22 E in a case where the operation mode is the operation mode MB, and outputs the selected signal as a signal S 23 H. 
     The driver  24 A ( FIG. 60A ) sets a voltage at the output terminal Tout 1  on the basis of the signals S 22 A, S 22 B, S 23 A, and S 23 B and a signal CTL. The driver  24 B sets a voltage at the output terminal Tout 2  on the basis of the signals S 23 C, S 23 D, S 22 C, and S 22 D and the signal CTL. The driver  24 C ( FIG. 60B ) sets a voltage at the output terminal Tout 3  on the basis of the signals S 22 E, S 22 F, S 23 E, and S 23 F and a signal CTL. The driver  24 D sets a voltage at the output terminal Tout 4  on the basis of the signals S 23 G, S 23 H, S 22 G, and S 22 H and the signal CTL. 
     In the operation modes MA (single-phase mode) and MB (differential mode), for example, as illustrated in  FIG. 8 , the driver  24 A sets the number of sub-drivers AA to “M” and the number of sub-drivers AB to “N” on the basis of a signal CTL. The same applies to the drivers  24 B to  24 D. 
     On the other hand, in the operation mode MC (three-phase mode), on the basis of a signal CTL, the drivers  24 A,  24 B,  24 C, and  24 D set the number of sub-drivers AA, AB, BA, BB, CA, CB, DA, and DB to be different from those in the case of the operation modes MA and MB as described below. 
       FIG. 61  illustrates a configuration example of the drivers  24 A and  24 B in the operation mode MC. In in the operation mode MC, the driver  24 A sets both the number of sub-drivers AA and the number of sub-drivers AB to “L” on the basis of a signal CTL. The number “L” may be set so as to meet, for example, “2×L=M+N”. The same applies to the drivers  24 B to  24 D. 
     With this configuration, for example, in a case where in the operation mode MC, the signals S 22 A and S 22 B are both set to low level, the signals S 23 A and  23 B both become high level. Therefore, the transistors  92  and  93  in the sub-drivers AB 1  to ABL of the driver  24 A go into on state, and the transistors  92  and  93  in the sub-drivers AA 1  to AAL go into off state. As a result, the driver  24 A is able to set the voltage at the output terminal Tout 1  to the medium-level voltage VM and the output impedance to about 50[Ω]. 
     (Operation Mode MA) 
       FIG. 62  illustrates the flow of signals in the operation mode MA. In  FIG. 62 , bold solid lines indicate the flow of signals related to signals DI 10  to DI 17 , and bold dashed lines indicate the flow of signals related to signals DI 20  to DI 27 . In this example, the operation of the transmitting circuit unit  72 A is described; however, the same applies to the operation of the transmitting circuit unit  72 B. 
     First, the flow of signals related to DI 10  to DI 17  is described. The operations of the serializers  28 A and  28 C, the encoders  29 A and  29 C, and the multiplexers  22 A and  22 B are the same as in the case of the second embodiment. On the basis of a signal Ssel, the selector  23 A selects an inverted signal of the signal S 22 B in the operation mode MA, and outputs the selected signal as a signal S 23 A. On the basis of a signal Ssel, the selector  23 B selects an inverted signal of the signal S 22 A in the operation mode MA, and outputs the selected signal as a signal S 23 B. In the operation mode MA, the signals S 22 A and S 22 B are signals that are inverted from each other; therefore, the inverted signal of the signal S 22 B corresponds to the signal S 22 A, and the inverted signal of the signal S 22 A corresponds to the signal S 22 B. As a result, the driver  24 A operates on the basis of the signals S 22 A and S 22 B. 
     Next, the flow of signals related to signals DI 20  to DI 27  is described. The operations of the serializers  28 B and  28 D, the encoders  29 B and  29 D, and the multiplexers  22 C and  22 D are the same as in the case of the second embodiment. On the basis of a signal Ssel, the selector  23 C selects an inverted signal of the signal S 22 D in the operation mode MA, and outputs the selected signal as a signal S 23 C. On the basis of a signal Ssel, the selector  23 D selects an inverted signal of the signal S 22 C in the operation mode MA, and outputs the selected signal as a signal S 23 D. In the operation mode MA, the signals S 22 C and S 22 D are signals that are inverted from each other; therefore, the inverted signal of the signal S 22 D corresponds to the signal S 22 C, and the inverted signal of the signal S 22 C corresponds to the signal S 22 D. As a result, the driver  24 B operates on the basis of the signals S 22 C and S 22 D. 
     In this way, in the operation mode MA, the transmitting device  70  transmits data to the receiving device  130  by using signals SIG 1  to SIG 4 , as with the transmitting device  60  according to the second embodiment. 
     (Operation Mode MB) 
       FIG. 63  illustrates the flow of signals in the operation mode MB. In  FIG. 63 , bold solid lines indicate the flow of signals related to signals DI 10  to DI 17 , and bold dashed lines indicate the flow of signals related to signals DI 20  to DI 27 . In this example, the operation of the transmitting circuit unit  72 A is described; however, the same applies to the operation of the transmitting circuit unit  72 B. 
     First, the flow of signals related to DI 10  to DI 17  is described. The operations of the serializers  28 A and  28 C, the encoders  29 A and  29 C, and the multiplexers  22 A and  22 B are the same as in the case of the second embodiment. On the basis of a signal Ssel, the selector  23 C selects the signal S 22 B in the operation mode MB, and outputs the selected signal as a signal S 23 C. On the basis of a signal Ssel, the selector  23 D selects the signal S 22 A in the operation mode MB, and outputs the selected signal as a signal S 23 D. As a result, the sub-drivers AA 1  to AAM of the driver  24 A operate on the basis of the signals S 22 A and S 22 B, and the sub-drivers BA 1  to BAM of the driver  24 B operate on the basis of the signals S 22 B and S 22 A. 
     Next, the flow of signals related to signals DI 20  to DI 27  is described. The operations of the serializers  28 B and  28 D, the encoders  29 B and  29 D, and the multiplexers  22 C and  22 D are the same as in the case of the second embodiment. On the basis of a signal Ssel, the selector  23 A selects the signal S 22 D in the operation mode MB, and outputs the selected signal as a signal S 23 A. On the basis of a signal Ssel, the selector  23 B selects the signal S 22 C in the operation mode MB, and outputs the selected signal as a signal S 23 B. As a result, the sub-drivers AB 1  to ABN of the driver  24 A operate on the basis of the signals S 22 D and S 22 C, and the sub-drivers BB 1  to BBN of the driver  24 B operate on the basis of the signals S 22 C and S 22 D. 
     In this way, in the operation mode MB, the transmitting device  70  transmits data to the receiving device  140  by using signals SIG 1 P and SIG 1 N and signals SIG 2 P and SIG 2 N, as with the transmitting device  60  according to the second embodiment. 
     (Operation Mode MC) 
       FIGS. 64A and 64B  illustrate the flow of signals in the operation mode MC. In  FIG. 64A , bold solid lines indicate the flow of signals related to a signal SIGA, and bold dashed lines indicate the flow of signals related to a signal SIGB. In  FIG. 64B , bold dashed-dotted lines indicate the flow of signals related to a signal SIGC. The operations of the serializers  28 A to  28 H, the encoders  29 A to  29 H, and the multiplexers  22 A to  22 H are the same as in the case of the second embodiment. 
     On the basis of a signal Ssel, the selector  23 A ( FIG. 64A ) selects an inverted signal of the signal S 22 B in the operation mode MC, and outputs the selected signal as a signal S 23 A. On the basis of a signal Ssel, the selector  23 B selects an inverted signal of the signal S 22 A in the operation mode MC, and outputs the selected signal as a signal S 23 B. As a result, the driver  24 A operates on the basis of the signals S 22 A and S 22 B. 
     Likewise, on the basis of a signal Ssel, the selector  23 C selects an inverted signal of the signal S 22 D in the operation mode MC, and outputs the selected signal as a signal S 23 C. On the basis of a signal Ssel, the selector  23 D selects an inverted signal of the signal S 22 C in the operation mode MC, and outputs the selected signal as a signal S 23 D. As a result, the driver  24 B operates on the basis of the signals S 22 C and S 22 D. 
     Likewise, on the basis of a signal Ssel, the selector  23 E ( FIG. 64B ) selects an inverted signal of the signal S 22 F in the operation mode MC, and outputs the selected signal as a signal S 23 E. On the basis of a signal Ssel, the selector  23 F selects an inverted signal of the signal S 22 E in the operation mode MC, and outputs the selected signal as a signal S 23 F. As a result, the driver  24 C operates on the basis of the signals S 22 E and S 22 F. 
     For example, in a case where the signals S 28 A, S 28 B, and S 28 E are “1”, “0”, and “0”, respectively, as illustrated in  FIG. 43 , the encoder  29 A sets the signals S 29 AP and S 29 AN to “1” and “0”, respectively; the encoder  29 B sets the signals S 29 BP and S 29 BN to “0” and “1”, respectively; and the encoder  29 E sets the signals S 29 EP and S 29 EN to “0” and “0”, respectively. As a result, as illustrated in  FIG. 48 , the output signal S 22 A of the multiplexer  22 A becomes “1”; the output signal S 22 B of the multiplexer  22 B becomes “0”; the output signal S 22 C of the multiplexer  22 C becomes “0”; the output signal S 22 D of the multiplexer  22 D becomes “1”; the output signal S 22 E of the multiplexer  22 E becomes “0”; and the output signal S 22 F of the multiplexer  22 F becomes “0”. 
     At this time, in the driver  24 A ( FIG. 64A ), the transistors  92  in the sub-drivers AA 1  to AAL and AB 1  to ABL go into on state, and the transistors  93  in the sub-drivers AA 1  to AAL and AB 1  to ABL go into off state. As a result, the driver  24 A sets the voltage at the output terminal Tout 1  to the high-level voltage VH and the output impedance to about 50[Ω]. 
     Furthermore, in the driver  24 B, the transistors  93  in the sub-drivers BA 1  to BAL and BB 1  to BBL go into on state, and the transistors  92  in the sub-drivers BA 1  to BAL and BB 1  to BBL go into off state. As a result, the driver  24 B sets the voltage at the output terminal Tout 2  to the low-level voltage VL and the output impedance to about 50[Ω]. 
     Moreover, in the driver  24 C ( FIG. 64B ), the transistors  92  and  93  in the sub-drivers CB 1  to CBL go into on state, and the transistors  92  and  93  in the sub-drivers CA 1  to CAL go into off state. As a result, the driver  24 C sets the voltage at the output terminal Tout 3  to the medium-level voltage VM and the output impedance to about 50 [Ω]. 
     In this way, the transmitter  72  sets the signal SIGA to the high-level voltage VH, the signal SIGB to the low-level voltage VL, and the signal SIGC to the medium-level voltage VM. As a result, the transmitting device  70  transmits the symbol “+x” to the receiving device  150 . 
     In this way, in the operation mode MC, the transmitting device  70  transmits data to the receiving device  150  by using signals SIGA, SIGB, and SIGC. 
     In this way, in the transmitting device  70 , when the voltages at the output terminals Tout 1 , Tout 2 , and Tout 3  are set to the medium-level voltage VM, the output impedance is set to about 50[Ω]. Accordingly, for example, the transmitting device  70  makes it possible to suppress signal reflection, and therefore, it is possible to enhance the waveform quality. Furthermore, in the transmitting device  70 , in a case where the voltages at the output terminals Tout 1 , Tout 2 , and Tout 3  are made transition from the high-level voltage VH or the low-level voltage VL to the medium-level voltage VM, the transition time is able to be reduced; therefore, it is possible to enhance the waveform quality. Consequently, it is possible to enhance the communication quality in the transmitting device  70 . 
     As described above, in the present embodiment, the output impedance is set to about 50[Ω] when the voltage at the output terminal is set to the medium-level voltage VM; therefore, it is possible to enhance the communication quality. 
     Modification Example 3-1 
     In the above-described embodiment, the four drivers  24 A,  24 B,  24 C, and  24 D are provided; however, it is not limited to this. A modification example is described in detail below. 
       FIGS. 65A and 65B  illustrate respective configuration examples of main parts of transmitting circuit units  74 A and  74 B of a transmitter  74  according to the present modification example.  FIG. 65A  depicts a circuit subsequent to the encoders  29 A to  29 D in  FIG. 60A , and  FIG. 65B  depicts a circuit subsequent to the encoders  29 E to  29 H in  FIG. 60B . The transmitting circuit unit  74 A includes four serializers  28  (the serializers  28 A,  28 B,  28 C, and  28 D), four encoders  29  (the encoders  29 A,  29 B,  29 C, and  29 D), four multiplexers  76  (multiplexers  76 A,  76 B,  76 C, and  76 D), eight selectors  77  (selectors  77 A,  77 B,  77 C,  77 D,  77 E,  77 F,  77 G, and  77 H), and four drivers  79  (drivers  79 A,  79 B,  79 C, and  79 D). The transmitting circuit unit  74 B includes four serializers  28  (the serializers  28 E,  28 F,  28 G, and  28 H), four encoders  29  (the encoders  29 E,  29 F,  29 G, and  29 H), four multiplexers  76  (multiplexers  76 E,  76 F,  76 G, and  76 H), eight selectors  77  (selectors  77 I,  77 J,  77 K,  77 L,  77 M,  77 N,  77 O, and  77 P), and four drivers  79  (drivers  79 E,  79 F,  79 G, and  79 H). 
     The multiplexer  76 A ( FIG. 65A ) alternately selects one of the signals S 29 AP and S 29 CP on the basis of a clock signal CLK, and outputs the selected signal as a signal S 76 AP, and outputs an inverted signal of the signal S 76 AP as a signal S 76 AN. The multiplexer  76 B alternately selects one of the signals S 29 AN and S 29 CN on the basis of a clock signal CLK, and outputs the selected signal as a signal S 76 BP, and outputs an inverted signal of the signal S 76 BP as a signal S 76 BN. The multiplexer  76 C alternately selects one of the signals S 29 BP and S 29 DP on the basis of a clock signal CLK, and outputs the selected signal as a signal S 76 CP, and outputs an inverted signal of the signal S 76 CP as a signal S 76 CN. The multiplexer  76 D alternately selects one of the signals S 29 BN and S 29 DN on the basis of a clock signal CLK, and outputs the selected signal as a signal S 76 DP, and outputs an inverted signal of the signal S 76 DP as a signal S 76 DN. The multiplexer  76 E ( FIG. 65B ) alternately selects one of the signals S 29 EP and S 29 GP on the basis of a clock signal CLK, and outputs the selected signal as a signal S 76 EP, and outputs an inverted signal of the signal S 76 EP as a signal S 76 EN. The multiplexer  76 F alternately selects one of the signals S 29 EN and S 29 GN on the basis of a clock signal CLK, and outputs the selected signal as a signal S 76 FP, and outputs an inverted signal of the signal S 76 FP as a signal S 76 FN. The multiplexer  76 G alternately selects one of the signals S 29 FP and S 29 HP on the basis of a clock signal CLK, and outputs the selected signal as a signal S 76 GP, and outputs an inverted signal of the signal S 76 GP as a signal S 76 GN. The multiplexer  27 H alternately selects one of the signals S 29 FN and S 29 HN on the basis of a clock signal CLK, and outputs the selected signal as a signal S 76 HP, and outputs an inverted signal of the signal S 76 HP as a signal S 76 HN. 
     On the basis of a signal Ssel, the selector  77 A ( FIG. 65A ) selects the signal S 76 AP in a case where the operation mode is the operation mode MA (single-phase mode) or the operation mode MC (three-phase mode), or selects the signal S 76 DP in a case where the operation mode is the operation mode MB (differential mode), and outputs the selected signal as a signal S 77 A. On the basis of a signal Ssel, the selector  77 B selects the signal S 76 BP in a case where the operation mode is the operation mode MA or the operation mode MC, or selects the signal S 76 CP in a case where the operation mode is the operation mode MB, and outputs the selected signal as a signal S 77 B. On the basis of a signal Ssel, the selector  77 C selects the signal S 76 CP in a case where the operation mode is the operation mode MA or the operation mode MC, or selects the signal S 76 BP in a case where the operation mode is the operation mode MB, and outputs the selected signal as a signal S 77 C. On the basis of a signal Ssel, the selector  77 D selects the signal S 76 DP in a case where the operation mode is the operation mode MA or the operation mode MC, or selects the signal S 76 AP in a case where the operation mode is the operation mode MB, and outputs the selected signal as a signal S 77 D. On the basis of a signal Ssel, the selector  77 E selects the signal S 76 BN in a case where the operation mode is the operation mode MA or the operation mode MC, or selects the signal S 76 CN in a case where the operation mode is the operation mode MB, and outputs the selected signal as a signal S 77 E. On the basis of a signal Ssel, the selector  77 F selects the signal S 76 AN in a case where the operation mode is the operation mode MA or the operation mode MC, or selects the signal S 76 DN in a case where the operation mode is the operation mode MB, and outputs the selected signal as a signal S 77 F. On the basis of a signal Ssel, the selector  77 G selects the signal S 76 DN in a case where the operation mode is the operation mode MA or the operation mode MC, or selects the signal S 76 AN in a case where the operation mode is the operation mode MB, and outputs the selected signal as a signal S 77 G. On the basis of a signal Ssel, the selector  77 H selects the signal S 76 CN in a case where the operation mode is the operation mode MA or the operation mode MC, or selects the signal S 76 BN in a case where the operation mode is the operation mode MB, and outputs the selected signal as a signal S 77 H. 
     On the basis of a signal Ssel, the selector  77 I ( FIG. 65B ) selects the signal S 76 EP in a case where the operation mode is the operation mode MA or the operation mode MC, or selects the signal S 76 HP in a case where the operation mode is the operation mode MB, and outputs the selected signal as a signal S 77 I. On the basis of a signal Ssel, the selector  77 J selects the signal S 76 FP in a case where the operation mode is the operation mode MA or the operation mode MC, or selects the signal S 76 GP in a case where the operation mode is the operation mode MB, and outputs the selected signal as a signal S 77 J. On the basis of a signal Ssel, the selector  77 K selects the signal S 76 GP in a case where the operation mode is the operation mode MA or the operation mode MC, or selects the signal S 76 FP in a case where the operation mode is the operation mode MB, and outputs the selected signal as a signal S 77 K. On the basis of a signal Ssel, the selector  77 L selects the signal S 76 HP in a case where the operation mode is the operation mode MA or the operation mode MC, or selects the signal S 76 EP in a case where the operation mode is the operation mode MB, and outputs the selected signal as a signal S 77 L. On the basis of a signal Ssel, the selector  77 M selects the signal S 76 FN in a case where the operation mode is the operation mode MA or the operation mode MC, or selects the signal S 76 GN in a case where the operation mode is the operation mode MB, and outputs the selected signal as a signal S 77 M. On the basis of a signal Ssel, the selector  77 N selects the signal S 76 EN in a case where the operation mode is the operation mode MA or the operation mode MC, or selects the signal S 76 HN in a case where the operation mode is the operation mode MB, and outputs the selected signal as a signal S 77 N. On the basis of a signal Ssel, the selector  77 O selects the signal S 76 HN in a case where the operation mode is the operation mode MA or the operation mode MC, or selects the signal S 76 EN in a case where the operation mode is the operation mode MB, and outputs the selected signal as a signal S 77 O. On the basis of a signal Ssel, the selector  77 P selects the signal S 76 GN in a case where the operation mode is the operation mode MA or the operation mode MC, or selects the signal S 76 FN in a case where the operation mode is the operation mode MB, and outputs the selected signal as a signal S 77 P. 
     The driver  79 A ( FIG. 65A ) operates on the basis of the signals S 76 AP, S 76 BP, S 77 A, and S 77 B and a signal CTL, and the driver  79 C operates on the basis of the signals S 76 BN, S 76 AN, S 77 E, S 77 F and a signal CTL. Then, the drivers  79 A and  79 C set a voltage at the output terminal Tout 1 . The driver  79 B operates on the basis of the signals S 77 C, S 77 D, S 76 CP, and S 76 DP and a signal CTL, and the driver  79 D operates on the basis of the signals S 77 G, S 77 H, S 76 DN, and S 76 CN and a signal CTL. Then, the drivers  79 B and  79 D set a voltage at the output terminal Tout 2 . 
     The driver  79 E ( FIG. 65B ) operates on the basis of the signals S 76 EP, S 76 FP, S 77 I, and S 77 J and a signal CTL, and the driver  79 G operates on the basis of the signals S 76 FN, S 76 EN, S 77 M, S 77 N and a signal CTL. Then, the drivers  79 E and  79 G set a voltage at the output terminal Tout 3 . The driver  79 F operates on the basis of the signals S 77 K, S 77 L, S 76 GP, and S 76 HP and a signal CTL, and the driver  79 H operates on the basis of the signals S 77 O, S 77 P, S 76 HN, and S 76 GN and a signal CTL. Then, the drivers  79 F and  79 H set a voltage at the output terminal Tout 4 . 
     In the operation modes MA (single-phase mode) and MB (differential mode), the drivers  79 A sets the number of sub-drivers AA to “M/2” and the number of sub-drivers AB to “N/2” on the basis of a signal CTL. The same applies to the drivers  79 B to  79 H. 
     On the other hand, in the operation mode MC (three-phase mode), the driver  24 A sets both the number of sub-drivers AA and the number of sub-drivers AB to “L/2” on the basis of a signal CTL. The number “L” may be set so as to meet, for example, “2×L=M+N”. The same applies to the drivers  79 B to  79 H. 
     With this configuration, for example, in a case where in the operation mode MC, the signals S 76 BP and S 76 BP are both set to low level, and the signals S 76 AN and S 76 BN are both set to high level, the signals S 77 A and S 77 B both become low level, and the signals S 77 E and S 77 F both become high level. Therefore, the transistors  92  and  93  in the driver  79 C go into on state, and the transistors  92  and  93  in the driver  79 A go into off state. As a result, the drivers  79 A and  79 C are able to set the voltage at the output terminal Tout 1  to the medium-level voltage VM and the output impedance to about 50[Ω]. 
     The two drivers  79 A and  79 C here correspond to a specific example of the “first driver” in the present disclosure. The plurality of sub-drivers AA 1  to AA(M/2) and CA 1  to CA(M/2) correspond to a specific example of the “first sub-driver unit” in the present disclosure, and the plurality of sub-drivers AB 1  to AB(N/2) and CB 1  to CB(N/2) correspond to a specific example of the “second sub-driver unit” in the present disclosure. The two drivers  79 B and  79 D correspond to a specific example of the “second driver” in the present disclosure. The plurality of sub-drivers BA 1  to BA(M/2) and DA 1  to DA(M/2) correspond to a specific example of the “third sub-driver unit” in the present disclosure, and the plurality of sub-drivers BB 1  to BB(N/2) and DB 1  to DB(N/2) correspond to a specific example of the “fourth sub-driver unit” in the present disclosure. The plurality of selectors  77 A to  77 H correspond to a specific example of the “selector unit” in the present disclosure. The plurality of multiplexers  76 A to  76 H correspond to a specific example of the “multiplexer unit” in the present disclosure. 
       FIG. 66  illustrates the flow of signals in the operation mode MA (single-phase mode). In this example, the operation of the transmitting circuit unit  74 A is described; however, the same applies to the operation of the transmitting circuit unit  74 B. 
     First, the flow of signals related to DI 10  to DI 17  is described. On the basis of a signal Ssel, the selector  77 A selects the signal S 76 AP in the operation mode MA, and outputs the selected signal as a signal S 77 A. On the basis of a signal Ssel, the selector  77 B selects the signal S 76 BP in the operation mode MA, and outputs the selected signal as a signal S 77 B. On the basis of a signal Ssel, the selector  77 E selects the signal S 76 BN in the operation mode MA, and outputs the selected signal as a signal S 77 E. On the basis of a signal Ssel, the selector  77 F selects the signal S 76 AN in the operation mode MA, and outputs the selected signal as a signal S 77 F. In the operation mode MA, the signals S 76 AP and S 76 BP are signals that are inverted from each other; therefore, the signal S 76 BN corresponds to the signal S 76 AP, and the signal S 76 BP corresponds to the signal S 76 AN. As a result, the driver  79 A operates on the basis of the signals S 76 AP and S 76 BP, and the driver  79 C operates on the basis of the signals S 76 AP and S 76 BP. 
     Next, the flow of signals related to signals DI 20  to DI 27  is described. On the basis of a signal Ssel, the selector  77 C selects the signal S 76 CP in the operation mode MA, and outputs the selected signal as a signal S 77 C. On the basis of a signal Ssel, the selector  77 D selects the signal S 76 DP in the operation mode MA, and outputs the selected signal as a signal S 77 D. On the basis of a signal Ssel, the selector  77 G selects the signal S 76 DN in the operation mode MA, and outputs the selected signal as a signal S 77 G. On the basis of a signal Ssel, the selector  77 H selects the signal S 76 CN in the operation mode MA, and outputs the selected signal as a signal S 77 H. In the operation mode MA, the signals S 76 CP and S 76 DP are signals that are inverted from each other; therefore, the signal S 76 DN corresponds to the signal S 76 CP, and the signal S 76 DP corresponds to the signal S 76 CN. As a result, the driver  79 B operates on the basis of the signals S 76 CP and S 76 DP, and the driver  79 D operates on the basis of the signals S 76 CP and S 76 DP. 
       FIG. 67  illustrates the flow of signals in the operation mode MB (differential mode). In this example, the operation of the transmitting circuit unit  74 A is described; however, the same applies to the operation of the transmitting circuit unit  74 B. 
     First, the flow of signals related to DI 10  to DI 17  is described. On the basis of a signal Ssel, the selector  77 C selects the signal S 76 BP in the operation mode MB, and outputs the selected signal as a signal S 77 C. On the basis of a signal Ssel, the selector  77 D selects the signal S 76 AP in the operation mode MB, and outputs the selected signal as a signal S 77 D. On the basis of a signal Ssel, the selector  77 G selects the signal S 76 AN in the operation mode MB, and outputs the selected signal as a signal S 77 G. On the basis of a signal Ssel, the selector  77 H selects the signal S 76 BN in the operation mode MB, and outputs the selected signal as a signal S 77 H. In the operation mode MB, the signals S 76 AP and S 76 BP are signals that are inverted from each other; therefore, the signal S 76 BN corresponds to the signal S 76 AP, and the signal S 76 BP corresponds to the signal S 76 AN. As a result, the sub-drivers AA 1  to AA(M/2) of the driver  79 A operate on the basis of the signals S 76 AP and S 76 BP, and the sub-drivers CA 1  to CA(M/2) of the driver  79 C operate on the basis of the signals S 76 AP and S 76 BP. Likewise, the sub-drivers BA 1  to BA(M/2) of the driver  79 B operate on the basis of the signals S 76 BP and S 76 AP, and the sub-drivers DA 1  to DA(M/2) of the driver  79 D operate on the basis of the signals S 76 BP and S 76 AP. 
     Next, the flow of signals related to signals DI 20  to DI 27  is described. On the basis of a signal Ssel, the selector  77 A selects the signal S 76 DP in the operation mode MB, and outputs the selected signal as a signal S 77 A. On the basis of a signal Ssel, the selector  77 B selects the signal S 76 CP in the operation mode MB, and outputs the selected signal as a signal S 77 B. On the basis of a signal Ssel, the selector  77 E selects the signal S 76 CN in the operation mode MB, and outputs the selected signal as a signal S 77 E. On the basis of a signal Ssel, the selector  77 F selects the signal S 76 DN in the operation mode MB, and outputs the selected signal as a signal S 77 F. In the operation mode MB, the signals S 76 CP and S 76 DP are signals that are inverted from each other; therefore, the signal S 76 DN corresponds to the signal S 76 CP, and the signal S 76 DP corresponds to the signal S 76 CN. As a result, the sub-drivers AB 1  to AB(N/2) of the driver  79 A operate on the basis of the signals S 76 DP and S 76 CP, and the sub-drivers CB 1  to CB(N/2) of the driver  79 C operate on the basis of the signals S 76 DP and S 76 CP. Likewise, the sub-drivers BB 1  to BB(N/2) of the driver  79 B operate on the basis of the signals S 76 CP and S 76 DP, and the sub-drivers DB 1  to DB(N/2) of the driver  79 D operate on the basis of the signals S 76 CP and S 76 DP. 
       FIGS. 68A and 68B  illustrate the flow of signals in the operation mode MC (three-phase mode). 
     On the basis of a signal Ssel, the selector  77 A ( FIG. 68A ) selects the signal S 76 AP in the operation mode MC, and outputs the signal S 76 AP as a signal S 77 A. On the basis of a signal Ssel, the selector  77 B selects the signal S 76 BP in the operation mode MC, and outputs the signal S 76 BP as a signal S 77 B. On the basis of a signal Ssel, the selector  77 E selects the signal S 76 BN in the operation mode MC, and outputs the signal S 76 BN as a signal S 77 E. On the basis of a signal Ssel, the selector  77 F selects the signal S 76 AN in the operation mode MC, and outputs the signal S 76 AN as a signal S 77 F. As a result, the driver  79 A operates on the basis of the signals S 76 AP and S 76 BP, and the driver  79 C operates on the basis of the signals S 76 BN and S 76 AN. 
     Likewise, on the basis of a signal Ssel, the selector  77 C selects the signal S 76 CP in the operation mode MC, and outputs the signal S 76 CP as a signal S 77 C. On the basis of a signal Ssel, the selector  77 D selects the signal S 76 DP in the operation mode MC, and outputs the signal S 76 DP as a signal S 77 D. On the basis of a signal Ssel, the selector  77 G selects the signal S 76 DN in the operation mode MC, and outputs the signal S 76 DN as a signal S 77 G. On the basis of a signal Ssel, the selector  77 H selects the signal S 76 CN in the operation mode MC, and outputs the signal S 76 CN as a signal S 77 H. As a result, the driver  79 B operates on the basis of the signals S 76 CP and S 76 DP, and the driver  79 D operates on the basis of the signals S 76 DN and S 76 CN. 
     Likewise, on the basis of a signal Ssel, the selector  77 I ( FIG. 68B ) selects the signal S 76 EP in the operation mode MC, and outputs the selected signal as a signal S 77 I. On the basis of a signal Ssel, the selector  77 J selects the signal S 76 FP in the operation mode MC, and outputs the signal S 76 FP as a signal S 77 J. On the basis of a signal Ssel, the selector  77 M selects the signal S 76 FN in the operation mode MC, and outputs the signal S 76 FN as a signal S 77 M. On the basis of a signal Ssel, the selector  77 N selects the signal S 76 EN in the operation mode MC, and outputs the signal S 76 EN as a signal S 77 N. As a result, the driver  79 E operates on the basis of the signals S 76 EP and S 76 FP, and the driver  79 G operates on the basis of the signals S 76 FN and S 76 EN. 
     Modification Example 3-2 
     In the above-described embodiment, the encoders  29  are provided in the preceding stage of the multiplexers  22 ; however, it is not limited to this. Instead of this, for example, encoders may be provided in the subsequent stage of the multiplexers  22 .  FIGS. 69A and 69B  illustrate respective configuration examples of transmitting circuit units  78 A and  78 B of a transmitter  78  according to a modification example. The transmitting circuit unit  78 A includes four serializers  21  (the serializers  21 A,  21 B,  21 C, and  21 D), four multiplexers  22  (the multiplexers  22 A,  22 B,  22 C, and  22 D), four encoders  64  (the encoders  64 A,  64 B,  64 C, and  64 D), four inverters  73  (the inverters  73 A,  73 B,  73 C, and  73 D), four selectors  23  (the selectors  23 A,  23 B,  23 C, and  23 D), and two drivers  24  (the drivers  24 A and  24 B). The transmitting circuit unit  78 B includes four serializers  21  (the serializers  21 E,  21 F,  21 G, and  21 H), four multiplexers  22  (the multiplexers  22 E,  22 F,  22 G, and  22 H), four encoders  64  (the encoders  64 E,  64 F,  64 G, and  64 H), four inverters  73  (the inverters  73 E,  73 F,  73 G, and  73 H), four selectors  23  (the selectors  23 E,  23 F,  23 G, and  23 H), and two drivers  24  (the drivers  24 C and  24 D). 
     Modification Example 3-3 
     In the above-described embodiment, the serializers  28 A to  28 H having the same configuration as those in  FIG. 3  are used; however, it is not limited to this. FIGS.  70 A and  70 B illustrate respective configuration examples of transmitting circuit units  81 A and  81 B of a transmitter  81  according to a modification example. The transmitting circuit unit  81 A includes four serializers  68  (the serializers  68 A,  68 B,  68 C, and  68 D), four encoders  29  (the encoders  29 A,  29 B,  29 C, and  29 D), four multiplexers  22  (the multiplexers  22 A,  22 B,  22 C, and  22 D), four inverters  73  (the inverters  73 A,  73 B,  73 C, and  73 D), four selectors  23  (the selectors  23 A,  23 B,  23 C, and  23 D), and two drivers  24  (the drivers  24 A and  24 B). The transmitting circuit unit  81 B includes four serializers  68  (the serializers  68 E,  68 F,  68 G, and  68 H), four encoders  29  (the encoders  29 E,  29 F,  29 G, and  29 H), four multiplexers  22  (the multiplexers  22 E,  22 F,  22 G, and  22 H), four inverters  73  (the inverters  73 E,  73 F,  73 G, and  73 H), four selectors  23  (the selectors  23 E,  23 F,  23 G, and  23 H), and two drivers  24  (the drivers  24 C and  24 D). 
     In the transmitter  81  according to the present modification example, the encoders  29  are provided in the preceding stage of the multiplexers  22 ; however, it is not limited to this. Instead of this, for example, encoders may be provided in the subsequent stage of the multiplexers  22 .  FIGS. 71A and 71B  illustrate respective configuration examples of transmitting circuit units  82 A and  82 B of a transmitter  82  according to a modification example. The transmitting circuit unit  82 A includes four serializers four serializers  68  (the serializers  68 A,  68 B,  68 C, and  68 D), four multiplexers  22  (the multiplexers  22 A,  22 B,  22 C, and  22 D), two encoders  29  (the encoders  29 A and  29 B), four inverters  73  (the inverters  73 A,  73 B,  73 C, and  73 D), four selectors  23  (the selectors  23 A,  23 B,  23 C, and  23 D), and two drivers  24  (the drivers  24 A and  24 B). The transmitting circuit unit  82 B includes four serializers  68  (the serializers  68 E,  68 F,  68 G, and  68 H), four multiplexers  22  (the multiplexers  22 E,  22 F,  22 G, and  22 H), two encoders  29  (the encoders  29 C and  29 D), four inverters  73  (the inverters  73 E,  73 F,  73 G, and  73 H), four selectors  23  (the selectors  23 E,  23 F,  23 G, and  23 H), and two drivers  24  (the drivers  24 C and  24 D). 
     4. Application Example 
     Subsequently, some application examples of the communication systems described in the above embodiments and modification examples are described. 
     Application Example 1 
       FIG. 72  illustrates an external appearance of a smartphone  300  (a multi-function mobile phone) to which the communication system in any of the above-described embodiments, etc. is applied. This smartphone  300  is equipped with various devices; the communication system in any of the above-described embodiments, etc. is applied to a communication system in which these devices exchange data between them. 
       FIG. 73  illustrates a configuration example of an application processor  310  used in the smartphone  300 . The application processor  310  includes a central processing unit (CPU)  311 , a memory controller  312 , a power controller  313 , an external interface  314 , a graphics processing unit (GPU)  315 , a media processor  316 , a display controller  317 , and a MIPI (Mobile Industry Processor Interface) interface  318 . In this example, the CPU  311 , the memory controller  312 , the power controller  313 , the external interface  314 , the GPU  315 , the media processor  316 , and the display controller  317  are coupled to a system bus  319 , which makes it possible for them to exchange data with one another through this system bus  319 . 
     The CPU  311  processes various pieces of information handled by the smartphone  300  in accordance with a program. The memory controller  312  controls a memory  501  that the CPU  311  uses when performing information processing. The power controller  313  controls the power to the smartphone  300 . 
     The external interface  314  is an interface for communication with an external device, and, in this example, is coupled to a wireless communication section  502  and an image sensor  410 . The wireless communication section  502  performs wireless communication with a mobile phone base station, and includes, for example, a baseband, radio frequency (RF) front-end, etc. The image sensor  410  acquires an image, and includes, for example, a CMOS sensor. 
     The GPU  315  performs image processing. The media processor  316  processes information of voice, text, graphics, etc. The display controller  317  controls a display  504  through the MIPI interface  318 . The MIPI interface  318  transmits an image signal to the display  504 . For example, a YUV or RGB signal or the like may be used as the image signal. The MIPI interface  318  operates on the basis of a reference clock supplied from an oscillation circuit  330  including, for example, a quartz crystal unit. For example, the communication system in any of the above-described embodiments, etc. is applied to this communication system between the MIPI interface  318  and the display  504 . 
       FIG. 74  illustrates a configuration example of the image sensor  410 . The image sensor  410  includes a sensor section  411 , an ISP (image signal processor)  412 , a JPEG (Joint Photographic Experts Group) encoder  413 , a CPU  414 , a RAM (random access memory)  415 , a ROM (read-only memory)  416 , a power controller  417 , an I 2 C (Inter-Integrated Circuit) interface  418 , and a MIPI interface  419 . In this example, these blocks are coupled to a system bus  420 , which makes it possible for them to exchange data with one another through this system bus  420 . 
     The sensor section  411  acquires an image, and includes, for example, a CMOS sensor. The ISP  412  performs a predetermined process on the image acquired by the sensor section  411 . The JPEG encoder  413  generates a JPEG image by encoding the image processed by the ISP  412 . The CPU  414  controls the blocks of the image sensor  410  in accordance with a program. The RAM  415  is a memory that the CPU  414  uses when performing information processing. The ROM  416  stores therein the program executed by the CPU  414 , a setting value obtained through calibration, etc. The power controller  417  controls the power to the image sensor  410 . The I 2 C interface  418  receives a control signal from the application processor  310 . Furthermore, although not illustrated, the image sensor  410  receives a clock signal as well as the control signal from the application processor  310 . Specifically, the image sensor  410  is configured to be able to operate on the basis of clock signals of various frequencies. The MIPI interface  419  transmits an image signal to the application processor  310 . For example, a YUV or RGB signal or the like may be used as the image signal. The MIPI interface  419  operates on the basis of a reference clock supplied from an oscillation circuit  430  including, for example, a quartz crystal unit. For example, the communication system in any of the above-described embodiments, etc. is applied to this communication system between the MIPI interface  419  and the application processor  310 . 
     Application Example 2 
       FIG. 75  illustrates a configuration example of a vehicle control system  600  to which the communication system in any of the above-described embodiments, etc. is applied. The vehicle control system  600  controls the operation of a vehicle, such as a car, an electric car, a hybrid electric car, or a motorcycle. This vehicle control system  600  includes a drive system control unit  610 , a body system control unit  620 , a battery control unit  630 , an outside-vehicle information detecting unit  640 , an in-vehicle information detecting unit  650 , and an integrated control unit  660 . These units are coupled to one another through a communication network  690 . As the communication network  690 , for example, a network that meets any standards such as CAN (Controller Area Network), LIN (Local Interconnect Network), LAN (Local Area Network), and FlexRay® may be used. The units each include, for example, a microcomputer, a storage device, a drive circuit that drives a device to be controlled, a communication I/F, etc. 
     The drive system control unit  610  controls the operation of a device associated with a drive system of the vehicle. A vehicle state detecting section  611  is coupled to the drive system control unit  610 . The vehicle state detecting section  611  detects the state of the vehicle, and includes, for example, a gyrosensor, an acceleration sensor, sensors to detect respective manipulated variables of an accelerator pedal and a brake pedal, the steering angle, etc. On the basis of information detected by the vehicle state detecting section  611 , the drive system control unit  610  controls the operation of a device associated with the drive system of the vehicle. For example, the communication system in any of the above-described embodiments, etc. is applied to this communication system between the drive system control unit  610  and the vehicle state detecting section  611 . 
     The body system control unit  620  controls the operations of on-board various devices, such as a keyless entry system, a power window device, and a variety of lamps. 
     The battery control unit  630  controls a battery  631 . The battery  631  is coupled to the battery control unit  630 . The battery  631  supplies electric power to a motor for driving, and includes, for example, a secondary battery, a cooling device, etc. The battery control unit  630  acquires information of temperature, output voltage, remaining battery, etc. from the battery  631 , and, on the basis of these pieces of information, controls the cooling device, etc. of the battery  631 . For example, the communication system in any of the above-described embodiments, etc. is applied to this communication system between the battery control unit  630  and the battery  631 . 
     The outside-vehicle information detecting unit  640  detects information of the outside of the vehicle. An imaging device  641  and an outside-vehicle information detector  642  are coupled to the outside-vehicle information detecting unit  640 . The imaging device  641  takes an image of the outside of the vehicle, and includes, for example, a ToF (Time-Of-Flight) camera, a stereo camera, a monocular camera, an infrared camera, etc. The outside-vehicle information detector  642  detects information of the outside of the vehicle, and includes, for example, a sensor to detect the weather and climate, a sensor to detect other vehicles, obstacles, pedestrians, etc. around the vehicle, etc. On the basis of the image obtained by the imaging device  641  and the information detected by the outside-vehicle information detector  642 , the outside-vehicle information detecting unit  640  recognizes, for example, the weather and climate, the road condition, etc., and detects objects around the vehicle, such as other vehicles, obstacles, pedestrians, and characters of signs and road markings, or detects the distance between these objects and the vehicle. For example, the communication system in any of the above-described embodiments, etc. is applied to this communication system between the outside-vehicle information detecting unit  640  and the imaging device  641  and the outside-vehicle information detector  642 . 
     The in-vehicle information detecting unit  650  detects information of the inside of the vehicle. A driver state detector  651  is coupled to the in-vehicle information detecting unit  650 . The driver state detector  651  detects the state of a driver, and includes, for example, a camera, a biosensor, a microphone, etc. On the basis of information detected by the driver state detector  651 , the in-vehicle information detecting unit  650  monitors, for example, the driver&#39;s level of tiredness, the driver&#39;s concentration degree, whether or not the driver is asleep at the wheel, etc. For example, the communication system in any of the above-described embodiments, etc. is applied to this communication system between the in-vehicle information detecting unit  650  and the driver state detector  651 . 
     The integrated control unit  660  controls the operation of the vehicle control system  600 . An operation section  661 , a display section  662 , and an instrument panel  663  are coupled to the integrated control unit  660 . The operation section  661  is a part handled by a passenger, and includes, for example, a touch panel, various buttons and switches, etc. The display section  662  displays thereon an image, and includes, for example, a liquid-crystal display panel, etc. The instrument panel  663  displays thereon the state of the vehicle, and includes meters such as a speedometer, various alarm lamps, etc. For example, the communication system in any of the above-described embodiments, etc. is applied to this communication system between the integrated control unit  660  and the operation section  661 , the display section  662 , and the instrument panel  663 . 
     The present technology is described above citing some embodiments and modification examples, and application examples; however, present technology is not limited to these embodiments, etc., and various modifications are possible. 
     For example, in the second and third embodiments, the transmitting device is provided with four output terminals; however, it is not limited to this, and the transmitting device may be provided with three output terminals instead. In this case, the transmitting device is able to transmit data by using signals SIG 1 , SIG 2 , and SIG 3  in the operation mode MA; signals SIG 1 P and SIG 1 N in the operation mode MB; and signals SIGA, SIGB, and SIGC in the operation mode MC. Furthermore, the transmitting device may be provided with, for example, five or more output terminals. Specifically, for example, in a case where the transmitting device is provided with six output terminals, the transmitting device is able to transmit data by using signals SIG 1  to SIG 6  in the operation mode MA; signals SIG 1 P and SIG 1 N, SIG 2 P and SIG 2 N, and SIG 3 P and SIG 3 N in the operation mode MB; and signals SIG 1 A, SIG 1 B, and SIG 1 C and SIG 2 A, SIG 2 B, and SIG 2 C in the operation mode MC. 
     It is to be noted that the effects described in this specification are mere examples and non-limiting, and there may be other effects. 
     It is to be noted that the present technology may have the following configurations. 
     (1) 
     A transmitting device including: 
     a first driver including a first sub-driver unit and a second sub-driver unit, the first driver being configured to be able to set a voltage at a first output terminal, the first sub-driver unit operating on the basis of a first control signal, the second sub-driver unit operating on the basis of, of the first control signal and a second control signal, a signal selected through a first selecting operation; and 
     a controller that controls the first selecting operation. 
     (2) 
     The transmitting device according to (1), further including a second driver including a third sub-driver unit and a fourth sub-driver unit, the second driver being configured to be able to set a voltage at a second output terminal, the third sub-driver unit operating on the basis of, of the first control signal and the second control signal, a signal selected through a second selecting operation, the fourth sub-driver unit operating on the basis of the second control signal, 
     in which the controller also controls the second selecting operation. 
     (3) 
     The transmitting device according to (2), in which 
     the transmitting device has a first operation mode and a second operation mode, and 
     the controller selects:
         in the first operation mode, the first control signal in the first selecting operation and the second control signal in the second selecting operation; and   in the second operation mode, the second control signal in the first selecting operation and the first control signal in the second selecting operation.
 
(4)
       

     The transmitting device according to (2) or (3), in which 
     an output impedance of the first sub-driver unit is lower than an output impedance of the second sub-driver unit, and 
     an output impedance of the third sub-driver unit is lower than an output impedance of the fourth sub-driver unit. 
     (5) 
     The transmitting device according to any of (2) to (4), in which the output impedance of the first sub-driver unit, the output impedance of the second sub-driver unit, the output impedance of the third sub-driver unit, and the output impedance of the fourth sub-driver unit are each configured to be settable. 
     (6) 
     The transmitting device according to any of (2) to (5), further including: 
     a first selector unit that performs the first selecting operation; and 
     a second selector unit that performs the second selecting operation. 
     (7) 
     The transmitting device according to any of (2) to (5), in which 
     the second sub-driver unit further performs the first selecting operation, and 
     the third sub-driver unit further performs the second selecting operation. 
     (8) 
     The transmitting device according to (7), in which 
     the second sub-driver unit includes:
         a fifth sub-driver unit that operates on the basis of the first control signal; and   a sixth sub-driver unit that operates on the basis of the second control signal, and       

     the controller controls the first selecting operation by enabling one of the fifth sub-driver unit and the sixth sub-driver unit. 
     (9) 
     The transmitting device according to any of (2) to (8), further including a multiplexer unit that generates a first signal, a second signal, a third signal, and a fourth signal, 
     in which the first control signal includes the first signal and the second signal, and 
     the second control signal includes the third signal and the fourth signal. 
     (10) 
     The transmitting device according to (9), further including a serializer unit that generates a first serial signal, a second serial signal, a third serial signal, and a fourth serial signal, 
     in which the multiplexer unit generates:
         the first signal on the basis of the first serial signal and the third serial signal;   the second signal on the basis of an inverted signal of the first serial signal and an inverted signal of the third serial signal;   the third signal on the basis of the second serial signal and the fourth serial signal; and   the fourth signal on the basis of an inverted signal of the second serial signal and an inverted signal of the fourth serial signal.
 
(11)
       

     The transmitting device according to (10), in which 
     in a case where the multiplexer unit generates the first signal on the basis of, of the first serial signal and the third serial signal, the first serial signal, the multiplexer unit generates the second signal on the basis of, of the inverted signal of the first serial signal and the inverted signal of the third serial signal, the inverted signal of the first serial signal, the third signal on the basis of, of the second serial signal and the fourth serial signal, the second serial signal, and the fourth signal on the basis of, of the inverted signal of the second serial signal and the inverted signal of the fourth serial signal, the inverted signal of the second serial signal, and 
     in a case where the multiplexer unit generates the first signal on the basis of, of the first serial signal and the third serial signal, the third serial signal, the multiplexer unit generates the second signal on the basis of, of the inverted signal of the first serial signal and the inverted signal of the third serial signal, the inverted signal of the third serial signal, the third signal on the basis of, of the second serial signal and the fourth serial signal, the fourth serial signal, and the fourth signal on the basis of, of the inverted signal of the second serial signal and the inverted signal of the fourth serial signal, the inverted signal of the fourth serial signal. 
     (12) 
     The transmitting device according to (10) or (11), in which the serializer unit generates the first serial signal by sequentially selecting each piece of bit data included in a parallel signal on the basis of a plurality of clock signals that differ from one another in phase. 
     (13) 
     The transmitting device according to (10) or (11), in which the serializer unit includes a shift register. 
     (14) 
     The transmitting device according to any of (2) to (6), further including: 
     a serializer unit that generates a first serial signal, a second serial signal, a third serial signal, and a fourth serial signal; and 
     a multiplexer unit that generates a first signal, a second signal, a third signal, and a fourth signal, 
     in which the first control signal includes the first serial signal and the third serial signal, 
     the second control signal includes the second serial signal and the fourth serial signal, 
     the multiplexer unit generates the first signal on the basis of the first serial signal and the third serial signal, the second signal on the basis of an inverted signal of the first serial signal and an inverted signal of the third serial signal, the third signal on the basis of a first selected signal being, of an inverted signal of the second serial signal and the first serial signal, one selected through the first selecting operation and a second selected signal being, of an inverted signal of the fourth serial signal and the third serial signal, one selected through the first selecting operation, and the fourth signal on the basis of a third selected signal being, of the inverted signal of the first serial signal and the second serial signal, one selected through the first selecting operation and a fourth selected signal being, of the inverted signal of the third serial signal and the fourth serial signal, one selected through the first selecting operation, 
     the first sub-driver unit operates on the basis of the first signal and the second signal, and 
     the second sub-driver unit operates on the basis of the third signal and the fourth signal. 
     (15) 
     The transmitting device according to (14), in which 
     in a case where the multiplexer unit generates the first signal on the basis of, of the first serial signal and the third serial signal, the first serial signal, the multiplexer unit generates the second signal on the basis of, of the inverted signal of the first serial signal and the inverted signal of the third serial signal, the inverted signal of the first serial signal, the third signal on the basis of, of the first selected signal and the second selected signal, the first selected signal, and the fourth signal on the basis of, of the third selected signal and the fourth selected signal, the third selected signal, and 
     in a case where the multiplexer unit generates the first signal on the basis of, of the first serial signal and the third serial signal, the third serial signal, the multiplexer unit generates the second signal on the basis of, of the inverted signal of the first serial signal and the inverted signal of the third serial signal, the inverted signal of the third serial signal, the third signal on the basis of, of the first selected signal and the second selected signal, the second selected signal, and the fourth signal on the basis of, of the third selected signal and the fourth selected signal, the fourth selected signal. 
     (16) 
     The transmitting device according to (14) or (15), in which 
     the multiplexer unit further generates: a fifth signal on the basis of, of the inverted signal of the first serial signal and the second serial signal, a signal selected through the second selecting operation and, of the inverted signal of the third serial signal and the fourth serial signal, a signal selected through the second selecting operation; a sixth signal on the basis of, of the inverted signal of the second serial signal and the first serial signal, a signal selected through the second selecting operation and, of the inverted signal of the fourth serial signal and the third serial signal, a signal selected through the second selecting operation; a seventh signal on the basis of the second serial signal and the fourth serial signal; and an eighth signal on the basis of the inverted signal of the second serial signal and the inverted signal of the fourth serial signal, 
     the third sub-driver unit operates on the basis of the fifth signal and the sixth signal, and 
     the fourth sub-driver unit operates on the basis of the seventh signal and the eighth signal. 
     (17) 
     The transmitting device according to any of (2) to (8), further including a third driver including a seventh sub-driver unit and an eighth sub-driver unit, the third driver being configured to be able to set a voltage at a third output terminal, the seventh sub-driver unit operating on the basis of a third control signal and the eighth sub-driver unit operating on the basis of, of the third control signal and a fourth control signal, a signal selected through a third selecting operation, 
     in which the controller also controls the third selecting operation. 
     (18) 
     The transmitting device according to (17), in which 
     the transmitting device has the first operation mode in which communication is performed by using a single-phase signal, the second operation mode in which communication is performed by using a differential signal, and a third operation mode in which communication is performed by using a signal having three voltage levels: a first voltage level, a second voltage level, and a third voltage level between the first voltage level and the second voltage level, and 
     the controller selects:
         in the first operation mode and the third operation mode, the first control signal in the first selecting operation, the second control signal in the second selecting operation, and the third control signal in the third selecting operation; and   in the second operation mode, the second control signal in the first selecting operation, the first control signal in the second selecting operation, and the fourth control signal in the third selecting operation.
 
(19)
       

     The transmitting device according to (18), in which 
     the first sub-driver unit includes a first switch provided on a path from a first power source to the first output terminal and a second switch provided on a path from a second power source to the first output terminal, 
     the second sub-driver unit includes a third switch provided on a path from the first power source to the first output terminal and a fourth switch provided on a path from the second power source to the first output terminal, and 
     in the third operation mode, the first driver puts all the first switch, the second switch, the third switch, and the fourth switch into off state, thereby setting the voltage at the first output terminal to the third voltage level. 
     (20) 
     The transmitting device according to (18), in which 
     the first sub-driver unit includes a first switch provided on a path from a first power source to the first output terminal and a second switch provided on a path from a second power source to the first output terminal, 
     the second sub-driver unit includes a third switch provided on a path from the first power source to the first output terminal and a fourth switch provided on a path from the second power source to the first output terminal, and 
     in the third operation mode, the first driver puts one of the first switch and the third switch into on state and the other one into off state, and puts one of the second switch and the fourth switch into on state and the other one into off state, thereby setting the voltage at the first output terminal to the third voltage level. 
     (21) 
     The transmitting device according to any of (18) to (10), further including a multiplexer unit that generates a first signal, a second signal, a third signal, a fourth signal, a fifth signal, a sixth signal, a seventh signal, and an eighth signal, 
     in which the first control signal includes the first signal and the second signal, 
     the second control signal includes the third signal and the fourth signal, 
     the third control signal includes the fifth signal and the sixth signal, and 
     the fourth control signal includes the seventh signal and the eighth signal. 
     (22) 
     The transmitting device according to (21), in which 
     in the third operation mode, the first driver selectively sets the voltage at the first output terminal to the first voltage level or the second voltage level in a case where the first signal and the second signal are different from each other; and 
     in the third operation mode, the first driver sets the voltage at the first output terminal to the third voltage level in a case where the first signal and the second signal are equal to each other. 
     (23) 
     The transmitting device according to (21) or (22), further including: 
     a serializer unit that generates eight serial signals including a first serial signal and a second serial signal; and 
     an encoder unit that generates a first encoding signal and a second encoding signal on the basis of the first serial signal and generates a third encoding signal and a fourth encoding signal on the basis of the second serial signal, in the first operation mode and the second operation mode, 
     in which the multiplexer unit generates the first signal on the basis of the first encoding signal and the third encoding signal and generates the second signal on the basis of the second encoding signal and the fourth encoding signal. 
     (24) 
     The transmitting device according to (23), in which in the third operation mode, the encoder unit generates the first encoding signal and the second encoding signal on the basis of, of the eight serial signals, two signals including the first serial signal, and generates the third encoding signal and the fourth encoding signal on the basis of, of the eight serial signals, two signals including the second serial signal. 
     (25) 
     The transmitting device according to (23) or (24), in which 
     in a case where the multiplexer unit generates the first signal on the basis of, of the first encoding signal and the third encoding signal, the first encoding signal, the multiplexer unit generates the second signal on the basis of, of the second encoding signal and the fourth encoding signal, the second encoding signal, and 
     in a case where the multiplexer unit generates the first signal on the basis of, of the first encoding signal and the third encoding signal, the third encoding signal, the multiplexer unit generates the second signal on the basis of, of the second encoding signal and the fourth encoding signal, the fourth encoding signal. 
     (26) 
     The transmitting device according to (23) or (25), in which 
     the first serial signal includes a first sub signal and a second sub signal, 
     the second serial signal includes a third sub signal and a fourth sub signal, and 
     the encoder unit generates the first encoding signal and the second encoding signal on the basis of the first sub signal and the second sub signal, and generates the third encoding signal and the fourth encoding signal on the basis of the third sub signal and the fourth sub signal. 
     (27) 
     The transmitting device according to (26), in which 
     the serializer unit generates the first sub signal and the second sub signal on the basis of a first parallel signal and a second parallel signal, 
     in the first operation mode and the second operation mode, the first parallel signal and the second parallel signal constitute a differential parallel signal, and the first sub signal and the second sub signal constitute a differential signal, and 
     in the first operation mode and the second operation mode, the serializer unit generates the first sub signal and the second sub signal by sequentially selecting each piece of bit data included in the differential parallel signal. 
     (28) 
     The transmitting device according to (27), in which 
     in the third operation mode, the first parallel signal and the second parallel signal are separate signals, 
     in the third operation mode, the serializer unit selects both first bit data included in the first parallel signal and second bit data included in the second parallel signal, 
     in a case where the first bit data and the second bit data are different from each other, the serializer unit generates the first sub signal and the second sub signal that are inverted from each other on the basis of the first bit data and the second bit data, and 
     in a case where the first bit data and the second bit data are equal to each other, the serializer unit generates the first sub signal and the second sub signal that have an equal predetermined signal level. 
     (29) 
     The transmitting device according to any of (18) to (20), further including an encoder unit that generates a first encoding signal, a second encoding signal, a third encoding signal, a fourth encoding signal, a fifth encoding signal, a sixth encoding signal, a seventh encoding signal, and an eighth encoding signal, 
     in which the first control signal includes the first encoding signal and the second encoding signal, 
     the second control signal includes the third encoding signal and the fourth encoding signal, 
     the third control signal includes the fifth encoding signal and the sixth encoding signal, and 
     the fourth control signal includes the seventh encoding signal and the eighth encoding signal. 
     (30) 
     The transmitting device according to (29), further including a multiplexer unit that generates eight signals including a first signal and a second signal, 
     in which the encoder unit generates: 
     in the first operation mode and the second operation mode, the first encoding signal on the basis of the first signal, and the second encoding signal on the basis of the second signal; and 
     in the third operation mode, the first encoding signal on the basis of, of the eight signals, two signals including the first signal, and the second encoding signal on the basis of, of the eight signals, two signals including the second signal. 
     (31) 
     The transmitting device according to (29), further including a multiplexer unit that generates eight signals including a first signal and a second signal, 
     in which the encoder unit generates the first encoding signal and the second encoding signal on the basis of the first signal and the second signal. 
     (32) 
     The transmitting device according to (31), further including a serializer unit that generates eight serial signals including a first serial signal and a second serial signal, 
     in which the first serial signal includes a first sub signal and a second sub signal, 
     the second serial signal includes a third sub signal and a fourth sub signal, and 
     the multiplexer unit generates the first signal on the basis of the first sub signal and the third sub signal, and generates the second signal on the basis of the second sub signal and the fourth sub signal. 
     (33) 
     A transmitting method including: 
     preparing a first control signal and a second control signal; and 
     causing a first sub-driver unit to operate on the basis of the first control signal and a second sub-driver unit to operate on the basis of, of the first control signal and the second control signal, a signal selected through a first selecting operation, thereby setting a voltage at a first output terminal. 
     (34) 
     A communication system provided with 
     a transmitting device, and 
     a receiving device, 
     the transmitting device including: 
     a first driver including a first sub-driver unit and a second sub-driver unit, the first driver being configured to be able to set a voltage at a first output terminal, the first sub-driver unit operating on the basis of a first control signal, the second sub-driver unit operating on the basis of, of the first control signal and a second control signal, a signal selected through a first selecting operation; and 
     a controller that controls the first selecting operation. 
     This application claims the benefit of Japanese Priority Patent Application JP2016-139024 filed with the Japan Patent Office on Jul. 14, 2016, the entire contents of which are incorporated herein by reference. 
     It should be understood by those skilled in the art that various modifications, combinations, sub-combinations, and alterations may occur depending on design requirements and other factors insofar as they are within the scope of the appended claims or the equivalents thereof.