Patent Publication Number: US-2023147703-A1

Title: Hybrid input lna rf frontend architecture

Description:
TECHNICAL FIELD 
     The present disclosure is related to electronic radio frequency (RF) circuits, and more particularly to a hybrid input architecture of an RF frontend (RFFE) that considers different input performance priorities to optimize performance and cost of the RFFE. 
     BACKGROUND 
     Processing of an input RF signal through an RF system (e.g., RFFE) may be provided via a combination of switches, filters and matching circuits, coupled to an amplifier, which in combination may provide an RF processing path for amplification of the input RF signal. In a traditional RFFE architecture used in, for example, a handheld device, different input RF signals corresponding to different frequency bands may require different RF processing paths. When designing an RFFE module, circuit designers may be required to take into consideration cost versus performance tradeoff of the RFFE module while supporting the different frequency bands. 
       FIG.  1 A  shows a prior art RFFE (receive side) architecture ( 100 A) that reduces cost by providing a combined amplification path, CAP, for processing of all of the supported frequency bands. Such frequency bands may include a plurality of (over-the-air) frequency bands (e.g., B a , B b , . . . , B k ) and one or more auxiliary frequency bands (e.g., AUX 1 , AUX 2 ). An RF signal corresponding to each of the frequency bands (e.g., B a , B b , . . . , B k ) is received at the antenna, ANT, and is selectively routed through a respective filter (e.g., a, b, . . . , k) of a filter bank, FB, via an antenna switch, ASW. A switch, B_SEL, selectively couples one of the supported frequency bands (e.g., B a , B b , . . . , B k , AUX), AUX 2  coupled to respective throws of the switch B_SEL) to the combined amplification path, CAP (e.g. coupled to the single pole of the switch B_SEL). For example, as shown in  FIG.  1 A , the switch, B_SEL, may couple an RF signal, RF SEL , corresponding to the selected frequency band, B a , to an input matching circuit, IM, of the combined amplification path, CAP. In turn, an amplifier, AP, and an output matching circuit, OM, of the combined amplification path, CAP, may further process the RF signal, RF SEL , for output of an amplified output RF signal, RF OUT . 
     The prior art RFFE architecture ( 100 A) of  FIG.  1 A  reduces cost of a corresponding RFFE module by reducing a number of components required for processing of the supported frequency bands (e.g., B a , B b , . . . , B k , AUX 1 , AUX 2 ). In particular, use of the combined amplification path, CAP, allows processing of the supported frequency bands via a single input matching circuit, IM, and a single amplifier, AP. Such reduction in the number of components may allow for a reduction in die area, and therefore a (physical) size, of a corresponding RFFE module. On the other hand, an insertion loss (inherent) of the switch, B_SEL, may degrade a noise figure (NF) performance of the RFFE architecture ( 100 A) with respect to all of the supported frequency bands. Furthermore, use of a same input match, IM, and amplifier, AP, may reduce flexibility in optimizing a performance (e.g., matching, gain, power, linearity, etc.) of the RFFE architecture ( 100 A) with respect to a specific frequency band of the supported frequency bands (e.g., B a , B b , . . . , B k , AUX 1 , AUX 2 ). Such performance shortcoming may be addressed by the prior art RFFE architecture ( 100 B) of  FIG.  1 B . 
     The prior art RFFE architecture ( 100 B) of  FIG.  1 B  increases performance of a corresponding RFFE module by providing a dedicated RF amplification path (e.g., DAP a , DAP b , . . . , DAP k , DAP 1 , DAP 2 ) for each of the supported frequency bands (e.g., B a , B b , . . . , B k , AUX 1 , AUX 2 ). Use of such dedicated amplification paths (e.g., DAP a , DAP b , . . . , DAP k , DAP 1 , DAP 2 , coupled to a same output matching circuit, OM) may remove requirement for the switch, B_SEL, of the RFFE architecture ( 100 A) of  FIG.  1 A , and therefore may improve a noise figure (NF) performance of the RFFE architecture ( 100 B). Furthermore, a dedicated input matching circuit (e.g., IM a , IM b , . . . , IM k , IM 1 , IM 2  of a bank of input matching circuits, IMB) and a dedicated amplifier (e.g., AP a , AP b , . . . , AP k , AP 1 , AP 2  of a bank of amplifiers, APB) of the dedicated RF amplification paths (e.g., DAP a , DAP b , . . . , DAP k , DAP 1 , DAP 2 ) may allow increased flexibility in optimizing a performance (e.g., matching, gain, power, linearity, etc.) of the RFFE architecture ( 100 B) with respect to a specific frequency band of the supported frequency bands (e.g., B a , B b , . . . , B k , AUX 1 , AUX 2 ). 
     The increased performance provided by the prior art RFFE architecture ( 100 B) of  FIG.  1 B  over the prior art RFFE architecture ( 100 A) of  FIG.  1 A  may be associated to an increased cost of components used in the dedicated RF amplification paths (e.g., DAP a , DAP b , . . . , DAP k , DAP 1 , DAP 2 ) and an increase in die area, and therefore a (physical) size and cost, of a corresponding RFFE module. 
     Based on the above, it would be clear to a person skilled in the art, that the prior art architectures ( 100 A,  100 B) provide a binary choice between optimizing a performance or a cost of a corresponding RFFE module when considered globally. Teachings according to the present disclosure provide circuit designers and/or system integrators tools that allow flexibility in choice between optimizing a performance or a cost of each individual RF processing path of different frequency bands supported by an RFFE module. Accordingly, by deploying such tools based on specific performance priorities of corresponding input RF signals of the supported frequency bands, performance and cost of the RFFE module may be simultaneously optimized. 
     SUMMARY 
     According to a first aspect of the present disclosure, a multi-input multi-band low noise amplifier (LNA) is presented, comprising: a dedicated RF processing path for processing of an input RF signal of a first frequency band, the dedicated RF processing path comprising: a dedicated cascode amplifier comprising a dedicated input transistor and a dedicated output cascode transistor that is coupled to a high side node; and a shared RF processing path for processing of at least two input RF signals of respective second and third frequency bands, the shared RF processing path comprising: an input band selection switch; and a multi-input shared cascode amplifier comprising a plurality of input transistors and a shared output cascode transistor coupled to the plurality of input transistors, wherein: the shared output cascode transistor is coupled to the high side node, and the input band selection switch is configured to selectively couple each of the at least two input RF signals to a shared input transistor of the plurality of input transistors. 
     According to a second aspect of the present disclosure, a multi-input multi-band low noise amplifier (LNA) is presented, comprising: a dedicated first band RF processing path for processing of a first frequency band RF signal received from an antenna through a dedicated first band filter, the dedicated first band RF processing path comprising: a dedicated first band input matching circuit coupled to a dedicated first band cascode amplifier, the dedicated first band cascode amplifier comprising: a dedicated first band input transistor and a dedicated first band output cascode transistor that is coupled to a high side node; and a shared RF processing path for processing of a second frequency band RF signal received from the antenna through a dedicated second band filter and of a first auxiliary frequency band RF signal that is not received from the antenna, the shared RF processing path comprising: an input band selection switch; a multi-input shared cascode amplifier comprising a plurality of input transistors and a shared output cascode transistor coupled to the plurality of input transistors; and a shared input matching circuit coupled between the input band selection switch and a shared input transistor of the plurality of input transistors, wherein: the shared output cascode transistor is coupled to the high side node, and the input band selection switch is configured to selectively couple one of the second frequency band RF signal or the first auxiliary frequency band RF signal to the shared input transistor. 
     According to a third aspect of the present disclosure, a method for optimizing performance and cost of a receive side of an RF front end (RFFE) is presented, the method comprising: assigning a performance priority to each band of a plurality of frequency bands for processing by the RFFE, the performance priority including a range from low to high; based on the assigning, establishing an RF processing performance for a respective RF processing path of the each band; based on the establishing, realizing the respective RF processing path based on circuit blocks provided by a toolkit; and based on the realizing, optimizing RF processing performance and cost of the RFFE. 
     Further aspects of the disclosure are provided in the description, drawings and claims of the present application. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The accompanying drawings, which are incorporated into and constitute a part of this specification, illustrate one or more embodiments of the present disclosure and, together with the description of example embodiments, serve to explain the principles and implementations of the disclosure. 
         FIG.  1 A  shows a simplified schematic of a prior RFFE architecture that optimizes cost over performance. 
         FIG.  1 B  shows a simplified schematic of a prior RFFE architecture that optimizes performance over cost. 
         FIG.  2 A  shows a simplified schematic of an exemplary embodiment of a combined amplification path comprising a single-input cascode amplifier that may be used in the configuration of  FIG.  1 A . 
         FIG.  2 B  shows a simplified schematic of an exemplary embodiment of dedicated amplification paths comprising a plurality of dedicated single-input cascode amplifiers that may be used in the configuration of  FIG.  1 B . 
         FIG.  3 A  shows a simplified schematic of an exemplary multi-input cascode amplifier comprising a shared cascode configuration. 
         FIG.  3 B  shows a simplified schematic of an exemplary multi-input cascode amplifier comprising a shared cascode configuration with branch decoupling switches. 
         FIG.  3 C  shows a simplified schematic of another exemplary multi-input cascode amplifier comprising a shared cascode configuration with branch decoupling switches. 
         FIG.  4 A  shows a simplified schematic of an input combiner circuit according to an embodiment of the present disclosure. 
         FIG.  4 B  shows an exemplary embodiment of inductors used in input matching circuits. 
         FIG.  5 A  shows various circuit blocks according to the present disclosure that may be used for optimizing performance or cost of an RF processing path of a hybrid input RFFE architecture according to the present disclosure. 
         FIG.  5 B  shows various circuit blocks that may be common to the RF processing paths of hybrid input RFFE architecture according to the present disclosure. 
         FIG.  5 C  shows a decision tree that may be used to realize the hybrid input RFFE architecture according to the present disclosure. 
         FIG.  5 D  shows another decision tree that may be used to realize the hybrid input RFFE architecture according to the present disclosure. 
         FIG.  6 A  shows a block diagram of a hybrid input RFFE architecture according to the present disclosure realized via the decision tree of  FIG.  5 C . 
         FIG.  6 B  shows a simplified schematic of a hybrid input RFFE architecture according to the present disclosure. 
         FIG.  6 C  shows the simplified schematic of the hybrid input RFFE architecture of  FIG.  6 B  with added details related to coupling to an antenna. 
         FIG.  7    shows various process steps of a method according to the present disclosure for optimizing performance and cost of a receive side of an RF front end (RFFE). 
     
    
    
     Like reference numbers and designations in the various drawings indicate like elements. 
     DETAILED DESCRIPTION 
       FIG.  2 A  shows a simplified schematic of an exemplary embodiment of a combined amplification path, CAP, comprising a single-input cascode amplifier, AP, that may be used in the configuration of  FIG.  1 A  described above. The combined amplification path, CAP, receives a selected input RF signal, RF SEL , and outputs an amplified RF signal, RF OUT , to a load, R L . The selected input RF signal, RF SEL , is coupled to an input transistor, M 1 , of the single-input cascode amplifier, AP, through an input matching circuit, IM, which as shown in  FIG.  2 A , may include a series-connected inductor, L IN . Input matching to the amplifier, AP, may be provided via a combination of the input matching circuit, L IN , and a degeneration inductor, L DEG , coupled to a source of the input transistor, M 1 . For operation across the plurality of supported frequency bands (e.g., B a , B b , . . . , B k , AUX 1 , AUX 2  of  FIG.  1 A ), the degeneration inductor, LDEG, may be adjustable (e.g., tunable, configurable, programmable, etc.), for example, via inductance selection switches as shown in  FIG.  2 A . 
     With continued reference to  FIG.  2 A , the amplifier, AP, may include one or more cascode transistors (e.g., M 2 ) in series connection with the input transistor, M 1 . A person skilled in the art is well aware of a principle of operation of the cascode configuration, CAS, comprising a common-source input transistor (e.g., M 1 ) coupled to one or more common-gate (cascode) transistors (e.g., M 2 ). Biasing of the cascode configuration, CAS, may be provided via a supply voltage, VDD, and a reference ground, Gnd, coupled between a high side node, CAS OUT  (e.g., drain of output cascode transistor M 2 ) and a low side node, CAS LS  (e.g., source of the input transistor M 1 ) of the cascode configuration, CAS. As shown in  FIG.  2 A , the high side node, CAS OUT , may be coupled to the supply voltage, V DD , through an output network, OCN, and the low side node, CAS LS , may be coupled to the reference ground, Gnd, through the degeneration inductor, L DEG . Furthermore, gate voltages (e.g., V G1 , V G2 , etc.) to gates of the transistors (e.g., M 1 , M 2 , etc.) may control a DC current (e.g., amplifier gain) through the cascode configuration, CAS, as well as operating conditions (i.e., biasing points) of each of the transistors (e.g., M 1 , M 2 , etc.). 
     The output network, OCN, of  FIG.  2 A  may include at least one inductor, L OCN , in series connection with the cascode configuration, CAS. Similar to the inductor, L DEG , in some embodiments, the inductor, L OCN , may be adjustable (e.g., via switches shown in  FIG.  2 A ). In some embodiments, the output network, OCN, may include an adjustable capacitor (e.g., C OCN ) and/or an adjustable resistor (e.g., R OCN ) in parallel with the inductor, L OCN . Elements (e.g., L OCN , C OCN , LR OCN ) of the output network, OCN, combined with the output matching circuit, OM, may be used to provide gain and/or output matching that is specific to a frequency band of the plurality of supported frequency bands (e.g., B a , B b , . . . , B k , AUX 1 , AUX 2  of  FIG.  1 A ). 
     As shown in  FIG.  2 A , the output matching circuit, OM, coupled to the high side node, CAS OUT , may include at least one series-connected capacitor, C OUT  (that may also be used as a DC decoupling capacitor). In some embodiments, the capacitor, C OUT , may be an adjustable capacitor for providing output matching that is specific to a frequency band of the plurality of supported frequency bands (e.g., B a , B b , . . . , B k , AUX 1 , AUX 2  of  FIG.  1 A ). 
     As described above with reference to  FIG.  1 A , the combined amplification path, CAP, of  FIG.  2 A  may not provide (complete) flexibility in optimizing performance with respect to a specific frequency band of the plurality of supported frequency bands (e.g., B a , B b , . . . , B k , AUX 1 , AUX 2  of  FIG.  1 A ). For example, no flexibility may be provided with respect to elements (e.g., L IN ) of the input matching circuit, IM, or with respect to elements (e.g., M 1 , M 2 ) of the cascode configuration, CAS. A person skilled in the art would know that, for example, value and/or type (in-circuit vs. out-of-circuit/SMD) of the inductor, L IN , and/or characteristics (e.g., size, width) of the transistors (M 1 , M 2 ) may affect performance of the cascode configuration, CAS, differently for the different supported frequency bands (e.g., B a , B b , . . . , B k , AUX 1 , AUX 2  of  FIG.  1 A ). 
       FIG.  2 B  shows a simplified schematic of an exemplary embodiment of dedicated amplification paths (e.g., IM b , CAS b , OCN, L DEG  associated to frequency band B b ) comprising a plurality of dedicated single-input cascode amplifiers (e.g., CAS b , OCN, L DEG  associated to frequency band Bb) that may be used in the configuration of  FIG.  1 B  described above. A person skilled in the art would clearly realize that the configuration ( 200 B) of  FIG.  2 B  is based on the configuration described above with reference to  FIG.  2 A  by providing dedicated input matching circuits (e.g., IM a , IM b , . . . , IM k , IM 1 , IM 2 ) coupled to respective dedicated cascode configurations (e.g., CAS a , CAS b , . . . , CAS k , CAS 1 , CAS 2 ) that are coupled (e.g., via nodes CAS OUT  and CAS LSL ) to common elements (e.g., OCN, L DEG ) to provide respective dedicated amplification paths for each of the supported frequency bands (e.g., B a , B b , . . . , B k , AUX 1 , AUX 2 ). 
     With continued reference to  FIG.  2 B , considering the dedicated amplification path (IM b , CAS b , OCN, L DEG ) associated to the frequency band, B b , the input matching circuit, IM b , comprising for example a series-connected inductor, L INb , receives an input RF signal at the frequency band, B b , and converts it to an RF signal, RF b , that is fed to the input transistor, M 1   b , of the cascode configuration, CAS b . In turn, the cascode configuration CAS b , comprising transistors (M 1   b , M 2   b ) coupled between the supply voltage, V DD , and the reference ground, Gnd, via high side and low side nodes, CAS OUT  and CAS LS , amplifies the RF signal, RF b , for output as RF OUT  through the output matching circuit, OM, that is coupled to the load, R L . While amplifying/processing the frequency band, B b , other cascode configurations (e.g., CAS H , n≠b) associated to other frequency bands (e.g., B n , n≠b) may be deactivated via, for example, a gate biasing voltage to one or more of the transistors (e.g., M 1   n  and/or M 2   n  n≠b). 
     As shown in  FIG.  2 B , the dedicated amplification paths include respective dedicated cascode configurations (e.g., CAS a , CAS b , . . . , CAS k , CAS 1 , CAS 2 ) that are coupled in parallel between the high side node, CAS OUT , and the low side node, CASES, and configured to receive dedicated RF signals (e.g., RF a , RF b , . . . , RF k , RF 1 , RF 2 ) through dedicated input matching circuits (e.g., IM a , IM b , . . . , IM k , IM 1 , IM 2 ), and output amplified versions thereof through common elements (e.g., OCN, OM) coupled to the high side node, CAS OUT . Accordingly, the configuration shown in  FIG.  2 B  overcomes shortcomings of the configuration of  FIG.  2 A  described above by allowing flexibility in choice of elements of the input matching circuits (e.g., IM a , IM b , . . . , IM k , IM 1 , IM 2 ) and/or of elements/transistors of the cascode configurations (e.g., CAS a , CAS b , . . . , CAS k , CAS 1 , CAS 2 ), at the expense of added cost (e.g., cost of added elements and larger die area). 
     As described above, while amplifying/processing the frequency band, B b , other cascode configurations (e.g., CAS H , n≠b) associated to other frequency bands (e.g., B n , n≠b) may be deactivated via, for example, a gate biasing voltage to one or more of the transistors (e.g., M 1   n  and/or M 2   n  n≠b). For example, by applying respective gate voltages to the (output) cascode transistors (M 2   n  n≠b) such transistors can be turned OFF, and therefore the corresponding cascode configurations (e.g., CAS n , n≠b) can be deactivated (e.g., no conduction through the cascode configurations). However, while turned OFF, the cascode transistors (M 2   n  n≠b) may present a capacitive load to the high side node, CAS OUT , which in turn may affect performance (e.g., linearity) of the frequency band, B b , being processed. In other words, the dedicated amplification paths provided by the configuration of  FIG.  2 B  may introduce some undesired effects that can degrade an optimal performance of a specific frequency band. 
     Teachings according to the present disclosure allow to consider performance priorities of the supported frequency bands and tailor/design/customize respective RF processing paths to achieve desired/specific performances. Performance priority of a frequency band may be in view of, for example, a minimum required sensitivity provided by the corresponding RF processing path which may be achieved by controlling/selecting elements of the RF processing path that may impact sensitivity. Such elements may include elements of the RF processing path that may impact/degrade noise figure (i.e., signal-to-noise figure) such as, for example, insertion loss introduced by switches, or a Q-factor of an inductor used, for example, in an input matching circuit. In other words, by considering a performance priority of a frequency band, a specific performance to be provided by a corresponding RF processing path may not necessarily require a dedicated RF processing path shown in the configuration of  FIG.  2 B , rather, a combined RF processing path according to the configuration of  FIG.  2 A  may be sufficient. Teaching according to the present disclosure provide the tools (e.g.,  FIGS.  5 A- 5 C  later described) that can be used to customize the respective RF processing paths to achieve the desired/specific performances. 
     Other elements that may impact a performance of an RF processing path may include elements of other RF processing paths. For example, considering the configuration of  FIG.  2 B , as described above, output cascode transistors (M 2   n  n≠b) of deactivated cascode configurations (e.g., CAS n , n≠b) coupled to the high side node, CAS OUT , can affect/degrade performance of the activated cascode configuration (e.g., CAS b ).  FIG.  3 A  shows a multi-input cascode amplifier ( 300 A) comprising a branched/shared cascode configuration (e.g., SCAS) that may be used to reduce a number of output cascode transistors coupled to the high side node, CAS OUT , while supporting a same number of frequency bands (e.g., input RF signals). 
     As shown in  FIG.  3 A , the shared cascode configuration, SCAS, may be provided by coupling (e.g., connecting) a source of a (shared) cascode transistor (e.g., M 2   2 ) to drains of at least two input transistors (e.g., Mlk, . . . , M 12 ). In other words, the transistors of the shared cascode configuration, SCAS, form a tree structure that connects a shared cascode transistor (e.g., M 2   2 ) to at least two transistors located at a level below a level of the shared cascode transistor. In this context, levels of the transistors being defined by their positions within a stack of transistors (e.g., M 1   k , . . . , M 1   2 , M 2   2 ) that forms the shared cascode configuration, SCAS, with a first level (e.g., input level) corresponding to the input transistors (e.g., M 1   k , . . . , M 1   2 ) having respective sources coupled to the low side node, CAS LS , and the last level (e.g., output level) corresponding to the output transistor (e.g., M 2   2 ) having a drain coupled to the high side node, CAS OUT . It should be noted that although the shared cascode configuration, SCAS, of  FIG.  3 A  includes two levels, teachings according to the present disclosure may equally apply to configurations that include more than two levels, such as three levels or more (e.g., input level, intermediate cascode levels, and output level), wherein a corresponding tree structure may be provided by one or more shared cascode transistors located at different levels. 
     With continued reference to  FIG.  3 A , by using the shared cascode configuration, SCAS, for processing of, for example, frequency bands (e.g., B k , . . . , AUX 2 ) having lower performance priorities, increased performance may be provided to the dedicated RF processing paths (e.g., using dedicated cascode configurations CAS a , CAS b , . . . , etc.) having, for example, higher performance priorities. In other words, the shared cascode configuration, SCAS, and the dedicated cascode configuration (e.g., CAS a , CAS b , . . . , etc.) shown in  FIG.  3 A  may be considered as elements that are part of a toolkit according to the present disclosure that can be used to customize the RF processing paths of the supported frequency bands (e.g., B a , B b , . . . , B k , . . . , AUX 2 ) to achieve the desired/specific performances. 
       FIG.  3 B  shows a simplified schematic of a multi-input cascode amplifier ( 300 B) comprising a shared cascode configuration, SCAS, as described above with reference to  FIG.  3 A . The configuration of  FIG.  3 B  further includes series switches (e.g., SW 2a , SW 2b , SW 22 ) that may be coupled between (output nodes of) each of the cascode configurations (CAS a , CAS b , SCAS) and the high side node, CAS OUT , and/or series switches (e.g., SW 1k , . . . , SW 12 ) that may be coupled between the shared cascode transistor (e.g., M 2   2 ) and the lower level (input) transistors (e.g., M 1   k , . . . , M 1   2 ). Such switches may be used for selective activating/deactivating of corresponding RF processing paths instead (or in addition) of use of gate voltages as described above. Use of such switches may be advantageous since, in contrast to transistors (e.g., M 1   k , . . . , M 1   2 , M 1   2 ) used as active elements of an amplifier, characteristics of the transistors used to form such switches may be optimized for operation as a switch with no regards to operation as an amplifier. As known to a person skilled in the art, such switches may be designed to provide a low ON resistance to reduce attenuation of a conducted RF signal when the RF processing path containing a switch is activated, and a low OFF capacitance to reduce capacitive loading on other processing paths when the RF processing path containing the switch is deactivated. It should be noted that although  FIG.  3 B  shows each of the available RF processing paths including at least one switch, according to some embodiments of the present disclosure one or more of the RF processing paths may not include any switch. This is shown in the exemplary configuration ( 300 C) of  FIG.  3 C , wherein the RF processing path for the frequency band, B a , does not include a switch coupled between a respective cascode configuration, CAS a , and the high side node, CAS OUT . Or in other words, the cascode configuration, CAS a , (i.e., output cascode transistor M 2   a ) is unconditionally coupled to the high side node, CAS OUT , whereas, for example, the cascode configuration, CAS b , (i.e., output cascode transistor M 2   b ) and the shared cascode configuration, SCAS, (i.e., output cascode transistor M 2   2 ) are selectively coupled to the high side node, CAS OUT , via respective switches SW 2b  and SW 22 . The configuration ( 300 C) of  FIG.  3 C  may allow increased performance for processing of the frequency band, B a , when compared to the performance provided for processing of the frequency band, B b . 
       FIG.  4 A  shows a simplified schematic of an input combiner circuit, ICN, according to an embodiment of the present disclosure that may be used to combine processing paths of at least two frequency bands to a common/shared processing path. For example, as shown in  FIG.  4 A , a band selection switch, B_SEL, may combine processing paths for the frequency bands B k  and AUX 1  to a common processing path that includes one input match circuit (e.g., IM k ). In the configuration ( 400 A) shown in  FIG.  4 A , a performance priority of the bands Bk and AUX 1  may be lower than respective performance priorities of the bands B a , B b , and AUX 2 . Such lower performance priority may allow the bands Bk and AUX 1  to be subjected, for example, to a higher insertion loss provided by the switch, B_SEL, and by a Q-factor of the input match circuit, IM k  (which cannot be optimized across both frequency bands). On the other hand, the lack of a switch and provision of dedicated input matching circuits (e.g., IM a , IM b , IM 2 ), may allow higher performance RF processing paths for the respective frequency bands (e.g., B a , B b , AUX 2 ) having higher performance priorities. 
     The configuration ( 400 ) of  FIG.  4 A  shows processing of the supported frequency bands (e.g., B a , B b , . . . , B k , AUX 1 , AUX 2 ) for provision of the RF signals (RF a , RF b , . . . , RF k , RF 2 ) that may be input to the cascode configurations (e.g., CAS a , CAS b , . . . , SCAS) of any one of the configurations shown in  FIG.  3 A ,  FIG.  3 B  or  FIG.  3 C . In particular, RF signals (e.g., RF a , RF b ) of the higher performance priority frequency bands (e.g., B a , B b ) may be processed through dedicated cascode configurations (e.g., CAS a , CAS b ), the (combined) RF signal (e.g., RF k ) of the lower performance priority frequency bands (e.g., B k , AUX 1 ) may be processed through one branch (e.g., M 1   k , M 2   2 ) of the shared cascode configuration, SCAS, and the RF signal (e.g., RF 2 ) of the higher performance priority frequency band (e.g., AUX 2 ) may be processed through another branch (e.g., M 1   2 , M 2   2 ) of the shared cascode configuration, SCAS. 
     With continued reference to  FIG.  4 A  in view of  FIGS.  3 A- 3 C , routing of the higher performance priority frequency bands (e.g., B a , B b ) through the respective dedicated cascode configurations (e.g., CAS a , CAS b ) and of the higher performance priority frequency band (e.g., AUX 2 ) through the shared cascode configuration, SCAS, further differentiates the higher performance priorities based on a highest performance priority wherein no sharing of a cascode configuration is provided, and a relatively lower performance priority wherein sharing of the cascode configuration is provided. In other words, teachings according to present disclosure is based on a multitier approach that assigns different tiers to different (groups of) frequency bands, each tier being assigned to a different set/combination of elements/circuits from a toolkit to tailor/design/customize an RF processing path with a desired/specific performance. A first tier (e.g., tier one, highest performance priority) may be assigned to the frequency bands (e.g., B a , B b ) which may not share the input matching circuit and the cascode configuration; a second tier (e.g., tier two, medium or lower performance priority) may be assigned to the frequency bands (e.g., AUX 2 ) which may not share the input matching circuit but may share the cascode configuration; and a third tier (e.g., tier three, lowest performance priority) may be assigned to the frequency bands (e.g., B k , AUX 1 ) which may share the input matching circuit and the cascode configuration. 
       FIG.  4 B  shows an exemplary embodiment of inductors (e.g., LIN a , LIN b , LIN k , LIN 2 ) used in respective input matching circuits (e.g., IM a , IM b , IM k , IM 2 ). A person skilled in the art would know that in some (traditional) RF frequency range of operation, optimal value of respective Q-factors of the inductors (e.g., L INa , L INB , L INk , L IN2 ), and therefore optimal noise figure performance provided by such inductors when used in matching circuits, may be provided via fixed value SMD (surface mount device) inductors. In other words, via out-of-circuit inductors that may be coupled/fixated/soldered to the respective RF processing paths via bumps (e.g., B 1  and B 2  shown in  FIG.  4 B ) formed on the RFFE module. As known to a person skilled in the art, provision of such bumps (e.g., B 1 , B 2 ) may require considerable die area which can therefore affect size and cost of the RFFE module. 
     The multitier approach according to the present disclosure may allow to reduce cost/size of tier three frequency bands by reducing a number of inductors of the input matching circuits of the corresponding RF processing paths via the input combiner circuit, ICN, shown in  FIG.  4 B . On the other hand, the multitier approach according to the present disclosure may allow to increase performance of tiers one and two frequency bands via dedicated inductors (e.g., L INa , L INb , L IN2 ) of dedicated input matching circuits (e.g., IM a , IM b , IM 2 ) shown in  FIG.  4 B . It should be noted that teachings according to the present disclosure are not limited to SMD inductors, and therefore for (higher) frequency ranges of operation where performance of such SMD inductors degrade, in-circuit inductors (e.g., per  FIG.  4 A ) that do not require bumps may be used. As known by a person skilled in the art, such in-circuit inductors may be formed via appropriate routing geometries of traces/conductors in a circuit 
       FIG.  5 A  shows various circuit blocks (e.g., a, b, c, d, s) according to the present disclosure that may be used for optimizing performance or cost of an RF processing path of a hybrid input RFFE architecture according to the present disclosure. Such circuit blocks (e.g., circuits with specific functionalities) are based on the above description with reference to  FIGS.  3 - 4   , and include: a dedicated input matching circuit, DIN, represented by the circuit block (a); an input combiner circuit, ICN, represented by the circuit block (b); a dedicated cascode amplifier/configuration represented by the circuit block (c); and a shared cascode amplifier/configuration represented by the circuit block (d). The circuit blocks (a, b, c, d, s) may be considered part of the toolkit according to the present teachings that may be used to tailor/design/customize an RF processing path with a desired/specific performance according to the multitier approach described above. In particular, each RF processing path may include a combination of one of (a) or (b), with one of (c) or (d). Furthermore, each RF processing path may be further combined with the circuit block (s). In turn, such combination may be coupled to the common circuit blocks (e, f, g) (or instead to e′, g) shown in  FIG.  5 B  to complete the RF processing path. 
       FIG.  5 B  shows various circuit blocks (e.g., e, f, g, e′) that may be common to the RF processing paths of hybrid input RFFE architecture according to the present disclosure. Such circuit blocks are based on the above description with reference to  FIGS.  3 - 4   , and include: an output combining network, OCN, represented by the circuit block (e); an output matching circuit, OM, represented by the circuit block (f); and a degeneration inductor, L DEG , represented by the circuit block (g). As shown in  FIG.  5 B , the blocks (e) and (f) may be combined to form an output combining and matching network, OCMN, that is represented by the circuit block (e′). 
     The RF processing paths of the hybrid input RFFE architecture according to the present disclosure may be realized by combining one of the circuit block pairs (a, c), (a, d) or (b, d) of  FIG.  5 A  with the common circuit blocks (e, f, g) of  FIG.  5 B , wherein a selection of the circuit block pairs for realizing a given RF processing path may be based on the multitier approach according to the present disclosure described above, and summarized in the decision tree ( 500 C) shown in  FIG.  5 C . As shown in  FIG.  5 C , realization of each of the RF processing paths may be based on at least two decisions represented by decision blocks ( 510 ) and ( 520 ). Decision block ( 510 ) establishes whether or not the RF processing path is of (e.g., associated to) a highest performance priority (e.g., tier one), and decision block ( 520 ) establishes whether or not the RF processing path is of (e.g., associated to) the lowest performance priority (e.g., tier three). It should be noted that such decisions may be equivalent to requirement or not for a dedicated cascode configuration (e.g., decision block  510 ), and requirement or not for a dedicated input matching circuit (e.g., decision block  520 ). 
     With continued reference to  FIG.  5 C , according to one exemplary embodiment of the present disclosure, if the top decision block ( 510 ) establishes that the RF processing path is of the highest performance priority (e.g., tier one), then the RF processing path may be assigned (e.g., realized via) circuit blocks (a, c) coupled to the common circuit blocks (e, f, g). If the combination of the decision blocks ( 510 ) and ( 520 ) establish that the RF processing path is of the medium performance priority (e.g., not of the lowest or highest performance priority, tier two), then the RF processing path may be assigned (e.g., realized via) circuit blocks (a, d) coupled to the common circuit blocks (e, f, g). On the other hand, if the combination of the decision blocks ( 510 ) and ( 520 ) establish that the RF processing path is of the lowest performance priority (e.g., tier three), then the RF processing path may be assigned (e.g., realized via) circuit blocks (b, d) coupled to the common circuit blocks (e, f, g). 
     In an alternative embodiment according to the present disclosure and as shown in the decision tree ( 500 D) of  FIG.  5 D , if the top decision block ( 510 ) establishes that the RF processing path is of a higher performance priority (e.g., tier one as described above, or a tier  1 . 5  that is higher than the tier  2  but lower than the tier  1 ), then the RF processing path may be assigned (e.g., realized via) circuit blocks (a, c) coupled to the common circuit blocks (e, f, g). Furthermore, distinction between the tier  1  (highest priority) or tier  1 . 5  (higher priority without being the highest priority) may be made via the decision block ( 530 ). Based on the outcome of the decision block ( 530 ), for the highest priority RF processing path, the circuit blocks (a, c) may be coupled to the common circuit block (e) directly and therefore without use of a series switch provided by the circuit block (s). On the other hand, for the higher (but not highest) priority RF processing path, the circuit blocks (a, c) may be coupled to the common circuit block (e) through the series switch provided by the circuit block (s). As described above (e.g., with reference to  FIG.  3 C ), coupling of RF processing paths other than a highest priority RF processing path to the common circuit block (e) through the series switch provided by the circuit block (s) can allow reducing off (path) capacitances presented to the highest priority RF processing path at the high side node CAS OUT . Accordingly, as shown in the decision tree ( 500 D) of  FIG.  5 D , all of the RF processing paths that are not of the highest priority are coupled to the common circuit block (e) through a series switch provided by the circuit block (s). 
       FIG.  6 A  shows a block diagram of a hybrid input RFFE architecture ( 600 A) according to the present disclosure realized via the decision tree of  FIG.  5 C . Accordingly, RF processing paths corresponding to the highest performance priority (e.g., tier one) frequency bands (Bi, . . . , B k−1 ) are realized via respective dedicated circuit blocks (a) (e.g., DIN 1 , . . . , DIN k−1 ), coupled to respective dedicated circuit blocks (c) (e.g., CAS 1 , . . . , CASk k−1 ), coupled to common circuit blocks (e, f, g) (e.g., OCN, OM, LDEG), or to common circuit blocks (e′, g) (e.g., OCMN, L DEG ). The RF processing path corresponding to the medium performance priority (e.g., tier two) frequency band, B k , is realized via a dedicated circuit block (a) (e.g., DIN k ), coupled to an input transistor (e.g., M IN1 ) of a shared circuit block (d) (e.g., SCAS), and coupled via a shared output cascode transistor (e.g., M OUT ) of the shared circuit block (d) to the common circuit blocks (e′, g). Finally, the RF processing paths corresponding to the lowest performance priority (e.g., tier three) frequency bands, (B k+1 , . . . , B n ) are realized via two shared circuit blocks (b) (e.g., ICN 1 , ICN 2 ), coupled to respective input transistors (e.g., M IN2 , M IN3 ) of the shared circuit block (d) (e.g., SCAS), and coupled via the shared output cascode transistor (e.g., M OUT ) of the shared circuit block (d) to the common circuit blocks (e′, g). It should be noted that the block diagram of  FIG.  6 A  shows an exemplary architecture which may be expanded to support any number of frequency bands, including zero, within any of the tiers. 
       FIG.  6 B  shows a simplified schematic of a hybrid input RFFE architecture ( 600 B) according to the present disclosure. In particular, the architecture ( 600 B) is based on application of the decision tree of  FIG.  5 C  on the frequency bands (e.g., B a , B b , . . . , B k , AUX 1 , AUX 2 ) supported by the prior art RFFE architectures shown in  FIG.  1 A and  1 B . Accordingly, the tier one frequency bands (B a , B b ) are processed via respective dedicated RF processing paths provided by dedicated input matching circuits (IM a , IM b ) (respectively comprising inductors L INa  and L INb ) that are respectively coupled to dedicated cascode amplifier configurations (CAS a , CAS b ); the tier two frequency band, AUX 2 , is processed via a dedicated input matching circuit (e.g., IM 2  comprising inductor L IN2 ) coupled to a dedicated input (e.g., input transistor M 1   2 ) of a shared cascode configuration, SCAS; and the tier three frequency bands (B e , AUX 1 ) are processed via a selection switch, B_SEL, coupled to a shared input matching circuit (e.g., IM k  comprising inductor L INk ) of an input combiner network, ICN, coupled to a dedicated input (e.g., input transistor M 1   k ) of the shared cascode configuration, SCAS. Furthermore, each of the RF processing paths is coupled to the output combiner network, OCN, and to the output matching circuit, OM, via the high side node, CAS OUT , and to the degeneration inductor, LDEG, via the low side node, CAS LS . 
     With continued reference to  FIG.  6 B , amplification of the RF signals (e.g., RF a , RF b , . . . , RF k , RF 2 ) associated to the supported frequency bands (e.g., B a , B b , . . . , B k , AUX 1 , AUX 2 ) may be provided via a multi-input single-output cascode low noise amplifier (e.g., CAS a , CAS b , SCAS, operating as an LNA) comprising a combination of stacked transistors (e.g., M 1   a , M 1   b , M 1   k , M 1   2 , M 2   a , M 2   b , M 2   2 ) that include input transistors (e.g., M 1   a , M 1   b , M 1   k , M 1   2 ) coupled to corresponding output cascode transistors (e.g., M 2   a , M 2   b , M 2   2 ). As can be seen in  FIG.  6 C , RF signals (e.g., RF a , RFb) corresponding to tier one frequency bands (e.g., B a , B b ) are amplified via input transistors (e.g., M 1   a , M 1   b ) coupled to respective output cascode transistors (e.g., M 2   a , M 2   b ) of the multi-input single-output amplifier (CAS a , CAS b , SCAS). On the other hand, RF signals (e.g., RF k , RF 2 ) corresponding to tier two or three frequency bands (e.g., B c , AUX 1 , AUX 2 ) are amplified via input transistors (e.g., M 1   k , M 1   2 ) coupled to a single output cascode transistor (e.g., M 2   2 ) of the multi-input single-output amplifier (CAS a , CAS b , SCAS). In other words, amplification of the tier one frequency bands (e.g., B a , Bb) is provided via dedicated output cascode transistors (e.g., M 2   a , M 2   b ), whereas amplification of the tier two or three frequency bands (e.g., B c , AUX 1 , AUX 2 ) is provided via a shared output cascode transistor (e.g., M 2   2 ). 
       FIG.  6 C  shows the simplified schematic of the hybrid input RFFE architecture of  FIG.  6 B  with added details related to coupling to an antenna, ANT, via an antenna switch, ASW, as described above with reference to  FIG.  1 A . An RF signal corresponding to each of the frequency bands (e.g., B a , B b , B c ) is received at the antenna, ANT, and is selectively routed through a respective filter (e.g., a, b, c) of a filter bank, FB, via the antenna switch, ASW. As understood by a person skilled in the art, the filters (e.g., a, b, c) may be of a variety of different types known in the art with performance characteristics, including insertion loss, that may be based on the type and/or a (bandpass) frequency range of a filter. In other words, the filters (a, b, c) associated to the frequency bands (B a , B b , B c ) may have different RF performances which may impact sensitivity provided by the corresponding RF processing paths at different degrees. Accordingly, information about quality of the filters (e.g., a, b, c) used for processing of the frequency bands (e.g., B a , B b , B c ) may be used to assign a performance priority to the frequency bands. In the exemplary configuration ( 600 C) shown in  FIG.  6 C , over-the-air frequency bands (B a , B b ) may be processed by filters (a, b) that may have a lower insertion noise performance (e.g., higher insertion loss) compared to the filter c used for processing the over-the-air band, B c . Accordingly, since the filters (a, b) may consume a larger portion of an available sensitivity budget of corresponding RF processing paths compared to the filter c, a higher performance priority (e.g., tier one) may be assigned to the frequency bands (B a , B b ), and a lower performance priority (e.g., tier three) may be assigned to the frequency band, B c . Accordingly, teachings according to the present disclosure may include equalization of sensitivity across the supported frequency bands at a lower possible cost (e.g., via usage of shared input matchings circuits and/or shared cascode configurations when possible). 
     With continued reference to  FIG.  6 C , auxiliary frequency bands (AUX 1 , AUX 2 ) may include different frequency ranges of operation. These may include, for example, a narrow frequency range (e.g., single-band) similar to one of the over-the-air frequency bands (B a , B b , B c ), or a broader/wider frequency range (e.g., multi-band) which accordingly may require special care in a corresponding input matching circuit. Furthermore, such auxiliary frequency bands may be pre-conditioned and therefore may not be processed by filters as shown in  FIG.  6 C . Because AUX 1  and AUX 2  are not processed by a filter, they may not be subjected to a corresponding filter insertion loss, and therefore such signals may be assigned a lower performance priority (e.g., tier two or three). Assuming that AUX 1  includes a narrow frequency range of operation and AUX 2  a broader frequency range of operation, then as shown in  FIG.  6 C , AUX 1  may be processed via the shared input matching circuit, IM k , of the input combiner network, ICN, whereas AUX 2  may be processed via a dedicated input matching circuit, IM 2  (that may include, for example, an adjustable inductor, L IN2 ). In other words, a medium performance priority (e.g., tier two) may be assigned to AUX 2 , and a lowest performance priority (e.g., tier three) may be assigned to AUX 1 . Accordingly, (a priori) assignment of the performance priority to a specific frequency band may not be solely based on band-specific elements (e.g., filters a, b, c), but may also be based on information about spectral content of the frequency band, and/or any other band specific parameter that may impact processing of a corresponding RF signal. 
       FIG.  7    is a process chart ( 700 ) showing various steps of a method according to the present disclosure for optimizing performance and cost of a receive side of an RF front end (RFFE). As can be seen in the process chart ( 700 , such steps include: assigning a performance priority to each band of a plurality of frequency bands for processing by the RFFE, the performance priority including a range from low to high, per step ( 710 ); based on the assigning, establishing an RF processing performance for a respective RF processing path of the each band, per step ( 720 ); based on the establishing, realizing the respective RF processing path based on circuit blocks provided by a toolkit, per step ( 730 ); and based on the realizing, optimizing RF processing performance and cost of the RFFE, per step ( 740 ). 
     The term “MOSFET”, as used in this disclosure, includes any field effect transistor (FET) having an insulated gate whose voltage determines the conductivity of the transistor, and encompasses insulated gates having a metal or metal-like, insulator, and/or semiconductor structure. The terms “metal” or “metal-like” include at least one electrically conductive material (such as aluminum, copper, or other metal, or highly doped polysilicon, graphene, or other electrical conductor), “insulator” includes at least one insulating material (such as silicon oxide or other dielectric material), and “semiconductor” includes at least one semiconductor material. 
     As used in this disclosure, the term “radio frequency” (RF) refers to a rate of oscillation in the range of about 3 kHz to about 300 GHz. This term also includes the frequencies used in wireless communication systems. An RF frequency may be the frequency of an electromagnetic wave or of an alternating voltage or current in a circuit. 
     Various embodiments of the invention can be implemented to meet a wide variety of specifications. Unless otherwise noted above, selection of suitable component values is a matter of design choice. Various embodiments of the invention may be implemented in any suitable integrated circuit (IC) technology (including but not limited to MOSFET structures), or in hybrid or discrete circuit forms. Integrated circuit embodiments may be fabricated using any suitable substrates and processes, including but not limited to standard bulk silicon, high-resistivity bulk CMOS, silicon-on-insulator (SOI), and silicon-on-sapphire (SOS). Unless otherwise noted above, embodiments of the invention may be implemented in other transistor technologies such as bipolar, BiCMOS, LDMOS, BCD, GaAs HBT, GaN HEMT, GaAs pHEMT, and MESFET technologies. However, embodiments of the invention are particularly useful when fabricated using an SOI or SOS based process, or when fabricated with processes having similar characteristics. Fabrication in CMOS using SOI or SOS processes enables circuits with low power consumption, the ability to withstand high power signals during operation due to FET stacking, good linearity, and high frequency operation (i.e., radio frequencies up to and exceeding 300 GHz). Monolithic IC implementation is particularly useful since parasitic capacitances generally can be kept low (or at a minimum, kept uniform across all units, permitting them to be compensated) by careful design. 
     Voltage levels may be adjusted, and/or voltage and/or logic signal polarities reversed, depending on a particular specification and/or implementing technology (e.g., NMOS, PMOS, or CMOS, and enhancement mode or depletion mode transistor devices). Component voltage, current, and power handling capabilities may be adapted as needed, for example, by adjusting device sizes, serially “stacking” components (particularly FETs) to withstand greater voltages, and/or using multiple components in parallel to handle greater currents. Additional circuit components may be added to enhance the capabilities of the disclosed circuits and/or to provide additional functionality without significantly altering the functionality of the disclosed circuits. 
     Circuits and devices in accordance with the present invention may be used alone or in combination with other components, circuits, and devices. Embodiments of the present invention may be fabricated as integrated circuits (ICs), which may be encased in IC packages and/or in modules for ease of handling, manufacture, and/or improved performance. In particular, IC embodiments of this invention are often used in modules in which one or more of such ICs are combined with other circuit blocks (e.g., filters, amplifiers, passive components, and possibly additional ICs) into one package. The ICs and/or modules are then typically combined with other components, often on a printed circuit board, to form part of an end product such as a cellular telephone, laptop computer, or electronic tablet, or to form a higher-level module which may be used in a wide variety of products, such as vehicles, test equipment, medical devices, etc. Through various configurations of modules and assemblies, such ICs typically enable a mode of communication, often wireless communication. 
     A number of embodiments of the invention have been described. It is to be understood that various modifications may be made without departing from the spirit and scope of the invention. For example, some of the steps described above may be order independent, and thus can be performed in an order different from that described. Further, some of the steps described above may be optional. Various activities described with respect to the methods identified above can be executed in repetitive, serial, and/or parallel fashion. 
     It is to be understood that the foregoing description is intended to illustrate and not to limit the scope of the invention, which is defined by the scope of the following claims, and that other embodiments are within the scope of the claims. In particular, the scope of the invention includes any and all feasible combinations of one or more of the processes, machines, manufactures, or compositions of matter set forth in the claims below. (Note that the parenthetical labels for claim elements are for ease of referring to such elements, and do not in themselves indicate a particular required ordering or enumeration of elements; further, such labels may be reused in dependent claims as references to additional elements without being regarded as starting a conflicting labeling sequence).