Patent Publication Number: US-11395386-B2

Title: Semiconductor device

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2020-013363, filed Jan. 30, 2020, the entire contents of which are incorporated herein by reference. 
     FIELD 
     Embodiments described herein relate generally to a semiconductor device. 
     BACKGROUND 
     Semiconductor devices for stably supplying power to loads are known. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a circuit diagram for explaining a configuration of a semiconductor device according to a first embodiment. 
         FIG. 2  is a diagram for explaining temperature characteristics of voltages in the semiconductor device according to the first embodiment. 
         FIG. 3  is a diagram for explaining temperature characteristics of currents in the semiconductor device according to the first embodiment. 
         FIG. 4  is a circuit diagram for explaining a configuration of a semiconductor device according to a second embodiment. 
         FIG. 5  is a circuit diagram for explaining a configuration of a semiconductor device according to a modification. 
         FIG. 6  is a diagram for explaining temperature characteristics of voltages and currents in the semiconductor device according to the modification. 
         FIG. 7  is a circuit diagram for explaining a configuration of a semiconductor device according to another embodiment. 
     
    
    
     DETAILED DESCRIPTION 
     In general, according to one embodiment, a semiconductor device includes a first current source, a first current mirror having an input end coupled to the first current source and an output end coupled to a first node, a second current source, a second current mirror having an input end coupled to the second current source and an output end coupled to a second node, a third current mirror having an input end coupled to the second node and an output end coupled to the first node, a fourth current mirror having an input end coupled to the first node, and an output driver configured to generate a current based on a current that flows to the output end of the fourth current mirror. A current that flows to the first current source changes at a first ratio with respect to temperature, a current that flows to the second current source changes at a second ratio having a negative correlation with respect to temperature, and an absolute value of the first ratio is smaller than an absolute value of the second ratio. 
     The embodiments of the present invention will be explained with reference to the drawings. In the following explanation, components having the same functions and configurations will be referred to by the same reference symbol. If structural components having the same reference symbols need to be distinguished from each other, letters or numerals may be added to the symbols. If the structural components do not particularly need to be distinguished from each other, only the common symbols will be used, without any letters or numerals attached. 
     1. First Embodiment 
     A semiconductor device according to a first embodiment will be explained. 
     The semiconductor device according to the first embodiment may be an integrated circuit (IC), serving as a driver for supplying a current to drive loads such as externally attached diodes. 
     1.1 Configuration 
     The configuration of the semiconductor device according to the first embodiment will be explained. 
       FIG. 1  is a circuit diagram for explaining the configuration of the semiconductor device according to the first embodiment. 
     A semiconductor device  1  is configured to supply a current IOUT to an externally driven light emitting diode (LED)  20 . For instance, the semiconductor device  1  and externally driven LED  20  may correspond to part of an automobile system. The current IOUT is a current for driving the externally driven LED  20 . 
     The externally driven LED  20  may include a plurality of LEDs that are serially coupled to each other, and may be coupled between the semiconductor device  1  and a ground in the forward direction. The externally driven LED  20  is driven by the current IOUT supplied from the semiconductor device  1 . In the example of  FIG. 1 , the externally driven LED  20  is illustrated as including three LEDs. The number of LEDs, however, is not particularly limited. Only one or two LEDs may be included, or four or more LEDs may be included. 
     The semiconductor device  1  includes an output driver  10  and a terminal P 1 . 
     The terminal P 1  is coupled to an input end (anode) of the externally driven LED  20 , and the current IOUT of the output driver  10  is output to the terminal P 1 . 
     The output driver  10  has a first end to which a signal IIN is supplied, a second end from which a current Iref is output, and a third end coupled to the terminal P 1  to output the current IOUT. Upon receipt of the signal IIN, the output driver  10  outputs the current IOUT, which is based on the current Iref output from the second end, through the third end to the terminal P 1 . The output driver  10  may include an amplification circuit. The amplification circuit is configured to output to the terminal P 1  a current IOUT that is larger than the current Iref, based on the current Iref. 
     The semiconductor device  1  includes a first current source IC 1 , a second current source IC 2 , a first current mirror CM 1 , a second current mirror CM 2 , a third current mirror CM 3 , and a fourth current mirror CM 4 . 
     First, the configuration of the first current source IC 1  will be explained. 
     The first current source IC 1  includes a constant voltage source VS 1 , an operational amplifier AMP 1 , a switch element Q 1  and a resistor R 1 . 
     The constant voltage source VS 1  is configured to output a voltage V 1  and includes a first end grounded and a second end coupled to the operational amplifier AMP 1 . The constant voltage source VS 1  may adopt a band gap reference (BGR). The constant voltage source VS 1  is a voltage source that is affected very little by temperature change, with a ratio of a change of the voltage V 1  to temperature change being significantly smaller than a ratio of a change of a forward voltage V 2  of a diode D, which will be described later, to temperature change. 
     The resistor R 1  exhibits a resistance r1. The resistor R 1  may be a polysilicon resistor or the like, and exhibits a negligibly small ratio of change in resistance to change in temperature. 
     The switch element Q 1  is an NPN bipolar transistor. A collector of the switch element Q 1  is coupled to a node NS, while an emitter of the switch element Q 1  is coupled to a node N 1 . Abase of the switch element Q 1  is coupled to the operational amplifier AMP 1 . 
     The operational amplifier AMP 1  includes a non-inversion input terminal (+), an inversion input terminal (−), and an output terminal. The non-inversion input terminal (+) is coupled to the second end of the constant voltage source VS 1 , and the voltage V 1  is input to this terminal. The inversion input terminal (−) is coupled to the node N 1 , and is grounded via the resistor R 1 . The output terminal is coupled to the base of the switch element Q 1 . 
     Next, the configuration of the first current mirror CM 1  will be explained. 
     The first current mirror CM 1  includes switch elements Q 2  and Q 3 , and resistors R 2  and R 3 . 
     The switch element Q 2  is a PNP bipolar transistor. A collector of the switch element Q 2  is, together with a base of the switch element Q 2 , coupled to the node N 8 . An emitter of the switch element Q 2  is coupled to a node N 2  via the resistor R 2 . 
     The switch element Q 3  is a PNP bipolar transistor. A base of the switch element Q 3  is coupled to the node N 8 . As a result, a voltage between the base of the switch element Q 2  and a collector of the switch element Q 2  becomes equal to a voltage at the base of the switch element Q 3 . A collector of the switch element Q 3  is coupled to a node N 3 . An emitter of the switch element Q 3  is coupled to the node N 2  via the resistor R 3 . 
     The resistors R 2  and R 3  may be polysilicon resistors or the like. The resistors R 2  and R 3  are designed in a manner such that the current flowing from an input end of the first current mirror CM 1  is equivalent to the current flowing from an output end of the first current mirror CM 1 , regardless of temperature. 
     With the above configuration, the first current mirror CM 1  outputs the current (output current) flowing to the switch element Q 3 , based on the current (reference current) flowing to the switch element Q 2 . 
     In the explanation below, among the first to fourth current mirrors CM 1  to CM 4 , a collector of a switch element to which the reference current flows may be referred to as an “input end” of the current mirror, while a collector of a switch element to which the output current flows may be referred to as an “output end” of the current mirror. 
     Next, the configuration of the second current source IC 2  will be explained. 
     The second current source IC 2  includes the diode D, a constant current source I 1 , an operational amplifier AMP 2 , a switch element Q 6 , and a resistor R 6 . 
     The constant current source I 1  outputs a current to a node N 4 . The diode D may include a plurality of diodes that are serially coupled to each other, and is coupled in the forward direction between the node N 4  and a ground so as to be driven by the constant current source I 1 . The diode D exhibits negative temperature characteristics, with a forward voltage decreasing in accordance with increasing temperature. An electric potential of the node N 4  therefore decreases in accordance with increasing temperature. In the example of  FIG. 1 , the diode D is illustrated as including two diodes. The number of diodes, however, is not particularly limited. Only one diode may be included, or three or more diodes may be included. 
     The resistor R 6  exhibits a resistance r6, and is coupled between a node N 5  and a ground. Similarly to the resistor R 1 , the resistor R 6  may be a polysilicon resistor or the like, and has a negligibly small ratio of the change of the resistance to temperature change. The current that flows to the resistor R 6  is determined by the forward voltage of the diode D and the resistance r6, as described later, and therefore exhibits temperature characteristics similar to those of the forward voltage of the diode D. 
     The switch element Q 6  is an NPN bipolar transistor. A collector of the switch element Q 6  is coupled to a node N 9 . An emitter of the switch element Q 6  is coupled to the node N 5 . A base of the switch element Q 6  is coupled to the operational amplifier AMP 2 . 
     The operational amplifier AMP 2  has a non-inversion input terminal (+), an inversion input terminal (−), and an output terminal. The non-inversion input terminal (+) is coupled to the node N 4 , and a voltage V 2  of the node N 4  is input to this terminal. The inversion input terminal (−) is coupled to the node N 5 , and grounded via the resistor R 6 . The output terminal is coupled to the base of the switch element Q 6 . 
     Next, the configuration of the second current mirror CM 2  will be explained. 
     The second current mirror CM 2  includes switch elements Q 7  and Q 8 , and resistors R 7  and R 8 . 
     The resistors R 7  and R 8  may be polysilicon resistors or the like. The resistors R 7  and R 8  are configured such that the current flowing from an input end of the second current mirror CM 2  is equivalent to the current flowing from an output end of the second current mirror CM 2 , regardless of temperature. 
     The switch element Q 7  is a PNP bipolar transistor. A collector of the switch element Q 7  serves as the input end of the second current mirror CM 2 , and is coupled, together with a base of the switch element Q 7 , to the node N 9 . An emitter of the switch element Q 7  is coupled to the node N 2  via the resistor R 7 . 
     The switch element Q 8  is a PNP bipolar transistor. A base of the switch element Q 8  is coupled to the node N 9 . As a result, a voltage between the base of the switch element Q 7  and the collector of the switch element Q 7  becomes equal to a voltage at the base of the switch element Q 8 . A collector of the switch element Q 8  serves as the output end of the second current mirror CM 2 , and is coupled to a node N 6 . An emitter of the switch element Q 8  is coupled to the node N 2  via the resistor R 8 . 
     With the above configuration, the second current mirror CM 2  generates a current flowing to the switch element Q 8 , based on the current flowing to the switch element Q 7 . 
     The configuration of the third current mirror CM 3  will now be explained. 
     The third current mirror CM 3  includes switch elements Q 9  and Q 10 , and resistors R 9  and R 10 . 
     The resistors R 9  and R 10  may be polysilicon resistors or the like. The resistors R 9  and R 10  are designed such that the current flowing to an input end of the third current mirror CM 3  is equivalent to the current flowing to an output end of the third current mirror CM 3 , regardless of temperature. 
     The switch element Q 9  is an NPN bipolar transistor. A collector of the switch element Q 9  serves as the input end of the third current mirror CM 3 , and is coupled to the node N 6 . An emitter of the switch element Q 9  is grounded via the resistor R 9 . 
     The switch element Q 10  is an NPN bipolar transistor. A collector of the switch element Q 10  serves as the output end of the third current mirror CM 3 , and is coupled to the node N 3 . An emitter of the switch element Q 10  is grounded via the resistor R 10 . 
     With the above configuration, the third current mirror CM 3  generates a current flowing to the switch element Q 10 , based on the current flowing to the switch element Q 9 . Furthermore, the input end of the third current mirror CM 3  is coupled to the output end of the second current mirror CM 2  via the node N 6 . The output end of the third current mirror CM 3  is coupled to the output end of the first current mirror CM 1  via the node N 3 . 
     The configuration of the fourth current mirror CM 4  will be explained. 
     The fourth current mirror CM 4  includes switch elements Q 4  and Q 5 , and resistors R 4  and R 5 . 
     The resistors R 4  and R 5  may be polysilicon resistors or the like. The resistors R 4  and R 5  are designed such that the current flowing to an input end of the fourth current mirror CM 4  is equivalent to the current flowing to an output end of the fourth current mirror CM 4 , regardless of temperature. 
     The switch element Q 4  is an NPN bipolar transistor. A collector of the switch element Q 4  serves as the input end of the fourth current mirror CM 4 , and is coupled, together with a base of the switch element Q 4 , to the node N 3 . An emitter of the switch element Q 4  is grounded via the resistor R 4 . 
     The switch element Q 5  is an NPN bipolar transistor. A base of the switch element Q 5  is coupled to the node N 3 . A collector of the switch element Q 5  serves as the output end of the fourth current mirror CM 4 , and is coupled to the second end of the output driver  10 . An emitter of the switch element Q 5  is grounded via the resistor R 5 . 
     With the above configuration, the fourth current mirror CM 4  generates a current flowing to the switch element Q 5 , based on the current flowing to the switch element Q 4 . Furthermore, the input end of the fourth current mirror CM 4  is coupled to both the output end of the first current mirror CM 1  and the output end of the third current mirror CM 3 , via the node N 3 . 
     1.2 Operations 
     Next, the operation of the semiconductor device according to the first embodiment will be explained. 
     With the operation of its operational amplifier AMP 1 , the first current source IC 1  operates in a manner such that an electric potential of the inversion input terminal (−) is equal to an electric potential of the non-inversion input terminal (+). An electric potential of the inversion input terminal (−) therefore becomes equal to the voltage V 1  input to the non-inversion input terminal (+) of the operational amplifier AMP 1 . As a result, an electric potential of the node N 1  coupled to the inversion input terminal (−) is equal to the voltage V 1 . 
     When an ON voltage is supplied from an output end of the operational amplifier AMP 1  to the base of the switch element Q 1 , the switch element Q 1  is turned to the ON state, and a current Iref 1 ′ as expressed by the following equation (1) thereby flows from the collector of the switch element Q 1  to the emitter of the switch element Q 1 .
 
 Iref 1′= V 1 /r 1  (1)
 
     The collector of the switch element Q 1  is coupled to the input end of the first current mirror CM 1  via the node N 8 . 
     In this manner, the current Iref 1 ′ flows into the switch element Q 2  of the first current mirror CM 1 , and a current Iref 1  having approximately the same current value as the current Iref 1 ′ flows into the switch element Q 3  of the first current mirror CM 1 . The current Iref 1 , however, is changeable to any desired level with respect to the current Iref 1 ′ by varying the resistances of the resistors R 2  and R 3 . 
     With the operation of its operational amplifier AMP 2 , the second current source IC 2  operates in a manner such that an electric potential of the inversion input terminal (−) is equal to an electric potential of the non-inversion input terminal (+). The electric potential of the inversion input terminal (−) therefore becomes equal to the voltage V 2  of the node N 4  input to the non-inversion input terminal (+) of the operational amplifier AMP 2 . As a result, an electric potential the node N 5  coupled to the inversion input terminal (−) is equal to the voltage V 2 . 
     When an ON voltage is supplied from an output end of the operational amplifier AMP 2  to the base of the switch element Q 6 , the switch element Q 6  is turned to the ON state, and thereby a current Iref 2 ″ as expressed by the following equation (2) flows from the collector of the switch element Q 6  to the emitter of the switch element Q 6 .
 
 Iref 2″= V 2/ r 6  (2)
 
     The collector of the switch element Q 6  is coupled to the input end of the second current mirror CM 2  via the node N 9 . In this manner, the current Iref 2 ″ flows into the switch element Q 7  of the second current mirror CM 2 , and a current Iref 2 ′ having approximately the same current value as the current Iref 2 ″ flows into the switch element Q 8  of the second current mirror CM 2 . The current Iref 2 ′, however, is changeable to any desired level with respect to the current Iref 2 ″ by varying the resistances of the resistors R 7  and R 8 . 
     With the collector of the switch element Q 9  coupled to the collector of the switch element Q 8 , the third current mirror CM 3  causes a current Iref 2  having approximately the same current value as the current Iref 2 ′ flowing into the node N 6  to flow into the switch element Q 10 . As a result, the current Iref 2  flows from the node N 3  to the switch element Q 10 . The current Iref 2 , however, is changeable to any desired level with respect to the current Iref 2 ′ by adjusting the resistances of the resistors R 9  and R 10 . 
     As described above, the output end of the second current mirror CM 2 , the output end of the third current mirror CM 3 , and the input end of the fourth current mirror CM 4  are commonly coupled to the node N 3 . As a result, a current Iref′ flowing from the node N 3  to the switch element Q 4  is a difference current as expressed by the following equation (3), which can be obtained by subtracting the current Iref 2  from the current Iref 1 .
 
 Iref′=Iref 1 −Iref 2  (3)
 
     The fourth current mirror CM 4  causes the current Iref having approximately the same level as the current Iref′ flowing from the node N 3  to the switch element Q 4  to flow to the switch element Q 5 . As a result, the current Iref flows from the output driver  10  to the switch element Q 10 . The current Iref, however, is changeable to any desired level with respect to the current Iref′ by varying the resistances of the resistors R 4  and R 5 . 
     With the operation of the amplification circuit of the output driver  10  and the like, the output driver  10  outputs a current IOUT that is larger than the current Iref to the terminal P 1 , based on the current Iref. The current IOUT output to the terminal P 1  drives the externally driven LED  20 . 1.3 Temperature Characteristics 
     Next, temperature characteristics of the currents Iref 1 , Iref 2  and Iref will be explained. 
       FIG. 2  is a diagram for explaining temperature characteristics of voltages in the semiconductor device according to the first embodiment.  FIG. 3  is a diagram far explaining temperature characteristics of currents in the semiconductor device according to the first embodiment. 
     As discussed above, the current Iref 1  is determined based on the voltage V 1  and resistance r1 in the same manner as expressed by equation (1), and changes at a first ratio with respect to temperature. The current Iref′ is determined based on the voltage V 2  and resistance r2 in the same manner as expressed by equation (2), and changes at a second ratio with respect to temperature. 
     The voltage V 2  is the electric potential of the node N 4 , which receives a current from the constant current source I 1  and is grounded via the diode D. This means that the voltage V 2  is the forward voltage of the diode D. If the diode D contains two serially coupled diodes, the voltage V 2  can be expressed by the following equation (4), using the forward voltages Vf of these two diodes.
 
 V 2=2× Vf   (4)
 
     When the current flowing into the diodes is maintained constant regardless of temperature, the forward voltages of the diodes exhibit negative temperature characteristics, which means that the forward voltages of the diodes decrease as temperature rises. As indicated in  FIG. 2 , the voltage V 2  of the node N 4  decreases as temperature rises, exhibiting negative temperature characteristics. 
     On the other hand, the voltage source VS 1  is configured such that the absolute value of a ratio of its voltage change to temperature change is negligibly small with respect to that of the diode D. Thus, as indicated in  FIG. 2 , a ratio of the voltage change of the voltage V 1  to temperature change is negligibly smaller than that of the voltage V 2 . 
     As described above, the current Iref 1 ′ is determined based on the voltage V 1  and resistance r1, and the current Iref 2 ″ is determined based on the voltage V 2  and resistance r6. Here, the resistances r1 and r6 change very little in accordance with temperature change. The currents Iref 1 ′ and Iref 2 ″ therefore exhibit temperature characteristics similar to the temperature characteristics of the voltages V 1  and V 2 , respectively. In other words, the current Iref 1 ′ changes very little under temperature change, while the current Iref 2 ″ exhibits negative temperature characteristics. Thus, as indicated in  FIG. 3 , the current Iref 2  exhibits negative temperature characteristics, decreasing as temperature rises. On the other hand, the current Iref 1  changes negligibly, little with respect to the current Iref 2  even when temperature rises. 
     The current Iref is a difference current obtained by subtracting the current Iref 2  having negative temperature characteristics from the current Iref 1 , which changes very little with respect to temperature change. Due to this, the current Iref demonstrates positive temperature characteristics, as indicated in  FIG. 3 . As a result, the current IOUT also demonstrates positive temperature characteristics in the same manner as the current Iref, increasing as temperature rises. 
     1.4 Effects of First Embodiment 
     In the semiconductor device  1  designed to drive the externally driven LED  20 , when a temperature of the externally driven LED  20  is higher than room temperature (e.g., 25 degrees Celsius), the current to be output to the externally driven LED  20  should be increased to greater than room temperature in order to maintain the externally driven LED  20  at a constant brightness. In other words, when the temperature of the externally driven LED  20  is higher than room temperature, the brightness of the externally driven LED  20  can be prevented from decreasing by increasing the current for driving the externally driven LED  20 . For this reason, the current IOUT of the semiconductor device  1  to be supplied to the externally driven LED  20  should be increased in accordance with the increase in the temperature of the externally driven LED  20  and the semiconductor device  1 . 
     According to the first embodiment, the first current mirror CM 1  includes the input end coupled to the first current source IC 1 , which can be regarded as a constant current source. The second current mirror CM 2  includes the input end coupled to the second current source IC 2  that outputs a current having negative temperature characteristics, and the output end coupled to the input end of the third current mirror CM 3 . The fourth current mirror CM 4  includes the input end commonly coupled to the output end of the first current mirror CM 1  and the output end of the third current mirror CM 3 , and the output end coupled to the output driver. With this configuration, the current Iref, and also the current IOUT for driving the externally driven LED  20 , exhibit positive temperature characteristics, increasing as temperature rise. In an automobile system, the semiconductor device  1  may be arranged adjacent to the externally driven LED  20  so that a temperature of the diode D inside the semiconductor device  1  may change in the same manner as the temperature of the externally driven LED  20 . The current Iref therefore may vary in accordance with temperature change of the semiconductor device  1  and the externally driven LED  20 . Thus, when a temperature of the semiconductor device  1  and the externally driven LED  20  is higher than room temperature, the current to be supplied to the externally driven LED  20  can be increased in comparison to the environment of room temperature. In this manner, the brightness of the externally driven LED  20 , which tends to be lowered due to the increased temperature of the semiconductor device  1  and the externally driven LED  20 , can be prevented from being lowered. 
     2. Second Embodiment 
     Next, a semiconductor device according to a second embodiment will be explained. The second embodiment differs from the first embodiment in that the second current source IC 2  determines the voltage to be output to the non-inversion input terminal (+) of the operational amplifier AMP 2 , using a decreased voltage of the externally driven LED  20 , instead of a decreased voltage of the diode D inside the semiconductor device  1 . Configurations and operations the same as those of the first embodiment will be omitted from the explanation, and the configurations and operations different from the first embodiment will be focused on. 
     2.1 Configuration 
       FIG. 4  is a circuit diagram for explaining the configuration of the semiconductor device according to the second embodiment, which corresponds to  FIG. 1  of the first embodiment. 
     As illustrated in  FIG. 4 , the semiconductor device  1  includes a terminal P 2  coupled to the externally driven LED  20 , in place of the diode D and the constant current source I 1  in  FIG. 1 . The terminal P 2  includes a first end coupled to the input end (anode) of the externally driven LED  20  and a second end coupled to the non-inversion input terminal (+) of the operational amplifier AMP 2 . With such a configuration, the terminal P 2  outputs the voltage V 2  of the terminal P 2  determined by the externally driven LED  20  to the non-inversion input terminal (+). 
     2.2 Operations and Temperature Characteristics 
     The operations other than that of the second current source IC 2  are the same as the operations of the first embodiment, and thus the explanation of the same operations is omitted. 
     In the second current source IC 2 , the operational amplifier ANP 2  operates to bring the electric potential of the inversion input terminal (−) to the same level as the voltage V 2  of the terminal P 2 , which is input to the non-inversion input terminal (+) of the operational amplifier AMP 2 . As a result, the electric potential of the node N 5  coupled to the inversion input terminal (−) is equal to the voltage V 2 . Thus, in the same manner as in the first embodiment, the current Iref 2 ″ expressed by equation (2) is output to the collector of the switch element Q 6 . 
     In the externally driven LED  20 , in which a plurality of LEDs are coupled to each other in the current flowing direction, the voltage V 2  of the terminal P 2  equals the electric potential obtained by adding up the forward voltages of the LEDs in the externally driven LED  20 . The forward voltages of the LEDs are lowered as temperature rises due to the temperature characteristics of the LEDs, in the same manner as the diode D of the first embodiment. The voltage V 2  therefore exhibits negative temperature characteristics, decreasing as the temperature of the externally driven LED  20  increase. Accordingly, the current Iref 2 ″ also exhibits negative temperature characteristics, decreasing as temperature increases. 
     As described earlier, the current Iref 2  that flows from the node N 3  to the collector of the switch element Q 10  has temperature characteristics similar to those of the current Iref 2 ″. The current Iref 2  therefore decreases as temperature rises. Accordingly, the current Iref also exhibits positive temperature characteristics, increasing as temperature rises, in the same manner as in the first embodiment. 
     2.3 Effects of Second Embodiment 
     According to the second embodiment, the terminal P 2  is coupled between the non-inversion input terminal (+) of the operational amplifier AMP 2  and the input end (anode) of the externally driven LED  20 . As such, the current value of the current Iref 2  can be determined using the temperature characteristics of the externally driven LED  20  in place of the temperature characteristics of the diode D provided in the semiconductor device  1 , and the effects similar to the first embodiment can be thereby attained. 
     3. Modification 
     The first and second embodiments have been discussed, but are not limitations. Various forms of modification can be suitably adopted. 
     For instance, in the first and second embodiments, the value of the current IOUT increases as temperature rises, but the embodiments are not limited thereto. In particular, when temperature is equal to or exceeds a predetermined value, the configuration may be configured such that the current IOUT decreases. 
     3.1 Configuration 
       FIG. 5  is a circuit diagram for explaining the configuration of a semiconductor device according to a modification, which corresponds to  FIG. 1  of the first embodiment. 
     As illustrated in  FIG. 5 , the semiconductor device  1  differs from the first embodiment in an additionally incorporated third current circuit IC 3 . Configurations and operations the same as those of the first embodiment will be omitted from the explanation, and the configurations and operations different from the first embodiment will be focused on. 
     The third current circuit IC 3  includes a switch element Q 11 , a resistor R 11 , and a constant current source I 2 . 
     The switch element Q 11  is an NPN bipolar transistor. A collector of the switch element Q 11  is an input end of the third current circuit IC 3 , and is coupled to the node N 3 . An emitter of the switch element Q 11  is grounded. A base of the switch element Q 11  is coupled to a node N 7  arranged between the constant current source I 2  and the resistor R 11 . 
     The constant current source I 2  supplies a current to the node N 7 . 
     The resistor R 11  may be a polysilicon resistor or the like. 
     The constant current source I 2  and the resistor R 11  are configured such that a ratio of a change of a voltage VN 7  of the node N 7  with respect to temperature change is negligibly smaller than a ratio of a change of an ON voltage of the switch element Q 11  with respect to temperature change. For instance, a ratio of a change of the current output by the constant current source I 2  to temperature change, and that of the resistance of the resistor R 11  are reduced so that the ratio of the voltage VN 7  of the node N 7  to temperature change can be sufficiently reduced. 
     3.2 Operations and Temperature Characteristics 
     The operations other than that of the third current circuit IC 3  are the same as the operations of the first embodiment, and thus the explanation of the same operations is omitted. 
       FIG. 6  is a diagram for explaining temperature characteristics of voltages and currents in the semiconductor device according to the modification. 
     A threshold voltage VfQ 11  of the switch element Q 11 , which exhibits negative temperature characteristics, decreases as temperature rises, as indicated in (a) of  FIG. 6 . 
     The node N 7  receives a current from the constant current source I 2 , and is grounded via the resistor R 11 . The voltage of the node N 7  is therefore determined by the constant current source I 2  and the resistance of the resistor R 11 . 
     As discussed above, the constant current source I 2  and the resistor R 11  are designed such that the ratio of the change of the voltage VN 7  with respect to temperature change is significantly smaller than the ratio of the threshold voltage VfQ 11  with respect to temperature change. In particular, the resistor R 11  is designed such that its resistance exhibits a change as small as the resistances r1 and r6 in accordance with temperature change. Furthermore, the constant current source I 2  is designed such that the current supplied exhibits a change as small as the constant current source I 1  in accordance with temperature change. 
     The above constant current source I 2  and resistor R 11  may be designed to satisfy VfQ 11 &gt;VN 7  when temperature is lower than a predetermined temperature T 1 , and VfQ 11 ≤VN 7  when temperature is higher than or equal to the predetermined temperature T 1 . As a result, the switch element Q 11  is turned to the OFF state when temperature is lower than the temperature T 1 , and to the ON state when temperature is higher than or equal to the temperature T 1 . 
     When the temperature of the semiconductor device  1  is lower than the temperature T 1 , as indicated in (b) of  FIG. 6 , a current Iref 3  does not flow between the node N 3  and the collector of the switch element Q 11 . The semiconductor device  1  therefore performs substantially the same operation as in the first embodiment. Thus, the current Iref exhibits positive temperature characteristics when temperature is lower than the temperature T 1  in the same manner as in the first embodiment, and the current value increases as temperature rises. 
     When the temperature of the semiconductor device  1  is higher than or equal to the temperature T 1 , the current Iref 3  flows between the node N 3  and the collector of the switch element Q 11 . The current Iref 1  flows from the collector of the switch element Q 3  to the node N 3 . The current Iref 2  flows from the node N 3  to the collector of the switch element Q 10 . The current Iref′ flows from the node N 3  to the collector of the switch element Q 4 . This means that the current Iref′ is a difference current obtained by subtracting the sum of the current Iref 2  and current Iref 3  from the current Iref 1 . The current Iref therefore can be expressed by the following equation (5) using the current Iref 1 , current Iref 2  and current Iref 3 .
 
 Iref=Iref 1−( Iref 2 +Iref 3)  (5)
 
     A temperature characteristics of the current Iref 3  will be explained. 
     As discussed earlier, the switch element Q 11  is turned to the ON state when temperature is higher than or equal to the temperature T 1 . For this reason, when temperature is higher than or equal to the temperature T 1 , the current Iref 3  exhibits positive temperature characteristics, changing at a third ratio, as indicated in (b) of  FIG. 6 . 
     The third current circuit IC 3  is configured such that the absolute value of the third ratio is greater than the absolute value of the second ratio. With such a configuration, the sum of the current Iref 2  and the current Iref 3  exhibits positive temperature characteristics. As a result, the current Iref exhibits negative temperature characteristics when temperature is higher than or equal to the temperature T 1 , and the value of the current Iref decreases as temperature rises, as indicated in (b) of  FIG. 6 . 
     3.3 Effects of Modification 
     According to the modification, the collector of the switch element Q 11  is coupled to the node N 3 . With this coupling, the current Iref 3  flows between the node N 3  and switch element Q 11  when the temperature of the semiconductor device  1  is higher than or equal to the temperature T 1 . As a result, the current Iref′ exhibits positive temperature characteristics below the temperature T 1 , and negative temperature characteristics at or above the temperature T 1 . In the same manner, the current Iref and current IOUT generated based on the current Iref′ exhibit positive temperature characteristics below the temperature T 1 , and negative temperature characteristics at or above the temperature T 1 . Thus, the current IOUT can be swiftly reduced when temperature rises higher than or equal to the temperature T 1  so that a breakdown of the output driver  10  due to an excessively increased current IOUT can be prevented. 
     4. Other Embodiments 
     In the first and second embodiments and modification, the resistors R 1  and R 6  are arranged inside the semiconductor device  1 , but the arrangement is not limited thereto. For instance, with additional terminals arranged in the semiconductor device  1 , the resistors R 1  and R 6  may be provided outside the semiconductor device  1 . 
       FIG. 7  is a circuit diagram for explaining the configuration of a semiconductor device  1  according to another embodiment, in which resistors R 1  and R 6  are provided outside the semiconductor device  1 .  FIG. 7  corresponds to  FIG. 1  of the first embodiment. 
     As illustrated in  FIG. 7 , the semiconductor device  1  further includes terminals P 3  and P 4 . The resistor R 1  is coupled between the terminal P 3  and the ground outside the semiconductor device  1 . The resistor R 6  is coupled between the terminal P 4  and the ground outside the semiconductor device  1 . 
     Such a configuration can produce effects similar to the first embodiment. In addition, by suitably designing the resistors R 1  and R 6  arranged outside the semiconductor device  1 , the level and temperature characteristics of the current IOUT can be easily adjusted. 
     In the first and second embodiments and modification, the switch elements Q 1 , Q 4  to Q 6  and Q 9  to Q 11  are NPN bipolar transistors, and the switch elements Q 2 , Q 3 , Q 7  and Q 8  are PNP bipolar transistors. The configuration, however, is not limited thereto. N-type metal-oxide-semiconductor (MOS) transistors may be adopted for the switch elements Q 1 , Q 4  to Q 6  and Q 9  to Q 11 , and P-type MOS transistors may be adopted for the switch elements Q 2 , Q 3 , Q 7  and Q 8 . 
     While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit.