Patent Publication Number: US-11652419-B2

Title: Systems and methods for voltage compensation based on load conditions in power converters

Description:
1. CROSS-REFERENCES TO RELATED APPLICATIONS 
     This application is a continuation of U.S. patent application Ser. No. 16/276,487, filed Feb. 14, 2019, which claims priority to Chinese Patent Application No. 201811636515.5, filed Dec. 29, 2018, both applications being incorporated by reference herein for all purposes. 
    
    
     2. BACKGROUND OF THE INVENTION 
     Certain embodiments of the present invention are directed to integrated circuits. More particularly, some embodiments of the invention provide systems and methods for voltage compensation based on load conditions in power converters. Merely by way of example, some embodiments of the invention have been applied to flyback power converters. But it would be recognized that the invention has a much broader range of applicability. 
     In recent years, with the development of integrated circuit and information technology, a variety of battery-powered portable electronic devices, such as mobile phones, digital cameras, and notebook computers, became increasingly popular. These battery-powered portable electronic devices raise the need for high-performance power-management chips with low cost, high efficiency and good transient characteristics. 
     Flyback power converters have been used extensively for its simple structure and low cost in low-power power supplies. But in conventional flyback power converters, the output-voltage regulation is often performed with secondary-side feedback, using an isolated arrangement of opto-coupler and shunt regulator (e.g., TL431). Such arrangement usually increases the system cost, size, and power consumption. 
     To reduce the system cost and size of the flyback power converter, converters that employ primary-side regulation have become popular for certain applications. In primary-side regulation, the output voltage is sensed by detecting the voltage of the auxiliary winding that is tightly coupled to the secondary winding. Since the voltage of the auxiliary winding should image the output voltage associated with the secondary winding, the detected voltage can be utilized to regulate the secondary-side output voltage. Hence, the expensive parts of opto-coupler and shunt regulator (e.g., TL431) often are no longer needed in order to save system cost and size. 
       FIG.  1    is a simplified diagram of a conventional flyback power converter with primary-side regulation (PSR). The power converter  100  includes a system controller  102 , a rectifying component  104  (e.g., a bridge rectifier), a primary winding  106  (e.g., Np), a secondary winding  108  (e.g., Ns), a power switch  110  (e.g., M 1 ), a rectifying diode  112  (e.g., D 1 ), two capacitors  114  and  116  (e.g., C 0  and C 1 ), three resistors  118 ,  120  and  122  (e.g., R 1 , R 2  and R 3 ), a current sensing resistor  124  (e.g., R CS ), and an auxiliary winding  126 . The system controller  102  includes a constant current (CC) control component  128 , a constant voltage (CV) control component  130 , a load compensation component  132 , and a drive and modulation component  134 . The system controller  102  further includes five terminals  136 ,  138 ,  140 ,  142  and  144 . For example, the power switch  110  is a field-effect transistor (FET), a bipolar junction transistor (BJT), or an insulated-gate bipolar transistor (IGBT). In one example, the system controller  102 , including components  128 ,  130 ,  132  and  134 , is located on a chip. For example, the terminals  136 ,  138 ,  140 ,  142  and  144  are pins of the chip. 
     As shown in  FIG.  1   , a system controller  102  is used to control and drive the power switch  110  (e.g., M 1 , a power MOSFET), which turns on and off to control (e.g., regulate) the output voltage and/or output current delivered to the load  146  on the secondary side of the power converter  100 . An alternating-current (AC) input voltage  148  is applied to the power converter  100 . The rectifying component  104  outputs a bulk voltage  150  (e.g., a rectified voltage no smaller than 0 V) associated with the AC input voltage  148 . The capacitor  116  (e.g., C 1 ) is charged in response to the bulk voltage  150  through the resistor  118  (e.g., R 1 ), and a voltage  152  is provided to the controller  102  at the terminal  136  (e.g., terminal VCC). If the voltage  152  is larger than a threshold voltage (e.g., an under-voltage lock-out threshold) in magnitude, the controller  102  begins to operate, and a voltage associated with the terminal  136  (e.g., terminal VCC) is clamped to a predetermined voltage. 
     In addition, the terminal  138  (e.g., terminal GATE) is connected to a gate terminal of the power switch  110  (e.g., M 1 ). The controller  102  outputs a drive signal  154  (e.g., a pulse-width-modulation signal) with a certain frequency and a certain duty cycle to close (e.g., turn on) or open (e.g., turn off) the power switch  110  so that the power converter  100  operates normally. 
     For example, if power switch  110  is closed, the power converter  100  stores the energy associated with AC input voltage  148 . In another example, if the power switch  110  is opened, the stored energy is delivered to the secondary side of the power converter  100  via the transformer including the primary winding  106  and the secondary winding  108 . The output voltage  156  (e.g., V out ) is mapped to the feedback voltage  158  (e.g., V FB ) through the auxiliary winding  126  and by resistors  120  and  122  (e.g., R 2  and R 3 ), and received by the controller  102  at terminal  144  (e.g., terminal FB). In this way, the controller on the primary side receives information about the output voltage and demagnetization of the power converter that can be used to regulate the output voltage, and, in turn, achieve constant voltage (CV) and/or constant current (CC) output. 
     Referring to  FIG.  1   , the feedback voltage  158  (e.g., V FB ) of the power converter  100  can be determined as follows: 
                     V   FB     =           R   2         R   2     +     R   3         ⁢     V     a   ⁢   u   ⁢   x         =         R   2         R   2     +     R   3         ⁢     (       V     o   ⁢   u   ⁢   t       +     V   d       )     ×       n   a       n   s                   (     Equation   ⁢           ⁢   1     )               
where V aux  represents the voltage of the auxiliary winding  126  during a demagnetization period of the power converter  100 , R 2  represents the resistance of resistor  120 , R 3  represents the resistance of resistor  122 , V out  represents the output voltage  156 , V d  represents the voltage drop across the diode  112  (e.g., D 1 ), n a  represents the number of turns of the auxiliary winding  126 , and n s  represents the number of turns of the secondary winding  108 .
 
     Based on Equation 1, the relationship between V FB  and V out  can be determined as follows: 
     
       
         
           
             
               
                 
                   
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     Hence, the output voltage  156  can be regulated through the regulation of the voltage of the auxiliary winding  126 . Since V FB  is an image of the output voltage V out , the output voltage is proportional to V FB . Under certain conditions, the output voltage  156  is regulated at a constant level, if the feedback voltage V FB  and voltage V d  across diode  112  (e.g., D 1 ) are kept constant by the controller  102 . However, for a given diode, the voltage V d  is current dependent, and therefore V d  changes if the load current I load  changes. 
     Moreover, the output cable line  160  generates a voltage drop that is proportional to the load current I load . This voltage drop causes the load voltage V load  received by the load  146  to decrease if the load current I load  increases. Assuming the resistance of the output cable line is R cable , the load voltage V load  at an equipment terminal  162  can be determined as follows: 
     
       
         
           
             
               
                 
                   
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     On one hand, different magnitudes of the load current result in different voltage drops across the diode  112  and the output cable line  160 , and, thus, the load voltage V load  is not constant at different load current levels. Rather, based on Equation 3, the load voltage V load  decreases as the load current I load  increases. Hence, at a default-load condition (e.g., the load current and/or load voltage being within a predetermined operating range of the power converter) or a high-load condition, the power converter  100  exhibits poor load-voltage regulation due to the voltage drop across the diode  112  and/or the output cable line  160 . 
     On the other hand, the controller  102  is powered via the auxiliary winding  126  through the voltage  152  provided to the controller  102  at the terminal  136  (e.g., terminal VCC). Hence, the controller also represents a load of the system. If the load current is small or there is no load connected to the equipment terminal  162  of the system, the current drawn by the controller  102  is not negligible. In this case, the secondary winding  108  and the auxiliary winding  126  exhibit cross regulation that results in the controller  102  being unable to regulate the load voltage V load . Thus, if the system is at a light-load or no load, the load voltage V load  becomes uncontrollably high due to cross regulation. 
     Hence it is highly desirable to improve the techniques of power converters. 
     3. BRIEF SUMMARY OF THE INVENTION 
     Certain embodiments of the present invention are directed to integrated circuits. More particularly, some embodiments of the invention provide systems and methods for voltage compensation based on load conditions in power converters. Merely by way of example, some embodiments of the invention have been applied to flyback power converters. But it would be recognized that the invention has a much broader range of applicability. 
     According to one embodiment, a system controller for regulating a power converter includes a first controller terminal; a second controller terminal; and a compensation current generator. The compensation current generator is configured to receive an input signal through the first controller terminal. The input signal indicates a first current flowing through a primary winding of a power converter. The compensation current generator is configured to receive a demagnetization signal related to a demagnetization period of the power converter and associated with an auxiliary winding of the power converter. The compensation current generator is configured to generate a compensation current based at least in part on the input signal and the demagnetization signal. The compensation current generator is connected to a resistor. The resistor is configured to generate a compensation voltage based at least in part on the compensation current and output a first reference voltage based at least in part on the compensation voltage and a second reference voltage. The system controller is configured to: generate an amplified signal based at least in part on the second reference voltage; generate a drive signal based at least in part on the amplified signal; and output the drive signal through the second controller terminal to a switch to affect the first current flowing through the primary winding of the power converter. 
     According to another embodiment, a system controller for regulating a power converter includes: a sample-and-hold signal generator; a multiplier; and a first filter. The sample-and-hold signal generator is configured to receive a first input signal and generate a sampled-and-held signal based at least in part on the first input signal. The first input signal indicates a first current flowing through a primary winding of a power converter. The sampled-and-held signal represents a peak of the first current. The multiplier is configured to receive a demagnetization signal and generate a multiplication signal based on at least information associated with the demagnetization signal and the sampled-and-held signal. The demagnetization signal is related to a demagnetization period of the power converter and is associated with an auxiliary winding of the power converter. The first filter is configured to receive the multiplication signal and generate a first filtered signal based at least in part on the multiplication signal. The first filtered signal is related to a drive signal outputted to a switch to affect the first current flowing through the primary winding of the power converter. 
     According to yet another embodiment, a system controller for regulating a power converter includes: a signal generator; and an error amplifier. The signal generator is configured to receive an input signal and a reference signal and output an output signal to generate a drive signal. The output signal is equal to an amplification value multiplied by a difference between the input signal and the reference signal. The error amplifier is configured to generate the input signal based on at least information associated with the output signal. The system controller is configured to: generate the drive signal based on at least information associated with the input signal; and output the drive signal to a switch of a power converter to affect a current flowing through a primary winding of the power converter. 
     According to yet another embodiment, a system controller for regulating a power converter includes: a first controller terminal; a second controller terminal; a compensation current generator; and an error amplifier. The compensation current generator is configured to: receive an input signal through the first controller terminal. The input signal indicates a first current flowing through a primary winding of a power converter. The compensation current generator is configured to: receive an amplified signal; and generate a compensation current based at least in part on the input signal and the amplified signal. The error amplifier is configured to: generate the amplified signal based on at least information associated with the compensation current; output the amplified signal to the compensation current generator; and output the amplified signal to generate a drive signal outputted through the second controller terminal to a switch to affect the first current flowing through the primary winding of the power converter. 
     According to yet another embodiment, a system controller for regulating a power converter includes: a first controller terminal; a second controller terminal; a compensation current generator; and an error amplifier. The compensation current generator is configured to: receive an input signal through the first controller terminal. The input signal indicates a first current flowing through a primary winding of a power converter. The compensation current generator is configured to: receive a demagnetization signal related to a demagnetization period of the power converter and associated with an auxiliary winding of the power converter; receive an amplified signal; in response to the power converter operating under a first load condition, generate a compensation current based at least in part on the input signal and the amplified signal; and in response to the power converter operating under a second load condition, generate the compensation current based at least in part on the input signal and the demagnetization signal. The error amplifier is configured to: generate the amplified signal based on at least information associated with the compensation current; output the amplified signal to the compensation current generator; and output the amplified signal to generate a drive signal outputted through the second controller terminal to a switch to affect the first current flowing through the primary winding of the power converter. The first load condition and the second load condition are different. 
     According to yet another embodiment, a method for regulating a power converter includes: receiving an input signal. The input signal indicates a first current flowing through a primary winding of a power converter. The method includes: receiving a demagnetization signal related to a demagnetization period of the power converter and associated with an auxiliary winding of the power converter; generating a compensation current based at least in part on the input signal and the demagnetization signal; generating a compensation voltage based at least in part on the compensation current; outputting a first reference voltage based at least in part on the compensation voltage and a second reference voltage; generating an amplified signal based at least in part on the second reference voltage; generating a drive signal based at least in part on the amplified signal; and outputting the drive signal to a switch to affect the first current flowing through the primary winding of the power converter. 
     According to yet another embodiment, a method for regulating a power converter includes: receiving an input signal. The input signal indicates a current flowing through a primary winding of a power converter. The method includes: generating a sampled-and-held signal based at least in part on the input signal. The sampled-and-held signal represents a peak of the current. The method includes: receiving a demagnetization signal; and generating a multiplication signal based on at least information associated with the demagnetization signal and the sampled-and-held signal. The demagnetization signal is related to a demagnetization period of the power converter and is associated with an auxiliary winding of the power converter. The method includes: receiving the multiplication signal; and generating a filtered signal based at least in part on the multiplication signal. The filtered signal is related to a drive signal. The method includes: outputting the drive signal to a switch to affect the first current flowing through the primary winding of the power converter. 
     According to yet another embodiment, a method for regulating a power converter includes: receiving an input signal and a reference signal; and outputting an output signal to generate a drive signal. The output signal is equal to an amplification value multiplied by a difference between the input signal and the reference signal. The method includes: generating the input signal based on at least information associated with the output signal; generating the drive signal based on at least information associated with the input signal; and outputting the drive signal to a switch of a power converter to affect a current flowing through a primary winding of the power converter. 
     According to yet another embodiment, a method for regulating a power converter includes: receiving an input signal. The input signal indicates a first current flowing through a primary winding of a power converter. The method includes: receiving an amplified signal; generating a compensation current based at least in part on the input signal and the amplified signal; generating the amplified signal based on at least information associated with the compensation current; generating a drive signal based at least in part on the amplified signal; and outputting the drive signal to a switch to affect the first current flowing through the primary winding of the power converter. 
     According to yet another embodiment, a method for regulating a power converter includes: receiving an input signal. The input signal indicates a first current flowing through a primary winding of a power converter. The method includes: receiving a demagnetization signal related to a demagnetization period of the power converter and associated with an auxiliary winding of the power converter; receiving an amplified signal; in response to the power converter operating under a first load condition, generating a compensation current based at least in part on the input signal and the amplified signal; in response to the power converter operating under a second load condition, generating the compensation current based at least in part on the input signal and the demagnetization signal; generating the amplified signal based on at least information associated with the compensation current; generating a drive signal based at least in part on the amplified signal; and outputting the drive signal to a switch to affect the first current flowing through the primary winding of the power converter. The first load condition and the second load condition are different. 
     Depending upon embodiment, one or more benefits may be achieved. These benefits and various additional objects, features and advantages of the present invention can be fully appreciated with reference to the detailed description and accompanying drawings that follow. 
    
    
     
       4. BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG.  1    is a simplified diagram of a conventional flyback power converter with primary-side regulation (PSR). 
         FIG.  2    is a simplified diagram showing a flyback power converter with primary-side regulation and load compensation according to one embodiment of the present invention. 
         FIG.  3    is a simplified timing diagram for the power converter as shown in  FIG.  2    according to one embodiment of the present invention. 
         FIG.  4    is a simplified diagram showing a controller as part of the power converter as shown in  FIG.  2    according to one embodiment of the present invention. 
         FIG.  5    is a simplified diagram showing a compensation signal generator as part of the controller as shown in  FIG.  4    according to one embodiment of the present invention. 
         FIG.  6    is a simplified timing diagram for the compensation signal generator as shown in  FIG.  5    according to one embodiment of the present invention. 
         FIG.  7    is a simplified diagram showing a compensation signal as a function of a load current as shown in  FIGS.  2  and  5    according to certain embodiments of the present invention. 
         FIG.  8    is a simplified diagram showing certain components of the compensation signal generator as shown in  FIG.  5    according to another embodiment of the present invention. 
     
    
    
     5. DETAILED DESCRIPTION OF THE INVENTION 
     Certain embodiments of the present invention are directed to integrated circuits. More particularly, some embodiments of the invention provide systems and methods for voltage compensation based on load conditions in power converters. Merely by way of example, some embodiments of the invention have been applied to flyback power converters. But it would be recognized that the invention has a much broader range of applicability. 
     According to some embodiments, the systems and methods include a two-segment voltage compensation scheme based on the load conditions in the power converters. For example, segment I of the compensation scheme compensates for a voltage drop across an output cable line of the power converter (e.g., at a high-load condition). In another example, segment II of the compensation scheme compensates for cross regulation at a load condition (e.g., at a no-load condition or at a light-load condition). 
       FIG.  2    is a simplified diagram showing a flyback power converter with primary-side regulation and load compensation according to one embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. The power converter  200  includes a system controller  202 , a rectifying component  204  (e.g., a bridge rectifier), a primary winding  206 , a secondary winding  208 , a power switch  210  (e.g., M 1 ), a rectifying diode  212  (e.g., D 1 ), two capacitors  214  and  216  (e.g., C 0  and C 1 ), three resistors  218 ,  220  and  222  (e.g., R 1 , R 2  and R 3 ), a current-sensing resistor  224  (e.g., R CS ), and an auxiliary winding  226 . In one embodiment, the system controller  202  includes a constant current (CC) control component  228 , a constant voltage (CV) control component  230 , a load compensation component  232 , and a drive and modulation component  234 . For example, the system controller  202  further includes five terminals  236 ,  238 ,  240 ,  242  and  244 . In another example, the power switch  210  is a field-effect transistor (FET), a bipolar junction transistor (BJT), or an insulated-gate bipolar transistor (IGBT). In one embodiment, the system controller  202 , including components  228 ,  230 ,  232  and  234 , is located on a chip. For example, the terminals  236 ,  238 ,  240 ,  242  and  244  are pins of the chip. In another embodiment, the terminal  242  is biased to a predetermined voltage (e.g., ground). 
     According to one embodiment, a system controller  202  is used to control and drive the power switch  210  (e.g., M 1 , a power MOSFET), which turns on and off to control (e.g., regulate) the load voltage  263  (e.g., V load ) and/or the load current  265  (e.g., I load ) delivered to the load  246  on the secondary side of the power converter  200 . For example, the output current  264  (e.g., I out ) is the load current  265  (e.g., I load ) of the power converter  200 . In another example, the load current  265  (e.g., I load ) of the power converter  200  is received by the load  246 . In yet another example, an alternating-current (AC) input voltage  248  is applied to the power converter  200 . In one example, the rectifying component  204  outputs a bulk voltage  250  (e.g., a rectified voltage no smaller than 0 V) associated with the AC input voltage  248 . In yet another example, the capacitor  216  (e.g., C 1 ) is charged in response to the bulk voltage  250  through the resistor  218  (e.g., R 1 ), and a voltage  252  is provided to the controller  202  at the terminal  236  (e.g., terminal VCC). According to one example, if the voltage  252  is larger than a threshold voltage (e.g., an under-voltage lock-out threshold) in magnitude, the controller  202  begins to operate, and a voltage associated with the terminal  236  (e.g., terminal VCC) is clamped to a predetermined voltage. In another example, the terminal  238  (e.g., terminal GATE) is connected to a gate terminal of the power switch  210  (e.g., MO. For example, the controller  202  outputs a drive signal  254  (e.g., a pulse-width-modulation signal) with a certain frequency and a certain duty cycle to close (e.g., turn on) or open (e.g., turn off) the power switch  210  so that the power converter  200  operates normally. 
     For example, if power switch  210  is closed, the power converter  200  stores the energy associated with AC input voltage  248 . In another example, if the power switch  210  is opened, the stored energy is delivered to the secondary side of the power converter  200  via the transformer including the primary winding  206  and the secondary winding  208 . In one example, the output voltage  256  (e.g., V out ) is mapped to the feedback voltage  258  (e.g., V FB ) through the auxiliary winding  226  and by resistors  220  and  222  (e.g., R 2  and R 3 ), and received by the controller  202  at terminal  244  (e.g., terminal FB). In another example, the resistors  220  and  222  (e.g., R 2  and R 3 ) receive an auxiliary current  266  that flows through the auxiliary winding  226 , and in response outputs a feedback signal  268  associated with the feedback voltage  258  (e.g., V FB ) to the terminal  244  (e.g., terminal FB). In yet another example, the controller on the primary side receives information about the output voltage and demagnetization of the power converter that can be used to control (e.g., regulate) the load voltage  263  (e.g., V load ) and/or load current  265  (e.g., I load ), and, in turn, achieve constant voltage (CV) and/or constant current (CC) output. 
     According to another embodiment, a primary current  270  that flows through the primary winding  206  is sensed by the current-sensing resistor  224 , which in response outputs the sensed signal  272  to the terminal  240  (e.g., terminal CS). For example, the sensed signal  272  is received by the load compensation component  232  through the terminal  240  (e.g., terminal CS) of the controller  202 . In another example, the load compensation component  232  receives the feedback signal  268  through the terminal  244  (e.g., terminal FB) of the controller  202 . In yet another example, the load compensation component  232  generates a signal  274  based on at least the sensed signal  272  and/or the feedback signal  268 , and outputs the signal  274 . 
     In one embodiment, the CV control component  230  receives the signal  274  from the load compensation component  232 . In one example, the CV control component  230  receives the sensed signal  272  through the terminal  240  (e.g., terminal CS) of the controller  202 . In another example, the CV control component  230  receives the feedback signal  268  through the terminal  244  (e.g., terminal FB) of the controller  202 . In yet another example, the CV control component  230  generates a signal  276  based on the sensed signal  272 , the feedback signal  268  and the signal  274 , and outputs the signal  276  to the drive and modulation component  234 . 
     In another embodiment, the CC control component  228  receives the feedback signal  268  through terminal  244  (e.g., terminal FB) on the primary side of the power converter  200 . In one example, the CC control component  228  receives the sensed signal  272  through terminal  240  (e.g., terminal CS) of the controller  202 . For example, the CC control component  228  generates a signal  278  based on the sensed signal  272  and the feedback signal  268 , and outputs the signal  278  to the drive and modulation component  234 . In yet another embodiment, the drive and modulation component  234  generates the drive signal  254  based on the signals  276  and  278 , and in response outputs the drive signal  254  to the power switch  210 . 
       FIG.  3    is a simplified timing diagram for the power converter  200  according to one embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. In one embodiment, the waveform  354  represents the drive signal  254  as a function of time. For example, the waveform  354  indicates turned-on and turned-off conditions of the switch  210  as a function of time. In another embodiment, the waveform  370  represents the primary current  270  (e.g., I pri ) as a function of time. For example, the primary current  270  (e.g., I pri ) flows through the switch  210 . In yet another embodiment, the waveform  380  represents the secondary current  280  (e.g., I sec ) as a function of time. For example, the secondary current  280  flows through the rectifying diode  212 . In yet another embodiment, the waveform  328  represents a demagnetization signal associated with the feedback signal  268  as a function of time. For example, if the waveform  354  is at a logic high level, the switch  210  is closed (e.g., turned on), and if the waveform  354  is at a logic low level, the switch  210  is open (e.g., turned off). 
     According to one embodiment, four time periods T on , T off , T dem , and T s  are shown in  FIG.  3   . For example, the time period T on  starts at time to and ends at time t 1 , and the time period T off  starts at time t 1  and ends at time t 3 . In another example, the time period T dem  starts at the time t 1  and ends at time t 2 , and the time period T s  starts at the time t 1  and ends at the time t 4 . For example, t 0 ≤t 1 ≤t 2 ≤t 3 ≤t 4 . In yet another example, the time period T dem  represents the signal pulse width of the demagnetization signal, and is within the time period T off . According to one example, the time period T s  (e.g., switching period) is the signal period of the demagnetization signal, and includes the time period T dem  (e.g., demagnetization period). 
     According to another embodiment, the load current  265  (e.g., the output current  264 ) is the average value of the secondary current  280  (e.g., I sec ) after rectification by the diode  212 , and load current I load  can be written as: 
     
       
         
           
             
               
                 
                   
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                     4 
                   
                   ) 
                 
               
             
           
         
       
     
     For example, assuming the ratio of number of turns of the primary winding  206  to the number of turns of secondary winding  208  is N s , I sec  is:
 
 I   sec   =I   pri   ×N   S   (Equation 5)
 
     In another example, further assuming the voltage across the current-sensing resistor  224  is V CS  and its resistance is R CS , I pri  is: 
     
       
         
           
             
               
                 
                   
                     I 
                     pri 
                   
                   = 
                   
                     
                       V 
                       CS 
                     
                     
                       R 
                       CS 
                     
                   
                 
               
               
                 
                   ( 
                   
                     Equation 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     6 
                   
                   ) 
                 
               
             
           
         
       
     
     According to yet another embodiment, substituting Equations 5 and 6 into Equation 4, the load current I load  (e.g., the output current  264 ) can be expressed as follows: 
     
       
         
           
             
               
                 
                   
                     I 
                     
                       l 
                       ⁢ 
                       o 
                       ⁢ 
                       a 
                       ⁢ 
                       d 
                     
                   
                   = 
                   
                     
                       
                         1 
                         2 
                       
                       × 
                       
                         I 
                         
                           s 
                           ⁢ 
                           e 
                           ⁢ 
                           c 
                         
                       
                       × 
                       
                         
                           T 
                           
                             d 
                             ⁢ 
                             e 
                             ⁢ 
                             m 
                           
                         
                         
                           T 
                           s 
                         
                       
                     
                     = 
                     
                       
                         1 
                         2 
                       
                       × 
                       
                         
                           V 
                           
                             C 
                             ⁢ 
                             S 
                           
                         
                         
                           R 
                           
                             C 
                             ⁢ 
                             S 
                           
                         
                       
                       × 
                       
                         N 
                         S 
                       
                       × 
                       
                         
                           T 
                           
                             d 
                             ⁢ 
                             e 
                             ⁢ 
                             m 
                           
                         
                         
                           T 
                           s 
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   
                     Equation 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     7 
                   
                   ) 
                 
               
             
           
         
       
     
     For example, if Rcs and Ns are constant for the power converter  200 , the load current I load  (e.g., the output current  264 ) is equivalent to: 
     
       
         
           
             
               
                 
                   
                     I 
                     
                       l 
                       ⁢ 
                       o 
                       ⁢ 
                       a 
                       ⁢ 
                       d 
                     
                   
                   = 
                   
                     K 
                     × 
                     
                       V 
                       
                         C 
                         ⁢ 
                         S 
                       
                     
                     × 
                     
                       
                         T 
                         
                           d 
                           ⁢ 
                           e 
                           ⁢ 
                           m 
                         
                       
                       
                         T 
                         s 
                       
                     
                   
                 
               
               
                 
                   ( 
                   
                     Equation 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     8 
                   
                   ) 
                 
               
             
           
         
       
     
     where 
             K   =       1     2   ⁢     R   CS         ×     N   S             
represents a constant value and the load current  265  (e.g., I load ) is proportional to
 
     
       
         
           
             
               
                 V 
                 CS 
               
               × 
               
                 
                   T 
                   
                     d 
                     ⁢ 
                     e 
                     ⁢ 
                     m 
                   
                 
                 
                   T 
                   s 
                 
               
             
             . 
           
         
       
     
     Based on Equation 8, I pri  and T dem  can be used to determine the load current I load  (e.g., the output current  264 ) according to some embodiments. In one embodiment, the controller  202  generates the signal  274 . For example, the signal  274  corresponds the load current I load  (e.g., the output current  264 ), and can be used to compensate for the drop in the load voltage  263  (e.g., the drop that is caused by the voltage drop across the diode  212  and/or caused by the output cable line  260 ). 
     In one embodiment, the load condition depends on the load current  265  (e.g., the output current  264 ). For example, the load condition is a no-load condition (e.g., the load current  265  being equal to zero). In another example, the load condition is a low-load condition (e.g., the load current  265  being small in magnitude). In yet another example, the load condition is a high-load condition (e.g., the load current  265  being large in magnitude). 
     For example, the signal  274  can be used to compensate for the drop in the load voltage  263  (e.g., the drop that is caused by the voltage drop across the diode  212  and/or caused by the output cable line  260 ) (e.g., at a high-load condition). In yet another example, the signal  274  can be used to compensate the increase in the load voltage  263  (e.g., the increase caused by cross regulation) (e.g., at a no-load condition or a low-load condition). In yet another example, the signal  274  can be used to compensate for the drop in the load voltage  263  (e.g., the drop that is caused by the voltage drop across the diode  212  and/or caused by the output cable line  260 ) (e.g., at a high-load condition), and also compensate for the increase in the load voltage  263  (e.g., the increase caused by cross regulation) (e.g., at a no-load condition or at a low-load condition). 
     According to one embodiment, under a default load condition, the signal  274  can be used to compensate for the drop in the load voltage  263  (e.g., the drop that is caused by the voltage drop across the diode  212  and/or caused by the output cable line  260 ). According to another embodiment, under a default condition, the signal  274  can be used to compensate the increase in the load voltage  263  (e.g., the increase caused by cross regulation). 
     According to another embodiment, during a time period (e.g., T on ) when the switch  210  is closed (e.g., turned on), the primary current  270  (e.g., I pri ) increases from a low value (e.g., the value  302  that is, for example, approximately zero at t 0 ) to a peak value (e.g., the peak-current value  304  at t 1 ) as shown by the waveform  370 . For example, at a time (e.g., t 1 ) when the switch  210  changes from closed (e.g., turned on) to open (e.g., turned off), the primary current  270  (e.g., I pri ) decreases from a peak value (e.g., the peak-current value  304  at t 1 ) to a low value (e.g., the value  306  that is, for example, approximately zero at t 1 ) as shown by the waveform  370 . In another example, at a time (e.g., t 1 ) when the switch  210  changes from closed (e.g., turned on) to open (e.g., turned off), the secondary current  280  (e.g., I sec ) increases from a low value (e.g., the value  308  that is, for example, approximately zero at t 1 ) to a peak value (e.g., the peak-current value  310  at t 1 ) as shown by the waveform  380 . In yet another example, during a time period (e.g., T dem ) the secondary current  280  (e.g., I sec ) decreases from a high value (e.g., the value  310  at t 1 ) to a low value (e.g., the value  312  at t 2 ) as shown by waveform  380 . 
       FIG.  4    is a simplified diagram showing a controller as part of the power converter  200  according to one embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. The controller  202  includes a modulation component  402  (e.g., PWM/PFM control), a logic control component  404 , a driver  406 , a demagnetization detector  408 , a switch  410 , a capacitor  412 , an error amplifier  414  (e.g., EA), a resistor  416  (e.g., R c ), a compensation signal generator  418  (e.g., a compensation current generator), a reference signal generator  420 , a power supply component  422  (e.g., power supply block), and two comparators  424  and  426  (e.g., COMP and OCP). In one embodiment, the controller  202  further includes five terminals  236 ,  238 ,  240 ,  242  and  244 . In another embodiment, the controller  202  is located on a chip. For example, the terminals  236 ,  238 ,  240 ,  242  and  244  are pins of the chip. In yet another embodiment, the power supply component  422  (e.g., power supply block) is connected to terminal  236  (e.g., terminal VCC). According to another embodiment, the terminal  242  is biased to a predetermined voltage (e.g., ground). 
     According to one embodiment, the demagnetization detector  408  receives the feedback signal  268  through the terminal  244  (e.g., terminal FB) of the controller  202 . For example, the demagnetization detector  408  generates a demagnetization signal  428  based on the feedback signal  268 , and outputs the demagnetization signal  428  to the compensation signal generator  418 . As an example, the demagnetization signal  428  relates to a demagnetization period (e.g., T dem ) of the power converter  200 . In one example, the demagnetization signal  428  is associated with the auxiliary winding  226 . For example, the feedback signal  268  relates to the auxiliary winding  226 . 
     According to another embodiment, the controller  202  includes a sample-and-hold circuit configured to sample the feedback signal  268  and output a sampled signal  430  (e.g., V fb_s ) based in part on the feedback signal  268 . For example, the sample-and-hold includes the switch  410  and the capacitor  412 . In one example, the switch  410  receives the feedback signal  268  through the terminal  244  (e.g., terminal FB) of the controller  202 , and samples the feedback signal  268  during the demagnetization of the auxiliary winding  226 . For example, if the switch  410  is closed (e.g., turned on), the feedback signal  268  flows through the switch  410  to charge the capacitor  412  to generate and hold the sampled signal  430  (e.g., V fb_s ), which is received by an inverting terminal (e.g., the “−” terminal) of the error amplifier  414 . In another example, the feedback signal  268  is sampled during the time period T dem . In yet another example, if the switch  410  is open (e.g., turned off), the capacitor  412  provides the sampled signal  430  to the inverting terminal (e.g., the “−” terminal) of the error amplifier  414 . 
     According to yet another embodiment, the compensation signal generator  418  receives the sensed signal  272  through terminal  240  (e.g., terminal CS) of the controller  202 . For example, the compensation signal generator  418  receives the demagnetization signal  428  from the demagnetization detector  408 . In another example, the compensation signal generator  418  receives the signal  274  (e.g., V comp ) from the error amplifier  414  (e.g., EA). 
     In one embodiment, the compensation signal generator  418  generates a compensation signal  432  (e.g., I c ) based on the sensed signal  272 , the signal  274  (e.g., V comp ) and the demagnetization signal  428 . In another embodiment, the compensation signal generator  418  generates the compensation signal  432  (e.g., I c ) based on the sensed signal  272  and the demagnetization signal  428 . In yet another embodiment, the compensation signal generator  418  generates a compensation signal  432  (e.g., I c ) based on the signal  274  (e.g., V comp ). 
     In another example, the compensation signal  432  (e.g., I c ) is a compensation current. For example, the compensation signal  432  (e.g., I c ) flows through the resistor  416  (e.g., R c ) to generate a compensation voltage ΔV c . As an example, the resistor  416  (e.g., R c ) is configured to generate the compensation voltage ΔV c . based in part on the compensation signal  432  (e.g., I c ). In one example, the resistor  416  (e.g., R c ) is configured to output a reference signal  434  based in part on the compensation signal  432  (e.g., I c ) and a reference signal  436 . For example, the reference signal  434  is a reference voltage (e.g., internal reference voltage V ref_f ). As an example, the reference signal  436  is a reference voltage (e.g., reference voltage V ref_cv ). In one example, the compensation voltage ΔV c  can be expressed as follows:
 
Δ V   c   =R   c   ×I   c   (Equation 9)
 
     In yet another example, based on Equation 8, the compensation signal generator  418  determines the magnitude of the load current I load  (e.g., the output current  264 ) to compensate for the drop in the load voltage  263  (e.g., the drop that is caused by the voltage drop across the diode  212  and/or caused by the output cable line  260 ). For example, the compensation signal  432  (e.g., I c ) is generated based on information associated with the magnitude of the load current I load  (e.g., the output current  264 ). 
     According to yet another embodiment, the error amplifier  414  (e.g., EA) receives a reference signal  434  (e.g., internal reference voltage V ref_f ). In one example, the error amplifier  414  (e.g., EA) the sampled signal  430  (e.g., V fb_s ). In another example, the sampled signal  430  (e.g., V fb_s ) is received by the inverting terminal (e.g., the “−” terminal) of the error amplifier  414 . In yet another example, a non-inverting terminal (e.g., the “+” terminal) of the error amplifier  414  receives the reference signal  434 . In another example, the reference signal  434  (e.g., internal reference voltage V ref_f ) is the sum of the compensation voltage ΔV cable  and a reference signal  436  (e.g., reference voltage V ref_cv ). In one embodiment, the reference signal generator  420  generates the reference signal  436  (e.g., reference voltage V ref_cv ). For example, the error amplifier  414  (e.g., EA) generates the signal  274  (e.g., V comp ) based on the reference signal  434  (e.g., internal reference voltage V ref_f ) and the sampled signal  430  (e.g., V fb_s ). In yet another example, the error amplifier  414  (e.g., EA) amplifies the difference between the reference signal  434  (e.g., internal reference voltage V ref_f ) and the sampled signal  430  (e.g., V fb_s ) to generate the signal  274  (e.g., V comp ). For example, the sampled signal  430  (e.g., V fb_s ) relates to the auxiliary winding  226 . 
     In one embodiment, the modulation component  402  (e.g., PWM/PFM control) receives the signal  274  (e.g., V comp ) from the error amplifier  414  (e.g., EA), and outputs a signal  436  to the logic control component  404  based on the signal  274  (e.g., V comp ). For example, the modulation component  402  (e.g., PWM/PFM control) controls the operating frequency and operating mode of the power converter  200 . 
     According to another embodiment, the logic control component  404  outputs a signal  438  to the driver  406 . For example, the driver  406  generates the drive signal  254  based on the signal  438  to affect the primary current  270  (e.g., I pri ). In one example, the primary current  270  (e.g., I pri ) flows through the primary winding  206 . In another example, based on Equations 4 and 5, the drive signal  438  by affecting the primary current  270  (e.g., I pri ) determines the load current I load  (e.g., the output current  264 ). 
     According to yet another embodiment, the logic control component  404  further receives signals  276  and  278  from the comparators  424  and  426  (e.g., COMP and OCP), respectively. For example, the logic control component  404  generates the signal  438  based on the signals  436 ,  276  and  278 . In another example, the logic control component  404  generates the signal  438  based on at least the signals  276  and  278  for generating the drive signal  254  to affect the primary current  270  (e.g., I pri ). 
     In another embodiment, the comparator  424  (e.g., COMP) receives the signal  274  (e.g., V comp ) from the error amplifier  414  (e.g., EA). For example, the comparator  424  (e.g., COMP) receives the signal  274  (e.g., voltage V comp ) at its inverting terminal (e.g., the “−” terminal). In another example, the comparator  424  (e.g., COMP) receives the sensed signal  272  through terminal  240  (e.g., terminal CS) of the controller  202 . In yet another example, the comparator  424  (e.g., COMP) receives the sensed signal  272  at its non-inverting terminal (e.g., the “+” terminal). In one embodiment, the comparator  424  (e.g., COMP) generates the signal  276  based on the sensed signal  272  and the signal  274  (e.g., V comp ). 
     According to another embodiment, the comparator  426  (e.g., OCP) receives a reference signal  444  (e.g., V ref ). For example, the comparator  426  (e.g., OCP) receives the reference signal  444  (e.g., V ref ) at its inverting terminal (e.g., the “−” terminal). In another example, the comparator  426  (e.g., OCP) receives the sensed signal  272  through terminal  240  (e.g., terminal CS) of the controller  202 . In yet another example, the comparator  426  (e.g., OCP) receives the sensed signal  272  at its non-inverting terminal (e.g., the “+” terminal). In one embodiment, the comparator  426  (e.g., OCP) generates the signal  278  based on the sensed signal  272  and the reference signal  444  (e.g., V ref ). For example, the reference signal  444  (e.g., V ref ) is a reference voltage.). 
     In one example, according to the loop control theory, under stable load condition (e.g., a load condition that allows the power converter to operate at equilibrium), the relationship between V fb_s  and V ref_f  can be expressed as follows:
 
 V   fb_s   =V   ref_f   =V   ref_cv   +ΔV   c   (Equation 10)
 
     In another example, V fb_s =V FB , and based on Equations 3 and 10, the load voltage  263  (e.g., V load ) at the equipment terminal  262  can be expressed as follows: 
     
       
         
           
             
               
                 
                   
                     V 
                     
                       l 
                       ⁢ 
                       o 
                       ⁢ 
                       a 
                       ⁢ 
                       d 
                     
                   
                   = 
                   
                     
                       
                         
                           
                             R 
                             2 
                           
                           + 
                           
                             R 
                             3 
                           
                         
                         
                           R 
                           2 
                         
                       
                       × 
                       
                         1 
                         
                           N 
                           S 
                         
                       
                       × 
                       
                         V 
                         
                           ref 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           _ 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           cv 
                         
                       
                     
                     + 
                     
                       
                         
                           
                             R 
                             2 
                           
                           + 
                           
                             R 
                             3 
                           
                         
                         
                           R 
                           2 
                         
                       
                       × 
                       
                         1 
                         
                           N 
                           S 
                         
                       
                       × 
                       Δ 
                       ⁢ 
                       
                         V 
                         c 
                       
                     
                     - 
                     
                       
                         I 
                         
                           l 
                           ⁢ 
                           o 
                           ⁢ 
                           a 
                           ⁢ 
                           d 
                         
                       
                       × 
                       
                         R 
                         
                           c 
                           ⁢ 
                           a 
                           ⁢ 
                           b 
                           ⁢ 
                           l 
                           ⁢ 
                           e 
                         
                       
                     
                     - 
                     
                       V 
                       d 
                     
                   
                 
               
               
                 
                   ( 
                   
                     Equation 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     11 
                   
                   ) 
                 
               
             
           
         
       
     
     For example, if 
                         R   2     +     R   3         R   2       ×     1     N   S       ×   Δ   ⁢     V   c       -       I     l   ⁢   o   ⁢   a   ⁢   d       ×     R     c   ⁢   a   ⁢   b   ⁢   l   ⁢   e           =   0     ,         
the load voltage  263  (e.g., V load ) is well compensated and kept at a constant level. In another example, the compensation voltage ΔV c  is based on the load current I load  (e.g., the output current  264 ), and ΔV c  can be adjust so that the following relationship holds true:
 
                     R   2     +     R   3         R   2       ×     1     N   S       ×   Δ   ⁢     V   c       =       I     l   ⁢   o   ⁢   a   ⁢   d       ×       R     c   ⁢   a   ⁢   b   ⁢   l   ⁢   e       .             
In yet another example, the adjustment of the compensation voltage ΔV c  results in changes to load voltage  263  (e.g., V load ) at the equipment terminal  262  to compensate for the drop in the load voltage  263  (e.g., the drop that is caused by the voltage drop across the diode  212  and/or caused by the output cable line  260 ), and to maintain the load voltage  263  (e.g., V load ) at a constant level.
 
       FIG.  5    is a simplified diagram showing a compensation signal generator as part of the controller  202  according to one embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. The compensation signal generator  418  includes a sample-and-hold signal generator  502 , a buffer  504 , a multiplier  506 , two filters  508  and  510 , a voltage-to-current converter  512 , two summation components  514  and  516  (e.g., signal combiners), a current source component  520  and a cross regulation compensation component  522  (e.g., a signal generator, or a transconductance amplifier). For example, the voltage-to-current converter  512  is a voltage-to-current converter. In another example, the filters  508  and  510  are low-pass filters. In yet another example, each of the summation components  514  and  516  is an adder, a subtractor, or a multiplexer. In yet another example, the summation components  514  is an adder. In yet another example, the summation components  516  is a subtractor. In yet another example, the current source component  520  is a constant-current source. 
     According to one embodiment, the sample-and-hold signal generator  502  samples and holds the sensed signal  272  (e.g., voltage V CS ) from the terminal  524  (e.g., terminal VCS) of the compensation signal generator  418 , and generates the signal  526  (e.g., V 1 ) based on the sensed signal  272 . For example, the signal  526  (e.g., V 1 ) represents the peak voltage of the sensed signal  272  (e.g., voltage V CS ), which corresponds to a peak current of the primary current  270  (e.g., I pri ). In another example, the buffer  504  receives the signal  526  and generates a buffered signal  528  based on the signal  526 . In yet another example, the multiplier  506  receives the buffered signal  528  and the demagnetization signal  428 , and generates a signal  530  (e.g., V 2 ) based on the buffered signal  530  and the demagnetization signal  428 . For example, the magnitude V 2  of signal  530  can be expressed as follows: 
     
       
         
           
             
               
                 
                   
                     V 
                     2 
                   
                   = 
                   
                     K 
                     × 
                     
                       V 
                       
                         C 
                         ⁢ 
                         S 
                       
                     
                     × 
                     
                       
                         T 
                         
                           d 
                           ⁢ 
                           e 
                           ⁢ 
                           m 
                         
                       
                       
                         T 
                         s 
                       
                     
                   
                 
               
               
                 
                   ( 
                   
                     Equation 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     12 
                   
                   ) 
                 
               
             
           
         
       
     
     where K is a magnification constant based on the buffer  504 . 
     According to another embodiment, the signal  530  (e.g., V 2 ) flows from the multiplier  506  to the filter  508 , which generates a signal  532  (e.g., V 3 ) based on the signal  530 . For example, the filter  508  filters out high-frequency components of signal  530  (e.g., V 2 ). In another example, the signal  532  (e.g., V 3 ) represent a direct-current (DC) component of the signal  530  (e.g., V 2 ). In yet another example, the signal  532  (e.g., V 3 ) is converted to a signal  534  (e.g., I o_s ) by the voltage-to-current converter  512 . In one example, the signal  534  (e.g., I o_s ) is a current. In another example, the summation component  514  receives the signal  534  (e.g., I o_s ) and a signal  536  (e.g., I gm ), and generates a signal  538 . In one embodiment, the signal  536  (e.g., I gm ) is a current. For example, the signal  538  is the sum of signal  534  and the signal  536 . In another example, the signal  538  is the sum of two currents (e.g., I o_s +I gm ). In yet another example, based on Equations 8 and 12, the magnitude of the signal  534  (e.g., I o_s ) can be expressed as follows: 
     
       
         
           
             
               
                 
                   
                     I 
                     
                       o 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       _ 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       s 
                     
                   
                   = 
                   
                     
                       
                         V 
                         3 
                       
                       R 
                     
                     = 
                     
                       
                         
                           K 
                           R 
                         
                         × 
                         
                           V 
                           
                             C 
                             ⁢ 
                             S 
                           
                         
                         × 
                         
                           
                             T 
                             
                               d 
                               ⁢ 
                               e 
                               ⁢ 
                               m 
                             
                           
                           
                             T 
                             s 
                           
                         
                       
                       ∝ 
                       
                         I 
                         load 
                       
                     
                   
                 
               
               
                 
                   ( 
                   
                     Equation 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     13 
                   
                   ) 
                 
               
             
           
         
       
     
     where R is a resistance based on the voltage-to-current converter  512 . For example, K and R can be kept at a constant level, and signal  534  (e.g., I o_s ) corresponds to the load current I load  (e.g., the output current  264 ). In another example, signal  534  (e.g., I o_s ) is proportional (e.g., linearly) to the load current I load  (e.g., the output current  264 ). In yet another example, signal  534  (e.g., I o_s ) can be used to adjust the load voltage  263  (e.g., V load ) at the equipment terminal  262 , and to compensate for the drop in the load voltage  263  (e.g., the drop that is caused by the voltage drop across the diode  212  and/or caused by the output cable line  260 ). 
       FIG.  6    is a simplified timing diagram for the compensation signal generator  418  according to one embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. In one embodiment, the waveform  654  represents the drive signal  254  as a function of time. For example, the waveform  654  indicates the turned-on and turned-off conditions of the switch  210  as a function of time. In another embodiment, the waveform  628  represents the demagnetization signal  428  generated by the demagnetization detector  408  as a function of time. In yet another embodiment, the waveform  626  represents the signal  526  (e.g., V 1 ) as a function of time. According to one embodiment, the waveform  672  represents the sensed signal  272  (e.g., voltage V CS ) as a function of time. In another embodiment, the waveform  630  represents the signal  530  (e.g., V 2 ) as a function of time. In yet another embodiment, the waveform  632  represents the signal  532  (e.g., V 3 ) as a function of time. For example, if the waveform  654  is at a logic high level, the switch  210  is closed (e.g., turned on), and if the waveform  654  is at a logic low level, the switch  210  is open (e.g., turned off). 
     According to one embodiment, four time periods T on , T off , T dem , and T s  are shown in  FIG.  6   . In one example, the time period T on  starts at time to and ends at time t 1 , and the time period T off  starts at time t 1  and ends at time t 3 . In another example, the time period T dem  starts at the time t 1  and ends at time t 2 , and the time period T s  starts at the time t 1  and ends at the time t 4 . For example, t 0 ≤t 1 ≤t 2 ≤t 3 ≤t 4 . In another example, the time period T dem  represents the signal pulse width of the demagnetization signal  428 , and is within the time period T off . In yet another example, the time period T s  (e.g., switching period) is the signal period of the demagnetization signal  428 , and includes the time period T dem  (e.g., demagnetization period). 
     According to another embodiment, during a time period (e.g., T on ) when the switch  210  is closed (e.g., on), the sensed signal  272  (e.g., voltage V CS ) increases from a low value (e.g., the value  602  that is, for example, approximately zero at t 0 ) to a peak value (e.g., the peak-voltage value  604  at t 1 ) as shown by the waveform  672 . In one example, at a time (e.g., t 1 ) when the switch  210  changes from closed (e.g., turned on) to open (e.g., turned off), the sensed signal  272  (e.g., voltage V CS ) decreases from the peak value (e.g., the peak-voltage value  604  at t 1 ) to a low value (e.g., the value  606  that is, for example, approximately zero at t 1 ) as shown by the waveform  672 . In another example, the signal  526  (e.g., V 1 ) is approximately constant in magnitude as shown by the waveform  626 . In yet another example, the signal  526  (e.g., V 1 ) represents the peak-voltage value  604  as shown by waveforms  626  and  672 . In one example, at a time (e.g., t 1 ) when the switch  210  changes from closed (e.g., turned on) to open (e.g., turned off), the signal  530  (e.g., V 2 ) increases from a low value (e.g., approximately zero) to a high value (e.g., the value  608  that is, for example, equal to K×V 1 ) as shown by waveform  630 . In yet another example, during a time period (e.g., T dem ) the signal  530  (e.g., V 2 ) keeps a high value (e.g., the value  608  that is, for example, equal to K×V 1 ) as shown by the waveform  630 . In yet another example, at a time (e.g., t 2 ) the signal  530  (e.g., V 2 ) decreases from a high value (e.g., the value  608  that is, for example, equal to K×V 1 ) to a low value (e.g., approximately zero) as shown by the waveform  630 . In yet another example, during a time period (e.g., the time period from t 2  to t 4 ) the signal  530  (e.g., V 2 ) keeps a low value (e.g., approximately zero) as shown by waveform  630 . In one example, during a time period (e.g., T dem ) the signal  532  (e.g., V 3 ) increases from a low value (e.g., the value  610  at t 1 ) to a high value (e.g., the value  612  at t 2 ) as shown by the waveform  632 . For example, during a time period (e.g., the time period from t 2  to t 4 ) the signal  532  (e.g., V 3 ) decreases from a high value (e.g., the value  612  at t 2 ) to a low value (e.g., the value  614  at t 4 ) as shown by the waveform  632 . 
     Referring back to  FIG.  2   , according to one embodiment, the controller  202  is powered via the auxiliary winding  226  through the voltage provided at the terminal  236  (e.g., terminal VCC). Hence, the controller  202  itself draws a current, which represents a load of the power converter  200 . If the load current  265  (e.g., the output current  264 ) is small or there is no load connected to the equipment terminal  262  of the power converter  200 , the current drawn by the controller  202  is not negligible. In this case, the secondary winding  208  and the auxiliary winding  226  exhibit cross regulation that can result in the controller  202  being unable to regulate the load voltage  263  (e.g., V load ), and the load voltage  263  (e.g., V load ) becoming uncontrollably high, if the cross regulation is not compensated for. In one embodiment, the controller  202  compensates for cross regulation (e.g., at a no-load condition or a light-load condition) as part of segment II of the compensation scheme. For example, the controller  202  receives the feedback signal  268  and the sensed signal  272  (e.g., voltage V CS ), and generates the signal  274  (e.g., V comp ) based on the feedback signal and the sensed signal  272  (e.g., voltage V CS ) in order to compensate for cross regulation. 
     As shown in  FIG.  5   , according to another embodiment, the cross regulation compensation component  522  receives the signal  274  (e.g., V comp ) and a reference signal  540  (e.g., V ref1 ). For example, the cross regulation compensation component  522  determines the difference between the signal  274  (e.g., V comp ) and the reference signal  540  (e.g., V ref1 ), and outputs the signal  536  (e.g., I gm ) to the summation component  514 . In yet another example, the signal  536  (e.g., I gm ) is a current. In another example, the magnitude of the signal  536  (e.g., I gm ) can be determined as follows:
 
 I   gm   =gm ×( V   comp   −V   ref1 )  (Equation 14)
 
     where gm is a constant transconductance value (e.g., an amplification value) of the cross regulation compensation component  522 . For example, the signal  536  (e.g., I gm ) increases in magnitude if the signal  274  (e.g., V comp ) increases in magnitude. In another example, the signal  536  (e.g., I gm ) is clamped at a constant value (e.g., L dc ) if the signal  536  (e.g., I gm ) becomes too high (e.g., exceeds a predetermined threshold value). 
     In another embodiment, the summation component  514  receives the signal  534  (e.g., I o_s ) and the signal  536  (e.g., I gm ), and generates the signal  538 . For example, the signal  538  is the sum of signal  534  and the signal  536 . In another example, the signal  538  flows from the summation component  514  to the filter  510 , and the filter  510  generates the signal  542  that is received by the summation component  516 . In yet another example, the summation component  516  further receives the signal  544  (e.g., I dc ) from the current source component  520 , and generates the compensation signal  432  (e.g., I c ) based on the signal  542  and the signal  544  (e.g., I dc ). In yet another example, the summation component  516  subtracts the signal  542  from signal  544  (e.g., I dc ) to generate the compensation signal  432  (e.g., I c ). In yet another example, the magnitude of the compensation signal  432  (e.g., I c ) can be determined as follows:
 
 I   c   =I   gm   +I   o_s   −I   dc   (Equation 15)
 
       FIG.  7    is a simplified diagram showing the compensation signal as a function of the load current according to certain embodiments of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. The axis  702  represents the load current  265  (e.g., I load ), and the axis  704  represents the compensation signal  432  (e.g., I c ). Additionally, the line  710  represents the compensation signal  432  as a function of the load current  265  (e.g., I load ). For example, the load current  265  (e.g., I load ) is the output current  264  (e.g., I out ). 
     In one example, when the power converter is operating at a no-load condition, the signal  536  (e.g., I gm ) and the signal  534  (e.g., I o_s ) are both zero in magnitude, and, based on Equation 15, the compensation signal  432  (e.g., I c ) can be determined as follows: I c =I dc . In this example, the reference signal  436  (e.g., reference voltage V ref_cv ) is negatively compensated, and, based on Equation 9, the compensation voltage ΔV c  can be determined as follows: ΔV c =−I dc ×R c . At this load condition, for example, the output voltage is reduced, and the impact of the cross regulation is compensated for with segment II of the compensation scheme. 
     In another example, when the power converter is operating at a low-load condition, the signal  536  (e.g., I gm ) and the signal  534  (e.g., Io o_s ) are close to zero in magnitude or small in magnitude. In this example, the reference signal  436  (e.g., reference voltage V ref_cv ) is also negatively compensated. At this load condition, for example, the output voltage is reduced, and the impact of the cross regulation is compensated for with segment II of the compensation scheme. 
     In yet another example, when the power converter is operating at a load that results in I gm +I o_s =I dc , based on Equation 15, the compensation signal  432  (e.g., I c ) is zero in magnitude. For example, based on Equation 9, the compensation voltage ΔV c  is also zero in magnitude. At this load condition, for example, little or no compensation is provided. 
     According to another example, when the load increases, the signal  274  (e.g., V comp ) increases in magnitude, and, in turn, the signal  536  (e.g., I gm ) increases in magnitude. If, for example, the signal  536  (e.g., I gm ) becomes too high (e.g., exceeds a predetermined threshold value), the signal  536  (e.g., I gm ) is clamped at a constant value (e.g., L dc ) so that I gm =I dc . In another example, based on Equation 15, the compensation signal  432  (e.g., I c ) can be determined as follows: I c =I o_s , and, for example, based on Equation 9, the compensation voltage ΔV c  is: ΔV c =I o_s ×R c . In yet another example, based on Equation 13, the compensation signal  432  (e.g., I c ) is proportional (e.g., linearly) to the load current  265  (e.g., the output current  264 ), and the compensation voltage ΔV c  is proportional (e.g., linearly) to the load current  265  (e.g., the output current  264 ). At this load condition (e.g., at a high-load condition), for example, the drop in the load voltage  263  (e.g., the drop that is caused by the voltage drop across the diode  212  and/or caused by the output cable line  260 ) is compensated for with segment I of the compensation scheme, and based on Equation 11, the load voltage  263  (e.g., V load ) can be maintained at a constant level. 
       FIG.  8    is a simplified diagram showing certain components of the compensation signal generator  418  according to another embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. The compensation signal generator  418  includes the sample-and-hold signal generator  502 , the buffer  504 , the multiplier  506 , the filters  508  and  510 , the voltage-to-current converter  512 , the summation components  514  and  516 , the current source component  520  and the signal generator  522 . For example, the voltage-to-current converter  512  is a voltage-to-current converter. In another example, the filters  508  and  510  are low-pass filters. In yet another example, each of the summation components  514  and  516  is an adder, a subtractor, or a multiplexer. In yet another example, the summation component  514  is an adder. In yet another example, the summation components  516  is a subtractor. In yet another example, the current source component  520  is a constant-current source. 
     According to one embodiment, the sample-and-hold signal generator  502  includes a switch  802  (e.g., NMO) and a capacitor  804  (e.g., C 0 ). For example, the switch  802  (e.g., NMO) is a transistor. In another example, the sample-and-hold signal generator  502  samples and holds the sensed signal  272  (e.g., voltage V CS ) from terminal  524  (e.g., terminal VCS) of the compensation signal generator  418 , and generates the signal  526  (e.g., V 1 ) based on the sensed signal  272 . In yet another example, the switch  802  samples the sensed signal  272  (e.g., voltage V CS ) in response to signal  806  (e.g., T on ), and the capacitor  804  (e.g., C 0 ) holds the signal  526  (e.g., V 1 ). In yet another example, the signal  526  (e.g., V 1 ) represents the peak voltage of the sensed signal  272  (e.g., voltage V CS ). In yet another example, the buffer  504  receives the signal  526  (e.g., V 1 ), and generates the buffered signal  528  based on the signal  526 . In yet another example, the buffer  504  generates the buffered signal  528  (e.g., K×V 1 ) by amplifying the signal  526  (e.g., V 1 ) K times. 
     According to another embodiment, the multiplier  506  includes an inverter  808  (e.g., NOT gate) and two switches  810  and  812  (e.g., NM 1  and NM 2 ). For example, each of the switches  810  and  812  (e.g., NM 1  and NM 2 ) is a transistor. In another example, the multiplier  506  receives the buffered signal  528  and the demagnetization signal  428 , and generates the signal  530  (e.g., V 2 ) based on the buffered signal  528  and the demagnetization signal  428 . In yet another example, the multiplier  506  processes the demagnetization signal  428  and determines on-sets (e.g., rising edges) of two consecutive demagnetization periods (e.g., two consecutive T dem ) in order to determine a switching period (e.g., T s ). 
     In yet another example, the switch  810  (e.g., NM 1 ) is closed (e.g., turned on) if the demagnetization signal  428  is at a logic high level. In yet another example, the switch  812  (e.g., NM 2 ) is closed (e.g., turned on) if the demagnetization signal  428  is at a logic low level. In yet another example, the switch  810  (e.g., NM 1 ) is open (e.g., turned off) if the demagnetization signal  428  is at a logic low level. In yet another example, the switch  812  (e.g., NM 2 ) is open (e.g., turned off) if the demagnetization signal  428  is at a logic high level. In yet another example, the signal  530  (e.g., V 2 ) is a pulse wave including a high value (e.g., K×V 1 , where V 1  is the peak voltage of V CS ) and a low value (e.g., approximately zero). In yet another example, the duty cycle of the signal  530  (e.g., V 2 ) is identical to the duty cycle of the demagnetization signal  428 . 
     According to another embodiment, the filter  508  includes a resistor  814  (e.g., R 1 ), three capacitors  816 ,  818 , and  820  (e.g., C 1 , C 1 , and C 3 ), two switches  822  and  824  (e.g., NM 3  and NM 4 ), and an inverter  826  (e.g., NOT gate). For example, each of the switches  822  and  824  (e.g., NM 3  and NM 4 ) is a transistor. In another example, the signal  530  (e.g., V 2 ) flows from the multiplier  506  to the filter  508 , which generates the signal  532  (e.g., V 3 ) based on the signal  530 . In yet another example, the filter  508  filters out high-frequency components of signal  530  (e.g., V 2 ). In another example, the signal  532  (e.g., V 3 ) represent a direct-current (DC) component of the signal  530  (e.g., V 2 ). 
     According to yet another embodiment, the voltage-to-current converter  512  includes an amplifier  828  (e.g., OP 1 ), a switch  830  (e.g., NM 5 ), and a resistor  832  (e.g., R 2 ). For example, the amplifier  828  (e.g., OP 1 ) is an operational amplifier. In another example, the switch  830  (e.g., NM 5 ) is a transistor. In yet another example, the signal  532  (e.g., V 3 ) is converted to the signal  534  (e.g., I o_s ) by the voltage-to-current converter  512 . In yet another example, the signal  534  (e.g., I o_s ) is a current. 
     According to yet another embodiment, the summation component  514  includes two switches  834  and  836  (e.g., MP 1  and MP 2 ). For example, each of the switches  834  and  836  (e.g., MP 1  and MP 2 ) is a transistor. In another example, the summation component  514  receives the signal  534  (e.g., I o_s ) and the signal  536  (e.g., I gm ), and generates the signal  538 . In yet another example, the signal  536  (e.g., I gm ) is a current. In yet another example, the signal  538  is the sum of signal  534  and the signal  536 . In one example, the signal  534  (e.g., I o_s ) and the signal  536  (e.g., I gm ) are added by the switch  834  (e.g., MP 1 ), and transferred to the filter  510  via the switch  836  (e.g., MP 2 ). 
     According to yet another embodiment, the filter  510  includes three resistors  838 ,  840 , and  842  (e.g., R 3 , R 4 , and R 5 ), two capacitors  844 , and  846  (e.g., C 4 , and C 5 ), and three switches  848 ,  850 , and  852  (e.g., NM 6 , NM 7 , and NM 8 ). For example, each of the switches  848 ,  850 , and  852  (e.g., NM 6 , NM 7 , and NM 8 ) is a transistor. In another example, the filter  510  receives the signal  538  from the summation component  514 . In yet another example, the filter  510  generates the signal  542  based on the signal  538 , and outputs the signal  542  to the summation component  516 , which includes two switches  854 , and  856  (e.g., MP 3 , and MP 4 ). In yet another example, each of the switches  854 , and  856  (e.g., MP 3 , and MP 4 ) is a transistor. In yet another example, the summation component  516  further receives the signal  544  (e.g., I dc ) from the current source component  520 , and generates the compensation signal  432  (e.g., I c ) based on the signal  542  and the signal  544  (e.g., I dc ). In yet another example, the summation component  516  subtracts the signal  542  from signal  544  (e.g., I dc ) to generate the compensation signal  432  (e.g., I c ). 
     According to yet another embodiment, the cross regulation compensation component  522  includes an amplifier  858  (e.g., gm). For example, the amplifier  858  is a transconductance amplifier. In another example, the amplifier  858  receives the signal  274  (e.g., V comp ) at its non-inverting terminal (e.g., the “+” terminal). In yet another example, the amplifier  858  receives the reference signal  540  (e.g., V ref1 ) at its inverting terminal (e.g., the “−” terminal). In yet another example, the cross regulation compensation component  522  determines the difference between the signal  274  (e.g., V comp ) and the reference signal  540  (e.g., V ref1 ), and outputs the signal  538  (e.g., I gm ) to the summation component  514 . 
     In some embodiments, the compensation signal generator  418  as shown in  FIG.  8    operates according to the simplified timing diagram as shown in  FIG.  6   . In certain embodiments, the compensation signal  432  (e.g., I c ) as shown in  FIG.  8    is a function of the load current  265  (e.g., the output current  264 ) as shown in  FIG.  7   . 
     According to one embodiment, a system controller for regulating a power converter includes a first controller terminal; a second controller terminal; and a compensation current generator. The compensation current generator is configured to receive an input signal through the first controller terminal. The input signal indicates a first current flowing through a primary winding of a power converter. The compensation current generator is configured to receive a demagnetization signal related to a demagnetization period of the power converter and associated with an auxiliary winding of the power converter. The compensation current generator is configured to generate a compensation current based at least in part on the input signal and the demagnetization signal. The compensation current generator is connected to a resistor. The resistor is configured to generate a compensation voltage based at least in part on the compensation current and output a first reference voltage based at least in part on the compensation voltage and a second reference voltage. The system controller is configured to: generate an amplified signal based at least in part on the second reference voltage; generate a drive signal based at least in part on the amplified signal; and output the drive signal through the second controller terminal to a switch to affect the first current flowing through the primary winding of the power converter. For example, the system controller is implemented according to at least  FIG.  3   , and/or  FIG.  4   . 
     In some examples, the first reference voltage is equal to a sum of the compensation voltage and the second reference voltage. In certain examples, the system controller is further configured to generate the amplified signal based at least in part on the second reference voltage and a sampled signal related to the auxiliary winding of the power converter. For example, the system controller further includes: an error amplifier configured to receive the sampled signal and a second reference signal and generate the amplified signal based at least in part on the sampled signal and the second reference signal. As an example, the error amplifier is further configured to receive the sampled signal at an inverting terminal and the second reference signal at a non-inverting terminal. 
     In other examples, the system controller further includes: a demagnetization detector configured to receive a feedback signal related to the auxiliary winding of the power converter and generate the demagnetization signal based at least in part on the feedback signal. For example, the system controller further includes: a sample-and-hold circuit configured to sample the feedback signal and output a sampled signal based at least in part on the feedback signal. In some examples, the system controller further includes: a comparator configured to receive the amplified signal and the input signal and generate a comparison signal. The system controller is further configured to generate the drive signal based at least in part on the comparison signal. In certain examples, the compensation current generator is configured to receive the amplified signal and generate the compensation current based at least in part on the amplified signal. 
     In other examples, the compensation current generator is further configured to generate the compensation current so that an output voltage of the power converter is independent of an output current of the power converter, the output voltage and the output current being related to a secondary winding of the power converter coupled to the primary winding. In some examples, the compensation current generator is further configured to generate the compensation current to keep an output voltage of the power converter at a constant level under one or more load conditions of the power converter. For example, the one or more load conditions include a no-load condition or a low-load condition. As an example, the one or more load conditions include a high condition. 
     According to another embodiment, a system controller for regulating a power converter includes: a sample-and-hold signal generator; a multiplier; and a first filter. The sample-and-hold signal generator is configured to receive a first input signal and generate a sampled-and-held signal based at least in part on the first input signal. The first input signal indicates a first current flowing through a primary winding of a power converter. The sampled-and-held signal represents a peak of the first current. The multiplier is configured to receive a demagnetization signal and generate a multiplication signal based on at least information associated with the demagnetization signal and the sampled-and-held signal. The demagnetization signal is related to a demagnetization period of the power converter and is associated with an auxiliary winding of the power converter. The first filter is configured to receive the multiplication signal and generate a first filtered signal based at least in part on the multiplication signal. The first filtered signal is related to a drive signal outputted to a switch to affect the first current flowing through the primary winding of the power converter. For example, the system controller is implemented according to at least  FIG.  5   ,  FIG.  6   , and/or  FIG.  8   . 
     In some examples, the system controller further includes: a buffer configured to receive the sampled-and-held signal and generate a buffered signal. The multiplier is further configured to: receive the buffered signal; and generate the multiplication signal based on the buffered signal and the demagnetization signal. In certain examples, the system controller includes: a voltage-to-current converter configured to receive the first filtered signal and generate a second current; and a first signal combiner configured to receive the second current and a third current and generate a summation signal based at least in part on the second current and the third current. For example, the system controller further includes: a second filter configured to receive the summation signal and generate a second filtered signal based at least in part on the summation signal; a current source configured to generate a constant current; and a second signal combiner configured to receive the second filtered signal and the constant current and output a compensation current to generate the drive signal. As an example, the second signal combiner is further configured to subtract the second filtered signal from the constant current to generate the compensation current. 
     In certain examples, the system controller further includes: a transconductance amplifier configured to receive a second input signal and a reference signal and generate the third current. The third current is equal to an amplification value multiplied by a difference between the second input signal and the reference signal. For example, the third current is equal to the amplification value multiplied by a subtraction result. The subtraction result is equal to the second input signal minus the reference signal. As an example, the system controller further includes: an error amplifier configured to generate a second input signal based on at least information associated with a compensation current. The system controller is configured to: generate the drive signal based on at least information associated with the second input signal. In one example, the error amplifier is further configured to generate the second input signal based at least in part on a sampled signal associated with the auxiliary winding and a reference signal related to the compensation current. 
     In other examples, the system controller further includes: a second filter configured to generate a second filtered signal based on at least information associated with the first filtered signal. The second filtered signal is related to the drive signal. In some examples, the system controller is configured to generate a compensation current based at least in part on the first filtered signal so that an output voltage of the power converter is independent of an output current of the power converter, the output voltage and the output current being related to a secondary winding of the power converter coupled to the primary winding. In certain examples, the system controller is further configured to generate a compensation current based at least in part on the first filtered signal to keep an output voltage of the power converter at a constant level under one or more load conditions of the power converter. For example, the one or more load conditions include a no-load condition or a low-load condition. As an example, the one or more load conditions include a high condition. 
     According to yet another embodiment, a system controller for regulating a power converter includes: a signal generator; and an error amplifier. The signal generator is configured to receive an input signal and a reference signal and output an output signal to generate a drive signal. The output signal is equal to an amplification value multiplied by a difference between the input signal and the reference signal. The error amplifier is configured to generate the input signal based on at least information associated with the output signal. The system controller is configured to: generate the drive signal based on at least information associated with the input signal; and output the drive signal to a switch of a power converter to affect a current flowing through a primary winding of the power converter. For example, the system controller is implemented according to at least  FIG.  5   ,  FIG.  6   , and/or  FIG.  8   . 
     In some examples, the output signal is equal to the amplification value multiplied by a subtraction result. The subtraction result is equal to the input signal minus the reference signal. In certain examples, the output signal is related to a compensation current. For example, the error amplifier is further configured to generate the input signal based on at least information associated with the compensation current. As an example, the error amplifier is further configured to receive a sampled signal associated with an auxiliary winding of the power converter and generate the input signal based on at least information associated with the compensation current and the sampled signal. In other examples, the system controller further includes: a filter configured to generate a filtered signal based on at least information associated with the output signal. The system controller is further configured to: generate the drive signal based on at least information associated with the filtered signal. In some examples, the system controller is configured to generate a compensation current based at least in part on the output signal so that an output voltage of the power converter is independent of an output current of the power converter, the output voltage and the output current being related to a secondary winding of the power converter coupled to the primary winding. 
     In certain examples, the system controller is further configured to generate a compensation current based at least in part on the output signal to keep an output voltage of the power converter at a constant level under one or more load conditions of the power converter. For example, the one or more load conditions include a no-load condition or a low-load condition. As an example, the one or more load conditions include a high condition. 
     According to yet another embodiment, a system controller for regulating a power converter includes: a first controller terminal; a second controller terminal; a compensation current generator; and an error amplifier. The compensation current generator is configured to: receive an input signal through the first controller terminal. The input signal indicates a first current flowing through a primary winding of a power converter. The compensation current generator is configured to: receive an amplified signal; and generate a compensation current based at least in part on the input signal and the amplified signal. The error amplifier is configured to: generate the amplified signal based on at least information associated with the compensation current; output the amplified signal to the compensation current generator; and output the amplified signal to generate a drive signal outputted through the second controller terminal to a switch to affect the first current flowing through the primary winding of the power converter. For example, the system controller is implemented according to at least  FIG.  3   , and/or  FIG.  4   . 
     In some examples, the error amplifier is further configured to receive a sampled signal associated with an auxiliary winding of the power converter and generate the amplified signal based at least in part on the sampled signal. For example, the system controller further includes: a demagnetization detector configured to receive a feedback signal related to the auxiliary winding and generate a demagnetization signal based at least in part on the feedback signal. As an example, the compensation current generator is configured to receive the demagnetization signal and generate the compensation current based at least in part on the input signal and the demagnetization signal. In one example, the system controller further includes: a sample-and-hold circuit configured to sample the feedback signal and output the sampled signal based at least in part on the feedback signal. 
     In certain examples, the system controller further includes: a comparator configured to receive the amplified signal and the input signal and generate a comparison signal. The system controller is further configured to generate the drive signal based at least in part on the comparison signal. In other examples, the compensation current generator is further configured to generate the compensation current so that an output voltage of the power converter is independent of an output current of the power converter, the output voltage and the output current being related to a secondary winding of the power converter coupled to the primary winding. In some examples, the compensation current generator is further configured to generate the compensation current to keep an output voltage of the power converter at a constant level under one or more load conditions of the power converter. For example, the one or more load conditions include a no-load condition or a low-load condition. As an example, the one or more load conditions include a high condition. 
     According to yet another embodiment, a system controller for regulating a power converter includes: a first controller terminal; a second controller terminal; a compensation current generator; and an error amplifier. The compensation current generator is configured to: receive an input signal through the first controller terminal. The input signal indicates a first current flowing through a primary winding of a power converter. The compensation current generator is configured to: receive a demagnetization signal related to a demagnetization period of the power converter and associated with an auxiliary winding of the power converter; receive an amplified signal; in response to the power converter operating under a first load condition, generate a compensation current based at least in part on the input signal and the amplified signal; and in response to the power converter operating under a second load condition, generate the compensation current based at least in part on the input signal and the demagnetization signal. The error amplifier is configured to: generate the amplified signal based on at least information associated with the compensation current; output the amplified signal to the compensation current generator; and output the amplified signal to generate a drive signal outputted through the second controller terminal to a switch to affect the first current flowing through the primary winding of the power converter. The first load condition and the second load condition are different. For example, the system controller is implemented according to at least  FIG.  3   ,  FIG.  4    and/or  FIG.  7   . 
     In some examples, the system controller further includes: a demagnetization detector configured to receive a feedback signal related to the auxiliary winding and generate the demagnetization signal based at least in part on the feedback signal. For example, the error amplifier is further configured to receive a sampled signal associated with the feedback signal and generate the amplified signal based at least in part on the sampled signal. In certain examples, the compensation current generator is further configured to generate the compensation current to keep an output voltage of the power converter at a constant level under the first load condition and the second load condition. In other examples, the first load condition includes a no-load condition or a low-load condition. In some examples, the second load condition includes a high-load condition. 
     According to yet another embodiment, a method for regulating a power converter includes: receiving an input signal. The input signal indicates a first current flowing through a primary winding of a power converter. The method includes: receiving a demagnetization signal related to a demagnetization period of the power converter and associated with an auxiliary winding of the power converter; generating a compensation current based at least in part on the input signal and the demagnetization signal; generating a compensation voltage based at least in part on the compensation current; outputting a first reference voltage based at least in part on the compensation voltage and a second reference voltage; generating an amplified signal based at least in part on the second reference voltage; generating a drive signal based at least in part on the amplified signal; and outputting the drive signal to a switch to affect the first current flowing through the primary winding of the power converter. For example, the method is implemented according to at least  FIG.  3    and/or  FIG.  4   . 
     According to yet another embodiment, a method for regulating a power converter includes: receiving an input signal. The input signal indicates a current flowing through a primary winding of a power converter. The method includes: generating a sampled-and-held signal based at least in part on the input signal. The sampled-and-held signal represents a peak of the current. The method includes: receiving a demagnetization signal; and generating a multiplication signal based on at least information associated with the demagnetization signal and the sampled-and-held signal. The demagnetization signal is related to a demagnetization period of the power converter and is associated with an auxiliary winding of the power converter. The method includes: receiving the multiplication signal; and generating a filtered signal based at least in part on the multiplication signal. The filtered signal is related to a drive signal. The method includes: outputting the drive signal to a switch to affect the current flowing through the primary winding of the power converter. For example, the method is implemented according to at least  FIG.  5   ,  FIG.  6   , and/or  FIG.  8   . 
     According to yet another embodiment, a method for regulating a power converter includes: receiving an input signal and a reference signal; and outputting an output signal to generate a drive signal. The output signal is equal to an amplification value multiplied by a difference between the input signal and the reference signal. The method includes: generating the input signal based on at least information associated with the output signal; generating the drive signal based on at least information associated with the input signal; and outputting the drive signal to a switch of a power converter to affect a current flowing through a primary winding of the power converter. For example, the method is implemented according to at least  FIG.  5   ,  FIG.  6   , and/or  FIG.  8   . 
     According to yet another embodiment, a method for regulating a power converter includes: receiving an input signal. The input signal indicates a first current flowing through a primary winding of a power converter. The method includes: receiving an amplified signal; generating a compensation current based at least in part on the input signal and the amplified signal; generating the amplified signal based on at least information associated with the compensation current; generating a drive signal based at least in part on the amplified signal; and outputting the drive signal to a switch to affect the first current flowing through the primary winding of the power converter. For example, the method is implemented according to at least  FIG.  3   , and/or  FIG.  4   . 
     According to yet another embodiment, a method for regulating a power converter includes: receiving an input signal. The input signal indicates a first current flowing through a primary winding of a power converter. The method includes: receiving a demagnetization signal related to a demagnetization period of the power converter and associated with an auxiliary winding of the power converter; receiving an amplified signal; in response to the power converter operating under a first load condition, generating a compensation current based at least in part on the input signal and the amplified signal; in response to the power converter operating under a second load condition, generating the compensation current based at least in part on the input signal and the demagnetization signal; generating the amplified signal based on at least information associated with the compensation current; generating a drive signal based at least in part on the amplified signal; and outputting the drive signal to a switch to affect the first current flowing through the primary winding of the power converter. The first load condition and the second load condition are different. For example, the method is implemented according to at least  FIG.  3   ,  FIG.  4    and/or  FIG.  7   . 
     For example, some or all components of various embodiments of the present invention each are, individually and/or in combination with at least another component, implemented using one or more software components, one or more hardware components, and/or one or more combinations of software and hardware components. In another example, some or all components of various embodiments of the present invention each are, individually and/or in combination with at least another component, implemented in one or more circuits, such as one or more analog circuits and/or one or more digital circuits. In yet another example, various embodiments and/or examples of the present invention can be combined. 
     Although specific embodiments of the present invention have been described, it will be understood by those of skill in the art that there are other embodiments that are equivalent to the described embodiments. Accordingly, it is to be understood that the invention is not to be limited by the specific illustrated embodiments, but only by the scope of the appended claims.