Patent Publication Number: US-9853842-B2

Title: Continuous time linear equalization for current-mode logic with transformer

Description:
CROSS-REFERENCES TO RELATED APPLICATIONS 
     The present application is a continuation of U.S. patent application Ser. No. 15/074,530 filed on Mar. 18, 2016, which is a continuation of U.S. patent application Ser. No. 14/679,934 filed on Apr. 6, 2015, the entire content of which is incorporated herein by reference. 
    
    
     BACKGROUND OF THE INVENTION 
     The present invention is directed to data communication systems and methods. 
     Over the last few decades, the use of communication networks exploded. In the early days of the Internet, popular applications were limited to emails, bulletin board, and mostly informational and text-based web page surfing, and the amount of data transferred was usually relatively small. Today, Internet and mobile applications demand a huge amount of bandwidth for transferring photo, video, music, and other multimedia files. For example, a social network like Facebook processes more than 500 TB of data daily. With such high demands on data and data transfer, existing data communication systems need to be improved to address these needs. For high-data communication applications, current-mode logic (CML) is often used as a part of a communication interface. 
     Over the past, there have been many types of communication systems and methods. Unfortunately, they have been inadequate for various applications. More specifically, the CMLs of existing communication systems are often inadequate. Therefore, improved systems and methods are desired. 
     BRIEF SUMMARY OF THE INVENTION 
     The present invention is directed to data communication systems and methods. More specifically, embodiments of the present invention provide a CML that uses one or more equalization modules to apply equalization via secondary windings of transformers that are coupled, directly or indirectly, to the CML outputs. An equalization modules includes a digital-to-analog converter (DAC) component that generates switching signals based on control signals received from an external equalization module. The equalization module also includes switchable resistors and/or capacitors. The switching signals are used to select the switchable resistors and/or capacitors. By switching resistors and/or capacitors at the equalization module, the outputs of the CML are equalized. There are other embodiments as well. 
     According to an embodiment, the present invention provides a current mode logic device. The device includes a first input and a second input for receiving data. The device also includes a first transistor comprising a first gate and a first output terminal and a first source terminal. The first gate is electrically coupled to the first input. The device further includes a second transistor comprising a second gate and a second output terminal. The second gate is electrically coupled to the second input. The device also includes a capacitor module coupled to the first source terminal. The capacitor module includes a plurality of capacitors. The device further includes a first resistor coupled to the first output terminal and a second resistor coupled to the second output terminal. The device includes a first transformer comprising a first primary winding and a first secondary winding. The primary winding is electrically coupled to the first resistor and the first output terminal. The device additionally includes a first equalization module coupled to the first secondary winding. The first equalization module includes a first DAC unit and a first plurality of resistors. The first DAC unit is configured to selectively switching one or more of the first plurality of resistors in response to equalization signals received from an equalization logic. 
     According to another embodiment, the present invention provides a communication system. The system includes a first communication line and a second communication line. The system also includes an adaptive equalization module. The system also includes a CML coupled to the first communication line and the second communication line. The CML comprises a first input and a second input for receiving data. The first input is coupled to the first communication line. The second input is coupled to the second communication line. The CML also includes a first transistor comprising a first gate and a first output terminal and a first source terminal. The first gate is electrically coupled to the first input. The CML further includes a second transistor comprising a second gate and a second output terminal. The second gate is electrically coupled to the second input. The CML additionally includes a capacitor module coupled to the first source terminal. The capacitor module includes a plurality of capacitors. The CML also includes a first transformer comprising a first primary winding and a first secondary winding. The first primary winding is electrically coupled to the first output terminal. The CML also includes a first equalization module coupled to the first secondary winding. The first equalization module includes a first DAC unit and a first plurality of resistors. The first DAC unit is configured to selectively switching one or more of the first plurality of resistors in response to equalization signals received from the adaptive equalization module. 
     According to yet another embodiment, the present invention provides a current mode logic device. The device includes a first input and a second input for receiving data. The device also includes a first transistor comprising a first gate and a first output terminal, and the first gate is electrically coupled to the first input. The device also includes a second transistor comprising a second gate and a second output terminal. The second gate is electrically coupled to the second input. The device further includes a first resistor coupled to the first output terminal. The device also includes a second resistor coupled to the second output terminal. The device includes a first transformer comprising a first primary winding and a first secondary winding. The first primary winding is electrically coupled to the first resistor and the first output terminal. The device additionally includes a first equalization module coupled to the first secondary winding. The first equalization module includes a first DAC unit and a first plurality of capacitors. The first DAC unit is configured to selectively switching one or more of the first plurality of capacitors in response to equalization signals received from an equalization logic. 
     It is to be appreciated that embodiments of the present invention provide many advantages over conventional systems. Through using transformers coupled to the output of CML devices, equalization of the output peaking magnitude can be effectively applied without shifting peaking frequency. Additionally, since DACs are used to control the equalization modules coupled to the CML, embodiments of the present invention are compatible with a variety of equalization systems, including adaptive equalization schemes such as decision feedback equalization (DFE). Embodiments of the presentation can be provided using existing semiconductor manufacturing processes, and thus can be inexpensively implemented in a range of systems. There are other benefits as well. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a simplified diagram illustrating connecting CML to a pair of communication line. 
         FIG. 2  is a simplified diagram illustrating a convention CML. 
         FIG. 3  is simplified diagram illustrating a CML according to an embodiment of the present invention. 
         FIGS. 4A and 4B  are simplified diagrams illustrating equalization modules according to embodiments of the present invention. 
         FIG. 5  is a simplified diagram illustrating equalization applied to an output data line. 
         FIG. 6  is a graph illustrating simulation of applying equalization at different settings of an equalization module according to an embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The present invention is directed to data communication systems and methods. More specifically, embodiments of the present invention provide a CML that uses one or more equalization modules to apply equalization via secondary windings of transformers that are coupled, directly or indirectly, to the CML outputs. An equalization modules includes a DAC component that generates switching signals based on control signals received from an external equalization module. The equalization module also includes switchable resistors and/or capacitors. The switching signals are used to select the switchable resistors and/or capacitors. By switching resistors and/or capacitors at the equalization module, the outputs of the CML are equalized. There are other embodiments as well. 
     Current mode logic, as mentioned above, has a wide range of applications. Among other features, CML provides fast operation and low power consumption, which makes it suitable for high-speed communication. For low-power and high-speed communication systems, such as optical communication network, CML can be used as a part of a device interface. In addition to being used in optical networks, CMLs have been used in various type of video links, such as HDMI, DVI, and others. 
     Used as buffers, CMLs have been implemented in tapered buffer chains, serializer-deserializer (SerDes) circuits, clock and data recover (CDR), multiplexers, and many others. With relatively low voltage swings, compared to static CMOS circuits, CML provides high-speed operation that is important for interface and communication applications. For example, CML can operates at a speed well over 200 Mbit/s. 
       FIG. 1  is a simplified diagram illustrating connecting CML to a pair of communication line. For example, a set of differential lines is provided between the source  101  and the destination  102 . A voltage Vcc of the CML is coupled to both of the differential lines respectively via resistors. 
       FIG. 2  is a simplified diagram illustrating a convention CML. As shown in  FIG. 2 , a pair of differential inputs Vin_P  206  and Vin_N  205  are respectively coupled to a pair of CMOS devices. A variable impedance module  207  controls a bank of capacitors and/or resistors gates. For example, by varying capacitor and/or resistor values, the source voltages of CMOS transistors can be changed, thus altering output voltages. However, as explained below, changing capacitance of the impedance module  207  would also cause a shift in peaking frequency. As shown, the outputs pair Vout_P  203  and Vout_N  204  are respectively coupled to resistors  201  and  202 . For example, as shown in  FIG. 1 , a CML is typically coupled to communication lines with resistors. 
     CMLs, as mentioned above, is often used in communication lines. For example, many SerDes transceivers utilize CMLs as a part of the transmission line. Similar to other types of communication devices, Serdes transceivers often need to use one or more equalizers to compensate channel attenuation (loss). More specifically, equalization is often needed to compensate high frequency losses in communication channels. By using equalization techniques to compensate channel attenuation, effective channel length can be increased and communication channel reliability improved. Preferably, equalization technique can be adjustable to compensate channels with different levels of attenuation. For example, equalization adjustment may be manual or automatic. For example, various types of linear and adaptive equalization techniques have been used. Often, automatic adjustment is referred to as “adaptive equalization”. In communication systems and SerDes, various types of linear and adaptive equalization techniques have been used. 
     An important aspect of providing equalization is applying equalization to communication channels. Among other things, designing a high bandwidth high gain EQ is challenging. Various equalization designs come with their power and/or area penalties. For example, a common approach involves adding inductors for gain peaking, but unfortunately this approach can only provide a fixed level of equalization, and it comes with a significant area penalty. In some conventional systems, equalization is provide by amplifiers with controllable degeneration and inductive gain peaking, and this approach provides controllable levels of equalization, but unfortunately adds significant power and area penalties. 
     It is to thus to be appreciated that embodiments of the present invention provide CMLs that are capable of applying adjustable equalization. Among other things, by applying equalization through CMLs, energy efficient and high performance equalization can be achieved. For example, CMLs equalization can be applied without incurring a large amount of power consumption. As described below, CMLs according to embodiments of the present invention comprise one or more transformers on their respective load stages, and these transformers function as tuned bandwidth boosters. It is to be appreciated that controlling the peaking of the inductor from the secondary winding reduces the component parasitic and power consumption. With transformer(s) as a load to CMLs, continuous time linear equalization (CTLE) can be applied. CMLs according to embodiments of the present invention are described in further details below. 
     The following description is presented to enable one of ordinary skill in the art to make and use the invention and to incorporate it in the context of particular applications. Various modifications, as well as a variety of uses in different applications will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to a wide range of embodiments. Thus, the present invention is not intended to be limited to the embodiments presented, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein. 
     In the following detailed description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. However, it will be apparent to one skilled in the art that the present invention may be practiced without necessarily being limited to these specific details. In other instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring the present invention. 
     The reader&#39;s attention is directed to all papers and documents which are filed concurrently with this specification and which are open to public inspection with this specification, and the contents of all such papers and documents are incorporated herein by reference. All the features disclosed in this specification, (including any accompanying claims, abstract, and drawings) may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise. Thus, unless expressly stated otherwise, each feature disclosed is one example only of a generic series of equivalent or similar features. 
     Furthermore, any element in a claim that does not explicitly state “means for” performing a specified function, or “step for” performing a specific function, is not to be interpreted as a “means” or “step” clause as specified in 35 U.S.C. Section 112, Paragraph 6. In particular, the use of “step of” or “act of” in the Claims herein is not intended to invoke the provisions of 35 U.S.C. 112, Paragraph 6. 
     Please note, if used, the labels left, right, front, back, top, bottom, forward, reverse, clockwise and counter clockwise have been used for convenience purposes only and are not intended to imply any particular fixed direction. Instead, they are used to reflect relative locations and/or directions between various portions of an object. 
       FIG. 3  is simplified diagram illustrating a CML according to an embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. A current mode logic device  300 , as shown in  FIG. 3 , includes a first input  315  (Vin_p) and a second input  316  (Vin_n) for receiving data. For example, the first input  315  and the second  316  are coupled to a pair of data transmission lines. The first input  315  and the second input  316  are respectively coupled to the gates of transistors  307  and  316 . It is to be understood that while MOS devices are shown as transistors, other types of transistor devices may be used as well, such as bipolar junction transistor (BJT) devices uses in early implementation of CMLs, and other types of transistor devices. While operating under similar operating principles, MOS or CMOS devices are preferred over BJT devices for their high speed and low voltage. Each of the transistors  307  and  316  comprises a drain terminal and a source terminal. The drain terminals of the transistors  307  and the  316  respectively provide a first output (Vout_n)  310  and a second output (Vout_p)  308 . The outputs  310  and  308 , as can be seen in  FIG. 3 , are configured in series with resistors and transformers, and thus the output voltages are affected by the characteristics (e.g., resistance and inductance) of the resistors and transformers. The source terminals of the transistors  307  and  316  are grounded via transistors  312  and  313 , which are controlled by the bias voltage  314 . Source resistor  321  and adjustable capacitance  320  are configured in parallel, and are respectively coupled to the source terminals of the transistors  307  and  309 . 
     As shown in  FIG. 3 , output  310  is coupled to resistor  303  and transformer  304  in series; output  308  is coupled to the resistor  306  and transformer  305  in series. Through the resistors and transformers, outputs  310  and  308  are connected to the high potential V DD . Therefore, the voltage swing of the outputs  310  and  308  is a function of the high potential V DD  and the resistors and the transformers. Additionally, voltage swing is affected by the tail current I SS  coupled to the source terminals of the transistors  315  and  316 . The inductances of the transformers  304  and  305  can be adjusted by equalization modules  302  and/or  303 . In  FIG. 3 , the resistors  303  and  306  are directly coupled to the outputs  310  and  308 , and the transformers  304  and  305  are coupled to the outputs via these resistors. It is to be appreciated that, depending on the implementation, the configuration of resistors, transformers, and outputs may be changed. For example, transformer  304  and the resistor  303  may switch their places, where the resistor  303  is directly coupled to the high potential V DD , and transformer  304  is directly coupled to the output  310  and the configured in series with the resistor  303 . There can be other variations as well. 
     Transformers  304  and  305  are characterized by adjustable inductance values. When the inductance values of the transformers  304  and  305  are changed, the voltages of the outputs  310  and  308  change correspondingly. Transformers  304  and  305 , implemented in conjunction with equalizer modules  302  and  301 , allow equalization to be applied to the outputs  310  and  308 . Depending on the specific implementation, one or more equalization modules are used. In  FIG. 3 , transformers  304  and  305  are respectively connected to two different equalizer modules. In a specific implementation, only transformer  304  is connected to the equalizer module  302 , and transformer  305  is not connected to an equalizer module. In another implementation, only transformer  305  is connected to the equalizer module  301 , and transformer  304  is not connected to an equalizer module. It is to be appreciated that other variations as possible as well. 
     Each of the transformers comprises a primary winding and a secondary winding. The equalization modules are coupled to the transformers via the secondary windings of the transformers. For example, the equalizer module  302  is coupled to the secondary winding of the transformer  304 , and the equalizer module  301  is coupled to the secondary winding of the transformer  305 . By changing electrical characteristics (e.g., resistance and/or capacitance) of the equalizer modules, the inductances of the transformers can be changed, which in turn changes the output voltages. For example, the transformers act substantially as an adjustable load that affects the data outputs of the CMLs. 
       FIGS. 4A and 4B  are simplified diagrams illustrating equalizer modules according to embodiments of the present invention. These diagrams merely provide an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. As shown in  FIG. 4A , a bank of resistors is switched by n control bits provided by a DAC module. The DAC module is connected to an equalization logic. For example, the equalization logic can be a DFE or other types of adaptive equalization logic. Based on the signals from the equalization logic, one or more of the resistors are turned on. As shown in  FIG. 4B , a bank of capacitors is switched by n control bits provided by a DAC module. Based on the signals from the equalization logic, one or more of the capacitors are turned on. In certain embodiments, an equalization module may include both capacitors and resistors that are selectively switched by one or more DAC modules. In various implementations, the equalization logic may be adaptive equalizer (e.g., DFE equalizer), linear equalizer, and/or other types of equalizers. As explained above, the equalization modules and transformers described according to embodiments of the present invention allow equalization to be applied at CMLs, and they can be used in conjunction with different equalization systems and methods. 
     In various embodiments, the resistor and capacitor values are predetermined and/or calibrated based on the equalization needs. More specifically, the resistor and capacitor values and the corresponding switching by the DAC is set based on the peaking required for the equalizer. In a specific embodiment, the DAC is 5-bits (e.g., 2 5 =32 steps) and covers a range of 16 dB of peaking, at a step of 0.5 dB. Depending on the implementation, DAC at different resolution may be used. For example, for an equalization scheme that requires fine tuning equalization amount, an 8-bit DAC (i.e., capable of 2 8 =256 steps) may be used; for an equalization scheme that requires small device area and low power consumption, a 3-bit (i.e., capable of 2 3 =8 steps) DAC can be used. 
     In various embodiments according to the present invention, an equalization module utilizes both resistors and capacitors, and the DAC is programmed to selected predetermined combinations of resistor and capacitor. For example, for high-speed boost change, the equalization module switches only capacitors. 
     Now referring back to  FIG. 3 . As shown, equalization modules applies equalization via the secondary windings (i.e., secondary paths) of the transformers, not directly to the outputs or the data path. Consequently, component parasitic and power consumption attributing to the equalization module are minimized. In addition, the transformers  304  and  305  substantially eliminate the need for switched inductors, which are typically expensive in power and area. 
     The source terminals of the transistors  307  and  309  are respectively coupled to transistors  313  and  312  as shown. Transistors  313  and  312  as shown are independently biased by a bias voltage V BIAS , which is electrically coupled to their respective gate terminals. Resistor  321  and the capacitor module  320  are configured in series and electrically coupled to the source terminals of transistors  307  and  309 . Resistor  321  and the capacitor module  320  are associated with the tail currents coming out of the transistors  307  and  309 . The electrical properties of resistor  321  and the capacitor module  320  consequently affect the magnitude of the tail currents, which in turn affect the voltage swing magnitude. The capacitor module  320  provides an adjustable capacitance. For example, the capacitor module  320  is implemented according to  FIG. 4B , where a bank of capacitors is switched by n control bits provided by a DAC module. Based on the signals from the equalization logic, one or more of the capacitors are turned on. By changing the capacitance of the capacitor module  320 , the CML outputs  308  and  310  can be changed as well. In various embodiments, the change of capacitance of the capacitor module  320  is coordinated with equalization module  302  and/or equalization module  301 . For example, selection of capacitors and/or resistors of equalization modules is coordinated against the selection of capacitors at the capacitor module  320 , wherein capacitors and resistors values are predetermined and matched accordingly. By changing both inductance coupled to the outputs and capacitance coupled to the tail currents, the system is capable of adjusting the output voltage levels without causing a shift in frequency. 
     It is to be appreciated that the CMLs according to embodiments of the present invention can provide equalization at specific target peaking frequencies.  FIG. 5  is a simplified diagram illustrating equalization applied to an output data line. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. As shown in graph  501 , by increasing capacitance, peaking is increased, but at the same time the peaking is shifted to a lower frequency. For example, if the original signal is at a capacitance C 3 , by increasing capacitance to C 2 , peaking is increased, and frequency is shifted lower; by further increasing capacitance to C 1 , peaking is further increased, and frequency is further lowered. For example, frequency shift shown in graph  501  may occur when the capacitor module  320  shown in  FIG. 3  is used alone to change the peaking magnitude. 
     Changing inductance also affect both peaking and frequency. As shown in graph  502 , when inductance is increased from L 3  to L 2 , both peaking and frequency are increased, and when inductance is increased to L 1 , both peaking and frequency are further increased. For example, frequency shift shown in graph  502  may occur when equalization modules  301  and/or  302  alone, without adjusting the capacitor module  320 , are used to change the peaking magnitude. 
     For the purpose of applying equalization, frequency shift is undesirable. It is thus to be appreciated that embodiments of the present invention allow equalization to be applied without shifting frequency, as shown in graph  503 . As can be seen in graph  503 , by adjusting both capacitance (through capacitor module coupled to the source terminals of the transistors) and inductance (through transformers coupled to the drain terminals of the transistors), the changes in peaking magnitude can be adjusted without causing frequency shift. For example, when the DAC is at a value of [0], the peaking magnitude is relatively low; however, when DAC is at value [1] or [n], which correspond to different combinations of the capacitors and/or resistors being selected, the corresponding peaking magnitudes are increased, but the peaking frequencies stayed the same. 
       FIG. 6  is a graph illustrating simulation of applying equalization at different settings of an equalization module according to an embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. As can be seen in  FIG. 6 , at different equalization peaking values (e.g., from 0 to about 15 dB), peaking frequencies stay centred. For example, both the capacitor module coupled to the tail current and the equalization module coupled to the output are adjusted to provide equalization without shifting the peaking frequency. 
     While the above is a full description of the specific embodiments, various modifications, alternative constructions and equivalents may be used. Therefore, the above description and illustrations should not be taken as limiting the scope of the present invention which is defined by the appended claims.