Patent Publication Number: US-10778262-B2

Title: Power amplification module

Description:
This application is a continuation of U.S. patent application Ser. No. 15/475,420 filed on Mar. 31, 2017 which claim priority from U.S. patent application Ser. No. 15/138,239 filed on Apr. 26, 2016 which claims priority from Japanese Patent Application No. 2015-093192 filed on Apr. 30, 2015. The contents of these applications are incorporated herein by reference in their entireties. 
    
    
     BACKGROUND 
     Technical Field 
     The present disclosure relates to a power amplification module. 
     A power amplification module is used in a mobile communication device such as a cellular phone in order to amplify the power of a radio frequency (RF) signal to be transmitted to a base station. A bias circuit is used in a power amplification module. The bias circuit is for supplying a bias current to a power amplification transistor. For example, in Japanese Unexamined Patent Application Publication (Translation of PCT Application) No. 2005-501458, there is disclosed a power amplification circuit that uses a bias circuit formed of a cascode current mirror circuit. 
       FIG. 10  illustrates the configuration of the power amplification circuit disclosed in Japanese Unexamined Patent Application Publication (Translation of PCT Application) No. 2005-501458. In the power amplification circuit illustrated in  FIG. 10 , the bias circuit is formed of transistors Q 2  to Q 5  (cascode current mirror circuit). This bias circuit outputs a bias current from the emitter of the transistor Q 3  toward the base of a transistor Q 1  that forms the amplification circuit. 
     Here, the bias current output from the bias circuit changes due to the effect of an RF signal (signal input to base of transistor Q 1 ).  FIG. 11  illustrates an example of the change in the bias current caused by the effect of the RF signal. As illustrated in  FIG. 11 , the bias current changes due to the effect of the RF signal. When the level of the RF signal is large, a negative current (current from base of transistor Q 1  toward emitter of transistor Q 3 ) is generated in the bias current. At this time, although part of the negative current flows to ground via the transistor Q 2 , not all of the negative current flows through the transistor Q 2 . The part of the negative current that does not flow through the transistor Q 2  attempts to flow toward the emitter of the transistor Q 3  but is cut due to the rectifying characteristics of the PN junction between the base and the emitter of the transistor Q 3 . When the negative part of the bias current is cut in this way, the average bias current becomes larger and the gain of the power amplification module increases. In other words, the linearity of the gain in the power amplification module is degraded. 
     This degradation of the linearity of the gain is generated from a smaller RF signal when the size of the current of a current supply Ibias is reduced. Consequently, if an attempt is made to use the power amplification circuit illustrated in  FIG. 10  as a variable gain amplification circuit by using the size of the current of the current source Ibias as a mode signal and causing the bias current of the transistor Q 1  to change in accordance with the mode signal, the degradation of the linearity of the gain is significant when control is performed to reduce the gain. 
     A configuration has also been considered in which cutting of the negative part of the bias current is suppressed by increasing the amount of current that flows to the transistor Q 2 , but this configuration is not preferable since it results in an increase in current consumption. Alternatively, cutting of the negative part of the bias current can also be suppressed by increasing the size of the current of the current source Ibias and increasing the size of the currents of the transistors Q 2  and Q 3 , but there is a problem in that, in addition to the increase in current consumption, control to lower the gain cannot be performed. 
     BRIEF SUMMARY 
     The present disclosure suppresses degradation of the linearity of the gain in a power amplification module. 
     A power amplification module according to an embodiment of the present disclosure includes: a first amplification transistor in which a first signal that is input to a base and a second signal that is obtained by amplifying the first signal are output from a collector; a first resistor; and a first bias circuit that supplies a first bias current to the base of the first amplification transistor via the first resistor. The first bias circuit includes: a first bipolar transistor in which a base and a collector are connected to each other and a bias control current that is supplied to the collector a second bipolar transistor in which a base and a collector are connected to each other and the collector is connected to an emitter of the first bipolar transistor: a third bipolar transistor in which a base is connected to the base of the first bipolar transistor, an emitter is connected to one end of the first resistor, and the first bias current is output from the emitter; a fourth bipolar transistor in which a collector is connected to the emitter of the third bipolar transistor and a base is connected to the base of the second bipolar transistor; and a first capacitor that is provided between the base and the emitter of the third bipolar transistor. 
     According to the embodiment of the present disclosure, degradation of the linearity of gain in a power amplification module can be suppressed. 
     Other features, elements, characteristics and advantages of the present disclosure will become more apparent from the following detailed description of embodiments of the present disclosure with reference to the attached drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
         FIG. 1  illustrates an example configuration of a transmission unit that includes a power amplification module according to an embodiment of the present disclosure; 
         FIG. 2  illustrates an example configuration of the power amplification module; 
         FIG. 3  illustrates example configurations of an amplification circuit and a bias circuit; 
         FIG. 4  illustrates example configurations of an amplification circuit and a bias circuit; 
         FIG. 5  illustrates another example configuration of the bias circuit; 
         FIG. 6  illustrates another example configuration of the bias circuit; 
         FIG. 7  illustrates another example configuration of the bias circuit; 
         FIG. 8  illustrates another example configuration of the bias circuit; 
         FIG. 9  illustrates another example configuration of the bias circuit; 
         FIG. 10  illustrates an example of a power amplification circuit that employs a bias circuit formed of a cascode current mirror circuit; and 
         FIG. 11  illustrates an example of a change in a bias current caused by the effect of an RF signal. 
     
    
    
     DETAILED DESCRIPTION 
     Hereafter, an embodiment of the present disclosure will be described while referring to the drawings.  FIG. 1  illustrates an example configuration of a transmission unit that includes a power amplification module according to an embodiment of the present disclosure. A transmission unit  100  is for example used in a mobile communication device such as a cellular phone in order to transmit various signals such as speech and data to a base station. Although such a mobile communication device would also be equipped with a reception unit for receiving signals from the base station, the description of such a reception unit is omitted here. 
     As illustrated in  FIG. 1 , the transmission unit  100  includes a base band unit  110 , an RF unit  111 , a power amplification module  112 , a front end unit  113  and an antenna  114 . 
     The base band unit  110  modulates an input signal such as speech or data on the basis of a modulation scheme such as HSUPA or LTE and outputs a modulated signal. In this embodiment, the modulated signal output from the base band unit  110  is output as IQ signals (I signal and Q signal) in which the amplitude and the phase are represented on an IQ plane. The frequencies of the IQ signals are on the order of several MHz to several tens of MHz, for example. In addition, the base band unit  110  outputs a mode signal MODE that is for controlling the gain in the power amplification module  112 . 
     The RF unit  111  generates an RF signal (RF IN ), which is for performing wireless transmission, from the IQ signals output from the base band unit  110 . The RF signal has a frequency of around several hundred MHz to several GHz, for example. In the RF unit  111 , the IQ signals may be converted into an intermediate frequency (IF) signal and an RF signal may be then generated from the IF signal, instead of directly converting the IQ signals into the RF signal. 
     The power amplification module  112  amplifies the power of the RF signal (RF IN ) output from the RF unit  111  up to the level that is required to transmit the RF signal to the base station, and outputs the amplified signal (RF OUT ). In the power amplification module  112 , the size of a bias current is determined on the basis of the mode signal MODE supplied from the base band unit  110  and the gain is controlled. 
     The front end unit  113  performs filtering on the amplified signal (RF OUT ) and switching on a reception signal received from the base station. The amplified signal output from the front end unit  113  is transmitted to the base station via the antenna  114 . 
       FIG. 2  illustrates an example configuration of the power amplification module  112 . As illustrated in  FIG. 2 , the power amplification module  112  includes amplification circuits  200  and  201 , bias circuits  210  and  211 , matching networks (MN)  220 ,  221  and  222 , inductors  230  and  231 , resistors  240  and  241  and a bias control circuit  250 . 
     The amplification circuits  200  and  201  form a two-stage amplification circuit. The amplification circuit  200  amplifies an RF signal (RF IN1 ) (first signal) and outputs an amplified signal (RF OUT1 ) (second signal). The amplified signal (RF OUT2 ) output from the amplification circuit  200  is input to the amplification circuit  201  via the matching network  221  as an RF signal (RF IN2 ). The amplification circuit  201  amplifies the RF signal (RF IN2 ) and outputs an amplified signal (RF OUT2 ) (third signal). The number of stages of the amplification circuit is not limited to two and may be one or three or more. 
     The bias circuits  210  and  211  supply bias currents to the amplification circuits  200  and  201 , respectively. The bias circuit  210  (first bias circuit) supplies a bias current I BIAS1  (first bias current) that corresponds to a bias control current I CONT1  (first bias control current) output from the bias control circuit  250  to the amplification circuit  200 . In addition, the bias circuit  211  (second bias circuit) supplies a bias current I BIAS2  (second bias current) that corresponds to a bias control current I CONT2  (second bias control current) output from the bias control circuit  250  to the amplification circuit  201 . 
     The matching networks  220 ,  221  and  222  are provided in order to match the impedances between the circuits. The matching networks  220 ,  221  and  222  are formed using inductors and capacitors, for example. 
     The inductors  230  and  231  are provided in order to isolate the RF signal. A power supply voltage V CC  is supplied to the amplification circuits  200  and  201  via the inductors  230  and  231 , respectively. 
     The bias control circuit  250  outputs the bias control currents I CONT1  and I CONT2 , which are for controlling the bias currents I BIAS1  and I BIAS2 , on the basis of the mode signal MODE. The bias control current I CONT1  is supplied to the bias circuit  210  via the resistor  240  (fourth resistor). In addition, the bias control current I CONT2  is supplied to the bias circuit  211  via the resistor  241 . By providing the power amplification module  112  with the resistors  240  and  241 , changes in the impedances of the bias circuits  210  and  211  seen from the bias control circuit  250  can be suppressed. In the power amplification module  112 , the gain is controlled by controlling the bias currents I BIAS1  and I BIAS2 . The bias control circuit  250  may be provided outside of the power amplification module  112 . In addition, the power amplification module  112  does not need to include the resistors  240  and  241 . 
       FIG. 3  illustrates example configurations of the amplification circuit  200  and the bias circuit  210 . 
     The amplification circuit  200  includes a transistor  300 A (first amplification transistor), a capacitor  301 A and a resistor  302 A (first resistor). The transistor  300 A is a heterojunction bipolar transistor (HBT), for example. The RF signal (RF IN1 ) is input to the base of the transistor  300 A via the capacitor  301 A. The power supply voltage V CC  is supplied to the collector of the transistor  300 A via the inductor  230 . The emitter of the transistor  300 A is grounded. In addition, the bias current I BIAS1  is supplied to the base of the transistor  300 A via the resistor  302 A. An amplified signal (RF OUT1 ) is output from the collector of the transistor  300 A. 
     A bias circuit  210 A includes transistors  310 A,  311 A,  312 A and  313 A and a capacitor  320 . The transistors  310 A to  313 A are HBTs, for example. The transistor  310 A (first bipolar transistor) is diode-connected and the bias control current I CONT1  is supplied to the collector thereof. The transistor  311 A (second bipolar transistor) is diode-connected, the collector thereof is connected to the emitter of the transistor  310 A and the emitter thereof is grounded. A power supply voltage (for example, battery voltage V BAT ) is supplied to the collector of the transistor  312 A (third bipolar transistor) and the base of the transistor  312 A is connected to the base of the transistor  310 A. The collector of the transistor  313 A (fourth bipolar transistor) is connected to the emitter of the transistor  312 A, the base of the transistor  313 A is connected to the base of the transistor  311 A, and the emitter of the transistor  313 A is grounded. One end of the capacitor  320  (first capacitor) is connected to the base of the transistor  312 A and the other end of the capacitor  320  is connected to the emitter of the transistor  312 A. 
     Operation of the bias circuit  210 A will be described. In the bias circuit  210 A, the bias current I BIAS1 , which corresponds to the bias control current I CONT1 , is output from the emitter of the transistor  312 A. Here, the bias current I BIAS1  undergoes amplitude fluctuations due to the effect of the RF signal (RF IN1 ). When the level of the RF signal (RF IN1 ) increases, the amplitude of the bias current I BIAS1  also increases. When the amplitude of the bias current I BIAS1  increases and a negative current is generated (current from amplification circuit  200  toward emitter of the transistor  312 A), part of this negative current flows from the emitter of the transistor  312 A into the base of the transistor  310 A via the capacitor  320 . In addition, part of this negative current also flows into the transistor  313 A. 
     Thus, current paths (capacitor  320  and transistor  313 A) for bypassing the negative current are provided in the bias circuit  210 A, and as a result, the bias current I BIAS1  is able to become negative along with the change in the RF signal (RF IN1 ). Therefore, since the negative part of the bias current I BIAS1  is not cut in the bias circuit  210 A, an increase in the average bias current in the case where the level of the RF signal (RF IN1 ) increases can be suppressed. Thus, degradation of the linearity of the gain in the power amplification module  112  can be suppressed. 
       FIG. 4  illustrates example configurations of the amplification circuit  201  and the bias circuit  211 . Constituent elements that are the same as those of the amplification circuit  200  and the bias circuit  210 A illustrated in  FIG. 3  are denoted by the same symbols and detailed description thereof is omitted. 
     The amplification circuit  201  includes a transistor  300 B (second amplification transistor), a capacitor  301 B and a resistor  302 B. The configuration of the inside of the amplification circuit  201  is the same as that of the inside of the amplification circuit  200  and therefore detailed description thereof is omitted. 
     The bias circuit  211  includes transistors  310 B,  311 B and  312 B. The transistor  310 B (fifth bipolar transistor) is diode-connected and the bias control current I CONT2  is supplied to the collector thereof. The transistor  311 B (sixth bipolar transistor) is diode-connected, the collector thereof is connected to the emitter of the transistor  310 B and the emitter thereof is grounded. A power supply voltage (for example, battery voltage V BAT ) is supplied to the collector of the transistor  312 B (seventh bipolar transistor) and the base of the transistor  312 B is connected to the base of the transistor  310 B. 
     Operation of the bias circuit  211  will be described. The bias circuit  211  does not include the current paths (capacitor  320  and transistor  313 A) that are for bypassing the negative current in the bias circuit  210 A. Therefore, in the bias circuit  211 , when level of the RF signal (RF IN2 ) increases, the negative part of the bias current I BIAS2  may be cut. Consequently, in the bias circuit  211 , the average bias current may increase when the level of the RF signal (RF IN2 ) increases. When the average bias current increases, the gain of the amplification circuit  201  increases. 
     Since an increase in the gain of the amplification circuit  201  is linked to a decrease in the linearity of the power amplification module  112 , a configuration the same as the bias circuit  210 A could also be considered for the bias circuit  211 . However, if current paths for bypassing the negative current are provided as in the bias circuit  210 A, it is possible that the maximum power of the amplification circuit  201  will be decreased. Therefore, in the power amplification module  112 , a configuration that does not include current paths for bypassing a negative current is adopted for the bias circuit  211 , which supplies the bias current I BIAS2  to the second-stage amplification circuit  201  that requires a higher power. 
     However, the bias circuit  211  may have the same configuration as the bias circuit  210 A. Furthermore, the bias circuit  211  may have the same configuration as any of bias circuits  210 B to  210 F described below. 
       FIG. 5  illustrates another example configuration of the bias circuit  210 . Constituent elements that are the same as those of the bias circuit  210 A illustrated in  FIG. 3  are denoted by the same symbols and description thereof is omitted. 
     A bias circuit  210 B includes a resistor  500  (second resistor) in addition to the configuration of the bias circuit  210 A. One end of the capacitor  320  is connected to the emitter of the transistor  312 A and the other end of the capacitor  320  is connected to one end of the resistor  500 . The other end of the resistor  500  is connected to the base of the transistor  312 A. 
     In the bias circuit  210 B, similarly to as in the bias circuit  210 A, when the amplitude of the bias current I BIAS1  increases and a negative current is generated, part of this negative current flows from the emitter of the transistor  312 A and is bypassed to the transistor  310 A via the capacitor  320  and the resistor  500 . Thus, an increase in the average bias current can be suppressed and an increase in the gain of the amplification circuit  200  can be suppressed. Then, by adjusting the resistance value of the resistor  500  in the bias circuit  210 B, the amount of current bypassed to the transistor  310 A can be adjusted. 
       FIG. 6  illustrates another example configuration of the bias circuit  210 . Constituent elements that are the same as those of the bias circuit  210 A illustrated in  FIG. 3  are denoted by the same symbols and description thereof is omitted. 
     A bias circuit  210 C includes a resistor  600  (third resistor) in addition to the configuration of the bias circuit  210 A. One end of the resistor  600  is connected to the base of the transistor  311 A and the other end of the resistor  600  is connected to the base of the transistor  313 A. 
     In the bias circuit  210 C, similarly to as in the bias circuit  210 A, when the amplitude of the bias current I BIAS1  increases and a negative current is generated, part of the negative current is bypassed to the transistor  313 A. Thus, an increase in the average bias current can be suppressed and an increase in the gain of the amplification circuit  200  can be suppressed. Then, by adjusting the resistance value of the resistor  600  in the bias circuit  210 C, the amount of current bypassed to the transistor  313 A can be adjusted. The bias circuit  210 B illustrated in  FIG. 5  may also be provided with the resistor  600 . Furthermore, bias circuits  210 D to  210 F described below may also be provided with the resistor  600 . 
       FIG. 7  illustrates another example configuration of the bias circuit  210 . Constituent elements that are the same as those of the bias circuit  210 A illustrated in  FIG. 3  are denoted by the same symbols and description thereof is omitted. 
     A bias circuit  210 D includes a capacitor  700  (second capacitor) in addition to the configuration of the bias circuit  210 A. One end of the capacitor  700  is connected to the base of the transistor  312 A and the other end of the capacitor  700  is connected to the emitter of the transistor  313 A. 
     In the bias circuit  210 D, similarly to as in the bias circuit  210 A, when the amplitude of the bias current I BIAS1  increases and a negative current is generated, part of the negative current is bypassed to the transistor  310 A. Thus, an increase in the average bias current can be suppressed and an increase in the gain of the amplification circuit  200  can be suppressed. The amount of current bypassed to the transistor  310 A can be adjusted by providing the capacitor  700  in the bias circuit  210 D. 
     In addition, in the bias circuit  210 D, the effect of variations in the capacitance value of the capacitor  320  can be suppressed by the capacitor  700 . For example, if there were no capacitor  700 , the size of the bypassed current would vary when the capacitance value of the capacitor  320  varies. In the bias circuit  210 D, when the capacitance value of the capacitor  320  increases due to variations, the capacitance value of the capacitor  700  will also similarly increase and therefore fluctuations in the size of the bypassed current are suppressed. 
     The bias circuits  210 B and  210 C illustrated in  FIGS. 5 and 6  may also be provided with the capacitor  700 . In addition, the bias circuits  210 E and  210 F described below may also be provided with the capacitor  700 . 
       FIG. 8  illustrates another example configuration of the bias circuit  210 . Constituent elements that are the same as those of the bias circuit  210 A illustrated in  FIG. 3  are denoted by the same symbols and description thereof is omitted. 
     A bias circuit  210 E includes a field effect transistor (FET)  800  (first FET) in addition to the configuration of the bias circuit  210 A. One end of the capacitor  320  is connected to the emitter of the transistor  312 A and the other end of the capacitor  320  is connected to the source of the FET  800 . The drain of the FET  800  is connected to the base of the transistor  312 A and a control voltage V CONT  (connection control signal) is supplied to the gate of the FET  800 . 
     In the bias circuit  210 E, the electrical connection of the capacitor  320  between the base and the emitter of the transistor  312 A is controlled by the control voltage V CONT  output from the bias control circuit  250 . 
     Specifically, for example, in the case where the power of the RF signal (RF IN1 ) is comparatively low, the FET  800  is turned on, and, consequently, part of the negative current of the bias current I BIAS1  is bypassed to the transistor  310 A and an increase in the gain of the amplification circuit  200  can be suppressed, similarly to as in the bias circuit  210 A. 
     Furthermore, for example, in the case where the power of the RF signal (RF IN1 ) is comparatively high, the FET  800  is turned off, and consequently the bypass to the transistor  310 A is halted and a reduction in the maximum power of the amplification circuit  200  can be suppressed. The size of the current for the FET  800  may be controlled in a step-wise manner in accordance with the level of the control voltage V CONT  rather than with an on/off binary operation. 
     The bias circuits  210 B to  210 D illustrated in  FIGS. 5 to 7  may also be provided with the FET  800 . In addition, a bias circuit  210 F described below may also be provided with the FET  800 . 
       FIG. 9  illustrates another example configuration of the bias circuit  210 . Constituent elements that are the same as those of the bias circuit  210 A illustrated in  FIG. 3  are denoted by the same symbols and description thereof is omitted. 
     A bias circuit  210 F includes FETs  900  and  901  instead of the transistors  310 A and  312 A of the bias circuit  210 A. The FET  900  (second FET) is diode-connected and the bias control current I CONT1  is supplied to the drain thereof. The collector of the transistor  311 A is connected to the source of the FET  900 . A power supply voltage (for example, battery voltage V BAT ) is supplied to the drain of the FET  901  (third FET) and the gate of the FET  901  is connected to the gate of the FET  900 . The collector of the transistor  313 A is connected to the source of the FET  901 . One end of the capacitor  320  is connected to the gate of the FET  901  and the other end of the capacitor  320  is connected to the source of the FET  901 . 
     In the bias circuit  210 F, the FETs  900  and  901  operate similarly to the transistors  310 A and  312 A of the bias circuit  210 A. In other words, the bias current I BIAS1  is output from the source of the FET  901 . In the bias circuit  210 F, similarly to as in the bias circuit  210 A, when the amplitude of the bias current I BIAS1  increases and a negative current is generated, part of the negative current is bypassed to the FET  900  via the capacitor  320 . Thus, an increase in the average bias current can be suppressed and an increase in the gain of the amplification circuit  200  can be suppressed. In the bias circuit  210 F, since the FETs  900  and  901  are used, lower voltage operation is possible compared with the case where the transistors  310 A and  312 A are used. The bias circuits  210 B to  210 E illustrated in  FIGS. 5 to 8  may also be provided with the FETs  900  and  901  instead of the transistors  310 A and  312 A. 
     Exemplary embodiments of the present disclosure have been described above. In the power amplification module  112 , by providing a current path for bypassing a negative current of the bias current I BIAS1  in the bias circuit  210 , the bias current I BIAS1  is able to become negative along with a change in the RF signal (RF IN1 ). Therefore, since the negative part of the bias current I BIAS1  is not cut in the bias circuit  210 , an increase in the average bias current in the case where the level of the RF signal (RF IN1 ) increases can be suppressed. Thus, degradation of the linearity of the gain in the power amplification module  112  can be suppressed. 
     Furthermore, in the power amplification module  112 , by providing the resistor  500  that is connected in series with the capacitor  320  as in the bias circuit  210 B illustrated in  FIG. 5 , the amount of current bypassed to the transistor  310 A can be adjusted. 
     In addition, in the power amplification module  112 , by providing the resistor  600  between the bases of the transistors  311  and  313  as in the bias circuit  210 C illustrated in  FIG. 6 , the amount of current bypassed to the transistor  313 A can be adjusted. 
     Furthermore, in the power amplification module  112 , by providing the capacitor  700  between the base of the transistor  312 A and the emitter of the transistor  313 A as in the bias circuit  210 D illustrated in  FIG. 7 , the amount of current bypassed to the transistor  310 A can be adjusted. In addition, the effect of variations in the capacitance value of the capacitor  320  can be canceled out by the capacitor  700 . 
     In addition, the power amplification module  112  can be provided with the FET  800  that controls the electrical connection of the capacitor  320  between the base and the emitter of the transistor  312 A, as in the bias circuit  210 E illustrated in  FIG. 8 . As a result, for example, in the case where the power of the RF signal (RF IN1 ) is comparatively high, the FET  800  is turned off, and consequently the bypass to the transistor  310 A is halted and a reduction in the maximum power of the amplification circuit  200  can be suppressed. 
     In addition, by providing the power amplification module  112  with the FETs  900  and  901  instead of the transistors  310 A and  312 A as in the bias circuit  210 F illustrated in  FIG. 9 , low voltage operation can be realized. 
     Furthermore, by providing the power amplification module  112  with the resistors  240  and  241 , as illustrated in  FIG. 2 , changes in the impedances of the bias circuits  210  and  211  seen from the bias control circuit  250  can be suppressed. 
     In addition, in the power amplification module  112 , for the bias circuit  211  that supplies the bias current I BIAS2  to the subsequent amplification circuit  201 , a configuration can be adopted that does not include a current path for bypassing the negative current of the bias current I BIAS2 , as illustrated in  FIG. 4 . In this way, a reduction in the maximum power in the subsequent power amplification circuit  201 , which requires a higher power, can be suppressed. In a power amplification module equipped with a power amplification circuit of three or more stages as well, the bias circuit that supplies a bias current to the final stage amplification circuit can have a configuration that does not include a current path for bypassing a negative current. 
     The embodiments described above are for enabling easy understanding of the present disclosure and the embodiments are not to be interpreted as limiting the present disclosure. The present disclosure can be modified or improved without departing from the gist of the disclosure and equivalents to the present disclosure are also included in the present disclosure. In other words, appropriate design modifications made to the embodiments by one skilled in the art are included in the scope of the present disclosure so long as the modifications have the characteristics of the present disclosure. For example, the elements included in the embodiments and the arrangements, materials, conditions, shapes, sizes and so forth of the elements are not limited to those exemplified in the embodiments and can be appropriately changed. In addition, the elements included in the embodiments can be combined as much as technically possible and such combined elements are also included in the scope of the present disclosure so long as the combined elements have the characteristics of the present disclosure. 
     While embodiments of the disclosure have been described above, it is to be understood that variations and modifications will be apparent to those skilled in the art without departing from the scope and spirit of the disclosure. The scope of the disclosure, therefore, is to be determined solely by the following claims.