Patent Publication Number: US-2023144373-A1

Title: Pixel array and devices including the same

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2021-0154253 filed on Nov. 10, 2021, and Korean Patent Application No. 10-2022-0101597 filed on Aug. 12, 2022, in the Korean Intellectual Property Office, the disclosures of which are incorporated by reference herein in their entireties. 
     BACKGROUND 
     The present disclosure relates to a pixel array, and more particularly, relate to a pixel array including a pixel including three transistors connected in series between a voltage supply line and a floating diffusion region to adjust a conversion gain and devices including the same. 
     In general, an image sensor converts an optical image into an electrical signal. With the development of the computer industry and the communication industry, the demand on image sensors with improved performance in various fields is increasing. An image sensor is classified as a charge coupled device (CCD) image sensor or a complementary metal-oxide-semiconductor (CMOS) image sensor. 
     The CMOS image sensor is easy to drive and makes it possible to miniaturize the product because a signal processing circuit is capable of being integrated into a single chip. Because the power consumption of the CMOS image sensor is very little, it is easy to apply the CMOS image sensor to products with the limited battery capacity. In addition, because the CMOS image sensor is capable of being manufactured by using the CMOS process technology, the costs for manufacturing may be reduced. Accordingly, the use of the CMOS image sensor is rapidly increasing as the high resolution is implemented together with the technology development. 
     The CMOS image sensor is implemented with a single chip where a pixel array including pixels each generating an analog pixel signal and a readout circuit for reading the analog pixel signal are coupled. The analog pixel signal generated by the pixel is converted into a digital pixel signal through an analog-to-digital converter included in the readout circuit and is then read out. The specification of the readout circuit is determined depending on how quickly an analog pixel signal is converted into a digital pixel signal without loss in the analog-to-digital conversion process and how quickly it is read out. 
     SUMMARY 
     Provided are an image sensor capable of performing a triple-conversion gain mode to optimize a dynamic range, a signal-to-noise ratio (SNR), and a noise, and an imaging device including the same. 
     According to an aspect of an example embodiment, a pixel array includes: pixels arranged in a matrix shape and separated from each other by front deep trench isolation (FDTI), each of the pixels having a same structure, wherein a first pixel among the pixels includes: a first floating diffusion region; a first group of photoelectric conversion elements that are separated from each other by the FDTI; a first group of charge transfer transistors respectively including vertical transfer gates, the first group of charge transfer transistors being configured to transfer photo-generated charges generated by the first group of photoelectric conversion elements to the first floating diffusion region; a first source follower transistor including a first gate connected with the first floating diffusion region; and a first transistor, a second transistor, and a first reset transistor connected in series, between the first floating diffusion region and a voltage supply line supplying a pixel power supply voltage, to adjust a first conversion gain of the first source follower transistor, wherein a first one of the first transistor, the second transistor, and the first reset transistor is provided in a first sub-pixel region of the first pixel together with a first photoelectric conversion element among the first group of photoelectric conversion elements, wherein a second one of the first transistor, the second transistor, and the first reset transistor, other than the first one of the first transistor, the second transistor, and the first reset transistor, is provided in a second sub-pixel region of the first pixel together with a second photoelectric conversion element among the first group of photoelectric conversion elements, and wherein the first sub-pixel region and the second sub-pixel region are separated from each other by the FDTI. 
     According to an aspect of an example embodiment, an image sensor includes: a pixel array including pixels arranged in a matrix shape and separated from each other front deep trench isolation (FDTI), each of the pixels having a same structure; and an analog-to-digital converter configured to convert an analog pixel signal output from the pixel array into a digital signal, wherein a first pixel among the pixels includes: a first floating diffusion region; a first group of photoelectric conversion elements that are separated from each other by the FDTI; a first group of charge transfer transistors respectively including vertical transfer gates, the first group of charge transfer transistors being configured to transfer photo-generated charges generated by the first group of photoelectric conversion elements to the first floating diffusion region; a first source follower transistor including a first gate connected with the first floating diffusion region; and a first transistor, a second transistor, and a first reset transistor connected in series between the first floating diffusion region and a voltage supply line supplying a pixel power supply voltage, to adjust a first conversion gain of the first source follower transistor, wherein a first one of the first transistor, the second transistor, and the first reset transistor is provided in a first sub-pixel region of the first pixel together with a first photoelectric conversion element among the first group of photoelectric conversion elements, wherein a second one of the first transistor, the second transistor, and the first reset transistor, other than the first one of the first transistor, the second transistor, and the first reset transistor, is provided in a second sub-pixel region of the first pixel together with a second photoelectric conversion element among the first group of photoelectric conversion elements, and wherein the first sub-pixel region and the second sub-pixel region are separated from each other by the FDTI. 
     According to an aspect of an example embodiment, an image processing device includes: an image sensor; and a processor configured to control an operation of the image sensor, wherein the image sensor includes: a pixel array including pixels arranged in a matrix shape and separated from each other front deep trench isolation (FDTI), each of the pixels having a same structure; and an analog-to-digital converter configured to convert an analog pixel signal output from the pixel array into a digital signal, wherein a first pixel among the pixels includes: a first floating diffusion region; a first group of photoelectric conversion elements that are separated from each other by the FDTI; a first group of charge transfer transistors respectively including vertical transfer gates, the first group of charge transfer transistors being configured to transfer photo-generated charges generated by the first group of photoelectric conversion elements to the first floating diffusion region; a first source follower transistor including a first gate connected with the first floating diffusion region; and a first transistor, a second transistor, and a first reset transistor connected in series between the first floating diffusion region and a voltage supply line supplying a pixel power supply voltage, to adjust a first conversion gain of the first source follower transistor, wherein a first one of the first transistor, the second transistor, and the first reset transistor is provided in a first sub-pixel region of the first pixel together with a first photoelectric conversion element among the first group of photoelectric conversion elements, wherein a second one of the first transistor, the second transistor, and the first reset transistor, other than the first one of the first transistor, the second transistor, and the first reset transistor, is provided in a second sub-pixel region of the first pixel together with a second photoelectric conversion element among the first group of photoelectric conversion elements, and wherein the first sub-pixel region and the second sub-pixel region are separated from each other by the FDTI. 
    
    
     
       BRIEF DESCRIPTION OF THE FIGURES 
       The above and other aspects and features of the present disclosure will become apparent by describing in detail embodiments thereof with reference to the accompanying drawings, in which: 
         FIG.  1    is a block diagram of an image sensor including a pixel array according to an embodiment of the present disclosure; 
         FIG.  2    is a circuit diagram of a first pixel and a second pixel of  FIG.  1   , which are connected through two connection lines; 
         FIG.  3 A  is a cross-sectional view of a sub-pixel region having an FDTI structure according to an embodiment of the present disclosure and including a transistor, a photoelectric conversion element, a vertical transfer gate, and a floating diffusion region; 
         FIG.  3 B  is a plan view of a sub-pixel region corresponding to the cross-sectional view illustrated in  FIG.  3 A ; 
         FIG.  4 A  is a plan view of a first pixel and a second pixel, each of which includes four photoelectric conversion elements; 
         FIG.  4 B  is a circuit diagram illustrating an embodiment of a second source follower transistor included in a second pixel of  FIG.  2   ; 
         FIG.  5 A  is a plan view of a first pixel and a second pixel, each of which includes eight photoelectric conversion elements; 
         FIG.  5 B  is a circuit diagram illustrating an embodiment of a first source follower transistor included in a first pixel of  FIG.  2   ; 
         FIG.  6 A  is a plan view of a first pixel and a second pixel, each of which includes 16 photoelectric conversion elements; 
         FIG.  6 B  is a circuit diagram illustrating an embodiment of a second transistor included in a first pixel of  FIG.  2   ; 
         FIG.  6 C  is a circuit diagram illustrating an embodiment of a second source follower transistor included in a second pixel of  FIG.  2   ; 
         FIG.  7    is a timing diagram of control signals supplied to a first pixel and a second pixel of  FIG.  2    when an image sensor of  FIG.  1    operates in a high conversion gain mode; 
         FIG.  8    is a timing diagram of control signals supplied to a first pixel and a second pixel of  FIG.  2    when an image sensor of  FIG.  1    operates in a medium conversion mode; 
         FIG.  9    is the timing diagram of control signals supplied to a first pixel and a second pixel of  FIG.  2    when an image sensor of  FIG.  1    operates in a low conversion gain mode; 
         FIG.  10    is a block diagram illustrating an implementation example of an image sensor illustrated in  FIG.  1   ; and 
         FIG.  11    is a block diagram of an image processing device including an image sensor illustrated in  FIG.  1   . 
     
    
    
     DETAILED DESCRIPTION 
     The front deep trench isolation or frontside deep trench isolation (FDTI) is a DTI that is formed from a first surface, on/in which transistors are formed, toward a second surface opposite to the first surface in the process of manufacturing an image sensor, as illustrated in  FIG.  3 A , for the purpose of isolating pixels. 
     An FDTI region (also called a “FDTI structure”) is a region (also called a “structure”) that is vertically expanded (or formed) from a first surface of a semiconductor substrate (e.g., an epitaxial layer) toward a second surface opposite to the first surface. Herein, the FDTI region or the FDTI material is simply referred to as “FDTI”. 
       FIG.  1    is a block diagram of an image sensor including a pixel array according to an embodiment of the present disclosure. Referring to  FIG.  1   , an image sensor  100  includes a pixel array  110 , a readout circuit  120 , and a control signal generator  150 . 
     The image sensor  100  may be a complementary metal-oxide-semiconductor (CMOS) image sensor and may be also called a solid-state imaging device. 
     The pixel array (also called an active pixel sensor (APS) array)  110  includes a plurality of pixels PIXEL arranged in the shape of a matrix with dimension m×n. The plurality of pixels PIXEL have the same structure and are isolated from each other by the FDTI. The plurality of pixels PIXEL perform photoelectric conversion and output pixel signals (or analog pixel signals) PIX 1  to PIXn depending on the photoelectric conversion to the readout circuit  120 . d 
     The readout circuit (also called an analog-to-digital converter)  120  includes a ramp signal generator  130 , a plurality of comparators  140 _ 1  to  140 _ n , and a plurality of correlated double sampling (CDS) circuits  145 _ 1  to  145 _ n.    
     The ramp signal generator  130  generates a ramp signal RAMP. For example, the ramp signal generator  130  may be a digital-to-analog converter. 
     The ramp signal RAMP is applied to the comparators  140 _ 1  to  140 _ n , and the comparators  140 _ 1  to  140 _ n  receive the pixel signals PIX 1  to PIXn transferred through pixel lines (or output lines) COL 1  to COLn, compare the pixel signals PIX 1  to PIXn with the ramp signal RAMP, and output comparison signals CDS_DCS 1  to CDS_DCSn depending on comparison results. 
     The comparators  140 _ 1  to  140 _ n  compare reset signals (or reset components) and light-sensed signals (or signal components) included in the pixel signals PIX 1  to PIXn with the ramp signal RAMP and output the comparison signals CDS_DCS 1  to CDS_DCSn depending on the comparison results. 
     According to an embodiment, the ramp signal RAMP is input to a first input terminal (e.g., an inverting input terminal) of each of the comparators  140 _ 1  to  140 _ n  and each of the pixel signals PIX 1  to PIXn is input to a second input terminal (e.g., a non-inverting input terminal) of each of the comparators  140 _ 1  to  140 _ n.    
     According to embodiments, the ramp signal RAMP may be input to the second input terminal of each of the comparators  140 _ 1  to  140 _ n , and each of the pixel signals PIX 1  to PIXn may be input to the first input terminal of each of the comparators  140 _ 1  to  140 _ n.    
     The CDS circuits  145 _ 1  to  145 _ n  count times that are taken for the comparison signals CDS_DCS 1  to CDS_DCSn to transition from the first state to the second state and may output count values. Herein, the first state may be one of a low level and a high level, and the second state may be the other of the low level and the high level. 
     The control signal generator  150  may generate control signals TG 1 , TG 2 , SEL 1 , SEL 2 , RG 1 , DCG 1 _ 1 , DCG 1 _ 2 , RG 2 , DCG 2 _ 1 , and DCG 2 _ 2  to be described with reference to  FIGS.  7  and  9    depending on a mode control signal MODE_ctl and may output the control signals to each pixel “PIXEL” included in the pixel array  110 . 
     For convenience of description, the control signals TG 1 , TG 2 , SEL 1 , SEL 2 , RG 1 , DCG 1 _ 1 , DCG 1 _ 2 , RG 2 , DCG 2 _ 1 , and DCG 2 _ 2  for controlling a first pixel  112  and a second pixel  113  are illustrated in  FIG.  1    as an example. 
       FIG.  2    is a circuit diagram of a first pixel and a second pixel of  FIG.  1   , which are connected through two connection lines. Referring to  FIGS.  1  and  2   , the image sensor  100  includes the first pixel  112  and the second pixel  113 . For convenience of description, dummy transistors are not illustrated in  FIG.  2   . 
     As the first pixel  112  is formed (or manufactured) by using the FDTI process, three transistors (i.e., a first transistor TR 1 _ 1 , a second transistor TR 1 _ 2 , and a first reset transistor RT 1 ) that are connected in series are connected between a first floating diffusion node ND 1 _ 1  and a first voltage node NP 1 . The first floating diffusion node ND 1 _ 1  is connected with a first floating diffusion region FD 1   a , and the first voltage node NP 1  is connected with a voltage supply line PWL supplying a pixel power supply voltage VPIX. A node is formed by using at least one metal contact. 
     To adjust a first conversion gain of a first source follower transistor SF 1 , the first pixel  112  includes the three transistors TR 1 _ 1 , TR 1 _ 2 , and RT 1  connected in series between the first floating diffusion node ND 1 _ 1  and the first voltage node NP 1 . 
     The first transistor TR 1 _ 1  is connected between a first connection node ND 1 _ 2  and the first floating diffusion node ND 1 _ 1 , and a first conversion gain control signal DCG 1 _ 1  is supplied to a gate G 11  of the first transistor TR 1 _ 1 . A gate is also called a gate electrode. The first connection node ND 1 _ 2  is connected with a second floating diffusion region FD 1   b.    
     The second transistor TR 1 _ 2  is connected between the first connection node ND 1 _ 2  and a second connection node ND 1 _ 3 , and a second conversion gain control signal DCG 1 _ 2  is supplied to a gate G 12  of the second transistor TR 1 _ 2 . The second connection node ND 1 _ 3  is connected with a third floating diffusion region FD 1   c.    
     The first reset transistor RT 1  is connected between the first voltage node NP 1  and the second connection node ND 1 _ 3 , and a first reset signal RG 1  is supplied to a gate G 13  of the first reset transistor RT 1 . 
     The first pixel  112  further includes a first group of charge transfer transistors TT 1 _ 1  to TT 1 _ k  (k being a natural number of 2 or more), the first source follower transistor SF 1 , and a first select transistor ST 1 . 
     The charge transfer transistors TT 1 _ 1  to TT 1 _ k  of the first group may transfer photo-generated charges generated by a first group of photoelectric conversion elements PD 1 _ 1  to PD 1 _ k  to the first floating diffusion region FD 1   a , and the photoelectric conversion elements PD 1 _ 1  to PD 1 _ k  of the first group are separated from each other by the FDTI. 
     The charge transfer transistors TT 1 _ 1  to TT 1 _ k  may transfer the photo-generated charges generated by the photoelectric conversion elements PD 1 _ 1  to PD 1 _ k  to the first floating diffusion region FD 1   a  in response to charge transfer control signals TG 1 _ 1  to TG 1 _ k  respectively supplied to gates G 1 _ 1  to G 1 _ k  thereof. Each of the gates G 1 _ 1  to G 1 _ k  may be a vertical transfer gate (VTG). 
     When each of the photoelectric conversion elements PD 1 _ 1  to PD 1 _ k  is a photodiode, a second terminal (e.g., an anode) of the photodiode may be connected with a negative voltage supply line NN supplying a first negative voltage Vneg (e.g., −0.6 V). 
     A gate G 14  of the first source follower transistor SF 1  is connected with the first floating diffusion node ND 1 _ 1 , and the first source follower transistor SF 1  is connected between the first voltage node NP 1  and a fifth connection node ND 1 _ 4 . 
     The first select transistor ST 1  is connected between the fifth connection node ND 1 _ 4  and a first output node Vout 1 , a first selection signal SEL 1  is supplied to a gate G 15  of the first select transistor ST 1 , and the first output node Vout 1  is connected with a first pixel line COL 1 . 
     As the second pixel  113  is formed (or manufactured) by using the FDTI process, three transistors (i.e., a third transistor TR 2 _ 1 , a fourth transistor TR 2 _ 2 , and a second reset transistor RT 2 ) that are connected in series are connected between a fourth floating diffusion node ND 2 _ 1  and a second voltage node NP 2 . The fourth floating diffusion node ND 2 _ 1  is connected with a fourth floating diffusion region FD 2   a , and the second voltage node NP 2  is connected with the voltage supply line PWL. The first voltage node NP 1  and the second voltage node NP 2  are connected with each other through a metal contact. 
     To adjust a second conversion gain of a second source follower transistor SF 2 , the second pixel  113  includes the three transistors TR 2 _ 1 , TR 2 _ 2 , and RT 2  connected in series between the fourth floating diffusion node ND 2 _ 1  and the second voltage node NP 2 . 
     As expressed by Equation 1 below, the conversion gain (CG) means a ratio of μN per e− supplied to each of the gates G 14  and G 24  of the source follower transistors SF 1  and SF 2  of the first and second pixels  112  and  113 . 
     
       
         
           
             
               
                 
                   CG 
                   = 
                   
                     
                       μ 
                       ⁢ 
                       V 
                     
                     
                       e 
                       - 
                     
                   
                 
               
               
                 
                   [ 
                   
                     Equation 
                     ⁢ 
                         
                     1 
                   
                   ] 
                 
               
             
           
         
       
     
     The third transistor TR 2 _ 1  is connected between a third connection node ND 2 _ 2  and the fourth floating diffusion node ND 2 _ 1 , and a third conversion gain control signal DCG 2 _ 1  is supplied to a gate G 21  of the third transistor TR 2 _ 1 . The third connection node ND 2 _ 2  is connected with a fifth floating diffusion region FD 2   b  through a metal contact. 
     The fourth transistor TR 2 _ 2  is connected between the third connection node ND 2 _ 2  and a fourth connection node ND 2 _ 3 , and a fourth conversion gain control signal DCG 2 _ 2  is supplied to a gate G 22  of the fourth transistor TR 2 _ 2 . The fourth connection node ND 2 _ 3  is connected with a sixth floating diffusion region FD 2   c  through a metal contact. 
     The second reset transistor RT 2  is connected between the second voltage node NP 2  and the fourth connection node ND 2 _ 3 , and a second reset signal RG 2  is supplied to a gate G 23  of the second reset transistor RT 2 . 
     The second pixel  113  further includes a second group of charge transfer transistors TT 2 _ 1  to TT 2 _ k , the second source follower transistor SF 2 , and a second select transistor ST 2 . 
     The charge transfer transistors TT 2 _ 1  to TT 2 _ k  of the second group may transfer photo-generated charges generated by a second group of photoelectric conversion elements PD 2 _ 1  to PD 2 _ k  to the fourth floating diffusion region FD 2   a , and the photoelectric conversion elements PD 2 _ 1  to PD 2 _ k  of the second group are separated from each other by the FDTI. 
     The charge transfer transistors TT 2 _ 1  to TT 2 _ k  may transfer the photo-generated charges generated by the photoelectric conversion elements PD 2 _ 1  to PD 2 _ k  to the fourth floating diffusion region FD 2   a  in response to charge transfer control signals TG 2 _ 1  to TG 2 _ k  respectively supplied to gates G 2 _ 1  to G 2 _ k  thereof. Each of the gates G 2 _ 1  to G 2 _ k  may be a vertical transfer gate (VTG). 
     When each of the photoelectric conversion elements PD 2 _ 1  to PD 2 _ k  is a photodiode, a second terminal (e.g., an anode) of the photodiode may be connected with the negative voltage supply line NN supplying the first negative voltage Vneg. 
     A gate G 24  of the second source follower transistor SF 2  is connected with the fourth floating diffusion node ND 2 _ 1 , and the second source follower transistor SF 2  is connected between the second voltage node NP 2  and a sixth connection node ND 2 _ 4 . 
     The second select transistor ST 2  is connected between the sixth connection node ND 2 _ 4  and a second output node Vout 2 , a second selection signal SEL 2  is supplied to a gate G 25  of the second select transistor ST 2 , and the second output node Vout 2  is connected with the first pixel line COL 1 . 
     A first connection line ML 1  electrically connects the first connection node ND 1 _ 2  with the third connection node ND 2 _ 2 , and a second connection line ML 2  electrically connects the second connection node ND 1 _ 3  with the fourth connection node ND 2 _ 3 . 
     For convenience of description, even though the connection lines ML 1  and ML 2  are illustrated in  FIG.  2    as disposed outside of the pixels  112  and  113 , the connection lines ML 1  and ML 2  may be disposed in a metal wiring layer of the pixel array  110 . 
     Below, an operation of each of the first pixel  112  and the second pixel  113  will be described. 
     When the reset transistors RT 1  and RT 2  are turned on in a state where the transistors TR 1 _ 1 , TR 1 _ 2 , TR 2 _ 1 , and TR 2 _ 2  are turned on, potentials of the floating diffusion regions FD 1   a  and FD 2   a  become a level of the pixel power supply voltage VPIX. 
     When the light is incident onto the photoelectric conversion elements PD 1 _ 1  to PD 1 _ k  and PD 2 _ 1  to PD 2 _ k , each of the photoelectric conversion elements PD 1 _ 1  to PD 1 _ k  and PD 2 _ 1  to PD 2 _ k  generates electron-hole pairs (EHPs), for example, photo-generated charges. Each of the photoelectric conversion elements PD 1 _ 1  to PD 1 _ k  and PD 2 _ 1  to PD 2 _ k  may be a photodiode, a phototransistor, a photogate, or a pinned photodiode, but embodiments of the present disclosure is not limited thereto. 
     When the charge transfer transistors TT 1 _ 1  to TT 1 _ k  are turned on depending on the charge transfer control signals TG 1 _ 1  to TG 1 _ k , the photo-generated charges generated by the photoelectric conversion elements PD 1 _ 1  to PD 1 _ k  are transferred to the floating diffusion region FD 1   a ; when the charge transfer transistors TT 2 _ 1  to TT 2 _ k  are turned on depending on the charge transfer control signals TG 2 _ 1  to TG 2 _ k , the photo-generated charges generated by the photoelectric conversion elements PD 2 _ 1  to PD 2 _ k  are transferred to the floating diffusion region FD 2   a.    
     As the photo-generated charges are transferred to the floating diffusion regions FD 1   a  and FD 2   a , gate voltages that are supplied to the gates G 14  and G 24  of the source follower transistors SF 1  and SF 2  change. When each of the select transistors ST 1  and ST 2  is turned on, a potential change of a source terminal of each of the source follower transistors SF 1  and SF 2  is output to the first pixel line COL 1  as the first pixel signal PIX 1 . 
     Each of the transistors TR 1 _ 1 , TR 1 _ 2 , RT 1 , TR 2 _ 1 , TR 2 _ 2 , RT 2 , SF 1 , SF 2 , ST 1 , and ST 2  may be implemented with an NMOSFET or PMOSFET. Each of the transistors TR 1 _ 1 , TR 1 _ 2 , RT 1 , TR 2 _ 1 , TR 2 _ 2 , RT 2 , SF 1 , SF 2 , ST 1 , and ST 2  may include a first electrode and a second electrode; each of electrodes of the transistors TR 1 _ 1 , TR 1 _ 2 , RT 1 , TR 2 _ 1 , TR 2 _ 2 , RT 2 , SF 1 , SF 2 , ST 1 , and ST 2  that are respectively connected with the nodes ND 1 _ 1 , ND 1 _ 2 , ND 1 _ 3 , ND 2 _ 1 , ND 2 _ 2 , ND 2 _ 3 , NP 1 , and NP 2  may be one of the first electrode and the second electrode. 
     Depending on whether a transistor is an NMOSFET or a PMOSFET, the first electrode is one of a drain electrode and a source electrode, and the second electrode is the other of the drain electrode and the source electrode. 
       FIG.  3 A  is a cross-sectional view of a sub-pixel region having an FDTI structure according to an embodiment of the present disclosure and including a transistor, a photoelectric conversion element, a vertical transfer gate, and a floating diffusion region. The cross-sectional view of  FIG.  3 A  is a conceptual diagram for describing the layout of at least one transistor, a photodiode, a vertical transfer gate VTG, and a floating diffusion region FD included in each of sub-pixel regions of  FIGS.  4 A,  5 A, and  6 A . 
     Referring to  FIG.  3 A , a sub-pixel region (also called a sub-pixel) SPX having the FDTI structure includes a transistor including a channel CH and a gate TRG, a photodiode PD, a vertical transfer gate VTG, and a floating diffusion region FD. In  FIG.  3 A , “n” means an n-type material, and “p” means a p-type material. 
     As illustrated in  FIG.  3 A , the channel CH of the transistor and the floating diffusion region FD are separated by a shallow trench isolation (STI) material (e.g., silicon dioxide (SiO2)). 
       FIG.  3 B  is a plan view of a sub-pixel region corresponding to the cross-sectional view illustrated in  FIG.  3 A . 
     A plan view of a pixel including four sub-pixel regions SPX 1  to SPX 4  is illustrated as an example, and the four sub-pixel regions SPX 1  to SPX 4  have the same structure. The four sub-pixel regions SPX 1  to SPX 4  are not completely separated by the FDTI. As such, charge transfer transistors formed in different sub-pixel regions may share the floating diffusion region FD. 
     The sub-pixel region SPX 1  includes the gate TRG of the transistor, the photodiode PD or a photodiode portion region PPR, and the vertical transfer gate VTG, along direction A-A′ illustrated in  FIGS.  3 A and  3 B . The four sub-pixel regions SPX 1  to SPX 4  have the same horizontal length LE and the same vertical length HE. 
     As the vertical transfer gate VTG is formed for each of the sub-pixel regions SPX 1  to SPX 4 , it is easy to separate the transistor from the floating diffusion region FD, and thus, the limitation on the spatial layout of the transistor decreases. 
     Referring to  FIG.  3 B , the transistor including the gate TRG includes a source/drain region S/D_R and a drain/source region D/S_R. Herein, the source/drain region S/D_R is connected with a first electrode, and the drain/source region D/S_R is connected with a second electrode. 
     “VTG” illustrated in  FIGS.  3 A and  3 B  corresponds to gates G 1 _ 1  to G 1 _ 4  and G 2 _ 1  to G 2 _ 4  illustrated in  FIG.  4 A , corresponds to gates G 1 _ 1  to G 1 _ 8  and G 2 _ 1  to G 2 _ 8  illustrated in  FIG.  5 A , and corresponds to gates G 1 _ 1  to G 1 _ 16  and G 2 _ 1  to G 2 _ 16  illustrated in  FIG.  6 A . 
     “FD” illustrated in  FIGS.  3 A and  3 B  corresponds to floating diffusion regions FD 1   a  and FD_ 1   b  illustrated in  FIGS.  4 A,  5 A, and  6 A . 
     “TRG” illustrated in  FIGS.  3 A and  3 B  corresponds to gates G 11 , G 12 , G 13 , G 14 _ 1 , G 15 , DG, G 21 , G 22 , G 23 , G 24 _ 1 , G 24 _ 2 , G 24 _ 3 , and G 25  illustrated in  FIG.  4 A , corresponds to gates G 11 , G 12 , G 13 , G 14 _ 1 , G 14 _ 2 , G 15 , DG, G 21 , G 22 , G 23 , G 24 _ 1 , G 24 _ 2 , and G 25  illustrated in  FIG.  5 A , and corresponds to gates G 11 , G 12 _ 1 , G 12 _ 2 , G 12 _ 3 , G 13 ,  14   a ,  14   b , G 15 , DG, G 21 , G 22 _ 1 , G 22 _ 2 , G 22 _ 3 , G 23 ,  24   a ,  24   b ,  24   c ,  24   d , and G 25  illustrated in  FIG.  6 A . 
       FIG.  4 A  is a plan view of a first pixel and a second pixel, each of which includes four photoelectric conversion elements. Referring to  FIGS.  2 ,  3 A,  3 B, and  4 A , the structure of the first pixel  112  is identical to the structure of the second pixel  113 . The first pixel  112  includes four sub-pixel regions, and the second pixel  113  includes four sub-pixel regions. Components included in each sub-pixel region may be understood from the description given with reference to  FIG.  2   . 
     Referring to  FIGS.  2  and  4 A , depending on the FDTI process, the four photoelectric conversion elements PD 1 _ 1  to PD 1 _ 4  and the four charge transfer transistors TT 1 _ 1  to TT 1 _ 4  are formed in the first pixel  112 , and the four photoelectric conversion elements PD 2 _ 1  to PD 2 _ 4  and the four charge transfer transistors TT 2 _ 1  to TT 2 _ 4  are formed in the second pixel  113 . 
     The charge transfer transistors TT 1 _ 1  to TT 1 _ 4  of the first pixel  112  respectively include the vertical transfer gates G 1 _ 1  to G 1 _ 4  formed in different sub-pixel regions. The charge transfer transistors TT 2 _ 1  to TT 2 _ 4  of the second pixel  113  respectively include the vertical transfer gates G 2 _ 1  to G 2 _ 4  formed in different sub-pixel regions. 
     The four charge transfer transistors TT 1 _ 1  to TT 1 _ 4  are formed to share the first floating diffusion region FD 1   a  in structure, and the four charge transfer transistors TT 2 _ 1  to TT 2 _ 4  are formed to share the fourth floating diffusion region FD 2   a  in structure. 
     The four sub-pixel regions included in the first pixel  112  and the four sub-pixel regions included in the second pixel  113  are separated from each other by the FDTI. According to embodiments, a second negative voltage (e.g., −1.5 V) may be supplied to the FDTI formed between the sub-pixel regions. 
     For example, the FDTI may be filled with an insulating material (e.g., silicon dioxide (SiO2) or any other dielectric material), and thus, the FDTI may electrically isolate the sub-pixel regions from each other. 
     The first electrodes of the four charge transfer transistors TT 1 _ 1  to TT 1 _ 4  are connected with the first floating diffusion node ND 1 _ 1  through a first transfer line FL 1 , the second electrodes of the four charge transfer transistors TT 1 _ 1  to TT 1 _ 4  are respectively connected with the first terminals of the four photoelectric conversion elements PD 1 _ 1  to PD 1 _ 4 , and the second terminals of the four photoelectric conversion elements PD 1 _ 1  to PD 1 _ 4  are connected with the negative voltage supply line NN. For example, when each of the photoelectric conversion elements is a photodiode, the first terminal may be a cathode, and the second terminal may be an anode. 
     In  FIG.  4 A , the first electrode of a dummy transistor DTr is connected with the negative voltage supply line NN, and the second electrode thereof is connected with the corresponding voltage node NP 1  or NP 2 . According to an embodiment, a body voltage that is supplied to the body of the dummy transistor DTr is supplied to a gate DG of the dummy transistor DTr. 
     Referring to  FIG.  4 A , in the first pixel  112 , the transistors TR 1 _ 1  and TR 1 _ 2  that respectively include the gates G 11  and G 12  are formed in the same sub-pixel region. As described with reference to  FIG.  3 A , the transistors TR 1 _ 1  and TR 1 _ 2  are separated from each other by the STI. 
     Also, in the second pixel  113 , the transistors TR 2 _ 1  and TR 2 _ 2  that respectively include the gates G 21  and G 22  are formed in the same sub-pixel region. As described with reference to  FIG.  3 A , the transistors TR 2 _ 1  and TR 2 _ 2  are separated from each other by the STI. 
     Referring to  FIGS.  3 A and  4 A , when a plurality of transistors are formed in one sub-pixel region, the plurality of transistors are separated from each other by the STI. 
     Referring to  FIGS.  2  and  4 A , the first connection line ML 1  electrically connects the first connection node ND 1 _ 2  with the third connection node ND 2 _ 2 , and the second connection line ML 2  electrically connects the second connection node ND 1 _ 3  with the fourth connection node ND 2 _ 3 . 
       FIG.  4 B  is a circuit diagram illustrating an embodiment of a second source follower transistor included in a second pixel of  FIG.  2   . Because the structure of the first source follower transistor SF 1  is identical to the structure of the second source follower transistor SF 2 , the second source follower transistor SF 2  including three sub-source follower transistors SF 2 _ 1 , SF 2 _ 2 , and SF 2 _ 3  connected in parallel are illustrated as an example, which will be described below. 
     One sub-source follower transistor SF 2 _ 1  of the three sub-source follower transistors SF 2 _ 1 , SF 2 _ 2 , and SF 2 _ 3  is formed in the second pixel  113 , and the remaining sub-source follower transistors SF 2 _ 2  and SF 2 _ 3  are formed in the first pixel  112 . Gates G 24 _ 1 , G 24 _ 2 , and G 24 _ 3  of the sub-source follower transistors SF 2 _ 1 , SF 2 _ 2 , and SF 2 _ 3  included in the second source follower transistor SF 2  are connected with a second transfer line FL 2  through metal contacts. 
     One of three sub-source follower transistors of the first pixel  112  is formed in the first pixel  112 , and the remaining sub-source follower transistors are formed in a pixel (e.g.,  111 ) immediately adjacent to the first pixel  112 . Gates of the sub-source follower transistors included in the first source follower transistor SF 1  are connected with the first transfer line FL 1  through metal contacts. 
     One of three sub-source follower transistors included in a source follower transistor of a pixel adjacent to the second pixel  113  is formed in the pixel, and the remaining sub-source follower transistors are formed in the second pixel  113 . Gates of the three sub-source follower transistors of the source follower transistor included in the pixel adjacent to the second pixel  113  are connected with a third transfer line FL 3  through metal contacts. 
     The gates SF 2 _ 1 , SF 2 _ 2 , and SF 2 _ 3  of the sub-source follower transistors of  FIG.  4 B  are connected with the fourth floating diffusion node ND 2 _ 1  through a metal contact and the second transfer line FL 2 . 
     The first electrode of the sub-source follower transistor SF 2 _ 1  implemented in the second pixel  113  from among the sub-source follower transistors SF 2 _ 1 , SF 2 _ 2 , and SF 2 _ 3  is connected with the sixth connection node ND 2 _ 4 , and the second electrode thereof is connected with the second voltage node NP 2 . 
     However, the first electrode of each of the sub-source follower transistors SF 2 _ 2  and SF 2 _ 3  implemented in the first pixel  112  from among the sub-source follower transistors SF 2 _ 1 , SF 2 _ 2 , and SF 2 _ 3  is connected with the sixth connection node ND 2 _ 4 , and the second electrode thereof is connected with the first voltage node NP 1 . 
     As illustrated in  FIG.  4 B , the sub-source follower transistor SF 2 _ 1  having the gate G 24 _ 1  is formed in the second pixel  113 , and the sub-source follower transistor SF 2 _ 2  having the gate G 24 _ 2  and the sub-source follower transistor SF 2 _ 3  having the gate G 24 _ 3  are formed in the first pixel  112 . In this case, the sub-source follower transistors SF 2 _ 2  and SF 2 _ 3  formed in the first pixel  112  are separated by the STI. 
       FIG.  5 A  is a plan view of a first pixel and a second pixel, each of which includes eight photoelectric conversion elements. The first pixel  112  includes eight sub-pixel regions, and the second pixel  113  includes eight sub-pixel regions. 
     Referring to  FIGS.  1 ,  2 ,  3 A,  3 B and  5 A , depending on the FDTI process, the eight photoelectric conversion elements PD 1 _ 1  to PD 1 _ 8  and the eight charge transfer transistors TT 1 _ 1  to TT 1 _ 8  are formed in the first pixel  112 , and the eight photoelectric conversion elements PD 2 _ 1  to PD 2 _ 8  and the eight charge transfer transistors TT 2 _ 1  to TT 2 _ 8  are formed in the second pixel  113 . 
     The charge transfer transistors TT 1 _ 1  to TT 1 _ 8  of the first pixel  112  respectively include the vertical transfer gates G 1 _ 1  to G 1 _ 8  formed in different sub-pixel regions; the charge transfer transistors TT 2 _ 1  to TT 2 _ 8  of the second pixel  113  respectively include the vertical transfer gates G 2 _ 1  to G 2 _ 8  formed in different sub-pixel regions. 
     The eight sub-pixel regions included in the first pixel  112  and the eight sub-pixel regions included in the second pixel  113  are separated from each other by the FDTI. 
     The first electrode of each of the eight charge transfer transistors TT 1 _ 1  to TT 1 _ 8  is connected with the first floating diffusion node ND 1 _ 1  through the first transfer line FL 1 , and the second electrode thereof is connected with the first terminal of each of the eight photoelectric conversion elements PD 1 _ 1  to PD 1 _ 8 . The second terminals of the eight photoelectric conversion elements PD 1 _ 1  to PD 1 _ 8  are connected with the negative voltage supply line NN. 
     In  FIG.  5 A , the first electrode of the dummy transistor DTr is connected with the negative voltage supply line NN, and the second electrode thereof is connected with the corresponding voltage node NP 1  or NP 2 . According to an embodiment, a body voltage that is supplied to the body of the dummy transistor DTr is supplied to the gate DG of the dummy transistor DTr. 
       FIG.  5 B  is a circuit diagram illustrating an embodiment of a first source follower transistor included in a first pixel of  FIG.  2   . 
     Because the structure of the first source follower transistor SF 1  of the first pixel  112  is identical to the structure of the second source follower transistor SF 2  of the second pixel  113 , the structure of the first source follower transistor SF 1  will be described with reference to  FIG.  5 B . 
     Referring to  FIG.  5 B , the first source follower transistor SF 1  of the first pixel  112  includes two sub-source follower transistors SF 1 _ 1  and SF 1 _ 2  connected in parallel. 
     The two sub-source follower transistors SF 1 _ 1  and SF 1 _ 2  are formed in different sub-pixel regions. 
     Referring to  FIGS.  2  and  5 A , the first connection line ML 1  electrically connects the first connection node ND 1 _ 2  connected with the second floating diffusion region FD 1   b  and the third connection node ND 2 _ 2  connected with the fifth floating diffusion region FD 2   b , and the second connection line ML 2  electrically connects the second connection node ND 1 _ 3  connected with the third floating diffusion region FD 1   c  and the fourth connection node ND 2 _ 3  connected with the sixth floating diffusion region FD 2   c.    
       FIG.  6 A  is a plan view of a first pixel and a second pixel, each of which includes 16 photoelectric conversion elements. 
     Referring to  FIGS.  1  to  3 B and  6 A , depending on the FDTI process, the 16 photoelectric conversion elements PD 1 _ 1  to PD 1 _ 16  and the 16 charge transfer transistors TT 1 _ 1  to TT 1 _ 16  are formed in the first pixel  112 , and the 16 photoelectric conversion elements PD 2 _ 1  to PD 2 _ 16  and the 16 charge transfer transistors TT 2 _ 1  to TT 2 _ 16  are formed in the second pixel  113 . 
     The charge transfer transistors TT 1 _ 1  to TT 1 _ 16  of the first pixel  112  respectively include the vertical transfer gates G 1 _ 1  to G 1 _ 16  formed in different sub-pixel regions; the charge transfer transistors TT 2 _ 1  to TT 2 _ 16  of the second pixel  113  respectively include the vertical transfer gates G 2 _ 1  to G 2 _ 16  formed in different sub-pixel regions. 
     The 16 sub-pixel regions included in the first pixel  112  and the 16 sub-pixel regions included in the second pixel  113  are separated from each other by the FDTI. 
     The first electrode of each of the 16 charge transfer transistors TT 1 _ 1  to TT 1 _ 16  is connected with the first floating diffusion node ND 1 _ 1  through the first transfer line FL 1 , and the second electrode thereof is connected with the first terminal of each of the 16 photoelectric conversion elements PD 1 _ 1  to PD 1 _ 16 . The second terminals of the 16 photoelectric conversion elements PD 1 _ 1  to PD 1 _ 16  are connected with the negative voltage supply line NN. 
       FIG.  6 B  is a circuit diagram illustrating an embodiment of a second transistor included in a first pixel of  FIG.  2   , and  FIG.  6 C  is a circuit diagram illustrating an embodiment of a second source follower transistor included in a second pixel of  FIG.  2   . 
     Referring to  FIGS.  2 ,  6 A,  6 B, and  6 C , because the second transistor TR 1 _ 2  and the fourth transistor TR 2 _ 2  have the same structure, the circuit diagram of the second transistor TR 1 _ 2  including three sub-transistors TR 1 _ 2   a , TR 1 _ 2   b , and TR 1 _ 2   c  connected in parallel is illustrated in  FIG.  6 B  as an example. The three sub-transistors TR 1 _ 2   a , TR 1 _ 2   b , and TR 1 _ 2   c  are formed in different sub-pixel regions. 
     Because the first source follower transistor SF 1  and the second source follower transistor SF 2  have the same structure, the circuit diagram of the second source follower transistor SF 2  including four sub-transistors SF 2   a , SF 2   b , SF 2   c , and SF 2   d  connected in parallel is illustrated in  FIG.  6 C  as an example. 
     Referring to  FIG.  6 A , the first source follower transistor SF 1  include four sub-transistors connected in parallel; two of the four sub-transistors are formed in the first pixel  112 , and the remaining sub-transistors are formed in a pixel (e.g.,  111 ) immediately adjacent to the first pixel  112 . 
     Referring to  FIG.  6 C , the second source follower transistor SF 2  includes the four sub-transistors SF 2   a , SF 2   b , SF 2   c , and SF 2   d  connected in parallel; two sub-transistors SF 2   a  and SF 2   b  of the four sub-transistors SF 2   a , SF 2   b , SF 2   c , and SF 2   d  are formed in the second pixel  113 , and the remaining sub-transistors SF 2   c  and SF 2   d  are formed in the first pixel  112 . The sub-transistors SF 2   a , SF 2   b , SF 2   c , and SF 2   d  include gates  24   a ,  24   b ,  24   c , and  24   d , respectively. 
       FIG.  7    is a timing diagram of control signals supplied to a first pixel and a second pixel of  FIG.  2    when an image sensor of  FIG.  1    operates in a high conversion gain mode. 
     Referring to  FIGS.  1  to  7   , when the image sensor  100  operates in a first conversion gain mode (e.g., a high conversion gain (HCG) mode), depending on the mode control signal MODE_ctl indicating that the image sensor  100  operates in the high conversion gain mode, the control signal generator  150  generates the control signals TG 1 , SEL 1 , RG 1 , DCG 1 _ 1 , DCG 1 _ 2 , RG 2 , DCG 2 _ 1 , and DCG 2 _ 2  having waveforms illustrated in  FIG.  7    and supplies the control signals TG 1 , SEL 1 , RG 1 , DCG 1 _ 1 , DCG 1 _ 2 , RG 2 , DCG 2 _ 1 , and DCG 2 _ 2  to the first pixel  112  and the second pixel  113 . 
     Herein, it is assumed that the first charge transfer control signal TG 1  collectively calls the first group of charge transfer control signals TG 1 _ 1  to TG 1 _ k  supplied to the gates G 1 _ 1  to G 1 _ k  of the charge transfer transistors TT 1 _ 1  to TT 1 _ k  and a waveform of each of the first group of charge transfer control signals TG 1 _ 1  to TG 1 _ k  is identical to the waveform of the first charge transfer control signal TG 1 . 
     It is assumed that the second charge transfer control signal TG 2  collectively calls the second group of charge transfer control signals TG 2 _ 1  to TG 2 _ k  supplied to the gates G 2 _ 1  to G 2 _ k  of the charge transfer transistors TT 2 _ 1  to TT 2 _ k  and a waveform of each of the second group of charge transfer control signals TG 2 _ 1  to TG 2 _ k  is identical to the waveform of the second charge transfer control signal TG 2 . 
     The first reset signal RG 1  is supplied to the gate G 13  of the first reset transistor RT 1 , the first conversion gain control signal DCG 1 _ 1  is supplied to the gate G 11  of the first control transistor TR 1 _ 1 , the second conversion gain control signal DCG 1 _ 2  is supplied to the gate G 12  of the second control transistor TR 1 _ 2 , and the first selection signal SEL 1  is supplied to the gate G 15  of the first select transistor ST 1 . 
     The second reset signal RG 2  is supplied to the gate G 23  of the second reset transistor RT 2 , the third conversion gain control signal DCG 2 _ 1  is supplied to the gate G 21  of the third control transistor TR 2 _ 1 , the fourth conversion gain control signal DCG 2 _ 2  is supplied to the gate G 22  of the fourth control transistor TR 2 _ 2 , and the second selection signal SEL 2  is supplied to the gate G 24  of the second select transistor ST 2 . 
     In this case, each of the transistors TT 1 _ 1  to TT 1 _ k , ST 1 , SF 1 , TR 1 _ 1 , TR 1 _ 2 , RT 1 , TT 2 _ 1  to TT 2 _ k , ST 2 , SF 2 , TR 2 _ 1 , TR 2 _ 2 , and RT 2  is an n-type MOS transistor. 
     In  FIGS.  7  to  9   , “H” means the high level for turning on the n-type MOS transistor, and “L” means the low level for turning off the n-type MOS transistor. 
     To perform the high conversion gain (HCG) mode, the control signal generator  150  generates the first charge transfer control signal TG 1  that toggles twice during a shutter time period SHT 1 . 
     During a first readout time period ReadT 1  in which the first pixel signal PIX 1  output from the first pixel  112  is read out, the control signal generator  150  generates the first charge transfer control signal TG 1  including a first pulse signal TG 1   a  and a second pulse signal TG 1   b.    
     During a second readout time period ReadT 2  in which the first pixel signal PIX 1  output from the second pixel  113  is read out, the control signal generator  150  generates the second charge transfer control signal TG 2  including a third pulse signal TG 2   a  and a fourth pulse signal TG 2   b.    
     According to embodiments, during the first readout time period ReadT 1 , only two charge transfer transistors TT 1 _ 1  and TT 1 _ 2  or TT 1 _ 1  and TT 1 _ 3  among the four charge transfer transistors TT 1 _ 1  to TT 1 _ 4  included in the first pixel  112  illustrated in  FIGS.  2  and  4 A  may be turned on in response to the first pulse signal TG 1   a  having the high level, and only two charge transfer transistors TT 1 _ 3  and TT 1 _ 4  or TT 1 _ 2  and TT 1 _ 4  among the four charge transfer transistors TT 1 _ 1  to TT 1 _ 4  may be turned on in response to the second pulse signal TG 1   b  having the high level. 
     Also, during the second readout time period ReadT 2 , only two charge transfer transistors TT 2 _ 1  and TT 2 _ 2  or TT 2 _ 1  and TT 2 _ 3  among the four charge transfer transistors TT 2 _ 1  to TT 2 _ 4  included in the second pixel  113  illustrated in  FIGS.  2  and  4 A  may be turned on in response to the third pulse signal TG 2   a  having the high level, and only two charge transfer transistors TT 2 _ 3  and TT 2 _ 4  or TT 2 _ 2  and TT 2 _ 4  among the four charge transfer transistors TT 2 _ 1  to TT 2 _ 4  may be turned on in response to the fourth pulse signal TG 2   b  having the high level. 
     According to embodiments, during the first readout time period ReadT 1 , only four charge transfer transistors TT 1 _ 1 , TT 1 _ 2 , TT 1 _ 5 , and TT 1 _ 6  or TT 1 _ 1 , TT 1 _ 3 , TT 1 _ 5 , and TT 1 _ 7  among the eight charge transfer transistors TT 1 _ 1  to TT 1 _ 8  included in the first pixel  112  illustrated in  FIGS.  2  and  5 A  may be turned on in response to the first pulse signal TG 1   a  having the high level, and only four charge transfer transistors TT 1 _ 3 , TT 1 _ 4 , TT 1 _ 7 , and TT 1 _ 8  or TT 1 _ 2 , TT 1 _ 4 , TT 1 _ 6 , and TT 1 _ 8  among the eight charge transfer transistors TT 1 _ 1  to TT 1 _ 8  may be turned on in response to the second pulse signal TG 1   b  having the high level. 
     Also, during the second readout time period ReadT 2 , only four charge transfer transistors TT 2 _ 1 , TT 2 _ 2 , TT 2 _ 5 , and TT 2 _ 6  or TT 2 _ 1 , TT 2 _ 3 , TT 2 _ 5 , and TT 2 _ 7  among the eight charge transfer transistors TT 1 _ 1  to TT 1 _ 8  included in the second pixel  113  illustrated in  FIGS.  2  and  5 A  may be turned on in response to the third pulse signal TG 2   a  having the high level, and only four charge transfer transistors TT 2 _ 3 , TT 2 _ 4 , TT 2 _ 7 , and TT 2 _ 8  or TT 2 _ 2 , TT 2 _ 4 , TT 2 _ 6 , and TT 2 _ 8  among the eight charge transfer transistors TT 2 _ 1  to TT 2 _ 8  may be turned on in response to the fourth pulse signal TG 2   b  having the high level. 
     According to embodiments, during the first readout time period ReadT 1 , only eight charge transfer transistors TT 1 _ 1 , TT 1 _ 2 , TT 1 _ 5 , TT 1 _ 6 , TT 1 _ 9 , TT 1 _ 10 , TT 1 _ 13 , and TT 1 _ 14  or TT 1 _ 1 , TT 1 _ 3 , TT 1 _ 5 , TT 1 _ 7 , TT 1 _ 9 , TT 1 _ 11 , TT 1 _ 13 , and TT 1 _ 15  among the 16 charge transfer transistors TT 1 _ 1  to TT 1 _ 16  included in the first pixel  112  illustrated in  FIGS.  2  and  6 A  may be turned on in response to the first pulse signal TG 1   a  having the high level, and only eight charge transfer transistors TT 1 _ 3 , TT 1 _ 4 , TT 1 _ 7 , TT 1 _ 8 , TT 1 _ 11 , TT 1 _ 12 , TT 1 _ 15 , and TT 1 _ 16  or TT 1 _ 2 , TT 1 _ 4 , TT 1 _ 6 , TT 1 _ 8 , TT 1 _ 10 , TT 1 _ 12 , TT 1 _ 14 , and TT 1 _ 16  among the 16 charge transfer transistors TT 1 _ 1  to TT 1 _ 16  may be turned on in response to the second pulse signal TG 1   b  having the high level. 
     Also, during the second readout time period ReadT 2 , only eight charge transfer transistors TT 2 _ 1 , TT 2 _ 2 , TT 2 _ 5 , TT 2 _ 6 , TT 2 _ 9 , TT 2 _ 10 , TT 2 _ 13 , and TT 2 _ 14  or TT 2 _ 1 , TT 2 _ 3 , TT 2 _ 5 , TT 2 _ 7 , TT 2 _ 9 , TT 2 _ 11 , TT 2 _ 13 , and TT 2 _ 15  among the 16 charge transfer transistors TT 2 _ 1  to TT 2 _ 16  included in the first pixel  112  illustrated in  FIGS.  2  and  6 A  may be turned on in response to the third pulse signal TG 2   a  having the high level, and only eight charge transfer transistors TT 2 _ 3 , TT 2 _ 4 , TT 2 _ 7 , TT 2 _ 8 , TT 2 _ 11 , TT 2 _ 12 , TT 2 _ 15 , and TT 2 _ 16  or TT 2 _ 2 , TT 2 _ 4 , TT 2 _ 6 , TT 2 _ 8 , TT 2 _ 10 , TT 2 _ 12 , TT 2 _ 14 , and TT 2 _ 16  among the 16 charge transfer transistors TT 2 _ 1  to TT 2 _ 16  may be turned on in response to the fourth pulse signal TG 2   b  having the high level. 
     During the first readout time period ReadT 1  of  FIG.  7   , the transistors ST 1 , TR 1 _ 2 , RT 1 , TR 2 _ 1 , TR 2 _ 2 , and RT 2  are turned on depending on the control signals SEL 1 , DCG 1 _ 2 , RG 1 , DCG 2 _ 1 , DCG 2 _ 2 , and RG 2  having the high level “H”, and the transistors TT 2 _ 1  to TT 2 _ k , ST 2 , and TR 1 _ 1  are turned off depending on the control signals TG 2 , SEL 2 , and DCG 1 _ 1  having the low level “L”. 
     For example, for an auto-focus operation, the first charge transfer control signal TG 1  including the first pulse signal TG 1   a  and the second pulse signal TG 1   b  is generated, and the second charge transfer control signal TG 2  including the third pulse signal TG 2   a  and the fourth pulse signal TG 2   b  is generated. 
     During the second readout time period ReadT 2  of  FIG.  7   , the transistors ST 2 , TR 1 _ 1 , TR 1 _ 2 , RT 1 , TR 2 _ 2 , and RT 2  are turned on depending on the control signals SEL 2 , DCG 1 _ 1 , DCG 1 _ 2 , RG 1 , DCG 2 _ 2 , and RG 2  having the high level “H”, and the transistors TT 1 _ 1  to TT 1 _ k , ST 1 , and TR 2 _ 1  are turned off depending on the control signals TG 1 , SEL 1 , and DCG 2 _ 1  having the low level “L”. 
     The second readout operation that is performed in the second readout time period ReadT 2  starts immediately after the first readout operation that is performed in the first readout time period ReadT 1 . 
       FIG.  8    is a timing diagram of control signals supplied to a first pixel and a second pixel of  FIG.  2    when an image sensor of  FIG.  1    operates in a medium conversion mode. 
     Referring to  FIGS.  1  to  6 C and  8   , when the image sensor  100  operates in a second conversion gain mode (e.g., a medium conversion gain (MCG) mode), depending on the mode control signal MODE_ctl indicating that the image sensor  100  operates in the medium conversion gain mode, the control signal generator  150  generates the control signals TG 1 , SEL 1 , DCG 1 _ 1 , DCG 1 _ 2 , RG 1 , DCG 2 _ 1 , DCG 2 _ 2 , and RG 2  having waveforms illustrated in  FIG.  8    and supplies the control signals TG 1 , SEL 1 , DCG 1 _ 1 , DCG 1 _ 2 , RG 1 , DCG 2 _ 1 , DCG 2 _ 2 , and RG 2  to the first pixel  112  and the second pixel  113 . 
     During the first readout time period ReadT 1  of  FIG.  8   , the transistors ST 1 , TR 1 _ 1 , RT 1 , TR 2 _ 1 , and RT 2  are turned on depending on the control signals SEL 1 , DCG 1 _ 1 , RG 1 , DCG 2 _ 1 , and RG 2  having the high level “H”, and the transistors ST 2 , TT 2 _ 1  to TT 2 _ k , TR 1 _ 2 , and TR 2 _ 2  are turned off depending on the control signals SEL 2 , TG 2 , DCG 1 _ 2 , and DCG 2 _ 2  having the low level “L”. 
     During the second readout time period ReadT 2  of  FIG.  8   , the transistors ST 2 , TR 1 _ 1 , RT 1 , TR 2 _ 1 , and RT 2  are turned on depending on the control signals SEL 2 , DCG 1 _ 1 , RG 1 , DCG 2 _ 1 , and RG 2  having the high level “H”, and the transistors ST 1 , TT 1 _ 1  to TT 1 _ k , TR 1 _ 2 , and TR 2 _ 2  are turned off depending on the control signals SEL 1 , TG 1 , DCG 1 _ 2 , and DCG 2 _ 2  having the low level “L”. 
     As illustrated in  FIG.  8   , each of the conversion gain control signals DCG 1 _ 1  and DCG 2 _ 1  shortly toggles once between the first readout time period ReadT 1  and the second readout time period ReadT 2  such that the first readout time period ReadT 1  and the second readout time period ReadT 2  are distinguished from each other. 
       FIG.  9    is the timing diagram of control signals supplied to a first pixel and a second pixel of  FIG.  2    when an image sensor of  FIG.  1    operates in a low conversion gain mode. 
     Referring to  FIGS.  1  to  6 C and  9   , when the image sensor  100  operates in a third conversion gain mode (e.g., a low conversion gain (LCG) mode), depending on the mode control signal MODE_ctl indicating that the image sensor  100  operates in the low conversion gain mode, the control signal generator  150  generates the control signals TG 1 , SEL 1 , TG 2 , SEL 2 , DCG 1 _ 1 , DCG 1 _ 2 , RG 1 , DCG 2 _ 1 , DCG 2 _ 2 , and RG 2  having waveforms illustrated in  FIG.  9    and supplies the control signals TG 1 , SEL 1 , TG 2 , SEL 2 , DCG 1 _ 1 , DCG 1 _ 2 , RG 1 , DCG 2 _ 1 , DCG 2 _ 2 , and RG 2  to the first pixel  112  and the second pixel  113 . 
     During the first readout time period ReadT 1  of  FIG.  9   , the transistors ST 1 , TR 1 _ 1 , TR 1 _ 2 , TR 2 _ 1 , and TR 2 _ 2  are turned on depending on the control signals SEL 1 , DCG 1 _ 1 , DCG 1 _ 2 , DCG 2 _ 1 , and DCG 2 _ 2  having the high level “H”, and the transistors ST 2 , TT 2 _ 1  to TT 2 _ k , RT 1 , and RT 2  are turned off depending on the control signals SEL 2 , TG 2 , RG 1 , and RG 2  having the low level “L”. 
     During the second readout time period ReadT 2  of  FIG.  9   , the transistors ST 2 , TR 1 _ 1 , TR 1 _ 2 , TR 2 _ 1 , and TR 2 _ 2  are turned on depending on the control signals SEL 2 , DCG 1 _ 1 , DCG 1 _ 2 , DCG 2 _ 1 , and DCG 2 _ 2  having the high level “H”, and the transistors ST 1 , TT 1 _ 1  to TT 1 _ k , RT 1 , and RT 2  are turned off depending on the control signals SEL 1 , TG 1 , RG 1 , and RG 2  having the low level “L”. 
     As illustrated in  FIG.  9   , each of the reset signals RG 1  and RG 2  shortly toggles once between the first readout time period ReadT 1  and the second readout time period ReadT 2  such that the first readout time period ReadT 1  and the second readout time period ReadT 2  are distinguished from each other. 
     According to embodiments, under the assumption that the number of photoelectric conversion elements PD 1 _ 1  to PD 1 _ k /PD 2 _ 1  to PD 2 _ k  included in each of the pixels  112  and  113  is 4 (i.e., when k=4), when a conversion gain of the low conversion gain mode is defined as LCG (or a third value), a conversion gain of the medium conversion gain mode is defined as MCG (or a second value), and a conversion gain of the high conversion gain mode is defined as HCG (or a first value), the HCG is greater than the MCG, and the MCG is greater than the LCG. 
     According to an embodiment, a ratio of MCG to LCG may be 2 (=MCG/LCG), and a ratio of HCG to LCG may be 4 (=HCG/LCG). 
     According to embodiments, when the number of photoelectric conversion elements PD 1 _ 1  to PD 1 _ k /PD 2 _ 1  to PD 2 _ k  included in each of the pixels  112  and  113  is 8 (i.e., when k=8), the HCG is greater than the MCG, and the MCG is greater than the LCG. 
     According to an embodiment, a ratio of MCG to LCG may be 2 (=MCG/LCG), and a ratio of HCG to LCG may be 8 (=HCG/LCG). Alternatively, a ratio of MCG to LCG may be 4 (=MCG/LCG), and a ratio of HCG to LCG may be 8 (=HCG/LCG). 
     According to embodiments, when the number of photoelectric conversion elements PD 1 _ 1  to PD 1 _ k /PD 2 _ 1  to PD 2 _ k  included in each of the pixels  112  and  113  is 16 (i.e., when k=16), the HCG is greater than the MCG, and the MCG is greater than the LCG. 
     According to an embodiment, in each of the source follower transistors SF 1  and SF 2 , when the LCG is 7.5 μN/e−, the MCG is 30 μN/e−, and the HCG is 120 μN/e−, a ratio of MCG to LCG may be 4 (=MCG/LCG), and a ratio of HCG to LCG may be 16 (=HCG/LCG). 
       FIG.  10    is a block diagram illustrating an implementation example of an image sensor illustrated in  FIG.  1   . 
     Referring to  FIGS.  1  and  10   , an image sensor  100 A includes a first semiconductor chip  210  and a second semiconductor chip  220 . The pixel array  110  may be integrated in the first semiconductor chip  210 , and the readout circuit  120  and the control signal generator  150  may be integrated in the second semiconductor chip  220 . According to embodiments, the image sensor  110  may be integrated in one semiconductor chip. 
       FIG.  11    is a block diagram of an image processing device including an image sensor illustrated in  FIG.  1   . Referring to  FIG.  11   , an image processing device  300  that is also called an imaging device or an image processing system includes a camera module  310 , a processor  320 , and a display device  330 . 
     The image processing device  300  may be used in a computer system, a mobile device, a CCTV system, a wearable computer, or an in-vehicle infotainment system. Examples of the mobile device include a smartphone, a laptop computer, a mobile internet device (MID), an internet of things (IoT) device, a drone, and the like. 
     The image sensor  100  or  100   a  of the camera module  310  photographs a subject by using a lens  312 , generates an image signal corresponding to the photographed subject, and sends the image signal to an image signal processor  314 . The image sensor  110  or  100   a  may be the image sensor  100 A described with reference to  FIG.  10   . 
     Image data processed by the image signal processor  314  may be provided to the processor  320 , and the processor  320  may display an image corresponding to the processed image data through the display device  330 . The processor  320  may be a CPU or application processor, and the display device  330  may be a light-emitting diode (LED) display device, an organic light-emitting diode (OLED) display device, or an active matrix OLED display device (AMOLED) display device. 
     A dynamic range is defined by  201   og  (saturation signal/dark signal). Each of the saturation signal and the dark signal may be a pixel signal output from the pixel “PIXEL” or the pixel array  110 . 
     According to an embodiment of the present disclosure, an image sensor supporting a triple conversion gain may optimize a dynamic range, a signal-to-noise ratio (SNR), and a noise compared to a conventional image sensor. 
     While example embodiments of the present disclosure have been described, it will be apparent to those of ordinary skill in the art that various changes and modifications may be made thereto without departing from the spirit and scope of the present disclosure as set forth in the following claims.