Patent Publication Number: US-8541299-B2

Title: Electrical interconnect forming method

Description:
This application is a divisional application claiming priority to Ser. No. 11/733,840, filed Apr. 11, 2007, now U.S. Pat. No. 7,786,001 issued Aug. 31, 2010. 
    
    
     FIELD OF THE INVENTION 
     The present invention relates to an electrical interconnect structure and associated method for forming an electrical interconnect structure. 
     BACKGROUND OF THE INVENTION 
     Connections between structures are typically unreliable and subject to failure. Accordingly, there exists a need in the art to overcome at least one of the deficiencies and limitations described herein above. 
     SUMMARY OF THE INVENTION 
     The present invention provides method for forming an electrical structure comprising: 
     providing a first substrate comprising a first electrically conductive pad, a second substrate comprising a second electrically conductive pad, a first transfer substrate comprising a first cavity, a first non-solder metallic core structure comprising a spherical shape, and a second non-solder metallic core structure comprising a spherical shape, wherein said first non-solder metallic core structure comprises a diameter that is less than a diameter of said first cavity, and wherein said second non-solder metallic core structure comprises a diameter that is less than a diameter of said first cavity; 
     forming a first solder structure on said first electrically conductive pad; 
     first dispensing said first non-solder metallic core structure into said first cavity within said first transfer substrate; 
     first positioning after said first dispensing, said first transfer substrate such that a first section of a surface of said first non-solder metallic core structure is in contact with said first solder structure; 
     first heating after said first positioning, said first non-solder metallic core structure to a temperature sufficient to cause said first solder structure to melt and form an electrical and mechanical connection between said first section of said surface of said first non-solder metallic core structure and said first electrically conductive pad; 
     removing after said first heating, said first transfer substrate from said non-solder metallic core structure; 
     applying a first underfill encapsulant layer to said first substrate; 
     forming a second solder structure on a second section of said surface of said first non-solder metallic core structure; 
     second dispensing said second non-solder metallic core structure into said first cavity within said first transfer substrate; 
     second positioning after said second dispensing, said first transfer substrate such that a first section of a surface of said second non-solder metallic core structure is in contact with said second solder structure; 
     second heating after said second positioning, said second non-solder metallic core structure to a temperature sufficient to cause said second solder structure to melt and form an electrical and mechanical connection between said second section of said surface of said first non-solder metallic core structure and said first section of said surface of said second non-solder metallic core structure; 
     removing after said second heating, said first transfer substrate from said second non-solder metallic core structure; 
     forming a third solder structure on said second electrically conductive pad; 
     third positioning said first substrate comprising said first non-solder metallic core and said second non-solder metallic core structure such that a second section of said surface of said second non-solder metallic core structure is in contact with said third solder structure; and 
     third heating after said third positioning, said second non-solder metallic core structure to a temperature sufficient to cause said second solder structure solder to melt and form an electrical and mechanical connection between said second section of said surface of said second non-solder metallic core structure and said second electrically conductive pad resulting in an electrical and mechanical connection between said first electrically conductive pad and said second electrically conductive pad. 
     The present invention provides a method for forming an electrical structure comprising: 
     providing a first substrate comprising a first electrically conductive pad and a second electrically conductive pad, a second substrate comprising third electrically conductive pad and a fourth electrically conductive pad, a first transfer substrate comprising a first cavity and a second cavity, and a non-solder metallic core structure comprising a spherical shape, wherein said non-solder metallic core structure comprises a diameter that is less than a diameter of said first cavity; 
     forming a first solder structure on said first electrically conductive pad; 
     forming a second solder structure on said second electrically conductive pad; 
     covering said second cavity with a film having an opening corresponding to said first cavity; 
     dispensing said non-solder metallic core structure into said first cavity within said first transfer substrate; 
     first positioning said first transfer substrate such that a first section of a surface of said non-solder metallic core structure is in contact with said first solder structure and said second cavity is aligned with said second solder structure; 
     first heating said non-solder metallic core structure to a temperature sufficient to cause said first solder structure to melt and form an electrical and mechanical connection between said first section of said surface of said non-solder metallic core structure and said first electrically conductive pad; 
     removing said first transfer substrate from said non-solder metallic core structure; 
     forming a third solder structure on said third electrically conductive pad; 
     forming a fourth solder structure on said fourth electrically conductive pad; 
     second positioning said first substrate comprising said non-solder metallic core structure such that a second section of said surface of said non-solder metallic core structure is in contact with said third solder structure and said second solder structure is in contact with said fourth solder structure; 
     second heating said non-solder metallic core structure to a temperature sufficient to cause said third solder structure solder to melt and form an electrical and mechanical connection between said second section of said surface of said non-solder metallic core structure and said third electrically conductive pad resulting in an electrical and mechanical connection between said first electrically conductive pad and said third electrically conductive pad; and 
     third heating said second solder structure and said fourth solder structure to a temperature sufficient to cause said second solder structure and said fourth solder structure to melt and form an electrical and mechanical connection between said second solder structure and said fourth solder structure resulting in an electrical and mechanical connection between said second electrically conductive pad and said fourth electrically conductive pad, wherein said second heating and said third heating are performed simultaneously. 
     The present invention advantageously provides a simple structure and associated method for forming connections between structures. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  illustrates a cross sectional view of a first electrical structure, in accordance with embodiments of the present invention 
         FIG. 2  depicts a first alternative to  FIG. 1  illustrating a cross sectional view of a second electrical structure, in accordance with embodiments of the present invention. 
         FIG. 3  depicts a first alternative to  FIG. 2  illustrating a cross sectional view of a third electrical structure, in accordance with embodiments of the present invention. 
         FIG. 4  depicts a first alternative to  FIG. 3  illustrating a cross sectional view of a fourth electrical structure, in accordance with embodiments of the present invention. 
         FIG. 5  illustrates a cross sectional view of a fifth electrical structure, in accordance with embodiments of the present invention. 
         FIG. 6  depicts a second alternative to  FIG. 2  illustrating a cross sectional view of a sixth electrical structure, in accordance with embodiments of the present invention. 
         FIG. 7  depicts a second alternative to  FIG. 1  illustrating a cross sectional view of an seventh electrical structure, in accordance with embodiments of the present invention. 
         FIG. 8  depicts a second alternative to  FIG. 3  illustrating a cross sectional view of a eighth electrical structure, in accordance with embodiments of the present invention. 
         FIGS. 9A-9G  illustrate a process for generating the electrical structure of  FIG. 1 , in accordance with embodiments of the present invention. 
         FIGS. 10A-10I  illustrate a process for generating the electrical structures of  FIG. 2 ,  FIG. 3 , and  FIG. 5 , in accordance with embodiments of the present invention. 
         FIGS. 11A-11F  illustrate a process for generating the electrical structure of  FIG. 4 , in accordance with embodiments of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       FIG. 1  illustrates a cross sectional view of an electrical structure  2   a , in accordance with embodiments of the present invention. Electrical structure  2   a  comprises a substrate  1 , a substrate  4 , and a plurality of interconnect structures  5   a . Substrate  1  comprises a plurality of electrically conductive pads  10 . Each pad of electrically conductive pads  10  may be connected to wires or electrical components within substrate  1 . Substrate  4  comprises a plurality of electrically conductive pads  12 . Each pad of electrically conductive pads  12  may be connected to wires or electrical components within substrate  4 . Substrate  1  may comprise, inter alia, a semiconductor device (e.g., an integrated circuit chip, a semiconductor wafer, etc), a chip carrier (organic or inorganic), a printed circuit board, etc. Substrate  4  may comprise, inter alia, a semiconductor device (e.g., an integrated circuit chip, a semiconductor wafer, etc), a chip carrier (organic or inorganic), a printed circuit board, etc. Each interconnect structure  5   a  comprises a non-solder metallic (i.e., does not comprise any solder material) core structure  14  and a solder structure  6   a . Solder structure  6   a  comprises solder. Solder is defined herein as a metal alloy comprising a low melting point (i.e., about 100 degrees Celsius to about 340 degrees Celsius) that is used to join metallic surfaces together without melting the metallic surfaces. Solder structure  6   a  comprises a layer of solder that completely surrounds non-solder metallic core structure  14 . Alternatively (i.e., instead of a layer of solder that completely surrounds non-solder metallic core structure  14 ), solder structure  6   a  could comprise a first portion of solder  9   a  attached to a top side  14   a  of non-solder metallic core structure  14  and a second portion of solder  9   b  attached to a bottom side  14   b  of non-solder metallic core structure  14 . Each non-solder metallic core structure  14  may comprise any conductive metallic material that does not comprise solder including, inter alia, copper, gold, nickel, etc. Each interconnect structure  5   a  electrically and mechanically connects an electrically conductive pad  10  to an electrically conductive pad  12 . Non-solder metallic core structure  14  comprises a cylindrical shape. Solder structure  6   a  may comprise any solder material suitable for flip chip interconnections including, inter alia, an alloy of tin such as SnCu, SnAgCu, SnPb, etc. 
       FIG. 2  depicts a first alternative to  FIG. 1  illustrating a cross-sectional view of an electrical structure  2   b , in accordance with embodiments of the present invention. Electrical structure  2   b  comprises substrate  1 , substrate  4 , and a plurality of interconnect structures  5   b . In contrast with electrical structure  2   a  of  FIG. 1 , electrical structure  2   b  of  FIG. 2  comprises a plurality of interconnect structures  5   b . Each of interconnect structures  5   b  comprises a spherical non-solder (i.e., does not comprise any solder material) metallic core structure  17  and a solder structure  6   b . Each solder structure  6   b  comprises a layer of solder that completely surrounds an associated non-solder metallic core structure  17 . Additionally, each of interconnect structures  5   b  may comprise an additional solder structure  6   d . Each solder structure  6   b  electrically and mechanically connects the associated non-solder metallic core structure  17  to an associated electrically conductive pad  10 . Each solder structure  6   d  electrically and mechanically connects the associated non-solder metallic core structure  17  (i.e., thru solder structure  6   b ) to an associated electrically conductive pad  12 . The aforementioned connections result in each interconnect structure  5   b  electrically and mechanically connecting an electrically conductive pad  10  to an associated electrically conductive pad  12 . Optionally, two different types of solder materials may be used for solder structure  6   b  and solder structure  6   d . For example, solder structure  6   b  may comprise an AuSn solder material and solder structure  6   d  may comprise a solder material such as, inter alia, SnAg, SnCu, SnAgCu, SnBi, etc. For first level area array interconnects, each non-solder metallic core structure  17  may comprise a diameter of about 25 microns to about 150 microns. For second level area array interconnects (e.g., a ball grid array (BGA)), each non-solder metallic core structure  17  may comprise a diameter of about 0.2 mm to about 1.5 mm. Each non-solder metallic core structure  17  may comprise a core of any conductive metallic material that does not comprise solder including, inter alia, copper, gold, nickel, etc. Additionally, each non-solder metallic core structure  17  may comprise an additional layer(s) of non-solder metallic materials (i.e., different from a material comprised by non-solder metallic core structure  17 ) surrounding (e.g., see layer  19  in  FIG. 3 , infra) non-solder metallic core structure  17 . The additional layer(s) may comprise any conductive metallic material including, inter alia, nickel, gold, tin, etc. 
       FIG. 3  depicts a first alternative to  FIG. 2  illustrating a cross sectional view of an electrical structure  2   c , in accordance with embodiments of the present invention. Electrical structure  2   c  comprises substrate  1 , substrate  4 , and a plurality of interconnect structures  5   c . In contrast with electrical structure  2   b  of  FIG. 2 , electrical structure  2   c  of  FIG. 3  comprises a plurality of interconnect structures  5   c . Each of interconnect structures  5   c  comprises a non-solder metallic core structure  17 , a solder structure  6   c , and a solder structure  6   d . Each solder structure  6   c  electrically and mechanically connects an associated non-solder metallic core structure  17  to an associated electrically conductive pad  10 . Each solder structure  6   d  electrically and mechanically connects an associated non-solder metallic core structure  17  to an associated electrically conductive pad  12 . The aforementioned connections result in each interconnect structure  5   c  electrically and mechanically connecting an electrically conductive pad  10  to an associated electrically conductive pad  12 . Optionally, two different types of solder materials may be used for solder structure  6   c  and solder structure  6   d . For example, solder structure  6   c  may comprise an AuSn solder material and solder structure  6   d  may comprise a solder material such as, inter alia, SnAg, SnCu, SnAgCu, SnBi, etc. Each non-solder metallic core structure  17  may comprise a core of any conductive metallic material that does not comprise solder including, inter alia, copper, gold, nickel, etc. Additionally, each non-solder metallic core structure  17  may comprise an additional layer(s)  19  of non-solder metallic materials (i.e., different from a material comprised by non-solder metallic core structure  17 ) surrounding non-solder metallic core structure  17 . Additional layer(s)  19  may comprise any conductive metallic material including, inter alia, nickel, gold, tin, etc. 
       FIG. 4  depicts a first alternative to  FIG. 3  illustrating a cross sectional view of an electrical structure  2   d , in accordance with embodiments of the present invention. Electrical structure  2   d  comprises substrate  1 , substrate  4 , and a plurality of interconnect structures  5   d . In contrast with electrical structure  2   c  of  FIG. 3 , electrical structure  2   d  of  FIG. 4  comprises a plurality of interconnect structures  5   d . Each of interconnect structures  5   d  comprises a non-solder metallic core structure  17   a , a non-solder metallic core structure  17   b , a solder structure  6   c , a solder structure  6   d , a solder structure  6   e . Additionally (i.e., optionally), electrical structure  2   d  comprises an underfill encapsulant layer  25   a  and an underfill encapsulant layer  25   b . Each solder structure  6   e  electrically and mechanically connects a non-solder metallic core structure  17   a  to an associated a non-solder metallic core structure  17   b . Each solder structure  6   c  electrically and mechanically connects a non-solder metallic core structure  17   a  to an associated electrically conductive pad  10 . Each solder structure  6   d  electrically and mechanically connects a non-solder metallic core structure  17   b  to an associated electrically conductive pad  12 . The aforementioned connections result in each interconnect structure  5   d  electrically and mechanically connecting an electrically conductive pad  10  to an associated electrically conductive pad  12 . Optionally, three different types of solder materials may be used for solder structure  6   c , solder structure  6   d , and solder structure  6   e . For example, solder structure  6   c  may comprise an AuSn solder material, solder structure  6   d  may comprise a solder material such as, inter alia, SnAg, SnCu, etc, and solder structure  6   e  may comprise a solder material such as, inter alia, SnAgCu, SnBi, etc. Each non-solder metallic core structure  17   a  and  17   b  may comprise a core of any conductive metallic material that does not comprise solder including, inter alia, copper, gold, nickel, etc. Non-solder metallic core structure  17   a  may comprise a first material (e.g., copper) and non-solder metallic core structure  17   b  may comprise a second material (e.g., gold). Additionally, each non-solder metallic core structure  17   a  and  17   b  may comprise an additional layer(s)  19  of metallic materials (i.e., different from a material comprised by non-solder metallic core structure  17   a  and  17   b ) surrounding non-solder metallic core structure  17   a  and  17   b . Additional layer(s)  19  may comprise any conductive metallic material including, inter alia, nickel, gold, tin, etc. Additionally, non-solder metallic core structure  17   a  may comprise a layer(s)  19  comprising a different material from a layer(s)  19  on non-solder metallic core structure  17   b . Underfill encapsulant layer  25   a  surrounds non-solder metallic core structures  17   a  and is in contact with substrate  1 . Underfill encapsulant layer  25   b  surrounds non-solder metallic core structures  17   b  and is in contact with substrate  4 . Underfill encapsulant layer  25   a  is in contact with underfill encapsulant layer  25   b . Underfill encapsulant layer  25   a  may comprise a first material (e.g., a highly filled silica-epoxy composite adhesive) and underfill encapsulant layer  25   b  may comprise a second and different material (e.g., a lightly filled silica-epoxy composite adhesive). Underfill encapsulant layer  25   a  may comprise a first coefficient of thermal expansion (e.g., comprising a range of about 5-15 ppm/C) that is different (e.g., lower) from a second coefficient of thermal expansion (e.g., comprising a range of about 15.1-40 ppm/C) comprised by encapsulant layer  25   b . Underfill encapsulent layer  25   a  may additionally comprise a filler  25   c  dispersed throughout. 
       FIG. 5  illustrates a cross sectional view of an electrical structure  2   e , in accordance with embodiments of the present invention. Electrical structure  2   e  in  FIG. 5  is a combination of electrical structures  2   b  and  2   c , of  FIGS. 2-3 . In addition to electrical structures  2   b  and  2   c , of  FIGS. 2-3 , electrical structure  2   e  in  FIG. 5  comprises interconnection structures  29  (i.e., comprising solder) electrically and mechanically connecting some of electrically conductive pads  10  to associated electrically conductive pads  12 . Therefore, electrical structure  2   e  uses a combination of interconnect structures  5   b ,  5   c , and  29  to electrically and mechanically connect electrically conductive pads  10  to associated electrically conductive pads  12 . Note that any combination and any configuration of interconnect structures  5   b ,  5   c , and  29  may be used to electrically and mechanically connect electrically conductive pads  10  to associated electrically conductive pads  12 . For example, electrical structure  2   e  may comprise only interconnect structures  5   c  and  29  to electrically and mechanically connect electrically conductive pads  10  to associated electrically conductive pads  12 . There may be any number or ratio of interconnect structures  5   b ,  5   c , and  29  arranged in any pattern (e.g., interconnect structures  5   b  and  29 : may be placed such that they are in alternating positions, may be placed in random positions, may be placed such that there is one interconnect structure  5   b  for every three interconnect structures  29 , may be placed such that interconnect structures  5   b  provide power and ground connections only and interconnect structures  29  are placed for signal interconnects only, etc). Additionally, electrical structure  2   e  may comprise an underfill encapsulant layer  31  between substrate  1  and substrate  4 . 
       FIG. 6  depicts a second alternative to  FIG. 2  illustrating a cross sectional view of an electrical structure  2   f , in accordance with embodiments of the present invention. In contrast with electrical structure  2   b  of  FIG. 2 , electrical structure  2   f  of  FIG. 6  comprises an underfill encapsulant layer  32   a  between substrate  1  and substrate  4 . In the case in which substrate  1  is a semiconductor device or a silicon wafer, underfill encapsulant layer  32   a  may alternately comprise an underfill layer applied prior to chip joining or applied on the silicon wafer over the interconnect structures  5   b . Such an underfill layer is defined as a wafer-level underfill. 
       FIG. 7  depicts a second alternative to  FIG. 1  illustrating a cross sectional view of an electrical structure  2   g , in accordance with embodiments of the present invention. In contrast with electrical structure  2   a  of  FIG. 1 , electrical structure  2   g  of  FIG. 7  comprises an underfill encapsulant layer  32   b  between substrate  1  and substrate  4 . In the case in which substrate  1  is a semiconductor device or a silicon wafer, underfill encapsulant layer  32   b  may alternately comprise an underfill layer applied prior to chip joining or applied on the silicon wafer over the interconnect structures  5   a . Such an underfill layer is defined as a wafer-level underfill 
       FIG. 8  depicts a second alternative to  FIG. 3  illustrating a cross sectional view of an electrical structure  2   h , in accordance with embodiments of the present invention. In contrast with electrical structure  2   c  of  FIG. 3 , electrical structure  2   h  of  FIG. 8  comprises an underfill encapsulant layer  32   c  between substrate  1  and substrate  4 . In the case in which substrate  1  is a semiconductor device or a silicon wafer, underfill encapsulant layer  32   c  may alternately comprise an underfill layer applied prior to chip joining or applied on the silicon wafer over the interconnect structures  5   c . Such an underfill layer is defined as a wafer-level underfill. 
       FIGS. 9A-9G  illustrate a process for generating electrical structure  2   a  of  FIG. 1 , in accordance with embodiments of the present invention. 
       FIG. 9A  illustrates a cross sectional view of a non-solder metallic layer  37  formed over an insulator layer  35 , in accordance with embodiments of the present invention. Non-solder metallic layer  37  may comprise any non-solder metallic material such as, inter alia, copper, gold, nickel, etc. Insulator layer  35  may comprise any insulator material such as, inter alia, a polymer film (e.g., polyimide), etc. 
       FIG. 9B  illustrates a cross sectional view of the structure of  FIG. 9A  after non-solder metallic interconnect structures  14  have been formed in order to form structure  35   a , in accordance with embodiments of the present invention. Non-solder metallic interconnect structures  14  may be formed by subtractively etching portions of non-solder metallic layer  37  (i.e., of  FIG. 1 ) in order to form non-solder metallic interconnect structures  14 . Non-solder metallic interconnect structures  14  may comprise various widths, heights, and height-to-width aspect ratios. A subtractive etching process comprises: 
     1. Applying and patterning a protective photo resist layer 
     2. Using chemical solutions to etch or dissolve unprotected regions of copper. 
     3. Stripping off the protective photo resist layer. 
     Each of non-solder metallic interconnect structures  14  may comprise a width of about 10 microns to about 100 microns and comprise a height-to-width aspect ratio of about 1:1 to about 5:1. 
       FIG. 9C  illustrates a cross sectional view of substrate  1  of  FIG. 1  after first portions of solder  9   a  (i.e., solder structures) have been formed thereby forming a structure  35   b , in accordance with embodiments of the present invention. For example, substrate  1  may comprise a silicon device wafer that is prepared with electrically conductive interconnect pads (e.g., see pads  10  of  FIG. 1 ). Solder is applied to the pads in order to form first portions of solder  9   a . Any method may be used to apply the solder to the electrically conductive interconnect pads, including, inter alia, applying solder as an injection molded solder. 
       FIG. 9D  illustrates a cross sectional view of structure  35   a  of  FIG. 9B  of  FIG. 1  aligned with structure  35   b  of  FIG. 9C , in accordance with embodiments of the present invention. Non-solder metallic interconnect structures  14  are aligned to associated first portions of solder  9   a . The alignment process may comprise using commercially available bonding tools that use optical sensing of fiducials on substrate  1  and insulator layer  35 . 
       FIG. 9E  illustrates a cross sectional view of structure  35   c  formed after the alignment process described with respect to  FIG. 9D , in accordance with embodiments of the present invention. In  FIG. 9E , a transfer process has been performed by heating the aligned assembly of  FIG. 9D  to a temperature above a melting point (i.e., with assistance of a fluxing agent or a fluxing atmosphere) of the solder used to form first portions of solder  9   a . Optionally, the transfer process may be assisted by a laser release process applied through a backside  21  of insulator layer  35 . Light energy generated by a laser is absorbed by insulator layer  35  at an interface  23  to non-solder metallic interconnect structures  14  causes adhesion (i.e., at interface  23 ) to be degraded hereby releasing non-solder metallic interconnect structures  14  from insulator layer  35 . Alternatively, an adhesive (i.e., at interface  23 ) may be degraded and release non-solder metallic interconnect structures  14  from insulator layer  35  during the solder melting process described, supra. 
       FIG. 9F  illustrates a cross sectional view of a process for aligning structure  35   c  of  FIG. 9E  with a structure  35   d , in accordance with embodiments of the present invention. Structure  35   d  comprises a substrate  4  comprising formed solder structures  9   b  (i.e., formed by a similar process to the process performed with respect to  FIG. 9C ). 
       FIG. 9G  illustrates a completed electrical structure  35   e  similar to electrical structure  2   a  of  FIG. 1 , in accordance with embodiments of the present invention. An assembly of substrate  1  to substrate  4  through non-solder metallic interconnect structures  14 , solder structures  9   a , and solder structures  9   b  is carried out by raising a temperature of non-solder metallic interconnect structures  14  above a melting temperature of solder structures  9   b  with the assistance of a fluxing agent or fluxing atmosphere. Optionally, non-solder metallic interconnect structures  14 , solder structures  9   a , and solder structures  9   b  may be encapsulated with polymeric material by capillary underfill following the joining of substrate  1  to substrate  4 . Alternatively, an underfill encapsulant may be applied at wafer-level or on singulated devices prior to the joining of substrate  1  to substrate  4 . 
       FIGS. 10A-10I  illustrate a process for generating electrical structure  2   b  of  FIG. 2 , electrical structure  2   c  of  FIG. 3 , and electrical structure  2   e  of  FIG. 5 , in accordance with embodiments of the present invention. Note that although  FIGS. 10A-10I  illustrate a process for applying solder as an injection molded solder, any solder applying process may be used. 
       FIG. 10A  illustrates a cross sectional view of a structure  39   a  comprising a filled glass or silicon mold  40  positioned over substrate  1  (i.e., from  FIGS. 2 and 3 ), in accordance with embodiments of the present invention. Glass or silicon mold  40  is filled with solder that when released from glass mold will become solder structures  6   b  of  FIG. 2 ,  6   c  of  FIG. 3 , and  6   b  of  FIG. 5 . The solder may comprise any solder suitable for flip chip interconnects including, inter alia, an alloy of tin such as, inter alia, AuSn, SnCu, SnAgCu, etc. The solder may comprise a high melting point so that solder structures  6   b ,  6   c  will not melt during a subsequent step. 
       FIG. 10B  illustrates a cross sectional view of a structure of  39   b  formed from structure  39   a  of  FIG. 10A , in accordance with embodiments of the present invention. In  FIG. 10B , the solder has been released from glass or silicon mold  40  to form solder structures  6   c  attached to electrically conductive pads  10  on substrate  1 . 
       FIG. 10C  illustrates a cross sectional view of a transfer substrate  43  comprising a plurality of non-solder metallic core structures  17 , in accordance with embodiments of the present invention. Non-solder metallic core structures  17  are positioned in cavities  43   a  within transfer substrate  43 . Each of cavities  43   a  comprises similar dimensions as non-solder metallic core structures  17  with cavity positions corresponding to positions of associated solder structures  6   c  on electrically conductive pads  10 . Transfer substrate  43  may comprise, inter alia, glass, silicon, or any material used for injection molded solder molds, etc. Non-solder metallic core structures  17  may be dispensed into cavities  43   a  as a slurry in a solvent such as, inter alia, water isopropanol, etc. The solvent may comprise an appropriate amount of flux to assist in the wetting of solder structures  6   c  to non-solder metallic core structures  17 . In a case in which non-solder metallic core structures  17  are coated with gold, flux is not necessary. Optionally, the solvent may additionally comprise a small amount of thermally degradable polymeric adhesive to aid in retaining non-solder metallic core structures  17  in cavities  43   a . Cavities  43   a  are fabricated to a size that will only cause one non-solder metallic core structure  17  to fall into it during a dispensing of non-solder metallic core structures  17 . 
       FIG. 10D  illustrates a cross sectional view of transfer substrate  43  of  FIG. 10C  comprising a selected plurality of non-solder metallic core structures  17 , in accordance with embodiments of the present invention. As an optional feature of the process, transfer substrate  43  may be covered with a polymeric film (i.e., not shown) with through-holes matching some pre-determined fraction of cavities  43   a . The pre-determined fraction of cavities  43   a  covered by the polymeric film will be prevented from receiving non-solder metallic core structures  17 . The pre-determined fraction of cavities  43   a  allows a packaging design engineer to selectively place non-solder metallic core structures  17 . Additionally, solder interconnects  29  may be selectively placed in some of cavities  43   a  (i.e., instead of select non-solder metallic core structures  17 ) for placement on substrate  1 . In this option, transfer substrate  43  may be couvered with a second polymeric film (i.e., not shown) with through-holes matching the remaining cavities  43   a . The cavities  43   a  covered by the polymeric film will be prevented from receiving solder interconnects  29 . 
       FIG. 10E  illustrates a cross sectional view of substrate  1  of  FIG. 10B  positioned over transfer substrate  43  comprising non-solder metallic core structures  17 , in accordance with embodiments of the present invention. Substrate  1  of  FIG. 10B  is positioned over transfer substrate  43  comprising non-solder metallic core structures  17  in order to transfer non-solder metallic core structures  17  to substrate  1 . 
       FIG. 10F  illustrates a cross sectional view of substrate  1  after non-solder metallic core structures  17  have been released from transfer substrate  43  and connected to solder structures  6   b , in accordance with embodiments of the present invention. In  FIG. 10F , solder structures  6   b  completely surround non-solder metallic core structures  17 . 
       FIG. 10G  depicts an alternative to  FIG. 10F  illustrating a cross sectional view of a structure  39   c  comprising substrate  1  after non-solder metallic core structures  17  have been released from transfer substrate  43  and connected to solder structures  6   c , in accordance with embodiments of the present invention. In  FIG. 10G , solder structures  6   c  partially surround non-solder metallic core structures  17 . 
       FIG. 10H  illustrates a cross sectional view of substrate  1  positioned over substrate  4 , in accordance with embodiments of the present invention. Substrate  1  is connected to substrate  4  in order to form electrical structure  2   b  of  FIG. 2 . 
       FIG. 10I  illustrates an alternative cross sectional view of substrate  1  positioned over substrate  4 , in accordance with embodiments of the present invention. In the case in which the option of  FIG. 10D  is used (i.e., comprising solder interconnect structures  29 ), the positioning (not shown) is done similarly as in  FIG. 10I . Substrate  1  is connected to substrate  4  in order to form electrical structure  2   c  of  FIG. 3 . 
       FIGS. 11A-11F  illustrate a process for generating electrical structure  2   d  of  FIG. 4 , in accordance with embodiments of the present invention. 
       FIG. 11A  illustrates structure  39   c  of  FIG. 10G  comprising an underfill layer  25   a , in accordance with embodiments of the present invention. Structure  39   c  in  FIG. 11A  has been formed by the process steps described with reference to  FIGS. 10A-10E . Underfill layer  25   a  may comprise a filler  25   c  to create a low coefficient of thermal expansion (CTE). Underfill layer  25   a  may comprise a coefficient of thermal expansion (CTE) similar to that of substrate  1 . 
       FIG. 11B  illustrates structure  39   c  comprising a glass or silicon mold  40   b  positioned over non-solder metallic core structures  17   a , in accordance with embodiments of the present invention. Glass or silicon mold  40   b  is filled with solder that when released from mold  40   b  will become solder structures  6   e  of  FIG. 4 . The solder may comprise any solder suitable for flip chip interconnects including, inter alia, an alloy of tin such as, inter alia, AuSn, SnCu, SnAgCu, etc. The solder may comprise a high melting point so that solder structures  6   e  will not melt during a subsequent step. 
       FIG. 11C  illustrates a cross sectional view of structure of  39   c  comprising solder structures  6   e  attached to non-solder metallic core structures  17   a , in accordance with embodiments of the present invention. In  FIG. 11C , the solder has been released from glass or silicon mold  40   b  to form solder structures  6   e  attached to non-solder metallic core structures  17   a.    
       FIG. 11D  illustrates a cross sectional view of structure  39   c  of  FIG. 11C  positioned over a transfer substrate  43  comprising non-solder metallic core structures  17   b , in accordance with embodiments of the present invention. Structure  39   c  of  FIG. 11C  is positioned over transfer substrate  43  comprising non-solder metallic core structures  17   b  in order to transfer and connect non-solder metallic core structures  17   b  to non-solder metallic core structures  17   a.    
       FIG. 11E  illustrates a cross sectional view of structure  39   c  of  FIG. 11D  after non-solder metallic core structures  17   b  have been connected to non-solder metallic core structures  17   a , in accordance with embodiments of the present invention. 
       FIG. 11F  illustrates a cross sectional view of structure  39   c  of  FIG. 11E  comprising an underfill layer  25   b  applied over underfill layer  25   a , in accordance with embodiments of the present invention. After underfill layer  25   b  is applied over underfill layer  25   a , substrate  1  is connected to substrate  4  in order to form electrical structure  2   d  of  FIG. 4 . 
     While embodiments of the present invention have been described herein for purposes of illustration, many modifications and changes will become apparent to those skilled in the art. Accordingly, the appended claims are intended to encompass all such modifications and changes as fall within the true spirit and scope of this invention.