Patent Publication Number: US-8536852-B2

Title: Current balance circuit to keep dynamic balance between currents in power passages of power connector

Description:
BACKGROUND 
     1. Technical Field 
     The present disclosure relates to balance circuits and, particularly, to a current balance circuit. 
     2. Description of Related Art 
     In a server, some components need to be connected to a motherboard to receive currents from the motherboard. A power connector connected between the motherboard and a component has many power passages to disperse the current from the motherboard to each power passage. However, the dispersed currents passing through the power passages are unequal. There is a status that some power passages bear too high current, which leads to a service life of the corresponding component being decreased. While some other power passages bear too low current, which leads to a work efficiency of the corresponding component being decreased. 
     BRIEF DESCRIPTION OF THE DRAWING 
     The drawing is a circuit diagram of an exemplary embodiment of a current balance circuit. 
    
    
     DETAILED DESCRIPTION 
     Referring the drawing, an exemplary embodiment of a current balance circuit  1  is connected between a power source  2  and a power connector  3 , to balance currents output by the power source  2  to a plurality of power passages, such as a first power passage  31  and a second power passage  32 , of the power connector  3 . The current balance circuit  1  includes a first current sensor  10 , a second current sensor  11 , a first control module  4 , a second control module  5 , an averager  16 , a first rheostat element such as a first Metal Oxide Semiconductor Field Effect Transistor (MOSFET) Q 1 , and a second rheostat element such as a second MOSFET Q 2 . 
     The first control module  4  includes a first subtracter  12 , a second subtracter  13 , and a first delay element  17 . The second control module  5  includes a third subtracter  14 , a fourth subtracter  15 , and a second delay element  18 . The averager  16  is used to calculate an average value of signals which are input to the average  16 , and output the average value. The first and second delay elements  17  and  18  are used to delay the signals which are input to the first and second delay elements  17  and  18 , and output the delayed signals. The first and second MOSFETs Q 1  and Q 2  have current conduction ability for the currents passing through the first and second MOSFETs Q 1  and Q 2 , and can be controlled by a voltage at gates of the first and second MOSFETs Q 1  and Q 2 . When the voltage at the gate of each of the first and second MOSFETs Q 1  and Q 2  is increased, the current conduction ability of the first and second MOSFETs Q 1  and Q 2  is enhanced, the currents passing through the first and second MOSFETs Q 1  and Q 2  are increased. When the voltage at the gate of each of the first and second MOSFETs Q 1  and Q 2  is decreased, the current conduction ability of the first and second MOSFETs Q 1  and Q 2  is weaken, the currents passing through the first and second MOSFETs Q 1  and Q 2  are decreased. 
     The first current sensor  10  is connected to the power source  2  to receive a first current I 1  output by the power source  2 , and convert the first current I 1  into a first voltage V 1 . The second current sensor  11  is connected to the power source  2  to receive a second current I 2  output by the power source  2 , and convert the second current I 2  into a second voltage V 2 . The averager  16  is connected to the first and second current sensors  10  and  11  to receive the first and second voltages V 1  and V 2 , and calculate an average voltage V 0  of the first and second voltages V 1  and V 2 . The averager  16  is also connected to first input terminals of the first and third subtracters  12  and  14  to output the average voltage V 0  to the first input terminals of the first and third subtracters  12  and  14 . A second input terminal of the first subtracter  12  is connected to the first current sensor  10  to receive the first voltage V 1 . An output terminal of the first subtracter  12  is connected to a first input terminal of the second subtracter  13 . An output terminal of the second subtracter  13  is connected to a gate (functioning as a control terminal of the first rheostat element) of the first MOSFET Q 1 , to output a first control signal such as a first control voltage to control the current conduction ability of the first MOSFET Q 1 . 
     The first delay element  17  is connected between the output terminal and a second input terminal of the second subtracter  13  to delay the first control voltage output by the second subtracter  13 , and output the delayed first control voltage to the second input terminal of the second subtracter  13 . A drain (functioning as a first terminal of the first rheostat element) of the first MOSFET Q 1  is connected to the first power passage  31 . A source S (functioning as a second terminal of the first rheostat) of the first MOSFET Q 1  is connected to the power source  2  via the first current sensor  10 , to receive the first current I 1  output by the power source  2 . 
     A second input terminal of the third subtracter  14  is connected to the second current sensor  11  to receive the second voltage V 2 . An output terminal of the third subtracter  14  is connected to a first input terminal of the fourth subtracter  15 . An output terminal of the fourth subtracter  15  is connected to the gate (functioning as a control terminal of the second rheostat element) of the second MOSFET Q 2 , to output a second control signal such as a second control voltage to control the current conduction ability of the second MOSFET Q 2 . The second delay element is connected between the output terminal and a second input terminal of the fourth subtracter  15 , to delay the second control voltage output by the fourth subtracter  15 , and output the delayed second control signal to the second input terminal of the fourth subtracter  15 . The drain (functioning as a first terminal of the second rheostat element) of the second MOSFET Q 2  is connected to the second power passage  32 . A source S (functioning as a second terminal of the second rheostat) of the second MOSFET Q 2  is connected to the power source  2  via the second current sensor  10  to receive the second current I 2  output by the power source  2 . 
     In the embodiment, the first and second current sensors  10  and  11  can convert the first and second currents I 1  and I 2  into the first and second voltage V 1  and V 2 , respectively, and at the same time directly output the first and second currents I 1  and I 2  received from the power source  2  to the sources S of the first and second MOSFETs Q 1  and Q 2 . In other embodiments, the sources S of the first and second MOSFETs Q 1  and Q 2  can be directly connected to the power source  2  to receive the corresponding first and second currents I 1  and I 2 . 
     The first subtracter  12  includes an amplifier U 1  and resistors R 1 -R 4 . The second subtracter  13  includes an amplifier U 2  and resistors R 5 -R 8 . The third subtracter  14  includes an amplifier U 3  and resistors R 9 -R 12 . The fourth subtracter  15  includes an amplifier U 4  and resistors R 13 -R 16 . A non-inverting terminal of the amplifier U 1  is connected to a first terminal of the resistor R 1 , and is grounded via the resistor R 3 . A second terminal of the resistor R 1  functions as the second input terminal of the first subtracter  12 . An inverting terminal of the amplifier U 1  is connected to a first terminal of the resistor R 2 , and connected to an output terminal (the output terminal of the first subtracter  12 ) of the amplifier U 1  via the resistor R 4 . A second terminal of the resistor R 2  functions as the first input terminal of the first subtracter  12 . A non-inverting terminal of the amplifier U 2  is connected a first terminal of the resistor R 6 , and is grounded via the resistor R 8 . A second terminal of the resistor R 6  functions as the second input terminal of the second subtracter  13 . An inverting terminal of the amplifier U 2  is connected to a first terminal of the resistor R 5 , and connected to an output terminal (the output terminal of the second subtracter  13 ) of the amplifier U 2  via the resistor R 7 . A second terminal of the resistor R 5  functions as the first input terminal of the second subtracter  13 . 
     A non-inverting terminal of the amplifier U 3  is connected to a first terminal of the resistor R 10 , and is grounded via the resistor R 12 . A second terminal of the resistor R 10  functions as the second input terminal of the third subtracter  14 . An inverting terminal of the amplifier U 3  is connected to the a first terminal of the resistor R 9 , and connected to an output terminal (the output terminal of the third subtracter  14 ) of the amplifier U 3  via the resistor R 11 . A second terminal of the resistor R 9  functions as the first input terminal of the third subtracter  14 . A non-inverting terminal of the amplifier U 4  is connected to a first terminal of the resistor R 13 , and is grounded via the resistor R 15 . A second terminal of the resistor R 13  functions as the second input terminal of the fourth subtracter  15 . An inverting terminal of the amplifier U 4  is connected to a first terminal of the resistor R 14 , and connected to an output terminal (the output terminal of the fourth subtracter  15 ) of the amplifier U 4  via the resistor R 16 . A second terminal of the resistor R 14  functions as the first input terminal of the fourth subtracter  15 . 
     In the embodiment, resistances of the resistors R 1 -R 4  are equal. Resistances of the resistors R 9 -R 12  are equal. Resistances of the resistors R 5  and R 7  are equal. Resistances of the resistors R 14  and R 16  are equal. In other embodiments, the resistances of the resistors R 1 -R 16  can be changed according to need. The rheostat elements Q 1  and Q 2  can be other elements, such as transistors. 
     When the power source  2  is working, the power source  2  outputs the first current I 1  to the first current sensor  10 , and outputs the second current I 2  to the second current sensor  11 . The first current sensor  10  converts the first current I 1  into the first voltage V 1 , outputs the first voltage V 1  to the averager  16  and the second input terminal of the first subtracter  12 , and outputs the first current I 1  to the first MOSFET Q 1 . The second current sensor  11  converts the second current I 2  into the second voltage V 2 , and outputs the second voltage V 2  to the averager  16  and the second input terminal of the third subtracter  14 . Wherein I 1 /I 2 =V 1 /V 2 . The averager  16  calculates the average voltage V 0  according to the received first and second voltages V 1  and V 2 , namely, V 0 =(V 1 +V 2 )/2. The averager  16  outputs the average voltage V 0  to the first input terminals of the first and third subtracters  12  and  14 . The first subtracter  12  subtracts the average voltage V 0  from the first voltage V 1 , to obtain a voltage Vout 1 =V 1 −V 0 . The first subtracter  12  outputs the voltage Vout 1  to the first input terminal of the second subtracter  13 . The second subtracter  13  subtracts the voltage Vout 1  from a voltage Vk 1 _ 1  at the second input terminal of the second subtracter  13 , to obtain a control voltage Vk 1 =P 1 *Vk 1 _ 1 −(V 1 −V 0 ), where P 1 =R 8 /(R 8 +R 6 ). The voltage Vk 1 _ 1  is obtained via the first delay element  17  delaying the control voltage Vk 1  output by the second subtracter  13  last time. 
     Similarly, the third subtracter  14  subtracts the average voltage V 0  from the second voltage V 2 , to obtain a voltage Vout 2 =V 2 −V 0 . The third subtracter  14  outputs the voltage Vout 2  to the first input terminal of the fourth subtracter  15 . The fourth subtracter  15  subtracts the voltage Vout 2  from a voltage Vk 2 _ 1  at the second input terminal of the fourth subtracter  15 , to obtain a control voltage Vk 2 =P 2 *Vk 2 _ 1 −(V 2 −V 0 ), where P 2 =R 15 /(R 15 +R 13 ). The voltage Vk 2 _ 1  is obtained via the second delay element  18  delaying the control voltage Vk 2  output by the fifth subtracter  15  last time. 
     When the first current I 1  output by the power source  2  is greater than the second current I 2  output by the power source  2 , the first voltage V 1  output by the first current sensor  10  is greater than the second voltage V 2  output by the second current sensor  11 , namely, (V 1 −V 0 )&gt;0, (V 2 −V 0 )&lt;0. The control voltage P 1 *Vk 1 _ 1 −(V 1 −V 0 ) output by the second subtracter  13  to the gate of the first MOSFET Q 1  is gradually decreased according to (V 1 −V 0 )&gt;0. The current conduction ability of the first MOSFET Q 1  is weaken. The first current I 1  is decreased. The control voltage P 2 *Vk 2 _ 1 −(V 2 −V 0 ) output by the fourth subtracter  15  to the gate of the second MOSFET Q 2  is gradually increased according to (V 2 −V 0 )&lt;0. The current conduction ability of the second MOSFET Q 2  is increased. The second current I 2  is increased. Therefore, a difference of currents passing through the first and second power passages  31  and  32  is decreased. The first current I 1  will be equal to the second current I 2 . When the first current I 1  is equal to the second current I 2 , namely, I 1 =I 2 , the first voltage V 1  is equal to the second voltage V 2 , and the average voltage V 0  is equal to each of the first and the second voltages V 1  and V 2 , namely, V 0 =V 1 =V 2 . The second subtracter  13  outputs the control voltage Vk 1 =P*Vk 1 _ 1 , the fourth subtracter  15  outputs the control voltage Vk 2 =P*Vk 1 _ 1 . Owing to the control voltage Vk 1 _ 1  is not equal to the control voltage Vk 2 _ 1 , the current conduction ability of the first and second MOSFETs Q 1  and Q 2  are different. The first current I 1  becomes unequal to the second current I 2 . The current balance circuit  1  adjusts the first and second currents I 1  and I 2  again, to make the first and second currents I 1  and I 2  keep a dynamic balance. 
     When the first current I 1  output by the power source  2  is less than the second current I 2  output by the power source  2 , the work process of balancing the first current I 1  and the second current I 2  now is same to the above-mentioned balancing of the first current I 1  and the second current I 2  when the first current I 1  is greater than the second current I 2 . Therefore, the work process of balancing the first current I 1  and the second current I 2  is not described detailed. The current balance circuit  1  decreases the current difference between the first and second currents I 1  and I 2  output by the power source  2 , to make the first current I 1  substantially equal to the second current I 2 , thereby keeping a current dynamic balance. In this embodiment, the absoluteness balance of the first and second currents I 1  and I 2  is transient. 
     In other embodiments, the power source  2  can correspond to a plurality of power connectors. Each of the plurality of power connectors corresponds to one current balance circuit  1 . The current balance circuit  1  can includes a plurality of current sensors. Each of the plurality of current sensors corresponds to one power passage of the corresponding power connector. 
     It is to be understood, however, that even though numerous characteristics and advantages of the present disclosure have been set forth in the foregoing description, together with details of the structure and function of the disclosure, the disclosure is illustrative only, and changes may be made in details, especially in matters of shape, size, and arrangement of parts within the principles of the disclosure to the full extent indicated by the broad general meaning of the terms in which the appended claims are expressed.