Patent Publication Number: US-3878380-A

Title: Exponent indicating system

Description:
United States Patent [191 Tsuiki 1 Apr. 15, 1975 [54] EXPONENT INDICATING SYSTEM 3,380,031 4/1968 Clayton et a1. 340/ 172.5 I 3,492,656 l/l970 Hildebrandt 340/1725 [75] Inventor: Takao TSlllkl, Tokyo, Japan 3,691,358 9/1972 Angelor et a1. 235/159 73 Assigneez Hitachi, Ltd Tokyo Japan 3,760,171 9/1973 An Wang et a1 235/156 [22] Filed: 1973 Primary Examiner-Malcolm A. Morrison [21] Appl. No.: 403,442 Assistant Examiner-David H. Malzahn Attorney, Agent, or Firm-Craig &amp; Antonelli [30] Foreign Application Priority Data Oct. 4, 1972 Japan 47-99044 [57] ABSTRACT An exponent indicating system for use in the display 52 us. c1. 235/152; 340/324 R of an electronic calculator or the lik hich om- 51 Int. Cl. G06f 3/14 prises a decimal point register having memory Places [58] Field f S h 235/156 159 160 164 in excess of the effective indication or calculation 235/152; 340/1725, 324 R places of the display. Using the excessive places, an exponent is indicated so as to show the approximate [56] R f n Ci d figures of a number having more places than the effectiVe indication 0r calculation places.  
 3,358,125 12/1967 Rinaldi 235/160 X 16 Claims, 5 Drawing Figures 1 i I I I I I l l 1 1111111111511 1 A RG1 DECIMAL POINT REGISTER WI DRd DRc DECIMAL POINT 891% DRIVER CKT CKT ---Pd rPc l 1 l l l 8 5C} I il I {I 1I !Ii B $l- I I I i .1 &#39;U CI&#39;U C I DISPLAY Z L i 1L1 {L l 1 v c 2 l 1 l 1 1 1 1 1 l l I s5 51 s: 1 1 1 1 1, 1 1 P0 P7 P6 P5 P4 P3 P2 P1 PATENTEDAPR 1 5 I975 SHEET 1 BF 5 FIG. la  
  f 5 Gd RGI DECIMAL POINT REGISTER COMMA DRIVER CKT DECIMAL POINT DRIVER CKT FIG. lb  
  2 DI D W 1 Um L5 0 I. 1.. R I D 7 H H 1 Y5 O N Y5 I I0 4 1C P 4 0 .1  
  n5 P ?l Y3 lion.&#34; 1 T2 I WC P 8 DJ IoP PATENTEUAPR 1 519. 5  
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 P IIIIIIIIIIIllIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIHIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIHI IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII BTI 8T4 II II II II II II H II II II II II II II II II II II II II II II II II II II DTI 1 FL FL DTa Fl I L F&#39;I BT81 r| r1 WP I I TH L I 4 DP I I I I I I I I I I I I I I I I I I I I I I I I I I EXPONENT INDICATING SYSTEM BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an indicating system for an electronic calculator, etc., and more particularly to an exponent indicating system therefor.  
 2. Description of the Prior Art In the conventional electronic desk calculators, when a calculated result or a set number exceeds the number of effective indication places or the number of effective calculation places, it is indicated as an error or overflow. This is a very undesirable condition.  
 SUMMARY OF THE INVENTION The present invention has been made with a view toward improving the situation of the prior art, and has its object in making it possible to indicate the approximate figures of a number whose number of places is larger than the number of effective indication places or effective calculation places.  
  In accordance with the present invention, there is provided an exponent indicating system which comprises a decimal point register storing the position of the decimal point of a calculated result or a set number. an exponent being indicated in conformity with the contents of the decimal point register when they reach a predetermined value.  
 BRIEF DESCRIPTION OF THE DRAWINGS FIG. la is a schematic block diagram of one embodiment of the present invention;  
  FIG. lb is a diagram of an alternative display device which may be used with the invention;  
  FIG. 2 is a schematic block diagram of a second embodiment of the present invention;  
  FIG. 3 is a schematic block diagram of a third embodiment of the present invention;  
  FIG. 4 is a schematic block diagram of a fourth embodiment of the present invention; and  
  FIG. 5 is a waveform diagram illustrating various waveforms which appear in the circuits of the other figures.  
  among the illustrated embodiments, the circuits in FIGS. la and lb indicate an exponent in the form of the position of a comma and in the form of a digit, respectively; the circuit in FIG. 2 indicates an exponent in the form of the number of commas; the circuit in FIG. 3 indicates an exponent under the condition in which a decimal point is fixed to the uppermost place; and the circuit in FIG. 4 indicates round numbers under the condition in which an exponent is fixed to 8&#34; (signifyingXlO&#34;) and a decimal point is made floating.  
 PREFERRED EMBODIMENTS OF THE INVENTION of the effective calculation or indication places. For example, assuming the number of effective calculation or indication places to be eight, the memory capacity of the decimal point register RG,, may correspond to sixteen places. In order to facilitate the explanation. the anterior 8place stage portion of the register R0,, is represented as a register RG while the posterior 8-place stage portion is represented as a register RG The register R6: of the posterior stage portion is one added anew for the indication of an exponent. This mechanism will be clearly understood from the explanation of the operation as given hereinbelow.  
  A Z-input AND gate AG, receives at one of its inputs a decimal point signal stored in the register RG,, and at the other input a timing pulse T, as shown in FIG. 5. The gate AG judges whether the decimal point indica tion or the exponent indication is to be made.  
  A 2-input AND gate AG receives at one ofits inputs the decimal point signal and at the other input the output signal of the AND gate AG A 2-input AND gate AG receives at one of its inputs the decimal point signal and at the other input the output signal of the AND gate AG applied through an inverter IN. The gates AG and AG are employed as control gates which effect the changeover between the decimal point indication and the exponent indication in conformity with the contents of the register RG,,.  
  A display device DP, is made of display tubes, light emitting diodes or the like. Each of eight positions of the display DP, is provided with numeral indicating segments 8 -5 generally forming the shape of the figure 8, a decimal point indicating segment S and a comma indicating segment S for indicating the exponent. The electrodes of these indicating segments have one side thereof commonly connected to a corresponding one of the position driver terminals P -P in each position. On the other side, the electrodes are commonly connected to respective segment driver terminals for each of corresponding segments of the eight positions. Among the segment driver terminals. only a decimal point segment-driving terminal P, and a comma segment-driving terminal P,- are illustrated in the drawing. The position driver terminals P -P are respectively connected to receive switching signals (digit signals) DT DT,.. as shown in FIG. 5.  
  A decimal point driver circuit DR, drives the decimal point segments 5,, in accordance with the decimal point signal which has been received from the AND gate AG Accordingly, the output terminal of the driver circuit DR is connected to the decimal point driver terminal P A comma driver circuit DR drives the comma segments 8, in response to the decimal point signal received from the AND gate AG Therefore, the output terminal of the driver circuit DR is connected to the comma driver terminal P The operation of the indicating circuit thus constructed will now be described.  
  When a number is set or a calculated result is requested, a decimal point signal representative of the position of the decimal point of the number is fed to the foremost stage portion of the register RG,,, and is circulatively stored within the register RG,,. Contents to be stored in the register RG, differ as below, in dependence on whether the integral part of the number falls within eight places or lies beyond eight places. In order to facilitate the explanation, the contents of the decimal point register RG,, will be expressed hereunder throughout the description of any embodiment by reading out successively from the uppermost place the states of the respective places within a reference time immediately before the timing pulse T shifts from the lower level (logic O&#34;) to the upper level (logic l namely, within a time in which the relation of T, DT, (=T,,,&#39;DT,,)=I holds among the timing pulse T the digit signal DT,,, a bit signal BT, and a clock pulse (1),, as shown in FIG. 5.  
  When the integral part is covered within eight places. a predetermined place of the register RG of the anterior stage portion becomes l&#34;, and all the places of the register RG of the posterior stage portion become By way of example, for a number 12.34.5678, the contents of the decimal point register RG,, become 00010000 00000000.  
  When the integral part exceeds eight places, all the places of the register RG of the anterior stage portion become and a predetermined place of the register RG of the posterior stage portion becomes By way of example, for a number 33333333123, the contents of the decimal point register RG,, become 0000000000l00000.&#34; In summary, the binary signal l representing the decimal point appears in the anterior stage register RG for a number whose integral part lies within eight places, while the signal 1&#34; moves rightwards and appears in the posterior stage register RG for a number whose integral part lies beyond eight places. In the latter case, the number of upper eight places is stored in the effective indication places of a numeral register (not shown) for storing numeral parts.  
  The AND gate AG detects by the use of the timing pulse T which of the anterior and posterior stage registers the binary signal 1&#34; representative of the decimal point is contained in. In more detail, if the binary signal l is in the register RG of the posterior stage portion. it will be delivered from the register RG to the AND gate AG in a period in which the timing pulse T, is l On the other hand, if it is in the register RG of the anterior stage portion, it will be delivered to the AND gate AG only during a period in which the timing pulse T,, is For this reason, when the output of the AND gate AG become 1&#34;, it is an indication that the binary signal representing the decimal point is included in the register RG of the posterior stage portion. namely, that the integral part of the set number has more than eight places. In contrast, when the output of the AND gate AG is 0&#34;, it is an indication that the integral part of the number lies within eight places.  
  Whether the decimal point signal stored in the register R6,, is to be fed to the decimal point driver circuit DR or to the comma driver &#39;circuit DR is determined on the basis of the detecting result of the AND gate AG This distribution or changeover is executed by the AND gates A0,, and AG More specifically, in the case where the integral part exceeds the number of effective indication places, that is, where the output of the AND gate AG is 1&#34;, the AND gate AG is enabled and the decimal point signal is fed to the comma driver circuit DR for exponent indication. In case where it falls within the effective indication places, that is, where the output of the AND gate AG is 0&#34;, the AND gate A6 is enabled and the decimal point signal is fed to the decimal point driver circuit DR For example, in the case where the integral part of a number has eleven places (33333333123) exceeding the eight effective indication places by three places, the contents of the decimal point register RG become 00000000 00100000.&#34; The decimal point signal delivered from the register RG,, (in this case, synchronized with the digit signal DT is fed to the comma drivier circuit DR to light the comma indicating segment S, which is in the third place as determined from the uppermost place (in the fifth place as determined from the lowermost place) and having the digit signal DT applied to the electrodes on one side. The approximate figures of the number are indicated as 33333333 in the display DP,. Also in the case where the integral part consists of three places, the decimal point signal synchronized with the digit pulse DT is delivered from the decimal point register RG However, it is fed to the decimal point driver circuit DR, by the AND gate AG,- In this case, the decimal point segment S in the fifth place is lit.  
  With the display device DP, in FIG. 1a, in the case where the integral part exceeds the effective indication places by n places, the exponent indication is performed in such a way that the comma indicating segment in the n-th place, as determined from the uppermost one, is lit. In order to make the reading easier, the comma indicating segments S, may be replaced with separate numerical indicating elements which are located in the respective places, as illustrated in FIG. lb. In this case, when the indication is, for example, 43678245, it is read as expressing 43678245Xl0 FIG. 2 shows another embodiment of the exponent indicating circuit according to the present invention.  
  The exponent indicating circuit in FIG. 2 is constructed by adding OR gates OG OG,,, AND gates AG,-AG,, and registers R6,, and RG to the exponent indicating circuit in FIG. la. It is a circuit for indicating an exponent in the form of a number of commas. That is. in accordance with the exponent indicating circuit in FIG. 2, the exponent n of the round numbers AX I0&#34; is indicated by lighting n commas.  
  Referring to the figure, the i-th OR gate 00, receives as its inputs the output signals of all of the flip-flop circuits from the lowermost place FF, to the i-th place FF, among the flip-flop circuits FF ,FF,,, which constitute the decimal point register of the posterior stage RG For example, the fifth OR gate 0G receives the output mal point signal of sixteen places is just loaded in the decimal point register RG,,, the AND gates AG,AG,, are enabled.  
 The registers RG; and RG store signals fed from the AND gates AG,-AG,,. The output signal of a flip-flop circuit FF in the lowermost place of the register R0, is fed to the comma segment driver circuit DR shown in FIG. la. The output signal of the flip-flop circuit FF, in the lowermost place of the register RG is fed to the decimal point segment driver circuit DR, through the AND gate AG which is controlled by the timing pulse T The posterior stage of the register RG is fed back to the anterior stage of the register RG through an AND gate AG The opening and closing of the feedback loop is controlled by the timing pulse T When the feedback loop is opened, that is, when the timing pulse T becomes 0 to disable the AND gate&#39;AG the contents of the register RG are cleared. The registers R6,, and R6 can also be used as registers for arithmetic control, for example, registers for controlling the progress of multiplication and division. In this case, the AND gates AG AG,, may be disabled during the calculations. In the embodiment. the two registers RG;, and R are connected in cascade, and thus the duty d of the indication is enhanced (d= /s).&#39; In the case where a reduction of the number of circuit elements is more preferable even at some sacrifice 0f the duty d (d=l/l6), only the register RG 3 may be employed in a manner to circulate its contents by means of the AND gate AG Description will now be made of the operation of the exponent indicating circuit thus constructed.  
  The AND gate AG effects essentially the same operation as that of the AND gate AG in FIG. 1. If the binary signal 1&#34; is contained in the decimal point register of the anterior stage portion RG (when the integral part is covered within eight places), it will be supplied from the. register RG to the AND gate AG at the level I&#34; of the timing pulse T Since the AND gate AG is in the enabled state at this time, the binary signal 1 subsequently passes through the AND gate AG and is supplied to the decimal point driver circuit DR On the other hand, if the binary signal l is contained in the decimal point register of the posterior stage portion RG (in the case where the integral part of the number has more than eight places), it will be supplied from the register RG- to the AND gate AG at the level 1&#34; of the timing pulse T namely, at the level 0&#34; of the timing pulse T Since, however, the AND gate AG is in the disabled state at this time, the binary signal 1&#34; cannot pass through the AND gate AG, and is not fed to the decimal point driver circuit DR,,.  
  In summary, the AND gate AG functions to pass the decimal point signal for the integral part within eight places, and to block the decimal point signal for the integral part over eight places. In the former case, a predetermined decimal point segment 8,, is lit. In the latter case, no decimal point segment 8,, is lit.  
  The i-th OR gate 0G, detects when any one of the outputs of the flip-flop circuits of the first to i-th places FF to FF I becomes l In other words, when the output of the flip-flop circuit of the i-th place FF, becomes the the outputs of OR gates 06, to 0G,, become The output signals of flip-flop FF, and the OR gates OG -OG are controlled by the AND gates AG- ,-AG,,, and are fed to the flip-flop circuits FF ,,FF in parallel. The timing at which the AND gates AGF&#39;AGg are enabled corresponds to the time at which the timing pulse T,,-DT,, becomes 1. Accordingly, only when the integral part of the number exceeds eight figures is the signal l fed to some of the flip-flop circuits FFgg-FFae. By way of example, for the integral part of a twelve-figure number (345678443213) which exceeds eight figures by four places, the contents of the decimal point register RG become 00000000 00010000. Then, the signal l is fed to the four flipflop circuits F F -F F That is, the contents of the register RG become 00001 I l 1 from the uppermost place (from FF The signal is fed to the comma driver circuit DR Thus, the IZ-figure number is indiponent 4 is indicated in such a manner that commas in the lower places are lit.  
  If the contents of the register RG are circulated in the opposite d i &#39;eqtion, the twelve-figure number will be indicated as 34567844&#34;. Unlike the case of the circuit in FIG. 2, the exponent 4 is indicated in such manner that commas in the upper places are lit.  
  FIG. 3 shows a fiirther embodiment according to which the exponent indicating circuit in FIG. I is somewhat modified. Herein, an exponent is indicated by one of the exponent indicating elements which are disposed above the respective numera segments forming the shape of the figure 8. When the exponent indication is performed, the position of the decimal point is fixed to the uppermost place.  
  Differences in the exponent indicating circuit in FIG. 3 from that in FIG. 1 principally relate to the additional provision of set preference RS flip-flop circuits FF and FF and AND gate A&#39;G and an OR gate 0G, and that the display element are employed instead of the comma indicating segments S as the exponent indicating elements.  
  The set preference RS flip-flop circuit FF in FIG. 3 is a delay type flip-flop circuit whose writing operation is conducted by a clock pulse (b, shown in FIG. and  
 whose reading operation is conducted by the clock pulse ([2 The set input terminal 5 of the flip-flop circuit FF is connected to receive the output signal of the AND gate AG namely. the signal indicating if the integral part exceeds eight places of the effective indication places. The delay type set preference RS flip-flop circuit FF, whose writing operation is conducted by a timing pulse (word pulse) W shown in FIG. 5, has its set input terminal Sconnected to an output terminal Q of the flip-flop circuit FF The flip-flop circuits FF, and FF, are adapted to be reset by the word pulse W Although detailed explanation of the operation is omitted, these flip-flop circuits store the output signal of the ANDgate AG for fixed periods of time (the period of the pulses dz, as to FF,,,, the period of the pulses W, as to FF on the basis of the standard truth tables of the set preference flip-flop circuits. That is, the flip-flop circuits FF, and FF store an indication if the integral part exceeds the effective indication places. In case where the effective indication places are exceeded, an output I is provided, whereas in the case where they are not exceeded, an output &#34;0&#34; is provided.  
  One of input terminals of the AND gate AG is connected to receive the digit signal DT for lighting the decimal point in the eighth place under the fixed state, while the other control input terminal is connected to receive the output signal of the flip-flop circuit FF To the inputs of the OR gate 0G, there are applied the digit signal DT (fixed point lighting signal) received after the control by the AND gate AG and a floating point lighting signal received after the control by the AND gate AG An output signal of the OR gate OG 10 is fed to the decimal point driver circuit DR A display device DP is rovided with the exponent indicating segment as previously stated. These exponent indicating segments are successively driven from the lowermost place by the digit signals DT,DT,,.  
  The exponent indicating circuit operates as described below.  
  In the case where the integral part of the number falls within eight places forming the effective indication places. the output of the flip-flop circuit FF, is always 0&#34;, and hence the AND gate AG is held disabled. As a consequence, similarly to the circuit in FIG. I, the  
 circuit in FIG. 3 effects only a decimal point indication and does not effect an exponent indication.  
  In the case where the number of figures of the integral part exceeds the number of effective indication places, the output of the flip-flop circuit FF, is always l The AND gate AG, is therefore kept disabled, so that the floating point signal is not fed from the decimal point register RG,, to the decimal point driver circuit DR,,. On the other hand, the AND gate AG is enabled, so that the fixed point signal DT, passes through the AND gate AG and the OR gate OG to be fed to the decimal point driver circuit DR Thus, the decimal point segment in the uppermost place (the eighth place) is fixedly lit. Further, the AND gate AG is also enabled, so that the decimal point signal passes through the AND gate AG to be fed to an exponent driver circuit DR,. Thus, a predetermined exponent indicating element is lit. In this manner, in the case where the integral part exceeds the effective indication places by in places, the m-th exp,onent indicating element as determined from the uppermost place is lit as in FIG. 1. By  
 way of example, a number 45678324283 is indicated as 4.5678324&#34;, and the indication is read as expressing the round number 4.5678324Xl&#39;.  
  FIG. 4 illustrates a still further embodiment of the exponent indicating circuit according to the present invention. With this embodiment, in the case where the integral part exceeds the number of effective indication places. the indication is made with the fixed exponent 8. In correspondence with the number of excessive places. the decimal point moves.  
  The construction of the exponent indicating circuit in FIG. 4 differs from that of the embodiment in FIG. 3, in the following points:  
  1. An indicating element &#39;XlO&#34; is provided. A pin P connected to electrodes of the indicating element on one side is connected to receive a DC voltage or a timing pulse such as a digit signal.  
  2. In order to raise the indication duty of the decimal point segments, the decimal point signal is derived from both a decimal point register of the anterior stage RG, and a decimal point register of the posterior stage RG and is fed to the decimal point driver circuit DR,,.  
  3. The number of places of each of the decimal point registers RG, and RG is increased by 2 for detection of an overflow, counting fraction over 1% as one and disregarding the rest, and so forth. Consequently, in the case where the number of places of the integral part is greater than eight, which forms the number of effective indication places (in the case where the exponent indi cation is performed), the decimal point signal is supplied from the third place of each register to the decimal point driver circuit DR,,. For the same reason, the number of the digit signals differing in phase from one another is increased from 8 to 10 though no illustration is made.  
  The operation of this exponent indicating circuit will now be explained.  
 When the integral part is covered within eight places forming the effective indication places, the output of the flip-flop circuit FF is always 0&#34;, and hence, the exponent driver circuit DR; does not operate and the indicating element X10 is not lit. The AND gate AG is enabled, while the AND gate AG is disabled. Therefore, the decimal point signal is delivered only from the lowermost places of the anterior and posterior stage registers through the OR gate 0G AND gate AG element &#39;X10. At this time the AND gate AG is dis abled, while the AND gate AG is enabled. Therefore, the decimal point signal is delivered from the third places (as reckoned from the lowermost place) of the anterior and posterior stage registers through the OR gate OG AND gate AG and OR gate 0G,; to the decimal point driver circuit DR,,. Thus, a predetermined decimal point segment is lit in correspondence with the number of places in excess of the number of effective indication places. It will be understood that the indication duty d of the decimal point segments is 1/10 in this case (without the OR gates 0G and 06, d=l/20).  
  As stated above, the position at which the decimal point signal is derived from each register is changedover between the lowermost place and the third place as reckoned from the lower-most place in dependence on whether or not the integral part exceeds the effective indication places. The reason for the changeover will be more definitely understood from the following description.  
 0000000000 for the integral part of eight places. The  
 decimal point segment in the first place is thus lit, so that no trouble arises. However, for the integral part exceeding eight places, by way of example, for a number 333333333333 greater than the eight places by four places, the contents of the decimal point register RG becomes 00000000000001000000. Since the signal l is present in the seventh place as reckoned from the lowermost place, the decimal point signal synchronized with the digit signal DT, appears in the lowermost place of the register RG or R0,. Eventually,  
 the decimal point segment in the second place as reckoned from the uppermost one is lit, to indicate the number as 33.333333Xl0 which is smaller by two places than actually should be. Therefore, the decimal point signal in the case of performing the exponent indication is derived two places previously in the embodiment. Accordingly, in the case where the decimal point I register RG is employed as the memory register for only the decimal point and the exponent as in the embodiments of FIGS. 1-3, theOR gate 0G inverter IN,, AND gates AG and AG and OR gate 0G can be dispensed within the exponent indicating circuit in FIG. 4.  
  As described above, in accordance with the present invention, the capacity (the number of memory places) of the decimal point register is made larger than the number of effective calculation places or the number of effective indication places, and the exponent indica- .;.9. tion is effected by utilizingthe.increased places. It is therefore possible that a&#34; number ,wh&#39;ose&#39;.- number..of places is greater than the number of effective indication places or the number of effective calculation places can be indicated: in approximate figures. i  
  Although the present invention has been described in connection with the preferred embodiments. itcan adopt various modified means without being restricted thereto. i  
  For example, an exponent indicating circuit may be constructed by combining the embodiments in FIGS. 1 to 4. For example, the indication duty can be raised in such way that the OR gate OG &#39;etc. in the circuit of FIG. 4 are added to the circuitsiofiFlGS. l and 3.  
  Although, in the embodiments. the decimal point signal not coded is stored in the decimal point register R6, the same object can be similarly accomplished when a decimal point signal coded into binary signals of l, 2, 4. 8 is stored in the register. In this case, accessory circuits, such as a decoder circuit. are required, but the capacity of the whole decimal point register can be reduced. Needless to say, the present invention is also applicable to the display device of a printer. etc.  
 What is claimed is:  
  1. An exponent indicating system for use with a numerical display device having a plurality of display positions. a decimal point indicator element for each position and an exponent indicator element, said system comprising a decimal point shift register having a number of stages which exceeds the number of display positions of said display device for storing the position of a decimal point of a number, an exponent indicator driver circuit connected to said exponent indicator element, first means connected to the output of said register for detecting the relative position of said decimal point with respect to the number of display positions in said display device, and second means connected to said register and said first gating means for actuating said exponent indicator driver circuit in dependence on the position of said decimal point in said number.  
  2. An exponent indicating system as defined in claim 1, wherein said first means includes a first AND gate having one input connected to the output of said register and clock means for applying a periodic clock pulse to a second input of said AND gate, said clock pulse having a duration equal to the shifting time of a number of stages of said register equal to the number of display positions of said display device.  
  3. An exponent indicating system as defined in claim 2, wherein said second means includes a second AND gate having one input connected to the output of said register and a second input connected to the output of said first AND gate, the output of said second AND gate being connected to said exponent indicator driver circuit.  
  4. An exponent indicating system as defined in claim 3, further including a decimal point driver circuit connected to said decimal point indicator elements and wherein said second means further includes a third AND gate having one input connected to the output of said register and an inverter circuit connecting the output of said first AND gate to a second input of said &#39;third AND gate, the output of said third AND gate being connected to said decimal point driver circuit.  
  5. An exponent indicating system as defined in claim 3, wherein said shift register has a number of stages equal to twice the number of display positionsof said display-device.  
  6. An exponent&#39;indicating system as defined in claim 3, whereinsaid first means further includes first and second flip-flops connected in tandem between &#39;theoutput of said first AND gate and the input to said second AND gate.  
  7. An exponent indicating system as defined in claim 6, further including a-de&#39;cimal point-driver circuit connected to said decimal point indicator elements, and wherein said second means further includes a third AND gate having one input connected to the output of said register and an inverter circuit connecting the output of said s&#39;econd&#39;flip-flop to a second input of said third AND gate, the output of said third AND gate being connected to said decimal point driver circuit.  
  8. An exponent indicating system as defined in claim 7, wherein said second means further includes a fourth AND gate having one input connected to the output of said second flip-flop and a second input receiving a timing pulse, and an OR gate having inputs connected to the outputs of said third and fourth AND gates and an output connected to said decimal point driver circuit.  
  9. An exponent indicating system for use with a numerical display device having a plurality of display positions, a decimal point indicator element for each position and an exponent indicator element, said system comprising a decimal point shift register having a number of stages which exceeds the number of display positions of said display device for storing the position of a decimal point of a number, an exponent indicator driver circuit connected to said exponent indicator element. first means connected to the output of said register for detecting the relative position of said decimal point with respect to the number of display positions in said display device. second means connected to said register for actuating said exponent indicator driver circuit in dependence on the position of said decimal point in said number. and a decimal point driver circuit responsive to said first means for actuating said decimal point indicator elements.  
  10. An exponent indicating system as defined in claim 9, wherein said shift register comprises first and second shift register portions connected in tandem and each portion having a number of stages equal to the number of display positions of said display device.  
  11. An exponent indicating system as defined in claim 10, wherein said second means includes a second shift register corresponding to the decimal point shift register, a plurality of OR gates corresponding to the respective stages of said second shift register portion and each having inputs connected to the respective outputs of each stage of said second shift register portion of equal or lower order, and a plurality of AND gates connecting the outputs of the respective OR gates to the inputs to respective stages of said second shift register, the output of said second shift register being 13. An exponent indicating system as defined in claim 12, wherein said second means includes first and second flip-flops connected in tandem between output of said first AND gate and said exponent indicator driver circuit.  
  14. An exponent indicating system as defined in claim 13, wherein said shift register is made up of first and second shift register portions connected in tandem and each having a number of stages exceeding the number of display positions of said display device.  
  15. An exponent indicating system as defined in claim 14, wherein said first means includes a first OR gate having inputs connected to the respective outputs of said shift register positions and&#39;means connecting the output of said first OR gate to said decimal point driver circuit.  
  16. An exponent indicating system as defined in claim 14, wherein said first means further includes a first OR gate having inputs connected to the respective outputs of said shift register portions, a second OR gate having respective inputs connected to intermediate points of said first and second shift register. portions, second and third AND gates having first inputs connected respectively to the outputs of said first and second OR gates, inverter means for applying to a second input of said first OR gate the inverted output of said second flip-flop, a second input of said second OR gate being connected directly to the output of said second flip-flop, and a third OR gate receiving the outputs of said second and third AND gates and having its output connected to said decimal point driver circuit.