Patent Publication Number: US-7719115-B2

Title: Semiconductor integrated circuit including a multi-level interconnect with a diagonal wire

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
   This application is a continuation application of application Ser. No. 11/249,388, filed Oct. 14, 2005, which is based upon and claims the benefit of priority from prior Japanese Patent Application No. P2004-301663, filed on Oct. 15, 2004; the entire contents of which are incorporated herein by reference. 

   BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention relates to a semiconductor integrated circuit, more specifically to a computer automated design system and a computer automated design method for designing a semiconductor integrated circuit including orthogonal wirings and oblique wirings in a multi-level interconnect. 
   2. Description of the Related Art 
   Along with miniaturization of integrated circuits in recent years, problems with crosstalk between adjacent wires have been of concern. Especially in cases of a wire pitch of 90 nm or less, crosstalk is more likely to occur, and various technologies to suppress crosstalk have been examined. 
   The technologies to suppress the occurrence of crosstalk between wires include a multi-level interconnect technology using a diagonal interconnect technology. The diagonal interconnect technology utilizes “diagonal interconnect” with wires extended in directions of 45° and 135° while wires are extended in directions of 0° and 90° in “orthogonal interconnect”. Employing the diagonal interconnect technology, a wire length can be shortened by the square root of double the wire length of the orthogonal interconnect. Therefore, the wiring area can be reduced to 30% and electric power consumption can be decreased, in comparison with the orthogonal interconnect. Since the wiring area is reduced by utilizing the diagonal interconnect technology, a pitch of diagonal wires can be magnified and the design rule can be modified, in comparison with the orthogonal interconnect technology. Accordingly, crosstalk can be reduced. 
   However, in the multi-level interconnect technology using an diagonal interconnect technology currently used in general, a wiring layer where the diagonal routing grid is simply arranged is placed in a layer above a wiring layer where the routing grid of the orthogonal interconnect is placed. Therefore, there is a tendency that grid points of the routing grid of the orthogonal interconnect do not match grid points of the routing grid of the diagonal interconnect. When the grid points do not match each other, in placement of a via hole in a portion where wires intersect at right angle, the via hole cannot be placed at any one of adjacent points of orthogonal interconnect and diagonal interconnect. The via hole must be therefore placed at another position. The problem of displacement of the grid points becomes more obvious with increasing reduction of wire width, and the design process is complicated due to restriction of placement positions of via holes. 
   SUMMARY OF THE INVENTION 
   An aspect of the present invention inheres in a computer automated design system, adapted for designing a multi-level interconnect of a semiconductor integrated circuit, encompassing a subject routing module configured to set a first grid area defined by a first line group and a second line group orthogonal to the first line group and a first diagonal grid area defined by a third line group extending diagonally to the first line group and a fourth line group orthogonal to the third line group in a subject wiring layer assigned as one of wiring layers in the multi-level interconnect, the third and fourth line groups being connected to the first to second line groups, and route a first wire in the first grid area and a first diagonal wire extending diagonally to a longitudinal direction of the first wire in the first diagonal grid area based on the first to fourth line groups; and a next routing module configured to set a second grid area defined by the first and second line groups and a second diagonal grid area defined by the third and fourth line groups in an upper wiring layer assigned on the subject wiring layer in the multi-level interconnect so that the second grid area and second diagonal grid area overlap the first grid area and first diagonal grid area, and route a second wire in the second grid area and a second diagonal wire extending diagonally to a longitudinal direction of the second wire in the second diagonal grid area based on the first to fourth line groups. 
   Another aspect of the present invention inheres in a computer automated design method for designing a multi-level interconnect of a semiconductor integrated circuit, encompassing setting a first grid area defined by a first line group and a second line group orthogonal to the first line group and a first diagonal grid area defined by a third line group extending diagonally to the first line group and a fourth line group orthogonal to the third line group in a subject wiring layer assigned as one of wiring layers in the multi-level interconnect, the third and fourth line groups being connected to the first to second line groups, and route a first wire in the first grid area and a first diagonal wire extending diagonally to a longitudinal direction of the first wire in the first diagonal grid area based on the first to fourth line groups; and setting a second grid area defined by the first and second line groups and a second diagonal grid area defined by the third and fourth line groups in an upper wiring layer assigned on the subject wiring layer in the multi-level interconnect so that the second grid area and second diagonal grid area overlap the first grid area and first diagonal grid area, and route a second wire in the second grid area and a second diagonal wire extending diagonally to a longitudinal direction of the second wire in the second diagonal grid area based on the first to fourth line groups. 
   Still another aspect of the present invention inheres in a semiconductor integrated circuit including a multi-level interconnect, the multi-level interconnect encompassing a subject wiring layer assigned as one of wiring layers implementing the multi-level interconnect, including a subject wire area placing a subject wire extending along a first direction and a subject diagonal wire area placing a subject diagonal wire being connected to the subject wire and extended diagonally to the first direction; a first insulating film on the subject wiring layer; and an upper wiring layer provided on the first insulating film including an upper wire area placing an upper wire extending along the first direction and an upper diagonal wire area placing an upper diagonal wire connected to the upper wire and extended diagonally to the first direction, the upper wire area and the upper diagonal wire area being provided above the subject wire area and the subject diagonal wire area. 

   
     BRIEF DESCRIPTION OF DRAWINGS 
       FIG. 1  is a block diagram illustrating a computer automated design system according to the embodiment of the present invention; 
       FIG. 2A  is a block diagram illustrating a first routing module of the computer automated design system according to the embodiment of the present invention; 
       FIG. 2B  is a block diagram illustrating a (k+1)-th routing module of the computer automated design system according to the embodiment of the present invention; 
       FIG. 3A  is a plan view illustrating a layout of the first layer designed by the computer automated design system according to the first embodiment of the present invention; 
       FIG. 3B  is a plan view illustrating a layout of the first layer designed by the computer automated design system according to the first embodiment of the present invention; 
       FIG. 4A  is a plan view illustrating a layout of the first layer designed by the computer automated design system according to the first embodiment of the present invention; 
       FIG. 4B  is a plan view illustrating a layout of the first layer designed by the computer automated design system according to the first embodiment of the present invention; 
       FIG. 5A  is a plan view illustrating detailed layout of the first diagonal grid area as shown in  FIGS. 3A-4B ; 
       FIG. 5B  is a plan view illustrating detailed layout of the first diagonal grid area as shown in  FIGS. 3A-4B ; 
       FIG. 6  is a schematic diagram illustrating a multi-level interconnect of the semiconductor integrated circuit designed by the computer automated design system according to the embodiment of the present invention; 
       FIG. 7  is a flowchart illustrating a computer automated design method according to the embodiment of the present invention; 
       FIG. 8  is a plan view illustrating a semiconductor integrated circuit designed by the computer automated design method according to the embodiment of the present invention; 
       FIG. 9  is a cross-sectional view taken on line VIIII-VIIII in  FIG. 8 ; 
       FIG. 10  is a cross-sectional view illustrating a method of manufacturing the semiconductor integrated circuit according to the embodiment of the present invention; 
       FIG. 11  is a cross-sectional view illustrating the method of manufacturing the semiconductor integrated circuit according to the embodiment of the present invention; 
       FIG. 12  is a cross-sectional view illustrating the method of manufacturing the semiconductor integrated circuit according to the embodiment of the present invention; 
       FIG. 13  is a cross-sectional view illustrating the method of manufacturing the semiconductor integrated circuit according to the embodiment of the present invention; 
       FIG. 14  is a cross-sectional view taken on line XIV-XIV in  FIG. 15 ; 
       FIG. 15  is a plan view illustrating the method of manufacturing the semiconductor integrated circuit according to the embodiment of the present invention; 
       FIG. 16  is a cross-sectional view illustrating the method of manufacturing the semiconductor integrated circuit; 
       FIG. 17  is a cross-sectional view illustrating the method of manufacturing the semiconductor integrated circuit; 
       FIG. 18  is a cross-sectional view illustrating the method of manufacturing the semiconductor integrated circuit; 
       FIG. 19  is a cross-sectional view illustrating the method of manufacturing the semiconductor integrated circuit; 
       FIG. 20  is a cross-sectional view illustrating the method of manufacturing the semiconductor integrated circuit; 
       FIG. 21  is a cross-sectional view taken on line XXI-XXI in  FIG. 22 ; 
       FIG. 22  is a plan view illustrating the method of manufacturing the semiconductor integrated circuit according to the embodiment of the present invention; 
       FIG. 23  is a cross-sectional view illustrating the method of manufacturing the semiconductor integrated circuit; 
       FIG. 24  is a cross-sectional view illustrating the method of manufacturing the semiconductor integrated circuit; 
       FIG. 25  is a cross-sectional view illustrating the method of manufacturing the semiconductor integrated circuit; 
       FIG. 26  is a cross-sectional view taken on line XXVI-XXVI in FIG.  27 ; 
       FIG. 27  is a plan view illustrating the method of manufacturing the semiconductor integrated circuit according to the embodiment of the present invention; 
       FIG. 28  is a cross-sectional view illustrating the method of manufacturing the semiconductor integrated circuit; 
       FIG. 29  is a cross-sectional view taken on line XXIX-XXIX in  FIG. 30 ; 
       FIG. 30  is a plan view illustrating the method of manufacturing the semiconductor integrated circuit according to the embodiment of the present invention; 
       FIG. 31  is a cross-sectional view illustrating a semiconductor integrated circuit according to the other embodiments of the present invention; 
       FIG. 32  is a cross-sectional view illustrating a semiconductor integrated circuit according to the other embodiments of the present invention; 
       FIG. 33  is a cross-sectional view illustrating a multi-level interconnect in the semiconductor integrated circuit according to the other embodiments of the present invention; 
       FIG. 34  is a cross-sectional view illustrating a multi-level interconnect in the semiconductor integrated circuit according to the other embodiments of the present invention; 
       FIG. 35  is a cross-sectional view illustrating a multi-level interconnect in the semiconductor integrated circuit according to the other embodiments of the present invention; 
       FIG. 36  is a cross-sectional view illustrating a multi-level interconnect in the semiconductor integrated circuit according to the other embodiments of the present invention; 
       FIG. 37  is a schematic diagram illustrating grid areas of the multi-level interconnect in the semiconductor integrated circuit according to the other embodiments of the present invention; 
       FIG. 38  is a schematic diagram illustrating grid areas of the multi-level interconnect in the semiconductor integrated circuit according to the other embodiments of the present invention; 
       FIG. 39  is a plan view illustrating grid areas of the multi-level interconnect in the semiconductor integrated circuit according to the other embodiments of the present invention; 
       FIG. 40  is a schematic view illustrating grid areas of the multi-level interconnect in the semiconductor integrated circuit according to the other embodiments of the present invention; 
       FIG. 41  is a plan view illustrating grid areas of the multi-level interconnect in the semiconductor integrated circuit according to the other embodiments of the present invention; 
       FIG. 42  is a schematic view illustrating grid areas of the multi-level interconnect in the semiconductor integrated circuit according to the other embodiments of the present invention; 
       FIG. 43  is a plan view illustrating grid areas of the multi-level interconnect in the semiconductor integrated circuit according to the other embodiments of the present invention; 
       FIG. 44  is a schematic view illustrating grid areas of the multi-level interconnect in the semiconductor integrated circuit according to the other embodiments of the present invention; 
       FIG. 45  is a plan view illustrating grid areas of the multi-level interconnect in the semiconductor integrated circuit according to the other embodiments of the present invention; 
       FIG. 46  is a plan view illustrating grid areas of the multi-level interconnect in the semiconductor integrated circuit according to the other embodiments of the present invention; 
       FIG. 47  is a plan view illustrating grid areas of the multi-level interconnect in the semiconductor integrated circuit according to the other embodiments of the present invention; and 
       FIG. 48  is a schematic view illustrating grid areas of the multi-level interconnect in the semiconductor integrated circuit according to the other embodiments of the present invention. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
   Various embodiments of the present invention will be described with reference to the accompanying drawings. It is to be noted that the same or similar reference numerals are applied to the same or similar parts and elements throughout the drawings, and the description of the same or similar parts and elements will be omitted or simplified. In the following descriptions, numerous details are set forth such as specific signal values, etc. to provide a thorough understanding of the present invention. However, it will be obvious to those skilled in the art that the present invention may be practiced without such specific details. 
   —Computer Automated Design System— 
   As shown in  FIG. 1 , a computer automated design system according to the embodiment of the present invention includes an input unit  4  which inputs information such as data or instructions from an operator, a central processing unit (CPU)  1 , which executes various arithmetic operations for a layout design and the like, an output unit  5  which outputs a layout result and the like, a data memory  2  which stores design information necessary for the layout design of the semiconductor integrated circuit, and a program memory  6  which stores a layout program of the semiconductor integrated circuit, and the like. 
   The CPU  1  arranges a logic cell, wires and the like on a chip region set in a memory space of the design system. The CPU  1  includes a information extraction module  10 , a first routing module  14 , a second routing module  15 , . . . , a k-th routing module  16 , and an (k+1)-th routing module  17 , . . . . 
   The information extraction module  10  extracts placement information of circuit elements such as cells, macrocells, and megacells placed in the chip area and information necessary to place wires such as power wires, clock wires, and signal wires in each wiring layer from the data memory  2 . 
   The first routing module  14  routes a first wiring layer based on placement information of cells placed in the chip area. As shown in  FIG. 2A , the first routing module  14  includes a chip area information extraction module  141 , a first grid area setting module  142 , a first diagonal grid area setting module  143 , a first routing module  144 , a first replacement area setting module  145 , and a first rerouting module  146 . 
   The chip area information extraction module  141  extracts placement information of circuit elements (macrocells), such as RAM and ROM, which are placed in the chip area. The first grid area setting module  142  reads from the data memory  2  the placement information of circuit elements extracted by the chip area information extraction module  141 , a primary direction of interconnect and routing conditions set in advance, and the like. The first grid area setting module  142  then sets a first grid area in a first wiring layer. 
   For example, as shown in  FIG. 3A , the first grid area  401   a  is composed of a plurality of rectangular areas defined by first grid lines (a first line group) X1, X2, X3, . . . , Xp−1, Xp, Xp+1, . . . and second grid lines (a second line group) Y1, Y2, Y3, . . . , Yp−1, Yp, Yp+1, . . . , which are orthogonal to the first grid lines X1, X2, X3, . . . , Xp−1, Xp, Xp+1, . . . . The first grid lines X1, X2, X3, . . . , Xp−1, Xp, Xp+1, . . . extend in parallel to the primary direction (a vertical direction in  FIG. 3A ). 
   The first diagonal grid area setting module  143  reads the placement information of macrocells extracted by the chip area information extraction module  141 , routing information, and the like and then sets first diagonal grid areas  402   a ,  402   b , and  402   c  in respective areas of the first wiring layer  400   a  under which macrocells are placed. The first diagonal grid areas  402   a ,  402   b , and  402   c  are composed of a plurality of rectangular areas defined by third grid lines (a third line group) Sp−1, Sp, Sp+1, . . . and fourth grid lines (a fourth line group) Tp−1, Tp, Tp+1, . . . , which are orthogonal to the third grid lines Sp−1, Sp, Sp+1, . . . . The third grid lines Sp−1, Sp, Sp+1, . . . extend in a direction (the upper right direction in  FIG. 3A ) rotated clockwise or counterclockwise by 45 degrees with respect to the primary direction in which the first grid lines X1, X2, X3, . . . , Xp−1, Xp, Xp+1, . . . extend. The positions at where the first diagonal grid areas  402   a ,  402   b , and  402   c  are placed are not limited to the areas above the areas where macrocells are placed and can be certainly set properly according to the purpose or application. 
     FIG. 3A  shows an example when the first diagonal grid areas  402   a ,  402   b , and  402   c  are placed at areas above the areas where macrocells are placed. Herein, the primary direction of the interconnect of the first wiring layer  400   a  is the vertical direction in the paper. On the other hand,  FIG. 3B  shows an example when the primary direction of the interconnect of the first wiring layer  400   a  is a diagonal direction (the upper right direction in the paper). As apparent from  FIGS. 3A and 3B , in boundaries between the first grid area  401   a  and each of the first diagonal areas  402   a ,  402   b , and  402   c , end portions of the first grid lines X1, X2, X3, . . . , Xp−1, Xp, Xp+1, . . . and second grid lines Y1, Y2, Y3, . . . , Yp−1, Yp, Yp+1, . . . are connected to respective end portions of the third grid lines Sp−1, Sp, Sp+1, . . . and fourth grid lines Tp−1, Tp, Tp+1, . . . . 
   The first routing module  144  shown in  FIG. 2A  routs a plurality of first wires extending in the primary direction and a plurality of first diagonal wires extending diagonally to the plurality of first wires in the first wiring layer  400   a  based on the first to fourth grid lines Xp−1, Xp, Xp+1, . . . , Yp−1, Yp, Yp+1, . . . , Sp−1, Sp, Sp+1, . . . , Tp−1, Tp, Tp+1, . . . , which are set by the first grid area setting module  142  and first diagonal grid area setting module  143 . The width of the rectangular areas defined by the first to fourth grids Xp−1, Xp, Xp+1, . . . , Yp−1, Yp, Yp+1, . . . , Sp−1, Sp, Sp+1, . . . , Tp−1, Tp, Tp+1, . . . can be set to a minimum interval considering placement of vias and the like. However, wires placed on respective grids are not necessarily placed on each of the rectangular areas defined by the first to fourth grid lines Xp−1, Xp, Xp+1, . . . , Yp−1, Yp, Yp+1, . . . , Sp−1, Sp, Sp+1, . . . , Tp−1, Tp, Tp+1, . . . and can be laid in necessary areas as needed. 
   The first replacement area setting module  145  reads results of routing the first wires and first diagonal wires placed by the first routing module  144  and sets as a first replacement area an area where the wire pitch is narrow and crosstalk may occur. For example, in an area between adjacent macrocells, the wire pitch is set small, and crosstalk is likely to occur. The first replacement area setting module  145  therefore sets, for example, as shown in  FIG. 4A , a first replacement area  403   a  between the first diagonal grid areas  402   a  and  402   b  based on an instruction of an operator inputted from the input unit  4 . The first replacement area setting module  145  sets a first replacement area  403   b  between the first diagonal grid areas  402   a  and  402   c  and sets a first replacement area  403   c  between the first diagonal grid areas  402   b  and  402   c . Furthermore, the first replacement area setting module  145  removes wires already existing in the first replacement areas  403   a ,  403   b , and  403   c  and places a plurality of grid areas defined by fifth grid lines (a fifth line group) Up−1, Up, Up+1, . . . and sixth grid lines (a sixth line group) Vp−1, Vp, Vp+1, . . . , which are orthogonal to the fifth grid lines. The fifth grid lines Up−1, Up, Up+1, . . . extend in a direction rotated clockwise or counterclockwise by 45 degrees with respect to the direction of grid lines of the removed wires. 
   The first replacement setting module  145  may automatically set the first replacement areas  403   a ,  403   b , and  403   c  by calculating congestion degree of wires and the like with a layout program stored in the program memory  6  and the like. 
   For example, as shown in  FIG. 4B , the first replacement area setting module  145  can set first replacement areas  403   d  and  403   e  in the first diagonal grid area  402   b  set in the first wiring layer  400   a . Furthermore, the first replacement area setting module  145  may remove wires already existing in the first replacement areas  403   d  and  403   e  and places a plurality of grid areas defined by the fifth grid lines Up−1, Up, Up+1, . . . and sixth grid lines Vp−1, Vp, Vp+1, . . . , which are orthogonal to the fifth grid lines Up−1, Up, Up+1, . . . . The fifth grid lines Up−1, Up, Up+1, . . . extend in a direction rotated by 45 degrees clockwise or counterclockwise with respect to the direction of grid lines of the removed wires. End portions of the fifth grid lines Up−1, Up, Up+1, . . . and sixth grid lines Vp−1, Vp, Vp+1, . . . are connected to respective end portions of the third grid lines Sp−1, Sp, Sp+1, . . . and fourth grid lines Tp−1, Tp, Tp+1, . . . placed in the first diagonal grid area  402   b.    
   As shown in  FIG. 5A , the first replacement area setting module  145  can set first replacement areas  403   p ,  403   q ,  403   s , and  403   t  in respective parts of the first diagonal grid area  402   a  of  FIG. 4B . The first replacement areas  403   p ,  403   q ,  403   s , and  403   t  may be arbitrarily set by the operator through the input unit  4  or may be automatically set by the first replacement area setting module  145  calculating the density of wires with the layout program stored in the program memory  6  and the like. 
   The first rerouting module  146  reroutes a plurality of the first wires extending in the primary direction or a plurality of the first diagonal wires extending diagonally to the first wires in the first wiring layer  400   a  as shown in  FIG. 5B  based on the fifth and sixth grid lines Up−1, Up, Up+1, . . . , Vp−1, Vp, Vp+1, . . . . The first wires or first diagonal wires are not necessarily rerouted in each rectangular area defined by the fifth and sixth grid lines Up−1, Up, Up+1, . . . , Vp−1, Vp, Vp+1, . . . and, as apparent from  FIG. 5B , can be placed in necessary areas on the fifth and sixth grid lines Up−1, Up, Up+1, . . . , Vp−1, Vp, Vp+1, . . . as needed. 
   The second routing module  15 , for example, as shown in  FIG. 6 , places wires in a second wiring layer based on position information of the first grid area  401   a , first diagonal grid areas  402   a  and  402   b , and the like of the first wiring layer  400   a . In a similar way, wires in third, fourth, and fifth wiring layers are also placed based on information on lower layers. Operations to place wires in the second, third, fourth, fifth, . . . layers are substantially similar to each other, and details thereof are described with the (k+1)-th routing module  17  performing routing of the topmost layer. 
   As shown in  FIG. 2B , the (k+1)-th routing module  17  shown in  FIG. 1  includes a k-th layer information extraction module  171 , a (k+1)-th grid area setting module  172 , a (k+1)-th diagonal grid area setting module  173 , and a (k+1)-th routing module  174 . 
   As shown in  FIG. 6 , the k-th layer information extraction module  171 , extracts position information of a k-th grid area  801   a  and  k -th diagonal grid areas  802   a  and  802   b  of a k-th wiring layer  800   a . The (k+1)-th grid area setting module  172  reads from the data memory  2  information of the grid areas of the k-th wiring layer  800   a  extracted by the k-th layer information extraction module  171 , the primary direction of the interconnect, the routing conditions, and the like and then sets a (k+1)-th grid area  901   a  right above the k-th grid area  801   a  such that the (k+1)-th grid area  901   a  and the k-th grid area  801   a  overlap each other. In a similar way, the (k+1)-th diagonal grid area setting module  173  reads from the data memory  2  information of the grid areas of the k-th wiring layer  800   a  extracted by the k-th layer information extraction module  171 , the primary direction of the interconnect, the routing conditions, and the like and then sets (k+1)-th diagonal grid areas  902   a  and  902   b  right above the k-th diagonal grid areas  802   a  and  802   b  such that the (k+1)-th diagonal grid area  902   a  and  902   b  and the k-th diagonal grid areas  802   a  and  802   b  overlap each other, respectively. The (k+1) routing module  174  reads from the data memory  2  the information of the grid areas set by the (k+1)-th grid area setting module  172  and (k+1)-th diagonal grid area setting module  173  and places a plurality of (k+1)-th wires and a plurality of (k+1)-th diagonal wires in a (k+1)-th wiring layer  900   a . The plurality of (k+1)-th wires extend in parallel to the primary direction, and the plurality of (k+1)-th diagonal wires extend in the direction rotated clockwise or counterclockwise by 45 degrees with respect to the direction in which the plurality of (k+1)-th wires extend. 
   Referring back to  FIG. 1 , the data memory  2  includes a cell information file  21 , a routing information file  22 , a first layer information file  24 , a second layer information file  25 , . . . , a k-th layer information file  26 , a (k+1)-th layer information file  27 , . . . . The cell information file  21  stores information including shapes, sizes, positions, and circuits of cells, macrocells, and megacells placed in the chip area. The routing information file  22  stores routing information necessary to form multi-level interconnect, connection information of circuits, and the like. The first layer information file  24  stores various types of information necessary to place the first wiring layer  400   a  on the chip area. The (k+1)-th layer information file  27  stores various types of information necessary to place the upper (k+1) wiring layer  900   a  on the k-th wiring layer  800   a.    
   The input unit  4  includes a keyboard, a mouse, a light pen, a flexible disk, and the like. The operator can input design data through the input unit  4 . It is also possible to input installation of layout parameters, calculations, cancellations. The display unit  5  displays input and output data, layout results and the like. The output unit  5  includes a display, a printer, and recording equipment, which record data to a computer readable recording media. The program memory  6  stores input and output data, layout program, and the like. 
   With the computer automated design system according to the embodiment, the rectangular areas (the first diagonal grid area  402   a , first replacement area  403   a , and the like) to place the diagonal wires are set in areas where the wire pitch is small and crosstalk may occur, and the rectangular area (the first grid area  401   a ) to place the orthogonal wires is set in the other area, which is apparent from a later-described automated design method. Since the wire lengths of the diagonal wires have square root of two times shorter than the orthogonal wires in the same wiring area, electric power consumption and crosstalk may be decreased. Since providing the diagonal wires can reduce the wiring area by 30% in comparison with the orthogonal wires, the semiconductor integrated circuit with higher integration can be achieved. Particularly, the computer automated design system may be suitable for designing the semiconductor integrated circuit having multi-level interconnect of 4-20 layers or 9-12 layers. Furthermore, with the computer automated design system according to the embodiment, the first diagonal grid areas  402   a  and  402   b  can be previously set by the first diagonal grid setting module  143  in areas where circuit elements such as RAM, ROM, and DSP are placed and crosstalk may occur based on the information of the chip area. It is therefore possible to design a semiconductor integrated circuit in which occurrence of crosstalk can be further suppressed. 
   As shown in the conceptual diagram of  FIG. 6 , when automated routing is performed using the computer automated design system according to the embodiment, the first grid area  401   a  and first diagonal grid areas  402   a  and  402   b  are placed in the first wiring layer  400   a . In the second wiring layer  500   a , a second grid area  501   a  is placed in an area right above the first grid area  401   a  so as to overlap the first grid area  401   a , and second diagonal grid areas  502   a  and  502   b  are placed in areas right above the first diagonal grid areas  402   a  and  402   b  so as to overlap the first diagonal grid areas  402   a  and  402   b , respectively. In a third wiring layer  600   a , a third grid area  601   a  is placed in an area right above the second grid area  501   a  so as to overlap the second grid area  501   a , and third diagonal grid areas  602   a  and  602   b  are placed in areas right above the second diagonal grid areas  502   a  and  502   b  so as to overlap the second diagonal grid areas  502   a  and  502   b , respectively. In a fourth wiring layer  700   a , a fourth grid area  701   a  is placed in an area right above the third grid area  601   a  so as to overlap the third grid area  601   a , and fourth diagonal grid areas  702   a  and  702   b  are placed in areas right above the third diagonal grid areas  602   a  and  602   b  so as to overlap the third diagonal grid areas  602   a  and  602   b , respectively. In the k-th wiring layer  800   a , the k-th grid area  801   a  is placed in an area right above a (k−1)-th grid area so as to overlap the (k−1)-th grid area, and k-th diagonal grid areas  802   a  and  802   b  are placed in areas right above the (k−1)-th diagonal grid areas so as to overlap the (k−1)-th diagonal grid areas, respectively. 
   As described above, with the automated design system according to the embodiment, the first diagonal grid areas  402   a  and  402   b , the second diagonal grid areas  502   a  and  502   b , . . . , (k+1)-th diagonal grid areas  902   a  and  902   b  to place the diagonal wires are placed in all the respective layers on the chip area so as to overlap each other. The first grid area  401   a , second grid area  501   a , . . . , (k+1)-th grid area  901   a  to place the orthogonal wires are placed in respective layers so as to overlap each other. The positions of the first to sixth grid lines Xp−1, Xp, Xp+1, . . . , Yp−1, Yp, Yp+1, . . . , Sp−1, Sp, Sp+1, . . . , Tp−1, Tp, Tp+1, . . . , Up−1, Up, Up+1, . . . , Vp−1, Vp, Vp+1, . . . placed in each layer therefore match those in another layer. Accordingly, there is no displacement generated between the grid points to place the orthogonal wires and the grid points to place the diagonal wires. Even in the case of forming finer and multi-level interconnect, the problem of restriction of placement positions of via holes due to the displacement between the grid points is not caused, thus facilitating interconnect design. 
   —Computer Automated Design Method— 
   A description is given of the automated design method according to the embodiment using a flowchart of  FIG. 7 . 
   In step S 100 , the information extraction module  10  shown in  FIG. 1  extracts various types of information including cell information, routing information, and the like necessary for interconnect design of a semiconductor integrated circuit. The cell information (circuit information) of cells, macrocells, and megacells placed in the chip area is stored in the cell information file  21  through the input unit  4 . The routing conditions and the like to form a multi-level interconnect on the chip area are stored in the routing information file  22  through the input unit  4 . 
   In step S 110 , interconnect of the first wiring layer  400   a  shown in  FIG. 1  is designed. In step S 111 , the chip area information extraction module  141  of  FIG. 2A  extracts circuit information of the chip area stored in the cell information file  21 . The detailed structure of the semiconductor integrated circuit is not particularly limited. For example, the semiconductor integrated circuit may be an ASIC such as NAND, NOR, AND, DRAM, LOGIC, and DRAM embedded LOGIC and may be a programmable device (PLD) such as FPGA and CPLD. Furthermore, the semiconductor integrated circuit can include an ASIC and a PLD mixed. 
   In step S 112 , the first grid area setting module  142  reads the circuit information extracted by the chip area information extraction module  141  and the routing information stored in the routing information file  22  and, as shown in  FIG. 4A , sets the first grid area  401   a , which is composed of a plurality of rectangular areas defined by the first grid lines X1, X2, X3, . . . , Xp−1, Xp, Xp+1, . . . and second grid lines Y1, Y2, Y3, . . . , Yp−1, Yp, Yp+1, . . . , in the first wiring layer  400   a . The first diagonal grid area setting module  143  reads the cell information extracted by the chip area information extraction module  141 , the routing information, and the like and, as shown in  FIG. 4A , sets the first diagonal grid areas  402   a ,  402   b , and  402   c , each of which is composed of a plurality of rectangular areas defined by the third grid lines Sp−1, Sp, Sp+1, . . . and fourth grid lines Tp−1, Tp, Tp+1, . . . , in the first wiring layer  400   a . For example, when macrocells requiring areas of certain sizes, such as RAM and ROM, are set under the first wiring layer  400   a  and the diagonal wires are desired to be set right above the areas where RAM, ROM, and the like are placed, the first diagonal grid area setting module  143  sets the first diagonal grid areas  402   a ,  402   b , and  402   c  right above the areas where RAM, ROM, and the like are placed. 
   In step S 113 , the first routing module  144  routes a plurality of first wires (not shown) extending in the primary direction and a plurality of the first diagonal wires extending diagonally to the first wires in the first wiring layer  400   a  based on the first to fourth grid lines Xp−1, Xp, Xp+1, . . . , Yp−1, Yp, Yp+1, . . . , Sp−1, Sp, Sp+1, . . . , Tp−1, Tp, Tp+1, . . . set by the first grid area setting module  142  and first diagonal grid area setting module  143 . 
   In step S 114 , as shown in  FIG. 4A  or  4 B, the first replacement area setting module  145  sets the first replacement areas  403   a ,  403   b ,  403   c ,  403   d ,  403   e , . . . in areas where crosstalk may occur. The first replacement areas  403   a ,  403   b ,  403   c ,  403   d ,  403   e , . . . can be set by an instruction from the operator through the input unit  4  based on calculation results of probability of occurrence of crosstalk and the like or can be automatically performed by the first replacement area setting module  145 . 
   In step S 115 , the first replacement area setting module  145  removes the plurality of first wires or first diagonal wires in the first replacement areas  403   a ,  403   b ,  403   c ,  403   d ,  403   e , . . . , which are routed by the first routing module  144 , and places a plurality of rectangular areas in the first replacement areas  403   a ,  403   b ,  403   c ,  403   d ,  403   e , . . . to reroute the removed wires in the areas with the wires removed. The placed rectangular areas are defined by the fifth and sixth grid lines Up−1, Up, Up+1, . . . , Vp−1, Vp, Vp+1, . . . . In step S 116 , in the first wiring layer  400   a , the first rerouting module  146  reroutes either a plurality of the first wires or first diagonal wires extending diagonally to the first wires based on the fifth and sixth grid lines Up−1, Up, Up+1, . . . , Vp−1, Vp, Vp+1, . . . . The routing information of the first wiring layer  400   a  is stored in the first layer information file  24  of  FIG. 1 . 
   In step S 120 , interconnect of the (k+1)-th wiring layer  900   a  above the first wiring layer  400   a  is designed. In step S 121 , the k-th layer information extraction module  171  extracts information of the k-th grid area  801   a  stored in the k-th layer information file  26 . In step S 122 , the (k+1)-th grid area setting module  172  reads the information of the wiring areas extracted by the k-th layer information extraction module  171 , the primary direction of the interconnect and routing conditions stored in the routing information file  22 , and the like and, as shown in  FIG. 6 , sets the (k+1)-th grid area  901   a  right above the k-th grid area  801   a . The (k+1)-th diagonal grid area setting module  173  reads the routing information extracted by the k-th layer information extraction module  171 , the routing conditions stored in the routing information file  22 , and the like and sets the (k+1)-th diagonal grid areas  902   a  and  902   b  right above the k-th diagonal areas  802   a  and  802   b , respectively. 
   In step S 123 , the (k+1)-th routing module  174  places a plurality of (k+1)-th wires (not shown) extending in parallel to the primary direction and a plurality of (k+1)-th diagonal wires (not shown) in the (k+1)-th wiring layer  900   a  based on the information of the wiring areas set by the (k+1)-th grid area setting module  172  and (k+1)-th diagonal grid area setting module  173 . Herein, the (k+1)-th diagonal wires extend in the direction rotated clockwise or counterclockwise by 45 degrees with respect to the direction in which the (k+1)-th wires extend. The routing result is stored in the (k+1)-th layer information file  27 . 
   With the automated design method according to the embodiment, as exemplified in  FIG. 6 , the second diagonal grid areas  502   a  and  502   b , . . . , and k-th diagonal grid areas  902   a  and  902   b  are placed in all the respective first to (k+1)-th wiring layers  400   a  to  900   a  so as to overlap respectively with the first diagonal grid areas  402   a  and  402   b  in which the diagonal wires are placed. It is therefore possible to align the first to sixth grid lines Xp−1, Xp, Xp+1, . . . , Yp−1, Yp, Yp+1, . . . , Sp−1, Sp, Sp+1, . . . , Tp−1, Tp, Tp+1, . . . , Up−1, Up, Up+1, . . . , Vp−1, Vp, Vp+1, . . . placed in respective wiring layers. By the alignment of the placement positions, the problem of restricting the placement of via holes due to the misalignment of the grid lines can be reduced. Accordingly, the interconnect design can be facilitated even in finer and multi-level interconnect. Furthermore, setting the rectangular areas to set the diagonal wires in each wiring layer can decrease wiring area compared to the case of using only the orthogonal interconnect. It is thus possible to increase the wiring efficiency of the semiconductor integrated circuit and thus achieve the higher density thereof. 
   —Semiconductor Integrated Circuit— 
   Next, an example of the semiconductor integrated circuit which can be manufactured using the computer automated design method according to the embodiment is shown in a plan view of  FIG. 8  and in a cross-sectional view of  FIG. 9 . As shown in  FIG. 9 , the semiconductor integrated circuit includes a substrate  30 , a plurality of elements  31   a  and  31   b  on the substrate  30 , and a first insulating film  40  on the plurality of elements  31   a  and  31   b . The first insulating film  40  is provided with a first wiring layer  400  including a first grid area  401  and a first diagonal grid area  402 . The first grid area  401  includes a plurality of first wires  41   a ,  41   b , . . . ,  41   l , . . . extending in parallel to a first primary direction. The first diagonal grid area  402  includes a plurality of first diagonal wires  42   d ,  42   e ,  42   f , . . . connected to the first wires  41   a ,  41   b , . . . ,  41   l , . . . and extended diagonally to the first primary direction. 
   The first wire  41   l  is electrically connected to the element  31   b  on the substrate  30  through a first via plug  351  buried in the first insulating film  40 . The first diagonal wires  42   d  and  42   f  are electrically connected to the element  31   a  through first via plugs  35   e  and  35   f  buried in the first insulating film  40 . A first stopper film  47  is provided on the first wiring  41   l , the first diagonal wires  42   e  and  42   f , and the first insulating film  40 . 
   A second insulating film  50  is provided on the first stopper film  47 . A second wire, which is not shown in the cross-sectional view of  FIG. 9 , and second diagonal wires  52   f  and  52   g  connected to the second wire are provided on the second insulating film  50 . The second diagonal wires  52   f  and  52   g  are connected to the first diagonal wires  42   e  and  42   f  through second via plugs  45   f  and  45   g  buried in the second insulating film  50 . A second stopper film  57  is provided on the second diagonal wires  52   f  and  52   g , and the second insulating film  50 . 
   A third insulating film  60  is provided on the second stopper film  57 . A third wire, which is not shown in the cross-sectional view of  FIG. 9 , third diagonal wires  62   e  and  62   f  and a third wire  62   g  are provided in the third insulating film  60 . The third diagonal wires  62   e  and  62   f  are connected to the second diagonal wires  52   f  and  52   g  through third via plugs  55   e  and  55   f  buried in the third insulating film  60 . A third stopper film  67  is provided on the third diagonal wires  62   e  and  62   f , the third wire  62   g  and the third insulating film  60 . 
   A fourth insulating film  70  is provided on the third stopper film  67 . A fourth wire, which is not shown in the cross-sectional view of  FIG. 9 , and fourth diagonal wires  72   g  and  72   h  connected to the fourth wire are provided in the fourth insulating film  70 . The fourth diagonal wires  72   g  and  72   h  are connected to the third diagonal wires  62   e  and  62   f  through fourth via plugs  65   g  and  65   h  buried in the fourth insulating film  70 . A fourth stopper film  77  is provided on the fourth diagonal wires  72   g  and  72   h  and the fourth insulating film  70 . 
   The material of the first to fourth wires  41   a ,  41   b , . . . ,  71   a ,  71   b , . . . , the first to fourth diagonal wires  42   a ,  42   b , . . . ,  72   a ,  72   b , . . . , and first to fourth via plugs  35   e ,  35   f , . . . ,  65   g ,  65   h , . . . can be aluminum (Al), copper (Cu), Al—Cu, Al-silicon (Si)—Cu, silver (Ag), gold (Au), or the like. The first to fourth insulating films  40 ,  50 ,  60 , and  70  can be low-dielectric constant insulating films (low-k films) with a relative dielectric constant of below 3.0. As such low-dielectric insulating films, organic silicon oxide films of polysiloxane, benzocyclobutene (BCB), and the like; inorganic silicon oxide films of hydrogen-silsesquioxane and the like; carbon fluoride (CF) films of polyallylene ether, parylene, polyimide fluoropolymer, and the like; and the like may be suitable. 
   In the semiconductor integrated circuit according to the embodiment, the diagonal wires (the first to fourth diagonal wires  42   a ,  42   b , . . . ,  72   a ,  72   b , . . . ) are placed in areas where crosstalk may occur. The wire pitch can be therefore increased without violating the design rule, thus reducing error operations of the semiconductor integrated circuit caused by crosstalk between wires. Furthermore, the areas where the diagonal wires are placed are disposed in each of the wiring layers on the substrate  30  so as to overlap and correspond to each other. This can reduce the misalignment of vias even in the multi-level interconnect. 
   —A Method of Manufacturing a Semiconductor Integrated Circuit— 
   A method of manufacturing a semiconductor integrated circuit according to the embodiment of the present invention is described. The method of manufacturing the semiconductor integrated circuit to be described below is an example. Thus, it is needless to say that the present invention can be achieved by use of various other manufacturing methods including a modified example of the one described below. 
   As shown in  FIG. 10 , the first insulating film  40  made from SiO2 film may be formed on a plurality of the elements  31   a  and  31   b  on the substrate  30 . A photoresist film  32  is spin-coated on the surface of the first insulating film  40  and then delineated by use of a photolithography process. Part of the first insulating film  40  is selectively stripped by reactive ion etching (RIE) using the delineated photoresist film  32  as an etching mask to form trenches  33   e ,  33   f , and  331  and via holes. 
   As shown in  FIG. 11 , the photoresist film  32  is removed. As shown in  FIG. 12 , a barrier metal  34  is deposited by CVD on the surface of the first insulating film  40  and the trenches  33   e ,  33   f , and  331 . For the barrier metal  34 , tungsten (W), titan silicon (TiSi), cobalt silicon (CoSi), nickel (N), NiSi, iron silicon (FeSi), aluminum (Al), Al—Si—Cu, Al—Si, Al—Cu, Ag, Au, or laminated films using these materials are suitable for use. 
   As shown in  FIG. 13 , a metal film  36  is formed by plating, CVD, or PVD. The metal film  36  is polished by CMP until the surface of the first insulating film  40  is exposed. As shown in  FIG. 14 , the first via plug  35   e  on a barrier metal  34   e , the first diagonal wire  42   e , the first via plug  35   f  on a barrier metal  34   f , the first diagonal wire  42   f , and the first wire  41   l  on a barrier metal  341  are formed. Accordingly, as shown in the plan view of  FIG. 15 , a plurality of the first wires  41   a ,  41   b ,  41   c , . . . ,  41   l , . . . , are formed on the first grid area  401 . The first diagonal wires  42   a ,  42   b , . . . ,  41   h , . . . , connected to the first wires  41   a ,  41   b ,  41   c , . . . ,  41   l , . . . , are formed in the first diagonal grid area  402 . 
   As shown in  FIG. 16 , the first stopper film  47  is deposited on the surfaces of the first wire  41   l , the first diagonal wires  42   e  and  42   f , and the first insulating film  40  by CVD. For the material of the first stopper film  47 , silicon carbide (SiC), carbon-doped silicon nitride (SiCN), SiN, carbon-doped silicon oxide (SiOC) is agreeable. Subsequently, as shown in  FIG. 17 , the second insulating film  50  is formed on the first stopper film  47  by CVD. For the material of the second insulating film  50 , a porous low-dielectric constant film such as organic silicon oxide film, inorganic silicon oxide film, CF film may be suitable. A photoresist film  42  is applied on the second insulating film  50 . 
   As shown in  FIG. 18 , a photoresist film  42  is delineated by use of a photolithography process. Part of the second insulating film  50  is selectively stripped by RIE using the delineated photoresist film  42  as an etching mask to form trenches  43   f , and  43   g  and via holes. As shown in  FIG. 19 , the photoresist film  42  is removed. As shown in  FIG. 20 , a barrier metal  44  is deposited on the surface of the second insulating film  50 , the trenches  43   f  and  43   g  and via holes. A metal film is formed on the barrier metal  44 . The metal film is polished by CMP until the surface of the second insulating film  50  is exposed. 
   As shown in  FIG. 21 , the second via plug  45   f  on a barrier metal  44   f , the second diagonal wire  52   f , the second via plug  45   g  on a barrier metal  44   g  and the second diagonal wire  52   g  are formed. Accordingly, as shown in the plan view of  FIG. 22 , a plurality of the second wires  51   a ,  51   b ,  51   c , . . . , are formed in the second wire area  501 . The second diagonal wires  52   a ,  52   b , . . . ,  52   g , . . . , connected to the second wires  51   a ,  51   b ,  51   c , . . . , are formed in the second diagonal grid area  502 . 
   As shown in  FIG. 23 , the second stopper film  57  is formed on the surfaces of the second diagonal wires  52   f  and  52   g  and the second insulating film  50 . The third insulating film  60  is formed on the second stopper film  57  by CVD. A photoresist film  52  is applied on the third insulating film  60 . The photoresist film  52  is delineated by use of a photolithography process. As shown in  FIG. 25 , part of the third insulating film  60  is selectively stripped by RIE using the delineated photoresist film  52  as an etching mask to form trenches  53   e ,  53   f  and  53   g  and via holes. The residual photoresist film  52  is removed. 
   As shown in  FIG. 25 , a barrier metal  54  is deposited on the surface of the third insulating film  60 , the trenches  53   e ,  53   f , and  53   g , and via holes. A metal film is formed on the barrier metal  54  and polished by CMP. As shown in  FIG. 26 , the third via plug  55   e  and the third diagonal wire  62   e  are formed in the third insulating film  60  through a barrier metal  54   e . The third via plug  55   f  and the third diagonal wire  62   f  are formed in the third insulating film  60  through a barrier metal  54   f . The third wire  62   g  is formed in the third insulating film  60  through a barrier metal  54   g . Accordingly, as shown in the plan view of  FIG. 27 , a plurality of the third wires  61   a ,  61   b ,  61   c , . . . , are formed in the third wire area  601 . The third diagonal wires  62   a ,  62   b , . . . ,  62   g , . . . , connected to the third wires  61   a ,  61   b ,  61   c , . . . , are formed in the third diagonal grid area  602 . 
   As shown in  FIG. 28 , the third stopper film  67  is formed on the surfaces of the third diagonal wires  62   e  and  62   f , third wire  62   g , and the third insulating film  60  by CVD. A fourth insulating film  70  is formed on the third stopper film  67  by CVD. A photoresist film  62  is applied on the fourth insulating film  70  and delineated by use of the photolithography process. The trenches  63   g  and  63   h  and via holes are formed by using the delineated photoresist film  62  as an etching mask. The photoresist film  62  is removed by RIE. 
   As shown in  FIG. 29 , a barrier metal is deposited on surfaces of the trenches  63   g  and  63   h , and via holes by plasma CVD, a metal film is formed on the barrier metal and polished by CMP. The fourth via plug  54   g  and the fourth diagonal wire  72   g  are buried in the trench  63   g  through the barrier metal  54   g . The fourth via plug  65   h  and the fourth diagonal wire  72   h  are buried in the trench  63   h  through the barrier metal  54   h . Accordingly, as shown in the plan view of  FIG. 30 , a plurality of the fourth wires  71   a ,  71   b ,  71   c , . . . , are formed in the fourth wire area  701 . The fourth diagonal wires  72   a ,  72   b , . . . ,  72   h , . . . , connected to the fourth wires  71   a ,  71   b ,  71   c , . . . , are formed in the fourth diagonal grid area  702 . The fourth stopper film  77  is formed on the fourth insulating film  70  by CVD. The semiconductor integrated circuit as shown in  FIG. 9  is then manufactured. 
   With the method of manufacturing a semiconductor integrated circuit according to the embodiment, the diagonal wires (the first to fourth diagonal wires  42   a ,  42   b , . . . ,  72   a ,  72   b , . . . ) can be formed in areas where crosstalk may occur. The wire pitch can be therefore increased without violating the design rule, and crosstalk can be reduced. Furthermore, the areas where the diagonal wires are placed are disposed in each of the wiring layers constituting a multi-level interconnect structure on the substrate  30  so as to correspond to each other, thus reducing the misalignment of vias connecting wires. 
   OTHER EMBODIMENTS 
   Various modifications will become possible for those skilled in the art after receiving the teachings of the present disclosure without departing from the scope thereof. 
   The first diagonal grid areas  402   a ,  402   b , . . . set by the first diagonal grid area setting module  143  can be properly changed based on the circuit information of the chip area. For example, when RAM, ROM, DSP, and the like, each of which requires an area of certain size, are used to form an integrated circuit, the entire area where RAM, ROM, DSP, and the like are placed is set to the diagonal grid area. In a semiconductor integrated circuit including an ASIC and a PLD mixed, the first grid area to place the orthogonal wires and the first diagonal grid area to place the diagonal wires can be placed in the ASIC part and the PLD part, respectively. 
   In the interconnect of the first layer designed by the first routing module  14 , either power supply wires, clock wires, or signal wires can be placed. 
   The semiconductor integrated circuit shown in  FIG. 9  exemplifies a semiconductor integrated circuit including four metal wiring layers but may include any number of metal wiring layers. 
   In addition to the semiconductor integrated circuits shown in  FIGS. 8 and 9 , various semiconductor integrated circuits can be manufactured. For example, as shown in  FIG. 31 , a second stopper film  57  on a second insulating film  50 , a third stopper film  67  on a third insulating film  60 , a fourth stopper film  77  of a fourth insulating film  70 , which are sequentially formed in a thickness direction of the substrate  30 , are individually perforated, and then cavities  58 ,  68 , and  78  are formed in the second, third, and fourth insulating films  50 ,  60 , and  70  by O2 asher, respectively. The second to fourth diagonal wires  52   f ,  52   g ,  62   e ,  62   f ,  62   g ,  72   g , and  72   h  thus form air gap interconnect. The relative dielectric constant between the insulating layers is reduced, and the signal transmission delay can be further reduced. 
   As shown in  FIG. 32 , in the second insulating film  50 , a second via plug  45   z  with a height H and second via plugs  45   x  and  45   y  with heights less than the height H of the second via plug  45   z  are embedded. The second via plugs  45   x  and  45   y  are adjacent to the second via plug  45   z . The second via plug  45   z  is connected to a second diagonal wire  52   z ; the second via plug  45   x  is connected to a second diagonal wire  52   x ; and the second via plug  45   y  is connected to a second diagonal wire  52   y.    
   The thus obtained second diagonal wires  52   x ,  52   y , and  52   z  are different from each other in height. The distance between the wires therefore is increased, and the parasitic capacitance between the wires is reduced. Also in the semiconductor integrated circuit with the structure shown in  FIG. 32 , it is possible to reduce the signal transmission delay influenced by the parasitic capacitance between wires and occurrence of crosstalk, which becomes prominent as the distance between wires gets smaller. The second diagonal wires  52   x ,  52   y , and  52   z  shown in  FIG. 32  can be formed by only changing the height of the second via plugs  45   x ,  45   y , and  45   z  based on a two-dimensional layout obtained by the design system shown in  FIG. 1 , and patterns of the wiring layers can be easily designed. 
   Considering the influence of the parasitic capacitance between wires and occurrence of crosstalk, it is suitable in the semiconductor integrated circuit shown in  FIG. 32  that the height H of the lower surface of the second diagonal wire  52   z  is set substantially equal to or more than the height of the upper surfaces of the second diagonal wires  52   x  and  52   y  connected to the second via plugs  45   x  and  45   y . In the second diagonal wires  52   x ,  52   y , and  52   z , side faces of two adjacent wire structures therefore do not face each other, and the parasitic capacitance between wires can be reduced. It is obvious that, to be exact, the height H of the lower surface of the second diagonal wire  52   z  vertically changes to some extent due to etching in the manufacturing process and the like. 
     FIG. 33  shows an example in which the interconnect structure shown in  FIG. 32  is applied to the second to fourth layers of the integrated circuit shown in  FIG. 9 .  FIG. 34  shows an example in which a diffusion preventing film (stopper film) is disposed on each of upper surfaces of the second diagonal wire  52   f , third diagonal wire  62   e , third wire  62   g , and fourth diagonal wire  72   g . In this case, film materials of the second insulating film  50   a  and  50   b  may be either the same or different; film materials of the third insulating films  60   a  and  60   b  may be either the same or different; and film materials of the fourth insulating films  70   a  and  70   b  may be either the same or different. The semiconductor integrated circuits shown in  FIGS. 31 to 34  shown as the examples include four metal wiring layers but may include any number of metal wiring layers depending on the application. For example, the interconnect structures as shown in  FIGS. 31-34  may be suitable for the semiconductor integrated circuit including multi-level interconnect of 4-20 layers or 9-12 layers. 
     FIG. 35  shows an example in which the interconnect structure shown in  FIG. 32  is applied to the first to fourth layer of the integrated circuit shown in  FIG. 9 .  FIG. 36  shows an example in which a diffusion preventing film (stopper film) is disposed on each of the upper surfaces of the second diagonal wire  52   f , third diagonal wire  62   e , third wire  62   g , and fourth diagonal wire  72   g . In this case, film materials of the second insulating films  50   a  and  50   b  may be either the same or different; film materials of the third insulating films  60   a  and  60   b  may be either the same or different; and film materials of the fourth insulating films  70   a  and  70   b  may be either the same or different. 
   Also in the semiconductor integrated circuits shown in  FIGS. 33 to 36 , side faces of two adjacent wire structures do not face each other. The distance between wires is increased, and the parasitic capacitance between wires is reduced. In the semiconductor integrated circuits shown in  FIGS. 33 to 36 , it is therefore possible to reduce the signal transmission delay due to the parasitic capacitance between wires and occurrence of crosstalk, which become prominent as the distance between wires gets smaller. 
   As shown in  FIG. 37 , in the semiconductor integrated circuit according to the embodiment, the topmost wiring layers (k-th wiring layer  800   a , (k+1)-th wiring layer  900   a ) can be set to the diagonal grid area. In this case, the diagonal grid area is set directly over areas where crosstalk may occur, and the occurrence of crosstalk can be suppressed. It is therefore possible to provide a semiconductor integrated circuit using a design method with the placement of via holes less restricted. 
   As shown in the perspective view of  FIG. 38  and the plan view of  FIG. 39 , the area of the first to (k+1)-th diagonal grid areas  402   a ,  502   a ,  602   a ,  702   a , . . . , can be set to broaden while advancing toward the upper layer. As shown in the perspective view of  FIG. 40  and the plane view of  FIG. 41 , a plurality of first to third diagonal grid areas  402   a ,  502   a ,  602   a ,  402   b ,  502   b , and  602   b  can be selectively set to the first to third wiring layers  400   a ,  500   a , and  600   a , respectively. 
   As shown in the perspective view of  FIG. 42  and the plan view of  FIG. 43 , the first to (k+1)-th diagonal grid areas  402   a ,  502   a ,  602   a ,  702   a , . . . , and  902   a  having different areas can be set to the first to (k+1)-th wiring layers  400   a ,  500   a , . . . , and  900   a . As shown in the perspective view of  FIG. 44  and the plan view of  FIG. 45 , a plurality of the first to (k+1)-th diagonal grid areas  402   a ,  502   a ,  602   a ,  702   a , . . . ,  802   a ,  902   a ,  402   a ,  502   a ,  602   b ,  602   b , . . . ,  802   b , and  902   b  can be selectively set to the first to third wiring layers  400   a ,  500   a , . . . , and  900   a.    
   As shown in the plan view of  FIG. 46  and the plane view of  FIG. 47 , the positions of the first to (k+1)-th diagonal grid areas  402   a ,  502   a ,  602   a ,  702   a , . . . ,  802   a , and  902   a  are not limited to the same areas and can be positioned on different areas. In this case, the diagonal grid areas are set over the entire areas positioned over the areas R 1  through R 3  where crosstalk may occur. In addition, since the first replacement area setting module  145  can replace the first to (k+1)-th grid areas  401   a ,  501   a ,  601   a ,  701   a , . . . , and  901   a  shown in  FIG. 42  to the first to (k+1)-th diagonal grid areas  403   a ,  503   a ,  603   a ,  703   a , . . . , and  903   a  shown in  FIG. 48 , the diagonal wires may be placed in entire layer of the semiconductor integrated circuit.