Patent Publication Number: US-8536888-B2

Title: Built in self test for transceiver

Description:
FIELD 
     The present disclosure relates to semiconductor devices and communications testing. 
     BACKGROUND 
     Digital transceivers have been developed to transmit and receive signals according to a variety of protocols, such as SONET, SDH, 10 GbE, PCI Express, SATA, Fibre channel, or the like. As part of the validation process for a transceiver, the transceiver is subjected to a test pattern that has been modulated to include jitter. Jitter in a high-frequency digital signal is manifested by deviation in a characteristic of the pulses, such as amplitude, phase timing, or the width of the signal pulse. Jitter may be caused by electromagnetic interference (EMI) and/or crosstalk with other signals. An important characteristic of a receiver design is its jitter tolerance. 
     Sophisticated and costly test equipment have been developed to emulate various signal streams that a transceiver may be expected to encounter in actual use, including “stressed” signal streams that have been modulated to include jitter. Unfortunately, the costs of automated test equipment (ATE) and the complexity of integrated circuits are both rising quickly. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a diagram of an integrated circuit (IC) with a built in self test (BIST) function. 
         FIG. 2  shows an embodiment of a test system including the IC of  FIG. 1 . 
         FIG. 3  is a block diagram of the “TX with RX Tester” block of  FIG. 1 . 
         FIG. 4  is a schematic diagram of an embodiment of the stressed transmitter block of  FIG. 3 . 
         FIG. 5  is a schematic diagram an embodiment of the eye stressed control logic block of  FIG. 3 . 
         FIG. 6A  is a timing diagram of an input signal from the test pattern generator of  FIG. 2 . 
         FIG. 6B  is a timing diagram of the PRE_SW signal of  FIGS. 3 and 5 , corresponding to the input signal in  FIG. 6A . 
         FIG. 7  is a flow chart of a method performed by the IC of  FIG. 1 . 
     
    
    
     DETAILED DESCRIPTION 
     This description of the exemplary embodiments is intended to be read in connection with the accompanying drawings, which are to be considered part of the entire written description. 
       FIG. 1  is a diagram of an integrated circuit (IC)  100  comprising a transceiver device under test (DUT) with a built in self test (BIST) function. In some embodiments, the IC  100  is configured to receive a simple input data stream DATAIN (approximating an ideal data stream) without jitter from a relatively simple test pattern generator. The test pattern generator may be external to the IC, such as external test pattern generator  200  shown in  FIG. 2 . The on-chip BIST circuitry  102  is configured to modify the input signal DATAIN to emulate a stressed signal. The stressed signal simulates such deviations in signal characteristics as may occur when a signal is transmitted through a long cable, for example. The stressed signal  103  is provided to the receiver amplifier  104 , and normal clock recovery circuit  106  eliminates jitter within the tolerance of the transceiver  100  to provide an output signal DATAOUT. The input signal DATAIN is compared to the recovered signal DATAOUT, and a bit error rate is determined based on the comparison. 
     As shown in  FIG. 1 , the input signal DATAIN from the test pattern generator  200  approximates an ideal pattern  120  having constant magnitude (voltage) and positive or negative polarity. The stressed signal  103  has a more complex pattern  122 . Due to RC delays, higher frequency pulses (e.g., pulse  122   c ) do not reach the steady state HIGH or LOW voltage values before the polarity of the signal reverses and have a significantly smaller voltage (magnitude) than the lower frequency pulses (e.g., pulse  122   a ). Intermediate frequency pulses (e.g.,  122   b ) more closely approach the steady state voltage before reversing polarity, and thus have an intermediate magnitude. The lowest frequency pulses  122   a  reach the steady state HIGH or LOW voltage and have a greater amplitude than pulses  122   c.    
     Thus, the stressed signal is characterized by amplitude that varies with the duration of the pulses. In other words, the greater the frequency of the signal, the smaller the amplitude is. 
     Ideally, the receiver  104 ,  106  is able to tolerate the jitter, and extract the original data stream. The waveform  124  shows the output stream DATAOUT from the transceiver. To the extent that bits of the output stream DATAOUT differ from the input stream DATAIN, bit errors are detected. 
       FIG. 1  shows the major blocks of the IC  100 . The input stream DATAIN may be provided directly from external terminals of the IC  100 , or may be received by way of an intermediate on-chip function. In other embodiments (not shown), the DATAIN stream is generated by another on-chip function. 
     The DATAIN stream is provided to a delay block  110  DIFO, which may be a latch, for example. DATAIN is also provided to the “TX with RX Tester” block  102 , which modulates the amplitude of the signal  103  to emulate an eye-stressed signal  122 . With block  122  included on-chip, there is no need for any external receiver stress test solution device. The block  102  provides the eye-stressed signal  103  to the receiver amplifier  104 . The clock recovery block  106  generates a clock signal from an approximate frequency reference, and then phase-aligns to the transitions in the stressed signal stream  103  with a phase-locked loop (PLL), not shown. The receiver amplifier  104  and clock recovery block  106  recover the signal stream within the jitter tolerance of the transceiver, to provide the output stream DATAOUT to the comparison block  108 . Non-matching bits are detected, and identified. 
       FIG. 2  shows a system including the IC  100  of  FIG. 1 . The system includes a test pattern generator (TPG) at least capable of providing an input signal stream that is compliant with the relevant protocol of the transceiver  100 , approximating an ideal signal without jitter. For example, TPG  200  may be capable of providing a stream to emulate SONET, SDH, 10 GbE, PCI Express, SATA, Fibre channel, or the like. For this purpose, the TPG  200  need not be capable of providing complex jitter patterns. For example, a relatively inexpensive model 81133A Pulse Pattern Generator sold by Agilent Technologies of Santa Clara, Calif., provides suitable test patterns. 
     In some embodiments, the BIST circuit block  102  includes two major functions  130 ,  132 . 
     The eye-stressed control block  130  is an encoder configured for receiving an input signal DATAIN and identifying whether a first condition is present, in which two or more consecutive input data bits have the same polarity as each other. The stressed transmitter  132  includes an output driver circuit for providing the stressed input signal  103  corresponding to the two or more consecutive input data bits. The stressed input signal  103  has an amplitude that is larger when the encoder  130  identifies that the first condition is present and smaller when the encoder identifies that two or more consecutive input data bits have different polarity from each other. 
     The receiver amplifier  104  on the IC substrate is configured to receive the stressed input signal  103  and provide the amplified signal to the clock recovery block  106  and digital output block  107 , which may be a D flip-flop, for example. Digital output block  107  outputs a signal based on the recovered clock signal and the state of the amplified signal. Digital output block  107  outputs a stream having constant amplitude and two polarity values to the data comparator  108 . This output stream DATAOUT is thus nearly the same as the delayed version of DATAIN from the latch  110  ( FIG. 1 ), except that any non-matching bits between the delayed DATAIN and DATAOUT are bit errors. The comparator  108  flags the bit errors in a comparator output signal  202 , which is received by the digital output results block  202 . Block  202  may be included in the TPG  200 , or may be a separate module in a computer or data acquisition system (not shown). The bit error rate of the transceiver is then determined from the frequency of bit errors identified by the comparator  108 . 
       FIG. 3  is a block diagram of one embodiment of the “TX with RX Tester” block  102 . The eye-stressed control logic block  130  of  FIG. 2  is implemented by an encoder that receives a DATA_CLK clock signal and the DATAIN input signal from the TPG  200 . The encoder  130  outputs the input stream as IN and its complement as IN_. Optionally, the encoder also receives a plurality of externally supplied configuration input signals CLRIN_ 1  to CLRIN_N. For each configuration input signal CLRIN_ 1  to CLRIN_N, a respective output signal PRE_SW 1  to PRE_SWN is output from the encoder  130 . The outputs PRE_SW 1  to PRE_SWN are based on the externally provided inputs CLRIN_ 1  to CLRIN and on dynamic conditions of the DATAIN stream, as described below. In some embodiments, the dynamic conditions of the DATAIN stream determine whether or not to apply a modulation factor to the DATAIN stream, and the externally provided inputs CLRIN_ 1  to CLRIN determine the amount of the modulation. In some embodiments the externally provided inputs CLRIN_ 1  to CLRIN determine the amount of the modulation by configuring a programmable current mirror. 
     In alternative embodiments, CLRIN_ 1  to CLRIN are not provided from an external source to block  130 . In some embodiments, block  130  uses a configuration that only depends on the dynamic conditions of the DATAIN stream to determine PRE_SW 1  to PRE_SWN, and does not depend on externally supplied configuration inputs. 
     The stressed transmitter (current boosting output driver) block  132  receives the input stream as a differential pair, IN and its complement IN_, and receives the control signals PRE_SW 1  to PRE_SWN if they are provided by the encoder  130 . In some embodiments, the stressed transmitter block  132  transmits a differential voltage signal PADP, PADM, which is modulated to emulate a stressed input signal. In other embodiments, the output of stressed transmitter block  132  is a single-ended signal. One of ordinary skill can readily modify stressed transmitter to convert a differential signal to a single ended signal, for example using a balun circuit. 
       FIG. 4  is a schematic diagram of an embodiment of the stressed transmitter block (current boosting output driver)  132  of  FIG. 3 . Block  132  includes three sections: a current bias circuit  440 , a current boosting circuit  400  and an output differential pair PADP, PADM. 
     In some embodiments, the current boosting circuit includes a programmable current mirror circuit  400 . A current source  402  provides a reference current to the reference transistor  404  and a first (fixed) mirror transistor  406 . The reference transistor  404  has its gate connected to its drain, so that V DG =0. One or more second (selectable) mirror transistors  420 ,  430  are provided. The reference transistor  404  and the first mirror transistor  406  have gates connected to each other. 
     All the mirror transistors  406 ,  420  and  430  are connected to each other in parallel, with their drains all connected to each other, and the sources of all the mirror transistors connected to the negative supply rail V SS . The one or more (selectable) second mirror transistor  420 ,  430  are selectively switchable to a connected configuration in which the gates of the one or more of the second mirror transistors  420 ,  430  are connected to the gate of the reference transistor  404 . For example, transistor  420  has a switch  422  for selectively connecting its gate to the gate of reference transistor  404 , and a switch  424  for selectively connecting its gate to V SS . (At any given time one of the switches  422  and  424  is closed, and the other of switches  422  and  424  is open.). Similarly, second transistor  430  has a switch  432  for selectively connecting the gate of transistor  430  to the gate of reference transistor  404 , and a switch  434  for alternatively connecting the gate of transistor  430  to V SS . The various switches  422 ,  424 ,  432  and  434  may be switching transistors, but other switching elements may be used. 
     The second mirror transistors  420 ,  430  are selectively connected in parallel to change the current mirror ratio of current mirror  400 . As is understood by one of ordinary skill in the art, the current mirror ratio (ratio of the output current at node  448  to the reference current  402 ) is given by the ratio of (W/L) MIRROR /(W/L) REFERENCE , where W/L is the width-to-length ratio of a transistor. By adding one or more parallel mirror transistor legs (e.g., transistors  420  and  430 ), the total of the numerator (W/L) MIRROR  is increased. The number and individual (W/L) value for each of the second mirror transistor legs  420 ,  430  are designed to vary the current mirror ratio in any desired range. For example, in some embodiments, the reference transistor  404 , first mirror transistor  406  and second mirror transistors  420 ,  430  are sized so that the current mirror ratio is 1.0 when all of the second mirror transistors  420 ,  430  have their gates disconnected (switches  422 ,  432  open and switches  424  and  434  closed); and the current mirror ratio is about 2.0 when all of the second mirror transistors have their gates connected to the gate of reference transistor  404  (switches  422 ,  432  closed and switches  424  and  434  open). The range of the current mirror ratio is selected to provide a range of currents for varying the bias voltage across its target range. The number of second mirror transistors may be varied to provide any desired number of intermediate current mirror ratios. 
       FIG. 4  shows an embodiment in which the current mirror ratio is varied by selectively adding mirror transistor legs without varying the reference transistor side of the current mirror. In other embodiments (not shown), the current mirror ratio is varied by selectively connecting parallel transistor legs on the reference transistor side, with all the reference transistor legs having their drains connected to each other and their sources connected to ground, and the programmable reference transistor legs having their gates switchably connectable to the gate of the reference transistor. In another embodiment, the current mirror ratio is varied by switchably connecting parallel transistor legs on both the reference side and the mirror side of the current mirror. In another embodiment, instead of providing a switch between the gate and the source of each second mirror transistor  420 ,  430 , a switch is provided between the gate and drain of each second mirror transistor. Other current mirror designs may also be used. 
     The bias circuit  440  includes a first transistor  442  and a second transistor  444 , each having its drain connected to the positive supply rail V DD , and each having its gate connected to node  448  of the current mirror circuit  400 . Transistor  442  also has its source connected to its gate at node  446 , so that V GS =0, and transistors  446  and  444  always have a bias voltage applied at their gates. Transistor  442  and the connected mirror transistors  406 ,  420 ,  430  form a voltage divider, so the bias voltage on the gates of transistors  446  and  444  at a given time is determined by the total parallel resistance of the ones of transistors  406 ,  420  and  430  which are conducting at that time. Thus, when the current is increased by the current boosting circuit  410 , the output amplitude of PADP, PADM is also increased. 
     The input signal IN and its complement IN are each provided to the gate of a respective PMOS transistor  452 ,  452 , to provide the differential voltage PADP, PADM. 
     The switching of the respective mirror transistor legs for connecting the gates of the second mirror transistors  420 ,  430  is independently controlled by the respective control signals PRE_SW 1  to PRE_SWN. The generation of these signals is described below with reference to  FIG. 5 . 
       FIG. 5  is a schematic diagram an embodiment of the eye stressed control logic (encoder)  130  of  FIG. 3 . In some embodiments, the encoder  130  includes: at least two storage devices  500 ,  502  for storing at least two consecutive values of the input signal DATAIN; and logic  504  for comparing the two consecutive values and outputting a first signal  505  that indicates whether the two consecutive values are the same or different. 
     In one embodiment, the DATAIN signal is input to a first D flip flop  500 . The DATA_CLK signal is input to the first D flip flop  500  and a second D flip flop  502 . The first flip flop  500  outputs the signal DATAIN as IN and its complement as IN_. The IN signal is provided to a second D flip flop  502  and to XNOR gate  504 . Thus, the first flip flop  500  stores the current value of DATAIN, and the second flip flop  502  stores the most recent previous value of DATAIN. The second flip flop  502  outputs its value to the other input of the XNOR gate  504 . Thus, XNOR gate outputs a logic HIGH when the outputs of both flip flops  500 ,  502  are the same (i.e., the current value of DATAIN and most recent previous value of DATAIN are the same) and a logic LOW when the outputs of both flip flops  500 ,  502  are different from each other (i.e., the current value of DATAIN and most recent previous value of DATAIN are different from each other). 
     In some embodiments, encoder  130  has a respective external input CLRIN[ 0 ] to CLRIN[N] corresponding to each respective (selectable) second mirror transistor  420 ,  430 . As noted above, CLRIN[ 0 ] to CLRIN[N] determine the amount of the modulation of PADP, PADM. Encoder  130  also includes a respective AND gate  510 - 512  corresponding to each respective (selectable) second mirror transistor  420 ,  430 . The output of XNOR gate  504  is input to one input of each of the AND gates  510 - 512 . The other input of each AND gate  510 - 512  receives a respective one of the external input signals CLRIN[ 0 ] to CLRIN[N]. Each AND gate  510 - 512  outputs a respective one of the switching control signals PRE_SW 1  to PRE_SWN that are used to independently control the selective connection of the programmable mirror transistors  420 ,  430 . Thus, each AND gate  510 - 512  outputs a logic HIGH if the external control signal CLRIN[ 0 ] to CLRIN[N] corresponding to that AND gate is logic high for selecting the corresponding (programmable) second transistor leg of current mirror  400 , and the dynamic conditions of the DATAIN signal are such that two consecutive bits of DATAIN have the same polarity. 
     Thus the logic  510 - 512  provides one or more second signals PRE_SW 1  to PRE_SWN to configure the output driver circuit  132 , responsive to the first signal  505  and one or more respective externally supplied configuration input signals CLRIN[ 0 ] to CLRIN[N]. 
       FIGS. 6A and 6B  are timing diagrams showing the effect of the XNOR logic gate  504  of  FIG. 5 .  FIG. 6A  is a timing diagram of an input signal from the test pattern generator  200  of  FIG. 2 .  FIG. 6B  is a timing diagram of the output  505  of XNOR gate  504 .  FIG. 6B  also represents the PRE_SW signal of  FIGS. 3 and 5 , corresponding to the input signal in  FIG. 6A , for any programmable current mirror leg having its external input signal CLRIN set to select that leg. In  FIGS. 6A and 6B , the duration of each bit is 2.5 nanoseconds. When two consecutive bits have the same polarity (no change in value for at least 5 nanoseconds), signal  505  and the PRE_SW signal of  FIG. 6B  takes a value of one. Whenever the polarity of DATAIN changes, the value of signal  505  and PRE_SW both return to zero. Thus, the output  505  of the XNOR gate  504  is HIGH whenever the currently received bit of DATAIN matches the most recently received bit; and the PRE_SW signal selectively connects the corresponding programmable current mirror transistor only when DATAIN has the same polarity for at least two consecutive bits. 
       FIG. 7  is a flow chart of a method of using the IC  100  with BIST. 
     At step  700 , the configuration inputs CLRIN[ 0 ] to CLRIN[N] are received by way of the external inputs of the IC  100 . 
     At step  702 , the values of CLRIN[ 0 ] to CLRIN[N] are provided to AND gate  504  to select which current mirror transistor legs will be connected for increasing the current mirror ratio during the periods when two or more consecutive input bits have the same polarity. 
     At step  704 , the input signal DATAIN is received. This signal approximates an ideal signal stream according to the relevant protocol. 
     At step  706 , the first on chip circuit (encoder  130 ) determines if two consecutive bits of the input signal DATAIN have the same polarity. 
     At step  708 , if two consecutive bits of the input signal DATAIN have the same polarity, step  710  is performed next. If not, then step  712  is performed next. 
     At step  710 , the second circuit (e.g., current boosting output driver  132 ) increases the signal amplitude, to form the stressed signal. In some embodiments, this is accomplished by selectively connecting one or more current mirror transistors (selected by their respective PRE_SW control signals) to increase the current mirror ratio. This in turn changes the voltage divider of the bias circuit  440  to increase the bias voltage and the differential signal pair PADP, PADM. 
     At step  712 , the stressed signal is transmitted to the on chip receiver  104 . 
     At step  714 , the output of the receiver  104  is compared to the input DATAIN. 
     At step  716 , if the bits matched, step  718  is executed. If not, step  720  is executed. 
     At step  718 , the non-matching bits are identified as a bit error. 
     At step  720 , matching bits indicate a good bit. 
     At the conclusion of the relevant test period, the bit error rate is determined. 
     Thus, embodiments are described in which an integrated circuit (IC), comprises a receiver on an IC substrate. The receiver is configured to receive a stressed input signal. A built in self test (BIST) circuit is provided on the IC substrate for testing the receiver. The BIST circuit comprises an encoder configured for receiving an input signal and identifying whether a first condition is present, in which two or more consecutive input data bits have the same polarity as each other. An output driver circuit provides the stressed input signal corresponding to the two or more consecutive input data bits. The stressed input signal has an amplitude that is larger when the encoder identifies that the first condition is present and smaller when the encoder identifies that two or more consecutive input data bits have different polarity from each other. 
     Method embodiments are described comprising: (a) receiving an input signal in an integrated circuit (IC); (b) using a first circuit within the IC to determine whether or not two consecutive data bits of the input signal have the same polarity; and (c) using a second circuit within the IC to modulate the input signal to increase an amplitude of the two consecutive data bits thereof if the two consecutive data bits of the input signal have the same polarity, thereby to form a stressed signal. 
     Although the subject matter has been described in terms of exemplary embodiments, it is not limited thereto. Rather, the appended claims should be construed broadly, to include other variants and embodiments, which may be made by those skilled in the art.