Patent Publication Number: US-10311188-B2

Title: Circuit design support apparatus, circuit design support method, and computer readable medium

Description:
TECHNICAL FIELD 
     The present invention relates to a technology for supporting circuit design. 
     BACKGROUND ART 
     For design of semiconductor integrated circuits (hereinafter also referred to as large scale integration (LSI)), there has been a technology of generating a register transfer level (RTL) describing behaviors of combined circuits of registers (flip-flops) by using a hardware description language. 
     In recent years, the circuit size of integrated circuits has been growing, and significant time is required for generation of the RTL. 
     Thus, a technology of automatically generating an RTL by using a high-level language such as the C language, the C++ language, and the System C language, which are more abstract than the RTL, has been proposed. 
     In addition, tools for generating an RTL from a high-level language are commercially available as high-level synthesis tools. 
     Behavioral description only describes the specification of behaviors but does not describe the specification on implementation. 
     Owing to general constraints in high-level synthesis, however, behavioral description may affect the implementation to be obtained as a result of the behavioral description depending on the manner in which the behavioral description is described. 
     For example, array variables in behavioral description are generally allocated to functional modules of a storage device such as a memory or a register (functional modules of a storage device will hereinafter be referred to as memory modules) in high-level synthesis. 
     Since an array variable is often described in a large size, an array variable is also allocated to a memory module of a large size in high-level synthesis. 
     Owing to the allocation to memory modules of large sizes in the high-level synthesis, a memory (hardware) having a large size may be allocated, which may increase the area of the LSI to be designed. 
     Typically, such a large memory is implemented by an external memory outside of the LSI to be designed. 
     With the current high-level synthesis tools, however, a specific memory module cannot be automatically allocated to an external memory. 
     Thus, in order to obtain an architecture in which a specific memory module is implemented by an external memory, the designer himself/herself needs to modify the behavioral description and describe a communication interface between the LSI and the external memory. 
     For example, Patent Literature 1 discloses a method of automatically generating a communication interface between an LSI and an external memory by providing the behavioral description created by the designer with configuration information of hardware to be designed (whether or not an external memory is present) and mapping information (specification of allocation of an array variable in the behavioral description to an external memory) without modifying the behavioral description by the designer. 
     CITATION LIST 
     Patent Literature 
     Patent Literature 1: JP 2008-204341 A 
     SUMMARY OF INVENTION 
     Technical Problem 
     In Patent Literature 1, however, the designer himeself/herself still needs to select to which memory an array variable in the behavioral description is to be allocated. 
     Thus, with the method of Patent Literature 1, the designer himself/herself has to select a memory module to which an external memory is to be allocated, which is not efficient. 
     A major object of the present invention is to solve such a problem as described above and to achieve a configuration capable of making circuit design procedures efficient. 
     Solution to Problem 
     A circuit design support apparatus according to the present invention, includes: 
     a binding data acquiring unit to acquire binding data describing a plurality of memory modules as functional modules of a design target circuit; and a memory module selecting unit to select an external memory module to be implemented as an external memory outside of the design target circuit from the memory modules described in the binding data on the basis of a constraint condition on the design target circuit. 
     Advantageous Effects of Invention 
     According to the present invention, the circuit design support apparatus selects a memory module to be implemented as an external memory, a designer need not consider a memory module to be implemented as the external memory, which makes circuit design procedures efficient. 
    
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         FIG. 1  is a diagram illustrating an example functional configuration of a high-level synthesis system according to a first embodiment. 
         FIG. 2  is a diagram illustrating an example functional configuration of a circuit design support apparatus according to the first embodiment. 
         FIG. 3  is a flowchart illustrating example operation of the circuit design support apparatus according to the first embodiment. 
         FIG. 4  is a table illustrating examples of constraint information according to the first embodiment. 
         FIG. 5  is a diagram illustrating an example of binding data according to the first embodiment. 
         FIG. 6  is a chart illustrating examples of write access timing and read access timing according to the first embodiment. 
         FIG. 7  is a table illustrating an example of determination on external memory module candidates based on write data holding cycle time according to the first embodiment. 
         FIG. 8  is a chart illustrating an example of memory modules that are subjects of a process of determining external memory candidates based on read access waiting time according to the first embodiment. 
         FIG. 9  is a diagram illustrating an example of determination on an external memory module candidate on the basis of a read access waiting time according to the first embodiment. 
         FIG. 10  is a diagram illustrating an example of determination on an external memory module candidate on the basis of a read access waiting time according to the first embodiment. 
         FIG. 11  is a table illustrating examples of external memory module candidates according to the first embodiment. 
         FIG. 12  is a table illustrating an example of procedures for selecting an external memory module according to the first embodiment. 
         FIG. 13  is a diagram illustrating an example hardware configuration of the circuit design support apparatus according to the first embodiment. 
     
    
    
     DESCRIPTION OF EMBODIMENTS 
     First Embodiment 
     ***Description of Configuration*** 
       FIG. 1  illustrates an example functional configuration of a high-level synthesis system  100  according to a first embodiment. 
     The functional configuration of the high-level synthesis system  100  in the first embodiment will be described on the basis of  FIG. 1 . 
     The high-level synthesis system  100 , however, may have a configuration different from that of  FIG. 1 . 
     For example, a high-level synthesis apparatus  110  and a circuit design support apparatus  200  may be configured in one apparatus. 
     The high-level synthesis system  100  is a system for carrying out high-level synthesis for circuit design of semiconductor integrated circuits and the like. 
     Hereinafter, a circuit to be designed, which is subject to high-level synthesis in the high-level synthesis system  100 , will be referred to as a design target circuit. 
     High-level synthesis is a technology for generating a register-transfer level (RTL) description describing operation of the design target circuit in the RTL from behavioral description describing behaviors of the design target circuit using a high-level language such as the C language, the C++ language, or the System C language. 
     The high-level synthesis system  100  includes a high-level synthesis apparatus  110  to carry out high-level synthesis, and a circuit design support apparatus  200  to support the high-level synthesis execution. 
     The high-level synthesis apparatus  110  includes a CDFG generating unit  111 , a scheduling unit  112 , a binding unit  113 , an RTL description generating unit  114 , and a high-level synthesis apparatus storage unit  120 . 
     The CDFG generating unit  111  generates CDFG data  122  containing a control data flow graph (CDFG) from a behavioral description file  121  containing behavioral description of a design target circuit. 
     The CDFG indicates the operation order of a plurality of arithmetic operations performed by the design target circuit. 
     The CDFG includes a control flow graph (CFG) and a data flow graph (DFG). 
     The scheduling unit  112  generates scheduling data  123  on the basis of the CDFG data  122 . 
     The scheduling data  123  is data indicating an execution time range of each of the arithmetic operations contained in the CDFG. 
     A method for generating the scheduling data  123  may be the same as a scheduling method in conventional high-level synthesis. 
     The binding unit  113  generates binding data  124  on the basis of the CDFG data  122  and the scheduling data  123 . 
     The binding data  124  describes functional modules of the design target circuit. 
     The binding data  124  describes as the functional modules, a plurality of operation modules (operation resources) which are allocated to the respective arithmetic operations included in the CDFG. 
     The operation modules are arithmetic units, registers, and the like. 
     The binding data  124  also describes a plurality of memory modules, which are modules of a memory device used by the operation modules. 
     Details of the binding data  124  will be described below. 
     Note that a method for generating the binding data  124  may be the same as a binding method in the conventional high-level synthesis. 
     The RTL description generating unit  114  generates an RTL description file  125  indicating an RTL description on the basis of the CDFG data  122 , the scheduling data  123 , and the binding data  124 . 
     A method for generating the RTL description file  125  may be the same as an RTL description generating method in the conventional high-level synthesis. 
     The high-level synthesis apparatus storage unit  120  stores data used, generated, input, and output by the high-level synthesis apparatus  110 . 
     Specifically, the high-level synthesis apparatus storage unit  120  stores the behavioral description file  121 , the CDFG data  122 , the scheduling data  123 , the binding data  124 , and the RTL description file  125 . 
       FIG. 2  illustrates an example functional configuration of the circuit design support apparatus  200  according to the first embodiment. 
     The functional configuration of the circuit design support apparatus  200  in the first embodiment will be described on the basis of  FIG. 2 . 
     The circuit design support apparatus  200  may have a functional configuration different from that of  FIG. 2 . 
     The circuit design support apparatus  200  includes a constraint information input accepting unit  210 , a binding data acquiring unit  220 , an external memory determining unit  230 , an external memory selecting unit  240 , a CDFG data acquiring unit  280 , an external memory interface generating unit  250 , a support data providing unit  260 , and a support apparatus storage unit  270 . 
     The constraint information input accepting unit  210  accepts constraint information  271  defining a constraint condition and the like on the design target circuit. 
     The constraint information  271  is input by a user using the circuit design support apparatus  200 . 
     The binding data acquiring unit  220  acquires the binding data  124  from the high-level synthesis apparatus  110 . 
     Note that a process performed by the binding data acquiring unit  220  corresponds to an example of a binding data acquiring process. 
     The external memory determining unit  230  analyzes a read cycle time and a write cycle time of a memory module on the basis of the constraint information  271  and the binding data  124 . 
     The external memory determining unit  230  then extracts external memory module candidates that are candidates for an external memory module, which is a memory module to be implemented as an external memory being outside of the design target circuit. 
     The external memory determining unit  230  then generates an external memory determination result  272  indicating the extracted external memory module candidates. 
     The external memory selecting unit  240  searches for a memory architecture satisfying the constraint condition on the basis of the constraint information  271 , the binding data  124 , and the external memory determination result  272 . 
     That is, the external memory selecting unit  240  selects a memory module that satisfies the constraint condition as the external memory module from the external memory module candidates. 
     More specifically, the external memory selecting unit  240  selects the external memory module from the external memory module candidates on the basis of at least either of a constraint condition on a circuit size and a constraint condition on latency. 
     The external memory selecting unit  240  then generates an external memory selection result  273  indicating the selected external memory module. 
     The external memory determining unit  230  and the external memory selecting unit  240  constitute a memory module selecting unit  2000 . 
     In addition, processes performed by the external memory determining unit  230  and the external memory selecting unit  240  correspond to examples of a memory module selecting process. 
     The CDFG data acquiring unit  280  acquires the CDFG data  122  from the high-level synthesis apparatus  110 . 
     The external memory interface generating unit  250  generates description of a module of a communication interface which is to be used by the design target circuit for communication with an external memory, on the basis of the external memory selection result  273 . 
     The external memory interface generating unit  250  then generates converted CDFG data  274  by replacing the description of the memory module corresponding to the external memory module in the CDFG data  122  with the description of the module of the communication interface. 
     The support data providing unit  260  provides the converted CDFG data  274  to the high-level synthesis apparatus  110 . 
     The scheduling unit  112  of the high-level synthesis apparatus  110  regenerates the scheduling data  123  on the basis of the provided converted CDFG data  274 . 
     The binding unit  113  and the RTL description generating unit  114  then regenerates the binding data  124  and the RTL description file  125  on the basis of the regenerated scheduling data  123  and the converted CDFG data  274 . 
     ***Description of Operation*** 
       FIG. 3  is a flowchart of a circuit design support process performed by the circuit design support apparatus  200  according to the first embodiment. 
     The circuit design support process performed by the circuit design support apparatus  200  in the first embodiment will be described on the basis of  FIG. 3 . 
     The circuit design support process may, however, be achieved by procedures different from those in  FIG. 3 . 
     Note that the circuit design support process illustrated in  FIG. 3  corresponds to an example of a circuit design support method and a circuit design support program of the present application. 
     In S 110 , the constraint information input accepting unit  210  accepts the constraint information  271  necessary for operating the circuit design support apparatus  200  from the user, and stores the acquired (received) constraint information  271  in the support apparatus storage unit  270 . 
     The constraint information defines the following five values: 
     (a) a cycle time threshold Tth for external memory determination; 
     (b) a latency constraint Lmax for external memory selection; 
     (c) a circuit size constraint Smax for external memory selection; 
     (d) optimization policy information P for external memory selection; and 
     (e) external memory configuration information Minfo for external memory selection and external memory interface generation. 
     First, (a) the cycle time threshold Tth for external memory determination will be described. 
     The cycle time threshold Tth for external memory determination is a threshold that is a reference for extracting the external memory module candidates. 
     The cycle time threshold Tth for external memory determination is used in S 132  and S 134 . 
     Hereinafter, the cycle time threshold Tth for external memory determination will also be simply referred to as a cycle time threshold Tth. 
     Next, (b) the latency constraint Lmax for external memory selection will be described. 
     The latency constraint Lmax for external memory selection is a constraint condition on the latency to be referred to at a time of selection of the external memory module from the external memory module candidates. 
     The external memory selecting unit  240  searches for a memory architecture satisfying the latency constraint Lmax for external memory selection. 
     The latency constraint Lmax for external memory selection is used in S 140 . 
     Hereinafter, the latency constraint Lmax for external memory selection will also be simply referred to as a latency constraint Lmax. 
     Next, (c) the circuit size constraint Smax for external memory selection will be described. 
     The circuit size constraint Smax for external memory selection is a constraint condition on the circuit size to be referred to at a time of selection of the external memory module from the external memory module candidates. 
     The external memory selecting unit  240  searches for a memory architecture satisfying the circuit size constraint Smax for external memory selection. 
     The circuit size constraint Smax for external memory selection is used in S 140 . 
     Hereinafter, the circuit size constraint Smax for external memory selection will also be simply referred to as a circuit size constraint Smax. 
     Next, (d) the optimization policy information P for external memory selection will be described. 
     The optimization policy information P for external memory selection is a guideline for optimization to be referred to at a time of selection of the external memory module from the external memory module candidates. 
     Circuit size optimization and latency optimization are selected as the optimization policy information P for external memory selection. 
     When the optimization policy information P for external memory selection is the circuit size optimization, the external memory selecting unit  240  searches for a memory architecture satisfying the latency constraint Lmax for external memory selection and the circuit size constraint Smax for external memory selection and minimizing the circuit size. 
     When the optimization policy information P for external memory selection is the latency optimization, the external memory selecting unit  240  searches for a memory architecture satisfying the latency constraint Lmax for external memory selection and the circuit size constraint Smax for external memory selection and minimizing the latency. 
     The optimization policy information P for external memory selection is used in S 140 . 
     Hereinafter, the optimization policy information P for external memory selection will also be simply referred to as optimization policy information P. 
     Next, (e) the external memory configuration information Minfo for external memory selection and external memory interface generation will be described. 
     The external memory configuration information Minfo for external memory selection and external memory interface generation is information indicating what hardware the external memory module selected in S 135  is implemented. 
     For example, the external memory configuration information Minfo for external memory selection and external memory interface generation indicates the type of the external memory (such as a DRAM, a DDR-SDRAM, or a QDR-SDRAM), or the like. 
     The external memory configuration information Minfo for external memory selection and external memory interface generation is used in S 140  and S 160 . 
     Hereinafter, the external memory configuration information Minfo for external memory selection and external memory interface generation will also be simply referred to as external memory configuration information Minfo. 
     The constraint information input accepting unit  210  acquires the constraint information  271  as illustrated in  FIG. 4 , for example. 
     After S 110 , the process proceeds to S 120 . 
     In S 120 , the binding data acquiring unit  220  of the circuit design support apparatus  200  acquires (receives) the binding data  124  generated by the binding unit  113  of the high-level synthesis apparatus  110  from the high-level synthesis apparatus  110 . 
     After S 120 , the process proceeds to S 130 . 
       FIG. 5  is a diagram illustrating an example of the binding data  124  according to the first embodiment. 
     The first embodiment will be described on the basis of the binding data illustrated in  FIG. 5 . 
     As illustrated in  FIG. 5 , the binding data describe a plurality of functional modules included in the design target circuit. 
     Quadrangles with “func” written therein in  FIG. 5  are operation modules of the design target circuit. 
     The operation modules refer to an arithmetic unit which performs an arithmetic operation and a resistor, as mentioned above. 
     Quadrangles with “mem” written therein in  FIG. 5  are memory modules of the design target circuit. 
     The memory modules refer to memory devices as mentioned above. 
     Arrows in  FIG. 5  indicate the flow of data. 
     The binding data indicate to which memory module each operation module performs read access (from which memory data is to be read) and to which memory module each operation module performs write access (in which memory an operation result is to be stored). 
     In addition, although not illustrated in  FIG. 5 , the binding data describes the timing (cycle time) of read access occurring in each memory module and an operating block (read access operating block) to perform the read access, and the timing (cycle time) of write access and an operating block (referred to as a write access operating block) to perform the write access. 
     In the present embodiment, the binding data acquiring unit  220  acquires the binding data  124  of  FIG. 5 . 
     The description refers back to  FIG. 3 , and continues from  5130 . 
     In S 130 , the external memory determining unit  230  selects a certain memory module from a plurality of memory modules described in the binding data  124 . 
     Hereinafter, the memory module selected in S 130  will be referred to as a determination subject memory module. 
     After S 130 , the process proceeds to S 131 . 
     In S 131 , the external memory determining unit  230  analyzes the life cycle of the determination subject memory module to acquire the following two cycle times: 
     (1) a cycle time when write access is terminated for the determination subject memory module; and 
     (2) a cycle time when the last read access to write data is started for the determination subject memory module. 
     Subsequently, the external memory determining unit  230  calculates “the cycle time of (1)—the cycle time of (2)” to obtain a write data holding cycle time Ts of the determination subject memory module. 
     As indicated by the expression above, the write data holding cycle time Ts is time from termination of write access to a memory module until start of the last read access to write data having been written in the memory module by the write access. 
     After S 131 , the process proceeds to S 132 . 
     In S 132 , the external memory determining unit  230  compares the write data holding cycle time Ts of the determination subject memory module obtained in S 131  with the cycle time threshold Tth for external memory determination in the constraint information  271 , to determine whether or not the determination subject memory module is to be an external memory module candidate. 
     If Ts≥Tth, the external memory determining unit  230  determines the determination subject memory module to be an external memory module candidate (YES), and the process proceeds to S 135 . 
     If Ts&lt;Tth, the external memory determining unit  230  does not determine the determination subject memory module to be an external memory module candidate (NO), and the process proceeds to S 133 . 
       FIG. 6  illustrates an example of a life time cycle analysis result of each memory module according to the first embodiment. 
       FIG. 7  illustrates an example of determination result on extraction of external memory module candidates based on the life time cycle analysis result of each memory module according to the first embodiment. 
     Specific examples of S 131  and S 132  will be explained on the basis of  FIGS. 6 and 7 . 
       FIG. 6  illustrates a result of analysis of write access cycle time and read access cycle time for each memory module in the binding data  124 . 
     On the basis of the analysis result, the external memory determining unit  230  acquires, for each memory module, the cycle time when write access is terminated and the cycle time when the last read access to write data is started. 
       FIG. 7  illustrates the cycle time when write access is terminated and the cycle time when the last read access to write data is started acquired for each memory module by the external memory determining unit  230  from  FIG. 6 . 
     In addition, the external memory determining unit  230  calculates, for each memory module holding cycle time Ts of write data , and compares Ts with Tth to determine whether or not each memory module is to be an external memory module candidate. 
     Tth is 1500 as illustrated in  FIG. 4 , Ts of mem 1  is 9000 and Ts of mem 4  is  2200  as illustrated in  FIG. 7 . 
     Thus, since Ts &gt;Tth is satisfied for mem 1  and mem 4 , mem 1  and mem 4  are extracted as external memory module candidates in the example of  FIG. 7 . 
     With the binding data of  FIG. 5  and the cycle times of  FIG. 6 , if calculation results of func 1  are accumulated in an external memory and data is acquired from the external memory at the start of operation of func 7 , mem 1  need not be included as an internal memory in the design target circuit. 
     Thus, mem 1  is extracted as an external memory module candidate. 
     Since mem 4  need not be included as an internal memory in the design target circuit, either, for a similar thought, mem 4  is extracted as an external memory module candidate. 
     Since, however, mem 1  is also used by func 2 , a small-capacity internal memory needs to be implemented separately. This will be described below. 
     The description refers back to  FIG. 3 , and continues from S 133 . 
     The external memory determining unit  230  applies a criterion of “whether data necessary for starting operations of operation modules requiring the determination subject memory module will be completely obtained in the cycle time not longer than the threshold Tth” to a determination subject memory module determined not to be an external memory module candidate as a result of S 132 . 
     In other words, the external memory determining unit  230  determines whether or not a determination subject memory module is to be an external memory module candidate on the basis of the criterion described above. 
     In S 133 , the external memory determining unit  230  analyzes the determination subject memory module to acquire the following two pieces of information: 
     (1) data stored in the determination subject memory module necessary for one iteration of a function requiring the determination subject memory module; and 
     (2) a cycle time Tg necessary for obtaining complete data of (1). 
     After the two pieces of information are acquired, the process proceeds to S 134 . 
     In S 134 , the external memory determining unit  230  compares the cycle time Tg obtained in S 133  with the cycle time threshold Tth at a time of the external memory determination in the constraint information  271 , to determine whether or not the determination subject memory module is to be extracted as the external memory module candidate. 
     If Tg≥Tth, the determination subject memory module is determined to be the external memory module candidate (YES), and the process proceeds to S 135 . 
     If Tg&lt;Tth, the determination subject memory module is determined to be a candidate for an internal memory module to be implemented as an internal memory (NO), and the process proceeds to S 136 . 
       FIG. 8  is a chart illustrating an example of memory modules that are subjects of the external memory determination in S 133 . 
     In  FIG. 8 , the memory modules other than mem 1  and mem 4  (the memory modules indicated by arrows) are the memory modules that are subjects of the external memory determination in S 133 . 
       FIG. 9  illustrates an example of determination of an external memory module candidate on mem 5 . 
       FIG. 10  illustrates an example of determination of an external memory module candidate on mem 3 . 
     Specific examples of S 131  and S 132  will be explained on the basis of  FIGS. 8, 9, and 10 . 
     In S 131  and S 132 , mem 1  and mem 4  are already determined to be external memory module candidates. 
     Thus, as illustrated in  FIG. 8 , mem 2 , mem 3 , mem 5 , and mem 6  are subjects of the external memory determination in S 133  and S 134 . 
       FIG. 9  illustrates a result of determination on whether or not mem 5  is an external memory module candidate. 
     First, the external memory determining unit  230  extracts read access to mem 5 . 
     If mem 5  is read in a loop as a result of the extraction, the external memory determining unit  230  analyzes which elements of mem 5  are accessed in the first iteration of the loop. 
     In the example of  FIG. 9 , since i=0 at the first iteration of the loop, mem 5 [ 0 ] and mem 5 [N] are accessed according to mem 5 [i] and mem 5 [N-i]. 
     Thus, if data of mem 5 [ 0 ] and mem 5 [N] are completely obtained, func 6  can start operating. 
     Subsequently, the external memory determining unit  230  extracts write access to mem 5 . 
     The external memory determining unit  230  then calculates the timing when mem 5 [ 0 ] and mem 5 [N] will completely be obtained. 
     In the example of  FIG. 9 , func 6  cannot start operating until write access to mem 5 [N] occurs, that is, until the operation of func 5  is terminated. 
     In the example of  FIG. 9 , the cycle time Tg from when func 5  starts operating until when func 6  is enabled to start operating (until write access to mem 5 [N] occurs) is 2000. 
     Thus, “Tg≥Tth” is satisfied, and mem 5  is determined to be the external memory module candidate. 
     With the binding data of  FIG. 5  and the cycle times of  FIG. 6 , if calculation results of func 5  are accumulated in an external memory and data is acquired from the external memory at the start of operation of func 6 , mem 5  need not be included as an internal memory in the design target circuit. 
     Thus, mem 5  is extracted as an external memory module candidate. 
       FIG. 10  illustrates a result of determination on whether or not mem 3  is an external memory module candidate. 
     First, the external memory determining unit  230  extracts read access to mem 3 . 
     If mem 3  is read in a loop as a result of the extraction, the external memory determining unit  230  analyzes which elements of mem 3  are accessed in the first iteration of the loop. 
     In the example of  FIG. 10 , since i=0 at the first iteration of the loop, mem 3 [ 0 ], mem 3 [ 1 ], and mem 3 [ 2 ] are accessed according to mem 3 [i], mem 3 [i+1], and mem 3  [i+2]. 
     Thus, if data of mem 3 [ 0 ], mem 3 [ 1 ], and mem 3 [ 2 ] are completely obtained, func 5  can start operating. 
     Subsequently, the external memory determining unit  230  extracts write access to mem 3 . 
     The external memory determining unit  230  then calculates the timing when mem 3 [ 0 ], mem 3 [ 1 ], and mem 3 [ 2 ] are completely obtained. 
     In the example of  FIG. 10 , func 5  cannot start operating until write access to mem 3 [ 2 ] occurs. 
     Since, however, data is written to mem 3 [ 2 ] without waiting to termination of the operation of func 3 , func 5  can be started to operate. 
     In the example of  FIG. 10 , the cycle time Tg from when func 3  starts operating until when func 5  is enabled to start operating (until write access to mem 3  [ 2 ] occurs) is 100. 
     Thus, “Tg&lt;Tth” is satisfied, and mem 3  is determined to be implemented by the internal memory. 
     As described above, the external memory determining unit  230  analyzes, for each memory module, the timing of write access and an operating block (write access operating block) to perform the write access, and the timing of read access and an operating block (read access operating block) to perform the read access, which are described in the binding data  124 . 
     The external memory determining unit  230  also calculates read access waiting time (the cycle time Tg in  FIG. 9 , for example), which is the time from when the write access operating block (func 5  in  FIG. 9 , for example) to perform write access of operand data to be used by the read access operating block (func 6  in  FIG. 9 , for example) for arithmetic operation starts operating until when the read access operating block (func 6  in  FIG. 9 , for example) is enabled to start read access to the operand data. 
     The external memory determining unit  230  then extracts a memory module (mem 5  in  FIG. 9 , for example) where the calculated read access waiting time is not shorter than the threshold as the external memory module candidate. 
     The description refers back to  FIG. 3 , and continues from S 135 . 
     If the determination subject memory module selected in S 131  is determined to be the external memory module candidate as a result of S 132  and S 134 , the external memory determining unit  230  writes information on the determination subject memory module in the external memory determination result  272  in S 135 . 
     After S 135 , the process proceeds to S 136 . 
     In S 136 , the external memory determining unit  230  checks whether or not all the memory modules in the binding data  124  have been analyzed. 
     If there is an unanalyzed memory module (NO), the process returns to S 130 . 
     If all the memory modules have been analyzed (YES), the process proceeds to S 140 . 
     In S 140 , the external memory selecting unit  240  selects an external memory module from the external memory module candidates in the external memory determination result  272  on the basis of the constraint information  271 . 
     After S 140 , the process proceeds to S 150 . 
       FIG. 11  illustrates an example of the external memory determination result  272  according to the first embodiment. 
       FIG. 12  illustrates an example of a memory architecture search result according to the first embodiment. 
     A specific example of S 140  will be explained on the basis of  FIGS. 11 and 12 . 
       FIG. 11  illustrates a list of memory modules determined to be external memory module candidates as a result of the external memory module determination performed by the external memory determining unit  230  on the memory modules described in the binding data  124 . 
     In the example of  FIG. 11 , mem 1 , mem 4 , mem 5 , and mem 6  are the external memory module candidates. 
     Thus, the external memory selecting unit  240  searches for a memory module to be the external memory module from mem 1 , mem 4 , mem 5 , and mem 6 . 
     Generally, when a memory inside an LSI is replaced by an external memory, so that a memory can be excluded from the LSI, which makes the circuit size of the LSI smaller. 
     The cycle time required to acquire data from an external memory is longer than that for acquiring data from a memory inside the LSI. 
     Thus, replacement of an LSI internal memory with an external memory involves a trade-off between the circuit size and the processing latency. 
     Thus, implementing all the memories determined to be the external memory module candidates as illustrated in  FIG. 11  as the external memories is not always an optimum solution. 
     A search to determine which memory module among the memory modules determined to be the external memory module candidates illustrated in  FIG. 11  is to be implemented as the external memory is therefore necessary. 
     In the present embodiment, the external memory selecting unit  240  generates all the combinations of a plurality of external memory module candidates. 
     The external memory selecting unit  240  then calculates, for each combination of external memory module candidates, the circuit size and the latency of a case where the external memory module candidates included in the combination are implemented as the external memories on the basis of the binding data  124 . 
     Furthermore, the external memory selecting unit  240  selects a combination from the plurality of combinations of external memory module candidates on the basis of the calculated circuit sizes and latencies, and selects the external memory module candidates included in the selected combination as the external memory modules. 
     More specifically, the external memory selecting unit  240  selects a combination, whose calculated circuit size satisifies the constraint condition on the circuit size and whose calculated latency satisifies the constraint condition on the latency, from the plurality of combinations of external memory module candidates. 
     If there are a plurality of combinations whose calculated circuit sizes satisfy the constraint condition on the circuit size and whose calculated latencies satisfy the constraint condition on the latency, the external memory selecting unit  240  selects a combination with the smallest calculated circuit size. 
     Alternatively, the external memory selecting unit  240  may select a combination with the shortest calculated latency. 
       FIG. 12  illustrates the circuit size and the latency of each combination of external memory module candidates calculated by the external memory selecting unit  240 . 
     The circuit size of the entire LSI in  FIG. 12  refers to a circuit size that is a sum of the circuit size of the design target circuit in a case where a certain memory module from a plurality of memory modules is implemented as the external memory and the circuit size of peripheral circuits. 
     In addition, the processing latency of the entire LSI in  FIG. 12  refers to processing latency occurring at the design target circuit in a case where a certain memory module from a plurality of memory modules is implemented as the external memory. 
     Specifically, the circuit size of the entire LSI is calculated as follows: 
     the circuit size of the entire LSI 
     =the circuit size of the design target circuit in a case where all the memory modules are internal memories 
     −the circuit size of memory modules to be the external memories 
     +the circuit size of the communication interfaces with the external memories. 
     Thus, the external memory selecting unit  240  obtains these three circuit sizes, and performs the above calculation using the three circuit sizes. 
     The first “circuit size of the design target circuit in a case where all the memory modules are internal memories” is a circuit size of the design target circuit when all the memory modules described in the binding data  124  are implemented as internal memories in the design target circuit. 
     The second “circuit size of memory modules to be external memories” is a circuit size of the external memories when certain external memory module candidates included in the combination are implemented as the external memories. 
     The third “circuit size of the communication interfaces with external memories” is a circuit size of the communication interfaces used by the design target circuit for communication with external memories when certain external memory module candidates included in the combination are implemented as the external memories. 
     Specifically, the processing latency of the entire LSI is calculated as follows: 
     the processing latency of the entire LSI 
     =the processing latency of the design target circuit in a case where all the memory modules are internal memories 
     +the processing latency when data are acquired from external memories. 
     Thus, the external memory selecting unit  240  obtains these two processing latencies, and performs the above calculation using the two processing latencies. 
     The first “processing latency of the design target circuit in a case where all the memory modules are internal memories” is latency occurring when all the memory modules described in the binding data are implemented as the internal memories in the design target circuit, and corresponds to a first latency. 
     The second “processing latency when data are acquired from external memories” is latency required for the design target circuit to acquire data from the external memories when certain external memory module candidates included in the combination are implemented as the external memories, and corresponds to a second latency. 
     Note that the external memory selecting unit  240  calculates the cycle time required to acquire data from the external memory on the basis of the external memory configuration information Minfo. 
     In the example of  FIG. 4 , since the external memory is a DDR_SDRAM, the cycle time required to acquire data from the external memory is calculated based on this. 
     The external memory selecting unit  240  selects a combination that satisfies the conditions, from the result in  FIG. 12 , on the basis of the latency constraint Lmax, the circuit size constraint Smax and the optimization policy information P in the constraint information  271 . 
     In the example of  FIG. 4 , since the optimization policy information P is priority to the circuit size, the external memory selecting unit  240  selects a memory architecture (a combination of external memory modules) satisfying the latency constraint Lmax and the circuit size constraint Smax and minimizing the circuit size. 
     The external memory selecting unit  240  then generates an external memory selection result  273  describing the selection result. 
     The description refers back to  FIG. 3  and continues from S 150 . 
     In S 150 , the CDFG data acquiring unit  280  of the circuit design support apparatus  200  acquires (receives) from the high-level synthesis apparatus  110 , the CDFG data  122  generated by the CDFG generating unit  111  of the high-level synthesis apparatus  110 . 
     After S 150 , the process proceeds to S 160 . 
     In S 160 , the external memory interface generating unit  250  of the circuit design support apparatus  200  automatically generates an external memory interface on the basis of the external memory selection result  273 . 
     The external memory interface generating unit  250  converts the description of the memory module selected to be the external memory module in the CDFG data  122  into description of the automatically generated external interface, to generate the converted CDFG data  274 . 
     For example, the external memory interface generating unit  250  generates the converted CDFG data  274  by using an interface generating apparatus disclosed in Patent Literature 1 or the like. 
     After S 160 , the process proceeds to S 170 . 
     In S 170 , the support data providing unit  260  provides (transmits) the converted CDFG data  274  to the high-level synthesis apparatus  110 . 
     The scheduling unit  112 , the binding unit  113 , and the RTL description generating unit  114  of the high-level synthesis apparatus  110  then generate the scheduling data  123 , the binding data  124 , and the RTL description file  125  on the basis of the provided converted CDFG data  274 . 
     ***Description of Effects of Embodiment*** 
     As described above, in the present embodiment, there exists an effect that the circuit design support apparatus is capable of extracting memory modules to be implemented as external memories from memory modules that are functional modules of the storage device (memory) in behavioral description, and automatically generating by high-level synthesis a circuit necessary when the memory modules are implemented as the external memories. 
     ***Summary*** 
     The present embodiment above describes a circuit design support apparatus that receives behavioral description, performs a high-level synthesis (behavioral synthesis) process, and outputs an RTL description, the circuit design support apparatus including: an external memory determining unit to calculate a holding cycle time of write data of each memory module and a cycle time required until data necessary to start operating each function requiring each memory module are completely obtained, from a binding result that is a result of the high-level synthesis, and determine whether each memory module is to be an external memory; an external memory selecting unit to search for a memory architecture satisfying a constraint condition from the memory modules that are external memory module candidates; and an external memory interface generating unit to automatically generate a communication interface with an external memory from a result of selection of the external memory selecting unit. 
     In addition, the present embodiment above describes a circuit design support method for receiving behavioral description, performing a high-level synthesis (behavioral synthesis) process, and outputting an RTL description, the circuit design support method including: an external memory determining process of calculating a holding cycle time of write data of each memory module and a cycle time required until data necessary to start operating each function requiring each memory module are completely obtained, from a binding result that is a result of the high-level synthesis, and determining whether each memory module is to be an external memory; an external memory selecting process of searching for a memory architecture satisfying a constraint condition from the memory modules that are external memory module candidates; and an external memory interface generating process of automatically generating a communication interface with an external memory from a result of selection of the external memory selecting process. 
     ***Description of Hardware Configuration*** 
     Finally, an example hardware configuration of the circuit design support apparatus  200  will be described with reference to  FIG. 13 . 
     The circuit design support apparatus  200  is a computer. 
     The circuit design support apparatus  200  includes hardware such as a processor  901 , an auxiliary storage device  902 , a memory  903 , a communication device  904 , an input interface  905 , and a display interface  906 . 
     The processor  901  is connected to other hardware via a signal line  910 , and controls these hardware. 
     The input interface  905  is connected to an input device  907 . 
     The display interface  906  is connected to a display  908 . 
     The processor  901  is an integrated circuit (IC) to perform processing. 
     The processor  901  is, for example, a central processing unit (CPU), a digital signal processor (DSP), or a graphics processing unit (GPU). 
     The auxiliary storage device  902  is a read only memory (ROM), a flash memory, or a hard disk drive (HDD), for example. 
     The memory  903  is, for example, a random access memory (RAM). 
     The communication device  904  includes a receiver  9041  to receive data, and a transmitter  9042  to transmit data. 
     The communication device  904  is a communication chip or a network interface card (NIC), for example. 
     The input interface  905  is a port to which a cable  911  of the input device  907  is connected. 
     The input interface  905  is a universal serial bus (USB) terminal, for example. 
     The display interface  906  is a port to which a cable  912  of the display  908  is connected. 
     The display interface  906  is an USB terminal or a high definition multimedia (HDMI: registered trademark) terminal, for example. 
     The input device  907  is a mouse, a keyboard, or a touch panel, for example. 
     The display  908  is, for example, a liquid crystal display (LCD). 
     The auxiliary storage device  902  stores programs to implement the functions of the constraint information input accepting unit  210 , the binding data acquiring unit  220 , the external memory determining unit  230 , the external memory selecting unit  240 , the external memory interface generating unit  250 , the support data providing unit  260 , and the CDFG data acquiring unit  280  (which will be collectively referred to as “units”) illustrated in  FIG. 2 . 
     The programs are loaded into the memory  903 , read by the processor  901 , and executed by the processor  901 . 
     Furthermore, the auxiliary storage device  902  also stores an operating system (OS). 
     At least part of the OS is loaded into the memory  903 , and the processor  901  executes the programs to implement the functions of the “units” while executing the OS. 
     While one processor  901  is illustrated in  FIG. 13 , the circuit design support apparatus  200  may include a plurality of processors  901 . 
     The plurality of processors  901  may then execute the programs to implement the functions of the “units” in cooperation with one another. 
     Furthermore, information, data, signal values, and variable values representing results of processing performed by the “units” are stored in the memory  903 , the auxiliary storage device  902 , or a register or a cache memory in the processor  901 . 
     The “units” may alternatively be provided in the form of “circuitry.” 
     Alternatively, a “unit” may be read as a “circuit,” a “step,” a “procedure,” or a “process.” 
     The “circuit” and “circuitry” are concepts including not only the processor  901  but also other types of processing circuits such as a logic IC, a gate array (GA), an application specific integrated circuit (ASIC), and a field-programmable gate array (FPGA). 
     REFERENCE SIGNS LIST 
       100 : high-level synthesis system,  110 : high-level synthesis apparatus,  111 : CDFG generating unit,  112 : scheduling unit,  113 : binding unit,  114 : RTL description generating unit,  120 : high-level synthesis apparatus storage,  121 : behavioral description file,  122 : CDFG data,  123 : scheduling data,  124 : binding data,  125 : RTL description file,  200 : circuit design support apparatus,  210 : constraint information input accepting unit,  220 : binding data acquiring unit,  230 : external memory determining unit,  240 : external memory selecting unit,  250 : external memory interface generating unit,  260 : support data providing unit,  270 : support apparatus storage unit,  271 : constraint information,  272 : external memory determination result,  273 : external memory selection result,  274 : converted CDFG data,  280 : CDFG data acquiring unit,  2000 : memory module selecting unit