Patent Publication Number: US-9905700-B2

Title: Semiconductor device or memory device and driving method thereof

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     One embodiment of the present invention relates to a semiconductor device. 
     Note that one embodiment of the present invention is not limited to the above technical field. The technical field of one embodiment of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. One embodiment of the present invention also relates to a process, a machine, manufacture, or a composition of matter. Specifically, examples of the technical field of one embodiment of the present invention disclosed in this specification include a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a lighting device, a power memory device, a memory device, a method of driving any of them, and a method of manufacturing any of them. 
     In this specification and the like, a semiconductor device generally means a device that can function by utilizing semiconductor characteristics. A transistor and a semiconductor circuit are embodiments of semiconductor devices. In some cases, a memory device, a display device, or an electronic device includes a semiconductor device. 
     2. Description of the Related Art 
     Flash memories have been widely used as non-volatile memory devices (e.g., see Patent Document 1). 
     In recent years, new non-volatile memory devices have been suggested in which a transistor including an oxide semiconductor in the channel formation region (hereinafter, referred to as OS transistor) and a transistor including silicon in the channel formation region (hereinafter, referred to as Si transistor) are used in combination (e.g., see Patent Documents 2 and 3). 
     REFERENCES 
     Patent Documents 
     
         
         [Patent Document 1] Japanese Published Patent Application No. S57-105889 
         [Patent Document 2] United States Published Patent Application No. 2013/0228839 
         [Patent Document 3] United States Published Patent Application No. 2013/0221356 
       
    
     SUMMARY OF THE INVENTION 
     Flash memories need high voltage for injection of electric charge to the floating gate or for removal of the electric charge and also need a circuit for generating the high voltage. The injection or removal of electric charge takes a relatively long time, and accordingly data cannot be easily written or erased at high speed. 
     Furthermore, for a circuit configuration including an OS transistor and a Si transistor, a reduction in cell size and an increase in integration are demanded. 
     In view of the above problems, an object of one embodiment of the present invention is to provide a semiconductor device that can hold data. Another object is to provide a highly integrated semiconductor device. Another object is to provide a semiconductor device having a substantially unlimited number of write cycles. Another object is to provide a semiconductor device with low power consumption. Another object is to provide a semiconductor device with high reliability. Another object is to provide a semiconductor device with excellent data retention capability. Another object is to provide a semiconductor device in which data is written or read at high speed. Another object is to provide a novel semiconductor device or the like or a driving method thereof. 
     Note that the above objects do not exclude the existence of other objects. In one embodiment of the present invention, there is no need to achieve all the objects. Other objects will be apparent from and can be derived from the description of the specification, the drawings, the claims, and the like. 
     One embodiment of the present invention is a semiconductor device including a first semiconductor layer, a first gate insulating film over the first semiconductor layer, a first gate electrode over the first gate insulating film, a second semiconductor layer over the first gate electrode, a conductive layer over the second semiconductor layer, a second gate insulating film covering the second semiconductor layer and the conductive layer, and a second gate electrode covering at least part of a side surface of the second semiconductor layer with the second gate insulating film interposed therebetween. An end portion of the second semiconductor layer and an end portion of the conductive layer are substantially aligned with each other. 
     Another embodiment of the present invention is a semiconductor device including a first semiconductor layer, a pair of electrodes over the first semiconductor layer, an interlayer film including an opening portion over the pair of electrodes, a first gate insulating film in contact with a top surface of the first semiconductor layer in the opening portion, a first gate electrode over the first gate insulating film, a second semiconductor layer over the first gate electrode, a conductive layer over the second semiconductor layer, a second gate insulating film covering the second semiconductor layer and the conductive layer, and a second gate electrode covering at least part of a side surface of the second semiconductor layer with the second gate insulating film interposed therebetween. A top surface of the interlayer film, a top surface of the first gate insulating film, and a top surface of the first gate electrode are substantially aligned with each other. An end portion of the second semiconductor layer and an end portion of the conductive layer are substantially aligned with each other. 
     Another embodiment of the present invention is a semiconductor device including a first semiconductor layer, a first gate insulating film over the first semiconductor layer, a first gate electrode over the first gate insulating film, a second semiconductor layer over the first gate electrode, a conductive layer over the second semiconductor layer, a second gate insulating film covering the first gate electrode, the second semiconductor layer, and the conductive layer, and a second gate electrode covers at least part of a side surface of the second semiconductor layer with the second gate insulating film interposed therebetween. An end portion of the first gate electrode, an end portion of the second semiconductor layer, and an end portion of the conductive layer are substantially aligned with each other. 
     Another embodiment of the present invention is a method of driving a memory device including a first semiconductor layer, a first gate insulating film over the first semiconductor layer, a first gate electrode over the first gate insulating film, a second semiconductor layer over the first gate electrode, a conductive layer over the second semiconductor layer, a second gate insulating film covering the second semiconductor layer and the conductive layer, and a second gate electrode covering at least part of a side surface of the second semiconductor layer with the second gate insulating film interposed therebetween. The first gate electrode, the second semiconductor layer, and the conductive layer overlap with each other. In the method of driving the memory device, the conductive layer and the first gate electrode are brought into electrical contact with each other through the second semiconductor layer, so that data is written into the memory device. The electrical contact between the conductive layer and the first gate electrode are broken and then a potential of the conductive layer is changed, so that the data is read by capacitive coupling with the second semiconductor layer as a dielectric between the conductive layer and the first gate electrode. 
     The above semiconductor layer is preferably an oxide semiconductor layer. 
     The above oxide semiconductor layer preferably includes a crystal with c-axis alignment. 
     With one embodiment of the present invention, a semiconductor device that can hold data can be provided. Alternatively, a semiconductor device having a substantially unlimited number of write cycles can be provided. Alternatively, a semiconductor device with low power consumption can be provided. Alternatively, a semiconductor device with high reliability can be provided. Alternatively, a highly integrated semiconductor device can be provided. Alternatively, a semiconductor device with excellent data retention capability can be provided. Alternatively, a semiconductor device in which data is written or read at high speed can be provided. Alternatively, a novel semiconductor device or the like can be provided. 
     Note that the effects of one embodiment of the present invention are not limited to those listed above. The above effects do not exclude the existence of other effects. The other effects are the ones that are not described above and will be described below. The other effects will be apparent from and can be derived from the description of the specification, the drawings, and the like by those skilled in the art. One embodiment of the present invention has at least one of the above effects and the other effects. Hence, one embodiment of the present invention does not have all the above effects in some cases. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIGS. 1A to 1C  are circuit diagrams of semiconductor devices. 
         FIG. 2A  and  FIGS. 2B and 2C  are a top view and cross-sectional views of the semiconductor device. 
         FIGS. 3A to 3C  illustrate a method of manufacturing a semiconductor device. 
         FIGS. 4A to 4C  illustrate the method of manufacturing a semiconductor device. 
         FIGS. 5A and 5B  illustrate the method of manufacturing a semiconductor device. 
         FIGS. 6A and 6B  illustrate the method of manufacturing a semiconductor device. 
         FIGS. 7A and 7B  illustrate the method of manufacturing a semiconductor device. 
         FIGS. 8A and 8B  illustrate the method of manufacturing a semiconductor device. 
         FIGS. 9A and 9B  illustrate a method of manufacturing a semiconductor device. 
         FIGS. 10A and 10B  illustrate a method of manufacturing a semiconductor device. 
         FIGS. 11A and 11B  illustrate a method of manufacturing a semiconductor device. 
         FIGS. 12A and 12B  illustrate a method of manufacturing a semiconductor device. 
         FIG. 13  is a block diagram of a semiconductor device. 
         FIG. 14A  is a flowchart showing a fabrication process of an electronic component, and  FIG. 14B  is a schematic perspective view of the electronic component. 
         FIGS. 15A to 15C  illustrate electronic devices in which semiconductor devices can be used. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Embodiments are described with reference to drawings. However, the embodiments can be implemented with various modes. It will be readily appreciated by those skilled in the art that modes and details can be changed in various ways without departing from the spirit and scope of the present invention. Thus, the present invention should not be interpreted as being limited to the description of the embodiments. 
     In this specification and the like, ordinal numbers such as “first”, “second”, and “third” are used in order to avoid confusion among components. Thus, the terms do not limit the number or order of components. In the present specification and the like, a “first” component in one embodiment can be referred to as a “second” component in other embodiments or claims. Alternatively, in the present specification and the like, a “first” component in one embodiment can be referred to without the ordinal number in other embodiments or claims. 
     In the drawings, the same components, components having similar functions, components formed of the same material, or components formed at the same time are denoted by the same reference numerals in some cases, and the description thereof is not repeated in some cases. 
     (Embodiment 1) 
     In this embodiment, an example of a semiconductor device having a function of a memory device is described using drawings. 
       FIGS. 1A and 1B  are circuit diagrams of a semiconductor device (memory device) of one embodiment of the present invention which can hold stored data even when power is not supplied and which has a substantially unlimited number of write cycles. 
     A memory cell  100  in  FIGS. 1A and 1B  includes a first transistor  110  and a second transistor  120 . A gate electrode of the first transistor  110  is connected to one of a source electrode and a drain electrode of the second transistor  120 . One of a source electrode and a drain electrode of the first transistor  110  is connected to a first wiring  101 . The other of the source electrode and the drain electrode of the first transistor  110  is connected to a second wiring  102 . The other of the source electrode and the drain electrode of the second transistor  120  is connected to a third wiring  103 . A gate electrode of the second transistor  120  is connected to a fourth wiring  104 . 
     As the first transistor  110 , any of a variety of field effect transistors such as a Si transistor and an OS transistor can be used. As the second transistor  120 , a transistor having an extremely low off-state current can be used, and, for example, an OS transistor is preferably used. 
     Although detailed later, the second transistor  120  is turned on to charge carrier from the third wiring  103  to FG as schematically shown in  FIG. 1A , and the second transistor  120  is turned off to serve as a capacitor as schematically shown in  FIG. 1B . 
     Note that functions of a “source” and a “drain” of a transistor are sometimes replaced with each other when the transistor of opposite polarity is used or when the direction of flow of current is changed in circuit operation, for example. Therefore, the terms “source” and “drain” can be used to denote the drain and the source, respectively, in this specification. 
       FIG. 1C  shows an example of a circuit diagram of a semiconductor device formed using a plurality of memory cells  100  in  FIGS. 1A and 1B . 
     The semiconductor device in  FIG. 1C  includes a memory cell array including the plurality of memory cells  100  arranged in a matrix, a driver  130 , a driver  140 , a driver  150 , a driver  160 , a plurality of first wirings  101  electrically connected to the driver  130 , a plurality of second wirings  102  electrically connected to the driver  140 , a plurality of third wirings  103  electrically connected to the driver  150 , and a plurality of fourth wirings  104  electrically connected to the driver  160 . 
     As shown in  FIG. 1C , the first wiring  101 , the second wiring  102 , the third wiring  103 , and the fourth wiring  104  are electrically connected to each memory cell  100 . Thus, operation of each memory cell  100  can be controlled with the driver  130 , the driver  140 , the driver  150 , and the driver  160 . 
     When data is written into the memory cell  100 , the driver  160  selects any fourth wiring  104 , the driver  130  and the driver  140  apply equal voltages to any first wiring  101  and any second wiring  102 , respectively, and the driver  150  applies, to any third wiring  103 , a voltage lower than the equal voltages. 
     When data is read in the memory cell  100 , the driver  130  outputs a potential suitable for reading to the third wiring  103 , with the fourth wirings  104  unselected by the driver  140 . 
     The driver  130  and the driver  140  may include a decoder. 
     Each of the memory cells  100  in  FIG. 1C  is electrically connected to the wirings that are from the respective drivers  130 ,  140 ,  150 , and  160 ; the disclosed invention is not limited thereto. A plurality of wirings from any one or more of the driver circuits may be electrically connected to the memory cell  100 . Alternatively, a structure may be employed in which a wiring from any one of the driver circuits is not electrically connected to any one or more of the memory cells  100 . 
       FIG. 2A  is a top view of the semiconductor device described with reference to  FIGS. 1A to 1C , and  FIGS. 2B and 2C  are cross-sectional views thereof. In the following description, common components in the semiconductor device in  FIGS. 1A to 2C  are denoted by the same reference numerals. The relative sizes of the components of the semiconductor device are not limited to those shown in  FIGS. 2A to 2C . 
       FIG. 2A  is the top view, and  FIG. 2B  illustrates a cross section along the dash-dot line A 1 -A 2  in  FIG. 2A . Note that for simplification of the drawing, some components in the top view in  FIG. 2A  are not illustrated. The direction of the dash-dot line A 1 -A 2  can be referred to as channel length direction. 
       FIG. 2C  illustrates a cross section along the dash-dot line B 1 -B 2  in  FIG. 2A . The direction of the dash-dot line B 1 -B 2  can be referred to as channel width direction. 
     The semiconductor device shown in  FIGS. 2A to 2C  includes an insulating film  202  over a substrate  201 , a first oxide semiconductor layer  203  over the insulating film  202 , a conductive layer  205   a  and a conductive layer  205   b  over the first oxide semiconductor layer  203 , a first interlayer insulating film  204  over the conductive layer  205   a  and the conductive layer  205   b , a first gate insulating film  206  which is formed in an opening portion in the first interlayer insulating film  204  and in contact with a top surface of the first oxide semiconductor layer  203 , a first gate electrode  207  over the first gate insulating film  206 , a second oxide semiconductor layer  208  over the first gate electrode  207 , a conductive layer  209  over the second oxide semiconductor layer  208 , a second gate insulating film  210  over the conductive layer  209 , a second gate electrode  211  covering at least part of a side surface of the second oxide semiconductor layer  208  with the second gate insulating film  210  interposed therebetween, a second interlayer insulating film  212  over the second gate insulating film  210  and the second gate electrode  211 , a wiring  213   a  and a wiring  213   b  over the second interlayer insulating film  212 , a third interlayer insulating film  214  over the wiring  213   a  and the wiring  213   b , and a wiring  215   a  and a wiring  215   b  over the third interlayer insulating film  214 . 
     The wiring  213   a  and the wiring  213   b  are in contact with, respectively, the conductive layer  205   a  and the conductive layer  205   b  in opening portions in the first interlayer insulating film  204 , the second gate insulating film  210 , and the second interlayer insulating film  212 . The wiring  215   a  is in contact with the conductive layer  209  in an opening portion in the second gate insulating film  210 , the second interlayer insulating film  212 , and the third interlayer insulating film  214 . The wiring  215   b  is in contact with the second gate electrode  211  in an opening portion in the second interlayer insulating film  212  and the third interlayer insulating film  214 . 
     In the first transistor  110  described in this embodiment, a region functioning as the first gate electrode  207  is formed in a self-aligned manner so as to fill the opening portion in the first interlayer insulating film  204  and the like. Such a transistor can also be referred to as self-align s-channel FET (SA s-channel FET), trench-gate s-channel FET, or trench-gate self-align (TGSA) FET. 
     The first gate electrode  207  of the first transistor  110  also serves as one of the source electrode and the drain electrode of the second transistor  120 . In addition, the first oxide semiconductor layer  203 , the first gate electrode  207 , the second oxide semiconductor layer  208 , and the conductive layer  209  serving as the other of the source electrode and the drain electrode of the second transistor  120  are stacked. Thus, the semiconductor device can be highly integrated. 
     The second oxide semiconductor layer  208  and the conductive layer  209  are formed in one etching step with one mask, and accordingly, end portions of the layers are substantially aligned with each other, as shown in  FIG. 2B . 
     As shown in  FIG. 2C , the first gate electrode  207  is formed to electrically surround the first oxide semiconductor layer  203  in the channel width direction, so that a gate electric field is applied to the first oxide semiconductor layer  203  in the side surface direction in addition to the perpendicular direction. In other words, a gate electric field is applied to the entire first oxide semiconductor layer  203 . Current flows through the entire first oxide semiconductor layer  203 , leading to an increase in on-state current. 
     Next, components of the semiconductor device illustrated in  FIGS. 2A to 2C  are described in detail. 
     The substrate  201  is not limited to a simple supporting substrate, and may be a substrate where another device such as a transistor is formed. In that case, at least one of the first gate electrode  207 , the conductive layer  205   a , and the conductive layer  205   b  may be electrically connected to the above-described device. 
     The insulating film  202  can have a function of supplying oxygen to the first oxide semiconductor layer  203  as well as a function of preventing diffusion of impurities from the substrate  201 . For this reason, the insulating film  202  is preferably an insulating film containing oxygen and further preferably an insulating film containing oxygen in which the oxygen content is higher than that in the stoichiometric composition. In the case where the substrate  201  is provided with another device as described above, the insulating film  202  also has a function as an interlayer insulating film. In that case, the insulating film  202  is preferably subjected to planarization treatment such as chemical mechanical polishing (CMP) treatment so as to have a flat surface. 
     The first oxide semiconductor layer  203  and the second oxide semiconductor layer  208  preferably include a crystalline layer in which c-axes are aligned in the direction perpendicular to a surface of the insulating film  202 . 
     The thicknesses of the first oxide semiconductor layer  203  and the second oxide semiconductor layer  208  are each greater than or equal to 1 nm and less than or equal to 200 nm, preferably greater than or equal to 3 nm and less than or equal to 60 nm. 
     For the first oxide semiconductor layer  203  and the second oxide semiconductor layer  208 , for example, an In—Ga—Zn oxide whose atomic ratio of In to Ga and Zn is 1:1:1, 5:5:6, 3:1:2, or the like can be used. The first oxide semiconductor layer  203  and the second oxide semiconductor layer  208  may be formed using the same material or different materials and may be stacked oxide semiconductor layers. 
     Note that stable electrical characteristics can be effectively imparted to a transistor in which an oxide semiconductor layer serves as a channel by reducing the concentration of impurities in the oxide semiconductor layer to make the oxide semiconductor layer intrinsic or substantially intrinsic. The term “substantially intrinsic” refers to the state where an oxide semiconductor layer has a carrier density lower than 1×10 17  /cm 3 , preferably lower than 1×10 15  /cm 3 , further preferably lower than 1×10 13  /cm 3 , still further preferably lower than 1×10 8  /cm 3  and higher than or equal to 1×10 −9  /cm 3 . 
     In the oxide semiconductor layer, hydrogen, nitrogen, carbon, silicon, and a metal element other than a main component are impurities. For example, hydrogen and nitrogen form donor levels to increase the carrier density, and silicon forms impurity levels in the oxide semiconductor layer. The impurity level becomes a trap, which might cause deterioration of the electrical characteristics of the transistor. Therefore, the concentration of the impurities at an interface between the first oxide semiconductor layer  203  and the second oxide semiconductor layer  208  is preferably reduced. 
     In order to make the oxide semiconductor layer intrinsic or substantially intrinsic, in SIMS (secondary ion mass spectrometry), for example, the concentration of silicon at a certain depth of the oxide semiconductor layer or in a region of the oxide semiconductor layer is lower than 1×10 19  atoms/cm 3 , preferably lower than 5×10 18  atoms/cm 3 , more preferably lower than 1×10 18  atoms/cm 3 . Furthermore, the concentration of hydrogen at a certain depth of the oxide semiconductor layer or in a region of the oxide semiconductor layer is lower than or equal to 2×10 20  atoms/cm 3 , preferably lower than or equal to 5×10 19  atoms/cm 3 , further preferably lower than or equal to 1×10 19  atoms/cm 3 , still further preferably lower than or equal to 5×10 18  atoms/cm 3 . Furthermore, the concentration of nitrogen at a certain depth of the oxide semiconductor layer or in a region of the oxide semiconductor layer is lower than 5×10 19  atoms/cm 3 , preferably lower than or equal to 5×10 18  atoms/cm 3 , further preferably lower than or equal to 1×10 18  atoms/cm 3 , still further preferably lower than or equal to 5×10 17  atoms/cm 3 . 
     In addition, in the case where the oxide semiconductor layer includes a crystal, the crystallinity of the oxide semiconductor layer might be decreased if silicon or carbon is included at high concentration. In order not to lower the crystallinity of the oxide semiconductor layer, for example, the concentration of silicon at a certain depth of the oxide semiconductor layer or in a certain region of the oxide semiconductor layer is lower than 1×10 19  atoms/cm 3 , preferably lower than 5×10 18  atoms/cm 3 , further preferably lower than 1×10 18  atoms/cm 3 . Furthermore, the concentration of carbon at a certain depth of the oxide semiconductor layer or in a certain region of the oxide semiconductor layer is lower than 1×10 19  atoms/cm 3 , preferably lower than 5×10 18  atoms/cm 3 , further preferably lower than 1×10 18  atoms/cm 3 , for example. 
     A transistor in which a highly purified oxide semiconductor film is used for the channel formation region as described above has an extremely low off-state current. In the case where the voltage between the source and the drain is set to approximately 0.1 V, 5 V, or 10 V, for example, the off-state current standardized on the channel width of the transistor can be as low as several yoctoamperes per micrometer to several zeptoamperes per micrometer. 
     For the conductive layer  205   a  and the conductive layer  205   b , a conductive material that is easily bonded to oxygen is preferably used. For example, Al, Cr, Cu, Ta, Ti, Mo, or W can be used. Among the materials, in particular, it is preferable to use Ti, which is particularly easily bonded to oxygen, or W, which has a high melting point and thus makes subsequent process temperatures comparatively high. Note that the conductive material that is easily bonded to oxygen includes, in its category, a material to which oxygen is easily diffused. 
     When the conductive material that is easily bonded to oxygen is in contact with an oxide semiconductor layer, a phenomenon occurs in which oxygen in the oxide semiconductor layer is diffused to the conductive material that is easily bonded to oxygen. The phenomenon noticeably occurs when the temperature is high. Since the manufacturing process of the transistor involves a heat treatment step, the above phenomenon causes generation of oxygen vacancies in the vicinity of a region which is in the oxide semiconductor layer and is in contact with the source electrode layer or the drain electrode layer. Hydrogen slightly contained in the layer and the oxygen vacancies are bonded to each other, whereby the region is markedly changed to an n-type region. Accordingly, the n-type regions can serve as a source or a drain region of the transistor. 
     In the case of forming a transistor with an extremely short channel length, an n-type region which is formed by the generation of oxygen vacancies might extend in the channel length direction of the transistor. In that case, the electrical characteristics of the transistor change; for example, the threshold voltage is shifted, or on and off states of the transistor is difficult to control with the gate voltage (in which case the transistor is turned on). Accordingly, when a transistor with an extremely short channel length is formed, it is not always preferable that a conductive material that can be bonded to oxygen be used for a source electrode layer and a drain electrode layer. 
     In such a case, a conductive material that is less likely to be bonded to oxygen than the above material can be used for the conductive layer  205   a  and the conductive layer  205   b . As such a conductive material, for example, a material containing tantalum nitride, titanium nitride, gold, platinum, palladium, or ruthenium can be used. Note that the conductive material may be stacked with the above-described conductive material that is easily bonded to oxygen. 
     The first gate insulating film  206  and the second gate insulating film  210  can be formed using an insulating film containing one or more of aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. The first gate insulating film  206  and the second gate insulating film  210  may be formed using the same material or different materials. The first gate insulating film  206  and the second gate insulating film  210  may be a stack of any of the above materials. 
     For the first gate electrode  207  and the second gate electrode  211 , a conductive film formed of Al, Ti, Cr, Co, Ni, Cu, Y, Zr, Mo, Ru, Ag, Ta, W, or the like can be used. The first gate electrode  207  and the second gate electrode  211  may be formed using the same material or different materials. The first gate electrode  207  and the second gate electrode  211  may be a stack of any of the above materials or may be formed using a conductive film containing nitrogen. 
     For the first interlayer insulating film  204 , the second interlayer insulating film  212 , and the third interlayer insulating film, an oxide such as silicon oxide or aluminum oxide can be used. Alternatively, when silicon nitride, aluminum nitride, silicon oxynitride, or aluminum oxynitride is stacked over silicon oxide or aluminum oxide, the function as a protective film can be enhanced. The first interlayer insulating film  204 , the second interlayer insulating film  212 , and the third interlayer insulating film may be formed using the same material or different materials. The first interlayer insulating film  204 , the second interlayer insulating film  212 , and the third interlayer insulating film may be a stack of any of the above materials. 
     The wiring  213   a , the wiring  213   b , the wiring  215   a , and the wiring  215   b  are each formed to have a single-layer structure or a stacked-layer structure using any of metals such as aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum, and tungsten, or an alloy containing any of these metals as a main component. The wiring  213   a , the wiring  213   b , the wiring  215   a , and the wiring  215   b  may be formed using the same material or different materials. 
     In the semiconductor device of this embodiment as a memory device, writing is performed as follows: a voltage is applied to the second gate electrode  211  to bring the conductive layer  209  and the first gate electrode  207  into electrical contact with each other through the second oxide semiconductor layer  208 ; equal voltages are applied to the conductive layer  205   a  and the conductive layer  205   b ; and a voltage lower than the equal voltages is applied to the conductive layer  209  to charge carrier to the first gate electrode  207 . 
     In this memory device, reading is performed as follows. The voltage of the second gate electrode  211  is set to 0 V or to a voltage at which the off-state current of the second transistor  120  is sufficiently reduced (to 1 zA or less, for example) to break the electrical contact between the conductive layer  209  and the first gate electrode  207 . Then, when a voltage is applied to the conductive layer  209 , the voltage can be applied to the first gate electrode  207  and the channel in the first transistor  110  because the first gate electrode  207  and the conductive layer  209  are capacitively coupled through the second oxide semiconductor layer  208 . Thus, the conductive layer  209  functions as a control gate, and the second oxide semiconductor layer  208  functions as a dielectric. 
     At this time, the apparent threshold of the first transistor  110  (the first oxide semiconductor layer  203 ) depends on the amount of the charge in the first gate electrode  207  functioning as a floating gate. Thus, a detected difference in voltage or current between the source and the drain of the first transistor  110  (the first oxide semiconductor layer  203 ) due to the change in threshold shows the amount of the charge in the first gate electrode  207  (i.e., written data). 
     Since the off-state current of the transistor in which an oxide semiconductor film is used for the channel formation region is extremely low as described above, the electrical charge in the first gate electrode  207  functioning as a floating gate through the second transistor  120  does not leak much, so that the data can be held. As described above, the semiconductor of this embodiment can be used as a memory device. 
     In the memory device, the control gate and the floating gate are capacitively coupled through the second oxide semiconductor layer  208 , although they are capacitively coupled through a gate insulating film therebetween or the like in a conventional flash memory or the like. For example, in the case where indium gallium zinc oxide (IGZO) is used for the second oxide semiconductor layer  208 , since the dielectric constant (approximately 15) of IGZO is higher than the dielectric constant (approximately 4) of silicon oxide, which is mainly used for the gate insulating film, a reduction in capacitor area can be achieved due to the high dielectric constant of the capacitor, although depending on the thickness of the second oxide semiconductor layer  208 . 
     In this embodiment, one embodiment of the present invention is described. Other embodiments of the present invention are described in other embodiments. Note that one embodiment of the present invention is not limited thereto. That is, since various embodiments of the present invention are disclosed in this embodiment and the other embodiments, one embodiment of the present invention is not limited to a specific embodiment. For example, an example in which a channel formation region, source and drain regions, and the like of a transistor include an oxide semiconductor is described as one embodiment of the present invention; however, one embodiment of the present invention is not limited to this example. Depending on circumstances or conditions, various transistors or a channel formation region, a source region, a drain region, or the like of a transistor in one embodiment of the present invention may include various semiconductors. Depending on circumstances or conditions, for example, at least one of silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, an organic semiconductor, and the like may be included in various transistors, a channel formation region of a transistor, a source region or a drain region of a transistor, or the like of one embodiment of the present invention. Alternatively, for example, depending on circumstances or conditions, various transistors or a channel formation region, a source region, a drain region, or the like of a transistor in one embodiment of the present invention does not necessarily include an oxide semiconductor. 
     This embodiment can be combined with any of the other embodiments in this specification as appropriate. 
     (Embodiment 2) 
     In this embodiment, a method of manufacturing the semiconductor device described in Embodiment 1 is described with reference to  FIGS. 3A to 3C ,  FIGS. 4A to 4C ,  FIGS. 5A and 5B ,  FIGS. 6A and 6B ,  FIGS. 7A and 7B , and  FIGS. 8A and 8B . 
     For the substrate  201 , a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like can be used. Alternatively, a single crystal semiconductor substrate or a polycrystalline semiconductor substrate made of silicon, silicon carbide, or the like, a compound semiconductor substrate made of silicon germanium, a silicon-on-insulator (SOI) substrate, or the like can be used. Any of these substrates further provided with a semiconductor element thereover may be used. 
     The insulating film  202  is formed over the substrate  201 . The insulating film  202  can be formed by a plasma CVD method, a sputtering method, or the like using an oxide insulating film of aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, or the like; a nitride insulating film of silicon nitride, silicon nitride oxide, aluminum nitride, aluminum nitride oxide, or the like; or a film in which any of the above materials are mixed. Alternatively, a stack including any of the above materials can be used, and at least an upper layer in contact with the first oxide semiconductor layer  203  is preferably formed using a material containing excess oxygen which can serve as a supply source of oxygen to the first oxide semiconductor layer  203 . 
     Oxygen may be added to the insulating film  202  by an ion implantation method, an ion doping method, a plasma immersion ion implantation method, or the like. Adding oxygen enables the insulating film  202  to supply oxygen much easily to the first oxide semiconductor layer  203 . 
     In the case where a surface of the substrate  201  is made of an insulator and there is no influence of impurity diffusion to the first oxide semiconductor layer  203  to be formed later, the insulating film  202  is not necessarily provided. 
     Next, an oxide semiconductor film  303  to be the first oxide semiconductor layer  203  is deposited over the insulating film  202  by a sputtering method, a CVD method, an MBE method, an ALD method, or a PLD method. 
     An oxide semiconductor that can be used for the first oxide semiconductor layer preferably contains at least indium (In) or zinc (Zn). Both In and Zn are preferably contained. Furthermore, in order to reduce variations in the electrical characteristics of the transistor including the oxide semiconductor, the oxide semiconductor preferably contains a stabilizer in addition to In and Zn. 
     As a stabilizer, gallium (Ga), tin (Sn), hafnium (Hf), aluminum (Al), zirconium (Zr), and the like can be given. As another stabilizer, lanthanoid such as lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), or lutetium (Lu) can be given. 
     As the oxide semiconductor, for example, any of the following can be used: indium oxide, tin oxide, zinc oxide, an In—Zn oxide, a Sn—Zn oxide, an Al—Zn oxide, an Zn—Mg oxide, a Sn—Mg oxide, an In—Mg oxide, an In—Ga oxide, an In—Ga—Zn oxide, an In—Al—Zn oxide, an In—Sn—Zn oxide, a Sn—Ga—Zn oxide, an Al—Ga—Zn oxide, a Sn—Al—Zn oxide, an In—Hf—Zn oxide, an In—La—Zn oxide, an In—Ce—Zn oxide, an In—Pr—Zn oxide, an In—Nd—Zn oxide, an In—Sm—Zn oxide, an In—Eu—Zn oxide, an In—Gd—Zn oxide, an In—Tb—Zn oxide, an In—Dy—Zn oxide, an In—Ho—Zn oxide, an In—Er—Zn oxide, an In—Tm—Zn oxide, an In—Yb—Zn oxide, an In—Lu—Zn oxide, an In—Sn—Ga—Zn oxide, an In—Hf—Ga—Zn oxide, an In—Al—Ga—Zn oxide, an In—Sn—Al—Zn oxide, an In—Sn—Hf—Zn oxide, and an In—Hf—Al—Zn oxide. 
     For example, the term “In—Ga—Zn oxide” means an oxide containing In, Ga, and Zn as its main components. The In—Ga—Zn oxide may contain another metal element in addition to In, Ga, and Zn. Note that in this specification, a film containing the In—Ga—Zn oxide is also referred to as IGZO film. 
     Alternatively, a material represented by InMO 3 (ZnO) m  (m&gt;0 is satisfied, and m is not an integer) may be used. Note that M represents one or more metal elements selected from Ga, Y, Zr, La, Ce, and Nd. A material represented by In 2 SnO 5 (ZnO) n  (n&gt;0, n is an integer) may be used. 
     Note that the oxide semiconductor film is preferably formed by a sputtering method. As a sputtering method, an RF sputtering method, a DC sputtering method, an AC sputtering method, or the like can be used. 
     In the case where an In—Ga—Zn oxide is used for the first oxide semiconductor layer  203 , a material whose atomic ratio of In to Ga and Zn is any of 1:1:1, 2:2:1, 2:2:3, 3:1:2, 5:5:6, 1:3:2, 1:3:3, 1:3:4, 1:3:6, 1:4:3, 1:5:4, 1:6:6, 2:1:3, 1:6:4, 1:9:6, 1:1:4, and 1:1:2 can be used. 
     Note that the expression “the composition of an oxide containing In, Ga, and Zn at the atomic ratio, In:Ga:Zn=a:b:c (a+b+c=1), is in the neighborhood of the composition of an oxide containing In, Ga, and Zn at the atomic ratio, In:Ga:Zn=A:B:C (A+B+C=1)” means that a, b, and c satisfy the following relation: (a−A) 2 +(b−B) 2 +(c−C) 2 ≦r 2 , and r may be 0.05, for example. The same applies to other oxides. 
     The structure of the oxide semiconductor film is described below. 
     In this specification, the term “parallel” indicates that the angle formed between two straight lines is greater than or equal to −10° and less than or equal to 10°, and accordingly also includes the case where the angle is greater than or equal to −5° and less than or equal to 5°. The term “perpendicular” indicates that the angle formed between two straight lines is greater than or equal to 80° and less than or equal to 100°, and accordingly also includes the case where the angle is greater than or equal to 85° and less than or equal to 95°. 
     In this specification, trigonal and rhombohedral crystal systems are included in a hexagonal crystal system. 
     An oxide semiconductor film is classified roughly into a single-crystal oxide semiconductor film and a non-single-crystal oxide semiconductor film. The non-single-crystal oxide semiconductor film includes any of a c-axis aligned crystalline oxide semiconductor (CAAC-OS) film, a polycrystalline oxide semiconductor film, a microcrystalline oxide semiconductor film, an amorphous oxide semiconductor film, and the like. 
     First, a CAAC-OS film is described. 
     A CAAC-OS film is one of oxide semiconductor films having a plurality of crystal parts, and most of the crystal parts each fit inside a cube whose one side is less than 100 nm. Thus, there is a case where a crystal part included in the CAAC-OS film fits inside a cube whose one side is less than 10 nm, less than 5 nm, or less than 3 nm. 
     In a transmission electron microscope (TEM) image of the CAAC-OS film, a boundary between crystal parts, that is, a grain boundary is not clearly observed. Thus, in the CAAC-OS film, a reduction in electron mobility due to the grain boundary is less likely to occur. 
     In the cross-sectional TEM image of the CAAC-OS film observed in a direction substantially parallel to the sample surface, metal atoms arranged in a layered manner are seen in the crystal parts. Each metal atom layer has a morphology reflecting unevenness of a surface over which the CAAC-OS film is formed (hereinafter, a surface over which the CAAC-OS film is formed is referred to as a formation surface) or a top surface of the CAAC-OS film, and is arranged parallel to the formation surface or the top surface of the CAAC-OS film. 
     In contrast, according to the TEM image of the CAAC-OS film observed in a direction substantially perpendicular to the sample surface (plan-view TEM image), metal atoms are arranged in a triangular or hexagonal configuration in the crystal parts. However, there is no regularity of arrangement of metal atoms between different crystal parts. 
     From the results of the cross-sectional TEM image and the plan TEM image, alignment is found in the crystal parts in the CAAC-OS film. 
     A CAAC-OS film is subjected to structural analysis with an X-ray diffraction (XRD) apparatus. For example, when the CAAC-OS film including an InGaZnO 4  crystal is analyzed by an out-of-plane method, a peak appears frequently when the diffraction angle (2θ) is around 31°. This peak is derived from the (009) plane of the InGaZnO 4  crystal, which indicates that crystals in the CAAC-OS film have c-axis alignment, and that the c-axes are aligned in a direction substantially perpendicular to the formation surface or the top surface of the CAAC-OS film. 
     On the other hand, in analysis of the CAAC-OS film by an in-plane method in which an X-ray is incident on a sample in a direction substantially perpendicular to the c-axis, a peak appears frequently when 2θ is around 56°. This peak is derived from the (110) plane of the InGaZnO 4  crystal. Here, analysis (φ scan) is performed under conditions where the sample is rotated around a normal vector of a sample surface as an axis (φ axis) with 2θ fixed at around 56°. In the case where the sample is a single-crystal oxide semiconductor film of InGaZnO 4 , six peaks appear. The six peaks are derived from crystal planes equivalent to the (110) plane. In contrast, in the case of a CAAC-OS film, a peak is not clearly observed even when φ scan is performed with 2θ fixed at around 56°. 
     According to the above results, in the CAAC-OS film having c-axis alignment, while the directions of a-axes and b-axes are irregularly oriented between different crystal parts, the c-axes are aligned in a direction parallel to a normal vector of a formation surface or a normal vector of a top surface. Thus, each metal atom layer arranged in a layered manner observed in the cross-sectional TEM image corresponds to a plane parallel to the a-b plane of the crystal. 
     Note that the crystal part is formed concurrently with deposition of the CAAC-OS film or is formed through crystallization treatment such as heat treatment. As described above, the c-axis of the crystal is aligned in a direction parallel to a normal vector of a formation surface or a normal vector of a top surface of the CAAC-OS film. Thus, for example, in the case where a shape of the CAAC-OS film is changed by etching or the like, the c-axis might not be necessarily parallel to a normal vector of a formation surface or a normal vector of a top surface of the CAAC-OS film. 
     The degree of crystallinity in the CAAC-OS film is not necessarily uniform. For example, in the case where crystal growth leading to the CAAC-OS film occurs from the vicinity of the top surface of the film, the degree of the crystallinity in the vicinity of the top surface is higher than that in the vicinity of the formation surface in some cases. Furthermore, when an impurity is added to the CAAC-OS film, the crystallinity in a region to which the impurity is added is changed, and the degree of crystallinity in the CAAC-OS film varies depending on regions. 
     Note that when the CAAC-OS film with an InGaZnO 4  crystal is analyzed by an out-of-plane method, a peak of 2θ may also be observed at around 36°, in addition to the peak of 2θ at around 31°. The peak at 2θ of around 36° indicates that a crystal having no c-axis alignment is included in part of the CAAC-OS film. It is preferable that in the CAAC-OS film, a peak of 2θ appear at around 31° and a peak of 2θ not appear at around 36°. 
     The CAAC-OS film is an oxide semiconductor film having low impurity concentration. The impurity is an element other than the main components of the oxide semiconductor film, such as hydrogen, carbon, silicon, or a transition metal element. In particular, an element having higher strength of bonding to oxygen than a metal element included in the oxide semiconductor film, such as silicon, disturbs the atomic arrangement of the oxide semiconductor film by depriving the oxide semiconductor film of oxygen and causes a decrease in crystallinity. Furthermore, a heavy metal such as iron or nickel, argon, carbon dioxide, or the like has a large atomic radius (molecular radius), and thus disturbs the atomic arrangement of the oxide semiconductor film and causes a decrease in crystallinity when it is contained in the oxide semiconductor film. Note that the impurity contained in the oxide semiconductor film might serve as a carrier trap or a carrier generation source. 
     The CAAC-OS film is an oxide semiconductor film having a low density of defect states. In some cases, oxygen vacancies in the oxide semiconductor film serve as carrier traps or serve as carrier generation sources when hydrogen is captured therein. 
     The state in which impurity concentration is low and density of defect states is low (the number of oxygen vacancies is small) is referred to as “highly purified intrinsic” or “substantially highly purified intrinsic” state. A highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has few carrier generation sources, and thus can have a low carrier density. Thus, the transistor including the oxide semiconductor film rarely has negative threshold voltage (is rarely normally on). The highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has few carrier traps. Accordingly, the transistor including the oxide semiconductor film has little variation in electrical characteristics and high reliability. Electric charge trapped by the carrier traps in the oxide semiconductor film takes a long time to be released, and might behave like fixed electric charge. Thus, the transistor which includes the oxide semiconductor film having high impurity concentration and a high density of defect states has unstable electrical characteristics in some cases. 
     With the use of the CAAC-OS film in a transistor, variation in the electrical characteristics of the transistor due to irradiation with visible light or ultraviolet light is small. 
     Next, a microcrystalline oxide semiconductor film is described. 
     In an image obtained with a TEM, crystal parts cannot be found clearly in the microcrystalline oxide semiconductor film in some cases. In most cases, a crystal part in the microcrystalline oxide semiconductor film is greater than or equal to 1 nm and less than or equal to 100 nm, or greater than or equal to 1 nm and less than or equal to 10 nm. An oxide semiconductor film including nanocrystal (nc), which is a microcrystal with a size greater than or equal to 1 nm and less than or equal to 10 nm, or a size greater than or equal to 1 nm and less than or equal to 3 nm, is specifically referred to as nc-OS (nanocrystalline oxide semiconductor) film. In an image obtained with a TEM, a crystal grain cannot be found clearly in the nc-OS film in some cases. 
     In the nc-OS film, a microscopic region (for example, a region with a size greater than or equal to 1 nm and less than or equal to 10 nm, in particular, a region with a size greater than or equal to 1 nm and less than or equal to 3 nm) has a periodic atomic order. There is no regularity of crystal orientation between different crystal parts in the nc-OS film. Thus, the orientation of the whole film is not observed. Accordingly, in some cases, the nc-OS film cannot be distinguished from an amorphous oxide semiconductor depending on an analysis method. For example, when the nc-OS film is subjected to structural analysis by an out-of-plane method with an XRD apparatus using an X-ray having a diameter larger than the diameter of a crystal part, a peak which shows a crystal plane does not appear. Furthermore, a diffraction pattern like a halo pattern appears in an electron diffraction pattern (also referred to as selected-area electron diffraction pattern) of the nc-OS film obtained by using an electron beam with a probe diameter (e.g., larger than or equal to 50 nm) larger than the diameter of a crystal part. Meanwhile, spots are observed in an electron diffraction pattern (also referred to as nanobeam electron diffraction pattern) of the nc-OS film which is obtained using an electron beam with a probe diameter (e.g., 1 nm or larger and 30 nm or smaller) close to, or smaller than the diameter of a crystal part. Furthermore, in a nanobeam electron diffraction pattern of the nc-OS film, regions with high luminance in a circular (ring) pattern are shown in some cases. Also in a nanobeam electron diffraction pattern of the nc-OS film, a plurality of spots are shown in a ring-like region in some cases. 
     The nc-OS film is an oxide semiconductor film that has high regularity as compared to an amorphous oxide semiconductor film. Therefore, the nc-OS film is likely to have a lower density of defect states than an amorphous oxide semiconductor film. Note that there is no regularity of crystal orientation between different crystal parts in the nc-OS film. Therefore, the nc-OS film has a higher density of defect states than the CAAC-OS film. 
     Note that an oxide semiconductor film may be a stacked film including two or more films of an amorphous oxide semiconductor film, a microcrystalline oxide semiconductor film, and a CAAC-OS film, for example. 
     For example, the CAAC-OS film can be deposited by a sputtering method using a polycrystalline oxide semiconductor sputtering target. When ions collide with the sputtering target, a crystal region included in the sputtering target may be separated from the target along the a-b plane; in other words, a sputtered particle having a plane parallel to the a-b plane (flat-plate-like sputtered particle or pellet-like sputtered particle) may flake off from the sputtering target. The flat-plate-like sputtered particle or pellet-like sputtered particle is electrically charged and thus reaches the substrate while maintaining its crystal state, without being aggregation in plasma, forming a CAAC-OS film. 
     After the oxide semiconductor film  303  is formed, first heat treatment may be performed. The first heat treatment may be performed at a temperature higher than or equal to 250° C. and lower than or equal to 650° C., preferably higher than or equal to 300° C. and lower than or equal to 500° C., in an inert gas atmosphere, an atmosphere containing an oxidizing gas at 10 ppm or more, or a reduced pressure state. Alternatively, the first heat treatment may be performed in such a manner that heat treatment is performed in an inert gas atmosphere, and then another heat treatment is performed in an atmosphere containing an oxidizing gas at 10 ppm or more, in order to compensate desorbed oxygen. The first heat treatment can increase the crystallinity of the oxide semiconductor film  303  and remove impurities such as water and hydrogen from the insulating film  202 . 
     Next, a conductive film  304  to be the conductive layers  205   a  and  205   b  is formed over the oxide semiconductor film  303  (see  FIG. 3A ). For the conductive film  304 , any of the materials described for the conductive layers  205   a  and  205   b  can be used. For example, a 100-nm-thick titanium film is formed by a sputtering method or the like. Alternatively, a tungsten film may be formed by a CVD method. 
     Next, the oxide semiconductor film  303  and the conductive film  304  are etched into an island shape to form the first oxide semiconductor layer  203  and a conductive layer  305  (see  FIG. 3B ). 
     Next, the first interlayer insulating film  204  is formed over the conductive layer  305  (see  FIG. 3C ). For the first interlayer insulating film  204 , any of the materials described for the first interlayer insulating film  204  in Embodiment 1 can be used. 
     Next, after a resist mask  220  is formed, an opening portion is formed in the first interlayer insulating film  204 , and thus the conductive layer  305  is etched so as to be divided over the first oxide semiconductor layer  203  to form the conductive layer  205   a  and the conductive layer  205   b  (see  FIG. 4A ). At this time, the conductive layer  305  may be over-etched, in which case the first oxide semiconductor layer  203  is partly etched. 
     Next, over the first interlayer insulating film  204 , an insulating film  406  to be the first gate insulating film  206  and a conductive film  407  to be the first gate electrode  207  are formed (see  FIG. 4B ). For the insulating film  406 , any of the materials described for the first gate insulating film  206  in Embodiment 1 can be used. The insulating film  406  can be formed by a sputtering method, a CVD method, an MBE method, an ALD method, a PLD method, or the like. For the conductive film  407 , any of the materials described for the first gate electrode  207  in Embodiment 1 can be used. 
     Next, the insulating film  406  and the conductive film  407  are etched by a chemical mechanical polishing (CMP) method or the like until a surface of the first interlayer insulating film  204  is exposed, whereby the first gate insulating film  206  and the first gate electrode  207  are formed (see  FIG. 4C ). 
     Next, the second oxide semiconductor layer  208  and the conductive layer  209  are formed over the first gate electrode  207  (see  FIG. 5A ). A cross section of the state in  FIG. 5A  in the channel width direction is illustrated in  FIG. 7A . For the second oxide semiconductor layer  208 , a material similar to the materials described for the second oxide semiconductor layer  208  in Embodiment 1 can be used. For the conductive layer  209  Al, Cr, Cu, Ta, Ti, Mo, W, or an alloy material containing any of these as a main component can be used. The conductive layer  209  may be a stacked layer including any of the above materials. 
     Next, the second gate insulating film  210  and a conductive film  501  are stacked in this order over the conductive layer  209  (see  FIG. 5B ). A cross section of the state in  FIG. 5B  in the channel width direction is illustrated in  FIG. 7B . For the second gate insulating film  210 , a material similar to the materials described for the second gate insulating film  210  in Embodiment 1 can be used. For the conductive film  501 , a material similar to the materials described for the conductive layer  209  in Embodiment 1 can be used. 
     Since the second oxide semiconductor layer  208  and the conductive layer  209  are formed in one etching step with one mask, end portions of the layers are aligned with each other and the layers can be favorably covered with the second gate insulating film  210 . Even if a stacked layer of the second oxide semiconductor layer  208  and the conductive layer  209  is thick, formation defects are less likely to be caused. Thus, higher yield in the fabrication process can be achieved. 
     Next, after a resist mask  230  is formed, etch-back is performed to process the conductive film  501  into the second gate electrode  211  covering a side surface of the second oxide semiconductor layer  208  with the second gate insulating film  210  interposed therebetween (see  FIG. 6A ). A cross section of the state in  FIG. 6A  in the channel width direction is illustrated in  FIG. 8A   
     Next, the second interlayer insulating film  212  is formed over the second gate electrode  211 . Then, opening portions are formed in the first interlayer insulating film  204 , the second gate insulating film  210 , and the second interlayer insulating film  212 . Over the second interlayer insulating film and in the opening portions, the wiring  213   a  and the wiring  213   b  are formed to be connected to the conductive layer  205   a  and the conductive layer  205   b , respectively. Then, the third interlayer insulating film  214  is formed over the wirings  213   a  and  213   b , and the wirings  215   a  and  215   b , which are shown not in the cross section of  FIG. 6B  in the channel length direction but in the cross section of  FIG. 2C  in the channel width direction, are formed over the third interlayer insulating film  214  (see  FIG. 6B ). A cross section of the state in  FIG. 6B  in the channel width direction is illustrated in  FIG. 8B . For the second interlayer insulating film  212  and the third interlayer insulating film  214 , materials similar to those described for the second interlayer insulating film  212  and the third interlayer insulating film  214  in Embodiment 1 can be used. For the wiring  213   a  and the wiring  213   b , materials similar to those described for the wiring  213   a  and the wiring  213   b  in Embodiment 1 can be used. For the wiring  215   a  and the wiring  215   b , materials similar to those described for the wiring  215   a  and the wiring  215   b  in Embodiment 1 can be used. 
     Through the above steps, the transistors  110  and  120  illustrated in  FIGS. 2A to 2C  can be manufactured. 
     This embodiment can be combined with any of the other embodiments in this specification as appropriate. 
     (Embodiment 3) 
     In this embodiment, a semiconductor device which has a structure different from that of the semiconductor device of Embodiment 1 is described with reference to  FIGS. 9A and 9B .  FIG. 9A  is a cross-sectional view in the channel length direction and  FIG. 9B  is a cross-sectional view in the channel width direction. 
     A difference from the semiconductor device of Embodiment 1 is that a second gate electrode  721  covers a side surface of an upper layer of the second oxide semiconductor layer  208  with the second gate insulating film  210  interposed therebetween and also covers side and top surfaces of the conductive layer  209  with the second gate insulating film  210  interposed therebetween. 
     For the second gate electrode  721 , a material similar to the materials described for the second gate electrode  211  can be used. 
     This embodiment can be combined with any of the other embodiments in this specification as appropriate. 
     (Embodiment 4) 
     In this embodiment, a semiconductor device which has a structure different from that of the semiconductor device of Embodiment 1 is described with reference to  FIGS. 10A and 10B .  FIG. 10A  is a cross-sectional view in the channel length direction and  FIG. 10B  is a cross-sectional view in the channel width direction. 
     Differences from the semiconductor device of Embodiment 1 are that a first protective film  801  is formed between the conductive layer  205   a  and the first interlayer insulating film  204  and between the conductive layer  205   b  and the first interlayer insulating film  204 , a second protective film  802  is formed between the first interlayer insulating film  204  and the second gate insulating film  210 , and a third protective film  803  is formed over the second gate insulating film  210  and the second gate electrode  211  and under the second interlayer insulating film  212 . As each of the above protective films, a silicon nitride film, a silicon nitride oxide film, an aluminum oxide film, an aluminum nitride film, or the like can be used. 
     This embodiment can be combined with any of the other embodiments in this specification as appropriate. 
     (Embodiment 5) 
     In this embodiment, a semiconductor device which has a structure different from that of the semiconductor device of Embodiment 1 is described with reference to  FIGS. 11A and 11B .  FIG. 11A  is a cross-sectional view in the channel length direction and  FIG. 11B  is a cross-sectional view in the channel width direction. 
     After a first gate insulating film  901  is formed over the conductive layers  205   a  and  205   b , a first gate electrode  902 , a second oxide semiconductor layer  903 , and a conductive layer  904  are stacked in this order. In the semiconductor device having such a structure, the first gate electrode  902 , the second oxide semiconductor layer  903 , and the conductive layer  904  can be formed in one etching step with one mask. Consequently, end portions of the first gate electrode  902 , the second oxide semiconductor layer  903 , and the conductive layer  904  are substantially aligned with each other, as illustrated in  FIGS. 11A and 11B . Accordingly, the process can be simplified and the productivity can be improved. 
     Next, a second gate insulating film  905  is formed over the conductive layer  904 , and a second gate electrode  906  is formed. 
     For the first gate insulating film  901 , the first gate electrode  902 , the second oxide semiconductor layer  903 , the conductive layer  904 , the second gate insulating film  905 , and the second gate electrode  906 , materials similar to those described for the first gate insulating film  206 , the first gate electrode  207 , the first oxide semiconductor layer  203 , the conductive layer  209 , the second gate insulating film  210 , and the second gate electrode  211  can be used. 
     This embodiment can be combined with any of the other embodiments in this specification as appropriate. 
     (Embodiment 6) 
     In this embodiment, a semiconductor device which has a structure different from that of the semiconductor device of Embodiment 1 is described with reference to  FIGS. 12A and 12B .  FIG. 12A  is a cross-sectional view in the channel length direction and  FIG. 12B  is a cross-sectional view in the channel width direction. 
     A difference from the semiconductor device of Embodiment 1 is that a first metal oxide layer  1001  over the insulating film  202 , a second metal oxide layer  1002  over the first metal oxide layer  1001 , and a third metal oxide layer  1003  over the second metal oxide layer  1002  are provided. The third metal oxide layer  1003  is formed in an opening portion in the first interlayer insulating film  204  and between the second metal oxide layer  1002  and the first gate insulating film  206 . 
     The second metal oxide layer is more like a semiconductor than the first metal oxide layer and the third metal oxide layer are. The first metal oxide layer and the third metal oxide layer are more like an insulator than the second metal oxide layer is. 
     For the first metal oxide layer  1001 , the second metal oxide layer  1002 , and the third metal oxide layer  1003 , materials similar to the materials described for the first oxide semiconductor layer  203  in Embodiment 2 can be used. The first metal oxide layer  1001  and the third metal oxide layer  1003  preferably contain the same metal element as one or more of the metal elements contained in the second metal oxide layer  1002 . 
     (Embodiment 7) 
     In this embodiment, a CPU including the memory device described in Embodiment 1 is described. 
       FIG. 13  is a block diagram illustrating a configuration example of a CPU partly including the memory device described in Embodiment 1. 
     The CPU illustrated in  FIG. 13  includes, over a substrate  1190 , an arithmetic logic unit (ALU)  1191 , an ALU controller  1192 , an instruction decoder  1193 , an interrupt controller  1194 , a timing controller  1195 , a register  1196 , a register controller  1197 , a bus interface  1198  (BUS I/F), a rewritable ROM  1199 , and a ROM interface (ROM I/F)  1189 . A semiconductor substrate, an SOI substrate, a glass substrate, or the like is used as the substrate  1190 . The ROM  1199  and the ROM interface  1189  may be provided over a separate chip. Needless to say, the CPU in  FIG. 13  is just an example in which the configuration is simplified, and an actual CPU may have a variety of configurations depending on the application. For example, the CPU may have the following configuration: a structure including the CPU illustrated in  FIG. 13  or an arithmetic circuit is considered as one core; a plurality of the cores are included; and the cores operate in parallel. The number of bits that the CPU can process in an internal arithmetic circuit or in a data bus can be 8, 16, 32, or 64, for example. 
     An instruction that is input to the CPU through the bus interface  1198  is input to the instruction decoder  1193  and decoded therein, and then, input to the ALU controller  1192 , the interrupt controller  1194 , the register controller  1197 , and the timing controller  1195 . 
     The ALU controller  1192 , the interrupt controller  1194 , the register controller  1197 , and the timing controller  1195  conduct various controls in accordance with the decoded instruction. Specifically, the ALU controller  1192  generates signals for controlling the operation of the ALU  1191 . While the CPU is executing a program, the interrupt controller  1194  determines an interrupt request from an external input/output device or a peripheral circuit on the basis of its priority or a mask state, and processes the request. The register controller  1197  generates an address of the register  1196 , and reads/writes data from/to the register  1196  in accordance with the state of the CPU. 
     The timing controller  1195  generates signals for controlling operation timings of the ALU  1191 , the ALU controller  1192 , the instruction decoder  1193 , the interrupt controller  1194 , and the register controller  1197 . For example, the timing controller  1195  includes an internal clock generator for generating an internal clock signal based on a reference clock signal, and supplies the internal clock signal to the above circuits. 
     In the CPU illustrated in  FIG. 13 , a memory cell is provided in the register  1196 . For the memory cell of the register  1196 , the transistors described in the above embodiments can be used. 
     In the CPU illustrated in  FIG. 13 , the register controller  1197  selects operation of retaining data in the register  1196  in accordance with an instruction from the ALU  1191 . That is, the register controller  1197  selects whether data is retained by a flip-flop or by a capacitor in the memory cell included in the register  1196 . When data retaining by the flip-flop is selected, a power supply voltage is supplied to the memory cell in the register  1196 . When data retaining by the capacitor is selected, the data is rewritten in the capacitor, and supply of power supply voltage to the memory cell in the register  1196  can be stopped. 
     This embodiment can be combined with any of the other embodiments in this specification as appropriate. 
     (Embodiment 8) 
     In this embodiment, examples in which the memory device described in any of the above embodiments is used as an electronic component are described using  FIGS. 14A and 14B . 
       FIG. 14A  shows an example where the memory device described in any of the above embodiments is used as an electronic component. Note that the electronic component is also referred to as semiconductor package or IC package. This electronic component has various standards and names corresponding to the direction of terminals or the shape of terminals; hence, one example of the electronic component is described in this embodiment. 
     A memory device including the transistors  110  and  120  described in Embodiment 1 with reference to  FIGS. 2A to 2C  is completed through an assembly process (post-process) of integrating detachable components on a printed board. 
     The post-process can be completed through the steps in  FIG. 14A . Specifically, after an element substrate obtained in the preceding process is completed (Step S 1 ), a back surface of the substrate is ground (Step S 2 ). The substrate is thinned in this step to reduce substrate warpage or the like caused in the preceding process and to reduce the size of the component. 
     After the back surface of the substrate is ground, a dicing step is performed to divide the substrate into a plurality of chips. Then, the divided chips are separately picked up, placed on a lead frame, and bonded thereto in a die bonding step (Step S 3 ). In the die bonding step, the chip is bonded to the lead frame by an appropriate method depending on products, for example, bonding with a resin or a tape. Note that in the die bonding step, a chip may be placed on and bonded to an interposer. 
     Next, wire bonding for electrically connecting a lead of the lead frame and an electrode on the chip through a metal wire is performed (Step S 4 ). As the metal wire, a silver wire or a gold wire can be used. Ball bonding or wedge bonding can be used as the wire bonding. 
     The wire-bonded chip is subjected to a molding step of sealing the chip with an epoxy resin or the like (Step S 5 ). Through the molding step, the inside of the electronic component is filled with a resin, whereby damage to a mounted circuit portion and wire caused by external mechanical force as well as deterioration of characteristics due to moisture or dust can be reduced. 
     Subsequently, the lead of the lead frame is plated. Then, the lead is cut and processed (Step S 6 ). This plating process prevents rust of the lead and facilitates soldering at the time of mounting the chip on a printed board in a later step. 
     Next, printing (marking) is performed on a surface of the package (Step S 7 ). After a final testing step (Step S 8 ), the electronic component is completed (Step S 9 ). 
     The above-described electronic component includes the memory device described in any of the above embodiments. Thus, the electronic component which achieves higher-speed operation and a smaller size can be obtained. 
       FIG. 14B  is a perspective schematic diagram illustrating a quad flat package (QFP) as an example of the completed electronic component. An electronic component  700  in  FIG. 14B  includes a lead  701  and a circuit portion  703 . The electronic component  700  in  FIG. 14B  is mounted on a printed board  702 , for example. A plurality of electronic components  700  which are combined and electrically connected to each other over the printed board  702  can be mounted on an electronic device. A completed circuit board  704  is provided in an electronic device or the like. 
     This embodiment can be combined with any of the other embodiments in this specification as appropriate. 
     (Embodiment 9) 
     In this embodiment, examples of an electronic device that can include any of the memory device, the transistors, the CPU, and the like (e.g., a DSP, a custom LSI, a PLD, and an RF-ID) described in the above embodiments are described. 
     The transistor, the memory device, and the CPU and the like described in the above embodiments can be applied to a variety of electronic devices (including game machines). Examples of the electronic devices include display devices such as televisions and monitors, lighting devices, personal computers, word processors, image reproduction devices, portable audio players, radios, tape recorders, stereos, phones, cordless phones, mobile phones, car phones, transceivers, wireless devices, game machines, calculators, portable information terminals, electronic notebooks, e-book readers, electronic translators, audio input devices, video cameras, digital still cameras, electric shavers, IC chips, high-frequency heating appliances such as microwave ovens, electric rice cookers, electric washing machines, electric vacuum cleaners, air-conditioning systems such as air conditioners, dishwashers, dish dryers, clothes dryers, futon dryers, electric refrigerators, electric freezers, electric refrigerator-freezers, freezers for preserving DNA, radiation counters, and medical equipment such as dialyzers and X-ray diagnostic equipment. The examples of the electronic devices also include alarm devices such as smoke detectors, heat detectors, gas alarm devices, and security alarm devices. The examples also include industrial equipment such as guide lights, traffic lights, belt conveyors, elevators, escalators, industrial robots, and power storage systems. Furthermore, moving objects and the like driven by fuel engines and electric motors using power from non-aqueous secondary batteries are also included in the category of electronic devices. Examples of the moving objects are electric vehicles (EV), hybrid electric vehicles (HEV) which include both an internal-combustion engine and a motor, plug-in hybrid electric vehicles (PHEV), tracked vehicles in which caterpillar tracks are substituted for wheels of these vehicles, motorized bicycles including motor-assisted bicycles, motorcycles, electric wheelchairs, golf carts, boats, ships, submarines, helicopters, aircrafts, rockets, artificial satellites, space probes, planetary probes, and spacecrafts. Some specific examples of these electronic devices are illustrated in  FIGS. 15A to 15C . 
     In a television set  8000  illustrated in  FIG. 15A , a display portion  8002  is incorporated in a housing  8001 . The display portion  8002  can display an image and a speaker portion  8003  can output sound. A memory device including the transistors  110  and  120  of one embodiment of the present invention can be used for a driver circuit for operating the display portion  8002 . 
     In addition, the television set  8000  may include a CPU  8004  for performing information communication or a memory. For the CPU  8004  and the memory, a CPU or a memory device including the transistors  110  and  120  of one embodiment of the present invention can be used. 
     An alarm device  8100  illustrated in  FIG. 15A  is a residential fire alarm, and includes a smoke or heat sensor portion  8102  and a microcomputer  8101 . The microcomputer  8101  is an example of an electronic device including any of the transistors, the memory device, and the CPU described in the above embodiments. 
     An air conditioner that includes an indoor unit  8200  and an outdoor unit  8204  illustrated in  FIG. 15A  is an example of an electronic device including any of the transistors, the memory device, the CPU, and the like described in the above embodiments. Specifically, the indoor unit  8200  includes a housing  8201 , an air outlet  8202 , a CPU  8203 , and the like. Although the CPU  8203  is provided in the indoor unit  8200  in  FIG. 15A , the CPU  8203  may be provided in the outdoor unit  8204 . Alternatively, the CPU  8203  may be provided in each of the indoor unit  8200  and the outdoor unit  8204 . When the transistors  110  and  120  described in the above embodiments are used for the CPU in the air conditioner, reduction in power consumption of the air conditioner can be achieved. 
     An electric refrigerator-freezer  8300  illustrated in  FIG. 15A  is an example of an electronic device including any of the transistors, the memory device, the CPU, and the like described in the above embodiments. Specifically, the electric refrigerator-freezer  8300  includes a housing  8301 , a door for a refrigerator  8302 , a door for a freezer  8303 , a CPU  8304 , and the like. In  FIG. 15A , the CPU  8304  is provided in the housing  8301 . When the transistors  110  and  120  described in the above embodiments are used for the CPU  8304  of the electric refrigerator-freezer  8300 , power consumption of the electric refrigerator-freezer  8300  can be reduced. 
       FIGS. 15B and 15C  illustrate an example of an electric vehicle that is an example of an electric device. An electric vehicle  9700  is equipped with a secondary battery  9701 . The output of electric power of the secondary battery  9701  is adjusted by a circuit  9702  and the electric power is supplied to a driving device  9703 . The circuit  9702  is controlled by a processing unit  9704  including a ROM, a RAM, a CPU, or the like that is not illustrated. When the transistors  110  and  120  described in the above embodiments are used for the CPU in the electric vehicle  9700 , power consumption of the electric vehicle  9700  can be reduced. 
     In the driving device  9703 , a DC motor or an AC motor is included either alone or in combination with an internal-combustion engine. The processing unit  9704  outputs a control signal to the circuit  9702  based on input data such as data on operation (e.g., acceleration, deceleration, or stop) by a driver or data during driving (e.g., data on an upgrade or a downgrade, or data on a load on a driving wheel) of the electric vehicle  9700 . The circuit  9702  adjusts the electric energy supplied from the secondary battery  9701  in accordance with the control signal of the processing unit  9704  to control the output of the driving device  9703 . In the case where the AC motor is mounted, although not illustrated, an inverter, which converts direct current into alternate current, is also incorporated. 
     This embodiment can be combined with any of the other embodiments in this specification as appropriate. 
     This application is based on Japanese Patent Application serial no. 2015-050624 filed with Japan Patent Office on Mar. 13, 2015, the entire contents of which are hereby incorporated by reference.