Patent Publication Number: US-2003229841-A1

Title: Reed-solomon decoder

Description:
FIELD OF THE INVENTION  
       [0001] The invention pertains generally to error detection/correction and more particularly to systems and methods used in Reed-Solomon decoders.  
       BACKGROUND OF THE INVENTION  
       [0002] A commonly used error correcting technique is a Reed-Solomon error correcting code. Using Reed-Solomon (RS) terminology, fixed-length (n) codewords are transmitted, each codeword comprising k information symbols and n−k appended error correcting (parity) symbols. Each symbol comprises s bits. An RS decoder can correct up to (n−k)/2 symbols that contain errors in a codeword.  
       [0003] Because each of these correctable symbols may contain multiple bit-errors, the RS encoding technique is particularly well suited for burst errors that affect multiple contiguous bits. A common RS encoding scheme uses a codeword of 255 eight-bit symbols, 223 of which are information symbols, and the remaining 32 symbols are error correcting parity symbols. This encoding scheme will correct up to 16 erroneous symbols in every 255-bit codeword, thereby providing a substantial improvement with respect to the ‘received’ Bit Error Rate.  
       [0004] The RS encoding scheme will also detect ‘erasures’, which are errors at known locations, and require less information to correct. The number of erasures plus twice the number of errors that an RS decoder can correct is (n−k)/2.  
       [0005] For ease of reference, the term ‘error’ is used hereinafter to refer to either an error of unknown location or an erasure of known location.  
       [0006]FIG. 1 illustrates an example block diagram of a prior art RS decoder  100 . The decoder  100  receives each codeword r(x)  101 , and produces a corrected codeword c(x)  151 . A syndrome calculator  110  processes the codeword  101  to produce corresponding syndrome polynomials S i (x)  111 . Each codeword has n−k syndromes that depend only on errors, and not on the transmitted codeword. From these syndromes  111 , an error locator polynomial Δ(x)  121  is produced. Euclid&#39;s algorithm  120  is illustrated for providing the error locator polynomial  121 , and an error magnitude polynomial Ω(x)  122 , although other techniques, such as the Berlekamp-Massey algorithm can be used as well. Each RS code has a parameter ‘α’ that is the primitive element of a Galois Field (FG) that is chosen for the RS code. The error locator polynomial is structured such that if an error occurs at position p, α −p  will be a root of the error polynomial (p is indexed from 0 to n−1).  
       [0007] An iterative approach is conventionally applied to test each value of α −p  for each position p in the codeword, to determine of α −p  is a root,  
         X   K     -   1       ,                 
 
       [0008] of the error locator polynomial  121 . A commonly used algorithm for this iterative test is the Chien error locator  130 . The Chien locator  130  also provides a related error differential term,  
           X   K     -   1              Δ   ′          (     X   K     -   1       )          132     ,                 
 
       [0009] that facilitates a determination of the magnitude  141  of the error, typically via the Forney error determination algorithm, as illustrated at block  140 .  
       [0010] The error determinator  140  evaluates the error magnitude polynomial  122  corresponding to the located error symbol. For each error that the error locator  130  locates, an error corrector  150  determines the corrected codeword c(x)  151 , based on the location  131  and magnitude  141  of this error. If an error is not detected for a given symbol, the symbol in the corrected codeword c(x)  151  at this evaluated position is equal to the symbol in the received codeword r(x)  101 .  
       [0011] WO-A-01/39378 shows a Reed-Solomon decoder that simultaneously searches for m roots of the error locator polynomial and the error magnitude polynomial. A polynomial evaluator includes a plurality of slice elements corresponding to each term of the polynomial. Each slice element includes a plurality of coefficient multipliers that are configured to evaluate the term for different values, thereby effecting a simultaneous evaluation of the polynomial at each of these different values.  
       [0012] US-B-6 279 137 shows a system and method for a storage-efficient parallel Chien search. The system determines the root of a polynomial by employing a parallel structure that implements a Chien Search and reduces the amount of storage required.  
       [0013] The location of an error in a codeword can be derived from the root of an error locator polynomial. The performance of the Chien Search is enhanced by the parallel structure, and the location of the error can be easily determined using a simple calculation that preferably includes the cycle count, the parallelism, and the index of the multiplier/summer rank that indicates a root. Multiple ranks of multipliers receive data stored in a single array of data storage units. Multiplier values of each multiplier are based on the elements of a Galois Field.  
       [0014] EP-A-1 102 406 shows a decoder circuit used for decoding Reed-Solomon codes. A decoder is provided which performs concurrent execution of a Chien search that determines the error locator polynomial for a received code word and a Forney algorithm that computes the error pattern.  
       [0015] US-B-6 347 389 shows a pipelined Reed-Solomon error/erasure decoder processes multiple code words in a pipelined fashion. The pipelined Reed-Solomon error/erasure decoder is designed to process Reed-Solomon encoded words that have been corrupted in a digital system by processing errors as well as erasures through a simple iterative modified syndrome process.  
       SUMMARY OF THE INVENTION  
       [0016] A problem to be solved by the invention is to provide an improved Reed-Solomon decoder and an improved method for Reed-Solomon decoding. Further, to provide an improved electronic system including a Reed-Solomon decoder, such as a DVD system.  
       [0017] In essence, the invention provides for improved Reed-Solomon decoding by combining a parallel Chien search with a modified serial Forney&#39;s computation. This enables to reduce the required hardware complexity of the decoder while increasing decoder performance.  
       [0018] In accordance with the invention, the error positions only are calculated in the parallel Chien search block. In a CD or DVD system, the erasure locations need not to be calculated in the Chien search as they are already known from the demodulation block of the CD or DVD system.  
       [0019] Because the erasure locations, which are commonly referred to as ‘roots’, are known, it is possible to reduce the complexity of the parallel Chien search logic. This implies that the Chien search logic has only to evaluate the error locator polynomial Δ(x).  
       [0020] The error locations and the roots that correspond to these error locations are known after evaluation of the error locator polynomial. Preferably the roots are stored in a shift register.  
       [0021] The hardware complexity is further reduced by the use of a modified serial Forney&#39;s algorithm. The high performance of the combined Chien and Forney&#39;s blocks enables to perform multiple-pass error corrections, which essentially decreases the output error rate.  
       [0022] The inventive Reed-Solomon decoder can be utilized in many electronic systems, such as DVD systems or other optical or magnetic storage systems.  
       [0023] In principle, the inventive method is suited for Reed-Solomon decoding and includes the steps of:  
       [0024] calculating a syndrome polynomial S(x) and an erasure locator polynomial Γ(x);  
       [0025] calculating a modified syndrome polynomial T(x)=S(x)Γ(x)mod2t, where t is the symbol-error correcting capability of the Reed-Solomon code;  
       [0026] performing Euclid&#39;s algorithm for calculating an error locator polynomial Δ(x) and an error evaluator polynomial Ω(x);  
       [0027] performing a parallel Chien search and concurrently computing an error/erasure locator polynomial Ψ(x)=Δ(x)Γ(x);  
       [0028] serially computing the error magnitudes according to Forney&#39;s equation.  
       [0029] In principle the inventive Reed-Solomon decoder includes:  
       [0030] means for calculating a syndrome polynomial S(x) and an erasure locator polynomial Γ(x);  
       [0031] means for calculating a modified syndrome polynomial T(x)=S(x)Γ(x)mod2t, wherein t is the symbol-error correcting capability of the Reed-Solomon code;  
       [0032] means for performing Euclid&#39;s algorithm to calculate an error locator polynomial Δ(x) and an error evaluator polynomial Ω(x);  
       [0033] means for computing an error/erasure locator polynomial Ψ(x)=Δ(x)Γ(x);  
       [0034] means for performing a parallel Chien search;  
       [0035] means for serially computing error magnitudes according to Forney&#39;s equation.  
       [0036] Advantageous additional embodiments of the invention are disclosed in the respective dependent claims. 
     
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
     [0037] Exemplary embodiments of the invention are described with reference to the accompanying drawings, which show in:  
     [0038]FIG. 1 example block diagram of a prior art error correcting decoder;  
     [0039]FIG. 2 example block diagram of a parallel Chien search circuit in accordance with the invention;  
     [0040]FIG. 3 example block diagram of a circuit for serial computation of Forney&#39;s equation in accordance with the invention. 
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS  
     [0041] The below listed definitions are used:  
                                                      Error locator polynomial:   Δ(x)           Erasure locator polynomial:   Γ(x)           Error / Erasure locator polynomial:   Ψ(x)           Error position:   i l , . . . ,i v             Error locations:   X 1  = a 1     l               Error values:   e k , 0 &lt;= k &lt; n           Erasure positions:   j l , . . . ,j f             Erasure locators:   Y 1 = a   j     l               Erasure values:   f k , 0 &lt;= k &lt; n                      
 
     [0042] The Reed-Solomon decoding can be considered as employing five steps.  
     [0043] Step 1:  
     [0044] Reed-Solomon decoding starts with calculating a syndrome polynomial S(x):  
         S        (   x   )       =       ∑     i   =   1       2      t              S   i          x   i                       
 
     [0045] Further an erasure locator polynomial Γ(x) is calculated, where  
         Γ        (   x   )       =       ∏     i   =   1     p          (     1   -     x                   a     j   i           )                     
 
     [0046] Thereby the erasure locations (roots) are found.  
     [0047] Step 2:  
     [0048] A modified syndrome polynomial T(x)=S(x)Γ(x) mod 2t is calculated, where t is the symbol-error correcting capability of the Reed-Solomon code.  
     [0049] Step 3:  
     [0050] Euclid&#39;s algorithm is used, which is a method for finding the greatest common divisor of two polynomials, cf. Y. M. Sugiyama, S. H. Kasahara, and T. Namekawa, “A Method for Solving the Key Equation for Decoding of Goppa Codes”, Information and Control, Volume 27, pp. 87-89, January 1975. Both the error locator polynomial Δ(x) and the error evaluator polynomial Ω(x) can be calculated using Euclid&#39;s algorithm. This is as such known from the prior art, cf. Steven B. Wicker, Vijay K. Bhargava, “Reed-Solomon codes and their applications”, IEEE Press 1994.  
     [0051] Step 4:  
     [0052] Next, the error locations are computed using a parallel Chien block. At the same time a new error/erasure locator polynomial Ψ(x)=Δ(x)Γ(x) is computed to increase the performance of RS decoder. This is a particular advantage of the invention.  
     [0053] Step 5:  
     [0054] The coefficients of a new error/erasure polynomial are loaded into the registers of a serial Forney&#39;s block, and the error/erasure magnitude values are computed.  
     [0055] The erasure locations (roots) are already known after carrying out step 1, or are obtained by means of the demodulation block of the CD or DVD system. Therefore the erasure locations need not be calculated in the Chien search of step 5. Advantageously, because the erasure locations are known one can reduce the complexity of the parallel Chien search logic, i.e. the Chien search logic needs to evaluate the error locator polynomial Δ(x) only. Advantageously, error locator polynomial Δ(x) has nine coefficients only. The error locations and the roots that correspond to these error locations are known after evaluation of this error locator polynomial.  
     [0056]FIG. 2 illustrates a parallel Chien search logic that comprises four ranks. Each cycle of the Chien search logic will check corresponding four trial roots in parallel:  
     [0057] Rank 0 of the Chien search logic searches for roots in every fourth field element that is defined by a sequence of field elements α 0 , α −4 , α −8 , and so on (i.e. error locations 0, 4, 8, . . . in a code word).  
     [0058] Rank 1 of the Chien search logic searches for roots in every fourth field element that is defined by a sequence of field elements α −3 , α −7 , α −11 , and so on (i.e. error locations 3, 7, 11, . . . in a code word).  
     [0059] Rank 2 of the Chien search logic searches for roots in every fourth field elements that is defined by a sequence of field elements α 2 , α −6 , α −10 , and so on (i.e. error locations 2, 6, 10, . . . in a code word).  
     [0060] Rank 3 of the Chien search logic searches for roots in every fourth field elements that is defined by a sequence of field elements α 1 , α −5 , α −9 , and so on (i.e. error locations 1, 5, 9, . . . in a code word).  
     [0061] The Galois Field counter GFC defines the power of the GF element. During initialisation, the α 0  element is loaded into the register. In each cycle (clock CLK) counter GFC is counted down.  
     [0062] If comparator comp1 indicates zero then the multiplication product in multiplier MUL 33  of the current power from counter GFC and the α −1  element is the root of the error locator polynomial. If comparator comp2 indicates zero then the multiplication product in multiplier MUL 34  of the current power from counter GFC and the α −2  element is the root of the error locator polynomial. If comparator comp3 indicates zero then the multiplication product in multiplier MUL 35  of the current power from counter GFC and the α −3  element is the root of the error locator polynomial. If comparator comp4 indicates zero then counter GFC defines the roots.  
     [0063] The shift register SHR 1  (in FIG. 3) is used to memorize the roots that correspond to the erasure or the error location. During Step  1  of the decoding process the roots that correspond to the erasure locations are memorized in the SHR 1  registers. The depth of SHR 1  register is 16. This is enough for memorizing all the errors and erasures that are decoded in a RS codeword of a CD or DVD system.  
     [0064] During Step  3  the error locator polynomial Δ(x) is computed and its nine coefficients are loaded into the registers REG 1  to REG 9  of the parallel Chien search block depicted in FIG. 2. These registers are clocked by clock CLK. Their output values are fed within each of the four ranks to a chain of multipliers MUL* and adders ADD*. The output of the rank 3 chain is fed to comparator comp1. The output of the rank 2 chain is fed to comparator comp2. The output of the rank 1 chain is fed to comparator comp3. The output of the rank 0 chain is fed to comparator comp4. The output of register REG 1  to REG 8  is in each case fed via a multiplicator MUL 32  to MUL 25 , respectively, applying in each case a factor α −32 , α −28 , α −24 , α −20 , . . . , α −4 , respectively.  
     [0065] The error locators are found during the evaluation of the error locator polynomial in the Chien search. The values of the inverse of the error locators are output from MUL 33 , MUL 34 , MUL 35 , and GF counter. These locations of the errors are loaded into the above SHR 1  registers.  
     [0066]FIG. 3 illustrates the block for calculating an error and erasure magnitude value at various symbol positions, yielding an error or erasure pattern. This block implements the modified Forney algorithm (serial implementation). The error magnitude values and the erasure magnitude values given by the modified Forney algorithm are  
                   e     i   k       =           Ω                   (     X   k     -   1       )           X   k     -   1              Ψ   ′          (     X   k     -   1       )                         and                   f     i   k         =       Ω        (     Y   k     -   1       )           Y   k     -   1              Ψ   ′          (     Y   k     -   1       )               ,                        (   1   )                       
 
     [0067] where  
       Ω                   (     X   K     -   1       )                   
 
     [0068] is the error evaluator polynomial Ω(x) evaluated at  
       x   =       X   K     -   1                     and                     Ψ   ′          (     X   K     -   1       )                       
 
     [0069] is the formal derivative Ψ′(x) of the error/erasure locator polynomial Ω(x) evaluated at  
       x   =       X   K     -   1                     or                 where                 Ω                   (     Y   K     -   1       )                     
 
     [0070] is the error evaluator polynomial Ω(x) evaluated at  
       x   =       Y   K     -   1       .                   
 
     [0071] The Ω(x)and Ψ′(x) polynomials are expressed below:  
     Ω( x )=Ω 0 +Ω 1   x +Ω 2   x   2 + . . . +Ω 15   x   15   (2)  
     Ψ′( x )=Ψ 1 +Ψ 3   x   2 +Ψ 5   x   4 + . . . +Ψ 15   x   14   (3)  
     [0072] The coefficients of an error evaluator polynomial (Ω 0  to Ω 15 ) are loaded into respective registers REG 0  to REG 15 . The coefficients Ψ1 to Ψ15 of the first derivation Ψ′(x) of an error/erasure polynomial Ψ(x) are loaded into the respective registers REG 16  to REG 23 . These registers as well as registers REG 0  to REG 15  are clocked by clock CLK.  
     [0073] Afterwards the root x, which corresponds to an erasure or an error location, is output from register SHR 1  and input in the Forney block. In a chain of multipliers MUL 0  to MUL 13  the degrees x 1 , x 2 , x 3 , . . . , x 15  of x are calculated from x. The coefficients Ω1 to Ω15 are multiplied by the respective degrees x 1 , x 2 , x 3 , . . . , x 15  of the current root x using respective multipliers MUL 14  to MUL 29 . In each cycle the set of 15 products is summed up by respective adders ADD 2  to ADD 15 . Additionally, in ADD  1  the value Ω0 is added to the first product. The output of adder A 3 D 15  is the result of the evaluation of the error evaluator polynomial Ω(x) at a current root  
       x   =       X   K     -   1       .                   
 
     [0074] The coefficients Ψ1, Ψ3, Ψ5, . . . , Ψ15 are multiplied with corresponding degrees x 1 , x 3 , x 5 , . . . , x 15  of the current root x by respective multipliers MUL 30  to MUL 37 . In each cycle of clock CLK, the set of products of these multipliers is summed up by respective adders ADD 16  to ADD 22 . The output of ADD 22  is the result of the evaluation of the error/erasure polynomial Ψ(x) at the current root  
       x   =       X   k     -   1       .                   
 
     [0075] If in equations (1) a multiplication is used instead of a division they look like  
                 e     i   k       =         Ω        (     X   k     -   1       )              (       X   k     -   1              Ψ   ′          (     X   k     -   1       )         )       -   1                       f     i   k         =       Ω        (     Y   k     -   1       )              (       Y   k     -   1              Ψ   ′          (     Y   k     -   1       )         )       -   1                                (   4   )                       
 
     [0076] The product Xk−1 Ψ′(Xk−1) from the output of adder ADD 22  is inverted in an GF inverter GFI and multiplied in a multiplier MUL 38  with above output value of adder ADD  15 , resulting in error magnitude e i     k    and erasure magnitude f i     k   , respectively. The calculated erasure or error magnitude values are output from multiplier MUL 38  and stored in a register SHR 2 . This register has the same depth as register SHR 1 . All roots, that have been stored in register SHR 1 , are processed in the Forney block in the same way. The calculated magnitude values are memorized in register SHR 2 .  
     [0077] Advantageously, the inventive Chien&amp;Forney stages used for determining error locations and error values in a DVD-system, require the following minimum hardware only: Chien search block: 36 multipliers, 32 adders, 9 registers, 4 comparators and 1 GF counter.  
     [0078] Forney block: 38 multipliers, 22 adders, 24 registers and 1 GF inverter,  
     [0079] whereas known Chien&amp;Forney stages require the following minimum hardware:  
     [0080] Chien search block: 34 multipliers, 31 adders, 33 registers, 1 comparator, 1 counter and 1 inverter.  
     [0081] Forney block: 136 multipliers, 124 adders, 33 registers, 4 comparators, 4 counters and 4 inverters.  
     [0082] In the invention 67 cycles only for outer code and 62 cycles only for the inner code are required to calculate the error/erasure locations and the error/erasures magnitudes. This is much faster when compared to conventional Chien and Fourney blocks.  
     [0083] The invention can be utilized for any electronic system that requires error determination and/or correction, such as CD, DVD, blue-laser DVD (Blu-Ray) or other storage systems. The invention enables to decrease the number of cycles needed to compute the error locations and the error values and at the same time requires hardware of relatively low complexity only.