Patent Publication Number: US-2012025293-A1

Title: Semiconductor memory device having a floating gate and a control gate and method of manufacturing the same

Description:
CROSS-REFERENCE TO RELATED APPLICATION(S) 
     This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2010-172739, filed on Jul. 30, 2010, the entire contents of which are incorporated herein by reference. 
     FIELD 
     Embodiments described herein relate generally to a semiconductor memory device and to a method of manufacturing the semiconductor memory device. 
     BACKGROUND 
     A NAND flash memory is known as a semiconductor memory device. The NAND flash memory is provided with nonvolatile memory elements having a floating gate and a control gate respectively. As to the NAND flash memory, requirement of writing and reading speed-up is increasing. In order to meet the requirement, the voltage ratio (coupling ratio) of the following two voltages needs to be raised. One of the voltages is a voltage which is applied between the control gate electrode and the floating gate electrode. The other of the voltages is a voltage which is applied between the floating gate electrode and a channel region of a semiconductor substrate. 
     For the purpose of raising the coupling ratio, the height of an element isolation region is set to be lower than that of an upper surface of a floating gate. Consequently, the contact area between an inter-gate insulating film and the floating gate can be increased and a control gate electrode can be embedded between floating gates. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a functional block diagram of a NAND flash memory according to a first embodiment. 
         FIG. 2  is a circuitry diagram of a portion of a memory cell array shown in  FIG. 1 . 
         FIG. 3  is a schematic and enlarged view of a section of the memory cell array which is taken along an A-A line of  FIG. 2 . 
         FIG. 4  is an enlarged view of a portion of a section of the memory cell array which is taken along a B-B line of  FIG. 2 . 
         FIG. 5  is an enlarged plane view of a portion C of the memory cell array which is shown in  FIG. 2 . 
         FIGS. 6A-6L  show respective sections of a semiconductor substrate which are obtained in steps of a method of manufacturing the NAND flash memory according to the first embodiment. 
         FIG. 7  shows a capacitance network of the NAND flash memory according to the first embodiment. 
         FIG. 8  is a sectional view of the semiconductor substrate to show a displacement of contacts. 
         FIGS. 9A-9G  show respective sections of a semiconductor substrate which are obtained in steps of a method of manufacturing the NAND flash memory according to a second embodiment. 
         FIG. 10  shows a portion of a section of a NAND flash memory according to a third embodiment. 
         FIG. 11  shows a portion of a section of a NAND flash memory according to a fourth embodiment. 
     
    
    
     DETAILED DESCRIPTION 
     According to one embodiment, a semiconductor memory device having a memory cells and word lines is provided. The memory cells are formed in a semiconductor layer and arranged in matrix. Each of the memory cells has a floating gate and a control gate. Each plurality of the memory cells is connected in series in a row direction. Each of the word lines is connected to each plurality of the control gates in a column direction. First and second intervals are provided for the memory cells alternately in the column direction. The second interval is larger than the first interval. 
     Hereinafter, further embodiments will be described with reference to the drawings. In the drawings, the same reference numerals denote the same or similar portions respectively. 
     For explanatory convenience, in the description of the embodiments, directions i.e. relative positional relationships for indicating up and down, right and left, high and low, or deep and shallow are mentioned as those determined according to a back surface side of a semiconductor substrate. Accordingly, in some parts of the description, the directions may be shown as different from those determined according to a gravity direction. In  FIGS. 3-11 , portions such as a front or back surface of a semiconductor memory device which are not important for explaining the embodiments may be omitted. 
     A NAND flash memory according to a first embodiment will be described with reference to  FIG. 1 . 
       FIG. 1  is a functional block diagram of the NAND flash memory. In a memory cell array  1  shown in  FIG. 1 , a plurality of memory cells is arranged in matrix. 
     A row decoder  2  is provided to select and drive word lines and selection gate lines respectively provided in the memory cell array  1 . A column decoder  3  is provided to select bit lines provided in the memory cell array  1 . 
     A high voltage generating unit  4  is provided to boost a power supply voltage supplied from outside. The high voltage generating unit  4  supplies a boosted voltage to the memory cells of the memory cell array  1 , the row decoder  2  and the column decoder  3 , when data stored in each memory cell is read, data is written into each memory cell, or data stored in each memory cell is erased. “High voltage” means a voltage which is larger than a supply voltage provided from outside and which is necessary for reading, writing and erasing. A control unit  5  controls the row decoder  2 , the column decoder  3  and the high voltage generating unit  4 , and has a function to control the memory cell array  1  through these decoders and the high voltage generating unit. 
     Further, the control unit  5  has a function to perform receiving commands from the exterior of the NAND flash memory and to perform outputting data to the exterior. The memory cell array  1 , the row decoder  2 , the column decoder  3 , the high voltage generating unit  4  and the control unit  5  are formed on a semiconductor substrate  100  described below. 
       FIG. 2  shows a portion of circuit configuration of the memory cell array  1  formed on the semiconductor substrate. The memory cell array  1  has a plurality of blocks.  FIG. 2  shows a block  11 , and portions of blocks  11   i−1  and  11   i+1 . “i” represents an arbitrary integer. 
     Each of the blocks  11   0 - 11   x  is provided with a plurality of NAND memory cell units. In  FIG. 2 , the NAND memory cell units  12   0 - 12   k  are provided in the block  11   i+1 . “k” is an arbitrary integer and is “4224”, for example. 
     Each of the NAND memory cell units is provided with a plurality of memory cells  13   0 - 13   65 . These memory cells are arranged to store data.  FIG. 2  shows that the memory cells  13   0 - 13   65  are arranged in the NAND memory cell unit  12   k . Each of the memory cells  13   0 - 13   65  is composed of a nonvolatile memory transistor having a floating gate and a control gate. 
     The memory cells  13   0 - 13   65  are connected in series. Each source of the memory cells is connected with a drain of adjacent one of the memory cells. First one to third ones of the memory cells  13   0 - 13   65  connected in series and arranged from both ends of the NAND memory cell units  12   k  may be used as dummy cells. The dummy cells store invalid data respectively. For example, the memory cells  13   0  and  13   65  of the first row from the both ends may be used as the dummy cells respectively. Or the memory cells  13   0 - 13   2  and  13   63 - 13   65  of the first to third row from the both ends may be used as dummy cells respectively. 
     Each of the NAND memory cell units  12   0 - 12   k  is further provided with selection gate transistors  14  and  15 . The selection gate transistors  14  are connected in series with the drains of the memory cells  13   0  connected in series with the others of the memory cells  13   0 - 13   65 , respectively. The selection gate transistors  15  are connected in series with the sources of the memory cells  13   65  connected in series with the others of the memory cells  13   0 - 13   65 , respectively. The NAND memory cell units  12   0 - 12   k  are selected by the selection gate transistors  14 ,  15  respectively. 
     The control gates of the nonvolatile memory transistors of the ones of the memory cells  13   0 - 13   65  which are arranged in each column are connected commonly to each of a plurality of word lines  16   0 - 16   65 . Specifically, among the memory cells  13   0 - 13   65  disposed in matrix, the memory cells of the NAND memory cell units  12   0 - 12   k  which are arranged in a column direction perpendicular to a series-connection direction of the memory cells, i.e. a row direction memory cell are connected commonly to each of a plurality of the word lines  16   0 - 16   65 . The portions of the word lines  16   0 - 16   65  corresponding to the positions of the memory cells functions as control gates. 
     Accordingly, when the memory cells  13   0 - 13   65  are connected in series in a block  11   i  as mentioned above, each 66 of the memory cells arranged in the column direction is connected commonly to each of the word lines  16   0 - 16   65 . 
     In each of page areas  21   0 - 21   65 , ones of the memory cells connected to each of the word lines  16   0 - 16   65  are arranged respectively. Each of page areas  21   0 - 21   65  includes the memory cells of the number of the NAND memory cell units in each block (“k+1” in  FIG. 2 ). For example, in a case of k=4224, 4096 memory cells may be used for a storage area, and 128 memory cells may be used for a redundancy area and another area. 
     Drains of the nonvolatile memory transistors constituting the memory cells  13   0 - 13   65  are connected to bit lines  19   0 - 19   k  respectively. The gates of the selection gate transistors  14  arranged in each column are commonly connected to each selection gate line  17 . Each drain of the selection gate transistors  14  is connected to each of the bit lines  19   0 - 19   k . 
     The gates of the selection gate transistors  15  arranged in each column are commonly connected to each selection gate lines  18 . The sources of the selection gate transistors  15  arranged in each column are commonly connected to each source line  20 . The source lines  20  are shared by ones of the blocks which adjoin in the column direction. 
       FIG. 3  is a schematic view of a structure of a section of the memory cell array  1  formed on the semiconductor substrate. The section is taken along a line A-A shown in  FIG. 2 . 
     The memory cells  13   0 - 13   65  have a stacked gate structure where a floating gate  22  and a portion of word line  16   n  which functions as a control gate are laminated via an insulating film on a P type semiconductor layer  25   a  formed in a N type semiconductor substrate  25 . 
     The memory cells  13   0 - 13   65  are connected in series in the column direction. For example, a source and a drain of a nonvolatile memory transistor constituting one of the memory cells  13   0  are respectively connected to a drain of an adjacent nonvolatile memory transistor constituting one of the memory cells  13   1  and a source  23   a1  of one of the selection gate transistors  14 . Further, a drain and a source of a nonvolatile memory transistor constituting one of the memory cells  13   65  are respectively connected to a source of an adjacent nonvolatile memory transistor constituting one of the memory cells  13   64  and a drain  23   b1  of one of the selection gate transistors  14 . 
     A drain  23   a2  of the one of the selection gate transistors  14  is connected to a bit line  19   0  via a contact plug  24   a . A source  23   b2  of the one of the selection gate transistors  15  is connected to a source line  20  via a contact plug  24   b . 
     The sources and drains of the nonvolatile memory transistors constituting memory cells  13   0  including the source  23   a1 ,  23   b2 , and the drain  23   a2 ,  23   b1 , can be formed by implanting ions into the P type layer  25   a  formed in the semiconductor substrate  25 . The floating gate  22 , a portion of the word line  16 , which functions as a control gate, and the contact plug  24   a ,  24   b  are embedded in an insulating layer  50 . The bit lines  19   0 - 19   k  are covered with the insulating film  51 . 
       FIG. 4  shows an enlarged and schematic view of a portion of a section of the memory cell array shown in  FIG. 2 . The section is taken along a line B-B shown in  FIG. 2 .  FIG. 4  shows six memory cells  13   n  of  FIG. 2 . 
     The memory cells  13   n  are electrically separated by element isolation insulating layers  26  including first and second element isolation layers  26   1 ,  26   2  respectively. Specifically, in the embodiment, the memory cells  13   n  are electrically separated using an STI structure. A silicon oxide film, which is deposited in the interiors of trenches formed in the semiconductor substrate  25  (the P type semiconductor layer  25   a ), can be used for the element isolation insulating layers  26 . 
     The widths of the first and second element isolation layers  26   1 ,  26   2  are different in the column direction. The first and second element isolation layers  26   1 ,  26   2  are arranged alternately and repeatedly in the column direction. The width of the second element isolation layer  26   2  is larger in the column direction than that of the first element isolation layer  26   1 . The memory cells  13   n  are formed so that a first interval W 1  and a second interval W 2  may be provided alternately and repeatedly among the memory cells. The first interval W 1  corresponds to the width of the first element isolation layer  26   1 . The second interval W 2  corresponds to the width of the second element isolation layer  26 . 
     The height of the first element isolation layer  26   1  is larger than that of the second element isolation layer  26   2 . The heights of the first element isolation layer  26   1  and the second element isolation layer  26   2  are larger than that of an upper surface of a tunnel insulating film  27 . 
     The height of the second element isolation layer  26   2  is smaller than that of a portion of an upper surface of the floating gate  22  which has a largest height. Accordingly, the portions  54  shown in  FIG. 3  which function as control gates, i.e. portions of the word line  16   n  is filled in a space between the floating gates  22  corresponding to the width of the second element isolation layer  26   2 . The word line  16   n  (the control gates) is formed via an inter-gate insulating film  28  on the first and second element isolation layers  26   1 ,  26   2  and the floating gate  22 . 
       FIG. 5  shows a positional relationship among the word lines  16   63 - 16   65 , the selection gate lines  18 , and active areas  56  in a portion C of the memory cell array  1  surrounded by a dotted line in  FIG. 2 . In each of the active areas  56 , a source, a drain and a channel region are formed.  FIG. 5  shows the active areas  56 , the word line  16   63 - 16   65 , one of the selection gate lines  18  and the first and second element isolation layers  26   1 ,  26   2 , and the other configurations are omitted to be shown, for explanatory convenience. 
     Each of the active areas  56  is formed between each of the first element isolation layers  26   1  and each of the second element isolation layers  26   2 . The active areas  26  are formed so that the first and the second intervals W 1 , W 2  may be provided alternately and repeatedly among the active areas. Accordingly, the active areas of the selection gate transistors shown in  FIGS. 2 ,  3  are formed so that the first and the second intervals W 2  may be provided alternately and repeatedly among the active areas. 
       FIGS. 6A-6L  show enlarged sectional views of a semiconductor substrate in respective steps of an example of a method of manufacturing the NAND flash memory according to the first embodiment. Each of  FIGS. 6A-6J  corresponds to a portion of the B-B section shown in  FIG. 2 .  FIG. 6K  corresponds to a portion of the A-A section shown in  FIG. 2 .  FIG. 6L  corresponds to a portion of a section taken along a line D-D shown in  FIG. 2 . 
     As shown in  FIG. 6A , a tunnel insulating film  27  and a floating gate layer  22  are formed in the order on a P type semiconductor layer  25   a  of a semiconductor substrate  25 . 
     A substrate composed of a semiconductor material such as silicon, or a substrate having a semiconductor region formed in the surface area, such as a SOI wafer, may be used as the semiconductor substrate  25 . A silicon oxide film formed by a thermal oxidation process, a plasma oxidation process or a CVD process may be used as the tunnel insulating film  27 . A poly-silicon film formed by a CVD process, for example, may be used as the floating gate layer  22 . 
     Then, a mask material is formed to provide the element isolation insulating layers  26  shown in  FIG. 4 . In order to form the mask material, a method of forming a mask material with a width equal to or smaller than that limited with lithography. The method may be, for example, a so-called “Double Patterning” which uses a side wall transfer method. 
     As shown in  FIG. 6B , a mask material  30  and a hard mask material  31  are formed on the floating gate layer  22 . The mask material  30  and the hard mask material  31  are used to form the first element isolation layers  26   1  shown in  FIG. 4 . A silicon nitride film or a silicon oxide film can be used as the mask material  30 . The silicon nitride film or the silicon oxide film may be formed using a CVD process, for example. A silicon oxide film, a silicon nitride film or an amorphous silicon film can be used as the hard mask material  31 . These films may be formed using a CVD process, for example. 
     As shown in  FIG. 6C , a resist pattern  32  is formed to pattern the hard mask material  31 . The resist pattern  32  can be formed using a photolithographic method. The pitch of the resist pattern  32  is double as large as that of the memory cells  13   n . The double pitch is a total length of the first interval W 1  and the second interval W 2 . 
     As shown in  FIG. 6D , the hard mask material  31  is etched by using the resist pattern  32  as a mask, and then the resist pattern  32  is removed. The etching of the hard mask material  31  can be performed using an anisotropic etching such as an RIE. 
     As shown in  FIG. 6E , slimming of the etched hard mask material  31  is carried out. The width of the hard mask material  31  after the slimming corresponds to the width of the element isolation layers  26   1 , and is a width of the first interval W 1  after correction of errors such as an etching conversion difference caused by manufacturing processes. One of the errors is an etching conversion difference, for example. Specifically, the width of the hard mask material  31  after the slimming may be 25% or less of the width of the resist pattern  32 , for example. 
     As shown in  FIG. 6F , a side wall film  33  is formed on a side surface of the hard mask material  31 . The side wall material  33  functions as a mask at the time of forming the element isolation layers  26   1 ,  26   2 . In order to form the side wall film  33 , a side wall material is formed to cover the floating gate layer  22 , the mask material  30  and the hard mask material  31  as a whole after the slimming of the hard mask material  31 . After forming the side wall material, the side wall film  33  is formed using the following etching process, for example. 
     A silicon nitride film, a silicon oxide film, or an amorphous silicon film respectively formed by CVD can be employed for the side wall film  33 . Such a film has a material characteristic which indicates a sufficient processing selection ratio at the time of etching the hard mask material  31 . An etching process such as RIE which leaves a portion of the side wall material on the hard mask material  31  may be used for etching the side wall material. The interval between portions of the hard mask material  31  after the etching corresponds to the width of the element isolation layer  26   2 . The interval exists on the opposite side of the hard mask material  31 . The interval is a width of the second interval W 2  after correction of errors such as an etching conversion difference caused by manufacturing processes. 
     Then, as shown in  FIG. 6G , the side wall film  33  is left and the hard mask material  31  is removed. A wet etching can be used to remove the hard mask material  31 . 
     There may be a case where removal of the hard mask material  31  is not necessary for peripheral regions other than the region to form the memory cell array  1 , for example, regions to form the row and the column decoders  2 ,  3 , the high voltage generating unit  4 , and the control unit  5 . In this case, a photoresist mask can be formed in the peripheral regions by a photolithography before removal of the hard mask material  31  according to necessity. 
     Then, as shown in  FIG. 6H , the mask material  30 , the floating gate layer  22 , the tunnel insulating film  27  and the semiconductor substrate  25  are etched in the order using the side wall film  33  as a mask so that trenches  34 ,  34   a  are formed. For the etching, an anisotropic etching, for example, RIE can be used. 
     The depths of the trenches  34 ,  34   a  depend on the widths of the trenches. The trenches  34  corresponding to narrower intervals provided between portions of the side wall film  33  are formed shallowly by the etching. On the other hand, the trenches  34   a  corresponding to wider intervals provided between portions of the side wall film  33  are formed deeply by the etching. These are caused by loading effect during etching. 
     As shown in  FIG. 6I , element isolation layers  26   1 ,  26   2  are filled in the trenches  34  and  34   a , respectively. In order to fill the element isolation layers  26   1 ,  26   2 , the side wall film  33  and the mask material  30  are removed in advance, using an etching process such as a wet etching. 
     After removal of the side wall film  33  and the mask material  30 , an insulating film such as a silicon oxide film is deposited or applied to fill the trenches  34 ,  34   a . For the deposition or application, CVD or SOG can be used. After filling the insulating film, flattening is performed using CMP, for example, and element isolation layers  26   1  and  26   2  are formed. 
     As shown in  FIG. 6J , the element isolation layers  26   1 ,  26   2  are etched until the heights of the layers become lower than the floating gate layer  22 . The heights of the element isolation layer  26   1 ,  26   2  correspond to the widths of the element isolation layers  26   1 ,  26   2  so that the heights of the element isolation layers  26   2  becomes lower than those of the element isolation layers  26   1  having narrower widths. These are caused by the loading effect described above during etching. 
     In the case, etching of exposed portions of the floating gate layer  22  which project from the element isolation layer  26   1 ,  26   2  progresses. As a result, the exposed portions of the floating gate layer  22  becomes thin, and the corner portions becomes round. 
     Then, as shown in  FIG. 4 , an inter-gate insulating film  28  and an electrically conductive film to form word lines including the word lines  16 , (control gates) are formed, after etching the element isolation layers  26   1 ,  26   2 . For the inter-gate insulating film  28 , a silicon oxide film or a silicon nitride film respectively formed using CVD for example, an insulating film having a higher dielectric constant such as an aluminum oxide, or a laminated film of a silicon oxide film and a silicon nitride film can be used. For the electrically conductive film, a polysilicon film formed using CVD for example can be used. 
     As shown in  FIG. 6K  which shows a portion of the A-A section of  FIG. 2 , the electrically conductive film, the gate insulating film  28 , and the floating gate layer  22  are patterned perpendicularly to the active areas  56  so that the word lines  16   0 , . . . ,  16   n , . . . ,  16   65  are formed. After forming the word lines, N type impurities are introduced into the semiconductor substrate  25  i.e. the P type semiconductor region by ion implantation so that sources and drains are formed. The sources and drains may be formed in a previous step. An interlayer insulating film  35  is formed so as to cover the entire surface including word lines  16   0 , . . . ,  16   n , . . . ,  16   65 . For the interlayer insulating film  35 , a silicon oxide film formed using CVD may be used. 
     Then, as shown in  FIG. 6L  showing the portion of the D-D section of  FIG. 2 , the interlayer insulating film  35  is etched to form contact holes  36  of a reverse circular truncated cone shape or a reverse elliptical truncated cone shape. In the contact holes  36 , contact conductive films of a circular truncated cone shape or an elliptical truncated cone shape are filled. The contact conductive films are composed of a combination of polysilicon or tungsten (W) and a barrier metal such as titanium nitride (TiN), for example. With filling electrically conductive films, contacts  37  are formed to connect the active areas  56  to wiring layers formed in an upper layer of the interlayer insulating film  35  electrically. The contacts  37  constitute portions of the contact plugs  24   a ,  24   b  shown in  FIG. 3 . 
     A third interval W 3  is provided in the column direction between bottom portions of the contacts  37 . The third interval W 3  is larger than the first interval W 1  and narrower than the second interval W 2 . In this case, the width of parts of the bottom portions of the contacts  37  on the side of the active areas  56  is desirably wider in the column direction, in order to suppress electric resistance between the active areas  56  and the contacts  37 . Thus, the positions of the contacts  37  in the column direction are extended from the tops of the active areas  56  to the tops of portions of the element isolation layers  26   2 , respectively, in consideration of misalignment arising between the contacts  37  and the active areas  56  in manufacturing. 
       FIG. 7  shows a capacitance network to explain effects of the NAND flash memory according to the first embodiment. V cg  is a gate voltage to be applied to the control gates. V ch  is a voltage of the semiconductor substrate  25 . C IPD  is a capacitance between each of the floating gates  22  and each of the control gates sandwiching the inter-gate insulating film  28 . C OX  is a capacitance between each of the floating gates  22  and each of the channel portions of the semiconductor substrate  25  sandwiching the tunnel insulating film  27 . C SP1  is a capacitance between the floating gates  22  adjacent to each other which sandwich each of the element isolation layers  26   1 . C SP2  is a capacitance between the floating gate  22  adjacent to each other which sandwich each of the element isolation layer  26   2 . 
     The coupling ratio is determined by the ratio of C IPD  to C OX , when C SP1  and C SP2  are small enough to be disregard. Accordingly, it is effective to increase C IPD  in order to make the coupling ratio large. 
     In the NAND flash memory according to the first embodiment, some of the intervals of the memory cells are set to the second interval W 2  to ensure a large depth for filling the control gates. As a result, C IPD  can be made large even if the memory cell array  1  is miniaturized. 
     In the NAND flash memory according to the first embodiment, the others of the intervals of the memory cells, i.e. the intervals of the memory cell  13   X  in  FIG. 7 , are set to the second interval W 2 . Thus, the distance between the adjacent floating gates is made small so that C SP1  can be made larger than C SP2 . As a result, the coupling ratio can be made larger, from the effect of the series connection capacitance of the adjacent capacitors of C IPD  and C SP1  which is indicated by an arrow. 
     The tip shapes of the floating gates  22  are thin on the sides of the control gates so that the opposite areas between the floating gates  22  and the control gate portions of the word lines  16   0 - 16   65  increases and the coupling ratio can be larger. In addition, reduction of the coupling ratio due to depleting of the control gates can be suppressed. Each tip shape of the floating gates  22  can be made thin by etching an oxide film existing on each surface of the floating gates  22  under a wet atmosphere. 
     As shown in  FIG. 8 , even when the contacts  37  are provided in misalignment, the width of an contact area between each of the contacts  37  and each of the active areas adjacent to each other does not become smaller than the interval between the adjacent active areas or the interval between the adjacent contacts  37  (respectively shown by thick arrows), in the case that the amount of the misalignment is smaller than the size of the contacts  37  which are provided to extend to the side of the element isolation layers  26   2 . Accordingly, lowering of the break down voltage of adjacent each of the contacts  37  and each of the active areas is suppressed. 
     According to the embodiment, since the heights of the element isolation layers  26   1  are higher than those of the element isolation layers  26   2  as shown in  FIG. 4 , failure of filling the word lines  16   n  can be suppressed. Further, since the width of the element isolation layers  26   2  is larger than the average pitch of the memory cells  13   n , failure of filling the word lines  16   n  and depleting of the same can be suppressed. 
     In the embodiment, silicidation of the surface portion of the semiconductor substrate  25  to be connected electrically to contacts  37  may be performed using Mo, W, Ti, Co, Ni etc. beforehand, when the contacts  37  are formed. Further, part of the surface portion of the semiconductor substrate  25  to be connected electrically to contacts  37  may be a cut shape in the case that a damascene process is employed to form the contacts  37 . 
     Before the etching described above using  FIG. 6H , the side wall films  33  may be covered with a mask, when the film thickness or the resistance to etching of the side wall films  33  are short. For the mask, a silicon oxide film or a silicon nitride film can be used. 
     In filling the insulating films of  FIG. 6I , voids may be produced in the insulating films  26   1 ,  26   2 . Especially, in the element isolation layers  26   1 , voids can be formed easily because the layers have a narrow width. 
     According to the embodiment, in  FIG. 2 , the drains  23 ,  23   a2 , 23 b1 , and the sources  23 ,  23   a1 ,  23   b2  are formed by implanting ions into semiconductor substrate  25 , but the with ion-implantation may be omitted when the memory cells  13   0 - 13   65  are electrically connected with each other in series. 
       FIGS. 9A to 9G  show steps of an example of a method of manufacturing a NAND flash memory according to a second embodiment.  FIGS. 9A to 9G  correspond to a portion of the B-B section of  FIG. 2 , respectively. The NAND flash memory of the second embodiment is not different from the first embodiment substantially in completed shape, but is different from the latter in that, in manufacturing, the number of times of exposure and development is increased by one and the side wall transfer process is not necessary to be used. 
     According to the example of the method of manufacturing the NAND flash memory according to the second embodiment, a tunnel insulating film  27  and a floating gate layer  22  are formed in the order on a P type semiconductor layer  25  formed in an N type semiconductor substrate, as the example of the method of manufacturing the NAND flash memory according to the first embodiment shown in  FIG. 6A . 
     Then, as shown in  FIG. 9A , mask materials  38 ,  39  are formed to provide element isolation layers  26   1  described below on the floating gate layer  22 . For the mask materials  38 ,  39 , a silicon oxide film or a silicon-nitride film which are formed using a CVD process can be employed. After forming the mask materials  38 ,  39 , a resist pattern  32  is formed to pattern the mask material  38 . 
     As shown in  FIG. 9B , the mask material  38  is etched by using the resist pattern  32  as a mask, the resist pattern  32  is removed. For the etching, an anisotropic etching such as RIE can be used. By the etching, an etching shape of a taper is desirably formed so that the opening width of the mask material  38  may corresponds to the width of the element isolation layers  26   1  described above. 
     As shown in  FIG. 9C , the mask material  39 , the floating gate layer  22 , the tunnel insulating film  27  and the semiconductor substrate  25  are etched in this order using the mask material  38  as a mask so that trenches  34  for forming element isolation layers are formed. 
     As shown in  FIG. 9D , element isolation layers  26   1  are filled in the trenches  34 . In order to fill the element isolation layers  26   1 , an etching process such as a wet etching are performed to remove the mask materials  38 ,  39 . After removal of the mask materials  38 ,  39 , an insulating film is formed or applied to fill the element isolation layers  26   1  in the trenches  34 . CVD or SOG can be used for the formation or application of the insulating film. After the element isolation layers  26   1  are filled, flattening is performed using CMP, for example. 
     Then, as shown in  FIG. 9E , mask materials  38   a ,  39   b  are formed in order to provide element isolation layers  26   2  described below on the floating gate layer  22  and the flattened element isolation layers  26   1 . After forming the mask materials  38   a ,  39   b , a resist pattern  32   a  is formed to pattern the mask material  38   a.    
     Further, as shown in  FIG. 9F , the mask material  38   a  is etched by using the resist pattern  32   a  as a mask, and the resist pattern  32   a  is removed. The etching process is performed using an anisotropic etching such as RIE. 
     In this case, the mask material  38   a  is desirably etched to have a taper shape so that the opening width of the patterned mask material  38   a  may correspond to the width of the element isolation layers  26   2 . The opening width of the mask material  38   a  is formed to correspond to the width of the element isolation layers  26   2  more easily when the angle of the taper is formed to be more closely perpendicular to the semiconductor substrate  25  than the mask material  38  shown in  FIG. 9B . 
     As shown in  FIG. 9G , the mask material  39   a , the floating gate layer  22 , the tunnel insulating film  27  and the semiconductor substrate  25  are etched in this order using the mask material  38   a  as a mask so that trenches  34  are formed to provide element isolation layers  26   2  described below. 
     Then, similarly to the step shown in  FIG. 6I , the element isolation layers  26   2  are filled in the trenches  34 . In order to fill the element isolation layers  26   2 , the mask materials  38   a ,  39   a  are removed using an etching process such as a wet etching. After removal of the mask materials  38   a ,  39   a , an insulating film is formed or applied to fill the element isolation layers  26   2 . CVD or SOG can be used for the formation or application of the insulating film. After the element isolation layers  26   2  are filled, flattening is performed using CMP, for example. 
     Since the subsequent steps are similar to the step of  FIG. 6J  and the subsequent steps of the example of the method of manufacturing the NAND flash memory according to the first embodiment, the former subsequent steps will be omitted to be explained. 
     The NAND flash memory according to the second embodiment can make the capacitance C IPD  large even when the memory cell array  1  is miniaturized as in first embodiment. Further, the coupling ratio can be larger. Lowering of the breakdown voltages between the contacts  37  and the active areas adjacent to each other can be suppressed, and the failure of filling the word lines  16 , and depleting of the same can be suppressed. 
       FIG. 10  shows a section of a NAND flash memory according to a third embodiment.  FIG. 10  corresponds to the B-B section of  FIG. 2 . 
     The NAND flash memory of the third embodiment differs from the first and second embodiments mainly in that memory cells  13   n1  composing a memory cell array are formed on a SOI (Silicon on Insulator) substrate and in that memory cells  13   n1  are laminated.  FIG. 10  shows a portion where two layers are laminated, for explanatory convenience. 
     In the first layer from the bottom, memory cells  13   n1  are formed on an insulating layer  42   1  which is provided on a silicon substrate  41 . In addition, a semiconductor layer  43  (a semiconductor region) is formed instead of the semiconductor substrate  25  employed in first and second embodiments. The element isolation layers  26   3 ,  26   4  are provided instead of the element isolation layers  26   1 ,  26   2 . 
     A silicon wafer may be used for the semiconductor substrate  41 . A silicon oxide film may be used for the insulating layer  42   1 . A silicon layer formed by epitaxial growth or a polysilicon layer formed by CVD may be used for the semiconductor layer  43 . The element isolation layers  26   3 ,  26   4  are same as those of the element isolation layers  26   1 ,  26   2  of the first and second embodiments, and  26   2  except for the point that the depth of the layers  26   3 ,  26   4  extends to a surface of the insulating layer  42   1 . A word line  16   n1  is formed on the insulating film  28 . 
     In the second layer from the bottom and an upper layer formed above the second layer, memory cells  13   n1  are formed on an insulating layer  42   2  which is formed to cover the word line  16   n1 . The other configurations of the second layer are same as those of the first layer. 
     In the NAND flash memory according to the third embodiment, similarly to the first and second embodiments, the capacitance C IPD  may be large, even the memory cell array is miniaturized. In addition, the coupling ratio may be larger. Lowering of break down voltage is suppressed between adjacent contact and an active area. Failure of filling the word lines  16   n1  and depleting of the word lines  16   n1  may be suppressed. 
     According to the embodiment, since the memory cells  13   n1  are formed on the SOI, leak current may be reduced and the memory cells  13   n1  may be easily formed in the laminated direction. 
       FIG. 11  shows a section of a NAND flash memory according to a fourth embodiment. The NAND flash memory has a memory cell array.  FIG. 11  corresponds to the B-B section of  FIG. 2 . 
     The NAND flash memory of the fourth embodiment differs from the first to third embodiments mainly in that flat inter-gate insulating film  44  is used instead of the inter-gate insulating film  28  used in the former. 
     For the inter-gate insulating film  44 , an insulating film having a higher dielectric constant, such as an aluminum oxide, may be used. 
     In the NAND flash memory according to the first to third embodiments, the element isolation layers  26   1 ,  26   2  are etched until the heights of the layers  26   1 ,  26   2  become lower than the floating gate  22 , as shown in  FIGS. 4 ,  6 J and  10 . In the fourth embodiment, the heights of the element isolation layers  26   1 ,  26   2  are almost same as the floating gate  22 . 
     According to the embodiment, the insulating film having the higher dielectric constant is used for the inter-gate insulating film  44  so that a desirable coupling ratio may be obtained. Thus, the area where a portion of the control gate portion of the word line  16   n  and the floating gate  22  faces each other may be small. 
     In the NAND flash memory according to the fourth embodiment, similarly to the first to third embodiments, the capacitance C IPD  may be large even if the memory cell array is miniaturized. In addition, the coupling ratio may be larger. Lowering of break down voltage is suppressed between adjacent contact and an active area. Failure of filling the word lines  16   n1  and depleting of the word lines  16   n1  may be suppressed. 
     The embodiments described above are NAND flash memories, but the embodiments are not limited to the NAND type. 
     In the manufacturing method of the NAND flash memory of the third embodiment mentioned above, the method of forming the SOI may be a SIMOX method or a wafer bonding method. 
     While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.