Patent Publication Number: US-2022231036-A1

Title: Memory device and method for fabricating the same

Description:
REFERENCE TO RELATED APPLICATION 
     This application claims the benefit of U.S. Provisional Application No. 63/107,579, filed on Oct. 30, 2020, and U.S. patent application Ser. No. 17/166,078, filed Feb. 3, 2021, the contents of which are incorporated herein by reference in their entirety. 
    
    
     BACKGROUND 
     Many modern-day electronic devices contain electronic memory. Electronic memory may be volatile or non-volatile. Non-volatile memory is able to retain data in the absence of power, whereas volatile memory loses data when power is lost. Dynamic random-access memory (DRAM) is volatile and requires frequent refresh. Examples of non-volatile memory includes resistive random-access memory (RRAM), magnetoresistive random-access memory (MRAM), ferroelectric random-access memory (FeRAM), phase-change memory (PCM), and so on. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. 
         FIG. 1A  illustrates a cross-sectional side view of an integrated circuit device according to some aspects of the present disclosure. 
         FIG. 1B  illustrates a cross-sectional side view of an integrated circuit device according to some other aspects of the present disclosure. 
         FIG. 2  illustrates a cross-sectional side view of an integrated circuit device according to some other aspects of the present disclosure. 
         FIGS. 3A-6  are a series of cross-sectional view illustrations exemplifying a method according to the present disclosure of forming a device such as the device of  FIG. 1A . 
         FIG. 7  provides a flow chart illustrating a method according to the present disclosure of forming an integrated circuit device including a ferroelectric layer according to the present disclosure. 
         FIGS. 8-13  are a series of cross-sectional view illustrations exemplifying a method according to the present disclosure of forming a device such as the device of  FIG. 1B . 
         FIG. 14  provides a flow chart illustrating a method according to the present disclosure of forming an integrated circuit device including a ferroelectric layer according to the present disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     The present disclosure provides many different embodiments, or examples, for implementing different features of this disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. 
     Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature&#39;s relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. 
     A variety of integrated circuit (IC) devices include layers of ferroelectric material. For example, ferroelectric memory uses a ferroelectric layer for data storage. The data may be stored by retaining a polarization of electric dipoles in the ferroelectric layer. A first orientation of those dipoles may represent a logical “1” and a second orientation may represent a logical “0”. There are a variety of ferroelectric memory structures. In some embodiments, a ferroelectric memory includes a ferroelectric layer disposed between two plates in a capacitor that stores data. A 1T-1C memory architecture, for example, may use ferroelectric capacitors. In some embodiments, a ferroelectric memory has the structure of a metal-ferroelectric-metal-insulator-semiconductor field-effect transistor (MFMIS-FET) in which the bottom electrode of a ferroelectric capacitor is coupled to the gate electrode of a field-effect transistor (FET). The gate electrode and the bottom electrode of the ferroelectric capacitor function as a single floating gate. In some embodiments, a ferroelectric memory has a ferroelectric layer disposed between a gate electrode and a channel in a transistor structure. A ferroelectric field effect transistor (FeFET) is an example. 
     It is desirable for ferroelectric memory to have long lifetime and high reliability. Lifetime is limited by time-dependent dielectric breakdown (TDDB) and bias temperature instability (BTI). TDDB manifests as a leakage current that increases over extended periods of operation. BTI seems related to charge trapping and manifests as a variation in a threshold voltage over periods of continuous operation. BTI includes positive bias temperature instability (PBTI) and negative bias temperature instability (NBTI). The causes and mechanisms of TDDB and BTI are not well understood making them difficult to manage. 
     The inventors of the present disclosure have determined that TDDB and BTI can be ameliorated by eliminating chlorine residues from ferroelectric layers and nearby structures, especially structures that border the ferroelectric layers. They have determined that as little as 1 ppm chlorine in the ferroelectric layer or one of the surrounding structures can result in TDDB/BTI and that TDDB/BTI can be substantially mitigated by producing and maintaining the ferroelectric layer and surrounding structures with less than 1 ppm chlorine. TDDB/BTI due to 1 ppm chlorine has been observed with ferroelectric materials of the composition Hf x Zr 1-x O 2  as a specific example. In the formula, x has a range from 0 to 1. The formula includes HfO 2 , HfZrO 2 , and ZrO 2 . 
     Ferroelectric layers are generally produced by atomic layer deposition (ALD) using metal chloride precursors. The performance of a ferroelectric layer is strongly influenced by layer thickness. ALD allows precise control of layer thicknesses. Metal chloride precursors have volatilities and reaction rates well suited to the ALD process. Ferroelectric memory may include other layers that comprise metals and are ordinarily produced by ALD using metal chloride precursors. These other layers include work function metal layers, electrodes, and insulating layers. While not wishing to be bound by theory, it has been observed that as little as 1 ppm of chlorine in any of these layers or in the metal electrodes of a ferroelectric memory device can result in the development of fixed charge clusters, particularly at interfaces, and that these fixed charge clusters can result in TDDB or BTI. 
     In accordance with the present disclosure, the ferroelectric layer of a ferroelectric memory cell has less than 1 ppm chlorine. In some embodiments, the ferroelectric memory cell comprises other layers that include metal compounds but have less than 1 ppm chlorine. In some embodiments, these other layers include a work function metal layer. In some embodiments, the work function metal layer comprises an alloy of two metals. In some embodiments, these other layers include a two work function metal layers. In some embodiments, the two work function metal layers are between the ferroelectric layer and an electrode. In some embodiments, the two work function metal layers are on opposite sides of the ferroelectric layer. In some embodiments, the other layers include an insulating layer. In some embodiments, the electrodes of the ferroelectric memory cell have less than 1 ppm chlorine. In some embodiments, all the structures of the ferroelectric memory cell have less than 1 ppm chlorine. 
     In some embodiments, the ferroelectric layer is produced from gaseous precursors that include chlorine-free metal compounds. In some embodiments, a work function metal layer is produced from gaseous precursors that include chlorine-free metal compounds. In some embodiments, the work function metal layer is produced from gaseous precursors that include a chlorine-free precursor of a first metal and a chlorine free precursor of a second metal. In some embodiments, an insulating layer is produced from gaseous precursors that include chlorine-free metal compounds. Using precursors that are chlorine-free eliminates chlorine residues. 
     In some embodiments, the chlorine-free precursors include metal compounds in which the metal is directly bonded to oxygen, nitrogen, carbon, or a combination thereof. In some embodiments, the chlorine-free precursors include a metal compound in which the metal is directly bonded to carbon. In some embodiments, the chlorine-free precursors include a metal compound in which the metal is directly bonded to oxygen. In some embodiments, the chlorine-free precursors include a metal compound in which the metal is directly bonded exclusively to oxygen and/or carbon. In some embodiments, the chlorine-free precursors include a metal compound with a hydrocarbon functional group. In some embodiments, the chlorine-free precursors include a metal compound with a carbonyl functional group. In some embodiments, the chlorine-free precursors include a metal in a cyclopentadienyl complex. In some embodiments, the chlorine-free metal precursors include a metal compound with a nitrogen functional group. In some embodiments, the chlorine-free metal precursors include a metal compound with hydrofluorocarbon functional group. 
     In some embodiments, the chlorine-free precursors include a metal compound in which the metal is directly bonded to nitrogen. In some embodiments, the chlorine-free precursors include a metal compound in which the metal is bonded exclusively to nitrogen. Excellent results have been obtained with precursors of the form M(NR 1 R 2 ) 4 , where M is zirconium (Zr), halfnium (Hf), or the like and R 1  and R 2  are organic functional groups. 
     In some embodiments, the organic functional groups are alkanes, alkenes, alkynes, alcohols, amines, ethers, aldehydes, ketones, carboxylic acids, esters, amides, or the like. In some embodiments, the precursors include one or more of:
     zirconium(IV) tert-butoxide (Zr[OC(CH 3 ) 3 ] 4  or ZTB);   bis(methyl-η5-clyclopentadienyl)methoxymethylzirconium (Zr[CH 3 C 5 H 4 ] 2 CH 3 OCH 3 , ZRCMMM, or ZrD-CO4);   tetrakis(dimethylamino)zirconium(IV) (Zr[N(CH 3 ) 2 ] 4  or TDMAZ);   tetrakis(ethylmethylamido)zirconium(IV) (Zr[N(CH 3 )(C 2 H 5 )] 4  or TEMAZ);   bis(methyl-η5-clyclopentadienyl)dimethylhafnium (Hf[CH 3 C 5 H 4 ] 2 CH 3 OCH 3 , HFCMME, or HfD-CO 2 );   bis(methyl-η5-clyclopentadienyl)methoxymethylhafnium (HfCH 3 OCH 3 [C 5 H 4 ] 2  or HfD-CO4);   tetrakis(dimethylamino)hafnium(IV) (Hf[N(CH 3 ) 2 ] 4  or TDMAH);   tetrakis(ethylmethylamido)hafnium(IV) (Hf[N(CH 3 )(C 2 H 5 )] 4  or TEMAH);   or the like.   

     The ferroelectric layer may be incorporated into any type of integrated circuit device. In some embodiments, the ferroelectric layer is included in a memory cell of a memory device. The memory can be of any type. In some embodiments the ferroelectric memory includes the ferroelectric layer in a transistor structure. In some embodiments, the transistor has a bottom gate. In some embodiments, the transistor has a top gate. In some embodiments, the transistor is in a three-dimensional (3D) memory array. In some embodiments, the transistor has a metal-ferroelectric-semiconductor (MFS) structure. In some embodiments, the transistor has a metal-ferroelectric-insulator-semiconductor (MFIS) structure. In some embodiments the ferroelectric memory includes the ferroelectric layer in a capacitor structure. In some embodiments, the memory is ferroelectric random access memory (FeRAM) in which the ferroelectric capacitor is coupled to a drain region of a field effect transistor (FET). In some embodiments, the memory has a metal-ferroelectric-metal-insulator-semiconductor (MFMIS) structure in which the ferroelectric capacitor is coupled to the gate of an FET. 
     A ferroelectric memory cell according to the present disclosure has a lower time-dependent dielectric breakdown rate (TDDB rate) and a lower BTI rate in comparison to an equivalent ferroelectric memory cell with just 1 ppm more of chlorine in the ferroelectric layer. TDDB rates may not be well characterized over short periods of operation but may be consistently determined when consider over a longer period of operation such as a period over which the leakage current doubles or a period over which the Weibull slope is decreasing. Accordingly, for use in comparisons, the TDDB rate may be defined as the initial leakage current divided by a time of operation over which the initial leakage current doubles. Alternatively, the TDDB rate may be determined over a period in which the Weibull slope is decreasing. 
     The ferroelectric layer of a ferroelectric memory cell according to the present disclosure may be formed with chlorine-free precursors. The ferroelectric layer of a comparison ferroelectric memory cell may be formed by adding some chloride precursors to the process gas mix. The comparison ferroelectric memory cell will have a larger TDDB rate than that of the ferroelectric memory cell according to the present disclosure. In some embodiments, the comparison memory cell that has 1 ppm more of chlorine in the ferroelectric layer has a TDDB more than twice that of a memory cell according to the present disclosure. In some embodiments, BTI rate, defined as the rate at which the threshold voltage changes during continuous operation, is half or less that of the comparison memory cell. 
       FIG. 1A  illustrates an integrated circuit device  100 A having a memory cell  101 A according to some aspects of the present disclosure. The memory cell  101 A includes a ferroelectric layer  107 A in a transistor structure. The transistor structure includes a gate electrode  105 A, an alloy work function metal layer  121 A, a second work function metal layer  123 A, the ferroelectric layer  107 A, an insulating layer  109 A, a channel layer  111 A, a source coupling  117 A, and a drain coupling  113 A. The ferroelectric layer  107 A is between the channel layer  111 A and the gate electrode  105 A. The insulating layer  109 A is an optional layer between the ferroelectric layer  107 A and the channel layer  111 A. The insulating layer  109 A makes direct contact with the ferroelectric layer  107 A at an interface  128 A. 
     The gate electrode  105 A, the alloy work function metal layer  121 A, and the second work function metal layer  123 A may be within a substrate  103 A underneath the ferroelectric layer  107 A. In this configuration, the gate electrode  105 A is a bottom gate. The source coupling  117 A and the drain coupling  113 A may be vias in an interlevel dielectric  115 A. Each of these structures has less than 1 ppm chlorine. 
     The alloy work function metal layer  121 A is between the second work function metal layer  123 A and the ferroelectric layer  107 A. The second work function metal layer  123 A is between the gate electrode  105 A and the alloy work function metal layer  121 A. The alloy work function metal layer  121 A makes direct contact with the ferroelectric layer  107 A at an interface  126 A. The second work function metal layer  123 A makes direct contact with the ferroelectric layer  107 A at an interface  124 A. The gate electrode  105 A makes direct contact with the ferroelectric layer  107 A at an interface  122 A. 
     In some embodiments, the ferroelectric layer  107 A is an HfZrO layer. In some embodiments, the ferroelectric layer  107 A is of the formula HF x Zr 1-x O 2  where x in the range from 0 to 1. In some embodiments, the ferroelectric layer is HF x Zr 1-x O 2  where x in the range from 0.1 to 0.9. In some embodiments, the ferroelectric layer is HF 0.5 Zr 0.5 O 2 . In some embodiments, the ferroelectric layer has HFZrO in more than 50% combined t-phase (tetragonal), o-phase (orthorhombic), and c-phase (cubic) and less than 50% m-phase (monoclinic). In some embodiments, the HFZrO is doped with smaller radius ions that increase 2Pr. Smaller radius ions include ions of aluminum (Al), silicon (Si), and the like. In some embodiments, the HFZrO is doped with larger radius ions that increase 2Pr. Larger radius ions include ions of lanthanum (La), scandium (Sc), calcium (Ca), barium (Ba), gadolinium (Gd), yttrium (Y), and the like. 2Pr is a measure of the switching polarization of a ferroelectric material. In some embodiments, the ferroelectric layer has oxygen vacancies. 
     In some embodiments, the ferroelectric layer  107 A is aluminum nitride (AlN) doped with scandium (Sc) or the like. The ferroelectric layer  107 A may alternatively be another ferroelectric material. Examples of other ferroelectric materials that may be used include, without limitation, hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), hafnium zirconium oxide (HfZrO), hafnium cerium oxide (HfCeO), hafnium oxide (HfO), hafnium silicon oxide (HfSiO), hafnium gadolinium oxide (HFGdO), and the like. 
     The ferroelectric layer  107 A may be from 0.1 nm to 100 nm thick. In some embodiments, the ferroelectric layer  107 A is from 1 nm to 30 nm thick. If the ferroelectric layer  107 A is too thin, it may not provide adequate threshold voltage switching in the memory cell  101 A. If the ferroelectric layer  107 A is too thick, it may not have a desired concentration of oxygen vacancies. The ferroelectric layer  107 A has a uniformity of thickness that is characteristic of formation by an atomic layer deposition process (ALD) and comprises less than 1 ppm chlorine. In some embodiments the ferroelectric layer  107 A is chlorine-free. 
     The insulating layer  109 A is a dielectric. In some embodiments, the insulating layer  109 A has a thickness in the range from 0.1 nm to 10 nm. In some embodiments, the insulating layer  109 A has a thickness in the range from 0.3 nm to 3 nm. If the insulating layer  109 A is too thin, it may not be functional. If the insulating layer  109 A is too thick, it may interfere with operation of the memory cell  101 A. The insulating layer  109 A has a uniformity of thickness that is characteristic of formation by an atomic layer deposition process (ALD) and comprises less than 1 ppm chlorine. 
     The insulating layer  109 A may comprise silicon (Si), magnesium (Mg), aluminum (Al), yttrium (Y), lanthanum (La), strontium (Sr), gadolinium (Gd), scandium (Sc), calcium (Ca), a compound thereof, a combination thereof, or the like. In some of these embodiments the insulating layer  109 A comprises a compound of two or more metals. In some embodiments, the insulating layer  109 A includes hafnium oxide (HfO 2 ). In some embodiments, the insulating layer  109 A comprises a compound that include silicon and a metal. In some embodiments, the insulating layer  109 A includes hafnium oxide (HfO 2 ) and silicon (Si). The atomic ratio of silicon to hafnium may be 10% or more. In any of these embodiments the insulating layer  109 A may be chlorine-free. 
     The channel layer  111 A is a semiconductor. In some embodiments, the channel layer  111 A is or includes an oxide semiconductor. Oxide semiconductors that may be suitable for the channel layer  111 A include, without limitation, zinc oxide (ZnO), magnesium oxide (MgO), gadolinium oxide (GdO), indium tungsten oxide (InWO), indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium gallium zinc tin oxide (InGaZnSnO or IGZTO), indium tin oxide (InSnO or ITO), combinations thereof, or the like. In some embodiments, the channel layer  111 A is or includes polysilicon, amorphous silicon, silicon geranium (SiGe), or the like. In some embodiments, the channel layer  111 A has a thickness in the range from 0.1 nm to 100 nm. In some embodiments, the channel layer  111 A has a thickness in the range from 2 nm to 30 nm. In some embodiments, the channel layer  111 A has a thickness in the range from 5 nm to 20 nm. In some of these embodiments the channel layer  111 A includes a metal compound and comprises less than 1 ppm chlorine. In some of these embodiments the channel layer  111 A is a compound that includes two distinct metals and is chlorine-free. 
     The source coupling  117 A, the drain coupling  113 A, and the gate electrode  105 A, may be formed of any suitable conductive materials. Suitable conductive materials may include doped polysilicon, graphene, metals, and the like. In some embodiments, the source coupling  117 A, the drain coupling  113 A, and the gate electrode  105 A are formed with metals. Some examples of metals that may be used are tungsten (W), copper (Cu), ruthenium (Ru), molybdenum (Mo), cobalt (Co), aluminum (Al), nickel (Ni), silver (Ag), gold (Au), titanium (Ti), tellurium (Te), platinum (Pt), tantalum (Ta), a combination thereof, an alloy thereof, or the like. 
     The source coupling  117 A and the drain coupling  113 A may comprise less than 1 ppm chlorine. In some embodiments the source coupling  117 A and the drain coupling  113 A are an alloy of two or more metals. In some of these embodiments each the source coupling  117 A and the drain coupling  113 A are chlorine-free. The gate electrode  105 A comprises less than 1 ppm chlorine. In some embodiments the gate electrode  105 A is an alloy of two or more metals. In some of these embodiments the gate electrode  105 A is chlorine-free. 
     The second work function metal layer  123 A may be a metal compound. Some examples of materials that may be used for the second work function metal layer  123 A are titanium nitride (TiN), tantalum nitride (TaN), molybdenum nitride (MoN), tungsten nitride (WN), tungsten carbonitride (WCN), zirconium nitride (ZrN), hafnium nitride (HfN), ruthenium oxide (RuOx), and the like. The second work function metal layer  123 A comprises less than 1 ppm chlorine. In some embodiments the second work function metal layer  123 A comprises an alloy of two or more metals. In some of these embodiments the second work function metal layer  123 A is chlorine-free. 
     The alloy work function metal layer  121 A comprises an alloy of two or more metals. In some embodiments, the alloy work function metal layer  121 A comprises an alloy of three or more metals. In some embodiments, the alloy work function metal layer  121 A comprises an alloy of four or more metals. The alloy work function metal layer  121 A comprises less than 1 ppm chlorine. In some embodiments the alloy work function metal layer  121 A is chlorine-free. The metals may be from the group that includes titanium (Ti), tantalum (Ta), molybdenum (Mo), tungsten (W), tungsten (W), zirconium (Zr), hafnium (Hf), ruthenium (Ru), nickel (Ni), manganese (Mn), palladium (Pd), iron (Fe), cobalt (Co), beryllium (Be), copper (Cu), barium (Ba), thorium (Th), calcium (Ca), strontium (Sr), silver (Ag), yttrium (Y), cerium (Ce), lanthanum (La), lithium (Li), cesium (Cs), and the like. The metals may be compounded with nitrogen, carbon, oxygen, or the like. Specific examples include zirconium-cerium (Zr—Ce), tungsten-beryllium (W—Be), copper-barium (Cu—Ba), tungsten-lanthanum (W—La), tungsten-yttrium (W—Y), tungsten-zirconium (W—Zr), tungsten-calcium (W—Ca), tungsten-strontium (W—St), tungsten-lithium (W—Li), nickel-barium (Ni—Ba), nickel-cesium (Ni—Cs), molybdenum-thorium (Mo—Th), molybdenum-cesium (Mo—Cs), tantalum-cesium (Ta—Cs), tantalum-thorium (Ta—Th), titanium-cesium (Ti—Cs), silver-barium (Ag—Ba), combinations of other work function metals, and the like. 
     The interlevel dielectric  115 A may be undoped silicate glass (USG) or the like. In some embodiments, the interlevel dielectric  115 A is a low-κ dielectric. In some embodiments, the interlevel dielectric  115 A is an extremely low-κ dielectric. A low-κ dielectric is a material having a dielectric constant lower than that of silicon dioxide. Examples of low-κ dielectrics include organosilicate glasses (OSG) such as carbon-doped silicon dioxide, fluorine-doped silicon dioxide (otherwise referred to as fluorinated silica glass or FSG), and organic polymer low-k dielectrics. Examples of organic polymer low-k dielectrics include polyarylene ether, polyimide (PI), benzocyclobutene, and amorphous polytetrafluoroethylene (PTFE). An extremely low-κ dielectric is a material having a dielectric constant of about 2.1 or less. An extremely low-κ dielectric can be formed by deposition of a low-κ dielectric in such a manner that it has porosity or air-gaps, whereby the effective dielectric constant of the composite including pores and air gaps is 2.1 or less. The interlevel dielectric  115 A has less than 1 ppm chlorine. In some embodiments the interlevel dielectric  115 A is chlorine-free. 
     The substrate  103 A may be a die cut from a wafer, such as a silicon wafer or the like. The substrate  103 A may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like. Other substrates, such as a multilayered or gradient substrate may also be used. In some embodiments, the semiconductor material of the substrate  103 A is or includes silicon, germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide, silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, gallium indium arsenide phosphide, combinations thereof, or the like. The substrate  103 A may be or include a dielectric material. For example, the substrate  103 A may be a dielectric substrate or may include a dielectric layer on a semiconductor substrate. The dielectric material may be an oxide such as silicon oxide, a nitride such as silicon nitride, a carbide such as silicon carbide, combinations thereof such as silicon oxynitride, silicon oxycarbide, silicon carbonitride, the like, or any other suitable dielectric. 
     In the memory cell  101 A, there is threshold voltage on the gate electrode  105 A at which the channel layer  111 A begins to conduct between the source coupling  117 A and the drain coupling  113 A. That threshold voltage may be varied through write and erase operations that alter a polarization of electrical dipoles within the ferroelectric layer  107 A. A first orientation of those electrical dipoles provides a first threshold voltage that may represent a logical “1” and a second orientation of those electrical dipoles provides a second threshold voltage that may represent a logical “0”. 
     A write operation for the memory cell  101 A may include setting the gate electrode  105 A to a programming voltage V th  while grounding the source coupling  117 A and the drain coupling  113 A. V th  may be the highest possible threshold voltage for the memory cell  101 A. For an erase operation, the gate electrode  105 A may be set to −V th  while grounding the source coupling  117 A and the drain coupling  113 A. A read operation may include setting the gate electrode  105 A to a voltage intermediate between the first threshold voltage and the second threshold voltage, for example ½ V th , setting the source coupling  117 A to V dd , setting the drain coupling  113 A to ground, and determining whether a resulting current is above or below a threshold. Operation of the memory cell  101 A includes a combination of the read, write, and erase operations. A specific operating protocol may be set for determining the TDDB rate or the BTI rate. In some embodiments, the operating protocol includes applying constant voltage stress (CVS). To determine the BTI rate small gate voltage pulses may be applied to measure V th  while voltage stress is continuously maintained. 
       FIG. 1B  illustrates an integrated circuit device  100 B having a memory cell  101 B according to some other aspects of the present disclosure. The memory cell  101 B has a transistor structure including a source region  118 B, a drain region  104 B, a channel  111 B, a ferroelectric layer  107 B, an insulating layer  109 B, an alloy work function metal layer  121 B, a second work function metal layer  123 B, and a gate electrode  105 B. The source region  118 B, the drain region  104 B, and the channel  111 B are provided by semiconductor portions of a substrate  103 B. The source region  118 B and the drain region  104 B have one doping type and the channel  111 B has an opposite doping type. A source coupling  117 B connects with the source region  118 B. A drain coupling  113 B connects with the drain region  104 B. The source coupling  117 B and the drain coupling  113 B are vias in an interlevel dielectric  115 B and may connect with a metal interconnect disposed over the substrate  103 B. The gate electrode  105 B is above the ferroelectric layer  107 B and the channel  111 B. In this configuration, the gate electrode  105 B is a top gate. 
     The description of the gate electrode  105 A applies to the gate electrode  105 B. The description of the alloy work function metal layer  121 A applies to the alloy work function metal layer  121 B. The description of the second work function metal layer  123 A applies to the second work function metal layer  123 B. The description of the ferroelectric layer  107 A applies to the ferroelectric layer  107 B. The description of the insulating layer  109 A applies to the insulating layer  109 B. The description of the substrate  103 A applies to the substrate  103 B with the proviso that the channel  111 B is a semiconductor. The description of the source coupling  117 A applies to the source coupling  117 B. The description of the drain coupling  113 A applies to the drain coupling  113 B. 
     While the memory cell  101 B has been presented as a memory cell, the same arrangement of materials may be used in a related field effect transistor with metal oxide semiconductor structure (MOSFET). The ferroelectric layer  107 B with the same composition may be used as a high-κ dielectric layer, although a different thickness may be more suitable for that application. As in the memory cell application, a low chlorine content facilitates achieving low TDDB. 
       FIG. 2  illustrates an integrated circuit device  200  having a 1T1C memory device that includes a transistor  227  and a ferroelectric capacitor  235  according to some aspects of the present disclosure. The ferroelectric capacitor  235  includes a ferroelectric layer  107 C between a top electrode  237  and a bottom electrode  211 . A first alloy work function metal layer  121 C is between the top electrode  237  and the ferroelectric layer  107 C and is in direct contact with the ferroelectric layer  107 C. A second alloy work function metal layer  121 D is between the bottom electrode  211  and the ferroelectric layer  107 C and is also in direct contact with the ferroelectric layer  107 C. 
     The ferroelectric capacitor  235  is disposed in a metal interconnect  223  that is over a semiconductor substrate  239 . The metal interconnect  223  includes wires  231  and vias  233 , which may be surrounded by an interlevel dielectric  115 C. The ferroelectric capacitor  235  may be disposed between the 3 rd  and 4 th  metallization layers, the 4 th  and 5 th  metallization layers, or any other adjacent pair of metallization layers in the metal interconnect  223 . The transistor  227  may include a gate electrode  225  and a gate dielectric  229  disposed over a doped region  228  of the semiconductor substrate  239 . Source/drain regions  221  may be provided by adjacent areas of the semiconductor substrate  239  having an opposite doping type. 
     The ferroelectric capacitor  235  may be operated as a memory cell by applying suitable voltages to a word line (WL), a bit line (BL), and a source line (SL). If the ferroelectric layer  107 C has a suitable thickness and mode of operation, it will store data according to the polarization of electrical dipoles. In that case, the ferroelectric capacitor  235  is ferroelectric memory cell. If the ferroelectric layer  107 C has a suitable thickness and mode of operation, it will store data according to a charge on the capacitor. In that case, the ferroelectric capacitor  235  is dynamic random-access memory (DRAM) cell. 
     The ferroelectric layer  107 C is a material having compositional alternatives as described for the ferroelectric layer  107 A. Likewise, the interlevel dielectric  115 C has the compositional alternatives of the interlevel dielectric  115 A. The description of the alloy work function metal layer  121 A applies to each of the first alloy work function metal layer  121 C and the second alloy work function metal layer  121 D. 
       FIGS. 3A through 6  illustrate cross-sectional views exemplifying a method according to the present disclosure of forming a memory cell. While  FIGS. 3A through 6  are described with reference to various embodiments of a method, it will be appreciated that the structures shown in  FIGS. 3A through 6  are not limited to the method but rather may stand alone separate from the method. While  FIGS. 3A through 6  are described as a series of acts, it will be appreciated that the order of the acts may be altered in other embodiments. While  FIGS. 3A through 6  illustrate and describe a specific set of acts, some acts that are illustrated and/or described may be omitted in other embodiments. Further, acts that are not illustrated and/or described may be included in other embodiments. While the method of  FIGS. 3A through 6  is described in terms of forming the integrated circuit device  100 A, the method may be used to form other integrated circuit devices. 
     As shown by the cross-sectional view  300  of  FIG. 3A , the method may begin with forming a mask  303  and using the match to etch a trench  301  in the substrate  103 A. The etch process may be a dry etch. The mask  303  may be formed using photolithography. After etching, the mask  303  may be stripped. 
     As shown by the cross-sectional view  320  of  FIG. 3B , the gate electrode  105 A, the second work function metal layer  123 A, and the alloy work function metal layer  121 A may be deposited in succession so as to fill the trench  301 . The alloy work function metal layer  121 A is formed by atomic layer deposition (ALD), chemical vapor deposition (CVD), or the like from gaseous precursors and the gaseous precursors are chlorine-free. The second work function metal layer  123 A may be deposited by ALD, CVD, physical vapor deposition (PVD), the like, or any other suitable process. In some embodiments, the second work function metal layer  123 A is formed by ALD, CVD, or the like from gaseous precursors and the gaseous precursors are chlorine-free. The gate electrode  105 A may be formed by ALD, CVD, PVD, electroplating, electroless plating, the like, or any other suitable process. In some embodiments, the gate electrode  105 A is formed by ALD, CVD, or the like from gaseous precursors and the gaseous precursors are chlorine-free. Processes that use gaseous precursors are better suited to forming alloys and other complex compositions. ALD allows more accurate control of composition than CVD. In addition, ALD allows precise control of layer thicknesses. 
     As shown by the cross-sectional view  340  of  FIG. 3C , a planarization process may be used to remove portions of the gate electrode  105 A, the second work function metal layer  123 A, and the alloy work function metal layer  121 A that deposited outside the trench  301 . The planarization process may be chemical mechanical polishing (CMP) or the like. 
     As shown by the cross-sectional view  400  of  FIG. 4 , the method may continue with forming the ferroelectric layer  107 A. The ferroelectric layer  107 A is formed by chemical vapor deposition (CVD), atomic layer deposition (ALD), or the like using chlorine-free gaseous precursors. In some embodiments, the ferroelectric layer  107 A is formed by ALD as described more fully below. ALD provides precise control of layer thickness and also helps regulate the addition of dopants such as aluminum (Al), silicon (Si), lanthanum (La), scandium (Sc), calcium (Ca), barium (Ba), gadolinium (Gd), yttrium (Y), and the like. When included, these dopants are provided by gaseous chlorine-free precursors. 
     As shown by the cross-sectional view  500  of  FIG. 5 , the method may continue with forming the insulating layer  109 A and the channel layer  111 A. The insulating layer  109 A and the channel layer  111 A may be formed by CVD, ALD, a combination thereof, or the like, or any other suitable process or processes. In some embodiments, these layers are formed from chlorine-free precursors. In some embodiments, the insulating layer  109 A is formed by ALD. ALD allows a thickness of the insulating layer to be accurately controlled. CVD and ALD process are conducive to forming the insulating layer with complexes of silicon and a metal or of two or more metals. ALD allows the most accurate control of compositions 
     As shown by the cross-sectional view  600  of  FIG. 6 , the method may continue with forming the interlevel dielectric  115 A over the channel layer  111 A. The interlevel dielectric  115 A may be formed by CVD, a liquid process such as a spin-on-glass process, or the like. In some embodiments, the interlevel dielectric  115 A is undoped silicate glass (USG) formed by CVD with silane (SiH4) or tetraethyl orthosilicate (TEOS). 
     As further shown in  FIG. 6 , a photoresist mask  601  may be formed and used to etch trenches  603  in the interlevel dielectric  115 A. Etching the trenches  603  may include a dry etch process such as plasma etching or any other suitable process. The trenches  603  may be filled with conductive material by atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), electroplating, electroless plating, the like, or any other suitable process followed by planarization to form a structure as shown in  FIG. 1A . Planarization may be CMP or any other suitable process. In some embodiments, the trenches  603  are filled by ALD, CVD, or the like from gaseous precursors and the gaseous precursors are chlorine-free. The use of gaseous precursors and ALD in particular facilitates precise control of the fill composition. 
       FIG. 7  presents a flow chart for a process  700  which may be used to form an integrated circuit device according to the present disclosure. The process  700  includes steps for forming the integrated circuit device  100 A of  FIG. 1A  and also includes a method of forming the ferroelectric layer  107 A that may be used to form other ferroelectric layers according to other embodiments of the present disclosure. While the process  700  of  FIG. 7  is illustrated and described herein as a series of acts or events, it will be appreciated that the illustrated ordering of such acts or events is not to be interpreted in a limiting sense. For example, some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein. Further, not all illustrated acts are required to implement one or more aspects or embodiments of the description herein, and one or more of the acts depicted herein may be carried out in one or more separate acts and/or phases. 
     The process  700  may begin with act  701 , etching a trench in a substrate. The cross-sectional view  300  of  FIG. 3A  provides an example. 
     The process  700  continues with act  702 , forming a bottom electrode, act  703 , depositing a second work function metal layer, and act  704 , depositing an alloy work function metal layer. The cross-sectional view  320  of  FIG. 3B  provides an example. These layers may deposit in the trench formed by act  701 . These layers may be formed from chlorine-free gaseous precursors. 
     Act  705  is chemical mechanical polishing (CMP). The cross-sectional view  340  of  FIG. 3C  provides an example. 
     Act  706  is forming the ferroelectric layer. The cross-sectional view  400  of  FIG. 4  provides an example. It should be appreciated that a ferroelectric layer according to the present disclosure may be formed in a different structure or at a different stage of processing. Act  706  may include an atomic layer deposition (ALD) process as further illustrated by acts  711  through  725 . 
     After forming the ferroelectric layer, the process  700  may continue with act  707  forming an insulating layer and act  708 , forming a channel layer. The cross-sectional view  500  of  FIG. 5  provides an illustrative example. Forming the insulating layer is optional. The insulating layer and the channel layer may be formed from chlorine-free gaseous precursors. 
     Act  709  is forming source and drain structures. The cross-sectional view  600  of  FIG. 6  together with  FIG. 1A  provides an example. The source and drain structures may be formed from chlorine-free gaseous precursors. 
     Act  706 , forming the ferroelectric layer, may be ALD. ALD involves cyclically repeating a series of steps whereby the ferroelectric layer is deposited uniformly and at a controlled rate. As illustrated, the ALD process may begin with act  711 , pulsing with water vapor or the like. 
     Pulsing means introducing the reagent into a process gas flow for a limited period of time. The process gas may include an inert carrier, such as nitrogen or argon that flows continuously through a chamber that contains the substrate. The chamber may be continuously exhausted through a vacuum system. In some embodiments, the ALD process is carried out at sub-atmospheric pressure. In some embodiments, the process is carried out at a pressure at or below 50 torr. In some embodiments, the process is carried out at pressures in the range from about 1 torr to about 10 torr. In some embodiments, the process is carried out at pressures in the range from about 2 torr to about 5 torr. Lower pressures facilitate maintaining precursors in gaseous form. 
     Through absorption or adsorption, a layer of the water vapor forms on a surface of the substrate. The water provides an oxygen source in chemical reactions that form the ferroelectric layer. Another suitable oxygen source may be substituted for water, such as O 2 , O 3  or plasma O 2  or plasma O 3 . The pulse is continued until the surface layer has formed. In some embodiments, the water pulse is 60 seconds or less. In some embodiments, the water pulse is in the range from one second to 10 seconds. 
     After the water has formed a layer on the surface, the process may continue with act  713 , purging the chamber. Purging the chamber may be purging with a non-reactive gas. Nitrogen may be a non-reactive gas. In some embodiments, the purge lasts 30 seconds or less. In some embodiments, the purge lasts from one second to 10 seconds. In some embodiments, the purge lasts 5 seconds or less. 
     The process may continue with act  715 , pulsing with a chlorine-free zirconium precursor. The chlorine-free zirconium precursor is a zirconium compound that reacts with the oxygen source on the surface to form a layer that includes zirconium. The precursor is selected to be volatile under the process conditions, to deposit only to an extent limited by the amount of the oxygen source such as water that is present on the surface, and to have an acceptable reaction rate. In some embodiments, the zirconium precursor pulse lasts 60 seconds or less. In some embodiments, the zirconium precursor pulse lasts from 0.5 seconds to 10 seconds. In some embodiments, the zirconium precursor pulse lasts from about 1 second to about 5 seconds. 
     In some embodiments, the zirconium precursor is a zirconium compound in which the zirconium is directly bonded to carbon. Bis(methyl-η5-clyclopentadienyl)methoxymethylzirconium (Zr[CH 3 C 5 H 4 ] 2 CH 3 OCH 3  or ZRCMMM) is an example. In some embodiments, the zirconium precursor is a zirconium compound in which the zirconium is directly bonded to oxygen. Zirconium(IV) tert-butoxide (Zr[OC(CH 3 ) 3 ] 4  or ZTB) is an example. In some embodiments, the zirconium precursor is a zirconium compound in which the zirconium is directly bonded to nitrogen. In some embodiments, the zirconium precursor has the form Zr(NR 1 R 2 ) 4  where and R 1  and R 2  are organic functional groups. tetrakis(dimethylamino)zirconium(IV) (Zr[N(CH 3 ) 2 ] 4  or TDMAZ) and tetrakis(ethylmethylamido)zirconium(IV) (Zr[N(CH 3 )(C 2 H 5 )] 4  or TEMAZ) are examples. In some embodiments, the zirconium precursor is one of those shown in the following table, or the like: 
     
       
         
           
               
               
             
               
                   
               
             
            
               
                 Bis(methyl-η5-clyclopentadienyl)methoxymethylzirconium 
                 Zr[CH 3 C 5 H 4 ] 2 CH 3 OCH 3   
               
               
                 Zirconium(IV) tert-butoxide 
                 Zr[OC(CH 3 ) 3 ] 4   
               
               
                 Tetrakis(dimethylamino)zirconium(IV) 
                 (Zr[N(CH 3 ) 2 ] 4   
               
               
                 Tetrakis(ethylmethylamido)zirconium(IV) 
                 Zr[N(CH 3 )(C 2 H 5 )] 4   
               
               
                 Bis(cyclopentadienyl)zirconium(IV) 
                 C 10 H12Zr 
               
               
                 Bis(methyl-η5-cyclopentadienyl)methoxymethylzirconium 
                 Zr(CH 3 C 5 H 4 ) 2 CH 3 OCH 3   
               
               
                 Dimethylbis(pentamethylcyclopentadienyl)zirconium(IV) 
                 C 22 H 36 Zr 
               
               
                 Tetrakis(dimethylamido)zirconium(IV) 
                 [(CH 3 ) 2 N] 4 Zr 
               
               
                 Tetrakis(ethylmethylamido)zirconium(IV) 
                 Zr(NCH 3 C 2 H 5 ) 4   
               
               
                 Zirconium(IV) dibutoxide(bis-2,4-pentanedionate) 
                 C 18 H 32 O 6 Zr 
               
               
                 Zirconium(IV) 2-ethylhexanoate 
                 Zr(C 8 H 15 O 2 ) 4   
               
               
                 Zirconium tetrakis(2,2,6,6-tetramethyl-3,5-heptanedionate) 
                 Zr(OCC(CH 3 ) 3 CHCOC(CH 3 ) 3 ) 4   
               
               
                   
               
            
           
         
       
     
     Following act  715  is act  717 , another purge. This purge may be like the purge of act  713 . There may then follow act  719 , another water pulse like act  711 , and act  721 , another purge. Acts  719  and  721  may be similar or identical to acts  711  and  713  and have the same description. 
     The process may continue with act  723 , pulsing with a chlorine-free hafnium precursor. The chlorine-free hafnium precursor is a hafnium compound that reacts with the oxygen source on the surface to form a layer that includes hafnium. The precursor is selected to be volatile under the process conditions, to deposit only to an extent limited by the amount of water or the like present on the surface, and to have an acceptable reaction rate. In some embodiments, the hafnium precursor pulse lasts 60 seconds or less. In some embodiments, the hafnium precursor pulse lasts from 0.5 seconds to 10 seconds. In some embodiments, the hafnium precursor pulse lasts from about 1 second to about 5 seconds. 
     In some embodiments, the hafnium precursor is a hafnium compound in which the hafnium is directly bonded to carbon. Bis(methyl-η5-clyclopentadienyl)dimethylhafnium (Hf[CH 3 C 5 H 4 ] 2 CH 3 OCH 3  or HfD-CO2) and bis(methyl-η5-clyclopentadienyl)methoxymethylhafnium (HfCH 3 OCH 3 [C 5 H 4 ] 2  or HfD-CO4) are examples. In some embodiments, the hafnium precursor is a hafnium compound in which the hafnium is directly bonded to oxygen. In some embodiments, the hafnium precursor is a hafnium compound in which the hafnium is directly bonded to nitrogen. In some embodiments, the hafnium precursor has the form Hf(NR 1 R 2 ) 4 , where R 1  and R 2  are organic functional groups. Tetrakis(dimethylamino)hafnium(IV) (Hf[N(CH 3 ) 2 ] 4  or TDMAH) and tetrakis(ethylmethylamido)hafnium(IV) (Hf[N(CH 3 )(C 2 H 5 )] 4  or TEMAH) are examples. In some embodiments, the hafnium precursor is one or more of those described in the following table, or the like: 
     
       
         
           
               
               
             
               
                   
               
             
            
               
                 Bis(methyl-η5-clyclopentadienyl)dimethylhafnium 
                 Hf[CH 3 C 5 H 4 ] 2 CH 3 OCH 3   
               
               
                 Bis(methyl-η5-clyclopentadienyl)methoxymethylhafnium 
                 HfCH 3 OCH 3 [C 5 H 4 ] 2   
               
               
                 Tetrakis(dimethylamino)hafnium(IV) 
                 (Hf[N(CH3) 2 ] 4   
               
               
                 tetrakis(ethylmethylamido)hafnium(IV) 
                 Hf[N(CH 3 )(C 2 H 5 )] 4   
               
               
                 Dimethylbis(cyclopentadienyl)hafnium(IV) 
                 (C 5 H 5 ) 2 Hf(CH 3 ) 2   
               
               
                 Hafnium(IV) tert-butoxide 
                 Hf[OC(CH 3 ) 3 ] 4   
               
               
                 Hafnium isopropoxide isopropanol 
                 C 12 H 28 HfO 4   
               
               
                 Tetrakis(diethylamido)hafnium(IV) 
                 [(CH 2 CH 3 ) 2 N] 4 Hf 
               
               
                 Tetrakis(dimethylamido)hafnium(IV) 
                 [(CH 3 ) 2 N] 4 Hf 
               
               
                 Tetrakis(ethylmethylamido)hafnium(IV) 
                 [(CH 3 )(C 2 H 5 )N] 4 Hf 
               
               
                   
               
            
           
         
       
     
     Following act  723  is act  725 , another purge and a repetition of the steps until the ferroelectric layer has been built up to a desired thickness. In the process as described, the actions that incorporate zirconium into the ferroelectric layer alternate with actions that incorporate hafnium into the ferroelectric layer. Optionally, the proportions of these actions are varied, or only the actions that incorporate zirconium are used or only the actions that incorporate halfnium are used. In some embodiments, one layer is deposited every 60 seconds or at a greater frequency. Selection of suitable precursors allows the desired rate to be achieved. 
     In some embodiments, an additional precursor that provides a metal ion is included with either the zirconium precursor or the hafnium precursor. Examples of metal ions that may be provided by the additional precursor include ions of aluminum (Al), silicon (Si), lanthanum (La), scandium (Sc), calcium (Ca), barium (Ba), gadolinium (Gd), yttrium (Y), and the like. In some embodiments the precursor is one of those shown in the following table, or the like: 
     
       
         
           
               
               
             
               
                   
               
             
            
               
                 Aluminum tris(2,2,6,6-tetramethyl-3,5-heptanedionate) 
                 Al(OCC(CH 3 ) 3 CHCOC(CH 3 ) 3 ) 3   
               
               
                 Triisobutylaluminum 
                 Al[(CH 3 ) 2 CHCH 2 ] 3   
               
               
                 Trimethylaluminum 
                 Al(CH 3 ) 3   
               
               
                 Tris(dimethylamido)aluminum(III) 
                 Al(N(CH 3 ) 2 ) 3   
               
               
                 (3-Aminopropyl)triethoxysilane 
                 H 2 N(CH 2 ) 3 Si(OC 2 H 5 ) 3   
               
               
                 N-sec-Butyl(trimethylsilyl)amine 
                 C 7 H 19 NSi 
               
               
                 1,3-Diethyl-1,1,3,3-tetramethyldisilazane 
                 C 8 H 23 NSi 2   
               
               
                 Dodecamethylcyclohexasilane 
                 (Si(CH 3 ) 2 ) 6   
               
               
                 Hexamethyldisilane 
                 (Si(CH 3 ) 3 ) 2   
               
               
                 Hexamethyldisilazane 
                 (CH 3 ) 3 SiNHSi(CH 3 ) 3   
               
               
                 2,4,6,8,10-Pentamethylcyclopentasiloxane 
                 (CH 3 SiHO) 5   
               
               
                 Pentamethyldisilane 
                 (CH3) 3 SiSi(CH 3 ) 2 H 
               
               
                 Silicon tetrabromide 
                 SiBr 4   
               
               
                 Tetraethylsilane 
                 Si(C 2 H 5 ) 4   
               
               
                 2,4,6,8-Tetramethylcyclotetrasiloxane 
                 (HSiCH 3 O) 4   
               
               
                 1,1,2,2-Tetramethyldisilane 
                 (CH 3 ) 2 SiHSiH(CH 3 ) 2   
               
               
                 Tetramethylsilane 
                 Si(CH 3 ) 4   
               
               
                 N,N′,N″-Tri-tert-butylsilanetriamine 
                 HSi(HNC(CH 3 ) 3 ) 3   
               
               
                 Tris(tert-butoxy)silanol 
                 ((CH 3 ) 3 CO) 3 SiOH 
               
               
                 Tris(tert-pentoxy)silanol 
                 (CH 3 CH 2 C(CH 3 ) 2 O) 3 SiOH 
               
               
                 Tris[N,N-Bis(trimethylsilyl)amide]gadolinium(III) 
                 Gd(N(Si(CH 3 ) 3 ) 2 ) 3   
               
               
                 Tris(tetramethylcyclopentadienyl)gadolinium(III) 
                 C 27 H 39 Gd 
               
               
                 Tris(isopropylcyclopentadienyl)gadolinium 
                 C 24 H 33 Gd 
               
               
                 Triethylgallium 
                 (CH 3 CH 2 ) 3 Ga 
               
               
                 Trimethylgallium 
                 Ga(CH 3 ) 3   
               
               
                 Tris(dimethylamido)gallium(III) 
                 C 12 H 36 Ga 2 N 6   
               
               
                 Lanthanum(III) isopropoxide 
                 C 9 H 21 LaO 3   
               
               
                 Tris[N,N-bis(trimethylsilyl)amide]lanthanum(III) 
                 La(N(Si(CH 3 ) 3 ) 2 ) 3   
               
               
                 Tris(cyclopentadienyl)lanthanum(III) 
                 La(C 5 H 5 ) 3   
               
               
                 Lanthanum (2,2,6,6-tetramethyl-3,5-heptanedionato) 
                 La(OCC(CH 3 ) 3 CHCOC(CH 3 ) 3 ) 3   
               
               
                 Tris(tetramethylcyclopentadienyl)lanthanum(III) 
                 C 27 H 39 La 
               
               
                 Tris[N,N-bis(trimethylsilyl)amide]yttrium 
                 [[(CH 3 ) 3 Si] 2 N] 3 Y 
               
               
                 Tris(butylcyclopentadienyl)yttrium(III) 
                 Y(C 5 H 4 CH 2 (CH 2 ) 2 CH 3 ) 3   
               
               
                 Tris(cyclopentadienyl)yttrium(III) 
                 Y(C 5 H 5 ) 3   
               
               
                 Yttrium 2-methoxyethoxide 
                 C 9 H 21 O 6 Y 
               
               
                 Yttrium(III) tris(isopropoxide) 
                 C 9 H 21 O 3 Y 
               
               
                 Yttrium(III) tris(2,2,6,6-tetramethyl-3,5-heptanedionate) 
                 Y(OCC(CH 3 ) 3 CHCOC(CH 3 ) 3 ) 3   
               
               
                   
               
            
           
         
       
     
     In some embodiments, the metal ion is aluminum (Al) or the like. In some embodiments, the metal ion is silicon (Si) or the like. In some embodiments, the metal ion is lanthanum (La) or the like. In some embodiments, the metal ion is gadolinium (Gd) or the like. In some embodiments, the metal ion is yttrium (Y) or the like. In some embodiments, the additional precursor includes the metal ion directly bonded to oxygen, nitrogen, carbon, or a combination thereof. In some embodiments, the additional precursor includes the metal ion directly bonded to carbon. In some embodiments, the additional precursor includes the metal ion directly bonded to oxygen. In some embodiments, the additional precursor includes the metal ion directly bonded exclusively to oxygen and/or carbon. In some embodiments, the additional precursor includes the metal ion directly bonded to nitrogen. 
       FIGS. 8 through 13  illustrate cross-sectional views exemplifying another method according to the present disclosure of forming a memory cell. While  FIGS. 8 through 13  are described with reference to various embodiments of a method, it will be appreciated that the structures shown in  FIGS. 8 through 13  are not limited to the method but rather may stand alone separate from the method. While  FIGS. 8 through 13  are described as a series of acts, it will be appreciated that the order of the acts may be altered in other embodiments. While  FIGS. 8 through 13  illustrate and describe a specific set of acts, some acts that are illustrated and/or described may be omitted in other embodiments. Further, acts that are not illustrated and/or described may be included in other embodiments. While the method of  FIGS. 8 through 13  is described in terms of forming the integrated circuit device  100 B, the method may be used to form other integrated circuit devices. 
     As shown by the cross-sectional view  800  of  FIG. 8 , the method may begin with forming a memory cell stack  801  on the substrate  103 B. The memory cell stack  801  may include an insulating layer  109 B, a ferroelectric layer  107 B, an alloy work function metal layer  121 B, a second work function metal layer  123 B, and a gate electrode  105 B. The process options for forming these layers are the same as for the insulating layer  109 A, the ferroelectric layer  107 A, the alloy work function metal layer  121 A, the second work function metal layer  123 A, and the gate electrode  105 A respectively. 
     As shown by the cross-sectional view  900  of  FIG. 9 , a mask  901  may be formed and used to pattern the memory cell  101 B from the memory cell stack  801 . The mask  901  may be formed with photolithography. Patterning may include dry etching. After patterning, the mask  901  may be stripped. 
     As shown by the cross-sectional view  1000  of  FIG. 10 , a sidewall spacer  125  may be formed around the memory cells  101 B. Forming the sidewall spacer  125  may comprise depositing a spacer material such as silicon nitride (SiN) or the like followed by etching. 
     As shown by the cross-sectional view  1100  of  FIG. 11 , the source region  118 B and the drain region  104 B may be dopped in a self-aligned doping process using the sidewall spacer  125 . 
     As shown by the cross-sectional view  1200  of  FIG. 12 , an interlevel dielectric  115 B may be formed over and around the memory cell  101 B. The process options for forming the interlevel dielectric  115 B are the same as for the interlevel dielectric  115 A. 
     As shown by the cross-sectional view  1300  of  FIG. 13 , a mask  1303  maybe formed using photolithography and used to pattern opening  1301  in the interlevel dielectric  115 B. The openings  1301  may be filled to form the source coupling  117 B and the drain coupling  113 B as shown in  FIG. 1B . The process options for filling the opening  1301  to form the source coupling  117 B and the drain coupling  113 B are the same as the ones for filling the trenches  603  (see  FIG. 6 ) to form the source coupling  117 A and the drain coupling  113 B. 
       FIG. 14  presents a flow chart for a process  1400  which may be used to form an integrated circuit device according to the present disclosure. The process  1400  includes steps for forming the integrated circuit device  100 B of  FIG. 1B . While the process  1400  of  FIG. 14  is illustrated and described herein as a series of acts or events, it will be appreciated that the illustrated ordering of such acts or events is not to be interpreted in a limiting sense. For example, some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein. Further, not all illustrated acts are required to implement one or more aspects or embodiments of the description herein, and one or more of the acts depicted herein may be carried out in one or more separate acts and/or phases. 
     The process  1400  begins with acts  1401  through  1409 , which form a memory cell stack such as the one illustrated by the cross-sectional view  800  of  FIG. 8 . Act  1401  is depositing an insulating layer, act  1403  is depositing a ferroelectric layer, act  1405  is depositing an alloy work function metal layer, act  1407  is depositing a second work function metal layer, and act  1409  is depositing a gate electrode. These may be substantially the same as act  707 , act  706 , act  704 , act  703 , and act  702  respectively of the process  700 . 
     Act  1411  is patterning the memory cell stack to define memory cells. The cross-sectional view  900  of  FIG. 9  provides an example. 
     Act  1413  is forming spacers around the memory cells. The cross-sectional view  1000  of  FIG. 10  provides an example. 
     Act  1415  is implanting source and drain regions adjacent the memory cells. The cross-sectional view  1100  of  FIG. 11  provides an example. 
     Act  1417  is depositing an interlevel dielectric over and around the memory cells. The cross-sectional view  1200  of  FIG. 12  provides an example. 
     Act  1419  is forming openings in the interlevel dielectric for source and drain connections. The cross-sectional view  1300  of  FIG. 13  provides an example. 
     Act  1421  is filling the openings with conductive material to form source and drain connection. Act  1423  is CMP.  FIG. 1B  provides an example of a resulting structure. 
     In some embodiments titanium (Ti), titanium nitride (TiN), or some other compound that includes titanium is formed from chlorine-free gaseous precursors. Examples of chlorine-free gaseous precursors that may be used to form layers with titanium (Ti), titanium nitride (TiN), the like, or other titanium compounds include tetrakis(diethylamido)titanium(IV) ([(C 2 H 5 ) 2 N] 4 Ti), tetrakis(dimethylamido)titanium(IV) ([(CH 3 ) 2 N] 4 Ti), tetrakis(ethylmethylamido)titanium(IV) ([(CH 3 C 2 H 5 )N] 4 Ti), titanium(IV) diisopropoxidebis(2,2,6,6-tetramethyl-3,5-heptanedionate) (Ti[OCC(CH 3 ) 3 CHCOC(CH 3 ) 3 ] 2 (OC 3 H 7 ) 2 ), and the like. 
     In some embodiments molybdenum (Mo), molybdenum nitride (MoN), or some other compound that includes molybdenum is formed from chlorine-free gaseous precursors. Examples of chlorine-free gaseous precursors that may be used to form layers with molybdenum (Mo), molybdenum nitride (MoN), the like, or other molybdenum compounds include cyclopentadienyl molybdenum tricarbonyl dimer (C 16 H 10 Mo 2 O 6 ), molybdenumhexacarbonyl (Mo(CO) 6 ), and the like. 
     In some embodiments nickel (Ni) or a compound that includes nickel is formed from chlorine-free gaseous precursors. Examples of chlorine-free gaseous precursors that may be used to form layers with nickel (Ni) or nickel compounds include bis(cyclopentadienyl)nickel(II) (Ni(C 5 H 5 ) 2 ), bis(ethylcyclopentadienyl)nickel(II) (Ni(C 5 H 4 C 2 H 5 ) 2 ), nickel(II) bis(2,2,6,6-tetramethyl-3,5-heptanedionate) (Ni(OCC(CH 3 ) 3 CHCOC(CH 3 ) 3 ) 2 ), and the like. 
     In some embodiments aluminum (Al), aluminum nitride (AlN), or some other compound that includes aluminum is formed from chlorine-free gaseous precursors. Examples of chlorine-free gaseous precursors that may be used to form layers with aluminum (Al), aluminum nitride (AlN), the like, or other aluminum compounds include aluminum tris(2,2,6,6-tetramethyl-3,5-heptanedionate) (Al(OCC(CH 3 ) 3 CHCOC(CH 3 ) 3 ) 3 ), triisobutylaluminum ([(CH 3 ) 2 CHCH 2 ] 3 Al), trimethylaluminum ((CH 3 ) 3 Al), tris(dimethylamido)aluminum(III) (Al(N(CH 3 ) 2 ) 3 ), and the like 
     In some embodiments copper (Cu) or a compound that includes copper is formed from chlorine-free gaseous precursors. Examples of chlorine-free gaseous precursors that may be used to form layers with copper (Cu) or copper compounds include copper bis(6,6,7,7,8,8,8-heptafluoro-2,2-dimethyl-3,5-octanedionate) (Cu(OCC(CH 3 ) 3 CHCOCF 2 CF 2 CF 3 ) 2 ), copper bis(2,2,6,6-tetramethyl-3,5-heptanedionate) (Cu(OCC(CH 3 ) 3 CHCOC(CH 3 ) 3 ) 2 ), and the like. 
     In some embodiments platinum (Pt) or a compound that includes platinum is formed from chlorine-free gaseous precursors. Examples of chlorine-free gaseous precursors that may be used to form layers with platinum (Pt) or platinum compounds include trimethyl(methylcyclopentadienyl)platinum(IV) (CsH 4 CH 3 Pt(CH 3 ) 3 ) and the like. 
     In some embodiments ruthenium (Ru) or a compound that includes ruthenium is formed from chlorine-free gaseous precursors. Examples of chlorine-free gaseous precursors that may be used to form layers with ruthenium (Ru) or ruthenium compounds include bis(cyclopentadienyl)ruthenium(II) (C 10 H 10 Ru), bis(ethylcyclopentadienyl)ruthenium(II) (C 7 H 9 RuC 7 H 9 ), triruthenium dodecacarbonyl (Ru 3 (CO) 12 ) 
     In some embodiments tantalum (Ta), tantalum nitride (TaN), or some other compound that includes tantalum is formed from chlorine-free gaseous precursors. Examples of chlorine-free gaseous precursors that may be used to form layers with tantalum (Ta), tantalum nitride (TaN), the like, or other tantalum compounds include pentakis(dimethylamino)tantalum(V) (Ta(N(CH 3 ) 2 ) 5 ), tantalum(V) ethoxide (Ta(OC 2 H 5 ) 5 ), tris(diethylamido)(tert-butylimido)tantalum(V)((CH 3 ) 3 CNTa(N(C 2 H 5 ) 2 ) 3 ), tris(ethylmethylamido)(tert-butylimido)tantalum(V) (C 13 H 33 N 4 Ta), and the like. 
     In some embodiments tungsten (W), tungsten nitride (WN), tungsten carbonitride (WCN), or some other compound that includes tungsten is formed from chlorine-free gaseous precursors. Examples of chlorine-free gaseous precursors that may be used to form layers with tungsten (W), tungsten nitride (WN), tungsten carbonitride (WCN), the like, or other tungsten compounds include bis(tert-butylimino)bis(tert-butylamino)tungsten ((C 4 H 9 NH) 2 W(C 4 H 9 N) 2 ), bis(tert-butylimino)bis(dimethylamino)tungsten(VI) (((CH 3 ) 3 CN) 2 W(N(CH 3 ) 2 ) 2 ), bis(cyclopentadienyl)tungsten(IV) dihydride (C 10 H 12 W), bis(isopropylcyclopentadienyl)tungsten(IV) dihydride ((C 5 H 4 CH(CH 3 ) 2 ) 2 WH 2 ), tetracarbonyl(1,5-cyclooctadiene)tungsten(0) (C 12 H 2 O 4 W), tungsten hexacarbonyl (W(CO) 6 ), and the like. 
     In some embodiments, a gaseous chlorine-free metal precursor is a metal compound having a hydrocarbon functional group. Each of the foregoing examples of chlorine-free metal precursors is an example in which the chlorine-free metal precursors is a metal compound having a hydrocarbon functional group. 
     In some embodiments, a gaseous chlorine-free metal precursor is a metal compound having a carbonyl functional group. Example in which the gaseous chlorine-free metal precursor is a metal compound having a carbonyl function group include cyclopentadienyl molybdenum tricarbonyl dimer (C 16 H 10 Mo 2 O 6 ), molybdenumhexacarbonyl (Mo(CO) 6 ), triruthenium dodecacarbonyl (Ru 3 (CO) 12 ), bis(isopropylcyclopentadienyl)tungsten(IV) dihydride ((C 5 H 4 CH(CH 3 ) 2 ) 2 WH 2 ), tungsten hexacarbonyl (W(CO) 6 ), and the like. These compounds may have particularly high deposition rates. 
     In some embodiments, a gaseous chlorine-free metal precursor is cyclopentadienyl complex. Example in which the chlorine-free metal precursor is a cyclopentadienyl complex include cyclopentadienyl molybdenum tricarbonyl dimer (C 16 H 10 Mo 2 O 6 ), bis(cyclopentadienyl)nickel(II) (Ni(C 5 H 5 ) 2 ), bis(ethylcyclopentadienyl)nickel(II) (Ni(C 5 H 4 C 2 H 5 ) 2 ), trimethyl(methylcyclopentadienyl)platinum(IV) (CsH 4 CH 3 Pt(CH 3 ) 3 ), bis(cyclopentadienyl)ruthenium(II) (C 10 H 10 Ru), bis(ethylcyclopentadienyl)ruthenium(II) (C 7 H 9 RuC 7 H 9 ), bis(cyclopentadienyl)tungsten(IV) dihydride (C 10 H 12 W), bis(isopropylcyclopentadienyl)tungsten(IV) dihydride ((C 5 H 4 CH(CH 3 ) 2 ) 2 WH 2 ), and the like. Many different metals can be formed into cyclopentadienyl complexes. Choosing cyclopentadienyl complexes enhances uniformity and predictability among deposition processes that may be used to form layers having a variety of compositions. In some embodiments, a deposition process uses two cyclopentadienyl complexes corresponding to two distinct metals. 
     In some embodiments, a gaseous chlorine-free metal precursor is a metal compound having a nitrogen function group. Example in which the chlorine-free metal precursor is a metal compound having a nitrogen function group include tetrakis(diethylamido)titanium(IV) ([(C 2 H 5 ) 2 N] 4 Ti), tetrakis(dimethylamido)titanium(IV) ([(CH 3 ) 2 N] 4 Ti), tetrakis(ethylmethylamido)titanium(IV) ([(CH 3 C 2 H 5 )N] 4 Ti), tris(dimethylamido)aluminum(III) (Al(N(CH 3 ) 2 ) 3 ), pentakis(dimethylamino)tantalum(V) (Ta(N(CH 3 ) 2 ) 5 ), tantalum(V) ethoxide (Ta(OC 2 H 5 ) 5 ), tris(diethylamido)(tert-butylimido)tantalum(V)((CH 3 ) 3 CNTa(N(C 2 H 5 ) 2 ) 3 ), tris(ethylmethylamido)(tert-butylimido)tantalum(V) (C 13 H 33 N 4 Ta), bis(tert-butylimino)bis(tert-butylamino)tungsten ((C 4 H 9 NH) 2 W(C 4 H 9 N) 2 ), bis(tert-butylimino)bis(dimethylamino)tungsten(VI) (((CH 3 ) 3 CN) 2 W(N(CH 3 ) 2 ) 2 ), and the like. These compounds may be particularly useful in forming nitrogen-containing metal compounds. 
     Some aspects of the present disclosure relate to an integrated circuit device that includes a ferroelectric layer having less than 1 ppm chlorine. In some embodiments, the ferroelectric layer is HF x Zr 1-x O 2 , wherein 0≤x≤1. In some embodiments, the ferroelectric layer. In some embodiments, the layer of ferroelectric is part of a memory cell. In some embodiments a work function metal layer in direct contact with the ferroelectric layer has less than 1 ppm chlorine. In some embodiments the work function metal layer comprises an alloy of two distinct metals. In some embodiments a second work function metal layer is also in direct contact with the ferroelectric layer and has less than 1 ppm chlorine. In some embodiments a gate electrode is also in direct contact with the ferroelectric layer and has less than 1 ppm chlorine. 
     Some aspects of the present disclosure relate to an integrated circuit device comprising a memory cell that includes a channel extending between a source and a drain, a gate electrode, and a ferroelectric layer between the gate electrode and the channel. The memory cell has a leakage current and a time-dependent dielectric breakdown rate (a TDDB rate). The TDDB rate is defined as an initial value of the leakage current divided by a time of operation over which the leakage current doubles from the initial value. The TDDB rate is less than an amount by which the TDDB rate would increase if 1 ppm of chlorine were added to the ferroelectric layer. 
     Some aspects of the present disclosure relate to a method of forming an integrated circuit device that includes forming a ferroelectric layer by atomic layer deposition using chlorine-free precursors. In some embodiments the chlorine-free precursors include a zirconium (Zr) precursor or a hafnium (Hf) precursor. In some embodiments, the method further includes forming a work function metal layer from gaseous chlorine-free precursors wherein the work function metal layer comes into direct contact with the ferroelectric layer. In some embodiments, the work function metal layer is an alloy work function metal layer. In some embodiments the gaseous chlorine-free precursors comprise a metal compound with a hydrocarbon functional group. In some embodiments the gaseous chlorine-free precursors comprise a metal compound with a carbonyl functional group. In some embodiments the gaseous chlorine-free precursors comprise a metal compound with a nitrogen functional group. In some embodiments the gaseous chlorine-free precursors comprise a metal in a cyclopentadienyl complex. 
     The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.