Patent Publication Number: US-7586329-B2

Title: Capacitively-coupled level restore circuits for low voltage swing logic circuits

Description:
RELATED APPLICATIONS 
     This application is a Continuation of U.S. application Ser. No. 10/931,379, filed Aug. 31, 2004 now U.S. Pat. No. 7,176,719, which is incorporated herein by reference. 
    
    
     FIELD 
     The present disclosure relates generally to regeneration of signals in semiconductor devices, and more particularly to level restore circuits for low voltage swing logic circuits. 
     BACKGROUND 
     Semiconductors devices such as s and processors reside in many computers and electronic products to store and process data. 
     A typical memory device or processor includes logic circuits to perform logic functions. Some logic circuits give the results of the logic functions in form of resulting signals with a relatively low voltage or low signal swing. In some cases, the resulting signals may have signal levels at inappropriate levels to be considered as full logic levels (logic one and logic zero) useful for further processing. In these cases, level restore circuits are used to restore the resulting signals to the full logic levels. Some level restore circuits have a sense amplifier with sense amplifier input nodes to sense the resulting signals provided by the logic circuits to generate output signals with the full logic levels. 
     A typical sense amplifier includes transistors. Transistors are susceptible to mismatches due to variations in manufacturing process. Mismatches in the transistors may create an offset voltage between the input nodes of the sense amplifier when the sense amplifier is reset. 
     The offset voltage may result in invalid logic levels at the output nodes of the typical sense amplifier after the reset. Further, mismatches in the transistors often require the signal swing of the resulting signals at or the input signals at the input nodes of the sense amplifier to be above a specific signal swing. Thus, in cases where the signal swing of the input signals is relatively low, a typical sense amplifier may be unreliable to produce output signals with correct logic levels. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  shows an embodiment of a level restore circuit. 
         FIG. 2  shows an exemplary timing diagram for  FIG. 1 . 
         FIG. 3  shows a variation of the level restore circuit of  FIG. 1 . 
         FIG. 4  shows an embodiment of device having a level restore circuit. 
         FIG. 5  shows an embodiment of a system. 
     
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
     The following description and the drawings illustrate specific embodiments of the present disclosure sufficiently to enable those skilled in the art to practice them. Other embodiments may incorporate structural, logical, electrical, process, and other changes. In the drawings, like features or like numerals describe substantially similar components throughout the several views. Examples merely typify possible variations. Portions and features of some embodiments may be included in or substituted for those of others. References to “an”, “one”, or “various” embodiments in the present disclosure are not necessarily to the same embodiment, and such references contemplate more than one embodiments. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present disclosure is defined by the appended claims, along with the full scope of equivalents to which such claims are entitled. 
       FIG. 1  shows a level restore circuit. Level restore circuit  100  receives an input signal pair IN and IN* and produces an output signal pair OUT and OUT*. In some embodiments, the IN and IN* signal pair is a differential signal pair and the OUT and OUT* signal pair is a differential signal pair. The IN and IN* signals have a signal swing smaller than the signal swing of the OUT and OUT* signals. In some embodiments, the OUT and OUT* signals have a signal swing corresponding to logic levels such as logic one and logic zero. 
     In some embodiments, the IN and IN* signals represent complementary data or complementary logic values such as logic one and logic zero. However, the signal levels of the IN and IN* signals themselves may not be at appropriate signal levels to drive other circuits or to allow other circuits to correctly interpret the IN and IN* signals as representing the complementary logic values. Level restore circuit  100  restores the signal levels of the IN and IN* signals to appropriate restored signal levels so that the restored signal levels can correctly be interpreted as the complementary logic values. In level restore circuit  100 , the OUT and OUT* signals represent the restored signal levels of the IN and IN* signals. 
     Level restore circuit  100  includes a first differential side  101  and a second differential side  102  coupled together by a capacitive network  160 . Differential sides  101  and  102  couple in parallel between supply nodes  105  and  107 . Supply node  105  receives a voltage V 1 . Supply node  107  receives a voltage V 2 . In some embodiments, V 1  is a supply voltage of level restore circuit  100  and V 2  is ground. 
     Differential side  101  has an input node  111  and output node  121 . Differential side  102  has an input node  112  and output node  122 . Input nodes  111  and  112  form an input node pair to receive the IN and IN* signals. Output nodes  121  and  122  form an output node pair to provide the OUT and OUT* signals. Differential sides  101  and  102  of level restore circuit  100  serve as differential sides of a differential amplifier or a sense amplifier. 
     Differential side  101  includes transistors  131  and  141  coupled in series between supply nodes  105  and  107 . Transistors  131  and  141  have a common drain coupled to output node  121 . Transistor  131  has gate coupled to input node  111  to receive the IN signal. Transistor  141  has gate coupled to a feedback node  151  to receive a feedback voltage from differential side  102 . 
     Differential side  102  includes transistor  132  and  142  coupled in series between supply nodes  105  and  107 . Transistors  132  and  142  have a common drain coupled to output node  122 . Transistor  132  has gate coupled to input node  112  to receive the IN* signal. Transistor  142  has a gate coupled to a feedback node  152  to receive a feedback voltage from differential side  101 . 
     In embodiments represented by  FIG. 1 , the transistors in each of the differential sides  101  and  102  are complementary metal-oxide semiconductor (CMOS) transistors. In some embodiments, the transistors in each of the differential sides  101  and  102  may be other types of transistors. In differential side  101 , transistors  131  and  141  are a pair of CMOS transistors with transistor  131  being a p-channel transistor and transistor  141  being an n-channel transistor. In differential side  102 , transistors  132  and  142  are a pair of CMOS transistors with transistor  132  being a p-channel transistor and transistor  142  being an n-channel transistor. CMOS transistors allow level restore circuit  100  to operate at a relatively high frequency and at a relatively low power. In some embodiments, the IN, IN*, OUT and OUT* signals have a frequency of seven gigahertz (7 GHz) and above. 
     Each of the transistors  131 ,  132 ,  141 , and  142  has a threshold voltage. The threshold voltage of a transistor is the gate-to-source voltage at which the transistor starts to turn on (start to conduct). Transistor parameters such as channel length, channel width, gate oxide thickness, and doping concentration affect the value of the threshold voltage. 
     Transistors  131 ,  132 ,  141 , and  142  are matched when the values of the transistor parameters among all of the transistors  131 ,  132 ,  141 , and  142  are unvaried. In some embodiments, transistors  131 ,  132 ,  141 , and  142  are matched when the threshold voltages among the transistors are unchanged. 
     Transistors  131 ,  132 ,  141 , and  142  are mismatched when at least one of the transistors has a transistor parameter with a value different from the values of the transistor parameters of other transistors. In some embodiments, transistors  131 ,  132 ,  141 , and  142  are mismatched such that the threshold voltage of one of the transistors is different from the threshold voltages of the other transistors. 
     Capacitive network  160  includes a coupling unit  170  and a stabilizing unit  180 . Coupling unit  170  provides a positive feedback between the differential sides  101  and  102  to allow the OUT and OUT* signals to switch between different signal levels based on the IN and IN* signals. Stabilizing unit  180  improves stability of the OUT and OUT* signals when the OUT and OUT* signals switch between the different signal levels. 
     Coupling unit  170  includes coupling capacitors  171  and  172 . Coupling capacitor  171  couples between output node  121  of differential side  101  and feedback node  152  of differential side  102  to provide a positive feedback to differential side  102 . 
     Coupling capacitor  172  couples between output node  122  of differential side  102  and feedback node  151  of differential side  101  to provide a positive feedback to differential side  101 . The connections of coupling capacitors  171  and  172  between differential sides  101  and  102  are referred to as capacitively cross-coupled connections or capacitively-coupled positive feedback connections. 
     Stabilizing unit  180  includes stabilizing capacitors  181  and  182 . Stabilizing capacitor  181  couples between output node  121  and feedback node  151 . Stabilizing capacitor  182  couples between output node  122  and feedback node  152 . Stabilizing capacitor  181  improves stability of the OUT signal when the OUT signal switches between different signal levels. Stabilizing capacitor  182  improves stability of the OUT* signal when the OUT* signal switches between different signal levels. 
     The capacitance values of coupling unit  170  and stabilizing unit  180  determine the gain of level restore circuit  100 . In some embodiments, each of the coupling capacitors  171  and  172  has a first capacitance value and each of the stabilizing capacitors  181  and  182  has a second capacitance value. The ratio of the first capacitance value and the second capacitance value determines the gain of level restore circuit  100 . 
     The capacitance value of each of the coupling capacitors  171  and  172  is greater than the capacitance value of each of the stabilizing capacitors  181  and  182 . In some embodiments, the capacitance value of each of the coupling capacitors  171  and  172  is about 10 times the capacitance value of each of the stabilizing capacitors  181  and  182 . For example, each of the coupling capacitors  171  and  172  may have a capacitance value of 100 femtofarads while each of the stabilizing capacitors  181  and  182  may have a capacitance value of 10 femtofarads. 
     Level restore circuit  100  further includes reset units  190  and  192 . Reset units  190  and  192  together form a reset network to reset level restore circuit  100  in a reset mode. Reset units  190  and  192  respond to a reset signal RESET. When the RESET signal is activated, level restore circuit  100  is reset. When the RESET signal is deactivated, level restore circuit  100  is released from the reset. In some embodiments, the RESET signal is activated when it has high signal level and deactivated when it has a low signal level. In some embodiments, the RESET signal is a clock signal. 
     Reset unit  192  resets the charge (voltage) held in stabilizing capacitors  181  and  182  of both differential sides  101  and  102  to an initial value during the reset mode of level restore circuit  100 . Reset unit  192  includes reset transistors  195  and  196 . Both transistors  193  and  194  respond to the reset signal RESET. Transistor  195  responds to the RESET signal to reset the charge in stabilizing capacitor  181  to an initial value. Transistor  196  responds to the RESET signal to reset the charge in stabilizing capacitor  182  to the initial value. In some embodiments, the initial value is zero. 
     Reset unit  190  includes reset transistors  193  and  194 . Transistor  193  responds to the RESET signal to reset input node  111  and output node  121  to a first reset voltage. Transistor  194  responds to the RESET signal to reset input node  112  and output node  122  to a second reset voltage. The first and second reset voltages are independent from each other. 
     In some embodiments, although the first and second reset voltages are independent from each other, each of the first and second reset voltages may be equal to an equalized voltage. For example, in embodiments where transistors  131 ,  132 ,  141 , and  142  are matched, each of the first and second reset voltages may be equal to an equalized voltage of the average of V 1  and V 2 . 
     In some embodiments, the first and second reset voltages are independent from each other and are also different voltages. For example, in embodiments where a mismatch exists among transistors  131 ,  132 ,  141 , and  142 , the first reset voltage may have a first value and second reset voltage may have a second value different from the first value. 
     Level restore circuit  100  restores the signal level of the IN and IN* signals to appropriate logic levels (represented by the OUT and OUT* signals) in both cases where transistors  131 ,  132 ,  141 , and  142  are matched or mismatched. 
     In level store circuit  100 , cross-coupling differential sides  101  and  102  with a capacitive network  160  reduces the effect of mismatches and offsets introduced by transistors  131 ,  132 ,  141 , and  142 . The reduction of the effect of mismatches and offsets allows level restore circuit  100  to be more reliable in producing the OUT and OUT* signals with correct logic levels based on the IN and IN* signals when the IN and IN* signal have a relatively low signal swing. 
     The operation of level restore circuit  100  is described in connection with  FIG. 2 . 
       FIG. 2  shows an exemplary timing diagram for  FIG. 1 . In  FIG. 2 , V 3  through V 8  represent voltages of the IN, IN*, OUT, and OUT* signals at different times such as times T 0 , T 1 , and T 2 . 
     Between times T 0  and T 1 , level restore circuit  100  of  FIG. 1  is reset. As described in  FIG. 1 , when level restore circuit  100  is reset, both input node  111  output node  121  are reset to a first reset voltage, and both node  112  output node  122  are reset to a second reset voltage. In  FIG. 2 , V 5  represents the first reset voltage and V 6  represents the second reset voltage. 
     During the reset between times T 0  and T 1  in  FIG. 2 , transistors  193 ,  194 ,  195 , and  196  turn on when the RESET signal is activated. Transistors  195  and  196  turn on to reset the potential across the plates of each of the stabilizing capacitors  181  and  182  to zero. Transistor  193  turns on to couple input node  111  and output node  121  together. Thus, the input node  111  and output node  121  are equalized to the first reset voltage. Transistor  194  turns on to couple input node  112  and output node  122  together. Thus, the input node  112  and output node  122  are equalized to a second reset voltage. 
     Transistors  193 ,  194 ,  195 , and  196  turn off when the RESET signal is deactivated after time T 1  in  FIG. 2 . When transistors  193 ,  194 ,  195 , and  196  turn off, input node  111  and output node  121  are separated from each other, input node  112  and output node  122  are also separated from each other. Level restore circuit  100  senses the differential signal at input nodes  111  and  112  and switches the OUT and OUT* signals to appropriately signal levels. 
     As shown in  FIG. 2 , the first and second reset voltages have different values. V 5  is less than V 6 . V OFFSET  is the offset voltage or the difference between V 6  and V 5 . In some embodiments, V OFFSET  exists because a mismatch exits among the transistors  131 ,  132 ,  141 , and  142  of  FIG. 1 . For example, the threshold voltage of the transistors  141  is lower than the threshold voltage of each of the other transistors  131 ,  141 , and  142 . When level restore circuit  100  is reset between times T 0  and T 1  in  FIG. 2 , the lower threshold voltage of transistor  141  of  FIG. 1  causes an offset voltage to develop (V OFFSET  in  FIG. 2 ) between input nodes  111  and  112  or between output nodes  121  and  122 . 
     From time T 1  to time T 2  (after the reset) the IN signal goes down from V 5  to V 4  while the IN* signal goes up from V 6  to V 7 . V DIFF1  is the difference between V 5  and V 4 . V DIFF2  is the difference between V 7  and V 6 . In some embodiments, V DIFF1  and V DIFF2  represent complementary data provided by a logic circuit. 
     In response to V DIFF1  and V DIFF2 , level restore circuit  100  switches the OUT signal from V 5  to V 8  and switches the OUT* signal from V 7  to V 3 . V 8  and V 3  of the OUT and OUT* signals correspond to logic one and logic zero of the complementary data represented by the IN and IN* signals. In some embodiments, V 8  and V 3  correspond to a rail-to-rail voltage such as Vcc and ground where Vcc is the supply voltage of level restore circuit  100 . 
     In some embodiments, V OFFSET  has a value of 200 mv (millivolt) while each of the V DIFF1  and V DIFF2  is about 50 mv (millivolt). The sum of V DIFF1  and V DIFF2  is the input differential voltage between the IN and IN* signal. Thus, in some embodiments, the input differential voltage (V DIFF1 +V DIFF2 ) is less than the offset voltage V OFFSET . In some embodiments, the differential voltage is about ten percent (10%) of Vcc and the offset voltage (V OFFSET ) is greater than 10% of Vcc, where Vcc is the supply voltage of level restore circuit  100 . 
     In other level restore circuits where differential sides are coupled together by hard wires instead of by a capacitive network such as the capacitive network  160  of  FIG. 1 , the other level restore circuits may interpret the offset voltage as being a part of the input differential voltage of the IN and IN* signals when the input differential voltage is less than the offset voltage. Thus, incorrect restored signal levels at the output nodes of the other level restore circuits may occur when the differential signal is less than the offset voltage in other level restore circuits. 
     In level restore circuit  100 , however, capacitors  171  and  172  absorb the offset voltage V OFFSET  such that the OUT and OUT* signals still give correct logic levels when mismatches exist among the transistors of level restore circuit  100  and when the input differential voltage is less than the offset voltage. As shown in  FIG. 2 , the mismatches result in an offset voltage VOFFSET and the input differential voltage (V DIFF1 +V DIFF2 ) is less than the offset voltage. However the OUT and OUT* signals still give correct logic levels at V 8  and V 3 , which correspond to logic one and logic zero. 
       FIG. 3  shows a variation of the level restore circuit of  FIG. 1 . In  FIG. 3 , level restore circuit  300  includes elements similar to the elements of level restore circuit  100  of  FIG. 1 . In  FIG. 3 , however, the p-channel and n-channel transistors swap locations and supply nodes  305  and  307  also swap locations in comparison with the level restore circuit  100  of  FIG. 1 . In  FIG. 3 , transistors  331  and  332  are n-channel transistors while transistors  341  and  342  are the p-channel transistors. Supply node  305  receives V 2  while supply node  307  receives V 1 . As described in  FIG. 1 , in some embodiments, V 1  is the supply voltage of level restore circuit  100  and V 2  is ground. Similarly for  FIG. 3 , in some embodiments, V 1  is the supply voltage of level restore circuit  300  and V 2  is ground. Level restore circuit  300  operates in a fashion similar to that of level restore circuit  100  of  FIG. 1 . 
       FIG. 4  shows an embodiment of a device having a level restore circuit. Device  400  may be a memory device, a processor, or other types of devices. For the purposes of illustrating embodiments of the present disclosure,  FIG. 400  shows only a portion of device  400 . Device  400  includes a circuit  410  and a level restore circuit  420 . 
     In some embodiments, device  400  is a memory device and circuit  410  includes an address decoder to decode address locations of memory cells of the memory device. In other embodiments, circuit  410  includes logic circuit for performing logic functions. Examples of logic functions include logic functions OR, NOR, AND, NAND, exclusive OR, and other logic functions. In some other embodiments, circuit  410  includes an adder circuit. 
     Circuit  410  receives a pair of complementary data signal D IN  and D IN * at input nodes  501  and  502  and generates complementary input or sense signal pair IN and IN*. The IN and IN* signals feed input nodes  411  and  412  of level restore circuit  420 . 
     Circuit  410  includes a data path  421  coupled between nodes  401  and  411 , and a data path  422  coupled between nodes  402  and  412 . Data path  401  includes at least one transistor  431  coupled in series between input nodes  401  and  411  to propagate the IN signal to node  411  in response to a control signal CTL 1 . Data path  402  includes at least one transistor  432  coupled in series between input nodes  402  and  412  to pass the IN* signal to node  412  response to a control signal CTL 2 . 
     In some embodiments, circuit  410  includes a pass transistor logic circuit for performing logic functions such that the IN and IN* represent the results of the logic functions performed to the D IN  and D IN * signals. In some embodiments, the IN and IN* signals have a signal swing smaller than the signal swing of the D IN  and D IN * signals. 
     Level restore circuit  400  receives the IN and IN* signals and generates output signals OUT and OUT*. Level rest ore circuit  400  restores the signal levels of the IN and IN* signals such that the signal swing of the OUT and OUT* signals is greater than the signal swing of the IN and IN* signal to appropriately represent the full logic levels of logic one and logic zero. 
     Level restore circuit  420  includes embodiments of level restore circuit  100  of  FIG. 1  and level restore circuit  300  of  FIG. 3 . 
       FIG. 5  shows an embodiment of a system. System  500  includes at least one processing unit or processor  510 , memory device  520 , memory controller  530 , graphic controller  540 , input and output (I/O) controller  550 , display  552 , keyboard  554 , pointing device  556 , and peripheral device  558 . Bus  560  connects all of these devices together. Clock circuit  570  provides a clock signal to at least one of the devices of system  500 . In some embodiments, system  500  may omit one or more devices shown in  FIG. 5 . In some embodiments, two or more devices shown in system  500  may be formed on a single chip. 
     Bus  560  may be conducting traces on a circuit board or may be one or more cables. Bus  560  may also connect the devices of system  500  by wireless means such as electromagnetic radiation (e.g., radio waves). Bus  560  may further include at least one optical link connection to at least one of the devices shown in  FIG. 5  to provide a signal to an optical link transceiver of at least one of the devices through the optical link. Peripheral device  558  may be a printer, an optical device (e.g., a compact disc read only memory (CD-ROM) device or a digital video disc (DVD) device), a magnetic device (e.g., floppy disk driver), or an audio device (e.g., a microphone).  520  may comprise a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, or a combination thereof. 
     At least one of the devices shown in system  500  includes embodiments of  FIG. 1  through  FIG. 4 . Thus, at least one of the devices shown in system  500  includes embodiments of either a level restore circuit such as level restore circuits  100  and  300  or a combination of a logic circuit and a level restore circuit such as logic circuit  410  and level restore circuit  420 . 
     System  500  may take the form of computers (e.g., desktops, laptops, hand-helds, servers, Web appliances, routers, etc.), wireless communication devices (e.g., cellular phones, cordless phones, pagers, personal digital assistants, etc.), computer-related peripherals (e.g., printers, scanners, monitors, etc.), entertainment devices (e.g., televisions, radios, stereos, tape and compact disc players, video cassette recorders, camcorders, digital cameras, MP3 (Motion Picture Experts Group, Audio Layer 4) players, video games, watches, etc.), and the like. 
     Various embodiments of the present disclosure provides circuits and methods for reducing the effect of mismatches in transistors and offsets in reset voltages of level restore circuits so that the level restore circuits are more reliable in producing output signals with correct logic levels based on input signals with a relatively low signal swing. 
     Some embodiments of the present disclosure include a circuit having a first differential side and a second differential side for generating a differential output signal pair based on a differential input signal pair. The circuit also has capacitive network for capacitively coupling the first differential side to the second differential side to provide a capacitively-coupled positive feedback between the first and second differential sides. The circuit further has a reset network for resetting the first and second differential sides to reset voltages independent from each other. The circuit may be used to receive signals with a relatively low signal swing from output nodes of a logic circuit to generate output signals with full logic levels. 
     Other embodiments of the present disclosure include a method of restoring signal levels. The method performs a reset to reset a first differential input node and a first differential output node of a first differential side to a first reset voltage and to rest a second differential input node and a differential output of a second differential side to a second reset voltage independent from the first reset voltage. The first and second differential sides are capacitively-coupled to store an offset voltage generated during the reset. The method also generates a differential output signal pair at the first and second differential output nodes based on a differential input signal pair received at the first and second differential input nodes after the reset. 
     Some other embodiments of the present disclosure are also described above. Further embodiments will be apparent to persons skilled in the art upon reading and understanding the above detailed description and viewing the drawings that form a part thereof, each of which are not to be taken in a limiting sense. 
     Although specific embodiments have been illustrated and described herein, it should be appreciated that any arrangement calculated to achieve the same purpose may be substituted for the specific embodiments shown. The present disclosure is intended to cover any and all adaptations or variations of various embodiments. Combinations of the above embodiments, and other embodiments not specifically described herein, will be apparent to those of skill in the art upon reviewing the above description. The scope of the present disclosure is defined by the appended claims and their legal equivalents.