Patent Publication Number: US-9893160-B2

Title: Methods of forming gate dielectric material

Description:
PRIORITY CLAIM 
     The present application is a continuation of U.S. application Ser. No. 13/004,309, filed Jan. 11, 2011, which claims priority of U.S. Application No. 61/394,418, filed Oct. 19, 2010, which are incorporated by reference herein in their entireties. 
     RELATED APPLICATIONS 
     The present application is related to U.S. patent application Ser. No. 12/687,574, filed on Jan. 14, 2010, titled METHODS AND APPARATUS OF FLUORINE PASSIVATION; Ser. No. 12/789,681, filed on May 28, 2010, titled SCALING EOT BY ELIMINATING INTERFACIAL LAYERS FROM HIGH-K/METAL GATES OF MOS DEVICES; Ser. No. 12/707,788, filed on Feb. 18, 2010, titled MEMORY POWER GATING CIRCUIT AND METHODS; Ser. No. 12/892,254, filed Sep. 28, 2010, titled METHODS OF FORMING INTEGRATED CIRCUITS; Ser. No. 12/758,426, filed on Apr. 12, 2010, titled FINFETS AND METHODS FOR FORMING THE SAME; Ser. No. 12/731,325, filed on Mar. 25, 2010, titled ELECTRICAL FUSE AND RELATED APPLICATIONS; Ser. No. 12/724,556, filed on Mar. 16, 2010, titled ELECTRICAL ANTI-FUSE AND RELATED APPLICATIONS; Ser. No. 12/757,203, filed on Apr. 9, 2010, titled STI STRUCTURE AND METHOD OF FORMING BOTTOM VOID IN SAME; Ser. No. 12/797,839, filed on Jun. 10, 2010, titled FIN STRUCTURE FOR HIGH MOBILITY MULTIPLE-GATE TRANSISTOR; Ser. No. 12/831,842, filed on Jul. 7, 2010, titled METHOD FOR FORMING HIGH GERMANIUM CONCENTRATION SiGe STRESSOR; Ser. No. 12/761,686, filed on Apr. 16, 2010, titled FINFETS AND METHODS FOR FORMING THE SAME; Ser. No. 12/766,233, filed on Apr. 23, 2010, titled FIN FIELD EFFECT TRANSISTOR; Ser. No. 12/757,271, filed on Apr. 9, 2010, titled ACCUMULATION TYPE FINFET, CIRCUITS AND FABRICATION METHOD THEREOF; Ser. No. 12/694,846, filed on Jan. 27, 2010, titled INTEGRATED CIRCUITS AND METHODS FOR FORMING THE SAME; Ser. No. 12/638,958, filed on Dec. 14, 2009, titled METHOD OF CONTROLLING GATE THICKNESS IN FORMING FINFET DEVICES; Ser. No. 12/768,884, filed on Apr. 28, 2010, titled METHODS FOR DOPING FIN FIELD-EFFECT TRANSISTORS; Ser. No. 12/731,411, filed on Mar. 25, 2010, titled INTEGRATED CIRCUIT INCLUDING FINFETS AND METHODS FOR FORMING THE SAME; Ser. No. 12/775,006, filed on May 6, 2010, titled METHOD FOR FABRICATING A STRAINED STRUCTURE; Ser. No. 12/886,713, filed Sep. 21, 2010, titled METHOD OF FORMING INTEGRATED CIRCUITS; Ser. No. 12/941,509, filed Nov. 8, 2010, titled MECHANISMS FOR FORMING ULTRA SHALLOW JUNCTION; Ser. No. 12/900,626, filed Oct. 8, 2010, titled TRANSISTOR HAVING NOTCHED FIN STRUCTURE AND METHOD OF MAKING THE SAME; Ser. No. 12/903,712, filed Oct. 13, 2010, titled FINFET AND METHOD OF FABRICATING THE SAME; 61/412,846, filed Nov. 12, 2010, 61/394,418, filed Oct. 19, 2010, titled METHODS OF FORMING GATE DIELECTRIC MATERIAL and 61/405,858, filed Oct. 22, 2010, titled METHODS OF FORMING SEMICONDUCTOR DEVICES; which are incorporated herein by reference in their entireties 
    
    
     TECHNICAL FIELD 
     The present disclosure relates generally to the field of semiconductor devices, and more particularly, to methods of forming gate dielectric material. 
     BACKGROUND 
     The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed. 
     In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling-down also produces a relatively high power dissipation value, which may be addressed by using low power dissipation devices such as complementary metal-oxide-semiconductor (CMOS) devices. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The present disclosure is best understood from the following detailed description when read with the accompanying figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the numbers and dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. 
         FIG. 1  is a flowchart of an exemplary method of forming gate dielectric material. 
         FIGS. 2A-2H  are schematic cross-sectional views of an integrated circuit during various fabrication stages. 
         FIG. 3  is a schematic drawing illustrating an exemplary ozone-containing-gas treatment. 
         FIG. 4  is a schematic drawing illustrating a J g -V g  (gate leakage current density-gate voltage) relation. 
         FIG. 5  is a table showing capacitance effective thickness (CET), gate leakage current, and uniformities of samples A-D. 
     
    
    
     DETAILED DESCRIPTION 
     During the scaling trend, various materials have been implemented for the gate electrode and gate dielectric for CMOS devices. CMOS devices have typically been formed with a gate oxide and polysilicon gate electrode. There has been a desire to replace the gate oxide and polysilicon gate electrode with a high dielectric constant (high-k) gate dielectric and metal gate electrode to improve device performance as feature sizes continue to decrease. 
     Standard cleaning 1 (SC1) process has been proposed to clean an oxide interfacial layer before formation of a high dielectric constant (high-k) dielectric material. It is found that the SC1 process may damage and/or roughen the surface of the oxide interfacial layer. The damaged and/or roughened oxide interfacial layer may adversely affect the formation of the subsequent high-k dielectric material formed thereon. The damaged and/or roughened oxide interfacial layer may deteriorate the gate leakage current of the transistor formed on the substrate. 
     It is understood that the following descriptions provides many different embodiments, or examples, for implementing different features of the disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Moreover, the formation of a feature on, connected to, and/or coupled to another feature in the present disclosure that follows may include embodiments in which the features are formed in direct contact, and may also include embodiments in which additional features may be formed interposing the features, such that the features may not be in direct contact. In addition, spatially relative terms, for example, “lower,” “upper,” “horizontal,” “vertical,” “above,” “below,” “up,” “down,” “top,” “bottom,” etc. as well as derivatives thereof (e.g., “horizontally,” “downwardly,” “upwardly,” etc.) are used for ease of the present disclosure of one features relationship to another feature. The spatially relative terms are intended to cover different orientations of the device including the features. 
       FIG. 1  is a flowchart of an exemplary method of forming gate dielectric material.  FIGS. 2A-2H  are schematic cross-sectional views of an integrated circuit during various fabrication stages. The integrated circuit may include various passive and active microelectronic devices, such as resistors, capacitors, inductors, diodes, metal-oxide-semiconductor field effect transistors (MOSFETs), complementary MOS (CMOS) transistors, bipolar junction transistors (BJTs), laterally diffused MOS (LDMOS) transistors, high power MOS transistors, FinFET transistors, or other types of transistors. It is understood that  FIGS. 2A-2H  have been simplified for a better understanding of the concepts of the present disclosure. Accordingly, it should be noted that additional processes may be provided before, during, and after the method  100  of  FIG. 1 , and that some other processes may only be briefly described herein. 
     Referring now to  FIG. 1 , the method  100  can include forming a silicon oxide gate layer over a substrate (block  110 ). The method  100  can include treating the silicon oxide gate layer with an ozone-containing gas (block  120 ). After treating the silicon oxide gate layer, the method  100  can include forming a high dielectric constant (high-k) gate dielectric layer over the treated silicon oxide gate layer (block  130 ). In some embodiments, the method  100  can optionally include treating a surface of the substrate with an ozone-containing gas (block  140 ). In other embodiments, the method  100  can optionally include vapor cleaning the surface of the substrate (block  150 ). 
     Referring now to  FIGS. 2A-2H  in conjunction with  FIG. 1 , an integrated circuit  200  can be fabricated in accordance with the method  100  of  FIG. 1 . In  FIG. 2A , the integrated circuit  200  can have a substrate  201 . The substrate  201  can be a silicon substrate doped with a P-type dopant, such as boron (a P-type substrate). Alternatively, the substrate  201  could be another suitable semiconductor material. For example, the substrate  201  may be a silicon substrate that is doped with an N-type dopant, such as phosphorous or arsenic (an N-type substrate). The substrate  201  may alternatively be made of some other suitable elementary semiconductor, such as diamond or germanium; a suitable compound semiconductor, such as silicon carbide, silicon germanium, indium arsenide, or indium phosphide; or a suitable alloy semiconductor, such as silicon germanium carbide, gallium arsenic phosphide, or gallium indium phosphide. Further, the substrate  201  could include an epitaxial layer (epi layer), may be strained for performance enhancement, and may include a silicon-on-insulator (SOI) structure. 
     In some embodiments, shallow trench isolation (STI) features (not shown) may also be formed in the substrate  201 . The STI features can be formed by etching recesses (or trenches) in the substrate  201  and filling the recesses with a dielectric material. In some embodiments, the dielectric material of the STI features includes silicon oxide. In alternative embodiments, the dielectric material of the STI features may include silicon nitride, silicon oxynitride, fluoride-doped silicate (FSG), and/or any suitable low-k dielectric material. 
     Referring to  FIG. 1 , the method  100  can include forming a silicon oxide gate layer over a substrate (block  110 ). For example, a silicon oxide gate layer  210  can be formed over on the substrate  201  as shown in  FIG. 2A . In some embodiments, the silicon oxide gate layer  210  can be formed by a thermal process, e.g., a furnace process and/or a rapid oxidation process using an oxygen-containing precursor, e.g., oxygen (O 2 ) and/or ozone (O 3 ). For example, the silicon oxide gate layer  210  can be grown in an oxygen environment of about 700 degrees Celsius or more, and in another example of about 800 degrees Celsius or more. In other embodiments, the silicon oxide gate layer  210  can be formed by an enhanced in-situ steam generation (EISSG) process. In still other embodiments, the silicon oxide gate layer  210  can be formed by an atomic layer deposition (ALD) process. 
     In some embodiments, the silicon oxide gate layer  210  can have a thickness less than about 1 nanometer (nm), and in one embodiment, may be in a range from approximately 0.3 nm to approximately 1 nm. In other embodiments, the silicon oxide gate layer  210  can have a thickness more than about 1 nm. In some embodiments, the silicon oxide gate layer  210  can be referred to as a base layer. In other embodiments, the silicon oxide gate layer  210  can be referred to as an interfacial layer. 
     Referring to  FIG. 1 , the method  100  can include treating the silicon oxide gate layer with an ozone-containing gas (block  120 ). For example, the silicon oxide gate layer  210  can be treated with an ozone-containing gas  220  as shown in  FIG. 2B . In some embodiments, the ozone-containing gas  220  can comprise ozone (O 3 ) and at least one carrier gas, e.g., nitrogen (N 2 ), helium (He), and/or other suitable carrier gases. The ozone can have a weight percentage ranging from about 1.35% to about 15.5%. In some embodiments, treating the silicon oxide gate layer  210  can have a processing time ranging from about 5 seconds to about 80 seconds. In other embodiments, the processing time can range from about 10 seconds to about 30 seconds. 
     It is noted that treating the silicon oxide gate layer  210  can form a desired amount of hydroxyl (—OH) bonds on the surface of the silicon oxide gate layer  210 . The hydroxyl bonds can help the subsequent formation of a high-k gate dielectric layer. In some embodiments, treating the silicon oxide gate layer  210  can be performed as shown in  FIG. 3 . In  FIG. 3 , the substrate  201  can be disposed over a stage  310  within a chamber  300 . In some embodiments, treating the silicon oxide gate layer  210  can optionally include rotating the substrate  201 . 
     In some embodiments, treating the silicon oxide gate layer  210  can include spreading a de-ionized (DI) water layer  320  over the silicon oxide gate layer  210 . The ozone-containing gas  220  can diffuse through the water layer  320 , such that the ozone-containing gas  220  can reach and treat the surface of the silicon oxide gate layer  210 . Since the ozone-containing gas  220  diffuses through the water layer  320 , the ozone in the ozone-containing gas  220  can have a supersaturating concentration for treating the silicon oxide gate layer  210 . In some embodiments, treating the silicon oxide gate layer  210  may increase the thickness of the silicon oxide gate layer  210 . In other embodiments, the increased thickness of the silicon oxide gate layer  210  can be about 10 Å or less. 
     Referring again to  FIG. 1 , the method  100  can include forming a high dielectric constant (high-k) gate dielectric layer over the treated silicon oxide gate layer (block  130 ). For example, a high-k gate dielectric layer  215  can be formed over the treated silicon oxide gate layer  210 , as shown in  FIG. 2C . As noted, the hydroxyl groups on the surface of the treated silicon oxide gate layer  210  can help the formation of the high-k gate dielectric layer  215 . The quality of the high-k gate dielectric layer  215  can be desirably achieved. 
     In one example, the high-k gate dielectric layer  215  is formed by an atomic layer deposition (ALD) process and includes a high-k dielectric material. A high-k dielectric material is a material having a dielectric constant that is greater than a dielectric constant of SiO 2 , which is approximately 4. In an embodiment, the high-k gate dielectric layer  215  includes hafnium oxide (HfO 2 ), which has a dielectric constant that is in a range from approximately 18 to approximately 40. In alternative embodiments, the high-k gate dielectric layer  215  may include one of AlO, HfO, ZrO, ZrO 2 , ZrSiO, YO, Y 2 O 3 , LaO, La 2 O 5 , GdO, Gd 2 O 5 , TiO, TiO 2 , TiSiO, TaO, Ta 2 O 5 , TaSiO, HfErO, HfLaO, HfYO, HfGdO, HfAlO, HfZrO, HfTiO, HfTaO, HfSiO, SrTiO, ZrSiON, HfZrTiO, HfZrSiON, HfZrLaO, HfZrAlO, and so on. 
     Referring to  FIG. 2D , a process  235  can be optional to nitridize at least a portion of the silicon oxide gate layer  210  (shown in  FIG. 2B ) to form a silicon oxynitride layer (SiON) layer (not shown) between the high-k gate dielectric layer  215  and the silicon oxide gate layer  210 . In some embodiments, the SiON layer can be formed by a decoupled plasma nitridization (DPN) process and/or other suitable nitridization processes. 
     Referring now to  FIG. 2E , a gate electrode layer  250  can be formed over the high-k gate dielectric layer  215 . The gate electrode layer  250  may include silicon, polysilicon, and/or a metallic material, such as TiN, TaN, TaC, TaSiN, WN, TiAl, W, Al, Cu, or any combinations thereof. The metal gate electrode layer  250  may be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), or another suitable technique. 
     Referring to  FIG. 2F , the silicon oxide gate layer  210 , the high-k gate dielectric layer  215 , and the gate electrode layer  250  (shown in  FIG. 2E ) can be patterned by using a photolithography process and an etch process to form a gate stack structure  251  including a silicon oxide gate layer  210   a , a high-k gate dielectric layer  215   a , and a gate electrode layer  250   a . In some embodiments, the gate stack structure  251  can be formed in a gate-last process flow that can be referred to as a replacement gate process flow. 
     Referring to  FIG. 2G , after the gate structure  251  is patterned, lightly doped source/drain (also referred to as LDD) regions  260  may be formed in portions of the substrate  201  on each side of the gate structure  251 . The LDD regions  260  may be formed by an ion implantation process and/or a diffusion process. N-type dopants, such as phosphorus or arsenic, may be used to form an NMOS device, and P-type dopants, such as boron, may be used to form a PMOS device. 
     Referring to  FIG. 2H , gate spacers  265  can then be formed over the substrate and on each side of the gate stack structure  251  using a deposition process and an etching process (for example, an anisotropic etching process). The gate spacers  265  can include a suitable dielectric material, such as silicon nitride, silicon oxide, silicon carbide, silicon oxy-nitride, or combinations thereof. Thereafter, heavily doped source/drain (S/D) regions  270  can be formed in portions of the substrate  201  on each side of the gate spacers  265 . The S/D regions  270  can be formed by an ion implantation process and/or a diffusion process. N-type dopants, such as phosphorus or arsenic, can be used to form an NMOS device, and P-type dopants, such as boron, can be used to form a PMOS device. The S/D regions  270  can be aligned with the gate spacers  265 . 
     After forming the S/D regions  270 , an inter-layer (or inter-level) dielectric (ILD) layer (not shown) can be formed over the substrate  201  and the gate stack structure  251 . The ILD layer can be formed by chemical vapor deposition (CVD), high density plasma CVD, spin-on, sputtering, or other suitable methods. In some embodiments, the ILD layer can include silicon oxide, e.g., undoped silicate glass (USG), boron-doped silicate glass (BSG), phosphor-doped silicate glass (PSG), boron-phosphor-doped silicate glass (BPSG), or the like, silicon oxy-nitride, silicon nitride, a low-k material, or any combinations thereof. 
     Although not illustrated, one or more annealing processes are performed on the semiconductor device to activate the S/D regions  270 . These annealing processes can have relatively high temperatures (such as temperatures greater than approximately 700 degrees Celsius) and can be performed before or after a chemical-mechanical polish (CMP) process on the ILD layer. 
     Thus,  FIGS. 2A-2H  illustrate the various stages of a “gate first” process. Additional processes may be performed to complete the fabrication of the integrated circuit  200 , such as the forming of an interconnect structure and other backend structures. For the sake of simplicity, these processes are not illustrated herein. 
     As described above, it is understood that the gate electrode layer  250   a  may either be used in a “gate first” process, or the gate electrode layer  250   a  can be used as a dummy gate electrode in a “gate last” process. For example, if gate electrode  250   a  shown in  FIG. 2H  is formed of a polysilicon material, a CMP process could be performed on the ILD layer (not shown) to expose a top surface of the gate stack structure  251 . Following the CMP process, the top surface of the gate structure  251  is substantially co-planar with the top surface of the ILD layer on either side of the gate stack structure  251 . Afterwards, the gate electrode  250   a  can be removed, thereby forming a trench in place of the gate electrode  250   a . The gate electrode  250   a  may be removed in a wet etching or a dry etching process, while the other layers of the integrated circuit  200  remain substantially un-etched. Since the polysilicon gate electrode  250   a  is removed in the gate last process, it is also referred to as a “dummy gate”. Finally, a metallic structure can be formed within the trench and over the high-k gate dielectric layer  215   a . The metallic structure can include at least one of a metal diffusion layer, a metallic work function layer, a metallic conductive layer, other suitable semiconductor layers, or any combinations thereof. 
     It is understood that additional processes may be performed to complete the fabrication of the integrated circuit  200 . For example, these additional processes may include deposition of passivation layers, formation of contacts, and formation of interconnect structures (e.g., lines and vias, metal layers, and interlayer dielectric that provide electrical interconnection to the device including the formed metal gate). For the sake of simplicity, these additional processes are not described herein. 
     Referring again to  FIG. 1 , in some embodiments, the method  100  can optionally include treating a surface of the substrate with an ozone-containing gas (block  140 ). For example, before the formation of the silicon oxide gate layer  210  (shown in  FIG. 2A ), the surface of the substrate  201  is treated with an ozone-containing gas. 
     In some embodiments, the ozone-containing gas can comprise ozone (O 3 ) and at least one carrier gas, e.g., nitrogen (N 2 ), helium (He), and/or other suitable carrier gases. The ozone can have a weight percentage ranging from about 1.35% to about 15.5%. In some embodiments, treating the surface of the substrate  201  can have a processing time ranging from about 5 seconds to about 80 seconds. In other embodiments, the processing time can range from about 10 seconds to about 30 seconds. 
     In some embodiments, treating the surface of the substrate  201  can optionally include rotating the substrate  201 . In some embodiments, treating the surface of the substrate  201  can include spreading a de-ionized (DI) water layer over the substrate  201 . The ozone-containing gas can diffuse through the water layer, such that the ozone-containing gas can reach and treat the surface of the substrate  201 . It is noted that though showing the ozone-treatment in block  140 , the scope of the present application is not limited thereto. In some embodiments, the ozone treatment can be replaced by, for example, a standard RCA clean, a SPM clean, a standard cleaning 1 (SC1), and/or standard cleaning 2 (SC2) processes. 
     Referring again to  FIG. 1 , in some embodiments, the method  100  can optionally include vapor cleaning the surface of the substrate (block  150 ). For example, before the formation of the silicon oxide gate layer  210  (shown in  FIG. 2A ), the surface of the substrate  201  can be vapor cleaned. In some embodiments, the vapor cleaning can use a vapor phase fluorine-containing chemical to clean the surface of the substrate  201 . 
     In some embodiments, the vapor phase fluorine-containing chemical can include a passivation mixture including fluorine and an alcohol, such as isopropyl alcohol (IPA), methanol, or ammonia. For example, the passivation mixture may include a hydrous hydrofluoric acid vapor and an IPA vapor supplied by a carrier gas such as nitrogen. In some embodiments, the passivation mixture includes ranging from about 10 wt % to about 80 wt % of hydrous hydrofluoric acid vapor, for example including hydrofluoric acid at about 49 wt %. In other embodiments, the passivation mixture includes hydrofluoric acid vapor and IPA vapor at a weight ratio ranging from around 0.5/1 to around 10/1, for example around 3/1. In still other embodiments, the passivation mixture may include hydrofluoric acid and an alcohol in a vapor phase form of HF and IPA. In yet still other embodiments, the passivation mixture may include hydrofluoric acid and ammonia (NH 3 ). Other carrier gases which are substantially non-reactive with silicon, such as argon, may be suitable. 
     In some embodiments, the vapor cleaning may occur at between ambient temperature and about 100 degrees Celsius and between atmospheric pressure and about 300 torr, and does not include high temperature implantation, annealing, UV light, or plasma processing, thereby avoiding interface defects that may occur from those processes. In other embodiments, the vapor cleaning may occur at between room temperature and about 100 degrees Celsius and between 1 mtorr and about 10 torr, and then with a baking process from about 50 to about 200 degrees. As noted, the blocks  140  and  150  shown in  FIG. 1  are merely optional and exemplary. In some embodiments, the order of the blocks  140  and  150  can be switched. 
       FIG. 4  is a schematic drawing illustrating a J g -V g  (gate leakage current density-gate voltage) relation. In  FIG. 4 , sample A was prepared by an SC1 process between the formations of the silicon oxide gate layer and the high-k gate dielectric layer. Samples B-D were prepared by the method  100  described above in conjunction with  FIG. 1  with different ozone-containing-gas treating time of about 10, 20, and 30 seconds, respectively. It was found that the gate leakage currents of the samples B-D are substantially and unexpectedly lower than that of the sample A as shown in  FIG. 4 . 
       FIG. 5  is a table showing capacitance effective thickness (CET), gate leakage current, and uniformities of samples A-D. As shown in  FIG. 5 , CETs and uniformities of CETs of the samples B-D are substantially similar to those of the sample A. The gate leakage currents of the samples B-D are unexpectedly and substantially reduced by 50.93%, 61.73%, and 63.88%, respectively, compared to that of the sample A. Additionally, the uniformities of the gate leakage currents of the samples B-D are improved compared with that of the sample A. 
     One aspect of this description relates to a method of fabricating a semiconductor device. The method includes contacting water with a silicon oxide layer. The method further includes diffusing an ozone-containing gas through water to treat the silicon oxide layer. The method further includes forming a dielectric layer over the treated silicon oxide layer. 
     Another aspect of this description relates to a method of fabricating a semiconductor device. The method includes contacting water with a silicon oxide layer. The method further includes diffusing an ozone-containing gas through water to treat the silicon oxide layer. The method further includes forming a dielectric layer over the treated silicon oxide layer, and nitridizing at least a portion of the silicon oxide layer to form a silicon oxynitride layer. 
     The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.