Patent Publication Number: US-9411912-B1

Title: Clock topology planning for reduced power consumption

Description:
CROSS REFERENCE 
     This non-provisional United States (U.S.) patent application claims the benefit of U.S. Provisional Patent Application No. 61/732,284 filed on Nov. 30, 2012 by inventors Ankush Sood, et al., entitled GRAPHICAL USER INTERFACE FOR PHYSICALLY AWARE CLOCK TREE PLANNING, incorporated herein by reference. 
    
    
     This application is also related to U.S. patent application Ser. No. 13/732,364 filed on Dec. 31, 2012 by inventors Tsuwei Ku, et al., entitled PHYSICALLY AWARE LOGIC SYNTHESIS OF INTEGRATED CIRCUIT DESIGNS, incorporated herein by reference. 
     FIELD 
     The embodiments of the invention relate generally to clock tree topology planning for designing integrated circuits. 
     BACKGROUND 
     Digital circuits within integrated circuit chips are often synchronized by one or more clock signals. Data is periodically stored in registers that are clocked by such clock signals. When data is not being evaluated, it is desirable to control or gate the clocks to unused circuitry in order to conserver power. Clock tree synthesis is thus important in assuring that data is captured when needed and that power is conserved when desired. 
     Traditional logic synthesis of register-transfer-logic (RTL) into Boolean logic gates provides little to no visibility into the consequences of logic implementation choices on clock synthesis. Clock synthesis is often considered at the end of the design even though decisions made in the front-end design flow of an integrated circuit may have significant consequences on the subsequent timing and power closure of the clock design and its clock tree. 
     Traditionally, clock signals are treated as ideal networks during logic synthesis and logic optimization. Physical information (e.g., driver size/strength, net widths, net lengths), buffering information (e.g., clock buffers, clock gating), or timing information (e.g., delay) is usually not estimated, or if estimated, not utilized during logic synthesis of other networks. It is usually during the back-end of the physical design of the overall integrated circuit design that clock synthesis occurs and any implementation details of the clock signals are explored. 
     For low power integrated circuit designs, estimating the costs of timing and power during automatic clock gate insertion is imprecise with such late clock synthesis. In lieu of reliable data, front-end designers typically focus on the gated flip-flop percentage. However, with the availability of advanced functional gating techniques, overly aggressive gating is an increasingly common result. Another negative consequence of clock synthesis occurring late in the design flow is the greater difficulty of grouping and cloning clock signals, such that it does not correspond to the physical netlist. With fewer clock signals grouped together, clock switching power may be greater. With clock synthesis occurring later in the design flow, it may be more difficult to obtain timing closure of the integrated circuit design during clock tree synthesis. 
     It is desirable to provide tools to the integrated circuit designer that are used earlier in the integrated circuit design flow to improve the synthesis of clock signal networks within an integrated circuit design. 
     BRIEF SUMMARY 
     The embodiments of the invention are best summarized by the claims that follow below. In brief, the embodiments of the invention include a method, apparatus and system for physically aware clock topology planning. 
     One aspect of physically aware clock topology planning is that some work may be performed pre-placement in the front end while other work to complete the clock tree plan is performed post placement. In the front end, a clock tree prototype may be developed from the netlist. The clock tree prototype is a Boolean representation of the clock tree that is oriented hierarchically. With a hierarchical representation, the position of clock buffers with respect to clock gates can be readily modeled. For example, a count of the number of clock buffers that precede a clock gate in a given clock path and the number that follow the clock gate and are shielded thereby (keeps them from being clocked) to save power can be made to evaluate power consumption in a clock subtree. 
     After the clock buffers, enable gates, clock gates, and clocked elements are placed within a floor plan, the clock tree plan does not need to follow the clock tree prototype and can be altered to optimize the physical placement of the clock buffers, enable gates, clock gates, and clocked elements to improve timing and power consumption. After placement in a floorplan, clocked elements in the clock tree plan can be optimized such as by merging clock subtrees at merger points or cloning clock gates for insertion into branches of a clock subtree. 
     After the planning, a subsequent clock tree synthesis can be performed in the back end to better select clock buffers in the clock tree to meet timing requirements and reduce power consumption. If timing is an issue, a merged clock subtree may be re-split post placement. 
     Another aspect of the embodiments of the invention is to achieve better timing. The enable signal logic for a clock gate may be synchronized to the clock signal logic to achieve more balanced timing in the generation of a gated clock signal. Enable logic must be in sync with the clock logic. 
     Another aspect of the embodiments of the invention is that physical placement is considered during the clock tree planning process. Another aspect of the embodiments of the invention is cluster placement of clocked elements in portions of the integrated circuit design. Cloning of clock gates or clock buffers, one or more times, may be used to improve timing and/or power consumption in one or more branches of clock signal paths within a clock subtree that lead to the clusters of clocked elements. The placement of buffers and clock gates in the clock tree is evaluated to optimize power and balance timing. 
     Another aspect of the embodiments of the invention is a merger algorithm that is used to evaluate merging of clock trees, clock gates, and clocked elements in the formation of an optimized clock tree plan. The merger algorithm is a bottom up recursive binary merging algorithm. A partial tree model of clock subtrees (a gate model, timing model, energy/power model) may be created to determine whether or not to merge. The partial tree models are recursively built as you move up the hierarchy towards the clock source at a clock generator. At every stage of hierarchy, a history of the lower level clock subtrees and clocked elements is maintained. The goal of the merger algorithm is to conserver maximum power while meeting timing requirements. To do so, the merger algorithm evaluates cost functions of potential mergers of clock subtrees. It evaluates power consumption/conservation, enable timing, signal skew, and data timing delay of the potential mergers of clock subtrees. With a merger, redundancy is avoided to reduce power consumption. Clock signal skew is balanced to avoid race conditions. Clock signal timing is balanced with data signal timing at a flip flop to assure capture of data while gating clock signals to conserver power. 
    
    
     
       BRIEF DESCRIPTIONS OF THE DRAWINGS 
       Various embodiments of the present invention taught herein are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings, in which: 
         FIG. 1A  illustrates placement of a clock generator or clock source and functional blocks (FB) in an integrated circuit. 
         FIG. 1B  illustrates global routing of a clock tree from a clock source to the respective functional blocks by interconnect wiring. 
         FIG. 1C  illustrates a functional block diagram of an idealized clock subtree into a functional block. 
         FIG. 1D  illustrates a functional block diagram of a non-idealized clock subtree into a functional block. 
         FIG. 1E  illustrates a functional block diagram of an exemplary clock tree from clock generator to clocked elements at lower levels of clock tree hierarchy. 
         FIG. 2  is an exemplary flow diagram of physical clock topology planning. 
         FIGS. 3A-3B  are exemplary clock subtree circuits to illustrate optimization by clock gate cloning. 
         FIGS. 4A-4B  are exemplary clock subtree circuits to illustrate optimization by elimination of clock gating and use of data recirculation in the date path. 
         FIGS. 5A-5B  are exemplary clock subtree circuits to illustrate optimization by clock buffer cloning. 
         FIGS. 5C-5D  are exemplary clock subtree circuits to illustrate optimization by rearranging clocked elements within clock gate clusters that have their clock signals gated by a clock gate. 
         FIGS. 6A-6B  are exemplary clock subtree circuits to illustrate timing balancing by insertion of clock buffers to compensate for asymmetric clock signal paths. 
         FIGS. 7A-7D  are functional block diagrams to illustrate balancing of time delays and the physical placement of clock buffers, enable gates, and the clock sinks or clocked elements. 
         FIGS. 8A-8B  are functional block diagrams to introduce the set of feasible disable signals for a clocked element, such as a flip flop or clock subtree. 
         FIGS. 8C-8D  are functional block diagrams to introduce how sets of feasible disable signals may be used to implement clock gating in a clock subtree. 
         FIG. 9A  is a functional block diagram of a clock tree planner-synthesizer that performs the functions of the physical clock topology planning described herein. 
         FIG. 9B  is a functional block diagram of the functional analyzer and the functional analysis engines therein for the clock tree planner-synthesizer shown in  FIG. 9A . 
         FIG. 9C  is a state diagram for the priority queue of the clock tree planner-synthesizer shown in  FIG. 9A . 
         FIGS. 10A-10B  are charts of exemplary timing models that may be used by the timing analyzer and optimizer to evaluate merger partners for the clocked elements. 
         FIG. 11A  is a chart of an exemplary switching energy model that may be used by the power analyzer and optimizer to evaluate merger partners for the clocked elements. 
         FIG. 11B  is a chart of an exemplary non switching power model that may be used by the power analyzer and optimizer to evaluate merger partners for the clocked elements. 
         FIG. 12  is a simplified schematic diagram of a wire routed between an input terminal of a clock subtree and the clock terminal of a clocked element over which a clock signal may propagate to explain how physical wire is considered in the timing and power models for a clock subtree. 
         FIG. 13  is a functional block diagram of a potential merger at a merge point between clock subtrees with respective feasible disables to evaluate costs of the potential merger and determine if the potential merger should be implemented. 
         FIG. 14A  is a functional block diagram of an exemplary potential merger at a merge point between clocked elements (e.g., flip-flops) to evaluate costs of the potential merger. 
         FIG. 14B  is a chart of timing delay to evaluate total timing delay costs of the exemplary potential merger at the merge point between clocked elements of  FIG. 14A . 
         FIG. 14C  is a chart of switching energy consumption to evaluate the total switching energy consumption costs of the exemplary potential merger at the merge point between clocked elements of  FIG. 14A . 
         FIG. 14D  is a chart of non-switching power consumption to evaluate the total non-switching power consumption costs of the exemplary potential merger at the merge point between clocked elements of  FIG. 14A . 
         FIG. 15  is a functional block diagram of a clock buffer being inserted into the ungated clock signal path to evaluate the costs of insertion of a clock buffer above a clock subtree. 
         FIG. 16A  is a timing diagram illustrating exemplary simulation vectors for feasible disable signals. 
         FIG. 16B  is a timing diagram illustrating an exemplary clock actively vector for a gated clock signal. 
         FIG. 16C  is a timing diagram illustrating an exemplary clock actively vector for an ungated clock signal. 
         FIG. 17  is a functional block diagram of a clock subtree with clock gates generating gated clock signals in response to the simulation vectors of feasible disable signals to determine the clock activity vectors for the gated clock signals. 
         FIGS. 18A-18E  are diagrams illustrating various states of one priority queue of the clock tree planner from being initially unsorted to sorted near completion of a portion of a clock tree network. 
         FIG. 19  is an exemplary floor plan of an integrated circuit design to illustrate the selection of potential nearest merger partners to a given clock subtree or clocked element. 
         FIG. 20  is a functional block diagram of an exemplary potential merger of clock subtrees at a merge point to evaluate costs of the potential merger without use of a clock gate. 
         FIG. 21  is a functional block diagram of an exemplary potential merger of clock subtrees at a merge point to evaluate timing and costs of the potential merger with the use of one or more clock gates. 
         FIG. 22  is a diagram illustrating the process of repeated merger evaluation and implementation using the queue of the clock tree planner through completion of clock subtree mergers. 
         FIGS. 23A-23B  are functional block diagrams to evaluate costs of an exemplary potential merger between a clock subtree and a clocked element at a merge point. 
         FIGS. 24A-24C  are functional block diagrams to evaluate costs of exemplary potential mergers between clock subtrees with and without clock gating in response to respective feasible disable signals. 
         FIG. 25  is an exemplary floor plan of an integrated circuit design to evaluate varying distances between exemplary potential merger partners of a given clock subtree. 
         FIGS. 26A-26C  are functional block diagrams to evaluate costs of potential mergers of clock subtrees with varying distances between merger partners such as shown in  FIG. 25 . 
         FIG. 27  is a timing diagram illustrating exemplary simulation vectors for feasible disable signals across potential clock merger partners to perform a bit wise compare and analyze feasibility of implementing clock gates and whether power is conserved in response to the simulation vectors. 
         FIG. 28  is a functional block diagram to evaluate costs of a potential merger of clock subtrees using the exemplary simulation vectors for the feasible disable signals shown in  FIG. 27 . 
         FIG. 29  is an exemplary floor plan of an integrated circuit design with physical placement of clock gates with respect to the clocked elements and clock generator in the clock tree that may be generated by the physical clock topology planner. 
         FIGS. 30A-30B  are diagrams of a computer system with a processor that executes instructions to provide physical clock tree planning that may be used to design integrated circuits. 
         FIG. 31  is a flow chart diagram depicting an exemplary process associated with the physical clock tree planning of a clock tree network within an integrated circuit design. 
         FIGS. 32A-32B  are diagrams illustrating one or more priority queues to list clocked elements and clock subtrees having common enable/disable signals that may be used within an integrated circuit design to gate clock signals to the listed elements. 
     
    
    
     It will be recognized that some or all of the Figures are for purposes of illustration and do not necessarily depict the actual relative sizes or locations of the elements shown. The Figures are provided for the purpose of illustrating one or more embodiments of the invention with the explicit understanding that they will not be used to limit the scope or the meaning of the claims. 
     DETAILED DESCRIPTION 
     In the following detailed description of the embodiments of the invention, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be obvious to one skilled in the art that the embodiments of the invention may be practiced without these specific details. In other instances well known methods, procedures, components, and circuits have not been described in detail so as not to unnecessarily obscure aspects of the embodiments of the invention. 
     Note also that the terms flip-flop and register are being used interchangeably herein. That is, each reference to a flip-flop herein also means a register of a plurality of flip-flops that are clocked together by the same clock signal. In a register, each flip flop typically has a data input coupled to a respective data signal to store data bits from a bus of parallel data signals. Accordingly, a reference to a flip-flop herein also means a register of a plurality of flip flops. A reference to one or more flip flops herein also means one or more registers. A reference to a plurality of flip flops herein also means a plurality of registers. A reference to a flip-flop cluster, a set of one or more independent flip-flops each being clocked by the same clock signal, also means a register cluster, a set of one or more independent registers each being clocked by the same clock signal. Conversely, a reference to a register herein also means a single flip-flop. 
     The terms enable signal and disable signal may also be used interchangeably herein in reference to the generation of gated clock signals. A gated clock signal is actively switching when it is enabled and is inactive when it is disabled from switching. Thus, a disable signal is the logical inverse of an enable signal and it is well known how to generate one from the other. Thus, the terms disable signal and enable signal may be used interchangeably herein when searching for signals that can be used to gate a clock signal at a clock gate. 
     Introduction 
     The embodiments of the invention include a method, apparatus and system for physically aware clock topology planning Clock topology planning (also referred to as clock tree planning) can be performed earlier with early physical information that is available from logic synthesis tools such that it can be performed in a physically aware manner and consider design trade-offs. With clock topology planning, the clock distribution network of clock signals is no longer viewed as a substantially idealized network. 
     Clock topology planning (CTP) determines placement of clock gates with respect to the flip flop placement (or register placement of a plurality of flip-flops) and what signals are used to generate enable signals to gate the clock gates that generate gated clock signals that clock the flip flops. One of the more significant goals of clock topology planning is to minimize power consumption by optimizing the generation of clock signals in the design integrated circuit. CTP uses an algorithm with models to provide estimates of power and timing at the front end of the design flow in order to optimize each and reduce power consumption while meeting timing requirements in the plan. The result of the CTP is the placement of key clock circuits (e.g., enable gates and clock gates) with respect to the registers and flip-flops of each functional block. While buffering clock signals to avoid timing skew and routing of the clock signals is important, the implementation is performed by clock tree synthesis after the clock topology plan is found to be acceptable. Buffers and routing that may be added to finalize the clock topology plan may be removed there-from. 
     Referring now to background  FIG. 1A , previously placement of functional blocks (FB)  104 A- 104 I in an integrated circuit  100  was performed prior to clock topology placement and routing as illustrated. Interconnect wire  108  of the data paths and control paths is routed between the functional blocks before there is any plan for a clock signal distribution network or clock network. Within the functional blocks, all the flip flops and registers in the circuit are placed. However, the clock distribution network from a clock source or clock generator  102  has yet to be planned, synthesized, placed and routed. A timing analysis may be performed on the data paths and control paths to determine the timing slack at the data inputs of the registers and flip flops within the blocks. Without any plan or synthesis of the clock network, a timing analysis of the clock network is not performed and it is assumed to be ideal clock distribution network. 
     Referring now to background  FIG. 1B , after the functional blocks have been synthesized, placed and routed, an idealized clock distribution network may be synthesized that distributes the clock signals to all the registers in the circuit (whose positions and timing data are already known). The clock tree is routed from a clock source  102  to the respective functional blocks  104 A- 104 I by ideal interconnect wiring  110 . However, the idealized clock distribution network that is initially placed and routed ignores clock timing issues of the clock distribution network. In an ideal circuit, the clock source  102  and the clock signal coupled into each register experience no timing delay. Any timing analysis performed with the idealized clock distribution network is not going to accurately depict the resultant real or non-ideal clock distribution network. In the backend of the design, the initial idealized clock distribution network is ripped up and the real clock distribution network is re-synthesized, placed, and routed. With the functional blocks  104 A- 104 I in their optimized placement with optimized routing, the synthesis of the clock distribution network is an afterthought where some sub-optimal decisions with respect to the clock network may be made. 
     Referring now to  FIG. 1C , an exemplary idealized clock distribution network in the functional block  104 I coupled to an idealized clock generator  102 I is illustrated. The ideal clock generator  102 I generates an ideal ungated clock signal  101 I that is coupled into the ideal functional block  104 I. Within the functional block  104 I, the clock signal  101 I is gated by a clock gate  112 I to generate an ideal gated clock signal  103 I in response to an enable signal  130 I. The ideal gated clock signal  103 I is coupled into the clock inputs (also referred to as a clock sink) of registers  114 A- 114 N comprising one or more D flip flops. 
     The enable signal  130 I is generated by enable logic  118 I that includes at least one enable gate  128 I. The enable signal is not generated by the clock circuitry. Thus, the enable signal does have timing delay associated with it in the front-end design flow when the clock network is treated to be ideal. The enable signal has a setup check with the ideal clock. With the enable timing delay, the slack of the enable signal at the clock gate  112 I is not always zero. The delay from the clock gate output to the FF clock input pin is zero in the ideal circuit  104 I. The delay from the clock gate output to the FF clock input pin is not traditionally accounted for in the front-end. Thus, the timing of the enable signal, despite the enable setup check, is not accurate in the front-end with the ideal circuit  104 I. In the embodiments of the invention, clock topology planning estimates the delay from the CG output pin to the clock input pin of the flip flop. This estimated delay is added to the setup requirements of the enable pin so that a clock signal is assured to arrive at the clock input pin of the flip flop within a clock period. Note that the delay from the ideal clock generator  102 I to the FF (e.g. flip flop  114 B) is still zero timing delay in the ideal circuit  104 I. 
     In an ideal clock tree network, there is little to no information as to how the clock tree network will be physically laid out into an integrated circuit design to provide clock signals to the clocked elements so they are clocked to store data. There is little to no information of where clocked elements such as flip flops are placed. There is little to no information as to how the clock signal paths are routed to the clock inputs of the clocked elements. 
     With an idealized clock tree network with idealized clock timing, a lack of transparency into the physical clock design can lead to poor implementations of clock gating. With an ideal circuit, the mapping of circuitry for the enable logic  118 I is dictated by timing criticality that can effect of power consumption and circuit area that typically are not considered. Furthermore, because physical placement is not accounted for, the clock enable timing endpoint is traditionally fixed relative to the ideal clock signal  101 I. Thus, the effects of long clock wires may not be considered. 
     In reality, timing delays and signal skew are introduced into the gated clock signal before it reaches the clock input to a clocked element such as a flip flop or register. The timing delays and signal skew of a clock signal may be from a number of factors. 
     Referring now to  FIG. 1D , instead of an idealized clock circuit, an exemplary real or non-idealized clock circuit is shown. A real or non-ideal clock generator  102 R has a real or non-ideal ungated clock signal  101 R coupled into a real or non-ideal functional block  104 R. Initial timing delay from the ideal clock signal may be from one or more external clock buffers  120  that introduce some timing skew into the non-ideal ungated clock signal  101 R at the clock input of the clock gate  112 R. 
     Within the functional block  104 R, an exemplary clock subtree is shown including real or non-ideal enable logic  118 R, a real or non-ideal clock gate  112 R, a plurality of real or non-ideal clock buffers  122 A- 122 G, and a plurality of clock sinks in the clock signal paths. The clock sinks are the clock inputs of the sets of the plurality of flip-flops or registers  114 A- 114 N. The clock gate  112 R may be an AND gate, NAND gate, OR gate, NOR gate, or multiplexer with one input coupled to a clock signal and the other coupled to a steady state logic one or logic zero. The clock gate may also be a part of a clock gating type of integrated cell from a standard cell library or a combination of a latch and standard cell gates. 
     In the enable signal path  150 , the circuit  104 R includes enable logic  118 R including the enable gate  128 R. The source of the enable signal may be generated by the flip flop  154 . The enable signal path  150  has an enable path delay EP for which timing delay may vary depending upon the worst case parameters (EP max ) or best case parameters (EP min ). The flip flop  154  may be clocked by an ungated clock signal generated by the clock generator  102 R that has been buffered by one or more clock buffers  121 A- 121 N. This clock signal path forms a launch enable path  152  with a launch timing delay L for the enable signal. The clock signal path from the generator  102 R to the clock input of the clock gate  112 R, forms a capture enable path  153  with a capture timing delay C. With the clock period T and the timing values EP, L, and C; setup and hold constraints for the enable signal  130 R at the clock gate  112 R can be formulated.
 
Enable Setup Constraint:  L+EP   max   &lt;T+C  
 
Enable Hold Constraint:  L+EP   min   &gt;C.  
 
For setup, the sum of the launch timing delay L along the launch path  152  and the maximum of the enable path delay EPmax along the signal path  150  should be less than the sum of the clock period T and capture timing delay C along the capture path  153 . Rearranging the setup equation, we can formulate an equation for Setup slack at the clock gate  112 R as follows:
 
Enable Setup Slack:  L+EP   max   −T−C =Setup slack
 
     If the enable setup slack is positive, there is margin in the enable signal arrival time at the enable input terminal to the clock gate. When there is positive slack in the enable signal path at a clock gate, buffers and clock-gates can be inserted below it in lower levels of clock tree hierarchy. If the enable setup slack is negative, the clock gate  112 R will not properly function to generate the gated clock signal  103 R. Negative slack indicates that the enable signal cannot arrive on time and that there is less time than required in the enable path. In which case, enable signal path needs to modified or the clock gate removed. 
     With positive enable setup slack, the timing amount (e.g., +100 ps) may be used to determine whether or not to merge clock subtrees below the clock gate  112 R. One may assume that the clock gate  112 R is enabled in advance by this amount so that it can be used for additional timing delay below the clock gate in the clock path. Additional clock gates or clock buffers may be inserted up to this amount, but not over. If a potential merger adds more delay in the clock path than this amount, it should be discarded. If no further potential merger falls within the slack timing value, they all exceed it, no further mergers should occur below the given clock gate  112 R. At the point where no more subtrees can be merged, the clock gate for the given subtree needs to be inserted, as long as the insertion of the clock gate saves power. If insertion of the clock gate does not conserver power, it is not inserted. 
     Initial timing delay from the ideal clock signal may be from one or more external clock buffers  120  that introduce some timing skew into the non-ideal ungated clock signal  101 R. Within the functional block  104 R, the clock signal  101 R is gated by a real or non-ideal clock gate  112 R to generate a non ideal gated clock signal  103 R in response to a real or non-ideal enable signal  130 R. 
     Before being coupled into the clock input terminals of one or more registers or D flip-flops  114 A- 114 N, the real or non-ideal gated clock signal  103 R may be split up and buffered by one or more clock buffers  122 A- 122 G to form the buffered gated clock signals  131 R- 133 R. The buffered clock signals  131 R- 133 R may be skewed from each other by timing differences in the one or more clock buffers  122 A- 122 G. 
     Timing setup of the enable signal  130 R at the enable input of the clock gate  112 R is relative to the arrival of the non-ideal ungated clock signal  101 R at the clock gate  112 R. The real or non-ideal enable signal  130 R is generated by real or non-ideal enable logic  118 R comprising of at least one real or non-ideal enable gate  128 R. 
     The gated clock signals  131 R- 133 R coupled into the clock inputs of the registers experience timing delay from various sources. As mentioned herein, one such source of delay may be from one or more external clock buffers  120  that introduce some timing skew. Various launch and capture clock paths may be formed for data that is coupled between clocked elements of a clock subtree. 
     For example, in  FIG. 1D , flip flops  114 A- 114 B may be coupled together such that a data path  160  forms between Q output of the flip flop  114 A and D input of flip flop  114 B. A launch clock path  162  is formed from the clock gate  112 R to the clock input of the flip flop  114 A with a launch timing L. A capture clock path  163  is formed from the clock gate  112 R to the clock input of the flip flop  114 B with a capture timing C. Along the data path  160 , there is a data path delay DP for which timing delay may vary depending upon the worst case parameters (DP max ) or best case parameters (DP min ). The difference between the launch clock path  162  and the capture clock path  163  is minimal so there would be a minimal amount of timing skew between each expected. 
     However as another example, consider the flip flops  114 N and  114 A being coupled together such that a data path  170  forms between Q output of the flip flop  114 N and D input of flip flop  114 A. A launch clock path  172  is formed from the clock gate  112 R to the clock input of the flip flop  114 N with a launch timing L. A capture clock path  173  is formed from the clock gate  112 R to the clock input of the flip flop  114 A with a capture timing C. Along the data path  170 , there is a data path delay DP for which timing delay may vary depending upon the worst case parameters (DP max ) or best case parameters (DP min ). The difference between the launch clock path  172  and the capture clock path  173  is more substantial so that so there could be some timing skew between each if the clock signal paths are not balanced. The embodiments of the invention, try to balance out clock paths at each merger point down to all the clocked elements (balance out insertion delay d) below it so as to try and minimize such timing skew across all clocked elements at a given level. 
     With the clock period T and the timing values DP, L, and C; a setup constraint for data signals on the data paths  160 , 170  at the input to the flip flops  114 B, 114 A can be formulated as follows:
 
Data Setup Constraint:  L+DP   max   &lt;T+C  
 
     For setup, the sum of the launch timing delay L along the launch path  162 , 172  and the maximum of the data path delay DPmax along the data signal path  160 , 170  should be less than the sum of the clock period T and capture timing delay C along the capture path  163 , 173 . Rearranging the setup equation, we can formulate an equation for setup slack at the flip flop as follows:
 
Data Slack:  L+DP   max   −T−C =slack
 
     Note that the difference between L and C of the launch and clock paths is a function of timing balance in the clock subtree. If equal, they difference is zero and then the slack is a function of DP max −T. Timing balance in the clock subtree can be accomplished by appropriate physical placement of the clock gates, enable gates, clock buffers, clocked elements as well as the insertion of clock buffers. 
     Note that if there is slack timing available at the enable input to the clock gate  112 R, (e.g., +300 ps), then additional buffers and clock gates can be inserted into the clock signal path up to that timing amount between the clock gate  112 R and the flip flops  114 A- 114 N or other lower level clocked elements. Insertion of additional clock buffers and clock gates may reduce power consumption, which is desirable. Buffers can conserver power if signal slew of a clock signal is improved in a clock path. Clock gates can conserve power by reducing the frequency of switching in clocked circuits in lower levels of the clock tree hierarchy. 
     Locally within each functional block, timing skew and/or delay in the clock signal may be introduced by the generation of the real or non-ideal enable signal  130 R. The enable logic  118 R, such as the enable gate  128 R, introduces delay and/or timing skew into the real or non-ideal gated clock signal  130 R. Timing setup of the enable signal  130 R at the enable input of the clock gate  112 R is relative to the arrival of the non-ideal ungated clock signal  101 R at the clock gate  112 R. It is desirable that the slack of enable signals at the input to a clock gate is greater than zero. If so, this positive slack time can be utilized as much as possible to push clock buffers down the clock tree hierarchy to a lower level below the given clock gate 
     The enable signal  130 R may have skew as may the non-ideal clock signal  101 R. The real or non-ideal clock gate  112 R has some timing delay associated with it before a gated clock output signal is generated. These are local sources of timing delay and skew that may be added to the non-ideal gated clock signal  130 R generated by a clock gate. 
     Furthermore, the capacitive load of the clock inputs of the registers may be too much for the clock gate to drive the non-ideal gated clock signal  130 R into them. The capacitive load may be split up and buffered by one or more clock buffers  122 A- 122 G. Locally, the one or more clock buffers  122 A- 122 G may be another source of timing delay and timing skew in the clock signals  131 R- 133 R before the registers  114 A- 114 N are clocked thereby. 
     The clock buffers  122 A- 122 G when inserted to buffer the clock signal add an insertion delay to the clock signal  131 R- 133 R that clock the registers. Relative to the clock period of the clock clocking the registers  114 A- 114 N, the insertion delay may have a large variance depending upon the clock topology and the fanout of the clock subtree. 
     Corrections to improve performance of a clock subtree may be made by various means such as by removing gates in the enable and/or clock paths, cloning gates to reduce loads, remapping the enable logic and insertion of clock gates, insertion of clock buffers, and sizing of clock gates and clock buffers. 
     It is desirable to plan and synthesize the clock tree network to take into account the reality of a non-ideal clock network that extends into the one or more functional blocks of an integrated circuit design. 
     Referring now to  FIG. 1E , an exemplary clock tree circuit  180  with some complexity is illustrated. The clock tree circuit  180  includes a clock generator  102 R, clock gates  112 A- 112 H, and clocked elements including flip-flops  114 A- 114 C, flip-flop clusters  106 A- 106 F, latch  115 , and register  116 , coupled together as shown. The clock tree circuit  180  has multiple levels (e.g., seven levels) of clock tree hierarchy from the clock generator  102 R at the top level to the flip flop cluster  106 F and its clocked flip flops at the lowest level. Embodiments of the invention operate bottoms up on clock trees such as that illustrated in  FIG. 1E , from the lowest level of clock tree hierarchy (e.g., flip flops in the flip flop cluster  106 F) up to the clock source (e.g., the clock generator  102 R). 
     The clock tree circuit  180  includes multiple levels of clock gates in the clock tree hierarchy. For example, flip flop cluster has four levels of clock gates between the output terminal of the clock generator  102 R and the clock inputs or clock sinks of the flip flops in the flip flop cluster  106 F. Moreover the output of clock gate  112 D is an enable input to clock gate  112 E that further complicates timing matters in the clock tree circuit. The worst case delay from the clock generator to a clock input may be those clocked elements that are physically placed far away, have a large number of gates in clock/enable paths, overload a clock buffer, or a combination of each. 
     The clock tree circuit  180  includes quite a few clock circuits in the enable and clock paths. If redundant clock circuits can be removed from the clock tree circuit  180 , switching energy may be conserved when clock signals switch and non-switching power may be conserved over time regardless. 
     Clock Topology Planning for Clock Tree Synthesis 
     Referring now to  FIG. 2 , an exemplary flow diagram of clock tree synthesis  200  is illustrated. The position of block  250 A above clock tree synthesis  200  illustrates the logic of an integrated circuit design, but for clock signal logic, being synthesized (mapped and placed) before the clock tree synthesis  200  occurs. The embodiments of the invention allow clock tree synthesis  200  to occur in conjunction with or even prior to the logic synthesis of the functional logic (e.g., data path logic and control logic) of the integrated circuit design. This is illustrated by block  250 A moving down to be even with the implementation process  210  in the clock tree synthesis flow  200 . 
     Prior IC design methodologies performed clock tree synthesis (CTS) as part of the implementation flow after the rest of the IC design had been synthesized and placed. In this case, there is little to no visibility into the effects of design choices on clock synthesis—despite the fact that decisions made early in the IC design flow may have significant consequences on the subsequent timing closure and power closure during the design of the clock tree to generate the clock signals for functional blocks. 
     Clock topology planning or clock tree planning (CTP) with the assistance of a GUI can occur earlier in the IC design flow so that the characteristics of the clock distribution network and its related components are better understood so that problems faced in the prior art may be avoided. In  FIG. 2 , this is illustrated by the block  250 A moving towards the position of block  250 B along the processes of clock tree synthesis  200 . 
     The clock tree planning GUI is described in detail in U.S. Provisional Patent Application No. 61/732,284 filed on Nov. 30, 2012 by inventors Ankush Sood, et al and in U.S. patent application Ser. No. 13/839,769, entitled GRAPHICAL USER INTERFACE FOR PHYSICALLY AW ARE CLOCK TREE PLANNING filed by Ankush Sood et al. on the same date herewith, both of which are incorporated herein by reference. The clock tree planning GUI may be used to view the clock topology plan provided by the embodiments described herein in advance of clock tree implementation so that the performance, power consumption, or other desired characteristics of the clock tree may be improved when the clock tree plan is finally implemented as a physical layout. 
     Clock topology planning, also referred to as clock tree planning, is a framework to provide early estimation and optimization of a clock network that generates clock signals within an integrated circuit design. The focus during clock tree planning is on the topology of the clock network, the functionality of the clock network, and placement of clock gates, enable gates, buffers, and flip-flops to balance timing to the flip-flops and meeting power and timing requirements. 
     Power consumption in an integrated circuit can be greatly influenced by a clock network. If there are accurate estimates of the distributional elements in a clock tree, a more accurate estimate of the parasitic capacitance that is switched may be had. Furthermore, a determination may be made as to whether or not the insertion of a particular clock gate to generate a clock signal will yield a net power savings and should be implemented or rejected. 
     In the physical domain, clock gating can be driven by the placement of the clock sinks, such as the placement of the latches, flip-flops, and registers. Cloning, the act of duplicating circuits to generate a clock signal, can be effective to partition the total capacitance of the fan-out for the purpose of reducing power or improving timing. Merging, the act of removing duplicate circuits and adding additional clock sinks to another signal, can be used to remove extra clock gating elements and shield more buffers in the clock tree and possibly improve power consumption. 
     An estimate of the relative insertion delays at clock gate clock inputs versus flip-flop inputs can be generated early. The early estimate of relative insertion delays allows enable functions to be modified, remapped, or rejected based upon the timing slack in an enable path. 
     A modification for example is to select for some reason a different function that may be a more active function with less power efficiency. Traditionally, logic synthesis of the clock tree network is complete such that modifications cannot be made. Cloning, a modification to the clock tree network, may also be used to reduce the per-driver load and buffering delay to the clock sink, thereby allowing the enable signal to arrive later in the clock cycle but still meet timing requirements. Modifications to the clock tree network allows the enable logic network to be mapped without overly critical enable paths, thereby reducing the area and power consumption of the clock tree network. 
     In  FIG. 2 , clock topology planning  200  includes the processes of de-clock gating  202 , a functional analysis process  204 , a clock tree topology planning process  206 , an incremental optimization process  208 , and an implementation process  210 . 
     During the de-clock gating process  202  the enable functions that are used to generate gated clock signals are identified and stored in a clock tree planning data base. 
     During functional analysis  204 , the RTL logic of the IC design is analyzed to identify additional feasible enable or disable signals that may be used to generate gated clock signals. 
     During the clock tree planning process  206 , an initial placement of enable gates, clock gates and flip-flops forming flip-flop clusters may be performed. Embodiments of the clock tree planning GUI may be used to evaluate the initial placement and make changes as may be desired. Routing of clock signals may be estimated with air lines by the using the X and Y coordinates for the placement of the enable gates, clock gates, and the clocked elements (e.g., the flip flops, registers, and latches). 
     During the incremental optimization process  208 , the clock tree topology is incrementally optimized in response to changes that are desired from the topology planning process  206 . 
     During the implementation process  210 , the clock tree topology is mapped into the gates (e.g., the enable gates, clock gates, buffers, and flip-flops) that are also placed into the layout of the integrated circuit design. 
     Clock Circuit Optimization Methods 
     One of the goals of the clock topology planning process is to reduce power consumption while at the same time meeting clock timing requirements. There are a number of ways a circuit may be optimized to meet both. 
     Referring now to  FIG. 3A , a clock subtree  300 A is illustrated. Clock subtree  300 A includes an enable gate  228 , a clock gate  212 , clock buffers  122 A- 122 B, and sets or clusters  306 A- 306 B of flip-flops  114 A- 114 D. Flip-flops  114 A- 114 C in each flip-flop cluster are clocked by the gated clock signal  303 . Flip-flop  114 D in each flip-flop cluster is clocked by the ungated clock signal  101 . The clock gate  212  generates the gated clock signal  303  in response to the ungated clock signal  101  and the enable signal  330 A. 
     In this implementation of clock gating, the gated clock signal  303  generated by the lone clock gate  212  is shared by all the flip-flops that can be gated in the subtree. Flip-flop  114 D in each flip-flop cluster  306 A- 306 B cannot be gated and remains clocked by the ungated clock signal  101 . With such a large fan out extra capacitive loading is placed on the clock buffers  122 A- 122 B and the clock gate  212 . Moreover, there may be significant cross-overs when routing the ungated clock signal  101  and the gated clock signals that adds further parasitic capacitance loading. With traditional synthesis, the clock buffers may be cloned in a non-physical manner, for example, such as by hierarchy or an arbitrary manner up to the maximum fan out constraints. This can result in a poor implementation of clock gating and the generation of gated clock signals within a clock subtree. 
     Referring now to  FIG. 3B , one method of optimization of the clock circuitry within a clock subtree circuit  300 B is illustrated. In  FIG. 3B , the clock gate  212  of  FIG. 3A  has been cloned such that there are now 2 clock gates  212 A- 212 B. An enable signal  330 B is coupled into the enabled inputs of each of the clock gates  212 A- 212 B. Each of the clock gates  212 A- 212 B generates the gated clock signal  303 A- 303 B, respectively. The gated clock signals  303 A- 303 B are coupled into the clock buffers  122 A- 122 B, respectively. The gated clock signal  303 A clocks the flip-flops  114 A- 114 C in the flip-flop cluster  306 A. The gated clock signal  303 B clocks the flip-flops  114 A- 114 C in the flip-flop cluster  306 B. The ungated clock signal  101  remains coupled into flip-flop  114 D of each flip-flop cluster  306 A- 306 B. In this manner, the switching power of the clock subtree may be reduced by the clock gate cloning and reduced overlap of fan out load at the cost of an added clock gate. 
     Enable logic that generates the enable signals for the clock gates in the clock subtrees may need to meet timing constraints for the enable signal. One such constraint in the generation of the enable signal may be a slack timing requirement on the enable signal path from the enable gate to the clock gate. This may limit the placement of the clock gate in the highest location in the topology of the clock subtree. Additionally, a timing constraint on the enable signals forces a timing driven cloning of the clock gates, or alternatively, a removal of the clock gate and formation of an ungated implementation by recycling the data in the data path. 
     Reference is now made to  FIGS. 4A-4B . In  FIG. 4A , a clock subtree circuit  400 A is illustrated including a clock gate  212  receiving the ungated clock signal  101  and enable signal  430 , a clock buffer  122 , and a flip-flop  414  within a flip-flop cluster  406 A. The clock gate  212  receives the ungated clock signal  101  and the enable signal  430  to generate the gated clock signal  403 . The flip-flop  414  has a data input D to receive data and a data output Q to drive out a data signal from the flip flop. 
     Timing constraints on the enable signal  430  may be so restrictive that the implementation of the clock gate  212  cannot be used to reduce power consumption and generate the gated clock signal to clock the flip-flop  414 . Instead, data output from the flip-flop  414  may be recycled back to its data input so that the state of the flip flop doesn&#39;t switch and change state when it is clocked. 
     In  FIG. 4B , a clock subtree circuit  400 B is illustrated. The clock subtree circuit  400 B is an ungated clock subtree circuit in comparison with the clock subtree circuit  400 A. The clock subtree circuit  400 B has eliminated the clock gate  212  and introduced a multiplexor  424  coupled to the flip-flop  414 . The multiplexor  424  can selectively recycle output data from the flip-flop&#39;s data output to data input. The enable signal  430  in this case is coupled into the enable input of the multiplexor  424 . The ungated clock signal  101  is buffered by the clock buffer  122  to generate a buffered ungated clock signal  413 . The buffered ungated clock signal  413  is coupled into the clock input of the flip-flop  414 . In this manner the ungated clock signal  101  may be coupled into the clock input of the flip-flop  414  with less timing delay and less signal skew. 
     With the enable signal  430  selected to be a logical 0, the data output from flip-flop  414  is coupled into mux input  0  and selected to be output from the multiplexor  424 . The data output of the flip-flop  414  is coupled back into the D input of the flip-flop  414 . In this manner the data output is recycled back into the input of the D flip-flop  414  when it is clocked by the clock, the ungated clock signal  101 . The state of the D flip-flop in this case does not change until the opposite input of the multiplexer  424  is selected. However, the flip flop  414  is still clocked by the clock signal  413  so that internal transistors may switch and some power consumed. The addition of the multiplexer will also consume some power, regardless. By gating the clock signal to ensure it does not reach the clock input, such as shown in  FIG. 4A , switching of circuits in the flip flop is avoided to conserve power. 
     When the enable signal  430  is generated to be a logical 1, the data input coupled into the multiplexor  424  is selected to the output therefrom and coupled into the D input of the flip-flop  414 . In this matter, new data may be registered by the D flip-flop  414  when it&#39;s clocked by the ungated clock signal  101 . Subsequently, the enable signal  430  may change state back to a logical 0 so that once again the data output from the D flip-flop is recycled around from output to input, so that the flip flop doesn&#39;t change state when clocked again by the ungated clock signal  101 . Thus, the ungated clock optimization of the clock circuit  400 B may conserve power by being gated with the enable signal  430  while meeting timing requirements. 
     In  FIGS. 3A-3B , cloning of a clock gate to partition the fan-out on the clock signal up into more manageable quantities was illustrated. A clock buffer may also be cloned to split up the fan out load of a plurality flip flops on a clock signal. 
     Reference is now made to  FIGS. 5A-5B . In  FIG. 5A , a clock subtree circuit  500 A includes enable logic with an enable gate  228 , a clock gate  212 , a clock buffer  122 A and a set or cluster  506  of clocked elements coupled together as shown. The cluster  506  includes flip-flops  114 A- 114 C so it may be referred to as a flip-flop cluster. 
     The clock buffer  122 A may experience too much capacitive load due to the fan out of the flip-flops  114 A- 114 C and the additional wire routing. For example, the wire route from clock buffer  122 A to flip flop  114 A may be long adding to the capacitive load placed on the clock buffer  122 A. To overcome this, the clock buffer  122 A may be cloned and have the fanout of the flip-flops split up into different clusters  506 A- 506 B so that the fan out load is divided up or partitioned amongst a plurality of clock buffers  122 A- 122 B. 
     In  FIG. 5B , a clock subtree circuit  500 B is illustrated with the clock buffer  122 A being cloned into an additional clock buffer  122 B over that of the clock subtree circuit  500 A. The inputs of the clock buffer  122 A and the clock buffer  122 B are coupled together and to the output of the clock gate  212 . The output of clock buffer  122 A is now coupled into the clock inputs of the flip-flops  114 B- 114 C of the flip flop cluster  506 B. The output of clock buffer  122 B is coupled into the flip-flop  114 A of the flip flop cluster  506 A. It may be the case that the clock route of the signal from the clock buffer  122 B to the flip-flop  114 A is long with a large capacity of loading. In this manner, the flip flop cluster  506  of  FIG. 5A  is regrouped into a pair of flip flop clusters  506 A- 506 B after the clock buffer is cloned. 
     Reference is now made to  FIGS. 5C and 5D .  FIGS. 5A and 5B  illustrated how a clock buffer may be cloned and a flip-flop cluster divided up into the plurality of flip-flop clusters and driven by a pair of clock buffers. To meet timing requirements and better match fan out, the flip flop clusters may also be regrouped without cloning additional gates. 
     In  FIG. 5C , a clock tree subcircuit  500 C is illustrated including clock gates  212 A- 212 B, enable gates  228 A- 228 B, and flip-flop clusters  506 C- 506 D. Flip-flop cluster  506 C includes flip-flops  114 A- 114 B having their clock inputs coupled to the output of the clock gate  212 A to receive the gated clock signal. Flip-flop cluster  506 D includes flip-flop  114 C having its clock input coupled to the output of the clock gate  212 B to receive a different gated clock signal. Enable signal EN 1   530 A is coupled to enable input of clock gate  212 B. Enable signal EN 2   530 B is coupled to the enable input of clock gate  212 A. It may be determined that to reduced power consumption and/or improve timing to meet a timing constraint that the flip-flops could be rearranged in their flip-flop clusters and be appropriately clocked by the gated clock signals. For example, consider that it was feasible to gate the clock signal to flip flop  114 B by either enable signal EN  1  or enable signal EN 2 . 
     In  FIG. 5D , a clock subtree circuit  500 D is illustrated. In the clock tree subcircuit  500 D, the flip-flop  114 A of the flip-flop cluster  506 E is clocked by the same gated clock  212 A and its gated clock signal as in clock subtree circuit  500 C of  FIG. 5C . However, the flip-flop  114 B is no longer clocked by the clock gate  212 A. Instead flip-flops  114 B and  114 C are now included in the flip-flop cluster of  506 F. Because flip flop  114 B could have a gated clock signal gated by either the enable signal EN 1  or enable signal EN 2 , both flip-flop  114 B and  114 C can be clocked by the gated clock signal generated by the clock gate  212 B. It may be advantageous to regroup clocked elements in different clusters so as to reduce power consumption and meet a timing constraint. Thus, a regrouping of clocked elements (e.g., flip-flops) within different clusters (e.g., the flip flop clusters) may be another technique that is used to optimize timing and/or power consumption during the clocked topology planning of each clock subtree within an integrated circuit design. 
     For timing optimization it is desirable to avoid highly asymmetric clock tree topologies. If a clock subtree topology is asymmetric, it may clock the flip-flops in the flip-flop clusters at different times such that an output coupled into another input of these flip-flops may have a race condition and result in a non-functioning circuit. It is desirable to balance out asymmetric clock tree topologies whenever possible. However, it may cost additional power to do so. 
     Reference is now made to  FIGS. 6A-6B . In  FIG. 6A , a clock subtree circuit  600 A is illustrated that has an asymmetric clock tree topology. Enable gates  228 A- 228 C in the circuit  600 A generate the enable signals, enable X, enable Y, and enable Z, respectively, that are coupled into the enable inputs of the clock gates  212 A- 212 C. The ungated clock signal  101  is buffered by clock buffer  122  to generate a buffered clock signal  603 . 
     The buffered clock signal  603  is coupled into the clock input of clock gate  212 A. The buffered clock signal  603  is also directly coupled into the clock input of flip-flop  114 A in the flip flop cluster  606  that leads to the asymmetry in the circuit. 
     The buffered clock signal  603  is gated by clock gates  212 A,  212 B, and  212 C before reaching the clock inputs of flip-flops  114 B- 114 E in the flip flop cluster  606 . Thus, the gated clock signals  623 B and  623 C will have different timing delays and skew from that of the buffered clock signal  603  that&#39;s directly coupled into the flip-flop  114 A. The asymmetry in the clock signals that are clocking flip-flops  114 A and flip-flops  114 B- 114 E can lead to timing problems, particularly if the output of flip-flop  114 A is coupled into the data input of one or more of the flip-flops  114 B- 114 E in the flip-flop cluster  606 . One method of balancing out the timing delays in the hierarchy of the clock tree, is to insert buffers or inverters for each clock gate in the parallel clock path. 
     In  FIG. 6B , clock buffers  622 A and  622 B are inserted between the clock buffer  122  and the flip-flop  114 A to form the buffered clock signals  623 A that is coupled into the clock input of flip flop  114 A. Clock buffer  622 A is inserted in the clock path as shown to balance the timing delay and signal skew that is generated by clock gate  212 A. Clock buffer  622 B is inserted in the clock signal path in order to balance the timing delay and timing skew that may be generated by clock gates  212 B and  212 C along their respective clock signal paths. In this manner the buffered clock signal  623 A coupled into the flip-flop  114 A is likely to have more similar timing characteristics to that of the gated clock signals  623 B and  623 C that are coupled into the flip-flops  114 B- 114 C and  114 D- 114 E, respectively. Because they balance timing, the clock buffers  622 A- 622 B may also be referred to as a time balancing clock buffers or skew balancing clock buffers. 
     The disadvantage of adding skew balancing clock buffers  622 A and  622 B is that there is additional power that is consumed as they actively switch their output signals in response to changes in state of the input signals. Thus, the additional power consumption to balance timing skew and timing delay be a factor in determining the implementation of the clock subtree. 
     While insertion of skew balancing clock buffers may be used to balance out signal timing in a plurality of clock paths within a clock subtree, insertion delay may be another issue to consider when inserting a clock buffer along a clock path between a clock source and a clock input to a flip-flop. Timing in the clock subtree is optimized in order to prevent gross timing violations and possibly save significant power downstream near the flip-flops of the flip-flop clusters. 
     In  FIG. 7A , a clock subtree circuit  700 A is illustrated to explain insertion delay of one or more clock buffers  720 A- 720 M. Clock source  102 R generates ungated clock signal  101  that may be directly coupled into the clock inputs of one or more flip-flops  704 A- 704 N of a flip-flop cluster  706 . The clock inputs of the one or more flip-flop  704 A- 704 N form a load that is placed upon the ungated clock signal  101 . Additionally the wire routing from the clock source  102 R to the flip-flop  704 A- 704 N forms additional capacitive loading that is placed on the ungated clock signal  101  and the output buffer of the clock source  102 R that generates the signal. To buffer these capacitive loads (also referred to as clock source load) from the clock source generator  102 R, one or more buffers  720 A- 720 M may be inserted in the clock path between the clock source  102 R and the clock input of the flip-flops  704 A- 704 N. For example, clock buffer  720 A may be positioned at a position  752 A as illustrated between the clock source  102 R and a node  701  before the signal fans out into the clock inputs of the flip-flops  704 A- 704 N. 
     The clock source  702 R is physically placed at a position  752  corresponding to X and Y coordinates within a plan or layout of an integrated circuit design. Similarly flip-flops  704 A- 704 N are placed at positions  754 A- 754 N respectively. Clock buffer  720 A is also positioned at a placement  752 A with X and Y coordinates of the route. 
     A clock source distance D CLK  as indicated in  FIG. 7A  may be determined from the respective placement positions of the clock source  102 R and the flip-flops  704 A- 704 N. A buffer input distance B 1  may be determined as indicated from the respective placement positions of the clock source  102 R and the clock buffer  720 A. A buffer output distance B 2  may be determined as indicated from the respective placement positions of the clock buffer  720 A and one or more of the flip flops  704 A- 704 M or a center of mass position of the flip flop cluster  706 . 
     Thus, when inserting the clock buffer  720 A, there is a clock timing delay that is added between the clock source and the flip flops along the clock signal path. The position  752 A of the clock buffer establishes the parasitic capacitive load of the wire along the distance B 2  of the clock path. The placement position  752 A of the clock buffer  720 A also establishes the distance B 1  between the clock source  752  and the clock buffer  720 A. To obtain a more accurate timing of the clock signal that clocks the flip-flops, the physical placement of the clock source  752 , the clock buffer  720 A, and the clocked elements should be considered. 
     Referring now to  FIG. 7B , a clock subtree circuit  700 B is illustrated including a clock source  102 R, a clock gate  702 , an enable gate  708  within enable logic, and a cluster  706  of flip-flops  704 A- 704 N. Similar to the clock buffer placement in  FIG. 7A , the physical placement of the clock gate  702  at a placement position  712  can affect timing of the clock signals along the clock signal paths. 
     For example, the clock source  102 R may be placed at a position  711  and the flip-flops  714 A- 714 M in the cluster  706  may be placed at positions  714 A- 714 M, respectively. Thus, the distance D CLK  from the clock source to the clock synchs may be determined. The clock gate  702  may be placed at a position  712  along the clock path between the clock source  102 R and the flip-flops  704 A- 704 N. Thus, a distance D CG  from the clock source to the clock gate and a distance D CM  from the output of the clock gate to the clock sinks of the flip flops may be determined. Thus, the position  712  where the clock gate  702  is inserted in a clock path can affect the timing of the clock signal into the clocked elements coupled to the clock signal path. If clock buffers  720 ,  721 A- 721 M are further inserted into the clock signal path, additional timing delay may be added and additional power may be consumed. 
     Furthermore, the timing of an enable signal can be effected by the physical placement  718  of the enable gate  708  with respect to the physical placement  712  of the clock gate  702  within the layout of the integrated circuit design. From these physical placements, a distance D EN  between the enable gate and the clock gate over which the enable signal propagates may be determined. Thus, the placement of the enable gate and the clock gate can affect the timing of the enable signal and whether it can meet timing constraints of the enable signal to the clock gate  702 . 
     During the physical clock topology planning process, the placement of the enable gates, the clock gates, and the flip-flops are considered to ensure that the timing constraints of the clock&#39;s signals are met in a clock subtree. 
     To buffer the capacitive loads, one or more clock buffers  720 ,  721 A- 721 M may be inserted into the clock signal path. Clock buffers  721 A- 722 M are physically placed after the clock gate  702 . Clock buffer  720  is physically placed before the clock gate. Thus, the clock buffer  720  may be always switched by an ungated clock signal from a clock source  711 , or at least with greater frequency that that of clock buffers  721 A- 722 M, due to the difference in placement with respect to the clock gate  702 . Thus, to reduce power consumption, it is preferable to push clock buffers, such as clock buffers  721 A- 722 M, further down in the hierarchy of the clock tree after clock gates so they are driven by gated clock signals and less frequently changing state to reduce power consumption. 
     The more clock buffers precede a clock gate, the more power is consumed. The more clock buffers that are shielded by a clock gate, the less often they may be clocked by a clock signal and thus saves power. Accordingly, the quantity and the physical placement of clock buffers is a factor in evaluating power consumption in the implementation of clock subtree circuits. 
     Referring now to  FIGS. 7C-7D , for example, the size of a cluster box for a flip flop cluster and the flip flop fan-out is proportional to the capability of balancing timing during a clock period  700  of a clock signal between the enable signal generation/receipt and clock gate/buffer (CG) placement with respect to the enable gate (EG). 
       FIGS. 7C-7D  illustrate that the sooner an enable signal  702 A is generated by the EG and received by the CG, the more time in the clock period there is for the CG to generate a gated clock signal and drive a larger fan out of flip flops. The clock gate is usually positioned in a flip flop cluster, such as illustrated in  FIGS. 7C-7D , in order to centrally drive the flip flops in the cluster and balance the gated clock signal delays from the CG to the flip flops within the cluster. 
     In  FIG. 7C , an enable signal is generated by the EG  708 A and is sent a short distance to the CG  702 A. An enable air line  732 A, (a line representing wire routing of the enable signal path), is coupled between X-Y placement coordinates of the EG  708 A and the CG  702 A to represent the short distance (enable distance Den) between them. Thus, the enable signal is available at an early time  730 A within the clock period Tp  700  along the time line illustrated in  FIG. 7C . Ample time remains in the clock period Tp  700  for the clock gate CG to drive a larger fan out of flip flops  704  that may be spread out in the flip flop cluster  706 A. A center of mass line  728 A coupled between a center of mass coordinate  716 A and the placement coordinate of the clock gate GC  702 A may be used to illustrate a center mass distance Dcm. 
     How much fanout a clock gate CG can drive is dependent on the setup slack time that is available at the enable pin (driven by the enable gate EG) of the clock gate CG. If the setup slack time is positive, more time is available than required by clock gate CG gate to receive the enable signal correctly, and more fanout can be driven by the clock gate CG. If the setup slack time is negative, an insufficient time is available for the clock gate CG gate to receive the enable signal correctly, a smaller fanout load is desirable on the clock gate CG. In this case, the clock gate may be mirrored or cloned to reduce the fanout load on each. 
     Whether a clock gate CG can drive more or less fanout load (e.g., the number of clock inputs to flip flops) on its output may be visually displayed within a user interface by a tag being appended to the clock gate. The tag may display the setup slack time value in picoseconds (ps), for example. The tag may be applied next to the clock gate CG with a bubble or overlaid on top of the clock gate CG. If the slack time is positive or zero, the tag and the time value may be displayed with a green color for example. If the slack time is negative, the tag and the time value may be displayed with a red color for example. In this manner, attention may be drawn to the user/designer to the slack time that is negative. 
     For planning purposes, knowing the clock period, the center mass distance may be estimated from the enable distance Den and/or enable time delay to determine the size of a flip flop cluster and the number of flip flops therein. With placement of the flip flops in the flip flop cluster, an actual center of mass can be calculated from the average of their placement coordinates as described further herein. 
     After the flip flops  704  are placed within the flip flop cluster  706 , gated clock signal airlines  733  (lines representing wire routing of the clock signal paths) may be displayed on a display device between the X-Y placement coordinates  712 A of the clock gate CG  702 A and the X-Y placement coordinates  714  of each flip flop  704  in the cluster  706 A. The display of the gated clock signal airlines  733  can illustrate how well the timing is balanced between the flip flops  704  in the cluster  706 . 
     In  FIG. 7D , an enable signal is generated by the EG  708 B. The enable signal propagates a longer distance to the position of the clock gate CG  702 B. An enable air line  732 B is coupled between X-Y placement coordinates of the EG  708 B and the CG  702 B to display on a display device the short distance (enable distance Den) between them. The enable distance Den between the EG  708 B and the CG  702 B is greater than the enable distance between the EG  708 A and the CG  702 A. Thus, the enable signal travels further to the clock gate CG  702 B. Assuming the enable gate generates the enable signal at the same time or it&#39;s the same enable signal, the enable signal is available at the clock gate  702 B at a later time  730 B within the clock period Tp  700  along the time line illustrated in  FIG. 7D . Accordingly, much less time remains in the clock period Tp  700  for the clock gate CG  702  to drive a fan out of flip flops  704  that are closer together in the smaller flip flop cluster  706 B. 
     Thus, an enable signal routed a longer distance from the enable gate to the clock gate causes the clock gate to have a smaller fan out with fewer flip flops to drive and thus, a smaller flip flop cluster. Conversely, an enable signal routed a shorter distance from the enable gate to the clock gate allows the clock gate to have a larger fan out with more flip flops to drive and thus, a larger flip flop cluster. 
     The clock tree planner can adjust the physical placement of the enable gate and clock gate with respect to the clocked elements in order to balance out timing delays and signal skew in the enable signal and the input clock signal to optimally generate a gated clock signal for the clocked elements. 
     Feasible Clock Disable Signals 
     In a clock subtree, knowledge of switching activity in the data paths is useful to determine what signals may used to generate enable signals for the clock gates and where clock gates may be placed with respect to the flip-flops and the flip-flop clusters along a clock signal path. 
     Referring now to  FIG. 8A , a clock sub-tree circuit  800 A is illustrated with a clock gate  812  and a flip-flop  814 . The ungated clock signal clock  101 R is coupled into the clock input of the clock gate  812 . An enable signal EN is coupled into the enable input E of the clock gate  812 . Alternatively, a clock disable signal ENB may be coupled into an enable bar input EB of the clock gate  812 . In either case, the clock gate  812  generates a gated clock signal  801  that is coupled into the clock input of the flip-flop  814 . 
     A data input signal D IN  is coupled into the D input of the flip-flop  814 . The flip flop  814  generates a data output D OUT  from the Q output of the flip-flop. With the gated clock signal  801  gated or disabled, the gated clock signal does not change state so that the data output D OUT  from the flip-flop also does not change state. Thus, during the time period that the gated clock signal  801  is gated or disabled, the flip flop  814  does not need to capture a new data input signal and can maintain the logical state of the data output D OUT . In this case, there is no switching activity in the flip flop and power can be conserved during the time period that the gated clock signal  801  is gated or disabled. 
     In the clock topology planning, it is desirable to determine clock disable signals that can be used to gate the clock to each flip-flop. From logic synthesis, all the possible clock disable signals are recorded that may be used as a clock disable signal for each clocked element. However, not all possible disable signals are feasible to use in gating the clock signal to a clocked element, such as a flip-flop. Thus, a search for feasible disable signals is undertaken. 
     Disable signal can be proven to be feasible if it only disables the clock to the flip flop when the flip flop&#39;s data value does not switch. That is when the disable signal is active, the data input signal at the input to the flip-flop  814  is not transferred to the Q output of the flip flop and the data output signal Dout can remain in a steady state. That is, during the timeframe when the disable signal is active, there is no requirement that the data input be registered by the flip flop  814  and generated a change in the output. There are other types and sources of disables that may be feasible, but most significantly a feasible disable is when a flip-flop or other clocked element need not be clocked. 
       FIG. 8A  further illustrates inverters  816 - 817 . To generate an enable signal using a circuit, a clock disable signal ENB is coupled into the input of an inverter  817  to generate the enable signal EN at its output. To generate a clock disable signal ENB using a circuit, an enable signal EN is coupled to the input of inverter  816  so that the disable signal ENB is generated at its output terminal. Because a disable signal is the inverse of an enable signal and it is well known how to generate each from the other, the terms disable signal and enable signal may be used interchangeably herein. 
     Referring now to  FIG. 8B , a flip-flop  814 A is illustrated having a set of feasible disable signals X, Y, and Z. Flip-flop  814 B in  FIG. 8B  has a set of feasible disable signals of X and Y. Each set of feasible disable signals includes disable signals of X and Y. Since there is overlap of the feasible disable signals of X and Y for each flip flop, the flip flops  814 A and  814 B may share clock gate circuits that disable the clock signal with the feasible disable signals X and Y. Sharing clock gate circuits can reduce the number of circuits that switch with a change in the clock signal and can conserve power. As discussed further herein, it is often desirable to gate the clock signal coupled into flip-flops to reduce power consumption in an integrated circuit design. 
     In  FIG. 8C , a clock sub-tree circuit  800 C is shown including clock gates  112 A- 112 C, clock buffers  122 A- 122 C, and flip flops  114 A- 114 F in a flip-flop cluster. Clock topology planning investigates what signals are used to disable the clock signal to the flip flops and where to place the clock gates and clock buffers, if any, in the clock sub-tree with respect to the placement of the flip flops. To determine the feasible signals that may be used to generate the disable signal to gate a clock at a clock gate, it is desirable to have knowledge of the switching activity of the underlying flip-flops that may have their clock signal gated. 
     For example, the clock tree sub-circuit  800 C may undergo logic simulation to determine the switching activity of the flip flops  114 A and  114 B and identify that they may be disabled by disable signals X and Z. It may further be determined from the switching activity generated by a logic simulation that flip flops  114 C and  114 D may have their clocks gated by disable signals X and Y. Similarly, after logic simulation, it may be determined that flip-flops  114 E and  114 F may have their clocks gated by a disable signal X for example. 
     How to gate the clock gates and generate gated clock signals in a clock sub-tree is determined in a bottom up manner starting with the flip-flops at the bottom of a clock subtree. 
     After determining what feasible disable signals may be used to gate the clocks to the flip flops through logic simulation, the feasible disable signals may be propagated upwards to the clock buffers  122 A- 122 C as shown in  FIG. 8C . The feasible disable signals may be further propagated upward in the clock subtree until used by a clock gate and are then dropped from further propagation as illustrated in the implementation of the clock gates  112 A- 112 C. 
     Clock gate  112 A disables the clock signal using the Z signal. Clock gate  112 B disables the clock signal with the Y disable signal. Clock gate  112 C disables the clock signal using the X disable signal. The gated clock signal output from clock gate  112 A is gated by the X disable signal. As a result of the combination of clock gates  112 B and  112 C, the gated clock signal output from clock gate  112 B is gated by both X and Y disable signals. Similarly, the output gated clock signal from clock gate  112 A is gated by X, Y, and Z disable signals in response to the combination of the clock gates  112 A- 112 C. 
     The clock subtree circuit  800 C is implemented to achieve all of the feasible clock gating possible with the respective disable signals. However, it may not be the most power conserving circuit due to clock gating that is not shared over a significant number of the flip flops. For example, clock gate  112 A with its disable signal Z is used to gate flip flops  114 A- 114 B but it is not shared by other branches of the clock sub-tree to gate other flip flops  114 C- 114 F. As a result, the addition of the clock gate  112 A to the clock subtree may consume more power than the amount saved by gating the clock signal into the flip flops  114 A- 114 B. Thus, it is desirable to achieve a balance between power consumption and the insertion of clock gates. Accordingly, clock gate  112 A may be dropped from the clock signal path in order to achieve an optimal clock sub-tree circuit. 
     Referring now to  FIG. 8D , the clock sub-tree circuit  800 D is illustrated as substantially similar to circuit  800 C but without the clock gate  112 A. The clock gate  112 A consumed more power than what would have been conserved by gating the clock signal to the flip flops  114 A- 114 B. Thus, even though there may be a greater number of feasible clock disable signals, they may not all be used in forming an optimal clock subtree circuit. During the time period when the disable signal Z is active, the data input signals to the flip flops  114 A- 114 B remains steady such that the output remains a steady state when clocked by the gated clock signal from the clock gate  112 B. Thus, the Z disable signal and its clock gate  112 A may be dropped from the clock sub-tree circuit  800 D. 
     Clock Tree Planner and Synthesizer 
     Referring now to  FIG. 9A , a functional block diagram of a clock tree planner/synthesizer  900  is shown. The clock tree planner/synthesizer  900  includes a functional analyzer  910 , a power analyzer  911 , a static timing analyzer  912 , an optimizer/placer  913 , a graphical user interface generator  914 , and one or more priority queues  915  in communication together as shown. The clock tree planner synthesizer  900  further includes an energy/power model  921  and a timing model  922  that are respectively used by the power analyzer  911  and the static timing analyzer  912 . 
     The clock tree planner-synthesizer  900  receives a register transfer level (RTL) net list  901  that includes partially constructed clock sub-trees and clocked elements, such as flip flops within flip flop clusters. The clock tree planner-synthesizer  900  further receives an initial placed net list  902  that includes the placement of clocked elements, such as flips flops within one of more flip-flop clusters. The clock tree planner-synthesizer  900  further receives a clock tree specification  904  for the integrated circuit design and a technology library  905  of physical logic gates that may be used to implement the integrated circuit design. The clock tree specification  904  includes clock design constraints for the clock tree network, such as clock period T and frequency, and may further include enable signal and clock signal timing constraints. The technology library  905  includes the physical circuits of the clock gates, enable gates, clocked elements, as well as other circuits for implementing the clock signal network. The technology library  905  may include information about the physical gates that can be used to model the circuits that are implemented in the clock tree network. The technology library  905  and is coupled into the optimizer  913  and other elements of the clock tree planner  900 . The clock tree planner-synthesizer  900  may further receive an initial floor plan for the logic blocks with the initial placement of the clocked elements in the clock tree. 
     In response to the input information, the clock tree planner-synthesizer  900  generates an optimized netlist  906  for the clock tree, including a physical clock gate typology of the clock gates with respect to the placement of the flip-flops. The clock tree planner-synthesizer  900  may further generate a graphical user interface  908  that may be provided to a graphics controller of a computer for display on a display device. 
     The one or more queues  915  of the clock tree planner-synthesizer  900  includes a priority list of partially built clock sub-trees and clocked elements, such as flip flops, latches or registers, that are to be evaluated as merger partners. One or more queues of clocked elements with common enable signals may be used to construct a clock tree from the bottom up. Placement information may be used to order the clocked elements within the queues initially with data path slack timing being used secondarily to evaluate merger candidates in the clock tree. The placement information may initially be from an initial placement. Placement information may be associated with the clock terminal input of the partially built clock sub-trees or a merger point. Placement information may include the placement coordinates of the clocked elements to evaluate the distance of separation between potential merger partners. If a flip-flop cluster of a plurality of flip flops are to be evaluated for merger, the center of mass coordinates may be used to evaluate the distance of separation between potential merger partners. 
     The function analyzer  910  receives the RTL net list  901  and the initial placed net list  902  to perform a logic simulation and determine the feasible enable/disable signals  920  for each clocked element that may be used with clock gates within a clock sub-tree to gate a clock signal and conserver power. The potential clock gate enable/disable signals  920  are communicated to the optimizer/placer  913  to evaluate alternate embodiments of the mapped gate implementation of each clock subtree. 
     Referring now to  FIG. 9B , a functional block diagram of the functional analyzer  910  is shown. The functional analyzer  910  receives the RTL netlist  901  and the initial placed netlist  902  to determine the potential clock gate enable/disable signals  920 . To determine the potential clock gate enable signals  920  for a clock sub tree, the functional analyzer  910  includes an RTL-coded enable analyzer  910 A, a structure feedback analyzer  910 B, a binary decision diagram based symbolic analyzer  910 C, a random simulation analyzer/SAT-based inferred enable analyzer  910 D, and a physical exclusive OR based clock gating analyzer  910 E. One or more of these analyzers  910 A- 910 E may be used to determine the potential clock gate enables  920  for a given clock subtree. 
     Referring back to  FIG. 9A , the power analyzer  911  analyzes the energy and power consumption of each clock subtree in response to a switching energy/power model  921 . The power analyzer  911  evaluates the alternate embodiments of each clock subtree to determine the lower or lowest power consumption. For example, the optimizer/placer  913  may communicate a clock subtree with and without one or more merged clock gates to determine the power consumption of each. The power analyzer  911  analyzes each in order to determine which can be synthesized and placed within an integrated circuit to provide reduced power consumption. 
     The static timing analyzer  912  analyzes the timing of the alternate embodiments of each clock subtree to be sure the timing requirements are met with the clock enable signals and the gated clock signals. If the timing requirements are not met with an implementation of a clock subs tree, the implementation is discarded and a further search for an optimum implementation of the clock subs tree is performed. 
     The optimizer/placer  913  optimizes each clock subtree and places the clock enable gates, clock buffers, and enable gates with respect to the registers/flip flops in the floorplan for the integrated circuit design. The optimizer/placer  913  selects the preferred implementation and placement of the gates of each clock subtree. 
     The graphical user interface generator  914  is in communication with the optimizer/placer  913  to receive the optimized clock tree netlist  906 . The graphical user interface generator  914  can display the placement of clock gates, enable gates, and clock buffers with respect to the registers and flip flops. The graphical user interface generator  914  implements the clock tree planning graphical user interface (GUI) that is described in detail in U.S. patent application Ser. No. 13/839,769, entitled GRAPHICAL USER INTERFACE FOR PHYSICALLY AWARE CLOCK TREE PLANNING filed by Ankush Sood et al (the “GUI patent application). The graphical user interface generator  914  can generate the various colored airlines and colored boundary boxes described in the GUI patent application, U.S. patent application Ser. No. 13/839,769. 
     Referring now to  FIG. 9C , illustrates a state machine which has four states  951 - 954 . The one or more queues  915  of partially built clock sub trees will transition through each of these states during the merging process. In state  951 , the most timing critical clock sub-tree may be popped first. The state machine then transitions to state  952 . 
     In state  952 , the clock sub-tree is searched to find merger partners from the bottom up starting at the lowest clocked elements, such as the flip-flops. In state  952 , potential merger partners for a clock sub-tree are analyzed to determine if a larger clock sub-tree can be generated to conserver power. After finding an appropriate merger partner, the state machine transitions to state  953 . 
     In state  953 , a new larger sub-tree is implemented in response to finding one or more merger partners. The process then goes to state  954 . 
     In state  954 , the merged clock sub-tree is pushed back into the appropriate queues until all clock sub-trees are analyzed. The state machine continues to cycle through the states for each of the one or more queues of the partially built clock sub-trees until no further merger may be had for a given set of merger partners. 
     Timing Models, Energy/Power Models, and Gate Models 
     Models that may be used by the clock tree planner  900  are now introduced so that the timing and power of complex clock networks within a clock sub-tree can be estimated and various potential clock subtree mergers can be evaluated. The clock tree planner  900  performs a bottoms up recursive binary merging process through a clock tree network. Multiple merger candidates are explored and evaluated on costs of power, energy and timing. Timing requirements must be met regardless. However, reducing power and energy consumption are goals that the clock tree planner strives to meet. To that end, the clock tree planner  900  is dynamically programmed with abstract models for power, energy, maximum timing delay, and minimum timing delay as a function of input clock signal slew. The models may be piece-wise linear interpolations. Partial tree models of potential mergers to be evaluated for power, energy, and timing are formed. The clock tree planner  900  recursively forms the potential merger candidates at each possible merger point in the clock tree hierarchy and preserves the constant time merger evaluations. To reduce power and switching energy, the clock tree planner strives to maximize clock gating, avoid unwanted skew or delay buffers (clock buffers to alleviate each), and minimize wire lengths by proper placement. 
     Clock gating is used whenever possible to reduce power consumption. The higher a clock gate is within the hierarchy of a clock tree network so that it can gate the clock and disable more circuitry from switching, the more power and switching energy may be conserved. Thus, it may be desirable to defer clock gating to upper levels of the hierarchy. To that end, the clock tree planner  900  pushes virtual enable signals upward in the clock tree hierarchy when shared between branches of the clock tree hierarchy. Non-shared enables, enable signals that cannot be shared, may be implemented by clock gates for the lone branch or otherwise dropped. Multiple levels of clock gating are explored given an analysis of timing and the capability of sharing clock gates. Simulation is used to capture the correlation of enable/disable signals and their probability of switching so that power consumption with clock gating can be estimated and redundancy between multiple clock gates can be avoided. 
     Enable signal timing can be used by the clock tree planner  900  to determine if clock gating is appropriate at each given merger point. The setup timing slack of an enable signal to a clock gate limits the level of hierarchy in the clock tree where the clock gate may be placed for a merge operation above it. If a potential clock subtree merger exceeds the setup timing slack, it is dropped from further consideration. This forces a timing driven cloning process or alternatively a removal of clock gating if an enable signal violates a setup timing check that would otherwise cause a clock tree to improperly function. The clock tree planner  900  is symmetry aware and avoids generating highly asymmetric clock tree topologies. If skew balancing clock buffers need to be added for timing balance between circuits in clock subtrees, the added net power cost is added to the unbalanced clock subtree to evaluate mergers. The clock tree planner  900  and the algorithm that it executes prevents gross timing violations in advance and saves power downstream. 
     Reference is now made to  FIGS. 10A-10B . As mentioned previously, the clock tree planner  900  utilizes a timing model  922  when performing a static timing analysis on each clock sub-tree to determine that timing constraints of clock signals and enable signals are being met. The timing model  922  also provides timing information that can be used to balancing out timing delays of clock signals along a clock path for a given clock time period, as well as to balance out timing between an enable/disable input signal and an input clock signal to a clock gate during a given clock time period. 
     In  FIG. 10A , a longest or worst case timing delay model  1010 W for a clocked element, such as a flip-flop, is shown. In  FIG. 10B , a shortest or best-case timing delay model  1010 B for a clocked element, such as a flip-flop, is illustrated. 
     The worst case timing delay model d late (slew)  1010 W and the best case timing delay model d early (slew)  1010 B are curves of piece wise linear interpolations of delay that are a function of signal slew of a clock input signal. The value of the time delay for a given clock signal slew rate represents the delay from the input to the moment data is captured by the clocked element in response to the clock signal. This time delay value may also be considered as an insertion delay time for a clock signal to clock a clock subtree or a clocked element. On the Y and X axes, the curves  1010 W and  1010 B are plotted input setup time of the data input versus slew rate of the clock signal. 
     For evaluation of a lone clocked element such as a flip-flop, the worst-case timing delay d late (slew) and the best-case timing delay d early (slew) are substantially similar such if it needs to be modeled, one model (such as d late (slew)) may be sufficient. When analyzing a lone flip-flop, these timing delay models may be input setup time models for the flip flop over the given slew rates. If the data path to the clocked element is available, the slack timing of the data signal may be used to represent the timing delay of the flip flop. 
     The input setup information for flip-flops can be obtained from the technology library that is received by the clock tree planner  900 . Other clock endpoints or clock input terminals of other clocked elements can be similarly modeled, such as latches, rams and other intellectual property (IP) macro models, with information available in a technology library, and if not, they may be computed or constructed by measuring timing values as a function of clock signal slew. Slack timing of a data input path to a clocked element is determined by a static timing analysis by the static timing analyzer. 
     As mentioned previously, clock tree planner  900  includes a power analyzer  911  and an energy/power model  921  to analyze power consumption. The energy/power model  921  may be used by the power analyzer  911  to analyze the power consumption of the different implementations of clock sub-trees and potential mergers partners of a plurality of clock sub-trees. 
     Referring now to  FIG. 11A , an exemplary switching energy model E sw (Slew)  1110 A as a function of slew is shown for the energy/power model  921  of the clock tree planner. The energy switching model, a piece wise linear interpolations of switching energy, provides the switching energy as a function of slew. Energy in Pico joules (pj) maybe plotted along the Y axis while signal slew in pico-seconds (ps) of the clock signal is plotted along the X axis. Switching energy can be readily changed into power consumption given the frequency of a clock signal if it constantly switches. A clock gate that periodically disables a clock signal so it does not clock a circuit, adds a probability component to the power computation that is explained further below with reference to equation 14. 
     Referring now to  FIG. 11B , an exemplary non-switching power model P nsw    1110 B, a linear interpolation of non-switching power consumption, is shown for the energy/power model  921  of the clock tree planner. Non-switching power P nsw  is a component of the total power consumption of a circuit with transistors, such as a clock gate, a clock buffer, an enable gate, and a clocked element, such as a flip-flop. The non-switching power P nsw  is the result of current leakage in the transistors of the circuit and is a constant over time as illustrated by non-switching power model P nsw    1110 B. Gating a clock signal into a clocked circuit or element so that it does not switch as often does not reduce the non-switching power consumption P nsw . 
     The switching energy model E sw (Slew) and the non-switching power model P nsw  for a given circuit (e.g., a flip-flop) may be obtained from the technology library that is received by the clock tree planner  900 . If unavailable, a circuit can be characterized to determine the switching energy model E sw (Slew) as a function of slew and the non-switching power model P nsw  for a given circuit. 
     Composing Clock Subtree Models and Computing Timing &amp; Power 
     With the timing and power models of circuits introduced, computing the timing and power of more complex clock sub-trees is now described. 
     Wire interconnect (also referred to as wire routing) that is used within an integrated circuit to connect clock signals to the various circuits can consume power and increase timing delay in a signal when they are switched to a different signal level (e.g., logic level zero to a logic level one or visa versa). This is due to the parasitic capacitance and parasitic resistance of the wire and the load it places on a driver of a circuit. The amount of power consumed and the amount of timing delay introduced into a signal can both be modeled as functions of the length of the wire interconnect. 
     Referring now to  FIG. 12 , an exemplary wire  1204  is illustrated that is used to route a clock signal from a clock input terminal IN  1202  to a clock endpoint  1205  of a flip-flop  1206 . The length of the clock signal (Len) from the input terminal  1202  to the clock endpoint  1205  can increase energy consumption (representing power consumption) and timing delay of the clock signal along the clock signal path. The wire timing delay model (delay per unit length) for a wire to compute the timing delay of the wire d wire (len) is available from the technology library received by the clock tree planner. The energy consumption model for a wire (energy per unit length) to compute the energy consumption of a wire E wire (len) is usually also available for reading from the technology library that is received by the clock tree planner. 
     In determining power consumption and timing delay of an overall clock net J, the length of wire routing Len from a clock gate to a flip flop or other sub-tree input K is considered in forming equations 1 through 4 to model the timing delay and power consumption of an overall clock net J as follows:
 
 d   late   J (slew)= d   late   k (slew)+ d   wire (len)  Eq. 1:
 
 d   early   J (slew)= d   early   k (slew)+ d   wire (len)  Eq. 2:
 
 E   SW   J (slew)= E   SW   k (slew)+ E   wire (len)  Eq. 3:
 
 P   NSW   J   =P   NSW   k   Eq. 4:
 
     Equations 1 and 2 add the timing delay of the wire length d wire (len) to the best case timing d early   k (slew) and worst case timing d late   k (slew) of a clocked element (e.g., a flip-flop) to determine the overall timing delay of a clock signal for the clock net J. If more than one clocked element and/or more than one wire segment are present along a clock net or clock signal path, such as from clock buffers and clock gates with the wire route there between, the sum of contributions of each are added together to determine the overall timing delay of the given clock signal path. 
     Equation 3 adds the energy used to transition a signal along the length of the wire E wire (len) to the energy E SW   k (slew) needed to slew the clock signal from a logic zero to a logic one or visa-versa to determine the overall energy used when a clock signal switches on the clock net J. 
     In equation 4, the non-switching power at the input K is the non-switching power of the overall clock network J. Because wire typically has no leakage, a length of the wire adds nothing to the non-switched power consumption. The nonswitching power consumption for the clock network J is equal to the non-switching power consumption of the active devices at input k, P NSW   J =? NSW   k , regardless of wire length. 
     Merge Points 
     As mentioned previously, merger partners are sought out to merge clock subtree circuits together into larger clock sub-trees and possibly share more clock gates to avoid redundancy and conserve power. When two sub-trees are connected together or two flip flops are clocked together, timing and power consumption models can be generated for the total to determine if the merger should be made. 
     Referring now to  FIG. 13 , a merged clock subtree circuit  1300  is illustrated with an M clock sub-tree  1302 A and an N clock sub-tree  1302 B merged together at a merge point  1301 . Equations 5 through 8 can be formed to model the total timing delay and power consumption of merged clock subtree  1300  at the merge point  1301  or a common input terminal.
 
 d   late   total =max( d   late   M   ,d   late   N )  Eq. 5
 
 d   early   total =min( d   early   M   ,d   early   N )  Eq. 6
 
 E   SW   total   =E   SW   M   +E   SW   N   Eq. 7
 
 P   NSW   total   =P   NSW   M   +P   NSW   N   Eq. 8
 
     The total worst case timing delay d late   total  for the merged clock subtree circuit  1300  is the maximum of the worst case timing delay d late   M  for the M clock subtree and the worst case timing delay d late   N  for the N clock subtree. The total best case timing delay d early   total  for the merged clock subtree circuit  1300  is the minimum of the best case timing delay d early   M  for the M clock subtree and the best case timing delay d early   N  for the N clock subtree. The total switching energy E SW   total  for the merged clock subtree is the sum of the switching energies for the M clock subtree E SW   M  and the N clock subtree E SW   N . The total non-switching power P NSW   total  for the merged clock subtree is the sum of the non-switching power consumptions for the M clock subtree P NSW   M  and the N clock subtree P NSW   N . 
     Furthermore, each clock sub-tree has a set of feasible disable signals that may be entirely different or may have one or more common disable signals. M clock sub-tree  1302 A has M feasible disables and N clock sub-tree  1302 B has N feasible disables for its respective flip-flops. With the merger of the two clock sub-trees, the set of feasible disables for the merged clock subtree is the intersection of the feasible disables of each as illustrated by equation 9. A clock disable signal can only be used for the entire merged sub-tree if it is valid for every flip-flop of each clock sub-tree  1302 A and  1302 B. Thus, the set of feasible disables for the merged clock subtree is the common feasible disable signals that are common to both sets of feasible disable signals.
 
Merged feasable Disables= M  Feasable Disables∩ N  Feasable Disables  Eq. 9
 
     By continuously merging clocked elements and clock subtrees from the bottom up towards a merge point, a hierarchical model for an arbitrary binary tree may be generated. The hierarchical model maintains the history of each merger and its models as it constructs the clock tree network from the bottom up until the clock source generator is finally reached. The history, including feasible disable signals at each level of hierarchy, may be particularly useful if a merger of clock subtrees is to be reconsidered. 
     Referring now to  FIG. 14A , an exemplary binary tree  1400  is illustrated after a number of merger operations. The binary tree  1400  includes a flip-flop  14 A of one clock sub-tree merged together with flip flops  1414 B- 1414 C of another clock sub-tree at the merger point  1401 C. The merger of flip-flops  1414 B- 1414 C occurred at the lowest level of hierarchy at merge point  1401 A to form an initial clock subtree that was subsequently merged together with flip-flop  1414 D at merger point  1401 B at the next level up in the hierarchy. Power and timing models for the exemplary binary tree  1400  can be formed using the model equations 5-8. 
     In  FIG. 14B , a total worst case timing delay model d late   total  for the merged clock subtree circuit  1400  as a function of the slew of the clock signal is illustrated by curve  1421 . In accordance with equation 5, the maximum delay of the flip flop or the clock sub-tree is selected to be the total timing delay for the merged binary tree  1400 . Curve  1421  likely represents the worst case timing delay model of the clock subtree circuit below the merger point  1401 B. 
     A total best case timing delay model d early   total  for the merged clock subtree circuit  1400  as a function of the slew of the clock signal is indicated by curve  1422 . In accordance with equation 6, the minimum delay of the flip flop or the clock sub-tree is selected to be the total timing delay for the merged clock subtree circuit  1400 . Curve  1422  likely represents the best case timing delay model of the flip flop  1414 A. 
     Reference is now made to  FIG. 14C  illustrating a curve  1431  that models a total switching energy E SW   total  for the merged clock subtree circuit  1400 . In accordance with equation 7, curve  1431  is formed by summing together the switching energy model for the clock subtree (represented by curve  1432 ) with the switching energy model for the flip-flop  1414 A (represented by the curve  1433 ). 
     Reference is now made to  FIG. 14D  illustrating a curve  1441  that models a total non-switching power consumption P NSW   total  of the merged clock subtree circuit  1400 . In accordance with equation 8, curve  1441  is formed by summing together the non-switching power consumption model for the clock subtree (represented by curve  1442 ) with the non-switching power consumption model for the flip-flop  1414 A (represented by the curve  1443 ). 
     With these models of the clock subtree circuit  1400 , further merges with other clock subtree circuits may be made building upon the models until the clock generator of the clock tree network is reached or no further merges can be considered. 
     Buffers and Clock-Gates 
     In  FIGS. 7A-7B , insertion timing delay was briefly discussed with regards to insertion of a clock buffer or a clock gate within a given clock sub-tree. The insertion of a clock buffer or a clock gate adds additional timing delay to the clock signal path from the clock generator. The insertion of a clock buffer or a clock gate can also transform the slew dependence to a different driver such that slew of a buffered clock signal can be improved over that of the original unbuffered clock signal. 
     From the input technology library that is used to implement the integrated circuit design, there are some known facts with regards to the clock buffers and clock gates. With respect to timing delay, the intrinsic delay through a clock buffer and a clock gate is provided as a function of the input slew of the input signal and the output capacitance applied to the output terminal, d intrisic   buffer (slew, C OUT ). Additionally, the output slew or transition time for the clock gate or clock buffer can be determined as a function of the input signal and the output capacitance on the output total, S buffer (slew,C OUT ). Furthermore, the energy used to switch the clock buffer or clock gate, E sw   buffer (slew, C OUT ), can be determined as a function of the input slew and the output capacitance. With regards to leakage currents, a non-switching power consumption P nsw   buffer  is also associated with the clock buffer or clock gate. With this information from the technology library, the affects of inserting a clock buffer and/or a clock gate on a sub-tree input can be determined. 
     In  FIG. 15 , a clock sub-tree circuit  1500  has a clock buffer  1501  inserted in the input clock path to buffer the capacitive load of the sub-tree circuit  1500  from the ungated clock signal  101  and the clock generator. The output signal slew from the clock buffer  1501  now establishes the input slew to the clock sub-tree  1502  and is used in determining the timing delay component of the clock sub-tree. Thus, the total delay from the clock signal  101  to the clock inputs of the flip flops  1514 A- 1514 C is now a function of the timing delay of the clock sub-tree summed together with the timing delay of the clock buffer  1501 . With the worst case model from the technology library, the total timing delay as a function slew is provided by equation 10.
 
 d   late   total (slew)= d   late   subtree ( S   buf (slew, C   Subtree ))+ d   intrisic   buffer (slew, C   Subtree )  Eq. 10:
 
     The timing delay component of the clock sub-tree in equation 10 is a function of the slew rate of the buffer S buf  for the given input slew from the clock signal  101  and the capacitive loading C Subtree  of the clock sub-tree  1502  that is on the output driver of the buffer  1501 . The timing delay component of the buffer is a function of the slew of the input clock signal  101  and the capacitive loading C Subtree  on the output of the clock buffer from the clock sub-tree  1502 . 
     With the best case model from the technology library, the total timing delay as a function slew is provided by equation 11.
 
 d   early   total (slew)= d   early   subtree ( S   buf (slew, C   Subtree ))+ d   intrinsic   buffer (slew, C   Subtree )  Eq. 11:
 
     For a given buffer and clock subtree, the timing delay component of the clock subtree may be looked up using a stored clock subtree model such as that illustrated in  FIG. 14B . The intrinsic buffer delay component of the total time delay may be extracted from the technology library. 
     The overall switching energy of the circuit when the buffer  1501  is inserted before the clock subtree is the sum of the switching energy of the clock sub-tree  1502  and the switching energy of the clock buffer  1501  as indicated by equation 12.
 
 E   total (slew)= E   sw   subtree ( S   buf (slew, C   Subtree ))+ E   sw   buffer (slew, C   Subtree )  Eq. 12:
 
     For a given buffer and clock subtree, the switching energy component of the clock subtree may be looked up using a stored clock subtree model such as that illustrated in  FIG. 14C . The intrinsic buffer switching energy component of the total switching energy may be extracted from the technology library. 
     The total non-switching power consumption of the circuit with the buffer  1501  inserted in the clock path is the sum of the non-switching power consumptions of the clock buffer  1501  and the clock sub-tree  1502  as indicated by equation 13.
 
 P   NSW   total   =P   NSW   subtree   +P   NSW   buffer   Eq. 13:
 
     For a given buffer and clock subtree, the non-switching power consumption component of the clock subtree may be looked up using a stored clock subtree model such as that illustrated in  FIG. 14D . The intrinsic non-switching power consumption component of the clock buffer may be extracted from the technology library. 
     With this information, an evaluation can be made if insertion of the clock buffer  1501  in the clock path is proper in the clock tree network of clock signals. 
     Evaluating Power Under Clock Gating 
     Previously the switching energy Esw has been computed for the various circuitry in the clock sub-trees and the overall clock typology. Typically, switching power consumption is determined to be the product of energy consumption and clock frequency. However, with the introduction of clock gating, the flip-flops and the wire interconnect is not always switching. There is an average probability that the clock to one or more flip-flops is gated such that power is not consumed when the switching of a clock signal is masked out or disabled. In this case, the switching power consumed is proportional to one minus the probability that the clock is gated to the flip-flop, (1−Prob CG ). With a single clock gate, the switching power consumption for the clock sub-trees can be calculated using equation 14.
 
 P   sw   =E   sw   *f   clk *(1−Prob CG )  Eq. 14
 
     In equation 14, switching power consumption is equal to the product of the switching energy, the clock frequency, and the quantity of one minus the probability that the clock is gated (1−Prob CG ). The probability Prob CG  that a clock signal is gated to one or more flip-flops can be estimated using functional stimulation data. 
     The function analyzer  910  in  FIG. 9A  performs functional simulation of the received RTL netlist to determine feasible clock disables. It further considers all the possibilities of implementing the clock disable for each disable signal over a period of time. Thus, a simulation vector for each disable signal may be formed representing a set of values over time for the clock disable signal. 
     In  FIG. 16A , exemplary simulation vectors  1601 - 1603  are illustrated for X, Y, and Z disable signals. In the exemplary simulation vector  1601 , the X disable signal is active during time periods T 4 -T 6  and T 10 -T 15  to disable a clock signal, for example. In exemplary simulation vector  1602 , the Y disable signal is active during time periods T 4 -T 6  to disable a clock signal. In exemplary simulation vector  1603 , the Z disable signal is active over times T 1 -T 3  to disable a clock signal. 
     Referring now to  FIG. 16B , a clock activity vector  1610  is illustrated for example. Given a clock tree with clock gates, the clock activity vector describes whether a given clock signal is switching overtime. A clock activity vector is not a simulation vector. In  FIG. 16B , the clock activity vector  1610  is for a gated clock signal because it does not switch during time periods T 4 -T 6  and T 15 . 
     Referring now to  FIG. 16C , an ungated clock signal, such as from the clock source, has a clock activity vector  1611  which is all ones. A clock activity vector  1611  with all ones over the given time period T 1 -T 15  represents that the given clock signal is always switching. 
     Referring now to  FIG. 17 , a clock tree sub-circuit  1700  is illustrated having clock gates  1712 A and  1712 B coupled together as shown. Clock gate  1712 A receives the ungated clock signal  101 R into a clock input and the disable signal X  1702 A at its enable input to generate a clock gated signal  1701 A. Given the input clock activity vector and the simulation vector for the disable signal of a given clock gate, the clock activity vector of the gated clock signal can be determined. 
     The ungated clock signal  101 R has a clock activity vector that is all ones. Disable signal X has a simulation vector  1710 A comprising for example 000111 over six clock cycles. A resultant clock activity vector  1711 A generated by the clock gate  1712 A in response to the gated clock signal  1710 A is illustrated. During the first three time periods the gated clock signal is active and in the last three time periods the gated clock signal is inactive (disabled) because the disable signal  1710 A is active. 
     The gated clock signal  1701 A is coupled into the clock input of the second clock gate  1712 B. The disable signal Y  1702 B is coupled into the enable input of the clock gate  1712 B in order to generate the gated clock signal  1701 B. 
     An exemplary simulation vector  1710 B for the disable signal Y is 100001. The gated clock  1712 B generates an output activity vector  1711 B for the gated clock signal  1701 B. Exemplary output clock activity vector  1711 B is 011000. The first bit is 0 because the disable signal Y is active during the first time period to negate the switching clock signal at the first time period. 
     To determine the resultant clock activity vector at the output of a clock gate, a bit-wise AND operation may be performed between an inverse simulation vector of a disable signal (enable simulation vector) and the clock activity vector for the clock signal input to the clock gate. Given a clock activity vector, a probability Prob CG  that the output gated clock signal does not switch (inactive) can be estimated. The probability Prob CG  that the output gated clock signal does not switch is determined by dividing the number of zeros in the clock activity vector by the number of bits in the clock activity vector as indicated by equation 15.
 
Prob CG =number of zeros/number of bits  Eq. 15
 
     Given the exemplary clock activity vector  1711 B for the gated clock signal  1701 B generated by the clock gate  1712 B, the probability Prob CG  that the output gated clock signal  1701 B does not switch is 4/6 or ⅔ (0.667 in decimal format). The probability that it does switch can readily be found by subtracting probability Prob CG  from one or (1−Prob CG ). 
     Merger Algorithm 
     Ideal clock tree synthesis assumes that the clock signal can reach all elements at the same time (e.g., time zero), such that there is no clock skew (the difference between d late  values for best and worst case timing parameters is zero). Thus, if a substantially balanced clock tree network can be formed through planning, than clock timing closure when the clock tree is implemented can readily occur. A clock subtree should not only be balanced within its own branches but also across to other clock subtrees to minimize clock skew. For example, in a binary merger of two clock subtrees, the two clock subtrees with the smallest magnitude of d late  values may be initially picked for merger because when joined, they are likely to have the least difference between d late  values. After merger, the next two with the smallest magnitude of d late  values is considered. Thus, an ordered queue of d late  timing values may be used for clock tree planning. 
     As mentioned previously herein, the clock tree planner  900  includes one or more queues  915  as shown in  FIG. 9A . A state machine  950  within the clock tree planner  900  executes states  951 - 954  with the one or more queues  915  as shown in  FIG. 9C  to step by step construct a balanced clock subtree, starting from the bottom level of clocked elements and working up to the clock generator  102  at the top level of hierarchy. A merger algorithm for clock tree planning functions in response to the one or more queues  915 . The merger algorithm is a bottom-up binary tree building algorithm that starts at the bottom of the clock tree hierarchy with clocked elements (e.g., flip-flops in the flip-flop clusters) and then moves upward towards the clock source that generates the root clock signal, the initial ungated clock signal. 
     The one or more queues  915  are priority queues, an ordered queue, that lists clocked elements initially and then unmerged clock subtrees as they are constructed and added into the queue. For a given integrated circuit design, the one or more queues  915  are initialized by inserting all of the clocked elements (e.g., the flip-flops, latches, registers, clock gates, etc.) into the queue for a common enable/disable signal. 
     Referring now to  FIG. 32A , illustrates a plurality of priority queues  3215 A- 3215 N (instances of the one or more queues  915 ) to list clocked elements and clock subtrees having common enable/disable signals. For example, latches L 1  and L 3  and flip-flops FF 1 , FF 3 ,FFX, FSFXY are listed in queue  3215 A for having X disable signal in common. Latches L 2  and L 3  and flip-flops FF 2 , FF 3 ,FFY, FSFXY are listed in queue  3215 B for having Y disable signal in common. Queue  3215 N lists clocked elements and clock subtrees that have both X and Y disable signals in common, such as latch L 3  and flip-flops FFY,FFXY in the example. 
     In an alternate embodiment, the plurality of priority queues  3215 A- 3215 N may be organized into a single queue  3125  but segment from each other as illustrated in  FIG. 32B . 
     Once the clocked elements are organized into the queues  3215 A- 3215 N, 3215  of common disable signals, they may be ordered in various ways from top to bottom for consideration of mergers or cluster between elements within the queues. 
     One such order is by physical location (X and Y coordinates on a grid) within a floorplan. Nearest neighbors, responsive to physical placement, may be determined as described herein for merging of clocked elements together into clusters and the merger of clock subtrees into larger clock subtrees. Nearest neighbors may be listed in the queue near each other so that they may be evaluated for merger or clustering together in order to conserve power and balance timing. 
     Secondarily, timing delay, such as data path slack timing or insertion delay timing, may be used to evaluate the order of each queue  3215 A- 3215 N. 
     Thus, a list of clocked elements can be arranged in priority based on feasible enable signals, physical location, and timing so that all may readily be considered as criteria for determining merger partners, such as a binary merger of two clocked elements or clocked subtrees. With a single queue, these criteria are not used in a mutually independent fashion. Three factors may be used concurrently for ordering. Feasible enable/disable signals can be used to order the queue. Physical location can be used to order a queue. Timing, such as data path slack timing, may be used to order clocked elements in a queue. For clock subtrees, the timing value of accumulated insertion delay Dlate ma be used to order the queue. In any case, an ordered queue is formed from which to pop a clocked element or clock subtree for consideration of being a merger candidate. 
     Consider  FIG. 18A , for example, clocked elements (e.g., latches L 1 -LN, Registers R 1 -RN, and flip-flops FF 1 -FFN) are in queue  915 A for a given common enable/disable signal and are desired to be reordered. As mentioned herein, these clocked elements can then be rearranged in a priority order based on physical location. They can also be reordered based on and timing, such as data path slack timing or clock path insertion delay timing. Data path slack timing values for the clocked elements (e.g., data-input slack timing for flip flops), based on a static timing analysis of the circuit using an ideal clock, can also be another time criterion that can be used to decide initial groupings of clocked elements. Similar slack timing implies that the clocked element can receive the clock at the same time, without causing further timing issues. A further ordering in the queue based on slack timing over the common feasible enable/disable signals and neighboring physical location may facilitate forming the initial grouping of clocked elements into clusters (or clock subtrees). 
       FIG. 18B  illustrates an exemplary order in a priority queue  915 B based on (accumulated insertion delay d late  or slack) timing with latches L 1 -LN at top of queue  915 B with the least time, registers R 1 -RN in the middle, and flip flops FF 1 -FFN near the bottom of queue  915 B with the most time. 
     To form a clock tree network from the bottom-up, it is assumed that the clock signal at the lowest level of clocked elements reaches all the clocked elements at the same time, such as time zero or zero picoseconds (0 ps) illustrated by flip-flops  1414 A- 1414 D in  FIG. 14A  for example. As the flip flop clusters and clock subtrees are formed from the clocked elements, the timing delay of a clock signal through the clock subtrees from the bottom-up to reach an upper merger point or input point accumulates to be the d late  timing value described further herein. The clock signal time to the merger point or input point of the subtree at the upper level of hierarchy is then (0−d late ) or simply (−d late ), such as illustrated by −d late M and −d late N in  FIG. 21  for example. In  FIG. 21 , d late M and d late N is the time for the clock signal to propagate down through the clock subtrees  1910 M and  1910 N, respectively. 
     As clock subtrees are formed from the clocked elements, they are pushed in proper order into the queue  915 , such as illustrated by the addition of clock subtrees A through clock subtrees N shown in queue  915 C of  FIG. 18C . With the order shown in  FIG. 18C , the clocked elements (L, R, and FF) have magnitudes of (−d late ) less than the magnitudes of (−d late ) for the added clock subtrees. After initialization, the priority queue  915  maintains a constant order so that the least negative (−d late ) is popped first so that is can be consideration for merger with the next least negative (−d late ). 
     The queue  915  can be ordered according to the timing delay signal (−d late ) to select two of the clocked elements and/or clocked subtrees with the least timing delay so they can achieve balanced timing within the clock tree network. Arranging the queue  915  in order top to bottom, from least negative (−d late ) to most negative (−d late ), it is expected that the clocked elements (e.g., flip flops, latches, registers) with (least negative value of −d late ) are to be closest to the top of the queue in one embodiment, and represent circuits in the leaves or bottom level of clock tree hierarchy of the final clock tree. In another embodiment, the queue  915  could be reverse ordered but operated upon from the bottom up, somewhat in parallel with the bottom-up operation on the hierarchy of the clock tree. 
     In  FIG. 18C , the unmerged clock subtrees A-N and clocked elements (e.g., flip-flops FF 1 -FFN) are ordered in the queue  915 C based on insertion delay, from least negative (−d late ) to most negative (−d late ). The order in queue  915 B would be equivalent if it were ordered from the smallest magnitude (+d late ) to the largest magnitude (+d late ) or simply ordered by increasing magnitude for positive d late  (+d late ). As more and more clock subtrees are formed, all of the lower level clocked elements may have been merged into clusters/clock subtrees such that clock subtrees A through clock subtrees N may only remain in the queue, such as illustrated by queue  915 D in  FIG. 18D . 
     Lower level clock subtrees are merged together to form larger clock subtrees with greater levels of hierarchy. Eventually the merger process may only need to evaluate two remaining clock subtrees (e.gl., clock subtree X and clock subtree Y) for merger, such as illustrated by queue  915 D in  FIG. 18D . With this final merger completed, a balanced clock tree network is formed. 
     Thus, the queue  915  ordered bottoms-up, conceptually flips the clock tree so that the clock generator is at bottom. The queue is utilized to construct a balanced clock tree network by evaluating mergers of clocked elements and clock subtrees, adjusting physical placement of clocked elements and clock subtrees as needed, and inserting clock buffers and clock gates as needed, all in a bottoms-up hierarchical fashion. While a single clock signal is considered in this example, if there are multiple clock signals generated by a clock generator, each may have its own queue to generate a clock network for each root clock source signal. The clocked elements driven by each clock are put into a separate queue  915  and then ordered so that a balanced clock tree network can be formed. 
     The state machine  950  in  FIG. 9C  starts a merger process by popping the clocked element or clock subtree from the top of the queue  915  to start generating a bottoms-up hierarchical order for the clock tree network. The elements in the queue  915  may be ordered by physical location, data path slack timing, and feasible enable/disable signals. Physical placement is important to evaluate to determine how to minimize wire lengths and merge elements together to balance timing delay and power consumption. Timing slack of data paths (data path slack) to clocked elements may be important to evaluate to merger candidates as well as to determine if useful clock skew is available. Grouping FFs/Latches together with a similar timing slack, allows the use of useful skew to improve timing on certain clock/data paths that would otherwise violate timing in the ideal clock scenario. However, even if the timing slacks are different, as long as clock trees are balanced with respect to timing (e.g., insertion timing delay), clock timing closure can be achieved assuming that timing was closed in an ideal clock scenario. Grouping clocked elements together based on feasible enable/disable signals, may provide common clock gating with common enable/disable signals to conserve power. 
     To achieve timing balance and minimize skew across clock subtrees, the clock subtree with the least d late  is considered initially for merger and usually with the next least d late . The least d late  and the next least d late  in the queue should already be closely balanced, requiring minimal changes in placement and added clock buffering to further balance out the difference between d late  values substantially to zero. Note that if the difference between a pair of d late  values is being balanced out, than the difference between a pair of d early  values should also be balanced out. 
     Referring now to  FIG. 19 , a floor plan  1900  of an integrated circuit design is shown to consider the physical placement of clocked elements and clock subtrees therein for evaluating merger candidates. Because a merger operation should be physically aware, nearby clock subtrees and clocked elements may be selected as potential merger partners with the currently popped clock subtree or clocked element. 
     Assume that clock subtree M  1910 M is the currently popped clock subtree for which a merger partner is sought. The clock subtree M  1910 M is placed within the floor plan  1900  with a clock input at a position  1920 M having X and Y coordinates. Each clock subtree placed within the floor plan  1900  has a physical position or location  1920  for their respective clock inputs with X and Y coordinates. 
     Given the position M  1920 M associated with the clock subtree M  1910 M, a comparison is made with each physical position  1920  of each other clock subtree and clocked element to determine each distance a wire route would need to be made to couple them together. The N nearest unmerged clock subtrees and clocked elements are determined, such as by a distance space lookup. N may be 100, for example, to find the  100  nearest unmerged clock subtrees or clocked element for potential merger with clock subtree M  1910 M. For example, clock subtrees  1910 A- 1910 N fall within the N nearest merger partners for the clock subtree M  1910 M. However, in comparing distances, clock subtree  1910 X falls outside of the N nearest unmerged clock subtrees. 
     In an alternate embodiment, nearby merger partners may be selected by using a radius R from the position  1920 M of the clock subtree  1910  to define a merger partner boundary  1950 . Potential merger partners with the boundary  1950  are considered to be the nearest merger partners for evaluation. In another alternate embodiment, a minimum spanning tree may be used to select nearby merger partners for evaluation of a merged clock subtree. 
     For each of the N nearest merger partners, the merger algorithm forms a pair-wise merge evaluation with the clock subtree  1910 M as one of merger partners for each. 
     Referring now to  FIG. 20 , the clock subtree M  1910 M and a neighboring clock subtree N  1910 N are being evaluated for a pair-wise merge at the merge point Q 1001  to form a larger clock subtree  2000 . The feasible clock disable signals for each clock subtree  1910 M and  1910 N have been previously determined. Clock subtree  1910 M, for example, has a feasible set of clock disables consisting of disable signals X and Y. Clock subtree  1910 N, for example, has a set of feasible clock disables consisting of disable signal X. 
     For a merger into a larger clock subtree  2000 , clock buffers may be added to prevent lower clock subtree input capacitance from exceeding a special capacitance value. A clock buffer may also be inserted into a clock signal path (or enable signal path) in the clock subtree  2000  to minimize unwanted clock timing skew, the difference between early and late timing delays, given some nominal value (e.g., an arbitrary value) of input signal slew in accordance with Eq. 16.
 
Unwanted clock timing skew= d   late (slew nom )− d   early (slew nom )  Eq. 16
 
     Moreover, each pair-wise merger into the larger clock subtree  2000  is evaluated to determine if non-common clock gates (a clock gate inserted into one leg or branch of a clock signal path but not the parallel leg or branch off a merger point) are to be inserted in either leg of the clock signal path to each clock subtree  1910 M, 1910 N. A non-common clock gate may be inserted if it provides an overall net power saving. 
     For example, the ungated clock signal  101 R may be gated for the entire clock subtree  2000  (including clock subtree  1910 M and  1910 N) using a common clock gate that is responsive to the common disable signal X. However in this example, the non-common disable signal Y can only be used to gate the clock subtree  1910 N with a non-common clock gate. In this example, a clock gate disabled by the signal Y may be inserted along the clock signal path between the merge point  2001  and the clock subtree  1910 M. This clock gate would be a non-common clock gate between the clock subtrees  1910 M and  1910 N. 
     Referring now to  FIG. 21  and continuing with the example illustrated in  FIG. 20 , a merged clock subtree  2100  is illustrated differing from clock subtree  2000  with the added clock gates  2012 A and  2012 B. The clock gate  2012 A is a common clock gate that is disabled by the signal X because it is a feasible disable signal that is common to both clock subtree  1910 M and  1910 N. Clock gate  2012 B is a non-common clock gate that is disabled by the non-common disable signal Y that is a feasible clock disable signal for only clock subtree  1910 M. 
     The common clock gate to the pair of clock subtree merger partners  1910 M and  1910 N typically conserves power for the entire merged clock subtree  2100 . However, the non-common clock gate  2012 B can either offer a net power savings or it can add a net power cost to the total power consumption of the merged clock subtree  2100 . If the non-common clock gate  2012 B prevents a signal switching into a large amount of capacitance in the clock subtree  1910 M, it may offer a net power savings. On the other hand, the non-common clock gate  2012 B consumes power when it&#39;s switched and adds additional capacitive loading that must be switched by the output of the clock gate  2012 A. If that is the case, additional clock buffering may need to be inserted because of the capacitive loading of the non-common clock gate  2012 B. A determination is made if the energy switching of the added non-common clock gate  2012 B is less than the product of the energy to switch the clock signals within the clock subtree M times the probability that the disable signal disables the clock signal to the clock subtree  1910 M as indicated by Equation 17a.
 
 E   sw   CG   &lt;E   sw   M *prob( Y )  Eq. 17a
 
     When considering mergers of clock subtrees and insertion of a clock gate in the clock signal path above the merged clock subtree, the merged clock subtree must meet a timing requirement governed by the enable or disable signal clocking of the given clock gate being inserted. For example in  FIG. 21 , consider the merged clock subtree below merger point  2001  and the insertion of clock gate  2012 A with the X enable signal. It may be determined that X enable signal has a positive input slack time S (e.g., see  FIG. 1D  and the discussion thereof) that would allow insertion of the clock gate  2012 A. Thus, the magnitude of the merger timing (d late ) at merger point  2001  for the merged clock subtree must be less than the positive slack time S of the X enable signal at the enable input to the clock gate  2012 A as indicated by Equation 17b.
 
 d late@merger point&lt; S  (slack timing being positive)  Eq. 17b
 
     The magnitude of the timing d late  at the merger point  2001  (dlate @ merger point) is the maximum of either the sum of d late M of the clock subtree  1910 M and the d late  of the clock gate  2012 B or the d late N of the clock subtree  1910 N. Otherwise, if equation 17b is not satisfied, the clock signal will not properly reach the clock subtree below and the circuits will not properly function. Thus, the enable/disable timing slack sets a ceiling for how much merging of clock subtrees may occur below it. If a potential merger exceeds this requirement, the clock gate may be removed, if possible, or else the potential merger abandoned in favor of a different type of merger. 
     Common clock disable signals, such as X disable signal in the example of  FIGS. 20-21 , are optimistically assumed to be implemented using a clock gate at a higher point in the clock tree (e.g., a virtual disable). For example, a clock disable signal Z that could be used to disable all clock subtrees and all the clocked elements therein would be used for a later merger that might merge across all clock subtrees. This is not assured, but it provides a best case scenario to compare mergers between pairs of clock subtrees. 
     Wires and perhaps clock buffers are added to connect clock signal paths together at the merger point  2001 . A common clock gate  2012 A was added above the merger point  2001  to form the merged clock subtree  2100  in  FIG. 21 . The merger point  2001  is not the clock input terminal for the merged clock subtree  2100 . A new clock input terminal with its physical placement is determined to be clock input terminal  2120  that may be at or near the clock input terminal of the clock gate  2012 A. 
     The new clock input terminal  2120  of the merged clock subtree  2100  is placed within the floor plan  1900  so that it can be used to determine possible subsequent merges with other clock subtrees. A Deferred Merge Embedding (DME) algorithm; introduced by Masato Edahiro in his paper entitled, Minimum Skew and Minimum Path Length Routing in VLSI Layout Design, published in NEC Research and Development Journal, volume 32 (1991), pages 569-575; may be used to physical place the new clock input terminal of the merged clock subtree. 
     Given the popped merger candidate from the queue, the merger algorithm evaluates pairs of potential merged clock subtrees, each including the given popped merger candidate. After each pair of potential merged clock subtrees are evaluated, the pair with the minimal additional power cost is selected for implementation and insertion back into the priority Q 905 . Before a merger, costs may be compared against the neighboring clock subtrees. These merger costs may account for extra clock buffers, extra wiring, non-common clock gating that was implemented and non-common enable/disable signals that were dropped from consideration. The merger costs are evaluated against the power savings of a merger that can reduce redundancy and possibly reduce the switching frequency of clocked circuits to conserver power. If merger costs exceed the power savings for a given proposed merger between clock subtrees, the potential merger may be dropped and a different merger with the popped merger candidate may then be considered. 
     Referring now to  FIG. 22 , an example process of mergers of clocked elements and clock subtrees is now described. In the priority queue  915 , clocked elements  2214 A- 2214 H may be initially ordered by increasing worst case time delay d late , illustrated from left to right in  FIG. 22 . Because the priority queue  915  is ordered by increasing worst case timing delay (the magnitude of d late ), mergers may more often occur between least d late  and next least d late  so that the clock subtrees may grow at a balanced rate. The clocked elements in the priority queue may be flip-flops registers, or latches. The clock subtrees are clusters of one or more latches, one or more flip-flops, or one or more registers with or without clock gates and enable gates. 
     At step  2201  in the example shown in  FIG. 22 , assume that there are initially eight flip-flops arranged in an order from left to right under consideration for potential merger pairs. The initial order in the queue  915  for clocked elements may be established under different criteria such as timing, physical placement, or common feasible disable signals. In evaluating merger candidates from the queue  915  during the merging process, flip flops with common feasible disable signals are initially grouped together for evaluation. Next the placement criterion for the flip flops is used to order and group the flip flops into clusters so that that the shortest clock paths with minimal insertion delays are created. Other criteria may be used to evaluate costs and benefits of mergers between clocked elements or clock subtrees. Moreover, timing of the potential mergers between clock subtrees is considered up to the enable slack timing of an enable gate when a clock gate is consider for insertion. Physical placement of clock buffering and clock gating may be considered to further balance out the difference between values of d late  for a merger pair, all the while conserving power and energy. 
     Each of the clocked elements  2214 A- 2214 H may have sets of one or more feasible disable signals to disable the clock input. The intersection of the feasible disable signals (common disable signals) is one criteria for selecting a merger partner. Physical placement may be another criteria for selecting merger partners. A nearest set of N clocked elements (or alternatively those placed within a radial distance) may be evaluated for merger with the selected or popped merger partner  2200 A- 2200 G. Maximum power savings or minimal power costs of a potential merger pair, while meeting timing requirements, may be the criteria for determining if a potential merger pair is to be implemented as a merged clock subtree. 
     In steps  2201 - 2207 , a selected merger partner  2200 A- 2200 G at the top of the queue (or alternatively the bottom of the queue if ordered differently) is used to determine and evaluate potential mergers with the other clocked elements in the priority queue. 
     In step  2201 , for example, clocked element  2214 A is the selected merger partner  2200 A that is to be evaluated with the nearest merger partner of clocked elements  2214 B through  2214 H. For example, it may be determined that a preferred merger partner is clocked element  2214 E for merger with clocked element  2214 A because it is the one with the minimum additional power cost, for example, and thus it may be implemented as clock subtree  2210 A. 
     At step  2202 , clock subtree  2210 A is placed in the queue  915  as a result of the merger of the clocked elements  2214 A and  2214 E. Clocked element  2214 B pops to the top of the queue and is now selected for evaluating pair-wise merger partners. At step  2202 , it is determined that clocked element  2214 H is the preferred merger partner to be merged with clocked element  2214 B and is implemented as clock subtree  2210 B. 
     At step  2203 , clock subtree  2210 B is pushed onto the queue  915  as a result of the pair-wise merge between clocked elements  2214 B and  2214 H. Clocked element  2214 C is popped to the top of the queue  915  to be the selected merger partner  2200 C. The clocked element  2214 C is evaluated with clocked elements  2214 D,  2214 H,  2214 G, clock subtree  2210 A, and clock subtree  2210 B. It is determined that clocked element  2214 C is the preferable merger partner to merge with clocked element  2214 F and is implemented as clock subtree  2210 C. 
     At step  2204 , clock subtree  2210 C is pushed onto the queue  915  as a result of the merger between clocked element  2214 C and clocked element  2214 F. Clocked element  2214 D is pushed to the top of the stack as the selected evaluation partner  2200 D. Clocked element  2214 D is evaluated for merger with clocked element  2214 G, and clock subtrees  2210 A through  2210 C. It is determined that clocked element  2214 G is the preferable merger partner to merge with clocked element  2214 D and is implemented as clock subtree  2210 D. 
     At step  2205 , clock subtree  2210 D is pushed onto the queue  915  as a result of the merger between clocked elements  2214 D and  2214 G. Clock subtree  2210 A is pushed to the top of the queue  915  and is now the selected evaluation partner  2200 E. Clock subtree  2210 A is evaluated for merger with clock subtrees  2210 B through  2210 D. It is determined that clock subtree  2210 D is the preferable merger partner to merge with clock subtree  2210 A, such as because the merged clock subtree provides maximum power conservation for example, and is implemented as clock subtree  2210 E. 
     At step  2206 , clock subtree  2210 E is pushed onto the queue  915  as a result of the merger between clock subtrees  2210 A and  2210 D. Clock subtree  2210 B, next in order, is pushed to the top of the queue  915  and is now the selected evaluation partner  2200 F. Clock subtree  2210 B is evaluated for merger with clock subtrees  2210 C and  2210 E. It is determined that clock subtree  2210 C is the preferable merger partner to merge with clock subtree  2210 B, such as because the merged clock subtree provides minimal power costs for example, and is implemented as clock subtree  2210 F. 
     At step  2207 , clock subtree  2210 F is pushed onto the queue  915  as a result of the merger between clock subtrees  2210 B and  2210 C. Clock subtree  2210 E, next in order, is pushed to the top of the queue to be the selected evaluation partner  2200 G. Clock subtree  2210 E is evaluated with clock subtree  2210 F for a pair-wise merger. At step  2207 , it is determined that it is appropriate to merge the clock subtrees  2210 E and  2210 F together. At step  2208 , clock subtree  2210 G is formed as a result of the pair-wise merger of clock subtrees  2210 E and  2210 F. The queue  915  outputs the clock subtree  2210 G for implementation. Another set of clocked elements and/or clock subtrees may be queued up into the priority queue for clock tree merger evaluation until the entire clock tree network is evaluated. 
     Previously, balanced merger partners were formed as a result of the merger order in the queue being based on timing delay. However, different levels of hierarchy may be evaluated to determine if they can be merged together. 
     Referring now to  FIG. 23A , an exemplary pair-wise merge between a clock subtree  2310  with multiple levels of clock hierarchy is evaluated with a clocked element  2314  at the lowest level of the clock hierarchy. Due to the differences in level of clock signal hierarchy, simply merging clock subtree  2310  with the clocked element  2314  at a merger point  2301  would result in an imbalanced clock tree. Clock signal timing skew, the difference between worst case timing delay and best case timing delay of a clock signal at a given input slew, d late (slew)−d early (slew), is different for the clock path through the multiple levels of clock hierarchy of the clock subtree  2310  to its clocked elements and the direct clock path to the clocked element  2314 . 
     Referring now to  FIG. 23B , a merged clock subtree  2300  is formed with clock buffers  2322 A through  2322 C inserted into the clock path between the merger point  2301  and the clock input of the clocked element  2314 . The inserted clock buffers  2322 A- 2322 C provide three levels of clock buffering to balance out timing delays experienced in the hierarchy of the clock subtree  2310  and differences in clock signal timing skew. The clock subtree  2310  has three levels of clock buffering before the clock signal reaches the clocked elements at the bottom or lowest level of hierarchy in the clock subtree. 
     While the merged clock subtree  2300  with inserted clock buffers  2322 A- 2322 C may be now balanced for timing delay and clock signal timing skew, power consumption has been increased as a result of the addition of the three inserted clock buffers  2322 A- 2322 C. Thus, imbalanced merger partners (such as clock subtree  2310  and clocked element  2314 ) are usually avoided because the extra clock buffers added drive up power costs outweighing the balancing of the timing delays and clock signal timing skew. 
     As mentioned previously, the clocked elements may have feasible disable signals associated with them for which clock gating may be shared. Merger partners that can share clock gating are preferred. 
     Referring now to  FIG. 24A , a determination is to be made whether clock subtree  2410 A can be merged with clock subtree  2410 B. A feasible disable signal for the clock subtree  2410 A comprises the set of an X disable signal. Similarly, the set of feasible disable signals for the clock subtree  2410 B comprises the X disable signal. As a result of both clock subtrees  2410 A and  2410 B having a common feasible disable signal, the X disable signal, they can be readily merged together to form a merged clock subtree  2410 C at the merger point  2401 A. The merged clock subtree  2410 C has the X disable signal as a feasible disable signal. 
     However, it may be the case that a pair of clock subtrees has no common feasible disable signal but may still be worth merging together into a larger clock subtree. 
     Referring now to  FIG. 24B , clock subtrees  2410 A and  2410 D have no common clock gating because of they have no common feasible disable signal but different feasible disable signals comprising X and Y disable signals, respectively. If merged together, clock subtrees  2410 A and  2410 D would form a merged clock subtree  2410 E including non-common clock gates  2412 A and  2412 B between the merge point  2410 B and the respective clock subtrees  2410 A and  2410 D. As a result of this merger, clock subtree  2410 E would have no common disable signal. Its set of feasible disables is an empty set as shown. Regardless, merger costs of the merged clock subtree  2410 E needs to be evaluated against the merger benefit of reduced power consumption in each of clock subtrees  2410 A and  2410 D due to the gated clock signals into each. Each of the clock subtrees  2410 A and  2410 D has at least one or more clocked elements for which power can be saved if a gated clock signal reduces the switching frequency. 
     As indicated by equation 18, if the merger cost to actually implement the clock gates  2412 A- 2412 B is only twice the time as the switching power of a single clock gate, without any further power consumption due to substantial wiring or otherwise, then the merger of clock subtrees  2410 A and  2410 D into clock subtree  2410 E is worth implementing.
 
Merger Costs=2* E   sw   CG   Eq. 18
 
     However, it may be the case that the implementation cost of the clock gates is too much. Regardless, a determination may be made as to whether clock subtrees should instead be merged together without any adding any clock gates and gating clock signals. 
     Referring now to  FIG. 24C , a determination is made whether clock subtree  2410 A should to be merged together with clock subtree  2410 D, without the use of clock gating. In this case, the proposal is to merge the clock subtrees  2410 A and  2410 D into clock subtree  2410 F. The clock inputs of the clock subtrees  2410 A and  2410 D are directly coupled together at the merger point  2401 C. The power cost of this merger is a lost opportunity cost due to the lack of clock gating. That is, given the feasible disable signals, power consumption is not conserved due to the lack of clock gating. In this case, the cost is the sum of products of the probability that the disable signals would disable the switching energy in each of the clock subtrees  2410 A and  2410 D as evidenced by Equation 18. Because the switching energy cost is likely to be high, due to all the switching energy in each of the clock subtrees being summed together, the merger of clock subtrees  2410 A and  2410 D into clock subtree  2410 F is typically not worth implementing. However, with few clocked elements, the merger of clock subtrees  2410 A and  2410 D into clock subtree  2410 F may be the minimal cost merger.
 
Merger Costs=Prob CG ( X )* E   sw   subtree M   +Prob   CG ( Y )* E   sw   subtree N   Eq. 18
 
     The distance between a pair of clock subtrees may be considered in whether or not to implement a merged clock subtree. Pairs of clock subtrees that may be merger partners with shared clock gating may be located close together or further apart within the set of potential merger partners. 
     Referring now to  FIG. 25 , consider the exemplary floor plan  2500  with clock subtrees  2510 A,  2510 B, and  2510 C placed therein. A neighborhood boundary of merger partners  2550  includes the clock subtrees  2510 A- 2510 C. Typically, merger partners with the same feasible clock disable signal are preferred to be merged together. However, the proximity of clock subtrees is a factor to consider given the energy cost in switching a clock signal over a long wire route due to parasitic capacitance. Moreover, resistances that are encountered with a long wire route coupled with the parasitic capacitance that may introduce clock timing delays (RC time delay) and clock signal timing skew (difference in late and early timing delay) into the clock signal at clock end points. 
     Reference is now made to  FIGS. 26A and 26B . An evaluation is undertaken to determining whether or not to merge clock subtree  2510 A with clock subtree  2510 B or clock subtree  2510 C. As illustrated in  FIG. 25 , for example, clock subtrees  2510 A and  2510 B are close together. Clock subtrees  2510 A and  2510 C are significantly further apart in the comparison of their placement or clock input terminal locations as shown in  FIG. 25 . 
     In  FIG. 26A , an evaluation is to be made of merging clock subtrees  2510 A and  2510 B together as they are the closer merger partners. Clock subtree  2510 A has one feasible clock disable signal, for example, comprising the X disable signal. Clock subtree  2510 B has no feasible disable signal, for example, as indicated by an empty set. Thus, clock subtree  2510 B is to be constantly clocked by an ungated clock signal. 
     If clock subtrees  2510 A and  2510 B are to be merged together, a merged clock subtree  2610 C would be formed. The merged clock subtree  2610 C has an inserted clock gate  2612 A that is gated by the X disable signal on the clock path between the merger point  2601 A and the clock subtree  2510 A. Clock subtree  2510 B is directly coupled to the merger point  2601 A because it can&#39;t be gated by any disable signal. The merger cost of merging clock subtrees  2510 A and  2510 B together is essentially the switching energy cost in switching the clock gate  2612 A. A comparison of this merger cost is made with the merger cost of merging clock subtrees  2510 A and  2510 C together. 
     Referring now to  FIG. 26B , an evaluation is made of merging clock subtrees  2510 A and  2510 C together at merger point  2601 B to form a larger merged clock subtree  2610 E. The pair of clock subtrees  2510 A and  2510 C are further apart than the pair of clock subtrees  2510 A and  2510 B. However, the pair of clock subtrees  2510 A and  2510 C has a common feasible disable signal in this example, disable signal X. Thus, the clock subtrees  2510 A and  2510 C may be disabled by the same disable signal to conserve power. Moreover, they may presumably be gated by a clock gate much higher in the clock tree hierarchy, another possible factor to consider when selecting to implement the merged clock subtree. 
     However, the distance between the clock subtrees  2510 A and  2510 C causes parasitic resistances and/or capacitances as indicated by the respective passive impedances  2611 A, 2611 B between the merger point  2601 B and the clock subtrees  2510 A, 2510 C. Thus, the cost of the merged clock tree  2610 E is the energy cost in switching the extra wire impedances  2611 A and  2611 B. Because the energy used to switch a few gates is relatively infinitesimal, not much distance is required between clock subtrees  2510 A and  2510 C before the switching energy of the long wire is greater than the switching energy of the single clock gate  2612 A (see Equation 20). Thus, the clock subtrees  2510 A and  2510 B of the closer merger partners is typically preferred over distant merger partners, even though there is no common feasible disable signals and only noncommon clock gating. Clock buffering that may be inserted into the clock paths to compensate for the parasitic impedances  2611 A- 2611 B, only increases the preference for the closer merger partner.
 
 E   sw   wire   &gt;E   sw   CG   Eq. 20
 
     Referring now to  FIG. 26C , when large distances exist between merger partners, clock gating is preferably used in the lower level of clock hierarchy if there are common feasible disable signals. With common disable signals and distant merger partners, clock gate cloning may automatically be used to implement clock gates for multiple subtrees that are to be merged together. 
     Clock subtree  2610 C is to be merged with clock subtree  2510 C at the merger point  2601 C. The parasitic impedance  2611 B results from the long wire route from the clock subtree  2510 C to the merger point  2610  that is closer to the clock subtree  2510 C. Clock gate  2612 A of clock subtree  2610 C is cloned into clock gate  2612 B that is placed between the merger point  2601 C and the clock subtree  2510 C. In this case, the clock gates  2612 A- 2612 B can gate a clock signal to clock subtrees  2510 A, 2510 C to conserver power while the clock subtree  2510 B is constantly switched over a shorter clock signal path to further conserve power. 
     In  FIG. 9A , the optimizer-placer  913  of the clock tree planner  900  may evaluate simulation vectors for the feasible disable signals when multiple levels of clock gating are possible in a clock subtree. These simulation vectors may be correlated bit wise to actually determine if power is saved by a clock gate and its respective simulation vector. 
     Referring now to  FIG. 27 , an exemplary simulation vector  2701  for an X feasible disable signal is illustrated adjacent an exemplary simulation vector  2702  for a Y feasible disable signal. In one embodiment of the invention, a logical zero value at a given time period in a simulation vector indicates that a gated clock signal is allowed to switch while a logical one indicates that the gated clock signal is disabled and does not switch during the given time period. In another embodiment, the logical values may swap to indicate when a gated clock signal is actively switching and disabled. Simulation vectors  2701 - 2702  are examples of simulation vectors over simulated time periods of time period T 1  through time period T 10 . 
     Simulation vector  2701  for the X disable signal has a bit pattern of 0000000111 over time period T 1  through time period T 10 . Simulation vector  2702  for the Y disable signal has a bit pattern of 0011111111 over time period T 1  through time period T 10 . The last three bits of the X simulation vector in time periods T 8  through T 10  are logical one as are the last three bits of the Y simulation vector. If both X and Y disable signals are used to gate clock signals in the same clock path from a clock generator, the correlation between the last three bits indicates that the X disable signal provides no additional gating of a clock signal over that of the Y disable signal. In this case, a single clock gate responsive to the Y disable signal may be all that is need to conserver power in reducing the switching of the clocked elements at the lower levels of hierarchy in the clock tree. 
     Referring now to  FIG. 28 , an evaluation of whether clock subtrees  2810 A and  2810 B should be merged together is made. Clock subtree  2810 A has a set of feasible disable signals of consisting of X and Y disable signals. Clock subtree  2810 B has a set of feasible disable signals consisting of the Y disable signal. Thus, the Y disable signal is common to both clock subtrees  2810 A and  2810 B. However, the X disable signal is not common to both clock subtrees  2810 A and  2810 B. The X disable signal is uncommon disable signal. Assume that the exemplary simulation vectors for X and Y disable signals of  FIG. 27  are used to evaluate the merger of the clock subtrees  2810 A and  2810 B. 
     Assuming a maximum clock gating to achieve maximum power conservation, clock subtrees  2810 A and  2810 B may be merged together to form the merged clock subtree  2810 C. The merged clock subtree  2810 C includes a pair of clock gates  2810 A- 2810 B and clock subtrees  2810 A- 2810 B coupled together as shown. Clock gate  2812 A at a lower level of clock tree hierarchy is gated by the X disable signal. Clock gate  2812 B at an upper level of clock tree hierarchy is disabled by the Y disable signal. Clock gate  2812 B is an implied optimistic clock gate due to the disable signal Y being common to the feasible sets of disable signals for both of the clock subtrees  2810 A and  2810 B. 
     In  FIG. 27 , when comparing the simulation vectors  2701  and  2702  together, it can be seen that the simulation vector for the disabled signal X provides no clock gating that is not otherwise provided by the Y simulation vector. The X disable signal only disables the clock signal during time periods T 8 , T 9  and T 10 . The Y disable signal disables the clock signal during time periods T 8 , T 9  and T 10  as well. Thus, it is expected that the clock gate  2812 A does not provide much in power savings when added to the clock path between the merge point  2801  and the clock subtree  2810 A. 
     As discussed previously herein, Equations 14 and 15 may be used to determine the power consumption of the merged clock subtree  2810 C with and without the clock gate  2812 A. The power savings may then be compared with the additional power consumed by adding the clock gate  2812 A. Given that simulation vector  2701  indicates that the clock to clock subtree  2810 A is infrequently gated, it is likely that the vector-based calculation for power consumption correctly identifies that the addition of the clock gate  2812 A provides no power savings at all and may consume more when added. In which case, the non-common clock gate with the non-common disable signal X will be removed from the merged clock subtree  2810 C before the merged clock subtree is implemented. In a circuit with the same feasible disable signals but different simulation vectors, the gated clock  2812 A may indeed conserve power and remain in the merged clock subtree. 
     From this, it can be observed that the activity of a disable signal may forecast whether it is used to gate a clock gate or not and its position within the clock tree hierarchy. A relatively inactive disable signal, such as X disable and its simulation vector  2701 , needs to gate a large capacitor such as from a long wire route or a large clock subtree to offer a net savings in power consumption when its added to the clock tree. This foretells placement of a relatively inactive disable signal in the hierarchy so that when it is disabled, a greater amount of power consumption is reduced. In contrast, a relatively active disable signal can be used to gate smaller subtrees for a net power savings in comparison with the switching power added by the clock gate. This foretells that relatively active disable signals, that more often disables a clock signal, may be more commonly used at lower levels of the hierarchy if possible. 
     Integration with Clock Tree Synthesis 
     The resultant output of the clock tree planner  900  is a fully placed clock tree network including the physical placement of clock gates, clock buffers, enable gates, and clocked elements with clock signal routes or enable signal routes defined between each. However in some cases, the final implementation of the clock tree network may be better left to a clock tree synthesizer. 
     In one embodiment, the clock tree planner is integrated with a clock tree synthesizer to better perform the implementation of the clock tree network. In other embodiments, the clock tree planner is an independent ECAD tool. To prepare the clock tree plan for implementation by a clock tree synthesizer, the clock buffers and wire routing formed during the clock tree planning process may be ripped out. What remains is the physical placement of the clock gates, enable gates, and the clocked elements (e.g., the flip-flops) within a floor plan. The clock tree synthesizer may better insert clock buffers within the clock tree network. Wire routing of clock signals may then be performed by a router that can overcome blockages, better follow layout rules, and utilize the multiple layers of wire interconnect that may be available to route a clock signal. 
     Referring now to  FIG. 29 , a floor plan  2900  of an integrated circuit design is illustrated. The floor plan  2900  includes clock gates  2912 A- 2912 B, flip-flops  2914 A- 2914 E, and clock generator  102 R placed within the floor plan at their respective locations with X and Y coordinates. The floor plan  2900  is a physical gate topology that may be used by a clock tree synthesizer or integrated synthesizer. The floor plan of the clocked tree topology is passed on to the synthesizer for completion of the clock tree using a clock tree synthesizer and a router for interconnecting the clock signal wires along the clock paths to the clock gates, the clock buffers, and the clocked elements. 
     Methods of Physical Clock Topology Planning Processes 
     Referring now to  FIG. 31 , a flow chart diagram depicting an exemplary process  3100  associated with the physical clock topology planning process for designing integrated circuits is shown. The process  3100  begins with block  3101  and then goes to process block  3103 . 
     At process block  3103 , an initial placed netlist and a floorplan of an integrated circuit design may be received. The initial placed netlist includes placement of a plurality of flip flops and one or more clock enable logic gates (clock gates). The process then goes to process block  3105 . 
     At process block  3105 , the integrated circuit design is analyzed to determine potential or feasible enable signals that may be used to gate the clock signals and generate gated clock signals that are coupled into the clock input of the plurality of flip flops to reduce power consumption. The process then goes to process block  3107 . 
     At process block  3107 , simultaneously optimizing and placing the clock enable logic gates are placed and simultaneously optimized in clock paths towards the plurality of flip flops in order to generate the gated clock signals and reduce the switching frequency of the plurality of flip flops. The feasible enable or feasible disable signals are analyzed to determine the logic signals that may be used to gate the clock of the clock signals and clock the plurality of flip-flops efficiently in order to conserve power. 
     A static timing analysis on the placed netlist may be performed to determine any criticalities in the timing of the enable signals or disable signals that may be used to gate the clock signals to the plurality of flip flops. Insertion delay in the enable signal to a clock gate due to the addition of enable logic gates is optimized so that it is reduced to as little delay as possible. Physical placement of the enable gate with respect to the clock gate can be adjusted to optimize the insertion delay out of the enable signal timing. With the insertion of a clock gate in the clock signal path, the insertion timing delay of the clock signal down to the clock gate can be balanced with the timing delay of the gated clock signal from the clock gate down to the flip flop. If the fanout on a clock gate is large, the clock signal timing may be improved by splitting up the fanout and cloning the clock gate so that the timing delay from the clock gate to the flip flops is reduced. The optimizing process may further include merging at least two clock gates together and clocking the plurality of flip flops with fewer gated clock signals to eliminate redundant circuits and reduce power consumption thereby. 
     The optimizing process may further include grouping a plurality of flips flops together that are gated by a common enable signal into one or more clusters (flip flop clusters). The flip flops in each cluster can then be clocked by a single gated clock signal generated by a single clock gate. 
     Further optimization may be had by regrouping flip flops across two or more clusters that have a common enable signal in order to reduce wire lengths and wire congestion and reduce power consumption. 
     If enable timing is poor, the optimization process may include ungating flip flops that have poor enable timing. The optimization process may also ungate flip flops when power consumed by the clock gate that generates the gated clock signal for the flip flops is greater than the power saved by clocking the flip flops with the gated clock signal. 
     After the optimizing process, the process can then go to process block  3109 . 
     At process block  3109 , variations in timing of the clock edges in the gated clock signals are minimized to more efficiently clock the plurality of flip flops to capture data. Timing variations may be minimized by placing the clock gates with respect to placement of the flip flops to minimize skew variation and placing the enable gates with respect to the clock gates to generate enable signals to minimize the negative slack on enable signal paths to the clock gates. 
     Timing variations can also be minimized by building a skew balanced clock tree prototype including placement of virtual clock buffers. Timing variations can also be minimized by building partial tree models, also referred to as clock subtrees herein at each node of the clock tree to model power and timing delay tradeoffs. Then, the clock gates may also be placed in response to the skew balanced clock tree prototype and the partial tree models to maximize power savings. 
     Processes of the physical clock topology planning process may be repeated, such as processes  3101  through  3109 , for each clock subtree from the bottom of the clock tree network until the clock generator at the top of the clock tree network is reached. 
     Computing Apparatus 
     Referring now to  FIGS. 30A-30B , an exemplary computing system or apparatus  3000  is illustrated for designing an integrate circuit  3099 . The exemplary computing apparatus  3000  is adapted to perform electronic computer aided design (ECAD) and may be used to execute instructions or code of software programs to perform the processes or elements of the methods disclosed herein. The computing apparatus  3000  includes an input device  3001 , such as a keyboard  3006 , mouse  3004 , Ethernet or other communications port; an output device  3002 , such as a monitor, speakers, a printer, communications port, or a writeable media drive; a processor  3010 ; and a storage device  3012  coupled together as shown. The storage device  3012  may include one or more of a memory  3014 , such as a volatile memory like RAM, SDRAM, DDR, DDR2, DDR3; and a storage media  3015 . The storage media  3015  may comprise a non-volatile memory such as a hard drive, a solid-state drive, and the like. In some embodiments, as is known in the art, the storage media may be located on another computing device across a network (not shown). Instructions may be loaded from the storage media into the memory. The processor may retrieve instructions from the storage media or memory and execute the instructions to perform the operations described herein. 
     Included in the storage device  3012  is a set of processor executable instructions that, when executed by the processor  3010  configure the computing apparatus to provide the graphical user interface in a manner consistent with the methods disclosed herein. The clock tree planning user interface and its layout windows shown in the Figures may be displayed on the output device  3002 , such as a monitor or a display device, in response to processor or machine readable instructions. 
     In one embodiment of the invention, the clock topology planning software may be part of a logic synthesis software tool (e.g., the RTL Compiler tool) whose instructions are executed by the processor. In another embodiment of the invention, the clock topology planning software may be a stand alone software tool with instructions that are executed independently by the processor. 
     The computing system includes a processor, a memory, a removable media drive, and a hard disk drive. The processor within the computer executes instructions stored in a machine-readable storage device such as the hard disk drive or a removable storage device (e.g., an optical medium (compact disk (CD), digital video disk (DVD), etc.), a magnetic medium (magnetic disk, a magnetic tape, etc.), or a combination of both. 
     When implemented in software, the elements of the embodiments of the invention are essentially the program, code segments, or instructions to perform the necessary tasks. The program, code segments, or instructions can be stored in a processor readable medium or storage device that can be read and executed by a processor. The processor readable medium may include any medium that can store information. Examples of the processor readable medium include an electronic circuit, a semiconductor memory device, a read only memory (ROM), a flash memory, an erasable programmable read only memory (EPROM), a floppy diskette, a CD-ROM, an optical disk, and a magnetic disk. The program or code segments may be downloaded via computer networks such as the Internet, Intranet, etc. and stored in the processor readable medium or storage device. 
     When implemented as an electronic computer aided design (ECAD) system, the elements of the embodiments of the invention include one or more processor to execute the program, code segments, or instructions that may be stored in a processor readable medium or storage device to perform the tasks or functions of a method or process. The one or more processors may be specifically adapted to electronic computer aided design including processing logic that may comprise hardware (e.g., circuitry, dedicated logic, etc.), software, or a combination of both. 
     Some portions of the preceding detailed description may have been presented in terms of algorithms and symbolic representations that perform operations on data bits within a computer memory. These algorithmic descriptions and representations are the tools used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is here, and generally, conceived to be a self-consistent sequence of operations leading to a desired result. The operations are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities may take the form of electrical (e.g., current or voltage) or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, levels, elements, symbols, characters, terms, numbers, or the like. 
     It should be kept in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless specifically stated otherwise as apparent from the above discussion, it is appreciated that throughout the description, discussions utilizing terms such as “processing” or “computing” or “calculating” or “determining” or “displaying” or the like, refer to the action and processes of a computer system, processing logic, or similar electronic computing device, that automatically or semi-automatically manipulates and transforms data represented as physical (electronic) quantities within the computer system&#39;s registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage, transmission or display devices. 
     Additionally, the embodiments of the invention are not described with reference to any particular programming language. It will be appreciated that a variety of programming languages may be used to implement the teachings of the embodiments of the invention as described herein. 
     CONCLUSION 
     Thus, it is seen that a system, method, and apparatus for physically aware clock topology planning is disclosed. It will be appreciated that the embodiments of the invention can be practiced by other means than that of the above-described embodiments, which are presented in this description for purposes of illustration and not of limitation. The specification and drawings are not intended to limit the exclusionary scope of this patent document. It is noted that various equivalents for the particular embodiments discussed in this description may be practice by the claimed invention as well. That is, while specific embodiments of the invention have been described, it is evident that many alternatives, modifications, permutations and variations will become apparent in light of the foregoing description. Accordingly, it is intended that the claimed invention embrace all such alternatives, modifications and variations as fall within the scope of the appended claims. The fact that a product, process or method exhibits differences from one or more of the above-described exemplary embodiments does not mean that the product or process is outside the scope (literal scope and/or other legally-recognized scope) of the following claims.