Patent Publication Number: US-2015084058-A1

Title: Light emitting device grown on a silicon substrate

Description:
FIELD OF THE INVENTION 
     The present invention relates to a semiconductor light emitting device such as a III-nitride light emitting diode grown on a silicon substrate. 
     BACKGROUND 
     Semiconductor light-emitting devices including light emitting diodes (LEDs), resonant cavity light emitting diodes (RCLEDs), vertical cavity laser diodes such as surface-emitting lasers (VCSELs), and edge emitting lasers are among the most efficient light sources currently available. Materials systems currently of interest in the manufacture of high-brightness light emitting devices capable of operation across the visible spectrum include Group III-V semiconductors, particularly binary, ternary, and quaternary alloys of gallium, aluminum, boron, indium, and nitrogen, also referred to as III nitride materials. Typically, III-nitride light emitting devices are fabricated by epitaxially growing a stack of semiconductor layers of different compositions and dopant concentrations on a sapphire, silicon carbide, silicon, III-nitride, or other suitable substrate by metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), or other epitaxial techniques. The stack often includes one or more n-type layers doped with, for example, Si, formed over the substrate, one or more light emitting layers in an active region formed over the n-type layer or layers, and one or more p-type layers doped with, for example, Mg, formed over the active region. Electrical contacts are formed on the n- and p-type regions. 
       FIG. 1  illustrates a flip chip LED described in more detail in U.S. Pat. No. 7,256,483. The LED includes n-type layers  16 , an active layer  18 , and p-type layers  20  grown on a sapphire growth substrate (not shown). Portions of the p-layer  20  and active layer  18  are etched away during the LED forming process, and metal  50  (metallization layer plus bonding metal) contacts the n-layer  16  on the same side as the p-contact metal  24 . An underfill material  52  may be deposited in the voids beneath the LED to reduce thermal gradients across the LED, add mechanical strength to the attachment between the LED and the package substrate, and prevent contaminants from contacting the LED material. The n-metal  50  and p-metal  24  are bonded to the pads  22 A and  22 B, respectively, on a package substrate  12 . Contact pads  22 A and  22 B on package substrate  12  are connected to solderable electrodes  26 A and  26 B using vias  28 A and  28 B and/or metal traces. The growth substrate is removed, exposing a surface of n-type layer  16 . This surface is roughened for increased light extraction, for example by photo-electrochemical etching using a KOH solution. 
     SUMMARY 
     It is an object of the invention to provide a light emitting device grown on a silicon substrate that exhibits improved light extraction. 
     Embodiments of the invention include a semiconductor structure, the semiconductor structure including a III-nitride light emitting layer disposed between an n-type region and a p-type region, and an aluminum-containing layer. The aluminum-containing layer forms the top surface of the semiconductor structure. A transparent material is disposed on the aluminum-containing layer. A surface of the transparent material textured. 
     A method according embodiments of the invention includes growing a semiconductor structure on a substrate including silicon. The semiconductor substrate includes an aluminum-containing layer in direct contact with the substrate, and a III-nitride light emitting layer disposed between an n-type region and a p-type region. The method further includes removing the substrate. After removing the substrate, a transparent material is formed in direct contact with the aluminum-containing layer. The transparent material is textured. 
     Embodiments of the invention include a semiconductor structure including a III-nitride light emitting layer disposed between an n-type region and a p-type region. The semiconductor structure further includes an aluminum-containing layer. A porous III-nitride region is disposed between the aluminum-containing layer and the III-nitride light emitting layer. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  illustrates a flip chip LED with a roughened top surface. 
         FIG. 2  illustrates a III-nitride structure grown on a silicon substrate. 
         FIG. 3  illustrates the structure of  FIG. 2  attached to a support in a flip chip configuration. 
         FIG. 4  illustrates a portion of the top surface of a device including a roughened transparent material disposed on the semiconductor structure of  FIG. 3 . 
         FIG. 5  illustrates a portion of a semiconductor structure including a porous layer disposed between preparation layers and a device structure. 
         FIG. 6  illustrates a device including a waveguide-interupting region and a scattering structure. 
         FIG. 7  illustrates the growth of pores in a porous III-nitride layer. 
         FIG. 8  illustrates an apparatus for forming a porous III-nitride layer. 
     
    
    
     DETAILED DESCRIPTION 
     Though the examples below refer to III-nitride LEDs that emit blue or UV light, semiconductor light emitting devices besides LEDs such as laser diodes, and semiconductor light emitting devices made from other materials systems such as other III-V materials, III-phosphide, and III-arsenide materials may be used in embodiments of the invention. 
     III-nitride devices are often grown on sapphire or SiC substrates. These substrates can be removed, as described above, by etching, laser lift-off, or any other suitable technique. The III-nitride material exposed by removing these substrates is usually GaN, which can be easily roughened, for example by photoelectrochemical etching. 
     Silicon is an attractive substrate for growth of III-nitride devices due to its low cost, wide availability, and well-characterized electrical and thermal properties. Silicon has not been widely used as a substrate for growth of III-nitride devices due to material quality problems including cracking resulting from the lattice mismatch and thermal mismatch between III-nitride material and silicon. In addition, chemical interaction between Ga and Si requires that the first growth layer be essentially Ga-free. AlN is typically used as the first growth layer. The AlN first growth layer induces compressive strain in the GaN layers grown over the AlN first growth layer. The mismatch in thermal expansion between Si and GaN induces a tensile strain in the GaN during cool down of the wafer from the high growth temperature. By growing in a compressive state at high temperature the tensile strain generated by the cool down is accommodated. 
       FIG. 2  illustrates a III-nitride structure grown on a silicon substrate  30 . In the embodiments described herein, the silicon substrate  30  may be a silicon wafer or a composite substrate such as a silicon-on-insulator substrate where the growth surface (i.e. the top surface) is silicon. In order to reduce or eliminate the problems associated with the lattice and thermal mismatch, one or more preparation layers  32  are grown first on silicon substrate  30 . In  FIG. 2 , two preparation layers are illustrated, an AlN seed layer  34  and an AlGaN buffer layer  36 . AlN seed layer  34  may be, for example, an AlN layer less than 100 nm thick and deposited at a temperature below the growth temperature of GaN, which is often greater than 900° C. AlGaN buffer layer  36  may be, for example, a substantially single crystal layer grown at a high temperature, for example greater than 800° C. AlGaN buffer layer  36  may generate compressive stress in the III-nitride device structure  38 , particularly in n-type region  40 , which may reduce cracking in III-nitride device structure  38 . In some embodiments, AlGaN buffer layer  36  is omitted, and III-nitride device structure  38  is grown directly on AlN seed layer  34 . A III-nitride device structure  38 , including an n-type region  40 , a light emitting region  42 , and a p-type region  44 , is grown on preparation layers  32 . The III-nitride device structure  38  is described in more detail below. 
     The aluminum-containing preparation layers  32 , as described above, may reduce or eliminate problems associated with lattice and thermal mismatch. However, the aluminum-containing preparation layers  32  are problematic for several reasons. First, as described above in reference to  FIG. 1 , in some devices, the growth substrate is removed and the semiconductor structure exposed by removing the growth substrate is roughened or patterned to improve light extraction. Unlike GaN, which is often the III-nitride surface exposed by removing a conventional sapphire or SiC growth substrate, the AlN seed layer  34  described above is difficult to roughen with common techniques such as wet etching and photoelectrochemical etching. AlN must be roughened or removed by dry etching, which is an aggressive process that can damage the semiconductor structure and thereby reduce wafer yields. Second, the low index of refraction of the aluminum-containing preparation layers  32  (AlN has an index of refraction of ˜2.2), may cause light generated in the higher index, largely GaN (index of refraction of ˜2.4) device structure  38  to be lost to internal waveguiding along the interface between the aluminum-containing preparation layers  32  and the device structure  38 . 
     Embodiments of the invention may reduce or eliminate the problems associated with the aluminum-containing preparation layers in a III-nitride device grown on a Si substrate. 
       FIG. 6  illustrates a device according to embodiments of the invention. In the device illustrated in  FIG. 6 , the semiconductor structure is flipped relative to the growth direction of the III-nitride layers and n- and p-contacts  46  and  48  are formed on the semiconductor structure in a flip chip manner as is known in the art. In order to address the problem of the difficulty of roughening the aluminum-containing preparation layers for light extraction after removing the silicon substrate, the device illustrated in  FIG. 6  includes a scattering structure  72  formed on the preparation layers  32  after the silicon substrate  30  is removed. Scattering structure  72  may be, for example, a roughened silicon oxide or silicon nitride layer, as described below. In order to address the problem of waveguiding along the interface between the aluminum-containing preparation layers  32  and device structure  38 , the device of  FIG. 6  includes a waveguide-interrupting scattering structure  70  between the preparation layers  32  and device structure  38 . Scattering structure  70  may be, for example, a porous III-nitride layer or a roughened, patterned, or textured III-nitride layer, as described below. 
     The device illustrated in  FIG. 6  may be formed as follows. As described above in reference to  FIG. 2 , preparation layers  32  are grown first on silicon substrate  30 . After preparation layers  32  are grown, in some embodiments, optional scattering structure  70  is formed. 
     Scattering structure  70  may be a roughened, patterned, or textured III-nitride layer. In some embodiments, AlN seed layer  34  and AlGaN buffer layer  36  are grown, then the wafer is removed from the reactor and processed, for example by etching or mechanical techniques, to create a roughened, textured, or patterned non-planar surface on the AlGaN buffer layer  36 . The wafer is then returned to the growth chamber and the device structure  38 , described below, is grown over the non-planar surface of AlGaN buffer layer  36 . In devices where AlGaN buffer layer  36  is omitted, the surface of AlN seed layer  34  may be made non-planar before growth of the device structure  38 . The roughened, textured, or patterned surface may increase the amount of scattering at the interface, which may reduce the amount of light lost to waveguiding at the interface. 
     Scattering structure  70  may be a region of porous semiconductor material  60  formed between preparation layers  32  and device structure  38 , as illustrated in  FIG. 5 . Porous region  60  may increase the amount of scattering at the interface, which may reduce the amount of light lost to waveguiding at the interface. 
     Porous region  60  may be formed by any suitable technique, as is known in the art. For example, porous region  60  may be formed as follows: one or more aluminum-containing preparation layers  32  are grown on the Si growth substrate, as described above. A III-nitride layer  62  which will be made porous, often GaN but any suitable III-nitride material including but not limited to AlGaN and InGaN, is grown over the preparation layers  32 . An arrangement for making III-nitride layer  62  porous is illustrated in  FIG. 8 . Silver  81  is deposited by thermal evaporation in a region of the top surface of semiconductor structure  80 , which includes III-nitride layer  62 , preparation layers  32 , and silicon substrate  30 . The wafer  80  is placed on a Teflon surface  82 . Silver area  81  is contacted with a washer  84  and the semiconductor structure  80  is secured to Teflon surface  82  with a bolt  86 . In an anodic etching process, a platinum wires  88  serving as the anode and cathode are connected to a power supply  90 . The anode wire is connected to washer  84 . The wafer  80  and platinum wires  88  are immersed in a 2M NaOH or KOH solution  92 . A direct current is applied through the wire and wafer, for example at a density between 10 and 20 mA/cm 2 . Optional UV-illumination  94  is supplied by a 250 W mercury lamp. An appropriate porosity may require 10 to 60 minutes of processing, after which the lamp and the current source are switched off. Alternatively, platinum may be applied directly over the surface of the wafer, or different solutions such as KOH, fluoride acids, or CH 3 OH:HF:H 2 O 2  are used in a photo-electro-chemically driven process. The density and size of the porosity may be controlled by varying the concentration of the solution. A small pore layer may be produced with a low molarity solution (0.5% KOH). A large pore layer beneath the surface may be produced with a high molarity solution (2% KOH). 
       FIG. 7  illustrates the growth of pores  76 . The etching almost exclusively occurs at the tips of the electrolyte-semiconductor interface, at the ends of the pores  76 , such that the pores grow downward from the bottoms of the pores, as illustrated by the arrows in  FIG. 7 . By altering the solution during etching, a multilayer porosity may be created. 
     In porous region  60  as illustrated in  FIG. 7 , air voids  76  are formed in the III-nitride material. The voids may have a width  78  on the order of tens to hundreds of nm in size, for example greater than 10 nm in size in some embodiments and less than 500 nm in size in some embodiments. Nearest neighbor voids may have a spacing  80  on the order of tens to hundreds of nm apart, for example greater than 10 nm apart in some embodiments and less than 500 nm apart in some embodiments. Porous region  60 , as illustrated in  FIG. 5 , may have a thickness  82  greater than 0.02 μm thick in some embodiments and less than 3 μm thick in some embodiments. The percent porosity, defined as the volume of voids as a percent of the total volume of porous region  60 , may be greater than 20% in some embodiments, less than 80% in some embodiments, and greater than 50% in some embodiments. The pores may be, in some embodiments, substantially parallel tunnels that extend from the surface of porous region  60  toward preparation layers  32 . Scattering is caused by the difference in index of refraction between the III-nitride material and the ambient gas inside the pores. 
     The thickness of the III-nitride layer  62  which is made into porous region  60  may be, for example, greater than 0.5 μm in some embodiments, less than 5 μm in some embodiments, less than 2 μm in some embodiments, between 0.5 and 1.5 μm in some embodiments, and 1 μm in some embodiments. The III-nitride layer is often n-type GaN though in some embodiments it may be undoped or p-type material. The entire thickness of III-nitride layer  62  may be made porous in some embodiments, or less than the entire thickness of III-nitride layer  62  may be made porous in some embodiments, such that a nonporous region of III-nitride layer  62  is disposed between porous region  60  and preparation layers  32 . In some embodiments, porous region  60  extends into preparation layers  32 . After forming the porous region  60 , the structure is returned to a growth reactor and the device structure  38  is grown, as described below. 
     A III-nitride device structure  38  is grown over any of the structures described above: preparation layers  32  without roughening or texturing, roughened or textured preparation layers  32 , or porous region  60 . The device structure  38  includes a light emitting or active region  42 , often including at least one InGaN light emitting layer, sandwiched between n- and p-type regions  40  and  44 , each typically including at least one GaN layer. An n-type region  40  may be grown first and may include multiple layers of different compositions and dopant concentration including, for example, layers which may be n-type or not intentionally doped, and n- or even p-type device layers designed for particular optical, material, or electrical properties desirable for the light emitting region to efficiently emit light. A light emitting or active region  42  is grown over the n-type region  40 . Examples of suitable light emitting regions  42  include a single thick or thin light emitting layer, or a multiple quantum well light emitting region including multiple thin or thick light emitting layers separated by barrier layers. A p-type region  44  may then be grown over the light emitting region  42 . Like the n-type region  40 , the p-type region  44  may include multiple layers of different composition, thickness, and dopant concentration, including layers that are not intentionally doped, or n-type layers. The total thickness of all the layers grown on substrate  30 , including regions  32  and  38 , may be less than 10 μm in some embodiments and less than 6 μmm in some embodiments. 
     After growth of device structure  38 , a wafer including substrate  30  and the semiconductor structures  32  and  38  grown on the substrate may be further processed. For example, to form flip chip LEDs, a reflective metal p-contact is formed on the p-type region  44 . The device structure  38  is then patterned by standard photolithographic operations and etched to remove, for each LED, a portion of the entire thickness of the p-type region  44  and a portion of the entire thickness of the light emitting region  42 , to form a mesa which reveals a surface of the n-type region  40  on which a metal n-contact is formed. The mesa and p- and n-contacts may be formed in any suitable manner. Forming the mesa and p- and n-contacts is well known to a person of skill in the art. 
     The wafer may then be singulated into individual devices which are individually attached to supports, or attached to a support on a wafer scale, before singulation. The support is a structure that mechanically supports the semiconductor structure. Examples of suitable supports include an insulating or semi-insulating wafer with conductive vias for forming electrical connections to the semiconductor structure, such as a silicon wafer, thick metal bonding pads formed on the semiconductor structure, for example by plating, or a ceramic, metal, or any other suitable mount. After attaching the semiconductor structure to a support, before or after singulating, the growth substrate may be removed from the III-nitride structure. 
       FIG. 3  illustrates a flip chip device attached to a support, with the growth substrate removed. The device structure  38  is attached to support  50  through metal n-contact  46  and metal p-contact  48 . The n- and p-contacts may be electrically isolated by a gap  47 , which may be filled with air, ambient gas, or a solid insulating material such as an oxide of silicon, silicone, or epoxy. The surface of grown semiconductor material exposed by removing the silicon growth substrate  30  is the surface of AlN seed layer  34 . Because one or both of contacts  46  and  48  are reflective, a majority of light escapes the structure of  FIG. 3  through the top and side surfaces. 
     In order to avoid the damage caused by roughening, texturing, or removing the AN seed layer exposed after removing the growth substrate as described above, in some embodiments a layer of roughened material is formed on the surface of the semiconductor structure revealed by removing the growth substrate.  FIG. 4  illustrates a portion of a device according to embodiments of the invention. As described above, when the growth substrate is removed, the surface of AlN seed layer  34  is exposed. In the structure illustrated in  FIG. 4 , a layer  56  of optically transparent material that has an index of refraction that is close to or matches the index of refraction of AlN seed layer  34  is formed over the surface of AlN seed layer  34 . The top surface  54  of layer  56  is roughened to enhance light extraction from the semiconductor structure. 
     Transparent material  56  is selected to be transparent to light emitted by the light emitting region, such that absorption or scattering by transparent material  52  is nominal. The refractive index of transparent material  56  is at least 1.9 in some embodiments, at least 2.0 in some embodiments, and at least 2.1 in some embodiments, such that the refractive index of transparent material  56  is close to the refractive indices of AN seed layer  34  (refractive index of 2.2) and any GaN layers in device structure  38  (refractive index of 2.4). Examples of suitable transparent materials  56  include non-III-nitride materials, oxides of silicon, nitrides of silicon, oxynitrides of silicon, SiO 2 , Si 3 N 4 , SiO x N y , and mixtures thereof. Transparent material  56  may be a multi-layer structure in some embodiments. Transparent material  56  may be formed by, for example, chemical vapor deposition or any other suitable technique. 
     The surface  54  of transparent material  56  may be patterned, roughened, or textured by any suitable technique or combination of techniques including, for example, dry or wet etching, and dry or wet etching utilizing self-masking, patterned masking, lithographic patterning, microsphere patterning, or any other suitable masking technique. For example, a Si 3 N 4  layer  56  may be patterned with random or regular features using known photolithography techniques such as i-line photoresist patterning, followed by CHF 3  plasma etching, as is known in the art. In some embodiments, the patterning, texturing, or roughening extends through an entire thickness of transparent material  56  to the surface of seed layer  34 . 
     In some embodiments, one or more additional, optional structures may be formed over the roughened surface  54  of transparent layer  56 . For example, one or more wavelength converting materials, optics, filters such as dichroic filters, or other structures may be disposed over transparent layer  56 , in contact with transparent layer  56  or spaced apart from transparent layer  56 . 
     Having described the invention in detail, those skilled in the art will appreciate that, given the present disclosure, modifications may be made to the invention without departing from the spirit of the inventive concept described herein. For example, different elements of different embodiments may be combined to form new embodiments. Therefore, it is not intended that the scope of the invention be limited to the specific embodiments illustrated and described.