Patent Publication Number: US-11031470-B2

Title: Semiconductor device and manufacturing method thereof

Description:
PRIORITY CLAIM AND CROSS-REFERENCE 
     The present application is a Divisional Application of the U.S. Application Ser. No. 15/795,519, filed Oct. 27, 2017, now U.S. Pat. No. 10,535,737, issued on Jan. 14, 2020, which is herein incorporated by reference in its entirety. 
    
    
     BACKGROUND 
     The semiconductor integrated circuit (IC) industry has experienced rapid growth. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process increases production efficiency and lowers associated costs. 
     Such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are desired. For example, a three dimensional transistor, such as a fin-like field-effect transistor (FinFET), has been introduced to replace a planar transistor. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. 
         FIGS. 1A to 17C  illustrate a method of manufacturing a semiconductor device at various stages in accordance with some embodiments. 
         FIGS. 18A to 36C  illustrate a method of manufacturing a semiconductor device at various stages in accordance with some embodiments. 
         FIGS. 37A to 37C  illustrate a method of manufacturing a semiconductor device at various stages in accordance with some embodiments. 
         FIGS. 38A to 38C  illustrate a method of manufacturing a semiconductor device at various stages in accordance with some embodiments. 
     
    
    
     DETAILED DESCRIPTION 
     The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. 
     Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature&#39;s relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. 
     The fins may be patterned by any suitable method. For example, the fins may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fins. 
       FIGS. 1A to 17C  illustrate a method of manufacturing a semiconductor device at various stages in accordance with some embodiments. 
     Reference is made to  FIGS. 1A and 1B , in which  FIG. 1A  is a top view of one stage of manufacturing a semiconductor device, and  FIG. 1B  is a cross-sectional view along line B-B of  FIG. 1A . A substrate  100  is provided. The substrate  100  may be a bulk silicon substrate. Alternatively, the substrate  100  may include an elementary semiconductor, such as silicon (Si) or germanium (Ge) in a crystalline structure; a compound semiconductor, such as silicon germanium (SiGe), silicon carbide (SiC), gallium arsenic (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and/or indium antimonide (InSb); or combinations thereof. Possible substrates  100  also include a silicon-on-insulator (SOI) substrate. SOI substrates are fabricated using separation by implantation of oxygen (SIMOX), wafer bonding, and/or other suitable methods. 
     The substrate  100  may also include various doped regions. The doped regions may be doped with p-type dopants, such as boron or BF 2 ; n-type dopants, such as phosphorus or arsenic; or combinations thereof. The doped regions may be formed directly on the substrate  100 , in a P-well structure, in an N-well structure, in a dual-well structure, and/or using a raised structure. The substrate  100  may further include various active regions, such as regions configured for an N-type metal-oxide-semiconductor transistor device and regions configured for a P-type metal-oxide-semiconductor transistor device. 
     Reference is made to  FIGS. 2A and 2B , in which  FIG. 2A  is a top view of one stage of manufacturing a semiconductor device, and  FIG. 2B  is a cross-sectional view along line B-B of  FIG. 2A . A plurality of first semiconductor layers  101  and second semiconductor layers  102  are formed over the substrate  100 , in which the first semiconductor layers  101  and second semiconductor layers  102  are alternately formed such that the first semiconductor layers  101  and second semiconductor layers  102  are alternately stacked on each other. It is understood that the numbers of layers of the first semiconductor layers  101  and second semiconductor layers  102  are merely used to explained, and the present disclosure is not limited thereto. 
     The first semiconductor layers  101  and the second semiconductor layers  102  may be formed by chemical vapor deposition (CVD), molecular beam epitaxy (MBE), or other suitable process(es). In some embodiments, the first semiconductor layers  101  are formed in a temperature higher than about 750° C., and the thickness of the first semiconductor layers  101  is in a range of about 5 nm to about 13.5 nm. In some other embodiments, the first semiconductor layers  101  is formed in a temperature lower than about 650° C., and the thickness of the first semiconductor layers  101  is in a range of about 3 nm to about 16.5 nm. 
     The first semiconductor layers  101  and the second semiconductor layers  102  have different materials and/or components, such that the first semiconductor layers  101  and the second semiconductor layers  102  have different etching rates. In some embodiments, the first semiconductor layers  101  are made from SiGe. The germanium percentage (atomic percentage) of the first semiconductor layers  101  is in the range between about 10 percent and about 20 percent, while higher or lower germanium percentages may be used. It is appreciated, however, that the values recited throughout the description are examples, and may be changed to different values. For example, the first semiconductor layers  101  may be Si 0.8 Ge 0.2  or Si 0.9 Ge 0.1 , the proportion between Si and Ge may vary from embodiments, and the disclosure is not limited thereto. The second semiconductor layers  102  may be pure silicon layers that are free from germanium. The second semiconductor layers  102  may also be substantially pure silicon layers, for example, with a germanium percentage lower than about 1 percent. In some other embodiments, the second semiconductor layers  102  and the substrate  100  may be made from the same material or different materials. In some embodiments, the first semiconductor layers  101  may be doped for tuning the threshold voltage (Vt), and the Vt of the first semiconductor layers  101  is close to the Vt of second semiconductor layers  102  while increasing the dopant concentration of the first semiconductor layers  101 . 
     Reference is made to  FIGS. 3A and 3B , in which  FIG. 3A  is a top view of one stage of manufacturing a semiconductor device, and  FIG. 3B  is a cross-sectional view along line B-B of  FIG. 3A . A patterned mask  107  is formed over the first semiconductor layers  101  and the second semiconductor layers  102  to define a fin region in the following process. In some embodiments, the patterned mask  107  is in contact with one of the second semiconductor layers  102 . The patterned mask  107  may be formed from, for example, Si 3 N 4  or other suitable materials. 
     Reference is made to  FIGS. 4A and 4B , in which  FIG. 4A  is a top view of one stage of manufacturing a semiconductor device, and  FIG. 4B  is a cross-sectional view along line B-B of  FIG. 4A . The substrate  100 , the first semiconductor layers  101 , and the second semiconductor layers  102  are patterned with the mask  107 . After the patterning, the patterned substrate  100  includes a protrusion portion  1001 , and the patterned first semiconductor layers  101  and the patterned second semiconductor layers  102  are disposed over the protrusion portion  1001 , in which the bottommost layer of the patterned first semiconductor layers  101  is in contact with the protrusion portion  1001 . In some embodiments, the protrusion portion  1001 , the patterned first semiconductor layers  101 , and the patterned second semiconductor layers  102  have substantially the same width. The patterned first semiconductor layers  101  and the patterned second semiconductor layers  102  extend along a direction D 1 . 
     The patterning may be performed using suitable process, such as etching. In some embodiments, the etching includes anisotropic etching, such as dry etching. Dry etching processes include a biased plasma etching process that uses a chlorine-based chemistry. Other dry etchant gasses include CF 4 , NF 3 , SF 6 , and He. Dry etching may also be performed anisotropically using such mechanisms as DRIE (deep reactive-ion etching). In some embodiments, the power of the dry etching process is about 150 Watt. 
     Reference is made to  FIGS. 5A and 5B , in which  FIG. 5A  is a top view of one stage of manufacturing a semiconductor device, and  FIG. 5B  is a cross-sectional view along line B-B of  FIG. 5A . An isolation structure  108  is formed over the substrate  100  and adjacent to the protrusion portion  1001  of the substrate  100 . The isolation structure  108 , which acts as a shallow trench isolation (STI) around the first and the second semiconductor layers  101  and  102  may be formed by performing a chemical vapor deposition (CVD), such as high density plasma CVD (HDPCVD), to form a dielectric material. Following a chemical mechanical polish (CMP) process is performed to level the top surface of the dielectric material with the top surface of the mask  107 , and the dielectric material is etched back to form the isolation structure  108 . In yet some other embodiments, the isolation structure  108  is an insulator layer of a SOI wafer. 
     Reference is made to  FIGS. 6A to 6C , in which  FIG. 6A  is a top view of one stage of manufacturing a semiconductor device,  FIG. 6B  is a cross-sectional view along line B-B of  FIG. 6A , and  FIG. 6C  is a cross-sectional view along line C-C of  FIG. 6A . A dummy gate structure  109  is formed over the substrate  100  and crossing the first semiconductor layers  101  and the second semiconductor layers  102  along a direction D 2 , in which the direction D 2  is different from the direction D 1 . For example, the direction D 2  is substantially vertical to the direction D 1 . 
     In some embodiments, the dummy gate structure  109  includes a dummy gate electrode and a gate dielectric underlying the dummy gate electrode. The dummy gate electrode may include polycrystalline-silicon (poly-Si) or poly-crystalline silicon-germanium (poly-SiGe). Further, the dummy gate electrode may be doped poly-silicon with uniform or non-uniform doping. The gate dielectric may include, for example, silicon dioxide, silicon nitride, a high-k dielectric material such as metal oxides, metal nitrides, metal silicates, transition metal-oxides, transition metal-nitrides, transition metal-silicates, oxynitrides of metals, metal aluminates, zirconium silicate, zirconium aluminate, or combinations thereof. In various examples, the gate dielectric may be deposited by an ALD process, a CVD process, a subatmospheric CVD (SACVD) process, a flowable CVD process, a PVD process, or other suitable process. By way of example, the gate dielectric may be used to prevent damage to the first semiconductor layers  101  and the second semiconductor layers  102  by subsequent processing (e.g., subsequent formation of the dummy gate electrode). 
     Reference is made to  FIGS. 7A to 7C , in which  FIG. 7A  is a top view of one stage of manufacturing a semiconductor device,  FIG. 7B  is a cross-sectional view along line B-B of  FIG. 7A , and  FIG. 7C  is a cross-sectional view along line C-C of  FIG. 7A . An isolation material  110  is formed over the substrate  100 . The isolation material  110  may be formed by suitable process, such as CVD or PVD. Further, a planarization process, such as chemical mechanical polishing (CMP), may be performed to the isolation material  110  until the dummy gate structure  109  is exposed, such that top surfaces of the isolation material  110  and the dummy gate structure  109  are substantially coplanar. In some embodiments, the isolation material  110  may be SiOC, or other suitable materials. 
     Reference is made to  FIGS. 8A to 8C , in which  FIG. 8A  is a top view of one stage of manufacturing a semiconductor device,  FIG. 8B  is a cross-sectional view along line B-B of  FIG. 8A , and  FIG. 8C  is a cross-sectional view along line C-C of  FIG. 8A . The isolation material  110  is partially removed by, for example, dry etching. Accordingly, the mask  107  is exposed from the isolation material  110  and the dummy gate structure  109 . In some embodiments, the top surface of the remained isolation material  110  is substantially level with the top surface of the mask  107 . 
     Reference is made to  FIGS. 9A to 9C , in which  FIG. 9A  is a top view of one stage of manufacturing a semiconductor device,  FIG. 9B  is a cross-sectional view along line B-B of  FIG. 9A , and  FIG. 9C  is a cross-sectional view along line C-C of  FIG. 9A . The mask  107  is patterned using the dummy gate structure  109  as a mask. After the mask  107  is patterned, the topmost second semiconductor layer  102  is exposed from the isolation material  110  and the dummy gate structure  109 . The mask  107  may be patterned by, for example, dry etching. In some embodiments, the etchants may be CHF 3  and Ar. The isolation material  110  may also be patterned during patterning the mask  107 . In other words, the mask  107  and the isolation material  110  may be patterned at the same time. 
     Reference is made to  FIGS. 10A to 10C , in which  FIG. 10A  is a top view of one stage of manufacturing a semiconductor device,  FIG. 10B  is a cross-sectional view along line B-B of  FIG. 10A , and  FIG. 10C  is a cross-sectional view along line C-C of  FIG. 10A . Plural gate spacers  111  are formed on opposite sidewalls of the dummy gate structure  109  and the mask  107 . In some embodiments, the gate spacers  111  include single or multiple layers. The gate spacers  111  can be formed by blanket depositing one or more dielectric layer(s) (not shown) on the previously formed structure. The dielectric layer(s) may include silicon nitride (SiN), oxynitride, silicon carbon (SiC), silicon oxynitride (SiON), oxide, and the like. The gate spacers  111  may be formed by methods such as CVD, plasma enhanced CVD, sputter, or the like. The gate spacers  111  may then be patterned, such as by one or more etch processes to remove horizontal portions of the gate spacers  111  from the horizontal surfaces of the structure. 
     Reference is made to  FIGS. 11A to 11C , in which  FIG. 11A  is a top view of one stage of manufacturing a semiconductor device,  FIG. 11B  is a cross-sectional view along line B-B of  FIG. 11A , and  FIG. 11C  is a cross-sectional view along line C-C of  FIG. 11A . The first semiconductor layers  101  and the second semiconductor layers  102  are patterned using the dummy gate structure  109  and the gate spacers  111  as a mask. The first semiconductor layers  101  and the second semiconductor layers  102  may be patterned by suitable process, such as etching. After the patterning, recesses R 1  are formed over the substrate  100 , in which one of the recesses R 1  is defined by the isolation material  110  and the semiconductor layers  101  and  102 . Then, plural source/drain structures  112  are formed in the recesses R 1 , respectively. Accordingly, the source/drain structures  112  are in contact with the isolation material  110 , and the semiconductor layers  101  and  102 . 
     In some embodiments, the source/drain structures  112  may be epitaxy structures, and may also be referred to as epitaxy structures  112 . The source/drain structures  112  may be formed using one or more epitaxy or epitaxial (epi) processes, such that Si features, SiGe features, and/or other suitable features can be formed in a crystalline state on the substrate  100 . In some embodiments, lattice constants of the source/drain structures  112  are different from lattice constants of the semiconductor layers  101  and  102 , such that the semiconductor layers  101  and  102  are strained or stressed to enable carrier mobility of the semiconductor device and enhance the device performance. In some embodiments, the source/drain structures  112  may include semiconductor material such as germanium (Ge) or silicon (Si); or compound semiconductor materials, such as gallium arsenide (GaAs), aluminum gallium arsenide (AlGaAs), silicon germanium (SiGe), silicon carbide (SiC), or gallium arsenide phosphide (GaAsP). 
     The epitaxy processes include CVD deposition techniques (e.g., vapor-phase epitaxy (VPE) and/or ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy, and/or other suitable processes. The epitaxy process may use gaseous and/or liquid precursors, which interact with the composition of the substrate  100  (e.g., silicon). The source/drain structures  112  may be in-situ doped. The doping species include P-type dopants, such as boron or BF 2 ; N-type dopants, such as phosphorus or arsenic; and/or other suitable dopants including combinations thereof. If the source/drain structures  112  are not in-situ doped, a second implantation process (i.e., a junction implant process) is performed to dope the source/drain structures  112 . One or more annealing processes may be performed to activate the source/drain structures  112 . The annealing processes include rapid thermal annealing (RTA) and/or laser annealing processes. 
     Reference is made to  FIGS. 12A to 12C , in which  FIG. 12A  is a top view of one stage of manufacturing a semiconductor device,  FIG. 12B  is a cross-sectional view along line B-B of  FIG. 12A , and  FIG. 12C  is a cross-sectional view along line C-C of FIG.  12 A. An isolation material  120  is formed over the substrate  100 . In some embodiments, the material of the isolation material  120  is the same as the isolation material  110 . Further, a planarization process, such as chemical mechanical polishing (CVD), may be performed to the isolation material  120  until the dummy gate structure  109  is exposed, such that top surfaces of the isolation material  120 , the dummy gate structure  109 , and the gate spacers  111  are substantially coplanar. 
     Reference is made to  FIGS. 13A and 13B , in which  FIG. 13A  is a top view of one stage of manufacturing a semiconductor device, and  FIG. 13B  is a cross-sectional view along line B-B of  FIG. 13A . In some embodiments, a replacement gate (RPG) process scheme is employed. In a RPG process scheme, a dummy polysilicon gate (the dummy gate electrode in this case) is formed first and is replaced later by a metal gate after high thermal budget processes are performed. In some embodiments, the dummy gate electrode is removed to form an opening with the spacers  111  as its sidewall. In some other embodiments, the gate dielectric is removed as well. Alternatively, in some embodiments, the dummy gate electrode is removed while the gate dielectric retains. The dummy gate electrode (and the gate dielectric) may be removed by dry etch, wet etch, or a combination of dry and wet etch. For example, a wet etch process may include exposure to a hydroxide containing solution (e.g., ammonium hydroxide), deionized water, and/or other suitable etchant solutions. 
     Reference is made to  FIGS. 14A and 14B , in which  FIG. 14A  is a top view of one stage of manufacturing a semiconductor device, and  FIG. 14B  is a cross-sectional view along line B-B of  FIG. 14A . The first semiconductor layers  101  (shown in  FIG. 13B ) are partially removed by suitable process, such as isotropic etching by using CF 4  as etchants. In some embodiments, the etching process may include etching selectivity, such that the second semiconductor layers  102  remain the same during the etching process. The remained first semiconductor layers  101  are labeled as  101 ′ in the following descriptions. After the etching process, a plurality of recesses R 2  are formed between two adjacent second semiconductor layers  102 , in which a bottommost recess R 2  is formed between one second semiconductor layer  102  and the substrate  100 . From other perspectives, some of the recesses R 2  are defined by two second semiconductor layers  102  and the first semiconductor layer  101 ′ therebetween. In some embodiments, the etching rate may be controlled (or tuned) such that the first semiconductor layers  101 ′ are kept between and in contact with two adjacent second semiconductor layers  102 , and the bottommost first semiconductor layer  101 ′ is kept between and in contact with one second semiconductor layer  102  and the substrate  100 . 
     Reference is made to  FIGS. 15A and 15B , in which  FIG. 15A  is a top view of one stage of manufacturing a semiconductor device, and  FIG. 15B  is a cross-sectional view along line B-B of  FIG. 15A . The mask  107  (shown in  FIGS. 14A and 14B ) is removed. In some embodiments, the mask  107  may be removed by suitable process, such as wet etching using HF as etchants. In some embodiments, the isolation structure  108  may be partially removed during the removal of the mask  107 . 
     Reference is made to  FIGS. 16A to 16C , in which  FIG. 16A  is a top view of one stage of manufacturing a semiconductor device,  FIG. 16B  is a cross-sectional view along line B-B of  FIG. 16A , and  FIG. 16C  is a cross-sectional view along line C-C of  FIG. 16A . A gate structure  115  is formed crossing and in contact with the first semiconductor layers  101 ′ and the second semiconductor layers  102 . A portion of the gate structure  115  is formed into the recesses R 2  (shown in  FIG. 15B ) and in contact with the remained first semiconductor layers  101 ′. 
     The gate structure  115  includes a gate dielectric  113  conformally formed on exposed surfaces of the first semiconductor layers  101 ′ and the second semiconductor layers  102  and a gate metal  114  formed over the gate dielectric  113 . The gate dielectric  113 , as used and described herein, includes dielectric materials having a high dielectric constant, for example, greater than that of thermal silicon oxide (˜ 3 . 9 ). The gate metal  114  may include a metal, metal alloy, and/or metal silicide. 
     In some embodiments, the gate metal  114  included in the gate structure  115  may include a single layer or alternatively a multi-layer structure, such as various combinations of a metal layer with a work function to enhance the device performance (work function metal layer), liner layer, wetting layer, adhesion layer and a conductive layer of metal, metal alloy or metal silicide. For example, the gate metal  114  formed may also include capping layer(s), work function metal layer(s), fill layer(s), and/or other suitable layers that are desirable in a metal gate structure. A work function metal layer included in the gate metal  114  may be an n-type or p-type work function layer. Exemplary p-type work function metals include TiN, TaN, Ru, Mo, Al, WN, ZrSi 2 , MoSi 2 , TaSi 2 , NiSi 2 , WN, other suitable p-type work function materials, or combinations thereof. Exemplary n-type work function metals include Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable n-type work function materials, or combinations thereof. The work function layer may include a plurality of layers. The work function layer(s) may be deposited by CVD, PVD, electro-plating and/or other suitable process. In some embodiments, the capping layer included in the gate metal  114  may include refractory metals and their nitrides (e.g. TiN, TaN, W 2 N, TiSiN, TaSiN). The cap layer of the gate metal  114  may be deposited by PVD, CVD, metal-organic chemical vapor deposition (MOCVD) and ALD. In some embodiments, the fill layer included in the gate metal  114  may include tungsten (W). The metal layer may be deposited by ALD, PVD, CVD, or other suitable process. 
     In some embodiments, the gate dielectric  113  may include a dielectric material such as silicon oxide (SiO 2 ), HfSiO, and/or silicon oxynitride (SiON). The interfacial layer may be formed by chemical oxidation, thermal oxidation, ALD, CVD, and/or other suitable method. The gate dielectric  113  may include a high-K dielectric layer such as hafnium oxide (HfO 2 ). Alternatively, the gate dielectric  113  may include other high-K dielectrics, such as TiO 2 , HfZrO, Ta 2 O 3 , HfSiO 4 , ZrO 2 , ZrSiO 2 , LaO, AlO, ZrO, TiO, Ta 2 O 5 , Y 2 O 3 , SrTiO 3  (STO), BaTiO 3  (BTO), BaZrO, HfZrO, HfLaO, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba,Sr)TiO 3  (BST), Al 2 O 3 , Si 3 N 4 , oxynitrides (SiON), combinations thereof, or other suitable material. The gate dielectric  113  may be formed by ALD, PVD, CVD, oxidation, and/or other suitable methods. 
     Reference is made to  FIGS. 17A to 17C , in which  FIG. 17A  is a top view of one stage of manufacturing a semiconductor device,  FIG. 17B  is a cross-sectional view along line B-B of  FIG. 17A , and  FIG. 17C  is a cross-sectional view along line C-C of  FIG. 17A . A planarization process, such as CMP, is performed to the gate structure  115  until the isolation material  120  is exposed. 
     The first semiconductor layers  101 ′ and the second semiconductor layers  102  may be collectively referred to as a channel structure  103 . Further, the first semiconductor layers  101 ′ and the second semiconductor layers  102  may be referred to as the first portions  101 ′ and the second portions  102  of the channel structure  103 , in which the first portions  101 ′ and the second portions  102  are made from different materials. The width W 1  of the first portions  101 ′ is smaller than width W 2  of the second portions  102  along the direction D 1 , and the width W 3  of the protrusion portion  1001  of the substrate  100  is substantially equal to the width W 2  of the second portions  102  along the direction D 1 . The gate structure  115  crosses the channel structure  103  along the direction D 2 . In some embodiments, the first portions  101 ′ have a thickness T 1 , in which the thickness T 1  is larger than the width W 1 . 
       FIGS. 18A to 36C  illustrate a method of manufacturing a semiconductor device at various stages in accordance with some embodiments. Some relevant structural and manufacturing details of the semiconductor device of  FIGS. 18A to 36C  are similar to the semiconductor device of  FIGS. 1A to 14B , and, therefore, similar descriptions in this regard will not be repeated hereinafter. 
     Reference is made to  FIGS. 18A and 18B , in which  FIG. 18A  is a top view of one stage of manufacturing a semiconductor device, and  FIG. 18B  is a cross-sectional view along line B-B of  FIG. 18A . A substrate  200  is provided. The structure and material of the substrate  200  may be the same as or similar to the substrate  100  of  FIGS. 1A and 1B . 
     Reference is made to  FIGS. 19A and 19B , in which  FIG. 19A  is a top view of one stage of manufacturing a semiconductor device, and  FIG. 19B  is a cross-sectional view along line B-B of  FIG. 19A . A plurality of first semiconductor layers  201  and second semiconductor layers  202  are formed over the substrate  200 , in which the first semiconductor layers  201  and second semiconductor layers  202  are alternately formed such that the first semiconductor layers  201  and second semiconductor layers  202  are alternately stacked on each other. The structure and material of the first semiconductor layers  201  and the second semiconductor layers  202  may respectively be the same as or similar to the first semiconductor layers  101  and second semiconductor layers  102  of  FIGS. 2A and 2B . 
     Reference is made to  FIGS. 20A and 20B , in which  FIG. 20A  is a top view of one stage of manufacturing a semiconductor device, and  FIG. 20B  is a cross-sectional view along line B-B of  FIG. 20A . A patterned mask  207  is formed over the first semiconductor layers  201  and the second semiconductor layers  202  to define a fin region in the following process. The structure and material of the patterned mask  207  may be the same as or similar to the patterned mask  107  of  FIGS. 3A and 3B . 
     Reference is made to  FIGS. 21A and 21B , in which  FIG. 21A  is a top view of one stage of manufacturing a semiconductor device, and  FIG. 21B  is a cross-sectional view along line B-B of  FIG. 21A . The substrate  200 , the first semiconductor layers  201 , and the second semiconductor layers  202  are patterned with the mask  207 . The patterned first semiconductor layers  201  and the patterned second semiconductor layers  202  extend along a direction D 1 . 
     Reference is made to  FIGS. 22A and 22B , in which  FIG. 22A  is a top view of one stage of manufacturing a semiconductor device, and  FIG. 22B  is a cross-sectional view along line B-B of  FIG. 22A . An isolation structure  208  is formed over the substrate  200  and adjacent to the protrusion portion  2001  of the substrate  200 . The isolation structure  208  may be formed by depositing a dielectric material over the substrate and following with a planarization process until the mask  207  is exposed. In some embodiments, the isolation structure  208  is in contact with the first semiconductor layers  201 , the second semiconductor layers  202 , and the mask  207 . The material of the isolation structure  208  may be the same as or similar to the isolation structure  108  of  FIGS. 5A and 5B . 
     Reference is made to  FIGS. 23A and 23B , in which  FIG. 23A  is a top view of one stage of manufacturing a semiconductor device, and  FIG. 23B  is a cross-sectional view along line B-B of  FIG. 23A . The mask  207  is patterned to form an opening O 1 . The opening O 1  exposes a middle portion of the second semiconductor layers  202  along the direction D 1 . 
     Reference is made to  FIGS. 24A and 24B , in which  FIG. 24A  is a top view of one stage of manufacturing a semiconductor device, and  FIG. 24B  is a cross-sectional view along line B-B of  FIG. 24A . The first semiconductor layers  201  and the second semiconductor layers  202  are patterned using the mask  207 . In some embodiments, the first semiconductor layers  201  and the second semiconductor layers  202  may be patterned by suitable process, such as etching. For example, an anisotropic etching using C 12  as etchant may be employed. During the etching process, a recess R 3  is formed in the first semiconductor layers  201  and the second semiconductor layers  202 . The remained first semiconductor layers  201  and second semiconductor layers  202  are labeled as  201 ′ and  202 ′, respectively. In some embodiments, the recess R 3  extends into the substrate  200 . 
     Reference is made to  FIGS. 25A and 25B , in which  FIG. 25A  is a top view of one stage of manufacturing a semiconductor device, and  FIG. 25B  is a cross-sectional view along line B-B of  FIG. 25A . A semiconductor material  203  is formed over the substrate  200  and into the recess R 3  (shown in  FIGS. 24A and 24B ). Then, a planarization process, such as CMP, may be performed to remove the excessive semiconductor material  203  until the topmost second semiconductor layer  202 ′ is exposed. The material of the semiconductor material  203  and the material of the second semiconductor layer  202 ′ are the same. Accordingly, the semiconductor material  203  and the second semiconductor layer  202 ′ may be collectively referred to as a channel structure  204  in the following descriptions. From other perspectives, the channel structure  204  includes a plurality of first portions  202 A and a plurality of second portions  202 B made from the same material, in which the width W 4  of the first portions  202 A is smaller than the width W 5  of the second portions  202 B. In some embodiments, the bottommost first portion  202 A extends into the substrate  200 . 
     Reference is made to  FIGS. 26A and 26B , in which  FIG. 26A  is a top view of one stage of manufacturing a semiconductor device, and  FIG. 26B  is a cross-sectional view along line B-B of  FIG. 26A . The isolation structure  208  is partially removed to expose the first semiconductor layers  201 ′ and the channel structure  204 . The isolation structure  208  may be removed by suitable process, such as etching by using HF as etchants. The remained isolation structure  208  is labeled  208 ′ in the following descriptions. 
     Reference is made to  FIGS. 27A to 27D , in which  FIG. 27A  is a top view of one stage of manufacturing a semiconductor device,  FIG. 27B  is a cross-sectional view along line B-B of  FIG. 27A ,  FIG. 27C  is a cross-sectional view along line C-C of  FIG. 27A , and  FIG. 27D  is a cross-sectional view along line D-D of  FIG. 27A . A dummy gate structure  209  is formed over the substrate  200  and crossing the channel structure  204  along the direction D 2 , in which the direction D 2  is different from the direction D 1 . For example, the direction D 2  is substantially vertical to the direction D 1 . The structure and material of the dummy gate structure  209  may be the same as or similar to the dummy gate structure  109  of  FIGS. 6A and 6B . 
     Reference is made to  FIGS. 28A to 28D , in which  FIG. 28A  is a top view of one stage of manufacturing a semiconductor device,  FIG. 28B  is a cross-sectional view along line B-B of  FIG. 28A ,  FIG. 28C  is a cross-sectional view along line C-C of  FIG. 28A , and  FIG. 28D  is a cross-sectional view along line D-D of  FIG. 28A . An isolation material  210  is formed over the substrate  200 . Further, a planarization process, such as chemical mechanical polishing (CVD), may be performed to the isolation material  210  until the dummy gate structure  209  is exposed, such that top surfaces of the isolation material  210  and the dummy gate structure  209  are substantially coplanar. The structure material of the isolation material  210  may be the same as or similar to the isolation material  110  of  FIGS. 7A and 7B . 
     Reference is made to  FIGS. 29A to 29D , in which  FIG. 29A  is a top view of one stage of manufacturing a semiconductor device,  FIG. 29B  is a cross-sectional view along line B-B of  FIG. 29A ,  FIG. 29C  is a cross-sectional view along line C-C of  FIG. 29A , and  FIG. 29D  is a cross-sectional view along line D-D of  FIG. 29A . The isolation material  210  is partially removed by, for example, dry etching. Accordingly, the topmost second portion  202 B of the channel structure  204  is exposed from the isolation material  210 . 
     Reference is made to  FIGS. 30A to 30D , in which  FIG. 30A  is a top view of one stage of manufacturing a semiconductor device,  FIG. 30B  is a cross-sectional view along line B-B of  FIG. 30A ,  FIG. 30C  is a cross-sectional view along line C-C of  FIG. 30A , and  FIG. 30D  is a cross-sectional view along line D-D of  FIG. 30A . Plural gate spacers  211  are formed on opposite sidewalls of the dummy gate structure  209 . The structure and material of the gate spacers  211  may be the same as or similar to the gate spacers  111  of  FIGS. 10A and 10C . 
     Reference is made to  FIGS. 31A to 31D , in which  FIG. 31A  is a top view of one stage of manufacturing a semiconductor device,  FIG. 31B  is a cross-sectional view along line B-B of  FIG. 31A ,  FIG. 31C  is a cross-sectional view along line C-C of  FIG. 31A , and  FIG. 31D  is a cross-sectional view along line D-D of  FIG. 31A . The first semiconductor layers  201 ′ and the second semiconductor layers  202 ′ are patterned using the dummy gate structure  209  and the gate spacers  211  as a mask. After the patterning, recesses R 4  are formed over the substrate  200 , in which one of the recesses R 2  is defined by the isolation material  210  and the semiconductor layers  201 ′ and  202 ′. Then, source/drain structures  212  are formed in the recesses R 4 , respectively. Accordingly, the source/drain structures  212  are in contact with the isolation material  210 , and the semiconductor layers  201 ′ and  202 ′. The structure and material of the source/drain structures  212  may be the same as or similar to the source/drain structures  112  of  FIGS. 11A and 11C . 
     Reference is made to  FIGS. 32A to 32C , in which  FIG. 32A  is a top view of one stage of manufacturing a semiconductor device,  FIG. 32B  is a cross-sectional view along line B-B of  FIG. 32A , and  FIG. 32C  is a cross-sectional view along line C-C of  FIG. 32A . An isolation material  220  is formed over the substrate  200 . In some embodiments, the material of the isolation material  220  is the same as the isolation material  210 . Further, a planarization process, such as chemical mechanical polishing (CVD), may be performed to the isolation material  220  until the dummy gate structure  209  is exposed, such that top surfaces of the isolation material  220 , the dummy gate structure  209 , and the gate spacers  211  are substantially coplanar. The structure and material of the isolation material  220  may be the same as or similar to the isolation material  120  of  FIGS. 12A and 12C . 
     Reference is made to  FIGS. 33A to 33B , in which  FIG. 33A  is a top view of one stage of manufacturing a semiconductor device,  FIG. 33B  is a cross-sectional view along line B-B of  FIG. 33A . The dummy gate structure  209  is removed. In some embodiments, a replacement gate (RPG) process scheme is employed. In a RPG process scheme, a dummy polysilicon gate (the dummy gate electrode in this case) is formed first and is replaced later by a metal gate after high thermal budget processes are performed. In some embodiments, the dummy gate electrode is removed to form an opening with the spacers  211  as its sidewall. In some other embodiments, the gate dielectric is removed as well. Alternatively, in some embodiments, the dummy gate electrode is removed while the gate dielectric retains. The dummy gate electrode (and the gate dielectric) may be removed by dry etch, wet etch, or a combination of dry and wet etch. For example, a wet etch process may include exposure to a hydroxide containing solution (e.g., ammonium hydroxide), deionized water, and/or other suitable etchant solutions. 
     Reference is made to  FIGS. 34A to 34B , in which  FIG. 34A  is a top view of one stage of manufacturing a semiconductor device,  FIG. 34B  is a cross-sectional view along line B-B of  FIG. 34A . The first semiconductor layers  201 ′ (shown in  FIG. 33B ) are removed by suitable process, such as isotropic etching by using CF 4  as etchant. In some embodiments, the etching process may include etching selectivity, such that the second semiconductor layers  202 ′ and the semiconductor material  203  remain the same during the etching process. After the etching process, plural recesses R 5  are formed between two adjacent second portions  202 B, in which the bottommost recess R 5  is between one second portions  202 B and the substrate  200 . From other perspectives, some of the recesses R 5  are defined by two second portions  202 B and the first portion  202 A therebetween. In some embodiments, the isolation structure  208 ′ may be partially removed during the etching process. 
     Reference is made to  FIGS. 35A to 35B , in which  FIG. 35A  is a top view of one stage of manufacturing a semiconductor device, and  FIG. 35B  is a cross-sectional view along line B-B of  FIG. 35A . A gate structure  215  is formed crossing and in contact with the channel structure  204  (the remained portion of second semiconductor layers  202 ′ and the semiconductor material  203 ). A portion of the gate structure  215  is formed into the recesses R 5  (shown in  FIG. 34B ). In some embodiments, the gate structure  215  includes a gate dielectric  213  conformally formed on exposed surfaces of the channel structure  204 , and a gate metal  214  formed over the gate dielectric  213 . The structure and material of the gate structure  215  may be the same as or similar to the gate structure  115  of  FIGS. 16B and 16C . 
     Reference is made to  FIGS. 36A to 36B , in which  FIG. 36A  is a top view of one stage of manufacturing a semiconductor device,  FIG. 36B  is a cross-sectional view along line B-B of  FIG. 36A , and  FIG. 36C  is a cross-sectional view along line C-C of  FIG. 36A . A planarization process, such as CMP, is performed to the gate structure  215  until the isolation material  220  is exposed, such that the top surface of the gate structure  215  is level with that of the isolation material  220 . 
       FIGS. 37A to 37C  illustrate a method of manufacturing a semiconductor device at various stages in accordance with some embodiments. 
     Reference is made to  FIG. 37A . The cross-sectional position of  FIG. 37A  is similar to the cross-sectional position of  FIG. 2B , and thus other relevant structural and manufacturing details will not be repeated hereinafter. A plurality of first semiconductor layers  301  and second semiconductor layers  302  are formed over the substrate  300 , in which the first semiconductor layers  301  and second semiconductor layers  302  are alternately formed such that the first semiconductor layers  301  and second semiconductor layers  302  are alternately stacked on each other. In some embodiments, the bottommost first semiconductor layer  301  has a thickness T 2 , and other first semiconductor layers  301  have thickness T 3 , in that thickness T 2  is larger than thickness T 3 . The structure and material of the first semiconductor layers  301  and second semiconductor layers  302  may be the same as or similar to the first semiconductor layers  101  and second semiconductor layers  102  of  FIGS. 2A and 2B . 
     Reference is made to  FIG. 37B . The cross-sectional position of  FIG. 37B  is similar to the cross-sectional position of  FIG. 15B , and thus other relevant structural and manufacturing details will not be repeated hereinafter. The first semiconductor layers  301  are partially removed by suitable process, such as isotropic etching by using CF 4  as etchant. In some embodiments, due to the etching properties, the bottommost layer of the first semiconductor layers  301  (shown in  FIG. 37A ) having larger thickness T 2  may have an etching rate faster than an etching rate of other first semiconductor layers  301  having thickness T 3  during the etching process. As a result, the bottommost layer of the first semiconductor layers  301  is consumed after the etching process. The remained first semiconductor layers  301  and the second semiconductor layers  302  may be collectively referred to as a channel structure  303 . Further, the first semiconductor layers  301  may be referred to as first portions  301  of the channel structure  303 , and the second semiconductor layers  302  may be referred to as second portions  302  of the channel structure  303 , respectively. The channel structure  303  is spaced from the substrate  300 , and one of the second portions  302  is the bottommost layer of the channel structure  303 . 
     Reference is made to  FIG. 37C . The cross-sectional position of  FIG. 37C  is similar to the cross-sectional position of  FIG. 17B , and thus other relevant structural and manufacturing details will not be repeated hereinafter. Since the channel structure  303  is spaced from the substrate  300 , the gate structure  315  is formed between the channel structure  303  and the substrate  300 . Further, the gate structure  315  substantially covers the bottom surface of the channel structure  303 . The structure and material of the gate structure  315  may be the same as or similar to the gate structure  115  of  FIGS. 16B and 16C . 
       FIGS. 38A to 38C  illustrate a method of manufacturing a semiconductor device at various stages in accordance with some embodiments. 
     Reference is made to  FIG. 38A . The cross-sectional position of  FIG. 38A  is similar to the cross-sectional position of  FIG. 37A , and thus other relevant structural and manufacturing details will not be repeated hereinafter. The first semiconductor layers  401  and the second semiconductor layers  402  are alternately stacked. The bottommost layer of the first semiconductor layers  401  has greater thickness than other first semiconductor layers  401 . Due to the lattice mismatch between the bottommost first semiconductor layer  401  and the substrate  400 , a portion of the bottommost first semiconductor layer  401  close to the substrate  400  may include more defects. On the other hands, other portions of the bottommost first semiconductor layers  401  away from the substrate  400  may have less defects due to strain relaxation. That is, the defects of the bottommost first semiconductor layers  401  decrease from the substrate  400  toward the second semiconductor layer  402 . The structure and material of the first semiconductor layers  401  and second semiconductor layers  402  may be the same as or similar to the first semiconductor layers  401  and second semiconductor layers  402  of  FIGS. 2A and 2B . 
     Reference is made to  FIG. 38B . The cross-sectional position of  FIG. 38B  is similar to the cross-sectional position of  FIG. 37B , and thus other relevant structural and manufacturing details will not be repeated hereinafter. Due to the etching property, the portion of the bottommost first semiconductor layer  401  having more defects may have a faster etching rate. As a result, in some embodiments, the portion of the of the bottommost first semiconductor layers  401  away from the substrate  400  having less defects may remain after the etching process. In some embodiments, the bottommost layer of first semiconductor layers  401  tapers from the second semiconductor layers  402  toward the substrate  400 . 
     Reference is made to  FIG. 38C . The cross-sectional position of  FIG. 38C  is similar to the cross-sectional position of  FIG. 37C , and thus other relevant structural and manufacturing details will not be repeated hereinafter. Since the channel structure  403  is spaced from the substrate  300 , the gate structure  315  is formed between the channel structure  403  and the substrate  400 . Further, the gate structure  415  substantially covers the bottom surface of the channel structure  403 . The structure and material of the gate structure  415  may be the same as or similar to the gate structure  115  of  FIGS. 16B and 16C . 
     According to the aforementioned embodiments, a channel structure having a plurality of first portions and second portions is provided. The first portions have a width smaller than that of the second portions, and one of the first portions is disposed between and in contact with two adjacent second portions. The gate structure is formed crossing the channel structure and in contact with the first portions and the second portions. With such configuration, the channel structure may be formed with higher aspect ratio. As a result, the I on  of the semiconductor device may be improved. 
     In some embodiments, a semiconductor device includes a substrate, a channel structure and a metal gate structure. The channel structure protrudes above the substrate. The channel structure includes alternately stacked first portions and second portions having widths greater than widths of the first portions, and the first portions and the second portions are made of the same semiconductor material. The metal gate structure wraps around the channel structure. 
     In some embodiments, a semiconductor device includes a substrate, a metal gate structure and a channel structure. The metal gate structure extends above the substrate. The channel structure is wrapped by the metal gate structure. The channel structure includes alternately stacked first portions and second portions. A width difference between the first and second portions along a lengthwise direction of the metal gate structure is greater than a width difference between the first and second portions along a widthwise direction of the metal gate structure. 
     In some embodiments, a method includes forming a multilayer stack of alternating first layers of a first semiconductor material and second layers of a second semiconductor material over a substrate, etching a trench extending through the multilayer stack to the substrate, forming a third layer of the first semiconductor material in the trench, removing the second layers of the second semiconductor material, while leaving the first layers of the first semiconductor material and the third layer of the first semiconductor material over the substrate, and forming a gate structure crossing the first layers of the first semiconductor material and the third layer of the first semiconductor material. 
     The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.