Patent Publication Number: US-7719910-B2

Title: Sense amplifier circuit and method for a dram

Description:
PRIORITY CLAIM 
   The present application is a Continuation of U.S. patent application Ser. No. 11/439,728, filed May 23, 2006; now U.S. Pat. No. 7,535,782 which application claims the benefit of French Patent Application Serial No. 05/51336, filed May 23, 2005; all of the foregoing applications are incorporated herein by reference in their entireties. 

   TECHNICAL FIELD 
   Embodiments of the present invention generally relate to DRAMs and, more specifically, to a DRAM cell sense amplifier. 
   BACKGROUND 
     FIG. 1  shows a conventional example of a DRAM cell sense amplifier in a configuration with precharge to the ground. To simplify the representation, the actual memory cells have not been shown, and an example of a memory architecture of the type to which embodiments of the present invention apply will be described in relation with  FIG. 2 . 
   Amplifier  1  comprises, between two terminals  2  and  3  of application of power supply voltages, respectively Vdd and GND (possibly via a switch not shown), a P-channel MOS transistor MP 1  and an amplification stage forming a flip-flop, formed of two parallel branches each comprising a P-channel MOS transistor MP 2 , respectively MP 3 , and an N-channel MOS transistor, respectively MN 2  and MN 3 . The junctions  4  and  5  of the respective series associations of transistors MP 2  and MN 2 , and of transistors MP 3  and MN 3 , are connected to so-called true or direct and complementary bit lines TBL and CBL of the memory cell column of the array network to which amplifier  1  is assigned. Terminals  4  and  5  also define respectively direct and complementary output terminals of sense amplifier  1 . The gates of transistors MP 2  and MN 2  are connected to point  5  while the gates of transistors MP 3  and MN 3  are connected to point  4 . 
   At each read cycle, a single memory cell of the column connected to amplifier  1  is read from, said cell being addressed by selecting a so-called word line by means of a decoder, not shown. 
     FIG. 2  very schematically and partially shows an example of architecture of a DRAM of the type to which embodiments of the present invention apply. For simplification, a single amplifier  1  (SAi) has been shown. Amplifier  1  is used to read bit lines CBLi and TBLi to which are connected memory cells  10 T(i,j),  10 T(i,j+1) on line TBLi and cells  10 C(i,j) and  10 C(i,j+1) on line CBLi. Each cell is formed of a selection transistor T and of a capacitor C between bit line CBLi or TBLi and a bias potential Vp. The respective gates of transistors Tare connected to word lines WLj and WLj+1. In  FIG. 2 , cells  10 C(i,j) and  10 T(i,j+1) have been shown in dotted lines to illustrate the fact that, to read, for example, from cell  10 T(i,j) of line i and of row j, the amplifier SAi assigned to the lines of rank i performs the reading from line TBLi while line CBLi is used as a reference line. 
   To read from the cells of a DRAM, the bit lines need to be precharged at a given voltage. 
   A first category of DRAMs provides a precharge of the bit lines to half the supply voltage, Vdd/2. 
   A second category of DRAMs to which embodiments of the present invention more specifically apply provides a precharge of the bit lines to ground to make the reading faster. 
   In this case, for each bit line, at least one reference cell  20  is used. Each reference cell  20  is typically formed of a memory point formed of a transistor T and of a capacitor C between line CBLi or TBLi and voltage Vp. The gates of transistors T are respectively connected to selection lines RefWL 1  and RefWL 2 . Further, the memory points of cells  20  are connected by a transistor T′ to a line  21  of application of a reference voltage Vref (for example, equal to Vdd/2) by being simultaneously controlled by a signal PREF of precharge of the reference cells. 
   DRAMs using reference cells in a ground precharge configuration are know in the art. 
   The use of reference cells in DRAMs increases the bulk of these memories (4 reference cells are further necessary in case of twisted bit lines in the above-mentioned example). 
   Further, the use of reference cells requires control of additional transistors, which generates an undesirable consumption equivalent to the reading from four cells instead of one. 
   Another disadvantage is that this lengthens the read cycles due to the time required to balance the charges of the reference cells. 
   Also known are sense amplifiers having parallel connected branches of transistors in series, in which junction points of the series associations are not connected to bit lines, the bit lines being connected to gates of additional transistors connected in parallel with transistors of the branches. 
   SUMMARY 
   Embodiments of the present invention overcome all or part of the disadvantages of conventional DRAMs and of their reading. 
   Another embodiment of the present invention is, more specifically, providing a solution avoiding use of reference cells. 
   A further embodiment of the present invention provides improved sensitivity of the sense amplifier. 
   According to one embodiment of the present invention, a sense amplifier of a DRAM includes in series between two terminals of application of a supply voltage at least one first transistor of a first channel type and an amplification stage formed of two parallel branches each including a second transistor of the first channel type in series with a transistor of a second channel type. The gates of the transistors of a same branch are connected to the junction of the transistors of the other branch. Each branch includes at least one first additional transistor of the first channel type in parallel with at least each second transistor of the first channel type. 
   According to an embodiment of the present invention, each first additional transistor is in parallel exclusively with the second transistor of the first channel type of the involved branch. 
   According to an embodiment of the present invention, each first additional transistor is in series with a second additional transistor of the same type between a first terminal of application of the supply voltage and said junction of the involved branch. 
   According to an embodiment of the present invention, one of said first additional transistors is turned on before turning-on of the first transistor of the first channel type. 
   A further embodiment of the present invention is a method for controlling a DRAM sense amplifier, which includes the turning-on of the first additional transistor which is connected in parallel with the amplification branch opposite to that containing the read memory cells. 
   Another embodiment of the present invention is a DRAM of the type comprising an array network of cells connected to direct and complementary columns of bit lines and to word lines, and sense amplifiers. 
   According to an embodiment of the present invention, the memory has no reference cell precharged to a fixed voltage. 
   The foregoing features and advantages of the present invention will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIGS. 1 and 2 , previously described, are intended to show the state of the art and the problem to solve; 
       FIG. 3  shows a DRAM cell sense amplifier according to an embodiment of the present invention 
       FIGS. 4A and 4B  illustrate the operation of the amplifier of  FIG. 3 , respectively for the reading of a state  0  and of a state  1 ; and 
       FIG. 5  is a schematic of a DRAM cell sense amplifier according to an alternative embodiment of the present invention. 
   

   DETAILED DESCRIPTION 
   The following discussion is presented to enable a person skilled in the art to make and use the invention. Various modifications to the embodiments will be readily apparent to those skilled in the art, and the generic principles herein may be applied to other embodiments and applications without departing from the spirit and scope of the present invention. Thus, the present invention is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed herein. 
   Same elements have been designated with same reference numerals in the different drawings. For clarity, only those elements which are necessary to the understanding of embodiments of the present invention have been shown in the drawings and will be described hereafter. In particular, the control circuits of the different memory elements have not been detailed, with embodiments of the present invention being compatible with conventional circuits and especially line and column decoders. Further, the generation and the synchronization of the control signals of the sense amplifier have not been detailed, with embodiments of the present invention being here again compatible with tools generally used to generate such signals. 
     FIG. 3  shows a DRAM cell sense amplifier  30  according to an embodiment of the present invention. 
   As previously discussed, a P-channel transistor MP 1  for controlling amplifier  30  connects a terminal  2  of application of a voltage Vdd to a stage forming a flip-flop formed of two parallel branches, each comprising a P-channel MOS transistor MP 2 , respectively, MP 3 , in series with an N-channel transistor MN 2 , respectively MN 3 . The respective sources of transistors MN 2  and MN 3  are connected to a terminal  3  of application of a ground voltage GND while the respective sources of transistors MP 2  and MP 3  are connected to the drain of transistor MP 1 . The junction points of transistors MP 2 , MN 2 , respectively, MP 3  and MN 3 , define input/output terminals  4  and  5  of the sense amplifier intended to be respectively connected to a direct bit line TBL and to a complementary bit line CBL. The gates of transistors MP 2  and MN 2  are connected together to point  5  while the gates of transistors MP 3  and MN 3  are connected together to point  4  of the other branch. Points  4  and  5  define the output terminals of the amplifier. 
   According to this embodiment of the present invention, two additional P-channel transistors MP 4  and MP 5  are connected in parallel respectively on transistors MP 2  and MP 3 . Transistors MP 4  and MP 5  are controlled by signals SENSE CB and SENSE TB. Transistors MP 4  and MP 5  have the function of dynamically biasing amplifier  30  during read cycles. 
   The memory architecture resembles that illustrated in  FIG. 2 , but without reference cells  20 , which are now no longer necessary. 
     FIG. 4A  illustrates the operation of amplifier  30  of  FIG. 3  for the reading of a state  0  from line TBL. 
   It is assumed that the cell to be read from has been addressed by the word line before a time t 10  so that no signal has been developed on line TBL, the read cell being at state  0 . At time t 10 , signal SENSE TB is switched to state  0  to turn on transistor MP 5  (transistor MP 4  remaining off). At a subsequent time t 11 , signal SENSE of amplifier  30  is switched to the low state to turn on transistor MP 1 . The voltage of the two lines TBL and CBL starts increasing since both P-channel MOS transistors MP 2  and MP 3  are in the on state. Further, an additional current flows through transistor MP 5 , which causes an imbalance in the amplifier to the advantage of line CBL, which increases faster. This voltage difference is amplified by the flip-flop circuit and, at a time t 12 , line CBL is at the high state while line TBL is at the low state. Biasing transistor MP 5  may be blocked from this time on by a state switching of signal SENSE TB. 
     FIG. 4B  illustrates the reading of a state  1  from line TBL. In this configuration, line TBL is not at state  0  but at a higher state (typically, a few hundreds of millivolts) before time t 10 , due to the opening of the memory point to be read by the switching of the corresponding word line. At time t 11  where transistor MP 5  is turned on by the switching to the low state of signal SENSE TB, the voltage of line CBL starts increasing. An additional current flows through transistor MP 5 . However, due to initial interval DV between the voltages of lines TBL and CBL, this current is not sufficient to switch line CBL to level Vdd and the obtained amplification results in an increase in the voltage of node  4  up to level Vdd, line CBL returning to 0. 
   Interval DV between the initial levels of lines TBL and CBL conditions the maximum width-to-length ratio (W/L) of transistors MP 5  and MP 4 . This ratio must then not be too high to avoid, on turning-on of transistor MP 1 , for a reading of a state  1  to result in a switching of the amplification cell. 
   Time t 10  when transistor MP 5  is turned on (or MP 4  if the reading is performed from line CBL) is of no importance, provided that it is performed before the amplification phase (before time t 11 ). 
   Transistors MP 2  and MP 3  are those which must conduct, as in a conventional amplifier, the read current. They must further be fast as compared with transistors MP 4  and MP 5 , which do not have this need. 
   The sizing of transistors MP 2  and MP 3  calls for a compromise since they are ideally desired to be fast (requiring a large width (W) to length (L) ratio), small (requiring small dimensions Wand L) and matched (requiring a large product W*L). 
   Since transistors MP 4  and MP 5  do not have to be fast, the two other requirements (small and matched) result in dimension criteria compatible with each other. 
   According to an alternative embodiment shown in  FIG. 5 , the transistors MP 4  and MP 5  are each coupled in series with a second transistor MP 6  and MP 7 , respectively, connecting them to supply line Vdd  2 , which are then controlled by the signal SENSE. Such transistors MP 6  and MP 7  in this example have a P channel and generate a slight increase in the amplifier surface area. 
   In the illustrated example, the bulks of transistors MP 2 , MP 3 , MP 4 , and MP 5  are brought to level Vdd, the bulks of transistors MN 2 , MN 3 , and MP 1  being connected to their respective sources. 
   An advantage of embodiments of the present invention is that they enable suppression of the reference cells in the DRAM lines. 
   Another advantage of embodiments of the present invention is that it is now no longer necessary to provide voltage level generators for these references. 
   Another advantage of embodiments of the present invention is that they do not alter the amplifier performances while suppressing the reference cells. 
   Of course, embodiments of the present invention are likely to have various alterations, modifications, and improvements which will readily occur to those skilled in the art. In particular, the respective dimensions to be given to the different transistors of the amplifier are within the abilities of those skilled in the art based on the functional indications given hereabove and on the application. 
   Further, the adaptation of the control signals of the different transistors is within the abilities of those skilled in the art. 
   Moreover, if the connections of the different bulks of the transistors have been specified in the discussed embodiments, these are examples only and these connections may be adapted according to the application. 
   Finally, although an embodiment of the present invention has been described in relation with an application where the precharge is to ground, it also applies to a precharge to the positive supply level (Vdd) by inverting the transistor types and with an N-channel transistor controlled by signal SENSE connecting the differential amplification state to ground. 
   Such alterations, modifications, and improvements are intended to be part of this disclosure, and are intended to be within the spirit and the scope of the present invention. Accordingly, the foregoing description is by way of example only and is not intended to be limiting. The present invention is limited only as defined in the following claims and the equivalents thereto. 
   A DRAM including sense amplifiers according to an embodiment of the present invention may be contained in a wide range of different types of electronic devices, such as in computer systems, cellular telephones, personal digital assistants, and so on.