Patent Publication Number: US-2015062618-A1

Title: Electronic device, and method for controlling power to control unit of electronic device

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to an electronic device, and a method for controlling power to a control unit of the electronic device. 
     2. Description of the Related Art 
     In the related art, it is known that, in an electronic device in which power is supplied at a plurality of power levels from a power supply apparatus, a sneak current occurring when a power supply of an entire system is turned on or off has to be prevented. Also, in a typical application specific integrated circuit (ASIC), a specification in which power is supplied at a plurality of power levels, that is, input/output (IO) power and CORE power are supplied is employed. At this time, in order to avoid a state in which an output of an IO terminal of the ASIC becomes unstable, it is known that the IO power has to be supplied before the CORE power at power-on, and the IO power has to be turned off after the CORE power at power-off. 
     In order to maintain a plurality of power supply timings in such an electronic device or ASIC, there is known a technique in which the power supply timings are controlled by using a delay circuit (see Japanese Patent Laid-Open No. 2004-266661). 
     In addition, there is known a technique in which the level of a preceding power supply voltage is monitored by using a comparator or a reset IC, subsequent power is controlled when the level exceeds or falls below a predetermined value, and thus a plurality of power supply timings are controlled. 
     SUMMARY OF THE INVENTION 
     An output of a power supply control circuit for power-on and an output of a power supply control circuit for power-off are connected to enable terminals of power generation circuits for generating power at a plurality of power levels. Because of this, there is required a selector circuit for switching, in accordance with a power supply status (power-on/off) of an electronic device or ASIC, a destination to which an enable terminal of each power generation circuit is connected, between the output of the power supply control circuit for power-on and the output of the power supply control circuit for power-off. This makes the configuration of all the power supply control circuits complicated and results in an increase in cost. 
     The present invention has been accomplished in order to solve the above problems. The present invention provides a mechanism in which turn-on control and turn-off control of a plurality of power supplies requested by a control unit of an electronic device are efficiently performed with a simple circuit configuration. 
     A power supply control apparatus according to the present invention includes: a plurality of generation units configured to each generate direct-current (DC) power having a different potential requested by a control unit of an electronic device; a plurality of monitor units configured to monitor whether or not the DC power generated by each generation unit has become a predetermined potential or higher; a first power supply control unit configured to turn on each generation unit in a predetermined order while checking that the DC power monitored by each monitor unit has become the predetermined potential or higher; and a second power supply control unit configured to, in accordance with a power-off instruction, cause each generation unit turned on by the first power supply control unit to change into a power-off state after a predetermined delay time. 
     Further features of the present invention will become apparent from the following description of exemplary embodiments with reference to the attached drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  illustrates the external appearance of an image forming apparatus to which a power supply control apparatus is applicable. 
         FIG. 2  is a block diagram illustrating the internal configuration of the image forming apparatus illustrated in  FIG. 1 . 
         FIG. 3  is a block diagram illustrating a detailed configuration of a power supply control unit illustrated in  FIG. 2 . 
         FIGS. 4A to 4C  illustrate the configurations of switches of the power supply control unit illustrated in  FIG. 2 . 
         FIG. 5  is a flowchart illustrating a control method executed by the power supply control apparatus. 
         FIG. 6  is a flowchart illustrating a control method executed by the power supply control apparatus. 
         FIG. 7  is a block diagram illustrating the configuration of a power-on control unit illustrated in  FIG. 3 . 
         FIG. 8  is a timing chart illustrating operations performed by the power-on control unit illustrated in  FIG. 7 . 
         FIG. 9  is a block diagram illustrating the configuration of a power-off control unit illustrated in  FIG. 3 . 
         FIGS. 10A to 10C  illustrate the internal circuit configurations of discharge circuits illustrated in  FIG. 3 . 
         FIG. 11  is a timing chart illustrating operations performed by the power-off control unit illustrated in  FIG. 3 . 
         FIG. 12  is a block diagram illustrating the configuration of a power supply control apparatus. 
         FIG. 13  is a block diagram illustrating the configuration of the power supply control apparatus. 
     
    
    
     DESCRIPTION OF THE EMBODIMENTS 
     Exemplary embodiments for implementing the present invention will be described below with reference to the drawings. 
     Description of System Configuration 
     First Embodiment 
       FIG. 1  illustrates the external appearance of an image forming apparatus to which a power supply control apparatus according to a first embodiment is applicable. Besides, an electronic device to which the power supply control apparatus according to this embodiment is applicable is not limited to the foregoing image forming apparatus, and examples of the electronic device include a printing apparatus, an image processing apparatus, a facsimile machine, a scanner device, an information processing apparatus, and a multi-function printer (MFP). In this embodiment, an example in which the power supply control apparatus supplies direct-current (DC) power having a different potential to a control unit of the electronic device will be described. Here, as such electronic devices, there are the foregoing image forming apparatus, a printing apparatus, a multifunction image processing apparatus, a facsimile machine, a scanner device, and an information processing apparatus. 
     In  FIG. 1 , an image forming apparatus  1  includes a scanner unit  10  serving as an image input device, a printer unit  20  serving as an image output device, and an operation unit  30  serving as a user interface. The image forming apparatus  1  further includes a controller unit  40  that controls the entire image forming apparatus, a power supply plug  3  serving as a source for supplying power to the image forming apparatus  1 , and a main switch  50  for supplying power to the image forming apparatus  1 . The power supply plug  3  is connected to an alternating-current (AC) outlet, which is not illustrated. 
     The scanner unit  10  converts information of an image into an electrical signal by inputting reflected light obtained by performing exposure scanning on the image on a document into a charge coupled device (CCD). The scanner unit  10  further converts the electrical signal into a luminance signal composed of red (R), green (G), and blue (B), and outputs, as image data, the luminance signal to the controller unit  40 . Documents are placed on a tray  102  of a document feeder  101 . When a user gives an instruction to start scanning via the operation unit  30 , a document scanning instruction is given from the controller unit  40  to the scanner unit  10 . In response to this instruction, the scanner unit  10  feeds the documents one by one from the tray  102  of the document feeder  101 , and scans the documents. As for document scanning, single or double-sided scanning of the documents is performed by controlling conveyance of the documents in accordance with a scanning condition set via the operation unit  30 . 
     The printer unit  20  is an image forming device that forms image data received from the controller unit  40  on paper. In this embodiment, an image forming method is an electrophotographic method using a photosensitive drum or a photosensitive belt; however, the present invention is not limited to this. For example, an ink-jet method of discharging ink from a minute nozzle array to print data on paper is also applicable. The printer unit  20  includes a plurality of paper cassettes  201 ,  202 , and  203  which enable selection of a different paper size or a different paper orientation. Paper with data printed thereon is ejected onto a paper ejection tray  204 . The controller unit  40  is a unit that controls an operation performed by the image forming apparatus  1 , and performs data transmission/reception, data conversion, and electric power control. 
       FIG. 2  is a block diagram illustrating the internal configuration of the image forming apparatus illustrated in  FIG. 1 . Power supply processing in the image forming apparatus  1  will be described below with reference to  FIG. 2 . 
     In  FIG. 2 , first, in the case where the image forming apparatus  1  is powered on, the user turns on the main switch  50 , and a power supply control unit  60  thereby converts AC power supplied from the power supply plug  3  into DC power having a predetermined potential. As a result, power is supplied to the scanner unit  10 , the printer unit  20 , the operation unit  30 , and controller unit  40 . 
     In the case where the image forming apparatus  1  is powered off, the user turns off the main switch  50 , and the power supply control unit  60  thereby stops power to the scanner unit  10 , the printer unit  20 , the operation unit  30 , and the controller unit  40 . 
     In the case where the image forming apparatus  1  performs a printing operation, job data is transferred to the controller unit  40  via a local area network (LAN)  2  and temporarily stored in a memory included in the controller unit  40 . The memory here includes a random access memory (RAM)  402  and a hard disk drive (HDD)  404 , which are described later. 
     The controller unit  40  converts the stored job data into image data and transfers it to the printer unit  20 . The printer unit  20  prints the image data received under the control of the controller unit  40  on recording paper and ejects the recording paper outside the apparatus. 
     In the case where the image forming apparatus  1  performs a scanning operation, the user places a document on the scanner unit  10 , operates a button referring to a screen of the operation unit  30  to thereby set a scanning operation, and gives an instruction to start the operation. The scanner unit  10  optically scans the document and converts it into image data under the control of the controller unit  40 . The converted image data is temporarily stored in the memory included in the controller unit  40 , and then is transferred to a destination specified in advance via the operation unit  30 . 
     In the case where the image forming apparatus  1  performs a copy operation, the user places a document on the scanner unit  10 , operates a button referring to the screen of the operation unit  30  to thereby set a copy operation, and gives an instruction to start the copy operation. The scanner unit  10  optically scans the document and converts it into image data under the control of the controller unit  40 . After the converted image data is temporarily stored in the memory included in the controller unit  40 , the controller unit  40  converts a data format of the image data into a data format that the printer unit  20  can use, and the printer unit  20  prints the image data on recording paper and ejects the recording paper outside the apparatus. 
       FIG. 3  is a block diagram illustrating a detailed configuration of the power supply control unit  60  illustrated in  FIG. 2 . 
     In  FIG. 3 , the power supply control unit  60  includes the main switch  50 , the power supply plug  3  serving as a source for supplying power, and an ACDC conversion unit  600  that converts AC power input from the power supply plug  3  into DC power. The power supply control unit  60  further includes a first power generation unit  601 , a second power generation unit  602 , and a third power generation unit  603  that generate a plurality of power supply voltages. 
     The power supply control unit  60  includes a power-on control unit  611  that controls a power-on operation performed on the first power generation unit  601 , the second power generation unit  602 , and the third power generation unit  603  which each generate DC power having a different potential requested by the controller unit  40 . The power supply control unit  60  further includes a power-off control unit  631  that controls a power-off operation, and a switch (SW)  621 , a SW  622 , and a SW  623  that each turn off power. The power supply control unit  60  further includes a discharge circuit  624 , a discharge circuit  625 , and a discharge circuit  626  that control fall time periods taken for the first power generation unit  601 , the second power generation unit  602 , and the third power generation unit  603  to be powered off, respectively. 
     Here, the first power generation unit  601 , the second power generation unit  602 , and the third power generation unit  603  are each composed of a DCDC converter with an enable control function. As illustrated in  FIGS. 4A to 4C , the SW  621 , the SW  622 , and the SW  623  that each turn off power have hard-wired configurations with switching field-effect transistors (FETs)  648 ,  649 , and  650 , respectively. 
     The SW  621 , the SW  622 , and the SW  623  have functions of disabling enable signals EN1, EN2, and EN3 for the first power generation unit  601 , the second power generation unit  602 , and the third power generation unit  603 , respectively. In this way, in this embodiment, the power-off control unit  631  gives power-off instructions after different delay times corresponding to the first power generation unit  601 , the second power generation unit  602 , and the third power generation unit  603 , respectively. Details will be discussed later with reference to  FIG. 9 . 
     The discharge circuit  624 , the discharge circuit  625 , and the discharge circuit  626  have discharge functions of causing power V1, power V2, and power V3 to fall quickly in power level, respectively. Because the scanner unit  10 , the printer unit  20 , the operation unit  30 , and the controller unit  40  to which the power V1, the power V2, and the power V3 are supplied each include a capacitor component, electric charge is being accumulated in the capacitor component during power-on. 
     In order to cause the power V1, the power V2, and the power V3 to fall quickly in power level from when power has been turned off, the electric charge accumulated in the capacitor component has to be removed. Because of this, the discharge circuit  624 , the discharge circuit  625 , and the discharge circuit  626  are provided for outputs of the power generation units, respectively. Here, the reason why enable control performed when the power generation units for the power V1, the power V2, and the power V3 are turned on and when they are turned off can be implemented by the hard-wired configurations with the switching FETs  648 ,  649 , and  650  is because a control method for power-on and a control method for power-off are configured to differ from each other. Thus, regardless of whether the power-on control unit  611  performs control for enabling or disabling the enable signals EN1, EN2, and EN3, the power-off control unit  631  can forcibly disable the enable signals EN1, EN2, and EN3. 
     Hence, such a simple circuit configuration as described in this embodiment that does not require such a selector circuit as described in the related art can be provided. 
     The power V2 and the power V3 generated by the second power generation unit  602  and the third power generation unit  603  are individually supplied to a central processing unit (CPU)  401  included in the controller unit  40 . Actually, power other than the power V2 and the power V3 generated by the second power generation unit  602  and the third power generation unit  603  is also supplied to the scanner unit  10 , the printer unit  20 , the operation unit  30 , the controller unit  40 , and the like. For the sake of simplicity here, supply of power to the CPU  401  included in the controller unit  40  will be described. 
     The controller unit  40  is electrically connected to the scanner unit  10  and the printer unit  20 , and is also connected to a personal computer (PC), an external apparatus, or the like via the LAN  2  or the like. This enables input/output of image data or device information. 
     The CPU  401  performs centralized control of access to/from various devices being connected to the controller unit  40  on the basis of a control program and the like stored in a read only memory (ROM)  403 , and also performs centralized control of various processes performed in the controller unit  40 . The RAM  402  is a system work memory in which the CPU  401  operates and also a memory in which image data is temporarily stored. This RAM  402  includes a static RAM (SRAM), information stored in which is retained even after power is turned off, and a dynamic RAM (DRAM), information stored in which is deleted after power is turned off. The ROM  403  stores a boot program for the apparatus, and the like. The HDD  404  is a hard disk drive and capable of storing system software or image data. 
     An operation unit interface (I/F)  405  is an interface unit that connects a system bus  407  and the operation unit  30 . The operation unit I/F  405  receives image data to be displayed on the operation unit  30  from the system bus  407  and outputs it to the operation unit  30 , and also outputs information input via the operation unit  30  to the system bus  407 . 
     A LAN controller  406  connects to the LAN  2  and the system bus  407 , and performs input/output control of information. 
     An image processing unit  409  is a unit that performs image processing operations, and is capable of reading image data stored in the RAM  402  and performing image processing operations, such as enlargement or reduction of Joint Photographic Experts Group (JPEG) image data, Joint Bi-level Image experts Group (JBIG) image data, or the like, and color adjustment of image data. 
     A scanner image processing unit  410  corrects, modifies, and edits image data received from the scanner unit  10  via a scanner I/F  411 . Besides, the scanner image processing unit  410  determines whether received image data is data based on a color document, monochrome document, text document, photographic document, or the like. Then, a determination result is attached to the image data. Such attached information is referred to as attribute data. 
     A printer image processing unit  412  performs image processing on the image data referring to attribute data attached to this image data. The image data subjected to the image processing is output to the printer unit  20  via a printer I/F  413 . 
     A power supply control process flow performed when the main switch  50  is turned on or off will be described below. 
       FIG. 5  is a flowchart illustrating a control method executed by the power supply control apparatus according to this embodiment. An example of a power-on process performed in the power supply control unit  60  is given here. Each step is implemented by hardware included in the power supply control unit  60  executing sequence control. A power supply control process of turning on each power generation unit while checking that power of each power generation unit has become a predetermined potential or higher after the main switch  50  has been turned on will be described in detail below. 
     The ACDC conversion unit  600  converts AC power from the power supply plug  3  into DC power, and supplies power to the power-on control unit  611 , the power-off control unit  631 , and the first power generation unit  601 . The main switch  50  is turned on (S 101 ). Subsequently, in response to the fact that a POWER_ON signal has been enabled, the power-on control unit  611  enables an enable signal EN1 for the first power generation unit  601  (S 102 ). The first power generation unit  601  causes power V1 to rise in power level by using the power input from the ACDC conversion unit  600  and the enable signal EN1 from the power-on control unit  611 . The power V1 acts as power to be input to the second power generation unit  602  and the third power generation unit  603 . 
     The power V1 is also input to the power-on control unit  611  as well. When the power-on control unit  611  monitors a voltage value of the power V1 from the first power generation unit  601  and detects that the voltage value of the power V1 has become higher than or equal to a predetermined voltage value set in advance (S 103 ), the power-on control unit  611  enables an enable signal EN2 for the second power generation unit  602  (S 104 ). The second power generation unit  602  generates power V2 by using the power V1 input from the first power generation unit  601  and the enable signal EN2 from the power-on control unit  611 , and outputs the power V2. 
     The power V2 is input to the power-on control unit  611 . When the power-on control unit  611  monitors a voltage value of the power V2 and detects that the voltage value of the power V2 has become higher than or equal to a predetermined voltage value set in advance (S 105 ), the power-on control unit  611  enables an enable signal EN3 for the third power generation unit  603  (S 106 ). The third power generation unit  603  generates power V3 by using the power V1 from the first power generation unit  601  and the enable signal EN3 from the power-on control unit  611 , and outputs the power V3. 
       FIG. 6  is a flowchart illustrating a control method executed by the power supply control apparatus according to this embodiment. An example of a power-off process performed in the power supply control unit  60  is given here. Each step is implemented by the hardware included in the power supply control unit  60  executing sequence control. A power supply control process performed when the main switch  50  is turned off will be described in detail below. 
     When a delay time Td3 has elapsed since the main switch  50  was turned off (S 201 ), in response to the fact that the POWER_ON signal has been disabled, the power-off control unit  631  turns off the SW  623  (gives a power-off instruction) (S 202 ). This disables the enable signal EN3 for the third power generation unit  603 . Then, output of the power V3 of the third power generation unit  603  is stopped (S 203 ). Because of this, the third power generation unit  603  changes into a power-off state. 
     Similarly, when a delay time Td2 has elapsed since the main switch  50  was turned off (S 204 ), the power-off control unit  631  turns off the SW  622  (S 205 ). This disables the enable signal EN2 for the second power generation unit  602 , and output of the power V2 of the second power generation unit  602  is stopped (S 206 ). In addition, when a delay time Td1 has elapsed since the main switch  50  was turned off (S 207 ), the power-off control unit  631  turns off the SW  621  (S 208 ). This disables the enable signal EN1 for the first power generation unit  601 , and output of the power V1 of the first power generation unit  601  is stopped (S 209 ). 
       FIG. 7  is a block diagram illustrating the configuration of the power-on control unit  611  illustrated in  FIG. 3 . 
     In  FIG. 7 , the power-on control unit  611  includes a buffer  613 , a comparator  614 , a comparator  615 , a voltage divider circuit  616  that generates a reference voltage Vref1, and a voltage divider circuit  617  that generates a reference voltage Vref2. 
     As described above, when the main switch  50  is turned on, the power-on control unit  611  detects that the main switch  50  has been turned on. Via the buffer  613 , a detected signal makes the enable signal EN1 for the first power generation unit  601  Hi and the enable signal EN1 is output. 
     In the comparator  614 , the power V1 from the first power generation unit  601  is input to a + input terminal, and a predetermined reference voltage Vref1 set in advance is input to a − input terminal. 
     The reference voltage Vref1 is generated by the voltage divider circuit  616  performing resistive division of a power V0. When the voltage of the power V1 becomes the reference voltage Vref1 or higher, the enable signal EN2 for the second power generation unit  602  is made Hi and is output. 
     Here, the reference voltage Vref1 is set to a value used for determining that the power V1 has risen in power level. Similarly, in the comparator  615 , the voltage of the power V2 input from the second power generation unit  602  is input to a + input terminal, and a predetermined reference voltage Vref2 set in advance is input to a − input terminal of the comparator  615 . The reference voltage Vref2 is generated by the voltage divider circuit  617  performing resistive division of the power V0. 
     When the voltage of the power V2 becomes the reference voltage Vref2 or higher, the enable signal EN3 for the third power generation unit  603  is made Hi and is output. In this way, a power-on sequence is generated using the comparators and the reference voltages Vref&#39;s at power-on. This is done to prevent, if an electrical failure occurs in any power generation unit of a plurality of power generation units and power is not output, a power generation unit subsequent to the faulty power generation unit from outputting power. If the power generation unit subsequent to the faulty power generation unit outputs power, the possibility of the occurrence of a sneak current described in the related art arises. 
       FIG. 8  is a timing chart illustrating operations performed by the power-on control unit  611  illustrated in  FIG. 7 . Operations performed by the power-on control unit  611  involved in the power-on control flow illustrated in  FIG. 5  will be described below. 
     When the enable signals EN1, EN2, and EN3 become Hi, the power V1, the power V2, and the power V3 output by the first power generation unit  601 , the second power generation unit  602 , and the third power generation unit  603  start to rise in power level, respectively. At this time, there occur rise time periods Tr1, Tr2, and Tr3 taken for the power V1, the power V2, and the power V3 to reach reference voltages Vref1 (voltage divider circuit  616 ), Vref2 (voltage divider circuit  617 ), Vref3 (voltage divider circuit  618 ) used for determining that the power V1, the power V2, and the power V3 have risen in power level, respectively. 
     That is, when the main switch  50  is turned on, in terms of power level, the power V1 succeeds in rising after Tr1, the power V2 succeeds in rising after Tr1+Tr2, and the power V3 succeeds in rising after Tr1+Tr2+Tr3. 
       FIG. 9  is a block diagram illustrating the configuration of the power-off control unit  631  illustrated in  FIG. 3 . Operations performed by the power-off control unit  631  involved in the power-off control flow illustrated in  FIG. 6  will be described below. Here, an example of a delay circuit is an analog circuit that includes a resistor and a capacitor. 
     In  FIG. 9 , the power-off control unit  631  includes an inverter  632 , AND gate circuits  633 ,  634 , and  635 , delay circuits  636 ,  637 , and  638  each including a resistor and a capacitor, and Schmitt buffers  639 ,  640 , and  641 . Here, the delay circuit  636  includes a resistor  642  and a capacitor  645 . Also, the delay circuit  637  includes a resistor  643  and a capacitor  646 . Furthermore, the delay circuit  638  includes a resistor  644  and a capacitor  647 . Besides, delay times of the delay circuits  636  to  638  for an off instruction are determined in accordance with the resistor  642  and capacitor  645 , the resistor  643  and capacitor  646 , and the resistor  644  and capacitor  647 , respectively. 
     As described above, when the main switch  50  is turned off, the POWER_ON signal becomes Low, and the power-off control unit  631  detects that the main switch  50  has been turned off. The POWER_ON signal is input to the inverter  632 , and a POWER_OFF signal which is a logical inversion of the POWER_ON signal is output. 
     The AND gate circuit  633  is a logic circuit having two inputs and one output. The POWER_OFF signal is input to one of the two inputs. A DELAY1 signal which is obtained by delaying the POWER_OFF signal with the delay circuit  636  and the Schmitt buffer  639  is input to the other of the two inputs. 
     At this time, a delay time Td1 of the DELAY1 signal with respect to the POWER_OFF signal is determined in accordance with a resistance value of the resistor  642  and a capacitance value of the capacitor  645  which are included in the delay circuit  636 . The AND gate circuit  633  outputs an OFF1 signal, which is the product of the POWER_OFF signal and the DELAY1 signal. 
     As a control signal for disabling the enable signal EN1 for the first power generation unit  601 , the OFF1 signal is input to the SW  621 . This can cause the output power V1 to start to fall in power level at an intended point in time. In addition, as a control signal for completing, within a predetermined time period, the fall of the power V1 output from the first power generation unit  601 , the OFF1 signal is also input to the discharge circuit  624 . The AND gate circuit  634  is also a logic circuit having two inputs and one output. The POWER_OFF signal is input to one of the two inputs. A DELAY2 signal which is obtained by delaying the OFF1 signal with the delay circuit  637  and the Schmitt buffer  640  is input to the other of the two inputs. 
     At this time, a delay time Td2 of the DELAY2 signal with respect to the POWER_OFF signal is determined in accordance with a resistance value of the resistor  643  and a capacitance value of the capacitor  646  which are included in the delay circuit  637 . The AND gate circuit  634  outputs an OFF2 signal, which is the product of the POWER_OFF signal and the DELAY2 signal. As a control signal for disabling the enable signal EN2 for the second power generation unit  602 , the OFF2 signal is input to the SW  622 . This can cause the output power V2 to start to fall in power level at an intended point in time. In addition, as a control signal for completing, within a predetermined time period, the fall of the power V2 output from the second power generation unit  602 , the OFF2 signal is also input to the discharge circuit  625 . The AND gate circuit  635  is also a logic circuit having two inputs and one output. The POWER_OFF signal is input to one of the two inputs. A DELAY3 signal which is obtained by delaying the OFF2 signal with the delay circuit  638  and the Schmitt buffer  641  is input to the other of the two inputs. 
     At this time, a delay time Td3 of the DELAY3 signal with respect to the POWER_OFF signal is determined in accordance with a resistance value of the resistor  644  and a capacitance value of the capacitor  647  which are included in the delay circuit  638 . The AND gate circuit  635  outputs an OFF3 signal, which is the product of the POWER_OFF signal and the DELAY3 signal. As a control signal for disabling the enable signal EN3 for the third power generation unit  603 , the OFF3 signal is input to the SW  623 . This can cause the output power V3 to start to fall in power level at an intended point in time. In addition, as a control signal for completing, within a predetermined time period, the fall of the power V3 output from the third power generation unit  603 , the OFF3 signal is also input to the discharge circuit  626 . 
     In this way, a power-off sequence is generated using the delay circuits and the AND gate circuits at power-off. This is because the case where an electrical failure occurs in any power generation unit of a plurality of power generation units and power is not stopped is very rare in comparison with the above-mentioned case at power-on. It is assumed that an electrical failure occurs in any power generation unit of a plurality of power generation units and a state in which power is not stopped occurs. In this case, if the first power generation unit  601  can be powered off with certainty, the second power generation unit  602  and the third power generation unit  603  are also powered off, and the occurrence of a prolonged sneak current can therefore be avoided. 
       FIGS. 10A to 10C  illustrate the internal circuit configurations of the discharge circuits  624 ,  625 , and  626  illustrated in  FIG. 3 . 
     In  FIGS. 10A to 10C , the discharge circuits  624  to  626  respectively include transistors  695  to  697  that discharge the output power V1 to the output power V3, and resistors  692  to  694  that adjusts fall time periods Tf1 to Tf3 of the output power V1 to the output power V3. The lower resistance values of the resistors  692 ,  693 , and  694  are, the shorter the fall time periods Tf1, Tf2, and Tf3 can be set. Besides, FETs can be included in place of the transistors  695  to  697 . 
       FIG. 11  is a timing chart illustrating operations performed by the power-off control unit  631  illustrated in  FIG. 3 . Operations performed by the power-off control unit  631  involved in the power-off control flow illustrated in  FIG. 6  will be described below. 
     In  FIG. 11 , the SW  621 , the SW  622 , and the SW  623  are turned off by the OFF1 signal, the OFF2 signal, and the OFF3 signal, respectively. When the enable signals EN1, EN2, and EN3 thereby become Low, the power V1, the power V2, and the power V3 output by the first power generation unit  601 , the second power generation unit  602 , and the third power generation unit  603  start to fall in power level, respectively. 
     At this time, points in time at which the power V1, the power V2, and the power V3 start to fall are points in time after the delay times Td1, Td2, and Td3 have elapsed since the POWER_OFF signal was output, respectively. Here, although the power V1, the power V2, and the power V3 are supplied to the scanner unit  10 , the printer unit  20 , the operation unit  30 , and the controller unit  40 , in order to prevent a sneak current, the order in which the power V1, the power V2, and the power V3 are turned off is the reverse order of that at power-on. 
     Thus, the power is turned off in the order of the power V3, the power V2, and the power V1. In order to do this, after the fall of the power V3 in power level has been completed, the power V2 is caused to start to fall. Then, after the fall of the power V2 has been completed, the power V1 is caused to start to fall. In this way, resistance values of the resistors  642 ,  643 , and  644  and capacitance values of the capacitors  645 ,  646 , and  647  which are respectively included in the delay circuits  636 ,  637 , and  638  are set so that the delay times Td3 to Td1 and the fall time periods Tf1 to Tf3 satisfy the relationship of Td3+Tf3&lt;Td2+Tf2&lt;Td1. 
     Hence, on/off control of a plurality of power supplies can be implemented with a simple circuit configuration that does not require a selector circuit for switching between a power supply control circuit for power-on and a power supply control circuit for power-off. 
     Second Embodiment 
     In a second embodiment, in the power-on control unit  611  illustrated in  FIG. 7  in the first embodiment, the case where reset ICs are included in place of the comparators will be described. Also, in the power-off control unit  631  illustrated in  FIG. 9  in the first embodiment, the case where flip-flop circuits are included in place of the delay circuits and the Schmitt buffers will be described. Besides, a description of the same hardware configuration as that described in the first embodiment will be omitted. 
       FIG. 12  is a block diagram illustrating the configuration of a power supply control apparatus according to this embodiment. An example of another configuration of the power-on control unit  611  illustrated in  FIG. 3  is given here. 
     In  FIG. 12 , a power-on control unit  651  includes a buffer  653 , a reset IC  654 , a reset IC  655 , a voltage divider circuit  656 , and a voltage divider circuit  657 . When the main switch  50  is turned on, the power-on control unit  651  detects that the main switch  50  has been turned on. 
     Via the buffer  653 , a detected signal makes the enable signal EN1 for the first power generation unit  601  Hi and the enable signal EN1 is output. In the reset IC  654 , the power V1 from the first power generation unit  601  is input to an input terminal, and a predetermined reference voltage Vref1 set in advance is input to a reference voltage terminal. The reference voltage Vref1 is generated by the voltage divider circuit  656  performing resistive division of a power V0. When the voltage of the power V1 becomes the reference voltage Vref1 or higher, the enable signal EN2 for the second power generation unit  602  is made Hi and is output. Here, the reference voltage Vref1 is set to a value used for determining that the power V1 has risen in power level. 
     Similarly, in the reset IC  655 , the voltage of the power V2 input from the second power generation unit  602  is input to an input terminal, and a predetermined reference voltage Vref2 set in advance is input to a reference voltage terminal. The reference voltage Vref2 is generated by the voltage divider circuit  657  performing resistive division of the power V0. When the voltage of the power V2 becomes the reference voltage Vref2 or higher, the enable signal EN3 for the third power generation unit  603  is made Hi and is output. 
       FIG. 13  is a block diagram illustrating the configuration of the power supply control apparatus according to this embodiment. An example of another configuration of the power-off control unit  631  illustrated in  FIG. 3  is given here. In this example, flip-flop circuits are included in place of delay circuits. 
     In  FIG. 13 , a power-off control unit  661  includes an inverter  662 , AND gate circuits  663 ,  664 , and  665 , flip-flop circuits  673 ,  674 , and  675 , and a clock generator  676 . When the main switch  50  is turned off, the POWER_ON signal becomes Low, and the power-off control unit  661  detects that the main switch  50  has been turned off. Here, a common clock is input from the clock generator  676  to the flip-flop circuits  673 ,  674 , and  675 . Also, gate outputs from the AND gate circuits  663  and  664  are input to D inputs of the flip-flop circuits  674  and  675 , respectively. 
     The POWER_ON signal is input to the inverter  662 , and a POWER_OFF signal which is a logical inversion of the POWER_ON signal is output. The AND gate circuit  663  is a logic circuit having two inputs and one output. The POWER_OFF signal is input to one of the two inputs. A DELAY1 signal which is obtained by delaying the POWER_OFF signal with the flip-flop circuit  673  is input to the other of the two inputs. At this time, the flip-flop circuit  673  synchronizes the input POWER_OFF signal with a clock signal generated by the clock generator  676 , and outputs a clock synchronization signal derived from the POWER_OFF signal. 
     For this reason, a delay time Td1 of the DELAY1 signal with respect to the POWER_OFF signal is determined in accordance with a period of one pulse of a clock generated by the clock generator  676 . The AND gate circuit  663  outputs an OFF1 signal, which is the product of the POWER_OFF signal and the DELAY1 signal. As a control signal for disabling the enable signal EN1 for the first power generation unit  601 , the OFF1 signal is input to the SW  621 . This can cause the output power V1 to start to fall in power level at an intended point in time. 
     In addition, as a control signal for completing, within a predetermined time period, the fall of the power V1 output from the first power generation unit  601 , the OFF1 signal is also input to the discharge circuit  624 . The AND gate circuit  664  and the AND gate circuit  665  are also each a logic circuit having two inputs and one output. The POWER_OFF signal is input to one of the two inputs. A DELAY2 signal and a DELAY3 signal which are obtained by respectively delaying the OFF1 signal and an OFF2 signal with the flip-flop circuits  674  and  675  are each input to the other of the two inputs. 
     At this time, the flip-flop circuits  674  and  675  each synchronize the input POWER_OFF signal with the clock signal generated by the clock generator  676 , and output a clock synchronization signal derived from the POWER_OFF signal. As control signals for respectively disabling the enable signals EN2 and EN3 for the second power generation unit  602  and the third power generation unit  603 , the OFF2 signal and an OFF3 signal respectively output from the AND gate circuit  664  and the AND gate circuit  665  are input to the SW  622  and the SW  623 , respectively. This can cause the output power V2 and the output power V3 to start to fall in power level at intended points in time, respectively. 
     In addition, as control signals for completing, within predetermined time periods, the falls of the power V2 and the power V3 respectively output from the second power generation unit  602  and the third power generation unit  603 , respectively, the OFF2 signal and the OFF3 signal are also input to the discharge circuit  625  and the discharge circuit  626 , respectively. 
     The processes of the present invention can also be implemented by causing a processing apparatus (CPU or processor) of, for example, a personal computer (computer) to execute software (program) acquired via a network or various storage media. 
     The present invention is not limited to the above-described embodiments, and various modifications (including an organic combination of the embodiments) can be made on the basis of the gist of the present invention and are not excluded from the scope of the present invention. 
     According to the present invention, turn-on control and turn-off control of a plurality of power supplies requested by a control unit of an electronic device are efficiently performed with a simple circuit configuration. 
     Other Embodiments 
     Embodiments of the present invention can also be realized by a computer of a system or apparatus that reads out and executes computer executable instructions recorded on a storage medium (e.g., non-transitory computer-readable storage medium) to perform the functions of one or more of the above-described embodiment(s) of the present invention, and by a method performed by the computer of the system or apparatus by, for example, reading out and executing the computer executable instructions from the storage medium to perform the functions of one or more of the above-described embodiment(s). The computer may comprise one or more of a central processing unit (CPU), micro processing unit (MPU), or other circuitry, and may include a network of separate computers or separate computer processors. The computer executable instructions may be provided to the computer, for example, from a network or the storage medium. The storage medium may include, for example, one or more of a hard disk, a random-access memory (RAM), a read only memory (ROM), a storage of distributed computing systems, an optical disk (such as a compact disc (CD), digital versatile disc (DVD), or Blu-ray Disc (BD)™), a flash memory device, a memory card, and the like. 
     While the present invention has been described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. The scope of the following claims is to be accorded the broadest interpretation so as to encompass all such modifications and equivalent structures and functions. 
     This application claims the benefit of Japanese Patent Application No. 2013-181348 filed Sep. 2, 2013, which is hereby incorporated by reference herein in its entirety.