Patent Publication Number: US-2022215864-A1

Title: Buffers and multiplexers

Description:
BACKGROUND OF THE INVENTION 
     Field of the Invention 
     The invention relates to a buffer circuit, and more particularly to a dual-mode buffer circuit. 
     Description of the Related Art 
     Modern high speed serial link devices are required to operate at a reduced data rate for backward compatibility. However, these devices may consume similar amount of DC (direct current) power at both a low data rate operation and a high data rate operation, which is not in line with general power management strategy at a low data rate operation or a low operation frequency. Thus, it is desired to provide a solution to adaptability switch a high-speed device a reduced power mode at a low data rate operation or a low operation frequency. 
     BRIEF SUMMARY OF THE INVENTION 
     An exemplary embodiment of a buffer is provided. The buffer may selectively operate at a first mode or a second mode. The buffer comprises a first signal input terminal, a first signal output terminal, and a path circuit coupled between the first signal input terminal and the first signal output terminal. The path circuit has a voltage source terminal. In response to the buffer operating at the first mode, a first signal transmission path is formed in the path circuit and between the first signal input terminal and the first signal output terminal. The first signal transmission path is disconnected from the voltage source terminal. 
     One exemplary embodiment of a multiplexer is provided. The multiplexer selectively operates at a first selection state or a second selection state and selectively operates at a first transmission mode or a second mode. The multiplexer comprises a first signal input terminal, a second signal input terminal, a first signal output terminal, and a path circuit coupled between the first and second signal input terminals and the first signal output terminal. The path circuit has voltage source terminal. In response to the buffer operating simultaneously at the first selection state and at the first transmission mode, a first signal transmission path is formed in the path circuit and between the first signal input terminal and the first signal output terminal, and the first signal transmission path is disconnected from the voltage source terminal. In response to the buffer operating simultaneously at the second selection state and at the first transmission mode, a second signal transmission path is formed in the path circuit and between the second signal input terminal and the first signal output terminal, and the second signal transmission path is disconnected from the voltage source terminal. 
     Another exemplary embodiment of a multiplexer is provided. The multiplexer selectively operates at a first selection state or a second selection state and selectively operates at a first transmission mode or a second mode. The multiplexer comprises a first signal input terminal, a first signal output terminal, a second signal output terminal, and a path circuit coupled between the first signal input terminal and the first and second signal output terminals. The path circuit has a voltage source terminal. In response to the buffer operating simultaneously at the first selection state and at the first transmission mode, a first signal transmission path is formed in the path circuit and between the first signal input terminal and the first signal output terminal, and the first signal transmission path is disconnected from the voltage source terminal. In response to the buffer operating simultaneously at the second selection state and at the first transmission mode, a second signal transmission path is formed in the path circuit and between the first signal input terminal and the second signal output terminal, and the second signal transmission path is disconnected from the voltage source terminal. 
     A detailed description is given in the following embodiments with reference to the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein: 
         FIGS. 1A ˜ 1 B show an exemplary embodiment of a buffer; 
         FIGS. 2A ˜ 2 B shows an exemplary embodiment of an operation of the buffer of  FIG. 1  at a passive mode and an active mode; 
         FIGS. 3A ˜ 3 C show one exemplary embodiment of a two-to-one multiplexer; 
         FIGS. 4A ˜ 4 D shows an exemplary embodiment of an operation of the two-to-one multiplexer of  FIGS. 3A ˜ 3 C at a passive mode and an active mode; 
         FIG. 5  shows another exemplary embodiment of a two-to-one multiplexer; 
         FIGS. 6A ˜ 6 C show one exemplary embodiment of a one-to-two multiplexer; 
         FIGS. 7A ˜ 7 D shows an exemplary embodiment of an operation of the one-to-two multiplexer of  FIGS. 6A ˜ 6 C at a passive mode and an active mode; and 
         FIG. 8  shows another exemplary embodiment of a one-to-two multiplexer. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims. 
       FIG. 1A  shows an exemplary embodiment of a buffer. As shown in  FIG. 1 , the buffer  1  comprises two signal input terminals INP 1  and INM 1 , two signal output terminals OUTN 1  and OUTM 1 , and a path circuit  10 . The signal input terminals INP 1  and INM 1  are pair of input terminals for receiving a differential input signal, wherein a positive element signal of the differential input signal is received by the signal input terminal INP 1 , while a negative element signal of the differential input signal is received by the signal input terminal INM 1 . The buffer  1  may selectively operate at a passive mode or an active mode according to the frequency of the differential input signal. When the data rate of the differential input signal is high, the buffer  1  operates at the active; when the data rate of the differential input signal is low, the buffer  1  operates at the passive mode for reducing consumption. The buffer  1  generates a differential output signal at the signal output terminals OUTN 1  and OUTM 1  according to the received differential input signal. The path circuit  10  comprises inductors L 11 ˜L 14 , switches SW 11 ˜SW 14 , resistors R 11 ˜R 12 , and an amplifier A 11 . The inductor L 11  is coupled between the signal input terminal INP 1  and a node N 11 . The switch SW 11  is coupled between the node N 11  and a node N 12 . The inductor L 13  is coupled between the node N 12  and the signal output terminal OUTP 1 . The switch SW 13  is coupled between the voltage source terminal VS 1  and a node N 13 . During the operation of the buffer  1 , an operation voltage VDD is provided to the voltage source terminal VS 1 . The resistor R 11  is coupled between the node N 13  and the node N 12 . The inductor L 12  is coupled between the signal input terminal INM 1  and the node N 14 . The switch SW 12  is coupled between the node N 14  and a node N 15 . The inductor L 14  is coupled between the node N 15  and the signal output terminal OUTM 1 . The switch SW 14  is coupled between the voltage source terminal VS 1  and a node N 16 . The resistor R 12  is coupled between the node N 16  and the node N 15 . A positive input terminal (+) of the amplifier A 11  is coupled to the node N 11 , and a negative input terminal (−) thereof is coupled to the node N 14 . A positive output terminal (+) of the amplifier A 11  is coupled to the signal output terminal OUTP 1 , and a negative output terminal (−) thereof is coupled to the signal output terminal OUTM 1 . 
     In the embodiment, the switches SW 11  and SW 12  are controlled by a switch signal S 11 , while the switches SW 13  and SW 14  are controlled by a switch signal S 12 . The buffer  1  may further comprise a signal generator  11  which operates to generate the switch signal S 11  and  12  based on a mode signal MODEL In an embodiment, the switch signals S 11  and S 12  are out of phase. In other words, the duration when the switches SW 11  and SW 12  does not overlap the duration when the switches SW 13  and SW 14 . The mode signal MODE 1  indicates which one of the passive mode and the active mode the buffer  1  operates at. 
     Referring to  FIG. 2A , when the buffer  1  operates at the passive mode, the switches SW 11  and SW 12  are turned on according to the switch signal S 11 , while the switches SW 13  and SW 14  are turned off according to the switch signal S 12 . Moreover, the amplifier A 11  is disabled. Since the switch SW 11  is turned on, there is a signal transmission path P 21  is formed in the path circuit  10  and between the signal input terminal INP 1  and the signal output terminal OUTP 1  for the positive element signal of the differential input signal. Since the switch SW 12  is turned on, there is a signal transmission path P 22  is formed in the path circuit  10  and between the signal input terminal INM 1  and the signal output terminal OUTM 1  for the negative element signal of the differential input signal. As shown in  FIG. 2A , the switches SW 13  and SW 14  are turned off, and each of the signal transmission paths P 21  and P 22  is disconnected from the voltage source terminal VS 1 . The components L 11 ˜L 14  and SW 11 ˜SW 12  in the signal transmission paths P 21  and P 22  are passive elements. Thus, no direct current (DC) power consumption is required at the passive mode. 
     Referring to  FIG. 2B , when the buffer  1  operates at the active mode, the switches SW 11  and SW 12  are turned off according to the switch signal S 11 , while the switches SW 13  and SW 14  are turned on according to the switch signal S 12 . Moreover, the amplifier A 11  is enabled. Since the switch SW 11  is turned off and the amplifier A 11  is enabled, there is a signal transmission path P 23  is formed in the path circuit  10  and between the signal input terminal INP 1  and the signal output terminal OUTP 1  for the positive element signal of the differential input signal. Since the switch SW 12  is turned off and the amplifier A 11  is enabled, there is a signal transmission path P 24  is formed in the path circuit  10  and between the signal input terminal INM 1  and the signal output terminal OUTM 1  for the negative element signal of the differential input signal. As shown in  FIG. 2B , the switches SW 13  and SW 14  are turned on. Thus, a DC current is provided from the voltage source terminal VS 1  to the signal transmission path P 23  through the switch SW 13 , the resistor R 11  and the inductor L 13 , and a DC current is provided from the voltage source terminal VS 1  to the signal transmission path P 24  through the switch SW 14 , the resistor R 12  and the inductor L 14 , which induces DC power consumption. 
     According to the above embodiment, the buffer  1  can selectively operate at two different modes: a passive mode and an active mode. In cases where the buffer  1  is applied in a high speed device, when the high speed device operates a low data rate for a low frequency signal, the buffer  1  switches to operate at the passive mode to provide a specific signal transmission path for the low frequency signal. The specific signal transmission path is disconnected from the voltage source terminal VS 1 , and only passive components are in the specific signal transmission path. Thus, no DC current is induced, which eliminates DC power consumption. 
     In an embodiment, the structure and operation of the buffer shown in  FIGS. 1A ˜ 1 B can applied in a two-to-one multiplexer.  FIGS. 3A ˜ 3 B show an exemplary embodiment of a two-to-one multiplexer. As shown in  FIG. 3A , a two-to-one multiplexer  3  comprises a pair of signal input terminals IN 1 P and IN 1 M, a pair of signal input terminals IN 2 P and IN 2 M, a pair of signal output terminal OUTP 3  and OUTM 3 , and a path circuit  30 . The signal input terminals IN 1 P and IN 1 M are configured to receive a differential input signal, wherein a positive element signal of this differential input signal is received by the signal input terminal IN 1 P, while a negative element signal thereof is received by the signal input terminal IN 1 M. The signal input terminals IN 2 P and IN 2 M are configured to receive another differential input signal, wherein a positive element signal of this differential input signal is received by the signal input terminal IN 2 P, while a negative element signal thereof is received by the signal input terminal IN 2 M. According to a selection signal SEL 3 , the two-to-one multiplexer  3  operates at a first selection state to select the differential input signal at the pair of signal input terminals IN 1 P and IN 1 M or at a second selection state to select the differential input signal at the pair of signal input terminals IN 2 P and IN 2 M and then transmits the selected differential input signal to the pair of signal output terminal OUTP 3  and OUTM 3  as a differential output signal. Moreover, the two-to-one multiplexer  3  may be controlled by a mode signal MODE 3  to selectively operate at a passive mode or an active mode according to the frequency of the selected differential input signal. When the data rate of the selected differential input signal is high, the two-to-one multiplexer  3  operates at the active; when the data rate of the selected differential input signal is low, the two-to-one multiplexer  3  operates at the passive mode for reducing consumption. 
     Referring to  FIG. 3B , the path circuit  30  comprises inductors L 31 ˜L 36 , switches SW 31 ˜SW 36 , resistors R 31 ˜R 32 , and amplifiers A 31 ˜A 32 . The inductor L 31  is coupled between the signal input terminal IN 1 P and a node N 31 . The switch SW 31  is coupled between the node N 31  and a node N 32 . The inductor L 33  is coupled between the node N 32  and the signal output terminal OUTP 3 . The switch SW 33  is coupled between the voltage source terminal VS 3  and a node N 33 . During the operation of the two-to-one multiplexer  3 , an operation voltage VDD is provided to the voltage source terminal VS 3 . The resistor R 31  is coupled between the node N 33  and the node N 32 . The inductor L 32  is coupled between the signal input terminal IN 1 M and the node N 35 . The switch SW 32  is coupled between the node N 35  and a node N 36 . The inductor L 34  is coupled between the node N 36  and the signal output terminal OUTM 3 . The switch SW 34  is coupled between the voltage source terminal VS 3  and a node N 37 . The resistor R 32  is coupled between the node N 37  and the node N 36 . A positive input terminal (+) of the amplifier A 31  is coupled to the node N 31 , and a negative input terminal (−) thereof is coupled to the node N 35 . A positive output terminal (+) of the amplifier A 31  is coupled to the signal output terminal OUTP 3 , and a negative output terminal (−) thereof is coupled to the signal output terminal OUTM 3 . 
     The inductor L 35  is coupled between the signal input terminal IN 2 P and a node N 34 . The switch SW 35  is coupled between the node N 34  and the node N 32 . The inductor L 36  is coupled between the signal input terminal IN 2 M and a node N 38 . The switch SW 36  is coupled between the node N 38  and the node N 36 . A positive input terminal (+) of the amplifier A 32  is coupled to the node N 34 , and a negative input terminal (−) thereof is coupled to the node N 38 . A positive output terminal (+) of the amplifier A 32  is coupled to the signal output terminal OUTP 3 , and a negative output terminal (−) thereof is coupled to the signal output terminal OUTM 3 . 
     In the embodiment, the switches SW 31  and SW 32  are controlled by a switch signal S 31 , the switches SW 33  and SW 34  are controlled by a switch signal S 32 , and the switches SW 35  and SW 36  are controlled by a switch signal S 33 . The two-to-one multiplexer  3  may further comprise a signal generator  31  which operates to generate the switch signal S 31 ˜S 33  based on the selection signal SEL 3  and the mode signal MODE 3 . The selection signal SEL 3  indicates which differential input signal is selected, and the mode signal MODE 3  indicates which one of the passive mode and the active mode the two-to-one multiplexer  3  operates at according to the frequency of the selected differential input signal. 
     Referring to  FIG. 4A , when the two-to-one multiplexer  3  operates simultaneously at the first selection state (for selecting the differential input signal at the pair of signal input terminals IN 1 P and IN 1 M) and at the passive mode, the switches SW 31  and SW 32  are turned on according to the switch signal S 31 , the switches SW 33  and SW 34  are turned off according to the switch signal S 32 , and the switches SW 35  and SW 36  are turned off according to the switch signal S 33 . Moreover, the amplifier A 31  and A 32  are disabled. Since the switches SW 31  is turned on, there is a signal transmission path P 41  is formed in the path circuit  30  and between the signal input terminal IN 1 P and the signal output terminal OUTP 3  for the positive element signal of the differential input signal at the signal input terminal IN 1 P. Since the switch SW 32  is turned on, there is a signal transmission path P 42  is formed in the path circuit  30  and between the signal input terminal IN 1 M and the signal output terminal OUTM 3  for the negative element signal at the signal input terminal IN 1 M. As shown in  FIG. 4A , the switches SW 33  and SW 34  are turned off, and each of the signal transmission paths P 41  and P 42  is disconnected from the voltage source terminal VS 3 . The components L 31 ˜L 34  and SW 31 ˜SW 32  in the signal transmission paths P 41  and P 42  are passive elements. Thus, no DC power consumption is required simultaneously at the first selection state and at the passive mode. 
     Referring to  FIG. 4B , when the two-to-one multiplexer  3  operates simultaneously at the first selection state and at the active mode, the switches SW 31  and SW 32  are turned off according to the switch signal S 31 , the switches SW 33  and SW 34  are turned on according to the switch signal S 32 , and the switches SW 35  and SW 36  are turned off according to the switch signal S 33 . Moreover, the amplifier A 31  is enabled, while the amplifier A 32  is disabled. Since the switch SW 31  is turned off and the amplifier A 31  is enabled, there is a signal transmission path P 43  is formed in the path circuit  30  and between the signal input terminal IN 1 P and the signal output terminal OUTP 3  for the positive element signal at the signal input terminal IN 1 P. Since the switch SW 32  is turned off and the amplifier A 31  is enabled, there is a signal transmission path P 44  is formed in the path circuit  30  and between the signal input terminal IN 1 M and the signal output terminal OUTM 3  for the negative element signal at the signal input terminal IN 1 M. As shown in  FIG. 4B , the switches SW 33  and SW 34  are turned on. Thus, a DC current is provided from the voltage source terminal VS 3  to the signal transmission path P 43  through the switch SW 33 , the resistor R 31  and the inductor L 33 , and a DC current is provided from the voltage source terminal VS 3  to the signal transmission path P 44  through the switch SW 34 , the resistor R 32  and the inductor L 34 , which induces DC power consumption. 
     Referring to  FIG. 4C , when the two-to-one multiplexer  3  operates simultaneously at the second selection state (for selecting the differential input signal at the pair of signal input terminals IN 2 P and IN 2 M) and at the passive mode, the switches SW 35  and SW 36  are turned on according to the switch signal S 33 , the switches SW 33  and SW 34  are turned off according to the switch signal S 32 , and the switches SW 31  and SW 32  are turned off according to the switch signal S 31 . Moreover, the amplifier A 31  and A 32  are disabled. Since the switches SW 35  is turned on, there is a signal transmission path P 45  is formed in the path circuit  30  and between the signal input terminal IN 2 P and the signal output terminal OUTP 3  for the positive element signal of the differential input signal at the signal input terminals IN 2 P. Since the switch SW 36  is turned on, there is a signal transmission path P 46  is formed in the path circuit  30  and between the signal input terminal IN 2 M and the signal output terminal OUTM 3  for the negative element signal at the signal input terminal IN 2 M. As shown in  FIG. 4C , the switches SW 33  and SW 34  are turned off, and each of the signal transmission paths P 45  and P 46  is disconnected from the voltage source terminal VS 3 . The components L 33 ˜L 36  and SW 35 ˜SW 36  in the signal transmission paths P 45  and P 46  are passive elements. Thus, no DC power consumption is required simultaneously at the first selection state and at the passive mode. 
     Referring to  FIG. 4D , when the two-to-one multiplexer  3  operates simultaneously at the second selection state and at the active mode, the switches SW 35  and SW 36  are turned off according to the switch signal S 33 , the switches SW 33  and SW 34  are turned on according to the switch signal S 32 , and the switches SW 31  and SW 32  are turned off according to the switch signal S 31 . Moreover, the amplifier A 32  is enabled, while the amplifier A 31  is disabled. Since the switch SW 35  is turned off and the amplifier A 32  is enabled, there is a signal transmission path P 47  is formed in the path circuit  30  and between the signal input terminal IN 2 P and the signal output terminal OUTP 3  for the positive element signal at the signal input terminal IN 2 P. Since the switch SW 36  is turned off and the amplifier A 32  is enabled, there is a signal transmission path P 48  is formed in the path circuit  30  and between the signal input terminal IN 2 M and the signal output terminal OUTM 3  for the negative element signal at the signal input terminal IN 2 M. As shown in  FIG. 4D , the switches SW 33  and SW 34  are turned on. Thus, a DC current is provided from the voltage source terminal VS 3  to the signal transmission path P 47  through the switch SW 33 , the resistor R 31  and the inductor L 33 , and a DC current is provided from the voltage source terminal VS 3  to the signal transmission path P 48  through the switch SW 34 , the resistor R 32  and the inductor L 34 , which induces DC power consumption. 
     According to the above embodiment, the two-to-one multiplexer  3  can selectively operate at two different modes: a passive mode and an active mode. In cases where the two-to-one multiplexer  3  is applied in a high speed device, when the high speed device operates a low data rate for a low frequency differential input signal, the two-to-one multiplexer  3  switches to operate at the passive mode to provide a specific signal transmission path for the low frequency differential input signal. The specific signal transmission path is disconnected from the voltage source terminal VS 3 , and only passive components are in the specific signal transmission path. Thus, no DC current is induced, which eliminates DC power consumption. 
       FIG. 5  shows a detailed structure of the path circuit  30  of the two-to-one multiplexer  3 . Each of the switches SW 31 , SW 32 , SW 35 , and SW 36  is implemented by a T switch. As shown in  FIG. 5 , the switch SW 31  comprises N-type transistors T 311 ˜T 313 , and the switch SW 32  comprises N-type transistors T 321 ˜T 323 . The gates of the transistors T 311 ˜T 312  and T 321 ˜T 322  receive the switch signal S 31 , and the gates of the transistors T 313  and T 323  receive a signal which is inverse to the switch signal S 31 . The switch SW 35  comprises N-type transistors T 351 ˜T 353 , and the switch SW 36  comprises N-type transistors T 361 ˜T 363 . The gates of the transistors T 351 ˜T 352  and T 361 ˜T 362  receive the switch signal S 33 , and the gates of the transistors T 353  and T 363  receive a signal which is inverse to the switch signal S 33 . The switch SW 33  comprises a P-type transistor T 331 , and the switch SW 34  comprises a P-type transistor T 341 . The gates of the transistors T 331  and T 341  receive the switch signal S 32 . 
     In the embodiment of  FIG. 5 , the amplifiers A 31 ˜A 32  are combined together and implemented by a circuit  50 . As shown in  FIG. 5 , the circuit  50  comprises N-type transistors T 51 ˜T 56 , capacitors C 51 ˜C 56 , resistors R 51 ˜R 58 , and bias terminals VB 51 ˜VB 52 . When a bias voltage is provided to the terminal VB 51  and the transistors T 55 ˜T 56  are turned on, the amplifier A 31  is enabled; otherwise, the amplifier A 31  is disabled. When a bias voltage is provided to the terminal VB 52  and the transistors T 55 ˜T 56  are turned on, the amplifier A 32  is enabled; otherwise, the amplifier A 32  is disabled. 
     In an embodiment, the structure and operation of the buffer shown in  FIGS. 1A ˜ 1 B can applied in a one-to-two multiplexer.  FIGS. 6A ˜ 6 B show an exemplary embodiment of a one-to-two multiplexer. As shown in  FIG. 3A , a one-to-two multiplexer  6  comprises a pair of signal input terminals INP 6  and INM 6 , a pair of signal output terminals OUT 1 P and OUT 1 M, a pair of signal output terminal OUT 2 P and OUT 2 M, and a path circuit  60 . The signal input terminals INP 6  and INM 6  are configured to receive a differential input signal, wherein a positive element signal of this differential input signal is received by the signal input terminal INP 6 , while a negative element signal thereof is received by the signal input terminal INM 6 . According to a selection signal SEL 6 , the one-to-two multiplexer  6  operates at a first selection state to transmit the differential input signal at the pair of signal input terminals INP 6  and INM 6  to the pair of signal output terminal OUT 1 P and OUT 1 M or at a second selection state to transmit the differential input signal at the pair of signal input terminals INP 6  and INM 6  to the pair of signal output terminal OUT 2 P and OUT 2 M as a differential output signal. Moreover, the one-to-two multiplexer  6  may be controlled by a mode signal MODE 6  to selectively operate at a passive mode or an active mode according to the frequency of the differential input signal. When the data rate of the differential input signal is high, the one-to-two multiplexer  6  operates at the active; when the data rate of the differential input signal is low, the one-to-two multiplexer  6  operates at the passive mode for reducing consumption. 
     Referring to  FIG. 6B , the path circuit  60  comprises inductors L 61 ˜L 66 , switches SW 61 ˜SW 68 , resistors R 61 ˜R 62 , and amplifiers A 61 ˜A 62 . The inductor L 61  is coupled between the signal input terminal INP 6  and a node N 61 . The switch SW 61  is coupled between the node N 61  and a node N 62 . The inductor L 63  is coupled between the node N 32  and the signal output terminal OUT 1 P. The switch SW 63  is coupled between the voltage source terminal VS 6  and a node N 63 . During the operation of the one-to-two multiplexer  6 , an operation voltage VDD is provided to the voltage source terminal VS 6 . The resistor R 61  is coupled between the node N 63  and the node N 62 . The inductor L 62  is coupled between the signal input terminal INM 7  and the node N 66 . The switch SW 62  is coupled between the node N 66  and a node N 67 . The inductor L 64  is coupled between the node N 67  and the signal output terminal OUT 1 M. The switch SW 64  is coupled between the voltage source terminal VS 6  and a node N 68 . The resistor R 62  is coupled between the node N 68  and the node N 67 . A positive input terminal (+) of the amplifier A 61  is coupled to the node N 61 , and a negative input terminal (−) thereof is coupled to the node N 66 . A positive output terminal (+) of the amplifier A 61  is coupled to the signal output terminal OUT 1 P, and a negative output terminal (−) thereof is coupled to the signal output terminal OUT 1 M. 
     The switch SW 65  is coupled between the node N 61  and the node N 64 . The inductor L 65  is coupled between the node N 64  and the signal output terminal OUT 2 P. The switch SW 67  is coupled between the voltage source terminal VS 6  and a node N 65 . The resistor R 63  is coupled between the node N 65  and the node N 64 . The switch SW 66  is coupled between the node N 66  and the node N 69 . The inductor L 66  is coupled between the node N 69  and the signal output terminal OUT 2 P. The switch SW 68  is coupled between the voltage source terminal VS 6  and a node N 80 . The resistor R 66  is coupled between the node N 60  and the node N 69 . A positive input terminal (+) of the amplifier A 62  is coupled to the node N 61 , and a negative input terminal (−) thereof is coupled to the node N 66 . A positive output terminal (+) of the amplifier A 62  is coupled to the signal output terminal OUT 2 P, and a negative output terminal (−) thereof is coupled to the signal output terminal OUT 2 M. 
     In the embodiment, the switches SW 61  and SW 62  are controlled by a switch signal S 61 , the switches SW 63  and SW 64  are controlled by a switch signal S 62 , the switches SW 65  and SW 66  are controlled by a switch signal S 63 , and the switches SW 67  and SW 68  are controlled by a switch signal S 64 . The one-to-two multiplexer  6  may further comprise a signal generator  61  which operates to generate the switch signal S 61 ˜S 64  based on the selection signal SEL 6  and the mode signal MODE 6 . The selection signal SEL 6  indicates which pair of signal output terminals the differential input signal is transmitted to, and the mode signal MODE 6  indicates which one of the passive mode and the active mode the one-to-two multiplexer  6  operates at according to the frequency of the differential input signal. 
     Referring to  FIG. 7A , when the one-to-two multiplexer  6  operates simultaneously at the first selection state (for transmitting the differential input signal to the pair of signal output terminals OUT 1 P and OUT 1 M) and at the passive mode, the switches SW 61  and SW 62  are turned on according to the switch signal S 61 , the switches SW 63  and SW 64  are turned off according to the switch signal S 62 , the switches SW 65  and SW 66  are turned off according to the switch signal S 63 , and the switches SW 67  and SW 68  are turned off according to the switch signal S 64 . Moreover, the amplifier A 61  and A 62  are disabled. Since the switches SW 61  is turned on, there is a signal transmission path P 71  is formed in the path circuit  60  and between the signal input terminal INP 6  and the signal output terminal OUT 1 P for the positive element signal of the differential input signal at the signal input terminal INP 6 . Since the switch SW 62  is turned on, there is a signal transmission path P 62  is formed in the path circuit  60  and between the signal input terminal INM 6  and the signal output terminal OUT 1 M for the negative element signal at the signal input terminal INM 6 . As shown in  FIG. 7A , the switches SW 63  and SW 64  are turned off, and each of the signal transmission paths P 71  and P 72  is disconnected from the voltage source terminal VS 6 . The components L 61 ˜L 64  and SW 61 ˜SW 62  in the signal transmission paths P 71  and P 72  are passive elements. Thus, no DC power consumption is required simultaneously at the first selection state and at the passive mode. 
     Referring to  FIG. 7B , when the one-to-two multiplexer  6  operates simultaneously at the first selection state and at the active mode, the switches SW 61  and SW 62  are turned off according to the switch signal S 61 , the switches SW 63  and SW 64  are turned on according to the switch signal S 62 , the switches SW 65  and SW 66  are turned off according to the switch signal S 64 , and the switches SW 67  and SW 68  are turned off according to the switch signal S 64 . Moreover, the amplifier A 61  is enabled, while the amplifier A 62  is disabled. Since the switch SW 61  is turned off and the amplifier A 61  is enabled, there is a signal transmission path P 73  is formed in the path circuit  60  and between the signal input terminal INP 6  and the signal output terminal OUT 1 P for the positive element signal at the signal input terminal INP 6 . Since the switch SW 62  is turned off and the amplifier A 61  is enabled, there is a signal transmission path P 74  is formed in the path circuit  60  and between the signal input terminal INM 6  and the signal output terminal OUT 1 M for the negative element signal at the signal input terminal INM 6 . As shown in  FIG. 7B , the switches SW 63  and SW 64  are turned on. Thus, a DC current is provided from the voltage source terminal VS 6  to the signal transmission path P 73  through the switch SW 63 , the resistor R 61  and the inductor L 63 , and a DC current is provided from the voltage source terminal VS 6  to the signal transmission path P 74  through the switch SW 63 , the resistor R 62  and the inductor L 64 , which induces DC power consumption. 
     Referring to  FIG. 7C , when the one-to-two multiplexer  6  operates simultaneously at the second selection state (for transmitting the differential input signal to the pair of signal input terminals OUT 2 P and OUT 2 M) and at the passive mode, the switches SW 65  and SW 66  are turned on according to the switch signal S 63 , the switches SW 67  and SW 67  are turned off according to the switch signal S 64 , the switches SW 61  and SW 62  are turned off according to the switch signal S 61 , and the switches SW 63  and SW 64  are turned off according to the switch signal S 62 . Moreover, the amplifier A 61  and A 62  are disabled. Since the switches SW 65  is turned on, there is a signal transmission path P 75  is formed in the path circuit  60  and between the signal input terminal INP 6  and the signal output terminal OUT 2 P for the positive element signal of the differential input signal at the signal input terminals INP 6 . Since the switch SW 66  is turned on, there is a signal transmission path P 76  is formed in the path circuit  60  and between the signal input terminal INM 6  and the signal output terminal OUT 2 M for the negative element signal at the signal input terminal INM 6 . As shown in  FIG. 7C , the switches SW 67  and SW 68  are turned off, and each of the signal transmission paths P 75  and P 76  is disconnected from the voltage source terminal VS 7 . The components L 61 ˜L 62  and L 65 ˜L 66  and SW 35 ˜SW 36  in the signal transmission paths P 75  and P 76  are passive elements. Thus, no DC power consumption is required simultaneously at the first selection state and at the passive mode. 
     Referring to  FIG. 7D , when the one-to-two multiplexer  6  operates simultaneously at the second selection state and at the active mode, the switches SW 65  and SW 66  are turned off according to the switch signal S 73 , the switches SW 67  and SW 67  are turned on according to the switch signal S 64 , the switches SW 61  and SW 62  are turned off according to the switch signal S 61 , and the switches SW 63  and SW 64  are turned off according to the switch signal S 62 . Moreover, the amplifier A 62  is enabled, while the amplifier A 61  is disabled. Since the switch SW 65  is turned off and the amplifier A 62  is enabled, there is a signal transmission path P 87  is formed in the path circuit  60  and between the signal input terminal INP 6  and the signal output terminal OUT 2 P for the positive element signal at the signal input terminal INP 6 . Since the switch SW 66  is turned off and the amplifier A 62  is enabled, there is a signal transmission path P 78  is formed in the path circuit  60  and between the signal input terminal INM 6  and the signal output terminal OUT 2 M for the negative element signal at the signal input terminal INM 6 . As shown in  FIG. 7D , the switches SW 67  and SW 68  are turned on. Thus, a DC current is provided from the voltage source terminal VS 6  to the signal transmission path P 77  through the switch SW 67 , the resistor R 63  and the inductor L 65 , and a DC current is provided from the voltage source terminal VS 6  to the signal transmission path P 78  through the switch SW 68 , the resistor R 64  and the inductor L 66 , which induces DC power consumption. 
     According to the above embodiment, the one-to-two multiplexer  6  can selectively operate at two different modes: a passive mode and an active mode. In cases where the one-to-two multiplexer  6  is applied in a high speed device, when the high speed device operates a low data rate for a low frequency differential input signal, the one-to-two multiplexer  6  switches to operate at the passive mode to provide a specific signal transmission path for the low frequency differential input signal. The specific signal transmission path is disconnected from the voltage source terminal VS 6 , and only passive components are in the specific signal transmission path. Thus, no DC current is induced, which eliminates DC power consumption. 
       FIG. 8  shows a detailed structure of the path circuit  60  of the one-to-two multiplexer  6 . Each of the switches SW 61 , SW 62 , SW 65 , and SW 66  is implemented by a T switch. As shown in  FIG. 8 , the switch SW 61  comprises N-type transistors T 611 ˜T 613 , and the switch SW 62  comprises N-type transistors T 621 ˜T 623 . The gates of the transistors T 611 ˜T 612  and T 621 ˜T 622  receive the switch signal S 61 , and the gates of the transistors T 613  and T 623  receive a signal which is inverse to the switch signal S 61 . The switch SW 65  comprises N-type transistors T 651 ˜T 653 , and the switch SW 66  comprises N-type transistors T 661 ˜T 663 . The gates of the transistors T 651 ˜T 652  and T 661 ˜T 662  receive the switch signal S 63 , and the gates of the transistors T 653  and T 663  receive a signal which is inverse to the switch signal S 63 . The switch SW 63  comprises a P-type transistor T 631 , and the switch SW 64  comprises a P-type transistor T 641 . The gates of the transistors T 631  and T 641  receive the switch signal S 62 . The switch SW 67  comprises a P-type transistor T 671 , and the switch SW 68  comprises a P-type transistor T 681 . The gates of the transistors T 671  and T 681  receive the switch signal S 64 . 
     In the embodiment of  FIG. 8 , the amplifiers A 61 ˜A 62  are combined together and implemented by a circuit  80 . As shown in  FIG. 8 , the circuit  80  comprises N-type transistors T 81 ˜T 586  capacitors C 81 ˜C 83 , resistors R 81 ˜R 85 , and a bias terminal VB 8 . When a bias voltage is provided to the terminal VB 8  and the transistors T 81  and T 83  are turned on, the amplifier A 61  is enabled; otherwise, the amplifier A 61  is disabled. When a bias voltage is provided to the terminal VB 8  and the transistors T 82  and T 84  are turned on, the amplifier A 62  is enabled; otherwise, the amplifier A 62  is disabled. 
     While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.