Patent Publication Number: US-4653106-A

Title: Indentation hardness meter

Description:
TECHNICAL FIELD 
     The present invention relates to an indentation hardness meter which impresses an indenter into a specimen of a metallic material or the like to make therein a quadrangular pyramidal or spherical impression and measures the hardness of the specimen by measuring the lengths of first and second diagonals of the quadrangular pyramidal impression or diameter of the spherical impression. 
     BACKGROUND ART 
     As the abovesaid type of indentation hardness meter, there has heretofore been proposed such an arrangement in which a quadrangular pyramidal impression made in a specimen is imaged by scanning through the use of a scanning image sensing device, first and second diagonal-length signals representing the lengths of first and second diagonals of the impression are obtained from the image output and a hardness signal representing the hardness of the specimen is derived from the first and second diagonal-length signals. 
     The conventional indentation hardness meter of such an arrangement possesses, however, defects that a complex, bulky and expensive scanning image sensing device is needed which is capable of imaging the impression by scanning its entire area two-dimesionally, that the arrangement for obtaining the first and second diagonal-length signals from the image output of the scanning image sensing device is extremely complex and that a relatively long period of time is required for obtaining the first and second diagonal-length signals. 
     DISCLOSURE OF THE INVENTION 
     According to the present invention, an indentation made in a specimen is imaged by scanning through a one-dimensional scanning image sensing device and, in the case of the indentation being quadrangular pyramidal, signals representing the lengths of its diagonals are produced and, in the case of the indentation being spherical, a signal representing its diameter is generated. 
     The scanning by the one-dimensional scanning image sensing device in this case does not cover the entire area of the impression but covers its area of a smaller width which contains its diagonals in the case of the impression being quadrangular pyramidal and its diameter in the case of the impression being spherical. 
     Therefore, the present invention is free from the abovesaid defects of the prior art. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic sectional view illustrating an example of the mechanical system of a first embodiment of the indentation hardness meter of the present invention; 
     FIG. 2 is a sectional view taken on the line II--II in FIG. 1; 
     FIG. 3 is a diagram showing an indentation made in a specimen; 
     FIG. 4 is a diagram explanatory of imaging of the specimen by one-dimensional scanning through a one-dimensional image sensing device; and includes waveform diagrams explanatory of one-dimensional scanning of the specimen; 
     FIG. 5 is a systematic connection diagram illustrating an example of the electrical system of the first embodiment of the indentation hardness meter of the present invention in the case of using the mechanical system show in FIGS. 1 and 2; 
     FIGS. 6, 7 and 8 are signal arrangement diagrams explanatory of the electrical system shown in FIG. 5; 
     FIG. 9 is a schematic sectional view illustrating an example of the mechanical system of a second embodiment of the indentation hardness meter of the present invention; 
     FIG. 10 is a sectional view taken on the line II--II in FIG. 9; 
     FIG. 11 is a diagram explanatory of imaging a specimen by one-dimensional scanning through the one-dimensional image sensing device; 
     FIG. 12 is a systematic connection diagram illustrating the electrical system of the second embodiment of the indentation hardness meter of the present invention in the case of employing the mechanical system shown in FIGS. 9 and 10; and 
     FIGS. 13 and 14 are signal arrangement diagrams explanatory of the electrical system shown in FIG. 12. 
    
    
     BEST MODE FOR CARRYING OUT THE INVENTION 
     Embodiment 1 
     A description will be given first of a first embodiment of the indentation hardness meter of the present invention. 
     FIGS. 1 and 2 illustrate an example of the mechanical arrangement of the indentation hardness meter of the present invention, which is provided with a vertically movable specimen table 1. 
     As in an ordinary indentation hardness meter, the specimen table 1 holds thereon a specimen 2 for impression thereinto an indenter (not shown) to make therein such a quadrangular pyramidal indentation 3 as shown in FIG. 3, and this specimen table has such a structure as described below. 
     That is, a tubular member 5 is fixedly mounted on a base 4, and another tubular member 6 carrying at its free end the abovesaid specimen table 1 is received in the tubular member 5 in a manner to be movable up and down. In this case, the inner peripheral surface of the inner end of the tubular member 6 has cut therein screw threads 7. 
     On the other hand, a threaded shaft 9, which threadedly engages the female screw 7 of the abovesaid tubular member 6 and carries at the free end a gear 8, is pivotally secured to the base 4. 
     Further, a motor 10 is mounted on the base 4, and its rotary shaft 11 is connected to the threaded shaft 9 through a gear 12 affixed to the rotary shaft, a gear 13 pivotally secured to the base 4 and the abovesaid gear 8 mounted on the threaded shaft 9. 
     Accordingly, when the motor 10 is driven to rotate in the forward direction, the threaded shaft 9 is rotated in the forward direction to raise the tubular member 6, and consequently the specimen table 1 moves up. 
     When the motor 10 is driven in the reverse direction, the threaded shaft 9 rotates in the reverse direction to lower the tubular member 6, and consequently, the specimen table 1 moves down. 
     Moreover, the illustrated example of the mechanical system of the first embodiment of the indentation hardness meter of the present invention has a image sensing device mount 20. 
     The image sensing device mount 20 has a movable board 22 having mounted thereon a one-dimensional scanning image sensing device 21 and a holder 23 which movably supports the movable board 22. 
     The holder 23 comprises a tubular portion 24, an annular portion 25 which is formed integrally with its upper end portion to extend therefrom outwardly in the radial direction, a tubular portion 26 which is formed integrally with the outer marginal portion of the annular portion 25 to extend therefrom upwardly, and a plate portion 27 which is formed integrally with the upper end portion of the tubular portion 26 to extend therefrom inwardly in the radial direction. In this case, a gear 28 is provided on the outer peripheral surface of the tubular portion 24. Further, the plate portion 27 has made therein a slit 29. 
     Such a holder 23 is rotatably mounted on a tubular member 41, with its tubular portion 24 loosely receiving the upper end portion of the tubular member 41 and the lower end face of the tubular portion 24 resting on an annular plate 42 which is formed integrally with the outer peripheral portion of the tubular member 41 to extend therefrom outwardly in the radial direction. 
     On the other hand, a support 40 is fixedly mounted on the aforesaid base 4, and a motor 30 is mounted on the support 40. 
     Further, a rotary shaft 31 of the motor 30 is connected to the holder 23 through a gear 32 mounted on the rotary shaft and the abovesaid gear 28 provided on the tubular portion 24 of the holder 23. 
     Accordingly, when the motor 30 is driven to rotate in the forward direction, the holder 23 is rotated in the forward diection, and when the motor 30 is driven in the reverse direction, the holder 23 rotates in the reverse direction. 
     The aforementioned movable board 22 is disposed between the annular portion 25 and the plate portion 27 of the holder 23 in a manner to be movable along a line b--b which passes through the axis a of the holder 23 and intersects it at right angles thereto. 
     Further, the movable board 22 has a rod 33 formed integrally therewith to extend upwardly thereof. 
     The rod 33 extends upwardly through the slit 29 made in the plate portion 27 of the holder 23. 
     Furthermore the free end of the rod 33 has cut therein a female screw 34 which extends on a line parallel to the line b--b in a plane intersecting the axis a of the holder 23. 
     On the other hand, a motor 35 is mounted on the plate portion 27 of the holder 23, and its rotary shaft 36 has cut screw threads 37 for threaded engagement with the female screw 34 of the rod 33. 
     Accordingly, when the motor 35 is driven to rotate in the forward direction, the movable board 22 moves in a first direction along the line b--b perpendicular to the axis a of the holder 23, and when the motor 35 is driven in the reverse direction, the movable board 22 moves along the line b--b perpendicular to the axis a of the holder 23 in a second direction reverse from the first direction. 
     Furthermore the aforementioned one-dimensional scanning image sensing device 21 has such an arrangement that many (2 n+1 ) solid-state image sensors (photoelectric transducers) E n  &#39;, E n-1  &#39;, . . . E 1  &#39;, E 0&#39;   E 1&#39;   E 2&#39;  . . . E n  are electrically connected in series one after another and are one-dimensionally aligned in a line, as will be evident from FIG. 5. 
     Such a one-dimensional scanning image sensing device 21 is mounted on the underside of the movable board 22 so that the line of arrangement on which the solid-state image sensors E n  &#39; to E 1  &#39;, E 0&#39;   E 1  to E n  are aligned extends across the axis a of the holder 23 and agree with a line c--c perpendicular to the line b--b, as viewed from the direction along the axis a of the holder 23. 
     Further, the annular portion 25 of the holder 23 has planted thereon an engaging pin 38 which extends downwardly thereof. 
     On the other hand, there are mounted on the aforementioned annular plate 42 switches 39 and 39&#39; which are activated when engaged with the engaging pin 38 planted on the holder 23. These switches 39 and 39&#39; are spaced apart an angular distance of 90° relative to the axis a of the holder 23. 
     Moreover, the aforesaid tubular member 41 is secured to a support 40 mounted on the base 4. 
     The tubular member 41 is mounted on the support 40 so that its axis d extends in the direction of vertical movement of the specimen table 1 and its one end bear a face-to-face relation to the specimen table 1. 
     Besides, the tubular member 41 has the annular plate 42 which is formed integrally therewith to extend outwardly in the radial direction thereof. 
     The tubular member 41 and the annular plate 42 rotatably support the holder 23, with the tubular member 24 receiving the tubular member 41 and the lower end face of the tubular member 24 of the holder 23 resting on the annular plate 42. 
     Accordingly, the axis a of the holder 23 is in agreement with the axis d of the tubular member 41. 
     Furthermore, the tubular member 41 has on one side thereof a tubular member 43 communicating therewith, and a light source 44 is disposed in the tubular member 43. 
     Light from the light source 44 is directed to the specimen 2 placed on the specimen table 1 through a lens 45 provided in the tubular member 42, half-mirror 46 provided in the tubular member 41 and a lens 47 provided in the tubular member 41, and the reflected light is directed to the one-dimensional scanning image sensing device 21 through the lens 47 and the half-mirror 46. 
     The foregoing has clarified an example of the mechanical system of the first embodiment of the indentation hardness meter of the present invention. 
     Next, a description will be given, with reference to FIG. 5, an example of the electrical system of the first embodiment of the indentation hardness meter of the present invention and its operation. 
     By applying the light from the light source 44 via the lens 45, the half-mirror 46 and the lens 47 to the specimen 2 and by applying the reflected light therefrom to the one-dimensional scanning image sensing device 21 via the lens 47 and the half-mirror 46, as described above, an image output (hereinafter identified generally by S) obtained by one-dimensional scanning of the specimen is provided from the one-dimensional scanning image sensing device 21. 
     In this case, as shown in FIG. 5, the one-dimensional scanning image sensing device 21 is driven under the control of clock pulses CP from a clock pulse generator 50, such as depicted in FIG. 4B. 
     Incidentally, the one-dimensional scanning image sensing device 21 has such as arrangement that the many solid-state image sensors E n  &#39;, E.sub.(n-1) &#39;, . . . E 1  &#39;, E 0&#39;  E 1&#39;  E 2&#39;  . . . E n  are electrically connected in series one after another and one-dimensionally aligned in a line on the aforesaid line c--c, as referred to previously. 
     Accordingly, the image output S is obtained as photoelectric conversion outputs S n  &#39;, S.sub.(n-1) &#39;, . . . S 1  &#39;, S 0&#39;  S 1&#39;  S 2&#39;  . . . S n  which are sequentially provided, by the respective scanning of the one-dimensional scanning image sensing device 21, from the solid-state image sensors E n  &#39;, E.sub.(n-1) &#39;, . . . E 1  &#39;, E 0&#39;  E 1&#39;  E 2&#39;  . . . E n&#39;  respectively. 
     Now, let a line, which extends in a plane containing the surface of the specimen 2 and contains a diagonal joining a pair of opposing points PX and PX&#39; of the impression 3 made in the specimen 2 on the specimen table 1 as shown in FIG. 3 (which diagonal will hereinafter be referred to as a first diagonal), be represented by LX 0  as shown in FIG. 4A, and let a line, which contains a diagonal joining the other pair of opposing points PY and PY&#39; (which diagonal will hereinafter be referred to as a second diagonal), be represented by LY 0 . Further, let an intersecting point of the lines LX 0  and LY 0  be represented by 0. Let a plurality m of lines, which extend in the plane containing the surface of the specimen 2 and in parallel to the line LX 0  and which are sequentially arranged at equal intervals e in a direction perpendicular to the line LX 0  on the side of the point PY with respect thereto over a range which is equal to one half of a width f smaller than the lengths of the abovesaid first and second diagonals (identified by NX and NY, respectively), that is, equal to f/2, be represented by LX 1 , LX 2&#39;  . . . LX m&#39;  respectively, as shown in FIG. 4A. Let a plurality m of lines, which are sequentially arranged in parallel to the line LX 0  and at equal intervals e in the direction perpendicular to the line LX 0  on the side of the point PY&#39; with respect thereto over the range equal to the abovesaid width f/2, be represented by LX 1 , LX 2  &#39;, . . . LX m  &#39;, respectively. 
     Similarly, let a plurality m of lines, which are sequentially arranged in parallel to the line LY 0  and at equal intervals e in a direction perpendicular to the line LY 0  on the side of the point PX with respect thereto over a range equal to the abovesaid width f/2, be represented by LY 1 , LY 2 , . . . LY m , respectively. Further, let a plurality of lines, which are sequentially aranged in parallel to the line LY 0  and at equal intervals e in the direction perpendicular to the line LY 0  on the side of the point PX&#39; with respect thereto over a range equal to the abovesaid width f/2, be represented by LY 1  &#39;, LY 2  &#39;, . . . LY m  &#39;, respectively. 
     Now, let it be assumed that the holder 23 having mounted thereon the one-dimensional scanning image sensing device 21 assumes its rotational position (which will hereinafter be referred to as a first rotational position), with the engaging pin 38 held in engagement with the switch 39 mounted on the annular plate 42, as shown in FIG. 2, and that the specimen 2 is preadjusted in position on the specimen table 1 so that the aforementioned line of arrangement c--c of the solid-state image sensors E n  &#39; to E 1  &#39; E 0  and E 1  to E n  of the one-dimensional scanning image sensing device 21 is parallel to and substantially in agreement with the abovesaid line LX 0  on the specimen 2 placed on the specimen table 1, as viewed from the direction along the axis a of the holder 23 and consequently along the axis d of the tubular member 41. 
     Further, let it be assumed that the holder 23 and the specimen table 1 each lie at such a position relative to the other that is lower than a relative position where the one-dimensional image sensing device 21 performs one-dimensional scanning of the impression 3 of the specimen 2 with its image held in focus (The former relative position will hereinafter be referred to as the in-focus position and the latter relative position as the reference position.). 
     In such a case, the outputs S n&#39;   to S 1  &#39;, S 0  and S 1   to S n&#39;  each of which constitutes the image output S obtained for each scanning, are provided from the one-dimensional scanning image sensing device 21, as shown in FIG. 4C. 
     That is to say, for example, the outputs S n  &#39; to S.sub.(n-1) &#39; and the outputs S.sub.(n-2) to S n  are obtained at substantially the same level and the outputs S.sub.(n-3) &#39; to S 1  &#39;, S 0  and S 1  to S.sub.(n-3) are obtained at levels lower than those of the outputs S n  &#39; to S.sub.(n-2) &#39; and S.sub.(n-2) to S n&#39;  but those outputs S.sub.(n-3) &#39;, S.sub.(n-4) &#39;, . . . among the outputs S.sub.(n-2) &#39; to S 1  &#39; which are in the vicinity of the output S.sub.(n-2) &#39; respectively assume levels which sequentially diminish from the level of the output S.sub.(n-2) &#39; and those S.sub.(n-3) &#39; S.sub.(n-4)&#39; . . . among the output S.sub.(n-2) to S 1  which are in the vicinity of the output S.sub.(n-2) respectively assume levels which sequentially diminish from the level of the output S.sub.(n-2). 
     In this case, the reason for which the outputs S n  &#39; to S.sub.(n-2) &#39; and S.sub.(n-2) to S n  assume substantially the same level is that these outputs S n  &#39; to S.sub.(n-2) &#39; and S.sub.(n-2) to S n  are the outputs of the solid-state image sensors S n  &#39; to E.sub.(n-2) &#39; and E.sub.(n-2) to E n  when they image the area of the specimen 2 on the line LX 0  except the points PX&#39; and PX. 
     The reason for which the levels of the outputs S.sub.(n-2) &#39;, S.sub.(n-3) &#39;, S.sub.(n-4) &#39;, . . . become gradually lower and the levels of the outputs S.sub.(n-2)&#39;  S.sub.(n-3)&#39; S.sub.(n-4)&#39; . . . become gradually lower is that the outputs S.sub.(n-2) &#39;, S.sub.(n-3) &#39;, S.sub.(n-4) &#39;, . . . are the outputs of the solid-state image sensors E.sub.(n-2) &#39;, E.sub.(n-3) &#39;, E.sub.(n-4) &#39;, . . . when they image the inclined area of the impression 3 which extends along the line LX 0  in the vicinity of the point PX&#39;, as viewed from above, and that the outputs S.sub.(n-2)&#39; S.sub.(n-3)&#39; S.sub.(n-4)&#39; . . . are the outputs of the solid-state image sensors E.sub.(n-2)&#39; E.sub.(n-3)&#39; E.sub.(n-4)&#39; . . . when they image the inclined area of the impression 3 which extends along the line LX 0  in the vicinity of the point PX, as viewed from above. 
     Incidentally, the specimen 2 is placed on the specimen table 1 so that line LX 0  is parallel to and substantially in agreement with the line of arrangement c--c of the solid-state image sensors E n  &#39; to E 1  &#39;, E 0  and E 1  to E n&#39;  as described previously, but, assuming that the holder 23 and the specimen table 1 lie at the aforementioned in-focus position relative to each other, the one-dimensional scanning image sensing device 21 generates, for each scanning, the abovesaid outputs S n  &#39; to S 1  &#39;, S 0  and S 1  to S n  in the same manner a referred to above with regard to FIG. 4C. In this case, however, as shown in FIG. 4D, the outputs S n  &#39; to S 1  &#39;, S 0  and S 1  to S n  are obtained at higher levels than in the case where the relative position of the holder 23 and the specimen table 1 is the aforesaid reference position, and the ratio of change at which the outputs S.sub.(n-2) &#39;, S.sub.(n-3) &#39;, S.sub.(n-4) &#39;, . . . progressively diminish and the ratio of change at which the outputs S.sub.(n-2)&#39; S.sub.(n-3)&#39; S.sub.(n-4)&#39;, . . . progressively diminish are both higher than in the case where the relative position of the holder 23 and the specimen table 1 is the abovementioned reference position. 
     The image output S of the one-dimensional scanning image sensing device 21, which is provided therefrom in the sequential order S n  &#39; to S 1  &#39;, S 0&#39;  S 1  to S n  for each scanning, is applied to an arithmetic processing circuit 51. 
     Now, the outputs S n  &#39; to S 1  &#39;, S 0  and S 1  to S n  which are sequentially obtained from the one-dimensional scanning image sensor 21 by u scanning operations starting from a certain time point t 1  are represented by first outputs S 1n  &#39; to S 11  &#39;, S 10  and S 11  to S 1n  ; second outputs S 2n  &#39; to S 21  &#39;, S 20  and S 21  to S 2n  ; . . . and uth outputs S un  &#39; to S u1  &#39;, S u0  and S u1   to S un&#39;  respectively, as shown in FIG. 6A. 
     Then, the arithmetic processing circuit 51 obtains from the ith (where i=1, 2, . . . u) outputs S in  &#39; to S i1  &#39;, S i0  and S i1  to S in  difference outputs ΔS in  &#39;, ΔS i (n-1) &#39;, . . . ΔS i1  &#39;, ΔS i1&#39; , ΔS i2&#39;  . . . ΔS in  which are respectively represented by ##EQU1## and the arithmetic processing circuit 51 decides and stores a maximum one of the difference outputs ΔS in  &#39; to ΔS i1  &#39; and ΔS i1  to ΔS in  (which maximum difference output will hereinafter be identified by ΔS i ) and outputs a positive pulse P i&#39;  as shown in FIG. 6B. 
     In this way, positive pulses P 1&#39;  P 2&#39;  . . . P u  are sequentially provided from the arithmetic processing circuit 51. 
     These positive pulses P 1&#39;  P 2&#39;  . . . P u  are supplied via a motor drive circuit 52 to the aforementioned motor 10. 
     When supplied with the positive pulses P 1&#39;  P 2&#39;  . . . P u  one after another, the motor 10 rotates in the forward direction step by step. 
     Consequently, the specimen table 1 moves up from the reference position step by step. 
     In this, case, the gear ratio between the gears 12 and 13, the gear ratio between the gears 13 and 8 and the pitches of the screw of the threaded shaft 9 and the female screw 7 of the tubular member 6 are selected so that the highest position of the specimen table 1 up to which it is raised step by step is above the aforesaid in-focus position. 
     After generating the positive pulses P 1  to P u&#39;  the arithmetic processing circuit 51 yields u negative pulses P 1  &#39; to P u  &#39; one after another, as shown in FIG. 6B. 
     These negative pulses P 1  &#39; to P u  &#39; are provided via the motor drive circuit 52 to the motor 10. 
     When supplied with the negative pulses P 1  &#39;, P 2  &#39;, . . . P u  &#39; in the sequential order, the motor 10 rotates in the reverse direction step by step. 
     In consequence, the specimen table 1 moves down from the abovesaid raised position step by step correspondingly, and the specimen table 1 thus returns to the reference position. 
     Moreover, the arithmetic processing circuit 51 decides a maximum value of the aforesaid maximum difference outputs ΔS 1  &#39; ΔS 2 , . . . ΔS u  (which maximum value will hereinafter be identified as an rth maximum difference output ΔS r  among the maximum difference outputs) before completion of the sequential generation of the negative pulses P 1  &#39; to P u  &#39;, or after generating the pulse P u  &#39;. 
     Then, after generating the pulse P u  &#39;, the arithmetic processing circuit outputs r positive pulses P 1  &#34; to P r  &#34;. 
     These positive pulses P 1  &#34; to P u&#34;  are provided via the motor drive circuit 52 to the motor 10. 
     Accordingly, the motor 10 rotates again in the forward direction step by step and the specimen table 1 moves up step by step correspondingly and stays at the raised position. 
     Incidentally, the abovementioned maximum difference output S r  among the maximum difference outputs ΔS 1  &#39; ΔS 2&#39;   . . . ΔS u  is obtained from the output S rn  &#39; to S r1  &#39;, S r0  and S r1  to S rn  which are provided from the one-dimensional scanning image sensing device 21 at high levels in the case where the one-dimensional image sensing device 21 scans the specimen 2 in the in-focus state, as will be seen from the description previously given in connection with FIG. 4D. 
     Further, the maximum difference outputs among the maximum difference outputs ΔS 1&#39;  ΔS 2&#39;   . . . ΔS u  except the maximum difference output ΔS r  are obtained from the outputs of the one-dimensional scanning image sensing device 21 which are obtained at low levels in the case where the one-dimensional scanning image sensing device 21 scans the specimen 2 in the out-of-focus state, as will be seen from the description previously given in respect of FIG. 4C. 
     Accordingly, the position up to which the specimen table 1 is brought up step by step on the basis of the pulses P 1  &#34; to P r  &#34; as mentioned above is the aforesaid in-focus position where the one-dimensional scanning image sensing device 21 scans the specimen 2 under the in-focus condition. 
     Therefore, after the specimen table 1 is brought to the in-focus position, the image output S of the one-dimensional scanning image sensing device 21 is obtained at a high level. 
     After the specimen table 1 is brought to the in-focus position as described above, the arithmetic processing circuit 51 produces m negative pulses G1 1   to G1 m . 
     These m negative pulses G1 1  to G1 m  are provided via a motor drive circuit 53 to the motor 35. 
     By sequential application of the pulses G1 1&#39;  G1 2&#39;  . . . G1 m&#39;  the motor 35 rotates in the forward direction step by step. In response to this, the aforementioned movable board 22 moves along the line b--b towards the line LX m  &#39; on the stepwise basis. In this case, the pitches of the screw 37 of the rotary shaft 36 of the motor 35 and the female screw 34 of the rod 33 of the movable board 22 are selected so that the movable board 22 moves a distance equal to the aforesaid spacing e for each step. 
     This provides the relationship that line LX m  &#39; on the specimen 2 is parallel to and substantially in agreement with the line of arrangement c--c of the solid-state image sensors E n  &#39; to E 1  &#39;, E 0  and E 1  to E n . 
     A plurality of sets of the outputs S n  &#39; to S 1  &#39;, S 0  and S 1  to S n  &#39; which are sequentially produced by (2m+1) scanning operations from a time point t 2  after the line LX m  &#39; on the specimen 2 has been brought into substantial agreement with the line of arrangement c--c as described just above, will hereinafter be identified as outputs QXL mn  &#39; to QXL m1  &#39;, QCX m0  &#39; and QXR m1  &#39; to QXR mn  &#39; by first scanning; outputs QXL(m-1)n&#39;  to QXL.sub.(m-1)1 &#39;, QXC.sub.(m-1)0 &#39; and QXR.sub.(m-1)1 &#39; to QXR.sub.(m-1)n &#39; by second scanning; . . . outputs QXL 1n  &#39; to QXL 11  &#39;, QXC 10  &#39; and QXR 11  &#39; to QXR 1n  &#39; by mth scanning; outputs QXL on  to QXL 01 , QXC 00  and QXR 01  to QXR 0n  by (m+1)th scanning; outputs QXL 1n  to QXL 11&#39;  QXC 10  and QXR 11  to QXR 1n  by (m+2)th scanning; outputs QXL 2n  to QXL 21&#39;  QXC 20  and QXR 21  to QXR 2n  by (m+3)th scanning; . . . and outputs QXL mn  to QXL m1&#39;  QXC m0  and QXR m1  to QXL mn  by (2m+1)th scanning, respectively, in the same manner as described previously with respect FIG. 6A, as shown in FIG. 7A. 
     Then the arithmetic processing circuit 51 stores the abovesaid outputs QXL jn  &#39; to QXL j1  &#39;, QXC j0  &#39; and QXR j1  &#39; to QXR jn  &#39; of the j&#39;th (j&#39;=m, (m-1), . . . 1) scanning and obtains difference outputs ΔQXL jn  &#39;, ΔQXL j (n-1)&#39;, . . . ΔQXL j1  &#39;, ΔQXR j1  &#39; WΔQXR j2  &#39;, . . . ΔQXR jn  &#39; which are respectively represented by ##EQU2## Then the arithmetic processing circuit 51 arrays and stores the abovesaid difference outputs ΔQXL j1  &#39; to ΔQXL jn  &#39; in this order. 
     Then the arithmetic processing circuit 51 detects the position on the array of the difference outputs where a difference output of a zero value appears for the first time after a plurality of difference outputs of positive values appear one after another (which output will hereinafter be identified as ΔQXL j  &#39;), as viewed from the side of the difference output ΔQXL j1  &#39; to the side of the difference output QXL jn  &#39;. 
     Thereafter the arithmetic processing circuit 51 stores an output which represents the array length from the position of the difference output ΔQXL j  &#39; to the position of the difference output ΔQXL j1  &#39; (which output will hereinfter be identified as WXL j  &#39;). 
     Furthermore, the arithmetic processing circuit 51 similarly detects the position on the array of the difference outputs where a difference output of a zero value appears for the first time after a plurality of difference outputs of positive values appear one after another (which output will hereinafter be identified as ΔQXR j  &#39;), as viewed from the side of the difference output ΔQXR j1  &#39; to the side of the difference output ΔQXR jn  &#39;. 
     Then the arithmetic processing circuit 51 stores an output which represents the array length from the position of the difference output ΔQXR j  &#39; to the position of the difference output ΔQXR j1  &#39; (which output will hereinafter be identified as WXR j  &#39;). 
     Then the arithmetic processing circuit 51 obtains, from the outputs WXL j  &#39; and QXR j  &#39; representing the abovesaid array lengths, an output MX j  &#39; represented by 
     
         MX.sub.j &#39;=WXL.sub.j &#39;+WXR.sub.j &#39; 
    
     and stores it. Then the arithmetic processing circuit 51 outputs a pulse HX j  &#39;, as shown in FIG. 7B. 
     Furthermore the arithmetic processing circuit 51 stores the abovesaid outputs QXL 0n  to QXL 01 , QXC 00  and QXR 01  to QXR 0n  of the (m+1)th scanning and obtains difference outputs ΔQXL 0n , ΔQXL 0 (n-1), . . . ΔQXL 01 , ΔQXR 01 , ΔQXR 02 , . . . ΔQXR 0n  which are respectively represented by ##EQU3## 
     Then the arithmetic processing circuit 51 arrays and stores the abovesaid difference outputs ΔQXL 01  to ΔQXL 0n  in this order. 
     Then the arithmetic processing circuit detects the position on the array of the difference outputs where a difference output of a zero value appears for the first time after a plurality of difference outputs of positive values appear one after another (which output will hereinafter be identified as ΔQXL 0 ), as viewed from the side of the difference output ΔQXL 01  to the side of the difference output QXL 0n . 
     Thereafter the arithmetic processing circuit 51 stores an output which represents the array length from the position of the difference output ΔQXL 0  to the position of the difference output ΔQXL 01  (which output will hereinfter be identified as WXL 0 ). 
     Furthermore, the arithmetic processing circuit 51 similarly detects the position on the array of the difference outputs where a difference output of a zero value appears for the first time after a plurality of difference outputs of positive values appear one after another (which output will hereinafter be identified as ΔQXR 0 ), as viewed from the side of the difference output ΔQXR 01  to the side of the difference output ΔQXR 0n . 
     Then the arithmetic processing circuit 51 stores an output which represents the array length from the position of the difference output ΔQXR 0  to the position of the difference output ΔQXR 01  (which output will hereinafter be identified as WXR 0 ). 
     Then the arithmetic processing circuit obtains, from the outputs WXL 0  and QXR 0  representing the above-said array lengths, an output MX 0  represented by 
     
         MX.sub.0 =WXL.sub.0 +WXR.sub.0 
    
     and stores it. Then the arithmetic processing circuit 51 outputs a pulse HX 0 , as shown in FIG. 7B. 
     Furthermore the arithmetic processing circuit 51 stores the abovesaid outputs QXL jn  to QXL j1 , QXC j0  and QXR j1  to QXR jn  of the jth (j=1, 2 . . . m) scanning and obtains difference outputs ΔQXL jn , ΔQXL j (n-1), . . . ΔQXL j1 , ΔQXR j1 , ΔQXR j2 , . . . ΔQXR jn  which are respectively represented by ##EQU4## 
     Then the arithmetic processing circuit 51 arrays and stores the abovesaid difference outputs ΔQXL j1  to ΔQXL jn  in this order. 
     Then the arithmetic processing circuit detects the position on the array of the difference outputs where a difference output of a zero value appears for the first time after a plurality of difference outputs of positive values appear one after another (which output will hereinafter be identified as ΔQXL j ), as viewed from the side of the difference output ΔQXL j1  to the side of the difference output QXL jn . 
     Thereafter the arithmetic processing circuit 51 stores an output which represents the array length from the position of the difference output ΔQXL j  to the position of the difference output ΔQXL j1  (which output will hereinfter be identified as WXL j ). 
     Furthermore, the arithmetic processing circuit 51 similarly detects the position on the array of the difference outputs where a difference output of a zero value appears for the first time after a plurality of difference outputs of positive values appear one after another (which output will hereinafter be identified as ΔQXR j ), as viewed from the side of the difference output ΔQXR j1  to the side of the difference output ΔQXR jn . 
     Then the arithmetic processing circuit 51 stores an output which represents the array length from the position of the difference output ΔQXR j  to the position of the difference output ΔQXR j1  (which output will hereinafter be identified as WXR j ). 
     Then the arithmetic processing circuit 51 obtains, from the outputs WXL j  and QXR j  representing the abovesaid array lengths, an output MX j  represented by 
     
         MX.sub.j =WXL.sub.j +WXR.sub.j 
    
     and stores it. Then the arithmetic processing circuit 51 outputs a positive pulse HX j , as shown in FIG. 7B. 
     In the manner described above, the arithmetic processing circuit 51 provides positive pulses HXm&#39;, HX.sub.(m-1) &#39;, . . . HX 1  &#39;, HX 0 , HX 1 , HX 2 , . . . HX m  one after another. 
     These pulses HX m  &#39;, HX.sub.(m-1) &#39;, . . . HX 1  &#39;, HX 0  &#39;, HX 1 , HX 2 , . . . HX m  are applied via the motor drive circuit 53 to motor 35. 
     Supplied with the pulses HX m  &#39;, HX.sub.(m-1) &#39;, . . . HX 1  &#39;, HX 0 , HX 1 , HX 2 , . . . HX m  one after another, the motor 35 rotates in the forward direction step by step. Consequently, the movable board 22 moves along the aforementioned line b--b step by step, the distance of movement for each step being equal to the aforesaid interval. 
     By such step-by-step movement of the movable board 22, the aforesaid line c--c held so far at the position relative to the holder 23 where the line is substantially in agreement with the line LX m  &#39;0 is brought into substantial agreement with the lines LX.sub.(m-1) &#39;, LX.sub.(m-2) &#39;, . . . LX 1  &#39;, LX 0  &#39;, LX 1 , . . . LX m  one after another. 
     Accordingly, the output MXL j  &#39; of the output MX j  represents the length from the central position O of the impression 3 of the specimen 2 to the marginal edge thereof on the side of the point PX&#39; on the aforementioned line LX j  &#39;. 
     The reason is as follows: The output WXL j  &#39; is representative of the array length from the position of the aforesaid difference output ΔQXL j  &#39; to the position of the difference output ΔQXL j1  &#39;. On the other hand, the difference output ΔQXL j  &#39; is the difference output of a zero value that appears for the first time on the array after a plurality of difference outputs of positive values appear one after another, as viewed from the side of the difference output ΔQXL j1  &#39; to the side of the difference output ΔQXL jn  &#39;. Accordingly, the position of the difference output ΔQXL j  &#39; on the array corresponds to the marginal edge of the impression 3 on the line LX j  &#39; on the side of the point PX&#39;, as will be evident from the description given previously of the general outputs S n  &#39;, S.sub.(n-1) &#39;, . . . S 1  &#39;, S 0 , S 1 , S 2 , . . . S.sub.(n-1), S n  with reference to FIGS. 4C and D. 
     For the same reason as mentioned above, the output WXR j  &#39; of the output MX j  &#39; represents the length of the impression 3 of the specimen 2 on the line LX j  &#39; from the central position O of the impression 3 to its marginal edge on the side of the point PX on the line LX j  &#39;. 
     Accordingly, the output MX j  &#39; represents the length of the impression 3 on the line LX j  &#39;. 
     Furthermore, for the same reason as given above, the outputs MX 0  and MX j  represents the lengths of the impression 3 on the lines LX 0  and LX j , respectively. 
     Moreover, after generating the pulses HX m  &#39;, HX.sub.(m-1) &#39;. . . HX 1  &#39;, HX 0 , HX 1 , HX 2 , . . . HX m , the arithmetic processing circuit 51 yields one switching pulse PXW, as shown in FIG. 7C. 
     This switching pulse PXW is provided to a motor drive circuit 54. 
     On the other hand, the motor drive circuit 54 has connected thereto the switches 39 and 39&#39; for engagement with the engaging pin 38 of the holder 23. 
     Since the holder 23 stays at the first rotational position, the switch 39 is operative when the switching pulse PXW is obtained. 
     When supplied with the switching pulse PXW during the operation of the switch 39, the motor drive circuit 54 generates sequential pulses KX, as shown in FIG. 7D. 
     Supplied with the sequential pulses KX, the motor 30 rotates in the forward direction step by step. In consequence, the holder 23 turns in the forward direction. 
     Then, when the holder 23 turns until the engaging pin is brought into engagement with the switch 39&#39;, the switch 39&#39; is activated. 
     As a result of this, the pulses KX are no more generated from the motor drive circuit 54 and the motor 30 stops, and consequently the holder 23 also stops. 
     When the holder 23 is thus stopped, it assumes such a rotational position relative to the specimen 2 that the line of arrangement c--c of the solid-state image sensors E n  &#39; to E 1  &#39;, E 0  and E 1  to E n  of the one-dimensional scanning image sensing device 21 substantially agrees with the aforementioned line LY&#39; 0  on the specimen 2 (which rotational position will hereinafter be referred to as the second rotational position). 
     A plurality of sets of the outputs S n  &#39; to S 1  &#39;, S 0  and S 1  to S n  &#39; which are sequentially produced by (2m+1) scanning operations from a time point t 3  after the holder 23 has been brought to the second rotational position where the line of arrangement c--c substantially agrees with the line LY m  &#39; on the specimen 2 as described just above, will hereinafter be identified as outputs QYL mn  &#39; to QYL m1  &#39;, QYC m0  &#39; and QYR m1  &#39; to QYR mn  &#39; by first scanning; outputs QYL.sub.(m-1)n &#39; to QYL.sub.(m-1)1 &#39;, QYC.sub.(m-1)0&#39; and QYR.sub.(m-1)1 &#39; to QYR.sub.(m-1)n &#39; by second scanning; . . . outputs QYL 1n  &#39; to QYL 11  &#39;, QYC 10  &#39; and QYR 11  &#39; to QYR 1n  &#39; by mth scanning; outputs QYL 0n  to QYL 01 , QYC 00  and QYR 01  to QYR 0n  by (m+1)th scanning; outputs QYL 1n  to QYL 11  &#39; QYC 10  and QYR 11  to QYR 1n  by (m+2)th scanning; outputs QYL 2n  to QYL 21  &#39; QYC 20  and QYR 21  to QYR 2n  by (m+3)th scanning; . . . and outputs QYL mn  to QYL m1  &#39; QYC m0  and QYR m1  to QYL mn  by (2m+1)th scanning, respectively, in the same manner as described previously with respect FIG. 7A, as shown in FIG. 8A. 
     Then the arithmetic processing circuit 51 stores the abovesaid outputs QYL jn  &#39; to QYL j1  &#39;, QYC j0  &#39; and QYR j1  &#39; to QYR jn  &#39; of the j&#39;th (j&#39;=m, (m-1), . . . 1) scanning and obtains difference outputs ΔQYL jn  &#39;, ΔQYL j (n-1) &#39;, . . . ΔQYL j1  &#39;, ΔQYR j1  &#39;, ΔQYR j2  &#39;, . . . ΔQYR jn  &#39; which are respectively represented by ##EQU5## 
     Then the arithmetic processing circuit 51 arrays and stores the abovesaid difference outputs ΔQYL j1  &#39; to ΔQYL jn  &#39; in this order. 
     Then the arithmetic processing circuit 51 detects the position on the array of the difference outputs where a difference output of a zero value appears for the first time after a plurality of difference outputs of positive values appear one after another (which output will hereinafter be identified as ΔQYL j  &#39;), as viewed from the side of the difference output ΔQYL j1  &#39; to the side of the difference output QYL jn  &#39;. 
     Thereafter the arithmetic processing circuit 51 stores an output which represents the array length from the position of the difference output ΔQYL j  &#39; to the position of the difference output ΔQYL j1  &#39; (which output will hereinafter be identified as WYL j  &#39;). 
     Furthermore. the arithmetic processing circuit 51 similarly detects the position on the array of the difference outputs where a difference output of a zero value appears for the first time after a plurality of difference outputs of positive values appear one after another (which output will hereinafter be identified as ΔQYR j  &#39;), as viewed from the side of the difference output ΔQYR j1  &#39; to the side of the difference output ΔQYR jn  &#39;. 
     Then the arithmetic processing circuit 51 stores an output which represents the array length from the position of the difference output ΔQYR j  &#39; to the position of the difference output ΔQYR j1  &#39; (which output will hereinafter be identified as WYR j  &#39;). 
     Then the arithmetic processing circuit 51 obtains, from the outputs WYL j  &#39; and QYR j  &#39; representing the abovesaid array lengths, an output MY j  &#39; represented by 
     
         MY.sub.j &#39;=WYL.sub.j &#39;+WYR.sub.j &#39; 
    
     and stores it. Then the arithmetic processing circuit outputs a pulse HY j  &#39;, as shown in FIG. 8B. 
     Furthermore the arithmetic processing circuit 51 stores the abovesaid outputs QYL 0n  to QYL 01 , QYC 00  and QYR 01  to QYR 0n  of the (m+1)th scanning and obtains difference outputs ΔQYL 0n , ΔQYL 0 (n-1), . . . ΔQYL 01 , ΔQYR 01 , ΔQYR 02 , . . . ΔQYR 0n  which are respectively represented by ##EQU6## 
     Then the arithmetic processing circuit 51 arrays and storeds the abovesaid difference outputs ΔQYL 01  to ΔQYL 0n  in this order. 
     Then the arithmetic processing circuit 51 detects the position on the array of the difference outputs where a difference output of a zero value appears for the first time after a plurality of difference outputs of positive values appear one after another (which output will hereinafter be identified as ΔQYL 0 ), as viewed from the side of the difference output QYL 01  to the side of the difference output ΔQYL 0n . 
     Thereafer the arithmetic processing circuit 51 stores an output which represents the array length from the position of the difference output ΔQYL 0  to the position of the difference output ΔQYL 01  (which output will hereinafter be identified as WYL 0 ). 
     Furthermore, the arithmetic processing circuit 51 similarly detects the position on the array of the difference outputs where a difference output of a zero value appears for the first time after a plurality of difference outputs of positive values appear one after another (which output will hereinafter be indentified as ΔQYR 0 ), as viewed from the side of the difference output ΔQYR 01  to the side of the difference output ΔQYR 0n . 
     Then the arithmetic processing circuit 51 stores an output which represents the array length from the position of the difference output ΔQYR 0  to the position of the difference output ΔQYR 01  (which output will hereinafter be identified as WYR 0 ). 
     Then the arithmetic processing circuit 51 obtains, from the output WYL 0  and QYR 0  representing the abovesaid aray lengths, an output MY 0  represented by 
     
         MY.sub.0 +WYL.sub.0 =WYR.sub.0 
    
     and stores it. Then the arithmetic processing circuit outputs a pulse HY 0 , as shown in FIG. 8B. 
     Futhermore, the arithmetic processing circuit 51 stores the abovesaid outputs QYL jn  to QYL j1 , QYC j0  and QYR j1  to QYR jn  of the jth (j=1, 2 . . . m) scanning and obtains difference outputs ΔQYL jn , ΔQYL j (n-1), . . . ΔQYL j1 , ΔQYR j1 , ΔQYR j2 , . . . ΔQYR jn  which are respectively represented by ##EQU7## 
     Then the arithmetic processing circuit 51 arrays and stores the abovesaid difference outputs ΔQYL j1  to ΔQYL jn  in this order. 
     Then the arithmetic processing circuit detects the position on the array of the difference outputs where a difference output of a zero value appears for the first time after a plurality of difference outputs of positive values appear one after another (which output will hereinafter be identified as ΔQYL j ), as viewed from the side of the difference output ΔQYL j1  to the side of the difference output QYL jn . 
     Thereafter the arithmetic processing circuit 51 stores an output which represents the array length from the position of the difference output ΔQYL j  to the position of the difference output ΔQYL j1  (which output will hereinfter be identified as WYL j ). 
     Furthermore, the arithmetic processing circuit 51 similarly detects the position on the array of the difference outputs where a difference output of a zero value appears for the first time after a plurality of difference outputs of positive values appear one after another (which output will hereinafter be identified as ΔQYR j ), as viewed from the side of the difference output ΔQYR j1  to the side of the difference output ΔQYR jn . 
     Then the arithmetic processing circuit 51 stores an output which represents the array length from the position of the difference output ΔQYR j  to the position of the difference output ΔQYR j1  (which output will hereinafter be identified as WYR j ). 
     Then the arithmetic processing circuit 51 obtains, from the outputs WYL j  and QYR j  representing the abovesaid array lengths, an output MY j  represented by 
     
         MY.sub.j =WYL.sub.j +WYR.sub.j 
    
     and stores it. Then the arithmetic processing circuit outputs a positive pulse HY j , as shown in FIG. 8B. 
     In the manner described above, the arithmetic processing circuit 51 provides positive pulses HY m  &#39;, HY.sub.(m-1) &#39;, . . . HY 1  &#39;, HY 0 , HY 1 , HY 2 , . . . HY m  one after another. 
     These pulses HY m  &#39;, HY.sub.(m-1) &#39;, . . . HY 1  &#39;, HY 0  &#39;, HY 1 , HY 2 , . . . HY m  are applied via the motor drive circuit 53 to motor 35. 
     Supplied with the pulses HY m  &#39;, HY.sub.(m-1) &#39;, . . . HY 1  &#39;, HY 0 , HY 1 , HY 2 , . . . HY m  one after another, the motor 35 rotates in the forward direction step by step. Consequently, the movable board 22 moves along the aforementioned line b--b step by step, the distance of movement for each step being equal to the aforesaid interval. 
     By such step-by-step movement of the movable board 22, the aforesaid line c--c held so far at the position relative to the holder 23 where the line is substantially in agreement with the line LY m  &#39; is brought into substantial agreement with the lines LY.sub.(m-1) &#39;, LY.sub.(m-2) &#39;, . . . LY 1  &#39;, LY 0  &#39;, LY 1 , . . . LY m  one after another. 
     Accordingly, the output MYL j  &#39; of the output MY j  &#39; represents the length from the central position O of the impression 3 of the specimen 2 to the marginal edge thereof on the side of the point PY&#39; on the aforementioned line LY j  &#39;. 
     The reason is as follows: The output WYL j  &#39; is representative of the array length from the position of the aforesaid difference output ΔQXL j  &#39; to the position of the difference output ΔQXL j1  &#39;. On the other hand, the difference output ΔQXL j  &#39; is the difference output of a zero value that appears for the first time on the array of the difference outputs ΔQXL j1  &#39; to ΔQXL jn  &#39; after a plurality of difference outputs of positive values appear one after another, as viewed from the side of the difference output ΔQXL j1  &#39; to the side of the difference output ΔQXL jn  &#39;. Accordingly, the position of the difference output ΔQXL j  &#39; on the array corresponds to the marginal edge of the impression 3 on the line LY j  &#39; on the side of the point PY&#39;, as will be evident from the description given previously of the general outputs S n  &#39;, S.sub.(n-1) &#39;, . . . S 1  &#39;, S 0 , S 1 , S 2 , . . . S.sub.(n-1), S n  with reference to FIGS. 4C and D. 
     For the same reason as mentioned above, the output WYR j  &#39; of the output MY j  &#39; represents the length of the impression 3 of the specimen 2 on the line LY j  &#39; from the central position O of the impression 3 to its marginal edge on the side of the point PY on the line LY j  &#39;. 
     Accordingly, the output MY j  &#39; represents the length of the impression 3 on the line LY j  &#39;. 
     Furthermore, for the same reason as given above, the outputs MY 0  and MY j  represents the lengths of the impression 3 on the lines LY 0  and LY j , respectively. 
     Moreover, after generating the pulses HY m  &#39;, HY.sub.(m-1) &#39;. . . HY 1  &#39;, HY 0 , HY 1 , HY 2 , . . . HY m , the arithmetic processing circuit 51 yields one switching pulse PYW, as shown in FIG. 8C. 
     This switching pulse PYW is provided to a motor drive circuit 54. 
     On the other hand, the motor drive circuit 54 has connected thereto the switches 39 and 39&#39; for engagement with the engaging pin 38 of the holder 23. 
     Since the holder 23 stays at the second rotational position, the switch 39 is operative when the switching pulse PYW is obtained. 
     When supplied with the switching pulse PYW during the operation of the switch 39&#39;, the motor drive circuit 54 generates sequential pulses KY, as shown in FIG. 8D. 
     The sequential pulses KY are provided to the motor 30. 
     Supplied with the sequential pulses KY, the motor 30 rotates in the reverse direction step by step. In consequence, the holder 23 turns in the reverse direction. 
     Then, when the holder 23 turns until the engaging pin is brought into engagement with the switch 39, the switch 39 is activated. 
     As a result of this, the pulses KY are no more generated from the motor drive circuit 54 and the motor 30 stops, and consequently the holder 23 also stops. 
     When the holder 23 is thus stopped, it assumes the first rotational position relative to the specimen 2 that the line of arrangement c--c of the solid-state image sensors E n  &#39; to E 1  &#39;, E 0  and E 1  to E n  of the one-dimensional scanning image sensing device 21 substantially agrees with the aforementioned line LX m  &#39; on the specimen 2. 
     As described previously, the arithmetic processing circuit 51 stores the outputs MY m  &#39; to MY 1  &#39;, My 0  and MY 1  to MY m  as well as the aforementioned outputs MX m  &#39; to MX.sub.(m-n) &#39;, MX 0  and MX 1  to MX m . 
     The arithmetic processing circuit 51 detects a maximum one (which will hereinafter be identified as MX) among the outputs MX m  &#39; to MX 1  &#39;, MX 0  and MX 1  to MX m  and yields the output MX. The output MX is the output MX 0  when the outputs MX m  &#39; to MX 1  &#39;, MX 0  and MX 1  to MX m  are obtained as described above. 
     Likewise, the arithmetic processing circuit 51 detects a maximum one (which will hereinafter be identified as MY) of the outputs MY m  &#39; to MY 1  &#39;, MY 0  and MY 1  to MY m  and yields the output MY. The output MY is the output MY 0  when the outputs MY m  &#39; to MY 1  &#39;, MY 0  and MY 1  to MY m  are obtained as described above. 
     The output MX represents the length NX of the first diagonal joining the points PX and PX&#39; of the impression 3 of the specimen 2, as will be seen from the foregoing description. 
     Similarly, the output MY represents the length NY of the first diagonal joining the points PY and PY&#39; of the impression 3 of the specimen 2, as will be evident from the foregoing description. 
     As described above, according to the first embodiment of the indentation hardness meter of the present invention, the lengths NX and NY of the first and second diagonals of the impression 3 made in the specimen 2 can be measured. 
     Accordingly, the hardness of the specimen 2 can be measured from the lengths NX and NY. 
     In this case, according to the indentation hardness meter of the present invention described in the foregoing, the impression 3 made in the specimen 2 is imaged by one-dimensional scanning through the use of the one-dimensional image sensing device 21 and the outputs representing the lengths of the first and second diagonals of the impression 3 are obtained from the image output. 
     Accordingly, the indentation hardness meter of the present invention has such a great feature that the image sensing device for obtaining the first and second diagonal-length signals may be a simple, small and inexpensive one-dimensional scanning image sensing device. 
     Moreover, according to the indentation hardness meter of the present invention, the first and second diagonal-length signals can be obtained at high speed without scanning the entire area of the impression by the one-dimensional scanning image sensing device. 
     In addition, the indentation hardness meter of the present invention has such a great advantage that the entire arrangement is simple. 
     Next, a description will be given of a second embodiment of the indentation hardness meter of the present invention. 
     FIGS. 9 and 10 illustrate an example of the mechanical system of the second embodiment of the indentation hardness meter of the present invention. 
     In FIGS. 9 and 10, the parts corresponding to those in FIGS. 1 and 2 are identified by the same reference numerals and no detailed description will be repeated. 
     The mechanical system of the indentation hardness meter of the present invention shown in FIGS. 9 and 10 is identical in construction with the mechanical system of the first embodiment of the indentation hardness meter of the present invention illustrated in FIGS. 1 and 2, except in the following points: 
     That is to say, the motor 30 mounted on the support 40, the gear 32 provided on the rotary shaft 31 and the gear 28 provided on the tubular member 24 of the holder 23 are omitted. Further, the engaging pin 38 planted on the annular portion 25 of the holder 23 and the switches 39 and 39&#39; for engagement with the engaging pin 38 are omitted. 
     Moreover, the holder 23 of the image sensing device mount 20 is fixedly disposed around the tubular member 41 by suitable fixing means (not shown), instead of being rotatably disposed around the tubular member 41. 
     The above is an example of the mechanical system of the second embodiment of the indentation hardness meter of the present invention. 
     Turning next to FIG. 12, an example of the electrical system of the indentation hardness meter of the present invention which employs the mechanical system described above with regard to FIGS. 9 and 10 will be described, together with its operation. 
     In FIG. 12, the parts corresponding to those in FIG. 5 are identified by the same reference numerals and no detailed description will be repeated. 
     The electrical system illustrated in FIG. 12 is identical in construction with the system shown in FIG. 5 except the omission of the motor 30 and the motor drive circuit 54 which has connected thereto the switches 39 and 39&#39; in the electrical system of FIG. 5. 
     By applying the light from the light source 44 via the lens 45, the half-mirror 46 and the lens 47 to the specimen 2 and by applying the reflected light therefrom to the one-dimensional scanning image sensing device 21 via the lens 47 and the half-mirror 46, the image output S obtained by one-dimensional scanning of the specimen is provided from the one-dimensional scanning image sensing device 21 in the same manner as described previously with respect to FIG. 5. 
     In this case, as shown in FIG. 12, the onedimensional scanning image sensing device 21 is driven under the control of the clock pulses CP from the clock pulse generator 50, such as depicted in FIG. 4B. 
     Incidentally, the one-dimensional scanning image sensing device 21 has such as arrangement that the many solid-state image sensors E n  &#39;, E.sub.(n-1) &#39;, . . . E 1  &#39;, E 0&#39;  E 1&#39;  E 2&#39;  . . . E n  are electrically connected in series one after another and one-dimensionally aligned in a line on the aforesaid line c--c, as shown in FIG. 10 and in the same manner as referred to previously. 
     Accordingly, the image output S is obtained as photoelectric conversion outputs S n  &#39;, S.sub.(n-1) &#39;, . . . S 1  &#39;, S 0&#39;  S 1&#39;  S 2&#39;  . . . S n  which are sequentially provided, by the respective scanning of the one-dimensional scanning image sensing device 21, from the solid-state image sensors E n  &#39;, E.sub.(n-1) &#39;, . . . E 1  &#39;, E 0&#39;  E 1&#39;  E 2&#39;  . . . E n&#39;  respectively, in the same manner as described previously in connection with FIGS. 4C and D. 
     Now, let a line, which extends in the plane containing the surface of the specimen 2 and contains the first diagonal joining a pair of opposing points PX and PX&#39; of the quadrangular pyramidal impression 3 made in the specimen 2 on the specimen table 1 as shown in FIG. 3, be represented by LX 0  as shown in FIG. 11 and in the same manner as described with respect to FIG. 4A, and let a line, which contains the second diagonal joining the other pair of opposing points PY and PY&#39;, be represented by LY 0 . Further, let an intersecting point of the lines LX 0  and LY 0  be represented by O. 
     Let a plurality m of lines, which extend in the plane containing the surface of the specimen 2 and in parallel to the line LX 0  and which are sequentially arranged at equal intervals e in a direction perpendicular to the line LX 0  on the side of the point PY with respect thereto over a range which is equal to one half of the width f smaller than the length NY of the abovesaid second diagonal, that is, equal to f/2, be represented by LX 1 , LX 2&#39;  . . . LX m&#39;  respectively, as shown in FIG. 11 and in the same manner as described previously in respect of 4A. Let a plurality m of lines, which are sequentially arranged in parallel to the line LX 0  and at equal intervals e in the direction perpendicular to the line LX 0  on the side of the point PY&#39; with respect thereto over the range equal to the abovesaid width f/2, be represented by LX 1  &#39;, LX 2  &#39;, . . . LX m  &#39;, respectively, in the same manner as described previously with respect to FIG. 4A. 
     Let a line, which passes through the point PY of the impression 3 of the specimen 2 on the specimen table 1 perpendicularly to the line LY 0  in the plane containing the surface of the specimen 2, be represented by LXU 0 , and let a line, which passes through the point PY&#39; perpendicularly to the line LY 0 , be represented by LXD 0 . 
     Let a plurality p of lines, which extend in parallel to the line LXU 0  and which are sequentially arranged side by side at the aforesaid equal intervals e on the side of the point PY&#39; with respect to the line LXU 0  over a range of a width h1 smaller than the length of the second diagonal, be represented by LXU 1  &#39;, LXU 2  &#39;, . . . LXU p  &#39;, respectively, as shown in FIG. 4A. Further, let a plurality q of line, which extend in parallel to the line LXU 0  and which are sequentially arranged side by side at the aforesaid equal intervals e on the opposite side from the point PY&#39; with respect to the line LXU 0  over a range of a width h2 equal to or smaller than the abovesaid width h1, be represented by LXU 1 , LXU 2 , . . . LXU q , respectively, as shown in FIG. 4A. 
     Let a plurality p of lines, which extend in parallel to the line LXD 0  and which are sequentially arranged side by side at the aforesaid equal intervals e on the side of the point PY with respect to the line LXD 0  over the range of the abovesaid width h1, be represented by LXD 1 , LXD 2  &#39;, . . . LXD p  &#39;, respectively, as shown in FIG. 4A. Further, let a plurality q of lines, which extend in parallel to the line LXD 0  and which are sequentially arranged side by side at the aforesaid equal intervals e on the opposite side from the point PY with respect to the line LXD 0  over the range of the abovesaid width h2, be represented by LXD 1  &#39;, LXD 2  &#39;, . . . LXD q , respectively, as shown in FIG. 4A. 
     Now let it be assumed that the specimen 2 is preadjusted in position on the specimen table 1 so that the abovementioned line LX 0  on the specimen 2 placed on the specimen table 1 is parallel to and substantially in agreement with the line of arrangement c--c of the solid-state image sensors E n  &#39; to E 1  &#39;, E 0  and E 1  to E n  of the one-dimensional scanning image sensing device 21, as viewed from the direction along the axis a of the holder 23 and consequently from the direction along the axis d of the tubular member 41, in the same manner as described previously with respect to the electrical system of the first embodiment of the present invention. 
     Further, let it be assumed that the specimen table 1 lies at its lowered reference position, as described previously in connection with the electrical system of the first embodiment of the present invention. 
     In such a case, the one-dimensional scanning image sensing device 21 provides the outputs S n  &#39; to S 1  &#39;, S 0  and S 1  to S n  in the same manner as described previously with regard to FIG. 4C. The image output S, which is obtained from the one-dimensional scanning image sensing device 21 in the sequential order S n  &#39; to S 1  &#39;, S 0  and S 1  to S n  for each scanning, is provided to the arithmetic processing circuit 51 as in the case of the first embodiment of the presenet invention. 
     Now, the outputs S n  &#39; to S 1  &#39;, S 0  and S 1  to S n  which are seqentially obtained from the one-dimensional scanning image sensing device 21 by u scanning operations starting from a certain time point t 1  will hereinafter be represented by first outputs S 1n  &#39; to S 11  &#39;, S 10  and S 11  to S 1n&#39;  ; second outputs S 2n  &#39; to S 21  &#39;, S 20  and S 21  to S 2n&#39;  ; . . . . and uth outputs S un  &#39; to S u1  &#39;, S u0  and S u1  to S un&#39;  respectively, as described previously in connection with FIG. 6A. 
     Then, the arithmetic processing circuit 51 obtains from the ith (where i=1, 2, . . . u) outputs S in  &#39; to S i1  &#39;, S i0  and S i1  to S in  difference outputs ΔS in  &#39;, ΔS i (n-1) &#39;, . . . ΔS i1  &#39;, ΔS i1 , ΔS i2&#39;  . . . ΔS in  which are the same as in the case of the first embodiment of the present invention, and the arithmetic processing circuit 51 decides and stores a maximum one of the difference outputs ΔS in&#39;  to ΔS i1  &#39; and ΔS i1   to ΔS in  (which maximum difference output will hereinafter be identified by ΔS i ) and outputs a positive pulse P i&#39;  in the same manner as described in respect of FIG. 6B. 
     In this way, positive pulses P 1&#39;  P 2&#39;  . . . P u  are sequentially provided from the arithmetic processing circuit 51, as is the case with the first embodiment of the present invention. 
     These positive pulses P 1&#39;  P 2&#39;  . . . P u  are supplied via a motor drive circuit 52 to the aforementioned motor 10, as is the case with the first embodiment of the present invention. Consequently, when supplied with the positive pulses P 1&#39;  P 2&#39;  . . . P u  one after another, the motor 10 rotates in the forward direction step by step, causing the specimen table 1 to move up from the aforementioned reference position step by step. 
     As in the case of the first embodiment of the present invention, after generating the positive pulses P 1  to P u&#39;  the arithmetic processing circuit 51 yields u negative pulses P 1  &#39; to P u  &#39; one after another, as described previously with regard to FIG. 6B. 
     These negative pulses P 1  &#39; to P u  &#39; are provided via the motor drive circuit 52 to the motor 10, as in the case of the first embodiment of the present invention. When supplied with the negative pulses P 1  &#39;, P 2  &#39;, . . . P u  &#39; in the sequential order, the motor 10 rotates in the reverse direction step by step. In consequence, the specimen table 1 moves down from the abovesaid raised position step by step correspondingly, and the specimen table 1 thus returns to the reference position. 
     Moreover, as in the case of the first embodiment of the present invention, the arithmetic processing circuit 51 decides a maximum one ΔS r  of the aforesaid maximum difference outputs ΔS 1 , ΔS 2 , . . . ΔS u  before completion of the sequential generation of the negative pulses P 1  &#39; to P u  &#39;, or after generating the pulse P u  &#39;. Then, after generating the pulse P u  &#39;, the arithmetic processing circuit outputs r positive pulses P 1  &#34; to P r  &#34;. 
     These positive pulses P 1  &#34; to P u  &#34; are provided via the motor drive circuit 52 to the motor 10, as in the case of the first embodiment of the present invention. 
     Accordingly, the motor 10 rotates again in the forward direction step by step and the specimen table 1 moves up step by step correspondingly and stays at the raised position. 
     The position up to which the specimen table 1 is thus brought up step by step is the aforesaid in-focus position where the one-dimensional scanning image sensing device 21 scans the specimen 2 under the in-focus condition, as described previously in respect of the first embodiment of the present invention. 
     Therefore, after the specimen table 1 is brought to the in-focus position, the image output S of the one-dimensional scanning image sensing device 21 is obtained at a high level. 
     After the specimen table 1 is brought to the infocus position as described above, the arithmetic processing circuit 51 produces m negative pulses G1 1  to G1 m , as in the case of the first embodiment of the present invention. These m negative pulses G1 1  to G1 m  are provided via a motor drive circuit 53 to the motor 35. Therefore, by sequential application of the pulses G1 1&#39;  G1 2&#39;  . . . G1 m&#39;  the motor 35 rotates in the forward direction step by step. In response to this, the aforementioned movable board 22 moves along the line b--b towards the line LX m  &#39; on the stepwise basis. 
     As a result of this, the line LX m  &#39; on the specimen 2 is parallel to and substantially in agreement with the line of arrangement c--c of the solidstate image sensors E n  &#39; to E 1  &#39;, E 0  and E 1  to E n , as in the case of the first embodiment of the present invention. 
     A plurality of sets of the outputs S n  &#39; to S 1  &#39;, S 0  and S 1  to S n&#39;  which are sequentially produced by (2m+1) scanning operations from a time point t 2  after the line LX m  &#39; on the specimen 2 has been brought into substantial agreement with the line of arrangement c--c as described just above, will hereinafter be identified as outputs QXL mn  &#39; to QXL m1  &#39;, QXC m0  &#39; and QXR m1  &#39; to QXR mn  &#39; by first scanning; outputs QXL.sub.(m-1)n &#39; to QXL.sub.(m-1)1 &#39;, QXC.sub.(m-1)0 &#39; and QXR.sub.(m-1)1 &#39; to QXR.sub.(m-1)n &#39; by second scanning; . . . outputs QXL 1n  &#39; to QXL 11  &#39;, QXC 10  &#39; and QXR 11  &#39; to QXR 1n  &#39; by mth scanning; outputs QXL 0n  to QXL 01 , QXC 00  and QXR 01  to QXR 0n  by (m+1)th scanning; outputs QXL 1n  to QXL.sub. 11&#39; QXC 10  and QXR 11  to QXR 1n  by (m+2)th scanning; outputs QXL 2n  to QXL 21&#39;  QXC 20  and QXR 21  to QXR 2n  by (m+3)th scanning; . . . and outputs QXL mn  to QXL m1&#39;  QXC m0  and QXR m1  to QXL mn  by (2m+1)th scanning, respectively, in the same manner as described previously with respect FIGS. 6A and 7A. 
     Then, as in the case of the first embodiment of the present invention, the arithmetic processing circuit 51 stores the abovesaid outputs QXL jn  &#39; to QXL j1  &#39;, QXC j0  &#39; and QXR j1  &#39; to QXR jn  &#39; of the j&#39;th (j&#39;=m, (m-1), . . . 1) scanning and obtains difference outputs ΔQXL jn&#39; , ΔQXL j (n-1)&#39;, . . . ΔQXL j1  &#39;, ΔQXR j1  &#39;  WΔQXR j2  &#39;, . . . ΔQXR jn  &#39;. 
     Then the arithmetic processing circuit 51 arrays and stores the abovesaid difference outputs ΔQXL j1  &#39; to ΔQXL jn  &#39; in this order and detects the position on the array of the difference outputs where the difference output of a zero value, ΔQXL j  &#39;, appears for the first time after a plurality of difference outputs of positive values appear one after another, as viewed from the side of the difference output ΔQXL j1  &#39; to the side of the difference output QXL jn  &#39;, as in the case of the first embodiment of the present invention. 
     Thereafter the arithmetic processing circuit 51 store the output WXL j  &#39; which represents the array length from the position of the difference output ΔQXL j  &#39; to the position of the difference output ΔQXL j1  &#39;. 
     Furthermore, as in the case of the first embodiment of the present invention, the arithmetic processing circuit 51 similarly detects the position on the array of the difference outputs where the difference output of a zero value, ΔQXR j  &#39;, appears for the first time after a plurality of difference outputs of positive values appear one after another, as viewed from the side of the difference output ΔQXR j1  &#39; to the side of the difference output ΔQXR jn&#39; . Then the arithmetic processing circuit 51 stores the output WXR j  &#39; which represents the array length from the position of the difference output ΔQXR j  &#39; to the position of the difference output ΔQXR j1  &#39;. 
     Then, as in the case of the first embodiment of the present invention, the arithmetic processing circuit 51 obtains, from the output WXL j  &#39; and WXR j  &#39; representing the abovesaid array lengths, the output MX j  &#39; represented by 
     
         MX.sub.j &#39;=WXL.sub.j &#39;+WXR.sub.j&#39; 
    
     and stores it. Then the arithmetic processing circuit 51 outputs the pulse HX j  &#39;, as described previously in connection with FIG. 7B. 
     Furthermore, as in the case of the first embodiment of the present invention, the arithmetic processing circuit 51 stores the abovesaid outputs QXL 0n  to QXL 01 , QXC 00  and QXR 01  to QXR 0n  of the (m+1)th scanning and obtains the difference outputs ΔQXL 0n , ΔQXL 0 (n-1), . . . ΔQXL 01 , ΔQXR 01 , ΔQXR 02 , . . . ΔQXR 0n . 
     Then, as in the case of the first embodiment of the present invention, the arithmetic processing circuit 51 arrays and stores the abovesaid difference outputs ΔQXL 01  to ΔQXL 0n  in this order and detects the position on the array of the difference outputs where the difference output of a zero value, ΔQXK 0 , appears for the first time after a plurality of difference outputs of positive values appear one after another, as viewed from the side of the difference output ΔQXL 01  to the side of the difference output QXL 0n . 
     Thereafter the arithmetic processing circuit 51 stores the output WXL 0  which represents the array length from the position of the difference output ΔQXL 0  to the position of the difference output ΔQXL 01 . 
     Furthermore, as in the case of the first embodiment of the present invention, the arithmetic processing circuit 51 similarly detects the position on the array of the difference outputs where the difference output of a zero value, ΔQXR 0 , appears for the first time after a plurality of difference outputs of positive values appear one after another, as viewed from the side of the difference output ΔQXR 01  to the side of the difference output ΔQXR 0n . Then the arithmetic processing circuit 51 stores the output WXR 0  which represents the array length from the position of the difference output ΔQXR 0  to the position of the difference output ΔQXR 01 . 
     Then, as in the case of the first embodiment of the present invention, the arithmetic processing circuit 51 obtains, from the outputs WXL 0  and WXR 0   representing the abovesaid array lengths, an output MX 0  represented by 
     
         MX.sub.0 =WXL.sub.0 +WXR.sub.0 
    
     and stores it. Then the arithmetic processing circuit outputs the pulse HX 0 , as described previously in connection with FIG. 7B. 
     Furthermore, as in the case of the first embodiment of the present invention, the arithmetic processing circuit 51 stores the abovesaid outputs QXL jn  to QXL j1 , QXC j0  and QXR j1  to QXR jn  of the jth (j=1, 2 . . . m) scanning and obtains difference outputs ΔQXL jn , ΔQXL j (n-1), . . . ΔQXL j1 , ΔQXR j1 , ΔQXR j2 , . . . ΔQXR jn . 
     Then the arithmetic processing circuit 51 arrays and stores the abovesaid difference outputs ΔQXL j1  to ΔQXL jn  in this order. Then, as in the case of the first embodiment of the present invention, the arithmetic processing circuit 51 detects the position on the array of the difference outputs where the difference output of a zero value, appears for the first time after a plurality of difference outputs of positive values appear one after another, as viewed from the side of the difference output ΔQXL j1  to the side of the difference output QXL jn . 
     Thereafter the arithmetic processing circuit 51 stores the output WXL j  which represents the array length from the position of the difference output ΔQXL j  to the position of the difference output ΔQXL j1 . 
     Furthermore, as in the case of the first embodiment of the present invention, the arithmetic processing circuit 51 similarly detects the position on the array of the difference outputs where the difference output of a zero value, ΔQXR j , appears for the first time after a plurality of difference outputs of positive values appear one after another, as viewed from the side of the difference output ΔQXR j1  to the side of the difference output ΔQXR jn . Then the arithmetic processing circuit 51 stores the output WXR j  which represents the array length from the position of the difference output ΔQXR j  to the position of the difference output ΔQXR j1 . 
     Then, as in the case of the first embodiment of the present invention, the arithmetic processing circuit 51 obtains, from the outputs WXL j  and WXR j  representing the abovesaid array lengths, the output MX j  represented by 
     
         MX.sub.j =WXL.sub.j +WXR.sub.j 
    
     and stores it. Then the arithmetic processing circuit 51 outputs the positive pulse HX j , as described previously in respect of FIG. 7B. 
     In the manner described above, the arithmetic processing circuit 51 provides the positive pulses HX m  &#39;, HX.sub.(m-1) &#39;, . . . HX 1  &#39;, HX 0 , HX 1 , HX 2 , . . . HX m  one after another, as in the case of the first embodiment of the present invention. 
     These pulses HX m  &#39;, HX.sub.(m-1) &#39;, . . . HX 1  &#39;, HX 0  &#39;, HX 1 , HX 2 , . . . HX m  are applied via the motor drive circuit 53 to motor 35. Supplied with the pulses HX m  &#39;, HX.sub.(m-1) &#39;, . . . HX 1  &#39;, HX 0  &#39;, HX 1 , HX 2 , . . . HX m  one after another, the motor 35 rotates in the forward direction step by step. Consequently, the movable board 22 moves along the aforementioned line b--b step by step, the distance of movement for each step being equal to the aforesaid interval. 
     By such step-by-step movement of the movable board 22, the aforesaid line c--c held so far at the position relative to the holder 23 where the line is substantially in agreement with the line LX m  &#39; is brought into substantial agreement with the lines LX.sub.(m-1), LX.sub.(m-2) &#39;, . . . LX 1  &#39;, LX 0  &#39;, LX 1 , . . . LX m  one after another, as in the case of the first embodiment of the present invention. 
     Accordingly, the output WXL j  &#39; of the output MX j  &#39; represents the length from the central position O of the impression 3 of the specimen 2 to the marginal edge thereof on the side of the point PX&#39; on the aforementioned line LX j  &#39;, as described previously in connection with the first embodiment of the present invention. Further, the output WXR j  &#39; of the output MX j  &#39; represents the length of the impression 3 of the specimen 2 from the central position O of the impression 3 to its marginal edge on the side of the point PX on the line LX j  &#39;. Accordingly, the output MX j  &#39; represents the length of the impression 3 on the line LX j  &#39;. 
     Furthermore, the outputs MX 0  and MX j  represents the lengths of the impression 3 on the lines LX 0  and LX j , respectively. 
     Moreover, after generating the pulses HX m  &#39;, HX.sub.(m-1) &#39; . . . HX 1  &#39;, HX 0 , HX 1 , HX 2 , . . . HX m , the arithmetic processing circuit 51 produces g positive pulses G2 1 , G2 2 , . . . G2 g  are after another. 
     These pulses G2 1 , G2 2 , . . . G2 g  are provided via the motor drive circuit 53 to the motor 35. 
     By sequential application of the pulses G2 1&#39;  G2 2&#39;  . . . G2 g , the motor 35 rotates in the forward direction step by step. In response to this, the aforementioned movable board 22 moves step by step along the line b--b towards the line LXU p  &#39; from the position relative to the holder 23 where the aforesaid line c--c is substantially in agreement with the line LX m . In this case, let it be assumed that the distance between the lines LX m  and LXU p  &#39; is g times larger than the aforementioned spacing e. 
     Accordingly, when the motor 35 is stopped from the forward step-by-step rotation and the movable board 22 is correspondingly stopped from the step-by-step movement, the movable board 22 assumes such a position relative to the holder 23 that line LXU p  &#39; on the specimen 2 is substantially in agreement with the line of arrangement c--c of the solid-state image sensors E n  &#39; to E 1  &#39;, E 0  and E 1  to E n  of the one-dimensional scanning image sensing device 21. 
     A plurality of sets of the outputs S n  &#39; to S 1  &#39;, S 0  and S 1  to S n&#39;  which are sequentially produced by (p+q+1) scanning operations from a time point t 4  after the line of arrangement c--c has been brought into substantial agreement with the line LXU p  &#39; on the specimen 2 as described just above, will hereinafter be identified as outputs QXUL pn  &#39; to QXUL p1  &#39;, QXUC p0  &#39; and QXUR p1  &#39; to QXUR pn  &#39; by first scanning; outputs QXUL.sub.(p-1)n &#39; to QXUL.sub.(p-1)1 &#39; QXUC.sub.(p-1)0 &#39; and QXUR.sub.(p-1) &#39; to QXUR.sub.(p-1)n &#39; by second scanning; . . . outputs QXUL 1n  &#39; to QXUL 11  &#39;, QXUC 10  &#39; and QXUR 11  &#39; to QXUR 1n  &#39; by pth scanning; outputs QXUL 0n  to QXUL 01 , QXUC 00  and QXUR 01  to QXR 0n  by (p+1)th scanning; outputs QXUL 1n  to QXUL 11&#39;  QXUC 10  and QXUR 11  to QXUR 1n  by (p+2)th scanning; outputs QXUL 2n  to QXUL 21&#39;  QXUC 20  and QXUR 21  to QXUR 2n  by (p+3)th scanning, . . . and outputs QXUL qn  to QXUL q1&#39; , QXUC q0  and QXUR q1  to QXUR qn  by (p+q+1)th scanning, respectively, in the same manner as described previously with respect FIG. 8A, as shown in FIG. 13A. 
     Then the arithmetic processing circuit 51 stores the abovesaid outputs QXUL kn  &#39; to QXUL k1  &#39;, QXUC k0  &#39; and QXUR k1  &#39; to QXUR kn  &#39; of the k&#39;th (k&#39;=p, (p-1), . . . 2,1) scanning and obtains difference outputs ΔQXUL kn  &#39;, ΔQXUL k (n-1) &#39;, . . . ΔQXUL k1  &#39;, ΔQXUR k1  &#39;, ΔQXUR k2  &#39;, . . . ΔQXUR kn  &#39; which are respectively represented by ##EQU8## 
     Then the arithmetic processing circuit 51 arrays and stores the abovesaid difference outputs ΔQXUL k1  &#39; to ΔQXUL kn  &#39; in this order. 
     Then the arithmetic processing circuit 51 detects the position on the array of the difference outputs where a difference output of a zero value appears for the first time after a plurality of difference outputs of positive values appear one after another (which output will hereinafter be identified as ΔQXUL m  &#39;), as viewed from the side of the difference output ΔQXUL k1  &#39; to the side of the difference output QXUL kn  &#39;. 
     Thereafter the arithmetic processing circuit 51 stores an output which represents the array length from the position of the difference output ΔQXUL m  &#39; to the position of the difference output ΔQXUL m1  &#39; (which output will hereinafter be identified as WXUL m  &#39;). 
     Furthermore, the arithmetic processing circuit 51 similarly detects the position on the array of the difference outputs where a difference output of a zero value appears for the first time after a plurality of difference outputs of positive values appear one after another (which output will hereinafter be identified as ΔQXUR k  &#39;), as viewed from the side of the difference output ΔQXUR k1&#39;  to the side of the difference output ΔQXUR kn  &#39;. 
     Then the arithmetic processing circuit 51 stores an output which represents the array length from the position of the difference output ΔQXUR k  &#39; to the position of the difference output ΔQXUR k1  &#39; (which output will hereinafter be identified as WXUR k  &#39;). 
     Then the arithmetic processing circuit 51 obtains, from the output WXUL k  &#39; and WXUR k  &#39; representing the abovesaid array lengths, an output MXU k  &#39; represented by 
     
         MX.sub.k &#39;=WXUL.sub.k &#39;+WXUR.sub.k &#39; 
    
     and stores it. 
     Then the arithmetic processing circuit 51 outputs a pulse HXU k  &#39;, as shown in FIG. 13B. 
     Furthermore the arithmetic processing circuit 51 stores the abovesaid outputs QXUL 0n  to QXUL 01 , QXUC 00  and QXUR 01  to QXUR 0n  of the (p+1)th scanning and obtains difference outputs ΔQXUL 0n , ΔQXUL 0 (n-1), . . . ΔQXUL 01 , ΔQXUR 01 , ΔQXUR 02 , . . . ΔQXUR 0n  which are respectively represented by ##EQU9## 
     Then the arithmetic processing circuit 51 arrays and stores the abovesaid difference outputs ΔQXUL 01  to ΔQXUL 0n  in this order. 
     Then the arithmetic processing circuit 51 detects the position on the array of the difference outputs where a difference output of a zero value appears for the first time after a plurality of difference outputs of positive values appear one after another (which output will hereinafter be identified as ΔQXUL 0 ), as viewed from the side of the difference output ΔQXUL 01  to the side of the difference output QXUL 0n . 
     Thereafter the arithmetic processing circuit 51 stores an output which represents the array length from the position of the difference output ΔQXUL 0  to the position of the difference output ΔQXUL 01  (which output will hereinfter be identified as WXUL 0 ). 
     Furthermore, the arithmetic processing circuit 51 similarly detects the position on the array of the difference outputs where a difference output of a zero value appears for the first time after a plurality of difference outputs of positive values appear one after another (which output will hereinafter be identified as ΔQXUR 0 ), as viewed from the side of the difference output ΔQXUR 01  to the side of the difference output ΔQXUR 0n . 
     Then the arithmetic processing circuit 51 stores an output which represents the array length from the position of the difference output ΔQXUR 0  to the position of the difference output ΔQXUR 01  (which output will hereinafter be identified as WXUR 0 ). 
     Then the arithmetic processing circuit 51 obtains, from the outputs WXUL 0  and WXUR 0  representing the abovesaid array lengths, an output MXU 0  represented by 
     
         MXU.sub.0 =WXUL.sub.0 +WXUR.sub.0 
    
     and stores it. Then the arithmetic processing circuit 51 outputs a pulse HXU 0 , as shown in FIG. 13B. 
     Furthermore the arithmetic processing circuit 51 stores the abovesaid outputs QXUL kn  to QXUL k1 , QXUC k0  and QXUR k1  to QXUR kn  of the kth (k=1, 2, . . . q) scanning and obtains difference outputs ΔQXUL kn , ΔQXUL k (n-1), . . . ΔQXUL k1 , ΔQXUR k1 , ΔQXUR k2 , . . . ΔQXUR kn  which are respectively represented by ##EQU10## 
     Then the arithmetic processing circuit 51 arrays and stores the abovesaid difference outputs ΔQXUL k1  to ΔQXUL kn  in this order. 
     Then the arithmetic processing circuit 51 detects the position on the array of the difference outputs where a difference output of a zero value appears for the first time after a plurality of difference outputs of positive values appear one after another (which output will hereinafter be identified as ΔQXUL k ), as viewed from the side of the difference output ΔQXUL k1  to the side of the difference output QXUL kn . 
     Thereafter the arithmetic processing circuit 51 stores an output which represents the array length from the position of the difference output ΔQXUL k  to the position of the difference output ΔQXUL k1  (which output will hereinfter be identified as WXUL k ). 
     Furthermore, the arithmetic processing circuit 51 similarly detects the position on the array of the difference outputs where a difference output of a zero value appears for the first time after a plurality of difference outputs of positive values appear one after another (which output will hereinafter be identified as ΔQXUR k ), as viewed from the side of the difference output ΔQXUR k1  to the side of the difference output ΔQXUR kn . 
     Then the arithmetic processing circuit 51 stores an output which represents the array length from the position of the difference output ΔQXUR k  to the position of the difference output ΔQXUR k1  (which output will hereinafter be identified as WXUR k ). 
     Then the arithmetic processing circuit 51 obtains, from the outputs WXUL k  and WXUR k  representing the abovesaid array lengths, an output MXU k  represented by 
     
         MXU.sub.k =WXUL.sub.k +WXUR.sub.k 
    
     and stores it. Then the arithmetic processing circuit 51 outputs a pulse HXU k , as shown in FIG. 13B. 
     In the manner described above, the arithmetic processing circuit 51 provides pulses HXU p  &#39;, HXU.sub.(p-1) &#39;, . . . HXU 1  &#39;, HXU 0 , HXU 1 , HXU 2 , . . . HXU q  one after another. 
     These pulses HXU p  &#39;, HXU.sub.(p-1) &#39;, . . . HXU 1  &#39;, HXU 0  &#39;, HXU 1 , HXU 2 , . . . HXU q  are applied via the motor drive circuit 53 to motor 35. 
     Supplied with the pulses HXU p  &#39;, HXU.sub.(p-1) &#39;, . . . HXU 1  &#39;, HXU 0 , HXU 1 , HXU 2 , . . . HXU q  one after another, the motor 35 rotates in the forward direction step by step. Consequently, the movable board 22 moves along the aforementioned line b--b step by step to the side opposite from the line LX m  from such a position relative to the holder 23 that the aforesaid line c--c is substantially in agreement with the line LXU p  &#39;. 
     By such step-by-step movement of the movable board 22, the aforesaid line c--c held so far at the position relative to the holder 23 where the line is substantially in agreement with the line LXU p  &#39; is brought into substantial agreement with the lines LXU.sub.(p-1), LXU.sub.(p-2) &#39;, . . . LXU 1  &#39;, LXU 0 , LXU 1 , . . . LXU q  one after another. 
     Accordingly, the output MXUL k  &#39; of the output MXU k  &#39; represents the length from the central position O of the impression 3 of the specimen 2 to the marginal edge thereof on the side of the point PX&#39; on the aforementioned line LXD k&#39; . 
     The reason is as follows: The output WXUL k  &#39; is representative of the array length from the position of the aforesaid difference output ΔQXUL k1  &#39; to the position of the difference output ΔQXUL k  &#39;. On the other hand, the difference output ΔQXUL k1  &#39; is the difference output of a zero value that appears for the first time on the array after a plurality of difference outputs of positive values appear one after another, as viewed from the side of the difference output ΔQXUL k1  &#39; to the side of the difference output ΔQXUL kn  &#39;. Accordingly, the position of the difference output ΔQXUL k  &#39; on the array corresponds to the marginal edge of the impression 3 on the line LXU k  &#39; on the side of the point PX&#39;, as will be evident from the description given previously of the general outputs S n  &#39;, S.sub.(n-1) &#39;, . . . S 1  &#39;, S 0 , S 1 , S 2 , . . . S.sub.(n-1), S n  with reference to FIGS. 4C and D. 
     For the same reason as mentioned above, the output WXUR k  &#39; of the output MXU k  &#39; represents the length of the impression 3 of the specimen 2 on the line LXU k  &#39; from the central position of the impression 3 to its marginal edge on the side of the point PX on the line LXU k  &#39;. 
     Accordingly, the output MXU k  &#39; represents the length of the impression 3 on the line LXU k  &#39;. 
     Furthermore, for the same reason as given above, the outputs MXU 0  and MXU k  represents the lengths of the impression 3 on the lines LXU 0  and LXU k , respectively. In this case, however, since the lines LXU 0  and LXU k  do not extend across the empression 3, the outputs MXU 0  and MXL k  are obtained as zero. 
     Moreover, after generating the pulses HXU p  &#39;, HXU.sub.(p-1) &#39;. . . HXU 1  &#39;, HXU 0 , HXU 1 , HXU 2 , . . . HXU q , the arithmetic processing circuit 51 yields z negative pulses G3 1 , G3 2 , . . . G3 z  one another, which are provided via the motor drive circuit 53 to the motor 35. 
     By sequential application of the pulses G3 1  &#39; G3 2  &#39;. . . G3 z  &#39; the motor 35 rotates in the reverse direction step by step. In response to this, the aforementioned movable board 22 moves step by step along the line b--b towards the line LXD p  &#39; from the position relative to the holder 23 where the aforesaid line c--c is substantially in agreement with the line LXU q . In this case, let it be assumed that the distance between the lines LU p  and LXD p  is z (where z is number of pulses G3 1  to G3 z ) times larger than the aforesaid spacing e. 
     Accordingly, when the motor 35 stopped from the reverse step-by-step rotation and the movable pg,77 board 22 is correspondingly stopped from the step-by-step movement, the movable board 22 assumes such a position relative to the holder 23 that line LXD p  on the specimen 2 is substantially in agreement with the line of arrangement c--c of the solid-state image sensors E n  &#39; to E 1  &#39;, E 0  and E 1  to E n . 
     A plurally of sets of the outputs S n  &#39; to S 1  &#39;, S 0  and S 1  to S n  &#39; which are sequentially produced by (p+q+1) scanning operations from a time point t 5  after the line of arrangement c--c has been brought into substantial agreement with the line LXD p  &#39; on the specimen 2 as described just above, will hereinafter be identified as outputs QXDL pn  &#39; to QXDL p1  &#39;, QXDC p0  &#39; and QXDR p1  &#39; to QXDR pn  &#39; by first scanning; outputs QXDL.sub.(p-1)n &#39; to QXDL.sub.(p-1)1 &#39;, QXDC.sub.(p-1)0 &#39; and QXDR.sub.(p-1) &#39; to QXDR.sub.(p-1)n &#39; by second scanning; . . . outputs QXDL 1n  &#39; to QXDL 11  &#39;, QXDC 10  &#39; and QXDR 11  &#39; to QXDR 1n  &#39; by pth scanning; outputs QXDL 0n  to QXDL 01 , QXDC 00  and QXDR 01  to QXDR 0n  by (p+1)th scanning; outputs QXDL 1n  to QXDL 11  &#39; QXDC 10  and QXDR 11  to QXDR 1n  by (p+2)th scanning; outputs QXDL 2n  to QXDL 21  &#39; QXDC 20  and QXDR 21  to QXDR 2n  by (p+3)th scanning; . . . and outputs QXDL qn  to QXDL q1  &#39; QXDC q0  and QXDR q1  to QXDL qn  by (p+q+1)th scanning, respectively, in the same manner as described previously with respect FIG. 13A, as shown in FIG. 14A. 
     Then the arithmetic processing circuit 51 stores the abovesaid outputs QXDL kn  &#39; to QXDL k1  &#39;, QXdC k0  &#39; and QXDR k1  &#39; to QXdR kn  &#39; of the k&#39;th (k&#39;=p, (p-1), . . . 1) scanning and obtains difference outputs ΔQXDL kn  &#39;, ΔQXDL k (n-1) &#39;, . . . ΔQXDL k1  &#39;, ΔQXDR k1  &#39;, ΔQXDR k2  &#39;, . . . ΔQXDR kn  &#39; which are respectively represented by ##EQU11## 
     Then the arithmetic processing circuit 51 arrays and stores the abovesaid difference outputs ΔQXDL k1  &#39; to ΔQXDL kn  &#39; in this order. 
     Then the arithmetic processing circuit 51 detects the position on the array of the difference outputs where a difference output of a zero value appears for the first time after a plurality of difference outputs of positive values appear one after another (which output will hereinafter be identified as ΔQXDL m  &#39;), as viewed from the side of the difference output ΔQXDL k1  &#39; to the side of the difference output QXDL kn  &#39; 
     Thereafter the arithmetic processing circuit 51 stores an output which represents the array length from the position of the difference output ΔQXDL m  &#39; to the position of the difference output ΔQXDL m1  &#39; (which output will hereinfter be identified as WXDL m  &#39;). 
     Furthermore, the arithmetic processing circuit 51 similarly detects the position on the array of the difference outputs where a difference output of a zero value appears for the first time after a plurality of difference outputs of positive values appear one after another (which output will hereinafter be identified as ΔQXDR k  &#39;), viewed from the side of the difference output ΔQXDR k1  &#39; to the side of the difference output ΔQXDR kn  &#39;. 
     Then the arithmetic processing circuit 51 stores an output which represents the array length from the position of the difference output ΔQXDR k  &#39; to the position of the difference output ΔQXDR k1  &#39; (which output will hereinafter be identified as WXDR k  &#39;). 
     Then the arithmetic processing circuit 51 obtains, from the outputs WXDL k  &#39; and WXDR k  &#39; representing the abovesaid array lengths, an output MX k  &#39; represented by 
     MXk k  &#39;=WXDL k&#39;+WXDR   k  &#39; 
     and stores it. 
     Then the arithmetic processing circuit 51 outputs a pulse HXD k  &#39;, as shown in FIG. 14B. 
     Furthermore the arithmetic processing circuit 51 stores the abovesaid outputs QXDL 0n  to QXDL 01 , QXDC 00  and QXDR 01  to QXDR 0n  of the (p+1)th scanning and obtains difference outputs ΔQXDL 0n , ΔQXDL 0 (n-1), . . . ΔQXDL 01 , ΔQXDR 01 , WΔQXDR 02 , . . . ΔQXDR 0n  which are respectively represented by ##EQU12## Then the arithmetic processing circuit 51 arrays and stores the abovesaid difference outputs ΔQXDL 01  to ΔQXDL 0n  in this order. 
     Then the arithmetic processing circuit 51 detects the position on the array of the difference outputs where a difference output of a zero value appears for the first time after a plurality of difference outputs of positive values appear one after another (which output will hereinafter be identified as ΔQXDL 0 ), as viewed from the side of the difference output ΔQXDL 01  to the side of the difference output QXDL 0n . 
     Thereafter the arithmetic processing circuit 51 stores an output which represents the array length from the position of the difference output ΔQXDL 0  to the position of the difference output ΔQXDL 01  (which output will hereinfter be identified as WXDL 0 ). 
     Furthermore, the arithmetic processing circuit 51 similarly detects the position on the array of the difference outputs where a difference output of a zero value appears for the first time after a plurality of difference outputs of positive values appear one after another (which output will hereinafter be identified as ΔQXDR 0 ), as viewed from the side of the difference output ΔQXDR 01  to the side of the difference output ΔQXDR 0n . 
     Then the arithmetic processing circuit 51 stores an output which represents the array length from the position of the difference output ΔQXDR 0  to the position of the difference output ΔQXDR 01  (which output will hereinafter be identified as WXDR 0 ). 
     Then the arithmetic processing circuit 51 obtains, from the outputs WXDL 0  and WXDR 0  representing the abovesaid array lengths, an output MXD 0  represented by MXD 0  =WXDL 0  +WXDR 0  and stores it. Then the arithmetic processing circuit outputs a pulse HXD 0 , as shown in FIG. 14B. 
     Furthermore the arithmetic processing circuit 51 stores the abovesaid outputs QXDL kn  to QXDL k1 , QXDC k0  and QXDR k1  to QXDR kn  of the kth scanning and obtains difference outputs ΔQXDL kn , ΔQXDL k (n-1), . . . ΔQXDL k1 , ΔQXDR k1 , WΔQXDR k2 , . . . ΔQXDR kn  which are respectively represented by ##EQU13## 
     Then the arithmetic processing circuit 51 arrays and stores the abovesaid difference outputs ΔQXDL k1  to ΔQXDL kn  in this order. 
     Then the arithmetic processing circuit 51 detects the position on the array of the difference outputs where a difference output of a zero value appears for the first time after a plurality of difference outputs of positive values appear one after another (which output will hereinafter be identified as ΔQXDL k ), as viewed from the side of the difference output ΔQXDL k1  to the side of the difference output QXDL kn . 
     Thereafter the arithmetic processing circuit 51 stores an output which represents the array length from the position of the difference output ΔQXDL k  to the position of the difference output ΔQXDL k1  (which output will hereinafter be identified as WXDL k ). 
     Furthermore, the arithmetic processing circuit 51 similarly detects the position on the array of the difference outputs where a difference output of a zero value appears for the first time after a plurality of difference outputs of positive values appear one after another (which output will hereinafter be identified as ΔQXDR k ), as viewed from the side of the difference output ΔQXDR k1  to the side of the difference output ΔQXDR kn . 
     Then the arithmetic processing circuit 51 stores an output which represents the array length from the position of the difference output ΔQXDR k  to the position of the difference output ΔQXDR k1  (which output will hereinafter be identified as WXDR k ). 
     Then the arithmetic processing circuit 51 obtains, from the outputs WXDL k  and WXDR k  representing the abovesaid array lengths, an output MXD k  represented by 
     
         MXD.sub.k =WXDL.sub.k +WXDR.sub.k 
    
     and stores it. Then the arithmetic processing circuit 51 outputs a pulse HXD k , as shown in FIG. 14B. 
     In the manner described above, the arithmetic processing circuit 51 provides pulses HXD p  &#39;, HXD.sub.(p-1) &#39;, . . . HXD 1  &#39;, HXD 0 , HXD 1 , HXD 2 , . . . HXD q  one after another. 
     These pulses HXD p  &#39;, HXD.sub.(p-1) &#39;, . . . HXD 1  &#39;, HXD 0 , HXD 1 , HXD 2 , . . . HXD q  are applied via the motor drive circuit 53 to motor 35. 
     Supplied with the pulses HXD p  &#39;, HXD.sub.(p-1) &#39;, . . . HXD 1  &#39;, HXD 0  &#39;, HXD 1 , HXD 2 , . . . HXD q  one after another, the motor 35 rotates in the forward direction step by step. Consequently, the movable board 22 moves along the aforementioned line b--b step by step to the side opposite from the line LX m  from such a position relative to the holder 23 that the aforesaid line c--c is substantially in agreement with the line LXD p  &#39;. By such step-by-step movement of the movable board 22, the aforesaid line c--c held so far at the position relative to the holder 23 where the line is substantially in agreement with the line LXD p  &#39; is brought into substantial agreement with the lines LXD.sub.(p-1), LXD.sub.(p-2), . . . LXD 1 , LXD 0 , LXD 1  &#39;, . . . LXD q  &#39; one after another. Accordingly, the output MXDL k  &#39; of the output MXD k  &#39; represents the length from the central position O of the impression 3 of the specimen 2 to the marginal edge thereof on the side of the point PX&#39; on the aforementioned line LXD k  &#39;. 
     The reason is as follows: The output WXDL k  &#39; is representative of the array length from the position of the aforesaid difference output ΔQXDL k  &#39; to the position of the difference output ΔQXDL k1  &#39;. On the other hand, the difference output ΔQXDL k  &#39; is the difference output of a zero value that appears for the first time on the array after a plurality of difference outputs of positive values appear one after another, as viewed from the side of the difference output ΔQXDL k1 , to the side of the difference output ΔQXDL kn  &#39;. Accordingly, the position of the difference output ΔQXDL k  &#39; on the array corresponds to the marginal edge of the impression 3 on the line LXD k  on the side of the point PX&#39;, as will be evident from the description given previously of the general outputs S n  &#39;, S.sub.(n-1) &#39;, . . . S 1  &#39;, S 0 , S 1 , S 2 , . . . S.sub.(n-1) &#39;, S n  with reference to FIGS. 4C and D. 
     For the same reason as mentioned above, the output WXdR k  &#39; of the output MXD k  &#39; represents the length of the impression 3 of the specimen 2 on the line LXD k  &#39; from the central position O of the impression 3 to its marginal edge on the side of the point PX on the line LXD k  &#39;. 
     Accordingly, the output MXD k  &#39; represents the length of the impression 3 on the line LXD k  &#39;. 
     Furthermore, for the same reason as given above, the outputs MXD 0  and MXD k  represents the lengths of the impression 3 on the lines LXD 0  and LXD k , respectively. In this case, however, since the lines LXD 0  and LXD k  do not cross the impression 3, the outputs MXD 0  and MXD k  are zero. 
     The arithmetic processing circuit 51 stores the outputs MXU p  &#39; to MXU 1 , MXU 0  and MXU 1  to MXU q  and outputs MXD p  &#39; to MXD 1  &#39; and MXD 1  to MXD q , together with the aforementioned outputs MX m  &#39; to MX 1 , MX 0  and MX 1  to MX m . 
     As in the case of the first embodiment of the present invention, the arithmetic processing circuit 51 detects the maximum output MX among the outputs MX m  &#39; to MX 1  &#39;, MX 0  and MX 1  to MX m  and yields the output MX. The output MX is the output MX 0  when the outputs MX m  &#39; to MX 1  &#39;, MX 0  and MX 1  to MX m  are obtained as described above. 
     The output MX represents the length NX of the first diagonal joining the points PX and PX&#39; of the impression 3 of the specimen 2, as will be seen from the foregoing description. 
     Further, as described above, the arithmetic processing circuit 51 stores the outputs MXU p  &#39;, MXU.sub.(p-1) &#39;, . . . MXU 1  &#39;, MXU 0 , MXU 1 , MXU 2 , . . . MXU q  in this sequential order. 
     Then the arithmetic processing circuit 51 detects the position on the array of the above outputs where an output of a zero value appears for the first time after a plurality of outputs of other values appear one after another, as viewed from the side of the output MXU p  &#39; to the side of the output MXU q  (which output will hereinafter be identified as MYU). 
     Then the arithmetic processing circuit 51 stores an output which represents the array length from the position of the output MYU to the position of the output MXU 0  (which output will hereinafter be identified as WYU). 
     Moreover, the arithmetic processing circuit 51 stores the outputs MXD p  &#39;, MXD.sub.(p-1) &#39;, . . . MXD 1  &#39;, MXD 0 , MXD 1 , MXD 2 , . . . MXD q  in this sequential order, as described above. Then the arithmetic processing circuit detects the position on the array of the outputs where an output of a zero value appears for the first time after a plurality of outputs of other values one after another (which output will hereinafter be identified as MYD), as viewed from the side of the output MXD p  &#39; to the side of the output MXD q . 
     Then the arithmetic processing circuit 51 stores an output which represents the array length from the position of the output MYD to the position of the output MYD 0  (which output will hereinafter be identified as WYD). 
     Thereafter the arithmetic processing circuit 51 obtains from the outputs WYU and WYD the output MY represented by 
     
         MY=WYU and WYD 
    
     The output MY represents the length NY of the second diagonal joining the points PY and PY&#39; of the impression 3 of the specimen 2. 
     As described above, according to the second embodiment of the indentation hardness meter of the present invention, too, the lengths NX and NY of the first and second diagonals of the impression 3 made in the specimen 2 can be measured. Accordingly, the hardness of the specimen 2 can be measured from the lengths NX and NY. 
     Further, according to the second embodiment of the indentation hardness meter of the present invention described in the foregoing, too, the impression 3 made in the specimen 2 is imaged by one-dimensional scanning through the use of the one-dimensional image sensing device 21 and the outputs representing the lengths of the first and second diagonals of the impression 3 are obtained from the image output. Accordingly, the indentation hardness meter of the present invention has such a great feature that the image sensing device for obtaining the first and second diagonal-length signals may be a simple, small and inexpensive one-dimensional scanning image sensing device. 
     Moreover, the second embodiment of the indentation hardness meter of the present invention also does not involve scanning the entire area of the impression by the one-dimensional scanning image sensing device, and hence it has striking features that the first and second diagonal-length signals can be obtained at high speed and that the entire arrangement is simple. 
     While the present invention has been described as being applied to the indentation hardness meter of the type that makes a quadrangular pyramidal impression in the specimen, it will be evident that the present invention can be applied to an indentation hardness meter which makes a spherical impression in the specimen. 
     Various other modification and variations may be effected without departing from the spirits of the present invention.