Patent Publication Number: US-8982633-B2

Title: Techniques for providing a direct injection semiconductor memory device

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This patent application is a continuation of U.S. patent application Ser. No. 12/785,971, filed May 24, 2010, which claims priority to U.S. Provisional Patent Application No. 61/180,810, filed May 22, 2009, each of which is hereby incorporated by reference herein in its entirety. 
    
    
     FIELD OF THE DISCLOSURE 
     The present disclosure relates generally to semiconductor memory devices and, more particularly, to techniques for providing a direct injection semiconductor memory device. 
     BACKGROUND OF THE DISCLOSURE 
     The semiconductor industry has experienced technological advances that have permitted increases in density and/or complexity of semiconductor memory devices. Also, the technological advances have allowed decreases in power consumption and package sizes of various types of semiconductor memory devices. There is a continuing trend to employ and/or fabricate advanced semiconductor memory devices using techniques, materials, and devices that improve performance, reduce leakage current, and enhance overall scaling. Silicon-on-insulator (SOI) and bulk substrates are examples of materials that may be used to fabricate such semiconductor memory devices. Such semiconductor memory devices may include, for example, partially depleted (PD) devices, fully depleted (FD) devices, multiple gate devices (for example, double, triple, or surrounding gate), and bipolar junction transistor (BJT) devices. 
     A semiconductor memory device may include a memory cell having a memory transistor with an electrically floating body region wherein electrical charges may be stored. When excess majority electrical charge carriers are stored in the electrically floating body region, the memory cell may store a logic high (e.g., binary “1” data state). When the electrical floating body region is depleted of majority electrical charge carriers, the memory cell may store a logic low (e.g., binary “0” data state). Also, a semiconductor memory device may be fabricated on silicon-on-insulator (SOI) substrates or bulk substrates (e.g., enabling body isolation). For example, a semiconductor memory device may be fabricated as a three-dimensional (3-D) device (e.g., multiple gate devices, bipolar junction transistors (BJTs), recessed gates and pillars) on a silicon-on-insulator (SOI) or bulk substrates. 
     In one conventional technique, the memory cell of the semiconductor memory device may be read by applying bias signals to a source/drain regions and/or a gate of the memory transistor. As such, a conventional reading technique may involve sensing an amount of current provided/generated by/in the electrically floating body region of the memory cell in response to the application of the source/drain region and/or gate bias signals to determine a data state stored in the memory cell. For example, the memory cell may have two or more different current states corresponding to two or more different logical states (e.g., two different current conditions/states corresponding to two different logic states: a binary “0” data state and a binary “1” data state). 
     In another conventional technique, the memory cell of the semiconductor memory device may be written to by applying bias signals to the source/drain region(s) and/or the gate of the memory transistor. As such, a conventional writing technique may result in an increase/decrease of majority charge carriers in the electrically floating body region of the memory cell which, in turn, may determine the data state of the memory cell. An increase of majority charge carriers in the electrically floating body region may result from impact ionization, band-to-band tunneling (gate-induced drain leakage “GIDL”), or direct injection. A decrease of majority charge carriers in the electrically floating body region may result from charge carriers being removed via drain region charge carrier removal, source region charge carrier removal, or drain and source region charge carrier removal, for example, using back gate pulsing. 
     Often, conventional reading and/or writing operations may lead to relatively large power consumption and large voltage potential swings which may cause disturbance to unselected memory cells in the semiconductor memory device. Also, pulsing between positive and negative gate biases during read and write operations may reduce a net quantity of majority charge carriers in the electrically floating body region of the memory cell in the semiconductor memory device, which, in turn, may result in an inaccurate determination of the state of the memory cell. Furthermore, in the event that a bias is applied to the gate of the memory transistor that is below a threshold voltage potential of the memory transistor, a channel of minority charge carriers beneath the gate may be eliminated. However, some of the minority charge carriers may remain “trapped” in interface defects. Some of the trapped minority charge carriers may recombine with majority charge carriers, which may be attracted to the gate as a result of the applied bias. As a result, the net quantity of majority charge carriers in the electrically floating body region may be reduced. This phenomenon, which is typically characterized as charge pumping, is problematic because the net quantity of majority charge carriers may be reduced in the electrically floating body region of the memory cell, which, in turn, may result in an inaccurate determination of the state of the memory cell. 
     In view of the foregoing, it may be understood that there may be significant problems and shortcomings associated with conventional techniques for operating semiconductor memory devices. 
     SUMMARY OF THE DISCLOSURE 
     Techniques for providing a direct injection semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a direct injection semiconductor memory device comprising a first region connected to a bit line extending in a first orientation and a second region connected to a source line extending in a second orientation. The direct injection semiconductor memory device may also comprise a body region spaced apart from and capacitively coupled to a word line extending in the second orientation, wherein the body region is electrically floating and disposed between the first region and the second region. The direct injection semiconductor memory device may further comprise a third region connected to a carrier injection line extending in the second orientation, wherein the first region, the second region, the body region, and the third region are disposed in sequential contiguous relationship. 
     In accordance with other aspects of the particular exemplary embodiment, the first region and the second region may be N-doped regions. 
     In accordance with further aspects of this particular exemplary embodiment, the body region and the third region may be a P-doped region. 
     In accordance with additional aspects of this particular exemplary embodiment, the first region, the body region, and the second regions may form a first bipolar junction transistor (BJT). 
     In accordance with yet another aspect of this particular exemplary embodiment, the body region, the second region, and the third region may form a second bipolar junction transistor (BJT). 
     In accordance with other aspects of the particular exemplary embodiment, the bit line may be connected to the first region via a bit line contact. 
     In accordance with further aspects of this particular exemplary embodiment, the source line may be connected to the second region via a source line contact. 
     In accordance with additional aspects of this particular exemplary embodiment, the word line may be circumferentially surrounded by an insulating/dielectric material. 
     In accordance with yet another aspect of this particular exemplary embodiment, the carrier injection line may be circumferentially surrounded by an insulating/dielectric material. 
     In accordance with other aspects of the particular exemplary embodiment, the carrier injection line may include an ohmic contact on a plurality of side portions of the third region in a fin configuration. 
     In accordance with further aspects of this particular exemplary embodiment, the word line may be disposed to cover a plurality of side portions of the body region in a fin configuration. 
     In accordance with additional aspects of this particular exemplary embodiment, the device may further comprise a plurality of barrier walls configured on a continuous planar region. 
     In accordance with yet another aspect of this particular exemplary embodiment, the device may further comprise a substrate disposed below the plurality of barrier walls. 
     In another exemplary embodiment, the technique may be realized as a method for biasing a direct injection semiconductor memory device. The method may comprise applying a first voltage potential to a first region via a bit line extending in a first orientation and applying a second voltage potential to a second region via a source line extending in a second orientation. The method may also comprise applying a third voltage potential to a body region via a word line extending in the second orientation, wherein the body region is electrically floating and capacitively coupled to the word line. The method may further comprise applying a fourth voltage potential to a third region via a carrier injection line extending in the second orientation, wherein the first region, the second region, the body region, and the third region are disposed in sequential contiguous relationship. 
     In accordance with other aspects of the particular exemplary embodiment, the method may further comprise increasing the third voltage potential applied to the word line from the third voltage potential applied to the word line during a hold operation to perform a read operation. 
     In accordance with further aspects of this particular exemplary embodiment, the method may further comprise increasing the second voltage potential applied to the source line from the second voltage potential applied to the source line during a hold operation to perform a read operation. 
     In accordance with additional aspects of this particular exemplary embodiment, the method may further comprise maintaining the first voltage potential applied during a hold operation and maintaining the fourth voltage potential applied to the carrier injection line during the hold operation to perform a read operation. 
     In accordance with yet another aspect of this particular exemplary embodiment, the method may further comprise maintaining the third voltage potential applied to the word line from the third voltage potential applied to the word line during a hold operation to perform a write logic high operation. 
     In accordance with other aspects of the particular exemplary embodiment, the method may further comprise maintaining the second voltage potential applied to the second region via the source line from the second voltage potential applied to the second region during a hold operation to perform a write logic high operation. 
     In accordance with further aspects of this particular exemplary embodiment, the method may further comprise increasing the fourth voltage potential applied to the third region via the carrier injection line from the fourth voltage applied to the third region during a hold operation to perform a write logic high operation. 
     In accordance with additional aspects of this particular exemplary embodiment, the method may further comprise increasing the third voltage potential applied to the word line from the third voltage potential applied to the word line during a hold operation to perform a write logic low operation. 
     In accordance with yet another aspect of this particular exemplary embodiment, the method may further comprise increasing the second voltage potential applied to the source line from the second voltage potential applied to the source line during a hold operation to perform a write logic low operation. 
     In accordance with other aspects of the particular exemplary embodiment, the method may further comprise maintaining the first voltage potential applied to the bit line from the first voltage potential applied to the bit line during a hold operation to perform a write logic low operation. 
     In accordance with further aspects of this particular exemplary embodiment, the method may further comprise increasing the first voltage potential applied to the bit line during a write logic low operation from the first voltage potential applied to the bit line during a hold operation to maintain a logic high stored in the memory cell. 
     The present disclosure will now be described in more detail with reference to exemplary embodiments thereof as shown in the accompanying drawings. While the present disclosure is described below with reference to exemplary embodiments, it should be understood that the present disclosure is not limited thereto. Those of ordinary skill in the art having access to the teachings herein will recognize additional implementations, modifications, and embodiments, as well as other fields of use, which are within the scope of the present disclosure as described herein, and with respect to which the present disclosure may be of significant utility. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       In order to facilitate a fuller understanding of the present disclosure, reference is now made to the accompanying drawings, in which like elements are referenced with like numerals. These drawings should not be construed as limiting the present disclosure, but are intended to be exemplary only. 
         FIG. 1  shows a schematic block diagram of a semiconductor memory device including a memory cell array, data write and sense circuitry, and memory cell selection and control circuitry in accordance with an embodiment of the present disclosure. 
         FIG. 2  shows a schematic diagram of at least a portion of a memory cell array having a plurality of memory cells in accordance with an embodiment of the present disclosure. 
         FIG. 3  shows a top view of a portion of a memory cell array having a plurality of memory cells in accordance with an embodiment of the present disclosure. 
         FIG. 4  shows a first cross-sectional view of a portion of a memory cell array having a plurality of memory cells along line A-A of  FIG. 3  in accordance with an embodiment of the present disclosure. 
         FIG. 5  shows a second cross-sectional view of a portion of a memory cell array having a plurality of memory cells along line B-B of  FIG. 3  in accordance with an embodiment of the present disclosure. 
         FIG. 6  shows a third cross-sectional view of a portion of a memory cell array having a plurality of memory cells along line C-C of  FIG. 3  in accordance with an embodiment of the present disclosure. 
         FIG. 7  shows a top view of a portion of a memory cell array in accordance with an embodiment of the present disclosure. 
         FIG. 8  shows control signal voltage waveforms for performing a refresh operation on a memory cell in accordance with an embodiment of the present disclosure. 
     
    
    
     DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS 
     Referring to  FIG. 1 , there is shown a schematic block diagram of a semiconductor memory device  10  comprising a memory cell array  20 , data write and sense circuitry  36 , and memory cell selection and control circuitry  38  in accordance with an embodiment of the present disclosure. The memory cell array  20  may comprise a plurality of memory cells  12  each connected to the memory cell selection and control circuitry  38  via a word line (WL)  28 , a source line (CN)  30 , and/or a carrier injection line (EP)  34 , and the data write and sense circuitry  36  via a bit line (EN)  32 . It may be appreciated that the source line (CN)  30  and the bit line (EN)  32  are designations used to distinguish between two signal lines and they may be used interchangeably. 
     The data write and sense circuitry  36  may read data from and may write data to selected memory cells  12 . In an exemplary embodiment, the data write and sense circuitry  36  may include a plurality of data sense amplifiers. Each data sense amplifier may receive at least one bit line (EN)  32  and a current or voltage reference signal. For example, each data sense amplifier may be a cross-coupled type sense amplifier to sense a data state stored in a memory cell  12 . Also, each data sense amplifier may employ voltage and/or current sensing circuitry and/or techniques. In an exemplary embodiment, each data sense amplifier may employ current sensing circuitry and/or techniques. For example, a current sense amplifier may compare current from a selected memory cell  12  to a reference current (e.g., the current of one or more reference cells). From that comparison, it may be determined whether the selected memory cell  12  contains a logic high (e.g., binary “1” data state) or a logic low (e.g., binary “0” data state). It may be appreciated by one having ordinary skill in the art that various types or forms of data write and sense circuitry  36  (including one or more sense amplifiers, using voltage or current sensing techniques, using or not reference cells, to sense a data state stored in a memory cell  12 ) may be employed to read data stored in memory cells  12  and/or write data to memory cells  12 . 
     The memory cell selection and control circuitry  38  may select and/or enable one or more predetermined memory cells  12  to facilitate reading data therefrom and/or writing data thereto by applying control signals on one or more word lines (WL)  28 , source lines (CN)  30 , and/or carrier injection lines (EP)  34 . The memory cell selection and control circuitry  38  may generate such control signals from address signals, for example, row address signals. Moreover, the memory cell selection and control circuitry  38  may include a word line decoder and/or driver. For example, the memory cell selection and control circuitry  38  may include one or more different control/selection techniques (and circuitry therefore) to select and/or enable one or more predetermined memory cells  12 . Notably, all such control/selection techniques, and circuitry therefore, whether now known or later developed, are intended to fall within the scope of the present disclosure. 
     In an exemplary embodiment, the semiconductor memory device  10  may implement a two step write operation whereby all the memory cells  12  in a row of memory cells  12  may be first written to a predetermined data state. For example, the memory cells  12  in a row of memory cells  12  may be first written to a logic high binary “1” data state) by executing a logic high (e.g., binary “1” data state) write operation. Thereafter, selected memory, cells  12  in the active row of memory cells  12  may be selectively written to a logic low (e.g., binary “0” data state) by executing a logic low (e.g., binary “0” data state) write operation. The semiconductor memory device  10  may also implement a one step write operation whereby selected memory cells  12  in an active row of memory cells  12  may be selectively written to either a logic high (e.g., binary “1” data state) or a logic low (e.g., binary “0” data state) without first implementing, a “clear” operation. The semiconductor memory device  10  may employ any of the exemplary writing, refreshing, holding, and/or reading techniques described herein. 
     The memory cells  12  may comprise one or more multi-gate devices or multiple gate field effect transistors. In an exemplary embodiment, the memory cells  12  may comprise one or more N-type bipolar junction transistors (BJTs), P-type bipolar junction transistors (BJTs) and/or both types of bipolar junction transistors (BJTs). Circuitry that is peripheral to the memory array  20  (for example, sense amplifiers or comparators, row and column address decoders, as well as line drivers (not illustrated herein)) may also include P-type and/or N-type bipolar junction transistors (BJTs) or P-type and/or N-type transistors. Regardless of whether P-type bipolar junction transistors (BJTs) or N-type bipolar junction transistors (BJTs) are employed in memory cells  12  in the memory array  20 , suitable voltage potentials (for example, positive or negative voltage potentials) for reading from and/or writing to the memory cells  12  may be applied. 
     Referring to  FIG. 2 , there is shown a schematic diagram of at least a portion of the memory cell array  20  having the plurality of memory cells  12  in accordance with an embodiment of the present disclosure. Each of the memory cells  12  may comprise a first bipolar junction transistor (BJT)  14   a  and a second bipolar junction transistor (BJT)  14   b  coupled to each other. For example, the first bipolar junction transistor (BJT)  14   a  and/or the second bipolar junction transistor (BJT)  14   b  may be an N-type bipolar junction transistor (BJT) or a P-type bipolar junction transistor (BJT). As illustrated in  FIG. 2 , the first bipolar junction transistor (BJT)  14   a  may be an N-type bipolar junction transistor (BJT) and the second bipolar junction transistor (BJT)  14   b  may be a P-type bipolar junction transistor (BJT). In another exemplary embodiment, the first bipolar junction transistor (BJT)  14   a  may be a P-type bipolar junction transistor (BJT) and the second bipolar junction transistor (BJT)  14   b  may be an N-type bipolar junction transistor (BJT). 
     Each memory cell  12  may be coupled to a respective word line (WL)  28 , a respective source line (CN)  30 , a respective bit line (EN)  32 , and a respective carrier injection line (EP)  34 . Data may be written to or read from a selected memory cell  12  by applying suitable control signals to a selected word line (WL)  28 , a selected source line (CN)  30 , a selected bit line (EN)  32 , and/or a selected carrier injection line (EP)  34 . In an exemplary embodiment, each word line (WL)  28 , source line (CN)  30 , and carrier injection line (EP)  34  may extend horizontally parallel to each other in a row direction. Each bit line (EN)  32  may extend vertically in a column direction perpendicular to each word line (WL)  28 , source line (CN)  30 , and/or carrier injection line (EP)  34 . 
     In an exemplary embodiment, one or more respective bit lines (EN)  32  may be coupled to one or more data sense amplifiers (not shown) of the data write and sense circuitry  36  to read data states of one or more memory cells  12  in the column direction. A data state may be read from one or more selected memory cells  12  by applying one or more control signals to the one or more selected memory cells  12  via a selected word line (WL)  28 , a selected source line (CN)  30 , and/or a selected carrier injection line (EP)  34  in order to generate a voltage potential and/or a current in the one or more selected memory cells  12 . The generated voltage potential and/or current may then be output to the data write and sense circuitry  36  via a corresponding bit line (EN)  32  in order to read a data state stored in each selected memory cell  12 . 
     In an exemplary embodiment, a data state may be read from a selected memory cell  12  via a selected bit line (EN)  32  coupled to the data sense amplifier of the data write and sense circuitry  36 . The source line (CN)  30  may be separately controlled via a voltage potential/current source (e.g., a voltage potential/current driver) of the memory cell selection and control circuitry  38 . In an exemplary embodiment, the data sense amplifier of the data write and sense circuitry  36  and the voltage potential/current source of the memory cell selection and control circuitry  38  may be configured on opposite sides of the memory cell array  20 . 
     In an exemplary embodiment, a data state may be written to one or more selected memory cells  12  by applying one or more control signals to the one or more selected memory cells  12  via a selected word line (WL)  28 , a selected source line (CN)  30 , a selected bit line (EN)  32 , and/or a selected carrier injection line (EP)  34 . The one or more control signals applied to the one or more selected memory cells  12  via a selected word line (WL)  28 , a selected source line (CN)  30 , a selected bit line (EN)  32 , and/or a selected carrier injection line (EP)  34  may control the first bipolar transistor  14   a  and/or the second bipolar transistor  14   b  of each selected memory cell  12  in order to write a desired data state to each selected memory cell  12 . 
     Referring to  FIG. 3 , there is shown a top view of a portion of the memory cell array  20  having a plurality of memory cells  12  in accordance with an embodiment of the present disclosure. As illustrated in the top view, the memory cell array  20  may include a plurality of memory cells  12  arranged in a matrix of rows and columns including a plurality of word lines  28  (WL), a plurality of source lines (CN)  30 , a plurality of bit lines (EN)  32 , and a plurality of carrier injection lines (EP)  34 . Each bit line (EN)  32  may extend in a first orientation along a first plane of the memory cell array  20 . Each source line (CN)  30  may extend in a second orientation along a second plane of the memory cell array  20 . Each word line (WL)  28  may extend in the second orientation along a third plane of the memory cell array  20 . Each carrier injection line (EP)  34  may extend in the second orientation along a fourth plane in the memory cell array  20 . The first plane, the second plane, the third plane, and the fourth plane may be arranged in different planes parallel to each other. 
     Referring to  FIG. 4 , there is shown a first cross-sectional view of a portion of the memory cell array  20  having a plurality of memory cells  12  in accordance with an embodiment of the present disclosure. For example,  FIG. 4  illustrates a cross-sectional view taken along line (A-A) of the top view shown in  FIG. 3 . The cross-sectional view of  FIG. 4  may illustrate a row of memory cells  12  in the memory cell array  20 . In an exemplary embodiment, each row and/or column of the memory cell array  20  may include a plurality of memory cells  12 . Each memory cell  12  may comprise an N+ source region  120 , a P− body region  122 , an N+ drain region  124  and a P+ injection region  126 . The N+ source region  120 , the P− body region  122 , the N+ region  124 , and/or the P+ injection region  126  may be disposed in sequential contiguous relationship, and may extend vertically from a plane defined by a P− substrate  130 . 
     In an exemplary embodiment, a plurality of memory cells  12  in the row direction of the memory cell array  20  may share one or more common regions. For example, two contiguous memory cells  12  in the row direction of the memory cell array  20  may share the N+ drain region  124 . Alternatively, two contiguous memory cells  12  in the row direction of the memory cell array  20  may share the P+ injection region  126 . 
     In an exemplary embodiment, the N+ source region  120  may be formed of a semiconductor material (e.g., silicon) comprising donor impurities (e.g., nitrogen, arsenic, and/or phosphorus) and coupled to the bit line (EN)  32 . In an exemplary embodiment, the bit line (EN)  32  may be formed of a metal material. In another exemplary embodiment, the bit line (EN)  32  may be formed of a polycide material (e.g., a combination of a metal material and a silicon material). In another exemplary embodiment, the bit line (EN)  32  may be formed of an N+ doped silicon layer. The bit (EN)  32  may be connected to a plurality of memory cells  12  (e.g., a column of memory cells  12 ). As shown in  FIG. 4 , the bit line (EN)  32  may be formed above the N+ source region  120 . 
     The bit line (EN)  32  may be connected to a plurality of memory cells  12  (e.g., a column of memory cells  12 ) via a plurality of bit line contacts  132 . For example, each bit line contact  132  may correspond to a memory cell  12  along a column direction of the memory cell array  20 . Each bit line contact  132  may be formed of a metal material or polysilicon material in order to couple a predetermined voltage potential from the bit line (EN)  32  to the N+ source region  120  of the memory cell  12 . For example, the bit line contact  132  may be formed of tungsten, titanium, titanium nitride, polysilicon or a combination thereof. The bit line contact  132  may have a height extending from the N+ source region  120  of the memory cell  12  to the bit line (EN)  32 . 
     In an exemplary embodiment, the P− body region  122  may be an electrically floating body region of the memory cell  12  configured to accumulate/store charges, and may be spaced apart from and capacitively coupled to the word line (WL)  28 . In an exemplary embodiment, the P− body region  122  may be formed of an undoped semiconductor material (e.g., intrinsic silicon). In another exemplary embodiment, the P− body region  122  may be formed of a semiconductor material (e.g., intrinsic silicon) comprising acceptor impurities. For example, the P− body region  122  may be formed of a silicon material doped with boron impurities. In other exemplary embodiments, the P− body region  122  may be formed of an undoped semiconductor material. 
     The word line (WL)  28  may be formed of a polycide material, a metal material, and/or a combination of a polycide material and a metal material. The word line (WL)  28  may be oriented in a column direction of the memory cell array  20  and connected to a plurality of memory cells  12 . The word line (WL)  28  may be arranged above the memory cells  12  (e.g., memory cells  12  located on a column direction of the memory cell array  20 ). In an exemplary embodiment, the word line (WL)  28  may be formed of a metal material, a polycide material (e.g., a combination of a metal material and a silicon material), and/or a combination of a metal material and a polycide material. In another exemplary embodiment, the word line (WL)  28  may be formed of a P+ doped silicon layer. As illustrated in  FIG. 4 , the word line (WL)  28  may be formed of two layers (e.g., a polycide layer and a metal layer). For example, the metal layer may be formed above the polycide layer to couple the polycide layer to a voltage/current source of the memory cell selection and control circuitry  38 . 
     The P− body region  122  and the word line (WL)  28  may be capacitively coupled via an insulating or dielectric region  128 . The insulating or dielectric region  128  may be formed of an insulating material, a dielectric material, or a combination of insulating and dielectric materials. In an exemplary embodiment, the insulating or dielectric region  128  may be arranged on one or more sides of the P− body region  122  to capacitively couple the P− body region  122  to the word line (WL)  28  in a fin configuration. In another exemplary embodiment, the insulating or dielectric region  128  may be arranged above the P− body region  122  in order to capacitively couple the word line (WL)  28  to the P− body region  122 . 
     In an exemplary embodiment, the N+ drain region  124  of the memory cell  12  may be connected to the source line (CN)  30 . In an exemplary embodiment, the N+ drain region  124  may be formed of a semiconductor material (e.g., silicon) comprising donor impurities (e.g., nitrogen, arsenic, and/or phosphorus). In an exemplary embodiment, the source line (CN)  30  may be formed of a polycide material. In another exemplary embodiment, the source (CN)  30  may be formed of a metal material. For example, the source line (CN)  30  may be formed of aluminum, copper, tungsten, titanium, titanium nitride, and/or a combination thereof. In another exemplary embodiment, the source line (CN)  30  may be formed of a doped polysilicon material. 
     The source line (CN)  30  may be connected to a plurality of memory cells  12  (e.g., a column of memory cells  12 ) via a plurality of source line contacts  136 . For example, each source line contact  136  may correspond to a memory cell  12  along a column direction of the memory cell array  20 . Each source line contact  136  may be formed of a metal layer or a polysilicon layer in order to couple a predetermined voltage potential from the source line (CN)  30  to the N+ drain region  124  of the memory cell  12 . For example, the source line contact  136  may be formed of tungsten, titanium, titanium nitride, polysilicon, and/or a combination thereof. The source line contact  136  may have a height extending from the N+ drain region  124  of the memory cell  12  to the source line (CN)  30 . 
     The P+ injection region  126  may be directly connected to the carrier injection line (EP)  34 . The P+ injection region  126  may be formed of a semiconductor material (e.g., silicon) comprising acceptor impurities. For example, the P+ injection region  126  may be formed of a silicon material doped with boron impurities. In an exemplary embodiment, the P+ injection region  126  may be configured as an input region for charges to be injected into the P− region  122  of the memory cell  12 . The charges to be injected into the P− region  122  of the memory cell  12  may be supplied by the carrier injection line (EP)  34  and input into the P− region  122  via the P+ injection region  126  and the N+ region  124 . 
     The carrier injection line (EP)  34  may be formed of a polycide material, a metal material, or a combination of a polycide material and a metal material. As illustrated in  FIG. 4 , the carrier injection line (EP)  34  may be formed of two layers (e.g., a polycide layer arranged below a metal layer). The carrier injection line (EP)  34  may include an ohmic contact to a plurality of sides portions of the P+ injection region  126  in a fin configuration. The carrier injection line (EP)  34  may extend in a column direction of the memory cell array  20 . For example, the carrier injection line (EP)  34  may extend horizontally in parallel to the word line (WL)  28  and/or the source line (CN)  30 , and may be coupled to a plurality of memory cells  12  (e.g., a row of memory cells  12 ). For example, the carrier injection line (EP)  34 , the word line (WL)  28  and/or the source line (CN)  30  may be arranged in different planes and configured to be parallel to each other. For example, the source line (CN)  30  may be arranged in a plane above a plane containing the word line (WL)  28  and a plane containing the carrier injection line (EP)  34 . 
     The word lines (WL)  28  and the carrier injection lines (EP)  34  may be separated from the N+ drain region  124  via an insulating/dielectric material  134 . In an exemplary embodiment, the insulating/dielectric material  134  may be formed from silicon nitride or silicon dioxide material in order to isolate the N+ drain region  124  from disturbances caused by voltage potentials applied on the word line (WL)  28  and/or the carrier injection line (EP)  34 . In an exemplary embodiment, the insulating/dielectric material  134  may circumferentially surround the word line (WL)  28  and/or the carrier injection line (EP)  34 . In other exemplary embodiments, the insulating/dielectric material  134  may be arranged between adjacent carrier injection lines (EP)  34 . 
     In an exemplary embodiment, the P− substrate  130  may be made of a semiconductor material (e.g., silicon) comprising acceptor impurities and may form a base of the memory cell array  20 . In alternative exemplary embodiments, a plurality of P− substrates  130  may form the base of the memory cell array  20  or a single P− substrate  130  may form the base of the memory cell array  20 . Also, the P− substrate  130  may be made in the form of a P-well substrate. 
     A plurality of barrier walls  140  may be formed on the P− substrate  130 . For example, the plurality of barrier walls  140  may be formed of an insulating material. The plurality of barrier walls  140  may include a continuous planar region configured above the P− substrate  130 . In an exemplary embodiment, the plurality of barrier walls  140  may be formed of an insulating oxide material. The plurality of barrier walls  140  may be oriented in a column direction and a row direction of the memory cell array  20 . For example, a first barrier wall  140  of the plurality of barrier walls  140  may be oriented in a column direction. A second barrier wall  140  of the plurality of barrier walls  140  may be oriented in a row direction. In an exemplary embodiment, the first barrier wall  140  oriented in the column direction and the second barrier wall  140  oriented in the row direction may be formed on the continuous planar region to form a trench region. The trench region may have a cross-sectional shape that may accommodate one or more memory cells  12  therein. For example, the trench region may have a cross-sectional shape of a square, a rectangle, a cylinder, and/or other shapes that may accommodate one or more memory cells  12 . 
     Referring to  FIG. 5 , there is shown a second cross-sectional view of a portion of the memory cell array  20  having a plurality of memory cells  12  in accordance with an embodiment of the present disclosure. For example,  FIG. 5  illustrates a cross-sectional view taken along line (B-B) of the top view shown in  FIG. 3 . The cross-sectional view of  FIG. 5  may illustrate a column of memory cells  12  in the memory cell array  20 . In an exemplary embodiment, each row and/or column of the memory cell array  20  may include a plurality of memory cells  12 . In an exemplary embodiment, the P− body regions  122  may be disposed on the continuous planar region of the barrier walls  140  and the P− substrate  130 . The P− body region  122  may be capacitively coupled to the word line (WL)  28  via the insulating or dielectric region  128 . The insulating/dielectric material  134  may be disposed on top of the word line (WL)  28 . 
     In an exemplary embodiment, the word line (WL)  28  may be configured on a plurality of sides of the P− body region  122 . For example, the word line (WL)  28  may be arranged to cover the top portion and the side portions of the P− body region  122 . As discussed above, the word line (WL)  28  may comprise a metal layer disposed on top of a polycide layer. The word line (WL)  28  may be capacitively coupled to the P− body region  122  via the insulating or dielectric region  128 . The insulating or dielectric region  128  may be disposed to cover a plurality sides of the P− body region  122 . For example, the insulating or dielectric region  128  may be disposed to cover the top portion and the side portions of the P− body region  122  to capacitively couple the word line (WL)  28  and the P− body region  122 . The P− body region  122  and the word line (WL)  28  may be capped by the insulating/dielectric material  134 . 
     Referring to  FIG. 6 , there is shown a third cross-sectional view of a portion of the memory cell array  20  having a plurality of memory cells  12  in accordance with an embodiment of the present disclosure. For example,  FIG. 6  illustrates a cross-sectional view taken along line (C-C) of the top view shown in  FIG. 3 . The cross-sectional view of  FIG. 6  may illustrate a column of memory cells  12  in the memory cell array  20 . In an exemplary embodiment, each row and/or column of the memory cell array  20  may include a plurality of memory cells  12 . In an exemplary embodiment, the P− body regions  122  may be disposed on the continuous planar region of the barrier walls  140  and the P− substrate  130 . The P− body region  1224  may be capacitively coupled to the word line (WL)  28  via the insulating or dielectric region  128 . The insulating/dielectric material  134  may be disposed on top of the word line (WL)  28 . 
     Referring to  FIG. 7 , there is shown a top view of a portion of the memory cell array  20  in accordance with an embodiment of the present disclosure. As illustrated in  FIG. 7 , the memory cell array  20  may include a plurality of memory cells  12  arranged in a matrix of rows and columns including a plurality of source lines (CN)  30  and a plurality of bit lines (EN)  32 . Each bit line (EN)  32  may extend in a first orientation along a first plane of the memory cell array  20 . Each source tine (CN)  30  may extend in a second orientation along a second plane of the memory cell array  20 . Each source line (CN)  30  may be coupled to a plurality of memory cells  12  (e.g., a column of memory cells  12 ) via a plurality of corresponding source line contacts  136 . For example, each source line contact  136  may correspond to a memory cell  12  along a column direction of the memory cell array  20 . Similarly, each bit line (EN)  32  may be connected to a plurality of memory cells  12  (e.g., a row of memory cells  12 ) via a plurality of corresponding bit line contacts  132 . For example, each bit line contact  132  may correspond to a memory cell  12  along a row direction of the memory cell array  20 . 
     Referring to  FIG. 8 , there are shown control signal voltage waveforms for performing a refresh operation on a memory cell in accordance with an embodiment of the present disclosure. The refresh operation may include control signals configured to perform one or more sub-operations. In an exemplary embodiment, the refresh operation may include a read operation, a write logic high (e.g., binary “1” data state) operation, and/or a write logic low (e.g., binary “0” data state) operation. 
     Prior to performing the refresh operation, the control signals may be configured to perform a hold operation in order to maintain a data state (e.g., a logic high (binary “1” data state) or a logic low (binary “0” data state)) stored in the memory cell  12 . In particular, the control signals may be configured to perform a hold operation in order to maximize a retention time of a data state (e.g., a logic low (binary “0” data state) and/or a logic high (binary “1” data state)) stored in the memory cell  12 . Also, the control signals for the hold operation may be configured to eliminate or reduce activities or fields (e.g., electrical fields between junctions which may lead to leakage of charges) within the memory cell  12 . 
     In an exemplary embodiment, during a hold operation, a negative voltage potential may be applied to the word line (WL)  28  (which is capacitively coupled to the P− region  122  of the memory cell  12 ), while voltage potentials applied to other regions (e.g., the N+ region  120 , the N+ region  124 , and/or the P+ region  126 ) may be maintained at approximately 0V. For example, the negative voltage potential applied to the word line (WL)  28  may be −1.5V. During the hold operation, the junction between the N+ region  124  and the P− region  122  and the junction between the N+ region  120  and the P− region  122  may be reverse biased in order to retain a data state (e.g., a logic high (binary “1” data state) or a logic low (binary “0” data state)) stored in the memory cell  12 . 
     In an exemplary embodiment, a refresh operation may include a read operation during which the control signals may be configured to read a data state (e.g., a logic low (binary “0” data state) and/or a logic high (binary “1” data state)) stored in one or more selected memory cells  12  of one or more selected rows of the memory cell array  20 . The control signals may be configured to a predetermined voltage potential to implement a read operation via the bit line (EN)  32 . In an exemplary embodiment, a voltage potential applied to the word line (WL)  28  (which is capacitively coupled to the P− region  122 ) and/or a voltage potential applied to the N+ region  124  via the source line (CN)  30  may be raised to a predetermined voltage potential in order to read a data state stored in the memory cell  12 . For example, the voltage potential applied to the word line (WL)  28  may be raised to 0V from −1.5V, while the voltage potential applied to the N+ region  124  of the memory cell  12  may be raised to 1.2V from 0V. 
     In an exemplary embodiment, during the read operation, the voltage potential applied to the word line (WL)  28  may be raised to 0V and the voltage potential applied to the source line (CN)  30  may be raised to 1.2V. Under such biasing, the junction between the P− region  122  and the N+ region  120  may become forward biased. Also, under such biasing, the junction between the P− region  122  and the N+ region  124  may be reverse biased or become weakly forward biased (e.g., above the reverse bias voltage and below forward bias threshold voltage, and/or the voltage potential at a p-diffusion region between the P− region  122  and the N+ region  124  is higher than the voltage potential at the n-diffusion region between the P− region  122  and the N+ region  124 ). A voltage potential or current may be generated when forward biasing the junction between the P− region  122  and the N+ region  120 . The voltage potential or current generated may be detected by a data sense amplifier in the data write and sense circuitry  36  via the bit line (EN)  32  coupled to the N+ region  120 . An amount of voltage potential or current generated may be representative of a data state (e.g., a logic low (binary “0” data state) and/or a logic high (binary “1” data state)) stored in the memory cell  12 . 
     In an exemplary embodiment, when a logic low (e.g., binary “0” data state) is stored in the memory cell  12 , the junction between the P− region  122  and the N+ region  120  may remain reverse biased or become weakly forward biased (e.g., above the reverse bias voltage and below forward bias threshold voltage, and/or the voltage potential at a p-diffusion region between the P− region  122  and the N+ region  120  is higher than the voltage potential at the n-diffusion region between the P− region  122  and the N+ region  120 ). A small amount of voltage potential and current or no voltage potential and current (e.g., compared to a reference voltage potential or current) may be generated when the junction between the P− region  122  and the N+ region  120  is reverse biased or weakly forward biased. A data sense amplifier in the data write and sense circuitry  36  may detect the small amount of voltage potential and current or no voltage potential and current via the bit line (EN)  32  coupled to the N+ region  120 . 
     In another exemplary embodiment, when a logic high (e.g., binary “1” data state) is stored in the memory cell  12 , the junction between the P− region  122  and the N+ region  120  may become forward biased. A larger amount of voltage potential or current (e.g., compared to a reference voltage potential or current) may be generated when the junction between the P− region  122  and the N+ region  120  is forward biased. A data sense amplifier in the data write and sense circuitry  36  may detect the larger amount of voltage potential or current via the bit line (EN)  32  coupled to the N+ region  120 . 
     In an exemplary embodiment, a refresh operation may include a write logic high (e.g., binary “1” data state) operation where the control signals may be configured to write a logic high (e.g., binary “1” data state) to one or more selected memory cells  12  of one or more selected rows of the memory cell array  20 . For example, the write logic high (e.g., binary “1” data state) operation may be performed via a corresponding bit line (EN(“1”))  32 . The write logic high (e.g., binary “1” data state) operation may be performed on one or more selected rows of the memory cell array  20 , or the entire memory cell array  20 , and a subsequent write logic low (e.g., binary “0” data state) operation may be performed on one or more selected memory cells  12 . In an exemplary embodiment, during a write logic high (e.g., binary “1” data state) operation, a voltage potential applied to the N+ region  120  via the corresponding bit line (EN(“1”))  32  of the memory cells  12  may be maintained at 0V. Also, the voltage potential applied to the word line (WL)  28  (which is capacitively coupled to the P− region  122 ) may be lowered to −1.5V. Further, a voltage potential applied to the N+ region  124  of the memory cells  12  may be lowered to 0V. Simultaneously to or subsequent to lowering a voltage potential applied to the source line (CN)  30 , a voltage potential applied to the carrier injection line (EP)  34  may be raised to 1.0V from 0V. 
     Under such biasing, the junction between the N+ region  120  and the P− region  122  may be reverse biased and the junction between the P+ region  126  and the N+ region  124  may become forward biased. A logic high (e.g., binary “1” data state) may be written to the P− region  122  (e.g., majority charge carriers injected into the P− region  122  from the P+ region  126 ) via the forward biased junction between the P+ region  126  and the N+ region  124 . As more majority charge carriers accumulate in the P− region  122 , the voltage potential at the P− region  122  may increase to approximately 0V to 0.7V above the voltage potential at N+ region  124 . At this time, the first bipolar junction transistor (BJT)  14   a  may start to switch to an “ON” state and the current generated by the first bipolar junction transistor (BJT)  14   a  may increase to approximately the same as the current generated by the second bipolar junction transistor (BJT)  14   b . The current generated by the first bipolar junction transistor (BJT)  14   a  and the current generated by the second bipolar junction transistor (BJT)  14   b  may cause the P− region  122  to reach a steady state potential after the write logic high (e.g., binary “1” data state) operation has been completed. 
     In an exemplary embodiment, a refresh operation may include a write logic low (e.g., binary “0” data state) operation during which the control signals may be configured to perform one or more write operations to one or more selected memory cells  12 . For example, the write logic low (e.g., binary “0” data state) operation may be performed via a corresponding bit line (EN(“0”))  32 . The write logic low (e.g., binary “0” data state) operation may be performed to one or more selected memory cells  12  after a write logic high (e.g., binary “1” data state) operation in order to deplete majority charge carriers that may have accumulated in the P-regions  122  of the one or more selected memory cells  12 . In an exemplary embodiment, during the write logic low (e.g., binary “0” data state) operation, a voltage potential applied to the N+ region  120  via the bit line (EN(“0”))  32  may be maintained at 0V in order to perform the write logic low (e.g., binary “0” data state) operation. Also, a voltage potential applied to the N+ region  124  via the source line (CN)  30  may be raised to 1.2V from 0V. Subsequent to or simultaneously to raising the voltage potential applied to the N+ region  124  via the source line (CN)  30 , a voltage potential applied to the word line (WL)  28  may be raised to approximately 0V from −1.5V. 
     Under such biasing, the junction between the N+ region  120  and the P− region  122  may become forward biased and the first bipolar junction transistor (BJT)  14   a  (e.g., regions  120 - 124 ) may be switched to an “ON” state. The majority charge carriers that may have accumulated in the P− region  122  during the write logic high (e.g., binary “1” data state) operation may be removed via the forward biased junction between the N+ region  120  and the P− region  122 . After removing the majority charge carriers from the P− region  122 , the memory cell  12  may represent a logic low (e.g., binary “0” data state). 
     In order to maintain a logic high (e.g., binary “1” data state) in one or more unselected memory cells  12  during the write logic low (e.g., binary “0” data state) operation, a masking operation may be performed on the one or more unselected memory cells  12 . For example, the voltage potential applied to the N+ region  120  via the bit line (EN(“1”)) of the one or more unselected memory cells  12  may be raised to 1.2V or higher (e.g., 1.5V) in order to prevent the depletion of majority charge carriers accumulated in the P− region  122 . Under such biasing, the junction between the N+ region  120  and the P− region  122  may not be forward biased and the junction between the P− region  122  and the N+ region  124  may not be forward biased in order to prevent the depletion of majority charge carriers accumulated in the P− region  122 . Thus, the logic high (e.g., binary “1” data state) may be maintained in the memory cell  12 . After completion of a write logic low (e.g., binary “0” data state) operation, the control signals may be configured to perform a hold operation. 
     At this point it should be noted that providing a direct injection semiconductor memory device in accordance with the present disclosure as described above typically involves the processing of input data and the generation of output data to some extent. This input data processing and output data generation may be implemented in hardware or software. For example, specific electronic components may be employed in a direct injection semiconductor memory device or similar or related circuitry for implementing the functions associated with providing a direct injection semiconductor memory device in accordance with the present disclosure as described above. Alternatively, one or more processors operating in accordance with instructions may implement the functions associated with providing a direct injection semiconductor memory device in accordance with the present disclosure as described above. If such is the case, it is within the scope of the present disclosure that such instructions may be stored on one or more processor readable media (e.g., a magnetic disk or other storage medium), or transmitted to one or more processors via one or more signals embodied in one or more carrier waves. 
     The present disclosure is not to be limited in scope by the specific embodiments described herein. Indeed, other various embodiments of and modifications to the present disclosure, in addition to those described herein, will be apparent to those of ordinary skill in the art from the foregoing description and accompanying drawings. Thus, such other embodiments and modifications are intended to fall within the scope of the present disclosure. Further, although the present disclosure has been described herein in the context of a particular implementation in a particular environment for a particular purpose, those of ordinary skill in the art will recognize that its usefulness is not limited thereto and that the present disclosure may be beneficially implemented in any number of environments for any number of purposes. Accordingly, the claims set forth below should be construed in view of the full breadth and spirit of the present disclosure as described herein.