Patent Publication Number: US-2021193785-A1

Title: Organic light emitting display apparatus

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application claims the benefit of the Korean Patent Application No. 10-2019-0173675 filed on Dec. 24, 2019, which is hereby incorporated by reference as if fully set forth herein. 
     TECHNICAL FIELD 
     The present disclosure relates to an organic light emitting display apparatus where a camera is mounted in a forward direction with respect to an organic light emitting display panel. 
     DISCUSSION OF THE RELATED ART 
     As various kinds of applications are provided in electronic devices such as smartphones, users need display apparatuses including a wider display unit. 
     Moreover, in electronic devices such as smartphones, a camera is mounted in a forward direction with respect to a display panel so that a user photographs its own form while looking at its own form. 
     In this case, in order to maximally enlarge a width of a display area displaying an image in a display apparatus, a camera may be provided in the display area. 
     However, in order to prevent a luminance deviation caused by the degradation in each driving transistor, four or more transistors are included in each pixel of an organic light emitting display panel which is a type of display panel. Therefore, even when a portion, corresponding to a camera, of the organic light emitting display panel is implemented as a transparent panel, a transmittance of light is reduced by transistors included in the transparent panel. 
     Due to this, the amount of light transferred to a camera is reduced, causing the degradation in quality of an image captured by the camera. 
     SUMMARY 
     Accordingly, embodiments of the present disclosure are directed to an organic light emitting display apparatus that substantially obviates one or more problems due to limitations and disadvantages of the related art. 
     An aspect of the present disclosure is to provide an organic light emitting display apparatus in which a first pixel driving circuit provided in a transparent area, corresponding to a position of a camera, of a display area includes two transistors, and a second pixel driving circuit provided in an opaque area, except the transparent area, of the display area includes at least three transistors. 
     Additional features and aspects will be set forth in the description that follows, and in part will be apparent from the description, or may be learned by practice of the inventive concepts provided herein. Other features and aspects of the inventive concepts may be realized and attained by the structure particularly pointed out in the written description, or derivable therefrom, and the claims hereof as well as the appended drawings. 
     To achieve these and other aspects of the inventive concepts, as embodied and broadly described herein, an organic light emitting display apparatus comprises an organic light emitting display panel including a display area, including a transparent area and an opaque area, and a non-display area, a gate driver sequentially supplying a gate pulse to a plurality of gate lines included in the organic light emitting display panel, and an initialization unit transferring gate pulses and/or initialization control signals, output from the gate driver, to a plurality of transparent area gate lines. A camera photographing a region in a forward direction with respect to the organic light emitting display panel is provided in the transparent area of a rear surface of the organic light emitting display panel. A first pixel driving circuit provided in the transparent area includes two transistors, and a second pixel driving circuit provided in the opaque area includes at least three transistors. 
     In another aspect, an organic light emitting display apparatus comprises an organic light emitting display panel including a display area, including a transparent area and an opaque area, and a non-display area, a digital gate driver supplying digital gate pulses to a plurality of transparent area gate lines provided in the transparent area, a digital data driver supplying digital data voltages to a plurality of transparent area data lines provided in the transparent area, a gate driver sequentially supplying a gate pulse to a plurality of opaque area gate lines provided in the opaque area, and a data driver supplying data voltages to a plurality of opaque area data lines provided in the opaque area. 
     It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the inventive concepts as claimed. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this application, illustrate embodiments of the disclosure and together with the description serve to explain principles of the disclosure. In the drawings: 
         FIG. 1  is an exemplary diagram illustrating an external configuration of an electronic device to which an organic light emitting display apparatus according to an embodiment of the present disclosure is applied; 
         FIG. 2  is an exemplary diagram illustrating an internal configuration of an organic light emitting display apparatus according to an embodiment of the present disclosure; 
         FIG. 3  is an exemplary diagram illustrating a configuration of a controller applied to an organic light emitting display apparatus according to an embodiment of the present disclosure; 
         FIG. 4  is an exemplary diagram illustrating a configuration of a gate driver applied to an organic light emitting display apparatus according to an embodiment of the present disclosure; 
         FIG. 5  is an exemplary diagram illustrating a first pixel and a second pixel each included in an organic light emitting display apparatus according to an embodiment of the present disclosure; 
         FIG. 6  is an exemplary diagram illustrating a structure of a first pixel applied to an organic light emitting display apparatus according to an embodiment of the present disclosure; 
         FIG. 7  is a cross-sectional view illustrating a structure of a first pixel applied to an organic light emitting display apparatus according to an embodiment of the present disclosure; 
         FIG. 8  is an exemplary diagram illustrating a structure of a second pixel applied to an organic light emitting display apparatus according to an embodiment of the present disclosure; 
         FIG. 9  is an exemplary diagram illustrating a gate driver, an initialization unit, and a transparent area each applied to an organic light emitting display apparatus according to an embodiment of the present disclosure; 
         FIG. 10  is an exemplary diagram illustrating a structure where a first pixel applied to the present disclosure is connected to a data line and a reference voltage supply line; 
         FIG. 11  is an exemplary diagram illustrating a structure of an initialization unit applied to the present disclosure; 
         FIG. 12  is an exemplary diagram showing waveforms of signals applied to an initialization unit applied to the present disclosure; 
         FIG. 13  is an exemplary diagram showing waveforms of signals applied to an organic light emitting display apparatus according to an embodiment of the present disclosure; 
         FIGS. 14 to 16  are exemplary diagrams illustrating a driving method of an organic light emitting display apparatus according to an embodiment of the present disclosure; 
         FIG. 17  is another exemplary diagram illustrating a first pixel and a second pixel each included in an organic light emitting display apparatus according to an embodiment of the present disclosure; 
         FIG. 18  is an exemplary diagram illustrating a gate driver, an initialization unit, and a transparent area each applied to the organic light emitting display apparatus illustrated in  FIG. 17 ; 
         FIG. 19  is an exemplary diagram illustrating a structure of a second driving voltage supply line for transferring a second driving voltage to a second driving voltage line included in an organic light emitting display apparatus according to an embodiment of the present disclosure; 
         FIG. 20  is another exemplary diagram illustrating an internal configuration of an organic light emitting display apparatus according to an embodiment of the present disclosure; 
         FIG. 21  is another exemplary diagram illustrating a structure of a first pixel applied to an organic light emitting display apparatus according to an embodiment of the present disclosure; 
         FIG. 22  is an exemplary diagram showing structures of digital gate signals applied to the organic light emitting display apparatus illustrated in  FIG. 20 ; 
         FIG. 23  is an exemplary diagram illustrating a first pixel and a second pixel each included in an organic light emitting display apparatus according to an embodiment of the present disclosure; 
         FIG. 24  is another exemplary diagram illustrating a first pixel and a second pixel each included in an organic light emitting display apparatus according to an embodiment of the present disclosure; and 
         FIG. 25  is an exemplary diagram illustrating a result obtained by comparing the compensation performance of a related art pixel driving circuit with the compensation performance of a first pixel driving circuit applied to an organic light emitting display apparatus according to an embodiment of the present disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     Reference will now be made in detail to the exemplary embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts. 
     Advantages and features of the present disclosure, and implementation methods thereof will be clarified through following embodiments described with reference to the accompanying drawings. The present disclosure may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art. Further, the present disclosure is only defined by scopes of claims. 
     A shape, a size, a ratio, an angle, and a number disclosed in the drawings for describing embodiments of the present disclosure are merely an example, and thus, the present disclosure is not limited to the illustrated details. Like reference numerals refer to like elements throughout. In the following description, when the detailed description of the relevant known function or configuration is determined to unnecessarily obscure the important point of the present disclosure, the detailed description will be omitted. In a case where ‘comprise’, ‘have’, and ‘include’ described in the present specification are used, another part may be added unless ‘only˜’ is used. The terms of a singular form may include plural forms unless referred to the contrary. 
     In construing an element, the element is construed as including an error range although there is no explicit description. 
     In describing a position relationship, for example, when a position relation between two parts is described as ‘on˜’, ‘over˜’, ‘under˜’, and ‘next˜’, one or more other parts may be disposed between the two parts unless ‘just’ or ‘direct’ is used. 
     In describing a time relationship, for example, when the temporal order is described as ‘after˜’, ‘subsequent˜’, ‘next˜’, and ‘before˜’, a case which is not continuous may be included unless ‘just’ or ‘direct’ is used. 
     It will be understood that, although the terms “first”, “second”, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. 
     In describing the elements of the present disclosure, terms such as first, second, A, B, (a), (b), etc., may be used. Such terms are used for merely discriminating the corresponding elements from other elements and the corresponding elements are not limited in their essence, sequence, or precedence by the terms. It will be understood that when an element or layer is referred to as being “on” or “connected to” another element or layer, it can be directly on or directly connected to the other element or layer, or intervening elements or layers may be present. Also, it should be understood that when one element is disposed on or under another element, this may denote a case where the elements are disposed to directly contact each other, but may denote that the elements are disposed without directly contacting each other. 
     The term “at least one” should be understood as including any and all combinations of one or more of the associated listed elements. For example, the meaning of “at least one of a first element, a second element, and a third element” denotes the combination of all elements proposed from two or more of the first element, the second element, and the third element as well as the first element, the second element, or the third element. 
     Features of various embodiments of the present disclosure may be partially or overall coupled to or combined with each other, and may be variously inter-operated with each other and driven technically as those skilled in the art can sufficiently understand. The embodiments of the present disclosure may be carried out independently from each other, or may be carried out together in co-dependent relationship. 
     Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. 
       FIG. 1  is an exemplary diagram illustrating an external configuration of an electronic device to which an organic light emitting display apparatus according to an embodiment of the present disclosure is applied. 
     The organic light emitting display apparatus according to an embodiment of the present disclosure may configure an electronic device. The electronic device may include, for example, a smartphone, a tablet personal computer (PC), a television (TV), a monitor, etc. In  FIG. 1 , a smartphone is illustrated as an example of the electronic device. In the following description, an example where the electronic device is a smartphone will be described. 
       FIG. 2  is an exemplary diagram illustrating an internal configuration of an organic light emitting display apparatus according to an embodiment of the present disclosure,  FIG. 3  is an exemplary diagram illustrating a configuration of a controller applied to an organic light emitting display apparatus according to an embodiment of the present disclosure, and  FIG. 4  is an exemplary diagram illustrating a configuration of a gate driver applied to an organic light emitting display apparatus according to an embodiment of the present disclosure. 
     The electronic device, as illustrated in  FIGS. 1 and 2 , may include an organic light emitting display apparatus  10  according to the present disclosure and an external case  20  which supports the organic light emitting display apparatus  10 . 
     The organic light emitting display apparatus according to an embodiment of the present disclosure, as illustrated in  FIGS. 1 to 4 , may include a display area AA displaying an image and a non-display area NAA provided outside the display area AA. The display area AA may include an organic light emitting display panel  100  including a transparent area AA 1  which transmits light and an opaque area AA 2  which does not transmit light, a camera  600  which is provided in the transparent area AA 1  in a rea surface of the organic light emitting display panel  100  and photographs a region in a forward direction with respect to the organic light emitting display panel  100 , a gate driver  200  which sequentially supplies a gate pulse to a plurality of gate lines GL 1  to TGLg included in the organic light emitting display panel  100 , a data driver  300  which supplies data voltages to a plurality of data lines DL 1  to DLd included in the organic light emitting display panel  100 , an initialization unit  500  which transfers gate pulses, output from the gate driver  200 , to a plurality of transparent area gate lines TGLg−4 to TGLg included in the transparent area AA 1  among the plurality of gate lines GL 1  to TGLg or transfers, to the transparent area gate lines TGLg−4 to TGLg, initialization control signals for initializing first pixel driving circuits provided in the transparent area AA 1 , and a controller  400  which controls driving of the gate driver  200 , the initialization unit  500 , and the data driver  300 . The first pixel driving circuit provided in the transparent area AA 1  and the second pixel driving circuit provided in the opaque area AA 2  may have different structures. Particularly, the number of transistors included in the first pixel driving circuit may be two, and the number of transistors included in the second pixel driving circuit may be at least three. 
     The camera  600  may be provided between the external case  20  and the organic light emitting display panel  100  and may be driven based on control by the controller  400  or control by an external system  800  which controls driving of the electronic device. The camera  600  may be provided in the rear surface of the organic light emitting display panel  100  and may perform a function of photographing a region in a forward direction with respect to the organic light emitting display panel  100 . Here, the forward direction with respect to the organic light emitting display panel  100  may denote a direction in which the organic light emitting display panel  100  displays an image. 
     The controller  400 , as illustrated in  FIG. 3 , may include a data aligner  430  which realigns input video data Ri, Gi, and Bi transferred from the external system  800  by using a timing synchronization signal TSS transferred from the external system  800  to generate image data Data and supplies the image data Data to the data driver  300 , a control signal generator  420  which generates a gate control signal GCS and a data control signal DCS by using the timing synchronization signal TSS, an input unit  410  which receives the timing synchronization signal TSS and the input video data Ri, Gi, and Bi from the external system  800 , transfers the input video data Ri, Gi, and Bi to the data aligner  430 , and transfers the timing synchronization signal TSS to the control signal generator  420 , and an output unit  440  which outputs the image data Data generated by the data aligner  430  to the data driver  300 , transfers the data control signal DCS generated by the control signal generator  420  to the data driver  300 , and transfers the gate control signal GCS generated by the control signal generator  420  to the gate driver  200 . The control signal generator  420  may generate a first turn-on control signal ALL_L for controlling the initialization unit  500  by using the timing synchronization signal TSS. However, the present embodiment is not limited thereto, and in other embodiments, the first turn-on control signal ALL_L may be generated by the gate driver  200 . 
     The gate driver  200  may be configured as an integrated circuit (IC), and then, may be mounted in the non-display area NAA or may be directly embedded into the non-display area NAA. 
     The gate driver  200 , as illustrated in  FIG. 4 , may include first to g th  stages ST 1  to STg. 
     Each of the first to g th  stages ST 1  to STg may generate a gate signal VG and an emission signal EM, output the gate signal to a gate line GL, and output the emission signal EM to an emission line. 
     For example, the first stage ST 1  driven by a gate start signal transferred from the controller  400  may generate a first gate signal VG 1  by using at least one gate clock transferred from the controller  400  and may output the first gate signal VG 1  to a first gate line GL 1 . Also, the first stage ST 1  may be driven by an emission start signal transferred from the controller  400  to generate a first emission signal EM 1  by using at least one emission clock transferred from the controller  400  and may output the first emission signal EM 1  to a first emission line which is arranged in parallel with the first gate line GL 1 . 
     In this case, the first gate signal VG 1  and the first emission signal EM 1  may drive the second stage ST 2 , and thus, the second stage ST 2  may generate a second gate signal VG 2  and a second emission signal EM 2  and may respectively output the second gate signal VG 2  and the second emission signal EM 2  to a second gate line GL 2  and a second emission line which is arranged in parallel with the second gate line GL 2 . 
     Moreover, the g−1 th  gate signal VGg−1 and the g−1 th  emission signal EMg−1 each output from the g−1th stage STg−1 may drive the g th  stage STg. Therefore, the g th  stage STg may generate a g th  gate signal VGg and a g th  emission signal EMg and may respectively output the g th  gate signal VGg and the g th  emission signal EMg to a g th  gate line GLg and a g th  emission line which is arranged in parallel with the g th  gate line GLg. 
     In this case, in the present disclosure, an order in which the first to g th  gate signals VG 1  to VGg and the first to g th  emission signals EM 1  to EMg are output is not limited to the above-described order. Therefore, in the present disclosure, an order in which the first to g th  gate signals VG 1  to VGg and the first to g th  emission signals EM 1  to EMg are output may be variously changed. 
     Moreover, a structure of each of the stages ST 1  to STg for outputting the first to g th  gate signals VG 1  to VGg and the first to g th  emission signals EM 1  to EMg may be variously designed by using stages for generating gate signals and emission signals, which are being used currently and generally. That is, the structure of each of the stages ST 1  to STg may be implemented as various types by using structures of stages which are being used currently. 
     To provide an additional description, the feature of the present disclosure may be a feature where a structure of each of the stages ST 1  to STg for generating the gate signals VG 1  to VGg and the emission signals EM 1  to EMg on the basis of the above-described order is implemented as various types by those skilled in the art, instead of a structure of each of the stages ST 1  to STg for generating the gate signals VG 1  to VGg and the emission signals EM 1  to EMg. 
     The data driver  300  may be equipped in a chip-on film attached on the organic light emitting display panel  100 . The chip-on film may be connected to a main board including the controller  400 . However, the data driver  300  may be directly mounted on the organic light emitting display panel  100  and may be electrically connected to the main board. The data driver  300  may convert the image data Data, transferred from the controller  400 , into data voltages and may output the data voltages to the data lines DL 1  to DLd. 
     The external system  800  may perform a function of driving the controller  400  and the electronic device. That is, when the electronic device is a smartphone, the external system  800  may receive various voice information, video information, and letter information over a wireless communication network and may transfer the video information to the controller  400 . In the following description, the video information transferred from the external system  800  to the controller  400  may be referred to as input video data. Also, the external system  800  may execute an application for controlling the camera  600 . The application may be downloaded to the external system  800  as an application (App) type, and then, may be executed by the external system  800 . 
     The organic light emitting display panel  100  may include a plurality of pixels  110  which each include an organic light emitting diode (OLED) and a pixel driving circuit for driving the OLED. Also, the organic light emitting display panel  100  may include a plurality of signal lines which define a pixel area, where the pixels  110  are provided, and supply a driving signal to the pixel driving circuit. The signal lines may include various kinds of lines, in addition to the gate lines GL 1  to TGLg and the data lines DL 1  to DLd. 
     In the following description, gate lines provided in the transparent area AA 1  among the gate lines GL 1  to TGLg may be referred to as transparent area gate lines, and gate lines provided in the opaque area AA 2  among the gate lines GL 1  to GLg may be referred to as opaque area gate lines. The transparent area gate lines may be referred to by reference numeral TGL, and the opaque area gate lines may be referred to by reference numeral GL. That is, a transparent area gate line among gate lines referred to by reference numeral GL may be referred to by reference numeral TGL. 
     For example, in the organic light emitting display apparatus illustrated in  FIG. 2 , first to g−5 th  gate lines GL 1  to GLg−5 may be referred to as opaque area gate lines, and g−4 th  to g th  gate lines TGLg−4 to TGLg may be referred to as transparent area gate lines. 
     Moreover, pixels provided in the transparent area among the pixels  110  may be referred to as first pixels, and pixels provided in the opaque area among the pixels  110  may be referred to as second pixels. 
     In this case, each of the first pixels may include a first pixel driving circuit and a first OLED, and each of the second pixels may include a second pixel driving circuit and a second OLED. 
     The organic light emitting display panel  100 , as illustrated in  FIGS. 1 and 2 , may include the display area AA displaying an image and the non-display area NAA provided outside the display area AA. 
     The display area AA may include a transparent area AA 1  which transmits light and an opaque area AA 2  which does not transmit light. The camera  600 , which photographs a region in the forward direction with respect to the organic light emitting display panel  100 , may be disposed at a portion, corresponding to the transparent area AA 1 , of the rear surface of the organic light emitting display panel  100 . 
     The transparent area AA 1  may be implemented to be transparent so that external light travels to the inside of the camera  600 . 
     The opaque area AA 2  may not need to transmit external light, and thus, may be implemented to be opaque. However, the opaque area AA 2  may also be implemented to be transparent. 
     The non-display area NAA may be provided outside the display area AA. 
     A width of the non-display area NAA may be formed to be very small, and then, when the most of the non-display area NAA is covered by the external case  20 , only the display area AA may be exposed at a front surface of the electronic device as illustrated in  FIG. 1 . 
     Each of the first pixels provided in the transparent area AA 1  may include the first pixel driving circuit including three transistors and a first OLED connected to the first pixel driving circuit, for performing internal compensation. 
     Each of the second pixels provided in the opaque area AA 2  may include the second pixel driving circuit including at least four transistors and a second OLED connected to the second pixel driving circuit, for performing internal compensation. 
     A detailed configuration of each of the first and second pixels will be described below in detail with reference to  FIGS. 5 to 8 . 
       FIG. 5  is an exemplary diagram illustrating a first pixel and a second pixel each included in an organic light emitting display apparatus according to an embodiment of the present disclosure,  FIG. 6  is an exemplary diagram illustrating a structure of a first pixel applied to an organic light emitting display apparatus according to an embodiment of the present disclosure,  FIG. 7  is a cross-sectional view illustrating a structure of a first pixel applied to an organic light emitting display apparatus according to an embodiment of the present disclosure, and  FIG. 8  is an exemplary diagram illustrating a structure of a second pixel applied to an organic light emitting display apparatus according to an embodiment of the present disclosure. 
     The display area AA of the organic light emitting display panel  100  may include a plurality of pixels  110  which includes an organic light emitting diode OLED and a pixel driving circuit PDC for driving the organic light emitting diode OLED. As described above, pixels provided in the transparent area AA 1  among the pixels  110  may be referred to as first pixels  110   a , and pixels provided in the opaque area AA 2  among the pixels  110  may be referred to as second pixels  110   b . In this case, each of the first pixels  110   a  may include a first pixel driving circuit PDC 1  and a first organic light emitting diode OLED 1  as illustrated in  FIG. 6 , and each of the second pixels  110   b  may include a second pixel driving circuit PDC 2  and a second organic light emitting diode OLED 2  as illustrated in  FIG. 8 . 
     Moreover, the organic light emitting display panel  100  may include a plurality of signal lines which define a plurality of pixel areas, where the pixels  110  are respectively provided, and supply a driving signal to the pixel driving circuit PDC. 
     Hereinafter, the signal lines applied to the first pixel  110   a  and the second pixel  110   b  will be described first, a structure of the first pixel  110   a  will be described with reference to  FIGS. 6 and 7 , and a structure of the second pixel  110   b  will be described with reference to  FIG. 8 . 
     First, the signal lines may include a gate line GL, a data line DL, a sensing pulse line SPL, a sensing line SL, a first driving voltage line PLA, a second driving voltage line PLB, an emission line EL, a reference voltage supply line, and a transfer line TL through which a reference voltage or a data voltage is supplied. 
     A plurality of gate lines GL, as illustrated in  FIG. 2 , may be arranged at certain intervals in a second direction (for example, a widthwise direction) of the organic light emitting display panel  100 . A gate line included in the first pixel  110   a  illustrated in  FIG. 6  may be referred to as a transparent area gate line TGL. 
     A plurality of sensing pulse lines SPL, as illustrated in  FIG. 8 , may be arranged at certain intervals in parallel with the gate lines GL. 
     A plurality of data lines DL, as illustrated in  FIGS. 2, 6, and 8 , may be arranged at certain intervals in a first direction (for example, a lengthwise direction) of the organic light emitting display panel  100  to intersect with the gate lines GL and the sensing pulse lines SPL. 
     A plurality of sensing lines SL, as illustrated in  FIG. 8 , may be arranged at certain intervals in parallel with the data lines DL. 
     The first driving voltage line PLA, as illustrated in  FIGS. 6 and 8 , may be provided apart from the data line DL and the sensing line SL by a certain interval in parallel with the data line DL and the sensing line SL. The first driving voltage line PLA may be connected to the gate driver  200  or a power supply  700  illustrated in  FIG. 2  and may transfer a first driving voltage ELVDD, supplied from the power supply  700 , to each pixel  110 . 
     The second driving voltage line PLB, as illustrated in  FIGS. 6 and 8 , may transfer a second driving voltage ELVSS, supplied from the power supply  700 , to each of the pixels  110 . 
     The emission lines EL, as illustrated in  FIG. 8 , may be arranged in parallel with the gate lines GL. The emission lines EL may supply an emission signal EM, transferred from the gate driver  200 , to the second pixels  110   b.    
     A reference voltage, which is to be supplied to each of the first pixels  110   a , may be supplied to the reference voltage supply line. The reference voltage may be supplied from the power supply  700 . 
     The transfer line TL, as illustrated in  FIG. 6 , may be connected to the first pixel  110   a . The transfer line TL may supply the first pixel  110   a  with the reference voltage supplied through the reference voltage supply line or a data voltage supplied through the data line DL. 
     A plurality of first pixels  110   a  may be provided in the transparent area AA 1 , and each of the first pixels  110   a , as illustrated in  FIG. 6 , may include a first pixel driving circuit PDC 1  and a first organic light emitting diode OLED 1 . 
     The first pixel driving circuit PDC 1  may include a capacitor CST including a first terminal connected to the transfer line TL through which the reference voltage or a data voltage Vdata is transferred, a driving transistor DR including a first terminal connected to the first driving voltage line PLA and a gate connected to a second terminal of the capacitor CST, and a first transistor SW 1  including a first terminal connected to the gate of the driving transistor DR, a second terminal connected to a second terminal of the driving transistor DR, and a gate connected to the transparent area gate line TGL. 
     A detailed driving method of the first pixel driving circuit PDC 1  will be described below in detail with reference to  FIGS. 9 to 16 . 
     A cross-sectional structure of the first pixel  110   a  including the first pixel driving circuit PDC 1  is illustrated in  FIG. 7 .  FIG. 7  illustrates a cross-sectional surface taken along line A-A′ illustrated in the transparent area of  FIG. 5 . In the cross-sectional structure of the first pixel  110   a  illustrated in  FIG. 7 , each of layers other than below-described portions may include an organic material, an inorganic material, or a mixture layer thereof and may perform a function of an insulator or a planarization layer. 
     A plurality of metal lines included in the first pixel  110   a  may be formed of transparent metal such as indium tin oxide (ITO). 
     The first organic light emitting diode OLED 1  may include an anode  20 , a light emitting layer  30 , and a cathode  40 . The cathode  40  may be formed of transparent metal. The anode  20  may be formed of a double layer including transparent metal  21  and silver (Ag)  22 , but the silver  22  may be omitted for enhancing a transmittance. 
     The capacitor CST may include metal included in each of the data line DL and the first driving voltage line PLA and metal included in each of the first transistor SW 1 , the second transistor SW 2 , and a gate of the driving transistor DR. 
     Various organic materials (for example, a material included in a bank, a material included in an insulation layer, and a material included in a planarization layer) included in the first pixel  110   a  may be formed of a transparent material. 
     As described above, since the number of transistors included in the first pixel driving circuit PDC 1  is three, a region X, where the first pixel driving circuit PDC 1  is disposed, of the first pixel  110   a  may decrease, and thus, a size of a transparent portion of the first pixel  110   a  may relatively increase. 
     Moreover, the number of transistors included in the first pixel driving circuit PDC 1  may be small and the region X with the first pixel driving circuit PDC 1  disposed therein may include a transparent material, and thus, a transmittance of the region X with the first pixel driving circuit PDC 1  disposed therein may more increase than that of a region with the second pixel driving circuit PDC 2  disposed therein. 
     Therefore, comparing with the second pixel  110   b , a transmittance of the first pixel  110   a  may increase, and thus, the amount of light transferred to the camera  600  through the first pixel  110   a  may increase. 
     In this case, a density (PPI) of each of the first pixels  110   a  included in the transparent area AA 1  may be set to be equal to a density (PPI) of each of the second pixels  110   b  included in the opaque area AA 2 . 
     Finally, the second pixels  110   b  may be provided in the opaque area AA 2 , and as illustrated in  FIG. 8 , each of the second pixels  110   b  may include a second pixel driving circuit PDC 2  and a second organic light emitting diode OLED 2 . 
     The second pixel driving circuit PDC 2  may include at least four transistors, for performing internal compensation. That is, the number (four or more) of transistors included in the second pixel driving circuit PDC 2  may be set to be greater than the number (three) of transistors included in the first pixel driving circuit PDC 1 . 
     For example, as illustrated in  FIG. 8 , the second pixel driving circuit PDC 2  may include a driving transistor Tdr which controls the amount of current flowing in the second organic light emitting diode OLED 2 , a switching transistor Tsw 1  which includes a first terminal connected to the data line DL, a second terminal connected to a gate of the driving transistor Tdr, and a gate connected to the gate line GL, an emission transistor Tsw 3  which includes a first terminal connected to the first driving voltage line PLA, a second terminal connected to the first terminal of the driving transistor Tdr, and a gate connected to the emission line EL, for controlling a current flowing to the driving transistor Tdr, a storage capacitor STC which is connected to the second terminal of the emission transistor Tsw 3  and the gate of the driving transistor Tdr, and a sensing transistor Tsw 2  which includes a first terminal connected to the second terminal of the driving transistor Tdr, a second terminal connected to a sensing line SL, and a gate connected to a sensing pulse line SPL. 
     A current supplied to the second organic light emitting diode OLED 2  through the second pixel driving circuit PDC 2  may be proportional to the square ((Vgs−Vth) 2 ) of a difference voltage between a gate-source voltage Vgs of the driving transistor Tdr and a threshold voltage Vth of the driving transistor Tdr. 
     In this case, the second pixel driving circuit PDC 2  may use signals having various forms so as to remove the threshold voltage Vth from the square ((Vgs−Vth) 2 ) of the difference voltage. 
     When the threshold voltage Vth is removed from the square ((Vgs−Vth) 2 ) of the difference voltage, a current supplied to the second organic light emitting diode OLED 2  may be maintained to be constant regardless of the threshold voltage Vth. 
     That is, even when the threshold voltage of the driving transistor Tdr included in the second pixel  110   b  is shifted because the organic light emitting display panel  100  is used for a long time, the second pixel driving circuit PDC 2  may remove the threshold voltage Vth from the square ((Vgs−Vth) 2 ) of the difference voltage, a current corresponding to a data voltage Vdata may flow to the second organic light emitting diode OLED 2 . 
     To provide an additional description, the second pixel driving circuit PDC 2  may perform a function of allowing a current corresponding to the data voltage Vdata to flow to the second organic light emitting diode OLED 2 , regardless of a shift of the threshold voltage of the driving transistor Tdr, and such a function may be referred to as internal compensation. The second pixel driving circuit PDC 2  may be configured as various types including at least four transistors so as to perform internal compensation, and a driving method of the second pixel driving circuit PDC 2  may be variously modified. 
       FIG. 9  is an exemplary diagram illustrating a gate driver, an initialization unit, and a transparent area each applied to an organic light emitting display apparatus according to an embodiment of the present disclosure,  FIG. 10  is an exemplary diagram illustrating a structure where a first pixel applied to the present disclosure is connected to a data line and a reference voltage supply line,  FIG. 11  is an exemplary diagram illustrating a structure of an initialization unit applied to the present disclosure, and  FIG. 12  is an exemplary diagram showing waveforms of signals applied to an initialization unit applied to the present disclosure. In  FIG. 9 , gate pulses supplied to the first pixel  110   a  and the second pixel  110   b  are illustrated. 
     As described above, the organic light emitting display apparatus according to an embodiment of the present disclosure may include the organic light emitting display panel  100  including the first pixels  110   a  and the second pixels  110   b , the gate driver  200 , the data driver  300 , the initialization unit  500 , and the controller  400 . 
     The transparent area AA 1 , as illustrated in  FIGS. 2 and 5 , may be formed from one end of the display area AA to the other end of the display area AA. For example, as illustrated in  FIGS. 2 and 5 , the transparent area AA 1  may be provided between a first non-display area NAA 1  including the gate driver  200  and a second non-display area NAA 2  facing the first non-display area NAA 1  in the non-display area NAA. 
     In this case, the initialization unit  500  may be provided in the first non-display area NAA 1  along with the gate driver  200 , or may be included in the gate driver  200 . When the initialization unit  500  is separated from the gate driver  200 , the initialization unit  500  may be provided between the gate driver  200  and the transparent area AA 1 . 
     The initialization unit  500 , as illustrated in  FIGS. 9 to 11 , may transfer gate pulses SCANg−3 to SCANg, output from the gate driver  200 , to transparent area gate lines TGL provided in the transparent area AA 1  among the plurality of gate lines or may transfer, to the transparent area gate lines TGL, initialization control signals VGL for initializing the first pixel driving circuits provided in the transparent area AA 1 . 
     To this end, the initialization unit  500  may include a plurality of first initialization drivers  510  connected to the transparent area gate lines TGL. 
     Each of the first initialization drivers  510 , as illustrated in  FIG. 11 , may include a first initialization transistor Tini 1 , which includes a first terminal connected to an initialization control signal supply line ISL, a second terminal connected to the transparent area gate line TGL, and a gate connected to a first turn-on control line TCL 1 , and a second initialization transistor Tini 2  which includes a first terminal connected to a transparent area gate output line TGOL of the gate driver  200 , a second terminal connected to the transparent area gate line TGL, and a gate connected to a second turn-on control line TCL 2 . 
     In this case, as illustrated in  FIG. 12 , a phase of a first turn-on control signal ALL_L supplied through the first turn-on control line TCL 1  may be set to be opposite to a phase of a second turn-on control signal EN_SN supplied through the second turn-on control line TCL 2 . 
     The first turn-on control signal ALL_L and the second turn-on control signal EN_SN may be generated by the controller  400 , or may be generated by the gate driver  200  on the basis of the gate control signal GCS. 
     The initialization control signal VGL supplied through the initialization control signal supply line ISL may have a voltage for turning on the first transistor SW 1 . 
     For example, as illustrated in  FIG. 10 , when the first transistor SW 1  is formed as a P-type transistor, the initialization control signal VGL may be a low voltage. 
     The initialization control signal VGL may be generated by the controller  400 , or may be generated by the gate driver  200  on the basis of the gate control signal GCS. 
     Referring to  FIGS. 11 and 12 , when the first turn-on control signal ALL_L is logic low and the second turn-on control signal EN_SN is logic high, the first initialization driver  510  may output the initialization control signal VGL (i.e., a low voltage), and when the first turn-on control signal ALL_L is logic high and the second turn-on control signal EN_SN is logic low, the first initialization driver  510  may output the gate signal VG. 
     For example, when the first turn-on control signal ALL_L is logic low and the second turn-on control signal EN_SN is logic high, the first initialization transistor Tini 1  may be turned on and the second initialization transistor Tini 2  may be turned off. Therefore, the initialization control signal VGL (i.e., a low voltage) may be transferred to the transparent area gate line TGL through the first initialization transistor Tini 1 . 
     Moreover, when the first turn-on control signal ALL_L is logic high and the second turn-on control signal EN_SN is logic low, the first initialization transistor Tini 1  may be turned off and the second initialization transistor Tini 2  may be turned on. Therefore, the gate signal GL may be transferred to the transparent area gate line TGL through the second initialization transistor Tini 2 . 
     The gate signal VG may include a signal (hereinafter simply referred to as a gate pulse SCAN) for turning on the first transistor SW 1  and a signal (hereinafter simply referred to as a gate-off signal Voff) for turning off the first transistor SW 1 . 
     To provide an additional description, as illustrated in  FIGS. 9 and 12 , in one frame period where the organic light emitting display panel displays one image, the initialization control signals VGL having a low voltage may be simultaneously transferred to the transparent area gate lines TGL and the first pixels  110   a  provided in the transparent area AA 1  may be initialized by the initialization control signals VGL, in a period where one gate pulse is output. 
     As described above, the gate signal VG or the initialization control signal VGL may be supplied to the transparent area gate line TGL. The gate signal VG may include the gate pulse SCAN and the gate-off signal Voff. 
     A generic name for the gate signal VG or the initialization control signal VGL supplied to the transparent area gate line TGL may be a transparent area gate signal TGS. The transparent area gate signal TGS, as illustrated in  FIG. 9 , may include the initialization control signal VGL, the gate-off signal Voff, and the gate pulse SCAN. 
     A first terminal of the capacitor CST included in the first pixel driving circuit PDC 1 , as illustrated in  FIGS. 9 and 10 , may be connected to a reference voltage control transistor Trc and a data voltage control transistor Tdc. 
     A first terminal of the reference voltage control transistor Trc may be connected to a reference voltage supply line RVL through which a reference voltage VREF is supplied, a second terminal thereof may be connected to the first terminal of the capacitor CST, and a gate thereof may be connected to an emission line EL through which an emission signal EM is supplied. 
     A first terminal of the data voltage control transistor Tdc may be connected to the first terminal of the capacitor CST, a second terminal thereof may be connected to the data driver  300 , and a gate thereof may be connected to a data control line DCL through which a data control signal DATA_EN is supplied. 
     A data extension line DEL provided between the second terminal of the reference voltage control transistor Trc and the first terminal of the data voltage control transistor Tdc may be connected to a plurality of transfer lines TL which are connected to first pixels  110   a  provided along data extension lines DEL. 
     A data line DL provided between the data voltage control transistor Tdc and the data driver  300  may be connected to a plurality of opaque area gate lines GL which are connected to second pixels  110   b  provided along the data line DL. 
     Hereinafter, a method of performing internal compensation by using the first pixel driving circuit PDC 1  will be described with reference to  FIGS. 1 to 16 . 
       FIG. 13  is an exemplary diagram showing waveforms of signals applied to an organic light emitting display apparatus according to an embodiment of the present disclosure, and  FIGS. 14 to 16  are exemplary diagrams illustrating a driving method of an organic light emitting display apparatus according to an embodiment of the present disclosure. 
     First, as illustrated in  FIGS. 12 to 14 , in a first period F 1 , the transparent area gate signals TGS having a low level may be supplied to the transparent area gate lines TGL. The transparent area gate signals TGS having a low level may be supplied to gates of the first transistors SW 1  included in the first pixel driving circuits PDC 1 . Therefore, the first transistors SW 1  may be turned on. The supply of the transparent area gate signals TGS having a low level to the transparent area gate lines TGL may denote that the first initialization transistor Tini 1  illustrated in  FIG. 11  are turned on by the first turn-on control signal ALL_L, and thus, the initialization control signal VGL having a low level is supplied to the transparent area gate line TGL. 
     In this case, the first driving voltage ELVDD may also have a low level, and thus, the driving transistor DR may also be turned on. A low level of the first driving voltage ELVDD may be equal to or less than the second driving voltage ELVSS. The second driving voltage ELVSS may have a high level. 
     The data control signal DATA_EN may have a high level and the emission signal EM may have a low level, and thus, the data voltage control transistor Tdc may be turned off and the reference voltage control transistor Trc may be turned on. Therefore, a reference voltage VREF may be supplied to the first terminal of the capacitor CST through the reference voltage control transistor Trc. A reference voltage VREF H  supplied through the reference voltage supply line RVL and the data voltage control transistor Tdc may have a high level. 
     Therefore, a difference voltage (=ELVDD L −VREF H ) between the first driving voltage ELVDD L  and the reference voltage VREF may be charged into the capacitor CST, a voltage VG at the gate of the driving transistor DR may be the first driving voltage ELVDD L , and a voltage V S  at a source of the driving transistor DR may be the first driving voltage ELVDD L . 
     Therefore, in the first period F 1 , the gate and the source of the driving transistor DR and the first organic light emitting diode OLED 1  may be initialized to the first driving voltage ELVDD L . 
     Subsequently, as illustrated in  FIGS. 12, 13, and 15 , in a second period F 2 , the transparent area gate signals TGS having a low level may be supplied to the transparent area gate lines TGL. The transparent area gate signals TGS having a low level may be supplied to gates of the first transistors SW 1  included in the first pixel driving circuits PDC 1 . Therefore, the first transistors SW 1  may be turned on. The supply of the transparent area gate signals TGS having a low level to the transparent area gate lines TGL may denote that the second initialization transistor Tini 2  illustrated in  FIG. 11  are turned on by the second turn-on control signal EN_SN, and thus, the gate pulse SCAN having a low level is supplied to the transparent area gate line TGL. 
     In this case, the first driving voltage ELVDD may have a high level, and the second driving voltage ELVSS may have a high level. 
     The data control signal DATA_EN may have a low level and the emission signal EM may have a high level, and thus, the data voltage control transistor Tdc may be turned on and the reference voltage control transistor Trc may be turned off. Therefore, a data voltage Vdata may be supplied to the first terminal of the capacitor CST through the data voltage control transistor Tdc. 
     Therefore, a voltage (=ELVDD H −|Vth|−Vdata) calculated by subtracting an absolute value of the threshold voltage Vth of the driving transistor DR and the data voltage Vdata from the first driving voltage ELVDD H  may be charged into the capacitor CST, the voltage V G  at the gate of the driving transistor DR may be a difference voltage (=ELVDD H −|Vth|) between the first driving voltage ELVDD H  and the absolute value of the threshold voltage Vth, and the voltage V S  at the source of the driving transistor DR may be the first driving voltage ELVDD H . 
     Therefore, in the second period F 2 , the threshold voltage Vth may be sensed, and the data voltage Vdata may be charged into the gate of the driving transistor DR. 
     Finally, as illustrated in  FIGS. 12, 13, and 16 , in a third period F 3 , the transparent area gate signals TGS having a high level may be supplied to the transparent area gate lines TGL. The transparent area gate signals TGS having a high level may be supplied to the gates of the first transistors SW 1  included in the first pixel driving circuits PDC 1 . Therefore, the first transistors SW 1  may be turned off. The supply of the transparent area gate signals TGS having a high level to the transparent area gate lines TGL may denote that the second initialization transistor Tini 2  illustrated in  FIG. 11  are turned on by the second turn-on control signal EN_SN, and thus, the gate-off signal Voff having a high level is supplied to the transparent area gate line TGL. 
     In this case, the first driving voltage ELVDD may have a high level, and the second driving voltage ELVSS may have a high level. That is, the first driving voltage ELVDD H  supplied to the transparent area AA 1  may have a low level in the first period F 1  and may have a high level in the third period F 3 . Therefore, a switch for transferring the first driving voltage ELVDD should be provided. The switch may be included in the power supply  700 , and in a case where the first driving voltage ELVDD H  is supplied through the gate driver  200 , the switch may be included in the gate driver  200 . A control signal for turning on the switch may be generated by the controller  400  and may be supplied to the switch. However, the first driving voltage ELVDD H  having a certain level may be supplied to the opaque area AA 2 . 
     The data control signal DATA_EN may have a high level and the emission signal EM may have a low level, and thus, the data voltage control transistor Tdc may be turned off and the reference voltage control transistor Trc may be turned on. Therefore, the reference voltage VREF L  having a low level may be supplied to the first terminal of the capacitor CST. 
     Therefore, the voltage (=ELVDD H −|Vth|−Vdata) calculated by subtracting the absolute value of the threshold voltage Vth of the driving transistor DR and the data voltage Vdata from the first driving voltage ELVDD H  may be charged into the capacitor CST, the voltage V G  at the gate of the driving transistor DR may be a voltage (=ELVDD H −|Vth|−Vdata+VREF L ) calculated by subtracting the absolute value of the threshold voltage Vth of the driving transistor DR and the data voltage Vdata from a sum of the first driving voltage ELVDD H  and the reference voltage VREF L , and the voltage V S  at the source of the driving transistor DR may be the first driving voltage ELVDD H . 
     In this case, a current I oled  flowing to the first organic light emitting diode OLED 1  through the driving transistor DR may be expressed as the following Equation 1. In Equation 1, a may be a proportional constant. 
     
       
         
           
             
               
                 
                   
                     I 
                     OLED 
                   
                   = 
                   
                     
                       
                         a 
                          
                         
                           ( 
                           
                             
                               V 
                               SG 
                             
                             - 
                             
                                
                               
                                 V 
                                 TH 
                               
                                
                             
                           
                           ) 
                         
                       
                       2 
                     
                      
                     
                       
 
                     
                     = 
                     
                       
                         a 
                          
                         
                           ( 
                           
                             Vdata 
                             - 
                             
                               VREF 
                               L 
                             
                           
                           ) 
                         
                       
                       2 
                     
                   
                 
               
               
                 
                   [ 
                   
                     Equation 
                      
                     
                         
                     
                      
                     1 
                   
                   ] 
                 
               
             
           
         
       
     
     That is, in the third period F 3 , the current I oled  flowing to the first organic light emitting diode OLED 1  may be based on the data voltage Vdata and the reference voltage VREF L  and may not be affected by a shift of the threshold voltage Vth of the driving transistor DR. 
     Therefore, even when the threshold voltage Vth of the driving transistor DR is shifted because the driving transistor DR is used for a long time, the current I oled  flowing to the first organic light emitting diode OLED 1  may not be affected by a shift of the threshold voltage Vth of the driving transistor DR. 
     That is, according to the present disclosure described above, the first pixel  110   a  and the second pixel  110   b  may output light based on the data voltage Vdata without being affected by a shift of the threshold voltage Vth. 
       FIG. 17  is another exemplary diagram illustrating a first pixel and a second pixel each included in an organic light emitting display apparatus according to an embodiment of the present disclosure, and  FIG. 18  is an exemplary diagram illustrating a gate driver, an initialization unit, and a transparent area each applied to the organic light emitting display apparatus illustrated in  FIG. 17 . In  FIG. 18 , gate pulses supplied to the first pixel  110   a  and the second pixel  110   b  are illustrated. In the following description, descriptions which are the same as or similar to descriptions given above with reference to  FIGS. 1 to 16  are omitted or will be briefly given. 
     As described above, the organic light emitting display apparatus according to an embodiment of the present disclosure may include the organic light emitting display panel  100  including the first pixels  110   a  and the second pixels  110   b , the gate driver  200 , the data driver  300 , the initialization unit  500 , and the controller  400 . 
     The transparent area AA 1 , as illustrated in  FIGS. 2 and 5 , may be formed from one end of the display area AA to the other end of the display area AA. 
     In this case, the initialization unit  500  may be provided in the first non-display area NAA 1  along with the gate driver  200 , or may be included in the gate driver  200 . When the initialization unit  500  is separated from the gate driver  200 , the initialization unit  500  may be provided between the gate driver  200  and the transparent area AA 1 . 
     Moreover, as illustrated in  FIGS. 1, 17, and 18 , the transparent area AA 1  may be surrounded by the opaque area AA 2 . That is, the transparent area AA 1  may be formed in only a region, corresponding to a region where the camera  600  is disposed in the organic light emitting display apparatus, of the organic light emitting display panel  100 . 
     In this case, as illustrated in  FIG. 18 , the initialization unit  500  may be provided in a boundary region between the transparent area AA 1  and a first opaque area AA 2   a  provided at one side of the transparent area AA 1 . The initialization unit  500  may include a plurality of first initialization drivers  511  connected to the transparent area gate lines. The boundary region may be the first opaque area AA 2   a , or may be the transparent area AA 1 . For example, the initialization unit  500  may be provided in the second pixels  110   b  provided in the first opaque area AA 2   a , provided in the first pixels  110   a  provided in the transparent area AA 1 , or provided in the first pixels  110   a  and the second pixels  110   b.    
     A configuration and a function of the initialization unit  500  may be the same as those of the initialization unit  500  described above with reference to  FIGS. 9 to 12 . 
     Therefore, a configuration and a function of the first initialization driver  511  illustrated in  FIG. 18  may be the same as those of the first initialization driver  510  described above with reference to  FIGS. 9 and 11 . 
     That is, as illustrated in  FIG. 11 , each of the first initialization drivers  511  illustrated in  FIG. 18  may include a first initialization transistor Tini 1 , which includes a first terminal connected to an initialization control signal supply line ISL, a second terminal connected to the transparent area gate line TGL, and a gate connected to a first turn-on control line TCL 1 , and a second initialization transistor Tini 2  which includes a first terminal connected to an opaque area gate line GL extending from the gate driver  200  to the first opaque area AA 2   a  among the gate lines, a second terminal connected to the transparent area gate line, and a gate connected to a second turn-on control line TCL 2 . 
     In this case, a difference between the first initialization driver  511  illustrated in  FIG. 18  and the first initialization driver  510  described above with reference to  FIGS. 9 and 11  may be that the first terminal of the second initialization transistor Tini 2  is connected to the opaque area gate line GL extending from the gate driver  200  to the first opaque area AA 2   a  among the gate lines. 
     That is, the initialization unit  500  described above with reference to  FIGS. 9 and 11  may be directly connected to the gate driver  200 , but the initialization unit  500  described above with reference to  FIG. 18  may be connected to the gate driver  200  through the first opaque area AA 2   a.    
     Therefore, the first terminal of the second initialization transistor Tini 2  illustrated in  FIG. 18  may be connected to the gate driver  200  through the opaque area gate line GL extending from the gate driver  200  to the first opaque area AA 2   a  among the gate lines. 
     Except for a structural difference described above, a configuration and a function of the first initialization driver  511  illustrated in  FIG. 18  may be the same as those of the first initialization driver  510  illustrated in  FIGS. 9 and 11 . 
     In this case, each of the first initialization drivers  511  illustrated in  FIG. 18  may transfer gate pulses SCANg−3 to SCANg, which are output from the gate driver  200  and pass through the first opaque area AA 2   a , to transparent area gate lines TGL provided in the transparent area AA 1  among the plurality of gate lines, or may transfer, to the transparent area gate lines TGL, initialization control signals VGL for initializing the first pixel driving circuits provided in the transparent area AA 1 . 
     In this case, as illustrated in  FIG. 18 , the initialization unit  500  may further include a plurality of second initialization drivers  512 . 
     For example, the second initialization drivers  512  may be provided in a boundary region between the transparent area AA 1  and a second opaque area AA 2   b  provided at the other side of the transparent area AA 1 . Also, the second initialization drivers  512  may be connected to the transparent area gate lines and a plurality of opaque area gate lines provided in the second opaque area AA 2   b.    
     That is, the second initialization drivers  512  may be provided to be symmetrical with the first initialization drivers  511  with the transparent areas AA 1  therebetween. 
     Therefore, a configuration, a function, and a driving method of each of the second initialization drivers  512  may be the same as those of each of the first initialization drivers  511 . 
     In the organic light emitting display apparatus, as illustrated in  FIG. 18 , the gate driver  200  may include a first driver  210 , provided at the one side (i.e., the first non-display area NAA 1 ) of the transparent area AA 1  in the non-display area NAA, and a second driver  220  provided at the other side (i.e., the second non-display area NAA 2 ) of the transparent area AA 1  in the non-display area NAA. 
     The first driver  210  and the second driver  220  may simultaneously output gate pulses to the same gate lines, or may output the gate pulses to different gate lines. 
     In this case, the initialization unit  500  (particularly, the first initialization driver  510  included in the initialization unit  500 ) may supply a gate pulse, supplied through the first opaque area AA 2   a  from the first driver  210 , to the transparent area gate line TGL. 
     The second driver  220  may supply a gate pulse to the second opaque area AA 2   b  provided at the other side NAA 2  of the transparent area AA 1 . The second initialization drivers  512  may supply gate pulses, transferred through the second opaque area AA 2   b  from the second driver  220 , to the transparent area gate lines TGL provided in the transparent area AA 1 . 
     However, the second initialization drivers  512  may be omitted. In this case, gate pulses supplied from the second driver  220  may be supplied to only opaque area gate lines provided in the second opaque area AA 2   b . That is, the opaque area gate lines provided in the second opaque area AA 2   b  may not be connected to the transparent area gate lines. 
       FIG. 19  is an exemplary diagram illustrating a structure of a second driving voltage supply line for transferring a second driving voltage to a second driving voltage line included in an organic light emitting display apparatus according to an embodiment of the present disclosure. 
     As described above with reference to  FIG. 13 , the second driving voltage ELVSS supplied to the first pixels  110   a  provided in the transparent area AA 1  may have a high level in the first period F 1  and the second period F 2  and may have a low level in the third period F 3 . 
     However, the second driving voltage ELVSS supplied to the second pixels  110   b  provided in the opaque area AA 2  may have a constant value. 
     Therefore, a transparent area second driving voltage supply line  191  for transferring the second driving voltage to a second driving voltage line PLB connected to the first pixel  110   a  may be implemented independently from an opaque area second driving voltage supply line  192  for transferring the second driving voltage to a second driving voltage line PLB connected to the second pixel  110   b.    
     For example, as illustrated in  FIG. 19 ( a ) , in a case where the transparent area is formed from one end of the display area AA to the other end of the display area AA, the transparent area second driving voltage supply line  191  may be provided to surround the transparent area AA 1  in the non-display area, and the opaque area second driving voltage supply line  192  may be provided to surround the opaque area AA 2  in the non-display area. 
     Moreover, as illustrated in  FIG. 19 ( b ) , in a case where the transparent area is surrounded by the opaque area, the transparent area second driving voltage supply line  191  may be provided at only a portion corresponding to the transparent area AA 1  in the non-display area, and the opaque area second driving voltage supply line  192  may be provided at only a portion corresponding to the opaque area AA 2  in the non-display area. 
     In this case, the second driving voltage supplied through the transparent area second driving voltage supply line  191  may vary as illustrated in  FIG. 13 , and the second driving voltage supplied through the opaque area second driving voltage supply line  192  may maintain to have a predetermined value (for example, 0 V). To this end, the controller  400  may control the power supply  700  which supplies the second driving voltage the transparent area second driving voltage supply line  191 . 
     Features of the present disclosure described above will be briefly described. 
     In the present disclosure, for example, an internal compensation circuit (i.e., the first pixel driving circuit PDC 1 ) including two PMOS transistors and one capacitor may be included in each of the first pixels  110   a  provided in the transparent area AA 1 , and an internal compensation circuit (i.e., the second pixel driving circuit PDC 2 ) including three or more transistors and one or more capacitors may be included in each of the second pixels  110   b  provided in the opaque area AA 2 . 
     Therefore, a light transmittance of the transparent area may be higher than that of the opaque area. 
     The transparent area AA 1  may correspond to a position of a camera disposed at the rear surface of the organic light emitting display panel  100  to face a region in front of the organic light emitting display panel  100 . 
     A density (PPI) of each of pixels provided in the transparent area AA 1  may be set to be equal to a density (PPI) of each of pixels provided in the opaque area AA 2 . Therefore, comparing with a related art organic light emitting display apparatus where a PPI of the transparent area is set to be lower than a PPI of the opaque area, the degradation in image quality may be minimized in the present disclosure. Accordingly, even when a camera is disposed at the rear surface of the organic light emitting display panel, photographing may be performed. 
     For example, in order to place the camera  600  and other sensors, as illustrated in  FIG. 5 , all regions corresponding to about 3 mm of an upper end (about 64 lines with respect to 537 ppi) of the organic light emitting display panel  100  may be formed as the transparent area AA 1 . 
     Moreover, as illustrated in  FIG. 17 , only a region corresponding to the camera  600  among regions corresponding to about 3 mm of the upper end of the organic light emitting display panel  100  may be the transparent area AA 1 . That is, only a region (about 3×3 mm, 537 ppi reference resolution 64×64), corresponding to the camera  600 , of the organic light emitting display panel  100  may be the transparent area AA 1 . 
     An anode of the first organic light emitting diode OLED 1  provided in the transparent area AA 1  may be formed of a transparent electrode and a reflective electrode, but may be formed of only transparent metal, for increasing a transmittance. 
     In addition to the anode, all lines provided in the transparent area AA 1  may be formed of transparent metal, for maximizing a transmittance of the transparent area AA 1 . 
     In the present disclosure, all first pixel driving circuits PDC 1  provided in the transparent area AA 1  may be simultaneously initialized, a threshold voltage may be compensated for by line units, data voltages may be recorded in all first pixels, and all lines may simultaneously emit light. 
     In the present disclosure, gate pulses output from the gate driver  200  may not differ from the related art. Therefore, a structure of the gate driver  200  may use a gate driver applied to a related art organic light emitting display apparatus. 
     In order to enhance a transmittance, as illustrated in  FIG. 12 , the first pixels  110   a  provided in the transparent area AA 1  may use transparent metal such as ITO instead of a metal line (for example, titanium/aluminum/titanium (Ti/Al/Ti)) of the related art, and particularly, a reflective electrode (Ag) of an anode may be omitted for enhancing a transmittance. 
     In the present disclosure, the first pixel driving circuit PDC 1  having a PMOS 3T1C structure occupying a smaller area than the second pixel driving circuit PDC 2  may be provided in the transparent area AA 1 , thereby minimizing the degradation in image quality of the camera  600  facing a region in front of the organic light emitting display panel  100 . Accordingly, according to the present disclosure, an organic light emitting display panel having a high-transmittance transparent area may be provided. 
     According to the present disclosure, even without a notch or a hole, a full display may be implemented for photographing a region in front of an organic light emitting display panel. 
     In the present disclosure, the PMOS 2T1C structure may use a global shutter driving manner, but such a structure is applied to only some lines corresponding to a camera region (i.e., the transparent area AA 1 ). Therefore, according to the present disclosure, a non-emission time for which a data voltage is recorded may be short, and thus, a high luminance of 600 nit or more may be implemented. 
     In the present disclosure, one organic light emitting display panel may include a transparent area, including an internal compensation circuit having the PMOS 2T1C structure, and an opaque area where an internal compensation circuit including three or more transistors is provided. 
     In the present disclosure, the transparent area including the internal compensation circuit having the PMOS 2T1C structure may be provided at a whole upper end line of the organic light emitting display panel, or may be provided in only a region corresponding to a camera. In this case, signals for controlling an internal compensation circuit (i.e., the first pixel driving circuit PDC 1 ) provided in the transparent area may be supplied to the first pixel driving circuit PDC 1  by the initialization unit  500 . 
     In the present disclosure, various lines provided in the transparent area may use transparent metal, but may use opaque metal which is being used currently and widely, for improving IR-drop. 
     In the present disclosure, the anode provided in the transparent area may be formed of only transparent metal such as ITO, for enhancing a transmittance, but in order to enhance emission efficiency although a transmittance is reduced, the anode may be formed of transparent metal (ITO) and opaque metal (Ag) or an alloy thereof. 
       FIG. 20  is another exemplary diagram illustrating an internal configuration of an organic light emitting display apparatus according to an embodiment of the present disclosure, and  FIG. 21  is another exemplary diagram illustrating a structure of a first pixel applied to an organic light emitting display apparatus according to an embodiment of the present disclosure. In the following description, descriptions which are the same as or similar to descriptions given above with reference to  FIGS. 1 to 19  are omitted or will be briefly given. Also, in  FIGS. 1 to 21 , like reference numerals refer to like elements. 
     The organic light emitting display apparatus according to an embodiment of the present disclosure, as illustrated in  FIG. 20 , may include a display area AA displaying an image and a non-display area NAA provided outside the display area AA. The display area AA may include an organic light emitting display panel  100  including a transparent area AA 1  which transmits light and an opaque area AA 2  which does not transmit light, a camera  600  which is provided in the transparent area AA 1  in a rea surface of the organic light emitting display panel  100  and photographs a region in a forward direction with respect to the organic light emitting display panel  100 , a digital gate driver  250  which sequentially supplies digital gate pulses to a plurality of gate lines TGLg−4 to TGLg (hereinafter simply referred to as a transparent area gate line) provided in the transparent area AA 1 , a digital data driver  350  which supplies digital data voltages to a plurality of data lines TDL 1  to TDLd (hereinafter simply referred to as a transparent area data line) provided in the transparent area AA 1 , a gate driver  200  which sequentially supplies a gate pulse to a plurality of gate lines GL 1  to GLg−5 (hereinafter simply referred to as an opaque area gate line) provided in the opaque area AA 2 , a data driver  300  which supplies data voltages to a plurality of data lines DL 1  to DLd (hereinafter simply referred to as an opaque area data line) provided in the opaque area AA 2 , and a controller  400  which controls driving of the digital gate driver  250 , the digital data driver  350 , the gate driver  200 , and the data driver  300 . A first pixel driving circuit provided in the transparent area AA 1  and a second pixel driving circuit provided in the opaque area AA 2  may have different structures. Particularly, the number of transistors included in the first pixel driving circuit may be two, and the number of transistors included in the second pixel driving circuit may be at least three. 
     That is, in the organic light emitting display apparatus illustrated in  FIG. 20 , the opaque area data lines DL 1  to DLd may be electrically disconnected from the transparent area data lines TDL 1  to TDLd. 
     In this case, the digital data driver  350  may supply the digital data voltages to the transparent area data lines TDL 1  to TDLd, and the data driver  300  may supply the data voltages to the opaque area data lines DL 1  to DLd. 
     Moreover, the digital gate driver  250  may supply the digital gate pulses to the transparent area gate lines TGLg−4 to TGLg, and the gate driver  200  may supply the gate pulses to the opaque area gate lines GL 1  to GLg−5. 
     A configuration and a function of the gate driver  200  may be the same as those of the gate driver described above with reference to  FIGS. 1 to 19 , and a configuration and a function of the data driver  300  may be the same as those of the data driver described above with reference to  FIGS. 1 to 19 . Therefore, detailed descriptions of the configurations and functions of the gate driver  200  and the data driver  300  are omitted. 
     A configuration and a function of the controller  400  may be similar to those of the controller described above with reference to  FIG. 3 . Therefore, as described above with reference to  FIG. 3 , the controller  400  may include the input unit  410 , the control signal generator  420 , the data aligner  430 , and the output unit  440 , and functions of the elements may be the same as the above-described functions. 
     In this case, as illustrated in  FIG. 20 , the controller  400  may further include functions of generating pieces of image data Data which are to be supplied to the digital data driver  350 , a digital data control signal DDCS for controlling the digital data driver  350 , and a digital gate control signal DGCS for controlling the digital gate driver  250  and transferring the generated data and signals to the digital data driver  350  and the digital gate driver  250 . 
     That is, the controller  400  may transfer the digital gate control signal DGCS to the digital gate driver  250  and may transfer the digital data control signal DDCS to the digital data driver  350 . In this case, the digital gate control signal DGCS may differ from the gate control signal GCS, and the digital data control signal DDCS may differ from the data control signal DCS. 
     However, in a case where the controller  400  and the data driver  300  are implemented as one first integrated circuit (IC) and the controller  400  and the digital data driver  350  are implemented as one second IC, a plurality of lines for transferring the input video data from the external system  800  may branch to the first IC and the second IC. Also, a timing synchronization signal TSS for generating the gate control signal GCS, the data control signal DCS, the digital gate control signal DGCS, and the digital data control signal DDCS may branch to the first IC and the second IC. 
     In this case, the first IC and the second IC may be independently driven, and particularly, a configuration and a function of the second IC may be the same as those of the controller  400  and the data driver  300 . 
     The digital gate driver  250  and the digital data driver  350  are technologies known to those skilled in the art and are being applied to various kinds of display apparatuses. Also, a feature of the present disclosure does not relate to a feature of each of the digital gate driver  250  and the digital data driver  350 . Therefore, detailed descriptions of the configurations and functions of the digital gate driver  250  and the digital data driver  350  are omitted, and a fundamental operating method of each of the digital gate driver  250  and the digital data driver  350  will be described below with reference to  FIG. 22 . 
     A structure of second pixel  110   b  provided in the opaque area AA 2  may be the same as a structure of the second pixel described above with reference to  FIG. 8 , and thus, its detailed description is omitted. 
     The first pixel  110   a  provided in the transparent area AA 1 , as illustrated in  FIG. 21 , may include a first organic light emitting diode OLED 1  and a first pixel driving circuit PDC 1  which drives the first organic light emitting diode OLED 1 . 
     The first pixel driving circuit PDC 1  may include a second transistor SW 2  which includes a first terminal connected to the transparent area data line TDL and a gate connected to the transparent area gate line TGL, a driving transistor DR which includes a first terminal connected to a first driving voltage line PLA, a gate connected to a second terminal of the second transistor SW 2 , and a second terminal connected to the first organic light emitting diode OLED 1 , and a second capacitor CST 2  which includes a first terminal connected to the gate of the driving transistor DR and a second terminal connected to the first terminal of the driving transistor DR. 
     A configuration of the first pixel  110   a  may be the same as a fundamental configuration applied to general organic light emitting display apparatuses. That is, as illustrated in  FIG. 21 , the first pixel driving circuit PDC 1  of the first pixel  110   a  may be implemented in a fundamental structure among structures of pixel driving circuits applied to an organic light emitting apparatus, and thus, may have a simplest structure among structures of pixel driving circuits. The first pixel driving circuit PDC 1  may not perform an internal compensation function. 
       FIG. 22  is an exemplary diagram showing structures of digital gate signals applied to the organic light emitting display apparatus illustrated in  FIG. 20 .  FIG. 22  illustrates digital gate signals DVG output to transparent area gate lines TGL in a period where one frame period starts. The digital gate signals DVG illustrated in  FIG. 22  may be output from the digital gate driver  250 . The digital gate signal DVG, like the gate signal VG, may include a digital gate pulse DSCAN for turning on the second transistors SW 2  connected to the transparent area gate line TGL and a digital gate-off signal DVoff for turning off the second transistors SW 2 . Hereinafter, a digital driving method using the digital gate driver  250  and the digital data driver  350  will be described. 
     Moreover, in the following description, an organic light emitting display apparatus where image data Data transferred from the controller  400  to the digital data driver  350  has 8 bits will be described as an example of the present disclosure. In this case,  FIG. 22  illustrates digital gate signals DVG applied up to 3 bits, but the forms of digital gate signals of 4 bits to 8 bits may be constructed as a form similar to  FIG. 22 . 
     In a digital driving method using the digital gate driver  250  and the digital data driver  350 , a gray level may be expressed by controlling a period where light is output. 
     For example, in a display apparatus which expresses 0 to 255 grays, 0 gray may be expressed as [00000000] corresponding to a binary number consisting of 8 bits, 1 gray may be expressed as [00000001], and 255 gray may be expressed as [11111111]. 
     In the binary number consisting of 8 bits, 8 bits may be referred to as a zeroth bit (bit[0]) to a seventh bit (bit[8]) in the order of a left bit to a right bit. 
     In one first pixel  110   a  provided in a first transparent area gate line, in order to express 0 gray, the controller  400  may transfer image data Data of [00000000] to the digital data driver  350 . 
     The image data may be converted into a data voltage and may be supplied to the second transistor SW 2  of the first pixel  110   a . For example, a data voltage corresponding to 0 in the image data may perform a function of turning off the driving transistor DR, and a data voltage corresponding to 1 may perform a function of turning on the driving transistor DR. That is, the image data may perform a function of turning on or off the driving transistor DR. To provide an additional description, the image data may perform a function of allowing the first organic light emitting diode OLED 1  to emit light or not to emit light. 
     A function of adjusting brightness of the light may be performed based on the digital gate signal DVG. 
     A method of adjusting brightness (i.e., luminance) of light on the basis of the image data Data and the digital gate signal DVG will be described below. 
     As illustrated in  FIG. 22 , when one frame period starts, a digital gate signal DVG 1  (i.e., a digital gate pulse DSCAN) having a low level may be output to the first transparent area gate line at a first timing. Therefore, the second transistor SW 2  included in the first pixel  110   a  connected to the first transparent area gate line may be turned on. 
     In this case, when a value “0” corresponding to a signal (i.e., the zeroth bit (bit[0])) for turning off the driving transistor DR is input to an n th  transparent area data line TDLn, a first pixel  110   a  connected to the n th  transparent area data line TDLn may not emit light. 
     When a second timing arrives, the digital gate signal DVG 1  (i.e., the digital gate-off signal DVoff) having a high level may be output to the first transparent area gate line. Therefore, the second transistor SW 2  included in the first pixel  110   a  connected to the first transparent area gate line may be turned off. Since the driving transistor DR are turned off at all of the first timing and the second timing, the first pixel  110   a  may not emit light at the second timing. That is, the first pixel  110   a  may not emit light at the second timing. 
     Such a state may be maintained up to third to eighth timings, the first pixel  110   a  may not emit light for the first to eighth timings. The first to eighth timings may be a period corresponding to the zeroth bit (bit[0]). 
     However, in a case where the second transistor SW 2  is turned on as the digital gate pulse DSCAN is output to the first transparent area gate line at the first timing, when a value “1” corresponding to a signal (i.e., the zeroth bit (bit[0])) for turning on the driving transistor DR is input to the n th  transparent area data line TDLn, the first pixel  110   a  connected to the n th  transparent area data line TDLn may emit light. 
     When the second timing arrives, the digital gate-off signal DVoff may be output to the first transparent area gate line. However, the driving transistor DR may still maintain a turn-on state on the basis of a voltage charged into the second capacitor CST 2 , and thus, the first pixel  110   a  may emit light at the second timing. 
     Such a state may be maintained up to the third to eighth timings, the first pixel  110   a  may emit light for the first to eighth timings. The first to eighth timings may be a period corresponding to the zeroth bit (bit[0]). 
     As illustrated in  FIG. 22 , the digital gate signal DVG 1  (i.e., the digital gate pulse DSCAN) having a low level may be output to the first transparent area gate line at a ninth timing. Therefore, the second transistor SW 2  included in the first pixel  110   a  connected to the first transparent area gate line may be turned on. 
     In this case, when a value “0” corresponding to a signal (i.e., the first bit NOD) for turning off the driving transistor DR is input to the n th  transparent area data line TDLn, the first pixel  110   a  connected to the n th  transparent area data line TDLn may not emit light. 
     When a tenth timing arrives, the digital gate signal DVG 1  (i.e., the digital gate-off signal DVoff) having a high level may be output to the first transparent area gate line. Therefore, the second transistor SW 2  included in the first pixel  110   a  connected to the first transparent area gate line may be turned off. Since the driving transistor DR are turned off at all of the ninth timing and the tenth timing, the first pixel  110   a  may not emit light at the tenth timing. 
     Such a state may be maintained up to eleventh to twenty-fourth timings, the first pixel  110   a  may not emit light for the ninth to twenty-fourth timings. The ninth to twenty-fourth timings may be a period corresponding to the first bit (bit[1]). 
     However, in a case where the second transistor SW 2  is turned on as the digital gate pulse DSCAN is output to the first transparent area gate line at the ninth timing, when a value “1” corresponding to a signal (i.e., the first bit NOD) for turning on the driving transistor DR is input to the n th  transparent area data line TDLn, the first pixel  110   a  connected to the n th  transparent area data line TDLn may emit light. 
     When the tenth timing arrives, the digital gate-off signal DVoff may be output to the first transparent area gate line. However, the driving transistor DR may still maintain a turn-on state on the basis of a voltage charged into the second capacitor CST 2 , and thus, the first pixel  110   a  may emit light at the tenth timing. 
     Such a state may be maintained up to the ninth to twenty-fourth timings, the first pixel  110   a  may emit light for the ninth to twenty-fourth timings. The ninth to twenty-fourth timings may be a period corresponding to the first bit (bit[1]). 
     In this case, a period corresponding to the zeroth bit (bit[0]) may include the first to eighth timings, and a period corresponding to the first bit (bit[1]) may include the ninth to twenty-fourth timings. That is, the period corresponding to the first bit (bit[1]) may be two times the period corresponding to the zeroth bit (bit[0]). To provide an additional description, a period where light corresponding to the first bit (bit[1]) is emitted may be longer than a period where light corresponding to the zeroth bit (bit[0]) is emitted. 
     Therefore, brightness corresponding to the first bit (bit[1]) may be brighter than brightness corresponding to the zeroth bit (bit[0]). 
     Based on the above-described principle, a period corresponding to a second bit (bit[2]) may be set to be longer than the period corresponding to the first bit (bit[1]), a period corresponding to a third bit (bit[3]) may be set to be longer than the period corresponding to the second bit (bit[2]), and a period corresponding to a seventh bit (bit[7]) may be set to be longer than a period corresponding to a sixth bit (bit[6]). 
     In each of the digital gate signals output from transparent area gate lines, an interval corresponding to the bits may be maintained to be constant, based on the above-described rule. 
     However, in each of the digital gate signals, a time at which a timing corresponding to the first bit starts may be differently set. 
     For example, as illustrated in  FIG. 22 , a timing at which a digital gate pulse corresponding to the zeroth bit (bit[0]) in a second digital gate pulse DVG 2  output to a second transparent area gate line is output may be delayed by eight timings compared to a timing at which a digital gate pulse corresponding to the zeroth bit (bit[0]) in the first digital gate pulse DVG 1  output to the first transparent area gate line is output. 
     Based on such a principle, timings for outputting the digital gate pulses may not overlap in the digital gate signals. 
     To provide an additional description, in a first pixel  110   a  which is supplied with a data voltage generated based on image data [00000000] corresponding to 0 gray, the driving transistor DR may be continuously turned off during one frame, and thus, light may not be emitted. Accordingly, 0 gray may be expressed. 
     In a first pixel  110   a  which is supplied with a data voltage generated based on image data [00000001] corresponding to 1 gray, light may be emitted at only eight timings corresponding to the zeroth bit (bit[0]). Accordingly, an image corresponding to 1 gray may be expressed. 
     In a first pixel  110   a  which is supplied with a data voltage generated based on image data [00000010] corresponding to 2 gray, light may be emitted at only sixteen timings corresponding to the first bit (bit[1]). Accordingly, an image corresponding to 2 gray may be expressed. 
     In a first pixel  110   a  which is supplied with a data voltage generated based on image data [00000011] corresponding to 3 gray, light may be emitted at twenty-four timings corresponding to the zeroth bit (bit[0]) and the first bit (bit[1]). Accordingly, an image corresponding to 3 gray may be expressed. 
     Based on the above-described principle, in a first pixel  110   a  which is supplied with a data voltage generated based on image data [11111111] corresponding to 255 gray, light may be emitted at timings corresponding to the zeroth bit (bit[0]) to the seventh bit (bit[7]). Accordingly, an image corresponding to 255 gray may be expressed. 
       FIG. 23  is an exemplary diagram illustrating a first pixel and a second pixel each included in an organic light emitting display apparatus according to an embodiment of the present disclosure. 
     The transparent area AA 1 , as illustrated in  FIGS. 20 and 23 , may be formed from one end of the display area AA to the other end of the display area AA. For example, the transparent area AA 1  may be provided between a first non-display area NAA 1  including the gate driver  200  and a second non-display area NAA 2  facing the first non-display area NAA 1  in the non-display area NAA. 
     In this case, as illustrated in  FIG. 23 , the second pixels  110   b  provided in the opaque area may be driven based on gate signals VG supplied from the gate driver  200  and data voltages Vdata supplied from the data driver  300 , and the first pixels  110   a  provided in the transparent area may be driven based on digital gate signals DVG supplied from the digital gate driver  250  and digital data voltages DVdata supplied from the digital data driver  350 . 
     That is, the first pixels  110   a  and the second pixels  110   b  may be independently driven. 
     In this case, the first pixels  110   a  may be driven by using the method (i.e., the digital driving method) described above with reference to  FIG. 22 . 
     The digital gate driver  250 , as illustrated in  FIGS. 20 and 23 , may be provided in only the first non-display area NAA 1 , but may be provided in all of the first non-display area NAA 1  and the second non-display area NAA 2 . In this case, two or more digital gate drivers  250  may simultaneously output digital gate signals having the same form to one transparent area gate line, or may output digital gate signals to different transparent area gate lines. 
     The gate driver  200  may be provided in only the first non-display area NAA 1 , or may be provided in all of the first non-display area NAA 1  and the second non-display area NAA 2 . 
       FIG. 24  is another exemplary diagram illustrating a first pixel and a second pixel each included in an organic light emitting display apparatus according to an embodiment of the present disclosure. 
     Moreover, as illustrated in  FIGS. 17 and 24 , the transparent area AA 1  may be surrounded by the opaque area AA 2 . That is, the transparent area AA 1  may be formed in only a region, corresponding to a region where the camera  600  is disposed in the organic light emitting display apparatus, of the organic light emitting display panel  100 . 
     In this case, as illustrated in  FIG. 24 , the second pixels  110   b  provided in the opaque area may be driven based on gate signals VG supplied from the gate driver  200  and data voltages Vdata supplied from the data driver  300 , and the first pixels  110   a  provided in the transparent area may be driven based on digital gate signals DVG supplied from the digital gate driver  250  and digital data voltages DVdata supplied from the digital data driver  350 . 
     That is, the first pixels  110   a  and the second pixels  110   b  may be independently driven. 
     In this case, the first pixels  110   a  may be driven by using the method (i.e., the digital driving method) described above with reference to  FIG. 22 . 
     In a case where the digital gate driver  250  is provided in only the first non-display area NAA 1  as illustrated in  FIG. 24 , the gate driver  200  may be provided in the second non-display area NAA 2 . 
     In this case, the transparent area gate lines TGL may be provided along the opaque area gate lines GL provided between the transparent area AA 1  and the digital gate driver  250 . 
     Moreover, the opaque area gate lines GL may extend, through the first opaque area AA 2   a  provided at one side of the transparent area AA 1  and the transparent area AA 1 , from the gate driver  200  to the second opaque area AA 2   b  provided at the other side of the transparent area AA 1 . 
     Hereinabove, the organic light emitting display apparatus described above with reference to  FIGS. 20 to 24  includes features which are the same as or similar to those of the organic light emitting display apparatus described above with reference to  FIGS. 1 to 19 . 
     That is, in the present disclosure described above with reference to  FIGS. 20 to 24 , for example, the first pixel driving circuit PDC 1  including two PMOS transistors and one capacitor may be included in each of the first pixels  110   a  provided in the transparent area AA 1 , and an internal compensation circuit (i.e., the second pixel driving circuit PDC 2 ) including three or more transistors and one or more capacitors may be included in each of the second pixels  110   b  provided in the opaque area AA 2 . 
     Therefore, a light transmittance of the transparent area may be higher than that of the opaque area. 
     The transparent area AA 1  may correspond to a position of a camera disposed at the rear surface of the organic light emitting display panel  100  to face a region in front of the organic light emitting display panel  100 . 
     A density (PPI) of each of pixels provided in the transparent area AA 1  may be set to be equal to a density (PPI) of each of pixels provided in the opaque area AA 2 . Therefore, comparing with a related art organic light emitting display apparatus where a PPI of the transparent area is set to be lower than a PPI of the opaque area, the degradation in image quality may be minimized in the present disclosure. Accordingly, even when a camera is disposed at the rear surface of the organic light emitting display panel, photographing may be performed. 
     In the present disclosure, the first pixel driving circuit PDC 1  having a PMOS 2T1C structure occupying a smaller area than the second pixel driving circuit PDC 2  may be provided in the transparent area AA 1 , thereby minimizing the degradation in image quality of the camera  600  facing a region in front of the organic light emitting display panel  100 . Accordingly, according to the present disclosure, an organic light emitting display panel having a high-transmittance transparent area may be provided. 
     According to the present disclosure, even without a notch or a hole, a full display may be implemented for photographing a region in front of an organic light emitting display panel. 
     Particularly, in the organic light emitting display apparatus according to the present disclosure described above with reference to  FIGS. 20 to 24 , the first pixel  110   a  and the second pixel  110   b  may be independently driven by different drivers. 
       FIG. 25  is an exemplary diagram illustrating a result obtained by comparing the compensation performance of a related art pixel driving circuit with the compensation performance of a first pixel driving circuit applied to an organic light emitting display apparatus according to an embodiment of the present disclosure. Particularly, in  FIG. 25 , (a) illustrates internal compensation performance based on the first pixel driving circuit PDC 1  having a structure illustrated in  FIG. 6 or 21 , and (b) illustrates internal compensation performance based on the second pixel driving circuit PDC 2  including seven transistors and one capacitor. 
     In the present disclosure, as described above, the first pixel  110   a  provided in the transparent area AA 1  may include, for example, an internal compensation circuit (i.e., the first pixel driving circuit PDC 1 ) including two transistors and one capacitor, and the second pixel  110   b  provided in the opaque area AA 2  may include, for example, at least three capacitors. 
     In this case, particularly,  FIG. 25  illustrates a result obtained by comparing the compensation performance of the second pixel  110   b , which includes seven transistors and one capacitor and performs internal compensation, with the compensation performance of the first pixel  110   a  which includes two transistors and one capacitor and performs internal compensation. 
     That is, in a low gray level such as 31 gray and 64 gray, compensation performance based on the first pixel driving circuit PDC 1  maintains the same level as compensation performance based on the second pixel driving circuit PDC 2 , but in 255 gray, compensation performance based on the first pixel driving circuit PDC 1  maintains a level which is higher than compensation performance based on the second pixel driving circuit PDC 2 . 
     Therefore, it may be seen that the compensation performance of the first pixel driving circuit PDC 1  is similar to that of the second pixel driving circuit PDC 2 , and thus, there is no an image quality difference between the transparent area and the opaque area. 
     In an organic light emitting display apparatus according to the embodiments of the present disclosure, a first pixel driving circuit provided in a transparent area, corresponding to a position of a camera, of a display area displaying an image may have a shape differing from that of a second pixel driving circuit provided in an opaque area, except the transparent area, of the display area. Particularly, the number of transistors included in the first pixel driving circuit may be two, and the number of transistors included in the second pixel driving circuit may be at least three. 
     Therefore, the amount of light transferred to the camera through the transparent area may increase, and thus, the quality of an image captured by the camera may be enhanced. 
     That is, according to the embodiments of the present disclosure, a transparent pixel structure (a PMOS 2T1C internal compensation circuit) may be applied to a region, where a front camera is disposed, of the organic light emitting display panel, and thus, even when a camera is disposed on a rear surface of the organic light emitting display panel, photographing may be performed. Particularly, according to the embodiments of the present disclosure, pixels of the transparent area may be implemented at the same density (pixel per inch (PPI)) as pixels of a related art organic light emitting display panel, and thus, the reduction in image quality may decrease compared to the related art organic light emitting display panel where the pixels of the transparent area are implemented at a low density (PPI). 
     The above-described feature, structure, and effect of the present disclosure are included in at least one embodiment of the present disclosure, but are not limited to only one embodiment. Furthermore, the feature, structure, and effect described in at least one embodiment of the present disclosure may be implemented through combination or modification of other embodiments by those skilled in the art. Therefore, content associated with the combination and modification should be construed as being within the scope of the present disclosure. 
     It will be apparent to those skilled in the art that various modifications and variations can be made in the present disclosure without departing from the spirit or scope of the disclosure. Thus, it is intended that the present disclosure covers the modifications and variations of this disclosure provided they come within the scope of the appended claims and their equivalents.