Patent Publication Number: US-8542782-B2

Title: Circuit for detecting a digital data stream and associated method

Description:
CROSS REFERENCE TO RELATED PATENT APPLICATIONS 
     This patent application claims priority to Provisional Application No. 61/180,126, filed on May 20, 2009. 
    
    
     TECHNICAL FIELD 
     The present disclosure relates to a circuit for detecting a digital data stream and an associated method, and more particularly, to a circuit for detecting whether a cosine component and a sine component in a digital data stream are swapped, called IQ swap, and for detecting a carrier frequency offset in the digital data stream, and an associated method. 
     BACKGROUND OF THE DISCLOSURE 
     In the Digital Video Broadcasting over Terrestrial 2 (DVB-T2) system, since various spectrum reverse operations may be involved during signal processing, a signal received from an antenna may be a correct spectrum or a reversed spectrum, and the reversed spectrum is equivalent to swapping cosine and sine components in the correct spectrum in the time-domain. To prevent errors from occurring during subsequent data demodulation due to the signal with a reversed spectrum, the receiver first determines whether the received signal is a correct or reversed spectrum and then switches connections of a multiplexer accordingly to transmit the correct signals to subsequent processing circuits—such approach however needs a rather longer detection time to undesirably affect processing performance of the receiver. 
     Further, orthogonal frequency-division multiplexing (OFDM) is implemented in the DVB-T2 system, and thus significant inter-carrier interference (ICI) is present in the receiver. To lower the ICI, the receiver generally adopts a circuit for improving carrier frequency offset. Therefore, it is an important task to provide a circuit with a minimal cost and a method with optimal efficiency for improving the carrier frequency offset. 
     SUMMARY OF THE DISCLOSURE 
     It is an object of the present disclosure to provide a circuit for detecting a digital data stream and an associated method, which are capable of quickly detecting whether cosine and sine components in the digital data stream are swapped, called IQ swapped, while also detecting a carrier frequency offset of the digital data stream to overcome the foregoing issues. 
     A circuit for detecting a digital data stream comprising a predetermined symbol is provided according to one embodiment of the present disclosure. The predetermine symbol comprises a first data and a second data, and the first data is generated by performing frequency shifting upon the second data. The circuit comprises a first detecting circuit, a second detecting circuit and a decision unit. The first detecting circuit is for detecting correlation between a first frequency-shifted data and the second data to generate a first correlated data, wherein the first frequency-shifted data is generated by performing first frequency shifting upon the first data. The second detecting circuit is for detecting correlation between a second frequency-shifted data and the second data to generate a second correlated data, wherein the second frequency-shifted data is generated by performing second frequency shifting upon the first data. The decision unit is for determining a signal status of the digital data stream according to the first and second correlated data. 
     A method for detecting a digital data stream comprising a predetermined symbol is provided according to another embodiment of the present disclosure. The predetermine symbol comprises a first data and a second data, and the first data is generated by performing frequency shifting upon the second data. The method comprises calculating correlation between a first frequency-shifted data and the second data to generate a first correlated data, wherein the first frequency-shifted data is generated by performing first frequency shifting upon the first data; calculating correlation between a second frequency-shifted data and the second data to generate a second correlated data, wherein the second frequency-shifted data is generated by performing second frequency shifting upon the first data; and determining a status of the digital data stream according to the first and the second correlated data. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The present disclosure will become more readily apparent to those ordinarily skilled in the art after reviewing the following detailed description and accompanying drawings, in which: 
         FIG. 1  is a schematic diagram of a circuit for detecting a digital data stream according to one embodiment of the present disclosure; 
         FIG. 2  is a schematic view of a DVB-T2 compliant digital data stream containing a P 1  symbol; 
         FIG. 3  is a schematic view of a DVB-T2 compliant receiver; 
         FIGS. 4   a  and  4   b  are flowcharts of a method for detecting a digital data stream according to one embodiment of the present disclosure; and 
         FIG. 5  is a schematic diagram of a correlated data outputted by a first detecting circuit or the second detecting circuit. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
       FIG. 1  shows a schematic diagram of a circuit  100  for detecting a digital data stream according to one embodiment of the present disclosure. As shown, the circuit  100  comprises a first detecting circuit  110 , a second detecting circuit  120  and a decision unit  130 . The first detecting circuit  110  comprises a frequency shifter  111 , three delay units  112 ,  115  and  116 , two correlators  113  and  117 , two filters  114  and  118 , and a multiplier  119 . The second detecting circuit  120  comprises a frequency shifter  121 , three delay units  122 ,  125  and  126 , two correlators  123  and  127 , two filters  124  and  128 , and a multiplier  129 . In this embodiment, the circuit  100  is applied to a DVB-T2 system, the frequency shifter  111  has a frequency offset of f sh , and the frequency shifter  121  has a frequency offset of −f sh , where f sh  is 1/1024T and T is a sampling cycle of the digital data stream. 
     In one embodiment of the present disclosure, delays of the delay units  112 ,  115  and  116 , and window lengths of the filters  114  and  118  of the first detecting circuit  110 , and delays of the delay units  122 ,  125  and  126 , and window lengths of the filters  124  and  128  of the second detecting circuit  120  are determined based on the digital data stream and a format of a P 1  symbol of the DVB-T2 specification.  FIG. 2  is a schematic diagram of a DVB-T2 compliant digital data stream comprising a P 1  symbol. As shown, a data frame comprises a P 1  symbol, a P 2  symbol and data. The P 1  symbol is mainly consisted of three data in sequence, namely a data C with 542 samples and a time length of T C , a data A with 1024 samples and a time length of T A , and a data B with 482 samples and a time length of T B . Further, the data C is a frequency-shifted data generated by performing frequency shifting upon a first half of the data A (i.e., a data C′), and the data B is a frequency-shifted data generated by performing frequency shifting upon a second half of the data A (i.e., a data B′). An equation for the P 1  symbol p 1 (t) is as below: 
                 p   1     ⁡     (   t   )       =     {               p     1   ⁢   A       ⁡     (   t   )       ⁢     ⅇ     ⅈ   ⁢       2   ⁢   π       1024   ⁢   T       ⁢   t               0   ≤   t   &lt;     542   ⁢   T                   p     1   ⁢   A       ⁡     (     t   -     542   ⁢   T       )               542   ⁢   T     ≤   t   &lt;     1566   ⁢   T                     p     1   ⁢   A       ⁡     (     t   -   1024     )       ⁢     ⅇ     ⅈ   ⁢       2   ⁢   π       1024   ⁢   T       ⁢   t                 1566   ⁢   T     ≤   t   &lt;     2048   ⁢   T               0         otherwise   ,                   
where p 1A  is content of the data A, and T is a sampling cycle of the digital data stream. For example, the delay units  112  and  122  provide a delay of T C  (i.e., a time of the 542 samples of the data C in the P 1  symbol), the delay units  116  and  126  provide a delay of T B  (i.e., a time of the 482 samples of the data B in the P 1  symbol), and the delay units  115  and  125  provide a delay of 2*T B  (i.e., twice the time of the 482 samples of the data B in the P 1  symbol). The filters  114  and  124  have a window length of approximately equal to the number of samples of the data C in the P 1  symbol; that is, 542, any integer approximating 542, or a value of 2 to the power of n (e.g., 256, 512 or 1024). Similarly, the filters  118  and  128  have a window length of approximately equal to the number of samples of the data B in the symbol P 1 ; that is, 482, any integer approximating 482, or a value of 2 to the power n (e.g., 256, 512 or 1024).
 
     The circuit  100  may be applied to a DVB-T2 compliant receiver  300  shown in  FIG. 3 . As shown in  FIG. 3 , the receiver  300  comprises a mixer  310 , a multiplexer  320 , a demodulator  330  and the circuit  100  shown in  FIG. 1 . The mixer  310  receives an input signal Vin and outputs a cosine component I and a sine component Q to the multiplexer  320  and the circuit  100 . The circuit  100  then determines whether the cosine component I and the sine component Q are swapped, and generates an output signal V out     —     1  to the multiplexer  320  to switch transmission paths. For example, when the circuit  100  determines that the cosine component I and the sine component Q are not swapped, the cosine component I is transmitted via a path P 1  and the sine component is transmitted via a path P 2  to a demodulator  330 ; when the circuit  100  determines that the cosine component I and the sine component Q are swapped, the cosine component I is transmitted via the path P 2  and the sine component Q is transmitted via the path P 1  to the demodulator  330 . Further, the circuit  100  may also determine a carrier frequency offset of the input signal Vin according to the cosine component I and the sine component Q to generate an output signal V out     —     2  to an oscillator (not shown) in the mixer  310  to adjust the output carrier frequency. 
     Supposing the P 1  symbol in the digital data stream is inputted into the circuit  100 , either the first detecting circuit  110  or the second detecting circuit  120  generates a sharper peak. More specifically, the second detecting circuit  120  generates a sharper peak while no noticeable difference is observed at the output of the first detecting circuit  110  when the cosine component I and the sine component Q are not swapped; on the contrary, the first detecting circuit  110  generates a sharper peak while no noticeable difference is observed at the output of the second detecting circuit  120  when the cosine component I and the sine component Q are swapped. Therefore, by comparing the amplitude of the output signals from the first detecting circuit  110  and the second detecting circuit  120 , it is determined whether the cosine component I and the sine component Q are swapped. 
     Operation details of the circuit  100  shall be described below. Also with reference to  FIG. 1 ,  FIGS. 4   a  and  4   b  are flowcharts of a method for detecting a digital data stream according to an embodiment of the present disclosure. Note that provided same results are substantially achieved, the steps according to the present disclosure need not be performed as sequences shown in  FIGS. 4   a  and  4   b.    
     Referring to  FIGS. 4   a  and  4   b , in Step  400 , the frequency shifter  111  in the first detecting circuit  110  performs frequency shifting upon a digital data stream. In the description below, suppose the circuit  100  is currently processing a P 1  symbol P 1 (t)*exp(j2πf 0 t) in the digital data stream, wherein f 0  is the frequency offset of the digital data stream. After the frequency shifter  111  performs frequency shifting upon the data P 1 (t)*exp(j2πf 0 t), a frequency-shifted data P 1     —     up (t) with a frequency offset f sh  of 1/2024T is generated, where T is a sampling cycle of the digital data stream. Suppose at this point, the cosine component I and the sine component are swapped, i.e., the data of the P 1  symbol is in fact j[P 1 (t)*exp(j2πf 0 t)]*, the frequency-shifted data j[P 1 (t)*exp(j2πf 0 t)]* is then represented as:
 
 P   1     —     up ( t )= jP   1 *( t ) e   j2π(−f     0     +f     sh     )t   (1)
 
     In Step  402 , the delay unit  112  delays the frequency-shifted data P 1     —     up (t) to generate a delayed data P 1     —     up     —     TC (t), where T C  represents the delay, i.e., 542 samples. The delay unit  116  delays the data P 1 (t)*exp(j2πf 0 t) of the P 1  symbol to generate a delayed data P 1     —     TB (t), where T B  represents the delay, i.e., 482 samples. The delayed data P 1     —     up     —     TC (t) and P 1     —     TB (t) are respectively represented as:
 
 P   1     —     up     —     TC ( t )= jP   1 *( t−T   c ) e   j2π(−f     0     +f     sh     )(t−T     c     )   (2)
 
 P   1     —     TB ( t )= jP   1 *( t−T   B ) e    −j2πf     0     (t−T     B     )   (3)
 
     In Step  404 , the correlator  113  correlates the data P 1 (t)*exp(j2πf 0 t) and the delayed data P 1     —     up     —     TC (t) to generate a correlated data D cor     —     1 , and the correlator  117  correlates the frequency-shifted data P 1     —     up (t) and the delayed data P 1     —     TB (t) to generate a correlated data D cor     —     3 . The correlated data D cor     —     1  and D cor     —     3  are respectively represented as:
 
 D   cor     —     1   =P   1 *( t ) P   1 ( t−T   c ) e   −j2πf     0     T     c     e   −j2πf     sh     (t−T     c     )   (4)
 
 D   cor     —     3   =P   1 *( t ) P   1 ( t−T   B ) e   j2πf     sh     t   e   −j2πf     0     T     B     (5)
 
     In Step  406 , the filter  114  performs low-pass filtering upon the correlated data D cor     —     1  to generate a filtered correlated data D cor     —     1     —     fil , and the filter  118  performs low-pass filtering upon the correlated data D cor     —     3  to generate a filtered correlated data D cor     —     3     —     fil . The correlated data D cor     —     1     —     fil  at a time point tε[2T C ,T C +T R ] and D cor     —     3     —     fil  at a time point tε[2T C +2T B ,2T C +T B +T R ] are respectively represented as:
 
 D   cor     —     1     —     fil   =c   1   ·   −j2πf     0     T     C     +N   i1   (6)
 
 D   cor     —     3     —     fil   =c   2   ·e   −j2πf     0     T     B     +N   i2   (7),
 
where c 1  and c 2  are constants and N i1  and N i2  are noise.
 
     In Step  408 , the filtered correlated data D cor     —     1     —     fil  is delayed by a time of 2T B  by the delayed unit  115  and then multiplied with the filtered correlated data D cor     —     3     —     fil  to obtain a correlated data D cor     —     5 . The correlated data D cor     —     5  at a time point tε[2T C +T A ,2T C +T R +T A ] is represented as:
 
 D   cor     —     5   =c   1   c   2   ·e   −j2πf     0     (T     C     +T     B     )   +N   i3   (8),
 
where N i3  is noise.
 
     In Step  410 , the frequency shifter  121  in the second detecting circuit  120  performs frequency shifting upon the data P 1 (t)*exp(j2πf 0 t) of the P 1  symbol. Note that the second detecting circuit  120  is synchronized with the first detecting circuit  110 ; that is, the second detecting circuit  120  and the first detecting circuit  110  at the same time receive a same signal. The frequency shifter  121  performs frequency shifting upon the data P 1 (t)*exp(j2πf 0 t) to generate a frequency-shifted data P 1     —     down (t) having a frequency offset f sh  of (−1/1024T), where T is a sampling cycle of the digital data stream. Suppose at this point the cosine component I and the sine component Q are not swapped, i.e., the P 1  symbol is P 1 (t)*exp(j2πf 0 t), the frequency-shifted data P 1     —     down (t) is represented as:
 
 P   1     —     down ( t )= P   1 ( t ) e   j2π(f     0     −f     sh     )t   (9)
 
     In Step  412 , the delay unit  122  delays the frequency-shifted data P 1     —     down (t) to generate a delayed data P 1     —     down     —     TC (t), where T C  represents the delay, i.e., 542 samples. The delay unit  126  delays the data P 1 (t)*exp(j2πf 0 t) of the P 1  symbol to generate a delayed data P 1     —     TB (t), where T B  represents the delay, i.e., 482 samples. The delayed data P 1     —     down     —     TC (t) and P 1     —     TB (t) are respectively represented as:
 
 P   1     —     down     —     TC ( t )= P   1 ( t−T   c ) e   j2π(f     0     −f     sh     )(t−T     c     )   (10)
 
 P   1     —     TB ( t )= P   1 ( t−T   B ) e   j2πf     0     (t−T     B     )   (11)
 
     In Step  414 , the correlator  123  correlates the data P 1 (t)*exp(j2πf 0 t) and the delayed data P 1     —     up     —     TC (t) to generate a correlated data D cor     —     2 , and the correlator  127  correlates the frequency-shifted data P 1     —     down (t) and the delayed data P 1     —     TB (t) to generate a correlated data D cor     —     4 . The correlated data D cor     —     2  and D cor     —     4  are respectively represented as:
 
 D   cor     —     2   =P   1 ( t ) P   1 *( t−T   c ) e   j2πf     0     T     c     e   j2πf     sh     (t−T     c     )   (12)
 
 D   cor     —     4   =P   1 ( t ) P   1 *( t−T   B ) e   −j2πf     sh     t   e   j2πf     0     T     B     (13)
 
     In Step  416 , the filter  124  performs low-pass filtering upon the correlated data D cor     —     2  to generate a filtered correlated data D cor     —     2     —fil   , and the filter  128  performs low-pass filtering upon the correlated data D cor     —     4  to generate a filtered correlated data D cor     —     4     —     fil . The filtered correlated data D cor     —     2     —     fil  at a time point tε[2T C ,T C +T R ] and the filtered correlated data D cor     —     4     —     fil  at a time point tε[2T C +2T B ,2T C +T B +T R ] are respectively represented as:
 
 D   cor     —     2     —     fil   =c   1   ·e   j2πf     0     T     C     +N   i1   (14)
 
 D   cor     —     4     —     fil   =c   2   ·e   j2πf     0     T     B     +N   i2   (15),
 
where c 1  and c 2  are constants and N i1  and N i2  are noise.
 
     In Step  418 , the filtered correlated data D cor     —     2     —     fil  is delayed by a time of 2T B  by the delayed unit  125  and then multiplied with the filtered correlated data D cor     —     4     —     fil  to obtain a correlated data D cor     —     6 . The correlated data D cor     —     6  at a time point t ε[2T C +T A ,2T C +T R +T A ] is represented as:
 
 D   cor     —     6   =c   1   c   2   ·e   j2πf     0     (T     C     +T     B     )   +N   i3   (16),
 
where N i3  is noise.
 
     More details on the correlated data D cor     —     5  and D cor     —     6  respectively generated by the first detecting circuit  110  and the second detecting circuit  120  shall be given below. When the cosine component I and the sine component Q are not swapped, at a time point t=2T C +2T B , while no noticeable difference is observed at an amplitude of the correlated data D cor     —     5  outputted by the first detecting circuit  110 , the correlated data D cor     —     6  outputted by the second detecting circuit  120  shows a peak as depicted in  FIG. 5  (supposing that the circuit  100  starts to receive the beginning of the data P 1 (t) of the P 1  symbol at a time t=0), with the amplitude of the peak being as stated by Equation (16). On the contrary, when the cosine component I and the sine component Q in the digital data stream are swapped, at a time point t=2T C +2T B , while no noticeable difference is observed at amplitude of the correlated data D cor     —     6  outputted by the second detecting circuit  120 , the correlated data D cor     —     5  outputted by the first detecting circuit  110  shows a peak, with the amplitude of the peak being as stated by Equation (8). 
     Therefore, in Step  420 , by comparing the amplitude of the correlated data D cor     —     5  and D cor     —     6 , the decision unit  130  determined whether the cosine component I and the sine component Q are swapped and accordingly generates an output signal V out     —     1  to the multiplexer  320  to determine transmission paths. 
     After the determining whether the cosine component I and the sine component Q are swapped, in Step  422 , the decision unit  130  selects either the correlated data D cor     —     5  or the correlated D cor     —     6 , and determines the carrier frequency offset, i.e., the foregoing f 0 , according to the numbers of samples in the data C and B of the P 1  symbol and a phase angle of the selected correlated data, i.e., either D cor     —     5  or D cor     —     6 . 
     More specifically, suppose the digital data stream contains a carrier frequency offset f 0 , and the cosine component I and the sine component Q in the digital data stream are swapped, the correlated data D cor     —     5  outputted by the first detecting circuit  110  at a time point t=2T C +2T B  is c 1 *exp(−2πf 0 (T C +T B )). The carrier frequency offset f 0  in the digital data stream is thus: 
                 f   0     =     -     θ     2   ⁢     π   ⁡     (       T   C     +     T   B       )               ,         
where θ is a phase angle of the correlated data D cor     —     5  at a time point t=2T C +2T B . On the other hand, suppose the digital data stream contains a carrier frequency offset f 0 , and the cosine component I and the sine component Q in the digital data stream are not swapped, the correlated data D cor     —     6  outputted by the second detecting circuit  120  at a time point t=2T C +2T B  is c 1 *exp(2πf 0 (T C +T B )). The carrier frequency offset f 0  in the digital data stream is thus:
 
                 f   0     =     θ     2   ⁢     π   ⁡     (       T   C     +     T   B       )             ,         
where θ is a phase angle of the correlated data D cor     —     6  at a time point t=2T C +2T B .
 
     Further, the circuit  100  may also be implemented for quickly retrieving the P 1  symbol from the digital data stream. More specifically, suppose the cosine component I and the sine component Q are swapped, a peak is reflected at a time point t=2T C +2T B  on the waveform of the correlated data D cor     —     5  outputted by the first detecting circuit  110 . Therefore, a time point where the peak occurs on the waveform of the correlated data D cor     —     5  outputted by the first detecting circuit  110  is first detected, and a start position of the data P 1 (t) of the P 1  symbol is then determined by going back a time of 2T C +2T B  from the detected time point, so as to retrieve the P 1  symbol and transmit the retrieved P 1  symbol to a subsequent processing unit for demodulation. On the contrary, suppose the cosine component I and the sine component Q are not swapped, a peak is reflected at a time point t=2T C +2T B  on the waveform of the correlated data D cor     —     6  outputted by the second detecting circuit  120 . Therefore, a time point where the peak occurs on the waveform of the correlated data D cor     —     6  outputted by the second detecting circuit  110  is first detected, and a start position of the data P 1 (t) of the P 1  symbol is then determined by going back a time of 2T C +2T B  from the detected time point, so as to retrieve the P 1  symbol and transmit the retrieved P 1  symbol to a subsequent processing unit for demodulation. 
     It is to be noted that, the embodiment shown in  FIG. 1  is implemented in the DVB-T2 system, and the circuit  100  applied for detecting whether the cosine and sine components in the digital data stream in the DVB-T2 system are IQ-swapped, as well as for estimating a carrier frequency offset of the digital data stream. However, the circuit according to the present disclosure may also be applied to other systems that process a structure as the P 1  symbol in the digital data stream shown in  FIG. 2 . That is, the circuit according to the present disclosure is applicable for detecting a digital data stream comprising a plurality of data frames, each of which having a predetermined symbol at a beginning thereof The predetermined symbol is similar to the P 1  symbol, as having a first data, a second data, a third data and a fourth data; and the first data is generated by performing a predetermined operation upon the second data, and the fourth data is generated by performing a predetermined operation upon the third data. Further, the predetermined symbol contains certain information for demodulating the digital data stream, such information of an FFT mode needed by data modulation and information of whether an antenna transceiving mode is multiple input or single input. 
     In others embodiments according to the present disclosure, the first detecting circuit  110  and the second detecting circuit  120  may also output corresponding correlated data via a single path. For example, in one embodiment of the present disclosure, the delay units  112  and  115 , the correlator  113 , the filter  114  and the multiplier  119  in the first detecting circuit  110 , and the delay units  122  and  125 , the correlator  123 , the filter  124  and the multiplier  129  in the second detecting circuit  120  shown in  FIG. 1  may be removed, and the decision unit  130  determines whether the cosine and sine components in the digital data stream are IQ-swapped directly according to the filtered correlated data D cor     —     3     —     fil  from the filter  118  and the filtered correlated data D cor     —     4     —     fil  from the filter  128 . In another embodiment of the present disclosure, the delay units  115  and  116 , the correlator  117 , the filter  118  and the multiplier  119  in the first detecting circuit  110 , and the delay units  125  and  126 , the correlator  127 , the filter  128  and the multiplier  129  in the second detecting circuit  120  may be removed, and the decision unit  130  determines whether the cosine and sine components in the digital data stream are IQ-swapped directly according to the filtered correlated data D cor     —     1     —     fil  from the filter  114  and the filtered correlated data D cor     —     2     —     fil  from the filter  124 . Note that the above modifications are within the scope of the present disclosure. 
     In conclusion, according to the circuit for detecting a digital data stream and an associated method thereof, within a relatively short period, a location of a P 1  symbol in a digital data stream is detected, whether a cosine component and a sine component in a digital data stream are IQ-swapped are detected, and a carrier frequency offset of the digital data stream is estimated all at the same time, thereby enhancing signal processing performance of a receiver. 
     While the present disclosure has been described in terms of what is presently considered to be the most practical and preferred embodiments, it is to be understood that the present disclosure needs not to be limited to the above embodiments. On the contrary, it is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims which are to be accorded with the broadest interpretation so as to encompass all such modifications and similar structures.