Patent Publication Number: US-6211022-B1

Title: Field leakage by using a thin layer of nitride deposited by chemical vapor deposition

Description:
This application is a Division of U.S. patent application Ser. No. 08/978,754, filed Nov. 26, 1997, now a Continued Prosecution Application. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to materials and methods used in the manufacture of a semiconductor device which includes an array of transistors to decrease current leakage to achieve better isolation between transistors. 
     2. Description of the Related Art 
     FIG. 1 shows a cross section of two NMOS transistors illustrating the typical configuration of materials used in the manufacture of a semiconductor device containing an array of transistors. The transistors are shown formed in a p-type silicon substrate  2 . A first transistor  4  includes n-type source and drain implant regions  6  and  8  provided in the substrate  2 . A polysilicon gate region  10  of the first transistor  4  is provided bridging the source  6  and drain  8  regions. The polysilicon gate region  10  is separated from the substrate  2  by a dielectric  22 . A second transistor  14  includes n-type source and drain implant regions  16  and  18  provided in the substrate  2 . A polysilicon gate region  20  of the second transistor  14  bridges the source and drain regions  16  and  18 . 
     A field oxide region  24  is provided in the substrate  2  separating region  8  of the first transistor  4  and region  16  of the second transistor  14 . The field oxide region  24  is provided to prevent field leakage between region  8  of the first transistor  4  and region  16  of the second transistor  14 . A polysilicon layer  26  overlies at least a portion of the field oxide region  24 . The polysilicon region  26  extends to serve as the gate region for other transistors (not shown) in the array, as do polysilicon regions  10  and  20 . 
     A dielectric region  22  surrounds at least a portion of the polysilicon gate regions  10  and  20  and overlies the polysilicon region  26 . The dielectric layer  22  can be composed of silicon dioxide, phosphorous silicate glass (PSG), tetraethyl orthosilicate (TEOS), borophosphorous tetraethyl orthosilicate (BPTEOS), or a combination of these materials. Although not shown, other layers of materials are applied above the dielectric layer  22  to complete fabrication of the array of transistors. For example, a metal layer can be provided above the dielectric layer  22  to provide an electrical connection to polysilicon gate regions  10 ,  20  and  26 . 
     The threshold of a transistor, or gate to source voltage required to turn on the transistor, can be controlled by increasing the distance between the source and drain regions. When a high threshold for a transistor is desired, such as 12 volts or higher, leakage current beneath the field oxide region separating two transistors can significantly affect how wide the separation between source and drain regions of a transistor needs to be for a desired threshold. To prevent increased separation between source and drain regions of a transistor with leakage current beneath the field oxide region, the width of the field oxide region separating source and drain regions of two transistors can be increased. 
     Current leakage beneath the field oxide region can result when H +  or Na +  ions from layers deposited above the field oxide region penetrate into the field oxide region. The H+ or Na+ ions in the field oxide layer cause a migration of ions from the p-substrate underlying the field oxide region so that the p-substrate inverts and effectively acts like an n-type substrate. With inversion of the p-substrate beneath the field oxide region, significant current leakage between source and gate regions, such as regions  8  and  16  of FIG. 1, can result. 
     For a large array of transistors where it is typically desirable to increase the density of transistors in a given area, increasing the distance between source and drain regions of transistors, or increasing the width of the field oxide regions to overcome the effects of current leakage beneath the field oxide region is undesirable. Further, when high threshold voltages are desired, charge pump circuitry is typically used to pump voltage above a 5V Vcc input pin to 12 volts or higher to turn on particular transistors. With significant current leakage, charge pump circuitry provided on the chip must be increased in size to supply necessary voltages. 
     It is, thus, desirable to take steps to reduce leakage current beneath the field oxide region separating transistors in an array. 
     SUMMARY OF THE INVENTION 
     The present invention includes a nitride layer deposited over the field oxide region separating transistors in an array to reduce field leakage current. The nitride layer has a dense lattice, effectively blocking H+ and Na+ penetration from overlying layers into the field oxide. With ions such as H+ and Na+ not penetrating into the field oxide layer to cause the underlying p-substrate to become inverted and act like an n-type substrate, leakage current between source and drain regions of transistors separated by the field oxide layer is reduced. With such a nitride layer, transistors can be created with a desired threshold while maintaining a limited distance between source and drain regions of the transistor and a limited field oxide layer width. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Further details of the present invention are explained with the help of the attached drawings in which: 
     FIG. 1 shows a cross section of two transistors of the prior art illustrating the typical configuration of materials used in the manufacture of an array of transistors; 
     FIG. 2 shows a cross section of a portion of a transistor array showing a nitride layer of the present invention; and 
     FIG. 3 shows data from experiments comparing the threshold voltage of a conventional transistor and a transistor manufactured with the nitride layer to increase threshold voltage. 
    
    
     DETAILED DESCRIPTION 
     FIG. 2 shows a cross section of a portion of a transistor array showing a nitride layer of the present invention as used to reduce field leakage current. In FIG. 2, the nitride layer  212  is shown deposited above the field oxide region  204  which separates two transistors, a first one of the transistors having a source or drain region  220 , and a second one of the transistors having a source or drain region  222 . The nitride layer further overlies a polysilicon gate  208  overlying the field oxide layer  204 . On top of the nitride layer  212 , a layer of dielectric material  216 , such as TEOS or other dielectric material is deposited. 
     The nitride layer of the invention includes any type of nitride which acts as a dielectric. An example of such a dielectric nitride is silicon nitride. However, other types of dielectric nitrides known in the art can be used according to this invention. 
     Chemical vapor deposition (CVD) is used as a process to deposit the nitride layer. The nitride layer thickness can range from about 100 Å to about 250 Å, and preferably from about 150 Å to about 200 Å, or more preferably about 180 Å in thickness. 
     The nitride layer can cover the entire semiconductor device, or it can be selectively deposited or etched to provide selective nitride coverage. 
     With transistors separated by a field oxide region without an overlying nitride layer having a threshold voltage set to approximately 12 volts, transistors separated by a field oxide region with an overlying nitride layer can have a threshold increasing to 15 volts without increasing transistor source and drain separation and without increasing the width of the field oxide region. With the nitride layer, a 100-fold reduction in leakage current can be provided. 
     FIG. 3 shows the threshold voltage of a field effect transistors for current leakage plotted against the cumulative probability of the value of the threshold for transistors with and without a layer. A cumulative probability of 0.5 represents the mean value of the data, and the negative and positive 95% confidence limits are represented by the 0.05 and 0.95 points, respectively. 
     Transistors without the CVD nitride layer (O) showed consistent voltages of around 12.5 volts to threshold, with the 95% confidence limits of about ±1V. In contrast, the transistors with the CVD nitride layer () had a threshold voltage of about 15.5 volts, with a 95% confidence limit of about 0.5 V. Thus, the increase in threshold voltage was about 3 V, which represents about a 100-fold decrease in current leakage. 
     Nitride is known to have a denser lattice structure, and one possible theory to account for the efficacy of the nitride layer in decreasing current leakage is that the layer can effectively block the H +  and Na +  from penetrating into the field oxide layer from the dielectric layer above, thereby preventing device degradation due to charge infiltration into the field oxide layer. However, other theories may explain the phenomenon and the invention does not rely upon any particular theory for its operability. 
     Although the invention has been described above with particularity, this was merely to teach one of ordinary skill in the art how to make and use the invention. Many modifications will fall within the scope of the invention, as that scope is defined by the claims which follow.