Patent Publication Number: US-10320401-B2

Title: Dual-path digital-to-time converter

Description:
TECHNICAL FIELD 
     Examples of the present disclosure generally relate to electronic circuits and, in particular, to a dual-path digital-to-time converter (DTC). 
     BACKGROUND 
     Digital phase-locked loops (DPLLs) are becoming attractive as replacements for analog PLLs in frequency synthesizers due to their technology portability, loop bandwidth configurability, and overall silicon area consumption. Moreover, among frequency synthesizers, those capable of fractional-N multiplication are preferred due to relaxed system level planning, such as input reference frequency and synthesized output frequency. However, several issues regarding quantization noise and non-linearity, which leads to spurious generation, limit the use of DPLLs in various applications. 
     On issue with fractional operation is when near-integer channels are desired, where unfiltered spurious tones can fall within the PLL loop bandwidth. The source of the more significant spurious tones is in the phase detector. Historically, in a DPLL, the fractional phase detector is implemented by a time-to-digital converter (TDC) that is capable of quantizing the phase difference between the input and output signals by inverter elements (delay). The limited resolution and non-linearity of the inverter elements in the TDC can produce prohibiting spurious tones. 
     Recently, the resolution of the phase detection has been improved by the use of a digital-to-time converter (DTC) that delays one of the signals (either input or output frequency) with much more accuracy. However, a conventional DTC is applied to only one of the signals, requiring the use of very complex calibration logic with potential large area and power consumption to avoid spurious tone generation. Even then, noise on the power supply and dynamic mismatches cannot be calibrated easily and very often the phase measurement results are worse than simulated. 
     SUMMARY 
     In an example, a digital-to-time converter (DTC) includes: a delay chain circuit having a plurality of delay cells coupled in sequence, the delay chain circuit including a first input to receive a first clock signal and a second input to receive a second clock signal; and a dynamic element matching (DEM) controller coupled to the delay chain circuit to provide a plurality of control signals to the plurality of delay cells, respectively. 
     In another example, a digital phase-locked loop (DPLL) includes: a digitally controlled oscillator (DCO) configured to generate a clock signal; and a digital-to-time converter (DTC) having first input coupled to an output of the DCO and a second input configured to receive a reference clock signal. The DTC includes: a delay chain circuit having a plurality of delay cells coupled in sequence, the delay chain circuit including a first input to receive the reference clock signal and a second input to receive the clock signal; and a DEM controller coupled to the delay chain circuit to provide a plurality of control signals to the plurality of delay cells, respectively. 
     In another example, a method of digital-to-time conversion includes: coupling a first clock signal to a first delay path and a second clock signal to a second delay path, each of the first and second delay paths implemented by a delay chain circuit having a plurality of delay cells coupled in sequence; providing a plurality of control signals to the plurality of delay cells to adjust delay of the first delay path with respect to the second delay path. 
     These and other aspects may be understood with reference to the following detailed description. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       So that the manner in which the above recited features can be understood in detail, a more particular description, briefly summarized above, may be had by reference to example implementations, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical example implementations and are therefore not to be considered limiting of its scope. 
         FIG. 1A  is a block diagram depicting a digital phase-locked loop (DPLL) according to an example. 
         FIG. 1B  is a block diagram depicting a DPLL according to another example. 
         FIG. 2A  is a graph illustrating a transfer function of a single-path DTC. 
         FIG. 2B  is a graph illustrating a transfer function of a dual-path DTC. 
         FIG. 3  is a block diagram depicting a DTC according to an example. 
         FIG. 4  is a block diagram depicting delay cells of a DTC according to an example. 
         FIGS. 5A-5C  depict block diagrams of a delay cell according to different examples. 
         FIGS. 6A-B  are schematic diagrams depicting multiplexers according to examples. 
         FIG. 7A-B  are schematic diagrams depicting delay circuits according to examples. 
         FIG. 8  is a block diagram depicting a DTC according to another example. 
         FIG. 9  is a block diagram depicting a field programmable gate array (FPGA) in which a dual-path DTC described herein can be used. 
     
    
    
     To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements of one example may be beneficially incorporated in other examples. 
     DETAILED DESCRIPTION 
     Various features are described hereinafter with reference to the figures. It should be noted that the figures may or may not be drawn to scale and that the elements of similar structures or functions are represented by like reference numerals throughout the figures. It should be noted that the figures are only intended to facilitate the description of the features. They are not intended as an exhaustive description of the claimed invention or as a limitation on the scope of the claimed invention. In addition, an illustrated example need not have all the aspects or advantages shown. An aspect or an advantage described in conjunction with a particular example is not necessarily limited to that example and can be practiced in any other examples even if not so illustrated or if not so explicitly described. 
     Techniques for providing a dual-path digital-to-time converter (DTC) are described. In an example, the DTC includes a delay chain circuit having a plurality of delay cells coupled in sequence. The delay chain circuit includes a first input to receive a reference clock signal and a second input to receive a synthesized high-frequency clock signal. The DTC further includes a dynamic element matching (DEM) controller coupled to the delay chain circuit to provide a plurality of control signals to the plurality of delay cells, respectively. The delay chain provides a fast path and a slow path, which is digitally selected by the control signals. These and other aspects can be understood with reference to the following description and the drawings. 
       FIG. 1A  is a block diagram depicting a digital phase-locked loop (DPLL)  100 A according to an example. The DPLL  100 A includes a digital-to-time converter (DTC)  102 , a loop filter  104 , a digitally controlled oscillator (DCO)  106 , and a divider  108 . A first input of the DTC  102  receives a reference clock signal (Φ R ), a second input of the DTC  102  is coupled to an output of the divider  108 , and a third input of the DTC  102  receives a digital signal (α). An output of the DTC  102  is coupled to an input of the loop filter  104 . An output of the loop filter  104  is coupled to an input of the DCO  106 . An output of the DCO  106  is coupled to a first input of the divider  108 . A second input of the divider  108  receives a digital signal (N). The digital signals α and N each have a width of multiple bits and the codes provided thereby are referred to as α and N, respectively. 
     In operation, the DCO  106  generates a clock signal (Φ V ). The divider  108  divides the clock signal Φ V  by the code N. The DTC  102  is a dual-path DTC that applies slightly different delays to the reference clock signal Φ R  and the divided clock signal Φ V  based on the code α. The DTC  102  provides a relative delay between the two input signals (Φ R  and divided Φ V ), rather than an absolute delay to one signal. The relative delay can be positive or negative, as described further below. The DTC  102  avoids code-dependent non-linearity, since the same total delay is implemented independent of the desired output delay, centered at mid-point, exploiting symmetry with respect to the center of the code α. The DTC  102  outputs a digital signal Φ E  representing a phase error. The loop filter  104  filters the digital signal Φ E  and generates an digital signal OTW. The digital signal OTW controls the oscillation frequency of the DCO  106  and thus the frequency of the clock signal Φ V . 
       FIG. 1B  is block diagram depicting a DPLL  100 B according to another example. The DPLL  100 B includes an accumulator  110 , an adder  109 , a loop filter  112 , a DCO  116 , the DTC  102 , and an accumulator  114 . An input of the accumulator  110  receives a digital signal FCW. An output of the accumulator  110  is coupled to a first input of the adder  109 . A second input of the adder  109  is coupled to an output of the accumulator  114 . A third input of the adder  109  is coupled to an output of the DTC  102 . An output of the adder  109  is coupled to an input of the loop filter  112 . An output of the loop filter  112  is coupled to an input of the DCO  116 . An output of the DCO  116  is coupled to a first input of the DTC  102 . A second input of the DTC receives the reference clock signal Φ R . The output of the DCO  116  is also coupled to a clock input of the accumulator  114 . Another input of the accumulator  114  receives a digital signal providing a value of “1.” 
     In operation, the DCO  106  generates a clock signal Φ V . The DTC  102  is a dual-path DTC that operates as described above based on the reference clock signal Φ R  and the clock signal Φ V  to generate a digital signal Φ E   _   FRAC . The accumulator  110  accumulates a code FCW every clock cycle. The adder  109  computes FCW−R V −Φ E   _   FRAC  and outputs a digital signal Φ E . The loop filter  112  filters the digital signal Φ E  and generates a digital signal OTW, which controls the oscillation frequency of the DCO  116 . The accumulator  114  operates as a counter that increments based on the clock signal Φ V . The accumulator  114  outputs a digital signal R V , which includes the accumulated value of the accumulator  114 . Thus, the DTC  102  can be used in both a divider-based DPLL (e.g., the DPLL  100 A) or a counter-based DPLL (e.g., the DPLL  100 B). 
     An advantage of the DTC  102  is a transfer function centered at the origin.  FIG. 2A  is a graph illustrating a transfer function  202  of a single-path DTC, which provides an absolute delay to one of the input clock signals. The x-axis represents DTC code and the y-axis represents the relative delay added between first input and second input, respectively. The transfer function  202  includes a non-zero y-intercept. Further, supply noise can alter the slope of the transfer function in either a positive or negative direction. The single-path DTC is strongly dependent on power supply noise, suffering from power supply jitter injection. 
       FIG. 2B  is a graph illustrating a transfer function  204  of the dual-path DTC  102 . The x-axis represents DTC code and the y-axis represents the converter time at the output. The transfer function  204  passes through the origin. The symmetry of the transfer function  204  about the origin reduces the effect of power supply noise on the output. In the DTC  102 , the relative delay, with respect to supply noise, is very small, since the noise affects both input clock signals equally. 
       FIG. 3  is a block diagram depicting a DTC  300  according to an example. The DTC  300  includes a dual-path delay chain  301  and control circuitry  350 . The dual-path delay chain  301  includes delay cells  302   1  . . .  302   M  (generally referred to as delay cells  302  or a delay cell  302 ). Inputs of the delay cell  302   M  receive a reference clock signal F ref  and a DCO output signal F DCO . The delay cells  302   M  . . .  302   1  successively coupled output-to-input. Outputs of the delay cell  302   1  can be coupled to inputs of a binary phase detector (BPD)  304 . The control circuitry  350  includes a binary phase detector (BPD)  304 , an accumulator  306 , a calibration circuit  308 , and a dynamic element matching (DEM) controller  310 . Outputs of the delay cell  302   1  are coupled to inputs of the BPD  304 . An output of the BPD  304  is coupled to an input of the accumulator  306 . An output of the accumulator  306  is coupled to a first input of the calibration circuit  308 . A second input of the calibration circuit  308  receives a digital signal S CTRL . An output of the calibration circuit  308  is coupled to an input of the DEM controller  310 . Outputs of the DEM controller  310  are coupled to additional inputs of the delay cells  302   M  . . .  302   1 , respectively. 
     The DTC  300  can be used as the DTC  102  in the DPLL  100 A or the DPLL  100 B, described above. In such case, F ref  is the signal Φ R , F DCO  is the divided clock signal Φ V  or the clock signal Φ V , S CTRL  is the signal α, and BB_out is Φ E  or Φ E   _   FRAC . The DTC  300  can also be used in other types of DPLLs, such as digital-to-analog converter (DAC)-based DPLLs. 
     In operation, the clock signal F ref  traverses a first path  305   1  through the delay cells  302  (referred to as the “reference path”) and the clock signal F DCO  traverses a second path  3052  through the delay cells  302  (referred to as the “DCO path”). Each of the delay cells  302  has one of two states: (1) in a first state, a fast delay is added to the reference path and a slow delay is added to the DCO path; or (2) in a second state, a slow delay is added to the reference path and a fast delay is added to the DCO path. The state of each delay cell  302  is determined by a logic signal output by the DEM controller  310 . The DEM controller  310  can set n of the delay cells  302  in the first state, resulting in M-n of the delay cells  302  being in the second state, where n is between zero and M inclusive. The delay chain  301  reduces mismatches and noise that intrinsically affect the delay cells  302 , forcing the input clock signals to experience similar delay modulation towards a more robust relative time difference (Δt) between them. The modulation of the delay difference, required for fractional-N operation to match the actual input phase difference, in opposite direction, is defined by the number of fast/slow delays that each of the input clock signals go through. The absolute delays applied to each of the input clock signals are not relevant, affecting only the maximum reference frequency. The time difference at the output of the delay chain  301 , if a correct DTC gain is provided, will be always within the DTC resolution defined by the difference between the reference and DCO paths (e.g., in the range of tens of femto-seconds). 
     The output of the delay chain  301  is coupled to the BPD  304 , which can operate as a bang-bang phase detector to produce a digital signal BB_out. The accumulator  306  operates to accumulate the output of the BPD  304 . The calibration circuit  308  receives both the output of the accumulator  306  and the signal S CTRL . The signal S CTRL  sets a selected time difference between the input clock signals. For example, the signal S CTRL  can be set to drive the time difference between the clock signals towards zero. The calibration circuit  308  monitors the accumulated output of the BPD  304  and adjusts the S CTRL  signal to compensate for supply noise and mismatches in the delay chain  301 . The DEM controller  310  can be a thermometer decoder or the like that generates the individual control signals for the delay cells  302 . 
       FIG. 4  is a block diagram depicting the delay cells  302  of the DTC  300  according to an example. The delay cells  302   M  . . .  302   1  include delay circuits  402   M  . . .  402   1 , respectively (generally referred to as delay circuits  402  or a delay circuit  402 ). The delay cells  302   M  . . .  302   1  also include delay circuits  404   M  . . .  404   1 , respectively (generally referred to as delay circuits  404  or a delay circuit  404 ). Each delay circuit  402  provides a time delay of τ 0 , and each delay circuit  404  provides a time delay of τ 1 , where to is less than τ 1  (i.e., to is the fast delay and τ 1  is the slow delay). The delay circuits  402   M  . . .  402   1  also include time delays σ M  . . . σ 1 , respectively, which represent the non-linearity associated therewith. Likewise, the delay circuits  404   M  . . .  404   1  also include time delays ε M  . . . ε 1 , respectively, which represent the non-linearity associated therewith. The delay circuits  402   M  . . .  402   1  also include time delays χ M  . . . χ 1 , respectively, which represent the uncorrelated noise associated therewith. The delay circuits  404   M  . . .  404   1  also include time delays ψ M  . . . ψ 1 , respectively, which represent the uncorrelated noise associated therewith. As supply voltage V DD  is coupled to each of the delay cells  302 . 
     Considering the architecture of  FIG. 4 , the time delays that both input clock signals will experience based on a control code S (where S is an integer) can be expressed as: 
               T   REF     =         ∑     i   =     S   +   1       M     ⁢     τ   0       +     σ   i     +     χ   i     +       ∑     k   =   0     S     ⁢     τ   1       +     ɛ   k     +     ψ   k                     T   DCO     =         ∑     i   =   0     S     ⁢     τ   0       +     σ   i     +     χ   i     +       ∑     k   =     S   +   1       M     ⁢     τ   1       +     ɛ   k     +     ψ   k             
where T REF  is the total time delay provided by the reference path and T DCO  is the total delay provided by the DCO path. The time-difference of the output of the delay chain  301  is:
 
               Δ   t     =       T   REF     -     T   DCO                     Δ   t     =         (     M   -     2   ·   S       )     ·     (       τ   0     -     τ   1       )       +       ∑     i   =     S   +   1       M     ⁢     (       σ   i     +     χ   i       )       -     (       ɛ   i     +     ψ   i       )     +       ∑     k   =   0     S     ⁢     (       ɛ   k     +     ψ   k       )       -     (       σ   k     +     χ   k       )             
where S is an integer between 0 and M.
 
       FIG. 5A  is a block diagram depicting a delay cell  302  according to an example. The delay cell  302  includes a multiplexer  502 , a fast delay circuit  402 , a slow delay circuit  404 , and a multiplexer  504 . The multiplexer  502  includes inputs IN  1  and IN 2  and outputs coupled to the fast delay  402  and the slow delay  404 , respectively. The multiplexer  504  includes inputs coupled to outputs of the fast delay  402  and the slow delay  404 , respectively. The multiplexer  504  includes outputs OUT  1  and OUT  2 . The multiplexers  502  and  504  have inputs that receive a given control signal S. In operation, the multiplexers  502  and  504  direct the input IN  1  to the output OUT  1  and the input IN  2  to the output OUT  2 . The multiplexers  502  and  504  direct the input IN  1  through either the fast delay  402  or the slow delay  404 , while directing the input IN  2  through either the slow delay  404  or the fast delay  402 , respectively, based on the value of S. The multiplexers  502  and  504  can be implemented in different ways. It is desirable, however, that the paths are symmetric as possible, reducing the mismatch between the paths. 
       FIG. 5B  is a block diagram depicting a delay cell  302 A according to another example. The delay cell  302 A is an alternative implementation of the delay cell  302  described above in  FIG. 5A . In the delay cell  302 A, the multiplexer  504  is omitted.  FIG. 5C  is a block diagram depicting a delay cell  302 B according to yet another example. The delay cell  302 B is an alternative implementation of the delay cell  302  described above in  FIG. 5A . In the delay cell  302 B, the multiplexer  502  is omitted. Thus, the delay cell  302  described above can be implemented with both input and output multiplexers ( FIG. 5A ), only an input multiplexer ( FIG. 5B ), or only an output multiplexer ( FIG. 5C ). In cases of only a single multiplexer in each delay cell  302 , the BPD  304  can receive a signal from the DEM controller  310  indicating the parity of the number of “flips” performed by the delay cells  302 . If there were an odd number of flips (odd parity), then the BPD  304  can invert its output. If there were an even number of flips (even parity), then the BPD  304  does not invert its output. 
       FIG. 6A  is a schematic diagram depicting a multiplexer  600 A according to an example. The multiplexer  600 A can implement the multiplexers  502  and  504  of each delay cell  302 . The multiplexer  600 A includes transmission gates  602 ,  604 ,  606 , and  608 . Inputs of the transmission gates  604  and  608  are coupled to a first input I 1 , and inputs of the transmission gates  602  and  606  are coupled to a second input I 2 . Outputs of the transmission gates  602  and  604  are coupled to an output O 1 , and outputs of the transmission gates  606  and  608  are coupled to an output O 2 . The control signal S is coupled to true control terminals of the transmission gates  602  and  608 , and complement control terminals of the transmission gates  604  and  606 . A complement of the control signal S is coupled to complement control terminals of the transmission gates  602  and  608 , and true control terminals of the transmission gates  604  and  606 . Use of the transmission gates  602  . . .  608  guarantees equal delay and load to both reference and DCO paths. The inner transmission gates  604  and  606  are active for S=0, and the output transmission gates  602  and  608  are active for S=1. 
       FIG. 7A  is a schematic diagram depicting a delay circuit  700 A according to an example. The delay circuit  700 A can implement the fast delay circuit  402  or the slow delay circuit  404 . The delay circuit  700 A includes an inverter  702 , a switched capacitor array  704 , and an inverter  706 . An input of the inverter  702  is coupled to an input IN. An output of the inverter  702  is coupled to the switched capacitor array  704 . An input of the inverter  706  is coupled to the switched capacitor array  704 . An output of the inverter  706  is coupled to an output OUT. The switched capacitor array  704  is coupled between the inverters  702  and  706 . In operation, the inverter  702  provides signal recovery, as well as buffering and isolation from the transmission gates of the input multiplexer. The inverter  706  provides buffering and isolation of the transmission gates of the output multiplexer. The switched capacitor array  704  includes a plurality of metal oxide semiconductor (MOS) capacitors  710   1  . . .  710   N  (where N is an integer greater than one) and a plurality of inverters  708   1  . . .  708   N . Outputs of the inverters  708  are coupled to first terminals of the MOS capacitors  710 . Second terminals of the MOS capacitors  710  are coupled to the node between the inverters  702  and  706 . Inputs of the inverters  708  receive control signals P N  . . . P 1  that determine the overall capacitance of the switched capacitor array  704 . The signals P N  . . . P 1  can be generated by the DEM controller  310 . The delay is given by Gm/C, where Gm is the transconductance of the inverter  702  and C is the capacitance of switched capacitor array  704 . To implement the fast delay, the control signals P N  . . . P 1  can control all MOS capacitors OFF to provide minimum capacitance. To implement the slow delay, the control signals P N  . . . P 1  can control one or more of the MOS capacitors to be ON to provide a particular capacitance that can be determined based on PVT conditions. 
       FIGS. 6A-7A  show one example of a multiplexer  600 A and delay circuit  700 A that can be used in the delay chain  301  of the DTC  300 . In another example, the transmission gates  602  . . .  608  can be replaced with three-state inverters.  FIG. 6B  shows a multiplexer  600 B having three-state inverters  610  . . .  616  that replace the transmission gates  602  . . .  608 .  FIG. 7B  shows a delay circuit  700 B, where the inverters  702  and  706  in the delay cell are omitted. In still another example, the inverters  702  and  706  can be disposed on the opposite sides of the respective input and output multiplexers. That is, the inverter  702  can be disposed at the input side of the input multiplexer, and the inverter  706  can be disposed at the output side of the output multiplexer. 
       FIG. 8  is a block diagram depicting a DTC  800  according to another example. In the present example, the delay chain of the DTC  800  is divided into separate delay chains  802   1 ,  802   2 , and  802   3 . Likewise, the DEM controller is divided into separate DEM controllers  806   1 ,  806   2 , and  806   3 . Likewise, the calibration circuit is divided into separate calibration circuits  808   1 ,  808   2 , and  808   3 . The output of the delay chain  802   1  is coupled to the input of the delay chain  802   2  and to an input of an accumulator  804   1 . An output of the accumulator  804   1  is coupled to an input of the calibration circuit  808   1 . An output of the calibration circuit  808   1  is coupled to an input of the DEM controller  806   1 . The output of the delay chain  802   2  is coupled to the input of the delay chain  802   3  and to an input of the accumulator  804   2 . An output of the accumulator  804   2  is coupled to an input of the calibration circuit  808   2 . An output of the calibration circuit  808   2  is coupled to an input of the DEM controller  806   2 . The output of the delay chain  802   3  is coupled to an input of an accumulator  804   3 . An output of the accumulator  804   3  is coupled to an input of the calibration circuit  808   3 . An output of the calibration circuit  808   3  is coupled to an input of the DEM controller  806   3 . Inputs of the calibration circuits  808   1 ,  808   2 , and  808   3  receive coarse, mid-coarse, and fine control signals. 
     In the present example, the dual-path DTC is segmented into unit-weighted blocks with different resolutions. Due to the fact that the dual-path DTC operates by centering the signal edges towards alignment, the input range of each segment is +/−0.5 least significant bit (LSB) of the previous segment, reducing exponentially the number of elements. A large dynamic range and ultra-fin resolution can be obtained with a fraction of the number of units. 
     The dual-path DTC described in the examples above can be implemented within an integrated circuit, such as a field programmable gate array (FPGA) or like type programmable circuit.  FIG. 9  illustrates an architecture of FPGA  900  that includes a large number of different programmable tiles including multi-gigabit transceivers (“MGTs”)  1 , configurable logic blocks (“CLBs”)  2 , random access memory blocks (“BRAMs”)  3 , input/output blocks (“IOBs”)  4 , configuration and clocking logic (“CONFIG/CLOCKS”)  5 , digital signal processing blocks (“DSPs”)  6 , specialized input/output blocks (“I/O”)  7  (e.g., configuration ports and clock ports), and other programmable logic  8  such as digital clock managers, analog-to-digital converters, system monitoring logic, and so forth. Some FPGAs also include dedicated processor blocks (“PROC”)  10 . FPGA  900  can include one or more instances of a dual-path DTC  902 , which can be constructed according to any example above. 
     In some FPGAs, each programmable tile can include at least one programmable interconnect element (“INT”)  11  having connections to input and output terminals  20  of a programmable logic element within the same tile, as shown by examples included at the top of  FIG. 9 . Each programmable interconnect element  11  can also include connections to interconnect segments  22  of adjacent programmable interconnect element(s) in the same tile or other tile(s). Each programmable interconnect element  11  can also include connections to interconnect segments  24  of general routing resources between logic blocks (not shown). The general routing resources can include routing channels between logic blocks (not shown) comprising tracks of interconnect segments (e.g., interconnect segments  24 ) and switch blocks (not shown) for connecting interconnect segments. The interconnect segments of the general routing resources (e.g., interconnect segments  24 ) can span one or more logic blocks. The programmable interconnect elements  11  taken together with the general routing resources implement a programmable interconnect structure (“programmable interconnect”) for the illustrated FPGA. 
     In an example implementation, a CLB  2  can include a configurable logic element (“CLE”)  12  that can be programmed to implement user logic plus a single programmable interconnect element (“INT”)  11 . A BRAM  3  can include a BRAM logic element (“BRL”)  13  in addition to one or more programmable interconnect elements. Typically, the number of interconnect elements included in a tile depends on the height of the tile. In the pictured example, a BRAM tile has the same height as five CLBs, but other numbers (e.g., four) can also be used. A DSP tile  6  can include a DSP logic element (“DSPL”)  14  in addition to an appropriate number of programmable interconnect elements. An IOB  4  can include, for example, two instances of an input/output logic element (“IOL”)  15  in addition to one instance of the programmable interconnect element  11 . As will be clear to those of skill in the art, the actual I/O pads connected, for example, to the I/O logic element  15  typically are not confined to the area of the input/output logic element  15 . 
     In the pictured example, a horizontal area near the center of the die (shown in  FIG. 9 ) is used for configuration, clock, and other control logic. Vertical columns  9  extending from this horizontal area or column are used to distribute the clocks and configuration signals across the breadth of the FPGA. 
     Some FPGAs utilizing the architecture illustrated in  FIG. 9  include additional logic blocks that disrupt the regular columnar structure making up a large part of the FPGA. The additional logic blocks can be programmable blocks and/or dedicated logic. For example, processor block  10  spans several columns of CLBs and BRAMs. The processor block  10  can various components ranging from a single microprocessor to a complete programmable processing system of microprocessor(s), memory controllers, peripherals, and the like. 
     Note that  FIG. 9  is intended to illustrate only an exemplary FPGA architecture. For example, the numbers of logic blocks in a row, the relative width of the rows, the number and order of rows, the types of logic blocks included in the rows, the relative sizes of the logic blocks, and the interconnect/logic implementations included at the top of  FIG. 9  are purely exemplary. For example, in an actual FPGA more than one adjacent row of CLBs is typically included wherever the CLBs appear, to facilitate the efficient implementation of user logic, but the number of adjacent CLB rows varies with the overall size of the FPGA. 
     While the foregoing is directed to specific examples, other and further examples may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.