Patent Publication Number: US-9837968-B2

Title: Amplifier circuits

Description:
CROSS-REFERENCES TO RELATED APPLICATIONS 
     The present application is a continuation patent application of U.S. patent application Ser. No. 13/656,904, filed Oct. 22, 2012, entitled “Amplifiers with noise splitting,” which is incorporated herein by reference in its entirety. 
    
    
     BACKGROUND 
     I. Field 
     The present disclosure relates generally to electronics, and more specifically to amplifiers. 
     II. Background 
     A wireless device (e.g., a cellular phone or a smartphone) in a wireless communication system may transmit and receive data for two-way communication. The wireless device may include a transmitter for data transmission and a receiver for data reception. For data transmission, the transmitter may modulate a radio frequency (RF) carrier signal with data to obtain a modulated RF signal, amplify the modulated RF signal to obtain an amplified RF signal having the proper output power level, and transmit the amplified RF signal via an antenna to a base station. For data reception, the receiver may obtain a received RF signal via the antenna and may amplify and process the received RF signal to recover data sent by the base station. 
     A wireless device may support carrier aggregation, which is simultaneous operation on multiple carriers. A carrier may refer to a range of frequencies used for communication and may be associated with certain characteristics. For example, a carrier may be associated with system information describing operation on the carrier. A carrier may also be referred to as a component carrier (CC), a frequency channel, a cell, etc. It is desirable to efficiently support carrier aggregation by the wireless device. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  shows a wireless device communicating with a wireless system. 
         FIGS. 2A to 2D  show four examples of carrier aggregation (CA). 
         FIG. 3  shows a block diagram of the wireless device in  FIG. 1 . 
         FIG. 4  shows a single-input multiple-output (SIMO) low noise amplifier (LNA) without noise splitting. 
         FIG. 5  shows a SIMO LNA with noise splitting at current buffer output. 
         FIGS. 6A to 7C  show some exemplary designs of the SIMO LNA with noise splitting at current buffer output. 
         FIG. 8  shows a SIMO LNA with noise splitting at gain circuit output. 
         FIGS. 9A to 9C  show some exemplary designs of the SIMO LNA with noise splitting at gain circuit output. 
         FIG. 10  shows a process for performing signal amplification. 
     
    
    
     DETAILED DESCRIPTION 
     The detailed description set forth below is intended as a description of exemplary designs of the present disclosure and is not intended to represent the only designs in which the present disclosure can be practiced. The term “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any design described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other designs. The detailed description includes specific details for the purpose of providing a thorough understanding of the exemplary designs of the present disclosure. It will be apparent to those skilled in the art that the exemplary designs described herein may be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form in order to avoid obscuring the novelty of the exemplary designs presented herein. 
     Amplifier with noise splitting and having good performance and other desirable characteristics are disclosed herein. These amplifiers may include SIMO LNAs supporting simultaneous reception of multiple transmitted signals. These amplifiers may be used for various types of electronic devices such as wireless communication devices. 
       FIG. 1  shows a wireless device  110  communicating with a wireless communication system  120 . Wireless system  120  may be a Long Term Evolution (LTE) system, a Code Division Multiple Access (CDMA) system, a Global System for Mobile Communications (GSM) system, a wireless local area network (WLAN) system, or some other wireless system. A CDMA system may implement Wideband CDMA (WCDMA), CDMA 1X, Evolution-Data Optimized (EVDO), Time Division Synchronous CDMA (TD-SCDMA), or some other version of CDMA. For simplicity,  FIG. 1  shows wireless system  120  including two base stations  130  and  132  and one system controller  140 . In general, a wireless system may include any number of base stations and any set of network entities. 
     Wireless device  110  may also be referred to as a user equipment (UE), a mobile station, a terminal, an access terminal, a subscriber unit, a station, etc. Wireless device  110  may be a cellular phone, a smartphone, a tablet, a wireless modem, a personal digital assistant (PDA), a handheld device, a laptop computer, a smartbook, a netbook, a cordless phone, a wireless local loop (WLL) station, a Bluetooth device, etc. Wireless device  110  may communicate with wireless system  120 . Wireless device  110  may also receive signals from broadcast stations (e.g., a broadcast station  134 ), signals from satellites (e.g., a satellite  150 ) in one or more global navigation satellite systems (GNSS), etc. Wireless device  110  may support one or more radio technologies for wireless communication such as LTE, WCDMA, CDMA 1X, EVDO, TD-SCDMA, GSM, 802.11, etc. 
     Wireless device  110  may support carrier aggregation, which is operation on multiple carriers. Carrier aggregation may also be referred to as multi-carrier operation. Wireless device  110  may be able to operate in low-band from 698 to 960 megahertz (MHz), mid-band from 1475 to 2170 MHz, and/or high-band from 2300 to 2690 and 3400 to 3800 MHz. Low-band, mid-band, and high-band refer to three groups of bands (or band groups), with each band group including a number of frequency bands (or simply, “bands”). Each band may cover up to 200 MHz and may include one or more carriers. Each carrier may cover up to 20 MHz in LTE. LTE Release 11 supports 35 bands, which are referred to as LTE/UMTS bands and are listed in 3GPP TS 36.101. Wireless device  110  may be configured with up to five carriers in one or two bands in LTE Release 11. 
     In general, carrier aggregation (CA) may be categorized into two types—intra-band CA and inter-band CA. Intra-band CA refers to operation on multiple carriers within the same band. Inter-band CA refers to operation on multiple carriers in different bands. 
       FIG. 2A  shows an example of contiguous intra-band CA. In the example shown in  FIG. 2A , wireless device  110  is configured with four contiguous carriers in one band in low-band. Wireless device  110  may send and/or receive transmissions on multiple contiguous carriers within the same band. 
       FIG. 2B  shows an example of non-contiguous intra-band CA. In the example shown in  FIG. 2B , wireless device  110  is configured with four non-contiguous carriers in one band in low-band. The carriers may be separated by 5 MHz, 10 MHz, or some other amount. Wireless device  110  may send and/or receive transmissions on multiple non-contiguous carriers within the same band. 
       FIG. 2C  shows an example of inter-band CA in the same band group. In the example shown in  FIG. 2C , wireless device  110  is configured with four carriers in two bands in low-band. Wireless device  110  may send and/or receive transmissions on multiple carriers in different bands in the same band group. 
       FIG. 2D  shows an example of inter-band CA in different band groups. In the example shown in  FIG. 2D , wireless device  110  is configured with four carriers in two bands in different band groups, which include two carriers in one band in low-band and two carriers in another band in mid-band. Wireless device  110  may send and/or receive transmissions on multiple carriers in different bands in different band groups. 
       FIGS. 2A to 2D  show four examples of carrier aggregation. Carrier aggregation may also be supported for other combinations of bands and band groups. 
       FIG. 3  shows a block diagram of an exemplary design of wireless device  110  in  FIG. 1 . In this exemplary design, wireless device  110  includes a transceiver  320  coupled to a primary antenna  310 , a transceiver  322  coupled to a secondary antenna  312 , and a data processor/controller  380 . Transceiver  320  includes multiple (K) receivers  330   pa  to  330   pk  and multiple (K) transmitters  350   pa  to  350   pk  to support multiple frequency bands, multiple radio technologies, carrier aggregation, etc. Transceiver  322  includes L receivers  330   sa  to  330   sl  and L transmitters  350   sa  to  350   sl  to support multiple frequency bands, multiple radio technologies, carrier aggregation, receive diversity, multiple-input multiple-output (MIMO) transmission from multiple transmit antennas to multiple receive antennas, etc. 
     In the exemplary design shown in  FIG. 3 , each receiver  330  includes an LNA  340  and receive circuits  342 . For data reception, antenna  310  receives signals from base stations and/or other transmitter stations and provides a received RF signal, which is routed through an antenna interface circuit  324  and presented as an input RF signal to a selected receiver. Antenna interface circuit  324  may include switches, duplexers, transmit filters, receive filters, matching circuits, etc. The description below assumes that receiver  330   pa  is the selected receiver. Within receiver  330   pa , an LNA  340   pa  amplifies the input RF signal and provides an output RF signal. Receive circuits  342   pa  downconvert the output RF signal from RF to baseband, amplify and filter the downconverted signal, and provide an analog input signal to data processor  380 . Receive circuits  342   pa  may include mixers, filters, amplifiers, matching circuits, an oscillator, a local oscillator (LO) generator, a phase locked loop (PLL), etc. Each remaining receiver  330  in transceivers  320  and  322  may operate in similar manner as receiver  330   pa.    
     In the exemplary design shown in  FIG. 3 , each transmitter  350  includes transmit circuits  352  and a power amplifier (PA)  354 . For data transmission, data processor  380  processes (e.g., encodes and modulates) data to be transmitted and provides an analog output signal to a selected transmitter. The description below assumes that transmitter  350   pa  is the selected transmitter. Within transmitter  350   pa , transmit circuits  352   pa  amplify, filter, and upconvert the analog output signal from baseband to RF and provide a modulated RF signal. Transmit circuits  352   pa  may include amplifiers, filters, mixers, matching circuits, an oscillator, an LO generator, a PLL, etc. A PA  354   pa  receives and amplifies the modulated RF signal and provides a transmit RF signal having the proper output power level. The transmit RF signal is routed through antenna interface circuit  324  and transmitted via antenna  310 . Each remaining transmitter  350  in transceivers  320  and  322  may operate in similar manner as transmitter  350   pa.    
       FIG. 3  shows an exemplary design of receiver  330  and transmitter  350 . A receiver and a transmitter may also include other circuits not shown in  FIG. 3 , such as filters, matching circuits, etc. All or a portion of transceivers  320  and  322  may be implemented on one or more analog integrated circuits (ICs), RF ICs (RFICs), mixed-signal ICs, etc. For example, LNAs  340 , and receive circuits  342  and may be implemented on one module, which may be an RFIC, etc. The circuits in transceivers  320  and  322  may also be implemented in other manners. 
     Data processor/controller  380  may perform various functions for wireless device  110 . For example, data processor  380  may perform processing for data being received via receivers  330  and data being transmitted via transmitters  350 . Controller  380  may control the operation of the various circuits within transceivers  320  and  322 . A memory  382  may store program codes and data for data processor/controller  380 . Data processor/controller  380  may be implemented on one or more application specific integrated circuits (ASICs) and/or other ICs. 
     Wireless device  110  may include one or more SIMO LNAs. A SIMO LNA includes a single input and multiple (M) outputs and can receive a single input RF signal at its input and provide up to M output RF signals from up to M outputs. A SIMO LNA may be used to simultaneously receive (i) multiple transmissions sent on multiple carriers in the same band for intra-band CA or (ii) multiple transmitted signals from different wireless systems (e.g., LTE and WCDMA). 
       FIG. 4  shows a block diagram of an exemplary design of a SIMO LNA  440  without noise splitting. SIMO LNA  440  includes multiple (M) amplifier circuits  450   a  to  450   m  coupled to M load circuits  490   a  to  490   m , respectively. The inputs of all M amplifier circuits  450   a  to  450   m  are coupled together. Each amplifier circuit  450  includes a gain circuit  460  coupled to a current buffer  470 . Each amplifier circuit  450  may be enabled by turning on its current buffer  470  via a respective Venb control signal. 
     An input RF signal (RFin) is applied to the M amplifier circuits  450   a  to  450   m . One or more amplifier circuits  450  may be enabled by turning on the associated current buffers  470 . For example, N amplifier circuits  450  may be enabled to concurrently receive transmissions on N sets of carriers in the same band for intra-band CA, where 1≦N≦M. Each set of carriers may include one or more carriers. Each enabled amplifier circuit  450  may amplify the input RF signal and provides an output RF signal to its load circuit  490 . 
     The N enabled amplifier circuits  450  in SIMO LNA  440  operate independently and have outputs that are separated from each other in order to provide isolation between different transmissions or signals being processed. Each gain circuit  460  outputs a signal current of i s  and a noise current of i n . The noise figure (NF) of each amplifier circuit  450  is dependent on the signal current and the noise current from the associated gain circuit  460 . Amplifier circuits  450  typically have worse noise figure when operating simultaneously as compare to one amplifier circuit  450  operating alone due to degradation of input matching or noise coupling between different amplifier circuits. 
     In an aspect of the present disclosure, a SIMO LNA with noise splitting may be used to support simultaneous reception of multiple transmissions or signals. Noise splitting refers to “splitting” of noise among multiple outputs such that each output observes less noise and can achieve a better/lower noise figure. 
       FIG. 5  shows a block diagram of an exemplary design of a SIMO LNA  540  with noise splitting at current buffer output. SIMO LNA  540  may be used for one or more LNAs  340  in  FIG. 3 . SIMO LNA  540  includes multiple (M) amplifier circuits  550   a  to  550   m  coupled to M load circuits  590   a  to  590   m , respectively. Each amplifier circuit  550  includes a gain circuit  560  coupled to a current buffer  570 . Each amplifier circuit  550  may be enabled by turning on its current buffer  570  via a respective Venb control signal. 
     In the exemplary design shown in  FIG. 5 , SIMO LNA  540  further includes interconnection circuits  580  coupled between the outputs of amplifier circuits  550 . Each interconnection circuit  580  may be implemented with a switch  582  (as shown in  FIG. 5 ) or with some other circuit. Each switch  582  may be (i) opened to isolate the two amplifier circuits  550  coupled to the switch or (ii) closed to connect the outputs of the two amplifier circuits  550  and sum the output currents from these amplifier circuits. 
     In general, any number of amplifier circuits  550  and any one of amplifier circuits  550  may be enabled at any given moment. Furthermore, any number of switches  582  and any one of switches  582  may be closed at any given moment. A given amplifier circuit  550  may drive its load circuit  590  by itself. Alternatively, multiple amplifier circuits  550  may have their outputs coupled together via their closed switches  582  and may collectively drive their load circuits  590 . The noise figures of amplifier circuits  550  having their outputs coupled together may be improved through noise splitting. 
     If all switches  582  are opened, then each amplifier circuit  550  may drive only its load circuit  590 . The output current provided by each amplifier circuit  550  to its load circuit  590  may be expressed as:
 
 i   m   =i   s,m   +i   n,m   Eq (1)
 
where i s,m  is a signal current from the m-th amplifier circuit  550 ,
 
     i n,m  is a noise current from the m-th amplifier circuit  550 , and 
     i m  is an output current from the m-th amplifier circuit  550 . 
     The noise power at each load circuit  590  may be expressed as:
 
 P   noise,m   ≈i   n,m   2   *R   load ,  Eq (2)
 
where R load  is an impedance of each load circuit  590 , and
 
     P noise,m  is the noise power at the m-th load circuit  590  without noise splitting. 
     If all switches  582  are closed, then the outputs of all M amplifier circuits  550   a  to  550   m  are shorted together at a summing node X. In this case, the total current i total  at the summing node may be expressed as: 
                           i   total     =       ⁢       (       i     s   ,   1       +     i     n   ,   1         )     +     (       i     s   ,   2       +     i     n   ,   2         )     +   …   +     (       i     s   ,   M       +     i     n   ,   M         )                   ≈       ⁢       M   *     i   s       +     (       i     n   ,   1       +     i     n   ,   2       +   …   +     i     n   ,   M         )                     Eq   ⁢           ⁢     (   3   )                 
where i s  is an average signal current from each amplifier circuit  550 , and
 
     i total  is a total current from all M amplifier circuits  550   a  to  550   m.    
     The signal currents i s,1  to i s,M  from the M amplifier circuits  550   a  to  550   m  (or more specifically, from M gain circuits  560   a  to  560   m ) should be similar since they are generated based on the same input RF signal, which is applied to all M amplifier circuits  550 . Hence, the total signal current may be approximately equal to M*i s . The noise currents i n,1  to i n,M  from the M amplifier circuits  550   a  to  550   m  should be uncorrelated. Hence, the total noise current is equal to the sum of the noise currents from the M amplifier circuits  550   a  to  550   m.    
     The total current at the summing node may be split and provided to the M load circuits  590   a  to  590   m . The current received by each load circuit  590  may be expressed as: 
                       i   load     =         i   total     M     ≈       i   d     +       (       i     n   ,   1       +     i     n   ,   2       +   …   +     i     n   ,   M         )     M           ,           Eq   ⁢           ⁢     (   4   )                 
where i load  is a load current provided to each load circuit  590 .
 
     The noise currents from the M amplifier circuits  550   a  to  550   m  should be uncorrelated and may add constructively or destructively. Hence, the noise power at each load circuit  590  may be expressed as: 
     
       
         
           
             
               
                 
                   
                     
                       P 
                       noise 
                     
                     ≈ 
                     
                       
                         
                           i 
                           n 
                           2 
                         
                         * 
                         
                           R 
                           load 
                         
                       
                       M 
                     
                   
                   , 
                 
               
               
                 
                   Eq 
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   
                     ( 
                     5 
                     ) 
                   
                 
               
             
           
         
       
     
     where i n  is an average noise current from each amplifier circuit  570 , and 
     P noise  is the noise power at each load circuit  590  with noise splitting. 
     As shown in equations (2) and (5), noise splitting may reduce the noise power at each load circuit  590  by a factor of M, which corresponds to the number of amplifier circuits  550  having their outputs shorted together. The reduction in noise power is due to the noise currents from the M amplifier circuits  550   a  to  550   m  being uncorrelated. The signal power at each load circuit  590  may be approximately the same regardless of whether or not the outputs of amplifier circuits  550  are shorted together. The constant signal power with or without noise splitting is due to the signal currents from the M amplifier circuits  550   a  to  550   m  being similar or highly correlated. The noise figure at each load circuit  590  may be improved with noise splitting since the signal power is approximately the same whereas the noise power is reduced by a factor of M with noise splitting. 
     SIMO LNA  540  with noise splitting at current buffer output may be implemented with various circuit architectures. Some exemplary designs of SIMO LNA  540  are described below. SIMO LNA  540  may also be implemented with transistors of various types. Some exemplary designs of SIMO LNA  540  implemented with N-channel metal oxide semiconductor (NMOS) transistors are described below. 
       FIG. 6A  shows a schematic diagram of an exemplary design of a SIMO LNA  640   a  with separate inductive degeneration and noise splitting at current buffer output. SIMO LNA  640   a  is one exemplary design of SIMO LNA  540  in  FIG. 5 . SIMO LNA  640   a  includes two amplifier circuits  650   a  and  650   b  and a switch  682   a . Each amplifier circuit  650  includes a gain circuit  660  and a current buffer  670 . SIMO LNA  640   a  receives an input RF signal, which is applied to both amplifier circuits  650   a  and  650   b . The input RF signal may include transmissions on one or two sets of carriers for carrier aggregation, with each set including one or more carriers. Alternatively, the input RF signal may include two transmitted signals (e.g., from two wireless systems) to be received simultaneously. 
     In the exemplary design shown in  FIG. 6A , each gain circuit  660  includes a gain transistor  664  and a source degeneration inductor  666 . Within gain circuit  660   a , gain transistor  664   a  has its gate receiving the input RF signal, its source coupled to one end of inductor  666   a , and its drain forming an output of gain circuit  660   a . The other end of inductor  666   a  is coupled to circuit ground. In the exemplary design shown in  FIG. 6A , each current buffer  670  includes a cascode transistor  674 . Within current buffer  670   a , cascode transistor  674   a  has its source forming an input of current buffer  670   a  and being coupled to the drain of gain transistor  664   a , its gate receiving a Venb1 control signal, and its drain forming an output of current buffer  670   a  and being coupled to a load circuit  690   a . Amplifier circuit  650   b  includes gain transistor  664   b , source degeneration inductor  666   b , and cascode transistor  674   b , which are coupled in similar manner as gain transistor  664   a , inductor  666   a , and cascode transistor  674   a  in amplifier circuit  650   a . Gain transistors  664  and cascode transistors  674  may be implemented with NMOS transistors, as shown in  FIG. 6A , or with transistors of other types. 
     In the exemplary design shown in  FIG. 6A , switch  682   a  includes NMOS transistors  684   a ,  684   b  and  686 . NMOS transistor  684   a  has its drain coupled to node A, its gate receiving a Sw control signal, and its source coupled to the drain of cascode transistor  674   a , which is the output of current buffer  670   a . NMOS transistor  684   b  has its drain coupled to node A, its gate receiving the Sw control signal, and its source coupled to the drain of cascode transistor  674   b , which is the output of current buffer  670   b . NMOS transistor  686  has its drain coupled to node A, its gate receiving a  Sw  control signal, and its source coupled to circuit ground. The  Sw  signal is complementary to the  Sw  signal. Switch  682   a  does not need to have a low resistance when it is closed. In particular, the on resistance of switch  682   a  should be low compared to the impedance of load circuit  690 . Switch  682   a  may be closed by (i) turning on NMOS transistors  684   a  and  684   b  with a high voltage on the Sw signal and (ii) turning off NMOS transistor  686  with a low voltage on the  Sw  signal. Conversely, switch  682   a  may be opened by (i) turning off NMOS transistors  684   a  and  684   b  with a low voltage on the Sw signal and (ii) turning on NMOS transistor  686  with a high voltage on the  Sw  signal. 
     Amplifier circuits  650   a  and  650   b  may also be implemented in other manners. In another exemplary design, an amplifier circuit may include a gain transistor having its source coupled directly to circuit ground (instead of to a source degeneration inductor). In yet another exemplary design, an amplifier circuit may include two gain transistors coupled in parallel and having their gates receiving the input RF signal. A first gain transistor may have its source coupled to a source degeneration inductor, as shown in  FIG. 6A . A second gain transistor may have its source coupled directly to circuit ground. Either the first or second gain transistor may be selected depending on the received power of the input RF signal. 
     In the exemplary design shown in  FIG. 6A , each load circuit  690  includes a transformer  692  comprising a primary coil  694  and a secondary coil  696 . A coil may also be referred to as an inductor coil, a winding, a conductor, etc. Within load circuit  690   a , a transformer  692   a  includes (i) a primary coil  694   a  coupled between the output of amplifier circuit  650   a  and a power supply (VDD) and (ii) a secondary coil  696   a  providing a first differential amplified RF signal to a first downconverter (not shown in  FIG. 6A ). Load circuit  690   b  includes a transformer  692   b  having (i) a primary coil  694   b  coupled between the output of amplifier circuit  650   b  and the VDD supply and (ii) a secondary coil  696   b  providing a second differential amplified RF signal to a second downconverter (not shown in  FIG. 6A ). Each downconverter may include two mixers to perform quadrature downconversion of an amplified RF signal from RF to baseband or an intermediate frequency. 
     Load circuits  690  may also be implemented in other manners. In another exemplary design, a load circuit may include an inductor and possibly a capacitor coupled between the output of an amplifier circuit and the VDD supply. In yet another exemplary design, a load circuit may include a P-channel metal oxide semiconductor (PMOS) transistor having its source coupled to the VDD supply and its drain coupled to the drain of a cascode transistor  674 . The PMOS transistor may provide an active load for cascode transistor  674 . 
     For simplicity,  FIG. 6A  shows SIMO LNA  640   a  including two amplifier circuits  650   a  and  650   b , which are coupled to two load circuits  690   a  and  690   b . SIMO LNA  640   a  may include more than two amplifier circuits  650  coupled to more than two load circuits  690 . 
     SIMO LNA  640   a  may operate in a single-output mode or a multi-output mode. In the single-output mode, SIMO LNA  640   a  receives the input RF signal and provides one output RF signal to one load circuit  690 . The single-output mode may be used to receive (i) a transmission on one carrier without carrier aggregation, or (ii) transmissions on one set of carriers among transmissions on multiple sets of carriers in different bands for inter-band CA, or (iii) a transmitted signal from one wireless system. In the multi-output mode, SIMO LNA  640   a  receives the input RF signal and provides two output RF signals to two load circuits  690 . The multi-output mode may be used to receive (i) transmissions on two sets of carriers for intra-band CA or (ii) two transmitted signals from two wireless systems. 
       FIG. 6B  shows operation of SIMO LNA  640   a  in the single-output mode with RFout 1  enabled. In this case, cascode transistor  674   a  is turned on and cascode transistor  674   b  is turned off. Furthermore, switch  682   a  is opened by turning off transistors  684   a  and  684   b  and turning on transistor  686 . Amplifier circuit  650   a  amplifies the input RF signal and provides a first output RF signal (RFout 1 ). Amplifier circuit  650   a  is isolated from amplifier circuit  650   b  via the opened switch  682   a.    
       FIG. 6C  shows operation of SIMO LNA  640   a  in the single-output mode with RFout 2  enabled. In this case, cascode transistor  674   b  is turned on, cascode transistor  674   a  is turned off, and switch  682   a  is opened. Amplifier circuit  650   b  amplifies the input RF signal and provides a second output RF signal (RFout 2 ). Amplifier circuit  650   b  is isolated from amplifier circuit  650   a  via the opened switch  682   a.    
       FIG. 6D  shows operation of SIMO LNA  640   a  in the multi-output mode. In this case, cascode transistors  674   a  and  674   b  are both turned on. Furthermore, switch  682   a  is closed by turning on transistors  684   a  and  684   b  and turning off transistor  686 . Amplifier circuits  650   a  and  650   b  amplify the input RF signal, and their output currents are summed. Approximately half of the total current is provided as the RFout 1  signal. The remaining current is provided as the RFout 2  signal. 
       FIG. 7A  shows a schematic diagram of an exemplary design of a SIMO LNA  640   b  with separate inductive degeneration and noise splitting at current buffer output. SIMO LNA  640   b  is another exemplary design of SIMO LNA  540  in  FIG. 5 . SIMO LNA  640   b  includes two amplifier circuits  650   a  and  650   b  and a switch  682   b . Each amplifier circuit  650  includes (i) gain circuit  660  comprising gain transistor  664  and source degeneration inductor  666  and (ii) current buffer  670  comprising cascode transistor  674 . Switch  682   b  includes an NMOS transistor  688  having its source coupled to the output of amplifier circuit  650   a , its gate receiving a Sw control signal, and its drain coupled to the output of amplifier circuit  650   b . A MOS transistor (e.g., NMOS transistor  688 ) may be implemented with a symmetric structure, and the source and drain of the MOS transistor may be interchangeable. SIMO LNA  640   b  may operate in the single-output mode or the multi-output mode, as described above for  FIGS. 6B to 6D . 
       FIGS. 6A and 7A  show two exemplary designs of a switch that may be used to short the outputs of two amplifier circuits. A switch may also be implemented in other manners. In another exemplary design, a capacitor and/or a resistor may be coupled in series with one or more MOS transistors, and the series combination may be coupled between the outputs of two amplifier circuits. The capacitor and/or resistor may improve isolation with a tradeoff in noise figure. 
       FIG. 7B  shows a schematic diagram of an exemplary design of a SIMO LNA  640   c  with shared inductive degeneration and noise splitting at current buffer output. SIMO LNA  640   c  is yet another exemplary design of SIMO LNA  540  in  FIG. 5 . SIMO LNA  640   c  includes two amplifier circuits  652   a  and  652   b  and switch  682   a . Each amplifier circuit  652  includes (i) a gain circuit  662  comprising gain transistor  664  and (ii) current buffer  670  comprising cascode transistor  674 . Gain transistors  664   a  and  664   b  in gain circuits  662   a  and  662   b  share a source degeneration inductor  666  having one end coupled to the sources of gain transistors  664   a  and  664   b  and the other end coupled to circuit ground. SIMO LNA  640   c  may operate in the single-output mode or the multi-output mode, as described above for  FIGS. 6B to 6D . 
       FIG. 7C  shows a schematic diagram of an exemplary design of SIMO LNA  640   c  with noise splitting at current buffer output and a load circuit  691  with transformer-based signal splitting. SIMO LNA  640   c  includes two amplifier circuits  652   a  and  652   b  sharing source degeneration inductor  666  as well as switch  682   a , which are coupled as described in  FIG. 7B . Load circuit  691  is coupled to amplifier circuits  652   a  and  652   b . In the exemplary design shown in  FIG. 7C , load circuit  691  comprises a transformer having a primary coil  693  and two secondary coils  695   a  and  695   b . Primary coil  693  has one end coupled to the output of amplifier circuit  652   a , the other end coupled to the output of amplifier circuit  652   b , and a center tap coupled to the VDD supply. Secondary coils  695   a  and  695   b  are magnetically coupled to primary coil  693 . Secondary coil  695   a  provides a first differential amplified RF signal to a first downconverter. Secondary coil  695   b  provides a second differential amplified RF signal to a second downconverter. In an exemplary design, secondary coils  695   a  and  695   b  may be symmetric with respect to each other. 
       FIG. 8  shows a block diagram of an exemplary design of a SIMO LNA  840  with noise splitting at gain circuit output. SIMO LNA  840  may be used for one or more LNAs  340  in  FIG. 3 . SIMO LNA  840  includes multiple (M) amplifier circuits  850   a  to  850   m , which are coupled to M load circuits  890   a  to  890   m , respectively. Each amplifier circuit  850  includes a gain circuit  860  coupled to a current buffer  870 . Each amplifier circuit  850  may be enabled by turning on its current buffer  870  via a respective Venb control signal. 
     In the exemplary design shown in  FIG. 8 , SIMO LNA  840  further includes interconnection circuits  880  between the outputs of gain circuits  860 . Interconnection circuits  880  allow the output currents from all enabled gain circuits  860  to be summed together. The total current from all enabled gain circuits  860  may then be split among current buffers  870  of all enabled amplifier circuits  850 . Interconnection circuits  880  may be implemented in various manners as described below. 
     SIMO LNA  840  with noise splitting at gain circuit output may be implemented with various circuit architectures and various types of transistors. Some exemplary designs of SIMO LNA  840  implemented with NMOS transistors are described below. 
       FIG. 9A  shows a schematic diagram of an exemplary design of a SIMO LNA  940   a  with separate inductive degeneration and noise splitting at gain circuit output. SIMO LNA  940   a  is one exemplary design of SIMO LNA  840  in  FIG. 8 . SIMO LNA  940   a  includes two amplifier circuits  950   a  and  950   b  and an interconnection circuit  980   a , which is implemented with an AC coupling capacitor  982 . Each amplifier circuit  950  includes (i) a gain circuit  960  comprising a gain transistor  964  and a source degeneration inductor  966  and (ii) a current buffer  970  comprising a cascode transistor  974 . Capacitor  982  is coupled between the outputs of gain circuits  960   a  and  960   b  and acts to electrically short the outputs of gain circuits  960   a  and  960   b . Since current buffers  970   a  and  970   b  can provide isolation, the outputs of gain circuits  960  may be effectively shorted together via capacitor  982  without the need to use switches. SIMO LNA  940   a  receives an input RF signal, which is applied to both amplifier circuits  950   a  and  950   b  Amplifier circuits  950   a  and  950   b  provide two output RF signals RFout 1  and RFout 2 , respectively. 
       FIG. 9A  shows an exemplary design in which interconnection circuit  980   a  is implemented with capacitor  982 . Capacitor  982  should be sufficiently large so that its impedance is small in comparison to the transconductance (or l/g m ) of cascode transistors  974 . An interconnection circuit may also be implemented in other manners with other circuits. 
     SIMO LNA  940   a  may operate in a single-output mode or a multi-output mode. In the single-output mode, SIMO LNA  940   a  receives the input RF signal and provides one output RF signal, which may be either RFout 1  or RFout 2 . In the multi-output mode, SIMO LNA  940   a  receives the input RF signal and provides two output RF signals RFout 1  and RFout 2 . 
       FIG. 9B  shows a schematic diagram of an exemplary design of a SIMO LNA  940   b  with shared inductive degeneration and noise splitting at gain circuit output. SIMO LNA  940   b  is another exemplary design of SIMO LNA  840  in  FIG. 8 . SIMO LNA  940   b  includes two amplifier circuits  952   a  and  952   b  and interconnection circuit  980   a . Each amplifier circuit  952  includes (i) a gain circuit  962  comprising gain transistor  964  and (ii) a current buffer  970  comprising cascode transistor  974 . Gain transistors  964   a  and  964   b  in gain circuits  962   a  and  962   b  share a source degeneration inductor  966  having one end coupled to the sources of gain transistors  964   a  and  964   b  and the other end coupled to circuit ground. SIMO LNA  940   b  may operate in the single-output mode or the multi-output mode. 
       FIG. 9C  shows a schematic diagram of an exemplary design of a SIMO LNA  940   c  with shared inductive degeneration and noise splitting at gain circuit output. SIMO LNA  940   c  is yet another exemplary design of SIMO LNA  840  in  FIG. 8 . SIMO LNA  940   c  includes two amplifier circuits  952   a  and  952   b , source degeneration inductor  966 , and an interconnection circuit  980   b . Interconnection circuit  980   b  includes two cross-coupled cascode transistors  984   a  and  984   b . Cascode transistor  984   a  has its source coupled to the drain of gain transistor  964   a , its gate receiving a Venb12 control signal, and its drain coupled to the output of amplifier circuit  952   b . Cascode transistor  984   b  has its source coupled to the drain of gain transistor  964   b , its gate receiving a Venb21 control signal, and its drain coupled to the output of amplifier circuit  952   a.    
     SIMO LNA  940   c  may operate in the single-output mode or the multi-output mode. In the single-output mode with RFout 1  enabled, amplifier circuit  952   a  may be enabled, amplifier circuit  952   b  may be disabled, NMOS transistors  984   a  and  984   b  may be turned off, and amplifier circuit  952   a  may provide the RFout 1  signal. Alternatively, amplifier circuit  952   a  may be enabled, gain transistor  964   b  and cascode transistor  984   b  may be enabled, cascode transistors  974   b  and  984   a  may be disabled, and amplifier circuit  952   a  may provide the RFout 1  signal. 
     In the single-output mode with RFout 2  enabled, amplifier circuit  952   b  may be enabled, amplifier circuit  952   a  may be disabled, NMOS transistors  984   a  and  984   b  may be turned off, and amplifier circuit  952   b  may provide the RFout 2  signal. Alternatively, amplifier circuit  952   b  may be enabled, gain transistor  964   a  and cascode transistor  984   a  may be enabled, cascode transistors  974   a  and  984   b  may be disabled, and amplifier circuit  952   b  may provide the RFout 2  signal. 
     In the multi-output mode, amplifier circuits  952   a  and  952   b  may both be enabled, NMOS transistors  984   a  and  984   b  may be enabled, and amplifier circuits  952   a  and  952   b  may provide the RFout 1  and RFout 2  signals, respectively. In the multi-output mode, gain circuit  962   a  may provide half its output current to cascode transistor  974   a  and the other half of its output current to cascode transistor  984   a . Similarly, gain circuit  962   b  may provide half its output current to cascode transistor  974   b  and the other half of its output current to cascode transistor  984   b . The currents from cascode transistors  974   a  and  984   b  may be summed at the output of amplifier circuit  952   a . The currents from cascode transistors  974   b  and  984   a  may be summed at the output of amplifier circuit  952   b . Cascode transistors  984   a  and  984   b  effectively short the drains of gain transistors  964   a  and  964   b  together while presenting low impedance to gain transistors  964   a  and  964   b . The noise figures of amplifier circuits  952   a  and  952   b  may be improved through noise splitting obtained by turning on cascode transistors  984   a  and  984   b  and splitting the output currents of gain transistors  964   a  and  964   b  in the multi-output mode. 
       FIGS. 9A and 9C  show two exemplary designs of interconnection circuit  980  between gain circuits  960 . An interconnection circuit between gain circuits may also be implemented in other manners. In another exemplary design, an interconnection circuit may be implemented with an NMOS transistor, which may be coupled as shown for NMOS transistor  688  in  FIG. 7A . In yet another exemplary design, an interconnection circuit may be implemented with two series NMOS transistors and a shunt NMOS transistor, which may be coupled as shown for series NMOS transistors  684   a  and  684   b  and shunt NMOS transistor  686  in  FIG. 6A . An interconnection circuit may be implemented in various manners and should have low impedance looking into the interconnection circuit. 
       FIGS. 6A to 9C  shows several exemplary designs of an LNA comprising a gain transistor and a cascode transistor. In another exemplary design, an LNA may comprise a NMOS transistor and a P-channel metal oxide semiconductor (PMOS) transistor coupled in similar manner as an inverter. In yet another exemplary design, an LNA may comprise a differential pair. An LNA may also be implemented in other manners. 
     The SIMO LNAs with noise splitting described herein may be used for various applications. The SIMO LNAs may be used to receive transmissions on multiple carriers (e.g., in the same band) for carrier aggregation. The SIMO LNAs may also be used to concurrently receive transmitted signals (e.g., in the same band) from multiple wireless systems (e.g., LTE and GSM, EVDO and CDMA 1X, WLAN and Bluetooth, etc.). The SIMO LNAs may also be used to concurrently receive transmissions for different services (e.g., voice and data). The SIMO LNAs may provide a single output RF signal in the single-output mode or multiple output RF signals in the multi-output mode. 
     The SIMO LNAs with noise splitting described herein may provide various advantages. First, these SIMO LNAs may have better noise figure due to noise splitting without sacrificing other performance metrics such as linearity. Second, the SIMO LNAs may be implemented with little additional die area and no increase in current consumption. Third, noise splitting may be applied to any circuit with two or more amplifier circuits sharing the same input RF signal. 
     In an exemplary design, an apparatus (e.g., a wireless device, an IC, a circuit module, etc.) may include a plurality of amplifier circuits and at least one interconnection circuit. The plurality of amplifier circuits (e.g., amplifier circuits  550   a  to  550   m  in  FIG. 5  or amplifier circuits  850   a  to  850   m  in  FIG. 8 ) may have their inputs coupled together and may receive an input RF signal. The at least one interconnection circuit (e.g., interconnection circuits  580  in  FIG. 5  or interconnection circuits  880  in  FIG. 8 ) may short at least two of the plurality of amplifier circuits coupled to the at least one interconnection circuit. Each interconnection circuit may be closed to short the outputs or internal nodes of two amplifier circuits coupled to that interconnection circuit. 
     In an exemplary design, the plurality of amplifier circuits may comprise a plurality of gain circuits (e.g., gain circuits  560  in  FIG. 5  or gain circuits  860  in  FIG. 8 ) and a plurality of current buffers (e.g., current buffers  570  in  FIG. 5  or current buffers  870  in  FIG. 7 ). Each amplifier circuit may include one gain circuit coupled to one current buffer. In an exemplary design, each gain circuit may comprise a gain transistor that receives the input RF signal and provides an amplified signal when the gain circuit is enabled. In an exemplary design, each current buffer may comprise a cascode transistor that receives an amplified signal from an associated gain circuit and provides an output RF signal when the current buffer is enabled. 
     In an exemplary design, one of the plurality of amplifier circuits may amplify the input RF signal and provide one output RF signal when this one amplifier circuit is enabled. The remaining amplifier circuits may be disabled. In an exemplary design, the plurality of amplifier circuits may be enabled to amplify the input RF signal and provide a plurality of output RF signals. Each amplifier circuit may provide an output current comprising a portion of the current from each of the plurality of gain circuits when the plurality of amplifier circuits are enabled. 
     In an exemplary design, noise splitting at current buffer output may be implemented, e.g., as shown in  FIG. 5 . The at least one interconnection circuit may comprise at least one switch (e.g., switches  582  in  FIG. 5 ) coupled between the outputs of the plurality of amplifier circuits. Each switch may be closed to short the outputs of two amplifier circuits coupled to that switch. The at least one interconnection circuit or switch may short the outputs of the plurality of amplifier circuits when the plurality of amplifier circuits are enabled. 
     In another exemplary design, noise splitting at gain circuit output may be implemented, e.g., as shown in  FIG. 8 . In an exemplary design, the at least one interconnection circuit may comprise at least one capacitor (e.g., capacitor  982  in  FIG. 9A ) coupled between the outputs of the plurality of gain circuits. Each capacitor may short the outputs of two gain circuits coupled to that capacitor. The at least one interconnection circuit may short the outputs of the plurality of gain circuits when the plurality of amplifier circuits are enabled. In another exemplary design, the at least one interconnection circuit may comprise a plurality of cascode transistors (e.g., cascode transistors  984  in  FIG. 9C ) coupled between the plurality of gain circuits and the plurality of current buffers. Each cascode transistor may be coupled between a gain circuit in one amplifier circuit and a current buffer in another amplifier circuit. The plurality of cascode transistors may be turned on when the plurality of amplifier circuits are enabled. 
     In an exemplary design, the plurality of amplifier circuits may comprise first and second amplifier circuits. The first amplifier circuit (e.g., amplifier circuit  650   a  in  FIG. 6A ) may comprise a first gain transistor (e.g., gain transistor  664   a ) and a first cascode transistor (e.g., cascode transistor  674   a ). The second amplifier circuit (e.g., amplifier circuit  650   b ) may comprise a second gain transistor (e.g., gain transistor  664   a ) and a second cascode transistor (e.g., cascode transistor  674   a ). In an exemplary design, a separate source degeneration inductor may be used for each gain circuit. The first amplifier circuit may comprise a first inductor (e.g., inductor  666   a ) coupled between the source of the first gain transistor and circuit ground. The second amplifier circuit may comprise a second inductor (e.g., inductor  666   b ) coupled between the source of the second gain transistor and circuit ground. In another exemplary design, a shared source degeneration inductor (e.g., inductor  666  in  FIG. 7B ) may be used for the first and second gain transistors and may be coupled between the sources of these gain transistors and circuit ground. 
     In an exemplary design, the at least one interconnection circuit may comprise a switch (e.g., switch  682   a  in  FIG. 6A  or switch  682   b  in  FIG. 7A ) coupled between the drains of the first and second cascode transistors. The switch may be opened when only the first or second amplifier circuit is enabled and may be closed when both the first and second amplifier circuits are enabled. In an exemplary design, the switch may comprise first, second and third transistors. The first transistor (e.g., NMOS transistor  684   a  in  FIG. 6A ) may be coupled between the drain of the first cascode transistor and an intermediate node. The second transistor (e.g., NMOS transistor  684   b ) may be coupled between the intermediate node and the drain of the second cascode transistor. The third transistor (e.g., NMOS transistor  686 ) may be coupled between the intermediate node and circuit ground. In another exemplary design, the switch may comprise a transistor (e.g., NMOS transistor  688  in  FIG. 7A ) coupled between the drains of the first and second cascode transistors. The switch may also be implemented in other manners. 
     In another exemplary design, the at least one interconnection circuit may comprise a capacitor (e.g., capacitor  982  in  FIG. 9A ) coupled between the drains of the first and second gain transistors. The first cascode transistor may be turned on and the second cascode transistor may be turned off when the first amplifier circuit is enabled. The second cascode transistor may be turned on and the first cascode transistor may be turned off when the second amplifier circuit is enabled. The first and second cascode transistors may both be turned on when the first and second amplifier circuits are enabled. 
     In yet another exemplary design, the at least one interconnection circuit may comprise third and fourth cascode transistors. The third cascode transistor (e.g., cascode transistor  984   a  in  FIG. 9C ) may be coupled between the drain of the first gain transistor and the drain of the second cascode transistor. The fourth cascode transistor (e.g., cascode transistor  984   b ) may be coupled between the drain of the second gain transistor and the drain of the first cascode transistor. The third and fourth cascode transistors may be turned on when the first and second amplifier circuits are both enabled. Only the first cascode transistor may be turned on, or both the first and fourth cascode transistors may be turned on, when the first amplifier circuit is enabled. Only the second cascode transistor may be turned on, or both the second and third cascode transistors may be turned on, when the second amplifier circuit is enabled. 
     The apparatus may include first and second load circuits coupled to the first and second amplifier circuits, respectively. In an exemplary design, the first load circuit (e.g., load circuit  690   a  in  FIG. 6A ) may comprise a first transformer (e.g., transformer  692   a ) coupled to the first amplifier circuit. The second load circuit (e.g., load circuit  690   b ) may comprise a second transformer (e.g., transformer  692   b ) coupled to the second amplifier circuit. The first and second load circuits may also be implemented in other manners. 
       FIG. 10  shows an exemplary design of a process  1000  for performing signal amplification. Process  1000  may be performed by a wireless device or by some other entity. An input RF signal may be applied to a plurality of amplifier circuits, which may have their inputs coupled together (block  1012 ). At least one of the plurality of amplifier circuits may be enabled to amplify the input RF signal and provide at least one output RF signal (block  1014 ). The plurality of amplifier circuits may be shorted via at least one interconnection circuit when the plurality of amplifier circuits are enabled in order to perform noise splitting and improve noise figure (block  1016 ). Each interconnection circuit may short the outputs or internal nodes of two amplifier circuits coupled to that interconnection circuit. 
     In an exemplary design of block  1014 , the input RF signal may be amplified with a plurality of gain circuits in the plurality of amplifier circuits. The plurality of amplifier circuits may provide output currents. The output current from each amplifier circuit may comprise a portion of the current from each of the plurality of gain circuits. 
     The amplifiers (e.g., SIMO LNAs) with noise splitting described herein may be implemented on an IC, an analog IC, an RFIC, a mixed-signal IC, an ASIC, a printed circuit board (PCB), an electronic device, etc. The amplifiers with noise splitting may also be fabricated with various IC process technologies such as complementary metal oxide semiconductor (CMOS), NMOS, PMOS, bipolar junction transistor (BJT), bipolar-CMOS (BiCMOS), silicon germanium (SiGe), gallium arsenide (GaAs), heterojunction bipolar transistors (HBTs), high electron mobility transistors (HEMTs), silicon-on-insulator (SOI), etc. 
     An apparatus implementing an amplifier with noise splitting described herein may be a stand-alone device or may be part of a larger device. A device may be (i) a stand-alone IC, (ii) a set of one or more ICs that may include memory ICs for storing data and/or instructions, (iii) an RFIC such as an RF receiver (RFR) or an RF transmitter/receiver (RTR), (iv) an ASIC such as a mobile station modem (MSM), (v) a module that may be embedded within other devices, (vi) a receiver, cellular phone, wireless device, handset, or mobile unit, (vii) etc. 
     In one or more exemplary designs, the functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage media may be any available media that can be accessed by a computer. By way of example, and not limitation, such computer-readable media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer. Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, includes compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk and blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media. 
     The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples and designs described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.