Patent Publication Number: US-2023164977-A1

Title: Semiconductor device and method for fabricating the same

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     The present application claims priority of Korean Patent Application No. 10-2021-0160342, filed on Nov. 19, 2021, which is incorporated herein by reference in its entirety. 
     BACKGROUND 
     1. Field 
     Embodiments of the present invention relate to a semiconductor device, and more particularly, to a semiconductor device including a bit line and a method for fabricating the semiconductor device. 
     2. Description of the Related Art 
     To fabricate highly integrated semiconductor devices, a transistor having a vertical channel has been proposed. 
     A vertical channel transistor using monocrystalline silicon as a channel has limitation in the degree of integration. Also, its electrical characteristics are deteriorated due to gate-induced drain leakage (GIDL) occurring in an overlapping region between a source/drain and a gate and junction leakage of a PN junction. 
     SUMMARY 
     Embodiments of the present invention are directed to a highly integrated semiconductor device, and a method for fabricating the semiconductor device. 
     In accordance with an embodiment of the present invention, a semiconductor device includes: a bit line; an oxide semiconductor pillar extending vertically from the bit line; a capacitor disposed over the oxide semiconductor pillar; and a word line disposed over a sidewall of the oxide semiconductor pillar, wherein the oxide semiconductor pillar includes: a lower oxide semiconductor interface layer coupled to the bit line; an upper oxide semiconductor interface layer coupled to the capacitor; and an oxide semiconductor channel layer disposed between the lower oxide semiconductor interface layer and the upper oxide semiconductor interface layer. 
     In accordance with another embodiment of the present invention, a semiconductor device includes: a substrate; a peripheral circuit portion disposed over the substrate; and a memory cell array including a bit line, a transistor, and a memory element that are vertically stacked over the peripheral circuit portion, wherein the transistor includes: an oxide semiconductor channel layer disposed between the bit line and a memory element; a tapered vertical word line disposed over a sidewall of the oxide semiconductor channel layer; a lower oxide semiconductor interface layer between the bit line and the oxide semiconductor channel layer; and an upper oxide semiconductor interface layer disposed between the capacitor and the oxide semiconductor channel layer. 
     In accordance with yet another embodiment of the present invention, a method for fabricating a semiconductor device includes: forming a bit line over a substrate; forming an oxide semiconductor pillar by stacking a lower interface layer, an oxide semiconductor channel layer, and an upper interface layer over the bit line in the recited order; forming a word line on a sidewall of the oxide semiconductor pillar; and forming a capacitor over the oxide semiconductor pillar. 
     In accordance with still another embodiment of the present invention, a semiconductor device includes: a first conductive line; an oxide semiconductor pillar extending vertically from the first conductive line; a memory element disposed over the oxide semiconductor pillar; and a second conductive line disposed over a sidewall of the oxide semiconductor pillar, wherein the oxide semiconductor pillar includes: a lower oxide semiconductor interface layer coupled to the first conductive line; an upper oxide semiconductor interface layer coupled to the memory element; and an oxide semiconductor channel layer disposed between the lower oxide semiconductor interface layer and the upper oxide semiconductor interface layer. 
     In accordance with another embodiment of the present invention, a vertical channel transistor includes: a lower oxide semiconductor interface layer; an upper oxide semiconductor interface layer; an oxide semiconductor channel layer extending vertically between the lower oxide semiconductor interface layer and the upper oxide semiconductor interface layer; and a tapered vertical gate disposed over a sidewall of the oxide semiconductor channel layer. The oxide semiconductor channel layer may include IGZO, ITZO or ZTO, and the lower oxide semiconductor interface layer and the upper oxide semiconductor interface layer may include indium-rich IGZO. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG.  1 A  is a schematic perspective view illustrating a semiconductor device. 
         FIG.  1 B  is a schematic plan view illustrating the semiconductor device of  FIG.  1 A . 
         FIG.  1 C  is a cross-sectional view taken along a line A-A′ shown in  FIG.  1 B . 
         FIG.  1 D  is a cross-sectional view taken along a line B-B′ shown in  FIG.  1 B . 
         FIG.  1 E  is a detailed cross-sectional view illustrating a capacitor. 
         FIGS.  2 A to  2 K  are cross-sectional views illustrating an example of a method for fabricating a semiconductor device in accordance with an embodiment of the present invention. 
         FIGS.  3 A to  3 E  are cross-sectional views illustrating an example of a method for forming a capacitor. 
         FIG.  4 A  is a cross-sectional view illustrating a semiconductor device in accordance with another embodiment of the present invention. 
         FIG.  4 B  is a cross-sectional view illustrating a semiconductor device in accordance with another embodiment of the present invention. 
         FIG.  5    is a cross-sectional view illustrating a semiconductor device in accordance with another embodiment of the present invention. 
         FIGS.  6 A to  6 C  are cross-sectional views illustrating a method for fabricating a semiconductor device in accordance with another embodiment of the present invention. 
         FIGS.  7 A to  7 G  are cross-sectional views illustrating a method for fabricating a semiconductor device in accordance with another embodiment of the present invention. 
         FIGS.  8  to  10    are cross-sectional views illustrating semiconductor devices in accordance with other embodiments of the present invention. 
         FIGS.  11 A to  11 C  are cross-sectional views illustrating a method for fabricating a semiconductor device in accordance with another embodiment of the present invention. 
         FIGS.  12 A and  12 B  are cross-sectional views illustrating a method for fabricating a semiconductor device in accordance with another embodiment of the present invention. 
         FIGS.  13 A to  13 D  are cross-sectional views illustrating a method for fabricating a semiconductor device in accordance with another embodiment of the present invention. 
         FIGS.  14 A and  14 B  are cross-sectional views illustrating a method for fabricating a semiconductor device in accordance with another embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION 
     Embodiments of the present invention will be described below in more detail with reference to the accompanying drawings. The present invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. Throughout the disclosure, like reference numerals refer to like parts throughout the various figures and embodiments of the present invention. 
     The drawings are not necessarily to scale and in some instances, proportions may have been exaggerated in order to clearly illustrate features of the embodiments. When a first layer is referred to as being “on” a second layer or “on” a substrate, it not only refers to a case where the first layer is formed directly on the second layer or the substrate but also a case where a third layer exists between the first layer and the second layer or the substrate. 
       FIG.  1 A  is a schematic perspective view illustrating a semiconductor device.  FIG.  1 B  is a schematic plan view illustrating the semiconductor device.  FIG.  1 C  is a cross-sectional view taken along a line A-A′ shown in  FIG.  1 B .  FIG.  1 D  is a cross-sectional view taken along a line B-B′ shown in  FIG.  1 B .  FIG.  1 E  is a detailed cross-sectional view illustrating a capacitor  130 . 
     Referring to  FIGS.  1 A to  1 E , the semiconductor device  100  may include a plurality of first conductive lines  110 , a plurality of oxide semiconductor pillars  120  vertically extending from the first conductive lines  110 , a plurality of memory elements  130  formed over the oxide semiconductor pillars  120 , and a plurality of second conductive lines  124  disposed over the respective sidewalls of the oxide semiconductor pillars  120 . Each oxide semiconductor pillar  120  may include a lower interface layer  122  coupled to the first conductive line  110 , an upper interface layer  123  coupled to the memory element  130 , and an oxide semiconductor channel layer  121  disposed between the lower interface layer  122  and the upper interface layer  123 . The lower interface layer  122  and the upper interface layer  122  may include an oxide semiconductor layer. The lower interface layer  122  and the upper interface layer  123  may be referred to as a lower oxide semiconductor interface layer and an upper oxide semiconductor interface layer, respectively. 
     The semiconductor device  100  may include a Dynamic Random Access Memory (DRAM), and the first conductive lines  110  and the second conductive lines  124  may correspond to bit lines and word lines, respectively. The memory elements  130  may correspond to capacitors. Hereinafter, the first conductive lines  110  and the second conductive lines  124  may be simply referred to as bit lines  110  and word lines  124 , respectively, and the memory elements  130  may be simply referred to as capacitors  130 . 
     The semiconductor device  100  may include an oxide semiconductor channel layer  121 , a bit line  110  disposed at a lower level than the oxide semiconductor channel layer  121 , a capacitor  130  disposed at a higher level than the oxide semiconductor channel layer  121 , a tapered vertical word line  124  disposed over a sidewall of the oxide semiconductor channel layer  121 , a lower interface layer  122  between the bit line  110  and the oxide semiconductor channel layer  121 , and an upper interface layer  123  between the capacitor  130  and the oxide semiconductor channel layer  121 . 
     The semiconductor device  100  may be described in detail as follows. 
     The semiconductor device  100  may include a substrate  101 , a buffer layer  102  over the substrate  101 , a bit line  110  over the buffer layer  102 , a vertical channel transistor TR over the bit line  110 , and a capacitor  130  over the vertical channel transistor TR. The vertical channel transistor TR may include an oxide semiconductor pillar  120 , a tapered vertical word line  124  disposed over both sidewalls of the oxide semiconductor pillar  120 , and a gate dielectric layer  125  between the oxide semiconductor pillar  120  and the tapered vertical word line  124 . The oxide semiconductor pillar  120  may include the oxide semiconductor channel layer  121 , the lower interface layer  122  between the oxide semiconductor channel layer  121  and the bit line  110 , and the upper interface layer  123  between the oxide semiconductor channel layer  121  and the capacitor  130 . A barrier layer  111  may be disposed between the bit line  110  and the lower interface layer  122 . 
     The semiconductor device  100  may further include first and second contact plugs  126  and  127  between the upper interface layer  123  and the capacitor  130 . 
     The substrate  101  may be a material suitable for semiconductor processing. The substrate  101  may include a semiconductor substrate. The substrate  101  may be formed of a silicon-containing material. The substrate  101  may include silicon, monocrystalline silicon, polysilicon, amorphous silicon, silicon germanium, monocrystalline silicon germanium, polycrystalline silicon germanium, carbon-doped silicon, a combination thereof, or a multilayer thereof. The substrate  101  may include other semiconductor materials such as germanium. The substrate  101  may include a III/V group semiconductor substrate, for example, a compound semiconductor substrate, such as GaAs. The substrate  101  may include a Silicon-On-Insulator (SOI) substrate. 
     The buffer layer  102  may include silicon oxide, silicon nitride, or a combination thereof. To reduce parasitic capacitance, the buffer layer  102  may be formed of silicon oxide. For example, the buffer layer  102  may include tetra ethyl ortho silicate (TEOS). 
     The bit line  110  may extend in a first direction D1 over the buffer layer  102 . The bit line  110  may include a metal-based material. The bit line  110  may include a metal, a metal nitride, a metal silicide, or a combination thereof. The bit line  110  may have a thickness of approximately 100 to 400 Å. The bit line  110  may include a tungsten layer. 
     The barrier layer  111  may include a metal, a metal nitride, a metal silicide, or a combination thereof. The barrier layer  111  may include titanium nitride, molybdenum, or ruthenium. The barrier layer  111  may have a thickness of approximately 10 to 50 Å. For example, the barrier layer  111  may include a titanium nitride layer. 
     The lower interface layer  122  and the upper interface layer  123  may include an oxide semiconductor material having a lower resistance than the oxide semiconductor channel layer  121 . The lower interface layer  122  and the upper interface layer  123  may include a metallic-rich oxide semiconductor material, and the oxide semiconductor channel layer  121  may include an oxygen-rich oxide semiconductor material. For example, the oxide semiconductor channel layer  121  may include indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), or zinc tin oxide (ZTO), and the lower interface layer  122  and the upper interface layer  123  may include indium-rich IGZO. Indium-rich IGZO may refer to a material with a higher indium content than gallium (Ga) and zinc (Zinc) in IGZO, for example, the content of indium may be approximately 40% or more. 
     The oxide semiconductor channel layer  121  may include an oxide semiconductor material. The oxide semiconductor channel layer  121  may contain indium. The oxide semiconductor channel layer  121  may include IGZO. The oxide semiconductor channel layer  121  may be formed to have a thickness of approximately 200 to 1000 Å. 
     The lower interface layer  122  may include an oxide semiconductor material. The lower interface layer  122  may contain indium. The lower interface layer  122  may include an indium-rich oxide semiconductor material. For example, the lower interface layer  122  may include indium-rich IGZO. The lower interface layer  122  may be formed to have a thickness of approximately 10 to 50 Å. 
     The upper interface layer  123  may include an oxide semiconductor material. The upper interface layer  123  may contain indium. The upper interface layer  123  may include an indium-rich oxide semiconductor material. For example, the upper interface layer  123  may include indium-rich IGZO. The upper interface layer  123  may be formed to have a thickness of approximately 10 to 50 Å. 
     As described above, the oxide semiconductor pillar  120  may extend vertically in a third direction D3 over the bit line  110 . The oxide semiconductor pillar  120  may be vertically stacked over the bit line  110  in an order of the lower interface layer  122 , the oxide semiconductor channel layer  121 , and the upper interface layer  123 . The lower interface layer  122 , the oxide semiconductor channel layer  121 , and the upper interface layer  123  may all include an oxide semiconductor material. The lower interface layer  122 , the oxide semiconductor channel layer  121 , and the upper interface layer  123  may all include IGZO, but the lower interface layer  122  and the upper interface layer  123  may have a higher indium concentration than the oxide semiconductor channel layer  121 . The oxide semiconductor channel layer  121  may be IGZO, and the lower interface layer  122  and the upper interface layer  123  may be indium-rich IGZO. The lower interface layer  122 , the oxide semiconductor channel layer  121 , and the upper interface layer  123  may be referred to as an active pillar. 
     A tapered vertical word line  124  having a double structure may be disposed over a sidewall of the oxide semiconductor channel layer  121 . The tapered vertical word line  124  and the bit line  110  may extend in directions crossing each other. The tapered vertical word line  124  may have a reverse tapered shape. The reverse tapered shape may refer to a shape the width of the bottom portion of which becomes gradually smaller than the width of the upper portion. For example, the tapered vertical word line  124  may include a lower level portion  124 L which is adjacent to the bit line  110  and an upper level portion  124 U which is adjacent to the capacitor  130 . The thickness of the lower level portion  124 L in the first direction D1 may be smaller than the thickness of the upper level portion  124 U. The lower level portion  124 L may be adjacent to the lower interface layer  122 , and the upper level portion  124 U may be adjacent to the upper interface layer  123 . The lower level portion  124 L and the upper level portion  124 U may be formed of the same material. The lower level portion  124 L and the bit line structure BL may be spaced apart from each other with a space. The lower level portion  124 L of the tapered vertical word line  124  and the bit line structure BL may not contact each other. 
     The tapered vertical word line  124  may include a metal-based material. The tapered vertical word line  124  may include a metal, a metal nitride, or a combination thereof. The tapered vertical word line  124  may include tantalum nitride (TaN), titanium nitride (TiN), tungsten (W), tungsten nitride (WN), or a combination thereof. 
     A gate dielectric layer  125  may be formed between the tapered vertical word line  124  and the oxide semiconductor pillar  120 . The gate dielectric layer  125  may include silicon oxide, silicon nitride, silicon oxynitride, a high-k material, or a combination thereof. The gate dielectric layer  125  may be disposed between the oxide semiconductor pillar  120  and the tapered vertical word line  124 . The gate dielectric layer  125  may include a horizontal portion that extends to be disposed between the lower level portion  124 L of the tapered vertical word line  124  and the bit line  110 , and the horizontal portion of the gate dielectric layer  125  may directly contact the barrier layer  111 . The oxide semiconductor pillar  120 , the gate dielectric layer  125 , and the tapered vertical word line  124  may form the vertical channel transistor TR. The tapered vertical word line  124  may be referred to as a tapered vertical gate. 
     The contact plugs  126  and  127  may include a first contact plug  126  and a second contact plug  127  over the first contact plug  126 . The first contact plug  126  may directly contact the upper interface layer  123 , and the second contact plug  127  may directly contact the capacitor  130 . The first contact plug  126  and the second contact plug  127  may vertically overlap with each other. The first contact plug  126  and the second contact plug  127  may include a metal-based material. The first contact plug  126  and the second contact plug  127  may include a metal, a metal nitride, or a combination thereof. The first contact plug  126  and the second contact plug  127  may be formed of the same metal-based material. According to another embodiment of the present invention, the first contact plug  126  and the second contact plug  127  may be formed of different metal-based materials. Sidewalls of the first contact plugs  126  may be surrounded by the gate dielectric layer  125 . 
     The capacitor  130  may include a lower electrode  132 , a dielectric layer  135 , and an upper electrode  136 . The lower electrode  132  may be formed over the second contact plug  127 . The lower electrode  132  may have a pillar shape. The lower electrodes  132  may be supported by the supporters  133  and  134 . A sidewall of the bottom portion of the lower electrode  132  may contact the etch stop layer  131 . According to another embodiment of the present invention, the lower electrodes  132  may have a cylindrical shape. 
     Although not illustrated, dielectric pillars may be disposed between the oxide semiconductor pillars  120  in the direction of the A-A′. 
       FIGS.  2 A to  2 K  are cross-sectional views illustrating an example of a method for fabricating a semiconductor device in accordance with an embodiment of the present invention. 
     Referring to  FIG.  2 A , a buffer layer  12  may be formed over a substrate  11 . The substrate  11  may be a material appropriate for semiconductor processing. The substrate  11  may include a semiconductor substrate. The substrate  11  may be formed of a silicon-containing material. The substrate  11  may include silicon, monocrystalline silicon, polysilicon, amorphous silicon, silicon germanium, monocrystalline silicon germanium, polycrystalline silicon germanium, carbon-doped silicon, a combination thereof, or a multilayer thereof. The substrate  11  may include other semiconductor materials, such as germanium. The substrate  11  may include a III/V-group semiconductor substrate, for example, a compound semiconductor substrate, such as GaAs. The substrate  11  may include a Silicon-On-Insulator (SOI) substrate. The buffer layer  12   may include a dielectric material. The buffer layer  12  may include silicon oxide, silicon nitride, or a combination thereof. 
     A conductive layer  13 A may be formed over the buffer layer  12 . The conductive layer  13 A may include a metal-based material. The conductive layer  13 A may include a metal, a metal nitride, a metal silicide, or a combination thereof. The conductive layer  13 A may be formed by atomic layer deposition (ALD), physical vapor deposition (PVD), or chemical vapor deposition (CVD). The conductive layer  13 A may be formed to have a thickness of approximately 100 to 400 Å. For example, as for the conductive layer  13 A, a tungsten layer may be deposited to have a thickness of approximately 200 Å by physical vapor deposition (PVD). In order to reduce parasitic capacitance between the substrate  11  and the conductive layer  13 A, the buffer layer  12  may be formed of silicon oxide. For example, the buffer layer  12  may include tetra ethyl ortho silicate (TEOS). 
     A barrier material layer  14 A may be formed over the conductive layer  13 A. The barrier material layer  14 A may include a metal-based material. The barrier material layer  14 A may include a metal, a metal nitride, a metal silicide, or a combination thereof. The barrier material layer  14 A may include titanium nitride, molybdenum, or ruthenium. The barrier material layer  14 A may be formed by atomic layer deposition (ALD), physical vapor deposition (PVD), or chemical vapor deposition (CVD). The barrier material layer  14 A may be formed to have a thickness of approximately 10 to 50 Å. For example, as for the barrier material layer  14 A, titanium nitride may be deposited to have a thickness of approximately 20 Å by physical vapor deposition (PVD). 
     An oxide semiconductor stack may be formed over the barrier material layer  14 A. For example, the oxide semiconductor stack may include a lower interface material layer  15 A, a channel material layer  16 A, and an upper interface material layer  17 A. 
     A lower interface material layer  15 A may be formed over the barrier layer  14 A. The lower interface material layer  15 A may include a conductive material. The lower interface material layer  15 A may include an oxide semiconductor material. The lower interface material layer  15 A may contain indium. The lower interface material layer  15 A may include an indium-rich oxide semiconductor material. For example, the lower interface material layer  15 A may include indium-rich IGZO. The lower interface material layer  15 A may be formed to have a thickness of approximately 10-50 Å. 
     A channel material layer  16 A may be formed over the lower interface material layer  15 A. The channel material layer  16 A may include a conductive material. The channel material layer  16 A may include an oxide semiconductor material. The channel material layer  16 A may contain indium. The channel material layer  16 A may include IGZO. The channel material layer  16 A may be formed to have a thickness of approximately 200 to 1000 Å. 
     An upper interface material layer  17 A may be formed over the channel material layer  16 A. The upper interface material layer  17 A may include a conductive material. The upper interface material layer  17 A may include an oxide semiconductor material. The upper interface material layer  17 A may contain indium. The upper interface material layer  17 A may include an indium-rich oxide semiconductor material. For example, the upper interface material layer  17 A may include indium-rich IGZO. The upper interface material layer  17 A may be formed to have a thickness of approximately 10 to 50 Å. 
     As described above, the lower interface material layer  15 A, the channel material layer  16 A, and the upper interface material layer  17 A may be vertically stacked over the barrier material layer  14 A. The lower interface material layer  15 A, the channel material layer  16 A, and the upper interface material layer  17 A may all include an oxide semiconductor material. The lower interface material layer  15 A, the channel material layer  16 A, and the upper interface material layer  17 A may all include IGZO, but the lower interface material layer  15 A and the upper interface material layer  17 A may have a higher indium concentration than the channel material layer  16 A. The channel material layer  16 A may be IGZO, and the lower interface material layer  15 A and the upper interface material layer  17 A may be indium-rich IGZO. As the lower interface material layer  15 A and the upper interface material layer  17 A contain a high concentration of indium, its resistance may be reduced lower than that of the channel material layer  16 A. Also, channel seamless interconnection of the channel material layer  16 A may be possible. 
     Subsequently, a sacrificial layer  18 A may be formed over the upper interface material layer  17 A. The sacrificial layer  18 A may include a stack of different materials. The sacrificial layer  18 A may include silicon nitride. 
     Referring to  FIG.  2 B , sacrificial lines  18  may be formed over the upper interface material layer  17 A. The sacrificial lines  18  may be formed by etching the sacrificial layer  18 A. The sacrificial lines  18  may serve to protect the lower interface material layer  15 A, the channel material layer  16 A, and the upper interface material layer  17 A from the subsequent processes. For example, the sacrificial lines  18  may be used as an etch barrier during an etching process of the lower interface material layer  15 A, the channel material layer  16 A, and the upper interface material layer  17 A. 
     Each of the sacrificial lines  18  may include a stack of different materials. The sacrificial lines  18  may include silicon nitride. The etching process of the sacrificial layer  18 A to form the sacrificial lines  18  may include a double patterning process. 
     Subsequently, the upper interface material layer  17 A, the channel material layer  16 A, and the upper interface material layer  15 A may be etched by using the sacrificial lines  18  as an etch barrier, and then the barrier material layer  14 A and the conductive layer  13 A may be etched. 
     A plurality of line structures  19 L and first trenches  19 T may be formed over the buffer layer  12  by a series of the etching processes described above. Each of the line structures  19 L may include a stack of a bit line  13 , a bit line barrier layer  14 , a lower interface layer  15 B, a channel material layer  16 B, an upper interface layer  17 B, and a sacrificial line  18 . The bit line barrier layer  14  may be formed by etching the barrier material layer  14 A, and the bit line  13  may be formed by etching the conductive layer  13 A. The lower interface layer  15 B, the channel material layer  16 B, and the upper interface layer  17 B may be formed by etching the lower interface material layer  15 A, the channel material layer  16 A, and the upper interface material layer  17 A, respectively. The first trenches  19 T may be disposed between the line structures  19 L. The stack of the lower interface layer  15 B, the channel material layer  16 B, and the upper interface layer  17 B may be referred to as an ‘oxide semiconductor line’. 
     Referring to  FIG.  2 C , dielectric lines  20  may be formed between the line structures  19 L. The dielectric lines  20  may include a dielectric material. For example, the dielectric lines  20  may include silicon oxide, silicon nitride, silicon carbon oxide (SiCO), spin-on-dielectric, or a combination thereof. After a dielectric material is deposited to fill the first trenches  19 T between the line structures  19 L to form the dielectric lines  20 , a planarization process of the dielectric material may be performed. The dielectric lines  20  may fill the first trenches  19 T, respectively. To form the dielectric lines  20 , a planarization process may be performed after a silicon nitride, silicon carbon oxide, and a spin-on dielectric layer are sequentially formed. 
     Referring to  FIG.  2 D , a portion of the line structures  19 L may be selectively etched to form the sacrificial pillars  18 P and the oxide semiconductor pillars  21 P. A bit line barrier layer  14  and a bit line  13  may be disposed below the oxide semiconductor pillars  21 P. 
     Each of the oxide semiconductor pillars  21 P may include a stack of a lower interface layer  15 , a channel layer  16 , and an upper interface layer  17 . The lower interface layer  15 , the channel layer  16 , and the upper interface layer  17  may be formed by etching the lower interface layer  15 B, the channel material layer  16 B, and the upper interface layer  17 B, respectively. A sacrificial pillar  18 P may be formed over the upper interface layer  17 . 
     Second trenches  22  may be formed between the oxide semiconductor pillars  21 P. The bottom surfaces of the second trenches  22  may expose the top surface of the bit line barrier layer  14 . The first trenches  19 T and the second trenches  22  may intersect with each other. The first trenches  19 T may be deeper than the second trenches  22 . In the direction of the line B-B′, the dielectric lines  20  may be cut by the second trenches  22 . Hereinafter, the dielectric lines  20  may be simply referred to as ‘dielectric pillars 20’. The dielectric pillars  20  may be disposed between the oxide semiconductor pillars  21 P in the direction of the line A-A′. 
     Each of the oxide semiconductor pillars  21 P may include first to fourth sidewalls SW 1  to SW 4 . A first sidewall SW 1  and a second sidewall SW 2  of the individual oxide semiconductor pillar  21 P may be exposed by the second trenches  22 , and a third sidewall SW 3  and a fourth sidewall SW 4  of the individual oxide semiconductor pillar  21 P may not be exposed by the dielectric pillars  20 . The sacrificial pillar  18 P may also include exposed sidewalls and non-exposed sidewalls just as the oxide semiconductor pillar  21 P. 
     Referring to  FIG.  2 E , a gate dielectric layer  23  may be formed over the exposed first and second sidewalls SW 1  and SW 2  of the oxide semiconductor pillars  21 P. The gate dielectric layer  23  may include silicon oxide, silicon nitride, silicon oxynitride, a high-k material, or a combination thereof. The high-k material may include a material having a higher dielectric constant than that of silicon oxide. For example, the high-k material may include a material having a dielectric constant which is greater than approximately 3.9. As another example, the high-k material may include a material having a dielectric constant which is greater than approximately 10. As another example, the high-k material may include a material having a dielectric constant of approximately 10 to 30. The high-k material may include at least one metallic element. The high-k material may include a hafnium-containing material. The hafnium-containing material may include hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, or a combination thereof. According to another embodiment of the present invention, the high-k material may include lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, aluminum oxide, or a combination thereof. As for the high-k material, other known high-k materials may be selectively used. The gate dielectric layer  23  may include a metal oxide. The gate dielectric layer  23  may be formed conformally over the first and second sidewalls SW 1  and SW 2  of the oxide semiconductor pillar  21 P. The gate dielectric layer  23  may conformally cover the exposed sidewalls and the top surface of the sacrificial pillar  18 P. The gate dielectric layer  23  and the lower interface layer  15  may have the same thickness. According to another embodiment of the present invention, the gate dielectric layer  23  may be thinner than the lower interface layer  15 . 
     A word line conductive layer  24 A may be formed over the gate dielectric layer  23 . The word line conductive layer  24 A may be conformally formed over the gate dielectric layer  23 . The word line conductive layer  24 A may include a metal-based material. The word line conductive layer  24 A may include a metal, a metal nitride, or a combination thereof. The word line conductive layer  24 A may include tantalum nitride (TaN), titanium nitride (TiN), tungsten (W), tungsten nitride (WN), or a combination thereof. 
     Spacers  25  may be formed over the word line conductive layer  24 A. The spacers  25  may include an oxide. To form the spacers  25 , an etch-back process may be performed after depositing silicon oxide over the word line conductive layer  24 A. The upper surface of the spacers  25  may be disposed at a lower level than the upper surface of the sacrificial pillars  18 P. 
     Referring to  FIG.  2 F , tapered vertical word lines  24  may be formed. In order to form the tapered vertical word lines  24 , the word line conductive layer  24 A may be selectively etched by using the spacers  25  as an etch barrier. The spacers  25  may serve to protect the tapered vertical word lines  24  during an etching process of the word line conductive layer  24 A. In the etching process of the word line conductive layer  24 A, an etch-back process and a wet etching process may be sequentially performed. Non-tapered vertical word lines may be formed by an etch-back process, and the tapered vertical word lines  24  may be formed by the subsequent wet etching process. In other words, the bottom portion of the tapered vertical word lines  24  may become thin by the wet etching process. The tapered vertical word lines  24  may correspond to the tapered vertical word lines  124  of  FIGS.  1 A,  1 B, and  1 D , and the bottom portion of the tapered vertical word lines  24  may correspond to the lower level portion  124 L. 
     Referring to  FIG.  2 G , the spacers  25  may be removed. Each of the tapered vertical word lines  24  may have a double structure and the tapered vertical word lines  24  may be respectively formed on the first and second sidewalls of the oxide semiconductor pillars  21 P. Referring to  FIGS.  1 A,  1 B, and  1 D , the tapered vertical word lines  24  may extend in the second direction D2, and the bit lines  13  may extend in the first direction D1. The oxide semiconductor pillars  21 P and the dielectric pillars  20  may be alternately disposed in the second direction D2, and the tapered vertical word lines  24  may extend along the exposed sidewalls of the oxide semiconductor pillars  21 P and the dielectric pillar  20 . 
     Referring to  FIG.  2 H , an inter-layer dielectric layer  26  may be formed over the tapered vertical word line  24 . The inter-layer dielectric layer  26  may be planarized to expose the upper surfaces of the sacrificial pillars  18 P. The inter-layer dielectric layer  26  may include silicon oxide, such as a spin-on dielectric layer (SOD). The sacrificial pillars  18 P may serve as an etch stop layer during a planarization process of the inter-layer dielectric layer  26 . 
     Subsequently, the sacrificial pillars  18 P may be selectively removed. Accordingly, hole-shaped recessed portions  18 R may be formed. The hole-shaped recesses  18 R may selectively expose the surfaces of the upper interface layers  17 . The sacrificial pillars  18 P may be removed by using a wet etching process. 
     Referring to  FIG.  2 I , first contact plugs  27  filling the hole-shaped recesses  18 R may be formed. The first contact plugs  27  may directly contact the upper interface layers  17 . The first contact plugs  27  may include a metal, a metal nitride, or a combination thereof. For example, in order to form the first contact plugs  27 , titanium nitride may be deposited to fill the hole-shaped recesses  18 R and then titanium nitride may be planarized to expose the surface of the inter-layer dielectric layer  26 . 
     Referring to  FIG.  2 J , second contact plugs  28  may be formed over the first contact plugs  27 . The first contact plugs  27  and the second contact plugs  28  may partially overlap with each other. The second contact plugs  28  may include a metal-based material. The second contact plugs  28  may include a metal, a metal nitride, or a combination thereof. For example, the second contact plugs  28  may include tungsten. According to another embodiment of the present invention, the first contact plugs  27  and the second contact plugs  28  may be formed of the same metal-based material. 
     A metal-based material may be deposited and etched to form the second contact plugs  28 . 
     Referring to  FIG.  2 K , a spacer material layer  29  may be formed over the second contact plugs  28 . The spacer material layer  29  may include silicon nitride. The spacer material layer  29  may be formed between the neighboring second contact plugs  28 . 
     A capacitor  30  may be formed over the second contact plug  28 . 
       FIGS.  3 A to  3 E  are cross-sectional views illustrating an example of a method for forming the capacitor  30 . Hereinafter, the structures formed before the formation of the second contact plugs  28  are omitted. 
     Referring to  FIG.  3 A , an etch stop layer  31  may be formed over the second contact plugs  28  and the spacer material layer  29 . A first mold layer  32 , a first supporter layer  33 , a second mold layer  34 , and a second supporter layer  35  may be sequentially formed over the etch stop layer  31 . 
     The etch stop layer  31  may be formed of a material having an etch selectivity with respect to the first mold layer  32 . The etch stop layer  31  may include silicon nitride or silicon oxynitride. The first mold layer  32  may include a dielectric material. The first mold layer  32  may be formed of silicon oxide (SiO 2 ). The first mold layer  32  may be formed to be thicker than the first supporter layer  33 . The first mold layer  32  may be formed by using a deposition process, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD). The first mold layer  32  may include silicon oxide doped with phosphorus or silicon oxide doped with boron. The first mold layer  32  may include USG (Undoped Silicate Glass), PSG (Phosphorous Silicate Glass), BSG (Boron Silicate Glass), BPSG (Boron Phosphorous Silicate Glass), FSG (Fluorine Silicate Glass), or a combination thereof. Phosphorus-doped silicon oxide and boron-doped silicon oxide may be readily removed during the subsequent process because the etching rate with respect to an etching solution is high. 
     The first supporter layer  33  may be formed of a material having an etch selectivity with respect to the first mold layer  32  and the second mold layer  34 . The first supporter layer  33  may include silicon nitride or silicon carbon nitride (SiCN). 
     The second mold layer  34  may include a dielectric material. The second mold layer  34  may be formed of silicon oxide (SiO 2 ). The second mold layer  34  may be formed to be thicker than the first supporter layer  33 . The second mold layer  34  may be formed by a deposition process, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD). The second mold layer  34  may include phosphorus-doped silicon oxide or boron-doped silicon oxide. The second mold layer  34  may include USG, PSG, BSG, BPSG, FSG, or a combination thereof. The first mold layer  32  and the second mold layer  34  may be formed of the same material or different materials. 
     According to another embodiment of the present invention, the first mold layer  32  and the second mold layer  34  may be formed of a silicon material, such as amorphous silicon or polysilicon. 
     The second supporter layer  35  may be formed of a material having an etch selectivity with respect to the second mold layer  34 . The second supporter layer  35  may include silicon nitride or silicon carbon nitride (SiCN). 
     The first supporter layer  33  and the second supporter layer  35  may be formed of the same material or different materials. Both of the first supporter layer  33  and the second supporter layer  35  may be formed of silicon nitride. According to another embodiment of the present invention, the first supporter layer  33  may be formed of silicon nitride, and the second supporter layer  35  may be formed of silicon carbon nitride. The second supporter layer  35  may be thicker than the first supporter layer  33 . 
     According to another embodiment of the present invention, another supporter layer may be further formed. For example, the supporter structure may be a multi-level supporter layer structure. 
     Subsequently, an opening  36  may be formed. To form the opening  36 , the second supporter layer  35 , the second mold layer  34 , the first supporter layer  33 , and the first mold layer  32  may be sequentially etched by using a mask layer (not shown) as an etch barrier. An etching process for forming the opening  36  may stop at the etch stop layer  31 . To form the opening  36 , a dry etching process, a wet etching process, or a combination thereof may be used. The opening  36  may be referred to as a hole in which a lower electrode (or a storage node) is to be formed. 
     Subsequently, the etch stop layer  31  may be etched in order to expose the upper surface of the second contact plug  38  below the opening  36 . 
     Referring to  FIG.  3 B , a lower electrode  37  may be formed in the opening  36 . The lower electrode  37  may fill the inside of the opening  36 . The lower electrode  37  may include polysilicon, a metal, a metal nitride, a conductive metal oxide, a metal silicide, a noble metal, or a combination thereof. The lower electrode  37  may include at least one among titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), titanium aluminum nitride (TiAIN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO 2 ), iridium (Ir), iridium oxide (IrO 2 ), platinum (Pt), and a combination thereof. The lower electrode  37  may include titanium nitride (TiN). The lower electrode  37  may include titanium nitride (ALD-TiN) which is formed by atomic layer deposition (ALD). According to another embodiment of the present invention, the lower electrode  37  may include a hybrid structure of a titanium nitride cylinder and a polysilicon pillar. 
     Referring to  FIG.  3 C , the second supporter layer  35 , the second mold layer  34 , and the first supporter layer  33  may be sequentially etched. As a result, a supporter opening  38  exposing the first mold layer  32  may be formed, and an upper-level supporter  35 S and a lower-level supporter  33 S may be formed. 
     The upper level supporter  35 S and the lower level supporter  33 S may contact the outer wall of the lower electrode  37 . The upper-level supporter  35 S and the lower-level supporter  33 S may prevent the lower electrodes  37  from collapsing in the subsequent process of removing the second mold layer  34  and the first mold layer  32 . 
     Referring to  FIG.  3 D , the second mold layer  34  and the first mold layer  32  may be removed through the supporter opening  38 . The first and second mold layers  32  and  34  may be removed by a wet dip-out process. The wet dip-out process for removing the first and second mold layers  32  and  34  may be performed by using an etching solution capable of selectively removing the first and second mold layers  32  and  34 . When the first and second mold layers  32  and  34   include silicon oxide, the first and second mold layers  32  and  34  may be removed by a wet etching process using hydrofluoric acid (HF). 
     Referring to  FIG.  3 E , a dielectric layer  39  may be formed over the lower electrode  37  and the lower and upper level supporters  33 S and  35 S. The dielectric layer  39  may include a high-k material having a higher dielectric constant than silicon oxide. The high-k material may include hafnium oxide (HfO 2 ), zirconium oxide (ZrO 2 ), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), tantalum oxide (Ta 2 O 5 ), niobium oxide (Nb 2 O 5 ) or strontium titanium oxide (SrTiO 3 ). According to another embodiment of the present invention, the dielectric layer  39  may be formed of a composite layer including two or more layers of the above-mentioned high-k materials. According to the embodiment of the present invention, the dielectric layer  39  may be formed of a zirconium oxide-based material having excellent leakage current characteristics while sufficiently lowering the equivalent oxide thickness (EOT). For example, it may include a ZAZ (ZrO 2 /Al 2 O 3 /ZrO 2 ) stack. According to another embodiment of the present invention, the dielectric layer  27  may include a TiO 2 /ZrO 2 /Al 2 O 3 /ZrO 2  stack, a TiO 2 /HfO 2 /Al 2 O 3 /HfO 2  stack, a Ta 2 O 5 /ZrO 2 /Al 2 O 3 /ZrO 2  stack, or a Ta 2 O 5 /HfO 2 /Al 2 O 3 /HfO 2  stack. 
     Subsequently, an upper electrode  40  may be formed over the dielectric layer  39 . The upper electrode  40  may fill the space between the neighboring lower electrodes  37 . The upper electrode  40  may extend to cover the upper portions of the lower electrodes  37 . The upper electrode  40  may include a conductive material. The upper electrode  40  may be stacked (reference numerals omitted) in the order of a liner electrode, a gap-fill electrode, and a low-resistance electrode. The liner electrode of the upper electrode  40  may include titanium nitride, and the gap-fill electrode of the upper electrode  40  may include silicon germanium. The low resistance electrode of the upper electrode  40  may include tungsten or tungsten nitride. 
       FIG.  4 A  is a cross-sectional view illustrating a semiconductor device in accordance with another embodiment of the present invention. The semiconductor device  200  of  FIG.  4 A  may be similar to the semiconductor device  100  shown in  FIGS.  1 A to  1 E . Hereinafter, as for the detailed descriptions on the constituent elements which also appear in  FIGS.  1 A to  1 E , the description of  FIGS.  1 A to  1 E  may be referred to. 
     Referring to  FIG.  4 A , the semiconductor device  200  may include a peripheral circuit portion PERI including a substrate  201 , and a memory cell array MCA over the peripheral circuit portion PERI. The memory cell array MCA may include a bit line  110 , a transistor TR, and a capacitor  130 . The transistor TR may include a vertical channel transistor. The memory cell array MCA may include a plurality of memory cells sharing the bit line  110 . 
     The transistor TR may include an oxide semiconductor pillar  120  which is disposed between the bit line  110  and the capacitor  130 , a tapered vertical word line  124  which is disposed over a sidewall of the oxide semiconductor pillar  120 , and a gate dielectric layer  125  disposed between the oxide semiconductor pillar  120  and the tapered vertical word line  124 . The oxide semiconductor pillar  120  may include a lower interface layer  122 , an oxide semiconductor channel layer  121 , and an upper interface layer  123 . The lower interface layer  122 , the oxide semiconductor channel layer  121 , and the upper interface layer  123  may all include an oxide semiconductor material. The lower interface layer  122 , the oxide semiconductor channel layer  121 , and the upper interface layer  123  may all include IGZO, but the lower interface layer  122  and the upper interface layer  123  may have a greater indium concentration than the oxide semiconductor channel layer  121 . The oxide semiconductor channel layer  121  may be IGZO, and the lower interface layer  122  and the upper interface layer  123  may be indium-rich IGZO. 
     The tapered vertical word line  124  may include a lower level portion  124 L and an upper level portion  124 U. 
     The bit line  110  and a peripheral transistor PERI_TR of the peripheral circuit portion PERI may be coupled to each other through a metal interconnection MLM. The uppermost layer of the metal interconnection MLM may pass through a buffer layer  102  to be coupled to the bit line  110 . 
     The semiconductor device  200  may include a peripheral-under-cell (PUC) structure in which the memory cell array MCA is formed over the peripheral circuit portion PERI. 
       FIG.  4 B  is a cross-sectional view illustrating a semiconductor device  200 M in accordance with another embodiment of the present invention. The semiconductor device  200 M of  FIG.  4 B  may be similar to the semiconductor device  100  shown in  FIGS.  1 A to  1 E . Hereinafter, as for the detailed descriptions on the constituent elements also appearing in  FIGS.  1 A to  1 E , descriptions of  FIGS.  1 A to  1 E  may be referred to. 
     Referring to  FIG.  4 B , the semiconductor device  200 M may be an array of memory cells including a bit line  110 , an oxide semiconductor pillar  120 , and a capacitor  130 . For example, the lower level memory cell array MCA_L and the upper level memory cell array MCA_U may be vertically stacked. Each of the memory cells of the lower level memory cell array MCA_L and the upper level memory cell array MCA_U may include a bit line  110 , a transistor TR, and a capacitor  130 . The transistor TR may include a vertical channel transistor. The transistor TR may include an oxide semiconductor pillar  120  which is disposed between the bit line  110  and the capacitor  130 , a tapered vertical word line  124  which is disposed over a sidewall of the oxide semiconductor pillar  120 , and a gate dielectric layer  125  disposed between the oxide semiconductor pillar  120  and the tapered vertical word line  124 . The oxide semiconductor pillar  120  may include a lower interface layer  122 , an oxide semiconductor channel layer  121 , and an upper interface layer  123 . The lower interface layer  122 , the oxide semiconductor channel layer  121 , and the upper interface layer  123  may all include an oxide semiconductor material. The lower interface layer  122 , the oxide semiconductor channel layer  121 , and the upper interface layer  123  may all include IGZO, but the lower interface layer  122  and the upper interface layer  123  may have a higher indium concentration than the oxide semiconductor channel layer  121 . The oxide semiconductor channel layer  121  may be IGZO, and the lower interface layer  122  and the upper interface layer  123  may be indium-rich IGZO. The tapered vertical word line  124  may include a lower level portion  124 L and an upper level portion  124 U. 
     The upper electrode  136  of the lower level memory cell array MCA_L may directly contact the buffer layer  102  of the upper level memory cell array MCA_U. 
     The lower level memory cell array MCA_L and the upper level memory cell array MCA_U may be stacked without wafer bonding. 
       FIG.  5    is a cross-sectional view illustrating a semiconductor device in accordance with another embodiment of the present invention. The semiconductor device  300  of  FIG.  5    may be similar to the semiconductor device  100  of  FIGS.  1 A to  1 E . Hereinafter, as for the detailed descriptions on the constituent elements also appearing in  FIGS.  1 A to  1 E , descriptions of  FIGS.  1 A to  1 E  may be referred to. 
     Referring to  FIG.  5   , the semiconductor device  300  may include a bit line  110 , a vertical channel transistor TR, and a capacitor  130  that are disposed vertically in the third direction D3. The vertical channel transistor TR may include an oxide semiconductor pillar  120  disposed between the bit line  110  and the capacitor  130 , a tapered vertical word line  124  disposed over a sidewall of the oxide semiconductor pillar  120 , and a gate dielectric layer  125  disposed between the oxide semiconductor pillar  120  and the tapered vertical word line  124 . The oxide semiconductor pillar  120  may include a lower interface layer  122 , an oxide semiconductor channel layer  121 , and an upper interface layer  123 . The lower interface layer  122 , the oxide semiconductor channel layer  121 , and the upper interface layer  123  may all include an oxide semiconductor material. The lower interface layer  122 , the oxide semiconductor channel layer  121 , and the upper interface layer  123  may all include IGZO, but the lower interface layer  122  and the upper interface layer  123  may have a higher indium concentration than the oxide semiconductor channel layer  121 . The oxide semiconductor channel layer  121  may be IGZO, and the lower interface layer  122  and the upper interface layer  123  may be indium-rich IGZO. 
     The semiconductor device  300  may further include a dummy plate  210  below the bit line  110 . The dummy plate  210  may include a metal-based material. The buffer layer  102  may be disposed between the dummy plate  210  and the bit line  110 . Although parasitic capacitance may be increased due to the dummy plate  210 , coupling noise may be improved because the coupling capacitance ratio between the bit lines  110  is decreased. Referring to  FIGS.  1 B and  5   , the coupling capacitance ratio between the bit lines  110  that are spaced apart from each other in the second direction D2 may decrease by the dummy plate  210 . The optimal ratio of the parasitic capacitance may be controlled by adjusting the thickness of the buffer layer  102  between the dummy plate  210  and the bit line  110 . 
       FIGS.  6 A to  6 C  are cross-sectional views illustrating a method for fabricating a semiconductor device in accordance with another embodiment of the present invention. The method of fabricating the semiconductor device of  FIGS.  6 A to  6 C  may be similar to that of  FIGS.  2 A to  2 K . Hereinafter, as for the detailed descriptions on the constituent elements also appearing in  FIGS.  2 A to  2 K , descriptions of  FIGS.  2 A to  2 K  may be referred to. 
     Referring to  FIG.  6 A , a buffer layer  12  may be formed over the substrate  11 . A conductive layer  13 A, a barrier material layer  14 A, a lower interface material layer  15 A, a channel material layer  16 A, and an upper interface material layer  17 A may be sequentially formed over the buffer layer  12 . 
     Subsequently, a first contact layer  27 A and a second contact layer  28 A may be stacked over the upper interface material layer  17 A. The first contact layer  27 A may include titanium nitride, and the second contact layer  28 A may include tungsten. 
     Referring to  FIG.  6 B , line structures  19 L may be formed. Each of the line structures  19 L may include a stack of a bit line  13 , a bit line barrier layer  14 , a lower interface layer  15 B, a channel material layer  16 B, an upper interface layer  17 B, a first contact layer  27 B, and the second contact layer  28 B. First trenches  19 T may be formed between the line structures  19 L. 
     Referring to  FIG.  6 C , a portion of the line structures  19 L may be selectively etched. As a result, oxide semiconductor pillars  21 P may be formed over the bit line barrier layer  14 . Each of the oxide semiconductor pillars  21 P may include a stack of a lower interface layer  15 , a channel layer  16 , and an upper interface layer  17 . The lower interface layer  15 , the channel layer  16 , and the upper interface layer  17  may be formed by etching the lower interface layer  15 B, the channel material layer  16 B, and the upper interface layer  17 B, respectively. A stack of first contact plugs  27  and second contact plugs  28  may be formed over the upper interface layers  17 . The first contact plugs  27  may be formed by etching the first contact layer  27 B, and the second contact plugs  28  may be formed by etching the second contact layer  28 B. 
     Trenches  22  may be formed between the oxide semiconductor pillars  21 P. The first contact plugs  27  and the second contact plugs  28  may be cut by the trenches  22 , and accordingly, each of the first contact plugs  27  and the second contact plugs  28  may have a pillar shape. 
     Subsequently, a gate dielectric layer  23  may be formed on the sides of the oxide semiconductor pillars  21 P. The gate dielectric layer  23  may cover the sidewalls of the first contact plugs  27  and the second contact plugs  28 . 
     Subsequently, tapered vertical word lines  24  may be formed over the gate dielectric layer  23 . 
     Subsequently, as illustrated in  FIG.  2 K , a capacitor  30  may be formed over the second contact plugs  28 . 
       FIGS.  7 A to  7 G  are cross-sectional views illustrating a method for fabricating a semiconductor device in accordance with another embodiment of the present invention. The method of fabricating the semiconductor device of  FIGS.  7 A to  7 G  may be similar to that of  FIGS.  2 A to  2 K . Hereinafter, as for the detailed descriptions on the constituent elements also appearing in  FIGS.  2 A to  2 K , descriptions of  FIGS.  2 A to  2 K  may be referred to. 
     Referring to  FIG.  7 A , a buffer layer  12  may be formed over the substrate  11 . A conductive layer  13 A and a barrier material layer  14 A may be formed over the buffer layer  12 . 
     Subsequently, a first sacrificial layer  15 D and a second sacrificial layer  18 D may be sequentially formed over the barrier material layer  14 A. The first sacrificial layer  15 D may include polysilicon, and the second sacrificial layer  18 D may include silicon nitride. 
     Referring to  FIG.  7 B , second sacrificial layer lines  18 L may be formed. The second sacrificial layer lines  18 L may be formed by etching the second sacrificial layer  18 D. The second sacrificial layer lines  18 L may be formed by a double patterning process. 
     Subsequently, a first sacrificial layer  15 D may be etched by using the second sacrificial layer lines  18 L as an etch barrier, and the barrier material layer  14 A and the conductive layer  13 A may be etched continuously. 
     A plurality of line structures  19 L may be formed over the buffer layer  12  by a series of the etching processes described above. Each of the line structures  19 L may include a stack of a bit line  13 , a bit line barrier layer  14 , a first sacrificial layer line  15 L, and a second sacrificial layer line  18 L. The bit line barrier layer  14  may be formed by etching the barrier material layer  14 A, and the bit line  13  may be formed by etching the conductive layer  13 A. The first sacrificial layer line  15 L may be formed by etching the first sacrificial layer  15 D. First trenches  19 T may be formed between the line structures  19 L. 
     Referring to  FIG.  7 C , dielectric lines  20  may be formed between the line structures  19 L. The dielectric lines  20  may include a dielectric material. For example, the dielectric lines  20  may include silicon oxide, silicon nitride, silicon carbon oxide (SiCO), a spin-on-dielectric layer, or a combination thereof. The dielectric lines  20  may be formed by depositing a dielectric material to fill the first trenches  19 T between the line structures  19 L and performing a planarization process of a dielectric material. The dielectric lines  20  may be formed by sequentially forming a silicon nitride, a silicon carbon oxide, and a spin-on dielectric layer and performing a planarization process. 
     Referring to  FIG.  7 D , a portion of the line structures  19 L may be selectively etched to form sacrificial pillars  21 P′. The bit line barrier layer  14  and the bit line  13  may be disposed below the sacrificial pillars  21 P′. 
     Each of the sacrificial pillars  21 P′ may include a stack of a first sacrificial pillar  15 LP and a second sacrificial pillar  18 LP. The first sacrificial pillar  15 LP may be formed by etching the first sacrificial layer line  15 L, and the second sacrificial pillar  18 LP may be formed by etching the second sacrificial layer line  18 L. 
     Second trenches  22  may be formed between the sacrificial pillars  21 P′. 
     Subsequently, the gate dielectric layer  23  and the tapered vertical word line  24  may be formed by a series of the processes as illustrated in  FIGS.  2 E and  2 F . In other words, referring to  FIG.  7 E , the gate dielectric layer  23  may be formed on the sides of the sacrificial pillars  21 P′. The tapered vertical word line  24  may be formed over the gate dielectric layer  23 . The bottom portion of the tapered vertical word line  24  may have a smaller thickness than the other portions. 
     Referring to  FIG.  7 F , an inter-layer dielectric layer  26  may be formed over the tapered vertical word line  24 . The inter-layer dielectric layer  26  may be planarized to expose the upper surfaces of the second sacrificial pillars  18 LP. 
     Subsequently, the second sacrificial pillars  18 LP and the first sacrificial pillars  15 LP may be selectively removed. Accordingly, pillar-shaped openings  18 H may be formed. The bottom surface of the pillar-shaped openings  18 H may expose the surface of the barrier layer  14 . 
     Referring to  FIG.  7 G , oxide semiconductor pillars  21 P filling the pillar-shaped openings  18 H may be formed. Each of the oxide semiconductor pillars  21 P may include a stack of the lower interface layer  15 , the channel layer  16 , and the upper interface layer  17 . The lower interface layer  15 , the channel layer  16 , and the upper interface layer  17  may be formed by epitaxial growth, individually. 
     The lower interface layer  15  may contain indium. The lower interface layer  15  may include an indium-rich oxide semiconductor material. For example, the lower interface layer  15  may include indium-rich IGZO. The lower interface layer  15  may be formed to have a thickness of approximately 10 to 50 Å. 
     A channel layer  16  may be formed on the lower interface layer  15 . The channel layer  16  may contain indium. The channel layer  16  may include IGZO. The channel layer  16  may be formed to have a thickness of 200 to 1000 A. 
     An upper interface layer  17  may be formed over the channel layer  16 . The upper interface layer  17  may contain indium. The upper interface layer  17  may include an indium-rich oxide semiconductor material. For example, the upper interface layer  17  may include indium-rich IGZO. The upper interface layer  17  may be formed to have a thickness of approximately 10 to 50 Å. 
     The oxide semiconductor pillars  21 P may partially fill the pillar-shaped openings  18 H, and thus hole-shaped recesses  18 R may be defined by the oxide semiconductor pillars  21 P. 
     Subsequently, a series of the processes as described in  FIGS.  2 I to  2 K  may be performed. 
       FIGS.  8  to  10    are cross-sectional views illustrating semiconductor devices in accordance with other embodiments of the present invention.  FIGS.  8  to  10    may be similar to the semiconductor device  100  shown in  FIGS.  1 A to  1 E , and also may be similar to the semiconductor device  300  shown in  FIG.  5   . Hereinafter, as for the detailed descriptions on the constituent elements also appearing in  FIGS.  1 A to  1 E  and  FIG.  5   , descriptions of  FIGS.  1 A to  1 E  and  FIG.  5    may be referred to. 
     Referring to  FIG.  8   , the semiconductor device  400  may include a substrate  101 , a buffer layer  102 , a bit line  110 , a barrier layer  111 , an oxide semiconductor pillar  120 , a tapered vertical word line  124 , a gate dielectric layer  125 , and a capacitor  130 . The semiconductor device  400  may further include a first contact plug  126  and a second contact plug  127  between the oxide semiconductor pillar  120  and the capacitor  130 . The oxide semiconductor pillar  120  may include a lower interface layer  122 , an oxide semiconductor channel layer  121 , and an upper interface layer  123 . The lower interface layer  122 , the oxide semiconductor channel layer  121 , and the upper interface layer  123  may all include an oxide semiconductor material. The lower interface layer  122 , the oxide semiconductor channel layer  121 , and the upper interface layer  123  may all include IGZO, but the lower interface layer  122  and the upper interface layer  123  may have a higher indium concentration than the oxide semiconductor channel layer  121 . The oxide semiconductor channel layer  121  may be IGZO, and the lower interface layer  122  and the upper interface layer  123  may be indium-rich IGZO. 
     The semiconductor device  400  may further include a dummy plate  210  below the bit line  110 . The buffer layer  102  may be disposed between the dummy plate  210  and the bit line  110 . According to another embodiment of the present invention, the dummy plate  210  may be omitted. 
     The semiconductor device  400  may further include an isolating dielectric layer  401  which is disposed between the tapered vertical word line  124  and the barrier layer  111 . The isolating dielectric layer  401  may be disposed below the gate dielectric layer  125 . The isolating dielectric layer  401  may further increase the distance between the lower level portion  124 L of the tapered vertical word line  124  and the bit line  110  (refer to a reference numeral H1). 
     Referring to  FIG.  9   , the semiconductor device  410  may include a substrate  101 , a buffer layer  102 , a bit line  110 , a barrier layer  111 , an oxide semiconductor pillar  120 , a tapered vertical word line  124 , a gate dielectric layer  125 , and a capacitor  130 . The semiconductor device  410  may further include a first contact plug  126  and a second contact plug  127  between the oxide semiconductor pillar  120  and the capacitor  130 . The oxide semiconductor pillar  120  may include a lower interface layer  122 ′, an oxide semiconductor channel layer  121 , and an upper interface layer  123 . The lower interface layer  122 ′, the oxide semiconductor channel layer  121 , and the upper interface layer  123  may all include IGZO, but the lower interface layer  122 ′ and the upper interface layer  123  may have a higher indium concentration than the oxide semiconductor channel layer  121 . The oxide semiconductor channel layer  121  may be IGZO, and the lower interface layer  122 ′ and the upper interface layer  123  may be indium-rich IGZO. 
     The semiconductor device  410  may further include a dummy plate  210  below the bit line  110 . The buffer layer  102  may be disposed between the dummy plate  210  and the bit line  110 . According to another embodiment of the present invention, the dummy plate  210  may be omitted. 
     The semiconductor device  410  may further include an isolating dielectric layer  401  which is disposed between the tapered vertical word line  124  and the barrier layer  111 . The isolating dielectric layer  401  may further increase the distance between the lower level portion  124 L of the tapered vertical word line  124  and the bit line  110  (refer to a reference numeral H1). 
     The height of the lower interface layer  122 ′ of the oxide semiconductor pillar  120  may be greater than the height of the upper interface layer  123 . Also, the height of the lower interface layer  122 ′ may be greater than the height of the lower interface layer  122  of  FIG.  8   . The lower interface layer  122 ′ and the isolating dielectric layer  401  may have the same height. 
     Referring to  FIG.  10   , the semiconductor device  420  may include a substrate  101 , a buffer layer  102 , a bit line  110 , a barrier layer  111 , an oxide semiconductor pillar  120 , a tapered vertical word line  124 , a gate dielectric layer  125 , and a capacitor  130 . The semiconductor device  420  may further include a first contact plug  126  and a second contact plug  127  between the oxide semiconductor pillar  120  and the capacitor  130 . The oxide semiconductor pillar  120  may include a lower interface layer  122 ″, an oxide semiconductor channel layer  121 , and an upper interface layer  123 . The lower interface layer  122 ″, the oxide semiconductor channel layer  121 , and the upper interface layer  123  may all include IGZO, but the lower interface layer  122 ″ and the upper interface layer  123  may have a higher indium concentration than the oxide semiconductor channel layer  121 . The oxide semiconductor channel layer  121  may be IGZO, and the lower interface layer  122 ″ and the upper interface layer  123  may be indium-rich IGZO. 
     The semiconductor device  420  may further include a dummy plate  210  below the bit line  110 . The buffer layer  102  may be disposed between the dummy plate  210  and the bit line  110 . According to another embodiment of the present invention, the dummy plate  210  may be omitted. 
     The semiconductor device  420  may further include an isolating dielectric layer  401  which is disposed between the tapered vertical word line  124  and the gate dielectric layer  125 . The isolating dielectric layer  401  may be disposed over the gate dielectric layer  125 . The isolating dielectric layer  401  may further increase the distance between the lower level portion  124 L of the tapered vertical word line  124  and the bit line  110  (refer to a reference numeral H1). 
     The height of the lower interface layer  122 ″ of the oxide semiconductor pillar  120  may be greater than the height of the upper interface layer  123 . The height of the lower interface layer  122 ″ may be greater than the height of the lower interface layer  122 ′ of  FIG.  9   . According to another embodiment of the present invention, the height of the lower interface layer  122 ″ may be the same as the height of the lower interface layer  122 ′ of  FIG.  9   . According to another embodiment of the present invention, the height of the lower interface layer  122 ″ may be the same as the height of the lower interface layer  122  of  FIG.  8   . 
     In the semiconductor devices  400 ,  410 , and  420  shown in  FIGS.  8  to  10   , the tapered vertical word line  124  and the bit line  110  may be spaced apart from each other by a sufficient distance due to the isolating dielectric layer  401  and the gate dielectric layer  125  (refer to a reference numeral H1). The isolating dielectric layer  401  may include silicon oxide. 
     The gate dielectric layer  125  of the semiconductor devices  400 ,  410 , and  420  shown in  FIGS.  8  to  10    may include a vertical portion  125 V which is disposed between the oxide semiconductor pillar  120  and the tapered vertical word line  124 , and a horizontal portion  125 F which extends from the vertical portion  125 V and is disposed between the bit line  110  and the tapered vertical word line  124 . The isolating dielectric layer  401  may be disposed at a lower level than the horizontal portion  125 F of the gate dielectric layer  125  (refer to  FIGS.  8  and  9   ) or may be disposed at a higher level than the horizontal portion  125 F of the gate dielectric layer  125  (refer to  FIG.  10   ). 
       FIGS.  11 A to  14 B  are examples of a method for fabricating the semiconductor devices in accordance with  FIGS.  8  to  10   . 
       FIGS.  11 A to  11 C  are cross-sectional views illustrating a method for fabricating a semiconductor device in accordance with another embodiment of the present invention. The method for fabricating the semiconductor device of  FIGS.  11 A to  11 C  may be similar to that of  FIGS.  2 A to  2 K . Hereinafter, as for the detailed descriptions on the constituent elements also appearing in  FIGS.  2 A to  2 K , descriptions of  FIGS.  2 A to  2 K  may be referred to.  FIGS.  11 A to  11 C  illustrate the fabrication method according to the line B-B′ shown in  FIG.  1 A . 
     First, referring to  FIGS.  2 A to  2 D , a buffer layer  12  may be formed over the substrate  11 , and a bit line  13  and a barrier layer  14  may be formed over the buffer layer  12 . Subsequently, oxide semiconductor pillars  21 P including a lower interface layer  15 , a channel layer  16 , and an upper interface layer  17  may be formed over the barrier layer  14 . Sacrificial pillars  18 P may be disposed over the upper interface layer  17 . Second trenches  22  may be formed between the oxide semiconductor pillars  21 P. 
     Subsequently, referring to  FIG.  11 A , an isolating dielectric layer  31  may be formed over the barrier layer  14 . The isolating dielectric layer  31  may be formed by depositing a dielectric layer  31 A over the oxide semiconductor pillars  21 P and then performing an etch-back process onto the dielectric layer  31 A. The isolating dielectric layer  31  may include silicon oxide. The height of the isolating dielectric layer  31  may be greater than the height of the lower interface layer  15 . 
     Referring to  FIG.  11 B , a gate dielectric layer  23  may be formed over the isolating dielectric layer  31 . The gate dielectric layer  23  may be formed on the exposed sidewalls of the oxide semiconductor pillars  21 P and the sacrificial pillars  18 P. The isolating dielectric layer  31  may be disposed between the gate dielectric layer  23  and the bit line  13 . The isolating dielectric layer  31  may be disposed at a lower level than the gate dielectric layer  23 . 
     Referring to  FIG.  11 C , the tapered vertical word lines  24  may be formed. Tapered vertical word lines  24  may be formed with reference to the methods illustrated in  FIGS.  2 E to  2 G . The gate dielectric layer  23 , the isolating dielectric layer  31 , and the barrier layer  14  may be disposed between the bottom portion of the tapered vertical word lines  24  and the bit line  13 . The tapered vertical word lines  24  and the bit line  13  may be spaced apart from each other by a sufficient distance due to the isolating dielectric layer  31  and the gate dielectric layer  23  (refer to a reference numeral H1). 
       FIGS.  12 A and  12 B  are cross-sectional views illustrating a method for fabricating a semiconductor device in accordance with another embodiment of the present invention. The method for fabricating the semiconductor device of  FIGS.  12 A and  12 B  may be similar to that of  FIGS.  2 A to  2 K . Hereinafter, as for the detailed descriptions on the constituent elements also appearing in  FIGS.  2 A to  2 K , descriptions of  FIGS.  2 A to  2 K  may be referred to.  FIGS.  12 A and  12 B  may be the fabrication method according to the line B-B′ shown in  FIG.  1 A . 
     First, referring to  FIGS.  2 A to  2 D , a buffer layer  12  may be formed over the substrate  11 , and a bit line  13  and a barrier layer  14  may be formed over the buffer layer  12 . Subsequently, oxide semiconductor pillars  21 P including a lower interface layer  15 , a channel layer  16 , and an upper interface layer  17  may be formed over the barrier layer  14 . Sacrificial pillars  18 P may be disposed over the upper interface layer  17 . 
     Subsequently, referring to  FIG.  12 A , a gate dielectric layer  23  may be formed over the barrier layer  14 . The gate dielectric layer  23  may be formed on the exposed sidewalls of the oxide semiconductor pillars  21 P and the sacrificial pillars  18 P. 
     Subsequently, an isolating dielectric layer  31  may be formed over the gate dielectric layer  23 . The isolating dielectric layer  31  may be formed by depositing a dielectric layer  31 A over the gate dielectric layer  23  and performing an etch-back process onto the dielectric layer  31 A. The isolating dielectric layer  31  may include silicon oxide. The height of the isolating dielectric layer  31  may be greater than the height of the lower interface layer  15 . A gate dielectric layer  23  may be disposed between the isolating dielectric layer  31  and the bit line  13 . 
     As described above, the isolating dielectric layer  31  may be formed after the gate dielectric layer  23  is formed. 
     Referring to  FIG.  12 B , tapered vertical word lines  24  may be formed. The tapered vertical word lines  24  may be formed with reference to the methods illustrated in  FIGS.  2 E to  2 G . A gate dielectric layer  23 , an isolating dielectric layer  31 , and a barrier layer  14  may be disposed between the bottom portion of the tapered vertical word lines  24  and the bit line  13 . The tapered vertical word lines  24  and the bit line  13  may be spaced apart from each other by a sufficient distance due to the isolating dielectric layer  31  and the gate dielectric layer  23  (refer to a reference numeral H1). 
       FIGS.  13 A to  13 D  are cross-sectional views illustrating a method for fabricating a semiconductor device in accordance with another embodiment of the present invention. The method for fabricating the semiconductor device of  FIGS.  13 A to  13 D  may be similar to that of  FIGS.  2 A to  2 K . Hereinafter, as for the detailed descriptions on the constituent elements also appearing in  FIGS.  2 A to  2 K , descriptions of  FIGS.  2 A to  2 K  may be referred to.  FIGS.  13 A to  13 D  may be the fabrication method according to the line B-B′ shown in  FIG.  1 A . 
     Referring to  FIGS.  2 A and  13 A , a buffer layer  12  may be formed over a substrate  11 , and a conductive layer  13 A and a barrier material layer  14 A may be sequentially formed over the buffer layer  12 . 
     A lower interface layer  15 C may be formed over the barrier material layer  14 A. The lower interface layer  15 C may include a conductive material. The lower interface layer  15 C may include an oxide semiconductor material. The lower interface layer  15 C may contain indium. The lower interface layer  15 C may include an indium-rich oxide semiconductor material. For example, the lower interface layer  15 C may include indium-rich IGZO. The lower interface layer  15 C may be formed to have a thickness of approximately 10 to 50 Å. The lower interface layer  15 C may be thicker than the lower interface material layer  15 A shown in  FIG.  2 A . 
     A channel material layer  16 A may be formed over the lower interface layer  15 C. The channel material layer  16 A may include a conductive material. The channel material layer  16 A may include an oxide semiconductor material. The channel material layer  16 A may contain indium. The channel material layer  16 A may include IGZO. The channel material layer  16 A may be formed to have a thickness of approximately 200 to 1000 Å. 
     An upper interface material layer  17 A may be formed over the channel material layer  16 A. The upper interface material layer  17 A may include a conductive material. The upper interface material layer  17 A may include an oxide semiconductor material. The upper interface material layer  17 A may contain indium. The upper interface material layer  17 A may include an indium-rich oxide semiconductor material. For example, the upper interface material layer  17 A may include indium-rich IGZO. The upper interface material layer  17 A may be formed to have a thickness of approximately 10 to 50 Å. The upper interface material layer  17 A may be thinner than the lower interface layer  15 C. 
     As described above, the lower interface layer  15 C, the channel material layer  16 A, and the upper interface material layer  17 A may be vertically stacked over the barrier material layer  14 A. The lower interface layer  15 C, the channel material layer  16 A, and the upper interface material layer  17 A may all include an oxide semiconductor material. The lower interface layer  15 C, the channel material layer  16 A, and the upper interface material layer  17 A may all include IGZO, but the lower interface layer  15 C and the upper interface material layer  17 A may have a higher indium concentration than the channel material layer  16 A. The channel material layer  16 A may be IGZO, and the lower interface material layer  15 A and the upper interface material layer  17 A may be indium-rich IGZO. As the lower interface layer  15 C and the upper interface material layer  17 A contain a high concentration of indium, the resistance may be reduced lower than that of the channel material layer  16 A. Also, channel seamless interconnection of the channel material layer  16 A is possible. 
     Subsequently, a sacrificial layer  18 A may be formed over the upper interface material layer  17 A. The sacrificial layer  18 A may include a stack of different materials. The sacrificial layer  18 A may include silicon nitride. 
     Referring to  FIG.  13 B , a bit line  13  and a barrier layer  14  may be formed over the buffer layer  12  by a series of the processes as illustrated in  FIGS.  2 B to  2 D . Subsequently, oxide semiconductor pillars  21 P including a lower interface layer  15 ′, a channel layer  16 , and an upper interface layer  17  may be formed over the barrier layer  14 . Sacrificial pillars  18 P may be disposed over the upper interface layer  17 . Second trenches  22  may be formed between the oxide semiconductor pillars  21 P. 
     Referring to  FIG.  13 C , an isolating dielectric layer  31  may be formed over the barrier layer  14 . A method of forming the isolating dielectric layer  31  may be the same as that of  FIG.  11 A . The height of the isolating dielectric layer  31  and the lower interface layer  15 ′ may be the same as each other. 
     Referring to  FIG.  13 D , a gate dielectric layer  23  may be formed over the isolating dielectric layer  31 , and tapered vertical word lines  24  may be formed over the gate dielectric layer  23 . The tapered vertical word lines  24  may be formed with reference to the methods illustrated in  FIGS.  2 E to  2 G . A gate dielectric layer  23 , an isolating dielectric layer  31 , and a barrier layer  14  may be disposed between the bottom portion of the tapered vertical word lines  24  and the bit line  13 . The tapered vertical word lines  24  and the bit line  13  may be spaced apart from each other by a sufficient distance due to the isolating dielectric layer  31  and the gate dielectric layer  23  (refer to a reference numeral H1). 
       FIGS.  14 A and  14 B  are cross-sectional views illustrating a method for fabricating a semiconductor device in accordance with another embodiment of the present invention. The method for fabricating the semiconductor device of  FIGS.  14 A and  14 B  may be similar to that of  FIGS.  2 A through  2 K . Hereinafter, as for the detailed descriptions on the constituent elements also appearing in  FIGS.  2 A to  2 K , descriptions of  FIGS.  2 A to  2 K  may be referred to.  FIGS.  14 A and  14 B  may be the fabrication method according to the line B-B′ shown in  FIG.  1 A . 
     First, as illustrated in  FIGS.  2 A to  2 D and  13 A and  13 B , a buffer layer  12  may be formed over the substrate  11 , and a bit line  13  and a barrier layer  14  may be formed over the buffer layer  12 . Subsequently, oxide semiconductor pillars  21 P including a lower interface layer  15 ′, a channel layer  16 , and an upper interface layer  17  may be formed over the barrier layer  14 . Sacrificial pillars  18 P may be disposed over the upper interface layer  17 . 
     Subsequently, referring to  FIG.  14 A , a gate dielectric layer  23  may be formed over the barrier layer  14 . The gate dielectric layer  23  may be formed on the exposed sidewalls of the oxide semiconductor pillars  21 P and the sacrificial pillars  18 P. 
     Subsequently, an isolating dielectric layer  31  may be formed over the gate dielectric layer  23 . The isolating dielectric layer  31  may be formed by depositing the dielectric layer  31 A over the gate dielectric layer  23  and performing an etch-back process onto the dielectric layer  31 A. The isolating dielectric layer  31  may include silicon oxide. The gate dielectric layer  23  may be disposed between the isolating dielectric layer  31  and the bit line  13 . 
     As described above, the isolating dielectric layer  31  may be formed after the gate dielectric layer  23  is formed. 
     Referring to  FIG.  14 B , tapered vertical word lines  24  may be formed. The tapered vertical word lines  24  may be formed with reference to the methods shown in  FIGS.  2 E to  2 G . The gate dielectric layer  23 , the isolating dielectric layer  31 , and the barrier layer  14  may be disposed between the bottom portion of the tapered vertical word lines  24  and the bit line  13 . The tapered vertical word lines  24  and the bit line  13  may be spaced apart from each other by a sufficient distance due to the isolating dielectric layer  31  and the gate dielectric layer  23  (refer to a reference numeral H1). 
     According to the embodiment of the present invention, since a bit line and a transistor are sequentially formed by using a depositable channel material, procedural difficulty may be reduced. 
     According to the embodiment of the present invention, the degree of integration may be increased by stacking a memory cell array without wafer bonding, and the degree of integration may be improved through a peripheral-under-cell (PUC) structure where a memory cell array is formed over a peripheral circuit portion. 
     According to the embodiment of the present invention, a metal oxide, particularly IGZO, may be used as a channel material to suppress gate-induced drain leakage and junction leakage so as to improve retention characteristics. 
     The effects desired to be obtained in the embodiments of the present invention are not limited to the effects mentioned above, and other effects not mentioned above may also be clearly understood by those of ordinary skill in the art to which the present invention pertains from the description below. 
     While the present invention has been described with respect to the specific embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.