Patent Publication Number: US-11394303-B2

Title: Flyback converter with synchronous rectifier switch fault detection

Description:
TECHNICAL FIELD 
     This application relates to switching power converters, and more particularly to flyback converters with synchronous rectifier switch fault detection. 
     BACKGROUND 
     As known in the flyback arts, a secondary-winding current in a flyback converter&#39;s transformer is rectified so as to not conduct while the primary-winding current conducts. This rectification may be performed by an output diode or by a synchronous rectifier switch transistor. Although an output diode is passive and thus requires no synchronous rectifier control, the use of an output diode lowers efficiency as compared to a flyback converter with synchronous rectification. Synchronous rectification is thus broadly used to improve efficiency. 
     The synchronous rectifier switch transistor is typically a metal-oxide-semiconductor field-effect transistor (MOSFET). To control the switching of a synchronous rectifier (SR) switch MOSFET, an SR controller monitors the drain-to-source voltage across the SR MOSFET. Based upon the drain-to-source voltage, the SR controller detects whether the power switch transistor has cycled off so that the SR MOSFET may be switched on. For example, if the SR MOSFET is an n-type metal-oxide semiconductor (NMOS) transistor, the SR controller switches on the SR MOSFET by increasing a gate-to-source voltage for the SR MOSFET above its threshold voltage. 
     But like any semiconductor device, the SR switch transistor is subject to manufacturing defects. For example, the SR switch transistor may be only slightly on (a partially-open fault condition) or off (an open fault condition) despite its threshold voltage being satisfied. In addition, to such partially-open or fully-open fault conditions, the gate of the SR switch transistor may be shorted to ground (a gate-to-ground short-circuit fault condition) or shorted to the source of the SR switch transistor (a gate-to-source short-circuit fault condition). 
     As a result of these fault conditions, the drain current that would ordinarily conduct through the channel of the SR switch transistor instead conducts through its body diode. The conduction through the body diode instead of the channel results in a relatively-high drain-to-source voltage across the SR switch transistor, which causes thermal stress to the power supply. The detection of an open fault condition, a partially-open fault condition, a gate-to-ground short-circuit fault condition, and a gate-to-source short-circuit fault condition is thus critical to the power supply reliability. Despite this criticality, existing fault condition techniques typically cannot detect the partially-open fault condition. 
     In a conventional SR switch transistor fault detection, a current source is applied to the gate of the SR switch transistor while a rate of change (dV/dt) for the drain-to-source voltage (Vds) across the SR switch transistor is detected to determine the gate-to-source capacitance for the SR switch transistor. If the gate-to-source capacitance is less than a first threshold amount, a gate open fault is deemed to be detected. Conversely, if the gate-to-source capacitance is higher than a second threshold amount, a gate-to-source short-circuit fault condition is deemed to be detected. The resulting conventional fault detection is only applicable during a start-up stage and cannot detect a partially-open fault condition, which is problematic with regard to ensuring reliability of the flyback converter. 
     Accordingly, there is a need in the art for flyback converters with improved fault detection for the operation of the synchronous rectifier switch transistor. 
     SUMMARY 
     In accordance with a first aspect of the disclosure, a secondary-side controller for a flyback converter is provided that includes: a gate driver for controlling a cycling of a synchronous rectifier switch transistor; a drain terminal for connecting to a drain of the synchronous rectifier switch transistor; a timer for timing a detection period beginning when the gate driver switches on the synchronous rectifier switch transistor and ending when a voltage of the drain terminal exceeds a negative voltage threshold; and a logic circuit configured to compare the detection period to a threshold period to detect whether the synchronous rectifier switch transistor has a partially-open fault condition or an open fault condition. 
     In accordance with a second aspect of the disclosure, a secondary-side controller for a flyback converter is provided that includes: a gate driver for controlling a cycling of a synchronous rectifier switch transistor through a gate terminal; a timer for timing a detection period beginning when the gate driver switches on the synchronous rectifier switch transistor and ending when a voltage of the gate terminal exceeds a positive threshold voltage; and a logic circuit configured to detect whether the synchronous rectifier switch transistor has a gate open fault condition responsive to the detection period being shorter than a first threshold period. 
     In accordance with a third aspect of the disclosure, a method of detecting a fault condition for a synchronous rectifier switch transistor in a flyback converter is provided that includes: switching on the synchronous rectifier switch transistor; while the synchronous rectifier switch transistor is on, beginning a timing of a first detection period responsive to a drain-to-source voltage of the synchronous rectifier switch transistor being greater than a negative threshold voltage; ending the timing of the first detection period responsive to switching off of the synchronous rectifier switch transistor; and detecting a partially-open fault condition for the synchronous rectifier switch transistor responsive to the first detection period being shorter than a first threshold period. 
     These and other aspects of the invention will become more fully understood upon a review of the detailed description, which follows. Other aspects, features, and embodiments will become apparent to those of ordinary skill in the art, upon reviewing the following description of specific, exemplary embodiments in conjunction with the accompanying figures. While features may be discussed relative to certain embodiments and figures below, all embodiments can include one or more of the advantageous features discussed herein. In other words, while one or more embodiments may be discussed as having certain advantageous features, one or more of such features may also be used in accordance with the various embodiments discussed herein. In similar fashion, while exemplary embodiments may be discussed below as device, system, or method embodiments it should be understood that such exemplary embodiments can be implemented in various devices, systems, and methods. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  illustrates a flyback converter including a secondary-side controller configured to detect synchronous rectifier switch transistor fault conditions including a partially-open fault condition, an open fault condition, a gate open fault condition, and a gate short-circuit fault condition in accordance with an aspect of the disclosure. 
         FIG. 2  illustrates the drain-to-source voltage monitoring features of the secondary-side controller of  FIG. 1  for the detection of the partially-open and open fault conditions in accordance with an aspect of the disclosure. 
         FIG. 3A  illustrates some operating waveforms for the secondary-side controller of  FIG. 2  during normal (no fault) operation. 
         FIG. 3B  illustrates some operating waveforms for the secondary-side controller of  FIG. 2  during operation with a fault condition. 
         FIG. 4  illustrates the gate terminal voltage monitoring features of the secondary-side controller of  FIG. 1  for the detection of the gate open and the gate short-circuit fault conditions in accordance with an aspect of the disclosure. 
         FIG. 5A  illustrates some operating waveforms for the secondary-side controller of  FIG. 4  during normal (no fault) operation. 
         FIG. 5B  illustrates some operating waveforms for the secondary-side controller of  FIG. 4  during operation with a gate open fault condition. 
         FIG. 5C  illustrates some operating waveforms for the secondary-side controller of  FIG. 4  during operation with a gate short-circuit fault condition. 
     
    
    
     Embodiments of the present disclosure and their advantages are best understood by referring to the detailed description that follows. It should be appreciated that like reference numerals are used to identify like elements illustrated in one or more of the figures. 
     DETAILED DESCRIPTION 
     Flyback converters are provided in which a secondary-side controller monitors the drain-to-source voltage (Vds) of the SR switch transistor while the SR switch transistor is cycled to detect both open fault conditions and partially-open fault conditions. The following discussion will be directed to embodiments in which the secondary-side controller is also the SR switch controller but it will be appreciated that the SR switch transistor fault monitoring and the SR switch control may be implemented in separate integrated circuits. An open fault condition occurs when the drain current for the SR switch transistor conducts entirely through the body diode such that the channel is closed (non-conducting). In contrast, the channel conducts some current in a partially-open fault condition such that the drain current is split between the partially-closed channel and the body diode. In addition, flyback converters are provided in which the secondary-side controller monitors a gate driver voltage that controls the SR switch transistor to detect a gate open fault condition or a gate short-circuit fault condition. A gate short-circuit fault condition may be caused by a gate-to-ground short circuit or a gate-to-source short circuit. 
     Turning now to the drawings, a flyback converter  100  with a fault-monitoring secondary-side SR controller  120  is shown in  FIG. 1 . Flyback converter  100  is powered by a rectified input voltage Vin such as produced by a diode bridge  112  that rectifies an AC voltage VAC from an AC mains. The input voltage Vin is carried on an input rail  114  and supported by an input capacitor Cin that couples between input rail  114  and a primary-side ground. A primary-side controller  118  controls the cycling of a power switch transistor SW to regulate an output voltage Vout supplied to a load  130 . When primary-side controller  118  switches on the power switch transistor SW, a primary-winding current conducts through a primary winding  108  of a transformer T 1 . A sense resistor Rs connects between a drain of the power switch transistor SW and the primary-side ground. The primary-winding current thus flows through the sense resistor Rs and develops a sense resistor voltage across the sense resistor Rs that is sensed by primary-side controller  118 . When the sense resistor voltage reaches a desired peak (Vipk), primary-side controller  118  switches off the power switch transistor SW. 
     SR controller  120  detects whether the power switch transistor SW is on or off by monitoring a drain-to-source voltage Vds across an SR switch transistor. To perform this monitoring, SR controller  120  has a drain monitoring terminal SR_D and a source monitoring terminal SR_S. In addition, SR controller  120  includes a gate terminal SR_G that connects to a gate of the SR switch transistor to control whether the SR switch transistor is on or off. In response to detecting that the power switch transistor SW is on, SR controller  120  maintains the SR switch transistor off to prevent a secondary-winding current from flowing in a secondary winding  110  of the transformer T 1 . In response to detecting that the power switch transistor SW is off, SR controller  120  switches on the SR switch transistor to let the secondary-winding current flow and charge an output capacitor Cout with the output voltage. Rather than monitor the drain-to-source voltage of the SR switch transistor to determine the switching state of the power switch transistor, SR controller  120  may instead receive a switch on or off status for the power switch transistor SW through an isolating channel  125  such as an optocoupler in alternative embodiments. 
     The faulting monitoring by SR controller  120  of fault conditions for the SR switch transistor will now be discussed in more detail. The drain-to-source voltage monitoring to detect open or partially-open fault conditions will be discussed first followed by a discussion of the gate driver voltage monitoring to detect the gate open or gate short-circuit fault conditions. The drain-to-source voltage monitoring features of SR controller  120  are shown in more detail in  FIG. 2 . Since the source voltage of the SR switch transistor is a secondary-side ground, SR controller  120  may monitor the drain-to-source voltage of the SR switch transistor by monitoring the drain voltage as received through its drain monitoring terminal SR_D. Note that a partially-open fault condition or an open fault condition for the SR switch transistor causes the drain-to-source voltage to be significantly more negative than normal while the SR switch transistor is on due to the conduction through the SR switch transistor&#39;s body diode. SR controller  120  advantageously exploits this negative behavior of the drain-to-source voltage through the inclusion of a comparator  205  that compares the drain voltage to a negative threshold voltage. In some embodiments, the negative threshold voltage should be lower than the body diode drop at higher operating temperatures but higher than the drain-to-source resistance-caused drop in the drain-to-source voltage at these higher operating temperatures. Since both these drops have a positive coefficient with respect to temperature increases, a threshold adaptation circuit  235  may adaptively lower the negative threshold voltage at higher operating temperatures. In the following discussion, it will be assumed that a default value for the negative threshold voltage is −280 mV but it will be appreciated that the default value and any adaptation of this default value will depend upon the particular semiconductor process node used to manufacture the SR switch transistor. In some embodiments, the SR switch transistor is a discrete device that is not integrated with the integrated circuit that includes SR controller  120 . 
     Comparator  205  receives the drain voltage at its non-inverting input such that comparator  205  will charge its output signal (designated as Comp_SRGO) to a power supply voltage in response to the drain-to-source voltage being greater than the negative threshold voltage. However, it will be appreciated that in alternative embodiments, comparator  205  may be in an active-low configuration such that the drain voltage is received at its inverting input. As used herein, a binary signal such as a comparator output signal is deemed to be asserted if the binary signal is true, regardless of whether the comparator is in an active-high or active-low configuration. 
     A timer  210  begins counting cycles of a clock signal from a clock  220  in response to the assertion of the comparator output signal Comp_SRGO to begin timing a detection period T. Timer  210  stops counting for the detection period T when a gate driver  215  switches off the SR switch transistor. In an NMOS embodiment, gate driver  215  discharges the gate terminal SR_G to ground to switch off the SR switch transistor. Timer  210  responds to the discharge of the gate terminal SR_G by stopping the counting. A logic circuit  230  then examines a resulting count from counter  210  to detect the partially-open and open fault conditions. In particular, a partially-open fault condition or an open fault condition for the SW switch transistor is deemed to be detected when logic circuit  230  determines that the count (the detection period T) is less than a threshold count. A partially-open or open fault condition is thus detected in response to the detection period T being less that a threshold period. In alternative embodiments, the timing of the detection period T may be performed using analog circuits rather than through timer  210 . For example, a current source may be configured to charge a capacitor according to an RC time constant in response to the assertion of the comparator output signal Comp_SRGO. The current source would then stop charging the capacitor in response to gate driver  215  switching off the SR switch transistor. The resulting voltage on the capacitor is thus proportional to the detection period T during which the capacitor was charged. The analog timing of detection period T is thus analogous to the timing by counter  210  except that it was performed in the analog domain. 
     Regardless of whether a detection period T between the crossing of the negative threshold voltage and the switching off of the SR switch transistor is measured in the digital domain as discussed with regard to timer  210  and logic circuit  230  or in the analog domain, a fault condition is detected in response to the detection period T being less than the threshold period. This may be better appreciated with reference to the example operating waveforms shown in  FIGS. 3A and 3B .  FIG. 3A  shows the drain voltage waveform in relation to the comparator output signal Comp_SRGO and the SR_G terminal voltage waveforms in the absence of a fault condition (normal operation) for the SR switch transistor. Since the channel is operating normally, the body diode for the SR switch transistor is conducting negligible current such that the drain-to-source voltage for the SR switch transistor is not strongly negative while the SR switch transistor is conducting (the SR_G terminal voltage thus being charged high). The SR switch transistor begins conducting at a time T 0 . Since the source-to-drain voltage is not being pulled strongly negatively by a body diode conduction, the drain voltage crosses the negative threshold voltage of −280 mV at a time T 1  that occurs well before (e.g., approximately 1 μs before) a time T 2  when the SW switch transistor stops conducting. The detection period T in  FIG. 3A  is thus approximately 1 μs. This detection period T is the delay between the negative threshold voltage crossing at time T 1  and the SR switch transistor switch-off at time T 2 . 
     In contrast, the SR switch transistor has a partially-open fault (or open fault) condition in the waveforms of  FIG. 3B . In  FIG. 3B , the SR switch transistor is again switched on at a time T 0  and switched off at a time T 2 . But since the drain-to-source voltage is being pulled more strongly negative due to the body diode conduction caused by the fault condition, the drain voltage only rises above the negative threshold voltage at a time T 1  that occurs just before time T 2 . The detection period T in  FIG. 3B  is thus relatively short, e.g., approximately 400 ns. 
     Referring again to  FIG. 1 , SR controller  120  may respond to the fault detection by stopping the cycling of the power switch transistor SW. For example, SR controller  120  could communicate the detection of the partially-open/open fault condition by a transmission of an alarm signal through the ground-isolating channel  125  such as an optoisolator or a digital isolator. In addition (or alternatively), SR controller  120  may notify a user of the fault detection such as by communicating the detection of the fault through a USB cable being used to charge a cellular telephone. 
     The gate drive voltage monitoring features for SR controller  120  for the detection of a gate open fault condition and/or a gate short-circuit fault condition are shown in  FIG. 4 . SR gate driver  215  includes a pull-up PMOS transistor P 1  having a source connected to a power supply node for a power supply voltage Vdrive and a drain connected to the gate terminal SR_G. SR gate driver  215  also includes a pull-down NMOS transistor M 1  having a source connected to ground and a drain connected to the gate terminal SR_G. During normal operation, an active-low pull-up signal Spu drives the gates of transistors P 1  and M 1  to control whether the SR switch transistor is on or off. When the SR switch transistor is to be switched on, the pull-up signal Spu is discharged to switch on the pull-up transistor P 1  to charge the gate terminal SR_G to the power supply voltage Vdrive. The discharging of the pull-up signal Spu switches off the pull-down transistor M 1 . When the SR switch transistor is to be switched off, the pull-up signal Spu is charged to a controller power supply voltage to switch on the pull-down transistor M 1  and to switch off the pull-up transistor P 1 . The switching on of the pull-down transistor M 1  discharges the gate terminal SR_G to switch off the SR switch transistor. 
     To be able to detect the gate open or gate short-circuit fault conditions during normal operation, SR gate driver  215  also drives a fault detection circuit  405  that measures a detection period T 2  that corresponds to a delay from when SR gate driver  215  begins a pull-up of the SR_G terminal voltage to when the SR_G terminal voltage crosses a positive threshold voltage Vdet_ref such as one-half the power supply voltage Vdrive. If the detection period T 2  is too long as compared to a no-fault delay, a gate short-circuit fault condition is deemed to be detected. Conversely, if the detection period T 2  is too short, a gate open fault condition is deemed to be detected. 
     The rise time of the SR_G terminal voltage as related to these fault conditions may be better appreciated through the following discussion. As seen in  FIG. 4 , the gate terminal SR_G of SR controller  120  connects to the gate (G) of the SR switch transistor through a gate resistor Rg. The SR switch transistor also has a gate-to-source capacitance Cgs between its gate G and its source S. During pull-up of the SR_G terminal, SR gate driver  215  has a pull-up resistance Rpu that includes an on-resistance of the pull-up transistor P 1 . Given these factors, it can be shown that the gate voltage as a function of time (Vg(t)) during the pull-up of the SR_G terminal may be expressed as:
 
 Vg ( t )= V drive(1− e   −t/τ )
 
where the time constant τ equals (Rpu+Rg)*Cgs. Similarly, the SR_G terminal voltage as a function of time (VSR_G(t)) during the pull-up may be expressed as
 
     
       
         
           
             
               VSR_G 
               ⁢ 
               
                 ( 
                 t 
                 ) 
               
             
             = 
             
               Vdrive 
               ⁡ 
               
                 ( 
                 
                   1 
                   - 
                   
                     
                       Rpu 
                       
                         Rpu 
                         + 
                         Rg 
                       
                     
                     ⁢ 
                     
                       e 
                       
                         
                           - 
                           t 
                         
                         ⁢ 
                         
                           / 
                         
                         ⁢ 
                         τ 
                       
                     
                   
                 
                 ) 
               
             
           
         
       
     
     If the gate resistance Rg is appreciable compared to the pull-up resistance Rpu or even larger, the measurement of the detection period T 2  becomes problematic due to the resulting rapid increase in the SR_G terminal voltage. To ease the measurement of the detection period T 2 , SR gate driver  215  may include a second pull-up PMOS transistor P 2  arranged in parallel with pull-up transistor P 1 . A fault detection active-low pull-up signal Sdet controls the gate of PMOS transistor P 2  and pull-down transistor M 1  during a fault detection mode. Pull-up transistor P 2  is sized to be several times smaller than pull-up transistor P 1  so that a detection pull-up resistance Rdet of SR gate driver  215  during a fault detection mode of operation is several times larger than pull-up resistance Rpu. During a fault measurement, pull-up transistor P 1  is not used but instead it is pull-up transistor P 2  that does the charging of the gate terminal SR_G voltage. The SR_G terminal voltage as a function of time (VSR_G(t)) during the pull-up in the fault detection mode may thus be expressed as 
               VSR_G   ⁢     (   t   )       =     Vdrive   ⁡     (     1   -       Rdet     Rdet   +   Rg       ⁢     e       -   t     ⁢     /     ⁢   τ1           )             
where the time constant τ1 equals (Rdet+Rg)*Cgs. Time constant τ1 is greater than time constant τ to slow the increase in the SR_G terminal voltage. In some applications, Rdet may be 20 or 30 ohms. Due to the relatively large resistance Rdet, the turn-on time for the SR switch transistor is increased but this increase is negligible since the default detection mode may be run relatively infrequently during operation. For example, the fault detection mode may be used to cycle on the SR switch transistor once every 1000 cycles.
 
     Fault detection circuit  405  includes a counter or timer  415  that begins counting the detection period T 2  responsive to cycles of a clock signal from a clock  420  when the fault detection active-low pull-up signal Sdet is asserted. A comparator  410  compare the SR_G terminal voltage to the positive threshold voltage Vdet_ref (e.g., one-half the power supply voltage Vdrive). When the SR_G terminal voltage rises to equal the positive threshold voltage Vdet_ref, comparator  410  asserts its output signal Vdet_out to stop counter  415  from counting. A logic circuit  425  then compares the resulting period T 2  to a no-fault period range that extends from a minimum value (denoted as Tgood) to a maximum value (denoted as Tshort). It will be appreciated that timer  415  may also be implemented in the analog domain analogously as discussed for timer  210 . If the period T 2  is within the no-fault period range such that Tgood≤T 2 ≥Tshort, then logic circuit  425  does not detect any faults. But if T 2 &lt;Tgood or T 2 &gt;Tshort, then logic circuit  425  asserts a fault detection signal. The minimum value may also be denoted herein as a second threshold period. Similarly, the maximum period Tshort may be denoted herein as a third threshold period. As discussed with regard to the detection of partially-open and open fault conditions, SR controller  120  may command a cessation of the cycling of the power switch transistor SW due to a detection of a gate open or gate short-circuit fault condition through a corresponding alarm signal transmitted through the isolating channel  125  (e.g., a command transmitted through an optoisolator). Similarly, SR controller  120  may notify a user of the detected fault through such as through a message transmitted through a USB cable to the user&#39;s smartphone. 
     Some example waveforms for the detection of gate open and gate short-circuit fault conditions by fault detection circuit  405  are shown in  FIGS. 5A, 5B, and 5C . Although Sdet may be an active-low signal, it is shown as active-high in  FIGS. 5A-5C  for illustration purposes. The SR_G terminal voltage waveform is designated as VSR_G. In  FIG. 5A , the assertion of the Vdet_out output signal from comparator  410  occurs after the assertion of the Sdet signal such that the detection period T 2  is greater than the minimum period Tgood and less than the maximum period Tshort.  FIG. 5A  thus corresponds to normal operation in which no gate open or gate short-circuit condition is detected. In  FIG. 5B , the assertion of the Vdet_out output signal occurs relatively quickly after the assertion of the Sdet signal such that the detection period T 2  is less than the minimum period Tgood.  FIG. 5B  thus corresponds to a detection of a gate open fault condition. In  FIG. 5C , the assertion of the Vdet_out output signal occurs relatively slowly after the assertion of the Sdet signal such that the detection period T 2  is greater than the maximum period Tshort.  FIG. 5C  thus corresponds to a detection of a gate short-circuit fault condition. It will thus be appreciated that fault detection circuit  405  distinguishes between gate open fault conditions and gate short-circuit fault conditions. These fault conditions may thus be communicated using separate alarm signals so that a user may be alerted of the fault identity. 
     Those of some skill in this art will by now appreciate that many modifications, substitutions and variations can be made in and to the materials, apparatus, configurations and methods of use of the devices of the present disclosure without departing from the scope thereof. In light of this, the scope of the present disclosure should not be limited to that of the particular embodiments illustrated and described herein, as they are merely by way of some examples thereof, but rather, should be fully commensurate with that of the claims appended hereafter and their functional equivalents.