Patent Publication Number: US-6657279-B1

Title: PNP lateral bipolar electronic device and corresponding manufacturing process

Description:
This application is a divisional of U.S. patent application Ser. No. 09/087,397, filed May 29, 1998, which has issued as U.S. Pat. No. 6,146,956. 
    
    
     TECHNICAL FIELD 
     This invention relates to an integrated circuit having a PNP bipolar electronic device. 
     In particular, the present invention relates to a lateral PNP bipolar electronic device which is integrated monolithically on a semiconductor substrate together with other bipolar devices of the NPN type. 
     BACKGROUND OF THE INVENTION 
     As is well known, preference is given to NPN transistors for implementing integrated circuitry of the bipolar type on semiconductor substrates, on account of their direct and alternating current amplifications being definitely better than those of PNP transistors. 
     Another disadvantage of PNP bipolar transistors is their close limitations in high frequency applications. 
     Despite all this, the inclusion of both NPN and PNP transistors on a common semiconductor substrate is still a necessity where suitable bias circuits, current mirror circuits and/or load devices for gain stages are to be provided. 
     The formation of PNP transistors on a semiconductor substrate is effected concurrently with that of NPN transistors, without any additional implanting or masking steps. 
     It is for this reason that it has become common practice to form PNP bipolar transistors of the so-called lateral type such that they can be compatible with the process flows adopted to fabricate NPN bipolar devices. 
     In this respect, FIG. 1 shows an enlarged cross-sectional view, taken on a vertical plane, of a lateral PNP device  6  formed on a P-type semiconductor substrate  1 . 
     The following are successively deposited onto this substrate  1 : a first buried layer  2  doped N+ to form the base region of the transistor, and a second layer  3 , doped N, which constitutes the active area of the PNP device to be. 
     Thereafter, a selective diffusion of P-type dopants is effected in the active area  3  to define a central emitter region  4  surrounded by collector  5 . 
     This solution has been widely used heretofore, to the point that a text, “Design and Realization of Bipolar Transistors”, Peter Ashburn, page 157, gives it as the principal configuration for a lateral PNP device that can ensure of a good current gain. 
     It should be noted that such lateral PNP transistors have an intrinsic current loss of about 3% compared to their respective collector currents; these currents can also be explained theoretically by having reference to the diagram in FIG. 2 of an equivalent electric circuit of a lateral PNP transistor. 
     It can be seen in FIG. 2 that the lateral PNP device, designated Q 1  in the equivalent circuit, is connected to a pair of parasitic PNP transistors Q 2  and Q 3  having their emitter regions connected to the emitter and collector regions, respectively, of the transistor Q 1 . 
     In addition, these parasitic devices Q 2  and Q 3  have their collector regions connected to the semiconductor substrate, and their base regions in common with the base region of Q 1 . 
     This equivalent electric circuit diagram shows that the parasitic currents are mainly attributable to the second parasitic device Q 2  draining toward the substrate some of the current being injected by the emitter of Q 1 , thereby lowering the efficiency of lateral emission. 
     Similar considerations apply to the third parasitic device Q 3 , which contributes instead to lowering the collection efficiency of the collector of Q 1  when the latter is biased into its saturation range. 
     To overcome drawbacks of this kind, tied to the parasitic currents, a conventional solution has been that of optimizing the efficiency of collection of the carriers in the collector region, so as to maximize the gain of lateral transistors. 
     For this reason, lateral PNP transistors have been implemented conventionally with their emitter region occupying, in the active area, a central position surrounded by two collector regions. 
     While being in many ways advantageous, this prior solution has a serious drawback in that it leads to increased values of certain characteristic parameters of the lateral PNP transistor, such as the base-collector and emitter-base capacitances, C bc  and C eb , which restrict performance at high frequencies. 
     This drawback is also connected with the considerable spread of the base region in the buried layer brought about by the need to control the lateral PNP device performance in the emitter and collector regions. 
     Particularly, a width W b  of this base region adversely affects the carrying parameter B*, which is tied to the W b  by the following formula:                B   *     ≈     1   -                    Wb   2         2      D                 τ                 (   1.1   )                         
     where D is the diffusion value, and t is the re-combination time of the carriers. 
     It should be noted that the B* factor is inversely proportional to a passage time through the base region, so that as it increases, the frequency performance of the lateral PNP device deteriorates. 
     Unfortunately, this type of lateral PNP device reveals serious limitations when attempts are made to improve its high frequency performance. 
     These limitations come from the practical impossibility of bringing the collector regions closer to the central emitter region. 
     This is both attributable to the photolithographic masks used for transferring the patterns of the active region, and to side diffusion effects during the formation of the emitter and collector regions, as well as to breakdown effects which may occur in a region between the base and the collector. 
     Consequently, the width W b  of the base region of the lateral PNP transistors always exhibits values between 2 μm and 4 μm. 
     FIG. 3 is a vertical cross-section view, to an enlarged scale, of a conventional lateral PNP transistor, highlighting polysilicon contacts  10  above the emitter  4  and collector  5  regions. 
     These contacts  10  are characterized by the presence of so-called “bird&#39;s beaks” which jut out sideways from the emitter and collector regions. The possibility of altering the width Wb of the base channel is usually hindered by the bird&#39;s beak protrusions. 
     In fact, calling W PPL  the distance between the emitter and the collector, L BB  the reach of the bird&#39;s beak, and D the misalignment between the polysilicon contact layer  10  and the active area, then: 
     
       
           W   B   &gt;W   PPL +2 *L   BB +2 *D   
       
     
     And substituting for some real sample values of such distances, we get: 
     
       
           W   B ≦1.0+2*0.5+2*0.4=2.8 μm 
       
     
     
       
           W   B ≦1.0+2*0.5+2*0.15=2.3 μm. 
       
     
     Thus, the heaviest restriction on the reduction of the base channel width appears to be due to the process implementation, rather than to its topography. 
     From FIG. 4, showing a schematic detail view of FIG. 3, it is evinced that the bird&#39;s beak partly overlaps the active area and that a window through which the implantation of BF 2  is effected is reduced accordingly. 
     This results in the creation of a P + -N junction within the polysilicon layer deposited, which keeps the base and collector currents far from the ideal. 
     SUMMARY OF THE INVENTION 
     In light of the foregoing considerations, an object of this invention is to provide a new topography conferring, on a lateral PNP device, such structural and functional features as to make it suitable for high frequency applications as well, thereby overcoming the aforesaid limitations and drawbacks. 
     Another object of this invention is to define the width of the base channel by way of the emitter structure. Particularly, an object of this invention is to reduce substantially the width of the base channel. In fact, a reduction in the base channel width would ensure an improved value of the carrying factor B*. 
     These and other objects of the present invention can be accomplished by providing a lateral PNP bipolar transistor having a substrate doped with impurities of the P type, a first buried layer doped with impurities of the N type to form a base region, and a second layer, overlying the first layer and having a conductivity of the N type, to form an active area with collector and emitter regions being formed in said active area and separated by a base channel region wherein a width of the base channel region is defined essentially by a contact opening formed above an oxide layer deposited over the base channel region. 
    
    
     The features and advantages of the inventive device will be apparent from the following description of the embodiment thereof, given by way of non-limitative example with reference to the accompanying drawings. 
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is an enlarged-scale sectional view taken on a vertical plane of a lateral PNP device integrated on a semiconductor substrate, according to the prior art. 
     FIG. 2 shows schematically an equivalent electric circuit of a lateral PNP device integrated on a semiconductor substrate, according to the prior art. 
     FIG. 3 is an enlarged-scale sectional detail view, taken on a vertical plane, of a lateral PNP device integrated on a semiconductor substrate, according to the prior art. 
     FIG. 4 is a partly enlarged detail view of FIG.  3 . 
     FIGS. 5 to  7  are vertical cross-section and time succession views, respectively showing schematically a portion of the semiconductor substrate whereon a lateral PNP device according to the invention is formed. 
     FIGS. 8 to  10  are schematic vertical cross-section and time succession views, respectively showing schematically a portion of the semiconductor substrate whereon a vertical NPN device is formed. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Referring to FIGS. 5-7, a preferred embodiment of a lateral PNP device  15  monolithically integrated on a semiconductor substrate together with other NPN devices, shown in FIGS. 8-10, will now be described. The device  15  can be advantageously operated even at high frequencies. 
     A multilayer structure, electrically isolated from other integrated devices by the selective growing of isolation oxide regions  11 , has been formed on a P-type semiconductor substrate  23 . 
     This multilayer structure is produced by successive deposition, onto the substrate  23 , of a first buried layer  20  doped for conductivity of the N type to form a base region, and of a second epitaxial layer  13 , over the first buried layer  20 , with conductivity of the N 31   type representing an active area of the lateral PNP device  15 . 
     A fabrication process for the present invention includes the definition of an emitter region  14  and a collector region  12 . 
     For this purpose, a first step of selectively diffusing P-type dopants onto predetermined portions of the surface of the active area is carried out. At the end of this operation, the emitter region  14  will be locate peripherally to the active area, opposite from the collector region  12 . 
     At this point, a polysilicon layer  16  is deposited onto the substrate surface and capped with a protective layer  17  of vapor deposited oxide (VAPOX). This layer  17  can be formed by oxidation of the polysilicon  16 . 
     By a subsequent dry etching step, an opening  18  is defined through the layers  17  and  16 , above the field oxide  11 . This etching is carried out with the assistance of an emitter mask, called the EMI mask, being shifted to the appropriate location. 
     The opening  18  is defined in the same manner as an opening  18 ′ during the formation of the NPN transistors included in the same integrated circuit, as shown in FIG.  8 . 
     This step allows the emitter  14  and collector  12  regions to be separated from each other and prevents misalignment of the masks. 
     A layer  19  of nitride is then deposited through the opening  18  and caused to adhere on the side walls of the opening. 
     A pair of spacers  21  are successively formed within the opening  18  over the nitride layer  19 . 
     The spacer structure  21  is self-aligned to the spacer structure formed in the NPN transistors, as shown in FIGS. 6 and 9. 
     The process of this invention further includes a step of forming an N-doped polysilicon contact  22 . The contact is formed at the location of the opening  18  and allowed to reach the surface of the oxide  11 . 
     A similar N-poly contact is also formed in the window  18 ′ overlying the active areas of the NPN transistors. 
     The polysilicon contact  22  is then contacted by a first metallization layer (not shown) formed on either the emitter or the collector side. 
     FIG. 7 clearly shows the width of the base channel region, comprising a middle portion with a width W E  and two opposite regions with a width D formed from the portion of the layer  16  that overlaps the oxide region  11 . 
     Thus: 
     
       
           W   B   ≧W   E +2 *D   
       
     
     Substituting for some real sample values of such distances, then: 
     
       
           W   B ≧0.8+2*0.4=1.6 μm 
       
     
     
       
           W   B ≧0.4+2*0.2=0.8 μm. 
       
     
     It will be readily appreciated from the above values that the process of this invention is highly beneficial in terms of reducing base channel width. 
     The results of actual tests carried out by the Applicant with the lateral PNP device  15  of the present invention have confirmed the advantages of this solution. 
     The adopted solution also allows the size of the lateral PNP device described hereinabove to be reduced, thereby further improving its frequency performance. 
     In conclusion, this lateral PNP device can be operated at high frequencies, with suitable collector current values and good amplification, to provide a superior figure of merit compared to that typical of conventional lateral PNP devices. 
     From the foregoing it will be appreciated that, although specific embodiments of the invention have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the invention. Accordingly, the invention is not limited except as by the appended claims.