Patent Publication Number: US-9899475-B2

Title: Epitaxial channel with a counter-halo implant to improve analog gain

Description:
REFERENCE TO RELATED APPLICATION 
     This Application is a Divisional of U.S. application Ser. No. 14/156,496 filed on Jan. 16, 2014, the contents of which is hereby incorporated by reference in its entirety. 
    
    
     BACKGROUND 
     Transistors are highly utilized in modern integrated circuits (ICs) for amplifying or switching electronic signals. A modern semiconductor IC contains millions or even billions of transistors on a single IC. To ensure proper yield the transistors are manufactured with accurate and precise placement of their various components and constituents. One such constituent is dopant impurities that are introduced into the channel region of a transistor. The dopant impurities directly influence the functionality and performance of the transistor. The characteristics and location of the dopant impurities, or the “dopant profile,” must be carefully controlled. Variations within a semiconductor manufacturing process can cause variation in the transistor device, performance degradation, and possible yield loss. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIGS. 1A-1B  illustrate cross-sectional views of some embodiments of performing a counter-halo implant in a long-channel transistor while simultaneously shadowing the counter-halo implant in a short-channel transistor. 
         FIG. 2  illustrates some embodiments of a method of performing a counter-halo implant on a plurality of long-channel transistors while simultaneously shadowing the counter-halo implant on a plurality of short-channel transistors. 
         FIGS. 3A-3J  illustrate cross-sectional views of some embodiments of forming a transistor with a counter-halo implant. 
         FIG. 4  illustrates a cross-sectional view of some embodiments a short-channel transistor and a long-channel transistor formed on a same substrate by the embodiments of  FIGS. 3A-3J . 
         FIGS. 5A-5B  illustrate graphs of some embodiments of dopant concentrations for a long-channel transistor that receives a counter-halo implant and a short-channel transistor that does not receive the counter-halo implant because of shadowing. 
         FIG. 6  illustrates some embodiments of a method of forming a long-channel transistor with a counter-halo implant while simultaneously preventing a short-channel transistor from receiving the counter-halo implant. 
     
    
    
     DETAILED DESCRIPTION 
     The description herein is made with reference to the drawings, wherein like reference numerals are generally utilized to refer to like elements throughout, and wherein the various structures are not necessarily drawn to scale. In the following description, for purposes of explanation, numerous specific details are set forth in order to facilitate understanding. It may be evident, however, to one of ordinary skill in the art, that one or more aspects described herein may be practiced with a lesser degree of these specific details. In other instances, known structures and devices are shown in block diagram form to facilitate understanding. 
     Short-channel length transistors formed semiconductor substrates are subject to drain-induced barrier lowering (DIBL) over comparatively long-channel transistors due to low channel doping or source/drain junctions which are too deep. DIBL results in leakage between the source and drain of a transistor, which can result in a loss gate control. To combat this effect, a localized halo implant is utilized to increase channel dopant concentrations near the source/drain regions of the channel. The higher doping in these regions reduces interaction between the source and drain without influencing the threshold voltage (V th ) of the device. However, while the halo implant can improve the performance and decrease leakage in short-channel transistors, it can degrade the source-to-drain transconductance (G ds ) of long-channel transistors. 
     Accordingly, some embodiments of the present disclosure relate to an implant that improves long-channel transistor performance with little to no impact on short-channel transistor performance. To mitigate DIBL, both long-channel and short-channel transistors on a substrate are subjected to a halo implant. While the halo implant improves short-channel transistor performance, it degrades long-channel transistor performance. Therefore, a counter-halo implant is performed on the long-channel transistors only to restore their performance. To achieve this, the counter-halo implant is performed at an angle that introduces dopant impurities near the source/drain regions of the long-channel transistors to counteract the effects of the halo implant, while the counter-halo implant is simultaneously shadowed from reaching the channel of the short-channel transistors. The embodiments disclosed herein can improve long-channel transistor DIBL, G ds , and gain with little to no impact on short channel transistor performance, and without additional mask cost. 
       FIG. 1A  illustrates a cross-sectional view of some embodiments of a pair of short-channel transistors  100 A formed on a substrate  102 , including first and second channel regions  112 A,  112 B of channel length L 1  residing between a plurality of source/drain regions  110 . The pair of short-channel transistors also include first and second gate structures  104 A,  104 B each composed of a hard mask (HM)  108  disposed on a gate electrode  106 . For the short-channel transistors  100 A, the first and second gate structures  104 A,  104 B have a vertical dimension (h) and are separated by a first horizontal space (s 1 ).  FIG. 1B  illustrates a cross-sectional view of some embodiments of a pair of long-channel transistors  100 B composed the same components and constituents as the pair of short-channel transistors  100 A, but having first and second channel regions  112 A,  112 B of channel length L 2 , where L 2 &gt;L 1 . Additionally, the pair of long-channel transistors  100 B are separated by a second horizontal space (s 2 ). 
     Both the short-channel transistors  100 A and long-channel transistors  100 B have been subjected to halo implantation to alleviate DIBL within the short-channel transistors  100 A. In order to counteract the effects of G ds  degradation within the long-channel transistors  100 B, a counter-halo implant is performed on the pair long-channel transistors  100 B only to restore their performance. To achieve this, an implant angle is chosen such that implanted dopant impurities reach the first and second channel regions  112 A,  112 B of the long-channel transistors  100 B, but are blocked from reaching the first and second channel regions  112 A,  112 B of the short-channel transistors  100 A. 
     For the short-channel transistors  100 A, a first angle (θ 1 ) greater than arctangent(s 1 /h) will not allow the counter-halo implant to reach the first and second channel regions  112 A,  112 B of the short-channel transistors  100 A due to shadowing of the implant by an adjacent gate structure. Conversely, for the long-channel transistors  100 B, a second angle (θ 2 ) of less than arctangent(s 2 /h) will allow the counter-halo implant to reach the first and second channel regions  112 A,  112 B of the long-channel transistors  100 B. Therefore, a counter-halo implant angle of θ 2 &gt;θ&gt;θ 1  will allow the counter-halo implant to reach only the first and second channel regions  112 A,  112 B of the long-channel transistors  100 B, while not impacting the short-channel transistors  100 A. This avoids additional the cost and manufacturing overhead required to produce a dedicated mask to perform the counter-halo implant on the long-channel transistors  100 B only. 
       FIG. 2  illustrates some embodiments of a method of  200  performing a counter-halo implant on a plurality of long-channel transistors while simultaneously shadowing the counter-halo implant on a plurality of short-channel transistors. While the method  200 , and subsequently the method  400 , are described as a series of acts or events, it will be appreciated that the illustrated ordering of such acts or events are not to be interpreted in a limiting sense. For example, some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein. In addition, not all illustrated acts may be required to implement one or more aspects or embodiments of the description herein. Further, one or more of the acts depicted herein may be carried out in one or more separate acts and/or phases. 
     At  202  a plurality of first gate structures are formed on a substrate. The first gate structures have a vertical dimension (h) and are separated by a first horizontal space (s 1 ). 
     At  204  a plurality of second gate structures are formed on the substrate. The second gate structures have the vertical dimension (h) and are separated by a second horizontal space (s 2 ), which is greater than the first horizontal space (s 1 ). 
     At  206  a counter-halo implant is performed at an angle with vertical to introduce dopant impurities into the substrate. The angle is greater than a first threshold of arctangent(s 1 /h) such that the implant is blocked from reaching the substrate by the first gate structures. Also, the angle is less than a second threshold of arctangent(s 2 /h) such that the implant is not blocked from reaching the substrate by the second gate structures. 
       FIGS. 3A-3J  illustrate cross-sectional views of some embodiments of forming a transistor with a counter-halo implant. 
       FIG. 3A  illustrates a cross-sectional view of some embodiments of a substrate  302 , where a well and V th  implant  304  is used to introduce dopant impurities of a first impurity type into a transistor region of the substrate  302 . The V th  implant introduces the impurities of the first impurity type into the transistor region of the substrate  302  to adjust the V th  of a transistor formed in subsequent processing steps. In some embodiments, the dopant impurities include p-type dopant impurities such as boron, carbon, indium, etc. In some embodiments, the dopant impurities include n-type dopant impurities such as phosphorous, antimony, or arsenic, etc. In various embodiments, the V th  implant uses an implant energy in a range of about 5 keV to about 150 keV. 
       FIG. 3B  illustrates a cross-sectional view of some embodiments of the substrate  302 , where an annealing operation is used to activate the implanted dopants, or to eliminate crystalline defects introduced during the well and V th  implant  304 , and promote diffusion and redistribution of dopant impurities. Various conventional annealing operations may be used and the annealing operations may drive the implanted dopant impurities deeper into semiconductor substrate  302  as indicated by darkness gradient of the substrate  302  in  FIG. 3B . 
       FIG. 3C  illustrates a cross-sectional view of some embodiments of the substrate  302 , which is recessed to a depth (d) in the transistor region. In some embodiments, formation of the recess includes one or more etching process(es), including but not limited to a dry process(es) such as a plasma etching process, wet etching process(es), or a combination of both. In some embodiments, a wet etch is used to form the recess. For example, an etchant such as carbon tetrafluoride (CF 4 ), HF, tetramethylammonium hydroxide (TMAH), or combinations of thereof, or the like may be used to perform the wet etch and form the recess. 
       FIG. 3D  illustrates a cross-sectional view of some embodiments of the substrate  302 , where a layer of carbon-containing material  306  is disposed over the transistor region. In some embodiments, the carbon-containing material  306  includes silicon carbide (SiC). 
       FIG. 3E  illustrates a cross-sectional view of some embodiments of the substrate  302 , where a layer of substrate material  308  is disposed over the layer of carbon-containing material  306 . In some embodiments, the layer of substrate material  308  includes silicon (Si). In various embodiments, the layer of carbon-containing material  306  and the layer of substrate material  308  are disposed by a suitable epitaxial method such as chemical vapor deposition (CVD), low pressure CVD (LPCVD), atomic layer CVD (ALCVD), ultrahigh vacuum CVD (UHVCVD), reduced pressure CVD (RPCVD), any suitable CVD; molecular beam epitaxy (MBE) processes, or any suitable combinations thereof. In some embodiments, the layer of carbon-containing material  306  has a thickness in a range of about 2 nanometers (nm) to about 15 nm. In some embodiments, the layer of substrate material  308  has a thickness in a range of about 5 nm to about 30 nm. 
       FIG. 3F  illustrates a cross-sectional view of some embodiments of the substrate  302 , where a gate dielectric  310  is disposed over the layer of substrate material  308 . In various embodiments, disposal of the gate dielectric  310  is achieved by the aforementioned epitaxial methods, or by various suitable dielectric deposition processes. In some embodiments, gate dielectric  310  includes a high-k dielectric layer such as hafnium oxide (HfO). Other embodiments may use other suitable high-k gate dielectric materials. Other embodiments may utilize an oxide layer such as silicon dioxide (SiO 2 ). In some embodiments, the gate dielectric  310  has a thickness in a range of about 1 nm to about 30 nm. 
       FIG. 3G  illustrates a cross-sectional view of some embodiments of the substrate  302 , where a gate structure ( 312 ,  314 ) is disposed over the gate dielectric  310  in the channel region of the substrate  302 . For the embodiments of  FIG. 3G , the gate structure includes a gate electrode  312  (e.g., polysilicon) disposed over the gate dielectric  310 , and a hard mask  314  formed over the gate electrode  312 . In various embodiments, the gate structure is formed by a suitable lithography method including, but to, optical lithography, multiple patterning (MP) optical lithography (e.g., double-patterning), deep ultraviolet (UV) lithography, extreme UV (EUV) lithography, or other suitable patterning technique. 
       FIG. 3H  illustrates a cross-sectional view of some embodiments of the substrate  302 , where lightly-doped-drain (LDD) implant (not shown) and a halo implant  316  is performed after patterning of the gate structure to form LDD regions  318 . The LDD implant utilizes dopants of a second impurity type (i.e., n-type or p-type), opposite the first impurity type of the well and V th  implants shown in  FIG. 3A . For the embodiments of  FIGS. 3A-3J , the LDD regions  318  utilize an n-type dopant (e.g., phosphorous, antimony, or arsenic, etc) and the well and V th  implants  304  utilize a p-type dopant (e.g., boron, carbon, indium, etc.). 
     In various embodiments, the halo implant  316  is performed at a first tilt angle (θ 1 ) of 20 degrees or less with respect to the vertical. The halo implant  316  introduces dopant impurities of the first impurity type (i.e., same as the well and V th  implants  304 ) into highly-doped regions  320  on opposite edges the channel region formed below the gate structure to mitigate DIBL effects. In one exemplary embodiment, the halo implant  316  is used to introduce a mixture of indium and carbon. In another exemplary embodiment, the halo implant  316  is used to introduce indium, boron, or BF 2  into the highly-doped regions  320 . 
       FIG. 3I  illustrates a cross-sectional view of some embodiments of the substrate  302 , where a counter-halo implant  322  is performed to deposit dopant impurities of the second impurity type (i.e., opposite the well and V th  implant  304 ). The counter-halo implant  322  compensates for the highly-doped regions  320  at opposite edges the channel region. For embodiments where the substrate  302  includes transistors with multiple channel lengths, the counter-halo implant  322  is performed at a second tilt angle (θ 2 ) with vertical. The second tilt angle (θ 2 ) is chosen such that comparatively long-channel transistors receive the implant, while comparatively short-channel transistors do not receive the implant due to shadowing of the channel region of the short-channel transistors by adjacent gate structures, as seen in the embodiments of  FIGS. 1A-1B . As a result of the counter-halo implant  322 , the long-channel transistors&#39; DIBL, G ds , and gain are improved while the short-channel transistors remain unaffected. 
     In some embodiments, the epitaxial channel formed by the layer of substrate material  308  and the layer of carbon-containing material  306  is subjected to an additional “heavy dose” V th  implant. The additional V th  implant enhances source-to-drain current control within the epitaxial channel of the short-channel devices. However, the additional V th  implant can also increase the V th  of the long-channel transistors by about 30 mV to about 100 mV. Accordingly, the shadowing method used to expose only the long-channel transistors to the counter-halo implant  322  can also be used to counter-act the effects of the heavy dose V th  implant. The epitaxial channels of the long-channel transistors can be isolated for a “long-channel V th -reduction” implant by the shadowing method. The long-channel V th -reduction implant is performed at the second tilt angle (θ 2 ) such that comparatively long-channel transistors again receive the implant, while comparatively short-channel transistors again do not receive the implant due to shadowing. The conditions (e.g., dose, energy, etc.) of the long-channel V th -reduction implant can be tuned to reduce the threshold voltage of the long-channel devices by the same amount that they were increased due to the heavy dose V th  implant (e.g., by about 30 mV to about 100 mV). As a result, the V th  of the long-channel transistors comprising epitaxial channels of the layer of substrate material  308  and the layer of carbon-containing material  306  can be made to be approximately equal to the V th  of a long-channel transistor with a channel formed directly within a substrate  302  (i.e., without the epitaxial channel). 
       FIG. 3J  illustrates a cross-sectional view of some embodiments of the substrate  302 , where spacers  324  are formed. In various embodiments, the spacers  324  include combinations of oxide, silicon, and nitride. Subsequent to spacer formation, the substrate  302  is then subjected to source/drain implant  326 , or embedded source/drain epitaxy (not shown), to form source/drains regions  328 . The source/drains regions  328  include the second dopant impurity type (i.e., the same as the LDD regions  318 ). 
       FIG. 4  illustrates a cross-sectional view of some embodiments a short-channel transistor  400 A and a long-channel transistor  400 B formed on a same substrate  302  by the embodiments of  FIGS. 3A-3J . The short-channel transistor  400 A does not receive the counter-halo implant  322 , while the long-channel transistor  400 B does. The short-channel transistor  400 A has a first channel region of channel length L 1 , and the long-channel transistor  400 B has a second channel region of channel length L 2 , where L 2 &gt;L 1 . For the embodiments of  FIG. 4 , the short-channel and long-channel transistors  400 A,  400 B include n-type metal-oxide field effect transistors (MOSFETs) formed on a silicon substrate  302 . The short-channel and long-channel transistors  400 A,  400 B further include first and second channel regions  402 A,  402 B, which have been doped with a p-type dopant impurities (e.g., boron, carbon, indium, etc.) at higher concentration levels than other parts of the first and second channel region  402 A,  402 B. The LDD and source/drain regions  318 ,  328  are formed with n-type dopant impurities (e.g., phosphorous, antimony, or arsenic). 
       FIGS. 5A-5B  illustrate graphs  500 A,  500 B of some embodiments of dopant concentrations for the short-channel transistor  400 A and the long-channel transistor  400 B along line AA′ of  FIG. 4 .  FIGS. 5A-5B  illustrate that the dopant concentration is higher at the edges of both the first and second channel regions  402 A,  402 B before and after the counter-halo implant  322 . However, it is observed that the dopant concentration at each end of the second channel region  402 B is reduced by an amount Δ after the counter-halo implant  322 . In the long-channel transistor  400 B the dopant concentration created by the halo implant  316  can be compensated by the counter-halo implant  322 , resulting in more flat channel profile along the channel direction AA′ for the long-channel transistor  400 B relative to the short-channel transistor  400 A. 
     Note that although the above exemplary embodiment has been described for an n-type MOSET, the disclosed embodiments may apply to a p-type MOSFET as well by reversing the dopant types from those described herein. 
       FIG. 6  illustrates some embodiments of a method  600  of forming a long-channel transistor with a counter-halo implant while simultaneously preventing a short-channel transistor from receiving the counter-halo implant. 
     At  602  dopant impurities of a first impurity type are introduced into first and second transistor regions of a substrate, where the first and second transistor region includes first and second channel regions and first and second source/drain regions, respectively. In some embodiments, an anneal is performed after introducing the dopant impurities of a first impurity type into the first and second transistor regions of the substrate. 
     At  604  the substrate is recessed over the first and second transistor regions. 
     At  606  first and second layers of carbon-containing material (e.g., silicon carbide) are formed over the first and second transistor regions. 
     At  608  first and second layers of substrate material (e.g., silicon) are formed over the first and second layers of carbon-containing material. 
     At  610  first and second gate dielectrics (e.g., HfO) are formed over the first and second layers of substrate material. 
     At  612  first and second gate structures are formed over the first and second gate dielectrics in the first and second channel regions. The first gate structure is separated by a first horizontal space (s 1 ) from a third gate structure. And, the second gate structure is separated by a second horizontal space (s 2 ) from a fourth gate structure, where s 2 &gt;s 1 . The first through fourth gate structures all have vertical dimension (h). 
     At  614  a first implant (i.e., a halo implant) is performed at a first angle to introduce further dopant impurities of the first impurity type into the substrate at edges of the first and second channel regions. 
     At  616  a second implant (i.e., a counter-halo implant) is performed at a second angle with vertical to introduce dopant impurities of the second type, which is opposite the first impurity type, into the first and second channel regions. The second angle is greater than a first threshold of arctangent(s 1 /h) such that the second implant is blocked from reaching the first channel regions by the third gate structure. The second angle is also less than a second threshold of arctangent(s 2 /h) such that the implant is not blocked from reaching the second channel regions by the fourth gate structure. 
     In some embodiments, a third implant (e.g., “heavy dose” V th  implant) is performed to introduce first additional dopant impurities into the first and second channel regions. The third implant enhances source-to-drain current control within the first channel region, but increases a threshold voltage within the second channel region by a delta value (e.g., in a range of about 30 mV to about 100 mV). In such embodiments, a fourth implant (e.g., a “long-channel V th -reduction” implant) may be performed at the second angle with vertical to introduce second additional dopant impurities into the second channel region. The second additional dopant impurities are again blocked from reaching the first channel region by the third gate structure. The fourth implant reduces the threshold voltage within the second channel region by about the delta value. As a result, the V th  of transistors with second channel regions comprising epitaxial channels can be made to be approximately equal to the V th  of transistors with second channel regions formed directly within a substrate  302 . 
     It will also be appreciated that equivalent alterations and/or modifications may occur to one of ordinary skill in the art based upon a reading and/or understanding of the specification and annexed drawings. The disclosure herein includes all such modifications and alterations and is generally not intended to be limited thereby. In addition, while a particular feature or aspect may have been disclosed with respect to only one of several implementations, such feature or aspect may be combined with one or more other features and/or aspects of other implementations as may be desired. Furthermore, to the extent that the terms “includes”, “having”, “has”, “with”, and/or variants thereof are used herein; such terms are intended to be inclusive in meaning—like “comprising.” Also, “exemplary” is merely meant to mean an example, rather than the best. It is also to be appreciated that features, layers and/or elements depicted herein are illustrated with particular dimensions and/or orientations relative to one another for purposes of simplicity and ease of understanding, and that the actual dimensions and/or orientations may differ substantially from that illustrated herein. 
     Therefore, some embodiments of the present disclosure relate to an implant that improves long-channel transistor performance with little to no impact on short-channel transistor performance. To mitigate DIBL, both long-channel and short-channel transistors on a substrate are subjected to a halo implant. While the halo implant improves short-channel transistor performance, it degrades long-channel transistor performance. Therefore, a counter-halo implant is performed on the long-channel transistors only to restore their performance. To achieve this, the counter-halo implant is performed at an angle that introduces dopant impurities near the source/drain regions of the long-channel transistors to counteract the effects of the halo implant, while the counter-halo implant is simultaneously shadowed from reaching the channel of the short-channel transistors. The embodiments disclosed herein can improve long-channel transistor DIBL, G ds , and gain with little to no impact on short channel transistor performance, and without additional mask cost. 
     In some embodiments, the present disclosure relates to an integrated chip. The integrated chip comprises a first gate electrode arranged over a first channel region having a first length, and a second gate electrode arranged over a second channel region having a second length greater than the first length. The first channel region and the second channel region have dopant profiles, respectively along the first length and the second length, which have a dopant concentration that is higher by edges than in a middle of the first channel region and the second channel region. The dopant concentration is higher by the edges of the first channel region than by the edges of the second channel region. 
     In other embodiments, the present disclosure relates to an integrated chip. The integrated chip comprises a first gate electrode arranged over a first channel region having a first length between first source/drain regions, and a second gate electrode arranged over a second channel region having a second length between second source/drain regions, wherein the second length is greater than the first length. A first plurality of highly doped regions protrude from sides of the first source/drain regions into the first channel region. A second plurality of highly doped regions protrude from sides of the second source/drain regions into the second channel region. A dopant concentration of the first plurality of highly doped regions is greater than a dopant concentration of the second plurality of highly doped regions. 
     In yet other embodiments, the present disclosure relates to integrated chip. The integrated chip comprises a first gate electrode arranged over a first channel region having a first length between first source/drain regions, and a second gate electrode arranged over a second channel region having a second length between second source/drain regions, wherein the second length is greater than the first length. A first plurality of highly doped regions protrude from sides of the first source/drain regions into the first channel region. A second plurality of highly doped regions protrude from sides of the second source/drain regions into the second channel region. The second plurality of highly doped regions comprise a first dopant species and a second dopant species having opposite doping types.