Patent Publication Number: US-2022216163-A1

Title: Method for manufacturing semiconductor mark, and semiconductor mark

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This is a continuation of International Patent Application No. PCT/CN2021/106577 filed on Jul. 15, 2021, which claims priority to Chinese patent application No. 202110016542.8 filed on Jan. 7, 2021. The disclosures of the above-referenced applications are hereby incorporated by reference in their entirety. 
    
    
     BACKGROUND 
     In a semiconductor manufacturing process, especially a Dynamic Random Access Memory (DRAM) manufacturing process, semiconductor marks need to be used to assist in the alignment of a semiconductor structure with a machine, etc. 
     SUMMARY 
     The disclosure relates to the technical field of semiconductors, and in particular to a method for manufacturing semiconductor mark and a semiconductor mark. 
     The disclosure provides a method for manufacturing semiconductor mark and a semiconductor mark, to improve the manufacturing efficiency of the semiconductor mark. 
     According to a first aspect of the disclosure, a method for manufacturing semiconductor mark is provided. The method includes the following operations. 
     A pattern having a peripheral edge corrected by Optical Proximity Correction (OPC) is provided. 
     Multiple independent alignment sections are cut from the pattern. 
     The multiple alignment sections are spliced to form a semiconductor mark having a peripheral edge corrected by OPC. 
     According to a second aspect of the disclosure, a semiconductor mark is provided, and the semiconductor mark is implemented according to the above method for manufacturing semiconductor mark. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Various objects, features, and advantages of the disclosure will become more apparent from the following detailed description of preferred implementations of the disclosure when considered in conjunction with the accompanying drawings. The drawings are merely exemplary illustrations of the disclosure and are not necessarily drawn to scale. In the drawings, like reference numerals refer to the same or similar components throughout. 
         FIG. 1  is a schematic flowchart of a method for manufacturing semiconductor mark according to an exemplary embodiment. 
         FIG. 2  is a schematic structural diagram of a method for manufacturing semiconductor mark according to a first exemplary embodiment. 
         FIG. 3  is a schematic structural diagram of a method for manufacturing semiconductor mark according to a second exemplary embodiment. 
         FIG. 4  is a schematic structural diagram of a method for manufacturing semiconductor mark according to a third exemplary embodiment. 
         FIG. 5  is a schematic structural diagram of a method for manufacturing semiconductor mark according to a fourth exemplary embodiment. 
         FIG. 6  is a schematic structural diagram of a method for manufacturing semiconductor mark according to a fifth exemplary embodiment. 
         FIG. 7  is a schematic structural diagram of a method for manufacturing semiconductor mark according to a sixth exemplary embodiment. 
         FIG. 8  is a schematic structural diagram of a method for manufacturing semiconductor mark according to a seventh exemplary embodiment. 
         FIG. 9  is a schematic structural diagram of a method for manufacturing semiconductor mark according to an eighth exemplary embodiment. 
         FIG. 10  is a schematic structural diagram of a method for manufacturing semiconductor mark according to a ninth exemplary embodiment. 
         FIG. 11  is a schematic structural diagram of a method for manufacturing semiconductor mark according to a tenth exemplary embodiment. 
         FIG. 12  is a schematic structural diagram of a method for manufacturing semiconductor mark according to an eleventh exemplary embodiment. 
         FIG. 13  is a simple schematic structural diagram showing the method for manufacturing semiconductor mark according to the eleventh exemplary embodiment. 
         FIG. 14  is a schematic structural diagram of a method for manufacturing semiconductor mark according to a twelfth exemplary embodiment. 
         FIG. 15  is a simple schematic structural diagram showing the method for manufacturing semiconductor mark according to the twelfth exemplary embodiment. 
     
    
    
     Reference numerals are illustrated as follows. 
       10 : pattern;  11 : original edge;  12 : cutting edge; 
       13 : first alignment section;  14 : second alignment section;  20 : first semiconductor mark; 
       21 : first section;  22 : second section;  23 : third section;  30 : second semiconductor mark; 
       24 : first section;  25 : second section;  1 : first fill region;  40 , third semiconductor mark; 
       131 : first alignment section;  141 : second alignment section;  2 : second fill region;  50 : fourth semiconductor mark; 
       16 : first alignment section;  17 : second alignment section;  18 : third alignment section;  19 : fourth alignment section;  60 : fifth semiconductor mark; 
       161 : first alignment section;  171 : second alignment section;  181 : third alignment section;  191 : fourth alignment section;  3 : third fill region;  70 : sixth semiconductor mark; 
       101 : first alignment section;  102 : second alignment section;  103 : third alignment section;  80 : seventh semiconductor mark. 
     DETAILED DESCRIPTION 
     Exemplary embodiments that embody the features and advantages of the disclosure will be described in detail in the following description. It will be appreciated that the disclosure may have various changes in different embodiments without departing from the scope of the disclosure, and that the description and drawings are illustrative in nature and are not intended to limit the disclosure. 
     In the following description of various exemplary embodiments of the disclosure, reference is made to the accompanying drawings, which form a part thereof, and in which various exemplary structures, systems, and steps capable of implementing various aspects of the disclosure are shown by way of illustration. It will be appreciated that other specific solutions of components, structures, exemplary devices, systems, and steps may be utilized and structural and functional modifications may be made without departing from the scope of the disclosure. Moreover, although the terms “on”, “between”, “in”, etc. may be used in this specification to describe different exemplary features and elements of the disclosure, these terms are used herein for convenience only, e.g., in accordance with the orientation of the examples in the figures. Nothing in this specification should be construed as requiring a particular three-dimensional orientation of the structure in order to fall within the scope of the disclosure. 
     In the related art, there is no uniform mode for manufacturing semiconductor marks, and the overall manufacturing efficiency is low. 
     An embodiment of the disclosure provides a method for manufacturing semiconductor mark. Referring to  FIG. 1 , the method for manufacturing semiconductor mark includes the following operations. 
     At  5101 , a pattern  10  having a peripheral edge corrected by Optical Proximity 
     Correction (OPC) is provided. 
     At S 103 , multiple independent alignment sections are cut from the pattern  10 . 
     At S 105 , the multiple alignment sections are spliced to form a semiconductor mark having a peripheral edge corrected by OPC. 
     In the method for manufacturing semiconductor mark according to an embodiment of the disclosure, a semiconductor mark having a peripheral edge corrected by OPC is obtained by cutting and splicing patterns  10  having a peripheral edge corrected by OPC. That is, the semiconductor mark having the peripheral edge corrected by OPC may be formed after multiple alignment sections are spliced, thereby saving time for OPC after the semiconductor mark is formed, and improving the manufacturing efficiency of the semiconductor mark. 
     It should be noted that an OPC technology is to compensate a distortion and offset of a pattern by changing the pattern systematically so that a final exposure pattern on a wafer substrate can meet design requirements of a circuit pattern. In the embodiment, the pattern  10  corrected by OPC is selected for cutting, and at least part of alignment sections obtained by cutting have been corrected by OPC. Therefore, it is possible to form a semiconductor mark having a peripheral edge corrected by OPC after the multiple alignment sections are spliced. 
     In an embodiment, the alignment section includes an original edge  11  corrected by OPC and a cutting edge  12  not corrected by OPC. The respective cutting edges  12  of the multiple alignment sections are spliced to form the semiconductor mark. 
     That is, alignment sections to be spliced are spliced according to the cutting edges  12 , and the original edges  11  corrected by OPC define the peripheral edge of the semiconductor mark. Therefore, the finally formed semiconductor mark is a semiconductor mark having the peripheral edge corrected by OPC. 
     In an embodiment, the multiple alignment sections include a first alignment section  13  and a second alignment section  14 . The first alignment section  13  includes a cutting edge  12 . The second alignment section  14  includes a cutting edge  12 . The first alignment section  13  and the second alignment section  14  are butted to form a first semiconductor mark  20 . The first alignment section  13  and the second alignment section  14  are obtained by cutting two opposite sides of the pattern  10 . That is, two corners corresponding to the obtained first alignment section  13  and second alignment section  14  are corrected by OPC. 
     In an embodiment, the first alignment section  13  and the second alignment section  14  may be formed by cutting two opposite corners of the pattern  10 . That is, the operation of cutting two opposite sides of the pattern  10  includes cutting upper and lower sides, left and right sides, or two opposite corners of the pattern  10 . 
     In some embodiments, as shown in  FIG. 2 , the method for manufacturing semiconductor mark includes the following operations. 
     As shown in (a) of  FIG. 2 , a pattern  10  having a peripheral edge corrected by OPC is provided. 
     As shown in (b) of  FIG. 2 , upper and lower sides of the pattern  10  are cut to obtain a first alignment section  13  and a second alignment section  14 . 
     As shown in (c) of  FIG. 2 , a cutting edge  12  of the first alignment section  13  and a cutting edge  12  of the second alignment section  14  are butted to form a first semiconductor mark  20 . 
     In some embodiments, as shown in  FIG. 5 , the method for manufacturing semiconductor mark includes the following operations. 
     As shown in (a) of  FIG. 5 , a pattern  10  having a peripheral edge corrected by OPC is provided. 
     As shown in (b) of  FIG. 5 , left and right sides of the pattern  10  are cut to obtain a first alignment section  13  and a second alignment section  14 . 
     As shown in (c) of  FIG. 5 , a cutting edge  12  of the first alignment section  13  and a cutting edge  12  of the second alignment section  14  are butted to form a first semiconductor mark  20 . 
     In some embodiments, after obtaining the first alignment section  13  and the second alignment section  14  shown in (b) of  FIG. 2  or  FIG. 5 , intermediate sections of the first alignment section  13  and the second alignment section  14  may be cut off and spliced, i.e., the first alignment section  13  and the second alignment section  14  are cut, so that a semiconductor mark obtained after splicing is shorter than the first semiconductor mark  20 . 
     In an embodiment, after forming the first semiconductor mark  20 , the method for manufacturing semiconductor mark further includes the following operations. The first semiconductor mark  20  is sequentially cut into a first section  21 , a second section  22 , and a third section  23 . The first section  21  and the third section  23  are butted to form a second semiconductor mark  30 . That is, an intermediate portion of the first semiconductor mark  20  is removed to obtain a second semiconductor mark  30  shorter than the first semiconductor mark  20 . 
     In some embodiments, as shown in  FIG. 3 , the method for manufacturing semiconductor mark includes the following operations. 
     As shown in (a) of  FIG. 3 , a first semiconductor mark  20  having a peripheral edge corrected by OPC is formed. 
     As shown in (b) of  FIG. 3 , the first semiconductor mark  20  is cut into three sections to obtain a first section  21 , a second section  22 , and a third section  23 . 
     As shown in (c) of  FIG. 3 , a cutting edge  12  of the first section  21  and a cutting edge  12  of the third section  23  are butted to form a second semiconductor mark  30 , i.e. the second section  22  is removed. 
     In some embodiments, as shown in  FIG. 6 , the method for manufacturing semiconductor mark includes the following operations. 
     As shown in (a) of  FIG. 6 , a first semiconductor mark  20  having a peripheral edge corrected by OPC is formed. 
     As shown in (b) of  FIG. 6 , the first semiconductor mark  20  is cut into three sections to obtain a first section  21 , a second section  22 , and a third section  23 . 
     As shown in (c) of  FIG. 6 , a cutting edge  12  of the first section  21  and a cutting edge  12  of the third section  23  are butted to form a second semiconductor mark  30 , i.e. the second section  22  is removed. 
     It should be noted that the first semiconductor mark  20  in  FIG. 3  is obtained by the method for manufacturing semiconductor mark shown in  FIG. 2 , while the first semiconductor mark  20  in  FIG. 6  is obtained by the method for manufacturing semiconductor mark shown in  FIG. 5 . 
     In an embodiment, after forming the first semiconductor mark  20 , the method for manufacturing semiconductor mark further includes the following operations. The first semiconductor mark  20  is cut into a first section  24  and a second section  25 . The first section  24  and the second section  25  are spaced apart and opposite to each other to form a first fill region  1 . A first compensation pattern section is filled in the first fill region  1  to form a third semiconductor mark  40 . The first compensation pattern section is corrected by OPC before filling or the first compensation pattern section is corrected by OPC after filling. That is, a lengthening process is performed by cutting the first semiconductor mark  20  from the middle, thereby obtaining a third semiconductor mark  40  longer than the first semiconductor mark  20 . 
     It should be noted that the first compensation pattern section is supplemented between the first section  24  and the second section  25 . Therefore, only a straight side instead of corners is corrected when OPC is performed thereon, the entire correction is less difficult, and the correction efficiency is relatively high. 
     In some embodiments, as shown in  FIG. 4 , the method for manufacturing semiconductor mark includes the following operations. 
     As shown in (a) of  FIG. 4 , a first semiconductor mark  20  having a peripheral edge corrected by OPC is formed. 
     As shown in (b) of  FIG. 4 , the first semiconductor mark  20  is cut into two sections to obtain a first section  24  and a second section  25 , and a first fill region  1  is formed between a cutting edge  12  of the first section  24  and a cutting edge  12  of the second section  25  after they are pulled apart. 
     As shown in (c) of  FIG. 4 , a first compensation pattern section is filled into the first fill region  1  to obtain a third semiconductor mark  40 . 
     In some embodiments, as shown in  FIG. 7 , the method for manufacturing semiconductor mark includes the following operations. 
     As shown in (a) of  FIG. 7 , a first semiconductor mark  20  having a peripheral edge corrected by OPC is formed. 
     As shown in (b) of  FIG. 7 , the first semiconductor mark  20  is cut into two sections to obtain a first section  24  and a second section  25 , and a first fill region  1  is formed between a cutting edge  12  of the first section  24  and a cutting edge  12  of the second section  25  after they are pulled apart. 
     As shown in (c) of  FIG. 7 , a first compensation pattern section is filled into the first fill region  1  to obtain a third semiconductor mark  40 . 
     It should be noted that the first semiconductor mark  20  in  FIG. 4  is obtained by the method for manufacturing semiconductor mark shown in  FIG. 2 , while the first semiconductor mark  20  in  FIG. 7  is obtained by the method for manufacturing semiconductor mark shown in  FIG. 5 . 
     In an embodiment, the multiple independent alignment sections include a first alignment section  131  and a second alignment section  141 . The first alignment section  131  includes a cutting edge  12 . The second alignment section  141  includes a cutting edge  12 . The first alignment section  131  and the second alignment section  141  are spaced apart and opposite to each other to form a second fill region  2 . A second compensation pattern section is filled into the second fill region  2  to form a fourth semiconductor mark  50 . The pattern  10  is cut from the middle to obtain the first alignment section  131  and the second alignment section  141 . The second compensation pattern section is corrected by OPC before filling, or the second compensation pattern section is corrected by OPC after filling. That is, the lengthening process is performed by cutting the pattern  10  from the middle, thereby obtaining a fourth semiconductor mark  50  longer than the pattern  10 . 
     In some embodiments, as shown in  FIG. 8 , the method for manufacturing semiconductor mark includes the following operations. 
     As shown in (a) of  FIG. 8 , a pattern  10  having a peripheral edge corrected by 
     OPC is provided. 
     As shown in (b) of  FIG. 8 , the pattern  10  is cut into two sections to obtain a first alignment section  131  and a second alignment section  141 , and a second fill region  2  is formed between a cutting edge  12  of the first alignment section  131  and a cutting edge  12  of the second alignment section  141  after they are pulled apart. 
     As shown in (c) of  FIG. 8 , a second compensation pattern section is filled into the second fill region  2  to obtain a fourth semiconductor mark  50 . 
     In some embodiments, on the basis of  FIG. 8 , the pattern  10  may be cut into left and right sections and then a semiconductor mark may be obtained according to the above manufacturing method. 
     In an embodiment, the multiple independent alignment sections include a first alignment section  16 , a second alignment section  17 , a third alignment section  18 , and a fourth alignment section  19 . The first alignment section  16  includes two cutting edges  12 . The second alignment section  17  includes two cutting edges  12 . The third alignment section  18  includes two cutting edges  12 . The fourth alignment section  19  includes two cutting edges  12 . The first alignment section  16 , the second alignment section  17 , the third alignment section  18 , and the fourth alignment section  19  are butted to form a fifth semiconductor mark  60 . An area of the fifth semiconductor mark  60  is smaller than that of the pattern  10 . 
     In an embodiment, the first alignment section  16 , the second alignment section  17 , the third alignment section  18 , and the fourth alignment section  19  are obtained by cutting four corners of the pattern  10 . That is, a middle portion of the pattern  10  is removed to obtain a relatively small fifth semiconductor mark  60  by splicing four diagonal sections of the pattern  10 . 
     In some embodiments, as shown in  FIG. 9 , the method for manufacturing semiconductor mark includes the following operations. 
     As shown in (a) of  FIG. 9 , a pattern  10  having a peripheral edge corrected by 
     OPC is provided. 
     As shown in (b) of  FIG. 9 , four corner sections of the pattern  10  are cut to obtain a first alignment section  16 , a second alignment section  17 , a third alignment section  18 , and a fourth alignment section  19 . 
     As shown in (c) of  FIG. 9 , a cutting edge  12  of the first alignment section  16  and a cutting edge  12  of the second alignment section  17  are butted, another cutting edge  12  of the first alignment section  16  and a cutting edge  12  of the third alignment section  18  are butted, another cutting edge  12  of the second alignment section  17  and a cutting edge  12  of the fourth alignment section  19  are butted, and another cutting edge  12  of the third alignment section  18  and another cutting edge  12  of the fourth alignment section  19  are butted, to form a fifth semiconductor mark  60 . 
     In an example, the pattern  10  is cut into four portions in two perpendicular directions, which are then secondarily cut to obtain the first alignment section  16 , the second alignment section  17 , the third alignment section  18 , and the fourth alignment section  19 , respectively. That is, the pattern  10  is first cut into four portions, and then the cut four portions are cut down to obtain the relatively small first alignment section  16 , second alignment section  17 , third alignment section  18 , and fourth alignment section  19 . 
     In some embodiments, as shown in  FIG. 10 , the method for manufacturing semiconductor mark includes the following operations. 
     As shown in (a) of  FIG. 10 , a pattern  10  having a peripheral edge corrected by OPC is provided. 
     As shown in (b) of  FIG. 10 , the pattern  10  is cut into four portions to obtain a first alignment section  161 , a second alignment section  171 , a third alignment section  181 , and a fourth alignment section  191 . 
     As shown in (c) of  FIG. 10 , the first alignment section  161 , the second alignment section  171 , the third alignment section  181 , and the fourth alignment section  191  are cut respectively to obtain a first alignment section  16 , a second alignment section  17 , a third alignment section  18 , and a fourth alignment section  19 . 
     As shown in (d) of  FIG. 10 , a cutting edge  12  of the first alignment section  16  and a cutting edge  12  of the second alignment section  17  are butted, another cutting edge  12  of the first alignment section  16  and a cutting edge  12  of the third alignment section  18  are butted, another cutting edge  12  of the second alignment section  17  and a cutting edge  12  of the fourth alignment section  19  are butted, and another cutting edge  12  of the third alignment section  18  and another cutting edge  12  of the fourth alignment section  19  are butted, to form a fifth semiconductor mark  60 . 
     In an embodiment, the multiple independent alignment sections include a first alignment section  161 , a second alignment section  171 , a third alignment section  181 , and a fourth alignment section  191 . The first alignment section  161  includes two cutting edges  12 . The second alignment section  171  includes two cutting edges  12 . The third alignment section  181  includes two cutting edges  12 . The fourth alignment section  191  includes two cutting edges  12 . The first alignment section  161 , the second alignment section  171 , the third alignment section  181 , and the fourth alignment section  191  are spaced apart and opposite to each other to form a third fill region  3 . A third compensation pattern section is filled into the third fill region  3  to form a sixth semiconductor mark  70 . The pattern  10  is cut in two perpendicular directions to obtain the first alignment section  161 , the second alignment section  171 , the third alignment section  181 , and the fourth alignment section  191 . The third compensation pattern section is corrected by OPC before filling, or the third compensation pattern section is corrected by OPC after filling. That is, a sixth semiconductor mark  70  having a larger area is obtained by cutting the pattern  10  into four portions and filling the third compensation pattern therebetween. 
     In some embodiments, as shown in  FIG. 11 , the method for manufacturing semiconductor mark includes the following operations. 
     As shown in (a) of  FIG. 11 , a pattern  10  having a peripheral edge corrected by OPC is provided. 
     As shown in (b) of  FIG. 11 , the pattern  10  is cut into four portions to obtain a first alignment section  161 , a second alignment section  171 , a third alignment section  181 , and a fourth alignment section  191 . A cutting edge  12  of the first alignment section  161  and a cutting edge  12  of the second alignment section  171  are spaced apart and opposite to each other. Another cutting edge  12  of the first alignment section  161  and a cutting edge  12  of the third alignment section  181  are spaced apart and opposite to each other. Another cutting edge  12  of the second alignment section  171  and a cutting edge  12  of the fourth alignment section  191  are spaced apart and opposite to each other. Another cutting edge  12  of the third alignment section  181  and another cutting edge  12  of the fourth alignment section  191  are spaced apart and opposite to each other. That is, a third fill region  3  is formed among the first alignment section  161 , the second alignment section  171 , the third alignment section  181 , and the fourth alignment section  191 . 
     As shown in (c) of  FIG. 11 , a third compensation pattern section is filled into the third fill region  3  to obtain a sixth semiconductor mark  70 . 
     It should be noted that the semiconductor marks obtained in  FIGS. 2-11  may be Overlay (OVL) marks. 
     In an embodiment, the multiple independent alignment sections include a first alignment section  101 , a second alignment section  102 , and a third alignment section  103 . The first alignment section  101  includes two cutting edges  12 , and the first alignment section  101  is L-shaped. The second alignment section  102  includes two cutting edges  12 , and the second alignment section  102  is straight. The third alignment section  103  includes two cutting edges  12 , and the third alignment section  103  is straight. The second alignment section  102  and the first alignment section  101  are butted while the third alignment section  103  and the first alignment section  101  are butted to form a seventh semiconductor mark  80 . That is, the first alignment section  101  forms an alignment standard by cutting out an L-shaped first alignment section  101  when butting the second alignment section  102  and the third alignment section  103 , so that the butting efficiency can be improved. 
     In an embodiment, a length of the second alignment section  102  is equal to that of one cutting edge  12  of the first alignment section  101 . A length of the third alignment section  103  is equal to that of the other cutting edge  12  of the first alignment section  101 . That is, portions of the second alignment section  102  and the third alignment section  103  overlay after forming the seventh semiconductor mark  80 . 
     In some embodiments, as shown in  FIG. 12 , the method for manufacturing semiconductor mark includes the following operations. 
     As shown in (a) of  FIG. 12 , one or more patterns  10  having peripheral edges corrected by OPC are provided. 
     As shown in (b) of  FIG. 12 , a first alignment section  101 , a second alignment section  102 , and a third alignment section  103  are cut from the periphery of the one or more patterns  10 . 
     As shown in (c) of  FIG. 12 , a cutting edge  12  of the first alignment section  101  and a cutting edge  12  of the second alignment section  102  are butted, and another cutting edge  12  of the first alignment section  101  and a cutting edge  12  of the third alignment section  103  are butted, to form a seventh semiconductor mark  80 . The second alignment section  102  and the third alignment section  103  overlay at a corner of the first alignment section  101 . 
     As can be seen in conjunction with  FIG. 13 , as shown in (a) of  FIG. 13 , two side portions of the pattern  10  are cut out to form an L-shaped first alignment section  101 . As shown in (b) of  FIG. 13 , a third side portion of the pattern  10  is cut out to form a straight second alignment section  102 . As shown in (c) of  FIG. 13 , a fourth side portion of the pattern  10  is cut out to form a straight third alignment section  103 . The length of the second alignment section  102  is equal to that of one cutting edge  12  of the first alignment section  101 . The length of the third alignment section  103  is equal to that of the other cutting edge  12  of the first alignment section  101 . 
     It should be noted that in the embodiment shown in  FIG. 13 , the first alignment section  101 , the second alignment section  102 , and the third alignment section  103  are obtained by cutting at least two patterns  10 . In some embodiments, the first alignment section  101 , the second alignment section  102 , and the third alignment section  103  may be secondarily cut after they have been cut, i.e., the middle section may be removed, or may be cut from the middle and lengthened, which are not limited herein. It may be adjusted according to actual requirements. 
     In an embodiment, the length of the second alignment section  102  is equal to that of one cutting edge  12  of the first alignment section  101 . The length of the third alignment section  103  is equal to the length of the other cutting edge  12  of the first alignment section  101  minus the width of the second alignment section  102 . That is, after forming the seventh semiconductor mark  80 , portions of the second alignment section  102  and the third alignment section  103  are just butted. 
     In some embodiments, as shown in  FIG. 14 , the method for manufacturing semiconductor mark includes the following operations. 
     As shown in (a) of  FIG. 14 , one or more patterns  10  having peripheral edges corrected by OPC are provided. 
     As shown in (b) of  FIG. 14 , a first alignment section  101 , a second alignment section  102 , and a third alignment section  103  are cut from the periphery of the one or more patterns  10 . 
     As shown in (c) of  FIG. 14 , a cutting edge  12  of the first alignment section  101  and a cutting edge  12  of the second alignment section  102  are butted, and another cutting edge  12  of the first alignment section  101  and a cutting edge  12  of the third alignment section  103  are butted, to form a seventh semiconductor mark  80 . The second alignment section  102  and the third alignment section  103  are just butted without overlay at the corner of the first alignment section  101 . 
     As can be seen in conjunction with  FIG. 15 , as shown in (a) of  FIG. 15 , two side portions of the pattern  10  are cut out to form an L-shaped first alignment section  101 . As shown in (b) of  FIG. 15 , a third side portion of the pattern  10  is cut out to form a straight second alignment section  102 . As shown in (c) of  FIG. 15 , a fourth side portion of the pattern  10  is cut out to form a straight third alignment section  103 . The length of the second alignment section  102  is equal to that of one cutting edge  12  of the first alignment section  101 . The length of the third alignment section  103  is equal to the length of the other cutting edge  12  of the first alignment section  101  minus the width of the second alignment section  102 . 
     It should be noted that in the embodiment shown in  FIG. 15 , the first alignment section  101 , the second alignment section  102 , and the third alignment section  103  are obtained by cutting at least two patterns  10 . In some embodiments, the first alignment section  101 , the second alignment section  102 , and the third alignment section  103  may be secondarily cut after they have been cut, i.e., the middle section may be removed, or may be cut from the middle and lengthened, which are not limited herein. It may be adjusted according to actual requirements. 
     In an embodiment, the first alignment section  101  and the second alignment section  102  are cut from the same pattern  10 , and the third alignment section  103  is cut from another pattern  10 , i.e., the first alignment section  101 , the second alignment section  102 , and the third alignment section  103  having two cutting edges  12 , respectively, are obtained by directly cutting the pattern  10 . 
     In an embodiment, the first alignment section  101 , the second alignment section  102 , and the third alignment section  103  are all cut from the same pattern  10 . After the first alignment section  101  and the second alignment section  102  are obtained by cutting, the remaining parts of the pattern  10  is corrected by OPC to cut the third alignment section  103 . When the first alignment section  101 , the second alignment section  102 , and the third alignment section  103  are obtained by cutting one pattern  10 , the first alignment section  101  and the second alignment section  102  may be obtained by cutting first. When cutting continues, the cut pattern  10  needs to be corrected by OPC to ensure that one corner is corrected by OPC, so that the third alignment section  103  obtained by cutting also includes only two cutting edges  12 . 
     In an embodiment, the first alignment section  101 , the second alignment section  102 , and the third alignment section  103  are all cut from the same pattern  10 . The remaining parts of the pattern  10  are cut to obtain a cut section after the first alignment section  101  and the second alignment section  102  are obtained by cutting. The cut section is corrected by OPC to obtain the third alignment section  103 . When the first alignment section  101 , the second alignment section  102 , and the third alignment section  103  are obtained by cutting one pattern  10 , the first alignment section  101  and the second alignment section  102  may be obtained by cutting first, and then the cutting continues to obtain a cut section having three cutting edges  12 , and the corner thereof is corrected by OPC, thereby obtaining the third alignment section  103  including only two cutting edges  12 . 
     It should be noted that for embodiments where the first alignment section  101 , the second alignment section  102 , and the third alignment section  103  are cut from one pattern  10 , although in some cases a compensation pattern section may be added, the length of a specific semiconductor mark needs to be taken into account. 
     It should be noted that the semiconductor marks obtained in  FIGS. 12-15  may be dicing marks. 
     According to the method for manufacturing semiconductor mark in the disclosure, a semiconductor mark having a peripheral edge corrected by OPC is obtained by cutting a pattern having a peripheral edge corrected by OPC and splicing the cut sections. That is, the semiconductor mark having the peripheral edge corrected by OPC may be formed after multiple alignment sections are spliced, thereby saving time for OPC after the semiconductor mark is formed, and improving the manufacturing efficiency of the semiconductor mark. 
     An embodiment of the disclosure further provides a semiconductor mark obtained according to the above method for manufacturing semiconductor mark. 
     The semiconductor mark in the present embodiment may be obtained according to the above method for manufacturing semiconductor mark according to size requirements. 
     After considering the specification and implementing the disclosure disclosed here, other implementations of the disclosure would readily be conceivable to a person skilled in the art. The disclosure is intended to cover any variations, uses, or adaptations of the disclosure following the general principles thereof and including such departures from the disclosure as come within known or customary practice in the art. It is intended that the specification and example implementations be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the foregoing claims. 
     It should be understood that the disclosure is not limited to the exact construction that has been described above and illustrated in the accompanying drawings, and that various modifications and changes may be made without departing from the scope thereof. It is intended that the scope of the disclosure only be limited by the appended claims.