Patent Publication Number: US-11387157-B2

Title: RF devices with enhanced performance and methods of forming the same

Description:
RELATED APPLICATIONS 
     This application claims the benefit of provisional patent application Ser. No. 62/866,869, filed Jun. 26, 2019, and provisional patent application Ser. No. 62/795,804, filed Jan. 23, 2019, the disclosures of which are hereby incorporated herein by reference in their entireties. 
    
    
     The present application is related to concurrently filed U.S. patent application Ser. No. 16/678,551, filed on Nov. 8, 2019, now U.S. Patent Application Publication No. 2020-0235066 A1, entitled “RF DEVICES WITH ENHANCED PERFORMANCE AND METHODS OF FORMING THE SAME,” U.S. patent application Ser. No. 16/678,586, filed on Nov. 8, 2019, now U.S. Patent Application Publication No. 2020-0234978 A1, entitled “RF DEVICES WITH ENHANCED PERFORMANCE AND METHODS OF FORMING THE SAME,” U.S. patent application Ser. No. 16/678,602, filed on Nov. 8, 2019, now U.S. Patent Application Publication No. 2020-0235040 A1, entitled “RF DEVICES WITH ENHANCED PERFORMANCE AND METHODS OF FORMING THE SAME,” and U.S. patent application Ser. No. 16/678,619, filed on Nov. 8, 2019, now U.S. Patent Application Publication No. 2020-0235074 A1, entitled “RF DEVICES WITH ENHANCED PERFORMANCE AND METHODS OF FORMING THE SAME,” the disclosures of which are hereby incorporated herein by reference in their entireties. 
     FIELD OF THE DISCLOSURE 
     The present disclosure relates to a radio frequency (RF) device and a process for making the same, and more particularly to an RF device with enhanced thermal and electrical performance, and a wafer-level fabricating and packaging process to provide the RF device with enhanced performance. 
     BACKGROUND 
     The wide utilization of cellular and wireless devices drives the rapid development of radio frequency (RF) technologies. The substrates on which RF devices are fabricated play an important role in achieving high level performance in the RF technologies. Fabrications of the RF devices on conventional silicon substrates may benefit from low cost of silicon materials, a large scale capacity of wafer production, well-established semiconductor design tools, and well-established semiconductor manufacturing techniques. Despite the benefits of using conventional silicon substrates for the RF device fabrications, it is well known in the industry that the conventional silicon substrates may have two undesirable properties for the RF devices: harmonic distortion and low resistivity values. The harmonic distortion is a critical impediment to achieve high level linearity in the RF devices built over silicon substrates. 
     In addition, high speed and high performance transistors are more densely integrated in RF devices. Consequently, the amount of heat generated by the RF devices will increase significantly due to the large number of transistors integrated in the RF devices, the large amount of power passing through the transistors, and/or the high operation speed of the transistors. Accordingly, it is desirable to package the RF devices in a configuration for better heat dissipation. 
     Wafer-level fan-out (WLFO) technology and embedded wafer-level ball grid array (eWLB) technology currently attract substantial attention in portable RF applications. WLFO and eWLB technologies are designed to provide high density input/output (I/O) ports without increasing the size of a package. This capability allows for densely packaging the RF devices within a single wafer. 
     To enhance the operation speed and performance of the RF devices, to accommodate the increased heat generation of the RF devices, to reduce deleterious harmonic distortion of the RF devices, and to utilize advantages of WLFO/eWLB technologies, it is therefore an object of the present disclosure to provide an improved wafer-level fabricating and packaging process for the RF devices with enhanced performance. Further, there is also a need to enhance the performance of the RF devices without increasing the device size. 
     SUMMARY 
     The present disclosure relates to a radio frequency (RF) device with enhanced performance, and a process for making the same. The disclosed RF device includes a mold device die and a multilayer redistribution structure. The mold device die includes a device region with a front-end-of-line (FEOL) portion and a back-end-of-line (BEOL) portion, a barrier layer, and a first mold compound. Herein, the FEOL portion resides over the BEOL portion and includes isolation sections and an active layer, which is surrounded by the isolation sections and does not extend vertically beyond the isolation sections. The barrier layer, which is formed of silicon nitride, continuously resides over a top surface of the active layer and top surfaces of the isolation sections of the FEOL portion. The first mold compound resides over the barrier layer. Silicon crystal, which has no germanium, nitrogen, or oxygen content, does not exist between the first mold compound and the active layer. The multilayer redistribution structure, which includes a number of bump structures, is formed underneath the BEOL portion of the mold device die. The bump structures are on a bottom surface of the multilayer redistribution structure and electrically coupled to the FEOL portion of the mold device die. 
     In one embodiment of the RF device, the active layer is formed from a strained silicon epitaxial layer, in which a lattice constant of silicon is greater than 5.461 at a temperature of 300K. 
     In one embodiment of the RF device, the barrier layer has a thickness between 100 Å and 10 μm. 
     In one embodiment of the RF device, the BEOL portion includes connecting layers, the FEOL portion further includes a contact layer, and the multilayer redistribution structure further includes redistribution interconnections. Herein, the active layer and the isolation sections reside over the contact layer, and the BEOL portion resides underneath the contact layer. The bump structures are electrically coupled to the FEOL portion of the mold device die via the redistribution interconnections within the multilayer redistribution structure and the connecting layers within the BEOL portion. 
     In one embodiment of the RF device, the isolation sections extend vertically beyond the top surface of the active layer to define an opening within the isolation sections and over the active layer. Herein, the barrier layer covers exposed surfaces within the opening. 
     In one embodiment of the RF device, the mold device die further includes a passivation layer over the top surface of the active layer and within the opening. Herein, the passivation layer is formed of silicon dioxide, and the barrier layer resides over the passivation layer. 
     In one embodiment of the RF device, the barrier layer directly resides over the top surface of the active layer. 
     In one embodiment of the RF device, a top surface of each isolation section and the top surface of the active layer are coplanar. Herein, the first mold compound resides over both the active layer and the isolation sections. 
     In one embodiment of the RF device, the first mold compound has a thermal conductivity greater than 1 W/m·K. 
     In one embodiment of the RF device, the first mold compound has a dielectric constant less than 8. 
     In one embodiment of the RF device, the first mold compound has a dielectric constant between 3 and 5. 
     In one embodiment of the RF device, the FEOL portion is configured to provide at least one of a switch field-effect transistor (FET), a diode, a capacitor, a resistor, or an inductor. 
     According to another embodiment, an alternative RF device includes a mold device die and a multilayer redistribution structure. The mold device die includes a device region with a FEOL portion and a BEOL portion, a barrier layer, and a first mold compound. Herein, the FEOL portion resides over the BEOL portion and includes isolation sections and an active layer, which is surrounded by the isolation sections and does not extend vertically beyond the isolation sections. The barrier layer, which is formed of silicon nitride, continuously resides over a top surface of the active layer and top surfaces of the isolation sections of the FEOL portion. The first mold compound resides over the barrier layer. Silicon crystal, which has no germanium, nitrogen, or oxygen content, does not exist between the first mold compound and the active layer. The multilayer redistribution structure, which is formed underneath the BEOL portion of the mold device die, extends horizontally beyond the mold device die. The multilayer redistribution structure includes a number of bump structures which are on a bottom surface of the multilayer redistribution structure, and electrically coupled to the FEOL portion of the mold device die. The alternative RF device further includes a second mold compound residing over the multilayer redistribution structure to encapsulate the mold device die. 
     In one embodiment of the alternative RF device, the active layer is formed from a strained silicon epitaxial layer, in which a lattice constant of silicon is greater than 5.461 at a temperature of 300K. 
     In one embodiment of the alternative RF device, the barrier layer has a thickness between 100 Å and 10 μm. 
     In one embodiment of the alternative RF device, the first mold compound is formed from a same material as the second mold compound. 
     In one embodiment of the alternative RF device, the first mold compound and the second mold compound are formed from different materials. 
     In one embodiment of the alternative RF device, the isolation sections extend vertically beyond the top surface of the active layer to define an opening within the isolation sections and over the active layer. Herein, the barrier layer covers exposed surfaces within the opening. 
     In one embodiment of the alternative RF device, the mold device die further includes a passivation layer over the top surface of the active layer and within the opening. Herein, the passivation layer is formed of silicon dioxide, and the barrier layer resides over the passivation layer. 
     In one embodiment of the alternative RF device, the barrier layer directly resides over the top surface of the active layer. 
     According to an exemplary process, a precursor wafer, which includes a number of device regions, a number of individual interfacial layers, and a silicon handle substrate, is firstly provided. Each device region includes a BEOL portion and a FEOL portion over the BEOL portion. The FEOL portion has isolation sections and an active layer, which is surrounded by the isolation sections and does not extend vertically beyond the isolation sections. Herein, each individual interfacial layer is over the active layer of a corresponding device region, and the silicon handle substrate is over each individual interfacial layer. Each individual interfacial layer is formed of SiGe. Next, the silicon handle substrate is removed completely to provide an etched wafer. A barrier layer, which is formed of silicon nitride, is then continuously applied over an entire backside of the etched wafer. Herein, the barrier layer covers a top surface of each active layer and a top surface of each isolation section. A first mold compound is applied over the barrier layer to provide a mold device wafer that includes a number of mold device dies. Herein, silicon crystal, which has no germanium, nitrogen, or oxygen content, does not exist between the active layer of each device region and the first mold compound. Each mold device die includes a corresponding device region, a portion of the barrier layer over the corresponding device region, and a portion of the first mold compound over the portion of the barrier layer. 
     In one embodiment of the exemplary process, the barrier layer has a thickness between 100 Å and 10 μm. 
     According to another embodiment, the exemplary process further includes bonding the precursor wafer to a temporary carrier via a bonding layer before the silicon handle substrate is removed, and debonding the temporary carrier and cleaning the bonding layer from the mold device wafer after the first mold compound is applied. 
     According to another embodiment, the exemplary process further includes forming a multilayer redistribution structure underneath the mold device wafer. Herein, the multilayer redistribution structure includes a number of bump structures on a bottom surface of the multilayer redistribution structure and redistribution interconnections within the multilayer redistribution structure. Each bump structure is electrically coupled to one active layer of a corresponding mold device die via the redistribution interconnections within the multilayer redistribution structure and connecting layers within the BEOL portion of the corresponding mold device die. 
     According to another embodiment, the exemplary process further includes singulating the mold device wafer into a number of individual mold device dies. A second mold compound is then applied around and over each individual mold device die to provide a double mold device wafer. Herein, the second mold compound encapsulates a top surface and side surfaces of each individual mold device die, while a bottom surface of each individual mold device die is exposed. A bottom surface of the double mold device wafer is a combination of the bottom surface of each individual mold device die and a bottom surface of the second mold compound. Next, a multilayer redistribution structure is formed underneath the double mold device wafer. The multilayer redistribution structure includes a number of bump structures on a bottom surface of the multilayer redistribution structure and redistribution interconnections within the multilayer redistribution structure. Each bump structure is electrically coupled to one active layer of a corresponding individual mold device die via the redistribution interconnections within the multilayer redistribution structure and connecting layers within the BEOL portion of the corresponding individual mold device die. 
     In one embodiment of the exemplary process, each individual interfacial layer has a uniform concentration of germanium greater than 15%, and each active layer is formed from an individual silicon epitaxial layer under a corresponding individual interfacial layer. 
     In one embodiment of the exemplary process, the precursor wafer further includes a number of individual buffer structures. Herein, each individual buffer structure resides between the silicon handle substrate and a corresponding individual interfacial layer. Each individual buffer structure is formed of SiGe with a vertically graded germanium concentration. The vertically graded germanium concentration within each individual buffer structure increases from the silicon handle substrate to the corresponding individual interfacial layer. Each individual interfacial layer is not strained by the silicon handle substrate and has a lattice constant greater than 5.461 at a temperature of 300K. The individual silicon epitaxial layer used to form the active layer of the corresponding device region is grown under and strained by a corresponding individual interfacial layer, such that a lattice constant of silicon in the individual silicon epitaxial layer is greater than 5.461 at a temperature of 300K. 
     According to another embodiment, the exemplary process further includes removing each individual buffer structure and each individual interfacial layer after removing the silicon handle substrate and before applying the barrier layer. 
     In one embodiment of the exemplary process, the active layer of each device region is in contact with the barrier layer after the barrier layer is applied. 
     According to another embodiment, the exemplary process further includes applying a passivation layer directly over the active layer of each device region after removing each individual buffer structure and each individual interfacial layer and before applying the barrier layer. Herein, the passivation layer is formed of silicon dioxide, and the barrier layer is directly over each passivation layer after the barrier layer is applied. 
     In one embodiment of the exemplary process, the passivation layer is applied by one of a plasma enhanced deposition process, an anodic oxidation process, and an ozone-based oxidation process. 
     In one embodiment of the exemplary process, the precursor wafer further includes a number of individual buffer structures. Herein, each individual buffer structure resides between a corresponding individual interfacial layer and one active layer of the corresponding device region. Each individual buffer structure is formed of SiGe with a vertically graded germanium concentration. The vertically graded germanium concentration within each individual buffer structure increases from the corresponding individual interfacial layer to the active layer of the corresponding device region. The individual silicon epitaxial layer used to form the active layer of the corresponding device region is grown under and strained by a corresponding individual buffer structure, such that a lattice constant of silicon in the individual silicon epitaxial layer is greater than a lattice constant of silicon in the silicon handle substrate. 
     In one embodiment of the exemplary process, providing the precursor wafer begins with providing a starting wafer that includes a common silicon epitaxial layer, a common interfacial layer over the common silicon epitaxial layer, and a silicon handle substrate over the common interfacial layer. The common interfacial layer is formed of SiGe with a uniform concentration of germanium greater than 15%. A complementary metal-oxide-semiconductor (CMOS) process is then performed to provide the precursor wafer. Herein, the isolation sections extend through the common silicon epitaxial layer and the common interfacial layer, and extend into the silicon handle substrate, such that the common interfacial layer is separated into the individual interfacial layers, and the common silicon epitaxial layer is separated into a number of individual silicon epitaxial layers. Each active layer is formed from a corresponding individual silicon epitaxial layer, each individual interfacial layer resides over a top surface of a corresponding active layer, and the silicon handle substrate resides over the interfacial layers. 
     In one embodiment of the exemplary process, the starting wafer further includes a common buffer structure between the silicon handle substrate and the common interfacial layer. Herein, the common buffer structure is formed of SiGe with a vertically graded germanium concentration. The vertically graded germanium concentration within the common buffer structure increases from the silicon handle substrate to the common interfacial layer. The common interfacial layer is not strained by the silicon handle substrate and has a lattice constant greater than 5.461 at a temperature of 300K. The common silicon epitaxial layer is grown under and strained by the common interfacial layer, such that a lattice constant of silicon in the common silicon epitaxial layer is greater than 5.461 at a temperature of 300K. 
     In one embodiment of the exemplary process, the isolation sections extend through the common silicon epitaxial layer, the common interfacial layer, the common buffer structure, and extend into the silicon handle substrate, such that the common buffer structure is separated into a number of individual buffer structures, the common interfacial layer is separated into a number of individual interfacial layers, and the common silicon epitaxial layer is separated into a number of individual silicon epitaxial layers. Herein, each individual buffer structure directly resides over a corresponding interfacial layer, and the silicon handle substrate resides directly over the number of individual buffer structures. 
     In one embodiment of the exemplary process, the starting wafer further includes a common buffer structure between the common interfacial layer and the common silicon epitaxial layer. Herein, the common buffer structure is formed of SiGe with a vertically graded germanium concentration. The vertically graded germanium concentration within the common buffer structure increases from the common interfacial layer to the common silicon epitaxial layer. The common silicon epitaxial layer is grown under and strained by the common buffer structure, such that a lattice constant of silicon in the common silicon epitaxial layer is greater than a lattice constant of silicon in the silicon handle substrate. 
     In one embodiment of the exemplary process, the silicon handle substrate is removed by a mechanical grinding process followed by an etching process. 
     In one embodiment of the exemplary process, the silicon handle substrate is removed by an etching process with an etchant chemistry, which is at least one of tetramethylammonium hydroxide (TMAH), potassium hydroxide (KOH), sodium hydroxide (NaOH), acetylcholine (ACH), and xenon difluoride (XeF 2 ). 
     In one embodiment of the exemplary process, the silicon handle substrate is removed by a reactive ion etching system with a chlorine-based gas chemistry. 
     In one embodiment of the exemplary process, the barrier layer is applied by a plasma enhanced chemical vapor deposition (PECVD) system or an atomic layer deposition (ALD) system. 
     In one embodiment of the exemplary process, the first mold compound has a thermal conductivity greater than 1 W/m·K and a dielectric constant less than 8. 
     Those skilled in the art will appreciate the scope of the present disclosure and realize additional aspects thereof after reading the following detailed description of the preferred embodiments in association with the accompanying drawing figures. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWING FIGURES 
       The accompanying drawing figures incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure. 
         FIG. 1  shows an exemplary radio frequency (RF) device with enhanced performance according to one embodiment of the present disclosure. 
         FIG. 2  shows an alternative RF device with enhanced thermal and electrical performance according to one embodiment of the present disclosure. 
         FIGS. 3A-15  show an exemplary wafer-level fabricating and packaging process that illustrates steps to provide the exemplary RF device shown in  FIG. 1 . 
         FIGS. 16-21  show an alternative wafer-level fabricating and packaging process that illustrates steps to provide the alternative RF device shown in  FIG. 2 . 
     
    
    
     It will be understood that for clear illustrations,  FIGS. 1-21  may not be drawn to scale. 
     DETAILED DESCRIPTION 
     The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims. 
     It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. 
     It will be understood that when an element such as a layer, region, or substrate is referred to as being “on” or extending “onto” another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being “over” or extending “over” another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly over” or extending “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. 
     Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” or “over” or “under” may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures. 
     The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and/or “including” when used herein specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. 
     Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. 
     With the looming shortage of conventional radio frequency silicon on insulator (RFSOI) wafers expected in the coming years, alternative technologies are being devised to get around the need for high resistivity using silicon wafers, the trap rich layer formation, and Smart-Cut SOI wafer process. One alternative technology is based on the use of a silicon germanium (SiGe) interfacial layer instead of a buried oxide layer (BOX) between a silicon substrate and a silicon epitaxial layer. However, this technology will also suffer from the deleterious distortion effects due to the silicon substrate, similar to what is observed in an RFSOI technology. The present disclosure, which relates to a radio frequency (RF) device with enhanced performance, and a wafer-level fabricating and packaging process for making the same, utilizes the SiGe interfacial layer without deleterious distortion effects from the silicon substrate. 
       FIG. 1  shows an exemplary RF device  10  with enhanced performance according to one embodiment of the present disclosure. For the purpose of this illustration, the exemplary RF device  10  includes a mold device die  12  that has a device region  14 , a barrier layer  15 , and a first mold compound  16 , and a multilayer redistribution structure  18  formed under the device region  14  of the mold device die  12 . 
     In detail, the device region  14  includes a front-end-of-line (FEOL) portion  20  and a back-end-of-line (BEOL) portion  22  underneath the FEOL portion  20 . In one embodiment, the FEOL portion  20  may be configured to provide a switch field-effect transistor (FET), and includes an active layer  24  and a contact layer  26 . The active layer  24  may be formed from a relaxed silicon epitaxial layer or from a strained silicon epitaxial layer, and includes a source  28 , a drain  30 , and a channel  32  between the source  28  and the drain  30 . Herein, a relaxed silicon epitaxial layer refers to a silicon epitaxial layer, in which the lattice constant of silicon is 5.431 at a temperature of 300K. The strained silicon epitaxial layer refers to a silicon epitaxial layer, in which the lattice constant of silicon is greater than the lattice constant in the relaxed silicon epitaxial layer, such as greater than 5.461, or greater than 5.482, or greater than 5.493, or greater than 5.515 at a temperature of 300K. As such, electrons in the strained silicon epitaxial layer may have enhanced mobility compared to the relaxed silicon epitaxial layer. Consequently, a FET formed from the strained silicon epitaxial layer may have a faster switching speed compared to a FET formed from a relaxed silicon epitaxial layer. 
     The contact layer  26  is formed underneath the active layer  24  and includes a gate structure  34 , a source contact  36 , a drain contact  38 , and a gate contact  40 . The gate structure  34  may be formed of silicon oxide, and extends horizontally underneath the channel  32  (i.e., from underneath the source  28  to underneath the drain  30 ). The source contact  36  is connected to and under the source  28 , the drain contact  38  is connected to and under the drain  30 , and the gate contact  40  is connected to and under the gate structure  34 . An insulating material  42  may be formed around the source contact  36 , the drain contact  38 , the gate structure  34 , and the gate contact  40  to electrically separate the source  28 , the drain  30 , and the gate structure  34 . In different applications, the FEOL portion  20  may have different FET configurations or provide different device components, such as a diode, a capacitor, a resistor, and/or an inductor. 
     In addition, the FEOL portion  20  also includes isolation sections  44 , which reside over the insulating material  42  of the contact layer  26  and surround the active layer  24 . The isolation sections  44  are configured to electrically separate the RF device  10 , especially the active layer  24 , from other devices formed in a common wafer (not shown). Herein, the isolation sections  44  may extend from a top surface of the contact layer  26  and vertically beyond a top surface of the active layer  24  to define an opening  46  that is within the isolation sections  44  and over the active layer  24 . The isolation sections  44  may be formed of silicon dioxide, which may be resistant to etching chemistries such as tetramethylammonium hydroxide (TMAH), xenon difluoride (XeF 2 ), potassium hydroxide (KOH), sodium hydroxide (NaOH), or acetylcholine (ACH), and may be resistant to a dry etching system, such as a reactive ion etching (RIE) system with a chlorine-based gas chemistry. 
     In some applications, the active layer  24  may be passivated to achieve proper low levels of current leakage in the device. The passivation may be accomplished with deposition of a passivation layer  48  over the top surface of the active layer  24  and within the opening  46 . The passivation layer  48  may be formed of silicon dioxide. In some applications, the RF device  10  may further include an interfacial layer and/or a buffer structure (not shown), which are formed of SiGe, over the top surface of the active layer  24  (described in the following paragraphs and not shown herein). If the passivation layer  48 , the buffer structure, and the interfacial layer exist, the interfacial layer and the buffer structure are vertically between the active layer  24  and the passivation layer  48 . 
     The barrier layer  15  extends over an entire backside of the device region  14 , such that the barrier layer  15  continuously covers exposed surfaces within the opening  46  and top surfaces of the isolation sections  44 . If the passivation layer  48  exists, the barrier layer  15  resides over the passivation layer  48 . If the passivation layer  48  is omitted, and the interfacial layer and/or the buffer structure exist, the barrier layer  15  resides over the interfacial layer or the buffer structure (not shown). If the passivation layer  48 , the buffer structure, and the interfacial layer are omitted, the barrier layer  15  may be in contact with the active layer  24  of the FEOL portion  20  (not shown). Note that the barrier layer  15  always covers the active layer  24 . 
     Herein, the barrier layer  15  is formed of silicon nitride with a thickness between 100 Å and 10 μm. The barrier layer  15  is configured to provide an excellent barrier to moisture and impurities, which could diffuse into the channel  32  of the active layer  24  and cause reliability concerns in the device. Moisture, for example, may diffuse readily through a silicon oxide layer (like the passivation layer  48 ), but even a thin nitride layer (like the barrier layer  15 ) reduces the diffusion of the water molecule by several orders of magnitude, acting as an ideal barrier. In addition, the barrier layer  15  may also be engineered so as to provide additional tensile strain to the active layer  24 . Such strain may be beneficial in providing additional improvement of electron mobility in n-channel devices. In some applications, the barrier layer  15  formed of silicon nitride may further passivate the active layer  24 . In such case, there may be no need for the passivation layer  48  described above. 
     The first mold compound  16  is directly over the barrier layer  15  and fills the opening  46 . The first mold compound  16  may be formed of thermoplastics or thermoset polymer materials, such as polyphenylene sulfide (PPS), overmold epoxies doped with boron nitride, alumina, carbon nanotubes, or diamond-like thermal additives, or the like. Notice that, regardless of the presence of the barrier layer  15 , the passivation layer  48 , or the interfacial layer, silicon crystal, which has no germanium, nitrogen, or oxygen content, does not exist between the first mold compound  16  and the top surface of the active layer  24 . Each of the barrier layer  15 , the passivation layer  48 , and the interfacial layer is formed of silicon composite. 
     Further, in some applications, the top surface of each isolation section  44  and the top surface of the active layer  24  may be coplanar (not shown), and the opening  46  is omitted. The barrier layer  15  resides over both the active layer  24  and the isolation sections  44  of the FEOL portion  20 , and the first mold compound  16  resides over the barrier layer  15 . Note that the active layer  24  never extends vertically beyond the isolation sections  44 , otherwise the isolation sections  44  may not fully separate the active layer  24  from other devices formed from the same wafer. 
     The BEOL portion  22  is underneath the FEOL portion  20  and includes multiple connecting layers  50  formed within dielectric layers  52 . Some of the connecting layers  50  (for internal connection) are encapsulated by the dielectric layers  52  (not shown), while some of the connecting layers  50  have a bottom portion not covered by the dielectric layers  52 . Certain connecting layers  50  are electrically connected to the FEOL portion  20 . For the purpose of this illustration, one of the connecting layers  50  is connected to the source contact  36 , and another connecting layer  50  is connected to the drain contact  38 . 
     The multilayer redistribution structure  18 , which is formed underneath the BEOL portion  22  of the mold device die  12 , includes a number of redistribution interconnections  54 , a dielectric pattern  56 , and a number of bump structures  58 . Herein, each redistribution interconnection  54  is connected to a corresponding connecting layer  50  within the BEOL portion  22  and extends over a bottom surface of the BEOL portion  22 . The connections between the redistribution interconnections  54  and the connecting layers  50  are solder-free. The dielectric pattern  56  is formed around and underneath each redistribution interconnection  54 . Some of the redistribution interconnections  54  (connect the mold device die  12  to other device components formed from the same wafer) may be encapsulated by the dielectric pattern  56  (not shown), while some of the redistribution interconnections  54  have a bottom portion exposed through the dielectric pattern  56 . Each bump structure  58  is formed at a bottom surface of the multilayer redistribution structure  18  and electrically coupled to a corresponding redistribution interconnection  54  through the dielectric pattern  56 . As such, the redistribution interconnections  54  are configured to connect the bump structures  58  to certain ones of the connecting layers  50  in the BEOL portion  22 , which are electrically connected to the FEOL portion  20 . Consequently, the bump structures  58  are electrically connected to the FEOL portion  20  via corresponding redistribution interconnections  54  and corresponding connecting layers  50 . In addition, the bump structures  58  are separate from each other and protrude from the dielectric pattern  56 . 
     In some applications, there may be extra redistribution interconnections (not shown) electrically coupled to the redistribution interconnections  54  through the dielectric pattern  56 , and extra dielectric patterns (not shown) formed underneath the dielectric pattern  56 , such that a bottom portion of some extra redistribution interconnections may be exposed. Consequently, each bump structure  58  is coupled to a corresponding extra redistribution interconnection through the extra dielectric pattern (not shown). Regardless of the level numbers of the redistribution interconnections and/or the dielectric pattern, the multilayer redistribution structure  18  may be free of glass fiber or glass-free. Herein, the glass fiber refers to individual glass strands twisted to become a larger grouping. These glass strands may then be woven into a fabric. The redistribution interconnections  54  may be formed of copper or other suitable metals. The dielectric pattern  56  may be formed of benzocyclobutene (BCB), polyimide, or other dielectric materials. The bump structures  58  may be solder balls or copper pillars. The multilayer redistribution structure  18  has a thickness between 2 μm and 300 μm. 
     The heat generated in the device region  14  may travel upward to a bottom portion of the first mold compound  16 , which is over the active layer  24 , and then will pass downward through the device region  14  and toward the multilayer redistribution structure  18 , which will dissipate the heat. It is therefore highly desirable for the first mold compound  16  to have a high thermal conductivity, especially for a portion next to the active layer  24 . The first mold compound  16  may have a thermal conductivity between 1 W/m·K and 100 W/m·K, or between 7 W/m·K and 20 W/m·K. In addition, the first mold compound  16  may have a low dielectric constant less than 8, or between 3 and 5 to yield low RF coupling. A thickness of the first mold compound  16  is based on the required thermal performance of the RF device  10 , the device layout, the distance from the multilayer redistribution structure  18 , as well as the specifics of the package and assembly. The first mold compound  16  may have a thickness between 200 μm and 500 μm. 
       FIG. 2  shows an alternative RF device  10 A, which further includes a second mold compound  60  compared to the RF device  10  shown in  FIG. 1 . Herein, the multilayer redistribution structure  18  may extend horizontally beyond the mold device die  12 , and the second mold compound  60  resides over the multilayer redistribution structure  18  to encapsulate the mold device die  12 . In this embodiment, the redistribution interconnections  54  of the multilayer redistribution structure  18  may extend horizontally beyond the mold device die  12 , and the bump structures  58  of the multilayer redistribution structure  18  may not be confined within a periphery of the mold device die  12 . The second mold compound  60  may be formed of a same or different material as the first mold compound  16 . Unlike the first mold compound  16 , the second mold compound  60  may not have thermal conductivity or dielectric constant requirements. 
       FIGS. 3A-15  provide an exemplary wafer-level fabricating and packaging process that illustrates steps to fabricate the exemplary RF device  10  shown in  FIG. 1 . Although the exemplary steps are illustrated in a series, the exemplary steps are not necessarily order dependent. Some steps may be done in a different order than that presented. Further, processes within the scope of this disclosure may include fewer or more steps than those illustrated in  FIGS. 3A-15 . 
     Initially, a starting wafer  62  is provided as illustrated in  FIGS. 3A and 3B . The starting wafer  62  includes a common silicon epitaxial layer  64 , a common interfacial layer  66  over the common silicon epitaxial layer  64 , and a silicon handle substrate  68  over the common interfacial layer  66 . Herein, the common silicon epitaxial layer  64  is formed from a device grade silicon material, which has desirable silicon epitaxy characteristics to form electronic devices. The silicon handle substrate  68  may consist of conventional low cost, low resistivity, and high dielectric constant silicon, which may have a lattice constant about 5.431 at a temperature of 300K. The common interfacial layer  66  is formed of SiGe, which separates the common silicon epitaxial layer  64  from the silicon handle substrate  68 . 
     At a fixed temperature, e.g., 300K, a lattice constant of relaxed silicon is 5.431 Å, while a lattice constant of relaxed Si 1-x Ge x  depends on the germanium concentration, such as (5.431+0.2x+0.027x 2 ) Å. The lattice constant of relaxed SiGe is larger than the lattice constant of relaxed silicon. If the common interfacial layer  66  is directly grown under the silicon handle substrate  68 , the lattice constant in the common interfacial layer  66  will be strained (reduced) by the silicon handle substrate  68 . If the common silicon epitaxial layer  64  is directly grown under the common interfacial layer  66 , the lattice constant in the common silicon epitaxial layer  64  may remain as the original relaxed form (about the same as the lattice constant in the silicon substrate). Consequently, the common silicon epitaxial layer  64  may not enhance electron mobility. 
     In one embodiment, a common buffer structure  70  may be formed between the silicon handle substrate  68  and the common interfacial layer  66 , as illustrated in  FIG. 3A . The common buffer structure  70  allows lattice constant transition from the silicon handle substrate  68  to the common interfacial layer  66 . The common buffer structure  70  may include multiple layers and may be formed of SiGe with a vertically graded germanium concentration. The germanium concentration within the common buffer structure  70  may increase from 0% at a top side (next to the silicon handle substrate  68 ) to X % at a bottom side (next to the common interfacial layer  66 ). The X % may depend on the germanium concentration within the common interfacial layer  66 , such as 15%, or 25%, or 30%, or 40%. The common interfacial layer  66 , which herein is grown under the common buffer structure  70 , may keep its lattice constant in relaxed form, and may not be strained (reduced) to match the lattice constant of the silicon handle substrate  68 . The germanium concentration may be uniform throughout the common interfacial layer  66  and greater than 15%, 25%, 30%, or 40%, such that the lattice constant of relaxed SiGe in the common interfacial layer  66  is greater than 5.461, or greater than 5.482, or greater than 5.493, or greater than 5.515 at a temperature of 300K. 
     Herein, the common silicon epitaxial layer  64  is grown directly under the relaxed common interfacial layer  66 , such that the common silicon epitaxial layer  64  has a lattice constant matching (stretching as) the lattice constant in the relaxed common interfacial layer  66 . Consequently, the lattice constant in the strained common silicon epitaxial layer  64  may be greater than 5.461, or greater than 5.482, or greater than 5.493, or greater than 5.515 at a temperature of 300K, and therefore greater than the lattice constant in a relaxed silicon epitaxial layer (e.g., 5.431 at a temperature of 300K). The strained common silicon epitaxial layer  64  may have higher electron mobility than a relaxed silicon epitaxial layer. A thickness of the common silicon epitaxial layer  64  may be between 700 nm and 2000 nm, a thickness of the common interfacial layer  66  may be between 200 Å and 600 Å, a thickness of the common buffer structure  70  may be between 100 nm and 1000 nm, and a thickness of the silicon handle substrate  68  may be between 200 μm and 700 μm. 
     In another embodiment, the common interfacial layer  66  may be formed directly under the silicon handle substrate  68 , and the common buffer structure  70  may be formed between the common interfacial layer  66  and the common silicon epitaxial layer  64 , as illustrated in  FIG. 3B . Herein, the lattice constant of the common interfacial layer  66  may be strained (reduced) by the silicon handle substrate  68 . The common buffer structure  70  may still be formed of SiGe with a vertically graded germanium concentration. The germanium concentration within the common buffer structure  70  may increase from 0% at a top side (next to the common interfacial layer  66 ) to X % at a bottom side (next to the common silicon epitaxial layer  64 ). The X % may be 15%, or 25%, or 30%, or 40%. The lattice constant at the bottom side of the common buffer structure  70  is greater than a lattice constant at the top side of the common buffer structure  70 . The common silicon epitaxial layer  64 , which herein is grown under the common buffer structure  70 , has a lattice constant matching (stretching as) the lattice constant at the bottom side of the common buffer structure  70 . Consequently, the lattice constant in the strained common silicon epitaxial layer  64  is greater than the lattice constant in a relaxed silicon epitaxial layer (e.g., 5.431 at a temperature of 300K). 
     In some applications, the common buffer structure  70  is omitted (not shown). The common interfacial layer  66  is grown directly under the silicon handle substrate  68  and the common silicon epitaxial layer  64  is grown directly under the common interfacial layer  66 . As such, the lattice constant in the common interfacial layer  66  is strained (reduced) to match the lattice constant in the silicon handle substrate  68 , and the lattice constant in the common silicon epitaxial layer  64  remains as the original relaxed form (about the same as the lattice constant in the silicon substrate). 
     Next, a complementary metal-oxide-semiconductor (CMOS) process is performed on the starting wafer  62  (in  FIG. 3A ) to provide a precursor wafer  72  with a number of the device regions  14 , as illustrated in  FIG. 4A . For the purpose of this illustration, the FEOL portion  20  of each device region  14  is configured to provide a switch FET. In different applications, the FEOL portion  20  may have different FET configurations or provide different device components, such as a diode, a capacitor, a resistor, and/or an inductor. 
     In one embodiment, the isolation sections  44  of each device region  14  extend through the common silicon epitaxial layer  64 , the common interfacial layer  66 , and the common buffer structure  70 , and extend into the silicon handle substrate  68 . As such, the common buffer structure  70  is separated into a number of individual buffer structures  70   l , the common interfacial layer  66  is separated into a number of individual interfacial layers  66   l , and the common silicon epitaxial layer  64  is separated into a number of individual silicon epitaxial layers  64   l . Each individual silicon epitaxial layer  64   l  is used to form a corresponding active layer  24  in one device region  14 . The isolation sections  44  may be formed by shallow trench isolation (STI). Herein, if the active layer  24  is formed from one individual silicon epitaxial layer  64   l  with strained (increased) lattice constant, the FET based on the active layer  24  may have a faster switching speed (lower ON-resistance) than a FET formed from a relaxed silicon epitaxial layer with relaxed lattice constant. 
     The top surface of the active layer  24  is in contact with a corresponding interfacial layer  66   l , which is underneath a corresponding buffer structure  70   l . The silicon handle substrate  68  resides over each individual buffer structure  70   l , and portions of the silicon handle substrate  68  may reside over the isolation sections  44 . The BEOL portion  22  of the device region  14 , which includes at least the multiple connecting layers  50  and the dielectric layers  52 , is formed under the contact layer  26  of the FEOL portion  20 . Bottom portions of certain connecting layers  50  are exposed through the dielectric layers  52  at the bottom surface of the BEOL portion  22 . 
     In another embodiment, the isolation sections  44  may not extend into the silicon handle substrate  68 . Instead, the isolation sections  44  may only extend through the common silicon epitaxial layer  64  and extend into the common interfacial layer  66 , as illustrated in  FIG. 4B . Herein, the common interfacial layer  66  remains continuous, and resides over the top surface of each active layer  24  and a top surface of each isolation section  44 . The common buffer structure  70  and the silicon handle substrate  68  remain intact. In addition, the isolation sections  44  may extend through the common silicon epitaxial layer  64  and the common interfacial layer  66 , and extend into the common buffer structure  70  (not shown). The common buffer structure  70  remains continuous and resides over each individual interfacial layer  66   l  and each isolation section  44 . The silicon handle substrate  68  remains over the common buffer structure  70 . Further, the isolation sections  44  may extend through the common silicon epitaxial layer  64  but do not extend into the common interfacial layer  66  (not shown). The top surface of each isolation section  44  and the top surface of each active layer  24  may be coplanar (not shown). The common interfacial layer  66 , the common buffer structure  70 , and the silicon handle substrate  68  remain intact. The common interfacial layer  66  is over each isolation section  44  and each active layer  24 , the common buffer structure  70  remains over the common interfacial layer  66 , and the silicon handle substrate  68  remains over the common buffer structure  70 . 
     After the precursor wafer  72  is completed, the precursor wafer  72  is then bonded to a temporary carrier  74 , as illustrated in  FIG. 5 . The precursor wafer  72  may be bonded to the temporary carrier  74  via a bonding layer  76 , which provides a planarized surface to the temporary carrier  74 . The temporary carrier  74  may be a thick silicon wafer from a cost and thermal expansion point of view, but may also be constructed of glass, sapphire, or any other suitable carrier material. The bonding layer  76  may be a span-on polymeric adhesive film, such as the Brewer Science WaferBOND line of temporary adhesive materials. 
     The silicon handle substrate  68  is then selectively removed to provide an etched wafer  78 , as illustrated in  FIG. 6 . The selective removal stops at each individual buffer structure  70   l  or at each interfacial layer  66   l . If the isolation sections  44  extend vertically beyond each individual buffer structure  70   l , the removal of the silicon handle substrate  68  will provide the opening  46  over each active layer  24  and within the isolation sections  44 . Removing the silicon handle substrate  68  may be provided by a mechanical grinding process and an etching process, or provided by the etching system itself. As an example, the silicon handle substrate  68  may be ground to a thinner thickness to reduce the following etching time. An etching process is then performed to at least completely remove the remaining silicon handle substrate  68 . Since the silicon handle substrate  68 , the individual buffer structure  70   l , and the individual interfacial layer  66   l  have different germanium concentrations, they may have different reactions to a same etching technique (for instance: different etching speeds with a same etchant). Consequently, the etching system may be capable of identifying the presence of the individual buffer structures  70   l  or the individual interfacial layers  66   l  (presence of germanium), and capable of indicating when to stop the etching process. Typically, the higher the germanium concentration, the better the etching selectivity between the silicon handle substrate  68  and the individual buffer structures  70   l  (or between the silicon handle substrate  68  and the individual interfacial layers  66   l ). The etching process may be provided by a wet etching system with an etchant chemistry, which is at least one of TMAH, KOH, NaOH, ACH, and XeF 2 , or a dry etching system, such as a reactive ion etching system with a chlorine-based gas chemistry. 
     During the removal process, the isolation sections  44  are not removed and protect sides of each active layer  24 . The bonding layer  76  and the temporary carrier  74  protect the bottom surface of each BEOL portion  22 . Herein, the top surface of each isolation section  44  and the top surface of each individual buffer structure  70   l  (or each individual interfacial layer  66   l ) are exposed after the removal step. If the isolation sections  44  only extend into the common buffer structure  70 , or only extend into the common interfacial layer  66 , or the top surface of each isolation section  44  and the top surface of each active layer  24  are coplanar, only the top surface of the common buffer structure  70  or the common interfacial layer  66  may be exposed (not shown). 
     Due to the narrow gap nature of the SiGe material, it is possible that the individual buffer structures  70   l  and/or the individual interfacial layers  66   l  may be conductive (for some type of devices). The individual buffer structures  70   l  and/or the individual interfacial layers  66   l  may cause appreciable leakage between the source  28  and the drain  30  of the active layer  24 . Therefore, in some applications, such as FET switch applications, it is desirable to also remove the individual buffer structures  70   l  and the individual interfacial layers  66   l , as illustrated in  FIG. 7 . Each active layer  24  is exposed (at a bottom of a corresponding opening  46 , if there is one opening  46  over each active layer  24 ). The individual buffer structures  70   l  and the individual interfacial layers  66   l  may be removed by the same etching process used to remove the silicon handle substrate  68 , or may be removed by another etching process, such as a chlorine-base dry etching system. Herein, if each individual interfacial layer  66   l  is thin enough, it may not cause any appreciable leakage between the source  28  and the drain  30  of the FEOL portion  20 . In that case, the individual interfacial layers  66   l  may be left (not shown). Similarly, if both the individual interfacial layer  66   l  and the individual buffer structure  70   l  are thin enough, they may not cause any appreciable leakage between the source  28  and the drain  30  of the FEOL portion  20 . Such that, the individual interfacial layers  66   l  and the individual buffer structures  70   l  may be left (not shown). 
     In some applications, after the removal of the silicon handle substrate  68 , the individual buffer structures  70   l , and the individual interfacial layers  66   l , the active layer  24  may be passivated to achieve proper low levels of current leakage in the device. The passivation layer  48  may be formed directly over each active layer  24  of each FEOL portion  20 , as illustrated in  FIG. 8 . The passivation layer  48  may be formed of silicon dioxide by a plasma enhanced deposition process, an anodic oxidation process, an ozone-based oxidation process, and a number of other proper techniques. If there is one opening  46  over each active layer  24  and within the isolation sections  44 , the passivation layer  48  is formed within the opening  46 . The passivation layer  48  is configured to terminate the surface bonds at the top surface of the active layer  24 , which may be responsible for unwanted leakage. 
     Next, the barrier layer  15  is applied continuously over entire backside of the etched wafer  78 , as illustrated in  FIG. 9 . Herein, the barrier layer  15  covers exposed surfaces within each opening  46  and covers the top surface of each isolation section  44 . If the passivation layer  48  is applied, the barrier layer  15  is in contact with a top surface of each passivation layer  48 , and side surfaces of each isolation section  44  within each opening  46 . If the passivation layer  48  does not exist, and the individual interfacial layer  66   l  and/or the individual buffer structure  70   l  remain, the barrier layer  15  is in contact with a top surface of the individual interfacial layer  66   l  or the individual buffer structures  70   l , and the side surfaces of each isolation section  44  within each opening  46  (not shown). If the passivation layer  48 , the individual interfacial layer  66   l , and the individual buffer structure  70   l  do not exist, the barrier layer  15  is in contact with a top surface of each active layer  24  and the side surfaces of each isolation section  44  within each opening  46  (not shown). The barrier layer  15  always covers the top surface of each active layer  24 , side surfaces of each isolation section  44  within each opening  46 , and the top surface of each isolation section  44 . 
     Herein, the barrier layer  15  is formed of silicon nitride with a thickness between 100 Å and 10 μm. The barrier layer  15  is configured to provide an excellent barrier to moisture and impurities, which could diffuse into the channel  32  of the active layer  24  and cause reliability concerns in the device. Moisture, for example, may diffuse readily through a silicon oxide layer (like the passivation layer  48 ), but even a thin nitride layer (like the barrier layer  15 ) reduces the diffusion of the water molecule by several orders of magnitude, acting as an ideal barrier. In some applications, the barrier layer  15  formed of silicon nitride may further passivate the active layer  24 . In such case, there may be no need for the passivation layer  48 . The barrier layer  15  may be formed by a chemical vapor deposition system such as a plasma enhanced chemical vapor deposition (PECVD) system, or an atomic layer deposition (ALD) system. 
     The first mold compound  16  is then applied over the barrier layer  15  to provide a mold device wafer  80 , as illustrated in  FIG. 10 . The mold device wafer  80  includes a number of the mold device dies  12 , each of which includes the device region  14 , a portion of the barrier layer  15 , and a portion of the first mold compound  16 . Herein, the first mold compound  16  fills each opening  46  and fully covers the barrier layer  15 . Notice that, regardless of the presence of the barrier layer  15 , the passivation layer  48 , or the individual interfacial layer  66   l , silicon crystal, which has no germanium, nitrogen, or oxygen content, does not exist between the first mold compound  16  and the top surface of each active layer  24 . The barrier layer  15 , the passivation layer  48 , and the individual interfacial layer  66   l  are silicon composite. 
     The first mold compound  16  may be applied by various procedures, such as compression molding, sheet molding, overmolding, transfer molding, dam fill encapsulation, and screen print encapsulation. The first mold compound  16  may have a superior thermal conductivity between 1 W/m·K and 100 W/m·K, or between 7 W/m·K and 20 W/m·K. The first mold compound  16  may have a dielectric constant less than 8, or between 3 and 5. During the molding process of the first mold compound  16 , the temporary carrier  74  provides mechanical strength and rigidity to the etched wafer  78 . A curing process (not shown) is then performed to harden the first mold compound  16 . The curing temperature is between 100° C. and 320° C. depending on which material is used as the first mold compound  16 . After the curing process, the first mold compound  16  may be thinned and/or planarized (not shown). 
     The temporary carrier  74  is then debonded from the mold device wafer  80 , and the bonding layer  76  is cleaned from the mold device wafer  80 , as illustrated in  FIG. 11 . A number of debonding processes and cleaning processes may be applied depending on the nature of the temporary carrier  74  and the bonding layer  76  chosen in the earlier steps. For instance, the temporary carrier  74  may be mechanically debonded using a lateral blade process with the stack heated to a proper temperature. Other suitable processes involve radiation of UV light through the temporary carrier  74  if it is formed of a transparent material, or chemical debonding using a proper solvent. The bonding layer  76  may be eliminated by wet or dry etching processes, such as proprietary solvents and plasma washing. After the debonding and cleaning process, the bottom portions of certain ones of the connecting layers  50 , which may function as input/output (I/O) ports of the mold device die  12 , are exposed through the dielectric layers  52  at the bottom surface of each BEOL portion  22 . As such, each mold device die  12  in the mold device wafer  80  may be electrically verified to be working properly at this point. 
     With reference to  FIGS. 12 through 14 , the multilayer redistribution structure  18  is formed underneath the mold device wafer  80  according to one embodiment of the present disclosure. Although the redistribution steps are illustrated in a series, the redistribution steps are not necessarily order dependent. Some steps may be done in a different order than that presented. Further, redistribution steps within the scope of this disclosure may include fewer or more steps than those illustrated in  FIGS. 12-14 . 
     A number of the redistribution interconnections  54  are firstly formed underneath each BEOL portion  22 , as illustrated in  FIG. 12 . Each redistribution interconnection  54  is electrically coupled to the exposed bottom portion of the corresponding connecting layer  50  within the BEOL portion  22 , and may extend over the bottom surface of the BEOL portion  22 . The connections between the redistribution interconnections  54  and the connecting layers  50  are solder-free. The dielectric pattern  56  is then formed underneath each BEOL portion  22  to partially encapsulate each redistribution interconnection  54 , as illustrated in  FIG. 13 . As such, the bottom portion of each redistribution interconnection  54  is exposed through the dielectric pattern  56 . In different applications, there may be extra redistribution interconnections (not shown) electrically coupled to the redistribution interconnection  54  through the dielectric pattern  56 , and extra dielectric patterns (not shown) formed underneath the dielectric pattern  56 , such that a bottom portion of each extra redistribution interconnection is exposed. 
     Next, a number of the bump structures  58  are formed to complete the multilayer redistribution structure  18  and provide a wafer-level fan-out (WLFO) package  82 , as illustrated in  FIG. 14 . Each bump structure  58  is formed at the bottom of the multilayer redistribution structure  18  and electrically coupled to an exposed bottom portion of the corresponding redistribution interconnection  54  through the dielectric pattern  56 . Consequently, the redistribution interconnections  54  are configured to connect the bump structures  58  to certain ones of the connecting layer  50  in the BEOL portion  22 , which are electrically connected to the FEOL portion  20 . As such, the bump structures  58  are electrically connected to the FEOL portion  20  via corresponding redistribution interconnections  54  and corresponding connecting layers  50 . In addition, the bump structures  58  are separate from each other and protrude vertically from the dielectric pattern  56 . 
     The multilayer redistribution structure  18  may be free of glass fiber or glass-free. Herein, the glass fiber refers to individual glass strands twisted to become a larger grouping. These glass strands may then be woven into a fabric. The redistribution interconnections  54  may be formed of copper or other suitable metals, the dielectric pattern  56  may be formed of BCB, polyimide, or other dielectric materials, and the bump structures  58  may be solder balls or copper pillars. The multilayer redistribution structure  18  has a thickness between 2 μm and 300 μm.  FIG. 15  shows a final step to singulate the WLFO package  82  into individual RF devices  10 . The singulating step may be provided by a probing and dicing process at certain isolation sections  44 . 
     In another embodiment,  FIGS. 16-21  provide an alternative process that illustrates steps to fabricate the alternative RF device  10 A shown in  FIG. 2 . Although the exemplary steps are illustrated in a series, the exemplary steps are not necessarily order dependent. Some steps may be done in a different order than that presented. Further, processes within the scope of this disclosure may include fewer or more steps than those illustrated in  FIGS. 16-21 . 
     After the debonding and cleaning process to provide the clean mold device wafer  80  as shown in  FIG. 11 , a singulating step is performed to singulate the mold device wafer  80  into individual mold device dies  12 , as illustrated in  FIG. 16 . This singulating step may be provided by a probing and dicing process at certain isolation sections  44 . Herein, each mold device die  12  may have a same height and includes the device region  14  with the FEOL portion  20  and the BEOL portion  22 , the barrier layer  15 , and the first mold compound  16 . 
     Next, the second mold compound  60  is applied around and over the mold device dies  12  to provide a double mold device wafer  84 , as illustrated in  FIG. 17 . The second mold compound  60  encapsulates a top surface and side surfaces of each mold device die  12 , while a bottom surface of each mold device die  12 , which is the bottom surface of the BEOL portion  22 , is exposed. A bottom surface of the double mold device wafer  84  is a combination of the bottom surface of each mold device die  12  and a bottom surface of the second mold compound  60 . Herein, the bottom portions of certain ones of the connecting layers  50  remain exposed at the bottom surface of each mold device die  12 . The second mold compound  60  may be applied by various procedures, such as sheet molding, overmolding, compression molding, transfer molding, dam fill encapsulation, or screen print encapsulation. The second mold compound  60  may be formed of the same or different material as the first mold compound  16 . However, unlike the first mold compound  16 , the second mold compound  60  does not have thermal conductivity or electrical resistivity requirements. The second mold compound  60  may be an organic epoxy resin system or the like. A curing process (not shown) is then used to harden the second mold compound  60 . The curing temperature is between 100° C. and 320° C. depending on which material is used as the second mold compound  60 . A grinding process (not shown) may be performed to provide a planarized top surface of the second mold compound  60 . 
     With reference to  FIGS. 18 through 20 , the multilayer redistribution structure  18  is formed according to one embodiment of the present disclosure. Although the redistribution steps are illustrated in a series, the redistribution steps are not necessarily order dependent. Some steps may be done in a different order than that presented. Further, redistribution steps within the scope of this disclosure may include fewer or more steps than those illustrated in  FIGS. 18-20 . 
     A number of the redistribution interconnections  54  are firstly formed underneath the double mold device wafer  84 , as illustrated in  FIG. 18 . Each redistribution interconnection  54  is electrically coupled to the corresponding connecting layer  50  within the BEOL portion  22 , and may extend horizontally beyond the corresponding mold device die  12  and underneath the second mold compound  60 . The connections between the redistribution interconnections  54  and the connecting layers  50  are solder-free. The dielectric pattern  56  is then formed underneath the double mold device wafer  84  to partially encapsulate each redistribution interconnection  54 , as illustrated in  FIG. 19 . As such, the bottom portion of each redistribution interconnection  54  is exposed through the dielectric pattern  56 . In different applications, there may be extra redistribution interconnections (not shown) electrically coupled to the redistribution interconnection  54  through the dielectric pattern  56 , and extra dielectric patterns (not shown) formed underneath the dielectric pattern  56 , such that a bottom portion of each extra redistribution interconnection is exposed. 
     Next, a number of the bump structures  58  are formed to complete the multilayer redistribution structure  18  and provide an alternative WLFO package  82 A, as illustrated in  FIG. 20 . Each bump structure  58  is formed at the bottom of the multilayer redistribution structure  18  and electrically coupled to an exposed bottom portion of the corresponding redistribution interconnection  54  through the dielectric pattern  56 . Consequently, the redistribution interconnections  54  are configured to connect the bump structures  58  to certain ones of the connecting layers  50  in the BEOL portion  22 , which are electrically connected to the FEOL portion  20 . As such, the bump structures  58  are electrically connected to the FEOL portion  20  via corresponding redistribution interconnections  54  and corresponding connecting layers  50 . Herein, the bump structures  58  may not be confined within a periphery of a corresponding mold device die  12 . In addition, the bump structures  58  are separate from each other and protrude vertically from the dielectric pattern  56 . 
       FIG. 21  shows a final step to singulate the alternative WLFO package  82 A into individual alternative RF devices  10 A. The singulating step may be provided by a probing and dicing process at portions of the second mold compound  60 , which are horizontally between adjacent mold device dies  12 . 
     Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.