Patent Publication Number: US-7724219-B2

Title: Circuit and method of effectively enhancing drive control of light-emitting diodes

Description:
CLAIM FOR PRIORITY 
   This patent specification is based on Japanese Patent Application No. JP2005-138788 filed on May 11, 2005 in the Japan Patent Office, the entire contents of which are incorporated by reference herein. 
   FIELD OF THE INVENTION 
   The present invention relates to a circuit and method of light-emitting diode drive control, and more particularly to a circuit and method of effectively enhancing a drive control of light-emitting diodes. 
   BACKGROUND OF THE INVENTION 
   A plurality of white light-emitting diodes are used for a backlight of a liquid crystal display apparatus included in a mobile electronic apparatus such as a cellular phone. A conventional method using a constant-current drive is generally used to cause the plurality of white light-emitting diodes to emit light with even luminance. 
     FIG. 1  illustrates a light-emitting diode (hereinafter referred to as an LED) drive circuit using the conventional constant-current drive method. As shown in  FIG. 1 , the LED drive circuit includes an LED LED 101  and a resistor R 101  having a resistance value r 101 . When iL (not shown) and Vc represent a drive current and a reference voltage of the LED LED 101 , respectively, iL is equal to Vc divided by r 101  (i.e., iL=Vc/r 101 ). 
   In the LED drive circuit, the drive current iL of the LED LED 101  is controlled so that a voltage drop by the resistor R 101  becomes equal to the reference voltage Vc. Therefore, a battery voltage Vbat needs to be larger than a forward voltage VF of the LED LED 101  added to the reference voltage Vc. Further, by taking into account the fact that the battery voltage Vbat decreases in the course of use, the battery voltage Vbat needs to be much larger than the forward voltage VF of the LED LED 101  added to the reference voltage Vc. As a result, the amount of electricity consumed by components other than the LED LED 101  increases, thereby impairing efficiency in power supply. 
     FIG. 2  illustrates another conventional LED drive circuit. As shown in  FIG. 2 , the LED drive circuit includes an LED LED 111 , a resistor R 11 , a charge pump circuit  111 , an LED inactive state detection circuit  112 , and a switching control circuit  113 . 
   The charge pump circuit  111  is used as a power source for the LED LED 111  so as to attempt to eliminate an influence of fluctuations in the battery voltage Vbat on the LED LED 111 . The switching control circuit  113  controls switching of the LED LED 111  between an active state and an inactive state. The LED inactive state detection circuit  112  detects a state of the LED LED 111 . When the inactive state of the LED LED 111  is detected, an enable signal is turned off to stop operation of the charge pump circuit  111  to attempt to improve efficiency in power supply. 
   BRIEF SUMMARY OF THE INVENTION 
   The invention provides a light-emitting diode drive circuit which includes a plurality of light-emitting diodes, a power supply circuit configured to output a variable output voltage to supply electric power to each of the plurality of light-emitting diodes, a plurality of current sources each configured to drive a corresponding one of the plurality of light-emitting diodes, a bias voltage setting circuit configured to generate and output a reference voltage for causing each of the plurality of current sources to have a current having a predetermined constant value, and a minimum set voltage for causing each of the plurality of current sources to have the current having the predetermined constant value when the reference voltage is input to each of the current sources, and a voltage detection circuit configured to sequentially compare output voltages of the plurality of current sources with the minimum set voltage to supply one of the output voltages which is smaller than the minimum set voltage, wherein the power supply circuit is configured to control a supply voltage so that the output voltage output from the voltage detection circuit becomes greater than or equal to the minimum set voltage output from the bias voltage setting circuit. 
   The invention further provides a method of controlling a circuit for driving a plurality of light-emitting diodes which includes the steps of outputting a variable output voltage to supply electric power to each of the plurality of light-emitting diodes, driving the plurality of light-emitting diodes by using a plurality of current sources, generating a reference voltage for causing each of the plurality of current sources to have a current having a predetermined constant value, outputting the reference voltage, generating a minimum set voltage for causing each of the plurality of current sources to have the current having the predetermined constant value when the reference voltage is input to each of the current sources, outputting the minimum set voltage, sequentially comparing output voltages of the plurality of current sources with the minimum set voltage, outputting one of the output voltages which is smaller than the minimum set voltage, and controlling the output voltage so that the output voltages of all current sources become greater than or equal to the minimum set voltage. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     A more complete appreciation of the disclosure and many of the attendant advantages thereof will be readily obtained as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings, wherein: 
       FIG. 1  is a circuit diagram illustrating an LED drive circuit using a conventional constant-current drive method; 
       FIG. 2  is a circuit diagram illustrating another LED drive circuit using the conventional constant-current drive method; 
       FIG. 3  is a circuit diagram illustrating an LED drive circuit according to an exemplary embodiment of the present invention; 
       FIG. 4  is a circuit diagram illustrating a voltage detection circuit included in the LED drive circuit shown in  FIG. 3 ; and 
       FIG. 5  is a circuit diagram illustrating a bias voltage setting circuit included in the LED drive circuit shown in  FIG. 3 . 
   

   DETAILED DESCRIPTION OF THE INVENTION 
   In describing the preferred embodiment illustrated in the drawings, specific terminology is employed for the sake of clarity. However, the disclosure of this patent specification is not intended to be limited to the specific terminology so selected and it is to be understood that each specific element includes all technical equivalents that operate in a similar manner. Referring now to the drawings, wherein like reference numerals designate identical or corresponding parts throughout the several views, particularly to  FIG. 3 , an LED drive circuit according to a preferred embodiment of the present invention is described. 
     FIG. 3  illustrates an exemplary configuration of an LED drive circuit  1  according to the preferred embodiment of the invention. 
   As shown in  FIG. 3 , the LED drive circuit  1  includes a power supply circuit  2 ; a voltage detection circuit  3 ; a bias voltage setting circuit  4 ; LEDs LED 1 , LED 2 , LED 3 , and LED 4 ; drive transistors M 1 , M 2 , M 3 , and M 4 , each including an NMOS transistor; and a bypass condenser C 1 . The LED drive circuit  1  further includes an output terminal OUT; and input terminals DIN 1 , DIN 2 , DIN 3 , and DIN 4 . 
   The configuration of the LED drive circuit  1  is now described in detail below. 
   The power supply circuit  2  includes a highly efficient step-up switching regulator including a circuit such as a charge pump circuit. An output terminal of the power supply circuit  2  is connected to ground through the bypass condenser C 1 . 
   Further, the power supply circuit  2  is connected to each anode of the LEDs LED 1  to LED 4  through the output terminal OUT. Cathodes of the LEDs LED 1  to LED 4  are connected to the voltage detection circuit  3 , and to drains of the drive transistors M 1  to M 4 , respectively, through the input terminals DIN 1  to DIN 4 , respectively. Sources of the drive transistors M 1  to M 4  are connected to respective ground voltages. Gates of the drive transistors M 1  to M 4  are connected to the bias voltage setting circuit  4 . 
   The power supply circuit  2 , the voltage detection circuit  3 , and the bias voltage setting circuit  4  are connected to each other. 
   Next, functions of each component of the LED drive circuit  1  are now described. 
   The power supply circuit  2  receives an input voltage Vin, and raises the input voltage Vin to a predetermined voltage, and outputs the predetermined voltage as an output voltage Vout. The power supply circuit  2  supplies the output voltage Vout to the LEDs LED 1  to LED 4 . Further, the power supply circuit  2  receives an operation stop signal STP and an output drain voltage Vdsx from the voltage detection circuit  3 , and receives a minimum drain voltage Vds 0  from the bias voltage setting circuit  4 . The power supply circuit  2  stops a switching operation when the operation stop signal STP from the voltage detection circuit  3  becomes active. The power supply circuit  2  causes the output voltage Vout to rise until the output drain voltage Vdsx becomes greater than or equal to the minimum drain voltage Vds 0 . 
   In a case in which the power supply circuit  2  includes a charge pump circuit including a catch condenser, the bypass condenser C 1  may be removed as the catch condenser has the same function as the bypass condenser C 1 . 
   The bias voltage setting circuit  4  receives an external data signal Din including data Din 0  to Din 3  for setting drive currents for driving the LEDs LED 1  to LED 4 . The bias voltage setting circuit  4  generates a reference gate voltage Vgs 0  and the minimum drain voltage Vds 0  each having a value according to the data signal Din, and outputs the reference gate voltage Vgs 0  and the minimum drain voltage Vds 0 . The reference gate voltage Vgs 0  is input to each of the gates of the drive transistors M 1  to M 4 . When being in a saturation state, the drive transistors M 1  to M 4  provide respective drain currents. The reference gate voltage Vgs 0  sets the drain currents of the drive transistors M 1  to M 4  to a predetermined constant value of the drive currents for driving the LEDs LED 1  to LED 4 . The minimum drain voltage Vds 0  is input to the power supply circuit  2  and the voltage detection circuit  3 . The minimum drain voltage Vds 0  has a minimum voltage value for causing the drive transistors M 1  to M 4  to provide the drain currents having the predetermined constant value when the reference gate voltage Vgs 0  is input to the drive transistors M 1  to M 4 . 
   When Vth represents each threshold voltage of the drive transistors M 1  to M 4 , for example, the reference gate voltage Vgs 0  and the minimum drain voltage Vds 0  generated and output by the bias voltage setting circuit  4  satisfy the following relational expression:
 
 Vds 0≧ Vgs 0 −Vth    (Expression 1)
 
   The voltage detection circuit  3  receives drain voltages Vds 1 , Vds 2 , Vds 3 , and Vds 4  from the drive transistors M 1  to M 4 , respectively, and receives the minimum drain voltage Vds 0  from the bias voltage setting circuit  4 . The voltage detection circuit  3  sequentially selects one of the drain voltages Vds 1  to Vds 4  in a predetermined order. When the selected one of the drain voltages Vds 1  to Vds 4  is smaller than the minimum drain voltage Vds 0 , the voltage detection circuit  3  exclusively outputs the selected one of the drain voltages Vds 1  to Vds 4  as the output drain voltage Vdsx to the power supply circuit  2 . When the drain voltages Vds 1  to Vds 4  all become greater than or equal to the minimum drain voltage Vds 0 , the voltage detection circuit  3  asserts the predetermined operation stop signal STP, in other words, outputs the operation stop signal STP to the power supply circuit  2  to cause the power supply circuit  2  to stop operating. 
   Further, the voltage detection circuit  3  receives an external enable signal EN. The voltage detection circuit  3  outputs the output drain voltage Vdsx when the enable signal EN is asserted, and stops outputting the output drain voltage Vdsx when the enable signal EN is turned off. 
   Having the above configuration, the drive transistors M 1  to M 4  with the gates biased by the reference gate voltage Vgs 0  from the bias voltage setting circuit  4  attempt to provide the drain currents having the predetermined constant value from the power supply circuit  2  through the LEDs LED 1  to LED 4 . However, when the output voltage Vout of the power supply circuit  2  is smaller than forward voltages of the LEDs LED 1  to LED 4 , the drain currents of the drive transistors M 1  to M 4  have smaller values than the predetermined constant value of the drive currents. Accordingly, the drain voltages Vds 1  to Vds 4  of the drive transistors M 1  to M 4  are smaller than the minimum drain voltage Vds 0 . 
   The voltage detection circuit  3  compares each of the voltages Vds 1  to Vds 4  of the drive transistors M 1  to M 4  with the minimum drain voltage Vds 0 . A method of comparing the voltages is such that, for example, the drain voltage Vds 1  of the drive transistor M 1  is firstly compared with the minimum drain voltage Vds 0 , and when the drain voltage Vds 1  is smaller than the minimum drain voltage Vds 0 , the drain voltage Vds 1  is output by the voltage detection circuit  3  as the output drain voltage Vdsx. The voltage detection circuit  3  is configured not to output, in this case, results of the comparison between each of the drain voltages Vds 2  to Vds 4  with the minimum drain voltage Vds 0 . 
   The power supply circuit  2  raises the output voltage Vout when the output drain voltage Vdsx output from the voltage detection circuit  3  is smaller than the minimum drain voltage Vds 0  output from the bias voltage setting circuit  4 . Therefore, the drive currents of the LEDs LED 1  to LED 4  increase, and the drain voltages Vds 1  to Vds 4  also increase. 
   On the other hand, when the output drain voltage Vdsx output from the voltage detection circuit  3  becomes greater than or equal to the minimum drain voltage Vds 0 , the voltage detection circuit  3  inhibits outputting the drain voltage Vds 1  as the output drain voltage Vdsx, as the drain current of the drive transistor M 1  reaches the predetermined constant value of the drive currents, and compares the drain voltage Vds 2  of the drive transistor M 2  with the minimum drain voltage Vds 0 . 
   When the forward voltage of the LED LED 2  is larger than the forward voltage of the LED LED 1 , the drain voltage Vds 2  of the drive transistor M 2  is smaller than the minimum drain voltage Vds 0  since the drain voltage Vds 2  is smaller than the drain voltage Vds 1  of the drive transistor M 1 . Therefore, the voltage detection circuit  3  outputs the drain voltage Vds 2  as the output drain voltage Vdsx. The voltage detection circuit  3  is configured not to output, also in this case, the results of comparison between each of the drain voltages Vds 3  and Vds 4  with the minimum drain voltage Vds 0 . 
   The power supply circuit  2  operates as in the case the drain voltage Vds 1  is output as the output drain voltage Vdsx. In other words, the power supply circuit  2  further raises the output voltage Vout until the drain voltage Vds 2  becomes greater than or equal to the minimum drain voltage Vds 0 . 
   When the drain voltage Vds 2  becomes not smaller the minimum drain voltage Vds 0 , since the drain current of the drive transistor M 2  reaches the predetermined constant value of the drive currents, the voltage detection circuit  3  inhibits outputting the drain voltage Vds 2  as the output drain voltage Vdsx. Accordingly, the voltage detection circuit  3  sequentially compares the drain voltages Vds 3  and Vds 4  with the minimum drain voltage Vds 0 , and raises the output voltage Vout until the drain voltages Vds 1  to Vds 4  all become greater than or equal to the minimum drain voltage Vds 0 . 
   In a case of a drive transistor using an LED having a small forward voltage as a load, a drain voltage of the drive transistor may already be greater than or equal to the minimum drain voltage Vds 0  at the time of comparison. In the case, the voltage detection circuit  3  performs comparison between a drain voltage of another transistor and the minimum drain voltage Vds 0  without outputting the drain voltage of the drive transistor. 
   When the drain voltages Vds 1  to Vds 4  all become greater than or equal to the minimum drain voltage Vds 0 , the voltage detection circuit  3  asserts the operation stop signal STP to cause the power supply circuit  2  to stop operating. The power supply circuit  2  is provided with the bypass condenser C 1  at the output terminal thereof, and a current is supplied to the LEDs LED 1  to LED 4  from the bypass condenser C 1  for a while after the power supply circuit  2  stops operating. When a voltage of the bypass condenser C 1  drops, and any one of the drain voltages Vds 1  to Vds 4  falls below the minimum drain voltage Vds 0 , the voltage detection circuit  3  turns off the operation stop signal STP, outputs the drain voltage which has fallen below the minimum drain voltage Vds 0  as the output drain voltage Vdsx, and causes the power supply circuit  2  to raise the output voltage Vout. As the above operations are repeated, the LEDs LED 1  to LED 4  are always supplied with the drive currents having the predetermined constant value. 
     FIG. 4  illustrates an example of the voltage detection circuit  3  shown in  FIG. 3 . As shown in  FIG. 4 , the voltage detection circuit  3  includes comparators  11 ,  12 ,  13 , and  14 ; a drain voltage output circuit; and an operation stop signal output circuit. The drain voltage output circuit includes inverters INV 11 , INV 12 , INV 13 , INV 14 , INV 15 , INV 16 , INV 17 , and INV 18 ; AND circuits AN 11 , AN 12 , AN 13 , and AN 14 ; and analog switches AS 11 , AS 12 , AS 13 , and AS 14 . The operation stop signal output circuit includes an AND circuit AN 15 . 
   A configuration of the voltage detection circuit  3  is described below in detail. 
   Respective inverting inputs of the comparators  11  to  14  receive the drain voltages Vds 1  to Vds 4  of the drive transistors M 1  to M 4 , respectively. Non-inverting inputs of the comparators  11  to  14  are connected to each other, and a connection part thereof receives the minimum drain voltage Vds 0  from the bias voltage setting circuit  4 . Output terminals of the comparators  11  to  14  are connected to input terminals of the AND circuits AN 11  to AN 14 , respectively, and to input terminals of the inverter INV  11  to  14 , respectively. 
   The AND circuit AN 11  paired with the comparator  11  includes two input terminals. The AND circuit AN 12  paired with the comparator  12  includes three input terminals. The AND circuit AN 13  paired with the comparator  13  includes four input terminals. The AND circuit AN 14  paired with the comparator  14  includes five input terminals. The AND circuit AN 15  includes four input terminals. Output terminals of the AND circuits AN 11  to AN 14  are connected to control input terminals of the analog switches AS 11  to AS 14 , respectively, and to inverting control input terminals of the analog switches AS 11  to AS 14 , respectively, through inverters INV 15  to INV 18 , respectively. 
   An output terminal of the inverter INV 11  is connected to the input terminals of the AND circuits AN 12  to AN 15 . An output terminal of the inverter INV 12  is connected to the input terminals of the AND circuits AN 13  to AN 15 . An output terminal of the inverter INV 13  is connected to the input terminals of the AND circuits AN 14  and AN 15 . An output terminal of the inverter INV 14  is connected to the input terminal of the AND circuit AN 15 . An output terminal of the AND circuit AN 15  serves as an output terminal for outputting the operation stop signal STP. Further, each of the remaining input terminals of the AND circuits AN 11  to AN 14  receive the enable signal EN from outside. Input terminals of the analog switches AS 11  to AS 14  receive the drain voltages Vds 1  to Vds 4  of the drive transistors M 1  to M 4 , respectively. Output terminals of the analog switches AS 11  to AS 14  are connected to each other, and a connection part thereof serves as an output terminal of the voltage detection circuit  3  for outputting the output drain voltage Vdsx. 
   Next, operations of each component of the voltage detection circuit  3  are described below. 
   When a signal level of the enable signal EN is low, output levels of the AND circuits AN 11  to AN 14  are low. In the case, the analog switches AS 11  to AS 14  are turned off and shut off. As a result, the output terminal for outputting the output drain voltage Vdsx has high impedance. 
   On the other hand, when the signal level of the enable signal EN is high, the following operations are performed. The comparator  11  compares the minimum drain voltage Vds 0  with the drain voltage Vds 1  of the drive transistor M 1 . When the drain voltage Vds 1  is smaller than the minimum drain voltage Vds 0 , an output level of the comparator  11  becomes high to cause an output level of the AND circuit  11  to be high. As a result the analog switch AS 11  is turned on, and the drain voltage Vds 1  input to the input terminal of the analog switch AS 11  is output as the output drain voltage Vdsx. Since an output signal of the comparator  11  is input to the input terminals of the AND circuits AN 12  to AN 15  with a signal level inverted in the inverter INV 11 , output levels of the AND circuits AN 12  to AN 15  become low. As a result, the analog switches AS 12  to AS 14  are turned off and shut off. Therefore, only the drain voltage Vds 1  is output from the output terminal as the output drain voltage Vdsx. Further, a signal level of the operation stop signal STP becomes low to negate the operation stop signal STP. 
   As described above, the output voltage Vout of the power supply circuit  2  is raised. When the output voltage Vout of the power supply circuit  2  increases, and the drain voltage Vds 1  becomes greater than or equal to the minimum drain voltage Vds 0 , the output level of the comparator  11  becomes low, and the output level of the AND circuit AN 11  also becomes low. As a result, the analog switch AS 11  is turned off to stop outputting the drain voltage Vds 1  as the output drain voltage Vdsx. Further, as the output level of the comparator  11  becomes low, the output level of the inverter INV 11  becomes high. As a result, a gate of the AND circuit AN 12  is opened. 
   Then, the comparator  12  compares the minimum drain voltage Vds 0  with the drain voltage Vds 2  of the drive transistor M 2 . When the drain voltage Vds 2  is smaller than the minimum drain voltage Vds 0 , an output level of the comparator  12  becomes high, and the output level of the AND circuit AN 12  also becomes high. As a result, the analog switch AS 12  is turned on, and the drain voltage Vds 2  input to the input terminal of the analog switch AS 12  is output as the output drain voltage Vdsx. Since an output signal of the comparator  12  is input to the input terminals of the AND circuits AN 13  to AN 15  with a signal level inverted in the inverter INV 12 , the output levels of the AND circuits AN 13  to AN 15  become low. As a result, the analog switches AS 13  and AS 14  are turned off and shut off. Therefore, only the drain voltage Vds 2  is output as the output drain voltage Vdsx. 
   Next, the output voltage Vout of the power supply circuit  2  is raised. When the output voltage Vout of the power supply circuit  2  increases, and the drain voltage Vds 2  becomes greater than or equal to the minimum drain voltage Vds 0 , the output level of the comparator  12  is inverted to low, and the output level of the AND circuit AN 12  also becomes low. As a result, the analog switch AS 12  is turned off to stop outputting the drain voltage Vds 2  as the output drain voltage Vdsx. 
   Subsequent operations are performed by repeating procedures as described above, and when the drain voltages Vds 1  to Vds 4  all become greater than or equal to the minimum drain voltage Vds 0 , no drain voltage is output as the output drain voltage Vdsx. Instead, the output level of the AND circuit AN 15  becomes high to assert the operation stop signal STP. When the operation stop signal STP is input to the power supply circuit  2 , the power supply circuit  2  stops operating, and as a result, stops supplying power. 
     FIG. 5  illustrates an example of the bias voltage setting circuit  4  shown in  FIG. 3 . As shown in  FIG. 5 , the bias voltage setting circuit  4  includes a proportional current generation circuit  21  serving as a constant-current circuit, and a voltage generation circuit  22 . 
   The proportional current generation circuit  21  includes a D/A converter  25 ; an operation amplification circuit  26 ; a current mirror circuit including PMOS transistors M 21 , M 22 , and M 23 ; an NMOS transistor M 24 ; and a resistor R 21 . The voltage generation circuit  22  includes NMOS transistors M 25 , M 26 , and M 27  serving as first, second, and third MOS transistors, respectively. 
   The proportional current generation circuit  21  generates currents proportional to the drive currents of the LEDs LED 1  to LED 4 . The voltage generation circuit  22  generates the reference gate voltage Vgs 0  and the minimum drain voltage Vds 0 . 
   A configuration of the bias voltage setting circuit  4  is described in detail below. 
   An output terminal of the D/A converter is connected to a non-inverting input terminal of the operation amplification circuit  26 . An output terminal of the operation amplification circuit  26  is connected to a gate of the NMOS transistor M 24 . An inverting input terminal of the operation amplification circuit  26  is connected to a source of the NMOS transistor M 24 , and is connected to ground through the resistor R 21 . A drain of the NMOS transistor M 24  is connected to a drain of the PMOS transistor M 21  which is connected to a gate of the PMOS transistor M 21 . Further, sources of the PMOS transistors M 21  to M 23  are connected to respective input voltages Vin, and gates of the PMOS transistors M 21  to M 23  are connected to each other. 
   A drain of the PMOS transistor M 22  is connected to a drain of the NMOS transistor M 25 , and a source of the NMOS transistor M 25  is connected to ground. A gate of the NMOS transistor M 25  is connected to the drain of the NMOS transistor M 25 , and to a gate of the NMOS transistor M 26 . A drain of the PMOS transistor M 23  is connected to a drain of the NMOS transistor M 26 , and to a gate of the NMOS transistor M 27 . A source of the NMOS transistor M 26  is connected to a drain of the NMOS transistor M 27 . A source of the NMOS transistor M 27  is connected to ground. 
   The D/A converter  25  receives the data Din 0  to Din 3  for setting the drive currents of the LEDs LED 1  to LED 4  from an external control circuit (not shown). The D/A converter outputs an output voltage Dout to the non-inverting input terminal of the operation amplification circuit  26 . The reference gate voltage Vgs 0  is output from a connection part between the drain of the NMOS transistor M 26  and the gate of the NMOS transistor M 27 . The minimum drain voltage Vds 0  is output from a connection part between the source of the NMOS transistor M 26  and the drain of the NMOS transistor M 27 . 
   According to the above configuration, a drain current of the NMOS transistor M 24  is derived by the output voltage Dout of the D/A converter  25 , which is set by the data Din 0  to Din 3 , divided by a resistance value of the resistor R 21 . The drain current of the NMOS transistor M 24  is proportional to the drive currents of the LEDs LED 1  to LED, and is output from each of the drains of the PMOS transistors M 22  and M 23  included in the current mirror circuit. Further, the NMOS transistor M 27  forms another current mirror circuit with the drive transistors M 1  to M 4 . A size of an element of the NMOS transistor M 27  to a size of each element of the drive transistors M 1  to M 4  is in a predetermined proportion, and the drain currents of the drive transistors M 1  to M 4  are determined by a drain current of the NMOS transistor M 27  multiplied by a factor of the predetermined proportion. When the predetermined proportion is 1 to 500, for example, each of the drain currents of the drive transistors M 1  to M 4  is 500 times as large as the drain current of the NMOS transistor M 27 . 
   Further, minimum drain voltages of the drive transistors M 1  to M 4  for maintaining a proportional relation with the drain current of the NMOS transistor M 27  is equal to the minimum drain voltage Vds 0  which is a drain voltage of the NMOS transistor M 27 . 
   Further, the drain voltage of the NMOS transistor M 27  is determined by drain currents of the PMOS transistors M 22  and M 23 , and a ratio of a size of the NMOS transistor M 25  to a size of the NMOS transistor M 26 . Therefore, it is possible to set the drain voltage of the NMOS transistor M 27  to a minimum voltage for feeding proportional amounts of currents to the drive transistors M 1  to M 4 . Since source and drain voltages of the drive transistors M 1  to M 4  can be set to small values, an excessive rise in voltage is not necessary, and as a result, electricity saving may be achieved. 
   When the PMOS transistors M 22  and M 23  are configured to have the same size and the same drain current, and the ratio of the size of the NMOS transistor M 25  to the size of the NMOS transistor M 26  is set to 1 to 4, the minimum drain voltage Vds 0  is set to a minimum voltage for the NOMS transistor M 27  to operate as a constant-current source. However, the present invention is not limited to the above configuration. In consideration of variations in bias effects of substrates, the ratio of the size of the NMOS transistor M 25  to the size of the NMOS transistor M 26  is not limited to such a value that theoretically sets the minimum drain voltage Vds 0 , and includes such a value that can secure a constant-current value in each process. 
   According to the above configuration, the output voltage Vout of the power supply circuit  2  may be equal a largest forward voltage among the forward voltages of the LEDs LED 1  to LED 4  added with the minimum drain voltage Vds 0  of a corresponding one of the drive transistors M 1  to M 4 . Therefore, the minimum drain voltage Vds 0  is considerably small compared with the forward voltages of the LEDs LED 1  to LED 4 . As a result, drive efficiency of the LEDs LED 1  to LED 4  may be significantly enhanced. 
   As described above, since the LED drive circuit  1  according to the embodiment of the present invention does not use a resistor for setting the drive currents of the LEDs LED 1  to LED 4 , the output voltage Vout of the power supply circuit  2  may be reduced for an amount corresponding to a voltage drop otherwise caused by the resistor. Further, the output voltage Vout of the power supply circuit  2  only needs to supply the predetermined drive current to the LED having the largest forward voltage. As a result, the output voltage Vout may be further reduced. 
   In addition, since the drive transistors M 1  to M 4  are configured to have the minimum drain voltage Vds 0  for feeding the drive currents having the predetermined constant value in the saturation state, the output voltage Vout of the power supply circuit  2  may be further reduced, thereby significantly enhancing the drive efficiency of the LEDs LED 1  to LED 4 . 
   Although the above embodiment describes the exemplary case in which four LEDs are driven, the present invention is not limited thereto. The present invention is applied to an LED drive circuit for driving a plurality of LEDs. 
   The above specific embodiment is illustrative, and many variations can be introduced on the embodiment without departing from the spirit of the disclosure or from the scope of the appended claims. For example, elements and/or features of different illustrative embodiments may be combined with each other and/or substituted for each other within the scope of this disclosure and appended claims.