Patent Publication Number: US-9893613-B1

Title: DC/DC converter

Description:
INCORPORATION BY REFERENCE 
     The disclosure of Japanese Patent Application No. 2016-149188 filed on Jul. 29, 2016 and Japanese Patent Application No. 2016-236352 filed on Dec. 6, 2016 including those specifications, claims and drawings, is incorporated herein by reference in its entirety. 
     BACKGROUND 
     The present invention relates to a DC/DC converter. The DC/DC converter described in Japanese Patent Publication No. 5457559 (JP 5457559 B) is known. In the technology of JP 5457559 B, by controlling the switching operation of switching devices, the accumulation amount and the emission amount of energy to the reactor are controlled, voltage is stepped up from low voltage side to high voltage side, and power is transmitted, or voltage is stepped down from high voltage side to low voltage side, and power is transmitted. The DC/DC converter has a subject that the reactor enlarges and becomes heavy. In order to reduce the size and weight of the reactor, it is conceivable to reduce the voltage applied to the reactor and to reduce the inductance value required for the reactor. In the technology of JP 5457559 B, the first to the fourth switching devices connected in series are provided; and the charge and discharge capacitor, which is connected between the intermediate connection point of the first and the second switching devices and the intermediate connection point of the third and fourth switching devices, is provided. Then, by changing the duty factor of the first switching device and the duty factor of the second switching device in the opposite direction mutually, it is configured to control the voltage of the charge and discharge capacitor to the target voltage. By controlling the voltage of the charge and discharge capacitor to the target voltage, the voltage applied to the reactor is reduced and the size and weight of the reactor are reduced. 
     SUMMARY 
     However, in the technology of JP 5457559 B, it is necessary to switch the change direction of the duty factor, depending on the power transmission direction between low voltage side and high voltage side. Specifically, in the case of stepping up from low voltage side to high voltage side and transmitting power, in order to increase the voltage of the charge and discharge capacitor, it is necessary to increase the duty factors of the first and the third switching devices more than the duty factors of the second and the fourth switching devices, so as to increase the charging time of the charge and discharge capacitor more than the discharging time; on the other hand, in order to decrease the voltage of the charge and discharge capacitor, it is necessary to decrease the duty factors of the first and the third switching devices less than the duty factors of the second and the fourth switching devices, so as to increase the discharging time of the charge and discharge capacitor more than the charging time. 
     On the other hand, in the case of stepping down from high voltage side to low voltage side and transmitting power, in order to increase the voltage of the charge and discharge capacitor, it is necessary to decrease the duty factors of the first and the third switching devices less than the duty factors of the second and the fourth switching devices; on the other hand, in order to decrease the voltage of the charge and discharge capacitor, it is necessary to increase the duty factors of the first and the third switching devices more than the duty factors of the second and the fourth switching devices. 
     In the technology of JP 5457559 B, it is configured to determine the power transmission direction between low voltage side and high voltage side by the current direction flowing through the reactor. However, when the current sensor for detecting the current of the reactor has an error, the current direction flowing through the reactor in low power cannot be detected correctly. Accordingly, in the technology of JP 5457559 B, in low power, it was difficult to determine the power transmission direction momentarily with sufficient accuracy. 
     Therefore, in the technology of JP 5457559 B, in low power, the power transmission direction is determined incorrectly, and the duty factor of each switching device is increased or decreased in the wrong direction; there was a possibility that the voltage of the charge and discharge capacitor deviates from the target voltage. Consequently, since there is a possibility that excess voltage is applied to the first to the fourth switching devices, it is necessary to use the high breakdown voltage device for the first to the fourth switching devices; as a result, there has been a problem that cost and volume of the DC/DC converter increase. 
     Thus, it is desirable to provide a DC/DC converter which does not need to switch the change direction of a control value depending on the power transmission direction between low voltage side and high voltage side and can control the voltage of the charge and discharge capacitor. 
     A DC/DC converter according to the present invention includes: 
     a low-voltage side capacitor which holds low side voltage; a high-voltage side capacitor which holds high side voltage, and whose a negative electrode side terminal was connected to a negative electrode side terminal of the low-voltage side capacitor; a first semiconductor circuit whose a first end was connected to the negative electrode side terminal of the low-voltage side capacitor; a second semiconductor circuit whose a first end was connected to a second end of the first semiconductor circuit, and whose a second end was connected to a positive electrode side terminal of the low-voltage side capacitor via a reactor; a third semiconductor circuit whose a first end was connected to the second end of the second semiconductor circuit; a fourth semiconductor circuit whose a first end was connected to a second end of the third semiconductor circuit, and whose a second end was connected to a positive electrode side terminal of the high-voltage side capacitor; a charge and discharge capacitor whose a first end was connected to an intermediate connection point between the first semiconductor circuit and the second semiconductor circuit, and whose a second end was connected to an intermediate connection point between the third semiconductor circuit and the fourth semiconductor circuit; and a controller that controls each of the semiconductor circuits, 
     wherein the DC/DC converter is capable of operation of one or both of 
     a step-up operation which converts an inputted voltage of the low-voltage side capacitor into a stepped up voltage and outputs to the high-voltage side capacitor by an on-off switching function of the switching element of the first and second semiconductor circuits, by having a function of a switching element in each of the first and second semiconductor circuits and having a function of a diode element in each of the third and fourth semiconductor circuits, and 
     a step-down operation which converts an inputted voltage of the high-voltage side capacitor into a stepped down voltage and outputs to the low-voltage side capacitor by an on-off switching function of the switching element of the third and fourth semiconductor circuits, by having a function of a switching element in each of the third and fourth semiconductor circuits and having a function of a diode element in each of the first and second semiconductor circuits, 
     wherein the controller controls an ON duty ratio and a phase of ON period in each of the semiconductor circuits of one or both of the first and second semiconductor circuits which have the on-off switching function, and the third and fourth semiconductor circuits which have the on-off switching function, and 
     wherein the controller controls a voltage of the charge and discharge capacitor, by performing 
     a Δduty control which performs one or both of a first ON duty ratio difference change which changes an ON duty ratio difference between the ON duty ratio of the first semiconductor circuit and the ON duty ratio of the second semiconductor circuit, and a second ON duty ratio difference change which changes an ON duty ratio difference between the ON duty ratio of the third semiconductor circuit and the ON duty ratio of the fourth semiconductor circuit, and 
     a phase shift control which performs one or both of a first phase difference change which changes a phase difference between the phase of ON period of the first semiconductor circuit and the phase of ON period of the second semiconductor circuit, and a second phase difference change which changes a phase difference between the phase of ON period of the third semiconductor circuit and the phase of ON period of the fourth semiconductor circuit. 
     According to the DC/DC converter of the present invention, the voltage of the charge and discharge capacitor is controlled by execution of the phase shift control which changes the phase difference of the ON period of each semiconductor circuit. In the phase shift control, it is possible to control the voltage of the charge and discharge capacitor without the need for switching the change direction of the phase difference depending on the power transmission direction between low voltage side and high voltage side. Accordingly, even in low power with low power transmission amount, the voltage of the charge and discharge capacitor can be controlled with sufficient accuracy. The voltage of the charge and discharge capacitor is controlled by execution of the Δduty control which changes the ON duty ratio difference of each semiconductor circuit. Accordingly, by combining the phase shift control and the Δduty control appropriately, the controllability of the voltage of the charge and discharge capacitor can be improved. Therefore, the breakdown voltage performance of the switching devices can be reduced and the cost and size of the DC/DC converter can be reduced. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a configuration diagram of a DC/DC converter according to Embodiment 1 of the present invention; 
         FIG. 2  is a circuit diagram showing a configuration of a controller according to Embodiment 1 of the present invention; 
         FIG. 3  is an explanation drawing showing an operation mode  1  of a DC/DC converter according to Embodiment 1 of the present invention; 
         FIG. 4  is an explanation drawing showing an operation mode  2  of a DC/DC converter according to Embodiment 1 of the present invention; 
         FIG. 5  is an explanation drawing showing an operation mode  3  of a DC/DC converter according to Embodiment 1 of the present invention; 
         FIG. 6  is an explanation drawing showing an operation mode  4  of a DC/DC converter according to Embodiment 1 of the present invention; 
         FIG. 7  is an explanation drawing of a DC/DC converter in the case where a step-up ratio is less than twice according to Embodiment 1 of the present invention; 
         FIG. 8  is an explanation drawing of a DC/DC converter in the case where a step-up ratio is greater than or equal to twice according to Embodiment 1 of the present invention; 
         FIG. 9  is an explanation drawing of a DC/DC converter in the case where a step-down ratio is less than twice according to Embodiment 1 of the present invention; 
         FIG. 10  is an explanation drawing of a DC/DC converter in the case where a step-down ratio is greater than or equal to twice according to Embodiment 1 of the present invention; 
         FIG. 11  is a related figure showing a process of a current limiting unit according to Embodiment 1 of the present invention; 
         FIG. 12  is an explanation drawing showing an execution region of a second calculation unit and a third calculation unit, and a limiting value of a limiter according to Embodiment 1 of the present invention; 
         FIG. 13  is a circuit diagram showing a configuration of a controller according to Embodiment 2 of the present invention; 
         FIG. 14  is an explanation drawing showing an execution region of a second calculation unit and a third calculation unit, and a limiting value of a limiter according to Embodiment 2 of the present invention; 
         FIG. 15  is a circuit diagram showing a configuration of a controller according to Embodiment 3 of the present invention; 
         FIG. 16  is a figure explaining setting of a distribution ratio in accordance with reactor current according to Embodiment 3 of the present invention; 
         FIG. 17  is a figure explaining setting of a distribution ratio in accordance with reactor current according to Embodiment 3 of the present invention; 
         FIG. 18  is a figure explaining setting of a distribution ratio in accordance with reactor current according to Embodiment 3 of the present invention; 
         FIG. 19  is a flow chart showing a processing of a distribution calculating unit according to Embodiment 4 of the present invention; and 
         FIG. 20  is a block diagram of a controller according to Embodiment 1 of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
     Embodiment 1 
     A DC/DC converter  1  according to Embodiment 1 will be explained with reference to drawings.  FIG. 1  is a configuration diagram showing a configuration of the DC/DC converter  1 ;  FIG. 2  is a circuit diagram (a block diagram) showing a configuration of a controller  109  of  FIG. 1 ;  FIG. 3  to  FIG. 6  are explanation drawings showing operation modes of the DC/DC converter  1  of  FIG. 1 .  FIG. 7  to  FIG. 10  are explanation drawings of operation of the DC/DC converter  1  of  FIG. 1 .  FIG. 11  is an explanation drawing of operation of a current limiting unit  25   a  of the controller  109  of  FIG. 2 .  FIG. 12  is an explanation drawing of operating range of the controller  109  of  FIG. 2  and operation of a limiter. 
     1. Schematic Configuration of DC/DC Converter  1   
     As shown in  FIG. 1 , the DC/DC converter  1  is provided with four terminals  1   a ,  1   b ,  1   c ,  1   d  as a terminal group. The DC/DC converter  1  steps up an input voltage V 1 , as a low side voltage of a direct current inputted between an input side positive electrode terminal  1   a  (VL) and an input side negative electrode terminal  1   b  (Vcom), to a voltage greater than or equal to the input voltage V 1 , and outputs an output voltage V 2 , as a high side voltage after stepping up, to a part between an output side positive electrode terminal  1   c  (VH) and an output side negative electrode terminal  1   d . In the present embodiment, a battery  2  is connected between the input side positive electrode terminal  1   a  and the input side negative electrode terminal  1   b , and an electric motor  3  is connected between the output side positive electrode terminal  1   c  and the output side negative electrode terminal  1   d . The input side negative electrode terminal  1   b  and the output side negative electrode terminal  1   d  are connected to each other by a wire. 
     The DC/DC converter  1  is provided with an input side smoothing capacitor  11  as a low voltage side capacitor, a reactor  12 , a DC voltage converter  101  as a series circuit of semiconductor circuits, a first voltage sensor  103 , a second voltage sensor  104 , a current sensor  105  as a reactor current detection unit, an output side smoothing capacitor  108  as a high voltage side capacitor, and a controller  109 . 
     A first terminal of the input side smoothing capacitor  11  is connected to the input side positive electrode terminal  1   a , and a second terminal is connected to the input side negative electrode terminal  1   b ; the input side smoothing capacitor  11  smooths and holds the input voltage V 1 . A first terminal of the output side smoothing capacitor  108  is connected to the output side positive electrode terminal  1   c , and a second terminal is connected to the output side negative electrode terminal  1   d ; the output side smoothing capacitor  108  smooths and holds the output voltage V 2 . A first end of the reactor  12  is connected to the positive electrode side terminal of the input side smoothing capacitor  11  and the input side positive electrode terminal  1   a , and second end is connected to the DC voltage converter  101 ; the reactor  12  is used for energy storage. 
     The DC voltage converter  101  is provided with a first to fourth semiconductor circuits which are serially connected, and a charge and discharge capacitor  101   a . The DC voltage converter  101  is capable of a step-up operation which steps up the input voltage V 1  to the output voltage V 2 , and a step-down operation which steps down the output voltage V 2  to the input voltage V 1 . In the present embodiment, as a first semiconductor circuit, a first switching device S 1 , and a first diode D 1  which is connected in inverse parallel with the first switching device S 1  are provided; as a second semiconductor circuit, a second switching device S 2 , and a second diode D 2  which is connected in inverse parallel with the second switching device S 2  are provided; as a third semiconductor circuit, a third switching device S 3 , and a third diode D 3  which is connected in inverse parallel with the third switching device S 3  are provided; and as a fourth semiconductor circuit, a fourth switching device S 4 , and a fourth diode D 4  which is connected in inverse parallel with the fourth switching device S 4  are provided. In this way, all of the first to the fourth semiconductor circuits have a switching function, and a function of a diode element. For each switching device S 1  to S 4 , for example, IGBT (Insulated Gate Bipolar Transistor) is used; when each gate signal G 1  to G 4  inputted into each switching device is High, each switching device S 1  to S 4  is turned on (closed circuit state), and when each gate signal G 1  to G 4  is low, each switching device S 1  to S 4  is turned off (open circuit state). 
     The fourth switching device S 4 , the third switching device S 3 , the second switching device S 2 , and the first switching device S 1  are serially connected in this order from the positive electrode side to the negative electrode side. An emitter terminal of the first switching device S 1  is connected to the negative electrode terminal of the input side smoothing capacitor  11  and the input side negative electrode terminal  1   b . A collector terminal of the fourth switching device S 4  is connected to the positive electrode terminal of the output side smoothing capacitor  108  and the output side positive electrode terminal  1   c . A connection point of a collector terminal of the second switching device S 2  and an emitter terminal of the third switching device S 3  is connected to the positive electrode terminal of the input side smoothing capacitor  11  and the input side positive electrode terminal  1   a  via the reactor  12 . A first terminal of the charge and discharge capacitor  101   a  is connected to a connection point of a collector terminal of the first switching device S 1  and an emitter terminal of the second switching device S 2 ; a second terminal is connected to a connection point of a collector terminal of the third switching device S 3  and an emitter terminal of the fourth switching device S 4 . 
     A first voltage sensor  103  detects a voltage between terminals of the output side smoothing capacitor  108  (the output voltage V 2  as the high side voltage). A second voltage sensor  104  detects a voltage of the charge and discharge capacitor  101   a  (a charge and discharge capacitor voltage V 0 ). A current sensor  105  detects a reactor current IL which flows through the reactor  12 . 
     2. The Configuration of the Controller  109   
     The controller  109  generates the gate signals G 1  to G 4  which perform an on/off control (switching operation) of each of the four switching devices S 1  to S 4  by PWM (Pulse Width Modulation) control, and controls an ON duty ratio and a phase of an ON period of each of the four switching devices S 1  to S 4 . The ON duty ratio is a ratio of the ON period to a switching period Tsw (=ON period/switching period Tsw). 
     The controller  109  is provided with processing circuits which perform the on/off control of each switching device S 1  to S 4 . The processing circuits of the controller  109  may be configured by analog electronic circuits, such as a comparator, an operational amplifier, and a differential amplifying circuit; may be configured by digital electronic circuits, such as a computing processing unit  90 , a storage apparatus  91  and input/output circuits  92 ,  93 ; and may be configured by both of analog electronic circuits and digital electronic circuits. 
     As shown in  FIG. 20 , the controller  109  may be provided with CPU (Central Processing Unit), DSP (Digital Signal Processor), ASIC (Application Specific Integrated Circuit), FPGA (Field Programmable Gate Array), various kinds of logical circuits, various kinds of signal processing circuits and the like, as the computing processing unit  90 . As the computing processing unit  90 , a plurality of the same type ones or the different type ones may be provided, and each processing may be shared and executed. As the storage apparatus  91 , RAM (Random Access Memory), ROM (Read Only Memory) and the like are used. The input/output circuits are provided with an input circuit  92 , such as an A/D converter, which inputs output signals of various kinds of sensors or switches such as current sensor and voltage sensor, into the computing processing unit  90 , and an output circuit  93 , such as a driving circuit, which outputs control signals to the electric loads, such as switching devices, from the computing processing unit  90 . The computing processing unit  90 , such as CPU, performs each processing by running software items (programs) stored in the storage apparatus  91  such as ROM, and collaborating with other hardware devices in the controller  109 , such as the storage apparatus  91 , the input/output circuits  92 ,  93 . 
     The controller  109  controls a voltage V 0  of the charge and discharge capacitor by performing a Δduty control and a phase shift control. The Δduty control is a control which performs one or both (in this example, both) of a first ON duty ratio difference change which changes an ON duty ratio difference between an ON duty ratio DT 1  of the first switching device S 1  and an ON duty ratio DT 2  of the second switching devices S 2 , and a second ON duty ratio difference change which changes an ON duty ratio difference between an ON duty ratio DT 3  of the third switching device S 3  and an ON duty ratio DT 4  of the fourth switching device S 4 . The phase shift control is a control which performs one or both (in this example, both) of a first phase difference change which changes a phase difference between a phase of an ON period of the first switching device S 1  and a phase of an ON period of the second switching device S 2 , and a second phase difference change which changes a phase difference between a phase of an ON period of the third switching device S 3  and a phase of the ON period of the fourth switching device S 4 . 
     In the present embodiment, in the Δduty control, the controller  109  changes the ON duty ratio difference so that a detection value of the charge and discharge capacitor voltage V 0  approaches a charge and discharge capacitor voltage target value V 0 ref. In the phase shift control, the controller  109  changes the phase difference so that the detection value of the charge and discharge capacitor voltage V 0  approaches the charge and discharge capacitor voltage target value V 0 ref. 
     The controller  109  controls the output voltage V 2  by performing a basis duty control. The basis duty control is a control which performs both of a first ON duty ratio change and a second ON duty ratio change so that a detection value of the output voltage V 2  approaches an output voltage target value V 2 ref. The first ON duty ratio change changes a basis ON duty ratio which is an average value between the ON duty ratio DT 1  of the first switching device S 1  and the ON duty ratio DT 2  of the second switching device S 2 , in the state of the same ON duty ratio difference and the same phase difference. The second ON duty ratio change changes a basis ON duty ratio which is an average value between the ON duty ratio DT 3  of the third switching device S 3  and the ON duty ratio DT 4  of the fourth switching device S 4 , in the state of the same ON duty ratio difference and the same phase difference. 
       FIG. 2  is a circuit diagram (a block diagram) showing a detailed configuration of the controller  109  according to the present embodiment. In the present embodiment, the controller  109  is provided with a first calculation unit  24 , a second calculation unit  25 , a third calculation unit  26 , and a switching control unit  30 , in order to perform the basis duty control, the Δduty control, and the phase shift control. 
     &lt;First Calculation Unit  24 &gt; 
     The first calculation unit  24  calculates a first calculation value Duty which changes the basis ON duty ratio. In the present embodiment, the first calculation unit  24  calculates the first calculation value Duty based on a difference voltage V 2 err (hereinafter, referred to an output difference voltage V 2 err) between the output voltage target value V 2 ref as a command value of the high side voltage, and the detection value of the output voltage V 2  as the high side voltage. 
     In the present embodiment, the first calculation unit  24  is provided with a subtractor  21  that calculates the output difference voltage V 2 err by subtracting the detection value of the output voltage V 2  from the output voltage target value V 2 ref, and a first controller  24   a  that calculates the first calculation value Duty based on the output difference voltage V 2 err. 
     The first controller  24   a  calculates the first calculation value Duty by performing a feedback control, such as P control, PI control, and PID control, to the output difference voltage V 2 err. The first controller  24   a  calculates the first calculation value Duty within a range of 0 to 1. Accordingly, the first controller  24   a  changes the first calculation value Duty so that the detection value of the output voltage V 2  approaches the output voltage target value V 2 ref. 
     &lt;Second Calculation Unit  25 &gt; 
     The second calculation unit  25  calculates a second calculation value Δduty which changes the ON duty ratio difference in the Δduty control, based on a difference voltage V 0 err (hereinafter, referred to a charge and discharge capacitor difference voltage V 0 err) between a charge and discharge capacitor voltage target value V 0 ref as a voltage command value of the charge and discharge capacitor, and the charge and discharge capacitor voltage V 0 . 
     In the present embodiment, the second calculation unit  25  is provided with a subtractor  23  that calculates the charge and discharge capacitor difference voltage V 0 err by subtracting the charge and discharge capacitor voltage V 0  from the charge and discharge capacitor voltage target value V 0 ref, and a second controller  25   c  that calculates the second calculation value Δduty based on the charge and discharge capacitor difference voltage V 0 err. The second controller  25   c  calculates the second calculation value Δduty by performing a feedback control, such as P control, PI control, and PID control, to the charge and discharge capacitor difference voltage V 0 err. Accordingly, the second controller  25   c  changes the second calculation value Δduty so that the charge and discharge capacitor voltage V 0  approaches the charge and discharge capacitor voltage target value V 0 ref. The ON duty ratio difference becomes 0 in a basis ON duty ratio difference from which the second calculation value Δduty becomes 0. 
     The second calculation unit  25  is provided with a multiplier  22  that calculates the charge and discharge capacitor voltage target value V 0 ref based on the detection value of the output voltage V 2 . In the present embodiment, in order to minimize the ripple current of the reactor  12 , the multiplier  22  sets a value obtained by multiplying 0.5 to the detection value of the output voltage V 2 , as the charge and discharge capacitor voltage target value V 0 ref. 
     In the present embodiment, the second calculation unit  25  changes the second calculation value Δduty in accordance with a reactor current IL detected by the current sensor  105 . For that, the second calculation unit  25  is provided with a current limiting unit  25   a  and a difference voltage correction unit  25   b . As described in detail later, the current limiting unit  25   a  calculates a value obtained by performing a limitation processing to the reactor current IL, as a reactor current IL* after limitation. Then, the difference voltage correction unit  25   b  outputs a value obtained by correcting the charge and discharge capacitor difference voltage V 0 err based on the reactor current IL* after limitation, as a difference voltage V 0 err* after current correction. Then, the second controller  25   c  calculates the second calculation value Δduty based on the difference voltage V 0 err* after current correction. 
     &lt;Third Calculation Unit  26 &gt; 
     The third calculation unit  26  calculates a third calculation value θ which changes the phase difference in the phase shift control based on the charge and discharge capacitor difference voltage V 0 err between the charge and discharge capacitor voltage target value V 0 ref and the charge and discharge capacitor voltage V 0 . 
     In the present embodiment, the third calculation unit  26  is provided with a third controller  26   a  that calculates the third calculation value θ based on the charge and discharge capacitor difference voltage V 0 err. The third controller  26   a  calculates the third calculation value θ by performing a feedback control, such as P control, PI control, and PID control, to the charge and discharge capacitor difference voltage V 0 err. Accordingly, the third controller  26   a  changes the third calculation value θ so that the charge and discharge capacitor voltage V 0  approaches the charge and discharge capacitor voltage target value V 0 ref. The phase difference becomes 180 degrees in a basis phase difference from which the third calculation value θ becomes 0. 
     In the present embodiment, the third calculation unit  26  calculates a value obtained by performing processing which reverses a positive or negative sign alternately at half period of a switching period Tsw described below to the third calculation value θ, as the final third calculation value ±θ. For that, the third calculation unit  26  is provided with a rectangular wave generator  26   c  that generates a rectangular wave which oscillates between +1 and −1 at the switching period Tsw, and a rectangular wave multiplier  26   b  that calculates the final third calculation value ±θ by multiplying the rectangular wave of ±1 to the third calculation value θ. As shown in  FIG. 7  and the like, the rectangular wave generator  26   c  generates the rectangular wave which oscillates synchronizing with a first triangular wave and a second triangular wave. Specifically, the rectangular wave generator  26   c  outputs+1 during a half period when the first triangular wave is decreasing and the second triangular wave is increasing, and outputs −1 during a half period when the first triangular wave is increasing and the second triangular wave is decreasing. 
     As shown in  FIG. 7  and the like, since the first triangular wave is decreasing during the third calculation value θ is a value of plus and the third calculation value becomes +θ, the first gate signal G 1  shifts to the phase delay side; since the first triangular wave is increasing during the third calculation value is −θ, the first gate signal G 1  shifts to the phase delay side. Accordingly, in the case where the third calculation value θ is a value of plus, the first gate signal G 1  shifts to the phase delay side by a time proportional to a magnitude of the third calculation value θ. On the other hand, since the second triangular wave is increasing during the third calculation value θ is a value of plus and third calculation value becomes +θ, the second gate signal G 2  shifts to the phase advance side; since the second triangular wave is decreasing during the third calculation value becomes −θ, the second gate signal G 2  shifts to the phase advance side. Accordingly, in the case where the third calculation value θ is a value of plus, the second gate signal G 2  shifts to the phase advance side by a time proportional to a magnitude of the third calculation value θ. Therefore, in proportion to the third calculation value θ, the phase of the ON period of the first switching device S 1  shifts in the delay direction, and the phase of the ON period of the second switching device S 2  shifts in the advance direction. In the same manner, in proportion to the third calculation value θ, the phase of the ON period of the fourth switching device S 4  shifts in the delay direction, and the phase of the ON period of the third switching device S 3  shifts in the advance direction. In the case where the third calculation value θ is a value of minus, the advance direction and the delay direction are reversed. 
     &lt;Switching Control Unit  30 &gt; 
     The switching control unit  30  controls the ON duty ratio and the phase of the ON period of each of the switching devices S 1  to S 4  based on the first calculation value Duty, the second calculation value Δduty, and the third calculation value ±θ. 
     In the present embodiment, the switching control unit  30  calculates a first control value SD 1  which added the second calculation value Δduty and the third calculation value ±θ to the first calculation value Duty, and calculates a second control value SD 2  which subtracted the second calculation value Δduty from the first calculation value Duty and added the third calculation value ±θ to the first calculation value Duty. The first control value SD 1  before addition of the third calculation value ±θ is proportional to the ON duty ratio of the first switching device S 1  and the OFF duty ratio of the fourth switching device S 4 ; the second control value SD 2  before addition of the third calculation value ±θ is proportional to the ON duty ratio of the second switching device S 2  and the OFF duty ratio of the third switching device S 3 . 
     The switching control unit  30  is provided with a Duty correction block  28  and a phase shift correction block  29 . The Duty correction block  28  is provided with an adder  28   a  that adds the second calculation value Δduty to the first calculation value Duty for calculation of the first control value SD 1 , and a subtractor  28   b  that subtracts the second calculation value Δduty from the first calculation value Duty for calculation of the second control value SD 2 . The phase shift correction block  29  is provided with an adder  29   a  that calculates the first control value SD 1  by adding the third calculation value ±θ to an output of the adder  28   a , and an adder  29   b  that calculates the second control value SD 2  by adding the third calculation value ±θ to an output of the subtractor  28   b.    
     The switching control unit  30  calculates the first triangular wave which oscillates between a minimum value (in this example, 0) and a maximum values (in this example, 1) at the switching period Tsw, and the second triangular wave whose a phase is inverted 180 degrees to the first triangular wave. Since the phase of the first triangular wave and the phase of the second triangular wave are inverted 180 degrees, the ripple current of the reactor  12  can be minimized. The phase of the ON period of each switching device can be shifted to the opposite direction by the simple processing which multiplies the rectangular wave which oscillates ±1 to the third calculation value θ. 
     Then, the switching control unit  30  controls a switching operation of one or both (in this example, both) of the first switching device S 1  and the fourth switching device S 4  based on the comparison result between the first control value SD 1  and the first triangular wave, and controls a switching operation of one or both (in this example, both) of the second switching device S 2  and the third switching device S 3  based on the comparison result between the second control value SD 2  and the second triangular wave. 
     For that, the switching control unit  30  is provided with a first triangular wave generator  30   e  that generates the first triangular wave, and a second triangular wave generator  30   f  that generates the second triangular wave. The switching control unit  30  is provided with a first comparator  30   a  that compares the first control value SD 1  with the first triangular wave to generate the first gate signal G 1 , and a second comparator  30   c  that compares the second control value SD 2  with the second triangular wave to generate the second gate signal G 2 . The first comparator  30   a  sets the first gate signal G 1  to Low in the case where the first triangular wave is larger than the first control value SD 1 , and sets the first gate signal G 1  to High in the case where the first triangular wave is less than the first control value SD 1 . Similarly, the second comparator  30   c  sets the second gate signal G 2  to Low in the case where the second triangular wave is larger than the second control value SD 2 , and sets the second gate signal G 2  to High in the case where the second triangular wave is less than the second control value SD 2 . 
     The switching control unit  30  is provided with a first inverting circuit  30   b  that generates the fourth gate signal G 4  which inverted High and Low of the first gate signal G 1 , and a second inverting circuit  30   d  that generates the third gate signal G 3  which inverted High and Low of the second gate signal G 2 . The first gate signal G 1  performs the switching operation of the first switching device S 1 ; the second gate signal G 2  performs the switching operation of the second switching device S 2 ; the third gate signal G 3  performs the switching operation of the third switching device S 3 ; and the fourth gate signal G 4  performs the switching operation of the fourth switching device S 4 . 
     &lt;Limiter  27 &gt; 
     The controller  109  is provided with a limiter  27  that performs a lower limitation of the first control value SD 1  by the minimum value (in this example, 0) and performs an upper limitation of the first control value SD 1  by the maximum value (in this example, 1), and performs a lower limitation of the second control value SD 2  by the minimum value and performs an upper limitation of the second control value SD 2  by the maximum value. In the present embodiment, as described in detail later, the limiter  27  applies a limitation to the third calculation value θ which the third controller  26   a  calculated. Here, θ* shows the third calculation value before limitation by the limiter  27 , and θ shows the third calculation value after limitation. 
     &lt;Explanation of Operation of DC/DC Converter  1 &gt; 
     Next, an operation of the DC/DC converter  1  in a steady state will be explained. The steady state means a state when the on/off control of the switching devices S 1  to S 4  is performed and the output voltage V 2  is stable. As operating states of the DC/DC converter  1 , there are two states of a state (a power running operation, a step-up operation) of driving the electric motor  3  by stepping up voltage and supplying electric power from the battery  2  to the electric motor  3 , and a state (a regenerative operation, a step-down operation) of stepping down electric power which the electric motor  3  generated and supplying to the battery  2 . 
     As shown in  FIG. 3  to  FIG. 6 , as operation modes which are switching patterns of the first to fourth switching devices S 1  to S 4 , there are four modes of a mode  1  to a mode  4 . In the mode  1 , as shown in  FIG. 3 , the first switching device S 1  and the third switching device S 3  are set to ON, and the second switching device S 2  and the fourth switching device S 4  are set to OFF. At the time of the step-up operation (the power running operation), as a current route is shown in  FIG. 3  by a dotted line, current flows through the first switching device S 1  and the third diode D 3 , and energy is stored in the charge and discharge capacitor  101   a . At the time of the step-down operation (the regenerative operation), as a current route is shown in  FIG. 3  by a dashed dotted line, current flows through the first diode D 1  and the third switching device S 3 , and the energy of the charge and discharge capacitor  101   a  is emitted. 
     In the mode  2 , as shown in  FIG. 4 , the first switching device S 1  and the third switching device S 3  are set to OFF, and the second switching device S 2  and the fourth switching device S 4  are set to ON. At the time of the step-up operation (the power running operation), as a current route is shown in  FIG. 4  by a dotted line, current flows through the second switching device S 2  and the fourth diode D 4 , and the energy of the charge and discharge capacitor  101   a  is emitted. At the time of the step-down operation (the regenerative operation), as a current route is shown in  FIG. 4  by a dashed dotted line, current flows through the second diode D 2  and the fourth switching device S 4 , and energy is stored in the charge and discharge capacitor  101   a.    
     In the mode  3 , as shown in  FIG. 5 , the first switching device S 1  and the second switching device S 2  are set to OFF, and the third switching device S 3  and the fourth switching device S 4  are set to ON. At the time of the step-up operation (the power running operation), as a current route is shown in  FIG. 5  by a dotted line, current flows through the third diode D 3  and the fourth diode D 4 , and the energy of the reactor  12  is emitted. At the time of the step-down operation (the regenerative operation), as a current route is shown in  FIG. 5  by a dashed dotted line, current flows through the third switching device S 3  and the fourth switching device S 4 , and energy is stored in the reactor  12 . 
     In the mode  4 , as shown in  FIG. 6 , the first switching device S 1  and the second switching device S 2  are set to ON, and the third switching device S 3  and the fourth switching device S 4  are set to OFF. At the time of the step-up operation (the power running operation), as a current route is shown in  FIG. 6  by a dotted line, current flows through the first switching device S 1  and the second switching device S 2 , and energy is stored in the reactor  12 . At the time of the step-down operation (the regenerative operation), as a current route is shown in  FIG. 6  by a dashed dotted line, current flows through the first diode D 1  and the second diode D 2 , and the energy of the reactor  12  is emitted. 
     By adjusting time ratio of these operation modes suitably, the input voltage V 1 , which is inputted to between the input side positive electrode terminal  1   a  and the input side negative electrode terminal  1   b , can be stepped up to the output voltage V 2  to output to between the output side positive electrode terminal  1   c  and the output side negative electrode terminal  1   d , and the output voltage V 2 , which is inputted to between the output side positive electrode terminal  1   c  and the output side negative electrode terminal  1   d , can be stepped down to the input voltage V 1  to output to between the input side positive electrode terminal  1   a  and the input side negative electrode terminal  1   b.    
     In the mode  1  to the mode  4 , at the time of the step-up operation, since current flows through the first switching device S 1  and the second switching device S 2  which were set to ON, the first and the second semiconductor circuits exhibit the function of the switching device; and since current flows through the third diode D 3  and the fourth diode D 4 , the third and the fourth semiconductor circuits exhibit the function of the diode element. At the time of the step-down operation, since current flows through the first diode D 1  and the second diode D 2 , the first and the second semiconductor circuits exhibit the function of the diode element; and since current flows through the third switching device S 3  and the fourth switching device S 4  which were set to ON, the third and the fourth semiconductor circuits exhibit the function of the switching device. 
     The DC/DC converter  1  differs in operation of the steady state between the case where a step-up ratio N and a step-down ratio N of the output voltage V 2  to the input voltage V 1  are less than twice, and the case where the step-up ratio N and the step-down ratio N are greater than or equal to twice. Here, the step-up ratio N and the step-down ratio N=the output voltage V 2 /the input voltage V 1 . 
     &lt;In the Case where the Step-Up Ratio is Less than Twice&gt; 
     First, the step-up operation (the power running operation) in the case where the step-up ratio N(=V 2 /V 1 ) is less than twice will be explained.  FIG. 7  shows the first triangular wave and the second triangular wave, the first control value SD 1  and the second control value SD 2 , the gate signals G 1  to G 4  of each switching device S 1  to S 4 , the operation modes, the reactor current IL, the current IC 0  of the charge and discharge capacitor  101   a  (hereinafter, referred to as a charge and discharge capacitor current IC 0 ), in the case where the step-up ratio N is less than twice. 
     In the example shown in  FIG. 7 , limitation is not performed by the limiter  27 , so it becomes θ=θ*; the charge and discharge capacitor voltage V 0  is controlled so as to become a 0.5 times value of the output voltage V 2  in the steady state; a size relation between the input voltage V 1 , the output voltage V 2 , and the charge and discharge capacitor voltage V 0  is as follows.
 
 V 2&gt; V 1&gt; V 0
 
     In the state (the mode  1  (dotted line in  FIG. 3 )) where the gate signals G 1 , G 3  of the first and the third switching device S 1 , S 3  are High, and the gate signals G 2 , G 4  of the second and the fourth switching device S 2 , S 4  are Low, according to the following route, energy shifts to the reactor  12  and the charge and discharge capacitor  101   a  from the input side smoothing capacitor  11 . 
     The input side smoothing capacitor  11 →the reactor  12 →the third diode D 3 →the charge and discharge capacitor  101   a →the first switching device S 1   
     Next, in the state (the mode  3  (dotted line in  FIG. 5 )) where the gate signals G 1 , G 2  of the first and the second switching devices S 1 , S 2  are Low, and the gate signals G 3 , G 4  of the third and the fourth switching devices S 3 , S 4  are High, according to the following route, energy stored in the reactor  12  shifts to the input side smoothing capacitor  11  and the output side smoothing capacitor  108 . 
     The input side smoothing capacitor  11 →the reactor  12 →the third diode D 3 →the fourth diode D 4 →the output side smoothing capacitor  108   
     Next, in the state (the mode  2  (dotted line in  FIG. 4 )) where the gate signals G 1 , G 3  of the first and the third switching devices S 1 , S 3  are Low, and the gate signals G 2 , G 4  of the second and the fourth switching devices S 2 , S 4  are High, according to the following route, energy stored in the charge and discharge capacitor  101   a  shifts to the input side smoothing capacitor  11  and the output side smoothing capacitor  108 , and energy is stored in the reactor  12 . 
     The input side smoothing capacitor  11 →the reactor  12 →the second switching device S 2 →the charge and discharge capacitor  101   a →the fourth diode D 4 →the output side smoothing capacitor  108   
     Next, in the state (the mode  3  (dotted line in  FIG. 5 )) where the gate signals of the first and the second switching devices S 1 , S 2  are Low, and the gate signals of the third and the fourth switching devices S 3 , S 4  are High, according to the following route, energy stored in the reactor  12  shifts to the input side smoothing capacitor  11  and the output side smoothing capacitor  108 . 
     The input side smoothing capacitor  11 →the reactor  12 →the third diode D 3 →the fourth diode D 4 →the output side smoothing capacitor  108   
     By repetition of operation of a sequence of “the mode  1 —the mode  3 —the mode  2 —the mode  3 ”, the input voltage V 1  inputted to between the input side positive electrode terminal  1   a  and the input side negative electrode terminal  1   b  is stepped up to any voltage between 1 time and twice to output to between the output side positive electrode terminal  1   c  and the output side negative electrode terminal  1   d  as the output voltage V 2 ; accordingly, energy of the battery  2  is supplied to the electric motor  3 . 
     &lt;In the Case where the Step-Up Ratio is Greater than or Equal to Twice&gt; 
     Next, the step-up operation (the power running operation) in the case where the step-up ratio N(=V 2 /V 1 ) is greater than or equal to twice will be explained.  FIG. 8  shows the first triangular wave and the second triangular wave, the first control value SD 1 , the second control value SD 2 , the gate signals G 1  to G 4  of each switching device S 1  to S 4 , the operation modes, the reactor current IL, the charge and discharge capacitor current IC 0 , in the case where the step-up ratio N is greater than or equal to twice. 
     The charge and discharge capacitor voltage V 0  is controlled so as to become a 0.5 times value of the output voltage V 2  in the steady state; a size relation between the input voltage V 1 , the output voltage V 2 , and the charge and discharge capacitor voltage V 0  is as follows.
 
 V 2&gt; V 0&gt; V 1
 
     In the state (the mode  1  (dotted line in  FIG. 3 )) where the gate signals G 1 , G 3  of the first and the third switching device S 1 , S 3  are High, and the gate signals G 2 , G 4  of the second and the fourth switching device S 2 , S 4  are Low, according to the following route, energy stored in the reactor  12  shifts to the input side smoothing capacitor  11  and the charge and discharge capacitor  101   a.    
     The input side smoothing capacitor  11 →the reactor  12 →the third diode D 3 →the charge and discharge capacitor  101   a →the first switching device S 1   
     Next, in the state (the mode  4  (dotted line in  FIG. 6 )) where the gate signals G 1 , G 2  of the first and the second switching devices S 1 , S 2  are High, and the gate signal G 3 , G 4  of the third and fourth switching devices S 3 , S 4  are Low, according to the following route, energy shifts to the reactor  12  from the input side smoothing capacitor  11 . 
     The input side smoothing capacitor  11 →the reactor  12 →the second switching device S 2 →the first switching device S 1   
     Next, in the state (the mode  2  (dotted line in  FIG. 4 )) where the gate signals G 1 , G 3  of the first and the third switching device S 1 , S 3  are Low, and the gate signals G 2 , G 4  of the second and the fourth switching device S 2  and S 4  are High, according to the following route, energy stored in the reactor  12  and the charge and discharge capacitor  101   a  shifts to the input side smoothing capacitor  11  and the output side smoothing capacitor  108 . 
     The input side smoothing capacitor  11 →the reactor  12 →the second switching device S 2 →the charge and discharge capacitor  101   a →the fourth diode D 4 →the output side smoothing capacitor  108   
     Next, in the state (the mode  4  (dotted line in  FIG. 6 )) where the gate signals G 1 , G 2  of the first and the second switching devices S 1 , S 2  are High, and the gate signals G 3 , G 4  of the third and the fourth switching devices S 3 , S 4  are Low, according to the following route, energy shifts to the reactor  12  from the input side smoothing capacitor  11 . 
     The input side smoothing capacitor  11 →the reactor  12 →the second switching device S 2 →the first switching device S 1   
     By repetition of operation of a sequence of “the mode  1 —the mode  4 —the mode  2 —the mode  4 ”, the input voltage V 1  inputted to between the input side positive electrode terminal  1   a  and the input side negative electrode terminal  1   b  is stepped up to any voltage, which is greater than or equal to twice, to output to between the output side positive electrode terminal  1   c  and the output side negative electrode terminal  1   d  as the output voltage V 2 ; accordingly, energy of the battery  2  is supplied to the electric motor  3 . 
     &lt;In the Case where the Step-Down Ratio is Less than Twice&gt; 
     Next, the step-down operation (the regenerative operation) in the case where the step-down ratio N(=V 2 /V 1 ) is less than twice will be explained.  FIG. 9  shows the first triangular wave and the second triangular wave, the first control value SD 1 , the second control value SD 2 , the gate signals G 1  to G 4  of each switching device S 1  to S 4 , the operation modes, the reactor current IL, the charge and discharge capacitor current IC 0 , in the case where the step-down ratio N is less than twice. 
     The charge and discharge capacitor voltage V 0  is controlled so as to become a 0.5 times value of the output voltage V 2  in the steady state; a size relation between the input voltage V 1 , the output voltage V 2 , and the charge and discharge capacitor voltage V 0  is as follows.
 
 V 2&gt; V 1&gt; V 0
 
     In the state (the mode  1  (dashed dotted line in  FIG. 3 )) where the gate signals G 1 , G 3  of the first and the third switching devices S 1 , S 3  are High, and the gate signals G 2 , G 4  of the second and the fourth switching devices S 2 , S 4  are Low, according to the following route, energy shifts to the smoothing capacitor  11  from the charge and discharge capacitor  101   a  and the reactor  12 . 
     The input side smoothing capacitor  11 ←the reactor  12 ←the third switching device S 3 ←the charge and discharge capacitor  101   a ←the first diode D 1   
     Next, in the state (the mode  3  (dashed dotted line in  FIG. 5 )) where the gate signals G 1 , G 2  of the first and the second switching devices S 1 , S 2  are Low, and the gate signal G 3 , G 4  of the third and the fourth switching devices S 3 , S 4  are High, according to the following route, energy shifts to the reactor  12  and the input side smoothing capacitor  11  from the output side smoothing capacitor  108 . 
     The input side smoothing capacitor  11 ←the reactor  12 ←the third switching device S 3 ←the fourth switching device S 4 ←the output side smoothing capacitor  108   
     Next, in the state (the mode  2  (dashed dotted line in  FIG. 4 )) where the gate signals G 1 , G 3  of the first and the third switching devices S 1 , S 3  are Low, and the gate signals G 2 , G 4  of the second and the fourth switching devices S 2 , S 4  are High, according to the following route, energy shifts to the charge and discharge capacitor  101   a  and the input side smoothing capacitor  11  from the output side smoothing capacitor  108  and the reactor  12 . 
     The input side smoothing capacitor  11 ←the reactor  12 ←the second diode D 2 ←the charge and discharge capacitor  101   a ←the fourth switching device S 4 ←the output side smoothing capacitor  108   
     Next, in the state (the mode  3  (dashed dotted line in  FIG. 5 )) where the gate signals G 1 , G 2  of the first and the second switching devices S 1 , S 2  are Low, and the gate signal G 3 , G 4  of the third and the fourth switching devices S 3 , S 4  are High, according to the following route, energy shifts to the reactor  12  and the input side smoothing capacitor  11  from the output side smoothing capacitor  108 . 
     The input side smoothing capacitor  11 ←the reactor  12 ←the third switching device S 3 ←the fourth switching device S 4 ←the output side smoothing capacitor  108   
     By repetition of operation of a sequence of “the mode  1 —the mode  3 —the mode  2 —the mode  3 ”, the output voltage V 2  between the output side positive electrode terminal  1   c  and the output side negative electrode terminal  1   d  is stepped down by any step-down ratio N(=V 2 /V 1 ) between 1 time and twice to output as the input voltage V 1  between the input side positive electrode terminal  1   a  and the input side negative electrode terminal  1   b ; accordingly, generated energy of the electric motor  3  is stored in the battery  2 . 
     &lt;In the Case where the Step-Down Ratio is Greater than or Equal to Twice&gt; 
     Next, the step-down operation (the regenerative operation) in the case where the step-down ratio N(=V 2 /V 1 ) is greater than or equal to twice will be explained.  FIG. 10  shows the first triangular wave and the second triangular wave, the first control value SD 1 , the second control value SD 2 , the gate signals G 1  to G 4  of each switching device S 1  to S 4 , the operation modes, the reactor current IL, the charge and discharge capacitor current IC 0 , in the case where the step-down ratio N is greater than or equal to twice. 
     The charge and discharge capacitor voltage V 0  is controlled so as to become a 0.5 times value of the output voltage V 2  in the steady state; a size relation between the input voltage V 1 , the output voltage V 2 , and the charge and discharge capacitor voltage V 0  is as follows.
 
 V 2&gt; V 0&gt; V 1
 
     In the state (the mode  1  (dashed dotted line in  FIG. 3 )) where the gate signals G 1 , G 3  of the first and the third switching devices S 1 , S 3  are High, and the gate signals G 2 , G 4  of the second and the fourth switching device S 2 , S 4  are Low, according to the following route, energy shifts to the reactor  12  and the input side smoothing capacitor  11  from the charge and discharge capacitor  101   a.    
     The input side smoothing capacitor  11 ←the reactor  12 ←the third switching device S 3 ←the charge and discharge capacitor  101   a ←the first diode D 1   
     Next, in the state (the mode  4  (dashed dotted line in  FIG. 6 )) where the gate signals G 1 , G 2  of the first and the second switching devices S 1 , S 2  are High, and the gate signals of the third and fourth switching devices S 3 , S 4  are Low, according to the following route, energy shifts to the input side smoothing capacitor  11  from the reactor  12 . 
     The input side smoothing capacitor  11 ←the reactor  12 ←the second diode D 2 ←the first diode D 1   
     Next, in the state (the mode  2  (dashed dotted line in  FIG. 4 )) where the gate signals G 1 , G 3  of the first and the third switching devices S 1 , S 3  are Low, and the gate signals of the second and the fourth switching devices S 2 , S 4  are High, according to the following route, energy shifts to the reactor  12 , the charge and discharge capacitor  101   a , and the input side smoothing capacitor  11  from the output side smoothing capacitor  108 . 
     The input side smoothing capacitor  11 ←the reactor  12 ←the second diode D 2 ←the charge and discharge capacitor  101   a ←the fourth switching device S 4 ←the output side smoothing capacitor  108   
     Next, in the state (the mode  4  (dashed dotted line in  FIG. 6 )) where the gate signals G 1 , G 2  of the first and the second switching devices S 1 , S 2  are High, and the gate signals G 3 , G 4  of the third and the fourth switching devices S 3 , S 4  and G 4  are Low, according to the following route, energy shifts to the input side smoothing capacitor  11  from the reactor  12 . 
     The input side smoothing capacitor  11 ←the reactor  12 ←the second diode D 2 ←the first diode D 1   
     By repetition of operation of a sequence of “the mode  1 —the mode  4 —the mode  2 —the mode  4 ”, the output voltage V 2  between the output side positive electrode terminal  1   c  and the output side negative electrode terminal  1   d  is stepped down by any step-down ratio N(=V 2 /V 1 ), which is greater than or equal to one, to output as the input voltage V 1  between the input side positive electrode terminal  1   a  and the input side negative electrode terminal  1   b ; accordingly, generated energy of the electric motor  3  is stored in the battery  2 . 
     &lt;A State Equation of the DC/DC Converter  1 &gt; 
     Supposing that the third calculation value θ is 0, in the present embodiment, the first ON duty ratio DT 1  of the first switching device S 1  becomes equal to the first control value SD 1 , the second ON duty ratio DT 2  of the second switching device S 2  becomes equal to the second control value SD 2 , the fourth ON duty ratio DT 4  of the fourth switching device S 4  becomes equal to a value obtained by subtracting the first control value SD 1  from one (=1−SD 1 ), and the third ON duty ratio DT 3  of the third switching device S 3  becomes equal to a value obtained by subtracting the second control value SD 2  from one (=1−SD 2 ). When a capacity of the output side smoothing capacitor  108  is set to C 2 , a capacity of the charge and discharge capacitor  101   a  is set to C 0 , an inductance value of the reactor  12  is set to L, a current which flows through the reactor  12  is set to IL, and the output current is set to Io, a state average equation of the DC/DC converter  1  can be expressed by an equation (1). 
     
       
         
           
             
               
                 
                   
                     
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     In a steady state, supposing that the left-hand side of the equation (1) is 0 and it is V 0 =0.5×V 2 , an equation (2) to an equation (4) are obtained. In a steady state, by making equal the first control value SD 1  and the second control value SD 2 , it is understood that the output voltage V 2  and the charge and discharge capacitor voltage V 0  are ideally converged to a constant value.
 
 V 2/ V 1=1/(1− DT 1)  (2)
 
 IL=Io /(1− DT 1)  (3)
 
 DT 1= DT 2  (4)
 
     In the present embodiment, as mentioned above, the controller  109  is provided with the first calculation unit  24 , and the first calculation unit  24  calculates the first calculation value Duty based on the output difference voltage V 2 err between the output voltage target value V 2 ref and the detection value of the output voltage V 2 . Then, as mentioned above, based on the first calculation value Duty, the switching control unit  30  calculates the first control value SD 1  and the second control value SD 2 , and changes the first ON duty ratio DT 1  of the first switching device S 1  and the second ON duty ratio DT 2  of the second switching device S 2 . According to this configuration, the first and the second ON duty ratio DT 1 , DT 2  can be changed so that the output voltage V 2  approaches the output voltage target value V 2 ref. 
     &lt;First Problem&gt; 
     However, in the actual DC/DC converter, there is a deviation from an ideal state, such as a loss owing to circuit resistance components, and an ON period error owing to variation in the signal delay of the gate signals. In particular, an influence on the charge and discharge capacitor voltage V 0  resulting from a difference between the first ON period of the first switching device S 1  and the second ON period of the second switching device S 2  at the time of the step-up operation, or a difference of the third ON period of the third switching device S 3  and the fourth ON period of the fourth switching device S 4  at the time of the step-down operation, is big. In the case where the first ON period is larger than the second ON period and the reactor current IL is positive (the power running operation), from the equation (1), the charge and discharge capacitor voltage V 0  increases gradually and finally becomes the same value as the output voltage V 2 . On the contrary, in the case where the first ON period is smaller than the second ON period and the reactor current IL is positive (the power running operation), from the equation (1), the charge and discharge capacitor voltage V 0  decreases gradually and finally becomes zero voltage. 
     If the charge and discharge capacitor voltage V 0  drops and becomes zero voltage; when the first switching device S 1  is ON state and the fourth switching device S 4  is OFF state, the output voltage V 2  is applied only to the fourth switching device S 4 ; when the first switching device S 1  is OFF state and the fourth switching device S 4  is ON state, the output voltage V 2  is applied only to the first switching device S 1 . On the contrary, if the charge and discharge capacitor voltage V 0  increases and becomes the output voltage V 2 , the output voltage V 2  is applied to either of the second switching device S 2  and the third switching device S 3 . In order to prevent overvoltage destruction of the switching devices, since it is necessary to set an element breakdown voltage of the switching devices to greater than or equal to the output voltage V 2 , it had become factors of excessive cost increase and efficiency deterioration. 
     To this problem, a first control method which controls the charge and discharge capacitor voltage V 0  will be explained. As seen from the equation (1), in the case where the reactor current IL is positive; if the second ON duty ratio DT 2  is made larger than the first ON duty ratio DT 1 , the charge and discharge capacitor voltage V 0  can be increased; if the second ON duty ratio DT 2  is made smaller than the first ON duty ratio DT 1 , the charge and discharge capacitor voltage V 0  can be decreased. On the other hand, In the case where the reactor current IL is negative; if the second ON duty ratio DT 2  is made larger than the first ON duty ratio DT 1 , the charge and discharge capacitor voltage V 0  can be decreased; if the second ON duty ratio DT 2  is made smaller than the first ON duty ratio DT 1 , the charge and discharge capacitor voltage V 0  can be increased. 
     Accordingly, in the present embodiment, as mentioned above, the controller  109  controls the charge and discharge capacitor voltage V 0  by performing the Δduty control. The Δduty control is the control which performs one or both (in this example, both) of the first ON duty ratio difference change which changes the ON duty ratio difference between the first ON duty ratio DT 1  of the first switching device S 1  and the second ON duty ratio DT 2  of the second switching devices S 2 , and the second ON duty ratio difference change which changes the ON duty ratio difference between the third ON duty ratio DT 3  of the third switching device S 3  and the fourth ON duty ratio DT 4  of the fourth switching device S 4 . In the Δduty control, the controller  109  changes the ON duty ratio difference so that the detection value of the charge and discharge capacitor voltage V 0  approaches the charge and discharge capacitor voltage target value V 0 ref. The controller  109  is provided with the second calculation unit  25  that calculates the second calculation value Δduty which changes the ON duty ratio difference in the Δduty control. 
     According to this configuration, although there is a second problem to be described below, even if the variation mentioned above occurs, by changing the second calculation value Δduty and changing the ON duty ratio difference between the first ON duty ratio DT 1  and the second ON duty ratio DT 2 , the charge and discharge capacitor voltage V 0  can be brought close to the target voltage V 0 ref of the charge and discharge capacitor, and cost increase and efficiency deterioration can be suppressed. 
     &lt;Second Problem&gt; 
     Depending on whether it is the power running operation or the regenerative operation, it is necessary to reverse positive/negative of change direction of the ON duty ratio difference (the second calculation value Δduty) to the difference voltage V 0 err between the target voltage V 0 ref of the charge and discharge capacitor and the charge and discharge capacitor voltage V 0 . Accordingly, in the present embodiment, the controller  109  reverses positive/negative of change direction of the ON duty ratio difference (the second calculation value Δduty) in accordance with positive/negative of the reactor current IL detected by the current sensor  105 . 
     However, in a low power state, a magnitude of the reactor current IL may become small and the reactor current IL may become within a detection error range of the current sensor  105 . For this reason, there was the case where determination of positive/negative of the reactor current IL was mistaken, and change direction of the second calculation value Δduty was mistaken. As a result, there was the case where the charge and discharge capacitor voltage V 0  deviated from the target voltage V 0 ref of the charge and discharge capacitor. In the case where the electric motor  3  is configured so as to continue the low power state, if the low power state is taken into consideration, it was necessary to set the element breakdown voltage of the switching device to greater than or equal to the output voltage V 2 , and factors of excessive cost increase and efficiency deterioration were not able to be avoided. 
     To this problem, a second control method which controls the charge and discharge capacitor voltage V 0  will be explained. In order to minimize ripple of the reactor current IL, in an ideal state without variation, a phase of the first gate signal G 1  of the first switching device S 1  and a phase of the second gate signal G 2  of the second switching device S 2  are shifted mutually by 180 degrees. When further phase shift amount from this state where phases are shifted by 180 degrees ideally is set to 8, the capacity of the charge and discharge capacitor  101   a  is set to C 0 , and the inductance value of the reactor  12  is set to L, state average equations of the charge and discharge capacitor voltage V 0  of the DC/DC converter  1  can be expressed by an equation (5). As shown in the equation (5), the state equations differ between the case where the step-up ratio N is less than twice and the case where the step-up ratio N is greater than or equal to twice. 
     
       
         
           
             
               
                 
                   
                     
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     As seen from the equation (5), when the additional phase shift Θ is set to a positive value, the voltage of the charge and discharge capacitor voltage V 0  will rise, and when the additional phase shift Θ is set to a negative value, the voltage of the charge and discharge capacitor voltage V 0  will drop. Accordingly, by changing a relative phase between the ON period of the first switching device S 1  and the ON period of the second switching device S 2  in an increasing direction or a decreasing direction, the voltage of the charge and discharge capacitor voltage V 0  can be changed in an increasing direction or a decreasing direction. 
     Accordingly, in the present embodiment, as mentioned above, the controller  109  controls the charge and discharge capacitor voltage V 0  by performing the phase shift control. The phase shift control is the control which performs one or both (in this example, both) of the first phase difference change which changes the phase difference between the phase of the ON period of the first switching device S 1  and the phase of the ON period of the second switching device S 2 , and the second phase difference change which changes the phase difference between the phase of the ON period of the third switching device S 3  and the phase of the ON period of the fourth switching device S 4 . In the phase shift control, the controller  109  changes the phase difference so that the detection value of the charge and discharge capacitor voltage V 0  approaches the charge and discharge capacitor voltage target value V 0 ref. The controller  109  is provided with a third calculation unit  26  that calculates the third calculation value θ which changes the phase difference in the phase shift control. 
     According to this configuration, it is not necessary to change the phase difference (the third calculation value θ) in accordance with positive/negative of the reactor current IL detected by the current sensor  105 ; even in the low power state where the magnitude of the reactor current IL is small and the reactor current IL becomes within the detection error range of the current sensor  105 , the charge and discharge capacitor voltage V 0  can accurately be controlled. 
     But since the method of generating the gate signals G 1  to G 4  by comparing the first triangular wave and the first control value SD 1  and comparing the second triangular wave and the second control value SD 2  is used, the third calculation value θ from which the first control value SD 1  and the second control value SD 2  become values other than 0 to 1 cannot be added or subtracted. In particular, in the case where the first calculation value Duty is around zero (low step-up, low step-down) or around one (high step-up, high step-down), since the first control value SD 1  and the second control value SD 2  approach the lower limit 0 and the upper limit 1 by small phase difference (the third calculation value θ), it is necessary to limit the phase difference (the third calculation value θ). In the present embodiment, in the case where the first calculation value Duty is around zero (low step-up, low step-down) or around one (high step-up, high step-down), as described below, the phase difference (the third calculation value θ) is limited. On the other hand, by limiting the phase difference (the third calculation value θ) in the case of low step-up, low step-down, high step-up, and high step-down, since the phase difference after limitation (third calculation value θ) is insufficient against the loss owing to the circuit resistance components, and the deviation amount of the charge and discharge capacitor voltage V 0  from the charge and discharge capacitor voltage target value V 0 ref owing to the variation in signal delay of the gate signals, there is a problem that the charge and discharge capacitor voltage V 0  hardly follow the charge and discharge capacitor voltage target value V 0 ref. 
     Accordingly, in the present embodiment, as described above, since not only the phase shift control by the third calculation value θ but also the Δduty control by the second calculation value Δduty can be performed, even in low step-up or high step-up, it is possible to make the charge and discharge capacitor voltage V 0  follow the charge and discharge capacitor voltage target value V 0 ref. 
     As mentioned above, in the Δduty control by the second calculation value Δduty, since the phase shift control by the third calculation value θ can be performed in the low power state where the charge and discharge capacitor voltage V 0  is hardly controlled with sufficient accuracy, it is possible to make the charge and discharge capacitor voltage V 0  follow the charge and discharge capacitor voltage target value V 0 ref with sufficient accuracy. 
     &lt;Detailed Operation of the Controller  109 &gt; 
     Hereinafter, detailed operation of the controller  109  will be explained. In the case where the output voltage V 2  is larger than the output voltage target value V 2 ref, in order to reduce the output voltage V 2 , the first calculation unit  24  reduces the first calculation value Duty by the first controller  24   a  so that both ON duty ratios DT 1 , DT 2  of the first and the second switching devices S 1 , S 2  become small. On the contrary, in the case where the output voltage V 2  is smaller than the output voltage target value V 2 ref, in order to raise the output voltage V 2 , the first calculation unit  24  increases the first calculation value Duty by the first controller  24   a  so that both ON duty ratios DT 1 , DT 2  of the first and the second switching devices S 1 , S 2  become large. 
     In the Δduty control, the controller  109  changes the positive or negative change direction of the ON duty ratio difference in accordance with a current direction of the reactor current IL detected by the current sensor  105 . In the present embodiment, the second calculation unit  25  changes the positive or negative change direction of the second calculation value Δduty, which changes the ON duty ratio difference, in accordance with the current direction of reactor current IL. Specifically, in the case where the reactor current IL is positive and the charge and discharge capacitor voltage V 0  is larger than the charge and discharge capacitor voltage target value V 0 ref, in order to reduce the charge and discharge capacitor voltage V 0 , the second calculation unit  25  decreases the second calculation value Δduty so that the first ON duty ratio DT 1  of the first switching device S 1  is decreased and the second ON duty ratio DT 2  of the second switching device S 2  is increased. In the case where the reactor current IL is positive and the charge and discharge capacitor voltage V 0  is smaller than the charge and discharge capacitor voltage target value V 0 ref, in order to raise the charge and discharge capacitor voltage V 0 , the second calculation unit  25  increases the second calculation value Δduty so that the first ON duty ratio DT 1  of the first switching device S 1  is increased and the second ON duty ratio DT 2  of the second switching device S 2  is decreased. 
     On the other hand, in the case where the reactor current IL is negative and the charge and discharge capacitor voltage V 0  is larger than the charge and discharge capacitor voltage target value V 0 ref, in order to reduce the charge and discharge capacitor voltage V 0 , the second calculation unit  25  increases the second calculation value Δduty so that the first ON duty ratio DT 1  of the first switching device S 1  is increased and the second ON duty ratio DT 2  of the second switching device S 2  is decreased. In the case where the reactor current IL is negative and the charge and discharge capacitor voltage V 0  is smaller than the charge and discharge capacitor voltage target value V 0 ref, in order to raise the charge and discharge capacitor voltage V 0 , the second calculation unit  25  decreases the second calculation value Δduty so that the first ON duty ratio DT 1  of the first switching device S 1  is decreased and the second ON duty ratio DT 2  of the second switching device S 2  is increased. 
     In the Δduty control, the controller  109  changes a magnitude of the change amount of the ON duty ratio difference in accordance with a magnitude of the reactor current IL. In the present embodiment, the second calculation unit  25  changes a magnitude of the second calculation value Δduty calculated based on the charge and discharge capacitor difference voltage V 0 err, in accordance with the magnitude of the reactor current IL. Specifically, the second calculation unit  25  decreases the magnitude of the second calculation value Δduty calculated based on the charge and discharge capacitor difference voltage V 0 err, as the magnitude of reactor current IL becomes large. 
     In the case where the reactor current IL is within a preliminarily set stop range of the Δduty control including zero, the controller  109  stops performing of the Δduty control, but controls the charge and discharge capacitor voltage V 0  by performing the phase shift control. In the present embodiment, in the case where the reactor current IL is within the preliminarily set stop range of the Δduty control including zero, the second calculation unit  25  stops a calculation of the second calculation value Δduty, and does not change the switching operation of the switching devices by the second calculation value Δduty. In the case where the reactor current IL is within the stop range of the Δduty control, the third calculation unit  26  calculates the third calculation value θ, and changes the switching operation of the switching devices by the third calculation value θ. 
     In the present embodiment, the second calculation unit  25  is provided with the current limiting unit  25   a  and the difference voltage correction unit  25   b  for the above-mentioned calculation of the second calculation value Δduty according to the reactor current IL.  FIG. 11  is a related figure showing a process of the current limiting unit  25   a . The current limiting unit  25   a  outputs a positive value as a reactor current IL* after limitation, in the case where the reactor current IL is positive; outputs a negative value as the reactor current IL* after limitation, in the case where the reactor current IL is negative; and outputs 0 as the reactor current IL* after limitation, in the case where the reactor current IL is within the stop range of the Δduty control including zero (−ILlim &lt;IL&lt;ILlim). In the present embodiment, the current limiting unit  25   a  sets IL* =IL at the outside of the stop range of the Δduty control. 
     Based on the charge and discharge capacitor difference voltage V 0 err and the reactor current IL* after limitation, as shown in the equation (6), the difference voltage correction unit  25   b  outputs 0 as a difference voltage V 0 err* after current correction, in the case where the reactor current IL* after limitation is 0; and outputs a value obtained by dividing the charge and discharge capacitor difference voltage V 0 err by the reactor current IL* after limitation, as the difference voltage V 0 err* after current correction, in the case where the reactor current IL* after limitation is not 0. Then, the difference voltage V 0 err* after current correction is inputted into the second controller  25   c.  
 
1) In the case of  IL*= 0  V 0 err*= 0 2) In the case of  IL*!= 0  V 0 err*=V 0 err/IL*   (6)
 
     Thus, in the case where the reactor current IL* after limitation is not 0, by dividing the charge and discharge capacitor difference voltage V 0 err by the reactor current IL* after limitation whose positive or negative sign is the same as the reactor current IL, the sign of a value inputted into the second controller  25   c  can be changed in accordance with positive/negative of the reactor current IL, and the positive or negative change direction of the second calculation value Δduty can be changed. By dividing the charge and discharge capacitor difference voltage V 0 err by the reactor current IL* after limitation which is equal to the reactor current IL, in the equation (2), since (DT 1  −DT 2 ) is in inverse proportion to the reactor current IL, a computed value of (DT 1  −DT 2 )/C 0 ×IL can be prevented from changing in accordance with the magnitude of the reactor current IL, and a change rate d(V 0 )/dt of the charge and discharge capacitor voltage V 0  can be prevented from changing in accordance with the magnitude of the reactor current IL. Therefore, control behavior of the charge and discharge capacitor voltage V 0  is not influenced by the magnitude of the reactor current IL and can be stabilized. 
     In the case where the reactor current IL is within the stop range of the Δduty control, the reactor current IL* after limitation is set to 0, and the difference voltage V 0 err* after current correction is set to 0, the second calculation value Δduty outputted from the second controller  25   c  becomes 0, and the Δduty control stops. In this case, by the phase shift control using the third calculation value θ, the charge and discharge capacitor voltage V 0  is controlled to approach the charge and discharge capacitor voltage target value V 0 ref. On the other hand, in the case where the reactor current IL is outside the stop range of the Δduty control, the charge and discharge capacitor voltage V 0  is controlled by the phase shift control and the Δduty control to approach the charge and discharge capacitor voltage target value V 0 ref. 
     In the case where the charge and discharge capacitor voltage V 0  is larger than the charge and discharge capacitor voltage target value V 0 ref, in order to reduce the charge and discharge capacitor voltage V 0 , the third calculation unit  26  decreases the third calculation value θ so as to advance the phase of the ON period of the first switching device S 1  and delay the phase of the ON period of the second switching device S 2 . On the other hand, in the case where the charge and discharge capacitor voltage V 0  is smaller than the charge and discharge capacitor voltage target value V 0 ref, in order to raise the charge and discharge capacitor voltage V 0 , the third calculation unit  26  increases the third calculation value θ so as to delay the phase of the ON period of the first switching device S 1  and advance the phase of the ON period of the second switching device S 2 . 
     The upper graph of  FIG. 12  shows an execution region of the Δduty control by the second calculation value Δduty, and an execution region of the phase shift control by the third calculation value θ. The vertical axis of the upper graph of  FIG. 12  is the reactor current IL. The horizontal axis of the upper graph of  FIG. 12  is the first calculation value Duty; when the first calculation value Duty is 0, the ON duty ratios DT 1 , DT 2  of the first and the second switching devices S 1 , S 2  become 0; when the first calculation value Duty is 1, the ON duty ratios DT 1 , DT 2  of the first and the second switching devices S 1 , S 2  become 1. In a region where the reactor current IL becomes within the stop range of the Δduty control from −ILlim to ILlim, the Δduty control is not performed but the phase shift control is performed. In a region where the reactor current IL becomes outside the stop range of the Δduty control, the Δduty control is performed. 
     In the case where the basis ON duty ratio which is the average value between the first ON duty ratio DT 1  of the first switching device S 1  and the second ON duty ratio DT 2  of the second switching device S 2  is less than or equal to a preliminarily set low power determination value DutyL, or in the case where the basis ON duty ratio is larger than or equal to a preliminarily set high power determination value DutyH, the controller  109  stops performing of the phase shift control, but controls the charge and discharge capacitor voltage V 0  by performing the Δduty control. In the present embodiment, in the case where the first calculation value Duty which changes the basis ON duty ratio is less than or equal to the low power determination value DutyL, or in the case where the first calculation value Duty is greater than or equal to the high power determination value DutyH, the third calculation unit  26  stops a calculation of the third calculation value θ, and does not change the switching operation of the switching devices by the third calculation value θ. In the case where the first calculation value Duty is less than or equal to the low power determination value DutyL, or in the case where the first calculation value Duty is greater than or equal to the high power determination value DutyH, the second calculation unit  25  calculates the second calculation value Δduty, and changes the switching operation of the switching devices by the third calculation value θ. 
     In the present embodiment, as shown in the upper graph of  FIG. 12 , in the region where the reactor current IL becomes outside the stop range of the Δduty control and the low step-up region (or the low step-down region) where the first calculation value Duty becomes less than or equal to the low power determination value DutyL, the phase shift control is not performed but the Δduty control is performed. In the region where the reactor current IL becomes outside the stop range of the Δduty control and the high step-up region (or the high step-down region) where the first calculation value Duty becomes greater than or equal to the high power determination value DutyH, the phase shift control is not performed but the Δduty control is performed. In the region where the reactor current IL becomes outside the stop range of the Δduty control and the region where the first calculation value Duty becomes outside the low step-up region and the high step-up region, the phase shift control and the Δduty control are performed. 
     The lower graph of  FIG. 12  shows a calculation of a limiting value θlim which limits the third calculation value θ in the limiter  27  in order to prevent the first control value SD 1  and the second control value SD 2  deviating from the range of 0 to 1 in the region where the phase shift control is performed. The vertical axis of the lower graph of  FIG. 12  shows the limiting value θlim; the horizontal axis of the lower graph shows the first calculation value Duty. 
     In the case where the first calculation value Duty is less than 0.5, since Duty—|Δduty| approaches the lower limit (in this example, 0), the limiting value θlim is set to Duty—|Δduty| so that Duty −|Δduty|−θ becomes greater than or equal to the lower limit (0). But in the case where Duty −|Δduty| becomes less than or equal to 0, the limiting value θlim is set to 0. In the case where the first calculation value Duty is greater than or equal to 0.5, since Duty +|Δduty| approaches the upper limit value (in this example, 1), the limiting value θlim is set to 1−Duty −|Δduty| so that Duty+|Δduty| +e becomes less than or equal to the upper limit value (1). But in the case where 1−Duty −|Δduty| becomes less than or equal to 0, the limiting value θlim is set to 0. In the region where the reactor current IL becomes within the stop range of the Δduty control and the Δduty control is not performed, it becomes |Δduty|=0, thereby, it becomes DutyL=0 and DutyH=1. In the region where the Δduty control is performed, it becomes DutyL=|Δduty| and DutyH=1−|Δduty|. Like this, in the region of −|Llim &lt;IL&lt;ILlim where the Δduty control is not performed, an operating range of the phase shift control is expanded, and it becomes possible to control the charge and discharge capacitor voltage V 0  to the charge and discharge capacitor voltage target value V 0 ref by the phase shift control. 
     As shown in an equation (7), in the case where a third calculation value θ* before limitation outputted from the third controller  26   a  becomes less than or equal to a value (−θlim) that multiplied −1 to the limiting value θlim, the limiter  27  sets −θlim to the third calculation value θ after limitation; in the case where the third calculation value θ* before limitation becomes greater than or equal to the limiting value θlim, the limiter  27  sets θlim to the third calculation value θ after limitation; in the case where the third calculation value θ* before limitation becomes within the range of −θlim to θlim, the limiter  27  sets the third calculation value θ* before limitation to the third calculation value θ after limitation as it is.
 
1) In the case of θ*&lt;=−θ lim θ=−θlim  2) In the case of θ*&gt;=θ lim θ=θlim  3) In the case of −θ lim&lt;θ*&lt;θlim θ=   (7)
 
     In this way, by applying limitation to the third calculation value θ using the first calculation value Duty and the second calculation value Δduty, the first control value SD 1  and the second control value SD 2  in which the second calculation value Δduty and the third calculation value θ were reflected can be prevented from becoming outside range of 0 to 1. 
     At least in the case where the phase difference which is changed by the phase shift control is fixed, the controller  109  controls the charge and discharge capacitor voltage V 0  by performing the Δduty control. In the present embodiment, even in the case where the third calculation value θ is fixed to the limiting value θlim by the limiter  27 , and in the case where it is the low step-up region or the high step-up region and the third calculation value θ is fixed to 0, the second calculation unit  25  changes the second calculation value Δduty. At least in the case where the ON duty ratio difference which is changed by the Δduty control is fixed, the controller  109  controls the charge and discharge capacitor voltage V 0  by performing the phase shift control. In the present embodiment, even in the case where it is within the stop range of the Δduty control and the second calculation value Δduty is fixed to 0, the third calculation unit  26  changes the third calculation value θ. Therefore, the charge and discharge capacitor voltage V 0  can be controlled by at least either the Δduty control or the phase shift control. 
     By providing the controllers  109  as described above, regardless of the power running operation (the step-up operation) or the regenerative operation (the step-down operation), high power or low power, it becomes possible to control the output voltage V 2  to the output voltage target value V 2 ref, and it becomes possible to control the charge and discharge capacitor voltage V 0  to the charge and discharge capacitor voltage target value V 0 ref without depending on the reactor current IL. Therefore, even though the element breakdown voltage of each switching device is reduced, it is possible to avoid the danger of element breakdown more certainly, thereby, the low cost and efficient DC/DC converter  1  can be obtained. Since the current sensor  105  should just have a function to determine the direction of the current which flows through the reactor  12  and have higher detection accuracy than the determination value ILlim which defines the stop range of the Δduty control, a low cost sensor can be used. 
     Embodiment 2 
     Next, the DC/DC converter  1  according to Embodiment 2 will be explained with reference to drawings.  FIG. 13  is a circuit diagram (a block diagram) showing a configuration of the controller  109  according to the present embodiment. The basic configuration of the DC/DC converter  1  according to the present embodiment is the same as that of Embodiment 1; however, a configuration of the limiter  27  and a configuration which performs the phase shift control also in the low step-up region and the high step-up region are different from Embodiment 1. 
     In the present embodiment, in the phase shift control, the controller  109  performs an upper limitation to a magnitude of a change amount of the phase difference so that a transition order of the operation modes, which are the switching patterns of the switching devices S 1  to S 4 , does not change. The controller  109  is provided with a first limiter  27 X and a second limiter  27 Y as the limiter. In the low step-up region and the high step-up region, the first limiter  27 X performs the upper limitation of the third calculation value θ, which represents the magnitude of the change amount of the phase difference, so that the transition order of the operation modes does not change. In the present embodiment, the first limiter  27 X performs an upper and lower limitation by the limiting value θlim to the third calculation value θ before limitation outputted from the third controller  26   a , as is the case with the equation (7), and outputs the third calculation value θ after limitation. 
     The upper row graph of  FIG. 14  shows the execution region of the Δduty control by the second calculation value Δduty, and the execution region of the phase shift control by the third calculation value θ. The vertical axis of the upper graph of  FIG. 14  is the reactor current IL. The horizontal axis of the upper graph of  FIG. 14  is the first calculation value Duty; when the first calculation value Duty is 0, the ON duty ratios DT 1 , DT 2  of the first and the second switching devices S 1 , S 2  are set to 0; when the first calculation value Duty is 1, the ON duty ratio DT 1 , DT 2  of the first and the second switching devices S 1 , S 2  are set to 1. In the region where the reactor current IL becomes within the stop range of the Δduty control from −ILlim to ILlim, as is the case with Embodiment 1, the Δduty control is not performed but the phase shift control is performed. In the region where the reactor current IL becomes outside the stop range of the Δduty control, the Δduty control is performed. 
     The lower graph of  FIG. 14  shows a calculation of the limiting value θlim, which is used in the first limiter  27 X, in a region where both of the Δduty control and the phase shift control are performed. The vertical axis of the lower graph of  FIG. 14  shows the limiting value θlim; the horizontal axis of the lower graph shows the first calculation value Duty. 
     In the case where the first calculation value Duty is less than 0.5, the limiting value θlim is set to the first calculation value Duty so that the transition order of the operation modes does not change (θlim=Duty). In the case where the first calculation value Duty is greater than or equal to 0.5, the limiting value θlim is set to a value obtained by subtracting the first calculation value Duty from 1 so that the transition order of the operation modes does not change (θlim=1−Duty). 
     Accordingly, in the present embodiment, since the limiting value θlim limits the third calculation value θ so that the transition order of operation modes does not change, it is not necessary to stop the phase shift control in the low step-up region and the high step-up region like Embodiment 1, and the phase shift control can be performed in the whole regions. 
     The second limiter  27 Y limits the second calculation value Δduty so that the first control value SD 1  and the second control value SD 2  do not become outside the range of the minimum values (in this example, 0) to the maximum value (in this example, 1). In the present embodiment, the second limiter  27 Y performs the upper and lower limitation by a second limiting value Δdutylim to the second calculation value Δduty* before limitation outputted from the second controller  25   c , and outputs the second calculation value Δduty after limitation. 
     The second calculation value Δduty* before limitation, the first calculation value Duty, and the third calculation value θ after limitation are inputted into the second limiter  27 Y. In the case where the first calculation value Duty is less than 0.5, the second limiting value Δdutylim is set to a value obtained by subtracting the absolute value of the third calculation value θ after limitation from the first calculation value Duty (Δdutylim=Duty −|θ|). In the case where the first calculation value Duty is greater than or equal to 0.5, the second limiting value Δdutylim is set to a value obtained by subtracting the first calculation value Duty and the absolute value of the third calculation value θ after limitation from 1 (Δdutylim =1−Duty −|θ|). 
     As shown in an equation (8), in the case where the second calculation value Δduty* before limitation outputted from the second controller  25   c  becomes less than or equal to a value (−Δdutylim) obtained by multiplying −1 to the second limiting value Δdutylim, the second limiter  27 Y sets −Δdutylim to the second calculation value Δduty after limitation; in the case where the second calculation value Δduty* before limitation becomes greater than or equal to the second limiting value Δdutylim, the second limiter  27 Y sets Δdutylim to the second calculation value Δduty after limitation; in the case where the second calculation value Δduty* before limitation becomes within the range of −Δdutylim to Δdutylim, the second limiter  27 Y sets the second calculation value Δduty* before limiting to the second calculation value Δduty after limitation as it is.
 
1) In the case of Δduty*&lt;=−Δduty lim Δduty=−Δduty lim 2) In the case of Δduty*&gt;=Δduty lim Δduty=Δduty lim 3) In the case of −Δduty lim &lt;Δduty*&lt;Δduty lim Δduty=Δduty*  (8)
 
     In this way, by applying limitation to the second calculation value Δduty using the first calculation value Duty and the third calculation value θ, the first control value SD 1  and the second control value SD 2  in which the second calculation value Δduty and the third calculation value θ were reflected can be prevented from becoming outside range of 0 to 1. 
     Even in the case where the third calculation value θ is fixed to the limiting value θlim by the first limiter  27 X, the second calculation unit  25  changes the second calculation value Δduty. Even in the case where it is within the stop range of the Δduty control and the second calculation value Δduty is fixed to 0, and in the case where the second calculation value Δduty is fixed to the second limiting value Δdutylim by the second limiter  27 Y, the third calculation unit  26  changes the third calculation value θ. Therefore, the charge and discharge capacitor voltage V 0  can be controllable by at least either the second calculation value Δduty or the third calculation value θ. 
     Even in the present embodiment, as is the case with Embodiment 1, regardless of the power running operation (the step-up operation) or the regenerative operation (the step-down operation), high power or low power, it becomes possible to control the output voltage V 2  to the output voltage target value V 2 ref, and it becomes possible to control the charge and discharge capacitor voltage V 0  to the charge and discharge capacitor voltage target value V 0 ref without depending on the reactor current IL. Therefore, even though the element breakdown voltage of each switching device is reduced, it is possible to avoid the danger of element breakdown more certainly, thereby, the low cost and efficient DC/DC converter  1  can be obtained. Since the current sensor  105  should have a function to determine the direction of the current which flows through the reactor  12  and have higher detection accuracy than the determination value ILlim which defines the stop range of the Δduty control, a low cost sensor can be used. 
     Embodiment 3 
     Next, the DC/DC converter  1  according to Embodiment 3 will be explained with reference to drawings.  FIG. 15  is a circuit diagram (a block diagram) showing a configuration of the controller  109  according to the present embodiment. The explanation for constituent parts the same as those in Embodiment 1 will be omitted. The basic configuration of the DC/DC converter  1  according to the present embodiment is the same as that of Embodiment 1; however, a configuration that the controller  109  calculates a current command value I 0 ref which flows into the charge and discharge capacitor  101   a  as a common intermediate control parameter in the Δduty control and the phase shift control, and changes the ON duty ratio difference and the phase difference based on the current command value I 0 ref is different from Embodiment 1. 
     That is to say, in the Δduty control and the phase shift control, the controller  109  changes the current command value I 0 ref (hereinafter, referred to as the charge and discharge capacitor current command value I 0 ref) which flows into the charge and discharge capacitor  101   a  so that the detection value of the charge and discharge capacitor voltage V 0  approaches the charge and discharge capacitor voltage target value V 0 ref. Then, the controller  109  changes the ON duty ratio difference based on the charge and discharge capacitor current command value I 0 ref, and changes the phase difference based on the charge and discharge capacitor current command value I 0 ref. 
     Since the charge and discharge capacitor current IC 0  is proportional to a time change speed (dV 0 /dt) of the charge and discharge capacitor voltage V 0 , it is an important parameter for controlling the charge and discharge capacitor voltage V 0 . According to the above-mentioned configuration, since the charge and discharge capacitor current command value I 0 ref, which is the common intermediate control parameter, is calculated in the Δduty control and the phase shift control, and the ON duty ratio difference and the phase difference are changed based on the charge and discharge capacitor current command value I 0 ref, it is possible to improve the control accuracy of the charge and discharge capacitor voltage V 0  by two kinds of control methods. 
     The controller  109  distributes the charge and discharge capacitor current command value I 0 ref to a current command value I 0 delta for the Δduty control and a current command value I 0 shift for the phase shift control. Then, the controller  109  changes the ON duty ratio difference based on the current command value I 0 delta for the Δduty control, and changes the phase difference based on the current command value I 0 shift for the phase shift control. 
     According to this configuration, since the charge and discharge capacitor current command value I 0 ref is distributed and the Δduty control and the phase shift control are performed, even if two kinds of control methods are used, the control behavior of the charge and discharge capacitor voltage V 0  can be stabilized. 
     In the present embodiment, as shown in  FIG. 15 , the controller  109  is provided with a current command calculating unit  31 . The current command calculating unit  31  calculates the charge and discharge capacitor current command value I 0 ref based on the difference voltage V 0 err (the charge and discharge capacitor difference voltage V 0 err) between the detection value of the charge and discharge capacitor voltage V 0  and the charge and discharge capacitor voltage target value V 0 ref. The current command calculating unit  31  calculates the charge and discharge capacitor current command value I 0 ref by performing a feedback control, such as P control, PI control, and PID control, to the charge and discharge capacitor difference voltage V 0 err. 
     The controller  109  is provided with a distribution calculating unit  32 . The distribution calculating unit  32  distributes the charge and discharge capacitor current command value I 0 ref to the current command value I 0 delta for the Δduty control and the current command value I 0 shift for the phase shift control. 
     In the present embodiment, the distribution calculating unit  32  changes a distribution ratio Ri between the current command value I 0 delta for the Δduty control and the current command value I 0 shift for the phase shift control in accordance with the reactor current IL detected by the current sensor  105 . In this example, the distribution ratio Ri is a distribution ratio of the current command value I 0 delta for the Δduty control to the charge and discharge capacitor current command value I 0 ref, and is set to a value of greater than or equal to 0 and less than or equal to 1. As shown in an equation (9), the distribution calculating unit  32  sets a value obtained by multiplying the charge and discharge capacitor current command value I 0 ref to the distribution ratio Ri, to the current command value I 0 delta for the Δduty control, and sets a value obtained by multiplying the charge and discharge capacitor current command value I 0 ref to a value obtained by subtracting the distribution ratio Ri from 1, to the current command value I 0 shift for the phase shift control.
 
 I 0delta= Ri×I 0ref  I 0shift=(1− Ri )× I 0ref 0&lt;= Ri&lt;= 1  (9)
 
     As shown in examples of  FIG. 16  to  FIG. 18 , in the case where the reactor current IL is within the preliminarily set stop range of the Δduty control including 0, the distribution calculating unit  32  sets the distribution ratio Ri to 0; in the case where the reactor current IL is outside the stop range of the Δduty control, the distribution calculating unit  32  sets the distribution ratio Ri to a larger value than 0. 
     When the distribution ratio Ri is set to 0, the current command value I 0 delta for the Δduty control becomes 0, thereby, as described later, the ON duty ratio difference becomes 0, and the Δduty control is stopped. On the other hand, when the distribution ratio Ri is set to a value larger than 0, the current command value I 0 delta for the Δduty control becomes a value larger than 0 or a value smaller than 0, thereby, as described later, the ON duty ratio difference becomes a value larger than 0 or a value smaller than 0, and the Δduty control is operated. 
     According to this configuration, in a region where the reactor current IL becomes within the stop range of the Δduty control, as is the case with Embodiments 1, 2, the Δduty control is not performed but the phase shift control is performed. In a region where the reactor current IL becomes outside the stop range of the Δduty control, the Δduty control is performed. In this case, since it is managed with the distribution ratio Ri, the control amount of the stopped Δduty control can be automatically distributed to the control amount of the phase shift control. 
     In  FIG. 16  to  FIG. 18 , the horizontal axis is the reactor current IL, and the vertical axis is the distribution ratio Ri. In examples shown in  FIG. 16  to  FIG. 18 , in the stop range of the Δduty control where the reactor current IL becomes within the range of −ILL to ILL (−ILL &lt;=IL&lt;=ILL), the distribution ratio Ri is set to 0, the Δduty control is stopped and the phase shift control is operated. In the range where the reactor current IL becomes less than or equal to −ILH or greater than or equal to ILH (IL&lt;=−ILH, ILH &lt;=IL), the distribution ratio Ri is set to one, the Δduty control is operated and the phase shift control is stopped. 
     In the range (−ILH &lt;=IL&lt;=−ILL) where the reactor current IL becomes within the range of −ILH to −ILL, and the range (ILL&lt;=IL&lt;=ILH) where the reactor current IL becomes within the range of ILL to ILH; in example shown in  FIG. 16 , the distribution ratio Ri is switched between 0 and 1 by hysteresis determination; in example shown in  FIG. 17 , the distribution ratio Ri is changed between 0 and 1 gradually; in example shown in  FIG. 18 , the distribution ratio Ri is changed between 0 and 1 stepwise. 
     The third calculation unit  26  which performs the phase shift control is provided with a phase difference conversion unit  33 . The phase difference conversion unit  33  converts the current command value I 0 shift for the phase shift control into the phase difference. An equation (10) is obtained by rearranging the equation (5) derived above, with regard to the phase shift amount from the basis phase difference  8  which is 180 degrees. Here, since a value obtained by multiplying the time change speed dV 0 /dt of the charge and discharge capacitor voltage V 0  to the capacity C 0  of the charge and discharge capacitor is equal to the charge and discharge capacitor current IC 0 , it is replaced to the charge and discharge capacitor current IC 0 . By using the equation (10), the charge and discharge capacitor current IC 0  can be converted into the phase shift amount Θ; the conversion equations differ depending on whether the step-up ratio N (the step-down ratio N) is less than twice. 
     
       
         
           
             
               
                 
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     Then, as shown in an equation (11), the phase difference conversion unit  33  converts the current command value I 0 shift for the phase shift control into the third calculation value θ* before limitation, using a phase difference conversion coefficient Z calculated based on the input voltage V 1  and the output voltage V 2 . Here, the phase difference conversion unit  33  switches a calculation equation of the phase difference conversion coefficient Z, depending on whether the step-up ratio N (the step-down ratio N) is less than twice. 
     
       
         
           
             
               
                 
                   
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     As is the case with Embodiment 1, as shown in an equation (7), in the case where the third calculation value θ* before limitation outputted from the phase difference conversion unit  33  becomes less than or equal to a value (−θlim) that multiplied −1 to the limiting value θlim, the limiter  27  sets −θlim to the third calculation value θ after limitation; in the case where the third calculation value before limitation becomes greater than or equal to the limiting value θlim, the limiter  27  sets θlim to the third calculation value θ after limitation; in the case where the third calculation value θ* before limitation becomes within the range of −θlim to θlim, the limiter  27  sets the third calculation value θ* before limitation to the third calculation value θ after limitation as it is. The limiting value θlim is set, as explained using the lower graph of  FIG. 12 . According to this configuration, as is the case with Embodiment 1, the transition order of the operation modes, which are switching patterns of the switching devices S 1  to S 4 , can be prevented from changing. 
     Then, as is the case with Embodiment 1, the rectangular wave multiplier  26   b  calculates the final third calculation value ±6 by multiplying the rectangular wave of ±1 outputted from the rectangular wave generator  26   c  to the third calculation value θ. 
     The second calculation unit  25  which performs the Δduty control is provided with a Δduty conversion unit  34 . The Δduty conversion unit  34  converts the current command value I 0 delta for the Δduty control into the ON duty ratio difference. An equation (12) is obtained by picking out the second line of the equation (1) derived above and rearranging with regard to (DT 1  −DT 2 ) which becomes the ON duty ratio difference. Here, as is the case with the equation (10), C 0 ×dV 0 /dt is replaced to the charge and discharge capacitor current IC 0 . Using the equation (12), the charge and discharge capacitor current IC 0  can be converted into the ON duty ratio difference. 
     
       
         
           
             
               
                 
                   
                     
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                   ( 
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                             d 
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                       IC 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       
                         0 
                         · 
                         
                           1 
                           
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                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             L 
                           
                         
                       
                     
                   
                 
               
               
                 
                     
                 
               
             
           
         
       
     
     Then, as shown in an equation (13), the Δduty conversion unit  34  calculates a value obtained by dividing the current command value I 0 delta for the Δduty control by the reactor current IL, as the second calculation value Δduty. Here, in the case where the reactor current IL is within the stop range of the Δduty control, since the current command value I 0 delta for the Δduty control is set to 0, the second calculation value Δduty is set to 0. According to this configuration, as is the case with Embodiment 1, the ON duty ratio difference is changed in accordance with the reactor current IL, and the positive or negative change direction of the ON duty ratio difference is changed in accordance with the current direction of the reactor current IL.
 
Δduty= I 0delta/ IL   (13)
 
     As is the case with Embodiment 2, the second limiter  27 Y may perform the upper and lower limitation by the second limiting value Δdutylim to the second calculation value Δduty outputted from the Δduty conversion unit  34 . 
     Since the configuration of the first calculation unit  24 , the switching control unit  30  and the like is the same as that of Embodiment 1, the explanation will be omitted. 
     Embodiment 4 
     Next, the DC/DC converter  1  according to Embodiment 4 will be explained with reference to drawings. The explanation for constituent parts the same as those in Embodiment 3 will be omitted. The basic configuration of the DC/DC converter  1  according to the present embodiment is the same as that of Embodiment 3; however, a processing of the distribution calculating unit  32  differs from Embodiment 3. 
     That is to say, in the case of performing the upper and lower limitation to one or both of the ON duty ratio difference and the phase difference, the distribution calculating unit  32  distributes a part, which exceeded the upper and lower limitation value in the phase difference or the ON duty ratio difference to which the upper and lower limitation was performed, to the current command value I 0 delta for the Δduty control or the current command value I 0 shift for the phase shift control corresponding to the phase difference or the ON duty ratio difference to which the upper and lower limitation is not performed. 
     According to this configuration, since the part of the current command value to which the upper and lower limitation is performed can be distributed to the current command value to which the upper and lower limitation is not performed, and it is possible to reflect in control of the charge and discharge capacitor voltage V 0 , the control behavior of the charge and discharge capacitor voltage V 0  can be stabilized. 
     In the present embodiment, in the case where a temporary set value of the phase difference, which is temporarily set corresponding to the current command value I 0 ref, is upper and lower limited, the distribution calculating unit  32  distributes the part of the current command value corresponding to the part which exceeded the upper and lower limitation value in the temporary set value of the phase difference, to the current command value I 0 delta for the Δduty control, and distributes a remaining part of the current command value to the current command value I 0 shift for the phase shift control. 
     It will be explained in detail using the flow chart shown in  FIG. 19 . In the step S 01 , the distribution calculating unit  32  sets the current command value I 0 ref to a temporary current command value I 0 shift* for the phase shift control. Next, in the step S 02 , the distribution calculating unit  32  calculates a temporary set value θref of the third calculation value by multiplying the phase difference conversion coefficient Z, which was calculated depending on whether the step-up ratio N (the step-down ratio N) is less than twice as shown in an equation (11), to the temporary current command value I 0 shift* for the phase shift control. 
     Next, in the step S 03 , the distribution calculating unit  32  determines whether or not the temporary set value θref of the third calculation value exceeds the upper limitation value θlim used in the limiter  27 . In the case where it is determined that the temporary set value θref of the third calculation value exceeds the upper limitation value θlim (in the step S 03 : Yes), in the step S 05 , the distribution calculating unit  32  sets a value obtained by dividing the upper limitation value θlim by the phase difference conversion coefficient Z, to the current command value I 0 shift for the phase shift control. 
     In the case where it is determined that the temporary set value θref of the third calculation value does not exceeds the upper limitation value θlim (in the step S 03 : No), in the step S 04 , the distribution calculating unit  32  determines whether or not the temporary set value θref of the third calculation value is lower than the lower limitation value −θlim used in the limiter  27 . In the case where it is determined that the temporary set value θref of the third calculation value is lower than the lower limitation value −θlim (in the step S 04 : Yes), in the step S 07 , the distribution calculating unit  32  sets a value obtained by dividing the lower limitation value −θlim by the phase difference conversion coefficient Z, to the current command value I 0 shift for the phase shift control. 
     In the case where it is determined that the temporary set value θref of the third calculation value is not lower than the lower limitation value −θlim (in the step S 04 : No), in the step S 06 , the distribution calculating unit  32  sets the temporary current command value I 0 shift* for the phase shift control to the current command value I 0 shift for the phase shift control. 
     In the step S 08 , the distribution calculating unit  32  sets a value obtained by subtracting the current command value I 0 shift for the phase shift control from the current command value I 0 ref, to the current command value I 0 delta for the Δduty control. 
     Alternatively, as is the case with Embodiment 3, the distribution calculating unit  32  may be configured to distribute the charge and discharge capacitor current command value I 0 ref to the current command value I 0 delta for the Δduty control and the current command value I 0 shift for the phase shift control depending on the distribution ratio Ri; and the distribution calculating unit  32  may be configured to distribute additionally apart of the current command value, which is corresponding to an exceeded part of the third calculation value θ to which the upper and lower limitation is performed in the limiter  27 , to the current command value I 0 delta for the Δduty control. 
     For example, in the case where the third calculation value θ* before limitation is upper limited by the limiting value θlim, the distribution calculating unit  32  adds additionally a value obtained by dividing the exceeded part (θ* −θlim) by the phase difference conversion coefficient Z, to the current command value I 0 delta for the Δduty control. Or, in the case where the third calculation value θ* before limitation is lower limited by the limiting value −θlim, the distribution calculating unit  32  adds additionally a value obtained by dividing the exceeded part (θ* +θlim) by the phase difference conversion coefficient Z, to the current command value I 0 delta for the Δduty control. 
     Alternatively, as is the case with Embodiment 3, the distribution calculating unit  32  may be configured to distribute the charge and discharge capacitor current command value I 0 ref to the current command value I 0 delta for the Δduty control and the current command value I 0 shift for the phase shift control depending on the distribution ratio Ri; and as is the case with Embodiment 2, in the second limiter  27 Y, the upper and lower limitation may be performed by the second limiting value Δdutylim to the second calculation value Δduty. In this case, a part of the current command value, which is corresponding to an exceeded part of the second calculation value Δduty to which the upper and lower limitation is performed in the second limiter  27 Y, may be additionally distributed to the current command value I 0 shift for the phase shift control. 
     For example, in the case where the second calculation value Δduty* before limitation is upper limited by the second limiting value Δdutylim, the distribution calculating unit  32  adds additionally a value obtained by multiplying the reactor current IL to the exceeded part (Δduty* −Δdutylim), to the current command value I 0 shift for the phase shift control. Or, in the case where the second calculation value Δduty* before limitation is lower limited by the second limiting value −Δdutylim, the distribution calculating unit  32  adds additionally a value obtained by multiplying the reactor current IL to the exceeded part (Δduty* +Δdutylim), to the current command value I 0 shift for the phase shift control. 
     Other Embodiments 
     Lastly, other embodiments of the present invention will be explained. Each of the configurations of embodiments to be explained below is not limited to be separately utilized but can be utilized in combination with the configurations of other embodiments as long as no discrepancy occurs. 
     (1) In each of the foregoing embodiments, there has been explained the case where the battery  2  is connected between the input side positive electrode terminal  1   a  and the input side negative electrode terminal  1   b  of low voltage side, and the electric motor  3  is connected between the output side positive electrode terminal  1   c  and the output side negative electrode terminal  1   d  of high voltage side. However, embodiments of the present invention are not limited to the foregoing case. That is to say, between the input side positive electrode terminal  1   a  and the input side negative electrode terminal  1   b  of low voltage side, any electric apparatuses which supply or consume direct current power, such as a battery or an electric motor, may be connected; between the output side positive electrode terminal  1   c  and the output side negative electrode terminals  1   d  of high voltage side, any electric apparatuses which supply or consume direct current power, such as a battery or an electric motor, may be connected. For example, an electric motor may be connected between the input side positive electrode terminal  1   a  and the input side negative electrode terminal  1   b  of low voltage side; a battery may be connected between the output side positive electrode terminal  1   c  and the output side negative electrode terminal  1   d  of high voltage side. 
     (2) In each of the foregoing embodiments, there has been explained the case where the DC/DC converter  1  can perform both of the step-up operation and the step-down operation; and all of the first to the fourth semiconductor circuits have the function of the switching device and the function of the diode element. However, embodiments of the present invention are not limited to the foregoing case. That is to say, the DC/DC converter  1  may perform only the step-up operation; only the first and the second semiconductor circuits may have the function of the switching device, and only the third and the fourth semiconductor circuits may have the function of the diode element. In this case, in the upper graphs of  FIG. 12  and  FIG. 14 , the controller  109  is configured to perform the control only in the region where the reactor current IL is positive; in  FIG. 1 , the controller  109  is configured to generate the first and the second gate signals G 1 , G 2 , and not to generate the third and the fourth gate signals G 3 , G 4 . The controller  109  calculates the first calculation value Duty for performing the first ON duty ratio change which changes the basis ON duty ratio which is the average value between the ON duty ratio of the first semiconductor circuit and the ON duty ratio of the second semiconductor circuit in the state of the same ON duty ratio difference and the same phase difference; calculates the second calculation value Δduty for performing the first ON duty ratio difference change which changes the ON duty ratio difference between the ON duty ratio of the first semiconductor circuit and the ON duty ratio of the second semiconductor circuit; calculates the third calculation value θ for performing the first phase difference change which changes the phase difference between the phase of the ON period of the first semiconductor circuit and the phase of the ON period of the second semiconductor circuit; and controls the switching operation of the first and the second semiconductor circuits which have the on-off switching function. 
     Alternatively, the DC/DC converter  1  may perform only the step-down operation; only the first and the second semiconductor circuits may have the function of the diode element, and only the third and the fourth semiconductor circuits may have the function of the switching device. In this case, in the upper graphs of  FIG. 12  and  FIG. 14 , the controller  109  is configured to perform the control only in the region where the reactor current IL is negative; in  FIG. 1 , the controller  109  is configured to generate the third and the fourth gate signal G 3 , G 4 , and not to generate the first and the second gate signals G 1 , G 2 . The controller  109  calculates the first calculation value Duty for performing the second ON duty ratio change which changes the basis ON duty ratio which is the average value between the ON duty ratio of the third semiconductor circuit and the ON duty ratio of the fourth semiconductor circuit in the state of the same ON duty ratio difference and the same phase difference; calculates the second calculation value Δduty for performing the second ON duty ratio difference change which changes the ON duty ratio difference between the ON duty ratio of the third semiconductor circuit and the ON duty ratio of the fourth semiconductor circuit; calculates the third calculation value θ for performing the second phase difference change which changes the phase difference between the phase of the ON period of the third semiconductor circuit and the phase of the ON period of the fourth semiconductor circuit; and controls the switching operation of the third and the fourth semiconductor circuits which have the on-off switching function. 
     (3) In each of the foregoing embodiments, there has been explained the case where the first voltage sensor  103  detects the voltage between terminals of the output side smoothing capacitor  108  (the output voltage V 2 ); and the controller  109  controls the output voltage V 2  by execution of the basis duty control which changes the basis ON duty ratio (the first calculation value Duty) so that the detection value of the output voltage V 2  as the high side voltage approaches the output voltage target value V 2 ref as the command value of high side voltage. However, embodiments of the present invention are not limited to the foregoing case. That is to say, the first voltage sensor  103  may be configured to detect the voltage between terminals of the input side smoothing capacitor  11  (the input voltage V 1 ); and the controller  109  may be configured to control the input voltage V 1  by execution of the basis duty control which changes the basis ON duty ratio (the first calculation value Duty) so that the detection value of the input voltage V 1  as the low side voltage approaches the input voltage target value V 1 ref as the command value of low side voltage. In this case, an electric motor may be connected between the input side positive electrode terminal  1   a  and the input side negative electrode terminals  1   b  of low voltage side; a battery may be connected between the output side positive electrode terminal  1   c  and the output side negative electrode terminals  1   d  of high voltage side. 
     (4) In each of the foregoing embodiments, there has been explained the case where in the Δduty control, the controller  109  changes the ON duty ratio difference so that the detection value of the charge and discharge capacitor voltage V 0  approaches the charge and discharge capacitor voltage target value V 0 ref; and in the phase shift control, the controller  109  changes the phase difference so that the detection value of the charge and discharge capacitor voltage V 0  approaches the charge and discharge capacitor voltage target value V 0 ref. However, embodiments of the present invention are not limited to the foregoing case. That is to say, in the Δduty control, the controller  109  may be configured to change the ON duty ratio difference in feedforward based on a set command value; and in the phase shift control, the controller  109  may be configured to change the phase difference in feedforward based on a set command value. 
     (5) In each of the foregoing embodiments, there has been explained the case where the controller  109  changes the basis ON duty ratio so that the detection value of the output voltage V 2  approaches the output voltage target value V 2 ref in the basis duty control. However, embodiments of the present invention are not limited to the foregoing case. That is to say, in the basis duty control, the controller  109  may be configured to change the basis ON duty ratio in feedforward based on a set command value. 
     (6) In each of the foregoing embodiments, there has been explained the case where the controller  109  calculates the first control value SD 1  and the second control value SD 2  based on the first calculation value Duty, the second calculation value Δduty, and the third calculation value θ; and the controller  109  performs on/off control of each switching device by the comparison between the first triangular wave and the first control value SD 1 , and the comparison between the second triangular wave and the second control value SD 2 . However, embodiments of the present invention are not limited to the foregoing case. That is to say, the controller  109  may be configured to realize the ON duty ratio difference, the phase difference, and the basis ON duty ratio in the Δduty control, the phase shift control, and the basis duty control by methods other than the triangular wave comparison. For example, in each of the Δduty control, the phase shift control, and the basis duty control, as explained using  FIG. 7  to  FIG. 10 , the controller  109  may determine the transition order of the operation modes  1  to  4  which are the switching patterns of the switching devices S 1  to S 4 , based on either the step-up operation or the step-down operation, and the step-up ratio or the step-down ratio; and the controller  109  may adjust the length of the period of each determined operation mode  1  to  4 , based on a command value of the ON duty ratio difference, a command value of the phase difference, and a command value of the basis ON duty ratio, which are calculated based on each difference voltage and the like; thereby, the controller  109  may realize the ON duty ratio difference of the command value, the phase difference of the command value, and the basis ON duty ratio of the command value. 
     Various modifications and alterations of this invention will be apparent to those skilled in the art without departing from the scope and spirit of this invention, and it should be understood that this is not limited to the illustrative embodiments set forth herein.