Patent Publication Number: US-9892034-B2

Title: Semiconductor device and operating method thereof

Description:
The present application claims priority under 35 U.S.C. § 119(a) to Korean application number 10-2015-0028785, filed on Mar. 2, 2015, in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety as set forth in full. 
     BACKGROUND 
     1. Technical Field 
     The present invention relates to a semiconductor device and an operation method thereof. Particularly, the present invention relates to a semiconductor device that controls mapping between a logical address requested from a host and a physical address of a memory device, and an operation method thereof. 
     2. Related Art 
       FIG. 1  is a block diagram illustrating a general memory system. The memory system may include a host  1  and a memory device. 
     The host  1  designates a logical address and requests the memory device  2  to perform a read/write operation. The memory device may include a control unit  3 , a memory cell array  4 , and a mapping table. The control unit  3  finds a physical address corresponding to the logical address with reference to the mapping table  30 , and performs the read/write operation by using the physical address of the memory cell array  4 . 
     When the memory device  2  is a NAND flash memory, page mapping, block mapping and the like are performed as a mapping scheme between a logical address and a physical address. 
       FIG. 2  is a diagram for explaining a conventional page mapping technology. 
     In the page mapping technology, the mapping table  30  stores a corresponding relation between a logical page address  10  managed by the host  1  and a physical page address  20  managed by the memory device  2 . 
     To this end, the mapping table  30  should have storage areas  31  corresponding to at least the number p of the logical page addresses  10 . Furthermore, the size of each storage area  31  should have enough data width to identify physical pages form one another. 
     For example, when the total number of physical pages is 2 N , the data width of each storage area  31  is N, and thus, the size of the mapping table  30  is P×N. 
     As described above, the page mapping technology has a problem where as the number of physical pages (i.e., the size of the memory cell array  4 ) increases, the size of the mapping table  30  excessively increases. 
       FIG. 3  is a diagram for explaining a conventional block mapping technology. 
     In the block mapping technology, a page address is hierarchized into a block address and an offset number for management.  FIG. 3  illustrates as an example in which one block includes two pages. 
     An offset number  12  of a logical page address and an offset number  22  of a physical page address correspond identically to each other. Accordingly, it is sufficient if the mapping table  30  stores a corresponding relation between a logical block address  11  and a physical block address  21 . 
     In  FIG. 3 , since the number B of logical block addresses  11  is ½ of the number of logical page addresses, the number of storage areas  31  of the mapping table  30  used in the block mapping technology is reduced to ½ as compared to when the page mapping technology is employed. 
     Furthermore, since the number of physical block addresses  21  is also ½ of the number of physical page addresses, the data width of storage areas  31  of the mapping table  30  is also reduced. For example, when the number of physical pages is 2 N , the number of physical blocks is 2 N-1  and, thus the data width of storage areas  31  is reduced to (N−1). 
     When employing the block mapping technology, the size of the mapping table is reduced as compared to when the page mapping technology is employed. 
     However, since the corresponding relation between the offset number  12  of the logical block address  11  and the offset number  22  of the physical block address  21  is fixed, frequent write requests for the same logical address may also lead to frequent erasures for the corresponding page or memory cell. 
       FIG. 4  is a diagram for explaining a conventional partition recognition mapping technology. 
     In the partition recognition mapping technology, a page address is hierarchized into a partition number and an offset number. 
     A partition number  13  managed by the host  1  and a partition number  23  in the memory device  2  correspond to each other in a one-to-one manner.  FIG. 4  illustrates as an example that two partitions are included. 
     The mapping table  30  is divided into two lower mapping tables  31  and  32  corresponding to the number of partitions. 
     The lower mapping table  31  stores a corresponding relation between an offset number  14  of a page belonging to a logical partition  0  and an offset number  24  of a page belonging to a physical partition  0  according to the page mapping technology. 
     The lower mapping table  32  stores a corresponding relation between an offset number  14  of a page belonging to a logical partition  1  and an offset number  24  of a page belonging to a physical partition  1  according to the page mapping technology. 
     In the partition recognition mapping technology, the number of storage areas of the mapping table is substantially the same as that of the page mapping technology, but the size of each storage area is reduced. As a consequence, the size of the mapping table in the partition recognition mapping technology is smaller than the size of the mapping table in the page mapping technology. 
     However, also in the partition recognition mapping technology, when a request is concentrated on a specific partition, the corresponding partition is quickly consumed as compared with other partitions, thereby reducing efficiency in using the entire storage space. 
     SUMMARY 
     An address mapping device capable of reducing the size of a mapping table and simultaneously reducing the number of erase operations, write operations, and garbage collections by dynamically expanding a physical address region corresponding to a specific logical address region when a request is concentrated on the logical address region, and an operation method thereof are described herein. 
     In one embodiment of the present invention, a semiconductor device includes a mapping table suitable for storing a corresponding relation between a logical address defined on a basis of regions and a physical address defined on a basis of extents, wherein one or more extents are dynamically allocated to one region. 
     In another embodiment of the present invention, an operating method of a semiconductor device includes storing a corresponding relation between a logical address including a region number and a region offset and a physical address including an extent number and an extent offset in first and second tables, wherein the first table stores an extent number index and the extent offset in a first index corresponding to the logical address, and the second table stores the extent number in a second index calculated by the region number and the extent number index, checking a physical address corresponding to a read-requested logical address by referring to the first table and the second table in response to a read request, and updating the first table or the second table in response to a write request. 
     The address mapping device and the operation method thereof according to the present technology are employed, so as to reduce the size of a mapping table. When a request is concentrated on a specific logical address region, a physical address region corresponding to the logical address region is dynamically expanded, so as to reduce the number of erase operations, write operations, and garbage collections. 
     Consequently, when a storage space is limited as with a mobile device it is possible to reduce the waste of the storage space due to an increase in the size of a mapping table and to substantially prevent performance degradation due to frequent background operations. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Features, aspects, and embodiments are described in conjunction with the attached drawings, in which: 
         FIG. 1  is a block diagram illustrating a memory system; 
         FIG. 2  to  FIG. 4  are diagrams explaining conventional address mapping technologies; 
         FIG. 5  is a diagram explaining an address mapping technology according to an embodiment of the present invention; 
         FIG. 6  is a flowchart illustrating a read operation when using an address mapping technology according to an embodiment of the present invention; 
         FIG. 7  is a flowchart illustrating a write operation when using an address mapping technology according to an embodiment of the present invention; 
         FIG. 8  is a flowchart illustrating an extent allocation operation of  FIG. 7 ; 
         FIG. 9  is a flowchart illustrating the execution of a write operation  FIG. 8 ; and 
         FIG. 10  is a graph illustrating the effects of the present invention. 
     
    
    
     DETAILED DESCRIPTION 
     Hereinafter, a semiconductor device and an operation method thereof according to the present invention will be described in detail with reference to the accompanying drawings through exemplary embodiments. 
       FIG. 5  is a diagram explaining a mapping technology according to an embodiment of the present invention. 
     In the present invention, a logical address  100  managed by a host  1  is hierarchized into a region number  110  and a region offset  120 , and a physical address  200  managed by a memory device  2  is hierarchized into an extent number  210  and an extent offset  220 . Hereinafter, an address indicates a page address. 
     In the present invention, a mapping table  300  includes a first table  310  and a second table  320 . 
     The second table  320  stores a corresponding relation between the region number  110  and an extent number  321 . In the present embodiment, an index (a second index) of the second table  320  is divided in units of the maximum number of extents allocable to a region. 
     Accordingly, when a region number is known, the range of extents allocable to a corresponding region is decided. As described below, the allocation of extents to a region may be dynamically controlled. 
     In order to check the extent number  210  corresponding to the region number  110  by using a logical address, an extent number index  311  is required in addition to the region number  110 . The extent number index  311  indicates a relative position of an extent within the range which may be associated with the region number  110 . 
     For example, the region number  110  is A (a bit number is 1), and the maximum number of extents allocable to a region is N (=2 i ), and the extent number index  311  is E, the second index corresponding to these values may be calculated as A×2 i +E. 
     The extent number index  311  is stored in the first table  310 . The first table  310  stores the extent number index  311  and an extent offset  312  according to a first index corresponding to each logical address. 
     When the region number  110  is A and the region offset  120  is B (a bit number is k), the first index corresponding to these values may be calculated as A×2 k +B. 
     The extent offset  220  of the physical address  200  corresponding to the logical address  100  may be known only by referring to the first table  310 , but the extent number  210  of the physical address  200  may be known by referring to both the first table  310  and the second table  320 . 
       FIG. 6  is a flowchart illustrating a read operation when using an address mapping technology according to an embodiment of the present invention. 
     First, a region number and a region offset are calculated in a read-requested logical address (S 110 ). 
     Next, the first table  310  is referred to using a first index calculated from the region number and the region offset, and an extent number index and an extent offset are decided (S 120 ). 
     Then, the second table  320  is referred to using a second index calculated from the region number, the maximum number of extents allocable to a region, and the extent number index, and an extent number is decided (S 130 ). 
     Last, a physical address is decided from the extent number and the extent offset and data of the physical address is read (S 140 ). 
       FIG. 7  is a flowchart illustrating a write operation when using the address mapping technology according to an embodiment of the present invention. 
     First, in order to store data of a write-requested logical address, it is determined whether a new free page is necessary (S 210 ). 
     When a new free page is not necessary, a write operation is performed for a free page selected from existing free pages (S 400 ). 
     When a new free page is necessary, it is determined whether the size of an extent allocated to a region is smaller than a critical point (S 220 ). In the present embodiment, the value of the critical point is a maximum size of an extent allocable to a region, and is twice as large as the size of the region. 
     When the size of the extent allocated to the region is smaller than the critical point, it is determined whether there are extra extents allocable to the corresponding region (S 230 ) and, other a garbage collection operation is performed (S 500 ). 
     When there are extra extents as the determination result of step S 230 , the extra extents are allocated to the corresponding region (S 300 ), and the write operation is performed (S 400 ). The write operation is performed for a free page existing in an extent newly allocated to the region. 
     When there are no extra extents as the determination result of step S 230 , the garbage collection operation is performed (S 500 ). 
     In the present embodiment, since the critical point is substantially the same as the maximum number of extents allocable to the region, when Yes is determined in step S 220 , Yes is also determined in step S 230 . However, when No is determined in step S 220 , No is also determined in step S 230 . 
     The garbage collection operation in step S 500  may be performed by selecting an extent in which the number of valid pages is minimal. The garbage collection operation in step S 500  may be performed by moving the valid page to another page of the selected extent or a page of another extent corresponding to substantially the same region number and erasing a block including only an invalid page. 
     Even when the garbage collection is performed (S 500 ), information in the mapping table  300  should be updated. A mapping table update operation in the garbage collection may be easily known from a mapping table update operation in a write operation. That is, when the extra extents are allocated (S 300 ) or the write operation is performed (S 400 ), it is necessary to update information in the mapping table  300 . This will be described with reference to  FIG. 8  and  FIG. 9 . 
       FIG. 8  is a flowchart illustrating in detail an extent allocation operation of  FIG. 7 . 
     First, an extent is selected from allocable extra extents in a region number of a write-requested logical address, and a second index corresponding to the number of the selected extent is checked in the second table  320  (S 310 ). 
     Next, an extent number index is calculated from the checked second index, the region number, and the maximum number of extents allocable to each region, and the extent number index is updated in the first table  310  by using a first index corresponding to the region number and a region offset (S 320 ). 
       FIG. 9  is a flowchart illustrating the execution of the write operation of  FIG. 8 . 
     When a free page is selected for the write operation, the first index corresponding to the region number and the region offset is calculated by an extent offset corresponding to the free page, and the extent offset is updated in the first table  310  by using the first index (S 410 ). 
     Since the free page has been selected from extents corresponding to the write-requested region, an extent number has already been set to correspond to the write-requested region. 
     Then, write-requested data is written in the free page (S 420 ). 
       FIG. 10  is a graph illustrating the effects of the present invention. 
     The experiment of  FIG. 10  has been performed using eMMC with a capacity of 32 GB, wherein the size of a page is 16 KB, the size of a block is 2 MB, the size of an extent is 16 MB, and the size of a region is 128 MB. 
     In the experiment substantially the same read/write operations have been performed for employing the page mapping technology and employing the mapping technology according to the present invention. 
     As a result of the experiment, when employing the conventional page mapping technology, the number of erasures having been performed is 19,444, but when employing the mapping technology according to the present invention, the number of erasures is reduced to 13,990. 
     The erase operation has been performed in a garbage collection operation, and the operation performance has been improved as the number of garbage collections is reduced. 
     In the experiment, since the number of physical pages is 2 M (=32 GB/16 KB=2 14 ), the size of a mapping table is 14×L when the number of all logical addresses is L. 
     In the experiment, the number of extents is 2 K (=32 G/16 M), and a bit number of an extent number is 11 (=log 2 2K), and a bit number of an extent offset is 3 (=14-11), and a maximum value of an extent offset index is 16 (=2×128 MB/16 MB), and a bit number of an extent number index is 4. 
     Accordingly, the size of the first table  310  is 7×L bits and the size of the second table  320  is (the number of regions)×11 bits. When the entire number of logical page addresses is substantially the same as the entire number of physical page addresses, the number of regions (32 GB/128 MB) is significantly smaller than the number (32 GB/16 KB) of all logical addresses. 
     As a consequence, when using the concept outlined in the present invention, the size of the mapping table is reduced to about ½ as compared to when using the conventional page mapping technology. 
     While certain embodiments have been described above, will be understood to those skilled in the art that the embodiments are examples only. Accordingly, the semiconductor device and the operation method thereof described herein should not be limited based on the described embodiments. Rather, the encoding device, the semiconductor device and the operation method thereof described herein should only be limited in light of the claims that follow when taken in conjunction with the above description and accompanying drawings.