Patent Publication Number: US-5424965-A

Title: Multiplication circuit for multiplying analog values

Description:
FIELD OF THE INVENTION 
     This invention relates to a multiplication circuit. 
     BACKGROUND OF THE INVENTION 
     In recent years, there have been complaints about the limitations of a digital computer because of the exponential increase in the amount of money needed for investment in equipment relating to minute processing technology. Thus an analog computer has been receiving a lot of attention. However, in an analog computer, a multi-valued register or memory is needed to store the data and such means have not been realized yet. 
     SUMMARY OF THE INVENTION 
     The present invention is invented so as to solve the conventional problems described above and has a purpose to provide a multiplication circuit capable of storing an analog computer&#39;s data. 
     A multiplication circuit according to the present invention converts voltage levels into a time domain by using a charged voltage of an RC circuit and resistors time as a clock number at a digital counter. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a circuit diagram showing a first embodiment of a multiplication circuit according to the present invention. 
     FIG. 2 is a circuit diagram showing a second embodiment of a multiplication circuit according to the present invention. 
    
    
     PREFERRED EMBODIMENT OF THE INVENTION 
     Hereinafter an embodiment of a multiplication circuit according to the present invention is described with reference to the attached drawings. 
     In FIG. 1, a multiplication circuit has a multiplexer MUX for selectively outputting analog data from D 1  to D n  which is to be multiplied. The output of multiplexer MUX is connected to a comparator COMP as a non-inverted input. The first RC circuit RC 1  is connected with an inverted input of comparator COMP and a stepwise starting signal RV 1  is input to RC 1 . RC 1  is composed of a resistor R 1  connected at a first terminal with RV 1 . Capacitor C 1  is connected at a first terminal with a second terminal of R 1  and a ground potential at the second terminal. A junction point of C 1  and R 1  is connected with the inverting input of comparator COMP. 
     Comparator COMP outputs a &#34;0&#34; when its input (D k  -RV 1 ) is smaller than 0, and outputs an active &#34;1&#34; when (D k  -RV 1 ) is greater than 0. 
     An output of COMP and RV 1  are input to a logical gate G having the function of (COMPxRV 1 ). The output of logical gate G is input to a counter CNT as enable signal E. Counter CNT counts during a period from the time when RV 1  becomes &#34;1&#34; to the time when the output to COMP becomes &#34;1&#34; . Counter CNT has a Read/Write switching input R/W, a clock input CLK and count data output CD. The following signal definitions are predetermined. 
     
                       TABLE 1                                                     
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When R/W is equal to 1, then counter CNT counts decrement-                
ally.                                                                     
When R/W is equal to 0, then counter CNT counts incrementally.            
Counter CNT counts the changes from 0 to 1 of clock CLK.                  
When a counter value of counter CNT is positive, then an output           
is 1.                                                                     
When a counter value of counter CNT is 0, then an output is               
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0.                                                                        
 
    
     When R/W is equal to 0, a selected one of analog data from D 1  to D n , which is defined as D k , is selected by multiplexer MUX. RV 1  is defined as &#34;1&#34; and is input to the inverted input of COMP. The electric potential of the inverted input decreases as C 1  is charged. When (D k  -RV 1 ) becomes &#34;0&#34; , COMP outputs a holding signal H, which is equal to 1. RV 1  is input to gate G simultaneously with the input of RC 1 . Counter CNT starts the counting of clock CLK and increments the count value. Clock CLK is a pulse train of a predetermined frequency and the final count value of counter CNT corresponds to a difference in time from the time of the inputting of RV 1  to time when (D k  -RV 1 ) becomes &#34;0&#34;. 
     Here, if the voltage of inverted input of comparator COMP is defined as V in  and the time corresponding to D k  is defined as t k , then the following formulas are obtained. 
     V in  =RV 1  exp(-t k  /R 1  C 1  ; and 
     t k  =-R 1  C 1  log(D k  /RV 1 ) 
     Finishing the first counting, holding the count values, selecting a new data D k+1 , and defining RV 1  as being equal to 1, then time t +1 , corresponding to D k+1  can be added to t k . Time can be obtained from the following formula, which is stored in counter CNT. 
     
         t.sub.k +t.sub.k+1 =-R.sub.1 C.sub.1 log{D.sub.k ×D.sub.k+1 /(RV.sub.1).sup.2 } 
    
     The formula is the time that corresponds to the multiplication result of D k  ×D k+1 . Storing the time as a count value is equivalent to holding the actual calculation result. 
     It is possible to perform the same calculation for any number of data, and it is possible to obtain a multiplication result of all data from D 1  to D k . 
     The second RC circuit RC 2  has the same characteristics as RC 1 . RC 2  is connected with output CD in order to read a count value of counter CNT. RC 2  includes a resistor R 2 , and a capacitor C 1  connected at the first terminal through a transistor Tr and a ground potential at the second terminal. A gate of Tr is connected with output CD. Assuming that R/W is equal to 1, the count value is decreased. When the count value is equal to 0, output CD becomes 0 and Tr is cut-off. C 2  is charged during a period from when RV 1  is equal to 1 to when CD is equal to 0. The charge voltage at the end of charging becomes an analog data output D out  corresponding to the total time. An analog data is calculated as a result of multiplication. 
     FIG. 2 shows a second embodiment in which the first and the second RC circuits are the same circuits. 
     When R/W is equal to 0, CD is equal to 1 and Tr is conductive. When RV is equal to 1, C is charged through R and Tr. When a count is stopped (i.e., when H is equal to 1), a time corresponding to data D k  is added to the count value. When R/W is equal to 1, the count value is decreased. When the value becomes equal to 0, CD is equal to 0. Then Tr is cut-off and the charged voltage of C becomes an analog data output D out . 
     In the second embodiment, the RC circuit is mutual so that it is possible to prevent a decline in accuracy of calculation which could be caused by different characteristics of RC circuits. 
     As mentioned above, a multiplication circuit according to the present invention converts voltage levels into the time domain by using the charge voltage of an RC circuit and registers time as a number of clock pulses at a digital counter, so that it is possible to provide a multiplication circuit capable of storing data.