Patent Publication Number: US-2021193823-A1

Title: Semiconductor device and method for fabricating the same

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This application is a division of U.S. application Ser. No. 16/378,584 filed Apr. 9, 2019, and incorporated herein by reference in its entirety. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The invention relates to a method for fabricating semiconductor device, and more particularly, to a method of using sidewall image transfer (SIT) technique to form fin-shaped structures. 
     2. Description of the Prior Art 
     With increasing miniaturization of semiconductor devices, it is crucial to maintain the efficiency of miniaturized semiconductor devices in the industry. However, as the size of the field effect transistors (FETs) is continuously shrunk, the development of the planar FETs faces more limitations in the fabricating process thereof. On the other hand, non-planar FETs, such as the fin field effect transistor (Fin FET) have three-dimensional structure, not only capable of increasing the contact to the gate but also improving the controlling of the channel region, such that the non-planar FETs have replaced the planar FETs and become the mainstream of the development. 
     The current method of forming the Fin FETs is forming a fin structure on a substrate primary, and then forming a gate on the fin structure. The fin structure generally includes the stripe-shaped fin formed by etching the substrate. However, under the requirements of continuous miniaturization, the width of each fin, as well as the pitch between fins have to be shrunk accordingly. Thus, the fabricating process of the Fin FETs also faces more challenges and limitations. For example, the fabricating process is limited by current mask and lithography techniques, such that it has problems to precisely define the position of the fin structure, or to precisely control the etching time, thereby leading to the fin collapse or over-etching issues, and seriously affecting the efficiency of the fin structure. 
     SUMMARY OF THE INVENTION 
     According to an embodiment of the present invention, a method for fabricating semiconductor device includes: forming a first semiconductor layer and an insulating layer on a substrate; removing the insulating layer and the first semiconductor layer to form openings; forming a second semiconductor layer in the openings; and patterning the second semiconductor layer, the insulating layer, and the first semiconductor layer to form fin-shaped structures. 
     According to another aspect of the present invention, a semiconductor device includes a fin-shaped structure on a substrate, wherein the fin-shaped structure further includes a first semiconductor layer on the substrate, a second semiconductor layer on the first semiconductor layer, an insulating layer on the second semiconductor layer, and a third semiconductor layer on the insulating layer. 
     These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIGS. 1-10  illustrate a method for fabricating a semiconductor device according to an embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION 
     Referring to  FIGS. 1-10 ,  FIGS. 1-10  illustrate a method for fabricating a semiconductor device according to an embodiment of the present invention. As shown in  FIG. 1 , a substrate  12  such as a semiconductor substrate is provided, in which the substrate  12  is preferably made of a group III-V semiconductor material or more specifically made of bulk gallium nitride (GaN). Next, a semiconductor layer  14  and an insulating layer  16  are sequentially formed on the surface of the substrate  12 , and a patterned mask  18  such as a patterned resist is formed on the insulating layer  16 , in which the patterned mask  18  includes a plurality of openings  20  exposing the surface of the insulating layer  16 . In this embodiment, the semiconductor layer  14  is preferably made of a group III-V semiconductor material while the semiconductor layer  14  and the substrate  12  are preferably made of different materials. Preferably, the semiconductor layer  14  is made of metal oxide including but not limited to for example aluminum gallium nitride (AlGaN) and the insulating layer  16  is made of metal oxides including but not limited to for example aluminum oxide (Al 2 O 3 ). 
     Next, as shown in  FIGS. 1-2 , an etching process is conducted by using the patterned mask  18  as mask to remove part of the insulating layer  16  and part of the semiconductor layer  14  to expose part of the substrate  12  surface for forming a patterned insulating layer  16  and a patterned semiconductor layer  14  on the substrate  12 . It should be noted that even though the etching process conducted at this stage preferably does not remove any of the substrate  12  so that the top surface of the substrate  12  is even with the bottom of the semiconductor layer  14 , according to another embodiment of the present invention, it would also be desirable to remove part of the insulating layer  16  and part of the semiconductor layer  14  and then remove part of the substrate  12  so that the top surface of the remaining substrate  12  is slightly lower than the bottom of the semiconductor layer  14 , which is also within the scope of the present invention. Next, the patterned mask  18  is stripped to expose the top of the patterned insulating layer  16  and openings from the patterned mask  18  are then transferred to form openings  20  in the patterned insulating layer  16  and patterned semiconductor layer  14 . 
     Next, as shown in  FIG. 3 , a growth process is conducted to form another semiconductor layer  22  to fill the openings  20  while extending upward to cover the top surface of the insulating layer  16 . It should be noted that since the top surface of the semiconductor layer  22  is non-planar immediately after the growth process, it would be desirable to conduct a planarizing process such as chemical mechanical polishing (CMP) process to remove part of the semiconductor layer  22  so that the top surface of the remaining semiconductor layer  22  becomes a planar surface. In this embodiment, the semiconductor layer  22  is preferably made of group III-V semiconductor material while the semiconductor layers  22  and  14  are preferably made of different materials but semiconductor layer  22  and the substrate  12  are made of same material. For instance, the substrate  12  and the semiconductor layer  22  are preferably made of GaN. 
     Next, as shown in  FIG. 4 , a hard mask  24  and another hard mask  26  are sequentially formed on the surface of the semiconductor layer  22 , and a plurality of mandrels  28  are formed on the hard mask  26 . In this embodiment, the hard masks  24 ,  26  are preferably made of different materials while the two masks  24 ,  26  could all be selected from the group consisting of silicon oxide (SiO 2 ), silicon nitride (SiN), silicon oxynitride (SiON), and silicon carbon nitride (SiCN). The formation of the mandrels  28  could be accomplished by forming at least a material layer (not shown) to cover the entire surface of the hard mask  26 , and a pattern transfer process is conducted by using etching process to remove part of the material layer to form a plurality of patterned materials serving as mandrels  28 . Preferably, the mandrels  28  could include materials such as but not limited to for example amorphous silicon, polysilicon, SiO 2 , or SiN. Preferably, each of the mandrels  28  share equal widths in this embodiment and the distance of pitch between the mandrels  28  are preferably the same. 
     Next, as shown in  FIG. 5 , a cap layer (not shown) is formed to cover the surfaces of the mandrels  28  and the hard mask  26 , and an etching back process is conducted to remove part of the cap layer to form spacers  30  adjacent to each of the mandrels  28 . In this embodiment, the spacers  30  could include dielectric materials such as but not limited to for example silicon oxide (SiO 2 ), silicon nitride (SiN), silicon oxynitride (SiON), and/or silicon carbon nitride (SiCN). It should be noted that since the sidewalls of the semiconductor layer  22  need to be aligned with sidewalls of the insulating layer  16  and semiconductor layer  14  underneath when patterning process is conducted to form fin-shaped structures in the later process, a combined width of a mandrel  28  and adjacent spacer  30  is preferably equal to a width of the patterned insulating layer  16  and/or patterned semiconductor layer  14  underneath. In other words, the sidewalls of the spacer  30  adjacent to two sides of each of the mandrels  28  are aligned with left and right sidewalls of the insulating layer  16  and semiconductor layer  14  underneath. 
     Next, as shown in  FIG. 6 , an etching process is conducted to remove the mandrels  28  so that only spacers  30  are remained on the hard mask  26 . 
     Next, as shown in  FIG. 7 , the pattern of the spacers  30  is then transfer to the stacked materials underneath. For instance, it would be desirable to conduct an etching process by using the spacers  30  as mask to remove the hard mask  26 , the hard mask  24 , the semiconductor layer  22 , the insulating layer  16 , the semiconductor layer  14 , and even part of the substrate  12  not covered by the spacers  30  to form fin-shaped structures  32 , and the spacers  30  are removed thereafter. It should be noted that the fin-shaped structures  32  formed at this stage if viewed from a top view perspective are preferably ring-shaped structures on the substrate  12 . 
     Next, as shown in  FIG. 8 , a fin cut process is conducted by using a patterned mask (not shown) to divide the ring-shape fin-shaped structures  32  into stripe patterns not contacting each other through etching process. Since the fin cut process cannot remove part of the fin-shaped structures  32  on the substrate  12  completely, part of the remaining fin-shaped structures or bumps  34  could be formed on the substrate  12  after the fin cut process. 
     Next, as shown in  FIG. 9 , an insulating layer  36  preferably made of silicon oxide is formed on the fin-shaped structures  32  to cover the substrate  12 , bumps  34 , and fin-shaped structures  32  entirely and a top surface of the insulating layer  36  is higher than the top surface of the fin-shaped structures  32 , and a planarizing process such as chemical mechanical polishing (CMP) process is conducted to remove part of the insulating layer  36 , hard mask  26 , and hard mask  24  so that the top surface of the remaining insulating layer  36  is substantially even with the top surface of the semiconductor layer  22 . Next, an ion implantation process  38  is conducted to implant n-type or p-type dopants into the semiconductor layer  22  to form well regions. 
     Next, as shown in  FIG. 10 , another etching process is conducted to remove part of the insulating layer  36  so that the top surface of the remaining insulating layer  36  is between the top surface and bottom surface of the semiconductor layer  22  as the tip of the semiconductor layer  22  of each of the fin-shaped structures  32  is exposed, in which the remaining insulating layer  36  preferably serving as a shallow trench isolation (STI)  40  while the exposed semiconductor layer  22  becomes channel regions for the transistors afterwards. Next, a standard transistor fabrication process could be conducted by forming a gate dielectric layer  42  and a gate material layer or gate electrode  44  made of polysilicon on the fin-shaped structures  32 , forming spacers adjacent to the sidewalls of the gate electrode  44 , and then forming source/drain regions in the fin-shaped structures  32  adjacent to two sides of the gate electrode  44 . This completes the fabrication of a semiconductor device according to an embodiment of the present invention. 
     Referring again to  FIG. 10 ,  FIG. 10  also illustrates a structural view of a semiconductor device according to an embodiment of the present invention. As shown in  FIG. 10 , the semiconductor device includes a plurality of fin-shaped structures  32  disposed on the substrate  12 , in which each of the fin-shaped structures  32  further includes a semiconductor layer  46  on the substrate  12 , a semiconductor layer  14  on the semiconductor layer  46 , an insulating layer  16  on the semiconductor layer  14 , and a semiconductor layer  22  on the insulating layer  16 . The semiconductor device further includes a STI  40  disposed around the fin-shaped structures  32 , a gate dielectric layer  42  disposed on the surface of the semiconductor layer  22 , and a gate electrode  44  or gate structure disposed on the gate dielectric layer  42 . In this embodiment, the left and right sidewalls of the semiconductor layer  46  are aligned with left and right sidewalls of the semiconductor layer  14 , the left and right sidewalls of the insulating layer  16 , and the left and right sidewalls of the semiconductor layer  22 , the top surface of the STI  40  is preferably between the top and bottom surfaces of the semiconductor layer  22 , and the STI  40  surrounds the semiconductor layer  46 , the semiconductor layer  14 , the insulating layer  16 , and part of the semiconductor layer  22 . 
     In this embodiment, the semiconductor layer  46  protruding above the surface of the substrate  12 , the semiconductor layer  22  serving as the channel region for the transistor device, and the substrate  12  are preferably made of same material such as a group III-V semiconductor material. Preferably, the substrate  12 , the semiconductor layer  46 , and the semiconductor layer  22  are made of GaN in this embodiment, in which the topmost semiconductor layer  22  serving as the channel region could include p-type or n-type dopants while the semiconductor layer  46  and the substrate  12  preferably not including any dopants. The semiconductor layer  14  is preferably made of a group III-V semiconductor layer different from the semiconductor layers  22 ,  46 . Preferably, the semiconductor layer  14  is made of AlGaN in this embodiment and the insulating layer  16  between the semiconductor layers  14 ,  22  is preferably made of Al 2 O 3 . 
     Overall, the present invention discloses an approach of using group III-V semiconductor material as a main material for fabricating fin-shaped structures. The fabrication of the fin-shaped structures is accomplished by first forming a first semiconductor layer made of AlGaN and an insulating layer made of Al 2 O 3  on the substrate, conducting a pattern transfer process to remove part of the insulating layer and part of the first semiconductor layer to form a plurality of openings, forming a semiconductor layer made of GaN in the openings, and then conducting a sidewall image transfer (SIT) process with the aid of mandrels and spacers to pattern the second semiconductor, the insulating layer, and the first semiconductor layer for forming a plurality of fin-shaped structures. 
     Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.