Patent Publication Number: US-2023154979-A1

Title: Method of manufacturing semiconductor devices and semiconductor devices

Description:
RELATED APPLICATION 
     This application is a divisional of U.S. patent application Ser. No. 17/104,019, now U.S. Pat. No. 11,557,649, filed Nov. 25, 2020, which claims priority to U.S. Provisional Patent Application No. 63/045,433 filed Jun. 29, 2020, the entire contents of which are incorporated herein by reference. 
    
    
     BACKGROUND 
     With increasing down-scaling of integrated circuits and increasingly demanding requirements of speed of integrated circuits, transistors need to have higher drive currents with increasingly smaller dimensions. Three dimensional field-effect transistors (FETs) were thus developed. Three dimensional (3D) FETs include vertical semiconductor nanostructures (such as fins, nanowires, nanosheets etc.) disposed over a substrate. The semiconductor nanostructures are used to form source and drain regions, and channel regions between the source and drain regions. Shallow trench isolation (STI) regions are formed to define the semiconductor nanostructures. The 3D FETs also include gate stacks, which are formed on the sidewalls and the top surfaces of the semiconductor fins or on the all sides of nanowires, nanosheets. Since 3D FETs have a three-dimensional channel structure, ion implantation processes to the channel require extra care to reduce any geometrical effects. With increasing down-scaling of integrated circuits, the spacing between nearby devices is decreasing and the different threshold voltage devices are coming closer together causing threshold voltage shift due to various process and/or structural issues. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The present disclosure is best understood from the following detailed description when read with the accompanying figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. 
         FIG.  1 A  shows a cross sectional view,  FIG.  1 B  shows a perspective view and  FIG.  1 C  is another cross sectional view of a semiconductor device according to an embodiment of the present disclosure. 
         FIGS.  2 A,  2 B,  2 C,  2 D,  2 E and  2 F  show cross sectional views of various stages of a sequential manufacturing process of a semiconductor device according to an embodiment of the present disclosure. 
         FIGS.  3 A,  3 B,  3 C,  3 D,  3 E and  3 F  show cross sectional views of various stages of a sequential manufacturing process of a semiconductor device according to an embodiment of the present disclosure.  FIG.  3 G  shows a process flow of manufacturing a semiconductor device according to an embodiment of the present disclosure. 
         FIG.  4 A  shows gate structures of multiple FETs with different threshold voltages according to embodiments of the present disclosure.  FIGS.  4 B and  4 C  show various work function adjustment material layers and high-k gate dielectric layers for multiple FETs with different threshold voltages according to embodiments of the present disclosure. 
         FIG.  5 A  shows a plan view (layout) of a CMOS circuit,  FIG.  5 B  shows a cross sectional view corresponding to area A 1  of  FIG.  5 A , and  FIG.  5 C  shows an enlarged view of area B 1  of  FIG.  5 B  according to an embodiment of the present disclosure. 
         FIG.  6 A  shows a plan view (layout) of a CMOS circuit,  FIG.  6 B  shows a cross sectional view corresponding to area A 1  of  FIG.  6 A , and  FIG.  6 C  shows an enlarged view of area B 1  of  FIG.  6 B  according to an embodiment of the present disclosure. 
         FIGS.  7 A,  7 B,  7 C,  7 D,  7 E,  7 F,  7 G and  7 I  show various stage of a manufacturing process of a semiconductor device according to embodiments of the present disclosure. 
         FIGS.  8 A,  8 B,  8 C,  8 D,  8 E,  8 F,  8 G,  8 H,  8 I,  8 J,  8 K and  8 L  show various views of a sequential manufacturing process of a semiconductor device according to embodiments of the present disclosure. 
         FIGS.  9 A,  9 B,  9 C,  9 D,  9 E,  9 F and  9 G  show cross sectional views of various stages of a sequential manufacturing process of a semiconductor device according to embodiments of the present disclosure. 
         FIGS.  10 A,  10 B,  10 C,  10 D and  10 E  show cross sectional views of various stages of a sequential manufacturing process of a semiconductor device according to embodiments of the present disclosure. 
         FIGS.  11 A,  11 B,  11 C,  11 D,  11 E,  11 F,  11 G,  11 H,  11 I,  11 J,  11 K,  11 L,  11 M,  11 N,  11 O,  11 P,  11 Q,  11 R,  11 S,  11 T,  11 U ,  11 V and  11 W shows various views of semiconductor devices according to embodiments of the present disclosure. 
         FIG.  12    shows a static random access memory (SRAM) layout according to embodiments of the present disclosure. 
         FIG.  13    shows various circuit layouts according to embodiments of the present disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     It is to be understood that the following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, dimensions of elements are not limited to the disclosed range or values, but may depend upon process conditions and/or desired properties of the device. Moreover, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed interposing the first and second features, such that the first and second features may not be in direct contact. Various features may be arbitrarily drawn in different scales for simplicity and clarity. In the accompanying drawings, some layers/features may be omitted for simplification. 
     Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature&#39;s relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. In addition, the term “made of” may mean either “comprising” or “consisting of.” Further, in the following fabrication process, there may be one or more additional operations in between the described operations, and the order of operations may be changed. In the present disclosure, a phrase “one of A, B and C” means “A, B and/or C” (A, B, C, A and B, A and C, B and C, or A, B and C), and does not mean one element from A, one element from B and one element from C, unless otherwise described. In the entire disclosure, a source and a drain are interchangeably used, and a source/drain refers to one of or both of the source and the drain. In the following embodiments, materials, configurations, dimensions, processes and/or operations as described with respect to one embodiment (e.g., one or more figures) may be employed in the other embodiments, and detailed description thereof may be omitted. 
     Disclosed embodiments relate to a semiconductor device, in particular, a gate structure of a field effect transistor (FET) and its manufacturing method. The embodiments such as those disclosed herein are generally applicable not only to planar FETs but also to a fin FET (FinFET), a double-gate FET, a surround-gate FET, an omega-gate FET or a gate-all-around (GAA) FET (such as a lateral gate-all-around FET or a vertical gate-all-around FET), and/or nanowire transistors, nanosheet transistors, nano-forksheet transistors, nano-slab transistors or any suitable device having one or more work function adjustment material (WFM) layers in the gate structure. 
     With technology scaling down, semiconductor devices (e.g., transistors) are disposed much closer to each other, and the proximity effects (damage to nearby devices) are concerned. In FET structures, building multiple Vt devices with low Vt is very crucial for low power consumption and boosting device performance. Composition and thickness of metal gate films play a crucial role in defining the device work function. Multiple FETs having different threshold voltages can be realized by adjusting materials and/or thicknesses of a gate dielectric layer and/or one or more work function adjustment material layers (WFMs) disposed between a gate dielectric layer and a body metal gate electrode layer (e.g., a W layer). Further, a high-k dipole layer is used to form different Vt devices. When different high-k dipole layers are used as a gate dielectric layer in nearby FET devices, a cross contamination (e.g., diffusion of La) between different Vt devices using different gate dielectric layers may be a problem. 
     The present disclosure relates to a method and a device structure for preventing La diffusion across a boundary of different Vt devices. 
       FIGS.  1 A and  1 C  show cross sectional views and  FIG.  1 B  is a perspective view of a semiconductor device according to an embodiment of the present disclosure. 
     In some embodiments, a semiconductor device includes a gate stack  80  disposed over a channel region of a fin structure  20 . The gate stack  80  includes an interfacial layer  81 , a gate dielectric layer  82 , a first conductive layer  83  as a cap layer, a second conductive layer  84  as a first barrier layer, a work function adjustment material layer or a work function adjustment layer (a WFM layer)  86 , a glue layer  87  and a body gate electrode layer  88  as shown in  FIG.  1 A . In some embodiments, the fin structure  20  is provided over a substrate  10  and protrudes from an isolation insulating layer  30 . Further, gate sidewall spacers  46  are disposed on opposite side faces of the gate stack  80  and one or more dielectric layers  50  are formed to cover the gate sidewall spacers  46 . In some embodiments, a piece of insulating material  42  is disposed between the gate sidewall spacer  46  and the isolation insulating layer  30 . Further, as shown in  FIG.  1 B , source/drain epitaxial layers  60  are formed over recessed fin structures. Although  FIG.  1 A  shows two fin structures and  FIG.  1 B  shows three fin structures, the number of fin structures is not limited to those shown in  FIGS.  1 A and  1 B . 
     In some embodiments, a channel region of the fin structure is made of Si for an n-type FET and is made of SiGe for a p-type FET. A Ge concentration of SiGe is in a range from about 20 atomic % to 60 atomic % in some embodiments, and is in a range from about 30 atomic % to 50 atomic % in other embodiments. In some embodiments, the channel region of the n-type FET includes Ge in an amount smaller than the SiGe channel of the p-type FET. In other embodiments, the channel regions of a p-type FET and an n-type FET are both made of Si or a compound semiconductor. 
     In some embodiments, the first conductive layer  83  includes a metal nitride, such as WN, TaN, TiN and TiSiN. In some embodiments, TiN is used. The thickness of the first conductive layer  83  is in a range from about 0.3 nm to about 30 nm in some embodiments, and is in a range from about 0.5 nm to about 25 nm in other embodiments. In some embodiments, the first conductive layer  83  is crystalline having, e.g., columnar crystal grains. In some embodiments, the first conductive layer  83  is not formed. In some embodiments, the first conductive layer  83  is formed and then removed after an annealing operation with a wet etching process. 
     In some embodiments, the second conductive layer  84  includes a metal nitride, such as WN, WCN, Ru, TiAlN, AN, TaN, TiN and TiSiN. In some embodiments, TaN is used. The thickness of the second conductive layer  84  is in a range from about 0.3 nm to about 30 nm in some embodiments, and is in a range from about 0.5 nm to about 25 nm in other embodiments. In some embodiments, the second conductive layer  84  functions as a barrier layer or an etch stop layer. In some embodiments, the second conductive layer  84  is thinner than the first conductive layer  83 . In some embodiments, the second conductive layer  84  is not formed. 
     In some embodiments, the WFM layer  86  is made of a conductive material such as a single layer of TiN, WN, WCN, Ru, W, TaAlC, TiC, TaAl, TaC, Co, Al, TiAl, or TiAlC, or a multilayer of two or more of these materials. For an n-type FET having a Si channel, an aluminum-containing layer, such as TiAl, TiAlC, TaAl and/or TaAlC and optionally one or more of TaN, TiN, WN, TiC, WCN, MoN and/or Co formed thereunder is used. For a p-type FET having a SiGe channel, one or more of TaN, TiN, WN, TiC, WCN, MoN and/or Co and one or more of TiAl, TiAlC, TaAl and TaAlC formed thereon is used. 
     In some embodiments, the glue layer  87  is made of one or more of TiN, Ti, and Co. In some embodiments, the body gate electrode layer  88  includes one or more layers of conductive material, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, WCN, Ru, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and/or combinations thereof. 
     As set forth above, the first conductive layer  83  and the second conductive layer  84  are not formed in some embodiments. In such a case, one or more WFM layers are formed directly on the gate dielectric layer  82 . 
       FIGS.  2 A- 3 F  show cross sectional views of various stages of a sequential manufacturing process of the semiconductor device according to an embodiment of the present disclosure.  FIG.  3 G  shows a process flow of manufacturing a semiconductor device according to an embodiment of the present disclosure. It is understood that in the sequential manufacturing process, one or more additional operations can be provided before, during, and after the stages shown in  FIGS.  2 A- 3 F , and some of the operations described below can be replaced or eliminated for additional embodiments of the method. The order of the operations/processes may be interchangeable. 
     As shown in  FIG.  2 A , one or more fin structures  20  are fabricated over a substrate  10 . The substrate  10  is, for example, a p-type silicon substrate with an impurity concentration in a range of about 1×10 15  cm −3  to about 1×10 18  cm −3 . In other embodiments, the substrate  10  is an n-type silicon substrate with an impurity concentration in a range of about 1×10 15  cm −3  to about 1×10 18  cm −3 . Alternatively, the substrate  10  may comprise another elementary semiconductor, such as germanium; a compound semiconductor including Group Iv-Iv compound semiconductors such as SiC and SiGe, Group III-V compound semiconductors such as GaAs, GaP, GaN, InP, InAs, InSb, GaAsP, AlGaN, AnnAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or combinations thereof. In one embodiment, the substrate  10  is a silicon layer of an SOI (silicon-on insulator) substrate. Amorphous substrates, such as amorphous Si or amorphous SiC, or insulating material, such as silicon oxide may also be used as the substrate  10 . The substrate  10  may include various regions that have been suitably doped with impurities (e.g., p-type or n-type conductivity). 
     In some embodiments, a part of the substrate  10  for p-type FETs is recessed by etching and a SiGe layer is formed over the recesses.  FIGS.  2 A- 3 F  show the case of an n-FET, but most of the fabrication process is substantially the same for a p-type FET. 
     The fin structures  20  can be patterned by any suitable method. For example, the fin structures  20  can be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and is patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fin structures  20 . 
     As shown in  FIG.  2 A , two fin structures  20  extending in the Y direction are disposed adjacent to each other in the X direction. However, the number of the fin structures is not limited to two. The numbers may be one, three, four or five or more. In addition, one of more dummy fin structures may be disposed adjacent to both sides of the fin structures  20  to improve pattern fidelity in patterning processes. The width of the fin structure  20  is in a range of about 5 nm to about 40 nm in some embodiments, and is in a range of about 7 nm to about 15 nm in certain embodiments. The height of the fin structure  20  is in a range of about 100 nm to about 300 nm in some embodiments, and is in a range of about 50 nm to 100 nm in other embodiments. The space between the fin structures  20  is in a range of about 5 nm to about 80 nm in some embodiments, and is in a range of about 7 nm to 15 nm in other embodiments. One skilled in the art will realize, however, that the dimensions and values recited throughout the descriptions are merely examples, and may be changed to suit different scales of integrated circuits. 
     After the fin structures  20  are formed, an isolation insulating layer  30  is formed over the fin structures  20 , as shown in  FIG.  2 B . 
     The isolation insulating layer  30  includes one or more layers of insulating materials such as silicon oxide, silicon oxynitride or silicon nitride, formed by LPCVD (low pressure chemical vapor deposition), plasma-CVD or flowable CVD. In the flowable CVD, flowable dielectric materials instead of silicon oxide are deposited. Flowable dielectric materials, as their name suggests, can “flow” during deposition to fill gaps or spaces with a high aspect ratio. Usually, various chemistries are added to silicon-containing precursors to allow the deposited film to flow. In some embodiments, nitrogen hydride bonds are added. Examples of flowable dielectric precursors, particularly flowable silicon oxide precursors, include a silicate, a siloxane, a methyl silsesquioxane (MSQ), a hydrogen silsesquioxane (HSQ), a mixture of MSQ and HSQ, a perhydrosilazane (TCPS), a perhydro-polysilazane (PSZ), a tetraethyl orthosilicate (TEOS), or a silyl-amine, such as trisilylamine (TSA). These flowable silicon oxide materials are formed in a multiple-operation process. After the flowable film is deposited, it is cured and then annealed to remove un-desired element(s) to form silicon oxide. The flowable film may be doped with boron and/or phosphorous. The isolation insulating layer  30  may be formed by one or more layers of spin-on-glass (SOG), SiO, SiON, SiOCN and/or fluoride-doped silicate glass (FSG) in some embodiments. 
     After forming the isolation insulating layer  30  over the fin structures  20 , a planarization operation is performed so as to remove part of the isolation insulating layer  30  and the mask layer (e.g., the pad oxide layer and the silicon nitride mask layer formed on the pad oxide layer). The planarization operation may include a chemical mechanical polishing (CMP) and/or an etch-back process. Then, the isolation insulating layer  30  is further removed so that an upper part of the fin structure  20 , which is to become a channel layer, is exposed, as shown in  FIG.  2 B . 
     In certain embodiments, the partial removing of the isolation insulating layer  30  is performed using a wet etching process, for example, by dipping the substrate in hydrofluoric acid (HF). In another embodiment, the partial removing of the isolation insulating layer  30  is performed using a dry etching process. For example, a dry etching process using CHF 3  or BF 3  as etching gases may be used. 
     After forming the isolation insulating layer  30 , a thermal process, for example, an anneal process, may be performed to improve the quality of the isolation insulating layer  30 . In certain embodiments, the thermal process is performed by using rapid thermal annealing (RTA) at a temperature in a range of about 900° C. to about 1050° C. for about 1.5 seconds to about 10 seconds in an inert gas ambient, such as an N 2 , Ar or He ambient. 
     Then, a dummy gate structure  40  is formed over part of the fin structures  20  as shown in  FIG.  2 C . 
     A dielectric layer and a poly silicon layer are formed over the isolation insulating layer  30  and the exposed fin structures  20 , and then patterning operations are performed so as to obtain a dummy gate structure  40  including a dummy gate electrode layer  44  made of poly silicon and a dummy gate dielectric layer  42 . The patterning of the poly silicon layer is performed by using a hard mask including a silicon nitride layer and an oxide layer in some embodiments. The dummy gate dielectric layer  42  can be silicon oxide formed by CVD, physical vapor deposition (PVD), atomic layer deposition (ALD), e-beam evaporation, or other suitable process. In some embodiments, the dummy gate dielectric layer  42  includes one or more layers of silicon oxide, silicon nitride, silicon oxy-nitride, or high-k dielectrics. In some embodiments, a thickness of the dummy gate dielectric layer  42  is in a range of about 1 nm to about 5 nm. 
     In some embodiments, the dummy gate electrode layer  44  is doped poly-silicon with uniform or non-uniform doping. In the present embodiment, the width of the dummy gate electrode layer  44  is in the range of about 30 nm to about 60 nm. In some embodiments, a thickness of the dummy gate electrode layer is in a range of about 30 nm to about 50 nm. In addition, one of more dummy gate structures may be disposed adjacent to both sides of the dummy gate structure  40  to improve pattern fidelity in patterning processes. The width of the dummy gate structure  40  is in a range of about 5 nm to about 40 nm in some embodiments, and is in a range of about 7 nm to about 15 nm in certain embodiments. 
     Further, as shown in  FIGS.  2 C and  2 D , sidewall spacers  46  are formed on opposite side faces of the dummy gate structures  40 .  FIG.  2 D  is a cross section in the y-z plane. An insulating material layer for sidewall spacers  46  is formed over the dummy gate structure  40 . The insulating material layer is deposited in a conformal manner so that it is formed to have substantially equal thicknesses on vertical surfaces, such as the sidewalls, horizontal surfaces, and the top of the dummy gate structure  40 , respectively. In some embodiments, the insulating material layer has a thickness in a range from about 5 nm to about 20 nm. The insulating material layer includes one or more of SiN, SiON and SiCN or any other suitable dielectric material. The insulating material layer can be formed by ALD or CVD, or any other suitable method. Next, bottom portions of the insulating material layer are removed by anisotropic etching, thereby forming gate sidewall spacers  46 . In some embodiments, the sidewall spacers  46  include two to four layers of different insulating materials. In some embodiments, part of the dummy gate dielectric layer  42  is disposed between the sidewall spacers  46  and the isolation insulating layer  30 . In other embodiments, no part of the dummy gate dielectric layer  42  is disposed between the sidewall spacers  46  and the isolation insulating layer  30 . 
     Subsequently, a source/drain region of the fin structure  20  not covered by the dummy gate structure  40  is etched down (recessed) to form a source/drain recess in some embodiments. After the source/drain recess is formed, one or more source/drain epitaxial layers  60  (see also,  FIG.  1 B ) are formed in the source/drain recess as shown in  FIG.  2 D . In some embodiments, a first epitaxial layer, a second epitaxial layer and a third epitaxial layer are formed. In other embodiments, no recess is formed and the epitaxial layers are formed over the fin structure. 
     In some embodiments, the first epitaxial layer includes SiP or SiCP for an n-type FinFET, and SiGe or Ge doped with B for a p-type FinFET. An amount of P (phosphorus) in the first epitaxial layer is in a range from about 1×10 18  atoms/cm 3  to about 1×10 20  atoms/cm 3 , in some embodiments. The thickness of the first epitaxial layer is in a range of about 5 nm to 20 nm in some embodiments, and in a range of about 5 nm to about 15 nm in other embodiments. When the first epitaxial layer is SiGe, an amount of Ge is about 25 atomic % to about 32 atomic % in some embodiments, and is about 28 atomic % to about 30 atomic % in other embodiments. The second epitaxial layer includes SiP or SiCP for an n-type FinFET, and SiGe doped with B for a p-type FinFET, in some embodiments. In some embodiments, an amount of phosphorus in the second epitaxial layer is higher than the phosphorus amount of the first epitaxial layer and is in a range of about 1×10 20  atoms/cm 3  to about 2×10 20  atoms/cm 3 . The thickness of the second epitaxial layer is in a range of about 20 nm to 40 nm in this embodiment, or in a range of about 25 nm to about 35 nm in other embodiments. When the second epitaxial layer is SiGe, an amount of Ge is about 35 atomic % to about 55 atomic % in some embodiments, and is about 41 atomic % to about 46 atomic % in other embodiments. The third epitaxial layer includes a SiP epitaxial layer in some embodiments. The third epitaxial layer is a sacrificial layer for silicide formation in the source/drain. An amount of phosphorus in the third epitaxial layer is less than the phosphorus amount of the second epitaxial layer and is in a range of about 1×10 18  atoms/cm 3  to about 1×10 21  atoms/cm 3  in some embodiments. When the third epitaxial layer is SiGe, an amount of Ge is less than about 20 atomic % in some embodiments, and is about 1 atomic % to about 18 atomic % in other embodiments. 
     In at least one embodiment, the source/drain epitaxial layers  60  are epitaxially-grown by an LPCVD process, molecular beam epitaxy, atomic layer deposition or any other suitable method. The LPCVD process is performed at a temperature of about 400 to 850° C. and under a pressure of about 1 Torr to 200 Torr, using a silicon source gas such as SiH 4 , Si 2 H 6 , or Si 3 H 8 ; germanium source gas such as GeH 4 , or G 2 H 6 ; carbon source gas such as CH 4  or SiH 3 CH 3  and phosphorus source gas such as PH 3 . 
     Still referring to  FIGS.  2 C and  2 D , an interlayer dielectric (ILD) layer  50  is formed over the S/D epitaxial layer  60  and the dummy gate structure  40 . The materials for the ILD layer  50  include compounds comprising Si,  0 , C and/or H, such as silicon oxide, SiCOH and SiOC. Organic materials, such as polymers, may also be used for the ILD layer  50 . 
     After the ILD layer  50  is formed, a planarization operation, such as CMP, is performed, so that the top portion of the dummy gate electrode layer  44  is exposed, as shown in  FIG.  2 D . In some embodiments, before the ILD layer  50  is formed, a contact etch stop layer, such as a silicon nitride layer or a silicon oxynitride layer, is formed. 
     Then, the dummy gate electrode layer  44  and the dummy gate dielectric layer  42  are removed, thereby forming a gate space  47  as shown in  FIGS.  2 E and  2 F .  FIG.  2 F  is a cross section along the Y direction (source-to-drain direction). The dummy gate structures can be removed using plasma dry etching and/or wet etching. When the dummy gate electrode layer  44  is polysilicon and the ILD layer  50  is silicon oxide, a wet etchant such as a TMAH solution can be used to selectively remove the dummy gate electrode layer  44 . The dummy gate dielectric layer  42  is thereafter removed using plasma dry etching and/or wet etching. 
       FIG.  3 A  shows the structure after the channel region of the fin structures  20  are exposed in the gate space  47 .  FIGS.  3 A- 3 F  correspond to area GS in  FIG.  2 E , and thus the sidewall spacers  46  and the ILD layer  50  are omitted from illustration. 
     As shown in  FIG.  3 B , at S 301  of  FIG.  3 G , an interfacial layer  81  is formed on the fin structure  20  and, at S 303  of  FIG.  3 G , a gate dielectric layer  82  is formed on the interfacial layer  81 . In some embodiments, the interfacial layer  81  is formed by using chemical oxidation. In some embodiments, the interfacial layer  81  includes one of silicon oxide, silicon nitride and silicon-germanium oxide. In some embodiments, when the channel is made of Si, the interfacial layer is a silicon oxide layer  81 N, and when the channel is made of SiGe, the interfacial layer is silicon-germanium oxide layer  81 P (see,  FIG.  4 A ). The thickness of the interfacial layer  81  is in a range from about 0.6 nm to about 2 nm in some embodiments. In some embodiments, the gate dielectric layer  82  includes one or more layers of a dielectric material, such as silicon oxide, silicon nitride, or a high-k dielectric material, other suitable dielectric material, and/or combinations thereof. Examples of high-k dielectric materials include HfO 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-alumina (HfO 2 —Al 2 O 3 ) alloy, La 2 O 3 , HfO 2 —La 2 O 3 , Y 2 O 3 , Dy 2 O 3 , Sc 2 O 3 , MgO or other suitable high-k dielectric materials, and/or combinations thereof. 
     The gate dielectric layer  82  may be formed by CVD, ALD or any suitable method. In one embodiment, the gate dielectric layer  82  is formed using a highly conformal deposition process such as ALD in order to ensure the formation of a gate dielectric layer having a uniform thickness around each channel layer. The thickness of the gate dielectric layer  82  is in a range from about 1 nm to about 30 nm in some embodiments. 
     In some embodiments, the gate dielectric layer  82  includes a La-doped hafnium oxide or LaHfOx. In some embodiments, one or more high-k dipole layers (e.g., La oxide) as described below are formed on the gate dielectric layer  82 , and then an annealing operation is performed after the dipole layer is formed. Further, in some embodiments, a cleaning operation is performed to remove residues of the dipole layer generated in patterning operations of the dipole layer. 
     Then, as shown in  FIG.  3 C , at S 305  of  FIG.  3 G , a first conductive layer  83  is formed. The first conductive layer  83  can be formed by CVD, ALD or any suitable method in some embodiments. In some embodiments, the first conductive layer  83  is made of TiN or TiSiN. In some embodiments, no first conductive layer  83  is formed. 
     In some embodiments, at S 307  of  FIG.  3 G , after the first conductive layer  83  is formed, a first annealing operation is performed for about 1 nsec (spike annealing, such as a laser annealing and/or isothermal annealing) to about 360 sec at a temperature of about 600° C. to about 950° C. in some embodiments. The first annealing can help densify the gate dielectric layer  82  and incorporate nitrogen into the gate dielectric layer  82 . Nitrogen helps passivate oxygen vacancies, reduce leakage and improve device reliability. The first annealing can also help form a stable intermixing layer, which helps provide a stable platform for subsequent metal gate film deposition onto the dielectric layer. When the temperature is too high, the first annealing may cause crystallization and grain boundary formation in the high-k gate dielectric layer  82 , which impacts leakage performance and regrowth of the interfacial layer  81 , which slows down device speed. In contrast, when the temperature is too low, the first annealing may not provide sufficient densification and/or nitridation in the high-k gate dielectric layer and cause device instability/variations during subsequent metal gate deposition processes. In some embodiments, when no first conductive layer  83  is formed, no annealing operation at this stage is performed. In some embodiments, the first conductive layer  83  is formed and then an annealing operation is performed; thereafter the first conductive layer  83  is removed with a wet etching process. 
     In some embodiments, the stacked structure including the interfacial layer  81 , the gate dielectric layer  82  and the first conductive layer  83  is soaked in a fluorine-containing gas (e.g., F 2  and/or NF 3 ) for about 4 sec to about 15 min at a temperature of about room temperature (25° C.) to about 550° C. in some embodiments. Incorporation of fluorine helps improve the work function adjustment, decrease Vt of a PMOS device, passivate oxygen vacancies in the gate dielectric layer  82 , reduce leakage and reduce dangling bonds in the gate dielectric layer. Thereafter, a capping layer made of, for example a crystalline, polycrystalline or amorphous Si, is formed over the first conductive layer  83 , and a second annealing operation is performed for about 1 nsec (spike annealing, such as a laser annealing) to about 360 sec at a temperature of about 550° C. to about 1300° C. in some embodiments. In some embodiments, the annealing temperature is from 900° C. to 1100° C. This results in the diffusion of the fluorine into the capping layer, the first conductive layer  83  and the gate dielectric layer  82  in some embodiments. After the second annealing operation, the capping layer is removed. The second annealing with the Si capping layer also helps improve the quality of the gate dielectric layer  82 . A gate dielectric layer, such as a high-k dielectric layer, is formed at a relatively low temperature to avoid crystallization and grain boundary formation, while metal gate films are deposited at relatively higher temperatures. Accordingly, it is desirable to make the high-k dielectric layer more thermally stable before the metal gate deposition. The second annealing with the capping layer at the temperature ranges as set forth above can densify the high-k dielectric layer, and make it thermally stable, without any thermal oxide inversion during the metal gate deposition. The second annealing also helps thermally in-diffuse the fluorine from the outer layers (e.g., the capping layer) into the first conductive layer  83 , the gate dielectric layer  82  and the interfacial layer  81 . The capping layer is used to protect the gate dielectric layer  82  and the first conductive layer  83  from undesirable oxidation damage and to isolate these films from the annealing atmosphere. After thermal stabilization of the gate dielectric layer, the capping layer is no longer required in the final device structure and therefore it is removed. 
     In other embodiments, no fluorine soaking operation accompanying formation of a Si capping layer and a second annealing operation is performed. 
     Subsequently, at S 309  of  FIG.  3 G , a second conductive layer, as a first barrier layer  84  is formed, and then at S 311  of  FIG.  3 G , one or more WFM layers  86  are formed. A metal gate layer including a glue layer  87  and a body metal layer (gate electrode layer)  88  is formed above the work function adjustment layer  86 , at S 313  of  FIG.  3 G . 
     In some embodiments, the second conductive layer  84  is made of TaN and serves as an etch stop barrier layer. The barrier layer  86  acts as a wet etching stop layer during patterning of p-type and n-type WFM layers subsequently formed to form multiple Vt devices. In some embodiments, no second conductive layer  84  is formed. 
     The work function adjustment material (WFM) layer  86  can be formed by ALD, PVD, CVD, e-beam evaporation, or other suitable process. Further, the WFM layer can be formed separately for the n-channel FET and the p-channel FET, which may use different metal layers. The body gate electrode layer (body metal layer)  88  and the glue layer  87  can be formed by CVD, ALD, electro-plating, or other suitable method. When the first and second conductive layers are not formed, the WFM layer  86  is directly formed on the gate dielectric layer  82 . In some embodiments, the first conductive layer  83  is formed and removed after the annealing operation S 307 , thereafter the second conductive layer is not formed and the WFM layer  86  is directly formed on the gate dielectric layer  82 . 
       FIG.  4 A  shows a cross section view of gate structures for FETs with different threshold voltages according to an embodiment of the present disclosure.  FIGS.  4 B and  4 C  show various work function adjustment material layers for multiple FETs with different threshold voltages according to embodiments of the present disclosure. 
     In some embodiments, a semiconductor device includes a first n-type FET N 1  having a WFM layer structure WF 1 , a second n-type FET N 2  having a WFM layer structure WF 2 , a third n-type FET N 3  having a WFM layer structure WF 3 , a first p-type FET P 1  having the WFM layer structure WF 3 , a second p-type FET P 2  having the WFM layer structure WF 2 , and a third p-type FET P 3  having the WFM layer structure WF 1 . A threshold voltage of the first n-type FET N 1  (ultra-low voltage FET) is smaller in an absolute value than a threshold voltage of the second n-type FET N 2  (low-voltage FET) and the threshold voltage of the second n-type FET N 2  is smaller in an absolute value than a threshold voltage of the third n-type FET N 3  (standard voltage FET). Similarly, a threshold voltage of the first p-type FET P 1  (ultra-low voltage FET) is smaller in an absolute value than a threshold voltage of the second p-type FET P 2  (low voltage FET) and the threshold voltage of the second p-type FET P 2  is smaller in an absolute value than a threshold voltage of the third p-type FET P 3  (standard voltage FET). The threshold voltage in an absolute value of the first n-type FET N 1  is designed to have substantially the same threshold voltage (e.g., ±1 mV) in an absolute value of the first p-type FET P 1 , the threshold voltage in an absolute value of the second n-type FET N 2  is designed to have substantially the same threshold voltage (e.g., ±1 mV) in an absolute value of the second p-type FET P 2 , and the threshold voltage in an absolute value of the third n-type FET N 3  is designed to have substantially the same threshold voltage (e.g., ±1 mV) in an absolute value of the third p-type FET P 3 . 
     In some embodiments, the WFM layer structure WF 1  includes a first WFM layer  100 , the WFM layer structure WF 2  includes, closer to the gate dielectric layer  82 , a second WFM layer  89 - 2  and the first WFM layer  100 , and the WFM layer structure WF 3  includes, closer to the gate dielectric layer  82 , a third WFM layer  89 - 1 , the second WFM layer  89 - 2  and the first WFM layer  100 , as shown in  FIG.  4 A . 
     In  FIG.  4 B , the semiconductor device includes three different threshold voltage levels. In other embodiments, as shown in  FIG.  4 C , more than three, e.g., nine different threshold voltages are utilized for an n-type FET and a p-type FET, respectively. In  FIG.  4 C , not only the WFM layer structures but also configurations HK 1 , HK 2  and HK 3  of the gate dielectric layer  82  (e.g., material, thickness, etc.) are adjusted to obtain a desired threshold voltage. HK 1 , HK 2 , HK 3  are composed of different materials such as HfO 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-alumina (HfO 2 —Al 2 O 3 ) alloy, La 2 O 3 , HfO 2 —La 2 O 3 , Y 2 O 3 , Dy 2 O 3 , Sc 2 O 3 , MgO or other suitable high-k dielectric materials, and/or combinations thereof. In some embodiments, HK 1 , HK 2  and HK 3  are composed of a high-k dielectric with some different concentrations of rare-earth metal and/or Group-III dopants (such as, La, Al, Mg, Sc, Dy, Y, Ti, Lu, Sr etc.). In some embodiments, HK 3  is composed of HfOx, HK 2  is composed of HfLaOx (or HfYOx, HfLuOx, HfSrOx, HfScOx, HfDyOx) and HK 1  is composed of HfLaOx (or HfYOx, HfLuOx, HfSrOx, HfScOx, HfDyOx), such that the amount of La (or Y, Lu, Sr, Sc, Dy) in HK 1  is higher than that in HK 2 . In some embodiments, HK 1  is composed of HfOx, HK 2  is composed of HfAlOx (or HfZrOx, HfTiOx) and HK 3  is composed of HfAlOx (or HfZrOx, HfTiOx), such that the amount of Al (or Zr, Ti) in HK 3  is higher than that in HK 2 . In some embodiments, HK 2  is composed of HfOx, HK 1  is composed of HfLaOx (or HfYOx, HfLuOx, HfSrOx, HfScOx, HfDyOx) and HK 3  is composed of HfAlOx (or HfZrOx, HfTiOx). The thicknesses of HK 1 , HK 2  and HK 3  are in the range from about 0.6 nm to about 30 nm in some embodiments. In some embodiments, more than three different high-k dielectric films are used. 
     In some embodiments, HK 1  includes hafnium oxide, HK 2  includes La-doped hafnium oxide and HK 3  includes a La-doped hafnium oxide having a higher La amount than HK 2 . 
     In a CMOS device, a gate electrode is commonly used for (shared by) an n-type FET and p-type FET, and thus an n-type FET and p-type FET having substantially the same threshold voltage are selected. For example, a CMOS device having an ultra-low voltage FET includes the first n-type FET N 1  and the first p-type FET P 1 .  FIG.  5 A  shows a plan view (layout) of such a CMOS device. 
     As shown in  FIG.  5 A , a gate electrode  80  is disposed over the channel regions of one or more fin structures  20 . In some embodiments, each of the n-type FET NFET and the p-type FET PFET includes two fin structures. In other embodiments, the number of the fin structures per FET is one or three or more (up to, e.g.,  10 ).  FIG.  5 B  shows a cross sectional view corresponding to area A 1  of  FIG.  5 A  and  FIG.  5 C  shows an enlarged view of area B 1  of  FIG.  5 B . In  FIGS.  5 B and  5 C , the glue layer  87  and the body metal layer  88  (shown in broken line) are omitted. 
     In some embodiments, the n-type FET NFET (e.g., N 1 ) and the p-type FET PFET have different gate dielectric layers (different materials). In some embodiments, the n-type FET includes a dipole high k dielectric layer  82 B (e.g., highly La-doped hafnium oxide), while the p-type FET includes a high-k dielectric layer  82  (e.g., no La-doped hafnium oxide). Further, the n-type FET NFET has the WFM layer structure WF 1  having the first WFM layer  100  (only), and the p-type FET (e.g., P 1 ) has the WFM layer structure WF 3  having the second and third WFM layers ( 89 - 2  and  89 - 1 , which are collectively referred to as  89  in  FIG.  5 B ) and the first WFM layer  100 . As shown in  FIG.  5 C , the gate dielectric layers of the n-type FET and the p-type FET are discontinuous, and separated by a part of the first WFM layer  100  and a part of the second and third WFM layers  89 - 1  and  89 - 2 . 
     Similarly, in  FIGS.  6 A- 6 C , a CMOS device having a threshold voltage Vt4 includes an n-type FET with a WFM layer structure WF 2  and a p-type FET with a WFM layer structure WF 2  (see,  FIG.  4 C ), and the n-type FET NFET (e.g., N 1 ) and the p-type FET PFET have different gate dielectric layers (different materials). In some embodiments, the n-type FET includes a second dipole high-k dielectric layer  82 B (e.g., high La-doped hafnium oxide), while the p-type FET includes a first dipole high-k dielectric layer  82 A (e.g., low La-doped hafnium oxide). As shown in  FIG.  6 C , the gate dielectric layers of the n-type FET and the p-type FET are discontinuous, and separated by a part of the second WFM layer  89 - 1 . 
     As set forth above, the gate dielectric layers made of different materials are separated from each other under the WFM layers, and thus it is possible to suppress cross contamination, such as La diffusion from a high La region to a low La region. 
       FIGS.  7 A- 7 I  show various stages of manufacturing gate dielectric layers for different Vt devices according to embodiments of the present disclosure.  FIGS.  7 A,  7 C,  7 D,  7 F and  7 H  show three regions of a gate space in which a gate dielectric layer is formed for different Vt devices. Although three regions are arranged as shown, the order of the regions is not limited to. Although three regions are shown, only two regions which are nearby are provided to one gate space as shown in  FIGS.  7 B,  7 E,  7 G and  7 I  in some embodiments. 
     After the structure shown in  FIG.  3 A  in which a gate space is formed, as shown in  FIGS.  7 A and  7 B , an interfacial layer (not shown in  FIGS.  7 A and 7 B ) is formed and then a high-k (non-dipole) dielectric layer  82  is formed on the interfacial layer. Further, a first dipole high-k dielectric layer  182  is formed on the high-k dielectric layer  82 . In some embodiments, the first dipole high-k dielectric layer  182  includes one or more of La 2 O 3 , Lu 2 O 3 , Sc 2 O 3 , SrO, ZrO 2 , Y 2 O 3 , DyO x , EuO x  and Yb 2 O 3 . In certain embodiments, the first dipole high-k dielectric layer  182  is made of lanthanum oxide (La 2 O 3 ). In some embodiments, at least one of the materials of the high-k dielectric layer  82  (base dielectric layer) for three regions is different from the other two regions. 
     Then, as shown in  FIG.  7 C , the first dipole high-k dielectric layer  182  is patterned such that the first dipole high-k dielectric layer  182  is removed from the first region and the second region (left and center regions in  FIG.  7 C ) and remains in the third region (right region in  FIG.  7 C ). 
     Next, a second dipole high-k dielectric layer  282  is formed on the high-k dielectric layer  82  in the first and second regions and on the first dipole high-k layer  182  in the third regions, and then a patterning operation is performed such that the second dipole high-k dielectric layer  282  is removed from the first region and remains in the second and third regions, as shown in  FIG.  7 D .  FIG.  7 E  also shows after the second high-k dipole layer  282  is patterned. The second dipole high-k dielectric layer  282  is made of the same material as or different material than the first dipole high-k dielectric layer  182 , and includes one or more of La 2 O 3 , Lu 2 O 3 , Sc 2 O 3 , SrO, CeO 2 , Y 2 O 3 , DyO x , EuO x  and Yb 2 O 3 . 
     After the structure shown in  FIGS.  7 D and  7 E  is formed, in some embodiments, an annealing operation is performed at a temperature between 400° C. to about 700° C. for about 2 sec to about 100 sec to drive-in the dipole doping elements from the first and/or second dipole high-k dielectric layers  182 ,  282  into the base high-k dielectric layer  82 , to form high-k dielectric layers  82 A and  82 B with different amounts of dopants, as shown in  FIGS.  7 F and  7 G . In some embodiments, the dipole doping elements includes one or more of La, Lu, Sc, Sr, Ce, Y, Dy, Eu and Yb, which is contained in the first and second dipole high-k dielectric layers  182 ,  282 . In certain embodiments, the doping element is La. 
     In some embodiments, the dipole element diffusion layers  82 A and  82 B are formed at a part of the high-k dielectric layer  82  and in other embodiments, the high-k dielectric layer  82  is fully converted to the dipole element diffusion layers  82 A and  82 B. The amount of the dipole dopant elements diffused into the layer  82 A is smaller than that into the layer  82 B in some embodiments. When the second dipole high-k dielectric layer  282  is made of a different material than the first dipole high-k dielectric layer  182 , at least one dopant in the layer  82 B is different from layer  82 A. In some embodiments, after the annealing operation, an optional wet etching is performed to remove the residues of the dipole layers  182  and  282  either partly or completely, as shown in  FIGS.  7 H and  7 I . 
     In some embodiments, the doping amount of the dipole element (e.g., La) in the low diffusion dipole element high-k dielectric layer  82 A is more than about 10-100 times the doping amount of the dipole element in the high-k dielectric layer  82 , the doping amount of the dipole element in the high diffusion dipole element high-k dielectric layer  82 B is more than about 3-100 times the doping amount of the dipole element in the low diffusion dipole element high-k dielectric layer  82 A. In some embodiments, the doping amount of the dipole element (e.g., La) in the low diffusion dipole element high-k dielectric layer  82 A is in a range from about 2×10 13  atoms/cm 2  to about 3×10 15  atoms/cm 2 , and the doping amount of the dipole element in the high diffusion dipole element high-k dielectric layer  82 B is higher than that in layer  82 A and is in a range from about 6×10 13  atoms/cm 2  to about 8×10 17  atoms/cm 2 . In some embodiments, the normal high-k dielectric layer  82  may contain the dipole element in a range from about 0 atoms/cm 2  to about 5×10 13  atoms/cm 2 , which is smaller than that of layer  82 A. 
     As set forth above, when the dipole element diffused high-k dielectric layer (e.g.,  82 A and  82 B) is adjacent to the normal high-k dielectric layer, or different concentration layers are adjacent to each other, the dipole dopant element diffuses across the boundary, which may cause a Vt shift or other electrical issues. In the present embodiments, a patterning operation to cut the gate dielectric layer at the boundary and fill the cut region (e.g., groove) with another material to suppress the diffusion of the dipole dopant. 
       FIGS.  8 A- 8 J  show cross sectional views of various stages of manufacturing the semiconductor device according to embodiments of the present disclosure. It is understood that in the sequential manufacturing process, one or more additional operations can be provided before, during, and after the stages shown in  FIGS.  8 A- 8 J  and some of the operations described below can be replaced or eliminated for additional embodiments of the method. The order of the operations/processes may be interchangeable. Materials, configurations, dimensions, processes and/or operations as described with respect to embodiments of  FIGS.  1 A- 7 I  can be employed in the following embodiments, and detailed description thereof may be omitted. 
       FIG.  8 A  shows a cross sectional view after the dipole element doped high-k dielectric layer  82 B is formed as explained with respect to  FIGS.  7 A- 7 I . As shown in  FIG.  8 A , the high-k dielectric layer  82  is in contact with the dipole element doped (high-doped) high-k dielectric layer  82 B in some embodiments. In other embodiments, the high-k dielectric layer  82  is in contact with the dipole element doped (low-doped) high-k dielectric layer  82 A, or the dipole element doped (low-doped) high-k dielectric layer  82 A is in contact with the dipole element doped (high-doped) high-k dielectric layer  82 B. The boundary is located over the isolation insulating layer  30  (see,  FIGS.  5 C and  6 C ). 
     Then, as shown in  FIG.  8 B , a hard mask layer  130  is formed over the gate dielectric layers  82  and  82 B, and further a mask pattern  135  is formed over the hard mask layer  130 . 
     In some embodiments, the hard mask layer  130  includes one or more of aluminum oxide, aluminum nitride, aluminum oxynitride, titanium oxide, titanium oxynitride, titanium nitride, tantalum oxynitride. The thickness of the hard mask layer  130  is in a range from about 0.5 nm to about 20 nm in some embodiments, and is in a range from about 0.8 nm to about 10 nm in other embodiments. When the thickness is too small, the hard mask layer  130  may not sufficiently function as a hard mask and/or the adhesion to the BARC layer may be insufficient, and when the thickness is too large, patterning of the hard mask layer may be difficult. The hard mask layer  130  can be formed by CVD, PVD, ALD, e-beam evaporation, or other suitable process. 
     The mask pattern  135  includes a photo resist pattern with an organic bottom antireflective coating (BARC) layer, or a patterned BARC layer. The mask pattern  135  is an opening (trench) pattern  76  corresponding to area A 2  shown in  FIG.  5 A . The width W 1  of the opening in the X direction is in a range from about 10 nm to about 150 nm in some embodiments, and is in a range from about 14 nm to about 120 nm in other embodiments. The minimum width may be limited to the lithography resolution and when the width is smaller than the ranges, the barrier effect may be insufficient. When the width is greater than the ranges, the trench is too close to the fin structure, and may cause damage to the fin structures. 
     As shown in  FIG.  8 C , the hard mask layer  130  is patterned by using the mask pattern  135  as an etching mask by wet and/or dry etching. The wet etchant includes an aqueous solution of NH 4 OH, H 2 O 2 , and/or HCl, or an aqueous solution of NH 4 F and HF in some embodiments. The dry etching uses etching gas including BCl 3  or other chlorine-containing gas in some embodiments. 
     Further, as shown in  FIG.  8 D , the high-k gate dielectric layers  82  and  82 B are patterned by using the mask pattern  135  and the patterned hard mask layer  130  as an etching mask, thereby forming a trench or opening  76 . Then, the mask pattern  135  is removed as shown in  FIG.  8 E . When the mask pattern  135  is made of an organic material, such as BARC, a plasma ashing process using N 2 , H 2 , Cl 2 , O 2  and/or CF 4  gases is used. In other embodiments, the mask pattern  130  is removed before the gate dielectric layers  82  and  82 B are patterned, and the high-k gate dielectric layers  82  and  82 B are patterned by using the patterned hard mask layer  135  as an etching mask. 
     Subsequently, the patterned hard mask layer  130  is removed as shown in  FIG.  8 F . In some embodiments, the patterned hard mask layer  130  is removed by using wet etching. The wet etchant includes an aqueous solution of NH 4 OH, H 2 O 2 , and/or HCl, or an aqueous solution of NH 4 F and HF in some embodiments. In other embodiments, the patterned hard mask layer  130  is removed by dry etching. The etching gas includes BCl 3  or other chlorine-containing gas in some embodiments. 
     In some embodiments, in the etching of the high-k gate dielectric layers  82  and  82 B, a part of the ILD layer  50  and a part of the isolation insulating layer  30  are also etched, as shown in  FIGS.  8 D and  8 I .  FIG.  81    is the Y directional cross section, while  FIG.  8 D  is the X directional cross section. In some embodiments, the etched amount D 1  of the ILD layer  50  is in a range from about 2 nm to about 5 nm and the etched amount D 2  of the isolation insulating layer  30  is in a range from about 1 nm to about 4 nm. As set forth above, the mask pattern  135  is an opening pattern corresponding to area A 2  shown in  FIG.  5 A  and disposed over two gate spaces. In other embodiments, the mask pattern  135  is disposed over only one gate space, or more than two gate spaces. 
     After the gate dielectric layers  82  and  82 B are separated as shown in  FIG.  8 F , the WFM layer  89  is formed and the WFM layer  100  is formed over the WFM layer  89  to fill the gap between the high-k gate dielectric layer  82  and the dipole element doped high-k dielectric layer  82 B, as shown in  FIG.  8 G . Further, as shown in  FIGS.  8 H and  8 J , a glue layer  87  and the body metal layer  88  are formed. In some embodiments, a cap layer  101  is formed over the WFM layer  100 . In some embodiments, the cap layer  101  includes one or more of TiN, TiSiN, Ta or TaN. As shown in  FIGS.  8 I and  8 J , a part of the WFM layer  89  penetrates into the isolation insulating layer  30 . 
     In some embodiments, adjacent gate electrodes are connected by a connection pattern  77  as shown in  FIGS.  8 K and  8 L .  FIG.  8 K  is a plan view after the body metal layer  88  is formed. In  FIGS.  8 K and  8 L , the layers constituting the gate electrode are omitted for simplicity. In some embodiments, as shown in  FIGS.  8 K and  8 L , when the opening (trench)  76  is formed over two gate spaces, the adjacent gate electrodes are connected by a connection pattern  77  made of the same conductive materials of the gate electrodes filled in the trench  76 . The gate dielectric layer in the NFET region is different in terms of the dipole element concentration than the gate dielectric layer in the PFET region. In other embodiments, since the metal gate structure is planarized or recessed, the gate connection pattern does not exist (see  FIG.  8 J ). 
       FIGS.  9 A- 9 G  show cross sectional views of various stages of manufacturing the semiconductor device according to embodiments of the present disclosure. It is understood that in the sequential manufacturing process, one or more additional operations can be provided before, during, and after the stages shown in  FIGS.  9 A- 9 G  and some of the operations described below can be replaced or eliminated for additional embodiments of the method. The order of the operations/processes may be interchangeable. Materials, configurations, dimensions, processes and/or operations as described with respect to embodiments of  FIGS.  1 A- 8 J  can be employed in the following embodiments, and detailed description thereof may be omitted. 
     As shown in  FIG.  9 A , after the structure shown in  FIG.  8 A  is formed, another dielectric layer  140  is formed over the gate dielectric layers  82  and  82 B. In some embodiments, the another dielectric layer  140  includes a high-k dielectric material, such as HfO 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-alumina (HfO 2 —Al 2 O 3 ) alloy, or any other suitable material. The another dielectric layer  140  includes no dipole elements in some embodiments. The another dielectric layer  140  is used to suppress defects in the gate dielectric layer and to improve the k-value of overall gate dielectric layer. In some embodiments, the another dielectric layer  140  is made of the same or different materials than the high-k dielectric layer  82 . 
     Then, as shown in  FIG.  9 B , similar to  FIG.  8 B , a hard mask layer  130  is formed over the another dielectric layer  140 , and further a mask pattern  135  is formed over the hard mask layer  130 . 
     As shown in  FIG.  9 C , similar to  FIG.  8 C , the hard mask layer  130  is patterned by using the mask pattern  135  as an etching mask. Further, as shown in  FIG.  9 D , the another dielectric layer  140  and the high-k gate dielectric layers  82  and  82 B are patterned by using the mask pattern  135  and the patterned hard mask layer  130  as an etching mask. Then, the mask pattern  135  is removed as shown in  FIG.  9 E . 
     Subsequently, the patterned hard mask layer  130  is removed as shown in  FIG.  9 F  by wet and/or dry etching. After the gate dielectric layers  82  and  82 B are separated as shown in  FIG.  9 F , the WFM layer  89  is formed and the WFM layer  100  is formed over the WFM layer  89  to fill the gap between the high-k gate dielectric layer  82  and the dipole element doped high-k dielectric layer  82 B, as shown in  FIG.  9 G . Further, similar to  FIGS.  8 H and  8 J , a glue layer  87  and the body metal layer  88  are formed. 
       FIGS.  10 A- 10 E  show cross sectional views of various stages of manufacturing the semiconductor device according to embodiments of the present disclosure. It is understood that in the sequential manufacturing process, one or more additional operations can be provided before, during, and after the stages shown in  FIGS.  10 A- 10 E  and some of the operations described below can be replaced or eliminated for additional embodiments of the method. The order of the operations/processes may be interchangeable. Materials, configurations, dimensions, processes and/or operations as described with respect to embodiments of  FIGS.  1 A- 9 G  can be employed in the following embodiments, and detailed description thereof may be omitted. 
       FIG.  10 A  shows the structure formed in  FIG.  8 F . Then, as shown in  FIG.  10 B , the another dielectric layer  140  is conformally formed to partially fill the gap between the high-k dielectric layer  82  and the dipole element doped high-k dielectric layer  82 B. Then, as shown in  FIG.  10 C , the WFM layer  89  is formed over the another dielectric layer  140 , and the WFM layer  100  is formed over the WFM layer  89 . 
     In other embodiments, the another dielectric layer  140  is formed to fully fill the gap between the high-k dielectric layer  82  and the dipole element doped high-k dielectric layer  82 B, as shown in  FIG.  10 D . Then, as shown in  FIG.  10 E , the WFM layer  89  is formed over the another dielectric layer  140 , and the WFM layer  100  is formed over the WFM layer  89 . 
     In the embodiments of  FIGS.  10 C and  10 E , at least the another dielectric layer  140  functions as a barrier layer to suppress diffusion of the dipole elements. 
       FIGS.  11 A- 11 V  show various boundary configurations between different Vt devices according to embodiments of the present disclosure. Materials, configurations, dimensions, processes and/or operations as described with respect to embodiments of  FIGS.  1 A- 10 E  can be employed in the following embodiments, and detailed description thereof may be omitted. 
     As shown in  FIGS.  11 A- 11 C , diffusion of the dipole element (e.g., La) from the higher doping concentration to the lower or zero concentration region can be suppressed by the WFM layer  89  and the WFM layer  100 . In  FIGS.  11 D- 11 F , diffusion of the dipole element from the higher doping concentration to the lower or zero concentration region can be suppressed by the WFM layer  100  and the cap layer  101 . In  FIGS.  11 G- 11 I , diffusion of the dipole element from the higher doping concentration to the lower or zero concentration region can be suppressed by the WFM layer  89 . 
     In  FIGS.  11 J- 11 L , diffusion of the dipole element (e.g., La) from the higher doping concentration to the lower or zero concentration region can be suppressed by the WFM layer  89  and the WFM layer  100 . In  FIGS.  11 M- 11 O , diffusion of the dipole element from the higher doping concentration to the lower or zero concentration region can be suppressed by the WFM layer  100  and the cap layer  101 . In  FIGS.  11 P- 11 R , diffusion of the dipole element from the higher doping concentration to the lower or zero concentration region can be suppressed by the WFM layer  89 . 
     In  FIGS.  11 S,  11 T,  11 U and  11 V , diffusion of the dipole element from the higher doping concentration to the lower or zero concentration region can be suppressed by the WFM layer  89  and the WFM layer  100 . 
     In some embodiments, the trench  76  does not necessarily cut the boundary of different gate dielectric layers. As shown in  FIG.  11 W , the trench cuts the lower dipole concentration dielectric layer (e.g.,  82 A,  82 B), and the WFM barrier is formed in the trench. 
       FIG.  12    shows an SRAM circuit layout according to embodiments of the present disclosure. In some embodiments, an SRAM unit cell includes six transistors (two pass-gate transistors (PGs), pull-up transistors (PUs) and pull-down transistors (PDs)), and the PD and PU are different conductivity, and thus, use different gate dielectric material in terms of dipole doping, and share the same gate electrode. In some embodiments, a boundary of the as formed gate dielectric layer is cut between the p-type FET and n-type FET as set forth above. In some embodiments, one trench  76  is formed over two gate spaces each of the PD and PU. 
       FIG.  13    show various circuit layouts where the present embodiments are applied. In some embodiments, a gate electrode is shared by a p-type FET and an n-type FET having different gate dielectric material in terms of dipole doping, a trench  76  is formed over the gate space at or around the boundary of the p-type FET and n-type FET. However, when a gate electrode is shared by a p-type FET and an n-type FET having the same gate dielectric material in terms of dipole doping, no trench  76  is necessary. 
     In the present disclosure, in a gate electrode disposed over and shared by a p-type FET and an n-type FET, gate dielectric layers having different dipole element (La, Sc, Sr, Ce, Y, Dy, Eu, Yb, Al, Lu, Nb, W, Mo, V etc.) doping concentration are separated from each other by a barrier layer to suppress dipole element diffusion. The barrier layer can be one or more WFM layers (e.g., TiAl, TiAlC, TaAl, TaAlC, TiN, TiSiN, Ru, WN, WCN, MoN, etc.), another dielectric layer (hafnium oxide, zirconium oxide, aluminum oxide, etc.) or any layers constituting the gate electrode (e.g., TaN, W, etc.). By suppressing the dipole element diffusion, it is possible to suppress Vt shift or any other degradation of device performances which would be otherwise caused by the dipole element diffusion. 
     It will be understood that not all advantages have been necessarily discussed herein, no particular advantage is required for all embodiments or examples, and other embodiments or examples may offer different advantages. 
     In accordance with one aspect of the present application, a semiconductor device includes a first field effect transistor (FET) including a first gate structure disposed over a first channel region, and a second FET having different conductivity type than the first FET and including a second gate structure disposed over a second channel region. The first gate structure includes a first gate dielectric layer over the first channel region, a first work function adjustment material (WFM) layer over the first gate dielectric layer, and a first metal gate electrode layer. The second gate structure includes a second gate dielectric layer over the second channel region, a second WFM layer over the second gate dielectric layer, and a second metal gate electrode layer. The first metal gate electrode layer and the second metal gate electrode layer are continuously formed and made of a same material. The first gate dielectric layer is separated from the second gate dielectric layer by a gap. At least one of the first gate dielectric layer or the second gate dielectric layer includes a dopant, and a dopant concentration is different between the first gate dielectric layer and the second gate dielectric layer. In one or more of the foregoing and following embodiments, the dopant is at least one selected from the group consisting of La, Sc, Sr, Ce, Y, Dy, Eu Pb, Tr, Nd, Gd, Pm, Pr, Ho, Er, Tm, Sm, Yb, Al, Nb, Mo, W, Ti, Hf, Zr, Ta, V, Ba and Mg. In one or more of the foregoing and following embodiments, the first and second gate dielectric layers include one selected from the group consisting of hafnium oxide, zirconium oxide and hafnium-zirconium oxide. In one or more of the foregoing and following embodiments, the first WFM layer and the second WFM layer are continuously formed and made of a same material. In one or more of the foregoing and following embodiments, the gap is filled by a part of the first or second WFM layers. In one or more of the foregoing and following embodiments, first and second WFM layers include at least one layer of one material selected from the group consisting of TiN, TiSiN, WN, WCN, MoN and Ru. In one or more of the foregoing and following embodiments, first and second WFM layers include at least one layer of one material selected from the group consisting of TaAl, TaAlC, TiAl or TiAlC. In one or more of the foregoing and following embodiments, a width of the gap along a gate extension direction is in a range from 14 nm to 120 nm. In one or more of the foregoing and following embodiments, each of the first WFM layer and the second WFM layer comprises one or more layers made of different material, and a layer structure of the first WFM is different from a layer structure of the second WFM. In one or more of the foregoing and following embodiments, the gap is filled by a part of the first WFM layer and a part of the second WFM layer. 
     In accordance with another aspect of the present disclosure, a semiconductor device includes a first field effect transistor (FET) including a first gate structure disposed over a first channel region, and a second FET having different conductivity type than the first FET and including a second gate structure disposed over a second channel region. The first gate structure includes a first gate dielectric layer over the first channel region, a second gate dielectric layer disposed over the first gate dielectric layer, a first work function adjustment material (WFM) layer over the second gate dielectric layer, and a first metal gate electrode layer. The second gate structure includes a third gate dielectric layer over the second channel region, a fourth gate dielectric layer over the second channel region, a second WFM layer over the fourth gate dielectric layer, and a second metal gate electrode layer. The first metal gate electrode layer and the second metal gate electrode layer are continuously formed, and the first gate dielectric layer is separated from the second gate dielectric layer by a gap. In one or more of the foregoing and following embodiments, at least one of the first gate dielectric layer or the third gate dielectric layer includes a dopant, the dopant is at least one selected from the group consisting of La, Sc, Sr, Ce, Y, Dy, Eu and Yb, and a dopant concentration is different between the first gate dielectric layer and the second gate dielectric layer. In one or more of the foregoing and following embodiments, the second gate dielectric layer and the fourth gate dielectric layer are made of a same material. In one or more of the foregoing and following embodiments, the second gate dielectric layer is separated from the fourth gate dielectric layer by a gap. In one or more of the foregoing and following embodiments, the second gate dielectric layer and the fourth gate dielectric layer are continuously formed and at least partially fill the gap. In one or more of the foregoing and following embodiments, compositions of the first and third gate dielectric layer are different from a composition of the second and fourth gate dielectric layer. 
     In accordance with another aspect of the present disclosure, a gate structure of a field effect transistor includes a first gate dielectric layer, a second gate dielectric layer, and one or more conductive layers disposed over the first gate dielectric layer and the second gate dielectric layer. The first gate dielectric layer is separated from the second gate dielectric layer by a gap filled with a diffusion blocking layer. In one or more of the foregoing and following embodiments, the first and second gate dielectric layers include one selected from the group consisting of hafnium oxide, zirconium oxide and hafnium-zirconium oxide, at least one of the first and second gate dielectric layers includes La as a dopant, and a dopant concentration is different between the first gate dielectric layer and the second gate dielectric layer. In one or more of the foregoing and following embodiments, the first gate dielectric layer includes no dopant. In one or more of the foregoing and following embodiments, at least one layer of the one or more conductive layers is continuously disposed over the first gate dielectric layer and the second gate dielectric layer. 
     In accordance with another aspect of the present disclosure, in a method of manufacturing a semiconductor device, a gate dielectric layer is formed in a gate space, where the gate space is formed by one or more insulating layers. The gate dielectric layer is separated into a first gate dielectric layer and a second gate dielectric layer by forming a trench. One or more work function adjustment material (WFM) layers are formed over the first gate dielectric layer and the second gate dielectric layer. A body gate electrode layer is formed over the one or more WFM layers. In one or more of the foregoing and following embodiments, the gate dielectric layer comprises a first region and a second region adjacent to the first region, at least one of the first region or the second region includes a dopant, a dopant concentration is different between the first region and the second region, and the first gate dielectric layer includes the first region and the second gate dielectric layer includes the second region. In one or more of the foregoing and following embodiments, the dopant is at least one selected from the group consisting of La, Sc, Sr, Ce, Y, Dy, Eu and Yb. In one or more of the foregoing and following embodiments, the gate dielectric layer includes one selected from the group consisting of hafnium oxide, zirconium oxide and hafnium-zirconium oxide. In one or more of the foregoing and following embodiments, the trench is filled by a part of the one or more WFM layers. In one or more of the foregoing and following embodiments, the gate dielectric layer is separated by the following operations. A hard mask layer is formed over the gate dielectric layer, a mask pattern having an opening is formed over the hard mask layer, the hard mask layer is patterned by using the mask pattern as an etching mask, the gate dielectric layer is patterned by using at least one of the mask pattern or the patterned hard mask layer as an etching mask, and the mask pattern and the patterned hard mask layer are removed. In one or more of the foregoing and following embodiments, the hard mask layer is made of a different material than the gate dielectric layer and includes at least one selected from the group consisting of one or more of aluminum oxide, aluminum nitride, aluminum oxynitride, titanium oxide and titanium oxynitride. In one or more of the foregoing and following embodiments, a thickness of the hard mask layer is in a range from 0.5 nm to 20 nm. In one or more of the foregoing and following embodiments, the mask pattern is made of an organic antireflective coating material. 
     In accordance with another aspect of the present disclosure, in a method of manufacturing a semiconductor device, a first gate dielectric layer is formed over a first channel region made of a first semiconductor material and over an isolation insulating layer, a second gate dielectric layer is formed over a second channel region made of a second semiconductor material and over the isolation insulating layer. The first gate dielectric layer is laterally in contact with the second gate dielectric layer at a boundary located over the isolation insulating layer. By using a patterning operation, the first gate dielectric layer and the second gate dielectric layer are separated by a trench. A diffusion barrier is formed by filling the trench with a dielectric material or a conductive material. At least one of the first gate dielectric layer or the second gate dielectric layer includes a dopant, a dopant concentration is different between the first gate dielectric layer and the second gate dielectric layer, and the diffusion barrier functions as a barrier for the dopant. In one or more of the foregoing and following embodiments, the first and second gate dielectric layer includes one selected from the group consisting of hafnium oxide, zirconium oxide and hafnium-zirconium oxide. In one or more of the foregoing and following embodiments, the dopant is at least one selected from the group consisting of La, Sc, Sr, Ce, Y, Dy, Eu and Yb. In one or more of the foregoing and following embodiments, in the separating the first gate dielectric layer and the second gate dielectric layer, a hard mask layer is formed over the first and second gate dielectric layers. A mask pattern having an opening is formed over the hard mask layer and above the boundary. The hard mask layer is patterned by using the mask pattern as an etching mask. The first and second gate dielectric layers are patterned by using at least one of the mask pattern or the patterned hard mask layer as an etching mask. The mask pattern and the patterned hard mask layer are removed. In one or more of the foregoing and following embodiments, the hard mask layer includes at least one selected from the group consisting of one or more of aluminum oxide, aluminum nitride, aluminum oxynitride, titanium oxide and titanium oxynitride. In one or more of the foregoing and following embodiments, a width of the trench is in a range from 10 nm to 150 nm. In one or more of the foregoing and following embodiments, the diffusion barrier includes at least one layer of TiAl, TiAlC, TaAl, TaAlC, TiN, TiSiN, Ru, WN, WCN, MoN or TaN. In one or more of the foregoing and following embodiments, the diffusion barrier includes at least one selected from the group consisting of one or more of aluminum oxide, aluminum nitride, aluminum oxynitride, titanium oxide and titanium oxynitride, and does not includes the dopant or includes a lower amount of the dopant than at least one of the first gate dielectric layer or the second gate dielectric layer. 
     In accordance with another aspect of the present disclosure, in a method of manufacturing a semiconductor device, a first gate dielectric layer is formed over a first channel region made of a first semiconductor material and over an isolation insulating layer. A second gate dielectric layer is formed over a second channel region made of a second semiconductor material and over the isolation insulating layer. The first gate dielectric layer is laterally in contact with the second gate dielectric layer at a boundary located over the isolation insulating layer. A third gate dielectric layer is formed over the first and second gate dielectric layers. By using a patterning operation, the first gate dielectric layer and the second gate dielectric layer are separated by a trench. One or more work function adjustment material (WFM) layers are formed over the third gate dielectric layer on the first gate dielectric layer and over the third gate dielectric layer on the second gate dielectric layer. A body gate electrode layer is formed over the one or more WFM layers. A part of the one or more WFM layers fills the trench. In one or more of the foregoing and following embodiments, at least one of the first gate dielectric layer or the second gate dielectric layer includes a dopant, a dopant concentration is different between the first gate dielectric layer and the second gate dielectric layer, and the dopant is at least one selected from the group consisting of La, Sc, Sr, Ce, Y, Dy, Eu and Yb. In one or more of the foregoing and following embodiments, the first, second and third gate dielectric layers each includes one selected from the group consisting of one or more of aluminum oxide, aluminum nitride, aluminum oxynitride, titanium oxide and titanium oxynitride. 
     The foregoing outlines features of several embodiments or examples so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments or examples introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.