Patent Publication Number: US-6711077-B2

Title: Wafer burn-in test and wafer test circuit

Description:
This is a divisional application of prior application Ser. No. 10/032,016 filed Dec. 31, 2001, now U.S. Pat. No. 6,570,796. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a wafer burn-in test and a wafer test circuit for a semiconductor memory device using a probe pad for contact, and in particular to a wafer burn-in test and a wafer test circuit which can cut down packaging expenses and improve F/T yield by performing a wafer burn-in test by using a pad for contact in a probe test of a wafer state. 
     2. Description of the Background Art 
     In general, a screening test is performed to identify a DRAM having a defect at an early stage. The screening test mostly employs a burn-in test mode (a high temperature high voltage operation test). The burn-in test operation exposes a potential defect in the DRAM in a short time by operating the DRAM in the worst conditions such as at a high temperature and a high voltage. In the burn-in test operation, an appropriate stress voltage, especially an accelerating stress voltage, is applied to the respective units of the chip to detect the defect. 
     The burn-in test operation is used not only for the DRAM but also for the other semiconductor memory devices. An internal power circuit for generating an internal power voltage Vint to the DRAM adjusts the internal voltage so that an internal circuit cannot receive an excessive stress voltage in the burn-in test operation, and thus applies only a stress voltage for screening thereto. 
     Generally, actual contact with the semiconductor memory device using a probe pad for contact is performed after a probe test of a wafer state and before packaging. Accordingly, when an inferior chip is not sufficiently screened in the probe test, if a defect occurs after packaging, the chip cannot be repaired. In order to solve the foregoing problem, the wafer burn-in test is executed in the wafer state before packaging. 
     FIG. 1 is a block diagram illustrating a conventional wafer burn-in test circuit including a first probe pad unit  1  for contact, a second probe pad unit  2  for contact, a first buffer unit  3 , a second buffer unit  4 , a decoder unit  5 , a data multiplexer unit  6 , a test mode block unit  7  and an array control unit  8 . 
     The first buffer unit  3  converts a signal BOP 0 IN inputted through the first probe pad unit  1  for contact into a CMOS level, and the second buffer unit  4  converts a signal BOP 1 IN inputted through the second probe pad unit  2  for contact into a CMOS level. 
     The decoder unit  5  receives the signals BOP 0  and BOP 1  from the first and second buffer units  3  and  4 , and generates a control signal BPX&lt;0:1&gt;. The data multiplexer unit  6  inputs/outputs a desired data bit based on the control signal BPX&lt;0:1&gt; from the decoder unit  5 . 
     The test mode block unit  7  generates a control signal TBIN&lt;0:1&gt; in the wafer burn-in test mode. The array control unit  8  controls bit lines, word lines and plate lines making up an access transistor (not shown) of a memory cell based on the control signal TBIN&lt;0:1&gt; from the test mode block unit  7 , thereby applying a stress voltage to the cell, bit line and storage node. 
     FIG. 2 is a circuit diagram illustrating the first buffer unit  3  of FIG.  1 . The first buffer unit  3  includes: a PMOS transistor MP 1  for transmitting a power voltage VDD to a node Nd 1  based on a power-up signal PUPB; a PMOS transistor MP 2  for transmitting the power voltage VDD to the node Nd 1  based on an initialization signal IDL; a PMOS transistor MP 3  for transmitting the power voltage VDD to the node Nd 1  based on a ground voltage VSS; a PMOS transistor MP 4  for transmitting the signal of the node Nd 1  to a node Nd 2  transmitting the signal BOP 0 IN from the first probe pad unit  1  based on the ground voltage VSS; an inverter IV 2  for receiving the signal of the node Nd 2 , and outputting an inverted signal to a node Nd 3 ; a PMOS transistor MP 5  for transmitting the power voltage VDD to the node Nd 2  based on the signal of the node Nd 3 ; and an inverter IV 3  for receiving the signal of the node Nd 3 , and outputting an inverted signal BOP 0 . 
     When the power-up signal PUPB has a high state, the power voltage VDD is supplied to the node Nd 1  through the PMOS transistors MP 1  and MP 3 , and the signal of the node Nd 1  is transmitted to the node Nd 2  through the PMOS transistor MP 4 . Therefore, the signal BOP 0 IN of the node Nd 2  has a high state during the power-up operation, and the output signal BOP 0  has a high state. That is, the first buffer unit  3  maintains the initial state during non-contact by the first probe pad unit  1 . 
     The second buffer unit  4  of FIG. 1 has the same constitution and operation as the first buffer unit  3  of FIG.  2 . Accordingly, the input signal BOP 1 IN of the second buffer unit  4  has a high state during the power-up operation, and the output signal BOP 1  has a high state. Identically, the second buffer unit  4  serves to maintain the initial state during non-contact by the second probe pad unit  2 . 
     FIG. 3 is a circuit diagram illustrating the decoder unit  5  of FIG.  1 . The decoder unit  5  includes: an inverter IV 10  for receiving the output signal BOP 0  from the first buffer unit  3 , and outputting an inverted signal; an inverter IV 20  for receiving the output signal BOP 1  from the second buffer unit  4 , and outputting an inverted signal; an inverter IV 30  for receiving the output signal from the inverter IV 20 , and outputting an inverted signal; a NAND gate ND for receiving the output signals from the inverters IV 10  and IV 20 ; inverters IV 50  and IV 60  connected in series, between an output node Nd 30  of the NAND gate ND and a node Nd 40  transmitting a control signal BPX 8 ; a NOR gate NR for receiving the output signal from the NAND gate ND and the output signal from the inverter IV 20 , and outputting a control signal BPX 4 ; and an inverter IV 40  connected between an output node Nd 20  of the inverter IV 30  and a node Nd 50  transmitting a control signal BPX 16 . 
     When the input signal BOP 0  from the first buffer unit  3  and the input signal BOP 1  from the second buffer unit  4  have a low state, the output signal BPX 8  has a high state, the output signal BPX 4  has a low state, and the output signal BPX 16  has a high state. When the input signal BOP 0  and the input signal BOP 1  have a high state, the output signal BPX 8  has a high state, the output signal BPX 4  has a low state, and the output signal BPX 16  has a low state. When the input signal BOP 0  has a low state and the input signal BOP 1  has a high state, the output signal BPX 8 , the output signal BPX 4  and the output signal BPX 16  have a low state. When the input signal BOP 0  has a high state and the input signal BOP 1  has a low state, the output signal BPX 8  has a high state, the output signal BPX 4  has a low state, and the output signal BPX 16  has a high state. 
     The data multiplexer unit  6  controls input/output of a desired data bit based on the output signal BPX&lt;0:1&gt; from the decoder unit  5 . 
     However, the conventional wafer burn-in test circuit has a disadvantage in that, although the number of prober pins for the wafer burn-in test is reduced in using the probe pad for the wafer burn-in test, the chip area is increased due to the probe pad. Moreover, since address information is required for the wafer burn-in test in the test mode using an address key, the number of the prober pins for the test is increased, thereby increasing the prober production cost and the setting time before the test. 
     SUMMARY OF THE INVENTION 
     Accordingly, it is an object of the present invention to provide a wafer burn-in test and a wafer test circuit which can cut down packaging expenses, improve F/T yield and reduce the production cost, by screening an inferior chip before packaging by executing a wafer burn-in test with a fuse and a probe pad for contact prior to the contact. 
     In order to achieve the above-described object of the invention, there is provided a wafer test circuit including: a buffer unit for initializing an input signal inputted through a probe pad unit having a floating state during non-contact before blowing a wafer, converting the signal into a CMOS level, and outputting the converted signal; a fuse unit for generating a first control signal for selecting a signal generation path for the test operation of a wafer state before blowing the wafer, and a signal generation path for the operation of a bit line after blowing the wafer; a multiplexer unit for receiving the first control signal from the fuse unit and the output signal from the buffer unit, generating a second control signal for the wafer test operation before blowing the wafer, and generating a third control signal for the operation of the bit line after blowing the wafer based on the first control signal; and a decoder unit for receiving the output signal from the multiplexer unit, and generating a decoded signal. 
     In another aspect of the present invention, a wafer test circuit includes: a first buffer unit for initializing an input signal inputted through a probe pad unit having a floating state during non-contact before blowing a wafer, converting the signal into a CMOS level, and outputting the converted signal; a fuse unit for generating a first control signal for selecting a signal generation path for the test operation of a wafer state before blowing the wafer, and a signal generation path for the operation of a bit line after blowing the wafer; a multiplexer unit for receiving the first control signal from the fuse unit and the output signal from the first buffer unit, generating a second control signal for the wafer test operation before blowing the wafer, and generating a third control signal for the operation of the bit line after blowing the wafer based on the first control signal; and a second buffer unit for receiving the output signal from the multiplexer unit, and generating a buffered signal. 
     In still another aspect of the present invention, a wafer burn-in test circuit includes: first and second probe pad units having a floating state before blowing a wafer; a first buffer unit for initializing a signal from the first probe pad unit in a power-up operation based on a power-up signal, converting the signal into a CMOS level, and outputting the converted signal; a second buffer unit for initializing a signal from the second probe pad unit during the power-up operation based on the power-up signal, converting the signal into a CMOS level, and outputting the converted signal; a fuse unit for generating a first control signal for selecting a signal generation path for a burn-in test operation of a wafer state before blowing the wafer, and a signal generation path for the operation of a bit line after blowing the wafer; a decoder and multiplexer unit for receiving the first control signal from the fuse unit and the output signals from the first and second buffer units, generating a second control signal for the wafer test operation before blowing the wafer, and generating a third control signal for the operation of the bit line after blowing the wafer based on the first control signal; a test mode block unit for generating a fourth control signal in the wafer burn-in test mode based on the second control signal from the decoder and multiplexer unit; an array control unit for controlling bit lines, word lines and plate lines making up an access transistor of a memory cell based on the fourth control signal from the test mode block unit, and applying a stress to the cell, bit line and storage node; and a data multiplexer unit for controlling input/output of a desired data bit based on the third control signal from the decoder and multiplexer unit. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention will become better understood with reference to the accompanying drawings which are given only by way of illustration and thus are not limitative of the present invention, wherein: 
     FIG. 1 is a block diagram illustrating a conventional wafer burn-in test circuit; 
     FIG. 2 is a circuit diagram illustrating a buffer unit of the circuit of FIG. 1; 
     FIG. 3 is a circuit diagram illustrating a decoder unit of the circuit of FIG. 1; 
     FIG. 4 is a block diagram illustrating a wafer burn-in test circuit in accordance with the present invention; 
     FIG. 5 is a circuit diagram illustrating a buffer unit of the circuit of FIG. 4; 
     FIG. 6 is a circuit diagram illustrating a fuse unit of the circuit of FIG. 4; and 
     FIG. 7 is a circuit diagram illustrating a decoder and multiplexer unit of the circuit of FIG.  4 . 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     A wafer burn-in test circuit and a wafer test circuit in accordance with a preferred embodiment of the present invention will now be described in detail with reference to the accompanying drawings. 
     In the following description, same drawing reference numerals are used for the same elements even in different drawings, and explanations thereof will be omitted. 
     FIG. 4 is a block diagram illustrating a wafer burn-in test circuit in accordance with the present invention, including a first probe pad unit  11  for contact, a second probe pad unit  22  for contact, a fuse unit  77 , a first buffer unit  33 , a second buffer unit  44 , a decoder and multiplexer unit  55 , a data multiplexer unit  66 , a test mode block unit  99  and an array control unit  88 . 
     The first buffer unit  33  converts a signal BOP 0 IN inputted through the first probe pad unit  31  into a CMOS level, and maintains an initial state during non-contact by the first probe pad unit  11 . 
     In the same manner, the second buffer unit  44  converts a signal BOP 1 IN inputted through the second probe pad unit  22  into a CMOS level, and maintains an initial state during non-contact by the second probe pad unit  22 . 
     The fuse unit  77  generates a control signal CTL for enabling a signal generation path for a burn-in test operation of a wafer state before blowing, and a signal generation path for the operation of a bit line after the blowing. 
     The decoder and multiplexer unit  55  receives the control signal CTL from the fuse unit  77  and the output signals BOP 0  and BOP 1  from the first and second buffer units  33  and  44 , generates a control signal WFBIN&lt;0:1&gt; for the wafer test operation before the blowing, and generates a control signal BPX&lt;0:1&gt; for the operation of the bit line after blowing based on the control signal CTL. 
     The test mode block unit  99  generates a control signal TBIN&lt;0:1&gt; during the wafer burn-in test mode based on the control signal WFBIN&lt;0:1&gt; from the decoder and multiplexer unit  55 . The array control unit  88  controls bit lines, word lines and plate lines making up an access transistor (not shown) of a memory cell based on the control signal TBIN&lt;0:1&gt; from the test mode block unit  99 , thereby applying a stress voltage to the cell, bit line and storage node. 
     The data multiplexer unit  66  controls input/output of a desired data bit based on the control signal BPX&lt;0:1&gt; from the decoder and multiplexer unit  55 . 
     FIG. 5 is a circuit diagram illustrating the first buffer unit  33  of the circuit of FIG.  4 . The first buffer unit  33  includes: a PMOS transistor MP 1  for transmitting a power voltage VDD to a node Nd 1  when a power-up signal PUPB has a high state; a PMOS transistor MP 2  for transmitting the power voltage VDD to the node Nd 1  when an initialization signal IDL has a low state; a PMOS transistor MP 3  for transmitting the power voltage VDD to the node Nd 1  based on a ground voltage VSS; a PMOS transistor MP 4  for transmitting the signal of the node Nd 1  to a node Nd 2  transmitting the signal BOP 0 IN from the first probe pad unit  11  based on the ground voltage VSS; an inverter IV 2  for receiving the signal of the node Nd 2 , and outputting an inverted signal to a node Nd 3 ; a PMOS transistor MP 5  for transmitting the power voltage VDD to the node Nd 2  based on the signal of the node Nd 3 ; and an inverter IV 3  for receiving the signal of the node Nd 3 , and outputting an inverted signal BOP 0 . 
     When the wafer has a pre-contact state, the first probe pad unit  11  has a floating state. Here, when the power-up signal PUPB has a high state, the power voltage VDD is supplied to the node Nd 1  through the PMOS transistors MP 1  and MP 3 , and the signal of the node Nd 1  is transmitted to the node Nd 2  through the PMOS transistor MP 4 . Therefore, the signal BOP 0 IN of the node Nd 2  has a high state during the power-up operation, and the output signal BOP 0  has a high state. That is, the first buffer unit  33  maintains the initial state during non-contact by the first probe pad unit  11 . 
     The second buffer unit  44  of FIG. 4 has the same constitution and operation as the first buffer unit  33  of FIG.  5 . Accordingly, the input signal BOP 1 IN of the second buffer unit  44  has a high state during the power-up operation, and the output signal BOP 1  has a high state. Identically, the second buffer unit  44  serves to maintain the initial state during non-contact by the second probe pad unit  22 . 
     FIG. 6 is a circuit diagram illustrating the fuse unit  77  of the circuit of FIG.  4 . The fuse unit  77  includes: a fuse connected between the power voltage VDD and a node Nd 100 ; an NMOS transistor MN 1  for transmitting the signal of the node Nd 100  to a node Nd 200  based on an enable signal SELIN; NMOS transistors MN 2  and MN 3  connected in series between the node Nd 200  and the ground voltage VSS, for discharging the signal of the node Nd 200  to the ground voltage VSS based on the power voltage VDD applied to gates thereof; an inverter IV 100  for receiving the signal of the node Nd 2 , and outputting an inverted control signal CTL; and an NMOS transistor MN 4  for discharging the signal of the node Nd 100  to the ground voltage VSS based on the control signal CTL. 
     Firstly, since the wafer has a pre-blown state, the node Nd 100  has a high state based on the power voltage VDD supplied through the fuse, and the control signal CTL which is the output signal has a low state. 
     When the control signal CTL has a low state, the decoder and multiplexer unit  55  intercepts the path for operating the bit line, and generates the signal for the wafer burn-in test operation. 
     FIG. 7 is a circuit diagram illustrating the decoder and multiplexer unit  55  of the circuit of FIG.  4 . The decoder and multiplexer unit  55  includes: a transmission gate SW 1  for transmitting the signal BOP 0  from the first buffer unit  33  to a node Nd 1000  when the output signal CTL from the fuse unit  77  has a high state; a PMOS transistor MP 1000  for transmitting the power voltage VDD to the node Nd 1000  when the output signal CTL from the fuse unit  77  has a low state; an inverter IV 2000  for inverting and outputting the signal of the node Nd 1000 ; a transmission gate SW 2  for transmitting the signal BOP 1  from the second buffer unit  44  to a node Nd 2000  when the output signal CTL from the fuse unit  77  has a high state; a PMOS transistor MP 2000  for transmitting the power voltage VDD to the node Nd 1000  when the output signal CTL from the fuse unit  77  has a low state; an inverter IV 3000  for inverting the signal of the node Nd 2000 , and generating a control signal BPX 16 ; a NAND gate ND for receiving the output signal from the inverter IV 2000  and the signal of the node Nd 2000 , and outputting a control signal BPX 8 ; and a NOR gate NR 1  for receiving the control signal BPX 8  and the control signal BPX 16 , and generating a control signal BPX 4 . In addition, the decoder and multiplexer unit  55  further includes: a transmission gate SW 3  for transmitting the signal BOP 1  from the second buffer unit  44  to a node Nd 3000  when the output signal CTL from the fuse unit  77  has a low state; a PMOS transistor MP 3000  for transmitting the power voltage VDD to the node Nd 3000  when the output signal CTL from the fuse unit  77  has a high state; an inverter IV 5000  for inverting the signal of the node Nd 3000 , and outputting a control signal WFBIN 0 ; a transmission gate SW 4  for transmitting the signal BOP 0  from the first buffer unit  33  to a node Nd 4000  when the output signal CTL from the fuse unit  77  has a low state; a PMOS transistor MP 4000  for transmitting the power voltage VDD to the node Nd 4000  when the output signal CTL from the fuse unit  77  has a high state; an inverter IV 6000  for inverting the signal of the node Nd 4000 , and generating a control signal WFBIN 1 ; and a NOR gate NR 2  for receiving the output signals from the inverters IV 5000  and IV 6000 , and generating a control signal WFBIN 2 . 
     Since the output signal CTL from the fuse unit  77  has a low state before blowing the wafer, the transmission gates SW 1  and SW 2  are turned off, so as not to generate the control signals BPX 8 , BPX 4  and BPX 16  for controlling the operation of the data multiplexer unit  66 . However, the transmission gates SW 3  and SW 4  are turned on, to receive the signals BOP 0  and BOP 1  from the first and second buffer units  33  and  44  and to generate the control signals WFBIN, WFBIN 1  and WFBIN 2  to the test mode block unit  99 . Accordingly, the test mode block unit  99  controls the array control unit  88  based on the control signals WFBIN, WFBIN 1  and WFBIN 2  from the decoder and multiplexer unit  55 , thereby performing a desired wafer burn-in test operation. That is, the array control unit  88  controls the bit lines, word lines and plate lines making up the access transistor of the memory cell based on the control signal TBIN&lt;0:1&gt; from the test mode block unit  99 , and applies a stress to the cell, bit line and storage node, thereby executing the wafer burn-in test operation. 
     On the other hand, when the fuse is blown after the probe test of the wafer state, the output signal CTL from the fuse unit  77  has a high state, and the transmission gates SW 3  and SW 4  are turned off, thereby disabling the control signals WFBIN, WFBIN 1  and WFBIN 2 . Therefore, the wafer burn-in test operation is not performed. In the case that the output signal CTL from the fuse unit  77  has a high state, the transmission gate SW 3  and SW 4  are turned on, and thus the control signals BPX 8 , BPX 4  and BPX 16  are generated based on a contact property of the probe pad. As a result, data input/output of the bit line is performed by the data multiplexer unit  66 . 
     As discussed earlier, in accordance with the present invention, the wafer burn-in test and the wafer test circuit can cut down packaging expenses and improve F/T yield, by screening an inferior chip before packaging by executing the wafer burn-in test with the fuse and the probe pad for contact prior to the contact. Moreover, an additional probe pad for the wafer burn-in test is not required, so that chip area is reduced. 
     As the present invention may be embodied in several forms without departing from the spirit or essential characteristics thereof, it should also be understood that the above-described embodiment is not limited by any of the details of the foregoing description, unless otherwise specified, but rather should be construed broadly within its spirit and scope as defined in the appended claims, and therefore all changes and modifications that fall within the metes and bounds of the claims, or equivalences of such metes and bounds are intended to be embraced by the appended claims.