Patent Publication Number: US-2023134961-A1

Title: Base die, memory system, and semiconductor structure

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application claims priority to Chinese Patent Application No. 202111275416.0 filed on Oct. 29, 2021, the disclosure of which is hereby incorporated by reference in its entirety. 
     BACKGROUND 
     Semiconductor memory can be divided into non-volatile memory and volatile memory. A dynamic random access memory (DRAM), as a volatile memory, has the advantages of high storage density and high read/write speed, and is widely used in various electronic systems. 
     As the DRAM has an increasingly advanced process and higher storage density, data stored in the DRAM may have errors, which may seriously affect the performance of the DRAM. Therefore, the error checking and correction or error correction coding technology is usually used in the DRAM to detect or correct errors of the stored data. 
     SUMMARY 
     Embodiments of the present disclosure relate to the technical field of semiconductors, and in particular, to a base die, a memory system, and a semiconductor structure. 
     According to some embodiments of the present disclosure, in one aspect of the embodiments of the present disclosure, a base die applied to a memory system is provided; the base die is configured to receive a first data and a first encoded data in a writing phase, where the first encoded data is obtained by performing a first error correction code (ECC) encoding processing on the first data, perform a second ECC encoding processing on the first data and the first encoded data to generate a second encoded data, and transmit a second data to a memory die in the writing phase, where the second data includes the first data, the first encoded data, and the second encoded data; the base die is further configured to receive the second data from the memory die in a reading phase, perform a first error checking and correction processing, and transmit a third data in the reading phase, where the third data includes the first data on which the first error checking and correction processing has been performed, and the first encoded data on which the first error checking and correction processing has been performed. 
     According to some embodiments of the present disclosure, in another aspect of the embodiments of the present disclosure, a memory system is provided, including a processor, a base die, and a memory die; the processor is configured to perform a first ECC encoding processing on first data in a writing phase to generate first encoded data, and transmit the first data and the first encoded data to the base die; the base die is configured to receive the first data and the first encoded data in the writing phase, perform a second ECC encoding processing to generate a second encoded data, and transmit a second data to the memory die in the writing phase, where the second data includes the first data, the first encoded data, and the second encoded data; and receive the second data from the memory die in a reading phase, perform a first error checking and correction processing, and transmit a third data to the processor in the reading phase, where the third data includes the first data on which the first error checking and correction processing has been performed and the first encoded data on which the first error checking and correction processing has been performed; the memory die is configured to receive the second data from the base die in the writing phase, store the second data, and transmit the second data to the base die in the reading phase; the processor is further configured to receive the third data from the base die in the reading phase, perform a second error checking and correction processing on the third data, and transmit the first data on which the second error checking and correction processing has been performed. 
     According to some embodiments of the present disclosure, in further another aspect of the embodiments of the present disclosure, a semiconductor structure is further provided, including: a carrier substrate; and the memory system described above, where the processor and the base die are both located on a surface of the carrier substrate, and the memory die is located on a surface of the base die that is away from the carrier substrate. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       One or more embodiments are exemplified by corresponding drawings, and these exemplified descriptions do not constitute a limitation on the embodiments. Components with the same reference numerals in the drawings are denoted as similar components, and the drawings are not limited by scale unless otherwise specified. 
         FIG.  1    is a schematic structural diagram of a semiconductor structure; 
         FIG.  2    is a schematic diagram of data transmission in the semiconductor structure provided in  FIG.  1   ; 
         FIG.  3    is a first schematic structural diagram of a base die according to an embodiment of the present disclosure; 
         FIG.  4    is a second schematic structural diagram of a base die according to an embodiment of the present disclosure; 
         FIG.  5    is a third schematic structural diagram of a base die according to an embodiment of the present disclosure; 
         FIG.  6    is a fourth schematic structural diagram of a base die according to an embodiment of the present disclosure; 
         FIG.  7    is a first schematic structural diagram of a memory system according to an embodiment of the present disclosure; 
         FIG.  8    is a second schematic structural diagram of a memory system according to an embodiment of the present disclosure; 
         FIG.  9    is a third schematic structural diagram of a memory system according to an embodiment of the present disclosure; 
         FIG.  10    is a fourth schematic structural diagram of a memory system according to an embodiment of the present disclosure; and 
         FIG.  11    is a cross-sectional schematic structural diagram of a semiconductor structure according to an embodiment of the present disclosure. 
     
    
    
     DETAILED DESCRIPTION 
       FIG.  1    is a schematic structural diagram of a semiconductor structure;  FIG.  2    is a schematic diagram of data transmission in the semiconductor structure provided in  FIG.  1   . 
     Referring to  FIG.  1   , a semiconductor structure may include: a substrate  11 ; a base die  12  and a processor  13  that are located on a surface of the substrate  11 ; and a plurality of core dies  14  stacked on the base die  12 , where the core dies  14  may be DRAM dies. Referring to  FIG.  2   , a data transmission process in the semiconductor structure includes: in a writing phase, the processor  13  transmits data to the base die  12 , and the base die  12  transmits the data to the core die  14 ; before transmitting the data, the processor  13  may first perform error correction code (ECC) encoding processing on the data. In a reading phase, the core die  14  transmits data to the base die  12 , and then the base die  12  transmits the data to the processor  13 ; the processor  13  receives the data and performs ECC decoding processing on the data, to implement detect and correct errors of the data. 
     Obviously, in the semiconductor structure, the base die  12  does not participate in the error checking and correction processing. That is, the base die  12  does not have an ECC encoding function and the corresponding error checking and correction function, and the error checking needs to be completed by the processor  13  or the core die  14 . This makes the originally tight die areas of the processor  13  and the core die  14  even tighter, which affects the performance of the processor  13  and the core die  14 . Therefore, the storage performance of the entire semiconductor structure still needs to be improved. 
     Embodiments of the present disclosure provide a base die, a memory system, and a semiconductor structure. The base die has an error checking and correction function.  FIG.  3    is a first schematic structural diagram of a base die according to an embodiment of the present disclosure;  FIG.  4    is a second schematic structural diagram of a base die according to an embodiment of the present disclosure;  FIG.  5    is a third schematic structural diagram of a base die according to an embodiment of the present disclosure; and  FIG.  6    is a fourth schematic structural diagram of a base die according to an embodiment of the present disclosure. 
     In order to make the objectives, technical solutions and advantages of the embodiments of the present disclosure clearer, the embodiments of the present disclosure are described below with reference to the drawings. Those skilled in the art should understand that many technical details are proposed in the embodiments of the present disclosure to make the present disclosure better understood. However, even without these technical details and various changes and modifications made based on the following embodiments, the technical solutions claimed in the present disclosure may still be realized. 
     Referring to  FIG.  3   , a base die  100  is applied to a memory system. The base die is configured to receive first data data 1  and first encoded data ecc 1  in a writing phase, where the first encoded data ecc 1  is obtained by performing a first ECC encoding processing on the first data data 1 , perform a second ECC encoding processing on the first data data 1  and the first encoded data ecc 1  to generate a second encoded data ecc2, and transmit a second data data 2  to a memory die in the writing phase, where the second data data 2  includes the first data data 1 , the first encoded data ecc 1 , and the second encoded data ecc 2 . The base die  100  is further configured to receive the second data data 2  from the memory die in a reading phase, perform a first error checking and correction processing, and transmit a third data data 3  in the reading phase, where the third data data 3  is the first data data 1  on which the first error checking and correction processing has been performed and the first encoded data ecc 1  on which the first error checking and correction processing has been performed. 
     In the embodiments of the present disclosure, the base die  100  participates in the ECC encoding processing and the error checking and correction processing in the data transmission process. Specifically, the base die  100  can perform the second ECC encoding processing on the first data data 1  and the first encoded data ecc 1 , and can perform the first error checking and correction processing on the first data data 1  and the first encoded data ecc 1  that are transmitted from the memory die, to check whether the first data data 1  and the first encoded data ecc 1  have errors in the writing and reading phases, and correct errors in the first data data 1  or the first encoded data ecc 1 , which helps improve the error checking and correction capability of the memory system and rationally use the die area of the base die  100 . In addition, the base die  100  can perform error checking and correction on the first encoded data ecc 1 , which ensures the accuracy of the first encoded data ecc 1 . Subsequently, during transmission of the first data data 1 , error checking and correction is further performed based on the first encoded data ecc 1  with accuracy, thereby further improving the accuracy of the first data data 1  during transmission. 
     In some embodiments, the base die  100  may be connected between a first port A and a second port B, where the first port A is connected to a data transmission port of a processor of the memory system, and the second port B is connected to a data transmission port of a memory die of the memory system. It may be understood that, the first port A and the second port B are general terms. The first port A includes a plurality of data transmission ports, and the second port B includes a plurality of data transmission ports. The number of data transmission ports is correlated to the number of pieces of data to be transmitted by the base die  100 . For example, the number of data transmission ports is the same as the number of pieces of data to be transmitted by the base die  100 , and one piece of data may be transmitted through one data transmission port. 
     The ECC encoding processing and the error checking and correction processing are both used for implementing ECC error checking and correction, to discover and locate errors of the first data during transmission and correct the errors. In some embodiments, the ECC error checking and correction may adopt an error correction mechanism of Reed Solomon Code (RS); accordingly, the ECC encoding processing may adopt an RS encoding algorithm to generate encoded data, and decoding processing in the error checking and correction processing may adopt an RS decoding algorithm. In other embodiments, the ECC error checking and correction may adopt an error correction mechanism of Hamming code; accordingly, the ECC encoding processing may adopt a Hamming code encoding algorithm to generate encoded data, and decoding processing in the error checking and correction processing may adopt a Hamming code decoding algorithm. 
     In some embodiments, the first data data 1  may be 256-bit data, and correspondingly, the first encoded data ecc 1  may be 16-bit data. It may be understood that, in other embodiments, the first encoded data may include different numbers of bits depending on specific algorithms adopted in the first ECC encoding processing. In addition, the first data data 1  may include other numbers of bits, for example,  128  or  512 . 
     In some embodiments, the first ECC encoding processing and the second ECC encoding processing are implemented by different encoding algorithms Accordingly, the first error checking and correction processing and the second error checking and correction processing that is performed by the processor are implemented by different decoding algorithms In this way, the error checking and correction is implemented by different compiling algorithms, which helps further improve the accuracy of data error correction and the capability of data error checking and correction and makes it easier for the base die  100  to recognize different encoded data. For example the first encoded data ecc 1  is 16-bit data, and the second encoded data ecc 2  may be 32-bit data. It should be noted that, in other embodiments, the first ECC encoding processing and the second ECC encoding processing may be implemented by the same encoding algorithm. In addition, the encoding algorithm adopted in the second ECC encoding processing corresponds to a decoding algorithm adopted in the first error checking and correction processing. 
       FIG.  4    is a second schematic structural diagram of a base die according to an embodiment of the present disclosure. Referring to  FIG.  4   , in some embodiments, the base die  100  may include: a second encoding module  110 , configured to receive the first data data 1  and the first encoded data ecc 1  in the writing phase, and perform the second ECC encoding processing to generate the second encoded data ecc 2 ; and a first error checking and correction module  120 , configured to receive the second data data 2  in the reading phase, and perform the first error checking and correction processing. 
     The second encoding module  110  is connected between a data transmission port of the processor and a data transmission port of the memory die. The first data data 1  and the first encoded data ecc 1  are transmitted to the second encoding module  110  as a whole. The first data data 1  transmitted to the second encoding module  120  on which data checking and correction has not been performed. The first data data 1  and the first encoded data ecc 1  as a whole correspond to the second encoded data ecc 2  generated by the second encoding module  120 . 
     The first error checking and correction module  120  is connected between the data transmission port of the processor and the data transmission port of the memory die. The first error checking and correction module  120  performs error checking and correction on the first data data 1  and the first encoded data ecc 1  by using the second encoded data ecc 2 . Specifically, paths on which the first error checking and correction module  120  can find data errors include: a transmission path through which the second encoding module  110  writes data into the memory die, and a transmission path on which the memory die reads data to the first error checking and correction module  120 . 
     The second ECC encoding processing and the first error checking and correction processing can perform error checking and correction on data transmission paths between the base die  100  and the memory die, which helps improve the capability of checking and correcting data errors. It should be noted that, the terms “first”, “second” and “third” in the embodiments of the present disclosure are merely for descriptive distinction but are not intended to particularly limit the sequence of the corresponding features. 
     The working principle of the base die  100  is described in detail below with reference to  FIG.  4   . 
     In the writing phase, the first data data 1  and the first encoded data ecc 1  from the processor are transmitted to the second encoding module  110 . The second encoding module  110  performs the second ECC encoding processing on the first data data 1  and the first encoded data ecc 1  to generate the second encoded data ecc 2 . Then, the first data data 1 , the first encoded data ecc 1 , and the second encoded data ecc 2  are written into the memory die. For example, the first data data 1  includes 256 bits, and the first encoded data ecc 1  includes 16 bits. The 272 bits of data are transmitted to the second encoding module  110 , and the generated second encoded data ecc 2  includes 32 bits. Therefore, the 272+32 bits of data are stored into the memory die. 
     In the reading phase, the first data data 1 , the first encoded data ecc 1 , and the second encoded data ecc 2  from the memory die are read out and transmitted to the first error checking and correction module  120 . The first error checking and correction module  120  performs the first error checking and correction processing, to obtain the first data data 1  on which the first error checking and correction processing has been performed and the first encoded data ecc 1  on which the first error checking and correction processing has been performed. The first data data 1  on which the first error checking and correction processing has been performed and the first encoded data ecc 1  on which the first error checking and correction processing has been performed can be transmitted to the processor. For example, the 272+32 bits of data are read out from the memory die. The first error checking and correction module  120  performs the first error checking and correction processing to output 272-bit data, where 256 bits of the data are the first data data 1  on which the first error checking and correction processing has been performed, and the 16 bits of data are the first encoded data ecc 1  on which the first error checking and correction processing has been performed. Then, the 272-bit data can be transmitted to the processor, so that the processor can perform the second error checking and correction processing. 
     In this way, in the reading phase, the base die  100  can perform the first error checking and correction processing on the first data data 1  and the first encoded data ecc 1 , so that the first data data 1  and the first encoded data ecc 1  transmitted back to the processor are data on which the error checking and correction processing has been performed. That is, the accuracy of the first data data 1  and the first encoded data ecc 1  transmitted back to the processor is improved. The high accuracy of the first encoded data ecc 1  helps further improve the accuracy of the error checking and correction performed on the first data data 1  during subsequent transmission. Then, the processor performs the second error checking and correction processing on the first data data 1  and the first encoded data ecc 1 , to obtain the first data data 1  on which the second error checking and correction processing has been performed. The first data data 1  on which the second error checking and correction processing has been performed will also have higher accuracy. 
     Based on the above, the base die  100  helps improve the overall accuracy of data error checking and correction of the memory system. In addition, the memory die in the memory system does not need to have the encoding processing and the error checking and correction processing, and the base die  100  can share the encoding processing function and the error checking and correction function required by the processor, which helps improve the performance of the processor and memory die and rationally use the die area of the base die  100 , thereby alleviating the pressure on die areas of the processor and the memory die, and improving the storage performance of the memory system. 
       FIG.  5    is a third schematic structural diagram of a base die according to an embodiment of the present disclosure. Referring to  FIG.  5   , in some embodiments, the base die  100  may further include: a first deserializer module  130 , configured to receive the first data data 1  and the first encoded data ecc 1  in the writing phase, perform a first deserialization processing on the first data data 1  and the first encoded data ecc 1 , and transmit the first data data 1  and the first encoded data ecc 1  on which the first deserialization processing has been performed to the second encoding module  110 ; and a first serializer module  140 , configured to receive the third data data 3  in the reading phase, perform a first serialization processing on the third data data 3 , and transmit the third data data 3  on which the first serialization processing has been performed to the processor. 
     The first deserializer module  130  and the first serializer module  140  can reduce the number of transmission channels between the base die  100  and the processor, and increase the number of bits transmitted on each transmission channel. In addition, as the number of transmission channels decreases, the number of data transmission ports required by the base die  100  and the processor can be reduced, to save the die area of the base die  100  and the die area of the processor. The first data data 1  and the first encoded data ecc 1  are transmitted to the first deserializer module  130  in a serial manner. The first deserializer module  130  is also known as a deserializer, which deserializes the first data data 1  and the first encoded data ecc 1 . The first serializer module  140  performs serialization processing on the third data data 3  and transmits the third data data 3  on which the serialization processing has been performed. The first serializer module  140  is also known as a serializer. 
     For example, the first data data 1  includes 256 bits, and the first data data 1  is transmitted to the first deserializer module  130  through 32 transmission channels. The first encoded data ecc 1  includes 16 bits, and the first encoded data ecc 1  is transmitted to the first deserializer module  130  through 2 transmission channels. After the first data data 1  and the first encoded data ecc 1  are deserialized by the first deserializer module  130 , the first data data 1  is transmitted to the first error checking and correction module  110  by using 256 transmission channels, and the first encoded data ecc 1  is transmitted to the first error checking and correction module  110  through 16 transmission channels. 
     For example, 256 bits of the data are the first data data 1  on which the first error checking and correction processing has been performed, and 16 bits of the data are the first encoded data ecc 1  on which the first error checking and correction processing has been performed. After the serialization processing by the first serializer module  140 , the third data data 3  is converted into 32+2 streams of data. Correspondingly, the 32+2 streams of data may be transmitted through 32+2 transmission channels, where 32 streams of the data are the first data data 1  on which the first error checking and correction processing has been performed, and 2 streams of the data are the first encoded data ecc 1  on which the first error checking and correction processing has been performed. Referring to  FIG.  5   , in some embodiments, in addition to the first deserializer module  130  and the first serializer module  140 , the base die  100  may further include: a second serializer module  150 , configured to receive the second data data 2  from the second encoding module  110  in the writing phase, perform a second serialization processing, and transmit the second data data 2  on which the second serialization processing has been performed to the memory die; and a second deserializer module  160 , configured to receive the second data data 2  from the memory die in the reading phase, perform a second deserialization processing, and transmit the second data data 2  on which the second deserialization processing has been performed to the error checking and correction module  120 . 
     The second serializer module  150  performs serialization processing on the second data data 2 , which helps reduce the number of transmission channels between the base die  100  and the memory die, so as to reduce the number of data transmission ports required by the base die  100  and the memory die, thereby saving the die area of the base die  100  and the die area of the memory die. For example, if the first data includes 256 bits, the first encoded data ecc 1  includes 16 bits, and the second encoded data includes 32 bits, after serialization processing by the second serializer module  150 , the second data data 2  can be transmitted by using 128+8+16 transmission channels, where the 128 transmission channels transmit the first data data 1 , the 8 transmission channels transmit the first encoded data ecc 1 , and the 16 transmission channels transmit the second encoded data ecc 2 . 
     In some embodiments, the base die  100  may be further configured to generate a first error checking marker signal during the first error checking and correction processing, and record, based on the first data data 1 , the first encoded data ecc 1 , and the second encoded data ecc 2  during transmission. Specifically, if the first data data 1 , the first encoded data ecc 1 , or the second encoded data ecc 2  has an error during transmission, the first error checking marker signal is generated; if none of the first data data 1 , the first encoded data ecc 1 , and the second encoded data ecc 2  has an error during transmission, no first error checking marker signal is generated. In addition, in some embodiments, the first error checking marker signal is defined as follows: if the first data data 1 , the first encoded data ecc 1 , or the second encoded data ecc 2  has an error during transmission, the first error checking marker signal is 1; if the first data data 1 , the first encoded data ecc 1 , and the second encoded data ecc 2  have no error during transmission, the first error checking marker signal is 0. In other embodiments, the first error checking marker signal may alternatively be defined as follows: if the first data data 1 , the first encoded data ecc 1 , or the second encoded data ecc 2  has an error during transmission, the first error checking marker signal is 0; if the first data data 1 , the first encoded data ecc 1 , and the second encoded data ecc 2  have no error during transmission, the first error checking marker signal is 1. 
     Through the first error checking marker signal, it can be learned whether the first data data 1 , the first encoded data ecc 1 , or the second encoded data ecc 2  transmitted on the data transmission path from the processor to the base die  100  has an error in the writing phase, and whether the first data data 1 , the first encoded data ecc 1 , or the second encoded data ecc 2  transmitted on the data transmission path from the memory die to the base die has an error in the reading phase. 
     As shown in  FIG.  6   ,  FIG.  6    is a schematic structural diagram based on  FIG.  4   . In some embodiments, the base die  100  may further include: a first memory cache module  101 , configured to store the error of the first data data 1 , the error of the first encoded data ecc 1 , and the error of the second encoded data ecc 2  during transmission; and a first command module  102 , configured to receive a first polling instruction PS 1 , and generate a first command signal CMD 1  and a first clock signal CLK 1 . The first memory cache module  101  is further configured to output a first representation signal flag 1  based on the first command signal CMD 1  and the first clock signal CLK 1 , where the first representation signal flag 1  represents the error of the first data data 1 , the error of the first encoded data ecc 1 , or the error of the second encoded data ecc 2  during transmission. 
     In some embodiments, if no first polling instruction PS 1  is received, the first memory cache module  101  only stores the error of first data data 1 , the error of the first encoded data ecc 1 , and the error of the second encoded data ecc 2  during transmission. After receiving the first polling instruction PS 1 , the first command module  102  controls the first memory cache module  101  to output the first representation signal flag 1  that represents the error of the first data data 1 , the error of the first encoded data ecc 1 , or the error of the second encoded data ecc 2  during transmission. The error of the first data data 1 , the error of the first encoded data ecc 1 , and the error of the second encoded data ecc 2  can be obtained based on the first representation signal flag 1 . 
     In some embodiments, the first representation signal flag 1  may be a binary string. For example, if an error of the first data data 1 , the first encoded data ecc 1 , or the second encoded data ecc 2  during transmission is detected, 1 is recorded; if no error of the first data data 1 , the first encoded data ecc 1 , or the second encoded data ecc 2  during transmission is detected, 0 is recorded. In this way, after a period of time, the first representation signal flag 1  is a binary string of 0s and 1s. In other embodiments, the first representation signal flag 1  may alternatively be a decimal value. For example, the first memory cache module  101  may be a counter, and if an error of the first data data 1 , the first encoded data ecc 1 , or the second encoded data ecc 2  during transmission is detected, the count is incremented by 1. In this way, after a period of time, the first representation signal flag 1  is a decimal value related to the number of errors. 
     In some embodiments, the first memory cache module  101  may be a first input first output (FIFO) register. By using the FIFO register as the first memory cache module  101 , a continuous data stream can be cached, to avoid data missing during a storage operation. In addition, the error of the first data data 1  during transmission can be pushed and stored collectively, which can avoid frequent bus operations and help improve the data transmission speed. 
     In some embodiments, the first clock signal CLK 1  may be generated by the first command module  102  independently; in other embodiments, the first clock signal CLK 1  may alternatively be provided from the external, for example, provided by a processor that generates the first polling instruction PS 1 . 
     The base die  100  provided in the foregoing embodiment not only has a data transmission function, but also has an ECC encoding processing function and an error checking and correction processing function. In this way, the die area of the base die  100  can be effectively used, to reduce the pressure on the die areas of the processor and the memory die and save the die areas of the processor and the memory die. 
     Moreover, the base die  100  can perform the second ECC encoding processing on the first data data 1  and the first encoded data ecc 1  to obtain the second encoded data ecc2, and can transmit the second encoded data ecc2, the first encoded data ecc 1 , and the first data data 1  to the memory die, so that the first error checking and correction processing is performed based on the second encoded data in the reading phase. Therefore, the error of the first data data 1  and the error of the first encoded data ecc 1  in the writing phase or the reading phase can be checked and corrected; moreover, the first data data 1  on which the first error checking and correction processing has been performed and the first encoded data ecc 1  on which the first error checking and correction processing has been performed can be transmitted to the processor, so that the processor performs error checking and correction processing again, thereby improving the error checking and correction capability of the memory system and the accuracy of the data error checking and correction. In addition, compared with the solution in which the base die does not perform the error checking and correction on the first encoded data, in the embodiments of the present disclosure, the base die  100  performs error checking and correction on the first encoded data ecc 1 , to improve the accuracy of the first encoded data ecc 1  transmitted to the memory die, thereby further ensuring the accuracy of the error checking and correction on the first data data 1 . 
     In some embodiments, the base die  100  may further have data serialization processing and serialization processing functions, which helps reduce the number of transmission channels between the processor and the base die  100  and reduce the number of transmission channels between the memory die and the base die  100 , thereby reducing the number of data transmission ports required by the processor, the base die  100 , and the memory die, and saving die areas of the processor, the base die  100 , and the memory die. 
     Another embodiment of the present disclosure further provides a memory system, where the memory system includes a processor, a memory die, and the base die provided in the foregoing embodiment. The memory system provided by another embodiment of the present disclosure is described in detail below with reference to the drawings. It should be noted that, for the parts the same as or corresponding to those mentioned in the foregoing embodiment, reference may be made to the foregoing embodiment, and details will not be described herein again. 
       FIG.  7    is a first schematic structural diagram of a memory system according to an embodiment of the present disclosure. 
     Referring to  FIG.  7   , the memory system includes: a base die  200 , a processor  300 , and a memory die  400 . The processor  300  is configured to: perform a first ECC encoding processing on first data data 1  in a writing phase to generate first encoded data ecc 1 , and transmit the first data data 1  and the first encoded data ecc 1  to the base die  200 . The base die  200  is configured to: receive the first data data 1  and the first encoded data ecc 1  in the writing phase, perform a second ECC encoding processing to generate a second encoded data ecc2, transmit a second data data 2  to the memory die  400  in the writing phase, where the second data data 2  includes the first data data 1 , the first encoded data ecc 1 , and the second encoded data ecc2, receive the second data data 2  from the memory die  400  in a reading phase, perform a first error checking and correction processing, and transmit a third data data 3  to the processor  300  in the reading phase, where the third data data 3  is the first data data 1  on which the first error checking and correction processing has been performed and the first encoded data ecc 1  on which the first error checking and correction processing has been performed. The memory die  400  is configured to receive the second data data 2  from the base die  200  in the writing phase, store the second data data 2 , and transmit the second data data 2  to the base die  200  in the reading phase. The processor  300  is further configured to receive the third data data 3  from the memory die  200  in the reading phase, perform a second error checking and correction processing on the third data data 3 , and transmit the first data data 1  on which the second error checking and correction processing has been performed. 
     In the foregoing memory system, both the ECC encoding processing and the error checking and correction processing on the data can be implemented by the base die  200 . Therefore, the memory die  400  does not need to perform the encoding processing and the error checking and correction processing, and the base die  200  can participate in the encoding processing and error checking and correction processing required by the processor  300 , so that functions required by the processor  300  and the memory die  400  are reduced, which can make the die areas of the processor  300  and the memory die  400  less tight, thereby better improving the performance of the processor  300  and the memory die  400 . For example, the reliability of the memory die  400  can be improved, thus enhancing the storage performance of the memory system. Moreover, both the base die  200  and the processor  300  can perform the error checking and correction processing on the first data, which helps improve the data error checking and correction capability of the memory system. 
     In some embodiments, the memory system may be a DRAM memory system, for example, a double data rate (DDR)  4  DRAM memory system, or a DDR 5  DRAM memory system. In other embodiments, the memory system may alternatively be a static random-access memory (SRAM) memory system, a NAND memory system, a NOR memory system, a FeRAM memory system, or a PcRAM memory system. 
     The processor  300  may include: a first encoding module  301 , configured to perform the first ECC encoding processing on the first data data 1  in the writing phase, to generate the first encoded data ecc 1 ; and a second error checking and correction module  302 , configured to receive the third data data 3  in the reading phase, and perform the second error checking and correction processing. 
     The base die  200  can provide a high-speed interface for data transmission in the memory system. In addition, the base die  200  is further configured to manage and control the memory die  400 . In some embodiments, the base die  200  may be configured to perform temperature monitoring and temperature management on the memory die  400 , and may further be configured to perform a Memory Build-In-Self Test (MBIST) on the memory die  400  and self-repair. In addition, the base die  200  is further configured to perform error checking and correction on transmitted data. 
       FIG.  8    is a second schematic structural diagram of a memory system according to an embodiment of the present disclosure. Referring to  FIG.  8   , in some embodiments, the base die  200  may include: a second encoding module  210 , configured to receive the first data data 1  and the first encoded data ecc 1  in the writing phase, and perform the second ECC encoding processing to generate the second encoded data ecc 2 ; and a first error checking and correction module  220 , configured to receive the second data data 2  in the reading phase, and perform the first error checking and correction processing. 
     For the working principle of the memory system, reference may be made to the corresponding description of foregoing embodiment, and details are not described herein again. It may be understood that, the processor  300  can perform the second error checking and correction processing on the first data data 1  on which the first error checking and correction processing has been performed. 
     In some embodiments, the first ECC encoding processing and the second error checking and correction processing are implemented by a first compiling algorithm; the second ECC encoding processing and the first error checking and correction processing are implemented by a second compiling algorithm, and the first compiling algorithm is different from the second compiling algorithm. The error checking and correction performed on data with different compiling algorithms helps further improve the accuracy of data error checking and correction. 
     Specifically, the second encoding module  210  and the first encoding module  301  may adopt different encoding algorithms; the first error checking and correction module  220  and the second error checking and correction module  302  may adopt different decoding algorithms. 
     It should be noted that, in other embodiments, the first compiling algorithm may be different from the second compiling algorithm. 
     Referring to  FIG.  8   , the memory die  400  includes: a first memory module  410 , configured to store the first data data 1  and the first encoded data ecc 1 ; and a second memory module  420 , configured to store the second encoded data ecc 2 . For example, the first memory module  410  may store 272 bits of data, and the second memory module  420  may store 32 bits of data. 
       FIG.  9    is a third schematic structural diagram of a memory system according to an embodiment of the present disclosure. Referring to  FIG.  9   , in some embodiments, the base die  200  may further include: a first deserializer module  230 , configured to receive the first data data 1  and the first encoded data ecc 1  in the writing phase, perform a first deserialization processing on the first data data 1  and the first encoded data ecc 1 , and transmit the first data data 1  on which the first deserialization processing has been performed and the first encoded data ecc 1  on which the first deserialization processing has been performed to the second encoding module  210 ; and a first serializer module  240 , configured to receive the third data data 3  in the reading phase, perform a first serialization processing on the third data data 3 , and transmit the third data data 3  on which the first serialization processing has been performed to the processor  300 . 
     Specifically, the first deserializer module  230  is connected between the data transmission port of the processor  300  and a data transmission port of the encoding module  210 . In this way, the number of transmission channels between the processor  300  and the base die  200  can be less than the number of bits of the first data data 1  and the first encoded data ecc 1 , thereby reducing the number of transmission channels between the processor  300  and the base die  200 . This can reduce the number of data transmission ports required by the base die  200  and the processor  300  and helps reduce the complexity of the electrical connection structure between the processor  300  and the base die  200 , thereby saving the die areas of the processor  300  and the base die  200 . 
     Referring to  FIG.  9   , the base die  200  may further include: a second serializer module  250 , configured to receive the second data data 2  from the second encoding module  210  in the writing phase, perform a second serialization processing, and transmit the second data data 2  on which the second serialization processing has been performed to the memory die  400 ; and a second deserializer module  260 , configured to receive the second data data 2  from the memory die  400  in the reading phase, perform a second deserialization processing, and transmit the second data data 2  on which the second deserialization processing has been performed to the first error checking and correction module  220 . 
     In this way, the number of transmission channels between the memory die  400  and the base die  200  can be less than the total number of bits of the first data data 1 , the first encoded data ecc 1 , and the second encoded data ecc2, thereby reducing the number of transmission channels between the memory die  400  and the base die  200 . This helps reduce the number of data transmission ports required by the base die  200  and the memory die  400  and helps reduce the complexity of the electrical connection structure between the memory die  400  and the base die  200 , thereby saving the die areas of the memory die  400  and the base die  200 . 
     It may be understood that, there are M data transmission channels between the processor  300  and the base die  200 , and there are N data transmission channels between the base die  200  and the memory die  400 , where M and N are both positive integers greater than 1, and N is greater than M. This is because that, not only the first data data 1  and the first encoded data ecc 1  but also the second encoded data ecc 2  needs to be transmitted between the base die  200  and the memory die  400 . 
     Referring to  FIG.  10   ,  FIG.  10    is a schematic structural diagram based on  FIG.  8   . In some embodiments, the base die  200  may be further configured to generate a first error checking marker signal during the first error checking and correction processing, and record, based on the first error checking marker signal, an error of the first data data 1 , an error of the first encoded data ecc 1 , and an error of the second encoded data ecc 2  during transmission. The memory system further includes: a first register  501 , configured to store the error of the first data data 1 , the error of the first encoded data ecc 1 , and the error of the second encoded data ecc 2  during transmission. 
     Specifically, referring to  FIG.  10   , the base die  200  may include: a first memory cache module  201 , configured to store the error of the first data data 1 , the error of the first encoded data ecc 1 , and the error of the second encoded data ecc 2  during transmission; and a first command module  202 , configured to receive a first polling instruction PS 1 , and generate a first command signal CMD 1  and a first clock signal CLK 1 . The first memory cache module  201  is further configured to output a first representation signal flag 1  to the first register  500  based on the first command signal CMD 1  and the first clock signal CLK 1 , where the first representation signal flag 1  represents the error of the first data data 1 , the error of the first encoded data ecc 1 , or the error of the second encoded data ecc 2  during transmission. 
     In some embodiments, the processor  300  may further be configured to send the first polling instruction PS 1  to the first command module  202 , that is, the processor  300  performs polling regularly, to control the first memory cache module  201  to output the first representation signal flag 1  to the first register  501 . It may be understood that, in other embodiments, the first polling instruction may alternatively be provided by an external circuit. 
     Referring to  FIG.  10   , in some embodiments, the processor  300  may be further configured to generate a second error checking marker signal during the second error checking and correction processing, and record, based on the second error checking marker signal, an error of the first data data 1  on which the first error checking and correction processing has been performed and an error of the first encoded data ecc 1  on which the first error checking and correction processing has been performed during transmission. The memory system may further include: a second register  502 , configured to store the error of the first data data 1  on which the first error checking and correction processing has been performed and the error of the first encoded data ecc 1  on which the first error checking and correction processing has been performed during transmission. 
     Referring to  FIG.  10   , in some embodiments, the processor  300  may further include: a second memory cache module  271 , configured to store the error of the first data data 1  on which the first error checking and correction processing has been performed and the error of the first encoded data ecc 1  on which the first error checking and correction processing has been performed during transmission; and a second command module  281 , configured to receive a second polling instruction PS 2 , and generate a second command signal CMD 2  and a second clock signal CLK 2 . The second memory cache module  271  is further configured to output a second representation signal flag 2  to the second register  502  based on the second command signal CMD 2  and the second clock signal CLK 2 , where the second representation signal flag 2  represents the error of the first data data 1  on which the first error checking and correction processing has been performed or the error of the first encoded data on which the first error checking and correction processing has been performed during transmission. 
     It may be understood that, the first register  501  and the second register  502  may be the same register. 
     In the memory system provided by the foregoing embodiment, the base die  200  can implement the error checking and correction function. Accordingly, the memory die  400  does not need to have the error checking and correction function, and the base die  200  can assist in the error checking and correction function originally taken by the processor  300 . Therefore, this helps save the space and areas of the processor  300  and the memory die  400 , thereby improving the storage performance of the memory die  400  and enhancing the storage performance of the memory system. Meanwhile, both the base die  200  and the processor  300  can perform error checking and correction processing on the first data. Therefore, the memory system has high data error checking and correction accuracy, and the RAS performance (i.e., reliability, availability, and serviceability) of the memory system is improved. 
     In some embodiments, the first error checking and correction module  220  and second error checking and correction module  302  can detect and correct errors on different data transmission paths, which improves the error checking and correction capability of the memory system and helps locate a specific data transmission path where an error occurs. 
     Accordingly, an embodiment of the present disclosure further provides a semiconductor structure. The semiconductor structure may include the memory system provided by the foregoing embodiment. The semiconductor structure provided by the embodiment of the present disclosure is described in detail below with reference to the drawings. It should be noted that, for the parts the same as or corresponding to those mentioned in the foregoing embodiment, reference may be made to the foregoing embodiment, and details will not be described herein again. 
       FIG.  11    is a cross-sectional schematic structural diagram of a semiconductor structure according to an embodiment of the present disclosure. 
     Referring to  FIG.  11   , the semiconductor structure includes: a carrier substrate  600 ; the memory system provided by the foregoing embodiment, where the processor  300  and the base die  200  are both located on a surface of the carrier substrate  600 , and the memory die  400  is located on a surface of the base die  200  that is away from the carrier substrate  600 . 
     The semiconductor structure may include a plurality of memory dies  400  stacked in sequence. The semiconductor structure may be a DRAM device, a SRAM device, or other memory. 
     In some embodiments, the carrier substrate  600  may be a printed circuit board (PCB). For the detailed description of the memory system, reference may be made to the foregoing embodiment, and details are not described herein again. 
     The semiconductor structure may be a 2.5-dimensional (2.5D) device. That is, the semiconductor structure is a stack structure, which helps reduce the size in a horizontal direction. In addition, the base die  200  in the semiconductor structure is used to implement the ECC error checking and correction function, thereby improving the performance of the semiconductor structure. 
     Those skilled in the art can understand that the above implementations are specific embodiments for implementing the present disclosure. In practical applications, various changes may be made to the above embodiments in terms of form and details without departing from the spirit and scope of the present disclosure. Any person skilled in the art may make changes and modifications to the embodiments without departing from the spirit and scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the scope defined by the claims.