Patent Publication Number: US-11031283-B2

Title: Trench isolation interfaces

Description:
PRIORITY INFORMATION 
     This application is a Continuation of U.S. application Ser. No. 16/396,288, filed Apr. 26, 2019, which is a Divisional of U.S. application Ser. No. 15/641,478, filed Jul. 5, 2017, and issued as U.S. Pat. No. 10,297,493 on May 21, 2019, the contents of which are included herein by reference. 
    
    
     TECHNICAL FIELD 
     The present disclosure relates generally to semiconductor devices and, more particularly, to trench isolation interfaces for use in memory, image, logic, and other semiconductor devices. 
     BACKGROUND 
     Implementing electronic circuits involves connecting separate devices or circuit components through specific electronic paths. In silicon integrated circuit (IC) fabrication, devices that are formed on or in a single substrate may be isolated from one another. The individual devices or circuit components may be subsequently interconnected to create a specific circuit configuration. As density of the devices continues to rise, and feature size shrinks below 50 nanometers (nm), parasitic inter-device capacitive coupling and fringing field induced leakage currents may become more problematic. Isolation technology, therefore, has become an important aspect of integrated circuit fabrication. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIGS. 1A and 1B  are cross-sectional views of a portion of embodiments of a trench isolation interface in accordance with a number of embodiments of the present disclosure. 
         FIGS. 2A and 2B  are cross-sectional views of a portion of embodiments of another trench isolation interface in accordance with a number of embodiments of the present disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     Dynamic random access memory (DRAM) devices, for example, may include an array of memory cells for storing data and peripheral circuits for controlling data in the memory cells. Each memory cell in DRAM may store one bit of data and may consist of one transistor and one capacitor. Within the array, each memory cell may be electrically isolated from adjacent memory cells. The degree to which large numbers of memory cells can be integrated into a single IC chip may depend, among other things, on the degree of isolation between the memory cells. Similarly, in metal-oxide-semiconductor (MOS) technology, isolation may be provided between adjacent devices, such as negative channel MOS (NMOS) transistors or positive channel MOS (PMOS) transistors and/or complementary MOS (CMOS) circuits, to prevent parasitic channel formation. An NMOS transistor and a PMOS transistor may be field effect transistors (FET) that in combination form a portion of a MOSFET CMOS. 
     Shallow trench isolation (STI) is one technique that may be used to isolate memory devices, such as memory cells and/or transistors, from one another. For instance, STI formation may include formation of (e.g., etching) a trench into a substrate, such as a crystalline silicon substrate, for a semiconductor device (e.g., a semiconductor substrate). An oxide, for instance, a high density plasma oxide, may be deposited to fill the trench and may be heated to densify the deposited oxide. 
     However, as the density of the device rises and the length and/or width of an active region (e.g., between an NMOS transistor and a PMOS transistor in a CMOS-type circuit) decreases, an STI structure formed as just described may be insufficient to adequately reduce a parasitic effect, among other possible effects, that may adversely affect performance of the CMOS-type circuit and/or contribute to operational problems for the associated memory device. Certain key FET device parameters, such as the current-voltage characteristics and device transconductance, could be adversely affected, thereby degrading device specifications and associated functionality of memory arrays or logic circuits. Accordingly, improvement of trench isolation techniques may be desirable to address these and similar problems. 
     The present disclosure includes specific semiconductor structures and methods for trench isolation interfaces. An example of a semiconductor structure includes a semiconductor substrate having an STI structure with a trench formed therein. An additional material layer in the trench forms a charged interface whereby parasitic fringing fields are reduced (e.g., prevented or terminated) due to uni-potential (metal-like) characteristics of the material. Another additional reactive dielectric material is deposited along the trench walls such that, by interaction with the semiconductor substrate of the STI structure, a high concentration of fixed negative charge is introduced. As a result, the parasitic threshold of the STI structure is sufficiently raised to reduce (e.g., eliminate) a possibility of a leakage path through the STI isolation. 
     In the following detailed description of the present disclosure, reference is made to the accompanying drawings that form a part hereof, and in which is shown by way of illustration how a number of embodiments of the disclosure may be practiced. These embodiments are described in sufficient detail to enable those of ordinary skill in the art to practice the embodiments of this disclosure, and it is to be understood that other embodiments may be utilized and that process, electrical, and/or structural changes may be made without departing from the scope of the present disclosure. 
     It is to be understood that the terminology used herein is for the purpose of describing particular embodiments only, and is not intended to be limiting. As used herein, the singular forms “a”, “an”, and “the” can include both singular and plural referents, unless the context clearly dictates otherwise. In addition, “a number of”, “at least one”, and “one or more”, e.g., a number of memory arrays, can refer to one or more memory arrays, whereas a “plurality of” is intended to refer to more than one of such things. Furthermore, the words “can” and “may” are used throughout this application in a permissive sense, i.e., having the potential to, being able to, not in a mandatory sense, i.e., must. The term “include,” and derivations thereof, means “including, but not limited to”. The terms “coupled” and “coupling” mean to be directly or indirectly connected physically or for access to and movement (transmission) of commands and/or data, as appropriate to the context. The terms “data” and “data values” are used interchangeably herein and can have the same meaning, as appropriate to the context. 
     “Substrate” as used herein is intended to mean a semiconductor substrate such as a base semiconductor layer or a semiconductor substrate having one or more layers, structures, or regions formed thereon. As such, a base semiconductor layer may be the lowest layer of silicon single crystal or silicon polycrystalline (polysilicon) material consisting of a silicon wafer or a silicon layer deposited on another material, such as silicon on sapphire. “Polysilicon” as used herein is intended to mean, in a number of embodiments, polysilicon that is doped (e.g., heavily doped n+ or p+ polysilicon), as appropriate to the context. For example, a polysilicon gate, as shown at  111  and described in connection with  FIGS. 1A and 1B  (e.g., a control gate, an access gate, etc.), may be formed from heavily doped polysilicon. “Layer” as used herein can refer to a layer formed on a substrate and/or a layer formed on a previously deposited layer using a number of deposition, processing, and thermal techniques, for example, as presented herein. The term “layer” is meant to include layers specific to the semiconductor industry, such as “barrier layer,” “dielectric layer,” and “conductive layer”, among other types of layers. The term “layer” is intended to be synonymous with the term “film”, as used in the semiconductor industry. The term “layer” may also include layers found in technology outside of semiconductor technology, such as coatings on glass. 
     The figures herein follow a numbering convention in which the first digit or digits correspond to the figure number and the remaining digits identify an element or component in the drawing. Similar elements or components between different figures may be identified by the use of similar digits. For example,  104  may reference element “ 04 ” in  FIG. 1 , and a similar element may be referenced as  204  in  FIG. 2 . Elements shown in the various embodiments herein can be added, exchanged, and/or eliminated so as to provide a number of additional embodiments of the present disclosure. In addition, the proportion and the relative scale of the elements provided in the figures are intended to illustrate certain embodiments of the present invention, and should not be taken in a limiting sense. 
       FIGS. 1A and 1B  are cross-sectional views of a portion of embodiments of a trench isolation interface structure  100  in accordance with a number of embodiments of the present disclosure. The figures shown herein each illustrate only one memory device (e.g., memory cell) cross-section in an X-Z plane with a trench isolation structure (e.g., STI structures  104  or  204 ) across the X direction only. However, the semiconductor structures contemplated herein can have STI structures for a plurality of memory cells in both directions of the X-Z plane and a Y-Z plane. 
     In  FIGS. 1A and 1B , the right and left edges of STI structure  104  are illustrated with an active non-volatile memory (NVM) cell, for example, cross-section in the middle between the right and left STI structure regions in a silicon substrate  109 . After defining a trench  106  in the silicon substrate  109 , a layer of aluminum oxide  107  (otherwise referred to as alumina or Al 2 O 3 ) may be formed, e.g., deposited, in the trench  106  over the polysilicon of the STI structure  104 . This may be followed by an appropriate anneal to create fixed negative charge at the interface  108  of the polysilicon and Al 2 O 3  due to interaction, e.g., a chemical reaction, between the polysilicon and the Al 2 O 3  resulting in formation of an aluminosilicate (AlSiO x ) at the interface  108 . In a number of embodiments, a layer of silicon oxide (SiO 2 ) (not shown) may be deposited in the trench  106  over the polysilicon of the STI structure  104  prior to depositing the Al 2 O 3  layer  107  thereon. Interaction between the SiO 2  and the Al 2 O 3  dielectric materials also may result in formation of an AlSiO x  at their interface. 
     Region  118  in  FIG. 1A  illustrates an extension of the silicon substrate  109  to a surface whereon an NVM stack structure may be fabricated thereafter. In  FIGS. 1A and 1B , an Al 2 O 3  collar (not shown) may be formed over the polysilicon of the STI structure  104  to extend beyond a polysilicon gate  111  (e.g., a control gate) of the active device. In the various STI structures described herein, a side-wall (not shown) of the polysilicon control gate  111  may merge with the STI structure  104  of the trench  106 . 
     As shown in the embodiment of  FIG. 1A , the polysilicon control gate  111  interfaces a high dielectric constant (k) dielectric blocking layer  113  of a silicon memory device  102  structure, which is extended on the top surface over the composite  104 / 107  isolation region (e.g., a combination of the polysilicon of the STI structure  104  and the Al 2 O 3  layer  107 ) of the STI structure  104 . Alternatively, in the embodiment shown in  FIG. 1B , the blocking layer  113  of the silicon memory device  120  structure may be formed under the polysilicon control gate  111  and between opposite walls  119  of the trench  106  bordering the composite  104 / 107  isolation region of the STI structure  104 . 
     Memory device  102 ,  120  stacked elements for an NVM device between the polysilicon control gate  111  and the silicon substrate  109 ,  118  may consist of three functional layers. As shown in  FIG. 1A , the stacked elements include a tunnel layer  117 , a trapping/charge storage layer  115 , and the charge blocking layer  113 . The corresponding tunnel layer is 117 and the corresponding trapping/storage layer is 123 in the memory cell of embodiment of  FIG. 1B . 
     For clarity, the figures shown herein illustrate active areas within the context of surrounding STI isolation regions associated with various embodiments of an NVM cell formed on and/or within the semiconductor substrate  109 . However, in a number of embodiments, the isolation schema described herein would be applicable to CMOS scaled NFET devices as well as n-channel NVM devices. This includes devices on any p-type substrate and/or devices fabricated over a number of p wells created on any n-type of substrate. The above isolation scheme also applies to n-channel FET technology built on other semiconductor substrates, including, but not limited to, Ge, SiGe, GaAs, InAs, InP, CdS, CdTe, other III/V compounds, and the like. 
     For CMOS scaled PFET devices and p-channel NVM devices, less stringent isolation techniques might be utilized. However, such devices may be fabricated either over an N-silicon substrate or within an N-well. In such devices, if implemented, a layer over the polysilicon of the STI structure  104  and/or an STI trench oxide (e.g., SiO 2 , among other possible oxides), may be a thin insulator (e.g., dielectric) layer that interacts with the polysilicon of the STI structure  104  and/or the trench oxide to form an excess of fixed positive charge at the interface with the polysilicon of the STI structure  104  to form an insulator. Such an insulator may be selected from various metal-silicon borides, for example. 
     Memory devices (e.g., as shown at  102  in  FIG. 1A, 120  in  FIG. 1B, 232  in  FIG. 2A, and 250  in  FIG. 2B ) may be organized in rows and columns in the form of memory array whereby a plurality (e.g., all) of memory devices may be isolated from each other by means of an STI structure (e.g., as shown at  104  in  FIGS. 1A and 1B  and at  204  in  FIGS. 2A and 2B ) having a respective trench isolation interface structure  100 ,  230 . A particular type of STI schema compatible to a particular memory device type may be implemented to provide isolation for a plurality (e.g., all) of memory devices of the same type within a memory array. For example, in a number of embodiments, there may be one STI isolation schema, as shown and described in connection with  FIGS. 1A and 1B , for the composite  104 / 107  isolation region for memory devices  102  and  120 , respectively. Another STI isolation schema, as shown and described in connection with  FIGS. 2A and 2B , may be used for memory devices  232  and  250 , respectively, such as the composite  204 / 207 / 240  isolation region (e.g., including interface  208  shown for  204 / 207  and interface  239  shown for  207 / 240 ). 
     The isolation schema described herein also may be applicable to FET device types that utilize polysilicon as a gate material. Gates of FET devices or FET-based memory devices may either be heavily doped polysilicon gates (e.g., per gate  111  embodiments for memory devices  102  and  120  shown in  FIGS. 1A and 1B ) or metal gates (e.g., per gate  234  embodiments for memory devices  232  and  250  shown in  FIGS. 2A and 2B ). In the embodiments shown at  102  and  232 , the respective control gates  111  and  234  (e.g., of a FET device or an NVM device) may be configured to overlap the STI structure  104 / 204  on each edge of the STI structure while remaining above an upper plane of the STI structure (e.g., not extending into and between the opposite walls  119 ,  219  of the trench  106 ,  206  bordering the isolation region of STI structures  104 / 204  formed from composites  104 / 107  and/or  204 / 207 / 240 ). In the embodiments shown at  120  and  250 , the respective control gates  111  and  234  (e.g., of the FET device or the NVM device) may be configured to be partially contained inside and below the upper plane of the STI structure (e.g., extending into and between the opposite walls  119 ,  219  of the trench  106 ,  206  bordering the isolation region of STI structures  104 / 204  formed from composites  104 / 107  and/or  204 / 207 / 240 ). 
     The parasitic edge fringing fields may be different depending upon whether the gates  111  and  234  are completely above the plane of the STI structure  104 / 204  (e.g., as shown for memory devices  102  and  232  in  FIGS. 1A and 2A , respectively) in comparison to memory devices  120  and  250  having the gate at least partially below the top plane of the STI structure within the silicon substrate thereof (e.g., as shown in  FIGS. 1B and 2B , respectively). In these embodiments, the fixed negative charge at the interface  108  of  FIGS. 1A and 1B  and the fixed negative charge at the interface  208  of  FIGS. 2A and 2B  is implemented to raise the parasitic threshold of the gate-overlapped STI regions and/or reduce the device leakage characteristics described herein. In the embodiments shown in  FIGS. 2A and 2B , an additional “injector silicon-rich nitride” (IN-SRN) layer  240  is shown to be deposited over at least a portion of the aluminum oxide layer (Al 2 O 3 )  207  in the trench  206 . The IN-SRN layer  240  is formed to contain silicon nanoparticles that are placed within direct tunneling distance from each other, thereby contributing to formation of a uni-potential dielectric material for the charged interface  208 . The uni-potential dielectric material may reduce (e.g., prevent or terminate) parasitic fringing fields (e.g., due to edge geometry effects of the memory device design, among other possible causes). The modified STI structures  204  containing the composite  204 / 207 / 240  isolation region may reduce (e.g., prevent or terminate) the fringing field effects and/or the device leakage to enhance memory device characteristics (e.g., performance of FET devices and/or NVM devices). 
     The figures shown herein each illustrate only one trench isolation structure (e.g., STI structure  104  or  204 ), however, the semiconductor structures contemplated herein can have any number of STI structures. For example, in a number of embodiments, there may be one STI structure per memory device (e.g., STI structure  104  for memory devices  102  and/or  120  shown and described in connection with  FIGS. 1A and 1B , respectively). 
     In a number of embodiments, the memory devices  102  and/or  120  shown and described in connection with  FIGS. 1A and 1B  and/or memory devices  232  and/or  250  shown and described in connection with  FIGS. 2A and 2B  may be, or may include at least one, FET-type transistor, as described herein (e.g., a number of NMOS transistors and/or PMOS transistors in a CMOS-type circuit). The memory devices  102 ,  120 ,  232  and/or  250  may be, or may include at least one, charge-trapping flash (CTF) memory device. In a number of embodiments, the memory devices  102 ,  120 ,  232  and/or  250  may be, or may include at least one, NAND and/or NOR non-volatile memory (NVM) device. Alternatively or in addition, the memory devices  102 ,  120 ,  232  and/or  250  may be, or may include at least one, nitride read-only memory (NROM) NVM device. Moreover, the memory devices  102 ,  120 ,  232  and/or  250  may be, or may include at least one, silicon-based unified memory (SUM) configured, in a number of embodiments, as volatile memory (VM) and/or NVM. 
     Each memory device  102 ,  120 ,  232  and/or  250  may be positioned interior to the STI structure  104  and/or  204  (e.g., as shown by double-headed arrows  119  in  FIGS. 1A and 1B and 219  in  FIGS. 2A and 2B ). For example, each memory device may have at least a portion thereof (e.g., an active region involved in storage of and/or a compute operations performed on a data value) positioned interior to the STI structure (e.g., in a channel). As shown in  FIGS. 1A and 1B , the memory devices  102  and/or  120  may be further positioned adjacent (e.g., contiguous) to the trench  106 . Alternatively or in addition, an IN-SRN layer (e.g., as shown at  240  and described in connection with  FIGS. 2A and 2B ) may be formed on a surface of the trench  106  opposite from the interface  208  with the semiconductor substrate  209  and/or the STI structure  204 . The memory devices  232  and/or  250  may be positioned adjacent (e.g., contiguous) to the IN-SRN layer  240 . 
     Suitable techniques for forming and/or removing portions of the STI structure  104  (e.g., including the trenches thereof) on or from the semiconductor substrate  109  and/or the layers formed thereon may include etching techniques such as, but not limited to, reactive ion etching (ME), plasma etching, chemical dry etching, and/or ion beam etching, among other possible etching techniques. 
     The etch process may be allowed to continue to at least remove a portion of the STI structure  104  and/or the semiconductor substrate  109  in forming a trench  106 . The depth that etching is performed into the STI structure  104  and/or the semiconductor substrate  109  to form the trench  106  may range from around 100 nanometers (nm) to around 800 nm. However, other depths may be implemented depending upon, for example, a desired aspect ratio (depth to width) of the opening into the STI structure  104  and/or the semiconductor substrate  109 . Portions of the STI structure (e.g., a bottom portion of trench  106  adjacent the semiconductor substrate  109  in  FIG. 1B  and/or a bottom portion of trench  206  adjacent the semiconductor substrate  209  in  FIG. 2B ) may be etched prior to etching other portions of the STI structure  104  and/or the layers (e.g., to form the upper portions of trench  106  and/or trench  206 . 
     The layers described herein in connection with  FIGS. 1A and 1B  and  FIGS. 2A and 2B  including, for example, an oxide (e.g., SiO 2 ) formed on the semiconductor substrate  109  used to form the STI structure  104  and the material  107  (e.g., Al 2 O 3 ) and/or the IN-SRN layer  240  used to fill trench  106 , may be deposited prior to and/or after forming (e.g., etching) a complete STI structure (e.g., including the trenches thereof). For example, some portions of the STI structure  104 ,  204  and/or the layers described herein positioned between portions of the STI structure (e.g., the portions of STI structure  104  associated with trench  106 ) may be deposited on the semiconductor substrate  109 ,  209  prior to etching the STI structure and/or the layers to form the trenches and/or the channel interior to (e.g., between) the portions of the STI structure  104 ,  204  (e.g., as shown by double-headed arrows  119  in  FIGS. 1A and 1B and 219  in  FIGS. 2A and 2B ). In a number of embodiments, the STI structure  104 ,  204  may be formed from the same material as the semiconductor substrate  109 ,  209  (e.g., polysilicon). 
     In a number of embodiments, some portions and/or layers of the memory devices  102 ,  120 ,  232  and/or  250  may be formed (e.g., deposited) interior to (e.g., between) the portions of the STI structure  104 ,  204  (e.g., in the channel). For example, a tunnel layer (e.g., as shown at  117  in  FIGS. 1A and 1B  and at  217  in  FIGS. 2A and 2B ) may be formed interior to the portions of the STI structure  104 ,  204 . 
     In a number of embodiments, some portions and/or layers of the memory devices  102 ,  120 ,  232  and/or  250  may be formed (e.g., deposited) exterior to the STI structure. For example, a gate (e.g., a control gate, an access gate, etc.) as shown at  111  in  FIGS. 1A and 1B  and at  234  in  FIGS. 2A and 2B  may be formed exterior to the portions of the STI structure  104 ,  204 . In a number of embodiments, the gate may be formed (e.g., deposited) as a layer after other layers of the memory device have been formed. Such a gate may be positioned on top of a channel of a corresponding memory device that is interior to the portions of the STI structure  104 ,  204 . Such a gate may have a length and/or width that extends beyond the channel interior to the STI structure  104 ,  204  (e.g., as shown by extending to the outer lines associated with the double-headed arrows  119  in  FIGS. 1A and 1B and 219  in  FIGS. 2A and 2B ). In a number of embodiments, the gate may extend above a horizontal portion of a trench (e.g., upper portion of trench  106  filled with material  107  shown in  FIGS. 1A and 1B ) for the length and/or width above the STI structure  104 ,  204 . 
     The layers described herein in connection with  FIGS. 1A and 1B  and  FIGS. 2A and 2B  (e.g., including the oxide and/or the material  107  and/or the IN-SRN layer  240  used to fill trench  106 ) may be deposited utilizing a number of deposition techniques. A particular deposition technique may be selected based upon, for example, suitability of the deposition technique in connection with a particular chemical composition of the layer to be deposited, a thickness, length, and/or width of the layer to be deposited, whether the layer is to be deposited on a horizontal, vertical, and/or slanted surface, and/or a chemical composition of an underlying layer upon which the layer is to be deposited, among other possible considerations. The particular deposition technique may be selected from a group of such techniques that includes, but is not limited to, chemical vapor deposition (CVD), low pressure CVD (LPCVD), plasma enhanced CVD (PECVD), plasma vapor deposition (PVD), and atomic layer deposition (ALD), among other possible deposition techniques. For a number of embodiments described herein, oxidation and/or nitridation techniques may be performed in association with (e.g., before, during, and/or after) the particular deposition technique. Appropriate annealing techniques also may be performed. 
       FIGS. 1A and 1B  each illustrate a cross-sectional view of a portion of an embodiment of a trench isolation interface structure  100  formed as a semiconductor structure. The semiconductor structure may, in a number of embodiments, include a polysilicon substrate (e.g., formed from the same material as polysilicon substrate  109 ) having an STI structure  104  with a trench  106  formed therein. In a number of embodiments, an oxide (not shown) formed on the surface of the STI structure  104  may be a SiO 2  dielectric layer (not shown). A material  107  used to fill the trench  106  may be an Al 2 O 3  dielectric layer that forms a trench isolation interface  108  in the trench  106  with a fixed negative charge. The trench isolation interface  108  may be formed by interaction of the Al 2 O 3  dielectric layer  107  with the SiO 2  dielectric layer on the STI structure  104  and/or with the polysilicon of the STI structure  104  itself. In a number of embodiments, the Al 2 O 3  dielectric layer  107  may be formed on a surface of the SiO 2  dielectric layer opposite from the STI structure  104 . 
     Alternatively, the Al 2 O 3  dielectric layer  107  may be formed between a surface of the STI structure  104  and the SiO 2  dielectric layer. In a number of embodiments, a memory device (e.g., memory device  102  in  FIG. 1A  and/or memory device  120  in  FIG. 1B ) may be included in the semiconductor structure. As described herein, the memory device  102 ,  120  may have a portion positioned interior to the STI structure  104  and adjacent the trench  106 . 
     The material  107  in the trench  106  may form a charged interface  108  by interaction with the polysilicon of the STI structure  104  (e.g., as shown in  FIG. 1A ) and/or by interaction with the polysilicon on an upper portion of the STI structure  104  and a lower portion adjacent the semiconductor substrate  109  itself (e.g., as shown in  FIG. 1B ). The material  107  in the trench may, in a number of embodiments, be the Al 2 O 3  dielectric. The semiconductor substrate of the STI structure  104  (and the semiconductor substrate  109 ) may be polysilicon formed outside the trench  106  relative to the memory device  102 ,  120  formed interior to the trench  106 . The charged interface  108  may be formed by an aluminosilicate (AlSiO x ) being formed at the interface  108  (e.g., via a chemical reaction at the interface  108  between the Al 2 O 3    107  in the trench  106  and the polysilicon of the STI structure  104 ). For example, the AlSiO x  may have a fixed negative charge with an electron density in a range of from around 1×10 11  to around 5×10 12  extra electrons (e.g., relative to a number of electrons that is substantially equal to a corresponding number of protons) per square centimeter at a uni-potential interface. 
     The charged interface  108  may, in a number of embodiments, raise the parasitic threshold of the STI structure  104  (e.g., a parasitic filed oxide threshold). For example, the raised parasitic threshold may increase an ability of the STI structure  104  to reduce (e.g., prevent or terminate) leakage of an electrical charge from the memory device  102 ,  120  (e.g., NAND, NOR, and/or NROM NVM devices, among other types of memory devices). The charged interface  108  may reduce (e.g., prevent or terminate) a rate of charge loss for the memory device. In a number of embodiments, the charged interface  108  may reduce (e.g., prevent or terminate) an edge fringing field intensity for the memory device. 
     As shown in  FIGS. 1A and 1B , the memory device  102 ,  120  may have a polysilicon gate  111  (e.g., a control gate, an access gate, etc.) formed above the STI structure  104 , which may, in a number of embodiments, be wider than opposite walls  119  of the trench  106 . The semiconductor structure may include an extension layer of a composite of the polysilicon of the STI structure  104  and the Al 2 O 3  dielectric layer  107  of the trench formed between the STI structure  104  and the polysilicon gate  111  that is formed wider than the opposite walls of the trench. 
     As shown in  FIG. 1A , the semiconductor structure may, in a number of embodiments, include a high dielectric constant (k) dielectric layer  113  formed between the polysilicon gate  111  and the Al 2 O 3  dielectric layer  107  of the extension layer. A middle portion of the high k dielectric layer  113  may extend into the channel between the walls  119  of the trench  106  a portion of a distance from the Al 2 O 3  dielectric material  107  of the extension layer to the semiconductor substrate  109 . The high k dielectric layer  113  may have a dielectric constant that is above 6.0. Examples of such high k dielectric materials that may be utilized (e.g., deposited) for formation of the high k dielectric layer include, but are not limited to, hafnium silicate ((HfO 2 ) x (SiO 2 ) 1-x ), hafnium dioxide (HfO 2 ), zirconium silicate ((ZrO 2 ) x (SiO 2 ) 1-x ), zirconium dioxide (ZrO 2 ), lanthanum oxide (La 2 O 3 ), and aluminum oxide (Al 2 O 3 ), among other high k dielectric materials. 
     As further shown in  FIG. 1A , the semiconductor structure may, in a number of embodiments, include a floating gate  115  of the memory device  102  that may be formed under the high k dielectric layer  113  (e.g., the middle portion thereof) and between opposite walls of the trench  106  formed from the Al 2 O 3  dielectric material  107 . The floating gate  115  may include a floating node within floating gate  115 , and the floating gate  115  may include and/or be surrounded by resistive material to isolate the floating node such that a charge contained in the floating node may remain unchanged over a period of time (e.g., by charge trapping for NVM). The floating gate  115  may be formed, for example, by a layer of aluminum oxide (Al 2 O 3 ) between two layers of silicon oxynitride (Si 2 ON 2 ), among other possible configurations for a floating gate. Direct tunneling (Fowler-Nordheim tunneling) and/or hot-carrier injection mechanisms may be utilized to modify an amount of charge stored in the floating gate  115 . 
     As further shown in  FIG. 1A , the semiconductor structure may, in a number of embodiments, include a tunnel layer  117  formed under the floating gate  115  and between the opposite walls of the trench  106  formed from the Al 2 O 3  dielectric  107 . The tunnel layer  117  may be formed, in a number of embodiments, from oxygen-rich silicon oxynitride (OR—SiON) (e.g., instead of or in addition to SiO 2 ). A polysilicon layer  118  may be formed as an extension of the polysilicon substrate  109  between the tunnel layer  117  and the polysilicon substrate  109 . 
     As shown in  FIG. 1B , the semiconductor structure may, in a number of embodiments, include a high k dielectric layer  113  formed under the polysilicon gate  111  and between opposite walls  119  of the trench  106  formed from the Al 2 O 3  dielectric material  107 . The polysilicon gate  111  may thus be positioned adjacent (e.g., contiguous) to the Al 2 O 3  dielectric material  107  of an upper portion of the trench  106 . A portion (e.g., a middle portion) of the polysilicon gate  111  may extend into the channel between the walls of the trench  106  a portion of a distance from an upper extension layer of the Al 2 O 3  dielectric material  107  to a lower extension layer of the Al 2 O 3  dielectric material  107  above the semiconductor substrate  109 . 
     The semiconductor structure shown in  FIG. 1B  may, in a number of embodiments, further include a floating plate  123  formed from IN-SRN (e.g., instead of or in addition to Si or SiO 2 ) to provide the functionality of the floating gate  115  shown and described in connection with  FIG. 1A . The floating plate  123  may be formed under the high k dielectric layer  113  and between opposite walls of the trench  106  formed from the Al 2 O 3  dielectric material  107 . A tunnel layer  117  may be formed under the floating plate  123  and between the opposite walls of the trench formed from the Al 2 O 3  dielectric. For example, the tunnel layer  117  may be formed between the floating plate  123  and the extension  118  of the polysilicon substrate  109 . 
     The semiconductor structure shown in  FIG. 1B , may, in a number of embodiments, include a solid nitride layer (not shown) formed under the high k dielectric layer  113  and between opposite walls of the trench  106  formed from the Al 2 O 3  dielectric material  107 . The solid nitride layer may be formed, in a number of embodiments, from a nitride ion (N 3− ) in combination with an element of similar or lower electronegativity. Examples of elements that may combine with N 3−  to form the solid nitride of the solid nitride layer include, but are not limited to, boron (B), Si, vanadium (V), titanium (Ti), and tantalum (Ta), among other elements. 
       FIGS. 2A and 2B  each illustrate a cross-sectional view of a portion of an embodiment of a trench isolation interface structure  230  formed as a semiconductor structure. The semiconductor structure may, in a number of embodiments, include a polysilicon substrate  209  having an STI structure  204  with a trench  206  formed therein. A material  207  used to fill the trench  206  may be an Al 2 O 3  dielectric layer  207  formed on a polysilicon surface of the STI structure  204 . A composite of the Al 2 O 3  dielectric layer  207  and the polysilicon of the STI structure  204  may form a trench isolation interface  208  in the trench  206  with a fixed negative charge by interaction in the trench  206  between the Al 2 O 3  dielectric layer  207  and the polysilicon of the STI structure  204 . The semiconductor structure may, in a number of embodiments, include an IN-SRN layer  240  formed on a surface of the trench  206  opposite from the STI structure  204  and adjacent the Al 2 O 3  dielectric layer  207  at interface  208 . In a number of embodiments, a SiO 2  dielectric layer (not shown) may be formed in the trench  206  on a surface of the STI structure  204  and the Al 2 O 3  dielectric layer  207  may be formed upon the SiO 2  dielectric layer. A composite of the SiO 2  dielectric layer and the Al 2 O 3  dielectric layer  207  may contribute to formation of the trench isolation interface  208  with the fixed negative charge. 
     In a number of embodiments, a memory device (e.g., memory device  232  in  FIG. 2A  and/or memory device  250  in  FIG. 2B ) may be included in the semiconductor structure. As described herein, the memory device  232 ,  250  may have a number of portions positioned interior to the STI structure  204  and adjacent the trench  206  and/or the IN-SRN layer  240 . The IN-SRN layer  240  may contribute to confinement in a charge reservoir of charges in the memory device. 
     As described in connection with  FIGS. 1A and 1B , the Al 2 O 3  dielectric layer  207  in the trench  206  in  FIGS. 2A and 2B  may contribute to formation of a charged interface  208  by interaction with the polysilicon of the STI structure  204  (e.g., as shown in  FIG. 2A ) and/or by interaction with the polysilicon of an upper portion of the STI structure  204  and a lower portion adjacent the semiconductor substrate  209  itself (e.g., as shown in  FIG. 2B ). The semiconductor substrate of the STI structure  204  (and the semiconductor substrate  209 ) may be polysilicon formed outside the trench  206  relative to the memory device  232 ,  250  formed interior to the trench  206 . As described in connection with  FIGS. 1A and 1B , a uni-potential interface in  FIGS. 2A and 2B  may be formed by AlSiO x  being formed at the interface  208  and the AlSiO x  may have a fixed negative charge with an electron density in a range of from around 1×10 11  to around 5×10 12  extra electrons per square centimeter. 
     A composite of the polysilicon of the STI structure  204 , the Al 2 O 3  dielectric layer  207 , and the IN-SRN layer  240  may, in a number of embodiments, form a completed interface (e.g., a composite isolation region including interfaces  208  and  239 ) that raises a parasitic threshold of the STI structure  204  (e.g., a parasitic filed oxide threshold). For example, the raised parasitic threshold may increase an ability of the STI structure  204  to reduce leakage of an electrical charge from the memory device  232 ,  250  (e.g., NAND, NOR, and/or NROM NVM devices, among other types of memory devices). The formed interface may reduce a rate of charge loss for the memory device. In a number of embodiments, the composite of the polysilicon of the STI structure  204 , the Al 2 O 3  dielectric layer  207 , and the IN-SRN layer  240  may reduce an edge fringing field intensity for the memory device. In a number of embodiments described herein, the IN-SRN layers  240  may be formed adjacent (e.g., contiguous) to the STI structure  204  and the trenches  106  containing the Al 2 O 3  dielectric material  207  may be formed on an outer surface thereof (e.g., adjacent the channel of the corresponding memory device). 
     The memory device  232 ,  250  may have an active region at least partially positioned interior to the STI structure  204  and adjacent the IN-SRN layer  240 . A channel for the memory device  232 ,  250  may be at least partially positioned interior to the IN-SRN layer  240 . The channel may have a width and/or a length  219  perpendicular to the IN-SRN layer  240  formed on a vertical surface of the trench  206 . The length and/or width  219  of the channel may, in a number of embodiments, be in a range of from around twenty (20) nm to around five (5) nm. 
     The composite of the polysilicon of the STI structure  204 , the Al 2 O 3  dielectric layer  207 , and the IN-SRN layer  240  may raise the parasitic threshold of the STI structure  204 , reduce leakage of an electrical charge from the memory device  232 ,  250 , and/or reduce an edge fringing field intensity for the memory device sufficient to improve operability of the memory devices having length and/or width  219  of the channel in the range of from around 20 nm to around 5 nm (e.g., relative to memory devices implemented in an STI configuration without the trench isolation interface structures  100 ,  230  described herein). 
     As shown in  FIGS. 2A and 2B , the memory device  232 ,  250  may have a gate  234  (e.g., a control gate, an access gate, etc.) formed above the STI structure  204 , which may, in a number of embodiments, be wider than opposite walls  219  of the trench  206  with the IN-SRN layer  240  formed thereon. The gate  234  may be formed from a metal (e.g., tungsten (W), aluminum (Al), among other possible metals). A metal may be utilized for the gate  234  (e.g., as opposed to the polysilicon described in connection with  FIGS. 1A and 1B ) in implementations of memory devices with relatively small length and/or width of the channel (e.g., in the range of from around 20 nm to around 5 nm) and/or memory devices in which a relatively high voltage threshold (Vt) and/or high k dielectric material is utilized (e.g., to contribute to reducing leakage of an electrical charge from the memory device  232 ,  250 ). 
     The metal gate  234  may, in a number of embodiments, be formed wider than opposite walls  219  of the trench  206 . An extension layer of the Al 2 O 3  dielectric layer  207  of the trench  206  and/or the IN-SRN layer  240  may be formed between the STI structure  204  and the metal gate  234  formed wider than the opposite walls of the trench. 
     In a number of embodiments, the semiconductor structure may include a tantalum nitride (TaN) layer  236  formed between the metal gate  234  and the opposite walls of the trench  206  having the IN-SRN layer  240  formed on the Al 2 O 3  dielectric material  207 . As shown in  FIG. 2A , the TaN layer  236  may be positioned adjacent (e.g., contiguous) to the metal gate  234  straight across a length and/or width of the metal gate  234 . As shown in  FIG. 2B , the TaN layer  236  may be positioned adjacent to the metal gate  234  such that a portion (e.g., a middle portion) of the TaN layer  236  and/or the metal gate  234  extend into the channel between the walls  219  of the trench  206  a portion of a distance from the extension layer of the Al 2 O 3  dielectric material  207  to the semiconductor substrate  209 . By extending partially into the channel, the TaN layer  236  may replace the IN-SRN layer  240  from being formed on the Al 2 O 3  dielectric material  207  in an upper portion of the channel. 
     The metal gate  234  and/or the TaN layer  236  may have a length and/or width that extends beyond the channel interior to the STI structure  204  (e.g., as shown by extending to the outer lines associated with the double-headed arrows  219  in  FIGS. 2A and 2B ). In a number of embodiments, the metal gate  234  may extend above a horizontal portion of a trench (e.g., upper portions of trench  206  filled with material  207  shown in  FIGS. 2A and 2B ) for the length and/or width above the STI structure  204 . 
     As shown in  FIG. 2A , the semiconductor structure may further include a high k dielectric layer  213 , as described herein, formed between the TaN layer  236  and the opposite walls of the trench  206  having the IN-SRN layer  240  formed thereon and across a channel for the memory device  232  between the opposite walls. Another IN-SRN layer  238  may, in a number of embodiments, be formed between the TaN layer  236  and the high k dielectric layer  213 . A floating gate  215  of the memory device  232  may be formed under the high k dielectric layer  213  (e.g., as shown at  113  and described in connection with  FIG. 1A ) and between opposite walls of the trench  216  having the IN-SRN layer  240  formed thereon and across a channel for the memory device  232  between the opposite walls. A tunnel layer  217  may be formed under the floating gate  215  and between the opposite walls of the trench having the IN-SRN layer  240  formed thereon. A polysilicon layer  218  may be formed between the tunnel layer  217  and the polysilicon substrate  209  (e.g., as an extension of the polysilicon substrate  209 ). 
     As shown in  FIG. 2B , the semiconductor structure may further include a high k dielectric layer  213  formed under the TaN layer  236  and between the opposite walls of, in a number of embodiments, the upper portion of the trench not having the IN-SRN layer  240  formed thereon and across a channel for the memory device  250  between the opposite walls. A floating plate  223  (e.g., as shown at  123  and described in connection with  FIG. 1B ) may be formed from IN-SRN. The floating plate  223  may be formed under the high k dielectric layer  213  and between opposite walls of the portion of the trench not having the IN-SRN layer  240  formed thereon. A tunnel layer  217  may be formed under the floating plate  223  and between the opposite walls of a lower portion of the trench  216  having the IN-SRN layer  240  formed thereon. The tunnel layer  217  may be formed between the floating plate  223  and the polysilicon substrate  209 . A polysilicon layer  218  may be formed between the tunnel layer  217  and the polysilicon substrate  209  (e.g., as an extension of the polysilicon substrate  209 ). 
     Embodiments described herein provide a method of forming a semiconductor structure including trench isolation interfaces. An example of such a method may include forming an STI structure  104 ,  204  in a polysilicon substrate material (e.g., the same material utilized to form the polysilicon substrate  109 ,  209 ). The method may include depositing a layer of Al 2 O 3  dielectric  107 ,  207  on vertical and/or horizontal surfaces of the Al 2 O 3  dielectric  107 ,  207  to form the trench  106 ,  206  between the STI structure  104 ,  204  and a memory device  102 ,  120 ,  232 ,  250 . The method may include forming a trench isolation interface  108 ,  208  in the trench  106 ,  206  with a fixed negative charge by interaction of the polysilicon substrate material with the Al 2 O 3  dielectric layer  107 ,  207 , thereby raising a parasitic threshold of the STI structure  104 ,  204  and/or reducing an edge fringing field intensity for the memory device  102 ,  120 ,  232 ,  250 . 
     The method may further include depositing a layer of IN-SRN  240  on the surface of the Al 2 O 3  dielectric layer  207  opposite from interface  208  at interface  239 . Alternatively and/or in addition, the method may further include depositing a layer of IN-SRN  240  on the surface of the STI structure  204  in the trench  206  prior to deposition of the Al 2 O 3  dielectric layer  207  thereon. The method may further include annealing the Al 2 O 3  dielectric layer  207  and/or the IN-SRN layer  240  after the deposition. 
     In a number of embodiments, annealing can be performed in an inert gas atmosphere (e.g., nitrogen, argon, helium and the like), which may or may not be mixed with oxygen. One example of an atmosphere employed in the annealing step of the present disclosure may include steam at a temperature about 600° Celsius (C) to about 700° C. for a time interval from about 30 to about 120 seconds. In another example, the atmosphere employed for the annealing step may be steam at a temperature from about 75° C. to about 600° C. for a time interval from about 30 to about 120 seconds. The annealing may be performed in a single ramp step or it can be performed using a series of ramp and soak cycles. 
     After annealing the Al 2 O 3  dielectric layer  207  and/or the IN-SRN layer  240 , the annealed semiconductor structure may then be subjected to suitable deposition and/or etch techniques that can be implemented to form the STI structure and memory device components described herein. The etching techniques may include, but are not limited to, dry etching techniques such as RIE, plasma etching, ion beam etching, and/or chemical dry etching, among others. Examples of suitable gases that can be employed in the dry etching process include but are not limited to, CF 4 , SF 6 , NF 3 , CHF 3  and combinations thereof. The gases may also be used in conjunction with oxygen or an inert gas such as nitrogen or helium. Alternatively, an oxide etch may be implemented using a wet chemical etch process. Suitable chemical etchants that may be utilized include HF and HNO 3 , among others. A buffered solution also may be utilized. 
     Additional processes can be performed using various techniques to complete an integrated circuit (IC) for use in an electronic system that includes a controller (e.g., a processor) and active semiconductor regions separated by the STI structure. Various types of devices can be formed. Such devices may include imaging devices, memory devices, and/or logic devices. For example, the completed IC can include an array of memory cells for an NVM or another type of memory device. In various ICs, logic devices for gate arrays, microprocessors, and/or digital signal processors may be formed. The STI structures described herein may separate the active regions from one another. 
     While example embodiments including various combinations and configurations of semiconductor structures for trench isolation interfaces have been illustrated and described herein, embodiments of the present disclosure are not limited to those combinations explicitly recited herein. Other combinations and configurations of the semiconductor structures for trench isolation interfaces disclosed herein are expressly included within the scope of this disclosure. 
     Although specific embodiments have been illustrated and described herein, those of ordinary skill in the art will appreciate that an arrangement calculated to achieve the same results can be substituted for the specific embodiments shown. This disclosure is intended to cover adaptations or variations of one or more embodiments of the present disclosure. It is to be understood that the above description has been made in an illustrative fashion, and not a restrictive one. Combination of the above embodiments, and other embodiments not specifically described herein will be apparent to those of skill in the art upon reviewing the above description. The scope of the one or more embodiments of the present disclosure includes other applications in which the above structures and methods are used. Therefore, the scope of one or more embodiments of the present disclosure should be determined with reference to the appended claims, along with the full range of equivalents to which such claims are entitled. 
     In the foregoing Detailed Description, some features are grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the disclosed embodiments of the present disclosure have to use more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed embodiment. Thus, the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate embodiment.