Patent Publication Number: US-10770161-B2

Title: Sense amplifier

Description:
This application is a Continuation Application of U.S. application Ser. No. 15/492,014, filed Apr. 20, 2017, now U.S. Pat. No. 10,181,358, which claims the benefit of U.S. provisional application Ser. No. 62/412,881, filed Oct. 26, 2016, the disclosure of which is incorporated by reference herein in its entirety. 
    
    
     TECHNICAL FIELD 
     The disclosure relates in general to a sense amplifier, and more particularly to a sense amplifier for reading a via Read-Only Memory (Via-ROM). 
     BACKGROUND 
     Along with the development of semiconductor technology, various memories are invented. Via Read-Only Memory (Via-ROM) records data by vias. Please refer to  FIG. 1 , which shows an example a Via-ROM  900 . The via-ROM  900  includes a plurality of word lines WL 9 , a plurality of bit lines BL 9  and a plurality of memory cells, such as code- 0  cells C 90  and code- 1  cells C 91 . The source of the code- 0  cell C 90  is connected to the ground, a via at the drain of the code- 0  cell C 90  is conducted, and the read voltage of the code- 0  cell C 90  is ground. The source of the code- 1  cell C 91  is connected to the ground, a via at the drain of the code- 1  cell C 91  is opened, and the read voltage of the code- 1  cell C 91  is high. 
     The read voltage of one selected code- 1  cell C 91  may be dropped due to the bit-line leakages happened on the other code- 0  cells C 90 . If a large number of code- 0  cells C 90  are formed on one bit line, the read voltage of the code- 1  cell C 91  on this bit line may be greatly dropped and cannot be accurately identified. 
     Especially, the bit-line leakages are easily happened at high speed via-ROM or high temperature environment and the read voltage of the code- 1  cell C 91  cannot be accurately identified. Therefore, how to compensate the read voltage under the bit-line leakage is an important issue nowadays. 
     SUMMARY 
     The disclosure is directed to a sense amplifier for reading a via Read-Only Memory (Via-ROM). An adaptive keeper is used to adaptively compensates a read voltage of a memory cell whose via is opened when a bit-line leakage is happened. 
     According to one embodiment, a sense amplifier for reading a via Read-Only Memory (Via-ROM) is provided. The sense amplifier includes a read circuit, an adaptive keeper circuit and a leakage monitor circuit. The read circuit is connected to the via-ROM. The adaptive keeper circuit is connected to the read circuit. The leakage monitor circuit is connected to the adaptive keeper circuit for forming a current mirror, such that the adaptive keeper circuit compensates a read voltage of a memory cell whose via is opened when a bit-line leakage is happened. 
     According to another embodiment, a sense amplifier for reading a via Read-Only Memory (Via-ROM) is provided. The sense amplifier includes a read circuit, a hybrid keeper circuit and a leakage monitor circuit. The read circuit is connected to the via-ROM. The hybrid keeper circuit is connected to the read circuit. The hybrid keeper circuit includes a static keeper circuit and an adaptive keeper circuit. The static keeper circuit and the adaptive keeper circuit are connected in parallel. The leakage monitor circuit is connected to the adaptive keeper circuit for forming a current mirror, such that the adaptive keeper circuit compensates a read voltage of a memory cell whose via is opened when a bit-line leakage is happened. 
     According to alternative another embodiment, a sense amplifier for reading a via Read-Only Memory (Via-ROM) is provided. The sense amplifier includes a read circuit, a static keeper circuit and a leakage monitor circuit. The read circuit is connected to the via-ROM. The static keeper circuit is connected to the read circuit. The leakage monitor circuit is connected to the read circuit for forming a current mirror, such that a read voltage of a memory cell whose via is opened is compensated when a bit-line leakage is happened. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  (prior art) shows an example a Via-ROM. 
         FIG. 2  shows a sense amplifier according one embodiment. 
         FIG. 3  shows a sense amplifier according another embodiment. 
         FIG. 4  shows a sense amplifier according another embodiment. 
     
    
    
     In the following detailed description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the disclosed embodiments. It will be apparent, however, that one or more embodiments may be practiced without these specific details. In other instances, well-known structures and devices are schematically shown in order to simplify the drawing. 
     DETAILED DESCRIPTION 
     Please refer to  FIG. 2 , which shows a sense amplifier SA 1  according one embodiment. The sense amplifier SA 1  is used for reading a via Read-Only Memory (Via-ROM)  100 . The sense amplifier SA 1  includes a read circuit R 1 , an adaptive keeper circuit AK 1  and a leakage monitor circuit LM 1 . The read circuit R 1  is connected to the Via-ROM  100 . The adaptive keeper circuit AK 1  is connected to the read circuit R 1 . The leakage monitor circuit LM 1  is connected to the adaptive keeper circuit AK 1 . 
     The read circuit R 1  is used for reading the read voltage of one memory cell of the Via-ROM  100 , such as a code- 1  cell C 1  whose via is opened, or a code- 0  cell (not shown) whose via is conducted. The code- 1  cell C 1  is connected to a word line WL and a bit line BL. Because the via of the code- 1  cell C 1  is opened, the read voltage of the code- 1  cell C 1  should be high. However, when the bit-line leakage is happened, the read voltage of the code- 1  cell C 1  may be dropped. 
     The leakage monitor circuit LM 1  is used for providing a leakage current Ioff. The leakage monitor circuit LM 1  and the adaptive keeper circuit AK 1  are connected to form a current mirror, such that the adaptive keeper circuit AK 1  compensates the read voltage of the code- 1  cell C 1  when the bit-line leakage is happened. 
     The leakage current Ioff of the leakage monitor circuit LM 1  and a driving of the adaptive keeper circuit AK 1  have a positive relationship. If the temperature is high or the speed of the Via-ROM is high, the bit-line leakage is easily happened. The leakage current Ioff of the leakage monitor circuit LM 1  is high and the driving of the adaptive keeper circuit AK 1  is high. Therefore, even if the read voltage of the code- 1  cell C 1  is greatly dropped due to the bit-line leakage, the adaptive keeper circuit AK 1  has enough driving ability to compensate the read voltage of the code- 1  cell C 1 . 
     If the temperature is low or the speed of the Via-ROM  100  is low, the bit-line leakage is not easily happened. The leakage current Ioff of the leakage monitor circuit LM 1  is low and the driving of the adaptive keeper circuit AK 1  is low. Therefore, when the read voltage of the code- 1  cell C 1  is not dropped or is slightly dropped due to the bit-line leakage, the adaptive keeper circuit AK 1  has low driving ability to slightly compensate the read voltage of the code- 1  cell C 1 . 
     Further, when a code- 0  cell (not shown) is read, the adaptive keeper circuit AK 1  has low driving ability or no driving ability, such that the read voltage of the code- 0  cell (not shown) can be accurately dropped to be ground. Thus, even if the bit-line leakages are happened at high speed via-ROM or high temperature environment and the read voltages of the code- 1  cell C 1  and the code- 0  cell (not shown) can be accurately identified respectively. 
     Referring to  FIG. 2 , a gate of a transistor T 11  of the leakage monitor circuit LM 1  is connected to a gate of a transistor T 12  of the adaptive keeper circuit AK 1 , and the gate of the transistor T 11  is connected to the source/drain of the transistor T 11 . A bias voltage Vbias of the transistor T 11  drives the transistor T 12  to be turned on. 
     In this embodiment, the leakage monitor circuit LM 1  and the read circuit R 1  are substantially the same. The leakage monitor circuit LM 1  is connected to a plurality of dummy cells, such as a plurality of code- 0  cells C 0 ′. Each gate of the code- 0  cells C 0 ′ is connected to a dummy word line WL′ which is grounded. Therefore, the leakage current Ioff can be simulated. 
     In one embodiment, the number of the dummy cells may range from 64 to 512, such as 64, 128, 511 or 512. The number of dummy cells connected to the leakage monitor circuit LM 1  is programmed. 
     Please refer to  FIG. 3 , which show a sense amplifier SA 2  according to another embodiment. In this embodiment, the sense amplifier SA 2  includes a read circuit R 2 , a hybrid keeper circuit HK 2  and a leakage monitor circuit LM 2 . The read circuit R 2  is similar to the read circuit R 1 , the leakage monitor circuit LM 2  is similar to the leakage monitor LM 1 , and the similarities are not repeated here. The hybrid keeper circuit HK 2  is connected to the read circuit R 2  and includes a static keeper circuit SK 2  and an adaptive keeper circuit AK 2 . The static keeper circuit SK 2  and the adaptive keeper circuit AK 2  are connected in parallel. 
     In this embodiment, the leakage monitor circuit LM 2  and the read circuit R 2  are substantially the same. The leakage monitor circuit LM 2  is connected to several dummy cells, such as the code- 0  cells C 0 ′. Each gate of the code- 0  cells C 0 ′ is connected to the dummy word line WL′ which is grounded. Therefore, the leakage current Ioff can be simulated. 
     The leakage current Ioff of the leakage monitor circuit LM 2  and a driving of the adaptive keeper circuit AK 2  have a positive relationship. If the temperature is high or the speed of the Via-ROM is high, the bit-line leakage is easily happened. The leakage current Ioff of the leakage monitor circuit LM 2  is high and the driving of the adaptive keeper circuit AK 2  is high. Therefore, even if the read voltage of the code- 1  cell C 1  is greatly dropped due to the bit-line leakage, the adaptive keeper circuit AK 2  has enough driving ability to compensate the read voltage of the code- 1  cell C 1 . 
     If the temperature is low or the speed of the Via-ROM  100  is low, the bit-line leakage is not easily happened. The leakage current Ioff of the leakage monitor circuit LM 2  is low and the driving of the adaptive keeper circuit AK 2  is turned off. Therefore, when the read voltage of the code- 1  cell C 1  is not dropped, the adaptive keeper circuit AK 2  has no driving ability and will not compensate the read voltage of the code- 1  cell C 1 . 
     Further, when a code- 0  cell (not shown) is read, the adaptive keeper circuit AK 2  has no driving ability, such that the read voltage of the code- 0  cell (not shown) can be accurately dropped to be ground. 
     In this embodiment, the driving of the static keeper circuit SK 2  is less than the driving of the adaptive keeper circuit AK 2 . The static keeper circuit SK 2  is used for assisting the adaptive keeper circuit AK 2  at the low temperature. 
     For example, if the temperature is low, the leakage current Ioff of the leakage monitor circuit LM 2  is low and the driving of the adaptive keeper circuit AK 2  is low. Even if the driving of the adaptive keeper circuit AK 2  is lowered, the static keeper circuit SK 2  still can compensate the read voltage of the code- 1  cell C 1 . Thus, even if the bit-line leakages are happened at high speed via-ROM or high temperature environment and the read voltages of the code- 1  cell C 1  and the code- 0  cell (not shown) can be accurately identified respectively. 
     In one embodiment, the number of the dummy cells may range from 64 to 512, such as 64, 128, 511 or 512. The number of dummy cells connected to the leakage monitor circuit LM 2  is programmed. 
     Please referring to  FIG. 4 , which shows a sense amplifier SA 3  according to another embodiment. The sense amplifier SA 3  includes a read circuit R 3 , a static keeper circuit SK 3  and a leakage monitor circuit LM 3 . The static keeper circuit SK 3  is connected to the read circuit R 3  to compensate the read voltage of the code- 1  cell C 1  when the bit-line leakage is happened. 
     Further, in this embodiment, the leakage monitor circuit LM 3  is connected to the read circuit R 3  for forming a current mirror. A gate of a transistor T 31  of the leakage monitor circuit LM 3  is connected to a gate of a transistor T 32  of the read circuit R 3 . When the bit-line leakage is happened, a bias voltage Vbias of the transistor T 31  drives the transistor T 32  to be turned on, such that a compensation voltage Vcp can compensate the read voltage of the code- 1  cell C 1 . Thus, even if the bit-line leakages are happened at high speed via-ROM or high temperature environment and the read voltages of the code- 1  cell C 1  and the code- 0  cell (not shown) can be accurately identified respectively. 
     It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed embodiments. It is intended that the specification and examples be considered as exemplary only, with a true scope of the disclosure being indicated by the following claims and their equivalents.