Patent Publication Number: US-6906529-B2

Title: Capacitive sensor device with electrically configurable pixels

Description:
BACKGROUND OF THE INVENTION 
   The present invention relates generally to capacitive sensors, and more particularly to an improved sensor device whose principal use is as a fingerprint sensor. 
   A capacitive distance sensor is disclosed in commonly assigned U.S. Pat. No. 6,114,862 by Tartagni et al., the relevant portions of the disclosure of which are incorporated herein by reference. The Tartagni patent discloses the basic structure and operation of a conventional solid-state fingerprint sensor that is formed on a single semiconductor chip.  FIGS. 1 and 2  herein are simplified schematic views generally corresponding to  FIGS. 1 and 4  of the Tartagni patent. The present invention provides an improvement over the structure disclosed in the Tartagni patent. 
   In  FIG. 1  a simplified layout of sixteen sensor elements or pixels conveys the concept of the system architecture of the sensor device, which is designated generally by reference numeral  10 , it being understood that many more pixels are employed in practice. For example, STMicroelectronics, Inc. manufactures and markets fingerprint sensors under the brand TouchChip®, which includes Model TCS2CF having 208×288 pixels and Model TCS1CD having 256×360 pixels. 
   These TouchChip® fingerprint sensors employ an active capacitive pixel-sensing technology, the fundamental aspects of which are disclosed in the Tartagni patent and conceptually reproduced herein in  FIGS. 1 and 2 . Each of these TouchChip® models employs an array pitch of 50 microns in which a space of 50×50 microns is allocated to each pixel providing an image resolution of 508 dots/inch (DPI) in both X and Y directions. The smaller Model TCS2CF sensor has a sensor surface size of 10.4×14.4 mm, and is designed for integration into portable electronic devices, such as laptop or notebook computers. The larger Model TCS1CD sensor has a sensor surface size of 18.0×12.8 mm, and is designed for integration into various computer and security systems that can accommodate its slightly larger size and usefully employ a larger fingerprint image. 
   With reference again to  FIG. 1 , the sensor device  10  includes sensor elements or pixels, some of which are designated by reference numeral  12 , arranged in a two-dimensional array A of X rows and Y columns. As noted above in describing the TCS2CF and TCS1CD TouchChip® fingerprint sensors, typically there are more rows than columns. A horizontal scanning stage  14  and a vertical scanning stage  16  are provided for addressing one pixel  12  at a time according to a predetermined scanning sequence. Control lines  18  from the scanning stages  14  and  16  are shown partially for clarity of illustration, but will be understood to run through the array to access each of the pixels  12 . 
   The sensor device  10  also includes a supply and logic unit  20 , which supplies power to the circuit elements of the device (including the pixels  12 ), controls the stages  14  and  16  for sending signals to the pixels  12 , and provides timing for various device operations. The unit  20  also sends a reference voltage pulse out on line  22 , which is connected to lines  24  running vertically through the array A to each of the pixels  12 . In a timed sequence in response to control signals from the scanning stages  14  and  16 , the pixels  12  provide output signals on lines  26 , which are connected to a common line  28  running from the unit  20  to a buffer  30 . The buffer  30  is connected to an analog-to-digital (A/D) converter  32 , which sends digital signals representing the values of the pixel output signals to output logic circuitry  34 . The output logic circuitry  34  has an output terminal  36  for sending data to a system processor (not shown) for fingerprint verification or imaging depending on the particular application. 
     FIG. 2  schematically shows two adjacent pixels  12 , which are separately designed as pixel  12 A and pixel  12 B. A skin surface portion  38  of a human finger is depicted over the two pixels with a fingerprint ridge  40  over pixel  12 A and a fingerprint valley  42  over pixel  12 B. A dielectric layer  44 , which is provided atop the array of pixels, has an upper surface  46  that defines a sensing surface to which the fingerprint-bearing skin of a user&#39;s finger is applied in a sensing operation. It will be appreciated that fingerprint ridges like the ridge  40  will directly contact the sensing surface  46 , and that fingerprint valleys like the valley  42  will be located just above the sensing surface  46 . Preferably, a grounded surface grid  48  is provided in the dielectric layer  44  running periodically through the array between rows and columns of pixels. This feature provides a constant reference voltage at the sensing surface  46 . The grounded surface grid  48  can also be connected to an electrostatic discharge (ESD) protection circuit (not shown). 
   Each pixel, of which pixels  12 A and  12 B are representative, includes first and second coplanar capacitor plates  50  and  52  embedded in the dielectric layer  44  just beneath the sensing surface  46 . One possible layout of the plates  50  and  52  is shown in  FIG. 1 , in which each pixel  12  has rectangular shaped plates  50  and  52  arranged side by side. Connected to the plates  50  and  52  of each pixel  12 A and  12 B is a sensor circuit  54 , which is shown as a generalize circuit block in FIG.  3 . As seen in  FIG. 2 , each sensor circuit  54  includes an inverting amplifier I connected across the plates  50  and  52 . A reference voltage pulse V r  is applied through a row select switch T 1  and an input capacitor C i  to the input of the inverting amplifier I. A reset switch T 2  is connected across the plates  50  and  52  of each pixel and in parallel with the inverting amplifier I. A reset signal R from the supply and logic unit  20 , which may be applied through the horizontal scanning stage  14 , controls the state of the reset switch T 2 . Parasitic capacitances are present in the sensor circuit  54  but are not expressly shown. The output of each inverting amplifier I is connected to a pixel output V out  through column select switch T 3 . 
   Referring collectively to  FIGS. 1-3 , the sensor device  10  operates as follows. With the fingerprint-bearing skin  38  of a user&#39;s finger in contact with the sensing surface  46 , the supply and logic unit  20  begins sequentially addressing individual pixels  12 . The reset switches T 2  of each pixel  12  are normally closed so that each inverting amplifier I begins a sensing operation at its logical threshold voltage. Just before each pixel  12  is addressed, its reset switch T 2  is opened. A row select RS signal is applied by the horizontal scanning stage  14  to each row sequentially, thus closing the row select switches T 1  in the selected row. A column select CS signal is also applied by the vertical scanning stage  16  to each column sequentially, thus closing the column select switches T 3  in the selected column. After a selected pixel  12  has been addressed in this manner, the reference voltage pulse V r  is applied causing the inverting amplifier I of the selected pixel  12  to generate an output signal V out  that is a function of the capacitance sensed by the plates  50  and  52 , which varies with the proximity of the fingerprint-bearing skin  38  of the user&#39;s finger above the sensing surface  46  at the site of the selected pixel  12 . Sequential addressing continues until each pixel&#39;s output V out  has been read out, converted to a digital value by the A/D converter  32 , and then transmitted to the output logic circuitry  36 , which may include a memory (not shown) for storing the pixel data. 
   Now referring to  FIG. 4 , a cross-section of a portion of an integrated circuit (IC) chip  60  is shown schematically to illustrate typical structures that can be used to fabricate transistors and conductors that form the circuitry of a sensor device. The IC chip  60  can be fabricated using conventional complementary metal-oxide-semiconductor (CMOS) processing technology that permits integration of both NMOS and PMOS transistors on the same chip.  FIG. 4  shows how the reset switch T 2  of  FIG. 2  could be implemented as an NMOS transistor and connected to capacitor plates  50  and  52  located above in dielectric layer  44 . 
   The chip  60  may be fabricated on a low resistivity P-type substrate  62 , which is preferably monocrystalline silicon. Grown atop and considered to be part of the substrate  62  is an epitaxial layer  64 , which is initially high resistivity P-type and is selectively doped during fabrication to form various regions that define circuit elements within the chip  60 . At the upper surface of the epitaxial layer  64  are heavily doped N-type source and drain regions  66  and  68  of NMOS transistor T 2 . The regions  66  and  68  are formed within a P well  70  that has an upper surface portion that defines the channel of transistor T 2 , a conventional gate structure being formed thereover. A PMOS transistor (not shown) can be formed in an N well  72  partially shown at the broken-off right edge of FIG.  4 . The gate structure of transistor T 2  includes a gate oxide layer  74 , a silicided polysilicon gate  76  and oxide sidewall spacers  78 . Such structures and methods for their fabrication are well known. 
   A composite interconnect structure of conductive and insulating layers is built up in successive steps atop the substrate  62 . The composite interconnect structure includes the capacitor plates  50  and  52  imbedded in the dielectric layer  44 , the gate structure of transistor T 2 , and the layers therebetween and surrounding transistor T 2  that encompass all of the other circuit elements of the chip  60 . A thick oxide layer  80 , which is formed atop the epitaxial layer  64 , has openings therein that define isolated active areas within which the regions of circuit elements, such as the source and drain regions  66  and  68  of transistor T 2 , are formed. 
   A dielectric layer  82  overlies the thick oxide layer  80  and the isolated active areas defined in the openings therein, including the regions  66  and  68  of transistor T 2  and the gate structure therebetween. The dielectric layer  82  is preferably a doped oxide such as borophosphosilicate glass (BPSG). A first metalization layer, which preferably primarily comprises aluminum, defines conductive interconnects  84  and  86 , which include contacts  88  that extend through etched openings in the dielectric layer  82  to contact the source and drain regions  66  and  68  of transistor T 2 . Other circuit elements of the chip  60  are interconnected by portions of the first metalization layer in like manner. 
   A planarized dielectric layer  90  covers the metal interconnects  84  and  86  and the portion of BPSG layer  82  that overlies the gate structure of transistors T 2 . Preferably, dielectric layer  90  is a composite of a lower undoped oxide, an intermediate spin-on-glass (SOG), and an upper undoped oxide, which are not shown separately. According to well-known processing techniques, the intermediate SOG portion of the composite dielectric layer  90  is used to planarize the structure. 
   The process continues by etching via openings through the dielectric layer  90  down to the conductive interconnects therebelow, and then performing a second metalization deposition of aluminum, which is patterned to form the plates  50  and  52  and includes metal vias  92  that connect the plates to the underlying conductive interconnects  84  and  86 . Then, the dielectric layer  44  is formed, preferably by successive deposition steps that produce a composite multilayer structure that includes a hydrogen silesquioxane (HSG) portion between the plates  50  and  52 , a thin intermediate portion of phosphosilicate glass (PSG) atop the HSQ and the plates  50  and  52 , a second intermediate portion of silicon nitride atop the PSG, and an outer portion of silicon carbide atop the silicon nitride. These multilayer portions of dielectric layer  44  are not separately delineated in  FIG. 4 , but techniques for their fabrication are well known. It will be appreciated by those skilled in the art that the outer portion of silicon carbide provides a hard, scratch-resistant sensing surface  46 . 
   The layout chosen for the plates  50  and  52  affects the sensitivity of the pixels. This fact is recognized by the Tartagni patent, which discloses in FIGS. 8-12 several different plate patterns as alternatives to two side-by-side rectangular plates. The various different plate patterns disclosed by the Tartagni patent have different sensitivities, which is a function of both the direct capacitance and fringing capacitance of the particular plate pattern. The direct capacitance of each plate is a function of its area and its proximity to the object being sensed. The fringing capacitance of two side-by-side plates is a function of the total perimeter length of adjacent faces or edges of the plates and their proximity to the object being sensed. The total feedback capacitance experienced by the inverting amplifier I is a function of the direct capacitances between the plates and the object being sensed, and of the fringing capacitance, which is modulated by the object being sensed. 
   The present invention provides an improved sensor device that can be fabricated using conventional CMOS processing techniques similar to those described above. Regardless of the particular plate pattern chosen, whether it is one of the five specific patterns shown in FIGS. 8-12 of U.S. Pat. No. 6,114,862 or a further variation thereof, each pixel output has an accuracy that depends to an extent on the particular plate pattern. However, it will be appreciated that the particular plate pattern is a permanent feature of a sensor device constructed according to the teachings of the Tartagni patent. The present invention recognizes and addresses this problem. 
   SUMMARY OF THE INVENTION 
   A sensor device structured according to the present invention has capacitor plates at each pixel location in an array of pixels, the plates being electrically configurable to assume various different patterns so that multiple sensing operations can be performed using different plate patterns to provide multiple capacitance readings for each pixel. The multiple capacitance readings are combined using a suitable algorithm to produce data representing a more accurate capacitance measurement for each pixel, enabling the capturing of a more accurate representation of the object being sensed, such as a human fingerprint. 
   The electrically configurable plates at each pixel location can be implemented in a subarray beneath a sensing surface. Each plate of each subarray can be selectively electrically connected to either one of two lower plates that define the capacitance that is sensed at each pixel during one sensing operation in a sequence of multiple sensing operations. The subarray plates at each pixel location can assume various different patterns according to their connection to one or the other of the two lower plates. The connection of each subarray plate to a lower plate can be effected by a memory cell dedicated to each subarray plate, the memory cell storing a logic zero or a logic one and driving one of two transistor switches ON according to the stored logic state to effect the connection. 
   The novel features believed to be characteristic of the invention are set forth in the appended claims. The nature of the invention, however, as well as its features and advantages, may be understood more fully upon consideration of the following illustrative embodiments, when read in conjunction with the accompanying drawings, wherein: 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a schematic block diagram showing the layout of the principal components of a prior-art sensor device over which the present invention provides an improvement; 
       FIG. 2  is a circuit diagram shown with a schematic side view of a small portion of a human finger contacting a sensing surface of a dielectric layer, shown in cross section, and positioned above two adjacent pixels of the device of  FIG. 1 ; 
       FIG. 3  is a generalized block diagram of a sensor circuit for one of the pixels of  FIG. 2 ; 
       FIG. 4  is a schematic cross section of a portion of a semiconductor chip showing a transistor integrated in the structure of one of the pixels of  FIG. 2 , only the metal and conductive polysilicon portions being cross-hatched for clarity of illustration; 
       FIG. 5  is a schematic plan view of a subarray of capacitor plates according to one embodiment of the invention; 
       FIG. 6  is a circuit diagram shown with a schematic cross section of a row of subarray plates taken along line  6 — 6  of  FIG. 5 ; 
       FIGS. 7A-F  are schematic plan views of subarrays of plates configured in selected different three-by-three patterns according to one embodiment of the invention; 
       FIGS. 8A-F  are schematic plan views of subarrays of plates configured in selected four-by-four patterns according to another embodiment of the invention; 
       FIGS. 9A-C  are schematic plan views of subarrays of plates configured in selected five-by-five patterns according to another embodiment of the invention; 
       FIG. 10  is a schematic block diagram similar to  FIG. 1 , but instead showing subarrays of plates at each pixel location according to one embodiment of the invention; and 
       FIG. 11  is a circuit diagram of an SRAM memory cell that can be employed in configuring the subarray plates of the inventive sensor device. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
   Referring to  FIGS. 5 ,  6 , and  10 , a sensor device  110  according to the present invention will now be described.  FIGS. 5 and 6  illustrate only one pixel  100  of the inventive sensor device  110 , it being understood that many additional identical pixels are laid out in a two-dimensional array, such as the array A depicted in FIG.  10 .  FIG. 10  is similar to  FIG. 1 , similar parts bearing similar reference numerals. Scanning stages  114  and  116 , under the control of supply and logic unit  120 , control the operation of the pixel array through lines  118  running through the array. Reference voltage pulses are applied on lines  124  to sensor circuits within the array, and sensed capacitance values are read out on lines  126  and inputted to buffer  130  on line  128 . The buffer  130  is connected to A/D converter  132 , which converts the sensed capacitance values to digital data, which are stored in output logic circuitry  134  and can be output on terminal  136  for further processing. 
   Instead of the two side-by-side rectangular plates for each pixel  12  of  FIG. 1 , a subarray of plates arranged in rows and columns is provided for each pixel  100  of the sensor device  110  of FIG.  10 . In the example shown in  FIG. 10 , each subarray has three rows and three columns of plates, providing nine total plates per subarray, which is one of various different subarray layouts contemplated by the invention. It is preferred for simplicity, but not necessary, that each subarray be organized in straight-line rows and columns of equal number. Other organizations and pixel shapes are possible and within the broader concept of the invention. Also,  FIG. 10  shows only four rows and four columns of pixels  100  to convey the concept of the basic system architecture, though there will be many more rows and columns of pixels in reality. In practice, when employed in a fingerprint sensor, the array of pixels of the inventive device may be arranged in a rectangular array of X rows and Y columns, such as the 208×288 or 256×360 pixel arrays of the above-mentioned TouchChip® fingerprint sensors of the prior art. 
   The preferred pixel  100  of  FIG. 5  includes a subarray of upper capacitor plates in which nine upper plates UP are arranged in three rows and three columns. Each plate preferably has a square layout, but may be rectangular or have a more complex shape consistent with the inventive concept. The upper plates are individually labeled UP 11  through UP 33  in which the subscripts designate the row and column of the subarray for the particular upper plate. Two lower plates LP 1  and LP 2  are provided for each pixel  100 , which are shown in dashed outline in FIG.  5  and in cross section in FIG.  6 . It will be appreciated from  FIG. 5  that each lower plate LP 1  and LP 2  overlaps at least one edge of each of the nine upper plates UP 11  through UP 33 . A common plate CP corresponding to each upper plate UP is centered beneath its upper plate, as shown in dashed outline in FIG.  5  and in cross section in  FIG. 6. A  via  102  extends down from each upper plate to connect it to its underlying common plate CP, as seen with respect to upper plates UP 21 , UP 22 , and UP 23  in FIG.  6 . 
   Shown in block diagram form in  FIG. 6  are the circuit elements that characterize each pixel  100  and their interconnections with each other, the lower plates LP and common plates CP. Such circuit elements are used to configure the upper plates UP during a sensing operation, and include memory cells M 21 , M 22 , and M 23 , and transistor switches T A , T B , T C , T D , T E , and T F , connected in the manner shown. These transistor switches preferably are implemented as NMOS transistors, and will be considered to be such in the description that follows. Each memory cell functions as a selectively configurable latch. 
   It will be appreciated from considering  FIGS. 5 and 6  together that the top row of upper plates UP 11 , UP 12 , and UP 13  and the bottom row of upper plates UP 31 , UP 32 , and UP 33  shown in  FIG. 5  each has a similar arrangement of lower plates, common plates, memory cells, and transistor switches as is shown in FIG.  6 . The circuit elements include a single sensor circuit  154  for each pixel  100 . The sensor circuit  154  is preferably essentially identical to the prior-art sensor circuit  54  described above, except that the sensor circuit  154  is connected across the first lower plate LP 1 , and the second lower plate LP 2  of the pixel  100 . 
   Each memory cell corresponding to each upper plate UP stores a logic zero or a logic one during a sensing operation, the stored bits corresponding to a predetermined interconnection pattern of the upper plates UP with one or the other of the lower plates LP 1  or LP 2 . As shown in  FIG. 6 , each memory cell has a true data node N T , a complementary data node N C , a connection to a word line W L , and a connection to a bit line B L . Memory cell M 21  has its data nodes connected to transistors T A  and T B , memory cell M 22  has its data nodes connected to transistors T C  and T D , and memory cell M 23  has its data nodes connected to transistors T E  and T F . 
   Referring to  FIGS. 7A through 7F , various selected patterns for the interconnection of the upper plates UP of  FIG. 5  are depicted by the shaded and unshaded squares representing the upper plates of a 3×3 subarray. Let it be assumed that all of the unshaded plates represent a first set in which each plate has been electrically connected to the first lower plate LP 1 , and that all of the shaded plates represent a second set in which each plate has been electrically connected to the second lower plate LP 2 . 
   By way of example, considering the middle row of FIG.  7 D and comparing it to  FIG. 6 , we can determine the logic states of the memory cells M 21 , M 22 , and M 23  and the ON/OFF states of the transistors T A , T B , T C , T D , T E , and T F  for effecting the electrical connections in  FIG. 6  for the condition indicated by the middle row of FIG.  7 D. Specifically, memory cell M 21  must be storing a logic one, and memory cells M 22  and M 23  must each be storing a logic zero. Therefore, the true data node N T  of memory cell M 21 , and the complementary data nodes N C  of memory cells M 22  and M 23  will each be at a high logic-level voltage, thus turning ON transistors T A , T C , and T F . Accordingly, transistor T A  electrically connects upper plate UP 21  to the first lower plate LP 1 , transistor T C  electrically connects upper plate UP 22  to the second lower plate LP 2 , and transistor T F  electrically connects upper plate UP 23  to the second lower plate LP 2 . It will also be appreciated that the complementary data node N C  of memory cell M 21  and the true data nodes N T  of memory cells M 22  and M 23  will each be at a low logic-level voltage, thus holding transistors T B , T D , and T E  OFF, thereby preventing electrical connection of the upper plates to the lower plates through those transistors under the stated condition. A similar determination can be made for each of the rows in each of the patterns shown in  FIGS. 7A through 7F , each pattern having a different set of shaded plates and a different set of unshaded plates, with corresponding connections being made to the lower plates of the pixel. 
   By varying the electrical interconnections between the upper plates UP and the lower plates LP of the subarray of pixel  100 , a sequence of different capacitance readings can be made for each pixel  100  of the sensor device  110  of the present invention.  FIG. 10  shows the basic system architecture of the inventive device  110 , which is similar to the basic system architecture of the prior-art device  10  depicted in FIG.  1 . However, rather than having a two-plate per pixel structure, each pixel  100  of the inventive device  110  has a subarray of upper capacitor plates, each of which can be dynamically electrically interconnected with one of two lower capacitor plates. 
   Moreover, the circuit elements for each pixel  100  are more complex in the inventive device  110 , which also includes a memory cell driving a pair of transistor switches for each upper plate of the subarray, as shown in FIG.  6 . This additional circuitry will require corresponding modifications to the basic system architecture. In particular, the modified horizontal and vertical scanning stages  114  and  116  include circuitry for driving the word lines and bit lines for addressing and reading in data bits to the memory cells to set up the upper plate/lower plate interconnection patterns before each sensing operation. The modified supply and logic unit  120  must additionally provide power to the memory cells in the pixel subarrays, and will include logic circuitry for setting up the various subarray patterns (shown by way of example in FIGS.  7 A through  7 F). Also, the unit  120  will require additional circuitry for timing the sequence of memory cell patterning cycles and consecutive sensing operations. Preferably, the output logic circuitry  134  is used to store capacitance measurement data, which will include data for at least several consecutive sensing operations. 
   For example, if 3×3 subarrays are used and the six patterns shown in  FIGS. 7A through 7F  are set up consecutively, then the data memory in the output logic circuitry  134  must be able to store six sets of capacitance measurement data for the entire pixel array, which could have 256×360 pixels for a modified version of a Model TCS1CD TouchChip® fingerprint sensor. The modified output logic circuitry  134  could also be programmed to algorithmically combine the several different sets of capacitance measurement data into a single set of pixel values for the entire array. In its most simple form, an algorithm could generate an average capacitance value from the several stored values for each pixel. More complex statistical algorithms could be used. The modified output logic circuitry  134  could thus read out the algorithmically combined values to a system processor, which can then perform a fingerprint verification operation or fingerprint imaging operation with a higher degree of accuracy. 
   Referring again to  FIGS. 7A through 7F , another aspect of the invention will be described. In order to reduce the number of memory cell write operations between sensing operations for faster fingerprint data acquisition, less than all of the memory cells can have their logic states changed between sensing operations while still achieving significantly different upper plate/lower plate interconnection patterns in each successive sensing operation. It will be seen that in moving from the pattern of  FIG. 7A  to the pattern of  FIG. 7B , only the upper right square and the middle-row center square in the subarray pattern have been changed. Similarly, in moving from the pattern of  FIG. 7B  to that of  FIG. 7C , only the upper left and lower center squares have changed. From  FIG. 7C  to  FIG. 7D , only the right center and lower-right corner squares have changed. From  FIG. 7D  to  FIG. 7E , only the left center and lower-left corner squares have changed. From  FIG. 7E  to  FIG. 7F , only the middle center and upper center squares have changed. Therefore, if one chose to use the successive patterns of  FIGS. 7A through 7F  in six successive sensing operations, after the first sensing operation, only two memory cell write operations per pixel need to be performed between sensing operations. Note that preferably each pixel stores the same subarray pattern in each sensing operation so that entire rows of the array, or even groups of rows, can be written into simultaneously, depending on the power of the bit-line driving circuitry. Note also that randomly generated subarray patterns could be used as an alternative to predetermined patterns, by including circuitry on the chip for random bit generation. It is believed, however, that using predetermined subarray patterns will achieve more consistently accurate results. Such predetermined subarray patterns can be stored on chip in a read-only memory (ROM). 
   Now referring to  FIGS. 8A through 8F , various patterns are shown using an alternative subarray size of sixteen upper capacitor plates arranged in four rows and four columns. Each upper capacitor plate can be selectively electrically connected to either one of two lower capacitor plates using the same basic technique described in connection with FIG.  6 . That is, each upper capacitor plate has an underlying common plate and a memory cell for driving ON one of two transistors to effect the interconnection. The two lower plates can be laid out interdigitally between adjacent columns.  FIGS. 8A through 8F  show such a layout for lower plate LP 1  and lower plate LP 2 . Other layouts are possible. 
   Once again, as noted above in connection with the 3×3 subarray patterns, it may be advantageous to change less than all of the upper plate/lower plate interconnections in the 4×4 subarrays in successive sensing operations. In moving sequentially through the patterns shown by the shaded and unshaded upper plates in  FIGS. 8A through 8F , only four of sixteen such interconnections are made at each stage. For example, in moving from  FIG. 8A  to  FIG. 8B , only the upper plates in the row second from the top have their interconnection with the lower plates LP 1  and LP 2  changed. It will be understood that the unshaded upper plates are each electrically connected to the first lower plate LP 1 , and that the shaded upper plates are each electrically connected to the second lower plate LP 2 . 
   Now referring to  FIGS. 9A through 9C , various upper plate/lower plate interconnection patterns are shown using an alternative subarray size of twenty-five upper capacitor plates arranged in five rows and five columns. Each upper capacitor plate can be selectively electrically connected to either one of two lower capacitor plates using the same basic technique as described in connection with FIG.  6 .  FIGS. 9A through 9C  show one possible interdigitated layout for the lower capacitor plates LP 1  and LP 2 . It will also be appreciated that only eight memory cell logic state changes are made in going from the shaded/unshaded pattern of  FIG. 9A  to that of  FIG. 9B , and from that of  FIG. 9B  to that of  FIG. 9C , with an advantageous minimization of memory write cycles while achieving significant pattern variation in successive sensing operations. 
   It will be appreciated that the 3×3 subarrays shown in  FIG. 10  can be replaced by 4×4 subarrays of upper plates with interdigitated lower plates LP 1  and LP 2  as shown in  FIG. 8A , or the 3×3 subarrays can be replaced by 5×5 subarrays as shown in FIG.  9 A. Even larger numbers of plates in larger subarrays could be implemented in the basic system architecture of FIG.  10 . If the size of each pixel, 50×50 microns as an example, is kept constant, then increasing the number of subarray plates will require each plate to be made smaller. However, if the pixel size is permitted to increase and fewer pixels are used in the device, the subarray plate size can be kept constant as the number of subarray plates is increased. It is contemplated that an optimum design can be arrived at with a minimum of experimentation. 
   Referring again to  FIG. 6 , the memory cells M 21 , M 22 , and M 23 , each with their true and complementary data nodes N T  and N C , can be conveniently implemented using a static random access memory cell or SRAM cell, which is a well-known type of memory cell. Such SRAM memory cells are often implemented using six transistors, as shown by way of example in FIG. 1 of U.S. Pat. No. 3,879,621 by Cavaliere et al. However, since it is not necessary to read data from the memory cells used in the subarrays of the inventive device  110 , a simplified version of the SRAM memory cell disclosed in the Cavaliere patent can be employed, as will now be described. 
   Referring to  FIG. 11 , a five-transistor SRAM memory cell M is shown with NMOS transistors Q 1 , Q 2 , and Q 3 , and PMOS transistors Q 4  and Q 5 . The memory cell M has a true data node N T  a complementary data node N C . Those skilled in the art will recognize that transistors Q 2  and Q 4  form one CMOS inverter, and that transistors Q 3  and Q 4  form a second CMOS inverter, each with their transistor drains D connected in common at one of the data nodes. The sources S of PMOS transistors Q 4  and Q 5  are connected to a high logic-level voltage, such as a positive supply voltage designated as +V. The sources S of NMOS transistors Q 2  and Q 3  are connected to a low logic-level voltage, such as ground supply voltage designated by the conventional ground symbol. The gates G of transistors Q 2  and Q 4  are connected together and to the complimentary data node N C . The gates G of transistors Q 3  and Q 5  are connected together and to the true data node N T . Those skilled in the art will recognize that the two cross-connected inverters latch a high logic-level voltage on one of the two data nodes and a low logic-level voltage on the other data node. The data nodes N T  and N C  drive the gates G of transistors T X  and T Y , which correspond to the pairs of transistors T A  and T B , or T C  and T D , or T E  and T F , shown in FIG.  6 . 
   In order to set the logic state of the memory cell M, or change its state, access to a bit line B L  is provided by NMOS transistor Q 1 , which can be turned ON by applying a high logic-level signal to its gate G through a word line W L . When transistor Q 1  has been selectively turned ON, a voltage applied to the bit line B L  drives the true data node N T  to a corresponding logic level. For example, to write a logic zero into the memory cell M, the bit line B L  is connected to the ground supply voltage while transistor Q 1  is ON, thereby discharging the true data node N T , and consequently turning PMOS transistors Q 5  ON and NMOS transistor Q 3  OFF, so that the complementary data node N C  is charged to the high logic-level voltage through transistor Q 5 . Then transistor Q 1  is turned OFF latching the true data node N T  low and the complementary data node N C  high. Similarly, to write a logic one into the memory cell M, the bit line B L  is connected to the positive supply voltage +V while transistor Q 1  is ON, thereby charging the true data node N T  to the high logic-level voltage, and consequently turning PMOS transistor Q 5  OFF and NMOS transistor Q 3  ON, so that the complementary data node N C  is held at the low logic-level voltage through transistor Q 3 . Then, transistor Q 1  is turned OFF latching the true data node high and the complementary data node low. As is known in the art, transistor Q 1  is made larger than transistors Q 2  and Q 4 , thereby allowing the true data node N T  to be driven to the desired logic-level voltage from the bit line B L  through transistor Q 1  against the will of whichever transistor Q 2  or Q 4  that happens to be ON. 
   An alternative to the CMOS type SRAM memory cell disclosed in the Cavaliere patent, is an NMOS resistive-load SRAM memory cell, an example of which is disclosed in FIG. 2 of U.S. Pat. No. 4,297,721 by McKenny et al. Such resistive-load type SRAM memory cell uses only four NMOS transistors and two polysilicon load resistors. Since, as noted above, the memory cells used in the subarrays of the inventive device do not need to be read, and can be written into by accessing only one data node, a three-transistor modified version of the resistive-load type SRAM memory cell can be employed in the subarrays of the inventive device  110 . 
   It will be appreciated that other types of memory cells could be used in the subarrays of the inventive device. For example, a conventional dynamic RAM (DRAM) type memory cell or a conventional Flash erasable programmable ROM (EPROM) type memory cell could be employed. The term “Flash” refers to the ability to rapidly erase the memory with electrical pulses. Thus, such memory types are also referred to as “electrically erasable” or EEPROM devices. However, each of these different types of memory devices would present their own design challenges to implement. 
   For example, a DRAM memory cell, as the term “dynamic” implies, requires periodic refresh cycles to maintain its storage of a high logic-level voltage, and it only has one data node with limited driving power. Flash EPROM memory cells require programming voltages exceeding the standard supply voltages available on a chip, which generally requires integration of a change pump on the chip. Also, it is typical of Flash EPROM memories that either the entire memory or a block portion of the memory is erased in one step. An example of a basic single-transistor, single capacitor DRAM memory cell is disclosed in U.S. Pat. No. 3,387,286 by Dennard. An example of a Flash EPROM memory cell is disclosed in U.S. Pat. No. 4,958,321 by Chang. In view of the foregoing design challenges, the presently preferred type of memory cell for the subarrays of the inventive device  110  is an SRAM memory cell, such as depicted in  FIG. 11  herein. 
   The relevant portions of the disclosures of U.S. Pat. Nos. 3,879,621; 4,297,721; 3,387,286; and 4,958,321 are incorporated herein by reference. Although preferred embodiments of the invention have been described in detail, it will be understood that various changes and substitutions can be made therein without departing from the spirit and scope of the invention as set forth in the appended claims.