Patent Publication Number: US-2022230055-A1

Title: Computing circuit and data processing method based on convolutional neural network and computer readable storage medium

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application claims the priority benefit of U.S. Provisional Application No. 63/139,809, filed on Jan. 21, 2021 and Taiwan Application No. 110140625, filed on Nov. 1, 2021. The entirety of each of the above-mentioned patent applications is hereby incorporated by reference herein and made a part of this specification. 
    
    
     BACKGROUND 
     Technical Field 
     The disclosure relates to a machine learning (ML) technology, and particularly relates to a computing circuit and a data processing method based on a convolutional neural network (CNN) and a computer readable storage medium. 
     Description of Related Art 
     Machine learning is an important topic in artificial intelligence (AI), and training samples may be analyzed to obtain rules therefrom, so as to predict unknown data through the rules. A machine learning model constructed after learning is used to infer data to be evaluated. 
     There are many types of algorithms for machine learning. For example, a neural network may make decisions through simulating the operation of human brain cells. The convolutional neural network provides better results in terms of image and voice recognition and has gradually become one of the widely applied and mainly researched and developed machine learning architectures. 
     It is worth noting that in the convolutional layer of the convolutional neural network architecture, a processing element slides a convolution kernel or a filter on input data and executes a specific computation. The processing element needs to repeatedly read the input data and a weight value from a memory and output a computation result to the memory. Furthermore, if different convolutional layers adopt convolution kernels with different sizes or different convolution computations, the number of accesses of the memory will be greatly increased. For example, the MobileNet model combines a convolution computation and a depthwise separable convolution computation. Therefore, the computations all need to respectively access the memory. 
     SUMMARY 
     The disclosure provides a computing circuit and a data processing method based on a convolutional neural network and a computer readable storage medium, which integrate multiple convolutional layers, so as to reduce the number of accesses of a memory. 
     A data processing method based on a convolutional neural network of the embodiment of the disclosure includes (but is not limited to) the following steps. Input data is read from a memory. A first computation is performed on first part data of the input data to obtain first output data. The first computation is configured with a first filter. A size of the first output data is related to a size of the first filter of the first computation and a size of the first part data. The first output data is buffered in a first buffer. When the first output data buffered in the first buffer is greater than a first predetermined data amount, a second computation is performed on the first output data to obtain second output data. The second computation is configured with a second filter. A size of the second output data is related to a size of the second filter of the second computation. The second output data is buffered in a second buffer. Third output data obtained by performing a third computation on the second output data is output to the memory. When performing the second computation on the first output data, the first computation is continuously performed on the input data. 
     A computing circuit based on a convolutional neural network of the embodiment of the disclosure includes (but is not limited to) a memory and a processing element. The memory is used to store input data. The processing element is coupled to the memory and includes first, second, and third computing devices, a first buffer memory, and a second buffer memory. The first computing device is used to perform a first computation on first part data of the input data to obtain first output data, and buffer the first output data to a first buffer memory of the processing element. A size of the first output data is related to a size of a first filter of the first computation and a size of the first part data. The second computing device is used to perform a second computation on second input data when the first output data buffered in the first buffer memory meets a size required for the second computation to obtain second output data, and buffer the second output data to a third memory of the processing element. The second computation is configured with a second filter, and a size of the second output data is related to a size of the second filter of the second computation. The third computing device is used to output third output data obtained by performing a third computation on the second output data to the memory. When the second computing device performs the second computation, the first computing device continuously performs the first computation. 
     A computer readable storage medium of the embodiment of the disclosure is used to store a program code, and the processor loads the program code to execute the data processing method based on the convolutional neural network. 
     Based on the above, in the computing circuit and the data processing method based on the convolutional neural network and the computer readable storage medium according to the embodiments of the disclosure, the output data is buffered in the memory in the processing element, and the computation thereof is triggered according to an activation condition of a next computing device (that is, a next computing layer). In this way, the next computing layer may trigger the computation in advance without waiting for a previous computing layer to finish computing all input data. In addition, the embodiments of the disclosure can reduce the number of accesses of the input data from the memory. 
     In order for the features and advantages of the disclosure to be more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a block diagram of elements of a computing circuit based on a convolutional neural network according to an embodiment of the disclosure. 
         FIG. 2  is a flowchart of a data processing method based on a convolutional neural network according to an embodiment of the disclosure. 
         FIG. 3  is a schematic diagram of input data according to an embodiment of the disclosure. 
         FIG. 4  is a schematic diagram of a first computation according to an embodiment of the disclosure. 
         FIG. 5A  and  FIG. 5B  are schematic diagrams of systolic array inputs and outputs according to an embodiment of the disclosure. 
         FIG. 6A  to  FIG. 6C  are schematic diagrams of systolic array outputs according to an embodiment of the disclosure. 
         FIG. 7A  is a schematic diagram of reading input data according to an embodiment of the disclosure. 
         FIG. 7B  is a schematic diagram of first output data according to an embodiment of the disclosure. 
         FIG. 7C  is a schematic diagram of reading input data according to an embodiment of the disclosure. 
         FIG. 7D  is a schematic diagram of first output data according to an embodiment of the disclosure. 
         FIG. 7E  is a schematic diagram of reading input data according to an embodiment of the disclosure. 
         FIG. 7F  is a schematic diagram of first output data according to an embodiment of the disclosure. 
         FIG. 8  is a schematic diagram of reading input data according to an embodiment of the disclosure. 
         FIG. 9A  is a schematic diagram of a trigger condition of a second computation according to an embodiment of the disclosure. 
         FIG. 9B  is a schematic diagram of buffered first output data according to an embodiment of the disclosure. 
         FIG. 10A  is a schematic diagram of a second computation according to an embodiment of the disclosure. 
         FIG. 10B  to  FIG. 10D  are schematic diagrams of second output data according to an embodiment of the disclosure. 
         FIG. 11  is a flowchart of a data processing method based on a convolutional neural network according to an embodiment of the disclosure. 
         FIG. 12A  is a schematic diagram of buffered first output data according to an embodiment of the disclosure. 
         FIG. 12B  is a schematic diagram of buffered second output data according to an embodiment of the disclosure. 
         FIG. 13A  is a schematic diagram of a third computation according to an embodiment of the disclosure. 
         FIG. 13B  is a schematic diagram of third output data according to an embodiment of the disclosure. 
         FIG. 14A  to  FIG. 14C  are schematic diagrams of systolic array outputs according to an embodiment of the disclosure. 
         FIG. 15  is a flowchart of a data processing method with the MobileNet architecture according to an embodiment of the disclosure. 
     
    
    
     DETAILED DESCRIPTION OF DISCLOSED EMBODIMENTS 
       FIG. 1  is a block diagram of elements of a computing circuit  100  based on a convolutional neural network according to an embodiment of the disclosure. Referring to  FIG. 1 , the computing circuit  100  includes (but is not limited to) a memory  110  and one or more processing elements (PE)  120 . 
     The memory  110  may be a dynamic random access memory (DRAM), a flash memory, a register, a combinational logic circuit, or a combination of the above elements. 
     The processing element  120  is coupled to the memory  110 . The processing elements  120  include (but are not limited to) a feature buffer memory  131 , a first first input first output (FIFO) unit  132 , a first weight buffer memory  133 , a first computing device  135 , a first buffer memory  151 , a second weight buffer memory  153 , a second computing device  155 , a second buffer memory  171 , a second first input first output unit  172 , a third weight buffer memory  173 , and a third computing device  175 . 
     In an embodiment, the feature buffer memory  131 , the first FIFO unit  132 , the first weight buffer memory  133 , and the first computing device  135  correspond to one layer of convolutional layer/computing layer. In addition, the first computing device  135  is configured with a first filter used in a first computation. 
     In an embodiment, the feature buffer memory  131  is used to store some or all input data from the memory  110 , the first FIFO unit  132  is used to input and/or output data in the feature buffer memory  131  according to a FIFO rule, the first weight buffer memory  133  is used to store one or more weights (forming a first convolution kernel/filter) from the memory  110 , and the first computing device  135  is used to perform the first computation. In an embodiment, the first computation is a convolution computation and will be detailed in subsequent embodiment. In another embodiment, the first computation may also be a depthwise separable convolution computation or other types of convolution computations. 
     In an embodiment, the first buffer memory  151 , the second weight buffer memory  153 , and the second computing device  155  correspond to one layer of convolutional layer/computing layer. In addition, the second computing device  155  is configured with a second filter used in a second computation. 
     In an embodiment, the first buffer memory  151  is used to store some or all input data output from the first computing device  135 , the second weight buffer memory  153  is used to store one or more weights (forming a second convolution kernel/filter) from the memory  110 , and the second computing device  155  is used to perform the second computation. In an embodiment, the second computation is a depthwise convolution computation and will be detailed in subsequent embodiment. In another embodiment, the second computation may also be a convolution computation or other types of convolution computations. 
     In an embodiment, the second buffer memory  171 , the second FIFO unit  172 , the third weight buffer memory  173 , and the third computing device  175  correspond to one layer of convolutional layer/computing layer. In addition, the third computing device  175  is configured with a third filter used in a third computation. 
     In an embodiment, the second buffer memory  171  is used to store some or all input data output from the second computing device  155 , the second FIFO unit  172  is used to input and/or output data in the second buffer memory  171  according to the FIFO rule, the third weight buffer memory  173  is used to store one or more weights (forming a third convolution kernel/filter) from the memory  110 , and the third computing device  175  is used to perform the third computation. In an embodiment, the third computation is a pointwise convolution computation and will be detailed in subsequent embodiment. In another embodiment, the third computation may also be a convolution computation or other types of convolution computations. 
     In an embodiment, the feature buffer memory  131 , the first buffer memory, the second buffer memory, the first weight buffer memory  133 , the second weight buffer memory  153 , and the third weight buffer memory  173  may be static random access memories (SRAMs), flash memories, registers, various types of buffers, or combinations of the above elements. 
     In an embodiment, some or all elements in the computing circuit  100  may form a neural network processing unit (NPU), a system on chip (SoC), or an integrated circuit (IC). 
     In an embodiment, the first computing device  135  has a first maximum computation amount in a unit time, the second computing device  155  has a second maximum computation amount in the same unit time, and the third computing device  175  has a third maximum computation amount in the same unit time. The first maximum computation amount is greater than the second maximum computation amount, and the first maximum computation amount is greater than the third maximum computation amount. 
     Hereinafter, the method according to the embodiment of the disclosure will be illustrated in conjunction with various devices, elements, and modules in the computing circuit  100 . Each process of the method may be adjusted according to implementation situations and is not limited thereto. 
       FIG. 2  is a flowchart of a data processing method based on a convolutional neural network according to an embodiment of the disclosure. Referring to  FIG. 2 , the processing element  120  reads the input data from the memory  110  (Step S 210 ). Specifically, the input data may be data (for example, color scale, brightness, or gray scale) of some or all pixels in an image. Alternatively, the input data may also be a data collection related to voice, text, patterns, or other aspects. 
     There are many ways to read the input data. In an embodiment, the processing element  120  reads all of the input data to serve as first part data. In another embodiment, the processing element  120  reads a part of the input data each time according to a data amount required for the first computation or the capacity of the feature buffer memory  131  to serve as the first part data. 
       FIG. 3  is a schematic diagram of input data F according to an embodiment of the disclosure. Referring to  FIG. 3 , it is assumed that the size of the input data F is configured with a height H, a width W, and a channel number C, and the size of first part data F fi1  read by the processing element  120  is configured with a height H fi1 , a width W fi1 , and the channel number C. The height H fi1  may be less than or equal to the height H, and the width W fi1  may be less than or equal to the width W. 
     It should be noted that the input data may be stored in a specific block or position in the memory  110 , but the embodiment of the disclosure does not limit the storage position of each element of the input data in the memory  110 . 
     The feature buffer memory  131  stores a part or all of the input data from the memory  110 . That is, the feature buffer memory  131  stores the first part data. The first computing device  135  performs the first computation on the first part data of the input data to obtain first output data (Step S 230 ). Specifically, performing the first computation is to perform the first computation (for example, a convolution computation) on the first part data and a corresponding weight. The size of the first output data is related to the size of the first filter of the first computation and the size of the first part data. 
     For example,  FIG. 4  is a schematic diagram of a first computation according to an embodiment of the disclosure. Referring to  FIG. 4 , the first computation takes a convolution computation as an example. The first part data F fi1  (with the size being configured with the height H fi1 , the width W fi1 , and the channel number C fi1 ) and a first filter K n  (with the size being configured with a height H kd  and a width W kd ). If the height H fi1  is greater than or equal to the height H kd  and the width W fi1  is greater than or equal to the width W kd , the first computing device  135  may trigger the first computation. For a result (that is, first output data F fo1 ) of the first computation, a height H f1o  is the height H fi1 −H kd +1, a width W f1o  is the width W fi1 −W kd +1, and a channel number Cno is the same as the channel number C fi1 . 
     For another example, if the size defined as (height, width, channel number) of the first part data F fi1  is (3, 32, 16), and the size defined as (height, width) of the first filter K n  is (3, 3), the size (height, width, channel number) of the first output data F fo1  is (1, 30, 16). 
     In an embodiment, the first computing device  135  adopts a systolic array structure. The first computing device  135  divides the first part data into multiple first systolic array inputs, and respectively performs the first computation on the first systolic array inputs to obtain multiple first systolic array outputs. The size of each first systolic array output is limited by the size of the systolic array. For example, an element number of the first systolic array output is less than or equal to the capacity of the systolic array. In addition, the first systolic array outputs based on the same first part data form the first output data. 
     For example,  FIG. 5A  and  FIG. 5B  are schematic diagrams of systolic array inputs and outputs according to an embodiment of the disclosure. Referring to  FIG. 5A  and  FIG. 5B , it is assumed that the size of the systolic array is number M sa ×number N sa . A height H a1o  of a systolic array output SA 1o  is 1, a width W a1o  thereof may be the number M sa , and a channel number C a1o  thereof may be the number N sa . Therefore, the first computing device  135  divides the first part data into a systolic array input SA 1i  (with the size being configured with a height H a1i , a width W ali , and a channel number C a1i ) and a systolic array input SA 2i  (with the size being configured with a height H a2i , a width W a2i , and a channel number C a2i ). The two systolic array inputs SA 1i  and SA 2i  are respectively performed with convolution computation with a weight of each channel of the filter K n , so as to obtain the systolic array outputs SA 1o  and SA 2o . A height H a2o  of the systolic array output SA 2o  is 1, a width W a2o  thereof may be less than or equal to the number M sa , and a channel number C a2o  thereof may be less than or equal to the number N sa . 
     For another example, the size defined as (height, width, channel number) of the first part data is (3, 32, 16), the size of the systolic array is 16×16, and the size of the filter  n  is 3×3. The height H a1o  of the systolic array output SA 1o  is 1, the width W a1o  thereof may be 16, and the channel number C a1o  thereof may be 16. In addition, the height H a1i  of the systolic array input SA 1i  is 3, the width W a1i  thereof is 18, and the channel number C a1i  thereof is 16. On the other hand, after the first computing device  135  distinguishes the systolic array input SA 1i  from the first part data, the systolic array input SA 2i  may be obtained. The height H a2i  of the systolic array input SA 2i  is 3, the width W a2i  thereof is 16, and the channel number C a2i  thereof is 16. In addition, the height H a2o  of the systolic array output SA 2o  is 1, the width W a2o  thereof is 14 (that is, the width W a2i -the width of the filter K n +1), and the channel number C a2o  thereof is 16. 
     For another example, Table (1) to Table (3) are first, second, and fifteenth data (the remaining data may be deduced by analogy) of the first part data stored in the feature buffer memory  131 : 
     
       
         
           
               
               
               
               
             
               
                   
                 TABLE 1 
               
               
                   
                   
               
             
            
               
                   
                 I(0, 2, 15) to 
                 I(0, 1, 15) to 
                 I(0, 0, 15) to 
               
               
                   
                 I(0, 2, 0) 
                 I(0, 1, 0) 
                 I(0, 0, 0) 
               
               
                   
                 I(1, 2, 15) to 
                 I(1, 1, 15) to 
                 I(1, 0, 15) to 
               
               
                   
                 I(1, 2, 0) 
                 I(1, 1, 0) 
                 I(1, 0, 0) 
               
               
                   
                 I(2, 2, 15) to 
                 I(2, 1, 15) to 
                 I(2, 0, 15) to 
               
               
                   
                 I(2, 2, 0) 
                 I(2, 1, 0) 
                 I(2, 0, 0) 
               
               
                   
                   
               
            
           
         
       
     
     
       
         
           
               
               
               
               
             
               
                   
                 TABLE 2 
               
               
                   
                   
               
             
            
               
                   
                 I(0, 3, 15) to 
                 I(0, 2, 15) to 
                 I(0, 1, 15) to 
               
               
                   
                 I(0, 2, 0) 
                 I(0, 2, 0) 
                 I(0, 1, 0) 
               
               
                   
                 I(1, 3, 15) to 
                 I(1, 2, 15) to 
                 I(1, 1, 15) to 
               
               
                   
                 I(1, 2, 0) 
                 I(1, 2, 0) 
                 I(1, 1, 0) 
               
               
                   
                 I(2, 3, 15) to 
                 I(2, 2, 15) to 
                 I(2, 1, 15) to 
               
               
                   
                 I(2, 2, 0) 
                 I(2, 2, 0) 
                 I(2, 1, 0) 
               
               
                   
                   
               
            
           
         
       
     
     
       
         
           
               
               
               
               
             
               
                   
                 TABLE 3 
               
               
                   
                   
               
             
            
               
                   
                 I(0, 17, 15) to 
                 I(0, 16, 15) to 
                 I(0, 15, 15) to 
               
               
                   
                 I(0, 17, 0) 
                 I(0, 16, 0) 
                 I(0, 15, 0) 
               
               
                   
                 I(1, 17, 15) to 
                 I(1, 16, 15) to 
                 I(1, 15, 15) to 
               
               
                   
                 I(1, 17, 0) 
                 I(1, 16, 0) 
                 I(1, 15, 0) 
               
               
                   
                 I(2, 17, 15) to 
                 I(2, 16, 15) to 
                 I(2, 15, 15) to 
               
               
                   
                 I(2, 17, 0) 
                 I(2, 16, 0) 
                 I(2, 15, 0) 
               
               
                   
                   
               
            
           
         
       
     
     I(i1,j1,n1) represents values of the input data read at a position (height position i1, width position j1, channel position n1). The first FIFO unit  132  sequentially inputs the data to the first computing device  135  from right to left and from top to bottom of the data. 
     Table (4) is data of a 3×3 filter with 16 channels used in the convolution computation: 
     
       
         
           
               
               
               
               
               
             
               
                 TABLE 4 
               
               
                   
               
               
                 Channel 0 
                 Channel 1 
                 . . . 
                 Channel 14 
                 Channel 15 
               
               
                   
               
             
            
               
                 F d0 (2, 2, 15) 
                 F d1 (2, 2, 15) 
                 . . . 
                 F d14 (2, 2, 15) 
                 F d15 (2, 2, 15) 
               
               
                 . . . 
                 . . . 
                 . . . 
                 . . . 
                 . . . 
               
               
                 F d0 (2, 2, 0) 
                 F d1 (2, 2, 0) 
                 . . . 
                 F d14 (2, 2, 0) 
                 F d15 (2, 2, 0) 
               
               
                 . . . 
                 . . . 
                 . . . 
                 . . . 
                 . . . 
               
               
                 F d0 (0, 0, 0) 
                 F d1 (0, 0, 0) 
                 . . . 
                 F d14 (0, 0, 0) 
                 F d15 (0, 0, 0) 
               
               
                 . . . 
                 . . . 
                 . . . 
                 . . . 
                 . . . 
               
               
                 F d0 (0, 0, 0) 
                 F d1 (2, 2, 15) 
                 . . . 
                 F d14 (2, 2, 15) 
                 F d15 (2, 2, 15) 
               
               
                   
               
            
           
         
       
     
     F dn (i2,j2,n2) represents values of an n-th filter read at a position (height position i2, width position j2, channel position n2). 
     Table (5) is the systolic array output: 
     
       
         
           
               
               
               
               
               
               
             
               
                 TABLE 5 
               
               
                   
               
             
            
               
                   
                 A(0,0,0) 
                 A(0,0,1) 
                 . . .  
                 A(0,0,14) 
                 A(0,0,15) 
               
               
                   
                 A(0,1,0) 
                 A(0,1,1) 
                 . . .  
                 A(0,1,14) 
                 A(0,1,15) 
               
               
                   
                 . . .  
                 . . .  
                 . . .  
                 . . .  
                 . . .  
               
               
                   
                 A(0,15,0) 
                 A(0,15,1) 
                 . . .  
                 A(0,15,14) 
                 A(0,15,15) 
               
               
                   
               
            
           
         
       
     
     A(i3,j3,n3) represents values of the systolic array output at a position (height position i3, width position j3, channel position n3), and the mathematical expression thereof is: 
         A ( i 3, j 3, n 3)= I ( i 3 j 3,0)× F   dn3 (0,0,0)+ I ( i 3 j 3,1)× F   dn3 (0,0,1)+ . . . + I ( i 3, j 3,15)×F dn 3(0,0,15) + I ( i 3, j 3+1,0)× F   dn3 (0,1,0)+ I ( i 3, j 3+1,1)× F   dn3 (0,1,1)+ . . . + I ( i 3, j 3+1,15)× F   dn3 (0,1,15)+ I ( i 3, j 3+2,0)× F   dn3 (0,2,0)+ I ( i 3, j 3+2,1)× F   dn3 (0,2,1)+ . . . + I ( i 3, j  3+2,15)× F   dn3 (0,2,15)+ I ( i 3+1, j 3,0)× F   dn3 (1,0,0)+ I ( i 3+1, j 3,1)× F   dn3 (1,0,1)+ . . . + I ( i 3+1, j 3,15)× F   dn3 (1,0,15)+ I ( i 3+1, j 3+1,0)× F   dn3 (1,1,0)+ I ( i 3+1, j 3+1,1)× F   dn3 (1,1,1)+ . . . + I ( i 3+1, j 3+1,15)× F   dn3 (1,1,15)+ I ( i 3+1, j 3+2,0)× F   dn3 (1,2,0)+ I ( i 3+1, j 3+2,1)× F   dn3 (1,2,1)+ . . . + I ( i 3+1, j 3+2,15)× F   dn3 (1,2,15)+ I ( i 3+2, j 3,0)× F   dn3 (2,0,0)+ I ( i 3+2, j 3,1)× F   dn3 (2,0,1)+ . . . + I ( i 3+2, j 3,15)× F   dn3 (2,0,15)+ I ( i 3+2, j 3+1,0)× F   dn3 (2,1,0)+ I ( i 3+2, j 3+1,1)× F   dn3 (2,1,1)+ . . . + I ( i 3+2, j 3+1,15)× F   dn3 (2,1,15)  I ( i 3+2, j 3+2,0)× F   dn3 (2,2,0)+ I ( i 3+2, j 3+2,1)× F   dn3 (2,2,1)+ . . . + I ( i 3+2, j 3+2,15)× F   dn3 (2,2,15)  (1).
 
       FIG. 6A  is a schematic diagram of a systolic array output SA 3o  according to an embodiment of the disclosure. Referring to  FIG. 6A , a height H a3o  of the systolic array output SA 3o  is 1, a width W a3o  thereof is 16, and a channel number C a3o  thereof is 16. In Mathematical Expression (1), i3∈0 represents the height, j3∈0 to 15 represents the width, and n3∈0 to 15 represents a filter output channel. 
       FIG. 6B  is a schematic diagram of a systolic array output SA 4o  according to an embodiment of the disclosure. Referring to  FIG. 6B , the height H a3o  of the systolic array output SA 4o  is 1, a width W a4o  thereof is 14, and the channel number C a3o  thereof is 16. In Mathematical Expression (1), i3∈0 represents the height, j3∈16 to 29 represents the width, and n3∈0 to 15 represents the filter output channel. In addition, a completed output  601  is the systolic array output SA 3o  of  FIG. 6A , and a currently processed output  602  is the systolic array output SA 4o . 
     By analogy,  FIG. 6C  is a schematic diagram of a systolic array output SA 4o  according to an embodiment of the disclosure. Referring to  FIG. 6C , the height H a3o  of the systolic array output SA 5o  is 1, a width W a5o  thereof is 14, and the channel number C a3o  thereof is 16. In 
     Mathematical Expression (1), i3∈4 represents the height, j3∈16 to 29 represents the width, and n3∈0 to 15 represents the filter output channel. In addition, the currently processed output  602  is the systolic array output SA 5o . The systolic array outputs SA 3o  to SA 5o  may form one or more first output data. 
     In an embodiment, the first computation is a convolution computation, and the first computing device  135  reads the first part data of the input data stored in the memory  110  toward a first sliding direction. The first computing device  135  divides the input data into multiple sections, and continues to read a next section in the first sliding direction parallel to the height of the input data, so as to serve as the first part data. 
     For example,  FIG. 7A  is a schematic diagram of reading first part data F i1  and F fi2  according to an embodiment of the disclosure. Referring to  FIG. 7A , if the first computation of the first part data F fi1  has been completed, the first computing device  135  will regard the first part data F fi1  as a completed input  701 , and further read the first part data F fi2 of the next section of the input data F toward a direction D 1  (for example, the bottom of the drawing) to serve as a currently processed input  702 . 
       FIG. 7B  is a schematic diagram of first output data F fo1  and F fo2  according to an embodiment of the disclosure. Referring to  FIG. 7B , the first output data F fo1  is the output of performing the convolution computation on the first part data F fi1  of  FIG. 7A  and serves as a completed output  703 . In addition, the first output data F fo2  is the output of performing the convolution computation on the first part data F fi2  of  FIG. 7A  and serves as a currently processed output  704 . The first output data F fo2  is also arranged at the bottom of the first output data F fo1  according to the direction D 1  of  FIG. 7A . 
       FIG. 7C  is a schematic diagram of reading input data F fi3  according to an embodiment of the disclosure. Referring to  FIG. 7C , if the completed input  701  has reached the bottom of the input data F, the first computing device  135  reads the first part data F fi3  of the next section of the input data F toward a direction D 2  (for example, the right side of the drawing) and from top to bottom (corresponding to the direction D 1  of  FIG. 7A ) to serve as the currently processed input  702 . 
       FIG. 7D  is a schematic diagram of first output data F fo3  according to an embodiment of the disclosure. Referring to  FIG. 7D , the first output data F fo3  is the output of performing the convolution computation on the first part data F fi3  of  FIG. 7C  and serves as the currently processed output  704 . Similarly, the currently processed output  704  is arranged at the right side of the completed output  703 . 
       FIG. 7E  is a schematic diagram of reading input data F fi4  according to an embodiment of the disclosure. Referring to  FIG. 7E , the first part data F fi4  of the currently processed input  702  is the last section of the input data. 
       FIG. 7F  is a schematic diagram of first output data F fo4  according to an embodiment of the disclosure. Referring to  FIG. 7F , the first output data F fo4  is the output of performing the convolution computation on the first part data F fi4  of  FIG. 7E  and serves as the currently processed output  704 . Similarly, the currently processed output  704  is arranged at the bottom of the completed output  703 , so as to complete the convolution computation of the input data F. 
     In another embodiment, the first computing device  135  reads the first part data of the input data stored in the memory  110  toward a second sliding direction (different from the first sliding direction). Similarly, the first computing device  135  divides the input data into multiple sections, and continues to read the next section in the second sliding direction parallel to the width of the input data, so as to serve as the first part data. 
     For example,  FIG. 8  is a schematic diagram of reading input data according to an embodiment of the disclosure. Referring to  FIG. 8 , if the first computation of the first part data Ffii has been completed, the first computing device  135  will regard the first part data F fi1  as the completed input  701 , and further read first part data F fi6  of the next section of the input data F toward the direction D 2  (for example, the right side of the drawing) to serve as the currently processed input  702 . Similarly, if the last section of the same row has been read toward the direction D 2 , the first computing device  135  will read the section at the bottom of the first part data F fi1 . In addition, for the arrangement of the first part data F fi1  and other first part data (not shown), reference may be made to the above description and will not be repeated here. 
     Referring to  FIG. 2 , the first computing device  135  buffers one or more first output data to the first buffer of the first buffer memory  151  (Step S 250 ). Specifically, different from the prior art that outputs the first output data to the memory  110 , the first output data of the embodiment of the disclosure outputs the first output data to the first buffer memory  151  of the second computing device  155 , thereby reducing the number of accesses of the memory  110 . 
     When the first output data buffered in the first buffer memory  151  (or the first buffer) is greater than the first predetermined data amount, the second computing device  155  performs the second computation on the first output data to obtain the second output data (Step S 270 ). Specifically, in the existing multi-convolutional layer architecture, a next convolutional layer needs to wait until a previous convolutional layer computes all input data thereof and outputs the input data to a main memory before reading the input data output by the previous convolutional layer from the main memory. Different from the prior art, in addition to buffering to a storage medium (for example, the first buffer memory  151  or the second buffer memory  171 ) other than the memory  110 , the embodiment of the disclosure may further trigger the convolution computation of the next convolutional layer whenever the size (that is, the first predetermined data amount) of the input data required by the next convolutional layer is satisfied. At the same time, if the computation of all the input data by the previous convolutional layer has not been completed, the computations of the two convolutional layers may be performed at the same time. In other words, when the second computing device  155  performs the second computation on the first output data, the first computing device  135  continuously performs the first computation on the input data. 
     It is worth noting that second part data input by the second computation includes the first output data buffered in the first buffer memory  151 , and the size of the second output data is related to the size of the second filter of the second computation. It is assumed that the second computation is a depthwise convolution computation. Each filter of the depthwise convolution computation only corresponds to data of one channel in the second part data. That is, any filter of the depthwise convolution computation only performs the convolution computation on the data of one channel. Therefore, the number of filters of the depthwise convolution computation is usually equal to a channel number of the second part data. However, each filter of the convolution computation performs the convolution computation on the data of all channels. In addition, as long as the height of the buffered first output data increases to the height of the filter and the width of the first output data increases to the width of the filter, the filter may perform the depthwise convolution computation on the buffered first output data (to serve as the second part data). 
     In an embodiment, it is assumed that the height of each filter used in the depthwise convolution computation is H kd , and the width of the filter is W kd . The height of the first output data of each section is H f1o , and the width of the first output data is W f1o . When the first output data buffered in the first buffer memory  151  or the first buffer is greater than W kd ×H kd , the second computing device  155  may perform the second computation. When the first output data buffered in the first buffer memory  151  or the first buffer is greater than the first predetermined data amount, the height formed by the first output data buffered in the first buffer memory  151  or the first buffer is M H ×H f1o  and the width formed is M W ×W f1o . M H  and M W  are multiples and positive integers, M H ×H f1o  is not less than H kd , and M W ×W f1o  is not less than W kd . In other words, when the height M H ×H f1o  of the buffered first output data is less than the height H kd  of the filter and the width M w ×W f1o  of the buffered first output data is less than the width W kd  of the filter, the second computing device  155  will continue to wait for a next first output data or systolic array output until the height M H ×H f1o  of the buffered first output data is greater than or equal to the height H kd  of the filter and the width M w ×W f1o  of the buffered first output data is greater than or equal to the width W kd  of the filter. 
     For example,  FIG. 9A  is a schematic diagram of a trigger condition of a second computation according to an embodiment of the disclosure, and  FIG. 9B  is a schematic diagram of buffered first output data according to an embodiment of the disclosure. Referring to  FIG. 9A , a completed input  901  of the input data corresponds to a completed output  903  of the first output data. If the sizes of a currently processed output  904  corresponding to a currently processed input  902  and the completed output  903  meet the size required by the second computation, the second computation may be triggered. 
     Referring to  FIG. 9B , it is assumed that the completed output  903  and the currently processed output  904  of  FIG. 9A  form buffered first output data F tfo . The size of the systolic array used by the first computing device  135  is 16×16, where a width W tfo1  of the systolic array output may be 16 or a width W tfo2  may be  14 . It is assumed that the height of each filter used in the depthwise convolution computation is 3, and the width of the filter is 3. The widths W tfo1  and W tfo2  are both greater than 3. If a fifth systolic array output is buffered in the first buffer memory  151 , the size (height, width, channel number) of the first to fifth systolic array output is (1, 16, 16) or (1, 14, 16), that is, the size formed by the output with a channel number C tfo  of 16 has satisfied the size of 3×3. That is, the systolic array output with a height of 1 is stacked into three layers, so that the height after stacking is 3. At this time, the systolic array outputs may be used as the second part data and may be used for the second computation. 
     It should be noted that in  FIG. 9A  and  FIG. 9B , as long as the number of stacked layers is equal to the height of the filter, the second computation is triggered. However, in other embodiments, the number of stacked layers may be greater than the height of the filter. 
     For the depthwise convolution computation,  FIG. 10A  is a schematic diagram of a second computation according to an embodiment of the disclosure. Referring to  FIG. 10A , it is assumed that the size (height, width, channel number) of second part data F si1  is (5, 30, 16), and the size of a filter F d  used in the depthwise convolution computation is 3×3. I(i4,j4,n4) represents values of the second part data at a position (height position i4, width position j4, channel position n4). F dn4 (i5,j5,n5) represents values of an n4-th filter read at a position (height position i5, width position j5). A(i4,j4,n4) represents values of the second output data or the systolic array output at a position defined as (height position i4, width position j4, channel position n4), and the mathematical expression thereof is: 
         A ( i 4, j 4, n 4)= I ( i 4, j 4, n 4)× F   dn4 (0,0)+ I ( i 4, j 4+1, n 4)× F   dn4 (0,1)+ I ( i 4, j 4+2, n 4)× F   dn4 (0,2)+ I ( i 4+1, j 4, n 4)× F   dn4 (1,0)+ I ( i 4+1, j 4+1, n 4)× F   dn4 (1,1)+ I ( i 4+1, j 4+2, n 4)× F   dn4 (1,2) + I ( i 4+2, j 4, n )× F   dn4 (2,0)+ I (i4+2,j4+1,n4)×F dn4 (2,1)+ I ( i 4+2, j 4+2, n 4)× F   dn4 (2,2)  (2).
 
       FIG. 10B  is a schematic diagram of second output data F so1  according to an embodiment of the disclosure. Referring to  FIG. 10B , it is assumed that the size (configured with height H so1 , width W so1 , and channel number C so1 ) of the currently processed second output data F so1  is (1,28, 16). Each value in the second output data F so1  is: 
         A (0,0, n 4)= I (0,0, n 4)× F   dn4 (0,0)+ I (0,1, n 4)× F   dn4 (0,1)+ I (0,2, n 4)× F   dn4 (0,2)+ I (1,0, n 4)× F   dn4 (1,0)+ I (1,1, n 4)× F   dn4 (1,1)+ I (1,2, n 4)× F   dn4 (1,2)+ I (2,0, n )&#39; F   dn4 (2,0)+I(2,1, n 4)× F   dn4 (2, 1 )+ I (2,2, n 4)× F   dn4 (2,2)  (3)
 
         A (0,1, n 4)= I (0,1, n 4)× F   dn4 (0,0)+ I (0,2,n4)× F   dn4 (0,1)+ I (0,3, n 4)×F dn4 (0,2)+ I (1,1, n 4)× F   dn4 (1,0)+I(1,2, n 4)× F   dn4 (1,1)+ I (1,3, n 4)× F   dn4 (1,2)+ I (2,1, n )× F   dn4 (2,0)+ I (2,2, n 4)× F   dn4 (2,1)+ I (2,3, n 4)× F   dn4 (2,2)  (4)
 
         A (0,27, n 4)= I (0,27, n 4)×F dn4 (0,0)+ I (0,28, n 4)× F   dn4 (0,1)+ I (0,29, n 4)× F   dn4 (0,2)+ I (1,27, n 4)× F   dn4 (1,0)+ I (1,28, n 4)× F   dn4 (1,1)+ I (1,29, n 4)× F   dn4 (1,2)+ I (2,27, n )× F   dn4 (2,0)+ I (2,28,n4)× F   dn4 (2,1)+ I (2,29, n 4)× F   dn4 (2,2)  (5)
 
     and the rest may be deduced by analogy, so there will be no repetition. 
       FIG. 10C  is a schematic diagram of second output data F so2  according to an embodiment of the disclosure. Referring to  FIG. 10C , a completed output  101  is the second output data F so1  of  FIG. 10B . The second output data F so2  is a currently processed output  102 , and the size thereof may be the same as the second output data F so1  of  FIG. 10B . Each value in the second output data F so2  is: 
         A (1,0, n 4)= I (1,0, n 4)× F   dn4 (0,0)+ I (1,1, n 4)× F   dn4 (0,1)+ I (1,2, n 4)× F   dn4 (0,2)++ I (2,0, n 4)× F   dn4 (1,0)+ I (2,1, n 4)× F   dn4 (1,1)+ I (2,2, n 4)× F   dn4 (1,2)+ I (3,0, n )× F   dn4 (2,0)+ I (3,1, n 4)× F   dn4 (2,1)+ I (3,2, n 4)× F   dn4 (2,2)  (6)
 
         A ( 1,1, n 4)= I (1,1, n 4)× F   dn4 (0,0)+ I (1,2, n 4)× F   dn4 (0,1)+ I (1,3, n 4)× F   dn4 (0,2)+ I (2,1, n 4)× F   dn4 (1,0)+ I (2,2, n 4)× F   dn4 (1,1)+ I (2,3, n 4)× F   dn4 (1,2)+ I (3,1, n )× F   dn4 (2,0)+ I (3,2, n 4)× F   dn4 (2,1)+ I (3,3, n 4)× F   dn4 (2,2)  (7)
 
         A (1,27, n 4)= I (1,27, n 4)× F   dn4 (0,0)+ I (1,28, n 4)× F   dn4 (0,1)+ I (1,29, n 4)× F   dn4 (0,2)+ I (2,27, n 4)× F   dn4 (1,0)+ I (2,28, n 4)× F   dn4 (1,1)+ I (2,29, n 4)× F   dn4 (1,2) + I (3,27, n )× F   dn4 (2,0)+ I (3,28, n 4)× F   dn4 (2,1)+ I (3,29, n 4)× F   dn4 (2,2)  (8)
 
     and the rest may be deduced by analogy, so there will be no repetition. 
       FIG. 10D  is a schematic diagram of second output data F so3  according to an embodiment of the disclosure. Referring to  FIG. 10D , the second output data F so3  is a currently processed output  102 , and the size thereof may be the same as the second output data F so1  of  FIG. 10B . Each value in the second output data F so3  is: 
         A (2,0, n 4)= I (2,0, n 4)× F   dn4 (0,0)+ I (2,1, n 4)× F   dn4 (0,1)+ I (2,2, n 4)× F   dn4 (0,2)+ I (3,0, n 4)× F   dn4 (1,0)+ I (3,1, n 4)× F   dn4 (1,1)+ I (3,2, n 4)× F   dn4 (1,2)+ I (4,0, n )× F   dn4 (2,0)+ I (4,1, n 4)× F   dn4 (2,1)+ I (4,2, n 4)× F   dn4 (2,2)  (9)
 
         A (2,1, n 4)= I (2,1, n 4)× F   dn4 (0,0)+ I (2,2, n 4)× F   dn4 (0,1)+ I (2,3, n 4)× F   dn4 (0,2)+ I (3,1, n 4)× F   dn4 (1,0)+ I (3,2, n 4)× F   dn4 (1,1)+ I (3,3, n 4)× F   dn4 (1,2)+ I (4,1, n )× F   dn4 (2,0)+ I (4,2, n 4)× F   dn4 (2,1)+ I (4,3, n 4)× F   dn4 (2,2)  (10)
 
         A (2,27, n 4)= I (2,27, n 4)× F   dn4 (0,0)+ I (2,28, n 4)× F   dn4 (0,1)+ I (2,29, n 4)× F   dn4 (0,2)+ I (3,27, n 4)× F   dn4 (1,0)+ I (3,28, n 4)× F   dn4 (1,1)+ I (3,29, n 4)× F   dn4 (1,2)+ I (4,27, n )× F   dn4 (2,0)+ I (4,28, n 4)× F   dn4 (2,1)+ I (4,29, n 4)× F   dn4 (2,2)  (11)
 
     and the rest may be deduced by analogy, so there will be no repetition. 
     In an embodiment, the second computing device  155  adopts a systolic array structure. The second computing device  155  divides the second part data (that is, a part of the buffered first output data) into multiple second systolic array inputs, and respectively performs the second computation on the second systolic array inputs to obtain multiple second systolic array outputs. The size of each second systolic array output is limited by the size of the systolic array. For example, an element number of the second systolic array output is less than or equal to the capacity of the systolic array. In addition, the second systolic array outputs based on the same second part data form the second output data. Taking  FIG. 10B  as an example, if the size of the systolic array is 16×16, the second output data F so1  includes 1×16×16 and 1×12×16 second systolic array outputs. 
     For the next convolutional layer,  FIG. 11  is a flowchart of a data processing method based on a convolutional neural network according to an embodiment of the disclosure. Referring to  FIG. 11 , in an embodiment, the second computing device  155  may buffer one or more second output data in a second buffer of the second buffer memory  171  (Step S 111 ) (Step S 280 ). Specifically, similarly, in the embodiment of the disclosure, the output of the previous convolutional layer is buffered in the buffer of the next convolutional layer, instead of directly outputting the output data to the memory  110 . 
     When the second output data buffered in the second buffer memory  171  or the second buffer is greater than a second predetermined data amount, the third computing device  175  may perform the third computation on the second output data to obtain third output data (Step S 113 ). Specifically, third part data input by the third computation includes the second output data buffered in the second buffer memory  171 , and the size of the third part data is related to the size of the filter of the third computation. It is assumed that the third computation is the pointwise convolution computation. The size of each filter of the pointwise convolution computation is only 1×1. Similar to the convolution computation, each filter of the pointwise convolution computation also performs the convolution computation on the data of all channels. In addition, as long as the height of the buffered second output data increases to the height (which is 1) of the filter and the width of the second output data increases to the width (which is 1) of the filter, the filter may perform the pointwise convolution computation on the buffered second output data (to serve as the third part data). 
     In an embodiment, as shown in  FIG. 10B  to  FIG. 10D , each second output data may satisfy the size required by the pointwise convolution computation. Therefore, the second FIFO unit  172  may sequentially input each second output data to the third computing device  175 . The third computing device  175  may perform the third computation on each buffered second output data. 
     For example,  FIG. 12A  is a schematic diagram of buffered first output data F tfo  according to an embodiment of the disclosure, and  FIG. 12B  is a schematic diagram of buffered second output data F tso  according to an embodiment of the disclosure. Referring to  FIG. 12A  and  FIG. 12B , if the second computing device  155  has completed the convolution computation on a part of the buffered first output data, the first buffer memory  151  may buffer the second systolic array output with the size (height, width, channel number) configured as (1, W so21 , C so2 ) or the second output data with the size configured as (1, W so 21 +W so21 , C so2 ), so as to become the buffered second output data F tso . The channel number C so2  is the same as a channel number C. 
       FIG. 13A  is a schematic diagram of a third computation according to an embodiment of the disclosure. Referring to  FIG. 13A , the third computing device  175  uses the buffered second output data F tso  of  FIG. 12B  as third part data F ti  (with a width W so3  thereof being W so21 +W so21 ), and performs the third computation on the third part data F ti  and a filter F p  used by the pointwise convolution computation. 
       FIG. 13B  is a schematic diagram of third output data F to  according to an embodiment of the disclosure. Referring to  FIG. 13A  and  FIG. 13B , the size of the third output data F to  is equal to the third part data F ti . That is, a width W to1  is the same as the width W so3 , and a channel number C to1  is the same as the channel number C so2 . 
     In an embodiment, the third computing device  175  adopts a systolic array structure. The third computing device  175  divides the third part data into multiple third systolic array inputs, and respectively performs the third computation on the third systolic array inputs to obtain multiple third systolic array outputs. The size of each third systolic array output is limited by the size of the systolic array. For example, an element number output by the third systolic array is less than or equal to the capacity of the systolic array. In addition, the third systolic array outputs based on the same third part data (that is, a part of the buffered second output data) form the third output data. For example, if the size of the third part data is 1×28×16 and the size of the systolic array is 16×16, the third output data includes 1×16×16 and 1×12×16 third systolic array outputs. 
     For example,  FIG. 14A  is a schematic diagram of a systolic array output SA 6o  according to an embodiment of the disclosure. Referring to  FIG. 14A , table (6) is the data of the second output data stored in the second buffer memory  171 : 
     
       
         
           
               
               
               
               
               
               
             
               
                   
                 TABLE 6 
               
               
                   
                   
               
             
            
               
                   
                 I(0, 0, 15) 
                 I(0, 0, 14) 
                 . . . 
                 I(0, 0, 1) 
                 I(0, 0, 0) 
               
               
                   
                 I(0, 1, 15) 
                 I(0, 1, 14) 
                 . . . 
                 I(0, 1, 1) 
                 I(0, 1, 0) 
               
               
                   
                 . . . 
                 . . . 
                 . . . 
                 . . . 
                 . . . 
               
               
                   
                 I(0, 15, 15) 
                 I(0, 15, 14) 
                 . . . 
                 I(0, 15, 1) 
                 I(0, 15, 0) 
               
               
                   
                   
               
            
           
         
       
     
     I(i6,j6,n6) represents values of the input data read at a position (height position i6, width position j6, channel position n6). The second FIFO unit  172  sequentially inputs the data to the third computing device  175  from right to left and from top to bottom. 
     Table (7) is data of a 1×1 filter with 16 channels used in the pointwise convolution computation: 
     
       
         
           
               
               
               
               
               
             
               
                 TABLE 7 
               
               
                   
               
               
                 Channel 0 
                 Channel 1 
                 . . . 
                 Channel 14 
                 Channel 15 
               
               
                   
               
             
            
               
                 F p0 (0, 0, 15) 
                 F p1 (0, 0, 15) 
                 . . . 
                 F P14 (0, 0, 15) 
                 F p15 (0, 0, 15) 
               
               
                 . . . 
                 . . . 
                 . . . 
                 . . . 
                 . . . 
               
               
                 F p0 (0, 0, 1) 
                 F p1 (0, 0, 1) 
                 . . . 
                 F p14 (0, 0, 1) 
                 F p15 (0, 0, 1) 
               
               
                 F p0 (0, 0, 0) 
                 F p1 (0, 0, 0) 
                 . . . 
                 F p14 (0, 0, 0) 
                 F p15 (0, 0, 0) 
               
               
                   
               
            
           
         
       
     
     F dn (i7,j7,n7) represents values of the n-th filter read at a position defined as (height position i7, width position j7, channel position n7). 
     Table (8) shows the systolic array output: 
     
       
         
           
               
               
               
               
               
             
               
                 TABLE 8 
               
               
                   
               
             
            
               
                 A(0, 0, 0) 
                 A(0, 0, 1) 
                 . . . 
                 A(0, 0, 14) 
                 A(0, 0, 15) 
               
               
                 A(0, 1, 0) 
                 A(0, 1, 1) 
                 . . . 
                 A(0, 1, 14) 
                 A(0, 1, 15) 
               
               
                 . . . 
                 . . . 
                 . . . 
                 . . . 
                 . . . 
               
               
                 A(0, 15, 0) 
                 A(0, 15, 1) 
                 . . . 
                 A(0, 15, 14) 
                 A(0, 15, 15) 
               
               
                   
               
            
           
         
       
     
     A(i6,j6,n6) represents values of the systolic array output at a position defined as (height position i6, width position j6, channel position n6), and the mathematical expression thereof is: 
         A ( i 6, j 3, n 6)= I ( i 6, j 6,0)× F   dn6 (0,0,0)+ I ( i 6, j 6,1)× F   dn6 (0,0,1)+ . . . + I ( i 6, j 6,15)× F   dn6 (0,0,15)  (12).
 
     Therefore, each value of the systolic array output SA 6o  is (n6∈0 to 15): 
         A (0,0, n 6)= I (0,0,0)× F   dn6 (0,0,0)+ I (0,0,1)× F   dn6 (0,0,1)+ . . . + I (0,0,15)× F   dn6 (0,0,15)  (13);
 
         A (0,1, n 6)= I (0,1,0)× F   dn6 (0,0,0)+ I (0,1,1)× F   dn6 (0,0,1)+ . . . + I (0,1,15)× F   dn6 (0,0,15)  (14).
 
         A (0,15, n 6)= I (0,15,0)× F   dn6 (0,0,0)+ I (0,15,1)× F   dn6 (0,0,1)+ . . . + I (0,15,15)× F   dn6 (0,0,15)  (15),
 
     and the rest may be deduced by analogy, so there will be no repetition. 
     For another example,  FIG. 14B  is a schematic diagram of a systolic array output SA 7o  according to an embodiment of the disclosure. Referring to  FIG. 14A , table (9) is data of the second output data stored in the second buffer memory  171 : 
     
       
         
           
               
               
               
               
               
               
             
               
                   
                 TABLE 9 
               
               
                   
                   
               
             
            
               
                   
                 I(0, 16, 15) 
                 I(0, 16, 14) 
                 . . . 
                 I(0, 16, 1) 
                 I(0, 17, 0) 
               
               
                   
                 I(0, 17, 15) 
                 I(0, 17, 14) 
                 . . . 
                 I(0, 17, 1) 
                 I(0, 17, 0) 
               
               
                   
                 . . . 
                 . . . 
                 . . . 
                 . . . 
                 . . . 
               
               
                   
                 I(0, 27, 15) 
                 I(0, 27, 14) 
                 . . . 
                 I(0, 27, 1) 
                 I(0, 27, 0) 
               
               
                   
                   
               
            
           
         
       
     
     Table (10) shows the systolic array output: 
     
       
         
           
               
               
               
               
               
             
               
                 TABLE 10 
               
               
                   
               
             
            
               
                 A(0, 16, 0) 
                 A(0, 16, 1) 
                 . . . 
                 A(0, 16, 14) 
                 A(0, 16, 15) 
               
               
                 A(0, 17, 0) 
                 A(0, 17, 1) 
                 . . . 
                 A(0, 17, 14) 
                 A(0, 17, 15) 
               
               
                 . . . 
                 . . . 
                 . . . 
                 . . . 
                 . . . 
               
               
                 A(0, 27, 0) 
                 A(0, 27, 1) 
                 . . . 
                 A(0, 27, 14) 
                 A(0, 27, 15) 
               
               
                   
               
            
           
         
       
     
     Therefore, each value of the systolic array output SA 7o  is (n6∈0 to 15): 
         A (0,16, n 6)= I (0,16,0)× F   dn6 (0,0,0)+ I (0,16,1)× F   dn6 (0,0,1)+ . . . + I (0,16,15)× F   dn6 (0,0,15)  (16);
 
         A (0,17, n 6)= I (0,17,0)× F   dn6 (0,0,0)+ I (0,17,1)× F   dn6 (0,0,1)+ . . . + I (0,17,15)× F   dn6 (0,0,15)  (17).
 
         A (0,27, n 6)= I (0,27,0)× F   dn6 (0,0,0)+ I (0,27,1)× F   dn6 (0,0,1)+ . . . + I (0,27,15)× F   dn6 (0,0,15)  (18),
 
     and the rest may be deduced by analogy, so there will be no repetition. In addition, the systolic array output SA 6o  of  FIG. 14A  is a completed output  141 , and the systolic array output SA 7o  is a currently processed output  142 . 
     For another example,  FIG. 14C  is a schematic diagram of a systolic array output SA 8o  according to an embodiment of the disclosure. Referring to  FIG. 14A , table (11) is data of the second output data stored in the second buffer memory  171 : 
     
       
         
           
               
               
               
               
               
               
             
               
                   
                 TABLE 11 
               
               
                   
                   
               
             
            
               
                   
                 I(2, 16, 15) 
                 I(2, 16, 14) 
                 . . . 
                 I(2, 16, 1) 
                 I(2, 17, 0) 
               
               
                   
                 I(2, 17, 15) 
                 I(2, 17, 14) 
                 . . . 
                 I(2, 17, 1) 
                 I(2, 17, 0) 
               
               
                   
                 . . . 
                 . . . 
                 . . . 
                 . . . 
                 . . . 
               
               
                   
                 I(2, 27, 15) 
                 I(2, 27, 14) 
                 . . . 
                 I(2, 27, 1) 
                 I(2, 27, 0) 
               
               
                   
                   
               
            
           
         
       
     
     Table (12) shows the systolic array output: 
     
       
         
           
               
               
               
               
               
             
               
                 TABLE 12 
               
               
                   
               
             
            
               
                 A(2, 16, 0) 
                 A(2, 16, 1) 
                 . . . 
                 A(2, 16, 14) 
                 A(2, 16, 15) 
               
               
                 A(2, 17, 0) 
                 A(2, 17, 1) 
                 . . . 
                 A(2, 17, 14) 
                 A(2, 17, 15) 
               
               
                 . . . 
                 . . . 
                 . . . 
                 . . . 
                 . . . 
               
               
                 A(2, 27, 0) 
                 A(2, 27, 1) 
                 . . . 
                 A(2, 27, 14) 
                 A(2, 27, 15) 
               
               
                   
               
            
           
         
       
     
     Therefore, each value of the systolic array output SA 8o  of the last currently processed output  142  is (n6∈0 to 15): 
         A (2,16, n 6)= I (2,16,0)× F   dn6 (0,0,0)+ I (2,16,1)× F   dn6 (0,0,1)+ . . . + I (2,16,15)× F   dn6 (0,0,15)  (19);
 
         A (2,17, n 6)= I (2,17,0)× F   dn6 (0,0,0)+ I (2,17,1)× F   d6 (0,0,1)+ . . . + I (2,17,15)× F   dn6 (0,0,15)  (20).
 
         A (2,27, n 6)= I (2,27,0)× F   dn6 (0,0,0)+ I (2,27,1)× F   dn6 (0,0,1)+ . . . + I (2,27,15)× F   dn6 (0,0,15)  (21),
 
     and the rest may be deduced by analogy, so there will be no repetition. 
     In an embodiment, when the third computing device  175  is running the third computation, the first computing device  135  and the second computing device  155  continuously respectively run the first computation and the second compution. In other words, if the first computing device  135  and the second computing device  155  have not completed the computation of all the input data, the computation by the first computing device  135 , the second computing device  155 , and the third computing device  175  may be performed together. 
     Referring to  FIG. 2 , lastly, the third computing device  175  outputs the third output data obtained by the third computation to the memory  110  (Step S 290 ). 
     In order to facilitate the understanding of the complete process, another embodiment is described below.  FIG. 15  is a flowchart of a data processing method with the MobileNet architecture according to an embodiment of the disclosure. Referring to  FIG. 15 , the first computing device  135  reads data with defined width of sections from the input data in the memory  110  to serve as the first part data (Step S 1501 ). The first computing device  135  judges whether a number of currently processed lines is greater than or equal to a number which is the size of the first filter-1 and whether a remainder obtained by dividing the number of lines by a first stride used in the first computation is 1 (Step S 1503 ). If the condition of Step S 1503  is met, the first FIFO unit  132  sequentially outputs the first part data to the first computing device  135  (Step S 1505 ). The first computing device  135  reads a weight of the first filter used in the convolution computation from the memory  110  (Step S 1511 ), performs the convolution computation (Step S 1513 ), and outputs the obtained first output data to the first buffer memory  151  (Step S 1515 ). The first computing device  135  judges whether the convolution computation has been performed on all data of a current line (whose size is the same as the size of the filter) in a current section (Step S 1517 ). If the convolution computation of the data has not been completed, the first FIFO unit  132  continues to output the first part data to the first computing device  135  (Step S 1505 ). If the convolution computation has been performed on all the data in the line, the first computing device  135  judges whether the convolution computation has been performed on all data of all lines in the current section (Step S 1518 ). If the convolution computation of the data of one or more lines in the current section has not been completed or the condition of Step S 1503  is met, the first computing device  135  continues to process data of a next line from the input data in the memory  110  (Step S 1507 ). If the convolution computation has been performed on all the data of each line in the current section, the first computing device  135  judges whether the convolution computation has been performed on all the data of all sections (Step S 1519 ). If there is still a section that the convolution computation of the data has not been completed, the first computing device  135  continues to process the data of the next section (Step S 1509 ). In addition, the first computing device  135  resets the number of currently processed lines to zero, and sets the currently processed width to: an original width+the width of the section-(first stride used in the first computation-1+a second stride used in the second computation-1). If the convolution computation has been performed on all the data of all the sections, the first computing device  135  completes all the convolution computation on the input data (Step S 1520 ). 
     The second computing device  155  judges whether the first output data buffered in the first buffer memory  151  is greater than the first predetermined data amount (Step S 1521 ). Taking the size of the second filter as 3×3 as an example, the second computing device  155  judges whether there are three lines of the buffered first output data. The second computing device  155  judges whether a remainder obtained by dividing the number of lines processed in the first computation by the second stride used in the second computation is equal to zero (Step S 1523 ). If the remainder is zero, the second computing device  155  reads the buffered first output data to serve as the second part data (Step S 1525 ). 
     If Step S 1521  and Step S 1523  do not meet the condition, the second computing device  155  judges whether the currently processed data is the first data of the first part data (Step S 1531 ). If the condition is not met in Step S 1531 , all the second computation is ended (Step S 1540 ). On the other hand, the second computing device  155  reads a weight of the second filter used in the depthwise convolution computation from the memory  110  (Step S 1533 ), performs the depthwise convolution computation (Step S 1535 ), and outputs the obtained second output data to the second buffer memory  171  (Step S 1537 ). The second computing device  155  judges whether the depthwise convolution computation has been performed on all data of all lines in a current section (Step S 1538 ). If the convolution computation of the data of one or more lines in the current section has not been completed, the second computing device  155  shifts to a next point index (for example, the second stride apart) (Step S 1527 ) and processes next data until the depthwise convolution computation has been performed on all the data of all the lines in the first buffer memory  151 , and the second computing device  155  sets the number of currently processed lines to: an original number of lines+1, and resets a currently processed width to zero (Step S 1539 ). Then, the second computing device  155  completes all the depthwise convolution computation on the second input data (Step S 1540 ). 
     The third computing device  175  judges whether the second output data buffered in the second buffer memory  171  has reached one line of the second output data (Step S 1541 ). The third computing device  175  reads the buffered second output data to serve as the third part data (Step S 1543 ). The third computing device  175  reads a weight of the third filter used in the pointwise convolution computation (Step S 1551 ) from the memory  110 , performs the pointwise convolution computation (Step S 1553 ), and outputs the obtained third output data to the memory  110  (Step S 1555 ). The third computing device  175  judges whether the pointwise convolution computation has been performed on all data of all lines in the second buffer memory  171 . If the pointwise convolution computation of the data has not been completed, the second FIFO unit  172  continues to output the third part data to the third computing device  175 . If the pointwise convolution computation of all the data of all the lines in the second buffer memory  171  has been completed, the third computing device  175  completes all the pointwise convolution computation on the third part data (Step S 1560 ). 
     The embodiment of the disclosure further provides a non-transitory computer readable storage medium (for example, a storage medium such as a hard disk, an optical disk, a flash memory, and a solid state disk (SSD)), which is used to store a program code. The computing circuit  100  or other processors may load the program code, so as to execute corresponding processes of one or more data processing methods according to the embodiments of the disclosure. Reference may be made to the above description for the processes and will not be repeated here. 
     In summary, in the computing circuit and the data processing method based on the convolutional neural network and the computer readable storage medium of the embodiments of the disclosure, the first output data and/or the second output data are buffered without being output to the memory, and when the buffered data meets the size required for the second computation and/or the third computation, the second computation and/or the third computation may be started. In this way, the number of accesses of the memory can be reduced, and the computing efficiency can be improved. 
     Although the disclosure has been disclosed in the above embodiments, the embodiments are not intended to limit the disclosure. Persons skilled in the art may make some changes and modifications without departing from the spirit and scope of the disclosure. The protection scope of the disclosure shall be defined by the appended claims.