Patent Publication Number: US-7595678-B2

Title: Switched-capacitor circuit

Description:
RELATED APPLICATION 
   The present application claims priority under 35 U.S.C. § 119(e)(1) to provisional application No. 60/825,230 filed on Sep. 11, 2006, the contents of which are incorporated herein by reference. 

   BACKGROUND OF THE INVENTION 
   1. Technical Field 
   The present invention relates to electronic circuits in general, and in particular to switched-capacitor circuits. 
   2. Description of Related Art 
   Switched-capacitor circuits are generally employed in a wide range of electronic devices such as analog-to-digital converters, digital-to-analog converters, delta-sigma modulators, filters, power supplies, voltage regulators, etc. In a basic switched-capacitor circuit, an input voltage is sampled onto a sampling capacitor during a first clock phase. During a non-overlapping second clock phase, the charges in the sampling capacitor are transferred to an integration capacitor. The output of the integration capacitor is subsequently fed back to a summing node. The impedance of the switched-capacitor circuit generally depends on the size of the sampling and integration capacitors and the frequency of a clock. 
   For many applications, special packaging or even heat sinks are commonly required to remove excessive heat dissipated from high-power integrated circuit devices. As a result, the amount of circuits and functions that can be integrated within one chip may be limited. Thus, many high-power applications can be benefited from comparable low-power circuits. As much as low-power circuits being important to non-portable electronic devices, low-power circuits are becoming increasingly in demand due to the proliferation of portable electronic devices such as mobile telephones, mp3 players, etc. 
   The present disclosure provides a low-power switched-capacitor circuit. 
   SUMMARY OF THE INVENTION 
   In accordance with a preferred embodiment of the present invention, a switched-capacitor circuit includes a p-channel switched-capacitor integrator and an n-channel switched-capacitor integrator. The p-channel switched-capacitor integrator includes a first set of input transistors controlled by a first set of capacitors and switches. The n-channel switched-capacitor integrator includes a second set of input transistors controlled by a second set of capacitors and switches. The p-channel switched-capacitor integrator and the n-channel switched-capacitor integrator function together in a push-pull fashion such that a required transconductance as well as width and drain current of the first and second sets of input transistors are reduced by half of those in a conventional switch-capacitor circuit. 
   All features and advantages of the present invention will become apparent in the following detailed written description. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The invention itself, as well as a preferred mode of use, further objects, and advantages thereof, will best be understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein: 
       FIG. 1   a  is a schematic diagram of a switched-capacitor circuit, according to the prior art; 
       FIG. 1   b  is a two-phase non-overlapping clock scheme; 
       FIG. 2  is a schematic diagram of a switched-capacitor circuit, in accordance with a preferred embodiment of the present invention; 
       FIG. 3  is a schematic diagram of a common-mode feedback circuit for the switched-capacitor circuit from  FIG. 2 , in accordance with a preferred embodiment of the present invention; and 
       FIG. 4  is a schematic diagram of a voltage reference circuit for the switched-capacitor circuit from  FIG. 2 , in accordance with a preferred embodiment of the present invention. 
   

   DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT 
   Referring now to the drawings and in particular to  FIG. 1   a , there is depicted a schematic diagram of a switched-capacitor circuit, according to the prior art. As shown, a switched-capacitor circuit  100  includes an operational amplifier  134 , sampling capacitors C S1 , C S2 , integration capacitors C I1 , C I2 , and switches S 1 , S 2 , S 3 , S 4 , S 5 , S 6 , S 7  and S 8 . Operational amplifier  134  can be a telescopic amplifier or a folded-cascode amplifier. Switches S 1 -S 4  are collectively referred to as signal conducting switches, and switches S 5 -S 8  are collectively referred to as summing junction switches. 
   Referring now to  FIG. 1   b , there is illustrated a two-phase non-overlapping clock scheme defined by four clock waveforms: φ 1 , φ 1D , φ 2  and φ 2D , The position of each of switches S 1 -S 8  from  FIG. 1   a  at any given time is determined by its corresponding one of clock waveforms. For the present embodiment, a switch is open when its corresponding clock waveform is in a “low” state, and a switch is close when its corresponding clock waveform is in a “high” state. Clock waveforms φ 1  and φ 1D  are in “high” states when φ 2  and φ 2D  are in “low” states. Clock waveforms φ 1D  and φ 2D  are similar to clock waveforms φ 1  and φ 2 , respectively. However, the falling edges of clock waveforms φ 1D  and φ 2D  are not initiated until after clock waveforms φ 1  and φ 2  have returned to their “low” states. Together, clock waveforms φ 1  and φ 1D  define a sampling phase of a clock scheme while clock waveforms φ 2  and φ 2D  define a transferring phase of the clock scheme. 
   With reference now to  FIG. 2 , there is depicted a schematic diagram of a switched-capacitor circuit, in accordance with a preferred embodiment of the present invention. As shown, a switched-capacitor circuit  200  includes a split-path pseudo-differential amplifier  210 , sampling capacitors C SPA , C SNA , C SPB , C SNB , integration capacitors C IPA , C INA , C IPB , C INB , and switches S 1 A, S 2 A, S 3 A, S 4 A, S 5 A, S 6 A, S 1 B, S 2 B, S 3 B, S 4 B, S 5 B, S 6 B. Preferably, the capacitance of each of sampling capacitors C SPA , C SNA , C SPB  and C SNB  is half the capacitance of C S1  or C S2  from  FIG. 1   a , and the capacitance of each of integration capacitors C IPA . C INA , C IPB  and C INB  is half the capacitance of C I1  or C I2  from  FIG. 1   a . The position of each of switches S 1 A-S 6 A and S 1 B-S 6 B at any given time is determined by its corresponding one of the clock waveforms from  FIG. 1   b.    
   Split-path pseudo-differential amplifier  210  includes p-channel transistors M 4 A, M 3 A and n-channel transistors M 2 A, M 1 A connected in series between a power supply V DD  and a power supply V SS . Split-path pseudo-differential amplifier  210  also includes p-channel transistors M 4 B, M 3 B and n-channel transistors M 2 B, M 1 B connected in series between power supply V DD  and power supply V SS . The gate of transistor M 3 A is connected to the gate of transistor M 3 B, and the gate of transistor M 2 A is connected to the gate of transistor M 2 B. Although split-path pseudo-differential amplifier  210  is shown to have p-channel transistors M 4 A, M 3 A, M 4 B, M 3 B and n-channel transistors M 2 A, M 1 A, M 2 B, M 1 B, each of transistors M 3 A, M 3 B, M 2 A, M 2 B is not essential for the operation of the present invention and can be replaced by a shorted wire without affecting the functionality of split-path pseudo-differential amplifier  210 . 
   The gate of input transistor M 4 A is connected to integration capacitor C IPA , and is selectively connected to sampling capacitor C SPA  via switch S 4 A. The gate of input transistor M 1 A is connected to integration capacitor C INA , and is selectively connected to sampling capacitor C SNA  via switch S 2 A. The gate of input transistor M 4 B is connected to integration capacitor C IPB , and is selectively connected to sampling capacitor C SPB  via switch S 4 B. The gate of input transistor M 1 B is connected to integration capacitor C INB , and is selectively connected to sampling capacitor C SNB  via switch S 2 B. 
   Split-path pseudo-differential amplifier  210  includes four inputs V in1   + , V in2   + , V in1   − , V in2   −  and two outputs V out   +  and V out   − . Input V in1   +  is selectively connected to sampling capacitor C SPA  via switch S 5 A. Input V in2   +  is selectively connected to sampling capacitor C SNA  via switch S 6 A. Input V in1   −  is selectively connected to sampling capacitor C SPB  via switch S 5 B. Input V in1   −  is selectively connected to sampling capacitor C SNB  via switch S 6 A. Output V out   +  is connected to integration capacitors C IPA , C INA  and a node located between transistors M 3 A and M 2 A. Output V out   −  is connected to integration capacitors C IPB , C INB  and a node located between transistors M 3 B and M 2 B. 
   Bias voltage V bpd  is selectively connected to sampling capacitor C SPA  via switch S 3 A, and is selectively connected to sampling capacitor C SPB  via switch S 3 B. Bias voltage V bpd  is selectively connected to input transistor M 4 A via switches S 3 A, S 4 A, and is selectively connected to input transistor M 4 B via switches S 3 B, S 4 B. Bias voltage V bnd  is selectively connected to sampling capacitor C SNA  via switch S 1 A, and is selectively connected to sampling capacitor C SNB  via switch S 1 B. Bias voltage V bnd  is selectively connected to input transistor M 1 A via switches S 1 A, S 2 A, and is selectively connected to input transistor M 1 B via switches S 1 B, S 2 B. Bias voltages V bpd  and V bnd  are generated by a feedback circuit  300  from  FIG. 3  along with its complementary circuit. 
   Split-path pseudo-differential amplifier  210  reduces power consumption through current reuse. During operation, each of the sampling capacitors (i.e., capacitors C SPA , C SNA , C SPB  and C SNB ) and integration capacitors (i.e., capacitors C IPA , C INA , C IPB  and C INB ) are split into two equal parts. One part is connected to the gates of n-channel input transistors (i.e., transistors M 1 A and M 1 B) and the other part is connected to the gates of p-channel input transistors (i.e., transistors M 4 A and M 4 B). As a result, both input transistors M 1 A and M 4 A (or transistors M 1 B and M 4 B) contribute signal amplification, while sharing the same drain current. 
   From an operating principle standpoint, the left half of switched-capacitor circuit  200  can be viewed as an n-channel switched-capacitor integrator (formed by transistors M 1 A, M 2 A, capacitors C SNA , C INA , and switches S 1 A, S 2 A) and a p-channel switched-capacitor integrator (formed by transistors M 3 A, M 4 A, capacitors C SPA , C IPA , and switches S 3 A, S 4 A) in parallel. Similarly, the right half of switched-capacitor circuit  200  can be viewed as an n-channel switched-capacitor integrator (formed by transistors M 1 B, M 2 B, capacitors C SNB , C INB , and switches S 1 B, S 2 B) and a p-channel switched-capacitor integrator (formed by transistors M 3 B, M 4 B, capacitors C SPB , C IPB , and switches S 3 B, S 4 B) in parallel. On both halves, each of the n-channel and p-channel switched-capacitor integrators, which together work in a push-pull fashion, only drives half of the capacitances that a conventional operational amplifier (such as operational amplifier  134  from  FIG. 1 ) needs to drive in order to meet specific signal-to-noise ratio (SNR) specifications. Thus, the required transconductance is reduced by half, as well as the width and drain current of input transistors, which effectively reduces the power dissipation and silicon area of split-path pseudo-differential amplifier  210 . The gate bias voltages for the p-channel and n-channel input transistors are generated through switched-capacitor bias network. 
   Bias voltages V bpd  and V bnd  are dynamically passed to the gates of p-channel transistors M 4 A, M 4 B and n-channel transistors M 1 A, M 1 B, respectively. Bias voltage V bnd  is connected to V bnc  in feedback circuit  300  from  FIG. 3 , and bias voltage V bpd  is connected to an equivalent node of a complementary version of feedback circuit  300  from  FIG. 3 . 
   Referring now to  FIG. 3 , there is illustrated a schematic diagram of a common-mode feedback circuit for switched-capacitor circuit  200  from  FIG. 2 , in accordance with a preferred embodiment of the present invention. As shown, feedback circuit  300  is a common-mode feedback circuit having a direct-charge transfer circuit  310  and an amplifier  320 . 
   With reference now to  FIG. 4 , there is depicted a schematic diagram of a voltage reference circuit for switched-capacitor circuit  200  from  FIG. 2 , in accordance with a preferred embodiment of the present invention. As shown, a voltage reference circuit  400  includes p-channel transistors M 4 , M 3  and n-channel transistors M 2 , M 1  connected in series between power supplies V DD  and V SS . The gate of transistor M 3  is connected to voltage V CP , and the gate of transistor M 2  is connected to voltage V CN . Bias voltage V bp  is selectively connected to transistor M 4  via switches S 41  and S 42 . Bias voltage V bn  is selectively connected to transistor M 1  via switches S 45  and S 46 . Input V I  is selectively connected to output V O  via switches S 43  and S 44 . 
   Voltage reference circuit  400  also includes capacitors C 41 -C 44 . Capacitor C 41  is connected between bias voltage V bp  and input V I , and capacitor C 42  is connected between input V I  and bias voltage V bn . Capacitor C 33  is connected between the gate of transistor M 4  and output V O , and capacitor C 44  is connected between output V O  and the gate of transistor M 1 . Preferably, the capacitance of each of capacitors C 41 -C 42  is half the capacitance of C S1  or C S2  from  FIG. 1   a , and the capacitance of each of capacitors C 43 -C 44  is half the capacitance of C I1  or C I2  from  FIG. 1   a.    
   As has been described, the present invention provides a switched-capacitor circuit having a split-path pseudo-differential amplifier. For the same transconductance, the input referred noise of the split-path pseudo-differential amplifier of the present invention is smaller than those of conventional telescopic amplifiers and folded-cascode amplifiers. Therefore, comparing to conventional switched-capacitor circuits that employ telescopic and folded-cascode amplifiers, the switched-capacitor circuit of the present invention consumes less power, occupies smaller silicon area, and has lower input referred noise. 
   While the invention has been particularly shown and described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention.