Patent Publication Number: US-9887242-B2

Title: Complementary metal oxide semiconductor element and manufacture method thereof

Description:
CROSS REFERENCE 
     This application claims the priority of Chinese Patent Application No. 201510970419.4, entitled “Complementary metal oxide semiconductor element and manufacture method thereof”, filed on Dec. 22, 2015, the disclosure of which is incorporated herein by reference in its entirety. 
     FIELD OF THE INVENTION 
     The present invention relates to a semiconductor field, and more particularly, relates to a complementary metal oxide semiconductor element and a manufacture method thereof. 
     BACKGROUND OF THE INVENTION 
     The Complementary Metal Oxide Semiconductor (COMS) element is constructed with the P-channel Metal Oxide Semiconductor (PMOS) and the N-channel Metal Oxide Semiconductor (NMOS), together. The CMOS element is the most fundamental circuit structure of the driving chip in the liquid crystal display. In traditional LCD, the driving chip and the substrate (such as the glass substrate) are separately designed without integration, which makes the manufacture cost of the LCD is higher and the thin and light design is hard to be real. In case that the driving chip can be directly manufactured on the substrate, it will be a huge progress for the display devices, such as LCDs. At present, the Low Temperature Poly-silicon (LTPS) technology is generally employed to manufacture the CMOS element on the substrate, which has certain progress in comparison with the separate design of the driving chip and the substrate. However, the LTPS technology is to respectively manufacture the semiconductor layers of the PMOS and the NMOS in the CMOS element. The relatively complicated manufacturing processes such as the laser annealing, doping, and ion implantation are included, and thus the cost is higher. 
     SUMMARY OF THE INVENTION 
     The present invention provides a complementary metal oxide semiconductor element, wherein the complementary metal oxide semiconductor element comprises: 
     a substrate, and the substrate comprises a first surface and a second surface, which are oppositely located; 
     a first metal layer located in the middle of the first surface; 
     an insulation layer located at the first metal layer and the first surface which does not cover the first metal layer; 
     a first type metal oxide semiconductor layer located on the insulation layer corresponding to the first metal layer; 
     a first metal part, a second metal part and a third metal part separately located on the insulation layer, respectively, and the first metal part and the second metal part are separately located at two sides of the first type metal oxide semiconductor layer and both contacts with the first type metal oxide semiconductor layer, and the second metal part is located between the first metal part and a third metal part, wherein the first metal part, the second metal part and the third metal part are defined to be a second metal layer; 
     a second type organic semiconductor layer, and the second type organic semiconductor layer is located in a gap between the second metal part and the third metal part, and on the second metal part and the third metal part where are adjacent to the gap; 
     a passivation layer, located on the first metal part, the second metal part and the third metal part, the first type metal oxide semiconductor layer between the first metal part and the second metal part, and the second type organic semiconductor layer; 
     a third metal layer, located on the passivation layer corresponding to the second type organic semiconductor layer. 
     The complementary metal oxide semiconductor element further comprises: 
     a first etching stopper layer, and the first etching stopper layer comprises a first via, and the first etching stopper layer is located between the first metal part and the first type metal oxide semiconductor layer, and the first metal part is connected with the first type metal oxide semiconductor layer through the first via. 
     The complementary metal oxide semiconductor element further comprises: 
     a second etching stopper layer, and the second etching stopper layer comprises a second via, and the second etching stopper layer is located between the second metal part and the first type metal oxide semiconductor layer, and the second metal part is connected with the first type metal oxide semiconductor layer through the second via. 
     The first type metal oxide semiconductor layer is an N-type metal oxide semiconductor layer, and the second type organic semiconductor layer is a P-type organic semiconductor layer; or the first type metal oxide semiconductor layer is a P-type metal oxide semiconductor layer, and the second type organic semiconductor layer is an N-type organic semiconductor layer. 
     As the first type metal oxide semiconductor layer is the N-type metal oxide semiconductor layer, the first type metal oxide semiconductor layer is IGZO or ITZO. 
     The present invention further provides a manufacture method of a complementary metal oxide semiconductor element, wherein the manufacture method of the complementary metal oxide semiconductor element comprises: 
     providing a substrate, and the substrate comprises a first surface and a second surface, which are oppositely located; 
     forming a first metal layer located in the middle of the first surface; 
     forming an insulation layer located at the first metal layer which does not cover the first surface of the first metal layer; 
     forming a first type metal oxide semiconductor layer located on the insulation layer corresponding to the first metal layer; 
     forming a first metal part, a second metal part and a third metal part separately located on the insulation layer, and the first metal part and the second metal part are separately located at two sides of the first type metal oxide semiconductor layer and both contacts with the first type metal oxide semiconductor layer, and the second metal part is located between the first metal part and a third metal part, wherein the first metal part, the second metal part and the third metal part are defined to be a second metal layer; 
     forming a second type organic semiconductor layer corresponding to a gap between the second metal part and the third metal part, and where are on the second metal part and the third metal part and adjacent to the gap; 
     forming a passivation layer on the second type organic semiconductor layer; 
     forming a third metal layer, located on the passivation layer corresponding to the second type organic semiconductor layer. 
     The manufacture method of the complementary metal oxide semiconductor element further comprises: 
     forming a first etching stopper layer, and a first via is formed in the first etching stopper layer, and the first etching stopper layer is located between the first metal part and the first type metal oxide semiconductor layer, and the first metal part is connected with the first type metal oxide semiconductor layer through the first via; 
     forming a second etching stopper layer, and a second via is formed in the second etching stopper layer, and the second etching stopper layer is located between the second metal part and the first type metal oxide semiconductor layer, and the second metal part is connected with the first type metal oxide semiconductor layer through the second via. 
     The step of forming a first metal layer located in the middle of the first surface comprises: 
     forming a first conductive layer, of which material of an entire layer is metal on the first surface; 
     covering the first conductive layer with a first photoresist layer; 
     exposing the first photoresist layer to remove the first photoresist layer at two sides of the first conductive layer; 
     etching the first conductive layer which is not covered with the first photoresist layer to remove the first conductive layer which is not covered with the first photoresist layer; 
     stripping the first photoresist layer which is remained to form the first metal layer. 
     The step of forming a first type metal oxide semiconductor layer located on the insulation layer corresponding to the first metal layer comprises: 
     forming a first semiconductor layer which is an entire layer on the insulation layer; 
     covering the entire first semiconductor layer with a second photoresist layer; 
     exposing the second photoresist layer to remove the second photoresist layer at two sides of the first semiconductor layer to preserve the second photoresist layer corresponding to the first metal layer; 
     etching the first semiconductor layer which is not covered with the second photoresist layer to remove the first semiconductor layer which is not covered with the second photoresist layer; 
     stripping the second photoresist layer which is remained to form the first type metal oxide semiconductor layer. 
     The step of forming a first metal part, a second metal part and a third metal part separately located on the insulation layer, and the first metal part and the second metal part are separately located at two sides of the first type metal oxide semiconductor layer and both contacts with the first type metal oxide semiconductor layer, and the second metal part is located between the first metal part and a third metal part, wherein the first metal part, the second metal part and the third metal part are defined to be a second metal layer comprises: 
     forming a second conductive layer, of which material of an entire layer is metal on the insulation layer; 
     covering the second conductive layer with a third photoresist layer; 
     exposing the third photoresist layer to form a first via corresponding to a middle of the first type metal oxide semiconductor layer and a second via separately located with the first via to partially expose the second conductive layer; 
     etching the second conductive layer which is not covered with the third photoresist layer to remove the second conductive layer which is not covered with the third photoresist layer; 
     stripping the third photoresist layer to form the first metal part, the second metal part and the third metal part. 
     In comparison with prior art, the NMOS and the PMOS in the CMOS element of the present invention and the manufacture method of the CMOS element are manufactured with the first type metal oxide semiconductor layer and the second type organic semiconductor layer. Therefore, the processes of the laser annealing, doping, and ion implantation required in prior art utilizing the LTPS process, and the high cost manufacture equipments required for these processes can be omitted. Accordingly, the manufacture process of the CMOS can be simplified to reduce the production cost of the CMOS element. Besides, the drain of the NMOS and the source of the PMOS are connected, the solo step of connecting the drain of the NMOS and the source of the PMOS is no longer required, and the manufacture process of the CMOS element can be simplified in advance. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       In order to more clearly illustrate the embodiments of the present invention or prior art, the following figures will be described in the embodiments are briefly introduced. It is obvious that the drawings are merely some embodiments of the present invention, those of ordinary skill in this field can obtain other figures according to these figures without paying the premise. 
         FIG. 1  is a circuit structure diagram of a complementary metal oxide semiconductor element according to a preferred embodiment of the present invention. 
         FIG. 2  is a circuit board diagram of the complementary metal oxide semiconductor element in  FIG. 1 . 
         FIG. 3  is a sectional structure diagram of one preferred embodiment along the I-I line in  FIG. 2 . 
         FIG. 4  is a sectional structure diagram of another preferred embodiment along the I-I line in  FIG. 3 . 
         FIG. 5  is a flowchart of a manufacture method of a complementary metal oxide semiconductor element according to a preferred embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
     Embodiments of the present invention are described in detail with the technical matters, structural features, achieved objects, and effects with reference to the accompanying drawings as follows. It is clear that the described embodiments are part of embodiments of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments to those of ordinary skill in the premise of no creative efforts obtained, should be considered within the scope of protection of the present invention. 
     Please refer to  FIG. 1 ,  FIG. 2  and  FIG. 3 , together.  FIG. 1  is a circuit structure diagram of a complementary metal oxide semiconductor element according to a preferred embodiment of the present invention;  FIG. 2  is a circuit board diagram of the complementary metal oxide semiconductor element in  FIG. 1 ;  FIG. 3  is a sectional structure diagram of one preferred embodiment along the I-I line in  FIG. 2 . The Complementary Metal Oxide Semiconductor (COMS) element  1  comprises a substrate  110 , and the substrate  110  comprises a first surface  110   a  and a second surface  110   b , which are oppositely located; a first metal layer  120  located in the middle of the first surface  110   a ; an insulation layer  130  located at the first metal layer  120  which does not cover the first surface  110   a  of the first metal layer  120 ; a first type metal oxide semiconductor layer  140  located on the insulation layer  130  corresponding to the first metal layer  120 ; a first metal part  151 , a second metal part  152  and a third metal part  153  separately located on the insulation layer  130 , respectively, and the first metal part  151  and the second metal part  152  are separately located at two sides of the first type metal oxide semiconductor layer  140  and both contacts with the first type metal oxide semiconductor layer  140 , and the second metal part  152  is located between the first metal part  151  and the third metal part  153 , wherein the first metal part  151 , the second metal part  152  and the third metal part  153  are defined to be a second metal layer  150 ; a second type organic semiconductor layer  160 , and the second type organic semiconductor layer  160  is located in a gap  154  between the second metal part  152  and the third metal part  153 , and on the second metal part  152  and the third metal part  153  where are adjacent to the gap  154 ; a passivation layer  170 , located on the first metal part  151 , the second metal part  152  and the third metal part  153 , the first type metal oxide semiconductor layer  140  between the first metal part  151  and the second metal part  152 , and the second type organic semiconductor layer  160 ; a third metal layer  180 , located on the passivation layer  170  corresponding to the second type organic semiconductor layer  160 . 
     In this embodiment, the first type metal oxide semiconductor layer  140  is a N-type metal oxide semiconductor layer, and the second type organic semiconductor layer  160  is a P-type organic semiconductor layer. It should be understood that in another embodiment, the first type metal oxide semiconductor layer  140  is a P-type metal oxide semiconductor layer, and the second type organic semiconductor layer  160  is a N-type organic semiconductor layer. As the first type metal oxide semiconductor layer  140  is the N-type metal oxide semiconductor layer, the first type metal oxide semiconductor layer  140  is Indium Gallium Zinc Oxide (IGZO) or Indium Tin Zinc Oxide (ITZO). 
     The introduction is conducted that the first type metal oxide semiconductor layer  140  is a N-type metal oxide semiconductor layer, and the second type organic semiconductor layer  160  is a P-type organic semiconductor layer. Then, which comprises the first type metal oxide semiconductor layer  140  is a N-channel Metal Oxide Semiconductor (NMOS), and which comprises the second type organic semiconductor layer  160  is a P-channel Metal Oxide Semiconductor (PMOS). Namely, in  FIG. 3 , the NMOS is at the left side of the dot line, and the PMOS is at the right side of the dot line. The first metal layer  120  is the gate of the NMOS, and the insulation layer  130  on the first metal layer  120  is the gate isolation layer of the NMOS, and the first metal part  151  is the source of the NMOS, and the second metal part  152  at the left side of the dot line is the drain of the NMOS. The insulation layer  130  at the right side of the dot line constructs the buffer layer of the PMOS. Then, the gate isolation layer of the NMSO and the buffer layer of the PMOS share the same layer, and the second metal part  152  at the right side of the dot line is the source of the PMOS. Because the second metal part  152  is an unitary body, the drain of the NMOS and the source of the PMOS are shared. The third metal part  153  construct the drain of the PMOS, and the second type organic semiconductor layer  160  is the channel layer of the PMOS, and the passivation layer  170  located on the second type organic semiconductor layer  160  construct the gate isolation layer of the PMOS. Then, the passivation layer of the NMOS and the gate isolation layer of PMOS share the same layer. The third metal layer  180  constructs the gate of the PMOS. 
     In this embodiment, that the respective layer structures are directly or indirectly located on the first surface  100   a  is illustrated for description. It is understood that in other embodiments, the respective layer structures also can be directly or indirectly located on the second surface  100   b.    
     Please refer to  FIG. 4 .  FIG. 4  is a sectional structure diagram of another preferred embodiment along the I-I line in  FIG. 3 . In this embodiment, the CMOS element  1  further comprises a first etching stopper layer  191 , and the first etching stopper layer  191  comprises a first via  191   a , and the first etching stopper layer  191  is located between the first metal part  151  and the first type metal oxide semiconductor layer  140 , and the first metal part  151  is connected with the first type metal oxide semiconductor layer  140  through the first via  191   a . The CMOS element further comprises a second etching stopper layer  192 , and the second etching stopper layer  192  comprises a second via  192   a , and the second etching stopper layer  192  is located between the second metal part  152  and the first type metal oxide semiconductor layer  140 , and the second metal part  152  is connected with the first type metal oxide semiconductor layer  140  through the second via  192   a . Both the first etching stopper layer  191  and the second etching stopper layer  192  are employed to protect the first type metal oxide semiconductor layer  140  so that the influence of the dry etching process to the first type metal oxide semiconductor layer  140  in the procedure of forming the second type organic semiconductor layer  160  can be prevented. 
     It is understood that in one embodiment, the CMOS element  1  only comprises the first etching stopper layer  191  without the second etching stopper layer  192 ; or in another embodiment, the CMOS element  1  only comprises the second etching stopper layer  192  without the first etching stopper layer  191 . As the CMOS element  1  comprises one etching stopper layer (the first etching stopper layer  191  or the second etching stopper layer  192 ), it still can protect the first type metal oxide semiconductor layer  140  in comparison with the CMOS element without the etching stopper layer so that the influence of the dry etching process to the first type metal oxide semiconductor layer  140  in the procedure of forming the second type organic semiconductor layer  160  can be prevented; as the CMOS element  1  comprises the first etching stopper layer  191  and the second etching stopper layer  192  at the same time, it can better protect the first type metal oxide semiconductor layer  140  so that the influence of the dry etching process to the first type metal oxide semiconductor layer  140  in the procedure of forming the second type organic semiconductor layer  160  can be prevented. Preferably, as the CMOS element  1  comprises the first etching stopper layer  191  and the second etching stopper layer  192  at the same time, the first etching stopper layer  191  and the second etching stopper layer  192  are at the same layer for convenience of forming the first etching stopper layer  191  and the second etching stopper layer  192 . 
     The manufacture method of the complementary metal oxide semiconductor element according to the preferred embodiment of the present invention is introduced below with the aforesaid description and the figures. Please refer to  FIG. 5 .  FIG. 5  is a flowchart of a manufacture method of a complementary metal oxide semiconductor element according to a preferred embodiment of the present invention. The manufacture method of the complementary metal oxide semiconductor element comprises following steps but not limited thereto. 
     Step S 101 , providing a substrate  110 , and the substrate  110  comprises a first surface  110   a  and a second surface  110   b , which are oppositely located. The substrate  110  can be but not be restricted to be a plastic substrate or a glass substrate. 
     Step S 102 , forming a first metal layer  120  located in the middle of the first surface  110   a . Specifically, the step S 102  comprises steps of: 
     Step S 102   a , forming a first conductive layer, of which material of an entire layer is metal on the first surface. The first conductive layer can be formed by sputtering. The material of the first conductive layer can comprise material of Mo/Al or Cu/Ti. 
     Step S 102   b , patterning the first conductive layer of the entire layer to form a first metal layer  120  located in the middle of the first surface  110   a . The step S 102   b  specifically comprises steps below. 
     Step I, covering the first conductive layer with a first photoresist layer. 
     Step II, exposing the first photoresist layer to remove the first photoresist layer at two sides of the first conductive layer. 
     Step III, etching the first conductive layer which is not covered with the first photoresist layer to remove the first conductive layer which is not covered with the first photoresist layer. 
     Step IV, stripping the first photoresist layer which is remained to form the first metal layer  120 . 
     Step S 103 , forming an insulation layer  130  located at the first metal layer  120  and the first surface  110  which does not cover the first metal layer  120 . The insulation layer  130  can be formed with Chemical Vapor Deposition (CVD) or coating. 
     Step S 104 , forming a first type metal oxide semiconductor layer  140  located on the insulation layer  130  corresponding to the first metal layer  120 . Specifically, the step S 104  comprises steps below. 
     Step S 104   a , forming a first semiconductor layer which is an entire layer on the insulation layer  130 . 
     Step S 104   b , covering the entire first semiconductor layer with a second photoresist layer. 
     Step S 104   c , exposing the second photoresist layer to remove the second photoresist layer at two sides of the first semiconductor layer to preserve the second photoresist layer corresponding to the first metal layer. 
     Step S 104   d , etching the first semiconductor layer which is not covered with the second photoresist layer to remove the first semiconductor layer which is not covered with the second photoresist layer. 
     Step S 104   e , stripping the second photoresist layer which is remained to form the first type metal oxide semiconductor layer  140 . 
     Step S 105 , forming a first metal part  151 , a second metal part  152  and a third metal part  153  separately located on the insulation layer  130 , and the first metal part  151  and the second metal part  152  are separately located at two sides of the first type metal oxide semiconductor layer  140  and both contacts with the first type metal oxide semiconductor layer  140 , and the second metal part  152  is located between the first metal part  151  and a third metal part  153 , wherein the first metal part  151 , the second metal part  152  and the third metal part  153  are defined to be a second metal layer  150 . Specifically, the step S 105  comprises steps below. 
     Step S 105   a , forming a second conductive layer, of which material of an entire layer is metal on the insulation layer  130 . 
     Step S 105   b , covering the second conductive layer with a third photoresist layer. 
     Step S 105   c , exposing the third photoresist layer to form a first via corresponding to a middle of the first type metal oxide semiconductor layer  140  and a second via separately located with the first via to partially expose the second conductive layer. 
     Step S 105   d , etching the second conductive layer which is not covered with the third photoresist layer to remove the second conductive layer which is not covered with the third photoresist layer. 
     Step S 105   e , stripping the third photoresist layer to form the first metal part  151 , the second metal part  152  and the third metal part  153 . 
     Step S 106 , forming a second type organic semiconductor layer  160  corresponding to a gap  154  between the second metal part  152  and the third metal part  153 , and where are on the second metal part  152  and the third metal part  153  and adjacent to the gap  154 . Specifically, the step S 106  comprises steps below. 
     Step S 106   a , covering a second organic semiconductor layer with an entire layer. The material of the second organic semiconductor layer can be pentacene. 
     Step S 106   b , patterning the second organic semiconductor layer to preserve the second organic semiconductor layer corresponding to the gap  154  between the second metal part  152  and the third metal part  153 , and the second metal part  152  adjacent to the gap  154  and the third metal part  153  adjacent to the gap  154  to form the second type organic semiconductor layer  160 . 
     Step S 107 , forming a passivation layer  170  on the second type organic semiconductor layer  160 . The passivation layer  170  can be formed by CVD or coating. 
     Step S 108 , forming a third metal layer  180 , located on the passivation layer  170  corresponding to the second type organic semiconductor layer  160 . Specifically, the step S 108  comprises steps below. 
     Step S 108   a , forming a third conductive layer, of which material of an entire layer is metal on the passivation layer  170 . The third conductive layer can be formed by sputtering. The material of the third conductive layer can comprise material of Mo/Al or Cu/Ti. Materials of the first metal layer  120 , the second metal layer  150  and the third metal layer  180  can be the same or different. 
     Step S 108   b , covering the third conductive layer with a fourth photoresist layer. 
     Step S 108   c , exposing the fourth photoresist layer to preserve the fourth photoresist layer corresponding to the second type organic semiconductor layer  160  and to remove the rest fourth photoresist layer. 
     Step S 108   d , etching the third conductive layer which is not covered with the fourth photoresist layer to remove the third conductive layer which is not covered with the fourth photoresist layer. 
     Step S 108   e , stripping the rest fourth photoresist layer to form the third metal layer  180 . 
     In one embodiment, the manufacture method of the CMOS element further comprises steps below. 
     Step S 109 , forming a first etching stopper layer  191 , and a first via  191   a  is formed in the first etching stopper layer  191 , and the first etching stopper layer  191  is located between the first metal part  151  and the first type metal oxide semiconductor layer  140 , and the first metal part  151  is connected with the first type metal oxide semiconductor layer  140  through the first via  191   a.    
     Step S 110 , forming a second etching stopper layer  192 , and a second via  192   a  is formed in the second etching stopper layer  192 , and the second etching stopper layer  192  is located between the second metal part  152  and the first type metal oxide semiconductor layer  140 , and the second metal part  152  is connected with the first type metal oxide semiconductor layer  140  through the second via  192   a.    
     In this embodiment, the first type metal oxide semiconductor layer  140  is a N-type metal oxide semiconductor layer, and the second type organic semiconductor layer  160  is a P-type organic semiconductor layer. It should be understood that in another embodiment, the first type metal oxide semiconductor layer  140  is a P-type metal oxide semiconductor layer, and the second type organic semiconductor layer  160  is a N-type organic semiconductor layer. As the first type metal oxide semiconductor layer  140  is the N-type metal oxide semiconductor layer, the first type metal oxide semiconductor layer  140  is IGZO or ITZO. 
     In comparison with prior art, the NMOS and the PMOS in the CMOS element  1  of the present invention and the manufacture method of the CMOS element  1  are manufactured with the first type metal oxide semiconductor layer  140  and the second type organic semiconductor layer  160 . Therefore, the processes of the laser annealing, doping, and ion implantation required in prior art utilizing the LTPS process, and the high cost manufacture equipments required for these processes can be omitted. Accordingly, the manufacture process of the CMOS can be simplified to reduce the production cost of the CMOS element. Besides, the drain of the NMOS and the source of the PMOS are connected, the solo step of connecting the drain of the NMOS and the source of the PMOS is no longer required, and the manufacture process of the CMOS element can be simplified. 
     Above are embodiments of the present invention, which does not limit the scope of the present invention. Any modifications, equivalent replacements or improvements within the spirit and principles of the embodiment described above should be covered by the protected scope of the invention.