Patent Publication Number: US-11049639-B2

Title: Coupled coils with lower far field radiation and higher noise immunity

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This application claims the benefit under 35 U.S.C. § 119(e) of U.S. Provisional Patent Application Ser. No. 62/458,505, filed on Feb. 13, 2017 and entitled “Coupled Coils with Lower Far Field Radiation and Higher Noise Immunity,” which is hereby incorporated herein by reference in its entirety. 
    
    
     FIELD OF THE DISCLOSURE 
     The present application relates to micro-fabricated coils. 
     BACKGROUND 
     Some types of circuits employ coils or windings. For instance, circuits having inductors or transformers may use windings. Examples include galvanic isolators. Micro-fabricated circuits sometimes use micro-fabricated coils. 
     SUMMARY OF THE DISCLOSURE 
     Micro-fabricated coils are described. In some situations, the micro-fabricated coils include interleaved coils. In some situations, pairs of interleaved coils are stacked with respect to each other, separated by an insulating material. In some situations, the interleaved coils have an S-shape. The interleaved coils may be employed in a galvanic isolator. 
     According to one aspect of the present application, a micro-fabricated coil structure is provided. The micro-fabricated coil structure may comprise a substrate, a first pair of interleaved coils on the substrate, a second pair of interleaved coils on the substrate, the second pair of interleaved coils being electromagnetically couplable to the first pair of interleaved coils, and an insulating layer separating the first pair of interleaved coils from the second pair of interleaved coils. 
     According to another aspect of the present application, an isolator is provided. The isolator may comprise a micro-fabricated transformer comprising a primary coil and a secondary coil, a transmitter, wherein the transmitter is configured to drive the primary coil, and a receiver, wherein the receiver is configured to receive signals from the secondary coil. The primary coil may be a first pair of interleaved coils on a substrate. The secondary coil may be a second pair of interleaved coils on the substrate. The second pair of interleaved coils may be separated from the first pair of interleaved coils by an insulating layer. The second pair of interleaved coils may be electromagnetically couplable to the first pair of interleaved coils. 
     According to another aspect of the present application, a method of manufacturing a coil structure on a substrate is provided. The method may comprise fabricating a first pair of interleaved coils, forming an insulating layer on the first pair of interleaved coils, and fabricating a second pair of interleaved coils on the insulating layer. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Various aspects and embodiments of the application will be described with reference to the following figures. It should be appreciated that the figures are not necessarily drawn to scale. Items appearing in multiple figures are indicated by the same reference number in all the figures in which they appear. 
         FIG. 1A  is a schematic diagram illustrating micro-fabricated stacked interleaved coils, according to some non-limiting embodiments. 
         FIG. 1B  is a cross-sectional view of the micro-fabricated stacked interleaved coils of  FIG. 1A  along  1 B- 1 B, according to some non-limiting embodiments. 
         FIG. 1C  is a top view of one pair of the micro-fabricated stacked interleaved coils of  FIG. 1A , according to some non-limiting embodiments. 
         FIG. 1D  is an equivalent circuit of the micro-fabricated stacked interleaved coils of  FIG. 1A . 
         FIG. 1E  is a flowchart illustrating an example of the operation of the micro-fabricated stacked interleaved coils of  FIGS. 1A and 1B , according to some non-limiting embodiments. 
         FIG. 2A  is a schematic illustrating a pair of micro-fabricated interleaved S coils, according to some non-limiting embodiments. 
         FIG. 2B  is an equivalent circuit of the interleaved coils of  FIG. 2A . 
         FIG. 2C  is a schematic illustrating an alternative layout of a pair of micro-fabricated interleaved S coils, according to some non-limiting embodiments. 
         FIG. 2D  is an equivalent circuit of the interleaved coils of  FIG. 2C . 
         FIG. 2E  is a layout view of the interleaved S coils of  FIG. 2A  with a bond pad arrangement, according to some non-limiting embodiments. 
         FIG. 2F  is a layout view of the interleaved S coils of  FIG. 2C  with a bond pad arrangement, according to some non-limiting embodiments. 
         FIG. 2G  is a layout view of an alternative layout of interleaved S coils with a bond pad arrangement, according to some non-limiting embodiments. 
         FIG. 2H  is a schematic illustrating the interleaved S coils of  FIG. 2A  driven by N-type transistors, according to some non-limiting embodiments. 
         FIG. 2I  is a schematic illustrating the interleaved S coils of  FIG. 2A  driven by P-type transistors, according to some non-limiting embodiments. 
         FIG. 3A  is a schematic diagram illustrating micro-fabricated stacked interleaved S coils, according to some non-limiting embodiments. 
         FIG. 3B  is an equivalent circuit of the micro-fabricated stacked interleaved S coils of  FIG. 3A . 
         FIG. 4  is a flowchart illustrating a method of manufacturing stacked interleaved coils described herein, according to some non-limiting embodiments. 
         FIG. 5  is a circuit employing micro-fabricated stacked interleaved coils described herein, according to some non-limiting embodiments. 
         FIG. 6  illustrates a system comprising the circuit of  FIG. 5 , according to some non-limiting embodiments. 
     
    
    
     DETAILED DESCRIPTION 
     Aspects of the present application provide micro-fabricated coils that may be used in galvanic isolator circuits, among other devices. The micro-fabricated coils include interleaved coils. In some situations, pairs of interleaved coils are stacked with respect to each other, separated by an insulating material. In some situations, the interleaved coils have an S-shape. Circuits incorporating the micro-fabricated coils described herein may exhibit improved noise immunity and power consumption, and may be made smaller than circuits incorporating alternative coil structures. 
     In some embodiments, stacked pairs of micro-fabricated interleaved coils are provided. A pair of interleaved coils may be formed by interleaving two coils. The two coils may be formed from a common metal layer of a micro-fabricated structure. In some embodiments, two pairs of interleaved coils may be positioned in proximity to each other, but separated by an insulating layer to provide galvanic isolation. For example, a first pair of interleaved coils may be vertically separated from a second pair of interleaved coils of a micro-fabricated structure by an insulating layer on a substrate. One pair of interleaved coils may be operated in a first voltage domain and the other pair of interleaved coils may be operated in a second voltage domain. Data and/or power signals may be transferred between the pairs of interleaved coils while maintaining galvanic isolation. The staked pairs of interleaved coils may provide beneficial operating characteristics, including reduced susceptibility to near field disturbances. 
     In some embodiments, a pair of interleaved coils may be formed by interleaving two “S” coils. An S coil is one in which the winding or trace assumes an S-like configuration, with part of the coil winding in one direction (e.g., clockwise) and part of the same coil winding in the opposite direction (e.g., counter-clockwise). Two planar S coils may be formed from a common metal layer of a micro-fabricated structure. The two S coils may provide four ends (e.g., bond pads serving as contact points). This interleaved structure may be referred to as an “SS” coil. The SS configuration may force the flux induced by the part of the coil winding in one direction to return to the part of the coil winding in the opposite direction to contain the flux that may escape the surface of the coil. Optionally, the SS coils may be connected to provide a center tap, and the center tap can be tied to a supply rail to source or sink displacement currents caused by a common mode voltage potential. The “SS” coil may provide beneficial operating characteristics, including reduced direct far field radiation and, more generally, reduced susceptibility to external fields, including both near field and far field disturbances. 
     In some embodiments, stacked SS coils are provided. Two SS coils may be separated by an insulating layer to provide galvanic isolation. For example, a first SS coil may be vertically separated from a second SS coil of a micro-fabricated structure by an insulating layer. These stacked SS coils may provide beneficial operating characteristics including reduced susceptibility to both near field and far field electromagnetic disturbances. Also, with suitable additional coupling, power requirements to achieve oscillation may be reduced. For example, stacked SS coils or a single SS coil may be applied to Voltage Control Oscillators (VCO) to achieve lower radiated emission and lower susceptibility to electromagnetic interferences (EMI). In another example, this configuration may also improve the performance of self-excited drive circuits by providing an additional energy path between the driver devices. Circuits incorporating the micro-fabricated coils described herein may consume less power and less chip area to implement than circuits incorporating alternative methods, such as increasing the number of turns of conventional coils or using phase modulation using parallel links. 
     In some embodiments, micro-fabricated coils may be formed in, partially in, or on a semiconductor substrate. For example, the traces may be patterned from a conductive layer, and may be planar in at least some embodiments. Standard integrated circuit fabrication processing may be used. 
     The aspects and embodiments described above, as well as additional aspects and embodiments, are described further below. These aspects and/or embodiments may be used individually, all together, or in any combination of two or more, as the application is not limited in this respect. 
     As described above, an aspect of the present application provides stacked pairs of micro-fabricated interleaved coils.  FIG. 1A  illustrates an example. Namely,  FIG. 1A  is a schematic diagram illustrating micro-fabricated stacked interleaved coils  100 , according to some non-limiting embodiments. The stacked interleaved coils  100  may include a first (e.g., top) pair of interleaved coils  101  and a second (e.g., bottom) pair of interleaved coils  103  on a substrate  114 . The two pairs of interleaved coils  101  and  103  may be separated by an insulating layer  110  (shown in  FIG. 1B ). The top pair of interleaved coils  101  may include a first coil  102  winding in a direction from terminal A to terminal A*, and a second coil  104  winding in the same direction as coil  102  from terminal B to terminal B*. The terminals of the top pair of interleaved coils may be accessible through bonding pads. The bottom pair of interleaved coils  103  may include a third coil  106  winding in a direction from terminal C to terminal C*, and a fourth coil  108  winding in the same direction as coil  106  from terminal D to terminal D*. The terminals of the bottom pair of interleaved coils may interconnect to a metallization layer  112  in the substrate  114  through vias  116 . Traces formed from the metallization layer  112  may connect the terminals of the bottom pair of interleaved coils to bonding pads. 
     In some embodiments, the top pair of interleaved coils  101  may include a center tap  122 . Terminal A* may be electrically connected to terminal B through the center tap  122  such that a mutual inductance can be established between coils  102  and  104 . The center tap  122  may be formed by wire bonding pads for terminals A* and B. Similarly, the bottom pair of interleaved coils  103  may include a center tap  124 . Terminal C* may be electrically connected to terminal D through the center tap  124 . The center tap  124  may be formed by traces of the metallization layer  112  or wire bonding pads for terminals C* and D. The use of such center taps is optional, as alternative embodiments lack the center taps. 
       FIG. 1B  illustrates a cross-sectional view of the stacked interleaved coils  100  along line  1 B- 1 B of  FIG. 1A . The top pair of interleaved coils may be formed from a metallization layer  118 M in an insulating layer  118 . The bottom pair of interleaved coils may be formed from a metallization layer  120 M in an insulating layer  120 . Metallization layers  118 M and  120 M may be substantially parallel to a surface  115  of the substrate  114 . The metallization layer  120 M may interconnect to the metallization layer  112  through vias  116 . The metallization layers  118 M,  120 M and  112  may be formed of aluminum, copper, gold, tungsten, or any other suitable conductive material, or any number of conductive materials in any suitable combination. The metallization layers  118 M,  120 M and  112  may be formed of the same conductive material in some embodiments, or different conductive materials. In some embodiments, the metallization layer  112  may be a copper layer. Traces of the metallization layer  112 , for example the center tap  124 , may be fabricated by a damascene process. In some embodiments, the metallization layers  118 M and  120 M may be aluminum layers. In some embodiments, the metallization layer  118 M may be gold and layer  120 M may be aluminum. The first pair of interleaved coils  101  may be fabricated by etching the aluminum layer  118 M to form windings with a width w. The second pair of interleaved coils  103  may be fabricated by etching the aluminum layer  120 M with the same width w or a differing width w′ with a differing pitch as may be dictated by the process rules, material and design requirements. The width w may be in the range of 1 to 20 μm, for example between 4 to 8 μm, including any value within those ranges. Alternative values are also possible. The two insulating layers  118  and  120  may be separated by the insulating layer  110 . The insulating layer  110  may include any suitable structure and material to provide electrical isolation between the stacked pairs of interleaved coils. In some embodiments, the insulating layer may have a multi-layer structure. For example, in the illustrated non-limiting example the insulating layer  110  may include a first layer  110 A and a second layer  110 B on top of the first layer  110 A. The layer  110 A may be formed of SiN. The layer  110 B may be formed of polyimide. The thickness of the insulating layer  110  may be in the range of 0.25 to 100 microns, for example being between 15 and 30 microns, including any value within those ranges. In embodiments where differing materials are used, one layer may be 0.5 to 2 microns of SiN and other insulating layers may be multiple depositions of 15 to 30 microns of polyimide to complete the second layer. 
       FIG. 1C  illustrates a top view of the first pair of interleaved coils  101 , according to some non-limiting embodiments. Although not visible in the figure, coil  102  may be substantially aligned with coil  106  of the second pair of interleaved coils  103  along a direction substantially perpendicular to the surface  115  of the substrate  114 . Likewise, coil  104  may be substantially aligned with coil  108  along the same direction. Therefore, aspects of the present application provide aligned vertically stacked pairs of interleaved coils separated by an insulating layer. In the illustrated example, each of the coils  102  and  104  has 2 turns. However, the present application is not limited in this regard. Each of the coils  102  and  104  may have any number of turns, for example, 2, 3, 3.5, 4, or more. Also, the coil  102  and the coil  104  may have different numbers of turns, for example, 2 turns for coil  102  and 2.5 for coil  104 . Other configurations are possible. 
     In the illustrated example shown in  FIG. 1A , the coils  106  and  108  of the second pair of interleaved coils  103  have the same numbers of turns as coils  102  and  104  of the first pair of interleaved coils  101 . However, the present application is not limited in this regard. The second pair of interleaved coils may have a number of turns different from that of the first pair of interleaved coils. A ratio of the number of turns of the first pair of interleaved coils to the number of turn of the second pair of interleaved coils may be designed in accordance with intended applications. 
       FIG. 1D  is an equivalent circuit of the stacked interleaved coils  100 . Terminals A, B, C, and D are marked with dots, indicating current flow from terminal A to terminal A*, from terminal B to terminal B*, from terminal C to terminal C*, and from terminal D to terminal D*. As a result, mutual inductances can be established in each pair of interleaved coils as well as between top and bottom pairs. 
       FIG. 1E  is a flowchart illustrating an example of the operation of the stacked interleaved coils  100 , according to some non-limiting embodiments. The method  150  of operating the stacked interleaved coils  100  may include, at stage  152 , applying a signal to the pair of interleaved coils  101  from terminal A through terminal A* and then terminal B to terminal B*. The signal applied may be a time-varying (e.g., alternating current (AC)) signal of any suitable frequency and amplitude. In some situations, the signal may be a data signal, carrying information. As a result of application of the signal to the pair of interleaved coils  101 , a varying magnetic field B may be generated at stage  154  of the method. The corresponding magnetic flux may pass through the second pair of interleaved coils  103 . Thus, at stage  156 , a signal may be induced in the pair of interleaved coils  103  between terminal C through terminal C* and then terminal D to terminal D*. The method  150 , however, represents a non-limiting manner of operation of the stacked interleaved coils  100 . 
     Another aspect of the present application provides stacked pairs of micro-fabricated interleaved coils assuming an S-like configuration, which may also be referred to as stacked SS coils.  FIG. 2A  schematically illustrates a pair of micro-fabricated interleaved coils  201 , according to some non-limiting embodiments. The pair of interleaved coils  201  may include a first S coil  202  interleaved with a second S coil  204 . The first S coil  202  starting at terminal A may include a clockwise coil portion  202 A and a counterclockwise coil portion  202 B ending at terminal A*. The second S coil  204  starting at terminal B may include a clockwise coil portion  204 A and a counterclockwise coil portion  204 B ending at terminal B*. The number of turns may not be the same for the two sides of the S coils, as various alternatives may be implemented in terms of the number of turns. In the illustrated example,  202 A and  204 B have 2 turns and  202 B and  204 A have 1.5 turns. However, these are non-limiting examples. 
     The shape of the SS-coil illustrated in  FIG. 2A  is non-limiting. In the illustration, the S coils  202  and  204  have a spiral shape. Alternatively, the S coils may have a rectangular shape. Other shapes are also possible while still being an S coil. 
       FIG. 2B  is an equivalent circuit of the interleaved SS coil of  FIG. 2A . Terminals A and B are marked with dots, indicating currents flow from terminal A to terminal A* and from terminal B to terminal B*. As a result, mutual inductances can be established between coil portions  202 A and  204 A as well as between coil portions  202 B and  204 B. 
       FIG. 2C  schematically illustrates an alternative layout of an SS coil including a pair of interleaved S coils  205 , according to some non-limiting embodiments.  FIG. 2D  is an equivalent circuit of the SS coil  205 . The SS coil  205  may include a first S coil  206  interleaved with a second S coil  208 . The first S coil  206  starting at terminal A may include a clockwise coil portion  206 A and a counterclockwise coil portion  206 B ending at terminal A*. The second S coil  208  starting at terminal B may include a clockwise coil portion  208 A and a counterclockwise coil portion  208 B ending at terminal B*. The difference between the SS coil  205  and the SS coil  201  of  FIG. 2A  is that the SS coil  205  has an equal number of turns on each side of the SS coil  205 , whereas the SS coil  201  has an unequal number of turns as described above in connection with  FIG. 2A . In the non-limiting example of  FIG. 2C , the coil portions  206 A,  206 B,  208 A and  208 B each have 1.75 turns. 
     SS coils of the types described herein may be physically implemented in any suitable manner. As described previously, the coils described herein may be microfabricated, and thus may be formed on a suitable substrate, such as a semiconductor substrate.  FIG. 2E  is a layout view of an SS coil  211  consistent with the SS coil  201  of  FIG. 2A  with a suitable bond pad arrangement, according to some non-limiting embodiments. The SS coil  211  may include the SS coil  201 , the terminals of which may interconnect through vias  216  to traces  212  and then to bond pads  230 . The interleaved S coils  202  and  204  may be formed from a metallization layer  220 M as may be bond pads  230 . The traces  212  may be formed from a metallization layer  212 M on a plane different from but substantially parallel to the plane of the metallization layer  220 M. The metallization layers  212 M and  220 M may be separated by an insulating layer such that the terminals of coils  202  and  204  may be connected to respective bond pads without being electrically short circuited. The metallization layer  220 M may be of the type described previously herein with respect to the metallization layer  120 M. The metallization layer  212 M may be of the type described previously herein with respect to the metallization layer  112 . The bond pads for terminals A, A*, B, and B* may be aligned in a line on one side of the SS coil  201 . 
       FIG. 2F  is a layout view of an SS coil  213  consistent with the SS coil  205  of  FIG. 2C  with a suitable bond pad arrangement, according to some non-limiting embodiments. The difference between the structure of  FIG. 2F  and the structure of  FIG. 2E  is substantially the same as the difference described previously herein between the SS coil  205  of  FIG. 2C  and the SS coil  201  of  FIG. 2A . 
       FIG. 2G  is a layout view of a further alternative of an SS coil  215  with a suitable bond pad arrangement, according to some non-limiting embodiments. The SS coil  215  may include SS coil  209 , the terminals of which may interconnect through vias  216  to traces  212  and then to bond pads  230 . The SS coil  209  may include a first S coil  218  interleaved with a second S coil  220 . The first S coil  218  starting at terminal A may include a clockwise coil portion and a counterclockwise coil portion ending at terminal A*. The second S coil  220  starting at terminal B may include a clockwise coil portion and a counterclockwise coil portion ending at terminal B*. The bond pads for terminals A and B may be aligned in a first line on a first side of the SS coil  209 . The bond pads for terminals A* and B* may be aligned in a second line on a second side of the SS coil  209  opposite the first side. 
       FIG. 2H  schematically illustrates an example of a circuit  250  in which the SS coil  201  may be implemented. Namely,  FIG. 2H  illustrates a circuit  250  in which the SS coil  201  is driven by cross-coupled NMOS transistors  252   a  and  252   b , according to some non-limiting embodiments. The circuit also includes a current source I 1 . A supply voltage Vdd is applied at the node connecting A* and B. 
       FIG. 2I  schematically illustrates an alternative circuit  260  for driving the SS coil  201 . In this non-limiting example, the SS coil  201  is driven by cross-coupled PMOS transistors  262   a  and  262   b , according to some non-limiting embodiments. A center tap may be formed between terminal A* and terminal B such that coil  202  and coil  204  are connected in series. This node between A* and B may be electrically grounded as shown. 
     According to some aspects of the present application, two SS coils are stacked relative to each other, and separated by an insulating structure.  FIG. 3A  illustrates an example, in the form of stacked SS coils  300 . The stacked SS coils  300  may include a top SS coil  301  and a bottom SS coil  303  separated by an insulating layer  310  (see  FIG. 3B ) to provide galvanic isolation. The insulating layer  310  is not shown in  FIG. 3A  for simplicity of illustration, but may be of the type described previously herein with respect to insulating layer  110 . The top SS coil  301  may include a first S coil  302  interleaved with a second S coil  304 . S coil  302  starting at terminal A may include a clockwise coil portion  302 A and a counterclockwise coil portion  302 B ending at terminal A*. S coil  304  starting at terminal B may include a clockwise coil portion  304 A and a counterclockwise coil portion  304 B ending at terminal B*. The bottom SS coil  303  may include a third S coil  306  interleaved with a fourth S coil  308 . S coil  306  starting at terminal C may include a clockwise coil portion  306 A and a counterclockwise coil portion  306 B ending at terminal C*. S coil  308  starting at terminal D may include a clockwise coil portion  308 A and a counterclockwise coil portion  308 B ending at terminal D*. The bottom SS coil  303  may be substantially identical to the top SS coil  301  in some embodiments, although alternatives are possible. A ratio of the number of turns of the top SS coil to the number of turns of the bottom SS coil may be designed in accordance with intended applications. For example, the ratio may be in the range of 0.01 to 10, for example, between 0.5 and 5, or between 0.8 and 2. 
     The stacked SS coils  300  may be formed in, partially in, or on a semiconductor substrate  314 . The top SS coil  301  may be formed using a first single metallization layer  318 M in an insulating layer  318  of a standard integrated fabrication process. The bottom SS coil  303  may be formed using a second metallization layer  320 M in an insulating layer  320  of a standard integrated fabrication process. Metallization layers  318 M and  320 M may be substantially parallel to a surface of the substrate  314 . The insulating layers  318  and  320  may be separated by insulating layer  310 , for example of the type described previously in connection with insulating layer  110 . The metallization layer  120 M may interconnect to a third metallization layer  312  through vias  316 . 
       FIG. 3B  is an equivalent circuit of the stacked SS coils  300  according to a non-limiting embodiment. Terminals A, B, C, and D are marked with dots, indicating current flow from terminal A to terminal A*, from terminal B to terminal B*, from terminal C to terminal C*, and from terminal D to terminal D*. As a result, mutual inductances can be established between coil portions on the same side of each SS coil as well as between top and bottom SS coils. 
       FIG. 4  illustrates a method of manufacturing micro-fabricated stacked interleaved coils described herein, according to some non-limiting embodiments. Method  400  may begin at stage  402 , in which a first pair of interleaved coils may be fabricated. The interleaved coils may be of any of the types described herein, including in at least some embodiments being interleaved S coils. The first pair of interleaved coils may be fabricated in a dielectric layer on a semiconductor substrate in some embodiments. 
     At stage  404 , an insulating layer may be formed on the first pair of interleaved coils. For example, the insulating layer  110  or  310  may be formed. As described previously herein, the insulating layer may have a multi-layer structure in some embodiments and may be formed of any suitable material to provide galvanic isolation. 
     Proceeding to stage  406 , a second pair of interleaved coils may be formed on the insulating layer. The second pair of interleaved coils may be any of the types described herein. In at least some embodiments, stage  406  involves aligning the second pair of interleaved coils with the previously formed first pair of interleaved coils. 
       FIG. 5  illustrates a circuit employing micro-fabricated stacked interleaved coils described herein, according to some non-limiting embodiments. The circuit may be an isolator  500  including a transmitter  504  formed on a substrate  502 , a transformer formed by micro-fabricated stacked interleaved coils described herein comprising a first pair of interleaved coils  506 A and a second pair of interleaved coils  506 B formed on a substrate  508 , along with a receiver  510 . Wire leads  512 A and  512 B from bond pads  514 A and  514 B on substrate  502  connect the driver output to the primary winding (first pair of interleaved coils  506 A) of the transformer. In the illustrated example, the primary (driving) coil is the first pair of interleaved coils  506 A and the secondary (receiving) coil is the second pair of interleaved coils  506 B. However, the present application is not limited to this configuration. For example, the primary and secondary coils may be reversed, the transmitter may be on substrate  508 , and the receiver may be on substrate  502 . In some embodiments, substrates  502  and  508  may be a single substrate. Wire leads  512 A and  512 B may be formed by metallization layers connected through vias. 
     Interleaved coils of the types described herein may be implemented in various settings. As has been described, some aspects of the present application employ interleaved coils in electrical isolators. Electrical isolators in turn may find application in various settings, including in automobiles, or other vehicles, such as boats or aircrafts.  FIG. 6  illustrates a system comprising the circuit  500  of  FIG. 5 , according to some non-limiting embodiments. Circuit  500  may be disposed in any suitable location of car  600 . Circuit  500  may be configured to transfer data and/or power signals between circuits of the car  600  that operate in different voltage domains while maintaining galvanic isolation. While  FIG. 6  illustrates one example, other uses of the various aspects of the present application are possible. 
     The terms “approximately”, “substantially,” and “about” may be used to mean within ±20% of a target value in some embodiments, within ±10% of a target value in some embodiments, within ±5% of a target value in some embodiments, and yet within ±2% of a target value in some embodiments.