Patent Publication Number: US-6982924-B2

Title: Data output control circuit

Description:
FIELD OF INVENTION 
   The present invention relates to a semiconductor device; and, more particularly, to a data output control circuit for outputting data. 
   DESCRIPTION OF PRIOR ART 
   A semiconductor memory device has been continuously improved to increase its operational speed. One of methods to improve an operational speed of a semiconductor memory device is to make the semiconductor memory device operate in synchronization with an external clock signal. Therefore, a semiconductor memory device which operates in synchronization with the external clock signal, namely a synchronous semiconductor memory device, has been developed. 
   The synchronous semiconductor memory device performs a data access operation at a rising edge of the external clock signal. That is, the synchronous semiconductor memory device can perform the data access operation once within one cycle of the external clock signal. 
   Such a synchronous semiconductor memory device that performs the data access operation once within one cycle of the external clock signal is particularly called a single data rate (SDR) synchronous semiconductor memory device. 
   However, the SDR synchronous semiconductor memory device had to be more improved for use in a high speed system. Therefore, a double data rate (DDR) synchronous semiconductor memory device has been developed. The DDR synchronous semiconductor memory device performs the data access operation at a rising edge and a falling edge of the external clock signal. That is, the DDR synchronous semiconductor memory device performs the data access operation twice within one cycle of the external clock signal. 
   Since the DDR synchronous semiconductor memory device should perform the data access operation twice within one cycle of the external clock signal, a data access method used in the SDR synchronous semiconductor memory device can not be used in the DDR synchronous semiconductor memory device. 
   If a cycle of the external clock signal is 10 nano-seconds, the DDR synchronous semiconductor memory device has only about 6 nano-seconds for performing the data access operation because about 4 nano-seconds is spent for other operations such as raising and lowering edges of the external clock signal. 
   Since 6 nano-seconds is too short time for the DDR synchronous semiconductor memory device to internally handle a data at both edges of the external clock signal, the DDR synchronous semiconductor memory device performs a data access operation at both edges, i.e., a falling edge and a rising edge, of the external clock signal only when a data is inputted into or outputted from the DDR synchronous semiconductor memory device and, thus, the DDR synchronous semiconductor memory device internally performs the data access operation in synchronization with one of the both edges of the external clock signal. 
   Therefore, a new data access method is required for a data to be inputted into or outputted from the DDR synchronous semiconductor memory device. 
   For the synchronous semiconductor memory device, some technical terms are used. One of those technical terms is a column address strobe (CAS) latency. 
   The CAS latency (CL) is the ratio between column access time and a clock cycle time. That is, the CL shows how many cycles of the external clock signal are spent while performing a read operation of a semiconductor memory device. For instance, in case that the CL is 3, if a read command is inputted, a data corresponding to the read command is outputted from a memory cell array after 3 cycles of the external clock signal. Therefore, at an initial state of the synchronous semiconductor memory device, the CL is detected by the synchronous semiconductor memory device and is used for outputting a data. 
   Meanwhile, the data outputted from the memory cell array is stored in a data output buffer. Then, the data stored in the data output buffer is finally outputted from the synchronous semiconductor memory device in response to an activated data output enable signal. The data output enable signal is generated by delaying a read command performing signal for a time period corresponding to the CL, wherein the read command performing signal is generated in response to the read command. Therefore, the synchronous semiconductor memory device activates the data output enable signal after time of the CL is passed. 
   Herein, the synchronous semiconductor memory device uses an internal operating clock signal which is outputted from a delay locked loop (DLL). When the external clock signal is inputted to the synchronous semiconductor memory device in order to be used as the internal operating clock signal, there occurs a time error between the external clock signal and the internal operating clock signal. Therefore, the DLL is applied to the synchronous semiconductor memory device for synchronizing the internal operating clock signal with the external clock signal. 
     FIG. 1  is a block diagram showing a conventional synchronous semiconductor memory device. 
   As shown, the conventional synchronous semiconductor memory device includes an input buffer  10 , a command decoder  20 , a read operation timing control unit  30 , a data output control unit  40 , a data output buffer  50 , a data output pad (DQ pad)  60 , a delay locked loop (DLL)  70  and a memory core block  80 . 
   The input buffer  10  receives a plurality of command signals such as a chip selection bar signal /CS, a row address strobe bar signal /RAS, a column address strobe bar signal /CAS and a write enable bar signal /WE for buffering and outputting those plurality of command signals. The command decoder  20  receives the plurality of command signals from the input buffer  10  for decoding the plurality of command signals and, thus, to output a control signal such as a read command signal rd. 
   The read operation timing control unit  30  receives the read command signal rd for generating a read command performing signal casp — rd which corresponds to the read command signal rd. There is a predetermined time difference between a timing of receiving the read command signal rd and a timing of generating the read command performing signal casp — rd. The predetermined time difference corresponds to clock cycles of a clock signal iclk, where the clock cycles of the clock signal iclk is an additive latency (AL). 
   Herein, the AL is the number of spent clock cycles of the clock signal iclk while a tRCD (RAS to CAS delay) is passed after the read command signal rd is inputted to the read operation timing control unit  30 . The tRCD is a time difference between an input timing of a row address and an input timing of a column address. 
   When the row address is inputted, the conventional synchronous semiconductor memory device is activated, and, then, the column address is inputted after the tRCD is passed. However, the read command signal rd is inputted prior to the column address after the row address is inputted. That is, the AL is a time difference between an input timing of the read command signal rd and an input timing of the column address. 
   The memory core block  80  outputs a data to the data output buffer  50  in response to the read command performing signal casp — rd, where the data inputted to the data output buffer  50  corresponds to an address signal addr. 
   The DLL  70  generates two delay locked clock signals, i.e., a delay locked falling edge clock signal fclk — dll and a delay locked rising edge clock signal rclk — dll by delay locking the clock signal iclk. The delay locked falling edge clock signal fclk — dll and the delay locked rising edge clock signal rclk — dll are used for a data to be outputted from the conventional synchronous semiconductor memory device synchronizing with a falling edge and a rising edge of an external clock signal. 
   The data output control unit  40  receives the read command performing signal casp — rd, the clock signal iclk, the delay locked falling edge clock signal fclk — dll and the delay locked rising edge clock signal rclk — dll for generating two data output enable signals, i.e., a rising data output enable signal routen and a falling data output enable signal fouten. 
   Herein, prior to outputting the rising data output enable signal routen and the falling data output enable signal fouten, there is a delay time corresponding to the CL. That is, after the data output control unit  40  receives the read command performing signal casp — rd, the rising data output enable signal routen and the falling data output enable signal fouten are outputted from the data output control unit  40  after the delay time corresponding to the CL is passed. 
   Herein, when the rising data output enable signal routen and the falling data output enable signal fouten are outputted, they are synchronized with the delay locked rising edge clock signal rclk — dll and the delay locked falling edge clock signal fclk — dll. The rising data output enable signal routen and the falling data output enable signal fouten respectively serve to output the data synchronously with a rising edge of the clock signal iclk and a falling edge of the clock signal iclk. 
   The data output buffer  50  receives the data from the memory core block  80  for outputting the received data to the D 0  pad in response to the rising data output enable signal routen and the falling data output enable signal fouten. 
     FIG. 2  is a block diagram showing the data output control unit  40  shown in  FIG. 1 . 
   As shown, the data output control unit  40  includes an internal signal generating unit  41 , a first signal shift unit  42 , a second signal shift unit  43 , a rising data output control unit  44  and a falling data output control unit  45 . 
   The internal signal generating unit  41  receives the read command performing signal casp — rd for generating an internal signal oe 00  by synchronizing the read command performing signal casp — rd with the clock signal iclk. 
   The first signal shift unit  42  receives the internal signal oe 00  and the delay locked rising edge clock signal rclk — dll for shifting the internal clock signal oe 00  synchronizing with the delay locked rising edge clock signal rclk — dll, whereby the first signal shift unit  42  outputs a first, a second, a third and a fourth shifted delay locked rising edge clock signals oe 10   — dll, oe 20   — dll, oe 30   — dll and oe 40   — dll. 
   That is, the internal signal oe 00  is synchronized with a first to a fourth rising edges of the delay locked rising edge clock signal rclk — dll to be respectively outputted as the first to the fourth shifted delay locked rising edge clock signals oe 10   — dll to oe 40   — dll. 
   Likewise, the second signal shift unit  43  receives the internal signal oe 00  and the delay locked falling edge clock signal fclk — dll for shifting the internal clock signal oe 00  synchronizing with the delay locked falling edge clock signal fclk — dll, whereby the second signal shift unit  43  outputs a first, a second, a third and a fourth shifted delay locked rising edge clock signals oe 15   — dll, oe 25   — dll, oe 35   — dll and oe 45   — dll. 
   That is, the internal clock signal oe 00  is synchronized with a first to a fourth rising edges of the delay locked falling edge clock signal fclk — dll to be respectively outputted as the first to the fourth shifted delay locked falling edge clock signals oe 15   — dll to oe 45   — dll. 
   The rising data output control unit  44  receives the first to the fourth shifted delay locked rising edge clock signals oe 10   — dll to oe 40   — dll for outputting one of the received signals as the rising data output enable signal routen depending on the CL. For instance, if the CL is 2, the first shifted delay locked rising edge clock signal oe 10   — dll is outputted as the rising data output enable signal routen. Likewise, if the CL is 3, 4 or 5, the second, the third or the fourth shifted delay locked rising edge clock signal oe 20   — dll, oe 30   — dll or oe 40   — dll is respectively outputted as the rising data output enable signal routen. 
   Likewise, falling data output control unit  45  receives the first to the fourth shifted delay locked falling edge clock signals oe 15   — dll to oe 45   — dll for outputting one of the received signals as the falling data output enable signal fouten depending on the CL. That is, if the CL is 2, 3, 4 or 5, the first, the second, the third or the fourth shifted delay locked falling edge clock signal oe 15   — dll, oe 25   — dll, oe 35   — dll or oe 45   — dll is respectively outputted as the falling data output enable signal fouten. 
     FIG. 3  is a schematic circuit diagram showing the first signal shift unit  42  shown in  FIG. 2 . 
   As shown, the first signal shift unit  42  includes a first to a fourth D-type flip-flops F 1  to F 4 . 
   Each clock input terminal of the first to the fourth D-type flip-flops receives the delay locked rising edge clock signal rclk — dll. The first D-type flip-flop F 1  receives the internal signal oe 00  through its data input terminal for outputting the first shifted delay locked rising edge clock signal oe 10   — dll through its main output terminal. An output signal from a sub output terminal of the first D-type flip-flop F 1  is inputted to a data input terminal of the second D-type flip-flop F 2 , and the second D-type flip-flop F 2  outputs the second shifted delay locked rising edge clock signal oe 20   — dll through its main output terminal. 
   Likewise, output signals from sub output terminals of the second and the third D-type flip-flops F 2  and F 3  are respectively inputted to data input terminals of the third and the fourth D-type flip-flop F 3  and F 4 , and the third and the fourth D-type flip-flops F 3  and F 4  output the third and the fourth shifted delay locked rising edge clock signals oe 30   — dll and oe 40   — dll. 
   Herein, the second signal shift unit  43  has the same structure as that of the first signal shift unit  42 . Therefore, detailed description of the second signal shift unit  43  is omitted. 
     FIG. 4  is a timing diagram showing an operation of the data output control unit  40  shown in  FIG. 2 . 
   The operation of the data output control unit  40  is described below referring to  FIGS. 1 to 4 . 
   The internal signal generating unit  41  receives the read command performing signal casp — rd for generating the internal signal oe 00  by synchronizing the read command performing signal casp — rd with the clock signal iclk. 
   Thereafter, the first signal shift unit  42  receives the internal signal oe 00  and the delay locked rising edge clock signal rclk — dll for generating the first to the fourth shifted delay locked rising edge clock signals oe 10   — dll to oe 40   — dll by synchronizing the internal signal oe 00  with four consecutive rising edges of the delay locked rising edge clock signal rclk — dll. 
   Then, the rising data output control unit  44  receives the first to the fourth shifted delay locked rising edge clock signals oe 10   — dll to oe 40   — dll and selects one of the received signals depending on the CL for outputting the selected signal as the rising data output enable signal routen. 
   Meanwhile, the second signal shift unit  43  and the falling data output control unit  45  perform the same operations of the first signal shift unit  42  and the rising data output control unit  44  in order to output the falling data output enable signal fouten. 
   As described above, the rising data output enable signal routen and the falling data output enable signal fouten are important signals which determine a timing of outputting data. Since the DDR synchronous semiconductor memory device performs the data access operation at both edges of a clock signal, the DDR synchronous semiconductor memory device should be provided with a rising data output control unit and a falling data output control unit for generating the rising data output enable signal and the falling data output enable signal respectively. 
   Therefore, size of a data output control circuit is increased and power consumption is also increased. 
   SUMMARY OF INVENTION 
   It is, therefore, an object of the present invention to provide a data output control circuit capable of generating a rising data output enable signal and a falling data output enable signal for reducing power consumption and for decreasing size of a synchronous semiconductor memory device. 
   In accordance with an aspect of the present invention, there is provided a data output control circuit for use in a synchronous semiconductor memory device including: a first data output enable signal generation unit for receiving an internal signal and generating a rising data output enable signal synchronizing with a rising edge of a DLL clock signal according to a CAS latency; and a second data output enable signal generation unit for receiving the rising data output enable signal and generating a falling data output enable signal synchronizing with a falling edge of the DLL clock signal. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The above and other objects and features of the present invention will become apparent from the following description of preferred embodiments taken in conjunction with the accompanying drawings, in which: 
       FIG. 1  is a block diagram showing a conventional synchronous semiconductor memory device; 
       FIG. 2  is a block diagram showing a data output control unit shown in  FIG. 1 ; 
       FIG. 3  is a schematic circuit diagram showing a first signal shift unit shown in  FIG. 2 ; 
       FIG. 4  is a timing diagram showing an operation of a data output control unit shown in  FIG. 2 ; 
       FIG. 5  is a block diagram showing a data output control circuit in accordance with a preferred embodiment of the present invention; 
       FIG. 6  is a schematic circuit diagram showing a signal shift unit shown in  FIG. 5 ; and 
       FIG. 7  is a block diagram showing a falling data output control unit shown in  FIG. 5 . 
   

   DETAILED DESCRIPTION OF INVENTION 
   Hereinafter, a data output control circuit for use in a synchronous semiconductor memory device in accordance with the present invention will be described in detail referring to the accompanying drawings. 
     FIG. 5  is a block diagram showing a data output control circuit in accordance with a preferred embodiment of the present invention. 
   As shown, the data output control circuit includes an internal signal generating unit  400 , a rising data output control unit  200  and a falling data output control unit  100 . 
   The internal signal generating unit  400  receives a read command performing signal casp — rd and a clock signal iclk for generating an internal signal oe 00  by synchronizing the read command performing signal casp — rd with the clock signal iclk. 
   The rising data output control unit  200  receives the internal signal oe 00  and a delay locked rising edge clock signal rclk — dll for generating a rising data output enable signal routen in response to a CAS latency (CL). 
   Likewise, the falling data output control unit  100  receives a primitive rising data output enable signal pri — routen from the rising data output control unit  200  and also receives a delay locked falling edge clock signal fclk — dll for generating a falling data output enable signal fouten. 
   The two data output enable signals, i.e., the rising data output enable signal routen and the falling data output enable signal fouten, are used as control signals for a data output buffer to output data. 
   Meanwhile, the rising data output control unit  200  includes a signal shift unit  210 , a signal selection unit  220  and a first buffering unit  230 . 
   The signal shift unit  210  receives the internal signal oe 00  and the delay locked rising edge clock signal rclk — dll for shifting the internal clock signal oe 00  synchronizing with the delay locked rising edge clock signal rclk — dll, whereby to output a first, a second, a third and a fourth shifted delay locked rising edge clock signals oe 10   — dll, oe 20   — dll, oe 30   — dll and oe 40   — dll. 
   That is, the internal signal oe 00  is synchronized with a first to a fourth rising edges of the delay locked rising edge clock signal rclk — dll to be respectively outputted as the first to the fourth shifted delay locked rising edge clock signals oe 10   — dll to oe 40   — dll. 
   The signal selection unit  220  includes a plurality of inverters and a plurality of transferring gates T 9  to T 12  for selecting one of the shifted delay locked rising edge clock signals oe 10   — dll to oe 40   — dll and for outputting the selected signal as the primitive rising data output enable signal pri — routen depending on the CL. 
   That is, one of the plurality of transferring gates T 9  to T 12  is turned on depending on the CL, and one of the shifted delay locked rising edge clock signals oe 10   — dll to oe 40   — dll which is connected to the turn-on transferring gate is outputted as the primitive rising data output enable signal pri — routen. For instance, if the CL is 2, the transferring gate T 9  is turned on; and, thus, the shifted delay locked rising edge clock signal oe 10   — dll is outputted as the primitive rising data output enable signal pri — routen. 
   The first buffering unit  230  includes two inverters I 5  and I 6  for receiving the primitive rising data output enable signal pri — routen. The first buffering unit  230  outputs the received primitive rising data output enable signal pri — routen as the rising data output enable signal routen after buffering the primitive rising data output enable signal pri — routen. 
     FIG. 6  is a schematic circuit diagram showing the signal shift unit  210  shown in  FIG. 5 . 
   As shown, the signal shift unit  210  includes a first to a fourth D-type flip-flops F 5  to F 8 . 
   Each clock input terminal of the first to the fourth D-type flip-flops receives the delay locked rising edge clock signal rclk — dll. The first D-type flip-flop F 5  receives the internal signal oe 00  through its data input terminal for outputting the first shifted delay locked rising edge clock signal oe 10   — dll through its main output terminal. An output signal from a sub output terminal of the first D-type flip-flop F 5  is inputted to a data input terminal of the second D-type flip-flop F 6 , and the second D-type flip-flop F 6  outputs the second shifted delay locked rising edge clock signal oe 20   — dll through its main output terminal. 
   Likewise, output signals from sub output terminals of the second and the third D-type flip-flops F 6  and F 7  are respectively inputted to data input terminals of the third and the fourth D-type flip-flops F 7  and F 8 , and the third and the fourth D-type flip-flops F 7  and F 8  output the third and the fourth shifted delay locked rising edge clock signals oe 30   — dll and oe 40   — dll. 
     FIG. 7  is a block diagram showing the falling data output control unit  100  shown in  FIG. 5 . 
   As shown, the falling data output control unit  100  includes a delay unit  110 , a clock synchronizing unit  120  and a second buffering unit  130 . 
   The delay unit  110  delays the delay locked falling edge clock signal fclk — dll for a predetermine delay time and outputs the delayed signal as a delayed delay locked falling edge clock signal fclk — dll — delay. Herein, the predetermined delay time is equal to a delay time which is spent while the delay locked rising edge clock signal rclk — dll is passed through the signal shift unit  210  and the signal selection unit  220 . 
   The delay unit  110  includes two transferring gates T 13  and T 14  for delaying the delay locked falling edge clock signal fclk — dll for a first delay time which is spent while the delay locked rising edge clock signal rclk — dll is passed through the signal selection unit  220 , and the delay unit  110  also includes two inverters I 7  and I 8  for delaying the delay locked falling edge clock signal fclk — dll for a second delay time which is spent while the delay locked rising edge clock signal rclk — dll is passed through the signal shift unit  210 . 
   The clock synchronizing unit  120  receives the primitive rising data output enable signal pri — routen and the delayed delay locked falling edge clock signal fclk — dll — delay for generating a primitive falling data output enable signal pri — fouten by synchronizing the primitive rising data output enable signal pri — routen with the delayed delay locked falling edge clock signal fclk — dll — delay. 
   The second buffering unit  130  receives and buffers the primitive falling data output enable signal pri — fouten to output the falling data output enable signal fouten. 
   An operation of the data output control circuit in accordance with the preferred embodiment of the present invention is described below referring to  FIGS. 5 to 7 . 
   The internal signal generating unit  400  generates the internal signal oe 00  by synchronizing the read command performing signal casp — rd with the clock signal iclk. 
   Thereafter, the signal shift unit  210  shifts the internal clock signal rclk — dll by synchronizing the internal signal oe 00  with consecutive four rising edges of the delay locked rising edge clock signal rclk — dll to thereby output the first to the fourth shifted delay locked rising edge clock signals oe 10   — dll to oe 40   — dll. 
   Thereafter, the signal selection unit  220  receives the first to the fourth shifted delay locked rising edge clock signals oe 10   — dll to oe 40   — dll and selects one of the received signals depending on the CL to thereby output the selected signal as the primitive rising data output enable signal pri — routen. 
   The buffering unit  230  receives the primitive rising data output enable signal pri — routen and outputs the received primitive rising data output enable signal pri — routen as the rising data output enable signal routen after buffering the primitive rising data output enable signal pri — routen. 
   Meanwhile, the falling data output control unit  100  receives the primitive rising data output enable signal pri — routen and the delay locked falling edge clock signal fclk — dll for delaying the delay locked falling edge clock signal fclk — dll for the predetermined delay time; and, thus, to output the delayed delay locked falling edge clock signal fclk — dll — delay. Then, the falling data output control unit  100  synchronizes the primitive rising data output enable signal pri — routen with the delayed delay locked falling edge clock signal fclk — dll — delay to output the falling data output enable signal fouten. 
   Herein, the falling data output control unit  100  includes the delay unit  110 , the clock synchronizing unit  120  and the second buffering unit  130 . 
   The delay unit  110  delays the delay locked falling edge clock signal fclk — dll for the predetermined delay time which is spent while the delay locked rising edge clock signal rclk — dll is passed through the signal shift unit  210  and the signal selection unit  220 , whereby the delay unit  110  outputs the delayed signal as the delayed delay locked falling edge clock signal fclk — dll — delay. 
   The clock synchronizing unit  120  receives the primitive rising data output enable signal pri — routen and the delayed delay locked falling edge clock signal fclk — dll — delay for generating the primitive falling data output enable signal pri — fouten by synchronizing the primitive rising data output enable signal pri — routen with the delayed delay locked falling edge clock signal fclk — dll — delay. 
   Thereafter, the second buffering unit  130  receives and buffers the primitive falling data output enable signal pri — fouten to output the falling data output enable signal fouten. 
   As described above, since the data output control circuit generates the falling data output enable signal fouten using the rising data output enable signal routen, a circuit block for generating the falling data output enable signal, i.e., the falling data output control unit  100  is not required to include a plurality of flip-flops or a plurality of transferring gates. 
   As a result, a semiconductor memory device can reduce its size and power consumption using the data output control circuit in accordance with the present invention. 
   The present application contains subject matter related to Korean patent application No. 2003-76835, filed in the Korean Patent Office on Oct. 31, 2003, the entire contents of which being incorporated herein by reference. 
   While the present invention has been described with respect to the particular embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.