Patent Publication Number: US-7584314-B1

Title: Universal serial-to-parallel and parallel-to-serial cable interface and method

Description:
TECHNICAL FIELD 
   This disclosure is generally directed to cable interfaces and more specifically to a universal cable interface and method. 
   BACKGROUND 
   Many different electronic devices are coupled to cables that carry electrical signals during operation. For example, broadcast video equipment is often coupled to coaxial cables or other cables capable of transporting video and audio signals. In the broadcast video industry, there are many different types of products, although often times there may be a relatively low volume of a particular product in actual use. As a result, equipment designers often need to design a product with the maximum amount of flexibility. A proposed new product can, for example, take advantage of the flexibility inherent in a field programmable gate array (FPGA). However, the proposed new product often has a very inflexible part of its design, namely its cable interface. 
   Today, there are specialized serializers (transmitters) and deserializers (receivers) for standard definition and high definition video content. This often makes it necessary for equipment manufacturers to design and build multiple specialized boards for a single product. Multiple boards are often needed to satisfy all of the various possible uses, such as different boards for different functions (like time code inserters, logo inserters, and format converters) and different content (like standard definition and high definition). Moreover, this often requires the use of more powerful or expensive FPGAs in a product since the FPGAs may, in some circumstances, be required to perform analog processing functions. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     For a more complete understanding of this disclosure and its features, reference is now made to the following description, taken in conjunction with the accompanying drawings, in which: 
       FIG. 1  illustrates an example universal cable interface; 
       FIGS. 2 and 3  illustrate example configurations of the universal cable interface of  FIG. 1 ; 
       FIG. 4  illustrates an example device for transmitting or receiving signals using a universal cable interface; and 
       FIG. 5  illustrates an example method for transmitting or receiving signals using a universal cable interface. 
   

   DETAILED DESCRIPTION 
     FIGS. 1 through 5 , discussed below, and the various embodiments used to describe the principles of the present invention in this patent document are by way of illustration only and should not be construed in any way to limit the scope of the invention. Those skilled in the art will understand that the principles of the invention may be implemented in any type of suitably arranged device or system. 
     FIG. 1  illustrates an example universal cable interface  100 . The universal cable interface  100  could, for example, be used in video equipment or other equipment for coupling a coaxial cable or other connector to the equipment. The embodiment of the universal cable interface  100  shown in  FIG. 1  is for illustration only. Other embodiments of the universal cable interface  100  could be used without departing from the scope of this disclosure. 
   In one aspect of operation, the universal cable interface  100  supports a universal interface between a cable (such as a coaxial cable) and a host processing device (such as an FPGA). This means the universal cable interface  100  can be configured as an input or an output, and the universal cable interface  100  could be configured to handle standard definition (SD) video signals and high definition (HD) video signals. This may allow equipment manufacturers to design a product with one or multiple universal cable interfaces  100  and an FPGA or other processing device, and the FPGA or other processing device can be programmed to define the product&#39;s function at a later time. This may allow equipment manufacturers to manufacture products in higher volumes, which may provide a cost savings over conventional design techniques. Also, because of the design of the universal cable interface  100 , equipment manufacturers may be able to use less complex or less powerful (and therefore less expensive) FPGAs or other processing devices since some or all analog functionality can be offloaded into the universal cable interface  100 . 
   As shown in  FIG. 1 , the universal cable interface  100  includes a cable equalizer  102 . The equalizer  102  is capable of equalizing data received over a cable, such as a coaxial cable or other media exhibiting dispersive loss characteristics. The equalizer  102  could receive and equalize standard definition or high definition video signals. The equalizer  102  could operate on data having a range of data rates, such as 143 megabits per second (Mbps) to 2.97 gigabits per second (Gbps). The equalizer  102  could also support any suitable standard related to video signals, such as the Society of Motion Picture and Television Engineers (SMPTE) 292M, 344M, 259M, and 424M standards. The equalizer  102  represents any suitable device or component capable of equalizing data. The equalizer  102  could, for example, represent an LMH0034 adaptive cable equalizer from NATIONAL SEMICONDUCTOR CORPORATION. 
   The output of the equalizer  102  is provided to a multiplexer  104 , which can also receive a second input. The multiplexer  104  selects one of the two inputs for output to a reclocker  106 . The specific input selected by the multiplexer  104  could be determined based on whether the universal cable interface  100  is being used as an input or an output. The multiplexer  104  represents any suitable device or component for selecting one of multiple inputs for output. 
   The reclocker  106  performs clock and data recovery on received serial data, such as by extracting a clock signal from the serial data. The clock signal could then be used in any suitable manner, such as to suppress accumulated jitter in the serial data. The reclocker  106  can operate on any suitable data, such as data conforming to the SMPTE 259M (A and C), SMPTE 292M, and SMPTE 424M standards at rates of 143 Mbps, 270 Mbps, 1.483 Gbps, 1.485 Gbps, and 2.97 Gbps. In this example, the reclocker  106  has two outputs. The upper output may represent the serial data, which could be provided via two differential outputs. The lower output may represent a low-jitter, serial data rate clock recovered by the reclocker  106 . The reclocker  106  represents any suitable device or component for performing clock and data recovery, such as an LMH0046 HD/SD Serial Digital Interface (SDI) reclocker with dual differential outputs from NATIONAL SEMICONDUCTOR CORPORATION. 
   The serial data from the reclocker  106  can be provided to a cable driver  108 . The cable driver  108  drives the cable or other transmission medium that is coupled to the equalizer  102 . The cable driver  108  could, for example, drive a 75Ω transmission line at rates up to 1.485 Gbps. The cable driver  108  could also support multiple slew rates for SMPTE 259M, SMPTE 292M, and SMPTE 424M compliance. The cable driver  108  represents any suitable device or component for driving a transmission line, such as an LMH0002 serial digital cable driver from NATIONAL SEMICONDUCTOR CORPORATION. 
   The serial data from the reclocker  106  can also be provided to a serial-to-parallel converter  110 . The converter  110  receives serial data from the reclocker  106  and converts the data into a parallel format. For example, the converter  110  could convert serial data into 4-bit or 5-bit parallel values. The converter  110  represents any suitable device or component for converting serial data into parallel data. The parallel data generated by the converter  110  could be provided to any suitable destination, such as an FPGA or other host processing device. By converting the serial data into a parallel format, the deserialization may reduce the data rate to a lower speed, allowing the data to be handled by a less powerful or lower cost FPGA or other host processing device. 
   The clock recovered by the reclocker  106  can be provided to the serial-to-parallel converter  110  and to a clock multiplier/divider  112 . The clock multiplier/divider  112  can also receive a clock signal from an external source, such as an FPGA or other host processing device. The clock multiplier/divider  112  then multiplies or divides the received clock signal, such as by multiplying or dividing the received clock signal by four or five. Whether the clock multiplier/divider  112  multiplies or divides the received clock signal may depend on whether the universal cable interface  100  is used as an input or an output. The clock multiplier/divider  112  represents any suitable device or component for multiplying or dividing a clock signal. By performing the clock multiplication or division in the universal cable interface  100 , the FPGA or other host processing device need not perform this function, which may again allow the use of a less powerful or lower cost FPGA or other host processing device. 
   The universal cable interface  100  also includes a parallel-to-serial converter  114 . The converter  114  receives parallel data from an external source (such as an FPGA or other host processing device) and converts the data into a serial format. For example, the converter  114  could convert 4-bit or 5-bit parallel data into serial format. The serial data generated by the converter  114  is provided to the multiplexer  104 , which selects either the equalized data from the equalizer  102  or the serialized data from the converter  114  for output to the reclocker  106 . The converter  114  represents any suitable device or component for converting parallel data into serial data. 
   A controller  116  controls the overall operation of the universal cable interface  100 . For example, the controller  116  can control the multiplexer  104  to control which data is provided to the reclocker  106 . The controller  116  could also configure certain components, such as by configuring the clock multiplier/divider  112  as a multiplier or a divider. In addition, the controller  116  could enable certain components and disable other components. These actions could be based on whether the universal cable interface  100  is being used as an input or an output. The controller  116  includes any hardware, software, firmware, or combination thereof for controlling the universal cable interface  100 . 
   As described above, depending on the configuration of the universal cable interface  100 , the universal cable interface  100  can function as an interface between a cable carrying data (such as SDI data) and a host processing device (such as an FPGA). The universal cable interface  100  can operate as an input or an output and handle standard definition or high definition video data. Because of this, the universal cable interface  100  could be used in a wide variety of applications. For example, it could be used in devices such as switchers or camcorders, which traditionally require parallel data communication. The universal cable interface  100  could also be used in applications such as a small-medium router, where an FPGA could replace a crosspoint switch normally used in the router. The universal cable interface  100  could represent a single component that can be used in any interface (input or output). 
     FIGS. 2 and 3  illustrate example configurations of the universal cable interface  100  of  FIG. 1 . More specifically,  FIG. 2  illustrates the universal cable interface  100  configured in receive (input) mode, and  FIG. 3  illustrates the universal cable interface  100  configured in transmit (output) mode. 
   As shown in  FIG. 2 , in the receive or input mode, an input signal is brought in through the equalizer  102  and provided to the reclocker  106  via the multiplexer  104 . The output of the reclocker  106  is supplied to the cable driver  108 , providing an active loopthrough (a buffered or delayed version of the input signal). The output of the reclocker  106  is also supplied to the serial-to-parallel converter  110  for conversion to a parallel format. The recovered clock from the reclocker  106  is provided to the serial-to-parallel converter  110  and to the clock multiplier/divider  112  (which in this configuration is operating as a clock divider). The clock multiplier/divider  112  slows the rate of the recovered clock provided by the reclocker  106 , such as by slowing the rate to one-fourth or one-fifth of the original rate. If the input signal is a high definition signal, this could slow the data rate to approximately 400 Mbps. The lower-rate data and the clock could be provided to a host processing device, such as a low-end FPGA (Spartan or Cyclone), and the remainder of the processing could be done within the host processing device. 
   As shown in  FIG. 3 , in the transmit or output mode, parallel data is received by the parallel-to-serial converter  114  and converted into serial data. An input clock signal is received by the clock multiplier/divider  112  (which in this example is configured as a multiplier), and the clock multiplier/divider  112  increases the rate of the clock signal (such as by multiplying the clock rate by four or five). The multiplied clock signal is provided to the parallel-to-serial converter  114  for use in converting the parallel data into serial data. The serialized data is provided to the reclocker  106  via the multiplexer  104 , and the reclocker  106  reclocks the data. This may be helpful, for example, in removing any requirements for a very pure clock coming from the FPGA or other host processing device. The reclocked data is then sent out through the cable driver  108 . 
   In some embodiments, the converters  110  and  114  share the same inputs/outputs (such as a set of input/output pins). When the universal cable interface  100  is configured as a receiver (input mode), the serial-to-parallel converter  110  provides parallel data to an FPGA or other host processing device via the input/output pins. When the universal cable interface  100  is configured as a transmitter (output mode), the parallel-to-serial converter  114  receives parallel data from an FPGA or other host processing device via the input/output pins. 
   In particular embodiments, the equalizer input and the cable driver output might be connected outside of a package containing the universal cable interface  100 . This could cause a loss of the loopthrough function while still allowing the universal cable interface  100  to be used as an input or an output. 
   Based on the above-described functionality, the universal cable interface  100  may be used to implement a cable interface in video or other equipment. Moreover, the universal cable interface  100  could be used in various parallel devices or to implement conventional serial devices as parallel devices. For example, to design an 8×8 router, it might ordinarily require eight equalizers, eight reclockers, eight cable drivers, and an 8×8 crosspoint switch. Based on this disclosure, sixteen universal cable interfaces  100  could be tied to a small FPGA programmed to implement the crosspoint functionality. To implement a 12×4 router, the exact same design could be used by changing the configuration of the universal cable interfaces  100  (converting four outputs into inputs) via software, rather than redesigning the 8×8 router. Designers could design truly modular products, with the only design question being how many universal cable interfaces  100  are required in a product. Given that, the designer could design a product, and its functionality (such as distribution amplifier, mixer, or logo inserter functionality) could be programmed after the product is assembled. 
   An example use of the universal cable interface  100  is shown in  FIG. 4 .  FIG. 4  illustrates an example device  400  for transmitting or receiving signals using one or more universal cable interfaces  100 . In this example, the device  400  includes a host processing device  402  (such as an FPGA) coupled to multiple universal cable interfaces  100 . Each of the universal cable interfaces  100  is coupled to a cable, such as a coaxial cable or other transmission medium. In this example, the device  400  could be configured as a router, where the host processing device  402  is used to transport data between different universal cable interfaces  100 . The exact number of inputs and outputs of the router is easily configurable by adjusting one or more of the universal cable interfaces  100 . The same device  400  could be used to perform other functions by configuring the universal cable interfaces  100  and programming the host processing device  402  appropriately. 
   Although  FIGS. 1 through 4  illustrate an example universal cable interface  100 , example configurations of the universal cable interface  100 , and an example use of the universal cable interface  100 , various changes could be made to  FIGS. 1 through 4 . For example, the universal cable interface  100  could include any other or additional components based on particular needs. Also, various components in the universal cable interface  100  could be combined or further subdivided. In addition, any suitable device could use the universal cable interface  100 . 
     FIG. 5  illustrates an example method  500  for transmitting or receiving signals using a universal cable interface. The embodiment of the method  500  shown in  FIG. 5  is for illustration only. Other embodiments of the method  500  could be used without departing from the scope of this disclosure. Also, for ease of explanation, the method  500  is described with respect to the universal cable interface  100  of  FIG. 1  configured as shown in  FIGS. 2 and 3 . The method  500  could be used with any suitable device in any suitable configuration. 
   A cable is coupled to a universal cable interface at step  502 . This could include, for example, coupling a coaxial cable or other transmission medium to the universal cable interface  100 . The cable can be connected to the universal cable interface  100  in any suitable manner, such as by using a BNC connector (for a coaxial cable). 
   A determination is made whether the universal cable interface is used as an input or an output at step  504 . This could include, for example, the controller  116  in the universal cable interface  100  determining whether the universal cable interface  100  has been configured to operate as an input or an output. 
   If configured to operate as an input, data and clock signals are received via the cable at step  506 . The data may represent serial data, such as serial standard definition or high definition video data, from any suitable source. The data is equalized at step  508 . This could include, for example, the equalizer  102  in the universal cable interface  100  receiving and equalizing the serial data. The data is reclocked at step  510 . This could include, for example, the reclocker  106  receiving the equalized serial data via the multiplexer  104  and reclocking the serial data to remove any accumulated jitter. An active loopthrough of the serial data is provided at step  512 . This could include, for example, providing the equalized serial data to the cable driver  108  for output. The reclocked data is deserialized and output in parallel format at step  514 . This could include, for example, the serial-to-parallel converter,  110  converting the reclocked data into a parallel format and outputting the parallel data to an FPGA or other processing device or destination. A recovered clock signal is divided and output at step  516 . This could include, for example, the clock multiplier/divider  112  dividing the clock signal by four or five and outputting the divided clock signal to the FPGA or other processing device or destination. In these steps, the controller  116  could take any necessary actions to ensure the universal cable interface  100  is configured appropriately. This could include setting the multiplexer  104  to provide the output of the equalizer  102  to the reclocker  106  and configuring the clock multiplier/divider  112  to divide the clock signal received from the reclocker  106 . 
   If configured to operate as an output, data and clock signals are received at step  518 . The data may represent parallel data, such as parallel data from an FPGA or other processing device or other source. The clock signal is multiplied and output at step  520 . This could include, for example, the clock multiplier/divider  112  multiplying the clock signal by four or five and outputting the clock signal to the parallel-to-serial converter  114 . The received data is serialized at step  522 . This could include, for example, the parallel-to-serial converter  114  converting the received data into a serial format and outputting the serial data to the multiplexer  104 . The serialized data is reclocked at step  524 . This could include, for example, the reclocker  106  receiving the serialized data via the multiplexer  104  and reclocking the serialized data. The reclocked data is then output at step  526 . This could include, for example, outputting the reclocked serial data over a cable via the cable driver  108 . In these steps, the controller  116  could again take any necessary actions to ensure the universal cable interface  100  is configured appropriately. This could include setting the multiplexer  104  to provide the output of the parallel-to-serial converter  114  to the reclocker  106  and configuring the clock multiplier/divider  112  to multiply the clock signal received from an external source. 
   Although  FIG. 5  illustrates one example of a method  500  for transmitting or receiving signals using a universal cable interface, various changes may be made to  FIG. 5 . For example, the universal cable interface  100  could be defined as an input or output and configured appropriately prior to execution of the method  500 , and step  504  might not involve any actual determinations made by the universal cable interface  100 . Also, while shown as a series of steps, various steps in  FIG. 5  could overlap or occur in parallel. 
   It may be advantageous to set forth definitions of certain words and phrases that have been used within this patent document. The term “couple” and its derivatives refer to any direct or indirect communication between two or more components, whether or not those components are in physical contact with one another. The terms “transmit,” “receive,” and “communicate,” as well as derivatives thereof, encompass both direct and indirect communication. The terms “include” and “comprise,” as well as derivatives thereof, mean inclusion without limitation. The term “or” is inclusive, meaning and/or. The phrases “associated with” and “associated therewith,” as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, be bound to or with, have, have a property of, or the like. The term “controller” means any device, system, or part thereof that controls at least one operation. A controller may be implemented in hardware, firmware, software, or some combination of at least two of the same. The functionality associated with any particular controller may be centralized or distributed, whether locally or remotely. 
   While this disclosure has described certain embodiments and generally associated methods, alterations and permutations of these embodiments and methods will be apparent to those skilled in the art. Accordingly, the above description of example embodiments does not define or constrain this invention. Other changes, substitutions, and alterations are also possible without departing from the spirit and scope of this invention as defined by the following claims.