Patent Publication Number: US-2019199333-A1

Title: Semiconductor device

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     The disclosure of Japanese Patent Application No. 2017-245271 filed on Dec. 21, 2017 including the specification, drawings and abstract is incorporated herein by reference in its entirety. 
     BACKGROUND 
     The present disclosure relates to techniques that are effective when applied to a semiconductor device, for example, a circuit with a parallel interface. 
     With the advancement in information processing technology, semiconductor devices capable of achieving high speed and low power consumption are becoming more popular. 
     In such semiconductor devices, for example, there is known technology relating to semiconductor storage devices based on data strobe signal (DQS) to achieve high speed data communication. 
     As examples of semiconductor storage devices based on data strobe signal (DQS), there are semiconductor storage devices with a data transfer rate of Gbps band, such as, for example, DDR4 SDRAM (Double Data Rate 4 Synchronous DRAM). 
     In general, a memory interface is provided between such a high speed semiconductor storage device and a central processing unit (CPU). 
     In this regard, a technique is disclosed that performs calibration of synchronous timing due to the fluctuation of data (Patent Document 1: Japanese Unexamined Patent Application Publication No. 2010-86246). 
     SUMMARY 
     On the other hand, in the case of parallel interface, there is a possibility that signal delay may occur due to the influence of crosstalk between adjacent signal lines. This signal delay causes a deviation of synchronous timing and so is an important problem in achieving high speed. 
     The present disclosure has been made to solve the above problem and an object thereof is to provide a semiconductor device capable of achieving stable data communication with a simple method. 
     Other objects and novel features will be apparent from the description of the present specification and the accompanying drawings. 
     A semiconductor device according to an aspect of the present disclosure includes a plurality of signal lines, as well as a driver circuit provided corresponding to the signal lines to transmit a plurality of data in parallel by driving each of the signal lines. Further, the semiconductor device also includes a plurality of delay circuits that are provided corresponding to each of the signal lines and can variably set the delay amount of data transmitted to the signal line, as well as a timing adjustment circuit for setting the delay amount of a corresponding signal line based on data of an adjacent signal line among the signal lines. 
     According to an embodiment, a semiconductor device can achieve stable data communication with a simple method. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a diagram showing the configuration of a semiconductor device  1  based on a first embodiment; 
         FIG. 2  is a timing chart of an interface circuit based on the first embodiment; 
         FIG. 3  is a diagram showing an example of an adjustment table of a timing adjustment circuit  200  with respect to data D 1  based on the first embodiment; 
         FIGS. 4A and 4B  are diagrams showing the relationship between adjustment values based on the first embodiment; 
         FIG. 5  is a diagram showing the configuration of a semiconductor device  1 # based on a second embodiment; and 
         FIG. 6  is a timing chart of an interface circuit based on the second embodiment. 
     
    
    
     DETAILED DESCRIPTION 
     Preferred embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. It is to be noted that like or corresponding parts are designated by like reference numerals throughout the accompanying drawings, and thus their description will not be repeated. 
     First Embodiment 
       FIG. 1  is a diagram showing the configuration of a semiconductor device  1  based on a first embodiment. 
     As shown in  FIG. 1 , the semiconductor device  1  includes an interface circuit. 
     More specifically, a parallel interface circuit will be described. 
     The semiconductor device  1  includes a plurality of signal lines DS 0  to DS 2  (hereinafter, also correctively referred to as signal line DS), as well as a driver circuit  100  provided corresponding to the signal lines to transmit a plurality of data D 0  to D 2  in parallel by driving each of the signal lines DS 0  to DS 2 . The semiconductor device  1  includes: a plurality of delay circuits DL 0  to DL 2  (hereinafter, also correctively referred to as delay circuit DL) that are provided corresponding to each of the signal lines DS 0  to DS 2  and can variably set the delay amount of data transmitted to the signal line; and sampling circuits S 0  to S 2  for sampling each of the data of the delay circuits DL 0  to DL 2 . Further, the semiconductor device  1  also includes; a timing adjustment circuit for setting the delay amount of a corresponding signal line based on data of an adjacent signal line; and signal change detection circuits DT 0  and DT 2  that are provided corresponding to each of the signal lines DS 0  and DS 2 . 
     In this example, a method for setting the delay amount of the delay circuit DL 1  of the signal line DS 1  is described as an example. 
     As an example, the driver circuit  100  includes a plurality of comparators. Each comparator outputs data D to the corresponding signal line DS based on the comparison between a reference voltage and an input voltage. In this example, the driver circuit  100  outputs read data D 0  to D 2  to each of the signal lines DS 0  to DS 2  as an example. 
       FIG. 2  is a timing chart of the interface circuit based on the first embodiment. 
     Referring to  FIG. 2 , it shows that the data D 0  of the signal line DS 0  changes from “L” level to “H” level with respect to the signal at time T 0 . The data D 2  of the signal line DS 2  changes from “L” level to “H” level. 
     The data D 1  of the signal line DS 1  changes from “H” level to “L” level at time T 2 . It is ideal that the signal changes from “H” level to “L” level in the signal line DS 1  at time T 0 , but it is shown that the fall period is delayed by a given period of time due to the influence of crosstalk of signal change in the signal lines DS 0  and DS 2 . 
     Thus, when a delay amount of a fixed value is added in the delay circuits DL 0  to DL 2 , the data D 1  of the signal line DS 1  lags behind other data. 
     At time T 3 , data D 0 _d and D 2 _ 2  through the delay circuits DL 0  and DL 2  are output. 
     At time T 4 , there is a possibility that delayed data D 1 _d through the delay circuit DL 1  may be output due to the influence of crosstalk. 
     In this example, the delay amount is adjusted with respect to the signal line DS 1 . More specifically, the delay amount is adjusted to a value that cancels the delay due to the influence of crosstalk of signal change in the signal lines DS 0  and DS 2 . This example shows the case in which the delay amount is adjusted by adjustment value L 2 #. 
     In this way, it is possible to align the synchronous timing of the sampling circuits S by cancelling the influence of the crosstalk. 
     In this example, the data D 0  and D 2  change at time T 1 . 
     The signal change detection circuits DT 0  and DT 2  detect the particular change and transit from “L” level to “H” level, respectively. 
     The timing adjustment circuit  200  obtains data of the signal lines DS 0  and DS 2 , respectively, based on data D 0 _tr and D 2 _tr that are input from the signal change detection circuits DT 0  and DT 2 . 
     When the data D 0 _tr and D 2 _tr are “H” level, the timing adjustment circuit  200  obtains the data D 0  and D 2  transmitted to the signal lines D 20  and DS 2 . The timing adjustment circuit  200  adjusts the delay amount based on the combination of the obtained data D 0 , D 2  and the data D 1  transmitted to the signal line DS 1 . 
       FIG. 3  is a diagram showing an example of the adjustment table of the timing adjustment circuit  200  with respect to the data D 1  based on the first embodiment. 
     Referring to  FIG. 3 , this shows a table for adjusting the adjustment value ΔL based on the state of the data D 1  as well as the state of the data D 0  and D 2 . 
     With respect to the data D 1 , when there is no signal change “x”, the adjustment value is 0 (none). 
     In the case in which the data D 1  transits from “L” level to “H” level, when the data D 2  transits from “L” level to “H” level, the signal timing is affected by crosstalk. In this case, the timing adjustment circuit  200  sets the adjustment value to adjustment value L 1 . The state of the data D 0  is the state of no signal change. 
     In the case in which the data D 1  transits from “L” level to “H” level, when the data D 0  transits from “L” level to “H” level, the signal timing is affected by crosstalk. In this case, the timing adjustment circuit  200  sets the adjustment value to adjustment value L 1 . The state of the data D 1  is the state of no signal change. 
     In the case in which the data D 1  transits from “L” level to “H” level, when the data D 0  transits from “L” level to “H” level and when the data D 2  changes from “L” level to “H” level, the signal timing is affected by crosstalk. In this case, the timing adjustment circuit  200  sets the adjustment value to adjustment value L 2 . 
     In the case in which the data D 1  transits from “L” level to “H” level, when the data D 2  transits from “H” level to “L” level, the signal timing is affected by crosstalk. In this case, the timing adjustment circuit  200  sets the adjustment value to adjustment value L 3 . The state of the data D 0  is the state of no signal change. 
     In the case in which the data D 1  transits from “L” level to “H” level, when the data D 0  transits from “H” level to “L” level, the signal timing is affected by crosstalk. In this case, the timing adjustment circuit  200  sets the adjustment value to the adjustment value L 3 . The state of the data D 1  is the state of no signal change. 
     In the case in which the data D 1  transits from “L” level to “H” level, when the data DO transits from “H” level to “L” level and the data D 2  changes from “H” level to “L” level, the signal timing is affected by crosstalk. In this case, the timing adjustment circuit  200  sets the adjustment value to adjustment value L 4 . 
     In the case in which the data D 1  transits from “H” level to “L” level, when the data D 2  transits from “L” level to “H” level, the signal timing is affected by crosstalk. In this case, the timing adjustment circuit  200  sets the adjustment value to adjustment value L 1 #. The state of the data D 0  is the state of no signal change. 
     In the case in which the data D 1  transits from “H” level to “L” level, when the data D 0  transits from “L” level to “H” level, the signal timing is affected by crosstalk. In this case, the timing adjustment circuit  200  sets the adjustment value to the adjustment value L 1 #. The state of the data D 1  is the state of no signal change. 
     In the case in which the data D 1  transits from “H” level to “L” level, when the data D 0  transits from “L” level to “H” level and the data D 2  transits from “L” level to “H” level, the signal timing is affected by crosstalk. In this case, the timing adjustment circuit  200  sets the adjustment value to adjustment value L 2 #. 
     In the case in which the data D 1  transits from “H” level to “L” level, when the data D 2  transits from “H” level to “L” level, the signal timing is affected by crosstalk. In this case, the timing adjustment circuit  200  sets the adjustment value to adjustment value L 3 #. The state of the data D 0  is the state of no signal change. 
     In the case in which the data D 1  transits from “H” level to “L” level, when the data D 0  transits from “H” level to “L” level, the signal timing is affected by crosstalk. In this case, the timing adjustment circuit  200  sets the adjustment value to the adjustment value L 3 #. The state of the data D 1  is the state of no signal change. 
     In the case in which the data D 1  transits from “H” level to “L” level, when the data D 0  transits from “H” level to “L” level and the data D 2  transits from “H” level to “L” level, the signal timing is affected by crosstalk. In this case, the timing adjustment circuit  200  sets the adjustment value to adjustment value L 4 #. 
     In the case in which the data D 1  transits from “L” level to “H” level, when the data D 0  transits from “L” level to “H” level and the data D 2  transits from “H” level to “L” level, or when the data D 0  transits from “H” level to “L” level and the data D 2  transits from “L” level to “H” level, the logic levels of the data of the adjacent signal lines DS are opposite to each other, so that crosstalk does not occur. For this reason, in this case, the adjustment value is 0 (none). 
     In the case in which the data D 1  transits from “H” level to “L” level, when the data D 0  transits from “L” level to “H” level and the data D 2  transits from “H” level to “L” level, or when the data D 0  transits from “H” level to “L” level and the data D 2  transits from “L” level to “H” level, the logic levels of the data of the adjacent signal lines DS are opposite to each other, so that crosstalk does not occur. For this reason, in this case, the adjustment value is 0 (none). 
       FIGS. 4A and 4B  are diagrams showing the relationship of adjustment values based on the first embodiment. 
     Referring to  FIG. 4A , this shows the relationship of the adjustment values L 1  to L 4 . 
     The adjustment values L 1  and L 2  that are set as adjustment value ΔL are negative. On the other hand, the adjustment values L 3  and L 4  are positive. The adjustment values L 1  and L 2  satisfy the relationship |L 2 |&gt;|L 1 |. The adjustment values L 3  and L 4  satisfy the relationship L 4 &gt;L 3 . 
     In the case in which the data D 1  transits from “L” level to “H” level, when the data D 0  transits from “L” level to “H” level and the data D 2  transits from “L” level to “H” level, the signal timing is affected by crosstalk more than when only either one of the data D 0  and D 2  transits. For this reason, it is necessary to increase the adjustment value of the delay amount. 
     In the case in which the data D 1  transits from “L” level to “H” level, when the data D 0  transits from “H” level to “L” level and the data D 2  transits from “H” level to “L” level, the signal timing is affected by crosstalk more than when only either one of the data D 0  and D 2  transits. For this reason, it is necessary to increase the adjustment value of the delay amount. 
     Referring to  FIG. 4B , this shows the relationship of the adjustment values L 1 # to L 4 #. 
     The adjustment values L 1 # and L 2 # that are set as adjustment value ΔL are negative. On the other hand, the adjustment values L 3 # and L 4 # are positive. The adjustment values L 1 # and L 2 # satisfy the relationship |L 2 #|&gt;|L 1 # 1 |. The adjustment values L 3 # and L 4 # satisfy the relationship L 4 #&gt;L 3 #. 
     In the case in which the data D 1  transits from “H” level to “L” level, when the data D 0  transits from “L” level to “H” level and the data D 2  transits from “L” level to “H” level, the signal timing is affected by crosstalk more than when only either one of the data D 0  and D 2  transits. For this reason, it is necessary to increase the adjustment value of the delay amount. 
     In the case in which the data D 1  transits from “H” level to “L” level, when the data D 0  transits from “H” level to “L” level and the data transits from. “H” level to “L” level, the signal timing is affected by crosstalk more than when only either one of the data D 0  and D 2  transits. For this reason, it is necessary to increase the adjustment value of the delay amount. 
     With this method, it is possible to adjust the delay amount of the delay circuit DL 1  of the signal line DS 1  to a value that cancels the influence of the crosstalk between adjacent signal lines DS. 
     Note that while this example has described the configuration in which the timing adjustment circuit  200  is provided for the signal line DS 1 , it is also possible to provide the timing adjustment circuit  200  can also be provided corresponding to each signal line DS according to the same method. With this configuration, it is possible to cancel the influence of crosstalk on each of the signal lines DS. As a result, it is possible to increase the effective window width for sampling a plurality of data in a plurality of sampling circuits S, and thus increase the speed of the process. 
     Further, the signal change detection circuits DT 0  and DT 2  respectively output detection signals D 0 _tr and D 2 _tr (“H” level) that detect the transition of the signal level of the signal lines DS 0  and DS 2 . 
     The timing adjustment circuit  200  obtains the signal level of the signal lines DS 0  and DS 2  according to the detection signal D 0 _tr and D 2 _tr. Thus, the timing adjustment circuit  200  can reliably obtain the transited data of the signal lines DS 0  and DS 2  with the detection signal D 0 _tr and D 2 _tr as a trigger. 
     In this way, it is possible to reliably set the adjustment value ΔL according to the adjustment table of  FIG. 3 . 
     The adjustment table of  FIG. 3  can be set by tests. 
     For example, the tests can use data output from a memory provided in the semiconductor device. Based on this data, the driver circuit  100  drives the signal line DS by using a predetermined data pattern. 
     For example, the driver circuit  100  drives the signal line DS according to alternating data patterns such as “101010”. It is also possible to set the adjustment table by detecting the delay difference by the delay circuit DL according to this drive. Various data patterns can be set. 
     Second Embodiment 
       FIG. 5  is a diagram showing the configuration of a semiconductor device  1 # based on a second embodiment. 
     As shown in  FIG. 5 , the semiconductor device  1 # includes an interface circuit. 
     More specifically, a parallel interface circuit will be described. 
     The semiconductor device  1 # includes a plurality of signal lines DS 0  to DS 5 , and a driver circuit  100  provided corresponding to the signal lines to transmit a plurality of data D 0  to D 5  in parallel by driving each of the signal lines DS 0  to DS 5 . The semiconductor device  1 # also includes: a plurality of delay circuits DL 0  to DL 5  that are provided corresponding to each of the signal lines DS 0  to DS 5  and can variably set the delay amount of the data transmitted to the signal line; and sampling circuits S 0  to S 5  for sampling data of each of the delay circuits DL 0  to DL 5 . 
     Further, the semiconductor device  1 # includes a timing adjustment circuit  210  for setting the delay amount of a corresponding signal line based on data of an adjacent signal line, as well as signal change detection circuits DT 0 , DT 1 , DT 3 , and DT 4  that are provided corresponding to each of the signal lines DS 0 , DS 1 , DS 3 , and DS 4 . 
     In this example, a method for setting the delay amount of the delay circuit DL 2  of the signal line DS 2  is described as an example. 
     As an example, the driver circuit  110  includes a plurality of comparators. Each comparator outputs data D to a corresponding signal line DS based on the comparison between a reference voltage and an input voltage. In this example, the driver circuit  110  outputs, as an example, read data D 0  to D 5  to each of the signal lines DS 0  to DS 5 . 
       FIG. 6  is a timing chart of the interface circuit based on the second embodiment. 
     Referring to  FIG. 6 , it shows that the data D 0  of the signal line DS 0  changes from “H” level to “L” level at time T 10 . The data D 1  of the signal line DS 1  changes from “L” level to “H” level. The data D 3  of the signal line DS 3  changes from “L” level to “H” level. The data D 4  of the signal line DS 4  maintains “L” level. 
     At T 11 , the data D 2  of the signal line DS 2  changes from “H” level to “L” level. It is ideal that the signal changes from “H” level to “L” level in the signal line DS 2  at time T 10 , but it is shown that the rise period is delayed by a given period of time due to the influence of crosstalk of signal change in the signal lines DS 0 , DS 1 , and DS 3 . 
     Thus, when a delay amount of a fixed value is added in the delay circuits DL 0 , DL 1 , and DL 3 , the data D 2  of the signal line DS 2  lags behind other data. 
     At time T 13 , the data D 0 _d, D 1 _d, and D 3 _d through the delay circuits DL 0 , DL 1 , and DL 3  are output. 
     There is a possibility that delayed data D 2 _d through the delay circuit DL 2  is output due to the influence of crosstalk at time T 14 . 
     In this example, the delay amount is adjusted with respect to the data D 2  of the signal line DS 2 . More specifically, the delay amount is adjusted to a value that cancels the delay due to the influence of crosstalk of signal change in the signal lines DS 0 , DS 1 , DS 3 , and DS 4 . This example shows the case in which the delay amount is adjusted by adjustment value Lx#. 
     In this way, it is possible to align the synchronous timing of the sampling circuits S by cancelling the influence of the crosstalk. 
     In this example, the data D 0 , D 1 , and D 2  change at time T 10 . 
     The signal change detection circuits DT 0 , DT 1 , and DT 3  detect the particular change and transit from “L” level to “H” level, respectively. 
     The timing adjustment circuit  210  obtains the data of the signal lines DS 0 , DS 1 , and DS 3 , respectively, based on the data D 0 _tr, D 1 _tr, and D 3 _tr that are input from the signal change detection circuits DT 0 , DT 1 , and DT 3 . 
     When the data D 0 _tr, D 1 _tr, and D 3 _tr are “H” level, the timing adjustment circuit  210  obtains the data D 0 , D 1 , and D 3  that are transmitted to the signal lines DS 0 , DS 1 , and DS 3 . The timing adjustment circuit  210  adjusts the delay amount based on the combination of the obtained data D 0 , D 1 , D 3  and the data D 2  transmitted to the signal line DS 2 . 
     More specifically, the timing adjustment circuit  210  adjusts the adjustment value ΔL based on the state of the data D 0 , D 1 , and D 3 , based on the same adjustment table as described in the first embodiment. 
     Note that this example has described the case in which the state of the data D 4  is not used because there is no change in the data transmitted to the signal line DS 4 . However, when there is a change in the data transmitted to the signal line DS 4 , the adjustment value ΔL is also adjusted for the data D 4  in the same way as described above. 
     With this method, it is possible to adjust the delay amount of the delay circuit DL 2  of the signal line DS 2  to a value that cancels the influence of crosstalk of adjacent signal lines DS. 
     In the second embodiment, the semiconductor device cancels the influence of crosstalk of adjacent four signal lines DS. In other words, it is possible to adjust the adjustment value to a highly accurate value ΔL. As a result, it is possible to increase the effective window width for sampling a plurality of data in the sampling circuits S, and thus increase the speed of the process. In other words, it is possible to achieve stable data communication with a simple method. 
     Note that while this example has described the configuration in which the timing adjustment circuit  210  is provided for the signal line DS 2 , the timing adjustment circuit  210  can also be provided corresponding to each of the signal lines DS according to the same method. In this way, it is possible to cancel the influence of crosstalk on each signal line DS. 
     The present disclosure has been described in detail based on preferred embodiments. However, the present disclosure is not limited to the specific embodiments and it goes without saying that the present disclosure can be variously modified without departing from the scope thereof.