Patent Publication Number: US-8123968-B2

Title: Multiple deposition for integration of spacers in pitch multiplication process

Description:
REFERENCE TO RELATED APPLICATIONS 
     This application is a continuation of U.S. patent application Ser. No. 11/213,486, now U.S. Pat. No. 7,390,746 to Bai, filed Aug. 25, 2005. 
     This application is also related to the following: U.S. Pat. No. 7,115,525 to Abatchev et al., filed Sep. 2, 2004; and U.S. Patent Provisional Application No. 60/662,323 to Tran et al., filed Mar. 15, 2005, entitled Pitch Reduced Patterns Relative To Photolithography Features. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates generally to integrated circuit fabrication and, more particularly, to masking techniques. 
     2. Description of the Related Art 
     As a consequence of many factors, including demand for increased portability, computing power, memory capacity and energy efficiency, integrated circuits are continuously being reduced in size. The sizes of the constituent features that form the integrated circuits, e.g., electrical devices and interconnect lines, are also constantly being decreased to facilitate this size reduction. 
     The trend of decreasing feature size is evident, for example, in memory circuits or devices such as dynamic random access memories (DRAMs), flash memory, static random access memories (SRAMs), ferroelectric (FE) memories, etc. To take one example, DRAM typically comprises millions of identical circuit elements, known as memory cells. In its most general form, a memory cell typically consists of two electrical devices: a storage capacitor and an access field effect transistor. Each memory cell is an addressable location that can store one bit (binary digit) of data. A bit can be written to a cell through the transistor and can be read by sensing charge in the capacitor. By decreasing the sizes of the electrical devices that constitute a memory cell and the sizes of the conducting lines that access the memory cells, the memory devices can be made smaller. Storage capacities and speeds can be increased by fitting more memory cells on a given area in the memory devices. 
     The continual reduction in feature sizes places ever greater demands on the techniques used to form the features. For example, photolithography is commonly used to pattern features, such as conductive lines. The concept of pitch can be used to describe the sizes of these features. Pitch is defined as the distance between an identical point in two neighboring features. These features are typically defined by spaces between adjacent features, which spaces are typically filled by a material, such as an insulator. As a result, pitch can be viewed as the sum of the width of a feature and of the width of the space on one side of the feature separating that feature from a neighboring feature. However, due to factors such as optics and light or radiation wavelength, photolithography techniques each have a resolution limit that results in a minimum pitch below which a particular photolithographic technique cannot reliably form features. Thus, the minimum pitch of a photolithographic technique is an obstacle to continued feature size reduction. 
     “Pitch doubling” or “pitch multiplication” is one proposed method for extending the capabilities of photolithographic techniques beyond their minimum pitch. A pitch multiplication method is illustrated in  FIGS. 1A-1F  and described in U.S. Pat. No. 5,328,810, issued to Lowrey et al., the entire disclosure of which is incorporated herein by reference. With reference to  FIG. 1A , a pattern of lines  10  is photolithographically formed in a photoresist layer, which overlies a layer  20  of an expendable material, which in turn overlies a substrate  30 . As shown in  FIG. 1B , the pattern is then transferred using an etch (preferably an anisotropic etch) to the layer  20 , thereby forming placeholders, or mandrels,  40 . The photoresist lines  10  can be stripped and the mandrels  40  can be isotropically etched to increase the distance between neighboring mandrels  40 , as shown in  FIG. 1C . A layer  50  of spacer material is subsequently deposited over the mandrels  40 , as shown in  FIG. 1D . Spacers  60 , i.e., the material extending or originally formed extending from sidewalls of another material, are then formed on the sides of the mandrels  40 . The spacer formation is accomplished by preferentially etching the spacer material from the horizontal surfaces  70  and  80  in a directional spacer etch, as shown in  FIG. 1E . The remaining mandrels  40  are then removed, leaving behind only the spacers  60 , which together act as a mask for patterning, as shown in  FIG. 1F . Thus, where a given pitch previously included a pattern defining one feature and one space, the same width now includes two features and two spaces, with the spaces defined by, e.g., the spacers  60 . As a result, the smallest feature size possible with a photolithographic technique is effectively decreased. 
     While the pitch is actually halved in the example above, this reduction in pitch is conventionally referred to as pitch “doubling,” or, more generally, pitch “multiplication.” Thus, conventionally, “multiplication” of pitch by a certain factor actually involves reducing the pitch by that factor. The conventional terminology is retained herein. 
     As can be seen in  FIGS. 1E and 1F , the separation between the spacers  60  is partly dependent upon the width of the mandrels  40 . As a result, any deformation of the mandrels  40  can change the desired position of the spacers  60 . For example, the mandrels  40  can be deformed during processing steps that occur after they are formed. 
     Accordingly, there is a need for methods of ensuring the physical integrity of the mandrels used in pitch multiplication. 
     SUMMARY OF THE INVENTION 
     According to one aspect of the invention, a process is provided for semiconductor processing. The process comprises providing a plurality of mandrels over a substrate in a reaction chamber. A first layer of spacer material is deposited on the mandrels using a first set of reactive species. A second layer of spacer material is then deposited over the mandrels using a second set of reactive species. The first and second layers of spacer material are etched to form spacers. 
     According to another aspect of the invention, a method is provided for semiconductor processing. The method comprises defining a pattern in a photoresist layer over a substrate. The pattern is transferred from the photoresist layer to an underlying layer of temporary material. Transferring the pattern from the photoresist layer forms a plurality of temporary placeholders in the layer of temporary material. A first layer of spacer material is deposited on the plurality of features by a first deposition process. A second layer of spacer material is then deposited on the first layer by a second deposition process. Spacer material of the first and second layers are removed from horizontal surfaces to form a plurality of vertically extending silicon oxide features on sidewalls of the temporary placeholders. The plurality of vertically extending silicon oxide features comprise spacer material of the first and second layers. The temporary placeholders are removed. The substrate is processed through a mask pattern defined by the plurality of vertically extending silicon oxide features. 
     According to yet another aspect of the invention, a method is provided for semiconductor processing. The method comprises providing a plurality of mandrels over a substrate. A chemical reaction barrier is formed on the mandrels. A layer of spacer material is formed on the chemical reaction barrier. The mandrel is preferentially removed relative to the spacer material. 
     According to yet another aspect of the invention, a method is provided for forming an integrated circuit. The method comprises forming a mandrel over a substrate. A first spacer layer is deposited over the mandrel by a first deposition process. A second spacer layer, which is more conformal than the first layer, is deposited on the first spacer layer and over the mandrel by a second deposition process. The mandrels are subsequently removed. 
     According to yet another aspect of the invention, a process is provided for forming an integrated circuit. The process comprises depositing a first layer of spacer material over a mandrel. A second layer of spacer material is subsequently deposited over the mandrel. The mandrel is selectively removed relative to the spacer material of the first and second layers. The first layer is denser than the second layer. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The invention will be better understood from the Detailed Description of the Preferred Embodiments and from the appended drawings, which are meant to illustrate and not to limit the invention, and wherein: 
         FIGS. 1A-1F  are schematic, cross-sectional side views of a sequence of masking patterns for forming conductive lines, in accordance with a prior art pitch doubling method; 
         FIG. 2A  is a micrograph, as viewed through a scanning electron microscope, of a perspective side view of a partially formed integrated circuit with mandrels, in accordance with preferred embodiments of the invention; 
         FIG. 2B  is a micrograph, as viewed through a scanning electron microscope, of a perspective side view of the partially formed integrated circuit of  FIG. 2A  after depositing spacer material using reactants highly reactive with the mandrels; 
         FIG. 3  is a schematic cross-sectional side view of a partially formed integrated circuit, in accordance with preferred embodiments of the invention; 
         FIG. 4  is a schematic cross-sectional side view of the partially formed integrated circuit of  FIG. 3  after forming lines in a photoresist layer, in accordance with preferred embodiments of the invention; 
         FIG. 5  is a schematic cross-sectional side view of the partially formed integrated circuit of  FIG. 4  after widening spaces between lines in the photoresist layer, in accordance with preferred embodiments of the invention; 
         FIG. 6  is a schematic, cross-sectional side view of the partially formed integrated circuit of  FIG. 5  after etching through a hard mask layer, in accordance with preferred embodiments of the invention; 
         FIG. 7  is a schematic, cross-sectional side view of the partially formed integrated circuit of  FIG. 6  after transferring a pattern from the hard mask layer to a temporary layer to form a pattern of mandrels in the temporary layer, on a first level, in accordance with preferred embodiments of the invention; 
         FIG. 8  is a schematic, cross-sectional side view of the partially formed integrated circuit of  FIG. 7  after a hard mask layer removal, in accordance with preferred embodiments of the invention; 
         FIG. 9  is a schematic, cross-sectional side view of the partially formed integrated circuit of  FIG. 8  after depositing a first layer of a spacer material, in accordance with preferred embodiments of the invention; 
         FIG. 10A  is a schematic, cross-sectional side view of the partially formed integrated circuit of  FIG. 9  after depositing a second layer of the spacer material onto the first layer, in accordance with preferred embodiments of the invention; 
         FIG. 10B  is another schematic, cross-sectional side view of the partially formed integrated circuit of  FIG. 10A , in accordance with preferred embodiments of the invention; 
         FIG. 11  is a schematic, cross-sectional side view of the partially formed integrated circuit of  FIGS. 10A and 10B , in accordance with preferred embodiments of the invention; 
         FIG. 12  is a schematic, cross-sectional side view of the partially formed integrated circuit of  FIG. 11  after selectively removing mandrels, in accordance with preferred embodiments of the invention; 
         FIG. 13  is a schematic, cross-sectional side view of the partially formed integrated circuit of  FIG. 12  after transferring a pattern formed by the spacers to a hard mask layer underlying the spacers, in accordance with preferred embodiments of the invention; 
         FIG. 14  is a schematic, cross-sectional side view of the partially formed integrated circuit of  FIG. 13  after transferring the spacer pattern to an underlying substrate, in accordance with preferred embodiments of the invention; 
         FIG. 15  is a schematic, cross-sectional side view of a partially formed integrated circuit having hard mask and additional masking layers disposed between spacers and the substrate, in accordance with preferred embodiments of the invention; 
         FIG. 16  is a schematic, cross-sectional side view of the partially formed integrated circuit of  FIG. 15  after transferring the spacer pattern into the additional masking layer, in accordance with preferred embodiments of the invention; and 
         FIG. 17  is a micrograph, as viewed through a scanning electron microscope, of a side cross section of a mandrel with overlying spacer material formed in accordance with preferred embodiments of the invention. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     It has been found that mandrels can be deformed during the deposition of spacer material.  FIG. 2A  shows mandrels before depositing spacer material. Where the mandrels are formed of amorphous carbon, silicon oxide can be used as a spacer material, among other materials possibilities. The spacer material is preferably deposited using a process that deposits highly conformal layers, e.g., processes such as thermal chemical vapor deposition of silicon oxide using O 3  and TEOS. O 3 , however, is a strong oxidizer and has been found to shrink and otherwise deform the amorphous carbon mandrels, as shown in  FIG. 2B . Consequently, spacers formed on the deformed mandrels may no longer be at their expected and desired positions and/or spacings from one another. As a result, the predictability and uniformity of spacer location and spacing can be adversely affected by mandrel deformation. 
     In preferred embodiments of the invention, in a process for minimizing mandrel deformation, a layer of material is deposited as a reaction barrier layer, i.e., a layer that prevents or reduces reactions between the mandrels and chemical species from a subsequent deposition of spacer material, including reactants and by-products of the subsequent deposition or chemical species deposited by the subsequent deposition. The material forming the reaction barrier layer can be different from the spacer material, but preferably is the same material as the spacer material. The reaction barrier layer is preferably deposited using a process and/or reactants having relatively less reactivity with the mandrels than the process and/or reactants used in the subsequent spacer material deposition. In addition, the reaction barrier layer is preferably deposited to a thickness sufficiently thick to act as a diffusion barrier that prevents reactants in the subsequent spacer material deposition from reacting with the mandrels under conditions prevalent during the second deposition. Optionally, multiple layers of material, which may the same or different materials, may be deposited to form the reaction barrier layer. 
     In accordance some preferred embodiments, the mandrels are formed of amorphous carbon and the spacer material and the material used in the reaction barrier layer is silicon oxide. Thus, the reaction barrier layer constitutes a first layer of spacer material and is formed using a process and reactants having low reactivity with the amorphous carbon. For example, the reaction barrier layer can be formed using O 2  and TEOS in a plasma-enhanced chemical vapor deposition (PECVD). While this PECVD process does not result in a film as conformal as, e.g., a film formed using O 3  and TEOS, this relative non-conformality can be minimized by depositing a layer only about as thick as necessary to reduce and, preferably, minimize reaction of the mandrels with a chemical species from a subsequent deposition of spacer material. 
     A second layer of spacer material can be deposited in the subsequent spacer material deposition. This deposition preferably results in a highly conformal layer of spacer material and can be accomplished using a process and reactants having high reactivity with the mandrels. The spacer material can be deposited by, e.g., using non-radical reactants such as O 3  and TEOS in a thermal CVD. Because the second layer of spacer material can preferably be deposited more conformally than the first layer, the second layer is preferably thicker than the first layer, so that a majority of the spacer material can be deposited by the more conformal deposition. Thus, a spacer layer that is an aggregate of the first and second layers can be deposited with good conformality by depositing a majority of the spacer layer during the second deposition. 
     Advantageously, the above-noted reaction of the O 3 , or ozone, with the mandrels is minimized by the presence of the reaction barrier layer which blocks the mandrels from the O 3 . Thus, deformation of the mandrels caused by reactions with reactants or deposited chemical species from spacer depositions can be minimized. As a result, spacers can be more reliably formed with desired spacings and positions. 
     Reference will now be made to the Figures, wherein like numerals refer to like parts throughout. It will be appreciated that the Figures are not necessarily drawn to scale. 
     Initially, a sequence of layers of materials is formed to allow formation of the spacers over a substrate. 
       FIG. 3  shows a cross-sectional side view of a partially formed integrated circuit  100 . While the preferred embodiments can be used to form any integrated circuit, they are particularly advantageously applied to form devices having arrays of electrical devices, including memory cell arrays for volatile and non-volatile memory devices such as DRAM, ROM or flash memory, including NAND flash memory. Consequently, the integrated circuit  100  can preferably be a memory chip or a logic or processor with embedded memory or a gate array. 
     With continued reference to  FIG. 3 , various masking layers  120 - 150  are preferably provided above a substrate  110 . The layers  120 - 150  will be etched to form a mask for patterning the substrate  110 , as discussed below. The materials for the layers  120 - 150  overlying the substrate  110  are preferably chosen based upon consideration of the chemistry and process conditions for the various pattern forming and pattern transferring steps discussed herein. Because the layers between a topmost selectively definable layer  120  and the substrate  110  preferably function to transfer a pattern derived from the selectively definable layer  120  to the substrate  110 , the layers  130 - 150  between the selectively definable layer  120  and the substrate  110  are preferably chosen so that they can be selectively etched relative to other exposed materials. It will be appreciated that a material is considered selectively, or preferentially, etched when the etch rate for that material is at least about 5 times greater, preferably at least about 10 times greater, more preferably at least about 20 times greater and, most preferably, at least about 40 times greater than that for surrounding materials. Because a goal of the layers  120 - 150  overlying the substrate  110  is to allow well-defined patterns to be formed in that substrate  110 , it will be appreciated that one or more of the layers  120 - 150  can be omitted or substituted if suitable other materials, chemistries and/or process conditions are used. For example, the layer  130  can be omitted in some embodiments where the resolution enhancement properties of that layer, as discussed below, are not desired. In other embodiments, discussed further below, additional masking layers can be added between the layer  150  and the substrate  110  to form a mask having improved etch selectivity relative to the substrate  110 . Exemplary materials for the various layers discussed herein include silicon oxide, silicon nitride, silicon, amorphous carbon, dielectric antireflective coatings (DARC, silicon rich silicon oxynitride), and organic bottom antireflective coatings (BARC), each of which can be selectively etched relative to at least 2 or 3 of the other materials, depending upon the application. 
     In addition to selecting appropriate materials for the various layers, the thicknesses of the layers  120 - 150  are preferably chosen depending upon compatibility with the etch chemistries and process conditions described herein. For example, when transferring a pattern from an overlying layer to an underlying layer by selectively etching the underlying layer, materials from both layers are removed to some degree. Preferably, the upper layer is thick enough so that it is not worn away over the course of the pattern transfer. 
     The selectively definable layer  120  overlies a first hard mask, or etch stop, layer  130 , which overlies a temporary layer  140 , which overlies a second hard mask, or etch stop, layer  150 , which overlies the substrate  110  to be processed (e.g., etched) through a mask. The selectively definable layer  120  is preferably photodefinable, e.g., formed of a photoresist, including any photoresist known in the art. For example, the photoresist can be any photoresist compatible with 157 nm, 193 nm, 248 nm or 365 nm wavelength systems, 193 nm wavelength immersion systems, extreme ultraviolet systems (including 13.7 nm systems) or electron beam lithographic systems. Examples of preferred photoresist materials include argon fluoride (ArF) sensitive photoresist, i.e., photoresist suitable for use with an ArF light source, and krypton fluoride (KrF) sensitive photoresist, i.e., photoresist suitable for use with a KrF light source. ArF photoresists are preferably used with photolithography systems utilizing relatively short wavelength light, e.g., 193 nm. KrF photoresists are preferably used with longer wavelength photolithography systems, such as 248 nm systems. In other embodiments, the layer  120  and any subsequent resist layers can be formed of a resist that can be patterned by nano-imprint lithography, e.g., by using a mold or mechanical force to pattern the resist. 
     The material for the first hard mask layer  130  preferably comprises an inorganic material. Exemplary materials include silicon oxide (SiO 2 ), silicon or a dielectric anti-reflective coating (DARC), such as a silicon-rich silicon oxynitride. Preferably, the first hard mask layer  130  is a dielectric anti-reflective coating (DARC). Using DARCs for the first hard mask layer  130  can be particularly advantageous for forming patterns having pitches near the resolution limits of a photolithographic technique. The DARCs can enhance resolution by minimizing light reflections, thus increasing the precision with which photolithography can define the edges of a pattern. 
     The temporary layer  140  is preferably formed of amorphous carbon, which, as noted above, offers very high etch selectivity relative to the preferred hard mask materials. More preferably, the amorphous carbon is a form of amorphous carbon that is highly transparent to light and that offers further improvements for photo alignment by being transparent to the wavelengths of light used for such alignment. Deposition techniques for forming such transparent carbon can be found in A. Helmbold, D. Meissner, Thin Solid Films, 283 (1996) 196-203, the entire disclosure of which is incorporated herein by reference. 
     The material for the second hard mask layer  150  is preferably chosen based upon the material used for the spacers and for the underlying substrate  110 . Where the spacer material is an oxide, the second hard mask layer  150  preferably comprises a dielectric anti-reflective coating (DARC) (e.g., a silicon oxynitride), silicon or aluminum oxide (Al 2 O 3 ). In addition, a bottom anti-reflective coating (BARC) (not shown) can optionally be used to control light reflections. In the illustrated embodiment, the second hard mask layer  150  comprises aluminum oxide. 
     The various layers discussed herein can be formed by various methods known in the art. For example, spin-on-coating processes can be used to form photodefinable layers, BARC, and spin-on dielectric oxide layers. Various vapor deposition processes, such as chemical vapor deposition, can be used to form hard mask layers. 
     Having formed a desired stack of layers, a pattern of spacers is next formed by pitch multiplication. 
     With reference to  FIG. 4 , a pattern comprising spaces or trenches  122 , which are delimited by photodefinable material features  124 , is formed in the photodefinable layer  120 . The trenches  122  can be formed by, e.g., photolithography with 248 nm or 193 nm light, in which the layer  120  is exposed to radiation through a reticle and then developed. After being developed, the remaining photodefined material forms mask features such as the illustrated lines  124  (shown in cross-section only). 
     As shown in  FIG. 5 , the photoresist lines  124  can be etched using an isotropic etch to “shrink” those features to adjust their widths. The extent of the etch is preferably selected so that the widths of the modified lines  124   a  are substantially equal to the desired spacing between the later-formed spacers  175  ( FIG. 11 ), as will be appreciated from the discussion below. Suitable etches include etches using an oxygen-containing plasma, e.g., a SO 2 /O 2 /N 2 /Ar plasma, a Cl 2 /O 2 /He plasma or a HBr/O 2 /N 2  plasma. For example, the width of the lines  124  can be reduced from about 80-120 nm to about 40-70 nm. Advantageously, the width-reducing etch allows the lines  124   a  to be narrower than would otherwise be possible using the photolithographic technique used to pattern the photodefinable layer  120 . In addition, the etch can smooth the edges of the lines  124   a , thus improving the uniformity of those lines. While the critical dimensions of the lines  124   a  can be etched below the resolution limits of the photolithographic technique, it will be appreciated that this etch does not alter the pitch of the spaces  122   a  and lines  124   a , since the distance between identical points in these features remains the same. 
     With reference to  FIG. 6 , the pattern in the (modified) photodefinable layer  120   a  is transferred to the hard mask layer  130 . This transfer is preferably accomplished using an anisotropic etch, such as an etch using a fluorocarbon plasma, although a wet (isotropic) etch may also be suitable if the hard mask layer  130  is thin. Preferred fluorocarbon plasma etch chemistries include CFH 3 , CF 2 H 2  and CF 3 H. 
     With reference to  FIG. 7 , the pattern in the photodefinable layer  120   a  and the hard mask layer  130  is transferred to the temporary layer  140  to form mandrels  145 . Layers  170   a  and  170   b  of spacer material ( FIGS. 9-10 ) will later be deposited on the mandrels  145 . It has been found that the temperatures used for spacer material deposition (which is preferably conformal, such that processes such as chemical vapor deposition are preferred) are typically too high for photoresist to withstand. Thus, the pattern is preferably transferred from the photodefinable layer  120   a  to the temporary layer  140 , which is formed of a material that can withstand the process conditions for spacer material deposition and etching, discussed below. In addition to having higher heat resistance than photoresist, the material forming the temporary layer  140  is preferably selected such that it can be selectively removed relative to the material for the spacers  175  ( FIG. 11 ) and the underlying etch stop layer  150 . As noted above, the layer  140  is preferably formed of amorphous carbon and, more preferably, transparent carbon. 
     The pattern in the modified photodefinable layer  120   a  is preferably transferred to the temporary layer  140  using a reactive ion etch (RIE) employing an oxygen-containing plasma, e.g., a plasma containing SO 2 , O 2  and Ar. Other suitable etch chemistries include a Cl 2 /O 2 /SiCl 4 , SiCl 4 /O 2 /N 2 , or HBr/O 2 /N 2 /SiCl 4 -containing plasma. Advantageously, the SO 2 -containing plasma is used as it can etch carbon of the preferred temporary layer  140  at a rate greater than 20 times and, more preferably, greater than 40 times the rate that the hard mask layer  130  is etched. A suitable SO 2 -containing plasma is described in U.S. patent application Ser. No. 10/931,772 to Abatchev et al., filed Aug. 31, 2004, the entire disclosure of which is incorporate herein by reference. It will be appreciated that the SO 2 -containing plasma can simultaneously etch the temporary layer  140  and also remove the photoresist layer  120   a . The resulting lines  124   b , separated by spaces  122   b , constitute the placeholders or mandrels along which a pattern of spacers  175  ( FIG. 11 ) will be formed. 
     With reference to  FIG. 8 , the hard mask layer  130  can be selectively removed to facilitate later spacer formation by leaving the mandrels  145  exposed for subsequent etching ( FIG. 12 ). The hard mask layer  130  can be removed using a buffered oxide etch (BOE), which is a wet etch comprising HF and NH 4 F. 
     Next, as shown in  FIG. 9 , a reaction barrier layer  170   a  is blanket deposited over exposed surfaces, including the hard mask layer  150  and the tops and sidewalls of the mandrels  145 . The material forming the layer  170   a  is preferably similar to the material used for the spacers, e.g., both materials can be forms of silicon oxide, or the layer  170   a  can be formed of a material for which an etch selectivity similar to that of the spacer material is available. The deposition process conditions and/or reactants, however, are chosen such that the deposition process results in minimal deformation of the mandrels. In addition, the layer  170   a  preferably has a composition and thickness that minimizes diffusion of reactants in a subsequent deposition through the layer  170   a  on to the mandrels  145 . The layer  170   a  is preferably a layer of a first spacer material which can be deposited using a first deposition process using a first set of precursors having minimal reactivity with the mandrels. 
     It will be appreciated that the first spacer material can be any material that can act as a mask for transferring a pattern to the underlying hard mask layer  150 . The spacer material preferably: 1) can be deposited with good step coverage; 2) can be deposited at a temperature compatible with the mandrels  145 ; and 3) can be selectively etched relative to the mandrels  145  and underlying hard mask layer  150 . Preferred materials include silicon, silicon oxides and silicon nitrides. In the illustrated embodiment, the first spacer material is silicon oxide, which provides particular advantages in combination with other selected materials of the masking stack. 
     As noted above, the silicon oxide is preferably deposited by a plasma enhanced chemical vapor deposition using oxygen gas (O 2 ) and TEOS as precursors. The reactants in this process advantageously have a low reactivity with mandrel materials, such as amorphous carbon, in comparison to other oxygen precursors such as O 3 . 
     An example of a suitable reactor system is the Applied Materials&#39; Producer™ system, which can remotely generate excited reactive species, such as an oxygen plasma. In one example of process conditions, O 2  is preferably remotely activated and flowed into the reactor at a rate of about 300-1000 sccm and, more preferably, about 400-600 sccm. TEOS is flowed into the reactor at a rate of about 200-800 mgm and, more preferably, about 400-600 mgm and a carrier gas, e.g., He, is flowed flowed into the reactor at a rate of about 2000-3000 sccm and, more preferably, about 2500 sccm. The RF power is preferably about 300-800 watts and, more preferably, about 500-600 watts. The pressure within the reactor is preferably maintained at about 5-10 torr and, more preferably, about 6-8 torr. 
     The reactor is preferably maintained at a temperature sufficiently low to prevent chemical or physical disruption of the amorphous carbon layer. In addition, it has been found that material deposited on amorphous carbon mandrels can peel off at high deposition temperatures. Consequently, the deposition temperature is preferably about 350-400° C. and, more preferably, about 375° C. 
     The layer of the first spacer material  170   a  is preferably deposited to a thickness of about 100-300 Å and, more preferably, about 150-250 Å. This thickness has been found to adequately protect the mandrels  145  from reactions with subsequent reactants, such O 3  which can oxidize the mandrels  145 . In addition, because films deposited by the PEVCD process may not be as conformal as films deposited by thermal CVD processes, this relatively thin layer  170   a  minimizes the affect of uniformities of the PECVD process on the ultimately deposited spacer layer  170  ( FIG. 10B ). 
     It will be appreciated that the conformality of a layer is related to its step coverage. A highly conformal layer has high step coverage. Preferably, the step coverage (the ratio of the thickness of the deposited layer at a midpoint up the height of the mandrel relative to the thickness of the deposited layer at a top of the mandrel in percentage terms) is about 50% or greater, more preferably, about 75% or greater and, most preferably, about 95% or greater. 
     With reference to  FIG. 10A , a layer of the second spacer material  170   b  is deposited on the layer of the first spacer material  170   a . The second layer  170   b  is preferably deposited by a process which can deposit a highly conformal film. In addition, as above, the deposition temperature is preferably sufficiently low to prevent chemical or physical disruption of the amorphous carbon layer. Preferably, the second layer  170   b  is deposited by a thermal chemical vapor deposition using ozone (O 3 ) and TEOS as precursors at a deposition temperature of about 350-450° C. and, more preferably, about 375° C. Preferably, the step coverage of the layer  170   b  is about 75% or greater, more preferably, about 85% or greater and, most preferably, about 95% or greater. 
     Depending on the capabilities of the reactor, the same reactor used for depositing the layer  170   a  may also be used for this thermal CVD. For example, the Applied Materials&#39; Producer™ system can be used for both this thermal CVD and the above-described PECVD. In one example of process conditions for the thermal CVD, the flow rate of O 3  into the reactor is about 4000-10000 sccm and, more preferably, about 6000 sccm. The flow rate of TEOS into the reactor is about 2000-3000 mgm and, more preferably, about 2400 mgm and a carrier gas, e.g., He or N 2 , is flowed flowed into the reactor at a rate of about 4000-10000 sccm and, more preferably, about 6000 sccm. The reaction chamber pressure is preferably maintained at about 40-400 torr and, more preferably, about 100 torr. 
     With continued reference to  FIG. 10A , it will be appreciated that where the first and second layers  170   a  and  170   b  are both formed of a similar spacer material, the layers  170   a  and  170   b  are shown as separate layers for ease of explanation and illustration. Where these layers  170   a  and  170   b  are formed of the same material, however, they may be viewed as forming a single layer  170  of spacer material, as illustrated in  FIG. 10B . 
     While generally being considered to be the “same” material, e.g., silicon oxide, the skilled artisan will appreciate that the different deposition processes used to form the layers  170   a  and  170   b  can cause small structural and chemical variations in those layers. For example, the layer  170   a , when formed with O 2  and TEOS in a PECVD, can have a higher density than the layer  170   b , when formed with O 3  and TEOS in a thermal CVD. In addition, the use of these different reactants can result in slightly different ratios of oxygen to silicon, and also the possible presence of different impurities, in the deposited layers  170   a  and  170   b . Given these differences between the layers  170   a  and  170   b , it will be appreciated that the layers can have slightly different properties. For example, the rate that the layers are etched by a given etchant can be slightly different. In addition, the ability of the layers to act as diffusion barriers can be different, e.g., the layer  170   a  can be a better diffusion barrier than the layer  170   b , which may be more porous than the layer  170   a.    
     It will be appreciated that the combined thickness of the layers  170   a  and  170   b  correspond approximately to the width of the spacers  175  ( FIG. 11 ). Thus, the thickness of the layer  170  is preferably determined based upon the desired width of the spacers  175 . As a result, after preferably depositing the first layer  170   a  to a thickness sufficiently thick to act as a reaction barrier, the layer  170   b  is preferably formed so that the aggregate thickness of the layers  170   a  and  170   b  is about the desired width of the spacers  175 . 
     With reference to  FIG. 11 , the spacer layer  170   a  and  170   b  are then subjected to an anisotropic etch to remove spacer material from horizontal surfaces  180  of the partially formed integrated circuit  100 . Such a directional etch, also known as a spacer etch, can be performed using a fluorocarbon plasma, e.g., a CF 4 /CHF 3 , C 4 F 8 /CH 2 F 2  or CHF 3 /Ar plasma. It will be appreciated that while shown for ease of illustration having approximately the same width as the mandrels  145 , the spacers  175  can have a smaller width than the mandrels  145 . 
     With reference to  FIG. 12 , a pattern of free standing spacers  175  is formed by removing the mandrels  145 . The mandrels  145  are selectively removed using an organic strip process. Preferred etch chemistries include a sulfur-containing plasma etch, such as an etch using SO 2 . 
     Thus, a pitch multiplied pattern of spacers  175  have been formed. In the illustrated embodiment, the pitch of the spacers  175  is roughly half that of the photoresist lines  124  and spaces  122  ( FIG. 4 ) originally formed by photolithography. Where the photoresist lines  124  had a pitch of about 200 nm, spacers  175  having a pitch of about 100 nm or less can be formed. 
     In some embodiments, particularly where the substrate  110  can be etched with good selectivity relative to the hard mask layer  150 , the hard mask layer  150  can be used as a mask to etch the substrate  110 . As shown in  FIG. 13 , the pattern formed by the spacers  175  can be transferred to the hard mask layer  150  using an anisotropic etch, e.g., a BCl 3 /Cl 2  plasma etch, to selectively etch the layer  150  through that pattern formed by the spacers  175 . 
     Optionally, the spacers  175  can be removed to reduce the aspect ratio of mask features before etching the substrate  110 . For example, where the spacers  175  comprise a silicon oxide, the spacer removal can be accomplished using a wet or dry etch, e.g., a wet buffered oxide etch or a dry etch using a CH 2 F 2 /C 4 F 8 /Ar/O 2  plasma. 
     With reference to  FIG. 14 , the hard mask layer  150  and/or the spacers  175  can be used as a mask through which the substrate  110  is processed. For example, the pattern in the hard mask  150  can be transferred to the substrate  110  by selectively etching the substrate  110 , using an etch chemistry appropriate for the material(s) of the substrate  110 , as known in the art. 
     With reference to  FIG. 15 , in other embodiments, especially where the substrate  110  is difficult to etch, intervening layers of masking material can be formed between the hard mask layer  150  and the substrate  110 . For example, additional layers  155  and  160  can be provided, as discussed in co-pending U.S. Patent Provisional Application No. 60/662,323 to Tran et al., filed Mar. 15, 2005, entitled Pitch Reduced Patterns Relative to Photolithography Features, the entire disclosure of which is incorporated herein by reference. 
     In such a case, the layer  150  preferably comprises a material that has good etch selectively relative to the spacers  175  and the layer  155 . Exemplary materials for the layers  150  and  155  include amorphous silicon and silicon oxide, respectively. The layer  155  advantageously allows for a pattern-cleaning step (e.g., with O 2  plasma) to remove any polymerized organic residue that may be present as the result of previous etch processes, such as the removal of mandrels  145 . After the cleaning step, a well-defined pattern can be transferred to the layer  160 . The layer  160  is preferably formed of amorphous carbon, which is advantageously resistant to many etch chemistries for removing silicon materials in the substrate  110 . As shown in  FIG. 16 , the pattern defined by the spacers  175  can be transferred to the layer  160 , which then serves as the primary mask for patterning the substrate  110 . Advantageously, due to the availability of extreme selectivity when etching amorphous carbon, a patterned hard mask layer  150  can be used after removal of spacers to transfer the pattern with lower and more uniform aspect ratio features to the primary masking layer  160 . 
     It will be appreciated that the formation of spacers according to the preferred embodiments offers numerous advantages. By minimizing reactions of mandrels with precursors for spacers, deformation of the mandrels can also be minimized. A silicon oxide spacer layer formed by a PECVD with O 2  and TEOS and then a thermal CVD with O 3  and TEOS is shown in  FIG. 17 . In comparison with the spacer layer shown in  FIG. 2B , shrinkage and deformation of the mandrels is advantageously reduced. Thus, because the positions and sizes of the mandrels are not significantly altered by the spacer layer deposition, the spacers can be more reliably formed at their desired and expected positions. 
     Moreover, while PECVD using O 2  and TEOS can have a relatively low conformality that discourages its use in spacer formation, the spacer layer has excellent conformality, as can be seen in  FIG. 17 . The spacers formed from the spacer layer can better approximate their desired dimensions and positions. Thus, the preferred embodiments allow improved control of the dimensions of features in a mask pattern. 
     It will be appreciated that while discussed with reference to particular materials for the various layers and parts discussed herein, other materials can also be used. Preferably, however, any other materials that may be used offer the appropriate etch selectivity relative to the materials that are used, as discussed above. Moreover, while two layers  170   a  and  170   b  are illustrated, more than two layers, deposited by one or two or more different processes, can be deposited to form the spacer layer  170  ( FIG. 10A ). While preferably formed of the same material, these layers can be formed of different materials. For example, one layer can be formed of silicon oxide, while the other is formed of silicon nitride. In another example, one layer is formed of aluminum oxide and the other is formed of silicon oxide. Where the layers are formed of different materials, the materials are preferably chosen so that suitable etch chemistries are available to perform a complete spacer etch and subsequent transfer of the spacer pattern to underlying layers. Advantageously, the material for the first layer can be chosen to have benefits for direct contact and process exposure to the mandrels, while the material for the second layer can be chosen to have benefits for completing the spacer layer (e.g., increased deposition rates, conformality, etc.). 
     In addition to the CVD processes discussed above, various other processes can be used to deposit the various layers of material discussed herein. For example, atomic layer deposition (ALD) can be employed, for depositing one or both of the layers  170   a  and  170   b , or additional layers to these layers. In some embodiments, ALD can be used to deposit a silicon oxide reaction barrier layer, using a self-limitingly deposited silicon precursor and an oxygen precursor, e.g., water, to form silicon oxide. Then, an O 3 -based process, e.g., a thermal CVD with O 3  and TEOS, could be used to form the silicon oxide layer to a desired thickness. 
     In other embodiments, the same deposition processes (e.g., thermal CVD, ALD or PECVD) can be used, while the reactants are chosen based upon reactivity with mandrel materials. Where different processes are employed, the reactants used can be different for each process, or some reactants can be kept constant. For example, when forming silicon oxide, the silicon reactants can be varied for each process and the oxidizer can be the same or different for each process. 
     Also, the masks discussed herein can be used to form various integrated circuit features, including, without limitation, interconnect lines, landing pads and parts of various electrical devices, such as capacitors and transistors, particularly for memory and logic arrays in which dense repeating patterns are desirable. As such, while illustrated as lines with regular spacing and regular widths for ease of illustration, the masks can have features with variable spacing and variable dimensions. Optionally, the spacers can be trimmed and/or masked and etched to formed features with desired dimensions. Moreover, the spacers  175  can be more than pitch doubled. An exemplary method for further pitch multiplication is discussed in U.S. Pat. No. 5,328,810 to Lowrey et al. with reference to  FIGS. 19-23  of that patent. Also, while illustrated with spacers formed on a single level, in other embodiments, spacers can be formed on multiple vertical levels and consolidated on a single level to form a mask pattern. 
     It will also be appreciated that the substrate  110  can comprise different materials, e.g., layers of different materials, or different materials in different lateral regions of the substrate. In such cases, the primary masking layer  160  is preferably used for superior etch selectivity. To transfer the pattern defined by the spacers to such a substrate, a succession of different chemistries, preferably dry-etch chemistries, can be used to successively etch through these different materials, if a single chemistry is not sufficient to etch all the different materials. It will also be appreciated that, depending upon the chemistry or chemistries used, the spacers  175  and the hard mask layer  150  may be etched. Using amorphous carbon for the primary mask layer  160 , however, advantageously offers excellent resistance to conventional etch chemistries, especially those used for etching silicon-containing materials. Thus, the primary mask layer  160  can effectively be used as a mask for etching through a plurality of substrate layers, or for forming high aspect ratio trenches. 
     The preferred embodiments can also be employed multiple times throughout an integrated circuit fabrication process to form features in a plurality vertical levels, which may be vertically contiguous or non-contiguous and vertically separated. In such cases, each of the individual levels to be patterned would constitute a substrate  110 . In addition, some of the preferred embodiments can be combined with other of the preferred embodiments, or with other masking methods known in the art, to form features on different areas of the same substrate  110  or on different vertical levels. 
     Accordingly, it will be appreciated by those skilled in the art that these and various other omissions, additions and modifications may be made to the methods and structures described above without departing from the scope of the invention. All such modifications and changes are intended to fall within the scope of the invention, as defined by the appended claims.