Patent Publication Number: US-2023163078-A1

Title: Semiconductor device

Description:
TECHNICAL FIELD 
     The present disclosure relates to a semiconductor device. 
     BACKGROUND ART 
     Existing semiconductor devices include the one called an intelligent power module (IPM). This type of semiconductor device includes a semiconductor chip, a control chip that controls the semiconductor chip, and a sealing resin covering the semiconductor chip and the control chip (see PTL 1). 
     PRIOR ART DOCUMENT 
     Patent Document 
     Patent Document 1: JP-A-2020-4893 
     SUMMARY OF THE INVENTION 
     Problem to be Solved by the Invention 
     The control chip receives and outputs a plurality of types of control signals. With an increase in the number of control signals, the number of conduction paths to the control chip has to be increased. However, constituting the conduction paths with a plurality of leads, as in conventional devices, may make it difficult to achieve a higher degree of integration of the semiconductor device. 
     The present disclosure has been accomplished in view of the foregoing situation, and provides a semiconductor device that allows a higher degree of integration to be achieved. 
     Means to Solve the Problem 
     According to an aspect of the present disclosure, there is provided a semiconductor device including: a substrate having a substrate obverse face and a substrate reverse face oriented in opposite directions to each other in a thickness direction; a conductive section formed of a conductive material and located on the substrate obverse face; the conductive section including a first section and a second section spaced apart from each other; a sealing resin covering at least a part of the substrate and an entirety of the conductive section; and a conductive section wire conductively bonded to the first section and the second section. 
     Advantages of the Invention 
     In the foregoing semiconductor device, the conductive section is formed on the substrate obverse face. Accordingly, conduction paths to electronic parts arranged on the substrate obverse face can be formed utilizing the conductive section provided on the substrate obverse face. Therefore, the conduction paths can be formed of finer lines and in higher density, compared with the case of, for example, using metal leads to constitute the conduction path. In addition, the conductive section wire is conductively bonded to the first section and the second section, spaced apart from each other on the conductive section. Therefore, for example in the case where connection wirings and electronic parts are arranged between the first section and the second section, the conduction path can be shortened, compared with the case of arranging the connection wiring between the first section and the second section through a long detour. Further, a higher degree of freedom can be attained in designing the conduction paths. Consequently, the semiconductor device configured as above allows a higher degree of integration to be achieved. 
     Other features and advantages of the present disclosure will become more apparent, through detailed description given hereunder with reference to the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG.  1    is a perspective view showing a semiconductor device according to a first embodiment. 
         FIG.  2    is a plan view showing the semiconductor device of  FIG.  1   . 
         FIG.  3    is a plan view showing the semiconductor device of  FIG.  1   , seen through a sealing resin. 
         FIG.  4    is a bottom view showing the semiconductor device of  FIG.  1   . 
         FIG.  5    is a cross-sectional view taken along a line V-V in  FIG.  3   . 
         FIG.  6    is a partially enlarged plan view from  FIG.  3   . 
         FIG.  7    is across-sectional view taken along a line VII-VII in  FIG.  6   . 
         FIG.  8    is a plan view showing a substrate of the semiconductor device of  FIG.  1   . 
         FIG.  9    is a flowchart showing a process in an exemplary manufacturing method of the semiconductor device shown in  FIG.  1   . 
         FIG.  10    is a partially enlarged plan view showing a semiconductor device according to a second embodiment. 
         FIG.  11    is a partially enlarged plan view showing a semiconductor device according to a third embodiment. 
         FIG.  12    is a partially enlarged plan view showing a semiconductor device according to a fourth embodiment. 
         FIG.  13    is a partially enlarged plan view showing a semiconductor device according to a fifth embodiment. 
         FIG.  14    is a partially enlarged plan view showing a semiconductor device according to a sixth embodiment. 
         FIG.  15    is a partially enlarged plan view showing a variation of the semiconductor device according to the first embodiment. 
     
    
    
     MODE FOR CARRYING OUT THE INVENTION 
     Hereafter, exemplary embodiments of the present disclosure will be described in detail, with reference to the drawings. 
     In the description of the present disclosure, the expression “An object A is formed in an object B”, and “An object A is formed on an object B” imply the situation where, unless otherwise specifically noted, “the object A is formed directly in or on the object B”, and “the object A is formed in or on the object B, with something else interposed between the object A and the object B”. Likewise, the expression “An object A is arranged in an object B”, and “An object A is arranged on an object B” imply the situation where, unless otherwise specifically noted, “the object A is arranged directly in or on the object B”, and “the object A is arranged in or on the object B, with something else interposed between the object A and the object B”. Further, the expression “An object A is located on an object B” implies the situation where, unless otherwise specifically noted, “the object A is located on the object B, in contact with the object B”, and “the object A is located on the object B, with something else interposed between the object A and the object B”. Further, the expression “An object A overlaps with an object B as viewed in a certain direction” implies the situation where, unless otherwise specifically noted, “the object A overlaps with the entirety of the object B”, and “the object A overlaps with a part of the object B”. 
       FIG.  1    to  FIG.  8    illustrate a semiconductor device according to a first embodiment. The semiconductor device A 1  shown in the mentioned drawings include a plurality of leads  11  to  15  (hereinafter simply “lead  1 ” where appropriate), a substrate  2 , a plurality of bonding sections  25 , a conductive section  3 , two semiconductor chips  4 , two control devices  5 , a plurality of passive elements  6 , a plurality of wires  71 , a plurality of wires  72 , wires  73   a  and  73   b,  and a sealing resin  8 . In this embodiment, the semiconductor device A 1  is the intelligent power module (IPM), without limitation thereto. The semiconductor device A 1  may be applied, for example, for use in an air-conditioner or a motor control device. 
       FIG.  1    is a perspective view showing the semiconductor device A 1 .  FIG.  2    is a plan view showing the semiconductor device A 1 .  FIG.  3    is a plan view showing the semiconductor device A 1 , seen through the sealing resin  8 . In  FIG.  3   , the outer shape pf the sealing resin  8  is indicated by imaginary lines (dash-dot-dot lines).  FIG.  4    is a bottom view showing the semiconductor device A 1 .  FIG.  5    is a cross-sectional view taken along a line V-V in  FIG.  3   .  FIG.  6    is a partially enlarged plan view from  FIG.  3   .  FIG.  7    is across-sectional view taken along a line VII-VII in  FIG.  6   .  FIG.  8    is a plan view showing the substrate  2  of the semiconductor device A 1 . 
     For the convenience in description, the thickness direction of the substrate  2  will be defined as z-direction, as shown in  FIG.  1   . There are two mutually perpendicular directions, each of which is perpendicular to the z-direction, and one of them will be defined as x-direction, and the other as y-direction. As shown in  FIG.  2    to  FIG.  4   , the x-direction extends along a pair of sides of the substrate  2  parallel to each other. The y-direction extends along the other pair of sides of the substrate  2  parallel to each other. A view in the z-direction (view in the thickness direction) may be expressed as plan view, where appropriate. 
     The substrate  2  is formed in a plate shape, and has a rectangular shape with the longer sides extending in the x-direction, as viewed in the z-direction. The thickness of the substrate  2  (size in the z-direction) is, for example, approximately 0.1 mm to 1.0 mm. The dimensions of the substrate  2  are not specifically limited. The substrate  2  is formed of an insulative material. The material of the substrate  2  is not specifically limited. It is preferable to form the substrate  2 , for example with a material having higher thermal conductivity than the material of the sealing resin  8 . Examples of material for the substrate  2  include ceramics such as alumina (Al 2 O 3 ), silicon nitride (SiN), aluminum nitride (AlN), and zirconia-toughened alumina. 
     The substrate  2  includes a substrate obverse face  21  and a substrate reverse face  22 . The substrate obverse face  21  and the substrate reverse face  22  are flat faces perpendicular to the z-direction, and oriented in opposite direction to each other in the z-direction. The substrate obverse face  21  is oriented upward in  FIG.  5   . On the substrate obverse face  21 , the conductive section  3  and the plurality of bonding sections  25  are formed, and also the plurality of leads  1  and the plurality of electronic parts are mounted. The plurality of electronic parts include, for example, two semiconductor chips  4 , two control devices  5 , and a plurality of passive elements  6 . Thus, the “electronic parts” are not just conductive bodies, but each have a predetermined function. The substrate reverse face  22  is oriented downward in  FIG.  5   . As shown in  FIG.  4   , the substrate reverse face  22  is exposed from the sealing resin  8 . The substrate obverse face  21  and the substrate reverse face  22  both have a rectangular shape. The shape of the substrate  2  is not limited to the illustrated example. 
     The conductive section  3  is formed on the substrate  2 . In this embodiment, the conductive section  3  is formed on the substrate obverse face  21  of the substrate  2 . The conductive section  3  is formed of a conductive material. Examples of the conductive material include, but are not limited to, silver (Ag), copper (Cu), and gold (Au). Alternatively, the conductive section  3  may be formed of a conductive material containing the cited metal. For the following description, it will be assumed that the conductive section  3  contains silver. Here, the conductive section  3  may contain copper instead of silver, or gold instead of silver or copper. Further, the conductive section  3  may contain Ag—Pt or Ag—Pd. The forming method of the conductive section  3  is not specifically limited but, for example, the conductive section  3  may be formed by sintering a paste containing the above-cited metal. The thickness of the conductive section  3  may be, for example, approximately 5 μm to 30 μm, without limitation thereto. 
     The shape of the conductive section  3  is not specifically limited. In this embodiment, the conductive section  3  includes, as shown in  FIG.  8   , a plurality of first pads  31 , a plurality of second pads  32 , and a plurality of connection wirings  33 . The first pads  31  each have, for example, an elongate rectangular shape, and a control device  5  ( 5   a,    5   b ) is conductively bonded thereto (see  FIG.  3   ). The shape of the first pad  31  is not specifically limited. The plurality of first pads  31  are spaced apart from one another. 
     The second pads  32  each have, for example, a rectangular shape, and the leads  15  (subsequently described), the passive element  6 , and one of the wires  72 ,  73   a,  and  73   b  are conductively bonded to the second pads  32 . The shape of the second pad  32  is not specifically limited. The plurality of second pads  32  are spaced apart from one another. As shown in  FIG.  6   , the plurality of second pads  32  include second pads  32   a,    32   b,    32   c,    32   d,    32   e,  and  32   f.  To the second pads  32   a  and  32   b,  the passive element  6  (thermistor  6   b ) is conductively bonded. In addition, the wire  73   a  is conductively bonded to the second pad  32   a,  and the wire  73   b  is conductively bonded to the second pad  32   b.  To the second pad  32   c,  the wire  73   a  is conductively bonded. To the second pad  32   d,  the wire  73   b  is conductively bonded. To the second pads  32   e  and  32   f,  the leads  15  (lead  15   a  and  15   b ) are conductively bonded. 
     As shown in  FIG.  6    and  FIG.  8   , the connection wirings  33  are connected to at least one of the first pads  31 , or at least one of the second pads  32 . To be more detailed, the plurality of connection wirings  33  include connection wirings each having two ends, and connection wirings each branched halfway thus having three ends (see  33   c  and  33   d  in  FIG.  6   ). Here, the present disclosure is not limited to the mentioned example, but may employ a connection wiring having four or more ends. In the illustrated example, the plurality of connection wirings  33  include three types of connection wiring, namely (1) connection wiring connected to one of the first pads  31  and one of the second pads  32 , (2) connection wirings connected to at least two first pads  31 , and (3) connection wirings connected to two second pads  32 . In the example shown in  FIG.  6   , the connection wiring  33   a  is connected to two second pads ( 32   c  and  32   e ), and the connection wiring  33   b  is also connected to two second pads ( 32   d  and  32   f ). The connection wiring  33   c  is connected to three first pads  31  (two bonded to the control device  5   a,  and one bonded to the control device  5   b ). The connection wiring  33   d  is connected to two first pads  31  (one bonded to the control device  5   a,  and one bonded to the control device  5   b ) and to one second pad  32  to which the lead  15  is bonded. Here, some of the first pads  31  and the second pads  32  are connected to none of the connection wirings  33 . 
     In this embodiment, at least one of the plurality of connection wirings  33  includes a portion overlapping with the control device  5 , as viewed in the z-direction. In other words, such a connection wiring  33  includes a portion arranged between the substrate obverse face  21  and the control device  5 . The connection wirings having the portion overlapping with the control device  5  may hereinafter be referred to as “overlapping wiring”. In the example shown in  FIG.  6   , a plurality of overlapping wirings are employed. 
     The plurality of bonding sections  25  are formed on the substrate  2 , as shown in  FIG.  8   . In this embodiment, the substrate obverse face  21  (more broadly, the substrate  2 ) includes two edges spaced apart from each other in the y-direction (each extending in the x-direction), and the plurality of bonding sections  25  are located close to one of such edges. The material of the bonding section  25  is not specifically limited but, for example, a material capable of bonding the substrate  2  and the lead  1  together may be employed. The bonding section  25  is, for example, formed of a conductive material. The conductive material for forming the bonding section  25  is not specifically limited. Examples of the conductive material for forming the bonding section  25  include a material containing silver (Ag), copper (Cu), or gold (Au). For the following description, it will be assumed that the bonding section  25  contains silver. The bonding section  25  according to this embodiment is formed of the same conductive material as that employed for the conductive section  3 . Here, the bonding section  25  may contain copper instead of silver, or gold instead of silver or copper. Further, the bonding section  25  may contain Ag—Pt or Ag—Pd. The forming method of the bonding section  25  is not specifically limited but, for example, the bonding section  25  may be formed, like the conductive section  3 , by sintering a paste containing the above-cited metal. The thickness of the bonding section  25  may be, for example, approximately 5 μm to 30 μm, without limitation thereto. 
     In this embodiment, the plurality of bonding sections  25  includes three bonding sections  251 ,  252 , and  253 , as shown in  FIG.  8   . The bonding sections  251 ,  252 , and  253  are spaced apart from one another. The substrate obverse face  21  (more broadly, the substrate  2 ) includes two edges spaced apart from each other in the x-direction (each extending in the y-direction), and the bonding section  251  is located close to one of such edges. To the bonding section  251 , the lead  11  (subsequently described) is bonded. The bonding section  253  is formed in a central portion of the substrate obverse face  21  in the x-direction. To the bonding section  253 , the lead  13  (subsequently described) is bonded. The bonding section  252  is formed so as to surround at least a part of the bonding section  251 . To the bonding section  252 , the lead  12  (subsequently described) is bonded. Here, the shape and location of the bonding sections  251 ,  252 , and  253  are not limited to the mentioned example. 
     The plurality of leads  1  each contain a metal, having higher thermal conductivity, for example, than the substrate  2 . The metal for forming the lead  1  is not specifically limited but, for example, copper (Cu), aluminum, iron (Fe), oxygen-free copper, or an alloy thereof (e.g., a Cu—Sn alloy, a Cu—Zr alloy, or a Cu—Fe alloy). The plurality of leads  1  may each be plated with nickel (Ni). The plurality of leads  1  may be formed by pressing a metal plate with a die, or patterning a metal plate by etching. The forming method of the plurality of leads  1  is not specifically limited. The thickness of the leads  1  may be, for example, approximately 0.4 mm to 0.8 mm, without limitation thereto. The leads  1  are spaced apart from one another. 
     In this embodiment, the plurality of leads  1  include the lead  11 , the lead  12 , the lead  13 , the lead  14 , and a plurality of leads  15 . The lead  11 , the lead  12 , the lead  13 , and the lead  14  each constitute a conduction path to the semiconductor chip  4 . The plurality of leads  15  each constitute a conduction path to the control device  5  or the passive element  6 . 
     The lead  11  is located on the substrate  2 , and more accurately on the substrate obverse face  21 , in this embodiment. The lead  11  exemplifies the “first lead” in the present disclosure. The lead  11  is bonded to the bonding section  25  via a bonding material  75 . The bonding material  75  may be any material that is capable of bonding the lead  11  to the bonding section  25 . From the viewpoint of transmission efficiency of the heat from the lead  11  to the substrate  2 , it is preferable that the bonding material  75  has high thermal conductivity and, for example, silver paste, copper paste, or solder may be employed. The bonding material  75  may be formed of an insulative material such as an epoxy-based resin or a silicone-based resin. In the case where the substrate  2  is without the bonding section  25 , the lead  11  may be bonded to the substrate  2 . 
     The configuration of the lead  11  is not specifically limited. In the example shown in  FIG.  5   , the lead  11  includes a bonding portion  111 , a protruding portion  112 , an inclined portion  113 , and a parallel portion  114 . 
     The bonding portion  111  includes an obverse face  111   a  and a reverse face  111   b.  The obverse face  111   a  and the reverse face  111   b  are flat faces perpendicular to the z-direction, and oriented in opposite directions to each other in the z-direction. The obverse face  111   a  is oriented upward in  FIG.  5   . To the obverse face  111   a,  a semiconductor chip  4   a  is bonded. The reverse face  111   b  is oriented downward. The reverse face  111   b  is bonded to the bonding section  25 , via the bonding material  75 . The inclined portion  113  and the parallel portion  114  are covered with the sealing resin  8 . The inclined portion  113  is connected to the bonding portion  111  and the parallel portion  114 , and inclined with respect to the bonding portion  111  and the parallel portion  114 . The parallel portion  114  is connected to the inclined portion  113  and the protruding portion  112 , and parallel to the bonding portion  111 . The protruding portion  112  is connected to the end portion of the parallel portion  114 , and corresponds to the portion of the lead  11  sticking out from the sealing resin  8 . The protruding portion  112  is sticking out in the direction opposite to the bonding portion  111 , in the y-direction. The protruding portion  112  serves, for example, to electrically connect the semiconductor device A 1  to an external circuit. In the illustrated example, the protruding portion  112  is bent to the side to which the obverse face  111   a  of the bonding portion  111  is oriented, in the z-direction. 
     The lead  12  is located on the substrate  2 , and more accurately on the substrate obverse face  21 , in this embodiment. The lead  12  exemplifies the “first lead” in the present disclosure. The lead  12  is bonded to the bonding section  25  via the bonding material  75 . The configuration of the lead  12  is not specifically limited. In this embodiment, the lead  12  is configured similarly to the lead  11 . The lead  12  is bonded to a semiconductor chip  4   b.    
     The lead  13  is located on the substrate  2 , and more accurately on the substrate obverse face  21 , in this embodiment. The lead  13  is bonded to the bonding section  25  via the bonding material  75 . The configuration of the lead  13  is not specifically limited. In this embodiment, the lead  13  is configured similarly to the lead  11 . The lead  13  is not bonded to the semiconductor chip  4 . 
     In this embodiment, the lead  14  is not located on the substrate  2 , and is without a portion corresponding to the bonding portion  111  and the inclined portion  113  of the lead  11 . Here, the configuration of the lead  14  is not limited to the above. 
     The plurality of leads  15  are each located on the substrate  2 , and more accurately on the substrate obverse face  21 , in this embodiment. The leads  15  each exemplify the “second lead” in the present disclosure. The leads  15  are each bonded to the second pad  32  of the conductive section  3 , via a conductive bonding material  76 . The conductive bonding material  76  may be any material that is capable of bonding the lead  15  to the second pad  32 , and electrically connecting the lead  15  and the second pad  32 . For example, silver paste, copper paste, or solder may be employed as the conductive bonding material  76 . The plurality of leads  15  include, as shown in  FIG.  6   , leads  15   a  and  15   b.  The lead  15   a  is conductively bonded to the second pad  32   e.  The lead  15   b  is conductively bonded to the second pad  32   f.    
     The configuration of the lead  15  is not specifically limited. In the example according to this embodiment shown in  FIG.  5   , the lead  15  includes a bonding portion  151 , a protruding portion  152 , an inclined portion  153 , and a parallel portion  154 . 
     The bonding portion  151  includes an obverse face  151   a  and a reverse face  151   b.  The obverse face  151   a  and the reverse face  151   b  are flat faces perpendicular to the z-direction, and oriented in opposite directions to each other in the z-direction. The obverse face  151   a  is oriented upward. The reverse face  151   b  is oriented downward. The reverse face  151   b  is bonded to the second pad  32 , via the conductive bonding material  76 . The inclined portion  153  and the parallel portion  154  are covered with the sealing resin  8 . The inclined portion  153  is connected to the bonding portion  151  and the parallel portion  154 , and inclined with respect to the bonding portion  151  and the parallel portion  154 . The parallel portion  154  is connected to the inclined portion  153  and the protruding portion  152 , and parallel to the bonding portion  151 . The protruding portion  152  is connected to the end portion of the parallel portion  154 , and corresponds to the portion of the lead  15  sticking out from the sealing resin  8 . The protruding portion  152  is sticking out in the direction opposite to the bonding portion  151 , in the y-direction. The protruding portion  152  serves, for example, to electrically connect the semiconductor device A 1  to an external circuit. In the illustrated example, the protruding portion  152  is bent to the side to which the obverse face  151   a  of the bonding portion  151  is oriented, in the z-direction. 
     The two semiconductor chips  4  are each located on one of the leads  1 . To distinguish between the two semiconductor chips  4 , one will be referred to as semiconductor chip  4   a,  and the other will be referred to as semiconductor chip  4   b.  When such distinction is unnecessary, the two semiconductor chips will simply be referred to as semiconductor chip  4 . The type and the function of the semiconductor chip  4  are not specifically limited. In this embodiment, it will be assumed that the semiconductor chip  4  is a power transistor for controlling power. The semiconductor chip  4  is, for example, a metal-oxide-semiconductor field-effect transistor (MOSFET) based on a silicon carbide (SiC) substrate. Here, the semiconductor chip  4  may be a MOSFET based on a silicon (Si) substrate instead of the SiC substrate, and may include, for example, an IGBT element. Further, the semiconductor chip  4  may be a MOSFET containing gallium nitride (GaN). Although the semiconductor device A 1  includes two semiconductor chips  4  in this embodiment, this is merely an example, and the number of semiconductor chips  4  is not specifically limited. 
     The semiconductor chip  4  has a rectangular plate shape as viewed in the z-direction, and includes an element obverse face  41 , an element reverse face  42 , a source electrode  43 , a gate electrode  44 , and a drain electrode  45 . The element obverse face  41  and the element reverse face  42  are oriented in opposite directions to each other, in the z-direction. The element obverse face  41  is oriented upward, and the element reverse face  42  is oriented downward. As shown in  FIG.  3   , the source electrode  43  and the gate electrode  44  are located on the element obverse face  41 . On the element reverse face  42 , the drain electrode  45  is located. The type and location of the source electrode  43 , the gate electrode  44 , and the drain electrode  45  are not specifically limited. 
     As shown in  FIG.  3    and  FIG.  5   , the semiconductor chip  4   a  is located on the lead  11 . The semiconductor chip  4   a  is, as shown in  FIG.  5   , bonded to the lead  11  via a non-illustrated conductive bonding material, with the element reverse face  42  opposed to the lead  11 . Accordingly, the drain electrode  45  of the semiconductor chip  4   a  is conductively connected to the lead  11 , via the conductive bonding material. The conductive bonding material is, for example, formed of silver paste, copper paste, or solder. As shown in  FIG.  3   , the source electrode  43  of the semiconductor chip  4   a  is conductively connected to the lead  12 , via the wires  71 . The wires  71  are, for example, formed of aluminum (Al) or copper (Cu). The material, the line diameter, and the number of wires  71  are not specifically limited. The semiconductor chip  4   b  is located on the lead  12 , as shown in  FIG.  3   . The semiconductor chip  4   b  is bonded to the lead  12  via a non-illustrated conductive bonding material, with the element reverse face  42  opposed to the lead  12 . Accordingly, the drain electrode  45  of the semiconductor chip  4   b  is conductively connected to the lead  12 , via the conductive bonding material. As shown in  FIG.  3   , the source electrode  43  of the semiconductor chip  4   b  is conductively connected to the lead  14 , via the wires  71 . Thus, a bridge circuit is formed, in which the drain electrode  45  of the semiconductor chip  4   a  and the source electrode  43  of the semiconductor chip  4   b  are connected. 
     As shown in  FIG.  3   , the source electrode  43  and the gate electrode  44  of the semiconductor chip  4   a  are each conductively connected to the control device  5   a,  via the wire  72  and the conductive section  3 . The wire  72  is, for example, formed of gold (Au), silver (Ag), copper (Cu), or aluminum (Al). The material, the line diameter, and the number of wires  72  are not specifically limited. The control device  5   a  inputs a drive signal to the gate electrode  44  of the semiconductor chip  4   a.  Likewise, the source electrode  43  and the gate electrode  44  of the semiconductor chip  4   b  are each conductively connected to the control device  5   b,  via the wire  72  and the conductive section  3 . The control device  5   b  inputs a drive signal to the gate electrode  44  of the semiconductor chip  4   b.  When a DC voltage is applied between the lead  11  and the lead  14 , and the drive signal is inputted to the gate electrode  44  of the semiconductor chips  4   a  and  4   b,  a switching signal for switching the voltage according to the drive signal is outputted from the lead  12 . 
     The two control devices  5 , which respectively serve to control the operation of the semiconductor chips  4 , are located on the substrate obverse face  21  of the substrate  2 . To distinguish between the two control devices  5 , one will be referred to as control device  5   a,  and the other will be referred to as control device  5   b.  When such distinction is unnecessary, the two control devices will simply be referred to as control device  5 . The control device  5   a  controls the operation of the semiconductor chip  4   a,  and the control device  5   b  controls the operation of the semiconductor chip  4   b.  As shown in  FIG.  5   , the control device  5  is located between the semiconductor chip  4  and the lead  15 , as viewed in the x-direction. In addition, as shown in  FIG.  3   , the control device  5   a  overlaps with the semiconductor chip  4   a,  and the control device  5   b  overlaps with the semiconductor chip  4   b,  as viewed in the y-direction. The location of the control device  5   a  and the control device  5   b  is not specifically limited. 
     The control device  5  includes a control chip, a die pad, a plurality of wires, a plurality of leads  53 , and a resin  54 . The control chip is an integrated circuit for controlling the operation of the semiconductor chip  4 , and outputs a drive signal for driving the semiconductor chip  4 . The die pad and the plurality of leads  53  are plate-shaped members, for example formed of copper (Cu). On the die pad, the control chip is mounted. The leads  53  are each connected to the control chip, via the wire. The resin  54  covers the entirety of the control chip and the wires, and a part of the leads  53 , and is formed of, for example, an insulative material such as an epoxy resin or silicone gel. 
     As shown in  FIG.  3   , the leads  53  are aligned in the y-direction at predetermined intervals, along the respective edges of the resin  54  in the x-direction. The leads  53  each extend in the x-direction, such that a part of each lead  53  protrudes from one of the edges of the resin  54  in the x-direction. The portion of each lead  53  protruding from the resin  54  is conductively bonded to the first pad  31  of the conductive section  3 . In this embodiment, the control device  5  is a small outline package (SOP). However, the package type of the control device  5  is not limited to SOP and, for example, may be a different type such as a quad flat package (QFP) or a small outline j-lead package (SOJ). The leads  53  are each bonded to the first pad  31  of the conductive section  3 , via the conductive bonding material  76 . 
     The control device  5  includes an opposing face. The opposing face is the face to be opposed to the substrate obverse face  21 , when the control device  5  is mounted on the substrate  2  (see  FIG.  5   ), and the resin  54  is provided over the entirety of the opposing face. In this embodiment, a part of the connection wiring  33  (overlapping wiring) overlaps with the control device  5  as viewed in the z-direction, and is located between the substrate obverse face  21  of the substrate  2  and the opposing face of the control device  5 . control device  5   , Since the control chip is covered with the resin  54 , and the resin  54  is provided over the opposing face, the control chip is prevented from contacting the overlapping wiring. In the case where the control chip is located directly on the substrate  2 , instead of the control device  5 , the control chip contacts the overlapping wiring, which impedes the overlapping wiring from being employed, and forces the connection wiring  33  to make a detour. The size and the shape of the control device  5 , and the number of leads are not specifically limited. Further, the control device  5  may include a plurality of control chips, or another circuit chip other than the control chip. 
     The plurality of passive elements  6  are located on the substrate obverse face  21  of the substrate  2 , and conductively bonded to the conductive section  3  or the lead  1 . The passive elements  6  may be, for example, a resistor, a capacitor, a coil, and a diode. The passive elements  6  include a shunt resistor  6   a  and a thermistor  6   b.    
     The shunt resistor  6   a  is located so as to span between the lead  12  and the lead  13 , and conductively bonded to the lead  12  and the lead  13 . The shunt resistor  6   a  causes the lead  13  to output a shunt current, branched from the current flowing to the lead  12 . 
     The thermistor  6   b  is conductively bonded to the second pad  32   a  and the second pad  32   b  of the conductive section  3 . The second pad  32   a  is conductively connected to the second pad  32   c,  via the wire  73   a.  The second pad  32   b  is conductively connected to the second pad  32   d,  via the wire  73   b.  The wires  73   a  and  73   b  are, for example, formed of gold (Au), silver (Ag), copper (Cu), or aluminum (Al). The material, the line diameter, and the number of wires  73   a  are  73   b  are not specifically limited. In this embodiment, the wires  73   a  and  73   b  are formed of the same material and in the same line diameter, as the wire  72 . The second pad  32   c  is conductively connected to the lead  15   a,  via the connection wiring  33   a  and the second pad  32   e.  The second pad  32   d  is conductively connected to the lead  15   b,  via the connection wiring  33   b  and the second pad  32   f.  Therefore, the second pad  32   a,  the wire  73   a,  the second pad  32   c,  the connection wiring  33   a,  and the second pad  32   e  constitute the conduction path for conductively connecting the thermistor  6   b  and the lead  15   a.  Likewise, the second pad  32   b,  the wire  73   b,  the second pad  32   d,  the connection wiring  33   b,  and the second pad  32   f  constitute the conduction path for conductively connecting the thermistor  6   b  and the lead  15   b.  When a voltage is applied between the lead  15   a  and the lead  15   b,  the thermistor  6   b  outputs a current according to the ambient temperature. In this embodiment, the thermistor  6   b  exemplifies the “electronic parts” or “bonded electronic parts” in the present disclosure. 
     The other passive elements  6  are conductively bonded to the second pad  32  of the conductive section  3 , and electrically connected to the control device  5 , via the connection wiring  33  and the first pad  31 . The type, the location, and the number of such other passive elements  6  are not specifically limited. 
     The sealing resin  8  covers at least the semiconductor chips  4   a  and  4   b,  the control devices  5   a  and  5   b,  the plurality of passive elements  6 , the wires  71 ,  72 ,  73   a,  and  73   b,  a part of each of the plurality of leads  1 , and a part of the substrate  2 . The material of the sealing resin  8  is not specifically limited but, for example, an insulative material such as an epoxy resin or silicone gel may be employed, as appropriate. 
     The sealing resin  8  includes a resin obverse face  81 , a resin reverse face  82 , and four resin side faces  83 . The resin obverse face  81  and the resin reverse face  82  are flat faces perpendicular to the z-direction, and oriented in opposite directions to each other in the z-direction. The resin obverse face  81  is oriented upward, and the resin reverse face  82  is oriented downward. The resin side faces  83  are connected to the resin obverse face  81  and the resin reverse face  82 , and oriented in the x-direction or y-direction. As shown in  FIG.  4   , the substrate reverse face  22  of the substrate  2  is exposed from the resin reverse face  82  of the sealing resin  8 . In this this embodiment, the substrate reverse face  22  and the resin reverse face  82  are flush with each other, as shown in  FIG.  5   . 
     Referring now to  FIG.  9   , an exemplary manufacturing method of the semiconductor device A 1  will be described hereunder. The manufacturing method described hereunder is a process for obtaining the semiconductor device A 1 , and the present disclosure is not limited to the following method. 
     As shown in  FIG.  9   , the manufacturing method of the semiconductor device A 1  includes a conductive section forming process (step S 1 ), a lead frame bonding process (step S 2 ), a semiconductor chip mounting process (step S 3 ), a control device mounting process (step S 4 ), a wire connecting process (step S 5 ), a resin forming process (step S 6 ), and a frame cutting process (step S 7 ). 
     In the conductive section forming process (step S 1 ), first, the substrate  2  is prepared. The substrate  2  is, for example, formed of a ceramic. Then the conductive section  3  and the plurality of bonding sections  25  are formed on the substrate obverse face  21  of the substrate  2 . In this example, the conductive section  3  and the plurality of bonding sections  25  are collectively formed at a time. For example, by printing a metal paste and then sintering the same, the conductive section  3  and the plurality of bonding sections  25 , containing a metal that serves as the conductive material, such as silver (Ag), can be obtained. 
     In the lead frame bonding process (step S 2 ), a bonding paste is printed on the plurality of bonding sections  25 , and a conductive bonding paste is printed on a part of the second pad  32  of the conductive section  3 . The bonding paste and the conductive bonding paste may be, for example, Ag paste or solder paste. Then the lead frame is prepared. The lead frame includes the plurality of leads  1 , and also a frame to which the plurality of leads  1  are connected. The shape of the lead frame is not specifically limited. Then the leads  11 ,  12 , and  13  out of the plurality of leads  1  are opposed to the plurality of bonding sections  25  via the bonding paste. In addition, the plurality of leads  15 , out of the plurality of leads  1 , are opposed to the conductive section  3  (second pad  32 ), via the conductive bonding paste. For example, by heating and then cooling the bonding paste and the conductive bonding paste, the bonding material  75  is obtained from the bonding paste, and the conductive bonding material  76  is obtained from the conductive bonding paste. As result, the leads  11 ,  12 , and  13  are bonded to the plurality of bonding sections  25  via the bonding material  75 , and the plurality of leads  15  are bonded to the conductive section  3 , via the conductive bonding material  76 . 
     In the semiconductor chip mounting process (step S 3 ), the conductive bonding paste is printed on predetermined positions on the lead  11  and the lead  12 . The conductive bonding paste may be, for example, Ag paste or solder paste. Then the semiconductor chip  4   a  is adhered to the conductive bonding paste painted on the lead  11 , and the semiconductor chip  4   ba  is adhered to the conductive bonding paste painted on the lead  12 . Thereafter, for example by heating and then cooling the conductive bonding paste, the conductive bonding material is obtained from the conductive bonding paste. As result, the semiconductor chip  4   a  is bonded to the lead  11  via the conductive bonding material, and the semiconductor chip  4   b  is bonded to the lead  12  via the conductive bonding material. Further, through the similar process, the shunt resistor  6   a  is bonded to the lead  12  and lead  13 , via the conductive bonding material. 
     In the control device mounting process (step S 4 ), the conductive bonding paste is printed on the first pad  31  of the conductive section  3 . The conductive bonding paste may be, for example, Ag paste or solder paste. Then the leads  53  of the control device  5   a  and the control device  5   b  are adhered to the conductive bonding paste. Thereafter, for example by heating and then cooling the conductive bonding paste, the leads  53  of the control device  5   a  and the control device  5   b  are bonded to the first pad  31 , via the conductive bonding material. Further, through the similar process, the thermistor  6   b  and the other passive elements  6  are bonded to the second pad  32  of the conductive section  3 , via the conductive bonding material. 
     In the wire connecting process (step S 5 ), the plurality of wires  71  are connected. In this example, wire materials formed of aluminum (Al) are sequentially connected, for example by a wedge bonding method. Thus, the plurality of wires  71  are obtained. Then the plurality of wires  72  are connected. In this example, wire materials formed of gold (Au) are sequentially connected, for example by a capillary bonding method. Thus, the plurality of wires  72  are obtained. Thereafter, the wires  73   a  and  73   b  are connected. In this example, wire materials formed of gold (Au) are sequentially connected, for example by the capillary bonding method. In this embodiment, the wire  73   a  is connected, by bonding the leading end of the wire material to the second pad  32   c,  moving the capillary while extruding the wire material, and bonding the wire material to the second pad  32   a.  Likewise, the wire  73   b  is connected, by bonding the leading end of the wire material to the second pad  32   d,  moving the capillary while extruding the wire material, and bonding the wire material to the second pad  32   b.  Alternatively, the wire may be bonded to the second pad  32   a  ( 32   b ) first. 
     In the resin forming process (step S 6 ), for example, a part of the lead frame, a part of the substrate  2 , the semiconductor chips  4   a  and  4   b,  the control devices  5   a  and  5   b,  the plurality of passive elements  6 , and the plurality of wires  71 ,  72 ,  73   a,  and  73   b  are enclosed in a mold. A resin material in a liquid state is injected into the space defined by the mold. Then the sealing resin  8  can be obtained, by curing the resin material. 
     In the frame cutting process (step S 7 ), the portions of the lead frame exposed from the sealing resin  8  are cut at predetermined positions. Accordingly, the plurality of leads  1  are divided from one another. Thereafter, for example through a process of bending the plurality of leads  1  as necessary, the semiconductor device A 1  configured as above can be obtained. 
     The advantageous effects provided by the semiconductor device A 1  will be described hereunder. 
     In the foregoing embodiment, the conductive section  3  is formed on the substrate obverse face  21 . The conductive section  3  includes the plurality of first pads  31 , to which the control device  5  is conductively bonded. Accordingly, the conductive section  3  formed on the substrate obverse face  21  can serve as the conduction path to the control device  5 . Therefore, the conduction paths can be formed of finer lines and in higher density, compared with the case of, for example, using a plurality of leads to constitute the conduction path. In addition, the connection wiring  33   c  and the connection wiring  33   d  are provided on the substrate obverse face  21 , between the second pad  32   a  and the second pad  32   c,  and between the second pad  32   b  and the second pad  32   d.  As shown in  FIG.  6   , the wire  73   a  passes over the connection wiring  33   c  and the connection wiring  33   d,  and is conductively bonded to the second pad  32   a  and the second pad  32   c,  so that the second pad  32   a  and the second pad  32   c  are electrically connected to each other. In other words, the wire  73   a  overlaps with the connection wiring  33   c  and the connection wiring  33   d,  as viewed in the z-direction. Likewise, the wire  73   b  passes over the connection wiring  33   c  and the connection wiring  33   d,  and is conductively bonded to the second pad  32   b  and the second pad  32   d,  so that the second pad  32   b  and the second pad  32   d  are electrically connected to each other. In other words, the wire  73   b  overlaps with the connection wiring  33   c  and the connection wiring  33   d,  as viewed in the z-direction. Arranging thus the wires  73   a  and  73   b  allows the conduction path to be shortened, compared with the case where the connection wiring between the second pad  32   a  and the second pad  32   c,  and the connection wiring between the second pad  32   b  and the second pad  32   d  have to be routed through a long detour. In addition, a higher degree of freedom can be attained, in designing the location of the thermistor  6   b  and the routing of the conduction paths. Therefore, a higher degree of integration can be achieved, in the semiconductor device A 1 . Further, the manufacturing cost can be reduced, compared with the case of employing a layered substrate, as the substrate  2 . Here, the wires  73   a  and  73   b  in the example shown in  FIG.  6    exemplify, without limitation thereto, the “conductive section wire” in the present disclosure. 
     In this embodiment, the overlapping wiring, which is a part of the connection wiring  33  of the conductive section  3 , is arranged so as to overlap with the control device  5 , as viewed in the z-direction. Such an arrangement allows the conduction path to be shortened, compared with the case of arranging the conduction path through a detour, so as not to overlap with the control device  5 , and also increases the degree of freedom in designing the conduction path. Consequently, a higher degree of integration can be achieved, in the semiconductor device A 1 . 
     In this embodiment, the plurality of leads  1  have higher thermal conductivity than the substrate  2 , and therefore a decline in heat dissipation performance from the semiconductor chip  4 , which may arise from the presence of the substrate  2 , can be prevented. In addition, the semiconductor chip  4   a  is directly bonded to the lead  11  via the conductive bonding material, and the semiconductor chip  4   b  is directly bonded to the lead  12  via the conductive bonding material. Therefore, the semiconductor chip  4   a  ( 4   b ) and the lead  11  ( 12 ) are electrically connected to each other, and also the heat from the semiconductor chip  4   a  ( 4   b ) can be efficiently transmitted to the lead  11  ( 12 ). Further, since the plurality of leads  1  are exposed from the sealing resin  8 , the conduction path from outside to the semiconductor chip  4  can be secured, and also the heat dissipation characteristic of the semiconductor chip  4  can be improved. In addition, the bonding section  25  is formed on the substrate  2 , and the leads  11 ,  12 , and  13  are bonded to the substrate  2 , via the bonding section  25 . The surface of the bonding section  25  can be made smoother, compared with the rough surface of the substrate obverse face  21  of the substrate  2 , which is formed of a ceramic. Such a configuration prevents formation of undesired minute voids, in the heat transmission path from the leads  11 ,  12 , and  13  to the substrate  2 , thereby further improving the heat dissipation performance of the semiconductor chip  4 . Further, the substrate reverse face  22  of the substrate  2  is exposed from the sealing resin  8 . Therefore, the heat transmitted from the semiconductor chip  4  to the substrate  2  can be more efficiently emitted to outside. 
     In this embodiment, the conductive section  3  and the bonding section  25  are formed of the same conductive material, and therefore the conductive section  3  and the bonding section  25  can be collectively formed at a time, on the substrate  2 . This contributes to improving the manufacturing efficiency of the semiconductor device A 1 . The plurality of leads  15  are bonded to the second pad  32  of the conductive section  3 , via the conductive bonding material  76 . Accordingly, the plurality of leads  15  can be fixed to the substrate  2 , with an increased strength. In addition, the resistance between the plurality of leads  15  and the conductive section  3  can be reduced. 
     Although the substrate  2  is constituted of a single layer in this embodiment, the present disclosure is not limited to such a configuration. For example, the substrate  2  may be a multilayer substrate composed of a plurality of layers. In such a case also, the manufacturing cost can be reduced, for example by reducing the number of layers. 
       FIG.  10    to  FIG.  15    illustrate other embodiments. In these drawings, the elements same as or similar to those of the first embodiment are given the same reference numeral. 
       FIG.  10    is a drawing for explaining a semiconductor device A 2  according to a second embodiment.  FIG.  10    is a partially enlarged plan view of the semiconductor device A 2 , showing the portion corresponding to  FIG.  6   . In  FIG.  10   , the sealing resin  8  is excluded. The semiconductor device A 2  is different from the semiconductor device A 1 , in that the wire  73   a  ( 73   b ) is conductively bonded to the second pad  32   e  ( 32   f ). 
     In the semiconductor device A 2 , the second pads  32   e  and  32   f  each have a rectangular shape elongate in the y-direction, and have a predetermined width (size in the x-direction), along the longitudinal direction. Although the second pad  32   e  ( 33   f ) of the semiconductor device A 1  overlaps in its entirety with the lead  15   a  ( 15   b ), as viewed in the z-direction, a part of the second pad  32   e  ( 33   f ) protrudes from the lead  15   a  ( 15   b ) toward the connection wiring  33   d,  in the semiconductor device A 2 . In the semiconductor device A 2 , the second pads  32   c  and  32   d,  and the connection wirings  33   a  and  33   b  are not provided, and the wire  73   a  ( 73   b ) is directly bonded to the second pad  32   e  ( 32   f ). In the second embodiment, therefore, the lead  15   a  ( 15   b ) is conductively bonded to the second pad  32   e  ( 32   f ), to which the wire  73   a  ( 73   b ) is conductively bonded. 
     In the second embodiment, the connection wiring  33   c  and the connection wiring  33   d  are provided on the substrate obverse face  21  of the substrate  2 , between the second pad  32   a  and the second pad  32   e,  and between the second pad  32   b  and the second pad  32   f.  The wire  73   a  passes over the connection wiring  33   c  and the connection wiring  33   d,  and is conductively bonded to the second pad  32   a  and the second pad  32   e,  so that the second pad  32   a  and the second pad  32   e  are electrically connected to each other. Likewise, the wire  73   b  passes over the connection wiring  33   c  and the connection wiring  33   d,  and is conductively bonded to the second pad  32   b  and the second pad  32   f,  so that the second pad  32   b  and the second pad  32   f  are electrically connected to each other. Such an arrangement allows the conduction path to be shortened, compared with the case where the connection wiring  33  between the second pad  32   a  and the second pad  32   e,  and the connection wiring  33  between the second pad  32   b  and the second pad  32   f  have to be routed through a long detour. In addition, a higher degree of freedom can be attained, in designing the location of the thermistor  6   b  and the routing of the conduction paths. Therefore, a higher degree of integration can be achieved, in the semiconductor device A 2 . Further, the manufacturing cost can be reduced by employing the single-layered substrate  2 , compared with the case of employing multilayer substrate (this also applies to the following embodiments). 
       FIG.  11    is a partially enlarged plan view for explaining a semiconductor device A 3  according to a third embodiment, and shows the portion corresponding to  FIG.  6   . In  FIG.  11   , the sealing resin  8  is excluded. The semiconductor device A 3  is different from the semiconductor device A 1 , in that the wire  73   a  ( 73   b ) is conductively bonded to a different second pad  32   g  ( 32   h ), instead of the second pad  32   a  ( 32   b ). 
     The semiconductor device A 3  includes connection wirings  33   e  and  33   f,  in addition to the second pads  32   g  and  32   h.  The second pad  32   g  is conductively connected to the second pad  32   a,  via the connection wiring  33   e.  Likewise, the second pad  32   h  is conductively connected to the second pad  32   b,  via the, connection wiring  33   f.  The wire  73   a  ( 73   b ) is conductively bonded to the second pad  32   g  ( 32   h ), instead of the second pad  32   a  ( 32   b ) to which the thermistor  6   b  is conductively bonded. 
     In the third embodiment, the connection wiring  33   c  and the connection wiring  33   d  are provided on the substrate obverse face  21 , between the second pad  32   g  and the second pad  32   c,  and between the second pad  32   h  and the second pad  32   d.  The wire  73   a  passes over the connection wiring  33   c  and the connection wiring  33   d,  and is conductively bonded to the second pad  32   g  and the second pad  32   c,  so that the second pad  32   g  and the second pad  32   c  are electrically connected to each other. Likewise, the wire  73   b  passes over the connection wiring  33   c  and the connection wiring  33   d,  and is conductively bonded to the second pad  32   h  and the second pad  32   d,  so that the second pad  32   hb  and the second pad  32   d  are electrically connected to each other. Such an arrangement allows the conduction path to be shortened, compared with the case where the connection wiring  33  between the second pad  32   g  and the second pad  32   c,  and the connection wiring  33  between the second pad  32   h  and the second pad  32   d  have to be routed through a long detour. In addition, a higher degree of freedom can be attained, in designing the location of the thermistor  6   b  and the routing of the conduction paths. Therefore, a higher degree of integration can be achieved, in the semiconductor device A 3 . Here, the wires  73   a  and  73   b  in the example shown in  FIG.  11    exemplify, without limitation thereto, the “conductive section wire” in the present disclosure. 
       FIG.  12    is a partially enlarged plan view for explaining a semiconductor device A 4  according to a fourth embodiment, and shows the portion corresponding to  FIG.  6   . In  FIG.  12   , the sealing resin  8  is excluded. The semiconductor device A 4  is different from the semiconductor device A 1 , in that the thermistor  6   b  is conductively connected the leads  15  ( 15   a,    15   b ) via the conductive section  3  ( 33   a,    33   b ), and that wires ( 73   c,    73   d ) are provided so as to pass over the connection wiring  33 . 
     The semiconductor device A 4  is without the second pads  32   c  and  32   d,  and the wires  73   a  and  73   b  (see  FIG.  6   ). Instead, the connection wiring  33   a  ( 33   b ) is connected to the second pad  32   a  ( 32   b ), in the semiconductor device A 4 . In other words, the second pad  32   a,  the connection wiring  33   a,  and the second pad  32   e  constitute the conduction path between the thermistor  6   b  and the lead  15   a,  and likewise the second pad  32   b,  the connection wiring  33   b,  and the second pad  32   f  constitute the conduction path between the thermistor  6   b  and the lead  15   b.    
     The semiconductor device A 4  includes second pads  32   i,    32   j,    32   k,  and  32   m,  connection wirings  33   g,    33   h,    33   i,  and  33   j,  and the wires  73   c,    73   d,  in place of the connection wirings  33   c  and  33   d  (see  FIG.  6   ). The connection wiring  33   g  has three ends, respectively connected to the first pad  31  (conductively bonded to the control device  5   b ), the second pad  32  (conductively bonded to the lead  15 ), and the second pad  32   i.  The connection wiring  33   h  has two ends, respectively connected to the first pad  31  (conductively bonded to the control device  5   a ) and the second pad  32   i.  The connection wiring  33   i  has two ends, respectively connected to the first pad  31  (conductively bonded to the control device  5   b ) and the second pad  32   k.  The connection wiring  33   j  has three ends, respectively connected to the two first pads  31  (conductively bonded to the control device  5   a ) and the second pad  32   m.  The wire  73   c  passes over the connection wiring  33   a  and the connection wiring  33   b,  and is conductively bonded to the second pad  32   i  and the second pad  32   j.  The wire  73   d  passes over the connection wiring  33   a  and the connection wiring  33   b,  and is conductively bonded to the second pad  32   k  and the second pad  32   m.    
     In the fourth embodiment, the connection wiring  33   a  and the connection wiring  33   b  each extend on the substrate obverse face  21 , so as to cross the region between the second pad  32   i  and the second pad  32   j,  and the region between the second pad  32   k  and the second pad  32   m.  The wire  73   c  passes over the connection wiring  33   a  and the connection wiring  33   b,  and is bonded to the second pad  32   i  and the second pad  32   j,  so that the second pad  32   i  and the second pad  32   j  are electrically connected to each other. Likewise, the wire  73   d  passes over the connection wiring  33   a  and the connection wiring  33   b,  and is bonded to the second pad  32   k  and the second pad  32   m,  so that the second pad  32   k  and the second pad  32   m  are electrically connected to each other. Such an arrangement allows the conduction path to be shortened, compared with the case where the connection wiring  33  between the second pad  32   i  and the second pad  32   j,  and the connection wiring  33  between the second pad  32   k  and the second pad  32   m  have to be routed through a long detour. In addition, a higher degree of freedom can be attained, in designing the location of the thermistor  6   b  and the routing of the conduction paths. Therefore, a higher degree of integration can be achieved, in the semiconductor device A 4 . 
       FIG.  13    is a partially enlarged plan view for explaining a semiconductor device A 5  according to a fifth embodiment, and shows the portion corresponding to  FIG.  12   . In  FIG.  13   , the sealing resin  8  is excluded. The semiconductor device A 5  is different from the semiconductor device A 4 , in that the wire  73   d  overlaps with the thermistor  6   b  as viewed in the z-direction (wire  73   d  passes over the thermistor  6   b ). 
     In the semiconductor device A 5 , the second pad  32   a  is located on the side of the lead  15  in the y-direction, with respect to the second pads  32   k  and  32   m,  and the thermistor  6   b  is oriented such that the long sides are parallel to the y-direction, as viewed in the z-direction. The wire  73   d  passes over the thermistor  6   b  and the connection wiring  33   b,  and is conductively bonded to the second pad  32   k  and the second pad  32   m.    
     In the fifth embodiment, the connection wiring  33   a  and the connection wiring  33   b  are provided on the substrate obverse face  21 , in the region between the second pad  32   i  and the second pad  32   j.  In the region between the second pad  32   k  and the second pad  32   m,  the thermistor  6   b  and the connection wiring  33   b  are provided. The wire  73   c  passes over (across) the connection wiring  33   a  and the connection wiring  33   b,  and is conductively bonded to the second pad  32   i  and the second pad  32   j,  so that the second pad  32   i  and the second pad  32   j  are electrically connected to each other. The wire  73   d  passes over the thermistor  6   b  and the connection wiring  33   b,  and is conductively bonded to the second pad  32   k  and the second pad  32   m,  so that the second pad  32   k  and the second pad  32   m  are electrically connected to each other. Such an arrangement allows the conduction path to be shortened, compared with the case where the connection wiring  33  between the second pad  32   i  and the second pad  32   j,  and the connection wiring  33  between the second pad  32   k  and the second pad  32   m  have to be routed through a long detour. In addition, a higher degree of freedom can be attained, in designing the location of the thermistor  6   b  and the routing of the conduction paths. Therefore, a higher degree of integration can be achieved, in the semiconductor device A 5 . 
       FIG.  14    is a partially enlarged plan view for explaining a semiconductor device A 6  according to a sixth embodiment, and shows the portion corresponding to  FIG.  12   . In  FIG.  14   , the sealing resin  8  is excluded. The semiconductor device A 6  is different from the semiconductor device A 4 , in that the second pad  32   m  (see  FIG.  12   ) is excluded, and that the wire  73   d  is conductively bonded to the connection wiring  33   j.    
     The semiconductor device A 6  is without the second pad  32   m.  The connection wiring  33   j  is only connected to the two first pads  31 , to which the control device  5   a  is  conductively bonded. The wire  73   d  passes over the connection wiring  33   a  and the connection wiring  33   b,  and is conductively bonded to the second pad  32   k  and the connection wiring  33   j.  In this embodiment, the extending direction of the wire  73   d  accords with the extending direction of the portion of the connection wiring  33   j  where the wire  73   d  is bonded. Such a configuration facilitates the connecting work of the wire  73   d,  in the wire connecting process. 
     In the sixth embodiment, the connection wiring  33   a  and the connection wiring  33   b  are provided on the substrate obverse face  21  of the substrate  2 , in the region between the second pad  32   i  and the second pad  32   j,  and in the region between the second pad  32   k  and the connection wiring  33   j.  The wire  73   c  passes over the connection wiring  33   a  and the connection wiring  33   b,  and is conductively bonded to the second pad  32   i  and the second pad  32   j,  so that the second pad  32   i  and the second pad  32   j  are electrically connected to each other. The wire  73   d  passes over the connection wiring  33   a  and the connection wiring  33   b,  and is conductively bonded to the second pad  32   k  and the connection wiring  33   j,  so that the second pad  32   k  and the connection wiring  33   j  are electrically connected to each other. Such an arrangement allows the conduction path to be shortened, compared with the case where the connection wiring  33  between the second pad  32   i  and the second pad  32   j,  and the connection wiring  33  between the second pad  32   k  and the connection wiring  33   j  have to be routed through a long detour. In addition, a higher degree of freedom can be attained, in designing the location of the thermistor  6   b  and the routing of the conduction paths. Therefore, a higher degree of integration can be achieved, in the semiconductor device A 6 . 
     In the first to fifth embodiments, the both ends of the wires  73  ( 73   a,    73   b,    73   c,    73   d ) are each conductively bonded to one of the second pads  32 . In the sixth embodiment, the both ends of the wires  73 , except for the wire  73   d,  are each conductively bonded to one of the second pads  32 . The wires  73  may each be conductively bonded to one of the connection wirings  33 , like the wire  73   d  according to the sixth embodiment. The wires  73  may each have only one end conductively bonded to the connection wiring  33 , or have the both ends conductively bonded to the connection wiring  33 . In this case, the space on the substrate obverse face  21  of the substrate  2  for forming the second pad  32  can be saved, which further contributes to improving the degree of integration in the semiconductor devices A 1  to A 5 . Here, when conductively bonding the wires  73  to the connection wiring  33 , it is preferable to align the extending direction of the wire  73  with the extending direction of the connection wiring  33  to a possible extent, in a view in the z-direction. 
     Although various patterns of the arrangement of the wires  73  have been described in the first to sixth embodiments, the present disclosure is not limited to those examples.  FIG.  15    is a partially enlarged plan view showing a variation of the semiconductor device A 1  according to the first embodiment. In  FIG.  15   , the sealing resin  8  is excluded. 
     In the variation shown in  FIG.  15   , the plurality of first pads  31  include a first pad  31   a.  The first pad  31   a  is longer in the x-direction than the other first pads  31 , and the control device  5   a  and a wire  73   e  are conductively bonded to the first pad  31   a.  The plurality of second pads  32  include second pads  32   n,    32   p,  and  32   q.  To the second pad  32   n,  the passive element  6  and the wire  72  are conductively bonded. To the second pad  32   p,  the wire  73   e  is conductively bonded. To the second pad  32   q,  the passive element  6  is conductively bonded. The plurality of connection wirings  33  include connection wirings  33   k  and  33   m.  The connection wiring  33   k  is connected to the second pad  32   n  and the second pad  32   p.  The connection wiring  33   m  is connected to the first pad  31 , to which the control device  5   a  is conductively bonded, and to the second pad  32   d  to which the passive element  6  is conductively bonded. The plurality of wires  73  include the wire  73   e.  The wire  73   e  passes over the connection wiring  33   m,  and is conductively bonded to the first pad  31   a  and the second pad  32   p.  Accordingly, the wire  73   e  is conductively bonded to the first pad  31   a  to which the control device  5   a  is conductively bonded, and to the second pad  32   p  conductively connected to the second pad  32   n  via the connection wiring  33   k,  the second pad  32   n  being conductively bonded to the passive element  6 . In this variation, the control device  5   a  or the passive element  6  exemplifies the “electronic parts” or “bonded electronic parts” in the present disclosure. 
     In the foregoing variation, the passive elements  6  that are relatively large in size in the y-direction are provided. Accordingly, the second pad  32   n  extends to the position quite close to the control device  5   a,  such that a space for locating the connection wiring  33  is unable to be secured, between the second pad  32   n  and the control device  5   a.  In this case, the second pad  32   n  and the first pad  31   a  can be conductively connected to each other, via the connection wiring  33   k,  the second pad  32   p,  and the wire  73   e.    
     Although the semiconductor devices A 1  to A 6  are formed as the IPM in the first to sixth embodiments, the present disclosure is not limited to those embodiments. The semiconductor device according to the present disclosure may be a semiconductor device other than the IPM. 
     The semiconductor device according to the present disclosure is not limited to the foregoing embodiments. The specific configuration of the elements of the semiconductor device according to the present disclosure may be modified in various manners. For example, a semiconductor device including the conductive section formed on the substrate obverse face, and the wire conductively bonded to each of the two sections spaced apart from each other in the conductive section, is encompassed in the scope of the present disclosure. 
     Appendix 1. 
     A semiconductor device including:
         a substrate having a substrate obverse face and a substrate reverse face oriented in opposite directions to each other in a thickness direction;   a conductive section formed of a conductive material and located on the substrate obverse face, the conductive section including a first section and a second section spaced apart from each other;   a sealing resin covering at least a part of the substrate and an entirety of the conductive section; and   a conductive section wire conductively bonded to the first section and the second section.       

     Appendix 2. 
     The semiconductor device according to appendix 1, wherein the conductive section includes a third section spaced apart from the first section and the second section, and
         the conductive section wire overlaps with the third section, as viewed in the thickness direction.       

     Appendix 3. 
     The semiconductor device according to appendix 1 or 2, further including electronic parts electrically connected to the conductive section, and arranged on the substrate obverse face, wherein the conductive section wire overlaps with the electronic parts, as viewed in the thickness direction. 
     Appendix 4. 
     The semiconductor device according to any one of appendices 1 to 3, further including bonded electronic parts arranged on the substrate obverse face,
         wherein the bonded electronic parts are conductively bonded to the first section.       

     Appendix 5. 
     The semiconductor device according to any one of appendices 1 to 3, wherein the conductive section includes a first wiring connected to the first section, and a fourth section connected to the first wiring. 
     Appendix 6. 
     The semiconductor device according to appendix 5, further including bonded electronic parts arranged on the substrate obverse face, wherein the bonded electronic parts are conductively bonded to the fourth section. 
     Appendix 7. 
     The semiconductor device according to appendix 4 or 6, wherein the bonded electronic parts include a thermistor. 
     Appendix 8. 
     The semiconductor device according to appendix 4 or 6, wherein the bonded electronic parts include a control device. 
     Appendix 9. 
     The semiconductor device according to any one of appendices 1 to 8, further including:
         a first lead arranged on the substrate obverse face, and higher in thermal conductivity than the substrate; and   a semiconductor chip located on the first lead.       

     Appendix 10. 
     The semiconductor device according to appendix 9, further including a bonding section formed on the substrate obverse face, and including the conductive material constituting the conductive section,
         wherein the first lead is bonded to the bonding section, via a bonding material.       

     Appendix 11. 
     The semiconductor device according to appendix 9 or 10, wherein a part of the first lead is covered with the sealing resin, and another part is exposed from the sealing resin. 
     Appendix 12. 
     The semiconductor device according to any one of appendices 9 to 11, further including a second lead spaced apart from the first lead, and bonded to the conductive section via a conductive bonding material,
         wherein a part of the second lead is covered with the sealing resin, and another part is exposed from the sealing resin.       

     Appendix 13. 
     The semiconductor device according to appendix 12, wherein the second lead is conductively bonded to the second section. 
     Appendix 14. 
     The semiconductor device according to appendix 12, wherein the conductive section further includes a second wiring connected to the second section, and a fifth section connected to the second wiring. 
     Appendix 15. 
     The semiconductor device according to appendix 14, wherein the second lead is conductively bonded to the fifth section. 
     Appendix 16. 
     The semiconductor device according to any one of appendices 9 to 15, wherein the semiconductor chip is a power transistor. 
     Appendix 17. 
     The semiconductor device according to any one of appendices 9 to 16, wherein the semiconductor chip includes a reverse face electrode bonded to the first lead. 
     Appendix 18. 
     The semiconductor device according to any one of appendices 1 to 17, wherein the substrate reverse face is exposed from the sealing resin. 
     Appendix 19. 
     The semiconductor device according to any one of appendices 1 to 18, wherein the substrate is formed of a ceramic. 
     REFERENCE SIGNS 
     A 1 , A 2 , A 3 , A 4 , A 5 , A 6 : semiconductor device 
       1 ,  11  to  15 ,  15   a,    15   b:  lead 
       111 : bonding portion 
       111   a:  obverse face 
       111   b:  reverse face 
       112 : protruding portion 
       113 : inclined portion 
       114 : parallel portion 
       151 : bonding portion 
       151   a:  obverse face 
       151   b:  reverse face 
       152 : protruding portion 
       153 : inclined portion 
       154 : parallel portion 
       2 : substrate 
       21 : substrate obverse face 
       22 : substrate reverse face 
       25 ,  251  to  253 : bonding section 
       3 : conductive section 
       31 ,  31   a:  first pad 
       32 ,  32   a  to  32   k,    32   m,    32   n,    32   p,    32   q:  second pad 
       33 ,  33   a  to  33   k,    33   m:  connection wiring 
       4 ,  4   a,    4   b:  semiconductor chip 
       41 : element obverse face 
       42 : element reverse face 
       43 : source electrode 
       44 : gate electrode 
       45 : drain electrode 
       5 ,  5   a,    5   b:  control device 
       53 : lead 
       6 : passive element 
       6   a:  shunt resistor 
       6   b:  thermistor 
       71 : wire 
       72 ,  72   a:  wire 
       73 ,  73   a  to  73   e:  wire 
       75 : bonding material 
       76 : conductive bonding material 
       8 : sealing resin 
       81 : resin obverse face 
       82 : resin reverse face 
       83 : resin side face