Patent Publication Number: US-10785435-B2

Title: Imaging system and imaging device

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This application is a U.S. National Phase of International Patent Application No. PCT/JP2018/001183 filed on Jan. 17, 2018, which claims priority benefit of Japanese Patent Application No. JP 2017-197508 filed in the Japan Patent Office on Oct. 11, 2017 and also claims priority benefit of Japanese Patent Application No. JP 2017-026824 filed in the Japan Patent Office on Feb. 16, 2017. Each of the above-referenced applications is hereby incorporated herein by reference in its entirety. 
     TECHNICAL FIELD 
     The present disclosure relates to an imaging system and an imaging device each of which captures an image. 
     BACKGROUND ART 
     In general, in imaging devices, pixels each including a photodiode are arranged in a matrix, and each of the pixels generates an electrical signal corresponding to an amount of received light. Thereafter, for example, an AD conversion circuit (an analog-to-digital converter) converts the electrical signal (an analog signal) generated in each of the pixels into a digital signal. PTL 1 discloses an imaging device that randomizes a signal read from the pixel array (for example, PTL 1). 
     CITATION LIST 
     Patent Literature 
     PTL 1: U.S. Unexamined Patent Application Publication No. 2014/0078364 
     SUMMARY OF THE INVENTION 
     Imaging devices are desired to perform a self-diagnosis by a BIST (Built-in self test) function to diagnose presence or absence of a malfunction. 
     It is desirable to provide an imaging system and an imaging device that make it possible to perform a self-diagnosis. 
     An imaging system according to an embodiment of the present disclosure includes an imaging device and a processing device. The imaging device is mounted in a vehicle, and captures and generates an image of a peripheral region of the vehicle. The processing device is mounted in the vehicle, and executes processing related to a function of controlling the vehicle on the basis of the image. The imaging device includes a first pixel, a second pixel, a first signal line, a second signal line, a first latch, a second latch, a transfer section, and a diagnosis section. The first signal line is coupled to the first pixel. The second signal line is coupled to the second pixel, and is different from the first signal line. The first latch is coupled to the first signal line, and stores a first digital code. The second latch is coupled to the second signal line, is adjacent to the first latch, and stores a second digital code. The transfer section transfers digital codes outputted from the first latch and the second latch. The diagnosis section performs diagnosis processing on the basis of the digital codes transferred from the first latch and the second latch. The processing device restricts the function of controlling the vehicle on the basis of a result of the diagnosis processing. 
     A first imaging device according to an embodiment of the present disclosure includes a first pixel, a second pixel, a first signal line, a second signal line, a first latch, a second latch, a transfer section, and a diagnosis section. The first signal line is coupled to the first pixel. The second signal line is coupled to the second pixel and different from the first signal line. The first latch is coupled to the first signal line and stores a first digital code. The second latch is coupled to the second signal line, is adjacent to the first latch, and stores a second digital code. The transfer section transfers digital codes outputted from the first latch and the second latch. The diagnosis section performs diagnosis processing on the basis of the digital codes transferred from the first latch and the second latch. 
     A second imaging device according to an embodiment of the present disclosure includes a plurality of signal lines, a plurality of pixels, a plurality of converters, a processor, and a transfer section. The plurality of pixels each applies a pixel voltage to the plurality of signal lines. The plurality of converters is provided corresponding to the plurality of signal lines, each performs AD conversion on the basis of a voltage of a corresponding signal line of the plurality of signal lines to generate a digital code and output the digital code, and sets, to a predetermined digital code, the digital code to be outputted in a first period. The processor performs predetermined processing on the basis of the digital code, and performs diagnosis processing in the first period. The transfer section transfers the digital code outputted from each of the plurality of converters to the processor. 
     In a first imaging system and the first imaging device according to the embodiments of the present disclosure, the transfer section transfers the digital code outputted from the first latch storing the first digital code, and transfers the digital code outputted from the second latch storing the second digital code. Thereafter, the diagnosis section performs the diagnosis processing on the basis of the digital codes transferred from the first latch and the second latch. 
     In the second imaging device according to the embodiment of the present disclosure, each of the plurality of converters performs AD conversion on the basis of the voltage of the corresponding signal line to generate the digital code. Thereafter, the transfer section transfers the digital code outputted from each of the plurality of converters to the processor. Each of the converters sets, to the predetermined digital code, the digital code to be outputted in the first period. 
     According to the first imaging system and the first imaging device according to the embodiments of the present disclosure, the digital codes outputted from the first latch storing the first digital code and the second latch storing the second digital code are transferred, which makes it possible to perform self-diagnosis. 
     According to the second imaging device according to the embodiment of the present disclosure, the digital code to be outputted from each of the converters is set to the predetermined digital code in the first period, which makes it possible to perform self-diagnosis. It is to be noted that effects described here are not necessarily limited and may include any of effects described in the present disclosure. 
    
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         FIG. 1  is a block diagram illustrating a configuration example of an imaging device according to an embodiment of the present disclosure. 
         FIG. 2  is a circuit diagram illustrating a configuration example of a pixel array illustrated in  FIG. 1 . 
         FIG. 3  is another circuit diagram illustrating a configuration example of the pixel array illustrated in  FIG. 1 . 
         FIG. 4  is another circuit diagram illustrating a configuration example of the pixel array illustrated in  FIG. 1 . 
         FIG. 5  is another circuit diagram illustrating a configuration example of the pixel array illustrated in  FIG. 1 . 
         FIG. 6  is a circuit diagram illustrating a configuration example of a voltage generator illustrated in  FIG. 4 . 
         FIG. 7A  is a circuit diagram illustrating a configuration example of one readout section illustrated in  FIG. 4 . 
         FIG. 7B  is a circuit diagram illustrating a configuration example of another readout section illustrated in  FIG. 4 . 
         FIG. 8  is a block diagram illustrating a configuration example of a signal processor illustrated in  FIG. 1 . 
         FIG. 9  is an explanatory diagram illustrating a configuration example of the imaging device illustrated in  FIG. 1 . 
         FIG. 10  is a timing chart illustrating an operation example of the imaging device illustrated in  FIG. 1 . 
         FIGS. 11A   11 B,  110 ,  11 D,  11 E,  11 F,  11 G,  11 H,  11 I and  11 J are timing waveform chart illustrating an operation example of the imaging device illustrated in  FIG. 1 . 
         FIGS. 12A, 12B, 12C, 12D, 12E, 12F, 12G, 12H and 12I  are another timing waveform chart illustrating an operation example of the imaging device illustrated in  FIG. 1 . 
         FIG. 13A  is an explanatory diagram illustrating an operation example of the readout section illustrated in  FIG. 7A . 
         FIG. 13B  is an explanatory diagram illustrating an operation example of the readout section illustrated in  FIG. 7B . 
         FIGS. 14A, 14B, and 14C  is a are timing chart illustrating an operation example of the readout sections illustrated in  FIGS. 13A and 13B . 
         FIGS. 15A, 15B, and 15C  are another timing chart illustrating an operation example of the readout sections illustrated in  FIGS. 13A and 13B . 
         FIG. 16  is an explanatory diagram illustrating an operation example of the imaging device illustrated in  FIG. 1 . 
         FIGS. 17A   17 B,  17 C,  17 D,  17 E,  17 F,  17 G,  17 H,  17 I, and  17 J are another timing waveform chart illustrating an operation example of the imaging device illustrated in  FIG. 1 . 
         FIGS. 18A, 18B, 18C, 18D, 18E, 18F, and 18G  are another timing waveform chart illustrating an operation example of the imaging device illustrated in  FIG. 1 . 
         FIGS. 19A, 19B, 19C, 19D, 19E, 19F, and 19G  are another timing waveform chart illustrating an operation example of the imaging device illustrated in  FIG. 1 . 
         FIGS. 20A, 20B, 20C, 20D, 20E, 20F, and 20G  are another timing waveform chart illustrating an operation example of the imaging device illustrated in  FIG. 1 . 
         FIGS. 21A, 21B, 21C, 21D, 21E, 21F, and 21G  are another timing waveform chart illustrating an operation example of the imaging device illustrated in  FIG. 1 . 
         FIGS. 22A   22 B,  22 C,  22 D,  22 E,  22 F,  22 G,  22 H,  22 I, and  22 J are another timing waveform chart illustrating an operation example of the imaging device illustrated in  FIG. 1 . 
         FIG. 23A  is another explanatory diagram illustrating an operation example of the readout section illustrated in  FIG. 7A . 
         FIG. 23B  is another explanatory diagram illustrating an operation example of the readout section illustrated in  FIG. 7B . 
         FIGS. 24A, 24B, 24C, 24D, and 24E  is a are timing chart illustrating an operation example of the readout sections illustrated in  FIGS. 23A and 23B . 
         FIG. 25A  is another explanatory diagram illustrating an operation example of the readout section illustrated in  FIG. 7A . 
         FIG. 25B  is another explanatory diagram illustrating an operation example of the readout section illustrated in  FIG. 7B . 
         FIGS. 24A, 24B, 24C, 24D, and 24E  is a are timing chart illustrating an operation example of the readout sections illustrated in  FIGS. 25A and 25B . 
         FIG. 27A  is another explanatory diagram illustrating an operation example of the readout section illustrated in  FIG. 7A . 
         FIG. 27B  is another explanatory diagram illustrating an operation example of the readout section illustrated in  FIG. 7B . 
         FIGS. 28A, 28B, 28C, 28D, and 28E  are timing chart illustrating an operation example of the readout sections illustrated in  FIGS. 27A and 27B . 
         FIG. 29  is a circuit diagram illustrating a configuration example of a pixel array according to a modification example. 
         FIG. 30  is a circuit diagram illustrating a configuration example of a pixel array according to another modification example. 
         FIG. 31A  is an explanatory diagram illustrating an operation example of a readout section according to another modification example. 
         FIG. 31B  is another explanatory diagram illustrating an operation example of a readout section according to another modification example. 
         FIGS. 32A, 32B, 32C, 32D, 32E, 32F, 32G, 32H, 32I, 32J, and 32K  is a are timing chart illustrating an operation example of the readout sections illustrated in  FIGS. 31A and 31B . 
         FIG. 33A  is an explanatory diagram illustrating an operation example of a readout section according to another modification example. 
         FIG. 33B  is another explanatory diagram illustrating an operation example of the readout section according to another modification example. 
         FIGS. 34A, 34B, 34C, 34D, 34E, 34F, 34G, 34H, 34I, 34J, and 34K  is a are timing chart illustrating an operation example of the readout sections illustrated in  FIGS. 33A and 33B . 
         FIG. 35  is a block diagram depicting an example of schematic configuration of a vehicle control system. 
         FIG. 36  is a diagram of assistance in explaining an example of installation positions of an outside-vehicle information detecting section and an imaging section. 
         FIG. 37  is an explanatory diagram illustrating a configuration example of an imaging device according to another modification example. 
         FIG. 38  is an explanatory diagram illustrating an example of circuit layouts in an upper substrate and a lower substrate. 
     
    
    
     MODES FOR CARRYING OUT THE INVENTION 
     Some embodiments of the present disclosure are described below in detail with reference to the drawings. It is to be noted that the description is given in the following order. 
     1. Embodiment 
     2. Application Example 
     1. Embodiment 
     [Configuration Example] 
       FIG. 1  illustrates a configuration example of an imaging device (an imaging device  1 ) according to an embodiment. The imaging device  1  includes a pixel array  10 , a scanner  21 , signal generators  22  and  23 , a readout section  40  (readout sections  40 S and  40 N), a controller  50 , and a signal processor  60 . 
     The pixel array  10  includes a plurality of pixels P arranged in a matrix. The plurality of pixels P includes a plurality of pixels P 1 , a plurality of light-shielded pixels P 2 , a plurality of dummy pixels P 3 , and a plurality of dummy pixels P 4 . The pixels P 1  each include a photodiode, and generate a pixel voltage Vpix corresponding to an amount of received light. The light-shielded pixels P 2  each include a pixel that is light-shielded, and detect a dark current of a photodiode, as will be described later. The dummy pixels P 3  and P 4  each include a pixel not including a photodiode. The pixel array  10  has a normal pixel region R 1 , light-shielded pixel regions R 21  and R 22 , and dummy pixel regions R 3  and R 4 . The plurality of pixels P 1  is disposed in the normal pixel region R 1 . The plurality of light-shielded pixels P 2  is disposed in the light-shielded pixel regions R 21  and R 22 . The plurality of dummy pixels P 3  is disposed in the dummy pixel region R 3 . The plurality of dummy pixels P 4  is disposed in the dummy pixel region R 4 . In this example, in the pixel array  10 , the dummy pixel region R 4 , the dummy pixel region R 3 , the light-shielded pixel region R 21 , the light-shielded pixel region R 22 , and the normal pixel region R 1  are disposed in this order from top to bottom in a vertical direction (a longitudinal direction in  FIG. 1 ). 
     The pixel array  10  includes a plurality of signal lines SGL ( 4096  signal lines SGL( 0 ) to SGL( 4095 ) in this example) extending in the vertical direction (the longitudinal direction in  FIG. 1 ). The plurality of signal lines SGL is disposed to penetrate through the normal pixel region R 1 , the light-shielded pixel regions R 21  and R 22 , and the dummy pixel regions R 3  and R 4 . In this example, one column of pixels P and two signal lines SGL are alternately disposed in a horizontal direction (a transverse direction in  FIG. 1 ). Even-numberth signal lines SGL (SGL( 0 ), SGL( 2 ), . . . ) are coupled to the readout section  40 S, and odd-numberth signal lines SGL (SGL( 1 ), SGL( 3 ), . . . ) are coupled to the readout section  40 N. 
     The normal pixel region R 1 , the light-shielded pixel regions R 21  and R 22 , and the dummy pixel regions R 3  and R 4  are described below. 
       FIG. 2  illustrates a configuration example of the normal pixel region R 1 . The pixel array  10  includes a plurality of control lines TGL, a plurality of control lines SLL, and a plurality of control lines RSTL in the normal pixel region R 1 . The control lines TGL extend in the horizontal direction (a transverse direction in  FIG. 2 ), and a control signal TG is applied from the scanner  21  to the control lines TGL. The control lines SLL extend in the horizontal direction, and a control signal SL is applied from the scanner  21  to the control lines SLL. The control lines RSTL extend in the horizontal direction, and a control signal RST is applied from the scanner  21  to the control lines RSTL. 
     The plurality of pixels P 1  includes a plurality of pixels P 1 A and a plurality of pixels P 1 B. The pixels P 1 A and the pixels P 1 B have circuit configurations that are the same as each other. The pixels P 1 A and P 1 B are alternately disposed in the vertical direction (the longitudinal direction in  FIG. 2 ). 
     The pixels P 1  (the pixels P 1 A and P 1 B) each include a photodiode  11  and transistors  12  to  15 . The transistors  12  to  15  each include an N-type MOS (Metal Oxide Semiconductor) transistor in this example. 
     The photodiode  11  serves as a photoelectric converter that generates an amount of charges corresponding to the amount of received light and accumulates the charges therein. The photodiode  11  has an anode grounded and a cathode coupled to a source of the transistor  12 . 
     The transistor  12  has a gate coupled to a corresponding one of the control lines TGL, a source coupled to the cathode of the photodiode  11 , and a drain coupled to a floating diffusion FD. The gate of the transistor  12  of the pixel P 1 A and the gate of the transistor  12  of the pixel P 1 B disposed below the pixel P 1 A are coupled to the same control line TGL. 
     With this configuration, in the pixels P 1 , the transistor  12  is turned to an ON state on the basis of the control signal TG, and the charges generated in the photodiode  11  of the pixel P 1  are transferred to the floating diffusion FD (a charge transfer operation). 
     The transistor  13  has a gate coupled to a corresponding one of the control lines RSTL, a drain supplied with a power source voltage VDD, and a source coupled to the floating diffusion FD. The gate of the transistor  13  of the pixel P 1 A and the gate of the transistor  13  of the pixel P 1 B disposed below the pixel P 1 A are coupled to the same control line control line RSTL. 
     With this configuration, in the pixels P 1 , the transistor  13  is turned to the ON state on the basis of the control signal RST before transfer of charges from the photodiode  11  to the floating diffusion FD, and the power source voltage VDD is supplied to the floating diffusion FD. This causes a voltage of the floating diffusion FD in the pixel P 1  to be reset (a reset operation). 
     The transistor  14  has a gate coupled to the floating diffusion FD, a drain supplied with the power source voltage VDD, and a source coupled to a drain of the transistor  15 . 
     The transistor  15  has a gate coupled to a corresponding one of the control lines SLL, the drain coupled to the source of the transistor  14 , and a source coupled to a corresponding one of the signal lines SGL. The source of the transistor  15  of the pixel P 1 A is coupled to an even-numberth signal line SGL (for example, the signal line SGL( 0 )), and the source of the transistor  15  of the pixel P 1 B is coupled to an odd-numberth signal line SGL (for example, the signal line SGL( 1 )). 
     With this configuration, in the pixels P 1  (the pixels P 1 A and P 1 B), the transistor  15  is turned to the ON state, which causes the transistor  14  to be coupled to a current source  44  (to be described later) of the readout section  40 . This causes the transistor  14  to operate as a so-called source follower and output, as the signal SIG, a voltage corresponding to the voltage of the floating diffusion FD to the signal line SGL through the transistor  15 . Specifically, in a P-phase (Pre-charge phase) period PP after the voltage of the floating diffusion FD is reset, the transistor  14  outputs, as the signal SIG, a reset voltage Vreset corresponding to the voltage of the floating diffusion FD at that time. Moreover, in a D-phase (Data phase) period PD after charges are transferred from the photodiode  11  to the floating diffusion FD, the transistor  14  outputs, as the signal SIG, the pixel voltage Vpix corresponding to the amount of received light. The pixel voltage Vpix corresponds to the voltage of the floating diffusion FD at that time. 
     Next, description is given of the light-shielded pixel regions R 21  and R 22 . As illustrated in  FIG. 1 , two rows of the light-shielding pixels P 2  are disposed in the light-shielded pixel region R 21 , and two rows of the light-shielded pixels P 2  are disposed in the light-shielded pixel region R 22 . A configuration of the light-shielded pixel region R 22  is similar to a configuration of the light-shielded pixel region R 21 , and the light-shielded pixel region R 21  is therefore described below as an example. 
       FIG. 3  illustrates a configuration example of the light-shielded pixel region R 21 . It is to be noted that  FIG. 3  also illustrates the scanner  21  in addition to the light-shielded pixel region R 21  of the pixel array  10 . The pixel array  10  includes the control line TGL, the control line SLL, and the control line RSTL in the light-shielded pixel region R 21 . The control line TGL extends in the horizontal direction (a transverse direction in  FIG. 3 ), and the control signal TG is applied from the scanner  21  to the control line TGL. The control line SLL extends in the horizontal direction, and the control signal SL is applied from the scanner  21  to the control line SLL. The control line RSTL extends in the horizontal direction, and the control signal RST is applied from the scanner  21  to the control line RSTL. 
     The plurality of light-shielded pixels P 2  includes a plurality of light-shielded pixels P 2 A and a plurality of light-shielded pixels P 2 B. The light-shielded pixels P 2 A and the light-shielded pixels P 2 B have circuit configurations that are the same as each other. The light-shielded pixels P 2 A include pixels in an upper row of the two rows of the light-shielded pixels P 2 , and the light-shielded pixels P 2 B include pixels in a lower row of the two rows of the light-shielded pixels P 2 . 
     The light-shielded pixels P 2  (the light-shielded pixels P 2 A and P 2 B) each include the photodiode  11  and the transistors  12  to  15 . The light-shielded pixels P 2  have the same circuit configuration as that of the pixels P 1  ( FIG. 2 ), and are different from the pixels P 1  in that light is shielded not to enter the photodiode  11 . 
     With this configuration, in the light-shielded pixels P 2  (the light-shielded pixels P 2 A and P 2 B), as with the pixels P 1 , the transistor  15  is turned to the ON state, which causes the transistor  14  to output, to the signal line SGL, the signal SIG corresponding to the voltage of the floating diffusion FD through the transistor  15 . The light-shielded pixels P 2  are light-shielded; therefore, the voltage of the floating diffusion FD in the D-phase period PD becomes a voltage corresponding to a dark current of the photodiode  11 . Accordingly, the transistor  14  outputs, as the signal SIG, the pixel voltage Vpix corresponding to the dark current in the D-phase period PD. 
     Next, description is given of the dummy pixel regions R 3  and R 4 . As illustrated in  FIG. 1 , two rows of the dummy pixels P 3  are disposed in the dummy pixel region R 3 , and two rows of the dummy pixels P 4  are disposed in the dummy pixel region R 4 . 
       FIG. 4  illustrates a configuration example of the dummy pixel region R 3 . It is to be noted that  FIG. 4  also illustrates the scanner  21  and the signal generator  22  in addition to the dummy pixel region R 3  of the pixel array  10 . The pixel array  10  includes the control line SLL, a control line VMAL, and a control line VMBL in the dummy pixel region R 3 . The control line SLL extends in the horizontal direction (a transverse direction in  FIG. 4 ), and the control signal SL is applied from the scanner  21  to the control line SLL. The control line VMAL extends in the horizontal direction, and a control signal VMA is applied from a voltage generator  30 A (to be described later) of the signal generator  22  to the control line VMAL. The control line VMBL extends in the horizontal direction, and a control signal VMB is applied from a voltage generator  30 B (to be described later) of the signal generator  22  to the control line VMBL. 
     The plurality of dummy pixels P 3  includes a plurality of dummy pixels P 3 A and a plurality of dummy pixels P 3 B. The dummy pixels P 3 A and the dummy pixels P 3 B have circuit configurations that are the same as each other. The dummy pixels P 3 A include pixels in an upper row of the two rows of the dummy pixels P 3 , and the dummy pixels P 3 B include pixels in a lower row of the two rows of the dummy pixels P 3 . 
     The dummy pixels P 3  (the dummy pixels P 3 A and P 3 B) each have the transistors  14  and  15 . In other words, the dummy pixels P 3  each correspond to the pixel P 1  ( FIG. 2 ) from which the photodiode  11  and the transistors  12  and  13  are removed. 
     In the dummy pixels P 3 A, the transistor  14  has the gate coupled to the control line VMAL, the drain supplied with the power source voltage VDD, and the source coupled to the drain of the transistor  15 . The transistor  15  has the gate coupled to the control line SLL, the drain coupled to the source of the transistor  14 , and the source coupled to an even-numberth signal line SGL (for example, the signal line SGL( 0 )). 
     In the dummy pixels P 3 B, the transistor  14  has the gate coupled to the control line VMBL, the drain supplied with the power source voltage VDD, and the source coupled to the drain of the transistor  15 . The transistor  15  has the gate coupled to the control line SLL, the drain coupled to the source of the transistor  14 , and the source coupled to an odd-numberth signal line SGL (for example, the signal line SGL( 1 )). 
     With this configuration, in the dummy pixels P 3 A, the transistor  15  is turned to the ON state, which causes the transistor  14  to output the signal SIG corresponding to a voltage of the control signal VMA to the signal line SGL through the transistor  15  in the P-phase period PP and the D-phase period PD Likewise, in the dummy pixels P 3 B, the transistor  15  is turned to the ON state, which causes the transistor  14  to output the signal SIG corresponding to a voltage of the control signal VMB to the signal line SGL through the transistor  15  in the P-phase period PP and the D-phase period PD. 
       FIG. 5  illustrates a configuration example of the dummy pixel region R 4 . It is to be noted that  FIG. 5  also illustrates the scanner  21  and the signal generator  23  in addition to the dummy pixel region R 4  of the pixel array  10 . The pixel array  10  includes the control line SLL and a control line SUNL in the dummy pixel region R 4 . The control line SLL extends in the horizontal direction (a transverse direction in  FIG. 5 ), and the control signal SL is applied from the scanner  21  to the control line SLL. The control line SUNL extends in the horizontal direction, and a control signal SUN is applied from the signal generator  23  to the control line SUNL. 
     The plurality of dummy pixels P 4  includes a plurality of dummy pixels P 4 A and a plurality of dummy pixels P 4 B. The dummy pixels P 4 A and the dummy pixels P 4 B have circuit configurations that are the same as each other. The dummy pixels P 4 A include pixels in an upper row of the two rows of the dummy pixels P 4 , and the dummy pixels P 4 B include pixels in a lower row of the two row of the dummy pixels P 4 . 
     The dummy pixels P 4  (the dummy pixels P 4 A and P 4 B) each include the transistors  14  and  15 . The dummy pixels P 4  have the same circuit configuration as that of the dummy pixels P 3  ( FIG. 4 ). The transistor  14  has the gate coupled to the control line SUNL, the drain supplied with the power source voltage VDD, and the source coupled to the drain of the transistor  15 . The transistor  15  has the gate coupled to the control line SLL, the drain coupled to the source of the transistor  14 , and the source coupled to the signal line SGL. The source of the transistor  15  of the dummy pixel P 4 A is coupled to an even-numberth signal line SGL (for example, the signal line SGL( 0 )), and the source of the transistor  15  of the dummy pixel P 4 B is coupled to an odd-numberth signal line SGL (for example, the signal line SGL( 1 )). 
     In the dummy pixels P 4 , as will be described later, in a case where the pixels P 1  in the normal pixel region R 1 , the light-shielded pixels P 2  in the light-shielded pixel regions R 21  and R 22 , and the dummy pixels P 3  in the dummy pixel region R 3  are selected as readout targets, the transistor  15  is turned to the ON state. Thereafter, for example, in a case where the imaging device  1  captures an image of an extremely bright subject, the dummy pixels P 4  each output a voltage corresponding to a voltage of the control signal SUN to the signal line SGL through the transistor  15  in a predetermined period before the P-phase period PP. Thus, in a case where the image of the extremely bright subject is captured, as will be described later, the dummy pixels P 4  each limit the voltage of the signal SIG to prevent the voltage of the signal SIG from becoming too low in the predetermined period before the P-phase period PP. 
     The scanner  21  ( FIG. 1 ) sequentially drives the plurality of pixels P 1  in the normal pixel region R 1  on the basis of an instruction from the controller  50 , and includes, for example, a shift register, an address decoder, etc. Specifically, the scanner  21  sequentially applies the control signal RST to the plurality of control lines RSTL in the normal pixel region R 1 , sequentially applies the control signal TG to the plurality of control lines TGL, and sequentially applies the control signal SL to the plurality of control lines SLL. 
     Moreover, as will be described later, the scanner  21  also has a function of driving the plurality of light-shielded pixels P 2  in the light-shielded pixel regions R 21  and R 22  and the plurality of dummy pixels P 3  in the dummy pixel region R 3  in a blanking period P 20 . 
     Further, as will be described later, in a case where the pixels P 1  in the normal pixel region R 1 , the light-shielded pixels P 2  in the light-shielded pixel regions R 21  and R 22 , and the dummy pixels P 3  in the dummy pixel region R 3  are selected as readout targets, the scanner  21  also has a function of driving the dummy pixels P 4  in the dummy pixel region R 4 . 
     On the basis of an instruction from the controller  50 , the signal generator  22  applies the control signal VMA to the control line VMAL in the pixel array  10 , and applies the control signal VMB to the control line VMBL. As illustrated in  FIG. 4 , the signal generator  22  includes two voltage generators  30  (the voltage generators  30 A and  30 B). The voltage generator  30 A and the voltage generator  30 B have circuit configurations that are the same as each other, and the voltage generator  30 A is therefore described below as an example. 
       FIG. 6  illustrates a configuration example of the voltage generator  30 A. The voltage generator  30 A includes a resistance circuit section  31 , a selector  32 , a temperature sensor  33 , and a selector  34 . The resistance circuit section  31  includes a plurality of resistors coupled in series, and divides the power source voltage VDD to generate a plurality of voltages. The selector  32  selects one from the plurality of voltages generated by the resistance circuit section  31  on the basis of a control signal supplied from the controller  50 , and outputs the selected voltage. The temperature sensor  33  detects a temperature, and generates a voltage Vtemp corresponding to the detected temperature. The selector  34  selects the voltage supplied from the selector  32  or the voltage Vtemp supplied from the temperature sensor  33  on the basis of a control signal supplied from the controller  50 , and outputs the selected voltage as the control signal VMA. 
     The voltage generator  30 A and the voltage generator  30 B are separately supplied with a control signal from the controller  50 . This makes it possible for the voltage generators  30 A and  30 B to generate the control signals VMA and VMB that are the same as each other, or to generate the control signals VMA and VMB that are different from each other. 
     The signal generator  23  applies the control signal SUN to the control line SUNL in the pixel array  10  on the basis of an instruction from the controller  50 . As will be described later, in a case where the imaging device  1  captures an image of an extremely bright subject, the control signal SUN limits the voltage of the signal SIG to prevent the voltage of the signal SIG from becoming too low in a predetermined period before the P-phase period PP. 
     The readout section  40  (the readout sections  40 S and  40 N) performs AD conversion on the basis of the signal SIG supplied from the pixel array  10  through the signal line SGL to generate an image signal DATA 0  (image signals DATA 0 S and DATA 0 N). The readout section  40 S is coupled to the even-numberth signal lines SGL (the signal line SGL( 0 ), SGL( 2 ), SGL( 4 ), . . . ), and is disposed below the pixel array  10  in the vertical direction (the longitudinal direction in  FIG. 1 ) in this example. The readout section  40 N is coupled to the odd-numberth signal lines SGL (the signal lines SGL( 1 ), SGL( 3 ), SGL( 5 ), . . . ), and is disposed above the pixel array  10  in the vertical direction in this example. 
       FIG. 7A  illustrates a configuration example of the readout section  40 S, and  FIG. 7B  illustrates a configuration example of the readout section  40 N. It is to be noted that  FIG. 7A  also illustrates the controller  50  and the signal processor  60  in addition to the readout section  40 S. Likewise,  FIG. 7B  also illustrates the controller  50  and the signal processor  60  in addition to the readout section  40 N. 
     The readout section  40  (the readout sections  40 S and  40 N) includes a plurality of AD (Analog to Digital) converters ADC (AD converters ADC( 0 ), ADC( 1 ), ADC( 2 ), . . . ), a plurality of switch sections SW (switch sections SW( 0 ), SW( 1 ), SW( 2 ), . . . ), and a bus wiring line  100  (bus wiring lines  100 S and  100 N). 
     The AD converters ADC each perform AD conversion on the basis of the signal SIG supplied from the pixel array  10  to convert the pixel voltage Vpix into a digital code CODE. The plurality of AD converters ADC is provided corresponding to the plurality of signal lines SGL. Specifically, in the readout section  40 S ( FIG. 7A ), a 0th AD converter ADC( 0 ) is provided corresponding to a 0th signal line SGL( 0 ), a second AD converter ADC( 2 ) is provided corresponding to a second signal line SGL( 2 ), and a fourth AD converter ADC( 4 ) is provided corresponding to a fourth signal line SGL( 4 ). Likewise, in the readout section  40 N ( FIG. 7B ), a first AD converter ADC( 1 ) is provided corresponding to a first signal line SGL( 2 ), a third AD converter ADC( 3 ) is provided corresponding to a third signal line SGL( 3 ), and a fifth AD converter ADC( 5 ) is provided corresponding to a fifth signal line SGL( 5 ). 
     The AD converters ADC each include capacitive elements  41  and  42 , the current source  44 , a comparator  45 , and a counter  46 . The capacitive element  41  has one end supplied with a reference signal REF supplied from the controller  50 , and another end coupled to a positive input terminal of the comparator  45 . The reference signal REF has a so-called ramp waveform in which a voltage level is gradually decreased with the passage of time in the P-phase period PP and the D-phase period PD. The capacitive element  42  has one end coupled to the signal line SGL and another end coupled to a negative input terminal of the comparator  45 . The current source  44  passes a current having a predetermined current value from the signal line SGL to a ground. The comparator  45  performs comparison between an input voltage at the positive input terminal and an input voltage at the negative input terminal, and outputs a result of the comparison as the signal CMP. The comparator  45  has the positive input terminal supplied with the reference signal REF through the capacitive element  41 , and the negative input terminal supplied with the signal SIG through the capacitive element  42 . The comparator  45  also has a function of performing zero adjustment that causes the positive input terminal and the negative input terminal to be electrically coupled to each other in a predetermined period before the P-phase period PP. The counter  46  performs a counting operation on the basis of the signal CMP supplied from the comparator  45 , and a clock signal CLK and a control signal CC supplied from the controller  50 . With this configuration, the AD converters ADC each perform AD conversion on the basis of the signal SIG, and outputs a count value CNT of the counter  46  as a digital code CODE having a plurality of bits (13 bits in this example). 
     The switch sections SW each supply, to the bus wiring line  100 , the digital code CODE outputted from a corresponding one of the AD converters ADC on the basis of the control signal SEL supplied from the controller  50 . The plurality of switch sections SW is provided corresponding to the plurality of AD converters ADC. Specifically, in the readout section  40 S ( FIG. 7A ), a 0th switch section SW( 0 ) is provided corresponding to the 0th AD converter ADC( 0 ), a second switch section SW( 2 ) is provided corresponding to the second AD converter ADC( 2 ), and a fourth switch section SW( 4 ) is provided corresponding to the fourth AD converter ADC( 4 ). Likewise, in the readout section  40 N ( FIG. 7B ), a first switch section SW( 1 ) is provided corresponding to the first AD converter ADC( 1 ), a third switch section SW( 3 ) is provided corresponding to the third AD converter ADC( 3 ), and a fifth switch section SW( 5 ) is provided corresponding to the fifth AD converter ADC( 5 ). 
     The switch sections SW each are configured with use of the same number (thirteen in this example) of transistors as the number of bits in the digital code CODE in this example. These transistors are subjected to ON/OFF control on the basis of respective bits (control signals SEL[ 0 ] to SEL[ 4095 ]) of the control signal SEL supplied from the controller  50 . Specifically, for example, the respective transistors are turned to the ON state on the basis of the control signal SEL[ 0 ], which causes the 0th switch section SW (SW( 0 )) ( FIG. 7A ) to supply the digital code CODE outputted from the 0th AD converter ADC( 0 ) to the bus wiring line  100 S Likewise, for example, the respective transistors are turned to the ON state on the basis of the control signal SEL[ 1 ], which causes the first switch section SW (SW( 1 )) ( FIG. 7B ) to supply the digital code CODE outputted from the first AD converter ADC( 1 ) to the bus wiring line  100 N. The same applies to the other switch sections SW. 
     The bus wiring line  100 S ( FIG. 7A ) includes a plurality of (thirteen in this example) wiring lines, and transmits the digital codes CODE outputted from the AD converters ADC of the readout section  40 S. The readout section  40 S supplies, to the signal processor  60 , the plurality of digital codes CODE, as the image signal DATA 0 S, supplied from the AD converters ADC of the readout section  40 S with use of the bus wiring line  100 S. 
     Likewise, the bus wiring line  100 N ( FIG. 7B ) includes a plurality of (thirteen in this example) wiring lines, and transmits the digital codes CODE outputted from the AD converters ADC of the readout section  40 N. The readout section  40 N supplies, to the signal processor  60 , the plurality of digital codes CODE, as the image signal DATA 0 N, supplied from the AD converters ADC of the readout section  40 N with use of the bus wiring line  100 N. 
     The controller  50  ( FIG. 1 ) supplies a control signal to the scanner  21 , the signal generators  22  and  23 , the readout section  40  (the readout sections  40 S and  40 N), and the signal processor  60 , and controls operations of these circuits, thereby controlling an operation of the imaging device  1 . 
     The controller  50  includes a reference signal generator  51 . The reference signal generator  51  generates the reference signal REF. The reference signal REF has a so-called ramp waveform in which the voltage level is gradually decreased with the passage of time in the P-phase period PP and the D-phase period PD. The reference signal generator  51  is allowed to change a gradient of the ramp waveform in the reference signal REF and a voltage offset amount OFS. Thereafter, the reference signal generator  51  supplies the generated reference signal REF to the AD converters ADC of the readout section  40  (the readout sections  40 S and  40 N). 
     With this configuration, for example, the controller  50  performs control through supplying a control signal to the scanner  21 , thereby causing the scanner  21  to sequentially drive the plurality of pixels P 1  in the normal pixel region R 1  and to drive the plurality of light-shielded pixels P 2  in the light-shielded pixel regions R 21  and R 22  and the plurality of dummy pixels P 3  in the dummy pixel region R 3  in the blanking period P 20 . Moreover, for example, the controller  50  performs control through supplying a control signal to the scanner  21 , thereby causing the scanner  21  to drive the dummy pixels P 4  in the dummy pixel region R 4  in a case where the pixels P 1  in the normal pixel region R 1 , the light-shielded pixels P 2  in the light-shielded pixel regions R 21  and R 22 , and the dummy pixels P 3  in the dummy pixel region R 3  are selected as readout targets. 
     Moreover, the controller  50  performs control through supplying a control signal to the signal generator  22 , thereby causing the signal generator  22  to apply the control signal VMA to the control line VMAL in the dummy pixel region R 3  and apply the control signal VMB to the control line VMBL. Further, the controller  50  performs control through supplying a control signal to the signal generator  23 , thereby causing the signal generator  23  to apply the control signal SUN to the control line SUNL in the dummy pixel region R 4 . 
     Furthermore, the controller  50  performs control through supplying the reference signal REF, the clock signal CLK, the control signal CC, and the control signal SEL (the control signals SEL[ 0 ] to SEL[ 4095 ]) to the readout section  40  (the readout sections  40 S and  40 N), thereby causing the readout section  40  to generate the image signal DATA 0  (the image signals DATA 0 S and DATA 0 N) on the basis of the signal SIG. 
     Moreover, the controller  50  supplies a control signal to the signal processor  60  to control an operation of the signal processor  60 . 
       FIG. 8  illustrates a configuration example of the signal processor  60 . The signal processor  60  performs predetermined signal processing on the basis of the image signal DATA 0  (the image signals DATA 0 S and DATA 0 N) supplied from the readout section  40  to output a signal-processed image signal as an image signal DATA. Moreover, the signal processor  60  also has functions of performing diagnosis processing on the basis of the image signal DATA 0  (the image signals DATA 0 S and DATA 0 N) and outputting a diagnosis result RES. The signal processor  60  includes processors  70  and  80 , and a diagnosis section  61 . 
     The processor  70  performs dark current correction on the basis of the image signal DATA 0  (the image signals DATA 0 S and DATA 0 N). In the dark current correction, a contribution portion of a dark current of the photodiode  11  is subtracted from the digital codes CODE included in the image signal DATA 0 . The processor  70  includes an average value calculation section  71 , an offset amount calculation section  72 , an average value calculation section  73 , a correction value calculation section  74 , and a correction section  75 . 
     The average value calculation section  71  determines an average value of the digital codes CODE, related to the plurality of light-shielded pixels P 2  in the light-shielded pixel region R 21 , included in the image signal DATA 0  on the basis of an instruction from the controller  50 . In other words, in a case where the digital codes CODE are generated through driving the plurality of light-shielded pixels P 2  in the light-shielded pixel region R 21  by the scanner  21 , and performing AD conversion by the readout section  40  on the basis of the signal SIG, the average value calculation section  71  determines the average value of these digital codes CODE. 
     The offset amount calculation section  72  calculates a voltage offset amount OFS of the reference signal REF in the D-phase period PD on the basis of a result of calculation by the average value calculation section  71 . Thereafter, the offset amount calculation section  72  supplies a result of such calculation to the controller  50 . The controller  50  stores the voltage offset amount OFS in a register, and the reference signal generator  51  of the controller  50  generates the reference signal REF on the basis of the voltage offset amount OFS. Thus, the reference signal generator  51  thereafter generates, in the D-phase period PD, the reference signal REF of which the voltage is shifted by the voltage offset amount OFS. Thereafter, the scanner  21  drives the plurality of light-shielded pixels P 2  in the light-shielded pixel region R 22 , and the readout section  40  performs AD conversion with use of the reference signal REF on the basis of the signal SIG, thereby generating the digital codes CODE. 
     The average value calculation section  73  determines an average value of the digital codes CODE, related to the plurality of light-shielded pixels P 2  in the light-shielded pixel region R 22 , included in the image signal DATA 0  on the basis of an instruction from the controller  50 . The digital codes CODE are generated in the D-phase period PD by the readout section  40  with use of the reference signal REF of which the voltage is shifted by the voltage offset amount OFS. The average value calculation section  73  determines an average value of the thus-generated digital codes CODE. 
     The correction value calculation section  74  calculates a correction value of the digital codes CODE on the basis of a result of calculation by the average value calculation section  73 . 
     The correction section  75  corrects the digital codes CODE, related to the plurality of pixels P 1  in the normal pixel region R 1 , included in the image signal DATA 0  with use of the correction value calculated by the correction value calculation section  74 . 
     With this configuration, the processor  70  determines an influence of the dark current of the photodiode  11  exerted on the digital codes CODE, on the basis of the digital codes CODE related to the plurality of light-shielded pixels P 2  in the light-shielded pixel regions R 21  and R 22 , and subtracts a contribution portion of the dark current from the digital codes CODE related to the plurality of pixels P 1  in the normal pixel region R 1 . 
     For example, in a case where the pixels P 1  in one row or the pixels P 1  in one column do not operate properly, thereby causing a linear streak in an image, the processor  80  performs correction processing on the image. The processor  80  includes a row average value calculation section  81 , a determination section  82 , a horizontal streak correction section  83 , a determination section  84 , a vertical streak correction section  85 , a selection controller  86 , and a selector  87 . 
     The row average value calculation section  81  calculates an average value of the digital codes CODE related to the pixels P 1  in one row in the normal pixel region R 1  on the basis of the image signal supplied from the processor  70 . 
     The determination section  82  determines whether or not a linear streak extending in the horizontal direction is generated, on the basis of an average value of the digital codes CODE in a plurality of rows supplied from the row average value calculation section  81 . Specifically, for example, in a case where a difference between an average value of the digital codes CODE related to the pixels P 1  in a target row and an average value of the digital codes CODE related to the pixels P 1  in a row above the target row is larger than a predetermined value and a difference between the average value of the digital codes CODE related to the pixels P 1  in the target row and an average value of the digital codes CODE related to the pixels P 1  in a row below the target row is larger than a predetermined value, the determination section  82  determines that a linear streak is generated in the target row. Thereafter, the determination section  82  supplies a result of such determination to the selection controller  86 . 
     The horizontal streak correction section  83  calculates the digital codes CODE related to the pixels P 1  in the target row on the basis of the digital codes CODE related to the pixel P 1  in the row above the target row and the digital codes CODE related to the pixels P 1  in the row below the target row. Specifically, for example, the horizontal streak correction section  83  determines an average value of the digital code CODE related to the pixel P 1  above a target pixel P 1  and the digital code related to the pixel P 1  below the target pixel P 1  to determine the digital code CODE related to the target pixel P 1 . 
     The determination section  84  determines whether or not a linear streak extending in the vertical direction is possibly generated, on the basis of the digital code CODE related to the target pixel P 1 , the digital code CODE related to the pixel P 1  on the left of the target pixel P 1 , and the digital code CODE related to the pixel P 1  on the right of the target pixel P 1  included in the image signal supplied from the processor  70 . Specifically, for example, in a case where a difference between the digital code CODE related to the target pixel P 1  and the digital code CODE related to the pixel P 1  on the left of the target pixel P 1  is larger than a predetermined value and a difference between the digital code CODE related to the target pixel P 1  and the digital code CODE related to the pixel P 1  on the right of the target pixel P 1  is larger than a predetermined value, the determination section  84  determines that a linear streak is possibly generated in a column including the target pixel P 1 . Thereafter, the determination section  84  supplies a result of such determination to the selection controller  86 . 
     For example, the vertical streak correction section  85  determines an average value of the digital code CODE related to the pixel P 1  on the right of the target pixel P 1  and the digital code CODE related to the pixel P 1  on the left of the target pixel P 1  to determine the digital code CODE related to the target pixel P 1 . 
     The selection controller  86  generates, on the basis of the results of the determination by the determination sections  82  and  84 , a selection signal used to indicate the digital code CODE to be selected from the digital code CODE supplied from the processor  70 , the digital code CODE supplied from the horizontal streak correction section  83 , and the digital code CODE supplied from the vertical streak correction section  85 . 
     The selector  87  selects, on the basis of the selection signal supplied from the selection controller  86 , the digital code CODE supplied from the processor  70 , the digital code CODE supplied from the horizontal streak correction section  83 , or the digital code CODE supplied from the vertical streak correction section  85 , and outputs the selected digital code CODE. 
     With this configuration, the processor  80  detects a linear streak on the basis of the image signal supplied from the processor  70 , and corrects the digital codes CODE to make the linear streak less noticeable. Thereafter, the processor  80  outputs the thus-processed image signal as the image signal DATA. It is to be noted that in this example, the processor  80  is provided in the imaging device  1 , but this is not limitative. The processor  80  may not be provided in the imaging device  1 , and a signal processor different from the imaging device  1  may perform processing of the processor  80 . 
     It is to be noted that in this example, in a case where the pixels P 1  in one row or the pixels P 1  in one column do not operate properly, thereby causing generation of a linear streak in an image, the processor  80  corrects the digital codes CODE to make the linear streak less noticeable, but this is not limitative. For example, in a case where the pixels P 1  in two adjacent rows do not operate properly, thereby causing generation of a linear streak in the image, the digital codes CODE may be corrected in a similar manner. 
     The diagnosis section  61  performs diagnosis processing on the basis of the image signal DATA 0  (the image signals DATA 0 S and DATA 0 N). Specifically, the diagnosis section  61  performs diagnosis processing through confirming whether or not the digital codes CODE included in the image signal DATA 0  satisfy predetermined specifications, and outputs the diagnosis result RES. 
     In the imaging device  1 , blocks illustrated in  FIG. 1  may be formed in one semiconductor substrate. Moreover, the blocks illustrated in  FIG. 1  may be formed in a plurality of semiconductor substrates. Specifically, for example, as illustrated in  FIG. 9 , the respective blocks in the imaging device  1  may be formed separately in two semiconductor substrates (an upper substrate  201  and a lower substrate  202 ). In this example, the upper substrate  201  and the lower substrate  202  are stacked, and are coupled to each other through a of vias  203  . . . . Specifically, the signal lines SGL in the upper substrate  201  are coupled to the readout section  40  in the lower substrate  202  through a plurality first set of vias (a first coupling section) of the plurality of vias  203 . It is to be noted that the layout of respective circuits is not limited thereto, and, for example, the signal generators  22  and  23  may be formed in the lower substrate  202 . In this case, the plurality of control lines VMAL, VMBL, and SUNL in the upper substrate  201  is coupled to the signal generators  22  and  23  in the lower substrate  202  through a second set of vias (a second coupling section) of the plurality of vias  203 . Such a stacked configuration makes it possible to achieve an advantageous design in terms of layout. Moreover, in the imaging device  1 , for example, even in a case where a short circuit between adjacent ones of the vias  203 , fixing of a voltage, etc. occur, it is possible to diagnose these malfunctions. 
       FIG. 38  illustrates an example of circuit layouts in the upper substrate  201  and the lower substrate  202 . 
     In this example, the pixel array  10  is formed in the upper substrate  201 . In other words, the plurality of pixels P 1  (pixels P 1 A and P 1 B), the plurality of light-shielded pixels P 2  (light-shielded pixels P 2 A and P 2 B), the plurality of dummy pixels P 3  (dummy pixels P 3 A and P 3 B), the plurality of dummy pixels P 4  (dummy pixels P 4 A and P 4 B), the control lines TGL, SLL, RSTL, VMAL, VMBL, and SUNL, and the signal line SGL are formed in the upper substrate  201 . 
     Moreover, electrode regions  201 A,  201 B, and  201 C are provided in the upper substrate  20 . The electrode region  201 A is provided on a lower side of the upper substrate  201 , the electrode region  201 B is provided on an upper side of the upper substrate  201 , and the electrode region  201 C is provided on a left side of the upper substrate  201 . A plurality of electrodes are formed in the electrode region  201 A, and the plurality of electrodes is coupled to, for example, a plurality of even-numberth signal lines SGL in the pixel array  10  through a via such as a TCV (Through Chip Via). A plurality of electrodes is formed in the electrode region  201 B, and the plurality of electrodes is coupled to, for example, a plurality of odd-numberth signal lines SGL in the pixel array  10  through a via such as a TCV. A plurality of electrodes is formed in the electrode region  201 C, and these electrodes are coupled to, for example, the control lines TGL, SLL, RSTL, VMAL, and VMBL in the pixel array  10  through a via such as a TCV. 
     In this example, the scanner  21 , the readout sections  40 S and  40 N, the reference signal generator  51 , and the processor  209  are formed in the lower substrate  202 . Herein, the processor  209  corresponds to circuits other than the reference signal generator  51  in the controller  50 , the signal generators  22  and  23 , and the signal processor  60 . The processor  209  is disposed around a middle in an upward-downward direction in  FIG. 38 . The scanner  21  is disposed on a left side of the processor  209 . The reference signal generator  51  is disposed on a right side of the processor  209 . The readout section  40 S is disposed below the processor  209 . The readout section  40 N is disposed above the processor  209 . The reference signals REF supplied from the reference signal generator  51  to two readout sections  40 S and  40 N desirably have the same waveform in the two readout sections  40 S and  40 N. Hence, a distance from the reference signal generator  51  to the readout section  40 S is desirably equal to a distance from the reference signal generator  51  to the readout section  40 N. It is to be noted that in this example, one reference signal generator  51  is provided, but this is not limitative. For example, two reference signal generators  51  (reference signal generators  51 S and  51 N) may be provided, and the reference signal REF generated by the reference signal generator  51 S may be supplied to the readout section  40 S, and the reference signal REF generated by the reference signal generator  51 N may be supplied to the readout section  40 N. 
     Moreover, electrode regions  202 A,  202 B, and  202 C are provided in the lower substrate  202 . The electrode region  202 A is provided adjacent to the readout section  40 S on a lower side of the lower substrate  202 . The electrode region  202 B is provided adjacent to the readout section  40 N on an upper side of the lower substrate  202 . The electrode region  202 C is provided adjacent to the scanner  21  on a left side of the lower substrate  202 . A plurality of electrodes is formed in the electrode region  202 A, and the plurality of electrodes is coupled to, for example, the readout section  40 S through a via such as a TCV. A plurality of electrodes is formed in the electrode region  202 B, and the plurality of electrodes is coupled to, for example, the readout section  40 N through a via such as a TCV. A plurality of electrodes is formed in the electrode region  202 C, and the plurality of electrodes is coupled to, for example, the scanner  21 , and the signal generators  22  and  23  in the processor  209  through a via such as a TCV. 
     In the imaging device  1 , the upper substrate  201  and the lower substrate  202  are bonded to each other. Thus, the plurality of electrodes in the electrode region  201 A of the upper substrate  201  is electrically coupled to the plurality of electrodes in the electrode region  202 A of the lower substrate  202 , the plurality of electrodes in the electrode region  201 B of the upper substrate  201  is electrically coupled to the plurality of electrodes in the electrode region  202 B of the lower substrate  202 , and the plurality of electrodes in the electrode region  201 C of the upper substrate  201  is electrically coupled to the plurality of electrodes in the electrode region  202 C of the lower substrate  202 . 
     With this configuration, the scanner  21  and the signal generators  22  and  23  in the lower substrate  202  supply the control signals TG, SL, RST, VMA, VMB, and SUN to the pixel array  10  in the upper substrate  201  through the plurality of electrodes in the electrode regions  201 C and  202 C. The pixel array  10  in the upper substrate  201  supplies the signal SIG to the readout sections  40 S and  40 N in the lower substrate  202  through the plurality of electrodes in the electrode regions  201 A and  202 A and the plurality of electrodes in the electrode regions  201 B and  202 B. The readout sections  40 S and  40 N in the lower substrate  202  perform AD conversion on the basis of the signal SIG to generate the image signal DATA 0  (the image signals DATA 0 S and DATA 0 N). The signal processor  60  in the lower substrate  202  performs diagnosis processing on the basis of the image signal DATA 0 , on the basis of the image signal DATA 0 , and outputs the diagnosis result RES. Thus, in the imaging device  1 , as will be described later, for example, even in a case where a short circuit between adjacent ones of the signal lines SGL in the pixel array  10 , a short circuit between adjacent electrodes or adjacent vias around the electrode regions  201 A,  201 B,  201 C,  202 A,  202 B, and  202 C, or fixing of a voltage in the signal lines SGL and the electrodes, etc. occur, it is possible to diagnose these malfunctions. 
     Moreover, disposing the pixel array  10  mainly in the upper substrate  201  in such a manner makes it possible to manufacture the upper substrate  201  with use of a semiconductor manufacturing process specific to pixels. In other words, the upper substrate  201  does not include a transistor except for the pixel array  10 ; therefore, for example, even in a case where an annealing process at 1000 degrees is performed, an influence is not exerted on circuits other than the pixel array  10 . Accordingly, in manufacturing of the upper substrate  201 , it is possible to introduce, for example, a high-temperature process for measures against white spots, and as a result, it is possible to improve characteristics in the imaging device  1 . 
     Herein, the signal line SGL corresponds to a specific example of a “signal line” in the present disclosure. The pixel P 1  corresponds to a specific example of a “pixel” in the present disclosure. The AD converter ADC corresponds to a specific example of a “first latch” and a “second latch” in the present disclosure. The plurality of switch sections SW and the bus wiring lines  100 S and  100 N correspond to a specific example of a “transfer section” in the present disclosure. 
     [Operation and Workings] 
     Next, description is given of an operation and workings of the imaging device  1  according to the present embodiment. 
     (Summary of Overall Operation) 
     First, description is given of a summary of an overall operation of the imaging device  1  with reference to  FIG. 1 . The signal generator  22  generates the control signals VMA and VMB. The signal generator  23  generates the control signal SUN. The scanner  21  sequentially drives the plurality of pixels P 1  in the normal pixel region R 1 . The pixels P 1  in the normal pixel region R 1  output the reset voltage Vreset as the signal SIG in the P-phase period PP, and output, as the signal SIG, the pixel voltage Vpix corresponding to the amount of received light in the D-phase period PD. Moreover, the scanner  21  drives the plurality of light-shielded pixels P 2  in the light-shielded pixel regions R 21  and R 22 , and the plurality of dummy pixels P 3  in the dummy pixel region R 3  in the blanking period P 20 . The light-shielded pixels P 2  in the light-shielded pixel regions R 21  and R 22  output the reset voltage Vreset as the signal SIG in the P-phase period PP, and output, as the signal SIG, the pixel voltage Vpix corresponding to the dark current in the D-phase period PD. The dummy pixel P 3 A in the dummy pixel region R 3  outputs the signal SIG corresponding to the voltage of the control signal VMA in the P-phase period PP and the D-phase period PD, and the dummy pixel P 3 B outputs the signal SIG corresponding to the voltage of the control signal VMB. Moreover, in a case where the pixels P 1  in the normal pixel region R 1 , the light-shielded pixels P 2  in the light-shielded pixel regions R 21  and R 22 , and the dummy pixels P 3  in the dummy pixel region R 3  are selected as readout targets, the scanner  21  drives the dummy pixels P 4  in the dummy pixel region R 4 . 
     The readout section  40  (the readout sections  40 S and  40 N) performs AD conversion on the basis of the signal SIG to generate the image signal DATA 0  (the image signals DATA 0 S and DATA 0 N). The signal processor  60  performs predetermined signal processing on the basis of the image signal DATA 0  to output a signal-processed image signal as the image signal DATA, and performs diagnosis processing on the basis of the image signal DATA 0  to output the diagnosis result RES. The controller  50  supplies the control signal to the scanner  21 , the signal generators  22  and  23 , the readout section  40  (the readout sections  40 S and  40 N), and the signal processor  60  to control operations of these circuits, thereby controlling the operation of the imaging device  1 . 
     (Detailed Operation) 
     In the imaging device  1 , the plurality of pixels P 1  in the normal pixel region R 1  accumulates charges in accordance with the amount of received light, and outputs, as the signal SIG, the pixel voltage Vpix corresponding to the amount of received light. This operation is described in detail below. 
       FIG. 10  illustrates an example of an operation of scanning the pixels P 1  in the normal pixel region R 1 .  FIGS. 11A, 11B, 11C, 11D, 11E, 11F, 11G, 11H, 11I, and 11J  illustrate an operation example of the imaging device  1 , where  FIG. 11A  indicates a waveform of a horizontal synchronization signal XHS,  FIG. 11B  indicates a waveform of a control signal RST(n−1) in an (n−1)th control line RSTL(n−1),  FIG. 11C  indicates a waveform of a control signal TG(n−1) in an (n−1)th control line TGL(n−1),  FIG. 11D  indicates a waveform of a control signal SL(n−1) in an (n−1)th control line SLL(n−1),  FIG. 11E  indicates a waveform of a control signal RST(n) in an nth control line RSTL(n),  FIG. 11F  indicates a waveform of a control signal TG(n) in an nth control line TGL(n),  FIG. 11G  indicates a waveform of a control signal SL(n) in an nth control line SLL(n),  FIG. 11H  indicates a waveform of a control signal RST(n+1) in an (n+1)th control line RSTL(n+1),  FIG. 11I  indicates a waveform of a control signal TG(n+1) in an (n+1)th control line TGL(n+1), and  FIG. 11J  indicates a waveform of a control signal SL(n+1) in an (n+1)th control line SLL(n+1). 
     As illustrated in  FIG. 10 , the imaging device  1  performs accumulation start driving D 1  on the pixels P 1  in the normal pixel region R 1  in order from top in the vertical direction in a period from a timing t 0  to a timing t 1 . 
     Specifically, for example, as illustrated in  FIGS. 11A, 11B, 11C, 11D, 11E, 11F, 11G, 11H, 11I, and 11J , in a horizontal period H starting from a timing t 21 , the scanner  21  generates the control signals RST(n−1) and TG(n−1) each having a pulse waveform ( FIGS. 11B and 11C ). Specifically, the scanner  21  changes voltages of the control signal RST(n−1) and the control signal TG(n−1) from a low level to a high level at a timing t 22 , and changes the voltages of the control signal RST(n−1) and the control signal TG(n−1) from the high level to the low level at a timing t 23 . In the pixel P 1  supplied with the control signals RST(n−1) and TG(n−1), both the transistors  12  and  13  are turned to the ON state at the timing t 22 . This causes the voltage of the floating diffusion FD and the voltage of the cathode of the photodiode  11  to be set to the power source voltage VDD. Thereafter, both the transistors  12  and  13  are turned to the OFF state at the timing t 23 . This causes the photodiode  11  to start accumulating charges in accordance with the amount of received light. Thus, an accumulation period P 10  starts in the pixel P 1 . 
     Next, in the horizontal period H starting from a timing t 24 , the scanner  21  generates the control signals RST(n) and TG(n) each having a pulse waveform ( FIGS. 11E and 11F ). This causes the pixel P 1  supplied with the control signals RST(n) and TG(n) to start accumulating charges in accordance with the amount of received light at a timing t 26 . 
     Next, in the horizontal period H starting from a timing t 27 , the scanner  21  generates the control signals RST(n+1) and TG(n+1) each having a pulse waveform ( FIGS. 11H and 11I ). This causes the pixel P 1  supplied with the control signals RST(n+1) and TG(n+1) to start accumulating charges in accordance with the amount of received light at a timing t 29 . 
     The scanner  21  performs the accumulation start driving D 1  in such a manner to sequentially start accumulation of charges in the pixels P 1 . Thereafter, in the respective pixels P 1 , charges are accumulated in an accumulation period P 10  until readout driving D 2  is performed. 
     Thereafter, as illustrated in  FIG. 10 , the scanner  21  performs the readout driving D 2  on the pixels P 1  in the normal pixel region R 1  in order from top in the vertical direction in a period from a timing t 10  to a timing t 11 . 
     Specifically, for example, as illustrated in  FIGS. 11A, 11B, 11C, 11D, 11E, 11F, 11G, 11H, 11I, and 11J , in the horizontal period H starting from a timing t 31 , the scanner  21  generates the control signals RST(n−1), TG(n−1), and SL(n−1) each having a pulse waveform ( FIGS. 11B, 11C, and 11D ). This causes the pixel P 1  supplied with the control signals RST(n−1), TG(n−1), and SL(n−1) to output the signal SIG, as will be described later. Specifically, this pixel P 1  outputs the reset voltage Vreset as the signal SIG in the P-phase period PP, and outputs the pixel voltage Vpix as the signal SIG in the D-phase period PD. Thereafter, the readout section  40  (the readout sections  40 S and  40 D) performs AD conversion on the basis of the signal SIG to generate the digital code CODE. 
     Next, in the horizontal period H starting from a timing t 32 , the scanner  21  generates the control signals RST(n), TG(n), and SL(n) each having a pulse waveform ( FIGS. 11E, 11F, and 11G ). This causes the pixel P 1  supplied with the control signals RST(n), TG(n), and SL(n) to output the signal SIG, and the readout section  40  performs AD conversion on the basis of the signal SIG to generate the digital code CODE. 
     Next, in the horizontal period H starting from a timing t 33 , the scanner  21  generates the control signals RST(n+1), TG(n+1), and SL(n+1) each having a pulse waveform ( FIGS. 11H, 11I, and 11J ). This causes the pixel P 1  supplied with the control signals RST(n+1), TG(n+1), and SL(n+1) to output the signal SIG, and the readout section  40  performs AD conversion on the basis of the signal SIG to generate the digital code CODE. 
     As described above, the imaging device  1  performs the readout driving D 2 , thereby sequentially performing AD conversion on the basis of the signals SIG (the reset voltage Vreset and the pixel voltage Vpix) from the pixels P 1 . 
     The imaging device  1  repeats such accumulation start driving D 1  and such readout driving D 2 . Specifically, as illustrated in  FIG. 10 , the scanner  21  performs the accumulation start driving D 1  in a period from the timing t 2  to the timing t 3 , and performs the readout driving D 2  in a period from the timing t 12  to the timing t 13 . Moreover, the scanner  21  performs the accumulation start driving D 1  in a period from the timing t 4  to the timing t 5 , and performs the readout driving D 2  in a period from the timing t 14  to the timing t 15 . 
     Next, the readout driving D 2  is described in detail. 
       FIGS. 12A, 12B, 12C, 12D, 12E, 12F, 12G, 12H, and 12I  illustrate an operation example of the readout driving D 2  in the target pixel P 1 , where  FIG. 12A  indicates the waveform of the horizontal synchronization signal XHS,  FIG. 12B  indicates a waveform of the control signal RST,  FIG. 12C  indicates a waveform of the control signal TG,  FIG. 12D  indicates a waveform of the control signal SL,  FIG. 12E  indicates a waveform of the reference signal REF,  FIG. 12F  indicates a waveform of the signal SIG,  FIG. 12G  indicates a waveform of the signal CMP outputted from the comparator  45  of the AD converter ADC,  FIG. 12H  indicates a waveform of the clock signal CLK, and  FIG. 12I  indicates the count value CNT in the counter  46  of the AD converter ADC. Herein, in  FIGS. 12E and 12F , the waveforms of the respective signals are plotted on the same voltage axis. The reference signal REF in  FIG. 12E  indicates a waveform at the positive input terminal of the comparator  45 , and the signal SIG in  FIG. 12F  indicates a waveform at the negative input terminal of the comparator  45 . 
     In the imaging device  1 , in a certain horizontal period (H), first, the scanner  21  performs an reset operation on the pixel P 1 , and the AD converter ADC performs AD conversion on the basis of the reset voltage Vreset outputted from the pixel P 1  in the following P-phase period PP. Thereafter, the scanner  21  performs an charge transfer operation on the pixels P 1 , and the AD converter ADC performs AD conversion on the basis of the pixel voltage Vpix outputted from the pixel P 1  in the D-phase period PD. This operation is described in detail below. 
     First, the horizontal period H starts at a timing t 41 , and then the scanner  21  changes the voltage of the control signal SL from the low level to the high level at a timing t 42  ( FIG. 12D ). Accordingly, in the pixel P 1 , the transistor  15  is turned to the ON state, and the pixel P 1  is electrically coupled to the signal line SGL. 
     Next, at a timing t 43 , the scanner  21  changes the voltage of the control signal RST from the low level to the high level ( FIG. 12B ). Accordingly, in the pixel P 1 , the transistor  13  is turned to the ON state, and the voltage of the floating diffusion FD is set to the power source voltage VDD (the reset operation). Moreover, in a period from a timing t 43  to a timing t 45 , the comparator  45  performs zero adjustment that causes the positive input terminal and the negative input terminal to be coupled to each other. 
     Next, at a timing t 44 , the scanner  21  changes the voltage of the control signal RST from the high level to the low level ( FIG. 12B ). Accordingly, in the pixel P 1 , the transistor  13  is turned to the OFF state. Thereafter, from the timing t 44  onward, the pixel P 1  outputs a voltage (the reset voltage Vreset) corresponding to the voltage of the floating diffusion FD at this time ( FIG. 12F ). 
     Next, at the timing t 45 , the comparator  45  ends the zero adjustment, and electrically disconnects the positive input terminal and the negative input terminal from each other. Thereafter, at this timing t 45 , the reference signal generator  51  changes the voltage of the reference signal REF to a voltage V 1  ( FIG. 12E ). 
     Next, in a period from a timing t 46  to a timing t 48  (the P-phase period PP), the readout section  40  performs AD conversion on the basis of the reset voltage Vreset. Specifically, first, at the timing t 46 , the controller  50  starts generation of the clock signal CLK ( FIG. 12H ). Simultaneously with this, the reference signal generator  51  of the controller  50  starts decreasing the voltage of the reference signal REF from the voltage V 1  by a predetermined change degree (a change pattern) ( FIG. 12E ). Accordingly, the counter  46  of the AD converter ADC starts a counting operation to sequentially change the count value CNT ( FIG. 12I ). 
     Thereafter, at the timing t 47 , the voltage of the reference signal REF falls below the voltage (the reset Vreset) of the signal SIG ( FIGS. 12E and 12F ). Accordingly, the comparator  45  of the AD converter ADC changes the voltage of the signal CMP from the high level to the low level ( FIG. 12G ). As a result, the counter  46  stops the counting operation ( FIG. 12I ). 
     Next, at the timing t 48 , the controller  50  stops generation of the clock signal CLK in association with end of the P-phase period PP ( FIG. 12H ). Simultaneously with this, the reference signal generator  51  stops change of the voltage of the reference signal REF, and changes the voltage of the reference signal REF to a voltage V 2  at the following timing t 49  ( FIG. 12E ). Accordingly, the voltage of the reference signal REF exceeds the voltage (the reset voltage Vreset) of the signal SIG ( FIGS. 12E and 12F ), which causes the comparator  45  of the AD converter ADC to change the voltage of the signal CMP from the low level to the high level ( FIG. 12G ). 
     Next, at a timing t 50 , the counter  46  of the AD converter ADC reverses polarity of the count value CNT on the basis of the control signal CC ( FIG. 12I ). 
     Next, at a timing t 51 , the scanner  21  changes the voltage of the control signal TG from the low level to the high level ( FIG. 12C ). Accordingly, in the pixel P 1 , the transistor  12  is turned to the ON state, and as a result, charges generated in the photodiode  11  are transferred to the floating diffusion FD (the charge transfer operation). Accordingly, the voltage of the signal SIG is decreased ( FIG. 12F ). 
     Thereafter, at a timing t 52 , the scanner  21  changes the voltage of the control signal TG from the high level to the low level ( FIG. 12C ). Accordingly, in the pixel P 1 , the transistor  12  is turned to the OFF state. Thereafter, from the timing t 52  onward, the pixel P 1  outputs a voltage (the pixel voltage Vpix) corresponding to the voltage of the floating diffusion FD at this time ( FIG. 12F ). 
     Next, in a period from a timing t 53  to a timing t 55  (the D-phase period PD), the readout section  40  performs AD conversion on the basis of the pixel voltage Vpix. Specifically, first, at the timing t 53 , the controller  50  starts generation of the clock signal CLK ( FIG. 12H ). Simultaneously with this, the reference signal generator  51  of the controller  50  starts decreasing the voltage of the reference signal REF from the voltage V 2  by a predetermined change degree (a change pattern) ( FIG. 12E ). Accordingly, the counter  46  of the AD converter ADC starts the counting operation to sequentially change the count value CNT ( FIG. 12I ). 
     Thereafter, at the timing t 54 , the voltage of the reference signal REF falls below the voltage (the pixel voltage Vpix) of the signal SIG ( FIGS. 12E and 12F ). Accordingly, the comparator  45  of the AD converter ADC changes the voltage of the signal CMP from the high level to the low level ( FIG. 12G ). As a result, the counter  46  stops the counting operation ( FIG. 12I ). Thus, the AD converter ADC obtains the count value CNT corresponding to a difference between the pixel voltage Vpix and the reset voltage Vreset. Thereafter, the AD converter ADC outputs the count value CNT as the digital code CODE. 
     Next, at the timing t 55 , the controller  50  stops generation of the clock signal CLK in association with end of the D-phase period PD ( FIG. 12H ). Simultaneously with this, the reference signal generator  51  stops change of the voltage of the reference signal REF, and changes the voltage of the reference signal REF to a voltage V 3  at the following timing t 56 , ( FIG. 12E ). Accordingly, the voltage of the reference signal REF exceeds the voltage (the pixel voltage Vpix) of the signal SIG ( FIGS. 12E and 12F ), which causes the comparator  45  of the AD converter ADC to change the voltage of the signal CMP from the low level to the high level ( FIG. 12G ). 
     Next, at a timing t 57 , the scanner  21  changes the voltage of the control signal SL from the high level to the low level ( FIG. 12D ). Accordingly, in the pixel P 1 , the transistor  15  is turned to the OFF state, and the pixel P 1  is electrically separated from the signal line SGL. 
     Thereafter, at a timing t 58 , the counter  46  of the AD converter ADC resets the count value CNT to “0” on the basis of the control signal CC ( FIG. 12I ). 
     As described above, in the imaging device  1 , the counting operation is performed on the basis of the reset voltage Vreset in the P-phase period PP, and after the polarity of the count value CTN is reversed, the counting operation is performed on the basis of the pixel voltage Vpix in the D-phase period PD. This makes it possible for the imaging device  1  to obtain the digital code CODE corresponding to a voltage difference between the pixel voltage Vpix and the reset voltage Vreset. In the imaging device  1 , such correlated double sampling is performed, which makes it possible to remove a noise component included in the pixel voltage Vpix, and as a result, it is possible to improve image quality of a captured image. 
     The readout section  40  (the readout sections  40 S and  40 N) supplies, as the image signal DATA 0  (the image signals DATA 0 S and DATA 0 N), the digital codes CODE outputted from the plurality of AD converters ADC through the bus wiring line  100  (the bus wiring lines  100 S and  100 N). Next, this data transfer operation is described in detail. 
       FIG. 13A  schematically illustrates an example of the data transfer operation in the readout section  40 S, and  FIG. 13B  schematically illustrates an example of the data transfer operation in the readout section  40 N. In  FIGS. 13A and 13B , a thick line indicates a bus wiring line for a plurality of bits (13 bits in this example). In  FIGS. 13A and 13B , for example, “0” in the AD converter ADC indicates the 0th AD converter ADC( 0 ), and “1” indicates the first AD converter ADC( 1 ). 
       FIGS. 14A, 14B, and 14C  illustrate a timing chart of the data transfer operations illustrated in  FIGS. 13A and 13B ,  FIG. 14A  indicates the waveform of the horizontal synchronization signal XHS,  FIG. 14B  indicates even bits of the control signal SEL, and  FIG. 14C  indicates odd bits of the control signal SEL. In  FIG. 14B , for example, “0” indicates that only a “0”th bit (the control signal SEL[ 0 ]) of even bits (the control signals SEL[ 0 ], SEL[ 2 ], SEL[ 4 ], . . . ) of the control signal SEL is active, and the other bits are inactive. Likewise, in  FIG. 14C , for example, “1” indicates that only a “first” bit (the control signal SEL[ 1 ]) of odd bits (the control signals SEL[ 1 ], SEL[ 3 ], SEL[ 5 ], . . . ) of the control signal SEL is active, and the other bits are inactive. 
     As illustrated in  FIG. 14B , the even bits of the control signal SEL become active in order of the control signal SEL[ 0 ], the control signal SEL[ 2 ], and the control signal SEL[ 4 ]. Hence, in the readout section  40 S ( FIG. 13A ), first, the digital code CODE of the 0th AD converter ADC( 0 ) is supplied to the bus wiring line  100 S. Subsequently, the digital code CODE of the second AD converter ADC( 2 ) is supplied to the bus wiring line  100 S. Subsequently, the digital code CODE of the fourth AD converter ADC( 4 ) is supplied to the bus wiring line  100 S. In such a manner, the digital codes CODE are transferred as the image signal DATA 0 S to the signal processor  60  in order from the AD converter ADC on the left (in transfer order F). 
     Likewise, as illustrated in  FIG. 14C , the odd bits of the control signal SEL become active in order of the control signal SEL[ 1 ], the control signal SEL[ 3 ], and the control signal SEL[ 5 ]. Hence, in the readout section  40 N ( FIG. 13B ), first, the digital code CODE of the first AD converter ADC( 1 ) is supplied to the bus wiring line  100 N. Subsequently, the digital code CODE of the third AD converter ADC( 3 ) is supplied to the bus wiring line  100 N. Subsequently, the digital code CODE of the fifth AD converter ADC( 5 ) is supplied to the bus wiring line  100 N. In such a manner, the digital codes CODE are transferred as the image signal DATA 0 N to the signal processor  60  in order from the AD converter ADC on the left (in the transfer order F). 
       FIGS. 15A, 15B, and 15C  illustrate another operation example of the data transfer operation, where  FIG. 15A  indicates the waveform of the horizontal synchronization signal XHS,  FIG. 15B  indicates even bits of the control signal SEL, and  FIG. 15C  indicates odd bits of the control signal SEL. 
     As illustrated in  FIG. 15B , the even bits of the control signal SEL become active in order of the control signal SEL[ 4094 ], the control signal SEL[ 4092 ], and the control signal SEL[ 4090 ]. Hence, in the readout section  40 S, first, the digital code CODE of a 4094th AD converter ADC( 4094 ) is supplied to the bus wiring line  100 S. Subsequently, the digital code CODE of a 4092nd AD converter ADC( 4092 ) is supplied to the bus wiring line  100 S. Subsequently, the digital code CODE of a 4090th AD converter ADC( 4090 ) is supplied to the bus wiring line  100 S. In such a manner, the digital codes CODE are transferred as the image signal DATA 0 S to the signal processor  60  in order from the AD converter ADC on the right. 
     Likewise, as illustrated in  FIG. 15C , the odd bits of the control signal SEL become active in order of the control signal SEL[ 4095 ], the control signal SEL[ 4093 ], and the control signal SEL[ 4091 ]. Hence, in the readout section  40 N, first, the digital code CODE of a 4095th AD converter ADC( 4095 ) is supplied to the bus wiring line  100 N. Subsequently, the digital code CODE of a 4093rd AD converter ADC( 4093 ) is supplied to the bus wiring line  100 N. Subsequently, the digital code CODE of a 4091st AD converter ADC( 4091 ) is supplied to the bus wiring line  100 N. In such a manner, the digital codes CODE are transferred as the image signal DATA 0 N to the signal processor  60  in order from the AD converter ADC on the right. 
     As described above, in the imaging device  1 , it is possible to change the order of transferring the digital codes CODE from the plurality of AD converters ADC to the signal processor  60 . This makes it possible for the imaging device  1  to easily obtain a captured image that is mirror-reversed. 
     (About Self-Diagnosis) 
     In  FIG. 10 , for example, the period from the timing t 11  to the timing t 12  serves as a so-called blanking period P 20  (a vertical blanking period), in which the imaging device  1  does not perform the readout driving D 2 . In other words, in this period, the signal lines SGL do not transmit the reset voltage Vreset and the pixel voltage Vpix related to the pixels P 1  in the normal pixel region R 1 . The imaging device  1  performs a self-diagnosis with use of the blanking period P 20 . Some self-diagnoses are described below as examples. It is to be noted that it is possible for the imaging device  1  to perform one of self-diagnoses to be described below in one blanking period P 20 , and perform a mutually different self-diagnosis for each blanking period P 20 . Moreover, the imaging device  1  may perform, in one blanking period P 20 , a plurality of self-diagnoses of the self-diagnoses to be described below. 
     (Self-Diagnosis A 1 ) 
     In a self-diagnosis A 1 , mainly whether or not it is possible for the signal lines SGL to transmit the signal SIG properly is diagnosed together with a basic operation of the AD converter ADC. Specifically, the voltage generators  30 A and  30 B of the signal generator  22  apply the control signal VMA to the control line VMAL, and apply the control signal VMB to the control line VMBL. Thereafter, the dummy pixels P 3  each output the signal SIG corresponding to the voltages of the control signals VMA and MVB to the signal line SGL in the blanking period P 20 . The readout section  40  performs AD conversion on the basis of the signal SIG to generate the digital code CODE. Thereafter, the diagnosis section  61  performs diagnosis processing on the basis of the digital code CODE. This operation is described in detail below. 
       FIG. 16  illustrates an example of the self-diagnosis A 1 . In the self-diagnosis A 1 , the voltage generator  30 A of the signal generator  22  generates a voltage V 10  in the P-phase period PP, and generates a voltage V 11  that is lower than the voltage V 10  in the D-phase period PD, thereby generating the control signal VMA. Moreover, the voltage generator  30 B generates the voltage V 10  in the P-phase period PP, and generates a voltage V 12  that is lower than the voltage V 11  in the D-phase period PD, thereby generating the control signal VMB. Thus, the voltage generators  30 A and  30 B generate voltages different from each other in the D-phase period PD. In the P-phase period PP and the D-phase period PD, the dummy pixel P 3 A in the dummy pixel region R 3  outputs the signal SIG corresponding to the voltage of the control signal VMA to an even-numberth signal line SGL (for example, the signal line SGL( 0 )) and the dummy pixel P 3 B outputs the signal SIG corresponding to the voltage of the control signal VMB to an odd-numberth signal line SGL (for example, the signal line SGL( 1 )). Hence, in the D-phase period PD, the voltage of the even-numberth signal line SGL (for example, the signal line SGL( 0 )) and the voltage of the odd-numberth signal line SGL (for example, the signal line SGL( 1 )) adjacent to that even-numberth signal line SGL are different from each other. 
     The readout section  40  (the readout sections  40 S and  40 N) performs AD conversion on the basis of the signal SIG to generate the image signal DATA 0  (the image signals DATA 0 S and DATA 0 N), and the diagnosis section  61  of the signal processor  60  performs diagnosis processing on the basis of the image signal DATA 0 , and outputs the diagnosis result RES. 
     The self-diagnosis A 1  is described below while focusing on the dummy pixel P 3  (the dummy pixel P 3 A) coupled to the 0th signal line SGL( 0 ), and the dummy pixel P 3  (the dummy pixel P 3 B) coupled to the first signal line SGL( 1 ). 
       FIGS. 17A, 17B, 17C, 17D, 17E, 17F, 17G, 17H, 17I, and 17J  illustrate an operation of the self-diagnosis A 1 , where  FIG. 17A  indicates the waveform of the horizontal synchronization signal XHS,  FIG. 17B  indicates the waveform of the control signal SL,  FIG. 17C  indicates a waveform of the control signal VMA,  FIG. 17D  indicates a waveform of the control signal VMB,  FIG. 17E  indicates the waveform of the reference signal REF,  FIG. 17F  indicates a waveform of the signal SIG (the signal SIG( 0 )) in the signal line SGL( 0 ),  FIG. 17G  indicates a waveform of the signal SIG (the signal SIG( 1 )) in the first signal line SGL( 1 ),  FIG. 17H  indicates the waveform of the clock signal CLK,  FIG. 17I  indicates the count value (the count value CNT( 0 )) in the counter  46  of the 0th AD converter ADC( 0 ), and  FIG. 17J  indicates the count value (the count value CNT( 1 )) in the counter  46  of the first AD converter ADC( 1 ). Herein, in  FIGS. 17C and 17D , the waveforms of the respective signals are plotted on the same voltage axis. Likewise, in  FIGS. 17E, 17F, and 17G , the waveforms of the respective signals are plotted on the same voltage axis. 
     First, the horizontal period H within the blanking period P 20  starts at a timing t 61 , and then the scanner  21  changes the voltage of the control signal SL from the low level to the high level at a timing t 62  ( FIG. 17B ). Accordingly, in the dummy pixels P 3 A and P 3 B, the transistors  15  are turned to the ON state, which causes the dummy pixel P 3 A to be electrically coupled to the signal line SGL( 0 ), and causes the dummy pixel P 3 B to be electrically coupled to the signal line SGL( 1 ). Hence, from this timing t 62  onward, the dummy pixel P 3 A outputs, as the signal SIG( 0 ), a voltage corresponding to the voltage (the voltage V 10 ) of the control signal VMA ( FIGS. 17C and 17F ), and the dummy pixel P 3 B outputs, as the signal SIG( 1 ), a voltage corresponding to the voltage (the voltage V 10 ) of the control signal VMB ( FIGS. 17D and 17G ). 
     Thereafter, the comparator  45  performs zero adjustment that causes the positive input terminal and the negative input terminal to be electrically coupled to each other in a period from a timing t 63  to a timing t 64 . 
     Next, at the timing t 64 , the comparator  45  ends the zero adjustment to electrically disconnect the positive input terminal and the negative input terminal from each other. Thereafter, at the timing t 64 , the reference signal generator  51  changes the voltage of the reference signal REF to the voltage V 1 . 
     Next, in a period from a timing t 65  to a timing t 67  (the P-phase period PP), the readout section  40  performs AD conversion. Specifically, first, at the timing t 65 , the controller  50  starts generation of the clock signal CLK ( FIG. 17H ). Simultaneously with this, the reference signal generator  51  of the controller  50  starts decreasing the voltage of the reference signal REF from the voltage V 1  by a predetermined change degree ( FIG. 17E ). The counter  46  of the AD converter ADC( 0 ) starts the counting operation, and sequentially changes the count value CNT( 0 ) ( FIG. 17I ). Likewise, the counter  46  of the AD converter ADC( 1 ) starts the counting operation, and sequentially changes the count value CNT( 1 ) ( FIG. 17J ). 
     Thereafter, at a timing t 66 , in a case where the voltage of the reference signal REF falls below the voltage of the signal SIG( 0 ) ( FIGS. 17E and 17F ), the counter  46  of the AD converter ADC( 0 ) stops the counting operation on the basis of the signal CMP ( FIG. 17I ). Likewise, at this timing t 66 , in a case where the voltage of the reference signal REF falls below the voltage of the signal SIG( 1 ) ( FIGS. 17E and 17G ), the counter  46  of the AD converter ADC( 1 ) stops the counting operation on the basis of the signal CMP ( FIG. 17J ). 
     Next, at the timing t 67 , the controller  50  stops generation of the clock signal CLK in association with end of the P-phase period PP ( FIG. 17H ). Simultaneously with this, the reference signal generator  51  stops change of the voltage of the reference signal REF, and changes the voltage of the reference signal REF to the voltage V 2  at the following timing t 68  ( FIG. 17E ). 
     Next, at a timing t 69 , the counter  46  of the AD converter ADC( 0 ) reverses polarity of the count value CNT( 0 ) on the basis of the control signal CC ( FIG. 17I ), and the counter  46  of the AD converter ADC( 1 ) reverses polarity of the count value CNT( 1 ) on the basis of the control signal CC in a similar manner ( FIG. 17J ). 
     Next, at a timing t 70 , the voltage generator  30 A of the signal generator  22  changes the voltage of the control signal VMA to the voltage V 11  ( FIG. 17C ), and the voltage generator  30 B changes the voltage of the control signal VMB to the voltage V 12  ( FIG. 17D ). Accordingly, the voltages of the signals SIG( 0 ) and SIG( 1 ) are decreased ( FIGS. 17F and 17G ). 
     Next, in a period from a timing t 71  to a timing t 74  (the D-phase period PD), the readout section  40  performs AD conversion. Specifically, first, at the timing t 71 , the controller  50  starts generation of the clock signal CLK ( FIG. 17H ). Simultaneously with this, the reference signal generator  51  of the controller  50  starts decreasing the voltage of the reference signal REF from the voltage V 2  by a predetermined change degree ( FIG. 17E ). Accordingly, the counter  46  of the AD converter ADC( 0 ) starts the counting operation to sequentially change the count value CNT( 0 ) ( FIG. 17I ), and the counter  46  of the AD converter ADC( 1 ) starts the counting operation to sequentially change the count value CNT( 1 ) in a similar manner ( FIG. 17J ). 
     Thereafter, at the timing t 72 , in a case where the voltage of the reference signal REF falls below the voltage of the signal SIG( 0 ) ( FIGS. 17E and 17F ), the counter  46  of the AD converter ADC( 0 ) stops the counting operation ( FIG. 17I ). Thereafter, the AD converter ADC( 0 ) outputs the count value CNT( 0 ) as the digital code CODE. 
     Moreover, at the timing t 73 , in a case where the voltage of the reference signal REF falls below the voltage of the signal SIG( 1 ) ( FIGS. 17E and 17G ), the counter  46  of the AD converter ADC( 1 ) stops the counting operation ( FIG. 17J ). Thereafter, the AD converter ADC( 1 ) outputs the count value CNT( 1 ) as the digital code CODE. 
     Next, at the timing t 74 , the controller  50  stops generation of the clock signal CLK in association with end of the D-phase period PD ( FIG. 17H ). Simultaneously with this, the reference signal generator  51  stops change of the voltage of the reference signal REF, and changes the voltage of the reference signal REF to the voltage V 3  at the following timing t 75  ( FIG. 17E ). 
     Next, at a timing t 76 , the scanner  21  changes the voltage of the control signal SL from the high level to the low level ( FIG. 17B ). Accordingly, in the dummy pixels P 3 A and P 3 B, the transistors  15  are turned to the OFF state, which causes the dummy pixel P 3 A to be electrically separated from the signal line SGL( 0 ), and causes the dummy pixel P 3 B to be electrically separated from the signal line SGL( 1 ). 
     Thereafter, at a timing t 77 , the counter  46  of the AD converter ADC( 0 ) resets the count value CNT( 0 ) to “0” on the basis of the control signal CC ( FIG. 17I ), and the counter  46  of the AD converter ADC( 1 ) resets the count value CNT( 1 ) to “0” on the basis of the control signal CC in a similar manner ( FIG. 17J ). 
     The readout section  40  (the readout sections  40 S and  40 N) generates the image signal DATA 0  (the image signals DATA 0 S and DATA 0 N) including the digital codes CODE generated by AD conversion, and the diagnosis section  61  of the signal processor  60  performs diagnosis processing on the basis of the image signal DATA 0 . 
     It is possible for the diagnosis section  61  to diagnose, on the basis of the digital codes CODE, for example, whether or not the signal line SGL in the pixel array  10  is broken. Specifically, it is possible for the diagnosis section  61  to diagnose whether or not the signal line SGL is broken, through confirming, for example, whether or not a value of the generated digital code CODE falls within a predetermined range corresponding to the voltages V 11  and V 12  having fixed voltage values that are different from each other. In particular, as illustrated in  FIG. 9 , in a case where the upper substrate  201  in which the pixel array  10  is formed, and the lower substrate  202  in which the readout section  40  is formed are coupled to each other through the vias  203 , it is possible for the diagnosis section  61  to diagnose, on the basis of the digital codes CODE, for example, whether or not poor coupling by the vias  203  occurs. 
     Moreover, it is possible for the diagnosis section  61  to diagnose, on the basis of the digital codes CODE, for example, whether or not a short circuit between adjacent ones of the signal lines SGL occurs. In particular, the signal generator  22  sets the voltages of the control signals VMA and VMB to voltages different from each other in the D-phase period PD, which causes the voltage of an even-numberth signal line SGL (for example, the signal line SGL( 0 )) and the voltage of an odd-numberth signal line SGL (for example, the signal line SGL( 1 )) adjacent to that even-numberth signal line SGL to be different from each other. Accordingly, for example, in a case where a short circuit between these signal lines SGL occurs, the digital codes CODE become the same. It is possible for the diagnosis section  61  to diagnose, on the basis of the digital codes CODE, whether or not a short circuit between the adjacent signal lines SGL occurs. 
     Further, it is possible for the diagnosis section  61  to diagnose, on the basis of the digital codes CODE, for example, whether or not a short circuit between the signal line SGL and another wiring line such as a power source ling or a ground line occurs. In other words, in a case where such a short circuit occurs, the voltage of the signal line SGL is fixed to a voltage that is the same as a predetermined voltage in the short-circuited wiring line (such as the power source line), which causes the digital code CODE to have a value corresponding to the predetermined voltage. It is possible for the diagnosis section  61  to diagnose, on the basis of the digital codes CODE, whether or not a short circuit between the signal line SGL and another wiring line occurs. 
     Furthermore, it is possible for the diagnosis section  61  to diagnose, on the basis of the digital codes CODE, whether or not the current source  44  is coupled to the signal line SGL, or whether or not a short circuit between the current source  44  and another wiring line occurs. 
     Moreover, it is possible for the diagnosis section  61  to diagnose a dynamic range of the imaging device  1 , for example, through appropriately setting the voltages V 11  and V 12 . Specifically, for example, it is possible for the diagnosis section  61  to set the voltage V 12  to a voltage corresponding to a highlight. 
     Further, it is possible for the diagnosis section  61  to diagnose characteristics of the AD converter ADC on the basis of the digital codes CODE. Specifically, for example, it is possible for the diagnosis section  61  to diagnose whether or not AD conversion is performable in the P-phase period PP. In other words, the P-phase period PP has a shorter time length than the D-phase period PD; therefore, an operation margin is small. Accordingly, it is possible for the diagnosis section  61  to diagnose the operation margin in the P-phase period, for example, through confirming the count value CNT( 0 ) after end of the P-phase period PP in a case where the voltage V 10  is set to various voltages. 
     (Self-Diagnosis A 2 ) 
     In order to capture an image of a dark subject or a bright subject, the imaging device  1  changes a change degree (a change pattern) of the voltage of the reference signal REF to change a conversion gain in the AD converter ADC. In a self-diagnosis A 2 , whether or not the reference signal generator  51  is allowed to change the change degree of the voltage of the reference signal REF is diagnosed. Specifically, in the blanking period P 20 , the reference signal generator  51  changes the change degree of the voltage of the reference signal REF in the P-phase period PP and the D-phase period PD. In this example, the signal generator  22  generates the control signals VMA and VMB that are the same as each other. Thereafter, the dummy pixel P 3  outputs the signal SIG corresponding to the voltages of the control signals VMA and VMB to the signal line SGL in the blanking period P 20 . The readout section  40  performs AD conversion on the basis of the signal SIG with use of the reference signal REF having a changed change degree to generate the digital code CODE. Thereafter, the diagnosis section  61  performs diagnosis processing on the basis of the digital code CODE. This operation is described in detail below. 
       FIGS. 18A, 18B, 18C, 18D, 18E, 18F, and 18G  illustrate an operation example of the self-diagnosis A 2 , where  FIG. 18A  indicates the waveform of the horizontal synchronization signal XHS,  FIG. 18B  indicates the waveform of the control signal SL,  FIG. 18C  indicates the waveform of the control signal VMA,  FIG. 18D  indicates the waveform of the reference signal REF,  FIG. 18E  indicates the waveform of the signal SIG (the signal SIG( 0 )) in the signal line SGL( 0 ),  FIG. 18F  indicates the waveform of the clock signal CLK, and  FIG. 18G  indicates the count value CNT (the count value CNT( 0 ) in the counter  46  of the 0th AD converter ( 0 ). 
     In this example, the reference signal generator  51  generates the reference signal REF having a smaller change degree of the voltage than that in the self-diagnosis A 1 . It is to be noted that in  FIGS. 18A, 18B, 18C, 18D, 18E, 18F, and 18G , for convenience of description, the reference signal REF in the self-diagnosis A 1  is indicated by a broken line. 
     First, at the timing t 61 , the horizontal period H within the blanking period P 20  starts, and then the scanner  21  changes the voltage of the control signal SL from the low level to the high level at the timing t 62  ( FIG. 18B ). This causes the dummy pixel P 3 A to output, as the signal SIG( 0 ), a voltage corresponding to the voltage (the voltage V 10 ) of the control signal VMA from the timing t 62  onward ( FIGS. 18C and 18E ). 
     Next, the comparator  45  performs zero adjustment that causes the positive input terminal and the negative input terminal to be electrically coupled to each other in the period from the timing t 63  to the timing t 64 . Thereafter, at the timing t 64 , the reference signal generator  51  changes the voltage of the reference signal REF to a voltage V 4  ( FIG. 18D ). 
     Thereafter, in the period from the timing t 65  to the timing t 67  (the P-phase period PP), the readout section  40  performs AD conversion. At the timing t 65 , the reference signal generator  51  of the controller  50  starts decreasing the voltage of the reference signal REF from the voltage V 4  by a predetermined change degree ( FIG. 18D ). The counter  46  of the AD converter ADC( 0 ) starts the counting operation at the timing t 65 , and stops the counting operation at the timing t 66  ( FIG. 18G ). 
     Next, the reference signal generator  51  stops change of the voltage of the reference signal REF at the timing t 67 , and changes the voltage of the reference signal REF to the voltage V 5  at the following timing t 68  ( FIG. 18D ). Thereafter, at the timing t 69 , the counter  46  of the AD converter ADC( 0 ) reverses polarity of the count value CNT( 0 ) on the basis of the control signal CC ( FIG. 18G ). 
     Next, at the timing t 70 , the voltage generator  30 A of the signal generator  22  changes the voltage of the control signal VMA to a voltage V 13  ( FIG. 18C ). Accordingly, the voltage of the signal SIG( 0 ) is decreased ( FIG. 18E ). 
     Next, in the period from the timing t 71  to the timing t 74  (the D-phase period PD), the readout section  40  performs AD conversion. At the timing t 71 , the reference signal generator  51  of the controller  50  starts decreasing the voltage of the reference signal REF from the voltage V 5  by a predetermined change degree ( FIG. 18D ). The counter  46  of the AD converter ADC( 0 ) starts the counting operation at the timing t 71 , and stops the counting operation at the timing t 72  ( FIG. 18G ). Thereafter, the AD converter ADC( 0 ) outputs the count value CNT( 0 ) as the digital code CODE. 
     Next, the reference signal generator  51  stops change of the voltage of the reference signal REF at the timing t 74 , and changes the voltage of the reference signal REF to a voltage V 6  at the following timing t 75  ( FIG. 18D ). 
     Thereafter, at the timing t 76 , the scanner  21  changes the voltage of the control signal SL from the high level to the low level ( FIG. 18B ). Thereafter, at the timing t 77 , the counter  46  of the AD converter ADC( 0 ) resets the count value CNT( 0 ) to “0” on the basis of the control signal CC ( FIG. 18G ). 
     The readout section  40  (the readout sections  40 S and  40 N) generates the image signal DATA 0  (the image signals DATA 0 S and DATA 0 N) including the digital codes CODE generated by AD conversion, and the diagnosis section  61  of the signal processor  60  performs diagnosis processing on the basis of the image signal DATA 0 . 
     It is possible for the diagnosis section  61  to diagnose, on the basis of the digital codes CODE, for example, whether or not the reference signal generator  51  is allowed to change a gradient degree of the reference signal REF. In other words, in the imaging device  1 , for example, in order to be able to capture an image of a bright subject or a dark subject, the gradient degree of the reference signal REF is changed. Specifically, in a case where an image of a dark subject is captured, the imaging device  1  decreases the gradient degree of the reference signal REF, thereby increasing the conversion gain in the AD converter ADC. For example, it is possible for the conversion gain in the case where the image of the dark subject is captured to be higher by 30 [dB] than the conversion gain in a case where an image of a bright subject is captured. It is possible for the diagnosis section  61  to diagnose, for example, whether or not the reference signal generator  51  is allowed to change the gradient degree of the reference signal REF, on the basis of the digital codes CODE generated in a case where the gradient degree of the reference signal REF is changed. 
     Moreover, as with the self-diagnosis A 1 , it is possible for the diagnosis section  61  to diagnose, for example, the operation margin in the P-phase period through confirming the count value CNT( 0 ) after end of the P-phase period PP, for example, in a case where the gradient degree of the reference signal REF is set to various values. 
     (Self-Diagnosis A 3 ) 
     The imaging device  1  adjusts the voltage offset amount OFS of the reference signal REF in the D-phase period PD to subtract a contribution portion of the dark current of the photodiode  11 . In a self-diagnosis A 3 , whether or not the reference signal generator  51  is allowed to change the voltage of the reference signal REF in the D-phase period PD is diagnosed. Specifically, in the blanking period P 20 , the reference signal generator  51  changes the voltage offset amount OFS of the reference signal REF in the D-phase period PD. In this example, the signal generator  22  generates the control signals VMA and VMB that are the same as each other. Thereafter, the dummy pixel P 3  outputs the signal SIG corresponding to the voltages of the control signals VMA and VMB to the signal line SGL in the blanking period P 20 . The readout section  40  performs AD conversion on the basis of the signal SIG with use of the reference signal REF having a changed change degree to generate the digital code CODE. Thereafter, the diagnosis section  61  performs diagnosis processing on the basis of the digital code CODE. This operation is described in detail below. 
       FIGS. 19A, 19B, 19C, 19D, 19E, 19F, and 19G  illustrate an operation example of the self-diagnosis A 3 , where  FIG. 19A  indicates the waveform of the horizontal synchronization signal XHS,  FIG. 19B  indicates the waveform of the control signal SL,  FIG. 19C  indicates the waveform of the control signal VMA,  FIG. 19D  indicates the waveform of the reference signal REF,  FIG. 19E  indicates the waveform of the signal SIG (the signal SIG( 0 )) in the signal line SGL( 0 ),  FIG. 19F  indicates the waveform of the clock signal CLK, and  FIG. 19G  indicates the count value CNT (the count value CNT( 0 )) in the counter  46  of the 0th AD converter ADC( 0 ). 
     In this example, the reference signal generator  51  decreases the voltage level of the reference signal REF in the D-phase period PD to a lower level than that in the self-diagnosis A 1 . It is to be noted that in  FIGS. 19A, 19B, 19C, 19D, 19E, 19F, and 19G , for convenience of description, the reference signal REF in the self-diagnosis A 1  is indicated by a broken line. 
     First, at the timing t 61 , the horizontal period H within the blanking period P 20  starts, and then the scanner  21  changes the voltage of the control signal SL from the low level to the high level at the timing t 62  ( FIG. 19B ). This causes the dummy pixel P 3 A to output, as the signal SIG( 0 ), a voltage corresponding to the voltage (the voltage V 10 ) of the control signal VMA from the timing t 62  onward ( FIGS. 19C and 19E ). 
     Next, the comparator  45  performs zero adjustment that causes the positive input terminal and the negative input terminal to be electrically coupled to each other in the period from the timing t 63  to the timing t 64 . Thereafter, at the timing t 64 , the reference signal generator  51  changes the voltage of the reference signal REF to the voltage V 4  ( FIG. 18D ). 
     Thereafter, in the period from the timing t 65  to the timing t 67  (the P-phase period PP), the readout section  40  performs AD conversion. At the timing t 65 , the reference signal generator  51  of the controller  50  starts decreasing the voltage of the reference signal REF from the voltage V 1  by a predetermined change degree ( FIG. 19D ). The counter  46  of the AD converter ADC( 0 ) starts the counting operation at the timing t 65 , and stops the counting operation at the timing t 66  ( FIG. 19G ). 
     Next, the reference signal generator  51  stops change of the voltage of the reference signal REF at the timing t 67 , and changes the voltage of the reference signal REF to a voltage V 7  at the following timing t 68  ( FIG. 19D ). Thereafter, at the timing t 69 , the counter  46  of the AD converter ADC( 0 ) reverses polarity of the count value CNT( 0 ) on the basis of the control signal CC ( FIG. 19G ). 
     Next, at the timing t 70 , the voltage generator  30 A of the signal generator  22  changes the voltage of the control signal VMA to a voltage V 14  ( FIG. 19C ). Accordingly, the voltage of the signal SIG( 0 ) is decreased ( FIG. 19E ). 
     Next, in the period from the timing t 71  to the timing t 74  (the D-phase period PD), the readout section  40  performs AD conversion. At the timing t 71 , the reference signal generator  51  of the controller  50  starts decreasing the voltage of the reference signal REF from the voltage V 7  by a predetermined change degree ( FIG. 19D ). The counter  46  of the AD converter ADC( 0 ) starts the counting operation at the timing t 71 , and stops the counting operation at the timing t 72  ( FIG. 19G ). Thereafter, the AD converter ADC( 0 ) outputs the count value CNT( 0 ) as the digital code CODE. 
     Next, the reference signal generator  51  stops change of the voltage of the reference signal REF at the timing t 74 , and changes the voltage of the reference signal REF to the voltage V 3  at the following timing t 75  ( FIG. 19D ). 
     Thereafter, at the timing t 76 , the scanner  21  changes the voltage of the control signal SL from the high level to the low level ( FIG. 19B ). Thereafter, at the timing t 77 , the counter  46  of the AD converter ADC( 0 ) resets the count value CNT( 0 ) to “0” on the basis of the control signal CC ( FIG. 19G ). 
     The readout section  40  (the readout sections  40 S and  40 N) generates the image signal DATA 0  (the image signals DATA 0 S and DATA 0 N) including the digital codes CODE generated by AD conversion, and the diagnosis section  61  of the signal processor  60  performs diagnosis processing on the basis of the image signal DATA 0 . 
     It is possible for the diagnosis section  61  to diagnose, on the basis of the digital code CODE, for example, whether or not the reference signal generator  51  is allowed to change the voltage of the reference signal REF in the D-phase period PD. The imaging device  1  adjusts the voltage offset amount OFS of the reference signal REF in the D-phase period PD to subtract a contribution portion of the dark current of the photodiode  11 . Specifically, the imaging device  1  increases the voltage offset amount OFS in a case where an amount of the dark current is large. It is possible for the diagnosis section  61  to diagnose whether or not the reference signal generator  51  is allowed to change the voltage of the reference signal RED in the D-phase period PD, on the basis of, for example, the digital code CODE obtained in a case where the voltage of the reference signal REF in the D-phase period PD is changed. 
     (Self-Diagnosis A 4 ) 
     In a case where an image of an extremely bright subject is captured, the imaging device  1  limits the voltage of the signal SIG with use of the dummy pixel P 4  to prevent the voltage of the signal SIG from becoming too low in a predetermined period before the P-phase period PP. This operation is described below. 
       FIGS. 20A, 20B, 20C, 20D, 20E, 20F, and 20G  illustrate an operation example of the readout driving D 2  in the target pixel P 1 , where  FIG. 20A  indicates the waveform of the horizontal synchronization signal XHS,  FIG. 20B  indicates a waveform of the control signal SUN,  FIG. 20C  indicates the waveform of the control signal RST,  FIG. 20D  indicates the waveform of the control signal TG,  FIG. 20E  indicates the waveform of the control signal SL,  FIG. 20F  indicates the waveform of the reference signal REF (reference signals REF 1 , REF 2 , and REF 3 ), and  FIG. 20G  indicates the waveform of the signal SIG (signals SIG 1 , SIG 2 , and SIG 3 ). Herein, in  FIGS. 20F and 20G , the waveforms of the respective signals are plotted on the same voltage axis. In  FIGS. 20F and 20G , the reference signal REF 1  and the signal SIG 1  indicate the reference signal REF and the signal SIG in a case where an image of a subject having normal brightness is captured. In other words, the reference signal REF 1  and the signal SIG 1  are the same as those illustrated in  FIGS. 12A, 12B, 12C, 12D, 12E, 12F, 12G, 12H, and 12I . The reference signal REF 2  and the signal SIG 2  indicate the reference signal REF and the signal SIG in a case where an image of an extremely bright subject is captured, as well as signals in a case where the dummy pixel P 4  does not work. The reference signal REF 3  and the signal SIG 3  indicate the reference signal REF and the signal SIG in a case where an image of an extremely bright subject is captured, as well as signals in a case where the dummy pixel P 4  works. 
     In the case where the image of the subject having normal brightness is captured, as with the case illustrated in  FIGS. 12A, 12B, 12C, 12D, 12E, 12F, 12G, 12H, and 12I , the AD converter ADC performs AD conversion in the P-phase period PP and performs AD conversion in the D-phase period PD on the basis of the signal SIG 1  with use of the reference signal REF 1 . Thereafter, the AD converter ADC outputs the count value CNT as the digital code CODE, as with the case illustrated in  FIGS. 12A   12 B,  120 ,  12 D,  12 E,  12 F,  12 G,  12 H, and  12 I. 
     In contrast, in the case where the image of the extremely bright subject is captured, electrons are leaked from the photodiodes  11  of peripheral pixels P 1  to the floating diffusion FD of the target pixel P 1 , which causes the signal SIG 2  to become lower from the timing t 44  onward ( FIG. 20G ). The comparator  45  performs zero adjustment that causes the positive input terminal and the negative input terminal to be electrically coupled to each other in the period from the timing t 43  to the timing t 45 , which causes the reference signal REF 2  to also become lower in accordance with the signal SIG 2  ( FIG. 20F ). Thereafter, the AD converter ADC performs AD conversion in the P-phase period PP, and performs AD conversion in the D-phase period PD. However, in this case, the signal SIG 2  is too low, thereby being saturated; therefore, the signal SIG 2  is not changed from the timing t 51  onward ( FIG. 20G ). Accordingly, the AD converter ADC outputs a value close to “0” as the digital code CODE. In other words, in spite of the extremely bright subject, the digital code CODE becomes a value close to “0”. 
     Hence, in the imaging device  1 , the voltage of the signal SIG in a predetermined period before the P-phase period PP is limited with use of the dummy pixel P 4 . Specifically, the signal generator  23  sets the control signal SUN to a high voltage in the period from the timing t 43  to the timing t 45  ( FIG. 20B ). The dummy pixel P 4  outputs a voltage corresponding to this control signal SUN to the signal line SGL in the period from the timing t 43  to the timing t 45 . Accordingly, in the period from the timing t 43  to the timing t 45 , a decrease in the voltage of the signal SIG 3  is suppressed. Thus, the voltage of the signal SIG 3  is limited to a voltage corresponding to the voltage of the control signal SUN. The comparator  45  performs zero adjustment that causes the positive input terminal and the negative input terminal to be electrically coupled to each other in this period from the timing t 43  to the timing t 45 , which causes the reference signal REF 3  to also become higher than the reference signal REF 2 . Thereafter, at the timing t 45 , in a case where the voltage of the control signal SUN becomes lower ( FIG. 20B ), the voltage of the signal SIG 3  is decreased to a level substantially equal to the voltage of the signal SIG 2 . The voltage of the signal SIG 3  is always lower than that of the reference signal REF 2  in the P-phase period PP. Accordingly, the counter  46  of the AD converter ADC continues the counting operation in the P-phase period PP, and reaches a predetermined count value (a full count value) at the timing t 48  at which generation of the clock signal CLK is stopped. In a case where the full count value is reached in the P-phase period PP, the counter  46  continues the counting operation in the following D-phase period PD irrespective of the signal CMP outputted from the comparator  45 . Thus, in spite of the extremely bright subject, the imaging device  1  avoids the digital code CODE from becoming a value close to “0”. 
     As described above, in the case where the image of the extremely bright subject is captured, the imaging device  1  limits the voltage of the signal SIG with use of the dummy pixel P 4  in the predetermined period before the P-phase period PP to prevent the voltage of the signal SIG from becoming too low. In the self-diagnosis A 4 , whether or not such a function of limiting the voltage of the signal SIG works is diagnosed. Specifically, the signal generator  22  sets the control signals VMA and VMB to a low voltage. In this example, the signal generator  22  generates the control signals VMA and VMB that are the same as each other. Thereafter, the dummy pixel P 3  outputs the signal SIG corresponding to the voltages of the control signals VMA and VMB to the signal line SGL in the blanking period P 20 . The readout section  40  performs AD conversion on the basis of the signal SIG to generate the digital code CODE. Thereafter, the diagnosis section  61  performs diagnosis processing on the basis of the digital code CODE. This operation is described in detail below. 
       FIGS. 21A, 21B, 21C, 21D, 21E, 21F, and 21G  illustrate an operation example of the self-diagnosis A 4 , where  FIG. 21A  indicates the waveform of the horizontal synchronization signal XHS,  FIG. 21B  indicate the waveform of the control signal SL,  FIG. 21C  indicates the waveform of the control signal SUN,  FIG. 21D  indicates the waveform of the control signal VMA,  FIG. 21E  indicates the waveform of the reference signal REF,  FIG. 21F  indicates the waveform of the signal SIG (the signal SIG( 0 )) in the signal line SGL( 0 ), and  FIG. 21G  indicates the waveform of the clock signal CLK. 
     First, the horizontal period H within the blanking period P 20  starts at the timing t 61 , and then the scanner  21  changes the voltage of the control signal SL from the low level to the high level at the timing t 62  ( FIG. 21B ). 
     Thereafter, at the timing t 63 , the signal generator  22  changes the voltage of the control signal VMA to a low voltage V 15  ( FIG. 21D ). Accordingly, the signal SIG( 0 ) is also decreased ( FIG. 21F ). Moreover, at the timing t 63 , the signal generator  23  changes the voltage of the control signal SUN to a high voltage. Accordingly, a decrease in the signal SIG( 0 ) is suppressed ( FIG. 21F ). The comparator  45  performs zero adjustment that causes the positive input terminal and the negative input terminal to be electrically coupled to each other in the period from the timing t 63  to the timing t 64 . 
     Next, at the timing t 64 , the signal generator  23  changes the voltage of the control signal SUN to a low voltage ( FIG. 21C ). Accordingly, the signal SIG( 0 ) is decreased ( FIG. 21F ). 
     Thereafter, in the period from the timing t 65  to the timing t 67  (the P-phase period PP), the readout section  40  performs AD conversion. The reference signal generator  51  of the controller  50  starts decreasing the voltage of the reference signal REF from the voltage V 1  by a predetermined change degree at the timing t 65  ( FIG. 21E ). The counter  46  of the AD converter ADC( 0 ) starts the counting operation at the timing t 65 . However, the voltage of the signal SIG( 0 ) is always lower than that of the reference signal REF in the P-phase period PP; therefore, the counter  46  of the AD converter ADC( 0 ) continues the counting operation in the P-phase period PP, and reaches a predetermined count value (a count value CNTF 1 ) at the timing t 67  at which generation of the clock signal CLK is stopped. Accordingly, the counter  46  determines whether or not to continue the counting operation in the next D-phase period PD irrespective of the signal CMP outputted from the comparator  45 . 
     The reference signal generator  51  stops change of the voltage of the reference signal REF at the timing t 67 , and changes the voltage of the reference signal REF to the voltage V 2  at the following timing t 68  ( FIG. 21E ). Thereafter, although not illustrated, the counter  46  of the AD converter ADC( 0 ) reverses polarity of the count value CNT( 0 ) on the basis of the control signal CC. 
     Next, in the period from the timing t 71  to the timing t 74  (the D-phase period PD), the readout section  40  performs AD conversion. The reference signal generator  51  of the controller  50  starts decreasing the voltage of the reference signal REF from the voltage V 2  by a predetermined change degree at the timing t 71  ( FIG. 21E ). The counter  46  of the AD converter ADC( 0 ) starts the counting operation at the timing t 71 . Thereafter, the counter  46  continues the counting operation in the D-phase period PD irrespective of the signal CMP outputted from the comparator  45 . Accordingly, the counter  46  reaches a predetermined count value (a count value CNTF 2 ) at the timing t 74  at which generation of the clock signal CLK is stopped. Thereafter, the AD converter ADC( 0 ) outputs the count value CNT( 0 ) as the digital code CODE. 
     The reference signal generator  51  stops change of the voltage of the reference signal REF at the timing t 74 , and changes the voltage of the reference signal REF to the voltage V 3  at the following timing t 75  ( FIG. 21E ). 
     Thereafter, at the timing t 76 , the scanner  21  changes the voltage of the control signal SL from the high level to the low level ( FIG. 21B ). Thereafter, although not illustrated, the counter  46  resets the count value CNT( 0 ) to “0” on the basis of the control signal CC. 
     The readout section  40  (the readout sections  40 S and  40 N) generates the image signal DATA 0  (the image signal DATA 0 S and DATA 0 N) including the digital codes CODE generated by AD conversion, and the diagnosis section  61  of the signal processor  60  performs diagnosis processing on the basis of the image signal DATA 0 . 
     The diagnosis section  61  diagnoses, on the basis of the digital code CODE, whether or not the function of limiting the voltage of the signal SIG works. Specifically, it is possible for the diagnosis section  61  to diagnose that the function of limiting the voltage of the signal SIG works, for example, through confirming that the digital code CODE becomes a predetermined count value (the count value CNTF 2 ). 
     Moreover, it is possible for the diagnosis section  61  to confirm an operation of the counter  46  on the basis of the digital code CODE. Specifically, in this operation, the diagnosis section  61  diagnoses whether or not the counter  46  performs the counting operation properly, through confirming the count value CNT( 0 ) after end of the P-phase period PP and the count value CNT( 0 ) after end of the D-phase period PD with use of continuation of the counting operation by the counter  46 . Moreover, it is possible for the diagnosis section  61  to confirm whether or not the counter  46  reverses polarity of the count value CNT, through confirming the count value CNT( 0 ) after end of the P-phase period PP and the count value CNT( 0 ) before start of the D-phase period PD. Further, it is possible for the diagnosis section  61  to confirm, on the basis of the digital code CODE, whether or not the counter  46  is allowed to reset the count value CNT to “0” after the D-phase period PD. 
     (Self-Diagnosis A 5 ) 
     In the imaging device  1 , each of two voltage generators  30 A and  30 B includes the temperature sensor  33 . This makes it possible for the imaging device  1  to detect a temperature. In a self-diagnosis A 5 , whether or not the temperature sensor  33  is allowed to generate a voltage Vtemp corresponding to the temperature is diagnosed. Specifically, the signal generator  22  outputs the voltage Vtemp outputted from the temperature sensor  33  as the control signals VMA and VMB in the D-phase period PD within the blanking period P 20 . In this example, the signal generator  22  generates the control signals VMA and VMB that are the same as each other. Thereafter, the dummy pixel P 3  outputs the signal SIG corresponding to the voltages of the control signals VMA and MVB to the signal line SGL in the blanking period P 20 . The readout section  40  performs AC conversion on the basis of the signal SIG to generate the digital code CODE. Thereafter, the diagnosis section  61  performs diagnosis processing on the basis of the digital code CODE. This operation is described in detail below. 
       FIGS. 22A, 22B, 22C, 22D, 22E, 22F, 22G, 22H, 22I, and 22J  illustrate an operation example of the self-diagnosis A 5 , where  FIG. 22A  indicates the waveform of the horizontal synchronization signal XHS,  FIG. 22B  indicates the waveform of the control signal SL,  FIG. 22C  indicates the waveform of the control signal VMA,  FIG. 22D  indicates the waveform of the control signal VMB,  FIG. 22E  indicates the waveform of the reference signal REF,  FIG. 22F  indicates the waveform of the signal SIG (the signal SIG( 0 )) in the signal line SGL( 0 ),  FIG. 22G  indicates the waveform of the signal SIG (the signal SIG( 1 )) in the signal line SGL( 1 ),  FIG. 22H  indicates the waveform of the clock signal CLK,  FIG. 22I  indicates the count value CNT (the count value CNT( 0 )) in the counter  46  of the 0th AD converter ADC( 0 ), and  FIG. 22J  indicates the count value CNT (the count value CNT( 1 )) in the counter of the first AD converter ADC( 1 ). 
     First, the horizontal period H within the blanking period P 20  starts at the timing t 61 , and then the scanner  21  changes the voltage of the control signal SL from the low level to the high level at the timing t 62  ( FIG. 22B ). Accordingly, from the timing t 62  onward, the dummy pixel P 3 A outputs, as the signal SIG( 0 ), a voltage corresponding to the voltage (the voltage V 10 ) of the control signal VMA ( FIGS. 22C and 22F ), and the dummy pixel P 3 B outputs, as the signal SIG( 1 ), a voltage corresponding to the voltage (the voltage V 10 ) of the control signal VMB ( FIGS. 22D and 22G ). 
     Next, the comparator  45  performs zero adjustment that causes the positive input terminal and the negative input terminal to be electrically coupled to each other in the period from the timing t 63  to the timing t 64 . Thereafter, at the timing t 64 , the reference signal generator  51  changes the voltage of the reference signal REF to the voltage V 1  ( FIG. 22E ). 
     Thereafter, in the period from the timing t 65  to the timing t 67  (the P-phase period PP), the readout section  40  performs AD conversion. At the timing t 65 , the reference signal generator  51  of the controller  50  starts decreasing the voltage of the reference signal REF from the voltage V 1  by a predetermined change degree ( FIG. 22E ). The counter  46  of the AD converter ADC( 0 ) starts the counting operation at the timing t 65 , and stops the counting operation at the timing t 66  ( FIG. 22I ). Likewise, the counter  46  of the AD converter ADC( 1 ) starts the counting operation at the timing t 65 , and stops the counting operation at the timing t 66  ( FIG. 22J ). 
     Next, the reference signal generator  51  stops change of the voltage of the reference signal REF at the timing t 67 , and changes the voltage of the reference signal REF to the voltage V 2  at the following timing t 68  ( FIG. 22E ). 
     Next, at the timing t 69 , the counter  46  of the AD converter ADC( 0 ) reverses polarity of the count value CNT( 0 ) on the basis of the control signal CC ( FIG. 22I ), and the counter  46  of the AD converter ADC( 1 ) reverses polarity of the count value CNT( 1 ) on the basis of the control signal CC in a similar manner ( FIG. 22J ). 
     Next, at the timing t 70 , the voltage generator  30 A of the signal generator  22  outputs, as the control signal VMA, the voltage Vtemp outputted from the temperature sensor  33  of the voltage generator  30 A ( FIG. 22C ), and the voltage generator  30 B outputs, as the control signal VMB, the voltage Vtemp outputted from the temperature sensor  33  of the voltage generator  30 B in a similar manner ( FIG. 22D ). Accordingly, the voltages of the signals SIG( 0 ) and SIG( 1 ) are decreased ( FIGS. 22F and 22G ). 
     Next, in the period from the timing t 71  to the timing t 74  (the D-phase period PD), the readout section  40  performs AD conversion. At the timing t 71 , the reference signal generator  51  of the controller  50  starts decreasing the voltage of the reference signal REF from the voltage V 2  by a predetermined change degree ( FIG. 22E ). The counter  46  of the AD converter ADC( 0 ) starts the counting operation at the timing t 71 , and stops the counting operation at the timing t 72  ( FIG. 22I ). Thereafter, the AD converter ADC( 0 ) outputs the count value CNT( 0 ) as the digital code CODE. Likewise, the counter  46  of the AD converter ADC( 1 ) starts the counting operation at the timing t 71 , and stops the counting operation at the timing t 72  ( FIG. 22J ). Thereafter, the AD converter ADC( 1 ) outputs the count value CNT( 1 ) as the digital code CODE. 
     Next, the reference signal generator  51  stops change of the voltage of the reference signal REF at the timing t 74 , and changes the voltage of the reference signal REF to the voltage V 3  at the following timing t 75  ( FIG. 22E ). 
     Thereafter, at the timing t 76 , the scanner  21  changes the voltage of the control signal SL from the high level to the low level ( FIG. 22B ). Thereafter, at the timing t 77 , the counter  46  of the AD converter ADC( 0 ) resets the count value CNT( 0 ) to “0” on the basis of the control signal CC ( FIG. 22I ), and the counter  46  of the AD converter ADC( 1 ) resets the count value CNT( 1 ) to “0” on the basis of the control signal CC in a similar manner ( FIG. 22J ). 
     The readout section  40  (the readout sections  40 S and  40 N) generates the image signal DATA 0  (the image signals DATA 0 S and DATA 0 N) including the digital codes CODE generated by AD conversion, and the diagnosis section  61  of the signal processor  60  performs diagnosis processing on the basis of the image signal DATA 0 . 
     It is possible for the diagnosis section  61  to diagnose, on the basis of the digital code CODE, for example, whether or not each of the temperature sensors  33  of the voltage generators  30 A and  30 B is allowed to generate the voltage Vtemp corresponding to the temperature. Specifically, it is possible for the diagnosis section  61  to diagnose whether or not each of the temperature sensors  33  is allowed to generate the voltage Vtemp corresponding to the temperature, through confirming whether or not the value of the generated digital code CODE falls within a predetermined range. Moreover, in the imaging device  1 , the voltage generators  30 A and  30 B include the temperature sensors  33  having the same circuit configuration; therefore, the voltage Vtemp generated by the temperature sensor  33  of the voltage generator  30 A and the voltage Vtemp generated by the temperature sensor  33  of the voltage generator  30 B are substantially equal to each other. As a result, the voltage of an even-numberth signal line SGL (for example, the signal line SGL( 0 )) and the voltage of an odd-numberth signal line SGL (for example, the signal line SGL( 1 )) adjacent to that even-numberth signal line SGL are substantially equal to each other. For example, in a case where one of the two temperature sensors  33  has a breakdown, the digital codes CODE are different, which makes it possible for the diagnosis section  61  to diagnose, on the basis of the digital codes CODE, whether or not the temperature sensors  33  have a malfunction. 
     (Self-Diagnosis A 6 ) 
     In a self-diagnosis A 6 , whether or not it is possible to supply the digital codes CODE outputted from the plurality of AD converters ADC to the signal processor  60  through the bus wiring line  100  (the bus wiring lines  100 S and  100 N) is diagnosed. Specifically, unillustrated latches provided in output sections of the plurality of AD converters ADC output the digital codes CODE having a predetermined bit pattern on the basis of the control signal CC in the blanking period P 20 . Thereafter, the controller  50  generates the control signal SEL, and the plurality of switch sections SW of the readout section  40 S sequentially transfers, as the image signal DATA 0 S, the digital codes CODE outputted from the AD converters ADC of the readout section  40 S to the signal processor  60  on the basis of the control signal SEL, and the plurality of switch sections SW of the readout section  40 N sequentially transfers, as the image signal DATA 0 N, the digital codes CODE outputted from the AD converters ADC of the readout section  40 N to the signal processor  60  on the basis of the control signal SEL. Thereafter, the diagnosis section  61  performs diagnosis processing on the basis of the digital codes CODE. In the imaging device  1 , these operations are performed a plurality of times while changing a bit pattern or transfer order. The AD converter ADC (for example, the AD converter ADC( 0 )) corresponds to a specific example of a “first latch” in the present disclosure. The AD converter ADC (for example, the AD converter ADC( 2 )) corresponds to a specific example of a “second latch” in the present disclosure. This operation is described in detail below. 
       FIGS. 23A and 23B  schematically illustrate an example of a data transfer operation in a first diagnosis A 61  of the self-diagnosis A 6 .  FIG. 23A  illustrates an operation in the readout section  40 S, and  FIG. 23B  illustrates an operation in the readout section  40 N. In  FIGS. 23A and 23B , unshaded AD converters ADC (for example, AD converters ADC( 0 ), ADC( 1 ), ADC( 4 ), ADC( 5 ), . . . ) of the plurality of AD converters ADC each output the digital code CODE in which all bits are “0”, on the basis of the control signal CC. Moreover, shaded AD converters ADC (for example, AD converters ADC( 2 ), ADC( 3 ), ADC( 6 ), ADC( 7 ), . . . ) each output the digital code CODE in which all bits are “1”, on the basis of the control signal CC. 
       FIGS. 24A, 24B, 24C, 24D, and 24E  illustrate a timing chart of the data transfer operations illustrated in  FIGS. 23A and 23B , where  FIG. 24A  indicates the waveform of the horizontal synchronization signal XHS,  FIG. 24B  indicates even bits of the control signal SEL,  FIG. 24C  indicates odd bits of the control signal SEL,  FIG. 24D  indicates the image signal DATA 0 S, and  FIG. 24E  indicates the image signal DATA 0 N. In  FIGS. 24D and 24E , an unshaded portion provided with “L” indicates the digital code CODE in which all bits are “0” (a first logic value) and a shaded portion provided with “H” indicates the digital code CODE in which all bits are “1” (a second logic value). 
     The even bits of the control signal SEL become active in order of the control signal SEL[ 0 ], the control signal SEL[ 2 ], and the control signal SEL[ 4 ], as illustrated in  FIG. 24B . Hence, in the readout section  40 S, first, the digital code CODE of the 0th AD converter ADC( 0 ) is supplied to the bus wiring line  100 S. The AD converter ADC( 0 ) outputs the digital code CODE in which all bits are ‘0” ( FIG. 23A ), which causes all bits of the image signal DATA 0 S at this time to become “0” ( FIG. 24D ). Next, the digital code CODE of the second AD converter ADC( 2 ) is supplied to the bus wiring line  100 S. The AD converter ADC( 2 ) outputs the digital code CODE in which all bits are “1” ( FIG. 23A ), which causes all bits of the image signal DATA 0 S at this time to become “1” ( FIG. 24D ). Next, the digital code CODE of the fourth AD converter ADC( 4 ) is supplied to the bus wiring line  100 S. The AD converter ADC( 4 ) outputs the digital code CODE in which all bits are “0” ( FIG. 23A ), which causes all bits of the image signal DATA 0 S at this time to become “0” ( FIG. 24D ). Thus, the digital code CODE in which all bits are “0” and the digital code CODE in which all bits are “1” are alternately transferred as the image signal DATA 0 S to the signal processor  60  in order from the AD converter ADC on the left (in the transfer order F) ( FIG. 23A  and  FIG. 24D ). 
     The same applies to the operation of the readout section  40 N, and the digital code CODE in which all bits are “0” and the digital code CODE in which all bits are “1” are alternately transferred as the image signal DATA 0 N to the signal processor  60  in order from the AD converter ADC on the left (in the transfer order F) ( FIG. 23B  and  FIG. 24E ). 
     The diagnosis section  61  of the signal processor  60  performs diagnosis processing through performing comparison between each of bits of the digital code CODE included in the image section DATA 0  and an expected value, on the basis of the image signal DATA 0  (the image signals DATA 0 S and DATA 0 N). In particular, in the first diagnosis A 61 , the digital codes CODE related to adjacent ones of the AD converters ADC are different from each other, which makes it possible to diagnose, for example, whether or not a short circuit between the bus wiring lines related to the adjacent ones of the AD converters ADC occurs. Specifically, it is possible for the diagnosis section  61  to diagnose, for example, whether or not in the readout section  40 S ( FIG. 23A ), a short circuit occurs between a wiring line close to the AD converter ADC( 2 ) of the bus wiring lines coupling the 0th AD converter ADC( 0 ) and the bus wiring line  100 S to each other and a wiring line close to the AD converter ADC( 0 ) of the bus wiring lines coupling the second AD converter ADC( 2 ) and the bus wiring line  100 S to each other. 
       FIGS. 25A and 25B  schematically illustrate an example of the data transfer operation in a second diagnosis A 62  of the self-diagnosis A 6 .  FIG. 25A  illustrates an operation in the readout section  40 S, and  FIG. 25B  illustrates an operation in the readout section  40 N.  FIGS. 26A, 26B, 26C, 26D, and 26E  illustrate a timing chart of the data transfer operations illustrated in  FIGS. 25A and 25B . As illustrated in  FIGS. 25A and 25B , the bit pattern of the digital code CODE outputted from each of the AD converters ADC is different from the bit pattern in the first diagnosis A 61  ( FIGS. 23A and 23B ). Specifically, for example, the AD converters ADC( 0 ), ADC( 1 ), ADC( 4 ), ADC( 5 ), and so on each output the digital code CODE in which all bits are “0” in the first diagnosis A 61  ( FIGS. 23A and 23B ), and output the digital code CODE in which all bits are “1” in the second diagnosis A 62 . Likewise, for example, the AD converters ADC( 2 ), ADC( 3 ), ADC( 6 ), ADC( 7 ), and so on each output the digital code CODE in which all bits are “1” in the first diagnosis A 61  ( FIGS. 23A and 23B ), and output the digital code CODE in which all bits are 0″ in the second diagnosis A 62 . 
     In the readout section  40 S, first, the digital code CODE of the 0th AD converter ADC( 0 ) is supplied to the bus wiring line  100 S ( FIG. 26B ). The AD converter ADC( 0 ) outputs the digital code CODE in which all bits are “1” ( FIG. 25A ), which causes all bits of the image signal DATA 0 S at this time to become “1” ( FIG. 26D ). Next, the digital code CODE of the second AD converter ADC( 2 ) is supplied to the bus wiring line  100 S ( FIG. 26B ). The AD converter ADC( 2 ) outputs the digital code CODE in which all bits are “0” ( FIG. 25A ), which causes all bits of the image signal DATA 0 S at this time to become “0” ( FIG. 26D ). Next, the digital code CODE of the fourth AD converter ADC( 4 ) is supplied to the bus wiring line  100 S ( FIG. 26B ). The AD converter ADC( 4 ) outputs the digital code CODE in which all bits are “1” ( FIG. 25A ), which causes all bits of the image signal DATA 0 S at this time to become “0” ( FIG. 26D ). Thus, the digital code CODE in which all bits are “1” and the digital code CODE in which all bits are “0” are alternately transferred as the image signal DATA 0 S to the signal processor  60  in order from the AD converter ADC on the left (in the transfer order F) ( FIG. 25A  and  FIG. 26D ). 
     The same applies to the operation of the readout section  40 N, and the digital code CODE in which all bits are “1” and the digital code CODE in which all bits are “0” are alternately transferred as the image signal DATA 0 N to the signal processor  60  in order from the AD converter ADC on the left (in the transfer order F) ( FIG. 25B  and  FIG. 26E ). 
     The diagnosis section  61  of the signal processor  60  performs the second diagnosis A 62  ( FIGS. 25A, 25B, 26A, 26B, 26C, 26D, and 26E ) in addition to the first diagnosis A 61  ( FIGS. 23A, 23B, 24A, 24B, 24C, 24D, and 24E ), which makes it possible to diagnose whether or not a short circuit occurs between the bus wiring line related to the AD converter ADC and another wiring line such as a power source line or a ground line. In other words, in a case where such a short circuit occurs, a voltage of a short-circuited wiring line of the bus wiring line is fixed. In the diagnosis section  61 , the bit pattern of the digital code CODE outputted from each of the AD converters ADC differs between the first diagnosis A 61  and the second diagnosis A 62 , which makes it possible to detect whether or not such fixing of the voltage occurs. As a result, it is possible for the diagnosis section  61  to diagnose whether or not a short circuit between the bus wiring line related to the AD converter ADC and another wiring line occurs. 
       FIGS. 27A and 27B  schematically illustrates an example of a data transfer operation in a third diagnosis A 63  of the self-diagnosis A 6 .  FIG. 27A  illustrates an operation in the readout section  40 S, and  FIG. 27B  illustrates an operation in the readout section  40 N.  FIGS. 28A, 28B, 28C, 28D, and 28E  illustrate a timing chart of the data transfer operations illustrated in  FIGS. 27A and 27B . In the third diagnosis A 63 , the transfer order F is different from that in the first diagnosis A 61 . 
     Even bits of the control signal SEL become active in order of the control signal SEL[ 4094 ], the control signal SEL[ 4092 ], and the control signal SEL[ 4090 ], as illustrated in  FIG. 28B . Accordingly, in the readout section  40 S, first, the digital code CODE of the 4094th AD converter ADC( 4094 ) is supplied to the bus wiring line  100 S. The AD converter ADC( 4094 ) outputs the digital code CODE in which all bits are “1”, which causes all bits of the image signal DATA 0 S at this time to become “1” ( FIG. 28D ). Next, the digital code CODE of the 4092nd AD converter ADC( 4092 ) is supplied to the bus wiring line  100 S ( FIG. 28B ). The AD converter ADC( 4092 ) outputs the digital code CODE in which all bits are “0”, which causes all bits of the image signal DATA 0 S at this time to become “0” ( FIG. 28D ). Next, the digital code CODE of the 4090th AD converter ADC( 4090 ) is supplied to the bus wiring line  100 S ( FIG. 28B ). The AD converter ADC( 4090 ) outputs the digital code CODE in which all bits are “1”, which causes all bits of the image signal DATA 0 S at this time to become “1” ( FIG. 28D ). Thus, the digital code CODE in which all bits are “1” and the digital code CODE in which all bits are “0” are alternately transferred as the image signal DATA 0 S to the signal processor  60  in order from the AD converter ADC on the right (in the transfer order F) ( FIG. 27A  and  FIG. 28D ). 
     The same applies to the operation of the readout section  40 N, and the digital code CODE in which all bits are “1” and the digital code CODE in which all bits are “0” are alternately transferred as the image signal DATA 0 N to the signal processor  60  in order from the AD converter ADC on the right (in the transfer order F) ( FIG. 27B  and  FIG. 28E ). 
     The diagnosis section  61  of the signal processor  60  performs the third diagnosis A 63 , which makes it possible to diagnose whether or not the transfer order in transfer of the digital codes CODE from the plurality of AD converters ADC to the signal processor  60  is changeable. 
     As described above, in the imaging device  1 , the self-diagnosis is performed in the blanking period P 20 , which makes it possible to diagnose presence or absence of a malfunction in the imaging device  1  while performing an imaging operation in which an image of a subject is captured, without exerting an influence on this imaging operation. 
     In the imaging device  1 , in the blanking period P 20 , the signal generator  22  generates the control signals VMA and VMB, and the plurality of dummy pixels P 3  in the dummy pixel region R 3  outputs the signal SIG corresponding to the control signals VMA and VMB to the signal line SGL, which makes it possible to diagnose a malfunction such as a break in the signal line SGL occurring in the pixel array  10 , for example. Moreover, in the imaging device  1 , the voltages of the control signals VMA and VMB are settable to various voltages, which makes it possible to diagnose various operations in the imaging device  1 . This makes it possible to enhance diagnosis performance. 
     Further, in the imaging device  1 , in the blanking period P 20 , the plurality of AD converters ADC outputs the digital codes CODE having a predetermined bit pattern on the basis of the control signal CC, which makes it possible to diagnose the data transfer operation from the plurality of AD converters ADC to the signal processor  60 . In particular, in the imaging device  1 , the bit patterns of the digital codes CODE outputted from the AD converter ADC and the transfer order are changeable, which makes it possible to enhance diagnosis performance. 
     It is to be noted that in the present embodiment, whether or not a short circuit occurs in the signal line SG 1  or the bus wiring line  100 S is diagnosed through detecting a difference between the digital code converted by each of the AD converters ADC and the digital code transferred to the diagnosis section  61 ; however, the present embodiment is not limited thereto. For example, a configuration in which a diagnosis-use digital code is forcefully injected into a latch provided on a downstream side of each of the AD converters ADC by an unillustrated diagnosis-use digital code injection section may be adopted. Specifically, in the blanking period P 20 , the digital code in which all bits are “0” is forcefully injected into a first latch provided on a downstream side of a first AD converter, and the digital code in which all bits are “1” is forcefully injected into a second latch provided on a downstream side of a second AD converter adjacent to the first AD converter. Thereafter, the controller  50  generates the control signal SEL, and the plurality of switch sections SW of the readout section  40 S sequentially transfers the digital codes CODE outputted from the respective latches to the diagnosis section  61  of the signal processor  60  on the basis of the control signal SEL. 
     The diagnosis section  61  diagnoses that the bus wiring line  100 S does not have a malfunction (is not short-circuited) in a case where the diagnosis section  61  determines that the digital code transferred from the first latch is the digital code in which all bits are “0” and the digital code transferred from the second latch is the digital code in which all bits are “1”. 
     In contrast, the diagnosis section  61  diagnoses that the signal line SGL or the bus wiring line  100 S has a malfunction (is short-circuited) in a case where the diagnosis section  61  determines that the digital code transferred from the first latch is not the digital code in which all bits are “0”, or in a case where the diagnosis section  61  determines that the digital code transferred from the second latch is not the digital code in which all bits are “1”. 
     Moreover, for example, in a case where the pixel array  10  and the readout sections  40 S and  40 N are formed in the upper substrate  201  and the diagnosis section  61  is formed in the lower substrate  202 , executing the above-described diagnosis makes it possible to also diagnose a malfunction in the vias  203  between the readout sections  40 S and  40 N and the diagnosis section  61  in addition to the bus wiring lines  100 S and  100 N. 
     [Effects] 
     As described above, in the present embodiment, in the blanking period, the signal generator  22  generates the control signals VMA and VMB, and the plurality of dummy pixels P 3  in the dummy pixel region R 3  outputs the signal corresponding to the control signals VMA and VMB to the signal line, which makes it possible to diagnose a malfunction occurring in the pixel array, for example. 
     In the present embodiment, in the blanking period, the plurality of AD converters outputs digital codes having a predetermined bit pattern, which makes it possible to diagnose the data transfer operation from the plurality of AD converters to the signal processor. 
     Modification Example 1 
     In the foregoing embodiment, for example, two pixels P 1  (the pixels P 1 A and P 1 B) adjacent to each other in the vertical direction (the longitudinal direction in  FIG. 1 ) in the normal pixel region R 1  of the pixel array  10  are coupled to the same control lines TGL, SLL, and RSTL; however, this is not limitative. The present modification example is described below with reference to some examples. 
       FIG. 29  illustrates an example of the normal pixel region R 1  in a pixel array  10 A of an imaging device  1 A according to the present modification example. In this example, one column of pixels P 1  and four signal lines SGL are alternately disposed in the horizontal direction (a transverse direction in  FIG. 29 ). The even-numberth signal line SGL (SGL( 0 ), SGL( 2 ), . . . ) are coupled to the readout section  40 S, and the odd-numberth signal line SGL (SGL( 1 ), SGL( 3 ), . . . ) are coupled to the readout section  40 N. The plurality of pixels P 1  includes a plurality of pixels P 1 A, a plurality of pixels P 1 B, a plurality of pixels P 1 C, and a plurality of pixels P 1 D. The pixels P 1 A to P 1 D have circuit configurations that are the same as one another. The pixels P 1 A, P 1 B, P 1 C, and P 1 D are disposed cyclically in this order in the vertical direction (a longitudinal direction in  FIG. 29 ). The pixels P 1 A, P 1 B, P 1 C, and P 1 D are coupled to the same control lines TGL, SLL, and RSTL. The pixel P 1 A is coupled to, for example, the signal line SGL( 0 ), the pixel P 1 B is coupled to, for example, the signal line SGL( 1 ), the pixel P 1 C is coupled to, for example, the signal line SGL( 2 ), and the pixel P 1 D is coupled to, for example, the signal line SGL( 3 ). It is to be noted that although description has been given with reference to the normal pixel region R 1  as an example, the same applies to the light-shielded pixel regions R 21  and R 22 , and the dummy pixel regions R 3  and R 4 . 
       FIG. 30  illustrates an example of a normal pixel region in a pixel array  10 B of another imaging device  1 B according to the present modification example. In this example, one column of the pixels P 1  and one signal line SGL are alternately disposed in the horizontal direction (a transverse direction in  FIG. 30 ). The even-numberth signal lines SGL (SGL( 0 ), SGL( 2 ), . . . ) are coupled to the readout section  40 S, and the odd-numberth signal lines SGL (SGL( 1 ), SGL( 3 ), . . . ) are coupled to the readout section  40 N. The pixels P 1  disposed side by side in the vertical direction (a longitudinal direction in  FIG. 30 ) are coupled to mutually different control lines TGL, SLL, and RSTL. It is to be noted that although description has been given with reference to the normal pixel region R 1  as an example, the same applies to the light-shielded pixel regions R 21  and R 22 , and the dummy pixel regions R 3  and R 4 . 
     Modification Example 2 
     In the foregoing embodiment, one bus wiring line  100 S is provided in the readout section  40 S, and one bus wiring line  100 N is provided in the readout section  40 N; however, this is not limitative. Alternatively, for example, a plurality of bus wiring lines may be provided in each of the readout sections  40 S and  40 N. The present modification example is described in detail below. 
       FIGS. 31A and 31B  schematically illustrate a configuration example of a readout section  40 C (readout sections  40 SC and  40 NC) of an imaging device  1 C according to the present modification example.  FIG. 31A  illustrates an example of the readout section  40 SC, and  FIG. 31B  illustrates an example of the readout section  40 NC. 
     The readout section  40 SC includes four bus wiring lines  100 S 0 ,  100 S 1 ,  100 S 2 , and  100 S 3 , as illustrated in  FIG. 31A . The bus wiring line  100 S 0  supplies a plurality of digital codes CODE as an image signal DATA 0 S to the signal processor  60 . The bus wiring line  100 S 1  supplies a plurality of digital codes CODE as an image signal DATA 1 S to the signal processor  60 . The bus wiring line  100 S 2  supplies a plurality of digital codes CODE as an image signal DATA 2 S to the signal processor  60 . The bus wiring line  100 S 3  supplies a plurality of digital codes CODE as an image signal DATA 3 S to the signal processor  60 . 
     In the readout section  40 SC ( FIG. 31A ), the AD converters ADC( 0 ), ADC( 2 ), ADC( 4 ), and ADC( 6 ) are assigned to the bus wiring line  100 S 0 . Specifically, the AD converters ADC( 0 ), ADC( 2 ), ADC( 4 ), and ADC( 6 ) each supply the digital code CODE to the bus wiring line  100 S 0  in a case where a corresponding switch section SW is in the ON state. Likewise, the AD converters ADC( 8 ), ADC( 10 ), ADC( 12 ), and ADC( 14 ) are assigned to the bus wiring line  100 S 1 , the AD converters ADC( 16 ), ADC( 18 ), ADC( 20 ), and ADC( 22 ) are assigned to the bus wiring line  100 S 2 , and the AD converters ADC( 24 ), ADC( 26 ), ADC( 28 ), and ADC( 30 ) are assigned to the bus wiring line  100 S 3 . Moreover, the AD converters ADC( 32 ), ADC( 34 ), ADC( 36 ), and ADC( 38 ) are assigned to the bus wiring line  100 S 0 , the AD converters ADC( 40 ), ADC( 42 ), ADC( 44 ), and ADC( 46 ) are assigned to the bus wiring line  100 S 1 , the AD converters ADC( 48 ), ADC( 50 ), ADC( 52 ), and ADC( 54 ) are assigned to the bus wiring line  100 S 2 , and the AD converters ADC( 56 ), ADC( 58 ), ADC( 60 ), and ADC( 62 ) are assigned to the bus wiring line  100 S 3 . The same applies to the AD converter ADC( 64 ) and subsequent even-numberth AD converters ADC. 
     The readout section  40 NC includes four bus wiring lines  100 N 0 ,  100 N 1 ,  100 N 2 , and  100 N 3 , as illustrated in  FIG. 31B . The bus wiring line  100 N 0  supplies a plurality of digital codes CODE as an image signal DATA 0 N to the signal processor  60 . The bus wiring line  100 N 1  supplies a plurality of digital codes CODE as an image signal DATA 1 N to the signal processor  60 . The bus wiring line  100 N 2  supplies a plurality of digital codes CODE as an image signal DATA 2 N to the signal processor  60 . The bus wiring line  100 N 3  supplies a plurality of digital codes CODE as an image signal DATA 3 N to the signal processor  60 . 
     In the readout section  40 NC ( FIG. 31B ), the AD converters ADC( 1 ), ADC( 3 ), ADC( 5 ), and ADC( 7 ) are assigned to the bus wiring line  100 N 0 . Specifically, the AD converters ADC( 1 ), ADC( 3 ), ADC( 5 ), and ADC( 7 ) each supply the digital code CODE to the bus wiring line  100 N 0  in a case where a corresponding switch section SW is in the ON state. Likewise, the AD converters ADC( 9 ), ADC( 11 ), ADC( 13 ), and ADC( 15 ) are assigned to the bus wiring line  100 N 1 , the AD converter ADC( 17 ), ADC( 19 ), ADC( 21 ), and ADC( 23 ) are assigned to the bus wiring line  100 N 2 , and the AD converters ADC( 25 ), ADC( 27 ), ADC( 29 ), and ADC( 31 ) are assigned to the bus wiring line  100 N 3 . Moreover, the AD converters ADC( 33 ), ADC( 35 ), ADC( 37 ), and ADC( 39 ) are assigned to the bus wiring line  100 N 0 , the AD converters ADC( 41 ), ADC( 43 ), ADC( 45 ), and ADC( 47 ) are assigned to the bus wiring line  100 N 1 , the AD converters ADC( 49 ), ADC( 51 ), ADC( 53 ), and ADC( 55 ) are assigned to the bus wiring line  100 N 2 , and the AD converters ADC( 57 ), ADC( 59 ), ADC( 61 ), and ADC( 63 ) are assigned to the bus wiring line  100 N 3 . The same applies to the AD converter ADC( 65 ) and subsequent odd-numberth AD converters ADC. 
     As described above, in the imaging device  1 C, the plurality of bus wiring lines is provided in each of the readout sections  40 SC and  40 NC, which makes it possible to reduce a data transfer time from the plurality of AD converters ADC to the signal processor  60 . 
     In a case where the self-diagnosis is performed, unshaded AD converters ADC (for example, the AD converters ADC( 0 ), ADC( 1 ), ADC( 4 ), ADC( 5 ), . . . ) of the plurality of AD converters ADC output the digital code CODE in which all bits are “0” in the blanking period P 20  on the basis of the control signal CC. Moreover, shaded AD converters ADC (for example, the AD converters ADC( 2 ), ADC( 3 ), ADC( 6 ), ADC( 7 ), . . . ) output the digital code CODE in which all bits are “1” in the blanking period P 20  on the basis of the control signal CC. 
       FIGS. 32A, 32B, 32C, 32D, 32E, 32F, 32G, 32H, 32I, 32J, and 32K  illustrate a timing chart of a data transfer operation according to the present modification example, where  FIG. 32A  indicates the waveform of the horizontal synchronization signal XHS,  FIG. 32B  indicates even bits of the control signal SEL,  FIG. 32C  indicates odd bits of the control signal SEL,  FIGS. 32D, 32E, 32F, and 32G  respectively indicate the image signals DATA 0 S, DATA 1 S, DATA 2 S, and DATA 3 S, and  FIGS. 32H, 32I, 32J, and 32K  respectively indicate the image signals DATA 0 N, DATA 1 N, DATA 2 N, and DATA 3 N. 
     In the even bits of the control signal SEL, as illustrated in  FIG. 32B , first, the control signals SEL[ 0 ], SEL[ 8 ], SEL[ 16 ], and SEL[ 24 ] become active. Accordingly, in the readout section  40 SC, the digital code CODE of the AD converter ADC( 0 ) is supplied to the bus wiring line  100 S 0 , the digital code CODE of the AD converter ADC( 8 ) is supplied to the bus wiring line  10051 , the digital code CODE of the AD converter ADC( 16 ) is supplied to the bus wiring line  100 S 2 , and the digital code CODE of the AD converter ADC( 24 ) is supplied to the bus wiring line  100 S 3 . Each of the AD converters ADC( 0 ), ADC( 8 ), ADC( 16 ), and ADC( 24 ) outputs the digital code CODE in which all bits are “0” ( FIG. 31A ), which causes all bits of the image signals DATA 0 S, DATA 1 S, DATA 2 S, and DATA 3 S at this time to become “0” ( FIGS. 32D, 32E, 32F, and 32G ). 
     Next, in the even bits of the control signal SEL, the control signals SEL[ 2 ], SEL[ 10 ], SEL[ 18 ], and SEL[ 26 ] become active ( FIG. 32B ). Accordingly, in the readout section  40 SC, the digital code CODE of the AD converter ADC( 2 ) is supplied to the bus wiring line  100 S 0 , the digital code CODE of the AD converter ADC( 10 ) is supplied to the bus wiring line  100 S 1 , the digital code CODE of the AD converter ADC( 18 ) is supplied to the bus wiring line  100 S 2 , and the digital code CODE of the AD converter ADC( 26 ) is supplied to the bus wiring line  10053 . Each of the AD converters ADC( 2 ), ADC( 10 ), ADC( 18 ), and ADC( 26 ) outputs the digital code CODE in which all bits are “1” ( FIG. 31A ), which causes all bits of the image signals DATA 0 S, DATA 1 S, DATA 2 S, and DATA 3 S at this time to become “1” ( FIGS. 32D, 32E, 32F , and  32 G). 
     Thus, the digital code CODE in which all bits are “0” and the digital code CODE in which all bits are “1” are alternately transferred as the image signal DATA 0 S to the signal processor  60  ( FIG. 32D ). The same applies to the image signals DATA 1 S, DATA 2 S, and DATA 3 S ( FIGS. 32E, 32F, and 32G ), and the same applies to the image signals DATA 0 N, DATA 1 N, DATA 2 N, and DATA 3 N ( FIGS. 32I, 32J, and 32K ). 
     Modification Example 3 
     In the foregoing embodiment, all bits of the digital code CODE are “0” or “1”; however, this is not limitative. The present modification example is described in detail below. 
       FIGS. 33A and 33B  schematically illustrate a configuration example of a readout section  40 D (readout sections  40 SD and  40 ND) of an imaging device  1 D according to the present modification example.  FIG. 33A  illustrates an example of the readout section  40 SD, and  FIG. 3DB  illustrates an example of the readout section  40 ND. 
     The readout section  40 SD includes four bus wiring lines  100 S 0 ,  100 S 1 ,  100 S 2 , and  100 S 3 , as illustrated in  FIG. 33A . In this example, the AD converters ADC( 0 ), ADC( 2 ), and ADC( 4 ) are assigned to the bus wiring line  100 S 0 , the AD converters ADC( 6 ), ADC( 8 ), and ADC( 10 ) are assigned to the bus wiring line  100 S 1 , the AD converters ADC( 12 ), ADC( 14 ), and ADC( 16 ) are assigned to the bus wiring line  100 S 2 , and the AD converters ADC( 18 ), ADC( 20 ), and ADC( 22 ) are assigned to the bus wiring line  100 S 3 . Moreover, the AD converters ADC( 24 ), ADC( 26 ), and ADC( 28 ) are assigned to the bus wiring line  100 S 0 , the AD converters ADC( 30 ), ADC( 32 ), and ADC( 34 ) are assigned to the bus wiring line  100 S 1 , the AD converters ADC( 36 ), ADC( 38 ), and ADC( 40 ) are assigned to the bus wiring line  100 S 2 , and the AD converters ADC( 42 ), ADC( 44 ), and ADC( 46 ) are assigned to the bus wiring line  100 S 3 . The same applies to the AD converter ADC( 48 ), and subsequent even-numberth AD converters ADC. 
     The readout section  40 ND includes four bus wiring lines  100 N 0 ,  100 N 1 ,  100 N 2 , and  100 N 3 , as illustrated in  FIG. 33B . In this example, the AD converters ADC( 1 ), ADC( 3 ), and ADC( 5 ) are assigned to the bus wiring line  100 N 0 , the AD converters ADC( 7 ), ADC( 9 ), and ADC( 11 ) are assigned to the bus wiring line  100 N 1 , the AD converters ADC( 13 ), ADC( 15 ), and ADC( 17 ) are assigned to the bus wiring line  100 N 2 , and the AD converters ADC( 19 ), ADC( 21 ), and ADC( 23 ) are assigned to the bus wiring line  100 N 3 . Moreover, the AD converters ADC( 25 ), ADC( 27 ), and ADC( 29 ) are assigned to the bus wiring line  100 N 0 , the AD converter ADC( 31 ), ADC( 33 ), and ADC( 35 ) are assigned to the bus wiring line  100 N 1 , the AD converters ADC( 37 ), ADC( 39 ), and ADC( 41 ) are assigned to the bus wiring line  100 N 2 , and the AD converters ADC( 43 ), ADC( 45 ), and ADC( 47 ) are assigned to the bus wiring line  100 N 3 . The same applies to the AD converter ADC( 49 ) and subsequent odd-numberth AD converters ADC. 
     In a case where the self-diagnosis is performed, unshaded AD converters ADC (for example, the AD converter ADC( 0 ), ADC( 1 ), ADC( 4 ), ADC( 5 ), . . . ) of the plurality of AD converters ADC output the digital code CODE having a bit pattern A (=0101010101010b) in the blanking period P 20  on the basis of the control signal CC. Moreover, shaded AD converters ADC (for example, the AD converters ADC( 2 ), ADC( 3 ), ADC( 6 ), ADC( 7 ), . . . ) output the digital code CODE having a bit pattern B (=1010101010101b) in the blanking period P 20  on the basis of the control signal CC. The bit patterns A and B are I/O alternating patterns, as well as mutually reversed patterns. 
       FIGS. 34A, 34B, 34C, 34D, 34E, 34F, 34G, 34H, 34I, 34J, and 34K  illustrate a timing chart of the data transfer operation according to the present modification example, where  FIG. 34A  indicates the waveform of the horizontal synchronization signal XHS,  FIG. 34B  indicates even bits of the control signal SEL,  FIG. 34C  indicates odd bits of the control signal SEL,  FIGS. 34D, 34E, 34F, and 34G  respectively indicate the image signals DATA 0 S, DATA 1 S, DATA 2 S, and DATA 3 S, and  FIGS. 34H, 34I, 34J, and 34K  respectively indicate the image signals DATA 0 N, DATA 1 N, DATA 2 N, and DATA 3 N. In  FIGS. 34D, 34E, 34F, 34G, 34H, 34I, 34J, and 34K , an unshaded portion provided with “A” indicates the digital code CODE having the bit pattern A (=0101010101010b), and a shaded portion provided with “B” indicates the digital code CODE having the bit pattern B (=1010101010101b). 
     In even bits of the control signal SEL, as illustrated in  FIG. 34B , first, the control signals SEL[ 0 ], SEL[ 6 ], SEL[ 12 ], and SEL[ 18 ] become active. Accordingly, in the readout section  40 SD, the digital code CODE of the AD converter ADC( 0 ) is supplied to the bus wiring line  100 S 0 , the digital code CODE of the AD converter ADC( 6 ) is supplied to the bus wiring line  100 S 1 , the digital code CODE of the AD converter ADC( 12 ) is supplied to the bus wiring line  100 S 2 , and the digital code CODE of the AD converter ADC( 18 ) is supplied to the bus wiring line  10053 . Each of the AD converters ADC( 0 ) and ADC( 12 ) outputs the digital code CODE having the bit pattern A ( FIG. 33A ), which causes the digital codes CODE of the image signals DATA 0 S and DATA 2 S at this time to have the bit pattern A ( FIGS. 34D and 34F ). Moreover, each of the AD converters ADC( 6 ) and ADC( 18 ) outputs the digital code CODE having the bit pattern B ( FIG. 33A ), which causes the digital codes CODE of the image signals DATA 1 S and DATA 3 S at this time to have the bit pattern B ( FIGS. 34E and 34G ). 
     Next, in even bits of the control signal SEL, the control signals SEL[ 2 ], SEL[ 8 ], SEL[ 14 ], and SEL[ 20 ] become active ( FIG. 34B ). Accordingly, in the readout section  40 SD, the digital code CODE of the AD converter ADC( 2 ) is supplied to the bus wiring line  100 S 0 , the digital code CODE of the AD converter ADC( 8 ) is supplied to the bus wiring line  100 S 1 , the digital code CODE of the AD converter ADC( 14 ) is supplied to the bus wiring line  100 S 2 , and the digital code CODE of the AD converter ADC( 20 ) is supplied to the bus wiring line  10053 . Each of the AD converters ADC( 2 ) and ADC( 14 ) outputs the digital code CODE having the bit pattern B ( FIG. 33A ), which causes the digital codes CODE of the image signals DATA 0 S and DATA 2 S at this time to have the bit pattern B ( FIGS. 34D and 34F ). Moreover, each of the AD converters ADC( 8 ) and ADC( 20 ) outputs the digital code CODE having the bit pattern A ( FIG. 33A ), which causes the digital codes CODE of the image signals DATA 1 S and DATA 3 S at this time to have the bit pattern A ( FIGS. 34E and 34G ). 
     Thus, the digital code CODE having the bit pattern A and the digital code CODE having the bit pattern B are alternately transferred as the image signal DATA 0 S to the signal processor  60  ( FIG. 34D ). The same applies to the image signals DATA 2 S, DATA 0 N, and DATA 2 N ( FIGS. 34F, 34H, and 34J ). Moreover, the digital code CODE having the bit pattern B and the digital code CODE having the bit pattern A are alternately transferred as the image signal DATA 01 S to the signal processor  60  ( FIG. 34E ). The same applies to the image signals DATA 3 S, DATA 1 N, and DATA 3 N ( FIGS. 34G, 34I, and 34K ). 
     As described above, in the imaging device  1 D, the bit pattern of the digital code CODE is the 1/0 alternating pattern, which makes it possible to diagnose, for example, whether or not a short circuit occurs between adjacent wiring lines of the bus wiring lines related to the respective AD converters ADC. Specifically, it is possible for the diagnosis section  61  to diagnose, for example, whether or not in the readout section  40 SD ( FIG. 33A ), a short circuit occurs between wiring lines adjacent to each other of bus wiring lines coupling the 0th AD converter ADC( 0 ) and the bus wiring line  100 S 0  to each other. 
     Other Modification Examples 
     Moreover, two or more of these modification examples may be combined. 
     2. Application Example 
     Next, description is given of an application example of the imaging devices described in the foregoing embodiment and modification examples. 
     The technology according to the present disclosure is applicable to various products. For example, the technology according to the present disclosure may be achieved in the form of an apparatus to be mounted to a mobile body of any kind such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility, an airplane, a drone, a vessel, a robot, a construction machine, an agricultural machine (a tractor), etc. 
       FIG. 35  is a block diagram depicting an example of schematic configuration of a vehicle control system  7000  as an example of a mobile body control system to which the technology according to an embodiment of the present disclosure can be applied. The vehicle control system  7000  includes a plurality of electronic control units connected to each other via a communication network  7010 . In the example depicted in  FIG. 35 , the vehicle control system  7000  includes a driving system control unit  7100 , a body system control unit  7200 , a battery control unit  7300 , an outside-vehicle information detecting unit  7400 , an in-vehicle information detecting unit  7500 , and an integrated control unit  7600 . The communication network  7010  connecting the plurality of control units to each other may, for example, be a vehicle-mounted communication network compliant with an arbitrary standard such as controller area network (CAN), local interconnect network (LIN), local area network (LAN), FlexRay, or the like. 
     Each of the control units includes: a microcomputer that performs arithmetic processing according to various kinds of programs; a storage section that stores the programs executed by the microcomputer, parameters used for various kinds of operations, or the like; and a driving circuit that drives various kinds of control target devices. Each of the control units further includes: a network interface (I/F) for performing communication with other control units via the communication network  7010 ; and a communication I/F for performing communication with a device, a sensor, or the like within and without the vehicle by wire communication or radio communication. A functional configuration of the integrated control unit  7600  illustrated in  FIG. 35  includes a microcomputer  7610 , a general-purpose communication I/F  7620 , a dedicated communication I/F  7630 , a positioning section  7640 , a beacon receiving section  7650 , an in-vehicle device I/F  7660 , a sound/image output section  7670 , a vehicle-mounted network I/F  7680 , and a storage section  7690 . The other control units similarly include a microcomputer, a communication I/F, a storage section, and the like. 
     The driving system control unit  7100  controls the operation of devices related to the driving system of the vehicle in accordance with various kinds of programs. For example, the driving system control unit  7100  functions as a control device for a driving force generating device for generating the driving force of the vehicle, such as an internal combustion engine, a driving motor, or the like, a driving force transmitting mechanism for transmitting the driving force to wheels, a steering mechanism for adjusting the steering angle of the vehicle, a braking device for generating the braking force of the vehicle, and the like. The driving system control unit  7100  may have a function as a control device of an antilock brake system (ABS), electronic stability control (ESC), or the like. 
     The driving system control unit  7100  is connected with a vehicle state detecting section  7110 . The vehicle state detecting section  7110 , for example, includes at least one of a gyro sensor that detects the angular velocity of axial rotational movement of a vehicle body, an acceleration sensor that detects the acceleration of the vehicle, and sensors for detecting an amount of operation of an accelerator pedal, an amount of operation of a brake pedal, the steering angle of a steering wheel, an engine speed or the rotational speed of wheels, and the like. The driving system control unit  7100  performs arithmetic processing using a signal input from the vehicle state detecting section  7110 , and controls the internal combustion engine, the driving motor, an electric power steering device, the brake device, and the like. 
     The body system control unit  7200  controls the operation of various kinds of devices provided to the vehicle body in accordance with various kinds of programs. For example, the body system control unit  7200  functions as a control device for a keyless entry system, a smart key system, a power window device, or various kinds of lamps such as a headlamp, a backup lamp, a brake lamp, a turn signal, a fog lamp, or the like. In this case, radio waves transmitted from a mobile device as an alternative to a key or signals of various kinds of switches can be input to the body system control unit  7200 . The body system control unit  7200  receives these input radio waves or signals, and controls a door lock device, the power window device, the lamps, or the like of the vehicle. 
     The battery control unit  7300  controls a secondary battery  7310 , which is a power supply source for the driving motor, in accordance with various kinds of programs. For example, the battery control unit  7300  is supplied with information about a battery temperature, a battery output voltage, an amount of charge remaining in the battery, or the like from a battery device including the secondary battery  7310 . The battery control unit  7300  performs arithmetic processing using these signals, and performs control for regulating the temperature of the secondary battery  7310  or controls a cooling device provided to the battery device or the like. 
     The outside-vehicle information detecting unit  7400  detects information about the outside of the vehicle including the vehicle control system  7000 . For example, the outside-vehicle information detecting unit  7400  is connected with at least one of an imaging section  7410  and an outside-vehicle information detecting section  7420 . The imaging section  7410  includes at least one of a time-of-flight (ToF) camera, a stereo camera, a monocular camera, an infrared camera, and other cameras. The outside-vehicle information detecting section  7420 , for example, includes at least one of an environmental sensor for detecting current atmospheric conditions or weather conditions and a peripheral information detecting sensor for detecting another vehicle, an obstacle, a pedestrian, or the like on the periphery of the vehicle including the vehicle control system  7000 . 
     The environmental sensor, for example, may be at least one of a rain drop sensor detecting rain, a fog sensor detecting a fog, a sunshine sensor detecting a degree of sunshine, and a snow sensor detecting a snowfall. The peripheral information detecting sensor may be at least one of an ultrasonic sensor, a radar device, and a LIDAR device (Light detection and Ranging device, or Laser imaging detection and ranging device). Each of the imaging section  7410  and the outside-vehicle information detecting section  7420  may be provided as an independent sensor or device, or may be provided as a device in which a plurality of sensors or devices are integrated. 
       FIG. 36  depicts an example of installation positions of the imaging section  7410  and the outside-vehicle information detecting section  7420 . Imaging sections  7910 ,  7912 ,  7914 ,  7916 , and  7918  are, for example, disposed at at least one of positions on a front nose, sideview mirrors, a rear bumper, and a back door of the vehicle  7900  and a position on an upper portion of a windshield within the interior of the vehicle. The imaging section  7910  provided to the front nose and the imaging section  7918  provided to the upper portion of the windshield within the interior of the vehicle obtain mainly an image of the front of the vehicle  7900 . The imaging sections  7912  and  7914  provided to the sideview mirrors obtain mainly an image of the sides of the vehicle  7900 . The imaging section  7916  provided to the rear bumper or the back door obtains mainly an image of the rear of the vehicle  7900 . The imaging section  7918  provided to the upper portion of the windshield within the interior of the vehicle is used mainly to detect a preceding vehicle, a pedestrian, an obstacle, a signal, a traffic sign, a lane, or the like. 
     Incidentally,  FIG. 36  depicts an example of photographing ranges of the respective imaging sections  7910 ,  7912 ,  7914 , and  7916 . An imaging range a represents the imaging range of the imaging section  7910  provided to the front nose. Imaging ranges b and c respectively represent the imaging ranges of the imaging sections  7912  and  7914  provided to the sideview mirrors. An imaging range d represents the imaging range of the imaging section  7916  provided to the rear bumper or the back door. A bird&#39;s-eye image of the vehicle  7900  as viewed from above can be obtained by superimposing image data imaged by the imaging sections  7910 ,  7912 ,  7914 , and  7916 , for example. 
     Outside-vehicle information detecting sections  7920 ,  7922 ,  7924 ,  7926 ,  7928 , and  7930  provided to the front, rear, sides, and corners of the vehicle  7900  and the upper portion of the windshield within the interior of the vehicle may be, for example, an ultrasonic sensor or a radar device. The outside-vehicle information detecting sections  7920 ,  7926 , and  7930  provided to the front nose of the vehicle  7900 , the rear bumper, the back door of the vehicle  7900 , and the upper portion of the windshield within the interior of the vehicle may be a LIDAR device, for example. These outside-vehicle information detecting sections  7920  to  7930  are used mainly to detect a preceding vehicle, a pedestrian, an obstacle, or the like. 
     Returning to  FIG. 35 , the description will be continued. The outside-vehicle information detecting unit  7400  makes the imaging section  7410  image an image of the outside of the vehicle, and receives imaged image data. In addition, the outside-vehicle information detecting unit  7400  receives detection information from the outside-vehicle information detecting section  7420  connected to the outside-vehicle information detecting unit  7400 . In a case where the outside-vehicle information detecting section  7420  is an ultrasonic sensor, a radar device, or a LIDAR device, the outside-vehicle information detecting unit  7400  transmits an ultrasonic wave, an electromagnetic wave, or the like, and receives information of a received reflected wave. On the basis of the received information, the outside-vehicle information detecting unit  7400  may perform processing of detecting an object such as a human, a vehicle, an obstacle, a sign, a character on a road surface, or the like, or processing of detecting a distance thereto. The outside-vehicle information detecting unit  7400  may perform environment recognition processing of recognizing a rainfall, a fog, road surface conditions, or the like on the basis of the received information. The outside-vehicle information detecting unit  7400  may calculate a distance to an object outside the vehicle on the basis of the received information. 
     In addition, on the basis of the received image data, the outside-vehicle information detecting unit  7400  may perform image recognition processing of recognizing a human, a vehicle, an obstacle, a sign, a character on a road surface, or the like, or processing of detecting a distance thereto. The outside-vehicle information detecting unit  7400  may subject the received image data to processing such as distortion correction, alignment, or the like, and combine the image data imaged by a plurality of different imaging sections  7410  to generate a bird&#39;s-eye image or a panoramic image. The outside-vehicle information detecting unit  7400  may perform viewpoint conversion processing using the image data imaged by the imaging section  7410  including the different imaging parts. 
     The in-vehicle information detecting unit  7500  detects information about the inside of the vehicle. The in-vehicle information detecting unit  7500  is, for example, connected with a driver state detecting section  7510  that detects the state of a driver. The driver state detecting section  7510  may include a camera that images the driver, a biosensor that detects biological information of the driver, a microphone that collects sound within the interior of the vehicle, or the like. The biosensor is, for example, disposed in a seat surface, the steering wheel, or the like, and detects biological information of an occupant sitting in a seat or the driver holding the steering wheel. On the basis of detection information input from the driver state detecting section  7510 , the in-vehicle information detecting unit  7500  may calculate a degree of fatigue of the driver or a degree of concentration of the driver, or may determine whether the driver is dozing. The in-vehicle information detecting unit  7500  may subject an audio signal obtained by the collection of the sound to processing such as noise canceling processing or the like. 
     The integrated control unit  7600  controls general operation within the vehicle control system  7000  in accordance with various kinds of programs. The integrated control unit  7600  is connected with an input section  7800 . The input section  7800  is implemented by a device capable of input operation by an occupant, such, for example, as a touch panel, a button, a microphone, a switch, a lever, or the like. The integrated control unit  7600  may be supplied with data obtained by voice recognition of voice input through the microphone. The input section  7800  may, for example, be a remote control device using infrared rays or other radio waves, or an external connecting device such as a mobile telephone, a personal digital assistant (PDA), or the like that supports operation of the vehicle control system  7000 . The input section  7800  may be, for example, a camera. In that case, an occupant can input information by gesture. Alternatively, data may be input which is obtained by detecting the movement of a wearable device that an occupant wears. Further, the input section  7800  may, for example, include an input control circuit or the like that generates an input signal on the basis of information input by an occupant or the like using the above-described input section  7800 , and which outputs the generated input signal to the integrated control unit  7600 . An occupant or the like inputs various kinds of data or gives an instruction for processing operation to the vehicle control system  7000  by operating the input section  7800 . 
     The storage section  7690  may include a read only memory (ROM) that stores various kinds of programs executed by the microcomputer and a random access memory (RAM) that stores various kinds of parameters, operation results, sensor values, or the like. In addition, the storage section  7690  may be implemented by a magnetic storage device such as a hard disc drive (HDD) or the like, a semiconductor storage device, an optical storage device, a magneto-optical storage device, or the like. 
     The general-purpose communication I/F  7620  is a communication I/F used widely, which communication I/F mediates communication with various apparatuses present in an external environment  7750 . The general-purpose communication I/F  7620  may implement a cellular communication protocol such as global system for mobile communications (GSM), worldwide interoperability for microwave access (WiMAX), long term evolution (LTE)), LTE-advanced (LTE-A), or the like, or another wireless communication protocol such as wireless LAN (referred to also as wireless fidelity (Wi-Fi), Bluetooth, or the like. The general-purpose communication I/F  7620  may, for example, connect to an apparatus (for example, an application server or a control server) present on an external network (for example, the Internet, a cloud network, or a company-specific network) via a base station or an access point. In addition, the general-purpose communication I/F  7620  may connect to a terminal present in the vicinity of the vehicle (which terminal is, for example, a terminal of the driver, a pedestrian, or a store, or a machine type communication (MTC) terminal) using a peer to peer (P2P) technology, for example. 
     The dedicated communication I/F  7630  is a communication I/F that supports a communication protocol developed for use in vehicles. The dedicated communication I/F  7630  may implement a standard protocol such, for example, as wireless access in vehicle environment (WAVE), which is a combination of institute of electrical and electronic engineers (IEEE) 802.11p as a lower layer and IEEE 1609 as a higher layer, dedicated short range communications (DSRC), or a cellular communication protocol. The dedicated communication I/F  7630  typically carries out V2X communication as a concept including one or more of communication between a vehicle and a vehicle (Vehicle to Vehicle), communication between a road and a vehicle (Vehicle to Infrastructure), communication between a vehicle and a home (Vehicle to Home), and communication between a pedestrian and a vehicle (Vehicle to Pedestrian). 
     The positioning section  7640 , for example, performs positioning by receiving a global navigation satellite system (GNSS) signal from a GNSS satellite (for example, a GPS signal from a global positioning system (GPS) satellite), and generates positional information including the latitude, longitude, and altitude of the vehicle. Incidentally, the positioning section  7640  may identify a current position by exchanging signals with a wireless access point, or may obtain the positional information from a terminal such as a mobile telephone, a personal handyphone system (PHS), or a smart phone that has a positioning function. 
     The beacon receiving section  7650 , for example, receives a radio wave or an electromagnetic wave transmitted from a radio station installed on a road or the like, and thereby obtains information about the current position, congestion, a closed road, a necessary time, or the like. Incidentally, the function of the beacon receiving section  7650  may be included in the dedicated communication I/F  7630  described above. 
     The in-vehicle device I/F  7660  is a communication interface that mediates connection between the microcomputer  7610  and various in-vehicle devices  7760  present within the vehicle. The in-vehicle device I/F  7660  may establish wireless connection using a wireless communication protocol such as wireless LAN, Bluetooth, near field communication (NFC), or wireless universal serial bus (WUSB). In addition, the in-vehicle device I/F  7660  may establish wired connection by universal serial bus (USB), high-definition multimedia interface (HDMI), mobile high-definition link (MHL), or the like via a connection terminal (and a cable if necessary) not depicted in the figures. The in-vehicle devices  7760  may, for example, include at least one of a mobile device and a wearable device possessed by an occupant and an information device carried into or attached to the vehicle. The in-vehicle devices  7760  may also include a navigation device that searches for a path to an arbitrary destination. The in-vehicle device I/F  7660  exchanges control signals or data signals with these in-vehicle devices  7760 . 
     The vehicle-mounted network I/F  7680  is an interface that mediates communication between the microcomputer  7610  and the communication network  7010 . The vehicle-mounted network I/F  7680  transmits and receives signals or the like in conformity with a predetermined protocol supported by the communication network  7010 . 
     The microcomputer  7610  of the integrated control unit  7600  controls the vehicle control system  7000  in accordance with various kinds of programs on the basis of information obtained via at least one of the general-purpose communication I/F  7620 , the dedicated communication I/F  7630 , the positioning section  7640 , the beacon receiving section  7650 , the in-vehicle device I/F  7660 , and the vehicle-mounted network I/F  7680 . For example, the microcomputer  7610  may calculate a control target value for the driving force generating device, the steering mechanism, or the braking device on the basis of the obtained information about the inside and outside of the vehicle, and output a control command to the driving system control unit  7100 . For example, the microcomputer  7610  may perform cooperative control intended to implement functions of an advanced driver assistance system (ADAS) which functions include collision avoidance or shock mitigation for the vehicle, following driving based on a following distance, vehicle speed maintaining driving, a warning of collision of the vehicle, a warning of deviation of the vehicle from a lane, or the like. In addition, the microcomputer  7610  may perform cooperative control intended for automatic driving, which makes the vehicle to travel autonomously without corresponding to the operation of the driver, or the like, by controlling the driving force generating device, the steering mechanism, the braking device, or the like on the basis of the obtained information about the surroundings of the vehicle. 
     The microcomputer  7610  may generate three-dimensional distance information between the vehicle and an object such as a surrounding structure, a person, or the like, and generate local map information including information about the surroundings of the current position of the vehicle, on the basis of information obtained via at least one of the general-purpose communication I/F  7620 , the dedicated communication I/F  7630 , the positioning section  7640 , the beacon receiving section  7650 , the in-vehicle device I/F  7660 , and the vehicle-mounted network I/F  7680 . In addition, the microcomputer  7610  may predict danger such as collision of the vehicle, approaching of a pedestrian or the like, an entry to a closed road, or the like on the basis of the obtained information, and generate a warning signal. The warning signal may, for example, be a signal for producing a warning sound or lighting a warning lamp. 
     The sound/image output section  7670  transmits an output signal of at least one of a sound and an image to an output device capable of visually or auditorily notifying information to an occupant of the vehicle or the outside of the vehicle. In the example of  FIG. 35 , an audio speaker  7710 , a display section  7720 , and an instrument panel  7730  are illustrated as the output device. The display section  7720  may, for example, include at least one of an on-board display and a head-up display. The display section  7720  may have an augmented reality (AR) display function. The output device may be other than these devices, and may be another device such as headphones, a wearable device such as an eyeglass type display worn by an occupant or the like, a projector, a lamp, or the like. In a case where the output device is a display device, the display device visually displays results obtained by various kinds of processing performed by the microcomputer  7610  or information received from another control unit in various forms such as text, an image, a table, a graph, or the like. In addition, in a case where the output device is an audio output device, the audio output device converts an audio signal constituted of reproduced audio data or sound data or the like into an analog signal, and auditorily outputs the analog signal. 
     Incidentally, at least two control units connected to each other via the communication network  7010  in the example depicted in  FIG. 35  may be integrated into one control unit. Alternatively, each individual control unit may include a plurality of control units. Further, the vehicle control system  7000  may include another control unit not depicted in the figures. In addition, part or the whole of the functions performed by one of the control units in the above description may be assigned to another control unit. That is, predetermined arithmetic processing may be performed by any of the control units as long as information is transmitted and received via the communication network  7010 . Similarly, a sensor or a device connected to one of the control units may be connected to another control unit, and a plurality of control units may mutually transmit and receive detection information via the communication network  7010 . 
     In the vehicle control system  7000  described above, the imaging device  1  according to the present embodiment described with use of  FIG. 1  is applicable to the imaging section  7410  in a further application example illustrated in  FIG. 35 . Accordingly, in the vehicle control system  7000 , performing a self-diagnosis makes it possible to diagnose whether or not the imaging section  7410  operates properly. Thereafter, in a case where the imaging section  7410  has a malfunction, for example, a result of the diagnosis is informed to the microcomputer  7610 , which makes it possible for the vehicle control system  7000  to apprehend that the imaging section  7410  has a malfunction. Accordingly, in the vehicle control system  7000 , for example, it is possible to perform appropriate processing such as calling driver&#39;s attention, which makes it possible to enhance reliability. Moreover, in the vehicle control system  7000 , it is possible to restrict a function of controlling a vehicle on the basis of a result of diagnosis processing. Specific examples of the function of controlling the vehicle include a function of collision avoidance or shock mitigation for the vehicle, a function of following driving based on a following distance, a function of vehicle speed maintaining driving, a function of a warning of collision of the vehicle, a function of a warning of deviation of the vehicle from a lane, etc. In a case where it is determined, as a result of the diagnosis processing, that the imaging section  7410  has a malfunction, it is possible to restrict or disable the function of controlling the vehicle. Accordingly, in the vehicle control system  7000 , it is possible to prevent an accident resulting from a detection error based on the malfunction in the imaging section  7410 . 
     Although the present technology has been described above referring to the embodiment, modification examples, and specific application examples thereof, the present technology is not limited to these embodiment, etc., and may be modified in a variety of ways. 
     For example, in the foregoing embodiment, the plurality of pixels P 1 A disposed side by side in the vertical direction (the longitudinal direction in  FIG. 2 ) is coupled to one AD converter ADC; however, this is not limitative. Alternatively, for example, as with an imaging device  1 E illustrated in  FIG. 37 , a plurality of pixels P belonging to one area AR may be coupled to one AD converter ADC. The imaging device  1 E is formed separately in two semiconductor substrates (an upper substrate  211  and a lower substrate  212 ). The pixel array  10  is formed in the upper substrate  211 . The pixel array  10  is divided into a plurality of (nine in this example) areas AR, and each of the areas AR includes a plurality of pixels P. The readout section  40  is formed in the lower substrate  212 . Specifically, in the lower substrate  212 , a region corresponding to one of the areas AR of the upper substrate  211  includes the AD converter ADC coupled to the plurality of pixels P belonging to that area AR. The upper substrate  211  and the lower substrate  212  are electrically coupled to each other by Cu—Cu bonding, for example. It is to be noted that in this example, the pixel array  10  is divided into nine areas AR; however, this is not limitative. Alternatively, for example, the pixel array  10  may be divided into eight or less or 10 or more areas AR, for example. 
     It is to be noted that effects described herein are merely illustrative and are not limitative, and may have other effects. 
     It is to be noted that the present technology may have the following configurations. 
     (1) 
     An imaging device including: 
     a plurality of signal lines; 
     a plurality of pixels that each apply a pixel voltage to the plurality of signal lines; 
     a plurality of converters that is provided corresponding to the plurality of signal lines, each performs AD conversion on the basis of a voltage of a corresponding signal line of the plurality of signal lines to generate a digital code and output the digital code, and is allowed to set, to a predetermined digital code, the digital code to be outputted in a first period; 
     a processor that performs predetermined processing on the basis of the digital code, and performs diagnosis processing in the first period; and 
     a transfer section that transfers the digital code outputted from each of the plurality of converters to the processor. 
     (2) 
     The imaging device according to claim ( 1 ), in which 
     the predetermine digital code includes a first code and a second code, 
     the plurality of converters sets the digital codes of converters adjacent to each other of the plurality of converters to codes different from each other of the first code and the second code. 
     (3) 
     The imaging device according to (2), in which 
     respective bits of the first code are set to a first logic value, and 
     respective bits of the second code are set to a second logic value. 
     (4) 
     The imaging device according to (2), in which 
     respective bits of the first code are alternately set to a first logic value and a second logic value, and 
     respective bits of the second code are set to reverse bits of the respective bits of the first code. 
     (5) 
     The imaging device according to any one of (2) to (4), in which 
     the transfer section alternately transfers the digital code outputted from the converter of which the digital code is set to the first code of the plurality of converters and the digital code outputted from the converter of which the digital code set to the second code of the plurality of converters. 
     (6) 
     The imaging device according to any one of (1) to (5), in which the transfer section is allowed to change transfer order in a case where the digital code outputted from each of the plurality of converters is transferred. 
     (7) 
     The imaging device according to any one of (1) to (6), in which the first period includes a period within a blanking period. 
     (8) 
     The imaging device according to any one of (1) to (7), in which the plurality of converters outputs the digital code generated in a second period different from the first period. 
     (9) 
     The imaging device according to any one of (1) to (8), in which 
     the transfer section includes: 
     a bus wiring line, 
     a plurality of switch sections that is provided corresponding to the plurality of converters, and each is turned to an ON state, thereby supplying the digital code outputted from a corresponding converter of the plurality of converters to the bus wiring line. 
     (10) 
     The imaging device according to any one of (1) to (8), in which 
     the transfer section includes: 
     a plurality of bus wiring lines, 
     a plurality of switch sections that is provided corresponding to the plurality of converters, and each is turned to an ON state, thereby supplying the digital code outputted from a corresponding converter of the plurality of converters to any one of the plurality of bus wiring lines. 
     This application claims the benefit of Japanese Priority Patent Application JP2017-026824 filed with the Japan Patent Office on Feb. 16, 2017 and Japanese Priority Patent Application JP2017-197508 filed with the Japan Patent Office on Oct. 11, 2017, the entire contents of which are incorporated herein by reference. 
     It should be understood by those skilled in the art that various modifications, combinations, sub-combinations, and alterations may occur corresponding to design requirements and other factors insofar as they are within the scope of the appended claims or the equivalents thereof.