Patent Publication Number: US-10769526-B2

Title: Machine learning accelerator architecture

Description:
FIELD 
     Embodiments relate generally to data processing and more particularly to data processing via a general-purpose graphics processing unit. 
     BACKGROUND OF THE DESCRIPTION 
     Deep learning algorithms are currently being implemented in various machine learning applications, such as audio/video recognition, video summarization, etc. These workloads currently operate on a variety of hardware platforms, including central processing units (CPUs), graphics processing units (GPUs) and fixed function hardware accelerators. These platforms typically perform various computations for Deep Learning Neural Network (DNN) topologies, with the most common computation involving DNN operations that include three-dimensional (3D) convolution and general matrix multiplication. 
     There have been recent efforts to enable these workloads to be computed with lower precision while maintaining acceptable accuracy limits. While converting floating point real numbers to lower precision, different quantization schemes may be followed. One popular scheme is based on representing each floating point number with an unsigned 8 bit integer through some transformation involving scaling and offset addition. Consequently, complex convolutional neural network (CNN)/general matrix-matrix multiplication (GEMM) operations on quantized inputs need to be calculated. These operations are typically computed in software via multiple pass throughs of data. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       So that the manner in which the above recited features of the present embodiments can be understood in detail, a more particular description of the embodiments, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments and are therefore not to be considered limiting of its scope. 
         FIG. 1  is a block diagram of a processing system, according to an embodiment. 
         FIG. 2  is a block diagram of an embodiment of a processor having one or more processor cores, an integrated memory controller, and an integrated graphics processor. 
         FIG. 3  is a block diagram of a graphics processor, which may be a discrete graphics processing unit, or may be a graphics processor integrated with a plurality of processing cores. 
         FIG. 4  is a block diagram of a graphics processing engine of a graphics processor in accordance with some embodiments. 
         FIG. 5  is a block diagram of hardware logic of a graphics processor core according to some embodiments. 
         FIG. 6A-6B  illustrate thread execution logic including an array of processing elements employed in a graphics processor core according to some embodiments. 
         FIG. 7  is a block diagram illustrating a graphics processor instruction formats according to some embodiments. 
         FIG. 8  is a block diagram of another embodiment of a graphics processor. 
         FIG. 9A  is a block diagram illustrating a graphics processor command format according to an embodiment. 
         FIG. 9B  is a block diagram illustrating a graphics processor command sequence according to an embodiment. 
         FIG. 10  illustrates exemplary graphics software architecture for a data processing system according to some embodiments. 
         FIG. 11A  is a block diagram illustrating an IP core development system that may be used to manufacture an integrated circuit to perform operations according to an embodiment. 
         FIG. 11B  illustrates a cross-section side view of an integrated circuit package assembly according to some embodiments. 
         FIG. 12  is a block diagram illustrating an exemplary system on a chip integrated circuit that may be fabricated using one or more IP cores, according to an embodiment. 
         FIGS. 13A-13B  are block diagrams illustrating exemplary graphics processors for use within an System on Chip (SoC), according to embodiments described herein. 
         FIGS. 14A-14B  illustrate additional exemplary graphics processor logic according to embodiments described herein. 
         FIG. 15  illustrates a machine learning software stack, according to an embodiment. 
         FIGS. 16A-16B  illustrate layers of exemplary deep neural networks. 
         FIG. 17  illustrates an exemplary recurrent neural network. 
         FIG. 18  illustrates training and deployment of a deep neural network. 
         FIG. 19  is a block diagram illustrating distributed learning. 
         FIG. 20  illustrates a computing device employing a machine learning accelerator, according to an embodiment. 
         FIG. 21  illustrates one embodiment of an accelerator. 
         FIG. 22  illustrates another embodiment of an accelerator. 
         FIG. 23  is a flow diagram illustrating one embodiment of a process performed at an accelerator. 
     
    
    
     DETAILED DESCRIPTION 
     In embodiments, various mechanisms for accelerating machine learning operations are described. 
     In the following description, numerous specific details are set forth to provide a more thorough understanding. However, it will be apparent to one of skill in the art that the embodiments described herein may be practiced without one or more of these specific details. In other instances, well-known features have not been described to avoid obscuring the details of the present embodiments. 
     In embodiments, a hardware accelerator is implemented to accelerate the computation of machine learning operations. In such embodiments, the hardware accelerator a first set of processing elements to perform matrix multiplication computations, a second set of processing elements to perform sum of elements of weights and offset multiply computations and a third set of processing elements to perform sum of elements of inputs and offset multiply computations. In a further embodiment, the computations performed by the first, second and third processing elements are computed in parallel. 
     System Overview 
       FIG. 1  is a block diagram of a processing system  100 , according to an embodiment. In various embodiments, the system  100  includes one or more processors  102  and one or more graphics processors  108 , and may be a single processor desktop system, a multiprocessor workstation system, or a server system having a large number of processors  102  or processor cores  107 . In one embodiment, the system  100  is a processing platform incorporated within a system-on-a-chip (SoC) integrated circuit for use in mobile, handheld, or embedded devices. 
     In one embodiment, the system  100  can include, or be incorporated within a server-based gaming platform, a game console, including a game and media console, a mobile gaming console, a handheld game console, or an online game console. In some embodiments, the system  100  is a mobile phone, smart phone, tablet computing device or mobile Internet device. The processing system  100  can also include, couple with, or be integrated within a wearable device, such as a smart watch wearable device, smart eyewear device, augmented reality device, or virtual reality device. In some embodiments, the processing system  100  is a television or set top box device having one or more processors  102  and a graphical interface generated by one or more graphics processors  108 . 
     In some embodiments, the one or more processors  102  each include one or more processor cores  107  to process instructions which, when executed, perform operations for system and user software. In some embodiments, each of the one or more processor cores  107  is configured to process a specific instruction set  109 . In some embodiments, instruction set  109  may facilitate Complex Instruction Set Computing (CISC), Reduced Instruction Set Computing (RISC), or computing via a Very Long Instruction Word (VLIW). Multiple processor cores  107  may each process a different instruction set  109 , which may include instructions to facilitate the emulation of other instruction sets. Processor core  107  may also include other processing devices, such a Digital Signal Processor (DSP). 
     In some embodiments, the processor  102  includes cache memory  104 . Depending on the architecture, the processor  102  can have a single internal cache or multiple levels of internal cache. In some embodiments, the cache memory is shared among various components of the processor  102 . In some embodiments, the processor  102  also uses an external cache (e.g., a Level-3 (L3) cache or Last Level Cache (LLC)) (not shown), which may be shared among processor cores  107  using known cache coherency techniques. A register file  106  is additionally included in processor  102  which may include different types of registers for storing different types of data (e.g., integer registers, floating point registers, status registers, and an instruction pointer register). Some registers may be general-purpose registers, while other registers may be specific to the design of the processor  102 . 
     In some embodiments, one or more processor(s)  102  are coupled with one or more interface bus(es)  110  to transmit communication signals such as address, data, or control signals between processor  102  and other components in the system  100 . The interface bus  110 , in one embodiment, can be a processor bus, such as a version of the Direct Media Interface (DMI) bus. However, processor busses are not limited to the DMI bus, and may include one or more Peripheral Component Interconnect buses (e.g., PCI, PCI Express), memory busses, or other types of interface busses. In one embodiment the processor(s)  102  include an integrated memory controller  116  and a platform controller hub  130 . The memory controller  116  facilitates communication between a memory device and other components of the system  100 , while the platform controller hub (PCH)  130  provides connections to I/O devices via a local I/O bus. 
     The memory device  120  can be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, flash memory device, phase-change memory device, or some other memory device having suitable performance to serve as process memory. In one embodiment the memory device  120  can operate as system memory for the system  100 , to store data  122  and instructions  121  for use when the one or more processors  102  executes an application or process. Memory controller  116  also couples with an optional external graphics processor  112 , which may communicate with the one or more graphics processors  108  in processors  102  to perform graphics and media operations. In some embodiments a display device  111  can connect to the processor(s)  102 . The display device  111  can be one or more of an internal display device, as in a mobile electronic device or a laptop device or an external display device attached via a display interface (e.g., DisplayPort, etc.). In one embodiment the display device  111  can be a head mounted display (HMD) such as a stereoscopic display device for use in virtual reality (VR) applications or augmented reality (AR) applications. 
     In some embodiments the platform controller hub  130  enables peripherals to connect to memory device  120  and processor  102  via a high-speed  110  bus. The I/O peripherals include, but are not limited to, an audio controller  146 , a network controller  134 , a firmware interface  128 , a wireless transceiver  126 , touch sensors  125 , a data storage device  124  (e.g., hard disk drive, flash memory, etc.). The data storage device  124  can connect via a storage interface (e.g., SATA) or via a peripheral bus, such as a Peripheral Component Interconnect bus (e.g., PCI, PCI Express). The touch sensors  125  can include touch screen sensors, pressure sensors, or fingerprint sensors. The wireless transceiver  126  can be a Wi-Fi transceiver, a Bluetooth transceiver, or a mobile network transceiver such as a 3G, 4G, or Long Term Evolution (LTE) transceiver. The firmware interface  128  enables communication with system firmware, and can be, for example, a unified extensible firmware interface (UEFI). The network controller  134  can enable a network connection to a wired network. In some embodiments, a high-performance network controller (not shown) couples with the interface bus  110 . The audio controller  146 , in one embodiment, is a multi-channel high definition audio controller. In one embodiment the system  100  includes an optional legacy I/O controller  140  for coupling legacy (e.g., Personal System  2  (PS/2)) devices to the system. The platform controller hub  130  can also connect to one or more Universal Serial Bus (USB) controllers  142  connect input devices, such as keyboard and mouse  143  combinations, a camera  144 , or other USB input devices. 
     It will be appreciated that the system  100  shown is exemplary and not limiting, as other types of data processing systems that are differently configured may also be used. For example, an instance of the memory controller  116  and platform controller hub  130  may be integrated into a discreet external graphics processor, such as the external graphics processor  112 . In one embodiment the platform controller hub  130  and/or memory controller  160  may be external to the one or more processor(s)  102 . For example, the system  100  can include an external memory controller  116  and platform controller hub  130 , which may be configured as a memory controller hub and peripheral controller hub within a system chipset that is in communication with the processor(s)  102 . 
       FIG. 2  is a block diagram of an embodiment of a processor  200  having one or more processor cores  202 A- 202 N, an integrated memory controller  214 , and an integrated graphics processor  208 . Those elements of  FIG. 2  having the same reference numbers (or names) as the elements of any other figure herein can operate or function in any manner similar to that described elsewhere herein, but are not limited to such. Processor  200  can include additional cores up to and including additional core  202 N represented by the dashed lined boxes. Each of processor cores  202 A- 202 N includes one or more internal cache units  204 A- 204 N. In some embodiments each processor core also has access to one or more shared cached units  206 . 
     The internal cache units  204 A- 204 N and shared cache units  206  represent a cache memory hierarchy within the processor  200 . The cache memory hierarchy may include at least one level of instruction and data cache within each processor core and one or more levels of shared mid-level cache, such as a Level 2 (L2), Level 3 (L3), Level 4 (L4), or other levels of cache, where the highest level of cache before external memory is classified as the LLC. In some embodiments, cache coherency logic maintains coherency between the various cache units  206  and  204 A- 204 N. 
     In some embodiments, processor  200  may also include a set of one or more bus controller units  216  and a system agent core  210 . The one or more bus controller units  216  manage a set of peripheral buses, such as one or more PCI or PCI express busses. System agent core  210  provides management functionality for the various processor components. In some embodiments, system agent core  210  includes one or more integrated memory controllers  214  to manage access to various external memory devices (not shown). 
     In some embodiments, one or more of the processor cores  202 A- 202 N include support for simultaneous multi-threading. In such embodiment, the system agent core  210  includes components for coordinating and operating cores  202 A- 202 N during multi-threaded processing. System agent core  210  may additionally include a power control unit (PCU), which includes logic and components to regulate the power state of processor cores  202 A- 202 N and graphics processor  208 . 
     In some embodiments, processor  200  additionally includes graphics processor  208  to execute graphics processing operations. In some embodiments, the graphics processor  208  couples with the set of shared cache units  206 , and the system agent core  210 , including the one or more integrated memory controllers  214 . In some embodiments, the system agent core  210  also includes a display controller  211  to drive graphics processor output to one or more coupled displays. In some embodiments, display controller  211  may also be a separate module coupled with the graphics processor via at least one interconnect, or may be integrated within the graphics processor  208 . 
     In some embodiments, a ring based interconnect unit  212  is used to couple the internal components of the processor  200 . However, an alternative interconnect unit may be used, such as a point-to-point interconnect, a switched interconnect, or other techniques, including techniques well known in the art. In some embodiments, graphics processor  208  couples with the ring interconnect  212  via an I/O link  213 . 
     The exemplary I/O link  213  represents at least one of multiple varieties of I/O interconnects, including an on package I/O interconnect which facilitates communication between various processor components and a high-performance embedded memory module  218 , such as an eDRAM module. In some embodiments, each of the processor cores  202 A- 202 N and graphics processor  208  use embedded memory modules  218  as a shared Last Level Cache. 
     In some embodiments, processor cores  202 A- 202 N are homogenous cores executing the same instruction set architecture. In another embodiment, processor cores  202 A- 202 N are heterogeneous in terms of instruction set architecture (ISA), where one or more of processor cores  202 A- 202 N execute a first instruction set, while at least one of the other cores executes a subset of the first instruction set or a different instruction set. In one embodiment processor cores  202 A- 202 N are heterogeneous in terms of microarchitecture, where one or more cores having a relatively higher power consumption couple with one or more power cores having a lower power consumption. Additionally, processor  200  can be implemented on one or more chips or as an SoC integrated circuit having the illustrated components, in addition to other components. 
       FIG. 3  is a block diagram of a graphics processor  300 , which may be a discrete graphics processing unit, or may be a graphics processor integrated with a plurality of processing cores. In some embodiments, the graphics processor communicates via a memory mapped I/O interface to registers on the graphics processor and with commands placed into the processor memory. In some embodiments, graphics processor  300  includes a memory interface  314  to access memory. Memory interface  314  can be an interface to local memory, one or more internal caches, one or more shared external caches, and/or to system memory. 
     In some embodiments, graphics processor  300  also includes a display controller  302  to drive display output data to a display device  320 . Display controller  302  includes hardware for one or more overlay planes for the display and composition of multiple layers of video or user interface elements. The display device  320  can be an internal or external display device. In one embodiment the display device  320  is a head mounted display device, such as a virtual reality (VR) display device or an augmented reality (AR) display device. In some embodiments, graphics processor  300  includes a video codec engine  306  to encode, decode, or transcode media to, from, or between one or more media encoding formats, including, but not limited to Moving Picture Experts Group (MPEG) formats such as MPEG-2, Advanced Video Coding (AVC) formats such as H.264/MPEG-4 AVC, as well as the Society of Motion Picture &amp; Television Engineers (SMPTE) 421M/VC-1, and Joint Photographic Experts Group (JPEG) formats such as JPEG, and Motion JPEG (MJPEG) formats. 
     In some embodiments, graphics processor  300  includes a block image transfer (BLIT) engine  304  to perform two-dimensional (2D) rasterizer operations including, for example, bit-boundary block transfers. However, in one embodiment, 2D graphics operations are performed using one or more components of graphics processing engine (GPE)  310 . In some embodiments, GPE  310  is a compute engine for performing graphics operations, including three-dimensional (3D) graphics operations and media operations. 
     In some embodiments, GPE  310  includes a 3D pipeline  312  for performing 3D operations, such as rendering three-dimensional images and scenes using processing functions that act upon 3D primitive shapes (e.g., rectangle, triangle, etc.). The 3D pipeline  312  includes programmable and fixed function elements that perform various tasks within the element and/or spawn execution threads to a 3D/Media sub-system  315 . While 3D pipeline  312  can be used to perform media operations, an embodiment of GPE  310  also includes a media pipeline  316  that is specifically used to perform media operations, such as video post-processing and image enhancement. 
     In some embodiments, media pipeline  316  includes fixed function or programmable logic units to perform one or more specialized media operations, such as video decode acceleration, video de-interlacing, and video encode acceleration in place of, or on behalf of video codec engine  306 . In some embodiments, media pipeline  316  additionally includes a thread spawning unit to spawn threads for execution on 3D/Media sub-system  315 . The spawned threads perform computations for the media operations on one or more graphics execution units included in 3D/Media sub-system  315 . 
     In some embodiments, 3D/Media subsystem  315  includes logic for executing threads spawned by 3D pipeline  312  and media pipeline  316 . In one embodiment, the pipelines send thread execution requests to 3D/Media subsystem  315 , which includes thread dispatch logic for arbitrating and dispatching the various requests to available thread execution resources. The execution resources include an array of graphics execution units to process the 3D and media threads. In some embodiments, 3D/Media subsystem  315  includes one or more internal caches for thread instructions and data. In some embodiments, the subsystem also includes shared memory, including registers and addressable memory, to share data between threads and to store output data. 
     Graphics Processing Engine 
       FIG. 4  is a block diagram of a graphics processing engine  410  of a graphics processor in accordance with some embodiments. In one embodiment, the graphics processing engine (GPE)  410  is a version of the GPE  310  shown in  FIG. 3 . Elements of  FIG. 4  having the same reference numbers (or names) as the elements of any other figure herein can operate or function in any manner similar to that described elsewhere herein, but are not limited to such. For example, the 3D pipeline  312  and media pipeline  316  of  FIG. 3  are illustrated. The media pipeline  316  is optional in some embodiments of the GPE  410  and may not be explicitly included within the GPE  410 . For example and in at least one embodiment, a separate media and/or image processor is coupled to the GPE  410 . 
     In some embodiments, GPE  410  couples with or includes a command streamer  403 , which provides a command stream to the 3D pipeline  312  and/or media pipelines  316 . In some embodiments, command streamer  403  is coupled with memory, which can be system memory, or one or more of internal cache memory and shared cache memory. In some embodiments, command streamer  403  receives commands from the memory and sends the commands to 3D pipeline  312  and/or media pipeline  316 . The commands are directives fetched from a ring buffer, which stores commands for the 3D pipeline  312  and media pipeline  316 . In one embodiment, the ring buffer can additionally include batch command buffers storing batches of multiple commands. The commands for the 3D pipeline  312  can also include references to data stored in memory, such as but not limited to vertex and geometry data for the 3D pipeline  312  and/or image data and memory objects for the media pipeline  316 . The 3D pipeline  312  and media pipeline  316  process the commands and data by performing operations via logic within the respective pipelines or by dispatching one or more execution threads to a graphics core array  414 . In one embodiment the graphics core array  414  include one or more blocks of graphics cores (e.g., graphics core(s)  415 A, graphics core(s)  415 B), each block including one or more graphics cores. Each graphics core includes a set of graphics execution resources that includes general-purpose and graphics specific execution logic to perform graphics and compute operations, as well as fixed function texture processing and/or machine learning and artificial intelligence acceleration logic. 
     In various embodiments the 3D pipeline  312  includes fixed function and programmable logic to process one or more shader programs, such as vertex shaders, geometry shaders, pixel shaders, fragment shaders, compute shaders, or other shader programs, by processing the instructions and dispatching execution threads to the graphics core array  414 . The graphics core array  414  provides a unified block of execution resources for use in processing these shader programs. Multi-purpose execution logic (e.g., execution units) within the graphics core(s)  415 A- 414 B of the graphic core array  414  includes support for various 3D API shader languages and can execute multiple simultaneous execution threads associated with multiple shaders. 
     In some embodiments the graphics core array  414  also includes execution logic to perform media functions, such as video and/or image processing. In one embodiment, the execution units additionally include general-purpose logic that is programmable to perform parallel general-purpose computational operations, in addition to graphics processing operations. The general-purpose logic can perform processing operations in parallel or in conjunction with general-purpose logic within the processor core(s)  107  of  FIG. 1  or core  202 A- 202 N as in  FIG. 2 . 
     Output data generated by threads executing on the graphics core array  414  can output data to memory in a unified return buffer (URB)  418 . The URB  418  can store data for multiple threads. In some embodiments the URB  418  may be used to send data between different threads executing on the graphics core array  414 . In some embodiments the URB  418  may additionally be used for synchronization between threads on the graphics core array and fixed function logic within the shared function logic  420 . 
     In some embodiments, graphics core array  414  is scalable, such that the array includes a variable number of graphics cores, each having a variable number of execution units based on the target power and performance level of GPE  410 . In one embodiment the execution resources are dynamically scalable, such that execution resources may be enabled or disabled as needed. 
     The graphics core array  414  couples with shared function logic  420  that includes multiple resources that are shared between the graphics cores in the graphics core array. The shared functions within the shared function logic  420  are hardware logic units that provide specialized supplemental functionality to the graphics core array  414 . In various embodiments, shared function logic  420  includes but is not limited to sampler  421 , math  422 , and inter-thread communication (ITC)  423  logic. Additionally, some embodiments implement one or more cache(s)  425  within the shared function logic  420 . 
     A shared function is implemented where the demand for a given specialized function is insufficient for inclusion within the graphics core array  414 . Instead a single instantiation of that specialized function is implemented as a stand-alone entity in the shared function logic  420  and shared among the execution resources within the graphics core array  414 . The precise set of functions that are shared between the graphics core array  414  and included within the graphics core array  414  varies across embodiments. In some embodiments, specific shared functions within the shared function logic  420  that are used extensively by the graphics core array  414  may be included within shared function logic  416  within the graphics core array  414 . In various embodiments, the shared function logic  416  within the graphics core array  414  can include some or all logic within the shared function logic  420 . In one embodiment, all logic elements within the shared function logic  420  may be duplicated within the shared function logic  416  of the graphics core array  414 . In one embodiment the shared function logic  420  is excluded in favor of the shared function logic  416  within the graphics core array  414 . 
       FIG. 5  is a block diagram of hardware logic of a graphics processor core  500 , according to some embodiments described herein. Elements of  FIG. 5  having the same reference numbers (or names) as the elements of any other figure herein can operate or function in any manner similar to that described elsewhere herein, but are not limited to such. The illustrated graphics processor core  500 , in some embodiments, is included within the graphics core array  414  of  FIG. 4 . The graphics processor core  500 , sometimes referred to as a core slice, can be one or multiple graphics cores within a modular graphics processor. The graphics processor core  500  is exemplary of one graphics core slice, and a graphics processor as described herein may include multiple graphics core slices based on target power and performance envelopes. Each graphics core  500  can include a fixed function block  530  coupled with multiple sub-cores  501 A- 501 F, also referred to as sub-slices, that include modular blocks of general-purpose and fixed function logic. 
     In some embodiments the fixed function block  530  includes a geometry/fixed function pipeline  536  that can be shared by all sub-cores in the graphics processor  500 , for example, in lower performance and/or lower power graphics processor implementations. In various embodiments, the geometry/fixed function pipeline  536  includes a 3D fixed function pipeline (e.g., 3D pipeline  312  as in  FIG. 3  and  FIG. 4 ) a video front-end unit, a thread spawner and thread dispatcher, and a unified return buffer manager, which manages unified return buffers, such as the unified return buffer  418  of  FIG. 4 . 
     In one embodiment the fixed function block  530  also includes a graphics SoC interface  537 , a graphics microcontroller  538 , and a media pipeline  539 . The graphics SoC interface  537  provides an interface between the graphics core  500  and other processor cores within a system on a chip integrated circuit. The graphics microcontroller  538  is a programmable sub-processor that is configurable to manage various functions of the graphics processor  500 , including thread dispatch, scheduling, and pre-emption. The media pipeline  539  (e.g., media pipeline  316  of  FIG. 3  and  FIG. 4 ) includes logic to facilitate the decoding, encoding, pre-processing, and/or post-processing of multimedia data, including image and video data. The media pipeline  539  implement media operations via requests to compute or sampling logic within the sub-cores  501 - 501 F. 
     In one embodiment the SoC interface  537  enables the graphics core  500  to communicate with general-purpose application processor cores (e.g., CPUs) and/or other components within an SoC, including memory hierarchy elements such as a shared last level cache memory, the system RAM, and/or embedded on-chip or on-package DRAM. The SoC interface  537  can also enable communication with fixed function devices within the SoC, such as camera imaging pipelines, and enables the use of and/or implements global memory atomics that may be shared between the graphics core  500  and CPUs within the SoC. The SoC interface  537  can also implement power management controls for the graphics core  500  and enable an interface between a clock domain of the graphic core  500  and other clock domains within the SoC. In one embodiment the SoC interface  537  enables receipt of command buffers from a command streamer and global thread dispatcher that are configured to provide commands and instructions to each of one or more graphics cores within a graphics processor. The commands and instructions can be dispatched to the media pipeline  539 , when media operations are to be performed, or a geometry and fixed function pipeline (e.g., geometry and fixed function pipeline  536 , geometry and fixed function pipeline  514 ) when graphics processing operations are to be performed. 
     The graphics microcontroller  538  can be configured to perform various scheduling and management tasks for the graphics core  500 . In one embodiment the graphics microcontroller  538  can perform graphics and/or compute workload scheduling on the various graphics parallel engines within execution unit (EU) arrays  502 A- 502 F,  504 A- 504 F within the sub-cores  501 A- 501 F. In this scheduling model, host software executing on a CPU core of an SoC including the graphics core  500  can submit workloads one of multiple graphic processor doorbells, which invokes a scheduling operation on the appropriate graphics engine. Scheduling operations include determining which workload to run next, submitting a workload to a command streamer, pre-empting existing workloads running on an engine, monitoring progress of a workload, and notifying host software when a workload is complete. In one embodiment the graphics microcontroller  538  can also facilitate low-power or idle states for the graphics core  500 , providing the graphics core  500  with the ability to save and restore registers within the graphics core  500  across low-power state transitions independently from the operating system and/or graphics driver software on the system. 
     The graphics core  500  may have greater than or fewer than the illustrated sub-cores  501 A- 501 F, up to N modular sub-cores. For each set of N sub-cores, the graphics core  500  can also include shared function logic  510 , shared and/or cache memory  512 , a geometry/fixed function pipeline  514 , as well as additional fixed function logic  516  to accelerate various graphics and compute processing operations. The shared function logic  510  can include logic units associated with the shared function logic  420  of  FIG. 4  (e.g., sampler, math, and/or inter-thread communication logic) that can be shared by each N sub-cores within the graphics core  500 . The shared and/or cache memory  512  can be a last-level cache for the set of N sub-cores  501 A- 501 F within the graphics core  500 , and can also serve as shared memory that is accessible by multiple sub-cores. The geometry/fixed function pipeline  514  can be included instead of the geometry/fixed function pipeline  536  within the fixed function block  530  and can include the same or similar logic units. 
     In one embodiment the graphics core  500  includes additional fixed function logic  516  that can include various fixed function acceleration logic for use by the graphics core  500 . In one embodiment the additional fixed function logic  516  includes an additional geometry pipeline for use in position only shading. In position-only shading, two geometry pipelines exist, the full geometry pipeline within the geometry/fixed function pipeline  516 ,  536 , and a cull pipeline, which is an additional geometry pipeline which may be included within the additional fixed function logic  516 . In one embodiment the cull pipeline is a trimmed down version of the full geometry pipeline. The full pipeline and the cull pipeline can execute different instances of the same application, each instance having a separate context. Position only shading can hide long cull runs of discarded triangles, enabling shading to be completed earlier in some instances. For example and in one embodiment the cull pipeline logic within the additional fixed function logic  516  can execute position shaders in parallel with the main application and generally generates critical results faster than the full pipeline, as the cull pipeline fetches and shades only the position attribute of the vertices, without performing rasterization and rendering of the pixels to the frame buffer. The cull pipeline can use the generated critical results to compute visibility information for all the triangles without regard to whether those triangles are culled. The full pipeline (which in this instance may be referred to as a replay pipeline) can consume the visibility information to skip the culled triangles to shade only the visible triangles that are finally passed to the rasterization phase. 
     In one embodiment the additional fixed function logic  516  can also include machine-learning acceleration logic, such as fixed function matrix multiplication logic, for implementations including optimizations for machine learning training or inferencing. 
     Within each graphics sub-core  501 A- 501 F includes a set of execution resources that may be used to perform graphics, media, and compute operations in response to requests by graphics pipeline, media pipeline, or shader programs. The graphics sub-cores  501 A- 501 F include multiple EU arrays  502 A- 502 F,  504 A- 504 F, thread dispatch and inter-thread communication (TD/IC) logic  503 A- 503 F, a 3D (e.g., texture) sampler  505 A- 505 F, a media sampler  506 A- 506 F, a shader processor  507 A- 507 F, and shared local memory (SLM)  508 A- 508 F. The EU arrays  502 A- 502 F,  504 A- 504 F each include multiple execution units, which are general-purpose graphics processing units capable of performing floating-point and integer/fixed-point logic operations in service of a graphics, media, or compute operation, including graphics, media, or compute shader programs. The TD/IC logic  503 A- 503 F performs local thread dispatch and thread control operations for the execution units within a sub-core and facilitate communication between threads executing on the execution units of the sub-core. The 3D sampler  505 A- 505 F can read texture or other 3D graphics related data into memory. The 3D sampler can read texture data differently based on a configured sample state and the texture format associated with a given texture. The media sampler  506 A- 506 F can perform similar read operations based on the type and format associated with media data. In one embodiment, each graphics sub-core  501 A- 501 F can alternately include a unified 3D and media sampler. Threads executing on the execution units within each of the sub-cores  501 A- 501 F can make use of shared local memory  508 A- 508 F within each sub-core, to enable threads executing within a thread group to execute using a common pool of on-chip memory. 
     Execution Units 
       FIGS. 6A-6B  illustrate thread execution logic  600  including an array of processing elements employed in a graphics processor core according to embodiments described herein. Elements of  FIGS. 6A-6B  having the same reference numbers (or names) as the elements of any other figure herein can operate or function in any manner similar to that described elsewhere herein, but are not limited to such.  FIG. 6A  illustrates an overview of thread execution logic  600 , which can include a variant of the hardware logic illustrated with each sub-core  501 A- 501 F of  FIG. 5 .  FIG. 6B  illustrates exemplary internal details of an execution unit. 
     As illustrated in  FIG. 6A , in some embodiments thread execution logic  600  includes a shader processor  602 , a thread dispatcher  604 , instruction cache  606 , a scalable execution unit array including a plurality of execution units  608 A- 608 N, a sampler  610 , a data cache  612 , and a data port  614 . In one embodiment the scalable execution unit array can dynamically scale by enabling or disabling one or more execution units (e.g., any of execution unit  608 A,  608 B,  608 C,  608 D, through  608 N- 1  and  608 N) based on the computational requirements of a workload. In one embodiment the included components are interconnected via an interconnect fabric that links to each of the components. In some embodiments, thread execution logic  600  includes one or more connections to memory, such as system memory or cache memory, through one or more of instruction cache  606 , data port  614 , sampler  610 , and execution units  608 A- 608 N. In some embodiments, each execution unit (e.g.  608 A) is a stand-alone programmable general-purpose computational unit that is capable of executing multiple simultaneous hardware threads while processing multiple data elements in parallel for each thread. In various embodiments, the array of execution units  608 A- 608 N is scalable to include any number individual execution units. 
     In some embodiments, the execution units  608 A- 608 N are primarily used to execute shader programs. A shader processor  602  can process the various shader programs and dispatch execution threads associated with the shader programs via a thread dispatcher  604 . In one embodiment the thread dispatcher includes logic to arbitrate thread initiation requests from the graphics and media pipelines and instantiate the requested threads on one or more execution unit in the execution units  608 A- 608 N. For example, a geometry pipeline can dispatch vertex, tessellation, or geometry shaders to the thread execution logic for processing. In some embodiments, thread dispatcher  604  can also process runtime thread spawning requests from the executing shader programs. 
     In some embodiments, the execution units  608 A- 608 N support an instruction set that includes native support for many standard 3D graphics shader instructions, such that shader programs from graphics libraries (e.g., Direct 3D and OpenGL) are executed with a minimal translation. The execution units support vertex and geometry processing (e.g., vertex programs, geometry programs, vertex shaders), pixel processing (e.g., pixel shaders, fragment shaders) and general-purpose processing (e.g., compute and media shaders). Each of the execution units  608 A- 608 N is capable of multi-issue single instruction multiple data (SIMD) execution and multi-threaded operation enables an efficient execution environment in the face of higher latency memory accesses. Each hardware thread within each execution unit has a dedicated high-bandwidth register file and associated independent thread-state. Execution is multi-issue per clock to pipelines capable of integer, single and double precision floating point operations, SIMD branch capability, logical operations, transcendental operations, and other miscellaneous operations. While waiting for data from memory or one of the shared functions, dependency logic within the execution units  608 A- 608 N causes a waiting thread to sleep until the requested data has been returned. While the waiting thread is sleeping, hardware resources may be devoted to processing other threads. For example, during a delay associated with a vertex shader operation, an execution unit can perform operations for a pixel shader, fragment shader, or another type of shader program, including a different vertex shader. 
     Each execution unit in execution units  608 A- 608 N operates on arrays of data elements. The number of data elements is the “execution size,” or the number of channels for the instruction. An execution channel is a logical unit of execution for data element access, masking, and flow control within instructions. The number of channels may be independent of the number of physical Arithmetic Logic Units (ALUs) or Floating Point Units (FPUs) for a particular graphics processor. In some embodiments, execution units  608 A- 608 N support integer and floating-point data types. 
     The execution unit instruction set includes SIMD instructions. The various data elements can be stored as a packed data type in a register and the execution unit will process the various elements based on the data size of the elements. For example, when operating on a 256-bit wide vector, the 256 bits of the vector are stored in a register and the execution unit operates on the vector as four separate 64-bit packed data elements (Quad-Word (QW) size data elements), eight separate 32-bit packed data elements (Double Word (DW) size data elements), sixteen separate 16-bit packed data elements (Word (W) size data elements), or thirty-two separate 8-bit data elements (byte (B) size data elements). However, different vector widths and register sizes are possible. 
     In one embodiment one or more execution units can be combined into a fused execution unit  609 A- 609 N having thread control logic ( 607 A- 607 N) that is common to the fused EUs. Multiple EUs can be fused into an EU group. Each EU in the fused EU group can be configured to execute a separate SIMD hardware thread. The number of EUs in a fused EU group can vary according to embodiments. Additionally, various SIMD widths can be performed per-EU, including but not limited to SIMD8, SIMD16, and SIMD32. Each fused graphics execution unit  609 A- 609 N includes at least two execution units. For example, fused execution unit  609 A includes a first EU  608 A, second EU  608 B, and thread control logic  607 A that is common to the first EU  608 A and the second EU  608 B. The thread control logic  607 A controls threads executed on the fused graphics execution unit  609 A, allowing each EU within the fused execution units  609 A- 609 N to execute using a common instruction pointer register. 
     One or more internal instruction caches (e.g.,  606 ) are included in the thread execution logic  600  to cache thread instructions for the execution units. In some embodiments, one or more data caches (e.g.,  612 ) are included to cache thread data during thread execution. In some embodiments, a sampler  610  is included to provide texture sampling for 3D operations and media sampling for media operations. In some embodiments, sampler  610  includes specialized texture or media sampling functionality to process texture or media data during the sampling process before providing the sampled data to an execution unit. 
     During execution, the graphics and media pipelines send thread initiation requests to thread execution logic  600  via thread spawning and dispatch logic. Once a group of geometric objects has been processed and rasterized into pixel data, pixel processor logic (e.g., pixel shader logic, fragment shader logic, etc.) within the shader processor  602  is invoked to further compute output information and cause results to be written to output surfaces (e.g., color buffers, depth buffers, stencil buffers, etc.). In some embodiments, a pixel shader or fragment shader calculates the values of the various vertex attributes that are to be interpolated across the rasterized object. In some embodiments, pixel processor logic within the shader processor  602  then executes an application programming interface (API)-supplied pixel or fragment shader program. To execute the shader program, the shader processor  602  dispatches threads to an execution unit (e.g.,  608 A) via thread dispatcher  604 . In some embodiments, shader processor  602  uses texture sampling logic in the sampler  610  to access texture data in texture maps stored in memory. Arithmetic operations on the texture data and the input geometry data compute pixel color data for each geometric fragment, or discards one or more pixels from further processing. 
     In some embodiments, the data port  614  provides a memory access mechanism for the thread execution logic  600  to output processed data to memory for further processing on a graphics processor output pipeline. In some embodiments, the data port  614  includes or couples to one or more cache memories (e.g., data cache  612 ) to cache data for memory access via the data port. 
     As illustrated in  FIG. 6B , a graphics execution unit  608  can include an instruction fetch unit  637 , a general register file array (GRF)  624 , an architectural register file array (ARF)  626 , a thread arbiter  622 , a send unit  630 , a branch unit  632 , a set of SIMD floating point units (FPUs)  634 , and in one embodiment a set of dedicated integer SIMD ALUs  635 . The GRF  624  and ARF  626  includes the set of general register files and architecture register files associated with each simultaneous hardware thread that may be active in the graphics execution unit  608 . In one embodiment, per thread architectural state is maintained in the ARF  626 , while data used during thread execution is stored in the GRF  624 . The execution state of each thread, including the instruction pointers for each thread, can be held in thread-specific registers in the ARF  626 . 
     In one embodiment the graphics execution unit  608  has an architecture that is a combination of Simultaneous Multi-Threading (SMT) and fine-grained Interleaved Multi-Threading (IMT). The architecture has a modular configuration that can be fine-tuned at design time based on a target number of simultaneous threads and number of registers per execution unit, where execution unit resources are divided across logic used to execute multiple simultaneous threads. 
     In one embodiment, the graphics execution unit  608  can co-issue multiple instructions, which may each be different instructions. The thread arbiter  622  of the graphics execution unit thread  608  can dispatch the instructions to one of the send unit  630 , branch unit  642 , or SIMD FPU(s)  634  for execution. Each execution thread can access 128 general-purpose registers within the GRF  624 , where each register can store 32 bytes, accessible as a SIMD 8-element vector of 32-bit data elements. In one embodiment, each execution unit thread has access to 4 Kbytes within the GRF  624 , although embodiments are not so limited, and greater or fewer register resources may be provided in other embodiments. In one embodiment up to seven threads can execute simultaneously, although the number of threads per execution unit can also vary according to embodiments. In an embodiment in which seven threads may access 4 Kbytes, the GRF  624  can store a total of 28 Kbytes. Flexible addressing modes can permit registers to be addressed together to build effectively wider registers or to represent strided rectangular block data structures. 
     In one embodiment, memory operations, sampler operations, and other longer-latency system communications are dispatched via “send” instructions that are executed by the message passing send unit  630 . In one embodiment, branch instructions are dispatched to a dedicated branch unit  632  to facilitate SIMD divergence and eventual convergence. 
     In one embodiment the graphics execution unit  608  includes one or more SIMD floating point units (FPU(s))  634  to perform floating-point operations. In one embodiment, the FPU(s)  634  also support integer computation. In one embodiment the FPU(s)  634  can SIMD execute up to M number of 32-bit floating-point (or integer) operations, or SIMD execute up to 2M 16-bit integer or 16-bit floating-point operations. In one embodiment, at least one of the FPU(s) provides extended math capability to support high-throughput transcendental math functions and double precision 64-bit floating-point. In some embodiments, a set of 8-bit integer SIMD ALUs  635  are also present, and may be specifically optimized to perform operations associated with machine learning computations. 
     In one embodiment, arrays of multiple instances of the graphics execution unit  608  can be instantiated in a graphics sub-core grouping (e.g., a sub-slice). For scalability, product architects can choose the exact number of execution units per sub-core grouping. In one embodiment the execution unit  608  can execute instructions across a plurality of execution channels. In a further embodiment, each thread executed on the graphics execution unit  608  is executed on a different channel. 
       FIG. 7  is a block diagram illustrating a graphics processor instruction formats  700  according to some embodiments. In one or more embodiment, the graphics processor execution units support an instruction set having instructions in multiple formats. The solid lined boxes illustrate the components that are generally included in an execution unit instruction, while the dashed lines include components that are optional or that are only included in a sub-set of the instructions. In some embodiments, instruction format  700  described and illustrated are macro-instructions, in that they are instructions supplied to the execution unit, as opposed to micro-operations resulting from instruction decode once the instruction is processed. 
     In some embodiments, the graphics processor execution units natively support instructions in a 128-bit instruction format  710 . A 64-bit compacted instruction format  730  is available for some instructions based on the selected instruction, instruction options, and number of operands. The native 128-bit instruction format  710  provides access to all instruction options, while some options and operations are restricted in the 64-bit format  730 . The native instructions available in the 64-bit format  730  vary by embodiment. In some embodiments, the instruction is compacted in part using a set of index values in an index field  713 . The execution unit hardware references a set of compaction tables based on the index values and uses the compaction table outputs to reconstruct a native instruction in the 128-bit instruction format  710 . 
     For each format, instruction opcode  712  defines the operation that the execution unit is to perform. The execution units execute each instruction in parallel across the multiple data elements of each operand. For example, in response to an add instruction the execution unit performs a simultaneous add operation across each color channel representing a texture element or picture element. By default, the execution unit performs each instruction across all data channels of the operands. In some embodiments, instruction control field  714  enables control over certain execution options, such as channels selection (e.g., predication) and data channel order (e.g., swizzle). For instructions in the 128-bit instruction format  710  an exec-size field  716  limits the number of data channels that will be executed in parallel. In some embodiments, exec-size field  716  is not available for use in the 64-bit compact instruction format  730 . 
     Some execution unit instructions have up to three operands including two source operands, src0  720 , src1  722 , and one destination  718 . In some embodiments, the execution units support dual destination instructions, where one of the destinations is implied. Data manipulation instructions can have a third source operand (e.g., SRC2  724 ), where the instruction opcode  712  determines the number of source operands. An instruction&#39;s last source operand can be an immediate (e.g., hard-coded) value passed with the instruction. 
     In some embodiments, the 128-bit instruction format  710  includes an access/address mode field  726  specifying, for example, whether direct register addressing mode or indirect register addressing mode is used. When direct register addressing mode is used, the register address of one or more operands is directly provided by bits in the instruction. 
     In some embodiments, the 128-bit instruction format  710  includes an access/address mode field  726 , which specifies an address mode and/or an access mode for the instruction. In one embodiment the access mode is used to define a data access alignment for the instruction. Some embodiments support access modes including a 16-byte aligned access mode and a 1-byte aligned access mode, where the byte alignment of the access mode determines the access alignment of the instruction operands. For example, when in a first mode, the instruction may use byte-aligned addressing for source and destination operands and when in a second mode, the instruction may use 16-byte-aligned addressing for all source and destination operands. 
     In one embodiment, the address mode portion of the access/address mode field  726  determines whether the instruction is to use direct or indirect addressing. When direct register addressing mode is used bits in the instruction directly provide the register address of one or more operands. When indirect register addressing mode is used, the register address of one or more operands may be computed based on an address register value and an address immediate field in the instruction. 
     In some embodiments instructions are grouped based on opcode  712  bit-fields to simplify Opcode decode  740 . For an 8-bit opcode, bits  4 ,  5 , and  6  allow the execution unit to determine the type of opcode. The precise opcode grouping shown is merely an example. In some embodiments, a move and logic opcode group  742  includes data movement and logic instructions (e.g., move (mov), compare (cmp)). In some embodiments, move and logic group  742  shares the five most significant bits (MSB), where move (mov) instructions are in the form of 0000xxxxb and logic instructions are in the form of 0001xxxxb. A flow control instruction group  744  (e.g., call, jump (jmp)) includes instructions in the form of 0010xxxxb (e.g., 0x20). A miscellaneous instruction group  746  includes a mix of instructions, including synchronization instructions (e.g., wait, send) in the form of 0011xxxxb (e.g., 0x30). A parallel math instruction group  748  includes component-wise arithmetic instructions (e.g., add, multiply (mul)) in the form of 0100xxxxb (e.g., 0x40). The parallel math group  748  performs the arithmetic operations in parallel across data channels. The vector math group  750  includes arithmetic instructions (e.g., dp4) in the form of 0101xxxxb (e.g., 0x50). The vector math group performs arithmetic such as dot product calculations on vector operands. 
     Graphics Pipeline 
       FIG. 8  is a block diagram of another embodiment of a graphics processor  800 . Elements of  FIG. 8  having the same reference numbers (or names) as the elements of any other figure herein can operate or function in any manner similar to that described elsewhere herein, but are not limited to such. 
     In some embodiments, graphics processor  800  includes a geometry pipeline  820 , a media pipeline  830 , a display engine  840 , thread execution logic  850 , and a render output pipeline  870 . In some embodiments, graphics processor  800  is a graphics processor within a multi-core processing system that includes one or more general-purpose processing cores. The graphics processor is controlled by register writes to one or more control registers (not shown) or via commands issued to graphics processor  800  via a ring interconnect  802 . In some embodiments, ring interconnect  802  couples graphics processor  800  to other processing components, such as other graphics processors or general-purpose processors. Commands from ring interconnect  802  are interpreted by a command streamer  803 , which supplies instructions to individual components of the geometry pipeline  820  or the media pipeline  830 . 
     In some embodiments, command streamer  803  directs the operation of a vertex fetcher  805  that reads vertex data from memory and executes vertex-processing commands provided by command streamer  803 . In some embodiments, vertex fetcher  805  provides vertex data to a vertex shader  807 , which performs coordinate space transformation and lighting operations to each vertex. In some embodiments, vertex fetcher  805  and vertex shader  807  execute vertex-processing instructions by dispatching execution threads to execution units  852 A- 852 B via a thread dispatcher  831 . 
     In some embodiments, execution units  852 A- 852 B are an array of vector processors having an instruction set for performing graphics and media operations. In some embodiments, execution units  852 A- 852 B have an attached L1 cache  851  that is specific for each array or shared between the arrays. The cache can be configured as a data cache, an instruction cache, or a single cache that is partitioned to contain data and instructions in different partitions. 
     In some embodiments, geometry pipeline  820  includes tessellation components to perform hardware-accelerated tessellation of 3D objects. In some embodiments, a programmable hull shader  811  configures the tessellation operations. A programmable domain shader  817  provides back-end evaluation of tessellation output. A tessellator  813  operates at the direction of hull shader  811  and contains special purpose logic to generate a set of detailed geometric objects based on a coarse geometric model that is provided as input to geometry pipeline  820 . In some embodiments, if tessellation is not used, tessellation components (e.g., hull shader  811 , tessellator  813 , and domain shader  817 ) can be bypassed. 
     In some embodiments, complete geometric objects can be processed by a geometry shader  819  via one or more threads dispatched to execution units  852 A- 852 B, or can proceed directly to the clipper  829 . In some embodiments, the geometry shader operates on entire geometric objects, rather than vertices or patches of vertices as in previous stages of the graphics pipeline. If the tessellation is disabled the geometry shader  819  receives input from the vertex shader  807 . In some embodiments, geometry shader  819  is programmable by a geometry shader program to perform geometry tessellation if the tessellation units are disabled. 
     Before rasterization, a clipper  829  processes vertex data. The clipper  829  may be a fixed function clipper or a programmable clipper having clipping and geometry shader functions. In some embodiments, a rasterizer and depth test component  873  in the render output pipeline  870  dispatches pixel shaders to convert the geometric objects into per pixel representations. In some embodiments, pixel shader logic is included in thread execution logic  850 . In some embodiments, an application can bypass the rasterizer and depth test component  873  and access un-rasterized vertex data via a stream out unit  823 . 
     The graphics processor  800  has an interconnect bus, interconnect fabric, or some other interconnect mechanism that allows data and message passing amongst the major components of the processor. In some embodiments, execution units  852 A- 852 B and associated logic units (e.g., L1 cache  851 , sampler  854 , texture cache  858 , etc.) interconnect via a data port  856  to perform memory access and communicate with render output pipeline components of the processor. In some embodiments, sampler  854 , caches  851 ,  858  and execution units  852 A- 852 B each have separate memory access paths. In one embodiment the texture cache  858  can also be configured as a sampler cache. 
     In some embodiments, render output pipeline  870  contains a rasterizer and depth test component  873  that converts vertex-based objects into an associated pixel-based representation. In some embodiments, the rasterizer logic includes a windower/masker unit to perform fixed function triangle and line rasterization. An associated render cache  878  and depth cache  879  are also available in some embodiments. A pixel operations component  877  performs pixel-based operations on the data, though in some instances, pixel operations associated with 2D operations (e.g. bit block image transfers with blending) are performed by the 2D engine  841 , or substituted at display time by the display controller  843  using overlay display planes. In some embodiments, a shared L3 cache  875  is available to all graphics components, allowing the sharing of data without the use of main system memory. 
     In some embodiments, graphics processor media pipeline  830  includes a media engine  837  and a video front-end  834 . In some embodiments, video front-end  834  receives pipeline commands from the command streamer  803 . In some embodiments, media pipeline  830  includes a separate command streamer. In some embodiments, video front-end  834  processes media commands before sending the command to the media engine  837 . In some embodiments, media engine  837  includes thread spawning functionality to spawn threads for dispatch to thread execution logic  850  via thread dispatcher  831 . 
     In some embodiments, graphics processor  800  includes a display engine  840 . In some embodiments, display engine  840  is external to processor  800  and couples with the graphics processor via the ring interconnect  802 , or some other interconnect bus or fabric. In some embodiments, display engine  840  includes a 2D engine  841  and a display controller  843 . In some embodiments, display engine  840  contains special purpose logic capable of operating independently of the 3D pipeline. In some embodiments, display controller  843  couples with a display device (not shown), which may be a system integrated display device, as in a laptop computer, or an external display device attached via a display device connector. 
     In some embodiments, the geometry pipeline  820  and media pipeline  830  are configurable to perform operations based on multiple graphics and media programming interfaces and are not specific to any one application programming interface (API). In some embodiments, driver software for the graphics processor translates API calls that are specific to a particular graphics or media library into commands that can be processed by the graphics processor. In some embodiments, support is provided for the Open Graphics Library (OpenGL), Open Computing Language (OpenCL), and/or Vulkan graphics and compute API, all from the Khronos Group. In some embodiments, support may also be provided for the Direct3D library from the Microsoft Corporation. In some embodiments, a combination of these libraries may be supported. Support may also be provided for the Open Source Computer Vision Library (OpenCV). A future API with a compatible 3D pipeline would also be supported if a mapping can be made from the pipeline of the future API to the pipeline of the graphics processor. 
     Graphics Pipeline Programming 
       FIG. 9A  is a block diagram illustrating a graphics processor command format  900  according to some embodiments.  FIG. 9B  is a block diagram illustrating a graphics processor command sequence  910  according to an embodiment. The solid lined boxes in  FIG. 9A  illustrate the components that are generally included in a graphics command while the dashed lines include components that are optional or that are only included in a sub-set of the graphics commands. The exemplary graphics processor command format  900  of  FIG. 9A  includes data fields to identify a client  902 , a command operation code (opcode)  904 , and data  906  for the command. A sub-opcode  905  and a command size  908  are also included in some commands. 
     In some embodiments, client  902  specifies the client unit of the graphics device that processes the command data. In some embodiments, a graphics processor command parser examines the client field of each command to condition the further processing of the command and route the command data to the appropriate client unit. In some embodiments, the graphics processor client units include a memory interface unit, a render unit, a 2D unit, a 3D unit, and a media unit. Each client unit has a corresponding processing pipeline that processes the commands. Once the command is received by the client unit, the client unit reads the opcode  904  and, if present, sub-opcode  905  to determine the operation to perform. The client unit performs the command using information in data field  906 . For some commands an explicit command size  908  is expected to specify the size of the command. In some embodiments, the command parser automatically determines the size of at least some of the commands based on the command opcode. In some embodiments commands are aligned via multiples of a double word. 
     The flow diagram in  FIG. 9B  illustrates an exemplary graphics processor command sequence  910 . In some embodiments, software or firmware of a data processing system that features an embodiment of a graphics processor uses a version of the command sequence shown to set up, execute, and terminate a set of graphics operations. A sample command sequence is shown and described for purposes of example only as embodiments are not limited to these specific commands or to this command sequence. Moreover, the commands may be issued as batch of commands in a command sequence, such that the graphics processor will process the sequence of commands in at least partially concurrence. 
     In some embodiments, the graphics processor command sequence  910  may begin with a pipeline flush command  912  to cause any active graphics pipeline to complete the currently pending commands for the pipeline. In some embodiments, the 3D pipeline  922  and the media pipeline  924  do not operate concurrently. The pipeline flush is performed to cause the active graphics pipeline to complete any pending commands. In response to a pipeline flush, the command parser for the graphics processor will pause command processing until the active drawing engines complete pending operations and the relevant read caches are invalidated. Optionally, any data in the render cache that is marked ‘dirty’ can be flushed to memory. In some embodiments, pipeline flush command  912  can be used for pipeline synchronization or before placing the graphics processor into a low power state. 
     In some embodiments, a pipeline select command  913  is used when a command sequence requires the graphics processor to explicitly switch between pipelines. In some embodiments, a pipeline select command  913  is required only once within an execution context before issuing pipeline commands unless the context is to issue commands for both pipelines. In some embodiments, a pipeline flush command  912  is required immediately before a pipeline switch via the pipeline select command  913 . 
     In some embodiments, a pipeline control command  914  configures a graphics pipeline for operation and is used to program the 3D pipeline  922  and the media pipeline  924 . In some embodiments, pipeline control command  914  configures the pipeline state for the active pipeline. In one embodiment, the pipeline control command  914  is used for pipeline synchronization and to clear data from one or more cache memories within the active pipeline before processing a batch of commands. 
     In some embodiments, return buffer state commands  916  are used to configure a set of return buffers for the respective pipelines to write data. Some pipeline operations require the allocation, selection, or configuration of one or more return buffers into which the operations write intermediate data during processing. In some embodiments, the graphics processor also uses one or more return buffers to store output data and to perform cross thread communication. In some embodiments, the return buffer state  916  includes selecting the size and number of return buffers to use for a set of pipeline operations. 
     The remaining commands in the command sequence differ based on the active pipeline for operations. Based on a pipeline determination  920 , the command sequence is tailored to the 3D pipeline  922  beginning with the 3D pipeline state  930  or the media pipeline  924  beginning at the media pipeline state  940 . 
     The commands to configure the 3D pipeline state  930  include 3D state setting commands for vertex buffer state, vertex element state, constant color state, depth buffer state, and other state variables that are to be configured before 3D primitive commands are processed. The values of these commands are determined at least in part based on the particular 3D API in use. In some embodiments, 3D pipeline state  930  commands are also able to selectively disable or bypass certain pipeline elements if those elements will not be used. 
     In some embodiments, 3D primitive  932  command is used to submit 3D primitives to be processed by the 3D pipeline. Commands and associated parameters that are passed to the graphics processor via the 3D primitive  932  command are forwarded to the vertex fetch function in the graphics pipeline. The vertex fetch function uses the 3D primitive  932  command data to generate vertex data structures. The vertex data structures are stored in one or more return buffers. In some embodiments, 3D primitive  932  command is used to perform vertex operations on 3D primitives via vertex shaders. To process vertex shaders, 3D pipeline  922  dispatches shader execution threads to graphics processor execution units. 
     In some embodiments, 3D pipeline  922  is triggered via an execute  934  command or event. In some embodiments, a register write triggers command execution. In some embodiments execution is triggered via a ‘go’ or ‘kick’ command in the command sequence. In one embodiment, command execution is triggered using a pipeline synchronization command to flush the command sequence through the graphics pipeline. The 3D pipeline will perform geometry processing for the 3D primitives. Once operations are complete, the resulting geometric objects are rasterized and the pixel engine colors the resulting pixels. Additional commands to control pixel shading and pixel back end operations may also be included for those operations. 
     In some embodiments, the graphics processor command sequence  910  follows the media pipeline  924  path when performing media operations. In general, the specific use and manner of programming for the media pipeline  924  depends on the media or compute operations to be performed. Specific media decode operations may be offloaded to the media pipeline during media decode. In some embodiments, the media pipeline can also be bypassed and media decode can be performed in whole or in part using resources provided by one or more general-purpose processing cores. In one embodiment, the media pipeline also includes elements for general-purpose graphics processor unit (GPGPU) operations, where the graphics processor is used to perform SIMD vector operations using computational shader programs that are not explicitly related to the rendering of graphics primitives. 
     In some embodiments, media pipeline  924  is configured in a similar manner as the 3D pipeline  922 . A set of commands to configure the media pipeline state  940  are dispatched or placed into a command queue before the media object commands  942 . In some embodiments, commands for the media pipeline state  940  include data to configure the media pipeline elements that will be used to process the media objects. This includes data to configure the video decode and video encode logic within the media pipeline, such as encode or decode format. In some embodiments, commands for the media pipeline state  940  also support the use of one or more pointers to “indirect” state elements that contain a batch of state settings. 
     In some embodiments, media object commands  942  supply pointers to media objects for processing by the media pipeline. The media objects include memory buffers containing video data to be processed. In some embodiments, all media pipeline states must be valid before issuing a media object command  942 . Once the pipeline state is configured and media object commands  942  are queued, the media pipeline  924  is triggered via an execute command  944  or an equivalent execute event (e.g., register write). Output from media pipeline  924  may then be post processed by operations provided by the 3D pipeline  922  or the media pipeline  924 . In some embodiments, GPGPU operations are configured and executed in a similar manner as media operations. 
     Graphics Software Architecture 
       FIG. 10  illustrates exemplary graphics software architecture for a data processing system  1000  according to some embodiments. In some embodiments, software architecture includes a 3D graphics application  1010 , an operating system  1020 , and at least one processor  1030 . In some embodiments, processor  1030  includes a graphics processor  1032  and one or more general-purpose processor core(s)  1034 . The graphics application  1010  and operating system  1020  each execute in the system memory  1050  of the data processing system. 
     In some embodiments, 3D graphics application  1010  contains one or more shader programs including shader instructions  1012 . The shader language instructions may be in a high-level shader language, such as the High Level Shader Language (HLSL) or the OpenGL Shader Language (GLSL). The application also includes executable instructions  1014  in a machine language suitable for execution by the general-purpose processor core  1034 . The application also includes graphics objects  1016  defined by vertex data. 
     In some embodiments, operating system  1020  is a Microsoft® Windows® operating system from the Microsoft Corporation, a proprietary UNIX-like operating system, or an open source UNIX-like operating system using a variant of the Linux kernel. The operating system  1020  can support a graphics API  1022  such as the Direct3D API, the OpenGL API, or the Vulkan API. When the Direct3D API is in use, the operating system  1020  uses a front-end shader compiler  1024  to compile any shader instructions  1012  in HLSL into a lower-level shader language. The compilation may be a just-in-time (JIT) compilation or the application can perform shader pre-compilation. In some embodiments, high-level shaders are compiled into low-level shaders during the compilation of the 3D graphics application  1010 . In some embodiments, the shader instructions  1012  are provided in an intermediate form, such as a version of the Standard Portable Intermediate Representation (SPIR) used by the Vulkan API. 
     In some embodiments, user mode graphics driver  1026  contains a back-end shader compiler  1027  to convert the shader instructions  1012  into a hardware specific representation. When the OpenGL API is in use, shader instructions  1012  in the GLSL high-level language are passed to a user mode graphics driver  1026  for compilation. In some embodiments, user mode graphics driver  1026  uses operating system kernel mode functions  1028  to communicate with a kernel mode graphics driver  1029 . In some embodiments, kernel mode graphics driver  1029  communicates with graphics processor  1032  to dispatch commands and instructions. 
     IP Core Implementations 
     One or more aspects of at least one embodiment may be implemented by representative code stored on a machine-readable medium which represents and/or defines logic within an integrated circuit such as a processor. For example, the machine-readable medium may include instructions which represent various logic within the processor. When read by a machine, the instructions may cause the machine to fabricate the logic to perform the techniques described herein. Such representations, known as “IP cores,” are reusable units of logic for an integrated circuit that may be stored on a tangible, machine-readable medium as a hardware model that describes the structure of the integrated circuit. The hardware model may be supplied to various customers or manufacturing facilities, which load the hardware model on fabrication machines that manufacture the integrated circuit. The integrated circuit may be fabricated such that the circuit performs operations described in association with any of the embodiments described herein. 
       FIG. 11A  is a block diagram illustrating an IP core development system  1100  that may be used to manufacture an integrated circuit to perform operations according to an embodiment. The IP core development system  1100  may be used to generate modular, re-usable designs that can be incorporated into a larger design or used to construct an entire integrated circuit (e.g., an SOC integrated circuit). A design facility  1130  can generate a software simulation  1110  of an IP core design in a high-level programming language (e.g., C/C++). The software simulation  1110  can be used to design, test, and verify the behavior of the IP core using a simulation model  1112 . The simulation model  1112  may include functional, behavioral, and/or timing simulations. A register transfer level (RTL) design  1115  can then be created or synthesized from the simulation model  1112 . The RTL design  1115  is an abstraction of the behavior of the integrated circuit that models the flow of digital signals between hardware registers, including the associated logic performed using the modeled digital signals. In addition to an RTL design  1115 , lower-level designs at the logic level or transistor level may also be created, designed, or synthesized. Thus, the particular details of the initial design and simulation may vary. 
     The RTL design  1115  or equivalent may be further synthesized by the design facility into a hardware model  1120 , which may be in a hardware description language (HDL), or some other representation of physical design data. The HDL may be further simulated or tested to verify the IP core design. The IP core design can be stored for delivery to a 3 rd  party fabrication facility  1165  using non-volatile memory  1140  (e.g., hard disk, flash memory, or any non-volatile storage medium). Alternatively, the IP core design may be transmitted (e.g., via the Internet) over a wired connection  1150  or wireless connection  1160 . The fabrication facility  1165  may then fabricate an integrated circuit that is based at least in part on the IP core design. The fabricated integrated circuit can be configured to perform operations in accordance with at least one embodiment described herein. 
       FIG. 11B  illustrates a cross-section side view of an integrated circuit package assembly  1170 , according to some embodiments described herein. The integrated circuit package assembly  1170  illustrates an implementation of one or more processor or accelerator devices as described herein. The package assembly  1170  includes multiple units of hardware logic  1172 ,  1174  connected to a substrate  1180 . The logic  1172 ,  1174  may be implemented at least partly in configurable logic or fixed-functionality logic hardware, and can include one or more portions of any of the processor core(s), graphics processor(s), or other accelerator devices described herein. Each unit of logic  1172 ,  1174  can be implemented within a semiconductor die and coupled with the substrate  1180  via an interconnect structure  1173 . The interconnect structure  1173  may be configured to route electrical signals between the logic  1172 ,  1174  and the substrate  1180 , and can include interconnects such as, but not limited to bumps or pillars. In some embodiments, the interconnect structure  1173  may be configured to route electrical signals such as, for example, input/output (I/O) signals and/or power or ground signals associated with the operation of the logic  1172 ,  1174 . In some embodiments, the substrate  1180  is an epoxy-based laminate substrate. The package substrate  1180  may include other suitable types of substrates in other embodiments. The package assembly  1170  can be connected to other electrical devices via a package interconnect  1183 . The package interconnect  1183  may be coupled to a surface of the substrate  1180  to route electrical signals to other electrical devices, such as a motherboard, other chipset, or multi-chip module. 
     In some embodiments, the units of logic  1172 ,  1174  are electrically coupled with a bridge  1182  that is configured to route electrical signals between the logic  1172 ,  1174 . The bridge  1182  may be a dense interconnect structure that provides a route for electrical signals. The bridge  1182  may include a bridge substrate composed of glass or a suitable semiconductor material. Electrical routing features can be formed on the bridge substrate to provide a chip-to-chip connection between the logic  1172 ,  1174 . 
     Although two units of logic  1172 ,  1174  and a bridge  1182  are illustrated, embodiments described herein may include more or fewer logic units on one or more dies. The one or more dies may be connected by zero or more bridges, as the bridge  1182  may be excluded when the logic is included on a single die. Alternatively, multiple dies or units of logic can be connected by one or more bridges. Additionally, multiple logic units, dies, and bridges can be connected together in other possible configurations, including three-dimensional configurations. 
     Exemplary System on a Chip Integrated Circuit 
       FIGS. 12-14  illustrated exemplary integrated circuits and associated graphics processors that may be fabricated using one or more IP cores, according to various embodiments described herein. In addition to what is illustrated, other logic and circuits may be included, including additional graphics processors/cores, peripheral interface controllers, or general-purpose processor cores. 
       FIG. 12  is a block diagram illustrating an exemplary system on a chip integrated circuit  1200  that may be fabricated using one or more IP cores, according to an embodiment. Exemplary integrated circuit  1200  includes one or more application processor(s)  1205  (e.g., CPUs), at least one graphics processor  1210 , and may additionally include an image processor  1215  and/or a video processor  1220 , any of which may be a modular IP core from the same or multiple different design facilities. Integrated circuit  1200  includes peripheral or bus logic including a USB controller  1225 , UART controller  1230 , an SPI/SDIO controller  1235 , and an I 2 S/I 2 C controller  1240 . Additionally, the integrated circuit can include a display device  1245  coupled to one or more of a high-definition multimedia interface (HDMI) controller  1250  and a mobile industry processor interface (MIPI) display interface  1255 . Storage may be provided by a flash memory subsystem  1260  including flash memory and a flash memory controller. Memory interface may be provided via a memory controller  1265  for access to SDRAM or SRAM memory devices. Some integrated circuits additionally include an embedded security engine  1270 . 
       FIGS. 13A-13B  are block diagrams illustrating exemplary graphics processors for use within an SoC, according to embodiments described herein.  FIG. 13A  illustrates an exemplary graphics processor  1310  of a system on a chip integrated circuit that may be fabricated using one or more IP cores, according to an embodiment.  FIG. 13B  illustrates an additional exemplary graphics processor  1340  of a system on a chip integrated circuit that may be fabricated using one or more IP cores, according to an embodiment. Graphics processor  1310  of  FIG. 13A  is an example of a low power graphics processor core. Graphics processor  1340  of  FIG. 13B  is an example of a higher performance graphics processor core. Each of the graphics processors  1310 ,  1340  can be variants of the graphics processor  1210  of  FIG. 12 . 
     As shown in  FIG. 13A , graphics processor  1310  includes a vertex processor  1305  and one or more fragment processor(s)  1315 A- 1315 N (e.g.,  1315 A,  1315 B,  1315 C,  1315 D, through  1315 N- 1 , and  1315 N). Graphics processor  1310  can execute different shader programs via separate logic, such that the vertex processor  1305  is optimized to execute operations for vertex shader programs, while the one or more fragment processor(s)  1315 A- 1315 N execute fragment (e.g., pixel) shading operations for fragment or pixel shader programs. The vertex processor  1305  performs the vertex processing stage of the 3D graphics pipeline and generates primitives and vertex data. The fragment processor(s)  1315 A- 1315 N use the primitive and vertex data generated by the vertex processor  1305  to produce a framebuffer that is displayed on a display device. In one embodiment, the fragment processor(s)  1315 A- 1315 N are optimized to execute fragment shader programs as provided for in the OpenGL API, which may be used to perform similar operations as a pixel shader program as provided for in the Direct 3D API. 
     Graphics processor  1310  additionally includes one or more memory management units (MMUs)  1320 A- 1320 B, cache(s)  1325 A- 1325 B, and circuit interconnect(s)  1330 A- 1330 B. The one or more MMU(s)  1320 A- 1320 B provide for virtual to physical address mapping for the graphics processor  1310 , including for the vertex processor  1305  and/or fragment processor(s)  1315 A- 1315 N, which may reference vertex or image/texture data stored in memory, in addition to vertex or image/texture data stored in the one or more cache(s)  1325 A- 1325 B. In one embodiment the one or more MMU(s)  1320 A- 1320 B may be synchronized with other MMUs within the system, including one or more MMUs associated with the one or more application processor(s)  1205 , image processor  1215 , and/or video processor  1220  of  FIG. 12 , such that each processor  1205 - 1220  can participate in a shared or unified virtual memory system. The one or more circuit interconnect(s)  1330 A- 1330 B enable graphics processor  1310  to interface with other IP cores within the SoC, either via an internal bus of the SoC or via a direct connection, according to embodiments. 
     As shown  FIG. 13B , graphics processor  1340  includes the one or more MMU(s)  1320 A- 1320 B, caches  1325 A- 1325 B, and circuit interconnects  1330 A- 1330 B of the graphics processor  1310  of  FIG. 13A . Graphics processor  1340  includes one or more shader core(s)  1355 A- 1355 N (e.g.,  1455 A,  1355 B,  1355 C,  1355 D,  1355 E,  1355 F, through  1355 N- 1 , and  1355 N), which provides for a unified shader core architecture in which a single core or type or core can execute all types of programmable shader code, including shader program code to implement vertex shaders, fragment shaders, and/or compute shaders. The exact number of shader cores present can vary among embodiments and implementations. Additionally, graphics processor  1340  includes an inter-core task manager  1345 , which acts as a thread dispatcher to dispatch execution threads to one or more shader cores  1355 A- 1355 N and a tiling unit  1358  to accelerate tiling operations for tile-based rendering, in which rendering operations for a scene are subdivided in image space, for example to exploit local spatial coherence within a scene or to optimize use of internal caches. 
       FIGS. 14A-14B  illustrate additional exemplary graphics processor logic according to embodiments described herein.  FIG. 14A  illustrates a graphics core  1400  that may be included within the graphics processor  1210  of  FIG. 12 , and may be a unified shader core  1355 A- 1355 N as in  FIG. 13B .  FIG. 14B  illustrates a highly-parallel general-purpose graphics processing unit  1430  suitable for deployment on a multi-chip module. 
     As shown in  FIG. 14A , the graphics core  1400  includes a shared instruction cache  1402 , a texture unit  1418 , and a cache/shared memory  1420  that are common to the execution resources within the graphics core  1400 . The graphics core  1400  can include multiple slices  1401 A- 1401 N or partition for each core, and a graphics processor can include multiple instances of the graphics core  1400 . The slices  1401 A- 1401 N can include support logic including a local instruction cache  1404 A- 1404 N, a thread scheduler  1406 A- 1406 N, a thread dispatcher  1408 A- 1408 N, and a set of registers  1410 A. To perform logic operations, the slices  1401 A- 1401 N can include a set of additional function units (AFUs  1412 A- 1412 N), floating-point units (FPU  1414 A- 1414 N), integer arithmetic logic units (ALUs  1416 - 1416 N), address computational units (ACU  1413 A- 1413 N), double-precision floating-point units (DPFPU  1415 A- 1415 N), and matrix processing units (MPU  1417 A- 1417 N). 
     Some of the computational units operate at a specific precision. For example, the FPUs  1414 A- 1414 N can perform single-precision (32-bit) and half-precision (16-bit) floating point operations, while the DPFPUs  1415 A- 1415 N perform double precision (64-bit) floating point operations. The ALUs  1416 A- 1416 N can perform variable precision integer operations at 8-bit, 16-bit, and 32-bit precision, and can be configured for mixed precision operations. The MPUs  1417 A- 1417 N can also be configured for mixed precision matrix operations, including half-precision floating point and 8-bit integer operations. The MPUs  1417 - 1417 N can perform a variety of matrix operations to accelerate machine learning application frameworks, including enabling support for accelerated general matrix to matrix multiplication (GEMM). The AFUs  1412 A- 1412 N can perform additional logic operations not supported by the floating-point or integer units, including trigonometric operations (e.g., Sine, Cosine, etc.). 
     As shown in  FIG. 14B , a general-purpose processing unit (GPGPU)  1430  can be configured to enable highly-parallel compute operations to be performed by an array of graphics processing units. Additionally, the GPGPU  1430  can be linked directly to other instances of the GPGPU to create a multi-GPU cluster to improve training speed for particularly deep neural networks. The GPGPU  1430  includes a host interface  1432  to enable a connection with a host processor. In one embodiment the host interface  1432  is a PCI Express interface. However, the host interface can also be a vendor specific communications interface or communications fabric. The GPGPU  1430  receives commands from the host processor and uses a global scheduler  1434  to distribute execution threads associated with those commands to a set of compute clusters  1436 A- 1436 H. The compute clusters  1436 A- 1436 H share a cache memory  1438 . The cache memory  1438  can serve as a higher-level cache for cache memories within the compute clusters  1436 A- 1436 H. 
     The GPGPU  1430  includes memory  1434 A- 1434 B coupled with the compute clusters  1436 A- 1436 H via a set of memory controllers  1442 A- 1442 B. In various embodiments, the memory  1434 A- 1434 B can include various types of memory devices including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. 
     In one embodiment the compute clusters  1436 A- 1436 H each include a set of graphics cores, such as the graphics core  1400  of  FIG. 14A , which can include multiple types of integer and floating point logic units that can perform computational operations at a range of precisions including suited for machine learning computations. For example and in one embodiment at least a subset of the floating point units in each of the compute clusters  1436 A- 1436 H can be configured to perform 16-bit or 32-bit floating point operations, while a different subset of the floating point units can be configured to perform 64-bit floating point operations. 
     Multiple instances of the GPGPU  1430  can be configured to operate as a compute cluster. The communication mechanism used by the compute cluster for synchronization and data exchange varies across embodiments. In one embodiment the multiple instances of the GPGPU  1430  communicate over the host interface  1432 . In one embodiment the GPGPU  1430  includes an I/O hub  1439  that couples the GPGPU  1430  with a GPU link  1440  that enables a direct connection to other instances of the GPGPU. In one embodiment the GPU link  1440  is coupled to a dedicated GPU-to-GPU bridge that enables communication and synchronization between multiple instances of the GPGPU  1430 . In one embodiment the GPU link  1440  couples with a high speed interconnect to transmit and receive data to other GPGPUs or parallel processors. In one embodiment the multiple instances of the GPGPU  1430  are located in separate data processing systems and communicate via a network device that is accessible via the host interface  1432 . In one embodiment the GPU link  1440  can be configured to enable a connection to a host processor in addition to or as an alternative to the host interface  1432 . 
     While the illustrated configuration of the GPGPU  1430  can be configured to train neural networks, one embodiment provides alternate configuration of the GPGPU  1430  that can be configured for deployment within a high performance or low power inferencing platform. In an inferencing configuration the GPGPU  1430  includes fewer of the compute clusters  1436 A- 1436 H relative to the training configuration. Additionally, the memory technology associated with the memory  1434 A- 1434 B may differ between inferencing and training configurations, with higher bandwidth memory technologies devoted to training configurations. In one embodiment the inferencing configuration of the GPGPU  1430  can support inferencing specific instructions. For example, an inferencing configuration can provide support for one or more 8-bit integer dot product instructions, which are commonly used during inferencing operations for deployed neural networks 
     Machine Learning Overview 
     A machine learning algorithm is an algorithm that can learn based on a set of data. Embodiments of machine learning algorithms can be designed to model high-level abstractions within a data set. For example, image recognition algorithms can be used to determine which of several categories to which a given input belong; regression algorithms can output a numerical value given an input; and pattern recognition algorithms can be used to generate translated text or perform text to speech and/or speech recognition. 
     An exemplary type of machine learning algorithm is a neural network. There are many types of neural networks; a simple type of neural network is a feedforward network. A feedforward network may be implemented as an acyclic graph in which the nodes are arranged in layers. Typically, a feedforward network topology includes an input layer and an output layer that are separated by at least one hidden layer. The hidden layer transforms input received by the input layer into a representation that is useful for generating output in the output layer. The network nodes are fully connected via edges to the nodes in adjacent layers, but there are no edges between nodes within each layer. Data received at the nodes of an input layer of a feedforward network are propagated (i.e., “fed forward”) to the nodes of the output layer via an activation function that calculates the states of the nodes of each successive layer in the network based on coefficients (“weights”) respectively associated with each of the edges connecting the layers. Depending on the specific model being represented by the algorithm being executed, the output from the neural network algorithm can take various forms. 
     Before a machine learning algorithm can be used to model a particular problem, the algorithm is trained using a training data set. Training a neural network involves selecting a network topology, using a set of training data representing a problem being modeled by the network, and adjusting the weights until the network model performs with a minimal error for all instances of the training data set. For example, during a supervised learning training process for a neural network, the output produced by the network in response to the input representing an instance in a training data set is compared to the “correct” labeled output for that instance, an error signal representing the difference between the output and the labeled output is calculated, and the weights associated with the connections are adjusted to minimize that error as the error signal is backward propagated through the layers of the network. The network is considered “trained” when the errors for each of the outputs generated from the instances of the training data set are minimized. 
     The accuracy of a machine learning algorithm can be affected significantly by the quality of the data set used to train the algorithm. The training process can be computationally intensive and may require a significant amount of time on a conventional general-purpose processor. Accordingly, parallel processing hardware is used to train many types of machine learning algorithms. This is particularly useful for optimizing the training of neural networks, as the computations performed in adjusting the coefficients in neural networks lend themselves naturally to parallel implementations. Specifically, many machine learning algorithms and software applications have been adapted to make use of the parallel processing hardware within general-purpose graphics processing devices. 
       FIG. 15  is a generalized diagram of a machine learning software stack  1500 . A machine learning application  1502  can be configured to train a neural network using a training dataset or to use a trained deep neural network to implement machine intelligence. The machine learning application  1502  can include training and inference functionality for a neural network and/or specialized software that can be used to train a neural network before deployment. The machine learning application  1502  can implement any type of machine intelligence including but not limited to image recognition, mapping and localization, autonomous navigation, speech synthesis, medical imaging, or language translation. 
     Hardware acceleration for the machine learning application  1502  can be enabled via a machine learning framework  1504 . The machine learning framework  1504  can provide a library of machine learning primitives. Machine learning primitives are basic operations that are commonly performed by machine learning algorithms. Without the machine learning framework  1504 , developers of machine learning algorithms would be required to create and optimize the main computational logic associated with the machine learning algorithm, then re-optimize the computational logic as new parallel processors are developed. Instead, the machine learning application can be configured to perform the necessary computations using the primitives provided by the machine learning framework  1504 . Exemplary primitives include tensor convolutions, activation functions, and pooling, which are computational operations that are performed while training a convolutional neural network (CNN). The machine learning framework  1504  can also provide primitives to implement basic linear algebra subprograms performed by many machine-learning algorithms, such as matrix and vector operations. 
     The machine learning framework  1504  can process input data received from the machine learning application  1502  and generate the appropriate input to a compute framework  1506 . The compute framework  1506  can abstract the underlying instructions provided to the GPGPU driver  1508  to enable the machine learning framework  1504  to take advantage of hardware acceleration via the GPGPU hardware  1510  without requiring the machine learning framework  1504  to have intimate knowledge of the architecture of the GPGPU hardware  1510 . Additionally, the compute framework  1506  can enable hardware acceleration for the machine learning framework  1504  across a variety of types and generations of the GPGPU hardware  1510 . 
     Machine Learning Neural Network Implementations 
     The computing architecture provided by embodiments described herein can be configured to perform the types of parallel processing that is particularly suited for training and deploying neural networks for machine learning. A neural network can be generalized as a network of functions having a graph relationship. As is known in the art, there are a variety of types of neural network implementations used in machine learning. One exemplary type of neural network is the feedforward network, as previously described. 
     A second exemplary type of neural network is the Convolutional Neural Network (CNN). A CNN is a specialized feedforward neural network for processing data having a known, grid-like topology, such as image data. Accordingly, CNNs are commonly used for compute vision and image recognition applications, but they also may be used for other types of pattern recognition such as speech and language processing. The nodes in the CNN input layer are organized into a set of “filters” (feature detectors inspired by the receptive fields found in the retina), and the output of each set of filters is propagated to nodes in successive layers of the network. The computations for a CNN include applying the convolution mathematical operation to each filter to produce the output of that filter. Convolution is a specialized kind of mathematical operation performed by two functions to produce a third function that is a modified version of one of the two original functions. In convolutional network terminology, the first function to the convolution can be referred to as the input, while the second function can be referred to as the convolution kernel. The output may be referred to as the feature map. For example, the input to a convolution layer can be a multidimensional array of data that defines the various color components of an input image. The convolution kernel can be a multidimensional array of parameters, where the parameters are adapted by the training process for the neural network. 
     Recurrent neural networks (RNNs) are a family of feedforward neural networks that include feedback connections between layers. RNNs enable modeling of sequential data by sharing parameter data across different parts of the neural network. The architecture for a RNN includes cycles. The cycles represent the influence of a present value of a variable on its own value at a future time, as at least a portion of the output data from the RNN is used as feedback for processing subsequent input in a sequence. This feature makes RNNs particularly useful for language processing due to the variable nature in which language data can be composed. 
     The figures described below present exemplary feedforward, CNN, and RNN networks, as well as describe a general process for respectively training and deploying each of those types of networks. It will be understood that these descriptions are exemplary and non-limiting as to any specific embodiment described herein and the concepts illustrated can be applied generally to deep neural networks and machine learning techniques in general. 
     The exemplary neural networks described above can be used to perform deep learning. Deep learning is machine learning using deep neural networks. The deep neural networks used in deep learning are artificial neural networks composed of multiple hidden layers, as opposed to shallow neural networks that include only a single hidden layer. Deeper neural networks are generally more computationally intensive to train. However, the additional hidden layers of the network enable multistep pattern recognition that results in reduced output error relative to shallow machine learning techniques. 
     Deep neural networks used in deep learning typically include a front-end network to perform feature recognition coupled to a back-end network which represents a mathematical model that can perform operations (e.g., object classification, speech recognition, etc.) based on the feature representation provided to the model. Deep learning enables machine learning to be performed without requiring hand crafted feature engineering to be performed for the model. Instead, deep neural networks can learn features based on statistical structure or correlation within the input data. The learned features can be provided to a mathematical model that can map detected features to an output. The mathematical model used by the network is generally specialized for the specific task to be performed, and different models will be used to perform different task. 
     Once the neural network is structured, a learning model can be applied to the network to train the network to perform specific tasks. The learning model describes how to adjust the weights within the model to reduce the output error of the network. Backpropagation of errors is a common method used to train neural networks. An input vector is presented to the network for processing. The output of the network is compared to the desired output using a loss function and an error value is calculated for each of the neurons in the output layer. The error values are then propagated backwards until each neuron has an associated error value which roughly represents its contribution to the original output. The network can then learn from those errors using an algorithm, such as the stochastic gradient descent algorithm, to update the weights of the of the neural network. 
       FIG. 16A-16B  illustrate an exemplary convolutional neural network.  FIG. 16A  illustrates various layers within a CNN. As shown in  FIG. 16A , an exemplary CNN used to model image processing can receive input  1602  describing the red, green, and blue (RGB) components of an input image. The input  1602  can be processed by multiple convolutional layers (e.g., first convolutional layer  1604 , second convolutional layer  1606 ). The output from the multiple convolutional layers may optionally be processed by a set of fully connected layers  1608 . Neurons in a fully connected layer have full connections to all activations in the previous layer, as previously described for a feedforward network. The output from the fully connected layers  1608  can be used to generate an output result from the network. The activations within the fully connected layers  1608  can be computed using matrix multiplication instead of convolution. Not all CNN implementations are make use of fully connected layers  1608 . For example, in some implementations the second convolutional layer  1606  can generate output for the CNN. 
     The convolutional layers are sparsely connected, which differs from traditional neural network configuration found in the fully connected layers  1608 . Traditional neural network layers are fully connected, such that every output unit interacts with every input unit. However, the convolutional layers are sparsely connected because the output of the convolution of a field is input (instead of the respective state value of each of the nodes in the field) to the nodes of the subsequent layer, as illustrated. The kernels associated with the convolutional layers perform convolution operations, the output of which is sent to the next layer. The dimensionality reduction performed within the convolutional layers is one aspect that enables the CNN to scale to process large images. 
       FIG. 16B  illustrates exemplary computation stages within a convolutional layer of a CNN. Input to a convolutional layer  1612  of a CNN can be processed in three stages of a convolutional layer  1614 . The three stages can include a convolution stage  1616 , a detector stage  1618 , and a pooling stage  1620 . The convolution layer  1614  can then output data to a successive convolutional layer. The final convolutional layer of the network can generate output feature map data or provide input to a fully connected layer, for example, to generate a classification value for the input to the CNN. 
     In the convolution stage  1616  performs several convolutions in parallel to produce a set of linear activations. The convolution stage  1616  can include an affine transformation, which is any transformation that can be specified as a linear transformation plus a translation. Affine transformations include rotations, translations, scaling, and combinations of these transformations. The convolution stage computes the output of functions (e.g., neurons) that are connected to specific regions in the input, which can be determined as the local region associated with the neuron. The neurons compute a dot product between the weights of the neurons and the region in the local input to which the neurons are connected. The output from the convolution stage  1616  defines a set of linear activations that are processed by successive stages of the convolutional layer  1614 . 
     The linear activations can be processed by a detector stage  1618 . In the detector stage  1618 , each linear activation is processed by a non-linear activation function. The non-linear activation function increases the nonlinear properties of the overall network without affecting the receptive fields of the convolution layer. Several types of non-linear activation functions may be used. One particular type is the rectified linear unit (ReLU), which uses an activation function defined as ƒ(x)=max(0, x), such that the activation is thresholded at zero. 
     The pooling stage  1620  uses a pooling function that replaces the output of the second convolutional layer  1606  with a summary statistic of the nearby outputs. The pooling function can be used to introduce translation invariance into the neural network, such that small translations to the input do not change the pooled outputs. Invariance to local translation can be useful in scenarios where the presence of a feature in the input data is more important than the precise location of the feature. Various types of pooling functions can be used during the pooling stage  1620 , including max pooling, average pooling, and 12-norm pooling. Additionally, some CNN implementations do not include a pooling stage. Instead, such implementations substitute and additional convolution stage having an increased stride relative to previous convolution stages. 
     The output from the convolutional layer  1614  can then be processed by the next layer  1622 . The next layer  1622  can be an additional convolutional layer or one of the fully connected layers  1608 . For example, the first convolutional layer  1604  of  FIG. 16A  can output to the second convolutional layer  1606 , while the second convolutional layer can output to a first layer of the fully connected layers  1608 . 
       FIG. 17  illustrates an exemplary recurrent neural network. In a recurrent neural network (RNN), the previous state of the network influences the output of the current state of the network. RNNs can be built in a variety of ways using a variety of functions. The use of RNNs generally revolves around using mathematical models to predict the future based on a prior sequence of inputs. For example, an RNN may be used to perform statistical language modeling to predict an upcoming word given a previous sequence of words. The illustrated RNN  1700  can be described as having an input layer  1702  that receives an input vector, hidden layers  1704  to implement a recurrent function, a feedback mechanism  1705  to enable a ‘memory’ of previous states, and an output layer  1706  to output a result. The RNN  1700  operates based on time-steps. The state of the RNN at a given time step is influenced based on the previous time step via the feedback mechanism  1705 . For a given time step, the state of the hidden layers  1704  is defined by the previous state and the input at the current time step. An initial input (x 1 ) at a first time step can be processed by the hidden layer  1704 . A second input (x 2 ) can be processed by the hidden layer  1704  using state information that is determined during the processing of the initial input (x 1 ). A given state can be computed as s t =ƒ(Ux t +Ws t-1 ), where U and W are parameter matrices. The function ƒ is generally a nonlinearity, such as the hyperbolic tangent function (Tan h) or a variant of the rectifier function ƒ(x)=max(0, x). However, the specific mathematical function used in the hidden layers  1704  can vary depending on the specific implementation details of the RNN  1700 . 
     In addition to the basic CNN and RNN networks described, variations on those networks may be enabled. One example RNN variant is the long short-term memory (LSTM) RNN. LSTM RNNs are capable of learning long-term dependencies that may be necessary for processing longer sequences of language. A variant on the CNN is a convolutional deep belief network, which has a structure similar to a CNN and is trained in a manner similar to a deep belief network. A deep belief network (DBN) is a generative neural network that is composed of multiple layers of stochastic (random) variables. DBNs can be trained layer-by-layer using greedy unsupervised learning. The learned weights of the DBN can then be used to provide pre-train neural networks by determining an optimal initial set of weights for the neural network. 
       FIG. 18  illustrates training and deployment of a deep neural network. Once a given network has been structured for a task the neural network is trained using a training dataset  1802 . Various training frameworks have been developed to enable hardware acceleration of the training process. For example, the machine learning framework  1504  of  FIG. 15  may be configured as a training framework  1804 . The training framework  1804  can hook into an untrained neural network  1806  and enable the untrained neural net to be trained using the parallel processing resources described herein to generate a trained neural network  1808 . To start the training process the initial weights may be chosen randomly or by pre-training using a deep belief network. The training cycle then be performed in either a supervised or unsupervised manner. 
     Supervised learning is a learning method in which training is performed as a mediated operation, such as when the training dataset  1802  includes input paired with the desired output for the input, or where the training dataset includes input having known output and the output of the neural network is manually graded. The network processes the inputs and compares the resulting outputs against a set of expected or desired outputs. Errors are then propagated back through the system. The training framework  1804  can adjust to adjust the weights that control the untrained neural network  1806 . The training framework  1804  can provide tools to monitor how well the untrained neural network  1806  is converging towards a model suitable to generating correct answers based on known input data. The training process occurs repeatedly as the weights of the network are adjusted to refine the output generated by the neural network. The training process can continue until the neural network reaches a statistically desired accuracy associated with a trained neural network  1808 . The trained neural network  1808  can then be deployed to implement any number of machine learning operations. 
     Unsupervised learning is a learning method in which the network attempts to train itself using unlabeled data. Thus, for unsupervised learning the training dataset  1802  will include input data without any associated output data. The untrained neural network  1806  can learn groupings within the unlabeled input and can determine how individual inputs are related to the overall dataset. Unsupervised training can be used to generate a self-organizing map, which is a type of trained neural network  1807  capable of performing operations useful in reducing the dimensionality of data. Unsupervised training can also be used to perform anomaly detection, which allows the identification of data points in an input dataset that deviate from the normal patterns of the data. 
     Variations on supervised and unsupervised training may also be employed. Semi-supervised learning is a technique in which in the training dataset  1802  includes a mix of labeled and unlabeled data of the same distribution. Incremental learning is a variant of supervised learning in which input data is continuously used to further train the model. Incremental learning enables the trained neural network  1808  to adapt to the new data  1812  without forgetting the knowledge instilled within the network during initial training. 
     Whether supervised or unsupervised, the training process for particularly deep neural networks may be too computationally intensive for a single compute node. Instead of using a single compute node, a distributed network of computational nodes can be used to accelerate the training process. 
       FIG. 19  is a block diagram illustrating distributed learning. Distributed learning is a training model that uses multiple distributed computing nodes to perform supervised or unsupervised training of a neural network. The distributed computational nodes can each include one or more host processors and one or more of the general-purpose processing nodes. As illustrated, distributed learning can be performed model parallelism  1902 , data parallelism  1904 , or a combination of model and data parallelism  1904 . 
     In model parallelism  1902 , different computational nodes in a distributed system can perform training computations for different parts of a single network. For example, each layer of a neural network can be trained by a different processing node of the distributed system. The benefits of model parallelism include the ability to scale to particularly large models. Splitting the computations associated with different layers of the neural network enables the training of very large neural networks in which the weights of all layers would not fit into the memory of a single computational node. In some instances, model parallelism can be particularly useful in performing unsupervised training of large neural networks. 
     In data parallelism  1904 , the different nodes of the distributed network have a complete instance of the model and each node receives a different portion of the data. The results from the different nodes are then combined. While different approaches to data parallelism are possible, data parallel training approaches all require a technique of combining results and synchronizing the model parameters between each node. Exemplary approaches to combining data include parameter averaging and update based data parallelism. Parameter averaging trains each node on a subset of the training data and sets the global parameters (e.g., weights, biases) to the average of the parameters from each node. Parameter averaging uses a central parameter server that maintains the parameter data. Update based data parallelism is similar to parameter averaging except that instead of transferring parameters from the nodes to the parameter server, the updates to the model are transferred. Additionally, update based data parallelism can be performed in a decentralized manner, where the updates are compressed and transferred between nodes. 
     Combined model and data parallelism  1906  can be implemented, for example, in a distributed system in which each computational node includes multiple GPUs. Each node can have a complete instance of the model with separate GPUs within each node are used to train different portions of the model. 
     Distributed training has increased overhead relative to training on a single machine. However, the parallel processors and GPGPUs described herein can each implement various techniques to reduce the overhead of distributed training, including techniques to enable high bandwidth GPU-to-GPU data transfer and accelerated remote data synchronization. 
     Exemplary Machine Learning Applications 
     Machine learning can be applied to solve a variety of technological problems, including but not limited to computer vision, autonomous driving and navigation, speech recognition, and language processing. Computer vision has traditionally been one of the most active research areas for machine learning applications. Applications of computer vision range from reproducing human visual abilities, such as recognizing faces, to creating new categories of visual abilities. For example, computer vision applications can be configured to recognize sound waves from the vibrations induced in objects visible in a video. Parallel processor accelerated machine learning enables computer vision applications to be trained using significantly larger training dataset than previously feasible and enables inferencing systems to be deployed using low power parallel processors. 
     Parallel processor accelerated machine learning has autonomous driving applications including lane and road sign recognition, obstacle avoidance, navigation, and driving control. Accelerated machine learning techniques can be used to train driving models based on datasets that define the appropriate responses to specific training input. The parallel processors described herein can enable rapid training of the increasingly complex neural networks used for autonomous driving solutions and enables the deployment of low power inferencing processors in a mobile platform suitable for integration into autonomous vehicles. 
     Parallel processor accelerated deep neural networks have enabled machine learning approaches to automatic speech recognition (ASR). ASR includes the creation of a function that computes the most probable linguistic sequence given an input acoustic sequence. Accelerated machine learning using deep neural networks have enabled the replacement of the hidden Markov models (HMMs) and Gaussian mixture models (GMMs) previously used for ASR. 
     Parallel processor accelerated machine learning can also be used to accelerate natural language processing. Automatic learning procedures can make use of statistical inference algorithms to produce models that are robust to erroneous or unfamiliar input. Exemplary natural language processor applications include automatic machine translation between human languages. 
     The parallel processing platforms used for machine learning can be divided into training platforms and deployment platforms. Training platforms are generally highly parallel and include optimizations to accelerate multi-GPU single node training and multi-node, multi-GPU training, while deployed machine learning (e.g., inferencing) platforms generally include lower power parallel processors suitable for use in products such as cameras, autonomous robots, and autonomous vehicles. 
       FIG. 20  illustrates one embodiment of a computing device  2000  employing an accelerator mechanism. Computing device  2000  (e.g., smart wearable devices, virtual reality (VR) devices, head-mounted display (HMDs), mobile computers, Internet of Things (IoT) devices, laptop computers, desktop computers, server computers, etc.) may be the same as data processing system  100  of  FIG. 1  and accordingly, for brevity, clarity, and ease of understanding, many of the details stated above with reference to  FIGS. 1-19  are not further discussed or repeated hereafter. As illustrated, in one embodiment, computing device  2000  is shown as hosting an accelerator  2010 . 
     Although illustrated as a separate component, other embodiments may feature accelerator  2010  being hosted by graphics processing unit (GPU)  2014 . In other embodiments, accelerator  2010  may be hosted by or part of firmware of central processing unit (“CPU” or “application processor”)  2012 . For brevity, clarity, and ease of understanding, throughout the rest of this document, accelerator  2010  may be discussed as a separate component; however, embodiments are not limited as such. 
     In yet another embodiment, accelerator mechanism  2010  may be partially and simultaneously hosted by multiple components of computing device  2000 , such as one or more of graphics driver  616 , GPU  2014 , GPU firmware, CPU  2012 , CPU firmware, operating system  2006 , and/or the like. It is contemplated that accelerator  2010  or one or more of their components may be implemented as hardware, software, and/or firmware. 
     Throughout the document, terms like “graphics domain” may be referenced interchangeably with “graphics processing unit”, “graphics processor”, or simply “GPU” and similarly, “CPU domain” or “host domain” may be referenced interchangeably with “computer processing unit”, “application processor”, or simply “CPU”. 
     Computing device  2000  may include any number and type of communication devices, such as large computing systems, such as server computers, desktop computers, etc., and may further include set-top boxes (e.g., Internet-based cable television set-top boxes, etc.), global positioning system (GPS)-based devices, etc. Computing device  2000  may include mobile computing devices serving as communication devices, such as cellular phones including smartphones, personal digital assistants (PDAs), tablet computers, laptop computers, e-readers, smart televisions, television platforms, wearable devices (e.g., glasses, watches, bracelets, smartcards, jewelry, clothing items, etc.), media players, etc. For example, in one embodiment, computing device  2000  may include a mobile computing device employing a computer platform hosting an integrated circuit (“IC”), such as system on a chip (“SoC” or “SOC”), integrating various hardware and/or software components of computing device  2000  on a single chip. 
     As illustrated, in one embodiment, computing device  2000  may include any number and type of hardware and/or software components, such as (without limitation) GPU  2014 , graphics driver (also referred to as “GPU driver”, “graphics driver logic”, “driver logic”, user-mode driver (UMD), UMD, user-mode driver framework (UMDF), UMDF, or simply “driver”)  616 , CPU  2012 , memory  2008 , network devices, drivers, or the like, as well as input/output (I/O) sources  2004 , such as touchscreens, touch panels, touch pads, virtual or regular keyboards, virtual or regular mice, ports, connectors, etc. 
     Computing device  2000  may include operating system (OS)  2006  serving as an interface between hardware and/or physical resources of the computer device  2000  and a user. It is contemplated that CPU  2012  may include one or more processors, such as processor(s)  102  of  FIG. 1 , while GPU  2014  may include one or more graphics processors (or multiprocessors). 
     It is to be noted that terms like “node”, “computing node”, “server”, “server device”, “cloud computer”, “cloud server”, “cloud server computer”, “machine”, “host machine”, “device”, “computing device”, “computer”, “computing system”, and the like, may be used interchangeably throughout this document. It is to be further noted that terms like “application”, “software application”, “program”, “software program”, “package”, “software package”, and the like, may be used interchangeably throughout this document. Also, terms like “job”, “input”, “request”, “message”, and the like, may be used interchangeably throughout this document. 
     It is contemplated and as further described with reference to  FIGS. 1-14 , some processes of the graphics pipeline as described above are implemented in software, while the rest are implemented in hardware. A graphics pipeline may be implemented in a graphics coprocessor design, where CPU  2012  is designed to work with GPU  2014  which may be included in or co-located with CPU  2012 . In one embodiment, GPU  2014  may employ any number and type of conventional software and hardware logic to perform the conventional functions relating to graphics rendering as well as novel software and hardware logic to execute any number and type of instructions. 
     As aforementioned, memory  2008  may include a random access memory (RAM) comprising application database having object information. A memory controller hub, such as memory hub  105  of  FIG. 1 , may access data in the RAM and forward it to GPU  2014  for graphics pipeline processing. RAM may include double data rate RAM (DDR RAM), extended data output RAM (EDO RAM), etc. CPU  2012  interacts with a hardware graphics pipeline to share graphics pipelining functionality. 
     Processed data is stored in a buffer in the hardware graphics pipeline, and state information is stored in memory  2008 . The resulting image is then transferred to I/O sources  2004 , such as a display component for displaying of the image. It is contemplated that the display device may be of various types, such as Cathode Ray Tube (CRT), Thin Film Transistor (TFT), Liquid Crystal Display (LCD), Organic Light Emitting Diode (OLED) array, etc., to display information to a user. 
     Memory  2008  may comprise a pre-allocated region of a buffer (e.g., frame buffer); however, it should be understood by one of ordinary skill in the art that the embodiments are not so limited, and that any memory accessible to the lower graphics pipeline may be used. Computing device  2000  may further include input/output (I/O) control hub (ICH)  107  as referenced in  FIG. 1 , as one or more I/O sources  2004 , etc. 
     CPU  2012  may include one or more processors to execute instructions in order to perform whatever software routines the computing system implements. The instructions frequently involve some sort of operation performed upon data. Both data and instructions may be stored in system memory  2008  and any associated cache. Cache is typically designed to have shorter latency times than system memory  2008 ; for example, cache might be integrated onto the same silicon chip(s) as the processor(s) and/or constructed with faster static RAM (SRAM) cells whilst the system memory  2008  might be constructed with slower dynamic RAM (DRAM) cells. By tending to store more frequently used instructions and data in the cache as opposed to the system memory  2008 , the overall performance efficiency of computing device  2000  improves. It is contemplated that in some embodiments, GPU  2014  may exist as part of CPU  2012  (such as part of a physical CPU package) in which case, memory  2008  may be shared by CPU  2012  and GPU  2014  or kept separated. 
     System memory  2008  may be made available to other components within the computing device  2000 . For example, any data (e.g., input graphics data) received from various interfaces to the computing device  2000  (e.g., keyboard and mouse, printer port, Local Area Network (LAN) port, modem port, etc.) or retrieved from an internal storage element of the computer device  2000  (e.g., hard disk drive) are often temporarily queued into system memory  2008  prior to being operated upon by the one or more processor(s) in the implementation of a software program. Similarly, data that a software program determines should be sent from the computing device  2000  to an outside entity through one of the computing system interfaces, or stored into an internal storage element, is often temporarily queued in system memory  2008  prior to its being transmitted or stored. 
     Further, for example, an ICH may be used for ensuring that such data is properly passed between the system memory  2008  and its appropriate corresponding computing system interface (and internal storage device if the computing system is so designed) and may have bi-directional point-to-point links between itself and the observed  110  sources/devices  2004 . Similarly, platform control hub (PCH) may be used for managing the various contending requests for system memory  2008  accesses amongst CPU  2012  and GPU  2014 , interfaces and internal storage elements that may proximately arise in time with respect to one another. 
     I/O sources  2004  may include one or more I/O devices that are implemented for transferring data to and/or from computing device  2000  (e.g., a networking adapter); or, for a large scale non-volatile storage within computing device  2000  (e.g., hard disk drive). User input device, including alphanumeric and other keys, may be used to communicate information and command selections to GPU  2014 . Another type of user input device is cursor control, such as a mouse, a trackball, a touchscreen, a touchpad, or cursor direction keys to communicate direction information and command selections to GPU  2014  and to control cursor movement on the display device. Camera and microphone arrays of computer device  2000  may be employed to observe gestures, record audio and video and to receive and transmit visual and audio commands. 
     Computing device  2000  may further include network interface(s) to provide access to a network, such as a LAN, a wide area network (WAN), a metropolitan area network (MAN), a personal area network (PAN), Bluetooth, a cloud network, a mobile network (e.g., 3rd Generation (3G), 4th Generation (4G), etc.), an intranet, the Internet, etc. Network interface(s) may include, for example, a wireless network interface having antenna, which may represent one or more antenna(e). Network interface(s) may also include, for example, a wired network interface to communicate with remote devices via network cable, which may be, for example, an Ethernet cable, a coaxial cable, a fiber optic cable, a serial cable, or a parallel cable. 
     Network interface(s) may provide access to a LAN, for example, by conforming to IEEE 802.11b and/or IEEE 802.11g standards, and/or the wireless network interface may provide access to a personal area network, for example, by conforming to Bluetooth standards. Other wireless network interfaces and/or protocols, including previous and subsequent versions of the standards, may also be supported. In addition to, or instead of, communication via the wireless LAN standards, network interface(s) may provide wireless communication using, for example, Time Division, Multiple Access (TDMA) protocols, Global Systems for Mobile Communications (GSM) protocols, Code Division, Multiple Access (CDMA) protocols, and/or any other type of wireless communications protocols. 
     Network interface(s) may include one or more communication interfaces, such as a modem, a network interface card, or other well-known interface devices, such as those used for coupling to the Ethernet, token ring, or other types of physical wired or wireless attachments for purposes of providing a communication link to support a LAN or a WAN, for example. In this manner, the computer system may also be coupled to a number of peripheral devices, clients, control surfaces, consoles, or servers via a conventional network infrastructure, including an Intranet or the Internet, for example. 
     It is to be appreciated that a lesser or more equipped system than the example described above may be preferred for certain implementations. Therefore, the configuration of computing device  2000  may vary from implementation to implementation depending upon numerous factors, such as price constraints, performance requirements, technological improvements, or other circumstances. Examples of the electronic device or computer system  2000  may include (without limitation) a mobile device, a personal digital assistant, a mobile computing device, a smartphone, a cellular telephone, a handset, a one-way pager, a two-way pager, a messaging device, a computer, a personal computer (PC), a desktop computer, a laptop computer, a notebook computer, a handheld computer, a tablet computer, a server, a server array or server farm, a web server, a network server, an Internet server, a work station, a mini-computer, a main frame computer, a supercomputer, a network appliance, a web appliance, a distributed computing system, multiprocessor systems, processor-based systems, consumer electronics, programmable consumer electronics, television, digital television, set top box, wireless access point, base station, subscriber station, mobile subscriber center, radio network controller, router, hub, gateway, bridge, switch, machine, or combinations thereof. 
     Embodiments may be implemented as any or a combination of: one or more microchips or integrated circuits interconnected using a parentboard, hardwired logic, software stored by a memory device and executed by a microprocessor, firmware, an application specific integrated circuit (ASIC), and/or a field programmable gate array (FPGA). The term “logic” may include, by way of example, software or hardware and/or combinations of software and hardware. 
     Embodiments may be provided, for example, as a computer program product which may include one or more machine-readable media having stored thereon machine-executable instructions that, when executed by one or more machines such as a computer, network of computers, or other electronic devices, may result in the one or more machines carrying out operations in accordance with embodiments described herein. A machine-readable medium may include, but is not limited to, floppy diskettes, optical disks, CD-ROMs (Compact Disc-Read Only Memories), and magneto-optical disks, ROMs, RAMs, EPROMs (Erasable Programmable Read Only Memories), EEPROMs (Electrically Erasable Programmable Read Only Memories), magnetic or optical cards, flash memory, or other type of media/machine-readable medium suitable for storing machine-executable instructions. 
     Moreover, embodiments may be downloaded as a computer program product, wherein the program may be transferred from a remote computer (e.g., a server) to a requesting computer (e.g., a client) by way of one or more data signals embodied in and/or modulated by a carrier wave or other propagation medium via a communication link (e.g., a modem and/or network connection). 
     As discussed above, there has been an effort to move deep learning based inference into lower precision to achieve higher compute efficiencies, thus enabling such capabilities on power-constrained hardware platforms. However, floating point real numbers must first be converted to the lower precision via one of a variety of different quantization schemes. Tensorflow® developed by Google® performs one such quantization scheme. 
     Tensorflow® is an open source machine learning software library, which supports a low precision quantization mode referred to as LOWP. LOWP transforms higher precision inputs into an unsigned 8 bit input data range through scaling and offset-addition operations. For instance, the LOWP quantization operation changes a dynamic range of 32 bit floating point (FP32) inputs to an 8 bit unsigned integer range of 0→255. For floating point inputs ranging from min x  to max x , an input x f  may be transformed into low precision input x q  as follows: 
     
       
         
           
             
               
                 
                   
                     
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     The first term (T1) of equation 6 for both CNN/GEMM is a traditional matrix multiplication compute performed on the 8 bit quantized input. The T1 compute is an 8-bit compute having an output of 32-bit accumulated values. Such matrix multiplication operations are accelerated through specialized hardware in several state of the art deep-learning solutions. However the final output requires another two terms, which are T2 and T3 and a constant addition (T4). 
     The T2 term computation involves a sum of elements of weights and multiply with offset(x) (e.g., t3_offset), while the T3 computation involves a sum of elements of input and multiply with offset(w) (t2_offset). T4 is a global constant that is added to each element of result. Tm is a modified bias with T4 and offsety (output offset). There is currently no hardware acceleration architecture to compute these terms. The current hardware solutions accelerate the matrix multiplication compute, but do not address the additional terms T2, T3, T4 as described earlier. These solutions compute the T2, T3, T4 terms in software through multiple pass-through of the data. 
     According to one embodiment, accelerator  2010  provides a hardware architecture that optimally implements GEMM/CNN operations on low precision quantized data in a single pass. In such an embodiment, accelerator  2010  calculates terms inline in a single pass (e.g., in parallel) with the T1 matrix multiplication operations, which enables calculation of final pixel values of the layer within accelerator  2010 . Thus, multiple passes through the data are avoided. Moreover, accelerator  2010  enables the fusion of next layers like ReLU or max-pooling within the same pass, thereby reducing the required data fetches/stores from/to system memory. In such an embodiment, accelerator  2010  may replace a quantized Re-Lu operation with an un-quantized ReLU on 32 bit data. 
       FIG. 21  illustrates one embodiment of an accelerator  2010 . As shown in  FIG. 21 , accelerator  2010  includes a compute grid having an array of tiles  2100  (e.g.,  2100 ( a )-( n )) coupled to input memory  2120 . In one embodiment, each tile  2100  includes processing elements  2105  (e.g.,  2105 ( a )-( n )) to perform computations. Additionally, each tile  2100  includes weight buffers  2108  and an output memory  2110 . According to one embodiment, two broadcasted inputs (e.g., operand1 and operand2) are received for both CNN and GEMM. In such an embodiment, PEs  2105  share input operand1, while tiles  2100  share operand2. This broadcast of inputs allows minimum data movement with N 2  compute operations to be performed per every 2N elements that are fetched, where N is the size of the compute grid in X or Y direction. 
     According to one embodiment, accelerator  2010  provides one or more tiles that are dedicated to perform inline computations of terms T2 and T3 from equation 3 (shown above), which provide the scaled values of a running sum of the two operands being multiplied and accumulated together.  FIG. 22  illustrates another embodiment of an accelerator  2200  for performing GEMM/CNN operations on low precision quantized data in a single pass. As shown in  FIG. 22 , accelerator  2200  includes T1, T2 and T3 compute elements  2205 ,  2210  and  2215 , respectively. According to some embodiments, elements  2205 ,  2210  and  2215  may be implemented with PEs  2105  on separate tiles  2100 . However, other embodiments may implement one or more of elements  2205 ,  2210  and  2215  on the same tile  2100 . 
     Accelerator  2200  also includes weights buffer  2220  and input buffer  2225 . According to one embodiment, buffer  2225  is implemented to store partial sums, while final T2 and T3 terms are computed via a single multiplication operation performed at the end. In a further embodiment, the T2 and T3 computations are forwarded back to the main T1 compute elements, keeping computationally costly memory reads and multiplication operations at a minimum. As a result, T1+T2+T3+Tm is computed by T1 compute elements  2205 . As discussed above, Tm is a modified bias with T4 and offsety (output offset). Accordingly, the result of T1+T2+T3+Tm is an accumulator 32-bit value. In a further embodiment, this 32-bit data is quantized by multiplying with an integer and right shifting by an integer value. 
       FIG. 23  is a flow diagram illustrating one embodiment of a process for performing a CNN/GEMM operation at accelerator  2010 . At processing block  2310 , the constant T4 is preloaded. At processing block  2315 , a CNN/GEMM matrix multiplication operation is performed at T1 compute elements  2205 . At processing block  2320 , T2 is computed at T2 compute elements  2210  in parallel with the T1 computation. For the T2 computation, the CNN computation is associated with kernels, while the GEMM computation is associated with a running sum of elements of a row in an A matrix. In both instances the T2 computation is mapped to input operand  1  of the accelerator  2010  compute grid. 
     In one embodiment, the operand1 is broadcast to an accumulator that calculates a running sum, in addition to all PEs  2105  in a tile. Thus, T2 may be calculated in two phases. At processing block  2324 , the T2 running sum (e.g., sum of all elements in a kernel across all the zdepth or sum of all elements of a row of A) is computed. At processing block  2326 , the T2 running sum is multiplied with an offset from T3 (t3_offset), which completes the T2 computation. 
     At processing block  2330 , the T3 term is computed at T3 compute elements  2215  in parallel with the T1 and T2 computations. In one embodiment, the T3 term is calculated from input feature maps (IFMs) in CNN embodiments, and elements of a B column in GEMM embodiments. As in the case of T2, the operand2 being broadcast to all accelerator  2010  tiles is also input to a running sum accumulator at T3 compute elements  2215 . Thus at processing block  2334 , the T3 running sum (e.g., of all the elements in a K×K box of IFM across all the zdepth of IFMs or sum of all elements in a column of B matrix sum) is calculated. At processing block  2336 , the T3 running sum is multiplied with an offset from T2 (t2_offset) to complete the T3computation. According to one embodiment, the constant term T4 is added as part of bias and is preloaded in the accumulator of each processing element. As a result, a final unquantized output is computed. In one embodiment, the final unquantized 32 bit value is the accumulated value of the four computed terms. 
     At processing block  2350 , post processing is performed, including the quantization of the final output. As shown in  FIG. 22 , tile  2200  includes a post processor circuit  2250 . Post processor circuit  2250  operates on the output data to perform operations rectified linear unit (ReLU) operations, as well as other post-processing. As a result, software intervention between various layers of a deep learning workload may be completely eliminated. 
     A typical neural network topology includes different layers, in which a CNN layer is most often followed by ReLU to introduce non-linearity. A ReLU operation is defined as Y=0, x&lt;0; and Y=x, X&gt;0. In the case of quantized inputs, ReLu may be replaced with a more costly quantized-ReLU operation, which is computationally costlier (Y=x, for X&gt;offset), and more importantly needs offline software run through the data to calculate the min value/offset. According to one embodiment, post processor circuit  2250  reverses the order of the layers, so that the original ReLu is performed on unquantized data. In such an embodiment, the unquantized ReLu simply zeros out negative values, and does not require any knowledge of a minimum value or range. Thus, the ReLu output is naturally positive, aiding in the post quantization of the output. This switch in the order of operations enables a fused CNN+ReLu+post-quantization within accelerator  2010 . 
     The foregoing description and drawings are to be regarded in an illustrative rather than a restrictive sense. Persons skilled in the art will understand that various modifications and changes may be made to the embodiments described herein without departing from the broader spirit and scope of the invention as set forth in the appended claims. 
     Some embodiments pertain to Example 1 that includes an apparatus to facilitate acceleration of machine learning operations, comprising accelerator circuitry, including a first set of processing elements to perform first computations including matrix multiplication operations, a second set of processing elements to perform second computations including sum of elements of weights and offset multiply operations and a third set of processing elements to perform third computations including sum of elements of inputs and offset multiply operations, wherein the second and third computations are performed in parallel with the first computations. 
     Example 2 includes the subject matter of Example 1, further comprising a weights buffer coupled to the second set of processing elements to provide weight values to the second set of processing elements. 
     Example 3 includes the subject matter of Examples 1 and 2, further comprising an input buffer coupled to the third set of processing elements to provide input values to the third set of processing elements. 
     Example 4 includes the subject matter of Examples 1-3, wherein results of the second and third computations are transmitted to the first set of processing elements. 
     Example 5 includes the subject matter of Examples 1-4, wherein the first set of processing elements computes a final result based on the results of the first, second and third computations and a constant value. 
     Example 6 includes the subject matter of Examples 1-5, wherein the post processor circuitry further to perform a quantization operation on the final result. 
     Example 7 includes the subject matter of Examples 1-6, further comprising post processor circuitry to perform one or more machine learning layer operations on the final result received from the first set of processing elements. 
     Example 8 includes the subject matter of Examples 1-7, wherein the one or more machine learning layer operations comprises rectified linear unit (ReLU) operations. 
     Example 9 includes the subject matter of Examples 1-8, wherein the ReLU operations are fused with the final result. 
     Some embodiments pertain to Example 10 that includes a method to facilitate acceleration of machine learning operations, comprising performing first computations including matrix multiplication operations at a first set of processing elements, performing second computations including sum of elements of weights and offset multiply operations at a second set of processing elements and performing third computations including sum of elements of inputs and offset multiply operations at a third set of processing elements, wherein the second and third computations are performed in parallel with the first computations. 
     Example 11 includes the subject matter of Example 10, further comprising receiving weight values at the second set of processing elements prior to performing the second computations. 
     Example 12 includes the subject matter of Examples 10 and 11, further comprising receiving input values at the third set of processing elements prior to performing the third computations. 
     Example 13 includes the subject matter of Examples 10-12, further comprising receiving results of the second and third computations at the first set of processing elements. 
     Example 14 includes the subject matter of Examples 10-13, further comprising computing a final result at the first set of processing elements based on the results of the first, second and third computations and a constant value. 
     Example 15 includes the subject matter of Examples 10-14, further comprising performing a quantization operation on the final result at the first set of processing elements. 
     Example 16 includes the subject matter of Examples 10-15, further comprising performing one or more machine learning layer operations on the final result received from the first set of processing elements. 
     Example 17 includes the subject matter of Examples 10-16, wherein the one or more machine learning layer operations comprises rectified linear unit (ReLU) operations. 
     Example 18 includes the subject matter of Examples 10-17, further comprising fusing the ReLU operations with the final result. 
     Some embodiments pertain to Example 19 that includes an accelerator comprising a plurality of tiles comprising a plurality of processing elements, including a first tile having a first set of processing elements to perform first computations including matrix multiplication operations, a second tile having a second set of processing elements to perform second computations including sum of elements of weights and offset multiply operations and a third set of processing elements to perform third computations including sum of elements of inputs and offset multiply operations, wherein the second and third computations are performed in parallel with the first computations. 
     Example 20 includes the subject matter of Example 19, wherein the second tile further comprises a weights buffer coupled to the second set of processing elements to provide weight values to the second set of processing elements and an input buffer coupled to the third set of processing elements to provide input values to the third set of processing elements. 
     Example 21 includes the subject matter of Examples 19 and 20, wherein results of the second and third computations are transmitted to the first set of processing elements, and wherein the first set of processing elements computes a final result based on the results of the first, second and third computations and a constant value. 
     Example 22 includes the subject matter of Examples 19-21, further comprising post processor circuitry to perform one or more machine learning layer operations on the final result received from the first set of processing elements. 
     The foregoing description and drawings are to be regarded in an illustrative rather than a restrictive sense. Persons skilled in the art will understand that various modifications and changes may be made to the embodiments described herein without departing from the broader spirit and scope of the invention as set forth in the appended claims.