Patent Publication Number: US-7221341-B2

Title: Display apparatus driving method using a current signal

Description:
This is a divisional application of application Ser. No. 10/650,776, filed on Aug. 29, 2003, now allowed. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a current signal output circuit for outputting a current signal. Further, the invention relates to a display apparatus using the current signal output circuit. 
     2. Related Background Art 
     Various display apparatus have been known as background arts. As an example of the display apparatus, there is a display apparatus using an electroluminescence element. The example is described in U.S. Pat. No. 6,373,454. 
     OBJECT AND SUMMARY OF THE INVENTION 
     The inventor of the application has investigated various constitutions as constitutions of display apparatus. 
     An explanation will be given of a constitution which has been investigated as a display apparatus using an electroluminescence element as follows. 
     An electroluminescence (EL) element is applied to a panel type image display system (hereinafter, referred to as EL panel) in which pixel display circuits generally constituted by TFTs are aligned two-dimensionally. As luminescence setting systems of the EL element, a voltage setting system and a current setting system can be pointed out. 
     &lt;EL Panel By Voltage Setting System&gt; 
       FIG. 12  shows a circuit constitution of a colored EL panel by a voltage setting system. 
     An input image signal  10  is pertinently inputted to column control circuits  22  provided by a number three times as much as a horizontal pixel number of an EL panel provided for each color of red, green and blue (RGB). Further, a horizontal scanning control signal  11   a  is inputted to an input circuit  6  to output a horizontal scanning control signal  11  and the horizontal control scanning control signal  11  is inputted to a horizontal shift register  3  comprising registers of the horizontal pixel number. The horizontal scanning control signal  11  comprises a horizontal clock signal and a horizontal scanning start signal. Further, a horizontal sampling signal group  17  outputted from respective terminals of the horizontal shift register  3  is inputted to the respectively assigned column control circuits  22 . 
     As shown in  FIG. 14 , the constitution of the column control circuit  22  is constructed by a very simple constitution in which a horizontal sampling signal SP is connected to M 100 /G, an input image signal video (here, one of RGB) is connected to M 100 /S and an image voltage data v (data) which is a column control signal  14  is outputted from M 100 /D. 
     Further, in the specification, for convenience of explanation, a gate electrode, a source electrode and a drain electrode of the transistor are respectively designated by abbreviated notations of /G, /S and /D and a signal and a signal line for supplying the signal are expressed without being differentiated from each other. 
     At an image display region  9 , pixel circuits  2  respectively having equivalent constitutions are arranged two-dimensionally and respectively assigned to drive EL display elements of RGB and display of one pixel is assigned to a set of three pieces of the pixel circuits  2 . 
     Image voltage data v (data) outputted from the column control circuit  22  is inputted to a group of the pixel circuits  2  arranged on the same column. Further, a vertical scanning control signal  12   a  outputs a vertical scanning control signal  12  via an input circuit  7  and the vertical scanning control signal  12  is inputted to a vertical shift register  5  including registers of a number equal to a vertical pixel number of the EL panel. The vertical scanning control signal  12  consists of a vertical clock signal and a vertical scanning control signal. Further, a row control signal  20  outputted from each of output terminals of the vertical shift register is inputted to the pixel circuits  2  arranged on the same row. 
     (Pixel Circuit of Voltage Setting System) 
       FIG. 13  shows a constitution of the pixel circuit  2  of the voltage setting system. 
     The voltage data v (data) is connected to M 300 /S. Further, the row control signals  20  correspond to P 13 , P 14  and P 15  and respectively connected to M 300 /G, M 200 /G and M 400 /G. M 300 /D is connected to a capacitor C 200  and the capacitor C 200  is connected to M 100 /G the source of which is connected to a power source and a capacitor C 100 . Further, M 100 /D and M 100 /G are respectively connected to M 200 /D and M 200 /S, M 100 /D is connected to M 400 /S, and M 400 /D is connected to a current injecting terminal of an EL element one end of which is grounded. 
     Next, an explanation will be given of operation of the EL panel of  FIG. 12  in reference to time charts of  FIGS. 15A ,  15 B,  15 C,  15 D and  15 E.  FIG. 15A  indicates the input image signal video,  FIG. 15B  indicates a horizontal sampling signal SP and  FIGS. 15C ,  15 D and  15 E indicate row control signals P 13  through P 15  of a corresponding row. Further,  FIGS. 15A ,  15 B,  15 C,  15 D and  15 E indicate three horizontal periods, that is, three row periods. 
     First, at time t 1  through t 2  in a horizontal blanking period of the input image signal, each horizontal sampling pulse SP is simultaneously changed to H level and at this occasion, blanking voltage which is the input image signal is made to constitute the column control signal  14 . Further, in SP of  FIG. 15B , the horizontal sample signal of the corresponding row is designated by a bold line. 
     ♦Before time t 5  (luminescence holding period) 
     At time t 1  through t 5 , the row control signals P 13  through P 15  of the pixel circuit  2  of the corresponding row are respectively brought into H level, H level and L level and even when each horizontal sampling pulse SP is simultaneously changed to H level at time t 1  through t 2 , M 200 , M 300  and M 400  of the pixel circuit  2  respectively stay to be OFF, OFF and ON an therefore, drain current of M 100  determined by the capacitor C 100  and voltage of M 100 /G of the pixel circuit  2  which is hold voltage of the gate capacitance is injected to the EL element and luminescence is continued. Further, at time t 1  through t 2  during the horizontal blanking period, voltage of the input image signal video is voltage Vb 1  at a vicinity of a black level as shown in  FIG. 15A . 
     ♦Time t 5  through t 9  (luminescence setting period) 
     At time t 5 , the row control signals P 13  and P 15  of the corresponding row change to L level and H level. At time t 5  through t 6 , each horizontal sampling pulse SP is simultaneously changed to H level again and at this occasion, the blanking voltage which is the input image signal is made to constitute the column control signal  14 . 
     At this occasion, in the pixel circuit  2  of the corresponding row shown in  FIG. 13 , M 400  is made OFF, current is not supplied to the EL element and therefore, the EL element is switched off. Further, M 200  and M 300  are respectively made ON and brought into an ON state and therefore, the capacitors C 100  and C 200  and the gate capacitance of M 100  are operated to discharge such that voltage of (VCC-M 100 /G) becomes proximate to threshold voltage Vth of M 100  and therefore, drain current of M 100  is reset to a very small value. Further, also at time t 5  through t 6  during the horizontal blanking period, voltage of the input image signal video is voltage Vb 1  at a vicinity of black level similar to that at time t 1  through t 2  as shown in  FIG. 15 . 
     At time t 6 , although SP and P 14  respectively become L level and H level, the voltage of (VCC-M 100 /G) of the pixel circuit  2  successively stays to be the threshold voltage Vth of M 100 . 
     At time t 7  through t 8 , SP of the corresponding row becomes H level and an input image signal value d 2  at this time is inputted to the pixel circuit  2  as v (data). At this time, voltage of M 100 /G of the pixel circuit  2  is changed by voltage ΔV. The voltage ΔV is generally shown by Equation (1).
 
Δ V=−d 2 ×C 200÷( C 200 +C 100 +C ( M 100))  (1)
 
where C(M 100 ) designates the gate input capacitance of M 100  in the pixel circuit  2 .
 
     At time t 8 , SP is changed again to L level, the change of the voltage M 100 /G shown by Equation (1) is held and the state is maintained until time t 9 . 
     ♦At and after t 9  (luminescence holding period) 
     At time t 9 , P 13  and P 15  are changed again to H level and L level respectively and M 300  and M 400  of the pixel circuit  2  are respectively brought into OFF and ON states. Drain current of M 100  determined by voltage of M 100 /G of the pixel circuit which has been change in this way is applied to the EL element, a change in a luminescence amount is brought about and the state is maintained. 
     Although during time t 9  through t 1 O and time t 1 l through t 12 , the corresponding SP signal is changed to H level, since M 300  of the pixel circuit  2  is made OFF, the luminescence operation of the EL element is not influenced thereby. 
     Equation (1) signifies that the luminescent amount can be set by the voltage value (d 2 ) constituting a reference by Vb 1  during the horizontal blanking period of the input image signal video. The drain current Id of M 100  of the pixel circuit  2  can generally be shown by Equation (2).
 
Id=β×Δ V 2  (2)
 
     The EL element basically carried out the luminescence operation in proportion to injected current and therefore, at the EL panel of the voltage setting system shown in  FIG. 12  it is known from Equation (2) that the luminescence amount of the EL element of each pixel can be controlled by a value in proportion to a square of the input image signal level constituting the reference by the blanking voltage. At the EL panel of the voltage-setting system, a circuit constitution of a liquid crystal panel having positive achievement can be applied thereto except the pixel circuit  2 . 
     &lt;EL Panel By Current Setting System&gt; 
       FIG. 3  shows a circuit constitution of a colored EL panel by a current setting system. First, an explanation will be given of a difference from the EL panel by the voltage setting system of  FIG. 12 . 
     An auxiliary column control signal  13   a  outputs an auxiliary column control signal  13  via an input circuit  8  and the auxiliary column control signal  13  is inputted to gate circuits  4  and  16 . Further, the horizontal sampling signal group  17  outputted to the respective terminals of the horizontal shift register  3  are inputted to a gate circuit  15  and a converted horizontal sampling signal group  18  is inputted to a column control circuit  1 . The gate circuit  15  is inputted with a control signal  21  outputted from the gate circuit  16 . The column control circuit  1  is inputted with a control signal  19  outputted from the gate circuit  4 . 
     (Column Control Circuit) 
       FIG. 8  shows the constitution of the column control circuits  1  aligned by a number the same as a horizontal pixel number of the EL panel of the current setting system. 
     Input image information is constituted by the input image signal video and a reference signal REF which are respectively inputted to M 100 /S, M 200 /S and as well as M 500 /S and M 600 /s. Further, the horizontal sampling signal group  18  outputted from the gate circuits  15  respectively comprise SPa and SPb and connected to M 100 /G, M 500 /G as well as M 200 /G, M 600 /G of the column control circuit  1 . Further, M 100 /D, M 200 /D, M 500 /D and M 600 /D are respectively connected with capacitors C 100 , C 200 , C 300  and C 400  and connected with M 300 /S, M 400 /S, M 700 /S and M 800 /S. The control signal  19  is constituted by P 11  and P 12  which are respectively connected to M 300 /G, M 700 /G as well as M 400 /G, M 800 /G. M 300 /D and M 400 /D as well as M 700 /D and M 800 /D are respectively connected to each other and inputted to a voltage to current conversion circuit gm as v (data) and v (REF). Further, the voltage to current conversion circuit gm is inputted with a reference current setting bias VB and outputs a current signal i (data) used as the column control signal  14 . 
       FIG. 10A  shows an example of a constitution of the voltage to current conversion circuit. Although an explanation thereof will be omitted since the basic operation is general, when, for example, a 200 ppi EL panel is assumed in an EL panel aiming at power conservation as a point of taking a consideration thereto, current injected to the EL element of each pixel is small and maximum current is assumed to be 100 nA significantly smaller than 1 μA. In order to achieve the voltage to current conversion characteristic as linear as possible under the condition, it is necessary to reduce a current drive function by reducing a W/L ratio of the gate region of M 200 , M 300 . 
       FIG. 10B  shows the voltage to current conversion characteristic of  FIG. 10A . According to the voltage to current conversion circuit of  FIG. 10A , it is difficult to carry out a design in which minimum current I 1  (black current) at minimum voltage V 1  (black level) is constituted by zero current. When the black current I 1  cannot be constituted by the zero current, contrast which is important as the image display panel cannot be ensured. 
       FIG. 11A  shows an example of a constitution of the voltage to current conversion circuit taking a measure of this point. Respective drain terminals of first source-coupled circuits M 200  and M 300  are connected with M 600  and M 700  in which respective sources thereof are grounded and drains and gates are shortcircuited. Further, there is provided M 800  operated as a second reference current source in which a source thereof is connected to a power source and a gate thereof is connected to the reference current bias VB, M 800 /D is connected to second source-coupled circuits M 900  and M 1000  and M 900 /G and M 100 O/G are respectively connected to M 700 /D and M 600 /D. Further, a current signal i (data) constituting the column control signal  14  is outputted from M 1000 /D via a current mirror circuit of M 400  and M 500  similar to the voltage to current conversion circuit of  FIG. 10A . In  FIG. 11A , in order to reduce a current drive function of M 600  and M 700  smaller than that of M 900  and M 1000 , a W/L ratio of a gate region of M 600  and M 700  is made to be smaller than W/L ratio of a gate region of M 900  and M 1000 . 
       FIG. 11B  shows a voltage to current conversion characteristic of the voltage to current conversion circuit as shown in  FIG. 11A  which has been designed in this way. Not only the black current I 1  at the black level V 1  can be reduced but also the voltage to current conversion characteristic can be realized without deteriorating the linearity. 
     An explanation will be given of operation of the column control circuit in reference to time charts of  FIGS. 9A ,  9 B,  9 C,  9 D,  9 E and  9 F. 
     At the time t 1 , control signals P 11  and P 12  are respectively changed to L level and H level. 
     During an effective period of the input image signal at time t 1  through t 4 , the horizontal sampling signal group SPa is generated. At the time t 2  through t 3 , SPa of the corresponding column is generated and video and REF at this time point are sampled to the capacitors C 100  and C 300  and held at and after time t 3 . 
     At time t 4 , the control signals P 11  and P 12  are respectively changed to H level and L level and (v(data)-v(REF)) inputted to the voltage to current conversion circuit becomes d 1  and the current signal i (data) is outputted as the column control signal  14  during time t 4  through t 7  based on image signal inputted at time t 2  through t 3 . 
     During the effective period of the input image signal at time t 4  through t 7 , the horizontal sampling signal group SPb is generated, at time t 5  through t 6 , SPb of the corresponding column is generated, inputs video and REF at the time point are sampled to the capacitors C 200  and C 400  and held at and after t 6 . 
     At time t 7 , the control signals P 11  and P 12  are respectively changed again to L level and H level, (v(data)-v(REF)) inputted to the voltage to the current to voltage conversion circuit becomes d 2  and the current signal i (data) is outputted as the column control signal  14  during one horizontal scanning period from time t 7  based on image information inputted at time t 5  through t 6 . 
     During the effective period of the input image signal of the one horizontal scanning period from time t 7 , the horizontal sampling signal group SPa is generated again, at time t 8  through t 9 , SPa of the column is generated and the inputs video and REF at the time point are sampled to the capacitors C 200  and C 400  and held at and after time t 9 . 
     By repeating the above-described operation, current signal i (data) which is the column control signal  14  is converted to a line successive signal updated at every horizontal scanning period of the input image signal video. 
     (Pixel Circuit of Current Setting System) 
       FIG. 6  is an example of a constitution of the pixel circuit  2  of the current setting system. P 9  and P 10  correspond to the row control signal  20 , the current signal i (data) is inputted as the column control signal  14  and M 100 /D is connected to a current injecting terminal of the grounded EL element. 
     The operation will be explained in reference to time charts of  FIGS. 7A ,  7 B and  7 C. At and before time t 0 , P 9  and P 10  of the corresponding m-th row are at H level and therefore, both of M 300  and M 400  are made OFF, current is injected to the EL element by voltage of M 100 /G determined by charge voltage held at the capacity C 100  and the gate capacitance of M 100  and the EL element becomes luminescent in accordance therewith. 
     At time t 0 , both of P 9  and P 10  of the corresponding row are changed to L level and the current signal i (m) of the m-th row is determined. That is, both of M 300  and M 400  are made ON and therefore, the current signal i (m) is supplied to M 200 , voltage of M 200 /G is set in accordance therewith, the capacitor C 100  and the gate capacitances M 100  and M 200  are charged and current in correspondence with the current signal i (m) starts to be injected to the corresponding EL element. 
     At time t 1  at which the current signal i (m) is determined, P 10  is changed to H level, M 300  is brought into an OFF state and the operation of setting the voltage of M 200 /G is finished and shifted to the holding operation. At time t 2 , P 9  is also changed to H level to thereby stop supplying current to M 200 , however, the voltage of M 200 /G set by the current signal i (m) stays to be held, the EL element is reset by injected current which is successively reset and the luminescence is continued. 
       FIG. 4  shows an example of other constitution of the pixel circuit  2  of the current setting system. P 7  and P 8  correspond to the row control signal  20 , the current signal i (data) is inputted as the column control signal  14  and M 400 /D is connected to the current injecting terminal of the grounded EL element. 
     The operation will be explained in reference to time charts of  FIGS. 5A ,  5 B and  5 C. At and before time t 0 , P 7  and P 8  of the corresponding m-th row are respectively at L level and H level and therefore, both of M 200  and M 300  are made OFF and M 400  is made ON and therefore, current is injected to the EL element by voltage of M 100 /G determined by charge voltage held at the capacitor C 100  and the gate capacitance M 100  and the EL element becomes luminescent in accordance therewith. 
     At time t 0 , P 7  and P 8  of the corresponding row respectively change to H level and L level and the current signal i (m) of the m-th row is determined. Both of M 200  and M 300  are made ON and M 400  is made OFF and therefore, current stops to be injected to the EL element of the corresponding row and the EL element of the corresponding row is switched off. Further, the current signal i (m) is supplied to M 100  and therefore, voltage of M 100 /G is set in accordance therewith and the capacitor C 100  and the gate capacitance of M 100  are charged. 
     At time t 1  at which the current signal i (m) is determined, P 8  is changed to H level again and M 200  is brought into an OFF state and the operation of setting the voltage of M 100 /G is finished and shifted to the holding operation. 
     At time t 2 , P 7  is changed to L level to thereby stop supplying current to M 100  and M 400  is made ON, drain current of M 100  set by voltage of M 100 /G is injected to the corresponding EL element and the EL element starts luminescence which is reset at and before time t 1  in accordance therewith and continues luminescence until the luminescence is set again. 
     Based on the above-described result of investigation, it is a problem of the application to realize a novel current signal output circuit which has not been known, particularly realize a current signal output circuit providing an output restraining dispersion. Further, it is a problem thereof to realize a display apparatus having small nonuniformity of display by using the current signal output circuit. 
     An aspect of the invention of a current signal output circuit according to the application is constituted as follows. That is, the aspect is constituted by a current signal output circuit for outputting a current signal in accordance with an inputted voltage signal comprising: 
     a current signal control circuit, the current signal control circuit comprising: 
     at least a first through a sixth switch, a first and a second capacitor element and a first and a second transistor; 
     wherein a first terminal of the first switch is connected to a voltage signal line for providing a voltage signal, a second terminal of the first switch is connected to a first terminal of the first capacitor element, 
     a second terminal of the first capacitor element is connected to a gate electrode of the first transistor, 
     a first terminal and a second terminal of the third switch are respectively connected to the gate electrode and a second main electrode of the first transistor, 
     a first main electrode of the first transistor is connected to a first power source, 
     the second main electrode of the first transistor is connected to a first terminal of the fourth switch, 
     a first terminal of the second switch is connected to the voltage signal line for providing the voltage signal and a second terminal of the second switch is connected to a first terminal of the second capacitor element, 
     a second terminal of the second capacitor element is connected to a gate electrode of the second transistor, 
     a first terminal and a second terminal of the fifth switch are respectively connected to a gate electrode and a second main electrode of the second transistor, 
     a first main electrode of the second transistor is connected to the first power source, 
     the second main electrode of the second transistor is connected to a first terminal of the sixth switch, 
     second terminals of the fourth and the sixth switches are connected to each other to constitute a current signal output terminal for outputting the current signal, 
     and control terminals of the first through the sixth switches are respectively connected to a first through a sixth control signal line. 
     Further, according to the application, the first terminal and the second terminal of the switch signifies two terminals conduction therebetween of which is controlled by the switch and conduction of the switch is controlled by the control signal inputted to the control terminal of the switch. Further, the first main electrode or the second main electrode of the transistor represents either of the two electrodes other than the gate electrode, that is, the source electrode and the drain electrode. Further, the first terminal or the second terminal of the capacitor element only indicates each of the two terminals of the capacitor element for convenience and is not provided with particularly differentiating significance. 
     Another aspect of the invention of a current signal output circuit according to the application is constituted as follows. That is, the aspect is constituted by a current signal output circuit for outputting a current signal in accordance with an inputted voltage signal comprising: 
     a current signal control circuit, the current signal control circuit comprising: 
     at least a first through an eighth switch, a first and a second capacitor element and a first through a fourth transistor; 
     wherein a first terminal of the first switch is connected to a voltage signal line for providing the voltage signal and a second terminal of the first switch is connected to a first terminal of the first capacitor element, 
     a second terminal of the first capacitor element is connected to a gate electrode of the first transistor, 
     a first terminal and a second terminal of the third switch are respectively connected to the gate electrode and a second main electrode of the first transistor, 
     a first main electrode of the first transistor is connected to a first power source, 
     the second main electrode of the first transistor is connected to a first terminal of the fourth switch and a first terminal of the seventh switch, 
     a second terminal of the seventh switch is connected to a first main electrode of the third transistor, 
     a gate electrode and the first main electrode or a second main electrode of the third transistor are shortcircuited and the second main electrode is connected to a second power source, 
     a first terminal of the second switch is connected to the voltage signal line for providing the voltage signal, 
     a second terminal of the second switch is connected to a first terminal of the second capacitor element, 
     a second terminal of the second capacitor element is connected to a gate electrode of the second transistor, 
     a first terminal and a second terminal of the fifth switch are respectively connected to the gate electrode and a second main electrode of the second transistor, 
     a first main electrode of the second transistor is connected to the first power source, 
     the second main electrode of the second transistor is connected to a first terminal of the sixth switch and a first terminal of the eighth switch, 
     a second terminal of the eighth switch is connected to a first main electrode of the fourth transistor, 
     a gate electrode and the first main electrode or a second main electrode of the fourth transistor are shortcircuited and the second main electrode is connected to a second power source, 
     second terminals of the fourth and the sixth switches are connected to each other to constitute a current signal output terminal for outputting the current signal to outside, and 
     control terminals of the first through the eighth switches are respectively connected to a first through an eighth control signal line. 
     Specifically, it is preferable when a time period for conducting both of the third switch and the seventh switch are conducted and/or a time period for conducting both of the fifth switch and the eighth switch are present. 
     Further, the following can be pointed out as another aspect of the invention of a current signal output circuit according to the application. That is, the aspect is a current signal output circuit for outputting a current signal in accordance with an inputted voltage signal characterized in comprising: 
     a current signal control circuit, the current signal control circuit comprising: 
     at least a first and a third switch, a first capacitor element, and a first transistor; 
     wherein a first terminal of the first switch is connected to a voltage signal line for providing the voltage signal, a second terminal of the first switch is connected to a first terminal of the first capacitor element, 
     a second terminal of the first capacitor element is connected to a gate electrode of the first transistor, 
     a first terminal and a second terminal of the third switch are respectively connected to the gate electrode and a second main electrode of the first transistor, and 
     a first main electrode of the first transistor is connected to a first power source. 
     In this case, there can preferably be adopted a constitution in which the gate electrode of the first transistor is charged via the third switch and discharged such that a voltage of the gate electrode of the first transistor becomes proximate to a threshold voltage and thereafter, the gate electrode of the first transistor is charged to a voltage in accordance with the voltage signal provided to the first switch and the current signal in accordance with the charged state is outputted from the second main electrode as the current signal. Further, there can preferably be adopted a constitution in which a current supply path for charging the gate electrode of the first transistor is connected to the second terminal of the third switch via the third switch. There can preferably be adopted a constitution further including a switch for controlling current flowing to the current supply path. 
     Another aspect of the invention of a current signal output circuit according to the application is constituted as follows. That is, the aspect is constituted by a current signal output circuit for outputting a current signal in accordance with an inputted voltage signal comprising: 
     a current signal control circuit, the current signal control circuit comprising: 
     at least a first switch, a first capacitor element and a first transistor; 
     wherein a first terminal of the first switch is connected to a voltage signal line for providing the voltage signal, a second terminal of the first switch is connected to a first terminal of the first capacitor element, 
     a second terminal of the first capacitor element is connected to a gate electrode of the first transistor, and 
     the first main electrode of the first transistor is connected to a first power source. 
     In this case, there can preferably be adopted a constitution in which the gate electrode is discharged such that a voltage of the gate electrode of the first transistor becomes proximate to a threshold voltage, thereafter the gate electrode of the first transistor is charged to a voltage in accordance with the voltage signal provided to the first switch and the current signal is outputted in accordance with the charged state from the second main electrode of the first transistor. 
     Further, in the constitution in which the voltage of the gate electrode of the first transistor is discharged to be proximate to the threshold voltage, there can preferably be adopted a constitution in which the gate electrode is discharged such that a voltage of the gate electrode of the first transistor becomes proximate to a threshold voltage in a time period in which the voltage signal provided to the first switch is at a reference level. 
     Further, there can preferably be adopted a constitution in which a current signal output circuit comprising at least two of the current signal control circuits, wherein the gate electrode of the first transistor is charged to a voltage in accordance with the voltage signal in other of the current signal control circuits when the current signal is outputted in one of the current signal control circuits. There can preferably be adopted a constitution in which each of the current signal control circuits includes a switch for controlling whether the current signal outputted from the second main electrode of the first transistor is outputted to outside, when the switch of one of the current signal control circuits is brought into a state of outputting the current signal outputted from the second main electrode of the first transistor to outside, the switch of other of the current signal control circuits is controlled to a state in which the current signal outputted from the second main electrode of the first transistor is not outputted to outside. 
     Further, the application includes another aspect of the invention of a display apparatus characterized in including the above-described current signal output circuit and a plurality of display elements in which the current signal output circuit supplies the current signal successively to the plurality of display elements. 
     Particularly, the application includes another aspect of the invention of a display apparatus include the current signal output circuit and a plurality of display elements in which the current signal output circuit is constituted to successively supply the current signal to the plurality of display elements and is controlled such that a corresponding relationship between at least two of the current signal control circuits constituting the current signal output circuit and respectives of the plurality of display elements is not fixed. That the current signal output circuit is controlled such that the corresponding relationship between at least two of the current signal control circuits constituting the current signal output circuit and respectives of the plurality of display elements is not fixed, signifies that when the current signal is successively supplied to the plurality of display elements by plural times, in a certain series of successive supply, when the output current from one of the current signal control circuits is supplied to a predetermined display element, in a series of successive supply different from the above-described series thereof such as a series thereof successive to the above-described series thereof, the output current from other of the current signal control circuits is supplied to the predetermined display element. When a screen is constituted by a plurality of display elements, a constitution of changing the current signal control circuits in correspondence with the respective display elements at each updating of the screen (including a case in which content of the display screen is not changed) at, for example, each frame is particularly preferable. 
     Further, as display apparatus there can preferably be adopted a constitution using the current signal output circuit for inputting a column direction signal and having a row direction control circuit for controlling a row direction signal as the display apparatus. Specifically, there can preferably be adopted a constitution further comprising a plurality of sets each comprising the current signal output circuit and the plurality of display elements to which the current signal output circuit successively supplies the current signal, wherein a matrix of the display elements is constituted by the display elements belonging to the respective sets, the current signal output circuit controls the matrix in a column direction thereof and includes a row control circuit for controlling the matrix in a row direction thereof. 
     Further, with regard to the constitution having the fourth switch and the sixth switch, there can be adopted a display apparatus comprising the current signal output circuit, and arranging a plurality of display elements for receiving supply of a signal from an output signal of the current signal at a two dimensional region, including a function of selectively operating the fourth and the sixth switches and the fourth and the sixth switches are changed by an odd number row or an even number row by a frame of a displayed image signal. When there are not other switches in correspondence with the fourth and the sixth switches, the fourth and the sixth switches may complimentarily be operated. 
     Further, as a constitution in which the corresponding relationship between the current signal control circuit and the display element is not fixed, there can preferably be adopted a constitution in which the current signal control circuit switches to output signals in correspondence with respective colors. 
     Further, as display elements in the above-described constitution, various constitutions of display elements such as combining an electron discharge element and a luminescent member which becomes luminescent by electrons discharged by the electron discharge element, particularly, the display element using the electroluminescence element is preferable. Further specifically, the display element having an electroluminescence element and a pixel circuit for driving the electroluminescence element can preferably be used. 
     Further, there can particularly preferably be adopted a constitution in which the display element includes the pixel circuit, the pixel circuit holds a voltage value in correspondence with a signal from the current signal output circuit and outputs a current value in accordance with the held voltage value. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  shows an embodiment of a column control circuit included in an electroluminescence element drive control circuit; 
         FIGS. 2A ,  2 B,  2 C,  2 D,  2 E,  2 F,  2 G,  2 H,  2 I,  2 J,  2 K and  2 L are time charts for explaining operation of the column control circuit of  FIG. 1 ; 
         FIG. 3  is a circuit diagram of a total of an EL panel by a current setting system; 
         FIG. 4  is a pixel circuit of the current setting system; 
         FIGS. 5A ,  5 B and  5 C are time charts for explaining operation of the pixel circuit of  FIG. 4 ; 
         FIG. 6  shows a pixel circuit of a current setting system; 
         FIGS. 7A ,  7 B and  7 C are time charts for explaining operation of the pixel circuit of  FIG. 6 ; 
         FIG. 8  shows an example of a column control circuit included in an EL element drive control circuit of a current setting system; 
         FIGS. 9A ,  9 B,  9 C,  9 D,  9 E and  9 F are time charts for explaining operation of the column control circuit of  FIG. 8 ; 
         FIGS. 10A and 10B  are views for explaining a voltage to current conversion circuit used in the column control circuit of the embodiment of  FIG. 8 .  FIG. 10A  is a circuit diagram.  FIG. 10B  is a view for explaining a voltage to current conversion characteristic of the circuit of  FIG. 10A ; 
         FIGS. 11A and 11B  are views for explaining other voltage to current conversion circuit of the embodiment of  FIG. 8 .  FIG. 8A  is a circuit diagram.  FIG. 8B  is a view for explaining a voltage to current conversion characteristic of the circuit of  FIG. 8A ; 
         FIG. 12  is a circuit diagram of a total of an EL panel by a voltage setting system; 
         FIG. 13  is a pixel circuit by the voltage setting system; 
         FIG. 14  is a column control circuit by the voltage setting system; 
         FIGS. 15A ,  15 B,  15 C,  15 D and  15 E are time charts for explaining operation of the EL panel of  FIG. 12 ; and 
         FIG. 16  is a view showing a constitution of an information display apparatus. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     First, when the pixel circuit of the voltage setting system as shown in  FIG. 13  is used, although a dispersion among transistors having the threshold voltage of Vth can be reset, the pixel circuit cannot deal with a dispersion in a drive coefficient β caused mainly by a dispersion in a mobility μ of the channel. Although it is preferable to enlarge a gate region area of the current-driven transistor M 100  in order to restrain the dispersion in the mobility μ of channel, in the case of a small-sized and highly fine panel aiming at 200 ppi considerably restricting the pixel circuit area, the dispersion in the drive coefficient β cannot significantly be improved by the gate region area of the drive transistor 
     Therefore, particularly in the case of assuming a small-sized display panel, there poses a problem that an image having a fixed noise in which brightnesses of individual pixels are randomly varied is brought about and a display panel having high image quality cannot be realized. 
     Further, when the pixel circuit of the current setting system as shown in  FIG. 4  is used, although dispersions in the threshold voltage Vth and the drive coefficient β can be reset even in a small-sized and highly fine display panel at the individual pixel circuit  2 , in the case of the current setting system, there is needed the current control circuit for outputting the current signal i (data) by carrying out voltage to current conversion from the point successive signal to the line successive signal as the column control signal  14 . 
     However, according to the voltage to current conversion circuit gm including the source-coupled circuits and the current mirror circuit as shown in  FIG. 10A  and  FIG. 11A , the voltage to current conversion characteristics of the respective pixel columns cannot be made uniform by the dispersions in the threshold voltage Vth and the drive coefficient β of TFT, a display panel having a fixed pattern of vertical stripes as an image is brought about and high image quality formation is difficult. 
     Further, when the current signal honest to the input image signal is going to be outputted to the pixel circuit as described above, the constitution of the column control circuit becomes complicated, which cannot be regarded as pertinent for small-sized formation of the display panel. 
       FIG. 1  shows an embodiment of a current signal control circuit (hereinafter, described mainly as column control circuit) included in an electroluminescence element drive control circuit used in an EL panel of a current setting system as shown in  FIG. 3 . Although a detailed explanation will be given of the invention in reference to a specific embodiment shown in  FIG. 1  as follows, the invention is not limited to the embodiment. 
     According to a preferable embodiment shown in  FIG. 1 , a column control circuit  1  includes at least a first through an eighth switch (M 1 , M 7 , M 2 , M 6 , M 8 , M 10 , M 4 , M 11 ), a first and a second capacitor element (C 1 , C 3 ) and a first through a fourth transistor (M 3 , M 9 , M 5 , M 12 ). A first terminal of the first switch M 1  is connected to an information voltage signal line (image signal video) for providing an information voltage signal, a second terminal of the first switch M 1  is connected to a first terminal of the capacitor element C 1 , a second terminal of the first capacitor element C 1  is connected to a gate electrode of the first transistor M 3 , the first terminal and a second terminal of the third switch M 2  are respectively connected to the gate electrode and a second main electrode of the first transistor M 3 , a first main electrode of the first transistor M 3  is connected to a first power source (GND), the second main electrode of the first transistor M 3  is connected to a first terminal of the fourth switch M 6  and a first terminal of the seventh switch M 4 , a second terminal of the seventh switch M 4  is connected to a first main electrode of the third transistor M 5 , a gate electrode and a first main electrode or a second main electrode of the third transistor M 5  are shortcircuited and the second main electrode is connected to a second power source (VCC), a first terminal of the second switch M 7  is connected to the information voltage signal line (image signal video) providing the information voltage signal, a second terminal of the second switch M 7  is connected to a first terminal of the second capacitor element C 3 , a second terminal of the second capacitor element C 3  is connected to a gate electrode of the transistor M 9 , a first terminal and a second terminal of the fifth switch M 8  are respectively connected to a gate electrode and a second main electrode of the transistor M 9 , a first main electrode of the second transistor M 9  is connected to the first power source GND, the second main electrode of the second transistor M 9  is connected to a first terminal of the sixth switch M 10  and a first terminal of the eighth switch M 11 , a second terminal of the eighth switch M 11  is connected to a first main electrode of the fourth transistor M 12 , a gate electrode and the first main electrode or a second electrode of the transistor M 12  are shortcircuited and the second main electrode is connected to a second power source VCC, the second terminals of the fourth and the sixth switches M 6  and M 10  are connected to each other to constitute a current signal output terminal for outputting the current signal to outside, and control terminals of the first through the eighth switches (M 1 , M 7 , M 2 , M 6 , M 8 , M 10 , M 4 , M 11 ) are respectively connected to a first through an eighth control signal line (SPa, SPb, P 1 , P 3 , P 4 , P 6 , P 2 , P 5 ). Further, according to the embodiment of  FIG. 1 , the column control circuit  1  also includes a third capacitor element (C 2 ) and a fourth capacitor element (C 4 ), a first terminal of the third capacitor element C 2  is connected to the first power source, a second terminal thereof is connected to the gate electrode of the first transistor M 3 , a first terminal of the fourth capacitor element C 4  is connected to the first power source and a second terminal thereof is connected to the gate of the second transistor M 9 , however, the capacitor elements C 2  and C 4  may be realized by only gate input capacitances (channel capacitance) of M 3  and M 9  and in this case, the capacitors C 2  and C 4  are not needed. 
     Next, with regard to a case of specifying channel characteristics of the transistors such that M 1  is of n-channel and M 5  is of p-channel as shown in  FIG. 1 , the constitution of the invention will be shown further specifically and the operation will be explained, however, this is only an example, when a relationship of potential between the first power source GND and the second power source VCC or the channel characteristics of the respective transistors are reverted, the constitution may pertinently be changed in accordance therewith. 
     The column control circuit  1  is inputted with the image signal video, the sampling signals SPa and SPb, and P 1  through P 6  which are the control signals  19 . 
     The image signal video is connected to M 1 /S and M 7 /S and the sampling signals SPa and SPb are respectively connected to M 1 /G and M 7 /G. M 1 /D is connected to the capacitor C 1  and other end of the capacitor C 1  is connected to the capacitor C 2  one end of which is grounded and M 3 /G the source of which is grounded. M 3 /D and M 3 /G are connected to M 2 /D and M 2 /S, and M 2 /G is connected with P 1 . M 3 /D is connected to M 4 /S, M 4 /D is connected to M 5  the source of which is connected to the power source VCC and the gate and the drain of which are shortcircuited and M 4 /G is connected with P 2 . Further, M 3 /D is connected to M 6 /S, M 6 /D is connected to the terminal for outputting the current signal i (data) and M 6 /G is connected with P 3 . Meanwhile, M 7 /D is connected to the capacitor C 3  and other end of the capacitor C 3  is connected to the capacitor C 4  one end of which is grounded and M 9 /G the source of which is grounded. M 9 /D and M 9 /G are connected to M 8 /D and M 8 /S, and M 8 /G is connected with P 4 . M 9 /D is connected with M 11 /S, M 11 /D is connected to M 12  the source of which is connected to the power source VCC and the gate and the drain of which are shortcircuited and M 11 /G is connected with P 5 . Further, M 9 /D is connected to M 10 /S, M 10 /D is connected to the terminal for outputting the current signal i (data) and M 10 /G is connected with P 6 . Further, gate sizes (W, L) and capacitance values of the respective transistors are constituted as follows.
 
M1=M7, M3=M9, M2=M8, M5=M12, C1=C3, C2=C4  (3)
 
     (Explanation of Operation of Column Control Circuit) 
       FIGS. 2A ,  2 B,  2 C,  2 D,  2 E,  2 F,  2 G,  2 H,  2 I,  2 J,  2 K and  2 L are time charts for explaining operation of  FIG. 1 . FIGS.  2 A,  2 B,  2 C,  2 D,  2 E,  2 F,  2 G,  2 H,  2 I,  2 J,  2 K and  2 L show operation of three horizontal scanning periods of the image signal, that is, of an amount of three rows in view from the EL panel. 
     ♦Immediately before time t 1   
     SPa and SPb are respectively at L, L level and P 1  through P 6  are respectively at L, L, H, L, H, L level. Therefore, the respective transistors for carrying out switching operation become as follows. 
     M 1 =Off, M 2 =OFF, M 4 =OFF, M 6 =ON, M 7 =OFF, M 8 =OFF, M 11 =ON, M 10 =OFF 
     At this occasion, M 3  and M 9  are driven by current by hold voltages Va 1  and Vb 1  respectively charged to the capacitors accompanied by the gate electrodes. That is, M 3 /D current Ia 1  is outputted to the current signal i (data) to constitute the column control signal  14 . M 9 /D current is supplied to M 12  to determine M 9 /D voltage. 
     ♦Time t 1  through t 7   
     At time t 1 , the input image signal video becomes a blanking level Vb 1  and SPa, P 2 , P 3 , P 5 , P 6  are respectively changed to H, H, L, L, H level. 
     Therefore, the respective transistors for carrying out switching operation become as follows. 
     M 1 =ON, M 2 =OFF, M 4 =ON, M 6 =OFF, M 7 =OFF, M 8 =OFF, M 11 =OFF, M 10 =ON 
     At this occasion, M 9 /D current Ib 1  driven by Vb 1  of M 9 /G voltage is outputted to the current signal i (data) in place of M 3 /D current Ib 2 . The current signal i (data) is connected to elements in correspondence with a large column pixel number by passing a column length of the EL panel and therefore, large parasitic capacitance must be driven and therefore, as shown in the figure, time is required in effective current supply transition Ia 1 →Ib 1  for the pixel circuits. Before time t 2  is reached, P 1  becomes H level to constitute M 2 =ON and M 3 /G is charged by M 5  in a short period of time from the time point to time t 2 . 
     At time t 2 , the operation of charging M 3 /G by M 5  is stopped and M 3 /G carries out self discharge operation to be proximate to the threshold voltage Vth of its own. 
     At time t 3 , SPa is changed to L level and constitutes ML=OFF. Before time t 4 , P 1  is changed to L level to constitute M 2 =OFF and the self discharge operation of M 3  is finished at the time point. During a period from this time point to time t 4 , both of M 2  and M 4  are made OFF and M 3 /D is rapidly changed to L level and therefore, more or less voltage drop is generated at M 3 /G as shown in the figure by drain-gate capacitance or the like. 
     At time t 4  at which P 2  is changed to H level, M 4 =ON is constituted and therefore, voltage of M 3 /D rises again and therefore, voltage of M 3 /G rises again as shown in the figure to return to substantially the original state. At the time point, the voltage of M 3 /G is proximate to the threshold voltage Vth of its own and therefore, M 3 /D current is almost zero. In an effective period of the image signal video of time t 1  through t 7 , although the horizontal sampling signal group SPa is generated, the horizontal sampling signal group SPb is not generated. At time t 5  through t 6 , the horizontal sampling signal SPa of the corresponding row is generated and the voltage of M 3 /G held at the vicinity of the threshold voltage Vth of its own is changed by transition voltage ΔV 1  by the image signal level d 1  constituting the reference by the blanking level at the time point. 
     ΔV 1  is generally shown by Equation (4).
 
Δ V 1 =d 1 ×C 1÷( C 1 +C 2 +C ( M 3))  (4)
 
     Notation C (M 3 ) designates gate input capacitance of M 3 . At this occasion, M 3 /D current is shown by Equation (2). When corresponding SPa is changed to L level, M 1 =OFF is constituted and changed to Va 2  more or less dropped by the parasitic capacitance operation of M 1  and the voltage of M 3 /G is brought into the holding state again. 
     ♦Time t 7  through t 13   
     At time t 7 , the input image signal video becomes the blanking level Vb 1  and SPb, P 2 , P 3 , P 5 , P 6  are respectively changed to H, L, H, H, L level. 
     Therefore, the respective transistors for carrying out switching operation become as follows. 
     M 1 =OFF, M 2 =OFF, M 4 =OFF, M 6 =ON, M 7 =ON, M 8 =OFF, M 11 =ON, M 10 =OFF 
     At this occasion, M 3 /D current Ia 2  driven by Va 2  of the voltage of M 3 /G is outputted to the current signal i (data) in place of M 9 /D current Ib 1 . The current signal i (data) is connected to the elements in correspondence with the large column pixel number by passing the column length of the EL panel and therefore, must drive large parasitic capacitance and therefore, time is required in effective current supply transition Ib 1 →Ia 2  for the pixel circuit as shown in the figure. Before time t 8  is reached, P 4  becomes H level to constitute M 8 =ON and in a short period of time from the time point to time T 8 , M 9 /G is charged by M 12 . 
     At time t 8 , the operation of charging M 9 /G by M 12  is stopped and M 9 /G carries out self discharge operation to be proximate to the threshold voltage Vth of its own. 
     At time t 9 , SPb is changed to L level to constitute M 7 =OFF. Before time t 10  is reached, P 4  is changed to L level to constitute M 8 =OFF and at the time point, the self discharge operation of M 9  is finished. During a period from the time point to time t 10 , both of M 8  and M 11  are made OFF and M 9 /D is rapidly changed to L level and therefore, the voltage of M 9 /G is more or less dropped as shown in the figure by the drain-gate capacitance or the like. 
     At time t 10  at which P 5  is changed to H level, M 11 =ON is constituted and therefore, the voltage of M 9 /D rises again and therefore, the voltage of M 9 /G rises again to return to substantially original state as shown in the figure. At the time point, the voltage of M 9 /G is at the vicinity of the threshold voltage Vth of its own and therefore, M 9 /D current is almost zero. In an effective period of the image signal video at time t 7  through t 13 , although the horizontal sampling signal group SPb is generated, the horizontal sampling signal group SPa is not generated. 
     At time t 11  through t 12 , the horizontal sampling signal SPb of the corresponding column is generated and the voltage of M 9 /G held at the vicinity of the threshold voltage Vth of its own is changed by transition voltage ΔV 2  by the image signal level d 2  constituting the reference by the blanking level at the time point. ΔV 2  is generally shown by Equation (5)
 
Δ V 2 =d 2 ×C 3÷( C 3 +C 4 +C ( M 9))  (5)
 
     Notation C(M 9 ) designates a gate input capacitance of M 9 . At this occasion, M 9 /D current is shown by Equation (2). When corresponding SPb is changed to L level, M 7 =OFF is constituted and the voltage of M 9 /G is changed to Vb 2  which is more or less dropped by the parasitic capacitance operation of M 7  and the voltage of M 9 /G is brought into the holding state again. 
     ♦Time t 13  through  1  horizontal scanning period 
     At time  13 , the input image signal video becomes the blanking level Vb 1 , and SPa, P 2 , P 3 , P 5 , P 6  are respectively changed to H, H, L, L, H level. 
     Therefore, the respective transistors for carrying out switching operation become as follows. 
     M 1 =ON, M 2 =OFF, M 4 =ON, M 6 =OFF, 
     M 7 =OFF, M 8 =OFF, M 11 =OFF, M 10 =ON 
     At this occasion, M 9 /D current Ib 2  driven by Vb 2  of the voltage of M 9 /G is outputted to the current signal i (data) in place of M 3 /D current Ia 2 . The current signal i (data) is connected to the elements in correspondence with the large number of column pixel number by passing the column length of the EL panel and therefore must drive the large parasitic capacitance and therefore, when Ia 2  and Ib 2  are different from each other, similar to the change of Ib 1 →Ia 2 , time is required in a change of effective current supply transition Ia 2 →Ib 2  for the pixel circuit. Before time t 14  is reached, P 1  becomes H level to constitute M 2 =ON and M 3 /G is charged by M 5  in a short period of time from this time point to time t 14 . 
     At time t 14 , operation of charging M 3 /G by M 5  is stopped and M 3 /G carries out self discharge operation to be proximate to the threshold voltage Vth of its own. 
     At time t 15 , SPa is changed to L level to constitute M 1 =OFF. Before time t 16  is reached, P 1  is changed to L level to constitute M 2 =OFF and the self discharge operation of M 3  is finished at the time point. During a period from this time point to time t 16 , both of M 2  and M 4  become OFF and M 3 /D is rapidly changed to L level and therefore, the voltage of M 3 /G is more or less dropped as shown in the figure by the drain-gate capacitance or the like. 
     At time t 16  at which P 2  is changed to H level, M 4 =ON is constituted and therefore, the voltage of M 3 /D rises again and therefore, the voltage of M 3 /G rises again to return to substantially the original state as shown in the figure. At the time point, the voltage of M 3 /G is at the vicinity of the threshold voltage Vth of its own and therefore, M 3 /D current is almost zero. 
     During an effective period of the image signal video at time t 16  through t 17 , although the horizontal sampling signal group SPa is generated, the horizontal sampling signal group SPb is not generated. 
     At time t 17  through t 18 , the horizontal sampling signal SPa of the corresponding row is generated and the voltage of M 3 /G held at the vicinity of the threshold voltage Vth of its own is changed by transition voltage ΔV 3  by an image signal level d 3  constituting the reference by the blanking level at the time point. 
     ΔV 3  is generally shown by Equation (6)
 
Δ V 3 =d 3 ×C 1÷( C 1 +C 2 +C ( M 3))  (6)
 
     Notation C(M 3 )designates the gate input capacitance of M 3 . At this occasion, M 3 /D current is shown by Equation (2). When corresponding SPa is changed to L level, M 1 =OFF is constituted and the voltage of M 3 /G is changed to the voltage Va 2  which is more or less dropped by the parasitic capacitance operation of M 1  and the voltage of M 3 /G is brought into the holding state again. 
     The EL panel of the invention is realized in an EL panel of a current setting system of an active matrix type as shown in  FIG. 3  by using the current signal control circuit of the invention as the column control circuit  1  and the EL panel can be operated similar to that of the background art except that the column control circuit  1  is controlled as described above. Therefore, the pixel circuit  2  having a mode as shown in  FIG. 4  or  FIG. 6  can naturally be used. 
     Further, the invention includes an electroluminescence panel in which a plurality of pixel circuits arranged in pair with electroluminescence elements for supplying injected current to each of the electroluminescence elements in accordance with an inputted current signal are arranged at a two-dimensional region, wherein a plurality of current signal control circuits for supplying the current signal to the pixel circuits in accordance with information voltage signals inputted from outside, each of the current signal control circuits is provided with a function of inputting a single one of the information voltage signals, holding a first voltage value in correspondence with the information voltage signal inputted during a time period of writing to the corresponding control circuit and outputting a current signal in correspondence with the held first voltage value to a selected one of the pixel circuits during an output time period of the control circuit and each of the pixel circuits is provided with a function of holding a second voltage value in correspondence with the current signal inputted during the time period of writing to the corresponding one of the pixel circuits and continuing to supply the injected current in correspondence with the held second voltage value to the electroluminescence element during corresponding luminescence time period. 
     Such an electroluminescence panel includes the EL panel as shown in  FIG. 3  using the current signal control circuit of the invention described above in details and using the pixel circuit of the current setting system as shown in  FIG. 4  through  FIG. 7  as a specific embodiment thereof. The explanation of the constitution and operation of the current signal control circuit according to the invention in reference to  FIG. 1  and  FIG. 2  corresponds to the explanation of the constitution and the operation of the pixel circuit of the background art in reference to  FIG. 4  through  FIG. 7  as follows. 
     First, the single information voltage signal inputted to the current signal control circuit corresponds to video and different from the background art as shown in  FIG. 8 , the reference signal REF is not necessary. 
     The time period of writing to the corresponding control circuit corresponds to a time period of making the first switch M 1  ON by the sampling signal SPa (for example, a time period in which SPa is at H during t 5  through t 6  in  FIG. 2 ) in the single current signal control circuit as shown in  FIG. 1 . The first voltage value in correspondence with the information voltage signal inputted to the corresponding current signal control circuit during the time period is held by, for example, the first capacitor element C 1  and the current signal in correspondence with the held first voltage value can be outputted by using the first transistor M 3  the gate electrode of which is connected to C 1 . The current signal is outputted to the selected pixel circuit during the output period of the control circuit, the output period of the control circuit corresponds to a time period in which the fourth switch M 6  is made ON by the fourth control signal P 3  (for example, a time period at which P 3  is at H of t 7  through t 13  in  FIG. 2 ) in the single current signal control circuit as shown in  FIG. 1 . Further, selection of the pixel circuit indicates that P 7  of the row control signal is at H, M 300  is made ON and M 100 /G is brought into a state of being operated to set during the time period of t 0  through t 2  in  FIG. 5 , which is also the time period of writing to the pixel circuit. 
     In each of the pixel circuits, the second voltage value in correspondence with the current signal inputted from the current signal control circuit during the time period of writing to the pixel circuit is held by utilizing the capacitance element C 100  as the second voltage holding means in the case of, for example, the pixel circuit of  FIG. 4  and the injected current in correspondence with the held second voltage value can continue supplying to the EL element during the corresponding luminescence time period by using the transistor M 3  the gate electrode of which is connected to C 100  as the injecting means. Here, the corresponding luminescence period is a time period in which, for example, P 7  at and after t 2  in  FIG. 5  is at L, M 300  is made OFF, M 400  is made ON and the injected current can be supplied to the EL element. 
     As explained above, according to the invention, the line successive current signal i (data) can be outputted based on the information voltage signal of the input image signal video. 
     The column control circuit  1  of  FIG. 1  is mounted with a voltage setting circuit and therefore, a consideration needs to be given to operation of M 3  and M 9  which are the current driving transistors. In the EL panel, the column control circuit  1  is provided with an area allowance in comparison with the pixel circuit and therefore, gate areas of M 3  and M 9  can be enlarged. Although generally, the dispersion Δβ of the drive coefficient of a basic size of TFT is about 20% pp, by enabling to enlarge the gate areas of M 3  and M 9  as in the invention, when the column control circuit is constituted by a size 16 times as large as that in the case of providing to the pixel electrode, it can be expected that the dispersion Δβ in the drive coefficient can be made to be about 5% pp of the quarter. 
     Further, in the operation shown in  FIG. 2 , when the fourth and the sixth switches (M 6 , M 10 ) are complimentarily operated by switching the horizontal scanning periods assigned with the control signals of respective pairs of SPa, Pa, P 2 , P 3  and SPb, P 4 , P 5 , P 6  such that odd number even number at every image signal frame, the current signal i (data) of each pixel is generated by M 3  and M 9  and therefore, the dispersion Δβ of the drive coefficient is further reduced to 3.5% pp of a multiplication of 1/√2 thereof. 
     Further, it is also possible that color processed by the column control circuit of the corresponding row is not determined but is switched by the input image signal at every image signal frame as in, for example, R→G→B, G→B→R, B→R→G and the current signal i (data) from the current control circuit  1  of three colors of the same pixel is switched. That is, when at least three colors of the image signal groups are inputted as information voltage signals, by constituting one set by three of the column control circuits and the current signals in correspondence with the image signals of respective colors outputted from the one set of column control circuits are switched to output among the three column control circuits included in the one set to column control circuits by a unit of the image signal frame. In this case, the dispersion Δβ of the drive coefficient can further be reduced to 2.0% pp of a multiplication of 1/√3 thereof. 
     Further, according to the invention, by alternately outputting the current signal i (data) by a first block including M 1  through M 6 , C 1  and C 2  using SPa, P 1 , P 2 , P 3  and a second block including M 7  through M 12 , C 3  and C 4  using SPb, P 4 , P 5 , P 6 , at a time point of finishing the group of the sample signal SPa or the group of SPb, a desired current output is provided from each of the column control circuits and therefore, such a constitution is preferable. However, when the current is constituted to supply to the pixel circuit from the time point of finishing the group of the sample signal SPa to a successive row control start timing, the column control circuit of  FIG. 1  may be constituted by a column control circuit which does not use SPb, P 4 , P 5 , P 6  and excludes M 7  through M 12 , C 3 , C 4 . 
     Further, in  FIG. 1 , the basic concept of the invention is not destroyed by eliminating the bias circuit of M 3 /D and M 9 /D and the charge circuit of M 3 /G and M 9 /G constituted by P 2 , M 4 , M 5  and P 5 , M 11  and M 12 . 
     Further, in  FIG. 2 , timings of changing P 1  and P 2  may be constituted by time t 1 , t 3 , t 13  and t 15  to be equal to those of SPa. Further, timings of changing P 4  and P 5  may be constituted by time t 8 , t 10  to be equal to those of SPb. 
     Further, although the invention achieves a significant effect when TFT which is normally problematic in the dispersion of the characteristic is used as the transistor, the invention is widely applicable even when the circuit is constituted by an insulating gate type field effect transistor using single crystal silicon. 
     As explained above, when the EL element drive control circuit applied with the invention is used, the dispersion of the element characteristic of the insulating gate type field effect transistor of TFT or the like can significantly be alleviated without deteriorating a request of highly fine display by a simple circuit constitution and therefore, the EL panel providing display image having uniform characteristic can be realized and significant effect is achieved also in small-sized formation of the highly fine EL panel. 
       FIG. 16  is a view for explaining a constitution of an information display apparatus using the EL panel explained in the above-described embodiment as a display apparatus. The information display apparatus takes a mode of any of a portable telephone, a portable computer, a still camera or a video camera. Or, the apparatus is an apparatus of realizing a plurality of respective functions thereof. An apparatus in correspondence with the EL panel explained in the above-described embodiment is a display apparatus  1601 . Notation  1602  designates an information input portion. In the case of a portable telephone, the information input portion is constituted to include an antenna, for example, in the case of PDA or a portable personal computer, the information input portion is constituted to include an interface portion with regard to a network and in the case of a still camera or a movie camera, the information input portion is constituted to include a sensor portion by CCD, CMOS and the like. Notation  1603  designates a cabinet for holding the information input portion  1602  and the display apparatus  1601 . 
     According to the present invention, an current signal having an excellent quality can be generated. Further, display having an excellent quality can be realized thereby.