Patent Publication Number: US-2023133879-A1

Title: Storage device sharing system and storage device sharing method

Description:
CROSS-REFERENCE TO RELATED PATENT APPLICATION 
     This application claims the benefit of priority to Taiwan Patent Application No. 110139983, filed on Oct. 28, 2021. The entire content of the above identified application is incorporated herein by reference. 
     FIELD OF THE DISCLOSURE 
     The present disclosure relates to a storage device sharing system and a storage device sharing method, and more particularly to a storage device sharing system and a storage device sharing method that can reduce area usage and power consumption. 
     BACKGROUND OF THE DISCLOSURE 
     Nowadays, many consumer products and computer peripheral products, such as notebook computers, computer monitors, TVs, etc., have multiple identical input or output interfaces, for example, multiple USB ports or multiple HDMI ports, and multiple chips having the same function may be used by these interfaces, respectively. 
     In addition, speeds of various input or output interfaces are also increasing, and the need for chips with signal amplification functions, such as retimers and redrivers, are also increasing. These multiple signal amplification chips with the same interface also use the same firmware. According to the conventional technology, each of these chips is usually equipped with a non-volatile random-access memory (NVRAM) to store the firmware. 
     Under this architecture, the use of a large number of NVRAMs leads to increased costs and PCB usage area. In addition, as power consumption is gradually being held in higher regard, most products need to pass the scrutiny of power consumption test certifications such as Energy Star (ES) 8.0, and the use of more NVRAM also leads to an increase in power consumption. 
     SUMMARY OF THE DISCLOSURE 
     In response to the above-referenced technical inadequacies, the present disclosure provides a storage device sharing system and a storage device sharing method. 
     In one aspect, the present disclosure provides a storage device sharing system that includes a storage device, a first chip, and a second chip. The first chip is connected to the storage device and having a first arbitration terminal. The second chip is connected to the storage device and has a second arbitration terminal. The second arbitration terminal is connected to the first arbitration terminal and has an arbitration potential. The first chip and the second chip are configured to enter a toggle mode, in which: the first chip acts as a master, and is configured to control the arbitration potential to a first control potential and a second control potential through the first arbitration terminal, and to communicate with the storage device in response to the arbitration potential being the first control potential; the second chip acts as a first slave, and is configured to communicate with the storage device in response to the arbitration potential being the second control potential. The first chip and the second chip are configured to determine whether a preferential communication event occurs, and the first chip or the second chip in which the preferential communication event occurs is configured to enter an arbitration mode, so as to adjust the arbitration potential from a first arbitration potential to a second arbitration potential and to be in communication with the storage device, and to adjust, in response to communication being completed, the arbitration potential from the second arbitration potential to the first arbitration potential. 
     In another aspect, the present disclosure provides a storage device sharing method, adapted to a storage device sharing system that includes a storage device, a first chip and a second chip, and the storage device sharing method includes: connecting the first chip to the storage device, in which the first chip has a first arbitration terminal; connecting the second chip to the storage device, wherein the second chip has a second arbitration terminal, and the second arbitration terminal is connected to the first arbitration terminal and has an arbitration potential; configuring the first chip and the second chip to enter a toggle mode, which includes: configuring the first chip to act as a master, so as to control the arbitration potential to a first control potential and a second control potential through the first arbitration terminal, and to communicate with the storage device in response to the arbitration potential being the first control potential; configuring the second chip to act as a first slave, so as to communicate with the storage device in response to the arbitration potential being the second control potential; configuring the first chip and the second chip to determine whether a preferential communication event occurs, and configuring the first chip or the second chip in which the preferential communication event occurs to enter an arbitration mode, so as to adjust the arbitration potential from a first arbitration potential to a second arbitration potential and to be in communication with the storage device, and to adjust, in response to communication being completed, the arbitration potential from the second arbitration potential to the first arbitration potential. 
     Therefore, in the storage device sharing system and storage device sharing method provided by the present disclosure, a structure in which multiple chips share a single storage device is utilized, and since the number of storage devices used is small, power consumption and circuit board usage area can be reduced, thereby reducing costs. 
     In addition, the storage device sharing system and storage device sharing method provided by the present disclosure are applicable to various existing storage devices and various communication interfaces, have a wide application range and provide high flexibility. 
     These and other aspects of the present disclosure will become apparent from the following description of the embodiment taken in conjunction with the following drawings and their captions, although variations and modifications therein may be affected without departing from the spirit and scope of the novel concepts of the disclosure. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The described embodiments may be better understood by reference to the following description and the accompanying drawings, in which: 
         FIG.  1    is a schematic diagram of a storage device sharing system that is applied to a main chip and a plurality of electronic devices according to a first embodiment of the present disclosure; 
         FIG.  2    is a circuit structure diagram of the storage device sharing system according to the first embodiment of the present disclosure; 
         FIG.  3    is a flowchart of a toggle mode according to the first embodiment of the present disclosure; 
         FIG.  4    is a signal timing diagram in the toggle mode according to the first embodiment of the present disclosure; 
         FIG.  5    is a flowchart of an arbitration mode according to the first embodiment of the present disclosure; 
         FIG.  6    is a signal timing diagram in the arbitration mode according to the first embodiment of the present disclosure; 
         FIG.  7    is a circuit diagram of a storage device sharing system according to a second embodiment of the present disclosure; 
         FIG.  8    is a signal timing diagram in the toggle mode according to the second embodiment of the present disclosure. 
     
    
    
     DETAILED DESCRIPTION OF THE EXEMPLARY EMBODIMENTS 
     The present disclosure is more particularly described in the following examples that are intended as illustrative only since numerous modifications and variations therein will be apparent to those skilled in the art. Like numbers in the drawings indicate like components throughout the views. As used in the description herein and throughout the claims that follow, unless the context clearly dictates otherwise, the meaning of “a”, “an”, and “the” includes plural reference, and the meaning of “in” includes “in” and “on”. Titles or subtitles can be used herein for the convenience of a reader, which shall have no influence on the scope of the present disclosure. 
     The terms used herein generally have their ordinary meanings in the art. In the case of conflict, the present document, including any definitions given herein, will prevail. The same thing can be expressed in more than one way. Alternative language and synonyms can be used for any term(s) discussed herein, and no special significance is to be placed upon whether a term is elaborated or discussed herein. A recital of one or more synonyms does not exclude the use of other synonyms. The use of examples anywhere in this specification including examples of any terms is illustrative only, and in no way limits the scope and meaning of the present disclosure or of any exemplified term. Likewise, the present disclosure is not limited to various embodiments given herein. Numbering terms such as “first”, “second” or “third” can be used to describe various components, signals or the like, which are for distinguishing one component/signal from another one only, and are not intended to, nor should be construed to impose any substantive limitations on the components, signals or the like. 
     First Embodiment 
       FIG.  1    is a schematic diagram of a storage device sharing system that is applied to a main chip and a plurality of electronic devices according to a first embodiment of the present disclosure, and  FIG.  2    is a circuit structure diagram of the storage device sharing system according to the first embodiment of the present disclosure. 
     Referring to  FIGS.  1  and  2   , the first embodiment of the present disclosure provides a storage device sharing system  1 , which includes a storage device  10 , a first chip  11  and a second chip  12 . The storage device  10  can be, for example, but not limited to, a non-volatile random-access memory (NVRAM), a flash memory, an electronic erasable rewritable read-only memory (EEPROM) or a one-time programmable read only memory (OTPROM). 
     As shown in  FIG.  1   , the first chip  11  can be connected between an electronic device  01  and a main chip  2 , and the second chip  12  can be connected between an electronic device  02  and the main chip  2 . In some embodiments, the first chip  11  and the second chip  12  can be, for example, but not limited to, a USB Type-C port control chip, or a high definition multimedia interface (HDMI) control chip, and each has an interface for connecting the electronic device  01  and the electronic device  02 , but the present disclosure is not limited thereto. 
     In addition, the storage device  10  stores one or more firmware for realizing the first chip  11  and the second chip  12 . When the first chip  11  and the second chip  12  are configured to perform certain functions, corresponding firmware need to be obtained from the storage device  10 . 
     The first chip  11  is connected to the storage device  10  through a first input/output (I/O) interface  110 , and has a first master-slave determination terminal MS 1  and a first arbitration terminal A 1 . The first I/O interface  110  can be, for example, but not limited to, a serial peripheral interface (SPI), an inter-integrated bus circuit (I2C) interface, a display data channel (DDC) and other communication interfaces. The first chip  11  can include, for example, a controller, a microcontroller, or a processor, which is not only used to communicate with the electronic device  01  and the main chip  2 , but also used to perform the functions mentioned in the following embodiments of the present disclosure. 
     As shown in  FIG.  2   , the first I/O interface  110  that is an SPI interface is taken as an example, the first I/O interface  110  can include pins SCLK 1 , SS 1 , MOSI 1 , and MISO 1 . The pin SCLK 1  is used to transmit a serial clock (SCLK) signal sent by the SPI master, the pin SS 1  is used to transmit a slave select (SS) signal sent by the SPI master, the pin MOSI 1  is used to transmit a master output slave input (MOSI) signal (data is sent by the SPI master), the pin MISO 1  is used to transmit a master input slave output (MISO) signal (data is sent by the SPI slave). 
     In addition, the storage device  10  can be, for example, a memory with an SPI interface. The pins SCLK 1 , SS 1 , MOSI 1 , and MISO 1  can be respectively connected to pins SCLK 0 , SS 0 , MOSI 0 , and MISO 0  of the storage device  10  to transmit the SCLK signal, the SS signal, the MOSI signal and the MISO signal, respectively, so as to access the storage device  10 . 
     On the other hand, the second chip  12  is connected to the storage device  10  through a second I/O interface  120 , and has a second master-slave determination terminal MS 1  and a second arbitration terminal A 2 . Similarly, the second  110  interface  120  that is an SPI interface is taken as an example, the second I/O interface  120  can include pins SCLK 2 , SS 2 , MOSI 2 , and MISO 2 , which are connected to the pins SCLK 0 , SS 0 , MOSI 0 , and MISO 0  of the storage device  10 , respectively. The pin SCLK 2  is used to transmit the SCLK signal, the pin SS 2  is used to transmit the SS signal, the pin MOSI 2  is used to transmit the MOSI signal, and the pin MISO 2  is used to transmit the MISO signal. 
     In this embodiment, the first master-slave determination terminal MS 1 , the first arbitration terminal A 1 , the second master-slave determination terminal MS 2 , and the second arbitration terminal A 2  can be, for example, general-purpose input/output (GPIO) pins. Under an architecture where multiple SPI masters (such as the first chip  11  and the second chip  12 ) share a single SPI slave (such as the storage device  10 ), the first master-slave determination terminal MS 1 , the first arbitration terminal A 1 , the second master-slave determination terminal MS 2  and the second arbitration terminal A 2  are used to implement communications between the multiple SPI masters, so as to control a timing sequence of the multiple SPI masters corresponding to the single SPI slave. 
     As shown in  FIG.  2   , the second arbitration terminal A 2  is connected to the first arbitration terminal A 1  and has an arbitration potential AP that is as the same as a potential of the first arbitration terminal A 1 . The first master-slave determination terminal MS 1  and the second master-slave determination terminal MS 2  are used to define the first chip  11  and the second chip  12  as a master and a slave, respectively. In more detail, the first master-slave determination terminal MS 1  and the second master-slave determination terminal MS 2  are used to define which one of the multiple SPI masters is the most important SPI master (that is, the master), which has the right to control the arbitration potential AP. 
     For example, the one that has the right to control the arbitration potential AP can be directly defined by a pull-up resistor and a pull-down resistor on the circuit board. For example, in  FIG.  2   , the first master-slave determination terminal MS 1  is connected to a first voltage source VDD 1  through a pull-up resistor RH 1 , and the second master-slave determination terminal MS 2  is connected to a ground terminal through a pull-down resistor RL 1 . Therefore, potentials of the first master-slave determination terminal MS 1  and the second master-slave determination terminal MS 2  are used to determine how the first chip  11  and the second chip  12  are allocated as the master and the slave. In the configuration of  FIG.  2   , the first chip  11  is defined as the master, and the second chip  12  is defined as the slave. 
     Furthermore, an initial level of the arbitration potential AP can be set by connecting the first arbitration terminal A 1  and the second arbitration terminal A 2  to the pull-up resistor or the pull-down resistor on the circuit board, and pins of the first arbitration terminal A 1  and the second arbitration terminal A 2  are set to an open-drain mode. Taking  FIG.  2    as an example, the first arbitration terminal A 1  and the second arbitration terminal A 2  can be connected to a second voltage source VDD 2  through a pull-up resistor RH 2 . 
     In the first embodiment of the present disclosure, two control modes are provided, namely an arbitration mode and a toggle mode, and the first chip  11  and the second chip  12  can be dynamically switched into any one of the two modes. 
     The toggle mode will first be described in further detail. In an initialization phase, for example, since all chips need to reload an initialized firmware content from the storage device  10  when the storage device sharing system  1  is turned on, the first chip  11  and the second chip can preferentially enter the toggle mode. Referring to  FIGS.  3  and  4   ,  FIG.  3    is a flowchart of a toggle mode according to the first embodiment of the present disclosure, and  FIG.  4    is a signal timing diagram in the toggle mode according to the first embodiment of the present disclosure. 
     As shown in  FIG.  3   , the toggle mode includes configuring the first chip  11  to perform the following steps: 
     Step S 300 : determining whether or not to communicate with the storage device  10  (that is, to store or read with the storage device  10 ). In the affirmative, the toggle mode proceeds to step S 301 . In the negative, the toggle mode repeats step S 300 . 
     Step S 301 : determining whether a potential of the first master-slave determination terminal MS 1  is a high potential or a low potential. 
     In this embodiment, since the first chip  11  is defined as the master by connecting the first master-slave determination terminal MS 1  to the pull-up resistor RH 1 , if the potential of the first master-slave determination terminal MS 1  is the high potential, it can be confirmed that the first chip  11  is the master, and the toggle mode proceeds to step S 302 : controlling the arbitration potential AP to a first control potential Vc 1  and a second control potential Vc 2  through the first arbitration terminal A 1 . For example, as shown in the arbitration potential AP in  FIG.  4   , the arbitration potential AP is controlled to the first control potential Vc 1  and the second control potential Vc 2  in a period TP. 
     If the potential of the first master-slave determination terminal MS 1  is the low potential, it means that the first chip  11  is defined as the slave, and a process corresponding to the second chip  12  in this embodiment, such as that provided under step S 312 , is executed. 
     Step S 303 : determining whether the arbitration potential AP is the first control potential Vc 1  or the second control potential Vc 2 . 
     In response to determining that the arbitration potential AP is the first control potential Vc 1 , the toggle mode proceeds to step S 304 : communicating with the storage device  10  until the arbitration potential AP is converted from the first control potential Vc 1  to the second control potential Vc 2 . In this step, the first chip  11  operates the SS signal, SCLK signal, MOSI signal, and MISO signal to communicate with the storage device  10 , as shown in  FIG.  4   . 
     In response to determining that the arbitration potential AP is the second control potential Vc 2  in step S 304 , the toggle mode repeats step S 303  until the arbitration potential AP is converted from the second control potential Vc 2  to the first control potential Vc 1 . 
     Further referring to  FIG.  3   , the toggle mode also includes configuring the second chip  12  to perform the following steps: 
     Step S 310 : determining whether to communicate with the storage device  10 . In the affirmative, the toggle mode proceeds to step S 301 . In the negative, the toggle mode repeats step S 310 . 
     Step S 311 : determining whether a potential of the second master-slave determination terminal MS 2  is a high potential or a low potential. 
     In this embodiment, since the second chip  12  is defined as the slave by connecting the second master-slave determination terminal MS 2  to the pull-down resistor RH 2 , if the potential of the second master-slave determination terminal MS 2  is the high potential, it can be confirmed that the second chip  12  is the slave, and the toggle mode proceeds to step S 312 : determining whether the arbitration potential AP is the first control potential Vc 1  or the second control potential Vc 2 . 
     If the potential of the second master-slave determination terminal MS 2  is the high potential, it means that the second chip  12  is defined as the master, and the process corresponding to the first chip  11  in this embodiment is executed, for example, step S 303 . 
     In response to determining that the arbitration potential AP is the second control potential Vc 2 , the toggle mode proceeds to step S 313 : communicating with the storage device  10  until the arbitration potential AP is converted from the second control potential Vc 2  to the first control potential Vc 1 . In response to determining that the arbitration potential AP is the first control potential Vc 1  in step S 312 , the toggle mode repeats step S 312  until the arbitration potential AP is converted from the first control potential Vc 1  to the second control potential Vc 2 . 
     The first chip  11  whose first master-slave determination terminal MS 1  is at the high potential communicates with the storage device  10  when the arbitration potential AP is at the first control potential Vc 1  (low potential), and the second chip  12  whose second master-slave determination terminal MS 2  is at the low potential operates the SS signal, SCLK signal, MOSI signal, and MISO signal to communicate with the storage device  10  in response to the arbitration potential AP being the second control potential Vc 2  (high potential). In addition, in  FIG.  2   , in response to the communication with the storage device  10  being completed, the first chip  11  and the second chip  12  both operate the SS, SCLK, MOSI, and MISO signals to an idle state, as shown by idle times Clk_Idle and SS_Idle in  FIG.  4   . 
     Therefore, the process of the toggle mode is simple, and the first chip  11  and the second chip  12  can communicate with the storage device  10  in an even, time-sharing manner. However, the period TP can be adjusted according to demand, and is not limited to being assigned in fixed and even manners. 
     Details on the arbitration mode will next be described. When a preferential communication event occurs in a chip, it can be switched to the arbitration mode, such that the chip can communicate with the storage device  10  and read the requisite firmware with a higher immediacy. The preferential communication event can be, for example, that the chip detects a connection with the electronic device, or that the chip triggers functions of current and voltage protections. 
     In addition, when the chip has a communication message that needs to be replied or a process with an electronic device that is connected to the chip, the chip can also enter the arbitration mode. For example, when the chip has a USB Type-C port controller function, it may receive different power delivery (PD) requests at any time and necessitate immediate communication with the storage device  10  to obtain the corresponding firmware. 
     Alternatively, when an interrupt event of a microcontroller of the chip is triggered, the chip also enters the arbitration mode. For example, when the chip is a retimer, it may be necessary to enter an interrupt flow for immediate processing due to abnormalities of the transmitted data. 
     Reference is made to  FIGS.  5  and  6   ,  FIG.  5    is a flowchart of an arbitration mode according to the first embodiment of the present disclosure, and  FIG.  6    is a signal timing diagram in the arbitration mode according to the first embodiment of the present disclosure. 
     The first chip  11  and the second chip  12  are respectively configured to perform the following steps: 
     Step S 50 : determining whether a preferential communication event occurs. Whichever one of the first and second chips  11 ,  12  having the preferential communication event enters the arbitration mode. 
     Step S 51 : determining whether the arbitration potential AP is the first arbitration potential AP 1  or the second arbitration potential AP 2 . As shown in  FIG.  6   , due to the pull-up resistor RH 2 , the first arbitration potential AP 1  and the second arbitration potential AP 2  are oppositely high and low potentials, respectively. In this embodiment, the first arbitration potential AP 1  and the aforementioned second control potential Vc 2  are the same potential (high potential), and the second arbitration potential AP 2  and the aforementioned first control potential Vc 1  are the same potential (low potential), but the present disclosure is not limited thereto. 
     In response to the arbitration potential AP being the first arbitration potential AP 1 , the arbitration mode proceeds to step S 52 : adjusting the arbitration potential AP to the second arbitration potential AP 2 , and communicating with the storage device  10 . In response to the arbitration potential AP being the second arbitration potential AP 2 , meaning that other chips may be communicating with the storage device  10 , the arbitration mode repeats step S 52  until the arbitration potential AP is converted to the first arbitration potential AP 1 . 
     In response to the communication with the storage device  10  being completed, the arbitration mode proceeds to step S 53 : adjusting the arbitration potential AP to the first arbitration potential AP 1 . The arbitration mode then returns to step S 50 . 
     In response to determining that the preferential communication event is excluded in step S 50 , the arbitration mode proceeds to step S 54 : configuring the first chip  11  and the second chip  12  to enter the toggle mode. 
     As shown in  FIGS.  5  and  6   , step S 52  can further include: 
     Step S 520 : adjusting the arbitration potential AP to the second arbitration potential AP 2  and waiting for the first predetermined time tAL. 
     Step S 521 : determining whether the arbitration potential AP is the first arbitration potential AP 1  or the second arbitration potential AP 2 . 
     In response to the arbitration potential AP being the second arbitration potential AP 2 , step S 522  is executed: initiating communication with the storage device. Otherwise, step S 520  is returned to. 
     In other words, the arbitration potential AP is operated at the low potential at time t 1 , time t 2  is then reached after the first predetermined time tAL, and then the arbitration potential AP is confirmed again to be at the low potential, the SS signal, SCLK signal, MOSI signal, and MISO signal can then be operated to communicate with the storage device  10 . 
     Step S 53  further includes: 
     Step S 530 : in response to the communication with the storage device  10  being completed, waiting for a second predetermined time tAT. 
     Step S 531 : adjusting the arbitration potential AP to the first arbitration potential AP 1 . 
     In other words, after the communication with the storage device  10  is completed, the SS signal, SCLK signal, MOSI signal, and MISO signal are first operated to the idle state, as shown by time t 3  and idle times Clk_Idle and SS_Idle in  FIG.  6   . Then, the arbitration potential AP is kept at the low potential for a period of time, for example, the second predetermined time tAT, and time t 4  in  FIG.  6    is then reached. 
     The above-mentioned first predetermined time tAL is to prevent multiple SPI masters from simultaneously initiating communication with the SPI slave, and the above-mentioned second predetermined time tAT is to ensure that the SPI slave have stably read the SS, SCLK, MOSI, MISO signals and restored to the idle state, such that other SPI masters can communicate with the SPI slave in the future. Although a control flow of the arbitration mode is more complicated, it allows the chip to communicate with the storage device in the higher immediacy. 
     Second Embodiment 
       FIG.  7    is a circuit diagram of a storage device sharing system according to a second embodiment of the present disclosure. The present embodiment utilizes an architecture that is similar to the first embodiment, and thus repeated descriptions are omitted. 
     The difference between this embodiment and the first embodiment is that the storage device sharing system  1  further includes a third chip  13 , which is connected to the storage device  10  through a third I/O interface  130 , and has a third master-slave determination terminal MS 3  and a third arbitration terminal A 3 . The number of chips in the storage device sharing system  1  is not limited to being three as provided in this embodiment, and can be increased and applied according to the method of this embodiment. 
     The third arbitration terminal A 3  is connected to the first arbitration terminal A 1  and the second arbitration terminal A 2 , and also has the arbitration potential AP. In contrast to the first chip  11  and the second chip  12  being defined as the master and the slave, the third master-slave determination terminal MS 3  is similarly used to define the third chip  13  as another slave. The third I/O interface  130  can include pins SCLK 3 , SS 3 , MOSI 3 , and MISO 3 , that are respectively connected to the pins SCLK 0 , SS 0 , MOSI 0 , and MISO 0  of the storage device  10  and used to transmit signals such as the SCLK, SS, MOSI, and MISO signals. 
     In this embodiment, the SPI master that acts as the master (i.e., the first chip  11 ) needs to replace the first arbitration terminal A 1  with a voltage control circuit  111  from the GPIO of the previous embodiment, so as to output multi-level voltages by acting as an arbitration potential generator, and to conveniently determine, by three phases in the toggle mode, lengths of time during which the first chip  11 , the second chip  12 , and the third chip  13  can access the storage device  10 . 
     In this embodiment, the first chip  11 , the second chip  12 , and the third chip  13  can use the same process as the first embodiment to execute the arbitration mode, the details of which are not repeated here. The SPI slaves that act as the slaves (i.e., the second chip  12  and the third chip  13 ) need to replace the second arbitration terminal A 2  and the third arbitration terminal A 3  from the GPIO of the previous embodiment with signal converters  121  and  131 , e.g., analog-to-digital converters, which are capable of reading three-stage (or multi-stage) potentials. 
     It should be noted that the toggle mode is different from the first embodiment. The following is based on  FIG.  3    and the differences are explained with reference to  FIG.  8   .  FIG.  8    is a signal timing diagram in the toggle mode according to the second embodiment of the present disclosure. As in step S 302 , the difference is that the first chip  11  further controls the arbitration potential AP to the first control potential Vc 1 , the second control potential Vc 2 , and the third control potential Vc 3  through the aforementioned voltage control circuit and the first arbitration terminal. 
     The difference from step S 303  is that the first chip  11  is configured to determine whether the arbitration potential AP is the first control potential Vc 1 , the second control potential Vc 2 , or the third control potential Vc 3 . 
     In response to determining that the arbitration potential AP is the first control potential Vc 1 , the first chip  11  communicates with the storage device  10 . If the arbitration potential AP is the second control potential Vc 2  or the third control potential Vc 3 , then the first chip  11  waits until the arbitration potential AP is converted to the first control potential Vc 1 , as shown by a signal timing of the pin MOSI 1  in  FIG.  8   . 
     For the second chip  12 , the difference is that in step S 312 , the second chip  12  determines whether the arbitration potential AP is the first control potential Vc 1 , the second control potential Vc 2 , or the third control potential Vc 3  through the signal converter  121 . In response to determining that the arbitration potential AP is the second control potential Vc 2 , the second chip  12  communicates with the storage device  10 . If the arbitration potential AP is the first control potential Vc 1  or the third control potential Vc 3 , the second chip  12  waits until the arbitration potential AP is converted to the second control potential Vc 2 , as shown by a signal timing of the pin MOSI 2  in  FIG.  8   . 
     Similar to the second chip  12 , the third chip  13  uses the signal converter  131  to determine whether the arbitration potential AP is the first control potential Vc 1 , the second control potential Vc 2 , or the third control potential Vc 3 . In response to determining that the arbitration potential AP is the third control potential Vc 3 , the third chip  13  communicates with the storage device  10 . If the arbitration potential AP is the first control potential Vc 1  or the second control potential Vc 2 , the third chip  13  waits until the arbitration potential AP is converted to the third control potential Vc 3 , as shown by a signal timing of the pin MOSI 3  in  FIG.  8   . 
     Beneficial Effects of the Embodiments 
     In conclusion, in the storage device sharing system and storage device sharing method provided by the present disclosure, a structure that multiple chips share a single storage device is utilized, and since the number of storage devices used is small, power consumption and circuit board usage area can be reduced, thereby reducing costs. 
     In addition, the storage device sharing system and storage device sharing method provided by the present disclosure are applicable to various existing storage devices and various communication interfaces, have a wide application range and provide high flexibility. 
     The foregoing description of the exemplary embodiments of the disclosure has been presented only for the purposes of illustration and description and is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. Many modifications and variations are possible in light of the above teaching. 
     The embodiments were chosen and described in order to explain the principles of the disclosure and their practical application so as to enable others skilled in the art to utilize the disclosure and various embodiments and with various modifications as are suited to the particular use contemplated. Alternative embodiments will become apparent to those skilled in the art to which the present disclosure pertains without departing from its spirit and scope.