Patent Publication Number: US-9430287-B2

Title: Cache performance prediction and scheduling on commodity processors with shared caches

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This application is a Continuation of and claims benefit of U.S. patent application Ser. No. 13/853,734, incorporated herein by reference in its entirety, which was filed on Mar. 29, 2013, which is a Continuation of and claims benefit of U.S. patent application Ser. No. 12/727,705, which was filed on Mar. 19, 2010 and subsequently issued as U.S. Pat. No. 8,429,665, has common title with the present application, and is incorporated herein by reference in its entirety. 
     This application has subject matter that is related to that disclosed in U.S. patent application Ser. No. 12/251,108, filed on Oct. 14, 2008 and Ser. No. 12/550,193, filed on Aug. 28, 2009, each of which is incorporated herein by reference in its entirety, and each of which were incorporated by reference in their entirety in U.S. patent application Ser. No. 13/853,734 and U.S. patent application Ser. No. 12/727,705. 
    
    
     BACKGROUND 
     Modern symmetric microprocessor systems (SMP) incorporate multiple processor cores sharing a last-level memory cache (LLC). A cache is a high-speed data storage area adjacent the processor core for storing a copy of recently accessed or frequently accessed data that is stored in the main memory system of a computer. The term “processor core” is used herein to indicate an execution engine that may coexist with other processor cores on a single die. In modern multi-core processors, each core often has one or two levels of its own cache, and shares a second- or third-level cache (the LLC) with one or more other cores on the same die. However, there are also processors with multiple cores on separate dies that share an LLC on the main mother board or within a processor package. Having more than one core allows for more than one thread to execute simultaneously on a single computer system (and not just time-wise interleaved). 
     When a thread that is executing on one core of a processor fetches data, it first checks local cache to see if the data is already present in the cache. When there are multiple levels of cache, the checks percolate through to the LLC if the earlier caches do not have the requested data. If the requested data is not in the LLC (an LLC “cache miss”) then the data is fetched from main memory, and a line is evicted from the LLC so that the newly-fetched data can be made available in the LLC in case it is needed again. When the LLC is shared by a plurality of processor cores, the data that was evicted was placed there by the same thread whose memory request resulted in the eviction, or by a different thread, possibly running on a different core. As a result, the execution of one thread on one core can adversely affect the execution of other threads running on the same or other cores that share the same LLC. 
     CPU resources are generally allocated to a plurality of concurrently running threads that may execute interleaved on a single core or simultaneously on a plurality of different cores, or both. There are many existing scheduling algorithms in use, which generally attempt to provide some “fair” distribution of processor resources to each of the executing threads. In some cases, a CPU scheduling algorithm may take into consideration a “proportional share” of the scheduling resources, such that some processes are granted a greater than even share of processor resources. In a proportional fair scheduling policy, for example, a first thread may be given a proportional share of 800, and a second thread given a proportional share of 400, so that the ratio between the two is 2:1, and the first thread is given twice the resources (i.e., CPU execution time) as the second. 
     Contention for LLC and other microarchitectural resources can adversely impact the fair distribution of processor resources among threads, making the distribution less fair. Microarchitecture refers to a physical implementation of an instruction set architecture in a computer system. Microarchitectural resources include the physical resources such as the cache, memory interconnects, and functional units. Contention for these resources result in delays in useful execution by one thread imposed by another thread. For example, because the execution of a first thread on a first core can interfere with data stored in the LLC that is shared with a second thread, and because a cache miss imparts a significant penalty in terms of the time it takes to fetch the data from the main memory, the presence of a shared LLC can result in delays in execution to the second thread caused by the first thread. 
     Further complexity is added to scheduling decisions when a computer has multiple processor “sockets” or “dies.” (The term, “die” or “chip” refers to a single, typically silicon-based integrated circuit, whereas “processor” generally refers to a processor package that is typically removably mounted to a “socket” on a computer motherboard, such that there is a one-to-one relationship between processors and sockets, although a single package can contain multiple dies or chips.) Herein, the term “processor” or “central processing unit” (“CPU”) will refer to a die, chip, package, or socket having multiple processing cores that share an LLC. Threads may be transferred from the one processor to the other and between cores of a single processor. The decision of which thread to transfer between processors should be made intelligently, based on expected behavior of the thread and its impact on microarchitectural resources, including the LLC of each processor. 
     SUMMARY 
     A computer implemented method to manage thread performance in a computing environment is provided. The method includes assigning a thread performance counter to threads being created in the computing environment. The thread performance counter measures a number of cache misses for a corresponding thread. The method also includes calculating a self-thread value S as a change in the thread performance counter of a given thread during a predetermined period. The method further includes calculating an other-thread value O as a sum of changes in all the thread performance counters during the predetermined period minus S. The method also includes calculating a first estimation adjustment value associated with a first probability that a second set of cache misses for the corresponding thread replace a cache area currently occupied by the corresponding thread. The method further includes estimating a cache occupancy for the given thread based on a previous occupancy E for the given thread, S, O, and the first estimation adjustment value. The method also includes assigning computing environment resources to the given thread based on the estimated cache occupancy. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1A  shows the process flow for the Exponential Equation method for calculating cache occupancy, in accordance with one embodiment. 
         FIG. 1B  shows the process flow for the Linear Approximation method for calculating cache occupancy, according to one embodiment. 
         FIG. 1C  shows a schematic block diagram of a virtualized computer system having a CPU scheduler. 
         FIG. 2  shows a schematic block diagram of a computer system having a traditional operating system with a CPU scheduler. 
         FIG. 3  shows pseudocode representing an algorithm that produces a predicted occupancy of a plurality of threads, given an initial occupancy, a miss rate curve for each thread, and a known size of the LLC. 
         FIG. 4  shows a flowchart illustrating by way of example a procedure representing a more general view of the algorithm shown in  FIG. 3 . 
         FIG. 5  shows a graph illustrating test data comparing predicted verses actual occupancies for a variety of thread parings running on a dual core processor. 
         FIG. 6  shows a flowchart illustrating by way of example a procedure for pairing one or more threads to a particular core such that threads are scheduled based on predicted occupancies using the cache divvying algorithm previously described. 
     
    
    
     DETAILED DESCRIPTION 
     Threads behave differently, requiring differing amounts of architectural resources, depending on the task they are performing and how they were programmed to complete that task. For example, U.S. patent application Ser. No. 12/251,108, filed Oct. 14, 2008 (“the &#39;108 application) describes how one can calculate a characteristic miss-rate curve (MRC) for each thread. The MRC represents expected cache miss rates (misses per cycle or unit of time) of a particular thread at different cache occupancies. In general, as cache occupancy increases, the miss-rate is reduced, but the relationship between cache occupancy and miss-rate can vary from one thread to another and between phases of execution of a single thread. That is, as the task being carried out by a particular thread changes or progresses, the miss-rate curve may change over time for that particular thread. Despite this dynamic behavior, historical behavior of a particular thread can be used (as described in the &#39;108 application) to produce the MRC for that thread, which has predictive value as its cache occupancy varies. 
     It is also possible to generate miss ratio curves (as opposed to miss rate curves) which express misses per instruction. Miss ratio curves express miss rate in relation to cache occupancy in a manner that is not sensitive to variations in instructions per cycle caused by certain types of microarchitectural contention, such as memory interconnect congestion. A miss-rate curve (misses per cycle) can be converted to a miss ratio (misses per instruction) curve by multiplying each datapoint by the cycles per instruction at the corresponding cache occupancy. Since the number of cycles per instruction depends on, among other things, microarchitectural factors, the cycles per instruction can vary as a function of cache occupancy. The cycles per instruction value can be determined using hardware performance counters and the system clock. In one embodiment, a miss-rate curve is obtained from a miss ratio curve by considering “ideal” instructions per cycle at a point of least resource contention (i.e., by observing the value at full cache occupancy.) Discussion of the ideal instructions per cycle is provided in Ser. No. 12/550,193 filed Aug. 28, 2009 and entitled, “Thread Compensation for Microarchitectural Contention,” (“the 193 application”), incorporated herein by reference. 
     The following describes an embodiment of a method to estimate the cache occupancy of threads. To describe the rationale behind the equations used in the different embodiments, a simple “balls in bins” model is used for easier understanding of how the different formulas described below apply to the cache occupancy determination specifically, and how they apply to the estimation of resource use in a computing environment in general. In one embodiment, a shared last-level cache is used, while other types of caches are used in other embodiments of the invention. The shared last-level cache may be n-way set associative or direct-mapped. The method estimates the current cache occupancy by a thread τ at a time t, given the contention for cache lines by multiple threads running on all the cores that share the LLC. At any given time t, a thread τ may be active on one core while other threads are active on the remaining cores, or thread τ may be de-scheduled. 
     In general, today&#39;s hardware caches reveal little information for the purpose of deriving spatial or quantitative information about cache usage. In one embodiment, hardware performance counters are used together with inference techniques to estimate cache usage. Virtually all modern processors provide performance counters through which information about various system events can be determined, such as instructions retired, cache misses, cache evictions and cycle times for execution sequences. Using two events, namely the local and global last-level cache misses, an estimate of the number of cache lines C i (t) occupied by thread τ i  at time t is derived. The global cache misses value is defined as the cumulative number of cache misses across all cores that share the same last-level cache. 
     In one embodiment, two assumptions for estimating cache occupancy are used. First, the cache is accessed uniformly at random. Second, the method relies on direct-mapped caches (i.e., hash structures). Other embodiments described below expand the method to dismiss the second assumption. The first assumption does not apply in most cases because of the locality properties of most typical threads, resulting in heavy-tailed distributions of cache access patterns. Notwithstanding, in the absence of spatial knowledge about the precise subset of “hot” cache lines for a thread&#39;s current phase of execution, assuming a uniformly random distribution of cache accesses suffices for the model described below. 
     Cache occupancy is, to a certain degree, dictated by the number of misses experienced by a thread because cache lines will be allocated in response to such misses either by pre-fetching or demand-fetching. Essentially, the current execution phase of a thread influences the thread&#39;s cache investment, because typical eviction policies tend to favor evicting lines not used for some time, such as a pseudo Least-Recently Used (LRU) replacement policy. Pseudo LRU is an efficient algorithm for finding an item that most likely has not been accessed very recently, given a set of items and a sequence of access events to the items. In one embodiment, the underlying architecture tracks the “least recently used” information for a pair of cache lines instead of tracking just a single cache line. After the least recently used cache line pair is selected, one cache line within the pair is selected randomly. This method accomplishes close-to-exact LRU behavior with lower hardware complexity. Any evicted lines no longer relevant to the current execution phase of τ i , will not be returned to the cache due to subsequent misses. Hence, the cache occupancy of a thread is a function of cache misses experienced by it over a time interval. 
     Returning to the “balls in bins” analogy, a few terms used in the model are introduced below:
         C uniformly random accessed cache lines are represented by bins. In a set-associative cache, the value C represents the sets of hashed cache lines.   σ r  represents the number of red balls. This term corresponds to the number of misses, hereinto referred as S, experienced by a chosen thread τ r  under observation, and represents the number of cache lines (or bins) allocated to thread τ r  due to misses.   σ b  represents the number of blue balls. This term corresponds to the number of misses, herein referred to as O, by each and every thread τ b  other than τ r , ∀b≠r. The misses occur on all cores of a multi-core processor which cause cache lines (and, hence, bins) to be allocated in response to such misses.   Each bin is infinitely deep and one ball wide, so only the top ball is visible when looking into the bin.       

     If there are C bins and σ r  red balls thrown at random, then the first question is “how many unique bins contain red balls after all balls are thrown?” Let Z i  represent a Bernoulli random variable whose value is 1 if a bin is occupied by a red ball and 0 otherwise. The expected number of bins with red balls, denoted E[Z] or simply E, equals Σ i=1   N E[Z i ]. This assumes that the expectation of each Bernoulli random variable is independent of all other random variables, which is the case if σ r  is sufficiently large. It should be noted that, if σ r  is sufficiently small, the probability that a given bin is occupied will approach 0 if all balls have been thrown into different bins. Over the lifetime of a system executing threads, misses will continue to occur and, by analogy, balls will be essentially limitless. 
     E[Z i ] is the probability that bin i is occupied by a red ball, which is the same as [1−Pr{bin i is empty}]. However, Pr{bin i is empty} is equal to 
               (     1   -     1   C       )       σ   r           
after σ r  independent balls are thrown. Therefore,
 
               E   ⁡     [     Z   i     ]       =     1   -         (     1   -     1   C       )       σ   r       .             
Consequently,
 
             E   =     C   ⁡     (     1   -       (     1   -     1   C       )       σ   r         )             
which approximates to
 
     
       
         
           
             
               C 
               ⁡ 
               
                 ( 
                 
                   1 
                   - 
                   
                     ⅇ 
                     
                       - 
                       
                         
                           σ 
                           r 
                         
                         C 
                       
                     
                   
                 
                 ) 
               
             
             . 
           
         
       
     
     Intuitively, the value of E grows from 0 to the maximum number of bins (or cache capacity), with exponentially more balls (or misses) needed to fill additional bins (or cache lines) as the current occupancy increases. This makes sense, because as more bins are occupied, there is a greater probability that a ball will land in an already occupied bin. 
     When a thread, whose cache misses are represented by red balls σ r , is de-scheduled then other threads may run, and the misses will cause evictions of red balls from bins. Similarly, on multi-core architectures with a shared cache, concurrent threads on other cores will be competing for bins (or cache lines) at the same time as thread τ r  under observation. For simplicity, the method corresponding to one embodiment is described for two cores with a shared cache. However, the method generalizes to a system with M cores sharing a given cache. The blue balls represent all misses from each and every thread, τ b |b≠r. Thread τ b  executes on a second core during the concurrent execution of τ r  on the first core. This scenario corresponds to the “balls in bins” problem with two ball colors, red and blue, and the problem is finding out how many bins have visible red balls when a finite sequence of red and blue balls have been thrown at random into C bins. 
     Each time a blue ball lands in a bin previously occupied by a red ball, the top visible ball is blue. This corresponds to the case where a cache line for τ r  is evicted to make way for some thread, τ b . Self collisions are also possible, causing multiple balls of the same color to land in the same bin, but only the top ball is visible. Given the probability of any two balls landing in the same bin, the probability of the top-most ball being red or blue is simply dependent on the ratio of red to blue balls. That is, to determine the number of bins with visible red balls, the expected occupancy by red balls E is calculated. E is equal to 
                   σ   r         σ   r     +     σ   b         ⁢     E   ⁡     [     Z   ′     ]         ,         
where E[Z′] is the expected number of bins occupied by either red or blue balls. When only red balls are thrown, the expected occupancy is
 
               C   ⁡     (     1   -     ⅇ     -       σ   r     C           )       ,         
therefore
 
               E   ⁡     [     Z   ′     ]       =       C   ⁡     (     1   -     ⅇ     -         σ   r     +     σ   b       C           )       .           
Consequently, the expected occupancy of red balls, after σ r +σ b  balls have been thrown is:
 
     
       
         
           
             
               
                 
                   E 
                   = 
                   
                     
                       
                         σ 
                         r 
                       
                       
                         
                           σ 
                           r 
                         
                         + 
                         
                           σ 
                           b 
                         
                       
                     
                     ⁢ 
                     
                       C 
                       ⁡ 
                       
                         ( 
                         
                           1 
                           - 
                           
                             ⅇ 
                             
                               - 
                               
                                 
                                   
                                     σ 
                                     r 
                                   
                                   + 
                                   
                                     σ 
                                     b 
                                   
                                 
                                 C 
                               
                             
                           
                         
                         ) 
                       
                     
                   
                 
               
               
                 
                   ( 
                   
                     Eq 
                     . 
                     
                         
                     
                     ⁢ 
                     A 
                   
                   ) 
                 
               
             
           
         
       
     
     If the rate of misses by threads on both cores is the same, such that σ r =σ b , then the expected cache occupancy of τ r  approaches 50 percent of the cache capacity (i.e., C/2). If every independent thread is represented by its own ball color, then the cache occupancy of each thread would approach C/c, where c represents the number of unique ball colors. 
     As noted herein, any computer architecture can be used as long as the cores share a memory cache. For purposes of example only, when using an architecture such as Intel Core® architecture, the number of misses experienced by τ r  is tracked for any specific interval of clock cycles, where τ r  is a thread whose cache occupancy is to be determined. In a system with two cores, the Intel performance counter event that represents local core misses in the L2 cache is L2_LINES_IN (with a mask setting set to the local core). By changing the event mask, L2_LINES_IN captures cache miss events on both cores. Hence, L2_LINES_IN (local) is representative of S, while L2_LINES_IN (both) is representative of S+O (i.e., the total misses across a pair of cores by τ r  and all other threads τ b ). 
       FIG. 1A  shows the process flow  10  for the Exponential Equation method  12  for calculating cache occupancy, in accordance with one embodiment. In operation  14 , the sampling interval is set. The number of misses S by the thread under observation is read in operation  16 , and the number of cache misses by all threads except for the thread under observation, O, is read in operation  18 . 
     The total number of misses, M, is calculated  20  by adding S+O. In another embodiment, M is read from a global counter, and then O is calculated as (M−S). In operation  22 , the ratio of self misses f is calculated by the fraction S/M. Similarly, the global miss ratio g is calculated  24  as M/C. In operation  26 , the new occupancy E′ of the thread under observation is calculated, based on the previous occupancy E, as fC(1−e −g )+e −g E. 
       FIG. 1B  shows the process flow  50  for the Linear Approximation method  52  for calculating cache occupancy, according to one embodiment. When using cache occupancy estimates for CPU scheduling, the calculation of E as defined in Equation (A) for each τ r  under observation can be inefficient to compute, in terms of cpu and memory resources. Additionally, Equation (A) is based on the assumption that the shared cache starts out empty. If E′ is the expected occupancy after a number of misses, a numerical solution based on the misses that occur since the previous estimate of cache occupancy E can be derived. Specifically, the newly expected cache occupancy of τ r  after generating σ r  misses in a predetermined interval, δ t , during which all other threads generate σ b  misses is: 
     
       
         
           
             
               
                 
                   
                     E 
                     ′ 
                   
                   = 
                   
                     
                       
                         
                           σ 
                           r 
                         
                         
                           
                             σ 
                             r 
                           
                           + 
                           
                             σ 
                             b 
                           
                         
                       
                       ⁢ 
                       
                         C 
                         ⁡ 
                         
                           ( 
                           
                             1 
                             - 
                             
                               ⅇ 
                               
                                 - 
                                 
                                   
                                     
                                       σ 
                                       r 
                                     
                                     + 
                                     
                                       σ 
                                       b 
                                     
                                   
                                   C 
                                 
                               
                             
                           
                           ) 
                         
                       
                     
                     + 
                     
                       
                         ⅇ 
                         
                           - 
                           
                             
                               
                                 σ 
                                 r 
                               
                               + 
                               
                                 σ 
                                 b 
                               
                             
                             C 
                           
                         
                       
                       ⁢ 
                       E 
                     
                   
                 
               
               
                 
                   ( 
                   
                     Eq 
                     . 
                     
                         
                     
                     ⁢ 
                     B 
                   
                   ) 
                 
               
             
           
         
       
     
     Using terms related to the cache performance instead to “balls in bins” terms, Equation (B) can be rewritten as: 
     
       
         
           
             
               
                 
                   
                     E 
                     ′ 
                   
                   = 
                   
                     
                       
                         S 
                         
                           S 
                           + 
                           O 
                         
                       
                       ⁢ 
                       
                         C 
                         ⁡ 
                         
                           ( 
                           
                             1 
                             - 
                             
                               ⅇ 
                               
                                 - 
                                 
                                   
                                     S 
                                     + 
                                     O 
                                   
                                   C 
                                 
                               
                             
                           
                           ) 
                         
                       
                     
                     + 
                     
                       
                         ⅇ 
                         
                           - 
                           
                             
                               S 
                               + 
                               O 
                             
                             C 
                           
                         
                       
                       ⁢ 
                       E 
                     
                   
                 
               
               
                 
                   ( 
                   
                     Eq 
                     . 
                     
                         
                     
                     ⁢ 
                     
                       B 
                       ′ 
                     
                   
                   ) 
                 
               
             
           
         
       
     
     The difference between Equations (A) and (B) is the addition of the last term in Equation (B) capturing the fraction of the previous occupancy unaffected by the latest set of misses. To approximate exponential occupancy curves (A) and (B), a piecewise-linear model is presented. The linear model approximates the expected occupancy of τ r  as follows:
 
 E′=E +(1−ε) S−εO   (Eq. C)
 
     In Equation (C), ε represents the fraction of the total cache lines currently expected to be occupied by τ r . That is, 
             ɛ   =       E   C     .           
While the exponential Equations are more precise, the piecewise-linear approximation can be evaluated more efficiently, making the linear approximation more practical for dynamic, online computations in critical code paths, such as the CPU scheduler for an operating system kernel or hypervisor.
 
     In one embodiment, Equation (C) is rewritten to facilitate maintaining cache occupancy estimates via incremental updates. In this method, occupancies are represented as fractions of the cache size C. Dividing Equation (C) throughout by C the following is obtained: 
     
       
         
           
             
               
                 E 
                 ′ 
               
               C 
             
             = 
             
               
                 E 
                 C 
               
               + 
               
                 
                   ( 
                   
                     1 
                     - 
                     ɛ 
                   
                   ) 
                 
                 ⁢ 
                 
                   S 
                   C 
                 
               
               - 
               
                 ɛ 
                 ⁢ 
                 
                   O 
                   C 
                 
               
             
           
         
       
     
     Which is equivalent to:
 
 e ′=ε+(1−ε)* s−ε*t   (Eq. D)
 
     Where e′=E′/C, s=S/C, and t=O/C. Equation (D) is sensitive to the values of s and t. For large values of s and t, the linear model becomes less accurate, since the occupancy update is more coarse-grained. One approach for improving accuracy is to perform several fine-grained updates instead of a single coarse-grained update. In one embodiment, N separate updates are performed, using s/N and t/N for each. Another embodiment avoids the overhead of multiple updates and is particularly useful when S+O&gt;kC, where k is a predetermined constant. In one embodiment, k is equal to three, but other values are also possible. The method uses scaled cache miss values, normalized by (S+O), that is, S/(S+O) and O/(S+O), instead of the raw values of S and O. In one embodiment, both of these improvements are used contemporaneously. 
     One embodiment for estimating occupancy using the linear approximation method is described in  FIG. 1B . The method  52  begins by determining a sample interval in operation  54 . Similar to what is performed in the exponential model of  FIG. 1A , the number of cache misses S and the number of misses by other threads O are read in operations  56  and  58 . In operation  60 , the occupancy ratio ε is calculated as the fraction E/C. 
     The linear model is not accurate when S/C or O/C is bigger than a predetermined value. In one embodiment, the predetermined value is ⅛, but other values are also possible. For example, if C is 64,000, then any value of S smaller than 8,000 will cause a ratio of S/C of less than ⅛ and the linear approximation method is considered accurate. The S/C ratio is checked in operation  62 , and if S/C or O/C is not smaller than this threshold value, then the method continues onto operation  64  to use incremental updates, as previously described with respect to Equation (D). Otherwise the method continues onto operation  66 . 
     Another embodiment does not combine the linear method with incremental updates and operation  62  is not performed, where the method flows directly from operation  60  to  66 . In operation  66 , the new occupancy E′ is calculated applying Equation (C) as previously described. 
     Another behavior characteristic of threads is referred to herein as “cache pressure,” which is the tendency of a particular thread at a particular occupancy to increase its share of the LLC. Cache pressure may be expressed mathematically as:
 
 P =(1− E/C )· M   O   (Eq. 1)
 
     where for a particular thread, E is the current LLC occupancy expressed as a number of cache lines occupied, C is the total number of cache lines in the LLC, and M O  is the miss-rate of the thread at the current occupancy E. 
     Calculating a thread&#39;s cache pressure requires the occupancy E and miss-rate M O . These values may be calculated as described in the &#39;108 application and the 193 application both of which are incorporated herein by reference. 
     In brief, occupancy of each thread is estimated according to Equation 2:
 
 E′=E +(1− E/C )· S−E/C·O   (Eq. 2)
 
     where E′ is an updated occupancy for a particular thread, E is the previous occupancy for that thread, C is the number of cache lines in the LLC, S is the number of misses caused by the particular thread, and O is the number of misses caused by other threads. 
     In Equation 2, the occupancy estimation assumes a random cache line replacement, rather than the more typical least recently used (LRU) cache line replacement scheme. It should be noted that there are a number of algorithms for LRU cache line replacement, but in general they tend to target for replacement cache lines that are the least recently accessed. Since different programs behave differently, the LRU cache line replacement scheme can impact relative cache occupancies to a significant degree in a scenario where two programs share an LLC and one of the two programs repeatedly accesses a current set of data that resides in the cache (i.e., high level of cache reuse) while the other program does not access the same data over and over, 
     To adjust the estimated LLC occupancies, Equation 2 can be modified as:
 
 E′=E ·(1− O·p 1)+( C−E )· S·p 2  (Eq. 3)
 
where:
 
 p 1=1/[ E +( r/R )·( C−E )]  (Eq. 4)
 
and
 
 p 2=1/[( R/r )· E +( C−E )]  (Eq. 5)
 
in which:
 
 r =( h+S )/ E   (Eq. 6)
 
and
 
 R =( H+O )/( C−E )  (Eq. 7)
 
     where h is the number of cache hits by the current thread since the previous occupancy calculation and H is the number of cache hits by other threads since the previous calculation. The values h and H can be determined using performance counters in the same manner that cache misses S and O are determined. The values r and R represent the intensity of cache reuse by the current and other threads, respectively. The value p1 denotes the probability that a miss falls on a line that belongs to the current thread, and p2 denotes the probability that a miss falls on a line that belongs to other threads. When there is random replacement, p2 is assumed to be the same as p1, which reduces Equation 3 to Equation 2. Equations 4-7 are designed to estimate p1 and p2 while taking into account effects of the LRU cache line replacement scheme. 
     While Equations A-D, 2, and 3 above represent different methods for estimating cache occupancy, other methods may be used that are consistent with the cache line replacement algorithm implemented by the processor. In addition, it should be understood that Equations A-D, 2, and 3 represent estimates of cache occupancy, not actual cache occupancies. 
     In one embodiment, the cache occupancy estimate for the currently-running thread on each core is updated every two milliseconds using Equation 2. A high-precision timer callback reads hardware performance counters to obtain the number of LLC cache misses for both the local core and the LLC as a whole since the last update. In addition to this periodic update, occupancy estimates may also be updated whenever a thread is rescheduled, based on the number of intervening cache misses since it last ran. 
     Using an MRC constructed from previous observations of thread execution, the miss rate for E′ can be determined as M(E′). MRCs may be generated based on passive monitoring, wherein the miss rate observations are plotted as they occur. It is also possible to actively perturb the execution of co-running threads to alter their relative cache occupancies temporarily, to obtain a full MRC. Varying the group of co-running threads scheduled with a particular thread typically causes the particular thread to visit a wider range of occupancy points. In one embodiment, the execution of some cores may be dynamically throttled, allowing threads on other cores to increase their occupancies. This may be achieved in some processor architectures using duty-cycle modulation techniques to slow down specific cores dynamically. For example, processors available from Intel Corporation of Santa Clara, Calif. allow system code to specify a multiplier (in discrete units of 12.5%) specifying the fraction of regular cycles during which a core should be halted for the purpose of thermal management. When a core is slowed down, its co-runners (i.e., other cores on the same processor) have an opportunity to increase their occupancy of the LLC, while the occupancy of the thread running on the throttled core is decreased. To limit any potential performance impact, in one embodiment, duty cycle modulation is enabled during less than 2% of execution time, which results in only negligible performance impact caused by cache performance curve generation with duty-cycle modulation. 
     In one embodiment, occupancy is tracked by quantizing in discrete units equal to one-eighth of the total cache size, and discrete curves are constructed to bound the space and time complexity of curve generation, while providing sufficient accuracy to be useful in cache-aware CPU scheduling enhancements. 
     At equilibrium occupancies, the cache pressure exerted by co-running threads are either equal or zero. If the cache pressures are not equal, then the thread with the highest cache pressure increases its cache occupancy. When multiple threads share a cache, the occupancies tend to fluctuate around values at which their cache pressures are equal, i.e., the equilibrium cache pressure. That is, while at a particular occupancy, different threads may exhibit different cache pressures, whereas at the equilibrium occupancy, which varies from one thread to another, the cache pressures of co-running threads will be the same. The term, “equilibrium” should not be construed as necessarily being some quiescent balance between the individual threads. In tests, in most cases, co-running threads do not actually converge at such equilibrium occupancies, but instead cycle through a series of occupancies with oscillating cache pressures. However the fluctuations of the occupancies will be around values at which the cache pressures are equal. 
     Because different threads have different operating characteristics and therefore place differing demands or system resources, and in particular the LLC, it is helpful when making scheduling decisions, or to improve the overall performance of the system, to run a particular thread with a particular core in a manner that complements other threads running on the same processor that consequently share the same LLC. 
       FIG. 1C  shows a virtualized computer system  100 . Computer system  100  includes a hardware system  110  having one or more physical central processing units (PCPUs)  120 ,  130 , each having a plurality of cores. PCPU  120  has a first core  122  and a second core  123 , with several levels of cache, including a last-level cache (LLC)  125 , which is shared between cores  122 , 123  of PCPU  120 . Although the example system shown in  FIG. 1C  represents the LLC as being a level 3 (L3) cache, it should be noted that in some processor architectures, the L2 cache is the last level shared cache. PCPU  130  likewise has a plurality of processor cores and a shared LLC  135 . PCPUs  120 ,  130 , are connected to a main memory system  140  via a memory interconnect  145 . Main memory  140  may comprise a system of memories, including volatile and nonvolatile memory, and can include uniform or non-uniform memory accesses (NUMA); the term “memory interconnect” referring to any communication paths for accessing memory. 
     System hardware  110  will include many components aside from those specifically mentioned here, and such omissions are for the purpose of not obscuring the most relevant elements of system  100  and should therefore not be construed as being limiting in any way. For example, PCPUs  120 ,  130 , main memory  140 , and memory interconnect  145 , may be just one node in a system with additional nodes (not shown) forming a non-uniform memory access (NUMA) based architecture. NUMA architecture is well known in the field of computer science. In such systems, a plurality of nodes each having one or more processors, local memory, and local input/output channels, are connected together so that they can read each other&#39;s memory and update each other&#39;s cache to ensure cache-coherency. NUMA architecture is referred to as “non-uniform” because it takes less time for an intra-node memory access (i.e., a processor accessing local memory) than it takes for an inter-node memory access (i.e., a processor accessing a remote memory). 
     In the example presented by system  100 , virtualization software  150  is executing on system hardware  110 , as shown conceptually in the diagram of  FIG. 1C . Of course, virtualization software  150  may reside in main memory  140  and be executed by one or both PCPUs  120 ,  130 , but is shown conceptually in  FIG. 1C  as running “on top of” system hardware  110 . Virtualization software  150  may comprise a plurality of software layers including a kernel  152 , which manages the hardware resources of system hardware  110 , and an instance of a virtual machine monitor (VMM, not shown) for each virtual machine (VM), which emulates hardware resources for the virtual machines. Kernel  152  includes CPU scheduler  155  for prioritizing and dispatching execution threads to cores  122 ,  123 , etc. Virtualization software  150  enables execution of a plurality of virtual machines  160 ,  170 , etc., in a well-understood manner. 
     Each virtual machine  160 ,  170  is an abstraction of a physical computer system, having virtual hardware including one or more virtual central processor units (VCPUs)  165 ,  175  each having one or more virtual cores (“VCORE”)  166 ,  168 ,  176 , etc. In addition, each VM includes guest system software  164 ,  174 , which includes a guest operating system and any number of applications. The guest operating system (OS) may be a commodity operating system such as Windows®, Linux®, etc., or a specialized “para-virtualized”) operating system. In either case, the guest operating system includes a kernel (not shown) that, among other tasks, assigns processes, such as ones associated with the guest applications, to the virtual cores of VCPUs that are conceptually part of that virtual machine but are implemented by virtualization software  150 . Instructions executing on virtual cores  166 ,  168 ,  176  may in fact be directly executed on PCPUs  120 ,  130 , but under the direction and control of virtualization software  150 . It is possible to present the VCPU topology to the guest OS with any number of virtual cores per VCPU. Thus, it is possible to present the two virtual cores in VM  165  as separate VCPUs rather than as a single VCPU having two cores. It should also be noted that although VM  160  has only on VCPU with two cores, any number of VCPUs each having any number of virtual cores may be presented. In one embodiment, the VMMs (not shown) include a thread mapped to each virtual core in the corresponding virtual machine, which is assigned by CPU scheduler  155  to one of the cores of PCPUs  120 ,  130 . In addition to the VMM threads, the CPU scheduler assigns threads corresponding to kernel  152  itself, so that kernel  152  can carry out its own tasks. CPU scheduler  155  distributes hardware resources, including PCPU time to each thread corresponding to each virtual core, and to any threads running within virtualization software  150 . 
       FIG. 2  shows a system  180  having system hardware  110  as described above with reference to  FIG. 1C , but with traditional operating system  185  executing thereon as shown conceptually in  FIG. 2  by positioning operating system  185  on system hardware  110 . Operating system  185  includes a kernel  182  for managing physical system hardware  110 , and other components and modules (not shown) providing an execution environment, as generally known in the field of operating system development, for executing applications  190 ,  195 , etc. Each application  190 ,  195  can have one or more threads  192 ,  193 ,  194 ,  197 ,  198 , etc., that are assigned by CPU scheduler  185  to one or more cores  122 ,  123 , etc., of system hardware  110 . 
     In one embodiment, CPU scheduler  155  ( FIG. 1C ) or  185  ( FIG. 2 ) manages PCPU cycles according to a generalized processor sharing (GPS) model. With GPS, each thread appears to execute on its own dedicated processor at a rate proportional to a value given by the thread&#39;s assigned weight divided by the sum of all the weights of all the threads. Thus, the greater the assigned weight for the thread relative to weights of other threads, the faster it executes relative to other threads in the system. This is considered a “proportional fair” system since the hardware resource is fairly distributed proportionally to the assigned weights. The CPU scheduler then determines which thread should be scheduled next based on which has not had its fair share of the processor resources based on its assigned weight. 
     Threads may execute until blocked or preemptively descheduled by CPU scheduler  155 ,  185 . Threads may block, e.g., when an input/output or event request is issued and execution cannot continue until the needed data is retrieved or some other event needs to complete. In virtualized computer systems such as that described above with reference to  FIG. 1C , the CPU scheduler  155  may deschedule a thread corresponding to a virtual core if it detects that the guest OS managing the virtual core is in an idle loop. By way of example, U.S. patent application Ser. No. 10/871,922, filed Jun. 18, 2004 and incorporated herein by reference, presents an embodiment for idle loop detection in guest operating systems. 
     The weight is an arbitrary number assigned to each thread. In one embodiment, the number is taken or derived from values given to processes, applications, virtual machines, or other software execution entities or abstractions, by an administrator or user of the computer system. For example, an administrator may decide that VM  160  ( FIG. 1C ) is more important than VM  170 , and should therefore be given three times the resources of VM  170 . The administrator/user may therefore assign a weight of 120 to VM  160  and a weight of 40 to VM  170 , or any pair of numbers having a 3:1 ratio. In one embodiment, the weight of 120 assigned to VM  160  is divided evenly among each virtual cores  166 ,  168 , so that each of the two virtual cores in VM  160  inherits half of the assigned weight of 120, i.e., a weight of 60. The virtualization software then takes the two threads created by the VMM (not shown) for VM  160 , one thread for each virtual core, and assigns PCPU time according to the weight of 60. VM  170 , having a single virtual core and an assigned weight of 40, will have a thread corresponding to virtual core  176  with a weight of 40. CPU scheduler  155  therefore assigns threads for virtual cores  166 ,  168 , and  176  to available PCPU cores according to the ratio 60:60:40, respectively. 
     In another embodiment, a weight or resource share is assigned to each VM without dividing the resource between the VM&#39;s virtual cores in a predetermined manner. In this embodiment, the consumption of PCPU execution time consumed by each VM is tracked as a total of its constituent VCPU resource consumption. Therefore, if one of the virtual cores idles in the VM, the share of PCPU resources allocated to that VM flows to the running virtual cores. 
     In practice, GPS can only be approximated as there are typically fewer processing cores than threads, and each core is time shared at some discrete granularity of time (e.g., several milliseconds). The principles of the GPS model are well known in the art of computer resource scheduling. 
     Common to many “proportional fair,” e.g., “weighted fair queuing” (WFQ) scheduling algorithms is the notion of virtual time. A thread&#39;s virtual time increases in proportion to real time based on (i.e., as a function of) the weight assigned the particular thread such that:
 
 v′=v+q/w   (Eq. 8)
 
     where v′ is the updated virtual time for a particular thread at real time t, v is the current virtual time for that thread before being updated, q is the actual time spent by that thread using a resource, and w is the weight for that thread. The actual time spent by the thread may be determined by PCPU execution time since the last update to v(t) for the thread. By prioritizing clients with lower virtual times, e.g., by scheduling them first, proportional-fair schedulers favor clients with higher weights. More precisely, the threads&#39; CPU usage ratios match (or approximate) their relative weights when the system is overcommitted, i.e., the threads are fully backlogged. The concept of virtual time is well known among programmers familiar with process scheduling in computer systems. However, reference is made to the &#39;193 Application, which provides a more detailed discussion. 
     PCPU resources may be divided among threads, or any higher level abstraction, including processes, applications, virtual cores, VCPUs, virtual machines, users, and groups. Each thread or higher-level abstraction may be referred to as a “resource consumer” or “client.” In one embodiment, resource shares are assigned to individual VMs running concurrently on a particular system. In this case, each VM has its virtual time stamp updated whenever any of its constituent virtual cores consumes PCPU time to execute guest code. Thus, when one virtual core idles in a guest VM, remaining virtual cores can consume the VM&#39;s full allocation of PCPU resources. Although the discussion following relates specifically to threads for clarity, it should be understood that the resource management algorithms described herein may be applied to any resource consumer at any level of abstraction. 
     Other proportional fair algorithms are known that do not rely on a notion of virtual time. One example is referred to as Lottery Scheduling, which is described by Carl A. Waldspurger and William E. Weihl in their paper entitled “Lottery Scheduling: Flexible Proportional-Share Resource Management” presented in the Proceedings of the First Symposium on Operating Systems Design and Implementation (OSDI &#39;94) pages 1-11, Monterey, Calif., November 1994, which is incorporated herein by reference. In this approach, resource rights are represented by lottery tickets, and each allocation is determined by holding a lottery, in which the resource is granted to the client with the winning ticket, picked at random. The resource is therefore, in the aggregate, allocated among competing clients in proportion to the number of tickets that they hold. 
     The execution of a thread τ 1  on one core of a given PCPU may interfere with data stored in the LLC for another thread τ 2  executing on the same or another core of the same PCPU. That is, cache misses seen by τ 1  result in memory accesses to populate the LLC with the necessary lines of data. Since the LLC is shared among all threads that execute on any of the PCPU&#39;s cores, cache misses by one thread may cause data stored by other threads to be evicted, which will result in further misses by the other threads sharing the same LLC. Therefore, if one thread is performing a memory-intensive task, it may unfairly utilize more than its fair share of the cache, causing other threads to spend an inordinate amount of time fetching data from the main memory that was evicted from the LLC by the thread performing the memory intensive task. This causes the progress of the other threads to suffer, sometimes to a great extent, at the expense of the one thread, since a significant amount of their time is spent performing time-consuming memory accesses, which only happen because of the one thread&#39;s memory-intensive activity. 
     The &#39;193 application describes a method for compensating one thread when its effective execution time is compromised by the greater cache pressure exerted by co-running threads. However, it may be useful to predict, based on previous behavior of a particular thread, how it will function with other threads running on a particular processor, so that scheduling decisions can be made that take into account the predicted behavior of the thread. That is, understanding, in advance of a scheduling decision, how the LLC will be divided among a plurality of co-running threads, can help make more intelligent scheduling decisions, as will be further described below. 
       FIG. 3  shows pseudocode  200  representing an algorithm that produces a predicted occupancy of a plurality of threads, given an initial occupancy, a miss rate curve for each thread, and a known size of the LLC. The algorithm presented in  FIG. 3  is designed to predict, based on known miss-rate or miss-ratio curves of a plurality of threads, the equilibrium occupancy for the threads, should they be scheduled to share a common LLC. The algorithm is based on an assumption that for any plurality of threads sharing a cache, the thread having the highest cache pressure at a given time will increase its occupancy, up to a point where the competing pressure by all other clients prevents it from increasing its occupancy. This generates the fluctuations around the equilibrium cache pressure previously discussed. 
     The algorithm simulates running a plurality of threads τ until the cache of size N is full or the cache pressures are zero. Lines of pseudocode  200  that include double-slash characters “//” contain comments (that do not form part of the algorithm) after the double-slash. Lines  1 - 4  of the pseudocode presented in Table 1 initialize variable S to the number of cache lines N, which is a constant value, and the occupancy E(i) for each thread τ(i) to zero. The value i is used to identify a particular thread τ(i). That is, the value i can represent an index for the arrays P(i) and E(i), each of which for a particular value thread τ(i) return or contain the corresponding pressure or occupancy, respectively. 
     Once the variables are initialized in lines  1 - 4 , Loop  202 , including lines  5 - 20 , repeats until S=0, i.e., the cache is full, or the pressures P(i) are zero for all threads τ(i), which is tested at line  20 . 
     Loop  202  includes three sections:  204 ,  206 , and  208 . In section  204 , the variable Pmax is initialized (set) to zero. Then, in section  206 , which contains a do-loop, each cache pressure P(i) is calculated for each thread τ(i) using Equation 1, which was described above. If the cache pressure for any thread is greater than Pmax (tested in line  10 ) then Pmax is set to that cache pressure in line  12  and the thread identifier corresponding to the thread having the maximum cache pressure is stored in the variable “max” in line  13 . 
     After calculating the cache pressure P for each thread τ and identifying the thread having the maximum cache pressure, loop  202 , in section  208 , then increases the presumed occupancy of the thread having the maximum cache pressure E(max) by an amount B in line  18  and subtracts B from the surplus (i.e., unassigned) cache S. Thus, in each execution of loop  202 , a chunk of LLC is assigned to the thread having the highest cache pressure, and the amount of available cache space left is reduced by the same amount. As stated previously, loop  202  repeats until no cache is left (S=0) or the cache pressures are zero (∀P(i)=0). The constant B is configurable, and serves to limit the number of iterations of the algorithm required to predict the equilibrium occupancies for the competing threads. In one embodiment, B is set to an amount equal one-eighth or one-sixteenth the total cache size C. During each iteration, the thread with the highest pressure increases its hypothetical cache occupancy. This in turn affects its current miss rate, and hence its current cache pressure. As the occupancy increases for a particular thread, its miss rate is reduced, and therefore the cache pressure diminishes. When the entire cache is divvied, or when all cache pressures reach zero, the algorithm terminates. 
       FIG. 4  shows a flowchart  250  illustrating by way of example a procedure representing a more general view of the algorithm shown in  FIG. 3 . The procedure begins as indicated at start block  252  and flows to operation  254  wherein values for the surplus (i.e., unassigned) cache and cache occupancies are initialized to the LLC cache size and zero, respectively. Then the procedure flows to operation  256  wherein the cache pressure for each thread is calculated according to Equation 1. As noted previously, there is a relationship between cache pressure and occupancy such that as occupancy increases for a particular thread, cache pressure is reduced. Then, in operation  258 , a block of the surplus cache is assigned to whichever thread has the highest cache pressure. That thread&#39;s occupancy is therefore increased and the surplus cache is decreased by the block amount. In example embodiments, the block amount B was set to one-eighth or one-sixteenth the cache size, as previously mentioned. 
     After the block from surplus cache is assigned in operation  258 , the procedure flows to operation  260  to determine if there is any remaining surplus cache. If there is no remaining surplus cache, then the procedure ends as indicated by done block  264 . However, if there is surplus cache remaining, then the procedure flows to operation  262 , wherein it is determined whether the cache pressures are zero. If the cache pressures are zero then the procedure ends as indicated by done block  264 , otherwise the procedure loops back to operation  256 . After the algorithm terminates, a predicted equilibrium cache occupancy is known for each of the threads tested. 
       FIG. 5  shows a graph  300  illustrating test data comparing predicted verses actual occupancies for a variety of thread parings running on a dual core processor. In this experiment, the cache divvying algorithm described above with reference to  FIGS. 3 and 4  was used to predict occupancies for six pairs of co-running threads, each pair shown in graph  300  separated from others by vertical dashed lines. In each case, the chunk size B was set to one-sixteenth of the cache size, which was 256 KB. Each co-runner generated 10 million interleaved cache references from a Valgrind trace. Valgrind is a well-known open source software tool for computer programmers that is publically available from the Valgrind Developers at Valgrind.org. A Valgrind trace precisely identifies what instructions are executed on a particular run of a program and can identify the state of the processor and other components such as the cache and memory at various points in execution. While 10 million cache references may be insufficient to lead to a full cache occupancy in all cases, results show that predicted occupancies are almost always within one chunk size of the actual cache occupancy, which is strongly suggestive that the cache divvying algorithm described herein is a valid method of predicting cache shares among co-running threads. 
     Once predictions of cache occupancies for co-running threads can be made, more intelligent decisions can be made when scheduling threads that share a common LLC. For a dual core processor, for example, selecting thread parings that result in the least amount of overall “conflict misses” can be made. Conflict misses are LLC misses that occur over a period of time in excess of the amount of misses that would occur at full cache occupancy, and can be simply determined using the known miss rate curve to determine the miss rate at full occupancy and subtract from that the miss rate at the occupancy predicted by the cache divvying algorithm. 
       FIG. 6  illustrates a flowchart  350  illustrating by way of example a procedure for pairing one or more threads to a particular core such that threads are scheduled based on predicted occupancies using the cache divvying algorithm previously described. The procedure begins as indicated by start block  253  and proceeds to operation  354  wherein one or more candidate threads are identified for scheduling on a processor having a shared LLC. In one embodiment, the candidate threads may be the next two threads in a scheduling queue. That is the two threads that have had the least of their fair share of processor time based on their corresponding assigned weights. In another embodiment, candidate threads may be selected among threads executing in other processors to see if it makes sense to switch the thread to the current processor for improving performance by reducing overall cache pressure. 
     Once a candidate thread or threads are identified, the procedure flows to operation  356  wherein the cache divvying algorithm discussed above with reference to  FIGS. 3 and 4  is used to predict the equilibrium occupancies of the candidate threads and any existing threads that would share the LLC according to the particular scenario being evaluated. For example, suppose two candidate threads are being tested to see which should be scheduled at an available core on a quad-core processor that currently has 3 running threads. There are two possible scenarios: either schedule one of the two candidate threads with the existing threads, or the other of the two candidate threads. The algorithm is run twice and the cache occupancies are predicted for all co-running threads in each scenario. 
     Then in operation  358 , the predicted cache occupancies and miss-rate curves for each of the co-running threads in each of the scenarios are compared to identify which of the scenarios result in the fewest conflict LLC misses for all the co-running threads. This information may then be combined with other information, including but not limited to the amount of time a runnable thread has been queued waiting to be dispatched, relative importance of threads, etc., to evaluate which scenario results in the least objectionable impact on all co-running threads. For example, it may be considered less objectionable for a relatively unimportant thread to be greatly impacted by LLC contention than for a relatively important thread to be mildly impacted by LLC contention. In another example, it may be less objectionable to schedule a first thread that has been waiting a long time than a second thread that has been waiting a short time, even though the first thread will impact an important co-running thread to a greater degree than the second thread. 
     Finally, in operation  360 , the candidate threads corresponding to the least objectionable scenario identified in operation  358  are scheduled that use the information in the available core. The procedure then ends as indicated by done block  362 . This is an example of a method for making more intelligent scheduling decisions using the predicted cache occupancies from the cache divvying algorithm. 
     The various embodiments described herein may employ various computer-implemented operations involving data stored in computer systems. For example, these operations may require physical manipulation of physical quantities—usually, though not necessarily, these quantities may take the form of electrical or magnetic signals, where they or representations of them are capable of being stored, transferred, combined, compared, or otherwise manipulated. Further, such manipulations are often referred to in terms, such as producing, identifying, determining, or comparing. Any operations described herein that form part of one or more embodiments of the invention may be useful machine operations. In addition, one or more embodiments of the invention also relate to a device or an apparatus for performing these operations. The apparatus may be specially constructed for specific required purposes, or it may be a general purpose computer selectively activated or configured by a computer program stored in the computer. In particular, various general purpose machines may be used with computer programs written in accordance with the teachings herein, or it may be more convenient to construct a more specialized apparatus to perform the required operations. 
     The various embodiments described herein may be practiced with other computer system configurations including hand-held devices, microprocessor systems, microprocessor-based or programmable consumer electronics, minicomputers, mainframe computers, and the like. 
     One or more embodiments of the present invention may be implemented as one or more computer programs or as one or more computer program modules embodied in one or more computer readable storage media. The term computer readable storage medium refers to any data storage device that can store data which can thereafter be input to a computer system—computer readable media may be based on any existing or subsequently developed technology for embodying computer programs in a manner that enables them to be read by a computer. Examples of a computer readable medium include a hard drive, network attached storage (NAS), read-only memory, random-access memory (e.g., a flash memory device), a CD (Compact Discs)—CD-ROM, a CD-R, or a CD-RW, a DVD (Digital Versatile Disc), a magnetic tape, and other optical and non-optical data storage devices. The computer readable medium can also be distributed over a network coupled computer system so that the computer readable code is stored and executed in a distributed fashion. 
     Although one or more embodiments of the present invention have been described in some detail for clarity of understanding, it will be apparent that certain changes and modifications may be made within the scope of the claims. Accordingly, the described embodiments are to be considered as illustrative and not restrictive, and the scope of the claims is not to be limited to details given herein, but may be modified within the scope and equivalents of the claims. In the claims, elements and/or steps do not imply any particular order of operation, unless explicitly stated in the claims. 
     In addition, while described virtualization methods have generally assumed that virtual machines present interfaces consistent with a particular hardware system, persons of ordinary skill in the art will recognize that the methods described may be used in conjunction with virtualizations that do not correspond directly to any particular hardware system. Virtualization systems in accordance with the various embodiments, implemented as hosted embodiments, non-hosted embodiments or as embodiments that tend to blur distinctions between the two, are all envisioned. Furthermore, various virtualization operations may be wholly or partially implemented in hardware. For example, a hardware implementation may employ a look-up table for modification of storage access requests to secure non-disk data. 
     Many variations, modifications, additions, and improvements are possible, regardless the degree of virtualization. The virtualization software can therefore include components of a host, console, or guest operating system that performs virtualization functions. Plural instances may be provided for components, operations or structures described herein as a single instance. Finally, boundaries between various components, operations and data stores are somewhat arbitrary, and particular operations are illustrated in the context of specific illustrative configurations. Other allocations of functionality are envisioned and may fall within the scope of the invention(s). In general, structures and functionality presented as separate components in exemplary configurations may be implemented as a combined structure or component. Similarly, structures and functionality presented as a single component may be implemented as separate components. These and other variations, modifications, additions, and improvements may fall within the scope of the appended claims(s).