Patent Publication Number: US-10789127-B2

Title: Method of operating memory controller for performing encoding and decoding by using a convolution-type low density parity check code

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application claims the benefit of Korean Patent Application No. 10-2017-0174168, filed on Dec. 18, 2017, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. 
     BACKGROUND 
     The inventive concept relates to a memory controller, and more particularly, to a memory controller for performing an encoding operation and a decoding operation on data for a memory operation, a memory system including the memory controller, and a method of operating the memory controller. 
     When performing decoding on a codeword based on a convolution-type low density parity check (LDPC) code, for example a spatially coupled LDPC code, it is possible to perform sliding window decoding with only a part of the entire codeword. With this decoding scheme, the data output latency of a memory system which is at a level equivalent to that of decoding based on the existing block LDPC code may be secured, and the memory system may have improved correction capability. However, when a memory system performs encoding and decoding based on a convolution-type LDPC code having a long length, the memory system has to decode the entire codeword and then output only a desired portion of a decoding result to a host as read data, due to the size unit of the read data that is received by the host from the memory system. Such a problem limits the improvement of the data output latency of the memory system. 
     SUMMARY 
     The inventive concept provides a memory controller capable of performing a decoding operation for improving the output latency of a memory system. 
     The inventive concept provides a memory system including the memory controller. 
     The inventive concept also provides a method of operating the memory controller. 
     According to an aspect of the inventive concept, there is provided a method of operating a memory controller configured to perform decoding by using a parity check matrix corresponding to a convolution-type low density parity check (LDPC) code. The method includes: receiving a codeword from at least one memory device, the codeword including a first sub-codeword and a second sub-codeword; decoding the first sub-codeword into first data by using first sliding windows in a first direction, set based on a first sub-matrix included in the parity check matrix and associated with the first sub-codeword; and decoding the second sub-codeword into second data by using second sliding windows in a second direction, set based on a second sub-matrix included in the parity check matrix and associated with the second sub-codeword. 
     According to another aspect of the inventive concept, there is provided a method of operating a memory system that performs encoding and decoding by using a parity check matrix corresponding to a convolution-type low density parity check (LDPC) code and includes a memory controller and at least one memory device. The method includes: receiving, by the memory controller, from a host, a write request and write data to be stored in the memory system; encoding, by the memory controller, first data of the write data into a first sub-codeword based on a first sub-matrix included in the parity check matrix; encoding, by the memory controller, second data of the write data into a second sub-codeword based on a second sub-matrix included in the parity check matrix; and writing, by the memory controller, a codeword in the at least one memory device, the codeword including the first sub-codeword and the second sub-codeword. 
     According to another aspect of the inventive concept, there is provided a method of operating a memory controller that performs decoding by using a parity check matrix corresponding to a convolution-type low density parity check (LDPC) code, wherein the parity check matrix includes a first partial parity check matrix, a second partial parity check matrix, and tunneling information associated with the first partial parity check matrix and the second partial parity check matrix. The method includes: receiving from a memory device a codeword including a first sub-codeword; performing a first phase decoding operation on the first sub-codeword by using first sliding windows set based on the first partial parity check matrix associated with the first sub-codeword; and performing a second phase decoding operation on the first sub-codeword by using the tunneling information based on a result of the first phase decoding operation. 
     According to yet another aspect of the inventive concept, there is provided a method of operating a memory system. The method comprises: a memory controller of the memory system receiving from a host a write request and write data to be stored in the memory system; the memory controller performing a convolution-type low density parity check (LDPC) encoding of the write data using a parity check matrix to produce a codeword corresponding to the write data, and the memory controller writing the codeword into one or more memory devices of the memory system. The LDPC encoding comprises: the memory controller encoding first data of the write data into a first sub-codeword based on a first sub-matrix included in the parity check matrix, and the memory controller encoding second data of the write data into a second sub-codeword based on a second sub-matrix included in the parity check matrix, wherein the codeword comprises the first sub-codeword and the second sub-codeword. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Embodiments of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings. 
         FIG. 1  is a schematic block diagram of an embodiment of a memory system. 
         FIG. 2  is a block diagram for explaining the operation of an embodiment of an error checking and correcting (ECC) logic. 
         FIG. 3  is a diagram for explaining an embodiment of a parity check matrix corresponding to a low density parity check (LDPC) code. 
         FIG. 4  is a diagram for explaining the operation of an ECC encoder of  FIG. 2 , which conforms to the structure of a parity check matrix. 
         FIG. 5  is a diagram for explaining a memory operation of an embodiment of a memory device. 
         FIGS. 6A and 6B  are diagrams for explaining the operation of the ECC decoder of  FIG. 2 , which conforms to the structure of a parity check matrix. 
         FIG. 7A  is a diagram for explaining the operation of the ECC encoder of  FIG. 2 , which conforms to the structure of a parity check matrix, and  FIG. 7B  is a flowchart of a method of generating termination parity in the structure of the parity check matrix of  FIG. 7A . 
         FIGS. 8A and 8B  are diagrams for explaining a memory operation of an embodiment of a memory device. 
         FIG. 9  is a diagram for explaining the operation of the ECC decoder of  FIG. 2 , which conforms to the structure of a parity check matrix. 
         FIGS. 10A and 10B  are diagrams for explaining a memory operation of an embodiment of a memory device. 
         FIG. 11  is a diagram for explaining the operation of the ECC decoder of  FIG. 2 , which conforms to the structure of a parity check matrix. 
         FIGS. 12A and 12B  are diagrams for explaining a decoding operation for a first sub-codeword of the ECC decoder of  FIG. 2 , which conforms to the structure of a parity check matrix. 
         FIG. 13  is a block diagram of an embodiment of a memory system. 
         FIGS. 14A, 14B, 14C, and 14D  are diagrams for explaining encoding and decoding methods according to embodiments. 
         FIG. 15  is a diagram for explaining the operation of the ECC encoder of  FIG. 2 , which conforms to the structure of a parity check matrix. 
         FIG. 16  is a flowchart illustrating an embodiment of a method of generating a tunneling parity. 
         FIG. 17  is a flowchart illustrating an embodiment of a decoding operation. 
         FIGS. 18, 19A, 19B, 19C, 20A, 20B and 21  are diagrams for explaining various embodiments of a second phase decoding operation of  FIG. 17 . 
     
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
     Hereinafter, embodiments of the inventive concept will be described in detail with reference to the accompanying drawings. Like reference numerals denote like elements in the drawings, and redundant description thereof will be omitted. 
       FIG. 1  is a block diagram of an embodiment of a memory system  1 . 
     Referring to  FIG. 1 , memory system  1  may include a memory controller  10  and one or more memory devices  20 . Memory system  1  shown in  FIG. 1  may correspond to any one of various data storage media based on a non-volatile memory, for example, a memory card, a universal serial bus (USB) memory, and a solid state drive (SSD). Memory device  20  may include a memory cell array  22  and an interface  24  for transmitting and receiving data and the like to and from memory controller  10 . Memory cell array  22  may have a two-dimensional structure (or a horizontal structure) formed in a direction parallel to a substrate, or a three-dimensional structure (or a vertical structure) formed in a direction perpendicular to the substrate. Memory cells in memory cell array  22  may be non-volatile memory cells. For example, memory cell array  22  may be a NAND flash memory cell array or a NOR flash memory cell array. Hereinafter, embodiments will be described in detail with reference to a case where the memory cells in memory cell array  22  are flash memory cells. However, embodiments are not limited thereto, and in other embodiments, the memory cells in memory cell array  22  may be resistive memory cells such as resistive random access memory (RRAM) cells, phase change RAM (PRAM) cells, or magnetic RAM (MRAM) cells. 
     Memory controller  10  may control memory operations such as write (or program), read, and erase operations on memory device  20  in response to a request (e.g., a write request, a read request, an erase request, etc.) received from a host HOST. Memory controller  10  may include a host interface  11 , a central processing unit (or processor)  13 , a memory interface  15 , RAM  17 , and a partially decodable error checking and correcting (ECC) logic element  19 . In various embodiments, partially decodable ECC logic element  19  may comprise a logic circuit and/or a processor configured to perform logic operations in response to instructions stored in a memory, etc. Hereinafter, partially decodable ECC logic element  19  is referred to as “ECC logic  19 ” for convenience of description. 
     Memory controller  10  may transmit and receive data and the like to and from the host HOST through host interface  11  and may transmit and receive data and the like to memory device  20  through memory interface  15 . For example, memory controller  10  may receive from the host HOST a write request and write data to be stored in memory system  1  by writing the data to one or more memory devices  20 . Also, memory controller  10  may receive from the host HOST a read request and an address or addresses to read data from memory devices  20  of memory system  1 . Host interface  11  may be connected to the host HOST via a parallel AT attachment (PATA) bus, a serial AT attachment (SATA) bus, a small computer system interface (SCSI), a USB, a PCIe, or the like. Central processing unit  13  may control overall operations (e.g., write, read, file system management) for memory device  20 . RAM  17  may operate under the control of central processing unit  13  and may be used as a work memory, a buffer memory, a cache memory, or the like. When RAM  17  is used as a working memory, data processed by central processing unit  13  may be temporarily stored in RAM  17 . When RAM  17  is used as a buffer memory, RAM  17  may be used to buffer write data to be transferred from the host HOST to memory device  20 , or read data to be transferred from memory device  20  to the host HOST. Furthermore, when ECC logic  19  encodes write data received from the host HOST, or decodes a codeword received from memory device  20 , RAM  17  may be used as a buffer for encoding and decoding operations. 
     ECC logic  19  may receive a codeword from memory device  20  and perform error correction decoding on the codeword. That is, because the codeword received from memory device  20  may have a bit error due to deterioration of memory cells of memory cell array  22 , noise related to a memory operation, or the like, ECC logic  19  may correct errors for the codeword and provide read data with integrity to the host HOST. ECC logic  19  may perform decoding on a codeword, based on a convolution-type low density parity check (LDPC) code, e.g., a spatially coupled LDPC code. The LDPC code may be a kind of linear block code that enables iterative decoding, and the LDPC code may be implemented with one parity check matrix. Hereinafter, the operation of ECC logic  19  will be described focusing on the parity check matrix corresponding to the LDPC code, and it is assumed that the codeword is a set of data having a size unit that may be encoded and generated or decoded through one parity check matrix corresponding to the LDPC code. The codeword may include sub-codewords, and the size unit of each of the sub-codewords may be less than or equal to a data size unit which memory controller  10  sends to the host HOST in response to a read request. 
     In an embodiment, ECC logic  19  may perform decoding on a sub-codeword basis. Performing decoding on a sub-codeword basis may be defined as a partial decoding operation. Specifically, ECC logic  19  may perform decoding on a sub-codeword basis, based on a sub-matrix or partial parity check matrix, according to the structure of the parity check matrix. Thus, since ECC logic  19  may perform decoding on a sub-codeword basis by using only a part of the parity check matrix, the time required to provide read data requested from the host HOST may be reduced. As a result, the data output latency of memory system  1  may be improved. 
     In an embodiment, ECC logic  19  may perform encoding of write data on a sub-codeword basis to enable decoding on a sub-codeword basis. Specifically, ECC logic  19  may perform encoding on a sub-codeword basis, based on a sub-matrix or partial parity check matrix, in accordance with the structure of the parity check matrix. 
     Memory controller  10  may rearrange a codeword generated as a result of an encoding operation of ECC logic  19  and provide the rearranged codeword to memory device  20 , so that later quick decoding may be performed. Memory device  20  may store the rearranged codeword directly in memory cell array  22  and provide the rearranged codeword to memory controller  10  in response to a read command from memory controller  10 . In an embodiment, memory controller  10  may rearrange write data in advance before the encoding operation of ECC logic  19  so that later quick decoding may be performed. In addition, memory device  20  may rearrange a stored codeword before outputting the stored codeword in response to a read command from memory controller  10  and output the rearranged codeword to memory controller  10 , so that later quick decoding may be performed. As described above, memory controller  10  or memory device  20  may efficiently perform a decoding operation by rearranging a codeword considering a later quick decoding operation, and may also perform a simple partial decoding operation. 
       FIG. 2  is a block diagram for explaining an embodiment of the operation of ECC logic  19 . Hereinafter, only a part of the configuration of memory system  1  is shown to explain the operation of ECC logic  19 , and a detailed configuration of memory system  1  is shown in  FIG. 1 . 
     Referring to  FIG. 2 , ECC logic  19  may include an ECC encoder  19   a  and an ECC decoder  19   b . ECC encoder  19   a  may generate an error correction code (ECC) for correcting a bit error. ECC encoder  19   a  may encode write data Data received from a host to thereby generate a codeword CW. The codeword CW may include at least two sub-codewords SubCWs and a termination parity PT. The termination parity PT may be bit data to ensure that a syndrome of the codeword CW becomes a zero vector. The details of the termination parity PT will be described below with reference to  FIG. 3 . Each of the sub-codewords SubCWs may include information bits corresponding to the write data Data and parity for error correction. Hereinafter, it is assumed that the parity may include a plurality of parity bits and the termination parity PT may include a plurality of termination parity bits. For example, ECC encoder  19   a  may divide a parity check matrix into a first sub-matrix and a second sub-matrix, encode some of the write data Data based on the first sub-matrix to thereby generate a first sub-codeword, and encode the remainder of the write data Data based on the second sub-matrix to thereby generate a second sub-codeword. 
     Memory interface  15  may receive the codeword CW from ECC encoder  19   a  and output the received codeword CW to memory device  20 . In this case, memory interface  15  may include a sequence rearrangement unit  15   a , and sequence rearrangement unit  15   a  may rearrange the order between the sub-codewords SubCWs and the termination parity PT of the codeword CW, or rearrange the order of bits included in one sub-codeword SubCW. Memory device  20  may receive the codeword CW and store the received codeword CW in memory cell array  22  and then may output a codeword CW′ stored in memory device  20  to memory controller  10  in response to a read command of memory controller  10 . As described above, the codeword CW′ may include bit errors due to deterioration of memory cells of memory device  20  or the like. Memory interface  15  may provide ECC decoder  19   b  with the codeword CW′ received from memory device  20 . Although  FIG. 2  shows a case in which the codeword CW′ is directly provided from memory interface  15  to ECC decoder  19   b , embodiments are not limited thereto. For example, memory controller  10  may further include a predetermined buffer (for example, RAM  17  in  FIG. 1 ), and the buffer may temporarily store the codeword CW′. ECC decoder  19   b  may selectively read (or receive) a part of a codeword from the buffer to thereby perform a decoding operation on a sub-codeword basis. ECC decoder  19   b  performs a decoding operation on a sub-codeword basis, and when the decoding of data Data corresponding to a data size unit output from memory controller  10  to the host is completed, memory controller  10  may directly output decoded data to the host. 
       FIG. 3  is a diagram for explaining an embodiment of a parity check matrix H corresponding to an LDPC code. 
     Referring to  FIG. 3 , a tanner graph may include 12 check nodes S 1  to S 12  and 27 variable nodes, i.e., 15 information nodes X 1 , X 2 , X 4 , X 5 , X 7 , X 8 , X 10 , X 11 , X 13 , X 14 , X 16 , X 17 , X 19 , X 20 , and X 22 , 7 parity nodes X 3 , X 6 , X 9 , X 12 , X 15 , X 18 , and X 21 , and 5 termination parity nodes X 23 , X 24 , X 25 , X 26 , and X 27 . The i-th column (where i is an integer) and the j-th row (where j is an integer) of the parity check matrix H may correspond to a variable node X i  and a check node S j , respectively. A parity check equation may be represented by variable nodes connected to one check node. For example, two information nodes X 1  and X 2  and the parity node X 3  may be connected to the check node S 1 , and in this way, one parity check equation may be derived. The parity check equation is a formula that constitutes H·CW T =0 (where CW is a matrix corresponding to a codeword), and thus, the parity check equation may be determined by the parity check matrix H. 
     Since the parity check matrix H includes 27 columns, the length of a codeword generated based on the parity check matrix H may be composed of 27 bits. The codeword may include parity and termination parity for checking and correcting information bits corresponding to data received from a host and a bit error. In particular, the termination parity is used to guarantee the reception quality of a codeword of a memory device, and may be generated based on the parity check matrix H by using a virtual information bit having a value which a memory controller and a memory device have determined in advance. In other words, the termination parity may be bit data to ensure that a syndrome of the entire codeword becomes a zero vector. The syndrome of the entire codeword may be a result of the operation of H·CW T . As an example, the termination parity may be generated based on a part or the entirety of each of eighth and ninth base matrices BM8 and BM9. However, the parity check matrix H shown in  FIG. 3  is only an example, is not limited thereto, and may be variously designed. In addition, the termination parity may be present in one sub-block LPDC code or be present over a plurality of sub-block LPDC codes, according to a code rate of a codeword and a degree value of a variable node. 
       FIG. 4  is a diagram for explaining the operation of ECC encoder  19   a  of  FIG. 2 , which conforms to the structure of a parity check matrix Ha. 
     Referring to  FIGS. 2 and 4 , the parity check matrix Ha may include first and second sub-matrices Sub_M 1   a  and Sub_M 2   a , and a termination matrix BM_Ta for generating termination parity may be positioned at a last part in the second sub-matrix Sub_M 2   a . That is, a twelfth base matrix BM12 may correspond to a termination matrix BM_Ta. ECC encoder  19   a  may encode first data Data_ 1  of the write data Data received from the host, based on the first sub-matrix Sub_M 1   a , to thereby generate a first sub-codeword SubCW_ 1   a , and may encode second data Data_ 2  of the write data Data, based on the second sub-matrix Sub_M 2   a , to thereby generate a second sub-codeword SubCW_ 2   a . Each of the first and second sub-codewords SubCW_ 1   a  and SubCW_ 2   a  may include an information sector I_Sec in which information bits are arranged, and a parity sector P_Sec in which parity is arranged. ECC encoder  19   a  may generate the termination parity by using the twelfth base matrix BM12 in encoding the second data Data_ 2 . A codeword CWa may include a first sub-codeword, a second sub-codeword, and termination parity. The termination parity may be positioned in a termination parity sector PT_sec at the rear end of the second sub-codeword SubCW_ 2   a . Memory controller  10  may output an encoded codeword CWa as described above to memory device  20 . 
     In an embodiment, memory controller  10  may rearrange data in advance before encoding, taking into account decoding to be described with reference to  FIG. 6A  and the like later. As an example, in a first case case 1 , memory controller  10  may not rearrange the first data Data_ 1  and may reverse the second data Data_ 2  so that the second data Data_ 2  is encoded in a direction from the most significant bit (MSB) of the second data Data_ 2  to the least significant bit (LSB) of the second data Data_ 2 . However, as in a second case case 2 , memory controller  10  may not control a rearrangement operation for the first data Data_ 1  and the second data Data_ 2 . 
       FIG. 5  is a diagram for explaining a memory operation of an embodiment of a memory device  100 . 
     Referring to  FIG. 5 , memory device  100  may include a control logic element  110 , a page buffer circuit  120 , a data input/output (I/O) circuit  130 , a voltage generator  140 , a row decoder  150 , and a memory cell array  160 . In various embodiments, control logic element  110  may comprise a logic circuit and/or a processor configured to perform logic operations in response to instructions stored in a memory, etc. Hereinafter, control logic element  110  is referred to as “control logic  110 ” for convenience of description. Data I/O circuit  130  may correspond to interface  24  of memory device  20  of  FIG. 1 . 
     Memory cell array  160  may be connected to row decoder  150  via word lines WLs, a string select line SSL, and ground select lines GSL and may be coupled to page buffer circuit  120  via bit lines BLs. Memory cell array  160  may include a plurality of memory blocks. 
     Row decoder  150  may decode an address to thereby select any one of the word lines WLs of memory cell array  160 . Row decoder  150  may provide a word line voltage VWL, received from voltage generator  140 , to a selected word line WL of memory cell array  160 . Page buffer circuit  120  may operate as a write driver or a sense amplifier in accordance with operations performed by control logic  110 . 
     Control logic  110  may control a memory operation based on a command CMD and an address ADDR received from a memory controller. Data I/O circuit  130  may receive first and second codewords CW 1   a  and CW 2   a . Data I/O circuit  130  may sequentially provide the received first and second codewords CW 1   a  and CW 2   a  to page buffer circuit  120 . For example, data I/O circuit  130  may provide bits of each of the received first and second codewords CW 1   a  and CW 2   a  in the order from LSB to MSB to page buffer circuit  120 . Page buffer circuit  120  may include a page buffer BF having a preset size and the first and second codewords CW 1   a  and CW 2   a  may be temporarily written to the page buffer BF. The size of the page buffer BF may correspond to a minimum size unit of data written to memory cell array  160  or read from memory cell array  160 . For example, the first codeword CW 1   a  may be stored in the page buffer BF in the order of a first sub-codeword SubCW_ 11   a , a second sub-codeword SubCW_ 12   a , and a termination parity PT, and the second codeword CW 2   a  may be stored in the page buffer BF in the order of a first sub-codeword SubCW_ 21   a , a second sub-codeword SubCW_ 22   a , and a termination parity PT. Page buffer circuit  120  may write the first and second codewords CW 1   a  and CW 2   a  stored in the page buffer BF into memory cell array  160  as one unit (e.g., a page unit) under the control of control logic  110 . 
     Control logic  110  may receive a read command CMD and an address ADDR from the memory controller. Page buffer circuit  120  may read codewords CW 1   a ′ and CW 2   a ′, stored in memory cell array  160 , under the control of control logic  110  and temporarily write the codewords CW 1   a ′ and CW 2   a ′ into the page buffer BF. Page buffer circuit  120  may output the codewords CW 1   a ′ and CW 2   a ′ stored in the page buffer BF to the memory controller through data I/O circuit  130  under the control of control logic  110 . 
     Although  FIG. 5  illustrates a page buffer BF having a size corresponding to the data size of two codewords, embodiments are not limited thereto. For example, the page buffer BF may be implemented to have various sizes according to a memory operation specification. 
       FIGS. 6A and 6B  are diagrams for explaining the operation of ECC decoder  19   b  of  FIG. 2 , which conforms to the structure of a parity check matrix Ha.  FIG. 6A  is a diagram illustrating a case where decoding is performed assuming the first case case 1  of  FIG. 4 , and  FIG. 6B  is a diagram illustrating a case where decoding is performed assuming the second case case 2  of  FIG. 4 . 
     Referring to  FIGS. 2 and 6A , ECC decoder  19   b  may decode a first sub-codeword SubCW_ 1   a ′ into first data Data_ 1  by using first sliding windows WD_ 1   a , WD_ 2   a , . . . in a first direction, set based on a first sub-matrix Sub_M 1   a  associated with the first sub-codeword SubCW_ 1   a ′. ECC decoder  19   b  may decode the first sub-codeword SubCW_ 1   a ′ by using a parity check equation derived from row and column components contained in each of the first sliding windows WD_ 1   a , WD_ 2   a , . . . in the first direction. Specifically, ECC decoder  19   b  may decode the first sub-codeword SubCW_ 1   a ′ while moving the first sliding windows WD_ 1   a , WD_ 2   a , . . . in a diagonal direction toward the lower right with respect to the parity check matrix Ha, and accordingly, the first sub-codeword SubCW_ 1   a ′ may be decoded in a direction from the LSB of the first sub-codeword SubCW_ 1   a ′ to the MSB thereof. As a result, as the decoding is performed, the LSB of the first data Data_ 1  may be generated first and the MSB of the first data Data_ 1  may be finally generated. Bits of the first data Data_ 1  corresponding to a sector in which decoding is completed may be preferentially output to the host HOST as read data. 
     ECC decoder  19   b  may decode a second sub-codeword SubCW_ 2   a ′ into second data Data_ 2  by using second sliding windows WD_ 1   b , WD_ 2   b , . . . in a second direction, which may be opposite to the first direction, set based on a second sub-matrix Sub_M 2   a  associated with the second sub-codeword SubCW_ 2   a ′. Specifically, ECC decoder  19   b  may decode the second sub-codeword SubCW_ 2   a ′ while moving the second sliding windows WD_ 1   b , WD_ 2   b , . . . in a diagonal direction toward the upper left with respect to the parity check matrix Ha, and accordingly, the second sub-codeword SubCW_ 2   a ′ may be decoded in a direction from the MSB of the second sub-codeword SubCW_ 2   a ′ to the LSB thereof. As described above, in the first case case 1  of  FIG. 4 , the second data Data_ 2  is reversed before being encoded, and thus, as the decoding is performed, the LSB of the second data Data_ 2  may be generated first and the MSB of the second data Data_ 2  may be finally generated. Bits of the second data Data_ 2  corresponding to a sector in which decoding is completed may be preferentially output to the host HOST. 
     Referring to  FIG. 6B , unlike  FIG. 6A , in the second case case 2  of  FIG. 4 , a rearrangement operation is not performed before encoding the second data Data_ 2 , and thus, as the decoding is performed, the MSB of the second data Data_ 2  may be generated first and the LSB of the second data Data_ 2  may be finally generated. Accordingly, when the decoding of the second sub-codeword SubCW_ 2   a ′ is completed and the entire second data Data_ 2  is generated, Bits from the LSB to the MSB of the second data Data_ 2  may be sequentially output to the host HOST. 
       FIG. 7A  is a diagram for explaining the operation of ECC encoder  19   a  of  FIG. 2 , which conforms to the structure of a parity check matrix Hb.  FIG. 7B  is a flowchart of a method of generating termination parity in the structure of the parity check matrix Hb of  FIG. 7A . 
     Referring to  FIGS. 2 and 7A , the parity check matrix Hb may include first and second sub-matrices Sub_M 1   b  and Sub_M 2   b , and a termination matrix BM_Tb for generating termination parity may be positioned at the boundary between the first sub-matrix Sub_M 1   b  and the second sub-matrix Sub_M 2   b . That is, a part of a sixth base matrix BM6 and a part of a seventh base matrix BM7 may correspond to the termination matrix BM_Tb. ECC encoder  19   a  may encode first data Data_ 1  of the write data Data received from the host, based on the first sub-matrix Sub_M 1   b , to thereby generate a first sub-codeword SubCW_ 1   b , and may encode second data Data_ 2  of the write data Data based on the second sub-matrix Sub_M 2   b  to thereby generate a second sub-codeword SubCW_ 2   b.    
     However, since the termination matrix BM_Tb is arranged at the boundary between the first sub-matrix Sub_M 1   b  and the second sub-matrix Sub_M 2   b , unlike the structure of the parity check matrix Ha in  FIG. 4 , the termination parity may be associated with the first and second sub-codewords SubCW_ 1   b  and SubCW_ 2   b . Accordingly, the termination parity may be generated using a result of the encoding of the first data Data_ 1  and a result of the encoding of the second data Data_ 2 . 
     Referring to  FIG. 7B  to explain the method of generating the termination parity, the first sub-codeword SubCW_ 1   b  is generated by encoding the first data Data_ 1  based on the first sub-matrix Sub_M 1   b  (operation S 100 ), and the second sub-codeword SubCW_ 2   b  is generated by encoding the second data Data_ 2  based on the second sub-matrix Sub_M 2   b  (operation S 110 ). A first partial syndrome of the first sub-codeword SubCW_ 1   b  is acquired based on the termination matrix BM_Tb associated with the termination parity (operation S 120 ), and a second partial syndrome of the second sub-codeword SubCW_ 2   b  is acquired based on the termination matrix BM_Tb associated with the termination parity (operation S 130 ). The termination parity is generated using the first partial syndrome and the second partial syndrome (operation S 140 ). 
     Referring back to  7 A, memory controller  10  may place a termination parity sector PT_sec, which is on a codeword CWb, at the rear end of the second sub-codeword SubCW_ 2   b . With respect to this, an operation of memory device  20  and an operation of ECC decoder  19   b  will be described with reference to  FIGS. 8A to 9 . Memory controller  10  may also place the termination parity sector PT_sec, which is on the codeword CWb, between the first sub-codeword SubCW_ 1   b  and the second sub-codeword SubCW_ 2   b . With respect to this, an operation of memory device  20  and an operation of ECC decoder  19   b  will be described with reference to  FIGS. 10A to 11 . 
       FIGS. 8A and 8B  are diagrams for explaining a memory operation of an embodiment of a memory device  100 . Hereinafter, the configuration of memory device  100  shown in  FIGS. 8A and 8B  is the same as that of memory device  100  shown in  FIG. 5 , and thus, detailed description thereof will be omitted. 
     Referring to  FIG. 8A , control logic  110  may control a write operation based on a write command W_CMD and an address ADDR received from a memory controller. Data I/O circuit  130  may receive first and second codewords CW 1   b  and CW 2   b . Data I/O circuit  130  may sequentially provide the received first and second codewords CW 1   b  and CW 2   b  to a page buffer circuit  120 . Page buffer circuit  120  may include a page buffer BF having a preset size. The first codeword CW 1   b  may be stored in the page buffer BF in the order of a first sub-codeword SubCW_ 11   b , a second sub-codeword SubCW_ 12   b , and a termination parity PT, and the second codeword CW 2   b  may be stored in the page buffer BF in the order of a first sub-codeword SubCW_ 21   b , a second sub-codeword SubCW_ 22   b , and a termination parity PT. Page buffer circuit  120  may write the first and second codewords CW 1   b  and CW 2   b  stored in the page buffer BF into memory cell array  160  under the control of control logic  110 . 
     Referring to  FIG. 8B , control logic  110  may receive from the memory controller a read command R_CMD and an address ADDR in memory cell array from which data is to be read. Page buffer circuit  120  may read first and second codewords CW 1   b ′ and CW 2   b ′, stored in memory cell array  160 , under the control of control logic  110  and temporarily write the first and second codewords CW 1   b ′ and CW 2   b ′ into the page buffer BF. Page buffer circuit  120  may output the first and second codewords CW 1   b ′ and CW 2   b ′ stored in the page buffer BF to the memory controller through data I/O circuit  130  under the control of control logic  110 . 
     Control logic  110  according to an embodiment may rearrange each of the first and second codewords CW 1   b ′ and CW 2   b ′ stored in the page buffer BF, based on output sequence management information M_Info, and output rearranged codewords through data I/O circuit  130 , and the memory controller may perform sequential decoding in a bit order of each of the first and second codewords CW 1   b ′ and CW 2   b ′ output from memory device  100 . In an embodiment, control logic  110  may control the first codeword CW 1   b ′ to be output in the order of a first sub-codeword SubCW_ 11   b ′ corresponding to an address ‘A’ to an address ‘B’, a termination parity PT corresponding to an address ‘C’ to an address ‘D’, and a second sub-codeword SubCW_ 12   b ′ corresponding to an address ‘B’ to an address ‘C’, based on the output sequence management information M_Info. In addition, control logic  110  may control the second sub-codeword SubCW_ 12   b ′ to be output in a bit order corresponding to a reverse address, that is, from the address ‘C’ to the address ‘B’. As a result, the first sub-codeword SubCW_ 11   b ′ may be output in the order from LSB to MSB, whereas the second sub-codeword SubCW_ 12   b ′ may be output in the order from MSB to LSB. In other embodiments, the second codeword CW 2   b ′ may also be output in the same manner as the first codeword CW 1   b′.    
     The order of bits that are output by data I/O circuit  130  may be set in advance for each area of the page buffer BF. That is, a forward output and a reverse output may be set in advance according to the area of the page buffer BF. The area of the page buffer BF may be specified using the address of the page buffer BF. Such setting information may be managed by control logic  110  as the output sequence management information M_Info. However, this case is only an example embodiment and is not limited thereto. For example, an output order of the first sub-codeword SubCW_ 11   b ′, second sub-codeword SubCW_ 12   b ′, and termination parity PT of the first codeword CW 1   b ′ and a forward output and a reverse output of the first sub-codeword SubCW_ 11   b ′ and second sub-codeword SubCW_ 12   b ′ of the first codeword CW 1   b ′ may be set by one or more flag bits. In addition, an output order of the first sub-codeword SubCW_ 21   b ′, second sub-codeword SubCW_ 22   b ′, and termination parity PT of the second codeword CW 2   b ′ and a forward output and a reverse output of the first sub-codeword SubCW_ 21   b ′ and second sub-codeword SubCW_ 22   b ′ of the second codeword CW 2   b ′ may be set by one or more flag bits. Control logic  110  may set the flag bit(s) for each of the first and second codewords CW 1   b ′ and CW 2   b ′ to thereby control an output order of each of the first and second codewords CW 1   b ′ and CW 2   b ′ so that the memory controller performs a sequential decoding in a bit order of each of the first and second codewords CW 1   b ′ and CW 2   b ′ output by memory device  100 . 
       FIG. 9  is a diagram for explaining the operation of ECC decoder  19   b  of  FIG. 2 , which conforms to the structure of a parity check matrix Hb. In  FIG. 9 , it is assumed that a codeword CWb′ is output from memory device  20  in the manner described with reference to  FIG. 8B . 
     Referring to  FIGS. 2 and 9 , memory device  20  may sequentially output a first sub-codeword SubCW_ 1   b ′ and termination parity to memory controller  10 . Memory device  20  may output second sub-codeword SubCW_ 2   b ′ to memory controller  10  in the order from MSB to LSB. ECC decoder  19   b  may receive the first sub-codeword SubCW_ 1   b ′ and the termination parity and immediately decode the first sub-codeword SubCW_ 1   b ′ by using first sliding windows WD_ 1   a , WD_ 2   b , . . . in a first direction. 
     Since ECC decoder  19   b  receives the second sub-codeword SubCW_ 2   b ′ in the order from MSB to LSB, ECC decoder  19   b  may perform decoding on the second sub-codeword SubCW_ 2   b ′ in the order from MSB to LSB by using second sliding windows WD_ 1   b , WD_ 2   b , . . . in a second direction, in this case opposite to the first direction. Other specific operations of ECC decoder  19   b  are similar to those described with reference to  FIG. 6B , and thus a detailed description thereof will be omitted. 
       FIGS. 10A and 10B  are diagrams for explaining a memory operation of an example embodiment of memory device  100 . Hereinafter, the configuration of memory device  100  has been described with reference to  FIG. 5 , and therefore, detailed description thereof will be omitted. 
     Referring to  FIG. 10A , control logic  110  may receive a write command W_CMD and an address ADDR from a memory controller, and unlike in  FIG. 8A , data I/O circuit  130  may receive rearranged codewords CW 1   b  and CW 2   b  from the memory controller. In an embodiment, a first codeword CW 1   b  may be stored in a page buffer BF of page buffer circuit  120  in the order of a first sub-codeword SubCW_ 11   b , a termination parity PT, and a reversed second sub-codeword SubCW_ 12   b , and a second codeword CW 2   b  may be stored in the page buffer BF in the order of a first sub-codeword SubCW_ 21   b , a termination parity PT, and a reversed second sub-codeword SubCW_ 22   b . Page buffer circuit  120  may write the first and second codewords CW 1   b  and CW 2   b  stored in the page buffer BF into memory cell array  160  under the control of control logic  110 . 
     Referring to  FIG. 10B , control logic  110  may receive a read command R_CMD and an address ADDR from the memory controller, and page buffer circuit  120  may read codewords CW 1   b ′ and CW 2   b ′, stored in memory cell array  160 , under the control of control logic  110  and temporarily write the read codewords CW 1   b ′ and CW 2   b ′ into the page buffer BF. Page buffer circuit  120  may output the codewords CW 1   b ′ and CW 2   b ′ stored in the page buffer BF to the memory controller through data I/O circuit  130  under the control of control logic  110 . 
       FIG. 11  is a diagram for explaining the operation of ECC decoder  19   b  of  FIG. 2 , which conforms to the structure of a parity check matrix Hb. In  FIG. 11 , it is assumed that a codeword CWb′ is output from memory device  20  in the manner described with reference to  FIG. 10B . 
     Referring to  FIG. 2  and  FIG. 11 , memory device  20  may output a first sub-codeword SubCW_ 1   b ′, termination parity, and a reversed second sub-codeword SubCW_ 2   b ′ to the memory controller in the order from LSB to MSB. Since ECC decoder  19   b  receives the reversed second sub-codeword SubCW_ 2   b ′ in the order from LSB to MSB, but the second sub-codeword SubCW_ 2   b ′ has a form reversed after encoding is completed in memory controller  10 , ECC decoder  19   b  may decode the reversed second sub-codeword SubCW_ 2   b ′ in the order from LSB to MSB by using second sliding windows WD_ 1   b , WD_ 2   b , . . . in a second direction which may be opposite to the first direction. Other specific operations of ECC decoder  19   b  are similar to those described with reference to  FIG. 9 , and detailed description thereof will be omitted. 
       FIGS. 12A and 12B  are diagrams for explaining a decoding operation for a first sub-codeword SubCW_ 1   b ′ of ECC decoder  19   b  of  FIG. 2 , which conforms to the structure of a parity check matrix Hb. 
     Referring to  FIGS. 2 and 12A , ECC decoder  19   b  may decode the first sub-codeword SubCW_ 1   b ′ based on only a first sub-matrix Sub_M 1   b . That is, ECC decoder  19   b  may change the sizes of first sliding windows WD_ 1   a  to WD_na in a first direction so that the first sliding windows WD_ 1   a  to WD_na in the first direction may be set only within the first sub-matrix Sub_M 1   b . As an example, ECC decoder  19   b  may set the last first sliding window WD_na to include a part of a termination matrix BM_Tb. ECC decoder  19   b  may decode the first sub-codeword SubCW_ 1   b ′ by using the first sliding windows WD_ 1   a  to WD_na in the first direction, which have variable sizes, and a termination parity Partial PT associated with a part of the termination matrix BM_Tb. In this way, the time required to decode the first sub-codeword SubCW_ 1   b ′ may be reduced, and as a result, the data output latency of memory system  1  may be improved. 
     Referring to  FIGS. 2 and 12B , ECC decoder  19   b  may decode the first sub-codeword SubCW_ 1   b ′ based on the first sub-matrix Sub_M 1   b  and a part of a second sub-matrix Sub_M 2   b . That is, ECC decoder  19   b  may set first sliding windows WD_ 1   a  to WD_na in a first direction, which have a fixed size, to include a part of the second sub-matrix Sub_M 2   b . For example, ECC decoder  19   b  may set the last first sliding window WD_na to include a part of the second sub-matrix Sub_M 2   b . ECC decoder  19   b  may decode the first sub-codeword SubCW_ 1   b ′ by using the first sliding windows WD_ 1   a  to WD_na in the first direction, a termination parity PT, and a part Partial SubCW_ 2   b ′ of a second sub-codeword associated with a part of a second sub-matrix Sub_M 2   b . ECC decoder  19   b  may selectively read the part Partial SubCW_ 2   b ′ of the second sub-codeword or the termination parity PT from a buffer in memory controller  10 . In this way, bit error correction capability for the first sub-codeword SubCW_ 1   b ′ may be improved, and thus the reliability of memory system  1  may be improved. 
       FIG. 13  is a block diagram of an embodiment of a memory system  200 . 
     Referring to  FIG. 13 , memory system  200  may include a memory controller  210  and a plurality of memory devices  230 _ 1  to  230 _ k . Memory controller  210  may include a memory interface unit  211 , an ECC logic element  212 , a host interface  213 , a RAM  214  and a central processing unit  215 . In various embodiments, ECC logic element  212  may comprise a logic circuit and/or a processor configured to perform logic operations in response to instructions stored in a memory, etc. Hereinafter, ECC logic element  212  is referred to as “ECC logic  212 ” for convenience of description. ECC logic  212  may include first to kth ECC circuits  212 _ 1  to  212 _ k , and memory interface unit  211  may include first to kth memory interfaces  211 _ 1  to  211 _ k . Memory interfaces  211 _ 1  to  211 _ k  may be connected to memory devices  230 _ 1  to  230 _ k  via channels CH 1  to CHk, respectively. Each of ECC circuits  212 _ 1  to  212 _ k  may divide data received together with a write request from a host and perform parallel encoding to thereby generate sub-codewords. The generated sub-codewords may be stored in memory devices  230 _ 1  to  230 _ k  in a distributed manner. And then, upon receiving a read request for data from the host, each of ECC circuits  212 _ 1  to  212 _ k  may receive the sub-codewords from memory devices  230 _ 1  to  230 _ k  through memory interface unit  211 . Each of ECC circuits  212 _ 1  to  212 _ k  may perform parallel decoding on the received sub-codewords, and then may merge data generated as a result of decoding by using RAM  214  and output the merged data to the host through host interface  213 . However, the embodiment of  FIG. 13  is only an example and is not limited thereto, and encoding/decoding operations may be performed by various methods according to an encoding/decoding operation policy of memory controller  210 . 
       FIGS. 14A, 14B, 14  C, and  14 D are diagrams for explaining embodiments of encoding and decoding methods. 
     Referring to  FIG. 14A , write data received from a host may be divided into first data Data_ 1  and second data Data_ 2 , and a first ECC circuit  212 _ 1  and a second ECC circuit  212 _ 2  may receive the first data Data_ 1  and the second data Data_ 2 , respectively. First ECC circuit  212 _ 1  may encode the first data Data_ 1 , and second ECC circuit  212 _ 2  may encode the second data Data_ 2 . The encoding operation of first ECC circuit  212 _ 1  and the encoding operation of second ECC circuit  212 _ 2  may be performed in parallel. 
     First ECC circuit  212 _ 1  and second ECC circuit  212 _ 2  may share first information SH_Info_ 1  necessary for their respective encoding operations. The first information SH_Info_ 1  may include some or all of the first data Data_ 1 , some or all of the second data Data_ 2 , and at least one of an encoding result for the first data Data_ 1  and an encoding result for the second data Data_ 2 . First ECC circuit  212 _ 1  and second ECC circuit  212 _ 2  may use the first information SH_Info_ 1  when performing the respective encoding operations. 
     First ECC circuit  212 _ 1  may output a first sub-codeword SubCW_ 1  generated by encoding the first data Data_ 1  to a first memory device  230 _ 1  through a first memory interface  211 _ 1 , and second ECC circuit  212 _ 2  may output a second sub-codeword SubCW_ 2  generated by encoding the second data Data_ 2  to a second memory device  230 _ 2  through a second memory interface  211 _ 2 . First memory device  230 _ 1  may store the first sub-codeword SubCW_ 1 , and second memory device  230 _ 2  may store the second sub-codeword SubCW_ 2 . 
     Referring to  FIG. 14B , unlike in  FIG. 14A , first ECC circuit  212 _ 1  may receive write data Data, divide the write data Data into first data and second data, encode the first data and the second data, and output first sub-codeword SubCW_ 1  and second sub-codeword SubCW_ 2 . 
     Referring to  FIG. 14C , first ECC circuit  212 _ 1  may receive a first sub-codeword SubCW_ 1 ′ from first memory device  230 _ 1  through first memory interface  211 _ 1  and decode the first sub-codeword SubCW_ 1 ′. Second ECC circuit  212 _ 2  may receive a second sub-codeword SubCW_ 2 ′ from second memory device  230 _ 2  through second memory interface  211 _ 2  and decode the second sub-codeword SubCW_ 2 ′. The decoding operation of first ECC circuit  212 _ 1  and the decoding operation of the second ECC circuit  212 _ 2  may be performed in parallel. 
     First ECC circuit  212 _ 1  and second ECC circuit  212 _ 2  may share second information SH_Info_ 2  necessary for their respective decoding operations. The second information SH_Info_ 2  may include a part or the entirety of the first sub-codeword SubCW_ 1 ′, a part or the entirety of the second sub-codeword SubCW_ 2 ′, and at least one of a decoding result for the first sub-codeword SubCW_ 1 ′ and a decoding result for the second sub-codeword SubCW_ 2 ′. First ECC circuit  212 _ 1  and second ECC circuit  212 _ 2  may use the second information SH_Info_ 2  when performing the respective decoding operations. 
     First ECC circuit  212 _ 1  may output first data Data_ 1  generated by decoding the first sub-codeword SubCW_ 1 ′, and second ECC circuit  212 _ 2  may output second data Data_ 2  generated by decoding the second sub-codeword SubCW_ 2 ′. 
     Referring to  FIG. 14D , unlike in  FIG. 14C , first ECC circuit  212 _ 1  may receive a codeword generated by merging a first sub-codeword SubCW_ 1 ′ and a second sub-codeword SubCW_ 2 ′. First ECC circuit  212 _ 1  may output data Data generated by decoding the codeword. 
       FIG. 15  is a diagram for explaining the operation of ECC encoder  19   a  of  FIG. 2 , which conforms to the structure of a parity check matrix Hc. 
     Referring to  FIGS. 2 and 15 , the parity check matrix Hc may include first to fourth partial parity check matrices Partial_H 1  to Partial_H 4 . Here, the first to fourth partial parity check matrices Partial_H 1  to Partial_H 4  may be independent matrices and may not be related to each other. Due to independent characteristics of the first to fourth partial parity check matrices Partial_H 1  to Partial_H 4 , correction capability may be degraded during encoding/decoding using the parity check matrix Hc. To compensate for this, the parity check matrix Hc may further include first to third tunneling information T_Info 1  to T_Info 3 . The first tunneling information T_Info 1  may be associated with the first and second partial parity check matrices Partial_H 1  and Partial_H 2  and a first tunneling check equation may be derived through the first tunneling information T_Info 1 . The second tunneling information T_Info 2  may be associated with the second and third partial parity check matrices Partial_H 2  and Partial_H 3  and a second tunneling check equation may be derived through the second tunneling information T_Info 2 . The third tunneling information T_Info 3  may be associated with the third and fourth partial parity check matrices Partial_H 3  and Partial_H 4  and a third tunneling check equation may be derived through the third tunneling information T_Info 3 . 
     ECC encoder  19   a  may encode first data of write data Data received from a host, based on the first partial parity check matrix Partial_H 1 , to thereby generate a first sub-codeword SubCW_ 1   c , encode second data of the write data Data, based on the second partial parity check matrix Partial_H 2 , to thereby generate a second sub-codeword SubCW_ 2   c , encode third data of the write data Data, based on the third partial parity check matrix Partial_H 3 , to thereby generate a third sub-codeword SubCW_ 3   c , and encode fourth data of the write data Data, based on the fourth partial parity check matrix Partial_H 4 , to thereby generate a fourth sub-codeword SubCW_ 4   c . In addition, ECC encoder  19   a  may generate a first tunneling parity P_Tunnel_ 1  by using the first tunneling information T_Info 1 , generate a second tunneling parity P_Tunnel_ 2  by using the second tunneling information T_Info 2 , and generate a third tunneling parity P_Tunnel_ 3  by using the third tunneling information T_Info 3 . The first to third tunneling parities P_Tunnel_ 1  to P_Tunnel_ 3  may satisfy the first to third tunneling check equations, respectively. 
     ECC encoder  19   a  may generate a codeword CWc including the first to fourth sub-codewords SubCW_ 1   c  to SubCW_ 4   c  and the first to third tunneling parities P_Tunnel_ 1  to P_Tunnel_ 3  by encoding the write data Data in the manner described above. A sub-codeword size described with reference to  FIG. 15  and thereafter may be equal to or different from that described before  FIG. 15 . 
       FIG. 16  is a flowchart illustrating an embodiment of a method of generating a tunneling parity. 
     Referring to  FIGS. 2, 15 and 16 , ECC encoder  19   a  may encode first data based on the first partial parity check matrix Partial_H 1  (operation S 200 ). ECC encoder  19   a  may store at least a part of the first sub-codeword SubCW_ 1   c  in a buffer in the memory controller  10  (operation S 210 ). ECC encoder  19   a  may encode second data based on the second partial parity check matrix Partial_H 2  (operation S 220 ). ECC encoder  19   a  may store at least a part of the second sub-codeword SubCW_ 2   c  in the buffer in memory controller  10  (operation S 230 ). Next, ECC encoder  19   a  may generate the first tunneling parity P_Tunnel_ 1 , which satisfies the first tunneling check equation derived by the first tunneling information T_Info_ 1 , by using the at least a part of the first sub-codeword SubCW_ 1   c  stored in the buffer and the at least a part of the second sub-codeword SubCW_ 2   c  stored in the buffer (operation S 235 ). In an embodiment, ECC encoder  19   a  may determine a value, at which a syndrome of a check matrix for tunneling becomes ‘0’, as the first tunneling parity P_Tunnel_ 1  by using the first sub-codeword SubCW_ 1   c  and the second sub-codeword SubCW_ 2   c.    
     ECC encoder  19   a  may encode third data based on the third partial parity check matrix Partial_H 3  (operation S 240 ). ECC encoder  19   a  may store at least a part of the third sub-codeword SubCW_ 3   c  in the buffer in memory controller  10  (operation S 250 ). Next, ECC encoder  19   a  may generate the second tunneling parity P_Tunnel_ 2 , which satisfies the second tunneling check equation derived by the second tunneling information T_Info_ 2 , by using the at least a part of the second sub-codeword SubCW_ 2   c  stored in the buffer and the at least a part of the third sub-codeword SubCW_ 3   c  stored in the buffer (operation S 255 ). 
     ECC encoder  19   a  may encode fourth data based on the fourth partial parity check matrix Partial_H 4  (operation S 260 ). ECC encoder  19   a  may store at least a part of the fourth sub-codeword SubCW_ 4   c  in the buffer in memory controller  10  (operation S 270 ). Next, ECC encoder  19   a  may generate the third tunneling parity P_Tunnel_ 3 , which satisfies the third tunneling check equation derived by the third tunneling information T_Info_ 3 , by using the at least a part of the third sub-codeword SubCW_ 3   c  stored in the buffer and the at least a part of the fourth sub-codeword SubCW_ 4   c  stored in the buffer (operation S 275 ). 
       FIG. 17  is a flowchart illustrating an embodiment of a decoding operation. Hereinafter, the decoding operation is described by focusing on the structure of the parity check matrix Hc of  FIG. 16 . However, embodiments are not limited thereto, and the decoding operation may be applied to the structures of the parity check matrices Ha and Hb of  FIGS. 4 and 7A . 
     An ECC decoder may perform a decoding operation over two phases. First, the ECC decoder may read a target sub-codeword from a buffer in a memory controller (operation S 300 ). The ECC decoder may perform decoding in a sliding window manner on the target sub-codeword by using one partial parity check matrix associated with the target sub-codeword (operation S 310 ). A first phase decoding operation may include operations S 300  and S 310 . Next, the ECC decoder may determine whether the first phase decoding operation is successful (operation S 320 ). When it is determined that the first phase decoding operation is successful (operation S 320 , YES), data generated through decoding may be transmitted to a host (operation S 330 ). When it is determined that the first phase decoding operation fails (operation S 320 , NO), the ECC decoder may select at least one sub-codeword adjacent to the target sub-codeword (operation S 340 ). The ECC decoder may further read a part or the entirety of the selected sub-codeword and a tunneling parity from the buffer in the memory controller (operation S 350 ). Next, the ECC decoder may perform joint decoding in a sliding window manner by using a partial parity check matrix, tunneling information, and the like associated with a part of the selected sub-codeword (operation S 360 ). A second phase decoding operation may include operations S 350  and S 360 . Next, the ECC decoder may determine whether the second phase decoding operation is successful (operation S 370 ). When it is determined that the second phase decoding operation is successful (operation S 370 , YES), data generated through decoding may be transmitted to the host (operation S 330 ). When it is determined that the second phase decoding operation fails (operation S 370 , NO), the ECC decoder may determine that decoding is unsuccessful (operation S 380 ) and end the decoding operation for the target sub-codeword. However, this case is only an example embodiment, and the decoding operation may be performed in more phases until the decoding for the target sub-codeword is successful. Further, as the decoding operation is performed in more phases, the ECC decoder may need more decoding-related data. 
       FIGS. 18, 19A, 19B, 19C, 20A and 20B  are diagrams for explaining various embodiments of the second phase decoding operation of  FIG. 17 . 
     Referring to  FIGS. 2 and 18 , ECC decoder  19   b  may further read a first tunneling parity P_Tunnel_ 1  and a part P_SubCW_ 2   c  of a second sub-codeword from a buffer in memory controller  10  in a second phase decoding operation, and may variably set the sizes of first sliding windows WD_ 1   a  to WD_na in a first direction so that the first sliding windows WD_ 1   a  to WD_na may include first tunneling information T_Info 1  and a part of a second partial parity check matrix Partial_H 2 . For example, ECC decoder  19   b  may set the last first sliding window WD_na to include the first tunneling information T_Info 1  and the part of the second partial parity check matrix Partial_H 2 . ECC decoder  19   b  may perform a second page decoding operation on a first sub-codeword SubCW_ 1   c  by using the first tunneling parity P_Tunnel_ 1 , the part P_SubCW_ 2   c  of the second sub-codeword, and the first sliding windows WD_ 1   a  to WD_na in the first direction which have variable sizes. 
     Referring to  FIGS. 2 and 19A , in the second phase decoding operation, ECC decoder  19   b  may further read a second sub-codeword SubCW_ 2   c  from the buffer in memory controller  10  and perform partial decoding on the second sub-codeword SubCW_ 2   c  based on the second partial parity check matrix Partial_H 2 . Data HD generated by a partial decoding operation may be referred to as hard decision data. 
     Referring to  FIG. 19B , ECC decoder  19   b  may further read a first tunneling parity P_Tunnel_ 1  from the buffer in memory controller  10  and decode a first sub-codeword SubCW_ 1   c ′ based on a first partial parity check matrix Partial_H 1  and a part of first tunneling information T_Info_ 1 . ECC decoder  19   b  may set first sliding windows WD_ 1   a  to WD_na, arranged in a second direction which may be opposite to the first direction and which have a fixed size, to include a part of the first tunneling information T_Info_ 1 . For example, ECC decoder  19   b  may set the first sliding window WD_na to include a part of the first tunneling information T_Info_ 1 . ECC decoder  19   b  may perform a second phase decoding operation on a first sub-codeword SubCW_ 1   c  by using the first sliding windows WD_ 1   a  to WD_na in the second direction, the first tunneling parity P_Tunnel_ 1  (or a part of the first tunneling parity P_Tunnel_ 1 ), and the hard decision data HD. 
     Referring to  FIG. 19C , ECC decoder  19   b  may perform a second phase decoding operation on a first sub-codeword SubCW_ 1   c  by using first sliding windows WD_ 1   a  to WD_na in the first direction, unlike in  FIG. 19B . 
     Referring to  FIG. 20A , ECC decoder  19   b  may determine the degree of decoding failure. When the degree of decoding failure exceeds a threshold, ECC decoder  19   b  may further read an adjacent sub-codeword and a tunneling parity to perform a second phase decoding operation, unlike the second phase decoding operation described with reference to  FIG. 18 . ECC decoder  19   b  may determine the degree of decoding failure based on the number of check nodes that do not satisfy a parity check equation corresponding to the first partial parity check matrix Partial_H 1 . 
     In  FIG. 20A , it is assumed that a first phase decoding operation of ECC decoder  19   b  performed on a second sub-codeword SubCW_ 2   c  has failed. ECC decoder  19   b  may further read a first tunneling parity P_Tunnel_ 1 , a part P_SubCW_ 1   c  of a first sub-codeword, a second tunneling parity P_Tunnel_ 2 , and a part P_SubCW_ 3   c  of a third sub-codeword from a buffer in memory controller  10  in the second phase decoding operation. In addition, ECC decoder  19   b  may set second sliding windows WD_ 1   b  to WD_nb in the first direction to include first tunneling information T_Info_ 1 , a part of a first partial parity check matrix Partial_H 1 , second tunneling information T_Info_ 2 , and a part of a third partial parity check matrix Partial_H 3 . For example, ECC decoder  19   b  may set the first sliding window WD_ 1   b  to include the first tunneling information T_Info_ 1  and a part of the first partial parity check matrix Partial_H 1 , and may set the last second sliding window WD_nb to include the second tunneling Information T_Info_ 2  and a part of the third partial parity check matrix Partial_H 3 . ECC decoder  19   b  may perform a second phase decoding operation on the second sub-codeword SubCW_ 2   c  by using the second sliding windows WD_ 1   b  to WD_nb in the first direction, the first tunneling parity P_Tunnel_ 1 , the part P_SubCW_ 1   c  of the first sub-codeword, the second tunneling parity P_Tunnel_ 2 , and the part P_SubCW_ 3   c  of the third sub-codeword. 
     Referring to  FIG. 20B , ECC decoder  19   b  may determine the degree of decoding failure. When the degree of decoding failure exceeds a threshold, ECC decoder  19   b  may perform a second phase decoding operation after further reading an adjacent sub-codeword and further generating hard decision data, unlike the second phase decoding operation described with reference to  FIG. 19B . 
     In  FIG. 20B , it is assumed that a first phase decoding operation of ECC decoder  19   b  performed on a second sub-codeword SubCW_ 2   c  has failed. ECC decoder  19   b  may further read a first sub-codeword SubCW_ 1   c  and a third sub-codeword SubCW_ 3   c  from a buffer in memory controller  10  in the second phase decoding operation, and may perform a partial decoding operation on the first sub-codeword SubCW_ 1   c  and a partial decoding operation on the third sub-codeword SubCW_ 3   c  to thereby generate first hard decision data HD 1  and second hard decision data HD 2 , respectively. ECC decoder  19   b  may perform a second phase decoding operation on the second sub-codeword SubCW_ 2   c  by using first sliding windows WD_ 1   a  to WD_na in the first direction, first and second tunneling parities P_Tunnel_ 1  and P_Tunnel_ 2 , and first and second hard decision data HD 1  and HD 2 . Furthermore, when a phase operation including the first phase decoding operation and the second phase decoding operation fail, ECC decoder  19   b  may perform a joint decoding operation according to embodiments by using a sub-codeword adjacent to a target sub-codeword to be decoded. 
     In addition, the decoding scheme according to the embodiments is not limited thereto, and a decoding scheme using sliding windows set in different directions, described with reference to  FIG. 6A  or the like, may be applied to one partial parity check matrix. That is, when decoding a sub-codeword based on a partial parity check matrix, the sub-codeword may be divided into smaller data units and the partial parity check matrix may be divided into partial sub-parity check matrices, and thus a bi-directional decoding scheme described with reference to  FIG. 6A  and the like may be applied. 
     As is traditional in the field of the inventive concepts, examples may be described and illustrated in terms of blocks which carry out a described function or functions. These blocks, which may be referred to herein as units or modules or the like, may be physically implemented by analog and/or digital circuits such as logic gates, integrated circuits, microprocessors, microcontrollers, memory circuits, passive electronic components, active electronic components, optical components, hardwired circuits and the like, and may optionally be driven by firmware and/or software. The circuits may, for example, be embodied in one or more semiconductor chips, or on substrate supports such as printed circuit boards and the like. The circuits constituting a block may be implemented by dedicated hardware, or by a processor (e.g., one or more programmed microprocessors and associated circuitry), or by a combination of dedicated hardware to perform some functions of the block and a processor to perform other functions of the block. 
     While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the following claims.