Patent Publication Number: US-6906601-B2

Title: Variable phase shifter and a system using variable phase shifter

Description:
FIELD OF THE INVENTION 
   This invention relates to a signal processing technology, more particularly to a variable phase shifter and a system using the variable phase shifter. 
   BACKGROUND OF THE INVENTION 
   Over the last decade, wireless communication services have been expanded. To provide such services, components of communication equipments have been complicated and large. It is therefore demanded to provide small size wireless communication equipments. In current smart antenna systems, a phase shifter is one of the main components, and is one of the limiting factors for reducing the size and required cost of the smart antenna systems. 
   The current phase shifters are categorized into a DSP phase shifter and a passive phase shifter. The DSP phase shifter converts received digital signals into digital form and performs phase shifting and power combining. The Power consumption in this approach is, however, high, and it requires off-chip components and silicon area. The passive phase shifters are expensive and cannot be integrated in a single chip. 
   Ellinger et al. discloses an adaptive antenna receiver in “An Antenna Diversity MMIC Vector Modulator for HIPERLAN with Low Power Consumption and Calibration Capability (IEEE Transactions on Microwave theory and techniques, Vol. 49, No. 5, May 2001)”.  FIG. 1  shows the vector modular  200  of Ellinger et al. The vector modular  200  includes three paths  201 ,  202  and  203 . For each path, a preamplifier is provided. In the paths  201 - 203 , a lowpass filter  204 , a capacitor  205  and a highpass filter  206  are provided. The gate nodes of three transistors E 50  are connected to the lowpass filter  204 , the capacitor  205  and the highpass filter  206 , respectively. An input signal is applied to the preamplifiers, then to the paths  201 - 203  and is transmitted to the transistors E 50 . The vector modulator  200  achieves 360° phase shift. 
   However, the vector modulator  200  uses multiple pre-amplifiers and multiple inductors. That may result in higher noise and no-linearity of phase shifting, and then result in high cost if it is implemented in silicon. Further, matching circuit is not used between the two amplifiers. That may result in loss, higher noise and higher power consumption. 
   Therefore, it is desirable to provide a new phase shifter, which can meet demands for a small size and low cost, and can be integrated in a single chip with applications. 
   SUMMARY OF THE INVENTION 
   It is an object of the invention to provide a novel phase shifter and a system that obviates or mitigates at least one of the disadvantages of existing systems. 
   In accordance with an aspect of the present invention, there is provided a variable phase shifter that has an input node for receiving an input signal, a first path and a second path for performing analog signal processing, an output node for combining the outputs of the first path and the second path to provide an output signal, and a bias controller for generating first and second bias signals in response to a phase control signal for controlling amplification of first and second active devices. The first path includes a first fixed phase shift element for shifting the phase of the input signal by a first shift value, and the first active device for amplifying the output of the first phase shift element. The first active device is inductively coupled to a ground via a first element of the first fixed phase shift element. The second path includes a second fixed phase shift element for shifting the phase of the input signal by a second shift value, and the second active device for amplifying the output of the second phase shift element. The second active device is inductively coupled to a ground via a second element of the second fixed phase shift element. 
   In accordance with a further aspect of the present invention, there is provided a smart antenna front end system that has a receiver for receiving an RF receiving signal from an antenna, including first and second variable phase shifter, and a transmitter for transmitting an RF transmitting signal from the antenna, including third and forth variable phase shifter. Each of the first, second, third and forth variable phase shifter includes an input node for receiving an input signal, a first path and a second path for performing analog signal processing, an output node for combining the outputs of the first path and the second path to provide an output signal, and a bias controller for generating first and second bias signals in response to a phase control signal for controlling amplification of first and second active devices. The first path includes a first fixed phase shift element for shifting the phase of the input signal by a first shift value, and the first active device for amplifying the output of the first phase shift element. The first active device is inductively coupled to a ground via a first element of the first fixed phase shift element. The second path includes a second fixed phase shift element for shifting the phase of the input signal by a second shift value, and the second active device for amplifying the output of the second phase shift element. The second active device is inductively coupled to a ground via a second element of the second fixed phase shift element. 
   In accordance with a further aspect of the present invention, there is provided a smart antenna front end system that has a local oscillator path including an local oscillator, and first and second variable phase shifter for shifting the phase of an input signal output from the local oscillator, a receiver for receiving an RF receiving signal from an antenna, and a transmitter for transmitting an RF transmitting signal from the antenna. The receiver includes a first mixer for mixing the RF receiving signal and the output of the first variable phase shifter, and a second mixer for mixing the RF receiving signal and the output of the second variable phase shifter. The transmitter includes a third mixer for mixing an IF signal and the output of the first variable phase shifter, and a fourth mixer for mixing the IF signal and the output of the second variable phase shifter. Each of the first and second variable phase shifter has an input node for receiving an input signal, a first path and a second path for performing analog signal processing, an output node for combining the outputs of the first path and the second path to provide an output signal, and a bias controller for generating first and second bias signals in response to a phase control signal for controlling amplification of first and second active devices. The first path including a first fixed phase shift element for shifting the phase of the input signal by a first shift value, and the first active device for amplifying the output of the first phase shift element. The first active device is inductively coupled to a ground via a first element of the first fixed phase shift element. The second path includes a second fixed phase shift element for shifting the phase of the input signal by a second shift value, and the second active device for amplifying the output of the second phase shift element. The second active device is inductively coupled to a ground via a second element of the second fixed phase shift element. 
   In accordance with a further aspect of the present invention, there is provided a differential phase shifter that has first and second variable phase shifters for receiving input signals. Each of the input signals is similar in amplitude and 180° out of phase. Each of the first and second variable phase shifters has an input node for receiving the corresponding input signal, a first path and a second path for performing analog signal processing, an output node for combining the outputs of the first path and the second path to provide an output signal, and a bias controller for generating first and second bias signals in response to a phase control signal for controlling amplification of first and second active devices. The first path includes a first fixed phase shift element for shifting the phase of the input signal by a first shift value, and the first active device for amplifying the output of the first phase shift element. The first active device is inductively coupled to a ground via a first element of the first fixed phase shift element. The second path includes a second fixed phase shift element for shifting the phase of the input signal by a second shift value, and the second active device for amplifying the output of the second phase shift element. The second active device is inductively coupled to a ground via a second element of the second fixed phase shift element. 
   Other aspects and features of the present invention will be readily apparent to those skilled in the art from a review of the following detailed description of preferred embodiments in conjunction with the accompanying drawings. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The invention will be further understood from the following description with reference to the drawings in which: 
       FIG. 1  is a schematic diagram showing a conventional vector modulator; 
       FIG. 2  is a block diagram showing a variable active phase shifter in accordance with an embodiment of the present invention; 
       FIG. 3  is a diagram showing an example of the phase shifter  10  of  FIG. 2 ; 
       FIG. 4A  is a diagram showing an additional component applied to the phase shifter of  FIG. 2 ; 
       FIG. 4B  is a diagram showing an additional component applied to the phase shifter of  FIG. 2 ; 
       FIG. 5  is a diagram showing a further example of the phase shifter of  FIG. 2 ; 
       FIG. 6  is a schematic diagram showing a further example of the phase shifter of  FIG. 2 ; 
       FIGS. 7A-7F  are diagrams showing examples of the LC ladder of  FIG. 3 ; 
       FIGS. 8A-8F  are diagrams showing examples of the LC ladder of FIG.  3 : 
       FIG. 9A  is a diagram showing an additional component combined with the fixed phase shift element of  FIG. 2 ; 
       FIG. 9B  is a diagram showing an additional component combined with the fixed phase shift element of  FIG. 2 ; 
       FIG. 9C  is a diagram showing the examples of the additional components of  FIGS. 9A-9B ; 
       FIG. 10  is a schematic diagram showing a further example of the phase shifter of  FIG. 2 ; 
       FIG. 11  is a schematic diagram showing a further embodiment of the phase shifter of  FIG. 10 ; 
       FIG. 12  is a schematic diagram showing an example of the bias controller of  FIG. 2 ; 
       FIG. 13  is a graph showing the operation of the bias controller of  FIG. 12 ; 
       FIG. 14  is a block diagram showing a smart antenna front-end/transceiver system using the phase shifter of  FIG. 2 ; 
       FIG. 15  is a diagram showing an example of a smart receiver for the smart antenna front-end/transceiver system of  FIG. 14 ; 
       FIG. 16  is a diagram showing an example of a smart transmitter for the smart antenna front-end/transceiver system of  FIG. 14 ; 
       FIG. 17  is a block diagram showing a further example of a smart antenna front-end/transceiver system using the phase shifter of  FIG. 2 ; 
       FIG. 18  is a diagram showing anther example of a smart antenna front-end/transceiver system using the phase shifter of  FIG. 2 ; 
       FIG. 19  is a schematic diagram showing a 2.5 GHz phase shifter of  FIG. 2  implemented in 0.18 μm CMOS; 
       FIG. 20  is a graph showing phase (°) vs. control voltage for the phase shifter of  FIG. 19 ; 
       FIG. 21  is a graph showing gain (dB) vs. control voltage for the phase shifter of  FIG. 19 ; 
       FIG. 22  is a schematic diagram showing a 2.5 GHz phase shifter of  FIG. 2  implemented with bipolar transistor; 
       FIG. 23  is a graph showing phase (°) vs. control voltage for the phase shifter of  FIG. 22 ; 
       FIG. 24  is a graph showing gain (dB) vs. control voltage for the phase shifter of  FIG. 22 ; 
       FIG. 25  is a schematic diagram showing a 5 GHz phase shifter of  FIG. 2  implemented with bipolar transistor; 
       FIG. 26  is a graph showing phase (°) vs. control voltage for the phase shifter of  FIG. 25 ; 
       FIG. 27  is a graph showing gain (dB) vs. control voltage for the phase shifter of  FIG. 25 ; 
       FIG. 28  is a schematic diagram showing a 5 GHz phase shifter of FIG.  2  and an LNA implemented with bipolar transistor; 
       FIG. 29  is a graph showing phase (°) vs. control voltage for the phase shifter of  FIG. 28 ; 
       FIG. 30  is a graph showing gain (dB) vs. control voltage for the phase shifter of  FIG. 28 ; 
       FIG. 31  is a diagram showing a smart antenna front-end system using the phase shifter of  FIG. 2 ; and 
       FIG. 32  is a diagram showing an example of the smart antenna front-end system of FIG.  31 . 
   

   DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 2  shows a variable active phase shifter  10  in accordance with an embodiment of the present invention. The phase shifter  10  includes fixed phase shift elements S 1  and S 2 , active devices Q 1  and Q 2 , and a combiner  12 . The fixed phase shift elements S 1  and S 2  are connected to an input node RF IN. The fixed phase shift elements S 1  and S 2  phase-shift an input signal (e.g. RF signal) by predetermined shift values. The active devices Q 1  and Q 2  receive the outputs of the fixed phase shift elements S 1  and S 2 , respectively, and amplify them. The controller  14  generates bias signals B 1  and B 2  in response to a phase control signal  16  for controlling the gain of the amplification of the active devices Q 1  and Q 2 . The combiner  12  combines the outputs of the active devices Q 1  and Q 2 . The combiner  12  is connected to an output node RF OUT. 
   In  FIG. 2 , two fixed phase shift elements S 1  and S 2  and two active devices Q 1  and Q 2  are shown. However, the active phase shifter  10  may have more than 3 fixed phase shift elements, and may have more than 3 active devices. 
   The active phase shifter  10  may be integrated into Radio Frequency Integrated Circuits (RFICs). The active phase shifter  10  may be part of a smart antenna front-end system and fabricated as System On a Chip (SOC). 
     FIG. 3  shows an example of the phase shifter  10  of FIG.  2 . The fixed phase shift element S 1  of  FIG. 3  includes an LC ladder # 1  and an inductor L 1  (inductance L 1 ). The fixed phase shift element S 2  of  FIG. 3  includes an LC ladder # 2  and an inductor L 2  (inductance L 2 ). Each of the active devices Q 1  and Q 2  is a NPN or NMOS transistors, and a common source (or a emitter) amplifier. The combiner  12  of  FIG. 3  is an adder, which is a node connected to the active devices Q 1  and Q 2 . 
   Each of the LC ladder may include a resistor, an inductor, a capacitor or any combination of such elements. The phase shift element S 1  acts as a sine component. The phase shift element S 2  acts as a cosine component. To obtain different phase range, different phase shift components S 1  and S 2 , are provided. 
   The LC ladders # 1  and # 2  are connected to the input node RF IN. The output of the LC ladder # 1  is connected to the active node  5  of the active device Q 1 . The output of the LC ladder # 2  is connected to the active node  5  of the active device Q 2 . The active node  5  may be a gate or a base. 
   The inductors L 1  and L 2  are used for balancing gain and phase. The inductor L 1  is connected between the ground and the node  4  of the active device Q 1 . The inductor L 2  is connected between the ground and the node  4  of the active device Q 2 . The node  4  may be a source or an emitter. The nodes  3  of the active devices Q 1  and Q 3  are connected to the adder  12 . The node  3  may be a drain or a collector. The adder  12  is connected to the output node RF OUT. 
   The active device Q 1  connects the inductor L 1  to the adder  12  in response to the voltage of the node  5 . The active device Q 2  connects the inductor L 2  to the adder  12  in response to the voltage of the node  5 . 
   The bias controller  14  of  FIG. 3  is connected to the active nodes  5  of the active devices Q 1  and Q 2  to control their bias based on the phase control signal  16 . The nodes  5  of the active devices Q 1  and Q 2  receive the bias signals B 1  and B 2  from the bias controller  14 , respectively. 
   As described above, the adder  12  of  FIG. 3  is a connection node. As the outputs (e.g., collectors or drains) of the active devices Q 1 -Q 2  are current sources, power combination is achieved by connecting collectors or drains of the active devices Q 1  and Q 2  in one node  12 . 
   The output of the adder  12  meets the following equation (1). 
                   A   1     ⁢     Sin   ⁡     (     ω   ⁢           ⁢   t     )         +       A   2     ⁢     Cos   ⁡     (     ω   ⁢           ⁢   t     )           =           A   1   2     +     A   2   2         ×     Sin   ⁡     (       ω   ⁢           ⁢   t     +       tan     -   1       ⁡     (       A   2       A   1       )         )                 (   1   )             
 
where A 1  represents gain (voltage) X input signal (peak voltage) of path N 1 , A 2  represents gain (voltage) X input signal (peak voltage) of path N 2 , ω represents the frequency of the input signal. In  FIG. 3 , the path N 1  includes the LC ladder # 1  and the active device Q 1 , and the path N 2  includes the LC ladder# 2  and the active device Q 2 .
 
   To control output phase, bias (gain) of two sine and cosine components are set as follows: 
               A   1     ∝         I   c     ⁡     (     Q   1     )         L   1               (   2   )                 A   2     ∝         I   c     ⁡     (     Q   2     )         L   2               (   3   )             
 
where I c  (Q 1 ) represents Idc current of the device Q 1 , and I c  (Q 2 ) represents Idc current of the device Q 2 .
 
For A 1  (0→1) and A 2  (0→1), therefore 
       (       A   2       A   1       )       
 
is from 0 to ∞, and output phase control 
         tan     -   1       ⁡     (       A   2       A   1       )         
 
will be (0→90°).
 
   Preferably, the inductors L 1  and L 2  are fabricated by bondwire, and may be on-chip inductors. The active devices Q 1  and Q 2  may be Si BJT, Si Bi-CMOS, Si CMOS, SiGe Bi-CMOS, SiGe HBT, GaAs HBT or GaAs MESFET. Value of L 1  and L 2  and size of Q 1  and Q 2  may be different to compensate for gain variation. To increase phase range, two or more phase shifter may be use in series. 
   To compensate for unwanted gain variation of the phase shifter  10 , an amplifier may be provided to the phase shifter  10 .  FIGS. 4A and 4B  show how the gain of the phase shifter  10  is adjusted using an amplifier  20 . In  FIG. 4A , the amplifier  20  is connected to the output of the phase shifter  10 . In  FIG. 4B , the amplifier  20  is connected to the input of the phase shifter  10 . The phase control signal  16  is applied to the phase shifter  10  and the amplifier  20 . Based on the phase control signal  16 , the gain of the phase shifter  10  is adjusted using a lookup table for calibration. The amplifier  20  may be a low noise amplifier (LNA). 
     FIG. 5  shows a further example of the phase shifter  10  to compensate for gain variation. In  FIG. 5 , the bias controller  14  is shown separately from a phase shifter  10 X. The phase shifter  10 X is similar to the phase shifter  10  of FIG.  1  and has similar elements as those of the phase shifter  10  except for the bias controller  14 . The phase shifter  10 X outputs a total bias control signal  18 , which is applied to the bias controller  14 . When the bias controller  14  receives the total bias control signal  18 , the bias controller  14  changes the values of the bias signals B 1  and B 2  without changing their ratio. 
   The total bias control signal is, for example, the total bias of the phase shifter  10 . In  FIG. 3 , total bias is, for example, expressed by (base current I B1  of Q 1 +base current I B2  of Q 2 ), and is proportional to gain of the phase shifter  10 . 
     FIG. 6  illustrates a schematic diagram showing a further example of the phase shifter  10  of FIG.  2 . The phase shifter  10  of  FIG. 6  includes the fixed phase shift elements S 1 -S 3 . The fixed phase shift element S 3  has an LC ladder # 3 , an inductor L 3  and an active device Q 3 . The active device Q 3  is activated by the output of the LC ladder # 3  and connects the inductor L 3  to the adder  12 . 
   The LC ladder # 3  may be similar to the LC ladder # 1  or # 2 , and have a resister to adjust the gain, an inductor, a capacitor or any combination of these elements. The active device Q 3  may be a NPN or NMOS transistor, and is similar to the active devices Q 2 -Q 3 . The Inductor L 3  may be similar to the inductors L 1 -L 2 . 
   The bias controller  14  is connected to the active nodes  5  of the active devices Q 1 -Q 3 , and generates bias signals B 1 -B 3  in response to the phase control signal  16  to control the bias of the active devices Q 1 -Q 3 . In  FIG. 6 , three fixed phase shift elements S 1 -S 3  are shown. However, the phase shifter  10  may include more than four fixed phase shift elements and the corresponding active devices. 
   The fixed phase shift element of the phase shifter  10  shown in  FIG. 4  is further described in detail.  FIGS. 7A-7F  show examples of the LC ladder # 1  of FIG.  3 .  FIGS. 8A-8F  show examples of the LC ladder # 2  of FIG.  3 . In  FIGS. 7A-7F  and  8 A- 8 F, a node  30  is connected to the node RF IN shown in  FIG. 2 , and a node  32  is connected to the active devices Q 1  and Q 2  so as to control their activations. 
   Additional component may be provided to the fixed phase shift element shown in  FIG. 2  for impedance matching as shown in  FIGS. 9A-9B .  FIGS. 9A-9B  show examples of additional components combined with the fixed phase shift element of FIG.  2 . As shown in  FIGS. 9A-9B , a component Z may be connected to a fixed phase shift element S 0 . The fixed phase shift element SO may be the fixed phase shift element S 1 , S 2  or S 3  shown in  FIGS. 2 ,  3  and  6 .  FIG. 9C  shows examples of the component Z. The component Z is may be a capacitor, an inductor, a resistor or any combination of these elements, and may be added to the input node and/or the output node of the fixed phase shift element S 0 . 
     FIG. 10  illustrates a schematic diagram showing a further example of the phase shifter  10  of FIG.  2 . The phase shift element S 1  of  FIG. 10  includes a inductors L 0  and L 1 , and a capacitor C 1 . “R 0 ” in  FIG. 10  represents series resistance (Q) of L 0 . The inductor L 0  is connected to the active node  5  of the active device Q 1 . The, capacitor C 1  is connected between the nodes  4 - 5  of the active device Q 1 . The phase shift element S 2  of  FIG. 10  includes the inductor L 2  and a capacitor C 2 . The capacitor C 2  is connected to the active node  5  of the active device Q 2 . Between the input node RF IN and the inputs of the first and second fixed phase shift elements S 1  and S 2 , a capacitor C 3  is provided for input impedance matching. Further, a load component Z 1  is connected to the output node RF OUT. 
   Preferably, the inductors L 1  and L 2  are inductors fabricated by bondwire, and the inductor L 0  is on-chip inductor. 
   The phase shift element S 1  may include a resistor, or may include more than one inductor. Such resistor(s) and/or inductor(s) may be connected in series. The phase shift element S 2  may include more than one capacitor, which are connected in series. Further, a series of capacitors/inductors may be provided between the input node RF IN and the inputs of the fixed phase shift elements. 
     FIG. 11  shows a further embodiment of a phase shifter of FIG.  10 . The differential phase shifter of  FIG. 11  includes a phase shifter  10 A and  10 B. The phase shifters  10 A- 10 B are similar to the phase shifter  10  of FIG.  10 . 
   The phase shifter  10 A receives an input signal RF 1 , and the phase shifter  10 B receives an input signal RF 2 . Two input signals RF 1  and RF 2  are equal in amplitude and 180° out of phase. The phase control signal  16  is provided to the bias controllers  14  in the phase shifters  10 A and  10 B. The outputs of the phase shifters  10 A and  10 B, i.e. RF OUT 1  and RF OUT 2 , are same signal and 180° out of phase. 
   The bias controller  14  of  FIG. 2  is further described in detail.  FIG. 12  shows an example of the bias controller  14  of FIG.  2 . The bias controller  14  of  FIG. 12  includes a current mirror circuit to provide two signals from output nodes Out  1  and Out  2 . 
   The bias controller  14  includes active devices Q 10 -Q 15 , resistors R 1 -R 7 . The active devices Q 10 -Q 13  may be a PNP or a PMOS transistor. The active devices Q 14 -Q 15  may be a NPN or a NMOS transistor. The connection node of the resistors R 2 -R 3  is set to Vcc/2. The active amplifier Q 12  is connected between the active amplifier Q 11  and the resistor R 5 , and is activated by the phase control signal  16 . The active amplifier Q 13  is connected between the active amplifier Q 11  and the resistor R 7 , and is activated by the Vcc/2. The output node Out 1  of the bias controller  14  is connected to the active device (e.g. Q 1  of  FIG. 2 ) of the phase shifter (i.e.  10  of  FIGS. 2 ,  3  and  6 ). The output node Out 2  of the bias controller  14  is connected to the active device (e.g. Q 2  of  FIG. 2 ) of the phase shifter  10 . 
   Current I 11  between the active amplifier Q 12  and the resistor R 5  and current I 12  between the active amplifier Q 13  and the resistor R 7  meet the equation (4).
 
 I   11 + I   12 =constant  (4)
 
   The sum of I 11  and I 12  is controlled by the value of the resistor R 1  and mirror ratio, i.e. the ratio of size of the PNPs (or of PMOSs) Q 10 -Q 11 .  FIG. 13  shows how the current  11  and  112  are changed by the phase control signal  16 . As shown in  FIG. 13 , when the voltage of the phase control signal  16  is equal to Vcc/2, which is a gate/base voltage of the active amplifier Q 13 , the current I 11  is equal to the current I 12 . 
   A smart antenna front-end is now described in detail.  FIG. 14  shows an example of a smart antenna front-end/transceiver system  50  using the phase shifter  10  of FIG.  2 . The smart antenna front-end/transceiver system  50  includes a smart receiver  52  and a smart transmitter  54 .  FIG. 15  shows an example of the smart receiver  54  for the smart antenna front-end system of FIG.  14 .  FIG. 16  shows an example of the smart transmitter  54  for the smart antenna front-end/transceiver system  50  of FIG.  14 . 
   The smart receiver  52  includes the phase shifters  10 C and  10 E. The smart transmitter  54  includes the phase shifters  10 D and  10 F. The phase shifters  10 C- 10 F may be similar to the phase shifter  10  shown in  FIG. 3 ,  6  or  10 . 
   An antenna  56  is provided to the phase shifters  10 C and  10 E. An antenna  58  is provided to the phase shifters  10 D and  10 F. One of the phase shifter  10 C and  10 E is selectively connected to the antenna  56  by a switch  60 . One of the phase shifter  10 B and  10 D is selectively connected to the antenna  58  by a switch  62 . A connection node RF OUT 0  connects the output node RF OUT of the phase shifter  10 C and the output node RF OUT of the phase shifter  10 D. 
   As described above, power combination is achieved with connected collectors or drains of active devices in the phase shifters. 
   A transceiver  72  receives the output of the phase shifter  10 C and/or  10 D, and processes it to output data to a processor (not shown). The transceiver  72  receives data from the processor (not shown) and outputs an RF single to the phase shifters  10 E and  10 F. 
   A matching circuit  74  may be provided between the phase shifter  10 C and  10 D and the transceiver  72  for impedance matching to the input of the transceiver  70  (e.g., 50 ohms). A component Z 1   a  may be connected to the output node RF OUT 0  as described in  FIGS. 9A-9C . 
   A matching circuit  76  may be provided between the phase shift elements  10 D and  10 F and the transceiver  70  for impedance matching to the input of transceiver  70  (e.g. 50 ohms). Components Z 1   b -Z 1   c  may be connected to the output nodes RF OUT of the phase shifter  10 E and  10 F, respectively, as described in  FIGS. 9A-9C . 
   The transceiver  72  has a received signal strength indicator (RSSI). The RSSI outputs a signal corresponding the received RF signal strength. The output signal (referred to as RSSI) is supplied to the phase controller  78 . The phase controller  78  outputs the phase control signal  16  based on the RSSI. The phase control signal  16  is provided to the bias controller  14  of each phase shifter. Accordingly, during receiving RF signal, the phase controller  78  changes the phase of the input RF signal and monitor RSSI to maximize the strength of the receiving RF signal. Further, the phase controller  78  keeps phase status (voltages) in its memory (not shown) and uses the phase status for transmission. 
   LNAs  64  and  66  may be provided to the inputs (i.e. RF IN of  FIG. 2 ) of the phase shifter  10 C and  10 D, respectively, as described in FIG.  4 A. Power Amplifiers (PAs)  68  and  70  may be provided to the outputs (i.e. RF OUT of  FIG. 2 ) of the phase shifter  10 E and  10 F, respectively, as described in FIG.  4 B. 
   In  FIG. 14 , two antennas  56  and  58  are shown. However, more than two antennas may be provided for better reception of RF signals. 
     FIG. 17  shows a further example of a smart antenna front-end/transceiver system  80  using the phase shifter  10  of FIG.  2 . The smart antenna front-end/transceiver system  80  of  FIG. 17  includes phase shifters  10 G and  10 H. The phase shifters  10 G and  10 H receive the output of a local oscillator  82  and output signals φ 1  and φ 2 , respectively. The phase shifters  10 G and  10 H may be similar to the phase shifter  10  shown in  FIG. 3 ,  6  or  10 . The smart antenna front-end system  80  further includes a smart receiver  84  and a smart transmitter  86 . 
   The smart receiver  84  includes mixers  88  and  90  and an adder  92 . The signals φ 1  and φ 2  are mixed with the outputs of the LNAs  64  and  66  at the mixers  88  and  90 , respectively. The adder  92  adds the outputs of the mixers  88  and  90  and outputs an IF signal with a desired phase. 
   The smart transmitter  86  includes mixers  94  and  96 . The signals φ 1  and φ 2  are mixed with an IF signal at the mixers  94  and  96 , respectively. The transmitter  86  outputs an RF signal with a desired phase. 
     FIG. 18  shows a further example of a smart antenna front-end/transceiver system  100  using the phase shifter  10  of FIG.  2 . The smart antenna front-end/transceiver system  100  includes a smart receiver  102  and a smart transmitter  104 . The smart receiver  102  includes phase shifters  10 I and  10 J. The smart transmitter  104  includes phase shifters  10 K and  10 L. The phase shifters  10 I- 10 L may be the phase shifter  10  shown in  FIG. 3 ,  6  or  10 . 
   At a receiving side, the outputs of the phase shifters  10 I and  10 J are inputted to a mixer  106 . The mixer  106  mixes its input with the output of a local oscillator  108  to output an IF signal. At a transmitting side, a mixer  110  mixes an IF signal with the output of a local oscillator  112 . The output of the mixer  110  is provided to the phase shifters  10 K and  10 L. 
     FIG. 19  shows a 2.5 GHz phase shifter  10  of  FIG. 2  implemented in 0.18 μm CMOS. The fixed phase shift element S 1  of  FIG. 19  includes the transistor R 0  (8 nH) and the inductor L 1  (0.8 nH). The fixed phase shift element S 2  of  FIG. 19  includes the capacitor C 2  (4 pF) and the inductor L 2  (1 nH). The bias controller  14 A of  FIG. 19  includes PMOS transistors Q 10  (W=10μ), Q 11  (W=100μ), Q 12 -Q 23 , NMOS transistors Q 14 -Q 15  (0.18 μ, W=10μ), a current source  120  (1 m) and resistors R 10 -R 11 (8 k). A component Z 5  is provided to the output node RF OUT. 
     FIG. 20  shows phase (°) of the output signal on RF OUT vs. phase control voltage (i.e., voltage of the phase control signal  16 ) for the phase shifter of FIG.  19 .  FIG. 21  shows gain (db) vs. control voltage for the phase shifter of FIG.  19 . 
   FIG. 22 shows a 2.5 GHz phase shifter  10  implemented with bipolar transistor. The fixed phase shift element S 1  of  FIG. 22  includes the resistor RO (7 nH) and the inductor L 1  (3 nH). The fixed phase shift element S 2  of  FIG. 22  includes the resistor R 12 (1 nH), the capacitor C 2  (8 pF) and the inductor L 2 (1 nH). The bias controller  14 B shown in  FIG. 22  includes PMOS transistors Q 10  (W=10μ), Q 11  (W=100μ), Q 12 -Q 23 , NPN transistors Q 14 -Q 15 , a current source  120  (1 m) and resistors R 10 -R 11  (8 k). 
     FIG. 23  shows phase (°) of the output signal on RF OUT vs. phase control voltage (i.e., voltage of the phase control signal  16 ) for the phase shifter of FIG.  22 .  FIG. 24  shows gain (db) vs. control voltage for the phase shifter of FIG.  22 . 
     FIG. 25  shows a 5 GHz phase shifter  10  implemented with bipolar transistor. The fixed phase shift element S 1  of  FIG. 25  includes the resistor R 0  (20) and the inductors L 0  (1 nH) and L 1  (1 nH). The fixed phase shift element S 2  of  FIG. 25  includes the capacitor C 2  (5 pF) and the inductor L 2  (0.3 nH). The bias controller  14 B shown in  FIG. 25  includes the current source  122  (0.05 m). Component Z 5  (3 nH) and Z 6  (0.12 pF) are provided to the output node RF OUT. 
     FIG. 26  shows phase (°) of the output signal on RF OUT vs. phase control voltage (i.e., voltage of the phase control signal  16 ) for the phase shifter of FIG.  25 .  FIG. 27  shows gain (db) vs. control voltage for the phase shifter of FIG.  25 . 
     FIG. 28  shows a 5 GHz phase shifter  10  and an LNA  122  implemented with bipolar transistors. The fixed phase shift element S 1  of  FIG. 28  includes the resistor R 0  ( 4 ) and the inductors L 0  (0.7 nH) and L 1  (1.1 nH). The fixed phase shift element S 2  of  FIG. 28  includes the capacitor C 2  (1.6 pF) and the inductor L 2  (0.2 nH). The bias controller  14 B shown in  FIG. 28  includes the current source  122  (0.05 m). Components Z 5  (9 nH) and Z 7  (2 nH) are provided to the output node RF OUT. 
   The LAN  122  is provided between the input node RF IN and the input nodes of the fixed phase shift elements S 1  and S 2 . The LAN  122  includes capacitors C 5  (3 pF) and C 6 -C 7  (0.3 pF), resistors R 15 -R 16  (8 k), inductors L 5 -L 6  (2 nH) and L 7 -L 8 (1.5 nH), NPN transistors Q 20 -Q 23  and current sources  124 - 126 (1 m). The LAN  122  pre-amplifies an input signal to provide the amplified input signal to the fixed phase shift elements S 1  and S 2 . The component Z 5  (9 nH) and Z 7 (2 nH) are provided to the output node RF OUT. 
     FIG. 29  shows phase (°) of the output signal on RF OUT vs. phase control voltage (i.e., voltage of the phase control signal) for the phase shifter of FIG.  28 .  FIG. 30  shows gain (dB) vs. control voltage for the phase shifter of FIG.  28 . 
   As shown in  FIGS. 23-24 ,  26 - 27  and  29 - 30 , the phase shifter  10  increases linearity and stability of phase shifting. 
     FIG. 31  shows a further example of a smart antenna front-end system  130  using the phase shifter  10  of FIG.  2 . The smart antenna front-end system  130  of 
     FIG. 31  includes the phase shifters  136  and  138  connected to the antennas  56  and  58 , phase shifters  136  and  138  and a combiner  140 . Each of the phase shifters  136  and  138  performs phase-shifting ranging from 0 to 90°. Each of the phase shifters  136  and  138  is similar to the phase shift  10  shown in FIG.  2 . The combiner  140  combines the outputs of the phase shifters  136  and  138 . The smart antenna front-end system  130  may include preamplifiers  132  and  134  for pre-amplifying an input signal to provide the amplified signal to the phase shifters  136  and  138 . 
     FIG. 32  shows an example of the smart antenna front-end system  130  of FIG.  31 . The phase shifter  136  includes the fixed phase shift elements S 1   a  and S 1   b . The phase shifter  138  includes the fixed phase shift elements S 1   b  and S 2   b . The component Z may be provided to the output node RF OUT. 
   The fixed phase shift element S 1   a  has a capacitor C 10  and an inductor L 10 , and is connected to an active device Q 31 . The fixed phase shift element S 2   a  has inductors L 11  and L 12 , and is connected to an active device Q 32 . The inductors L 10  and L 12  are similar to the inductor L 1  or L 2  of FIG.  3 . The active devices Q 31  and Q 32  may be a NPN or NMOS transistor. The fixed phase shift element S 1   b  has a capacitor C 11  and an inductor L 13 , and is connected to an active device Q 33 . The fixed phase shift element S 2   b  has inductors L 14  and L 15 , and is connected to an active device Q 34 . The inductors L 13  and L 15  are similar to the inductor L 1  or L 2  of FIG.  3 . The active devices Q 33  and Q 34  may be a NPN or NMOS transistor. 
   The bias of each active device Q 31 -Q 34  is controlled by the bias controller (i.e.  14  of FIG.  2 ). 
   As described in equation (5), range of phase shifter ( 136  and  138 ) is 180°:
 
ΔØ=(0°→90°)−(0°→90°)=90°→−90°  (5) 
 
   According to the embodiment of the present invention, the phase shifter  10  uses minimum transistors and amplifiers to improve overall linearity and stability for phase shifting. 
   Mutiple amplifiers cause nonlinearity. Since the phase shifter  10  does not have a preamplifier for each path, that results in linearity and stability for phase shifting and size reduction. 
   An on-chip inductor is large and expensive, and creates unwanted EM and substrate coupling especially in silicon. Multiple on-chip inductors require high cost, and cause gain loss and unwanted RF coupling of phase shifting circuit. The phase shifter  10  of  FIG. 10  uses one on-chip inductor (L 0 ). That results in low cost and linearity and stability of phase shifting. 
   According to the embodiment of the present invention, input and output impedances are well matched. That allows gain loss, noise and power consumption to be lower. 
   Further, the phase shifter  10  is suitably implemented on silicon CMOS/bipolar, since the phase shifter  10  has few inductors, and the input/output matching is performed. The phase shifter  10  can be integrated on a Radio Frequency Integrated Circuit (RFIC). That enables smart antenna on a single chip. 
   While particular embodiments of the present invention have been shown and described, changes and modifications may be made to such embodiments without departing from the true scope of the invention.