Patent Publication Number: US-9898068-B2

Title: Semiconductor device, electronic device, and method for controlling semiconductor device

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is based upon and claims the benefit of priority from Japanese patent application No. 2013-012958, filed on Jan. 28, 2013, the disclosure of which is incorporated herein in its entirety by reference. 
     BACKGROUND 
     The present invention relates to a semiconductor device, an electronic device, and a method for controlling a semiconductor device. 
     It is required that power consumption of semiconductor devices be reduced while also ensuring the required performance thereof. 
     For example, Japanese Unexamined Patent Application Publication No. 2002-288150 discloses a semiconductor integrated circuit device including a high-performance central processing unit (CPU), a low-power-consumption CPU, a process judgment unit, a power supply voltage control management unit, and a clock supply control unit. The process judgment unit determines whether the high-performance CPU or the low-power-consumption CPU is the optimum CPU to be used, on the basis of a process to be executed by the semiconductor integrated circuit device. The power supply voltage control management unit controls power supply to the high-performance CPU and the low-power-consumption CPU on the basis of the determination result made by the process judgment unit. The clock supply control unit controls clock supply to the high-performance CPU and the low-power consumption CPU on the basis of the determination result made by the process judgment unit. 
     Japanese Unexamined Patent Application Publication No. 2005-285093 discloses a power supply device for supplying power to a processor. The power supply device includes a required task performance table, a power mode table, a required system performance calculation block, and a power mode determination block. The required task performance table stores performance required for each of a plurality of tasks to be executed by the processor. In the power mode table, an operating frequency and an application voltage which the processor uses to achieve required system performance are defined. The required system performance calculation block calculates required system performance on the basis of the required task performance table. The power mode determination block sets the operating frequency and application voltage of the processor on the basis of the required system performance calculated by the required system performance calculation block and the power mode table. 
     SUMMARY 
     The inventors have found various problems when developing semiconductor devices. Each of the embodiments disclosed in the present application provides a semiconductor device which allows performance to follow a dynamically changing load. 
     Other problems and novel characteristics will be apparent from the description of the present specification and the accompanying drawings. 
     A semiconductor device according to one embodiment includes a frequency regulating circuit including a table. The frequency regulating circuit controls the frequency of a clock to be provided to a CPU core, on the basis of the table and an operating state signal output by the CPU core. 
     According to the one embodiment, it is possible to provide a semiconductor device that allows performance to follow a dynamically changing load. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The above and other aspects, advantages and features will become more apparent from the following description of certain embodiments taken in conjunction with the accompanying drawings, in which: 
         FIG. 1  is a block diagram of a semiconductor device according to a comparative example; 
         FIG. 2  is a conceptual diagram of a method for controlling the semiconductor device according to the comparative example; 
         FIG. 3A  is a front view of a wireless communication terminal according to a first embodiment; 
         FIG. 3B  is a rear view of the wireless communication terminal according to the first embodiment; 
         FIG. 4  is a block diagram of a wireless communication device included in the wireless communication terminal according to the first embodiment; 
         FIG. 5  is a block diagram of a semiconductor device according to the first embodiment; 
         FIG. 6  is a conceptual diagram of a method for controlling the semiconductor device according to the first embodiment; 
         FIG. 7  is a block diagram of a table according to the first embodiment; 
         FIG. 8  shows values stored in registers included in the table according to the first embodiment; 
         FIG. 9  shows values stored in a parameter table included in the table according to the first embodiment; 
         FIG. 10  is a graph showing an example of settings in the table according to the first embodiment; 
         FIG. 11A  is a graph showing another example of settings in the table according to the first embodiment; 
         FIG. 11B  is a graph showing another example of settings in the table according to the first embodiment; 
         FIG. 11C  is a graph showing another example of settings in the table according to the first embodiment; 
         FIG. 11D  is a graph showing another example of settings in the table according to the first embodiment; 
         FIG. 12  is a block diagram of a frequency regulating circuit according to a modification of the first embodiment; 
         FIG. 13  is a graph showing an example of settings in a table according to the modification of the first embodiment; 
         FIG. 14  is a block diagram of a semiconductor device according to a second embodiment; 
         FIG. 15  is a flowchart of a method for controlling the semiconductor device according to the second embodiment; 
         FIG. 16A  is a state transition diagram of a first frequency regulating circuit according to the second embodiment; 
         FIG. 16B  is a state transition diagram of a second frequency regulating circuit according to the second embodiment; 
         FIG. 16C  is a state transition diagram of a third frequency regulating circuit according to the second embodiment; 
         FIG. 16D  is a state transition diagram of a fourth frequency regulating circuit according to the second embodiment; 
         FIG. 17A  is a graph showing an example of settings in a first table according to the second embodiment; 
         FIG. 17B  is a graph showing an example of settings in a second table according to the second embodiment; 
         FIG. 17C  is a graph showing an example of settings in a third table according to the second embodiment; 
         FIG. 17D  is a graph showing an example of settings in a fourth table according to the second embodiment; 
         FIG. 18  is a graph showing the relationship between performance and power of the semiconductor device according to the second embodiment; 
         FIG. 19  is a block diagram of a semiconductor device according to a third embodiment; 
         FIG. 20A  is a block diagram of a third frequency regulating circuit according to the third embodiment; 
         FIG. 20B  is a block diagram of a fourth frequency regulating circuit according to the third embodiment; 
         FIG. 21A  is a state transition diagram of the third frequency regulating circuit according to the third embodiment; 
         FIG. 21B  is a state transition diagram of the fourth frequency regulating circuit according to the third embodiment; 
         FIG. 21C  is a state transition diagram of a power management unit which provides an operating voltage to a third CPU core; and 
         FIG. 21D  is a state transition diagram of a power management unit which provides an operating voltage to a fourth CPU core. 
     
    
    
     DETAILED DESCRIPTION 
     Now, specific embodiments will be described in detail with reference to the accompanying drawings. Note that the following description and drawings are simplified as appropriate in order to provide a clear explanation. 
     &lt;Configuration of Semiconductor Device According to Comparative Example&gt; 
     First, referring to  FIG. 1 , the configuration of a semiconductor device according to a comparative example examined by the inventors will be described. The semiconductor device according to the comparative example includes a CPU  90  and a clock frequency control circuit CFCC. 
     &lt;Operation of Semiconductor Device According to Comparative Example&gt; 
     Next, the operation of the semiconductor device according to the comparative example will be described. The clock frequency control circuit CFCC provides a clock CK to a core  9  of the CPU  90 . The core  9  performs a process on the basis of the clock CK. The core  9  also generates an idle state signal ISS indicating the idle state of the core  9 . The CPU  90  generates a frequency control signal FCS on the basis of the idle state signal ISS under OS (operating system) control. The frequency control signal FCS indicates the set frequency of the clock CK. The clock frequency control circuit CFCC controls the frequency of the clock CK on the basis of the frequency control signal FCS. 
     Referring to  FIG. 2 , the operation of the semiconductor device according to the comparative example will be described in detail. The CPU  90  controls the frequency of the clock CK at regular frequency control intervals under OS control. Specifically, the CPU  90  calculates the active time ratio of the core  9  at each frequency control interval on the basis of the idle state signal ISS. The active time ratio is the proportion of the active state time in a frequency control interval. Based on the active time ratio, the CPU  90  generates a frequency control signal FCS indicating the set frequency of the clock CK. Based on the frequency control signal FCS, the clock frequency control circuit CFCC controls the frequency of the clock CK. 
     Hereafter, problems with the method of controlling the frequency of the clock CK on the basis of the calculated active time ratio of the core  9  under OS control will be described. 
     The method of controlling the frequency of the clock CK on the basis of the active time ratio needs a long frequency control interval. For this reason, if the performance required of the core  9  dynamically changes, the performance achieved by the core  9  cannot follow the required performance. Specifically, the frequency of the clock CK is constant at the frequency control interval from time T 0  to time T 5 . Accordingly, the achieved performance is limited to a level corresponding to the constant frequency. If the frequency of the clock CK is insufficient to meet the required performance, the core  9  remains in an active state even after the required performance falls to zero. For example, while the required performance falls to zero at time T 1 , the active state which has started at time T 0  is extended until time T 2  in order to process tasks which the core  9  has not been able to process by time T 1 . While the required performance falls to zero at time T 4 , the active state which has started at time T 3  is extended until time T 5  in order to process tasks which the core  9  has not been able to process by time T 4 . 
     The power consumption of the core  9  includes a base portion and an effective portion. The base portion is power which is required as long as the core  9  is placed in an active state. The effective portion is power which is required in accordance with the performance achieved by the core  9 . If the active state is extended, the base portion of the power consumption is expanded. Further, the software control may fail. In this case, by setting the lower limit of the set frequency of the clock CK to a high value, the extension of the active state can be avoided. However, power consumption would be increased in a case that the required performance is constant at a low value. 
     Further, at each frequency control interval, overhead occurs where the CPU  90  must calculate the active time ratio under OS control. Accordingly, it is difficult to shorten the frequency control interval. Note that the overhead is omitted in  FIG. 2 . 
     First Embodiment 
     Overview of Wireless Communication Terminal 
     Firstly, with reference to  FIGS. 3A and 3B , an explanation will be given of an overview of a wireless communication terminal suitable for use as an electronic device to which a semiconductor device according to a first embodiment is applied. Each of  FIGS. 3A and 3B  is an exterior view showing an exemplary structure of a wireless communication terminal  500 . 
     Note that  FIGS. 3A and 3B  each show the case where the wireless communication terminal  500  is a smartphone. However, the wireless communication terminal  500  may be another wireless communication terminal such as a feature phone (e.g., a flip mobile phone terminal), a portable game terminal, a tablet PC (Personal Computer), a notebook PC, a car navigation device, and the like. Needless to say, the semiconductor device according to the present embodiment is applicable to any device other than wireless communication terminals. 
       FIG. 3A  shows one main surface (front face) of a housing  501  that forms the wireless communication terminal  500 . On the front face of the housing  501 , a display device  502 , a touch panel  503 , a plurality of operation buttons  504 , and a camera device  505  are disposed. On the other hand,  FIG. 3B  shows the other main surface (back face) of the housing  501 . On the back face of the housing  501 , a camera device  506  is disposed. 
     The display device  502  is a display device such as a liquid crystal display (LCD: Liquid Crystal Display), an organic EL display (OLED: Organic Light-Emitting Diode) and the like. The display device  502  is disposed such that the displaying face is positioned on the front face of the housing  501 . 
     The touch panel  503  is disposed so as to cover the displaying face of the display device  502 . Alternatively, it is disposed on the back side of the display device  502 . The touch panel  503  senses the position on the displaying face touched by the user. That is, the user can intuitively operate the wireless communication terminal  500  by touching the displaying face of the display device  502  with a finger, a dedicated pen (generally referred to as a stylus) and the like. 
     The operation buttons  504  are used for auxiliary operating of the wireless communication terminal  500 . Note that such operation buttons may not be provided depending on the wireless communication terminals. 
     The camera device  505  is a sub-camera whose lens unit is positioned on the front face of the housing  501 . Note that such a sub-camera may not be provided depending on the wireless communication terminals. 
     The camera device  506  is a main camera whose lens unit is positioned on the back face of the housing  501 . 
     &lt;Structure of Wireless Communication Device&gt; 
     With reference to  FIG. 4 , an explanation will be given of the structure of a wireless communication device  600  in which the semiconductor device according to the present embodiment is installed.  FIG. 4  is a block diagram showing an exemplary structure of the wireless communication device  600  according to the first embodiment. The wireless communication device  600  is, for example, the internal structure of the wireless communication terminal  500  shown in the  FIGS. 3A and 3B . As shown in  FIG. 4 , the wireless communication device  600  includes an application processor (host IC)  601 , a baseband processor  602 , an RFIC (Radio Frequency Integrated Circuit)  603 , a main memory  604 , a battery  605 , a power management circuit PMC, a display unit  607 , a camera unit  608 , an operation input unit  609 , an audio IC  610 , a microphone  611 , a speaker  612 , and a GPU (Graphics Processor Unit)  613 . The power management circuit PMC is, for example, a power management IC (PMCI: Power Management Integrated Circuit). 
     The application processor (host IC)  601  is a semiconductor integrated circuit that reads programs stored in the main memory  604  to carry out processing for implementing various functions of the wireless communication device  600 . For example, the application processor  601  reads an OS (Operating System) program from the main memory  604  and executes the same, and executes any application program that operates on the OS program. 
     The baseband processor  602  subjects data transmitted and received by the mobile communication terminal to baseband processing, which includes an encoding process (e.g., error correction coding of convolution codes, turbo codes and the like), a decoding process and the like. 
     Particularly as to voice data, the baseband processor  602  receives transmission voice data from the audio IC  610  and performs an encoding process on the received transmission voice data, and transmits the encoded transmission voice data to the RFIC  603 . More specifically, the baseband processor  602  performs an encoding process on PCM (Pulse Code Modulation) data received from the audio IC  610 , so that the PCM data is converted into AMR (Adaptive Multi Rate) data that can be received by the RFIC  603 . 
     On the other hand, the baseband processor  602  receives reception voice data from the RFIC  603  and performs a decoding process on the received reception voice data, and transmits the decoded reception voice data to the audio IC  610 . More specifically, the baseband processor  602  performs a decoding process on AMR data, which is the reception voice data demodulated by the RFIC  603 , so that the AMR data is converted into PCM data. Note that the AMR data is compressed data and the PCM data is uncompressed data. 
     The RFIC  603  performs analog RF signal processing. The analog RF signal processing includes frequency upconversion, frequency downconversion, amplification and the like. 
     Particularly as to voice data, the RFIC  603  generates a transmission RF signal from transmission voice data modulated by the baseband processor  602 , and transmits the transmission RF signal via an antenna in a wireless manner (Up Link). 
     On the other hand, the RFIC  603  receives a reception RF signal via the antenna in a wireless manner and generates reception voice data from the reception RF signal, and transmits the generated reception voice data to the baseband processor  602  (Down Link). 
     The main memory (external memory)  604  stores programs and data that are used by the application processor  601 . Further, the main memory  604  stores the program that is used for a vocoder process performed by the baseband processor  602 , that is, a codec. A volatile memory such as a DRAM (Dynamic Random Access Memory) is frequently used as the main memory  604 . Stored data in a volatile memory is cleared when power supply is shut down. Needless to say, a non-volatile memory that retains stored data even when power supply is shut down may be used as the main memory  604 . 
     The battery  605  is an electric battery, and used when the wireless communication device  600  operates independently of an external power supply. Note that the wireless communication device  600  may be supplied with power from the battery  605  even when it is connected to any external power supply. Further, it is preferable to use a secondary battery as the battery  605 . 
     The power management circuit PMC generates an internal power supply from the battery  605  or an external power supply. This internal power supply is supplied to each of the blocks in the wireless communication device  600 . The power management circuit PMC controls the voltage of the internal power supply for each block supplied with the internal power supply. The power management circuit PMC performs the voltage control for the internal power supply based on instructions from the application processor  601 . Further, the power management circuit PMC can control supplying and blocking of the internal power supply for each block. In addition, the power management circuit PMC also performs charging control for the battery  605  when supply from the external power supply is available. 
     The display unit  607  corresponds to the display device  502  shown in  FIGS. 3A and 3B , and is a display device such as a liquid crystal display (LCD: Liquid Crystal Display), an organic EL display (OLED: Organic Light-Emitting Diode) and the like. The display unit  607  displays various images in accordance with processes performed by the application processor  601  and the GPU  613 . The images displayed on the display unit  607  include user-interface images by which the user provides operation instructions to the wireless communication device  600 , camera images, moving images and the like. 
     The camera unit  608  acquires an image in accordance with an instruction from the application processor  601 . The camera unit  608  corresponds to the camera devices  505  and  506  in  FIGS. 3A and 3B . 
     The operation input unit  609  is a user interface for the user to operate to provide an operation instruction to the wireless communication device  600 . The operation input unit  609  corresponds to the touch panel  503  and the operation buttons  504  shown in  FIGS. 3A and 3B . 
     The audio IC  610  converts reception voice data, which is a digital signal received from the baseband processor  602 , into an analog signal, and drives the speaker  612 . Thus voice is output from the speaker  612 . 
     On the other hand, the audio IC  610  subjects voice, which is an analog signal detected by the microphone  611 , to an analog-to-digital (A/D) conversion, and outputs the converted signal to the baseband processor  602 . More specifically, the audio IC  610  generates PCM data, which is a digital signal, from voice which is an analog signal. 
     &lt;Configuration of Semiconductor Device According to First Embodiment&gt; 
     Referring to  FIG. 5 , the configuration of the application processor  601 , which is a semiconductor device according to the present embodiment, will be described. The application processor  601  is, for example, LSI (Large-Scale Integrated circuit). The application processor  601  includes a CPU  10 , a frequency regulating circuit FRC 1 , and a clock frequency control circuit CFCC 1 . The CPU  10  includes a core  1 . The frequency regulating circuit FRC 1  includes a table T 1 . In the table T 1 , performance values of the core  1  and frequency values of a clock CK 1  are associated with each other. 
     &lt;Operation of Semiconductor Device According to First Embodiment&gt; 
     Next, the operation of the application processor  601 , which is a semiconductor device according to the present embodiment, will be described. The clock frequency control circuit CFCC 1  provides a clock CK 1  to the core  1  of the CPU  10 . The core  1  performs a process on the basis of the clock CK 1 . The core  1  outputs an operating state signal OSS 1  indicating the operating state of the core  1 . The operating state signal OSS 1  is a performance monitor signal indicating the performance of the core  1 . The performance indicated by the operating state signal OSS 1  may be an absolute value or a relative value with respect to the maximum performance of the core  1 . The unit of performance is, for example, a million instructions per second (MIPS). The frequency regulating circuit FRC 1  controls the frequency of the clock CK 1  on the basis of the table T 1  and the operating state signal OSS 1 . Specifically, the frequency regulating circuit FRC 1  outputs a frequency control signal FCS 1  on the basis of the table T 1  and the operating state signal OSS 1 . The frequency control signal FCS 1  indicates the set frequency of the clock CK 1 . The clock frequency control circuit CFCC 1  controls the frequency of the clock CK 1  on the basis of the frequency control signal FCS 1 . 
     Referring to  FIG. 6 , the operation of the application processor  601 , which is a semiconductor device according to the present embodiment, will be described in detail. The frequency regulating circuit FRC 1  controls the frequency of the clock CK 1  at regular frequency control intervals. Specifically, referring to the table T 1 , the frequency regulating circuit FRC 1  determines a frequency corresponding to the performance of the core  1  indicated by the operating state signal OSS 1 . The frequency regulating circuit FRC 1  then outputs a frequency control signal FCS 1  indicating the determined frequency. Based on the frequency control signal FCS 1 , the clock frequency control circuit CFCC 1  controls the frequency of the clock CK 1 . Since the frequency control interval according to the present embodiment is short, the performance achieved by the core  1  can follow the performance required of the core  1 . The power consumed by the core  1  includes a base portion and an effective portion. The base portion is power which is required as long as the core  1  is placed in an active state. The effective portion is power which is required in accordance with the performance achieved by the core  1 . 
     &lt;Comparison Between Semiconductor Device According to First Embodiment and Semiconductor Device According to Comparative Example&gt; 
     According to the present embodiment, the frequency regulating circuit FRC 1  controls the frequency of the clock CK 1  on the basis of the performance of the core  1  indicated by the operating state signal OSS 1 . For this reason, the frequency control interval can be shortened compared to that in the comparative example. Even when the required performance (load) dynamically changes, the achieved performance can follow the required performance. As a result, the active state of the core  1  is not extended. Therefore, expansion of the base portion of the power consumption of the core  1  is prevented, allowing a reduction in power consumption. Since the achieved performance can follow the dynamically changing required performance, the lower limit of the set frequency of the clock CK 1  can be set to a low value. 
     According to the present embodiment, the frequency regulating circuit FRC 1  serving as a dedicated circuit for controlling the frequency of the clock CK 1  is provided. The frequency regulating circuit FRC 1  includes the table T 1 . Thus the frequency regulating circuit FRC 1  can control the frequency of the clock CK 1  without depending on the OS. As a result, according to the present embodiment, no overhead occurs, unlike in the comparative example. 
     While the case where the application processor  601  includes the single CPU core  1  has been described, the application processor  601  may include a plurality of CPU cores  1 . In this case, a frequency regulating circuit FRC 1  and a clock frequency control circuit CFCC 1  are provided for each CPU core  1 . 
     &lt;Detailed Description of Table Used in Clock Frequency Control According to First Embodiment&gt; 
     Referring to  FIG. 7 , the table T 1  includes registers  11  and a comparator  12 . The comparator  12  includes a calculator  13  and a parameter table  14 . 
     Referring to  FIG. 8 , values stored in the registers  11  will be described. The registers  11  store, as points P 0  to P 5 , combinations of performance values and frequency values. The performance values serve as first parameters; the frequency values serve as second parameters. Specifically, the registers  11  store point PO, which is a combination of a performance value “0” and a frequency value “10%”, point P 1 , which is a combination of a performance value “10” and a frequency value “40%”, point P 2 , which is a combination of a performance value “20” and a frequency value “65%”, and point 3, which is a combination of a performance value “30” and a frequency value “80%”. The registers  11  also store point 4, which is a combination of a performance value “50” and a frequency value “90%”, and point P 5 , which is a combination of a performance value “85” and a frequency value “90%”. While  FIG. 8  shows a case where the performance values and frequency values are respectively relative values with respect to the maximum values, these values may be absolute values. 
     Based on points P 0  to P 5  stored in the registers  11 , the calculator  13  calculates point P 0 -A which is interpolated between points P 0  and P 1 , point P 1 -A which is interpolated between points P 1  and P 2 , point P 2 -A which is interpolated between points P 2  and P 3 , points P 3 -A to P 3 -C which are interpolated between points P 3  and P 4 , and points P 4 -A to P 4 -D which are interpolated between points P 4  and P 5 . 
     Referring to  FIG. 9 , the parameter table  14  stores points P 0  to P 5 , P 0 -A, P 1 -A, P 2 -A, P 3 -A to P 3 -C, and P 4 -A to P 4 -D. Point P 0 -A is a combination of a performance value “5” and a frequency value “25%”. Point P 1 -A is a combination of a performance value “15” and a frequency value “52%”. Point P 2 -A is a combination of a performance value “25” and a frequency value “72%”. Point P 3 -A is a combination of a performance value “35” and a frequency value “82%”. Point P 3 -B is a combination of a performance value “40” and a frequency value “85%”. Point P 3 -C is a combination of a performance value “45” and a frequency value “87%”. Point P 4 -A is a combination of a performance value “55” and a frequency value “90%”. Point P 4 -B is a combination of a performance value “60” and a frequency value “90%”. Point P 4 -C is a combination of a performance value “65” and a frequency value “90%”. Point P 4 -D is a combination of a performance value “70” and a frequency value “90%”. 
       FIG. 10  is a graph showing the correspondences between the performance values and the frequency values stored in the parameter table  14 . Points P 0  to P 5  are represented by solid circles; points P 0 -A, P 1 -A, P 2 -A, P 3 -A to P 3 -C, and P 4 -A to P 4 -D are represented by open circles. 
     Referring to the parameter table  14 , the comparator  12  determines a frequency value FRQ 1  corresponding to the performance value of the core  1  indicated by the operating state signal OSS 1 . The frequency regulating circuit FRC 1  outputs the frequency control signal FCS 1  indicating the frequency value FRQ 1 . 
     Since the calculator  13  calculates interpolation points P 0 -A, P 1 -A, P 2 -A, P 3 -A to P 3 -C, and P 4 -A to P 4 -D on the basis of points P 0  to P 5  stored in the registers  11 , the contents of the parameter table  14  can be changed by only changing the small number of points, P 0  to P 5 , stored in the registers  11 . For this reason, the contents of the parameter table  14  are easily changed in accordance with the situation in which the wireless communication terminal  600  is used. Since these points can be set freely, it is also possible to define a curved frequency trajectory. 
     &lt;Example of settings in Tables According to First Embodiment&gt; 
     Next, an example of settings in the table T 1  according to the present embodiment will be described. 
       FIG. 11A  is a graph showing the contents of the parameter table  14  which conforms to music play mode. In the music play mode, the performance required of the CPU  10  is small. Accordingly, the frequency values of points P 1  to P 5  are set to a low value. 
       FIG. 11B  is a graph showing the contents of the parameter table  14  which conforms to a touch panel input operation mode. In the touch panel input operation mode, the frequency values steeply rise at points P 0  to P 2  in order to quickly respond to a touch operation on the touch panel  503  by the user. 
       FIG. 11C  is a graph showing the contents of the parameter table  14  which conforms to a three dimensional (3D) graphics mode. In the 3D graphics mode, the frequency values of points P 0  to P 2  steeply rise in order to quickly respond to a request sent from the GPU  613  to the CPU  10 . Note that in view of the electric current, the upper limit value of the frequency (the frequency values of points P 2  to P 5 ) is limited to a value lower than that in the touch panel input operation mode. 
       FIG. 11D  is a graph showing the contents of the parameter table  14  which conforms to a power saving mode. In the power saving mode, when the performance values are smaller than or equal to a certain threshold (the performance value of point P 4 ), the frequency values are set to low values in order to reduce current consumption; when the performance values are higher than the threshold, the frequency values are set to high values. 
     &lt;Modification of First Embodiment&gt; 
     Next, a modification of the first embodiment will be described. In the present modification, an operating state signal OSS 1  output by the core  1  indicates the idle state of the core  1 . For this reason, the configuration and operation of a frequency regulating circuit FRC 1  differ from those described above. 
     Referring to  FIG. 12 , a frequency regulating circuit FRC 1  according to the present modification includes a table T 1  and a calculator  15 . The calculator  15  calculates an active time ratio ATR 1  of the core  1  on the basis of the operating state signal OSS 1  indicating the idle state of the core  1 . The active time ratio ATR 1  indicates an operating period per unit time of the core  1 . The active time ratio ATR 1  is, for example, the proportion of active state time in a frequency control interval. The frequency regulating circuit FRC 1  outputs a frequency control signal FCS 1  on the basis of the table T 1  and the active time ratio ATR 1 . 
     Referring to  FIG. 13 , in the table T 1  according to the present modification, active time ratios of the core  1  and frequency values of a clock CK 1  are associated with each other. Note that in the table T 1  according to the present modification, idle periods per unit time of the core  1  and frequency values may be associated with each other. An idle period per unit time of the core  1  is, for example, the proportion of idle time in a frequency control interval. In this case, the calculator  15  calculates idle time per unit time of the core  1  on the basis of the idle state of the core  1  indicated by the operating state signal OSS 1 . The frequency regulating circuit FRC 1  outputs a frequency control signal FCS 1  on the basis of the table T 1  and the idle period per unit time of the core  1 . 
     In the present modification, as also in the first embodiment, the frequency regulating circuit FRC 1  serving as a dedicated circuit for controlling the frequency of the clock CK 1  is provided. The frequency regulating circuit FRC 1  includes the table T 1 . Accordingly, the frequency regulating circuit FRC 1  can control the frequency of the clock CK 1  without depending on the OS. As a result, according to the present modification, no overhead occurs, unlike in the comparative example. Since no overhead occurs, the frequency control interval can be shortened compared to that in the comparative example. Therefore, even if the required performance (load) dynamically changes, the achieved performance can follow the required performance. As a result, the active state of the core  1  is not extended. Since the active state of the core  1  is not extended, expansion of the base portion of the power consumption of the core  1  is prevented, allowing a reduction in power consumption. Note that if the operating state signal OSS 1  indicates the performance of the core  1 , the frequency control interval can be further shortened. 
     Second Embodiment 
     Next, an application processor  601 , which is a semiconductor device according to a second embodiment, will be described. The application processor  601  according to the second embodiment includes a plurality of CPU cores. Hereafter, descriptions of items which are common to the first embodiment may be omitted. 
     &lt;Configuration of Semiconductor Device According to Second Embodiment&gt; 
     Referring to  FIG. 14 , the configuration of the application processor  601 , which is a semiconductor device according to the second embodiment, will be described. The application processor  601  includes CPUs  10  and  20 . The CPU  10  is a power-saving CPU, which has a low operating frequency and low performance. The CPU  20  is a high-performance CPU, which has a high operating frequency and high performance. The CPU  10  includes cores  1  and  2 . The CPU  20  includes cores  3  and  4 . The cores  1  to  4  perform processes on the basis of clocks CK 1  to CK 4 , respectively. 
     The application processor  601  includes frequency regulating circuits FRC 1  to FRC 4  and clock frequency control circuits CFCC 1  to CFCC 4 . The frequency regulating circuit FRC 1  includes a table T 1  for controlling the frequency of the clock CK 1  and a switching circuit SC 1 . In the table T 1 , performance values of the core  1  and frequency values of the clock CK 1  are associated with each other. The frequency regulating circuit FRC 2  includes a table T 2  for controlling the frequency of the clock CK 2  and a switching circuit SC 2 . In the table T 2 , performance values of the core  2  and frequency values of the clock CK 2  are associated with each other. The frequency regulating circuit FRC 3  includes a table T 3  for controlling the frequency of the clock CK 3  and a switching circuit SC 3 . In the table T 3 , performance values of the core  3  and frequency values of the clock CK 3  are associated with each other. The frequency regulating circuit FRC 4  includes a table T 4  for controlling the frequency of the clock CK 4  and a switching circuit SC 4 . In the table T 4 , performance values of the core  4  and frequency values of the clock CK 4  are associated with each other. 
     The configurations of the tables T 1  to T 4  according to the present embodiment are the same as that of the table T 1  according to the first embodiment. Points P 0  to P 5  are set in the respective tables T 1  to T 4  according to the present embodiment. Note that the correspondences between the performance values and the frequency values in the tables T 1  to T 4  according to the present embodiment are set as described below. The correspondences between the performance values and the frequency values vary among the CPU cores so as to reduce power consumption. The correspondences between the performance values and the frequency values preferably match the characteristics (power-saving type or high-performance type) of the cores  1  to  4  as control objects. 
     &lt;Operation of Semiconductor Device According to Second Embodiment&gt; 
     Next, the operation of the application processor  601 , which is a semiconductor device according to the present embodiment, will be described. 
     The clock frequency control circuit CFCC 1  provides the clock CK 1  to the core  1  of the CPU  10 . The core  1  performs a process based on the clock CK 1 . The core  1  outputs an operating state signal OSS 1  indicating the operating state of the core  1 . The operating state signal OSS 1  is a performance monitor signal indicating the performance of the core  1 . Based on the table T 1  and the operating state signal OSS 1 , the frequency regulating circuit FRC 1  controls the frequency of the clock CK 1 . Specifically, based on the table T 1  and the operating state signal OSS 1 , the frequency regulating circuit FRC 1  outputs a frequency control signal FCS 1  indicating the set frequency of the clock CK 1 . Based on the frequency control signal FCS 1 , the clock frequency control circuit CFCC 1  controls the frequency of the clock CK 1 . Based on the table T 1  and the operating state signal OSS 1 , the switching circuit SC 1  outputs a switching request SW 11 . Based on a switching request SW 21 , the frequency regulating circuit FRC 1  makes a transition between the control states. 
     The clock frequency control circuit CFCC 2  provides the clock CK 2  to the core  2  of the CPU  10 . The core  2  performs a process based on the clock CK 2 . The core  2  outputs an operating state signal OSS 2  indicating the operating state of the core  2 . The operating state signal OSS 2  is a performance monitor signal indicating the performance of the core  2 . Based on the table T 2  and the operating state signal OSS 2 , the frequency regulating circuit FRC 2  controls the frequency of the clock CK 2 . Specifically, based on the table T 2  and the operating state signal OSS 2 , the frequency regulating circuit FRC 2  outputs a frequency control signal FCS 2  indicating the set frequency of the clock CK 2 . Based on the frequency control signal FCS 2 , the clock frequency control circuit CFCC 2  controls the frequency of the clock CK 2 . Based on the table T 2  and the operating state signal OSS 2 , the switching circuit SC 2  outputs a switching request SW 12  and a switching request SW 21 . Based on a switching request SW 11  and a switching request SW 22 , the frequency regulating circuit FRC 2  makes a transition between the control states. 
     The clock frequency control circuit CFCC 3  provides the clock CK 3  to the core  3  of the CPU  20 . The core  3  performs a process based on the clock CK 3 . The core  3  outputs an operating state signal OSS 3  indicating the operating state of the core  3 . The operating state signal OSS 3  is a performance monitor signal indicating the performance of the core  3 . Based on the table T 3  and the operating state signal OSS 3 , the frequency regulating circuit FRC 3  controls the frequency of the clock CK 3 . Specifically, based on the table T 3  and the operating state signal OSS 3 , the frequency regulating circuit FRC 3  outputs a frequency control signal FCS 3  indicating the set frequency of the clock CK 3 . Based on the frequency control signal FCS 3 , the clock frequency control circuit CFCC 3  controls the frequency of the clock CK 3 . Based on the table T 3  and the operating state signal OSS 3 , the switching circuit SC 3  outputs a switching request SW 13  and the switching request SW 22 . Based on the switching request SW 12  and a switching request SW 23 , the frequency regulating circuit FRC 3  makes a transition between the control states. 
     The clock frequency control circuit CFCC 4  provides the clock CK 4  to the core  4  of the CPU  20 . The core  4  performs a process based on the clock CK 4 . The core  4  outputs an operating state signal OSS 4  indicating the operating state of the core  4 . The operating state signal OSS 4  is a performance monitor signal indicating the performance of the core  4 . Based on the table T 4  and the operating state signal OSS 4 , the frequency regulating circuit FRC 4  controls the frequency of the clock CK 4 . Specifically, based on the table T 4  and the operating state signal OSS 4 , the frequency regulating circuit FRC 4  outputs a frequency control signal FCS 4  indicating the set frequency of the clock CK 4 . Based on the frequency control signal FCS 4 , the clock frequency control circuit CFCC 4  controls the frequency of the clock CK 4 . Based on the table T 4  and the operating state signal OSS 4 , the switching circuit SC 4  outputs the switching request SW 23 . Based on the switching request SW 13 , the frequency regulating circuit FRC 4  makes a transition between the control states. 
     Referring to  FIG. 15 , coordination among the clock controls for the cores  1  to  4  will be described.  FIG. 15  is a flowchart of a method for controlling a semiconductor device according to the second embodiment. The method for controlling a semiconductor device includes steps S 100  to S 103 , S 105 , S 111  to S 115 , S 121  to S 125 , S 131 , S 132 , S 134 , and S 135 . 
     In step S 100 , settings are made in the table T 1 . Specifically, the calculator  13  of the table T 1  calculates interpolation points between points P 0  to P 5  stored in the registers  11  of the table T 1 . The parameter table  14  of the table T 1  stores points P 0  to P 5  and the interpolation points. As in the table T 1 , settings are made in the tables T 2  to T 4 . 
     The frequency regulating circuit FRC 1  checks the performance value indicated by the operating state signal OSS 1  (S 101 ). The frequency regulating circuit FRC 1  compares the performance value indicated by the operating state signal OSS 1  with the table T 1  (S 102 ). If the performance value indicated by the operating state signal OSS 1  is greater than the largest (the performance value of point P 5 ) of the performance values in the table T 1  (YES in S 103 ), the process proceeds to step S 111 . If the performance value indicated by the operating state signal OSS 1  is not greater than the largest of the performance values in the table  1  (NO in S 103 ), the frequency regulating circuit FRC 1  sets the frequency of the clock CK 1  on the basis of the table T 1  and the performance value indicated by the operating state signal OSS 1  (S 105 ). After step S 105 , the process returns to step S 101 . 
     The frequency regulating circuit FRC 2  checks the performance value indicated by the operating state signal OSS 2  (S 111 ). The frequency regulating circuit FRC 2  compares the performance value indicated by the operating state signal OSS 2  with the table T 2  (S 112 ). If the performance value indicated by the operating state signal OSS 2  is greater than the largest (the performance value of point P 5 ) of the performance values in the table T 2  (YES in S 113 ), the process proceeds to step S 121 . If the performance value indicated by the operating state signal OSS 2  is not greater than the largest of the performance values in the table T 2  (NO in S 113 ), the process proceeds to step S 114 . If the performance value indicated by the operating state signal OSS 2  is smaller than the smallest (the performance value of point P 0 ) of the performance values in the table T 2  (YES in S 114 ), the process returns to step S 101 . If the performance value indicated by the operating state signal OSS 2  is not smaller than the smallest of the performance values in the table T 2  (NO in S 114 ), the frequency regulating circuit FRC 2  sets the frequency of the clock CK 2  on the basis of the table T 2  and the performance value indicated by the operating state signal OSS 2  (S 115 ). After step S 115 , the process returns to step S 111 . 
     The frequency regulating circuit FRC 3  checks the performance value indicated by the operating state signal OSS 3  (S 121 ). The frequency regulating circuit FRC 3  compares the performance value indicated by the operating state signal OSS 3  with the table T 3  (S 122 ). If the performance value indicated by the operating state signal OSS 3  is greater than the largest (the performance value of point P 5 ) of the performance values in the table T 3  (YES in S 123 ), the process proceeds to step S 131 . If the performance value indicated by the operating state signal OSS 3  is not greater than the largest of the performance values in the table T 3  (NO in S 123 ), the process proceeds to step S 124 . If the performance value indicated by the operating state signal OSS 3  is smaller than the smallest (the performance value of point P 0 ) of the performance values in the table T 3  (YES in S 124 ), the process returns to step S 111 . If the performance value indicated by the operating state signal OSS 3  is not smaller than the smallest of the performance values in the table T 3  (NO in S 124 ), the frequency regulating circuit FRC 3  sets the frequency of the clock CK 3  on the basis of the table T 3  and the performance value indicated by the operating state signal OSS 3  (S 125 ). After step S 125 , the process returns to step S 121 . 
     The frequency regulating circuit FRC 4  checks the performance value indicated by the operating state signal OSS 4  (S 131 ). The frequency regulating circuit FRC 4  compares the performance value indicated by the operating state signal OSS 4  with the table T 4  (S 132 ). If the performance value indicated by the operating state signal OSS 4  is smaller than the smallest (the performance value of point P 0 ) of the performance values in the table T 4  (YES in S 134 ), the process returns to step S 121 . If the performance value indicated by the operating state signal OSS 4  is not smaller than the smallest of the performance values in the table T 4  (NO in S 134 ), the frequency regulating circuit FRC 4  sets the frequency of the clock CK 4  on the basis of the table T 4  and the performance value indicated by the operating state signal OSS 4  (S 135 ). After step S 135 , the process returns to step S 131 . 
     Referring to  FIGS. 16A to 16D , the coordination among the clock controls for the cores  1  to  4  will be further described. 
       FIG. 16A  is a state transition diagram of the frequency regulating circuit FRC 1 . The frequency regulating circuit FRC 1  can be placed in states S 10 , S 11 , and S 12 . In the initial state, S 10 , the frequency regulating circuit FRC 1  makes settings in the table T 1 , as described in step S 100 . When the settings are completed, the frequency regulating circuit FRC 1  makes a transition from state S 10  to state S 11 . 
     In state S 11 , the frequency regulating circuit FRC 1  repeatedly performs steps S 101  to S 105  to control the frequency of the clock CK 1  on the basis of the table T 1  and the operating state signal OSS 1 . In state S 11 , the frequency of the clock CK 1  changes in accordance with a change in the performance value indicated by the operating state signal OSS 1 . When the load on the application processor  601  is increased, the performance value indicated by the operating state signal OSS 1  is increased as well. When the performance value indicated by the operating state signal OSS 1  is greater than the largest of the performance values in the table T 1  (the performance value of point P 5 , which is the upper limit setting), it can be judged that the load has been increased to the extent that the core  1  alone cannot process the load. Therefore, when the frequency regulating circuit FRC 1  detects that the performance value indicated by the operating state signal OSS 1  is greater than the largest of the performance values in the table T 1  (YES in S 103 ), the frequency regulating circuit FRC 1  outputs the switching request SW 11  to the frequency regulating circuit FRC 2  and makes a transition from state S 11  to state S 12 . 
     In state S 12 , the frequency regulating circuit FRC 1  fixes the frequency of the clock CK 1  to the largest frequency value in the table T 1  (the frequency value of point P 5 ). When the frequency regulating circuit FRC 1  receives the switching request SW 21  from the frequency regulating circuit FRC 2 , the frequency regulating circuit FRC 1  makes a transition from state S 12  to state S 11 . 
       FIG. 16B  is a state transition diagram of the frequency regulating circuit FRC 2 . The frequency regulating circuit FRC 2  can be placed in states S 20 , S 29 , S 21 , and S 22 . In the initial state, S 20 , the frequency regulating circuit FRC 2  makes settings in the table T 2 , as described in step S 100 . When the settings are completed, the frequency regulating circuit FRC 2  makes a transition from state S 20  to state S 29 . In state S 29 , the frequency regulating circuit FRC 2  prevents the clock frequency control circuit CFCC 2  from providing the clock CK 2 . When the frequency regulating circuit FRC 2  receives the switching request SW 11  from the frequency regulating circuit FRC 1 , the frequency regulating circuit FRC 2  causes the clock frequency control circuit CFCC 2  to start providing the clock CK 2  to the core  2  and makes a transition from state S 29  to state S 21 . 
     In state S 21 , the frequency regulating circuit FRC 2  repeatedly performs steps S 111  to S 115  to control the frequency of the clock CK 2  on the basis of the table T 2  and the operating state signal OSS 2 . In state S 21 , the frequency of the clock CK 2  changes in accordance with a change in the performance value indicated by the operating state signal OSS 2 . When the load on the application processor  601  is increased, the performance value indicated by the operating state signal OSS 2  is increased as well. When the performance value indicated by the operating state signal OSS 2  is greater than the largest of the performance values in the table T 2  (the performance value of point P 5 , which is the upper limit setting), it can be judged that the load has been increased to the extent that the cores  1  and  2  alone cannot process the load. Therefore, when the frequency regulating circuit FRC 2  detects that the performance value indicated by the operating state signal OSS 2  is greater than the largest of the performance values in the table T 2  (YES in S 113 ), the frequency regulating circuit FRC 2  outputs the switching request SW 12  to the frequency regulating circuit FRC 3  and makes a transition from state S 21  to state S 22 . 
     In contrast, when the load on the application processor  601  is reduced, the performance value indicated by the operating state signal OSS 2  is reduced as well. When the performance value indicated by the operating state signal OSS 2  is smaller than the smallest of the performance values in the table T 2  (the performance value of point P 0 , which is the lower limit setting), it can be judged that the load has been reduced to the extent that the core  1  alone can process the load. Therefore, when the frequency regulating circuit FRC 2  detects that the performance value indicated by the operating state signal OSS 2  is smaller than the smallest of the performance values in the table T 2  (YES in S 114 ), the frequency regulating circuit FRC 2  outputs the switching request SW 21  to the frequency regulating circuit FRC 1  and makes a transition from state S 21  to state S 29 . 
     In state S 22 , the frequency regulating circuit FRC 2  fixes the frequency of the clock CK 2  to the largest frequency value in the table T 2  (the frequency value of point P 5 ). When the frequency regulating circuit FRC 2  receives the switching request SW 22  from the frequency regulating circuit FRC 3 , the frequency regulating circuit FRC 2  makes a transition from state S 22  to state S 21 . 
       FIG. 16C  is a state transition diagram of the frequency regulating circuit FRC 3 . The frequency regulating circuit FRC 3  can be placed in states S 30 , S 39 , S 31 , and S 32 . In the initial state, S 30 , the frequency regulating circuit FRC 3  makes settings in the table T 3 , as described in step S 100 . When the settings are completed, the frequency regulating circuit FRC 3  makes a transition from state S 30  to state S 39 . In state S 39 , the frequency regulating circuit FRC 3  prevents the clock frequency control circuit CFCC 3  from providing the clock CK 3 . When the frequency regulating circuit FRC 3  receives the switching request SW 12  from the frequency regulating circuit FRC 2 , the frequency regulating circuit FRC 3  causes the clock frequency control circuit CFCC 3  to start providing the clock CK 3  to the core  3  and makes a transition from state S 39  to state S 31 . 
     In state S 31 , the frequency regulating circuit FRC 3  repeatedly performs steps S 121  to S 125  to control the frequency of the clock CK 3  on the basis of the table T 3  and the operating state signal OSS 3 . In state S 31 , the frequency of the clock CK 3  changes in accordance with a change in the performance value indicated by the operating state signal OSS 3 . When the load on the application processor  601  is increased, the performance value indicated by the operating state signal OSS 3  is increased as well. When the performance value indicated by the operating state signal OSS 3  is greater than the largest of the performance values in the table T 3  (the performance value of point P 5 , which is the upper limit setting), it can be judged that the load has been increased to the extent that the cores  1  to  3  alone cannot process the load. Therefore, when the frequency regulating circuit FRC 3  detects that the performance value indicated by the operating state signal OSS 3  is greater than the largest of the performance values in the table T 3  (YES in S 123 ), the frequency regulating circuit FRC 3  outputs the switching request SW 13  to the frequency regulating circuit FRC 4  and makes a transition from state S 31  to state S 32 . 
     In contrast, when the load on the application processor  601  is reduced, the performance value indicated by the operating state signal OSS 3  is reduced as well. When the performance value indicated by the operating state signal OSS 3  is smaller than the smallest of the performance values in the table T 3  (the performance value of point P 0 , which is the lower limit setting), it can be judged that the load has been reduced to the extent that the cores  1  and  2  alone can process the load. Therefore, when the frequency regulating circuit FRC 3  detects that the performance value indicated by the operating state signal OSS 3  is smaller than the smallest of the performance values in the table T 3  (YES in S 124 ), the frequency regulating circuit FRC 3  outputs the switching request SW 22  to the frequency regulating circuit FRC 2  and makes a transition from state S 31  to state S 39 . 
     In state S 32 , the frequency regulating circuit FRC 3  fixes the frequency of the clock CK 3  to the largest frequency value in the table T 3  (the frequency value of point P 5 ). When the frequency regulating circuit FRC 3  receives the switching request SW 23  from the frequency regulating circuit FRC 4 , the frequency regulating circuit FRC 3  makes a transition from state S 32  to state S 31 . 
       FIG. 16D  is a state transition diagram of the frequency regulating circuit FRC 4 . The frequency regulating circuit FRC 4  can be placed in states S 40 , S 49 , and S 41 . In the initial state, S 40 , the frequency regulating circuit FRC 4  makes settings in the table T 4 , as described in step S 100 . When the settings are completed, the frequency regulating circuit FRC 4  makes a transition from state S 40  to state S 49 . In state S 49 , the frequency regulating circuit FRC 4  prevents the clock frequency control circuit CFCC 4  from providing the clock CK 4 . When receiving the switching request SW 13  from the frequency regulating circuit FRC 3 , the frequency regulating circuit FRC 4  causes the clock frequency control circuit CFCC 4  to start providing the clock CK 4  to the core  4  and makes a transition from state S 49  to state S 41 . 
     In state S 41 , the frequency regulating circuit FRC 4  repeatedly performs steps S 131  to S 135  to control the frequency of the clock CK 4  on the basis of the table T 4  and the operating state signal OSS 4 . In state S 41 , the frequency of the clock CK 4  changes in accordance with a change in the performance value indicated by the operating state signal OSS 4 . When the load on the application processor  601  is reduced, the performance value indicated by the operating state signal OSS 4  is reduced as well. When the performance value indicated by the operating state signal OSS 4  is smaller than the smallest of the performance values in the table T 4  (the performance value of point P 0 , which is the lower limit setting), it can be judged that the load has been reduced to the extent that the cores  1  to  3  alone can process the load. Therefore, when the frequency regulating circuit FRC 4  detects that the performance value indicated by the operating state signal OSS 4  is smaller than the smallest of the performance values in the table T 4  (YES in S 134 ), the frequency regulating circuit FRC 4  outputs the switching request SW 23  to the frequency regulating circuit FRC 3  and makes a transition from state S 41  to state S 49 . 
     &lt;Example of settings in Tables According to Second Embodiment&gt; 
     Next, an example of settings in the tables T 1  to T 4  according to the present embodiment will be described. 
       FIG. 17A  is a graph showing the correspondences between the performance values and frequency values set in the table T 1 . Points P 0  to P 5  are represented by solid circles. To allow the power-saving type core  1  alone to process a light load, settings are made in the table T 1  so that the frequency of the clock CK 1  is easily increased. 
       FIG. 17B  is a graph showing the correspondences between the performance values and frequency values in the table T 2 . Points P 0  to P 5  are represented by solid circles. In the section from point P 0  to point P 4 , the frequency value is linearly increased in accordance with increases in the performance value. As seen above, settings are made in the table T 2  so that the frequency of the clock CK 2  is easily increased. Note that to allow the power-saving type cores  1  and  2  alone to process the load as much as possible, the performance value of point P 5  is set to a large value, and thus occurrence of the switching request SW 12  is reduced. 
       FIG. 17C  is a graph showing the correspondences between the performance values and frequency values set in the table T 3 . Points P 0  to P 5  are represented by solid circles. To allow the high-performance, power-consuming core  3  and the power-saving type cores  1  and  2  alone to process the load, the upper limit of the set frequency of the clock CK 3  (the frequency values of points P 2  to P 5 ) is limited, and thus occurrence of the switching request SW 13  is reduced. 
       FIG. 17D  is a graph showing the correspondences between the performance values and frequency values set in the table T 4 . Points P 0  to P 5  are represented by solid circles. To reduce the operating time of the core  4  as much as possible, settings are made in the table T 4  such that the frequency of the clock CK 4  is easily increased. 
     As seen above, clock frequency control which is intended to reduce power consumption can be performed for the CPUs  10  and  20 , which differ from each other in characteristics. 
     In the present embodiment, the operating state signals OSS 1  to OSS 4  may indicate the idle states of the cores  1  to  4 , respectively. In this case, the frequency regulating circuits FRC 1  to FRC 4  output frequency control signals FCS 1  to FCS 4 , respectively, through processes the same as that of the frequency regulating circuit FRC 1  according to the modification of the first embodiment. 
     According to the present embodiment, clock controls for the cores  1  to  4  can be coordinated. In other words, the number of CPU cores, which perform processes, can be increased and reduced in accordance with a change in the load on the application processor  601 . As a result, the performance of the entire application processor  601  can satisfactorily follow the dynamically changing load. Further, even when CPU cores are added to the application processor  601 , it is only necessary to add frequency regulating circuits and clock frequency control circuits corresponding to the added CPU cores. That is, the application processor  601 , which is a semiconductor device according to the present embodiment, has good expandability. Further, the division of roles between the power-saving type cores  1  and  2  and the high-performance type cores  3  and  4  is optimized. Thus, while allowing the performance of the entire application processor  601  to satisfactorily follow the dynamically changing load, the power consumption of the entire application processor  601  can be reduced. 
     Referring to  FIG. 18 , other technical advantages of the present embodiment will be described.  FIG. 18  is a graph showing the relationship between the performance and the power of the entire application processor  601 , which is a semiconductor device according to the present embodiment.  FIG. 18  shows a processing mode corresponding to states S 11 , S 29 , S 39 , and S 49 , a processing mode corresponding to states S 12 , S 21 , S 39 , and S 49 , a processing mode corresponding to states S 12 , S 22 , S 31 , and S 49 , a processing mode corresponding to states S 12 , S 22 , S 32 , and S 41 , and transitions between the processing modes. If there is a power limit serving as the current limit of the entire application processor  601 , it is possible to set a performance limit corresponding to the power limit in the table and thus to prevent the clock frequency from being increased to frequencies greater than or equal to a frequency value corresponding to the performance limit. Thus it is possible to numerically define the upper limit current of the entire application processor  601 , which is usually difficult to define. 
     Third Embodiment 
     Next, an application processor  601 , which is a semiconductor device according to a third embodiment, will be described. In the third embodiment, the operating voltage of cores  3  and  4  of the CPU  20  is additionally controlled. Hereafter, descriptions of items which are common to the second embodiments may be omitted. 
     &lt;Configuration of Semiconductor Device According to Third Embodiment&gt; 
     Referring to  FIG. 19 , the configuration of the application processor  601 , which is a semiconductor device according to the third embodiment, will be described. The application processor  601  includes CPUs  10  and  20 . The configurations of the CPUs  10  and  20  are the same as those in the second embodiment. 
     The application processor  601  includes frequency regulating circuits FRC 1  to FRC 4  and clock frequency control circuits CFCC 1  to CFCC 4 . The configurations of the frequency regulating circuits FRC 1  and FRC 2  are the same as those in the second embodiment. The configurations of the clock frequency control circuits CFCC 1  to CFCC 4  are the same as those in the second embodiment. On the other hand, the configurations of the frequency regulating circuits FRC 3  and FRC 4  differ from those in the second embodiment. The power management circuit PMC includes a power management unit  5  for providing an operating voltage to the core  3  and a power management unit  6  for providing an operating voltage to the core  4 . 
     Referring to  FIG. 20A , the configuration of the frequency regulating circuit FRC 3  will be described. The frequency regulating circuit FRC 3  includes tables T 3  and T 30  for controlling the frequency of a clock CK 3  and a switching circuit SC 3 . In the tables T 3  and T 30 , performance values of the core  3  and frequency values of the clock CK 3  are associated with each other. The correspondences between the performance values and the frequency values in the table T 3  differ from those in the table T 30 . The table T 3  corresponds to a normal voltage NV (to be described later); the table T 30  corresponds to an overdrive voltage ODV (to be described later). 
     Referring to  FIG. 20B , the configuration of the frequency regulating circuit FRC 4  will be described. The frequency regulating circuit FRC 4  includes tables T 4  and T 40  for controlling the frequency of a clock CK 4  and a switching circuit SC 4 . In the tables T 4  and T 40 , performance values of the core  4  and frequency values of the clock CK 4  are associated with each other. The correspondences between the performance values and the frequency values in the table T 4  differ from those in the table T 40 . The table T 4  corresponds to a normal voltage NV (to be described later); the table T 40  corresponds to an overdrive voltage ODV (to be described later). 
     &lt;Operation of Semiconductor Device According to Third Embodiment&gt; 
     Next, the operation of the application processor  601 , which is a semiconductor device according to the present embodiment, will be described. 
     The operations of the CPU  10 , the frequency regulating circuits FRC 1  and FRC 2 , and clock frequency control circuits CFCC 1  and CFCC 2  are the same as those in the second embodiment. 
     Referring to  FIGS. 19 and 20A , the clock frequency control circuit CFCC 3  provides the clock CK 3  to the core  3  of the CPU  20 . The core  3  performs a process based on the clock CK 3 . The core  3  outputs an operating state signal OSS 3  indicating the operating state of the core  3 . The operating state signal OSS 3  is a performance monitor signal indicating the performance of the core  3 . In one control state, the frequency regulating circuit FRC controls the frequency of the clock CK 3  on the basis of the table T 3  and the operating state signal OSS 3 . Specifically, the frequency regulating circuit FRC 3  outputs a frequency control signal FCS 3  on the basis of the table T 3  and the operating state signal OSS 3 . In the other control state, the frequency regulating circuit FRC 3  controls the frequency of the clock CK 3  on the basis of the table T 30  and the operating state signal OSS 3 . Specifically, the frequency regulating circuit FRC 3  outputs a frequency control signal FCS 3  on the basis of the table T 30  and the operating state signal OSS 3 . The frequency control signal FCS 3  indicates the set frequency of the clock CK 3 . Based on the frequency control signal FCS 3 , the clock frequency control circuit CFCC 3  controls the frequency of the clock CK 3 . Based on the table T 3  and the operating state signal OSS 3 , the switching circuit SC 3  outputs switching requests SW 13  and SW 22 . Also, based on the table T 30  and the operating state signal OSS 3 , the switching circuit SC 3  outputs switching requests SW 15  and SW 24  and a voltage reduction request DW 3 . Based on switching requests SW 12 , SW 23 , and SW 25 , the frequency regulating circuit FRC 3  makes a transition between the control states. Also, based on a switching request SW 14 , the frequency regulating circuit FRC 3  makes a transition between the control states, and outputs a voltage increase request UP 3 . 
     Referring to  FIGS. 19 and 20B , the clock frequency control circuit CFCC 4  provides the clock CK 4  to the core  4  of the CPU  20 . The core  4  performs a process based on the clock CK 4 . The core  4  outputs an operating state signal OSS 4  indicating the operating state of the core  4 . The operating state signal OSS 4  is a performance monitor signal indicating the performance of the core  4 . In one control state, the frequency regulating circuit FRC 4  controls the frequency of the clock CK 4  on the basis of the table T 4  and the operating state signal OSS 4 . Specifically, the frequency regulating circuit FRC 4  outputs a frequency control signal FCS 4  on the basis of the table T 4  and the operating state signal OSS 4 . In the other control state, the frequency regulating circuit FRC 4  controls the frequency of the clock CK 4  on the basis of the table T 40  and the operating state signal OSS 4 . Specifically, the frequency regulating circuit FRC 4  outputs a frequency control signal FCS 4  on the basis of the table T 40  and the operating state signal OSS 4 . The frequency control signal FCS 4  indicates the set frequency of the clock CK 4 . Based on the frequency control signal FCS 4 , the clock frequency control circuit CFCC 4  controls the frequency of the clock CK 4 . Based on the table T 4  and the operating state signal OSS 4 , the switching circuit SC 4  outputs the switching requests SW 14  and SW 23 . Also, based on the table T 40  and the operating state signal OSS 4 , the switching circuit SC 4  outputs the switching request SW 25  and a voltage reduction request DW 4 . Based on the switching requests SW 13  and SW 24 , the frequency regulating circuit FRC 4  makes a transition between the control states. Also, based on the switching request SW 15 , the frequency regulating circuit FRC 4  makes a transition between the control states, and outputs a voltage increase request UP 4 . 
     Referring to  FIG. 19 , based on the voltage increase request UP 3 , the power management unit  5  makes a transition from a state in which the power management unit  5  provides the normal voltage NV serving as an operating voltage to the core  3  to a state in which the power management unit  5  provides the overdrive voltage ODV as the operating voltage. The overdrive voltage ODV is higher than the normal voltage NV. In contrast, based on the voltage reduction request DW 3 , the power management unit  5  makes a transition from the state in which the power management unit  5  provides the overdrive voltage ODV serving as the operating voltage to the core  3  to the state in which the power management unit  5  provides the normal voltage NV as the operating voltage. 
     Referring to  FIG. 19 , based on the voltage increase request UP 4 , the power management unit  6  makes a transition from a state in which the power management unit  6  provides the normal voltage NV serving as an operating voltage to the core  4  to a state in which the power management unit  6  provides the overdrive voltage ODV as the operating voltage. The overdrive voltage ODV is higher than the normal voltage NV. In contrast, based on the voltage reduction request DW 4 , the power management unit  6  makes a transition from the state in which the power management unit  6  provides the overdrive voltage ODV serving as the operating voltage to the core  4  to the state in which the power management unit  6  provides the normal voltage NV as the operating voltage. 
     Referring to  FIG. 21A , the operation of the frequency regulating circuit FRC 3  will be further described.  FIG. 21A  is a state transition diagram of the frequency regulating circuit FRC 3 . The frequency regulating circuit FRC 3  can be placed in states S 30 , S 39 , and S 31  to S 34 . In the initial state, S 30 , the frequency regulating circuit FRC 3  makes settings in the tables T 3  and T 30 . The states S 39 , S 31 , and S 32 , a transition between states S 30  and S 39 , a transition between states S 39  and S 31 , and a transition between states S 31  and S 32  are the same as those in the second embodiment. When the frequency regulating circuit FRC 3  receives the switching request SW 14  from the frequency regulating circuit FRC 4 , the frequency regulating circuit FRC 3  outputs the voltage increase request UP 3  to the power management unit  5  and makes a transition from state S 32  to state S 33 . 
     In state S 33 , the frequency regulating circuit FRC 3  controls the frequency of the clock CK 3  on the basis of the table T 30  and the operating state signal OSS 3 . In state S 33 , the frequency of the clock CK 3  changes in accordance with a change in the performance value indicated by the operating state signal OSS 3 . The processing capacity of the core  3  when the frequency regulating circuit FRC 3  is placed in state S 33  is greater than that of the core  3  when the frequency regulating circuit FRC 3  is placed in state S 31 . When the load on the application processor  601  is increased, the performance value indicated by the operating state signal OSS 3  is increased as well. When the performance value indicated by the operating state signal OSS 3  is greater than the largest of the performance values in the table T 30 , it can be judged that the load has been increased to the extent that the application processor  601  cannot process the load with the current processing capacity of the processor  601 . Therefore, when the frequency regulating circuit FRC 3  detects that the performance value indicated by the operating state signal OSS 3  is greater than the largest of the performance values in the table T 30 , the frequency regulating circuit FRC 3  outputs the switching request SW 15  to the frequency regulating circuit FRC 4  and makes a transition from state S 33  to state S 34 . 
     In contrast, when the load on the application processor  601  is reduced, the performance value indicated by the operating state signal OSS 3  is reduced as well. When the performance value indicated by the operating state signal OSS 3  is smaller than the smallest of the performance values in the table T 30 , it can be judged that the load has been reduced to the extent that the current processing capacity of the application processor  601  is excessive with respect to the load. Therefore, when the frequency regulating circuit FRC 3  detects that the performance value indicated by the operating state signal OSS 3  is smaller than the smallest of the performance values in the table T 30 , the frequency regulating circuit FRC 3  outputs the switching request SW 24  to the frequency regulating circuit FRC 4 , outputs the voltage reduction request DW 3  to the power management unit  5 , and makes a transition from state S 33  to state S 32 . 
     In state S 34 , the frequency regulating circuit FRC 3  fixes the frequency of the clock CK 3  to the largest frequency value in the table T 30 . The processing capacity of the core  3  when the frequency regulating circuit FRC 3  is placed in state S 34  is greater than that of the core  3  when the frequency regulating circuit FRC 3  is placed in state S 32 . When the frequency regulating circuit FRC 3  receives the switching request SW 25  from the frequency regulating circuit FRC 4 , the frequency regulating circuit FRC 3  makes a transition from state S 34  to state S 33 . 
     Referring to  FIG. 21B , the operation of the frequency regulating circuit FRC 4  will be further described.  FIG. 21B  is a state transition diagram of the frequency regulating circuit FRC 4 . The frequency regulating circuit FRC 4  can be placed in states S 40 , S 49 , and S 41  to S 43 . In the initial state, S 40 , the frequency regulating circuit FRC 4  makes settings in the tables T 4  and T 40 . The states S 49  and S 41 , transition between states S 40  and S 49 , and a transition between states S 49  and S 41  are same as those in the second embodiment. 
     In state S 41 , when the load on the application processor  601  is increased, the performance value indicated by the operating state signal OSS 4  is increased as well. When the performance value indicated by the operating state signal OSS 4  is greater than the largest of the performance values in the table T 4 , it can be judged that the load has been increased to the extent that the application processor  601  cannot process the load with the current processing capacity of the processor  601 . Therefore, when the frequency regulating circuit FRC 4  detects that the performance value indicated by the operating state signal OSS 4  is greater than the largest of the performance values in the table T 4 , the frequency regulating circuit FRC 4  outputs the switching request SW 14  to the frequency regulating circuit FRC 3  and makes a transition from state S 41  to state S 42 . 
     In state S 42 , the frequency regulating circuit FRC 4  fixes the frequency of the clock CK 4  to the largest frequency value in the table T 4 . When the frequency regulating circuit FRC 4  receives the switching request SW 15  from the frequency regulating circuit FRC 3 , the frequency regulating circuit FRC 4  outputs the voltage increase request UP 4  to the power management unit  6  and makes a transition from state S 42  to state S 43 . When the frequency regulating circuit FRC 4  receives the switching request SW 24  from the frequency regulating circuit FRC 3 , the frequency regulating circuit FRC 4  makes a transition from state S 42  to state S 41 . 
     In state S 43 , the frequency regulating circuit FRC 4  controls the frequency of the clock CK 4  on the basis of the table T 40  and the operating state signal OSS 4 . In state S 43 , the frequency of the clock CK 4  changes in accordance with a change in the performance value indicated by the operating state signal OSS 4 . The processing capacity of the core  4  when the frequency regulating circuit FRC 4  is placed in state S 43  is greater than that of the core  4  when the frequency regulating circuit FRC 4  is placed in state S 41 . When the load on the application processor  601  is reduced, the performance value indicated by the operating state signal OSS 4  is reduced as well. When the performance value indicated by the operating state signal OSS 4  is smaller than the smallest of the performance values in the table T 40 , it can be judged that the load has been reduced to the extent that the current processing capacity of the application processor  601  is excessive with respect to the load. Therefore, when the frequency regulating circuit FRC 4  detects that the performance value indicated by the operating state signal OSS 4  is smaller than the smallest of the performance values in the table T 40 , the frequency regulating circuit FRC 4  outputs the switching request SW 25  to the frequency regulating circuit FRC 3 , outputs the voltage reduction request DW 4  to the power management unit  6 , and makes a transition from state S 43  to state S 42 . 
     Referring to  FIG. 21C , the operation of the power management unit  5  will be further described.  FIG. 21C  is a state transition diagram of the power management unit  5 . The power management unit  5  can be placed in states S 51  and S 52 . In the initial state, S 51 , the power management unit  5  provides the normal voltage NV serving as an operating voltage to the core  3 . When the power management unit  5  receives the voltage increase request UP 3  from the frequency regulating circuit FRC 3 , the power management unit  5  makes a transition from state S 51  to state S 52 . In state S 52 , the power management unit  5  provides the overdrive voltage ODV serving as the operating voltage to the core  3 . In contrast, when the power management unit  5  receives the voltage reduction request DW 3  from the frequency regulating circuit FRC 3 , the power management unit  5  makes a transition from state S 52  to state S 51 . As seen above, in both the case where the frequency regulating circuit FRC 3  is placed in state S 31  and the case where it is placed in state S 32 , the power management unit  5  is placed in state S 51 . On the other hand, in both the case where the frequency regulating circuit FRC 3  is placed in state S 33  and the case where it is placed in state S 34 , the power management unit  5  is placed in state S 52 . 
     Referring to  FIG. 21D , the operation of the power management unit  6  will be further described.  FIG. 21D  is a state transition diagram of the power management unit  6 . The power management unit  6  can be placed in states S 61  and S 62 . In the initial state, S 61 , the power management unit  6  provides the normal voltage NV serving as an operating voltage to the core  4 . When the power management unit  6  receives the voltage increase request UP 4  from the frequency regulating circuit FRC 4 , the power management unit  6  makes a transition from state S 61  state S 62 . In state S 62 , the power management unit  6  provides the overdrive voltage ODV serving as the operating voltage to the core  4 . In contrast, when the power management unit  6  receives the voltage reduction request DW 4  from the frequency regulating circuit FRC 4 , the power management unit  6  makes a transition from state S 62  to state S 61 . As seen above, in both the case where the frequency regulating circuit FRC 4  is placed in state S 41  and the case where it is placed in state S 42 , the power management unit  6  is placed in state S 61 . On the other hand, when the frequency regulating circuit FRC 4  is placed in state S 43 , the power management unit  6  is placed in state S 62 . 
     Note that in the present embodiment, the operating state signals OSS 1  to OSS 4  may indicate the idle states of the cores  1  to  4 , respectively. In this case, the frequency regulating circuits FRC 1  to FRC 4  output frequency control signals FCS 1  to FCS 4 , respectively, through processes the same as that of the frequency regulating circuit FRC 1  according to the modification of the first embodiment. 
     According to the present embodiment, clock controls and operating voltage controls for the plurality of CPU cores can be coordinated. Thus the performance of the entire application processor  601  can more satisfactorily follow the dynamically changing load. 
     &lt;Variations&gt; 
     In the foregoing, while the invention made by the inventors has been specifically explained based on the embodiments, it goes without saying that the present invention is not limited to the above-described embodiments, and that various modifications can be made within the range not departing from the gist of the present invention. For example, transitions may be made among the control states on the basis of comparisons between thresholds different from the tables T 1  to T 4 , T 30 , and T 40  and the operating state signals OSS 1  to OSS 4 . 
     The first to third embodiments can be combined as desirable by one of ordinary skill in the art. 
     While the invention has been described in terms of several embodiments, those skilled in the art will recognize that the invention can be practiced with various modifications within the spirit and scope of the appended claims and the invention is not limited to the examples described above. 
     Further, the scope of the claims is not limited by the embodiments described above. 
     Furthermore, it is noted that the Applicant&#39;s intent is to encompass equivalents of all claim elements, even if amended later during prosecution.