Patent Publication Number: US-2023162774-A1

Title: Memory cell and method of operating the same

Description:
PRIORITY CLAIM 
     The present application is a continuation of U.S. application Ser. No. 17/196,131, filed Mar. 9, 2021, which claims the benefit of U.S. Provisional Application No. 63/031,851, filed May 29, 2020, which are herein incorporated by reference in their entireties. 
    
    
     BACKGROUND 
     The semiconductor integrated circuit (IC) industry has produced a wide variety of digital devices to address issues in a number of different areas. Some of these digital devices, such as memory macros, are configured for the storage of data. As ICs have become smaller and more complex, the resistance of conductive lines within these digital devices are also changed affecting the operating voltages of these digital devices and overall IC performance. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. 
         FIG.  1    is a block diagram of a memory cell array, in accordance with some embodiments. 
         FIG.  2 A  is a circuit diagram of a memory cell, in accordance with some embodiments. 
         FIG.  2 B  is a circuit diagram of a memory cell, in accordance with some embodiments. 
         FIG.  2 C  is a circuit diagram of a memory cell, in accordance with some embodiments. 
         FIG.  3 A  is a circuit diagram of a memory cell, in accordance with some embodiments. 
         FIG.  3 B  is a circuit diagram of a memory cell, in accordance with some embodiments. 
         FIG.  3 C  is a circuit diagram of a memory cell, in accordance with some embodiments. 
         FIG.  4 A  is a circuit diagram of a memory cell, in accordance with some embodiments. 
         FIG.  4 B  is a circuit diagram of a memory cell, in accordance with some embodiments. 
         FIG.  4 C  is a circuit diagram of a memory cell, in accordance with some embodiments. 
         FIG.  5    is a cross-sectional view of an integrated circuit, in accordance with some embodiments. 
         FIG.  6    is a functional flow chart of a method of manufacturing an integrated circuit, in accordance with some embodiments. 
         FIG.  7    is a flowchart of a method of operating a circuit, in accordance with some embodiments. 
     
    
    
     DETAILED DESCRIPTION 
     The following disclosure provides different embodiments, or examples, for implementing features of the provided subject matter. Specific examples of components, materials, values, steps, arrangements, or the like, are described below to simplify the present disclosure. These are, of course, merely examples and are not limiting. Other components, materials, values, steps, arrangements, or the like, are contemplated. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. 
     Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature&#39;s relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. 
     In accordance with some embodiments, a memory cell includes a write bit line, a write transistor and a read transistor. The write transistor is coupled between the write bit line and a first node. The read transistor is coupled to the write transistor by the first node. The write transistor is configured to set a stored data value of the memory cell by a write bit line signal that adjusts a polarization state of the read transistor. In some embodiments, the polarization state corresponds to the stored data value of the memory cell. 
     In some embodiments, the read transistor includes a first gate terminal coupled to the write transistor by the first node, and a ferroelectric region having the polarization state that corresponds to the stored data value of the memory cell. 
     In some embodiments, by using the ferroelectric region in the memory cell, the memory cell has less charge leakage at the first node compared to other approaches. In some embodiments, by using the ferroelectric region in the memory cell, the ferroelectric region is able to hold or maintain the polarization state even after voltage at the first node is removed thereby resulting in the memory cell having a longer data retention time and a larger memory window than other approaches. In some embodiments, by having at least a longer data retention time or a larger memory window than other approaches, the memory cell is refreshed less than other approaches resulting in less power consumption than other approaches. 
       FIG.  1    is a block diagram of a memory cell array  100 , in accordance with some embodiments. In some embodiments, memory cell array  100  is part of an integrated circuit. 
     Memory cell array  100  comprises an array of memory cells  102 [ 1 , 1 ],  102 [ 1 , 2 ], . . . ,  102 [ 2 , 2 ], . . . ,  102 [M,N] (collectively referred to as “array of memory cells  102 A”) having M rows and N columns, where N is a positive integer corresponding to the number of columns in array of memory cells  102 A and M is a positive integer corresponding to the number of rows in array of memory cells  102 A. The rows of cells in array of memory cells  102 A are arranged in a first direction X. The columns of cells in array of memory cells  102 A are arranged in a second direction Y. The second direction Y is different from the first direction X. In some embodiments, the second direction Y is perpendicular to the first direction X. Each memory cell  102 [ 1 , 1 ],  102 [ 1 , 2 ], . . . ,  102 [ 2 , 2 ], . . . ,  102 [M,N] in array of memory cells  102 A is configured to store a corresponding bit of data. 
     Array of memory cells  102 A is a dynamic random-access memory (DRAM) array including DRAM-like memory cells. In some embodiments, each memory cell in array of memory cells  102 A corresponds to a two transistor (2T) memory cell with 1-Ferroelectric field effect transistor (FeFET) as shown in  FIGS.  2 A- 2 C . In some embodiments, each memory cell in array of memory cells  102 A corresponds to a three transistor (3T) memory cell with 1-FeFET as shown in  FIGS.  3 A- 3 C . In some embodiments, each memory cell in array of memory cells  102 A corresponds to a four transistor (4T) memory cell with 1-FeFET as shown in  FIGS.  4 A- 4 C . 
     Different types of memory cells in array of memory cells  102 A are within the contemplated scope of the present disclosure. For example, in some embodiments, each memory cell in array of memory cells  102 A is a static random access memory (SRAM). In some embodiments, each memory cell in array of memory cells  102 A corresponds to a ferroelectric resistive random-access memory (FeRAM) cell. In some embodiments, each memory cell in array of memory cells  102 A corresponds to a magneto-resistive random-access memory (MRAM) cell. In some embodiments, each memory cell in array of memory cells  102 A corresponds to a resistive random-access memory (RRAM) cell. Other configurations of array of memory cells  102 A are within the scope of the present disclosure. 
     Memory cell array  100  further includes M write word lines WWL[ 1 ], . . . WWL[M](collectively referred to as “write word line WWL”). Each row 1, . . . , M in array of memory cells  102 A is associated with a corresponding write word line WWL[ 1 ], . . . , WWL[M]. Each row of memory cells in array of memory cells  102 A is coupled with a corresponding write word line WWL[ 1 ], . . . , WWL[M]. For example, memory cells  102 [ 1 , 1 ],  102 [ 1 , 2 ], . . . ,  102 [ 1 ,N] in row 1 are coupled with write word line WWL[ 1 ]. Each write word line WWL extends in the first direction X. 
     Memory cell array  100  further includes M read word lines RWL[ 1 ], . . . RWL[M](collectively referred to as “read word line RWL”). Each row 1, . . . , M in array of memory cells  102 A is associated with a corresponding read word line RWL[ 1 ], . . . , RWL[M]. Each row of memory cells in array of memory cells  102 A is coupled with a corresponding read word line RWL[ 1 ], . . . , RWL[M]. For example, memory cells  102 [ 1 , 1 ],  102 [ 1 , 2 ], . . . ,  102 [ 1 ,N] in row 1 are coupled with read word line RWL[ 1 ]. Each read word line RWL extends in the first direction X. 
     Memory cell array  100  further includes N write bit lines WBL[ 1 ], . . . WBL[N](collectively referred to as “write bit line WBL”). Each column 1, . . . , N in array of memory cells  102 A is associated with a corresponding write bit line WBL[ 1 ], . . . , WBL[N]. Each column of memory cells in array of memory cells  102 A is coupled with a corresponding write bit line WBL[ 1 ], . . . , WBL[N]. For example, memory cells  102 [ 1 , 1 ],  102 [ 2 , 1 ], . . . ,  102 [M, 1 ] in column 1 are coupled with write bit line WBL[ 1 ]. Each write bit line WBL extends in the second direction Y. 
     Memory cell array  100  further includes N read bit lines RBL[ 1 ], . . . RBL[N] (collectively referred to as “read bit line RBL”). Each column 1, . . . , N in array of memory cells  102 A is associated with a corresponding read bit line RBL[ 1 ], . . . , RBL[N]. Each column of memory cells in array of memory cells  102 A is coupled with a corresponding read bit line RBL[ 1 ], . . . , RBL[N]. For example, memory cells  102 [ 1 , 1 ],  102 [ 2 , 1 ], . . . ,  102 [M, 1 ] in column 1 are coupled with read bit line RBL[ 1 ]. Each read bit line RBL extends in the second direction Y. 
     Other configurations of memory cell array  100  are within the scope of the present disclosure. Different configurations of at least write bit lines BL, write word lines WWL, read bit lines RBL or read word lines RWL in memory cell array  100  are within the contemplated scope of the present disclosure. In some embodiments, memory cell array  100  includes additional write ports (write word lines WWL or write bit lines WBL) and/or read ports (read word lines RWL or read bit lines RBL). Furthermore, in some embodiments, array of memory cells  102 A includes multiple groups of different types of memory cells. 
     By way of an illustrative example, a write operation is performed to memory cell  102 [ 1 , 1 ] located in row 1 and column 1 of array of memory cells  102 A. Row 1 includes memory cells  102 [ 1 , 1 ],  102 [ 1 , 2 ], . . . ,  102 [ 1 ,N] that are selected by write word line WWL[ 1 ]. Column 1 includes memory cells  102 [ 1 , 1 ],  102 [ 2 , 1 ], . . . ,  102 [M, 1 ] that are selected for receiving a data signal and storing a binary bit of data by write bit line WBL[ 1 ]. Together, write word line WWL[ 1 ] and write bit line WBL[ 1 ] select and store a binary bit of data in memory cell  102 [ 1 , 1 ]. 
     By way of an illustrative example, a read operation is performed to memory cell  102 [ 1 , 1 ] located in row 1 and column 1 of array of memory cells  102 A. Row 1 includes memory cells  102 [ 1 , 1 ],  102 [ 1 , 2 ], . . . ,  102 [ 1 ,N] that are selected by read word line RWL[ 1 ]. Column 1 includes memory cells  102 [ 1 , 1 ],  102 [ 2 , 1 ], . . . ,  102 [M, 1 ] that are selected to access the stored binary bit of data by read bit line RBL[ 1 ]. Together, read word line RWL[ 1 ] and read bit line RBL[ 1 ] select and read the binary bit of data stored in memory cell  102 [ 1 , 1 ]. 
       FIG.  2 A  is a circuit diagram of a memory cell  200 A, in accordance with some embodiments. 
     Memory cell  200 A is an embodiment of a memory cell in array of memory cells  102 A of  FIG.  1    expressed in a schematic diagram, and similar detailed description is therefore omitted. 
     Components that are the same or similar to those in one or more of  FIGS.  2 A- 2 C,  3 A- 3 C,  4 A- 4 C  (shown below) are given the same reference numbers, and detailed description thereof is thus omitted. For ease of illustration, some of the labeled elements of  FIGS.  2 A- 2 C,  3 A- 3 C,  4 A- 4 C  are not labelled in each of  FIGS.  2 A- 2 C,  3 A- 3 C,  4 A- 4 C . In some embodiments,  FIGS.  2 A- 2 C,  3 A- 3 C,  4 A- 4 C  include additional elements not shown in  FIGS.  2 A- 2 C,  3 A- 3 C,  4 A- 4 C . 
     Memory cell  200 A is usable as one or more memory cells in array of memory cells  102 A of  FIG.  1   . 
     Memory cell  200 A includes a write transistor M 1 , a read transistor M 2 , a write word line WWL, a read word line RWL, a write bit line WBL and a read bit line RBL. 
     Write word line WWL corresponds to a write word line of write word lines WWL[ 1 ], . . . , WWL[M], read word line RWL corresponds to a read word line of read word lines RWL[ 1 ], . . . , RWL[M], write bit line WBL corresponds to a write bit line of write bit lines WBL[ 1 ], . . . , WBL[N], and read bit line RBL corresponds to a read bit line of read bit lines RBL[ 1 ], . . . , RBL[N] of  FIG.  1   , and similar detailed description is therefore omitted. 
     Write transistor M 1  includes a gate terminal coupled to write word line WWL, a drain terminal coupled to write bit line WBL, and a source terminal coupled to at least a gate terminal of read transistor M 2  by a node ND 1 . Write transistor M 1  is configured to write data in memory cell  200 A. Write transistor M 1  is enabled (e.g., turned on) or disabled (e.g., turned off) in response to a write bit line signal on the write bit line WBL. 
     Write transistor M 1  is shown as a P-type Metal Oxide Semiconductor (PMOS) transistor. In some embodiments, write transistor M 1  is an N-type Metal Oxide Semiconductor (NMOS) transistor. 
     Read transistor M 2  includes a drain terminal coupled to read word line RWL, a source terminal coupled to read bit line RBL, and a gate terminal coupled to the source terminal of write transistor M 1 . 
     Read transistor M 2  is referred to as a ferroelectric field effect transistor (FeFET) device, as read transistor M 2  includes a ferroelectric region  202  positioned within the gate terminal of the read transistor M 2 . The ferroelectric region  202  is configured to have different polarization states based on the voltage applied to the gate of the read transistor M 2 . The polarization of the ferroelectric region  202  determines the conductivity (e.g., low resistance state or high resistance state) of read transistor M 2  which represents the data stored in read transistor M 2 . 
     Data is stored by programming the ferroelectric region  202  to have different polarization states. The different polarization states create two different threshold voltage states (e.g., Vth) that correspond to a logic ‘1’ and a logic ‘0’. Due to the threshold voltage difference, the ferroelectric region  202  in the read transistor M 2  is configured to use specific gate voltages based on its logic state to turn on. In some embodiments, the difference between these gate voltages is referred to as memory window. 
     The binary states of stored data in memory cell  200 A are encoded in the form of the polarization of the ferroelectric region  202 . The direction or value of the polarization (e.g., +P or −P) of the ferroelectric region  202  determines the resistance state (e.g., low or high) of the read transistor M 2 . In some embodiments, a low resistance state of the read transistor M 2  corresponds to the read transistor M 2  being turned on or conducting, and a high resistance state of the read transistor M 2  corresponds to the read transistor M 2  being turned off or not conducting. In some embodiments, a low resistance state of the read transistor M 2  corresponds to a first stored value (e.g., logic “0” or “1”), and a high resistance state of the read transistor M 2  corresponds to a second stored value (e.g., logic “1” or “0”) opposite from the first stored value. A voltage of the gate of the read transistor M 2  or node ND 1  controls the polarization states and corresponding electric field in the ferroelectric region  202  of read transistor M 2 . 
     Write transistor M 1  is configured to write data by controlling the voltage of node ND 1  or the gate of read transistor M 2  thereby controlling the polarization states of the ferroelectric region  202  of read transistor M 2 . In some embodiments, if the write transistor M 1  is enabled or turned on, a voltage of the write bit line WBL is configured to control the voltage of the node ND 1  or the gate of read transistor M 2 . Thus, in some embodiments, the polarized state of the ferroelectric region  202  is controlled by the voltage of the write bit line WBL. In some embodiments, the voltage of the write bit line WBL corresponds to the data stored in memory cell  200 A. In some embodiments, the polarization state of the ferroelectric region  202  is maintained even after an electric field or a corresponding voltage at node ND 1  is removed, and the read transistor M 2  is a non-volatile transistor device. 
     Read transistor M 2  is configured to read data stored in memory cell  200 A. In some embodiments, read transistor M 2  is configured to output data stored in memory cell  200 A based on whether read transistor M 2  is turned on or off. The polarization state of the ferroelectric region  202  determines whether read transistor M 2  is turned on or off. 
     In some embodiments, write transistor M 1  and read transistor M 2  each include channel regions that are formed of a same type of material. In some embodiments, write transistor M 1  and read transistor M 2  each have channel regions that have a silicon body or bulk. 
     Read transistor M 2  is shown as a PMOS transistor. In some embodiments, read transistor M 2  is an NMOS transistor. 
     During a write operation of memory cell  200 A, the voltage of the write bit line WBL (e.g., data to be stored in memory cell  200 A) is set by a write driver circuit (not shown), and the write word line WWL is set to a logical low thereby turning on write transistor M 1 . In response to write transistor M 1  being turned on, the voltage of the write bit line WBL is applied to the gate of read transistor M 2  or node ND 1 . As the voltage of the write bit line WBL is applied to the gate of read transistor M 2  or node ND 1 , the write bit line voltage controls the polarization state of the ferroelectric region  202  and the corresponding data stored by read transistor M 2 . In other words, the voltage of the write bit line WBL is used to set the read transistor M 2  in a low resistance state (e.g., conducting) or a high resistance state (e.g., not conducting). Afterwards, the write word line WWL is set to a logical high thereby turning off write transistor M 1 . 
     In response to write transistor M 1  being turned off, data stored in memory cell  200 A is held, and memory cell  200 A is in a hold mode. 
     By using ferroelectric region  202  in memory cell  200 A, memory cell  200 A does not have charge leakage at node ND 1  compared to other approaches (such as DRAM). By using ferroelectric region  202  in memory cell  200 A, the non-volatile nature of the ferroelectric material in ferroelectric region  202  is able to hold or maintain the polarization state even after the voltage at node ND 1  is removed thereby resulting in a longer data retention time and a larger memory window than other approaches. By having at least a longer data retention time or a larger memory window than other approaches, memory cell  200 A is refreshed less than other approaches resulting in less power consumption than other approaches. 
     In some embodiments, memory cell  200 A and memory cells  200 B- 200 C ( FIGS.  2 B- 2 C ) have a 2T memory cell structure that is compatible with complementary metal oxide semiconductor (CMOS) processes and is therefore scalable. 
     During a read operation of memory cell  200 A, the voltage of the read bit line RBL is pre-discharged to a logical low, and the read word line RWL is raised to a logical high. In some embodiments, if the read transistor M 2  is in a low resistance state, then the read transistor M 2  is turned on or conducting, and the current from the read word line RWL through the read transistor M 2  to the read bit line RBL is sensed by a sense amplifier (not shown), and the data associated with the read transistor M 2  being in a low resistance state (e.g., “1” or “0”) is read out. In some embodiments, if the read transistor M 2  is in a high resistance state, then the read transistor M 2  is turned off or not conducting, and the current from the read word line RWL through the read transistor M 2  to the read bit line RBL is sensed by a sense amplifier (not shown), and the data associated with the read transistor M 2  being in a high resistance state (e.g., “0” or “1”) is read out. In this embodiment, the current through the read transistor M 2  is negligible since the read transistor M 2  is turned off. Afterwards, the read word line RWL is set to a logical low. 
     Other transistor terminals for each of the transistors M 1 , M 2 , M 1 ′ or M 2 ′ (described below) of the present application are within the scope of the present disclosure. For example, reference to the drains and sources of a same transistor in the present disclosure can be changed to a source and a drain of the same transistor. Thus, for write transistor M 1 , reference to the drain and source of write transistor M 1  can be changed to the source and drain of write transistor M 1 , respectively. Similarly, for read transistor M 2 , reference to the drain and source of read transistor M 2  can be changed to the source and drain of read transistor M 2 , respectively. 
     Other configurations or quantities of transistors in memory cell  200 A are within the scope of the present disclosure. 
       FIG.  2 B  is a circuit diagram of a memory cell  200 B, in accordance with some embodiments. 
     Memory cell  200 B is an embodiment of a memory cell in array of memory cells  102 A of  FIG.  1    expressed in a schematic diagram, and similar detailed description is therefore omitted. 
     Memory cell  200 B is usable as one or more memory cells in array of memory cells  102 A of  FIG.  1   . Memory cell  200 B includes a write transistor M 1 ′, read transistor M 2 , write word line WWL, read word line RWL, write bit line WBL and read bit line RBL. 
     Memory cell  200 B is a variation of memory cell  200 A of  FIG.  2 A , and similar detailed description is therefore omitted. In comparison with memory cell  200 A of  FIG.  2 A , write transistor M 1 ′ replaces write transistor M 1  of  FIG.  2 A , and similar detailed description is therefore omitted. 
     Write transistor M 1 ′ is shown as a PMOS transistor. In some embodiments, write transistor M 1 ′ is an NMOS transistor. In some embodiments, write transistor M 1 ′ is similar to write transistor M 1  of  FIG.  2 A , and similar detailed description is therefore omitted. The operation of memory cell  200 B is similar to the operation of memory cell  200 A described above, and similar detailed description is therefore omitted. 
     In comparison with write transistor M 1  of  FIG.  2 A , write transistor M 1 ′ includes an oxide channel region  210 , and similar detailed description is therefore omitted. In some embodiments, one or more transistors having oxide channel regions of the present disclosure include thin film transistors (TFTs). In some embodiments, the oxide channel region  210  for write transistor M 1 ′ includes an oxide semiconductor material including zinc oxide, cadmium oxide, indium oxide, IGZO, SnO 2 , TiO 2 , or combinations thereof, or the like. Other transistor types or oxide materials for write transistor M 1 ′ are within the scope of the present disclosure. 
     In some embodiments, by including write transistor M 1 ′ with an oxide channel region  210  and an FeFET read transistor M 2 , memory cell  200 B has lower leakage current than other approaches that do not include an oxide channel region in the write transistor. In some embodiments, by reducing the leakage current of memory cell  200 B, memory cell  200 B has a longer data retention time than other approaches. By having a longer data retention time than other approaches, memory cell  200 B is refreshed less than other approaches resulting in less power consumption than other approaches. In some embodiments, by reducing the leakage current of memory cell  200 B, memory cell  200 B has less write disturbance errors than other approaches. Furthermore, since memory cell  200 B is similar to memory cell  200 A, memory cell  200 B also has the benefits discussed above with respect to memory cell  200 A. In some embodiments, the oxide channel region  210 ,  220 ,  230  or  240  of memory cell  200 B- 200 C,  300 B- 300 C and  400 B- 400 C ( FIGS.  2 B- 2 C,  3 B- 3 C &amp;  4 B- 4 C ) can be integrated into a back end of line (BEOL) process thereby increasing the memory density of memory cell  200 B- 200 C,  300 B- 300 C and  400 B- 400 C. 
     Other configurations, connections or quantities of transistors in memory cell  200 B are within the scope of the present disclosure. 
       FIG.  2 C  is a circuit diagram of a memory cell  200 C, in accordance with some embodiments. 
     Memory cell  200 C is an embodiment of a memory cell in array of memory cells  102 A of  FIG.  1    expressed in a schematic diagram, and similar detailed description is therefore omitted. 
     Memory cell  200 C is usable as one or more memory cells in array of memory cells  102 A of  FIG.  1   . Memory cell  200 C includes write transistor M 1 ′, a read transistor M 2 ′, write word line WWL, read word line RWL, write bit line WBL and read bit line RBL. 
     Memory cell  200 C is a variation of memory cell  200 B of  FIG.  2 B , and similar detailed description is therefore omitted. In comparison with memory cell  200 B of  FIG.  2 B , read transistor M 2 ′ replaces read transistor M 2  of  FIG.  2 B , and similar detailed description is therefore omitted. 
     Read transistor M 2 ′ is shown as a PMOS transistor. In some embodiments, read transistor M 2 ′ is an NMOS transistor. In some embodiments, read transistor M 2 ′ is similar to read transistor M 2  of  FIGS.  2 A- 2 B , and similar detailed description is therefore omitted. The operation of memory cell  200 C is similar to the operation of memory cell  200 A (described above) or memory cell  200 B, and similar detailed description is therefore omitted. 
     In comparison with read transistor M 2  of  FIG.  2 B , read transistor M 2 ′ includes an oxide channel region  220 , and similar detailed description is therefore omitted. In some embodiments, the oxide channel region  220  for read transistor M 2 ′ includes an oxide semiconductor material including zinc oxide, cadmium oxide, indium oxide, IGZO, SnO 2 , TiO 2 , or combinations thereof, or the like. 
     In some embodiments, the oxide channel region  220  of read transistor M 2 ′ includes the same oxide semiconductor material as the oxide channel region  210  of write transistor M 1 ′. In some embodiments, the oxide channel region  220  of read transistor M 2 ′ includes a different oxide semiconductor material as the oxide channel region  210  of write transistor M 1 ′. Other transistor types or oxide materials for read transistor M 2 ′ are within the scope of the present disclosure. 
     In some embodiments, read transistor M 2 ′ includes an oxide channel region  220 , and write transistor M 1 ′ includes a silicon channel region having a silicon body or bulk similar to write transistor M 1 . 
     In some embodiments, by including write transistor M 1 ′ with an oxide channel region  210  and read transistor M 2 ′ with an oxide channel region  220  and as an FeFET, memory cell  200 C has lower leakage current than other read transistor approaches. In some embodiments, by reducing the leakage current of memory cell  200 C, memory cell  200 C has the benefits discussed above with respect to memory cell  200 B. Furthermore, since memory cell  200 C is similar to memory cell  200 A, memory cell  200 C also has the benefits discussed above with respect to memory cell  200 A. 
     Other configurations, connections or quantities of transistors in memory cell  200 C are within the scope of the present disclosure. 
       FIG.  3 A  is a circuit diagram of a memory cell  300 A, in accordance with some embodiments. 
     Memory cell  300 A is an embodiment of a memory cell in array of memory cells  102 A of  FIG.  1    expressed in a schematic diagram, and similar detailed description is therefore omitted. 
     Memory cell  300 A is usable as one or more memory cells in array of memory cells  102 A of  FIG.  1   . Memory cell  300 A includes write transistor M 1 , read transistor M 2 , write word line WWL, read word line RWL, write bit line WBL, read bit line RBL and a transistor M 3 . 
     Memory cell  300 A is a variation of memory cell  200 A of  FIG.  2 A , and similar detailed description is therefore omitted. In comparison with memory cell  200 A of  FIG.  2 A , memory cell  300 A further includes transistor M 3 , and similar detailed description is therefore omitted. 
     Transistor M 3  includes a source terminal coupled to read bit line RBL, a drain terminal coupled to the source terminal of read transistor M 2 , and a gate terminal configured to receive a control signal CS. In some embodiments, transistor M 3  is turned on or turned off in response to control signal CS. For example, in some embodiments, during a read operation of a selected memory cell, similar to memory cell  300 A, the selected memory cell includes a selected transistor M 3 , and unselected memory cells, similar to memory cell  300 A, include an unselected transistor M 3 . In these embodiments, selected transistor M 3  is turned on in response to a first value of control signal CS, and unselected transistors M 3  in corresponding unselected cells are turned off in response to a second value of control signal CS. In these embodiments, the second value of control signal CS is inverted from the first value of control signal CS. In these embodiments, the transistors M 3  in unselected memory cells are turned off thereby reducing leakage current. 
     In comparison with memory cell  200 A of  FIG.  2 A , the source terminal of read transistor M 2  of  FIGS.  3 A- 3 C  is coupled with the drain terminal of transistor M 3 , and is therefore not directly coupled with the read bit line RBL as is shown in  FIG.  2 A . 
     Transistor M 3  of  FIGS.  3 A- 3 B  is enabled or disabled in response to a control signal CS. Transistor M 3  is configured to electrically couple/decouple read transistor M 2  to/from the read bit line RBL in response to control signal CS. For example, if control signal CS is logically low, transistor M 3  is enabled or turned on, and transistor M 3  thereby electrically couples the source of read transistor M 2  to the read bit line RBL. For example, if control signal CS is logically high, transistor M 3  is disabled or turned off, and transistor M 3  thereby electrically decouples the source of read transistor M 2  from the read bit line RBL. 
     The operation of memory cell  300 A is similar to the operation of memory cell  200 A described above, and similar detailed description is therefore omitted. For example, in comparison with the write operation of memory cell  200 A of  FIG.  2 A , during the write operation of memory cell  300 A, transistor M 3  is disabled or turned off, and the operation of the other portions of memory cell  300 A are similar to the write operation of memory cell  200 A described above, and similar detailed description is therefore omitted. For example, in comparison with the read operation of memory cell  200 A of  FIG.  2 A , during the read operation of memory cell  300 A, transistor M 3  is enabled or turned on, and the operation of the other portions of memory cell  300 A are similar to the read operation of memory cell  200 A described above, and similar detailed description is therefore omitted. 
     Transistor M 3  is shown as a PMOS transistor. In some embodiments, transistor M 3  is an NMOS transistor. 
     In some embodiments, transistor M 3  and at least write transistor M 1  or read transistor M 2 , include channel regions that are formed of a same type of material. In some embodiments, transistor M 3  has a channel region that has a silicon body or bulk. In some embodiments, transistor M 3  and at least write transistor M 1  or read transistor M 2 , include channel regions that have a silicon body or bulk. 
     In some embodiments, by including write transistor M 1 , read transistor M 2  (e.g., FeFET), and transistor M 3 , memory cell  300 A is similar to memory cell  200 A. In some embodiments, since memory cell  300 A is similar to memory cell  200 A, memory cell  300 A has the benefits discussed above with respect to memory cell  200 A. 
     In some embodiments, memory cell  300 A and memory cells  300 B- 300 C ( FIGS.  3 B- 3 C ) have a 3T memory cell structure that is compatible with CMOS processes and is therefore scalable. 
     Other transistor terminals for each of transistors M 1 , M 2 , M 3 , M 1 ′, M 2 ′ and M 3 ′ of the present application are within the scope of the present disclosure. For example, reference to the drains and sources of a same transistor in the present disclosure can be changed to a source and a drain of the same transistor. 
     Other configurations or quantities of transistors in memory cell  300 A are within the scope of the present disclosure. 
       FIG.  3 B  is a circuit diagram of a memory cell  300 B, in accordance with some embodiments. 
     Memory cell  300 B is an embodiment of a memory cell in array of memory cells  102 A of  FIG.  1    expressed in a schematic diagram, and similar detailed description is therefore omitted. 
     Memory cell  300 B is usable as one or more memory cells in array of memory cells  102 A of  FIG.  1   . Memory cell  300 B includes write transistor M 1 ′, read transistor M 2 , write word line WWL, read word line RWL, write bit line WBL, read bit line RBL and transistor M 3 . 
     Memory cell  300 B is a variation of memory cell  300 A of  FIG.  3 A  and memory cell  200 B of  FIG.  2 B , and similar detailed description is therefore omitted. For example, memory cell  300 B combines features similar to memory cell  300 A of  FIG.  3 A  and memory cell  200 B of  FIG.  2 B . 
     In comparison with memory cell  300 A of  FIG.  3 A , write transistor M 1 ′ of  FIG.  2 B  replaces write transistor M 1  of  FIG.  3 A , and similar detailed description is therefore omitted. 
     Write transistor M 1 ′ is described in memory cell  200 B of  FIG.  2 B , and similar detailed description is therefore omitted. Write transistor M 1 ′ is shown as a PMOS transistor. In some embodiments, write transistor M 1 ′ is an NMOS transistor. The operation of memory cell  300 B is similar to the operation of memory cell  300 A described above, and similar detailed description is therefore omitted. 
     In some embodiments, by including write transistor M 1 ′ with an oxide channel region  210 , read transistor M 2  (e.g., FeFET) and transistor M 3 , memory cell  300 B achieves benefits similar to the benefits discussed above with respect to memory cell  300 A and memory cell  200 B. 
     Furthermore, since memory cell  300 B is similar to memory cell  200 A, memory cell  300 B also has the benefits discussed above with respect to memory cell  200 A. 
     Other configurations, connections or quantities of transistors in memory cell  300 B are within the scope of the present disclosure. 
       FIG.  3 C  is a circuit diagram of a memory cell  300 C, in accordance with some embodiments. 
     Memory cell  300 C is an embodiment of a memory cell in array of memory cells  102 A of  FIG.  1    expressed in a schematic diagram, and similar detailed description is therefore omitted. 
     Memory cell  300 C is usable as one or more memory cells in array of memory cells  102 A of  FIG.  1   . Memory cell  300 C includes write transistor M 1 ′, read transistor M 2 ′, write word line WWL, read word line RWL, write bit line WBL, read bit line RBL and a transistor M 3 ′. 
     Memory cell  300 C is a variation of memory cell  300 B of  FIG.  3 B , and similar detailed description is therefore omitted. In comparison with memory cell  300 B of  FIG.  3 B , read transistor M 2 ′ replaces read transistor M 2  of  FIG.  3 B  and transistor M 3 ′ replaces transistor M 3  of  FIG.  3 B , and similar detailed description is therefore omitted. 
     Read transistor M 2 ′ is described in memory cell  200 C of  FIG.  2 C , and similar detailed description is therefore omitted. Read transistor M 2 ′ is shown as a PMOS transistor. In some embodiments, read transistor M 2 ′ is an NMOS transistor. 
     Transistor M 3 ′ is shown as a PMOS transistor. In some embodiments, transistor M 3 ′ is an NMOS transistor. In some embodiments, transistor M 3 ′ is similar to transistor M 3  of  FIGS.  3 A- 3 B , and similar detailed description is therefore omitted. The operation of memory cell  300 C is similar to the operation of memory cell  300 A (described above) or memory cell  300 B, and similar detailed description is therefore omitted. 
     In comparison with transistor M 3  of  FIG.  3 B , transistor M 3 ′ includes an oxide channel region  230 , and similar detailed description is therefore omitted. In some embodiments, the oxide channel region  230  for transistor M 3 ′ includes an oxide semiconductor material including zinc oxide, cadmium oxide, indium oxide, IGZO, SnO 2 , TiO 2 , or combinations thereof, or the like. 
     In some embodiments, the oxide channel region  230  of transistor M 3 ′ includes the same oxide semiconductor material as the oxide channel region  210 ,  220  of at least write transistor M 1 ′ or read transistor M 2 ′. In some embodiments, the oxide channel region  230  of transistor M 3 ′ includes a different oxide semiconductor material as the oxide channel region  210 ,  220  of at least write transistor M 1 ′ or read transistor M 2 ′. Other transistor types or oxide materials for transistor M 3 ′ are within the scope of the present disclosure. 
     In some embodiments, one of read transistor M 2 ′ or transistor M 3 ′ includes an oxide channel region  220  or  230 , and the other of read transistor M 2 ′ or transistor M 3 ′ includes a silicon channel region having a silicon body or bulk similar to read transistor M 2  or transistor M 3 , respectively. 
     In some embodiments, by including write transistor M 1 ′ with an oxide channel region  210 , read transistor M 2 ′ with an oxide channel region  220  and as an FeFET, and transistor M 3 ′ with an oxide channel region  230 , memory cell  300 C achieves benefits similar to the benefits discussed above with respect to memory cell  300 A and memory cell  200 C. Furthermore, since memory cell  300 C is similar to memory cell  200 A, memory cell  300 C also has the benefits discussed above with respect to memory cell  200 A. 
     Other configurations, connections or quantities of transistors in memory cell  300 C are within the scope of the present disclosure. 
       FIG.  4 A  is a circuit diagram of a memory cell  400 A, in accordance with some embodiments. 
     Memory cell  400 A is an embodiment of a memory cell in array of memory cells  102 A of  FIG.  1    expressed in a schematic diagram, and similar detailed description is therefore omitted. 
     Memory cell  400 A is usable as one or more memory cells in array of memory cells  102 A of  FIG.  1   . Memory cell  400 A includes write transistor M 1 , read transistor M 2 , write word line WWL, read word line RWL, write bit line WBL, read bit line RBL, transistor M 3  and a transistor M 4 . 
     Memory cell  400 A is a variation of memory cell  300 A of  FIG.  3 A , and similar detailed description is therefore omitted. In comparison with memory cell  300 A of  FIG.  3 A , memory cell  400 A further includes transistor M 4 , and similar detailed description is therefore omitted. 
     Transistor M 4  includes a drain terminal, a gate terminal and a source terminal. The drain terminal of transistor M 4  is coupled to read write line RWL. The gate terminal of transistor M 4  is coupled to the drain terminal of write transistor M 1 , the gate terminal of read transistor M 2  and node ND 1 . The source terminal of transistor M 4  is coupled to a node ND 2 . In some embodiments, node ND 2  is electrically coupled to a reference voltage supply. In some embodiments, the reference voltage supply has a reference voltage VSS. In some embodiments, the reference voltage supply corresponds to ground. 
     Transistor M 4  of  FIGS.  4 A- 4 C  is enabled or disabled in response to a voltage of node ND 1 . In some embodiments, the voltage of node ND 1  corresponds to the write bit line signal, and thus transistor M 4  of  FIGS.  4 A- 4 C  is enabled or disabled in response to the write bit line signal. 
     Transistor M 4  of  FIGS.  4 A- 4 C  is configured to electrically couple/decouple the read word line RWL to/from node ND 2  in response to the write bit line signal on the write bit line WBL. For example, if the write bit line signal is logically low, transistor M 4  is enabled or turned on, and transistor M 4  thereby electrically couples the read word line RWL to node ND 2 . For example, if the write bit line signal is logically high, transistor M 4  is disabled or turned off, and transistor M 4  thereby electrically decouples the read word line RWL from node ND 2 . 
     In comparison with memory cell  300 A of  FIG.  3 A , the drain terminal of read transistor M 2  of  FIGS.  4 A- 4 C  is coupled with a reference voltage supply. In some embodiments, the reference voltage supply has a reference voltage VSS. In some embodiments, the reference voltage supply corresponds to ground. 
     In comparison with memory cell  300 A of  FIG.  3 A , the gate terminal of transistor M 3  of  FIGS.  4 A- 4 C  is coupled with the read word line RWL. Transistor M 3  of  FIGS.  4 A- 4 C  is enabled or disabled in response to a read word line signal on the read word line RWL. Transistor M 3  of  FIGS.  4 A- 4 C  is configured to electrically couple/decouple read transistor M 2  to/from the read bit line RBL in response to the read word line signal on the read word line RWL. For example, if the read word line signal is logically low, transistor M 3  is enabled or turned on, and transistor M 3  thereby electrically couples the source of read transistor M 2  to the read bit line RBL. For example, if the read word line signal is logically high, transistor M 3  is disabled or turned off, and transistor M 3  thereby electrically decouples the source of read transistor M 2  from the read bit line RBL. 
     The operation of memory cell  400 A is similar to the operation of memory cell  200 A described above, and similar detailed description is therefore omitted. For example, in comparison with the write operation of memory cell  200 A of  FIG.  2 A  and memory cell  300 A of  FIG.  3 A , during the write operation of memory cell  400 A, transistor M 4  is enabled or disabled in response to the write bit line signal on the write bit line WBL, transistor M 3  is enabled or disabled in response to the read word line signal on the read word line RWL, and the operation of the other portions of memory cell  400 A are similar to the write operation of memory cell  200 A described above, and similar detailed description is therefore omitted. 
     During a read operation of memory cell  400 A, the voltage of the read bit line RBL is pre-charged to a logical high, and the read word line RWL is lowered to a logical low causing transistor M 3  to be enabled or turned on. In some embodiments, if the read transistor M 2  of  FIGS.  4 A- 4 C  is in a low resistance state, then the read transistor M 2  is turned on or conducting, and the voltage of the read bit line RBL is pulled towards VSS by read transistor M 2 , and the voltage or current of the read bit line RBL is sensed by a sense amplifier (not shown), and the data associated with the read transistor M 2  being in a low resistance state (e.g., “1” or “0”) is read out. In some embodiments, if the read transistor M 2  of  FIGS.  4 A- 4 C  is in a high resistance state, then the read transistor M 2  is turned off or not conducting, and the voltage of the read bit line RBL is not pulled towards VSS by read transistor M 2 , and the voltage or current of the read bit line RBL is sensed by a sense amplifier (not shown), and the data associated with the read transistor M 2  being in a high resistance state (e.g., “1” or “0”) is read out. In this embodiment, the change in the voltage of the read bit line RBL is negligible since the read transistor M 2  is turned off. Afterwards, the read word line RWL is set to a logical high thereby causing transistor M 3  to turn off. 
     Transistor M 4  is shown as a PMOS transistor. In some embodiments, transistor M 4  is an NMOS transistor. 
     In some embodiments, transistor M 4  and at least write transistor M 1 , read transistor M 2  or transistor M 3 , include channel regions that are formed of a same type of material. In some embodiments, transistor M 4  has a channel region that has a silicon body or bulk. 
     In some embodiments, by including write transistor M 1 , read transistor M 2  (e.g., FeFET), transistor M 3  and transistor M 4 , memory cell  400 A is similar to memory cell  200 A. In some embodiments, since memory cell  400 A is similar to memory cell  200 A, memory cell  400 A has the benefits discussed above with respect to memory cell  200 A. 
     In some embodiments, memory cell  400 A and memory cells  400 B- 400 C ( FIGS.  4 B- 4 C ) have a 4T memory cell structure that is compatible with CMOS processes and is therefore scalable. 
     Other transistor terminals for each of transistors M 1 , M 2 , M 3 , M 4 , M 1 ′, M 2 ′, M 3 ′ and M 4 ′ of the present application are within the scope of the present disclosure. For example, reference to the drains and sources of a same transistor in the present disclosure can be changed to a source and a drain of the same transistor. 
     Other configurations or quantities of transistors in memory cell  400 A are within the scope of the present disclosure. 
       FIG.  4 B  is a circuit diagram of a memory cell  400 B, in accordance with some embodiments. 
     Memory cell  400 B is an embodiment of a memory cell in array of memory cells  102 A of  FIG.  1    expressed in a schematic diagram, and similar detailed description is therefore omitted. 
     Memory cell  400 B is usable as one or more memory cells in array of memory cells  102 A of  FIG.  1   . Memory cell  400 B includes write transistor M 1 ′, read transistor M 2 , write word line WWL, read word line RWL, write bit line WBL, read bit line RBL, transistor M 3  and transistor M 4 . 
     Memory cell  400 B is a variation of memory cell  400 A of  FIG.  4 A  and memory cell  200 B of  FIG.  2 B , and similar detailed description is therefore omitted. For example, memory cell  400 B combines features similar to memory cell  400 A of  FIG.  4 A  and memory cell  200 B of  FIG.  2 B . 
     In comparison with memory cell  400 A of  FIG.  4 A , write transistor M 1 ′ of  FIG.  2 B  replaces write transistor M 1  of  FIG.  4 A , and similar detailed description is therefore omitted. 
     Write transistor M 1 ′ is described in memory cell  200 B of  FIG.  2 B , and similar detailed description is therefore omitted. Write transistor M 1 ′ is shown as a PMOS transistor. In some embodiments, write transistor M 1 ′ is an NMOS transistor. The operation of memory cell  400 B is similar to the operation of memory cell  400 A described above, and similar detailed description is therefore omitted. 
     In some embodiments, by including write transistor M 1 ′ with an oxide channel region  210  and read transistor M 2  (e.g., FeFET), transistor M 3  and transistor M 4 , memory cell  400 B achieves benefits similar to the benefits discussed above with respect to memory cell  400 A and memory cell  200 B. 
     Furthermore, since memory cell  400 B is similar to memory cell  200 A, memory cell  300 B also has the benefits discussed above with respect to memory cell  200 A. 
     Other configurations, connections or quantities of transistors in memory cell  400 B are within the scope of the present disclosure. 
       FIG.  4 C  is a circuit diagram of a memory cell  400 C, in accordance with some embodiments. 
     Memory cell  400 C is an embodiment of a memory cell in array of memory cells  102 A of  FIG.  1    expressed in a schematic diagram, and similar detailed description is therefore omitted. 
     Memory cell  400 C is usable as one or more memory cells in array of memory cells  102 A of  FIG.  1   . Memory cell  400 C includes write transistor M 1 ′, read transistor M 2 ′, write word line WWL, read word line RWL, write bit line WBL, read bit line RBL, transistor M 3 ′ and a transistor M 4 ′. 
     Memory cell  400 C is a variation of memory cell  400 B of  FIG.  4 B , and similar detailed description is therefore omitted. In comparison with memory cell  400 B of  FIG.  4 B , read transistor M 2 ′ replaces read transistor M 2  of  FIG.  4 B , transistor M 3 ′ replaces transistor M 3  of  FIG.  4 B  and transistor M 4 ′ replaces transistor M 4  of  FIG.  4 B , and similar detailed description is therefore omitted. 
     Read transistor M 2 ′ is described in memory cell  200 C of  FIG.  2 C , and similar detailed description is therefore omitted. Read transistor M 2 ′ is shown as a PMOS transistor. In some embodiments, read transistor M 2 ′ is an NMOS transistor. 
     Transistor M 3 ′ is described in memory cell  300 C of  FIG.  3 C , and similar detailed description is therefore omitted. Transistor M 3 ′ is shown as a PMOS transistor. In some embodiments, transistor M 3 ′ is an NMOS transistor. 
     Transistor M 4 ′ is shown as a PMOS transistor. In some embodiments, transistor M 4 ′ is an NMOS transistor. In some embodiments, transistor M 4 ′ is similar to transistor M 4  of  FIGS.  4 A- 4 B , and similar detailed description is therefore omitted. The operation of memory cell  400 C is similar to the operation of memory cell  400 A (described above) or memory cell  400 B, and similar detailed description is therefore omitted. 
     In comparison with transistor M 4  of  FIG.  4 B , transistor M 4 ′ includes an oxide channel region  240 , and similar detailed description is therefore omitted. In some embodiments, the oxide channel region  240  for transistor M 4 ′ includes an oxide semiconductor material including zinc oxide, cadmium oxide, indium oxide, IGZO, SnO 2 , TiO 2 , or combinations thereof, or the like. 
     In some embodiments, the oxide channel region  240  of transistor M 4 ′ includes the same oxide semiconductor material as the oxide channel region  210 ,  220  or  230  of at least write transistor M 1 ′, read transistor M 2 ′ or transistor M 3 ′. In some embodiments, the oxide channel region  240  of transistor M 4 ′ includes a different oxide semiconductor material as the oxide channel region  210 ,  220  or  230  of at least write transistor M 1 ′, read transistor M 2 ′ or transistor M 3 ′, respectively. Other transistor types or oxide materials for transistor M 4 ′ are within the scope of the present disclosure. 
     In some embodiments, one of read transistor M 2 ′, transistor M 3 ′ or transistor M 4 ′ includes an oxide channel region  220 ,  230  or  240 , and the other of read transistor M 2 ′, transistor M 3 ′ or transistor M 4  includes a silicon channel region having a silicon body or bulk similar to read transistor M 2 , transistor M 3  or transistor M 4 , respectively. 
     In some embodiments, by including write transistor M 1 ′ with an oxide channel region  210 , read transistor M 2 ′ with an oxide channel region  220  and as an FeFET, transistor M 3 ′ with an oxide channel region  230  and transistor M 4 ′ with an oxide channel region  240 , memory cell  400 C achieves benefits similar to the benefits discussed above with respect to memory cell  400 A and memory cell  200 C. Furthermore, since memory cell  400 C is similar to memory cell  200 A, memory cell  400 C also has the benefits discussed above with respect to memory cell  200 A. 
     Other configurations, connections or quantities of transistors in memory cell  400 C are within the scope of the present disclosure. 
       FIG.  5    is a cross-sectional view of an integrated circuit  500 , in accordance with some embodiments. 
     Integrated circuit  500  is an embodiment of read transistor M 2  and M 2 ′ of  FIGS.  2 A- 2 C,  3 A- 3 C and  4 A- 4 C , and similar detailed description is therefore omitted. In some embodiments, integrated circuit  500  includes additional elements not shown for ease of illustration. 
     Integrated circuit  500  is shown as a planar transistor; however, other transistors are within the scope of the present disclosure. In some embodiments, integrated circuit  500  is a fin field effect transistor (FinFET), a nanosheet transistor, a nanowire transistor, or the like. In some embodiments, integrated circuit  500  is an FeFET or the like, and is manufactured as part of a back end of line (BEOL) process. 
     Integrated circuit  500  includes a substrate  502 . In some embodiments, substrate  502  is a p-type substrate. In some embodiments, substrate  502  is an n-type substrate. In some embodiments, substrate  502  includes an elemental semiconductor including silicon or germanium in crystal, polycrystalline, or an amorphous structure; a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and GaInAsP; any other suitable material; or combinations thereof. In some embodiments, the alloy semiconductor substrate has a gradient SiGe feature in which the Si and Ge composition change from one ratio at one location to another ratio at another location of the gradient SiGe feature. In some embodiments, the alloy SiGe is formed over a silicon substrate. In some embodiments, first substrate  502  is a strained SiGe substrate. In some embodiments, the semiconductor substrate has a semiconductor on insulator structure, such as a silicon on insulator (SOI) structure. In some embodiments, the semiconductor substrate includes a doped epi layer or a buried layer. In some embodiments, the compound semiconductor substrate has a multilayer structure, or the substrate includes a multilayer compound semiconductor structure. 
     In some embodiments, integrated circuit  500  is a silicon transistor (e.g., has a silicon channel region (not labelled)), and substrate  502  has a silicon body or bulk. In some embodiments, integrated circuit  500  is an oxide transistor (e.g., has an oxide channel region  210 ,  220 ,  230  or  240 ), and substrate  502  includes an oxide semiconductor material including zinc oxide, cadmium oxide, indium oxide, IGZO, SnO 2 , TiO 2 , or combinations thereof, or the like. 
     Integrated circuit  500  further includes a drain region  504  and a source region  506  in substrate  502 . In some embodiments, at least a portion of source region  506  or a portion of drain region  504  extends above substrate  502 . In some embodiments, the source region  506  and the drain region  504  are embedded in substrate  502 . 
     Drain region  504  is an embodiment of the drain terminal of read transistor M 2  and M 2 ′ of  FIGS.  2 A- 2 C,  3 A- 3 C and  4 A- 4 C , and similar detailed description is therefore omitted. Source region  506  is an embodiment of the source terminal of read transistor M 2  and M 2 ′ of  FIGS.  2 A- 2 C,  3 A- 3 C and  4 A- 4 C , and similar detailed description is therefore omitted. 
     In some embodiments, the drain region  504  and source region  506  of  FIG.  5    is referred to as an oxide definition (OD) region which defines the source or drain diffusion regions of integrated circuit  500  or read transistor M 2  and M 2 ′ of  FIGS.  2 A- 2 C,  3 A- 3 C and  4 A- 4 C , and similar detailed description is therefore omitted. 
     In some embodiments, integrated circuit  500  is a P-type FeFET transistor, therefore the substrate  502  is an N-type region, the drain region  504  is a P-type active region having P-type dopants implanted in substrate  502 , and the source region  506  is a P-type active region having P-type dopants implanted in substrate  502 . 
     In some embodiments, integrated circuit  500  is an N-type FeFET transistor, therefore the substrate  502  is a P-type region, the drain region  504  is an N-type active region having N-type dopants implanted in substrate  502 , and the source region  506  is a an N-type active region having N-type dopants implanted in substrate  502 . 
     In some embodiments, N-type dopants include phosphorus, arsenic or other suitable N-type dopants. In some embodiments, P-type dopants include boron, aluminum or other suitable p-type dopants. 
     Integrated circuit  500  further includes an insulating layer  510  on substrate  502 . In some embodiments, the insulating layer  510  is between the drain region  504  and the source region  506 . In some embodiments, the insulating layer  510  is a gate dielectric layer. In some embodiments, the insulating layer includes an insulating material including SiO, SiO 2  or combinations thereof, or the like. In some embodiments, insulating layer  510  includes a gate oxide or the like. 
     Integrated circuit  500  further includes a metal layer  512  over the insulating layer  510 . In some embodiments, the metal layer  512  includes Cu, TiN, W or combinations thereof, or the like. In some embodiments, the metal layer  512  is a conductive layer including doped polysilicon. In some embodiments, integrated circuit  500  does not include metal layer  512 . 
     Integrated circuit  500  further includes a ferroelectric layer  520  over at least the conductive layer  512  or the insulating layer  510 . In some embodiments, where integrated circuit  500  does not include metal layer  512 , ferroelectric layer  520  is on the insulating layer  510 . Ferroelectric layer  520  is an embodiment of ferroelectric region  202  of  FIGS.  2 A- 2 C,  3 A- 3 C  and  4 A 4 C, and similar detailed description is therefore omitted. 
     In some embodiments, ferroelectric layer  520  includes a ferroelectric material. In some embodiments, a ferroelectric material includes HfO 2 , HfZrO, HfO, perovskite, SBT, PZT or combinations thereof, or the like. 
     Ferroelectric layer  520  has polarization states P1 or P2 that correspond to polarization states P+ or P− in  FIG.  2 A , and similar detailed description is therefore omitted. Polarization state P1 points in a first direction Y. Polarization state P2 points in a second direction (e.g., negative Y) opposite of the first direction Y. 
       FIG.  5    shows both polarization states P1 and P2. However, in some embodiments, due to the non-volatility of the ferroelectric layer  520 , once the polarization state P1 or P2 of integrated circuit  500  is set based on the gate voltage VG, integrated circuit  500  includes one of the polarization states P1 or P2. 
     The ferroelectric layer  520  creates a capacitance in integrated circuit  500 . Furthermore, the MOS transistor of integrated circuit  500  also has a capacitance. In some embodiments, the capacitance of the ferroelectric layer  520  and the capacitance of the MOS transistor are matched to operate integrated circuit  500  in a non-volatile mode. In some embodiments, the capacitance of the ferroelectric layer  520  is adjusted based on a thickness T 1  of the ferroelectric layer  520 . In some embodiments, by changing thickness T 1 , integrated circuit  500  can operate in a non-volatile mode or a volatile mode. 
     In some embodiments, the thickness T 1  of the ferroelectric layer  520  ranges from about 3 nanometers (nm) to about 50 nm. In some embodiments, as the thickness T 1  increases, the ability of the ferroelectric layer  520  to preserve the hysteresis and bi-stable polarization states (e.g., P1 or P2) is increased and the leakage current of integrated circuit  500  decreases. In some embodiments, as the thickness T 1  decreases, the ability of the ferroelectric layer  520  to preserve the hysteresis and bi-stable polarization states (e.g., P1 or P2) is reduced and the leakage current of integrated circuit  500  increases. In some embodiments, integrated circuit  500  does not include the insulating layer  510  and metal layer  512 , and the ferroelectric layer  520  is directly on substrate  502 . In some embodiments, integrated circuit  500  does not include the insulating layer  510 , and the metal layer  512  is directly on substrate  502 . 
     Integrated circuit  500  further includes a gate structure  530  over the ferroelectric layer  520 . The gate structure  530  includes a conductive material such as a metal or doped polysilicon (also referred to herein as “POLY”). 
     In some embodiments, integrated circuit  500  is an embodiment of write transistor M 1  and M 1 ′ of  FIGS.  2 A- 2 C,  3 A- 3 C and  4 A- 4 C . In these embodiments, integrated circuit  500  does not include the ferroelectric layer  520 . 
     By being included in memory cell array  100  and memory circuit  200 A- 200 C,  300 A- 300 C and  400 A- 400 C discussed above with respect to  FIGS.  1 ,  2 A- 2 C,  3 A- 3 C and  4 A- 4 C , integrated circuit  500  operates to achieve the benefits discussed above with respect to memory cell array  100  and memory circuit  200 A- 200 C,  300 A- 300 C and  400 A- 400 C. 
       FIG.  6    is a functional flow chart of a method  600  of manufacturing an integrated circuit (IC), in accordance with some embodiments. It is understood that additional operations may be performed before, during, and/or after the method  600  depicted in  FIG.  6   , and that some other processes may only be briefly described herein. In some embodiments, other order of operations of method  600  is within the scope of the present disclosure. Method  600  includes exemplary operations, but the operations are not necessarily performed in the order shown. Operations may be added, replaced, changed order, and/or eliminated as appropriate, in accordance with the spirit and scope of disclosed embodiments. In some embodiments, one or more of the operations of method  600  is not performed. 
     In some embodiments, the method  600  is usable to manufacture or fabricate at least memory cell array  100  ( FIG.  1   ), memory cell  200 A- 200 C,  300 A- 300 C or  400 A- 400 C ( FIG.  2 A- 2 C,  3 A- 3 C or  4 A- 4 C ) or integrated circuit  500  ( FIG.  5   ). 
     In operation  602  of method  600 , the drain region  504  of a transistor is fabricated in substrate  502 . In some embodiments, the drain region of method  600  includes at least the drain of read transistor M 2  or M 2 ′. In some embodiments, the transistor of method  600  includes at least read transistor M 2  or M 2 ′. In some embodiments, the drain region is fabricated in a first well within the substrate, and the first well has a dopant opposite of the dopant of the drain region. 
     In some embodiments, the transistor of method  600  includes at least transistor M 1 , M 1 ′, M 3 , M 3 ′, M 4  or M 4 ′. In some embodiments, the drain region of method  600  includes at least the drain of transistor M 1 , M 1 ′, M 3 , M 3 ′, M 4  or M 4 ′. 
     In operation  604  of method  600 , the source region  504  of the transistor is fabricated in substrate  502 . In some embodiments, the source region of method  600  includes at least the source of read transistor M 2  or M 2 ′. In some embodiments, the transistor of method  600  includes at least read transistor M 2  or M 2 ′. In some embodiments, the source region is fabricated in the first well. In some embodiments, the source region of method  600  includes at least the source of transistor M 1 , M 1 ′, M 3 , M 3 ′, M 4  or M 4 ′. 
     In some embodiments, at least operation  602  or  604  includes the formation of source/drain features that are formed in the substrate. In some embodiments, the formation of the source/drain features includes, a portion of the substrate is removed to form recesses, and a filling process is then performed by filling the recesses in the substrate. In some embodiments, the recesses are etched, for example, a wet etching or a dry etching, after removal of a pad oxide layer or a sacrificial oxide layer. In some embodiments, the etch process is performed to remove a top surface portion of the active region. In some embodiments, the filling process is performed by an epitaxy or epitaxial (epi) process. In some embodiments, the recesses are filled using a growth process which is concurrent with an etch process where a growth rate of the growth process is greater than an etch rate of the etch process. In some embodiments, the recesses are filled using a combination of growth process and etch process. For example, a layer of material is grown in the recess and then the grown material is subjected to an etch process to remove a portion of the material. Then a subsequent growth process is performed on the etched material until a desired thickness of the material in the recess is achieved. In some embodiments, the growth process continues until a top surface of the material is above the top surface of the substrate. In some embodiments, the growth process is continued until the top surface of the material is co-planar with the top surface of the substrate. In some embodiments, a portion of substrate  502  is removed by an isotropic or an anisotropic etch process. The etch process selectively etches substrate  502  without etching gate structure  530 . In some embodiments, the etch process is performed using a reactive ion etch (RIE), wet etching, or other suitable techniques. In some embodiments, a semiconductor material is deposited in the recesses to form the source/drain features. In some embodiments, an epi process is performed to deposit the semiconductor material in the recesses. In some embodiments, the epi process includes a selective epitaxy growth (SEG) process, CVD process, molecular beam epitaxy (MBE), other suitable processes, and/or combination thereof. The epi process uses gaseous and/or liquid precursors, which interacts with a composition of the substrate. In some embodiments, the source/drain features include epitaxially grown silicon (epi Si), silicon carbide, or silicon germanium. Source/drain features of the IC device associated with gate structure  530  are in-situ doped or undoped during the epi process in some instances. When source/drain features are undoped during the epi process, source/drain features are doped during a subsequent process in some instances. The subsequent doping process is achieved by an ion implantation, plasma immersion ion implantation, gas and/or solid source diffusion, other suitable processes, and/or combination thereof. In some embodiments, source/drain features are further exposed to annealing processes after forming source/drain features and/or after the subsequent doping process. 
     In some embodiments, source/drain features have n-type dopants that include phosphorus, arsenic or other suitable n-type dopants. In some embodiments, the n-type dopant concentration ranges from about 1×10 12  atoms/cm2 to about 1×10 14  atoms/cm2. 
     In some embodiments, source/drain features have p-type dopants that include boron, aluminum or other suitable p-type dopants. In some embodiments, the p-type dopant concentration ranges from about 1×10 12  atoms/cm2 to about 1×10 14  atoms/cm2. 
     In operation  606  of method  600 , an insulating layer  510  is fabricated on the substrate  502 . In some embodiments, at least fabricating the insulating layer  510  of operation  610  includes performing one or more deposition processes to form one or more dielectric material layers. In some embodiments, a deposition process includes a chemical vapor deposition (CVD), a plasma enhanced CVD (PECVD), an atomic layer deposition (ALD), or other process suitable for depositing one or more material layers. 
     In operation  608  of method  600 , a conductive layer is deposited on the insulating layer  510 . In some embodiments, the conductive layer of method  600  is metal layer  512 . In some embodiments, the conductive layer of operation  608  is formed using a combination of photolithography and material removal processes to form openings in an insulating layer (not shown) over the substrate. In some embodiments, the photolithography process includes patterning a photoresist, such as a positive photoresist or a negative photoresist. In some embodiments, the photolithography process includes forming a hard mask, an antireflective structure, or another suitable photolithography structure. In some embodiments, the material removal process includes a wet etching process, a dry etching process, an RIE process, laser drilling or another suitable etching process. The openings are then filled with conductive material, e.g., copper, aluminum, titanium, nickel, tungsten, or other suitable conductive material. In some embodiments, the openings are filled using CVD, PVD, sputtering, ALD or other suitable formation process. 
     In operation  610  of method  600 , a ferroelectric layer  520  is formed on at least the insulating layer  510  or the conductive layer (metal layer  512 ). In some embodiments, at least operation  606  or  608  is not performed. In some embodiments, operations  606  and  608  are not performed, and the ferroelectric layer  520  is formed directly on substrate  502 . In some embodiments, operation  606  is not performed and the conductive layer (e.g., metal layer  512 ) is deposited on substrate  502 . In some embodiments, operation  608  is not performed and the ferroelectric layer  520  is deposited on insulating layer  510 . 
     In operation  612  of method  600 , a gate region  530  of the transistor is fabricated. In some embodiments, fabricating the gate region includes performing one or more deposition processes to form one or more conductive material layers. In some embodiments, fabricating the gate regions includes forming gate electrodes. In some embodiments, gate regions are formed using a doped or non-doped polycrystalline silicon (or polysilicon). In some embodiments, the gate regions include a metal, such as Al, Cu, W, Ti, Ta, TiN, TaN, NiSi, CoSi, other suitable conductive materials, or combinations thereof. 
       FIG.  7    is a flowchart of a method  700  of operating a circuit, in accordance with some embodiments. In some embodiments,  FIG.  7    is a flowchart of method  700  of operating a memory circuit, such as memory cell array  100  of  FIG.  1    or memory cell  200 A- 200 C,  300 A- 300 C or  400 A- 400 C ( FIG.  2 A- 2 C,  3 A- 3 C or  4 A- 4 C ) or integrated circuit  500  ( FIG.  5   ). 
     It is understood that additional operations may be performed before, during, and/or after the method  700  depicted in  FIG.  7   , and that some other processes may only be briefly described herein. In some embodiments, other order of operations of method  700  is within the scope of the present disclosure. Method  700  includes exemplary operations, but the operations are not necessarily performed in the order shown. Operations may be added, replaced, changed order, and/or eliminated as appropriate, in accordance with the spirit and scope of disclosed embodiments. In some embodiments, one or more of the operations of method  700  is not performed. 
     In operation  702  of method  700 , a write operation of a memory cell is performed. In some embodiments, the memory cell of method  700  includes memory cell  200 A- 200 C,  300 A- 300 C or  400 A- 400 C. In some embodiments, the memory cell of method  700  includes at least a memory cell of memory cell array  100 . In some embodiments, operation  702  includes at least operation  704 ,  706 ,  708  or  710 . 
     In operation  704  of method  700 , a write bit line signal is set on a write bit line WBL. In some embodiments, the write bit line signal of method  700  includes a write bit line signal of write bit line WBL. In some embodiments, the write bit line signal corresponds to a stored data value in the memory cell. 
     In operation  706  of method  700 , a write transistor is turned on in response to a write word line signal thereby electrically coupling the write bit line WBL to a gate of a read transistor. In some embodiments, the write transistor of method  700  includes at least write transistor M 1  or M 1 ′. In some embodiments, the read transistor of method  700  includes at least read transistor M 2  or M 2 ′. In some embodiments, the gate of read transistor of method  700  includes at least the gate terminal of read transistor M 2  or M 2 ′. In some embodiments, the write word line signal of method  700  includes a write word line signal of write word line WWL. In some embodiments, the read transistor of method  700  includes integrated circuit  500 . In some embodiments, the write transistor of method  700  includes integrated circuit  500 . 
     In operation  708  of method  700 , the stored data value of the memory cell is set by adjusting a polarization state of the read transistor thereby turning on or off the read transistor. 
     In some embodiments, the polarization state of the read transistor of method  700  includes the polarization state P+ or P− of at least read transistor M 2  or M 2 ′. In some embodiments, the polarization state of the read transistor of method  700  includes the polarization state P1 or P2 of integrated circuit  500 . In some embodiments, the polarization state corresponds to the stored data value of the memory cell. 
     In operation  710  of method  700 , the write transistor is turned off in response to the write word line signal thereby electrically decoupling the write bit line and the gate of the read transistor from each other. In some embodiments, operation  710  further includes holding the stored data value in the memory cell. 
     In operation  712  of method  700 , a read operation of the memory cell is performed. In some embodiments, operation  712  includes at least operation  714 ,  716 ,  718  or  720 . 
     In operation  714  of method  700 , a voltage of a read bit line RBL is pre-discharged to a first voltage (VSS) or the voltage of the read bit line RBL is pre-charged to a second voltage (VDD) different from the first voltage. In some embodiments, the first voltage of method  700  includes reference voltage VSS. In some embodiments, the second voltage of method  700  includes supply voltage VDD. 
     In operation  716  of method  700 , a voltage of a read word line RWL is adjusted from a third voltage to a fourth voltage. In some embodiments, the voltage of the read word line RWL is the read word line signal. In some embodiments, the third voltage of method  700  includes a voltage of a logically high signal. In some embodiments, the third voltage of method  700  includes a supply voltage VDD. In some embodiments, the fourth voltage of method  700  includes a voltage of a logically low signal. In some embodiments, the fourth voltage of method  700  includes a reference voltage VSS. 
     In operation  718  of method  700 , the voltage of the read bit line is sensed in response to adjusting the voltage of the read word line from the third voltage to the fourth voltage thereby outputting the stored data value in the memory cell. In some embodiments, rather than sensing the voltage of the read word line, operation  718  includes sensing the current of the read bit line in response to adjusting the voltage of the read word line from the third voltage to the fourth voltage thereby outputting the stored data value in the memory cell. 
     In some embodiments, the stored data value of the memory cell has a first logical value corresponding to a first resistance state of the read transistor, or a second logical value corresponding to a second resistance state of the read transistor. In some embodiments, the second logical value is opposite of the first logical value. In some embodiments, the second resistance state is opposite of the first resistance state. In some embodiments, first logical value is one of logical 1 or logical 0, and the second logical value is the other of logical 0 or logical 1. In some embodiments, the first resistance state is one of the low resistance state or the high resistance state and the second resistance state is the other of the high resistance state or the low resistance state. 
     In some embodiments, adjusting the voltage of the read word line RWL from the third voltage to the fourth voltage of operation  718  comprises turning on a first transistor in response to a first control signal or the voltage of the read word line being the fourth voltage thereby electrically coupling the read bit line to a source of the read transistor. In some embodiments, the first transistor of method  700  includes transistor M 3  or M 3 ′. In some embodiments, the first control signal of method  700  includes control signal CS. In some embodiments, the source of the read transistor of method  700  includes the source terminal of read transistor M 2  or M 2 ′. 
     In operation  720  of method  700 , the voltage of the read word line is adjusted from the fourth voltage to the third voltage. In some embodiments, adjusting the voltage of the read word line from the fourth voltage to the third voltage of operation  720  comprises turning off the first transistor in response to the first control signal or the voltage of the read word line being the third voltage thereby electrically decoupling the read bit line and the source of the read transistor from each other. 
     By operating method  700 , the memory circuit operates to achieve the benefits discussed above with respect to memory cell array  100  of  FIG.  1    or memory cell  200 A- 200 C,  300 A- 300 C or  400 A- 400 C ( FIG.  2 A- 2 C,  3 A- 3 C or  4 A- 4 C ) or integrated circuit  500  ( FIG.  5   ). 
     While method  700  was described above with reference to a single memory cell of memory cell array  100 , it is understood that method  700  applies to each row and each column of memory cell array  100 , in some embodiments. 
     Furthermore, various PMOS or NMOS transistors shown in  FIG.  2 A- 2 C,  3 A- 3 C or  4 A- 4 C  are of a particular dopant type (e.g., N-type or P-type) are for illustration purposes. Embodiments of the disclosure are not limited to a particular transistor type, and one or more of the PMOS or NMOS transistors shown in  FIG.  2 A- 2 C,  3 A- 3 C or  4 A- 4 C  can be substituted with a corresponding transistor of a different transistor/dopant type. Similarly, the low or high logical value of various signals used in the above description is also for illustration. Embodiments of the disclosure are not limited to a particular logical value when a signal is activated and/or deactivated. Selecting different logical values is within the scope of various embodiments. Selecting different numbers of transistors in  FIG.  2 A- 2 C,  3 A- 3 C or  4 A- 4 C  is within the scope of various embodiments. 
     It will be readily seen by one of ordinary skill in the art that one or more of the disclosed embodiments fulfill one or more of the advantages set forth above. After reading the foregoing specification, one of ordinary skill will be able to affect various changes, substitutions of equivalents and various other embodiments as broadly disclosed herein. It is therefore intended that the protection granted hereon be limited only by the definition contained in the appended claims and equivalents thereof. 
     One aspect of this description relates to a memory cell. The memory cell includes a write bit line, a read word line, and a write transistor coupled between the write bit line and a first node. In some embodiments, the memory cell further includes a read transistor coupled to the write transistor by the first node. In some embodiments, the read transistor includes a ferroelectric layer, a drain terminal of the read transistor coupled to the read word line, and a source terminal of the read transistor coupled to a second node. In some embodiments, the write transistor is configured to set a stored data value of the memory cell by a write bit line signal that adjusts a polarization state of the read transistor, the polarization state corresponding to the stored data value. In some embodiments, the write transistor includes a drain terminal of the write transistor coupled to the write bit line; a source terminal of the write transistor coupled to the first node and the read transistor; and a gate terminal of the write transistor coupled to a write word line. In some embodiments, the read transistor further includes a gate terminal of the read transistor coupled to the source terminal of the write transistor by the first node, and the gate terminal of the read transistor is on the ferroelectric layer. In some embodiments, the source terminal of the read transistor is coupled to a read bit line by the second node. In some embodiments, the memory cell further includes a first transistor coupled to the read transistor. In some embodiments, the first transistor includes a drain terminal of the first transistor coupled to the source terminal of the read transistor by the second node; a source terminal of the first transistor coupled to a read bit line; and a gate terminal of the first transistor. In some embodiments, the gate terminal of the first transistor is configured to receive a control signal. In some embodiments, the read transistor includes a channel region of the read transistor; a gate insulating layer over the channel region of the read transistor; and a gate layer on the ferroelectric layer, where the ferroelectric layer is between the gate insulating layer and the gate layer. 
     Another aspect of this description relates to a memory cell. The memory cell includes a write bit line, a write word line, a read word line, and a write transistor of a first type. In some embodiments, the write transistor is coupled to the write bit line, the write word line and a first node. In some embodiments, the write transistor is configured to be enabled or disabled in response to a write word line signal. In some embodiments, the memory cell further includes a read transistor of the first type. In some embodiments, the read transistor includes a drain terminal of the read transistor is coupled to the read word line, and a gate terminal of the read transistor coupled to the write transistor by the first node, and a ferroelectric layer having a polarization state that corresponds to a stored data value in the memory cell. In some embodiments, the write transistor is configured to set the stored data value in the memory cell by a write bit line signal that adjusts the polarization state of the ferroelectric layer. In some embodiments, the read transistor further includes a source terminal of the read transistor coupled to a second node. In some embodiments, the source terminal of the read transistor is coupled to a read bit line by the second node. In some embodiments, the memory cell further includes a first transistor of the first type, coupled to the read transistor. In some embodiments, the first transistor includes a drain terminal of the first transistor coupled to the source terminal of the read transistor by the second node; a source terminal of the first transistor coupled to a read bit line; and a gate terminal of the first transistor configured to receive a control signal. In some embodiments, the write transistor includes an oxide channel region; and the read transistor includes a silicon channel region. In some embodiments, the write transistor includes an oxide channel region; and the read transistor includes another oxide channel region. In some embodiments, the read transistor further includes a gate insulating layer over a channel region of the read transistor; and a gate layer on the ferroelectric layer. In some embodiments, the ferroelectric layer is between the gate insulating layer and the gate layer. In some embodiments, the ferroelectric layer includes a ferroelectric material including HfO 2 , HfZrO, HfO or combinations thereof. 
     Still another aspect of this description relates to a method of operating a memory cell. The method includes a method of operating a memory cell, the method may include. The method further includes performing a read operation of the memory cell, the performing the read operation of the memory cell may include: pre-discharging a voltage of a read bit line to a first voltage or pre-charging the voltage of the read bit line to a second voltage different from the first voltage, adjusting a voltage of a read word line from a third voltage to a fourth voltage, sensing the voltage of the read bit line in response to adjusting the voltage of the read word line from the third voltage to the fourth voltage thereby outputting a stored data value in the memory cell, and adjusting the voltage of the read word line from the fourth voltage to the third voltage. In some embodiments, adjusting the voltage of the read word line from the third voltage to the fourth voltage includes turning on a first transistor in response to a first control signal or the voltage of the read word line being the fourth voltage thereby electrically coupling the read bit line to a source of a read transistor. In some embodiments, adjusting the voltage of the read word line from the fourth voltage to the third voltage includes turning off a first transistor in response to a first control signal or the voltage of the read word line being the third voltage thereby electrically decoupling the read bit line and a source of a read transistor from each other. In some embodiments, the stored data value of the memory cell has a first logical value corresponding to a first resistance state of a read transistor, or a second logical value corresponding to a second resistance state of the read transistor, the second logical value being opposite of the first logical value, the second resistance state being opposite of the first resistance state. In some embodiments, the method further includes performing a write operation of the memory cell. 
     The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.