Patent Publication Number: US-2023157019-A1

Title: Process for a 3-dimensional array of horizontal nor-type memory strings

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     The present application is a continuation application of U.S. patent application (“Parent Application”), Ser. No. 16/924,531, entitled “PROCESS FOR A 3-DIMENSIONAL ARRAY OF HORIZONTAL NOR-TYPE MEMORY STRINGS,” filed on Jul. 9, 2020, which is related to and claims priority of U.S. provisional patent application (“Provisional Application”), Ser. No. 62/872,174, entitled “PROCESS FOR A 3-DIMENSIONAL ARRAY OF HORIZONTAL NOR-TYPE MEMORY STRINGS,” filed on Jul. 9, 2019. The disclosures of the Parent Application and the Provisional Application are hereby incorporated by reference in their entireties. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a fabrication process for memory circuits. In particular, the present invention relates to a fabrication process for a 3-dimensional array of NOR-type memory strings. 
     2. Discussion of the Related Art 
     The Non-provisional Applications disclose 3-dimensional arrays of horizontal NOR-type memory strings (“HNOR arrays”) and methods for fabricating such HNOR arrays. In this description, a NOR-type memory string includes numerous storage transistors sharing a common source region and a common drain region. A storage transistor in this context is a variable-threshold transistor whose threshold voltage is determined by the amount of electrical charge trapped or stored in a charge storage region (e.g., an oxide-nitride-oxide triple-layer) provided between a channel region and a gate region. Reading, programming, inhibiting and erasing operations carried out on the storage transistor are accomplished by applying proper voltage biases to the source, drain, gate and channel regions of the storage transistor. In one example, an HNOR array is fabricated over a planar surface of a semiconductor substrate and includes a regular arrangement of horizontal NOR-type memory strings (“HNOR memory strings”). In this disclosure, the terms “horizontal” and “vertical” refer, respectively, to directions that are substantially parallel and substantially orthogonal to the planar surface. Each HNOR string includes storage transistors formed along one or both sides of a strip of semiconductor material (“active strip”), with each active strip including (i) two heavily-doped semiconductor layers providing, respectively, the common drain and the common source regions for the storage transistors, and (ii) a layer of lightly-doped semiconductor layer provided between the heavily-doped semiconductor layers. The lightly-doped semiconductor layer provides channel regions for the storage transistors. In the example, at least one of the heavily-doped semiconductor layers is in contact with a metallic conductive layer along its length to reduce the electrical resistance in the heavily-doped semiconductor layer. Multiple active strips may be stacked one on top of another (“active stack”), and multiple active stacks may be formed side-by-side and spaced from each other to form an HNOR array. A charge-trapping layer is provided on the sidewalls of each active stack. Between adjacent active stacks are provided vertical conductors, each serving as a local word line that connects the gate electrodes of storage transistors in multiple active strips of two adjacent active stacks. A storage transistor may be formed where the lightly-doped semiconductor layer of an active strip overlaps a vertical conductor, isolated from the vertical conductor by a charge-trapping material. 
     SUMMARY 
     The present invention provides highly efficient fabrication processes for HNOR arrays. In these processes, the channel regions of the storage transistors in the HNOR arrays are protected by a protective layer after deposition until the subsequent deposition of a charge-trapping material before forming local word lines. Both the silicon for the channel regions and the protective material may be deposited in amorphous form and are subsequently crystallized in an anneal step. The protective material may be silicon boron, silicon carbon or silicon germanium. The protective material induces greater grain boundaries in the crystallized silicon in the channel regions, thereby providing greater charge carrier mobility, greater conductivity and greater current densities. 
     According to one embodiment of the present invention, a process comprising: (a) forming, above a planar surface of a substrate, a structure comprising a plurality of groups of material layers, each group of material layers (“active layer”) provided one above another along a first direction substantially orthogonal to the planar surface of the substrate, each active layer including (i) first and second layers of a first material, (ii) a layer of a second material provided between the first and second layers of the first material, and (iii) an isolation layer separating the active layer from an adjacent active layer; (b) etching a first set of trenches through the active layers, with each trench running along a second direction substantially parallel to the planar surface of the substrate, thereby forming a first plurality of material stacks (“active stacks”) out of the structure; (c) in each active stack, forming recesses into the layers of the second material by removing a portion of each layer of the second material from sidewalls of the active stack; (d) depositing conformally a layer of a channel material over the sidewalls of the active stacks; (e) depositing a layer of a protective material over the layer of the channel material and filling the recesses; (f) etching back the layer of the protective material to expose the layer of the channel material on the sidewalls of the active stacks, while retaining, in each recess of each active stack, a portion of the layer of protective material to cover a corresponding portion of the layer of the channel material; (g) removing exposed portions of the layer of the channel material from the side walls of the active stacks; and (h) filling the first set of trenches by a fifth material. 
     In some embodiments, the isolation layer comprises silicon oxy-carbide (SiOC), the second material comprises a silicon oxide, which may also selected for the fifth material. The channel material may a lightly-doped p-type or n-type semiconductor material, while the first material may be a heavily-doped n-type or p-type semiconductor material (i.e., of opposite dopant type as the third material). The first material may be first provided as a sacrifice material and subsequently replaced by the semiconductor material, so as to reduce the number of deposition and in situ doping steps for the semiconductor materials. 
     The active stacks may be formed by multiple trench-forming steps, with each successive trench-forming dividing the active stacks into narrow active stacks. Oxide pillars may be provided to lend mechanical support for the active stacks during the trench-forming steps. The oxide pillars may be anchored in the substrate. 
     According to one embodiment of the present invention, after each trench-forming step, the steps (c) to (g) above are repeated to provide the channel material and the protective covering. Thereafter, the process (a) forms a plurality of shafts in the trenches, exposing in each shaft the portions of the protective material; and (b) removes the portions of the protective material to expose the corresponding portions of the channel material. A charge trapping layer on the sidewalls of the shafts may then be deposited and the shafts filled with a conductive material. In some embodiment, the shafts may also be formed in multiple successive etch step. At each such etch step, the shafts that are formed in previous etch step is filled with a sacrificial material. In this manner, even though the etch steps are high aspect ratio etch steps, the sacrificial material lends mechanical support. The sacrificial material may be, for example, silicon oxy-carbide (SiOC). 
     Using the process steps of the present invention, the each active layer of each active stack in the HNOR array thus formed includes a common source region, a common drain region and a channel region for the storage transistors. The conductors in the shafts provide the local word lines. The local word lines may be connected to decoding circuitry by global word lines that may be provided above or below the HNOR array. 
     The present invention is better understood upon consideration of the detailed description below in conjunction with the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG.  1    shows cross sections A and B of semiconductor structure  100 , at one intermediate step of a fabrication process for an HNOR array, according to one embodiment of the present invention. 
         FIG.  2    shows resulting cross sections A and B of semiconductor structure  100  of  FIG.  1   , after a recess step creates a recess in HTO layer  107 , in accordance with one embodiment of the present invention. 
         FIG.  3    shows resulting cross sections A and B of semiconductor structure  100  of  FIG.  2   , after depositions of amorphous silicon layer  301  and SiGe layer  302 , in accordance with one embodiment of the present invention. 
         FIG.  4    shows resulting cross sections A and B of semiconductor structure  100  of  FIG.  3   , after anisotropic and isotropic etch steps of SiGe layer  302 , in accordance with one embodiment of the present invention. 
         FIG.  5    shows resulting cross sections A and B of semiconductor structure  100  of  FIG.  4   , after an isotropic etch step of polysilicon layer  301 , in accordance with one embodiment of the present invention. 
         FIG.  6   a    is a top view (i.e., an X-Y plane view), showing locations of exemplary pillars  601 - 1  to  601 - 5  on exemplary active stacks  112 - 1  to  112 - 3  in semiconductor structure  100  of  FIG.  5   , in accordance with one embodiment of the present invention. 
         FIG.  6   b    shows resulting cross sections A and B of semiconductor structure  100  of  FIG.  5   , after filling pillars  601  and trenches  112  with silicon oxide and planarization by CMP, in accordance with one embodiment of the present invention. 
         FIG.  7    shows resulting cross sections A and B of semiconductor structure  100  of  FIG.  6   b   , after creating trenches  114 - 1  and  114 - 2  in active stacks  112 - 2  and  112 - 3  by etching the active layers down to etch stop layer  104 , in accordance with one embodiment of the present invention. 
         FIG.  8    shows resulting cross sections A and B of semiconductor structure  100  of  FIG.  7   , after replacement of SAC1 material in layers  106  and  108  by N + -doped polysilicon, in accordance with one embodiment of the present invention. 
         FIG.  9   a    shows resulting cross sections A and B of semiconductor structure  100  of  FIG.  8   , after replacing SAC2 layers  109  with metallic conductor layer  109  (“drain metal”) and providing, in recessed portions of oxide layers  107  of active stacks  701 , a second set of polysilicon layers  301  and SiGe layers  302 , in accordance with one embodiment of the present invention. 
         FIG.  9   b    shows X-Y plane cross sections C and D of a portion of semiconductor structure  100  of  FIG.  9   a   , along line A-A′ through N + -doped polysilicon layer  106  or  108 , and along line B-B′ through HTO  107 , respectively, after first set of memory holes  901 - 1  to  901 - 3  are cut, in accordance with one embodiment of the present invention. 
         FIG.  10    shows cross sections C and D of semiconductor structure  100  of  FIG.  9   b   , after memory holes  901 - to  901 - 3  are filled with SiOC, in accordance with one embodiment of the present invention. 
         FIG.  11    shows cross sections C and D of semiconductor structure  100  of  FIG.  10   , after second set of memory holes  902 - 1  to  902 - 3  are cut, in accordance with one embodiment of the present invention. 
         FIG.  12    shows cross sections C and D of semiconductor structure  100  of  FIG.  11   , after removal of the SiOC material from first set of memory holes  901 - 1  to  901 - 3 , in accordance with one embodiment of the present invention. 
         FIG.  13    shows cross sections C and D of semiconductor structure  100  of  FIG.  12   , after an oxide etch step expands memory holes  901  and  902 , in accordance with one embodiment of the present invention. 
         FIG.  14    shows cross sections C and D of semiconductor structure  100  of  FIG.  13   , after a SiGe etch step removes SiGe at memory holes  901  and  902 , thereby exposing channel polysilicon layer  302  underneath, in accordance with one embodiment of the present invention. 
         FIG.  15    shows cross sections C and D of semiconductor structure  100  of  FIG.  14   , after successive conformal depositions of ONOA layer  1101  and polysilicon liner  1102 , in accordance with one embodiment of the present invention. 
         FIG.  16    shows cross sections C and D of semiconductor structure  100  of  FIG.  15   , after the punch-through etch step exposes conductor-filled vias  1201  at the bottom of memory holes  901 , in accordance with one embodiment of the present invention. 
         FIG.  17    shows cross sections C and D of semiconductor structure  100  of  FIG.  16   , after memory holes  901  and  902  are conductor-filled, in accordance with one embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The present invention provides highly efficient fabrication processes for HNOR arrays.  FIG.  1    shows cross sections A and B of semiconductor structure  100 , at one intermediate step of a fabrication process for an HNOR array, according to one embodiment of the present invention. Initially, a network of interconnection conductors (“bottom word lines”)  102 , such as tungsten conductors, are formed above a planar surface of substrate  101 . Substrate  101  may be, for example, a semiconductor wafer (e.g., a silicon wafer). Bottom word lines  102 —including conductor-filled via for their electrical connection—may be formed using, for example, a damascene process. In the damascene process, bottom word lines  102  are defined and deposited in insulator layer  103  (e.g., silicon oxide), and chemical-mechanical polished (CMP). Bottom word lines  102  are provided as parallel conductors running along the same direction. To facilitate this detailed description, the vertical direction in the figures is indicated by the Z-direction and the cross sections A and B in the figures are seen as taken in the X-Z plane, with the Y-direction being the direction orthogonal to both the X- and Z-directions. 
     As shown in  FIG.  1   , cross sections A and B are, respectively, vertical sections through oxide layer  103  between adjacent conductors of bottom word lines  102  and through a conductor of bottom word line  102 , respectively. Thereafter, etch-stop layer  104  (e.g., a  50 - 100 . A thick layer of aluminum oxide) is provided to protect bottom word lines  102  and to carry out subsequent etching steps with greater precision. Several groups of material layers—each group being referred herein as an “active layer”—are then successively formed over etch-stop layer  104 . As described below, the material layers in each active layer may be a functional layer or a precursor (or “sacrificial” layer) to a functional layer in an active strip. In  FIG.  1   , even though only two active layers (i.e., active layers  110 - 1  and  110 - 2 ) are shown, solely for the purpose of illustration, any suitable number of active layers may be provided (e.g., 8, 16, 32 or more). Active layer  110 - 1  includes (i) deposited oxide layer  105 - 1  (e.g., 500-1500 Å thick layer of silicon oxy-carbide or “SiOC”); (ii) first sacrificial layer  106 - 1  (first “SAC1” layer; e.g., a 350-1100 Å thick layer of silicon nitride), (iii) high temperature oxide (HTO) layer  107 - 1  (e.g., 500-1500 Å), (iv) second SAC1 layer  108 - 1  (e.g., 150-500 Å thick), and (v) second sacrificial layer  109 - 1  (“SAC2” layer; e.g., 250-700 Å thick layer of silicon boron (SiB), silicon carbon (SiC) or silicon-germanium (SiGe)). The other active layers (e.g., active layer  110 - 2 ) each have substantially the same material layers. In this description, a suffixed reference numeral indicates a reference to a specific instance (“specific reference”). For example, the suffixed reference “105-1” refers is a reference to a specific instance of a set of like features that are each referenced generally by reference numeral “105.” A statement that is made in the context of a general reference (i.e., a non-specific reference) is applicable to all specific references. 
     Hard mask  111  is then provided on the active layers. An anisotropic etch of the active layers  110  down to etch-stop layer  104  is then carried out, to form first set of active stacks  112  (e.g., active stacks  112 - 1 ,  112 - 2 , . . . and  112 - n ) and trenches  113  (e.g., trenches  113 - 1 ,  113 , . . . and  113 - n ). Active stacks  112  and trenches  113  may be, for example, 190 nm and 70 nm wide (X-direction), respectively. 
     In this embodiment, as discussed below, first and second SAC1 layers  106 - 1  and  108 - 1  are to be replaced at a subsequent step by in situ-doped N +  polysilicon to provide source and drain regions, respectively, for the storage transistors. Silicon nitride may be used for the SAC1 layers, because of the etch-selectivity of silicon nitride available relative to HTO layer  107 . SAC2 layer  109 - 1  is to be subsequently replaced by a metal layer to provide a low resistivity in the drain region. Any of silicon boron, silicon carbon and silicon germanium may be selected for SAC2 layer  109 - 1 , on account of their etch-selectivity (e.g., in hot phosphoric acid) relative to N + -doped polysilicon. 
     Thereafter, an isotropic oxide etch step recesses HTO oxide  107  (e.g., by 75-250 Å) in each active layer. The resulting cross sections of semiconductor structure  100  is shown in  FIG.  2   . Amorphous silicon layer  301  (e.g., 40-120 Å thick) is then deposited conformally over the sidewalls of active stacks.  112 , including the recessed surface of HTO layers  107 . Following the conformal deposition of amorphous silicon layer  301 , amorphous silicon germanium (SiGe) layer  302  (e.g., 100-300 Å thick) is deposited over amorphous silicon layer  301 . An anneal step may then be carried out to crystallize both amorphous silicon layer  301  and amorphous SiGe layer  302  into crystallized layers. Amorphous silicon layer  301  becomes a polysilicon layer. 
     SiGe layer  302  provides numerous benefits. As SiGe typically has larger grain boundaries than polysilicon, crystallization of amorphous silicon in the presence of SiGe results in a material that also has larger grain boundaries than typical polysilicon and, hence, a greater carrier mobility. The greater carrier mobility provides both a greater electrical conductivity and an ability to sustain a higher electrical current density. SiGe layer  302  also protects polysilicon layer  301  from various subsequent etch steps (e.g., anisotropic dry etch steps) and prevents polysilicon stringers from being formed out of polysilicon silicon layer  301 .  FIG.  3    shows resulting cross sections A and B of semiconductor structure  100  of  FIG.  2   , after depositions of amorphous silicon layer  301  and SiGe layer  302 , in accordance with one embodiment of the present invention. 
     An anisotropic etch step, followed by an isotropic etch, are then carried out to remove SiGe layer  302  from the sidewalls of active stacks  112 . During these etches, inside the recessed portions of HTO layer  107 , SiGe layer  302  shields polysilicon layer  301  underneath. The isotropic etch step may be tuned with high selectivity (e.g., 100:1) to polysilicon to avoid damaging the exposed portions of polysilicon layer  301 .  FIG.  4    shows resulting cross sections A and B of semiconductor structure  100  of  FIG.  3   , after anisotropic and isotropic etch steps of SiGe layer  302 , in accordance with one embodiment of the present invention. 
     Thereafter, an isotropic etch step (e.g., a radical etch step using hydrogen, chlorine, ammonia, or any combination of these species, in either atomic or molecular form) removes polysilicon layer  301  from the sidewalls of active stacks  112 . This isotropic etch step may be tuned with high selectivity (e.g., 100:1) to SiGe to avoid removal of the remaining SiGe layer  302  from the recessed portions of HTO layer  107 .  FIG.  5    shows resulting cross sections A and B of semiconductor structure  100  of  FIG.  4   , after the isotropic etch step of polysilicon layer  301 , in accordance with one embodiment of the present invention. These portions of polysilicon layer  301  (“channel polysilicon layer  301 ”) that are overlaid and protected by SiGe layer  302  are intended for serving subsequently as channel regions of storage transistors in the HNOR array. 
     In some embodiments, where the number of active layers in an active stack is large, it may be desirable to design the etch steps creating active stacks  112  to have less than a predetermined aspect ratio. In one method, the active stacks in an HNOR array are created by multiple etch steps. Oxide pillars are also provided to lend mechanical support to the active stacks.  FIG.  6   a    is a top view (i.e., a view over an X-Y plane), showing locations of exemplary oxide pillars  601 - 1  to  601 - 5  on exemplary active stacks  112 - 1  and  112 - 2 , in accordance with one embodiment of the present invention. In  FIG.  6   a   , exemplary active stacks  112 - 1  and  112 - 2  each extend lengthwise along the Y-direction, spaced apart along the X-direction by exemplary trench  113 - 1 . Underneath active stacks  112 - 1  and  112 - 2  and running along the X-direction are bottom word lines  102  (e.g., exemplary bottom word lines WL- 1  to WL- 3 ). 
       FIG.  6   a    shows in dashed lines exemplary bottom word lines WL- 1 , WL- 2  and WL- 3 . Active stacks  112 - 1  and  112 - 2  may each be, for example, 70 nm wide along the X-direction. Bottom word lines WL- 1  to WL- 3  may be 40 nm apart and may each have a width, for example, of 40 nm along the Y-direction. Exemplary oxide pillars  601 - 1 ,  601 - 2  and  601 - 3  are provided in a staggered formation in adjacent active stacks  112 - 1  and  112 - 2 . Each oxide pillar may be oval and may have X- and Y-dimensions of 40 nm and 80 nm, respectively. As shown in  FIG.  6   a   , oxide pillars  601 - 1  and  601 - 3  each overlap half the width of each of adjacent bottom word lines WL- 1  and WL- 2 , and pillar  601 - 2  overlaps half the width of each of adjacent bottom word lines WL- 2  and WL- 3 . Not having sharp corners allow the oxide pillars to be formed using relatively less demanding etch steps. The mechanical support required during the etch steps of active stack formation may be satisfied by having oxide pillars  601 - 3  and  601 - 4 —which are both provided on active stack  113 - 2 —placed even microns apart along the Y-direction. 
     Oxide pillars  601  are positioned in each active stack such that, when an additional etch step—described below in conjunction with  FIG.  7   —creates additional trenches  114 , active stacks  112  are each further divided into smaller active stacks  701 . For example, as illustrated in  FIG.  6   a   , active trenches  114 - 1  and  114 - 2  are to be formed between dashed lines  651 - 1  and  651 - 2  and between dashed lines  651 - 3  and  651 - 4 , respectively, resulting in active stacks  112 - 1  and  12 - 2  being further divided into active stacks  701 - 1  to  701 - 4 . 
     Following the isotropic polysilicon etch step of  FIG.  5   , the shafts for oxide pillars  601  are etched. To provide the requisite mechanical support, the pillar shafts extend through the active layers, etch stop layer  104 , isolation layer  103  and bottom word line layer  102  into substrate  101 . Trenches  113 - 1  and  113 - 2  and the pillar shafts are then filled with a silicon oxide.  FIG.  6   b    shows resulting cross sections A and B of semiconductor structure  100  of  FIG.  5   , after filling pillar shafts of oxide pillars  601  and trenches  113  with silicon oxide and planarization by CMP, in accordance with one embodiment of the present invention. 
     With the mechanical support by oxide pillars  601  and oxide-filled trenches  113 , additional trenches  114  are created in active stacks  112  by an etch step that remove the active layers down to etch stop layer  104 .  FIG.  7    shows resulting cross sections A and B of semiconductor structure  100  of  FIG.  6   , after creating trenches  114 - 1  and  114 - 2  in active stacks  112 - 2  and  112 - 3  by etching the active layers down to etch stop layer  104 , in accordance with one embodiment of the present invention. As shown in  FIG.  7   , trenches  114 - 1  and  114 - 2  are created by etching active stacks  112 - 1  and  112 - 2 . This etch step divides active stacks  112  into active stacks  701 . For example, as shown in  FIG.  7   , active stacks  112 - 1  and  112 - 2  are divided by this etch step into active stacks  701 - 1 ,  701 - 2 ,  701 - 3  and  701 - 4 , respectively. Active stacks  701  and trenches  114  may be 70 nm and 60 nm wide, respectively, along the X-direction. 
     Trenches  114  expose the sidewalls of active stacks  701 . SAC1 layers  106  and  108  of each of active layers  110  are then replaced by N +  polysilicon layers  106  and  108  using an isotropic etch step (e.g., hot phosphoric acid) of the SAC1 material, followed by an in situ N + -doped polysilicon deposition (e.g., dopant concentration ˜0.5-1.5×10 21  cm −3 ). An anisotropic etch then removes excess N + -doped polysilicon from trenches  114 , thereby preventing any shorting between N+-doped polysilicon layers  106  and  108 . Thereafter, a wet clean step (e.g., SC-1 cleaning, aqueous hydrofluoric acid and deionized water) may be performed.  FIG.  8    shows resulting cross sections A and B of semiconductor structure  100  of  FIG.  7   , after replacement of the SAC1 material in SAC1 layers  106  and  108  by N + -doped polysilicon, in accordance with one embodiment of the present invention. 
     Then, SAC2 layers  109  are replaced by metallic conductor layers. As SAC2 layers  109  may be SiB, SiC, SiGe or any of their combinations, SAC2 layers  109  may be removed using a suitable highly selective radical etch that is selective to oxide, nitride, and silicon. Such a radical etch may be accomplished using, for example, gaseous Cl 2 , F 2  or both. A metal-fill step using a suitable metal (e.g., tungsten (W)) may then be carried out, following deposition of a liner material (e.g., titanium nitride (TiN)). An anisotropic etch step then removes the excess fill-metal and the liner from trench  114 . Thereafter, the steps of  FIGS.  2 - 5    (i.e., recessing the HTO layer, depositions of amorphous silicon and SiGe layers, annealing, anisotropic and isotropic etch steps of the SiGe layer, and the isotropic etch step of the polysilicon layer that results from annealing the amorphous silicon), as illustrated by the description above, are then carried out along the sidewalls of active stacks  701  to prepare additional channel regions in the exposed sidewalls of active stacks  701 . Thereafter, trenches  114  are filled with a silicon oxide and are planarized by a CMP step. 
       FIG.  9   a    shows resulting cross sections A and B of semiconductor structure  100  of  FIG.  8   , after replacing SAC2 layers  109  with metallic conductor layer  109  (“drain metal”) and providing, in recessed portions of oxide layers  107  of active stacks  701 , a second set of channel polysilicon layers  301  and SiGe layers  302 , in accordance with one embodiment of the present invention. 
     First set of local word line shafts (“memory holes”)  901  are then excavated by an oxide etch step in oxide-filled trenches  112  and  114 . The etch step excavates the silicon oxide in oxide-filled trenches  112  and  114  down to etch stop layer  104 .  FIG.  9   b    shows X-Y plane cross sections C and D of semiconductor structure  100  of  FIG.  9   a   , along line A-A′ through N + -doped polysilicon layer  106  or  108 , and along line B-B′ through HTO  107 , respectively, after first set of memory holes  901 - 1  to  901 - 3  are cut, in accordance with one embodiment of the present invention. As shown in  FIG.  9   b   , first set of memory holes  901  are arranged in a staggered formation. 
     First set of memory holes  901  are then filled with SiOC, as a sacrificial material.  FIG.  10    shows cross sections C and D of semiconductor structure  100  of  FIG.  9   b   , after memory holes  901 - to  901 - 3  are filled with SiOC, in accordance with one embodiment of the present invention. Thereafter, second set of memory holes  902  are excavated by an oxide etch step in oxide-filled trenches  112  and  114 ; memory holes  902  are also arranged in a staggered formation. The etch step excavates the silicon oxide in oxide-filled trenches  112  and  114  down to etch stop layer  104 .  FIG.  11    shows cross sections C and D of semiconductor structure  100  of  FIG.  10   , after second set of memory holes  902 - 1  to  902 - 3  are excavated, in accordance with one embodiment of the present invention. 
     The SiOC material in memory holes  901  and  902  is then removed by an etch step.  FIG.  12    shows cross sections C and D of semiconductor structure  100  of  FIG.  11   , after removal of the SiOC material from first set of memory holes  901 - 1  to  901 - 3  and  901 - 1  to  902 - 3 , in accordance with one embodiment of the present invention. An oxide recess step is then carried out to expand memory holes  901  and  902 .  FIG.  13    shows cross sections C and D of semiconductor structure  100  of  FIG.  12   , after the oxide etch step expands memory holes  901  and  902 , in accordance with one embodiment of the present invention. Note that, in both oxide-filled trenches  112  and  114 , the X-direction width at cross section D (i.e., cross section through oxide layer  107 , channel polysilicon layer  301  and SiGe layer  302 ) is less than the X-direction width at cross section C (i.e., cross section through N + -doped polysilicon layer  106 ) because of SiGe layers  302 . Consequently, the oxide recess steps that expand memory holes  901  and  902  in the X-direction at cross section D reaches SiGe layers  302  before reaching the sidewalls of N + -doped polysilicon layer  106  at cross section C. Thus, at cross section D, memory holes  901  and  902  are therefore oval. The oxide recess step may be a time-controlled etch step. The final critical dimensions of memory hole  901  and  902  depend on the etch time. 
     A SiGe etch step then breaks through SiGe layer  302  at memory holes  901  and  902  to expose underlying channel polysilicon layer  301 .  FIG.  14    shows cross sections C and D of semiconductor structure  100  of  FIG.  13   , after a SiGe etch step removes the SiGe material from memory holes  901  and  902 , thereby exposing channel polysilicon layer  302  underneath, in accordance with one embodiment of the present invention. 
     Thereafter, successive depositions of conformal layers of silicon oxide ( 1101   a ), silicon nitride ( 1101   b ), silicon oxide ( 1101   c ) and aluminum oxide ( 1101   d ) are carried out to form charge-trapping (“ONOA”) layer  1101 . Silicon oxide (“tunnel oxide”) layer  1101   a  may be, for example, 1.0-1.5 nm thick. Silicon nitride layer  1101   b —which traps charge carriers that tunnel through tunnel oxide  1101   a  from channel polysilicon  301 —may be, for example, 3.0-5.0 nm thick. Silicon oxide layer  1101   c  and aluminum oxide layer  1101   d , which may be ˜1.5-4.5 nm and ˜1.0-3.0 nm, respectively, form a “blocking” layer. A further sacrificial layer of polysilicon (“polysilicon liner”)  1102  may be provided to protect ONOA layer  1101  during the next etch steps.  FIG.  15    shows cross sections C and D of semiconductor structure  100  of  FIG.  14   , after successive conformal depositions of ONOA layer  1101  and polysilicon liner  1102 , in accordance with one embodiment of the present invention. 
     An anisotropic etch step removes the portions of ONOA layer  1101  and polysilicon liner  1102  at the bottom of memory holes  901  and  902 , thereby exposing etch stop layer  104 . In this embodiment, memory holes  901  are provided above conductor-filled vias  1201  that allow electrical connections to selected ones of underlying bottom word lines  102 . A punch-through etch step removes etch stop layer  104  at the bottom of memory holes  901 , such that the conductor plugs (e.g., tungsten) that are to be subsequently placed in memory holes  901  to serve as local word lines may be voltage-biased from bottom word lines  102 . In this embodiment, conductor plugs (e.g., tungsten) in memory holes  902  are provided to serve as local word lines that are voltage-biased from word lines (“top word lines”) to be formed above memory structure  100 .  FIG.  16    shows cross sections C and D of semiconductor structure  100  of  FIG.  15   , after the punch-through etch step exposes conductor-filled vias  1201  at the bottom of memory holes  901 , in accordance with one embodiment of the present invention. 
     Polysilicon liner  1102  is then removed. A conformal adhesion layer—such as a metal liner (e.g., titanium nitride) layer—is deposited into memory holes  901  and  902 , which is followed by a metal filling step (e.g., tungsten). Planarization using a CMP step may then be carried out.  FIG.  17    shows cross sections C and D of semiconductor structure  100  of  FIG.  16   , after memory holes  901  and  902  are conductor-filled and planarized, in accordance with one embodiment of the present invention. 
     The top word lines and other interconnect layers may then be provided in a conventional manner. 
     The above detailed description is provided to illustrate specific embodiments of the present invention and is not intended to be limiting. Numerous variations and modifications within the scope of the present invention are possible. The present invention is set forth in the accompanying claims below.