Patent Publication Number: US-5528756-A

Title: Method and apparatus for performing supervisory functions in digital systems and obtaining diagnostics thereof

Description:
FIELD OF THE INVENTION 
     This invention relates to digital system supervisory and diagnostic circuitry and more particularly to a method and apparatus that performs supervisory functions such as a watchdog and low voltage detects and obtains diagnostic thereof for use with micro-processor-based industrial control equipment. 
     DESCRIPTION OF THE PRIOR ART 
     Supervisory functions such as watchdog circuits and low voltage detect circuits have been available for many years and are well known in the electronic development field. Existing methods for watchdog circuits include using a capacitively coupled signal from an address decoder in order to reset an analog or digital watchdog timer. One drawback of such a method is that the micro-processor may lose its place in the program sequence and inadvertently output an address in the watchdog address field. Should that occur the watchdog timer will reset as if everything is all right. 
     Electro-Magnetic Interference (EMI) or Radio Frequency Interference (RFI) are the most common causes for a microprocessor based system&#39;s program sequence to fail. Terms such as &#34;the micro-processor got lost&#34; are often used to refer to the effects of the above types of interference. For ease of description these interferences will be referred to hereinafter as EMI. 
     EMI can be conducted through wiring or radiated through the air. The effects of EMI can cause the address bus or data bus to change states in one or more printed circuit board trace lines. Usually that one change is all that it takes to get the micro-processor to start operating from the wrong memory locations or on incorrect data. A capacitively coupled or single address type watchdog is typically not sufficient due to the fact that it is quite possible for the micro-processor, after an EMI upset, to inadvertently output an address within the watchdog address field. The watchdog may not activate a reset if EMI causes the code to be stuck in a loop which happens to have the watchdog activation write command or if EMI causes a jump to execute code out of a data structure that happens to contain a combination of data which appears as being within the watchdog address field. 
     Improved watchdog methods have used two address or data sets to activate sequentially in order to prevent just one accidental instance of the micro-processor from triggering the watchdog circuit. This is a vast improvement over the single address approach. However, these watchdogs are typically designed to activate one address or data than the other over a fixed period of time in order to clear the watchdog timer. 
     Depicted in FIGS. 1a and b are block diagrams of two typical approaches used in the prior art for watchdog function circuitry. The prior art circuit 60 of FIG. 1a has an address decoder 62 which receives an address 67 from the microprocessor 61. If the address 67 is within the decoded range, the decoder 62 will output a variation in signal 68, which is directly connected to the watchdog timer 65. Such a signal may be a normally high signal that pulses low for a short period of time. This variation in output signal can also be coupled to the watchdog timer 65 through capacitor 63 rather than directly connected as is signal 68. Capacitor 63 only passes a signal from decoder 62 to watchdog timer 65 that changes states. Regardless of how the signal gets to the watchdog timer 65, the watchdog timer 65 is cleared by the level or the edge direction of the signal. The timer 64 within the watchdog may be set with an analog circuit such as a resistor-capacitor (RC) network or digitally with a counter. If the watchdog timer 65 is not cleared within the time period set by the RC network or counter in timer 64 then a reset signal 69 is generated for a system reset 66. 
     The prior art watchdog circuit 70 of FIG. 1b is an improvement over the circuit 60. Circuit 70 is often incorporated within micro-processor chips. An address 79 from the micro-processor 71 is decoded by address decoder 72. An address field is assigned to the watchdog function; however, only certain data 80 is recognized by the data decoder 73. The logic 74 determines whether the combination of decoded address and data is valid to clear the watchdog timer 76. The time period and enable/disable watchdog is typically set by data 78 from the micro-processor 71 once within so many cycles after a reset condition. 
     The limitation in time from a reset is required because this type of watchdog circuit 70 is very susceptible to a lost micro-processor writing to enable or disable the watchdog function. The reason for the susceptibility is that it would take only one write to the address field to enable or disable the watchdog function. Although this possibility of EMI disabling the watchdog function still exists during the first number of cycles in circuit 70, the limitation on the number of accessible cycles reduces the probability of an inadvertent watchdog disable. Unfortunately, this type of watchdog circuit 70 requires the software to handle the enable/disable feature during a predetermined number of initial cycles from reset. This requirement could become a potential problem if the system software is burdened with several functions requiring nearly immediate attention from start-up. 
     The advancement of electronic products has increased the reliability and interrelationship of software related functions and algorithms. Systems used in industrial control applications require watchdog type functions for the micro-processor based products. The dependency on software in these products has increased substantially as well; hence, having a watchdog clear timer operation every so many lines of code is not necessarily good enough, nor desirable, in some cases. Applying a watchdog function to a consecutive series of larger tasks is more likely to be a better approach. If the micro-processor does get lost and starts running some loop that happens to have the prior art watchdog activation sequence within the loop, then the watchdog may not trigger a reset. What is needed is an approach that can be customized to fit the current software development requirements and is flexible enough to adapt to the section of code that is running at the time. 
     Often the prior art methods require the watchdog to be enabled or disabled within the first so many cycles after a reset with the hope that EMI will not reprogram the enable/disable state during this time. Not only is this approach susceptible during this time, but it does not provide the flexibility to change the watchdog state during normal operation. Hence, once the watchdog is set with prior art methods it does not have the flexibility to work with a variety of individual software routine requirements. 
     Another problem with the prior art watchdog functions is the inability to distinguish an EMI reset from a power failure reset. This type of diagnostic would be very helpful in several applications. For example, in industrial control installations, EMI or problems with the electrical power, such as spikes or dips, can create reset problems. However, the solution to correcting the installation depends on which type of reset problem is exhibited, whether it is a result of EMI or electrical power problems. Often, industrial installations are only monitored once in a while, unless of course there is an obvious problem. Therefore, intermittent reset failures may go undetected for very long periods of time. Furthermore, different software functions may be warranted given either an EMI reset or a power failure reset. 
     There are very simple circuits in the prior art for monitoring the voltage level of the power supply. One such circuit 190 is shown in FIG. 2. A reference voltage (V --  REF) 191 can be set by a zener diode or other means and input to one input of a comparator 193. The voltage supply line signal (VCC) 192 goes into the other input of the comparator 193. Commonly a resistor divider (not shown) is set between the voltage supply line and ground to create a center tapped voltage that is used as the voltage supply line signal 192 that is to be compared to a voltage reference signal 191. Occasionally a positive feedback resistor R1 of high resistance is placed across the comparator 193 in order to provide hysteresis. In this case, it may be necessary to swap the polarity of the connections of the signals 191 and 192 at the inputs to the comparator 193. 
     The hysteresis is used to eliminate multiple oscillations on the low voltage detect (LVD) output signal 194 which can occur from noise on the incoming voltage supply signal 192. Multiple oscillations can cause havoc on a system when the LVD signal 194 is used as the system reset. Depending on the system reset configuration, the signal from comparator 193 may or may not need to be inverted with a simple logic inverter. The high resistance feedback resistor which provides the hysteresis for immunity from multiple oscillations is not suited for implementation in integrated circuit chip implementations and requires extensive silicon area. 
     FIG. 2 also shows the waveforms for the VCC, V --  REF and LVD signals. The threshold 196 for the reference voltage 191 is displayed as a dashed line. The voltage supply signal 197 rises in amplitude as power is applied. The LVD signal 195 does not go high until the voltage supply signal 197 surpasses the reference voltage threshold 196. In a similar manner, the LVD signal 195 goes low as soon as the voltage supply signal 197 falls below the reference voltage threshold 196. 
     In contrast to the prior art, the present invention provides a technique that eliminates oscillations from the reset signal while using a simple comparator without the hysteresis feedback resistor. This technique is ideally suited for integrated circuit chip applications. The present invention eliminates oscillations by providing a delay whose length is programmable by the user and is designed so that the length of the delay can never be zero. 
     In addition, the present invention provides the ability to detect between EMI resets and power failures resets. Furthermore, the present invention allows flexible watchdog features that permit a variety of watchdog activations in order to safely customize to various software tasks which are being run in the system. 
     SUMMARY OF THE INVENTION 
     A method for performing a watchdog function in a digital system which has a control cycle. In the method first and second signals are generated for at least a predetermined number of times every control cycle. In every control cycle a predetermined pattern of occurrence of the first and second signals is counted until a predetermined count is reached. The method determines by no later than the end of each control cycle if the predetermined count has or has not been obtained. The digital system is reset if it has been determined that the predetermined count was not obtained by no later than the end of a control cycle. 
     A method for performing diagnostics in a digital system that has a control cycle. In the method a watchdog function is enabled during one of the control cycles. The enabled watchdog function is then performed in the manner described above in each of the control cycles that are subsequent to the control cycle in which the watchdog function is enabled. 
     A method for performing diagnostics in a digital system that has a control cycle. In the method the enabled watchdog function is then performed in the manner described above in each of the control cycles. 
     A method for performing a low voltage detect function in a digital system that has a control cycle. In the method the voltage of a power supply in the system is monitored. A signal which indicates low power supply voltage is generated when the monitored voltage is below a reference voltage. In response to the signal indicative of low power supply voltage the digital system is reset and the control cycles are stopped. The power supply voltage is monitored and a signal indicative of adequate power supply voltage is generated when the low power supply voltage rises above the reference voltage. The method then starts the first control cycle a predetermined time after the generation of the signal that indicates an adequate power supply voltage. The method selects in a control cycle a time duration for those control cycles that occur subsequent to the control cycle in which the time duration is selected. 
    
    
     DESCRIPTION OF THE DRAWINGS 
     FIGS. 1a and 1b are block diagrams of two prior art implementation for a watchdog function. 
     FIG. 2 shows an implementation of a low voltage detect circuit from the prior art and waveforms associated therewith. 
     FIG. 3 the diagnostic circuitry of the invention. 
     FIG. 4 is a diagram which shows the waveforms of the signals associated with the diagnostic functions. 
     FIG. 5 shows the digital clock timing signal generation circuitry for the diagnostic circuitry. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT (s) 
     Depicted in FIG. 3 is one embodiment for the watchdog circuit 10 of the present invention. A data bus 11 from a micro-processor based system (not shown) is input to a decoder 13. Control lines 12 from the micro-processor based system are input to logic 15. These control lines 12 can be, but not limited to, read/write and chip select signals from the micro-processor based system. The logic 15 enables the decoder 13. An AND gate 16 receives inputs in the form of the watchdog state signal 14, the decoder watchdog down signal 43 and the reset external signal 33. The NAND gate 17 has inputs from another NAND gate 18 and the decoder watchdog up signal 42. The NAND gate 18 has inputs from the other NAND gate 17 and AND gate 16. 
     Inverter 19 inverts the signal from NAND gate 18 to provide a signal 44 which is used to clock data flip-flop 22. The D flip-flops 22, 23, 24, and 25 each have their inverted output &#34;Q NOT&#34; tied to their data input &#34;D&#34;. The Q NOT signal of each flip-flop is also tied to the clock input of the next flip-flop, that is Q NOT of 22 is tied to the D input of 23, etc. The flip-flop clear (CLR) terminals for the flip-flops 22-25 are tied to receive signal 36 from AND gate 35. The watchdog state signal 14 is determined from the inverted output of flip-flop 25. 
     The watchdog state signal 14 also feeds the data input of flip-flop 21. Flip-flop 21 is clocked from a latch watchdog state signal 20. The signal 20 is generated from a clock 0 generation circuit 160 shown in FIG. 5, and more specifically from signal 181 which has the waveform 181W as shown in FIG. 5. The output &#34;Q&#34; 37 of flip-flop 25 goes to the data input &#34;D&#34; of flip-flop 26. Watchdog enable/disable signal 41, also from decoder 13, is used to clock flip-flop 26. Flip-flops 26 and 21 are cleared by the reset external signal 33. The output &#34;Q&#34; of flip-flop 26 is the watchdog disabled status signal 27. The NAND gate 29 receives one input from the inverted output 45 of flip-flop 26 and the other input from the output signal 46 of flip-flop 21. A low voltage detect (LVD) signal 34 comes from a comparator circuit 190 (see FIG. 2). The signal 34 is shown in FIG. 2 as signal 194 having a waveform 195. This LVD signal 34 is one input to a NAND gate 30 whose other input is from NAND gate 29. 
     A cycle start pulse signal 28 comes from circuit 160 of FIG. 5. The signal 28 is shown in FIG. 5 as signal 184 having a waveform 184W. This cycle start pulse signal 28 can be used to indicate the start of a control cycle in an industrial control product and is one input to a NOR gate 31 whose other input comes from NOR gate 32. NOR gate 32 has one input from NOR gate 31 as well as its other input from NAND gate 30. The output of NOR gate 32 produces the reset external signal 33. This reset external signal 33 feeds one input to an AND gate 35 which also has an input from the cycle start pulse signal 28 which is inverted at the AND gate 35 input. Inverter 38 inverts the reset external signal 33 to provide an output that is used to clock flip-flop 39. Data for flip-flop 39 comes from the LVD signal 34 which also is used to clear the flip-flop 39. 
     The output &#34;Q&#34; of flip-flop 39 is the reset status 40. The reset status signal 40 provides an indication of the cause of the last reset. If the reset status signal is a zero the last reset resulted from a low voltage detect whereas if the reset status signal is a one the last reset was caused by the watchdog. Therefore, the monitoring of the reset status signal provides the ability to discriminate between the cause of the reset. 
     A person skilled in the art can appreciate that certain predictable events can clearly be associated with causing these distinguishable resets. For example, a dip in system power supply voltage would most likely cause a low voltage detect reset; whereas, a strong EMI spike would most likely cause a watchdog reset. The user of the system in which the present invention is included could take advantage of this information by customizing the system reset program to expedite the system initialization given the knowledge of the type of reset which has just occurred. 
     FIG. 4 shows the timing relationship between various signals in circuit 10. Timing waveform 143 relates to watchdog down signal 43. Timing waveform 142 relates to watchdog up signal 42. Timing waveform 141 relates to watchdog enable/disable signal 41. Timing waveform 144 which is indicative of signal 44 shows the operation due to the watchdog up 142 and down 143 signals. It should be noted that there is a break, portrayed as a vertical squiggly line, in the waveforms shown above the dashed line in FIG. 4. The break is necessary for the presentation of the waveforms in the figure because waveform 144 has to have eight rising edges before waveform 137, which correlates to signal 37, will go high. As can be seen in FIG. 4, the watchdog up signal causes a rising edge on the signal 44 and the watchdog down signal causes a trailing edge on the signal 44. Therefore, in order for signal 44 to have the eight rising edges there must be at least fifteen alternating operations of the watchdog up and down signals. 
     It should also be noted that waveform 114, which correlates to watchdog state signal 14, is the inverse of waveform 137. The signal 14 can be monitored by the micro-processor to verify clearing the watchdog state. Several states of the watchdog can be monitored by the micro-processor simply by routing the desired signals such as WD --  S 14, WD --  D 27, and STAT 40, to the input of a data latch (not shown) which the micro-processor can access. The methods for latching, clocking, and accessing this data from the data latch to the micro-processor will not be described since these methods are well known to any one skilled in the art. 
     Additional watchdog up and down operations are acceptable both in alternating and consecutive forms as can be seen in waveforms 143, 142, and 144 as long as the minimum number of alternating operations described above is met. Software routines can therefore be designed to operate just one of the watchdog operations such as a single watchdog up operation in a specifically called subroutine function. A task can run this subroutine function from once to a number of times possibly based on some passed parameter to the subroutine, which is not possible with some prior art approaches. A good software design would apply some sort of a reasonable sequence of alternating watchdog operations. 
     One such design may have the operating system only perform a watchdog down operation after a specific task returns successfully along with a guaranteed operating system task queue of at least 15 alternating watchdog operations per control cycle. As long as waveform 137 is high by the time the negative going pulse of waveform 120, which correlates to latch watchdog state signal 20, goes high, the watchdog circuit 10 will not cause the reset external 33 to go low. Reset external 33 is the signal that would normally be connected to the system reset line. 
     If the software wants to disable the watchdog function then it must first perform the 15 alternating watchdog operations shown in waveforms 143 and 142. Afterward the software must perform an enable/disable watchdog operation which produces the pulse shown in 141. This pulse latches the state of waveform 137 and produces waveform 127. Monitoring the state of signal 27 allows the micro-processor to verify whether the watchdog function is enabled or disabled. Once signal 27 is high, signal 45 is low, which disables the watchdog action through NAND gate 29. However, the low voltage detect circuitry is still active through NAND gate 30. This allows an application to utilize the LVD 34 portion of the embodiment without requiring the watchdog portion. 
     Enabling the watchdog is very easy simply by performing a watchdog enable/disable operation, that is producing the pulse shown in 141, prior to a 15 alternating watchdog operation sequence. As is shown in FIG. 4, enabling the watchdog does not require that the 15 operation sequence first be performed before the watchdog is enabled. Therefore, it is much easier to enable the watchdog of the present invention than to disable it which is a desirable feature. 
     For example, a lost micro-processor inadvertently writes to disable the watchdog after the alternating 15 operation sequence has occurred. There is a high probability that the lost micro-processor would write the disable command again sometime afterward especially if it is stuck in a loop. The writing of the disable command produces the pulse shown in 141. However, the next time the micro-processor writes the disable command it is almost certain that the alternating 15 operation sequence would not have taken place and the watchdog would get enabled again. Shortly afterward the reenabled watchdog will, as a result of its reenabling, cause a system reset, even though initially EMI may have caused the watchdog to disable. 
     A disadvantage of the prior art is the inability to enable/disable the watchdog while running. It might be thought that it is ludicrous to allow an operation to disable the Watchdog in normal operation because a lost micro-processor could inadvertently rewrite the enable/disable watchdog register. That thought would be correct if the methods of the prior art were used. This is why the prior art methods limit the write time to only a few cycles after start-up to reduce the possibility of an inadvertent enable/disable watchdog write. 
     In contrast, the invention drastically reduces the possibility that an inadvertent enable/disable watchdog write will disable the watchdog by requiring the 15 alternating sequence followed by a watchdog enable/disable operation before the control cycle elapses. In fact, a series of EMI pulses over a short period of time caused possibly by a nearby motor failure could potentially rewrite the prior art enable/disable watchdog register. However, the invention is practically immune to this type of EMI disturbance. 
     For example, the initial EMI disturbance could trigger a watchdog reset. Another EMI disturbance during those first cycles of the operation after the reset could potentially rewrite the prior art watchdog enable/disable register. Several consecutive EMI disturbances increase the probability of inadvertently rewriting a watchdog disable in the prior art. Once the EMI disturbances have passed the prior art system may be running with the watchdog inadvertently disabled. 
     In order for an EMI disturbance to cause the present invention to rewrite the enable/disable register, the EMI would have to first allow 15 alternating consecutive watchdog operations within the control cycle period. This would be very difficult to achieve in the presence of consecutive EMI disturbances. Hence, a controlled watchdog enable/disable such as the one described herein would have advantages over the prior art not only in reduced susceptibility as described above, but also in providing the ability to offer a controlled enable/disable watchdog feature. 
     The capability of the present invention to allow disabling of the watchdog permits its use in products not requiring watchdog functionality. This saves software development time and programming memory, yet utilizes the benefits of economy of scale for the procurement of a versatile chip that can also be used in products that do require a watchdog function as well as in products that do not require that function. Furthermore, the ability to disable the watchdog feature in specific instances of the software provides an extra level of flexibility to the software development. Some software applications, for example, those that require continuous fast down loading, may not have time to be performing watchdog operations in between the down loading. Another example is the speeding up of off-line operations which do not require a watchdog environment. 
     Waveform 134 shows the low voltage detect (LVD) signal 34. The waveform 133 shows the reset external signal 33. It should be noted that there is a period of time between the rising edge of waveform 134 and the rising edge of waveform 133. This time period is set by the programmable clock generation circuit 160 shown in FIG. 5. The LVD signal 34 is shown as waveform 185 in FIG. 5. The reset external waveform 186 of FIG. 5, which is a portion of waveform 133 of FIG. 4, rises when cycle start pulse 184 and waveform 184W rise. The circuits 10, 160, and 190, with or without the feedback resistor R1 shown in FIG. 2, provide the time delay from power-up. The time when waveform 133 pulses low indicates that a watchdog reset has occurred. 
     As will be described in more detail below, the present invention allows for a delayed reset external signal to be provided on power up without the need for the hysteresis resistor R1 and therefore is ideally suited for integrated circuit chip applications. The delay allows the entire system to first settle out before the reset external signal is applied thereto to thereby provide noise immunity. In addition, the present invention allows the length of the delay to be programed by the user and is designed so that the length of the delay can never be zero. 
     It should be noted that waveform 140, of FIG. 4, which corresponds to signal 40 tracks the status of the reset. As was described above, if status signal 40 is low, then the last reset was due to a low voltage detect. If the signal 40 is high, the last reset must have occurred due to a watchdog fail. As mentioned previously, the state of signal 40 can be read by the micro-processor. 
     FIG. 5 displays the programmable clock generation and timing circuitry 160. The crystal oscillator 161 clocks binary counter 162. The LVD signal 34 is used to reset each of the binary counters 162, 169, and 182 to an initial zero state. The connection of the LVD signal to the counters is not shown in FIG. 5. Once the LVD signal 34 and LVD waveform 185 both go high, the binary counter 162 can start to count. Programmed stored data 163 is set with the micro-processor (not shown). The programmed stored data 163 bits are reset to zero with the LVD 34 signal during power-up. 
     Stored data bits 166 from data set 163 select which binary counter output line of 164 will pass through multiplexer 167. In FIG. 5, the heavy dark line indicates a connection that carries more than one bit. While the multiple lines for those connections are not shown in FIG. 5, those skilled in the art will be able to provide the same from the description set forth herein. 
     The multiplexer output 168 is used to clock binary counter 169. The other set of stored data bits 171 in programmed stored data 163 are used as input to the logic 172 and as inputs to the logic OR function 173 which is a number of OR gates arranged to provide, as described below, a predetermined output when the bits 171 are all zero. For ease of drawing only one such OR gate 173 is shown in FIG. 5. 
     The logic 172 is used to output high lines given certain inputs 171. For example, if 171 is all zeroes, the logic 172 puts out all ones. Otherwise logic 172 outputs all zeroes. These all ones or all zeroes from logic 172 are OR&#39;d to each data bit 171 respectively at gates 173 to produce a predetermined binary number. In one embodiment for circuit 160, the logic 172 and OR functions 173 produce a 6 bit 101101, that is, a binary forty-five, when the stored data bits 171 are all zero. This type of functionality guarantees that the OR gates 173 will never have all zeroes at its output 77, even from power-up and therefore guarantees a predetermined delay as will be discussed below. The outputs 77 select the channels to multiplex in multiplexers 178. 
     The binary counter 169 has outputs 174 to multiplexers 78. A supply 170 supplies high level lines 175 to multiplexers 178. Multiplexer 178 passes, depending on the signals 177, certain of the specified binary counter output lines 174 and non-specified high level logic lines 175 through lines 180 to AND gate 179. In other words, if binary counter 169 has 6 bits to output over 174, and the signals 177 are for example, 001001, which can be thought of as a binary nine, then the least significant bit of 174 and third most significant bit of 174 will pass to AND gate 179. The other four bits passed to AND gate 179 will be provided by multiplexer 178 from the associated ones of the non-specified high level logic lines 175. 
     The output 165 of the AND gate 179 is used to reset the binary counter 169. Hence, the operation of the logic between outputs 168 and 165 functions as a programmable clock divider based on the programmed stored data 163. The binary counter 182 takes in this clock divided signal 165 and further reduces it in a binary form. The logic 183 has inputs from both 165 and binary counter 182 output signals to thereby produce clock signals 181 and 184. In FIG. 5, the waveform for the signal 181 is represented as 181W and the waveform for the cycle start signal 184 is represented as 184W. Details of the logic 183 need not be given since one skilled in the art can easily derive the same from the inputs as shown in circuit 160 and the description given herein to arrive at the waveforms 181W and 184W. 
     Standard crystal frequencies can be used to generate standard baud rates with clock dividers. Often the required ratio can first be made of dividers using factors of 2; however, additional factors, dependent on the crystal frequency, such as 5, and 9 are required as well. If for example, 5 and 9 are the only programmable additional factors of desire, the multiplexer 178, associated input logic 171, 172, 173, 177, 174, and 175, and AND gate 179 inputs 180 can all be reduced in complexity as described directly below. 
     In the case of 5, a binary 101, and 9, a binary 1001, the two least significant bits, 0 and 1 are common. Therefore, the least significant bit can be fed directly from the binary counter 169 to AND gate 179 without going through multiplexer 178. The second from least significant bit of binary counter 169 does not need to go any where. The programmed stored data 163 bits can be reduced since the two least significant bits do not need to be specified. 
     More programmed stored data bits 171 may be reduced by mapping smaller unused data patterns to represent desired data patterns for the multiplexer 178 channel select lines 177. For example, if only 5, 9, and 45, a binary 101101, will be used as dividing patterns, only two bits 171 would be necessary using the above example. The logic 172 and OR functions 173 could be designed to yield a 45 representation when bits 171 are 00, passing 1011 across 177; whereas five would have bits 171 of 01 which pass 0001 across 177, and nine would use the 171 bit pattern of 10 to pass 0010 across 177 to multiplexer 178. In the example of 5 and 9, described above, it was not necessary to have the last two bits for the multiplexer. 
     The use of a binary counter 162 to do the initial divide by a multiple of 2 helps reduce power. The programmable counter divider circuitry that surrounds counter 169 is run and reset from a much slower frequency on output 168 than if that circuitry were to exchange places with counter 162. 
     The logic 172 and OR gate 173 functions, along with the LVD signal 34 resetting the programmed stored data 163 and counters 162, 169, and 182, to provide the ability to delay the rise of the reset external waveform 186 a predetermined amount from the rise of the LVD waveform 185. This predetermined delay acts as a noise immunity feature in the output of the reset external signal 33. Even if the LVD signal oscillates continuously for a period of time, the reset external signal 33 and waveform 186 will not go high until the LVD has stopped oscillating and is in the high state for the predetermined amount of time. This predetermined amount of time will typically be on the order of several milliseconds which is well above a typical LVD oscillation period. As was described above, the predetermined amount of time is programmable and is determined by the count in the program stored data 163. As was also described above, if the bits in the programmed stored data 163 are all zero the predetermined amount of time is not zero and is fixed by the arrangement of the OR gates 173. 
     Another feature of this reset external signal 33 is that it will go low the instant that the LVD signal 34 indicates a low voltage supply. The reset external signal 33 will remain low, even if the LVD is oscillating. Once again the reset external signal 33 will not go high until the voltage supply was all right for at least the predetermined amount of time. This time delay is very desirable in systems during power-up because it gives the entire system a chance to settle and start operating from a reliable supply level. 
     It should be appreciated that while both a watchdog circuit 10 and a programmable clock generation and timing circuit 160 have both been described herein in conjunction with one another, circuit 10 may be used independent of circuit 160 and circuit 160 may be used independent of circuit 10. 
     It should further be appreciated that the time between occurrences of the cycle start pulse is the time duration of the control cycle of the system in which the present invention is used. Therefore, the time duration of the control cycle is determined either by the count in programmed stored data 163 or if the count is all zeroes then the predetermined time fixed by the arrangement of the OR gates 173. 
     It is to be understood that the description of the preferred embodiment(s) is (are) intended to be only illustrative, rather than exhaustive, of the present invention. Those of ordinary skill will be able to make certain additions, deletions, and/or modifications to the embodiment(s) of the disclosed subject matter without departing from the spirit of the invention or its scope, as defined by the appended claims.