Patent Publication Number: US-9847389-B2

Title: Semiconductor device including an active region and two layers having different stress characteristics

Description:
CROSS-REFERENCE TO RELATED APPLICATION(S) 
     The present application is a divisional of U.S. patent application Ser. No. 11/613,326, entitled “SEMICONDUCTOR DEVICE INCLUDING AN ACTIVE REGION AND TWO LAYERS HAVING DIFFERENT STRESS CHARACTERISTICS,” filed on Dec. 20, 2006, the entirety of which is herein incorporated by reference. 
    
    
     FIELD OF THE INVENTION 
     This invention relates in general to integrated circuits and more specifically to an integrated circuit with tensile and compressive layer regions. 
     DESCRIPTION OF THE RELATED ART 
     Many integrated circuits have semiconductor devices having active regions, including channel regions. Carrier mobility within the channel regions may determine the performance of such semiconductor devices. Typically, the carrier mobility within the channel regions is a function of the type of material being used to form the channel regions. Many materials used to form the channel regions respond to compressive and tensile stresses/strains. Typically, a stress layer formed using an etch-stop layer has been used to generate either compressive or tensile stress on the channel regions. Such etch-stop layers, however, have several problems. For example, conventional dual etch-stop layers may degrade performance of certain types of semiconductor devices. 
     Thus, there is a need for an integrated circuit with tensile and compressive layer regions arranged in a manner to optimize performance of certain semiconductor devices. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The present invention may be better understood, and its numerous objects, features, and advantages made apparent to those skilled in the art by referencing the accompanying drawings. 
         FIG. 1  is a view of an exemplary integrated circuit with a tensile region and a compressive region, consistent with one embodiment of the invention; 
         FIG. 2  is another view of the exemplary integrated circuit of  FIG. 1 , consistent with one embodiment of the invention; 
         FIG. 3  is a view of a portion of an exemplary integrated circuit with a tensile region and a compressive region where the tensile region and the compressive region are offset with respect to the channel region in a lateral direction, consistent with one embodiment of the invention; 
         FIG. 4  is a view of a portion of an exemplary integrated circuit with a tensile region and a compressive region where the tensile region and the compressive region are offset with respect to the channel region in a lateral direction and a transverse direction, consistent with one embodiment of the invention; 
         FIG. 5  is a view of a portion of an exemplary integrated circuit with a tensile region and a compressive region where the tensile region and the compressive region are offset with respect to the active region in a lateral direction and a transverse direction, consistent with one embodiment of the invention; 
         FIG. 6  is a view of a portion of an exemplary integrated circuit with a tensile region and a compressive region, consistent with one embodiment of the invention; and 
         FIG. 7  is another view of the portion of the exemplary integrated circuit shown in  FIG. 6 , consistent with one embodiment of the invention. 
     
    
    
     Skilled artisans appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help improve the understanding of the embodiments of the present invention. 
     DETAILED DESCRIPTION 
     The following sets forth a detailed description of a mode for carrying out the invention. The description is intended to be illustrative of the invention and should not be taken to be limiting. 
     In one aspect, an integrated circuit includes a device including an active region of the device, where the active region of the device includes a channel region having a transverse and a lateral direction. The lateral direction is the direction of electric current flow through the channel region. The transverse direction is the direction within the active region perpendicular to the direction of electric current flow in the channel region. The device further includes an isolation region adjacent to the active region in a traverse direction from the active region, where the isolation region includes a first region located in a transverse direction to the channel region. The isolation region further includes a second region located in a lateral direction from the first region and located in a transverse direction from a portion of the active region, wherein the portion of the active region is located in a lateral direction from the channel region. The first region of the isolation region is under a stress of a first type, wherein the second region of the isolative region is one of under a lesser stress of the first type or of under a stress of a second type being opposite of the first type. 
     In another aspect, an integrated circuit includes a device including an active region of the device, where the active region of the device includes a channel region having a transverse and a lateral direction. The device further includes an isolation region adjacent to the active region. The device further includes a first layer of a material, where the first layer includes a portion located over a first region of the isolative region, the first region is located in a transverse direction from the channel region of the device, and the first layer of material is not located over the active region. The active device further includes a second layer of material, the second layer including a portion located over a second region of the isolative region, the second region is located in a lateral direction from the first region of the isolative region and is located in a transverse direction from a portion of the active region, wherein the portion of the active region is located in a lateral direction from the channel region, wherein the second layer is not located over the first region of the isolative region, where the first layer of material is not located over the second region of the isolation region. 
     In yet another aspect, an integrated circuit includes a device including an active region of the device, where the active region of the device includes a channel region having a transverse and a lateral direction. The device further includes an isolation region adjacent to the active region in a traverse direction from the active region, where the isolation region includes a first region located in a transverse direction to the channel region. The isolation region further includes a second region located in a lateral direction from the first region and located in a transverse direction from a portion of the active region, wherein the portion of the active region is located in a lateral direction from the channel region. The device further includes a first layer located over the first region of the isolative region and the second region of the isolative region, the first layer is not located over the active region of the device, where the first layer is separated from the first region by a first vertical distance, the first layer is separated from the second region by a second vertical distance, the second vertical distance being a greater distance than the first vertical distance. 
       FIG. 1  is a view of an exemplary integrated circuit with a tensile region and a compressive region, consistent with one embodiment of the invention. A portion  10  of the integrated circuit may include semiconductor devices having different conductivity. For example, portion  10  of the integrated circuit may include n-type devices in active region  12  and p-type devices in active regions  18 . Further, various compressive and tensile layers may be used to achieve a desired level of stress/strain in a channel region of these semiconductor devices. For example, p-type devices may have a layer  14  of a material over at least active regions  18 . Layer  14  may be formed using a compressive etch-stop material. N-type devices may have a layer  16  of a material over at least active regions  12  corresponding to the n-type devices. Layer  16  may be formed using a tensile etch-stop material. Layers  14  and  16  can include an oxide, a nitride, an oxynitride, or a combination thereof and can be grown or deposited. The magnitude of the stress in the channels of devices located in active regions  12  and  18  is a function of the thickness and inherent stress of the overlying film and the thickness and inherent stresses of films overlying nearby active and isolation regions. One or more process parameters such as pressure, temperature, gas ratio, power density, frequency, irradiation, ion implantation, or any combination thereof, can be used to affect the stress in a film. In one embodiment, a plasma-enhanced chemical vapor deposition (“PECVD”) can be used to deposit a tensile film or a compressive film. In another embodiment, the process parameter(s) can increase or decrease the magnitude of the stress without changing type of stress (i.e., tensile or compressive). Although not described specifically, various semiconductor manufacturing techniques can be used to achieve the various layers described with reference to  FIG. 1 . An isolation region (underlying layers  14  and  16 ) contains portions  20 ,  22 ,  26 ,  28 ,  30 ,  32 ,  34 ,  36 , and  38 , which in the illustrated embodiment are overlaid with layer  16 . In another embodiment, some of the portions  20 ,  22 ,  26 ,  28 ,  30 ,  32 ,  34 ,  36 , and  38  may be overlaid with layer  16  and others may be overlaid with layer  14 . 
     A channel  19  may be formed as part of p-type devices in active region  18 . The channel may have a channel length and a channel width. The term “channel length” is intended to mean a dimension of a channel region of a transistor structure, wherein the dimension represents a minimum distance between a source region and a drain region or between source/drain regions of the transistor structure. From a top view, the channel length is typically in a direction that is substantially perpendicular to channel-source region interface, channel-drain region interface, channel-source/drain region interface, or the like. The term “channel width” is intended to mean a dimension of a channel region of a transistor structure, wherein the dimension is measured in a direction substantially perpendicular to the channel length. From a top view, the channel width typically extends from one channel region-field isolation region interface to an opposite channel region-field isolation region interface. 
       FIG. 2  is a cross-section view  40  of the exemplary integrated circuit of  FIG. 1 , consistent with one embodiment of the invention. In particular, for illustration purposes,  FIG. 2  shows a cross-section view  40  of a portion  10  of an integrated circuit, along direction  2 - 2 , as labeled in  FIG. 1 . As shown in  FIG. 2 , the portion of integrated circuit  10  may include a substrate  42  and an isolation region  44  formed over substrate  42 . Substrate  42  can include a monocrystalline semiconductor wafer, a semiconductor-on-insulator wafer, a flat panel display (e.g., a silicon layer over a glass plate), or other substrate conventionally used to form semiconductor or electronic devices. Moreover,  FIG. 2  shows a cross-section view of gate region  46  corresponding to semiconductor devices formed as part of the integrated circuit. Further, each gate region may have at least one sidewall spacer  48 .  FIG. 2  further shows a cross-section view of layer  14  and layer  16 . As shown in  FIG. 2  with respect to a direction legend indicating a lateral direction and a vertical direction, gate region  46  extends both in a lateral direction and a vertical direction. Isolation region  44  may include a first region  47  and a second region  45 . First region  47  may be overlaid with a tensile material, such that it may provide a tensile stress in a transverse direction in the channel region transverse to region  47 . Second region  45  may be overlaid with a compressive material, such that it may provide a compressive stress in a lateral direction in the channel region transverse to region  47 . As a result of the configuration shown in  FIGS. 1 and 2 , the carrier mobility enhancement due to lateral and transverse channel stress for p-type devices in active region  18  may be increased in a dual etch-stop layer integration. 
       FIG. 3  is a view of a portion  50  of an exemplary integrated circuit with a tensile region and a compressive region where the tensile region and the compressive region are offset with respect to the channel region in a lateral direction, consistent with one embodiment of the invention. P-type devices  56  (also, referred to as a bank of p-type devices) and n-type devices  58  (also, referred to as a bank of n-type devices) may be formed as part of the exemplary integrated circuit. P-type devices  56  may have channel regions ( 62 ,  64 , and  66 ) formed as part of these devices. Portion  50  of the integrated circuit may include a layer  52 , which may be compressive like layer  14  of  FIG. 1 . Portion  50  may further include a layer  54 , which may be tensile like layer  16  of  FIG. 1 . As shown in  FIG. 3 , p-type devices  56  have channel regions ( 62 ,  64 , and  66 ), which are offset from the channel regions ( 68 ,  70 , and  72 ) of n-type devices  58 . By way of example, channel region  62  is offset from channel region  68  by a distance  74  in the lateral direction. Although  FIG. 3  shows three exemplary p-type and three exemplary n-type devices in portion  50  of the integrated circuit, the integrated circuit may include many types of such devices and other types of devices. Moreover, in the illustrated embodiment  76 ,  78 , and  80  represent portions of the boundary between layer  52  and layer  54  which are closer to bank  58  than bank  56 . Similarly  82 ,  84 , and  86  represent portions of the boundary between layer  52  and layer  54  which are closer to bank  56  than bank  58 . In order to optimize device performance, the distance from boundaries  76 ,  78 , and  80  to bank  58  may be different than the distance from boundaries  82 ,  84 , and  86  to bank  56 . Similarly, the length of boundaries  76 ,  78 , and  80  may be different from the length of boundaries  82 ,  84 , and  86 . Also, although layer  52  and layer  54  are shown as having a non-straight boundary, in another embodiment they may have a straight-line boundary. In this embodiment, the extent in the transverse direction to which the gate regions associated with  62 ,  64 ,  66 ,  68 ,  70 , and  72  overlie the isolation region between bank  56  and bank  58  may be optimized, as the lift provided by the vertical height of such a gate region reduces the channel stress impact of overlying stress layers  52  or  54 . For example, in a further embodiment, a straight line boundary between layer  52  and layer  54  may be placed nearer to p-type devices  56  than n-type devices  58 , and the transverse extent to which gates associated with n-device channels  68 ,  70 , and  72  overlie the isolation region between p-type devices  56  and n-type devices  58  may be greater than the transverse extent to which gates associated with p-device channels  62 ,  64 , and  66  overlie the isolation region between p-type devices  56  and n-type devices  58 . 
       FIG. 4  is a view of a portion  90  of an exemplary integrated circuit with a tensile region and a compressive region where the tensile region and the compressive region are offset with respect to the channel region in a lateral direction and a transverse direction, consistent with one embodiment of the invention. Portion  90  of the integrated circuit may include a layer  92 , which may be tensile like layer  16  of  FIG. 1 . Portion  50  may further include a layer  94 , which may be compressive like layer  14  of  FIG. 1 . N-type devices may be present in an N-MOS region  96  underlying layer  92 . The N-MOS region  96  is an active region that has a pair of edges  402  and  404  extending in the lateral direction along opposite sides of the N-MOS region  96 , and a pair of edges  406  and  408  extending in the transverse direction along opposite sides of the N-MOS region  96 . Channel regions  442 ,  444 , and  446  lie within the N-MOS region  96 . P-type devices may be present in a P-MOS region  98  underlying layer  94 . The P-MOS region  98  is an active region that has a pair of edges  422  and  424  extending in the lateral direction along opposite sides of the P-MOS region  98 , and a pair of edges  426  and  428  extending in the transverse direction along opposite sides of the P-MOS region  98 . Channel regions  462 ,  464 , and  466  lie within the P-MOS region  98 . A boundary  100  between layers  92  and  94  may be configured, such that layer  92  extends in a transverse direction away from an active region corresponding to n-type devices  96  for a distance  102  at a distance  104  from a transverse edge of the active region corresponding to n-type devices. Further, layer  92  may extend by a distance  102  at a distance  106  from another transverse edge of the active region corresponding to the n-type devices. Therefore, the layer  92  extends in a transverse direction away from the point where the edges  406  and  402  intersect by a distance  109 , and extends away in a transverse direction from the edge  402  at a channel region of the N-MOS active region by a distance  108 . Similarly, the layer  94  extends in a transverse direction away from the point where the edges  422  and  428  intersect by a distance  105 , and extends away in a transverse direction from the edge  422  at channel region of the P-MOS channel region by a distance  108 . The distances  104  and  106  may be the same or may be different to optimize the compressive and tensile stresses created by layers  94  and  92 , respectively. In another embodiment, distance  102  may be negative, such that layer  92  extends in a transverse direction toward an active region corresponding to n-type devices. Also illustrated at  FIG. 4  are points  191 - 194 , where intermediate point  192  extends away from point  191  along boundary  100  in a lateral direction; intermediate point  193  extends away from point  192  along boundary  100  in a transverse direction; and intermediate point  194  extends away from point  193  along boundary  100  in a lateral direction to a location that is nearer the middle channel region. 
       FIG. 5  is a view of a portion  110  of an exemplary integrated circuit with a tensile region and a compressive region where the tensile region and the compressive region are offset with respect to the active region in a lateral direction and a transverse direction, consistent with one embodiment of the invention. Portion  110  of the integrated circuit may include a layer  116 , which may be compressive like layer  14  of  FIG. 1 . Portion  110  may further include a layer  114 , which may be tensile like layer  16  of  FIG. 1 . P-type devices  112  may be formed as part of portion  110  of the integrated circuit. Gate regions corresponding to p-type devices may or may not extend below layer  114 . A region occupied by layer  114  may be selected to optimize the compressive and tensile stresses created by layers  116  and  114 . By way of example, a distance  118  of a transverse edge of layer  114  from a transverse edge of an active region corresponding to p-type devices  112  may be configured appropriately, and may be either positive or negative. Similarly, a distance  120  of the other transverse edge of layer  114  from the other transverse edge of the active region corresponding to the p-type devices  112  may be selected appropriately. Likewise, a distance  122  of a lateral edge of layer  114  from a lateral edge of the active region corresponding to p-type devices  112  may be selected appropriately. Distances  118 ,  120 , and  122  may be optimized to equalize and maximize the stresses in the channels of p-type devices  112  induced by layers  114  and  116  such that all p-type devices operate at the same performance level. In particular, this optimization of stresses would result in better performance for the p-type devices located near the lateral edges of p-type devices bank  112 . 
       FIG. 6  is a view of a portion  130  of an exemplary integrated circuit with a tensile region and a compressive region, consistent with one embodiment of the invention. Portion  130  of the integrated circuit may include a layer  136 , which may be compressive like layer  14  of  FIG. 1 . Portion  130  may further include a layer  138 , which may be tensile like layer  16  of  FIG. 1 . P-type devices  132  may be formed as part of portion  130  of the integrated circuit. N-type devices  134  may be formed as part of portion  130  of the integrated circuit. Moreover, as shown in  FIG. 6 , dummy poly structures (or gate lines)  140 ,  142 ,  144 , and  146  may be formed in the boundary region between a region occupied by p-type devices and a region occupied by the n-type devices. Dummy poly structures  140 ,  142 ,  144 , and  146  may be formed under layer  138 . The dummy poly structures  140 ,  142 ,  144 , and  146  lift layer  138  away from the underlying isolation regions and minimize the degrading effect of layer  138  on the lateral channel stress of channel regions  148 , as is described below. Dummy poly structures  140 ,  142 ,  144 , and  146  may be offset from channel regions  148  of p-type devices by a selected distance. 
       FIG. 7  is a cross-section view  150  of the portion  130  of the exemplary integrated circuit shown in  FIG. 6 , consistent with one embodiment of the invention. In particular, for illustration purposes,  FIG. 7  shows a cross-section view  150  of a portion of an integrated circuit, along direction  7 - 7 , as labeled in  FIG. 6 . As shown in  FIG. 7 , the portion of integrated circuit may include a substrate  152  and an isolation region  154  formed over substrate  42 . Substrate  152  can include a monocrystalline semiconductor wafer, a semiconductor-on-insulator wafer, a flat panel display (e.g., a silicon layer over a glass plate), or other substrate conventionally used to form semiconductor or electronic devices. Moreover,  FIG. 7  shows a cross-section view of gate regions  148 , which overlay channel regions corresponding to semiconductor devices formed as part of the integrated circuit.  FIG. 7  further shows dummy poly structures  140 ,  142 ,  144 , and  146 . The presence of dummy poly structures  140 ,  142 ,  144 , and  146  provides a lift to layer  138 . In particular, layer  138  may be lifted by an offset of  156  because of the presence of dummy poly structures  140 ,  142 ,  144 , and  146 . Although  FIG. 7  shows a particular arrangement and a particular number of dummy poly structures in a region occupied by layer  138 , a different arrangement of a different number of dummy poly structures may be used, as well. 
     In the foregoing specification, the invention has been described with reference to specific embodiments. However, one of ordinary skill in the art appreciates that various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of present invention. Although not described, conventional semiconductor processing techniques can be used to form the various layers, regions, and devices described above. Moreover, the integrated circuit portions containing the devices discussed above may be applied to all devices on the integrated circuit or to only a subset of the devices. In particular, tensile and compressive stress experienced by only the end devices may be modified in the manner described above. 
     Benefits, other advantages, and solutions to problems have been described above with regard to specific embodiments. However, the benefits, advantages, solutions to problems, and any element(s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential feature or element of any or all the claims. As used herein, the terms “comprises,” “comprising,” or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.