Patent Publication Number: US-11640958-B2

Title: Packaged die and RDL with bonding structures therebetween

Description:
This application is a continuation application of U.S. patent application Ser. No. 16/118,656, entitled “Packaged Die and RDL with Bonding Structures Therebetween,” filed on Aug. 31, 2018, now U.S. Pat. No. 11,004,838, issued on May 11, 2021, which is a continuation application of U.S. patent application Ser. No. 15/131,821, entitled “Semiconductor Packages and Methods of Forming the Same,” filed on Apr. 18, 2016, now U.S. Pat. No. 10,068,887, issued on Sep. 4, 2018, which is a divisional application of U.S. patent application Ser. No. 14/222,475, entitled “Semiconductor Packages and Methods of Forming the Same,” filed on Mar. 21, 2014, now U.S. Pat. No. 9,318,452, which applications are incorporated herein by reference. 
    
    
     BACKGROUND 
     Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic equipment, as examples. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductive layers of material over a semiconductor substrate, and patterning the various material layers using lithography to form circuit components and elements thereon. 
     The semiconductor industry has experienced rapid growth due to improvements in the integration density of a variety of electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration density has come from shrinking the semiconductor process node (e.g., shrink the process node towards the sub-20 nm node). As the demand for miniaturization, higher speed and greater bandwidth, as well as lower power consumption and latency has grown recently, there has grown a need for smaller and more creative packaging techniques of semiconductor dies. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. 
         FIGS.  1 A through  1 D  illustrate cross-sectional views of intermediate steps in forming a die package in accordance with some embodiments. 
         FIGS.  2 A through  2 E  illustrate cross-sectional views of intermediate steps in forming a redistribution layer in accordance with some embodiments. 
         FIGS.  3 A through  3 D  illustrate cross-sectional views of intermediate steps in forming a semiconductor package including the die package from  FIGS.  1 A through  1 D  and the redistribution layer from  FIGS.  2 A through  2 E  in accordance with some embodiments. 
         FIGS.  4 A through  4 D  illustrate a bonding interface between the die package from  FIGS.  1 A through  1 D  and the redistribution layer from  FIGS.  2 A through  2 E  in accordance with various embodiments. 
     
    
    
     DETAILED DESCRIPTION 
     The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. 
     Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature&#39;s relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. 
     Embodiments will be described with respect to embodiments in a specific context, namely a three dimensional (3D) integrated fan-out (InFO) package-on-package (PoP) device. Other embodiments may also be applied, however, to other electrically connected components, including, but not limited to, package-on-package assemblies, die-to-die assemblies, wafer-to-wafer assemblies, die-to-substrate assemblies, in assembling packaging, in processing substrates, interposers, substrates, or the like, or mounting input components, boards, dies or other components, or for connection packaging or mounting combinations of any type of integrated circuit or electrical component. 
       FIGS.  1 A through  1 D  illustrate cross-sectional views of intermediate steps in forming a die package  100  in accordance with some embodiments. The die package  100  in  FIG.  1 A  includes dielectric layer  104  over a carrier substrate  102 , and bond pads  106  and electrical connectors  108  over the dielectric layer  104 . The carrier substrate  102  may be any suitable substrate that provides (during intermediary operations of the fabrication process) mechanical support for the layers over the carrier substrate  102 . The carrier substrate  102  may be a wafer including glass, silicon (e.g., a silicon wafer), silicon oxide, metal plate, a ceramic material, or the like. 
     The dielectric layer  104  is formed over the carrier substrate  102 . The passivation layer can be silicon nitride, silicon carbide, silicon oxide, low-k dielectrics such as carbon doped oxides, extremely low-k dielectrics such as porous carbon doped silicon dioxide, a polymer, such as an epoxy, polyimide, benzocyclobutene (BCB), polybenzoxazole (PBO), the like, or a combination thereof, although other relatively soft, often organic, dielectric materials can also be used. The dielectric layer  104  may be deposited by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), a spin-on-dielectric process, the like, or a combination thereof. 
     The bond pads  106  are formed over the dielectric layer  104 . In some embodiments, the bond pads  106  are formed by forming recesses (not shown) into the dielectric layer  104 . The recesses may be formed to allow the bond pads  106  to be embedded into the dielectric layer  104 . In other embodiments, the recesses are omitted as the bond pads  106  may be formed on a first side  104 A of the dielectric layer  104 . The bond pads  106  electrically and/or physically couple the subsequently bonded dies  110  to the subsequently bonded package  400  (see  FIG.  3 D ), and/or the electrical connectors  108 . In some embodiments, the bond pads  106  include a thin seed layer (not shown) made of copper, titanium, nickel, gold, the like, or a combination thereof. The conductive material of the bond pads  106  may be deposited over the thin seed layer. The conductive material may be formed by an electro-chemical plating process, CVD, ALD, PVD, the like, or a combination thereof. In an embodiment, the conductive material of the bond pads  106  is copper, tungsten, aluminum, silver, gold, the like, or a combination thereof. 
     In an embodiment, the bond pads  106  are underbump metallizations (UBMs) that include three layers of conductive materials, such as a layer of titanium, a layer of copper, and a layer of nickel. However, one of ordinary skill in the art will recognize that there are many suitable arrangements of materials and layers, such as an arrangement of chrome/chrome-copper alloy/copper/gold, an arrangement of titanium/titanium tungsten/copper, or an arrangement of copper/nickel/gold, that are suitable for the formation of the UBMs  106 . Any suitable materials or layers of material that may be used for the UBMs  106  are fully intended to be included within the scope of the current application. 
     The electrical connectors  108  are formed over the dielectric layer  104  and extend from the dielectric layer  104  in a direction that is substantially perpendicular to the first side  104 A of the dielectric layer  104 . The electrical connectors  108  may be stud bumps, which are formed by wire bonding on the bond pads, and cutting the bond wire with a portion of bond wire left attached to the respective bond ball. For example, in  FIG.  1 A , the electrical connectors  108  include a lower portion and an upper portion, wherein the lower portion may be a bond ball formed in the wire bonding, and the upper portion may be the remaining bond wire. The upper portion of the electrical connector  108  may have a uniform width and a uniform shape that are uniform throughout the top part, the middle part, and the bottom part of upper portion. The electrical connectors  108  are formed of non-solder metallic materials that can be bonded by a wire bonder. In some embodiments, the electrical connectors  108  are made of copper wire, gold wire, the like, or a combination thereof, and may have a composite structure including a plurality of layers. 
     In alternative embodiments, the electrical connectors  108  are formed through electrical plating. In these embodiments, the electrical connectors  108  are made of copper, aluminum, nickel, gold, silver, palladium, the like, or a combination thereof, and may have a composite structure including a plurality of layers. In these embodiments, a sacrificial layer (not shown) is formed over the carrier substrate. A plurality of openings is formed in the sacrificial layer to expose the underlying bond pads. A plating step is then performed to plate the electrical connectors  108 . After the formation of the electrical connectors  108 , the sacrificial layer is then removed. 
     The electrical connectors  108  and the bond pads  106  may be collectively referred to as a backside redistribution layer for the die package  100 . This backside redistribution layer may be used to couple another package(s) or component(s) (see package  400  in  FIG.  3 D ) to the die package  100 . 
       FIG.  1 B  illustrates bonding one or more dies  110  to the bond pads  106 . A first side of the die(s)  110  may be coupled to the bond pads  106 . The die(s)  110  may be a single die or may be more than two dies. The dies(s)  110  may include a logic die, such as a central processing unit (CPU), a graphics processing unit (GPU), the like, or a combination thereof. In some embodiments, the die(s)  110  includes a die stack (not shown) which may include both logic dies and memory dies. The die(s)  110  may include an input/output (I/O) die, such as a wide I/O die that provides a connection between the die package  100  and the subsequently attached package  400  (see  FIG.  3 D ). 
     The die(s)  110  include contact areas  112  on a second side of the die(s)  110 . In some embodiments, the contact areas  112  are similar to the bond pads  106  described above and the description is not repeated herein. In other embodiments, the contact areas  112  are vias extending from the second side of the die(s) partially into the die(s)  110  or, in some embodiments, completely through the die(s)  110 . The vias  112  may be formed by an etch process to form holes (not shown) in the die(s)  110  and the holes may be filled by a conductive material such as copper, aluminum, nickel, gold, silver, palladium, the like, or a combination thereof, and may have a composite structure including a plurality of layers. The vias  112  may also include seed layers, barrier layers, liners, the like, or a combination thereof. 
       FIG.  1 C  illustrates the encapsulation of the die(s)  110  and the electrical connectors  108 . In some embodiments, the die(s)  110  and the electrical connectors  108  are encapsulated by a molding material  114 . The molding material  114  may be molded on the die(s)  110  and the electrical connectors  108 , for example, using compression molding. In some embodiments, the molding material  114  is made of a molding compound, a polymer, an epoxy, silicon oxide filler material, the like, or a combination thereof. A curing step may be performed to cure the molding material  114 , wherein the curing may be a thermal curing, a Ultra-Violet (UV) curing, the like, or a combination thereof. 
     In some embodiments, the die(s)  110 , the contact areas  112 , and the electrical connectors  108  are buried in the molding material  114 , and after the curing of the molding material  114 , a planarization step, such as a grinding, is performed on the molding material  114  as illustrated in  FIG.  1 D . The planarization step is used to remove excess portions of the molding material  114 , which excess portions are over top surfaces of the contact areas  112  and the electrical connectors  108 . In some embodiments, surfaces  112 A of the contact areas  112  and surfaces  108 A of the electrical connectors  108  are exposed, and are level with a surface  114 A of the molding material  114 . The electrical connectors  108  may be referred to as through molding vias (TMVs), through package vias (TPVs), and/or through InFO vias (TIVs) and will be referred to as TIVs  108  hereinafter. 
       FIGS.  2 A through  2 E  illustrate cross-sectional views of intermediate steps in forming a redistribution layer  204  in accordance with some embodiments.  FIG.  2 A  illustrates a redistribution layer  204  over a carrier substrate  202 . The redistribution layer  204  is formed with a first side  204 A distal the carrier substrate  202  and a second side  204 B proximate the carrier substrate  202 . 
     The redistribution layer  204  includes more than one metal layer, namely M 1  and M N , wherein the metal layer M 1  is the metal layer immediately adjacent the carrier substrate  202 , and metal layer M N  (sometimes referred to as the top metal layer M N ) is the metal layer immediately adjacent UBMs  210  (see  FIG.  2 B ). Throughout the description, the term “metal layer” refers to the collection of the metal lines  208  in the same layer. The redistribution layer  204  further includes more than one passivation layer  206 , wherein the more than one metal layers (M 1  through M N ) are disposed in the more than one passivation layers  206 . 
     The passivation layers  206  can be silicon nitride, silicon carbide, silicon oxide, low-k dielectrics such as carbon doped oxides, extremely low-k dielectrics such as porous carbon doped silicon dioxide, a polymer, such as an epoxy, polyimide, BCB, PBO, the like, or a combination thereof, although other relatively soft, often organic, dielectric materials can also be used, and deposited by CVD, PVD, ALD, a spin-on-dielectric process, the like, or a combination thereof. In an embodiment, each passivation layer  206  is formed to a thickness from about 5 μm to about 15 μm. The passivation layers  206  may undergo a curing step to cure the passivation layers  206 , wherein the curing may be a thermal curing, an UV curing, the like, or a combination thereof. 
     The metal layers, M 1  and M N , may be formed using a single and/or a dual damascene process, a via-first process, or a metal-first process. The metal layers (M 1  and M N ) and vias may be formed of a conductive material, such as copper, aluminum, titanium, the like, or a combination thereof, with or without a barrier layer. In an embodiment, each of the metal layers M 1  through M N  has a thickness in a range from about 3 μm to about 15 μm. 
     A damascene process is the formation of a patterned layer embedded in another layer such that the top surfaces of the two layers are coplanar. A damascene process, which creates either only trenches or vias, is known as a single damascene process. A damascene process, which creates both trenches and vias at once, is known as a dual damascene process. 
     In an exemplary embodiment, the metal layers M 1  through M N  are formed using a dual damascene process. In this example, the formation of the M 1  layer may begin with the formation of an etch stop layer (not shown) on the lowermost passivation layer  206  and with the next passivation layer  206  on the etch stop layer. Once the next passivation layer  206  is deposited, portions of the next passivation layer  206  may be etched away to form recessed features, such as trenches and vias, which can be filled with conductive material to connect different regions of the redistribution layer  204  and accommodate the metal lines  208  and vias. This process may be repeated for the remaining metal layers through M N . 
     The redistribution layer  204  may be referred to as a frontside redistribution layer for the die package  100 . This frontside redistribution layer  204  may be utilized to couple the die package  100  via the connectors  212  to one or more packages, package substrates, components, the like, or a combination thereof. 
     The number of metal layers M 1  to M N  and the number of passivation layers  206  are only for illustrative purposes and are not limiting. There could be other number of layers that is more or less than the two metal layers illustrated. There may be other number of passivation layers, and other number of metal layers different from those illustrated in  FIG.  2 A . 
       FIG.  2 B  illustrates the forming of UBMs  210  over and electrically coupled to the top metal layer M N . A set of openings (not shown) may be formed through the topmost passivation layer  206  to expose surfaces of the metal lines  208  in the metal layer M N . The UBMs  210  may extend through these openings in the passivation layer  206  and also extend along a surface of passivation layer  206 . The UBMs  210  may include three layers of conductive materials, such as a layer of titanium, a layer of copper, and a layer of nickel. However, one of ordinary skill in the art will recognize that there are many suitable arrangements of materials and layers, such as an arrangement of chrome/chrome-copper alloy/copper/gold, an arrangement of titanium/titanium tungsten/copper, or an arrangement of copper/nickel/gold, that are suitable for the formation of the UBMs  210 . Any suitable materials or layers of material that may be used for the UBMs  210  are fully intended to be included within the scope of the current application. 
       FIG.  2 C  illustrates the formation of a set of conductive connectors  212  over and electrically coupled to the UBMs  210 . The conductive connectors  212  may be solder balls, metal pillars, controlled collapse chip connection (C4) bumps, micro bumps, electroless nickel-electroless palladium-immersion gold technique (ENEPIG) formed bumps, or the like. The conductive connectors  212  may include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or a combination thereof. In an embodiment in which the conductive connectors  212  are solder bumps, the conductive connectors  212  are formed by initially forming a layer of solder through such commonly used methods such as evaporation, electroplating, printing, solder transfer, ball placement, or the like. Once a layer of solder has been formed on the structure, a reflow may be performed in order to shape the material into the desired bump shapes. In another embodiment, the conductive connectors  212  are metal pillars (such as a copper pillar) formed by a sputtering, printing, electro plating, electroless plating, CVD, or the like. The metal pillars may be solder free and have substantially vertical sidewalls. In some embodiments, a metal cap layer (not shown) is formed on the top of the metal pillar connectors  212 . The metal cap layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, the like, or a combination thereof and may be formed by a plating process. 
       FIG.  2 D  illustrates flipping the redistribution layer  204  over and placing it on a dicing tape  218  and removing the carrier substrate  202 . After the carrier substrate  202  is removed, the second side  204 B of the redistribution layer  204  is exposed. As illustrated in  FIG.  2 D , a set of openings  220  are formed in at least one of the passivation layers  206  to expose portions of the metal lines  208 . The openings  220  may be formed a laser drill process, an etch process, the like, or a combination thereof. 
       FIG.  2 E  illustrates the formation of a set of bonding structures  222  in the openings  220  and electrically coupled to the exposed metal lines  208  of the redistribution layer  204 . The bonding structures  222  may include solder paste, micro bumps, solder balls, UBMs, flux, the like, or a combination thereof. The details of the bonding structures will be discussed below in  FIGS.  4 A through  4 D . 
       FIGS.  3 A through  3 D  illustrate cross-sectional views of intermediate steps in forming a semiconductor package  300  including the die package  100  from  FIGS.  1 A through  1 D  and the redistribution layer  204  from  FIGS.  2 A through  2 E  in accordance with some embodiments. 
       FIG.  3 A  illustrates the die package  100  being flipped over with the contact areas  112  and the TIVs  108  being over aligned with the bonding structures  222  of the redistribution layer  204 .  FIG.  3 B  illustrates bonding the die package  100  to the redistribution layer  204 . 
     The bonding between the die package  100  and the redistribution layer  204  may be a solder bonding or a direct metal-to-metal (such as a copper-to-copper or tin-to-tin) bonding. In an embodiment, the die package  100  is bonded to the redistribution layer  204  by a reflow process. During this reflow process, the bonding structures  222  are in contact with the contact areas  112  and the TIVs  108  to physically and electrically couple the die package  100  to the redistribution layer  204  and to form bonding joints  224  from the bonding structures  222 . In some embodiments, a bonding structure (not shown), which may be similar to the bonding structures  222 , is formed on the contact areas  112  and the TIVs  108  before the die package  100  and the redistribution layer  204  are bonded together. 
     In some embodiments, after the bonding process there may be a small gap between the die package  100  and the redistribution layer  204  caused by the standoff height of the bonding structures  224 . In other embodiments, there may be no gap between the die package  100  and the redistribution layer  204 . 
     Typically, the redistribution layer would be formed directly on the die package and the processes involved in forming the redistribution layer (e.g. passivation etching, passivation curing, metal line deposition, etc.) can cause significant warpage. However, in the disclosed embodiments, by forming the redistribution layer  204  on a carrier substrate  202 , and bonding the formed redistribution layer  204  to the die package  100 , the warpage of the package  300  can be reduced. For example, the carrier substrate  202  can be selected such that it is very rigid and will have very minimal to no warpage during the formation of the redistribution layer  204 . In addition, a carrier substrate  202  can be selected such that it has a similar coefficient of thermal expansion (CTE) to the redistribution layer  204  and, will thus, minimize the warpage from any CTE mismatch. 
       FIG.  3 C  illustrates removing the carrier substrate  102  to expose a second side  104 B of the dielectric layer  104 . After the carrier substrate  102  is removed, openings  302  are formed from the second side  104 B of the dielectric layer  104  to expose surfaces  108 B of the TIVs  108  and surfaces  106 B of the bond pads  106 . The openings  220  may be formed a laser drill process, an etch process, the like, or a combination thereof. 
       FIG.  3 D  illustrates bonding a package  400  to the package  300  with a set of connectors  408  extending through the openings  302 . The package  400  includes a substrate  402  and one or more stacked dies  410  coupled to the substrate  402 . 
     The substrate  402  may be made of a semiconductor material such as silicon, germanium, diamond, or the like. Alternatively, compound materials such as silicon germanium, silicon carbide, gallium arsenic, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenic phosphide, gallium indium phosphide, combinations of these, and the like, may also be used. Additionally, the substrate  402  may be a silicon-on-insulator (SOI) substrate. Generally, an SOI substrate includes a layer of a semiconductor material such as epitaxial silicon, germanium, silicon germanium, SOI, silicon germanium on insulator (SGOI), or combinations thereof. The substrate  402  is, in one alternative embodiment, based on an insulating core such as a fiberglass reinforced resin core. One example core material is fiberglass resin such as FR4. Alternatives for the core material include bismaleimide-triazine (BT) resin, or alternatively, other PC board materials or films. Build up films such as Ajinomoto build-up film (ABF) or other laminates may be used for substrate  402 . The substrate  402  may be referred to as a package substrate  402 . 
     The substrate  402  may include active and passive devices (not shown in  FIG.  3 D ). As one of ordinary skill in the art will recognize, a wide variety of devices such as transistors, capacitors, resistors, combinations of these, and the like may be used to generate the structural and functional requirements of the design for the semiconductor package  400 . The devices may be formed using any suitable methods. 
     The substrate  402  may also include metallization layers (not shown). The metallization layers may be formed over the active and passive devices and are designed to connect the various devices to form functional circuitry. The metallization layers may be formed of alternating layers of dielectric (e.g., low-k dielectric material) and conductive material (e.g., copper) with vias interconnecting the layers of conductive material and may be formed through any suitable process (such as deposition, damascene, dual damascene, or the like). In some embodiments, the substrate  402  is substantially free of active and passive devices. 
     The substrate  402  may have bond pads  404  on a first side the substrate  402  to couple to the stacked dies  410 , and bond pads  406  on a second side of the substrate  402 , the second side being opposite the first side of the substrate  402 , to couple to the conductive connectors  408 . The bond pads  404  and  406  may be similar to the bond pads  106  described above and the description is not repeated herein, although the bond pads  404 ,  406 , and  106  need not be the same. 
     In the illustrated embodiment, the stacked dies  410  are coupled to the substrate  402  by with contact pads  414  and wire bonds  412 , although other connections may be used, such as conductive bumps. In an embodiment, the stacked dies  410  are stacked memory dies. For example, the stacked memory dies  410  may include low-power (LP) double data rate (DDR) memory modules, such as LPDDR1, LPDDR2, LPDDR3, or the like memory modules. 
     In some embodiments, the stacked dies  410  and the wire bonds  412  may be encapsulated by a molding material  414 . The molding material  414  may be molded on the stacked dies  410  and the wire bonds  412 , for example, using compression molding. In some embodiments, the molding material  414  is a molding compound, a polymer, an epoxy, silicon oxide filler material, the like, or a combination thereof. A curing step may be performed to cure the molding material  414 , wherein the curing may be a thermal curing, a UV curing, the like, or a combination thereof. 
     In some embodiments, the stacked dies  410  and the wire bonds  412  are buried in the molding material  414 , and after the curing of the molding material  414 , a planarization step, such as a grinding, is performed to remove excess portions of the molding material  414  and provide a substantially planar surface for the package  400 . 
     After the package  400  is formed, the package  400  is bonded to package  300  by way of conductive connectors  408 , the bond pads  406 , the bond pads  106 , and the TIVs  108 . In some embodiments, the stacked memory dies  410  may be coupled to the die(s)  110  through the contact pads  414 , the wire bonds  412 , the bond pads  406  and  404 , the conductive connectors  408 , the bond pads  106 , and the TIVs  108 . 
     The conductive connectors  408  may be similar to the conductive connectors  212  described above and the description is not repeated herein, although the conductive connectors  408  and  212  need not be the same. 
     The bonding between the package  400  and the package  300  may be a solder bonding or a direct metal-to-metal (such as a copper-to-copper or tin-to-tin) bonding. In an embodiment, the package  400  is bonded to the package  300  by a reflow process. During this reflow process, the conductive connectors  408  are in contact with the bond pads  406  and  106 , and the TIVs  108  to physically and electrically couple the package  400  to the package  300 . 
     An underfill material (not shown) may be injected or otherwise formed in the space between the package  400  and the package  300  and surrounding the conductive connectors  408 . The underfill material may, for example, be a liquid epoxy, deformable gel, silicon rubber, or the like, that is dispensed between the structures, and then cured to harden. This underfill material is used, among other things, to reduce damage to and to protect the conductive connectors  408 . 
     It should be noted that the number of semiconductor dies (e.g., semiconductor die(s)  110  and  410 ), through InFO vias (e.g., TIVs  108 ), and conductive connectors (e.g. conductive connectors  212  and  408 ) shown in  FIG.  3 D  are merely an example. There may be many variations, modifications, and alternatives. For example, a person skilled in the art will recognize that the semiconductor package  500  may accommodate any number of semiconductor dies, TIVs, and conductive connectors. 
       FIGS.  4 A through  4 D  illustrate a bonding interface between the die package  100  and the redistribution layer  204  in accordance with various embodiments. The portion of package  500  that is illustrated in  FIGS.  4 A through  4 D  is the highlighted area of  FIG.  3 D  that is labeled  FIG.  4   . The bonding structures  600  (e.g.  600 A and  600 B) in  FIGS.  4 A through  4 D  are various embodiments of the bonding structure  222  as illustrated in  FIG.  3 A  before the die package  100  and the redistribution layer  204  are bonded together. 
       FIG.  4 A  illustrates the bonding structures  600  of the die package  100  and the redistribution layer  204  wherein the bonding structures  600  are micro bumps. The bonding structures  600 A are coupled to the bond pads  106  and the TIVs  108  of the die package  100 , and the bonding structures  600 B are coupled to the metal lines  208  of redistribution layer  204  in the openings  220  (see  FIG.  2 D ). In an embodiment, the bonding structures  600 A and  600 B are formed to have a height H 1  in a range from about 10 μm to about 40 μm, and a width W 2  in a range from about 5 μm to about 50 μm. The bonding structures  600 A and  600 B can be formed at a pitch P 1  in a range from about 10 μm to about 300 μm. 
     In the illustrated embodiment, both the bonding structures  600 A and  600 B are micro bumps including seed layers  602  ( 602 A and  602 B), conductive layers  604  ( 604 A and  604 B), and cap layers  606  ( 606 A and  606 B). The bonding structures  600 B coupled to the redistribution layer  204  are formed in the openings  220  (see  FIG.  2 D ), with a portion of a passivation layer  206  separating the two openings  220  illustrated in  FIG.  4 A . In an embodiment, the openings  220  are formed to have a width W 1  in a range from about 25 μm to about 150 μm. 
     The seed layers  602  may be formed by an electro-chemical plating process, CVD, ALD, PVD, the like, or a combination thereof. The seed layer  602  may be formed of titanium copper alloy, tantalum copper alloy, the like, or a combination thereof. 
     The conductive layers  604  may be formed on the seed layer  602  by an electro-chemical plating process, CVD, ALD, PVD, the like, or a combination thereof. The conductive layer  604  may be formed of copper, titanium, nickel, gold, the like, or a combination thereof to have a thickness T 1  from about 2 μm to about 10 μm. 
     The cap layers  606  may be formed on the conductive layer  604  by an electro-chemical plating process, CVD, ALD, PVD, the like, or a combination thereof. The cap layer  606  may be formed of tin, nickel, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, the like, or a combination thereof to have a thickness T 2  from about 3 μm to about 10 μm. 
     The bonding structures  600 A are bonded to the bonding structures  600 B by a reflow process. During this reflow process, at least the cap layers  606 A of the bonding structures  600 A are in contact with at least the cap layers  606 B of the bonding structures  600 B to physically and electrically couple the die package  100  to the redistribution layer  204  and to form bonding joints  224  from the bonding structures  600 A and  600 B. 
       FIG.  4 B  illustrates the bonding structures  600  of the die package  100  and the redistribution layer  204  wherein the bonding structures  600  are micro bumps with a metal paste layer  608 . The bonding structures  600 A are coupled to the bond pads  106  and the TIVs  108  of the die package  100 , and the bonding structures  600 B are coupled to the metal lines  208  of redistribution layer  204  in the openings  220  (see  FIG.  2 D ). In an embodiment, the bonding structures  600 A and  600 B are formed to have a height H 1  in a range from about 50 μm to about 120 μm, and a width W 2  in a range from about 70 μm to about 250 μm. The bonding structures  600 A and  600 B can be formed at a pitch P 1  in a range from about 140 μm to about 400 μm. 
     In the illustrated embodiment, both the bonding structures  600 A and  600 B are micro bumps including seed layers  602  ( 602 A and  602 B), conductive layers  604  ( 604 A and  604 B), cap layers  606  ( 606 A and  606 B), and metal paste layers  608  ( 608 A and  608 B). The bonding structures  600 B coupled to the redistribution layer  204  are formed in the openings  220  (see  FIG.  2 D ), with a portion of a passivation layer  206  separating the two openings  220  illustrated in  FIG.  4 B . In an embodiment, the openings  220  are formed to have a width W 1  in a range from about 90 μm to about 400 μm. 
     The seed layers  602 , the conductive layers  604 , and the cap layers  606  are similar to the description above in  FIG.  4 A  and the descriptions are not repeated herein. 
     The metal paste layers  608  may be formed on the cap layers  606  by a metal-paste printing process that is applied to the cap layers  606 . According to the locations of the cap layers  606 , a stencil may be employed to print the metal paste on top of the cap layers  606 . In some embodiments, the metal paste layers  608  are formed in openings of a patterned photo resist (not shown), which is removed after the openings are filled with metal paste. The metal paste layers  608  may be formed of a solder paste, a tin silver paste, flux, the like, or a combination thereof to have a thickness T 3  in a range from about 30 μm to about 100 μm. 
     The bonding structures  600 A are bonded to the bonding structures  600 B by a reflow process. During this reflow process, at least the metal paste layers  608 A of the bonding structures  600 A are in contact with at least the metal paste layers  608 B of the bonding structures  600 B to physically and electrically couple the die package  100  to the redistribution layer  204  and to form bonding joints  224  from the bonding structures  600 A and  600 B. 
     The bonding structures  600  including the metal paste layers  608  may improve the quality of the bonding joint  224 , but the bonding joints  224  formed from the bonding structures  600  including the metal paste layers  608  may also have an increased height and width. 
       FIG.  4 C  illustrates the bonding structures  600  of the die package  100  and the redistribution layer  204  wherein the bonding structures  600  are formed of a metal paste layer. The bonding structures  600 A are coupled to the bond pads  106  and the TIVs  108  of the die package  100 , and the bonding structures  600 B are coupled to the metal lines  208  of redistribution layer  204  in the openings  220  (see  FIG.  2 D ). In an embodiment, the bonding structures  600 A and  600 B are formed to have a height H 1  in a range from about 30 μm to about 100 μm, and a width W 2  in a range from about 70 μm to about 250 μm. The bonding structures  600 A and  600 B can be formed at a pitch P 1  in a range from about 140 μm to about 400 μm. 
     In the illustrated embodiment, both the bonding structures  600 A and  600 B are metal paste layers  612  ( 612 A and  612 B). The bonding structures  600 B coupled to the redistribution layer  204  are formed in the openings  220  (see  FIG.  2 D ), with a portion of a passivation layer  206  separating the two openings  220  illustrated in  FIG.  4 C . In an embodiment, the openings  220  are formed to have a width W 1  in a range from about 90 μm to about 400 μm. 
     The metal paste layers  612  may be formed by a metal-paste printing process that is applied to the TIVs  108 , the contact areas  112 , and/or the metal lines  208 . According to the locations of the TIVs  108 , the contact areas  112 , and/or the metal lines  208 , a stencil may be employed to print the metal paste on top of the TIVs  108 , the contact areas  112 , and/or the metal lines  208 . In some embodiments, the metal paste layers  612  are formed in openings of a patterned photo resist (not shown), which is removed after the openings are filled with metal paste. The metal paste layers  612  may be formed of a solder paste, a tin silver paste, flux, the like, or a combination thereof to have the height H 1 . 
     The bonding structures  600 A are bonded to the bonding structures  600 B by a reflow process. During this reflow process, at least the metal paste layers  612 A of the bonding structures  600 A are in contact with at least the metal paste layers  612 B of the bonding structures  600 B to physically and electrically couple the die package  100  to the redistribution layer  204  and to form bonding joints  224  from the bonding structures  600 A and  600 B. 
       FIG.  4 D  illustrates the bonding structures  600  of the die package  100  and the redistribution layer  204  wherein the bonding structures  600  are formed of solder bumps. The bonding structures  600 A are coupled to the bond pads  106  and the TIVs  108  of the die package  100  and flux  620  is formed in the openings  220  of the redistribution layer  204  (see  FIG.  2 D ). In an embodiment, the bonding structures  600 A are formed to have a height H 1  in a range from about 20 μm to about 50 μm, and a width W 2  in a range from about 40 μm to about 80 μm. The bonding structures  600 A can be formed at a pitch P 1  in a range from about 80 μm to about 160 μm. 
     In the illustrated embodiment, the bonding structures  600 A are bump structures including UBMs  630  and solder bumps  632  over the UBMs  630 . The flux layers  620  are formed in the openings  220  of the redistribution layer  204  (see  FIG.  2 D ), with a portion of a passivation layer  206  separating the two openings  220  illustrated in  FIG.  4 D . In an embodiment, the openings  220  are formed to have a width W 1  in a range from about 25 μm to about 150 μm. 
     The UBMs  630  may be similar to the UBMs  210  described above and the description is not repeated herein. The solder bumps  632  may be similar to the connectors  212  described above and the description is not repeated herein. In some embodiments, a layer of flux (not shown) may be formed on the contact areas  112  and the TIVs  108  before the solder bumps  632  are formed. The flux layers  620  are formed in the openings  220 , and, in some embodiments, the flux layers  620  substantially fill the openings  220 . 
     The bonding structures  600 A are bonded to the flux layers  620  by a reflow process. During this reflow process, at least the solder bumps  632  of the bonding structures  600 A are in contact with at least the flux layers  620  to physically and electrically couple the die package  100  to the redistribution layer  204  and to form bonding joints  224  from the bonding structures  600 A and the flux layers  620 . 
     By forming the redistribution layer on a carrier substrate, and bonding the formed redistribution layer on the die package, the warpage of the bonded package can be significantly reduced. Typically, the redistribution layer would be formed directly on the die package and the processes involved in forming the redistribution layer (e.g. passivation etching, passivation curing, metal line deposition, etc.) can cause significant warpage. However, in the disclosed embodiments, the carrier substrate for the redistribution layer can be selected such that it is very rigid and will have very minimal to no warpage during the formation of the redistribution layer. In addition, the carrier substrate for the redistribution layer can be selected such that it has a similar coefficient of thermal expansion (CTE) to the redistribution layer and, will thus, minimize any warpage from CTE mismatch. 
     An embodiment is a semiconductor package including a first package including one or more dies, and a redistribution layer coupled to the one or more dies at a first side of the first package with a first set of bonding joints. The redistribution layer including more than one metal layer disposed in more than one passivation layer, the first set of bonding joints being directly coupled to at least one of the one or more metal layers, and a first set of connectors coupled to a second side of the redistribution layer, the second side being opposite the first side. 
     Another embodiment is a semiconductor package including a die package including a first die having a first side and a second side, the second side being opposite the first side, an encapsulant surrounding the first die and having a first side substantially level with the first side of the first die and a second side substantially level with the second side of the first die, and a through package via extending through the encapsulant from the first side to the second side of the encapsulant. The semiconductor package further includes a redistribution layer bonded to the first side of the first die and the through package via with a set of bonding joints, the redistribution layer comprising a plurality of metal layers disposed in a plurality of passivation layers, each of the set of bonding joints being directly coupled to a first metal layer of the plurality of metal layers. 
     A further embodiment is a method including forming a first die package over a first carrier substrate, the first die package comprising a first die and a first electrical connector, forming redistribution layer over a second carrier substrate, the redistribution layer including one or more metal layers disposed in one or more passivation layers, and removing the second carrier substrate from the redistribution layer to expose a first passivation layer of the one or more passivation layers. The method further includes forming openings in the first passivation layer to expose portions of a first metal layer of the one or more metal layers, forming a first set of bonding structures in the openings in the first passivation layer, the first set of bonding structures being coupled to the first metal layer, and bonding the redistribution layer to the first die package using the first set of bonding structures to form a first set of bonding joints, at least one of the first set of bonding joints being bonded to the first die of the first die package and at least another one of the first set of bonding joints being bonded to the first electrical connector. 
     In yet another embodiment, a method is provided. The method includes forming a first die package over a first carrier substrate, the first die package including a first die and a first electrical connector, forming redistribution layer over a second carrier substrate, the redistribution layer including one or more metal layers disposed in one or more passivation layers, and removing the second carrier substrate from the redistribution layer to expose a first passivation layer of the one or more passivation layers. The method further includes forming openings in the first passivation layer to expose portions of a first metal layer of the one or more metal layers, and forming a first set of bonding structures in the openings in the first passivation layer, the first set of bonding structures being coupled to the first metal layer. The redistribution layer is bonded to the first die package using the first set of bonding structures to form a first set of bonding joints, at least one of the first set of bonding joints being bonded to the first die of the first die package and at least another one of the first set of bonding joints being bonded to the first electrical connector. 
     In yet still another embodiment, a method is provided. The method includes forming redistribution layer over a first carrier substrate, the redistribution layer including one or more metal layers disposed in one or more passivation layers, and after forming the redistribution layer, attaching the redistribution layer to a second carrier substrate, the redistribution layer being interposed between the first carrier substrate and the second carrier substrate. The first carrier substrate is removed to expose an exposed surface of the redistribution layer, and the exposed surface of the redistribution layer is bonded to a semiconductor structure. 
     In yet still another embodiment, a method is provided. The method includes forming a first passivation layer over a first carrier substrate, forming redistribution layer over the first passivation layer, the redistribution layer including one or more metal layers disposed in one or more second passivation layers, and attaching the redistribution layer to a second carrier substrate. The method further includes removing the first carrier substrate from the first passivation layer, forming openings in the first passivation layer to expose portions of a first metal layer of the one or more metal layers, and forming first conductive structures in the openings in the first passivation layer, the first conductive structures being electrically coupled to the first metal layer. The redistribution layer is bonded to a first die package. 
     In yet still another embodiment, a semiconductor package includes a die comprising a contact pad, and a redistribution structure comprising a redistribution line and a passivation layer. A first portion of the redistribution line extends through the passivation layer. The semiconductor package further includes a first bonding joint coupled to the first portion of the redistribution line and the contact pad. The first bonding joint is in physical contact with a first surface of the passivation layer. An entirety of the first bonding joint is interposed between the first surface of the passivation layer and the contact pad. 
     In yet still another embodiment, a semiconductor package includes a first package comprising one or more dies, and a redistribution structure coupled to the first package by a first bonding joint extending between the redistribution structure and the first package. The redistribution structure includes a redistribution line and a passivation layer. The passivation layer is interposed between the redistribution line and the first package. The first bonding joint includes a first conductive layer in physical contact with the redistribution line and the passivation layer, a second conductive layer in physical contact with the one or more dies, and a solder joint interposed between the first conductive layer and the second conductive layer. A portion of the redistribution line extends into the first conductive layer. 
     In yet still another embodiment, a semiconductor package includes a die comprising a contact pad, a first bonding structure coupled to the contact pad, and a redistribution structure comprising a first redistribution line and a passivation layer. A first portion of the first redistribution line extends through the passivation layer. The first bonding structure includes a first seed layer in physical contact with the contact pad, a first conductive layer in physical contact with the first seed layer, and a first cap layer in physical contact with the first conductive layer. The semiconductor package further includes a second bonding structure coupled to the first portion of the first redistribution line and the first bonding structure. The second bonding structure includes a second seed layer in physical contact with the first portion of the first redistribution line and the passivation layer, a second conductive layer in physical contact with the second seed layer, and a second cap layer in physical contact with the second conductive layer and coupled to the first cap layer. The first portion of the first redistribution line extends into the second seed layer. The first portion of the first redistribution line is spaced apart from the second conductive layer. 
     The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.