Patent Publication Number: US-11037504-B2

Title: Pixel array substrate

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application claims the priority benefit of Taiwan patent application serial no. 108140713, filed on Nov. 8, 2019. The entirety of the above-mentioned patent application is hereby incorporated by reference here and made a part of this specification. 
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The invention relates to a pixel array substrate, and in particular, to a pixel array substrate including sensing pixels. 
     2. Description of Related Art 
     Designs of a high screen-to-body ratio and a full screen have been mainstreams of specifications of small and medium-sized panels. To achieve the high screen-to-body ratio and the full screen, a plurality of sensing pixels used for fingerprint recognition may be integrated into a pixel array substrate of a display panel, to form an in-cell fingerprint panel. The in-cell fingerprint panel has a full-screen (which may also be referred to as non-fixed point) fingerprint recognition function, which may support various applications, and can improve user experience, and increase added value of the display panel. In the in-cell fingerprint panel, sensing signals of the plurality of sensing pixels need to be transmitted to an external processing circuit by using a read-out circuit. However, the read-out circuit needs to occupy an outer lead bonding (OLB) region of the display panel, adversely affecting a screen-to-body ratio of the display panel. 
     SUMMARY OF THE INVENTION 
     The invention provides a display device with good performance. 
     A pixel array substrate in the invention includes a substrate, a plurality of display pixels, a plurality of sensing pixels, and a read-out circuit. The substrate includes a first region and a second region. The second region is located between the first region and an edge of the substrate. The plurality of display pixels are disposed on the first region and the second region of the substrate. The plurality of sensing pixels are disposed on the first region of the substrate. The read-out circuit is electrically connected to the plurality of sensing pixels. A portion of the read-out circuit is disposed on the second region of the substrate, and the portion of the read-out circuit is located between two of the plurality of display pixels. 
     In an embodiment of the invention, each display pixel includes a data line, a scanning line, a transistor, and a pixel electrode. The transistor of the display pixel is electrically connected to the data line and the scanning line. The pixel electrode is electrically connected to the transistor of the display pixel. A light shielding pattern shields the scanning line of one of the two display pixels and the portion of the read-out circuit. 
     In an embodiment of the invention, the substrate further includes a third region located between the second region and the edge of the substrate. The pixel array substrate further includes a plurality of sensing fan-out lines electrically connected to the read-out circuit, and disposed on the third region of the substrate. At least one display pixel is located between the portion of the read-out circuit and the plurality of sensing fan-out lines. 
     In an embodiment of the invention, the portion of the read-out circuit includes at least one portion of a reset circuit. 
     In an embodiment of the invention, the portion of the read-out circuit includes at least one portion of an active load circuit. 
     In an embodiment of the invention, the portion of the read-out circuit includes at least one portion of a multiplexer. 
     In an embodiment of the invention, the pixel array substrate further includes a plurality of read-out lines electrically connected to the plurality of sensing pixels. The multiplexer includes a plurality of selection transistors. A plurality of first ends of the plurality of selection transistors of the multiplexer are electrically connected to the plurality of read-out lines. The portion of the read-out circuit includes the plurality of selection transistors of the multiplexer. 
     In an embodiment of the invention, the pixel array substrate further includes a plurality of read-out lines electrically connected to the plurality of sensing pixels. The multiplexer includes a plurality of selection transistors and a plurality of bus lines. A plurality of first ends of the plurality of selection transistors of the multiplexer are electrically connected to the plurality of read-out lines, and a plurality of second ends of the plurality of selection transistors of the multiplexer are electrically connected to the plurality of bus lines. The portion of the read-out circuit includes the plurality of bus lines. 
     In an embodiment of the invention, the pixel array substrate further includes a plurality of read-out lines electrically connected to the plurality of sensing pixels. The multiplexer includes a plurality of selection transistors and a plurality of bus lines. A plurality of first ends of the plurality of selection transistors of the multiplexer are electrically connected to the plurality of read-out lines respectively, and a plurality of second ends of the plurality of selection transistors of the multiplexer are electrically connected to the plurality of bus lines. The portion of the read-out circuit includes at least one of the plurality of bus lines and the plurality of selection transistors of the multiplexer. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a schematic top view of a display device  10  according to an embodiment of the invention. 
         FIG. 2  is a schematic partial top view of a substrate  110  of a pixel array substrate  100  according to an embodiment of the invention. 
         FIG. 3  shows at least one display pixel DPX and one sensing pixel FPX on one first sub-region  112   a  of a first region  112  of a substrate  110  according to an embodiment of the invention.  FIG. 3  corresponds to one first sub-region  112   a  in  FIG. 2 . 
         FIG. 4  shows a plurality of display pixels DPX on two adjacent second sub-regions  114   a  of a second region  114  of a substrate  110  and a portion of a read-out circuit  130  (for example, a reset circuit  131 ) on one of the two second sub-regions  114   a  according to an embodiment of the invention. 
         FIG. 5  is a schematic equivalent circuit diagram of a pixel array substrate  100  according to an embodiment of the invention. 
         FIG. 6  shows a plurality of display pixels DPX on two adjacent second sub-regions  114   a  of a second region  114  of a substrate  110  and a portion of a read-out circuit  130  (for example, an active load circuit  132 ) on one of the two second sub-regions  114   a  according to an embodiment of the invention. 
         FIG. 7  shows a plurality of display pixels DPX on two adjacent second sub-regions  114   a  of a second region  114  of a substrate  110  and a portion of a read-out circuit  130  (for example, a portion of a multiplexer  133 ) on one of the two second sub-regions  114   a  according to an embodiment of the invention. 
         FIG. 8  shows a plurality of display pixels DPX on two adjacent second sub-regions  114   a  of a second region  114  of a substrate  110  and a portion of a read-out circuit  130  (for example, a portion of a multiplexer  133 ) on one of the two second sub-regions  114   a  according to an embodiment of the invention. 
     
    
    
     DESCRIPTION OF THE EMBODIMENTS 
     Exemplary embodiments of the invention are described in detail, and examples of the exemplary embodiments are shown in the accompanying drawings. Whenever possible, the same component symbols are used in the drawings and descriptions to indicate the same or similar parts. 
     It should be understood that when a component such as a layer, film, region or substrate is referred to as being “on” or “connected” to another component, it may be directly on or connected to the another component, or an intermediate component may exist. In contrast, when a component is referred to as being “directly on” or “directly connected to” another component, there is no intermediate component. As used herein, “connection” may refer to a physical and/or an electrical connection. Further, “electrical connection” or “coupling” may mean that there is another component between two components. 
     As used herein, “about”, “approximately”, or “substantially” is inclusive of the stated value and means within an acceptable deviation range of the particular value as determined by one of ordinary skills in the art, considering the discussed measurement and a particular quantity of errors associated with the measurement (i.e., the limitations of the measurement system). For example, “about” may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the stated value. Further, as used herein, “about”, “approximately”, or “substantially” may be used to select a more acceptable deviation range or standard deviation depending on optical properties, etch properties, or other properties, rather than applying one standard deviation to all properties. 
     Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skills in the art to which the present invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having meanings consistent with their meanings in the context of the related art and the present invention and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. 
       FIG. 1  is a schematic top view of a display device  10  according to an embodiment of the invention. 
       FIG. 1  shows a substrate  110 , sensing fan-out lines  120 , display fan-out lines  140 , an external processing circuit  210  electrically connected to the sensing fan-out lines  120 , and an external processing circuit  220  electrically connected to the display fan-out lines  140 , of the display device  10 . Other components of the display device  10  are omitted. In addition, the external processing circuits  210  and  220  may also be integrated into a single component. 
       FIG. 2  is a schematic partial top view of a substrate  110  of a pixel array substrate  100  according to an embodiment of the invention.  FIG. 2  corresponds to a portion R in  FIG. 1 . 
       FIG. 3  shows at least one display pixel DPX and one sensing pixel FPX on one first sub-region  112   a  of a first region  112  of a substrate  110  according to an embodiment of the invention.  FIG. 3  corresponds to one first sub-region  112   a  in  FIG. 2 . 
       FIG. 4  shows a plurality of display pixels DPX on two adjacent second sub-regions  114   a  of a second region  114  of a substrate  110  and a portion (for example, a reset circuit  131 ) of a read-out circuit  130  on one of the two second sub-regions  114   a  according to an embodiment of the invention.  FIG. 4  corresponds to a portion r in  FIG. 2 . 
       FIG. 5  is a schematic equivalent circuit diagram of a pixel array substrate  100  according to an embodiment of the invention. 
     It needs to be noted that, the equivalent circuit diagram in  FIG. 5  is used to describe an electrical connection relationship between components of the pixel array substrate  100 . Positions of the components of the pixel array substrate  100  shown in  FIG. 5  do not represent actual disposition positions of the components. For the disposition positions of the components of the pixel array substrate  100 , refer to other figures. 
     Referring to  FIG. 1 , a display device  10  includes a pixel array substrate  100 , an opposite substrate (not shown) relative to the pixel array substrate  100 , and a display medium (not shown) disposed between the pixel array substrate  100  and the opposite substrate. 
     For example, in the present embodiment, the display medium may be a liquid crystal. However, the invention is not limited thereto. According to other embodiments, the display medium may alternatively be an organic light-emitting diode (OLED), a micro LED, a mini LED, a quantum dot LED, or other types of display mediums. 
     Referring to  FIG. 1 , the pixel array substrate  100  includes a substrate  110 . The substrate  110  includes a first region  112  and a second region  114 . The second region  114  is located between the first region  112  and an edge  110   a  of the substrate  110 . The substrate  110  is mainly a component configured to carry the pixel array substrate  100 . In the present embodiment, a material of the substrate  110  may be glass, quartz, organic polymer, or an opaque/reflective material (for example, wafer, ceramics, or other applicable materials), or other applicable materials. 
     Referring to  FIG. 1  and  FIG. 2 , in the present embodiment, the first region  112  includes a plurality of first sub-regions  112   a  arranged in an array. Each first sub-region  112   a  includes at least one display pixel region  112   a - 1  and a sensing pixel region  112   a - 2 . Referring to  FIG. 2  and  FIG. 3 , the at least one display pixel region  112   a - 1  of each first sub-region  112   a  is configured to set at least one display pixel DPX. The sensing pixel region  112   a - 2  of each first sub-region  112   a  is configured to set a sensing pixel FPX. Referring to  FIG. 1 , in other words, the first region  112  is a main display and sensing region of the display device  10 . 
     Referring to  FIG. 1  and  FIG. 2 , in the present embodiment, the second region  114  includes a plurality of second sub-regions  114   a  arranged in an array. Each second sub-region  114   a  includes at least one display pixel region  114   a - 1  and a quasi-sensing pixel region  114   a - 2 . Referring to  FIG. 2  and  FIG. 4 , the at least one display pixel region  114   a - 1  of each second sub-region  114   a  is configured to set at least one display pixel DPX. The quasi-sensing pixel region  114   a - 2  of each second sub-region  114   a  is configured to set a portion of a read-out circuit  130  instead of a sensing pixel FPX. Referring to  FIG. 1 , in other words, the second region  114  is a display and quasi-sensing region of the display device  10 . 
     Referring to  FIG. 1 , in the present embodiment, the substrate  110  of the pixel array substrate  100  further includes a third region  116 . The third region  116  is located between the second region  114  and the edge  110   a  of the substrate  110 . In the present embodiment, the pixel array substrate  100  further includes a plurality of sensing fan-out lines  120 . The plurality of sensing fan-out lines  120  are electrically connected between the read-out circuit  130  (shown in  FIG. 5 ) and a plurality of sensing pads (not shown), and the plurality of sensing pads are configured to bond with an external processing circuit  210 . The pixel array substrate  100  further includes a plurality of display fan-out lines  140 . The plurality of display fan-out lines  140  are electrically connected between a plurality of display pixels DPX and a plurality of display pads (not shown), and the plurality of display pads are configured to bond with an external processing circuit  220 . The plurality of sensing fan-out lines  120 , the plurality of sensing pads (not shown) configured to bond with the external processing circuit  210 , the plurality of display fan-out lines  140 , and the plurality of display pads (not shown) configured to bond with the external processing circuit  220  are disposed on the third region  116  of the substrate  110 . In other words, the third region  116  of the substrate  110  is an OLB region of the display device  10 . 
     Referring to  FIG. 2 ,  FIG. 3 , and  FIG. 4 , a plurality of display pixels DPX are disposed on the first region  112  and the second region  114  of the substrate  110 . Specifically, in the present embodiment, the plurality of display pixels DPX are disposed on a plurality of display pixel regions  112   a - 1  of the plurality of first sub-regions  112   a  of the display and sensing region (that is, the first region  112 ) and a plurality of display pixel regions  114   a - 1  of the plurality of second sub-regions  114   a  of the display and quasi-sensing region (that is, the second region  114 ). 
     Referring to  FIG. 3 , for example, in the present embodiment, each display pixel DPX may include a data line DL, a scanning line SL, a transistor T, and a pixel electrode PE. A first end Ta and a control end Tc of the transistor T of the display pixel DPX are electrically connected to the data line DL and the scanning line SL respectively. The pixel electrode PE is electrically connected to a second end Tb of the transistor T of the display pixel DPX. 
     Referring to  FIG. 2  and  FIG. 3 , a plurality of sensing pixels FPX are disposed on the first region  112  of the substrate  110 . Specifically, in the present embodiment, the plurality of sensing pixels FPX are disposed on a plurality of sensing pixel regions  112   a - 2  of the plurality of first sub-regions  112   a  of the display and sensing region (that is, the first region  112 ), and are not disposed on a plurality of quasi-sensing pixel regions  114   a - 2  of the plurality of second sub-regions  114   a  of the display and quasi-sensing region (that is, the second region  114 ). The plurality of sensing pixels FPX are disposed on most of the area of the display device  10 , and are used for light sensing. For example, in the present embodiment, the plurality of sensing pixels FPX may be used for receiving a light beam reflected by a biological feature (for example, but not limited to, a fingerprint), thereby achieving almost full-screen biometric recognition. 
     Referring to  FIG. 3  and  FIG. 5 , for example, in the present embodiment, each sensing pixel FPX may include a photosensitive element PD, a first transistor T 1 , a second transistor T 2 , a reference voltage line L VSS  configured to provide a reference voltage VSS, a sensing scanning line L SR  configured to provide a read voltage SR, a power supply line L VDD  configured to provide a power supply voltage VDD, and a read-out line L OUT  configured to receive a sensing output signal. A first end T 1   a  of the first transistor T 1  is electrically connected to the reference voltage line L VSS , a control end T 1   c  of the first transistor T 1  is electrically connected to the sensing scanning line L SR , and a second end T 1   b  of the first transistor T 1  is electrically connected to a control end T 2   c  of the second transistor T 2  and the photosensitive element PD. A first end T 2   a  of the second transistor T 2  is electrically connected to the power supply line L VDD , and a second end T 2   b  of the second transistor T 2  is electrically connected to the read-out line L OUT . However, the invention is not limited thereto. In other embodiments, the sensing pixels FPX may alternatively be other types of circuits. In addition, in the present embodiment, the photosensitive element PD may be a photodiode including silicon-rich oxide (SRO). However, the invention is not limited thereto. 
     Referring to  FIG. 5 , the pixel array substrate  100  further includes a read-out circuit  130  electrically connected to a plurality of read-out lines L OUT  of the plurality of sensing pixels FPX. For example, in the present embodiment, the read-out circuit  130  may selectively include a reset circuit  131 , an active load circuit  132 , and a multiplexer  133 . However, the invention is not limited thereto. In addition, it needs to be noted that, a type of the read-out circuit  130  shown in  FIG. 5  is merely used to describe the invention rather than limit the invention. In other embodiments, the read-out circuit  130  may alternatively be of other types. 
     Referring to  FIG. 2 ,  FIG. 4 , and  FIG. 5 , it should be noted that, a portion of the read-out circuit  130  is disposed on the second region  114  of the substrate  110 , and the portion of the read-out circuit  130  is located between two display pixels DPX. In other words, the portion of the read-out circuit  130  is disposed on at least one quasi-sensing pixel region  114   a - 2 . 
     Referring to  FIG. 4 , in the present embodiment, the plurality of display pixels DPX are arranged as a plurality of display pixel rows R DPX . The portion of the read-out circuit  130  is located between two adjacent display pixel rows R DPX . A light shielding pattern BM shields the scanning line SL of the display pixel DPX of one of the two display pixel rows R DPX  and the portion of the read-out circuit  130 . In other words, in the present embodiment, the portion of the read-out circuit  130  may be disposed below the light shielding pattern BM. The light shielding pattern BM is, for example, a portion, which overlaps the scanning line SL, of a black matrix. However, the invention is not limited thereto. The light shielding pattern BM may be disposed on the substrate  110  of the pixel array substrate  100 , or may be disposed on the opposite substrate. 
     Referring to  FIG. 1 ,  FIG. 2 , and  FIG. 4 , in the present embodiment, at least one display pixel DPX (for example, lower three display pixels DPX in  FIG. 4 ) is located between the portion of the read-out circuit  130  (for example, but not limited to, the reset circuit  131  in  FIG. 4 ) and the plurality of sensing fan-out lines  120  (shown in  FIG. 1 ). 
     How the portion of the read-out circuit  130  may be disposed on the quasi-sensing pixel regions  114   a - 2  is described by way of example with reference to  FIG. 4 ,  FIG. 6 ,  FIG. 7 , and  FIG. 8 . 
     Referring to  FIG. 2 ,  FIG. 4 , and  FIG. 5 , in an embodiment, at least one portion of the reset circuit  131  of the read-out circuit  130  may be disposed on the at least one quasi-sensing pixel region  114   a - 2 , and located between the plurality of display pixels DPX. For example, the reset circuit  131  may include at least one reset transistor T 3 , a reset signal line L RST  configured to provide a reset signal RST, and a reference voltage line L VSS  configured to provide a reference voltage VSS. A first end T 3   a  of each reset transistor T 3  is electrically connected to the reference voltage line L VSS , a control end T 3   c  of each reset transistor T 3  is electrically connected to the reset signal line L RST , and a second end T 3   b  of each reset transistor T 3  is electrically connected to a corresponding read-out line L OUT . Referring to  FIG. 4 , the at least one reset transistor T 3 , the reset signal line L RST , and the reference voltage line L VSS  of the read-out circuit  130  may be disposed on one of the quasi-sensing pixel regions  114   a - 2 . However, the invention is not limited thereto. 
     In addition, it needs to be noted that, a quantity of reset transistors T 3  of the reset circuit  131  that are electrically connected to a single read-out line L OUT  is not specially limited. The quantity of the reset transistors T 3  of the reset circuit  131  that are electrically connected to the single read-out line L OUT  may be determined according to charging and discharging capacity requirements on the reset transistors T 3  and a component size design space. 
       FIG. 6  shows a plurality of display pixels DPX on two adjacent second sub-regions  114   a  of a second region  114  of a substrate  110  and a portion of a read-out circuit  130  (for example, an active load circuit  132 ) on one of the two second sub-regions  114   a  according to an embodiment of the invention.  FIG. 5  corresponds to a portion r in  FIG. 2 . 
     Referring to  FIG. 2 ,  FIG. 5 , and  FIG. 6 , in an embodiment, at least one portion of the active load circuit  132  of the read-out circuit  130  may be disposed on the at least one quasi-sensing pixel region  114   a - 2 , and located between the plurality of display pixels DPX. For example, in the present embodiment, the active load circuit  132  may include a load transistor T 4  configured to form a resistance, a bias signal line L VB  configured to provide a bias voltage VB, and a reference voltage line L VSS  configured to provide a reference voltage VSS. A first end T 4   a  of each load transistor T 4  is electrically connected to the reference voltage line L VSS , a control end T 4   c  of each load transistor T 4  is electrically connected to the bias signal line L VB , and a second end T 4   b  of each load transistor T 4  is electrically connected to a corresponding read-out line L OUT . Referring to  FIG. 6 , the load transistor T 4 , the bias voltage signal line L VB , and the reference voltage line L VSS  of the read-out circuit  130  may be disposed on one quasi-sensing pixel region  114   a - 2 . However, the invention is not limited thereto. 
       FIG. 7  shows a plurality of display pixels DPX on two adjacent second sub-regions  114   a  of a second region  114  of a substrate  110  and a portion of a read-out circuit  130  (for example, a portion of a multiplexer  133 ) on one of the two second sub-regions  114   a  according to an embodiment of the invention.  FIG. 7  corresponds to a portion r in  FIG. 2 . 
     Referring to  FIG. 2 ,  FIG. 5 , and  FIG. 7 , in an embodiment, at least one portion of the multiplexer  133  of the read-out circuit  130  may be disposed on the at least one quasi-sensing pixel region  114   a - 2 , and located between the plurality of display pixels DPX. The multiplexer  133  may also be referred to as a zone-switch circuit. Referring to  FIG. 5  and  FIG. 7 , for example, in the present embodiment, the multiplexer  133  includes n selection transistor groups G, n selection lines L ZSW  configured to provide a multiplex signal ZSW, and m bus lines LS. The n selection transistor groups G are electrically connected to the n selection lines L ZSW  respectively. A plurality of control ends T 5   c  of a plurality of selection transistors T 5  of each selection transistor group G are electrically connected to a same selection line L ZSW , a plurality of first ends T 5   a  of the plurality of selection transistors T 5  of each selection transistor group G are electrically connected to a plurality of read-out lines L OUT , and a plurality of second ends T 5   b  of the plurality of selection transistors T 5  of each selection transistor group G are electrically connected to the first to the m th  bus lines L S . n and m are positive integers greater than or equal to 2. 
     Referring to  FIG. 5  and  FIG. 7 , in an embodiment, the plurality of selection transistors T 5  of one selection transistor group G, one selection line L ZSW , the first bus line L S1 , and the second bus line L S2  of the multiplexer  133  may be disposed on one quasi-sensing pixel region  114   a - 2 , and located between the plurality of display pixels DPX. However, the invention is not limited thereto. 
     In addition, it needs to be noted that, a quantity of selection transistors T 5  of the multiplexer  133  that are electrically connected to a single read-out line L OUT  is not specially limited. The quantity of the selection transistors T 5  of the multiplexer  133  that are electrically connected to the single read-out line L OUT  may be determined according to charging and discharging capacity requirements of on the selection transistors T 5  and a component size design space. 
       FIG. 8  shows a plurality of display pixels DPX on two adjacent second sub-regions  114   a  of a second region  114  of a substrate  110  and a portion of a read-out circuit  130  (for example, a portion of a multiplexer  133 ) on one of the two second sub-regions  114   a  according to an embodiment of the invention.  FIG. 8  corresponds to a portion r′ in  FIG. 2 . 
     Referring to  FIG. 2 ,  FIG. 5 , and  FIG. 8 , in an embodiment, at least one portion of the multiplexer  133  of the read-out circuit  130  may be disposed on the at least one quasi-sensing pixel region  114   a - 2 , and located between the plurality of display pixels DPX. Referring to  FIG. 5  and  FIG. 8 , for example, in the present embodiment, the (k−1) th  bus line L Sk−1 , the k th  bus line L Sk , and the (k+1) th  bus line L Sk+1  of the multiplexer  133  may be disposed on one quasi-sensing pixel region  114   a - 2 , and located between the plurality of display pixels DPX. k is a positive integer greater than or equal to 2. 
     It should be noted that, in the foregoing embodiments, the portion of the read-out circuit  130  is disposed on the second region  114  of the substrate  110 , and the portion of the read-out circuit  130  is located between the plurality of display pixels DPX. That is, at least one portion of the read-out circuit  130  is disposed on the at least one quasi-sensing pixel region  114   a - 2  of the display and quasi-sensing region (that is, the second sub-region  114   a ). Therefore, the at least one portion of the read-out circuit  130  does not need to be disposed on the third region  116  (that is, the OLB region) of the substrate  110 , so that a width W (labeled in  FIG. 1 ) of the third region  116  of the substrate  110  is reduced. Therefore, the display device  10  with a high screen-body ratio is achieved.