Patent Publication Number: US-2022238382-A1

Title: Semiconductor structure and method for forming the same

Description:
BACKGROUND 
     The electronics industry has experienced an ever increasing demand for smaller and faster electronic devices that are able to support greater numbers of increasingly complex and sophisticated functions. Accordingly, there is a continuing trend in the semiconductor industry to manufacture low-cost, high-performance, low-power integrated circuits (ICs). Thus far these goals have been achieved in large part by scaling down semiconductor IC dimensions (e.g., minimum feature size) and thereby improving production efficiency and reducing associated costs. However, such downscaling has also introduced increased complexity to the semiconductor manufacturing process. Thus, the realization of continued advances in semiconductor ICs and devices required similar advances in semiconductor manufacturing processes and technology. 
     As technology nodes achieve progressively smaller scales, in some IC designs, researchers have hoped to replace a typical polysilicon gate with a metal gate to improve device performance by decreasing feature sizes. One approach of forming the metal gate is called a “gate-last” approach, sometimes referred to as replacement polysilicon gate (RPG) approach. In the RPG approach, the metal gate is fabricated last, which allows for a reduced number of subsequent operations. 
     Further, as the dimensions of a transistor decrease, the thickness of the gate dielectric layer may be reduced to maintain performance with a decreased gate length. In order to reduce gate leakage, a high dielectric constant (high-k or HK) gate dielectric layer is used to provide a thickness as effective as that provided by a typical gate oxide used in larger technology nodes. A high-k metal gate (HKMG) approach including the metal gate electrode and the high-k gate dielectric layer is therefore recognized. However, the HKMG approach is a complicated approach, and many issues arise. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It should be noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. 
         FIG. 1  is a flowchart representing a method for forming a semiconductor structure according to aspects of the present disclosure. 
         FIG. 2  shows perspective views illustrating portions of a semiconductor structure at a fabrication stage according to aspects of the present disclosure in one or more embodiments. 
         FIG. 3  shows cross-sectional views taken along lines X 1 -X 1 ′ and X 2 -X 2 ′ of  FIG. 2 , respectively. 
         FIGS. 4 to 11  are schematic drawings illustrating the semiconductor structure at various fabrication stages subsequent the stages shown in to  FIG. 3  according to aspects of the present disclosure in one or more embodiments. 
         FIG. 12  shows perspective views illustrating portions of a semiconductor structure at a fabrication stage according to aspects of the present disclosure in one or more embodiments. 
         FIG. 13  shows cross-sectional views taken along lines X 1 -X 1 ′, X 2 -X 2 ′ and X 3 -X 3 ′ of  FIG. 12 , respectively. 
         FIGS. 14 to 21  are schematic drawings illustrating the semiconductor structure at various fabrication stages subsequent to the stage shown in  FIG. 13  according to aspects of the present disclosure in one or more embodiments. 
     
    
    
     DETAILED DESCRIPTION 
     The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of elements and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. 
     Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper,” “on” and the like, may be used herein for ease of description to describe one element or feature&#39;s relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. 
     As used herein, the terms such as “first,” “second” and “third” describe various elements, components, regions, layers and/or sections, but these elements, components, regions, layers and/or sections should not be limited by these terms. These terms may be only used to distinguish one element, component, region, layer or section from another. The terms such as “first,” “second” and “third” when used herein do not imply a sequence or order unless clearly indicated by the context. 
     Notwithstanding that the numerical ranges and parameters setting forth the broad scope of the disclosure are approximations, the numerical values set forth in the specific examples are reported as precisely as possible. Any numerical value, however, inherently contains certain errors necessarily resulting from the standard deviation found in the respective testing measurements. Also, as used herein, the terms “substantially,” “approximately” or “about” generally mean within a value or range that can be contemplated by people having ordinary skill in the art. Alternatively, the terms “substantially,” “approximately” or “about” mean within an acceptable standard error of the mean when considered by one of ordinary skill in the art. People having ordinary skill in the art can understand that the acceptable standard error may vary according to different technologies. Other than in the operating/working examples, or unless otherwise expressly specified, all of the numerical ranges, amounts, values and percentages such as those for quantities of materials, durations of times, temperatures, operating conditions, ratios of amounts, and the likes thereof disclosed herein should be understood as modified in all instances by the terms “substantially,” “approximately” or “about.” Accordingly, unless indicated to the contrary, the numerical parameters set forth in the present disclosure and attached claims are approximations that can vary as desired. At the very least, each numerical parameter should at least be construed in light of the number of reported significant digits and by applying ordinary rounding techniques. Ranges can be expressed herein as from one endpoint to another endpoint or between two endpoints. All ranges disclosed herein are inclusive of the endpoints, unless specified otherwise. 
     With the ongoing down-scaling of integrated circuits, power supply voltages of the circuits may be reduced. However, the voltage reduction may be different in different circuits or regions. For example, threshold voltage (Vt) requirements may be different between the memory circuits and the core circuits. A multiple-Vt capability is therefore required for device design. 
     Further, as the gate length (Lg) scale is reduced in advanced nodes, to realize the multiple-Vt design using different gate metal materials becomes challenging due to the limited Lg and the gap-filling ability requirements. 
     Embodiments of a method for forming a semiconductor structure are therefore provided. The semiconductor structure is formed in an HKMG process in accordance with the embodiments. The semiconductor structure can be formed in a planar device process according to some embodiments. The semiconductor structure can be formed in a non-planar device in alternative embodiments. In some embodiments, the method for forming the semiconductor structure includes in-situ and/or ex-situ nitridation on barrier layers. The barrier layers with different nitrogen (N) concentrations may have different metal barrier abilities. In some embodiments, when the metal includes aluminum (Al), the barrier including greater N concentration provides greater Al-diffusion barrier ability. Further, the greater Al-diffusion barrier ability is required by higher-voltage devices. Accordingly, the method provides barriers with different N concentrations to meet multiple-Vt structure requirements. 
       FIG. 1  is a flowchart representing a method for forming a semiconductor structure  10  according to aspects of the present disclosure. The method  10  includes a number of operations ( 101 ,  102 ,  103 ,  104 ,  105 ,  106 , and  107 ). The method  10  will be further described according to one or more embodiments. It should be noted that the operations of the method  10  may be rearranged or otherwise modified within the scope of the various aspects. It should be further noted that additional processes may be provided before, during, and after the method  10 , and that some other processes may just be briefly described herein. Thus, other implementations are possible within the scope of the various aspects described herein. 
       FIG. 2  shows perspective views illustrating portions of a semiconductor structure according to aspects of the present disclosure. In some embodiments, in operation  101 , the method  10  include forming a first FET device  210   a  and a second FET device  210   b  over a substrate  200 . In some embodiments, the substrate  200  may be a semiconductor substrate such as a silicon substrate. The substrate  200  may also include other semiconductors such as germanium (Ge), silicon carbide (SiC), silicon germanium (SiGe), or diamond. 
     Alternatively, the substrate  200  may include a compound semiconductor and/or an alloy semiconductor. The substrate  200  may include various layers, including conductive or insulating layers formed on a semiconductor substrate. The substrate  200  may include various doping configurations depending on design requirements, as is known in the art. For example, different doping profiles (e.g., n wells or p wells) may be formed on the substrate  200  in regions designed for different device types (e.g., n-type field-effect transistors (NFET), or p-type field-effect transistors (PFET)). The suitable doping may include ion implantation of dopants and/or diffusion processes. 
     In some embodiments, the substrate  200  may include a first region  202   a  and a second region  202   b . Further, the substrate  200  may include isolation structures, e.g., shallow trench isolation (STI) structures  204  interposing the first and second regions  202   a  and  202   b . The first and second regions  202   a  and  202   b  are defined for accommodating different devices. For example, the first region  202   a  may accommodate a high voltage (HV) device while the second region  202   b  may accommodate a low voltage (LV) device. In some embodiments, the HV device used herein is a device having an operating voltage greater than that of the LV device. However, operating voltages can vary for different applications, thus they are not limited herein. 
     In some embodiments, the devices  210   a  and  210   b  may be planar transistors or multi-gate transistors, such as fin-like FETs (FinFETs). 
     In some embodiments, in operation  101 , the first FET device  210   a  is formed in the first region  202   a . In some embodiments, the first FET device  210   a  may be an HV device. In some embodiments, the first FET device  210   a  may an n-type HV device, but the disclosure is not limited thereto. The first FET device  210   a  may include a first gate structure  212   a  and a first source/drain  214   a . In some embodiments, the first FET device  210   a  may be a first FinFET device, and a first fin structure  206   a  is disposed over the substrate  200 , as shown in  FIG. 2 . A portion of the first fin structure  206   a  covered by the first gate structure  212   a  serves as a channel region, and portions of the first fin structure  206   a  exposed through the first gate structure  212   a  serve as the first source/drain  214   a.    
     In operation  101 , the second FET device  210   b  is formed in the second region  202   b . In some embodiments, the second FET device  210   b  may be an LV device. In some embodiments, the second FET device  210   a  may be an n-type LV device, but the disclosure is not limited thereto. The second FET device  210   b  may include a second gate structure  212   b  and a second source/drain  214   b . In some embodiments, the second FET device  210   b  is a second FinFET device, and a second fin structure  206   b  is disposed over the substrate  200 , as shown in  FIG. 2 . Similar to the first FET device  210   a  described above, in the second FET device  210   b , a portion of the second fin structure  206   b  covered by the second gate structure  212   b  serves as a channel region, and portions of the second fin structure  206   b  exposed through the second gate structure  212   b  serve as the second source/drain  214   b.    
     In some embodiments, the first gate structure  212   a  and the second gate structure  212   b  are sacrificial gate structures. The first and second sacrificial gate structures may respectively include a dielectric layer and a sacrificial semiconductor layer. In some embodiments, the semiconductor layers are made of polysilicon, but the disclosure is not limited thereto. In some embodiments, spacers  216  (shown in  FIG. 3 ) can be formed over sidewalls of the sacrificial gate structures. In some embodiments, the spacers  216  are made of silicon nitride (SiN), silicon carbide (SiC), silicon oxide (SiO), silicon oxynitride (SiON), silicon carbide or any other suitable material, but the disclosure is not limited thereto. In some embodiments, the spacers  216  are formed by deposition and etch back operations. 
     As shown in  FIG. 2 , in some embodiments, the first source/drain  214   a  is formed over the first fin structure  206   a  at two opposite sides of the first gate structure  212   a . Similarly, the second source/drain  214   b  is formed over the second fin structure  206   b  at two opposite sides of the second gate structure  212   b . In some embodiments, heights of the first source/drain  214   a  and the second source/drain  214   b  may be greater than heights of the first and second fin structures  206   a  and  206   b . In some embodiments, the first and second source/drain  214   a  and  214   b  may be formed by forming recesses in the fin structures  206   a  and  206   b  and growing a strained material in the recesses by an epitaxial (epi) process. In addition, the lattice constant of the strained material may be different from the lattice constant of the fin structures  206   a  and  206   b . Accordingly, the first and second source/drain  214   a  and  214   b  may serve as stressors that improve carrier mobility. In some embodiments, the first source/drain  214   a  and the second source/drain  214   b  may both include n-type dopants. However, a dopant concentration of the first source/drain  214   a  may be different from that of the second source/drain  214   b.    
     In some embodiments, after the forming of the source/drain structures, a contact etch stop layer (CESL)  218  may be formed to cover the first and second gate structures  212   a  and  212   b  over the substrate  200 . In some embodiments, the CESL  218  can include silicon nitride, silicon oxynitride, and/or other applicable materials. Subsequently, an inter-layer dielectric (ILD) structure  220  may be formed on the CESL  218  in accordance with some embodiments. The ILD structure  220  may include multilayers made of multiple dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, tetraethoxysilane (TEOS), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), low-k dielectric material, and/or other applicable dielectric materials. Examples of low-k dielectric materials include, but are not limited to, fluorinated silica glass (FSG), carbon-doped silicon oxide, amorphous fluorinated carbon, parylene, bis-benzocyclobutenes (BCB), or polyimide. Next, a polishing process is performed on the ILD structure  220  and the CESL  218  to expose top surfaces of the first and second gate structures  212   a  and  212   b , as shown in  FIG. 3 . In some embodiments, the ILD structure  220  and the CESL  218  are planarized by a chemical mechanical polishing (CMP) process until the top surfaces of the first and second gate structures  212   a  and  212   b  are exposed. Consequently, the ILD structure  220  surrounds the first and second gate structures  212   a ,  212   b  and the first and second fin structures  206   a ,  206   b . In other words, the fin structures  206   a ,  206   b  and the sacrificial gate structures  212   a ,  212   b  are embedded in the ILD structure  220 , while a top surface of the sacrificial gate structures  212   a ,  212   b  remains exposed, as shown in  FIG. 3 . 
     Referring to  FIG. 4 , in some embodiments, in operation  102 , the method  10  includes forming a first gate trench  221   a  in the first FET device  210   a  and a second gate trench  221   b  in the second FET device  210   b . In some embodiments, the sacrificial semiconductor layer is removed. In some embodiments, the dielectric layer may be removed for forming an interfacial layer (IL). In some embodiments, the dielectric layer may be left in the gate trench, though not shown. It should be noted that the removal of the dielectric layer may be performed depending on different process or product requirements. Accordingly, the first fin structure  206   a  is exposed through the first gate trench  221   a , and the second fin structure  206   b  is exposed through the second gate trench  221   b , as shown in  FIG. 4 . Additionally, in some embodiments, a protecting cap may be formed over the ILD structure  220 . The protecting cap may include a material different from that of the ILD structure  220 . The protecting cap protects the ILD structure  220  during the removing of the sacrificial semiconductor layer and other subsequent operations. 
     Referring to  FIG. 5 , in some embodiments, in operation  103 , the method  10  includes forming a first high-k gate dielectric layer  222   a  in the first gate trench  221   a  and a second high-k gate dielectric layer  222   b  in the second gate trench  221   b . A thickness of the first high-k gate dielectric layer  222   a  and a thickness of the second high-k gate dielectric layer  222   b  are similar. In some embodiments, the thicknesses of the first and second high-k gate dielectric layers  222   a  and  222   b  may be between approximately 1 nanometer and approximate 3 nanometers, but the disclosure is not limited thereto. In some embodiments, an IL layer may be formed prior to the forming of the first and second high-k gate dielectric layers  222   a  and  222   b , though not shown. The IL layer may include an oxide-containing material such as SiO or SiON. In some embodiments, the IL layer covers portions of the fin structures  206   a ,  206   b  exposed in the gate trenches  221   a ,  221   b . The first and second high-k gate dielectric layers  222   a  and  222   b  may be simultaneously formed on the IL layer. In some embodiments, the first and second high-k gate dielectric layers  222   a  and  222   b  may be conformally formed in the gate trenches  221   a  and  221   b . Accordingly, the first high-k gate dielectric layer  222   a  covers at least sidewalls of the first gate trench  221   a , and the second high-k gate dielectric layer  222   b  covers at least sidewalls of the second gate trench  221   b . In some embodiments, the first and second high-k gate dielectric layers  222   a  and  222   b  include a high-k dielectric material having a high dielectric constant, for example, greater than that of thermal silicon oxide ( ˜ 3.9). The high-k dielectric material may include hafnium oxide (HfO 2 ), zirconium oxide (ZrO 2 ), lanthanum oxide (La 2 O 3 ), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), yttrium oxide (Y 2 O 3 ), strontium titanate (SrTiO 3 ), hafnium oxynitride (HfOxNy), other suitable metal-oxides, or combinations thereof. 
     Referring to  FIG. 6 , in some embodiments, in operation  104 , the method  10  includes forming a first barrier layer  224   a  over the first high-k gate dielectric layer  222   a  and a second barrier layer  224   b  over the second high-k gate dielectric layer  222   b . In some embodiments, the first and second barrier layers  224   a  and  224   b  are formed simultaneously. In some embodiments, the first and second barrier layers  224   a  and  224   b  may be conformally formed in the gate trenches  221   a  and  221   b . A thickness of the first barrier layer  224   a  and a thickness of the second barrier layer  224   b  are similar. In some embodiments, the thicknesses of the first and second barrier layers  224   a  and  224   b  may be between approximately 0.1 nanometer and approximately 10 nanometers, but the disclosure is not limited thereto. For example, the thicknesses of the first and second barrier layers  224   a  and  224   b  may be less than approximately 1.5 nanometer. Further, the first and second barrier layers  224   a  and  224   b  include a same material. In some embodiments, the first and second barrier layers  224   a  and  224   b  both include tungsten (W). For example, the first and second barrier layers  224   a  and  224   b  may include W-based metal, such as WNx, WCx, WCxNy, W-based metal with oxygen, W-based metal without oxygen, or combinations thereof. Further, a W concentration in each of the first and second barrier layers  224   a  and  224   b  is between approximately 10% and approximately 70%, but the disclosure is not limited thereto. 
     In some embodiments, in operation  105 , the method  10  includes increasing a nitrogen (N) concentration in the first barrier layer  224   a  and an N concentration in the second barrier layer  224   b . Further, the increasing of the N concentrations includes an in-situ treatment and/or an ex-situ treatment. In some embodiments, the N concentration in the first and second barrier layers  224   a  and  224   b  may be increased by the in-situ treatment. The in-situ treatment includes a prolonged ammonia (NH 3 ) pulse during the forming of the first and second barrier layers  224   a  and  224   b  and/or a post-ammonia soak. In some embodiments, a deposition method may be used to form the first and second barrier layers  224   a  and  224   b , and a variable supply of nitrogen-excited species through a remote plasma generator may be involved. By controlling the pulse duration, pulse condition, flow rate, and therefore chemical availability, the N concentration of the first and second barrier layers  224   a  and  224   b  can be adjusted. In some embodiments, a post-NH 3  soak may be used in a thermal environment or a plasma environment. By controlling soak duration, soak condition, and therefore chemical availability, the N concentration of the first and second barrier layers  224   a  and  224   b  can be adjusted. In some embodiments, the W—N bonding can be enhanced in the NH 3  environment or by plasma. In some comparative approaches, when the W-containing barrier layers  224   a  and  224   b  are exposed to air, tungsten oxide tends to be formed. However, the in-situ treatment helps to form more robust W—N bonding for better oxidation resistance, thus mitigating the oxidation issue. In other words, oxidation immunity of the barrier layers  224   a  and  224   b  may be improved by the in-situ treatment. 
     Referring to  FIG. 7 , in some embodiments, the N concentration in the first and second barrier layers  224   a  and  224   b  may be increased by the ex-situ treatment. In some embodiments, the ex-situ treatment may be performed after the in-situ treatment. In other embodiments, the ex-situ treatment may be performed directly after the forming of the first and second barrier layers  224   a  and  224   b . In still other embodiments, the ex-situ treatment may be omitted. The ex-situ treatment may include a nitridation  223  using NH 3 , nitrogen (N 2 ), triatomic hydrogen (H 3 ), inert gas, or combinations thereof. In some embodiments, the nitridation  223  may be performed at a temperature between approximately 200° C. and approximately 600° C., in a pressure between approximately 1 mTorr and approximately 100 mTorr, and in a flow rate between approximately 1 standard cubic centimeters per minute (sccm) and approximately 100 standard liters per minute (slm or slpm). As mentioned above, in some comparative approaches when the W-containing barrier layers  224   a  and  224   b  are exposed to air, tungsten oxide tends to be formed. However, the ex-situ treatment helps to reduce surface oxidation and re-form W—N bonding, and thus further mitigates the oxidation issue and improves oxidation immunity. 
     Accordingly, the first and second barrier layers  224   a  and  224   b  may be referred to as N-containing barrier layers after the increasing of the N concentration. Further, the N concentration in each of the first and second N-containing barrier layers  224   a  and  224   b  may be increased to between approximately 10% and approximately 70%, but the disclosure is not limited thereto. 
     Referring to  FIG. 8 , in some embodiments, in operation  106 , the method  10  includes removing the second barrier layer  224   b  to expose the second high-k gate dielectric layer  222   b  in the second gate trench  221   b . In some embodiments, a protecting layer or a masking layer may be formed in the first region  202   b , and a suitable etching operation may be performed to remove the second barrier layer  224   b . Thus, the second barrier layer  224   b  is removed from the second region  202   b . The protecting layer or the masking layer is removed after the removing of the second barrier layer  224   b.    
     Referring to  FIG. 9 , in some embodiments, in operation  107 , the method  10  includes forming a first work function metal layer  226   a  over the first barrier layer  224   a  and a second work function metal layer  226   b  over the second high-k gate dielectric layer  222   b . A thickness of the first work function metal layer  226   a  and a thickness of the second work function metal layer  226   b  may be similar. In some embodiments, the thicknesses of the first and second work function metal layers  226   a  and  226   b  may be between approximately 0.5 nanometer and approximately 5 nanometers, but the disclosure is not limited thereto. In some embodiments, the first work function metal layer  226   a  may be in direct contact with the first barrier layer  224   a , while the second work function metal layer  226   b  may be in direct contact with the second high-k gate dielectric layer  222   b . A thickness of the first work function metal layer  226   a  and a thickness of the second work function metal layer  226   b  may be similar. The first work function metal layer  226   a  and the second work function metal layer  226   b  may both be n-type work function metal layers. Further, the first and second work function metal layers  226   a  and  226   b  may include same n-type metal materials. In some embodiments, the first work function metal layer  226   a  and the second work function metal layer  226   b  may both be n-type work function metal layers including aluminum (Al). In some embodiments, the first and second work function metal layers  226   a  and  226   b  may be single-layered structures or multilayers of two or more materials, but the disclosure is not limited thereto. In some embodiments, an Al-containing n-type metal layer may be the layer closest to the first barrier layer  224   a  and the second high-k gate dielectric layer  222   b.    
     Referring to  FIG. 10 , in some embodiments, a gap-filling metal layer  228  is formed to fill the first gate trench  221   a  and the second gate trench  221   b . In some embodiments, the gap-filling metal layer  228  can include conductive material such as Al, Cu, AlCu, or W, but is not limited to the above-mentioned materials. 
     Referring to  FIG. 11 , in some embodiments, a planarization operation such as a CMP may be performed to remove superfluous layers. Accordingly, portions of the first and second high-k gate dielectric layers  222   a  and  222   b , portions of the first barrier layer  224   a , portions of the first and second work function metal layers  226   a  and  226   b , and portions of the gap-filling layer  228  are removed. Thus, a first metal gate structure  230   a  is formed in the first FET device  210   a  in the first region  202   a , and a second metal gate structure  230   b  is formed in the second FET device  210   b  in the second region  202   b . In some embodiments, a top surface of the first metal gate structure  230   a , a top surface of the second metal gate structure  230   b  and top surfaces of the ILD structure  220  may be aligned with each other (i.e., the top surfaces may be co-planar). 
     Accordingly, a semiconductor structure  20  is obtained as shown in in  FIG. 11 . The semiconductor structure  20  includes the first FET device  210   a  and the second FET device  210   b . As mentioned above, the first FET device  210   a  and the second FET device  210   b  may both be FinFET devices. Therefore, the first FET device  210   a  includes the first metal gate structure  230   a  over the first fin structure  206   a , and the second FET device  210   b  includes the second metal gate structure  230   b  over the second fin structure  206   b . The first metal gate structure  230   a  includes the first high-k gate dielectric layer  222   a , the first work function metal layer  226   a  over the first high-k gate dielectric layer  222   a , and the first barrier layer  224   a  between the first work function metal layer  226   a  and the first high-k gate dielectric layer  222   a . In some embodiments, the N concentration in the first barrier layer  224   a  is between approximately 10% and approximately 70%. Therefore, the first barrier layer  224   a  is referred to as an N-containing barrier layer. The second metal gate structure  230   b  includes the second high-k gate dielectric layer  222   b  and the second work function metal layer  226   b  over the second high-k gate dielectric layer  222   b . As mentioned above, the first and second work function metal layers  226   a  and  226   b  may be n-type work function metal layers. Further, the first and second work function metal layers  226   a  and  226   b  may be Al-containing n-type work function metal layers. 
     In some embodiments, it is found that Al may diffuse from the work function metal layers  226   a  and  226   b . As shown in  FIG. 11 , because the second work function metal layer  226   b  is in contact with the second high-k gate dielectric layer  222   b , Al may diffuse into the second high-k gate dielectric layer  222   b . Consequently, the second high-k gate dielectric layer  222   b  may include metal material, such as Al. Similarly, Al may diffuse from the first work function metal layer  226   a . However, because the first barrier layer  224   a  is disposed between the first work function metal layer  226   a  and the first high-k gate dielectric layer  222   a , the first barrier layer  224   a  may mitigate the Al diffusion. It should be noted that in some comparative approaches, a barrier layer with a thickness the same as that of the first barrier layer  224   a  is not sufficient to mitigate the Al diffusion. In contrast to the comparative approaches, the method  10  includes increasing the nitrogen concentration in the first barrier layer  224   a  such that, as mentioned above, the first barrier layer  224   a  is referred to as an N-containing barrier layer. Nitrogen in the N-containing barrier layer  224   a  helps to obstruct A1 diffusion even in such a thin layer (i.e., a layer having a thickness less than 1.5 nanometer). Therefore, A1 diffusion into the first high-k gate dielectric layer  222   a  is less than that into the second high-k gate dielectric layer  222   b . In some embodiments, the first high-k gate dielectric layer  222   a  may still include the metal material such as A1, but a metal concentration (i.e., the A1 concentration) of the first high-k gate dielectric layer  222   a  is less than a metal concentration (i.e., the A1 concentration) of the second high-k gate dielectric layer  222   b.    
     It should be noted that the second high-k gate dielectric layer  222   b  with greater A1 concentration is suitable for an LV device, and the first high-k gate dielectric layer  222   b  with a lower A1 concentration is suitable for an HV device. Accordingly, the semiconductor structure  20  is a multiple-Vt structures suitable for device design. 
     Accordingly, the method  10  includes forming the N-containing barrier layer  224   a  by in-situ and/or ex-situ treatment for the HV device. The N-containing barrier layer  224   a  is able to mitigate the A1 diffusion with a relatively thinner profile. Further, such thin barrier layer  224   a  renders less impact on gap filling. In short, the method  10  provides the N-containing barrier in order to meet multiple-Vt structure requirements with competitive gap-filling ability. 
       FIG. 12  shows perspective views illustrating portions of a semiconductor structure according to aspects of the present disclosure,  FIG. 13  shows cross-sectional views taken along lines X 1 -X 1 ′, X 2 -X 2 ′ and X 3 -X 3 ′ of  FIG. 12 , respectively, and  FIGS. 14 to 21  are schematic drawings illustrating the semiconductor structure at various fabrication stages subsequent to the stage shown in  FIG. 13  according to aspects of the present disclosure in one or more embodiments. It should be noted that same elements in  FIGS. 2 to 11  and  FIGS. 12 to 21  are indicated by same numerals, and can include a same material. Thus, repeated descriptions of details are omitted for brevity. 
     In some embodiments, in operation  101 , the method  10  includes forming a first FET device  210   a , a second FET device  210   b  and a third FET device  210   c  over a substrate  200 . As mentioned above, the substrate  200  may include regions designed for different device types. For example, the substrate  200  may include a first region  202   a , a second region  202   b  and a third region  202   c . Further, the substrate  200  may include isolation structures, e.g., STI structures  204 , interposing the regions  202   a ,  202   b  and  202   c . The regions  202   a ,  202   b  and  202   c  are defined for accommodating different devices. For example, the first region  202   a  may accommodate an HV device, the second region  202   b  may accommodate an LV device, and the third region  202   c  may accommodate a middle voltage (MV) device. In some embodiments, the HV device used herein is a device have an operating voltage greater than that of the LV device, and the MV device is a device have an operating voltage between those of the HV device and the LV device. As mentioned above, operating voltages can vary for different applications, thus they are not limited herein. Additionally, the region arrangement is not limited by  FIGS. 12 to 21 . 
     As mentioned above, the devices  210   a  to  210   c  may be planar transistors or multi-gate transistors, such as FinFETs. The first and second FET devices  210   a  and  210   b  are similar to those described above; therefore, repeated descriptions of details are omitted for brevity. 
     In some embodiments, in operation  101 , the third FET device  210   c  is formed in the third region  202   c . In some embodiments, the third FET device  210   c  may be an MV device. In some embodiments, the third FET device  210   c  may an n-type MV device, but the disclosure is not limited thereto. The third FET device  210   c  may include a third gate structure  212   c  and a third source/drain  214   c . In some embodiments, the third FET device  210   c  may be a third FinFET device, and a third fin structure  206   c  is disposed over the substrate  200 , as shown in  FIG. 12 . The third gate structure  212   c  is a sacrificial gate structure. As mentioned above, the sacrificial gate structure may include a dielectric layer and a sacrificial semiconductor layer. As also mentioned above, spacers  216  (shown in  FIG. 13 ) can be formed over sidewalls of the sacrificial gate structure  212   c.    
     As shown in  FIG. 12 , the third source/drain  214   c  is formed over the third fin structure  206   c  at two opposite sides of the third gate structure  212   c  in accordance with some embodiments. In some embodiments, a height of the third source/drain  214   c  may be greater than a height of the fin structure  206   c . In some embodiments, the third source/drain  214   c  may include strained material serving as stressors that improve carrier mobility. In some embodiments, both of the third source/drain  214   c  may include n-type dopants, and a dopant concentration of the third source/drain  214   c  may be different from those of the first source/drain  214   a  and the second source/drain  214   b.    
     As mentioned above, a CESL  218  may be formed to cover the sacrificial gate structures  212   a ,  212   b  and  212   c  over the substrate  200 . Subsequently, an ILD structure  220  may be formed on the CESL  218 . A polishing process may be performed on the ILD structure  220  and the CESL  218  to expose top surfaces of the sacrificial gate structures  212   a ,  212   b  and  212   c , as shown in  FIG. 13 . 
     Referring to  FIG. 14 , in some embodiments, in operation  102 , the method  10  includes forming a first gate trench  221   a  in the first FET device  210   a , a second gate trench  221   b  in the second FET device  210   b , and a third gate trench  221   c  in the third FET device  210   c . As mentioned above, a removal of the dielectric layer may be performed depending on different process or product requirements. In some embodiments, the first fin structure  206   a  is exposed through the first gate trench  221   a , the second fin structure  206   b  is exposed through the second gate trench  221   b , and the third fin structure  206   c  is exposed through the third gate trench  221   c , as shown in  FIG. 14 . 
     Referring to  FIG. 15 , in some embodiments, in operation  103 , the method  10  includes forming a first high-k gate dielectric layer  222   a  in the first gate trench  221   a , a second high-k gate dielectric layer  222   b  in the second gate trench  221   b , and a third high-k gate dielectric layer  222   c  in the third gate trench  221   c . In some embodiments, an IL layer may be formed prior to the forming of the high-k gate dielectric layers  222   a ,  222   b  and  222   c , though not shown. In some embodiments, the high-k gate dielectric layers  222   a ,  222   b  and  222   c  may be simultaneously and conformally formed in the gate trenches  221   a ,  221   b  and  221   c , respectively. 
     Referring to  FIG. 16 , in some embodiments, in operation  104 , the method  10  includes forming a first barrier layer  224   a  on the first high-k gate dielectric layer  222   a , a second barrier layer  224   b  on the second high-k gate dielectric layer  222   b , and a third barrier layer  224   c  on the third high-k gate dielectric layer  222   c . In some embodiments, the barrier layers  224   a ,  224   b  and  224   c  are formed simultaneously. In some embodiments, the barrier layers  224   a ,  224   b  and  224   c  may be conformally formed in the gate trenches  221   a ,  221   b  and  221   c , respectively. A thickness of the first barrier layer  224   a , a thickness of the second barrier layer  224   b  and a thickness of the third barrier layer  224   c  are similar. In some embodiments, the thicknesses of the barrier layers  224   a ,  224   b  and  224   c  may be between approximately 0.1 nanometer and approximately 10 nanometers, but the disclosure is not limited thereto. For example, the thicknesses of the barrier layers  224   a ,  224   b  and  224   c  may be less than approximately 1.5 nanometer. Further, the barrier layers  224   a ,  224   b  and  224   c  include a same material. In some embodiments, the barrier layers  224   a ,  224   b  and  224   c  include tungsten. For example, the barrier layers  224   a ,  224   b  and  224   c  may include W-based metal, such as WNx, WCx, WCxNy, W-based metal with oxygen, W-based metal without oxygen, or combinations thereof. Further, a W concentration in each of the barrier layers  224   a ,  224   b  and  224   c  is between approximately 10% and approximately 70%, but the disclosure is not limited thereto. 
     In some embodiments, in operation  105 , the method  10  includes increasing a nitrogen concentration in each of the barrier layers  224   a ,  224   b  and  224   c . As mentioned above, the increasing of the N concentrations includes an in-situ treatment and/or an ex-situ treatment. In some embodiments, the N concentration in each of the barrier layers  224   a ,  224   b  and  224   c  may be increased by the in-situ treatment. The in-situ treatment may be similar to those described above; therefore, repeated description of the in-situ treatment is omitted for brevity. 
     Referring to  FIG. 17 , in some embodiments, the N concentration in each of the barrier layers  224   a ,  224   b  and  224   c  may be increased by the ex-situ treatment. In some embodiments, the ex-situ treatment may be performed after the in-situ treatment. In other embodiments, the ex-situ treatment may be performed directly after the forming of the barrier layers  224   a ,  224   b  and  224   c . The ex-situ treatment may include a first nitridation  223 - 1  using NH 3 , N 2 , H 3 , inert gas, or combinations thereof. Parameters of the first nitridation  223 - 1  may be similar to those described above; therefore, repeated description of the ex-situ treatment is omitted for brevity. 
     Referring to  FIG. 18 , in some embodiments, in operation  105 , the method  10  may include performing a second nitridation  223 - 2  to further increase the N concentration. In some embodiments, a masking layer or protecting layer  225  may be formed to cover the second region  202   b  and the third region  202   c . The second nitridation  223 - 2  may use NH 3 , N 2 , H 3 , inert gas, or combinations thereof. Parameters of the second nitridation  223 - 2  may be similar to those described above; therefore, repeated description of the ex-situ treatment is omitted for brevity. In some embodiments, the N concentration of the first barrier layer  224   a  may be further increased, and thus the N concentration of the first barrier layer  224   a  is greater than the N concentrations of the second barrier layer  224   b  and the third barrier layer  224   c . Additionally, the masking layer or the protecting layer  225  is removed after the second nitridation. 
     Accordingly, the first, second and third barrier layers  224   a ,  224   b  and  224   c  may be referred to as N-containing barrier layers after the increasing of the N concentration. The N concentration in each of the N-containing barrier layers  224   a ,  224   b  and  224   c  may be increased to between approximately 10% and approximately 70%, but the disclosure is not limited thereto. Further, the N concentration of the first barrier layer  224   a  is greater than the N concentrations of the second barrier layer  224   b  and the third barrier layer  224   c  due to the two ex-situ treatments. 
     Referring to  FIG. 19 , in some embodiments, in operation  106 , the method  10  includes removing the second barrier layer  224   b  to expose the second high-k gate dielectric layer  222   b  in the second gate trench  221   b . In some embodiments, a protecting layer or a masking layer (not shown) may be formed in the first region  202   a  and the third region  202   c , and a suitable etching operation may be performed to remove the second barrier layer  224   b . Thus, the second barrier layer  224   b  is removed from the second region  202   b . The protecting layer or the masking layer is removed after the removing of the second barrier layer  224   b.    
     Referring to  FIG. 20 , in some embodiments, in operation  107 , the method  10  includes forming a first work function metal layer  226   a  over the first barrier layer  224   a , a second work function metal layer  226   b  over the second high-k gate dielectric layer  222   b , and a third work function metal layer  226   c  over the third barrier layer  224   c . In some embodiments, the first work function metal layer  226   a  may be in direct contact with the first barrier layer  224   a , and the third work function metal layer  226   c  may be in direct contact with the third barrier layer  224   c . In contrast with the first and third work function metal layers  226   a  and  226   c , the second work function metal layer  226   b  may be in direct contact with the second high-k gate dielectric layer  222   b . A thickness of the first work function metal layer  226   a , a thickness of the second work function metal layer  226   b  and a thickness of the third work function metal layer  226   c  may be similar. The work function metal layers  226   a ,  226   b  and  226   c  may all be n-type work function metal layers. Further, the work function metal layers  226   a ,  226   b  and  226   c  may include same n-type metal materials. In some embodiments, the work function metal layers  226   a ,  226   b  and  226   c  may all be n-type work function metal layers that includes aluminum. 
     Referring to  FIG. 21 , in some embodiments, a gap-filling metal layer  228  is formed to fill the first gate trench  221   a , the second gate trench  221   b  and the third gate trench  221   c.    
     Referring to  FIG. 21 , in some embodiments, a planarization operation such as a CMP may be performed to remove superfluous layers. Accordingly, a first metal gate structure  230   a  is formed in the first FET device  210   a  in the first region  202   a , a second metal gate structure  230   b  is formed in the second FET device  210   b  in the second region  202   b , and a third metal gate structure  230   c  is formed in the third FET device  210   c  in the third region  202   c . In some embodiments, a top surface of the first metal gate structure  230   a , a top surface of the second metal gate structure  230   b , a top surface of the third metal gate structure  230   c , and top surfaces of the ILD structure  220  may be aligned with each other (i.e., the top surfaces may be co-planar). 
     Accordingly, a semiconductor structure  20 ′ is obtained as shown in  FIG. 21 . The semiconductor structure  20 ′ includes the first FET device  210   a , the second FET device  210   b  and the third FET device  210   c . As mentioned above, the FET devices  210   a ,  210   b  and  210   c  may all be FinFET devices. Therefore, the first FET device  210   a  includes the first metal gate structure  230   a  over the first fin structure  206   a , the second FET device  210   b  includes the second metal gate structure  230   b  over the second fin structure  206   b , and the third FET device  210   c  includes the third metal gate structure  230   c  over the third fin structure  206   c . The first metal gate structure  230   a  includes the first high-k gate dielectric layer  222   a , the first work function metal layer  226   a , and the first barrier layer  224   a  between the first work function metal layer  226   a  and the first high-k gate dielectric layer  222   a . In some embodiments, the N concentration in the first barrier layer  224   a  is between approximately 10% and approximately 70%. Therefore, the first barrier layer  224   a  is referred to as an N-containing barrier layer. The third metal gate structure  230   c  includes the third high-k gate dielectric layer  222   c , the third work function metal layer  226   c , and the third barrier layer  224   c  between the third work function metal layer  226   c  and the third high-k gate dielectric layer  222   c . In some embodiments, the N concentration in the third barrier layer  224   c  is between approximately 10% and approximately 70%. Therefore, the third barrier layer  224   c  is also referred to as an N-containing barrier layer. However, the N concentration of the first barrier layer  224   a  is greater than the N concentration of the third barrier layer  224   c . The second metal gate structure  230   b  includes the second high-k gate dielectric layer  222   b  and the second work function metal layer  226   b . As mentioned above, the work function metal layers  226   a ,  226   b  and  226   c  may be n-type work function metal layers. Further, the work function metal layers  226   a ,  226   b  and  226   c  may be A1-containing n-type work function metal layers. 
     As mentioned above, it is found that A1 may diffuse from the work function metal layers  226   a  and  226   b . As shown in  FIG. 21 , because the second work function metal layer  226   b  is in contact with the second high-k gate dielectric layer  222   b , A1 may diffuse into the second high-k gate dielectric layer  222   b . Consequently, the second high-k gate dielectric layer  222   b  may include metal material, such as A1. Similarly, A1 may diffuse from the first work function metal layer  226   a  and from the third work function metal layer  226   c . However, the first barrier layer  224   a  and the third barrier layer  224   c  may mitigate the A1 diffusion due to the introduction of nitrogen. As mentioned above, nitrogen in the N-containing barrier layers  224   a  and  224   c  helps to obstruct A1 diffusion even in such thin layers. Therefore, A1 diffusion into the first high-k gate dielectric layer  222   a  and the third high-k gate dielectric layer  222   c  is less than that into the second high-k gate dielectric layer  222   b . Further, the first barrier layer  224   a  may have greater A1 diffusion barrier ability due to its greater N concentration. In some embodiments, the first high-k gate dielectric layer  222   a , the second high-k gate dielectric layer  222   b  and the third high-k gate dielectric layer  222   c  may still include the metal material such as A1, but a metal concentration (i.e., the A1 concentration) of the third high-k gate dielectric layer  222   c  is less than a metal concentration (i.e., the A1 concentration) of the second high-k gate dielectric layer  222   b , and a metal concentration (i.e., the A1 concentration) of the first high-k gate dielectric layer  222   a  is less than the metal concentration (i.e., the A1 concentration) of the third high-k gate dielectric layer  222   c.    
     It should be noted that the second high-k gate dielectric layer  222   b  with high A1 concentration is suitable for an LV device, the first high-k gate dielectric layer  222   a  with low A1 concentration is suitable for an HV device, and the third high-k gate dielectric layer  222   c  with medium A1 concentration is suitable for an MV device. Accordingly, the semiconductor structure  20 ′ is a multiple-Vt structure suitable for device design. 
     Accordingly, the method  10  includes forming the N-containing barrier layers  224   a  and  224   c  with different N concentration by in-situ and ex-situ treatment for the HV device. The N-containing barrier layers  224   a  and  224   c  are able to mitigate the A1 diffusion, therefore such thin barrier layers have less impact on gap filling. In short, the method  10  provides the N-containing barrier for meeting multiple-Vt structure requirements with competitive gap-filling ability. 
     In summary, the present disclosure provides a method for forming a semiconductor structure. The method may be integrated into an HKMG process. The method may also be integrated with formation of a planar device or a non-planar device. In some embodiments, the method for forming the semiconductor structure includes in-situ and/or ex-situ nitridation of barrier layers. The barrier layers with different nitrogen concentrations may have different metal barrier abilities, thereby helping the semiconductor structure to meet multiple-Vt structure requirements. 
     Some embodiments of the present disclosure provide a semiconductor structure. The semiconductor structure includes a first metal gate structure and a second metal gate structure. The first metal gate structure includes a first high-k gate dielectric layer, a first work function metal layer over the first high-k gate dielectric layer, and an N-containing barrier layer between the first high-k gate dielectric layer and the first work function metal layer. The second metal gate structure includes a second high-k gate dielectric layer and a second work function metal layer over the second high-k gate dielectric layer. The first high-k gate dielectric layer and the second high-k gate dielectric layer include a same metal material. The first high-k gate dielectric layer has a first metal concentration, the second high-k gate dielectric layer has a second metal concentration, and the first metal concentration is less than the second metal concentration. 
     Some embodiments of the present disclosure provide a semiconductor structure. The semiconductor structure includes a first metal gate structure and a second metal gate structure. The first metal gate structure includes a first high-k gate dielectric layer, a first work function metal layer over the first high-k gate dielectric layer, and a first N-containing barrier layer between the first high-k gate dielectric layer and the first work function metal layer. The second metal gate structure includes a second high-k gate dielectric layer, a second work function metal layer over the second high-k gate dielectric layer, and a second N-containing barrier layer between the second high-k gate dielectric layer and the second work function metal layer. The first N-containing barrier layer has a first N concentration, the second N-containing barrier layer has a second N concentration, and the first N concentration is greater than the second N concentration. The first high-k gate dielectric layer has a first metal concentration, the second high-k gate dielectric layer has a second metal concentration, and the first metal concentration is less than the second metal concentration. 
     Some embodiments of the present disclosure provide a method for forming a semiconductor structure. The method includes following operations. A first FET device and a second FET device are formed over a substrate. A first gate trench is formed in the first FET device, and a second gate trench is formed in the second FET device. A first high-k gate dielectric layer is formed in the first gate trench, and a second high-k gate dielectric layer is formed in the second gate trench. A first barrier layer is formed over the first high-k gate dielectric layer, and a second barrier layer is formed over the second high-k gate dielectric layer. An N concentration in the first barrier layer and an N concentration in the second barrier layer are increased. The second barrier layer is removed to expose the second high-k gate dielectric layer. A first work function metal layer is formed over the first barrier layer, and a second work function metal layer is formed over the second high-k gate dielectric layer. 
     The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.