Patent Publication Number: US-11386958-B2

Title: Methods and apparatuses including a string of memory cells having a first select transistor coupled to a second select transistor

Description:
PRIORITY APPLICATION 
     This application is a continuation of U.S. application Ser. No. 16/422,209, filed May 24, 2019, which is a continuation of U.S. application Ser. No. 16/009,995, filed Jun. 15, 2018, now issued as U.S. Pat. No. 10,340,009, which is a continuation of U.S. application Ser. No. 15/443,548, filed Feb. 27, 2017, now issued as U.S. Pat. No. 10,020,056, which is a continuation of U.S. application Ser. No. 15/131,671, filed Apr. 18, 2016, now issued as U.S. Pat. No. 9,583,154, which is a continuation of U.S. application Ser. No. 14/456,222, filed Aug. 11, 2014, now issued as U.S. Pat. No. 9,318,200, all of which are incorporated herein by reference in their entirety. 
    
    
     BACKGROUND 
     The semiconductor industry has a market driven need to reduce the size of devices, such as transistors, and reduce the number of devices for a given apparatus. Some product goals include lower power consumption, higher performance, and smaller sizes. Various memory architectures have been proposed to decrease the power consumption in a memory device, some of which may sacrifice power consumed during a read or write operation or overall size of an apparatus for a reduced leakage current. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  shows a circuit diagram of a prior art memory array. 
         FIG. 2A  shows a planar view block diagram of a prior art memory, array. 
         FIG. 2B  shows a planar view block diagram of the prior art memory array of  FIG. 2A  from the direction indicated by the lines  2 B- 2 B in  FIG. 2A . 
         FIG. 3A  shows a block diagram of a memory array, in accord with one or more embodiments. 
         FIG. 3B  shows a block diagram of an example of another memory, array, in accord with one or more embodiments. 
         FIG. 4A  shows a planar view block diagram of a memory array, in accord with one or more embodiments. 
         FIG. 4B  shows a planar view block diagram of the memory array of  FIG. 4A  from the direction indicated by the lines  4 B- 4 B in  FIG. 4A , in accord with one or more embodiments. 
         FIG. 4C  shows a planar view block diagram of the memory array of  FIG. 4A  from the direction indicated by the lines  4 B- 4 B in  FIG. 4A , in accord with one or more embodiments. 
         FIG. 5  shows a circuit diagram of a memory array, in accord with one or more embodiments. 
         FIG. 6  shows another circuit diagram of another memory array, in accord with one or more embodiments. 
         FIG. 7A  shows a planar view block diagram of a u-shaped memory array, in accord with one or more embodiments. 
         FIG. 7B  shows a planar view block diagram of the memory array of  FIG. 7A  from the direction indicated by the lines  7 B- 7 B in  FIG. 7A , in accord with one or more embodiments. 
         FIG. 8  shows a circuit diagram of another memory array, in accord with one or more embodiments. 
         FIG. 9A  shows a planar view block diagram of a memory array, in accord with one or more embodiments. 
         FIG. 9B  shows a planar view block diagram of the memory array of  FIG. 9B  from the direction indicated by the lines  9 B- 9 B in  FIG. 9A , in accord with one or more embodiments. 
         FIG. 10  shows a circuit diagram of another memory array, in accord with one or more embodiments. 
         FIG. 11  shows a table of decoder logic states, in accord with one or more embodiments. 
         FIG. 12  shows a flow diagram of a method of performing a read operation, in accord with one or more embodiments. 
         FIG. 13A  shows a waveform of a read operation, in accord with one or more embodiments. 
         FIG. 13B  shows a waveform of another read operation, in accord with one or more embodiments. 
         FIG. 14  shows a flow diagram of a method of performing a program operation, in accord with one or more embodiments. 
         FIG. 15  shows a waveform of a program operation, in accord with one or more embodiments. 
     
    
    
     DETAILED DESCRIPTION 
     A conventional  3 D NAND memory architecture includes a string of memory cells formed along a polysilicon pillar between a first select transistor (e.g., a Select Gate (SG) transistor sometimes referred to as an SG Drain (SGD) transistor) and a second select transistor (e.g., an SG transistor sometimes referred to as an SG Source (SGS) transistor). The leakage current of the SGD transistor is relatively high and is not significantly reduced during a read operation. This leakage current can increase with temperature. According to at least one embodiment disclosed herein, a string that includes at least two SGS transistors can be used to suppress such a leakage current. For example, two SGS transistors can be coupled between a source (e.g., a source plate, source node, source line, source region, source layer, etc.) and a memory cell of the string. A drive transistor coupled to one of the two SGS transistors can be the same drive transistor that drives an SGD transistor, so as to reduce the number of drive transistors required to drive the SG transistors of the memory array. 
     Note that as used herein, a gate is a part of a transistor. A CG is a control gate that is a part of a memory cell and an SG is a control gate that is part of a select transistor. The memory cell can include a data storage structure, such as a charge storage structure (e.g., a floating gate and/or a charge trap) or variable resistance structure, for example. Generally, a select transistor that is coupled between a source and a memory cell is considered an SGS transistor and a select transistor that is coupled between a data line and a memory cell is considered an SGD transistor. As used herein, both an SGS transistor and an SGD transistor are referred to as a select transistor. For memory cells including a charge storage structure, the charge stored on the charge storage structure represents at least a portion of a bit of stored data. The SGD transistor typically does not include a charge storage structure, but embodiments are not limited thereto. In a double SGS memory architecture, one SGS transistor can include a charge storage structure and the other SGS transistor might not include a charge storage structures. However, both SGS transistors can include or not include charge storage structures. 
       FIG. 1  shows a circuit diagram of an example of a prior art memory array  100 . The array  100  includes a data line  102 , a plurality of select transistors  104 , a plurality of memory cells  106 A,  106 B,  106 C,  106 D,  106 E,  106 F,  106 G, and  106 H, a plurality of select transistors  108 , and a source  110 . 
     Each of the SGD select transistors  104  is coupled between a memory cell  106 A and a data line  102 . Each of the SGD select transistors  104  is coupled to a respective drive transistor (not shown in  FIG. 1 ). The drive transistor is typically large (on the order of about one hundred time larger than the select transistor  104 ) and takes a relatively large amount of space in a corresponding apparatus. 
     Each memory cell  106 A-H can be coupled to other memory cells on the same tier, such as through a CG connection  112 A,  112 B,  1120 ,  112 D,  112 E,  112 F,  112 G, or  112 H, respectively. In  FIG. 1 , each memory cell  106 A is on the same tier as all other memory cells  106 A. Similarly, all memory cells  106 B are on the same tier, and so forth. 
     Each of the SGS select transistors  108  is coupled to the other select transistors  108  on the same tier, such as through the SGS connection  114 . The SGS select transistors  108  are coupled between a respective memory cell  10611  and the source  110 . 
     In performing a read operation using a memory array such as memory array  100 , gates of the unselected SGD select transistors  104  are driven to a reference voltage (e.g., zero volts or ground, such as V ss ), while gates of a selected SGD select transistor  104  and the SGS select transistor  108  are driven to a higher voltage, such as V cc , and the source  110  is driven to a reference voltage, such as V ss . In this state, leakage current may flow through any unselected SGD select transistors  104  towards the source  110 . The potential on the data line  102  is often used to identify the value of the data stored in the memory cell that is being read. For example, for a single level cell, a V cc  potential on the data line  102  might indicate that the memory cell stores a data value of “0” and a V ss  potential on the data line  102  might indicate that the memory cell stores a data value of “1”. 
       FIG. 2A  shows a planar view block diagram of a prior art memory array  200 .  FIG. 2B  shows a planar view block diagram of the prior art memory array  200  of  FIG. 2A . The memory array  200  includes data lines  202 A,  202 B,  202 C, and  202 D, SGD connections  204 A,  204 B,  204 C, and  204 I) (which are sometimes referred to as “drain select lines”), CG connections  206 A,  206 B,  206 C, and  206 D (which are sometimes referred to as “word lines”), SGS connections  208 A,  208 B,  208 C, and  208 D (which are sometimes referred to as “source select lines”), a source  210 , and pillars  212 A,  212 B,  212 C,  212 D,  212 E,  212 F and  212 G. The memory array  200  can be similar to memory array  100 , but with separate SGS connections  208 A-D (electrically insulated from each other), such that a separate drive transistor is required to drive each SGS connection  208 A-D. 
     The memory array  200  can provide a structure that allows an SGS connection  208 A-D to control access to channels in unselected pillars  212 A-D and provide the ability to make the unselected channels float. In this manner, the unselected channels can be boosted by a capacitive coupling between the CG connections and the floating channels, such as when a V pass_read  or V read  voltage is applied to the CG connections as shown in  FIG. 13A or 13B . The floating unselected channel voltages can suppress the electric field in a tunnel oxide between the respective unselected channel and the storage structures so that the electric field is sufficiently small. This floating voltage and small electric field can suppress a Fowler-Nordheim tunnel current for the unselected pillars when reading. Thus, the read disturbance for unselected memory cells of the unselected pillars can be reduced, and the cell threshold voltages can remain relatively unchanged on reading, and the read disturbance can be reduced. However, this added flexibility in driving the SG connections  204 A-D and  208 A-D individually requires a drive transistor for each, individual SG connection  204 A-D and  208 A-D. 
     The added drive transistors take up a relatively large amount of space and can draw more power than select transistors or memory cells. The drive transistors are typically driven to a potential of about twenty volts, such as during a program operation, so the size of the drive transistors can be relatively large when compared to a select transistor that is typically driven to about seven or eight volts during a read or program operation. A memory array that operates with such additional drive transistors also can consume more power than a memory array that operates with fewer drive transistors. Thus, the leakage current and read disturbance can be reduced, but at the expense of more space and possibly an increase in overall power consumption. 
       FIG. 3A  shows a block diagram of an example of a memory array  300 A, in accord with one or more embodiments.  FIG. 3B  shows a block diagram of an example of a memory array  300 B, in accord with one or more embodiments. The memory arrays  300 A and  300 B each include a plurality of select transistors  302 A,  302 B, and  302 C, memory cells  304 , drive transistors  306 A and  306 B, and a decoder  308 . 
     A string of the memory arrays  300 A and  300 B includes a plurality of select transistors  302 A,  302 B, and  302 C coupled to each other, such as through a plurality of memory cells  304 . The select transistor  302 A at a first end of the string can be coupled to one of the memory cells  304 . The select transistor  302 A can also be coupled to a data line of the memory array (data line not shown in  FIG. 3A or 3B ). The memory array  300  can include a plurality of memory cells  304  coupled in series, such as shown in  FIG. 5, 6, 8 , or  10 . 
     A select transistor  302 B can be coupled between a memory cell of the plurality of memory cells  304  and the select transistor  302 C. The select transistor  302 C can be coupled between the select transistor  3029  and the source (the source is not shown in  FIG. 3A or 3B ). 
     A drive transistor  306 A can be coupled to both the select transistor  302 A and the select transistor  302 C, such as shown in  FIG. 3A . Alternatively, a drive transistor  306 A can be coupled to both the select transistor  302 A and the select transistor  302 B, such as shown in  FIG. 39 . A decoder  308  can include circuitry to determine which drive transistors to activate to access a targeted string of a plurality of strings, such as in a read operation or a program operation (see  FIG. 11  for an example of decoder logic). 
     An advantage of the memory array  300 A or  300 B can include the ability to program a specific memory cell while still maintaining the flexibility to selectively boost or precharge any of the channels of the memory array. This advantage can be provided without an increase in the number of drive transistors over the number of drive transistors required to drive the memory array  200  of  FIG. 2 . The advantage can be provided by including a second select transistor  302 B or  302 C coupled between the source and the memory cells  304  and coupling the select transistor  302 B or  302 C to the select transistor  302 A and the drive transistor  306 A. In this way, the leakage current and read disturbance from performing the read operation, as described with regard to  FIG. 1 , can be reduced, while still maintaining flexibility in selecting or unselecting the select transistors  302 A-C. The leakage current or read disturbance can be reduced by, for example, driving unselected transistors to cut-off unselected channels in a selected block of memory cells. 
       FIG. 4A  shows a planar view block diagram of a memory array  400 A, in accord with one or more embodiments.  FIG. 4B  shows a planar view block diagram of an embodiment of the memory array  400 A of  FIG. 4A .  FIG. 4C  shows a planar view block diagram of a memory array  400 C, that is an alternative embodiment of the memory array  400 A of  FIG. 4A , in accord with one or more embodiments. The memory array  400 A includes a plurality of data lines  402 A,  4029 ,  402 C, and  402 D, pillars  404 A,  404 B,  404 C,  404 D,  404 E,  404 F and  404 G, SGD connections  406 A,  406 B,  406 C, and  406 D, CG connections  408 A,  4089 ,  408 C, and  408 D, SGS connections  410 A or  410 A,  410 B,  410 C, and  410 D, SGS connections  412 A or  412 A,  412 B,  412 C, and  412 I), and a source  414 . 
     The embodiment of memory array  400 A or  400 B includes a plurality of strings of memory cells. Each string of the memory array  400 A or  400 B includes a select transistor coupled to a respective one of the SGD connections  406 A-D, a plurality of memory cells coupled to CG connections  408 A-D, a select transistor coupled to SGS connection  410 A, and a select transistor coupled to a respective one of the SGS connections  412 A-D. The SGS connection  410 A can represent a plurality of SGS connections electrically connected to each other, such as to form an SGS plate. The strings of  FIGS. 4A and 4B  are arranged in a vertical string configuration. 
     The embodiment of the memory array  400 A or  400 C includes a plurality of strings of memory cells. Each string of the memory array  400 A or  400 C includes a select transistor coupled to a respective one of the SGD connections  406 A-D, a plurality of memory cells coupled to CG connections  408 A-D, a select transistor coupled to a respective one of the SGS connections  410 A-D, and a select transistor coupled to SGS connection  412 A. The SGS connection  412 A can represent a plurality of SGS connections electrically connected to each other so as to form an SGS plate. The strings of memory cells of  FIG. 4C  are arranged in a vertical string configuration. 
     The data, lines  402 A-D can include a conductive material, such as metal or a semiconductor (e.g., a doped semiconductor, such as conductively doped polysilicon). The data lines  402 A-D can be coupled to pillars  404 A-O through SOD select transistors. The pillars  404 A-G can be driven to selectively activate a particular string for reading or programming. The pillars  404 A-O can include a semiconductor material, such as polysilicon, germanium, indium, doped versions thereof, or combinations thereof, among others. 
     The SGD connections  406 A-D can be electrically isolated from one another, such as by an electric insulator (e.g., a dielectric or an air gap). The SOD connections  406 A-D can include a conductive material, such as a conductively, doped semiconductor material. The SGD connections  406 A-D can be separated from the pillar  404 A-O by one or more dielectric materials, such as an oxide, to form SGD select transistors. 
     The CG connections  408 A-D can include a conductive material, such as a conductively doped semiconductor material. The CG connections  408 A-D can each comprise a plurality of CG connections. A CG connection  408 A-D can be separated from a pillar  404 A-D by one or more dielectric and/or semiconductor materials to form a memory cell, such as one including a charge storage structure. For example, conductively doped polysilicon between a CG connection and the pillar (and separated from the CG connection and the pillar by one or more dielectric materials) can store a charge thereon. 
     The memory array  400 A or  400 B includes two tiers of SGS connections  410 A and  412 A-D between the CG connections  408 A-D and the source  414 . Each SGS connection  412 A-D can be coupled to a respective SGD connection  406 A-D (electrical coupling not shown in  FIGS. 4A and 4B ). 
     The memory array  400 A or  400 C includes two tiers of SGS connections  410 A-D and  412 A between the CG connections  408 A-D and the source  414 . Each SGS connection  410 A-D can be coupled to a respective SGD connection  406 A-D (electrical coupling not shown in  FIGS. 4A and 4C ). 
       FIG. 5  shows a circuit diagram  500  of a memory array, in accord with one or more embodiments. The circuit diagram  500  can be of the memory array  400 A or  400 B of  FIGS. 4A and 4B , with the circuit diagram  500  including eight memory cells per string instead of four as shown in  FIGS. 4A and 4B . The memory array of the circuit diagram  500  includes a data line  502 , SGD select transistors  506 A,  506 B,  506 C, and  506 D, memory cells  508 A,  5089 ,  508 C,  508 D,  508 E,  508 F,  5080 , and  508 H, SGS select transistors  510 A,  510 B,  510 C, and  510 D, SGS select transistors  512 A,  5129 ,  512 C, and  512 D, and a source  514 . 
     The SGD select transistor  506 A includes a gate that can include the SOD connection  406 A. The memory cell  508 A includes a gate that can include the CO connection  408 A. Similarly, the SGS select transistor  510 A includes a gate that can include the SGS connection  410 A and the SGS select transistor  512 A includes a gate that can include the SGS connection  412 A. The pillar  404 A-G can function as a body of the select transistors and the memory cells. The source  514  can include the source  414 . The data line  502  can include the data line  402 A-D. 
     The memory array can include a plurality of strings of memory cells, each coupled between the data line  502  and the source  514 . Each string can include a respective SOI) select transistor  506 A-D, a plurality of serially coupled memory cells  508 A-H, a respective SGS select transistor  510 A-D, and a respective SGS select transistor  512 A-D. The strings of memory cells in  FIG. 5  are arranged in a vertical string configuration. 
     The SGD select transistor  506 A-D for each string can be coupled between a data line  502  and a memory cell  508 A of the respective string. The SGS select transistor  510 A-D of each string can be coupled between a memory cell  508 H of the respective string and another respective SGS select transistor  512 A-D of the string. Each SGS select transistor  512 A-D can be coupled between a respective SGS select transistor  510 A-D and a source  514 . 
     Gates of each of the SGS select transistors  510 A-D can be coupled to each other and to a drain of a drive transistor  518 B. A gate of the SGD select transistor  506 A-D of each string can be coupled to the gate of an SGS select transistor  512 A-D of the same string, such as through a connection  516 A,  516 B,  516 C, or  516 D, respectively. The gates of the select transistors  506 A-D and  512 A-D, respectively, can both be coupled to a drain of a respective drive transistor  518 A. 
     By including at least two select transistors coupled between the source  514  and the memory cell  508 H for each string, and by including the connections  516 A-D, the amount of leakage current during a read operation be reduced in at least some embodiments. Also, such a configuration can provide the ability to selectively boost channels of unselected strings of memory cells, such as during programming operations. 
       FIG. 6  shows a circuit diagram  600  of a memory array, in accord with one or more embodiments. The circuit diagram  600  can be of the memory, array  400 A or  400 C of  FIGS. 4A and 4C , with the circuit diagram  600  including eight memory cells per string instead of four as shown in  FIGS. 4A and 4C . The strings of memory cells depicted in  FIG. 6  are arranged in a vertical string configuration. 
     The SGD select transistor  606 A includes a gate that can include the SOD connection  406 A. The memory cell  608 A includes a gate that can include the CG connection  408 A. Similarly, the SGS select transistor  610 A includes a gate that can include the SGS connection  410 A and the SGS select transistor  612 A includes a gate that can include the SGS connection  412 A. The pillar  404 A-G can function as a body of the select transistors and the memory cells. The source  614  can include the source  414 . The data line  602  can include the data line  402 A-D. 
     A memory array configured consistent with the circuit diagram  600  of  FIG. 6  can include an SGS select transistor  610 A-D with a channel length (the length of the gate of the SGS select transistor  610 A-D) that is shorter than the channel length of the SGS select transistor  510 A. The channel length of the SGS select transistor  510 A can be longer so as to handle power required during a program operation without damaging the SGS select transistor  510 A. The SGS select transistor  610 A-D may not need to be driven to the same high voltage potentials as the SGS select transistor  510 A, and thus may include a shorter channel length, such as without the risk of damaging the SGS select transistor  610 A-D. 
       FIG. 7A  shows a planar view block diagram of a memory array  700 , in accord with one or more embodiments.  FIG. 7B  shows a planar view block diagram of the memory array  700  of  FIG. 7A , in accord with one or more embodiments. The memory array  700  can be similar to the memory arrays  400 A-C of  FIGS. 4A-4C  with the memory array  700  configured as a U-Shaped (e.g., a Bit-Cost Scalable (BICS)) memory array. 
     The memory array  700  includes data lines  702 A,  702 B,  702 C, and  702 D, pillars  704 A,  704 B,  704 C,  704 D and  704 E, SGD connections  706 A and  706 I, CG connections  708 A,  708 B,  708 C,  708 D,  708 E,  708 F,  708 G,  708 H,  708 I,  708 J,  708 K,  708 L,  708 M,  708 N,  708 O, and  708 P, SGS connections  710 A and  710 B, SGS connections  712 A and  712 B, and a source  714 . The memory array  700  of  FIG. 7B  shows two strings of memory cells, each including a U-shaped pillar  704 A,  704 E, an SGD select transistor coupled to an SGD connection  706 A,  706 B, a plurality of serially coupled memory cells coupled to CG connections  708 A-H,  708 I-P, an SGS select transistor coupled to an SGS connection  710 A,  710 B, and an SGS select transistor coupled to an SGS connection  712 A,  712 B. 
     A data line  702 A-E can be coupled to one or more pillars  704 A-E. The CG connections  708 E-H can be coupled to the CG connections  708 I-L, such as through a respective connection  716 . The connection  716  can include a conductive material such as a metal or a semiconductor. The connection  716  can include the same material as the CG connection  708 A-I, such as to form two CG connections using some of the same material. Similarly, an SGD connection  706 A-B can be coupled to a respective SGS connection  710 A-B, such as through the connection  718 . The connection  718  can include the same material as the SG connections  706 A-B or  710 A-B, such as to form two SG connections using some of the same material. Similarly, the SGS connections  712 A and  712 B can be coupled to each other, such as through the connection  720 . The connection  720  can include the same material as the SGS connection  712 A or  712 B, such as to form two SGS connections using some of the same material. 
       FIG. 8  shows a circuit diagram  800  of a memory array that includes a configuration similar to the memory array  700 , in accord with one or more embodiments. The circuit diagram  800  shows four strings of memory cells while the memory array  700  shown in  FIG. 7B  only shows two strings of memory cells. 
     The SGD select transistor  806 A includes a gate that can include the SOD connection  706 A. The memory cell  808 A includes a gate that can include the CG connection  708 A. Similarly, the SGS select transistor  810 A includes a gate that can include the SGS connection  710 A and the SGS select transistor  812 A includes a gate that can include the SGS connection  712 A. The channels  804 A-G can be formed in the pillars  704 A-G. The source  814  can include the source  714 . The data line  802 A,  802 E can include the data line  702 A,  702 E, respectively. 
     The strings of memory cells shown in the circuit diagram  800  include an SGD select transistor  806 A or  806 B coupled between a data line  802 A or  802 E, respectively, and a memory cell  808 A or  808 P, respectively. A plurality of memory cells  808 A-H or  808 I-P can be serially coupled to one another. A pass transistor  824  can be coupled between groups of memory cells  808 A-D and  808 E-H (or groups  808 I-L and  808 M-P) of the string (e.g., between memory cells  808 D and  808 E or  808 L and  808 M as shown in  FIG. 8 ). 
     An SGS select transistor  810 A-B is coupled between the memory cell  808 H-I, respectively, and another SGS select transistor  812 A-B, respectively. The SGS select transistor  812 A-B is coupled between the SGS select transistor  810 A-B, respectively, and the source  814 . 
     The SGD select transistor  806 A-B can include a gate coupled to the gate of the SGS select transistor  810 A-B, respectively, such as through a connection  818 . By including such a connection, the number of drive transistors  828  can be reduced as compared to a memory array that does not include a second select transistor coupled between the source  814  and a memory cell  808 A or  808 I. 
     In a P-BICS (a Piped Shaped BICS) memory architecture, such as that shown and described in “Disturbless Flash Memory due to High Boost Efficiency on BiCS Structure and Optimal Memory Film Stack for Ultra High Density Storage Device,” in  IEDM Tech. Dig.,  2008, pp. 851-854, authored by Komori et al., the number of SG drive transistors required is 32 (for a P-BICS with 16 strings of memory cells),  16  for the SGD select transistors between the data line and the memory cells and another sixteen for the SGS select transistors between the source and the memory cells. In contrast, a memory array arranged according to the circuit diagram  800  that includes 16 strings of memory cells can be driven using 17 drive transistors: one per string to drive both a SGD select transistor  806 A and a SGS select transistor  810 A (or both  806 B and  810 B) for a respective string (for a total of 16 drive transistors) and one drive transistor to drive SGS select transistors  812 A-B. Thus, a significant reduction in the number of drive transistors can be realized using the memory array  700  or a memory array configured according to the circuit diagram  800 . 
       FIG. 9A  shows a planar view block diagram of a memory array  900 , in accord with one or more embodiments.  FIG. 9B  shows a planar view block diagram of the memory array  900  of  FIG. 9A , in accord with one or more embodiments. The memory array  900  can be similar to the memory array  700  of  FIGS. 7A and 7B  with the memory array  900  including a second. SGD connection  922 A or  922 B between the data line  902 A or  902 E and the CG connection  908 A or  908 P, respectively. 
     The memory array  900  can include data lines  902 A,  902 B,  902 C,  902 D, and  902 E, pillars  904 A,  904 B,  904 C,  904 D, and  904 E, SGD connections  906 A and  906 B, CG connections  908 A,  908 B,  908 C,  908 D,  908 E,  908 F,  908 G,  908 H,  908 I,  908 J,  908 K,  908 L,  908 M,  908 N,  908 O, and  908 P, SGS connections  910 A and  910 B, SGS connections  912 A and  912 B, and a source  914 . The memory array  900  of  FIG. 9B  shows two strings of memory cells. Each string can include a U-shaped pillar  904 A-E, a first SGD select transistor coupled to a first SOD connection  922 A-B, a second SGD select transistor coupled to a second SGD connection  906 A-B, a plurality of memory cells coupled to CG connections  908 A-P, a first SGS select transistor coupled to a first SGS connection  910 A-B, and a second. SGS select transistor coupled to a second SGS connection  912 A-B. 
     A data line  902 A-E can be coupled to one or more pillars  904 A-E. Each CG connection of a subset of CG connections  908 E-H can be coupled to a respective CG connection of a corresponding subset of CG connections  908 I-L, such as through the connections  916 . The connections  916  can include a conductive material such as a metal or a semiconductor. The connections  916  can include the same material as the CG connections  908 E-L, such as to form two CG connections using some of the same material. Similarly, the SGD connection  906 A-B can be coupled to a respective SGS connection  910 A-B, such as through the connection  918 . The connection  918  can include the same material as the SG connection  906 A-B or  910 A-B, such as to form two SG connections using some of the same material. Similarly, the SGS connections  912 A and  912 B can be coupled to each other, such as through the connection  920 . The connection  920  can include the same material as the SGS connection  912 A or  912 B, such as to form a connection between two SGS connections using some of the same material. 
     The memory array  900  can include SOI) connections  922 A-B. The SOD connections  922 A-B can be between the data lines  902 A and  902 E and the SOD connections  906 A and  906 B, respectively, such as shown in  FIG. 9A or 9B . 
       FIG. 10  shows a circuit diagram  1000  of a memory array that is configured similar to the memory array  900 , in accord with one or more embodiments. The circuit diagram  1000  shows four strings of memory cells, while the memory array  900  depicted in  FIG. 9A or 9B  only shows two strings of memory cells. A string of memory cells configured in accord with the circuit diagram  1000  can include two SGD select transistors (e.g., an SGD select transistor  1006 A-B and an SGD select transistor  1022 A-B) coupled between a data line  1002 A and  1002 E and a memory cell  1008 A and  1008 P, respectively. 
     The SGD select transistor  1006 A of a string includes a gate that can include the SOI) connection  906 A. The memory cell  1008 A of the string include gates that can include the CG connection  908 A. Similarly, the SGS select transistor  1010 A includes a gate that can include the SGS connection  910 A and the SGS select transistor  1012 A includes a gate that can include the SGS connection  912 A. A channel  1004  can be formed in the pillar  904 . The source  1014  can include the source  914 . The data line  1002 A can include the data line  902 A. 
     A string of memory cells in the circuit diagram  1000  can include a SGD select transistor  1022 A-B coupled between a SGD select transistor  1006 A-B and a data line  1002 A and  1002 E, respectively. The SGD select transistor  1006 A-B can be coupled between the SGD select transistor  1022 A-B and a memory cell  1008 A and  1008 P, respectively. A plurality of memory cells  1008 A-H and  1008 I-P can be coupled in series between the SGD select transistor  1006 A-B and an SGS select transistor  1010 A-B, respectively. A pass transistor  1024  can be coupled between two groups of the memory cells of a string, such as shown in  FIG. 10 . 
     The SGS select transistor  1010 A-B can be coupled between a memory cell  1008 H-I and another SGS select transistor  1012 A-B, respectively. The SGS select transistor  1012 A-B can be coupled between the SGS select transistor  1010 A-B, respectively, and the source  1014 . 
     The SGD select transistor  1006 A-B of a string can include a gate coupled to the gate of the SGS select transistor  1010 A-B of the string, such as through a connection  1018 . The SGD select transistor  1022 A-B of a string can include a gate coupled to a gate of the SGD select transistor  1022 A-B of another string, such as through a SGD connection  1026 . By including the SGD connection  1026  and the SGD select transistor  1022 A-B, the number of SG drive transistors  1028  can be reduced as compared to a memory array that does not include a second select transistor coupled between the data line and the memory cell. The number of drive transistors  1028  required to drive a memory array configured in accord with the circuit diagram  1000  that includes sixteen strings of memory cells (two sets of eight strings of memory cells that mirror each other and include some of the same drive transistors) can be eleven as follows: 1) one for each SGD select transistor  1006 A-B, which also serves as a driver for the SGS select transistor  1010 A-B that is coupled to the SGD select transistor  1006 A-B for a total of eight drive transistors; 2) one drive transistor for each half of the SGD select transistors  1022 A-B for a total of two drive transistors; and 3) one drive transistor to drive the SGS select transistors  1012 A-B of all sixteen strings of memory strings. See the discussion with regard to  FIG. 8  for the number of drive transistors required for similar circuits. 
       FIG. 11  shows a table  1100  of decoder logic states, in accord with one or more embodiments. The table  1100  depicts, by way of example, how a decoder (e.g., decoder  308 ) can determine which drive transistors to activate to perform an access (e.g., a read or program) operation on a desired string. According to the table  1100 , to access string “1”, for example, DT0 (drive transistor “0”) would be activated (e.g., to activate both the select transistors  1006 B and  1010 B), DT2 would be activated (e.g., to activate both the SGD select transistors  1022 A and  1022 B), and DT4 would be activated (e.g., to activate the SGS select transistors  1012 A-B). Accordingly, a decoder can cause a unique set of DT states to, for example, read or program a particular memory cell or string of memory cells. 
       FIG. 12  shows a flow diagram of a method  1200  of performing a read operation using a memory array that includes at least two select transistors coupled between a source and a memory cell of a string (e.g., a memory array configured in accord with the circuit diagram  500 ,  600 ,  800 , or  1000 ), in accord with one or more embodiments. The method  1200  as illustrated includes: at operation  1202 , precharging channels of strings of memory cells (of a selected block of memory cells) to a precharge voltage; at operation  1204 , driving gates of select transistors of an unselected string of memory cells to cut-off; at operation  1206 , driving a control gate of a selected memory cell to a read voltage; and at operation  1208 , determining the stored data value of a memory cell based on a signal (e.g., a voltage or current signal) on a data line. 
     The operation at  1202  can include precharging (e.g., boosting) the channels of a selected block (e.g., one or more memory cells) through data lines. A data line can be coupled to the memory cells of a respective string by activating a corresponding SGD select transistor(s). The operation at  1204  can include driving control gates of a plurality of select transistors of an unselected string of memory cells to a reference voltage (e.g., V ss ) to inactivate the unselected select transistors, thereby cutting off the channel of the unselected string of memory cells. 
     The method  1200  can also include driving control gates of unselected memory cells of a string to a read_pass voltage greater than the read voltage. The method  1200  can further include driving a source to the reference voltage. Also, the method  1200  can include driving gates of the select transistors of a selected string(s) to a voltage sufficient to activate the select transistors (e.g., V cc ) of the selected string in response to (e.g., after or shortly after, such as on the order of nanoseconds) the control gate of the selected memory cell being driven to the read voltage. 
       FIG. 13A  shows a wave diagram of a read operation  1300 A using a memory array, such as the memory array  300 A,  300 B, the memory array  400 A-C,  700 , or  900 , or a memory array configured in accordance with the circuit diagram  500 ,  600 ,  800 , or  1000 , in accord with one or more embodiments. While  FIG. 13A  illustrates reference numbers of  FIG. 7 , it will be understood that the waveforms illustrated show a general read waveform for a selected block of memory cells having strings that include at least two select transistors coupled between the source and a memory cell. The waveform of  FIG. 13A  can depict some aspects of the method  1200 . 
     Pillars of a selected block can be driven from corresponding data lines so as to precharge the channels of the memory cells of the selected block. The channels of unselected strings of the block can be driven to float, such as by driving the control gate of the SGD select transistor (e.g.,  706 B) and the commonly coupled control gate of one of the SGS select transistor (e.g.,  710 B) of each unselected string to a reference voltage (e.g., V ss  or other reference voltage), so that the channels of the unselected strings can be cut-off during data line sensing. According to at least one of the disclosed embodiments, as a result, the leakage current through the SGD select transistors of the unselected strings can be at least partially suppressed. The channels of the unselected strings can be boosted by the CGs of the selected block, such as when they are driven to a pass_read and/or read voltage (e.g., a V pass_read  or V read , such as shown in  FIG. 13A ). An advantage of performing such an operation, in accord with at least one of the disclosed embodiments, can include reduced read disturbance. 
       FIG. 13B  shows a wave diagram of another read operation  1300 B using a memory array, such as the memory array  300 A,  300 B, the memory array  400 A-C,  700 , or  900 , or a memory array configured in accord with the circuit diagram  500 ,  600 ,  800 , or  1000 , in accord with one or more embodiments. While  FIG. 13B  illustrates reference numbers of  FIG. 7 , it will be understood that the waveforms illustrated show a general read waveform for a selected block of memory cells including strings having two select transistors coupled between the source and a memory cell. The waveform of  FIG. 13B  can depict some aspects of the method  1200 . 
     Pillars of a selected block can be driven from the data lines of the selected block so as to precharge the channels of memory cells of the selected block. The channels of unselected strings of the block can be driven to float, such as by applying a reference voltage (e.g. V ss ) to the control gates of SGD and SGS select transistors of the unselected strings, so that the channels of the unselected strings can be cut-off during data line sensing. According to at least one of the disclosed embodiments, as a result, the leakage current through the unselected SGD select transistors can be suppressed. The unselected pillar channels can be boosted by the CGs, such as through application of a voltage to such CGs (e.g., V pass_read  or V read , such as shown in  FIG. 13B ). An advantage of performing such an operation, in accord with at least one of the disclosed embodiments, can include reduced read disturbance. 
     Some differences between the wave diagram  1300 A and the wave diagram  1300 B include not temporarily reducing the voltages on the CGs of the memory cells and selected SGD select transistors after driving those gates to a voltage higher than V ss  (e.g., V cc ). For example, as shown in  FIG. 13B , the CGs of the memory cells of the selected block are driven to V pass_read  instead of V cc , after which the voltage on the CG of the selected memory cell is reduced to V read . Also, the voltage on the gate of the SGD select transistor(s) of the selected string is maintained at V cc  instead of temporarily reducing it to V ss . An advantage of performing an embodiment such as that discussed with respect to  FIG. 13B  may be realized in circumstances where the threshold voltage of the cell selected to be read is higher than V cc  (where performing an embodiment such as that discussed with respect to  FIG. 13A  may lead to the channel of the selected cell not being sufficiently precharged). 
       FIG. 14  shows a flow diagram of a method  1400  of performing a program operation on a selected block of memory array that includes strings having at least two select transistors coupled between a source and a memory cell (e.g., memory array  300 A or  300 B or memory array  400 A-C,  700 , or  900  or a memory array configured in accordance with the circuit diagram  500 ,  600 ,  800 , or  1000 ), in accord with one or more embodiments. The method  1400  as illustrated includes: at operation  1402 , selectively precharging channels of memory cells to a voltage selected from the group comprising at least one of a program enable voltage (e.g., V ss  or ground) and a program inhibit voltage (e.g., V cc ) or other voltage intermediate to the program inhibit voltage and the program enable voltage, such as a Selective Slow Programming Convergence (SSPC) voltage; at operation  1404 , driving gates of a plurality of select transistors of an unselected string of memory cells with a single drive transistor to cut-off the channel of the unselected string of memory cells; and, at operation  1406 , driving a gate of a selected memory cell of a selected string of memory cells to a program voltage to program the selected memory cell. 
     SSPC can account for preexisting charges present on a given connection. SSPC can be used when programming a memory cell or block of memory cells. Using SSPC, a memory cell is programmed with incrementally increased programming pulses applied to CG connections to which the memory cell is coupled. After each pulse, a verify operation can help determine the threshold voltage for the cell. When the threshold voltage reaches a pre-verify threshold, the data connected to that particular cell can be biased with an intermediate voltage that slows down the change in the threshold voltage of the cell. Other memory cells can continue to be programmed at their normal pace. As the threshold voltage for each cell reaches the pre-verify level, it is biased with the intermediate voltage. The data lines can be biased with an inhibit voltage as the cell threshold voltage reaches the verify voltage threshold. 
     The operation at  1402  can include precharging the channels through data lines. The data lines can be coupled to the channels of a block of memory cells by activation of the SGD select transistors. The program voltage (e.g., V program ) can be greater than both the program enable and program inhibit voltages. 
     The method  1400  can also include driving CGs of unselected memory cells of the strings to a pass_program voltage less than the program voltage. The method  1400  can further include driving a source from a first reference voltage (e.g., V ss ) to a second reference voltage (e.g., V cc ) prior to driving the control gates of the memory cells to the pass_program voltage. 
       FIG. 15  shows a wave diagram of a program operation  1500  using a memory array, such as the memory array  300 A,  300 B, the memory array  400 ,  700 , or  900 , or a memory array configured in accord with the circuit diagram  500 ,  600 ,  800 , or  1000 , in accord with one or more embodiments. While  FIG. 15  illustrates reference numbers of  FIG. 7 , it will be understood that the waveforms illustrated show a general program waveform for a selected block of a memory array including two select transistors coupled between the source and a memory cell. The channels of the selected block can be driven from the data lines so as to selectively precharge channels of memory cells of the selected block. SGD and SGS select transistors of the unselected strings can then be cut-off to allow the channels of the unselected strings of memory cells to float during programming. The waveform of  FIG. 15  can depict some aspects of the method  1400 . 
     An advantage of using a string of memory cells as discussed herein can include not increasing the number of drive transistors required to drive select transistors of the string of memory cells while maintaining or increasing channel selectivity. The leakage current through unselected channels can be reduced so that a number of faulty read operations can be reduced. For example, the read disturbance or the leakage current can be reduced. An advantage can include a read power reduction, such as in embodiments where the unselected channels can be floating. Similarly, a time to perform a read or program operation can be reduced, such as in embodiments where unselected channels can be floating. 
     While the above description and drawings illustrate some embodiments of strings of memory cells using n-type logic, it will be understood that p-type logic could be used in creating such strings of memory cells. Also, while the above description and drawings illustrate some strings of memory cells with certain numbers of memory cells, it will be understood that more or fewer memory cells can be included in a string of memory cells. Typically, the number of memory cells in a string is a power of two, such as two, four, eight, sixteen, thirty-two, sixty-four, etc., but different numbers of memory cells can be included in a string. The number of strings of memory cells in a block of memory can likewise be increased or decreased. An apparatus or device, as described herein, can refer to any of a system, device, die, circuit, or the like. 
     The above description and the drawings illustrate some embodiments to enable those skilled in the art to practice the embodiments of the invention. Other embodiments may incorporate structural, logical, electrical, process, and other changes. Examples merely typify possible variations. Portions and features of some embodiments may be included in, or substituted for, those of other embodiments. Many other embodiments will be apparent to those of skill in the art upon reading and understanding the above description.