Patent Publication Number: US-7906955-B2

Title: On-chip current sensing methods and systems

Description:
CROSS REFERENCED TO RELATED APPLICATIONS 
     This application is a continuation of U.S. patent application Ser. No. 11/707,023, filed on Feb. 16, 2007, which claims the benefit of U.S. Provisional Patent Application No. 60/809,393, filed May 31, 2006, both of which are incorporated herein by reference in their entirety. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates generally to circuitry, and more specifically to circuitry that senses a current. 
     2. Background 
     Portable electronic devices are becoming increasingly popular in the marketplace. Such portable devices often include a low power switch regulator, which includes power conversion circuitry and other mixed-signal circuitry. A variety of techniques have been employed to improve the performance of conventional switch regulators. A trend in the industry is to integrate the power conversion circuitry and the other mixed signal circuitry on the same substrate to improve efficiency. Current sensing is another technique that may be used to improve the performance of a switch regulator. For example, an integrated switch-mode converter of the switch regulator may be configured to sense a current of the portable electronic device. Several conventional current sensing techniques are available. However, each of these techniques has problems that may render the respective techniques inadequate and/or undesirable for at least some applications. 
     Many conventional techniques sense current by incorporating a serial resistor in the path of the current. For instance, a first conventional technique uses an off-chip resistor coupled in series with an inductor to sense the current of the inductor. However, this technique requires the entire current of the inductor to flow through the resistor. For this and other reasons, the first conventional technique is characterized by a relatively high power dissipation. Moreover, additional input/output (I/O) pins and board routing are needed for implementation of this technique. 
     In a second conventional technique, a resistor is coupled in series with a main power switch. The drain current of the main power switch flows through the resistor, enabling the drain current to be sensed. However, this technique is characterized by relatively low efficiency. For example, the resistor used in the second conventional technique needs to be large enough to provide sufficient swing for further analog signal processing. 
     What is needed is a system and method that addresses one or more of the aforementioned shortcomings of conventional current sensing techniques. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS/FIGURES 
       The accompanying drawings, which are incorporated herein and form part of the specification, illustrate embodiments of the present invention and, together with the description, further serve to explain the principles of the invention and to enable a person skilled in the pertinent art(s) to make and use the invention. 
         FIG. 1  is a schematic representation of an example switch regulator module, according to an embodiment of the present invention. 
         FIG. 2  is an example implementation of the switch regulator module shown in  FIG. 1 , according to an embodiment of the present invention. 
         FIG. 3  shows a portion of the switch regulator module of  FIG. 2 , according to an example embodiment of the present invention. 
         FIG. 3A  shows a portion of the switch regulator module of  FIG. 2 , according to another example embodiment of the present invention. 
         FIG. 4  shows example waveforms associated with the switch regulator module of  FIG. 2 , according to an embodiment of the present invention. 
         FIG. 5  is a timing diagram according to an embodiment of the present invention. 
         FIG. 6  is a flowchart of a method of sensing a current according to an embodiment of the present invention. 
     
    
    
     In the drawings, like reference numbers indicate identical or functionally similar elements. Additionally, the leftmost digit(s) of a reference number identifies the drawing in which the reference number first appears. 
     DETAILED DESCRIPTION OF THE INVENTION 
     Although the embodiments of the invention described herein refer specifically, and by way of example, to portable electronic devices and components thereof, including low power switch regulators, it will be readily apparent to persons skilled in the relevant art(s) that the invention is equally applicable to other devices and systems. It will also be readily apparent to persons skilled in the relevant art(s) that the invention is applicable to any apparatus or system requiring switch regulation. 
     This specification discloses one or more embodiments that incorporate the features of this invention. The embodiment(s) described, and references in the specification to “one embodiment”, “an embodiment”, “an example embodiment”, etc., indicate that the embodiment(s) described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described. 
       FIG. 1  is a schematic representation of an example switch regulator module  100 , according to an embodiment of the present invention. Switch regulator module  100  includes a P-type switch  102 , an N-type switch  104 , an impedance  106 , a resistor  108 , a capacitor  110 , a current sensing module  112 , an optional transimpedance amplifier  114 , and a switch driver  116 . P-type switch  102  and N-type switch  104  are shown as field effect transistors (FETs) for illustrative purposes and are not intended to limit the scope of the present invention. P-type switch  102  and N-type switch  104  may be any type of transistor, including but not limited to high electron mobility transistor (HEMT), bipolar junction transistor (BJT), etc. 
     In  FIG. 1 , when P-type switch  102  is “on” and N-type switch  104  is “off”, current sensing module  112  senses the voltage dV across the source and drain terminals of P-type switch  102  to determine the current dI that flows through P-type switch  102 . Current sensing module  112  provides a sense current dI sense  based on the current dI without the need for conventional current sensing techniques. Switch regulator module  100  is shown to include transimpedance amplifier  114  for illustrative purposes, though the scope of the present invention is not limited in this respect. For instance, switch regulator module  100  need not necessarily include transimpedance amplifier  114 . Transimpedance amplifier  114  provides a sense voltage V sense     —     out  based on the sense current dI sense  in switch regulator module  100 . 
     Referring to  FIG. 1 , an input voltage V in  is received at node  118 , which is coupled to a source of P-type switch  102 . A node  120  is coupled to a drain of P-type switch  102 . Impedance  106  is coupled between node  120  and an output node  128 . N-type switch  104  is coupled between node  120  and a ground potential. Resistor  108  and capacitor  110  are coupled in series between output node  128  and the ground potential. In  FIG. 1 , resistor  108  is not a physical resistor. Instead, resistor  108  represents the equivalent resistance of capacitor  110 . 
     Switch driver  116  is coupled between a gate of P-type switch  102  and a gate of N-type switch  104  to control the “on” and “off” states of respective switches  102  and  104 . Switch driver  116  turns on P-type switch  102  in response to turning off N-type switch  104 . Switch driver  116  sets the duty cycle of P-type switch  102  based on the proportion of time that P-type switch  102  is turned on. Switch driver  116  turns on N-type switch  104  in response to turning off P-type switch  102 . Switch driver  116  sets the duty cycle of N-type switch  104  based on the proportion of time that N-type switch  104  is turned on. Turning on P-type switch  102  and N-type switch  104  at the same time would cause a shoot-through current, effectively short-circuiting V in  to the ground potential. Accordingly, switch driver  116  is configured to ensure that P-type switch  102  and N-type switch  104  are not turned on at the same time. 
     Current sensing module  112  is coupled to nodes  118  and  120 . Current sensing module  112  senses input voltage V in  at node  118  and another voltage V′ at node  120  and provides sense current dI sense  to transimpedance amplifier  114  based on the difference between V in  and V′. In  FIG. 1 , transimpedance amplifier  114  is shown to be external to current sensing module  112  for illustrative purposes. However, persons skilled in the relevant art(s) will recognize that current sensing module  112  can include transimpedance amplifier  114 . 
     Switch regulator module  100  is shown as a buck regulator for illustrative purposes and is not intended to limit the scope of the present invention. Persons skilled in the relevant art(s) will recognize that the present invention is applicable to all types of regulators, including but not limited to boost regulators. It will also be recognized that switch regulator module  100  need not necessarily be a regulator. 
       FIG. 2  is an example implementation of switch regulator module  100  shown in  FIG. 1 , according to an embodiment of the present invention. In  FIG. 2 , current sensing module  112  is shown to include transimpedance amplifier  114  for illustrative purposes. Current sensing module  112  further includes timing control module  220 , transistors  202 ,  204   a , and  204   b , and a current amplifier  208 . Timing control module  220  is coupled to switch driver  116 , a gate of transistor  204   a , and a gate of transistor  204   b . A source of transistor  204   a  is coupled to node  120 , and a drain of transistor  204   a  is coupled to node B of current amplifier  208 . A source of transistor  204   b  is coupled to node  118 , and a drain of transistor  204   b  is coupled to node B of current amplifier  208 . A source of transistor  202  is coupled to node  118 , and a drain of transistor  202  is coupled to node A of current amplifier  208 . A gate of transistor  202  is coupled to a ground potential. 
     Referring to  FIG. 2 , timing control module  220  and transistor  204   b  are configured to maintain a known voltage at node B of current amplifier  208  when P-type switch  102  is turned off. For example, the voltage at node B of current amplifier  208  may be substantially the same when P-type switch  102  is turned on and when P-type switch  102  is turned off. Timing control module  220  turns on transistor  204   a  and turns off transistor  204   b  when switch driver  116  turns off N-type switch  104  and turns on P-type switch  102 . Timing control module  220  turns off transistor  204   a  and turns on transistor  204   b  before switch driver  116  turns off P-type switch  102  and turns on N-type switch  104 . 
     In  FIG. 2 , current amplifier  208  is shown to include transistors  212 ,  214 , and  216  and current sources  218   a, b , and  c , though the scope of the present invention is not limited in this respect. Current amplifier  208  may have any of a variety of circuit implementations, as will be recognized by persons skilled in the relevant art(s). Current amplifier  208  senses a voltage V B  at node B and sets the voltage V A  at node A to be substantially equal to V B . For example, current amplifier  208  may set V A  by driving node C appropriately. 
     Referring to  FIG. 2 , a source of transistor  212  is coupled to node A. A gate of transistor  212  is coupled to a drain of transistor  212  and to a gate of transistor  214 . A source of transistor  214  is coupled to node B of current amplifier  208 . A drain of transistor  214  is coupled to node C. Current source  218   a  is coupled between the drain of transistor  212  and a ground potential. Current source  218   b  is coupled between node C and the ground potential. 
     Node C is further coupled to a gate of transistor  216 . A source of transistor  216  is coupled to node A, and a drain of transistor  216  is coupled to node D. Current source  218   c  is coupled between node D and the ground potential. 
     According to the embodiment of  FIG. 2 , current sources  218   a - c  are configured such that current I 2  is substantially equal to the sum of I 1  and I 3  (i.e., I 2 =I 1 +I 3 ). In this embodiment, the feedback loop formed by transistors  212 ,  214 , and  216  may have relatively high bandwidth and/or give relatively fast response to current variation with relatively low power dissipation, as compared to conventional current sensing techniques. 
     Referring to  FIG. 2 , the drain-to-source resistance of P-type switch  102  is represented as R ds1 . Transistors  202  and  204   a  have drain-to-source resistances that are represented as R ds2  and R ds3 , respectively. The voltage V A  at node A may be represented as
 
 V   A   =V   in −( I   1   +I   3 )* R   ds2 .  (Equation 1)
 
The voltage V B  at node B may be represented as
 
 V   B   =V   in   −dI*R   ds1   −I   2   *R   ds3 .  (Equation 2)
 
In the embodiment of  FIG. 2 , the static voltage across transistor  202  is the same as the static voltage across transistor  204   a  when the sense current I sense  equals zero. When current amplifier performs properly, voltages V A  and V B  are the same. Accordingly,
 
 V   A   =V   B   =V   in   −dI*R   ds1   −I   2   *R   ds3   (Equation 3)
 
and the sense current dI sense  may be represented as
 
 dI   sense =( V   in   −V   A )/ R   ds2 −( I   1   +I   3 ).  (Equation 4)
 
     In the embodiment of  FIG. 2 , transistors  202  and  204   a  have the same device size (i.e., the same gate length L and gate width W), and I 2 =I 1 +I 3 . Substituting Equation 3 into Equation 4 and incorporating the above-described relationships provides: 
     
       
         
           
             
               
                 
                   
                     dI 
                     sense 
                   
                   = 
                   
                     dI 
                     ⋆ 
                     
                       
                         
                           R 
                           
                             ds 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             1 
                           
                         
                         
                           R 
                           
                             ds 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             2 
                           
                         
                       
                       . 
                     
                   
                 
               
               
                 
                   ( 
                   
                     Equation 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     5 
                   
                   ) 
                 
               
             
           
         
       
     
     Referring to  FIG. 2 , transimpedance amplifier  114  includes a variable resistor  226  and an amplifier  228 . Amplifier  228  has an inverting node  222 , a non-inverting node  224 , and an output node  230 . Variable resistor  226  is coupled between inverting node  222  and output node  230 . Non-inverting node  224  is coupled to a common mode potential. Current sensing module  112  provides the sense current dI sense  at inverting node  222 . Sense current dI sense  flows through variable resistor  226 , thereby setting the sense voltage V sense     —     out . Using Equation 5 for dI sense , the sense voltage V sense     —     out  may be represented as: 
                     V   sense_out     =         dI   sense     ⋆     R   fb       =     dI   ⋆       R     ds   ⁢           ⁢   1         R     ds   ⁢           ⁢   2         ⋆       R   fb     .                 (     Equation   ⁢           ⁢   6     )               
Variable resistor  114  may be a poly resistor, though the scope of the present invention is not limited in this respect. As shown in Equation 6, the sense voltage V sense     —     out  is proportional to the ratio between the drain-to-source resistance R ds1  of P-type switch  102  and the drain-to-source resistance R ds2  of transistor  202 .
 
     In  FIG. 2 , transistors  202 ,  204   a - b ,  212 ,  214 , and  216  are shown as field effect transistors (FETs) for illustrative purposes. However, the scope of the present invention is not limited in this respect. Persons skilled in the relevant arts will recognize that transistors  202 ,  204   a - b ,  212 ,  214 , and  216  may be of any type, including but not limited to high electron mobility transistor (HEMT), bipolar junction transistor (BJT), etc. 
     Referring now to  FIGS. 3 and 3A , one or more switches and/or transistors of switch regulator module  100  may include a plurality of transistors. The plurality of transistors may be coupled in parallel, series, cascade, cascode, or any combination thereof, to provide some examples. Transistors that are coupled in parallel have a lower on-resistance, as compared to a single transistor. Transistors that are coupled in series have a higher on-resistance and a greater operating range, as compared to a single transistor. Transistors that are cascade-coupled have a higher voltage tolerance, as compared to a single transistor. 
     In  FIG. 3 , switches  102  and  104  are each shown to be a plurality of cascode-coupled transistors for illustrative purposes. Switch  102  includes transistors  302   a  and  302   b , each of which may have a rated voltage beyond which its performance diminishes. Cascode-coupling transistors  302   a  and  302   b  may enable the combination of transistors  302   a  and  302   b  to be used at voltages beyond the rated voltage of transistor  302   a  or  302   b  alone. Switch  104  includes transistors  304   a  and  304   b , the cascode-coupled combination of which may be capable of proper operation at voltages beyond the rated voltage of transistor  304   a  or  304   b  alone. 
     Transistors  202  and  204   a  are each shown to be a plurality of series-connected transistors for illustrative purposes. Transistor  202  includes transistors  306   1  through  306   n . Transistor  204   a  includes transistors  308   1  through  308   n . In the embodiment of  FIG. 3 , transistors  306   1 - 306   n  and  308   1 - 308   n  are each based on a unit element, which is defined as an element having a unit gate length L and a unit gate width W. Transistors  306   1 - 306   n  and  308   1 - 308   n  can each include any number of unit elements in any of a variety of configurations. 
     In  FIG. 3 , the unit element is based on the size of P-type switch  102 . For example, each of transistors  306   1 - 306   n  and  308   1 - 308   n  may be the same size as P-type switch  102 , meaning that each of transistors  306   1 - 306   n  and  308   1 - 308   n  includes the same number of unit elements as P-type switch  102  in the same configuration as P-type switch  102 . In another example, one or more of transistors  306   1 - 306   n  and  308   1 - 308   n  may include a number of unit elements that is different from the number of unit elements included in P-type switch  102 . In yet another example, one or more of transistors  306   1 - 306   n  and  308   1 - 308   n  may include unit elements having a configuration that is different from the configuration of the unit elements in P-type switch  102 . As suggested above, each of transistors  306   1 - 306   n  or  308   1 - 308   n  need not necessarily have the same configuration. Transistor  202  is configured to have enough series-connected transistors  306  to provide sufficient dynamic range for current sensing module  112 . 
     In  FIG. 3A , transistors  302   a ,  302   b ,  304   a , and  304   b  are each shown to be a plurality of parallel-coupled transistors for illustrative purposes. Transistors  302   a  and  302   b  include transistors  302   a   1  through  302   a   m  and  302   b   1  through  302   b   m , respectively. Transistors  304   a  and  304   b  include transistors  304   a   1  through  304   a   m  and  304   b   1  through  304   b   m , respectively. In the embodiment of  FIG. 3A , transistors  302   a   1 - 302   a   m ,  302   b   1 - 302   b   m ,  304   a   1 - 304   a   m , and  304   b   1 - 304   b   m  are each based on the same unit element. Transistors  302   a   1 - 302   a   m ,  302   b   1 - 302   b   m ,  304   a   1 - 304   a   m , and  304   b   1 - 304   b   m  can each include any number of unit elements in any of a variety of configurations. 
     According to some embodiments, basing transistors and/or switches on the same unit element may enable process and/or temperature variation between the transistors and/or switches to be cancelled in the first order. For example, process and/or temperature variation between P-type switch  102  and transistor  202  may be cancelled in the first order by basing P-type switch  102  and transistor  202  on the same unit element. Referring to  FIGS. 3 and 3A , the unit element on which transistors  302   a   1 - 302   a   m ,  302   b   1 - 302   b   m ,  304   a   1 - 304   a   m , and  304   b   1 - 304   b   m  are based may be the same as the unit element on which transistors  306   1 - 306   n  and  308   1 - 308   n  are based. It should be noted that the examples described herein are provided for illustrative purposes and are not intended to limit the scope of the present invention. 
       FIG. 4  shows example waveforms associated with the switch regulator module  100  of  FIG. 2 , according to an embodiment of the present invention. 
     Waveform  410  shows the current dI that flows through P-type switch  102  and impedance  106 . Waveform  420  shows the sense current dI sense , as determined by current sensing module  112 . Waveform  430  shows the sense voltage V sense     —     out , which is provided at node  230  of switch regulator module  100 . 
     Referring to  FIG. 4 , a trigger event occurs at approximately 140 ns along the time axis, causing the current dI that flows through impedance  106  and the sense current dI sense  to return to approximately zero amps, as shown in respective waveforms  410  and  420 . As shown in waveform  430 , the trigger event further causes the sense voltage V sense     —     out  to return to a substantially constant magnitude. The trigger event need not occur at the time shown in  FIG. 4  and may occur at any time. 
     The trigger event can be based on any of a variety of factors, including but not limited to load current, desired output voltage, and/or input voltage. For example, the trigger event may occur when dI sense  reaches a threshold. In  FIG. 4 , the trigger event is shown to occur when dI sense  is approximately 7.6 μA. In this example, the trigger event may be set to occur when dI sense  reaches 7.6 μA. In another example, the trigger event may occur when V sense     —     out  reaches a threshold. In  FIG. 4 , the trigger event is shown to occur when V sense     —     out  is approximately 1.26 V. In this example, the trigger event may be set to occur when V sense     —     out  reaches 1.26 V. The values for dI sense  and V sense     —     out  in  FIG. 4  are provided for illustrative purposes and are not intended to limit the scope of the present invention. 
       FIG. 5  is a timing diagram according to an embodiment of the present invention. In  FIG. 5  and with reference to switch regulator module  100  of  FIG. 1 , P 1  and P 2  represent the signals that switch driver  116  uses to control the respective gates of P-type switch  102  and N-type switch  104 . P 1   a  and P 1   ba  represent the signals that timing control module  220  uses to control the respective gates of transistor  204   a  and transistor  204   b.    
     As shown in  FIG. 5 , P 1  and P 1   a  are initially “high”, indicating that P-type switch  102  and transistor  204   a , respectively, are turned off. P 2  is initially high, indicating that N-type switch  104  is turned on. P 1   ba  is initially “low”, indicating that transistor  204   b  is turned on. At time t 1 , switch driver  116  sets P 2  at a low state, thereby turning off N-type switch  104 . At time t 2 , switch driver  116  sets P 1  at a low state, thereby turning on P-type switch  102 . At time t 3 , timing control module  220  sets P 1   a  at a low state and sets P 1   ba  at a high state, thereby turning on transistor  204   a  and turning off transistor  204   b.    
     A trigger event occurs at time t 4 . At time t 5 , in response to the trigger event, timing control module  220  sets P 1   a  at a high state and sets P 1   ba  at a low state, thereby turning off transistor  204   a  and turning on transistor  204   b . At time t 6 , switch driver  116  sets P 1  at a high state, thereby turning off P-type switch  102 . At time t 7 , switch driver  116  sets P 2  at a high state, thereby turning on N-type switch  104 . 
     Referring to  FIG. 5 , d 1  through d 5  represent delays, the respective durations of which may be represented as d 1 =t 2 −t 1 , d 2 =t 3 −t 2 , d 3 =t 5 −t 4 , d 4 =t 6 −t 5 , and d 5 =t 7 −t 6 . Delay d 1  is implemented to allow N-type switch  104  to turn off sufficiently before P-type switch  102  is turned on at t 2 . Delay d 2  is implemented to allow a transient voltage glitch associated with P-type switch  102  to settle (e.g., stop ringing) before transistors  204   a - b  are toggled at t 3 . Delay d 3  is the time period between the occurrence of the trigger event at t 4  and the toggling of transistors  204   a - b  at t 5 . Delay d 4  is implemented to allow transistors  204   a - b  to sufficiently change respective states before P-type transistor  102  is turned off at t 6 . Delay d 5  is implemented to allow P-type switch  102  to turn off sufficiently before N-type switch  104  is turned on at t 7 . 
       FIG. 6  illustrates a flowchart  600  of a method of sensing a current that flows through a switch in accordance with an embodiment of the present invention. The invention, however, is not limited to the description provided by the flowchart  600 . Rather, it will be apparent to persons skilled in the relevant art(s) from the teachings provided herein that other functional flows are within the scope and spirit of the present invention. 
     Flowchart  600  will be described with continued reference to switch regulator module  100  described above in reference to  FIG. 2 , though the method is not limited to that embodiment. 
     Referring now to  FIG. 6 , a first voltage is sensed at an input port of a switch at block  610 . For example, transistor  202  may sense the first voltage at node  118  of switch regulator module  100 . A second voltage is sensed at an output port of the switch at block  620 . For instance, transistor  204   a  may sense the second voltage at node  120  of switch regulator module  100 . At block  630 , a sense current that is proportional to the current that flows through the switch is generated based on the first voltage and the second voltage. For example, current amplifier  208  may generate the sense current that is proportional to the current that flows through switch  102  based on the first voltage and the second voltage. As shown a block  640 , a sense voltage optionally is generated based on the sense current. For instance, transimpedance amplifier  114  may generate the sense voltage. 
     Referring back to block  630  of  FIG. 6 , a sense current is shown to be generated for illustrative purposes. However, the invention is not limited in this respect. It will be apparent to persons skilled in the relevant art(s) that any signal that is proportional to the current that flows through the switch may be generated. For example, the signal may be a voltage. 
     The current sensing techniques described herein may provide lower power dissipation and/or higher efficiency, as compared to conventional current sensing techniques. These current sensing techniques may be relatively easy to implement and may provide relatively fast sensing of the current that flows through P-type switch  102 . Transistors  202  and  204   a  may be configured to substantially reduce or cancel process and/or temperature variations associated with P-type switch  102 . Embodiments of the present invention may be capable of tolerating a relatively high input voltage range without using high voltage tolerant devices. Switch regulator module  100  may be easily scaled with higher switching frequency by adjusting the current of current amplifier  208 . Embodiments of the present invention may be incorporated into any of a variety of applications, including but not limited to over-current protection and/or current programming. For instance, switch regulator module  100  may be configured to switch to relatively bigger devices if the sense current dI sense  exceeds a threshold. 
     CONCLUSION 
     Example embodiments of the methods, systems, and components of the present invention have been described herein. As noted elsewhere, these example embodiments have been described for illustrative purposes only, and are not limiting. Other embodiments are possible and are covered by the invention. Such other embodiments will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein. Thus, the breadth and scope of the present invention should not be limited by any of the above described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.