Patent Publication Number: US-2021191899-A1

Title: Data processing circuit, data storage device including the same, and operating method thereof

Description:
CROSS-REFERENCES TO RELATED APPLICATION 
     The present application is a continuation application of U.S. patent application Ser. No. 14/873,975, filed on Oct. 2, 2015, and claims priority under 35 U.S.C. § 119(a) to Korean Patent Application No. 10-2015-0076165, filed on May 29, 2015, which is incorporated herein by reference in its entirety. 
    
    
     BACKGROUND 
     1. Technical Field 
     Various embodiments generally relate to a data storage device and, more particularly, to a data storage device capable of randomizing and de-randomizing data. 
     2. Related Art 
     Data storage devices store data provided from an external device in response to a write request from the external device. Data storage devices also provide stored data to external devices in response to a read request from the external device. The external device is an electronic device capable of processing data, examples of which include computers, digital cameras and mobile phones. Data storage devices may be embedded in the external device, or may be physically separate but electrically coupled to the external device. 
     The data storage device may be a personal computer memory card international association (PCMCIA) card, a compact flash (CF) card, a smart media card, a memory stick, a multimedia card in the form of an MMC, an eMMC, an RS-MMC and an MMC-micro, a secure digital card in the form of an SD, a mini-SD and a micro-SD, a universal flash storage (UFS), or a solid state drive (SSD). 
     A data storage device includes nonvolatile memory for data storage. A nonvolatile memory apparatus can retain stored data even without a constant power source. Examples of nonvolatile memory apparatuses include flash memory, such as NAND flash or NOR flash, ferroelectric random access memory (FeRAM), phase change random access memory (PCRAM), magnetoresistive random access memory (MRAM) and resistive random access memory (RERAM). 
     SUMMARY 
     In an embodiment of the present invention, a data processing circuit may include: a plurality of transformation blocks suitable for respectively transforming in parallel a plurality of input bit groups into a plurality of output bit groups, wherein each of the transformation blocks transforms a corresponding input bit group into a corresponding output bit group using a random pattern. 
     In an embodiment of the present invention, a data storage device may include: a plurality of transformation blocks suitable for respectively transforming in parallel a plurality of write bit groups into a plurality of transformed write bit groups; and a nonvolatile memory apparatus suitable for storing the transformed write bit groups. 
     In an embodiment of the present invention, a method for operating a data storage device may include: transforming respectively in parallel a plurality of write bit groups into a plurality of transformed write bit groups; and storing the transformed write bit groups. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a block diagram exemplarily illustrating a data processing circuit in accordance with an embodiment of the present invention. 
         FIG. 2  is a diagram illustrating an example of first and second LFSRs shown in  FIG. 1 . 
         FIG. 3  is a block diagram exemplarily illustrating randomization and de-randomization of a data processing circuit of  FIG. 1  in accordance with an embodiment of the present invention. 
         FIG. 4  is a block diagram exemplarily illustrating a data storage device in accordance with an embodiment of the present invention. 
         FIG. 5  is a flow chart exemplarily illustrating an operation of a data storage device of  FIG. 4  in accordance with an embodiment of the present invention. 
         FIG. 6  is a flow chart exemplarily illustrating an operation of a data processing circuit of  FIG. 4  in accordance with an embodiment of the present invention. 
         FIG. 7  is a flow chart exemplarily illustrating an operation of a data storage device of  FIG. 4  in accordance with an embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION 
     Hereinafter, a data processing system and an operating method thereof according to the present invention will be described with reference to the accompanying drawings through exemplary embodiments of the present invention. The present invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to describe the present invention in detail to the extent that a person skilled in the art to which the invention pertains can enforce the technical concepts of the present invention. 
     It is to be understood that embodiments of the present invention are not limited to the particulars shown in the drawings, that the drawings are not necessarily to scale, and, in some instances, proportions may have been exaggerated to more clearly depict certain features of the invention. While particular terminology is used, it is to be appreciated that the terminology used is for describing particular embodiments only and is not intended to limit the scope of the present invention. 
       FIG. 1  is a block diagram exemplarily illustrating a data processing circuit  100  in accordance with an embodiment of the present invention. 
     Referring to  FIG. 1 , the data processing circuit  100  may transform a plurality of input bits IBT into a plurality of output bits OBT, and output the output bits OBT. The data processing circuit  100  may generate the output bits OBT by randomizing the input bits IBT. The data processing circuit  100  may generate output data by randomizing a pattern of the input bits IBT in order to minimize data interference and suppress data deformation. 
     The plurality of input bits IBT may be inputted in parallel to the data processing circuit  100 . For example, the total number of the bits inputted in parallel to the data processing circuit  100  may be 8, 16 or the like. 
     The plurality of input bits IBT may be grouped into a plurality of input bit groups. For example, upper half bits and lower half bits among the plurality of input bits IBT may be grouped into first and second input bit groups IBG 1  and IBG 2 , respectively. The number of input bit groups are not intended to be a limiting feature. 
     The data processing circuit  100  may include a plurality of transformation blocks, for example, first and second transformation blocks  110  and  120 . 
     The first and second input bit groups IBG 1  and IBG 2  may be inputted in parallel to the first and second transformation blocks  110  and  120 . The first input bit group IBG 1  may be inputted to the first transformation block  110 , and at substantially the same time, the second input bit group IBG 2  may be inputted to the second transformation block  120 . The plurality of input bits IBT comprising the first and second input bit groups IBG 1  and IBG 2  may be inputted in parallel to the first and second transformation blocks  110  and  120 . 
     The first and second transformation blocks  110  and  120  may respectively transform the first and second input bit groups IBG 1  and IBG 2  in parallel into first and second output bit groups OBG 1  and OBG 2 . The first transformation block  110  may transform the first input bit group IBG 1  into the first output bit group OBG 1 , and at substantially the same time, the second transformation block  120  may transform the second input bit group IBG 2  into the second output bit group OBG 2 . 
     The first and second transformation blocks  110  and  120  may respectively output in parallel the first and second output bit groups OBG 1  and OBG 2 . The first and second transformation blocks  110  and  120  may output in parallel the output bits OBT comprising the first and second output bit groups OBG 1  and OBG 2 . 
     The first transformation block  110  may include a first random pattern generation unit  111  and a first calculation unit  113 . 
     The first random pattern generation unit  111  may generate a first random pattern RPT 1  based on a seed SEED. The first random pattern generation unit  111  may include a first linear feedback shift register (hereinafter, referred to as a ‘first LFSR’) for generating the first random pattern RPT 1  based on the seed SEED. 
     The first calculation unit  113  may perform a logic operation on the first input bit group IBG 1  and the first random pattern RPT 1 , and generate the first output bit group OBG 1 . For example, the logic operation of the first calculation unit  113  may be an XOR operation. 
     The second transformation block  120  may include a second random pattern generation unit  121  and a second calculation unit  123 . 
     The second random pattern generation unit  121  may generate a second random pattern RPT 2  based on the seed SEED. The second random pattern generation unit  121  may include a second linear feedback shift register (hereinafter, referred to as a ‘second LFSR’) for generating the second random pattern RPT 2  based on the seed SEED. 
     The second calculation unit  123  may perform a logic operation on the second input bit group IBG 2  and the second random pattern RPT 2 , and generate the second output bit group OBG 2 . For example, the logic operation of the second calculation unit  123  may be an XOR operation. 
     In accordance with the embodiment, the first and second LFSRs  111  and  121  may correspond to different characteristic polynomials. Meanwhile, in accordance with the embodiment, when the data processing circuit  100  includes at least three LFSRs, the LFSRs may correspond to at least two characteristic polynomials. 
     In accordance with the embodiment, each of the first and second LFSRs  111  and  121  may generate a maximum length sequence. 
     In accordance with the embodiment, the degrees of the characteristic polynomials of the first and second LFSRs  111  and  121  may be a multiple number of the plurality of input bit groups IBG 1  and IBG 2  inputted to the first and second transformation blocks  110  and  120 , respectively. In accordance with the embodiment, the degree of each of the characteristic polynomials of the first and second LFSRs  111  and  121  may be a multiple number of the plurality of input bits IBT inputted to the data processing circuit  100 . 
     In accordance with the embodiment, the data processing circuit  100  may inverse transform the transformed data by performing the above-described data transformation process. When the output bits OBT are inputted in parallel to the first and second transformation blocks  110  and  120 , the first and second transformation blocks  110  and  120  may respectively transform in parallel the first and second output bit groups OBG 1  and OBG 2  into the first and second input bit groups IBG 1  and IBG 2 . Further, the first and second transformation blocks  110  and  120  may output in parallel the first and second input bit groups IBG 1  and IBG 2 , that is, the input bits IBT. 
     Even though it is illustrated in  FIG. 1  that the data processing circuit  100  includes two transformation blocks  110  and  120 , the number of transformation blocks included in the data processing circuit  100  is not be specifically limited. The number of the transformation blocks included in the data processing circuit  100  may determine the bit number of respective input bit groups. For example, when the number of transformation blocks included in the data processing circuit  100  is L, the bit number of respective input bit groups of the input bits IBT having J number of bits will be J/L. The number of bits of each output bit group may be set to be the same as the number of bits of each input bit group. 
       FIG. 2  is a diagram illustrating an example of the first and second LFSRs  111  and  123  shown in  FIG. 1 .  FIG. 2  illustrates an LFSR of the Fibonacci implementation, another implementation, for example, an LFSR of the Galois implementation, may also be realized. 
     Referring to  FIG. 2 , the LFSR may include 16 registers D 1  to D 16  which are electrically coupled in series. The seed SEED may be inputted to the first register D 1 , each of the registers D 1  to D 15  may shift a stored value to next register each time a clock signal is enabled (not shown), and the last register D 16  may output a sequence SQ, for example, each of the first and second random patterns RPT 1  and RPT 2  of  FIG. 1 .  FIG. 2  exemplarily shows the outputs of the registers D 16 , D 14 , D 13  and D 11  as the tabs. The tabs may be fed back to the first register D 1  after XOR operations through XOR operation units T 1  to T 3 . The LFSR may be used to generate a random pattern, for example, each of the first and second random patterns RPT 1  and RPT 2  of  FIG. 1 . The LFSR may generate a random pattern of K bits based on the values stored in K number of registers selected among N number of total registers in the LSFR each time the clock signal is enabled. 
     The LFSR comprising N number of total registers may correspond to the following characteristic polynomial. 
         f ( x )= x   N   +a   (N-1)   x   (N-1)   +a   (N-2)   x   (N-2)   + . . . +a   1   x+ 1 
     In the above polynomial, the coefficient a i  may be 0 or 1 according to the positions of the tabs. For example, the LFSR shown in  FIG. 2  may correspond to the following characteristic polynomial. 
         f ( x )= x   16   +x   14   +x   13   +x   11 +1 
     The LFSR shown in  FIG. 2  may correspond to a tab sequence [16, 14, 13, 11] representing the positions of the tabs. 
     The sequence SQ outputted from the last register D 16  in response to the enablement of the clock signal, that is, the output of the LFSR may be repeated with a predetermined cycle. 
     When the characteristic polynomial of the LFSR is a primitive polynomial, the LFSR may output the sequence SQ with a maximum length. When the LFSR including the N registers outputs the sequence SQ with a maximum length, the length of the sequence SQ may be 2 N −1. In other words, when the LFSR outputs the sequence SQ with a maximum length, the sequence SQ may be repeated with a cycle of 2 N −1. The sequence SQ may be defined as a maximum length sequence or an M-sequence. The M-sequence may be outputted when the N registers have 2 N −1 number of states except that all of the N registers have the state of 0. 
     For example, the tab progressions of the LFSR including 4 tabs and outputting the M-sequence may be as follows: 
     [16, 15, 13, 4], [16, 15, 12, 10], [16, 15, 12, 1], [16, 15, 10, 4], [16, 15, 9, 6], [16, 15, 9, 4], [16, 15, 7, 2], [16, 15, 4, 2], [16, 14, 13, 11], [16, 14, 13, 5], [16, 14, 12, 7], [16, 14, 11, 7], [16, 14, 9, 7], [16, 14, 9, 4], [16, 14, 8, 3], [16, 13, 12, 11], [16, 13, 12, 7], [16, 13, 11, 6], [16, 13, 9, 6], [16, 13, 6, 4], [16, 12, 9, 7], [16, 12, 9, 6], [16, 11, 10, 5], [16, 11, 9, 8], [16, 11, 9, 7], [16, 10, 9, 6]. 
     As to the representative characteristics of the M-sequence, the M-sequence may have the maximum cycle of 2 N −1, and the M-sequence may include 2 (N-1)  number of 1s and 2 (N-1) −1 number of 0s. Therefore, the random pattern generated from the LFSR, which outputs the M-sequence, may improve randomness of data. 
     Referring again to  FIG. 1 , the first and second random pattern generation units  111  and  121  may be the same or different. 
     In accordance with the embodiment, the first and second LFSRs  111  and  121  may correspond to different characteristic polynomials, in which case the first and second LFSRs  111  and  121  may output different sequences or different random patterns RPT 1  and RPT 2  based on the same seed SEED. 
     In accordance with the embodiment, the degree of the characteristic polynomials of the first and second LFSRs  111  and  121  may be a multiple number of the plurality of input bit groups IBG 1  and IBG 2  inputted to the first and second transformation blocks  110  and  120 , respectively. Each of the first and second LFSRs  111  and  121  may include N number of registers in total, and the N may be a multiple number of each of the plurality of input bit groups IBG 1  and IBG 2 . 
     In accordance with the embodiment, the degree of each of the characteristic polynomials of the first and second LFSRs  111  and  121  may be a multiple number of the plurality of input bits IBT inputted to the data processing circuit  100 . For example, each of the first and second LFSRs  111  and  121  may include N number of registers in total, and the N may be a multiple number of the plurality of input bits IBT. 
     In accordance with the embodiment, each of the first and second LFSRs  111  and  121  may output the M-sequence. When each of the first and second LFSRs  111  and  121  includes N number of the registers in total, the first and second LFSRs  111  and  121  may output the sequences SQ or the first and second random patterns RPT 1  and RPT 2  with the cycle of 2 N −1, respectively. 
       FIG. 3  is a block diagram exemplarily illustrating randomization and de-randomization of the data processing circuit  100  of  FIG. 1  in accordance with an embodiment of the present invention.  FIG. 3  exemplarily shows upper 4 bits and lower 4 bits, among the input bits IBT of 8 bits, that are grouped into the first and second input bit groups IBG 1  and IBG 2 , respectively. 
     The input bits IBT may be inputted in parallel to the data processing circuit  100 . The first and second input bit groups IBG 1  and IBG 2  may be respectively inputted in parallel to the first and second transformation blocks  110  and  120 . 
     The first and second LFSRs  111  and  121  may generate the different first and second random patterns RPT 1  and RPT 2  based on the seed SEED due to the different characteristic polynomials. The first calculation unit  113  may generate the first output bit group OBG 1  by performing an XOR operation on corresponding bits of the first input bit group IBG 1  and the first random pattern RPT 1 , and at substantially the same time, the second calculation unit  123  may generate the second output bit group OBG 2  by performing an XOR operation on corresponding bits of the second input bit group IBG 2  and the second random pattern RPT 2 . 
     The first and second output bit groups OBG 1  and OBG 2  may be outputted in parallel from the first and second transformation blocks  110  and  120 . The output bits OBT comprising the first and second output bit groups OBG 1  and OBG 2  may be outputted in parallel from the data processing circuit  100 . 
       FIG. 4  is a block diagram exemplarily illustrating the data storage device  100  in accordance with an embodiment of the present invention. 
     The data storage device  10  may include a controller  200  and a nonvolatile memory apparatus  300 . 
     The controller  200  may include a processor  210 , a data processing circuit  220 , and a memory  230 , which may be electrically coupled and communicate with one another through an internal bus  240 . 
     The processor  210  may control the general operations of the data storage device  10 . The processor  210  may control the components of the controller  200  to perform predetermined functions. The processor  210  may control the write operation or the read operation of the nonvolatile memory apparatus  300  in response to a write request or a read request from an external device. 
     The data processing circuit  220  may transform write bits WB to be stored in the nonvolatile memory apparatus  300  into transformed write bits RDWB, and may inverse transform the read bits RDRB, which are read from the nonvolatile memory apparatus  300 , into inverse-transformed read bits RB. When the transformed write bits RDWB have the same value as the read bits RDRB, the inverse-transformed read bits RB may have the same values as the write bits WB, which means that the write bits WB may be restored to have the original value through the transformation process as described above with reference to  FIGS. 1 to 3  when the write bits WB are stored in and then read from the nonvolatile memory apparatus  300 . 
     The data processing circuit  220  may include a plurality of transformation blocks (not shown). The plurality of transformation blocks may respectively transform in parallel a plurality of write bit groups included in the write bits WB into a plurality of transformed write bit groups, and may respectively output in parallel the plurality of transformed write bit groups. The transformed write bits RDWB may comprise the plurality of transformed write bit groups. 
     Further, the data processing circuit  220  may inverse transform in parallel a plurality of read bit groups included in the read bits RDRB into a plurality of inverse-transformed read bit groups. The inverse-transformed read bits RB may comprise the plurality of inverse-transformed read bit groups. The data processing circuit  220  may inverse transform the read bits RDRB into the plurality of inverse-transformed read bits RB by performing a transformation process to the plurality of read bits RDRB in substantially the same manner as the transformation process to the plurality of write bits WB. 
     The data processing circuit  220  may be the same as the data processing circuit  100  described with reference to  FIGS. 1 to 3 . In this case, for example, the write bits WB and the transformed write bits RDWB may be the plurality of input bits IBT and the plurality of output bits OBT described with reference to  FIGS. 1 to 3 , respectively. 
     The seed inputted to the data processing circuit  220  may correspond to a memory region of the nonvolatile memory apparatus  300 , in or from which data are to be stored or read. For example, the seed may be provided to the data processing circuit  220  according to the address offset of the corresponding memory region of the nonvolatile memory apparatus  300 . Accordingly, the seed corresponding to each memory region is fixed, and thus the data may be restored to have the original value through the same seed where the data is stored in and then read from the corresponding memory region of the nonvolatile memory apparatus  300  through the transformation process as described above with reference to  FIGS. 1 to 3 . 
     The memory  230  may serve as a working memory, a buffer memory or a cache memory of the processor  210 . The memory  230  as a working memory may store software programs and various program data for driving the processor  210 . The memory  230  as a buffer memory may buffer the data transmitted between the external device and the nonvolatile memory apparatus  300 . The memory  230  as a cache memory may temporarily store cache data. 
     The nonvolatile memory apparatus  300  may be provided in parallel with the plurality of transformed write bits RDWB, and store the plurality of transformed write bits RDWB through a write operation. The nonvolatile memory apparatus  300  may read the plurality of transformed write bits RDWB stored therein, as the plurality of read bits RDRB, and output in parallel the plurality of read bits RDRB. The nonvolatile memory apparatus  300  may transmit and receive data in parallel to and from the controller  200  through a plurality of data lines DL. 
     While  FIG. 4  shows an example in which the data storage device  10  includes one nonvolatile memory apparatus  300 , the embodiment is not limited to such an example, and it is to be noted that the data storage device  10  may include a plurality of nonvolatile memory apparatus  300 . 
     According to an embodiment, the data processing circuit  220  may be disposed in the nonvolatile memory apparatus  300  instead of the controller  200 . In this case, the data processing circuit  220  may transform the plurality of write bits WB transmitted from the controller  200 , and may inverse transform the read bits RDRB into the inverse-transformed read bits RB and transmit the inverse-transformed read bits RB to the controller  200 . 
     According to an embodiment, the data processing circuit  220  may be integrated into a separate chip and be disposed between the controller  200  and the nonvolatile memory apparatus  300 , and may transmit transformed/inverse-transformed data between the controller  200  and the nonvolatile memory apparatus  300 . 
       FIG. 5  is a flow chart exemplarily illustrating an operation of the data storage device  10  of  FIG. 4  in accordance with an embodiment of the present invention.  FIG. 5  shows a process of transforming data to be stored in the nonvolatile memory apparatus  300 . 
     Referring to  FIGS. 4 and 5 , at step S 110 , the data processing circuit  220  may receive in parallel the plurality of write bit groups included in the plurality of write bits WB. The plurality of write bits WB may be inputted in parallel to the data processing circuit  220 . 
     At step S 120 , the plurality of transformation blocks included in the data processing circuit  220  may transform in parallel the plurality of write bit groups into the transformed write bit groups through different random patterns, respectively. 
     At step S 130 , the controller  200  may transmit in parallel the plurality of transformed write bit groups to the nonvolatile memory apparatus  300 . The plurality of transformed write bits RDWB may comprise the plurality of transformed write bit groups. 
     At step S 140 , the nonvolatile memory apparatus  300  may store the transformed write bit groups through a write operation. 
       FIG. 6  is a flow chart exemplarily illustrating an operation of the data processing circuit  220  of  FIG. 4  in accordance with an embodiment of the present invention.  FIG. 6  exemplarily shows step S 120  described with reference to  FIG. 5 . 
     Referring to  FIGS. 4 and 6 , at step S 111 , the plurality of random pattern generation units included in the data processing circuit  220  may generate a plurality of different random patterns based on a seed. The plurality of random pattern generation units may be the random pattern generation units  111  and  121  described with reference to  FIGS. 1 to 3 . 
     At step S 112 , the plurality of calculation units included in the data processing circuit  220  may perform logic operations on the plurality of write bit groups and the plurality of random patterns, and generate the plurality of transformed write bit groups. The plurality of calculation units may be the calculation units  113  and  123  described with reference to  FIGS. 1 to 3 . 
       FIG. 7  is a flow chart exemplarily illustrating an operation of the data storage device  10  of  FIG. 4  in accordance with an embodiment of the present invention.  FIG. 7  shows a process of inverse-transforming the data read from the nonvolatile memory apparatus  300 . 
     Referring to  FIGS. 4 and 7 , at step S 210 , the nonvolatile memory apparatus  300  may read the plurality of transformed write bit groups stored therein, as the plurality of read bit groups. The plurality of read bits RDRB may comprise the plurality of read bit groups. 
     At step S 220 , the nonvolatile memory apparatus  300  may transmit in parallel the plurality of read bit groups to the controller  200 . 
     At step S 230 , the plurality of transformation blocks included is in the data processing circuit  220  may respectively inverse-transform in parallel the plurality of read bit groups to generate the plurality of inverse-transformed read bit groups. The plurality of inverse-transformed read bits RB may comprise the plurality of inverse-transformed read bit groups. 
     According to the embodiments, it is possible to effectively improve the randomness of data to be stored in the nonvolatile memory apparatus  300  through data processing by the plurality of transformation blocks disposed in parallel. Accordingly, it is possible to secure data reliability. Moreover, the rate of increase in the hardware size of the data processing circuit  220  for the parallel process of the plurality of transformation blocks is significantly smaller than the increase rate in hardware size for increasing the degree of the LFSR in order to lengthen the sequence. Therefore an advantage may be provided in retaining price competitiveness. 
     While various embodiments have been described above, it will be understood to those skilled in the art that the embodiments described are examples only. Accordingly, the data processing circuit, the data storage device including the same and the operating method thereof described herein should not be limited based on the described embodiments.