Patent Publication Number: US-2022223592-A1

Title: Semiconductor device including fin field effect transistor

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application is a continuation of U.S. patent application Ser. No. 16/382,439 filed Apr. 12, 2019, which is incorporated by reference herein in its entirety. 
     Korean Patent Application No. 10-2018-0106428, filed on Sep. 6, 2018, in the Korean Intellectual Property Office, and entitled: “Semiconductor Device and Method of Manufacturing the Same,” is incorporated by reference herein in its entirety. 
    
    
     BACKGROUND 
     1. Field 
     The present disclosure relates to a semiconductor device, and more particularly, to a semiconductor device including a fin field effect transistor and a method of manufacturing the same. 
     2. Description of the Related Art 
     A semiconductor device may include an integrated circuit with metal oxide semiconductor field effect transistors (MOSFETs). As size and design rule of the semiconductor device are gradually decreased, sizes of the MOSFETs are also scaled down. The scale down of MOSFETs may deteriorate operating characteristics of the semiconductor device. Accordingly, various researches have been developed to manufacture semiconductor devices having superior performances while overcoming limitations due to high integration of the semiconductor devices. 
     SUMMARY 
     According to some example embodiments, a semiconductor device may include a first gate pattern and a second gate pattern that are disposed on a substrate and spaced apart from each other, and a separation pattern that separates the first gate pattern and the second gate pattern from each other. The first gate pattern may comprise a first high-k dielectric pattern and a first metal-containing pattern on the first high-k dielectric pattern. The first metal-containing pattern may cover a sidewall of the first high-k dielectric pattern. The second gate pattern may comprise a second high-k dielectric pattern and a second metal-containing pattern on the second high-k dielectric pattern. The separation pattern may be in direct contact with the first metal-containing pattern and spaced apart from the first high-k dielectric pattern. 
     According to some example embodiments, a semiconductor device may include a plurality of first active fins that protrude from a substrate, a plurality of second active fins that protrude from the substrate and are spaced apart from the first active fins, a first gate pattern that crosses over the first active fins and is elongated in a first direction, a second gate pattern that crosses over the second active fins and is elongated in the first direction, and a separation pattern between the first gate pattern and the second gate pattern. The first gate pattern may comprise a first high-k dielectric pattern. The separation pattern may be spaced apart from the first high-k dielectric pattern. 
     According to some example embodiments, a semiconductor device may include a substrate including a first gate region, a second gate region, and a separation region between the first and second gate regions, and a first gate pattern and a second gate pattern that are provided on the substrate and respectively disposed on the first gate region and the second gate region. The first gate pattern may comprise a first high-k dielectric pattern. The first high-k dielectric pattern may not be exposed at a sidewall of the first gate pattern. The sidewall of the first gate pattern may be adjacent to the separation region. 
     According to some example embodiments, a method of manufacturing a semiconductor device may include providing a substrate including a first gate region, a second gate region, and a separation region between the first and second gate regions, forming a high-k dielectric layer on an entire surface of the substrate; removing the high-k dielectric layer from the separation region to form a first high-k dielectric pattern and a second high-k dielectric pattern on the first gate region and the second gate region, respectively, forming a metal-containing layer on the entire surface of the substrate, and removing the metal-containing layer from the separation region to form a first gate pattern and a second gate pattern on the first gate region and the second gate region, respectively. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Features will become apparent to those of skill in the art by describing in detail exemplary embodiments with reference to the attached drawings, in which: 
         FIG. 1  illustrates a plan view of a semiconductor device according to some example embodiments. 
         FIG. 2  illustrates a cross-sectional view along lines A-A′, B-B′, C-C′ of  FIG. 1 , according to example embodiments. 
         FIG. 3  illustrates a cross-sectional view along line D-D′ of  FIG. 1 . 
         FIGS. 4 to 7, 8B, and 9 to 12  illustrate cross-sectional views of stages in a method of manufacturing a semiconductor device. 
         FIG. 8A  illustrates a plan view of a stage in a method of manufacturing a semiconductor device having the plan view of  FIG. 1 . 
         FIG. 13  illustrates a cross-sectional view showing a stage in a method of manufacturing a semiconductor device having the cross-sectional view of  FIG. 2 . 
         FIG. 14  illustrates a cross-sectional view along lines A-A′, B-B′, C-C′ of  FIG. 1 , according to other example embodiments. 
         FIG. 15  illustrates a cross-sectional view along lines A-A′, B-B′, C-C′ of  FIG. 1 , according to other example embodiments. 
         FIG. 16  illustrates a plan view of a semiconductor device according to some example embodiments. 
         FIG. 17  illustrates a cross-sectional view along lines A-A′, B-B′, C-C′ of  FIG. 16 , according to some example embodiments. 
         FIG. 18  illustrates a cross-sectional view along lines A-A′, B-B′, C-C′ of  FIG. 16 , according to some example embodiments. 
         FIG. 19  illustrates a plan view of a semiconductor device according to some example embodiments. 
         FIG. 20  illustrates a cross-sectional view along lines A-A′, B-B′, C-C′ of  FIG. 19 , according to some example embodiments. 
         FIG. 21  illustrates a cross-sectional view of a stage in a method of manufacturing a semiconductor device having the cross-sectional view of  FIG. 20 . 
         FIG. 22  illustrates a plan view of a semiconductor device according to some example embodiments. 
         FIG. 23  illustrates a cross-sectional view along lines A-A′, B-B′, C-C′ of  FIG. 22 . 
         FIG. 24A  illustrates a plan view of a semiconductor device according to some example embodiments. 
         FIG. 24B  illustrates a cross-sectional view along lines A-A′, B-B′, C-C′ of  FIG. 24A . 
         FIG. 25  illustrates a cross-sectional view along lines A-A′, B-B′, C-C′ of  FIG. 1 , according to other example embodiments. 
         FIG. 26  illustrates a cross-sectional view along lines A-A′, B-B′, C-C′ of  FIG. 1 , according to other example embodiments. 
         FIG. 27  illustrates a perspective view of a semiconductor device according to example embodiments. 
         FIG. 28  illustrates a cross-sectional view along lines A-A′, B-B′, C-C′ of  FIG. 1 , according to other example embodiments. 
     
    
    
     DETAILED DESCRIPTION 
     Some example embodiments will now be described in detail with reference to the accompanying drawings. 
       FIG. 1  illustrates a plan view showing a semiconductor device according to some example embodiments.  FIG. 2  illustrates a cross-sectional view taken along lines A-A′, B-B′, C-C′ of  FIG. 1 , according to some example embodiments.  FIG. 3  illustrates a cross-sectional view taken along line D-D′ of  FIG. 1 , according to some example embodiments. 
     Referring to  FIGS. 1 to 3 , a semiconductor substrate  1  may include a first gate region GR 1  and a second gate region GR 2  that are spaced apart from each other, e.g., along a first direction X, and also include a separation region SR between the first and second gate regions GR 1  and GR 2 . The semiconductor substrate  1  may be, e.g., a single crystalline silicon wafer substrate or a silicon-on-insulator (SOI) substrate. A plurality of first active fins AF 1  and a plurality of second active fins AF 2  may protrude in a third direction Z from a top surface of the semiconductor substrate  1 . The first active fins AF 1  may be disposed on the first gate region GR 1 , and the second active fins AF 2  may be disposed on the second gate region GR 2 . 
     A first gate pattern GP 1  and a third gate pattern GP 3  may cross over the first active fins AF 1 , e.g., the first and third gate patterns GP 1  and GP 3  may be parallel to each other and spaced apart from each other along a second direction Y. A second gate pattern GP 2  and a fourth gate pattern GP 4  may cross over the second active fins AF 2 , e.g., the second and fourth gate patterns GP 2  and GP 4  may be parallel to each other and spaced apart from each other along the second direction Y. The first, second, third, and fourth gate patterns GP 1 , GP 2 , GP 3 , and GP 4  may be elongated in the first direction X. The first gate pattern GP 1  may be adjacent to and spaced apart from the second gate pattern GP 2 , e.g., along the first direction X. The first and second gate patterns GP 1  and GP 2  may be placed on an imaginary straight line. The third gate pattern GP 3  may be adjacent to and spaced apart from the fourth gate pattern GP 4 , e.g., along the first direction X. The third and fourth gate patterns GP 3  and GP 4  may be placed on an imaginary straight line. 
     Each of the first and second active fins AF 1  and AF 2  may have a linear or bar shape that extends in the second direction Y intersecting the first direction X. The semiconductor device may be a fin field effect transistor. 
     First device isolation patterns  3   a  may be disposed on the semiconductor substrate  1  between the first active fins AF 1 . Second device isolation patterns  3   b  may be disposed on the semiconductor substrate  1  between the second active fins AF 2 . A third device isolation pattern  3   m  may be disposed on the semiconductor substrate  1  between one of the first active fins AF 1  that is most adjacent to the second gate pattern GP 2  and one of the second active fins AF 2  that is most adjacent to the first gate pattern GP 1 . The first, second, and third device isolation patterns  3   a ,  3   b , and  3   m  may have their top surfaces lower than those of the first and second active fins AF 1  and AF 2 . The first, second, and third device isolation patterns  3   a ,  3   b , and  3   m  may have a single- or multi-layered structure that includes, e.g., one or more of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer. 
     The first active fins AF 1  may be spaced apart from each other, e.g., along the first direction X, at an interval corresponding to a first width W 1  of each of the first device isolation patterns  3   a . The second active fins AF 2  may be spaced apart from each other, e.g., along the first direction X, at an interval corresponding to a second width W 2  of each of the second device isolation patterns  3   b . The third device isolation pattern  3   m  may have a third width W 3 , e.g., along the first direction X, corresponding to a distance between one of the first active fins AF 1  that is most adjacent to the second gate pattern GP 2  and one of the second active fins AF 2  that is most adjacent to the first gate pattern GP 1 . The first width W 1  may be substantially the same as the second width W 2 . The third width W 3  may be greater than the first and second widths W 1  and W 2 . 
     The first and third gate patterns GP 1  and GP 3  may be in contact with the top surfaces and lateral surfaces of the first active fins AF 1  and with the top surfaces of the first device isolation patterns  3   a . The second and fourth gate patterns GP 2  and GP 4  may be in contact with the top surfaces and lateral surfaces of the second active fins AF 2  and with the top surfaces of the second device isolation patterns  3   b.    
     The first gate pattern GP 1  may include a first high-k dielectric pattern HK 1 , a first metal-containing pattern MG 1 , and a first capping pattern CP 1 . The second gate pattern GP 2  may include a second high-k dielectric pattern HK 2 , a second metal-containing pattern MG 2 , and a second capping pattern CP 2 . The third gate pattern GP 3  may include a third high-k dielectric pattern HK 3 , a third metal-containing pattern MG 3 , and a third capping pattern CP 3 . The fourth gate pattern GP 4  may include a fourth high-k dielectric pattern HK 4 , a fourth metal-containing pattern MG 4 , and a fourth capping pattern CP 4 . 
     The first, second, third, and fourth high-k dielectric patterns HK 1 , HK 2 , HK 3 , and HK 4  may be formed of a material, whose dielectric constant is greater than that of a silicon oxide layer, including one or more of, e.g., hafnium oxide (HfO 2 ), hafnium silicate (HfSiO), hafnium oxynitride (HfON), hafnium silicon oxynitride (HfSiON), hafnium aluminum oxide (HfAlO 3 ), lanthanum oxide (LaO), lanthanum aluminum oxide (LaAlO), zirconium oxide (ZrO), zirconium silicate (ZrSiO), zirconium oxynitride (ZrON), zirconium silicon oxynitride (ZrSiON), titanium oxide (TiO 2 ), barium strontium titanium oxide (BaSrTiO), barium titanium oxide (BaTiO), strontium titanium oxide (SrTiO), yttrium oxide (YO), aluminum oxide (Al 2 O 3 ), tantalum oxide (Ta 2 O 3 ), and lead scandium tantalum oxide (PbScTaO). 
     Each of the first, second, third, and fourth gate patterns GP 1 , GP 2 , GP 3 , and GP 4  may further include a dielectric layer between a corresponding one of the first, second, third, and fourth high-k dielectric patterns HK 1 , HK 2 , HK 3 , and HK 4  and a corresponding one of the first and second active fins AF 1  and AF 2 . The dielectric layer may have a single- or multi-layered structure that includes, e.g., one or more of a silicon oxide layer, a silicon oxynitride layer, and a silicon nitride layer. The first, second, third, and fourth high-k dielectric patterns HK 1 , HK 2 , HK 3 , and HK 4  and the dielectric layer may serve as gate dielectric layers. 
     Each of the first, second, third, and fourth metal-containing patterns MG 1 , MG 2 , MG 3 , and MG 4  may include one or more of a work function pattern, diffusion break pattern, and a metal line pattern. The work function pattern may be an N-type work function pattern or a P-type work function pattern. The N-type work function pattern may include, e.g., one or more of lanthanum (La), lanthanum oxide (LaO), tantalum (Ta), tantalum nitride (TaN), niobium (Nb), and titanium nitride (TiN). The P-type work function pattern may include, e.g., one or more of aluminum (Al), aluminum oxide (Al 2 O 3 ), titanium nitride (TiN), tungsten nitride (WN), and ruthenium oxide (RuO 2 ). The diffusion break pattern may include a metal nitride layer, e.g., a titanium nitride layer, a tantalum nitride layer, and a tungsten nitride layer. The metal line pattern may include one or more of, e.g., tungsten, copper, and aluminum. 
     Referring to a cross-section taken along line B-B′ in  FIG. 2 , the first gate pattern GP 1  may be configured such that the first metal-containing pattern MG 1  contact a sidewall of the first high-k dielectric pattern HK 1 . The first metal-containing pattern MG 1  may be in partial contact with the top surface of the third device isolation pattern  3   m . The second gate pattern GP 2  may be configured such that the second metal-containing pattern MG 2  may be in contact with a sidewall of the second high-k dielectric pattern HK 2 . The second metal-containing pattern MG 2  may be in partial contact with the top surface of the third device isolation pattern  3   m . Each of the third and fourth gate patterns GP 3  and GP 4  may have a cross-section parallel to the first and second gate patterns GP 1  and GP 2  in the first direction X, and may have structures the same as or similar to the cross-section taken along line B-B′ in  FIG. 2 . 
     Referring to a cross-section taken along line C-C′ shown in  FIG. 2 , the first high-k dielectric pattern HK 1  may extend to cover a sidewall of the first metal-containing pattern MG 1 . The third high-k dielectric pattern HK 3  may extend to cover a sidewall of the third metal-containing pattern MG 3 . As shown in  FIG. 3 , the second high-k dielectric pattern HK 2  may extend to cover a sidewall of the second metal-containing pattern MG 2 . The fourth high-k dielectric pattern HK 4  may extend to cover a sidewall of the fourth metal-containing pattern MG 4 . 
     In the cross-section taken along line B-B′ in  FIG. 2 , a first separation pattern SP 1  may be interposed between the first gate pattern GP 1  and the second gate pattern GP 2 . A second separation pattern SP 2  may be interposed between the third gate pattern GP 3  and the fourth gate pattern GP 4 . The first and second separation patterns SP 1  and SP 2  may include a single or multiple layer of dielectric, e.g., silicon oxide, silicon nitride, and silicon oxynitride. The first separation pattern SP 1  may be in contact with the first metal-containing pattern MG 1  and the first capping pattern CP 1 , and may be spaced apart from the first high-k dielectric pattern HK 1 . The first metal-containing pattern MG 1  may be interposed between the first separation pattern SP 1  and the sidewall of the first high-k dielectric pattern HK 1 . The first separation pattern SP 1  may be in contact with the second metal-containing pattern MG 2  and the second capping pattern CP 2 , and may be spaced apart from the second high-k dielectric pattern HK 2 . The first separation pattern SP 1  may be in contact with both the first metal-containing pattern MG 1  and the second metal-containing pattern MG 2 . 
     The first high-k dielectric pattern HK 1  may not be exposed at a sidewall of the first gate pattern GP 1 , which sidewall is on or adjacent to the separation region SR. The second high-k dielectric pattern HK 2  may not be exposed at a sidewall of the second gate pattern GP 2 , which sidewall is on or adjacent to the separation region SR. The sidewall of the first high-k dielectric pattern HK 1  may not be aligned with the sidewall of the first metal-containing pattern MG 1 . The sidewall of the second high-k dielectric pattern HK 2  may not be aligned with the sidewall of the second metal-containing pattern MG 2 . For example, as illustrated in  FIG. 2 , while the first high-k dielectric pattern HK 1  may be, e.g., continuous and, conformal on the first active fins AF 1  and the first device isolation pattern  3   a  therebetween, the first high-k dielectric pattern HK 1  may extend only on a portion of the third device isolation pattern  3   m , so a portion of the third device isolation pattern  3   m  may be exposed, e.g., not covered, by the first high-k dielectric pattern HK 1 , e.g., a portion of the third device isolation pattern  3   m  surrounding the first separation pattern SP 1 , may be covered by the first metal-containing pattern MG 1 , e.g., so the first metal-containing pattern MG 1  contacts the third device isolation pattern  3   m  and separates between the first high-k dielectric pattern HK 1  and the first separation pattern SP 1 . The second high-k dielectric pattern HK 2  has a same structure. 
     The first and second separation patterns SP 1  and SP 2  may have their bottom surface lower than the top surface of the third device isolation pattern  3   m . The bottom surfaces of the first and second separation patterns SP 1  and SP 2  may be located at the same height as, e.g., or lower than, that of the top surface of the third device isolation pattern  3   m.    
     The first gate pattern GP 1  may have a fourth width W 4  parallel to the second direction Y. The first separation pattern SP 1  may have a fifth width W 5  parallel to the second direction Y. The fourth width W 4  may be substantially the same as the fifth width W 5 . A width parallel to the second direction Y of each of the second, third, and fourth gate patterns GP 2 , GP 3 , and GP 4  may be the same as the fourth width W 4 . A width parallel to the second direction Y of the second separation pattern SP 2  may be the same as the fifth width W 5 . 
     Spacers  10  may cover sidewalls of the first, second, third, and fourth gate patterns GP 1 , GP 2 , GP 3 , and GP 4  and sidewalls of the first and second separation patterns SP 1  and SP 2 . The spacer  10  may have a single- or multi-layered structure that includes, e.g., one or more of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer. 
     In the cross-section taken along line C-C′ in  FIG. 2 , the first active fins AF 1  may be recessed at their upper portions on opposite sides of each of the first and third gate patterns GP 1  and GP 3 , and the recessed upper portions may be replaced with first source/drain patterns SD 1 . As shown in  FIG. 3 , the second active fins AF 2  may be recessed at their upper portions on opposite sides of each of the second and fourth gate patterns GP 2  and GP 4 , and the recessed upper portions may be replaced with second source/drain patterns SD 2 . Each of the first and second source/drain patterns SD 1  and SD 2  may include an epitaxial layer of semiconductor, e.g., silicon and germanium. Each of the first and second source/drain patterns SD 1  and SD 2  may include doped N-type or P-type impurities. The first source/drain pattern SD 1  may be spaced apart in the first direction X from the second source/drain pattern SD 2 . The first and second source/drain patterns SD 1  and SD 2  may have their top ends higher than the top surfaces of the first and second active fins AF 1  and AF 2 . 
     A first interlayer dielectric layer  20  may fill a space between the first and second separation patterns SP 1  and SP 2 , a portion of a space between the first and third gate patterns GP 1  and GP 3 , and a portion of a space between the second and fourth gate patterns GP 2  and GP 4 . The first interlayer dielectric layer  20  may have a top surface coplanar with those of the first and second separation patterns SP 1  and SP 2  and those of the first, second, third, and fourth gate patterns GP 1 , GP 2 , GP 3 , and GP 4 . 
     A second interlayer dielectric layer  30  may be disposed on the first interlayer dielectric layer  20 . Each of the first and second interlayer dielectric layers  20  and  30  may have a single- or multi-layered structure that includes, e.g., one or more of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and a porous low-k dielectric layer. Each of contact plugs  40  may penetrate the second and first interlayer dielectric layers  30  and  20  and have coupling to a corresponding one of the first and second source/drain patterns SD 1  and SD 2 . 
       FIGS. 4 to 7, 8B, and 9 to 12  illustrate cross-sectional views showing stages in a method of manufacturing a semiconductor device having the cross-section of  FIG. 2 , according to some example embodiments.  FIG. 8A  illustrates a plan view of a method of manufacturing a semiconductor device having the plan view of  FIG. 1 , according to some example embodiments. 
     Referring to  FIG. 4 , the semiconductor substrate  1  may be prepared. The semiconductor substrate  1  may be a single crystalline silicon substrate or a silicon-on-insulator (SOI) substrate. The semiconductor substrate  1  may be etched to form a plurality of trenches. A device isolation layer may be formed on the semiconductor substrate  1  so as to fill the trenches, and then a planarization process may be performed to form the first, second, and third device isolation patterns  3   a ,  3   b , and  3   m  and to expose a top surface of the semiconductor substrate  1 . When viewed in plan view, the first, second, and third device isolation patterns  3   a ,  3   b , and  3   m  may be formed in positions other than those overlapped by the first active fins AF 1  and the second active fins AF 2 , as will be discussed below. The semiconductor substrate  1  may include the first gate region GR 1  and the second gate region GR 2  that are spaced apart from each other, and also include the separation region SR between the first and second gate region GR 1  and GR 2  (see  FIG. 1 ). 
     Referring to  FIG. 5 , an etch-back process may be performed to remove upper portions of the first, second, and third device isolation patterns  3   a ,  3   b , and  3   m  and to expose portions of the semiconductor substrate  1  that are between the first, second, and third device isolation patterns  3   a ,  3   b , and  3   m . As such, the first and second active fins AF 1  and AF 2  may be formed. When viewed in plan view, as shown in  FIG. 1 , the first and second active fins AF 1  and AF 2  may be arranged in a plurality of linear shapes extending in the second direction Y. A dielectric layer, a polysilicon layer, and a dummy capping layer may be sequentially formed on an entire surface of the semiconductor substrate  1 , and then patterned to form dummy gate patterns PDG. Each of the dummy gate patterns PDG may include a dummy gate dielectric pattern  4 , a dummy polysilicon pattern  5 , and a dummy capping pattern  7  that are sequentially stacked. The dummy gate dielectric pattern  4  may be formed of, e.g., a silicon oxide layer. The dummy capping pattern  7  may be formed of, e.g., a silicon nitride layer. When viewed in plan view, the dummy gate patterns PDG may have a plurality of linear shapes that are spaced apart from each other and extend in the first direction X. For example, when viewed in plan view, as shown in  FIG. 1 , one of the dummy gate patterns PDG may have a linear shape that runs along the first and third gate patterns GP 1  and GP 3  and the first separation pattern SP 1  that are discussed above with reference to  FIG. 1 , and another one of the dummy gate patterns PDG may have a linear shape that runs along the second and fourth gate patterns GP 2  and GP 4  and the second separation pattern SP 2  that are discussed above with reference to  FIG. 1 . 
     Referring to  FIG. 6 , a spacer layer may be conformally stacked on the entire surface of the semiconductor substrate  1  and then anisotropically etched to form the spacers  10  covering sidewalls of the dummy gate patterns PDG. The spacer  10  may be formed to have a single- or multi-layered structure that includes, e.g., one or more of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer. An etching process may be performed on the first and second active fins AF 1  and AF 2  on opposite sides of each of the dummy gate patterns PDG, which may result in the formation of recesses R 1 . One or more of silicon and germanium may be supplied to perform a selective epitaxial growth process to form the first source/drain patterns SD 1  in the recesses R 1 . The second source/drain patterns SD 2  may also be formed as shown in  FIG. 3 . The first interlayer dielectric layer  20  may be stacked on the entire surface of the semiconductor substrate  1  and then a planarization process may be performed to expose top surfaces of the dummy gate patterns PDG. 
     Referring to  FIG. 7 , the exposed dummy gate patterns PDG may be removed to form a first groove G 1  and a second groove G 2  each of which extends in the first direction X between the spacers  10 . The first and second grooves G 1  and G 2  may partially expose top surfaces and sidewalls of the first and second active fins AF 1  and AF 2 , and also partially expose top surfaces of the first, second, and third device isolation patterns  3   a ,  3   b , and  3   m . A deposition process, e.g., chemical vapor deposition or atomic layer deposition, may be performed to conformally form a high-k dielectric layer HK on the entire surface of the semiconductor substrate  1 . The high-k dielectric layer HK may also be conformally formed on an upper portion of the first interlayer dielectric layer  20  and on inner walls and floors of the first and second grooves G 1  and G 2 . The high-k dielectric layer HK may be formed of a material, whose dielectric constant is greater than that of a silicon oxide layer, including one or more of, e.g., hafnium oxide (HfO 2 ), hafnium silicate (HfSiO), hafnium oxynitride (HfON), hafnium silicon oxynitride (HfSiON), hafnium aluminum oxide (HfAlO 3 ), lanthanum oxide (LaO), lanthanum aluminum oxide (LaAlO), zirconium oxide (ZrO), zirconium silicate (ZrSiO), zirconium oxynitride (ZrON), zirconium silicon oxynitride (ZrSiON), titanium oxide (TiO 2 ), barium strontium titanium oxide (BaSrTiO), barium titanium oxide (BaTiO), strontium titanium oxide (SrTiO), yttrium oxide (YO), aluminum oxide (Al 2 O 3 ), tantalum oxide (Ta 2 O 3 ), and lead scandium tantalum oxide (PbScTaO). Before the high-k dielectric layer HK is formed, a silicon oxide layer or a silicon nitride layer may be formed as a gate dielectric layer. 
     Referring to  FIGS. 8A and 8B , a protective layer  41  may be stacked on the entire surface of the semiconductor substrate  1 . The protective layer  41  may lie on the high-k dielectric layer HK and fill the first and second grooves G 1  and G 2 . The protective layer  41  may have selectivity with respect to the high-k dielectric layer HK, and may be formed of a layer having superior gap-fill characteristics. For example, the protective layer  41  may be formed to have a single- or multi-layered structure that includes, e.g., one or more of a silicon nitride layer, a spin-on-carbon (SOC) layer, a spin-on-hardmask (SOH) layer, an amorphous carbon layer (ACL), and a bottom antireflective coating (BARC) layer that is a cross-linked organic polymer material. A first mask pattern M 1  may be formed on the protective layer  41 . For example, the first mask pattern M 1  may be formed of a photoresist pattern. The first mask pattern M 1  may be formed to have a first opening OP 1  that partially exposes a top surface of the protective layer  41 . When viewed in plan view, the first opening OP 1  may be formed to have a linear or bar shape that is elongated in the second direction Y on the separation region SR. The first opening OP 1  may have a sixth width W 6  parallel to the first direction X. 
     Referring to  FIGS. 8A, 8B, and 9 , an etching process may be performed in which the first mask pattern M 1  is used as an etching mask to successively etch the protective layer  41  and the high-k dielectric layer HK, which etching process may form a first separation hole  47   a  and a second separation hole  47   b  that partially expose the top surface of the third device isolation pattern  3   m . When viewed in plan view, the first separation hole  47   a  may be formed at a location where the first groove G 1  and the first opening OP 1  intersect each other, and the second separation hole  47   b  may be formed at a location where the second groove G 2  and the first opening OP 1  intersect each other. The etching process may remove the high-k dielectric layer HK from the separation region SR, and a residual high-k dielectric layer HK may be divided into a first preliminary high-k dielectric pattern HK 13  and a second preliminary high-k dielectric pattern HK 24  that are spaced apart from each other. The first preliminary high-k dielectric pattern HK 13  may be disposed on the first gate region GR 1 , and the second preliminary high-k dielectric pattern HK 24  may be disposed on the second gate region RG 2 . In a cross-sectional view taken along line C-C′ in  FIG. 9 , the first preliminary high-k dielectric pattern HK 13  may also be disposed on the first interlayer dielectric layer  20 . 
     Referring to  FIGS. 9 and 10 , the first mask pattern M 1  and the protective layer  41  may be removed. A plating process or a deposition process, e.g., sputtering or physical vapor deposition, may be used to stack a metal-containing layer MG on the entire surface of the semiconductor substrate  1 . The metal-containing layer MG may be formed to include one or more of a work function layer, a diffusion break layer, and a metal line layer. The metal-containing layer MG may cover the first interlayer dielectric layer  20 . The metal-containing layer MG may fill the first and second grooves G 1  and G 2  and the first and second separation holes  47   a  and  47   b.    
     Referring to  FIGS. 10 and 11 , an etch-back process may be performed to remove the metal-containing layer MG, the first preliminary high-k dielectric pattern HK 13 , and the second preliminary high-k dielectric pattern HK 24  that are on the first interlayer dielectric layer  20 , to expose upper inner walls of the first and second grooves G 1  and G 2  and upper inner walls of the first and second separation holes  47   a  and  47   b , to form a first preliminary metal-containing pattern MG 12  in each of the first groove G 1  and the first separation hole  47   a , and to form a second preliminary metal-containing pattern MG 34  in each of the second groove G 2  and the second separation hole  47   b . The first and second preliminary metal-containing patterns MG 12  and MG 34  may be formed to have their top surfaces lower than that of the first interlayer dielectric layer  20 . A residual first preliminary high-k dielectric pattern HK 13  may be divided into a first high-k dielectric pattern HK 1  and a third high-k dielectric pattern HK 3 . Likewise, a residual second preliminary high-k dielectric pattern HK 24  may be divided into a second high-k dielectric pattern HK 2  and a fourth high-k dielectric pattern HK 4 . A capping layer may be stacked on the entire surface of the semiconductor substrate  1 , and then an etch-back process may be performed to form a first preliminary capping pattern CP 12  on the first preliminary metal-containing pattern MG 12  and to form a second preliminary capping pattern CP 34  on the second preliminary metal-containing pattern MG 34 . 
     Therefore, on the first gate region GR 1 , the first groove G 1  may be provided therein with the first high-k dielectric pattern HK 1 , the first preliminary metal-containing pattern MG 12 , and the first preliminary capping pattern CP 12 , and the second groove G 2  may be provided therein with the third high-k dielectric pattern HK 3 , the second preliminary metal-containing pattern MG 34 , and the second preliminary capping pattern CP 34 . On the second gate region GR 2 , the first groove G 1  may be provided therein with the second high-k dielectric pattern HK 2 , the first preliminary metal-containing pattern MG 12 , and the first preliminary capping pattern CP 12 . On the second gate region GR 2 , the second groove G 2  may be provided therein with the fourth high-k dielectric pattern HK 4 , the second preliminary metal-containing pattern MG 34 , and the second preliminary capping pattern CP 34 . No high-k dielectric pattern may be provided in each of the first and second separation holes  47   a  and  47   b.    
     Referring to  FIG. 11 , a second mask pattern M 2  may be formed on the first interlayer dielectric layer  20 , the first preliminary capping pattern CP 12 , and the second preliminary capping pattern CP 34 . The second mask pattern M 2  may be formed of, e.g., a photoresist pattern. The second mask pattern M 2  may include a second opening OP 2 . The second opening OP 2  may have identical or similar position and planar shape to those of the first opening OP 1  of  FIG. 8A . For example, when viewed in plan view, the second opening OP 2  may have a linear or bar shape that is elongated in the second direction Y on the separation region SR. The second opening OP 2  may have a seventh width W 7  parallel to the first direction X. To stably separate gate patterns which will be discussed below in  FIG. 12 , the seventh width W 7  may be less than the sixth width W 6  of the first opening OP 1 . On the separation region SR, the second opening OP 2  may expose the top surface of the first interlayer dielectric layer  20  and top surfaces of the first and second preliminary capping patterns CP 12  and CP 34 . 
     Referring to  FIGS. 11 and 12 , an etching process may be performed on the first and second preliminary capping patterns CP 12  and CP 34  that are exposed to the second opening OP 2  on the separation region SR and on the first and second preliminary metal-containing patterns MG 12  and MG 34  below the exposed first and second preliminary capping patterns CP 12  and CP 34 , which etching process may expose the top surface of the third device isolation pattern  3   m  and the inner walls of the first and second separation holes  47   a  and  47   b . The first preliminary metal-containing pattern MG 12  may thus be divided into a first metal-containing pattern MG 1  and a second metal-containing pattern MG 2 . Likewise, the second preliminary metal-containing pattern MG 34  may be divided into a third metal-containing pattern MG 3  and a fourth metal-containing pattern MG 4 . In addition, the first preliminary capping pattern CP 12  may be divided into a first capping pattern CP 1  and a second capping pattern CP 2 . Likewise, the second preliminary capping pattern CP 34  may be divided into a third capping pattern CP 3  and a fourth capping pattern CP 4 . Therefore, the first gate pattern GP 1  and the second gate pattern GP 2  may be formed spaced apart from each other. The third gate pattern GP 3  and the fourth gate pattern GP 4  may also be formed spaced apart from each other. The etching process may be performed in an over-etching manner to reliably guarantee separation. Thus, an upper portion of the third device isolation pattern  3   m  may be partially recessed. 
     Because the first and second preliminary high-k dielectric patterns HK 13  and HK 24  are already cut in the step of  FIG. 9 , none of the first, second, third, and fourth high-k dielectric patterns HK 1 , HIK 2 , HK 3 , and HK 4  are required to be etched during the etching process. Thus, there may be no difficulty in successively etching a metal-containing layer and a high-k dielectric layer, and it may be possible to avoid the possibility that the high-k dielectric layer remains on the separation region SR. In addition, the separation of gate patterns may be preferably accomplished to prevent bridge or short between the gate patterns. As a result, a semiconductor device may improve in reliability, decrease in defect rate, and increase in manufacturing yield. 
     Referring to  FIGS. 12 and 2 , the second mask pattern M 2  may be removed. When the second mask pattern M 2  is formed of a carbon-containing material, e.g., photoresist, an ashing process may be performed to remove the second mask pattern M 2 . The semiconductor substrate  1  may be stacked thereon with a separation layer to fill the first and second separation holes  47   a  and  47   b , and then a polishing process may be performed to form the first separation pattern SP 1  and the second separation pattern SP 2  in the first separation hole  47   a  and the second separation hole  47   b , respectively. Subsequently, referring to  FIGS. 2 and 3 , the second interlayer dielectric layer  30  may be stacked on the first interlayer dielectric layer  20 . The second and first interlayer dielectric layers  30  and  20  may be patterned to form contact holes that expose the first and second source/drain patterns SD 1  and SD 2 , and then the contact holes may be filled with a conductive material to form contact plugs  40 . 
       FIG. 13  illustrates a cross-sectional view showing a method of manufacturing a semiconductor device having the cross-sectional view of  FIG. 2 , according to some example embodiments. 
     Referring to  FIG. 13 , in the step of  FIG. 11 , the second opening OP 2  may have a width greater than the seventh width W 7 . For example, the second opening OP 2  may have a width equal to or greater than that of the first opening OP 1  of  FIG. 8B . In this case, a subsidiary spacer  52  may be additionally formed to cover a sidewall of the second opening OP 2  such that the second opening OP 2  may be controlled to finally have a width equal to the seventh width W 7 . The second mask pattern M 2  and the subsidiary spacer  52  may be used as an etching mask to etch the exposed first and second preliminary capping patterns CP 12  and CP 34  and their underlying first and second preliminary metal-containing patterns MG 12  and MG 34 , which etching may expose the top surface of the third device isolation pattern  3   m  and the inner walls of the first and second separation holes  47   a  and  47   b . The first preliminary metal-containing pattern MG 12  may thus be divided into the first metal-containing pattern MG 1  and the second metal-containing pattern MG 2 . Likewise, the second preliminary metal-containing pattern MG 34  may be divided into the third metal-containing pattern MG 3  and the fourth metal-containing pattern MG 4 . In addition, the first preliminary capping pattern CP 12  may be divided into the first capping pattern CP 1  and the second capping pattern CP 2 . Likewise, the second preliminary capping pattern CP 34  may be divided into the third capping pattern CP 3  and the fourth capping pattern CP 4 . Therefore, the first gate pattern GP 1  and the second gate pattern GP 2  may be formed spaced apart from each other. The third gate pattern GP 3  and the fourth gate pattern GP 4  may also be formed spaced apart from each other. Subsequently, the second mask pattern M 2  and the subsidiary spacer  52  may be removed, and the first and second separation patterns SP 1  and SP 2  may be formed. 
     As discussed above, on the separation region SR, a high-k dielectric layer may be first removed, and thereafter a metal-containing layer may be removed to separate gate patterns. When the metal-containing layer and the high-k dielectric layer are successively etched on the separation region SR, i.e., without cutting the high-k dielectric layer in advance, the high-k dielectric layer may be hardly etched with an etchant for etching the metal-containing layer. Furthermore, metal residues may remain on the high-k dielectric layer, and accordingly the high-k dielectric layer may be harder to etch. Therefore, the high-k dielectric layer may remain on the separation region SR, and in this case, the gate patterns may suffer from bridge or short, which in turn, may deteriorate reliability of a semiconductor device. 
     In contrast, according to example embodiments, because the high-k dielectric layer is first removed, the high-k dielectric layer may not be required to be etched in an etching process where the metal-containing layer is etched to separate the gate patterns. Hence, a gate separation process may be easily performed, and the high-k dielectric layer may not remain on the separation region SR, with the result that a semiconductor may improve in reliability and decrease in defect rate. Furthermore, a manufacturing yield may be increased. 
       FIG. 14  illustrates a cross-sectional view taken along lines A-A′, B-B′, C-C′ of  FIG. 1 , according to some example embodiments. 
     Referring to  FIG. 14 , the first separation pattern SP 1  may be in contact with the sidewall of the first high-k dielectric pattern HK 1 , but spaced apart from the sidewall of the second high-k dielectric pattern HK 2 . Other configurations may be identical or similar to those discussed above with reference to  FIG. 2 . The structure shown in  FIG. 14  may be eventually formed when a slight misalignment occurs, in the step of  FIG. 12 , to cause the sidewall of the first high-k dielectric pattern HK 1  to be exposed at the inner wall of the first separation hole  47   a.    
       FIG. 15  illustrates a cross-sectional view taken along lines A-A′, B-B′, C-C′ of  FIG. 1 , according to some example embodiments. 
     Referring to  FIG. 15 , the first separation pattern SP 1  may be in contact with the sidewall of the first high-k dielectric pattern HK 1  and also with the sidewall of the second high-k dielectric pattern HK 2 . The first separation pattern SP 1  may have a bottom surface whose width is equal to or less than an interval between the first high-k dielectric pattern HK 1  and the second high-k dielectric pattern HK 2 . Other configurations may be identical or similar to those discussed above with reference to  FIG. 2 . The structure shown in  FIG. 15  may be formed when the second opening OP 2  of the second mask pattern M 2  shown in  FIG. 11  has the seventh width W 7  equal to or greater than the sixth width W 6  of the first opening OP 1  of the first mask pattern M 1  shown in  FIG. 8B . 
       FIG. 16  illustrates a plan view showing a semiconductor device according to some example embodiments.  FIG. 17  illustrates a cross-sectional view taken along lines A-A′, B-B′, C-C′ of  FIG. 16 , according to some example embodiments. 
     Referring to  FIGS. 16 and 17 , the first separation pattern SP 1  and the second separation pattern SP 2  may not be in contact with the spacer  10  of  FIG. 2 , but in direct contact with the first interlayer dielectric layer  20 . The fifth width W 5  parallel to the second direction Y of the first separation pattern SP 1  may be greater than the fourth width W 4  parallel to the second direction Y of the first gate pattern GP 1 . Other configurations may be identical or similar to those discussed with reference to  FIGS. 1 and 2 . A semiconductor device according to the present embodiment may be manufactured as follows. In the step of  FIG. 12 , when an etching process is performed on the first and second preliminary capping patterns CP 12  and CP 34  exposed to the second opening OP 2  and on the first and second preliminary metal-containing patterns MG 12  and MG 34  below the exposed first and second preliminary capping patterns CP 12  and CP 34 , the spacers  10  may all be simultaneously removed from the separation region SR. Therefore, the first interlayer dielectric layer  20  may be exposed in the second direction Y at the inner walls of the first and second separation holes  47   a  and  47   b . Subsequent processes may be identical or similar to those discussed above with reference to  FIG. 2 . 
       FIG. 18  illustrates a cross-sectional view taken along lines A-A′, B-B′, C-C′ of  FIG. 16 , according to some example embodiments. 
     Referring to  FIG. 18 , each of the first and second separation patterns SP 1  and SP 2  may have, at an upper portion thereof, a separation pattern protrusion SPP that protrudes in the second direction Y from a sidewall thereof. The separation pattern protrusion SPP may have a first vertical length L 1  between top and bottom ends thereof, and the first vertical length L 1  may be substantially the same as a second vertical length L 2  corresponding to a thickness of the first capping pattern CP 1 . The spacer  10  may remain below the separation pattern protrusion SPP. The separation pattern protrusion SPP may cause the spacer  10  to have a top end that is located at a lower height than that of top surfaces of the first and second separation patterns SP 1  and SP 2 . Other configurations may be identical or similar to those discussed above with reference to  FIG. 2 . 
     The structure of  FIG. 18  may be formed as follows. In the step of  FIG. 12 , when an etching process is performed on the first and second preliminary capping patterns CP 12  and CP 34  exposed to the second opening OP 2 , an upper portion of the spacer  10  may also be etched. An etching depth of the spacer  10  may be the same as thicknesses of the first and second preliminary capping patterns CP 12  and CP 34 . The spacer  10  may remain on the separation region SR. Processes identical or similar to those discussed above with reference to  FIG. 2  may be subsequently performed. 
       FIG. 19  illustrates a plan view showing a semiconductor device according to some example embodiments.  FIG. 20  illustrates a cross-sectional view taken along lines A-A′, B-B′, C-C′ of  FIG. 19 , according to some example embodiments. 
     Referring to  FIGS. 19 and 20 , the first separation pattern SP 1  may have, at the upper portion thereof, the separation pattern protrusion SPP that protrudes in the first direction X from the sidewall thereof. The first separation pattern SP 1  may have a T-shaped cross-section. Although not shown, the second separation pattern SP 2  may have a cross-section identical or similar to that of the first separation pattern SP 1 . The separation pattern protrusion SPP may partially cover top surfaces of the first and second metal-containing patterns MG 1  and MG 2 . Other configurations may be identical or similar to those discussed above with reference to  FIG. 2 . 
       FIG. 21  illustrates a cross-sectional view showing a method of manufacturing a semiconductor device having the cross-sectional view of  FIG. 20 , according to some example embodiments. 
     Referring to  FIG. 21 , in a state identical or similar to that illustrated in  FIG. 11 , the second mask pattern M 2  may be used as an etching mask to etch the exposed first and second preliminary capping patterns CP 12  and CP 34 , and thus the first preliminary metal-containing pattern MG 12  may be exposed at its top surface. The second opening OP of the second mask pattern M 2  may have a width greater than the seventh width W 7  of  FIG. 11 . The first preliminary capping pattern CP 12  may be divided into the first capping pattern CP 1  and the second capping pattern CP 2 . A subsidiary spacer  52  may be formed to cover each sidewall of the second mask pattern M 2 , the first capping pattern CP 1 , and the second capping pattern CP 2 . The formation of the subsidiary spacer  52  may cause the width of the second opening OP 2  to be reduced eventually to the seventh width W 7 . The subsidiary spacer  52  and the second mask pattern M 2  may be used as an etching mask to etch the first and second preliminary metal-containing patterns MG 12  and MG 34 , which etching may form the first and second separation holes  47   a  and  47   b.    
     Subsequently, the second mask pattern M 2  and the subsidiary spacer  52  may be removed, and the first and second separation patterns SP 1  and SP 2  may be formed. 
       FIG. 22  illustrates a plan view showing a semiconductor device according to some example embodiments.  FIG. 23  illustrates a cross-sectional view taken along lines A-A′, B-B′, C-C′ of  FIG. 22 , according to some example embodiments. 
     Referring to  FIGS. 22 and 23 , the top surface of the first interlayer dielectric layer  20  may be lower than those of the first and second separation patterns SP 1  and SP 2 . A third vertical length L 3  corresponding to a height from the top surface of the first interlayer dielectric layer  20  to the top surface of the first separation pattern SP 1  may be substantially the same as a fourth vertical length L 4  corresponding to a height from the top surface of the third device isolation pattern  3   m  to the bottom surface of the first separation pattern SP 1 . Each of the first and second separation patterns SP 1  and SP 2  may have, at the upper portion thereof, the separation pattern protrusion SPP that extends in the second direction Y from the sidewall thereof. The separation pattern protrusions SPP may be connected to each other such that, when viewed in plan as shown in  FIG. 22 , the first and second separation patterns SP 1  and SP 2  may be integrally formed into a linear or bar shape that is elongated in the second direction Y. Other configurations may be identical or similar to those discussed above with reference to  FIG. 17 . 
     The semiconductor device of  FIG. 23  may be manufactured as follows. In the step of  FIG. 12 , when an etching process is performed on the first and second preliminary capping patterns CP 12  and CP 34  exposed to the second opening OP 2  and on the first and second preliminary metal-containing patterns MG 12  and MG 34  below the exposed first and second preliminary capping patterns CP 12  and CP 34 , the spacers  10  may all be simultaneously removed from the separation region SR. In addition, when an upper portion of the third device isolation pattern  3   m  is over-etched, an upper portion of the first interlayer dielectric layer  20  may also be etched on the separation region SR, and accordingly the top surface of the first interlayer dielectric layer  20  may be lowered. When the third device isolation pattern  3   m  and the first interlayer dielectric layer  20  are formed of the same material such as a silicon oxide layer, the first interlayer dielectric layer  20  may be removed as much as a thickness removed from the upper portion of the third device isolation pattern  3   m . Other manufacturing processes may be identical or similar to those discussed with reference to  FIG. 17 . 
       FIG. 24A  illustrates a plan view showing a semiconductor device according to some example embodiments.  FIG. 24B  illustrates a cross-sectional view taken along lines A-A′, B-B′, C-C′ of  FIG. 24A , according to some example embodiments. 
     Referring to  FIGS. 24A and 24B , the separation region SR may include a separation pattern SP, which has a linear shape extending along the second direction Y. The separation pattern SP may be interposed not only between the first and second gate patterns GP 1  and GP 2  but also between the third and fourth gate patterns GP 3  and GP 4 . The separation pattern SP may be disposed in a separation groove GS. The separation pattern SP may be spaced apart from all of the first and second high-k dielectric patterns HK 1  and HK 2 . The separation pattern SP may have a uniform thickness along the second direction Y. The separation pattern SP may have a bottom surface lower than the top surface of the third device isolation pattern  3   m . Other configurations may be identical or similar to those discussed above with reference to  FIGS. 1 and 2 . 
     The semiconductor device of  FIG. 24B  may be manufactured as follows. In the steps of  FIGS. 11 and 12 , when a removal process is performed on the first preliminary capping pattern CP 12  exposed to the second opening OP 2  and on the first preliminary metal-containing pattern MG 12  below the exposed first preliminary capping pattern CP 12 , the spacer  10  and the first interlayer dielectric layer  20  exposed to the second opening OP 2  may also be removed to expose the top surface of the third device isolation pattern  3   m  below the first preliminary metal-containing pattern MG 12 . In this case, the separation region SR may be provided thereon with a separation groove GS whose shape is transferred from that of the second opening OP 2 . When viewed in plan, the separation groove GS may have a linear shape extending along the second direction Y. A separation pattern SP may be formed in the separation groove GS. 
       FIG. 25  illustrates a cross-sectional view taken along lines A-A′, B-B′, C-C′ of  FIG. 1 , according to some example embodiments. 
     Referring to  FIG. 25 , the first gate pattern GP 1  may include a first high-k dielectric pattern HK 1 , a first work function pattern WK 1 , a first metal line pattern IG 1 , and a first capping pattern CP 1 . The second gate pattern GP 2  may include a second high-k dielectric pattern HK 2 , a second work function pattern WK 2 , a second metal line pattern IG 2 , and a second capping pattern CP 2 . 
     Each of the first and second work function patterns WK 1  and WK 2  may be an N-type work function pattern or a P-type work function pattern. The N-type work function pattern may include one or more of lanthanum (La), lanthanum oxide (LaO), tantalum (Ta), tantalum nitride (TaN), niobium (Nb), and titanium nitride (TiN). The P-type work function pattern may include one or more of aluminum (Al), aluminum oxide (Al 2 O 3 ), titanium nitride (TiN), tungsten nitride (WN), and ruthenium oxide (RuO 2 ). The first and second metal line patterns IG 1  and IG 2  may include one or more of tungsten, copper, and aluminum. 
     In a cross-section taken along line B-B′ in  FIG. 25 , the first work function pattern WK 1  may have a sidewall aligned with that of the first high-k dielectric pattern HK 1 . The first metal line pattern IG 1  may be in contact with the sidewall of the first high-k dielectric pattern HK 1  and the sidewall of the first work function pattern WK 1 . The sidewall of the first high-k dielectric pattern HK 1  and the sidewall of the first work function pattern WK 1  may be spaced apart from the first separation pattern SP 1 . The second work function pattern WK 2  may have a sidewall aligned with that of the second high-k dielectric pattern HK 2 . The second metal line pattern IG 2  may be in contact with the sidewall of the second high-k dielectric pattern HK 2  and the sidewall of the second work function pattern WK 2 . The sidewall of the second high-k dielectric pattern HK 2  and the sidewall of the second work function pattern WK 2  may be spaced apart from the second separation pattern SP 2 . Other configurations may be identical or similar to those discussed above with reference to  FIG. 2 . 
     The semiconductor device of  FIG. 25  may be manufactured as follows. In the step of  FIG. 7 , a work function layer may be conformally formed on the high-k dielectric layer HK, and in the step of  FIG. 9 , the work function layer may be cut when the high-k dielectric layer HK is cut on the separation region SR. As like that shown in  FIG. 10 , a metal line layer may be formed on the work function layer and the high-k dielectric layer HK, and then the processes discussed above with reference to  FIGS. 11 and 12  may be subsequently performed. 
       FIG. 26  illustrates a cross-sectional view taken along lines A-A′, B-B′, C-C′ of  FIG. 1 , according to some example embodiments. 
     Referring to  FIG. 26 , the first gate pattern GP 1  may include the first high-k dielectric pattern HK 1 , the first work function pattern WK 1 , the first metal line pattern IG 1 , and the first capping pattern CP 1 . The second gate pattern GP 2  may include the second high-k dielectric pattern HK 2 , the second work function pattern WK 2 , the second metal line pattern IG 2 , and the second capping pattern CP 2 . In a cross-section taken along line B-B′ in  FIG. 26 , the first work function pattern WK 1  may have a sidewall in contact with the first high-k dielectric pattern HK 1 . The first separation pattern SP 1  may be in contact with the sidewall of the first work function pattern WK 1 , and may be spaced apart from the first high-k dielectric pattern HK 1 . The second work function pattern WK 2  may have a sidewall in contact with the second high-k dielectric pattern HK 2 . The second separation pattern SP 2  may be in contact with the sidewall of the second work function pattern WK 2 , and may be spaced apart from the second high-k dielectric pattern HK 2 . Other configurations may be identical or similar to those discussed above with reference to  FIG. 2 . The structure of  FIG. 26  may be formed when the metal-containing layer MG is replaced with a double layer that includes, e.g., consists of, the work function layer and the metal line layer. 
       FIG. 27  illustrates a perspective view showing a semiconductor device according to some example embodiments. 
     Referring to  FIG. 27 , a semiconductor substrate  1  may be provided that includes a first gate region GR 1 , a second gate region GR 2 , and a separation region SR between the first and second gate regions GR 1  and GR 2 . A device isolation pattern  3  may be disposed in the semiconductor substrate  1  on the separation region SR. A first gate pattern GP 1  may be disposed on the semiconductor substrate  1  on the first gate region GR 1 , and a second gate pattern GP 2  may be disposed on the semiconductor substrate  1  on the second gate region GR 2 . On the separation region SR, the semiconductor substrate  1  may be provided thereon with a first separation pattern SP 1  that separates the first and second gate patterns GP 1  and GP 2  from each other. The first gate pattern GP 1  may include a first high-k dielectric pattern HK 1 , a first metal-containing pattern MG 1 , and a first capping pattern CP 1  that are sequentially stacked. The second gate pattern GP 2  may include a second high-k dielectric pattern HK 2 , a second metal-containing pattern MG 2 , and a second capping pattern CP 2  that are sequentially stacked. The first separation pattern SP 1  may be spaced apart from all of the first and second high-k dielectric patterns HK 1  and HK 2 . The semiconductor substrate  1  may be provided therein with source/drain regions SDR each of which is adjacent to a corresponding one of the first and second gate patterns GP 1  and GP 2 . The source/drain region SDR may be doped with P-type or N-type impurities. A semiconductor device according to the present embodiment may include no active fins AF 1  and AF 2  of  FIG. 2 . In addition, in the semiconductor device according to the present embodiment, the first and second high-k dielectric patterns HK 1  and HK 2  may not extend onto sidewalls of the first and second metal-containing patterns MG 1  and MG 2 . Although not shown, the first gate pattern GP 1 , the second gate pattern GP 2 , and the first separation pattern SP 1  may have their sidewalls covered with spacers. 
     The semiconductor device of  FIG. 27  may be manufactured as follows. A semiconductor substrate  1  may be prepared to include a first gate region GR 1 , a second gate region GR 2 , and a separation region SR between the first and second gate regions GR 1  and GR 2 . A device isolation pattern  3  may be formed in the semiconductor substrate  1  on the separation region SR. A high-k dielectric layer may be formed on an entire surface of the semiconductor substrate  1  and then removed from the separation region SR, which removal may form a first high-k dielectric pattern HK 1  and a second high-k dielectric pattern HK 2  on the first gate region GR 1  and the second gate region GR 2 , respectively. In this step, shapes of the first and second high-k dielectric patterns HK 1  and HK 2  may be determined by partial removal of the high-k dielectric layer from the first and second gate regions GR 1  and GR 2 . A metal-containing layer and a capping layer may be sequentially formed on the entire surface of the semiconductor substrate  1  and then patterned to form a first metal-containing pattern MG 1 , a second metal-containing pattern MG 2 , a first capping pattern CP 1 , and a second capping pattern CP 2 . Therefore, a first gate pattern GP 1  and a second gate pattern GP 2  may be formed. An ion implantation process may be performed to form source/drain regions SDR. 
       FIG. 28  illustrates a cross-sectional view taken along lines A-A′, B-B′, C-C′ of  FIG. 1 , according to some example embodiments. 
     Referring to  FIG. 28 , each of the first and second separation patterns SP 1  and SP 2  may include a first separation dielectric layer  91  and a second separation dielectric layer  93 . The first separation dielectric layer  91  may have a different material from that of the second separation dielectric layer  93 . For example, one of the first and second separation dielectric layers  91  and  93  may be a silicon oxide layer, and the other of the first and second separation dielectric layers  91  and  93  may be a silicon nitride layer. The first separation dielectric layer  91  may cover a bottom surface and a sidewall of the second separation dielectric layer  93 . Each of the first and second separation patterns SP 1  and SP 2  may have a double-layered structure composed of different dielectric layers as shown in  FIG. 29 , but alternatively may have a triple- or more-layered structure. Each of the first and second separation patterns SP 1  and SP 2  may include an air gap or a seam. 
     According to embodiments, a semiconductor device may improve in reliability. In a method of manufacturing a semiconductor device according to embodiments, because the removal of a high-k dielectric layer occurs before removal of a metal-containing layer from a separation region, the separation of gate patterns may be accomplished to prevent bridge or short between the gate patterns. In such case, a cutting failure may be prevented because no residues of the high-k dielectric layer are left on the gate cutting region. As a result, the semiconductor may improve in reliability, decrease in defect rate, and increase in manufacturing yield. 
     Example embodiments have been disclosed herein, and although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purpose of limitation. In some instances, as would be apparent to one of ordinary skill in the art as of the filing of the present application, features, characteristics, and/or elements described in connection with a particular embodiment may be used singly or in combination with features, characteristics, and/or elements described in connection with other embodiments unless otherwise specifically indicated. Accordingly, it will be understood by those of skill in the art that various changes in form and details may be made without departing from the spirit and scope of the present invention as set forth in the following claims.