Patent Publication Number: US-10324859-B2

Title: Multi-plane memory management

Description:
TECHNICAL FIELD 
     The present disclosure, in various embodiments, relates to multi-plane memory and more particularly relates to multi-plane memory management. 
     BACKGROUND 
     Many electrical circuits and devices, such as data storage devices or the like, include multi-plane memory. Multi-plane memory may have certain planes that are defective and other planes that are not defective. A multi-plane memory may be managed by removing all planes from operation in response to one plane including a defect, resulting in some memory planes that are not defective, but are unused. 
     SUMMARY 
     Apparatuses are presented for multi-plane memory management. In one embodiment, an apparatus includes a failure detection circuit that detects a failure of a storage element during an operation. An apparatus, in certain embodiments, includes a test circuit that performs a test on a storage element. An apparatus, in one embodiment, includes a recycle circuit that enables a portion of a storage element for use in operations in response to the portion of the storage element passing a test. 
     Systems are presented for multi-plane memory management. A system, in one embodiment, includes a controller. In various embodiments, a system includes an array of memory devices. In some embodiments, the controller is configured to identify a failure of a memory device during a multi-plane operation. In a further embodiment, the controller is configured to perform an erase operation on a plane of a memory device. In certain embodiments, the controller is configured to perform a program operation on a successfully erased plane of a memory device. 
     An apparatus for multi-plane memory management, in one embodiment, includes means for checking operation of a memory block, the memory block being removed from use in operations in response to a failure of the memory block during an operation. In some embodiments, an apparatus includes means for returning at least a first plane of a memory block for use in operations in response to a successful operation check, wherein a second plane of the memory block remains unused for operations. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       A more particular description is included below with reference to specific embodiments illustrated in the appended drawings. Understanding that these drawings depict only certain embodiments of the disclosure and are not therefore to be considered to be limiting of its scope, the disclosure is described and explained with additional specificity and detail through the use of the accompanying drawings, in which: 
         FIG. 1A  is a schematic block diagram illustrating one embodiment of a system for multi-plane memory management; 
         FIG. 1B  is a schematic block diagram illustrating another embodiment of a system for multi-plane memory management; 
         FIG. 2  is a schematic block diagram illustrating one embodiment of a string of storage cells; 
         FIG. 3  is a schematic block diagram illustrating one embodiment of an array of storage cells; 
         FIG. 4  illustrates one embodiment of a 3D, vertical NAND flash memory structure; 
         FIG. 5  is a schematic block diagram illustrating one embodiment of a memory recycling component; 
         FIG. 6  is a schematic block diagram illustrating a further embodiment of a memory recycling component; 
         FIG. 7  is a schematic flow chart diagram illustrating one embodiment of a method for multi-plane memory management; and 
         FIG. 8  is a schematic flow chart diagram illustrating a further embodiment of a method for multi-plane memory management. 
     
    
    
     DETAILED DESCRIPTION 
     Aspects of the present disclosure may be embodied as an apparatus, system, method, or computer program product. Accordingly, aspects of the present disclosure may take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, micro-code, or the like) or an embodiment combining software and hardware aspects that may all generally be referred to herein as a “circuit,” “module,” “apparatus,” or “system.” Furthermore, aspects of the present disclosure may take the form of a computer program product embodied in one or more non-transitory computer readable storage media storing computer readable and/or executable program code. 
     Many of the functional units described in this specification have been labeled as modules, in order to more particularly emphasize their implementation independence. For example, a module may be implemented as a hardware circuit comprising custom VLSI circuits or gate arrays, off-the-shelf semiconductors such as logic chips, transistors, or other discrete components. A module may also be implemented in programmable hardware devices such as field programmable gate arrays, programmable array logic, programmable logic devices, or the like. 
     Modules may also be implemented at least partially in software for execution by various types of processors. An identified module of executable code may, for instance, comprise one or more physical or logical blocks of computer instructions which may, for instance, be organized as an object, procedure, or function. Nevertheless, the executables of an identified module need not be physically located together, but may comprise disparate instructions stored in different locations which, when joined logically together, comprise the module and achieve the stated purpose for the module. 
     Indeed, a module of executable code may include a single instruction, or many instructions, and may even be distributed over several different code segments, among different programs, across several memory devices, or the like. Where a module or portions of a module are implemented in software, the software portions may be stored on one or more computer readable and/or executable storage media. Any combination of one or more computer readable storage media may be utilized. A computer readable storage medium may include, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing, but would not include propagating signals. In the context of this document, a computer readable and/or executable storage medium may be any tangible and/or non-transitory medium that may contain or store a program for use by or in connection with an instruction execution system, apparatus, processor, or device. 
     Computer program code for carrying out operations for aspects of the present disclosure may be written in any combination of one or more programming languages, including an object oriented programming language such as Python, Java, Smalltalk, C++, C#, Objective C, or the like, conventional procedural programming languages, such as the “C” programming language, scripting programming languages, and/or other similar programming languages. The program code may execute partly or entirely on one or more of a user&#39;s computer and/or on a remote computer or server over a data network or the like. 
     A component, as used herein, comprises a tangible, physical, non-transitory device. For example, a component may be implemented as a hardware logic circuit comprising custom VLSI circuits, gate arrays, or other integrated circuits; off-the-shelf semiconductors such as logic chips, transistors, or other discrete devices; and/or other mechanical or electrical devices. A component may also be implemented in programmable hardware devices such as field programmable gate arrays, programmable array logic, programmable logic devices, or the like. A component may comprise one or more silicon integrated circuit devices (e.g., chips, die, die planes, packages) or other discrete electrical devices, in electrical communication with one or more other components through electrical lines of a printed circuit board (PCB) or the like. Each of the modules described herein, in certain embodiments, may alternatively be embodied by or implemented as a component. 
     A circuit, as used herein, comprises a set of one or more electrical and/or electronic components providing one or more pathways for electrical current. In certain embodiments, a circuit may include a return pathway for electrical current, so that the circuit is a closed loop. In another embodiment, however, a set of components that does not include a return pathway for electrical current may be referred to as a circuit (e.g., an open loop). For example, an integrated circuit may be referred to as a circuit regardless of whether the integrated circuit is coupled to ground (as a return pathway for electrical current) or not. In various embodiments, a circuit may include a portion of an integrated circuit, an integrated circuit, a set of integrated circuits, a set of non-integrated electrical and/or electrical components with or without integrated circuit devices, or the like. In one embodiment, a circuit may include custom VLSI circuits, gate arrays, logic circuits, or other integrated circuits; off-the-shelf semiconductors such as logic chips, transistors, or other discrete devices; and/or other mechanical or electrical devices. A circuit may also be implemented as a synthesized circuit in a programmable hardware device such as field programmable gate array, programmable array logic, programmable logic device, or the like (e.g., as firmware, a netlist, or the like). A circuit may comprise one or more silicon integrated circuit devices (e.g., chips, die, die planes, packages) or other discrete electrical devices, in electrical communication with one or more other components through electrical lines of a printed circuit board (PCB) or the like. Each of the modules described herein, in certain embodiments, may be embodied by or implemented as a circuit. 
     Reference throughout this specification to “one embodiment,” “an embodiment,” or similar language means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, appearances of the phrases “in one embodiment,” “in an embodiment,” and similar language throughout this specification may, but do not necessarily, all refer to the same embodiment, but mean “one or more but not all embodiments” unless expressly specified otherwise. The terms “including,” “comprising,” “having,” and variations thereof mean “including but not limited to” unless expressly specified otherwise. An enumerated listing of items does not imply that any or all of the items are mutually exclusive and/or mutually inclusive, unless expressly specified otherwise. The terms “a,” “an,” and “the” also refer to “one or more” unless expressly specified otherwise. 
     Aspects of the present disclosure are described below with reference to schematic flowchart diagrams and/or schematic block diagrams of methods, apparatuses, systems, and computer program products according to embodiments of the disclosure. It will be understood that each block of the schematic flowchart diagrams and/or schematic block diagrams, and combinations of blocks in the schematic flowchart diagrams and/or schematic block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a computer or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor or other programmable data processing apparatus, create means for implementing the functions and/or acts specified in the schematic flowchart diagrams and/or schematic block diagrams block or blocks. 
     It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. Other steps and methods may be conceived that are equivalent in function, logic, or effect to one or more blocks, or portions thereof, of the illustrated figures. Although various arrow types and line types may be employed in the flowchart and/or block diagrams, they are understood not to limit the scope of the corresponding embodiments. For instance, an arrow may indicate a waiting or monitoring period of unspecified duration between enumerated steps of the depicted embodiment. 
     In the following detailed description, reference is made to the accompanying drawings, which form a part thereof. The foregoing summary is illustrative only and is not intended to be in any way limiting. In addition to the illustrative aspects, embodiments, and features described above, further aspects, embodiments, and features will become apparent by reference to the drawings and the following detailed description. The description of elements in each figure may refer to elements of proceeding figures. Like numbers may refer to like elements in the figures, including alternate embodiments of like elements. 
       FIG. 1A  is a block diagram of one embodiment of a system  100  comprising a memory recycling component  150  for a non-volatile memory device  120 . The memory recycling component  150  may be part of and/or in communication with a non-volatile memory media controller  126 , a non-volatile memory element  123 , a device driver, or the like. The memory recycling component  150  may operate on a non-volatile memory system  102  of a computing device  110 , which may comprise a processor  111 , volatile memory  112 , and a communication interface  113 . The processor  111  may comprise one or more central processing units, one or more general-purpose processors, one or more application-specific processors, one or more virtual processors (e.g., the computing device  110  may be a virtual machine operating within a host), one or more processor cores, or the like. The communication interface  113  may comprise one or more network interfaces configured to communicatively couple the computing device  110  and/or non-volatile memory controller  126  to a communication network  115 , such as an Internet Protocol (IP) network, a Storage Area Network (SAN), wireless network, wired network, or the like. 
     The non-volatile memory device  120 , in various embodiments, may be disposed in one or more different locations relative to the computing device  110 . In one embodiment, the non-volatile memory device  120  comprises one or more non-volatile memory elements  123 , such as semiconductor chips or packages or other integrated circuit devices disposed on one or more printed circuit boards, storage housings, and/or other mechanical and/or electrical support structures. For example, the non-volatile memory device  120  may comprise one or more direct inline memory module (DIMM) cards, one or more expansion cards and/or daughter cards, a solid-state-drive (SSD) or other hard drive device, and/or may have another memory and/or storage form factor. The non-volatile memory device  120  may be integrated with and/or mounted on a motherboard of the computing device  110 , installed in a port and/or slot of the computing device  110 , installed on a different computing device  110  and/or a dedicated storage appliance on the network  115 , in communication with the computing device  110  over an external bus (e.g., an external hard drive), or the like. 
     The non-volatile memory device  120 , in one embodiment, may be disposed on a memory bus of a processor  111  (e.g., on the same memory bus as the volatile memory  112 , on a different memory bus from the volatile memory  112 , in place of the volatile memory  112 , or the like). In a further embodiment, the non-volatile memory device  120  may be disposed on a peripheral bus of the computing device  110 , such as a peripheral component interconnect express (PCI Express or PCIe) bus, a serial Advanced Technology Attachment (SATA) bus, a parallel Advanced Technology Attachment (PATA) bus, a small computer system interface (SCSI) bus, a FireWire bus, a Fibre Channel connection, a Universal Serial Bus (USB), a PCIe Advanced Switching (PCIe-AS) bus, or the like. In another embodiment, the non-volatile memory device  120  may be disposed on a data network  115 , such as an Ethernet network, an Infiniband network, SCSI RDMA over a network  115 , a storage area network (SAN), a local area network (LAN), a wide area network (WAN) such as the Internet, another wired and/or wireless network  115 , or the like. 
     The computing device  110  may further comprise a non-transitory, computer readable storage medium  114 . The computer readable storage medium  114  may comprise executable instructions configured to cause the computing device  110  (e.g., processor  111 ) to perform steps of one or more of the methods disclosed herein. Alternatively, or in addition, the memory recycling component  150  may be embodied as one or more computer readable instructions stored on the non-transitory storage medium  114 . 
     The non-volatile memory system  102 , in the depicted embodiment, includes a memory recycling component  150 . The memory recycling component  150 , in one embodiment, is configured to recycle portions of storage elements for the non-volatile memory device  120  described below. The memory recycling component  150 , in certain embodiments, may detect a failure of a storage element during an operation. The memory recycling component  150  may also perform a test on the storage element. The memory recycling component  150  may enable a portion of the storage element for use in operations in response to the portion of the storage element passing the test. Thus, portions of storage elements may be recycled. 
     In one embodiment, the memory recycling component  150  may comprise logic hardware of one or more non-volatile memory devices  120 , such as a non-volatile memory media controller  126 , a non-volatile memory element  123 , a device controller, a field-programmable gate array (FPGA) or other programmable logic, firmware for an FPGA or other programmable logic, microcode for execution on a microcontroller, an application-specific integrated circuit (ASIC), or the like. In another embodiment, the memory recycling component  150  may comprise executable software code, such as a device driver or the like, stored on the computer readable storage medium  114  for execution on the processor  111 . In a further embodiment, the memory recycling component  150  may include a combination of both executable software code and logic hardware. 
     In one embodiment, the memory recycling component  150  is configured to receive storage requests from a device driver or other executable application via a bus  125  or the like. The memory recycling component  150  may be further configured to transfer data to/from a device driver and/or storage clients  116  via the bus  125 . Accordingly, the memory recycling component  150 , in some embodiments, may comprise and/or be in communication with one or more direct memory access (DMA) modules, remote DMA modules, bus controllers, bridges, buffers, and so on to facilitate the transfer of storage requests and associated data. In another embodiment, the memory recycling component  150  may receive storage requests as an API call from a storage client  116 , as an IO-CTL command, or the like. 
     According to various embodiments, a non-volatile memory controller  126  in communication with one or more memory recycling components  150  may manage one or more non-volatile memory devices  120  and/or non-volatile memory elements  123 . The non-volatile memory device(s)  120  may comprise recording, memory, and/or storage devices, such as solid-state storage device(s) and/or semiconductor storage device(s) that are arranged and/or partitioned into a plurality of addressable media storage locations. As used herein, a media storage location refers to any physical unit of memory (e.g., any quantity of physical storage media on a non-volatile memory device  120 ). Memory units may include, but are not limited to: pages, memory divisions, blocks, sectors, collections or sets of physical storage locations (e.g., logical pages, logical blocks), or the like. 
     A device driver and/or the non-volatile memory media controller  126 , in certain embodiments, may present a logical address space  134  to the storage clients  116 . As used herein, a logical address space  134  refers to a logical representation of memory resources. The logical address space  134  may comprise a plurality (e.g., range) of logical addresses. As used herein, a logical address refers to any identifier for referencing a memory resource (e.g., data), including, but not limited to: a logical block address (LBA), cylinder/head/sector (CHS) address, a file name, an object identifier, an inode, a Universally Unique Identifier (UUID), a Globally Unique Identifier (GUID), a hash code, a signature, an index entry, a range, an extent, or the like. 
     A device driver for the non-volatile memory device  120  may maintain metadata  135 , such as a logical to physical address mapping structure, to map logical addresses of the logical address space  134  to media storage locations on the non-volatile memory device(s)  120 . A device driver may be configured to provide storage services to one or more storage clients  116 . The storage clients  116  may include local storage clients  116  operating on the computing device  110  and/or remote, storage clients  116  accessible via the network  115  and/or network interface  113 . The storage clients  116  may include, but are not limited to: operating systems, file systems, database applications, server applications, kernel-level processes, user-level processes, applications, and the like. 
     A device driver may be communicatively coupled to one or more non-volatile memory devices  120 . The one or more non-volatile memory devices  120  may include different types of non-volatile memory devices including, but not limited to: solid-state storage devices, semiconductor storage devices, SAN storage resources, or the like. The one or more non-volatile memory devices  120  may comprise one or more respective non-volatile memory media controllers  126  and non-volatile memory media  122 . A device driver may provide access to the one or more non-volatile memory devices  120  via a traditional block I/O interface  131 . Additionally, a device driver may provide access to enhanced functionality through the SCM interface  132 . The metadata  135  may be used to manage and/or track data operations performed through any of the Block I/O interface  131 , SCM interface  132 , cache interface  133 , or other, related interfaces. 
     The cache interface  133  may expose cache-specific features accessible via a device driver for the non-volatile memory device  120 . Also, in some embodiments, the SCM interface  132  presented to the storage clients  116  provides access to data transformations implemented by the one or more non-volatile memory devices  120  and/or the one or more non-volatile memory media controllers  126 . 
     A device driver may present a logical address space  134  to the storage clients  116  through one or more interfaces. As discussed above, the logical address space  134  may comprise a plurality of logical addresses, each corresponding to respective media locations of the one or more non-volatile memory devices  120 . A device driver may maintain metadata  135  comprising any-to-any mappings between logical addresses and media locations, or the like. 
     A device driver may further comprise and/or be in communication with a non-volatile memory device interface  139  configured to transfer data, commands, and/or queries to the one or more non-volatile memory devices  120  over a bus  125 , which may include, but is not limited to: a memory bus of a processor  111 , a peripheral component interconnect express (PCI Express or PCIe) bus, a serial Advanced Technology Attachment (ATA) bus, a parallel ATA bus, a small computer system interface (SCSI), FireWire, Fibre Channel, a Universal Serial Bus (USB), a PCIe Advanced Switching (PCIe-AS) bus, a network  115 , Infiniband, SCSI RDMA, or the like. The non-volatile memory device interface  139  may communicate with the one or more non-volatile memory devices  120  using input-output control (IO-CTL) command(s), IO-CTL command extension(s), remote direct memory access, or the like. 
     The communication interface  113  may comprise one or more network interfaces configured to communicatively couple the computing device  110  and/or the non-volatile memory controller  126  to a network  115  and/or to one or more remote, network-accessible storage clients  116 . The storage clients  116  may include local storage clients  116  operating on the computing device  110  and/or remote, storage clients  116  accessible via the network  115  and/or the network interface  113 . The non-volatile memory controller  126  is part of and/or in communication with one or more non-volatile memory devices  120 . Although  FIG. 1A  depicts a single non-volatile memory device  120 , the disclosure is not limited in this regard and could be adapted to incorporate any number of non-volatile memory devices  120 . 
     The non-volatile memory device  120  may comprise one or more elements  123  of non-volatile memory media  122 , which may include but is not limited to: ReRAM, Memristor memory, programmable metallization cell memory, phase-change memory (PCM, PCME, PRAM, PCRAM, ovonic unified memory, chalcogenide RAM, or C-RAM), NAND flash memory (e.g., 2D NAND flash memory, 3D NAND flash memory), NOR flash memory, nano random access memory (nano RAM or NRAM), nanocrystal wire-based memory, silicon-oxide based sub-10 nanometer process memory, graphene memory, Silicon-Oxide-Nitride-Oxide-Silicon (SONOS), programmable metallization cell (PMC), conductive-bridging RAM (CBRAM), magneto-resistive RAM (MRAM), magnetic storage media (e.g., hard disk, tape), optical storage media, or the like. The one or more elements  123  of non-volatile memory media  122 , in certain embodiments, comprise storage class memory (SCM). 
     While legacy technologies such as NAND flash may be block and/or page addressable, storage class memory, in one embodiment, is byte addressable. In further embodiments, storage class memory may be faster and/or have a longer life (e.g., endurance) than NAND flash; may have a lower cost, use less power, and/or have a higher storage density than DRAM; or offer one or more other benefits or improvements when compared to other technologies. For example, storage class memory may comprise one or more non-volatile memory elements  123  of ReRAM, Memristor memory, programmable metallization cell memory, phase-change memory, nano RAM, nanocrystal wire-based memory, silicon-oxide based sub-10 nanometer process memory, graphene memory, SONOS memory, PMC memory, CBRAM, MRAM, and/or variations thereof. 
     While the non-volatile memory media  122  is referred to herein as “memory media,” in various embodiments, the non-volatile memory media  122  may more generally comprise one or more non-volatile recording media capable of recording data, which may be referred to as a non-volatile memory medium, a non-volatile storage medium, or the like. Further, the non-volatile memory device  120 , in various embodiments, may comprise a non-volatile recording device, a non-volatile memory device, a non-volatile storage device, or the like. 
     The non-volatile memory media  122  may comprise one or more non-volatile memory elements  123 , which may include, but are not limited to: chips, packages, planes, die, or the like. A non-volatile memory media controller  126  may be configured to manage data operations on the non-volatile memory media  122 , and may comprise one or more processors, programmable processors (e.g., FPGAs), ASICs, micro-controllers, or the like. In some embodiments, the non-volatile memory media controller  126  is configured to store data on and/or read data from the non-volatile memory media  122 , to transfer data to/from the non-volatile memory device  120 , and so on. 
     The non-volatile memory media controller  126  may be communicatively coupled to the non-volatile memory media  122  by way of a bus  127 . The bus  127  may comprise an I/O bus for communicating data to/from the non-volatile memory elements  123 . The bus  127  may further comprise a control bus for communicating addressing and other command and control information to the non-volatile memory elements  123 . In some embodiments, the bus  127  may communicatively couple the non-volatile memory elements  123  to the non-volatile memory media controller  126  in parallel. This parallel access may allow the non-volatile memory elements  123  to be managed as a group, forming a logical memory element  129 . The logical memory element may be partitioned into respective logical memory units (e.g., logical pages) and/or logical memory divisions (e.g., logical blocks). The logical memory units may be formed by logically combining physical memory units of each of the non-volatile memory elements. 
     The non-volatile memory controller  126  may organize a block of word lines within a non-volatile memory element  123 , in certain embodiments, using addresses of the word lines, such that the word lines are logically organized into a monotonically increasing sequence (e.g., decoding and/or translating addresses for word lines into a monotonically increasing sequence, or the like). In a further embodiment, word lines of a block within a non-volatile memory element  123  may be physically arranged in a monotonically increasing sequence of word line addresses, with consecutively addressed word lines also being physically adjacent (e.g., WL 0 , WL 1 , WL 2 , WLN). 
     The non-volatile memory controller  126  may comprise and/or be in communication with a device driver executing on the computing device  110 . A device driver may provide storage services to the storage clients  116  via one or more interfaces  131 ,  132 , and/or  133 . In some embodiments, a device driver provides a block-device I/O interface  131  through which storage clients  116  perform block-level I/O operations. Alternatively, or in addition, a device driver may provide a storage class memory (SCM) interface  132 , which may provide other storage services to the storage clients  116 . In some embodiments, the SCM interface  132  may comprise extensions to the block device interface  131  (e.g., storage clients  116  may access the SCM interface  132  through extensions or additions to the block device interface  131 ). Alternatively, or in addition, the SCM interface  132  may be provided as a separate API, service, and/or library. A device driver may be further configured to provide a cache interface  133  for caching data using the non-volatile memory system  102 . 
     A device driver may further comprise a non-volatile memory device interface  139  that is configured to transfer data, commands, and/or queries to the non-volatile memory media controller  126  over a bus  125 , as described above. 
       FIG. 1B  illustrates an embodiment of a non-volatile storage device  210  that may include one or more memory die or chips  212 . Memory die  212 , in some embodiments, includes an array (two-dimensional or three dimensional) of memory cells  200 , die controller  220 , and read/write circuits  230 A/ 230 B. In one embodiment, access to the memory array  200  by the various peripheral circuits is implemented in a symmetric fashion, on opposite sides of the array, so that the densities of access lines and circuitry on each side are reduced by half. The read/write circuits  230 A/ 230 B, in a further embodiment, include multiple sense blocks  250  which allow a page of memory cells to be read or programmed in parallel. 
     The memory array  200 , in various embodiments, is addressable by word lines via row decoders  240 A/ 240 B and by bit lines via column decoders  242 A/ 242 B. In some embodiments, a controller  244  is included in the same memory device  210  (e.g., a removable storage card or package) as the one or more memory die  212 . Commands and data are transferred between the host and controller  244  via lines  232  and between the controller and the one or more memory die  212  via lines  234 . One implementation can include multiple chips  212 . 
     Die controller  220 , in one embodiment, cooperates with the read/write circuits  230 A/ 230 B to perform memory operations on the memory array  200 . The die controller  220 , in certain embodiments, includes a memory recycling component  150 , a state machine  222 , and an on-chip address decoder  224 . In one embodiment, the state machine  222  comprises at least a portion of the memory recycling component  150 . In a further embodiment, the controller  244  comprises at least a portion of the memory recycling component  150 . In various embodiments, one or more of the sense blocks  250  comprises at least a portion of the memory recycling component  150 . 
     The memory recycling component  150 , in one embodiment, is configured to identify a failure of a memory device during a multi-plane operation, perform an erase operation on one or more planes of the memory device, and perform a program operation on one or more successfully erased planes of the memory device. 
     The state machine  222 , in one embodiment, provides chip-level control of memory operations. The on-chip address decoder  224  provides an address interface to convert between the address that is used by the host or a memory controller to the hardware address used by the decoders  240 A,  240 B,  242 A,  242 B. In certain embodiments, the state machine  222  includes an embodiment of the memory recycling component  150 . The memory recycling component  150 , in certain embodiments, is embodied as software in a device driver, hardware in a device controller  244 , and/or hardware in a die controller  220  and/or state machine  222 . 
     In one embodiment, one or any combination of die controller  220 , memory recycling component  150 , decoder circuit  224 , state machine circuit  222 , decoder circuit  242 A, decoder circuit  242 B, decoder circuit  240 A, decoder circuit  240 B, read/write circuits  230 A, read/write circuits  230 B, and/or controller  244  can be referred to as one or more managing circuits. 
       FIG. 2  depicts one embodiment of a NAND string comprising a plurality of storage elements. The NAND string depicted in  FIG. 2 , in some embodiments, includes four transistors  260 ,  262 ,  264 ,  266  connected in series and located between a first select transistor  270  and a second select transistor  272 . In some embodiments, a transistor  260 ,  262 ,  264 ,  266  includes a control gate and a floating gate. A control gate  290 ,  292 ,  294 ,  296 , in one embodiment, is connected to, or comprises a portion of, a word line. In a further embodiment, a transistor  260 ,  262 ,  264 ,  266  is a storage element, storage cell, or the like, also referred to as a memory cell. In some embodiments, a storage element may include multiple transistors  260 ,  262 ,  264 ,  266 . 
     The first select transistor  270 , in some embodiments, gates/connects the NAND string connection to a bit line  280  via a drain select gate SGD. The second select transistor  272 , in certain embodiments, gates/connects the NAND string connection to a source line  282  via a source select gate SGS. The first select transistor  270 , in a further embodiment, is controlled by applying a voltage to a corresponding select gate  286 . The second select transistor  272 , in some embodiments, is controlled by applying a voltage to corresponding select gate  288 . 
     As shown in  FIG. 2 , the source line  282 , in one embodiment, is connected to the sources of each transistor/storage cell  260 ,  262 ,  264 ,  266  in the NAND string. The NAND string, in some embodiments, may include some storage elements  260 ,  262 ,  264 ,  266  that have been programmed and some storage elements  260 ,  262 ,  264 ,  266  that have not been programmed. As described in more detail below, the memory recycling component  150  controls whether portions of a storage device, such as a NAND string, uses are used for operations. 
       FIG. 3  is a circuit diagram depicting a plurality of NAND strings  320 ,  340 ,  360 ,  380 . An architecture for a flash memory system using a NAND structure may include several NAND strings  320 ,  340 ,  360 ,  380 . For example,  FIG. 3  illustrates NAND strings  320 ,  340 ,  360 ,  380  in a memory array  200  that includes multiple NAND strings  320 ,  340 ,  360 ,  380 . In the depicted embodiment, each NAND string  320 ,  340 ,  360 ,  380  includes drain select transistors  322 ,  342 ,  362 ,  382 , source select transistors  327 ,  347 ,  367 ,  387 , and storage elements  323 - 326 ,  343 - 346 ,  363 - 366 ,  383 - 386 . While four storage elements  323 - 326 ,  343 - 346 ,  363 - 366 ,  383 - 386  per NAND string  320 ,  340 ,  360 ,  380  are illustrated for simplicity, some NAND strings  320 ,  340 ,  360 ,  380  can include any number of storage elements, e.g., thirty-two, sixty-four, or the like storage elements. 
     NAND strings  320 ,  340 ,  360 ,  380 , in one embodiment, are connected to a source line  319  by source select transistors  327 ,  347 ,  367 ,  387 . A selection line SGS may be used to control the source side select transistors. The various NAND strings  320 ,  340 ,  360 ,  380 , in one embodiment, are connected to bit lines  321 ,  341 ,  361 ,  381  by drain select transistors  322 ,  342 ,  362 ,  382 . The drain select transistors  322 ,  342 ,  362 ,  382  may be controlled by a drain select line SGD. In some embodiments, the select lines do not necessarily need to be in common among the NAND strings  320 ,  340 ,  360 ,  380 ; that is, different select lines can be provided for different NAND strings  320 ,  340 ,  360 ,  380 . 
     As described above, each word line WL 0 -WLn comprises one or more storage elements  323 - 383 ,  324 - 384 ,  325 - 385 ,  326 - 386 . In the depicted embodiment, each bit line  321 ,  341 ,  361 ,  381  and the respective NAND string  320 ,  340 ,  360 ,  380  comprise the columns of the memory array  200 , storage block, erase block, or the like. The word lines WL 0 -WLn, in some embodiments, comprise the rows of the memory array  200 , storage block, erase block, or the like. Each word line WL 0 -WLn, in some embodiments, connects the control gates of each storage element  323 - 383 ,  324 - 384 ,  325 - 385 ,  326 - 386  in a row. Alternatively, the control gates may be provided by the word lines WL 0 -WLn themselves. In some embodiments, a word line WL 0 -WLn may include tens, hundreds, thousands, millions, or the like of storage elements  323 - 383 ,  324 - 384 ,  325 - 385 ,  326 - 386 . 
     In one embodiment, each storage element  323 - 326 ,  343 - 346 ,  363 - 366 ,  383 - 386  is configured to store data. For example, when storing one bit of digital data, the range of possible threshold voltages (“VTH”) of each storage element  323 - 326 ,  343 - 346 ,  363 - 366 ,  383 - 386  may be divided into two ranges which are assigned logical data “1” and “0.” In one example of a NAND type flash memory, the VTH may be negative after the storage elements  323 - 326 ,  343 - 346 ,  363 - 366 ,  383 - 386  are erased, and defined as logic “1.” In one embodiment, the VTH after a program operation is positive and defined as logic “0.” 
     When the VTH is negative and a read is attempted, in some embodiments, storage elements  323 - 326 ,  343 - 346 ,  363 - 366 ,  383 - 386  will turn on to indicate logic “1” is being stored. When the VTH is positive and a read operation is attempted, in a further embodiment, a storage element will not turn on, which indicates that logic “0” is stored. Each storage element  323 - 383 ,  324 - 384 ,  325 - 385 ,  326 - 386  may also store multiple levels of information, for example, multiple bits of digital data. In such an embodiment, the range of VTH value is divided into the number of levels of data. For example, if four levels of information can be stored in each storage element  323 - 326 ,  343 - 346 ,  363 - 366 ,  383 - 386 , there will be four VTH ranges assigned to the data values “11”, “10”, “01”, and “00.” 
     In one example of a NAND type memory, the VTH after an erase operation may be negative and defined as “11.” Positive VTH values may be used for the states of “10”, “01”, and “00.” In one embodiment, the specific relationship between the data programmed into the storage elements  323 - 326 ,  343 - 346 ,  363 - 366 ,  383 - 386  and the threshold voltage ranges of the storage elements  323 - 326 ,  343 - 346 ,  363 - 366 ,  383 - 386  depends upon the data encoding scheme adopted for the storage elements  323 - 326 ,  343 - 346 ,  363 - 366 ,  383 - 386 . 
     In some embodiments, portions of the storage elements  323 - 326 ,  343 - 346 ,  363 - 366 ,  383 - 386  may be defective. In such an embodiment, the memory recycling component  150  may manage which portions of the storage elements  323 - 326 ,  343 - 346 ,  363 - 366 ,  383 - 386  are used for operations. 
       FIG. 4  illustrates one embodiment of a cross-sectional view of a 3D, vertical NAND flash memory structure  429  or string  429 . In one embodiment, the vertical column  432  is round and includes four layers; however, in other embodiments more or less than four layers can be included and other shapes can be used (e.g., a “U” shape instead of an “I” shape or the like). In one embodiment, a vertical column  432  includes an inner core layer  470  that is made of a dielectric, such as SiO2. Other materials can also be used. Surrounding inner core  470  is polysilicon channel  471 . Materials other than polysilicon can also be used. Note that it is the channel  471  that connects to the bit line. Surrounding channel  471  is a tunneling dielectric  472 . In one embodiment, tunneling dielectric  472  has an ONO structure. Surrounding tunneling dielectric  472  is a shared charge trapping layer  473 , such as (for example) Silicon Nitride. Other materials and structures can also be used. The technology described herein is not limited to any particular material or structure. 
       FIG. 4  depicts dielectric layers DLL 49 , DLL 50 , DLL 51 , DLL 52  and DLL 53 , as well as word line layers WLL 43 , WLL 44 , WLL 45 , WLL 46 , and WLL 47 . Each of the word line layers includes a word line region  476  surrounded by an aluminum oxide layer  477 , which is surrounded by a blocking oxide (SiO2) layer  478 . The physical interaction of the word line layers with the vertical column forms the memory cells. Thus, a memory cell, in one embodiment, comprises channel  471 , tunneling dielectric  472 , charge trapping layer  473  (e.g., shared with other memory cells), blocking oxide layer  478 , aluminum oxide layer  477  and word line region  476 . In some embodiments, the blocking oxide layer  478  and aluminum oxide layer  477 , may be replaced by a single layer of material with insulating properties or by more than 2 layers of different material with insulating properties. Furthermore, the materials used are not limited to silicon dioxide (SiO2) or aluminum oxide. For example, word line layer WLL 47  and a portion of vertical column  432  comprise a memory cell MC 1 . Word line layer WLL 46  and a portion of vertical column  432  comprise a memory cell MC 2 . Word line layer WLL 45  and a portion of vertical column  432  comprise a memory cell MC 3 . Word line layer WLL 44  and a portion of vertical column  432  comprise a memory cell MC 4 . Word line layer WLL 43  and a portion of vertical column  432  comprise a memory cell MC 5 . In other architectures, a memory cell may have a different structure; however, the memory cell would still be the storage unit. 
     When a memory cell is programmed, electrons are stored in a portion of the charge trapping layer  473  which is associated with the memory cell. These electrons are drawn into the charge trapping layer  473  from the channel  471 , through the tunneling dielectric  472 , in response to an appropriate voltage on word line region  476 . The threshold voltage (Vth) of a memory cell is increased in proportion to the amount of stored charge. In one embodiment, the programming is achieved through Fowler-Nordheim tunneling of the electrons into the charge trapping layer. During an erase operation, the electrons return to the channel or holes are injected into the charge trapping layer to recombine with electrons. In one embodiment, erasing is achieved using hole injection into the charge trapping layer via a physical mechanism such as gate induced drain leakage (GIDL). 
     Storage cells in the same location or position in different memory structures  429  (e.g., different NAND strings  429 ) on different bit lines, in certain embodiments, may be on the same word line. Each word line may store one page of data, such as when 1-bit of data is stored per cell (SLC); two pages of data, such as when 2-bits of data are stored per cell (MLC); three pages of data, such as when 3-bits of data are stored per cell (TLC); four pages of data, such as when 4-bits of data are stored per cell (QLC); or another number of pages of data. 
     In the depicted embodiment, a vertical, 3D NAND flash memory structure  429  comprises an “I” shaped memory structure  429 . In other embodiments, a vertical, 3D NAND flash memory structure  429  may comprise a “U” shaped structure, or may have another vertical and/or stacked architecture. In certain embodiments, four sets of strings  429  (e.g., four sets of 48 word lines, or another predefined number of word lines) may form an erase block, while in other embodiments, fewer or more than four sets of strings  429  may form an erase block. As may be appreciated, any suitable number of storage cells may be part of a single string  429 . In one embodiment, a single string  429  includes 48 storage cells. 
       FIG. 5  depicts one embodiment of a memory recycling component  150 . The memory recycling component  150  may be substantially similar to the memory recycling component  150  described above with regard to  FIGS. 1A, 1B, 2 , and/or  3 . In general, as described above, the memory recycling component  150  detects a failure of a storage element during an operation, performs a test on the storage element, and enables a portion of the storage element for use in operations in response to the portion of the storage element passing the test. Accordingly, the memory recycling component  150  may facilitate reusing portions of storage elements that have been identified as having defects. In the depicted embodiment, the memory recycling component  150  includes a failure detection circuit  502 , a test circuit  504 , and a recycle circuit  506 . 
     In one embodiment, the failure detection circuit  502  detects a failure of a storage element during an operation. The failure may be detected in response to the storage element having a high error rate, invalid data, an invalid checksum, and so forth. In various embodiments, the operation includes a multi-plane operation. As used herein, performing a multi-plane operation may include performing any operation involving a storage element having multiple-planes (e.g., multi-plane). The operation may be any suitable operation, such as a read operation, a write operation, a program operation, a verify operation, and so forth. In some embodiments, the failure detection circuit  502  may mark multiple planes of a block as bad during a multi-plane operation even though only one or more of the multiple planes may have errors (e.g., an error rate that is too high). 
     In certain embodiments, the test circuit  504  performs a test on the storage element. In various embodiments, the test includes one or more of an erase operation, a program operation, and a read operation. The test may be used to determine whether at least a portion of the storage element functions properly so that the portion of the storage element may be used for at least some operations. In various embodiments, performing the test includes performing an erase operation on a portion of the storage element, performing a program operation on a successfully erased portion of the storage element, and/or performing a read operation on a successfully programmed portion of the storage element. In some embodiments, the test circuit  504  may use a test pattern to test the storage element to determine if the storage element is acceptable for use with user data. In certain embodiments, the test pattern may be user data that has been programmed to a different location and still exists at the different location. 
     In some embodiments, the recycle circuit  506  enables a portion of the storage element for use in operations in response to the portion of the storage element passing the test. In certain embodiments, passing the test includes being successfully read. In some embodiments, the passing the test includes being successfully erased and/or successfully programed. In various embodiments, performing the program operation includes programming the successfully erased portion with a test pattern. In some embodiments, the portion of the storage element enabled by the recycle circuit  506  includes a successfully read portion of the storage element. In one embodiment, the recycle circuit  506  removes the portion of the storage element (that has passed the test) from a bad storage element pool and puts the portion of the storage element into a good storage element pool, while the remainder of the storage element may remain in the bad storage element pool. In certain embodiments, the storage element includes one or more of a word line, a string, and a block. In various embodiments, the storage element includes multiple blocks, and the portion of the storage element includes one or more blocks of the multiple blocks. In such embodiments, at least one block of the multiple blocks remains disabled for use in operations. In one embodiment, the storage element includes multiple planes, and the portion of the storage element includes one or more planes of the multiple planes. In some embodiments, the storage element is withdrawn from use for operations in response to the failure of the storage element during the operation. 
     Turning to  FIG. 6 , a further embodiment of a memory recycling component  150  is illustrated. The memory recycling component  150  may be substantially similar to the memory recycling component  150  described above with regard to  FIGS. 1A, 1B, 2, 3 , and/or  5 . In the depicted embodiment, the memory recycling component  150  includes the failure detection circuit  502 , the test circuit  504 , and the recycle circuit  506  and further includes an erase operation circuit  602 , a program operation circuit  604 , and a read operation circuit  606 . The failure detection circuit  502 , the test circuit  504 , and the recycle circuit  506  may be substantially as described above with regard to  FIG. 5 . 
     In one embodiment, the erase operation circuit  602  is used to perform an erase operation on a failed storage element, such as a failed multi-plane storage element, to facilitate testing the failed storage element to determine whether a portion of the failed storage element may be moved from an unused memory resource pool to a resource pool of memory that may be used. 
     In certain embodiments, the program operation circuit  604  is used to perform a program operation on a failed storage element, such as a failed multi-plane storage element, to facilitate testing the failed storage element to determine whether a portion of the failed storage element may be moved from an unused memory resource pool to a resource pool of memory that may be used. 
     In various embodiments, the read operation circuit  606  is used to perform a read operation on a failed storage element, such as a failed multi-plane storage element, to facilitate testing the failed storage element to determine whether a portion of the failed storage element may be moved from an unused memory resource pool to a resource pool of memory that may be used. 
       FIG. 7  depicts one embodiment of a method  700  for multi-plane memory management. The method  700  begins and the failure detection circuit  502  observes  702  a defect in an operation involving a multi-plane memory block. The operation command may be a read command, a write command, a program command, a verify command, and so forth. The failure detection circuit  502  labels  704  the multi-plane memory block as a defective memory block. In certain embodiments, the memory recycling component  150  may manage use of the defective memory block. In one embodiment, the memory recycling component  150  cycles  706  use of memory blocks without using the defective memory block. For example, the memory recycling component  150  may cycle memory blocks using user data in between user program operations without mapping user data to the defective memory block. In some embodiments, the defective memory block may be indicated as invalid. The test circuit  504  tests  708  the defective memory block. Moreover, the recycle circuit  506  returns  710  portions of the defective memory block to use, and the method  700  ends. Accordingly, portions of defective multi-plane memory blocks may be returned to use. In various embodiments, the recycle circuit  506  places the portions of the defective memory block into a reserve pool. 
       FIG. 8  is a schematic flow chart diagram illustrating a further embodiment of a method  800  for multi-plane memory management. The method  800  begins, and the failure detection circuit  502  identifies  802  a failure of a memory device during a multi-plane operation. The memory device may be a multi-plane device, a block, a word line, a string, or another memory device. In one embodiment, the failure detection circuit  502 , in response to identifying the failure of the memory device, removes the memory device from use in operations (e.g., marks the memory device as bad). In such embodiments, the failure detection circuit  502 , in response to removing the memory device from use in operations, waits a predetermined period of time prior to performing the erase operation on the plane of the memory device. 
     Moreover, the test circuit  504  performs  804  an erase operation on a plane of the memory device. The test circuit  504  performs  806  a program operation on a successfully erased plane of the memory device, and the method  800  ends. By using the method  800 , portions of defective multi-plane memory devices may be tested to be returned to use. 
     In some embodiments, the test circuit  504  performs  808  a read operation on a successfully programed plane of the memory device. In such embodiments, the recycle circuit  506  enables a successfully read plane of the memory device for use in operations. In certain embodiments, the recycle circuit  506  enable a successfully programed plane of the memory device for use in operations. In various embodiments, the test circuit  504  may perform  808  the read operation on a portion of a memory device (e.g., an entire plane). In certain embodiments, the test circuit  504  may perform  808  the read operation on a subset of a portion of a memory device (e.g., a subset of a plane). For example, in one embodiment, multiple pages may be shared by the same memory cells. In such an embodiment, only lower page cells may be tested or only upper page cells may be tested. By testing a subset of a portion of a memory device, a speed of testing may be increased thereby reducing a time occupied by testing. 
     A means for checking operation of a memory block, the memory block being removed from use in operations in response to a failure of the memory block during an operation, in various embodiments, may include one or more of a memory recycling component  150 , a test circuit  504 , a non-volatile memory device  120 , a non-volatile memory medium controller  126 , a non-volatile memory device interface  139 , a host computing device  110 , a device driver, a controller (e.g., a device driver, or the like) executing on a host computing device  110 , a processor  111 , an FPGA, an ASIC, other logic hardware, and/or other executable code stored on a computer readable storage medium. Other embodiments may include similar or equivalent means for checking operation of a memory block, the memory block being removed from use in operations in response to a failure of the memory block during an operation. 
     A means for returning at least a first plane of the memory block for use in operations in response to a successful operation check, wherein a second plane of the memory block remains unused for operations, in certain embodiments, may include one or more of a memory recycling component  150 , a recycle circuit  506 , a non-volatile memory device  120 , a non-volatile memory medium controller  126 , a non-volatile memory device interface  139 , a host computing device  110 , a device driver, a controller (e.g., a device driver, or the like) executing on a host computing device  110 , a processor  111 , an FPGA, an ASIC, other logic hardware, and/or other executable code stored on a computer readable storage medium. Other embodiments may include similar or equivalent means for returning at least a first plane of the memory block for use in operations in response to a successful operation check, wherein a second plane of the memory block remains unused for operations. 
     A means for identifying the memory block for removal from use in operations, in some embodiments, may include one or more of a memory recycling component  150 , a failure detection circuit  502 , a non-volatile memory device  120 , a non-volatile memory medium controller  126 , a non-volatile memory device interface  139 , a host computing device  110 , a device driver, a controller (e.g., a device driver, or the like) executing on a host computing device  110 , a processor  111 , an FPGA, an ASIC, other logic hardware, and/or other executable code stored on a computer readable storage medium. Other embodiments may include similar or equivalent means for identifying the memory block for removal from use in operations. 
     A means for determining to check operation of the memory block, in one embodiment, may include one or more of a memory recycling component  150 , a test circuit  504 , a non-volatile memory device  120 , a non-volatile memory medium controller  126 , a non-volatile memory device interface  139 , a host computing device  110 , a device driver, a controller (e.g., a device driver, or the like) executing on a host computing device  110 , a processor  111 , an FPGA, an ASIC, other logic hardware, and/or other executable code stored on a computer readable storage medium. Other embodiments may include similar or equivalent means for determining to check operation of the memory block. 
     The present disclosure may be embodied in other specific forms without departing from its spirit or essential characteristics. The described embodiments are to be considered in all respects only as illustrative and not restrictive. The scope of the disclosure is, therefore, indicated by the appended claims rather than by the foregoing description. All changes which come within the meaning and range of equivalency of the claims are to be embraced within their scope.