Patent Publication Number: US-9838044-B1

Title: Noise-predictive detector adaptation with corrected data

Description:
CROSS REFERENCE TO RELATED APPLICATION 
     The present disclosure is a continuation application of and claims the benefit of priority under 35 USC 120 of U.S. application Ser. No. 13/546,859, filed Jul. 11, 2012, which claims the benefit of the priority of U.S. Provisional Application Ser. No. 61/507,004, filed Jul. 12, 2011, the above-identified applications are incorporated herein by reference in their entirety. 
    
    
     BACKGROUND 
     The present disclosure describes systems and techniques relating to decoders and decoding techniques. 
     Basic components of a communication system include a transmitter and a receiver. The transmitter and receiver can communicate over a channel such as a wireless channel, optical channel, or wired channel. Other types of channels are possible. For example, the channel can be a read channel formed by reading encoded information from a surface of a hard drive disk. Factors such as noise corruption and channel distortion can introduce errors into data transmitted by the transmitter. To address such introduced errors, the transmitter can encode data. 
     SUMMARY 
     The present disclosure includes apparatus, systems, and techniques relating to noise-predictive detector adaptation. A described technique includes operating a decoder to decode a received encoded signal based on estimation parameters to produce paths including a first path and a second path, the second path being an alternate to the first path, determining a decoded path based on at least a portion of the paths, determining a winning path of the first path and the second path based on whether the decoded path matches the first path or the second path, and updating the estimation parameters based on one or more error terms and the winning path to favor selection of the winning path by the decoder and to disfavor selection of a losing path of the first and second paths by the decoder. 
     These and other implementations can include one or more of the following features. Updating the estimation parameters can include adjusting the estimation parameters to cause, in the decoder, a decrease in a metric associated with the winning path for a subsequent iteration of the decoder. In some implementations, the paths are associated with respective path metric values where the first path is associated with a smallest one of the path metric values. Implementations can include selecting the second path such that a path metric difference between the first path and the second path is less than a threshold. Implementations can include filtering the received encoded signal to produce sample codewords. The decoder can be configured to use the sample codewords to produce the paths. Determining the decoded path can include applying an error correction code to one or more of the paths to determine a correct path. 
     Implementations can include determining the estimation parameters based on first estimation parameters and second estimation parameters; and determining the first estimation parameters based on one or more of the sample codewords and a preliminary detection of one or more codewords indicated by the received encoded signal. The first and the second estimation parameters can include filter coefficients and a mean shift parameter. 
     Updating the estimation parameters can include adjusting the second estimation parameters based on the one or more error terms and the winning path. Updating the estimation parameters can include combining the first estimation parameters and second estimation parameters to produce combined estimation parameters; updating the combined estimation parameters based on the one or more error terms and the winning path to produce updated combined estimation parameters; and updating the second estimation parameters based on the updated combined estimation parameters and the first estimation parameters. Determining the estimation parameters can include combining the first estimation parameters and the second estimation parameters using a normalization technique. 
     A receiver can include a decoder configured to decode a received encoded signal based on estimation parameters to produce paths including a first path and a second path, the second path being an alternate to the first path. The receiver can include circuitry configured to determine a decoded path based on at least a portion of the paths. Further, the receiver can include an updater configured to perform operations that include determining a winning path of the first path and the second path based on whether the decoded path matches the first path or the second path; and updating the estimation parameters based on one or more error terms and the winning path to favor selection of the winning path by the decoder and to disfavor selection of a losing path of the first and second paths by the decoder in a subsequent iteration. 
     A decoder can be configured to process the sample codewords by iteratively processing codeword information and exchanging information between a soft output Viterbi algorithm (S OVA) decoder and a low density parity check (LDPC) decoder. The SOVA decoder can be configured to produce the paths based on the estimation parameters. The LDPC decoder can be configured to produce the decoded path. Other types of decoders are possible. 
     A system can include a filter to produce sample codewords based on a received encoded signal; a decoder configured to decode the sample codewords by iteratively processing codeword information and exchanging information between a soft input soft output (SISO) decoder and a code decoder, and an updater. Decoding the sample codewords can include operating the SISO decoder to produce a first path and a second path based on estimation parameters, the second path being an alternate to the first path, and operating the code decoder to produce a decoded path. The updater can be configured to determine a winning path of the first and second paths based on whether the decoded path matches the first path or the second path and update the estimation parameters based on one or more error terms and the winning path to favor selection of the winning path by the SISO decoder in a subsequent iteration and to disfavor selection of a losing path of the first and second paths by the decoder in the subsequent iteration. 
     The updater can be configured to perform operations such as determining the estimation parameters based on first estimation parameters and second estimation parameters, determining the first estimation parameters based on one or more of the sample codewords and a preliminary detection of one or more codewords indicated by the received encoded signal, combining the first estimation parameters and second estimation parameters to produce combined estimation parameters; updating the combined estimation parameters based on the one or more error terms and the winning path to produce updated combined estimation parameters; and updating the second estimation parameters based on the updated combined estimation parameters and the first estimation parameters. 
     Particular embodiments of the technology described in this document can be implemented so as to realize one or more of the following advantages. One or more described technologies can be used to improve a bit-error-rate (BER) performance of a receiver. One or more described techniques can be used to perform noise reduction (NR) estimation in addition to minimum mean square error (MMSE) estimation such that the estimation process is able to quickly converge and track changes in a read channel. 
     Details of one or more implementations are set forth in the accompanying drawings and the description below. Other features and advantages may be apparent from the description and drawings, and from the claims. 
    
    
     
       DRAWING DESCRIPTIONS 
         FIG. 1  shows an example architecture of a wireless communication system with a transmitter and a receiver. 
         FIG. 2  shows an example of an iterative decoder system. 
         FIG. 3  shows an example of a receiver system process that includes performing an adaptation technique. 
         FIG. 4  shows another example of a receiver system process that includes performing an adaptation technique. 
         FIG. 5  shows an example of selecting and storing event information from multiple decoder instances. 
         FIG. 6  shows an example of an event comparator of a receiver architecture. 
         FIG. 7  shows another example of a receiver system process that includes performing an adaptation technique. 
     
    
    
     Like reference symbols in the various drawings indicate like elements. 
     DETAILED DESCRIPTION 
     The systems and techniques described herein can be implemented as one or more devices, such as one or more integrated circuit (IC) devices in a wireless communication device, an optical communication device, or a computer readable storage device. For example, the systems and techniques disclosed can be implemented in a wireless local area network (WLAN) transceiver device (e.g., a WLAN chipset) suitable for use in an orthogonal frequency-division multiplexing (OFDM) multiple-input and multiple-output (MIMO) system. Further, the systems and techniques disclosed can be implemented in a computer storage device, such as a hard disk drive or an optical disk drive. For example, one or more described techniques and systems can be used to decode encoded data read from a surface of a magnetic disk. 
       FIG. 1  shows an example architecture of a wireless communication system  100  with a transmitter  101  and a receiver  102 . The transmitter  101  includes a media access controller (MAC)  105 , a physical layer (PHY)  108  that includes a code encoder  110 , and a channel interface  115  to transmit data over a channel  120 . The MAC  105  can provide user data to the PHY  108  for transmission. The PHY  108  can operate the code encoder  110  to encode data for transmission by using an error correction code (ECC) technique. For example, the code encoder  110  can include an low density parity check (LDPC) encoder or a turbo code encoder. An LDPC code, for example, is an error correcting code used to detect and correct errors when transmitting data over a noisy transmission channel such as channel  120 . Other types of encoders are possible. The receiver  102  includes a channel interface  130  to receive data over the channel  120 , an analog-to-digital converter (ADC)  140 , a finite impulse response (FIR) filter  150 , a FIR memory  160 , a decoder system  170 , and a MAC  180 . The MAC  108  can receive decoded user data from the decoder system  170  and can pass the user data to an application process. The decoder system  170  includes a code decoder  172 , a path decoder  174 , memory  176 , an updater  178 , and communications bus  171 . 
     In the receiver  102 , the analog signal received via the channel  120  is initially filtered by the channel interface  130 , and the filtered analog signal is sampled by the ADC  140 . The ADC samples are equalized by the FIR filter  150  and provided to the decoder system  170  by way of storing data in the FIR memory  160 . In some implementations, the FIR filter  150  can be configured to generate FIR sample codewords from a received encoded signal via the ADC  140  and store the sample codewords in the FIR memory  160 . 
     One or more of the decoders  172 ,  174  of the decoder system  170  can decode sample codewords, produced by the FIR filter  150 , based on estimation parameters. The updater  178  can include one or more estimators to estimate and update the estimation parameters. The estimators can include a minimum mean square error (MMSE) estimator and a noise reduction (NR) estimator. Estimation parameters can include filter coefficients and a mean shift value. Other types of estimation parameters are possible. In some implementations, the filter coefficients are provided to the FIR filter  150 . 
     The path decoder  174  of the decoder system  170  can be a soft input soft output (SISO) decoder such as a Soft Output Viterbi Algorithm (SOVA) decoder or a Bahl-Cocke-Jelinek-Raviv “BCJR” decoder. SOVA, for example, is based on the classical Viterbi algorithm and uses a modified path metric to take into account the a priori probabilities of input symbols or bits and produces a soft output indicating the reliability of a decision about the input symbols. In some implementations, the path decoder  174  is a hard-output based decoder. Various examples of a code decoder  172  include a LDPC decoder and a turbo code decoder. Other types of decoders are possible. 
     In some implementations, the path decoder  174  and the code decoder  172 , are configured to act together as an iterative decoder. For example, the path decoder  174  and the code decoder  172  can both be configured to iteratively process codeword information and pass resulting information back and forth such that each successive iteration improves overall data accuracy. The path decoder  174  receives the FIR sample codewords and, when available, prior information from the code decoder  172 . At an initial iteration, the prior information is set to zero for all bits in the iterative codeword. Based on the received FIR sample codewords and the prior information, the path decoder  174  produces reliability information. Reliability information from the path decoder  174  is forwarded to the code decoder  172 . The code decoder  172  generates updated reliability information based on code constraints, and sends the updated reliability information back to the path decoder  174 . This process is repeated till a stopping criterion has been met. 
       FIG. 2  shows an example of an iterative decoder system  201 . The system  201  includes a Viterbi decoder  203 , SOVA decoder  205 , LDPC decoder  210 , channel LLR decorrelator (CLD) mappers such as a first CLD mapper  215  and a second CLD mapper  220 , pseudo-random binary sequence (PRBS) generator  225 , selector  227 , NR estimator  230 , MMSE estimator  235 , and updater  240 . The system  201  includes memories such as a pre-decision memory  245 , FIR memory  250 , decision memory  255 , and event memory  260 . These memories can include storage space for multiple items such as information relating to multiple codewords that are being decoded by the system. In some implementations, the updater  240  includes the NR estimator  230  and the MMSE estimator  235 . 
     A FIR filter  247  processes a digital version of a received encoded signal  202  that is provided via a channel interface  209 . In some implementations, the channel interface  209  includes circuitry to couple with one or more antennas for receiving wireless communication signals. In some implementations, the channel interface  209  includes a read channel apparatus for reading data from a surface of a rotatable disk such as a magnetic disk or an optical disk. Based on the received encoded signal  202 , the filter  247  produces and stores FIR samples in the FIR memory  250 . The FIR filter  247  can be a filter that processes the received encoded signal  202  to produce a signal, for example, whose impulse response settles to zero in a finite number of sample intervals. 
     The Viterbi decoder  203  processes the FIR samples and produces hard decisions based on the FIR samples for each codeword. These hard decisions at this initial stage of the decoding pipeline can be referred to as pre-decisions. The Viterbi decoder  203  generates hard decision information that includes pre-decision bits and stores the pre-decision bits in the pre-decision memory  245 . Since the Viterbi decoder  203  may receive the FIR samples and process the information with a relatively short latency, Viterbi decoder  203  can act as a “preliminary” Viterbi decoder that quickly provides input signals for the rest of the system  201 . In this manner, Viterbi decoder  203  may process the FIR samples quickly to help ensure that a channel estimation process converges correctly, while an iterative decoder (including the SOVA decoder  205  and the LDPC decoder  210 ) may take a longer amount of time and sufficiently checks for errors while decoding the data. 
     The SOVA decoder  205  produces soft information and path decision information in response to one or more codewords of the encoded signal  202 . The SOVA decoder  205  produces a most-likely (ML) path indication which is stored in the decision memory  255 . In some implementations, the SOVA decoder  205  updates the pre-decision information in the pre-decision memory  245 . The updater  240  loads estimation parameters into the SOVA decoder  205 , which then uses the parameters to produce the soft information and path decision information. The SOVA decoder  205  can output one or more alternate paths to the event memory  260 . These one or more alternate paths are different from the ML path. Based on output from the SOVA decoder  205 , the LDPC decoder  210  can produce a decoded path (which can sometimes be referred to as a “true path” or “true data” or “corrected data”). This decoded path is the best estimate of the codeword based on the current decoding state of the system  201 . In some implementations, the ML path is selected by the SOVA decoder  205  to have the smallest path metric and the alternate path is selected to have the second smallest path metric. 
     The system  201  can employ multiple estimation techniques to improve the reliability of the overall decoding process. These estimation techniques include MMSE estimation and NR estimation. The MMSE estimator  235  produces MMSE estimation parameters based on information stored in the pre-decision memory  245  and the FIR memory  250 . The MMSE estimator  235  attempts to minimize square error along a ML path. The NR estimator  230  uses an adaptation technique in conjunction with MMSE estimation to improve the bit-error-rate (BER) performance of the system  201 . 
     The NR estimator  230  uses multiple types of information such as event location information, pre-decision information, alternate path information, ML path information, FIR samples, MMSE estimates, and LDPC decoded data to produce an NR estimation output. The updater  240  can combine the NR estimation parameters and the MMSE estimation parameters to provide combined estimation parameters to the SOVA decoder  205 . 
     The NR estimator  230  uses an adaptation technique that considers whether the decoded path from the LDPC decoder  210  matches a ML path or an alternate path (which is sometimes referred to as a trace back path). If the ML path is the same as the decoded path, the adaptation technique adapts one or more estimation parameters such that the squared-error along the ML path is smaller, but the squared-error along the alternate path is larger. If the alternate path is the same as the decoded path, the technique adapts the one or more estimation parameters such that the squared-error along the ML path is larger, but the squared-error along the alternate path is smaller. 
     In some implementations, the PRBS generator  225  generates a pseudo-random binary sequence to the NR estimator  230  during a PRBS mode. In a calibration mode, the selector  227  provides the NR estimator  230  with an output of the PRBS generator  225  instead of an output of the first CLD mapper  215 . The system  201  can enter a PRBS mode for one or more reasons such as for a calibration purpose or during a period of very low SNR to aid in the convergence of the LDPC decoder  210 . 
     In some implementations, the information passed between the SOVA decoder  205  and the LDPC decoder  210  represents a bit reliability metric, such as a log-likelihood-ratio (LLR) message. The LLR can be obtained using a natural logarithmic function of the ratio of the probability of the value being 1 to the probability of the value being 0 in accordance with this equation: 
               LLR   ⁡     (     b   i     )       =     log   ⁡     (       P   ⁡     (       b   i     =   0     )         P   ⁡     (       b   i     =   1     )         )             
where, b i  represents a bit value. An LLR value can include a sign that indicates whether the transmitted bit is determined to be “0” or “1”, and a magnitude representing the confidence of that determination. For example, values of LLR&gt;0 indicate a higher probability that the value of the transmitted bit is 0, whereas values of LLR&lt;0 indicate a higher probability that the value of the transmitted bit is 1.
 
     An LDPC code that can be decoded by the LDPC decoder  210  can be represented using parity check matrices. An (N, K) LDPC code is a parity check code, where K is the number of bits to be encoded, N is the size (or length) of the resulting coded block and M (N-K) represents the additional error correction bits added by the code. Thus, an LDPC code, C, is specified in terms of a low-density (sparse) M-by-N binary parity check matrix H having dimensions M×N. A binary string, c, of length N is a codeword in the LDPC code C, if and only if Hc={right arrow over (0)} is satisfied. For example, 
             H   =     [         1       1       1       1       1       1       1           1       0       1       0       1       0       1           0       1       0       1       0       1       0         ]           
where the parity check matrix H is shown for an LDPC code with N=7 and K=5. Then, the binary string c=(1,0,1,0,1,0,1) T  is a codeword in the LDPC code C. The codeword, c, is generated by introducing redundancy bits. For example, an LDPC encoder receives a word of length K and outputs a codeword (e.g., codeword c) of length N by inserting N-K redundancy bits into the received word. Each bit of an LDPC codeword, c, corresponds to a column of the parity check matrix H. For example, bit  1  corresponds to the 1st column of matrix H, bit  2  corresponds to the second column of matrix H, etc.
 
     A receiver system, in general, can use an array of bits on a path at time t, where a t  represents the bit value on a path at time t, to determine an error term for a branch. For example, the system computes the error term of a branch with data a t-4 , . . . , a t  in accordance with the following equation: 
             err   =       ∑     k   =   0     3     ⁢       (         f     MMSE   ,   k       ⁡     (     a     t   -   3     t     )       +       f     NR   ,   k       ⁡     (     a     t   -   3     t     )         )     ⁢     (       y     t   -   k       -     L   ⁡     (     p   k     )       -       m   MMSE     ⁡     (     p   k     )       -       m   NR     ⁡     (     p   k     )         )               
where f MMSE,k (x) represents a MMSE non-linear filter coefficient k of state x; f NR,k (x) represents the NR non-linear filter coefficient k of state x; m MMSE (x) represents the MMSE mean shift of state x; m NR (x) represents the NR mean shift of state x; and y t  represents the FIR sample at time t. In some implementations, there are four MMSE non-linear filter coefficients and four NR non-linear filter coefficients per state. The 5-bit patterns p 0  to p 3  are computed in accordance with the following:
 
 p   0   =a   t-4   a   t-3   a   t-2   a   t-1   a   t  
 
 p   1   =b   t-5   a   t-4   a   t-3   a   t-2   a   t-1  
 
 p   2   =b   t-6   b   t-5   a   t-4   a   t-3   a   t-2  
 
 p   3   =b   t-7   b   t-6   b   t-5   a   t-4   a   t-3  
 
where b t  represents the pre-decision bit from a preliminary Viterbi decoder (e.g., Viterbi decoder  203  of  FIG. 2 ) at time t.
 
     The system applies an ECC technique to a decoding output to produce a correct path. The decoding output can include multiple paths through a trellis. The system uses an update technique based on the correct path and a signed least mean squares (LMS) technique to update a mean shift parameter in accordance with the following equation:
 
 m   NR ( p   k )   m   NR ( p   k )±μ m   sgn ( err )( f   MMSE,k ( a   t   t-3 )+ f   NR,k ( a   t   t-3 ))
 
where μ m  is an update weight value for the mean shift parameter. For mean shift, the system uses the plus direction if the branch is on the correct path, otherwise the system uses the minus direction if the branch is on the wrong path. The system can update filter coefficients in accordance with the following equation:
 
 f   NR,k (α t   t-3 )   f   NR,k ( a   t   t-3 ) + μ f   sgn ( err )( y   t-k   −L ( p   k )− m   MMSE ( p   k )− m   NR ( p   k ))
 
where μ f  is an update weight value for the filter coefficients. The system uses the minus direction if the branch is on the correct path, otherwise the system uses the plus direction if the branch is on the wrong path.
 
     The system can maintain separate sets of estimation parameters such as filter coefficients and mean shift values. In some implementations, the system can share the same parameters between MMSE and NR estimation. In this case, the system can start with MMSE estimation; after a few iterations, switch off MMSE estimation; and then run NR estimation. In some implementations, the system computes the sums:
 
 f   total,k ( x )= f   MMSE,k ( x )+ f   NR,k ( x ),
 
 m   total ( x )= m   MMSE ( x )+ m   NR ( x )
 
where the system adapts the resulting combination of the filter parameters and the resulting combination of the mean shift parameters. Based on these sums, the system computes
 
             err   =       ∑     k   =   0     3     ⁢       (       f     total   ,   k       ⁡     (     a     t   -   3     t     )       )     ⁢     (       y     t   -   k       -     L   ⁡     (     p   k     )       -       m   total     ⁡     (     p   k     )         )               
for the error term. The system computes
 
 m   total ( p   k )   m   total ( p   k )±μ m   sgn ( err )( f   total,k ( a   t   t-3 ))
 
for the m total  updates and
 
 f   total,k ( a   t   t-3 )   f   total,k ( a   t   t-3 ) + μ f   sgn ( err )( y   t-k   −L ( p   k )− m   total ( p   k ))
 
for the f total  updates. The system computes back the NR parameters in accordance with:
 
 f   NR,k ( x )= f   total,k ( x )− f   MMSE,k ( x )
 
 m   NR ( x )= m   total ( x )− m   MMSE ( x )
 
at the end of adaptation.
 
     In some implementations, there is no NR estimation for variance. Note that there is an indirect effect to variance because NR estimation adapts the 0th filter tap f NR,0 (x), where MMSE does not adapt the 0th tap because it can be fixed to one. Since all taps are adapted by NR estimation, the taps can go to zero or diverge. Hence, a receiver system can periodically normalize the estimation parameters. In some implementations, the receiver system can use the following equation 
               a   ^     =         max     a   =   0000       1111     ⁢     (         f     MMSE   ,   0       ⁡     (   a   )       +       f     NR   ,   0       ⁡     (   a   )         )             
to find the maximum 0th tap value (â) The system can perform a division where β=1/â is computed. In some implementations, this division does not have to be accurate, however β≦1/â should hold with any less-accurate division procedure so that the new combined nonlinear coefficient is less than or equal to one. The system can normalize taps in accordance with the equation
 
 f   NR,k ( a ) − f   MMSE,k ( a )+β( f   MMSE,k ( a )+ f   NR,k ( a ))
 
for all tap values (e.g., 0000 to 1111) and all k values (0, 1, 2, and 3).
 
       FIG. 3  shows an example of a receiver system process that includes performing an adaptation technique. In some implementations, the process periodically performs adaptation to adjust estimation parameters for decoding received signals. In some implementations, the process continuously performs adaptation to adjust estimation parameters for decoding received signals. At  305 , the process produces sample codewords based on a received encoded signal. Producing sample codewords can include operating a FIR filter to determine FIR sample codewords. At  310 , the process decodes the sample codewords by iteratively processing codeword information and exchanging information between a soft input soft output (SISO) decoder (e.g., SOVA decoder or a BCJR decoder) and a code decoder (e.g., LDPC decoder or a turbo code decoder). At  315 , the process operates the SISO decoder to produce a first path and a second path based on estimation parameters, the second path being an alternate to the first path. The paths can be generated based on different paths of bits defined on a trellis structure. The process can select a next bit of a path on the trellis structure based on a branch metric (e.g., the probability of the next bit being a “1” is associated with a first branch metric value, where the probability of the next bit being a “0” is associated with a second, different branch metric value). A path metric can be defined as a sum of individual branch metric values. For example, the paths can be associated with respective path metric values where the first path can be associated with a smallest one of the path metrics. The SISO decoder can select the second path such that a path metric difference between the first path and the second path is less than a threshold. For example, the second path has the second smallest path metric. At  320 , the process operates the code decoder to produce a decoded path. 
     At  325 , the process determines a winning path of the first and second paths based on whether the decoded path matches the first path or the second path. At  330 , the process updates the estimation parameters based on one or more error terms and the winning path to favor selection of the winning path by the SISO decoder in a subsequent iteration and to disfavor selection of a losing path of the first and second paths by the SISO decoder in the subsequent iteration. Updates estimation parameters can include updating a first set of estimation parameters and updating a second set of estimation parameters. Each of the first estimation parameters and second estimation parameters can include filter coefficients for a filter such as a FIR filter and a mean shift parameter. In some implementations, the second set of estimation parameters is considered to be a fine-grain adjustment to the first set of estimation parameters. After updating the estimation parameters at  330 , the process can continue at  305  to produce additional sample codewords. In some implementations, the process causes the SISO decoder to reprocess codewords based on the updated estimation parameters. 
       FIG. 4  shows another example of a receiver system process that includes performing an adaptation technique. At  405 , a receiver system process determines the initial MMSE and NR estimation parameters. At  410 , a global decoder iteration is performed and resulting event information is saved. At  415 , the process produces a decoded path based on an LDPC output. At  420 , the process runs an adaptation based on the saved event information and the decoded path to update a combination of the MMSE and NR estimation parameters. At  425 , the process determines an update to the NR estimation parameters based on an output of the adaptation process. At  430 , the process combines MMSE and NR estimation parameters using a normalization technique, such as described above. At  435 , the process performs an additional global decoder iteration based on the normalized estimation parameters. 
       FIG. 5  shows an example of selecting and storing event information from multiple SOVA instances. A SOVA decoder can include hardware that operates multiple SOVA instances  505   a - d . Each of the SOVA instances  505   a - d  can be configured to simultaneously process different sections of each sample codeword and produce events. In some implementations, the SOVA instances  505   a - d  produce events that merge directly to the ML path. A selector  510  can select events from the SOVA instances  505   a - d  based on comparing metric values with a predetermined threshold value, and write the selected events to an event memory  515 . In some implementations, the selector  510  selects one of the events from the SOVA instances  505   a - d  and writes the selected one to the event memory  515 . Some receivers use a clock period of 4T. Further, one or more memories  515  of a receiver can run at a 4T clock period. For each 4T cycle, each SOVA instance  505   a - d  produces two events for a total of eight events. Each event can be associated with a metric such as a path metric. In some implementations, the selector  510  selects the event with the smallest path metric value and stores the selected event to the memory  515 . 
       FIG. 6  shows an example of an event comparator of a receiver architecture. The receiver architecture  602  includes a decision memory  613 , event memory  615 , LDPC memory  617 , an event comparator  620 , queue  630 , and NR estimator  640 . The NR estimator  640  uses multiple types of information such as event location information, pre-decision information, alternate path information, ML path information, FIR samples, and LDPC decoded data to produce an NR estimation output. The information can be stored in one or more memories  613 ,  615 ,  617  of a receiver. 
     Memories such as the decision memory  613 , event memory  615 , and LDPC memory  617  provide data to a comparator  620 . Based on an output from a LDPC decoder, the LDPC memory  617  can provide a decoded path to the comparator  620 . Based on an output from a SOVA decoder, the decision memory  613  can provide ML path information to the comparator  620 . Also based on an output from a SOVA decoder, the event memory  615  can provide an input event that includes event location information, pre-decision information (e.g., pre-decision bits), and alternate path information. In some implementations, event location information for a single event includes a SOVA chunk index value and an offset value for a start of a location within the identified SOVA chunk. 
     In response to an input event received via event memory  615 , the comparator  620  receives ML path data from the decision memory  613 , a decoded path from the LDPC memory  617 , and an alternate path from the event memory  615 . The comparator  620  compares the decoded path with the ML path and an alternate path. If the decoded path does not equal the ML path and the decoded path does not equal the alternative path, the comparator  620  discards the input event. Otherwise, the comparator  620  writes event information into the queue  630 . The event information includes the input event, ML path, and a path indication as to whether the decoded path matches the ML path or the alternate path. The queue  630  buffers information for the NR estimator  640 . The NR estimator  640  can use the path indication to update one or more estimation parameters as described above. 
       FIG. 7  shows another example of a receiver system process that includes performing an adaptation technique. At  705 , the process operates a decoder to decode a received encoded signal based on estimation parameters to produce paths including a first path and a second path, the second path being an alternate to the first path. In some implementations, the paths are associated with respective path metrics where the first path is associated with a smallest one of the path metrics. Implementations can include selecting the second path such that a path metric difference between the first path and the second path is less than a threshold. The process can include determining an initial version of the estimation parameters based on first estimation parameters and second estimation parameters. In some implementations, the decoder includes a hard-output decoder such as a Reed-Solomon code decoder or a Bose-Ray-Chaudhuri “BCH” code decoder. In some implementations, the decoder includes a LDPC decoder or a turbo code decoder. In some implementations, the decoder includes an iterative decoder that includes a first decoder and a second decoder. At  710 , the process determines a decoded path based on at least a portion of the paths. Determining the decoded path can include applying an error correction code to the paths to determine a correct path. In some implementations, an LDPC decoder can be used to produce the decoded path. 
     At  715 , the process determines a winning path of the first path and the second path based on whether the decoded path matches the first path or the second path. At  720 , the process updates the estimation parameters based on one or more error terms and the winning path to favor selection of the winning path by the decoder and to disfavor selection of a losing path of the first and second paths by the decoder in a subsequent iteration. Updating the estimation parameters can include adjusting the estimation parameters to cause, in the decoder, a decrease in a metric associated with the winning path for the subsequent iteration. Updating the estimation parameters can include adjusting the estimation parameters to cause, in the decoder, an increase in a metric associated with the losing path for the subsequent iteration. In some implementations, a subsequent iteration of a decoder refers to the decoder processing the next codeword. The process can update estimation parameters based on a codeword being fully and successfully decoded by the decoder. In some implementations, if the process detects a decoding failure for a received codeword, then the decoder is not required to update the estimation parameters. In some implementations, a subsequent iteration of a decoder refers to the decoder processing the same codeword in an additional iteration, or processing the next codeword. 
     Updating the estimation parameters, at  720 , can include combining the first estimation parameters and second estimation parameters to produce combined estimation parameters; updating the combined estimation parameters based on the one or more error terms and the winning path to produce updated combined estimation parameters. The process can include updating the second estimation parameters based on the updated combined estimation parameters and the first estimation parameters. Determining estimation parameters for a subsequent iteration can include combining the first estimation parameters and an updated version of the second estimation parameters using a normalization technique. 
     A few embodiments have been described in detail above, and various modifications are possible. The disclosed subject matter, including the functional operations described in this specification, can be implemented in electronic circuitry, computer hardware, firmware, software, or in combinations of them, such as the structural means disclosed in this specification and structural equivalents thereof, including potentially a program operable to cause one or more data processing apparatus to perform the operations described (such as a program encoded in a computer-readable medium, which can be a memory device, a storage device, a machine-readable storage substrate, or other physical, machine-readable medium, or a combination of one or more of them). 
     The term “data processing apparatus” encompasses all apparatus, devices, and machines for processing data, including by way of example a programmable processor, a computer, or multiple processors or computers. The apparatus can include, in addition to hardware, code that creates an execution environment for the computer program in question, e.g., code that constitutes processor firmware, a protocol stack, a database management system, an operating system, or a combination of one or more of them. 
     A program (also known as a computer program, software, software application, script, or code) can be written in any form of programming language, including compiled or interpreted languages, or declarative or procedural languages, and it can be deployed in any form, including as a stand alone program or as a module, component, subroutine, or other unit suitable for use in a computing environment. A program does not necessarily correspond to a file in a file system. A program can be stored in a portion of a file that holds other programs or data (e.g., one or more scripts stored in a markup language document), in a single file dedicated to the program in question, or in multiple coordinated files (e.g., files that store one or more modules, sub programs, or portions of code). A program can be deployed to be executed on one computer or on multiple computers that are located at one site or distributed across multiple sites and interconnected by a communication network. 
     While this specification contains many specifics, these should not be construed as limitations on the scope of what may be claimed, but rather as descriptions of features that may be specific to particular embodiments. Certain features that are described in this specification in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination. Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a subcombination or variation of a subcombination. 
     Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. In certain circumstances, multitasking and parallel processing may be advantageous. Moreover, the separation of various system components in the embodiments described above should not be understood as requiring such separation in all embodiments. 
     Other embodiments fall within the scope of the following claims.