Patent Publication Number: US-8525320-B2

Title: Microelectronic die packages with leadframes, including leadframe-based interposer for stacked die packages, and associated systems and methods

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is a divisional of U.S. application Ser. No. 11/923,290 filed Oct. 24, 2007, now U.S. Pat. No. 7,947,529, which claims foreign priority benefits of Republic of Singapore Application No. 200706008-0 filed Aug. 16, 2007, each of which is incorporated herein by reference in its entirety. 
    
    
     TECHNICAL FIELD 
     The present disclosure is directed generally to microelectronic die packages with leadframes, and more particularly to leadframes configured for stacked die packages. 
     BACKGROUND 
     Packaged microelectronic assemblies, such as memory chips and microprocessor chips, typically include a microelectronic die mounted to a substrate and encased in a plastic protective covering. The die includes functional features, such as memory cells, processor circuits, and interconnecting circuitry. The die also typically includes bond pads electrically coupled to the functional features. The bond pads are electrically connected to pins or other types of terminals that extend outside the protective covering for connecting the die to busses, circuits, and/or other microelectronic assemblies. 
     In one conventional arrangement, the die is mounted to a supporting substrate (e.g., a printed circuit board), and the die bond pads are electrically coupled to corresponding bond pads of the substrate with wirebonds. After encapsulation, the substrate can be electrically connected to external devices with solder balls or other suitable connections. Accordingly, the substrate supports the die and provides an electrical link between the die and the external devices. 
     In other conventional arrangements, the die can be mounted to a leadframe that has conductive lead fingers connected to a removable frame. The frame temporarily supports the lead fingers in position relative to the die during manufacture. Each lead finger is coupled to a corresponding bond pad of a die (e.g., via a wire bond or a metal redistribution layer), and the assembly is encapsulated in such a way that the frame and a portion of each of the lead fingers extend outside the encapsulating material. The frame is then trimmed off, and the exposed portions of each lead finger connect the die to external components. In general, individual lead fingers can be bent and then coupled to a corresponding external bond pad. 
     Die manufacturers have come under increasing pressure to reduce the size of dies and the volume occupied by the dies, and to increase the capacity of the resulting encapsulated assemblies. To meet these demands, die manufacturers often stack multiple dies on top of each other to increase the capacity or performance of the device within the limited surface area on the circuit board or other element to which the dies are mounted. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIGS. 1A and 1B  are cross-sectional side views of a stacked system that includes microelectronic die packages configured and stacked in accordance with an embodiment of the disclosure. 
         FIG. 2A  is a top view of a microelectronic assembly that includes a frame, a release layer, and a support substrate. 
         FIGS. 2B and 2C  are partially exploded cross-sectional side views of the assembly of  FIG. 2A . 
         FIG. 3A  is a top view of the assembly of  FIG. 2A  having microelectronic dies positioned within openings of the frame. 
         FIGS. 3B and 3C  are cross-sectional side views of the assembly of  FIG. 3A . 
         FIG. 4A  is a top view of the assembly of  FIG. 3A  encapsulated in a dielectric material. 
         FIGS. 4B and 4C  are cross-sectional side views of the assembly of  FIG. 4A . 
         FIGS. 5A and 5B  are cross-sectional side views of the assembly of  FIG. 4A  after partial removal of the dielectric material. 
         FIGS. 6A and 6B  are cross-sectional side and bottom views of the assembly of  FIGS. 5A and 5B  after removing the support substrate. 
         FIG. 7A  is a cross-sectional side view of the assembly of  FIGS. 6A and 6B  after forming a spacer layer. 
         FIG. 7B  is a cross-sectional side view of the assembly of  FIG. 7A  after lead thinning in accordance with an alternative embodiment of the disclosure. 
         FIG. 8  is a cross-sectional side view of the assembly of  FIG. 7A  after singulation. 
         FIG. 9  is a cross-sectional side view of a stacked system that includes microelectronic die packages configured and stacked in accordance with an alternative embodiment of the disclosure. 
         FIG. 10  is a cross-sectional side view of a stacked system having microelectronic die packages that include dies of different sizes in accordance with an embodiment of the disclosure. 
         FIG. 11  is a cross-sectional side view of a stacked system having metal traces for selectively electrically coupling individual microelectronic die packages in accordance with an embodiment of the disclosure. 
         FIG. 12  is a cross-sectional side view of a stacked system having metal solder connectors configured for selectively electrically coupling individual microelectronic die packages in accordance with an embodiment of the disclosure. 
         FIG. 13  is a schematic illustration of a system in which the microelectronic die packages and stacked systems may be incorporated. 
     
    
    
     DETAILED DESCRIPTION 
     Specific details of several embodiments of the disclosure are described below with reference to semiconductor devices and methods for fabricating semiconductor devices. The semiconductor components are manufactured on semiconductor wafers that can include substrates upon which and/or in which microelectronic devices, micromechanical devices, data storage elements, optics, read/write components, and other features are fabricated. For example, SRAM, DRAM (e.g., DDR/SDRAM), flash memory (e.g., NAND flash memory), processors, imagers, and other types of devices can be constructed on semiconductor wafers. Although many of the embodiments are described below with respect to semiconductor devices that have integrated circuits, other types of devices manufactured on other types of substrates may be within the scope of the invention. Moreover, several other embodiments of the invention can have different configurations, components, or procedures than those described in this section. A person of ordinary skill in the art, therefore, will accordingly understand that the invention may have other embodiments with additional elements, or the invention may have other embodiments without several of the features shown and described below with reference to  FIGS. 1A-13 . 
       FIGS. 1A and 1B  are cross-sectional side views of one embodiment of a stacked system  102  having a plurality of die packages  100  (identified individually by reference numbers  100   a - d ). Individual die packages  100  can include a microelectronic die  107 , a molded dielectric casing  106 , and metal leads  108  (or metal contacts) that are spaced apart from lateral sides of the die  107 . The casing  106  has lateral sides  103 , a top side  104 , and a bottoms side  105 , and the casing  106  encapsulates at least a portion of the die  107  and the leads  108 . The die packages  100  further include metal traces  110  that electrically couple the leads  108  to the die  107  and a dielectric spacer layer  112  encasing the traces  110  and a portion of an active side of the die  107 . The die packages  100  can also include package bond pads  114  coupled to the traces  110 . The stacked system  102 , for example, has an interposer substrate  118  with metal bump pads  117  electrically connected to the bond pads  114  at the first die package  100   a  by bond pad connections  116 . 
     The stacked system  102  shown in  FIGS. 1A and 1B  includes the four stacked die packages  100   a - d  physically coupled together, at least in part, by adhesive layers  119   a - c , and the leads  108  of the die packages  100   a - d  electrically coupled together by external inter-package connectors  120 . The connectors  120 , for example, can be metal solder lines that wet to lateral contact surfaces of the leads  108  at the lateral sides  103  of the casing  106 , but do not wet to the casing  106  itself. In this embodiment, the connectors  120  form along at least the lateral contact surfaces of sets of vertically aligned leads  108  and across die package gaps  115  between such vertically aligned leads  108  to electrically bridge the die packages  100   a - d . Thus, the bonds  116  are electrically coupled to microelectronic dies within the die packages  100   a - d  through conduction paths that include the leads  108  and the connectors  120 . As shown in  FIGS. 1A and 1B , the external inter-package connectors  120  may also attach to top and bottom contact surfaces of the leads  108  at the top and bottom surfaces  104 - 105  of the casing  106 , respectively. In alternative embodiments, the connectors  120  may attach only to the portion of the leads  108  flush with the lateral surfaces  103  of the casing  106 , or combinations of the surfaces of the leads  108  at the lateral, top, and bottom surfaces  103 - 105  of the casing  106 . Accordingly, several embodiments of the connectors  120  have a portion that projects at least laterally outward from the lateral edges of the die package  100   a - d  and another portion that extends between the top and bottom sides of individual die packages  100   a - d.    
     The stacked system  102  may be formed by a method that includes stacking the die packages  100   a - d , aligning the leads  108  of the die packages  100   a - d , and forming the connectors  120  at individual leads  108  of the die packages  100   a - d . Stacking and aligning the leads  108  may include stacking the die packages  100   a - d  in sequence so that the leads  108  are placed above and/or below leads on a corresponding die package. Forming the connectors  120  may be carried out, for example, using wave or reflow soldering processes. Using wave soldering, a pumped wave or cascade of liquid-phase metal solder can be applied across lateral sides of the die packages  100   a - d . Using reflow soldering, solder paste having metal powder particles can be applied across the lateral sides of the die packages  100   a - d  and then heated to melt the metal particles. In these, or other soldering processes, the metal solder selectively wets (e.g., when heated) to the higher energy surfaces associated with the leads  108  and not to the lower energy surfaces associated with the casing  106 . When the metal solder cools, the connectors  120  are formed across individual leads  108 . A die package spacing distance t 1  of 60 microns, for example, may ensure that the surface tension associated with the applied solder allows the connectors  120  to bridge between the leads  108 . 
     In general, and in contrast to the stacked system  102 , conventional methods of stacking packages or dies have been challenging and expensive, and even then misalignments occur. For example, conventional leads need to be accurately aligned, and thus attaching a conventional lead on one package to a conventional lead on a corresponding package is time-intensive. Also, because individual leads occupy only a small surface area, each conventional lead-to-lead interconnection needs to be carefully inspected. The process of stacking conventional packages is also difficult to standardize because dies are made in a variety of sizes, and packages likewise vary in size. Thus, the process of stacking and interconnecting conventional packages needs to be tailored to an arrangement of a particular package type. 
     By using the leads  108  as a framework for interconnecting devices, however, several embodiments of microelectronic die packages  100  can overcome these and other issues related to conventional die package stacking. For example, because the leads  108  are exposed at lateral surface portions of the casing  106 , each set of leads can be electrically coupled together using a simple soldering process to intercouple the die packages  100   a - d . Also, because the connectors  120  can selectively wet to the conductive leads  108  but not attach to the casing  106  between the leads  108 , the lead-to-lead interconnections are reliable and do not require the same alignment tolerances as conventional lead-to-lead inspection. The leads  108  can further establish the exterior package dimensions such that a standardized package size may be used to house a variety of differently sized dies, an example of which is described further with reference to  FIG. 10 . 
       FIGS. 2A-8  illustrate stages of forming the microelectronic die package  100   a  in accordance with one embodiment of the disclosure.  FIG. 2A  is a top view of a microelectronic assembly  121  that includes a metal frame  122  and a release layer  124 . The frame  122  comprises openings  126 , metal lead portions  127 , and dicing lanes  128 . The openings  126  expose a portion of the release layer  124  for attaching and positioning the die  107  adjacent to the lead portions  127 , and the dicing lanes  128  provide a cutting or cleavage path for singulating the individual die package  100   a  from the frame  122  (described further with reference to  FIG. 8 ). In one embodiment, the frame  122  may be made from copper and may include selective copper plating along the lead portions  127 . In other embodiments, the frame  122  may comprise a variety of other metallic materials such as aluminum or an aluminum-copper alloy. The release layer  124  may be, for example, a thermal or UV release film. 
       FIGS. 2B and 2C  are partially exploded cross-sectional side views of the assembly  121  showing the frame  122 , the release layer  124 , and a support substrate  130  (e.g., a silicon wafer or other type of structure having planar surface).  FIGS. 2B and 2C  also show individual dicing lane  128 , first tier and second tier portions  132 - 133  of the lead portions  127 , and gaps  136  between individual lead portions  127 . The first and second tier portions  132 - 133 , the gaps  136 , and the support substrate  130  define bottom and lateral sides of a cavity, which will be subsequently filled with a dielectric material (described further with reference to  FIGS. 4A-C ). 
       FIG. 3A  is a top view of the assembly  121  after microelectronic die placement.  FIG. 3A , more specifically, shows the frame  122 , the lead portions  127 , and the openings  126 , with individual dies  107  placed within the openings  126  and adjacent to the lead portions  127 .  FIGS. 3B and 3C  are cross-sectional side views further showing the openings  126 , the first tier and second tier portions  132 - 133  of the lead portions  127 , and a top-side surface  139  of the dies  107 . The first tier portions  132  are below the top-side surface  139  of the dies  107  and the second tier portions  133  extend above the top-side surface  139 . In one embodiment, the second tier portions  133  may have a thickness t 2  in the range of about 250 to 1000 microns. In another embodiment, t 2  could be on the order of 650 microns or larger, which would eliminate a need for backgrinding the dies  107 . In addition, it is also contemplated that the first and second tier portions  132 - 133  could have thicknesses that are configured to promote heat conduction away from the dies  107 . 
       FIG. 4A  is a top view of the assembly  121  after a dielectric material  140  has been formed on a top side of the metal frame  122  and a top side of the dies  107 . The dielectric material  140 , for example, may be a polymer or plastic that is heated and subsequently deposited on top of and within the gaps of the frame  122 . The dielectric material  140 , for example, can be molded over the frame  122  and the top sides of the dies  107 .  FIGS. 4B and 4C  are cross-sectional side views showing the dielectric material  140  filling the openings  126  around the dies  107  and the gaps  136  between the lead portions  127 . After curing and/or cooling, the hardened dielectric material  140  should form a protective and electrically isolative covering over the dies  107 , within gaps between lateral sides  142  of the dies  107  and the lead portions  127 , and within the gaps  136 . To ensure that all of the leads and dies within the assembly  121  are encapsulated, the dielectric material  140  may optionally extend above the lead portions  127  by a thickness t 3 . 
       FIGS. 5A and 5B  are cross-sectional side views of the assembly  121  after partial removal of the dielectric material  140  that show a top-side surface  146  of the dielectric material  140  flush with a top-side surface  148  of the lead portions  127 . A backgrinding process, chemical etch, or chemical-mechanical polishing process may remove the upper portion of the dielectric material  140  to create the planar surface  146  for package-to-package stacking and to expose the top-side surface portions  148  of the lead portions  127  for electrical coupling between individual die packages. 
       FIGS. 6A and 6B  are cross-sectional side and bottom views of the assembly  121  after removing the release layer  124  and the support substrate  130  to expose a bottom-side surface  150  (e.g., active side) of the dies  107  and expose bottom-side surfaces  152  of the lead portions  127 . The bottom-side surfaces  150  of the dies  107  include bond pads  154  (or active features) electrically coupled to an integrated circuit within the dies  107  (not shown). The dielectric material  140  holds the dies  107  in place and separates the dies  107  from the lead portions  127 . 
       FIG. 7A  is a cross-sectional side view of the assembly  121  after forming an embodiment of the dielectric spacer layer  112  at the bottom-side surface  150  of the dies  107 . The spacer layer  112  includes metal traces  110  electrically coupling the bond pads  154  to the lead portions  127  and the package bond pads  114 . The spacer layer  112  may be made from a material such as a non-conductive oxide or polymer. The metal traces  110  and the package bond pads  114 , for example, may be made from copper or aluminum. The spacer layer  112  can accordingly be a redistribution structure. It is also contemplated that in certain embodiments, the package bond pads  114  may be omitted. For example, in  FIG. 1A  the package bond pads of the die packages  100   b - d  could be omitted because these pads are not electrically connected to any external bond pads. 
       FIG. 7B  is a cross-sectional side view that illustrates an additional or alternative stage in forming a microelectronic die package in accordance with another embodiment. In this embodiment, the lead portions  127  are thinned to a thickness so that the dielectric material  140  extends above the top-side surfaces  148  of the lead portions  127  and retains the planar surface  146  attained in the stage of  FIGS. 5A-B . A chemical etch, for example, may thin the lead portions  127  without removing material from the dielectric material. 
       FIG. 8  is a cross-sectional side view of the package  100   a  after singulation through the dicing lanes  128  (e.g., by a dicing saw or a chemical etch) to yield separated dies  107  housed in casings  106  and coupled to the leads  108 . The singulation process forms exposed surface portions  157  of the leads  108  along the lateral edges of the casings. The top- and bottom-side surfaces  148  and  152  of the leads  108  can also be exposed or otherwise accessible. Accordingly, the die package  100   a  may be placed within a stacked system, such as the stacked system  102 , and the connectors  120  can be formed along the die package  100   a  at any of the surfaces  148 ,  152 , and  157 . 
     Many variations may be made to the stacked system  102 . For example, in lieu of the bond pad connections  116  shown in  FIG. 1A , wire bonds may electrically couple the stacked system  102  to an interposer substrate. In other embodiments, the adhesive layers  119   a - c  interposed between the stacked packages may not be necessary. The connectors  120  alone, for example, could be used to hold the individual die packages  100   a - d  together by temporarily clamping the packages  100   a - d  until metal solder is applied and the connectors  120  are formed. Also, the stacked system may include any number of individual microelectronic die packages having more or fewer packages than those presented in the illustrated embodiments. 
     In another embodiment, the stacked system  102  includes packages that house the same type of die. For example, the stacked system  102  could be a memory, such as a static dynamic access memory (SRAM). In this embodiment, the leads  108  would provide word and bit line access to individual SRAM dies housed in the die packages  100   a - d . Accordingly, the aggregated individual SRAM dies form a large SRAM, which has a reduced footprint relative to a conventional SRAM of the same size. 
       FIG. 9  is a cross-sectional side view showing an alternative embodiment of a stacked system  158  including microelectronic die packages formed in accordance with the additional, alternative stage described with reference to  FIG. 7B  and having a casing  159  that extends above the leads  108 . Thus, this embodiment may be used, for example, to stack microelectronic die packages that house thick or non-backgrinded dies. 
       FIG. 10  is a cross-sectional side view showing a stacked system  160  that includes microelectronic die packages  162   a - c  having corresponding microelectronic dies  164   a - c . The die packages  162   a - c  share a common lateral dimension d 1 , but the microelectronic dies  164   a - c  have different lateral dimensions d 2 , d 3 , and d 4 . In one embodiment, the stacked system  160  may be a memory module that includes an interface circuit at the die  164   a ; a control circuit at the die  164   b ; and a memory at the die  164   c . Because the packages  162   a - c  share the common lateral dimension d 1 , a myriad of different types of stacked systems may be created by stacking preferred die packages or exchanging certain die packages. For example, an alternative embodiment of the DRAM-based memory module could be assembled by using smaller magnetoresistive RAM (MRAM) based dies housed in die packages having the lateral dimension d 1 . Accordingly, DRAM-based die packages  162   b - c  could be exchanged for MRAM-based die packages. 
       FIG. 11  is a cross-sectional side view showing a stacked system  170  that includes microelectronic die packages  172   a - d  separated by dielectric spacer layers  174   a - d  and having corresponding first metal leads  176   a - d  and second metal leads  178   a - d  respectively coupled together by first and second connectors  184   a - b . In this view, the spacer layer  174   a  includes corresponding metal traces  180   a - b , the spacer layer  174   c  includes corresponding metal traces  181   a - b , the spacer layer  174   d  includes a single metal trace  182 , and the spacer layer  174   b  includes no corresponding metal traces. The first connector  184   a  is applied across the first leads  176   a - d  to selectively electrically couple first, third, and fourth packages  172   a ,  172   c , and  172   d ; and the second connector  184   b  is applied across the second leads  178   a - d  to selectively electrically couple the first and third packages  172   a  and  172   c . Thus, one side of the die package  172   d  and both sides of the die package  172   b  are electrically isolated from the connectors  184   a - b . The process of stacking the die packages  172   a - d  can be the same as the process described with reference to  FIGS. 1A-B . The process of forming the die packages  172   a - d  can be similar to the method of manufacturing described with reference to  FIGS. 2A-8 , but instead of connecting a metal trace to every metal lead, individual metal trace-lead couplings have been omitted. 
       FIG. 12  is a cross-sectional side view showing a stacked system  190  having microelectronic die packages  192   a - d  and individual external inter-package connectors  194   a - c  intercoupling the die packages  192   a - d  at corresponding sets of leads  196   a - c . The connector  194   a  intercouples the first, second, and third die packages  192   a - c  at the first set of leads  196   a ; the connector  194   b  intercouples the third and fourth die packages  192   c - d  at the second set of leads  196   b ; and the connector  194   c  intercouples the first, second, third, and fourth die packages  192   a - d  at the third set of leads  196   c . The connectors  194   a - c  can be configured to selectively route individual sets of the leads by applying metal solder across a limited lateral surface portion of packaging casing. Leads that are not soldered to remain electrically isolated from the stacked system  190 . Combinations of the techniques illustrated in  FIGS. 10-11  may be employed to create a desired stacked system that includes a variety of die packages that perform an aggregated circuit function in other embodiments (i.e., by omitting certain metal traces within the dielectric spacer layers and not forming metal solder connectors at certain metal leads). 
     Any one of the microelectronic devices described above with reference to  FIGS. 1A-12  can be incorporated into any of a myriad of larger and/or more complex systems  490 , a representative one of which is shown schematically in  FIG. 13 . The system  490  can include a processor  491 , a memory  492  (e.g., SRAM, DRAM, Flash, and/or other memory device), input/output devices  493 , and/or other subsystems or components  494 . Microelectronic devices may be included in any of the components shown in  FIG. 13 . The resulting system  490  can perform any of a wide variety of computing, processing, storage, sensor, imaging, and/or other functions. Accordingly, representative systems  490  include, without limitation, computers and/or other data processors, for example, desktop computers, laptop computers, Internet appliances, hand-held devices (e.g., palm-top computers, wearable computers, cellular or mobile phones, personal digital assistants), multi-processor systems, processor-based or programmable consumer electronics, network computers, and minicomputers. Other representative systems  490  include cameras, light or other radiation sensors, servers and associated server subsystems, display devices, and/or memory devices. In such systems, individual dies can include imager arrays, such as CMOS imagers. Components of the system  490  may be housed in a single unit or distributed over multiple, interconnected units, e.g., through a communications network. Components can accordingly include local and/or remote memory storage devices and any of a wide variety of computer-readable media. 
     From the foregoing, it will be appreciated that specific embodiments of the invention have been described herein for purposes of illustration, but well-known structures and functions have not been shown or described in detail to avoid unnecessarily obscuring the description of the embodiments of the invention. Where the context permits, singular or plural terms may also include the plural or singular term, respectively. Moreover, unless the word “or” is expressly limited to mean only a single item exclusive from the other items in reference to a list of two or more items, then the use of “or” in such a list is to be interpreted as including (a) any single item in the list, (b) all of the items in the list, or (c) any combination of the items in the list. Additionally, the term “comprising” is inclusive and is used throughout to mean including at least the recited feature(s) such that any greater number of the same feature and/or additional types of other features are not precluded. It will also be appreciated that specific embodiments of the invention have been described herein for purposes of illustration, but that various modifications may be made without deviating from the inventions. For example, many of the elements of one of embodiment can be combined with other embodiments in addition to, or in lieu of, the elements of the other embodiments. Accordingly, the invention is not limited except as by the appended claims.