Patent Publication Number: US-6339554-B1

Title: Semiconductor memory device with replacement programming circuit

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a semiconductor memory device having a spare memory cell. 
     2. Description of the Background Art 
     The arrangement of a main portion of a conventional semiconductor memory device will be described in relation to FIG.  10 . In the diagram, memory cells are represented by reference characters m 0  to m 63 , word lines disposed corresponding to the rows are represented by reference characters w 0  to w 63 , and a bit line disposed corresponding to a column is represented by reference characters “bit,” respectively. Further, a spare memory cell that can replace a memory cell is represented by reference characters r 0 , and a spare word line that can replace a word line is represented by reference characters sw 0 . 
     Bit line “bit” is connected to memory cells m 0  to m 63  and spare memory cell r 0 , and transmits data read from or to be written into memory cells m 0  to m 63  and spare memory cell r 0 . Word lines w 0  to w 63  are connected to memory cells m 0  to m 63 , and each word line sends a selecting signal to a corresponding memory cell. Spare word line sw 0  is connected to spare memory cell r 0  and sends a selecting signal to the corresponding spare memory cell. 
     As shown in FIG. 10, the conventional semiconductor memory device includes a replacement control circuit  100 # 0 , a decoder  105 # 0  including programming circuits  102 # 0  to  102 # 5  and logic circuits  103 # 0  to  103 # 63 , a comparator  120 # 0 , and an AND circuit  119 # 0 . Each of replacement control circuit  100 # 0  and programming circuits  102 # 0  to  102 # 5  includes a fuse. 
     When a defective memory cell is replaced with a spare memory cell (using spare word line sw 0 ), the fuse included in replacement control circuit  100 # 0  is blown. Thus, a replacement control signal R 0  of a logic high or H level indicating the use of the spare memory cell will be output. 
     The fuse included in each of programming circuits  102 # 0  to  102 # 5  is blown according to an address of the defective memory cell. The output from the programming circuit having a blown fuse attains the H level. Signals g 0  to g 5  are output from programming circuits  102 # 0  to  102 # 5 . 
     Comparator  120 # 0  compares a 6-bit address signal ad&lt;0:5&gt; with signals g 0  to g 5 , and outputs an H level signal when a match occurs. AND circuit  119 # 0  activates spare word line sw 0  according to replacement control signal R 0  and a comparison result from comparator  120 # 0 . 
     Logic circuits  103 # 0  to  103 # 63  each include AND circuits  104 A and  104 B and an NAND circuit  106 . Logic circuits  103 # 0  to  103 # 63  are provided corresponding to a 64-bit address. Each of logic circuits  103 # 0  to  103 # 63  receives a signal g 0  or an inverted signal /g 0  of signal g 0 , a signal g 1  or an inverted signal /g 1  of signal g 1 , a signal g 2  or an inverted signal /g 2  of signal g 2 , a signal g 3  or an inverted signal /g 3  of signal g 3 , a signal g 4  or an inverted signal /g 4  of signal g 4 , and a signal g 5  or an inverted signal /g 5  of signal g 5 . 
     In the diagram, logic circuit  103 # 0  receives signals g 0 , g 1 , g 2 , g 3 , g 4 , and g 5 , while logic circuit  103 # 63  receives signals /g 0 , /g 1 , /g 2 , /g 3 , /g 4 , and /g 5 . NAND circuit  106  receives replacement control signal R 0  and outputs from AND circuits  104 A and  104 B. Row address non-selection signal t 0  to t 63  are output from logic circuits  103 # 0  to  103 # 63 , respectively. 
     The conventional semiconductor memory device further includes AND circuits  108 # 0  to  108 # 63 . AND circuits  108 # 0  to  108 # 63  are respectively provided to word lines w 0  to w 63 . AND circuits  108 # 0  to  108 # 63  receive row address nonselection signals t 0  to t 63  and decode signals a 0  to a 63 , respectively. Decode signals a 0  to a 63  are obtained by decoding address signal ad&lt;0:5&gt; by a row decoder not shown. Word lines w 0  to w 63  are respectively activated according to outputs from AND circuits  108 # 0  to  108 # 63 . 
     When the memory cells are all normal, replacement control signal R 0  is at a logic low or L level so that spare word line sw 0  is in the inactive state. In this case, row address non-selection signals t 0  to t 63  attain the H level. One of word lines w 0  to w 63  is activated according to decode signals a 0  to a 63 . 
     When a defect is found in a memory cell and the defective memory cell is to be replaced with a spare memory cell, a fuse in replacement control circuit  100 # 0  and a corresponding fuse in programming circuits  102 # 0  to  102 # 5  are blown. 
     An example is given in which a memory cell m 0  is defective. Assume that the address of word line w 0  is “000000” (=ad&lt;0:5&gt;). In this case, all the fuses in programming circuits  102 # 0  to  102 # 5  are blown. Signals g 0  to g 5  all attain the H level so that signal t 0  output from logic circuit  103 # 0  attains the L level. Consequently, when an address signal designating memory cell m 0  is input and decode signal a 0  attains the H level, word line w 0  is not activated. 
     At this time, comparator  120 # 0  outputs an H level signal since the input address signal ad&lt;0:5&gt; corresponds to signals g 0  to g 5 . As a result, spare word line sw 0  is activated. 
     FIG. 11 shows another arrangement of the main portion of a conventional semiconductor memory device. The conventional semiconductor memory device shown in FIG. 11 has an arrangement for replacing two word lines. In the diagram, spare memory cells that can replace the memory cells are represented by reference characters r 0  and r 1 , and spare word lines that can replace word lines are represented by reference characters sw 0  and sw 1 . 
     A bit line “bit” is connected to memory cells m 0  to m 63  and spare memory cells r 0  and r 1 , and transmits data read from or to be written into memory cells m 0  to m 63  and spare memory cells r 0  and r 1 . Spare word lines sw 0  and sw 1  are connected to spare memory cells r 0  and r 1 , and each spare word line sends a selecting signal to a corresponding spare memory cell. 
     As shown in FIG. 11, the conventional semiconductor memory device includes replacement control circuits  100 # 0  and  100 # 1 , decoders  105 # 0  and  105 # 1 , comparators  120 # 0  and  120 # 1 , and AND circuits  119 # 0  and  119 # 1 . 
     Replacement control circuit  100 # 1  has the same arrangement as replacement control circuit  100 # 0 , and its fuse is blown when spare word line sw 1  is to be used. Consequently, an H level replacement control signal R 1  is output. 
     The arrangement of decoder  105 # 1  is the same as that of decoder  105 # 0 . The fuse included in each of programming circuits  102 # 0  to  102 # 5  is blown according to an address of a defective memory cell. Hereinafter, the outputs from programming circuits  102 # 0  to  102 # 5  included in decoder  105 # 1  will be referred to as signals h 0  to h 5 . 
     Each of logic circuits  103 # 0  to  103 # 63  included in decoder  105 # 1  receives a signal h 0  or an inverted signal /h 0  of signal h 0 , a signal h 1  or an inverted signal /h 1  of signal h 1 , a signal h 2  or an inverted signal /h 2  of signal h 2 , a signal h 3  or an inverted signal /h 3  of signal h 3 , a signal h 4  or an inverted signal /h 4  of signal h 4 , and a signal h 5  or an inverted signal /h 5  of signal h 5 . Logic circuits  103 # 0  to  103 # 63  perform logical processing according to replacement control signal R 1 . Row address non-selection signals output from decoder  105 # 1  will be referred to as signals u 0  to u 63 . 
     Comparator  120 # 1  has the same arrangement as comparator  120 # 0 , compares address signal ad&lt;0:5&gt; with signals h 0  to h 5 , and outputs an H level signal when a match occurs. AND circuit  119 # 1  activates spare word line sw 1  according to replacement control signal R 1  and a comparison result from comparator  120 # 1 . 
     The conventional semiconductor memory device shown in FIG. 11 further includes AND circuits  110 # 0  to  110 # 63  and  108 # 0  to  108 # 63 . AND circuits  110 # 0  to  110 # 63  and AND circuits  108 # 0  to  108 # 63  are respectively provided to word lines w 0  to w 63 . 
     An AND circuit  110 #i (i=0, 1, . . . , 63) receives row address non-selection signals ti and ui. AND circuit  108 #i receives a decode signal ai and an output from AND circuit  110 #i. 
     When the row address non-selection signal output from decoder  105 # 0  or the row address non-selection signal output from decoder  105 # 1  is at the L level, the corresponding word line remains inactivate regardless of the input address signal. 
     When all memory cells are normal, replacement control signals R 0  and R 1  attain the L level so that spare word lines sw 0  and sw 1  are in the inactive state. On the other hand, row address non-selection signals are all at the H level so that one of word lines w 0  to w 63  is activated according to decode signals a 0  to a 63 . 
     For instance, when defects are found in memory cells m 0  and m 1 , fuses in replacement control circuits  100 # 0  and  100 # 1 , fuses in programming circuits  102 # 0  to  102 # 5  included in decoder  105 # 0 , and fuses in programming circuits  102 # 0  to  102 # 4  included in decoder  105 # 1  are blown. 
     As a result, replacement control signals R 0  and R 1  attain the H level. At this time, row address non-selection signal t 0  and signal u 1  attain the L level. Consequently, outputs from AND circuits  110 # 0  and  110 # 1  attain the L level, and outputs from AND circuits  110 # 2  to  110 # 63  attain the H level. 
     Word line w 0  or word line w 1  is not activated even when an address signal designating the defective memory cell m 0  or the defective memory cell m 1  is input (even when decode signal a 0  or a 1  is at the H level). 
     On the other hand, when the input address signal ad&lt;0:5&gt; corresponds to signals g 0  to g 5  in comparator  120 # 0 , spare word line sw 0  is activated. When the input address signal ad&lt;0:5&gt; corresponds to signals h 0  to h 5  in comparator  120 # 1 , spare word line sw 1  is activated. 
     Thus configured, the conventional semiconductor memory device can perform normal processing using a spare word line instead of the word line connected to a defective memory cell. 
     Being configured in the above-described manner, however, the conventional semiconductor memory device requires fuses (of the number that equals the number of addresses) necessary for programming the defective addresses as well as fuses for controlling the use of a spare memory cell (replacement control circuit). 
     Consequently, in order to replace the defective memory cells that exist over a plurality of rows by using a plurality of spare word lines, fuses of the number derived from first adding one to the number of addresses and then multiplying the sum by the number of spare word lines would be required. 
     As a result, when the number of spare word lines is increased for repairing defective memory cells, the region for mounting the fuses also increases, which interferes with the reduction in the overall chip area. 
     SUMMARY OF THE INVENTION 
     Thus, the present invention provides a semiconductor memory device capable of replacing a defective memory cell with a spare memory cell with small area requirement. 
     The semiconductor memory device according to the present invention is provided with a normal memory cell array including a plurality of memory cells arranged in a matrix of rows and columns, and a plurality of memory lines for storing data into or reading stored data from the plurality of memory cells; a spare memory cell array including a plurality of spare memory cells and a plurality of spare memory lines, each provided for replacing a defective memory line of the plurality of memory lines, for storing data into or reading stored data from a corresponding spare memory cell; and a replacement programming portion including a plurality of programming portions, each of the plurality of programming portions having a prescribed number of fuses required for programming an address of the defective memory line; and semiconductor memory device further provided with a select control circuit for performing a replacement according to a programmed state of the plurality of programming portions. 
     Preferably, the replacement programming portion includes a plurality of logic circuits respectively provided to the plurality of programming portions, each of the plurality of logic circuits outputs a selecting signal of a prescribed level when at least one fuse out of the prescribed number of fuses is blown. The select control circuit includes a plurality of control circuits respectively provided to the plurality of programming portions, and each of the plurality of control circuits activates a corresponding spare memory line in response to the selecting signal of the prescribed level received from a corresponding logic circuit. 
     More preferably, the plurality of memory lines include n memory lines (the n is an integer not less than two), and the plurality of spare memory lines includes a first spare memory line and a second spare memory line. The plurality of programming portions include a first programming portion correspondingly provided to the first spare memory line, and a second programming portion correspondingly provided to the second spare memory line. The replacement programming portion further includes a first decode circuit for generating a signal for driving to an unselected state, based on a programmed state of the first programming portion, one of (n−1) memory lines excluding a first memory line from the n memory lines, and a second decode circuit for generating a signal for driving to an unselected state, based on a programmed state of the second programming portion, one of (n−1) memory lines excluding a second memory line different from the first memory line from the n memory lines. The select control circuit further includes a circuit for inactivating the first memory line using an output from the second decode circuit when the first memory line is defective and for inactivating the second memory line using an output from the first decode circuit when the second memory line is defective. 
     With the above-described semiconductor memory device, the repair can be performed using only the fuses of the number required for designating the memory lines (word lines or bit lines) to be replaced. As a result, the chip area can be reduced. 
     The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic block diagram representing the overall arrangement of a semiconductor memory device  1000  according to a first embodiment of the present invention. 
     FIG. 2 is a diagram representing the arrangement of a replacement programming circuit  1  according to the first embodiment of the present invention. 
     FIG. 3 is a diagram representing the arrangement of a replacement programming circuit  10  according to the first embodiment of the present invention. 
     FIG. 4 is a circuit diagram representing the arrangement of a programming circuit using a fuse. 
     FIG. 5 is a circuit diagram related to the description of a row select control circuit  53  according to the first embodiment of the present invention. 
     FIG. 6 is a diagram representing the arrangement of a main portion of a semiconductor memory device according to a second embodiment of the present invention. 
     FIG. 7 is a diagram illustrating an example of the arrangement of a comparing portion  40  according to the second embodiment of the present invention. 
     FIGS. 8A and 8B are circuit diagrams representing the arrangement of a comparator according to the second embodiment of the present invention. 
     FIG. 9 is a circuit diagram illustrating an example of the arrangement of a row select circuit  66  according to the second embodiment of the present invention. 
     FIG. 10 is a diagram illustrating an example of the arrangement of a conventional semiconductor memory device. 
     FIG. 11 is a diagram illustrating another example of the arrangement of the conventional semiconductor memory device. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The embodiments of the present invention will be described hereinafter in detail with reference to the drawings. Throughout the drawings, the same or corresponding parts are denoted by the same reference characters, and the descriptions thereof will not be repeated. 
     First Embodiment 
     A semiconductor memory device  1000  according to the first embodiment of the present invention will be described in relation to FIG.  1 . As shown in FIG. 1, semiconductor memory device  1000  is provided with a controller  50  for receiving an external control signal to generate a corresponding internal control signal, an address buffer  51  for taking in an address ad&lt;0:5&gt; according to the control by controller  50 , a replacement programming portion  52 , a row select control circuit  53  for selectively driving a corresponding word line, a memory cell array  54  including a plurality of memory cells, a spare memory cell array  55  including a spare memory cell for replacing a defective memory cell, and a row decoder  56  for decoding an output ad&lt;0:5&gt; from address buffer  51 . 
     Replacement programming portion  52  includes a replacement programming circuit  1  shown in FIG. 2 and a replacement programming circuit  10  shown in FIG.  3 . Each of replacement programming circuits  1  and  10  includes fuses of the number required for programming a defective address. Replacement programming circuits  1  and  10  allow the replacement with two spare word lines to be performed. 
     Replacement programming circuit  1  shown in FIG. 2 includes programming circuits  2 # 0  to  2 # 5  and logic circuits  3 # 0  to  3 # 63 . Each of programming circuits  2 # 0  to  2 # 5  is formed by inverters  110  and  111 , a PMOS transistor  112 , capacitance elements  113  and  114 , and a fuse  115 , as shown in FIG.  4 . Capacitance element  114  is connected between a powersupply node for receiving a power-supply voltage and a node N 1 , and fuse  115  is connected between a ground node for receiving a ground voltage and node N 1 . Inverter  110  is connected between a node N 2  and node N 1 , and inverts a signal from node N 1 . Transistor  112  is connected between a power-supply node for receiving a power-supply voltage and node N 1 , and has a gate connected to node N 2 . Capacitance element  113  is connected between a ground node for receiving a ground voltage and node N 2 . Inverter  111  is connected between node N 2  and an output node N 3 , and inverts a signal from node N 2 . 
     The fuse is blown by a laser according to an address indicating a defective memory cell. When the fuse is blown, an H level signal is output from output node N 3 ; otherwise, an L level signal is output from output node N 3 . 
     As shown in FIG. 2, programming circuits  2 # 0  to  2 # 5  respectively output signals e 0  to e 5 . Each of logic circuits  3 # 0  to  3 # 62  includes AND circuits  4 A,  4 B and  4 C. Logic circuit  3 # 63  includes AND circuits  4 A and  4 B and an NAND circuit  6 . 
     Each of logic circuits  3 # 0  to  3 # 63  receives a signal e 0  or an inverted signal /e 0  of signal e 0 , a signal e 1  or an inverted signal /e 1  of signal e 1 , a signal e 2  or an inverted signal /e 2  of signal e 2 , a signal e 3  or an inverted signal /e 3  of signal e 3 , a signal e 4  or an inverted signal /e 4  of signal e 4 , and a signal e 5  or an inverted signal /e 5  of signal e 5 . 
     The logic circuits respectively receive different combinations of signals. More specifically, logic circuit  3 # 0  receives signals e 0 , e 1 , e 2 , e 3 , e 4 , and e 5 , while logic circuit  3 # 63  receives signals /e 0 , /e 1 , /e 2 , /e 3 , /e 4 , and /e 5 . Signals b 0  to b 63  are output from logic circuits  3 # 0  to  3 # 63 , respectively. When a fuse in any one of programming circuits  2 # 0  to  2 # 5  is blown, signal b 63  attains the H level. 
     Replacement programming circuit  10  shown in FIG. 3 includes programming circuits  12 # 0  to  12 # 5  and logic circuits  13 # 0  to  13 # 63 . Each of programming circuits  12 # 0  to  12 # 5  has the arrangement shown in FIG. 4, and has a fuse blown according to an address indicating a defective memory cell. Programming circuits  12 # 0  to  12 # 5  output signals f 0  to f 5 . Each of logic circuits  13 # 1  to  13 # 63  includes AND circuits  4 A,  4 B, and  4 C. Logic circuit  13 # 0  includes AND circuits  4 A and  4 B and an NAND circuit  6 . 
     Each of logic circuits  13 # 0  to  13 # 63  receives a signal f 0  or an inverted signal /f 0  of signal f 0 , a signal f 1  or an inverted signal /f 1  of signal f 1 , a signal f 2  or an inverted signal /f 2  of signal f 2 , a signal f 3  or an inverted signal /f 3  of signal f 3 , a signal f 4  or an inverted signal /f 4  of signal f 4 , and a signal f 5  or an inverted signal /f 5  of signal f 5 . 
     The logic circuits respectively receive different combinations of signals. More specifically, logic circuit  13 # 63  receives signals f 0 , f 1 , f 2 , f 3 , f 4 , and f 5 , while logic circuit  13 # 0  receives signals /f 0 , /f 1 , /f 2 , /f 3 , /f 4 , and /f 5 . 
     Signals c 0  to c 63  are output from logic circuits  13 # 0  to  13 # 63 , respectively. When a fuse in any one of programming circuits  12 # 0  to  12 # 5  is blown, signal c 0  attains the H level. 
     Signal b 63  is used as a signal for indicating whether to use or not to use a spare memory cell, and signals b 0  to b 62  are used to inactivate (repair) the word lines corresponding to  63  addresses out of  64  addresses. The word line corresponding to the one remaining address is inactivated using signal c 63 . 
     Similarly, signal c 0  is used as a signal for indicating whether to use or not to use a spare memory cell, and signals c 1  to c 63  are used to inactivate (repair) the word lines corresponding to  63  addresses out of  64  addresses. The word line corresponding to the one remaining address is inactivated using signal b 0 . 
     Now, row select control circuit  53  will be described in relation to FIG.  5 . FIG. 5 shows the relations between row select control circuit  53  and memory cell array  54  and spare memory cell array  55 . 
     In the diagram, memory cells are represented by reference characters m 0  to m 63 , word lines disposed corresponding to the rows are represented by reference characters w 0  to w 63 , and a bit line disposed corresponding to a column is represented by the reference characters “bit,” respectively. Further, spare memory cells that can replace the memory cells are represented by reference characters r 0  and r 1 , and spare word lines that can replace the word lines are represented by reference characters sw 0  and sw 1 . 
     Bit line “bit” is connected to memory cells m 0  to m 63  and spare memory cells r 0  and r 1 , and transmits data read from or to be written into memory cells m 0  to m 63  and spare memory cells r 0  and r 1 . Word lines w 0  to w 63  are connected to memory cells m 0  to m 63 , and each word line sends a selecting signal to a corresponding memory cell. Spare word lines sw 0  and sw 1  are connected to spare memory cells r 0  and r 1 , and each spare word line sends a selecting signal to a corresponding spare memory cell. 
     Row select control circuit  53  includes comparators  20 # 0  and  20 # 1  and AND circuits  19 # 0  and  19 # 1 . Comparator  20 # 0  compares signals e 0  to e 5  with an address signal ad&lt;0:5&gt; and outputs an H level signal when a match occurs between signals e 0  to e 5  and address signal ad&lt;0:5&gt;; otherwise, it outputs an L level signal. AND circuit  19 # 0  receives an output from comparator  20 # 0  and a signal b 63 , and activates spare word line sw 0 . The selection of spare memory cell r 0  is controlled by signal b 63 . 
     Comparator  20 # 1  compares signals f 0  to f 5  with address signal ad&lt;0:5&gt; and outputs an H level signal when a match occurs between signals f 0  to f 5  and address signal ad&lt;0:5&gt;; otherwise, it outputs an L level signal. AND circuit  19 # 1  receives an output from comparator  20 # 1  and signal c 0 , and activates spare word line sw 1 . The selection of spare memory cell r 1  is controlled by signal c 0 . 
     Row select control circuit  53  further includes OR circuits  15 # 1  to  15 # 62  and  16 # 1  to  16 # 62 , NAND circuits  17 # 0  to  17 # 63 , and AND circuits  18 # 0  to  18 # 63 . 
     For word lines w 1  to w 62  are disposed OR circuits  15 # 1  to  15 # 62  and  16 # 1  to  16 # 62 , NAND circuits  17 # 1  to  17 # 62 , and AND circuits  18 # 1  to  18 # 62 , respectively. 
     For word line w 0 , an NAND circuit  17 # 0  and an AND circuit  18 # 0  are disposed. For word line w 63 , an NAND circuit  17 # 63  and an AND circuit  18 # 63  are disposed. 
     OR circuits  15 # 1  to  15 # 62  respectively receive signals b 1  to b 62  and signals c 1  to c 62 . OR circuits  16 # 1  to  16 # 62  each receive signals c 0  and b 63 . 
     NAND circuits  17 # 1  to  17 # 62  respectively receive outputs from OR circuits  15 # 1  to  15 # 62  and outputs from OR circuits  16 # 1  to  16 # 62 . NAND circuit  17 # 0  receives signals b 0  and b 63 . NAND circuit  17 # 63  receives signals c 0  and c 63 . NAND circuits  17 # 0  to  17 # 63  respectively output row address non-selection signals s 0  to s 63 . 
     AND circuits  18 # 0  to  18 # 63  respectively receive row address nonselection signals s 0  to s 63  and decode signals a 0  to a 63 . Decode signals a 0  to a 63  are obtained by decoding address signal ad&lt;0:5&gt; by row decoder  56 . Word lines w 0  to W 63  are respectively activated according to outputs from AND circuits  18 # 0  to  18 # 63 . 
     Now, the operation of semiconductor memory device  1000  according to the first embodiment of the present invention will be described. First, a test is conducted for memory cells m 0  to m 63 , and if no defect is found, none of the fuses in programming circuits  2 # 0  to  2 # 5  and  12 # 0  to  12 # 5  is blown by the laser. Programming circuits  2 # 0  to  2 # 5  and  12 # 0  to  12 # 5  output L level signals e 0  to e 5  and f 0  to f 5 . 
     In this case, signals b 63  and c 0  take a value indicating that no replacement is to be performed (L level). AND circuits  19 # 0  and  19 # 1  output the L level signal. Thus, spare word lines sw 0  and sw 1  are not activated. On the other hand, NAND circuits  17 # 0  to  17 # 63  output the H level signals. Thus, a corresponding word line is activated in response to decode signals a 0  to a 63 . 
     Next, the case in which a test is conducted for memory cells m 0  to m 63  and in which defects are found in memory cells m 0  and m 1  will be described. According to the address of a defective memory cell m 0 , all the fuses in programming circuits  2 # 0  to  2 # 5  are blown by the laser. According to the address of a defective memory cell m 1 , the fuse in programming circuit  12 # 0  is blown by the laser. 
     Signals b 0  and c 1  attain the H level, signals b 63  and c 0  take a value indicating that a replacement is to be performed (H level), and the remaining signals attain the L level. 
     In this case, of OR circuits  15 # 1  to  15 # 62 , OR circuit  15 # 1  outputs an H level signal, and OR circuits  15 # 2  to  15 # 62  output L level signals. Address non-selection signals respectively output from NAND circuits  17 # 0  and  17 # 1  attain the L level, and the address non-selection signals output from NAND circuits  17 # 2  to  17 # 63  attain the H level. 
     Thus, even when an address signal for selecting memory cell m 0  or memory cell m 1  is input (even when decode signal a 0  or a 1  is at the H level), word lines w 0  and w 1  are not activated. 
     On the other hand, when an address signal for selecting any one of memory cells m 2  to m 63  is input (when one of decode signals a 2  to a 63  attains the H level), a corresponding word line is activated. 
     When address signal ad&lt;0:5&gt; for selecting memory cell m 0  is input, comparator  20 # 0  outputs an H level signal, thereby activating spare word line sw 0 . As a result, spare memory cell r 0  is accessed instead of memory cell m 0 . 
     When address signal ad&lt;0:5&gt; for selecting memory cell m 1  is input, comparator  20 # 1  outputs an H level signal, thereby activating spare word line sw 1 . As a result, spare memory cell r 1  is accessed instead of memory cell m 1 . 
     As seen from the above, according to the arrangement of the present invention, a fuse (replacement control circuit) dedicated for the switching control need not be provided, and a portion of the fuses used for designating an address can be utilized to activate a spare word line instead of the word line to which a defective memory cell is connected. Thus, the number of fuses and the layout area can be reduced. 
     Moreover, the arrangement of programming circuits  2 # 0  to  2 # 5  and  12 # 0  to  12 # 5  is not limited to the one shown in FIG. 4, and similar effects can be achieved by employing other arrangements. 
     In addition, in the present embodiment, two types of circuits, replacement programming circuits  1  and  10 , are used; however, the same effect can be achieved by using either one of the two kinds of circuits. 
     Furthermore, although the description is given regarding the replacement of a word line, the present invention is not so limited and can be applied to the replacement per bit line. 
     Second Embodiment 
     The semiconductor memory device according to the second embodiment of the present invention will be described in relation to FIG.  6 . FIG. 6 is a diagram representing the arrangement of a main portion of the semiconductor memory device according to the second embodiment of the present invention. As shown in FIG. 6, the semiconductor memory device according to the second embodiment of the present invention is provided with replacement programming circuits  1 # 0  to  1 # 3  and  10 # 0 , a comparison portion  40 , a row decoder  56 , a memory cell array  64 , a spare memory cell array  65 , and a row select circuit  66 . 
     Replacement programming circuits  1 # 0  to  1 # 3  have the same arrangement as that of replacement programming circuit  1  shown in FIG. 2, while replacement programming circuit  10 # 0  has the same arrangement as replacement programming circuit  10  shown in FIG.  3 . Each of replacement programming circuits  1 # 0  to  1 # 3  and  10 # 0  includes fuses of the number required for designating an address of a defective memory cell. 
     As described above, for each of replacement programming circuits  1 # 0  to  1 # 3 , one of  64  outputs is used as a signal for indicating whether to use or not to use a spare memory cell. A word line that cannot be repaired by replacement programming circuits  1 # 0  to  1 # 3  is replaced based on an output from replacement programming circuit  10 # 0 . Replacement programming circuits  1 # 0  to  1 # 3  and  10 # 0  allow the repair with five spare word lines to be performed. 
     In the diagram, word lines disposed corresponding to the rows are represented by reference characters w 0  to w 63 , and bit lines disposed corresponding to the columns are represented by reference characters bit0 to bit63, respectively. Further, spare word lines that can replace the word lines are represented by reference characters sw 0 , sw 1 , sw 2 , sw 3  and sw 4 . Moreover, each of the bit lines is connected to a corresponding memory cell and a corresponding spare memory cell. 
     Programming circuits  2 # 0  to  2 # 5  included in replacement programming circuit  1 # 0  output signals z 0 # 0  to z 0 # 5 , programming circuits  2 # 0  to  2 # 5  included in replacement programming circuit  1 # 1  output signals z 1 # 0  to z 1 # 5 , programming circuits  2 # 0  to  2 # 5  included in replacement programming circuit  1 # 2  output signals z 2 # 0  to z 2 # 5 , programming circuits  2 # 0  to  2 # 5  included in replacement programming circuit  1 # 3  output signals z 3 # 0  to z 3 # 5 , and programming circuits  12 # 0  to  12 # 5  included in replacement programming circuit  10 # 0  output signals z 4 # 0  to z 4 # 5 , respectively. 
     Logic circuits  3 # 0  to  3 # 63  included in replacement programming circuit  1 # 0  output signals y 0 # 0  to y 0 # 63 , logic circuits  3 # 0  to  3 # 63  included in replacement programming circuit  1 # 1  output signals y 1 # 0  to y 1 # 63 , logic circuits  3 # 0  to  3 # 63  included in replacement programming circuit  1 # 2  output signals y 2 # 0  to y 2 # 63 , logic circuits  3 # 0  to  3 # 63  included in replacement programming circuit  1 # 3  output signals y 3 # 0  to y 3 # 63 , and logic circuits  13 # 0  to  13 # 63  included in replacement programming circuit  10 # 0  output signals y 4 # 0  to y 4 # 63 , respectively. 
     Signals y 0 # 63 , y 1 # 63 , y 2 # 63 , y 3 # 63 , and y 4 # 0  are used as signals for indicating whether to use or not to use a spare memory cell. These signals attain the H level when the replacement is to be performed; otherwise, the signals attain the L level. 
     As shown in FIG. 7, comparing portion  40  includes comparators  70 # 0  to  70 # 4  and AND circuits  72 # 0  to  72 # 4 . The arrangement of comparators  70 # 0  to  70 # 4  is the same as comparator  20 # 0 . Comparators  70 # 0  to  70 # 4  respectively output enable signals ENABL 0  to ENABL 4 . 
     An example of the arrangement of a comparator is shown in FIGS. 8A and 8B. The comparator includes an EXNOR unit  70  shown in FIG.  8 A and an AND circuit  74  shown in FIG.  8 B. EXNOR unit  70  includes EXNOR circuits  770 # 0  to  770 # 5 . EXNOR circuit  770 #k (k=0,1, . . . ,5) receives an address signal ad(k) and an output from a programming circuit (for instance, Z 0 #k, Z 1 #k, . . . ) and outputs a signal B(k). AND circuit  74  calculates the logical product of bit B( 0 ) to B( 5 ) of signal B&lt;0:5&gt;, and outputs an enable signal (for instance, enable signal ENABL 0 ). 
     As shown in FIG. 7, comparator  70 # 0  compares address signal ad&lt;0:5&gt; with signals z 0 # 0  to z 0 # 5 . Comparator  70 # 1  compares address signal ad&lt;0:5&gt; with signals z 1 # 0  to z 1 # 5 . Comparator  70 # 2  compares address signal ad&lt;0:5&gt; with signals z 2 # 0  to z 2 # 5 . Comparator  70 # 3  compares address signal ad&lt;0:5&gt; with signals z 3 # 0  to z 3 # 5 . Comparator  70 # 4  compares address signal ad&lt;0:5&gt; with signals z 4 # 0  to z 4 # 5 . 
     AND circuit  72 # 0  activates spare word line sw 0  based on an output from comparator  70 # 0  and a signal y 0 # 63 . AND circuit  72 # 1  activates spare word line sw 1  based on an output from comparator  70 # 1  and a signal y 1 # 63 . AND circuit  72 # 2  activates spare wordline sw 2  based on an output from comparator  70 # 2  and a signal y 2 # 63 . AND circuit  72 # 3  activates spare word line sw 3  based on an output from comparator  70 # 3  and a signal y 3 # 63 . AND circuit  72 # 4  activates spare wordline sw 4  based on an output from comparator  70 # 4  and a signal y 4 # 0 . 
     Row select circuit  66  shown in FIG. 6 activates word lines w 0  to w 63  according to decode signals a 0  to a 63  received from row decoder  56 , signals y 0 # 0  to y 0 # 63 , signals y 1 # 0  to y 1 # 63 , signals y 2 # 0  to y 2 # 63 , signals y 3 # 0  to y 3 # 63 , and signals y 4 # 0  to y 4 # 63 . 
     An example of a specific arrangement of row select circuit  66  is shown in FIG.  9 . In FIG. 9, an OR circuit  22  calculates an OR of signals y 0 # 63  to y 3 # 63 , and an OR circuit  23  calculates an OR of signals y 0 # 0  to y 3 # 0 . Similarly, OR circuits  24 # 1 , . . . ,  24 # 62  respectively calculate the OR&#39;s of signals y 0 # 1  to y 3 # 1 , . . . , signals y 0 # 62  to y 3 # 62 . 
     NAND circuit  17 # 0  receives an output from OR circuit  22  and an output from OR circuit  23 , and NAND circuit  17 # 63  receives signals y 4 # 0  and y 4 # 63 . Further, OR circuits  15 # 1  to  15 # 62  respectively receive outputs from OR circuits  24 # 1  to  24 # 62  and signals y 4 # 1  to y 4 # 62 . Each of OR circuits  16 # 1  to  16 # 62  receives signal y 4 # 0  and an output from OR circuit  22 . 
     As described above, when employing a plurality of spare word lines, the semiconductor memory device can be arranged to include two types of address programming circuits (replacement programming circuits  1  and  10 ) for different repair locations so that every memory cell can be repaired while only a small layout area is required. 
     Although the present invention has been described and illustrated in detail, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the spirit and scope of the present invention being limited only by the terms of the appended claims.