Patent Publication Number: US-10778925-B2

Title: Multiple column per channel CCD sensor architecture for inspection and metrology

Description:
PRIORITY APPLICATIONS 
     The present application is a continuation-in-part of U.S. patent application Ser. No. 16/397,072 filed Apr. 29, 2019 and entitled “Dual-Column-Parallel CCD Sensor And Inspection Systems Using A Sensor”, which is a divisional of U.S. Pat. No. 10,313,622 issued Jun. 4, 2019 and entitled “Dual-Column-Parallel CCD Sensor And Inspection Systems Using A Sensor”, which claims priority to U.S. Provisional Patent Application 62/319,130 filed Apr. 6, 2016 and entitled “Dual-Column-Parallel CCD Sensor And Inspection Systems Using A Sensor”. The present application also claims priority to U.S. Provisional Patent Application 62/733,635 filed Sep. 20, 2018 and entitled “Three-Column Per Channel CCD Sensor Architecture For Inspection And Metrology”, by Brown et al. 
    
    
     BACKGROUND OF THE DISCLOSURE 
     Field of the Disclosure 
     The present application relates to image sensors and associated electronic circuits suitable for sensing radiation at visible, UV, deep UV (DUV), vacuum UV (VUV), extreme UV (EUV) and X-ray wavelengths, and for sensing electrons or other charged particles, and to methods for operating such image sensors. The sensors and circuits are particularly suitable for use in inspection systems, including those used to inspect photomasks, reticles, and semiconductor wafers. 
     Related Art 
     The integrated circuit industry requires inspection tools that provide increasingly higher sensitivity to detect smaller defects and particles, while maintaining high throughput for a lower cost of ownership. The semiconductor industry is currently manufacturing semiconductor devices with feature dimensions around 20 nm and smaller. Within a few years, the industry will be manufacturing devices with feature dimensions around 5 nm. Particles and defects just a few nm in size can reduce wafer yields and must be captured to ensure high-yield production. Furthermore, efforts have been spent on speeding up inspection to cope with the transition from today&#39;s 300 mm wafers to 450 mm wafers in the near future. Thus, the semiconductor industry is driven by ever greater demand for inspection tools that can achieve high sensitivity at high speed. 
     An image sensor is a key component of a semiconductor inspection tool. It plays an important role in determining defect detection sensitivity and inspection speed. Considering their image quality, light sensitivity, and readout noise performance, CCDs are widely used as image sensors for semiconductor inspection applications. There are two fundamental ways to improve the sensitivity of CCD image sensors. The first one is to increase the amplitude of the signal, and the second one is to reduce the noise level. In the past decades, many efforts have been devoted in both ways. As various technologies, such as backside illumination, anti-reflection coatings, full depletion, and micro-lenses, have been developed, the sensitivity of CCD image sensors has been increased with advancement of quantum efficiency and thereby improvement in signal intensity. 
     CCD image sensors suffer from three major types of noise, namely shot noise, dark-current noise, and read noise. The photons incident on an image sensor carry time-dependent fluctuations in the photon flux. The image sensor exhibits lower shot noise, the statistical variations in the incident photon flux, when it uses pixel binning and/or frame averaging because then there will be more collected photons per output pixel. Dark current is generated by the thermal excitation of charge carriers into the conduction band within the silicon of an image sensor. CCD cooling, Multi-Pinned-Phase (MPP), and/or dark image subtraction techniques have suppressed the dark-current noise to such a level that its contribution is negligible over the short exposure times (typically a few to hundreds of milliseconds) used in high-speed inspection. Read noise arises from the on-chip electronics and can be reduced by carefully designed electronics and image processing techniques. 
     As readout speed increases, read noise becomes the dominant noise factor limiting the sensitivity of a CCD image sensor. The CCD on-chip amplifier requires high bandwidth to measure the signal (image) charge in each pixel at a high pixel clock rate. Read noise increases as the result of the high bandwidth. Conventional full-frame CCD image sensors employ a serial-readout architecture, thus demanding a high pixel clock rate (such as 20 MHz or higher) and high readout speed. It is difficult or impossible to reduce the read noise at such high speeds. As pixel sizes on the article being inspected are reduced in order to detect smaller defects (for example, by increasing the optical magnification of the image), increased readout speed is needed to maintain overall inspection speed (e.g. to keep the number of wafers inspected per hour approximately constant as the image pixel size decreases). This means that read noise will tend to increase rather than decrease. 
     Column-Parallel CCD (CPCCD) image sensors are known in the art. Each column of CPCCD pixels is equipped with an amplifier that facilitates parallel readout of each image charge. See, for example, J. R. Janesick, “Scientific charge-coupled devices”, 2001, SPIE, p 60. The column-parallel readout eases the requirements for pixel clock rate and can help reduce read noise at high readout speed. However, it is only practical to implement a column-parallel readout architecture for large-pixel CCD designs (such as pixel widths of more than 30 μm). In the case of a CCD sensor with a small column pitch (such as a pitch between about 6 μm and about 25 μm, which is best suited to high-speed semiconductor inspection applications), the one-amplifier-per-column layout cannot be implemented due to space constraints. Furthermore, a column parallel design requires that all outputs be clocked simultaneously. That results in high switching currents and high read noise. 
     Therefore, a need arises for providing a CCD image sensor that facilitates high-sensitivity and high-speed operation of an inspection system and overcomes some, or all, of the above disadvantages. 
     SUMMARY OF THE DISCLOSURE 
     The present invention is directed to multiple-column-per-channeler-channel CCD image sensors and an associated readout method that facilitates both high-sensitivity and high-speed readout operations by way of utilizing a novel readout circuit to coordinate the high-speed transfer of charges generated in associated groups of adjacent pixel columns to a single (shared) floating diffusion for readout by a single (shared) amplifier. This one-amplifier-per-two-or-more-columns arrangement facilitates the production of CCD sensors with small column pitches (e.g., between about 6 μm and about 25 μm) that are suitable for high-speed semiconductor inspection applications by way of avoiding the high switching currents, high read noise, and the amplifier space problems associated with one-amplifier-per-column CPCCD sensors. Moreover, the one-amplifier-per-multiple-columns (i.e., multiple-columns-per-channel, also referred to below as N-columns-per-channel) arrangement is implemented using an output clock rate of a summing gate control signal that is multiple-times (e.g., 2×, 3× or 4×) the line clock rate speed, thereby avoiding both the high pixel clock rate issues associated with conventional CPCCD sensors, and also avoiding the high read noise problems associated with serial readout approaches. 
     According to a specific embodiment of the invention, a three-column-per-channel CCD image sensor includes an array of pixels arranged in parallel columns, and a novel readout circuit includes multiple readout structures respectively coupled to receive image data from an associated group of columns. Each readout structure includes three rows of transfer gates operably coupled to receive image charges from the associated group of columns, a shared summing gate coupled to alternately receive image charges passed from the transfer gates, and an output circuit including a single amplifier configured to generate output voltage signals based on the image charges transferred from the associated group of columns. According to an aspect of the present invention, the three rows of transfer gates in each group of associated columns are operably coupled such that a (first) transfer gate control signal applied to a first-row (first) transfer gate in one column is substantially simultaneously applied to a (fourth) transfer gate in the associated second column, and such that a second transfer gate control signal applied to a first-row (second) transfer gate in the second column is substantially simultaneously applied to a (third) transfer gate in the first column. According to another aspect, the summing gate of each readout structure is configured to receive respective image charges from the three third-row transfer gates during three different time periods, and is configured to pass each respectively received image charge to an output circuit (e.g., a floating diffusion coupled to an amplifier) in accordance with one or more summing gate control signals. Coupling the transfer gates in adjacent columns and utilizing a shared summing gate in this manner facilitates efficient and reliable transfer of image charges from three or more columns of pixels to one shared output circuit with low noise and at a reasonable clock rate (i.e., three or more times the line clock rate), thereby facilitating the production of image sensors particularly suitable for use in inspection systems, including those used to inspect photomasks, reticles, and semiconductor wafers. 
     According to another embodiment, an image sensor is fabricated on a semiconductor substrate (e.g. monocrystalline silicon) having formed therein multiple symmetrical fork-shaped buried diffusions, each having parallel upstream (first, second and third) elongated portions, a downstream (fourth) elongated portion in which the sense node (i.e., floating diffusion) is formed, and an intervening (fifth) V-shaped merge section connecting the three upstream elongated portions to the downstream elongated portion. The upstream elongated portions respectively define the associated columns mentioned above. Polycrystalline silicon pixel gate structures are formed over the upstream elongated portions, thereby forming pixels that serve to generate image charges and buffer cells that serve to transfer the image charges along the three associated columns toward the V-shaped merge section. Three rows of transfer gates are generated by polycrystalline silicon transfer gate structures formed over portions of the upstream (first, second and third) elongated portions, thereby forming three transfer gates configured to transfer image charges along each column toward the V-shaped merge section. A summing gate is formed by way of a polycrystalline silicon gate structure disposed over the V-shaped merge section and configured to receive image charges from the three associated columns of each channel by way of the three upstream elongated portions, and configured to pass the receive image charges to the downstream elongated section. As in the embodiment described above, the transfer gate electrodes in the three rows of transfer gates are effectively coupled to facilitate efficient and reliable transfer of image charges from the three associated columns to the summing gate, and the summing gate is controlled by a summing gate control signal to pass the image charges from the three associated columns to the shared output circuit with low noise and at a reasonable clock rate (i.e., three times the line clock rate). By utilizing symmetrical fork-shaped buried diffusions in combination with the coupled transfer gates and summing gates to transfer image charges to an sense node (e.g., a shared floating diffusion disposed in the downstream elongated diffusion portion), the present invention facilitates the highly efficient, high speed and low noise transfer of image charges from two columns of pixels for output using a single amplifier controlled or otherwise operably coupled to the floating diffusion. Since the transfer gates of adjacent columns switch alternately, the clock signals to the transfer gates are approximately balanced and generate minimal substrate currents thus allowing high-speed clocking while maintaining a low noise level. Since each output circuit is connected to three columns, in contrast to a conventional high-speed CCD that might have 12, 16 or more columns per output, the pixel clock rate in image sensor is only three times the line clock rate instead of 12, 16 or more times the line clock rate. Since noise increases with a higher bandwidth, an image sensor with a lower pixel clock rate can be less noisy than one with higher pixel clock rate. 
     According to a specific embodiment, cross-coupling of associated polycrystalline silicon transfer gate structures disposed in the two different rows is achieved by conductive (e.g., metal or doped polycrystalline silicon) linking structures connected between the three associated transfer gate structures. That is, a (first) transfer gate structure disposed in the first row of one column is electrically connected by way of a (first) conductive linking structure to a (fifth) transfer gate structure disposed in the second row of the associated third column, and also connected by way of a (second) conductive linking structure to a (third) transfer gate structure disposed in the third row and second column. This arrangement facilitates reliable control over the three associated transfer gate structures by applying the associated transfer gate control signal to the (first) transfer gate structure, whereby the transfer gate control signal is substantially simultaneously applied to the two associated transfer gate structures (i.e., by way of transmission over the (first) conductive linking structures). In one embodiment, the conductive linking structures are implemented using polycrystalline silicon, where the three associated transfer gate structures and the conductive linking structure are fabricated as an integral step-shaped composite polycrystalline silicon structure This embodiment avoids the extra complexity, cost and potential reduced yield associated with using two layers of metal interconnections, or alternatively allows a second layer of metal to be used to reduce the series resistance of the clock signals enabling higher speed operation. 
     According to another specific embodiment, the summing gate is implemented using a tapered polycrystalline silicon structure having an upstream edge (i.e., the edge facing the upstream elongated diffusion portions) that is longer than its downstream edge (i.e., the edge facing the downstream elongated diffusion portion). The tapered summing gate structure facilitates efficient transfer of image charges from the upstream elongated diffusion portions to the downstream elongated diffusion portion. In a preferred embodiment, a similarly tapered output gate structure is disposed over a downstream portion of the V-shaped merge section (i.e., between the summing gate structure and the downstream elongated diffusion portion), and functions to prevent charge spill from the sense node back to the summing gate. 
     According to another specific embodiment, the shared output circuit of each associated column group includes a floating diffusion formed in the downstream (fourth) elongated diffusion portion, and an on-chip pre-amplifier that is operably coupled to the floating diffusion by way of a conductive (metal or polycrystalline silicon) structure. In one embodiment, the conductive structure is implemented using a polycrystalline silicon structure that is formed and patterned such that a lower/vertical poly portion extends through a contact hole to the floating diffusion, and an upper/horizontal poly portion extends horizontally from the lower/vertical poly portion and forms the gate structure for a first-stage gain transistor of the on-chip pre-amplifier. This arrangement facilitates self-alignment of the floating diffusion and the polysilicon gate structure and facilitates connection to the pre-amplifier without the need for a metal interconnect, thereby further reducing noise and floating diffusion capacitance and increasing charge conversion efficiency, thus improving the sensor&#39;s signal-to-noise ratio. 
     An inspection method utilizing the multiple-column-per-channel CCD sensor of the present invention includes directing and focusing radiation onto the sample and receiving radiation from the sample and directing received radiation to a CCD image sensor. The received radiation may include scattered radiation or reflected radiation. The CCD sensor incorporates a N-column-per-channel readout structure comprising N rows of transfer gates, a common summing gate, a floating diffusion (also known as a sense node), and an amplifier per group of columns. The N-column-per-channel readout structure is implemented in a way that all the columns have identical charge transfer and signal readout paths. In one embodiment, the N-column-per-channel CCD may use a self-aligned floating diffusion with a polysilicon contact connected to the amplifier. In another embodiment the N-column-per-channel CCD may comprise metal interconnects in the readout structure with equalized channel response and minimized crosstalk. 
     The method of inspecting can further include generating clock voltage waveforms and controlling the timing of the on-chip N-column-per-channel readouts and the off-chip signal processing circuits for appropriate synchronization of the sensor readout and digitization of the output signals. Exemplary clock voltage waveforms and timing configurations used to drive an exemplary three-column-per-channel configuration as an example to explain some of the possible methods for synchronization of the sensor output. The clock driving schemes may be implemented by an apparatus including an analog-to-digital converter (ADC), a digital signal processor, a clock driver, and external processing, storage, and control circuitry. 
     A system for inspecting a sample is also described. This system includes an illumination source, a light detection device, optics configured to direct light from the illumination source to the sample and to direct light outputs or reflections from the sample to the device, and a driving circuit. In one embodiment, the light detection device may comprise a CCD array sensor, such as a Time Delay Integration (TDI) sensor. In another embodiment, the device may comprise a CCD line sensor. The CCD sensor incorporates a N-column-per-channel readout structure comprising, per group of N associated columns, N×N transfer gates, a common summing gate, a floating diffusion, and an amplifier. Each column of the CCD pixels is terminated by a N transfer gates. Each group of N associated columns combine into a common summing gate, and the common summing gate tapers towards a small floating diffusion where an amplifier converts each image charge to a corresponding output voltage signal. The N-column-per-channel readout structure is implemented in a way that all the columns have substantially identical charge transfer and signal readout path characteristics. The driving circuit supplies bias voltages and clock signals to the on-chip N-column-per-channel readout structure and off-chip signal processing circuits in order to read the sensor output with the desired timing. 
     In one embodiment, the CCD sensor may further comprise a semiconductor membrane. In another embodiment, the semiconductor membrane may include circuit elements formed on a first surface of the semiconductor membrane and a pure boron layer deposited on a second surface of the semiconductor membrane. In yet another embodiment, the system may include multiple CCD sensors. 
     The sample may be supported by a stage, which moves relative to the optics during the inspection. The electrical charges may be read out from the sensor in synchrony with the motion of the stage. 
     The exemplary inspection system may include one or more illumination paths that illuminate the sample from different angles of incidence and/or different azimuth angles and/or with different wavelengths and/or polarization states. The exemplary inspection system may include one or more collection paths that collect light reflected or scattered by the sample in different directions and/or are sensitive to different wavelengths and/or to different polarization states. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  illustrates a multiple-column-per-channel CCD sensor having an architecture for inspection and metrology according to a generalized embodiment of the present invention. 
         FIGS. 2A, 2B and 2C  are partial block diagrams depicting simplified image capture and image transfer operations performed by the CCD sensor of  FIG. 1  during a sample inspection operation according to an exemplary embodiment of the present invention. 
         FIGS. 3A and 3B  respectively depict a simplified three-column-per-channel CCD sensor and a simplified four-column-per-channel CCD sensor according to alternative exemplary embodiments of the present invention. 
         FIGS. 4A, 4B, 4C, 4D, 4E, 4F, 4G and 4H  illustrate a portion of the exemplary three-column-per-channel CCD sensor of  FIG. 3A  during operation. 
         FIG. 5  illustrates a partial three-column-per-channel CCD sensor including a readout structure fabricated in accordance with another specific embodiment of the present invention. 
         FIG. 6  is a simplified plan view showing a partial three-column-per-channel CCD sensor in accordance with another specific embodiment of the present invention. 
         FIG. 7  is a simplified plan view depicting operation of the three-column-per-channel CCD sensor of  FIG. 6  in accordance with an embodiment of the present invention. 
         FIG. 8  illustrates exemplary voltage waveforms and timing configurations of clock signals to drive the on-chip three-column-per-channel readouts and off-chip signal processing circuits in accordance with another exemplary embodiment of the present invention. 
         FIG. 9  illustrates an exemplary apparatus for driving a multiple-column-per-channel CCD image sensor and off-chip signal processing circuits with synchronization of the image sensor readout. 
         FIG. 10  illustrates an exemplary inspection system. 
         FIGS. 11A and 11B  illustrates an exemplary inspection system with line illumination and one or more collection channels. 
         FIG. 12  illustrates an exemplary inspection system with normal and oblique illumination. 
     
    
    
     DETAILED DESCRIPTION OF THE DRAWINGS 
     The present invention relates to an improvement in sensors for semiconductor inspection systems. The following description is presented to enable one of ordinary skill in the art to make and use the invention as provided in the context of a particular application and its requirements. As used herein, directional terms such as “top”, “bottom”, “over”, “under”, “underneath”, “left”, “right”, “vertical”, “horizontal” and “down” are intended to provide relative positions for purposes of description, and are not intended to designate an absolute frame of reference. Various modifications to the described embodiments will be apparent to those with skill in the art, and the general principles defined herein may be applied to other embodiments. Therefore, the present invention is not intended to be limited to the particular embodiments shown and described, but is to be accorded the widest scope consistent with the principles and novel features herein disclosed. 
       FIG. 1  is a block diagram depicting a simplified system  100  for inspecting a sample S using a multiple-column-per-channel charge-coupled-device (CCD) image sensor  110  and an analog-to-digital converter (ADC)  150  according to a generalized embodiment of the present invention. System  100  includes a radiation source  101  (e.g., a laser) and an optical system  103  configured to direct emitted radiation DR onto sample S, and configured to direct received (e.g., reflected) radiation RR from an imaged region IR of sample S onto image sensor  110 . As explained below, image sensor  110  generates analog output signals V OUT1  to V OUTW  that are converted into digital image data values Dx by ADC  150 . System  100  also includes a digital signal processing (DSP) and external processing (EP) circuit  160  that receive and processes digital image data values Dx from ADC  150 , and a timing generator circuit  170  that generates clock, reset and control signals utilized to control the operations of image sensor  110  and ADC  150 . Those skilled in the art will recognize that the operation of system  100 , which is described below with reference to certain exemplary embodiments, is greatly simplified herein for brevity. 
     Referring to the upper right portion of  FIG. 1 , image sensor  110  includes an array of pixels arranged in multiple pixel groups  111 - 1  to  111 -W, and optical system  103  is configured such that portions of received radiation RR received from sections S 1  to SN of imaged region IR are respectively directed onto corresponding pixel groups  111 - 1  to  111 -W of image sensor  110 . Each pixel group  111 - 1  to  111 -W includes multiple (M×N) pixels disposed in multiple (M) rows  113 - 1  to  113 -M and multiple (N) columns  112 - 1  to  112 -N, where the term “multiple” is defined herein to mean two or more. For example, pixel group  111 - 1  includes M horizontally-aligned rows of pixels, where pixels P 11 , P 12  . . . P 1 N collectively form (define) an associated top row  113 - 1  of pixels, and pixels PM 1 , PM 2  . . . PMN define an associated bottom (edge) row of pixels. Similarly, pixel group  111 - 1  includes N vertically-aligned columns of pixels, where pixels P 11 , P 21  . . . PM 1  define an associated leftmost column  112 - 1 , and pixels P 1 N, P 2 N . . . PMN define an associated rightmost column  112 -N. Note that the three-dot symbols provided in image sensor group  111 - 1  are intended to indicate that each pixel group  111 - 1  to  111 -W includes multiple rows and multiple columns—in exemplary practical image sensors disclosed herein that are considered useful in high-speed inspection applications, each pixel group would typically comprise three or more columns of pixels and between one row (i.e., as in a line sensor) and several thousand rows of pixels. Each pixel group  111 - 2  to  111 -W is understood including the same number of pixels as that included in pixel group  111 - 1 . 
     The pixels of pixel groups  111 - 1  to  111 -W are configured in cooperation with optical system  103  to capture and store corresponding analog image data values (charges) having values (charge amounts) determined by the amount of radiation received from a corresponding section of imaged region IR during each imaging operation performed by system  100 . For example, at a given moment when imaged region IR is oriented relative to sample S as shown in  FIG. 1 , each pixel Pll to PMN of pixel group  111 - 1  captures and stores an image data value (charge) received by way of radiation portion RP 1  from a corresponding imaged region section S 1  (e.g., the portion of sample S disposed in the leftmost portion of imaged region IR), thereby causing pixels P 11  to PMN to capture and store a corresponding charge in the manner described below. At the same time, the pixels of pixel group  111 - 2  store image data received by way of radiation portion RP 2  from a corresponding imaged region section S 2 , which is adjacent to section S 1 . In this way, radiation received from each section S 1  to SW of imaged region IR is thereby captured by a corresponding pixel group  111 - 1  to  111 -W of image sensor  110  such that the pixels of image sensor  110  capture image data from the entire portion of sample S disposed within imaged region IR. Similarly, the pixels of each pixel group store image data received from a corresponding sub-section of each imaged region section. 
     According to a presently preferred embodiment, system  100  performs scanning-type inspection operations during which sample S undergoes a scanning movement (i.e., is translated or moved) relative to optical system  103  and image sensor  110  while directed radiation DR is directed onto sample S and received radiation RR is directed to image sensor  110 . In one embodiment, sample S is moved (e.g., using an X-Y table) in a downward (negative Y-axis) direction relative to radiation source  101 , optical system  103  and image sensor  110 , which are maintained in a stationary (fixed) position during each scanning-type inspection operation. In another embodiment, sample S is maintained in a stationary position while radiation source  101 , optical system  103  and image sensor  110  are moved in an upward (Y-axis) direction relative to sample S. As explained below, charges stored in image sensor  110  are shifted in a synchronized manner such that captured image data from sample S is transferred from pixel to pixel along the columns of pixels of image sensor  110  in coordination with the scanning movement of sample S. 
       FIGS. 2A to 2C  depict the synchronized movement of sample S and the charges stored in image sensor  110  during an exemplary simplified scanning-type inspection operation.  FIGS. 2A to 2C  show representative portions of system  100  ( FIG. 1 ) at sequential times t 0 , t 1  and t 2  (indicated by “ 100 (t 0 )”, “ 100 (t 1 )” and “ 100 (t 2 )” in  FIGS. 2A to 2C , respectively. Each of these figures shows an enlarged section S 1  of sample S and eight pixels P 11  to P 24  disposed in the top four rows of the leftmost two columns  112 - 1  and  112 - 2  of pixel group  111 - 1  of image sensor  110  (other portions of sample S and system  100  are omitted for brevity and clarity). For explanatory purposes, section S 1  of sample S is divided into sub-sections S 100  to S 115 , which correspond to adjacent minute regions of sample S. 
       FIG. 2A  shows system  100  at an initial time t 0  when the optical system (not shown) is positioned relative to sample S such that imaged region IR(t 0 ) encompasses sub-sections S 102  to S 115  of section S 1 . As explained above, at this time radiation from sections S 102  to S 115  is directed to pixel group  111 - 1  by way of radiation (light) portions RP 102  to RP 115 , whereby pixels P 11  to P 24  respectively capture/store charges C 102  to C 115  based on the amount of received light from sub-sections  5102  to S 115 . That is, pixels P 11  to P 24  of pixel group  111 - 1  receive corresponding light portions RP 102  to RP 115  reflected/emitted from corresponding sub-sections of section S 1  of sample S, whereby each pixel receives and stores a corresponding charge C 102  to C 115  having an amount determined by the amount of radiation received during time period t 0 . For example, pixel P 11  captures received radiation portion RP 102  from sub-section S 102  of sample S and generates/stores a corresponding charge C 102  having a charge level that increases by the amount of received radiation received during period t 0 . Similarly, pixel P 12  generates/stores charge C 112  in accordance with a radiation amount associated with radiation portion R 112  received from sub-section S 112  during period t 0 , pixel P 21  generates/stores charge C 103  generates/stores charge C 103  in accordance with radiation portion R 103  received from sub-section  5103  during period t 0 , etc. 
       FIG. 2B  shows system  100 (t 1 ) after movement of sample S relative to the optical system (not shown) causes imaged region IR(t 1 ) to move incrementally upward (i.e., in direction D) relative to sample S, whereby imaged region IR(t 1 ) encompasses sub-sections S 101  to S 114  of section S 1 . Referring to the right side of  FIG. 2B , at the same time imaged region IR is moved incrementally in direction D, and image sensor  110  is simultaneously driven (i.e., controlled by way of line clock signals PV 1 , PV 2  and PV 3 ) such that the analog image data values (i.e., charges C 102  to C 115 ) are generated and systematically transferred along columns  112 - 1  and  112 - 2  from pixels P 11  to P 24  toward an output sensing node (described below). Specifically, as imaged region IR(t 1 ) shifts to encompass sub-sections S 101  to S 114 , image sensor  110  is driven to shift charges C 102  to C 115  downward, whereby charges C 102  to C 114  are shifted along column  112 - 1  from pixels P 11 -P 31  to pixels P 21 -P 41  and charges C 112  to C 114  are shifted along column  112 - 2  from pixels P 12 -P 32  to pixels P 22 -P 42  (as indicated by the curved dashed arrows in  FIG. 2B ), and charges C 105  and C 115  are shifted either to a subsequent pair of pixels or out of pixel group  111 - 1  to readout circuit  120 - 1 . Note that the downward shifting rate of charges C 102  to C 114  is coordinated (synchronized) with the movement rate of imaged region IR(t 1 ) such that each of these charges continues to be influenced by radiation received from the same sub-section of sample S during period t 1 . That is, charge C 102 , which is stored in pixel P 21  during period t 1 , is influenced by radiation portion RP 102  transmitted from sub-section S 102  during period t 1 . Note also that sub-sections S 101  and S 111 , which are effectively added to imaged region IR(t 1 ) by way of movement of optics  103  ( FIG. 1 ), transmit radiation portions RP 101  and RP 111 , respectively, that are transmitted by way of the optical system to pixels P 11  and P 12  during period t 1 . 
       FIG. 2C  shows system  100 (t 2 ) after an additional incremental movement in direction D of the imaged region IR of sample S relative to the optical system (not shown) causes imaged region IR(t 2 ) encompass sub-sections S 100  to S 113  of section S 1 . Similar to that shown in  FIG. 2B , image sensor  110  is driven to systematically transfer charges C 101  to C 113  downward from pixels P 11  to P 24 . By continuously driving image sensor  110  in coordination with movement of the optical system relative to the sample in the manner described above with reference to  FIGS. 2A to 2C , analog image data is continuously captured during the scanning-type inspection operation performed by system  100 . 
     In alternative embodiments, the above-mentioned shifting of charged along columns  112 - 1  and  112 - 2  may be accomplished using three-phase line control signals PV 1 , PV 2  and PV 3 , as indicated in  FIG. 1 , or may be accomplished using two-phase line control signals. An advantage of a sensor configured with three-phase line control signals is that charge may be moved in either direction by generating line control signals PV 1  to PV 3  using alternative sequences that are known in the art, whereas two-phase line control signals can only move the charges in one direction. In another alternative embodiment, an image sensor using three-phase line control signals may be configured with buffer, transfer and output circuits at both the top and bottom of the pixel array to enable readout of the signal in either direction (i.e., by way of a second ADC circuit and a second DSP/EP circuit). Depending on whether single direction or bidirectional transfer is required, system  100  may use two-phase or three-phase line control signals. 
     Referring again to  FIG. 1 , image sensor  110  also includes readout circuits  120 - 1  to  120 -W, where each readout circuit (e.g., readout circuit  120 - 1 ) includes an optional row of buffer cells  123 , a plurality of transfer (shift register) gates T 11  to TNN arranged in rows  133 - 1  to  133 -N, a summing gate  142 - 1  that is operably coupled to the transfer gates of last transfer gate row  133 -N, and an output circuit (sensing node)  145 - 1  including a floating diffusion  144 - 1  and an amplifier  147 - 1  that are operably coupled to summing gate  142 - 1  and configured to generate and transmit analog image data values V OUT1  to ADC  150 . Note that each readout circuit  120 - 1  to  120 -W is operably coupled to an associated pixel groups  111 - 1  to  111 -W of the generalized embodiment such that output circuits/sense nodes  145 - 1  to  145 -W respectively generate and transmit analog image data values V OUT1  to V OUTW  to corresponding portions  150 - 1  to  150 -W of ADC  150 . As described below, the charges that move along each column of pixels of image sensor  110  are transferred to specific charge storage cells and shift registers before reaching the output circuits/sense nodes. Accordingly, the buffer cells and transfer gates of each readout circuit  120 - 1  to  120 -W are referred to as being part of a corresponding column of associated pixel groups  111 - 1  to  111 -W. For example, charge storage cell B 1  and shift registers T 11  and TN 1  of readout circuit  120 - 1  are referred to as part of the leftmost column  112 - 1  of pixel group  111 - 1 , which includes pixels P 11 , P 21  and PM 1 . 
     Buffer cells B 1  to BN of readout circuit  120 - 1  respectively includes at least one row  123  of N charge storage (buffer) cells that are controlled by one or more buffer cell signals BG to receive and buffer (temporarily store) analog image data values (charges) transferred in parallel (i.e., simultaneously) from an edge (bottom) row  113 -M of pixels in associated pixel groups  111 - 1  to  111 -W. For example, upon each assertion of buffer cell signal BG, each buffer cell B 1 , B 2  . . . BN of readout circuit  120 - 1  respectively receives a charge from corresponding pixels PM 1 , PM 2  . . . PMN disposed in a lowermost (edge) row  113 -N of pixel group  111 - 1 . In some embodiments, the buffer cells may be omitted, whereby charges are transferred from the edge row of pixels directly to the uppermost shift register elements of transfer circuits  130 - 1  to  130 -W. 
     Transfer circuits  130 - 1  to  130 -W include shift registers (storage cells) T 11  to TNN that are disposed in columns  112 - 1  to  112 -N and arranged in N transfer gate rows  133 - 1  to  133 -N and controlled by transfer clock signal CLK 1  to CLKN. In a preferred embodiment, the number of transfer gate rows  133 - 1  to  133 -N and the number of transfer clock signal CLK 1  to CLKN is equal to the number (N) of columns  112 - 1  to  112 -N disposed in each associated pixel group  111 - 1  to  111 -W (e.g., when each pixel group includes three columns, three rows of transfer gates are provided and controlled by three transfer clock signals). The N transfer gates in each column are respectively controlled by one of the N transfer clock signals such that an image charge received by an uppermost transfer gate from an associated buffer cell is sequentially passed along the vertically arranged transfer gates to a lowermost transfer gate. For example, in column  112 - 1 , an image charge is received and stored by uppermost transfer gate T 11  from associated buffer cell B 1  in response to assertion of transfer clock signal CLK 1 , and the image charge is then sequentially passed along transfer gates disposed in column  112 - 1  until it is received and stored by transfer gate TN 1  in response to assertion of transfer clock signal CLKN. The operation of transfer gates T 11  to TNN is described in additional detail below. 
     Each readout structure of sensor  110  includes a shared summing gate that receives image charges from the associated group of transfer gates, and in turn passes the image signals to an associated sense node in accordance with a summing gate control signal SG. For example, readout structure  120 - 1  includes shared summing gate  142 - 1  configured to receive image from transfer gates TN 1  to TNN in lowermost (edge) row  133 -N, and to pass the image signals to an output circuit  145 - 1  including a floating diffusion (sense node)  144 - 1  and an amplifier  147 - 1 . With this arrangement, as an image charge moves down column  112 - 1 , transfer gates T 11  to TN 1  control the transfer of the image charge from pixel PM 1  into the common summing gate  142 - 1 . Transfer gates T 12  to TN 2  and T 13  to TN 3  perform a similar function for columns  112 - 2  and  112 - 3 , respectively. Summing gate  142 - 1  sequentially receives image charges passed along columns  112 - 1 ,  112 - 2  and  112 - 3  without adding noise during charge transfer, and sequentially passes the image charges to floating diffusion  144 - 1 , which is configured to collect and store the image charge for readout by way of amplifier  147 - 1 , which converts image charge to voltage and transmits buffered voltage to ADC  150 . ADC  150  includes multiple analog-to-digital converter units  150 - 1  to  150 -W that respectively convert analog output signals V OUT1  to V OUTN  into corresponding digital output values Dx that are then transferred to DSP/EP circuit  160  for processing and storage using known techniques. The image charge transfer operation is described below with reference to a three-column-per-channel sensor, and exemplary voltage waveforms and timing configurations of the above clock/control signals are depicted in  FIG. 8 . 
     Timing generator  170  includes a pixel control circuit  171 , a pixel buffer control circuit  173 , a transfer gate control circuit  175 , an output control circuit  177 , and an ADC control circuit  179 , where each of these control circuits is configured using known circuit design techniques to generate one or more of the clock/control signals utilized to operate sensor  110  in the manner described below. For example, pixel control circuit  171  generates two-or-more line control signals PVX that control the image capture and charge shifting operations of pixel groups  111 - 1  to  111 -W in the manner described below. In a similar manner, buffer control circuit  173  generates buffer control signal BG that controls the charge buffering operations of buffer circuits B 1  to BN, transfer gate control circuit  175  generates transfer gate control signals CLK 1  to CLKN that control the operation transfer gates T 11  to TNN in the manner described below, output control circuit  177  generates output circuit clock signal SG and reset gate control signal RG that control the operation of summing gate  142 - 1  and output circuit  145 - 1  as described below, and ADC control circuit  179  generates an ADC clock signal ADC-C that controls the timing of analog-to-digital conversion operations of ADC circuits  150 - 1  to  150 -W, whereby final image data values Dx are generated and transmitted to DSP &amp; EP circuit  160  for storage and/or processing. Those skilled in the art will recognize that the various control circuits and control signals depicted in  FIG. 1  are greatly simplified for purposes of description, and that the functions and control signals utilized in the description below are utilized solely for purposes of describing the present invention, and are not intended to limit the appended claims unless otherwise specified in the claims. 
       FIGS. 3A and 3B  respectively depict a simplified three-column-per-channel CCD sensor  110 A and a simplified four-column-per-channel CCD sensor  110 B according to alternative exemplary embodiments of the present invention, where each of sensors  110 A and  110 B may be implemented in place of generalized sensor  110  of  FIG. 1 . Specifically, CCD sensor  110 A ( FIG. 3A ) includes a group  111 A- 1  having pixels P 11  to PM 3  arranged three columns  112 A- 1 ,  112 A- 2  and  112 A- 3  and M pixel rows  113 A- 1  to  113 A-M that transfer image charges to a readout circuit structure  120 A- 1 , and CCD sensor  110 B includes a group  111 B- 1  having pixels P 11  to PM 4  arranged four columns  112 B- 1  to  112 B- 4  and M pixel rows  113 B- 1  to  113 B-M that transfer image charges to a readout circuit structure  120 B- 1 . In each sensor  110 A and  110 B, image charges are generated and transferred down the columns of pixels in response to three-phase pixel control (line clock) signals PV 1 , PV 2  and PV 3  as described above with reference to  FIG. 1 . Each sensor  110 A and  110 B includes multiple channels like those shown in  FIGS. 3A and 3B . 
     Each readout structures  120 A- 1  ( FIG. 3A ) and  120 B- 1  ( FIG. 3B ) includes a row of N buffer cells, N×N transfer gates disposed in N rows and N columns, a shared summing gate and an output circuit, where “N” represents the number of pixel columns disposed in pixel group  111 A- 1  and  111 B- 1  (i.e., N equals three in the case of sensor  110 A, and N equals four in the case of sensor  110 B). For example, pixel group  111 A- 1  of sensor  110 A includes three columns  112 A- 1 ,  112 A- 2  and  112 A- 3 , so readout structure  120 A- 1  includes a row  123 A including three buffer cells B 1 , B 2  and B 3 , nine transfer gates T 11  to T 33  disposed in three rows  133 A- 1 ,  133 A- 2  and  133 A- 3 , shared summing gate  142 A- 1  and output circuit  145 A- 1 . Similarly, pixel group  111 B- 1  of sensor  110 B includes four columns  112 B- 1 ,  112 B- 2 ,  112 B- 3  and  112 B- 4 , so readout structure  120 B- 1  includes a row  123 B including four buffer cells B 1 , B 2 , B 3  and B 4 , sixteen transfer gates T 11  to T 44  disposed in four rows  133 B- 1 ,  133 B- 2 ,  133 B- 3  and  133 A- 4 , shared summing gate  142 B- 1  and output circuit  145 B- 1 . In each case the buffer cells and transfer gates are configured to transfer respective image signals from multiple (N) columns to the (single) shared summing gate in accordance with N transfer gate control signals (i.e., three signals CLK 1 , CLK 2  and CLK 3  in the case of readout circuit  120 A- 1 , and four signals CLK- 1 , CLK 2 , CLK 3  and CLK 4  in the case of readout circuit  120 B- 1 ), which in turn passes the image signals to an associated output circuit  145 A- 1  or  145 B- 1  in accordance with a summing gate control signal SG. According to an aspect of the present invention, the N×N transfer gates of output circuits  120 A- 1  and  120 B- 1  are configured and coupled such that each of the N transfer gates in each transfer gate row of output circuits  120 A- 1  and  120 B- 1  is controlled by a different transfer gate control signal, and each of the N transfer gates in each of the N columns of output circuits  120 A- 1  and  120 B- 1  is controlled by a different transfer gate control signal. For example, in output circuit  120 A- 1  ( FIG. 3A ), transfer gate T 11  is controlled by signal CLK 1 , transfer gate T 12  is controlled by signal CLK 2 , and transfer gate T 13  is controlled by signal CLK 3 , whereby the three transfer gates in transfer gate row  133 A- 1  are controlled by different transfer gate control signals. Similarly, referring to column  112 A- 1  of output circuit  120 A- 1  ( FIG. 3A ), transfer gate T 11  is controlled by signal CLK 1 , transfer gate T 21  is controlled by signal CLK 2 , and transfer gate T 31  is controlled by signal CLK 3 , whereby the three transfer gates in column  112 A- 1  are controlled by different transfer gate control signals. This feature similarly applies to rows  133 A- 2  and  133 A- 3  and columns  112 A- 2  and  112 A- 3  of output circuit  120 A- 1 , and to rows  133 B- 1  to  133 B- 4  and  112 B- 1  to  112 B- 4  of output circuit  120 B- 1 . In one embodiment, this feature is achieved by way of applying each transfer gate control signal to a transfer gate in one row and passing the transfer gate control signal to one or more associated transfer gates in one or more other rows by way of conductive link(s). For example, in  FIG. 3A  transfer gate T 11  passes signal CLK 1  to associated transfer gate T 23  in transfer gate row  133 A- 2  by way of a conductive link  131 A- 11 , which in turn passes signal CLK 1  to associated transfer gate T 32  in transfer gate row  133 A- 3  by way of a conductive link  131 A- 12 . In a similar manner, transfer gate T 21  passes signal CLK 2  to associated transfer gate T 33  by way of a conductive link  131 A- 2 , and transfer gate T 22  passes signal CLK 3  to associated transfer gate T 13  by way of a conductive link  131 A- 3 . 
       FIGS. 4A to 4H  depict a portion of three-column-per-channel CCD sensor  110 A ( FIG. 3A ) during the transfer of image charges from pixel group  111 A- 1  to readout structure  120 A- 1  during exemplary simplified operation of sensor  110 A. In these figures the operating state of sensor  110 A is depicted at sequential time periods t 0  to t 7 , which are indicated in parentheses at the top of each figure (e.g.,  FIG. 4A  shows sensor  110 A during an initial time period t 0 , indicated by “ 110 A(t 0 )”). To simplify the following description, only the position of image charges starting with charges C 11 , C 12  and C 13  is depicted in  FIGS. 4A to 4H , and other image charges concurrently being processed by readout circuit structure  120 A- 1  during and prior to time tO are omitted for clarity. 
       FIG. 4A  shows sensor  110 A(t 0 ) when image charges C 11 , C 12  and C 13  are simultaneously transferred in parallel from edge pixel row  113 A-M to buffer row  123 A in accordance with assertion of buffer control signal BG, and charges C 21 , C 22  and C 23  are simultaneously transferred from a prior pixel row (not shown) into edge row  113 A-M in accordance with control signals PVX (e.g., signals PV 1 , PV 2  and PV 3 ). At this point image charges C 21 , C 22  and C 23  are respectively stored in pixels PM 1 , PM 2  and PM 3  and continue to receive image data from a sample, as described above, prior to being passed into readout structure  120 A- 1 . 
       FIGS. 4B, 4C and 4D  depict sensor  110 A at time periods t 1 , t 2  and t 3  during the alternating (sequential) transfer of image charges C 11 , C 12  and C 13  into first transfer gate row  133 A- 1  from buffer cells B 1  to B 3  according to a simplified exemplary embodiment. During time period t 1  ( FIG. 4B ), transfer gate control signal CLK 1  is actuated/toggled (signals CLK 2  and CLK 3  are de-activated) to cause the transfer of image charge C 11  from buffer cell B 1  in (first) column  112 A- 1  into (first) transfer gate T 11 . During time period t 2  ( FIG. 4C ), transfer gate control signal CLK 2  is actuated (and signals CLK 1  and CLK 3  are de-activated) to cause the transfer of image charge C 12  from buffer cell B 2  in (second) column  112 A- 2  into transfer gate T 12 , and to cause the transfer of image charge C 11  from first transfer gate T 11  into transfer gate T 21 . During time period t 3  ( FIG. 4D ), transfer gate control signal CLK 3  is actuated (signals CLK 1  and CLK 2  are de-activated) to cause the transfer of image charge C 13  from buffer cell B 3  in middle (third) column  112 A- 3  into transfer gate T 13 , to cause the transfer of image charge C 11  from transfer gate T 11  into transfer gate T 31 , and to cause the transfer of image charge C 12  from transfer gate T 12  into transfer gate T 22 . As indicated in  FIG. 4D , subsequent to the transfer of image charge C 13 , image charges C 21 , C 22  and C 23  are simultaneously transferred in parallel from edge pixel row  113 A-M to buffer row  123 A in accordance with assertion of buffer control signal BG, and charges C 31 , C 32  and C 33  are simultaneously transferred from a prior pixel row (not shown) into edge row  113 A-M in accordance with control signals PVX. 
       FIGS. 4E, 4F and 4G  depict sensor  110 A during time periods t 4 , t 5  and t 6  during the subsequent sequential transfer of image charges C 21 , C 22  and C 23  from buffer row  123 A into output circuit  120 A- 1  while image charges C 11 , C 12  and C 13  are sequentially transferred into summing gate  142 - 1 . 
       FIG. 4E  depicts image sensor  110  during (first) time period t 4  after the second row of image charges are into output circuit  120 A- 1 , when (first) transfer clock signal CLK 1  is again asserted (i.e., CLK 1 =HI) to transfer a (first) image charge C 21  of the second row into (first) transfer gate T 11 , and also to transfer (fourth) image charge C 11  of the first row of image charges into summing gate  142 A- 1 . As indicated by the dashed-line arrows, transfer gates T 11 - 133  are configured and coupled such that the assertion of signal CLK 1  during time period t 4  causes image charge C 21  to be transferred from (first) buffer cell B 1  to (first) transfer gate T 11 , causes image charge C 12  to be transferred from (second) transfer gate T 22  to (third) transfer gate T 32 , and causes image charge C 13  to be transferred from (fourth) transfer gate T 13  to (fifth) transfer gate T 23 . Note that the assertion of signal CLK 1  causes the transfer of one optical charge in each of the three columns  112 A- 1  to  112 A- 3  (i.e., buffer cell B 1  and transfer gate T 11  are in column  112 A- 1 , transfer gates T 22  and T 32  are in second column  112 A- 2 , and transfer gates T 13  and T 23  are in third column  112 A- 3 ). Also note that the assertion of signal CLK 1  causes the transfer of optical charges such that only one optical charge is disposed in each of the three transfer gate rows  133 A- 1  to  133 A- 3  during a given time period (i.e., charges C 21 , C 12  and C 13  are respectively disposed in transfer gates T 11 , T 32  and T 23  during time t 4 , where transfer gate T 11  is disposed in first transfer gate row  133 A- 1 , transfer gate T 23  is disposed in second transfer gate row  133 A- 2 , and transfer gate T 32  is disposed in third transfer gate row  133 A- 3 ). With this arrangement, one image charge (i.e., image charge C 11  in  FIG. 4E ) is transferred from (sixth) transfer gate T 31  into shared summing gate  142 A- 1  during (first) time period t 4 . 
       FIG. 4F  depicts image sensor  110  during (second) time period t 5  when (second) transfer clock signal CLK 2  is asserted (i.e., CLK 2 =HI) to transfer a (second) image charge C 22  of the second row of image charges into (seventh) transfer gate T 12 , and also to transfer (fifth) image charge C 12  of the first row of image charges into summing gate  142 A- 1 . As indicated by the dashed-line arrows, assertion of signal CLK 2  during time period t 5  causes image charge C 22  to be transferred from (second) buffer cell B 2  to (seventh) transfer gate T 12 , causes image charge C 21  to be transferred from (first) transfer gate T 11  to (eight) transfer gate T 21 , and causes image charge C 13  to be transferred from (fifth) transfer gate T 23  to (ninth) transfer gate T 33 . As indicated in  FIG. 4F , during (first) time period t 4 , summing gate  142 A- 1  is controlled by way of summing gate control signal SG to transfer (fourth) image charge C 11  to floating diffusion  144 A- 1  of output circuit  145 A- 1 , whereby the associated charge stored on floating diffusion  144 A- 1  causes amplifier  147 A- 1  to generate an output voltage signal V OUT1  that is equal to a voltage V C11  corresponding to a charge amount of image charge C 11 . In addition (second) image charge C 12  is transferred from (third) transfer gate T 32  to summing gate  142 A- 1  during time period t 5 . 
     During subsequent time period t 6  ( FIG. 4G ), (third) transfer clock signal CLK 3  is asserted (i.e., CLK 3 =HI) to transfer a (third) image charge C 23  of the second row of image charges into (fourth) transfer gate T 13 , and also to transfer (sixth) image charge C 13  of the first row of image charges into summing gate  142 A- 1 . As indicated by the dashed-line arrows, assertion of signal CLK 3  during time period t 6  causes image charge C 23  to be transferred from (third) buffer cell B 3  to (fourth) transfer gate T 13 , causes image charge C 22  to be transferred from (seventh) transfer gate T 12  to (second) transfer gate T 22 , and causes image charge C 21  to be transferred from (eighth) transfer gate T 21  to (sixth) transfer gate T 31 . In addition, summing gate  142 A- 1  is controlled by summing gate control signal SG (e.g., transmitted from output control circuit  177 , see  FIG. 1 ) to transfer image charge C 12  into floating gate  144 A- 1 , whereby the associated charge stored on floating diffusion  144 A- 1  causes amplifier  147 A- 1  to generate an output voltage signal V OUT1  equal to a voltage V C12  corresponding to image charge C 12 . Note that floating diffusion  405 - 4  may be reset between each charge transfer (i.e. after transfer of C 11  before transfer of C 12 ). The reset transistor and the reset signal are not depicted in  FIGS. 4A-4H  in order to simplify the figures and explain the charge transfer operation more clearly. In addition, a buffer control circuit (e.g., circuit  173 ; see  FIG. 1 ) asserts buffer control signal BG that control buffer cells B 1 , B 2  and B 3  to simultaneously respectively receive seventh, eighth and ninth image charges C 31 ,C 32 ,C 33  (i.e., a third row of image charges) from edge pixel row  113 A-M during (third) time period t 6  after (sixth) image charge C 23  is transferred from (third) buffer cell B 3  to (fourth) transfer gate T 13 . Subsequently, a fourth row of image charges C 41 , C 42  and C 43  are transferred in to edge pixel row  113 A-M in the manner described above. 
       FIG. 4H  depicts sensor  110 A during a subsequent time period t 7  during which transfer clock signal CLK 1  is again asserted to transfer the first image charge C 31  of the third row of image charges from buffer cell B 1  into transfer gate T 11 , to transfer image charge C 23  from transfer gate T 13  into transfer gate T 23 , to transfer image charge C 22  from transfer gate T 22  to transfer gate T 32 , and also to transfer (sixth) image charge C 13  of the first row of image charges into summing gate  142 A- 1 . In addition, summing gate  142 A- 1  is controlled to transfer image charge C 13  into floating gate  144 A- 1 , thereby causing amplifier  147 A- 1  to generate an output voltage signal V OUT1  equal to a voltage V C13  corresponding to image charge C 13 . 
     As established by the example shown in  FIGS. 4A to 4H , sensor  100 A provides a one-amplifier-per-three-columns (three-columns-per-channel) arrangement that facilitates the production of CCD sensor with small column pitches (e.g., between about 6 μm and about 25 μm) by way of avoiding the high switching currents, high read noise, and the amplifier space problems associated with one-amplifier-per-column approaches, while only marginally increasing output clock rates (i.e., summing gate control signal SG has a clock rate that is only three-times the line clock rate of line control signal(s) PVX). 
       FIG. 5  illustrates a partial multiple-column-per-channel CCD image sensor  100 C according to an exemplary preferred embodiment of the present invention. 
     According to an aspect of the present invention, sensor  100 C includes a symmetrical fork-shaped buried diffusion  502  that serves to facilitate the transfer of image charges from pixels disposed in three columns  112 C- 1 ,  112 C- 2  and  112 C- 2  to one shared output circuit. Fork-shaped buried diffusion  502  comprises a continuous n-doped region formed in a semiconductor substrate  501  and includes parallel upstream (first, second and third) elongated portions  502 - 1 ,  502 - 2  and  502 - 3  that are connected to a downstream (fourth) elongated portion  502 - 4  by way of a - shaped merge section  502 - 5 . The continuous n-doped region is formed using known techniques such that image charges (comprising electrons) accumulated by the pixels in each column  112 C- 1  to  112 C- 3  are constrained to travel along upstream elongated portions  502 - 1  to  502 - 3 , and are respectively directed by fork-shaped merge section  502 - 5  into downstream elongated portion  502 - 4 . 
     Pixels are formed in respective associated columns  112 C- 1  to  112 C- 3  by way of polycrystalline silicon pixel gate structures  515 - 1 ,  515 - 2  and  515 - 3  respectively formed over upstream elongated portions  502 - 1 ,  502 - 2  and  502 - 3 . Additional pixels may be formed in each column  511  and  512  (e.g., above edge pixel row  113 C-M including pixels PM 1 , PM 2  and PM 3 , which are shown in the figure). Image charges generated by pixels PM 1 , PM 2  and PM 3  are constrained to move down columns  112 C- 1  to  112 C- 3  by upstream elongated diffusion portions  502 - 1 ,  502 - 2  and  502 - 3 , respectively, and by three-phase pixel control signals PV 1 , PV 2  and PV 3  that are generated in the manner described below. 
     Similar to the previous embodiment, sensor  100 C includes three rows  113 C- 1 ,  113 C- 2  and  113 C- 2  having nine transfer gates T 11  to T 33 , where first row  113 C- 1  includes transfer gates T 11 , T 13  and T 12 , second row  113 C- 2  includes transfer gates T 21 , T 23  and T 22 , and third row includes transfer gates T 31 , T 33  and T 32 . First row transfer gates T 11 , T 13  and T 12  are formed by polycrystalline silicon transfer gate structures  504 - 11 ,  504 - 31  and  504 - 21  respectively operably disposed over upstream elongated diffusion portions  502 - 1 ,  502 - 2  and  502 - 3  between buffer cell row  123 C and second row  133 C- 2  of transfer gates. Second transfer gate row  113 C- 2  is formed by polycrystalline silicon transfer gate structures  504 - 12 ,  504 - 32  and  504 - 22  respectively operably disposed over elongated diffusion portions  502 - 1 ,  502 - 2  and  502 - 3  between the first transfer gate row  113 C- 1  and third transfer gate row  133 C- 3 . Third transfer gate row  113 C- 3  is formed by polycrystalline silicon transfer gate structures  504 - 13 ,  504 - 33  and  504 - 23  respectively operably disposed over elongated diffusion portions  502 - 1 ,  502 - 2  and  502 - 3  between the second transfer gate row  113 C- 2  and summing gate  142 C, which is disposed over V-shaped merge section  502 - 4 . With this arrangement, transfer gates T 11 , T 12  and T 13  are configured to transfer image charges passed along the leftmost (first) column  112 C- 1  toward V-shaped merge section  502 - 4 , transfer gates T 12 , T 22  and T 32  are configured to transfer image charges passed along the rightmost (second) column  112 C- 2  toward V-shaped merge section  502 - 4 , and transfer gates T 13 , T 23  and T 33  are configured to transfer image charges passed along the central (third) column  112 C- 3  toward summing gate  142 C. 
     As set forth above, the transfer gate structures forming transfer gates T 11  to T 13  are effectively coupled to facilitate efficient and reliable transfer of image charges from columns  112 C- 1 ,  112 C- 2  and  112 C- 3  to summing gate  142 C. Specifically, (first) transfer gate T 11 , (third) transfer gate T 32  and (fifth) transfer gate T 23  are coupled to simultaneously receive transfer gate control signal CLK 1 , which is transmitted on signal line  562 - 1 , (eighth) transfer gate T 21 , (ninth) transfer gate T 33  and (seventh) transfer gate T 12  are coupled to receive transfer gate control signal CLK 2 , which is transmitted on signal line  562 - 2 , and (sixth) transfer gate T 31 , (fourth) transfer gate T 13  and (second) transfer gate T 22  are coupled to receive transfer gate control signal CLK 3 , which is transmitted on signal line  562 - 3 . This arrangement is referred to herein as effective coupling because associated transfer gates (e.g., T 11 , T 23  and T 32 ) are effectively coupled such that, for example, when (first) transfer gate control signal CLK 1  is applied on first transfer gate structure T 11 , it is substantially simultaneously applied to (third) transfer gate T 32  and (fifth) transfer gate structure T 23 . 
     According to the depicted embodiment, the effective coupling of associated transfer gates is at least partially achieved using one or more conductive (e.g., metal or doped polycrystalline silicon) linking structures that are connected between the associated transfer gate structures. Referring to the region between columns  112 C- 1  and  112 C- 2  in  FIG. 5 , first-row, first column transfer gate T 11  is implemented by horizontally oriented elongated polycrystalline silicon gate structure  504 - 11 , and is connected to second-row, middle column transfer gate structure  504 - 32  by way of an associated conductive linking structure  532 . Similarly, transfer gate T 23  is coupled to transfer gate T 32  by a second conductive link structure extending between gate structures  504 - 32  and  504 - 23 . This linking arrangement facilitates reliable cross-couple control over associated transfer gate structures  504 - 11 ,  504 - 32  and  504 - 23  in that, when transfer gate control signal CLK 1  is applied to transfer gate structure  504 - 11 , it is also substantially simultaneously applied to transfer gate structures  504 - 32  and  504 - 23  (i.e., by way of transmission over intervening conductive linking structures  532 ). 
     A summing gate  142 C is formed over V-shaped merge region  502 - 4  such that summing gate  142 C functions to transfer image charges from columns  112 C- 1 ,  112 C- 2  or  112 C- 3   512  to downstream elongated diffusion portion  502 - 4 . In one embodiment, summing gate  142 C is implemented as a tapered polycrystalline silicon structure  505  having an upstream edge  505 U having a width W 1  (i.e., measured in a direction perpendicular to columns  112 C- 1  to  112 C- 3 ) that is longer than a width W 2  of its downstream edge  505 D. This tapered summing gate structure facilitates efficient transfer of image charges from upstream elongated diffusion portions  502 - 1  to  502 - 3  to downstream elongated diffusion portion  502 - 4 . Summing gate  142 C is controlled by applying summing gate control signal SG to structure  505 , whereby summing gate  142 C functions in a manner similar to that described above with reference to summing gate  142 A, where a clock rate of summing gate control signal SG is three times faster than a line clock rate of the pixel control signals PV 1 , PV 2  and PV 3 . In one embodiment, an additional tapered output gate structure  506  is disposed over a downstream portion of the V-shaped merge section  502 - 5  (i.e., between summing gate structure  505  and downstream elongated diffusion portion  502 - 4 ), and functions to prevent charge spill from the sense node back to summing gate  142 C. 
     During operation, image charges are generated in pixels  520 - 1  and  520 - 2  are transferred along columns  511  and  512  at a clock rate determined by line clock signals PV 1 , PV 2  and PV 3 . Examples of waveforms of the various control signals are shown in  FIG. 8 . A simplified explanation follows of how waveforms such as those shown in  FIG. 8  can transfer charges in sensor  500 . Note that  FIG. 8  includes the control signal VBG for a buffer cell which is present in some embodiments, but not depicted in  FIG. 5 . When transfer gate control signal C 1  generates a high voltage (i.e. a voltage that is more positive than a low voltage) on signal line  562 - 1 , potential wells are formed under transfer gate structures  504 - 11  and  504 - 22 . Similarly, when transfer gate control signal C 2  generates a high voltage on signal line  562 - 2 , potential wells are formed under transfer gate structures  504 - 12  and  504 - 21 . When line clock signal PV 3  is driven to a low voltage, image charges transfer from under pixels  520 - 1  and  520 - 2  (or, alternatively, when the control signal VB on the buffer cell in, for example,  FIGS. 5G and 8A  is driven to a low voltage, image charges transfer from under intervening buffer cells in columns  511  and  512 , not shown) to under transfer gate structures  504 - 11  and  504 - 12 . Implanted barriers at appropriate locations in channels  502 - 1  and  502 - 2  prevent the charges from transferring under gates  504 - 21  and  504 - 22  while control signals C 1  and C 2  are at approximately equal potentials. The use of implanted barriers to enable two-phase clocking in CCDs is well known. Next, transfer gate control signal C 1  toggles such that the voltage on signal line  562 - 1  switches from high to low, while transfer gate control signal C 2  is still high, whereby potential wells under transfer gates  504 - 11  and  504 - 22  collapse. Thus, the image charge under transfer gate  504 - 11  moves under transfer gate  504 - 21 , and an image charge under transfer gate  504 - 22  moves under summing gate  505 . When transfer gate control signal C 2  switches from high to low, the image charge under transfer gate  504 - 21  moves under summing gate structure  505  while the image charge under transfer gate  504 - 12  moves under transfer gate  504 - 22 . By way of example but not as a limitation, a high voltage may mean a voltage of approximately +5V, whereas a low voltage may mean a voltage of approximately −5V, relative to the potential of the substrate. One skilled in the relevant art understands that the appropriate voltages to use depend on many factors including doping level(s) in the buried channel, doping levels of the polysilicon gate electrodes, thicknesses and dielectric constants of dielectric layers, and dimensions and full-well capacity of the pixels and gate structures. 
     By repeating the operations described above, image charges generated by pixels in two columns (i.e., columns  511  and  512 ) are sequentially transferred to a single output circuit by way of shared (common) summing gate  505 . Simultaneously, other pairs of columns sequentially clock their charges under the corresponding common summing gates provided for those pairs of columns. Exemplary voltage waveforms and timing configurations of the above clock signals are depicted in additional detail in  FIGS. 8A, 8B, and 8C . In the preferred embodiment shown in  FIG. 5 , each column utilizes one transfer gate pair to clock image charge to the common summing gate. In other embodiments, two or more transfer gate pairs per column could be used to implement other charge transfer schemes. Note that sensor  500  may also be operated to sum charges from the two columns in summing gate  505  by reading out summing gate  505  at the same rate as the line clock instead of at twice the line clock frequency. This allows an instrument incorporating sensor  500  to have different operating modes that trade off spatial resolution for improved signal-to-noise ratio. 
     Referring to the lower portion of  FIG. 5 , output circuit  145 C is implemented by a floating diffusion  144 C formed in downstream elongated diffusion portion  502 - 4 , and an on-chip pre-amplifier circuit  147 C that is operably coupled to floating diffusion  144 C by way of a suitable (metal or polysilicon) conductive structure  535 . On-chip pre-amplifier  147 C functions to convert image charges stored on floating diffusion  144 C to voltage signals, and to deliver buffered voltage signals V OUT  to output terminal  510 . A pre-amplifier is widely used in CCD sensors to amplify and/or buffer the signal and prepare it for further processing. Multiple pre-amplifier and buffer configurations known in the art are suitable for use in multiple-column-per-channel CCD image sensor  100 C. Pre-amplifier  147 C may comprise multiple transistors, resistors, and capacitors. By way of example, amplifier  147 C may comprise two stages of source followers. The first stage source follower includes a gain transistor M 1  and a current sink transistor M 2 ; the second stage source follower includes a gain transistor M 3 , whereby output terminal  510  of amplifier  147 C is formed by the source terminal of transistor M 3 . A reset transistor  508  is provided that includes a source terminal connected to floating diffusion  144 C, a gate terminal controlled by a reset clock signal RG, and a drain terminal connected to a reset voltage RD. A typical operation (integration and readout) cycle begins by resetting floating diffusion  144 C to voltage RD by way of toggling reset transistor  508 , waiting a predetermined integration period, then sampling output voltage at output terminal  510 . During the integration period, the voltage level at output terminal  510  changes (becomes more negative) by an amount proportional to the image charge funneled to floating diffusion  144 C. During the readout period, an ADC (not shown) measures the analog voltage level and converts it to a digital number for further signal processing. The ADC may be located on chip or off chip. 
     Sensor  110 C is fabricated using techniques similar to those shown and described in related U.S. Published Patent Application No. 2017-0295334-A1, which is incorporated herein by reference in its entirety. 
       FIG. 6  illustrates a partial multi-column-per-channel CCD image sensor  110 D according to another exemplary preferred embodiment of the present invention. Similar to sensor  110 C (described above), sensor  110 D utilizes fork-shaped buried diffusions  602 - 1 ,  602 - 2  and  602 - 3  to facilitate the transfer of image charges from pixels (not shown) disposed in associated columns  112 D- 11  to  112 D- 33 , where each associated group of columns share a single sense node  144 D formed in the manner described above (e.g., columns  112 D- 11 ,  112 D- 12  and  112 D- 13  share sense node  144 D- 1 ). Similar to the previous embodiment, sensor  110 D includes a row  123 D of buffer cells controlled by a polycrystalline silicon buffer cell structure  603 , three rows  133 D- 1 ,  133 D- 2  and  133 D- 3  of transfer gates formed by polycrystalline silicon transfer gate structures (described below), tapered polycrystalline silicon summing gate structures  605 - 1  to  605 - 3 . Image sensor  110 D operates substantially as described above with reference to sensor  110 C. 
     Sensor  110 D differs from sensor  110 C in that the three rows of transfer gates utilized by sensor  110 D are implemented using integral step-shaped composite polycrystalline silicon structures. As indicated in upper portion of  FIG. 6 , one such step-shaped composite polycrystalline silicon structure  604 - 11  includes a first (upper) horizontal step portion that forms first-row (first) transfer gate structure  604 - 111 , a second (middle) horizontal portion that forms second row (fifth) transfer gate structure  604 - 132 , a third (lower) horizontal portion that forms third row (third) transistor gate structure  604 - 123 , a diagonal (first) polycrystalline silicon conductive linking structure  632 - 11  that integrally connects transfer gate structures  604 - 111  and  604 - 132 , and a second diagonal polycrystalline silicon conductive linking structure  632 - 12  that integrally connects transfer gate structures  604 - 123  and  604 - 132 . Additional step-shaped composite polycrystalline silicon structures are indicated in dashed lines in order to more clearly depict the features of transfer gate structure  604 - 11 , but are understood to be essentially identical in structure. Similar to sensor  110 C, the step-shaped composite polycrystalline silicon structures provide effective coupling between associated first-, second- and third-row transfer gates by way of applying transfer control signals CLK 1 , CLK 2  and CLK 3  to step-shaped composite polycrystalline silicon structures in an alternating pattern. Specifically, associated transfer gate structures  604 - 111 ,  604 - 132  and  604 - 123  are coupled by polycrystalline silicon conductive linking structures  632 - 11  and  632 - 12  such that a first control signal CLK 1  applied to transfer gate structure  604 - 111  is transmitted by way of conductive linking structure  632 - 11  to transfer gate structure  604 - 132 , and from transfer gate structure  605 - 132  to transfer gate structure  604 - 123  by way of conductive linking structure  632 - 12 . Polycrystalline silicon structures  604 - 01  and  604 - 12  are disposed on opposite sides of polycrystalline silicon structure  604 - 11 , and therefore are connected to receive control signals CLK 2  and CLK 3 , respectively, thereby establishing an effective coupling between associated transfer gate structures. 
       FIG. 7  illustrates an exemplary layout for metal interconnects of an on-chip amplifier in which sensor outputs are optimized with equalized response and minimized crosstalk. Although various types of amplifiers could be used in CCD image sensors to convert image charge to voltage and drive external load at the output circuit of each channel, for illustrative purposes an amplifier comprising two stages of source followers is shown. In a preferred embodiment, one block of sensor outputs  701  comprises four channels of two-stage source follower amplifiers, whereby the first stage  702  is not shown in  FIG. 7  for brevity (first stage  702  is located close to the floating diffusion as described above). Metal interconnects  703 - 1 ,  703 - 2 ,  703 - 3 , and  703 - 4  connect the output terminals of the first stages  702 - 1 ,  702 - 2 ,  702 - 3 , and  702 - 4  to the corresponding gate terminals of second stage transistors M 3 - 1 , M 3 - 2 , M 3 - 3 , and M 3 - 4 , respectively. The source terminals of the second stage transistors are connected to metal pads OS, namely, M 3 - 1  to OS 1 , M 3 - 2  to OS 2 , M 3 - 3  to OS 3 , and M 3 - 4  to OS 4 . In one embodiment, the CCD image sensor is flip-chip bonded to a second semiconductor (e.g., silicon) substrate with one or more ADCs and other signal processing circuits. An ADC reads a sensor output signal at a metal pad through a solder ball. 
     For each two-stage amplifier, the first stage transistors are kept small to minimize the load on the floating diffusion. This results in a low transconductance and low driving capability of first stage  702 . For that reason, the second stage comprises a larger transistor M 3  to drive an external circuit which may have an input capacitance as large as several pico-farads. As most heat dissipation happens in the second stage, it is important to spread out the large transistors M 3 - 1 , M 3 - 2 , M 3 - 3 , and M 3 - 4 . Furthermore, in a preferred embodiment, metal pads OS 1 , OS 2 , OS 3 , and OS 4  with a diameter of about 50 μm to 100 μm are used to provide good mechanical strength for flip-chip bonding. As the lateral width of a typical CCD pixel in a preferred embodiment is between about 6 μm and about 25 μm, four channels of sensor outputs can be grouped in block  701  in order to accommodate large transistors and metal pads. Depending on the pixel size, the output transistor size and the metal pad size, fewer or more channels could be grouped in one block of sensor outputs. However, the number of channels in one block should be as few as practical in order to keep the metal interconnects short enough for high bandwidth operation, while maintaining a high transistor and metal pad density. In preferred embodiments, the number of output channels in one block is between two and eight. 
     In one embodiment, transistors M 3 - 1 , M 3 - 2 , M 3 - 3 , and M 3 - 4  are placed close to metal pads OS 1 , OS 2 , OS 3 , and OS 4 , respectively. Metal interconnects  703 - 1 ,  703 - 2 ,  703 - 3 , and  703 - 4  between the first and second stages of the amplifiers have different lengths to spread out transistors M 3 - 1 , M 3 - 2 , M 3 - 3 , and M 3 - 4  within the block. For the channel driving the metal pad OS 1 , which is closest to the first stage of the amplifier, metal interconnect  703 - 1  is the shortest and would add a minimal load to the first stage  702 - 1  in the absence of metal piece  704 - 1 . For the channel driving the farthest metal pad OS 4 , metal interconnect  703 - 4  is the longest, and its capacitance becomes the dominant contributor to the total load on the first stage  702 - 4 . Metal pieces  704 - 1 ,  704 - 2 ,  704 - 3 , and  704 - 4  with successively smaller areas are added to metal interconnects  703 - 1 ,  703 - 2 ,  703 - 3 , and  703 - 4  respectively to balance interconnect capacitances between different channels. With equalized total load capacitance across all the four channels, the sensor outputs feature uniform channel response and minimized crosstalk. Note that, in one embodiment,  704 - 4  may be omitted since the associated interconnect  703 - 4  has the largest capacitance. Note also that, although the areas of the traces  703 - 1 ,  703 - 2  etc. are usually the biggest factors determining the bandwidths of the outputs, other factors including the doping of the silicon beneath traces  703 - 1 ,  703 - 2  etc., the resistance of any polysilicon interconnects, and the transconductances of transistors such as M 3  shown in  FIG. 5  may result in different outputs having different bandwidths in absence of metal pieces  704 - 1 ,  704 - 2  etc. The areas of metal pieces  704 - 1 ,  704 - 2  etc. may be chosen so as to compensate for these and other factors. In an alternative embodiment, the second stage transistors may be placed close to the first stage transistors with different length traces connecting those transistors to the metal pads such as OS 1 , OS 2 , OS 3  and OS 4 . 
       FIG. 8  illustrates exemplary voltage waveforms and timing configurations of clock signals to drive the on-chip multiple-column-per-channel readout structure in accordance with one embodiment of the present invention. Voltage and time are plotted in arbitrary units. Voltages of different clock signals are not necessarily plotted to the same scale. 
     Although a three-phase CCD array sensor is utilized in the particular embodiment illustrated in  FIG. 8 , the present clock driving scheme can also apply to other CCD area sensors and line sensors. Each pixel of the three-phase CCD sensor comprises three polysilicon gates driven by continuous phase clocks P 1 V, P 2 V, and P 3 V, respectively. The phase clocks are synchronized to a line clock (not shown), which controls charge transfer from a row of pixels to the readout structure. Each of the three clock signals is shifted in phase by 120 degrees relative to the other two clock signals, enabling charge transfer down the column as briefly described in  FIG. 4 . U.S. Pat. No. 7,609,309, entitled “Continuous clocking of TDI sensors”, issued on Oct. 27, 2009 and U.S. Pat. No. 7,952,633, entitled “Apparatus for continuous clocking of TDI sensors”, issued on May 31, 2011 describe additional aspects and details of the continuous clock driving scheme. Both patents are incorporated herein by reference. 
     Referring to the multiple-column-per-channel readout structure depicted in  FIG. 5  and its clock driving scheme illustrated in  FIG. 8 , clock signal VBG drives the row of buffer cells  123 C, clock signals C 1 , C 2  and C 3  refer to transfer clock signals CLK 1 , CLK 2  and CLK 3 , respectively, which drive the three rows of transfer gates T 11  to T 33 , clock signal SG drives the summing gate, clock signal RG drives the gate of reset transistor  508 , and V OUT , which represents measured pixel values at the ADC. These control signals are synchronized to a free-running internal clock ADC-C of an ADC in an off-chip signal processing circuit. During a clock cycle, clock signal VBG increases gradually from low to high and drops sharply after it reaches a peak value. In a conventional CCD, image charges transfer from pixels to a horizontal output register (or to buffer cells similar to  503 ) at a constant rate because clock signals similar to P 1 V, P 2 V, P 3 V, and VB run at a constant frequency. In one embodiment that includes two rows of buffer cells, a second buffer cell clock signal (not shown), approximately 180° out of phase with VBG, drives that second row. In another embodiment with more than two rows of buffer cells, odd-numbered rows (starting with the row of buffer cells adjacent to the last row of pixels) are driven by clock signal VBG, and even-numbered rows are driven by a clock signal approximately 180° out of phase with VBG. An advantage of using an even number of rows of buffer cells is that the two buffer cell clock signals, being approximately 180° out of phase with one another, is that the currents from these clock signals approximately cancel minimizing noise currents flowing in the sensor. In one embodiment of the present invention clock signals C 1 , C 2  and C 3  sequentially move image charge from transfer gates T 13 , T 23  and T 33  (i.e., image charges respectively generated in the pixels of the three columns  112 C- 1 ,  112 C- 2  and  112 C- 3 ) into common summing gate  505 , while clock signal SG transmits the image charge to floating diffusion  144 C at twice the frequency of phase clocks P 1 V, P 2 V, and P 3 V. Clock signal RG resets the voltage of floating diffusion  144 C in preparation for the image charge at the next clock cycle. Clock signal RST (not shown) is generated by a timing generator and is synchronized to ADC-C. After clock signal RG resets the voltage at the floating diffusion, clock signal SIG (not shown) triggers correlated double sampling (CDS) during which the sensor output is sampled and prepared for digitization. 
     In the illustrative example depicted in  FIG. 8 , transfer clock signals C 1 , C 2  and C 3  that drive the transfer gates are shown as rectangular pulses. In preferred embodiments, these clocks are shaped so as to reduce noise while ensuring efficient high-speed signal transfer. Rise and fall times of other clock signals are also controlled so as to ensure efficient charge transfer and to minimize noise. In one embodiment, clocks C 1 , C 2  and C 3  have approximately half sine-wave shapes similar to those illustrated for buffer clock VBG, but at twice the frequency. Since transfer clock signals C 1 , C 2  and C 3  are substantially 120° out of phase with each other, the currents that result from these clocks approximately cancel one another, reducing noise that might degrade the signal-to-noise ratio of the image. 
       FIG. 8  illustrates clock waveforms and timing for reading out each individual pixel of the image sensor as a separate signal. As long as the full-well capacity of the summing and output gates is large enough compared with the signal level, it is also possible to sum pairs of adjacent pixels by transferring the signal under each summing gate to the corresponding output gate and floating diffusion once per line clock rather than twice per line clock. Image rows may be summed together by, for example, transferring two lines into the buffer cells before transferring the signal under buffer cells to the first row of transfer gates. Systems and methods described in U.S. patent application Ser. No. 15/210,056 entitled “Dark-Field Inspection Using a Low-Noise Sensor”, filed on Jul. 14, 2016 by Chuang et al., may be used in combination with the sensor described herein. This patent application is incorporated herein by reference. 
       FIG. 9  is a simplified diagram of an apparatus  900  that can implement features and methodologies described herein. The apparatus includes a CCD image sensor  901  which comprises one of the multiple-column-per-channel CCD sensors disclosed herein, off-chip signal processing circuits  902 , and external storage, processing, and control circuits  903 . CCD sensor  901  detects incident radiation, converts photo-generated electrons to voltage, and outputs the voltage signal to off-chip signal processing circuits  902 . For brevity only function blocks necessary to explain the present invention are depicted in the off-chip signal processing circuits  902 . These include ADC  9021 , digital signal processor  9022 , and clock driver  9023 . ADC  9021  comprises CDS and ADC circuits and digitizes the CCD analog output signals. A digital output of ADC  9021  is sent to digital signal processor  9022  for post-processing and, optionally, data compression. A timing generator  90221  incorporated in digital signal processor  9022  generates clock signals, which are buffered by clock driver  9023  to control CCD sensor  901  and ADC  9021 . For example, clock driver  9023  may provide clock signals P 1 V, P 2 V, P 3 V, VB, C 1 , C 2 , SG, RG, OS, and ADC-C as described above and illustrated in  FIG. 8 . Digital signal processor  9022  interfaces with external storage, processing, and control circuits  903  for further signal processing, control and data transfer, such as clock synchronization. 
     Note that the apparatus depicted in  FIG. 9  may incorporate the waveform generator described in U.S. Pat. No. 9,347,890, entitled “A Low-Noise Sensor and an Inspection System Using a Low-Noise Sensor”, to Brown et al., and/or the apparatus may implement a method described in that application. The &#39;890 patent is incorporated herein by reference. 
     Buffer cells, transfer gates, summing gates, output gates, readout gates, floating diffusion and output amplifiers are well known in CCD image sensors and will not be described in more detail here. The configurations shown in  FIGS. 1, 3A, 3B, 5, 6, and 7  are merely by way of example to explain the operation of the multiple-column-per-channel CCD sensor. Different configurations of the readout structure are possible without departing from the scope of the invention. In one exemplary embodiment one or more transfer gate pairs with one or more buffer cells could be used. In another exemplary embodiment, five or more transfer gates may be connected to one summing gate. In this exemplary embodiment, each column would comprise five transfer gates, and five-phase clocks could be used to sequentially clock the signal from each column into the summing gate. These three-phase clocks would be substantially 72° out of phase with respect to one another. Such a sensor might be described as a five-column parallel CCD sensor, but it would operate in a substantially similar manner to the three-column parallel CCD sensors described herein and is within the scope of the present invention. 
     In another exemplary embodiment a self-aligned floating diffusion with a polysilicon contact connected to on-chip amplifier could be used. In yet another exemplary embodiment, metal interconnects of on-chip amplifier may be optimized to equalize channel response and minimize crosstalk. Details of commonly used semiconductor manufacturing processes that are not directly relevant to the invention are not included in order to avoid complicating the description. 
       FIG. 10  illustrates an exemplary inspection system  1000  configured to inspect a sample  1080 , such as a wafer, reticle, or photomask. Sample  1080  is placed on a stage  1120  to facilitate movement to different regions of sample  1080  underneath the optics. Stage  1120  may comprise an X-Y stage or an R-θ stage. In some embodiments, stage  1120  can adjust the height of sample  1080  during inspection to maintain focus. In other embodiments, an objective lens  1050  can be adjusted to maintain focus. 
     An illumination source  1020  may comprise one or more lasers and/or a broad-band light source. Illumination source  1020  may emit DUV and/or VUV radiation. Optics  1030 , including an objective lens  1050 , directs that radiation towards and focuses it on sample  1080 . Optics  1030  may also comprise mirrors, lenses, polarizers and/or beam splitters (not shown for simplicity). Light reflected or scattered from sample  1080  is collected, directed, and focused by optics  1030  onto a sensor  1060 , which is within a detector assembly  1040 . 
     Detector assembly  1040  includes at least one of the sensors described herein. In one embodiment, the output of sensor  1060  is provided to a computing system  1140 , which analyzes the output. Computing system  1140  is configured by program instructions  1180 , which can be stored on a carrier medium  1160 . In one embodiment computing system  1140  controls the inspection system  1000  and sensor  1060  to inspect a structure on sample  1080  and read out the sensor in accordance with a method disclosed herein. 
     In one embodiment, illumination source  1020  may be a continuous source, such as an arc lamp, a laser-pumped plasma light source, or a CW laser. In another embodiment, illumination source  1020  may be a pulsed source, such as a mode-locked laser, a Q-switched laser, or a plasma light source pumped by a Q-switched laser. In one embodiment of inspection system  1000  incorporating a Q-switched laser, the sensor or sensors within detector assembly  1040  are synchronized with the laser pulses. 
     One embodiment of inspection system  1000  illuminates a line on sample  1080 , and collects scattered and/or reflected light in one or more dark-field and/or bright-field collection channels. In this embodiment, detector assembly  1040  may include a line sensor or an electron-bombarded line sensor. Another embodiment of inspection system  1000  illuminates an area on sample  1080 , and collects scattered and/or reflected light in one or more dark-field and/or bright-field collection channels. In this embodiment, detector assembly  1040  may include an array sensor or an electron-bombarded array sensor. 
     Additional details of various embodiments of inspection system  1000  are described in U.S. Pat. No. 9,279,774, entitled “Wafer inspection system”, issued on Mar. 8, 2016 to Romanovsky et al., U.S. Pat. No. 7,957,066, entitled “Split field inspection system using small catadioptric objectives”, to Armstrong et al., U.S. Pat. No. 7,345,825, entitled “Beam delivery system for laser dark-field illumination in a catadioptric optical system”, to Chuang et al., U.S. Pat. No. 5,999,310, entitled “Ultra-broadband UV microscope imaging system with wide range zoom capability”, issued on Dec. 7, 1999, U.S. Pat. No. 7,515,649, entitled “Surface inspection system using laser line illumination with two dimensional imaging”, issued on Apr. 28, 2009. All of these patents are incorporated herein by reference. 
       FIGS. 11A and 11B  illustrate aspects of dark-field inspection systems that incorporate sensors and/or methods described herein in accordance with other exemplary embodiments of the present invention. In  FIG. 11A , illumination optics  201  comprises a laser system  220 , which generates light  202  that is focused by a mirror or lens  203  into a line  205  on surface of a wafer or photomask (sample)  211  being inspected. The sample being inspected may be patterned or unpatterned. Collection optics  210  directs light scattered from line  205  to a sensor  215  using lenses and/or mirrors  212  and  213 . An optical axis  214  of collection optics  210  is not in the illumination plane of line  205 . In some embodiments, optical axis  214  is approximately perpendicular to line  205 . Sensor  215  comprises an array sensor, such as a linear array sensor. Sensor  215  may comprise a sensor as described herein, and/or one of the methods described herein may be used to read out the sensor. 
       FIG. 11B  illustrates one embodiment of multiple dark-field collection systems  231 ,  232  and  233 , each collection system substantially similar to collection optics  210  of  FIG. 11A . Collection systems  231 ,  232  and  233  may be used in combination with illumination optics substantially similar to illumination optics  201  of  FIG. 11A . Each collection system  231 ,  232  and  233  incorporates one, or more, of the sensors described herein. Sample  211  is supported on stage  221 , which moves the areas to be inspected underneath the optics. Stage  221  may comprise an X-Y stage or an R-θ stage, which preferably moves substantially continuously during the inspection to inspect large areas of the sample with minimal dead time. 
     More details of inspection systems in accordance with the embodiments illustrated in  FIGS. 11A and 11B  are described in U.S. patent application Ser. No. 15/153,542 entitled “Sensor With Electrically Controllable Aperture For Inspection And Metrology Systems”, filed May 12, 2016, U.S. Pat. No. 7,515,649, entitled “Surface inspection system using laser line illumination with two dimensional imaging”, issued on Apr. 28, 2009, and U.S. Pat. No. 6,608,676, entitled “System for detecting anomalies and/or features of a surface”, issued on Aug. 19, 2003. All of these patents and patent applications are incorporated herein by reference. 
       FIG. 12  illustrates an inspection system  300  configured to detect particles or defects on a sample, such as an unpatterned wafer, using both normal and oblique illumination beams. In this configuration, a laser system  330  provides a laser beam  301 . A lens  302  focuses beam  301  through a spatial filter  303 . Lens  304  collimates the beam and conveys it to a polarizing beam splitter  305 . Beam splitter  305  passes a first polarized component to the normal illumination channel and a second polarized component to the oblique illumination channel, where the first and second components are orthogonal. In a normal illumination channel  306 , the first polarized component is focused by optics  307  and reflected by a mirror  308  towards a surface of a sample  309 . The radiation scattered by sample  309  (such as a wafer or photomask) is collected and focused by a paraboloidal mirror  310  to a sensor  311 . 
     In an oblique illumination channel  312 , the second polarized component is reflected by a beam splitter  305  to a mirror  313  which reflects such beam through a half-wave plate  314  and focused by optics  315  to sample  309 . Radiation originating from the oblique illumination beam in oblique channel  312  and scattered by sample  309  is collected by paraboloidal mirror  310  and focused to sensor  311 . Sensor  311  and the illuminated area (from the normal and oblique illumination channels on sample  309 ) are preferably at the foci of paraboloidal mirror  310 . 
     Paraboloidal mirror  310  collimates the scattered radiation from sample  309  into a collimated beam  316 . Collimated beam  316  is then focused by an objective  317  and through an analyzer  318  to sensor  311 . Note that curved mirrored surfaces having shapes other than paraboloidal shapes may also be used. An instrument  320  can provide relative motion between the beams and sample  309  so that spots are scanned across the surface of sample  309 . Sensor  311  may comprise one or more of the sensors described herein. U.S. Pat. No. 6,201,601, entitled “Sample inspection system”, issued to Vaez-Iravani et al. on Mar. 13, 2001, U.S. Pat. No. 9,279,774, entitled “Wafer Inspection”, issued to Romanovsky et al. on Mar. 8, 2016, and U.S. Published Application 2016-0097727, entitled “TDI Sensor in a Darkfield System” by Vazhaeparambil et al. and published on Apr. 7, 2016, describe additional aspects and details of inspection system  300 . These documents are incorporated herein by reference. 
     The various embodiments of the structures and methods of this invention that are described above are illustrative only of the principles of this invention and are not intended to limit the scope of the invention to the particular embodiments described. For example, one or more CCD array sensors, including three-phase sensors or other multi-phase sensors, and/or CCD line sensors may be utilized in an inspection system to inspect a sample. 
     The image sensors described herein may be incorporated into a module or system such as one described in U.S. Pat. No. 8,754,972, entitled “Integrated multi-channel analog front end and digitizer for high speed imaging applications”, issued on Jun. 17, 2014 to Brown et al. This patent is incorporated herein by reference. 
     It is also to be understood that where sensors or methods are described as detecting light that these descriptions may also apply to detecting electromagnetic radiation of different wavelengths including infra-red, visible light, ultra-violet, extreme UV and X-rays, and to detecting charged particles such as electrons. 
     Thus, the invention is limited only by the following claims and their equivalents.