Patent Publication Number: US-2010123509-A1

Title: Pad circuit for the programming and i/o operations

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a pad circuit, and more particularly, to a pad circuit for the programming and I/O operations. 
     2. Description of the Prior Art 
     A typical chip is equipped with conductive pads to receive external power potentials and to exchange data with other external circuits/chips. For example, the chip is equipped with power pads and ground pads to transmit the positive or negative voltage and the ground voltage to the power supplies. Similarly, the chip is also equipped with signal input/output (I/O) pads to receive input signals and to transmit output signals. The chip communicates with other circuit through the conductive pads. However, an integrated circuit (IC) chip may be subjected to an Electrostatic Discharge (ESD) event both in the manufacturing process and in the system application. The ESD signal may be transmitted into the chip through the pads of the chip, which damages the internal circuit of the chip. Thus, the pad circuit of the chip is designed for buffering signals as well as protecting ESD events. 
     Please refer to  FIG. 1 .  FIG. 1  is a schematic diagram of a pad circuit  1   0  according to the prior art. The pad circuit  10  is used for the programming operation. In addition, the pad circuit  10  has an ESD protection circuit to discharge the ESD induced current. In the pad circuit  10 , the resistor R and the capacitor C are coupled in series to the pad  11  and the power/ground terminal VSS to form a resistor-capacitor (RC) network. The PMOS transistor P 1  and NMOS transistor N 2  are coupled to the pad  11  and the power/ground terminal VSS as an inverter. The gates of the two transistors P 1  and N 2  as the input of the inverter are controlled by the voltage at the node A 2  of the RC network while the drains of the two transistors P 1  and N 2  as the output of the inverter control the trigger of the NMOS transistor N 1  at the node A 1 . When the NMOS transistor N 1  between the pad  11  and the power/ground terminal VSS is triggered by a high voltage, the NMOS transistor N 1  opens a conducting current path of low impendence between the pad  11  and the power/ground terminal VSS. Thus, the ESD induced current can be discharged. 
     When the pad circuit  10  is used for receiving voltage signals, the NMOS transistor N 1  should be turned off to prevent the leakage current. For example, when the pad circuit  10  is used for the programming operation, a programming voltage 7.5V is applied to the pad  11 . Thus, a high voltage level is generated at the node A 2  and a low voltage level is generated at the node A 1 . The NMOS transistor N 1  is turned off, and the transmission gate  16  is turned on. The programming voltage is transmitted to the node A 4 . Unfortunately, the pad circuit  10  cannot be used for the I/O operation. Referring to  FIG. 1  again, when the pad  11  receives I/O voltages 0/3.3 Volts, the NMOS transistor N 1  will induce a large leakage current at I/O transient states. For example, when the I/O voltage changes from 0 Volts to 3.3 Volts, the PMOS transistor P 1  is turned on so as to generate a high voltage level at the node A 1 . Thus, the NMOS transistor N 1  is turned on and the leakage current is generated. 
     SUMMARY OF THE INVENTION 
     According to an embodiment of the present invention, a pad circuit for the programming and I/O operations comprises a pad, a gate driving circuit, a voltage selection circuit, and an ESD detection/avoiding circuit. The gate driving circuit is coupled between the pad and a first power/ground terminal, for discharging an ESD induced current. The voltage selection circuit is coupled to the pad and a second power/ground terminal, for outputting a voltage of the pad or a voltage of the second power/ground terminal to the gate driving circuit. The ESD detection/avoiding circuit is coupled to the pad, for isolating an ESD induced voltage. 
     These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a schematic diagram of a pad circuit according to the prior art. 
         FIG. 2  is a schematic diagram of a first embodiment of a pad circuit according to the present invention. 
         FIG. 3  is a truth table for the voltage selection circuit. 
         FIG. 4A ,  FIG. 4B , and  FIG. 4C  are schematic diagrams of a second embodiment of a pad circuit according to the present invention. 
         FIG. 5  is a schematic diagram of a third embodiment of a pad circuit according to the present invention. 
     
    
    
     DETAILED DESCRIPTION 
     Please refer to  FIG. 2 .  FIG. 2  is a schematic diagram of a first embodiment of a pad circuit  20  according to the present invention. The pad circuit  20  includes a pad  21 , a gate driving circuit  22 , a voltage selection circuit  23 , and an ESD detection/avoiding circuit  24 . The gate driving circuit  22  is used to discharge the electrostatic discharge (ESD) induced current. The gate driving circuit  22  includes an NMOS transistor N 1 , a PMOS transistor P 1 , an NMOS transistor N 2 , a resistor R 1  and a capacitor C 1 . The gate of the NMOS transistor N 1  is coupled to the node A 1 . The source of the NMOS transistor N 1  is coupled to the first power/ground terminal VSS. The drain of the NMOS transistor N 1  is coupled to the pad  21 . The gate of the PMOS transistor P 1  is coupled to the node A 2 . The source of the PMOS transistor P 1  is coupled to the pad  21 . The drain of the PMOS transistor P 1  is coupled to the node A 1 . The gate of the NMOS transistor N 2  is coupled to the node A 2 . The source of the NMOS transistor N 2  is coupled to the first power/ground terminal VSS. The drain of the NMOS transistor N 2  is coupled to the node A 1 . The first end of the resistor R 1  is coupled to the node A 3 . The second end of the resistor R 1  is coupled to node A 2 . The first end of the capacitor C 1  is coupled to the node A 2 . The second end of the capacitor C 1  is coupled to the first power/ground terminal VSS. The ESD detection/avoiding circuit  24  is used to isolate the ESD induced voltage. The ESD detection/avoiding circuit  24  includes a PMOS transistor P 2 . The gate of the PMOS transistor P 2  is coupled to the node A 1 . The source of the PMOS transistor P 2  is coupled to the pad  21 . The drain of the PMOS transistor P 2  is coupled to the node A 4 . 
     The voltage selection circuit  23  selects a high voltage from the second power/ground terminal and the pad  21  and outputs the selected voltage to the gate driving circuit  22 , so that the pad circuit  20  can be used for the programming and I/O operations. The voltage selection circuit  23  includes a PMOS transistor P 3  and a PMOS transistor P 4 . The source of the PMOS transistor P 3  is coupled to the second power/ground terminal VDD. The gate of the PMOS transistor P 3  is coupled to the pad  21 . The drain and the body of the PMOS transistor P 3  are coupled to the node A 3 . The source of the PMOS transistor P 4  is coupled to the pad  21 . The gate of the PMOS transistor P 4  is coupled to the second power/ground terminal VDD. The drain and the body of the PMOS transistor P 4  are coupled to the node A 3 . By switching the PMOS transistors P 3  and P 4 , a higher voltage is selected from the voltage of the second power/ground terminal VDD and the voltage of the pad  21  to the node A 3 . 
     Please refer to  FIG. 3 .  FIG. 3  is a truth table for the voltage selection circuit  23 . V_PAD is the voltage of the pad  21 . VDD is the power supply that provides 3.3V. V_A 3  is the voltage of the node A 3 . When the pad circuit  20  is used for the programming operation, the pad  21  receives a programming voltage, for example, 7.5 Volts. Thus, the PMOS transistor P 3  is turned off, and the PMOS transistor P 4  is turned on. The voltage of the node A 3  is 7.5V. The node A 2  is at a high voltage level and the node A 1  is at a low voltage level. Thus, the NMOS transistor N 1  is turned off and the PMOS transistor P 2  is turned on. The programming voltage is transmitted to the node A 4 . For the I/O operation, the pad  21  receives an I/O voltage, for example, 3.3 Volts or 0 Volt. The voltage selection circuit  23  can select the high voltage from the second power/ground terminal VDD and the pad  21 . When the pad  21  receives the voltage 3.3 Volts or 0 Volt, the voltage of the node A 3  is always 3.3 Volts. The node A 2  is at the high voltage level and the node A 1  is at the low voltage level. Thus, the NMOS transistor N 1  is turned off and the PMOS transistor P 2  is turned on. The I/O voltage is transmitted to the node A 4 . However, the I/O voltage can be transmitted from the pad  21  to an internal circuit directly. 
     In addition, the pad circuit  20  can protect the pad  21  from ESD events referenced to the first power/ground terminal VSS. In response to an ESD event that induces a rapid positive voltage increased on the pad  21 , the capacitor C 1  initially holds the node A 2  well below the pad  21 . The gate driving circuit  22  drives the gate of the NMOS transistor N 1  to turn on the NMOS transistor N 1 . Once turned on, the NMOS transistor N 1  acts as a low resistance between the pad  21  and the first power/ground terminal VSS. The NMOS transistor N 1  will remain conductive for a period of time which is determined by the RC time constant of the gate driving circuit  22 . As a result, this RC time constant should be set long enough to exceed the maximum expected duration of an ESD event. 
     Please refer to  FIG. 4A ,  FIG. 4B , and  FIG. 4C .  FIG. 4A ,  FIG. 4B  and  FIG. 4C  are schematic diagrams of a second embodiment of a pad circuit  30  according to the present invention. In this embodiment, the PMOS transistor P 1  is replaced with a cascode circuit  331  or  332  to prevent the leakage issue when the voltages of the first power/ground terminal VDD and the pad  21  increase at the same time. In addition, a diode D 1  can be used to prevent the leakage issue. In comparison with the first embodiment, the cascode circuits  331  and  332  further include a PMOS transistor P 5 . As shown in  FIG. 4A , the gate of the PMOS transistor P 5  is coupled to the gate of the PMOS transistor P 1 . The source of the PMOS transistor P 5  is coupled to the pad  21 . The drain of the PMOS transistor P 5  is coupled to the source of the PMOS transistor P 1 . As shown in  FIG. 4B , the gate of the PMOS transistor P 5  is coupled to the source of the PMOS transistor P 1 . The source of the PMOS transistor P 5  is coupled to the pad  21 . The drain of the PMOS transistor P 5  is coupled to the source of the PMOS transistor P 1 . As shown in  FIG. 4C , the diode D 1  is coupled between the source of the PMOS transistor P 1  and the pad  21 . 
     Please refer to  FIG.5 .  FIG. 5  is a schematic diagram of a third embodiment of a pad circuit  40  according to the present invention. In this embodiment, an ESD detection/avoiding circuit  44  uses a transmission gate to improve the electricity. In comparison with the first embodiment, the ESD detection/avoiding circuit  44  further includes an NMOS transistor N 4 . The gate of the NMOS transistor N 4  is coupled to the node A 2 . The source of the NMOS transistor N 4  is coupled to the pad  21 . The drain of the NMOS transistor N 4  is coupled to the node A 4 . 
     In conclusion, the pad circuit according to the present invention includes a pad, a gate driving circuit, a voltage selection circuit, and an ESD detection/avoiding circuit. The gate driving circuit is used to discharge the ESD induced current. The ESD detection/avoiding circuit is used to isolate the ESD induced voltage. The voltage selection circuit selects a higher voltage from a power/ground terminal and the pad and outputs it to the gate driving circuit, so that the pad circuit can be used for the programming and I/O operations. 
     Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention.