Patent Publication Number: US-2006017910-A1

Title: Composite printing

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS  
      This application is a divisional application of and claims priority to U.S. application Ser. No. 10/688,306, filed on Oct. 17, 2003, the contents of which are incorporated herein by reference. 
    
    
     BACKGROUND  
      This disclosure relates to the printing of substrates.  
      Various lithographic techniques can be used to print patterns such as those that define integrated circuits in microelectronic devices. For example, optical lithography, e-beam lithography, UV and EUV lithography, x-ray lithography and imprint printing techniques can all be used to form micron- and submicron-sized features. 
    
    
     DESCRIPTION OF DRAWINGS  
       FIG. 1  is a top view of a wafer.  
       FIG. 2  is a sectional view of a portion of a layout piece on a wafer during processing.  
       FIG. 3  is a top view of a layout piece after exposure and development to form a two-dimensional array of features.  
       FIG. 4  is a sectional view of the layout piece of  FIG. 3 .  
       FIGS. 5, 6 , and  7  are sectional views along the same plane as  FIG. 4  after additional processing.  
       FIG. 8  shows a top view of a layout piece after exposure and development to form a pattern.  
       FIG. 9  shows a sectional view of the layout piece of  FIG. 8 .  
       FIGS. 10 and 11  are sectional views along the same plane as  FIG. 9  after additional processing.  
       FIG. 12  shows a top view of a layout piece after removal of a sacrificial layer.  
       FIG. 13  shows a sectional view of the layout piece of  FIG. 12 .  
       FIG. 14  shows a composite optical lithography system.  
       FIG. 15  shows an example patterning system in the composite optical lithography system of  FIG. 14 . 
    
    
      Like reference symbols in the various drawings indicate like elements.  
     DETAILED DESCRIPTION  
       FIG. 1  shows a top view of a wafer  100 . Wafer  100  is a semiconductor wafer being processed to form at least one integrated circuit device such as a microprocessor, a chipset device, or a memory device. For example, wafer  100  can be used to form a collection of SRAM memory devices. Wafer  100  can include silicon, gallium arsenide, or indium phosphide. Wafer  100  includes an array of die portions  105 . Wafer  100  can be diced or otherwise processed to form a collection of dice that can be packaged to form individual integrated circuit devices. Each die portion  105  includes one or more layout pieces  110 . A layout piece  110  is a section of a die portion  105  that includes a pattern. The pattern defined in a layout piece  110  generally contributes to the function of integrated circuit devices formed from die portions  105 .  
       FIG. 2  is a sectional view of a portion of layout piece  110  on wafer  100 . At the processing stage illustrated in  FIG. 2 , layout piece  110  includes a substrate  205 , a pattern layer  210 , a sacrificial layer  215 , and a printing layer  220 . Substrate  205  can be the base wafer or another layer formed during previous processing. Pattern layer  210  is the portion of layout piece  110  that is to be patterned. Pattern layer  210  can be patterned to form all or a portion of a microelectronic device. Pattern layer  210  can be, e.g., an electrical insulator such as silicon dioxide or nitride, a semiconducting material such as p- or n-doped silicon, or a conducting layer such as copper or aluminum. Sacrificial layer  215  is a temporary layer that can be selectively removed from pattern layer  210 . Sacrificial layer  215  can be an interlayer dielectric (ILD) such as a silicon oxide or nitride. Printing layer  220  is a material that is sensitive to one or more techniques for printing patterns. For example, printing layer  220  can be a positive or negative photoresist. The following description assumes printing layer  220  to be a positive photoresist.  
      Resist layer  220  can be exposed and developed to form a pattern.  FIG. 3  is a top view and  FIG. 4  is a sectional view of layout piece  110  after exposure and development to form a two-dimensional array  300  of repeating features  305 . Features  305  repeat in array  300  in that, excepting manufacturing defects and other irregularities in individual features  305 , array  300  includes a repetitive order or arrangement of individual features  305 . Array  300  can be rectangular or square with a length  310  and a width  315  that occupies all or a portion of layout piece  110 . Features  305  in array  300  have a pitch  320 . The pitch of features is the smallest spatial periodicity of the features. For example, contact pitch  320  is the sum of the width  325  of a contact  305  and the shortest distance  330  to the next nearest contact  305 . Only a single pair of contacts  305  need be at pitch  320 . Thus, the separation distance and width of contacts  305  can vary (e.g., in the horizontal and vertical directions) and array  300  can still have pitch  320 .  
      Features  305  can be formed using any of a number of different lithographic techniques such as e-beam lithography, interference lithography, and optical lithography using phase-shifting masks and optical proximity correction techniques. These lithographic techniques can involve the exposure of wafer  100  using an interference pattern. For example, features  305  can be formed using interference lithography by exposing resist  220  using two orthogonal sets of interfering laser beams with a wavelength λ 1  to form the array of features with pitch  320  approaching ½λ 1 . The orthogonal sets can be generated by splitting a single source four ways using a pyramidal prism and interfering the reflections from two orthogonal pairs of opposing pairs of mirrors. The orthogonal pairs can illuminate a substrate at different angles of illumination or the orthogonal pairs can illuminate a substrate at the same angle of illumination. Illuminating at the same angle can impart the substrate with the same pitch in both, orthogonal, directions. Alternatively, the orthogonal sets can be generated by double exposing resist  220  after wafer  100  is subject to a 90° rotation in a traditional interferometric lithography system.  
      Features  305  can display features characteristic of the lithographic technique used to form features  305 . For example, when features  305  are formed using interference lithography, features  305  can be formed with a definition characteristic of interference lithography and a pitch approaching ½λ 1  with minimal feature distortion of the type that arises due to imperfections in projection printing systems and techniques. For example, features  305  can be formed without imperfections that arise due to the use of a mask, lenses, projection optics, and/or the backscattering of electrons. Features  305  can also show the influence of the relatively large depth of focus provided by interferometric lithography techniques. For example, the relatively large depth of focus can provide precise control of the dimensional characteristics of features, especially relative to the control provided by optical systems in which high numerical apertures limit both the depth of field and the ability to print real world substrates that are not ideally flat.  
       FIGS. 5, 6 , and  7  are sectional views along the same plane as  FIG. 4  after additional processing. In particular,  FIG. 5  shows layout piece  110  after an etch has defined cavities  505  in sacrificial layer  215 . For example, cavities  505  can be defined using a dry plasma etch. Cavities  505  can inherit the character of features  305  that are characteristic of the lithographic technique used to form features  305 . For example, when features  305  are exposed using interference lithography, cavities  505  can inherit the definition characteristic of interference lithography where minimal pitch approaches ½λ 1  with minimal feature distortion of the type that arises due to imperfections in projection printing systems and techniques. Cavities  505  can be generally cylindrical with their axes oriented perpendicular to the plane of wafer  100 . Cavities  505  can be defined to have substantially the same pitch  320  as features  305 . Cavities  505  can have diameters smaller, larger, or substantially the same as the diameters of features  305 , depending on the etch process selected to define cavities  505 .  
       FIG. 6  shows layout piece  110  after resist  220  has been stripped.  FIG. 7  shows layout piece  110  after a new resist layer  705  has been formed above sacrificial layer  215 . Resist layer  705  can either cap or fill cavities  505  of sacrificial layer  215 . Resist layer  705  can be formed, e.g., by spin coating photoresist on wafer  100 .  
       FIG. 8  shows a top view and  FIG. 9  shows a sectional view of layout piece  110  after resist layer  705  has be exposed and developed to form a  FIG. 805 .  FIG. 805  can be arbitrarily shaped in that  FIG. 805  need not include a repetitive order or arrangement.  FIG. 805  is aligned with the two-dimensional array of cavities  505  to either expose (for example, at  810 ) or cover (for example, at  815 ) individual cavities  505 .  
       FIG. 805  can be formed with a length  820  and a width  825  that occupies all or a portion of layout piece  110 .  FIG. 805  can include elements with a pitch  830 . Pattern element pitch  830  is the sum of the width  835  of an element  840  and the shortest distance  845  to the next nearest element  850 . Only a single pair of elements in  FIG. 805  need be at pitch  830 . Thus, the separation distance and width of elements can vary, and  FIG. 805  can still have pitch  830 . Pitch  830  can be two or more times as large as contact pitch  320 .  
      Since pattern pitch  830  can be relatively larger than contact pitch  320 ,  FIG. 805  can be formed using lithographic systems and techniques that have a lower resolution than the systems and techniques used to form features  305 . For example, if features  305  are formed using an interferometric lithography system with a wavelength λ 1 , then  FIG. 805  can be formed using an optical lithography system with a wavelength larger than λ 1 . As another example,  FIG. 805  can be formed using a traditional binary optical lithography system, or other lithographic systems such as imprint and e-beam lithographic systems capable of achieving the lower resolution.  
      The exposure or shielding of cavities  505  by  FIG. 805  can be used to introduce irregularity into the repeating array of cavities  505  after hardening of resist  705 . In other words, the arbitrary shape of  FIG. 805  can be used to stop the periodic reoccurrence of features in layout piece  110 .  
       FIGS. 10 and 11  are sectional views along the same plane as  FIG. 8  after additional processing. In particular,  FIG. 10  shows layout piece  110  after an etch has defined cavities  1005  in pattern layer  210 . For example, cavities  1005  can be defined using a dry plasma etch. Cavities  1005  can inherit, by way of cavities  505 , the character of features  305  that are characteristic of the lithographic technique used to form features  305 . For example, when features  305  are exposed using interference lithography, cavities  1005  can inherit, by way of cavities  505 , the definition characteristic of interference lithography with minimal feature distortion of the type that arises due to imperfections in projection printing systems and techniques at a pitch approaching λ 1 . Cavities  1005  can be generally cylindrical, with their axes oriented perpendicular to the plane of wafer  100 . Cavities  1005  can be defined to have substantially the same pitch  320  as features  305 . Cavities  1005  can have diameters smaller, larger, or substantially the same as the diameters of cavities  505 .  
       FIG. 11  shows layout piece  110  after resist  705  has been stripped to expose previously covered cavities  505 . FIGS.  12  shows a top view and  FIG. 13  shows a sectional view of layout piece  110  after sacrificial layer  215  has been removed. Sacrificial layer  215  can be removed by chemical mechanical polishing (CMP) or by etching. After removal of sacrificial layer  215  and the exposure of cavities  1005 , pattern layer  210  in layout piece  110  includes a collection of pattern features  1205 . Pattern features  1205  can be used in a functional design layout of a microelectronic device. Pattern features  1205  can have pitch  320  that is limited by the pitch available from the lithographic technique used to form contacts  305 . Moreover, depending upon the geometry of resist  FIG. 805 , pattern features  1205  can also have an arbitrary arrangement in pattern layer  210  since, after irregularity is introduced into repeating array  300 , the impact of at least some of the small pitch features  305  upon wafer  100  has been eliminated.  
      Such composite patterning can prove advantageous. For example, a single layout piece can be patterned with features using a higher resolution system or technique and the functional impact of those features can be modified or even eliminated using a lower resolution system or technique. For example, older, typically lower resolution, equipment can be used to modify the impact of higher resolution features, providing increased lifespans to the older equipment. Patterning cost can be decreased by devoting high resolution systems to the production of high resolution features while using less expensive, lower resolution systems for the modification of the impact of those high resolution features. For example, high resolution but relatively inexpensive interferometric systems can be combined with relatively inexpensive low resolution systems to produce high quality, high resolution patterns without large capital investments. Since the arrangement of patterns produced using interferometric systems can be changed using lower resolution systems, the applicability of interferometric systems can be increased. In particular, interferometric systems can be used to form substantially arbitrary arrangements of features that are not constrained by the geometries and arrangements of interference patterns.  
       FIG. 14  shows a composite optical lithography system  1400 . System  1400  includes an environmental enclosure  1405 . Enclosure  1405  can be a clean room or other location suitable for printing features on substrates. Enclosure  1405  can also be a dedicated environmental system to be placed inside a clean room to provide both environmental stability and protection against airborne particles and other causes of printing defects.  
      Enclosure  1405  encloses an interference lithography system  1410  and a patterning system  1415 . Interference lithography system  1410  includes a collimated electromagnetic radiation source  1420  and interference optics  1425  that together provide interferometric patterning of substrates. Patterning system  1415  can use any of a number of different approaches for patterning a substrate. For example, patterning system  1415  can be an e-beam projection system, an imprint printing system, or an optical projection lithography system. Patterning system  1415  can also be a maskless module, such as an electron beam direct write module, an ion beam direct write module, or an optical direct write module.  
      Systems  1410 ,  1415  can share a common mask handling subsystem  1430 , a common wafer handling subsystem  1435 , a common control subsystem  1440 , and a common stage  1445 . Mask handling subsystem  1430  is a device for positioning a mask in system  1400 . Wafer handling subsystem  1435  is a device for positioning a wafer in system  1400 . Control subsystem  1440  is a device for regulating one or more properties or devices of system  1400  over time. For example, control subsystem  1440  can regulate the position or operation of a device in system  1400  or the temperature or other environmental qualities within environmental enclosure  1405 .  
      Control subsystem  1440  can also translate stage  1445  between a first position  1450  and a second position  1455 . Stage  1445  includes a chuck  1460  for gripping a wafer. At first position  1450 , stage  1445  and chuck  1460  can present a gripped wafer to patterning system  1415  for patterning. At second position  1455 , stage  1445  and chuck  1460  can present a gripped wafer to interference lithography system  1410  for interferometric patterning.  
      To ensure the proper positioning of a wafer by chuck  1460  and stage  1445 , control subsystem  1440  includes an alignment sensor  1465 . Alignment sensor  1465  can transduce and control the position of the wafer (e.g., using wafer alignment marks) to align a pattern formed using interference lithography system  1410  with a pattern formed by patterning system  1415 . Such positioning can be used when introducing irregularity into a repeating array of features, as discussed above.  
       FIG. 15  shows an example optical lithographic implementation of patterning system  1415 . In particular, patterning system  1415  can be a step-and-repeat projection system. Such a patterning system  1415  can include an illuminator  1505 , a mask stage  1510 , and projection optics  1515 . Illuminator  1505  can include an electromagnetic radiation source  1520  and an aperture/condenser  1525 . Source  1520  can be the same as source  1420  or source  1520  can be an entirely different device. Source  1520  can emit at the same or at a different wavelength as source  1420 . Aperture/condenser  1525  can include one or more devices for collecting, collimating, filtering, and focusing the electromagnetic emission from source  1420  to increase the uniformity of illumination upon mask stage  1510 .  
      Mask stage  1510  can support a mask  1530  in the illumination path. Projection optics  1515  can be a device for reducing image size. Projection optics  1515  can include a filtering projection lens. As stage  1445  repeatedly translates a gripped wafer for exposure by illuminator  1505  through mask stage  1510  and projection optics  1515 , alignment sensor  1465  can ensure that the exposures are aligned with a repeating array of interferometric features to introduce irregularity into the repeating array.  
      A number of implementations have been described. Nevertheless, it will be understood that various modifications may be made. For example, both positive and negative resists can be used for either of resist layers  220 ,  705 . Lithographic techniques that use different wavelengths can be used to process the same substrate. Substrates other than semiconductor wafers can be patterned. Accordingly, other implementations are within the scope of the following claims.