Patent Publication Number: US-6337571-B2

Title: Ultra-high-frequency current probe in surface-mount form factor

Description:
FIELD OF THE INVENTION 
     The present invention relates to a current probe for ultra high frequency current measurements. 
     BACKGROUND OF THE INVENTION 
     Presently available current probes measure the current flowing through a signal line by being coupled magnetically to the signal line. Some current probes require that the signal line be broken and be threaded through a magnetic core to provide the magnetic coupling. Other current probes do not require that the signal line be disrupted in this manner. 
     For example, U.S. Pat. No. 5,044,974, issued Apr. 2, 1991 to Cattaneo et al. shows a current probe which includes an assembly on which is mounted an electronic printed circuit board. The assembly includes a magnetic circuit consisting of a stack of metal sheets. The signal whose current is being monitored is sent through a winding around the magnetic circuit. The winding is formed by U shaped conductor portions surrounding three sides of the magnetic circuit in the assembly, and through corresponding conductive traces on the printed circuit board interconnecting the U shaped conductor portions. These traces are laid out to allow the number of windings around the magnetic circuit to be varied. A second winding around the magnetic circuit is used to provide an input to a measuring device. A further provision of a location for a Hall cell within the magnetic circuit allows for the second winding to zero out the net magnetic flux in the magnetic circuit, allowing the device to be used as a nulling sensor. This current probe can be mounted on a main printed circuit board, and operates at relatively low frequencies. 
     However, all existing ultra high frequency current probes of relatively high sensitivity require that the signal line whose current is being observed be threaded through, and possibly wound around, a closed ferrite high frequency transformer core. In this way, the signal line forms one winding of a transformer. The other winding of the transformer is connected to the test equipment (i.e. oscillo-scope, network analyzer, etc.). In these current probes, the presence of the ferrite core, and the test equipment attached to its winding, causes some amount of change to the electrical characteristics of the circuit. This is because the transformer and the attached test equipment form an electrical element having a finite resistance, and, most likely, a non-zero reactance. Thus, the results of the test do not accurately reflect the operation of the circuit with the current probe removed. 
     Mechanically, such an arrangement also produces much wear and tear on the circuit being observed. This is because to make a measurement the signal line must be broken, the ferrite core threaded onto the signal line, the signal line reconnected, the measurement made, the signal line broken again, the ferrite core removed and the signal line reconnected again. There is also wear and tear on the current probe itself from this procedure. For production line testing, high volume measurements are performed, often, with automated handling of the product being tested (i.e. by robots). In such an environment, a current probe as described above must be inserted manually in the circuit. The time required for inserting and removing such a current probe is significant. 
     A current probe which operates at ultra high frequencies, which makes connections between the signal line being observed and the test equipment fast, easy and able to be performed by automated handling, and which can provide a minimal change to the electrical characteristics of the signal being observed is desirable. 
     SUMMARY OF THE INVENTION 
     In accordance with principles of the present invention an ultra high frequency current probe is fabricated in the form of a surface mount device, designed to be a part of the circuit providing the current being observed. 
     Because such a current probe becomes a part of the electrical circuit, it has a minimal effect on the electrical characteristics of the signal being observed. Also there is no manual handling of a current probe during testing. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING 
     In the drawing: 
     FIG. 1 is a block diagram of a current probe according to the present invention illustrated in place to measure the current through a signal line; 
     FIG. 2 is a schematic diagram of the input section of the current probe illustrated in FIG. 1; 
     FIG. 3 is a schematic diagram of the output section of the current probe illustrated in FIG. 1; and 
     FIG. 4 is a plan view of the top of the surface mount device in which the current probe illustrated in FIG. 1 is embodied. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     FIG. 1 is a block diagram of an ultra high frequency current probe according to the present invention. The current probe is illustrated in place to measure the current through a signal line. In FIG. 1, an input terminal  5  is coupled to a source (not shown) of an input current signal Iin. This current signal Iin may include ultra high frequency components, typically around two to four gigahertz (GHz). Input terminal  5  is coupled to an input terminal of a signal line in the form of a transmission line, illustrated in FIG. 1 as transmission line  10 . In the illustrated embodiment, the transmission line  10  has a 50Ω characteristic impedance. An output terminal of transmission line  10  acts as a source of the current being measured, and is coupled to a current input terminal of a current probe  20 . A current output terminal of the probe  20  is coupled to an input terminal of a second transmission line  30  which is the continuation of the signal line carrying the current is being observed. In the illustrated embodiment, the transmission line  30  also has a 50Ω characteristic impedance. The input terminal of the second transmission line  30  acts as a sink for the current being measured. An output terminal of the second transmission line  30  is coupled to an output terminal  15 . Output terminal  15  generates a current Iout, and is coupled to the remainder of the circuit being tested (not shown). A test voltage output terminal of the current probe  20  is coupled to a test voltage output terminal Vtest  25 . The current probe  20  also includes a terminal coupled to a source of reference potential (ground). 
     In operation, the current probe  20  produces a voltage between the test voltage output terminal Vtest and ground representing the value of the current passing from the current input terminal to the current output terminal of the current probe  20 . However, the current probe  20  also has the electrical characteristics of a 50Ω transmission line. Thus, the presence of the current probe  20  in the signal line being observed has a minimal effect on the electrical characteristics of that signal line, and, therefore, on the remainder of the circuit (not shown) through which that current signal is flowing. Such a current probe  20  has the high frequency performance of a lumped 50Ω transmission line with a short delay and a cut-off frequency of approximately 4 GHz. 
     FIG. 2 is a schematic diagram of the input section of the current probe illustrated in FIG.  1 . In FIG. 2, elements which are the same as those in FIG. 1 are designated by the same reference number, and are not described in detail below. In FIG. 2, the 50Ω transmission line  10  is coupled to an input terminal  22  of the current probe  20 . The input terminal  22  is coupled to a first electrode of a first capacitor C 1 , and a first electrode of a primary winding Wp of a high frequency transformer T 1 . A second electrode of the primary winding Wp is coupled to a first electrode of a second capacitor C 2  and to an output terminal  24  of the current probe  20 . Respective second electrodes of the first and second capacitors, C 1  and C 2 , are coupled to ground. The output terminal  24  of the current probe  20  is coupled to the 50Ω transmission line  30 . The primary winding Wp is coupled through a high frequency ferrite core to a secondary winding Ws. The secondary winding Ws produces a voltage signal representing the current flowing through the primary winding in a manner to be described in more detail below. 
     In operation, the combination of the 50Ω transmission line  10  and 50Ω transmission line  30  carry the signal current. The input terminal  22  transports the signal current from the transmission line  10  into the current probe, and is fabricated in the current probe  20  to have substantially a 50 characteristic impedance. Similarly, the output terminal  24  transports the signal current from the current probe  20  to the transmission line  30 , and is also fabricated to have substantially a 50Ω characteristic impedance. The primary winding Wp is fabricated as a sense wire threaded through the high frequency ferrite core between the input and output terminals,  22  and  24 . While the signal current is traversing the primary winding, the high frequency transformer T 1  converts its electromagnetic flux field into a voltage at the secondary winding Ws. The sense wire is the only location where the characteristic impedance of the signal carrying line potentially can vary from the 50Ω characteristic impedance. 
     However, the inductance of the primary winding Wp is countered by the first and second capacitors C 1  and C 2 . The combination of the primary winding Wp and the first and second capacitors, C 1  and C 2 , forms a 50Ω lumped network which maintains the 50Ω characteristic impedance of the signal carrying line. In the illustrated embodiment, the primary winding has an impedance of 2.2 nanoHenries (nH). To maintain an impedance of 50Ω in the lumped network the first and second capacitors require capacitances of less than 1.0 picoFarads (pf) each. With such a lumped network the 50 characteristic impedance of the signal line is maintained from the input transmission line  10 , into the current probe  20  through input terminal  22 , through the high frequency transformer T 1 , out of the current probe  20  through output terminal  24  and to the output transmission line  30 . In this way the effect of the current probe on the signal characteristics of the circuit it is measuring is minimized. 
     In the illustrated embodiment, the parasitic capacitance of the input terminal  22  and the output terminal  24  are each substantially the desired capacitance of the first and second capacitors C 1  and C 2 . Discrete capacitors, thus, are not necessary in the illustrated embodiment. However, one skilled in the art will understand that different physical arrangements can result in parasitic capacitances having different values, and that different arrangements for the primary winding Wp can have different inductances. In such cases, different values of capacitors C 1  and C 2  to may be required to form the required 50Ω lumped network. In these arrangements, discrete capacitors may be necessary to provide the required capacitance. 
     FIG. 3 is a schematic diagram of the output section of the current probe illustrated in FIG.  1 . In FIG. 3, elements which are the same as those illustrated in FIGS. 1 and 2 are designated by the same reference number and are not described in detail below. In FIG. 3, a first electrode of the secondary winding Ws of the high frequency transformer T 1  is coupled through an equivalent inductance Lc to a first electrode of an equivalent resistance Rc. A second electrode of the resistance Rc is coupled to a second electrode of the secondary winding. The loop formed by the secondary winding Ws, the equivalent inductance Lc and the equivalent resistance Rc represents the equivalent circuit for the transformer T 1  secondary winding Ws, in which the secondary winding Ws leakage inductance is Lc and the core loss resistance is Rc. 
     The second electrode of the equivalent inductance Lc is also coupled to a first electrode of a second inductance L 2  and to the test voltage Vtest output terminal  26 . A second electrode of the second inductance L 2  is coupled to a first electrode of a second resistor R 2 . A second electrode of the second resistor R 2  is coupled to the second electrode of the secondary winding Ws, and to ground. In the illustrated embodiment, the inductance of the second inductance L 2  is 8.2 nH, and the resistance of the second resistor R 2  is 61.9Ω. 
     In operation, the current flowing from the current input terminal  22 , through the primary winding Wp of the transformer T 1  to the current output terminal  24  induces a voltage across the secondary winding Ws in a known manner. The combination of the electrical characteristics (i.e. Lc and Rc) of the secondary winding Ws and the second inductance L 2  and second resistor R 2  produce an output impedance between the test voltage Vtest output terminal  26  and ground of 50Ω. Provided this output terminal is connected to the test equipment through a 50Ω transmission line, and properly terminated at the test equipment with a 50Ω input impedance, the current probe  20  will produce minimal loading on the circuit being tested. 
     In order to minimize the time and manual effort necessary to install and remove the current probe, e.g. in a production test environment as described above, the current probe  20  illustrated in FIG. 1 is fabricated as a surface mount device (SMD). This SMD is designed to be a permanent part of the circuit board, e.g. a printed circuit board, containing the signal line being observed. In the illustrated embodiment, the signal line being observed is fabricated on the circuit board as a  50  transmission line by copper traces of appropriate size and spacing on the surface of a circuit board, in a known manner. A gap is left in the copper traces forming the transmission line, thus forming on one side of the gap the input transmission line  10  and on the other side of the gap the output transmission line  30 . The current input terminal  22  of the SMD is coupled to the input transmission line  10  and the current output terminal  24  is connected to the output transmission line  30 , thus completing the signal line circuit. As described above, because the current probe  20  maintains as closely as possible the 50Ω characteristic impedance of the signal line, the changes to the 50Ω characteristic impedance of the transmission line carrying the signal due to current probe  20  are minimal, and the transmission line environment is maintained as closely as possible. 
     FIG. 4 is a plan view of a top layer  504  of an SMD  500  in which the current probe  20  illustrated in FIG. 1 is embodied. Elements corresponding to those illustrated in FIGS. 1 through 3 are designated by the same reference numbers. The SMD  500  in FIG. 4 includes a ground layer (not shown) within the SMD  500  and arranged parallel to the top layer  504 . Solder pads  402  and  404  are coupled to the input transmission line  10  (not shown) via a pair of wires forming the input terminal  22  of the current probe  20 . In a similar manner solder pads  408  and  410  are coupled to the output transmission line  30  (also not shown) via a pair of wires forming the output terminal  24 . Also a pair of wires (not shown for simplicity) forming the Vtest output terminal  26  and carrying the test voltage Vtest signal is coupled to solder pads  414  and  416 . In the illustrated embodiment, the solder pads  402  and  410  and  416  are all connected to respective signal vias which connect them from the top layer  504  of the SMD  500  to the ground layer (not shown). 
     A sense wire, forming the primary Wp of the high frequency transformer T 1  is electrically connected between the input current signal solder pad  404  and the output current signal solder pad  408 . The sense wire Wp is threaded through the center of a toroidal high frequency ferrite transformer core, illustrated in side view in FIG.  4 . 
     A secondary winding Ws is wound around the ferrite transformer core, as represented by the diagonal lines in FIG. 4. A first end of the secondary winding Ws is connected through a wire  424  to a solder pad  422  which is coupled to the ground layer through a signal via. A second end of the secondary winding Ws is connected through a wire  426  to the test voltage Vtest signal solder pad  414 . The test voltage Vtest signal solder pad  414  is also connected to a first electrode of the inductor L 2  via a signal trace  417 . A second electrode of the inductor L 2  is connected to a first electrode of the resistor R 2  via a signal trace  419 . A second electrode of the resistor R 2  is connected to the ground solder pad  422  through a wire  428 . The inductor L 2  and resistor R 2  are fabricated in a known manner on the top layer  504  of the SMD  500 . 
     As described above, the parasitic capacitance of the input terminal  22  and solder pads  402  and  404 , and the output terminal  24  and solder pads  408  and  410 , have sufficient capacitance to form the first and second capacitors C 1  and C 2  of the 50Ω lumped circuit. In the illustrated embodiment, discrete capacitors C 1  and C 2  are, thus, not necessary. However, also as described above, there are configurations in which discrete capacitors C 1  and C 2  are necessary. Such an arrangement is illustrated in phantom in FIG.  4 . The top of the input current signal solder pad  404  is also connected to the first electrode of the first capacitor C 1  (shown in phantom) via a signal trace  403  (also shown in phantom). The top of the output current signal solder pad  408  is connected to the first electrode of the second capacitor C 2  (shown in phantom) via a signal trace  411  (also shown in phantom). Second electrodes of the first and second capacitors C 1  and C 2  are connected to the ground solder pad  422 . The first and second capacitors C 1  and C 2  are fabricated in a known manner on the top lay er  504  of th e SMD  500 . 
     As described above, the combination of the first and second capacitors, C 1  and C 2 , (parasitic or discrete) and the inductance of the primary winding Wp form a lumped 50Ω network to preserve the 50Ω characteristic impedance of the signal line through the current probe  20 ; and the combination of the inductor L 2 , the resistor R 2  and the inductance and resistance of the secondary winding Ws present a 50Ω output impedance at the test voltage Vtest output terminal. The overall dimensions of the SMD  500  are around 0.385 inches (0.978 cm) square. This is a relatively small component and may fit easily on a printed circuit board. 
     In addition, the illustrated embodiment of the current probe  20  approximates a 50Ω lumped impedance transmission line with a known time delay, both in the signal current line, and at the test voltage (Vtest) output terminal. The time delay in the illustrated current probe  20  ranges from 120 picoseconds (psec) to 170 psec, depending upon the shielding and other microwave absorbent material physically disposed around the current probe  20 . This electrical characteristic simplifies modeling the performance of the current probe. Furthermore, the bandwidth of the illustrated current probe  20  runs from around 160 kilohertz (kHz) to around 3.2 GHz. This is much wider than existing current probes which can be mounted on circuit boards (e.g. U.S. Pat. No. 5,004,974, described above), and allows the illustrated current probe  20  to be used in ultra high frequency circuits. 
     The illustrated embodiment of the present invention has been described for a circuit being tested fabricated in the form of a circuit board, such as a printed circuit board, and the current probe has been described in the form of a surface mounted device. One skilled in the art will understand, however, that circuits being tested may be fabricated in a variety of forms, and the current probe may be fabricated in any manner appropriate for the circuit being tested. Furthermore, in the illustrated embodiment, the transmission lines carrying the signal being observed were fabricated to have a 50Ω characteristic impedance. One skilled in the art will understand that the characteristic impedance may be any appropriate value.