Patent Publication Number: US-8121200-B2

Title: Multi-level LVDS data transmission with embedded word clock

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     The present application is related to copending U.S. provisional application (“Copending Application”), entitled “Tri-level LVDS Data Transmission with Embedded Word Clock”, Ser. No. 60/830,861, filed on Jul. 13, 2006. The Copending Application is hereby incorporated by reference in its entirety. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to data communication; in particular, the present invention relates signaling conventions in data communication. 
     2. Discussion of the Related Art 
     In high speed data communications, a serial format has many advantages. For example, a serial format does not require synchronizing the parallel data and avoids the high cost of multiple conductors. However, the serial format must allow the receiver to easily recover the clock signal and to recognize data signal boundaries (e.g., word boundaries). Typically, the receiver includes a sophisticated clock recovery circuit for extracting an embedded clock signal, and the transmitted signal includes a special bit pattern or encoding to demarcate data boundaries. 
     SUMMARY 
     According to one embodiment of the present invention, a multi-level signal uses a third signal (and optionally, a fourth signal level) to signal both a word clock edge and a data word boundary. At the receiver, a level detector detects a transition to or from the third level as a clock signal transition and the word boundary. The bit clock can be recovered using a conventional clock multiplier. Bi-level signaling is used for data between the word boundaries. 
     According to another embodiment of the present invention, additional signal states are available in the multi-level signal by modulating the pulse width at the third signal level. In one implementation, when the signal stays at the third level for one bit period, it signals that the transmitted bits are data. In that implementation, when the signal stays at the third level for two and three bit periods, it signals that the transmitted bits are control information and audio data, respectively. 
     The present invention is better understood upon consideration of the detailed description below and the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIGS. 1(   a ) and  1 ( b ) show a multi-level serial data signals  100  and  150 , respectively, according to one embodiment of the present invention. 
         FIG. 2(   a ) shows transmitter circuit  200  for a multi-level serial data signal, in accordance with one embodiment of the present invention. 
         FIG. 2(   b ) shows transmitter circuit  250  for a multi-level serial data signal, in accordance with one embodiment of the present invention. 
         FIG. 3  shows a block diagram of a receiver  300  for a multi-level serial data signal, in accordance with one embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The present invention is particularly applicable to high speed data transmission operations where a serial data format is preferred and over a low-noise channel. One application is, for example, is data communication between two movable components of a device, such as between the foldable pieces of a “flip” cellular phone. 
       FIGS. 1(   a ) and  1 ( b ) show a multi-level serial data signals  100  and  150 , respectively, according to one embodiment of the present invention. As shown in  FIG. 1(   a ), multi-level serial data signal  100  uses a low voltage differential signaling (LVDS) format (e.g., signal voltage levels between ±3.3 volts). Serial data signal  100  uses third level signaling (e.g., ±200 mV) for the first bit (i.e., bit D 0 ) within a data word (e.g., D 0 -D 15 ) and bi-level signaling (e.g., ±100 mV) for the remaining bits within the data word. The term “word” denotes an organization of data that consists of multiple bits. Typical convenient word lengths are 8, 16, 32, 64, or 128, although there are no restrictions on the number of bits.  FIG. 1(   b ) shows an alternative multi-level serial data signal  150  with a common mode component. A common mode component may give out relatively stronger electromagnetic interference. In a lower speed application, the data signal  FIG. 1(   b ) is preferable because it is simpler to implement, relative to the data signal of  FIG. 1(   a ). 
       FIGS. 1(   a ) and  1 ( b ) also show that additional signal states are available in the multi-level signal by modulating the pulse width at the third signal level. As shown in each of  FIGS. 1(   a ) and  1 ( c ), the multi-level signal may stay at the third level for one, two or three bit periods (i.e., D 0 , D 0 -D 1  and D 0 -D 2 , respectively). In one implementation, the pulse width encodes the nature of the bits transmitted. (Of course, the pulse width may be modulated for even greater duration.) For example, if the muliti-level signal returns to bi-level signaling after bit D 0 , the transmitted bits are indicated to be data. In that implementation, when the multi-level signal stays at the third level for two and three bit periods, it signals that the transmitted bits are control information and audio data, respectively. 
       FIG. 2(   a ) shows transmitter circuit  200  for a multi-level serial data signal, in accordance with one embodiment of the present invention. As shown in  FIG. 2(   a ), transmitter circuit  200  includes a differential amplifier having differential input terminals  201   a  and  201   b  driving the control input terminals of transistors  203   a  and  203   b . The source and drain terminals of transistors  203   a  and  203   b  are serially connected respectively to the power supply reference voltages through load transistors  204   a  and  204   b  and current source  205  to provide a differential output signal across output terminals  202 ( a ) and  202 ( b ). An additional switched current source  206  is provided to modulate the current through the load transistors for multi-level signaling. During bi-level signaling, the switch current source is switched off. To signal at the third signal level (e.g., at a word boundary) switched current source  206  is turned on to increase the voltage swing across output terminals  202 ( a ) and  202 ( b ). 
     An alternative implementation is shown in  FIG. 2(   b ) as transmitter circuit  250 , in accordance with one embodiment of the present invention. Transmitter  250  differs from transmitter  200  by sourcing the current in switched current source  206  through additional input transistors  207 ( a ) and  207 ( b ), which are activated only during signaling at the third signal level. Input transistors  207 ( a ) and  207 ( b ) are connected in parallel to input transistors  201 ( a ) and  201 ( b ). Transmitter  250  provides better dynamic range than transmitter  200  of  FIG. 2(   a ). 
     The high level (e.g., the third level) can be adjusted by separate circuitry if a constant common mode is desired, or by a push-pull circuitry configuration. Otherwise for a constant voltage high level, the waveform can be shown as in  FIG. 1(   b ). 
       FIG. 3  shows a block diagram of a receiver  300  for a multi-level serial data signal, in accordance with one embodiment of the present invention. In receiver  300 , a level detector  301  is set to detect the signal transitions to the third (or the fourth, if present) signal level across output terminals  202 ( a ) and  202 ( b ). As this signal transitions occur at a word boundary, the signal transition can be used as input to a clock multiplier  303  (which is typically implemented to include a phase locked loop, as illustrated in  FIG. 3 ) useful in generating the bit clock that is synchronous with the bits between the bits signaled at the third (or fourth) signal level, which in turn is used to deserialize the serial data. When word synchronization is substantially achieved (i.e., a good phase lock is achieved by the phase-locked loop in clock multiplier  303 ), third (or fourth) level signaling at the word boundary may be omitted to save power—i.e., using only bi-level signaling—until either re-synchronization is required or a change in the nature of the data transmitted. The receiver may indicate achievement of synchronization to the transmitter, when the receiver and the transmitter are capable of bidirectional communication. 
     It is observed that, using the above signaling scheme, even including the circuits for recovering the bit clock from the transmitted signal, the resulting receiver has a lower power dissipation and a simpler circuitry than that using a conventional clock recover circuit. 
     The above detailed description is provided to illustrate specific embodiments of the present invention and is not intended to be limiting. Many variations and modifications within the scope of the invention are possible. The present invention is set forth in the accompanying claims.