Patent Publication Number: US-11036597-B2

Title: Semiconductor memory system and method of repairing the semiconductor memory system

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     The present application claims priority under 35 U.S.C. § 119(a) to Korean Application No. 10-2018-0038902, filed on Apr. 3, 2018, which is incorporated herein by references in its entirety. 
     BACKGROUND 
     1. Technical Field 
     Various embodiments of the present disclosure relate to a semiconductor memory system and, more particularly, to a semiconductor memory system and method of repairing the semiconductor memory system. 
     2. Related Art 
     Semiconductor memory devices employed in semiconductor memory systems for storing data may be typically categorized as either volatile semiconductor memory devices or nonvolatile semiconductor memory devices. The volatile semiconductor memory devices may store data by charging cell capacitors or discharging cell capacitors. The volatile semiconductor memory devices such as dynamic random access memory (DRAM) devices may retain their stored data when their power supplies are provided and may lose their stored data when their power supplies are interrupted. These volatile semiconductor memory devices may be mainly used as main memory devices of computer systems or the like. In contrast, the nonvolatile semiconductor memory devices may retain their stored data even when their power supplies are interrupted. The nonvolatile semiconductor memory devices may include flash memory devices, phase change random access memory (PCRAM) devices, etc., and may be mainly used as storage media for storing programs and data in computer systems, portable communication systems, or other application systems. 
     A semiconductor memory device may be packaged and used by a memory die or a memory chip. In some cases, a plurality of memory chips may be mounted and stacked on a substrate, like a printed circuit board (PCB), to provide a memory module. The memory module may further include a spare chip in addition to the plurality of memory chips. In the event of a memory chip failure, the memory chip and its functionality may be replaced by the spare chip. 
     SUMMARY 
     In accordance with the present teachings, a semiconductor memory system includes a memory medium and a data input/output (I/O) pin repair control circuit. The memory medium includes a plurality of memory dies and a spare die. Each of the plurality of memory dies has a plurality of memory regions and a plurality of data I/O pins, and the spare die has a plurality of spare regions and a plurality of data I/O pins. The data I/O pin repair control circuit performs a repair process for replacing an abnormal data I/O pin among the plurality of data I/O pins included in any of the plurality of memory dies with a data I/O pin of the plurality of data I/O pins included in the spare die. 
     Also in accordance with the present teachings, is a method of repairing a semiconductor memory system including a plurality of memory dies and a spare die, wherein each of the plurality of memory dies has a plurality of memory regions and a plurality of data input/output (I/O) pins, and wherein the spare die has a plurality of spare regions and a plurality of data I/O pins. The method includes performing a repair process for replacing an abnormal data I/O pin among the plurality of data I/O pins included in any of the plurality of memory dies with a data I/O pin of the plurality of data I/O pins included in the spare die. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The accompanying figures, where like reference numerals refer to identical or functionally similar elements throughout the separate views, together with the detailed description below, are incorporated in and form part of the specification, and serve to further illustrate embodiments of concepts that include the claimed novelty, and explain various principles and advantages of those embodiments. 
         FIG. 1  shows a block diagram illustrating a semiconductor memory system, according an embodiment of the present disclosure. 
         FIG. 2  shows a block diagram illustrating a configuration of a memory die included in a memory medium of the semiconductor memory system shown in  FIG. 1 . 
         FIG. 3  shows is a block diagram illustrating a configuration of a spare die included in the memory medium of the semiconductor memory system shown in  FIG. 1 . 
         FIGS. 4 and 5  show schematic views illustrating a method of repairing a semiconductor memory system, according an embodiment of the present disclosure. 
         FIG. 6  shows a flowchart illustrating a method of repairing a semiconductor memory system, according an embodiment of the present disclosure. 
         FIG. 7  shows a schematic view illustrating a process for changing data in a mode register set (MRS) during a repair process of a semiconductor memory system, according an embodiment of the present disclosure. 
         FIGS. 8 and 9  show block diagrams illustrating data migration during a repair process performed with data input/output (I/O) terminals as a unit in a semiconductor memory system, according an embodiment of the present disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     In the following description of embodiments, it will be understood that the terms “first” and “second” are intended to identify an element, but not used to define only the element itself or to mean a particular sequence. In addition, when an element is referred to as being located “on,” “over,” “above,” “under,” or “beneath” another element, it is intended to mean relative position relationship, but not used to impose the limitation that the two elements are in direct contact with one another. For example, there may be one or more intervening components present between the two elements. Accordingly, terms such as “on,” “over,” “above,” “under,” “beneath,” “below” and the like are used herein for the purpose of describing particular embodiments only and are not intended to limit the scope of the present disclosure. Further, when an element is referred to as being “connected” or “coupled” to another element, the two elements may be electrically or mechanically connected or coupled together directly, or there may be one or more intervening components the two elements. 
     Various embodiments are directed to semiconductor memory systems supporting repair with a data input/output (I/O) terminal as a unit and methods of repairing the semiconductor memory systems. 
     In general, if one or more data I/O terminals of any one of a plurality of memory dies included in a memory medium malfunctions, a repair process may be performed to replace the memory die having the malfunctioning data I/O terminal with a spare die. After the repair process, if a command for selecting the memory die having the malfunctioning data I/O terminal occurs, the spare die may be selected by the command and data communication may be realized with the spare die instead of the memory die having the malfunctioning data I/O terminal. Each of the memory dies may have a plurality of data I/O terminals. Thus, even though one among the plurality of data I/O terminals of any one of the memory dies malfunctions, an entire portion of the spare die may be used to repair the memory die having only the single malfunctioning data I/O terminal. Accordingly, the present disclosure may provide semiconductor memory systems which are repairable in units of data I/O terminals such that two or more memory dies are repaired using only one spare die. 
       FIG. 1  shows a block diagram illustrating a semiconductor memory system  10 , according an embodiment of the present disclosure. Referring to  FIG. 1 , the semiconductor memory system  10  may be configured to include a memory medium  100  and a memory controller  200 . In an embodiment, the memory medium  100  may have a configuration of a memory module. The memory medium  100  may include a plurality of memory dies (e.g., first to n th  memory dies  110 - 1 , . . . , and  110 - n ) and a plurality of spare dies (e.g., first to m th  spare dies  120 - 1 , . . . , and  120 - m ). In an embodiment, the first to n th  memory dies  110 - 1 , . . . , and  110 - n  and the first to m th  spare dies  120 - 1 , . . . , and  120 - m  may be realized using volatile semiconductor memory devices, such as DRAM devices. In another embodiment, the first to n th  memory dies  110 - 1 , . . . , and  110 - n  and the first to m th  spare dies  120 - 1 , . . . , and  120 - m  may be realized using nonvolatile semiconductor memory devices, such as PCRAM devices. Each of the first to n th  memory dies  110 - 1 , . . . , and  110 - n  and the first to m th  spare dies  120 - 1 , . . . , and  120 - m  may include a mode register set (MRS). Although not shown in  FIG. 1 , each of the first to n th  memory dies  110 - 1 , . . . , and  110 - n  and the first to m th  spare dies  120 - 1 , . . . , and  120 - m  may have a plurality of data I/O terminals (also referred to as data I/O pins) for data transmission. The memory medium  100  may communicate with the memory controller  200  through a data I/O line DQ. That is, the memory medium  100  may receive data from the memory controller  200  through the data I/O line DQ and may output the data to the memory controller  200  through the data I/O line DQ. In addition, the memory medium  100  may also communicate with the memory controller  200  through a command/address line CMD/ADDR. That is, the memory medium  100  may receive a command and an address from the memory controller  200  through the command/address line CMD/ADDR. 
     The memory controller  200  may be configured to include a host command processing circuit  210 , an error correction code (ECC) circuit  220 , and a data I/O (DQ) pin repair control circuit  230 . The host command processing circuit  210  may be configured to process a command and an address which are outputted by a host. In an embodiment, a command processed by the host command processing circuit  210  may include a read command or a write command for the memory medium  100 . In an embodiment, if the read command and the address are transmitted from the host to the host command processing circuit  210 , the host command processing circuit  210  may operate to transmit read data in the memory medium  100 , which is designated by the address, to the ECC circuit  220 . In an embodiment, if the write command and the address are transmitted from the host to the host command processing circuit  210  and write data is transmitted from the host to the ECC circuit  220 , then the host command processing circuit  210  may operate to store ECC encoded write data, which is encoded by the ECC circuit  220 , to a storage region designated by the address among a plurality of storage regions of the memory medium  100 . 
     The ECC circuit  220  may include an ECC encoder and an ECC decoder. The ECC encoder may perform an ECC encoding operation of the write data transmitted from the host during a write operation for the memory medium  100 . The ECC encoder may perform the ECC encoding operation of the write data to generate a codeword including the write data and parity data. Data stored in the memory medium  100  may have a codeword form. The ECC decoder may perform an ECC decoding operation of the read data transmitted from the memory medium  100  during a read operation for the memory medium  100 . If the read data has an error, the error may be detected and corrected by the ECC decoding operation. The error correction of the read data may be achieved within the range of an error correction capability of the ECC circuit  220 . The error correction capability of the ECC circuit  220  may be defined as the number of erroneous bits or erroneous symbols which are correctable using the ECC circuit  220 . The ECC encoding operation and the ECC decoding operation may be performed in units of bits or symbols, according to an error correction algorithm employed in the ECC encoding operation and the ECC decoding operation. 
     The data I/O (DQ) pin repair control circuit  230  may monitor whether any of the first to n th  memory dies  110 - 1 , . . . , and  110 - n  has at least one abnormal data I/O pin that malfunctions. In order to monitor the function of the first to n th  memory dies  110 - 1 , . . . , and  110 - n , the data I/O (DQ) pin repair control circuit  230  may access information on erroneous data generated by the ECC circuit  220 . Whether any of the first to n th  memory dies  110 - 1 , . . . , and  110 - n  has at least one abnormal data I/O pin that malfunctions may be discriminated by monitoring the frequency of errors of data transmitted through the data I/O pins. For example, if the error occurrence frequency for the data transmitted through a first data I/O pin of the first memory die  110 - 1 , included in the memory medium  100 , is greater than a predetermined reference value, then the data I/O (DQ) pin repair control circuit  230  may regard the first data I/O pin of the first memory die  110 - 1  as an abnormal data I/O pin that is malfunctioning. The predetermined reference value for discriminating whether the data I/O pins of the first to n th  memory dies  110 - 1 , . . . , and  110 - n  are functioning normally or not may be set in relation to the reliability or desired reliability of the semiconductor memory system  10 . In an embodiment, the predetermined reference value may be set to have a low number in order to increase the reliability of the semiconductor memory system  10 . However, if the predetermined reference value is too low, the number of times that the repair process is performed may increase to cause a degradation in function of the semiconductor memory system  10 . Accordingly, the determination of the reference value may be made with consideration of the performance of the semiconductor memory system  10 . 
     If a specific data I/O pin among the plurality of data I/O pins is determined as being functioning abnormally by the data I/O (DQ) pin repair control circuit  230 , then the data I/O (DQ) pin repair control circuit  230  may perform a repair process in units of data I/O pins. While the repair process is being performed in units of data I/O pins, there may be a disruption in accessing the memory medium  100 . Thus, a halt command for interrupting the operation of the host for accessing the semiconductor memory system may be transmitted to the host before the repair process is performed. For some embodiments, the repair process performed in units of data I/O pins by the data I/O (DQ) pin repair control circuit  230  is not executed by replacing an entire portion of a memory chip having the abnormal data I/O pin with a spare die but executed by replacing only the abnormal data I/O pin with any one of a plurality of data I/O pins of the spare die. The repair process performed in units of data I/O pins is described below. 
       FIG. 2  shows a block diagram illustrating a configuration of a memory die  110  corresponding to any one of the memory dies included in the memory medium  100  of the semiconductor memory system  10  shown in  FIG. 1 . That is, each of the first to n th  memory dies  110 - 1 , . . . , and  110 - n  may have substantially the same configuration as the memory die  110  illustrated in  FIG. 2 . In  FIG. 2 , an MRS of the memory die  110  is omitted. Referring to  FIG. 2 , the memory die  110  may include a memory storage region  111  and a plurality of data I/O pins, for example, first to fourth data I/O pins DQ 0 , DQ 1 , DQ 2  and DQ 3  (also, denoted by ‘ 112 A,’ ‘ 112 B,’ ‘ 112 C,’ and ‘ 112 D’). The memory storage region  111  may be divided into a plurality of memory regions, for example, first to fourth memory regions  111 A,  111 B,  111 C, and  111 D. The memory die  110  may further include a data I/O logic circuit  113  functioning as an interface circuit between the memory regions  111 A,  111 B,  111 C, and  111 D and the data I/O pins  112 A,  112 B,  112 C, and  112 D. For an embodiment, the number of the memory regions  111 A,  111 B,  111 C, and  111 D may be equal to the number of the data I/O pins  112 A,  112 B,  112 C, and  112 D. 
     In the present embodiment, the first to fourth memory regions  111 A,  111 B,  111 C, and  111 D may be distinguished from each other according to the first to fourth data I/O pins  112 A,  112 B,  112 C, and  112 D that execute data communication with the first to fourth memory regions  111 A,  111 B,  111 C, and  111 D. In an embodiment, the first memory region  111 A may be defined as the region that receives or outputs data through the first data I/O pin  112 A. The second memory region  111 B may be defined as a region that receives or outputs data through the second data I/O pin  112 B. The third memory region  111 C may be defined as a region that receives or outputs data through the third data I/O pin  112 C, and the fourth memory region  111 D may be defined as a region that receives or outputs data through the fourth data I/O pin  112 D. 
       FIG. 3  shows a block diagram illustrating a configuration of a spare die  120  corresponding to any one of the spare dies included in the memory medium  100  of the semiconductor memory system  10  shown in  FIG. 1 . That is, each of the first to m th  spare dies  120 - 1 , . . . , and  120 - m  may have substantially the same configuration as the spare die  120  illustrated in  FIG. 3 . In  FIG. 3 , an MRS of the memory die  120  is omitted. Referring to  FIG. 3 , the spare die  120  may include a spare storage region  121  and a plurality of data I/O pins, for example, first to fourth data I/O pins DQ 0 , DQ 1 , DQ 2 , and DQ 3  (also, denoted by ‘ 122 A,’ ‘ 122 B,’ ‘ 122 C,’ and ‘ 122 D’). The spare storage region  121  may be realized to have substantially the same configuration as the memory storage region  111  of the memory die  110  illustrated in  FIG. 2 . The spare storage region  121  may be divided into a plurality of spare regions, for example, first to fourth spare regions  121 A,  1218 ,  121 C, and  121 D. The spare die  120  may further include a data I/O logic circuit  123  functioning as an interface circuit between the spare regions  121 A,  121 B,  121 C, and  121 D and the data I/O pins  122 A,  122 B,  122 C, and  122 D. The number of spare regions  121 A,  121 B,  121 C, and  121 D may be equal to the number of the data I/O pins  122 A,  122 B,  122 C, and  122 D, for an embodiment. 
     In the present embodiment, the first to fourth spare regions  121 A,  121 B,  121 C, and  121 D may be distinguished from each other according to the first to fourth data I/O pins  122 A,  122 B,  122 C, and  122 D that execute data communication with the first to fourth memory regions  121 A,  121 B,  121 C, and  121 D. In an embodiment, the first spare region  121 A may be defined as a region that receives or outputs data through the first data I/O pin  122 A. The second memory region  121 B may be defined as a region that receives or outputs data through the second data I/O pin  122 B. The third memory region  121 C may be defined as a region that receives or outputs data through the third data I/O pin  122 C, and the fourth memory region  121 D may be defined as a region that receives or outputs data through the fourth data I/O pin  122 D. The first spare region  121 A, the second spare region  121 B, the third spare region  121 C, and the fourth spare region  121 D of the spare die  120  may be designed to have substantially the same configuration as the first memory region  111 A, the second memory region  111 B, the third memory region  111 C, and the fourth memory region  111 D, respectively, of the memory die  110 . 
       FIGS. 4 and 5  show schematic views illustrating a method of repairing the semiconductor memory system  10  shown in  FIG. 1  in units of data I/O pins. The present embodiment is described as having three memory dies (i.e., the first to third memory dies  110 - 1 ,  110 - 2 , and  110 - 3 ) and one spare die (i.e., the spare die  120  shown in  FIG. 3 ). For other embodiments, semiconductor memory system different number of memory dies and spare dies. In the present embodiment, each of the first to third memory dies  110 - 1 ,  110 - 2 , and  110 - 3  may have four data I/O pins DQ 0 , DQ 1 , DQ 2 , and DQ 3 . Each of the first to third memory dies  110 - 1 ,  110 - 2 , and  110 - 3 , for example, may have substantially the same configuration as the memory die  110  described with reference to  FIG. 2 . In addition, the spare die  120  may have substantially the same configuration as the spare die  120  described with reference to  FIG. 3 . 
     Referring to  FIG. 4 , if the fourth data I/O pin DQ 3  among the data I/O pins DQ 0 , DQ 1 , DQ 2 , and DQ 3  of the first memory die  110 - 1  is discriminated as an abnormal data I/O pin (denoted by the word ‘FAULT’) by the data I/O (DQ) pin repair control circuit  230  while the data stored in each of the first to third memory dies  110 - 1 ,  110 - 2 , and  110 - 3  are read out, then a repair process may be performed to replace the fourth data I/O pin DQ 3  of the first memory die  110 - 1  with a first data I/O pin DQ 0  of the spare die  120  in units of data I/O pins. That is, the first to third data I/O pins DQ 0 , DQ 1 , and DQ 2  of the first memory die  110 - 1  having the fourth data I/O pin DQ 3  malfunctioning is not affected by the repair process. If the repair process for the fourth data I/O pin DQ 3  of the first memory die  110 - 1  is performed, then data is transmitted through the first data I/O pin DQ 0  of the spare die  120  instead of through the fourth data I/O pin DQ 3  of the first memory die  110 - 1 . 
     Referring to  FIG. 5 , it is assumed that the second data I/O pin DQ 1  among the data I/O pins DQ 0 , DQ 1 , DQ 2 , and DQ 3  of the third memory die  110 - 3  is discriminated as an abnormal data I/O pin (denoted by the word ‘FAULT’) by the data I/O (DQ) pin repair control circuit  230  after the repair process is performed to replace the fourth data I/O pin DQ 3  of the first memory die  110 - 1  with the first data I/O pin DQ 0  of the spare die  120  in units of data I/o pins. In such a case, another repair process may be performed to replace the second data I/O pin DQ 1  (corresponding to an abnormal data I/O pin) of the third memory die  110 - 3  with any one of the remaining data I/O pins of the spare die  120 , for example, with a second data I/O pin DQ 1  of the spare die  120  in units of data I/O pins. That is, the data I/O pins DQ 0 , DQ 2 , and DQ 3  of the third memory die  110 - 3  is not affected by the repair process for the second data I/O pin DQ 1  of the third memory die  110 - 3 . If the repair process for the second data I/O pin DQ 1  of the third memory die  110 - 3  is performed, then data may be transmitted through the second data I/O pin DQ 1  of the spare die  120  instead of through the second data I/O pin DQ 1  of the third memory die  110 - 3 . 
     Considering  FIGS. 4 and 5  together, the first data I/O pin DQ 0  of the spare die  120  replaces the abnormal data I/O pin DQ 3  of the first memory die  110 - 1  in a first repair process (see  FIG. 4 ). During a later-performed second repair process, the second data I/O pin DQ 1  of the spare die  120  replaces the abnormal data I/O pin DQ 1  of the third memory die  110 - 3  (see  FIG. 5 ). As shown, the same spare die  120  is used on a pin-by-pin basis to repair two different memory dies, namely, the first die  110 - 1  and the third die  110 - 3 . In another embodiment, two different pins on the spare die  120  are used to repair two different abnormal data I/O pins one the same memory die at different times. 
     After the repair process is performed in units of data I/O pins, data transmission through the abnormal data I/O pins of the memory dies is no longer executed. Instead, data transmission through the replaced data I/O pins of the spare die  120  is executed. For the successful execution of the repair process, data migration may be achieved such that data inputted to the abnormal data I/O pins of the memory dies are transmitted through the replaced data I/O pins of the spare die  120 . Since the data stored in the memory dies have a form of a codeword generated by the ECC encoding operation, it may be necessary to perform the ECC decoding operation and the ECC encoding operation again using the ECC circuit  220  for the data migration. 
       FIG. 6  shows a flowchart illustrating a method of repairing the semiconductor memory system  10  in units of data I/O pins, according to an embodiment of the present disclosure.  FIG. 7  shows a schematic view illustrating a process for changing data in a mode register set (MRS) during a repair process of the semiconductor memory system  10 , according an embodiment of the present disclosure. In addition,  FIGS. 8 and 9  show block diagrams illustrating data migration during a repair process of the semiconductor memory system  10  performed in units of data I/O pins. Referring to  FIG. 6 , set values of the mode register set (MRS) of the spare die  120  may be changed to activate a first data I/O pin DQ 0  of the spare die  120  (operation  310 ). As a result, data may be stored in a storage region of the spare die  120  through the first data I/O pin DQ 0  of the spare die  120 . 
     As illustrated in  FIG. 7 , the mode register set (MRS) may be configured to have a four-bit code which is capable of activating or deactivating the data I/O pins. Each of the MRSs included in the spare die  120  and the memory dies  110 - 1 ,  110 - 2 , and  110 - 3  may be designed to have substantially the same configuration as the MRS illustrated in  FIG. 7 . A first bit A 0  of the four-bit code may be used to activate or deactivate the first data I/O pin DQ 0 . For example, the first data I/O pin DQ 0  may be deactivated if the first bit A 0  has a logic level of “0”, and the first data I/O pin DQ 0  may be activated if the first bit A 0  has a logic level of “1.” A second bit A 1  of the four-bit code may be used to activate or deactivate the second data I/O pin DQ 1 . For example, the second data I/O pin DQ 1  may be deactivated if the second bit A 1  has a logic level of “0,” and the second data I/O pin DQ 1  may be activated if the second bit A 1  has a logic level of “1.” A third bit A 2  of the four-bit code may be used to activate or deactivate the third data I/O pin DQ 2 . For example, the third data I/O pin DQ 2  may be deactivated if the third bit A 2  has a logic level of “0,” and the third data I/O pin DQ 2  may be activated if the third bit A 2  has a logic level of “1.” A fourth bit A 3  of the four-bit code may be used to activate or deactivate the fourth data I/O pin DQ 3 . For example, the fourth data I/O pin DQ 3  may be deactivated if the fourth bit A 3  has a logic level of “0,” and the fourth data I/O pin DQ 3  may be activated if the fourth bit A 3  has a logic level of “1.” 
     All of the data I/O pins DQ 0  to DQ 3  of the spare die  120  may be deactivated before a repair process is performed using the spare die  120 . That is, all of the bits constituting the four-bit code of the MRS included in the spare die  120  may be set to have a logic level of “0” before a repair process is performed using the spare die  120 . Thus, in order that the data migration for the repair process is achieved in units of data I/O pins, a logic level of the first bit A 0  of the four-bit code of the MRS included in the spare die  120  may be firstly changed from “0” to “1” to activate the first data I/O pin DQ 0 . If data transmission through the first data I/O pin DQ 0  of the spare die  120  is allowed by changing the set value of the MRS included in the spare die  120 , the data migration from at least one of the memory dies  110 - 1 ,  110 - 2 , and  110 - 3  to the spare die  120  may be executed. 
     As illustrated in  FIG. 8 , during the repair process performed in units of data I/O pins, the data migration may be achieved by moving data in a fourth memory region  111 - 1 D transmitted through a fourth data I/O pin (DQ 3 )  112 - 1 D (corresponding to an abnormal data I/O pin that malfunctions) of the first memory die  110 - 1  to the first spare region  121 A of the spare die  120 , controlled by the first data I/O pin (DQ 0 )  122 A. The data stored in the fourth memory region  111 - 1 D may be comprised of symbols corresponding to units of the ECC operation. In such a case, some of the symbols stored in the fourth memory region  111 - 1 D may be encoded by an ECC encoding operation together with symbols stored in the other memory regions  111 - 1 A,  111 - 1 B and  111 - 1 C included in the first memory die  110 - 1 . Thus, before the data migration is executed, all of the data stored in all of the memory regions  111 - 1 A,  111 - 1 B,  111 - 1 C, and  111 - 1 D included in the first memory die  110 - 1  may be decoded by an ECC decoding operation and the ECC decoded data may be encoded by an ECC encoding operation. Before the ECC decoding operation and the ECC encoding operation for all of the data in the first memory die  110 - 1  are performed, an address may be set to be ‘0’ (operation  320  of  FIG. 6 ). The address of ‘0’ may denote a first address of a memory storage region in the first memory die  110 - 1  having the fourth data I/O pin  112 - 1 D that malfunctions. 
     After reading the data having the address of ‘0’ in the first memory die  110 - 1 , an ECC decoding operation of the read data may be performed (operation  330  of  FIG. 6 ). During the operation  330 , a parity bit included in the data having the address of ‘0’ and a codeword form may be removed to provide an original read data, and the data having the address of ‘0’ may be corrected within the range of an error correction capability of the ECC circuit  220  if an erroneous bit in included in the data having the address of ‘0.’ After the ECC decoding operation of the read data is performed, an arbitration process may be performed to assign the fourth data I/O pin (DQ 3 )  112 - 1 D (corresponding to an abnormal data I/O pin) of the first memory die  110 - 1  to the first data I/O pin DQ 0  ( 122 A) (corresponding to an activated data I/O pin) of the spare die  120  (operation  340  of  FIG. 6 ). Next, an ECC encoding operation may be performed to encode the ECC decoded data, and a write operation may be performed to store the ECC encoded data to the spare die  120  (operation  350  of  FIG. 6 ). In such a case, the ECC encoding operation may be performed in units of data stored in the first to fourth memory regions  111 - 1 A,  111 - 1 B,  111 - 1 C, and  111 - 1 D of the first memory die  110 - 1 . That is, the ECC encoding operation of the data stored in the first memory region  111 - 1 A, the ECC encoding operation of the data stored in the second memory region  111 - 1 B, the ECC encoding operation of the data stored in the third memory region  111 - 1 C, and the ECC encoding operation of the data stored in the fourth memory region  111 - 1 D may be separately performed by each respective memory region. 
     After the ECC encoding operations are performed, the ECC encoded data other than the data stored in the fourth memory region  111 - 1 D may be written to the first memory region  111 - 1 A, the second memory region  111 - 1 B, and the third memory region  111 - 1 C during the write operation. Accordingly, the data written to the first memory region  111 - 1 A may be transmitted through the first data I/O pin (DQ 0 )  112 - 1 A of the first memory die  110 - 1 . The data written to the second memory region  111 - 1 B may be transmitted through the second data I/O pin (DQ 1 )  112 - 1 B of the first memory die  110 - 1 . The data written to the third memory region  111 - 1 C may be transmitted through the third data I/O pin (DQ 2 )  112 - 1 C of the first memory die  110 - 1 . The data stored in the fourth memory region  111 - 1 D may be written to the first spare region  121 A of the spare die  120  during the write operation. The data written to the first spare region  121 A may be transmitted through the first data I/O pin (DQ 0 )  122 A of the spare die  120 . 
     After the ECC encoding operation and the write operation for the data having the address of ‘0’ are performed as operation  350 , whether a current address (i.e., the address of ‘0’) is a final address may be discriminated (operation  360  of  FIG. 6 ). If the current address is not a final address, then the address may increase by one (operation  370  of  FIG. 6 ). In such a case, the operations  330  to  360  for the data having the increased address may be sequentially executed again. If the address is a final address, then the MRS of the first memory die  110 - 1  having the fourth data I/O pin  112 - 1 D corresponding to an abnormal data I/O pin may be set to deactivate the fourth data I/O pin  112 - 1 D (operation  380  of  FIG. 6 ). Specifically, as described with reference to  FIG. 7 , the fourth data I/O pin  112 - 1 D may be deactivated by changing a logic level of a fourth bit A 3  of an MRS  114 - 1  included in the first memory die  110 - 1  from ‘0’ to ‘1.’ As such, data transmission through the fourth data I/O pin  112 - 1 D may be interrupted by changing a set value of the MRS  114 - 1  included in the first memory die  110 - 1 . 
     As described with reference to  FIG. 5 , if the second data I/O pin (DQ 1 )  112 - 3 B among the data I/O pins  112 - 3 A,  112 - 3 B,  112 - 3 C, and  112 - 3 D of the third memory die  110 - 3  is discriminated as an abnormal data I/O pin (denoted by the word ‘FAULT’) by the data I/O (DQ) pin repair control circuit  230  after the first data I/O pin  122 A of the spare die  120  is used in the previous repair process performed in units of data I/O pins, then an additional repair process for third memory die  110 - 3  may be performed in units of data I/O pins. In such a case, the second data pin (DQ 1 )  112 - 3 B corresponding to an abnormal data I/O pin of the third memory die  110 - 3  may be replaced with any one (e.g., the second data I/O pin  122 B) of the remaining data I/O pins of the spare die  120 . Specifically, the second data I/O pin  122 B of the spare die  120  may be activated by changing a set value of the MRS  124  of the spare die  120 . That is, the second data I/O pin  122 B of the spare die  120  may be activated by changing a logic level of the second bit A 1  of a four-bit code of the MRS  124  included in the spare die  120  from ‘0’ to ‘1.’ 
     As illustrated in  FIG. 9 , during the repair process for the third memory die  110 - 3  performed in units of data I/O pins, the data migration may be achieved by moving data in the second memory region  111 - 3 B transmitted through the second data I/O pin (DQ 1 )  112 - 3 B (corresponding to an abnormal data I/O pin that malfunctions) of the third memory die  110 - 3  to the second spare region  121 B controlled by the second data I/O pin (DQ 1 )  122 B of the spare die  120 . In such a case, the data migration may be achieved in substantially the same way as described with reference to  FIG. 8 . That is, before the data migration is executed, ECC decoding operations of all of the data stored in all of the memory regions  111 - 3 A,  111 - 3 B,  111 - 3 C, and  111 - 3 D included in the third memory die  110 - 3  may be performed by increasing the address of the data, and the ECC decoded data may be encoded by ECC encoding operations. The ECC encoding operations of the memory regions  111 - 3 A,  111 - 3 B,  111 - 3 C, and  111 - 3 D may be separately performed by each respective memory region. 
     After the ECC decoding operations are performed, an arbitration process may be performed to assign the second data I/O pin (DQ 1 )  112 - 3 B (corresponding to an abnormal data I/O pin) of the third memory die  110 - 3  to the second data I/O pin DQ 1  ( 122 B) (corresponding to an activated data I/O pin) of the spare die  120  before the ECC encoding operations are performed. Next, the ECC encoding operation for the ECC decoded data may be performed, and the ECC encoded data may be written to the spare die  120  by a write operation. Accordingly, the data stored in the second memory region  111 - 3 B of the third memory die  110 - 3  may be written to the second spare region  121 B of the spare die  120 . If the data migration for all addresses is finished, then the second data I/O pin (DQ 1 )  112 - 3 B corresponding to an abnormal data I/O pin of the third memory die  110 - 3  may be deactivated by changing a logic level of the second bit A 1  of the four-bit code of the MRS  114 - 3  included in the third memory die  110 - 3  from ‘1’ to ‘0.’ 
     Embodiments disclosed herein have been described for illustrative purposes. Those of ordinary skill in the art will appreciate that various modifications, additions, and substitutions are possible for presented embodiments without departing from the scope and spirit of the present disclosure as disclosed in the accompanying claims.