Patent Publication Number: US-11665799-B2

Title: Dimming mode detection circuit, dimming mode detection method, non-dimming mode detection circuit and LED lighting system

Description:
RELATED APPLICATIONS 
     This application is a continuation of the following application, U.S. patent application Ser. No. 17/209,521, filed on Mar. 23, 2021, and which is hereby incorporated by reference as if it is set forth in full in this specification, and which also claims the benefit of Chinese Patent Application No. 202010256638.7, filed on Apr. 2, 2020, which is incorporated herein by reference in its entirety. 
    
    
     FIELD OF THE INVENTION 
     The present invention generally relates to the field of power electronics, and more particularly to dimming mode detection circuits and methods, non-dimming mode detection circuits, and LED lighting systems. 
     BACKGROUND 
     A switched-mode power supply (SMPS), or a “switching” power supply, can include a power stage circuit and a control circuit. When there is an input voltage, the control circuit can consider internal parameters and external load changes, and may regulate the on/off times of the switch system in the power stage circuit. Switching power supplies have a wide variety of applications in modern electronics. For example, switching power supplies can be used to drive light-emitting diode (LED) loads. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG.  1    is a waveform diagram of an example operation of the lighting system with a trailing edge dimmer. 
         FIG.  2    is a waveform diagram of example operation of a trailing edge detection circuit, in accordance with embodiments of the preset invention. 
         FIG.  3    is a schematic block diagram of an example LED lighting system, in accordance with embodiments of the preset invention. 
         FIG.  4    is a schematic block diagram of a first example dimming mode detection circuit, in accordance with embodiments of the preset invention. 
         FIG.  5    is a schematic block diagram of a second example dimming mode detection circuit, in accordance with embodiments of the preset invention. 
         FIG.  6    is a schematic block diagram of an example leading edge detection circuit, in accordance with embodiments of the preset invention. 
         FIG.  7    is a waveform diagram of an example operation of the leading edge detection circuit in  FIG.  6   , in accordance with embodiments of the preset invention. 
         FIG.  8    is a schematic block diagram of an example trailing edge detection circuit, in accordance with embodiments of the preset invention. 
         FIG.  9    is a waveform diagram of an example operation of the trailing edge detection circuit in  FIG.  8   , in accordance with embodiments of the preset invention. 
         FIG.  10    is a schematic block diagram of an example mode lock module and an example fourth logic module, in accordance with embodiments of the preset invention. 
         FIG.  11    is a waveform diagram of an example operation of the mode lock module and the fourth logic module in  FIG.  10   , in accordance with embodiments of the preset invention. 
         FIG.  12    is a schematic block diagram of an example non-dimming mode detection circuit, in accordance with embodiments of the preset invention. 
     
    
    
     DETAILED DESCRIPTION 
     Reference may now be made in detail to particular embodiments of the invention, examples of which are illustrated in the accompanying drawings. While the invention may be described in conjunction with the preferred embodiments, it may be understood that they are not intended to limit the invention to these embodiments. On the contrary, the invention is intended to cover alternatives, modifications and equivalents that may be included within the spirit and scope of the invention as defined by the appended claims. Furthermore, in the following detailed description of the present invention, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it may be readily apparent to one skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known methods, procedures, processes, components, structures, and circuits have not been described in detail so as not to unnecessarily obscure aspects of the present invention. 
     Because light-emitting diode (LED) has characteristics of high efficiency and energy saving, LED lighting has been widely used to replace traditional incandescent lamps and fluorescent lamps. For LED lighting systems with a triode alternating current (TRIAC) dimmer, three common dimming methods are utilized: leading edge dimming mode, trailing edge dimming mode, and non-dimming mode. Due to characteristics of the TRIAC dimmer itself, a holding current is a minimum main current required to keep the TRIAC dimmer in an on-state. Therefore, a bleeder circuit can be suitable for a TRIAC dimmer in LED lighting systems. When a current provided in the main loop is less than the holding current of the TRIAC dimmer, the bleeder circuit can provide additional current to maintain the on-state of the TRIAC dimmer. Due to different operation principles of the three dimming modes, the required bleeder current in the three modes is different, such that the operation state of the bleeder circuit is different. If the dimming mode is detected, the operation state of the bleeder circuit can be controlled, so a detection method for the dimming mode is important. 
     A typical lighting system includes a rectifier which receives an alternating current (AC) input voltage to generate a bus voltage along the DC bus to a DC/DC power converter. The DC/DC power converter outputs a corresponding DC voltage for powering a light source. For example, the light source can be one or more LEDs. The typical lighting system can also include a dimmer which connects between the AC input voltage and the rectifier and provides dimming capability by chopping the AC input voltage. Typically, the detection method for the dimming mode is sampling of the bus voltage. When a continuous fast rising edge in the bus voltage is detected, the dimming mode is configured as a leading edge dimming mode. When a continuous fast falling edge in the bus voltage is detected, the dimming mode is configured as a trailing edge dimming mode. If there is neither a continuous fast rising edge nor a continuous fast falling edge in the bus voltage, the dimming mode is configured as a non-dimming mode. 
     Referring now to  FIG.  1   , shown is a waveform diagram of an example operation of the lighting system with a trailing edge dimmer. In this example, when the lighting system operates at the trailing edge dimming mode, the bus voltage may not immediately become zero when the trailing edge dimmer is performed, so the trailing edge dimmer may not be turned off immediately until the bus voltage drops to zero. Therefore, the detection method for the leading edge dimming mode may be inaccurate by detecting the rapid falling edge in the bus voltage when the leading edge dimmer operates. When a conduction angle of the trailing edge dimmer is relatively large, the falling edge of the bus voltage is relatively slow; that is, the falling slope is small, and the fast falling edge cannot be detected. In this way, the lighting system can trigger the non-dimming mode by mistake, resulting in error control of the bleeder circuit. 
     Particular embodiments provide a dimming mode detection circuit for an LED lighting system. The LED lighting system can receive alternating current input voltage Vac, and can generate a bus voltage to drive an LED load. The dimming mode detection circuit can include a leading trailing edge detection circuit to generate a leading edge detection signal to determine whether the LED lighting system operates in a leading edge dimming mode, and a trailing edge detection circuit to generate a trailing edge detection signal in accordance with a time length of a first interval of a first voltage representative of the bus voltage during two adjacent sine half-wave cycles, in order to determine whether the LED lighting system operates in a trailing edge dimming mode. 
     In addition, starting and end points of the first interval can be within two adjacent sine half-wave cycles. Further, when the leading edge detection signal is active, the LED lighting system may operate in the leading edge dimming mode. Also, when the time length of the first interval is greater than a first reference time during N (e.g., N is a positive integer) consecutive sine half-wave cycles and a first voltage does not have a fast rising edge, the LED lighting system may operate in the trailing edge dimming mode. In addition, when the time length of the first interval is greater than a first reference time during N consecutive sine half-wave cycles and the first voltage does not have a fast rising edge, the trailing edge detection signal can be active, and the LED lighting system may operate in the trailing edge dimming mode when the trailing edge detection signal is active and the leading edge detection signal is inactive. 
     In addition, when the LED lighting system neither operates in the leading edge dimming mode, nor in the trailing edge dimming mode, the LED lighting system may operate in a non-dimming mode. Also, when the trailing edge detection signal and the leading edge detection signal are detected to be inactive during N consecutive sine half-wave cycles, the LED lighting system may operate in a non-dimming mode, where N is a positive integer. Further, a starting point of the first interval can be configured as a falling phase of the first voltage during a current sine half-wave cycle, and an end point of the first interval may be configured as a rising phase of the first voltage during a next sine half-wave cycle. Further, a voltage of the first voltage at the starting point of the first interval can be less than a voltage of the first voltage at the end point of the first interval. 
     In addition, if the voltages of the first voltage at the starting and end points of the first interval are both small, the difference between the time length of the first interval and the time length of the first interval in the non-dimming mode can be relatively small, and it may be difficult to distinguish between the trailing edge dimming mode and the non-dimming mode. If the voltages of the first voltage at the starting and end points of the first interval are both relatively large, the dimmer may not start to operate at the starting point of the first interval. In this case, the trailing edge dimming mode and the non-dimming mode may not be distinguished. In particular embodiments, the voltage at the of the starting point of the first interval can be smaller than the voltage of the first voltage at the end point of the first interval. 
     In addition, a moment when the first voltage drops to a first reference voltage during a current sine half-wave cycle is the starting point of the first interval, and a moment when the first voltage rises to a second reference voltage during a next sine half-wave period can be the end point of the first interval, where the first reference voltage is less than the second reference voltage. Further, the first reference voltage may not be less than a first time, a starting point of the first time can be a moment when the first voltage drops to the first reference voltage in a current sine half-wave cycle in an non-dimming mode, and an end point of the first time may be a moment when the first voltage rises to the second reference voltage in a next sine half-wave cycle in the non-dimming mode. 
     In addition, when the first voltage rises to a third reference voltage, and then rises to a fourth reference voltage rapidly during N consecutive sine half-wave cycles, the leading edge detection signal may be active, and the LED lighting system operates in the leading edge dimming mode. Further, when a second time is less than a second reference time during N consecutive sine half-wave cycles, the leading edge detection signal can be active, where the second time is configured as a time length during which the first voltage rises from the third reference voltage to the fourth reference voltage, and N is a positive integer. 
     Particular embodiments may provide a non-dimming mode detection circuit for the LED lighting system. The non-dimming mode detection circuit can detect a time length of a first interval of a first voltage representative of the bus voltage during two adjacent sine half-wave cycles, in order to determine whether the LED lighting system operates in a non-dimming mode. Further, starting and end points of the first interval can be within two adjacent sine half-wave cycles. In addition, the non-dimming mode detection circuit can generate a first detection signal. For example, when a time length of the first interval is not greater than a first reference time during N consecutive sine half-wave cycles, the first detection signal may be active, and the LED lighting system operates in the non-dimming mode, where N is a positive integer. 
     In particular embodiments, operation of the dimming mode detection circuit can include, when a continuous fast rising edge of the first voltage is detected, the LED lighting system operates in the leading edge dimming mode. In addition, when the time length of the first interval is greater than the first reference time, and the continuous fast rising edge of the first voltage cannot be detected, the LED lighting system operates in the trailing edge dimming mode. Further, when the LED lighting system neither operates in the leading edge dimming mode nor in the trailing edge dimming mode, the LED lighting system operates in non-dimming mode, such that the LED lighting system has no dimmer or the LED lighting system has a dimmer that does not work. In certain embodiments, the dimmer can be configured as a silicon-controlled dimmer. In this way, particular embodiments adopt different methods in order to determine the leading edge dimming mode and the trailing edge dimming mode. The leading edge detection circuit can detect a fast rising edge of the first voltage, in order to determine the leading edge dimming mode. 
     Referring now to  FIG.  2   , shown is a waveform diagram of example operation of a trailing edge detection circuit, in accordance with embodiments of the preset invention. In the current sine half-wave cycle, the moment when voltage V 1  drops to reference voltage Vref 1  is the starting point of the first interval, and in the next sine half-wave cycle, the moment when voltage V 1  rises to reference voltage Vref 2  is the end point of the first interval, and the time length of the first interval is t. When time length t of the first interval is greater than the first reference time, and the leading edge detection circuit determines that the LED lighting system does not operate in the leading edge dimming mode, the LED lighting system can be determined to operate in the trailing edge dimming mode. Here, the first reference time is not less than a first time, a starting point of the first time is a moment when the first voltage drops to the first reference voltage in a current sine half-wave cycle in a non-dimming mode, and an end point of the first time is a moment when the first voltage rises to the second reference voltage in a next sine half-wave cycle in the non-dimming mode. To determine whether the LED lighting system operates in the trailing edge dimming mode, the dimming mode detection circuit can detect whether time length t of the first interval is greater than the first reference time, also detect whether the LED lighting system operates in the leading edge dimming mode, because in the leading edge dimming mode time length t of the first interval is also greater than the first reference time. 
     In some cases, it may not be necessary to determine whether the LED lighting system operates in the trailing edge dimming mode or the leading edge dimming mode, but only whether the LED lighting system operates in the non-dimming mode. Since the time length of the first interval can be greater than the first reference time in the trailing edge dimming mode and the leading edge dimming mode, the operating principle of the non-dimming mode detection circuit can determine the non-dimming mode based on the time length of the first interval. Further, when the time length of the first interval is greater than the first reference time, the LED lighting system may operate in the non-dimming mode. In particular embodiments, the dimming mode detection circuit can adopt different methods to detect the leading edge dimming mode and the trailing edge dimming mode, can accurately distinguish three different modes of the dimmer, and may improve the compatibility of the LED lighting system for the dimmer and the detection accuracy of the trailing edge dimming mode. This method can substantially avoid the problem of triggering the non-dimming mode by mistake, and error control of the bleeder circuit caused by factors, such as the rapid falling edge of the first voltage being not detected when the LED lighting system operates at the trailing edge dimming mode. In this way, strong versatility that is not limited by the operation method of the dimmer, accurate detection, and suitability for high-efficiency LED dimming systems can be achieved. 
     Referring now to  FIG.  3   , shown is a schematic block diagram of an example LED lighting system, in accordance with embodiments of the preset invention. This particular example LED lighting system can include a rectifier bridge, an LED drive circuit, a dimming mode detection circuit, and a bleeder circuit. The rectifier bridge can rectify AC input voltage Vac and output a bus voltage for powering an LED load. The LED drive circuit can provide a current to the LED load. The dimming mode detection circuit can detect the dimming mode of the LED lighting system, and distinguish the operation state of a silicon-controlled dimmer in the LED lighting system. The bleeder circuit can be controlled according to the dimming mode. 
     In one embodiment, the dimming mode detection circuit can receive voltage V 1  representative of the bus voltage, and determine the dimming mode of the LED lighting system according to voltage V 1 . When the dimming mode detection circuit determines that the LED lighting system operates in a leading edge dimming mode or a trailing edge dimming mode, the bleeder circuit can be controlled to provide a bleeder current required to maintain the normal operation of the silicon-controlled dimmer. When the dimming mode detection circuit determines that the LED lighting system operates in a non-dimming mode, that is, the LED lighting system has no silicon-controlled dimmer or the silicon-controlled dimmer in the LED lighting system is disabled, the bleeder circuit may not operate, in order to reduce power loss and improve efficiency. Here, voltage V 1  can characterize an output voltage of the rectifier bridge, and may be, e.g., the output voltage of the rectifier bridge or its divided voltage. 
     Referring now to  FIG.  4   , shown is a schematic block diagram of a first example dimming mode detection circuit, in accordance with embodiments of the preset invention. This example dimming mode detection circuit can include trailing edge detection circuit  1  and leading edge detection circuit  2 . Trailing edge detection circuit  1  can include comparison module  11  and control module  12 . Comparison module  11  can generate processed signal V 11  and processed signal V 12  in accordance with reference voltage Vref 1 , reference voltage Vref 2 , and voltage V 1 . Control module  12  can generate trailing edge detection signal ‘trail’ according to processed signals V 11  and V 12 , and may generate trailing edge mode determination signal ‘trail mode’ according to trailing edge detection signal ‘trail’ and leading edge detection signal ‘lead’ generated by leading edge detection circuit  2 . The trailing edge dimming mode of the LED lighting system can be determined by trailing mode determination signal ‘trail mode’. For example, reference voltage Vref 1  is less than reference voltage Vref 2 . In other embodiments, reference voltage Vref 1  can be equal to or greater than reference voltage Vref 2 . 
     Control module  12  can include logic module  121 , timing module  122 , judgment and counting module  123 , and logic module  124 . Logic module  121  can receive processed signal V 11  and generate an output signal after logic processed. Timing module  122  can receive the output signal of logic module  121 , and may generate an output signal. Judgment and counting module  123  can receive the output signal of timing module  122  and processed signal V 12 , and may generate trailing edge detection signal ‘trail’. Logic module  124  can generate trailing edge mode determination signal ‘trail mode’ according to trailing edge detection signal ‘trail’ and leading edge detection signal ‘lead’. Here, the timing time of timing module  122  is the first reference time. In some cases, control module  12  can also include delay module  125 . Delay module  125  can receive processed signal V 12 , and may output the delayed version of processed signal V 12  to judgment and counting module  123 . The sum of the delay time of delay module  125  and the timing time of timing module  122  is first reference time. The addition of delay module  125  can help reduce the interference of processed signal V 12 . 
     Leading edge detection circuit  2  can include comparison module  21  and control module  22 . Comparison module  21  can generate processed signal V 13  and processed signal V 14  in accordance with reference voltage Vref 3 , reference voltage Vref 4 , and voltage V 1 . Control module  22  can generate leading edge detection signal ‘lead’ according to processed signals V 13  and V 14 , and may generate leading edge mode determination signal ‘lead mode’ according to leading edge detection signal ‘lead’. The leading edge dimming mode of the LED lighting system can be determined by leading edge mode determination signal ‘lead mode’. Here, e.g., reference voltage Vref 3  is less than reference voltage Vref 4 . 
     For example, control module  22  can include delay circuit  221 , judgment and counting module  222 , and logic module  223 . Delay circuit  221  can receive processed signal V 13 , and may output a delayed version of processed signal V 13 . Judgment and counting module  222  can receive the delayed processed signal of V 13  and processed signal V 14 , and may output leading edge detection signal ‘lead’. Logic module  223  can receive leading edge detection signal ‘lead’ and output leading edge mode determination signal ‘lead mode’. The delay time of delay circuit  221  is a second reference time. It should be understood that “module” as used herein can include hardware circuitry. 
     The dimming mode detection circuit can also include fourth logic circuit  3  for generating non-dimming mode detection signal ‘AC mode’ according to count signal ‘count’, leading edge detection signal ‘lead’, and trailing edge detection signal ‘trail’. The non-dimming mode of the LED lighting system can be determined by non-dimming mode detection signal ‘AC mode’. Here, count signal ‘count’ can represent the number of sine half-wave cycles that have passed. In some cases, comparison modules  11  and  12  can be the same module, in order to reduce the number of devices. In addition, reference voltage Vref 1  can be equal to reference voltage Vref 3 , and reference voltage Vref 2  may be equal to reference voltage Vref 4 . 
     Referring now to  FIG.  5   , shown is a schematic block diagram of a second example dimming mode detection circuit, in accordance with embodiments of the preset invention. In this particular example, the dimming mode detection circuit can also include mode lock module  4 . Mode lock module  4  can include comparison module  41 , counting module  42 , and logic module  43 . Comparison module  41  can receive voltage V 1 , and may generate processed signal V 15 . Counting module  42  can receive processed signal V 15 , and may generate an output signal. Logic module  43  can receive the output signal of counting module  42 , and may generate mode lock signal ‘mode lock’. When the dimming mode of the LED lighting system is determined, mode lock signal ‘mode lock’ can be active, and mode lock module  4  can lock the detected dimming mode in the current period (e.g., leading edge dimming mode or trailing edge dimming mode or non-dimming mode), such that dimming mode detection circuit may not continue to detect the dimming mode of the LED lighting system. The addition of mode lock module  4  can prevent undesired factors, such as mains jitter, from making the detected dimming mode abnormal. 
     In this example, logic module  223  in leading edge detection circuit  2  can generate leading edge mode determination signal ‘lead mode’ according to leading edge detection signal ‘lead’ and mode lock signal ‘mode lock’. Logic module  124  in trailing edge detection circuit  1  can generate trailing edge mode determination signal ‘trail mode’ according to leading edge detection signal ‘lead’, trailing edge detection signal ‘trail’, and mode lock signal ‘mode lock’. Logic module  3  can generates anon-dimming mode detection signal ‘AC mode’ according to the output signal of counting module  42 , leading edge detection signal ‘lead’, and trailing edge detection signal ‘trail’. 
     Referring now to  FIG.  6   , shown is a schematic block diagram of an example leading edge detection circuit, in accordance with embodiments of the preset invention. In this particular example, leading edge detection circuit  2  can include comparison module  21  and control module  22 . Comparison module  21  can include comparators COMP 3  and COMP 4 . Comparator COMP 3  can receive voltage V 1  at a non-inverting input terminal, and reference voltage Vref 3  at an inverting input terminal, and may generate processed signal V 13  at an output terminal. Comparator COMP 4  can receive voltage V 1  at a non-inverting input terminal, and reference voltage Vref 4  at an inverting input terminal, and may generate processed signal V 14  at an output terminal. 
     Judgment and counting module  222  can detect that voltage V 1  has a fast rising edge during N consecutive half-wave cycles, and then may generate the active leading detection signal. In this way, the dimming mode of the LED lighting system can be determined as the leading edge dimming mode. In this particular example, N is 3. Further, since reference voltage Vref 3  is less than reference voltage Vref 4 , comparator COMP 3  can generate an active high level. When processed signal V 13  is at a high level and is delayed by the reference time, processed signal V 14  is already at a high level, it can be considered that the time that voltage V 1  rises from reference voltage Vref 3  to reference voltage Vref 4  is very short, and voltage V 1  exhibits a fast rising edge. 
     Judgment and counting module  222  can include N D flip-flops. An input terminal of the first D flip-flop can receive processed signal V 14 , and an input terminal of each of the remaining N−1 D flip-flops can receive a signal generated by an output signal of the previous D flip-flop being logically AND&#39;ed with processed signal V 14 . Trigger terminals of the N D flip-flops may all receive the output signal of delay circuit  221 , and an output signal of the last D flip-flop is leading edge detection signal ‘lead’. In this particular example, judgment and counting module  222  can include three D flip-flops. When the leading edge detection circuit detects that voltage V 1  may have a fast rising edge during three consecutive half-wave cycles, and leading edge detection signal ‘lead’ can be a high level. Logic module  223  can include an RS flip-flop. A set terminal of the RS flip-flop can receive a signal generated by leading edge detection signal ‘lead’ being logically NAND&#39;ed with mode lock signal mode ‘lock’ by the NAND-gate, and a signal at an output terminal of the RS flip-flop can be logically NAND&#39;ed with mode lock signal ‘mode lock’ by the NAND-gate, in order to generate leading edge mode determination signal ‘lead mode’. 
     Referring now to  FIG.  7   , shown is a waveform diagram of an example operation of the leading edge detection circuit in  FIG.  6   , in accordance with embodiments of the preset invention. As shown, during each of the three consecutive sine half-wave cycles processed signal V 13  is at a high level, and after the delay time (e.g., the second reference time) of the delay circuit processed signal V 14  is already at a high level. That is, when delayed processed signal V 13 ′ changes from the low level to the high level processed signal V 14  is already at a high level, so the leading edge detection signal ‘lead’ is the high level, and the mode lock signal ‘mode lock’ is controlled by the digital logic circuit to be high, and the leading mode determination signal ‘lead mode’ can be high. In this way, the LED lighting system may operate in the leading edge dimming mode, the detection for the dimming mode can be completed, the dimming mode may be locked, and the dimming mode detection circuit may not continue to detect the dimming mode of the LED lighting system. 
     Referring now to  FIG.  8   , shown is a schematic block diagram of an example trailing edge detection circuit, in accordance with embodiments of the preset invention. Trailing edge detection circuit  1  can include comparison module  11  and control module  12 . Comparison module  11  can include comparators COMP 1  and COMP 2 . Comparator COMP 1  can receive voltage V 1  at a non-inverting input terminal, and reference voltage Vref 1  at an inverting input terminal, and may generate processed signal V 11  at an output terminal. Comparator COMP 2  can receive voltage V 1  at a non-inverting input terminal, and reference voltage Vref 2  at an inverting input terminal, and may generate processed signal V 12  at an output terminal. 
     Logic module  121  can be configured as an inverter, and processed signal V 11  can be inverted by the inverter, and then output to timing module  122 . When judgment and counting module  123  detects that a time length of a first interval is greater than the timing time set by timing module  122  during N consecutive sine half-wave cycles, trailing edge detection signal ‘trail’ can be active. When the fast rising edge of voltage V 1  is not detected during N consecutive sine half-wave cycles, the dimming mode of the LED lighting system can be determined as the trailing edge dimming mode, and trailing edge mode detection signal ‘trail mode’ can be a high level. The fast rising edge may not be detected for N (e.g., 3) half-sine cycles (e.g., the front cut detection signal lead is low), the system can be considered as operating in the rear cut dimming mode, and the trail mode judgment signal trail mode can be high. Judging and counting module  123  can include N D flip-flops. An input terminal of first D flip-flop can receive the output signal of timing module  122 , and an input terminal of each of the remaining N−1 D flip-flops can receive a signal in which an output signal of the previous D flip-flop and the output signal of timing module  122  are AND&#39;ed. Trigger terminals of the N D flip-flops may all receive processed signal V 12 , and an output signal of the last D flip-flop is trailing edge detection signal ‘trail’. 
     Logic module  124  can include an RS flip-flop. A set terminal of the RS flip-flop can receive a signal after leading edge detection signal ‘lead’ and mode lock signal mode ‘lock’ pass through the NAND-gate. An OR-gate can receive an output terminal of the RS flip-flop at a first input terminal, and leading edge detection signal ‘lead’ at a second input terminal. An AND-gate can receive an output terminal of the OR-gate at a first input terminal, and mode lock signal ‘mode lock’ at a second input terminal, and may generate trailing mode determination signal ‘trail mode’ at an output terminal. 
     Referring now to  FIG.  9   , shown is a waveform diagram of an example operation of the trailing edge detection circuit in  FIG.  8   , in accordance with embodiments of the preset invention. As shown, when processed signal V 11  is at a low level, the input signal of timing module  122  is a high level, and timing module  122  can operate. When the time length of the first interval is greater than timing time Ton of timing module  122  during each of N consecutive cycles, that is, a time length from the moment when processed signal V 11  changes from a high level to a low level to the moment when processed signal V 12  changes from a low level to a high level is greater than timing time Ton (e.g., first reference time), trailing edge detection signal ‘trail’ can be high. 
     When trailing edge detection signal ‘trail’ is high and the leading detection signal ‘lead’ is low, and the mode lock signal ‘mode lock’ is high after being logically control by the digital logic circuit, and the trail mode determination signal ‘trail mode’ is high level, the LED lighting system may operate in the trailing edge dimming mode. In this way, the detection for the dimming mode can be completed, dimming mode detection can be, the dimming mode may be locked, and the dimming mode detection circuit may not continue to perform the detection for the dimming mode. As shown, timing time Ton of the timing module is the first reference time. In the non-dimming mode, timing time Ton is set to be a time length from a moment when voltage V 1  drops to reference voltage Vref 1  in a current sine half-wave cycle to a moment when voltage V 1  rises to reference voltage Vref 2  in the next sine half-wave cycle. 
     Referring now to  FIG.  10   , shown is a schematic block diagram of an example mode lock module and an example fourth logic module, in accordance with embodiments of the preset invention. This example mode lock module can include comparison module  41 , counting module  42 , and logic module  43 . Comparison module  41  can include comparator COMP 5 . Comparator COMP 5  can receive voltage V 1  at a non-inverting input terminal, and reference voltage Vref 5  at an inverting input terminal, and may generate processed signal V 15  at an output terminal. Counting module  42  can receive processed signal V 15  and may generate signal ‘AC’. In this example, counting module  42  can be configured as a D flip-flop. The D flip-flop can receive an inverted version of signal ‘AC’ at an input terminal, and processed signal V 15  at a trigger terminal, and may generate signal ‘AC’ at an output terminal. 
     Logic module  43  can include an RS flip-flop. The RS flip-flop can receive a signal generated by signal ‘AC’ being logically OR′ with trailing edge detection signal ‘trail’ and leading edge detection signal ‘lead’ at a set terminal, and enable signal En_b at a reset terminal, and may generate mode lock signal ‘mode lock’ at an output terminal. Logic module  3  can include a OR-gate, a NOR-gate, and an AND-gate. The NOR-gate can receive trailing edge detection signal ‘trail’ and leading edge detection signal ‘lead’ at input terminals. An input terminal of the NOR-gate can connect to an output terminal of the OR-gate. The AND-gate can receive signal ‘AC’ and an output signal of the NOR-gate at input terminals, and may generate non-dimming mode determination signal ‘AC mode’ at an output terminal. 
     Referring now to  FIG.  11   , shown is a waveform diagram of an example operation of the mode lock module and the fourth logic module in  FIG.  10   , in accordance with embodiments of the preset invention. As shown, when voltage V 1  is greater than reference voltage Vref 5 , processed signal V 15  is at a high level, and counting module  42  can be triggered. When processed signal V 15  has a high level during each of M continuous sine half-wave cycles, that is, input voltage Vac may be provided for the LED lighting system during M continuous sine half-wave cycles, and output signal ‘AC’ of counting module  42  is a high level. 
     When leading edge detection signal ‘trail’ and leading edge detection signal ‘lead’ are both low levels, non-dimming mode determination signal ‘AC mode’ is a high level, and the LED lighting system can be determined to operate in the non-dimming mode. In this way, the detection for the dimming mode may be completed, and the dimming mode can be locked, in order to avoid abnormality of the system due to, e.g., mains jitter. In addition the dimming mode detection circuit may not continue to perform the detection for the dimming mode. In one embodiment, the number M of consecutive sine half-wave cycles to be detected in the non-dimming mode is greater than the number N of consecutive sine half-wave cycles to be detected in the trailing dimming mode and the leading dimming mode. That is, M is a positive integer that is greater than positive integer N. 
     In order to reduce the number of components, comparison modules  11 ,  21 , and  41  can be combined into one comparison module in some cases. In addition, the dimming mode detection circuit may only need two comparators in some cases. Also for example, reference voltage Vref 1  can be equal to reference voltage Vref 3 , and reference voltages Vref 2 , Vref 4 , and Vref 5  can be equal. As another example, processing signals V 11  and V 13  can essentially be the same signal, and processing signals V 12 , V 14 , and V 15  can essentially be the same signal. 
     Referring now to  FIG.  12   , shown is a schematic block diagram of an example non-dimming mode detection circuit, in accordance with embodiments of the preset invention. This example non-dimming mode detection circuit can include comparison module  51  and control module  52 . Comparison module  51  can generate processed signals V 11  and V 12  according to reference voltages Vref 1  and Vref 2 , and voltage V 1 . Control module  52  can generate detection signal Vf according to processed signals V 11  and V 12 , and may generate non-dimming mode detection signal ‘AC mode’ according to detection signal Vf. The non-dimming mode of the LED lighting system can be determined by non-dimming mode detection signal ‘AC mode’. Here for example, reference voltage Vref 1  is less than reference voltage Vref 2 . In other examples, reference voltage Vref 1  can be equal to or greater than reference voltage Vref 2 . 
     Control module  52  can include logic module  521 , timing module  522 , judgment and counting module  523 , and logic module  524 . Logic module  521  can receive processed signal V 11 , and may generate an output signal. Timing module  522  can receive the output signal of logic module  521 , and may generate an output signal. Judgment and counting module  523  can receive the output signal of timing module  522  and processed signal V 12 , and may generate detection signal Vf. Logic module  524  can generate non-dimming mode detection signal ‘AC mode’ in accordance with detection signal Vf. Here, the timing time of timing module  522  is the first reference time. 
     In addition, when a time length of the first interval is detected to be not greater than a first reference time during N consecutive sine half-wave cycles, detection signal Vf can be active, and the LED lighting system may operate in the non-dimming mode, where N is a positive integer. That is, the time length from the moment when processed signal V 11  changes from a high level to a low level to the moment when processed signal V 12  changes from a low level to a high level may not be greater than the first reference time, detection signal Vf can be a high level, and the LED lighting system may operate in the non-dimming mode. In one embodiment, control module  52  can also include delay module  525 . Delay module  525  can receive processed signal V 12  and output the delayed processed signal to judgment and counting module  524 . The sum of the delay time of delay module  525  and the timing time of timing module  522  is first reference time. The addition of delay module  125  can help reduce the interference of processed signal V 12 . 
     Particular embodiments may provide a dimming mode detection method for the LED lighting system. In a first step, a leading edge detection signal can be generated to determine whether the LED lighting system operates in a leading edge dimming mode. In a second step, a time length of a first interval of a first voltage representative of the bus voltage can be detected during two adjacent sine half-wave cycles, in order to determine whether the LED lighting system operates in a trailing edge dimming mode in accordance with the time length of the first interval and the leading edge detection signal. Further, starting and end points of the first interval can be within two adjacent sine half-wave cycles. 
     In addition, when the LED lighting system neither operates in the leading edge dimming mode, nor in the trailing edge dimming mode, the LED lighting system may operate in a non-dimming mode. Also, when the leading edge detection signal is active, the LED lighting system can operate in the leading edge dimming mode. Further, when the time length of the first interval is greater than a first reference time during each of N consecutive sine half-wave cycles and the first voltage does not have a fast rising edge, the trailing edge detection signal may be active, and the LED lighting system can operate in the trailing edge dimming mode, where N is a positive integer. 
     In addition, a trailing edge detection signal can be generated in accordance with the time length of the first interval. When the time length of the first interval is greater than a first reference time during each of the N consecutive sine half-wave cycles, the trailing edge detection signal can be active, and the LED lighting system may operate in the trailing edge dimming mode when the trailing edge detection signal is active and the leading edge detection signal is inactive. Also, when the trailing edge detection signal and the leading edge detection signal are detected to be inactive during N consecutive sine half-wave cycles, the LED lighting system may operate in a non-dimming mode, where N is a positive integer. 
     In addition, a starting point of the first interval can be configured as a falling phase of the first voltage during a current sine half-wave cycle, and an end point of the first interval may be configured as a rising phase of the first voltage during a next sine half-wave cycle. Further, a voltage of the first voltage at the starting point of the first interval may be less than a voltage of the first voltage at the end point of the first interval. Also, when a time length of the first interval is detected to be not greater than a first reference time, the LED lighting system may operate in the non-dimming mode. Further, a moment when the first voltage drops to a first reference voltage during a current sine half-wave cycle is the starting point of the first interval, and a moment when the first voltage rises to a second reference voltage during a next sine half-wave period is the end point of the first interval, where the first reference voltage is less than the second reference voltage. 
     In addition, when the first voltage rises to a third reference voltage, and then rises to a fourth reference voltage rapidly, the leading edge detection signal can be active, and the LED lighting system may operate in the leading edge dimming mode. Further, when a second time is less than a second reference time during N (e.g., a positive integer) consecutive half-sine cycles, the leading edge detection signal can be active, where the second time is configured as a time length during which the first voltage rises from the third reference voltage to the fourth reference voltage. 
     The embodiments were chosen and described in order to best explain the principles of the invention and its practical applications, to thereby enable others skilled in the art to best utilize the invention and various embodiments with modifications as are suited to particular use(s) contemplated. It is intended that the scope of the invention be defined by the claims appended hereto and their equivalents.