Patent Publication Number: US-11031516-B2

Title: Photoelectric conversion element, photoelectric conversion module, and solar photovoltaic power generation system

Description:
This application is the U.S. national phase of International Application No. PCT/JP2014/078384 filed 24 Oct. 2014 which designated the U.S. and claims priority to JP Patent Application No. 2013-222818 filed 25 Oct. 2013, the entire contents of each of which are hereby incorporated by reference. 
     TECHNICAL FIELD 
     The present invention relates to a photoelectric conversion element, a photoelectric conversion module, and a solar photovoltaic power generation system. 
     BACKGROUND ART 
     In recent years, a solar battery which serves as a photoelectric conversion element has drawn attention. An example of the solar battery is a rear surface electrode type solar battery. 
     The rear surface electrode type solar battery is disclosed in Japanese Unexamined Patent Application Publication No. 2007-281156. In the related art, the rear surface electrode type solar battery includes a crystalline semiconductor; an n-type non-crystalline semiconductor layer which is formed on a rear surface which is opposite to an irradiation surface of sunlight, in the crystalline semiconductor; a p-type non-crystalline semiconductor layer which is formed on the rear surface; and electrodes which are formed on the n-type non-crystalline semiconductor layer and the p-type non-crystalline semiconductor layer. 
     However, as described in the related art, in a case where the electrodes are formed on the non-crystalline semiconductor layers, there is a problem that the contact resistance between the non-crystalline semiconductor layer and the electrode increases. 
     SUMMARY OF INVENTION 
     An object of the present invention is to provide a photoelectric conversion element which can reduce the contact resistance between a non-crystalline semiconductor layer containing impurities and an electrode formed on the non-crystalline semiconductor layer, and can improve the element characteristics. 
     A photoelectric conversion element according to embodiments of the present invention includes: a semiconductor substrate, a first semiconductor layer, a second semiconductor layer, a first electrode, and a second electrode. The first semiconductor layer has a first conductive type. The second semiconductor layer has a second conductive type opposite to the first conductive type. The first electrode is formed on the first semiconductor layer. The second electrode is formed on the second semiconductor layer. The first electrode includes a first transparent conductive layer and a first metal layer. The first transparent conductive layer is formed on the first semiconductor layer. The first metal layer is formed on the first transparent conductive layer. The first metal layer includes a plurality of metal crystal grains in which the average crystal grain size in the in-surface direction of the first metal layer is greater than the thickness of the first metal layer. 
     The photoelectric conversion element according to the embodiments of the present invention can prevent the contact resistance between a non-crystalline semiconductor layer containing impurities and an electrode formed on the non-crystalline silicon layer from increasing, and can improve the element characteristics. 
    
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         FIG. 1  is a sectional view illustrating a schematic configuration of a photoelectric conversion element according to a first embodiment of the present invention. 
         FIG. 2A  is a sectional view illustrating a manufacturing method of a photoelectric conversion element illustrated in  FIG. 1 , and is a sectional view illustrating a silicon substrate. 
         FIG. 2B  is a sectional view illustrating the manufacturing method of the photoelectric conversion element illustrated in  FIG. 1 , and is a sectional view illustrating a state where an intrinsic non-crystalline silicon layer is formed on the rear surface of the silicon substrate and an n-type non-crystalline silicon layer and a p-type non-crystalline silicon layer are formed on the intrinsic non-crystalline silicon layer. 
         FIG. 2C  is a sectional view illustrating the manufacturing method of the photoelectric conversion element illustrated in  FIG. 1 , and is a sectional view illustrating a state where a passivation film is formed on a light-receiving surface of the silicon substrate. 
         FIG. 2D  is a sectional view illustrating the manufacturing method of the photoelectric conversion element illustrated in  FIG. 1 , and is a sectional view illustrating a state where a reflection prevention film is formed on the passivation film. 
         FIG. 2E  is a sectional view illustrating the manufacturing method of the photoelectric conversion element illustrated in  FIG. 1 , and is a sectional view illustrating a state where a transparent conductive layer and a metal film are formed. 
         FIG. 2F  is a sectional view illustrating the manufacturing method of the photoelectric conversion element illustrated in  FIG. 1 , and is a sectional view illustrating a state where an electrode is formed. 
         FIG. 3  is a graph illustrating a relationship between an average crystal grain size and the annealing temperature. 
         FIG. 4  a graph illustrating a relationship between the average crystal grain size and contact resistance. 
         FIG. 5  is a sectional view illustrating a schematic configuration of a sample when the contact resistance is measured. 
         FIG. 6  is a schematic view illustrating an interface level of a metal crystal grain. 
         FIG. 7  is a band diagram of the interface between the electrode and the n-type non-crystalline silicon layer in a case where the metal crystal grain is small. 
         FIG. 8  is a band diagram of the interface between the electrode and the n-type non-crystalline silicon layer in a case where the metal crystal grain is large. 
         FIG. 9  is a graph illustrating a relationship between cell resistance and an average value of the average crystal grain size. 
         FIG. 10  is a graph illustrating a relationship between conversion efficiency η and the average value of the average crystal grain size. 
         FIG. 11  is a graph illustrating a relationship between a curve factor FF and the average value of the average crystal grain size. 
         FIG. 12  is a sectional view illustrating an example of a schematic configuration of a photoelectric conversion element according to an application example 1 of a first embodiment of the present invention. 
         FIG. 13  is a sectional view illustrating an example of a schematic configuration of a photoelectric conversion element according to an application example 2 of the first embodiment of the present invention. 
         FIG. 14  is a sectional view illustrating an example of a schematic configuration of a photoelectric conversion element according to an application example 3 of the first embodiment of the present invention. 
         FIG. 15  is a sectional view illustrating a schematic configuration of a photoelectric conversion element according to a second embodiment of the present invention. 
         FIG. 16A  is a sectional view illustrating a manufacturing method of the photoelectric conversion element illustrated in  FIG. 15 , and is a sectional view illustrating a state where an n-type diffusion layer is formed on the rear surface side of the silicon substrate. 
         FIG. 16B  is a sectional view illustrating the manufacturing method of the photoelectric conversion element illustrated in  FIG. 15 , and is a sectional view illustrating a state where an insulation film is formed on the rear surface of the silicon substrate. 
         FIG. 16C  is a sectional view illustrating the manufacturing method of the photoelectric conversion element illustrated in  FIG. 15 , and is a sectional view illustrating a state where a p-type diffusion layer is formed on the front surface side of the silicon substrate. 
         FIG. 16D  is a sectional view illustrating the manufacturing method of the photoelectric conversion element illustrated in  FIG. 15 , and is a sectional view illustrating a state where a non-crystalline film is formed on the light-receiving surface of the silicon substrate. 
         FIG. 16E  is a sectional view illustrating the manufacturing method of the photoelectric conversion element illustrated in  FIG. 15 , and is a sectional view illustrating a state where the non-crystalline film is formed on a passivation film. 
         FIG. 16F  is a sectional view illustrating the manufacturing method of the photoelectric conversion element illustrated in  FIG. 15 , and is a sectional view illustrating a state where the metal film is formed. 
         FIG. 16G  is a sectional view illustrating the manufacturing method of the photoelectric conversion element illustrated in  FIG. 15 , and is a sectional view illustrating a state where the electrode is formed. 
         FIG. 17  is a sectional view illustrating a schematic configuration of a photoelectric conversion element according to an application example of the second embodiment of the present invention. 
         FIG. 18  is a sectional view illustrating a schematic configuration of a photoelectric conversion element according to a third embodiment of the present invention. 
         FIG. 19A  is a sectional view illustrating a manufacturing method of the photoelectric conversion element illustrated in  FIG. 18 , and is a sectional view illustrating a state where the n-type diffusion layer is formed on the rear surface side of the silicon substrate. 
         FIG. 19B  is a sectional view illustrating the manufacturing method of the photoelectric conversion element illustrated in  FIG. 18 , and is a sectional view illustrating a state where the p-type diffusion layer is formed on the front surface side of the silicon substrate. 
         FIG. 19C  is a sectional view illustrating the manufacturing method of the photoelectric conversion element illustrated in  FIG. 18 , and is a sectional view illustrating a state where the non-crystalline film is formed on the front surface of the silicon substrate. 
         FIG. 19D  is a sectional view illustrating the manufacturing method of the photoelectric conversion element illustrated in  FIG. 18 , and is a sectional view illustrating a state where the non-crystalline film is formed on the rear surface of the silicon substrate. 
         FIG. 19E  is a sectional view illustrating the manufacturing method of the photoelectric conversion element illustrated in  FIG. 18 , and is a sectional view illustrating a state where the metal film is formed. 
         FIG. 19F  is a sectional view illustrating the manufacturing method of the photoelectric conversion element illustrated in  FIG. 18 , and is a sectional view illustrating a state where the electrode is formed. 
         FIG. 20  is a sectional view illustrating a schematic configuration of a photoelectric conversion element according to an application example 1 of the third embodiment of the present invention. 
         FIG. 21  is a sectional view illustrating a schematic configuration of a photoelectric conversion element according to an application example 2 of the third embodiment of the present invention. 
         FIG. 22  is a sectional view illustrating a configuration of a photoelectric conversion module provided with the photoelectric conversion element according to the embodiment. 
         FIG. 23  is a schematic view illustrating a configuration of a solar photovoltaic power generation system provided with the photoelectric conversion element according to the embodiment. 
         FIG. 24  is a schematic view illustrating a configuration of a photoelectric conversion module array illustrated in  FIG. 23 . 
         FIG. 25  is a schematic view illustrating a configuration of the solar photovoltaic power generation system provided with the photoelectric conversion element according to the embodiment. 
     
    
    
     DESCRIPTION OF EMBODIMENTS 
     A photoelectric conversion element according to embodiments of the present invention includes: a semiconductor substrate, a first semiconductor layer, a second semiconductor layer, a first electrode, and a second electrode. The first semiconductor layer has a first conductive type. The second semiconductor layer has a second type opposite to the first conductive type. The first electrode is formed on the first semiconductor layer. The second electrode is formed on the second semiconductor layer. The first electrode includes a first transparent conductive layer and a first metal layer. The first transparent conductive layer is formed on the first semiconductor layer. The first metal layer is formed on the first transparent conductive layer. The first metal layer includes a plurality of metal crystal grains in which the average crystal grain size in the in-surface direction of the first metal layer is greater than the thickness of the first metal layer. 
     In the first aspect, it is possible to reduce the contact resistance between the first semiconductor layer and the first electrode formed on the first semiconductor layer. As a result, it is possible to improve the characteristics of the photoelectric conversion element. 
     In addition, the first electrode has a structure in which the first transparent conductive layer and the first metal layer are layered in order. Therefore, in a case where the first electrode is disposed on the rear surface side of the semiconductor substrate, reflectivity becomes high on the rear surface side of the semiconductor substrate. As a result, short-circuit in photoelectric current increases. Therefore, it is possible to improve the characteristics of the photoelectric conversion element. 
     In the photoelectric conversion element according to a second aspect of the present invention, in the photoelectric conversion element according to the first aspect, the first metal layer has silver as a main component. 
     In the second aspect, it is possible to reduce resistance of the first metal layer. In addition, in a case where the first electrode is formed on the rear surface opposite to a light-incident side of the semiconductor substrate, by effectively reflecting light reaching the rear surface, conversion efficiency is improved. 
     In the photoelectric conversion element according to a third aspect of the present invention, in the photoelectric conversion element according to the first or second aspect, the first semiconductor layer and the second semiconductor layer are formed on the rear surface opposite to a light-receiving surface on the semiconductor substrate. 
     In the third aspect, in the rear surface electrode type photoelectric conversion element, it is possible to improve the element characteristics. 
     In the photoelectric conversion element according to a fourth aspect of the present invention, in the photoelectric conversion element according to any of the first to third aspects, in the metal crystal grains, a crystal axis which is parallel to the thickness direction of the semiconductor substrate is preferentially oriented in the &lt;111&gt; direction. 
     In the fourth aspect, it is possible to prevent the contact resistance between the first electrode and the first semiconductor layer from increasing. 
     In the photoelectric conversion element according to a fifth aspect of the present invention, in the photoelectric conversion element according to any of the first to fourth aspects, the first conductive type is an n-type, and the average crystal grain size is less than 3.33 times the thickness of the first metal layer. 
     In the fifth aspect, it is possible to prevent the contact resistance between the first electrode and the first semiconductor layer from increasing. 
     In the photoelectric conversion element according to a sixth aspect of the present invention, in the photoelectric conversion element according to any of the first to fourth aspects, the first conductive type is the n-type, and the average crystal grain size is 2.85 times or less than the thickness of the first metal layer. 
     In the sixth aspect, it is possible to further prevent the contact resistance between the first electrode and the first semiconductor layer from increasing. 
     In the photoelectric conversion element according to a seventh aspect of the present invention, in the photoelectric conversion element according to any of the first to fourth aspects, the first conductive type is the n-type, and the average crystal grain size is 1.55 times or greater and 2.85 times or less than the thickness of the first metal layer. 
     In the seventh aspect, it is possible to still further prevent the contact resistance between the first electrode and the first semiconductor layer from increasing. 
     In the photoelectric conversion element according to an eighth aspect of the present invention, in the photoelectric conversion element according to any of the first to fourth aspects, the first conductive type is a p-type, and the average crystal grain size is 3.3 times or less than the thickness of the first metal layer. 
     In the eighth aspect, it is possible to prevent the contact resistance between the first electrode and the first semiconductor layer from increasing. 
     In the photoelectric conversion element according to a ninth aspect of the present invention, in the photoelectric conversion element according to any of the first to fourth aspects, the first conductive type is a p-type, and the average crystal grain size is 1.03 times or greater and 2.95 times or less than the thickness of the first metal layer. 
     In the ninth aspect, it is possible to further prevent the contact resistance between the first electrode and the first semiconductor layer from increasing. 
     In the photoelectric conversion element according to a tenth aspect of the present invention, in the photoelectric conversion element according to any of the first to fourth aspects, the first conductive type is the p-type, and the average crystal grain size is 1.53 times or greater and 2.15 times or less than the thickness of the first metal layer. 
     In the tenth aspect, it is possible to still further prevent the contact resistance between the first electrode and the first semiconductor layer from increasing. 
     In the photoelectric conversion element according to an eleventh aspect of the present invention, in the photoelectric conversion element according to any of the first to fourth aspects, a second electrode includes a second transparent conductive layer formed on the second semiconductor layer, and a second metal layer formed on the second transparent conductive layer. The second metal layer includes a plurality of metal crystal grains. A contact area between the second electrode and the second semiconductor layer is 1 times or greater than the contact area between the first electrode and the first semiconductor layer. An average value of the average crystal grain size of the metal crystal grain in the first metal layer, and the average crystal grain size of the metal crystal grain in the second metal layer, is 1.03 times or grater and 2.15 times or less than the thickness of the first metal layer and the second metal layer. 
     In the eleventh aspect, it is possible to improve the element characteristics. 
     In the photoelectric conversion element according to a twelfth aspect of the present invention, in the photoelectric conversion element according to the first aspect, the first semiconductor layer is formed on the semiconductor substrate, and includes a first conductive type non-crystalline semiconductor. Between the semiconductor substrate and the first semiconductor layer, a third semiconductor layer including an intrinsic non-crystalline semiconductor is formed. 
     In the twelfth aspect, compared to a case where the first semiconductor layer is formed directly on the semiconductor substrate, the passivation characteristics of the rear surface of the semiconductor substrate is improved. 
     In the photoelectric conversion element according to a thirteenth aspect of the present invention, in the photoelectric conversion element according to the twelfth aspect, the intrinsic non-crystalline semiconductor is hydrogenated amorphous silicon. 
     In the thirteenth aspect, the passivation characteristics of the rear surface of the semiconductor substrate is further improved. 
     In the photoelectric conversion element according to a fourteenth aspect of the present invention, in the photoelectric conversion element according to the twelfth aspect, the first conductive type non-crystalline semiconductor is hydrogenated amorphous silicon. 
     In the fourteenth aspect, it is possible to suppress deterioration of contact interface between the first electrode and the first semiconductor layer. 
     In the photoelectric conversion element according to a fifteenth aspect of the present invention, in the photoelectric conversion element according to the first aspect, the second electrode includes the second transparent conductive layer and the second metal layer. The second transparent conductive layer is formed on the second semiconductor layer. The second metal layer is formed on the second transparent conductive layer. The second metal layer includes a plurality of metal crystal grains in which the average crystal grain size in the in-surface direction of the second metal layer is greater than the thickness of the second metal layer. 
     In the fifteenth aspect, it is possible to decrease the contact resistance between the second semiconductor layer and the second electrode formed on the second semiconductor layer. As a result, it is possible to further improve the characteristics of the photoelectric conversion element. 
     In the photoelectric conversion element according to a sixteenth aspect of the present invention, in the photoelectric conversion element according to the fifteenth aspect, the second semiconductor layer is formed to be in contact with the semiconductor substrate, and includes a second conductive type non-crystalline semiconductor. Between the semiconductor substrate and the second semiconductor layer, a fourth semiconductor layer including the intrinsic non-crystalline semiconductor is formed. 
     In the sixteenth aspect, compared to a case where the second semiconductor layer is formed directly on the semiconductor substrate, the passivation characteristics of the rear surface of the semiconductor substrate is improved. 
     In the photoelectric conversion element according to a seventeenth aspect of the present invention, in the photoelectric conversion element according to the sixteenth aspect, the intrinsic non-crystalline semiconductor is hydrogenated amorphous silicon. 
     In the seventeenth aspect, the passivation characteristics of the rear surface of the semiconductor substrate is further improved. 
     In the photoelectric conversion element according to an eighteenth aspect of the present invention, in the photoelectric conversion element according to the sixteenth aspect, the second conductive type non-crystalline semiconductor is hydrogenated amorphous silicon. 
     In the eighteenth aspect, it is possible to suppress the deterioration of the contact interface between the second electrode and the second semiconductor layer. 
     A photoelectric conversion module according to the first aspect of the present invention includes the photoelectric conversion element according to any of the first to eighteenth aspects of the present invention. 
     In the first aspect, it is possible to improve performance of the photoelectric conversion module. 
     A photoelectric conversion system according to the first aspect of the present invention includes the photoelectric conversion module according to the first aspect of the present invention. 
     In the first aspect, it is possible to improve performance of the photoelectric conversion system. 
     Hereinafter, more specific embodiments of the present invention will be described with reference to the drawings. The same parts or the same corresponding parts in the drawings will be given the same reference numerals, and the description thereof will not be repeated. 
     First Embodiment 
       FIG. 1  illustrates a photoelectric conversion element  10  according to a first embodiment of the present invention. The photoelectric conversion element  10  is the rear surface electrode type solar battery. 
     The photoelectric conversion element  10  includes a silicon substrate  12 , a passivation film  14 , a reflection preventing film  16 , intrinsic non-crystalline silicon layers  18  and  19 , an n-type non-crystalline silicon layer  20   n , a p-type non-crystalline silicon layer  20   p , an electrode  22   n , and an electrode  22   p.    
     The silicon substrate  12  is an n-type single crystal silicon substrate. The thickness of the silicon substrate  12  is, for example, 50 μm to 300 μm. The specific resistance of the silicon substrate  12  is, for example, 1.0 Ω·cm to 10.0 Ω·cm. In addition, instead of the n-type single crystal silicon substrate, an n-type polycrystal silicon substrate, an n single crystal germanium, or an n-type single crystal silicon germanium, may be used, and in general, the semiconductor substrate may be used. Instead of the n-type, the p-type may be used. 
     Although not illustrated, a texture structure is formed on the light-receiving surface of the silicon substrate  12 . Accordingly, the light which is incident on the silicon substrate  12  is blocked up, and the use efficiency of the light can be improved. 
     It is preferable that the orientation of the silicon substrate  12  is (100). Accordingly, it becomes easy to form the texture structure. 
     The light-receiving surface of the silicon substrate  12  is covered with the passivation film  14 . The passivation film  14  is, for example, a hydrogenated amorphous silicon film. The film thickness of the passivation film  14  is, for example, 3 nm to 30 nm. In addition, as the passivation film  14 , instead of the hydrogenated amorphous silicon film, a silicon nitride film, a silicon oxide film, or a silicon oxynitride film, may be used. 
     The reflection preventing film  16  covers the passivation film  14 . The reflection preventing film  16  is, for example, a silicon nitride film. The film thickness of the reflection preventing film  16  is, for example, 50 nm to 200 nm. 
     On the rear surface of the silicon substrate  12 , the intrinsic non-crystalline silicon layers  18  and  19  are formed. The intrinsic non-crystalline silicon  18  and  19  are made of, for example, an i-type hydrogenated amorphous silicon (a-Si:H). The intrinsic non-crystalline silicon layer  18  is formed at a part of the rear surface of the silicon substrate  12 . The intrinsic non-crystalline silicon layer  19  is formed to be adjacent to the intrinsic non-crystalline silicon layer  18  on the rear surface of the silicon substrate  12 . In other words, the intrinsic non-crystalline silicon layers  18  and  19  are alternately formed on the entire rear surface of the silicon substrate  12 . The thickness of the intrinsic non-crystalline silicon layers  18  and  19  is, for example, 10 nm. In the example illustrated in  FIG. 1 , the intrinsic non-crystalline silicon layer  19  is formed to be adjacent to the intrinsic non-crystalline silicon layer  18 , but, for example, may be formed at a part of the region in which the intrinsic non-crystalline silicon layer  18  is not formed on the rear surface of the silicon substrate  12 . In addition, the intrinsic non-crystalline silicon layers  18  and  19  may be made only of a non-crystalline phase, or may be made of a fine crystalline phase and a non-crystalline phase. 
     On the intrinsic non-crystalline silicon layer  18 , the n-type non-crystalline silicon layer  20   n  is formed. The n-type non-crystalline silicon layer  20   n  is made of the hydrogenated amorphous silicon (a-Si:H(n)) containing n-type impurities (for example, phosphorus). The thickness of the n-type non-crystalline silicon layer  20   n  is, for example, 10 nm. The impurities concentration of the n-type non-crystalline silicon layer  20   n  is, for example, 1×10 19  cm −3  to 1×10 21  cm −3 . The n-type non-crystalline silicon layer  20   n  may be made only of the non-crystalline phase, or may be made of the fine crystalline phase and the non-crystalline phase. An example of a case where the n-type non-crystalline silicon layer  20   n  is made of the fine crystalline phase and the non-crystalline phase, is, for example, an n-type microcrystalline silicon. 
     On the intrinsic non-crystalline silicon layer  19 , the p-type non-crystalline silicon layer  20   p  is formed. The p-type non-crystalline silicon layer  20   p  is made of the hydrogenated amorphous silicon (a-Si:H(p)) containing p-type impurities (for example, boron). The thickness of the p-type non-crystalline silicon layer  20   p  is, for example, 10 nm. The impurities concentration of the p-type non-crystalline silicon layer  20   p  is, for example, 1×10 19  cm −3  to 1×10 21  cm −3 . The p-type non-crystalline silicon layer  20   p  may be made only of the non-crystalline phase, or may be made of the fine crystalline phase and the non-crystalline phase. An example of a case where the p-type non-crystalline silicon layer  20   p  is made of the fine crystalline phase and the non-crystalline phase, is a p-type microcrystalline silicon. In the example illustrated in  FIG. 1 , the n-type non-crystalline silicon layer  20   n  is formed to be adjacent to the p-type non-crystalline silicon layer  20   p , but it is not necessary to be adjacent to the p-type non-crystalline silicon layer  20   p , and for example, the n-type non-crystalline silicon layer  20   n  may be formed at least at a part on the non-crystalline silicon layer  18 , or the p-type non-crystalline silicon layer  20   p  may be formed at least at a part on the non-crystalline silicon layer  19 . 
     In the in-surface direction of the silicon substrate  12 , it is preferable that the width dimension of the n-type non-crystalline silicon layer  20   n  is less than the width dimension of the p-type non-crystalline silicon layer  20   p . As a ratio of the area of the p-type non-crystalline silicon layer  20   p  with respect to the sum of the area of the n-type non-crystalline silicon layer  20   n  and the area of the p-type non-crystalline silicon layer  20   p  (area ratio of the p-type non-crystalline silicon layer  20   p ) increases, the distance by which the light-generated minority carrier (positive hole) should move to reach the p-type non-crystalline silicon layer  20   p  decreases. Therefore, the number of recombining positive holes until reaching the p-type non-crystalline silicon layer  20   p  decreases, and the short-circuit in photoelectric current increases. Therefore, a conversion ratio of the photoelectric conversion element  10  is improved. A preferable area ratio of the p-type non-crystalline silicon layer  20   p  is 63% to 90%. 
     Although not illustrated, the texture structure may be formed on the rear surface of the silicon substrate  12 . In this case, in the intrinsic non-crystalline silicon layers  18  and  19 , and the n-type non-crystalline silicon layer  20   n  and the p-type non-crystalline silicon layer  20   p , unevenness which corresponds to the texture structure of the rear surface of the silicon substrate  12  is formed. 
     On the n-type non-crystalline silicon layer  20   n , the electrode  22   n  is formed. The electrode  22   n  includes a transparent conductive layer  26   n  and a metal layer  28   n . The transparent conductive layer  26   n  is made of, for example, ITO. The thickness of the transparent conductive layer  26   n  is, for example, 0.1 nm to 20 nm. The metal layer  28   n  has silver as a main component. The metal layer  28   n  may contain metal (for example, titanium) other than silver. The thickness of the metal layer  28   n  is, for example, 100 nm to 1000 nm. 
     On the p-type non-crystalline silicon layer  20   p , the electrode  22   p  is formed. The electrode  22   p  includes a transparent conductive layer  26   p  and a metal layer  28   p . The transparent conductive layer  26   p  is made of, for example, ITO. The thickness of the transparent conductive layer  26   p  is, for example, 0.1 nm to 20 nm. The metal layer  28   p  has silver as a main component. The metal layer  28   p  may contain metal (for example, titanium) other than silver. The thickness of the metal layer  28   p  is, for example, 100 nm to 1000 nm. 
     In addition, in a case where the texture structure is formed on the rear surface of the silicon substrate  12 , adhesiveness between the electrode  22   n  and the n-type non-crystalline silicon layer  20   n  and adhesiveness between the electrode  22   p  and the p-type non-crystalline silicon layer  20   p  are improved. Accordingly, yield and reliability of the photoelectric conversion element  10  are improved. Furthermore, compared to a case where the rear surface of the silicon substrate  12  is flat, since the contact surface between the electrode  22   n  and the n-type non-crystalline silicon layer  20   n , and a contact area between the electrode  22   p  and the p-type non-crystalline silicon layer  20   p  become large, the contact resistance decreases. In addition, when viewed from the thickness direction of the silicon substrate  12 , the texture may be formed in any one of a region including at least a part of the region overlapping the electrode  22   n , and a region including at least a part of the region overlapping the electrode  22   p.    
     [Manufacturing Method of Photoelectric Conversion Element] 
     With reference to  FIGS. 2A to 2F , a manufacturing method of the photoelectric conversion element  10  will be described. 
     First, as illustrated in  FIG. 2A , the silicon substrate  12  is prepared. The silicon substrate  12  has the texture structure on the entire light-receiving surface. A method for forming the texture structure is, for example, wet etching. By performing the wet etching on the entire light-receiving surface of the silicon substrate  12 , the texture structure is formed on the entire light-receiving surface of the silicon substrate  12 . The wet etching is performed, for example, by using an alkaline solution. The time for the wet etching is, for example, 10 minutes to 60 minutes. The alkaline solution used in the wet etching is, for example, NaOH or KOH, and the concentration thereof is, for example, 5%. 
     Next, as will be described in  FIG. 2B , intrinsic non-crystalline silicon layers  18  and  19  are formed on the rear surface of the silicon substrate  12 , the n-type non-crystalline semiconductor layer  20   n  is formed on the intrinsic non-crystalline semiconductor layer  18 , and the p-type non-crystalline semiconductor layer  20   p  is formed on the intrinsic non-crystalline semiconductor layer  19 . 
     The intrinsic non-crystalline silicon layers  18  and  19  can be formed, for example, by a plasma CVD. In a case where the intrinsic non-crystalline silicon layers  18  and  19  are formed by the plasma CVD, reaction gas which is led into a reaction chamber provided with a plasma CVD device, is silane gas and hydrogen gas. The temperature of the silicon substrate  12  is, for example, 100° C. to 300° C. 
     Next, the p-type non-crystalline silicon layer is formed on the intrinsic non-crystalline silicon layers  18  and  19 . The p-type non-crystalline silicon layer can be formed, for example, by the plasma CVD. In a case where the p-type non-crystalline silicon layer is formed by the plasma CVD, the reaction gas which is led into the reaction chamber provided in the plasma CVD device, is silane gas, hydrogen gas, and diboran gas. The temperature of the silicon substrate  12  is, for example, 100° C. to 300° C. 
     Next, a coating layer which serves as a mask is formed on the p-type non-crystalline silicon layer. The coating layer is obtained by patterning the silicon nitride film formed on the p-type non-crystalline silicon layer. Instead of the silicon nitride film, the silicon oxide film or the silicon oxynitride film may be used. The patterning is performed, for example, by a photolithography method. The coating layer covers a part which becomes the p-type non-crystalline silicon layer  20   p  later, that is, a p-type non-crystalline silicon layer formed on the intrinsic non-crystalline silicon layer  19 , on the p-type non-crystalline silicon layer formed on the intrinsic non-crystalline silicon layers  18  and  19 . 
     Next, the p-type non-crystalline silicon layer formed on the intrinsic non-crystalline silicon layer  18  is removed. A method of removing the p-type non-crystalline silicon layer may be dry etching, or may be wet etching. Accordingly, the p-type non-crystalline silicon layer  20   p  is formed on the intrinsic non-crystalline silicon layer  19 . At this time, the coating layer is formed on the p-type non-crystalline silicon layer  20   p.    
     Next, an n-type non-crystalline silicon layer is formed on the intrinsic non-crystalline silicon layer  18 , and on the coating layer formed on the p-type non-crystalline silicon layer  20   p . The n-type non-crystalline silicon layer can be formed, for example, by the plasma CVD. In a case where the n-type non-crystalline silicon layer is formed by the plasma CVD, the reaction gas which is led into the reaction chamber provided in the plasma CVD device, is silane gas, hydrogen gas, and phosphine gas. The temperature of the silicon substrate  12  is, for example, 100° C. to 300° C. 
     Next, the coating layer formed on the p-type non-crystalline silicon layer  20   p  is removed. Accordingly, the n-type non-crystalline silicon layer  20   n  is formed on the intrinsic non-crystalline silicon layer  18 . The method of removing the coating layer formed on the p-type non-crystalline silicon layer  20   p  is, for example, wet etching. 
     Next, as illustrated in  FIG. 2C , on the light-receiving surface of the silicon substrate  12 , the passivation film  14  is formed. The passivation film  14  is formed, for example, by the plasma CVD. 
     Next, as illustrated in  FIG. 2D , the reflection preventing film  16  is formed on the passivation film  14 . The reflection preventing film  16  is formed, for example, by forming the silicon nitride film, the silicon oxide film, or the silicon oxynitride film, for example, by the plasma CVD. 
     Next, as illustrated in  FIG. 2E , the transparent conductive layers  26   n  and  26   p  and metal layers  21   n  and  21   p  are formed. A forming method of the transparent conductive layers  26   n  and  26   p  and the metal layers  21   n  and  21   p  is, for example, as follows. 
     First, on the n-type non-crystalline silicon layer  20   n  and the p-type non-crystalline silicon layer  20   p , by deposition or sputtering, the transparent conductive layer made of ITO and the metal layer made of silver are formed. Next, a resist pattern which serves as a mask is formed on the metal layer. The resist pattern is obtained by patterning the resist formed on the metal layer. The patterning is performed, for example, by the photolithography and etching. In a case of being viewed from the thickness direction of the silicon substrate  12 , the resist pattern is formed so as not to overlap a boundary between the n-type non-crystalline silicon layer  20   n  and the p-type non-crystalline silicon layer  20   p.    
     Next, in the transparent conductive layer and the metal layer, a part which is not covered with the resist pattern is removed. A method of removing the transparent conductive layer and the metal layer is, for example, wet etching. 
     Next, the resist pattern is removed. Accordingly, the transparent conductive layer  26   n  and the metal layer  21   n  are formed on the n-type non-crystalline silicon layer  20   n , and the transparent conductive layer  26   p  and the metal layer  21   p  are formed on the p-type non-crystalline silicon layer  20   p . A method of removing the resist pattern is, for example, wet etching. 
     Next, as illustrated in  FIG. 2F , the electrodes  22   n  and  22   p  are formed. Accordingly, the photoelectric conversion element  10  which is an object is obtained. 
     The electrodes  22   n  and  22   p  are formed by performing the heat treatment with respect to the metal films  21   n  and  21   p . The heat treatment is performed, for example, by using a hot plate. The time for the heat treatment is, for example, 15 minutes. It is preferable that the temperature of the heat treatment is 100° C. to 200° C. The heat treatment is performed, for example, in the atmosphere. The heat treatment may be performed in the inert atmosphere or in a vacuum. The heat treatment may be performed by some processes, after the metal films  21   n  and  21   p  are formed. For example, the heat treatment may be performed when a module is manufactured. In addition, after performing the heat treatment or the like and growing the metal crystal grain having a desired size, on the electrodes  22   n  and  22   p , the conductive film may further be formed. In this case, it is possible to determine the boundary between the electrode  22   n  and the conductive film, and between the electrode  22   p  and the conductive film, from discontinuity of distribution of the metal crystal grain, discontinuity of composition, or the like. 
     [Average Crystal Grain Size] 
     In the photoelectric conversion element  10 , by making the average crystal grain size of the plurality of metal crystal grains (hereinafter, simply called an average crystal grain size) included in the metal layers  28   n  and  28   p  greater than the thickness of the metal layers  28   n  and  28   p , it is possible to improve the element characteristics. Hereinafter, this will be described. In addition, after performing the heat treatment or the like and growing the metal crystal grain having the desired size, on the electrodes  22   n  and the electrode  22   p , further, in a case where the conductive film is formed, the relationship between the metal layer in which the metal crystal grain having the desired size is formed, and the thickness of the metal layer, may satisfy the above-described conditions. 
     The average crystal grain size is obtained by analyzing the front surfaces of the metal layers  28   n  and  28   p  by an electron backscatter diffraction pattern. The metal layers  28   n  and  28   p  include the plurality of metal crystal grains. 
     The average crystal grain size is an average of a product of the crystal grain size of each metal crystal grain and an area occupying ratio. The crystal grain size is obtained by the following equation (1).
 
Crystal grain size=2×{(area of crystal grain)/π} 1/2   (1)
 
     The “area of crystal grain” in the equation (1) is measured by using the electron backscatter diffraction pattern. The equation (1) assumes that the calculation is performed on the assumption that the area of the crystal grain is an area of a circle, and on the assumption that the crystal grain size is the diameter of the circle. When obtaining the crystal grain size, a corresponding grain boundary of sigma 3 (Σ3) is not handled as a grain boundary. In addition, in a case where deviation of the crystal orientation is equal to or less than 5 degrees, the same crystal grain is achieved. 
     The area occupying ratio is obtained by dividing the area of the metal crystal grain by the area of the measurement region. Here, the area of the metal crystal grain is the area when orthographic projection is performed on a plane perpendicular to the thickness direction of the silicon substrate  12 . The measurement region is 8 μm×23 μm. Furthermore, the metal crystal grain including the boundary of the measurement region is not included in the calculation of the average crystal grain size. 
     In a case of being viewed from the thickness direction of the silicon substrate  12 , the crystal orientation of the metal crystal grain is preferentially orientated to &lt;111&gt;. In this case, since the crystal orientation of the metal crystal grain is aligned, uniformity of a work function of the metal crystal grain on the interface between the transparent conductive layer  26   n  and the metal layer  28   n , and a work function of the metal crystal grain on the interface between the transparent conductive layer  26   p  and the metal layer  28   p , is improved. As a result, it is possible to suppress irregularity of the contact resistance. In addition, work functions of a {110} surface, a {100} surface, and a {111} surface of silver, are respectively 4.52 eV, 4.64 eV, and 4.74 eV. The work function of the {111} surface is the largest. Therefore, by making the surface orientation of the metal crystal grain preferentially oriented to {111}, that is, by making the crystal orientation of the metal crystal grain preferentially oriented to &lt;111&gt; with respect to the thickness direction of the silicon substrate  12 , in particular, an effect of reducing the contact resistance between the p-type non-crystalline silicon layer  20   p  and the electrode  22   p , is achieved. 
     In a case where a metal film  21   n  is heat-treated at 150° C. for 15 minutes, a ratio of occupying the metal layer  28   n  by the metal crystal grain having the crystal orientation of the &lt;111&gt; direction within 10 degrees with respect to the thickness direction of the silicon substrate  12 , is 49.2%. In a case where a metal film  21   p  is heat-treated at 150° C. for 15 minutes, a ratio of occupying the metal layer  28   p  by the metal crystal grain having the crystal orientation of the &lt;111&gt; direction within 10 degrees with respect to the thickness direction of the silicon substrate  12 , is 48.8%. 
     In a case where the film thickness of the metal layer  28   n  is 0.4 μm, in the plurality of metal crystal grains, a ratio of occupying the metal layer  28   n  by the metal crystal grain having the diameter which is equal to or greater than 0.4 μm, is 7.6% before the heat treatment, and is 53.0% after the heat treatment at 150° C. for 15 minutes. In a case where the film thickness of the metal layer  28   p  is 0.4 μm, in the plurality of metal crystal grains, a ratio of occupying the metal layer  28   p  by the metal crystal grain having the diameter which is equal to or greater than 0.4 μm, is 3.0% before the heat treatment, and is 46.1% after the heat treatment at 150° C. for 15 minutes. 
     The average crystal grain size depends on the temperature (hereinafter, simply referred to as annealing temperature) when the metal layers  21   n  and  21   p  are heat-treated.  FIG. 3  is a graph illustrating a relationship between the average crystal grain size and the annealing temperature.  FIG. 3  illustrates the average crystal grain size in a case where the annealing temperature is 25° C. This shows the average crystal grain size in a state where the heat treatment is not performed. As illustrated in  FIG. 3 , in the metal layers  28   n  and  28   p , when the annealing temperature becomes high, the average crystal grain size becomes large. Here, the thickness of the metal layers  28   n  and  28   p  is 0.4 μm. In other words, by performing the heat treatment with respect to the metal layers  21   n  and  21   p , the average crystal grain size becomes greater than the thickness of the metal layers  28   n  and  28   p.    
       FIG. 4  is a graph illustrating a relationship between the average crystal grain size and the contact resistance. 
     The contact resistance is measured by creating a sample  30  illustrated in  FIG. 5  and using the sample  30 . The sample  30  includes a silicon substrate  32 , an electrode  34 , a non-crystalline silicon layer  36 , and an electrode  38 . 
     In the contact resistance between the electrode  22   n  and the n-type non-crystalline silicon layer  20   n , the electrode  34  is considered as the electrode  22   n . In this case, the non-crystalline silicon layer  36  contains n-type impurities, and the silicon substrate  32  is an n-type silicon substrate. A resistance ratio of the n-type silicon substrate is equal to or less than 0.01 Ω·cm. The configuration and thickness of the electrode  34  are the same as the configuration and the thickness of the electrode  22   n . The thickness and an impurities concentration of the non-crystalline silicon layer  36  are the same as those of the n-type non-crystalline silicon layer  20   n . The thickness of the silicon substrate  32  is 300 μm. 
     In the contact resistance between the electrode  22   p  and the p-type non-crystalline silicon layer  20   p , the electrode  34  is considered as the electrode  22   p . In this case, the non-crystalline silicon layer  36  contains p-type impurities, and the silicon substrate  32  is a p-type silicon substrate. A resistance ratio of the p-type silicon substrate is equal to or less than 0.01 Ω·cm. The configuration and thickness of the electrode  34  are the same as the configuration and the thickness of the electrode  22   p . The thickness and an impurities concentration of the non-crystalline silicon layer  36  are the same as those of the p-type non-crystalline silicon layer  20   p.    
     In any case where the contact resistance between the electrode  22   n  and the n-type non-crystalline silicon layer  20   n  is measured, and where the contact resistance between the electrode  22   p  and the p-type non-crystalline silicon layer  20   p  is measured, the electrode  38  is a layered structure of titanium (Ti), palladium (Pd), and silver (Ag). 
     As illustrated in  FIG. 4 , when the average crystal grain size in the metal layer  28   n  becomes greater than the thickness (0.4 μm) of the metal layer  28   n , the contact resistance between the n-type non-crystalline silicon layer  20   n  and the electrode  22   n  becomes lower than the contact resistance in a state where the heat treatment is not performed. In addition, when the average crystal grain size in the metal layer  28   n  is equal to or greater than the 1.33 μm, the contact resistance between the n-type non-crystalline silicon layer  20   n  and the electrode  22   n  becomes greater than the contact resistance in a state where the heat treatment is not performed (when the average crystal grain size in the metal layer  28   n  is equal to or less than 1.14 μm, the contact resistance between the n-type non-crystalline silicon layer  20   n  and the electrode  22   n  is smaller than the contact resistance in a state where the heat treatment is not performed). Therefore, it is preferable that the average crystal grain size of the metal layer  28   n  is greater than 1 times the film thickness of the metal layer  28   n . The average crystal grain size of the metal layer  28   n  is more preferably greater than 1 times and less than 3.33 times the film thickness of the metal layer  28   n , still more preferably greater than 1 times and equal to or less than 2.85 times the film thickness of the metal layer  28   n , and further still more preferably equal to or greater than 1.55 times and equal to or less than 2.85 times the film thickness of the metal layer  28   n . Specifically, in a case where the thickness of the metal layer  28   n  is 0.4 μm, the average crystal grain size in the metal layer  28   n  is preferably greater than 0.4 μm, more preferably greater than 0.4 μm and less than 1.33 μm, still more preferably greater than 0.4 μm and equal to or less than 1.14 μm, and still more preferably equal to or greater than 0.62 μm and equal to or less than 1.14 μm. In this case, the contact resistance becomes extremely low, and the element characteristics are improved. 
     Here, as a reason why the contact resistance decreases by increasing the average crystal grain size, for example, the following reason is considered. 
     As illustrated in  FIG. 6 , it is considered that a high density interface level is present in the crystal grain boundary which is the interface between the metal crystal grains  24 . In other words, as the crystal grain boundary becomes dense, the influence of the interface level increases. 
     In a case where the metal crystal grain  24  is small, the interface level increases. Therefore, as illustrated in  FIG. 7 , a dipole is formed between the interface level (charged to plus) at which an electron is discharged, and an electron carrier (electron accumulation layer) evoked on the front surface of the transparent conductive layer  26   n . As a result, an energy barrier increases, non-ohmic properties are easily achieved, and the contact resistance increases. In addition, in  FIG. 7 , in order to make it easy to determine the influence of the interface level, it is described that an interface level region is present between the transparent conductive layer  26   n  and the metal layer  28   n.    
     Meanwhile, in a case where the metal crystal grain  24  is large, the crystal grain boundary becomes small. Therefore, the interface level density effectively decreases. In this case, as illustrated in  FIG. 8 , band bending occurs so that a Fermi level of the transparent conductive layer  26   n  and a Fermi level of the metal layer  28   n  match each other, and the electron accumulation layer is formed in the transparent conductive layer  26   n . Since the energy barrier between the transparent conductive layer  26   n  and the metal layer  28   n  is rarely present, the ohmic properties are achieved, and the contact resistance decreases. In a case where the crystal grain size of the metal crystal grain  24  is large, the contact resistance can be reduced. When the average crystal grain size in the metal layer  22   n  is greater than the film thickness of the metal layer  22   n , since most of the crystal grain boundary between the metal crystal grains  24  penetrate in the film thickness direction of the metal layer  22   n , the crystal grain boundary density becomes extremely low in the vicinity of the interface with the transparent conductive layer  26   n , and the interface level density becomes extremely low. Therefore, it is preferable that the average crystal grain size in the metal layer  22   n  is greater than the film thickness of the metal layer  22   n . Similarly, it is preferable that the average crystal grain size in the metal layer  22   p  is greater than the film thickness of the metal layer  22   p.    
     The reason why the contact resistance becomes high as the average crystal grain size becomes extremely large, is considered as follows, for example. In other words, when the average crystal grain size becomes extremely large, the diffusion speed of oxygen in the metal layer increases. Accordingly, it is considered that the oxygen is likely to infiltrate into the metal layer from the outside, the metal layer is oxidized and the high resistance is achieved, or high resistance is achieved by making the oxygen reach the non-crystalline silicon layer and oxidizing the non-crystalline silicon layer. 
     In  FIG. 4 , when the average crystal grain size in the metal layer  28   p  becomes greater than 1.48 times (0.59 μm) the thickness of the metal layer  28   p , the contact resistance between the p-type non-crystalline silicon layer  20   p  and the metal layer  28   p  becomes greater than the contact resistance in a state where the heat treatment is not performed. In other words, in a case where the average crystal grain size in the metal layer  28   p  is equal to or greater than 1.03 times and less than 1.48 times (0.41 μm to 0.59 μm) the thickness of the metal layer  28   p , the contact resistance between the p-type non-crystalline silicon layer  20   p  and the electrode  22   p  becomes smaller than the contact resistance in a state where the heat treatment is not performed. 
     The reason why the contact resistance decreases in a case where the average crystal grain size in the metal layer  28   p  is equal to or greater than 1.03 times and less than 1.48 times (0.41 μm to 0.59 μm) the thickness of the metal layer  28   p , is considered as similar to that in a case of the metal layer  28   n.    
       FIG. 9  is a graph illustrating a relationship between the contact resistance (cell resistance) per 1 cm 2  of a photoelectric conversion element, and an average value of the average crystal grain size. The cell resistance is the contact resistance of the photoelectric conversion element  10  when a ratio of the contact area between the electrode  22   n  and the n-type non-crystalline silicon layer  20   n , and the contact area between the electrode  22   p  and the p-type non-crystalline silicon layer  20   p , is assumed. The average value of the average crystal grain size is an average value of the average crystal grain size in the electrode  22   n  and the average crystal grain size in the electrode  22   p . In  FIG. 9 , each expression in the general example, such as n:p=2:1, n:p=1:1, n:p=1:2, illustrates that ratios of the contact area between the electrode  22   n  and of the n-type non-crystalline silicon layer  20   n , and the contact area between the electrode  22   p  and the p-type non-crystalline silicon layer  20   p , are respectively 2:1, 1:1, and 1:2. 
     In a case where the contact area between the electrode  22   n  and the n-type non-crystalline silicon layer  20   n  is 1, and the contact area between the electrode  22   p  and the p-type non-crystalline silicon layer  20   p  is N, the cell resistance is obtained by the following equation (2).
 
Cell resistance={(the contact resistance between the electrode 22 n  and the n-type non-crystalline silicon layer 20 n )×(1+ N )}+{(the contact resistance between the electrode 22 p  and the p-type non-crystalline silicon layer 20 p )}×(1+ N )/ N/}   (2)
 
     As illustrated in  FIG. 9 , in a case where the contact area between the electrode  22   p  and the p-type non-crystalline silicon layer  20   p  is 1 times or greater than the contact area between the electrode  22   n  and the n-type non-crystalline silicon layer  20   n , and the average value of the average crystal grain size is equal to or greater than 0.41 μm and equal to or less than 0.86 μm, the cell resistance becomes lower than the cell resistance in a state where the heat treatment is not performed. Therefore, it is preferable that the average of the average crystal grain size is equal to or greater than 1.03 times and equal to or less than 2.15 times the thickness of the metal layer  28   n  and the thickness of the metal layer  29   n.    
       FIG. 10  is a graph illustrating a relationship between conversion efficiency η and the average value of the average crystal grain size. The conversion efficiency η is standardized by using the conversion efficiency η in a state where the heat treatment is not performed as a standard. The average value of the average crystal grain size is a value obtained by averaging the average crystal grain size of the plurality of metal crystal grains contained in the metal layer  28   n , and the average crystal grain size of the plurality of metal crystal grains contained in the metal layer  28   p.    
       FIG. 11  is a graph illustrating a relationship between a curve factor FF and the average value of the average crystal grain size. The curve factor FF is standardized by using the curve factor FF in a state where the heat treatment is not performed as a standard. The average value of the average crystal grain size is obtained by averaging the average crystal grain size of the plurality of metal crystal grains contained in the metal layer  28   n , and the average crystal grain size of the plurality of metal crystal grains contained in the metal layer  28   p.    
       FIGS. 10 and 11  illustrate a measurement result in a case where the thickness of the metal layers  28   n  and  28   p  is 0.4 μm, and the contact area between the electrode  22   p  and the p-type non-crystalline silicon layer  20   p  is 3 times the contact area between the electrode  22   n  and the n-type non-crystalline silicon layer  20   n . As illustrated in  FIGS. 10 and 11 , in a case where the average value of the average crystal grain size is greater than the thickness of the metal layers  28   n  and  28   p , the element characteristics (specifically, the conversion efficiency η and the curve factor FF) are improved. In particular, the curve factor FF is improved because the contact resistance between the n-type non-crystalline silicon layer  20   n  and the electrode  22   n  and the contact resistance between the p-type non-crystalline silicon layer  20   p  and the electrode  22   p  become low by performing the heat treatment. In other words, in the photoelectric conversion element  10 , since the contact resistance between the n-type non-crystalline silicon layer  20   n  and the electrode  22   n  and the contact resistance between the p-type non-crystalline silicon layer  20   p  and the electrode  22   p  can become low, it is possible to improve the curve factor FF. As a result, it is possible to improve the conversion efficiency η. 
     The average value of the average crystal grain size is preferably greater than the thickness of the metal layers  28   n  and  28   p  and equal to or less than 3.3 times the thickness of the metal layers  28   n  and  28   p . The average value of the average crystal grain size is further preferably equal to or greater than 1.03 times the thickness of the metal layers  28   n  and  28   p  and equal to or less than 3.3 times the thickness of the metal layers  28   n  and  28   p . Specifically, in a case where the thickness of the metal layers  28   n  and  28   p  is 0.4 μm, the average value of the average crystal grain size is preferably equal to or greater than 0.41 μm and equal to or less than 1.32 μm. In this case, as illustrated in  FIGS. 10 and 11 , the element characteristics are improved. 
     The average value of the average crystal grain size is more preferably equal to or greater than 1.03 times the thickness of the metal layers  28   n  and  28   p , and equal to or less than 2.95 times the thickness of the metal layers  28   n  and  28   p . Specifically, in a case where the thickness of the metal layers  28   n  and  28   p  is 0.4 μm, the average value of the average crystal grain size is equal to or greater than 0.41 μm and equal to or less than the 1.18 μm. In this case, as illustrated in  FIGS. 10 and 11 , the element characteristics are further improved. 
     The average value of the average crystal grain size is further more preferably equal to or greater than 1.53 times the thickness of the metal layers  28   n  and  28   p , and equal to or less than 2.15 times the thickness of the electrodes  22   n  and  22   p . Specifically, in a case where the thickness of the metal layers  28   n  and  28   p  is 0.4 μm, the average value of the average crystal grain size is more preferably equal to or greater than 0.61 μm and equal to or less than the 0.86 μm. In this case, as illustrated in  FIGS. 10 and 11 , the element characteristics are still further improved. 
     Application Examples 1 to 3 of First Embodiment 
     The photoelectric conversion element according to the first embodiment of the present invention may have configurations illustrated in  FIGS. 12 to 14 . 
       FIG. 12  is a sectional view illustrating an example of a schematic configuration of a photoelectric conversion element  10 A according to an application example 1 of the first embodiment of the present invention. As illustrated in  12 , the photoelectric conversion element  10 A is not provided with the intrinsic non-crystalline silicon layer  18  compared to the photoelectric conversion element  10 . 
     When manufacturing the photoelectric conversion element  10 A, for example, the intrinsic non-crystalline silicon layer and the p-type non-crystalline silicon layer are formed in order on the rear surface of the silicon substrate  12 . Next, in the p-type non-crystalline silicon layer, a part except the part which becomes the p-type non-crystalline silicon layer  20   p  later is removed, and in the intrinsic non-crystalline silicon layer, a part except the part which becomes the intrinsic non-crystalline silicon layer  19  later is removed. Next, on the resist pattern formed on the p-type non-crystalline silicon layer  20   p , and on the rear surface of the silicon substrate  12 , the n-type non-crystalline silicon layer is formed. Next, the resist pattern formed on the p-type non-crystalline silicon layer  20   p  is removed. Accordingly, on the rear surface of the silicon substrate  12 , the intrinsic non-crystalline silicon layer  19 , the p-type non-crystalline silicon layer  20   p , and the n-type non-crystalline silicon layer  20   n  are formed. 
       FIG. 13  is a sectional view illustrating an example of a schematic configuration of a photoelectric conversion element  10 B according to an application example 2 of the first embodiment of the present invention. As illustrated in  FIG. 13 , the photoelectric conversion element  10 B is not provided with the intrinsic non-crystalline silicon layer  19  compared to the photoelectric conversion element  10 . 
     When manufacturing the photoelectric conversion element  10 B, for example, the intrinsic non-crystalline silicon layer, the n-type non-crystalline silicon layer, and the coating layer are formed in order on the rear surface of the silicon substrate  12 . Next, by using the photolithography method, the coating layer, the n-type non-crystalline silicon layer, and the intrinsic non-crystalline silicon layer are patterned, a part of the silicon substrate  12  is exposed, and the n-type non-crystalline silicon layer  20   n  and the intrinsic non-crystalline silicon layer  18  are formed. At this time, the coating layer is formed on the n-type non-crystalline silicon layer  20   n . Next, on the coating layer formed on the n-type non-crystalline silicon layer  20   n , and on the rear surface of the silicon substrate  12 , the p-type non-crystalline silicon layer is formed. Next, the coating layer formed on the n-type non-crystalline silicon layer  20   n  is removed. Accordingly, on the rear surface of the silicon substrate  12 , the intrinsic non-crystalline silicon layer  18  and the p-type non-crystalline silicon layer  20   p  are formed, and the n-type non-crystalline silicon layer  20   n  is formed on the intrinsic non-crystalline silicon layer  18 . 
     In addition,  FIG. 14  is a sectional view illustrating an example of a schematic configuration of a photoelectric conversion element  10 C according to an application example 3 of the first embodiment of the present invention. As illustrated in  FIG. 14 , the photoelectric conversion element  10 C is not provided with the intrinsic non-crystalline silicon layers  18  and  19  compared to the photoelectric conversion element  10 . 
     When manufacturing the photoelectric conversion element  10 C, for example, the n-type silicon layer and the coating layer are formed in order on the rear surface of the silicon substrate  12 . Next, the coating layer and the n-type non-crystalline silicon layer are patterned, a part of the silicon substrate  12  is exposed, and the n-type non-crystalline silicon layer  20   n  is formed. At this time, the coating layer is formed on the n-type non-crystalline silicon layer  20   n . Next, on the coating layer formed on the n-type non-crystalline silicon layer  20   n , and on the rear surface of the silicon substrate  12 , the p-type non-crystalline silicon layer is formed. Next, the coating layer formed on the n-type non-crystalline silicon layer  20   n  is removed. Accordingly, on the rear surface of the silicon substrate  12 , the n-type non-crystalline silicon layer  20   n  and the p-type non-crystalline silicon layer  20   p  are formed. 
     Second Embodiment 
       FIG. 15  is a sectional view illustrating a configuration of a photoelectric conversion element  50  according to a second embodiment of the present invention. The photoelectric conversion element  50  includes a silicon substrate  52 , a non-crystalline film  54 , a non-crystalline film  56 , an electrode  58 , an insulation film  60 , and an electrode  62 . 
     The silicon substrate  52  is an n-type single crystal silicon substrate. The silicon substrate  52  includes a p-type diffusion layer  64   p  and an n-type diffusion layer  64   n.    
     The p-type diffusion layer  64   p  contains, for example, boron (B) as p-type impurities. The maximum concentration of boron (B) is, for example, 1×10 18  cm −3  to 1×10 20  cm −3 . The thickness of the p-type diffusion layer  64   p  is, for example, 50 nm to 1000 nm. 
     The n-type diffusion layer  64   n  is in contact with the rear surface opposite to the light incident side of the silicon substrate  52 , and is disposed at a desired interval in the in-surface direction of the silicon substrate  52 . The n-type diffusion layer  64   n  contains, for example, phosphorus (P) as n-type impurities. The maximum concentration of phosphorus (P) is, for example, 1×10 18  cm −3  to 1×10 20  cm −3 . The thickness of the n-type diffusion layer  64   n  is, for example, 50 nm to 1000 nm. 
     Other description of the silicon substrate  52  is the same as the description of the silicon substrate  12 . 
     The non-crystalline film  54  is disposed to be in contact with the front surface on the light-incident side of the silicon substrate  52 . The non-crystalline film  54  includes at least the non-crystalline phase, and made of, for example, a-Si:H. The thickness of the non-crystalline film  54  is, for example, 1 nm to 20 nm. 
     The non-crystalline film  56  is disposed to be in contact with the non-crystalline film  54 . The non-crystalline film  54  includes at least the non-crystalline phase, and made of, for example, silicon nitride. The thickness of the non-crystalline film  56  is, for example, 50 nm to 200 nm. 
     The electrode  58  penetrates the non-crystalline film  54  and the non-crystalline film  56 , is in contact with the p-type diffusion layer  64   p  of the silicon substrate  52 , and is disposed on the non-crystalline film  56 . The electrode  58  includes a transparent conductive layer  58 A and a metal layer  58 B. The transparent conductive layer  58 A is in contact with the p-type diffusion layer  64   p . The transparent conductive layer  58 A is made of, for example, ITO. The thickness of the transparent conductive layer  58 A is, for example, 0.1 nm to 20 nm. The metal layer  58 B is in contact with the transparent conductive layer  58 A. The metal layer  58 B has silver as a main component. The metal layer  58 B may contain metal other than silver. The thickness of the metal layer  58 B is, for example, 100 nm to 1000 nm. 
     The insulation film  60  is disposed to be in contact with the rear surface of the silicon substrate  52 . The insulation film  60  is made of, for example, silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide. The thickness of the insulation film  60  is, for example, 50 nm to 1000 nm. 
     The electrode  62  penetrates the insulation film  60 , is in contact with the n-type diffusion layer  64   n  of the silicon substrate  52 , and is disposed to cover the insulation film  60 . The electrode  62  includes a transparent conductive layer  62 A and a metal layer  62 B. The transparent conductive layer  62 A is in contact with the n-type diffusion layer  64   n . The transparent conductive layer  62 A is made of, for example, ITO. The thickness of the transparent conductive layer  62 A is, for example, 0.1 nm to 20 nm. The metal layer  62 B is in contact with the transparent conductive layer  62 A. The metal layer  62 B has silver as a main component. The metal layer  62 B may contain metal other than silver. The thickness of the metal layer  62 B is, for example, 100 nm to 1000 nm. 
     [Manufacturing Method of Photoelectric Conversion Element] 
     With reference to  FIGS. 16A to 16G , a manufacturing method of the photoelectric conversion element  50  will be described. 
     First, as illustrated in  FIG. 16A , the n-type diffusion layer  64   n  is formed on the silicon substrate  52 . Specifically, first, the silicon substrate  52  is prepared. Next, the rear surface of the silicon substrate  52  is coated with the resist. Next, the resist is patterned by the photolithography method, and the resist pattern is formed. Next, by using the resist pattern as a mask, the n-type impurities, such as P and arsenic (As), are ion-injected into the silicon substrate  52 . According to this, the n-type diffusion layer  64   n  is formed on the rear surface side of the silicon substrate  52 . In addition, after the ion injection, the heat treatment may be performed for electrically vitalizing the n-type impurities. Instead of the ion injection method, a gas phase diffusion method, a solid phase diffusion method, a plasma doping method, or an ion doping method, may be used. 
     Next, as illustrated in  FIG. 16B , the insulation film  60  is formed on the entire rear surface of the silicon substrate  52 . The insulation film  60  is formed, for example, by the plasma CVD method. In addition, the insulation film  60  may be formed by an atomic layer deposition method (ALD) and a heat CVD method. 
     Next, as illustrated in  FIG. 16C , the p-type diffusion layer  64   p  is formed on the silicon substrate  52 . Specifically, the p-type impurities, such as B, gallium (Ga), or indium (In), are ion-injected into the silicon substrate  52  from the light-incident side. Accordingly, the p-type diffusion layer  64   p  is formed on the light-incident side of the silicon substrate  52 . In addition, after the ion injection, the heat treatment may be performed for electrically vitalizing the p-type impurities. In addition, not being limited to the ion injection, the p-type diffusion layer  64   p  may be formed by a gas phase diffusion method and a solid phase diffusion method. Instead of the ion injection method, a gas phase diffusion method, a solid phase diffusion method, a plasma doping method, or an ion doping method, may be used. 
     Next, as illustrated in  FIG. 16D , the non-crystalline film  54  is formed on the light-receiving surface of the silicon substrate  52 . The non-crystalline film  54  is formed, for example, by the plasma CVD. 
     Next, as illustrated in  FIG. 16E , the non-crystalline film  56  is formed on the non-crystalline film  54 . The non-crystalline film  56  is formed, for example, by the plasma CVD. 
     Next, as illustrated in  FIG. 16F , the transparent conductive layers  58 A and  62 A and metal layers  581 B and  621 B, are formed. A forming method of the transparent conductive layers  58 A and  62 A and the metal layers  581 B and  621 B is, for example, as follows. 
     First, the entire surface of the non-crystalline film  56  is coated with the resist. Next, the resist is patterned by the photolithography method, and the resist pattern is formed. Next, by using mixed liquid of hydrofluoric acid and nitric acid by using a photoresist as a mask, etching is performed with respect to a part of the non-crystalline film  56  and the non-crystalline film  54 . Next, resist pattern is removed. Accordingly, a part of the p-type diffusion layer  64   p  is exposed. Next, by the deposition method and the sputtering method, the transparent conductive layer and the metal layer are formed. Next, the transparent conductive layer and the metal layer are patterned. Accordingly, the transparent conductive layer  58 A and the metal layer  581 B are formed. 
     Next, the entire surface of the insulation film  60  is coated with the resist. Next, the resist is patterned by the photolithography method, and the resist pattern is formed. Next, by using the resist pattern as a mask, by using hydrofluoric acid, the etching is performed with respect to a part of the insulation film  60 , and the resist pattern is removed. Accordingly, a part of the n-type diffusion layer  64   n  of the silicon substrate  52  is exposed. 
     Next, by using the deposition method or the sputtering method, the transparent conductive layer  62 A and the metal layer  621 B, are formed. 
     Next, the heat treatment is performed with respect to the metal layers  581 B and  621 B, and the electrodes  58  and  62  are formed. The heat treatment is performed similar to the first embodiment. Accordingly, as illustrated in  FIG. 16G , the photoelectric conversion element  50  is obtained. 
     Even in the photoelectric conversion element  50 , similar to the photoelectric conversion element  10 , the element characteristics are improved. 
     In addition, in the photoelectric conversion element  50 , by the p-type diffusion layer  64   p  provided on the entire front surface of the silicon substrate  52 , the depletion layer is formed on the entire light-receiving surface of the silicon substrate  52 , and high carrier transmission in the horizontal direction is achieved by the p-type diffusion layer  64   p . According to this, it is possible to effectively separate electron-positive hole pair generated by the light. Furthermore, by the non-crystalline film  54  (for example, i-type a-Si:H) provided on the front surface of the silicon substrate  52 , it is possible to obtain a high passivation effect. In a case where a-Si:H is used as the non-crystalline film  54 , the passivation performance deteriorates due to high temperature processing (for example, 300° C. or higher), but in the photoelectric conversion element  50 , the low contact resistance is obtained in a low temperature process at 250° C. or lower. 
     In addition, the photoelectric conversion element  50  may be provided with the n-type diffusion layer instead of the p-type diffusion layer  64   p , and may be provided with the p-type diffusion layer instead of the n-type diffusion layer  64   n . In addition, in the photoelectric conversion element  50 , the conductive type of the silicon substrate  52  may be the p-type. 
     Application Example of Second Embodiment 
       FIG. 17  is a sectional view illustrating a schematic configuration of a photoelectric conversion element  50 A according to an application example of the second embodiment. Compared to the photoelectric conversion element  50 , instead of the non-crystalline film  54 , the photoelectric conversion element  50 A is provided with a non-crystalline film  70  and a non-crystalline film  72 . In addition, compared to the photoelectric conversion element  50 , the photoelectric conversion element  50 A is provided with an electrode  76  instead of the electrode  58 . 
     The non-crystalline film  70  includes at least the non-crystalline phase, and is made of a-Si, for example. It is preferable that the non-crystalline film  70  is made of the i-type a-Si, but may contain p-type impurities having lower concentration than the concentration of the p-type impurities contained in the non-crystalline film  72 . The thickness of the non-crystalline film  70  is, for example, 5 nm to 20 nm. The non-crystalline film  70  is in contact with the p-type diffusion layer  64   p  of the silicon substrate  50 , is disposed on the p-type diffusion layer  64   p , and passivates the silicon substrate  52 . 
     The non-crystalline film  72  includes at least non-crystalline phase, and is made of, for example, p-type a-Si:H. The film thickness of the non-crystalline film  72  is, for example, 1 nm to 30 nm. The non-crystalline film  72  is in contact with the non-crystalline film  70 , and is disposed on the non-crystalline film  70 . 
     The electrode  76  penetrates the non-crystalline film  56 , is in contact with the non-crystalline film  72 , and is disposed on the non-crystalline film  56 . The electrode  76  includes a transparent conductive layer  76 A and a metal layer  76 B. The transparent conductive layer  76 A is in contact with the non-crystalline film  72 . The transparent conductive layer  76 A is made of, for example, ITO. The thickness of the transparent conductive layer  76 A is, for example, 0.1 nm to 20 nm. The metal layer  76 B is in contact with the transparent conductive layer  76 A. The metal layer  76 B has silver as a main component. The metal layer  76 B may contain metal other than silver. The thickness of the metal layer  76 B is, for example, 100 nm to 1000 nm. 
     In the photoelectric conversion element  50 A, the electrode  76  is not directly in contact with the silicon substrate  52 , and the front surface of the silicon substrate  52  is coated with the non-crystalline film  70 . Therefore, compared to the photoelectric conversion element  50 , more excellent passivation characteristics are further obtained. As a result, the photoelectric conversion efficiency can be further improved. 
     A manufacturing method of the photoelectric conversion element  50 A may be a method in which a process of forming the non-crystalline film  54  is changed to a process of forming the non-crystalline film  70  and the non-crystalline film  72 , and in which a process of forming the electrode  58  is changed to a process of forming the electrode  76 , from the manufacturing method of the photoelectric conversion element  50 . 
     In addition, the photoelectric conversion element  50 A may not be provided with the non-crystalline film  70 . In the photoelectric conversion element  50 A, the n-type diffusion layer may be provided instead of the p-type diffusion layer  64   p , the p-type diffusion layer may be provided instead of the n-type diffusion layer  64   n , and the film made of n-type a-Si:H may be provided instead of the non-crystalline film  72 . The conductive type of the silicon substrate  52  may be changed to the p-type. 
     Third Embodiment 
       FIG. 18  is a sectional view illustrating a schematic configuration of a photoelectric conversion element  80  according to a third embodiment of the present invention. In the photoelectric conversion element  80 , a silicon substrate  82  is provided instead of the silicon substrate  52  of the photoelectric conversion element  50 , non-crystalline films  84  and  86  are provided instead of the insulation film  60 , and an electrode  88  is provided instead of the electrode  62 . Other parts are the same as those of the photoelectric conversion element  50 . 
     In the silicon substrate  82 , an n-type diffusion layer  90   n  is provided instead of the n-type diffusion layer  64   n  of the silicon substrate  52 . Other parts are the same as those of the silicon substrate  52 . 
     The n-type diffusion layer  90   n  is in contact with the entire rear surface opposite to the light-incident side of the silicon substrate  82 , and is disposed in the silicon substrate  82 . The n-type diffusion layer  90   n  has the same thickness as that of the n-type diffusion layer  64   n , and contains the n-type impurities having the same concentration as that of the n-type impurities of the n-type diffusion layer  64   n.    
     The non-crystalline thin film  84  includes at least the non-crystalline phase, and is made of, for example, i-type a-Si:H or n-type a-Si:H. In addition, the film thickness of the non-crystalline thin film  84  is, for example, 1 nm to 20 nm. The non-crystalline thin film  84  is in contact with the rear surface opposite to the light-incident side of the silicon substrate  82 , and is disposed on the silicon substrate  82 . 
     The non-crystalline thin film  86  includes at least the non-crystalline phase, and is made of, for example, silicon nitride. In addition, the film thickness of the non-crystalline thin film  86  is, for example, 50 nm to 200 nm. 
     The electrode  88  penetrates the non-crystalline thin films  84  and  86 , is in contact with the n-type diffusion layer  90   n , and is disposed on the non-crystalline thin film  86 . The electrode  88  includes a transparent conductive layer  88 A and a metal layer  88 B. The transparent conductive layer  88 A is in contact with the n-type diffusion layer  90   n . The transparent conductive layer  88 A is made of, for example, ITO. The thickness of the transparent conductive layer  88 A is, for example, 0.1 nm to 20 nm. The metal layer  88 B is in contact with the transparent conductive layer  88 A. The metal layer  88 B has silver as a main component. The metal layer  88 B may contain metal other than silver. The thickness of the metal layer  88 B is, for example, 100 nm to 1000 nm. 
     In the photoelectric conversion element  80 , the front surface on the light-incident side of the silicon substrate  82  is passivated by the non-crystalline thin film  54 , and the rear surface of the silicon substrate  82  is passivated by the non-crystalline thin film  84 . Accordingly, high photoelectric conversion efficiency is obtained. Furthermore, the light may be incident on the rear surface side of the silicon substrate  82 . 
     [Manufacturing Method of Photoelectric Conversion Element] 
     With reference to  FIGS. 19A to 19F , a manufacturing method of the photoelectric conversion element  80  will be described. 
     First, as illustrated in  FIG. 19A , the n-type diffusion layer  90   n  is formed on the silicon substrate  82 . Specifically, n-type impurities, such as P and arsenic (As), are ion-injected into the silicon substrate  82 , and the n-type diffusion layer  90   n  is formed on the rear surface side of the silicon substrate  82 . In addition, after the ion injection, the heat treatment may be performed for electrically vitalizing the n-type impurities. Instead of the ion injection method, a gas phase diffusion method, a solid phase diffusion method, a plasma doping method, or an ion doping method, may be used. 
     Next, as illustrated in  FIG. 19B , the p-type diffusion layer  64   p  is formed on the silicon substrate  82 . Specifically, p-type impurities, such as B, gallium (Ga), or indium (In), are ion-injected into the silicon substrate  82  from the light-incident side. Accordingly, the p-type diffusion layer  64   p  is formed on the light-incident side of the silicon substrate  82 . In addition, after the ion injection, the heat treatment may be performed for electrically vitalizing the p-type impurities. In addition, not being limited to the ion injection, the p-type diffusion layer  64   p  may be formed by a gas phase diffusion method and a solid phase diffusion method. 
     Next, as illustrated in  FIG. 19C , the non-crystalline films  54  and  56  are formed on the light-receiving surface of the silicon substrate  82 . The non-crystalline films  54  and  56  are formed, for example, by the plasma CVD. 
     Next, as illustrated in  FIG. 19D , the non-crystalline thin films  84  and  86  are layered in order on the rear surface of the silicon substrate  82 . The non-crystalline films  84  and  86  are formed, for example, by the plasma CVD. 
     Next, as illustrated in  FIG. 19E , the transparent conductive layers  58 A and  88 A and the metal layers  581 B and  881 B are formed. A forming method of the transparent conductive layers  58 A and  88 A and the metal layers  581 B and  881 B is, for example, as follows. 
     First, the entire surface of the non-crystalline film  56  is coated with the resist. Next, the resist is patterned by the photolithography method, and the resist pattern is formed. Next, by using a photoresist as a mask, etching is performed with respect to a part of the non-crystalline film  56  and the non-crystalline film  54 . Next, resist pattern is removed. Accordingly, a part of the p-type diffusion layer  64   p  is exposed. Next, by the deposition method and the sputtering method, the transparent conductive layer and the metal layer are formed. Next, the transparent conductive layer and the metal layer are patterned. Accordingly, the transparent conductive layer  58 A and the metal layer  581 B are formed. 
     Next, the entire surface of the non-crystalline film  86  is coated with the resist. Next, the resist is patterned by the photolithography method, and the resist pattern is formed. Next, by using the resist pattern as a mask, the etching is performed with respect to a part of the non-crystalline film  86 , and the resist pattern is removed. Accordingly, a part of n-type diffusion layer  64   n  of the silicon substrate  82  is exposed. 
     Next, by using the deposition method and the sputtering method, the transparent conductive layer and the metal layer are formed. Next, the transparent conductive layer and the metal layer are patterned. Accordingly, the transparent conductive layer  88 A and the metal layer  881 B are formed. 
     Next, the heat treatment is performed with respect to the metal layers  581 B and  881 B, and the electrodes  58  and  88  are formed. The heat treatment is performed similar to the first embodiment. Accordingly, as illustrated in  FIG. 19F , the photoelectric conversion element  80  is obtained. 
     In the photoelectric conversion element  80 , similar to the photoelectric conversion element  10 , the element characteristics are improved. 
     In addition, in the photoelectric conversion element  80 , the n-type diffusion layer may be provided instead of the p-type diffusion layer  64   p , and the p-type diffusion layer may be provided instead of the n-type diffusion layer  90   n . In this case, the non-crystalline thin film  54  is made of i-type a-Si:H or n-type a-Si:H, and the non-crystalline thin film  84  is made of i-type a-Si:H or p-type a-Si:H. 
     Application Example 1 of Third Embodiment 
       FIG. 20  is a vertically sectional view illustrating a schematic configuration of a photoelectric conversion element  80 A according to an application example 1 of the third embodiment. Compared to the photoelectric conversion element  80 , the photoelectric conversion element  80 A is provided with the non-crystalline film  70  and the non-crystalline film  72  instead of the non-crystalline film  54 . Instead of the non-crystalline film  84 , a non-crystalline film  94  and a non-crystalline film  96  are provided. Instead of the electrode  58 , the electrode  76  is provided. Instead of the electrode  88 , an electrode  98  is provided. 
     The non-crystalline thin film  94  includes at least the non-crystalline phase, and is made of, for example, i-type a-Si:H or n-type a-Si:H. The non-crystalline thin film  94  is in contact with the rear surface of the silicon substrate  82 , and is disposed on the rear surface of the silicon substrate  82 . 
     The non-crystalline thin film  96  includes at least the non-crystalline phase, and is made of, for example, n-type a-Si. The non-crystalline thin film  96  is in contact with the non-crystalline film  94 , and is disposed on non-crystalline thin film  941 . 
     The electrode  98  penetrates the non-crystalline thin film  86 , is in contact with the non-crystalline thin film  96 , and is disposed on the non-crystalline thin film  86 . The electrode  98  includes a transparent conductive layer  98 A and a metal layer  98 B. The transparent conductive layer  98 A is in contact with the non-crystalline film  96 . The transparent conductive layer  98 A is made of, for example, ITO. The thickness of the transparent conductive layer  98 A is, for example, 0.1 nm to 20 nm. The metal layer  98 B is in contact with the transparent conductive layer  98 A. The metal layer  98 B has silver as a main component. The metal layer  98 B may contain metal other than silver. The thickness of the metal layer  98 B is, for example, 100 nm to 1000 nm. 
     A manufacturing method of the photoelectric conversion element  80 A may be a method in which a process of forming the non-crystalline film  54  is changed to a process of forming the non-crystalline film  70  and the non-crystalline film  72 , a process of forming the non-crystalline film  84  is changed to a process of forming the non-crystalline film  94  and the non-crystalline film  96 , a process of forming the electrode  58  is changed to a process of forming the electrode  76 , and a process of forming the electrode  88  is changed to a process of forming the electrode  98 , from the manufacturing method of the photoelectric conversion element  80 . 
     In the configurations of the photoelectric conversion element  80 A, the non-crystalline films  70  and  72  are formed between the electrode  76  and the silicon substrate  82 , and the non-crystalline films  94  and  96  are formed between the electrode  98  and the silicon substrate  82 . Therefore, compared to the photoelectric conversion element  80 , a higher passivation effect is obtained. 
     In addition, the photoelectric conversion element  80 A may not be provided with the non-crystalline films  70  and  94 . In the photoelectric conversion element  80 A, the n-type diffusion layer may be provided instead of the p-type diffusion layer  64   p , the p-type diffusion layer may be provided instead of the n-type diffusion layer  90   n , a film made of n-type a-Si:H may be provided instead of the non-crystalline film  72 , and a film made of p-type a-Si:H may be provided instead of the non-crystalline film  96 . The conductive type of the silicon substrate  82  may be changed to the p-type. 
     Application Example 2 of Third Embodiment 
       FIG. 21  is a vertically sectional view illustrating a schematic configuration of a photoelectric conversion element  80 B according to an application example 2 of the third embodiment. Compared to the photoelectric conversion element  80 , instead of the non-crystalline film  54 , the photoelectric conversion element  80 B is provided with the non-crystalline film  70  and the non-crystalline film  72 . Instead of the electrode  58 , the electrode  76  is provided. 
     A manufacturing method of the photoelectric conversion element  80 B may be a method in which a process of forming the non-crystalline film  54  is changed to a process of forming the non-crystalline film  70  and the non-crystalline film  72 , and a process of forming the electrode  58  is changed to a process of forming the electrode  76 , from the manufacturing method of the photoelectric conversion element  80 . 
     In addition, the photoelectric conversion element  80 B may not be provided with the non-crystalline film  70 . In the photoelectric conversion element  80 B, the n-type diffusion layer may be provided instead of the p-type diffusion layer  64   p , the p-type diffusion layer may be provided instead of the n-type diffusion layer  90   n , and a film made of n-type a-Si:H may be provided instead of the non-crystalline film  72 . The conductive type of the silicon substrate  82  may be changed to the p-type. 
     Fourth Embodiment 
       FIG. 22  is a schematic view illustrating a configuration of the photoelectric conversion module provided with the photoelectric conversion element according to the embodiment. With reference to  FIG. 22 , a photoelectric conversion module  1000  includes a plurality of photoelectric conversion elements  1001 , a cover  1002 , output terminals  1003  and  1004 . 
     The plurality of photoelectric conversion elements  1001  are disposed in a shape of an array, and are connected to each other in series. Instead of being connected to each other in series, parallel connection or connection in which the series connection and the parallel connection are combined, may be employed. Each of the plurality of photoelectric conversion elements  1001  is made of any of the photoelectric conversion elements  10 ,  10 A,  10 B,  10 C,  50 ,  50 A,  80 ,  80 A, and  80 B. 
     The cover  1002  is made of pollution-resistant cover, and covers the plurality of photoelectric conversion elements  1001 . 
     The output terminal  1003  is connected to the photoelectric conversion element  1001  disposed at one end among the plurality of photoelectric conversion elements  1001  that are connected to each other in series. 
     The output terminal  1004  is connected to the photoelectric conversion element  1001  disposed at the other end among the plurality of photoelectric conversion elements  1001  that are connected to each other in series. 
     As described above, the characteristics of the photoelectric conversion elements  10 ,  10 A,  10 B,  10 C,  50 ,  50 A,  80 ,  80 A, and  80 B, are improved. Therefore, the performance of the photoelectric conversion module  1000  can be improved. 
     In addition, not being limited to the configuration illustrated in  FIG. 22 , the photoelectric conversion module according to the fourth embodiment may be configured in any manner as long as any of the photoelectric conversion elements  10 ,  10 A,  10 B,  10 C,  50 ,  50 A,  80 ,  80 A, and  80 B, is used. 
     Fifth Embodiment 
       FIG. 23  is a schematic view illustrating a configuration of a solar photovoltaic power generation system provided with the photoelectric conversion element according to the embodiment. With reference to  FIG. 23 , a solar photovoltaic power generation system  1100  includes a photoelectric conversion module array  1101 , a connection box  1102 , a power conditioner  1103 , a distribution board  1104 , and a power meter  1105 . 
     The connection box  1102  is connected to the photoelectric conversion module array  1101 . The power conditioner  1103  is connected to the connection box  1102 . The distribution board  1104  is connected to the power conditioner  1103  and an electrical machine  1110 . The power meter  1105  is connected to the distribution board  1104  and a commercial power system. 
     The photoelectric conversion module array  1101  converts sunlight into electricity, generates DC power, and supplies the generated DC power to the connection box  1102 . 
     The connection box  1102  receives the DC power generated by the photoelectric conversion module array  1101 , and supplies the received DC power to the power conditioner  1103 . 
     The power conditioner  1103  converts the DC power received from the connection box  1102  into AC power, and supplies the converted AC power to the distribution board  1104 . 
     The distribution board  1104  supplies the AC power received from the power conditioner  1103 , and/or commercial power received via the power meter  1105 , to the electrical machine  1110 . In addition, when the AC power received from the power conditioner  1103  is greater than power consumption of the electrical machine  1110 , the distribution board  1104  supplies residual AC power to the commercial power system via the power meter  1105 . 
     The power meter  1105  measures the power in the direction toward the distribution board  1104  from the commercial power system, and measures the power in the direction toward the commercial power system from the distribution board  1104 . 
       FIG. 24  is a schematic view illustrating a configuration of the photoelectric conversion module array  1101  illustrated in  FIG. 23 . With reference to  FIG. 24 , the photoelectric conversion module array  1101  includes a plurality of photoelectric conversion modules  1120  and output terminals  1121  and  1122 . 
     The plurality of photoelectric conversion modules  1120  are disposed in a shape of an array, and are connected to each other in series. Each of the plurality of photoelectric conversion modules  1120  is made of the photoelectric conversion module  1000  illustrated in  FIG. 22 . 
     The output terminal  1121  is connected to the photoelectric conversion module  1120  which is positioned at one end among the plurality of photoelectric conversion modules  1120  that are connected to each other in series. 
     The output terminal  1122  is connected to the photoelectric conversion module  1120  which is positioned at the other end among the plurality of photoelectric conversion modules  1120  that are connected to each other in series. 
     An operation in the solar photovoltaic power generation system  1100  will be described. The photoelectric conversion module array  1101  converts the sunlight into electricity, generates the DC power, and supplies the generated DC power to the power conditioner  1103  via the connection box  1102 . 
     The power conditioner  1103  converts the DC power received from the photoelectric conversion module array  1101  into the AC power, and supplies the converted AC power to the distribution board  1104 . 
     When the AC power received from the power conditioner  1103  is equal to or greater than the power consumption of the electrical machine  1110 , the distribution board  1104  supplies the AC power received from the power conditioner  1103  to the electrical machine  1110 . In addition, the distribution board  1104  supplies the residual AC power to the commercial power system via the power meter  1105 . 
     In addition, when the AC power received from the power conditioner  1103  is less than the power consumption of the electrical machine  1110 , the distribution board  1104  supplies the AC power received from the commercial power system and the AC power received from the power conditioner  1103 , to the electrical machine  1110 . 
     As described above, the solar photovoltaic power generation system  1100  is provided with any of the photoelectric conversion elements  10 ,  10 A,  10 B,  10 C,  50 ,  50 A,  80 ,  80 A, and  80 B in which the element characteristics are improved. Therefore, performance of the solar photovoltaic power generation system  1100  can be improved. 
     In addition, not being limited to configurations illustrated in  FIGS. 23 and 24 , the solar photovoltaic power generation system according to the fifth embodiment may be configured in any manner as long as any of the photoelectric conversion elements  10 ,  10 A,  10 B,  10 C,  50 ,  50 A,  80 ,  80 A, and  80 B is used. 
     Sixth Embodiment 
       FIG. 25  is a schematic view illustrating a configuration of the solar photovoltaic power generation system provided with the photoelectric conversion element according to the embodiment. With reference to  FIG. 25 , a solar photovoltaic power generation system  1200  includes subsystems  1201  to  120   n  (n is an integer which is equal to or greater than 2), power conditioners  1211  to  121   n , and a converter  1221 . The solar photovoltaic power generation system  1200  is a solar photovoltaic power generation system of which the dimension is greater than that of the solar photovoltaic power generation system  1100  illustrated in  FIG. 23 . 
     The power conditioners  1211  to  121   n  are respectively connected to the subsystems  1201  to  120   n.    
     The converter  1221  is connected to the power conditioners  1211  to  121   n  and the commercial power system. 
     Each of the subsystems  1201  to  120   n  is made of module systems  1231  to  123   j  (j is an integer which is equal to or greater than 2). 
     Each of the module systems  1231  to  123   j  includes photoelectric conversion module arrays  1301  to  130   i  (i is an integer which is equal to or greater than 2), connection boxes  1311  to  131   i , and a power collection box  1321 . 
     Each of the photoelectric conversion module arrays  1301  to  130   i  is configured the same as the photoelectric conversion module array  1101  illustrated in  FIG. 34 . 
     The connection boxes  1311  to  131   i  are respectively connected to the photoelectric conversion module arrays  1301  to  130   i.    
     The power collection box  1321  is connected to the connection boxes  1311  to  131   i . In addition, j power collection boxes  1321  of the subsystem  1201  are connected to the power conditioner  1211 . j power collection boxes  1321  of the subsystem  1202  are connected to the power conditioner  1212 . Hereinafter, similarly, j power collection boxes  1321  of the subsystem  120   n  are connected to the power conditioner  121   n.    
     i photoelectric conversion module arrays  1301  to  130   i  of the module system  1231  convert the sunlight into electricity, generate the DC power, and supply the generated DC power to the power collection box  1321  via each of the connection boxes  1311  to  131   i . i photoelectric conversion module arrays  1301  to  130   i  of the  1232  convert the sunlight into electricity, generate the DC power, and supply the generated DC power to the power collection box  1321  via each of the connection boxes  1311  to  131   i . Hereinafter, similarly, i photoelectric conversion module arrays  1301  to  130   i  of the module system  123   j  convert the sunlight into electricity, generate the DC power, and supply the generated DC power to the power collection box  1321  via the connection boxes  1311  to  131   i.    
     In addition, j power collection boxes  1321  of the subsystem  1201  supply the DC power to the power conditioner  1211 . 
     j power collection boxes  1321  of the subsystem  1202  similarly supply the DC power to the power conditioner  1212 . 
     Hereinafter, similarly, j power collection boxes  1321  of the subsystem  120   n  supply the DC power to the power conditioner  121   n.    
     The power conditioners  1211  to  121   n  respectively convert the DC power received from the subsystems  1201  to  120   n  to the AC power, and supply the converted AC power to the converter  1221 . 
     The converter  1221  receives the AC power from the power conditioners  1211  to  121   n , converts a voltage level of the received AC power, and supplies the power to the commercial power system. 
     As described above, the solar photovoltaic power generation system  1200  is provided with any of the photoelectric conversion elements  10 ,  10 A,  10 B,  10 C,  50 ,  50 A,  80 ,  80 A, and  80 B in which the element characteristics are improved. Therefore, the performance of the solar photovoltaic power generation system  1200  can be improved. 
     In addition, not being limited to configurations illustrated in  FIG. 25 , the solar photovoltaic power generation system according to the sixth embodiment may be configured in any manner as long as any of the photoelectric conversion elements  10 ,  10 A,  10 B,  10 C,  50 ,  50 A,  80 ,  80 A, and  80 B is used. 
     Above, the embodiments of the present invention are described in detail, but the description is merely an example, but the description is merely an example, and the present invention is not limited to the above-described embodiments. 
     For example, in the first embodiment, the silicon substrate  12  may be the p-type single crystal silicon substrate. In this case, it is preferable that the width dimension of the p-type non-crystalline silicon layer  20   p  becomes smaller than the width dimension of the n-type non-crystalline silicon layer  20   n  in the in-surface direction of the silicon substrate  12 . This is similar in the application examples 1 to 3. 
     In the first embodiment, the texture structure on the light-receiving surface side of the silicon substrate  12 , and the texture structure of the rear surface side, are not necessary configuration elements. This is similar in the application examples 1 to 3. 
     In the first embodiment, the passivation film  14  and the reflection preventing film  16  are not necessary configuration elements. This is similar in the application examples 1 to 3. 
     In the first embodiment, the high concentration region may be formed on the light-receiving surface side of the silicon substrate  12 . The high concentration region is a region in which the impurities having the same conductive type as the silicon substrate  12  are doped to higher concentration than the silicon substrate  12 . The high concentration region functions as a front surface field (FSF). This is similar in the application examples 1 to 3.