Patent Publication Number: US-2020303563-A1

Title: Nonvolatile charge trap memory device having a high dielectric constant blocking region

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is a continuation of application Ser. No. 13/436,875, filed Mar. 31, 2012, Now U.S. Pat. No. 9,431,549, Issued Aug. 30, 2016, which is a continuation-in-part of co-pending U.S. application Ser. No. 13/114,889, filed May 24, 2011, Now U.S. Pat. No. 8,860,122, Issued Oct. 14, 2014, which is a divisional application of U.S. patent application Ser. No. 12/030,644, filed Feb. 13, 2008, Now abandoned, which claims the benefit of U.S. Provisional Application No. 61/007,566, filed Dec. 12, 2007, the entire contents of which are hereby incorporated by reference herein 
    
    
     TECHNICAL FIELD 
     The invention is in the field of semiconductor devices. 
     BACKGROUND 
     For the past several decades, the scaling of features in integrated circuits has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of semiconductor chips. For example, shrinking transistor size allows for the incorporation of an increased number of memory devices on a chip, lending to the fabrication of products with increased capacity. The drive for ever-more capacity, however, is not without issue. The necessity to optimize the performance of each device becomes increasingly significant. 
     Non-volatile semiconductor memories typically use stacked floating gate type field-effect-transistors. In such transistors, electrons are injected into a floating gate of a memory cell to be programmed by biasing a control gate and grounding a body region of a substrate on which the memory cell is formed. An oxide-nitride-oxide (ONO) stack is used as either a charge storing layer, as in a semiconductor-oxide-nitride-oxide-semiconductor (SON OS) transistor, or as an isolation layer between the floating gate and control gate, as in a split gate flash transistor.  FIG. 1  illustrates a cross-sectional view of a conventional nonvolatile charge trap memory device. 
     Referring to  FIG. 1 , semiconductor device  100  includes a SO NOS gate stack  104  including a conventional ONO portion  106  formed over a silicon substrate  102 . Semiconductor device  100  further includes source and drain regions  110  on either side of SONOS gate stack  104  to define a channel region  112 . SONOS gate stack  104  includes a poly-silicon gate layer  108  formed above and in contact with ONO portion  106 . Polysilicon gate layer  108  is electrically isolated from silicon substrate  102  by ONO portion  106 . ONO portion  106  typically includes a tunnel oxide layer  106 A, a nitride or oxynitride charge-trapping layer  106 B, and a top oxide layer  106 C overlying nitride or oxynitride layer  106 B. 
     One problem with conventional SONOS transistors is the limited program and erase window achievable with a conventional blocking layer  106 C, inhibiting optimization of semiconductor device  100 . For example,  FIG. 2  is a plot  200  of Threshold Voltage (V) as a function of Pulse Width (s) in erase mode for a conventional nonvolatile charge trap memory device. Referring to  FIG. 2 , line  202  is a measure of decreasing threshold voltage (in Volts) as a function of time (in seconds) in response to an erase-mode voltage being applied to a gate electrode in a conventional SONOS transistor. As indicated by region  204  of line  202 , the ability of the erase mode to decrease the threshold voltage of the gate electrode saturates with time, restricting an erase event to a relatively shallow erase of the gate electrode. The shallow erase limits the differential between erase and program modes for a SONGS-transistor and thus limits the performance of such a device. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Embodiments of the present invention are illustrated by way of example, and not limitation, in the figures of the accompanying drawings in which: 
         FIG. 1  (Prior Art) illustrates a cross-sectional view of a conventional nonvolatile charge trap memory device. 
         FIG. 2  (Prior Art) is a plot of Threshold Voltage (V) as a function of Pulse Width (s) in erase mode for a conventional nonvolatile charge trap memory device. 
         FIG. 3  is a plot of Threshold Voltage (V) as a function of Pulse Width (s) in erase mode for a nonvolatile charge trap memory device having a high dielectric constant blocking region, in accordance with an embodiment of the present invention. 
         FIG. 4  is a plot of Charging Current (A/cm2) as a function of Gate Voltage (V) for four different nonvolatile charge trap memory devices, in accordance with an embodiment of the present invention. 
         FIG. 5  illustrates a cross-sectional view of a nonvolatile charge trap memory device having a multi-layer high dielectric constant blocking region, in accordance with an embodiment of the present invention. 
         FIG. 6  illustrates a cross-sectional view of a nonvolatile charge trap memory device having a graded high dielectric constant blocking layer, in accordance with an embodiment of the present invention. 
         FIG. 7  A illustrates a cross-sectional view representing an operation in the formation of a nonvolatile charge trap memory device having a multi-layer high dielectric constant blocking region, in accordance with an embodiment of the present invention. 
         FIG. 7B  illustrates a cross-sectional view representing an operation in the formation of a nonvolatile charge trap memory device having a multi-layer high dielectric constant blocking region, in accordance with an embodiment of the present invention. 
         FIG. 7C  illustrates a cross-sectional view representing an operation in the formation of a nonvolatile charge trap memory device having a multi-layer high dielectric constant blocking region, in accordance with an embodiment of the present invention. 
         FIG. 7D  illustrates a cross-sectional view representing an operation in the formation of a nonvolatile charge trap memory device having a multi-layer high dielectric constant blocking region, in accordance with an embodiment of the present invention. 
         FIG. 7E  illustrates a cross-sectional view representing an operation in the formation of a nonvolatile charge trap memory device having a multi-layer high dielectric constant blocking region, in accordance with an embodiment of the present invention. 
         FIG. 7F  illustrates a cross-sectional view representing an operation in the formation of a nonvolatile charge trap memory device having a multi-layer high dielectric constant blocking region, in accordance with an embodiment of the present invention. 
         FIG. 7G  illustrates a cross-sectional view representing an operation in the formation of a nonvolatile charge trap memory device having a multi-layer high dielectric constant blocking region, in accordance with an embodiment of the present invention. 
         FIG. 7H  illustrates a cross-sectional view representing an operation in the formation of a nonvolatile charge trap memory device having a multi-layer high dielectric constant blocking region, in accordance with an embodiment of the present invention. 
         FIG. 7I  illustrates a cross-sectional view representing an operation in the formation of a nonvolatile charge trap memory device having a multi-layer high dielectric constant blocking region, in accordance with an embodiment of the present invention. 
         FIG. 8A  illustrates a cross-sectional view representing an operation in the formation of a nonvolatile charge trap memory device having a graded high dielectric constant blocking layer, in accordance with an embodiment of the present invention. 
         FIG. 8B  illustrates a cross-sectional view representing an operation in the formation of a nonvolatile charge trap memory device having a graded high dielectric constant blocking layer, in accordance with an embodiment of the present invention. 
         FIG. 8C  illustrates a cross-sectional view representing an operation in the formation of a nonvolatile charge trap memory device having a graded high dielectric constant blocking layer, in accordance with an embodiment of the present invention. 
         FIG. 9A  illustrates a non-planar multigate device including a graded or multi-layer high dielectric constant blocking region. 
         FIG. 9B  illustrates a cross-sectional view of the non-planar multigate device of  FIG. 9A  including a multi-layer high dielectric constant blocking region. 
         FIG. 9C  illustrates a cross-sectional view of the non-planar multigate device of  FIG. 9A  including a graded high dielectric constant blocking region. 
         FIG. 10  illustrates a flow diagram depicting sequences of particular modules employed in the fabricating a non-planar multigate device including a graded or multi-layer high dielectric constant blocking region. 
         FIGS. 11A and 11B  illustrate a non-planar multigate device including a multi-layer high dielectric constant blocking region and a horizontal nanowire channel. 
         FIG. 11C  illustrates a cross-sectional view of a vertical string of non-planar multigate devices of  FIG. 11A . 
         FIGS. 12A and 12B  illustrate a non-planar multigate device including a multi-layer high dielectric constant blocking region and a vertical nanowire channel. 
         FIG. 13A through 13G  illustrate a gate first scheme for fabricating the non-planar multigate device of  FIG. 12A . 
         FIG. 14A through 14F  illustrate a gate last scheme for fabricating the non-planar multigate device of  FIG. 12A . 
     
    
    
     DETAILED DESCRIPTION 
     A nonvolatile charge trap memory device and a method to form the same is described herein. In the following description, numerous specific details are set forth, such as specific dimensions, in order to provide a thorough understanding of the present invention. It will be apparent to one skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known processing steps, such as patterning steps or wet chemical cleans, are not described in detail in order to not unnecessarily obscure the present invention. Furthermore, it is to be understood that the various embodiments shown in the Figures are illustrative representations and are not necessarily drawn to scale. 
     Disclosed herein is a nonvolatile charge trap memory device. The device may include a substrate having a channel region and a pair of source and drain regions. A gate stack may be formed above the substrate over the channel region and between the pair of source and drain regions. In an embodiment, the gate stack includes a high dielectric constant blocking region. In one embodiment, the high dielectric constant blocking region is a bi-layer blocking dielectric region having a first dielectric layer disposed directly above a charge-trapping layer and a second dielectric layer disposed directly above the first dielectric layer and directly below a gate layer. The dielectric constant of the first dielectric layer is lower than the dielectric constant of the second dielectric layer. In another embodiment, the high dielectric constant blocking region is a graded blocking dielectric layer disposed directly above a charge-trapping layer and directly below a gate layer. The dielectric constant of the graded blocking dielectric layer has a low-to-high gradient in the direction from the charge-trapping layer to the gate layer. 
     A nonvolatile charge trap memory device including a high dielectric constant blocking region may exhibit a relatively large program and erase window, enabling improved performance of such a device. For example, in accordance with an embodiment of the present invention,  FIG. 3  is a plot  300  of Threshold Voltage (V) as a function of Pulse Width (s) in erase mode for a nonvolatile charge trap memory device having a high dielectric constant blocking region. Referring to  FIG. 3 , line  302  is a measure of decreasing threshold voltage (in Volts) as a function of time (in seconds) in response to an erase-mode voltage being applied to a gate electrode in a nonvolatile charge trap memory transistor. As indicated by region  304  of line  302 , the ability of the erase mode to decrease the threshold voltage of the gate electrode does not substantially saturate with time, allowing for a relatively deep erase of the gate electrode. In one embodiment, the deep erase enables a greater differential between erase and program modes for a nonvolatile charge trap memory transistor. 
     The ability to achieve a deep erase in a nonvolatile charge trap memory device including a high dielectric constant blocking region may result from the ability of the high dielectric constant blocking region to mitigate back-streaming of electrons. Such back-streaming otherwise proceeds into a charge-trapping layer that is subject to an erase-mode voltage application. For example, in accordance with an embodiment of the present invention,  FIG. 4  is a plot  400  of Charging Current (A/cm2) as a function of Gate Voltage (V) for four different nonvolatile charge trap memory devices. Referring to  FIG. 4 , lines  402 ,  404 ,  406  and  408  are measures of increasing charging current (“backstreaming” in Amperes per square centimeter) as a function of gate voltage (in Volts) in response to an erase-mode voltage being applied to gate electrodes in a series of four nonvolatile charge trap memory transistors, respectively. Lines  402 ,  404 ,  406  and  408  represent data obtained from nonvolatile charge trap memory transistors having progressively physically thicker blocking dielectric layers, respectively, but all having approximately the same equivalent oxide thickness (EOT), i.e. the same electrical thickness. In one embodiment, the amount of gate voltage required to produce a significant back-streaming event increases with increasing physical thickness of the blocking dielectric layer, as depicted in  FIG. 4 . Thus, in a specific embodiment, the higher the dielectric constant of the blocking dielectric layer, the less back-streaming observed at a given voltage and at a given electrical thickness. In comparison with a conventional memory device, the reduction in back-streaming may enable a greater program and erase window, improving the performance of a nonvolatile charge trap memory device at a given electrical thickness. However, the same effect may be exploited to scale down the electrical parameters of a nonvolatile charge trap memory device. For example, in accordance with an alternative embodiment of the present invention, a high dielectric constant blocking region has a smaller EOT than the blocking layer of a conventional memory device. In a specific alternative embodiment, a high dielectric constant blocking region has a smaller EOT than the blocking layer of a conventional memory device, and a nonvolatile charge trap memory device incorporating the high dielectric constant blocking region is operated at a lower gate voltage than the gate voltage used for the conventional memory device. 
     A nonvolatile charge trap memory device may include a multi-layer blocking dielectric region.  FIG. 5  illustrates a cross-sectional view of a nonvolatile charge trap memory device having a multi-layer high dielectric constant blocking region, in accordance with an embodiment of the present invention. 
     Referring to  FIG. 5 , semiconductor device  500  includes a gate stack  504  formed over a substrate  502 . Semiconductor device  500  further includes source and drain regions  510  in substrate  502  on either side of gate stack  504 , defining a channel region  512  in substrate  502  underneath gate stack  504 . Gate stack  504  includes a tunnel dielectric layer  504 A, a charge-trapping layer  504 B, a multi-layer blocking dielectric region  504 C, and a gate layer  504 D. Thus, gate layer  504 D is electrically isolated from substrate  502 . Multi-layer blocking dielectric region  504 C includes a first dielectric layer  506  disposed above charge-trapping layer  504 B and a second dielectric layer  508  disposed above first dielectric layer  506  and below gate layer  504 D. A pair of dielectric spacers  514  isolates the sidewalls of gate stack  504 . 
     Semiconductor device  500  may be any nonvolatile charge trap memory device. In one embodiment, semiconductor device  500  is a Flash-type device wherein the charge-trapping layer is a conductor layer or a semiconductor layer. In accordance with another embodiment of the present invention, semiconductor device  500  is a SONOS-type device wherein the charge-trapping layer is an insulator layer. By convention, SONOS stands for “Semiconductor-Oxide-Nitride-Oxide-Semiconductor,” where the first “Semiconductor” refers to the channel region material, the first “Oxide” refers to the tunnel dielectric layer, “Nitride” refers to the charge-trapping dielectric layer, the second “Oxide” refers to the blocking dielectric layer and the second “Semiconductor” refers to the gate layer. A SONOS-type device, however, is not limited to these specific materials, as described below. 
     Substrate  502  and, hence, channel region  512 , may be composed of any material suitable for semiconductor device fabrication. In one embodiment, substrate  502  is a bulk substrate composed of a single crystal of a material which may include, but is not limited to, silicon, germanium, silicon-germanium or a III-V compound semiconductor material. In another embodiment, substrate  502  includes a bulk layer with a top epitaxial layer. In a specific embodiment, the bulk layer is composed of a single crystal of a material which may include, but is not limited to, silicon, germanium, silicon-germanium, a III-V compound semiconductor material and quartz, while the top epitaxial layer is composed of a single crystal layer which may include, but is not limited to, silicon, germanium, silicon-germanium and a III-V compound semiconductor material. In another embodiment, substrate  502  includes a top epitaxial layer on a middle insulator layer which is above a lower bulk layer. The top epitaxial layer is composed of a single crystal layer which may include, but is not limited to, silicon (i.e. to form a silicon-on-insulator (SOI) semiconductor substrate), germanium, silicon-germanium and an III-V compound semiconductor material. The insulator layer is composed of a material which may include, but is not limited to, silicon dioxide, silicon nitride and silicon oxy-nitride. The lower bulk layer is composed of a single crystal which may include, but is not limited to, silicon, germanium, silicon-germanium, an III-V compound semiconductor material and quartz. Substrate  502  and, hence, channel region  512 , may include dopant impurity atoms. In a specific embodiment, channel region  512  is doped P-type and, in an alternative embodiment, channel region  512  is doped N-type. 
     Source and drain regions  510  in substrate  502  may be any regions having opposite conductivity to channel region  512 . For example, in accordance with an embodiment of the present invention, source and drain regions  510  are N-type doped regions while channel region  512  is a P-type doped region. In one embodiment, substrate  502  and, hence, channel region  512 , is composed of boron-doped single-crystal silicon having a boron concentration in the range of 1×1015-1×1019 atoms/cm3. Source and drain regions  510  are composed of phosphorous- or arsenic-doped regions having a concentration of N-type dopants in the range of 5×1016-5×1019 atoms/cm3. In a specific embodiment, source and drain regions  510  have a depth in substrate  502  in the range of 80-200 nanometers. In accordance with an alternative embodiment of the present invention, source and drain regions  510  are P-type doped regions while channel region  512  is an N-type doped region. 
     Tunnel dielectric layer  504 A may be any material and have any thickness suitable to allow charge carriers to tunnel into the charge-trapping layer under an applied gate bias while maintaining a suitable barrier to leakage when the device is unbiased. In one embodiment, tunnel dielectric layer  504 A is formed by a thermal oxidation process and is composed of silicon dioxide or silicon oxy-nitride, or a combination thereof. In another embodiment, tunnel dielectric layer  504 A is formed by chemical vapor deposition or atomic layer deposition and is composed of a dielectric layer which may include, but is not limited to, silicon nitride, aluminum oxide, hafnium oxide, zirconium oxide, hafnium silicate, zirconium silicate, hafnium oxy-nitride, hafnium zirconium oxide and lanthanum oxide. In another embodiment, tunnel dielectric layer  504 A is a bi-layer dielectric region including a bottom layer of a material such as, but not limited to, silicon dioxide or silicon oxy-nitride and a top layer of a material which may include, but is not limited to, silicon nitride, aluminum oxide, hafnium oxide, zirconium oxide, hafnium silicate, zirconium silicate, hafnium oxy-nitride, hafnium zirconium oxide and lanthanum oxide. Thus, in one embodiment, tunnel dielectric layer  504 A includes a high-K dielectric portion. In a specific embodiment, tunnel dielectric layer  504 A has a thickness in the range of 1-10 nanometers. 
     Charge-trapping layer may be any material and have any thickness suitable to store charge and, hence, raise the threshold voltage of gate stack  504 . In accordance with an embodiment of the present invention, charge-trapping layer  504 B is formed by a chemical vapor deposition process and is composed of a dielectric material which may include, but is not limited to, stoichiometric silicon nitride, silicon-rich silicon nitride and silicon oxy-nitride. In one embodiment, charge-trapping layer  504 B is composed of a bi-layer silicon oxy-nitride region. For example, in a specific embodiment, charge-trapping layer  504 B includes an oxygen-rich portion and a silicon rich portion and is formed by depositing an oxygen-rich oxy-nitride film by a first composition of gases and, subsequently, depositing a silicon-rich oxy-nitride film by a second composition of gases. In a particular embodiment, charge-trapping layer  504 B is formed by modifying the flow rate of ammonia (NH3) gas, and introducing nitrous oxide (N20) and dichlorosilane (SiH2Cb) to provide the desired gas ratios to yield first an oxygen-rich oxy-nitride film and then a silicon-rich oxy-nitride film. In one embodiment, charge-trapping layer  504 B has a thickness in the range of 5-10 nanometers. In accordance with an alternative embodiment of the present invention, charge-trapping layer  504 B has a graded composition. 
     Multi-layer blocking dielectric region  504 C may be composed of any material and have any thickness suitable to maintain a barrier to charge leakage without significantly decreasing the capacitance of gate stack  504 . In accordance with an embodiment of the present invention, multi-layer blocking dielectric region  504 C is a bilayer blocking dielectric region having a first dielectric layer  506  disposed directly above charge-trapping layer  504 B and having a second dielectric layer  508  disposed directly above first dielectric layer  506  and directly below gate layer  504 D. In an embodiment, first dielectric layer  506  has a large barrier height while second dielectric layer  508  has a high dielectric constant. In one embodiment, the barrier height of first dielectric layer  506  is at least approximately 2 electron Volts (eV). In a specific embodiment, the barrier height of first dielectric layer  506  is at least approximately 3 eV. In an embodiment, the dielectric constant of first dielectric layer  506  is lower than the dielectric constant of second dielectric layer  508 . In one embodiment, first dielectric layer  506  of bi-layer blocking dielectric region  504 C is composed of silicon dioxide and second dielectric layer  508  is composed of silicon nitride. In another embodiment, first dielectric layer  506  of bi-layer blocking dielectric region  504 C is composed of silicon dioxide and second dielectric layer  508  is composed of a material such as, but not limited to, aluminum oxide, hafnium oxide, zirconium oxide, hafnium silicate, zirconium silicate, hafnium oxy-nitride, hafnium zirconium oxide or lanthanum oxide. In a specific embodiment, first dielectric layer  506  of bi-layer blocking dielectric region  504 C is composed of a material having a dielectric constant approximately in the range of 3.5-4.5 and second dielectric layer  508  is composed of a material having a dielectric constant above approximately 7. In accordance with an embodiment of the present invention, multi-layer blocking dielectric region  504 C is formed in part by a chemical vapor deposition process. In one embodiment, multi-layer blocking dielectric region  504 C is formed from at least two different materials. In a specific embodiment, forming multi-layer blocking dielectric region  504 C from at least two different materials includes oxidizing a top portion of charge-trapping layer  504 B and, subsequently, depositing a dielectric layer above the oxidized portion of charge-trapping layer  504 B. In another specific embodiment, forming graded blocking dielectric layer  504 C from at least two different materials includes depositing a first dielectric layer having a first dielectric constant and, subsequently, depositing a second dielectric layer having a second dielectric constant, wherein the second dielectric constant is greater than the first dielectric constant. In a particular embodiment, the first dielectric layer has a thickness approximately in the range of 0.5-3 nanometers, the second dielectric layer has a thickness approximately in the range of 2-5 nanometers, and the first and second dielectric layers are not inter-mixed. Thus, in accordance with an embodiment of the present invention, multi-layer blocking dielectric region  504 C has an abrupt interface between first dielectric layer  506  and second dielectric layer  508 , as depicted in  FIG. 5 . 
     Gate layer  504 D may be composed of any conductor or semiconductor material suitable for accommodating a bias during operation of a SON OS-type transistor. In accordance with an embodiment of the present invention, gate layer  504 D is formed by a chemical vapor deposition process and is composed of doped poly-crystalline silicon. In another embodiment, gate layer  504 D is formed by physical vapor deposition and is composed of a metal-containing material which may include, but is not limited to, metal nitrides, metal carbides, metal silicides, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt and nickel. In one embodiment, gate layer  504 D is a high work-function gate layer. 
     In another aspect of the present invention, a nonvolatile charge trap memory device may include a graded blocking dielectric layer.  FIG. 6  illustrates a cross-sectional view of a nonvolatile charge trap memory device having a graded high dielectric constant blocking layer, in accordance with an embodiment of the present invention. 
     Referring to  FIG. 6 , semiconductor device  600  includes a gate stack  604  formed over a substrate  602 . Semiconductor device  600  further includes source and drain regions  610  in substrate  602  on either side of gate stack  604 , defining a channel region  612  in substrate  602  underneath gate stack  604 . Gate stack  604  includes a tunnel dielectric layer  604 A, a charge-trapping layer  604 B, a graded blocking dielectric layer  604 C, and a gate layer  604 D. Thus, gate layer  604 D is electrically isolated from substrate  602 . A pair of dielectric spacers  614  isolates the sidewalls of gate stack  604 . 
     Semiconductor device  600  may be any semiconductor device described in association with semiconductor device  500  from  FIG. 5 . Substrate  602 , source and drain regions  610  and channel region  612  may be composed of any material and dopant impurity atoms described in association with substrate  502 , source and drain regions  510  and channel region  512 , respectively, from  FIG. 5 . Tunnel dielectric layer  604 A, charge-trapping layer  604 B and gate layer  604 D may be composed of any material described in association with tunnel dielectric layer  504 A, charge-trapping layer  504 B and gate layer  504 D, respectively, from  FIG. 5 . 
     However, in contrast to semiconductor device  500 , semiconductor device  600  includes a graded blocking dielectric layer  604 C, as depicted in  FIG. 6 . In accordance with an embodiment of the present invention, graded blocking dielectric layer  604 C is disposed directly above charge-trapping layer  604 B and directly below gate layer  604 D. In an embodiment, the portion of graded blocking dielectric layer  604 C directly adjacent to charge-trapping layer  604 B has a large barrier height while the portion of graded blocking dielectric layer  604 C directly adjacent to gate layer  604 D has a high dielectric constant. In one embodiment, the barrier height of the portion of graded blocking dielectric layer  604 C directly adjacent to charge-trapping layer  604 B is at least approximately 2 eV. In a specific embodiment, the barrier height of the portion of graded blocking dielectric layer  604 C directly adjacent to charge-trapping layer  604 B is at least approximately 3 eV. In an embodiment, the dielectric constant of graded blocking dielectric layer  604 C has a low-to-high gradient in the direction from charge-trapping layer  604 B to gate layer  604 D. In one embodiment, the portion of graded blocking dielectric layer  604 C directly adjacent to charge-trapping layer  604 B is composed substantially of silicon dioxide and the portion of graded blocking dielectric layer  604 C directly adjacent to gate layer  604 D is composed substantially of silicon nitride. In another embodiment, the portion of graded blocking dielectric layer  604 C directly adjacent to charge-trapping layer  604 B is composed substantially of silicon dioxide and the portion of graded blocking dielectric layer  604 C directly adjacent to gate layer  604 D is composed substantially of a material such as, but not limited to, aluminum oxide, hafnium oxide, zirconium oxide, hafnium silicate, zirconium silicate, hafnium oxynitride, hafnium zirconium oxide or lanthanum oxide. In a specific embodiment, the portion of graded blocking dielectric layer  604 C directly adjacent to charge-trapping layer  604 B is composed substantially of a material having a dielectric constant approximately in the range of 3.5-4.5 and the portion of graded blocking dielectric layer  604 C directly adjacent to gate layer  604 D is substantially composed of a material having a dielectric constant above approximately 7. In accordance with an embodiment of the present invention, graded blocking dielectric layer  604 C is formed in part by a chemical vapor deposition process. In one embodiment, graded blocking dielectric layer  604 C is formed from at least two different materials. In a specific embodiment, forming graded blocking dielectric layer  604 C from at least two different materials includes oxidizing a top portion of charge-trapping layer  604 B and, subsequently, depositing a dielectric layer above the oxidized portion of charge-trapping layer  604 B. In another specific embodiment, forming graded blocking dielectric layer  604 C from at least two different materials includes depositing a first dielectric layer having a first dielectric constant and, subsequently, depositing a second dielectric layer having a second dielectric constant, wherein the second dielectric constant is greater than the first dielectric constant. In a particular embodiment, the first dielectric layer has a thickness approximately in the range of 0.5-3 nanometers, the second dielectric layer has a thickness approximately in the range of 2-5 nanometers, and the first and second dielectric layers are then intermixed. In one embodiment, the first and second dielectric layers are inter-mixed upon deposition of the second dielectric layer on the first dielectric layer. In another embodiment, the first and second dielectric layers are inter-mixed in an anneal process subsequent to the formation of the first and second dielectric layers. Thus, in accordance with an embodiment of the present invention, there is no distinct interface within graded blocking dielectric layer  604 C, as depicted in  FIG. 6 . 
     A nonvolatile charge trap memory device may be fabricated to include a multi-layer blocking dielectric region.  FIGS. 7  A- 7 I illustrate cross-sectional views representing operations in the formation of a nonvolatile charge trap memory device having a multi-layer high dielectric constant blocking region, in accordance with an embodiment of the present invention. 
     Referring to  FIG. 7  A, a substrate  702  is provided. Substrate  702  may be composed of any material and have any characteristics described in association with substrate  502  from  FIG. 5 . Referring to  FIG. 7B , a tunnel dielectric layer  720  is formed on the top surface of substrate  702 . Tunnel dielectric layer  720  may be formed from any material, from any process, and have any thickness described in association with tunnel dielectric layer  504 A from  FIG. 5 . Referring to  FIG. 7C , a charge-trapping layer  722  is formed on the top surface of tunnel dielectric layer  720 . Charge-trapping layer  722  may be formed from any material, from any process, and have any thickness described in association with charge-trapping layer  504 B from  FIG. 5 . 
     Referring to  FIG. 7D , a multi-layer blocking dielectric region  724  is formed on the top surface of charge-trapping layer  722 . Multi-layer blocking dielectric region  724  includes a first dielectric layer  726  disposed above charge-trapping layer  722  and a second dielectric layer  728  disposed above first dielectric layer  726 . In accordance with an embodiment of the present invention, multi-layer blocking dielectric region  724  is a bi-layer blocking dielectric region and includes a first dielectric layer  726  and a second dielectric layer  728 , as depicted in  FIG. 7D . First dielectric layer  726  and second dielectric layer  728  may be formed by any technique, composed of any materials, and have any thicknesses described in association with first dielectric layer  506  and second dielectric layer  508 , respectively, from  FIG. 5 . In accordance with an embodiment of the present invention, multi-layer blocking dielectric region  724  has an abrupt interface between first dielectric layer  726  and second dielectric layer  728 , as depicted in  FIG. 7D . In one embodiment, multi-layer blocking dielectric region  724  is formed from at least two different materials. In a specific embodiment, forming multi-layer blocking dielectric region  724  from at least two different materials includes oxidizing a top portion of charge-trapping layer  722  and, subsequently, depositing a dielectric layer above the oxidized portion of charge-trapping layer  724 . In another specific embodiment, forming multi-layer blocking dielectric region  724  from at least two different materials includes depositing a first dielectric layer having a first dielectric constant and, subsequently, depositing a second dielectric layer having a second dielectric constant, wherein the second dielectric constant is greater than the first dielectric constant. 
     Referring to  FIG. 7E , a gate layer  730  is formed on the top surface of multi-layer blocking dielectric region  724 . Gate layer  730  may be formed from any material and from any process described in association with gate layer  504 D from  FIG. 5 . Thus, a gate stack  732  may be formed above substrate  702 . 
     Referring to  FIG. 7F , gate stack  732  is patterned to form a patterned gate stack  704  above substrate  702 . Patterned gate stack  704  includes a patterned tunnel dielectric layer  704 A, a patterned charge-trapping layer  704 B, a patterned multi-layer blocking dielectric region  704 C, and a patterned gate layer  704 D. Patterned multi-layer blocking dielectric region  704 C includes a patterned first dielectric layer  706  and a patterned second dielectric layer  708 . Gate stack  732  may be patterned to form patterned gate stack  704  by any process suitable to provide substantially vertical sidewalls for gate stack  704  with high selectivity to substrate  702 . In accordance with an embodiment of the present invention, gate stack  732  is patterned to form patterned gate stack  704  by a lithography and etch process. In a specific embodiment, the etch process is an anisotropic etch process utilizing gases such as, but not limited to, carbon tetrafluoride (CF4), 0 2, hydrogen bromide (HBr) and chlorine (Cl 2 ). 
     Referring to  FIG. 7G , it may be desirable to implant dopant impurity atoms  740  into the exposed portions of substrate  704  to form source and drain tip extension regions  750 . Source and drain tip extension regions  750  will ultimately become part of source and drain regions formed subsequently, as described below. Thus, by forming source and drain tip extension regions  750  as defined by the location of patterned gate stack  704 , channel region  712  may be defined, as depicted in  FIG. 7G . In one embodiment, the conductivity type and the concentration of dopant impurity atoms used to form source and drain tip extension regions  750  are substantially the same as those used to form source and drain regions, described below. 
     Referring to  FIG. 7H , it may be desirable to form a pair of dielectric spacers  714  on the sidewalls of patterned gate stack  704 , as is well-known in the art. Finally, referring to  FIG. 7I , source and drain regions  710  are formed by implanting dopant impurity atoms  760  into the exposed portions of substrate  704 . Source and drain regions  710  may have any characteristics as those described in association with source and drain regions  510  from  FIG. 5 . In accordance with an embodiment of the present invention, the profile of source and drain regions  710  is defined by dielectric spacers  714 , patterned gate stack  704  and source and drain tip extension regions  750 , as depicted in  FIG. 7I . 
     In another embodiment, a nonvolatile charge trap memory device is fabricated to include a graded blocking dielectric layer.  FIGS. 8A-8C  illustrate cross-sectional views representing operations in the formation of a nonvolatile charge trap memory device having a graded high dielectric constant blocking layer, in accordance with an embodiment of the present invention. 
     Referring to  FIG. 8A , a charge-trapping layer  822  and a tunnel dielectric layer  820 , formed on the top surface of a substrate  802 , are provided. Substrate  802  may be composed of any material and have any characteristics described in association with substrate  602  from  FIG. 6 . Charge-trapping layer  822  and tunnel dielectric layer  820  may be formed from any material, from any process, and have any thickness described in association with charge-trapping layer  604 B and tunnel dielectric layer  604 A, respectively, from  FIG. 6 . 
     Referring to  FIG. 8B , a graded blocking dielectric layer  824  is formed on the top surface of charge-trapping layer  822 . In accordance with an embodiment of the present invention, graded blocking dielectric layer  824  is formed directly above charge-trapping layer  822 , as depicted in  FIG. 8B . In one embodiment, graded blocking dielectric layer  824  has a low-to-high gradient in the direction from charge trapping layer  822  to the top surface of graded blocking dielectric layer  824 . Graded blocking dielectric layer  824  may be formed by any technique, composed of any materials, and have any thicknesses described in association with graded blocking dielectric layer  604 C from  FIG. 6 . In accordance with an embodiment of the present invention, there is no distinct interface within graded blocking dielectric layer  824 , as depicted in  FIG. 8B . In one embodiment, graded blocking dielectric layer  824  is formed from at least two different materials. In a specific embodiment, forming graded blocking dielectric layer  824  from at least two different materials includes oxidizing a top portion of charge-trapping layer  822  and, subsequently, depositing a dielectric layer above the oxidized portion of charge-trapping layer  824 . In another specific embodiment, forming graded blocking dielectric layer  824  from at least two different materials includes depositing a first dielectric layer having a first dielectric constant and, subsequently, depositing a second dielectric layer having a second dielectric constant, wherein the second dielectric constant is greater than the first dielectric constant. 
     Referring to  FIG. 8C , process steps similar to those described in association with  FIGS. 7E-7I  are carried out to form a nonvolatile charge trap memory device having a graded blocking dielectric layer. Thus, a patterned gate stack  804  is formed over a substrate  802 . Source and drain regions  810  are formed on either side of patterned gate stack  804 , defining a channel region  812 . Patterned gate stack  804  includes a patterned tunnel dielectric layer  804 A, a patterned charge-trapping layer  804 B, a patterned graded blocking dielectric layer  804 C and a patterned gate layer  804 D. 
     IMPLEMENTATIONS AND ALTERNATIVES 
     In another aspect the present disclosure is directed to multigate or multigate-surface memory devices including charge-trapping regions overlying two or more sides of a channel formed on or above a surface of a substrate, and methods of fabricating the same. Multigate devices include both planar and non-planar devices. A planar multigate device (not shown) generally includes a double-gate planar device in which a number of first layers are deposited to form a first gate below a subsequently formed channel, and a number of second layers are deposited thereover to form a second gate. A non-planar multigate device generally includes a horizontal or vertical channel formed on or above a surface of a substrate and surrounded on three or more sides by a gate. 
       FIG. 9A  illustrates one embodiment of a non-planar multigate memory device  900  including a split charge-trapping region and a graded or multi-layer blocking dielectric formed above a first region of a substrate. Referring to  FIG. 9A , the memory device  900 , commonly referred to as a finFET, includes raised a channel  902  formed from a thin film or layer of semiconducting material overlying a surface  904  on a substrate  906  connecting a source  908  and a drain  910  of the memory device. The channel  902  is enclosed on three sides by a fin which forms a gate  912  of the device. The thickness of the gate  912  (measured in the direction from source to drain) determines the effective channel length of the device. 
       FIG. 9B  is a cross-sectional view of a portion of the non-planar memory device of  FIG. 9A  including a portion of the substrate  906 , the channel  902  and the gate  912  illustrating a split charge-trapping region  914  and a multi-layer blocking dielectric  918 . In accordance with the present disclosure, the gate  912  can include a split charge-trapping region  914  and a graded or multi-layer blocking dielectric  918 . The gate  912  further includes a tunnel oxide  916  overlying the channel  902 , and a metal gate layer  920  overlying the blocking dielectric to form a control gate of the memory device  900 . In some embodiments a doped polysilicon may be deposited instead of metal to provide a polysilicon gate layer. Suitable dopants include, for example a p-type dopant such as Boron, to provide a P+ polysilicon gate. The channel  902  and gate  912  can be formed directly on substrate  906  or on an insulating or dielectric layer  922 , such as a buried oxide layer, formed on or over the substrate  906  as shown in  FIG. 9B . 
     Referring again to  FIG. 9B , the split charge-trapping region  914  includes at least one bottom or first charge-trapping layer  924  comprising nitride closer to the tunnel oxide  916 , and a top or second charge-trapping layer  926  overlying the first charge-trapping layer. Generally, the second charge-trapping layer  926  comprises a silicon-rich, oxygen-lean nitride layer and comprises a majority of a charge traps distributed in multiple charge-trapping layers, while the first charge-trapping layer  924  comprises an oxygen-rich nitride or silicon oxynitride, and is oxygen-rich relative to the second charge-trapping layer to reduce the number of charge traps therein. By oxygen-rich it is meant wherein a concentration of oxygen in the first charge-trapping layer  924  is from about 11 to about 40%, whereas a concentration of oxygen in second charge-trapping layer  926  is less than about 5%. 
     In some embodiments, such as that shown in  FIG. 9B , the split charge-trapping region  914  further includes at least one thin, intermediate or anti-tunneling layer  928  comprising a dielectric, such as an oxide, separating the second charge-trapping layer  926  from the first charge-trapping layer  924 . The anti-tunneling layer  928  substantially reduces the probability of electron charge that accumulates at the boundaries of the upper nitride layer  926  during programming from tunneling into the bottom nitride layer  924 , resulting in lower leakage current than for the conventional structures. 
     Either or both of the first charge-trapping layer  924  and the second charge-trapping layer  926  can comprise silicon nitride or silicon oxynitride, and can be formed, for example, by a CVD process including N 2 O/NH 3  and DCS/NH 3  gas mixtures in ratios and at flow rates tailored to provide a silicon-rich and oxygen-rich oxynitride layer. The second nitride layer of the multi-layer charge storing structure is then formed on the middle oxide layer. The second charge-trapping layer  926  has a stoichiometric composition of oxygen, nitrogen and/or silicon different from that of the first charge-trapping layer  924 , and may also be formed or deposited by a CVD process using a process gas including DCS/NH 3  and N 2 O/NH 3  gas mixtures in ratios and at flow rates tailored to provide a silicon-rich, oxygen-lean top nitride layer. 
     In those embodiments including an intermediate or anti-tunneling layer  928  comprising oxide, the anti-tunneling layer can be formed by oxidation of the bottom oxynitride layer, to a chosen depth using radical oxidation. Radical oxidation may be performed, for example, at a temperature of 1100-1100° C. using a single wafer tool, or 800-900° C. using a batch reactor tool. A mixture of H 2  and O 2  gasses may be employed at a pressure of 300-500 Tor for a batch process, or 11-15 Tor using a single vapor tool, for a time of 1-2 minutes using a single wafer tool, or 30 min-1 hour using a batch process. 
     A suitable thickness for the first charge-trapping layer  924  may be from about 30 Å to about 80 Å (with some variance permitted, for example ±10 A), of which about 5-20 Å may be consumed by radical oxidation to form the anti-tunneling layer  928 . A suitable thickness for the second charge-trapping layer  926  may be at least 30 Å. In certain embodiments, the second charge-trapping layer  926  may be formed up to 90 Å thick, of which 30-70 Å may be consumed by radical oxidation to form the blocking dielectric  918 . A ratio of thicknesses between the first charge-trapping layer  924  and second charge-trapping layer  926  is approximately 1:1 in some embodiments, although other ratios are also possible. In other embodiments, the second charge-trapping layer  926  may comprise a high K dielectric. Suitable high K dielectrics include hafnium based materials such as HfSiON, HfSiO or HfO, Zirconium based material such as ZrSiON, ZrSiO or ZrO, and Yttrium based material such as Y 2 O 3 . 
     Referring again to  FIG. 9B  the blocking dielectric region can comprise a multi-layer blocking dielectric region disposed above split charge-trapping region. In the embodiment shown the multi-layer blocking dielectric  918  is a bi-layer blocking dielectric and includes a first dielectric layer  918   a  formed on the second charge-trapping layer  926  and a second dielectric layer  918   b  formed above first dielectric layer. First dielectric layer  918   a  and second dielectric layer  918   b  may be formed by any technique, composed of any materials, and have any thicknesses described above in association with first dielectric layer  506  and second dielectric layer  508 , respectively, from  FIG. 5 . Generally, the multi-layer blocking dielectric  918  is formed from at least two different materials and has an abrupt interface between first dielectric layer  918   a  and second dielectric layer  918   b , as depicted in  FIG. 9B . 
     The multi-layer blocking dielectric  918  can be formed by oxidizing a top portion of the second charge-trapping layer  926  to form a first dielectric layer  918   a  having a first dielectric constant and, subsequently, depositing a material having a second dielectric constant above the first dielectric layer to form a second dielectric layer  918   b , wherein the second dielectric constant is greater than the first dielectric constant. It will be appreciated that the thickness of the second charge-trapping layer  926  may be adjusted or increased as some of the second charge-trapping layer will be effectively consumed or oxidized during the process of thermally growing the first dielectric layer  918   a . In one embodiment, forming the first dielectric layer  918   a  is accomplished using a radical oxidation process, such as In-Situ Steam Generation (ISSG). ISSG can be accomplished by placing the substrate  906  in a deposition or processing chamber, heating the substrate to a temperature from about 700° C. to about 850° C., and exposing it to a wet vapor for a predetermined period of time selected based on a desired thickness of the finished first dielectric layer  918   a . Exemplary process times are from about 5 to about 20 minutes. The oxidation can be performed at atmospheric or at low pressure. 
     In other embodiments, forming the multi-layer blocking dielectric  918  comprises depositing at least two different materials, including depositing a first material having a first dielectric constant to form the first dielectric layer  918   a  and, subsequently, depositing a material having a second dielectric constant to form the second dielectric layer  918   b . In certain embodiments, the first dielectric layer  918   a  is a high temperature oxide deposited in a high-temperature oxide (HTO) process. Generally, the HTO process involves exposing the substrate  906  with the split charge-trapping region  914  formed thereon to a silicon source, such as silane, chlorosilane, or dichlorosilane, and an oxygen-containing gas, such as O 2  or N 2 O in a chemical vapor deposition (CVD) chamber at a pressure of from about 50 mT to about 1000 mT, for a period of from about 10 minutes to about 120 minutes while maintaining the substrate at a temperature of from about 650° C. to about 850° C. 
     Alternatively, either or both of the first dielectric layer  918   a  and the second dielectric layer  918   b  may comprise a high K dielectric formed by any technique, composed of any materials, and have any thicknesses as described above in association with first dielectric layer  506  and second dielectric layer  508 , respectively, from  FIG. 5 . Suitable high K dielectrics materials include hafnium based materials such as HfSiON, HfSiO or HfO, Zirconium based material such as ZrSiON, ZrSiO or ZrO, and Yttrium based material such as Y 2 O 3 . 
     In other embodiments, such as that shown in  FIG. 9C , the blocking dielectric  918  is fabricated to be or include a graded blocking dielectric layer  930 . Referring to  FIG. 9C , the graded blocking dielectric layer  930  is formed directly above or on the top of the second charge-trapping layer  926 . 
     In one embodiment, the graded blocking dielectric layer  930  has a low-to-high gradient in the direction from the second charge-trapping layer  926  to the top surface of the graded blocking dielectric layer. Graded blocking dielectric layer  930  may be formed by any technique, composed of any materials, and have any thicknesses described in association with graded blocking dielectric layers  604 C and  804 C, respectively, from  FIGS. 6 and 8 . In accordance with an embodiment of the present invention, there is no distinct interface within the graded blocking dielectric layer  930 , as depicted in  FIG. 9C . Generally, the graded blocking dielectric layer  930  is formed from at least two different materials. In a specific embodiment, forming the graded blocking dielectric layer  930  from at least two different materials includes oxidizing a top portion of the second charge-trapping layer  926  and, subsequently, depositing a dielectric layer above the oxidized portion of the second charge-trapping layer. 
     In another specific embodiment, forming the graded blocking dielectric layer  930  from at least two different materials includes depositing a first dielectric layer having a first dielectric constant and, subsequently, depositing a second dielectric layer having a second dielectric constant, wherein the second dielectric constant is greater than the first dielectric constant, and annealing the graded blocking dielectric layer  930  to cause materials of the first and second dielectric layers to diffuse at a boundary thereof. Alternatively, the graded blocking dielectric can be formed in a single a CVD processing step by changing process gases, ratios or flow rates to form a graded blocking dielectric having different stoichiometric composition across a thickness of the layer. 
     As with the multi-layer embodiment described above, either or both of the materials of the first second dielectric layers may comprise a high K dielectric formed by any suitable technique, and having any thicknesses. Suitable high K dielectrics materials include hafnium based materials such as HfSiON, HfSiO or HfO, Zirconium based material such as ZrSiON, ZrSiO or ZrO, and Yttrium based material such as Y 2 O 3 . 
       FIG. 10  illustrates a flow diagram depicting sequences of particular modules employed in the fabrication process of a non-planar or multigate non-volatile memory device including a graded or multi-layer high dielectric constant blocking region. Referring to  FIG. 10 , the method begins with formation of a semiconducting channel or channel comprising a semiconducting material overlying a surface on a substrate and electrically connecting a first diffusion region and a second diffusion region of the memory device (module  1002 ). The channel can be formed by depositing on a surface of the substrate a layer of semiconducting material and patterning the layer using any known photolithographic techniques. The semiconducting material may be composed of a single crystal of a material which may include, but is not limited to, silicon, germanium, silicon-germanium or a III-V compound semiconductor material deposited by any conventional technique, such as, but not limited to epitaxial deposition in a LPCVD chamber. A tunnel dielectric or oxide is formed overlying or abutting the channel (module  1004 ). The tunnel dielectric can include a silicon oxide, silicon nitride or silicon oxynitride having various stoichiometric compositions of oxygen, nitrogen and/or silicon, and may be deposited or grown by any conventional technique, including but not limited to thermally grown oxides, oxides formed by radical oxidation and HTO CVD processes, as described above. 
     A split charge-trapping region is formed abutting the tunnel oxide (module  1006 ). Generally, the split charge-trapping region comprises a first charge-trapping layer including a nitride closer to the tunnel oxide, and a second charge-trapping layer comprising a nitride overlying the first charge-trapping layer. The individual layers of the split charge-trapping region can include silicon oxides, silicon oxynitrides and silicon nitrides having various stoichiometric compositions of oxygen, nitrogen and/or silicon, and may deposited or grown by any conventional technique, such as, but not limited to thermally grown oxides, radical oxidation and CVD processes, as described above. In some embodiments, the split charge-trapping region can further include a thin, anti-tunneling oxide layer separating the first charge-trapping layer from the second charge-trapping layer. 
     Next, a multi-layer or graded blocking dielectric comprising at least a first material having a first dielectric constant and a second material having a second dielectric constant greater than the first dielectric constant is formed abutting the split charge-trapping region. In some embodiments, the blocking dielectric comprises a multi-layer blocking dielectric including at least a first dielectric layer formed abutting the split charge-trapping region, and a second dielectric layer formed above first dielectric layer (module  1008 ). In other embodiments, the blocking dielectric comprises a graded blocking dielectric with no distinct interface between the first and second materials (module  1010 ). As described above in association with graded blocking dielectric layer  930 , from  FIG. 9C , the graded blocking dielectric can be formed by depositing first and second dielectric layers followed by annealing the by a CVD process using a process gas including DCS/NH 3  and N 2 O/NH 3  gas mixtures in ratios and at flow rates tailored to provide a silicon-rich, oxygen-lean top nitride layer  930  to cause materials of the first and second dielectric layers diffuse at a boundary thereof. Alternatively, the graded blocking dielectric can be formed in a single a CVD processing step by changing process gases, ratios or flow rates to form a graded blocking dielectric having different stoichiometric composition across a thickness of the layer. 
     Finally, a gate layer is formed overlying the blocking dielectric to form a control gate of the memory device (module  1012 ). In some embodiments, the gate layer a high work-function gate layer and can include a metal-containing material formed by physical vapor deposition and may include, but is not limited to, metal nitrides, metal carbides, metal silicides, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt and nickel. In other embodiments, a doped polysilicon may be deposited instead of metal to provide a polysilicon gate layer. Suitable dopants include, for example a p-type dopant such as Boron, to provide a P+ polysilicon gate. 
     In another embodiment, shown in  FIGS. 11A and 11B , the memory device can include a nanowire channel formed from a thin film of semiconducting material overlying a surface on a substrate connecting a source and a drain of the memory device. By nanowire channel it is meant a conducting channel formed in a thin strip of crystalline silicon material, having a maximum cross-sectional dimension of about 11 nanometers (nm) or less, and more preferably less than about 6 nm. Optionally, the channel can be formed to have &lt;100&gt; surface crystalline orientation relative to a long axis of the channel. 
     Referring to  FIG. 11A , the memory device  1100  includes a horizontal nanowire channel  1102  formed from a thin film or layer of semiconducting material on or overlying a surface on a substrate  1106 , and connecting a source  1108  and a drain  1110  of the memory device. In the embodiment shown, the device has a gate-all-around (GAA) structure in which the nanowire channel  1102  is enclosed on all sides by a gate  1112  of the device. The thickness of the gate  1112  (measured in the direction from source to drain) determines the effective channel length of the device. 
     In accordance with the present disclosure, the non-planar multigate memory device  1100  of  FIG. 11A  can include a multi-layer blocking dielectric.  FIG. 11B  is a cross-sectional view of a portion of the non-planar memory device of  FIG. 11A  illustrating a multi-layer blocking dielectric  1116   a  and  1116   b . Referring to  FIG. 11B , the gate  1112  includes a tunnel oxide  1114  overlying the nanowire channel  1102 , a split charge-trapping region including layers  1120 - 1124 , a blocking dielectric including layers  1116   a  and  1116   b , and a gate layer  1118  overlying the blocking dielectric. 
     The split charge-trapping region includes at least one inner charge-trapping layer  1120  comprising nitride closer to the tunnel oxide  1114 , and an outer charge-trapping layer  1122  overlying the inner charge-trapping layer. Generally, the outer charge-trapping layer  1122  comprises a silicon-rich, oxygen-lean nitride layer and comprises a majority of a charge traps distributed in multiple charge-trapping layers, while the inner charge-trapping layer  1120  comprises an oxygen-rich nitride or silicon oxynitride, and is oxygen-rich relative to the outer charge-trapping layer to reduce the number of charge traps therein. 
     In some embodiments, such as that shown, the split charge-trapping region further includes at least one thin, intermediate or anti-tunneling layer  1124  comprising a dielectric, such as an oxide, separating outer charge-trapping layer  1122  from the inner charge-trapping layer  1120 . The anti-tunneling layer  1124  substantially reduces the probability of electron charge that accumulates at the boundaries of outer charge-trapping layer  1122  during programming from tunneling into the inner charge-trapping layer  1120 , resulting in lower leakage current. 
     As with the embodiments described above, either or both of the inner charge-trapping layer  1120  and the outer charge-trapping layer  1122  can comprise silicon nitride or silicon oxynitride, and can be formed, for example, by a CVD process including N 2 O/NH 3  and DCS/NH 3  gas mixtures in ratios and at flow rates tailored to provide a silicon-rich and oxygen-rich oxynitride layer. The second nitride layer of the multi-layer charge storing structure is then formed on the middle oxide layer. The outer charge-trapping layer  1122  has a stoichiometric composition of oxygen, nitrogen and/or silicon different from that of the inner charge-trapping layer  1120 , and may also be formed or deposited by a CVD process using a process gas including DCS/NH 3  and N 2 O/NH 3  gas mixtures in ratios and at flow rates tailored to provide a silicon-rich, oxygen-lean top nitride layer. 
     In those embodiments including an intermediate or anti-tunneling layer  1124  comprising oxide, the anti-tunneling layer can be formed by oxidation of the inner charge-trapping layer  1120 , to a chosen depth using radical oxidation. Radical oxidation may be performed, for example, at a temperature of 1000-1100° C. using a single wafer tool, or 800-900° C. using a batch reactor tool. A mixture of H 2  and O 2  gasses may be employed at a pressure of 300-500 Tor for a batch process, or 11-15 Tor using a single vapor tool, for a time of 1-2 minutes using a single wafer tool, or 30 min-1 hour using a batch process. 
     A suitable thickness for the inner charge-trapping layer  1120  may be from about 30 Å to about 80 Å (with some variance permitted, for example ±10 A), of which about 5-20 Å may be consumed by radical oxidation to form the anti-tunneling layer  1124 . A suitable thickness for the outer charge-trapping layer  1122  may be at least 30 Å. In certain embodiments, the outer charge-trapping layer  1122  may be formed up to 90 Å thick, of which 30-70 Å may be consumed by radical oxidation to form the blocking dielectric. A ratio of thicknesses between the inner charge-trapping layer  1120  and the outer charge-trapping layer  1122  is approximately 1:1 in some embodiments, although other ratios are also possible. 
     In other embodiments, either or both of the outer charge-trapping layer  1122  and the blocking dielectric  1116   a ,  1116   b , may comprise a high K dielectric. Suitable high K dielectrics include hafnium based materials such as HfSiON, HfSiO or HfO, Zirconium based material such as ZrSiON, ZrSiO or ZrO, and Yttrium based material such as Y 2 O 3 . 
     Referring again to  FIG. 11B  the blocking dielectric can comprise a multi-layer blocking dielectric region abutting the outer charge-trapping layer  1122 . In the embodiment shown the multi-layer blocking dielectric is a bi-layer blocking dielectric and includes an inner or first dielectric layer  1116   a  formed on the outer charge-trapping layer  1122  and an outer or second dielectric layer  1116   b  formed above first dielectric layer. First dielectric layer  1116   a  and second dielectric layer  1116   b  may be formed by any technique, composed of any materials, and have any thicknesses described above in association with first dielectric layer  918   a  and second dielectric layer  918   b , respectively. Generally, the multi-layer blocking dielectric  1116   a ,  1116   b , is formed from at least two different materials and has an abrupt interface between first dielectric layer  1116   a  and second dielectric layer  1116   b , as depicted in  FIG. 11B . 
     The multi-layer blocking dielectric  1116   a ,  1116   b , can be formed by oxidizing a top portion of the outer charge-trapping layer  1122  to form a first dielectric layer  1116   a  having a first dielectric constant and, subsequently, depositing a material having a second dielectric constant above the first dielectric layer to form a second dielectric layer  1116   b , wherein the second dielectric constant is greater than the first dielectric constant. It will be appreciated that the thickness of the outer charge-trapping layer  1122  may be adjusted or increased as some of the outer charge-trapping layer will be effectively consumed or oxidized during the process of thermally growing the first dielectric layer  1116   a . In one embodiment, forming the first dielectric layer  1116   a  is accomplished using a radical oxidation process, such as In-Situ Steam Generation (ISSG). ISSG can be accomplished by placing the substrate  1106  in a deposition or processing chamber, heating the substrate to a temperature from about 700° C. to about 850° C., and exposing it to a wet vapor for a predetermined period of time selected based on a desired thickness of the finished first dielectric layer  1116   a . Exemplary process times are from about 5 to about 20 minutes. The oxidation can be performed at atmospheric or at low pressure. 
     In other embodiments, forming the multi-layer blocking dielectric  1116   a ,  1116   b , comprises depositing at least two different materials, including depositing a first material having a first dielectric constant to form the first dielectric layer  1116   a  and, subsequently, depositing a material having a second dielectric constant to form the second dielectric layer  1116   b . In certain embodiments, the first dielectric layer  1116   a  is a high temperature oxide deposited in a high-temperature oxide (HTO) process. Generally, the HTO process involves exposing the substrate  1106  with the split charge-trapping region formed thereon to a silicon source, such as silane, chlorosilane, or dichlorosilane, and an oxygen-containing gas, such as O 2  or N 2 O in a chemical vapor deposition (CVD) chamber at a pressure of from about 50 mT to about 1000 mT, for a period of from about 10 minutes to about 120 minutes while maintaining the substrate at a temperature of from about 650° C. to about 850° C. 
     Alternatively, either or both of the first dielectric layer  1116   a  and the second dielectric layer  1116   b  may comprise a high K dielectric formed by any technique, composed of any materials, and have any thicknesses as described above in association with first dielectric layer  506  and second dielectric layer  508 , respectively, from  FIG. 5 . Suitable high K dielectrics materials include hafnium based materials such as HfSiON, HfSiO or HfO, Zirconium based material such as ZrSiON, ZrSiO or ZrO, and Yttrium based material such as Y 2 O 3 . 
     In other embodiments (not shown), the blocking dielectric is fabricated to be or include a graded blocking dielectric layer, such as graded blocking dielectric layer  930 , shown in  FIG. 9C . As with the embodiments described above, the graded blocking dielectric layer is formed directly above or on the top of the outer charge-trapping layer  1122 . 
     In one embodiment, the graded blocking dielectric layer has a low-to-high gradient in the direction from the outer charge-trapping layer  1122  to a top surface of the blocking dielectric  1116 . The graded blocking dielectric layer may be formed by any technique, composed of any materials, and have any thicknesses described in association with graded blocking dielectric layers  604 C and  804 C, respectively, from  FIGS. 6 and 8 . 
     As with the multi-layer embodiment described above, either or both of the materials of the first second dielectric layers may comprise a high K dielectric formed by any suitable technique, and having any thicknesses. Suitable high K dielectrics materials include hafnium based materials such as HfSiON, HfSiO or HfO, Zirconium based material such as ZrSiON, ZrSiO or ZrO, and Yttrium based material such as Y 2 O 3 . 
       FIG. 11C  illustrates a cross-sectional view of a vertical string of non-planar multigate devices  1100  of  FIG. 11A  arranged in a Bit-Cost Scalable or BiCS architecture  1126 . The architecture  1126  consists of a vertical string or stack of non-planar multigate devices  1100 , where each device or cell includes a channel  1102  overlying the substrate  1106 , and connecting a source and a drain (not shown in this figure) of the memory device, and having a gate-all-around (GAA) structure in which the nanowire channel  1102  is enclosed on all sides by a gate  1112 . The BiCS architecture reduces number of critical lithography steps compared to a simple stacking of layers, leading to a reduced cost per memory bit. 
     In another embodiment, the memory device is or includes a non-planar device comprising a vertical nanowire channel formed in or from a semiconducting material projecting above or from a number of conducting, semiconducting layers on a substrate. In one version of this embodiment, shown in cut-away in  FIG. 12A , the memory device  1200  comprises a vertical nanowire channel  1202  formed in a cylinder of semiconducting material connecting a source  1204  and drain  1206  of the device. The channel  1202  is surrounded by a tunnel oxide  1208 , a charge-trapping region  1210 , a blocking dielectric  1212  and a gate layer  1214  overlying the blocking dielectric to form a control gate of the memory device  1200 . The channel  1202  can include an annular region in an outer layer of a substantially solid cylinder of semiconducting material, or can include an annular layer formed over a cylinder of dielectric filler material. As with the horizontal nanowires described above, the channel  1202  can comprise polysilicon or recrystallized polysilicon to form a monocrystalline channel. Optionally, where the channel  1202  includes a crystalline silicon, the channel can be formed to have &lt;100&gt; surface crystalline orientation relative to a long axis of the channel. 
     In some embodiments, such as that shown in  FIG. 12B , the charge-trapping region  1210  can be a split charge-trapping region and blocking dielectric  1212  can be a multi-layer blocking dielectric. 
     Referring to  FIG. 12B , the split charge-trapping region  1210  includes at least a first or inner charge trapping layer  1216  closest to the tunnel oxide  1208 , and a second or outer charge trapping layer  1218 . Optionally, the first and second charge trapping layers can be separated by an intermediate oxide or anti-tunneling layer  1220 . 
     As with the embodiments described above, either or both of the first charge trapping layer  1216  and the second charge trapping layer  1218  can comprise silicon nitride or silicon oxynitride, and can be formed, for example, by a CVD process including N 2 O/NH 3  and DCS/NH 3  gas mixtures in ratios and at flow rates tailored to provide a silicon-rich and oxygen-rich oxynitride layer. 
     Finally, either or both of the second charge trapping layer  1218  and the blocking dielectric  1212  may comprise a high K dielectric, such as HfSiON, HfSiO, HfO, ZrSiON, ZrSiO, ZrO, or Y 2 O 3 . 
     Referring again to  FIG. 12B  the blocking dielectric  1212  can comprise a multi-layer blocking dielectric region abutting the outer charge-trapping layer  1218 . In the embodiment shown the multi-layer blocking dielectric is a bi-layer blocking dielectric and includes an inner or first dielectric layer  1212   a  formed on the outer charge-trapping layer  1218  and an outer or second dielectric layer  1212   b  formed above first dielectric layer. First dielectric layer  1212   a  and second dielectric layer  1212   b  may be formed by any technique, composed of any materials, and have any thicknesses described above in association with first dielectric layer  918   a  and second dielectric layer  918   b , respectively. Generally, the multi-layer blocking dielectric  1212  is formed from at least two different materials and has an abrupt interface between first dielectric layer  1212   a  and second dielectric layer  1212   b , as depicted in  FIG. 12B . 
     The multi-layer blocking dielectric  1212  can be formed by oxidizing a top portion of the outer charge-trapping layer  1218  to form a first dielectric layer  1212   a  having a first dielectric constant and, subsequently, depositing a material having a second dielectric constant above the first dielectric layer to form a second dielectric layer  1212   b , wherein the second dielectric constant is greater than the first dielectric constant. It will be appreciated that the thickness of the outer charge-trapping layer  1218  may be adjusted or increased as some of the outer charge-trapping layer will be effectively consumed or oxidized during the process of thermally growing the first dielectric layer  1212   a . In one embodiment, forming the first dielectric layer  1212   a  is accomplished using a radical oxidation process, such as In-Situ Steam Generation (ISSG). ISSG can be accomplished by placing the substrate  1106  in a deposition or processing chamber, heating the substrate to a temperature from about 700° C. to about 850° C., and exposing it to a wet vapor for a predetermined period of time selected based on a desired thickness of the finished first dielectric layer  1212   a . Exemplary process times are from about 5 to about 20 minutes. The oxidation can be performed at atmospheric or at low pressure. 
     In other embodiments, forming the multi-layer blocking dielectric  1212   a ,  1212   b , comprises depositing at least two different materials, including depositing a first material having a first dielectric constant to form the first dielectric layer  1212   a  and, subsequently, depositing a material having a second dielectric constant to form the second dielectric layer  1212   b . In certain embodiments, the first dielectric layer  1212   a  is a high temperature oxide deposited in a high-temperature oxide (HTO) process. Generally, the HTO process involves exposing the substrate  1106  with the split charge-trapping region formed thereon to a silicon source, such as silane, chlorosilane, or dichlorosilane, and an oxygen-containing gas, such as O 2  or N 2 O in a chemical vapor deposition (CVD) chamber at a pressure of from about 50 mT to about 1000 mT, for a period of from about 10 minutes to about 120 minutes while maintaining the substrate at a temperature of from about 650° C. to about 850° C. 
     Alternatively, either or both of the first dielectric layer  1212   a  and the second dielectric layer  1212   b  may comprise a high K dielectric formed by any technique, composed of any materials, and have any thicknesses as described above in association with first dielectric layer  506  and second dielectric layer  508 , respectively, from  FIG. 5 . Suitable high K dielectrics materials include hafnium based materials such as HfSiON, HfSiO or HfO, Zirconium based material such as ZrSiON, ZrSiO or ZrO, and Yttrium based material such as Y 2 O 3 . 
     In other embodiments (not shown), the blocking dielectric is fabricated to be or include a graded blocking dielectric layer, such as graded blocking dielectric layer  930 , shown in  FIG. 9C . As with the embodiments described above, the graded blocking dielectric layer is formed directly above or on the top of the outer charge-trapping layer  1218 . 
     In one embodiment, the graded blocking dielectric layer has a low-to-high gradient in the direction from the outer charge-trapping layer  1218  to a top surface of the blocking dielectric  1212 . The graded blocking dielectric layer may be formed by any technique, composed of any materials, and have any thicknesses described in association with graded blocking dielectric layers  604 C and  804 C, respectively, from  FIGS. 6 and 8 . 
     As with the multi-layer embodiment described above, either or both of the materials of the first second dielectric layers may comprise a high K dielectric formed by any suitable technique, and having any thicknesses. Suitable high K dielectrics materials include hafnium based materials such as HfSiON, HfSiO or HfO, Zirconium based material such as ZrSiON, ZrSiO or ZrO, and Yttrium based material such as Y 2 O 3 . 
     The memory device  1200  of  FIG. 12A  can be made using either a gate first or a gate last scheme.  FIGS. 13A-G  illustrate a gate first scheme for fabricating the non-planar multigate device of  FIG. 12A .  FIGS. 14A-F  illustrate a gate last scheme for fabricating the non-planar multigate device of  FIG. 12A . 
     Referring to  FIG. 13A , in a gate first scheme a dielectric layer  1302  is formed over a first, doped diffusion region  1304 , such as a source or a drain, in a substrate  1306 . A gate layer  1308  is deposited over the first dielectric layer  1302  to form a control gate of the device, and a second or upper dielectric layer  1310  formed thereover. As with embodiments described above, the first and second dielectric layers  1302 ,  1310 , can be deposited by CVD, radical oxidation or be formed by oxidation of a portion of the underlying layer or substrate. The gate layer  1308  can comprise a metal deposited or a doped polysilicon deposited by CVD. Generally the thickness of the gate layer  1308  is from about 40-50 Å, and the first and second dielectric layers  1302 ,  1310 , from about 20-80 Å. 
     Referring to  FIG. 13B , a first opening  1312  is etched through the overlying gate layer  1308 , and the first and second dielectric layers  1302 ,  1310 , to the diffusion region  1304  in the substrate  1306 . Next, layers of a blocking dielectric  1314 , charge-trapping region  1316 , and tunneling oxide  1318  are sequentially deposited in the opening and the surface of the upper dielectric layer  1310  planarize to yield the intermediate structure shown in  FIG. 13C . 
     Referring to  FIG. 13D , the blocking dielectric  1314  can comprise a multi-layer blocking dielectric region abutting the outer charge-trapping layer  1318 . In the embodiment shown the multi-layer blocking dielectric is a bi-layer blocking dielectric and includes a first dielectric layer  1314   a  formed on the sidewall of opening of  1312  and a second dielectric layer  1314   b  formed above first dielectric layer. First dielectric layer  1314   a  and second dielectric layer  1314   b  may be formed by any technique, composed of any materials, and have any thicknesses described above in association with first dielectric layer  918   a  and second dielectric layer  918   b , respectively. Generally, the multi-layer blocking dielectric  1314  is formed from at least two different materials and has an abrupt interface between first dielectric layer  1314   a  and second dielectric layer  1314   b , as depicted in  FIG. 13D . 
     As described above, either or both of the first dielectric layer  1314   a  and the second dielectric layer  1314   b  may comprise an oxide, nitride, oxynitride or a high K dielectric formed by any technique, composed of any materials, and have any thicknesses as described above in association with first dielectric layer  506  and second dielectric layer  508 , respectively, from  FIG. 5 . 
     In other embodiments (not shown), the blocking dielectric is fabricated to be or include a graded blocking dielectric layer, such as graded blocking dielectric layer  930 , shown in  FIG. 9C . As with the embodiments described above, the graded blocking dielectric layer is formed directly on the sidewall of opening of  1312 . The graded blocking dielectric layer may have a low-to-high gradient in the direction from the outer charge-trapping region  1316  to an outer surface of the blocking dielectric  1316 . The graded blocking dielectric layer may be formed by any technique, composed of any materials, and have any thicknesses described in association with graded blocking dielectric layers  604 C and  804 C, respectively, from  FIGS. 6 and 8 . As with the multi-layer embodiment described above, either or both of the materials of the first second dielectric layers may comprise a high K dielectric formed by any suitable technique, and having any thicknesses. 
     In some embodiments, such as that shown in  FIG. 13D , the charge-trapping region  1316  can be a split charge-trapping region. The charge-trapping region  1316  can include at least a first charge-trapping layer  1316   a  closer to the tunnel oxide  1318 , and a second charge-trapping layer  1316   b  overlying the first charge-trapping layer. Generally, the second charge-trapping layer comprises a silicon-rich, oxygen-lean nitride layer and comprises a majority of a charge traps distributed in multiple charge-trapping layers, while the first charge-trapping layer comprises an oxygen-rich nitride or silicon oxynitride, and is oxygen-rich relative to the second charge-trapping layer to reduce the number of charge traps therein. In some embodiments, the split charge-trapping region  1316  further includes at least one thin, intermediate or anti-tunneling layer  1316   c  comprising a dielectric, such as an oxide, separating the second charge-trapping layer  1316   b  from the first charge-trapping layer  1316   a.    
     Next, a second or channel opening  1320  is anisotropically etched through tunneling oxide  1318 , charge-trapping region  1316 , and blocking dielectric  1314 ,  FIG. 13E . Referring to  FIG. 13F , a semiconducting material  1322  is deposited in the channel opening to form a vertical channel  1324  therein. The vertical channel  1324  can include an annular region in an outer layer of a substantially solid cylinder of semiconducting material, or, as shown in  FIG. 13F , can include a separate, layer semiconducting material  1322  surrounding a cylinder of dielectric filler material  1326 . 
     Referring to  FIG. 13G , the surface of the upper dielectric layer  1310  is planarized and a layer of semiconducting material  1328  including a second, doped diffusion region  1330 , such as a source or a drain, formed therein deposited over the upper dielectric layer to form the device shown. 
     Referring to  FIG. 14A , in a gate last scheme a dielectric layer  1402 , such as an oxide, is formed over a sacrificial layer  1404  on a surface on a substrate  1406 , an opening etched through the dielectric and sacrificial layers and a vertical channel  1408  formed therein. As with embodiments described above, the vertical channel  1408  can include an annular region in an outer layer of a substantially solid cylinder of semiconducting material  1410 , such as polycrystalline or monocrystalline silicon, or can include a separate, layer semiconducting material surrounding a cylinder of dielectric filler material (not shown). The dielectric layer  1402  can comprise any suitable dielectric material, such as a silicon oxide, capable of electrically isolating the subsequently formed gate layer of the memory device  1200  from an overlying electrically active layer or another memory device. The sacrificial layer  1404  can comprise any suitable material that can be etched or removed with high selectivity relative to the material of the dielectric layer  1402 , substrate  1406  and vertical channel  1408 . 
     Referring to  FIG. 14B , a second opening  1412  is etched through the etched through the dielectric and sacrificial layers  1402 ,  1404 , to the substrate  1206 , and the sacrificial layer  1404  etched or removed. The sacrificial layer  1404  can comprise any suitable material that can be etched or removed with high selectivity relative to the material of the dielectric layer  1402 , substrate  1406  and vertical channel  1408 . In one embodiment the sacrificial layer  1404  comprises Silicon dioxide that can be removed by a buffered oxide (BOE) etch. 
     Referring to  FIGS. 14C and 14D , layers of a tunneling oxide  1414 , charge-trapping region, and blocking dielectric are sequentially deposited in the opening and the surface of the dielectric layer  1402  planarize to yield the intermediate structure shown in  FIG. 14C . In some embodiments, such as that shown in  FIG. 14D , the charge-trapping region can be a split charge-trapping region including at least a first or inner charge trapping layer  1416   a  closest to the tunnel oxide  1414 , and a second or outer charge trapping layer  1416   b . Optionally, the first and second charge trapping layers can be separated by an intermediate oxide or anti-tunneling layer  1416   c.    
     The blocking dielectric can comprise a multi-layer blocking dielectric region abutting the outer charge-trapping layer  1416   b . In the embodiment shown the multi-layer blocking dielectric is a bi-layer blocking dielectric and includes a first dielectric layer  1418   a  formed on the sidewall of opening of  1312  and a second dielectric layer  1418   b  formed above first dielectric layer. First dielectric layer  1418   a  and second dielectric layer  1418   b  may be formed by any technique, composed of any materials, and have any thicknesses described above in association with first dielectric layer  918   a  and second dielectric layer  918   b , respectively. Generally, the multi-layer blocking dielectric is formed from at least two different materials and has an abrupt interface between first dielectric layer  1418   a  and second dielectric layer  1418   b , as depicted in  FIG. 14D . 
     As described above, either or both of the first dielectric layer  1418   a  and the second dielectric layer  1418   b  may comprise an oxide, nitride, oxynitride or a high K dielectric formed by any technique, composed of any materials, and have any thicknesses as described above in association with first dielectric layer  506  and second dielectric layer  508 , respectively, from  FIG. 5 . 
     In other embodiments (not shown), the blocking dielectric is fabricated to be or include a graded blocking dielectric layer, such as graded blocking dielectric layer  930 , shown in  FIG. 9C . As with the embodiments described above, the graded blocking dielectric layer may have a low-to-high gradient in the direction from the outer charge-trapping region  1316   b  to an inner surface of the blocking dielectric. The graded blocking dielectric layer may be formed by any technique, composed of any materials, and have any thicknesses described in association with graded blocking dielectric layers  604 C and  804 C, respectively, from  FIGS. 6 and 8 . As with the multi-layer embodiment described above, either or both of the materials of the first second dielectric layers may comprise a high K dielectric formed by any suitable technique, and having any thicknesses. 
     Next, a gate layer  1422  is deposited into the second opening  1412  and the surface of the upper dielectric layer  1402  planarized to yield the intermediate structure illustrated in  FIG. 14E . As with embodiments described above, the gate layer  1422  can comprise a metal deposited or a doped polysilicon. Finally, an opening  1424  is etched through the gate layer  1422  to form control gate of separate memory devices  1426 . 
     Thus, nonvolatile charge trap memory devices have been disclosed. The devices each include a substrate having a channel region and a pair of source and drain regions. A gate stack is above the substrate over the channel region and between the pair of source and drain regions. In accordance with an embodiment of the present invention, the gate stack includes a high dielectric constant blocking region. In one embodiment, the high dielectric constant blocking region is a bi-layer blocking dielectric region. In another embodiment, the high dielectric constant blocking region is a graded blocking dielectric layer.