Patent Publication Number: US-5892775-A

Title: Method and apparatus for providing error-tolerant storage of information

Description:
BACKGROUND OF THE INVENTION 
     1. Technical Field 
     This invention relates to a method and a circuit for storing information such as digital data or signals in a permuted order in a memory storage device. 
     2. Discussion of Related Art 
     Recent advances in the manufacture of semiconductor devices have yielded memories having ever increasing speed and density characteristics. Generally, the higher the density of a semiconductor memory, the more memory sites or locations are available for data storage. However, the increased density renders the memory less error tolerant from defects or faults. For example, if a given area of the semiconductor memory is defective, whether from the manufacturing process or field-induced, more memory sites or a larger portion of the stored data will be corrupted. A field-induced defect may result from a magnetic storm which passes through certain areas of the memory, causing data corruption in that portion of the memory device and loss of data integrity required when data is read from the memory. Common memory defects are single dimensional, e.g., the memory is defective in a single row or column of a given matrix of the memory. Two dimensional faults involve multiple columns and/or rows. 
     SUMMARY OF THE INVENTION 
     The method and circuit according to the present invention provide error-tolerant storage of information in a storage medium. Generally, the information is arranged or assigned in a permuted order wherein consecutive elements of the information are stored in well-separated, or at least &#34;nonadjacent&#34;, locations of the storage medium. The information may be in the form of digital data bits, samples of audiovisual signals or blocks of samples. If the information is time-ordered or is sequential, the method and circuit of the invention permute the time-ordering or the sequence associated with the elements of the information prior to or at the time of storage of the elements in memory. When the information is retrieved or read from the memory, the original time-ordering or sequence of the elements of the information is restored by de-permuting or inverting the writing or storage scheme. 
     A method according to the illustrative embodiment of the present invention provides error-tolerant storage of information in a storage medium having at least one area definable by M×N storage sites, the method comprising the steps of: 
     partitioning the information into a plurality of groups, at least one of the groups having a plurality of bits in consecutive time order and being suitable for storage in respective ones of said M×N sites; 
     arranging the plurality of bits in permuted order; and, 
     storing the plurality of bits in the permuted order whereby consecutive bits occupy nonadjacent sites of said M×N sites of said storage medium. 
     The method further includes the steps of: 
     retrieving the stored plurality of bits from said storage medium; and, 
     rearranging the retrieved plurality of bits in a de-permuting order to reconstruct at least one of the groups in consecutive time order. 
     Preferably, the step of reconstructing at least one of the groups from the memory includes reconstructing bits in the consecutive time order despite the existence of one-dimensional or two-dimensional errors in the memory. 
     The step of arranging the plurality of bits in a permuted order according to the illustrative embodiment of the present invention provides a Manhattan distance of at least 2 between any consecutive bits of at least one of the groups. Further, consecutive bits are arranged wherein they do not occupy the same row or column of the M×N sites. This ensures error-tolerant storage to at least one-dimensional errors. A Manhattan distance is a term known in the field as the sum of the horizontal distance and the vertical distance between two objects. 
     The illustrative method according to the invention also arranges the bit-ordering to provide a well-separated distance between consecutive bits, e.g., a Manhattan distance of 5 for 6×6 storage sites. The method further arranges the bit ordering such that consecutive bits do not occupy the same row or column. In such an embodiment, the memory is said to be error-tolerant to 2-dimensional errors. 
     Another illustrative embodiment of the present invention is a circuit for providing error-tolerant storage of digital signals, which comprises: 
     a storage medium having at least one area definable by M×N storage sites; 
     means for time-ordering the digital signals into S successive samples, S being equal to M×N; 
     means for accessing the storage medium including means for storing the S samples into the storage medium; and, 
     a permutator for permuting the time-ordering of the S successive samples, the permutator being configured to cooperate with the means for accessing to store the S samples into the storage medium in a permuted order when neighboring bits of the S successive samples are stored in non-neighboring storage sites in the storage medium. 
     Preferably, the circuit according to the illustrative embodiment permutes the S successive samples in an order which well separates the distance between any neighboring samples, e.g., by a Manhattan distance of at least 2, and consecutive samples do not occupy the same row or column of the memory. 
     The circuit further includes a decoder for retrieving the S samples stored in the storage medium and for decoding the permuted order to recover the original time ordering of the S successive samples. 
     Advantageously, the illustrative technique according to the present invention of separation and storage of consecutive bits or samples facilitates error tolerance to at least single and two-dimensional faults in the storage device. Further, in the case in which the stored signal is a digital data sequence, and error-correcting coding is involved, the illustrative technique separates or &#34;de-clusters&#34; errors that require correction; thus, the technique makes simpler the error correction process. In the case in which the storage signal is an audio or video signal, the illustrative technique permits simpler signal enhancement at the receiving end by known techniques such as nearest neighbor interpolation. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 illustrates a block diagram of a circuit for providing error-tolerant storage of information according to an illustrative embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
     The device according to the illustrative embodiment of the present invention includes means for permuting the order of signals representing the information intended for storage in a memory. The signal time-ordering is permuted prior to or at the time of storage in the memory such that when the information or data is stored in the permuted order, it is more tolerant to errors or defects that exist, and/or that may occur in the memory. 
     FIG. 1 shows a circuit arrangement in which a signal or information from signal source 101 is processed by encoder 110 to provide error-tolerant storage of the information in memory 140. 
     Signal source 101 is an information source which is preferably digital data. The signal source 101 may also be in the form of analog signals such as human speech. The analog signals are digitized by a known sampling circuit (not shown) prior to being forwarded to encoder 110. Clock 113 supplies clock signal C1 to synchronize the signal source to encoder 110. 
     The output of data latch 111 is connected to the input of shift registers 115 and 117. Counter 129 is an n stage counter operative responsive to clock signal C1 from clock 113 to provide a coded output corresponding to the first n stages of the counter in complementary signals Q and Q&#39; corresponding to the last counter stage. Thus, for the first n counts of the clock pulses, signal Q&#39; is enabling and signal Q is inhibiting. Responsive to counter signal Q&#39; and clock pulses C1, the output of data latch 111 is serially inserted into shift register 117. At this time, signal Q from counter 129 inhibits shift register 115 so that the previous n outputs from signal source 101 are temporarily stored therein. 
     For illustration, assume that shift register 115 is adapted to temporarily store 36 successive bits of signal source 101. Each of the stages of shift register 115 is connected to an input of switch 122, and switch 122 is operative responsive to each clock pulse to selectively transfer 1 of the 36 bits from register 115 to line 124. Switch 122 is addressed by the output of permutator 133, which is responsive to the output of stages 1 through 36 of counter 129. 
     According to the present illustrative embodiment, permutator 133 may be in the form of a look-up table or a customized sequencer. Permutator 133 responds to counter outputs 130 to generate control codes for appropriately switching the data output for storage in memory 140 at the appropriate time. In the case of a look-up table, the counter outputs an address for outputting the control codes stored in the look-up table to Switch 122. Similarly, a sequencer will output a preprogrammed control code depending upon the count from counter 129. 
     Memory 140 may be sectionalized into M×N storage sites. For example, in a 6×6 memory site area, the bit order may be arranged as shown in Table 1: 
     
                       TABLE 1
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         Column (j)
Row (i)    0     1        2   3      4   5
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0          1     3        5   20     22  24
1          7     9        11  26     28  30
2          13    15       17  32     34  36
3          19    21       23  2      4   6
4          25    27       29  8      10  12
5          31    33       35  14     16  18
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     Permutator 133 in cooperation with switch 122 outputs the 36 bits in accordance with the order shown in the matrix above by rearranging each number according to the formula 
     
         6k.sub.1 +2k.sub.2 +k.sub.3                                (1) 
    
     for numbers between 1 and 36, wherein k 1  is a modulo 6 number, k 2  is a modulo 2 number and k 3  is a modulo 1 number. The numbers 1 to 36 can be expressed as shown in Table 2: 
     
                       TABLE 2
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K        k.sub.1        k.sub.2
                              k.sub.3
______________________________________
1        0              0     0
2        0              0     1
3        0              1     0
4        0              1     1
5        0              2     0
6        0              2     1
7        1              0     0
8        1              0     1
9        1              1     0
.        .              .     .
.        .              .     .
.        .              .     .
35       5              2     0
36       5              2     1
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     where 
     
         (i,j)=k.sub.1 (1,0)+k.sub.2 (0,1)+k.sub.3 (3,3)            (2) 
    
     To illustrate the application of formula (2), take bit number 8 which, according to the modulo representation of Table 2, is 101. When applied to formula (2), the (i,j) position is 
     
         1(1,0)+0(0,1)+1(3,3)=(1,0)+(3,3)=(4,3) 
    
     and bit number 8 can be found in the fourth row (i) and the third column (j). 
     As another example, bit number 26 is represented by 401 in Table 2 and 
     
         (i,j)=4(1,0)+0(0,1)+1(3,3)=(4,0)+(3,3)=(7,3) 
    
     which is equivalent to (1,3) in modulo 6. It can be seen that bit number 26 is placed in the first row (i) and the third column (j). 
     Note that in the matrix where M and N=6 as shown in Table 1, consecutive bit numbers are well separated, the minimum separation between successive bit numbers having a Manhattan distance of 5, and consecutive bit numbers do not occupy the same row or column of the matrix. For example, bit numbers 2 and 3 are separated by 2 columns and 3 rows. 
     Advantageously, with the bit pattern as shown in Table 1 stored in memory 140, it is apparent to one of ordinary skill in the art that such storage arrangement is error tolerant to at least single or 2 dimensional faults or defects. For example, if data in a portion of the memory 140 is corrupted for any reason, such as in a magnetic storm or from a defective manufacturing process, the information recovered from decoding the uncorrupted stored data would still be intelligible. 
     To illustrate, suppose there exists data corruption in the area of the matrix denoted by (2,2) to (3,3) or error in bit numbers 17, 23, 32 and 2. Because the data corruption did not occur in consecutive or successive bit numbers, the information recovered from reading the memory and decoding the matrix is still largely intact and when reconstructed, would still be intelligible. This is especially true if the stored information is sampled audio signals. 
     In cases where the M×M matrix in which M is odd, the following formula is applicable: ##EQU1## 
     For example, a 5×5 matrix with M and N=5 wherein the bit numbers 1 to 25 are represented in lexicographic order is presented in Table 2. 
     
         ______________________________________
Column
Row     0          1     2        3   4
______________________________________
0       1          24    17       15  8
1       21         19    12       10  3
2       16         14    7        5   23
3       11         9     2        25  18
4       6          4     22       20  13
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     It can be appreciated that the memory is more error-tolerant the further away the distance is between successive bit numbers. Preferably, the encoder 110 according to the present invention permutes the bit order so that the Manhattan distance between successive bits is at least 2 and successive bits do not occupy the same row or column. In most instances, with consecutive bits in different columns or rows, a Manhattan distance of 2 will be tolerant to one-dimensional errors, such as defects along rows, columns or diagonals in the memory of storage process. In the example shown above in Table 1, with the Manhattan distance of 5, the memory is tolerant to two-dimensional errors such as errors in the shape of rectangles, squares or circles. 
     To recover the signal source data stored in memory 140, the encoding process performed by encoder 110 is reversed by decoder 120 wherein counter 169, clock 151, shift registers 157 and 159 and access memory 140 are reversed in timing order from the writing process in encoder 110. The reversed ordering is performed by de-permutator 181 in cooperation with switch circuit 165 to rearrange the bit numbers in the sequential ordering as output by signal source 101. The information output at line 190 is then the recovered version of signal source 101. 
     If error correction coding is employed, usually for the case in which the signal source is a digital data sequence, an error correcting coder (not shown) is connected to output 190. Because of the &#34;declustering&#34; of the data sequence from the technique according to the illustrative embodiments of the present invention, the error correction codec overhead is reduced. Numerous error correction schemes known to one ordinary skilled in the art are applicable to the circuit and method of the present invention. 
     Although a number of specific embodiments of this invention have been shown and described herein, it is to be understood that these embodiments are merely illustrative of the many possible specific arrangements which can be devised in application of the principles of the invention. Numerous and varied other arrangements can be devised in accordance with these principles by those of ordinary skill in the art without departing from the spirit and scope of the invention.