Patent Publication Number: US-8970197-B2

Title: Voltage regulating circuit configured to have output voltage thereof modulated digitally

Description:
FIELD OF THE INVENTION 
     The present invention relates to a voltage regulator circuit field, and more particularly to a voltage regulator circuit configured to have its output voltage modulated in a digital manner. 
     BACKGROUND OF THE INVENTION 
     Typically, the conventional voltage regulator circuit includes an operational amplifier (OP Amp) and a power metal-oxide semiconductor field-effect transistor (MOSFET). Specifically, the power MOSFET is configured to have its one source/drain terminal providing an output voltage; and the operational amplifier is configured to control the conduction degree of the power MOSFET according to the value of the output voltage. 
     However, due to requiring operating the operational amplifier at saturation, the conventional voltage regulator circuit, cannot be operated at low voltages. 
     SUMMARY OF THE INVENTION 
     Therefore, one object of the present invention is to provide a voltage regulator circuit configured to have its output voltage modulated in a digital manner, and thereby the voltage regulator circuit is capable of being operated at low voltages. 
     An embodiment of the present invention provides a voltage regulator circuit, which includes a plurality of first transistors and a control circuit. Each first transistor has two source/drain terminals and a gate terminal. One source/drain terminal of each transistor is electrically coupled to a source voltage, and the other source/drain terminals of the transistors are electrically coupled to each other and corporately referred to as an output terminal of the voltage regulator circuit. The control circuit is electrically coupled to the gate terminals of the transistors and configured to determine the number of the transistors to be turned on according to the difference between the voltage at the output terminal and a predetermined reference voltage. 
     In summary, the voltage regulator circuit according to the present invention includes a plurality of transistors and a control circuit. Each of the transistors functions as a pull-up circuit for pulling up the level of voltage outputted from the voltage regulator circuit. The control circuit is configured to determine the number of the aforementioned transistors to be turned on according to the difference between the output voltage of the voltage regulator circuit and a predetermined reference voltage. In other words, the number of the transistors to be turned on in the voltage regulator circuit dynamically varies with the difference value between the output voltage of the voltage regulator circuit and the predetermined reference voltage. In addition, the voltage regulator circuit according to the present invention can be operated at a relatively low voltage due to being implemented in a digital manner. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The embodiments of the present invention will become more readily apparent to those ordinarily skilled in the art after reviewing the following detailed description and accompanying drawings, in which: 
         FIG. 1  is a schematic view of a voltage regulator circuit in accordance with an embodiment of the present invention; 
         FIG. 2  is a schematic view of one circuit implementation of the control circuit depicted in  FIG. 1 ; 
         FIG. 3  is a schematic view of another circuit implementation of the control circuit depicted in  FIG. 1 ; and 
         FIG. 4  is a schematic view illustrating one connection structure of an internal circuit and a corresponding delay control unit. 
     
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
     The embodiments of the present invention will now be described more specifically with reference to the following embodiments. It is to be noted that the following descriptions of preferred embodiments of this invention are presented herein for purpose of illustration and description only. It is not intended to be exhaustive or to be limited to the precise form disclosed. 
       FIG. 1  is a schematic view of a voltage regulator circuit in accordance with an embodiment of the present invention. As shown, the voltage regulator circuit  100  in this embodiment includes a control circuit  140  and a plurality of (for example, eight) transistors  112 ,  114 ,  116 ,  118 ,  122 ,  124 ,  126  and  128 ; wherein each of the transistors  112 ,  114 ,  116 ,  118 ,  122 ,  124 ,  126  and  128  has two source/drain terminals and a gate terminal. In this embodiment, the transistors  112 ,  114 ,  116  and  118  are P-type metal-oxide semiconductor field-effect transistors (MOSFET), and the transistors  122 ,  124 ,  126  and  128  are N-type metal-oxide semiconductor field-effect transistors. 
     Each of the transistors  112 ,  114 ,  116  and  118  is configured to have its one source/drain terminal electrically coupled to a source voltage VDD; and its the other source/drain terminal electrically coupled to an output terminal  130  of the voltage regulator circuit  100 . In addition, each of the transistors  122 ,  124 ,  126  and  128  is configured to have its one source/drain terminal electrically coupled to the output terminal  130 ; and its other source/drain terminal electrically coupled to a reference voltage (for example, is electrically coupled to ground GND). According to the above circuit configurations, it is understood that each of the transistors  112 ,  114 ,  116  and  118  functions as a pull-up circuit, which is used to pull up the voltage level at the output terminal  130  of the voltage regulator circuit  100 ; and each of the transistors  122 ,  124 ,  126  and  128  functions as a pull-down circuit, which is used to pull down the voltage level at the output terminal  130  of the voltage regulator circuit  100 . 
     The control circuit  140 , electrically coupled to the gate terminals of the transistors  112 ,  114 ,  116 ,  118 ,  122 ,  124 ,  126  and  128 , is configured to determine, based on the difference between the voltage VOUT at the output terminal  130  and a predetermined reference voltage VREF, the number of the transistors  112 ,  114 ,  116 ,  118 ,  122 ,  124 ,  126  and  128  to be turned on or turned off. For example, the control circuit  140  is configured to, if determining that the voltage VOUT drops and has a predetermined difference smaller than the predetermined reference voltage VREF, turn on at least one of the transistors  112 ,  114 ,  116  and  118  so as to pull up the voltage level of the voltage VOUT at the output terminal  130 . In addition, it is to be noted that the number of the transistors  112 ,  114 ,  116  and  118  to be turned on increases with increasing difference between the voltage VOUT at the output terminal  130  and the predetermined reference voltage VREF. 
     Alternatively, the control circuit  140  is configured to, if determining that the voltage VOUT increases and has a predetermined difference greater than the predetermined reference voltage VREF, turn on at least one of the transistors  122 ,  124 ,  126  and  128  so as to pull down the voltage level of the voltage VOUT at the output terminal  130 . In addition, it is to be noted that the number of the transistors  122 ,  124 ,  126  and  128  to be turned on increases with increasing difference between the voltage VOUT at the output terminal  130  and the predetermined reference voltage VREF. Thus, through the aforementioned modulation, the voltage VOUT at the output terminal  130  is stabilized due to the voltage level thereof can only vary in a predetermined range. 
     The control circuit  140  can be implemented by several different circuit designs.  FIG. 2  is a schematic view of one circuit implementation of the control circuit  140 . As shown, the control circuit  140  includes a plurality of (for example, eight) sense amplifiers  241 ˜ 248 , which are commonly used in a memory, and each of them is configured to receive two voltages (i.e., a first and second voltages supplied into a first and second input terminals thereof, respectively), compare the two inputted voltages and accordingly output a comparison result. Specifically, the sense amplifiers  241 ˜ 248  each output a logic-1 (or, logic-high) comparison result from an output terminal thereof if the first voltage is greater than the second voltage; alternatively, the sense amplifiers  241 ˜ 248  each output a logic-0 (or, logic-low) comparison result if the second voltage is greater than the first voltage. 
     As illustrated in  FIGS. 1 ,  2 , the sense amplifiers  241 ˜ 248 , having their output terminals electrically coupled to the gate terminals of the respective transistors  112 ,  114 ,  116 ,  118 ,  122 ,  124 ,  126  and  128 , are configured to output respective comparison results RS1, RS2, RS3, RS4, RS5, RS6, RS7 and RS8 by performing a comparison between the voltage VOUT at the output terminal  130  and the respective predetermined reference voltages of 0.98×VREF, 0.96×VREF, 0.94×VREF, 0.94×VREF, 1.02×VREF, 1.04×VREF, 1.06×VREF and 1.08×VREF. In this embodiment, the comparison results RS1, RS2, RS3, RS4, RS5, RS6, RS7 and RS8 are used to turn on or turn off the transistors  112 ,  114 ,  116 ,  118 ,  122 ,  124 ,  126  and  128 , respectively; and the voltages of 0.92×VREF, 0.94×VREF, 0.96×VREF, 0.98×VREF, 1.02×VREF, 1.04×VREF, 1.06×VREF and 1.08×VREF are obtained through multiplying the predetermined reference voltage VREF by a plurality of different predetermined percentages. 
     Specifically, it is understood that the predetermined reference voltages of 0.92×VREF, 0.94×VREF, 0.96×VREF, and 0.98×VREF can be obtained by employing one or more voltage divider, and the predetermined reference voltages of 1.02×VREF, 1.04×VREF, 1.06×VREF, and 1.08×VREF can be obtained by employing one or more boost circuit or one or more charge pump; and the present invention is not limited thereto. 
     Please refer to  FIG. 2  again. For example, in the case of the voltage VOUT at the output terminal  130  being smaller than a voltage of 0.98×VREF but greater than 0.96×VREF, the sense amplifier  241  is configured to output a logic-0 comparison result RS1 to turn on the P-type transistor  112  and thereby pulling up the voltage level of the voltage VOUT. Meanwhile, the sense amplifiers  242 ,  243  and  244  are configured to output logic-1 comparison results RS2, RS3 and RS4 to turn off the P-type transistors  114 ,  116  and  118 , respectively; and the sense amplifiers  245 ,  246 ,  247  and  248  are configured to output logic-0 comparison results RS5, RS6, RS7 and RS8 to turn off the N-type transistors  122 ,  124 ,  126  and  128 , respectively. In other words, when the voltage VOUT at the output terminal  130  drops and is smaller than a voltage of 0.98×VREF but greater than 0.96×VREF, only the transistor  112  is turned on and the rest of the transistors  114 ,  116 ,  118 ,  122 ,  124 ,  126  and  128  are turned off; and thus, the voltage level of the voltage VOUT is pulled up by the transistor  112  only and the transistors  114 ,  116 ,  118 ,  122 ,  124 ,  126  and  128  each are configured not to perform the pull-up or pull-down operations on the voltage VOUT. 
     In another case of the voltage VOUT at the output terminal  130  being smaller than a voltage of 0.96×VREF but greater than 0.94×VREF, the sense amplifiers  241 ,  242  are configured to output logic-0 comparison results RS1, RS2 to turn on the P-type transistors  112 ,  114 , respectively, and thereby pulling up the voltage level of the voltage VOUT. Meanwhile, the sense amplifiers  243 ,  244  are configured to output logic-1 comparison results RS3, RS4 to turn off the P-type transistors  116 ,  118 , respectively; and the sense amplifiers  245 ,  246 ,  247  and  248  are configured to output logic-0 comparison results RS5, RS6, RS7 and RS8 to turn off the N-type transistors  122 ,  124 ,  126  and  128 , respectively. In other words, when the voltage VOUT at the output terminal  130  drops and is smaller than a voltage of 0.96×VREF but greater than 0.94×VREF, the transistors  112 ,  114  are turned on and the rest of the transistors  116 ,  118 ,  122 ,  124 ,  126  and  128  are turned off; and thus, the voltage level of the voltage VOUT is pulled up by the transistors  112 ,  114  and the transistors  116 ,  118 ,  122 ,  124 ,  126  and  128  are configured not to perform the pull-up or pull-down operations on the voltage VOUT. According to the aforementioned configurations, it is understood that the number of the transistors  112 ,  114 ,  116  and  118  to be turned on increases with increasing difference between the voltage VOUT at the output terminal  130  and the predetermined reference voltage VREF (i.e., with decreasing voltage VOUT at the output terminal  130  with relative to the predetermined reference voltage VREF); and accordingly the pull-up speed of the voltage VOUT at the output terminal  130  increases with increasing number of the transistors to be turned on in the transistors  112 ,  114 ,  116  and  118 . 
     On the contrary, in the case of the voltage VOUT at the output terminal  130  being greater than a voltage of 1.02×VREF but smaller than 1.04×VREF, the sense amplifier  245  is configured to output a logic-1 comparison result RS5 to turn on the N-type transistor  122  and thereby pulling down the voltage level of the voltage VOUT. Meanwhile, the sense amplifiers  246 ,  247  and  248  are configured to output logic-0 comparison results RS6, RS7 and RS8 to turn off the N-type transistors  124 ,  126  and  128 , respectively; and the sense amplifiers  241 ,  242 ,  243  and  244  are configured to output logic-1 comparison results RS1, RS2, RS3 and RS4 to turn off the P-type transistors  112 ,  114 ,  116  and  118 , respectively. In other words, when the voltage VOUT at the output terminal  130  increases and is greater than a voltage of 1.02×VREF but smaller than 1.04×VREF, only the transistor  122  is turned on and the rest of transistors  112 ,  114 ,  116 ,  118 ,  124 ,  126  and  128  are turned off; and thus, the voltage level of the voltage VOUT is pulled down by the transistor  122  only and the transistors  112 ,  114 ,  116 ,  118 ,  124 ,  126  and  128  each are configured not to perform the pull-up or pull-down operations on the voltage VOUT. 
     In another case of the voltage VOUT at the output terminal  130  keeping increasing and being greater than a voltage of 1.04×VREF but smaller than 1.06×VREF, the sense amplifiers  245 ,  246  are configured to output logic-1 comparison results RS5, RS6 to turn on the N-type transistors  122 ,  124 , respectively, and thereby pulling down the voltage level of the voltage VOUT. Meanwhile, the sense amplifiers  247 ,  248  are configured to output logic-0 comparison results RS7, RS8 to turn off the N-type transistors  126 ,  128 , respectively; and the sense amplifiers  241 ,  242 ,  243  and  244  are configured to output logic-1 comparison results RS1, RS2, RS3 and RS4 to turn off the P-type transistors  112 ,  114 ,  116  and  118 , respectively. In other words, when the voltage VOUT at the output terminal  130  increases and is greater than a voltage of 1.04×VREF but smaller than 1.06×VREF, the transistors  122 ,  124  are turned on and the rest of transistors  112 ,  114 ,  116 ,  118 ,  126  and  128  are turned off; and thus, the voltage level of the voltage VOUT is pulled down by the transistors  122 ,  124  and the transistors  112 ,  114 ,  116 ,  118 ,  126  and  128  are configured not to perform the pull-up or pull-down operations on the voltage VOUT. According to the aforementioned configurations, it is understood that the number of transistors  122 ,  124 ,  126  and  128  to be turned on increases with increasing difference between the voltage VOUT at the output terminal  130  and the predetermined reference voltage VREF (i.e., with increasing voltage VOUT at the output terminal  130  with relative to the predetermined reference voltage VREF); and accordingly the pull-down speed of the voltage VOUT at the output terminal  130  increases with increasing number of the transistors to be turned on in the transistors  122 ,  124 ,  126  and  128 . 
     In summary, because the control circuit  140  dynamically switches on or off each of the transistors  112 ,  114 ,  116 ,  118 ,  122 ,  124 ,  126  and  128  based on a difference between the voltage VOUT at the output terminal  130  and the predetermined reference voltage VREF, the voltage VOUT at the output terminal  130  is stabilized due to the voltage level thereof can be only varied in a predetermined range. 
       FIG. 3  is a schematic view of another circuit implementation of the control circuit  140 . As shown, the control circuit  140  includes a plurality of phase delay units  342 ,  352 ,  372  and  382 , a plurality of (e.g., four) phase comparison units  360  and a plurality of (e.g., four) phase comparison units  390 . The phase delay unit  342  includes a delay chain  344  and a plurality of (e.g., eight) delay control units  346 . The delay chain  344 , including a plurality of (e.g., eight) internal circuits  344 - 2  coupled in series, is configured to receive a clock signal CLK and delay the phase of the received clock signal CLK. The delay control unit  346  is, according to the value of the voltage VOUT at the output terminal  130  of the voltage regulator circuit  100 , configured to control the time delay degree of the signal supplied to its associated internal circuit  344 - 2  in the delay chain  344 ; wherein the circuit connection structure of the delay control unit  346  and corresponding internal circuit  344 - 2  will be described in detail later. 
     Likewise, the phase delay unit  352  includes a delay chain  354  and a plurality of (e.g., eight) delay control units  356 . The delay chain  354 , including a plurality of (e.g., eight) internal circuits  354 - 2  coupled in series, is configured to receive a clock signal CLK and delay the phase of the received clock signal CLK. The delay control unit  356  is, according to the value of the reference voltage VREF, configured to control the time delay degree of the signal supplied to its associated internal circuit  354 - 2  in the delay chain  354 . The phase comparison unit  360  is configured to have its two input terminals electrically coupled to an output of corresponding stage of the internal circuits  344 - 2  in the delay chain  344  and an output of corresponding stage of the internal circuits  354 - 2  in the delay chain  354 , respectively, and generate a comparison result (i.e., one of the comparison results RS1, RS2, RS3 and RS4) by performing a comparison between the phases of the two output signals and thereby control the switch-on or switch-off of one transistor (i.e., one of the transistors  112 ,  114 ,  116  and  118 ). As mentioned above, the comparison results RS1, RS2, RS3 and RS4 are used to turn on or turn off the transistors  112 ,  114 ,  116  and  118 , respectively. 
     Likewise, the phase delay unit  372  includes a delay chain  374  and a plurality of (e.g., eight) delay control units  376 . The delay chain  374 , including a plurality of (e.g., eight) internal circuits  374 - 2  coupled in series, is configured to receive an inversion signal CLKB of the clock signal CLK and delay the phase of the received inversion signal CLKB. The delay control unit  376  is, according to the value of the reference voltage VREF, configured to control the time delay degree of the signal supplied to its associated internal circuit  374 - 2  in the delay chain  374 . Likewise, the phase delay unit  382  includes a delay chain  384  and a plurality of (e.g., eight) delay control units  386 . The delay chain  384 , including a plurality of (e.g., eight) internal circuits  384 - 2  coupled in series, is configured to receive the inversion signal CLKB and delay the phase of the received inversion signal CLKB. The delay control unit  386  is, according to the value of the voltage VOUT at the output terminal  130 , configured to control the time delay degree of the signal supplied to its associated internal circuit  384 - 2  in the delay chain  384 . 
     The phase comparison unit  390  is configured to have its two input terminals electrically coupled to an output of corresponding stage of internal circuits  374 - 2  in the delay chain  374  and an output of corresponding stage of the internal circuits  384 - 2  in the delay chain  384 , respectively, and generate a comparison result (i.e., one of the comparison results RS5, RS6, RS7 and RS8) by performing a comparison between the phases of the two output signals and thereby control the switch-on or switch-off of one transistor (i.e., one of the transistors  122 ,  124 ,  126  and  128 ). As mentioned above, the comparison results RS5, RS6, RS7 and RS8 are used to turn on or turn off the transistors  122 ,  124 ,  126  and  128 , respectively. 
     Additionally, in this embodiment the internal circuits  344 - 2 ,  354 - 2 ,  374 - 2  and  384 - 2  each can be implemented by an inverter; and the delay control units  346 ,  356 ,  376  and  386  each can be implemented by a transistor (e.g., an N-type MOS transistor). As depicted in  FIG. 3 , the transistors (i.e., delay control units)  346 ,  386  are configured to have their gate terminals receiving the voltage VOUT at the output terminal  130  of the voltage regulator circuit  100 ; and the transistors (i.e., delay control units)  356 ,  376  are configured to have their gate terminals receiving the predetermined reference voltage VREF. In addition, the inverters (i.e., internal circuits)  344 - 2 ,  354 - 2 ,  374 - 2  and  384 - 2  each are configured to be electrically coupled to the reference voltage (e.g., electrically coupled to ground GND) via the transistors (i.e., delay control units)  346 ,  356 ,  376  and  386 , respectively. 
       FIG. 4  is a schematic view illustrating one connection structure of one internal circuit and one corresponding delay control unit; wherein the internal circuit illustrated herein is implemented by an inverter, and the delay control unit is implemented by a transistor. As shown, the inverter is constituted by a P-type transistor  402  and an N-type transistor  404 . The transistor  402  is configured to have its one source/drain terminal electrically coupled to the source voltage VDD; its the other source/drain terminal referred to as an output terminal of the inverter and providing an output signal OUT; and its gate terminal referred to as an input terminal of the inverter and receiving an input signal IN. The transistor  404  is configured to have its one source/drain terminal electrically coupled to the output terminal of the inverter; and its gate terminal electrically coupled to the input terminal of the inverter. The transistor (i.e., delay control unit)  406  is configured to have its one source/drain terminal electrically coupled to the other source/drain terminal of the transistor  404 ; its other source/drain terminal electrically coupled to a reference voltage (for example, is electrically coupled to ground GND); and its gate terminal receiving an input voltage VI. The input voltage VI is either the voltage VOUT at the output terminal  130  of the voltage regulator circuit  100  or the predetermined reference voltage VREF. According to the circuit structure illustrated in  FIG. 4 , it is understood that the charge/discharge speed of the voltage (i.e., output signal OUT) at the output terminal of the inverter increases with increasing input voltage VI. 
     Please refer back to  FIG. 3 . As shown, the phase comparison unit  360 ,  390  each can be implemented by a D-type flip-flop. The D-type flip-flop has a signal input terminal D, a clock input terminal Δ and a signal output terminal Q. Specifically, the D-type flip-flop (i.e., phase comparison unit)  360  is configured to have its signal input terminal D and clock input terminal Δ receiving the output signals of corresponding stage of the internal circuits  344 - 2 ,  354 - 2  in the delay chains  344 ,  354 , respectively; and its signal output terminal Q outputting a comparison result (i.e., one of the comparison results RS1, RS2, RS3 and RS4). Likewise, the D-type flip-flop (i.e., phase comparison unit)  390  is configured to have its signal input terminal D and clock input terminal Δ receiving the output signals of corresponding stage of internal circuits  374 - 2 ,  384 - 2  in the delay chains  374 ,  384 , respectively; and its signal output terminal Q outputting a comparison result (i.e., one of the comparison results RS5, RS6, RS7 and RS8). In addition, the D-type flip-flop outputs a logic-1 (or, logic-high) comparison result if the signal at the signal input terminal D has a phase lead with respect to the signal at the clock input terminal Δ; alternatively, the D-type flip-flop outputs a logic-0 (or, logic-low) comparison result if the signal at the signal input terminal D has a phase lag with respect to the signal at the clock input terminal Δ. 
     According to the circuit implementation of the control circuit  140  as illustrated in  FIG. 3 , it is understood that the values of voltage VOUT at the output terminal  130  of the voltage regulator circuit  100  and the predetermined reference voltage VREF each can be converted into a phase-delay degree by the delay chains  344 ,  354 ,  374  and  384  and the corresponding delay control units  346 ,  356 ,  376  and  386 ; wherein the phase delay degree decreases with increasing voltage value. Therefore, the phase comparison units  360 ,  390  each can, according to the phase relationship between the two inputted signals, generate a comparison result (i.e., one of the comparison results RS1, RS2, RS3, RS4, RS5, RS6, RS7 and RS8) to turn on or turn off its corresponding transistor (i.e., one of the transistors  112 ,  114 ,  116 ,  118 ,  122 ,  124 ,  126  and  128 ). In addition, according to the circuit implementation of the control circuit  140  as illustrated in  FIG. 3 , it is understood that the number of the transistors  112 ,  114 ,  116  and  118  to be turned on, as well as the pull-up speed of the voltage level of the voltage VOUT at the output terminal  130 , increases with increasing difference between the voltage VOUT and the predetermined reference voltage VREF. Alternatively, the number of the transistors  122 ,  124 ,  126  and  128  to be turned on, as well as the pull-down speed of the voltage level of the voltage VOUT at the output terminal  130 , increases with increasing difference between the voltage VOUT at the output terminal  130  and the predetermined reference voltage VREF. 
     In addition, it is to be noted that the voltage regulator circuit  100  according to the present invention is not limited to the element size (specifically, the aspect ratio) of the transistors arranged therein. In other words, the transistors  112 ,  114 ,  116  and  118  can have the same element size and the transistors  122 ,  124 ,  126  and  128  can have the same element size. Or, all the transistors  112 ,  114 ,  116 ,  118 ,  122 ,  124 ,  126  and  128  can have the same element size. Or, the transistors  112 ,  114 ,  116  and  118  can have different element sizes and the transistors  122 ,  124 ,  126  and  128  can have different element sizes. Or, all the transistors  112 ,  114 ,  116 ,  118 ,  122 ,  124 ,  126  and  128  can have different element sizes. 
     In addition, it is apparent to those ordinarily skilled in the art that the voltage regulator circuit  100  can be implemented by the transistors  112 ,  114 ,  116  and  118  only without the transistors  122 ,  124 ,  126  and  128 ; and accordingly, the control circuit  140  is configured to control the transistors  112 ,  114 ,  116  and  118  only. For example, in the case of having a circuit implementation as illustrated in  FIG. 2 , the control circuit  140  can employ the sense amplifiers  241 ,  242 ,  243  and  244  only; and in the case of having a circuit implementation as illustrated in  FIG. 3 , the control circuit  140  can employ the phase delay units  342 ,  352  and the associated phase comparison units  360  only. In addition, it is understood that the voltage regulator circuit  100  according to the present invention is not limited to the number of the transistors (i.e. transistors  112 ,  114 ,  116 ,  118 ,  122 ,  124 ,  126  and  128 ) arranged therein. In other words, the number of the transistors adopted in the voltage regulator circuit  100  can be adjusted according to an actual design requirement; and accordingly, the number of sense amplifiers (i.e. sense amplifiers  241 ˜ 248 ) adopted in the control circuit  140  having a circuit implementation illustrated in  FIG. 2  should be adjusted correspondingly, or the number of stages in the delay chains (i.e. the delay chains  344 ,  354 ,  374  and  384 ) and the number of phase comparison units (i.e., the phase comparison units  360 ,  390 ) adopted in the control circuit  140  having a circuit implementation illustrated in  FIG. 3  should be adjusted correspondingly. 
     In summary, the voltage regulator circuit according to the present invention includes a plurality of transistors and a control circuit. Each of the transistors functions as a pull-up circuit for pulling up the level of voltage outputted from the voltage regulator circuit. The control circuit is configured to determine the number of the aforementioned transistors to be turned on according to the difference between the output voltage of the voltage regulator circuit and a predetermined reference voltage. In other words, the number of the transistors to be turned on in the voltage regulator circuit dynamically varies with the difference value between the output voltage of the voltage regulator circuit and the predetermined reference voltage. In addition, the voltage regulator circuit according to the present invention can be operated by a relatively low voltage due to being implemented in a digital manner. 
     While the invention has been described in terms of what is presently considered to be the most practical and preferred embodiments, it is to be understood that the invention needs not be limited to the disclosed embodiment. On the contrary, it is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims which are to be accorded with the broadest interpretation so as to encompass all such modifications and similar structures.