Patent Publication Number: US-5251284-A

Title: Optimal parametric signal processor with lattice basic cell

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This is a continuation of copending application Ser. No. 07/423,540 filed on Oct. 11, 1989 now abandoned and which was a continuation of Ser. No. 07/298,338, now abandoned filed on Jan. 13, 1989, which was a continuation of Ser. No. 06/904,382 filed on Sep. 4, 1986now abandoned and which was a continuation-in-part of co-pending, U.S. patent application Ser. No. 837,260, now abandoned by Carayannis et al., filed Mar. 7, 1986, and entitled OPTIMAL PARAMETRIC SIGNAL PROCESSOR, the entire disclosure of which is hereby incorporated by reference thereto. 
    
    
     FIELD OF THE INVENTION 
     The present invention relates to the field of signal processing, and in particular, parametric signal processing. 
     BACKGROUND OF THE INVENTION 
     Parametric signal processing is used in many areas, such as speech and image analysis, synthesis and recognition, neurophysics, geophysics, array processing, computerized tomography, communications and astronomy, to name but a few. 
     One example of signal processing of particular importance is the linear prediction technique, which is used for speech analysis, synthesis and recognition, and for the processing of seismic signals, to enable the reconstruction of geophysical substrata. The linear prediction technique employs a specialized autocorrelation function. 
     Another form of signal processing which finds a multitude of applications, is the determination of an optimal (in the least square sense) finite impulse response filter. A signal processor employing such a technique works with the autocorrelation of the filter input signal and the cross-correlation between the input and the desired response signal, and may be used in many of the above-mentioned applications. 
     Still another form of signal processing of particular importance is known in the art as &#34;L-step ahead&#34; prediction and filtering, for solving the &#34;optimum lag&#34; problem. This technique is especially useful in designing spiking and shaping filters. Signal processors which perform this function employ a specialized autocorrelation function which also takes into account a time lag associated with the system. 
     Generally, as the order of the system under investigation increases, the complexity of the signal processing necessary to provide useful information also increases. For example, using the general Gaussian elimination procedure, a system of order p can be processed in &#34;O(p 3 )&#34; steps, indicating the number of steps as being &#34;on the order of&#34; p 3 , i.e., a function of p cubed. Thus, it will be appreciated that a system having order of p=100 requires on the order of one million processing steps to process the signal, a limitation of readily apparent significance, especially where real time processing is required. 
     Signal processing techniques have been developed which have reduced the number of operations required to process a signal. One such method has been based on a technique developed by N. Levinson, which requires O(p 2 ) sequential operations to process the signal. In particular, the &#34;Levinson technique&#34;  requires O(2·p 2 ) sequential operations in order to process the signal. An improved version of this technique, known as the &#34;Levinson-Durbin&#34; technique requires O(1·p 2 ) sequential operations to process the signal. Neither of these schemes is suitable for parallel implementation. On the general subject of the Levinson and Levinson-Durbin techniques, see N. Levinson, &#34;The Wiener RMS (Root-Mean-Square) Error Criterion in Filter Design and Prediction&#34;, J. Math Phys., Vol. 25, pages 261-278, January 1947; and J. Durbin, &#34;The Fitting of Time Series Models&#34;, Rev. Int. Statist. Inst., Vol. 28, pages 233-244, 1960. 
     Although they represent an order of magnitude improvement over the Gaussian elimination technique, the Levinson and Levinson-Durbin techniques are too slow for many complex systems where real time processing is required. 
     Another way of implementing the main recursion of the Levinson-Durbin technique, for the computation of what is widely known as &#34;lattice coefficients&#34;, was developed by Schur in 1917, in order to establish a system stability criterion. See I. Schur, &#34;Uber Potenzreihen Die Im Innern Des Einheitskreises Beschrankt Sind&#34;, J. Reine Anoewandte Mathematik, Vol. 147, 1917, pages 205-232. Lev-Ari and Kailath, of Stanford University, have developed a different approach, based on the Schur and Levinson techniques, which provides a triangular &#34;ladder&#34; structure for signal processing. The Lev-Ari and Kailath technique uses the signal, per se, as the input to the processor, rather than autocorrelation coefficients, and it is used in the signal modelling context. See H. Lev-Ari and T. Kailath, &#34;Schur and Levinson Algorithms for Non-Stationary Processes&#34;, IEEE International Conference on Acoustics, Speech and Signal Processing, 1981, pages 860-864. 
     In another modification to the Schur technique, Le Roux and C. Gueguen re-derived the Schur algorithm, giving emphasis to the finite word length implementation, using fixed point arithmetics. See Le Roux and Gueguen, &#34;A Fixed Point Computation of Partial Correlation, Coefficients&#34;, IEEE Transactions on Acoustics, Speech, and Signal Processing, June 1977, pages 257-259. 
     Finally, Kung and Hu, have developed a parallel scheme, based on the Schur technique, which uses a plurality of parallel processors, to process a signal, having order p, in O(p) operations, a significant improvement compared to the Levinson-Durbin technique. See Kung and Hu, &#34;A Highly Concurrent Algorithm and Pipelined Architecture for Solving Toeplitz Systems&#34;, IEEE Transactions on Acoustics, Speech and Signal Processing, Vol. ASSP-31, No. 1, February 1983, pp. 66-76. However, the application of the Kung and Hu technique is severely limited insofar as it requires that the number of processors be equal to the order of the system to be solved. Thus, the Kung and Hu technique cannot process a signal produced by a system having an order greater than the number of parallel processors. System complexity is therefore a major limiting factor in using the Kung and Hu technique, insofar as many complex systems may have orders much higher than the number of parallel processors currently available in modern VLSI or other technology. 
     OBJECTS AND SUMMARY OF THE INVENTION 
     It is therefore an object of the present invention to overcome the difficulties associated with prior art signal processors and methods. 
     It is another object of the present invention to provide an optimal parametric signal processor and processing method. 
     It is another object of the present invention to provide a signal processor and processing method which can be implemented using (i) a single processing unit, to process a signal in a fully sequential manner, (ii) a plurality of processing units to process a signal in fully parallel manner, or (iii) a lesser plurality of processing units to process a signal in a &#34;partitioned parallel&#34; manner. 
     It is another object of the present invention to provide a linear prediction signal processor which also forms the basis for L-step ahead and least square-finite impulse response (LS-FIR) processors. 
     It is another object of the present invention to provide a signal processing structure having minimal hardware complexity. 
     In accordance with a basic aspect of the present invention, a signal processor which receives autocorrelation coefficients corresponding to a system, for providing lattice coefficients of the system, comprises processor means for 
     (1) receiving a plurality of autocorrelation coefficients; 
     (2) multiplying a first pair of adjacent autocorrelation coefficients by a first lattice coefficient, resulting in respective first and second products, and for adding (i) one of the first pair of autocorrelation coefficients to the first product, and (ii) the other of said first pair of coefficients, to the second product, to yield a first pair of first intermediate values, during a first time interval; 
     (3) multiplying a second pair of adjacent autocorrelation coefficients by the first lattice coefficient, resulting in respective third and fourth products, and for adding (i) one of the second pair of autocorrelation coefficients to the third product, and (ii) the other of the second pair of coefficients to the fourth product, to yield a second pair of first intermediate values, during a second time interval; and 
     (4) multiplying a selected first and second of the first intermediate values by a second lattice coefficient, resulting in respective fifth and sixth products, and for adding (i) the first of the first intermediate values to the sixth product, and (ii) the second of said first intermediate values to the fifth product, to yield a pair of second intermediate values, during a third time interval; and 
     divider circuitry for forming the quotient of a selected pair of autocorrelation coefficients to produce the first lattice coefficient, and for forming the quotient of a selected pair of the first intermediate values to produce the second lattice coefficient. 
     The processor means may comprise a plurality of parallel processing units, wherein the first and second time intervals occur substantially simultaneously, and precede the third time interval, to provide a fully parallel, or &#34;parallel-partitioned&#34; signal processing. Alternatively, the processor means may comprise a single processing unit, wherein the first time interval precedes the second time interval, which in turn precedes the third time interval, to provide a fully sequential signal processor. 
     In accordance with another aspect of the present invention, a signal processor which receives autocorrelation coefficients of a system, for providing lattice coefficients of the system, comprises an input device for receiving the autocorrelation coefficients, and at least two parallel processing units, each of which includes a processor for (i) multiplying a first one of the autocorrelation coefficients by a first lattice coefficient, resulting in a first product, (ii) multiplying a second one of the autocorrelation coefficients, adjacent to the first one of the autocorrelation coefficients by the first lattice coefficient, resulting in a second product, (iii) and adding (a) the second one of the autocorrelation coefficients to the first product, and (b) the first one of the autocorrelation coefficients to the second product, to yield a pair of first intermediate values. A storage and retrieval structure is provided for applying at least one of the pair of first intermediate values from each of the processing units to at least one of the processing units, to thereby multiply a respective first and second of the first intermediate values by a second lattice coefficient to produce respective third and fourth products, and to add the first of the first intermediate values to the fourth product and the second of the first intermediate values to the third product, to yield a respective pair of second intermediate values. Divider circuitry is also provided for forming the quotient of a selected pair of the autocorrelation coefficients to produce the first lattice coefficient, and for forming the quotient of a selected pair of the first intermediate values, to produce the second lattice coefficient. 
     Many other aspects of the present invention will become apparent to those skilled in the art, the above aspects being merely exemplary. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The foregoing and other objects, aspects and embodiments of the present invention will be described in more detail below with reference to the following drawing figures, of which: 
     FIG. 1 illustrates the &#34;superlattice&#34; processing structure, for the non-symmetrical case, in accordance with the invention of the parent application; 
     FIG. 2 illustrates the signal processing structure which allows the direct predictor coefficients a i , to be derived from the lattice coefficients k i  produced by either the structure of FIG. 1 or the corresponding structure of the present invention; 
     FIG. 3 illustrates the &#34;superlattice&#34; processing structure for the symmetrical case, in accordance with the invention of the parent application; 
     FIG. 4 illustrates a &#34;butterfly basic cell&#34; in accordance with the invention of the parent application; 
     FIG. 5 illustrates the repeated use of the basic cell of FIG. 4, in order to provide the processing structure of FIGS. 1 and 3, in accordance with the invention of the parent application; 
     FIG. 6 illustrates a &#34;lattice basic cell&#34; in accordance with the present invention; 
     FIG. 7 illustrates the repeated use of the lattice basic cell, in accordance with the present invention, and its relationship to the butterfly basic cell; 
     FIG. 8 illustrates the superlattice processing structure for the symmetrical case, in accordance with the present invention; 
     FIG. 9 illustrates the implementation of the superlattice structure using three lattice basic cells, for a system having order eight; 
     FIGS. 10A and 10B illustrate, in detail, the signal flow within the superlattice structure using lattice basic cells, and butterfly basic cells, respectively; 
     FIG. 11 illustrates the signal flow through real and virtual processors which implement the arrangement of FIG. 9; and 
     FIG. 12 illustrates a hardware implementation of the arrangement shown in FIGS. 9 and 11, in accordance with the present invention, illustrating the three lattice basic cells, and associated hardware. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Since the present invention flows from the invention of the parent application, Ser. No. 837,260, a description of the relevant parts of the parent application, as they relate to the present invention, will be made, with reference to FIGS. 1-5, herein. 
     The Non-Symmetrical Case 
     With reference to FIG. I, there is shown a &#34;superlattice&#34; structure of multipliers, designated by triangles, and adders, designated by circles, arranged in a manner to process a signal in order to produce a linear predictor for a non-symmetrical system. This superlattice structure also forms the basis for L-step ahead and LS-FIR processors. 
     As shown in the figure, a signal from a system, having order P, such as a seismic signal, is applied to a well known digital autocorrelator 10, which produces autocorrelation coefficients r -5  through r 5 . The autocorrelation coefficients are delivered to an input device 12, such as a digital register, or buffer memory, for application to the superlattice structure. With the exception of autocorrelation coefficients r -5 , r 0  and r 5 , each autocorrelation coefficient is applied to a pair of multipliers which function to multiply each coefficient by a pair of &#34;lattice coefficients&#34; k n  and k n   * , k n  being the normal lattice coefficient, and k n   *  being the &#34;adjoint&#34; lattice coefficient. The multipliers indicated by white triangles function to multiply the autocorrelation coefficients by the normal lattice coefficient k n , while the multipliers indicated by the black triangles function to multiply the autocorrelation coefficients by the adjoint lattice coefficients k n   * . Production of the normal and adjoint lattice coefficients will be described below. 
     The two products produced by multiplying each autocorrelation coefficient by the normal and adjoint lattice coefficients are added, in the adders indicated by the circles in the figure, to an adjacent pair of autocorrelation coefficients, to produce a set of first intermediate values ζ n   1 , where n=-3, -2, -1, 0, 2, 3, 4, 5, and ξ m   1 , where m=-5, -4, -3, -2, 0, 1, 2, 3. For example, the autocorrelation coefficient r -4 , is multiplied by k 1  and k 1  * in multipliers 14 and 16, respectively, and the products are added to the pair of autocorrelation coefficients r -3  and r -5 , which are adjacent to coefficient r -4 , in adders 18 and 20, respectively. Similarly, autocorrelation coefficient r -3 , after multiplication by lattice coefficients k 1  and k 1* , is individually added to the adjacent pair autocorrelation coefficients r -4  and r -2 . The same process takes place for autocorrelation coefficients r -2  through r 4 , to produce the set of first intermediate values, as shown. 
     For the sake of continuity, the autocorrelation coefficients r -5  through r 5 , are also designated as ζ n   0  and λ m   0 , where n=-4 to 5 and m=-5 to 4. 
     The lattice coefficients are calculated as follows: 
     
         k.sub.m+1 =-ζ.sub.m+1.sup.1 /ζ.sub.o.sup.m 
    
     
         k*.sub.m+1 =ξ.sub.m+1.sup.m /ξ.sub.o.sup.m 
    
     The lattice coefficients k 1  and k 1*  are produced directly from the autocorrelation coefficients, while the second set of lattice coefficients, k 2  and k 2  *, are calculated from the first intermediate values. 
     In a manner similar to that performed to generate the first intermediate values, selected pairs of adjacent first intermediate values, for example, ξ -4   1  and ζ -3   1  are multiplied by the normal and adjoint lattice coefficients k 2  and k 2* , respectively, in multipliers 22 and 24. Two first intermediate values ζ -2   1  and ξ -5   1 , adjacent to, and on either side of the selected pair, are added to the products produced by multipliers 22 and 24 in adders 26 and 18, respectively, to produce two second intermediate values ζ -2   2  and ξ -5   2 . The remaining second intermediate values are generated in a similar manner, namely, by multiplying a selected pair of adjacent first intermediate values by the normal and adjoint lattice coefficients k 2  and k 2  *, and by adding to the products, the first intermediate values adjacent to, and on either side of, the selected pair. 
     It will also be seen that, following this signal flow, the third intermediate values and final intermediate values are generated in a similar manner. 
     It will be seen that this superlattice structure therefore implements the Schur-typ recursions of the form ##EQU1## 
     The lattice coefficients k i  completely characterize the linear predictor and can be used instead of the direct predictor coefficients. In fact, they are preferred for storage, transmission and fast speech synthesis, since they have the considerable advantages of being ordered, bounded by unity and can readily be used for stability control, efficient quantization, and the like. Since r0 corresponds to the energy of the signal, and will therefore have the greatest amplitude of any of the signals processed by the superlattice, all variables can be normalized with respect to r 0 , thus facilitating the use of &#34;fixed point&#34; processing with its attendant advantages of precision, speed, and processing simplicity. 
     The arrangement shown in FIG. 1 can produce lattice coefficients for a system of the type Ra=-d, where R has a Toeplitz structure. A detailed analysis of this technique is given by G. Carayannis et al., &#34;A New Look on the Parallel Implementation of the Schur Algorithm for the Solution of Toeplitz Equations&#34;, IEEE International Conference on Acoustics. Speech and Signal Processing, Mar. 26-29, 1985, the entire disclosure of which is hereby incorporated by reference. 
     Although the lattice coefficients k i  and k i  * are usually preferred, the direct predictor coefficients a i , which are useful in spectral estimation, for example, can be derived from the lattice coefficients using the processing structure of FIG. 2. As shown, the lattice coefficients k 1  and k 1*  are applied to a pair of multipliers 30 and 32, which function to multiply those lattice coefficients by the second lattice coefficients k 2  and k 2* , respectively, to produce a first set of products a 1 ,2 and a* 1 ,2, respectively. These products are then multiplied, in multipliers 34 and 36, respectively, by k 3  * and k 3 , and added to k 2  * and k 2 , respectively, to produce the values a* 2 ,3 and a 2 ,3, respectively. Also, the value of the lattice coefficients k 2  and k 2  * are multiplied by k 3  * and k 3 , respectively, in multipliers 38 and 40, and the intermediate values a* 1 ,2 and a 1 ,2 are added to these products to produce further intermediate values a* 1 ,3 and a 1 ,3 , respectively. This process continues until the direct filter coefficients a 1 ,8 through a 8 ,8 and a* 1 ,8 through a* 8 ,8 are produced. Though described with reference to the parent application, the processing structure of FIG. 2 can also be used with the present invention, as will be appreciated by those skilled in the art. 
     The Symmetrical Case 
     A special situation exists where the system to be analyzed can be characterized by Ra=-d, where R has a symmetrical Toeplitz structure, as in the case of auto-regressive linear prediction. In such cases, the superlattice structure of FIG. 1 is simplified to the symmetrical superlattice form shown in FIG. 3, since r i  =r -i  ; k i  =k i  * and ζ i   m  =ε -i   m , for the symmetrical case. Thus, the two triangular lobes of FIG. 1 become identical, so that one of them can be omitted, allowing the elimination of half of the signal processing. It will be seen that signal processing structure for the symmetrical case, shown in FIG. 3, provides linear prediction, or auto-regressive modelling, by calculating the lattice coefficients, or in the symmetrical case, the &#34;PARCOR&#34; (partial correlation) coefficients. 
     It should initially be noted that with this signal processing structure (as well as that shown in FIG. 1) there is no redundancy. That is, each ζ appearing in the processor is produced only once. Additionally, only those signals needed for the production of lattice coefficients, or PARCORs are involved. Thus, the signal processing structure shown in FIG. 3 (and in FIG. 1) represent optimal processing schemes. 
     In a manner similar to that shown for the nonsymmetrical case of FIG. 1, a system signal is applied to a digital autocorrelator 10, which produces autocorrelation coefficients which characterize the symmetrical system, namely, r 0  through r 8 . The coefficients are applied to an input device 42, such as a digital register or memory. Note that the signal processor of FIG. 3 receives a signal from a system having an order of 8, whereas the system in FIG. 1 receives a signal from a system having an order of 5. 
     As with the signal processor of FIG. 1, the signal processor of FIG. 3 takes each autocorrelation coefficient, except the first and last, namely r 0  and r 8 , and multiplies it by the first lattice coefficient k 1 , which is calculated from r 0  and r 1  (ζ 0   0 , ζ 1   o ), according to the general formula k p  =-ζ p   P-1  /ζ 0   P-2 . The product of each such multiplication is added, individually, to the adjacent two autocorrelation coefficients, to produce the first intermediate values ζ n   1 , where n=0, 2 to 8 and -6 to -1. For example, autocorrelation coefficient r 1 , designated as ζ 1   o  and ζ -1   o , for the sake of conformance with the intermediate variables, is multiplied by lattice coefficient k 1 , and autocorrelation coefficients r 0  and r 2  are added, individually, to the product, to produce a pair of first intermediate values ζ O   1  and ζ 2   1 , respectively. Similarly, the next two first intermediate values, namely ζ -1   1  and ζ 3   1  are produced by multiplying autocorrelation coefficient r 2  by the lattice coefficient k 1 , and adding, individually, the adjacent autocorrelation coefficients, namely, r 1  and r 3  to the products. 
     The second intermediate values can be calculated from the first intermediate values in a similar manner. First, k 2  can be calculated from the ratio of ζ 2   1  and ζ 0   1  in accordance with the formula given above. Then, second intermediate values ζ 3   2  and  ζ 0   2 , for example, are calculated by multiplying the first intermediate values ζ -1   1  and ζ 2   1  by the lattice coefficient k 2 , and adding the adjacent first intermediate values ζ 3   1  and ζ 0   1  to the products, individually. The signal processing continues until the final values ζ 8   7  and ζ 0   7  are obtained, from which the last lattice coefficient k 8  can be calculated from the above formula. 
     The signal processor illustrated in FIG. 3 can be implemented as described with reference to FIGS. 4-8, of the parent application. 
     If direct predictor coefficients are desired, the processing structure shown in FIG. 2 can be employed for the symmetrical case as well as the non-symmetrical case. However, the processing structure of FIG. 2 is somewhat simplified for the symmetrical case since k n  =k n  *. 
     Returning to FIG. 3, implements recursions of the form ζ i   m  =ζ i   m-1  +k m  ζ m-i   m-1 . the symmetrical superlattice of FIG. 3 several points should now be noted. Although drawn as a triangular lobe, to illustrate the precise details of the signal processing, it will be appreciated that the various items of hardware, namely, the multipliers, designated by triangles, and the adders, designated by circles, can be comprised of a single set of 14 multipliers and 14 adders which first function to produce the first intermediate values, then the second intermediate values, and so on through the final values. Furthermore, if 14 multipliers and adders are not available, a lesser number can be shared within any given group of intermediate values. 
     Butterfly Basic Cell 
     A first way to implement this approach, in accordance with one of the aspects of the invention of the parent application, is to utilize a structure which will be called the &#34;butterfly basic cell&#34; or &#34;BBC&#34;. 
     Specifically, FIG. 4 illustrates a BBC 44 which comprises a pair of multipliers 46 and a pair of adders 48. As shown in FIG. 4, the BBC 44 functions to produce a signal e=a+k i .b, and a signal f=d +k i .c. 
     The BBC can be realized with one &#34;two-cycled&#34; processor, or two &#34;one-cycled&#34; processors, to provide signals e and f. The use of the BBC, as defined in FIG. 4, provides a homogeneous configuration in the hardware, in the sense that the repetition of the same BBC suffices to produce the whole superlattice structure. 
     More specifically, FIG. 5 illustrates three BBC&#39;s denoted by solid, dashed and dotted lines, respectively. By merely duplicating the processing unit illustrated in FIG. 4, a superlattice of any size can be &#34;constructed&#34;, to process a signal of virtually any complexity. For example, the superlattice of FIG. 5 will process a signal from a system having order 3. To process a signal from a system having order 4, a first additional BBC can be &#34;placed on top of&#34; BBC 2, to produce first intermediate values e 3  and f 3  (not shown). A second additional BBC would similarly be added, to receive as inputs, e 2 , f 2 , e 3  and f 3 , to produce outputs h 2 , i 2  (not shown). Finally, a third additional BBC would be used to receive h 1 , i 1 , h 2  and i 2  as inputs, and produce outputs j 1  and l 1  (also not shown). 
     Lattice Basic Cell 
     In accordance with the present invention, the processing required for the structure of FIG. 3 is implemented in the manner illustrated in FIG. 6, which illustrates a structure 45 which will be called the &#34;Lattice Basic Cell&#34; or &#34;LBC&#34;. Specifically, the LBC 45, shown in FIG. 6, functions to take a pair of values a,b and multiply each of those values individually, in multipliers 47, by lattice coefficient k i , and the respective products are added to the other of the inputs in adders 49, to produce values e=a+k i  b and g=b+k i  a. Note that the same operation produces e and g when the inputs a and b are interchanged. 
     FIG. 7 illustrates the relationship between the LBC of FIG. 6 and the BBC of FIG. 4. Specifically, within each adjacent pair of LBC&#39;s resides a single BBC. LBC 1 receives inputs a and b and produces outputs e and g therefrom, and LBC 2 similarly receives a pair of inputs, c and d, to produce a pair of outputs f and h. On the other hand, the BBC, illustrated in FIG. 7 by double lines, takes inputs a, b, c and d to produce a pair of outputs e and f, in a manner identical to that illustrated in FIG. 4. 
     Thus, it will be appreciated that a structure similar to that shown in FIG. 3 can be implemented through the repetitive use of LBC&#39;s, rather than BBC&#39;s. One such implementation is illustrated in FIG. 8, which is identical to FIG. 3 except for the upper and lower extensions, which produce intermediate values ζ n   n , for n=1 to 7, along the lower border of the triangular lobe and ζ n   1 , where n=-7 to -1 and i=1 to 7, respectively, along the upper border of the lobe. These additional extensions to the superlattice are due to the structure of the LBC&#39;s. 
     Although it may appear that the use of the LBC&#39;s leads to a structure which is not optimal, because of the upper and lower extensions of the superlattice, there is a distinct advantage when the LBC&#39;s are used instead of the BBC&#39;s: the use of the LBC&#39;s produces a superlattice in which the size of the bordering buffer can be reduced to one-half the size necessary in the case where BBC&#39;s are used, as will be fully explained below. The hardware implementation of the LBC&#39;s is therefore preferable over that of the BBC&#39;s. 
     Also, although the intermediate quantities in the upper extensions of the superlattice are not necessary for the solution of the eighth order signal, those quantities would be used for a signal having order nine The intermediate quantities ζ n   n  in the lower extensions are, by definition, zero, as a consequence of the Yule-Walker equations. 
     In view of the foregoing, it will be appreciated by those skilled in the art that the use of the LBC&#39;s to implement the superlattice illustrated in FIG. 8 can be achieved in a fully parallel implementation, in an order recursive implementation, or in a parallel partitioned implementation, as explained in detail, in the case of BBC&#39;s, in the parent application. A parallel partitioned implementation of the superlattice using the LBC&#39;s will now be described herein, since such implementation includes elements of both the fully parallel and order recursive implementations. 
     Partitioned Parallel Implementation Using LBC&#39;s 
     With reference to FIG. 9, three LBC&#39;s 51, 53 and 55 are illustrated within a superlattice structure for processing a signal from a system having order 8. The signal is processed using the three LBC&#39;s which process the autocorrelation coefficients r 0  -r 3  to produce the first set of intermediate values ζ n   1 , n=-2, 3, -1, 2, 0, and 1. At this point, ζ -2   1  is stored, and the intermediate values ζ 3   1 , ζ -1   1 , ζ 2   1    and ζ 0   1  are fed back to the inputs of two of the LBC&#39;s, for example 53 and 55, and second intermediate values ζ n   2 , n=-1, 3, 0, and 2 are produced. Then, ζ -1   2  is stored and the intermediate values ζ 3   2  and ζ 0   2  are fed back to a single LBC, for example 55, and processed to produce third intermediate values ζ 0   3  and ζ 3   3 . 
     Thusfar, the LBC&#39;s 51, 53 and 55 have implemented, in parallel, the processing technique of the present invention, but for only a portion, or &#34;partition&#34; of the superlattice, corresponding in width to the number of parallel LBC&#39;s employed. This partition will be referred to as &#34;partition 1&#34;. After processing partition 1, the LBC&#39;s 51, 53 and 55 are now supplied with autocorrelation coefficients r 3  -r 6 , in order to implement a second partition, referred to in FIG. 9 as &#34;partition 2&#34;. The LBC&#39;s process the autocorrelation coefficients to produce the first intermediate values ζ n   1 , where n=-5, 6, -4, 5, -3 and 4, which values, except for ζ -5   1 , are fed back to the basic cells 51, 53 and 55, along with the single intermediate value ζ -2   1 , stored during the processing of partition 1. Note that only a single first intermediate value produced during partition 1 is used during the processing of partition 2, in contrast with the implementation using BBC&#39;s, described in the parent application, which requires that two first intermediate values produced during partition 1 be used during the processing of partition 2. 
     The processing of partition 2 continues in a similar manner, until it is complete. As will be appreciated, during the processing of the first two partitions, the lattice coefficients which have been produced (k 1  -k 7 ) are stored. It will also be appreciated that during the processing of partitions 1 and 2, basic cells 51, 53 and 55 operate to &#34;cut through&#34; the superlattice in parallel, in order to provide lattice coefficients k 2  -k 4 , in partition 1, and then recursively &#34;cut through&#34; the superlattice in parallel, to produce lattice coefficients k 5  -k 7  in partition 2. There now only remains the processing for the last lattice coefficient k 8 , which is accomplished in a third partition, &#34;partition 3&#34;. Since the system is of order 8, the processing during partition 3 requires only two LBC&#39;s, for example, 53 and 55. This is in contrast with the third partition shown in FIG. 6 of the parent application, which requires only a single BBC. Although there are three partitions in both cases (FIG. 9 of the present case and FIG. 6 of the parent), the number of partitions can vary between the two techniques. 
     Specifically, the following formulas relate the number of processors (n), the number of partitions (n p ), the system order (p) and the number of active processors in the last partition (α): ##EQU2## where the brackets &#34;[ ]&#34; indicate the integer part of the argument. 
     As mentioned above, an inspection of FIG. 9 will reveal that only a single first intermediate value, ζ -2   1 , a single second intermediate value, ζ -1   2 , and a single third intermediate value, ζ 0   3 , produced during partition 1, need to be stored for the processing of partition No. 2, and likewise for those intermediate values produced during partition No. 2, for use with partition No. 3. This is in contrast with the BBC implementation of the parent application, where a pair of first intermediate values ζ 4   1  and ζ -2   1 , produced during partition 1, are necessary for partition 2, and so on. This leads to a simplified hardware implementation, where the size of the bordering buffer required to implement the structure of FIG. 9 need only be one-half the size of the bordering buffer required to implement the structure of FIG. 6 of the parent application. 
     This principle is briefly explained in FIGS. 10A and 10B, which illustrate the topology of signal flow between partitions in the LBC and BBC implementations, respectively. As shown in FIG. 10A, only a single value at any given time needs to be used from one partition to the next using the LBC implementation, while as shown in FIG. 10B, two different quantities must be stored at a given time for use in the succeeding partition, using the BBC implementation. Thus, a simplified bordering buffer can be realized, as illustrated in FIG. 11, which illustrates the signal flow through real and virtual processors implementing the arrangement of FIG. 9. Specifically, the signal processor is implemented using three parallel processors 57, 59 and 61, designated &#34;real processors&#34;, which respectively include the basic cells 51, 53 and 55 of FIG. 9. Each of the processors 57, 59 and 61 can implement an LBC either as one &#34;two-cycled&#34; processor, or as two &#34;one-cycled&#34; processors. Also shown in FIG. 11, are a plurality of other processors, termed &#34;virtual processors&#34;, the existence of which is simulated, in order to process an input signal in accordance with the superlattice structure of FIG. 9. Each of the processors 57, 59 and 61 receives a pair of adjacent autocorrelation coefficients at its a and b inputs, and functions to process the a and b inputs, along with the lattice coefficient k, to produce a pair of outputs e and g (also shown in FIG. 6). The first lattice coefficient k 1  is produced by dividing autocorrelation coefficients r 1  and r 0  in an initial divider 63. One of the first intermediate values, e, from processor 61 is stored in the bordering buffer, BB, as compared with two such first intermediate values stored in the bordering buffer of the parent application, shown in FIG. 7 therein. 
     First intermediate value e from processor 57 is applied to the a input of virtual processor 63 and first intermediate value g from processor 59 is applied to the b input of virtual processor 63, along with the second lattice coefficient, k 2 , calculated from the quotient of first intermediate values e and g from real processors 57 and 59, respectively. Although illustrated as being transmitted to a further processor 63, the first intermediate values are actually fed back into the same real processors, as will be explained in more detail with reference to FIG. 12. 
     At each iteration through each partition, a new lattice coefficient is calculated, and only a single intermediate value needs to be stored for use in the succeeding partition. 
     FIG. 12 illustrates an example of an actual hardware implementation for providing the partitioned parallel process using LBC&#39;s. Specifically, the parallel processors 57, 59 and 61 are shown as including the LBC&#39;s 51, 53 and 55 of FIG. 9, respectively, and associated logic. Each processor also includes an a,b register and an e,g register, which function to individually store the values a, b, and e, g, associated with each basic cell (as illustrated in FIG. 6), and a k register, which stores the value of a lattice coefficient. 
     Each of the a,b registers receives the appropriate autocorrelation coefficients from an r-buffer 65, via r-bus 65&#39;. The r-buffer also directly provides the first two autocorrelation coefficients r 1  and r 0  to divider 67 and associated logic, which accordingly calculates the initial lattice coefficient k 1 . The output from divider 67 is applied to the k-buffer 69, via k-bus 69&#39;, for storage of the lattice coefficients used throughout the signal processing. 
     The outputs of the a,b registers in the three processors are connected to their associated LBC&#39;s. The third input to the LBC&#39;s is provided by its associated k register, which in turn receives its input from the k-buffer via the k-bus 69&#39;. The output of each LBC is applied to the e,g register. The outputs of the e register in the bottom and middle processors are applied to the inputs of the a registers of the middle and top processors, respectively, while the output of the e register in the top processor is applied to the bordering buffer 71 via the bordering bus 71&#39;. The outputs of the e registers in the bottom and middle processors are also applied to dividers 67 and 73, respectively, the former of which also receives an output from the g register of the bottom processor. In addition, the outputs of the g registers in each processor are applied to the inputs of the b registers of the associated processor, and in the case of the middle processor, the output of the g register is applied to divider 67, while in the case of the top processor, the output of the g register is applied to the divider 73. The outputs from the dividers 67 and 73 are applied to the k-buffer via the k-bus 69&#39;. The divider 67 also receives as an input a signal from the bordering bus 71&#39;, as does the a,b register of the bottom processor 57. 
     The operation of the hardware shown in FIG. 12 to produce the superlattice processing structure illustrated in FIGS. 9 and 11 will now be described: 
     Phase 0--Initial Division (k 1  computation--storage--transmission) 
     The divider 67, attached to the bottom processor, accepts the first two autocorrelation coefficients from the r buffer 65 and produces k 1 . All other elements are idle. k 1  is stored in the k-buffer 69 and transmitted to the k-register of each processor through the k-bus 69&#39;. 
     Phase 1--Initialization of Partition 1 
     The a,b registers of all processors are initialized through the r-bus 65&#39; with the proper autocorrelation coefficients. 
     Phase 2--Lattice Basic Cell computations 
     The LBC&#39;s of all processors compute intermediate values and store them in the e,g registers of each processor. 
     Phase 3--k 2  computation--storage--transmission 
     The divider 67 attached to the bottom processor computes k 2  from the e register of the bottom processor and the g register of the middle processor. k 2  is stored in the k-buffer 69 and transmitted to the a k-register of each processor through the k-bus 69&#39;. 
     Phase 4--Initialization of the a,b registers of each processor, update of the bordering buffer 71 
     The following transfers take place: 
     e of the bottom processor→a of the middle processor. 
     e of the middle processor→a of the top processor. 
     e of the top processor→bordering buffer. 
     g of the middle processor→b of the middle processor. 
     g of the top processor→b of the top processor. 
     Phase 5--Lattice Basic Cell computation with the bottom element idle 
     The LBC&#39;s of the middle and top processor produce intermediate values which are stored in their corresponding e,g registers. 
     Phase 6--k 3  computation--storage--transmission 
     The divider attached to the middle processor computes k 3 , fed by the e register of this processor and the g register of the top processor. k 3  is stored in the k-buffer 69 and transmitted to the k-register of each processor through the k-bus 69&#39;. 
     Phase 7--Initialization of the a,b registers, update of the bordering buffer 
     The following transfers take place: 
     e of the middle processor→a of the top processor. 
     e of the top processor→bordering buffer. 
     g of the top processor→b of the top processor. 
     Phase 8--Top Lattice Basic Cell computation with the bottom and middle processors idle 
     The top LBC computes intermediate values and stores them in its e,g register. 
     Phase 9--Bordering buffer update 
     The following transfer takes place: 
     e of the top processor→bordering buffer. 
     Phase 10 k 1  retransmission 
     k 1 , which has been stored in the k-buffer, is transmitted to the k-registers of all processors through the k-bus. 
     Phase 11 Initialization of partition 2 
     The a,b registers of all processors are initialized through the r-bus with the proper autocorrelation coefficients. 
     Phase 12 Lattice Basic Cell computations 
     The LBC&#39;s of all processors compute intermediate values and store them in the e,g registers of each processor. 
     Phase 13 Initialization of the a,b registers, update of the bordering buffer, and k 2  retransmission 
     The following transfers take place: The a register of the bottom processor is initialized from the bordering buffer. k 2  is retransmitted to the k-registers of all processors. 
     e of the bottom processor→a of the middle processor. 
     e of the middle processor→a of the top processor. 
     e of the top processor→bordering buffer. 
     g of the bottom processor→b of the bottom processor. 
     g of the middle processor→b of the middle processor. 
     g of the top processor→b of the top processor. 
     The a register of the bottom processor must be initialized from the bordering buffer before the contents of the latter are destroyed by the storage of the newly computed contents of e register in the top processor. 
     Phase 14 Lattice Basic Cell computations 
     The same as Phase 12. 
     Phase 15 Initialization of the a,b registers, update of the bordering buffer, k 3  retransmission 
     The same as Phase 13, but k 3  is retransmitted instead of k 2 . 
     Phase 16 Lattice Basic Cell computations 
     The same as Phase 12. 
     Phase 17 k 4  computation - storage - transmission 
     The divider attached to the bottom processor computes k 4  fed by the g register of the bottom processor and a quantity from the bordering buffer. k 4  is stored in the k-buffer and transmitted to the k-register of each processor through the k-bus. 
     Phase 18 Initialization of the a,b registers, update of the bordering buffer 
     The same as Phase 13, except for k 2  retransmission. 
     Phase 19 LBC computation 
     The same as Phase 12. 
     Phase 20 k 5  computation-storage-transmission 
     The same as Phase 3, but k 5  is computed-stored-transmitted instead of k 2 . 
     Phase 21 Initialization of the a,b registers, update of the bordering buffer 
     The same as Phase 4. 
     Phase 22 LBC computations with the bottom processor idle 
     The same as Phase 5. 
     Phase 23 k 6  computation-storage-transmission 
     The same as Phase 6, but k 6  is computed-stored-transmitted instead of k 3 . 
     Phase 24 Initialization of the a,b registers, update of the bordering buffer 
     The same as Phase 7. 
     Phase 25 Top LBC computations with the bottom and middle processors idle 
     The same as Phase 8. 
     Phase 26 Bordering Buffer update 
     The same as Phase 9. 
     Phase 27 k 1  retransmission 
     The same as Phase 10. 
     Phase 28 Initialization of partition 3 
     The same as Phase 11. 
     The continuation through the third partition will be understood by those skilled in the art in view of the foregoing. 
     The superlattice concept is suitable for efficient hardware implementation with commercially available processors. A small number of processors, i.e., 3 to 6 may be used for many applications with very good results and a substantial increase in processing speed over that of prior art signal processors. 
     It will thus be appreciated that the present invention allows the use of a feasible number of parallel processors to perform highly efficient linear prediction signal processing. When so implemented, the parallel-partitioned implementation provides the benefits of parallel processing, manageable hardware complexity, and optimal signal processing for a given number of available processors. It will also be appreciated that by using the LBC&#39;s, hardware complexity can be minimized. 
     Various changes and variations to the present invention will occur to those skilled in the art in view of the foregoing description. It is intended that all such changes and variations be encompassed so long as the present invention is employed, as defined by the following claims.