Patent Publication Number: US-9842806-B2

Title: Stacked semiconductor devices

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application is a continuation of U.S. application Ser. No. 14/733,330, filed Jun. 8, 2015, which is a continuation of U.S. application Ser. No. 13/468,655, filed May 10, 2012, now U.S. Pat. No. 9,054,165, which is a divisional of U.S. application Ser. No. 11/831,247 filed Jul. 31, 2007, which is incorporated herein by reference in its entirety. 
    
    
     TECHNICAL FIELD 
     The present invention is related to semiconductor devices and methods for manufacturing semiconductor devices suitable for stacked die packages and other applications. 
     BACKGROUND 
     Semiconductor devices are typically manufactured on semiconductor wafers or other types of workpieces using sophisticated equipment and processes that enable reliable, high-quality manufacturing. The individual dies (e.g., devices) generally include integrated circuits and a plurality of bond-pads coupled to the integrated circuits. The bond-pads provide external contacts through which supply voltage, electrical signals, and other input/output parameters are transmitted to/from the integrated circuits. The bond-pads are usually very small, and they are typically arranged in dense arrays having a fine pitch between bond-pads. The wafers and dies can also be quite delicate. As a result, the dies are packaged for protection and to provide terminals that can be reliably connected to printed circuit boards. 
     Semiconductor device manufacturers are developing more sophisticated devices in smaller sizes that have increasingly dense arrays of input/output terminals within decreasing “footprints” on printed circuit boards (i.e., the height and surface area that the device occupies on a printed circuit board). One technique to increase the density of microelectronic devices within a given footprint is to stack one microelectronic die on top of another. To fabricate stacked-die packages, the upper and lower dies are electrically coupled to each other and/or a lead frame or interposer substrate. In some applications, it may be desirable to form interconnects that extend completely through the dies or through a significant portion of the dies. Such interconnects can electrically couple bond-pads or other conductive elements at a front side of the dies to conductive elements at the back side of the dies. Through-substrate interconnects, for example, are constructed by forming deep vias at the front side of the workpiece in alignment with corresponding bond-pads. The vias are often blind vias in that they are closed at one end within the workpiece. The blind vias are then lined with a dielectric material and filled with a conductive fill material. The workpiece is thinned from the back side to expose the interconnects and reduce the thickness of the final dies. Solder balls or other external electrical connectors are subsequently attached to the through-substrate interconnects at the back side and/or the front side of the workpiece. The external connectors can be attached to the interconnects either before or after singulating the dies from the workpiece. 
     Conventional processes for forming external connectors on through-substrate interconnects at the back side of the workpiece include (a) depositing a dielectric layer on the back side of the workpiece, (b) forming a photo-resist layer on the dielectric layer, (c) patterning and developing the photo-resist layer, (d) etching completely through the dielectric layer to form holes aligned with corresponding interconnects, (e) removing the photo-resist layer from the workpiece, and (f) forming external connectors on the interconnects located in the holes in the dielectric layer. One concern with forming external connectors on the back side of a workpiece is that conventional processes are relatively expensive because patterning the photo-resist layer requires expensive and time-consuming photolithography equipment and processes to achieve the tolerances required in semiconductor devices. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a schematic cross-sectional view of a portion of a semiconductor wafer with semiconductor devices in accordance with an embodiment of the technology. 
         FIGS. 2A-2F  are schematic cross-sectional views illustrating embodiments of stages of a method for fabricating semiconductor devices. 
         FIGS. 3A and 3B  are schematic cross-sectional views illustrating stages of an embodiment of another method for fabricating semiconductor devices. 
         FIGS. 4A-4C  are top plan views of different embodiments of semiconductor devices. 
         FIG. 5  is a flow chart illustrating an embodiment of a method for fabricating semiconductor devices. 
         FIG. 6  is a flow chart illustrating another embodiment of a method for fabricating semiconductor devices. 
         FIG. 7  is a flow chart illustrating another embodiment of a method for fabricating semiconductor devices. 
         FIG. 8  is a schematic cross-sectional view illustrating an embodiment of a stacked-die assembly. 
         FIGS. 9A and 9B  are schematic cross-sectional views illustrating stages of an embodiment of another method for fabricating semiconductor devices. 
         FIG. 10  is a schematic illustration of a system including semiconductor devices. 
     
    
    
     DETAILED DESCRIPTION 
     Specific details of several embodiments are described below with reference to semiconductor devices and methods for fabricating semiconductor devices. The semiconductor devices are manufactured on and/or in semiconductor wafers that can include substrates upon which and/or in which microelectronic devices, micromechanical devices, data storage elements, optics, read/write components, and other features are fabricated. For example, SRAM, DRAM (e.g., DDR/SDRAM), flash memory (e.g., NAND flash-memory), processors, imagers, and other types of devices can be constructed on semiconductor wafers. Although many of the embodiments are described below with respect to semiconductor devices that have integrated circuits, other embodiments can have other types of devices manufactured on other types of substrates. Moreover, several other embodiments can have different configurations, different components, or additional features or procedures than those described in this section. Still other embodiments may not have several of the features shown and described below with reference to  FIGS. 1-10 . 
       FIG. 1  is a schematic cross-sectional view illustrating a portion of an embodiment of a semiconductor wafer  100 . In this embodiment, the semiconductor wafer  100  includes a semiconductor substrate  102  having a first surface  104  and a second surface  106 . The semiconductor substrate  102  can be formed from silicon, gallium arsenide, or other suitable semiconductive materials. The wafer  100  also includes a plurality of semiconductor dies  110  (e.g., devices) formed on and/or in the semiconductor substrate  102 . The dies  110  are arranged in a die pattern across the semiconductor substrate  102  such that the dies  110  are spaced apart by cutting lanes C-C. For purposes of illustration, only two dies  110  are illustrated in  FIG. 1 , but in practice a large number of dies (e.g., 50-250) are formed on a single semiconductor substrate. Individual dies  110  include integrated circuitry  112 , a plurality of first external contact sites  114  at the first surface  104  of the substrate  102 , and a plurality of second external contact sites  116  at least proximate to the second surface  106  of the substrate  102 . The dies  110  can further include a plurality of conductive features  120  electrically coupled to the integrated circuitry  112 , the first external contact sites  114 , and the second external contact sites  116 . 
     The particular embodiment of the conductive features  120  illustrated in  FIG. 1  are through-substrate interconnects. In this embodiment, the conductive features  120  have first ends  122  at the first external contact sites  114  and second ends  124  defining the second external contact sites  116 . The second ends  124  of the conductive features  120  can be offset from the second surface  106  of the substrate  102 . For example, the second ends  124  of the conductive features  120  can project outwardly or otherwise away from the second surface  106  of the substrate such that the tips of the second ends  124  are spaced apart from the second surface  106  by an offset distance O. 
     The semiconductor wafer  100  can further include a dielectric layer  130  at the second surface  106  of the substrate  102 . The dielectric layer  130  can be composed of a polymeric material or another suitable dielectric material for protecting the second surface  106  of the substrate  102 . The dielectric layer  130 , for example, can be composed of a photo-imageable polymer, such as a photo-imageable polyimide. The dielectric layer  130  has a plurality of depressions  132  at the second external contact sites  116 . The depressions extend to a depth D at an intermediate level within the dielectric layer  130  such that at least the tips of the second ends  124  of the conductive features  120  are exposed within the depressions  132 . In many applications, the depressions  132  have bottom surfaces  134  at the intermediate depth D such that the bottom surfaces  134  are below the tips of the second ends  124  of the conductive features  120  but above the second surface  106  of the substrate  102 . The depth that the depressions  132  extend into the dielectric layer  130  is accordingly less than the total thickness T of the dielectric layer  130  such that a portion of the dielectric layer  130  remains on the second surface  106  of the substrate  102  at the depressions  132 . As such, the portions of the second surface  106  aligned with the depressions  132  and adjacent to the conductive features  120  are not exposed within the depressions  132 , but at least a portion of the second ends  124  of the conductive features  120  are exposed within the depressions  132 . 
       FIGS. 2A-2F  illustrate stages of forming a portion of one of the semiconductor dies  110  noted by the dotted lines in  FIG. 1 . Referring to  FIG. 2A , the substrate  102  is mounted to a carrier film  210  by an adhesive  212  at the first surface  104 . The substrate  102  is at a full thickness at this stage, and the conductive feature  120  has been formed in a blind hole such that the second end  124  of the conductive feature  120  is at an intermediate elevation I within the substrate  102 . Suitable methods for forming the conductive feature  120  are disclosed in U.S. patent application Ser. Nos. 10/925,501; 11/056,211; 11/217,877; and Ser. No. 11/215,214, all of which are incorporated by reference herein in their entirety. 
       FIG. 2B  illustrates a stage after the substrate  102  has been thinned from the full thickness illustrated in  FIG. 2A  to at least the intermediate elevation I ( FIG. 2A ) to form a thinned surface  214  at which the second end  124  of the conductive feature  120  is exposed or very nearly exposed. In the embodiment illustrated in  FIG. 2B , the substrate  102  has been thinned to the extent that the second end  124  of the conductive feature  120  is exposed at the thinned surface  214 . In other embodiments, however, the substrate  102  can be thinned to a thinned surface  214 ′ (shown in dashed lines) spaced apart from the second end  124  of the conductive feature  120  by a small distance such that the second end  124  is not exposed at this stage. The substrate  102  can be thinned using back-grinding, chemical-mechanical planarizing, or other suitable techniques for efficiently and accurately removing material from the substrate  102 . 
       FIG. 2C  illustrates a subsequent stage in which material has been removed from the thinned surface  214  illustrated in  FIG. 2B  to form the second surface  106  of the substrate at an elevation that is spaced apart from the second end  124  of the conductive feature  120 . For example, a tip  221  of the second end  124  can be spaced apart or otherwise offset from the second surface  106  by the offset distance O explained above with respect to  FIG. 1 . The material can be removed from the thinned surface  214  illustrated in  FIG. 2B  to form the second surface  106  of the substrate  102  shown in  FIG. 2C  by etching or otherwise removing material from the substrate  102  without removing as much material from the second end  124  of the conductive feature  120 . Suitable processes for selectively etching silicon or other semiconductor materials are known in the art. 
       FIGS. 2D-2F  illustrate additional stages of methods for fabricating semiconductor devices.  FIG. 2D  illustrates a stage after a dielectric material has been deposited onto the second surface  106  of the substrate  102  to form the dielectric layer  130 . The dielectric material can be deposited using spin-on, electrochemical deposition (e.g., electrophoretic resists), or other suitable techniques for depositing the dielectric material onto the second surface  106 . The dielectric layer  130  also covers the second end  124  of the conductive feature  120 . The dielectric material of the dielectric layer  130  can be a photo-imageable polymer or other suitable dielectric material for protecting the second surface  106  of the substrate  102 . 
       FIG. 2E  illustrates a subsequent stage including irradiating areas of the dielectric layer  130  at the second ends  124  of the conductive features  120  to form photo-reacted material  250  (illustrated in dotted lines) in the dielectric layer  130 . The photo-reacted material  250  shown in  FIG. 2E  extends to at least approximately the depth D in the dielectric layer  130 . As a result, the dielectric layer  130  has a remaining thickness T r  between the second surface  106  and the photo-reacted material  250 . The photo-reacted material  250  can be formed by positioning a mask  260  relative to the substrate  102  such that openings  262  in the mask  260  are at least generally aligned with the second ends  124  of corresponding conductive features  120 . After positioning the mask  260 , the portions of the dielectric layer  130  aligned with the openings  262  are irradiated at an energy level E less than the minimum energy level E 0  required for the radiation to photo-chemically react the dielectric material through the full thickness T of the dielectric layer  130 . By irradiating areas of the dielectric layer  130  at the second ends  124  of the conductive features  120  at the energy level E, the photo-reacted material  250  extends to only the intermediate depth D within the dielectric layer  130  instead of the full thickness T of the dielectric layer  130 . The relative dosage level for exposing or otherwise irradiating the dielectric material can be selected according to several parameters. The energy level E, for example, can be the lowest amount of energy that forms a photo-reacted region with sufficient depth to be at or below the tip  221  of the second end  124  of the conductive feature  120 . In one embodiment, the energy level E can be approximately 20-50% of E 0 . In other embodiments, the energy level E can be less than approximately 80% of the energy E 0 , less than approximately 50% of E 0 , or 10% to 80% of E 0 . 
       FIG. 2F  illustrates a stage in which one of the depressions  132  is formed in the dielectric layer  130  by removing the photo-reacted material  250  ( FIG. 2E ) from the dielectric layer  130 . The depression  132  can be formed by developing the photo-reacted region of the dielectric layer  130  with a suitable solution that dissolves the photo-reacted region selectively relative to the unreacted portions of the dielectric layer  130  and the material of the conductive feature  120 . The depression  132  exposes at least a portion of the second end  124  of the conductive feature  120  without exposing the second surface  106  of the substrate  102 . For example, the floor or bottom surface  134  of the depression  132  can be spaced apart from the second surface  106  of the substrate  102  by approximately the remaining thickness T r  ( FIG. 2E ) of the dielectric layer  130  such that the remaining thickness of the dielectric layer covers the surface of the substrate adjacent to the second end  124  of the conductive feature  120 . The depression  132  and the second end  124  of the conductive feature  120  accordingly define the second external contact site  116  associated with this conductive feature  120 . 
     In the particular embodiment illustrated in  FIG. 2F , the depression  132  has a cross-sectional dimension W 1  greater than a cross-sectional dimension W 2  of the conductive feature  120 . The depression  132  can have other cross-sectional dimensions that are equal to or less than the cross-sectional dimension W 2  of the conductive feature  120 . The ability to use a larger cross-sectional dimension for the depression  132  compared to the cross-sectional dimension of the conductive feature  120  makes it easier to align the openings in the mask  260  ( FIG. 2E ) with the conductive features  120 . After forming the depressions  132 , the carrier film  210  and adhesive  212  can be removed from the first surface  104 , and then solder balls, wire bonds, or other types of connectors can be attached to the first and second external contact sites  114  and  116 . 
     Several embodiments described above with respect to  FIGS. 2A-2F  can cost-effectively form stackable dies and inhibit metal shorting to the substrate. For example, because the depressions  132  can be larger than the second ends  124  of the conductive features  120 , the alignment tolerance between the openings  262  in the mask  260  ( FIG. 2E ) and the conductive features  120  can be relatively large to mitigate alignment concerns. Additionally, because the depressions  132  do not expose the second surface  106  of the substrate  102 , the second external contact sites  116  eliminate the possibility of shorting between the substrate  102  and solder balls or other conductive connectors attached to the second ends  124  of the conductive features  120 . 
       FIGS. 3A and 3B  illustrate stages of another method for forming a semiconductor device. Like reference numbers refer to like components in  FIGS. 1-3B .  FIG. 3A , more specifically, illustrates a stage similar to the stages illustrated in  FIGS. 2D and 2E  explained above. In  FIG. 3A , however, the dielectric layer  130  is irradiated at the second end  124  of the conductive feature  120  using a laser L instead of a micro-lithography process. The laser L ablates or otherwise removes the portion of the dielectric layer  130  covering the second end  124  of the conductive feature  120 . The dielectric layer  130  in this embodiment, therefore, does not need to be a photo-imageable polymer or other type of a photo-imageable material. The dielectric layer  130  can instead be any suitable material that can be removed using a suitable laser.  FIG. 3B  illustrates a stage after which the laser L has formed a depression  132  in the dielectric layer  130  to expose at least a portion of the second end  124  of the conductive feature  120 . The exposed portion of the second end  124  in the depression  132  accordingly defines one of the second external contact sites  116 . 
       FIGS. 4A-4C  illustrate various types of depressions formed relative to the second ends  124  of the conductive features  120 , and like reference numbers refer to like components in  FIGS. 4A-4C .  FIG. 4A , more specifically, illustrates an embodiment in which discrete depressions  132   a  are formed at corresponding conductive members  120 . For example, only a single second end  124  of a single conductive member  120  is exposed in a single one of the depressions  132   a . The depressions  132   a  can be circular, rectilinear, or any other suitable shape to expose the individual conductive members  120 .  FIG. 4B  illustrates an alternative embodiment in which individual depressions  132   b  expose a plurality of second ends  124  of separate conductive features  120 . The depressions  132   b , for example, can be long trenches aligned with the second ends  124  of a plurality of conductive features  120  along one direction Y relative to the wafer.  FIG. 4C  illustrates another embodiment in which the individual depressions  132   c  extend along a direction X of the wafer relative to the depressions  132   b  illustrated in  FIG. 4B . 
       FIG. 5  is a flow chart illustrating an embodiment of a method  500  for fabricating a semiconductor device. The method  500  can include forming a conductive feature extending through a semiconductor substrate such that the conductive feature has an end projecting outwardly from a surface of the substrate (block  510 ). The method  500  can further include forming a dielectric layer over the surface of the substrate and the end of the conductive feature (block  520 ) and forming a recess (e.g., a depression) in the dielectric layer (block  530 ). The recess, for example, can extend to an intermediate depth within the dielectric layer such that at least a portion of the end of the conductive feature is in the recess. 
       FIG. 6  is a flow chart of an embodiment of another method  600  for fabricating a semiconductor device. The method  600  can include constructing a plurality of conductive features, such as interconnects in a semiconductor substrate (block  610 ). The interconnects can be constructed such that individual interconnects have a first end electrically coupled to a bond site at a first surface of a substrate and a second end projecting away from a second surface of the substrate. For example, the second end of the interconnect can project away from the second surface of the substrate such that a tip of the second end of the interconnect is non-planar relative to the second surface of the substrate (e.g., offset from the second surface  106 ). The method  600  can further include depositing a photosensitive or otherwise photo-reactive dielectric layer over the second surface of the substrate and the second ends of the interconnects (block  620 ). The method can also include irradiating areas of the dielectric layer at the second ends of the interconnects to form a plurality of photo-reacted regions in the dielectric layer (block  630 ) and removing the photo-reacted regions such that at least a portion of the second ends of the interconnects are exposed (block  640 ). The process of irradiating areas of the dielectric layer can include forming the photo-reacted regions such that the photo-reacted regions extend to a depth in the dielectric layer less than the thickness of the dielectric layer. 
       FIG. 7  is a flow chart of an embodiment of another method  700  for fabricating a semiconductor device. The method  700  can include forming conductive features in a semiconductor substrate (block  710 ) such that the conductive features have first contact ends at bond sites and second contact ends spaced apart from the first contact ends. The method  700  can further include offsetting the second contact ends of the conductive features from a surface of the semiconductor substrate (block  720 ) and covering the surface of the substrate and the second contact ends of the conductive features with a dielectric material (block  730 ). The method  700  can also include exposing the contact ends of the conductive features by forming depressions in the dielectric material (block  740 ). For example, the depressions can be formed to be at least as large as the second contact ends without exposing the surface of the substrate through the depressions. 
       FIG. 8  is a schematic cross-sectional view of a stacked-die assembly  800  having a first semiconductor die  110   a  and a second semiconductor device  110   b  stacked on the first semiconductor die  110   a . The first and second semiconductor dies  110   a - b  can be similar to the semiconductor dies  110  described above with respect to  FIG. 1 , and therefore like reference numbers refer to like components in  FIGS. 1 and 8 . The stacked-die assembly  800  can be formed by depositing first connectors  801  onto the first external contact sites  114  of the first semiconductor die  110   a  and disposing second connectors  802  between the second ends  124  of the conductive features  120  of the first semiconductor die  110   a  and the first external contact sites  114  of the second semiconductor die  110   b . The second connectors  802  can be solder balls or other types of electrical links that are deposited or otherwise formed on either the second ends  124  of the conductive features  120  of the first semiconductor die  110   a  or the first external contact sites  114  of the second semiconductor die  110   b . The first and second semiconductor dies  110   a - b  are then aligned and positioned so that the second connectors  802  electrically couple the conductive features  120  of the first semiconductor die  110   a  with corresponding conductive features  120  of the second semiconductor die  110   b.    
       FIGS. 9A and 9B  are schematic cross-sectional views of stages of another embodiment for fabricating semiconductor devices, and like reference numbers refer to like components and procedures in  FIGS. 1-9B .  FIG. 9A  illustrates globally irradiating the dielectric layer  130  at an energy level E less than the energy level E 0  using a lamp to form a stratum of photo-reacted material  950  (illustrated in dotted lines) at an intermediate depth completely across the dielectric layer  130 . The photo-reacted material  950  shown in  FIG. 9A  is similar to the photo-reacted region shown in  FIG. 2E , and thus the photo-reacted material  950  extends to at least approximately the depth D in the dielectric layer  130 . As a result, the dielectric layer  130  has a remaining thickness T r  between the second surface  106  and the photo-reacted material  950 . The irradiation procedure in  FIG. 9A , however, is a global flood exposure procedure that exposes large areas and even the full surface area of the dielectric layer  130  without using a mask or micro-lithography equipment. Suitable systems for exposing the dielectric layer  130  include ultraviolet lamps, such as the UVEX UV tool, as an alternative to stepper or scanner tools used in micro-lithography processes. The relative dosage level for exposing or otherwise irradiating the dielectric material can be selected according to several parameters. The applied energy level E, for example, can be the lowest amount of energy that forms the photo-reacted region with sufficient depth to be at or below the tip  221  of the second end  124  of the conductive feature  120 . As noted above, the energy level E can be approximately 20-50% of E 0 , but in other embodiments the energy level E can be less than approximately 80% of the energy level E 0 , less than approximately 50% of E 0 , or 10% to 80% of E 0 . 
       FIG. 9B  illustrates a subsequent stage in which the stratum of photo-reacted material  950  has been stripped or otherwise removed completely across the substrate to expose the second ends  124  of the conductive features  120 . The photo-reacted material  950  can be removed by developing the photo-reacted material  950  to clear the portion of the dielectric layer  130  above the second ends  124 . The remaining thickness of the dielectric layer accordingly covers the second side of the surface of the substrate adjacent to the second ends of the conductive features  120  and across other regions of the substrate surface. In this embodiment, the second ends  124  define the external contact sites at the second side or back side of the wafer. After forming the external contact sites, solder balls or other electrical connectors can be formed at the second ends  124  of the conductive features  120 . 
     The embodiment of the method shown in  FIGS. 9A and 9B  provides a fast, low-cost process for forming external contact sites at through-substrate interconnects or other types of interconnects. For example, several examples of the method shown in  FIGS. 9A and 9B  use a flood lamp instead of micro-lithography equipment to increase the number of wafers that can be processed per hour and reduce the use of expensive micro-lithography equipment. 
     Any one of the semiconductor components described above with reference to  FIGS. 1-10  can be incorporated into any of a myriad of larger and/or more complex systems, a representative example of which is system  1000  shown schematically in  FIG. 10 . The system  1000  can include a processor  1001 , a memory  1002  (e.g., SRAM, DRAM, flash, and/or other memory device), input/output devices  1003 , and/or other subsystems or components  1004 . The foregoing semiconductor components described above with reference to  FIGS. 1A-6  may be included in any of the components shown in  FIG. 10 . The resulting system  1000  can perform any of a wide variety of computing, processing, storage, sensing, imaging, and/or other functions. Accordingly, representative systems  1000  include, without limitation, computers and/or other data processors, for example, desktop computers, laptop computers, Internet appliances, hand-held devices (e.g., palm-top computers, wearable computers, cellular or mobile phones, personal digital assistants, etc.), multi-processor systems, processor-based or programmable consumer electronics, network computers, and minicomputers. Other representative systems  1000  include cameras, light or other radiation sensors, servers and associated server subsystems, display devices, and/or memory devices. In such systems, individual dies can include imager arrays, such as CMOS imagers. Components of the system  1000  may be housed in a single unit or distributed over multiple, interconnected units (e.g., through a communications network). The components of the system  1000  can accordingly include local and/or remote memory storage devices and any of a wide variety of computer-readable media. 
     From the foregoing, it will be appreciated that specific embodiments have been described herein for purposes of illustration, but well-known structures and functions have not been shown or described in detail to avoid unnecessarily obscuring the description of the embodiments of the invention. Where the context permits, singular or plural terms may also include the plural or singular term, respectively. Moreover, unless the word “or” is expressly limited to mean only a single item exclusive from the other items in reference to a list of two or more items, then the use of “or” in such a list is to be interpreted as including (a) any single item in the list, (b) all of the items in the list, or (c) any combination of the items in the list. Additionally, the term “comprising” is used throughout to mean including at least the recited feature(s) such that any greater number of the same feature and/or additional types of other features are not precluded. It will also be appreciated that specific embodiments have been described herein for purposes of illustration, but that various modifications may be made without deviating from the inventions. For example, many of the elements of one embodiment can be combined with other embodiments in addition to, or in lieu of, the elements of the other embodiments. Accordingly, the disclosure can include other embodiments not shown or described above.