Patent Publication Number: US-6343306-B1

Title: High speed one&#39;s complement adder

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates to adders in general and in particular to one&#39;s complement adders built from two&#39;s complement adders. 
     Two&#39;s complement adders and one&#39;s complement adders are circuits used to add binary numbers, typically adding two binary numbers at a time. The operation of such adders is essentially the same for different sizes of binary numbers, but the addends and the sums are normally all represented by the same number of bits. 
     Binary addition (one&#39;s complement and two&#39;s complement) can be explained with a few simple examples. Suppose the two four-bit binary numbers 0011 and 0110 are being added. With two&#39;s complement addition, the sum of these two numbers is 1001. Two&#39;s complement addition corresponds well to the grade school notion of addition, in that 0011 and 0110 are binary representations of 3 and 6, respectively, and 1001 is the binary representation of 9, which is the sum of 3 and 6. Where N-bit binary numbers are being added and the sum is greater than 2 N−1 , a carry results. For example, 1001 and 1000 sum to 0001 and a carry (the carry bit representing in “1” in the 16&#39;s column). With one&#39;s complement addition, the carries are added back to the result. Thus, the one&#39;s complement sum of 0011 and 0110 is 1001 (as with two&#39;s complement addition), but the one&#39;s complement sum of 1001 and 1000 is 0010. 
     Two&#39;s complement adders are much more prevalent than one&#39;s complement adders because two&#39;s complement addition is used more. As standard cell logic developed, many cell developers refined and optimized two&#39;s complement adder cells. Cells are preconfigured and pre-tested logic components for a particular process technology, usually a discrete logic technology or a semiconductor technology such as ECL or CMOS. While many two&#39;s complement adders have been developed for use in various process technologies, one&#39;s complement adders are not typically developed. Instead, one&#39;s complement adders are formed from two&#39;s complement adders. 
     One common and simple approach to creating an one&#39;s complement adder out of a two&#39;s complement adder is to start with a standard two&#39;s complement adder and connect the carry output of the two&#39;s complement adder to the carry input of the two&#39;s complement adder to effect the one&#39;s complement addition. Thus, the addends are added and, if the result of that addition generated a carry, the carry input is added to the result. This two-step process is a well-known approach to making a one&#39;s complement adder out of a two&#39;s complement adder. An example of such a one&#39;s complement adder is shown in FIG.  1 . There, a two&#39;s complement adder  10  is configured to be a one&#39;s complement adder by coupling the carry output of two&#39;s complement adder  10  (COUT) to the carry input of two&#39;s complement adder  10  (CIN). Thus, when two N-bit addends, A and B, are applied to the addend inputs of two&#39;s complement adder  10  (IN 1  and IN 2 ), the resulting N-bit output, R, is provided at the output of two&#39;s complement adder  10  (OUT), where R=A+B, with “+” representing the N-bit one&#39;s complement addition operation. 
     Of course, the circuit must take into account that the two addends must be added together and the sum generated before the carry input is taken into account. Otherwise, a race condition might occur. One solution to the race problem is proposed in U.S. Pat. No. 4,298,952. As shown in that patent, the carry output can be conditioned into a generate signal G that is coupled to the carry input instead of the carry output. 
     While the conventional uses of two&#39;s complement adders to form one&#39;s complement adders work well in practice, they are often too slow for some applications. While changing to faster process technologies might increase the speed of a circuit, a better result is usually had by reducing the number of logic cycles needed for a given operation. 
     SUMMARY OF THE INVENTION 
     The problems of the prior art described above are overcome by the present invention. A one&#39;s complement adder according to one embodiment of the present invention uses two two&#39;s complement adders. Both of the two&#39;s complement adders are coupled to receive first and second addends at their addend inputs, however the first two&#39;s complement adder is adapted to output a first sum that is the one&#39;s complement sum that would result if no carry occurred upon addition of the first and second addends and the second two&#39;s complement adder is adapted to output a second sum that is the one&#39;s complement sum that would result if a carry did occur. A selector selects one of the first sum and the second sum as its output (and the output of the one&#39;s complement adder) based on whether or not a carry occurred. 
     In a particular embodiment, the indication of whether or not a carry occurred or not is determined from the carry output of the first complement adder. In a specific embodiment, the first sum is effected by setting the carry input for the first two&#39;s complement adder to “0” (no carry in), the second sum is effected by setting the carry input for the second two&#39;s complement adder to “1” (carry in) and the selector is a multiplexer with a select input coupled to the carry output of the first two&#39;s complement adder. 
     One advantage of such a one&#39;s complement adder is that the addition occurs in one pass instead of the passes of the conventional one&#39;s complement adder. 
    
    
     A further understanding of the nature and advantages of the inventions herein may be realized by reference to the remaining portions of the specification and the attached drawings. 
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic diagram of a prior art one&#39;s complement adder. 
     FIG. 2 is a schematic diagram of a one&#39;s complement adder according to one embodiment of the present invention. 
     FIG. 3 illustrates packet datagrams; FIG.  3 ( a ) shows the format of an IP packet datagram and FIG.  3 ( b ) shows the format of a UDP packet datagram. 
     FIG. 4 is a block diagram of a packet processor which uses the one&#39;s complement adder of FIG. 2 to process packets such as those shown in FIG.  3 . 
    
    
     DESCRIPTION OF THE SPECIFIC EMBODIMENTS 
     One specific embodiment of a one&#39;s complement adder  100  is shown in the schematic diagram shown as FIG.  2 . One&#39;s complement adder  100  is shown comprising two two&#39;s complement adders  102  and a multiplexer  104 . When a specific two&#39;s complement adder is referenced, the label “ 102 ( 0 )” or “ 102 ( 1 )” is used. Each two&#39;s complement adder  102  includes two addend inputs, IN 1  and IN 2 , a carry out output COUT, a carry in input CIN and a two&#39;s complement addition output OUT. Multiplexer  104  includes two selection inputs IN 0  and IN 1 , a selection input SEL and an output OUT. 
     In the schematic diagram of FIG. 2, the binary values of two addends, A and B, are provided to addend inputs of one&#39;s complement adder  100 , which are coupled within one&#39;s complement adder  100  to the addend inputs of two&#39;s complement adders  102 , with the addend A being applied to the addend input IN 1  of each two&#39;s complement adder  102  and the addend B being applied to the addend input IN 2  of each two&#39;s complement adder  102 . A logical level indicating “no carry” (“0” in this example) is applied to two&#39;s complement adder  102 ( 0 ), while a logical level indicating “carry” (“1” in this example) is applied to two&#39;s complement adder  102 ( 1 ). The output OUT of two&#39;s complement adder  102 ( 0 ) is coupled to the input IN 0  of multiplexer  104  and the output OUT of two&#39;s complement adder  102 ( 1 ) is coupled to the input IN 1  of multiplexer  104 . As for the carry out outputs, the COUT output of two&#39;s complement adder  102 ( 0 ) is coupled to the selection input SEL of multiplexer  104  and the COUT output of two&#39;s complement adder  102 ( 1 ) is left unconnected. 
     If necessary, two&#39;s complement adders  102  and the output of one&#39;s complement adder  100  are clocked by a clock signal (not shown) and the addends A and B are supplied at the appropriate time within a clock period. As the addends are applied to two&#39;s complement adders  102 , two&#39;s complement adder  102 ( 0 ) generates a sum that would be the one&#39;s complement sum of A and B if there were no carry and two&#39;s complement adder  102 ( 1 ) generates a sum that would be the one&#39;s complement sum of A and B if there were a carry. About the same time that two&#39;s complement adders  102  output their results to multiplexer  104 , two&#39;s complement adder  102 ( 0 ) outputs the carry signal (“carry” or “no carry”) for the addition. As can be seen from the schematic of FIG. 2, if there is a carry, the resultant one&#39;s complement sum, R, is the sum output by two&#39;s complement adder  102 ( 1 ), but if there is no carry, R is the sum output by two&#39;s complement adder  102 ( 0 ). 
     As described above, the circuit shown in FIG. 2 will output the correct one&#39;s complement sum in one clock cycle (half the time it would take one two&#39;s complement adder to perform the full operation). That circuit trades off less efficient use of chip real estate (since two two&#39;s complement adders are needed where only one was needed in the prior art scheme) to increase processing speed. In many applications, speed is more critical than chip space usage. One such application is error checking checksums in a packet-switched network. 
     The Internet is, at its core, a packet-switched network. Two common protocols for Internet packet traffic are TCP/IP (Transport Control Protocol/Internet Protocol) packets and UDP (User Datagram Protocol) packets. FIG. 3 shows examples of packet datagrams; FIG.  3 ( a ) shows the format of an IP packet datagram and FIG.  3 ( b ) shows the format of a UDP packet datagram. As shown, both IP packets and UDP packets include 16-bit header checksum fields. 
     As a router or other packet handling device receives and forwards packets, it is often desirable for the device to drop corrupted packets instead of forwarding them. There are many benefits to dropping corrupted packets, such as the fact that it reduces the downstream work that has to be done on data that cannot be used anyway and it may reduce the time it takes the sender or receiver to detect that a packet was lost and needs to be retransmitted. One way to detect corrupted packets is to check the checksums of the packets as they pass though the device. However, since packets are relatively small, many packets must pass through the device in a given time span, if the packets are to be checked, the checksums must be checked very quickly. 
     In the IP protocol, the checksum of a packet is calculated by treating the packet&#39;s header as a sequence of 16-bit words and taking the one&#39;s complement sum of all the words (except the word representing the checksum itself) and using the one&#39;s complement of the resulting sum as the checksum. Thus, upon receipt of a packet, the device can check for corruption by performing a 16-bit one&#39;s complement addition of all the words of the packet&#39;s header. 
     Various other Internet protocols use the same checksum process, such as ICMP (Internet Control Message Protocol) and IGMP (Internet Group Management Protocol). Other non-Internet protocols also might use a similar checksum process. Given that the checksums need to be calculated very quickly, it is advantageous to use the one&#39;s complement adder described above. In one prototype ASIC (application specific integrated circuit), operating with a 133 MHz clock speed, a one&#39;s complement addition operation is completed in about 7.5 ns. 
     FIG. 4 is a block diagram of a device  200  that uses a one&#39;s complement adder, such as one&#39;s complement adder  100  shown in FIG. 2, to quickly calculate and check checksums. Device  200  is shown comprising a packet processor  202  with one&#39;s complement adder  100 . As packets pass through device  200 , they are processed by logic circuits  204 ,  206 . As the data from the packets passes from logic circuit  204  to logic circuit  206 , it is read by checksum processor  202 . In some implementations, the tap for checksum processor  202  is before all other active processing in device  200 , in which case logic  204  would be replaced with a pass-though. However checksum processor  202  obtains the packet data, it processes the packet headers, as described above, using one&#39;s complement adder  100  to perform the one&#39;s complement addition. Checksum processor  202  outputs an error signal (“error” or “no error”) depending on the result of the addition. That error signal is used, among other uses, by logic circuit  206  to decide whether to drop a corrupted packet. 
     The above description is illustrative and not restrictive. Many variations of the invention will become apparent to those of skill in the art upon review of this disclosure. For example, the one&#39;s complement adder of the present invention could be used in any other circuit needing a one&#39;s complement adder calculation. Also, the examples above generally operate on two addends at a time, however one skilled in the art would, after reading this disclosure, be able to generalize to adders with more than two addends without undue experimentation. Furthermore, although a multiplexer is used to select among the results provided by the two&#39;s complement adders, other selector logic could be used in place of a multiplexer. The scope of the invention should, therefore, be determined not with reference to the above description, but instead should be determined with reference to the appended claims along with their full scope of equivalents.