Patent Publication Number: US-10777534-B2

Title: Three-dimensional stacking structure

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application is a divisional application of U.S. application Ser. No. 15/164,883, filed on May 26, 2016, now allowed. The entirety of the above-mentioned patent applications is hereby incorporated by reference herein and made a part of this specification. 
    
    
     BACKGROUND 
     High-density integration of diverse components such as microprocessors, memory, optoelectronics, mixed signal circuits and microelectromechanical systems (MEMS) is a challenging task. One possible solution for high-density integration is three-dimensional stacking, also called three-dimensional integration, of different microelectronic components at the wafer level. The three-dimensional stacking structures offer numerous advantages, including higher density of interconnects, decreased length of interconnects and packaging size or volume reduction. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. 
         FIG. 1  is a perspective view of a portion of an exemplary three-dimensional stacking structure in accordance with some embodiments of the present disclosure. 
         FIGS. 2A-2H  are the perspective views and cross-sectional views showing a three-dimensional stacking structure at various stages of the manufacturing method for forming the three-dimensional stacking structure according to some embodiments of the present disclosure. 
         FIG. 3  is an exemplary flow chart showing the process steps of the manufacturing method for forming a three-dimensional stacking structure in accordance with some embodiments of the present disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     The following disclosure provides many different embodiments or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. 
     Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature&#39;s relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. 
     It should be appreciated that the following embodiment(s) of the present disclosure provides applicable concepts that can be embodied in a wide variety of specific contexts. The specific embodiment(s) discussed herein is merely illustrative and is related to a three-dimensional (3D) integration structure or assembly, and does not limit the scope of the present disclosure. Embodiments of the present disclosure describe the exemplary manufacturing process of 3D stacking structures and the 3D stacking structures fabricated there-from. Certain embodiments of the present disclosure are related to the 3D stacking structures formed with wafer bonding structures and stacked wafers and/or dies. Other embodiments relate to 3D integration structures or assemblies including post-passivation interconnect (PPI) structures or interposers with other electrically connected components, including wafer-to-wafer assembled structures, die-to wafer assembled structures, package-on-package assembled structures, die-to-die assembled structures, and die-to-substrate assembled structures. The wafers or dies may include one or more types of integrated circuits or electrical components on a bulk semiconductor substrate or a silicon/germanium-on-insulator substrate. The embodiments are intended to provide further explanations but are not used to limit the scope of the present disclosure. 
     Other features and processes may also be included. For example, testing structures may be included to aid in the verification testing of the 3D packaging or 3DIC devices. The testing structures may include, for example, test pads formed in a redistribution layer or on a substrate that allows the testing of the 3D packaging or 3DIC, the use of probes and/or probe cards, and the like. The verification testing may be performed on intermediate structures as well as the final structure. Additionally, the structures and methods disclosed herein may be used in conjunction with testing methodologies that incorporate intermediate verification of known good dies to increase the yield and decrease costs. 
       FIG. 1  illustrates a cross-sectional view of a portion of an exemplary 3D stacking structure in accordance with some embodiments of the present disclosure. In  FIG. 1 , the 3D stacking structure  20 ′ comprises at least a first die  100 ′, a second die  200 ″ and a spacer protective structure  360 . In some embodiments, the first die  100 ′ includes a first bonding structure  120  comprising bonding elements  126  and contact pads  128 . The contact pads  128  are input/output (I/O) pads, bump pads or bond pads, for example. In some embodiments, the second die  200 ″ includes a second bonding structure  220  having bonding elements  226  and at least one seal ring structure  228 . In one embodiment, the seal ring structure  228  is arranged along a periphery of the second die  200 ″ and surrounds the bonding elements  226 . The second die  200 ″ is stacked on the first die  100 ′, and the second bonding structure  220  is hybrid-bonded with the first bonding structure  120 . In some embodiments, the spacer protective structure  360  is disposed on the first die  100 ′ and surrounds the second die  200 ″. In certain embodiments, the spacer protective structure  360  covers sidewalls  300   b  and the top surface  300   a  of the second die  200 ″. In one embodiment, the material of the spacer protective structure  360  includes a dielectric material of good gas barrier properties so that the spacer protective structure  360  protects the second die  200 ″ from the moisture. The 3D stacking structure  20 ′ further comprises an anti-bonding layer  140  disposed on the first die  100 ′ and located between the spacer protective structure  360  and the first die  100 ′. In one embodiment, the material of the anti-bonding layer  140  includes chromium or graphene. 
       FIGS. 2A-2H  illustrate the cross-sectional views of portions of a 3D stacking structure  20  at various stages of the manufacturing methods for forming the 3D stacking structure according to some embodiments of the present disclosure. In  FIG. 2A , in some embodiments, a first wafer  100  including semiconductor devices  104 , isolation structures  107  and metallization structures  108  formed in a semiconductor substrate  102  is provided. In some embodiments, the first wafer includes a plurality of first dies  100 ′. In certain embodiments, the semiconductor devices  104  are formed in the semiconductor wafer  100  during the front-end-of-line (FEOL) processes. In certain embodiments, the first wafer  100  is a semiconductor wafer made of silicon or other semiconductor materials, such as III-V semiconductor materials. In some embodiments, the semiconductor substrate  102  may include elementary semiconductor materials such as silicon or germanium, compound semiconductor materials such as silicon carbide, gallium arsenic, indium arsenide, or indium phosphide or alloy semiconductor materials such as silicon germanium, silicon germanium carbide, gallium arsenic phosphide, or gallium indium phosphide. In exemplary embodiments, the semiconductor device  104  embedded in an insulation layer  103  includes a gate structure  105  and active regions  106 , located between the isolation structures  107 . The semiconductor devices  104  shown in  FIG. 2A  are merely examples, and other devices may be formed in the first wafer  100 . In some embodiments, the semiconductor devices  104  are N-type metal-oxide semiconductor (NMOS) devices and/or P-type metal-oxide semiconductor (PMOS) devices. In some embodiments, the semiconductor devices  104  are transistors, memories or power devices, or other devices such as capacitors, resistors, diodes, photo-diodes, sensors or fuses. 
     As shown in  FIG. 2A , in certain embodiments, the metallization structures  108  are embedded within the insulation layer  103  and formed over the semiconductor devices  104 . In some embodiments, the insulation layer  103  includes one or more dielectric layers. In some embodiments, a material of the insulation layer  103  includes silicon oxide, a spin-on dielectric material, a low-k dielectric material or a combination thereof. The formation of the insulation layer  103  includes performing one or more processes by chemical vapor deposition (CVD) or by spin-on, for example. In some embodiments, the metallization structures  108  include interconnect structures, such as metal lines, via and contact plugs. In certain embodiments, the materials of the metallization structures  108  include aluminum (Al), aluminum alloy, copper (Cu), copper alloy, tungsten (W), or combinations thereof. In exemplary embodiments, the semiconductor devices  104  are electrically connected with the metallization structures  108  and some of the semiconductor devices  104  are electrically interconnected through the metallization structures  108 . The metallization structures  108  shown herein are merely for illustrative purposes, and the metallization structures  108  may include other configurations and may include one or more through vias and/or damascene structures. 
     As shown in  FIG. 2A , in some embodiments, a hybrid bonding structure  120  is formed over the insulation layer  103  and the metallization structures  108 . In exemplary embodiments, the hybrid bonding structure  120  includes conductive features  122  embedded in a dielectric material  124 . In some embodiments, the conductive features  122  include at least bonding elements  126  located within the bonding region  100 B of the first wafer  100  and contact pads  128  located within the non-bonding region  100 A of the first wafer  100 . The contact pads  128  are input/output (I/O) pads, bump pads or bond pads, for example. In exemplary embodiments, the non-bonding region  100 A is an I/O region of the first wafer  100 , and the contact pads  128  are I/O pads. Alternatively, in some embodiments, the non-bonding region  100 A is an I/O region of the first wafer  100 , and the contact pads  128  are bump pads. In one embodiment, the top surfaces  126   a  of the bonding elements  126  are exposed from the dielectric material  124 , for wafer bonding. In one embodiment, the contact pads  128  are embedded and covered by the dielectric material  124 . Although not expressly shown in  FIG. 2A , some of the conductive features  122  are electrically interconnected to one another and some of the conductive features  122  are electrically connected with the underlying metallization structures  108  and/or the semiconductor devices  104 . 
     In exemplary embodiments, the conductive features  122  are made of conductive materials, such as copper (Cu), copper alloys, aluminum (Al), aluminum alloys, nickel (Ni), solder materials or combinations thereof. In some embodiments, if the conductive material is copper or copper alloy, which is easy to diffuse, a diffusion barrier layer  127  is needed. In  FIG. 2A , in certain embodiments, the bonding element  126  is made of copper or copper alloys, and the diffusion barrier layer  127  is formed between the bonding element  126  and the dielectric material  124 . The material of the diffusion barrier layer  127  includes silicon nitride (SiN), silicon oxynitride (SiON), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), aluminum nitride (AlN) or cobalt alloys. In some embodiments, the conductive material of the bonding element  126  is copper, and the diffusion barrier layer  127  is made of Ti, TiN, Ta, TaN, Ta/TaN, CoP or CoW. 
     In some embodiments, the dielectric material  124  is made of silicon oxide, silicon nitride, benzocyclobutene (BCB), epoxy, polyimide (PT), or polybenzoxazole (PBO). In certain embodiments, the dielectric material  124  is made of silicon oxide or silicon nitride. In certain embodiments, the dielectric material  124  is made of benzocyclobutene (BCB) by spin coating. When a soft polymer material(s), such as BCB polymer, is used, the hybrid bonding structure can be more tolerant to the stress, thus enhancing the reliability of the 3D stacking structure. 
     As the devices in the vicinity of through-substrate vias (TSVs) often suffer from serious performance degradation due to the stress induced by the TSV, the hybrid bonding structure described in the above embodiments is not formed with the TSV, even though the hybrid bonding structure may be compatible with TSVs. 
       FIG. 2B  is a partial cross-sectional view of the 3D stacking structure at one of various stages of the manufacturing method. As shown in  FIG. 2B , in exemplary embodiments, the non-bonding regions  100 A of the first wafer  100  is patterned to form shallow openings  130 , and top surfaces  128   a  of the contact pads  128  are exposed by the openings  130 . In some embodiments, the bonding region(s)  100 B is covered by a mask pattern  132 , and using the mask pattern  132  as an etching mask, the non-bonding regions  100 A are patterned and etched to a depth enough to expose the contact pads  128 . In one embodiment, the patterning of the non-bonding regions  100 A and the formation of the shallow openings  130  include performing at least one anisotropic etching process. 
       FIG. 2C  is a partial cross-sectional view of the 3D stacking structure at one of various stages of the manufacturing method. As shown in  FIG. 2C , in exemplary embodiments, an anti-bonding layer  140  is formed within the openings  130  and fills up the openings  130 . In one embodiment, the anti-bonding layer  140  are least covers the contact pads  128  and may extend beyond the contact pads  128 . In some embodiments, the top surface  140   a  of the anti-bonding layer  140  levels with the top surface  120   a  of the hybrid bonding structure  120 . In one embodiment, the material of the anti-bonding layer  140  includes chromium or graphene. In some embodiment, the anti-bonding layer  140  functions to prevent bonding between the non-bonding regions  100 A of the first wafer  100  and another wafer or die thereon. In some embodiments, after forming the anti-bonding layer  140 , the mask pattern  132  ( FIG. 2B ) is removed and the top surface  120   a  of the hybrid bonding structure  120  (including the top surfaces  126   a  of the bonding elements  126 ) in the bonding region  100 B is exposed. In certain embodiments, a surface activation process is optionally performed to prepare the top surface  120   a  of the hybrid bonding structure  120  (including the top surfaces  126   a  of the bonding elements  126 ) ready for wafer bonding. 
       FIG. 2D  is a partial cross-sectional view of the 3D stacking structure at one of various stages of the manufacturing method. As shown in  FIG. 2D , a second wafer  200  is provided. In some embodiments, the second wafer is a semiconductor wafer, made of a semiconductor material similar to or different from that of the first wafer  100 . In alternative embodiments, the second wafer  200  may be regarded as one or more second dies  200 ′. The second wafer  200  includes semiconductor devices  204 , isolation structures  207  and metallization structures  208  formed in a semiconductor substrate  202 . In some embodiments, the semiconductor substrate  202  is similar to the semiconductor substrate  102 . In exemplary embodiments, the semiconductor device  204  embedded in an insulation layer  203  includes a gate structure  205  and active regions  206  located between the isolation structures  207 . The semiconductor devices  204  shown in  FIG. 2D  are merely examples, and semiconductor devices  204  may be similar to the semiconductor devices  104  or may be different types of semiconductor devices. 
     As shown in  FIG. 2D , the second wafer  200  further includes metallization structures  208  embedded in the insulation layer  203  and a hybrid bonding structure  220  over the insulation layer  203  and the metallization structures  208 . In some embodiments, the insulation layer  203  includes one or more dielectric layers. In some embodiments, a material of the insulation layer  203  includes silicon oxide, a spin-on dielectric material, a low-k dielectric material or a combination thereof. The formation of the insulation layer  103  includes performing one or more processes by CVD or by spin-on, for example. The material of the insulation layer  203  may be the same with or different from that of the insulation layer  103 . In some embodiments, the metallization structures  208  include interconnect structures, such as metal lines, via and contact plugs. In certain embodiments, the materials of the metallization structures  208  include aluminum, aluminum alloy, copper, copper alloy, tungsten, or combinations thereof. In exemplary embodiments, the semiconductor devices  204  are electrically connected with the metallization structures  208  and some of the semiconductor devices  204  are electrically interconnected through the metallization structures  208 . The configurations and arrangement of the metallization structures  208  are similar to or different from those of the metallization structures  108 , as the semiconductor devices  104  and  204  may be similar or different. The metallization structures  208  shown herein are merely for illustrative purposes and the metallization structures  208  may include other configurations and may include one or more through vias and/or damascene structures. 
     In  FIG. 2D , in some embodiments, the hybrid bonding structure  220  includes conductive features  222  embedded in a dielectric material  224 . In some embodiments, the conductive features  222  include at least bonding elements  226  and seal ring structure(s)  228  located within the bonding region(s)  200 B of the second wafer  200 . In certain embodiments, the seal ring structure(s)  228  is arranged along the periphery of the bonding region  200 B to surround the bonding region  200 B and between the bonding region  200 B and the non-bonding regions  200 A. In one embodiment, the seal ring structure  228  embedded within the dielectric material  224  of the hybrid bonding structure  220  includes a ring pattern surrounding the second bonding elements. The hybrid bonding structure  220  has no conductive features  222  arranged within the non-bonding region  200 A of the second wafer  200 . In exemplary embodiments, the bonding region  200 B is a device region and the non-bonding region(s)  200 A is a peripheral region. The conductive features  222  are made of conductive materials, such as Cu, copper alloy, Al, aluminum alloy, or combinations thereof. In some embodiments, the bonding element  226  is made of copper or copper alloys, and a diffusion barrier layer  227  is formed between the bonding element  226  and the dielectric material  224 . The material of the dielectric material  224  is similar to that of the dielectric material  124 . Alternatively, in other embodiments, the material of the dielectric material  224  may be different to that of the dielectric material  124 , as long as the dielectric materials  124 ,  224  can establish satisfactory bonding. 
     As shown in  FIG. 2D , in certain embodiments, the top surfaces  226   a  of the bonding elements  226  are exposed from the dielectric material  224 , for wafer bonding in the subsequent processes. In certain embodiments, a surface activation process is optionally performed to prepare the top surface  220   a  of the hybrid bonding structure  220  ready for wafer bonding. Although not expressly shown in  FIG. 2D , some of the conductive features  222  are electrically interconnected to one another and some of the conductive features  222  are electrically connected with the underlying metallization structures  208  and/or the semiconductor devices  204 . The configurations and arrangement of the conductive features  222  in the hybrid bonding structure  220  of the second wafer  200  are different from those of the conductive features  122  in the hybrid bonding structure  120  of the first wafer  100 . That is, the footprint of the first wafer  100  is different from the footprint of the second wafer  200 . 
     During the wafer on wafer bonding process, if the top wafer (or die) and the bottom wafer (or die) have to adopt the same footprint, the design flexibility is quite limited and the TSVs are often needed for bonding. Alternatively, as described in certain embodiments of the present disclosure, since the top wafer (or die) and the bottom wafer (or die) have different footprints, the design flexibility is improved and costly TSVs are unnecessary. 
       FIG. 2E  is a partial cross-sectional view of the 3D stacking structure  20  at one of various stages of the manufacturing method. As shown in  FIG. 2E , in some embodiments, the second wafer  200  is stacked over the first wafer  100 , and the top surfaces  220   a ,  120   a  (shown in  FIGS. 2C &amp; 2D ) of the hybrid bonding structures  220  and  120  are in direct contact with each other. In certain embodiments, the first and second wafers  100  and  200  are aligned and then stacked in a way that the hybrid bonding structure  220  of the second wafer  200  can be bonded, face-to-face, with the hybrid bonding structure  120  of the first wafer  100 . In some embodiments, the alignment of the first and second wafers  100  and  200  comprises using an optical alignment method with infrared (IR) light. In some embodiments, through the alignment, at least the bonding elements  226  (the top surface  226   a ) of the hybrid bonding structure  220  in the bonding region  200 B of the second wafer  200  are in contact with the bonding elements  126  (the top surface  126   a ) of the hybrid bonding structure  120  in the bonding region  100 B of the first wafer  100 , even though the footprint of the second wafer  200  is different to that of the first wafer  100 . In certain embodiments, through the alignment, the dielectric material  224  of the hybrid bonding structure  220  in the non-bonding regions  200 A of the second wafer  200  is in direct contact with the anti-bonding layer  140  arranged in the non-bonding regions  100 A of the first wafer  100 , However, the dielectric material  224  of the hybrid bonding structure  220  in the non-bonding regions  200 A of the second wafer  200  is not bonded to the anti-bonding layer  140 , as the anti-bonding layer  140  impart anti-bonding effects between the anti-bonding layer  140  and the dielectric material  224  of the hybrid bonding structure  220 . 
     Referring to  FIG. 2E , in certain embodiments, after the alignment and stacking, the first and second wafers  100  and  200  are bonded together by hybrid bonding technology. In some embodiments, the first and second wafers  100  and  200  are bonded by applying heat and/or force. In one embodiments, during the application of hybrid bonding technology, a low temperature heating process at a temperature of about 100° C. to about 200° C. is performed to heat and bond the dielectric materials  124  and  224  of the hybrid bonding structures  120 ,  220  and a high temperature heating process is performed at a temperature of about 200° C. to about 300° C. to heat the bonding elements  126 ,  226  of the hybrid bonding structures  120 ,  220  in the bonding regions  100 B,  200 B, such that the conductive bonding elements  126 ,  226  are bonded and the dielectric materials  124  and  224  are cured. In alternative embodiments, the first and second wafers  100 ,  200  may be bonded through dielectric bonding technology such as polymer bonding and oxide fusion bonding, metallic bonding technology such as thermo-compression bonding and eutectic bonding or the combinations thereof. 
     Referring to  FIG. 2E , in some embodiments, after the hybrid bonding of the first and second wafers  100 ,  200 , a thinning process is performed to a bottom side of the second wafer  200  to remove a portion of the substrate  202  without exposing the semiconductor devices  204 . In certain embodiments, the thinning process includes a grinding operation and/or a chemical mechanical polishing (CMP) process. In one embodiment, an isotropic etching process is optionally performed to remove the defects resultant from the previous processes. In alternative embodiments, if a die  200 ′, instead of the second wafer  200 , is provided for stacking, the thinning process may be performed before the bonding of the first and second wafers  100  and  200 . On the other hand, when the first and second wafer are bonded to form a more robust structure before the thinning process, a better thinning process is performed with higher reliability and the second wafer  200  may be thinned down to a smaller thickness (such as less than 2 microns), thus further reducing the height of the 3D stacking structure  20 . 
       FIG. 2F  is a partial cross-sectional view of the 3D stacking structure  20  at one of various stages of the manufacturing method. As shown in  FIG. 2F , in some embodiments, after the stacking and bonding of the first and second wafers  100 ,  200 , in some embodiments, a grooving process is performed to the second wafer  200  (or dies  200 ′) to form grooves  250  between the bonding region  200   b  and the non-bonding region(s)  200 A and along the periphery of the non-bonding regions  200 A. In certain embodiments, the grooving process includes performing one or more laser cutting processes. In one embodiment, the laser cutting process is performed several times with an infrared laser such as an Nd-YAG (neodymium-doped yttrium aluminum garnet) laser. In certain embodiments, the grooves  250  are formed along the predetermined inscribing lanes of the wafer with a depth d, which is deep enough so as to remove certain portions of the second wafer  200  in the subsequent processes. In alternative embodiments, the grooving process includes a mechanical cutting process, an inscribing process or an etching process. 
       FIG. 2G  is a partial cross-sectional view of the 3D stacking structure  20  at one of various stages of the manufacturing method. As shown in  FIG. 2G , in some embodiments, the non-bonding regions  200 A of the second wafer  200  (or dies  200 ′) are removed from the second wafer  200  along the grooves  250  by a compressing process performed to the second wafer  200  (shown in  FIG. 2F ). In certain embodiments, the compressing process includes a mechanical cleaving process, an ultrasonic cleaving process or other suitable stressing processes. Referring to  FIG. 2G , in certain embodiments, through the formation of the grooves  250  between the bonding region  200 B and the non-bonding region(s)  200 A and along the periphery of the non-bonding regions  200 A, the non-bonding regions  200 A of the second wafer  200  are effectively and precisely removed and the remained second wafer becomes the incised structure(s)  300  and the anti-bonding layer  140  overlying the contact pads  128  in the non-bonding regions  100 A is exposed. In addition, in some embodiments, the seal ring structures  228  embedded within the second wafer  200  are able to ensure the removal of the non-bonding regions  200 A without damaging the bonding elements  226  or the bonding regions  200 B of the second wafer  200 . In some embodiments, as shown in  FIG. 2G , a material layer  350  is formed over the incised structure  300 , at least covering the sidewalls  300   b  and top surface  300   a  of the incised structure  300  and the anti-bonding layer  140 . In exemplary embodiments, the material layer  350  includes a dielectric material of good gas barrier properties. In some embodiment, the dielectric material of good gas barrier properties includes silicon nitride, silicon oxynitride or other suitable dielectric materials, and the dielectric material of the gas barrier properties is formed by plasma enhanced chemical vapor deposition (PECVD). 
     In exemplary embodiments, the incised structure  300  refers to the remained second wafer  200  or the incised dies  200 ″ by removing (cutting off) the non-bonding regions  200 A of the second wafer  200  or the die  200 ′. In one embodiment, in  FIG. 2G , the seal ring structure  228  of the second bonding structure  220  is located along the periphery of the incised structure  300  (the incised second wafer) and surrounds the second bonding elements  226 . In certain embodiments, the size of the second wafer  200  is equivalent to or smaller than the size of the first wafer  100 , and after the compressing process removing the non-bonding regions  200 A, the incised structure  300  (the cut second wafer) becomes smaller in sizes than the first wafer  100 . Alternatively, when one or more dies  200 ′ (only one is shown) are stacked on the first wafer  100 , the size of the incised die(s)  200 ″ becomes smaller after the compressing process. 
       FIG. 2H  is a partial cross-sectional view of the 3D stacking structure  20  at one of various stages of the manufacturing method. As shown in  FIG. 2H , in some embodiments, the material layer  350  is etched by performing an etching back process to partially remove the material layer  350  over the incised structure  300  to form a spacer protective structure  360  around the incised structure  300  and remove the material layer  350  and the anti-bonding layer  140  above the contact pads  128  to expose the contact pads  128  for further connection. In some embodiments, the etching back process includes one or more isotropic etching processes and/or anisotropic etching processes. In certain embodiments, the etching rate and etching selectivity of the material layer  350  to the anti-bonding layer  140  or to the contact pads  128  are finely tuned so that the material layer  350  and the anti-bonding layer  140  on the contact pads  128  are removed together, leaving the top surfaces  128   a  of the contact pads  128  exposed. In exemplary embodiments, the spacer protective structure  360  is formed like a hat or a cap on the sidewalls  300   b  and on the top surface  300   a  of the incised structure  300 , protecting the incised structure  300  of the 3D stacking structure  20  from outside moisture or oxidation. In some embodiments, during the etching back process, a portion of the anti-bonding layer  140  under the spacer protective structure  360  is not removed and remained between the first wafer  100  and the spacer protective structure  360 . In  FIG. 2G , in one embodiment, the top surfaces  128   a  of the contact pads  128  are mostly exposed (i.e. not covered by the material layer  350  and the remained anti-bonding layer  140 ) and a portion of the anti-bonding layer  140  remains on the contact pads  128 . That is, the top surfaces  128   a  of the contact pads  128  are exposed from the first bonding structure  120  and the anti-bonding layer  140  located on the contact pads prevents bonding between the spacer protective structure  360  and the contact pads  128 . In some embodiments, a dicing process is subsequently performed to further dice the 3D stacking structure  20  into individual stacking structures  20 . 
     In alternative embodiments, the top surfaces  128   a  of the contact pads  128  are exposed from the first bonding structure  120  and the remained anti-bonding layer  140  is not in contact with the contact pads  128  (as shown in the individual 3D stacking structure  20 ′ in  FIG. 1 ) when a larger distance between the contact pads  128  and the incised structure  300  is kept. 
     In exemplary embodiments, as the material layer  350  and the anti-bonding layer  140  above the contact pads  128  are both removed during the etching back process, the contact pads  128  of the first wafer  100  are exposed and further connections structures such as pillars, bumps or solder balls may be formed thereon for external electrical connection. Alternatively, the 3D stacking structure  20  may be additional processed in the subsequent processes to be connected with further connection structures before dicing, and these subsequent processes may be modified based on the product design and will not be described in details herein. 
     In some embodiments described herein, the contact pads  128  of the first wafer  100  are allowed for bonding or for further connection by removing the non-bonding region(s)  200 A of the second wafer  200  above the contact pads  128  of the first wafer  100  and by removing the anti-bonding layer  140  on the contact pads  128  during the formation of the spacer protective structure  360 . 
     In some embodiments described herein, following the removal of the non-bonding region(s) of the top wafer or die, the contact pads such as bump pads or I/O pads in the bottom wafer or die are exposed so that bumps, balls or connection elements are subsequently formed thereon for electrical connection. By doing so, the footprints of the top wafer or die do not have to be the same as the footprints of the bottom wafer or die and no TSVs are required for connecting the contact pads. As described in certain embodiments, during the wafer on wafer bonding process, because the footprints of the top wafer (or die) are independent to the footprints of the bottom wafer (or die), the design flexibility is improved. Additionally, the spacer protective structure(s) formed around the incised structure (or cut dies) shields off the outside moisture and protects the open edges of the incised structure of the 3D stacking structure, leading to better reliability and a more robust structure. 
       FIG. 3  is an exemplary flow chart showing some of the process steps of the manufacturing method for a 3D stacking structure in accordance with some embodiments of the present disclosure. In Step  300 , a first wafer with a first bonding structure is provided, and the first wafer has at least one first bonding region and at least one first non-bonding region. In Step  302 , an anti-bonding layer is formed in the non-bonding region of the first wafer and covers top surfaces of contact pads of the first bonding structure. In Step  304 , a second wafer with a second bonding structure is provided, and the second wafer has at least one second bonding region and at least one second non-bonding region. In Step  306 , the second wafer is stacked on the first wafer. In Step  308 , the second bonding structure of the second wafer is bonded with the first bonding structure of the first wafer. In Step  310 , grooves are formed in the second wafer between the second bonding region and the second non-bonding region and along a periphery of the second non-bonding region. In Step  312 , the second non-bonding region of the second wafer is removed and the anti-bonding layer in the first non-bonding region of the first wafer is exposed. In Step  314 , a material layer is formed covering the remained second wafer and the anti-bonding layer in the at least one first non-bonding region of the first wafer. In Step  316 , the material layer is etched to form a spacer protective structure surrounding the remained second wafer and the anti-bonding layer is removed to expose the top surfaces of the contact pads in the at least one first non-bonding region of the first wafer. In some embodiments, a dicing process is performed to the 3D stacking structure to form the individual stacking structures. 
     Although the steps of the method are illustrated and described as a series of acts or events, it will be appreciated that the illustrated ordering of such acts or events are not to be interpreted in a limiting sense. In addition, not all illustrated process or steps are required to implement one or more embodiments of the present disclosure. 
     In the above embodiments, as the anti-bonding layer is formed over the contact pads of the first wafer, the non-bonding region of the second wafer is removed and easily detaching from the first wafer. In some embodiments, the anti-bonding layer protects the contact pads, and during etching back of the material layer, portions of the anti-bonding layer and the material layer are removed together to form the spacer protective structure and to expose the contact pads. Accordingly, the stacking structure with the spacer protective structure shielding the top wafer or dies can be more robust, thus leading to improved electrical performance and better reliability of the semiconductor device. 
     In some embodiments of the present disclosure, a stacking structure comprising a first die, a second die, a spacer protective structure and an anti-bonding layer is provided. The first die has a first bonding structure and the first bonding structure comprises contact pads. The second die has a second bonding structure. The second die is stacked on the first die, and the second bonding structure is bonded with the first bonding structure. The spacer protective structure is disposed over the first die and surrounds the second die. The spacer protective structure covers sidewalls of the second die. The anti-bonding layer is disposed over the first die and located between the spacer protective structure and the first die. 
     In some embodiments of the present disclosure, a method for forming a stacking structure is described. A first wafer with a first bonding structure is provided. The first wafer has at least one first bonding region and at least one first non-bonding region. An anti-bonding layer is formed in the at least one first non-bonding region of the first wafer and covers top surfaces of contact pads of the first bonding structure. A second wafer with a second bonding structure is provided. The second wafer has at least one second bonding region and at least one second non-bonding region. The second bonding structure of the second wafer is bonded with the first bonding structure of the first wafer. Grooves are formed in the second wafer between the at least one second bonding region and the at least one second non-bonding region. The at least one second non-bonding region of the second wafer is removed and the anti-bonding layer in the at least one first non-bonding region of the first wafer is exposed. A material layer is formed covering the remained second wafer and the anti-bonding layer in the at least one first non-bonding region of the first wafer. The material layer is etched to form a spacer protective structure surrounding the remained second wafer and at least a portion of the anti-bonding layer is removed to expose the top surfaces of the contact pads. 
     In some embodiments of the present disclosure, a method for forming a stacking structure is described. A first wafer with a first bonding structure is provided. The first wafer has at least one first bonding region and at least one first non-bonding region. The at least one first non-bonding region of the first wafer is etched to form openings exposing contact pads of the first bonding structure. An anti-bonding layer is formed within the openings in the at least one first non-bonding region of the first wafer to cover top surfaces of the contact pads of the first bonding structure. A second wafer with a second bonding structure is provided. The second wafer has at least one second bonding region and at least one second non-bonding region. The second wafer is bonded onto the first wafer. The at least one second non-bonding region of the second wafer is removed to expose the anti-bonding layer on the at least one first non-bonding region of the first wafer. A material layer covering the remained second wafer and the anti-bonding layer on the at least one first non-bonding region of the first wafer is formed. The material layer is etched to form a spacer protective structure surrounding the remained second wafer and remove at least a portion of the anti-bonding layer to expose the top surfaces of the contact pads in the at least one first non-bonding region of the first wafer. 
     The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.