Patent Publication Number: US-10775828-B1

Title: Reference voltage generation circuit insensitive to element mismatch

Description:
BACKGROUND OF THE INVENTION 
     Field of the Invention 
     The invention relates to a reference voltage generation circuit, and, more particularly, to a reference voltage generation circuit which is insensitive to element mismatch. 
     Description of the Related Art 
     Integrated circuits often require a reference voltage which remains stable under PVT (process, voltage, temperature) variations. A bandgap reference circuit is provided to generate a reference voltage which is not varied with the temperature variation. However, a reference voltage generated by a bandgap reference circuit may vary due to mismatch between elements induced by process variations, such as mismatch between metal-oxide-semiconductor (MOS) transistors of a current mirror circuit within the bandgap reference circuit. Thus, it is desired to provide a bandgap reference circuit which is insensitive to the element mismatch. 
     BRIEF SUMMARY OF THE INVENTION 
     An exemplary embodiment of a reference voltage generation circuit for generating an output voltage is provided. The reference voltage generation circuit comprises a bandgap reference circuit and a voltage adjustment circuit. The bandgap reference circuit generates the output voltage at an output node and a reference voltage. The voltage adjustment circuit is coupled to the bandgap reference circuit. The voltage adjustment circuit receives the output voltage and the reference voltage, compares the output voltage with the reference voltage to generate a comparison result, and adjusts the output voltage according to the comparison result. 
     Anther exemplary embodiment of a reference voltage generation circuit is provided for generating an output voltage at an output node. The reference voltage generation circuit comprises a first bipolar transistor, a second bipolar transistor, a first resistor, a second resistor, a third resistor, a first operational amplifier, and a voltage adjustment circuit. The first bipolar transistor has a base coupled to a ground terminal, a collector coupled to the ground terminal, and an emitter coupled to a first node. The second bipolar transistor has a base coupled to the ground terminal, a collector coupled to the ground terminal, and an emitter coupled to a second node. The first resistor is coupled between the second node and a third node. The second resistor is coupled to the output node and the first node. The third resistor is coupled to a reference node and the third node. The first operational amplifier has a non-inverting input terminal coupled to the third node, an inverting input terminal coupled to the first node, and an output terminal. The first current mirror circuit is coupled to a voltage source and further coupled to the output node and the reference node. The voltage adjustment circuit is coupled to the output node and the reference node to receive the output voltage and a reference voltage respectively. The voltage adjustment circuit compares the output voltage with the reference voltage to generate a comparison result and adjusts the output voltage according to the comparison result. 
     Another exemplary embodiment of a reference voltage generation circuit is provided for generating an output voltage at an output node. The reference voltage generation circuit is provided comprises a first bipolar transistor, a second bipolar transistor, a first resistor, a second resistor, a third resistor, an operational amplifier, a fourth resistor, a fifth resistor, a sixth resistor, a current mirror circuit, a first voltage adjustment circuit, and a second voltage adjustment circuit. The first bipolar transistor has a base coupled to a ground terminal, a collector coupled to the ground terminal, and an emitter coupled to a first node. The second bipolar transistor has a base coupled to the ground terminal, a collector coupled to the ground terminal, and an emitter coupled to a second node. The first resistor is coupled between the second node and a third node. The second resistor is coupled to a first reference node and the first node. The third resistor is coupled to a second reference node and the third node. The operational amplifier has a non-inverting input terminal coupled to the third node, an inverting input terminal coupled to the first node, and an output terminal. The fourth resistor is coupled between the third node and the ground terminal. The fifth resistor is coupled between a third reference node and the output node. The sixth resistor is coupled between the output node and the ground terminal. The current mirror circuit is coupled to a voltage source and further coupled to the first, second, and third reference nodes. The first voltage adjustment circuit is coupled to the first reference node and the second reference node to receive a first reference voltage and a second reference voltage respectively. The first voltage adjustment circuit compares the first reference voltage with the second reference voltage to generate a first comparison result and adjusts the first reference voltage according to the first comparison result. The second voltage adjustment circuit is coupled to the second reference node and the third reference node to receive the second reference voltage and a third reference voltage respectively. The second voltage adjustment circuit compares the second reference with the third reference voltage to generate a second comparison result and adjusts the output voltage according to the second comparison result. 
     A detailed description is given in the following embodiments with reference to the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein: 
         FIG. 1  shows an exemplary embodiment of a reference voltage generation circuit; 
         FIG. 2  shows another exemplary embodiment of a reference voltage generation circuit; 
         FIG. 3  shows another exemplary embodiment of a reference voltage generation circuit; 
         FIG. 4  shows another exemplary embodiment of a reference voltage generation circuit. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims. 
       FIG. 1  shows an exemplary embodiment of a reference voltage generation circuit. Referring to  FIG. 1 , a reference voltage generation circuit  1  comprises a bandgap reference circuit  10  and a voltage adjustment circuit  11 . The bandgap reference circuit  10  operates to generate an output voltage Vo which does not vary with temperature variation and serves as a reference voltage for integrated circuits (not shown) coupled to the reference voltage generation circuit  1 . In ideal cases, the output voltage Vo should be equal to a predetermined value. However, in cases where mismatch between two elements, which are used to generate the output voltage Vo and the reference voltage Vref 10  respectively, is occurred due to process variations, the output voltage Vo varies to be larger or less than the predetermined value when there is no compensation or adjustment operation. According to the embodiment, the bandgap reference circuit  10  further operates to generate a reference voltage Vref 10  which also does not vary with temperature variations. The voltage adjustment circuit  11  receives the output voltage Vo and the reference voltage Vref 10  and compares the output voltage Vo with the reference voltage Vref 10 . The voltage adjustment circuit  11  adjusts the output voltage Vo according to the comparison result, so that the output voltage Vo is eventually equal to the predetermined value. Thus, through the comparison and adjustment operations, the output voltage Vo is maintained at the predetermined value, that is, the output voltage is not disadvantageously affected by the element mismatch. 
     Referring to  FIG. 2 , in an exemplary embodiment of the reference voltage generation circuit  1 , the bandgap reference circuit  10  comprises a pair of bipolar transistors Q 1  and Q 2 , resistors R 1 -R 3 , an operational amplifier  20 , and a current mirror circuit  21 . The base of the bipolar transistor Q 1  is coupled to a ground terminal GND, the collector thereof is coupled to the ground terminal GND, and the emitter thereof is coupled to a node N 21 . The base of the bipolar transistor Q 2  is coupled to the ground terminal GND, the collector thereof is coupled to the ground terminal GND, and the emitter thereof is coupled to a node N 20 . In the embodiment of  FIG. 2 , the size of the bipolar transistor Q 2  is n times the size A of the bipolar transistor Q 1  (the size of the bipolar transistor Q 2  is represented by n×A). In other words, the size ratio of the bipolar transistor Q 2  and the bipolar transistor Q 1  is equal to n, and the size ratio is represented by 
                 Q   ⁢   2       Q   ⁢   1       =         n   ×   A     A     =   n           
in  FIG. 2 . In an example, n is a positive integer, for example, n is equal to 8 (n=8). The resistor R 1  is coupled between a node N 22  and the node N 20 . The resistor R 2  is coupled between an output node Nout and the node N 21 . The resistor R 3  is coupled to a reference node Nref 10  and the node N 22 . In the embodiment, the resistance value of the resistor R 2  is equal to the resistance value of the resistor R 3 . The non-inverting input terminal (+) of the operational amplifier  20  is coupled to the node N 22 , and the inverting input terminal (−) thereof is coupled to the node N 21 , and an output terminal thereof is coupled to the current mirror circuit  21  at a node N 23 . In the embodiment, the current mirror circuit  21  comprises metal-oxide-semiconductor (MOS) transistors M 1  and M 2 . In the embodiment, the MOS transistors M 1  and M 2  are implemented by P-type MOS (PMOS) transistors. The gate of the PMOS transistor M 1  is coupled to the node N 23 , the source thereof is coupled to a voltage source VS, and the drain thereof is coupled to the output node Nout. The gate of the PMOS transistor M 2  is coupled to the node N 23 , the source thereof is coupled to the voltage source VS, and the drain thereof is coupled to the reference node Nref 10 . According to the structure of the current mirror circuit  21 , the PMOS transistors M 1  and M 2  are controlled by the output at the output terminal of the operational amplifier  20 . In the embodiment, the ratio of width to length of the PMOS transistor M 1  is m times the ratio (W/L) of width to length of the PMOS transistor M 2  (the ratio of width to length of the PMOS transistor M 1  is represented by m(W/L)).
 
     When the reference voltage generation circuit  1  receives a supply voltage VDD through the voltage source VS, the reference voltage generation circuit  1  operates. Based on the operation of the current mirror circuit  21  and the characteristic of the operational amplifier  20 , currents I 1  and I 2  following respectively through the resistors R 2  and R 3  are generated, and the output voltage Vo and the reference voltage Vref 10  are generated at the output node Nout and the reference node Nref 10  respectively. Based on the operation of the reference voltage generation circuit  1 , the current I 2  is represented as: 
                     I   ⁢           ⁢   2     =           V   ⁢           ⁢   1     -     V   ⁢           ⁢   3         R   ⁢   1       =         Δ   ⁢           ⁢     V     B   ⁢   E           R   ⁢   1       =         V   T       R   ⁢   1       ⁢     ln   ⁡     (   nm   )                     Equation   ⁢           ⁢     (   1   )                 
wherein, V 1  represents the voltage at the node N 21 , V 3  represents the voltage at the node N 20 , ΔV BE  represents the difference between the base-emitter voltages of the bipolar transistors Q 1  and Q 2 , and V T  represents the threshold voltage of the bipolar transistors. The current I 2  is proportional to absolute temperature (i.e. PTAT), that is, the current I 2  has a positive temperature coefficient. Since the ratio of width to length of the PMOS transistor M 1  is m times the ratio (W/L) of width to length of the PMOS transistor M 2 , the current I 1  is m times the current I 2 , represented as:
 
 I 1= m×I 2  Equation (2)
 
The current I 1  is also proportional to absolute temperature. Then, the output voltage Vo is represented as:
 
                   Vo   =         V     B   ⁢   E   ⁢   1       +     I   ⁢           ⁢   1   ×   R   ⁢           ⁢   2       =       V     B   ⁢   E   ⁢   1       +     m   ×       V   T       R   ⁢   1       ⁢     ln   ⁡     (   nm   )       ×   R   ⁢           ⁢   2                 Equation   ⁢           ⁢     (   3   )                 
wherein, V BE1  represents the base-emitter voltage of the bipolar transistor Q 1 , which is inversely proportional to absolute temperature (i.e. IPTAT). That is, the base-emitter voltage V BE1  has a negative temperature coefficient. Due to the PTAT current I 1  and the IPTAT base-emitter voltage V BE1 , the output voltage Vo has a zero temperature coefficient.
 
     In cases (ideal cases) where there is no mismatch between the PMOS transistors M 1  and M 2  (that is, m=1), Equation (3) is re-written as: 
                   Vo   =         V     B   ⁢   E   ⁢   1       +     I   ⁢           ⁢   1   ×   R   ⁢           ⁢   2       =       V     B   ⁢   E   ⁢   1       +         V   T       R   ⁢   1       ⁢     ln   ⁡     (   n   )       ×   R   ⁢           ⁢   2                 Equation   ⁢           ⁢     (   4   )                 
In these ideal cases, the current I 1  is equal to the current I 2 , and, thus, both of the output voltage Vo and the reference voltage Vref 10  are equal to a predetermined value, such as 1.25 volts (V). However, in some situations, mismatch may occur between the PMOS transistors M 1  and M 2  due to process variations, which means that m is larger than or less than 1 (m&gt;1 or m&lt;1). In these cases, the current I 1  becomes not equal to the current I 2 , so that the output voltage Vo is not equal to the reference voltage Vref 10 , and the output voltage Vo is also not equal to the predetermined value.
 
     According to the embodiment, the voltage adjustment circuit  11  is provided to compensate for the mismatch between the PMOS transistors M 1  and M 2 . Referring to  FIG. 2 , the voltage adjustment circuit  11  comprises a comparator  22  and a path control circuit  23 . The non-inverting input terminal (+) of the comparator  22  receives the output voltage Vo and the inverting input terminal (−) thereof receives the reference voltage Vref 10 . During the operation of the reference voltage generation circuit  1 , the comparator  22  compares the output voltage Vo with the reference voltage Vref 10  and generates a control signal S 22  at its output terminal according to the comparison result of the above comparison. The path control circuit  23  comprises an inverter composed of a PMOS transistor Ma and an N-type MOS (NMOS) transistor Mb. The gate of the PMOS transistor Ma is coupled to the output terminal of the comparator  22  to receive the control signal S 22 , the source thereof is coupled to the voltage source VS to receive the supply voltage VDD, and the drain thereof is coupled to the output node Nout. The gate of the NMOS transistor Mb is coupled to the output terminal of the comparator  22  to receive the control signal S 22 , the drain thereof is coupled to the output node Nout, and the source thereof is coupled to the ground terminal GND. 
     When the output voltage Vo is less than the reference voltage Vref 10  due to the mismatch between the PMOS transistors M 1  and M 2  (in the cases where m&lt;1), the comparator  22  generates the control signal S 22  with a low voltage level to turn on the PMOS transistor Ma, so that, there is a charge path P 20  formed between the voltage source VS and the output node Nout. Thus, the output node Nout is charged by the charge path P 20  to increase the current I 1 . Due to the virtual ground of the operational amplifier  20 , the voltage V 1  at the inverting input terminal is equal to the voltage V 2  at the non-inverting input terminal. Based on the equal voltages V 1  and V 2 , the resistors R 2  and R 3  with the same resistance value, and the operation of the current mirror circuit  21 , the current I 1  is increased and eventually equal to the current I 2 , which makes the output voltage Vo equal to the reference voltage Vref 10 . Thus, the output voltage Vo is eventually adjusted to the predetermined value. 
     When the output voltage Vo is larger than the reference voltage Vref 10  due to the mismatch between the PMOS transistors M 1  and M 2  (in the cases where m&gt;1), the comparator  22  generates the control signal S 22  with a high voltage level to turn on the NMOS transistor Mb, so that, there is a discharge path P 21  formed between the output node Nout and the ground terminal GND. Thus, the output node Nout is discharged by the discharge path P 21  to decrease the current I 1 . Based on the equal voltages V 1  and V 2 , the resistors R 2  and R 3  with the same resistance value, and the operation of the current mirror circuit  21 , the current I 1  is decreased and eventually equal to the current I 2 , which makes the output voltage Vo equal to the reference voltage Vref 10 . Thus, the output voltage Vo is eventually adjusted to the predetermined value. 
     According to the above embodiment, through the disposition of the resistors R 2  and R 3  and the operation of the voltage adjustment circuit  11 , the output voltage Vo can be adjusted for compensating for the mismatch between the PMOS transistors M 1  and M 2 , such that the reference voltage generation circuit  1  is insensitive to the mismatch induced by the process variations. 
     According to the structure of the reference voltage generation circuit  1 , there is an operational amplifier  20 . Usually, the offset voltage of an operational amplifier is in a range 1-10 mV. When the operational amplifier  20  has an offset voltage, the voltage output Vo may have up to 20% error. In order to eliminate the effect of the offset voltage, the reference voltage generation circuit  1  further comprises an offset current generation circuit  12 , as shown in  FIG. 3 . In the following paragraphs, to discuss the operation of the offset current generation circuit  12  and the elimination of the offset voltage clearly, it is assumed that m is equal to 1 (m=1), and the operation related to the above adjustment of the output voltage Vo is omitted. Note that, in the embodiment of  FIG. 3 , the size of the bipolar transistor Q 2  is 2×n times the size A of the bipolar transistor Q 1  (the size of the bipolar transistor Q 2  is represented by 2×n×A), that is, the size ratio of the bipolar transistors Q 2  and Q 1  is equal to 2×n, and the size ratio is represented by 
                 Q   ⁢   2       Q   ⁢   1       =         2   ×   n   ×   A     A     =     2   ×   n             
in  FIG. 3 . Moreover, the offset voltage of the operational amplifier  20  is represented by a voltage Vos at the non-inverting input terminal of the operational amplifier  20 .
 
     Referring to  FIG. 3 , the offset current generation circuit  12  comprises a pair of bipolar transistors Q 1   a  and Q 2   a , a resistor R 1   a , an operational amplifier  30 , and a current mirror circuit  31  composed of MOS transistors M 1   a -M 4   a . The base of the bipolar transistor Q 1   a  is coupled to the ground terminal GND, the collector thereof is coupled to the ground terminal GND, and the emitter thereof is coupled to a node N 31 . The base of the bipolar transistor Q 2   a  is coupled to the ground terminal GND, the collector thereof is coupled to the ground terminal GND, and the emitter thereof is coupled to a node N 30 . In the embodiment of  FIG. 3 , the size of the bipolar transistor Q 1   a  is equal to the size A of the bipolar transistor Q 1 , and the size of the bipolar transistor Q 2   a  is twice the size of the bipolar transistor Q 1   a  (that is, the size of the bipolar transistor Q 2   a  is equal to twice the size A of the bipolar transistor Q 1 , represented by 2×A). Thus, the size ratio of the bipolar transistor Q 2   a  and the bipolar transistor Q 1   a  is equal to 2 and is represented by 
                 Q   ⁢   2   ⁢   a       Q   ⁢   1   ⁢   a       =         2   ×   A     A     =   2           
in  FIG. 3 . In other words, the size of the bipolar transistor Q 2  is n times the size of the bipolar transistor Q 2   a . The size ratio of the bipolar transistor Q 2   a  and the bipolar transistor Q 1  is equal to n, and the size ratio is represented by
 
                 Q   ⁢   2       Q   ⁢   2   ⁢   a       =         2   ×   n   ×   A       2   ×   A       =   n           
in  FIG. 3 . The resistor R 1   a  is coupled between a node N 32  and the node N 30 . In the embodiment, the resistance value of the resistor R 1   a  is equal to the resistance value of the resistor R 1 . The non-inverting input terminal (+) of the operational amplifier  30  is coupled to the node N 32  and the inverting input terminal (−) thereof is coupled to the node N 31 . As shown in  FIG. 3 , the offset voltage of the operational amplifier  30  is represented by a voltage Vos at the non-inverting input terminal of the operational amplifier  30 . In the embodiment, the MOS transistors M 1   a -M 4   a  of the current mirror circuit are implemented by PMOS transistors. The gate of the PMOS transistor M 1   a  is coupled to the output terminal of the operational amplifier  30 , the source thereof is coupled to the voltage source VS, and the drain thereof is coupled to the node N 31 . The gate of the PMOS transistor M 2   a  is coupled to the output terminal of the operational amplifier  30 , the source thereof is coupled to the voltage source VS, and the drain thereof is coupled to the node N 32 . The gate of the PMOS transistor M 3   a  is coupled to the output terminal of the operational amplifier  30 , the source thereof is coupled to the voltage source VS, and the drain thereof is coupled to the node N 21 . The gate of the PMOS transistor M 4   a  is coupled to the output terminal of the operational amplifier  30 , the source thereof is coupled to the voltage source VS, and the drain thereof is coupled to the node N 22 . According to the structure of the current mirror circuit, the PMOS transistors M 1   a -M 4   a  are controlled by the output at the output terminal of the operational amplifier  30 .
 
     In the cases where the offset voltages of the operational amplifier  20  is considered, since m is equal to 1, the current I 3  is equal to the current through the resistor R 1 , and the current I 3  is represented as: 
     
       
         
           
             
               
                 
                   
                     I 
                     ⁢ 
                     
                         
                     
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                     3 
                   
                   = 
                   
                     
                       [ 
                       
                         
                           
                             V 
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                               ( 
                               
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                   Equation 
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   
                     ( 
                     5 
                     ) 
                   
                 
               
             
           
         
       
     
     Through the operation of the current mirror circuit of the offset current generation circuit  12 , the currents I 1   a , I 2   a , I 3   a , and I 4   a  are equal. Thus, when the offset voltages of the operational amplifier  30  is considered, the current I 3   a  is represented as: 
     
       
         
           
             
               
                 
                   
                     I 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     3 
                     ⁢ 
                     a 
                   
                   = 
                   
                     
                       [ 
                       
                         
                           
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                       ] 
                     
                     × 
                     
                       1 
                       
                         R 
                         
                           1 
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                           a 
                         
                       
                     
                   
                 
               
               
                 
                   Equation 
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   
                     ( 
                     6 
                     ) 
                   
                 
               
             
           
         
       
     
     Referring to  FIG. 3 , the current I 1  is represented as:
 
 I 1= I 3− I 3 a   Equation (7).
 
     Since the resistance value of the resistor R 1   a  is equal to the resistance value of the resistor R 1 , Equation (7) is re-written, based on Equation (5)˜Equation (7), as: 
     
       
         
           
             
               
                 
                   
                     I 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     1 
                   
                   = 
                   
                     
                       V 
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                         ( 
                         n 
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                       1 
                       
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                   Equation 
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   
                     ( 
                     8 
                     ) 
                   
                 
               
             
           
         
       
     
     According to the current I 4  and the resistor R 2 , the output voltage Vo is represented as: 
     
       
         
           
             
               
                 
                   Vo 
                   = 
                   
                     
                       
                         V 
                         
                           B 
                           ⁢ 
                           E 
                           ⁢ 
                           1 
                         
                       
                       + 
                       
                         I 
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                         ⁢ 
                         2 
                       
                     
                     = 
                     
                       
                         V 
                         
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                           E 
                           ⁢ 
                           1 
                         
                       
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                           ( 
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                         2 
                       
                     
                   
                 
               
               
                 
                   Equation 
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   
                     ( 
                     9 
                     ) 
                   
                 
               
             
           
         
       
     
     It can be found that Equation (9) is the same as Equation (4), which means that the offset voltage Vos of the operational amplifier  20  is cancelled through the generation of the current I 3   a  (offset current). According to the embodiment of  FIG. 3 , through the operations of the voltage adjustment circuit  11  and the offset current generation circuit  12 , the mismatch between the PMOS transistors M 1  and M 2  is compensated for, and the offset voltage Vos of the operational amplifier  20  is eliminated, which enhance the stability of the output voltage Vo. 
     In the above embodiments, the reference voltage generation circuit  1  generates the output voltage Vo which is larger than 1V, such as 1.25V. In some applications, a stable reference voltage which is less than 1V is required. Thus, according to other embodiments, a reference voltage generation circuit is provided to generate an output voltage which is less than 1V, such as 0.5V. Referring to  FIG. 4 , a reference voltage generation circuit  1 ′ comprises a bandgap reference circuit  10 ′, a voltage adjustment circuit  11 , and a voltage adjustment circuit  13 . The bandgap reference circuit  10 ′ comprises a pair of bipolar transistors Q 1  and Q 2 , resistors R 1 ˜R 4 , Rb and Ro, an operational amplifier  20 , and a current mirror circuit  21 ′, and the current mirror circuit  21 ′ comprises PMOS transistors M 1 ˜M 3 . Referring to  FIGS. 2 and 4 , the connections of the bipolar transistors Q 1  and Q 2 , the resistors R 1 ˜R 3 , the operational amplifier  20 , and the PMOS transistors M 1  and M 2  in the embodiment of  FIG. 4  are similar to those in the embodiment of  FIG. 2 , and, thus, the description related to the connections of these elements is omitted here. Note that, in  FIG. 4 , the joint node between the PMOS transistor M 1  and the resistor R 2  is represented as Nref 40  instead of the node Nout in  FIG. 2 , and the voltage at the joint node therebetween is referred to as a reference voltage Vref 40  instead of the output voltage Vo in  FIG. 2 . Moreover, the structure of the voltage adjustment circuit  11  in the embodiment of  FIG. 4  is similar to that in the embodiment of  FIG. 2 , and, thus, the related description is also omitted. In the following, the connections of the elements not shown in  FIG. 2  will be described. 
     Referring to  FIG. 4 , the resistor Rb is coupled between the node N 22  and the ground terminal GND. The resistor Ro is coupled to an output node Nout and the ground terminal GND. The resistor R 4  is coupled between a reference node Nref 41  and the output node Nout. In the embodiment, the resistance value of the resistor R 4  is equal to the resistance values of the resistors R 2  and R 3 . The gate of the PMOS transistor M 3  is coupled to the node N 23 , the source thereof is coupled to the voltage source VS, and the drain thereof is coupled to the reference node Nref 41 . 
     In the embodiment of  FIG. 4 , the operations of the bipolar transistors Q 1  and Q 2 , the resistors R 1 ˜R 3 , the operational amplifier  20 , and the PMOS transistors M 1  and M 2  are the same as those in the embodiment of  FIG. 2 , and the related description is omitted here. Based on the operations of the bipolar transistors Q 1  and Q 2 , the resistors R 1 ˜R 3 , the operational amplifier  20 , and the PMOS transistors M 1  and M 2 , a current Ib flowing through the resistor Rb is generated and represented as: 
                   Ib   =         V   ⁢           ⁢   2     Rb     =       V   ⁢           ⁢   1     Rb               Equation   ⁢           ⁢     (   10   )                 
wherein, since V 1  has a negative temperature coefficient, the current Ib also has a negative temperature coefficient. In the embodiment, the current I 2  is represented as:
 
 I 2= I 4+ Ib   Equation (11)
 
wherein, the current I 4  follows through the resistor R 1  and has a positive temperature coefficient. Thus, in the embodiment, the current I 2  has a zero temperature coefficient. Through the current mirror operation of the PMOS transistors M 1  and M 3  and the voltage division of the resistors R 4  and Ro, the output voltage Vo is generated at the output node Nout.
 
     In ideal cases, there is no mismatch between the PMOS transistors M 1  and M 2  (that is, m=1) and between the PMOS transistors M 2  and M 3 . However, in some situations, mismatch may occur between the PMOS transistors M 1  and M 2  (m&gt;1 or m&lt;1), and mismatch may occur between the PMOS transistors M 2  and M 3 , which causes that the output voltage Vo is not equal to a predetermined value, such as 0.5V. As described above, the mismatch between the PMOS transistors M 1  and M 2  can be compensated for through the operation of the voltage adjustment circuit  11 . In the embodiment, the reference voltage generation circuit  1 ′ further comprises the voltage adjustment circuit  13  to compensate for the mismatch between the PMOS transistors M 2  and M 3 . Referring to  FIG. 4 , the voltage adjustment circuit  13  comprises a comparator  40  and a path control circuit  41 . The non-inverting input terminal (+) of the comparator  40  receives the reference voltage Vref 41  and the inverting input terminal (−) thereof receives the reference voltage Vref 10 . During the operation of the reference voltage generation circuit  1 ′, the comparator  40  compares the reference voltage Vref 41  with the reference voltage Vref 10  and generates a control signal S 40  at its output terminal according to the comparison result of the above comparison. The path control circuit  41  comprises an inverter composed of a PMOS transistor Mc and an NMOS transistor Md. The gate of the PMOS transistor Mc is coupled to the output terminal of the comparator  40  to receive the control signal S 40 , the source thereof is coupled to the voltage source VS to receive the supply voltage VDD, and the drain thereof is coupled to the output node Nout. The gate of the NMOS transistor Md is coupled to the output terminal of the comparator  40  to receive the control signal S 40 , the drain thereof is coupled to the output node Nout, and the source thereof is coupled to the ground terminal GND. 
     When the reference voltage Vref 41  is less than the reference voltage Vref 10  due to the mismatch between the MOS transistors M 2  and M 3 , the comparator  40  generates the control signal S 40  with a low voltage level to turn on the PMOS transistor Mc, so that, there is a charge path P 40  formed between the voltage source VS and the output node Nout. Thus, the reference node Nref 41  is charged by the charge path P 40  to increase the current Io. Based on the resistors R 3  and R 4  with the same resistance value and the operation of the current mirror circuit  21 ′, the current Io is increased and eventually equal to the current I 2 , which makes the reference voltage Vref 41  equal to the reference voltage Vref 10 . Through the voltage division, the output voltage Vo is eventually equal to the predetermined value with the increment of the current Io. 
     When the reference voltage Vref 41  is larger than the reference voltage Vref 10  due to the mismatch between the MOS transistors M 2  and M 3 , the comparator  40  generates the control signal S 40  with a high voltage level to turn on the NMOS transistor Md, so that, there is a discharge path P 41  formed between the output node Nout and the ground terminal GND. Thus, the reference node Nref 41  is discharged by the discharge path P 41  to decrease the current Io. Based on the resistors R 3  and R 4  with the same resistance value and the operation of the current mirror circuit  21 ′, the current Io is decreased and eventually equal to the current I 2 , which makes the reference voltage Vref 41  equal to the reference voltage Vref 10 . Through the voltage division, the output voltage Vo is eventually equal to the predetermined value with the decrement of the current Io. 
     According to the above embodiment, through the disposition of the resistors R 2 ˜R 4  and the operations of the voltage adjustment circuit  11  and  13 , the output voltage Vo, which is less than 1V, can be adjusted for compensating for the mismatch between the PMOS transistors M 1  and M 2  and between the PMOS transistors M 2  and M 3 , such that the reference voltage generation circuit  1 ′ is insensitive to the mismatch induced by the process variations. 
     While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.