Patent Publication Number: US-RE45419-E

Title: Surface acoustic wave device and method of fabricating the same

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The invention generally relates to surface acoustic wave devices and methods of fabricating the same, and more particularly, to a surface acoustic wave device having a SAW chip hermetically sealed, and a method of fabricating the same. 
     2. Description of the Related Art 
     Recently, there has been a demand to downsize electric parts mounted to electronic devices and improve the performance thereof with downsizing and high performance of the electronic devices. For instance, there have been similar demands on surface acoustic wave (SAW) devices that are electric parts used as filters, delay lines, oscillators in electronic devices capable of transmitting and receiving radio waves. 
     A description will now be given of a filter device equipped with a conventional SAW device.  FIG. 1A  is a perspective view of a SAW filter  100 , and  FIG. 1B  is a cross-sectional view taken along a line F-F shown in  FIG. 1A . This type of SAW device is disclosed, for example, Japanese Patent Application Publication No. 8-18390 (see  FIG. 4 , particularly). 
     Referring to  FIG. 1A , the SAW filter  100  includes a ceramic package  102  having a cavity  109 , a metal cap  103  and a SAW chip  110 . The SAW chip  110  is placed in the cavity  109 , which is sealed with the metal cap  103 . As shown in  FIG. 1B , the package  102  has a three-layer structure composed of three joined substrates  102 a,  102 b and  102 c. Electrode pads  105  are provided on the top of the substrate  102 b, and foot patterns  107  are provided on the bottom of the substrate  102 c. Wiring patterns  106  are provided on sides of the package  102 , and connect the electrode pads  105  and the foot patterns  107 . The SAW chip  110  is fixed to the bottom of the cavity  109  so that comb-like electrodes (an interdigital transducer: IDT)  113  on the SAW chip  110  face up. Electrode pads  114  on the SAW chip  110  are connected to the electrode pads  105  via wires  108 . The metal cap  103  is bonded to the top surface of the package by a bonding material made of solder or resin, which material serves as a washer  104 . 
     There is another proposal to mount the SAW chip in flip-chip fashion (see, for example, Japanese Patent Application Publication No. 2001-110946).  FIGS. 2A and 2B  show this type of SAW device. More particularly,  FIG. 2A  is a perspective view of a SAW chip  210  of a SAW filter  200 , and  FIG. 2B  is a cross-sectional view of the SAW filter  200 , which view corresponds to a cross section taken along the line F-F shown in  FIG. 1A . 
     As shown in  FIG. 2A , the SAW chip  210  has a piezoelectric material substrate (hereinafter referred to as piezoelectric substrate)  211 . Comb-like electrodes  213  that form an IDT are formed on a main surface (upper surface) of the piezoelectric substrate  211 . Electrode pads  214  are provided on the main surface and are electrically connected to the IDT  213  via wiring patterns. As shown in  FIG. 2B , a package  202  has a cavity  209 . Electrode pads  205  are provided on the bottom of the cavity  209 , which is also referred to as die-attached surface. The pads  205  are positioned so as to correspond to the electrode pads  214  of the SAW chip  211 . The SAW chip  210  is flip-chip mounted in the cavity  209  so that the IDT  213  and the electrode pads  214  face the die-attached surface. The electrode pads  214  and  205  are bonded via metal bumps  208  so that these pads are electrically and mechanically fixed together. The electrode pads  205  are electrically connected to foot patterns  207  on the backside of the package  202  by means of via-wiring lines  206 , which penetrate the bottom portion of the package  202 . A metal cap  203  closes an opening of the cavity  209  and is bonded to the package  202  by a bonding material  204 . 
     A duplexer equipped with a transmit filter and a receive filter may be formed by using SAW filters as mentioned above. Such a duplexer will now be described with reference to  FIGS. 3A and 3B . A duplexer  300  shown in these figures has a transmit filter  310 a and a receive filter  310 b, each of which filters is like the SAW filter  100 .  FIG. 3A  shows a cross section of the duplexer  300 , which corresponds to that taken along the line F-F shown in  FIG. 1A .  FIG. 3B  is a plan view of a SAW chip  310 . 
     Referring to  FIG. 3A , the duplexer  300  has a package  302  in which the SAW chip  310  is mounted. A matching-circuit board  321  and a main board  322  are provided on the bottom side of the package  302 . The matching-circuit board  321  is provided in such a way as to be sandwiched by the main board  322 . As shown in  FIG. 3B , the SAW chip  310  is equipped with the transmit filter  310 a and the receive filter  310 b. Each of the filters  310 a and  310 b has respective IDTs  313  arranged in ladder fashion. The IDTs  313  are connected to electrode pads  314  via wiring patterns  315 . 
     The SAW filter or duplexer as mentioned above is required to have the SAW chip hermetically sealed. The metal cap is used, along with bonding material or resin, to accomplish hermetically sealing. 
     However, there are drawbacks to be solved. A large joining area (seal width) at the interface between the package and the cap is needed to hermetically seal the cavity with high reliability. However, this prevents downsizing of the package. Downsizing of package is also restricted due to the use of wires because the wires need a relatively wide pattern for bonding. The package is the multilayer substrate made of ceramics, which is comparatively expensive. The device needs the process of assembling the cap, chip and package device, and is therefore costly. 
     It is an object of the present invention to provide a downsized, less expensive, productive SAW device and a method of fabricating the same. 
     This object of the present invention is achieved by a surface acoustic wave device comprising: a piezoelectric substrate having a first surface on which comb-like electrodes, first pads connected thereto, and a first film are provided, the first film being located so as to surround the comb-like electrodes; and a base substrate having a second surface on which second pads joined to the first pads and a second film joined to the first film are provided, the first and second films joined by a surface activation process defining a cavity in which the comb-like electrodes and the first and second pads are hermetically sealed. 
     The above objects of the present invention are also achieved by a method of fabricating a surface acoustic wave device comprising the steps of: (a) forming a first film on a first surface of a piezoelectric substrate on which comb-like electrodes and first pads are formed so as to be surround by the first film; (b) forming a second film on a second surface of a base substrate, the second film corresponding to the first film in position; (c) subjecting a surface activation process to surfaces of the first and second films; and (d) joining the first and second films so as to join activated surfaces thereof, the comb-like electrodes being hermetically sealed in a cavity defined by the first and second films. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Other objects, features and advantages of the present invention will become more apparent from the following detailed description when read in conjunction with the accompanying drawings, in which: 
         FIG. 1A  is a perspective view of a conventional SAW device; 
         FIG. 1B  is a cross-sectional view taken along a line F-F shown in  FIG. 1A ; 
         FIG. 2A  is a perspective view of a SAW chip used in a conventional SAW device shown in  FIG. 2B ; 
         FIG. 2B  is a cross-sectional view of the conventional SAW device that has the SAW chip shown in  FIG. 2A ; 
         FIG. 3A  is a cross-sectional view of a conventional duplexer; 
         FIG. 3B  is a plan view of a SAW chip used in the duplexer shown in  FIG. 3A ; 
         FIG. 4A  is a perspective view of a SAW device in which the fundamental concepts of the present invention are realized; 
         FIG. 4B  is a cross-sectional view taken along a line A-A shown in  FIG. 4A ; 
         FIGS. 5A and 5B  show a surface activation process; 
         FIG. 6A  is a plan view of a SAW chip according to a first embodiment of the present invention; 
         FIG. 6B  is a cross-sectional view taken along a line B-B shown in  FIG. 6A ; 
         FIG. 7A  is a plan view of a base substrate used in the first embodiment of the present invention; 
         FIG. 7B  is a cross-sectional view taken along a line C-C shown in  FIGS. 7A and 7C ; 
         FIG. 7C  is a bottom view of the base substrate shown in  FIGS. 7A and 7B ; 
         FIG. 8  is a cross-sectional view of a SAW device according to the first embodiment of the present invention; 
         FIGS. 9A through 9J  show a method of producing the SAW chip shown in  FIGS. 6A and 6B ; 
         FIGS. 10A through 10F  show a method of producing the base substrate shown in  FIGS. 7A through 7C ; 
         FIGS. 11A through 11F  show another method of producing the base substrate shown in  FIGS. 7A through 7C ; 
         FIGS. 12A through 12G  show another process of producing the SAW device shown in  FIG. 8 ; 
         FIG. 13A  is a plan view of a base substrate according to a second embodiment of the present invention; 
         FIG. 13B  is a cross-sectional view taken along a line D-D shown in  FIGS. 13A and 13C ; 
         FIG. 13C  is a bottom view of the base substrate shown in  FIGS. 13A and 13B ; 
         FIG. 14  is a circuit diagram of the SAW device according to the second embodiment; 
         FIG. 15A  is a plan view of a SAW chip according to a third embodiment of the present invention; 
         FIG. 15B  is a cross-sectional view taken along a line E-E shown in  FIG. 15A ; 
         FIGS. 16A and 16B  show a method of producing a joined substrate used in the third embodiment; 
         FIG. 17A  is a plan view of a part of a substrate in which SAW chips, each shown in  FIGS. 6A and 6B , are integrally arranged in rows and columns according to a fourth embodiment; 
         FIG. 17B  is a plan view of a part of a substrate in which base substrates, each shown in  FIGS. 7A through 7C , are integrally arranged in rows and columns; 
         FIG. 18  is a plan view of a part of a substrate in which SAW chips are integrally arranged in rows and columns according to a fifth embodiment; 
         FIG. 19  is a plan view of a SAW device equipped with an LTCC substrate according to a sixth embodiment; 
         FIG. 20A  is a plan view of a duplexer according to a seventh embodiment; and 
         FIG. 20B  is a circuit diagram of a SAW device equipped with the duplexer shown in  FIG. 20A . 
     
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     A description will now be given of the fundamental concepts of the present invention.  FIG. 4A  is a perspective view of a SAW device  1  having the fundamental concepts of the invention, and  FIG. 4B  is a cross-sectional view taken along a line A-A shown in  FIG. 4A . 
     The SAW device  1  has a piezoelectric substrate  11 A and a base substrate  2 A. On the main (upper) surface of the piezoelectric substrate  11 A, provided are comb-like electrodes (IDT)  13 , electrode pads  14  and wiring patterns  15 . Electrode pads  5  are provided on a main surface of the base substrate  2 A. The electrode pads  5  are provided at positions that correspond to the electrode pads  14 . 
     A metal film  16  is provided on a peripheral potion on the main surface of the piezoelectric substrate  11 A. The metal film  16  is located further out than the IDT  13  and the pads  14  so as to surround these patterns. Similarly, a metal film  4  is provided on a peripheral portion on the main surface of the base substrate  2 A. The metal films  16  and  4  are joined so that a cavity  9  defined by the piezoelectric substrate  11 A and the base substrate  2 A can be hermetically sealed. In the cavity  9  thus sealed hermetically, there are the IDT  13 , the electrode pads  14  and the wiring patterns  15 . 
     When the substrates  11 A and  2 A are joined so that the metal films  16  and  4  are joined, the electrode pads  14  and  5  are joined. An electric contact with the pads  14  on the substrate  11 A can be made on the backside of the base substrate  2 A via a via-hole  6 a that penetrates the base substrate  2 A. The via-hole  6 a may be full of a conductor such as a metal bump, so that a via-wiring line can be made. The input and output terminals of the IDT  13  can be extended up to the backside of the base substrate  2 A. 
     The piezoelectric substrate  11 A may be a piezoelectric single-crystal substrate of a 42° Y-cut X-propagation lithium tantalate (LiTaO 3 :LT). The LT substrate has a linear expansion coefficient of 16.1 ppm/° C. in the X direction in which the SAW is propagated. The LT substrate may be replaced by a piezoelectric single-crystal substrate of Y-cut lithium niobate (LiNbO 3 :LN). 
     The IDT  13 , the electrode pads  14 , the wiring patterns  15  and the metal film  16  may be made of a conductor that contains, as the major component, at least one of gold (Au), aluminum (Al), copper (Cu), titanium (Ti), chromium (Cr) and tantalum (Ta). The patterns may be a single layer or a laminate composed of at least two conductive layers, each of which contains at least one of Au, Al, Cu, Ti, Cr and Ta. The conductors may be deposited by, for instance, sputtering. 
     The base substrate  2 A may be made of an insulator that contains, as the major component, at least one of silicon, ceramics, aluminum ceramics, BT (Bismuthimido-Triazine) resin, PPE (Polyphenylene-Ethel), polyimide resin, glass-epoxy and glass-cloth. The first embodiment employs silicon for the base substrate  2 A because silicon can easily be processed and handled at the stage of wafer. Preferably, the base substrate  2 A is made of a silicon substance that has a resistivity as low as 1000 Ω·m or greater in order to avoid degradation of the filter characteristic stemming from the resistance of silicon. 
     The electrode pads  5  and the metal film  4  on the main surface of the base substrate  2 A may be made of a conductor that contains, as the major component, at least one of Au, Al, Cu, Ti, Cr and Ta. The conductors may be deposited by, for instance, sputtering. The pads  5  and the film  4  may be a single layer or a laminate of at least two layers. 
     An adhesive may be used to join the substrates  11 A and  2 A. However, it is preferable to directly bond the substrates  11 A and  2 A metal films 16 and 4 at room temperature. In this case, the bonding strength can be enhanced by applying a surface activation process to the joining surfaces of the substrates  11 A and  2 A. Now, a description will be given, with reference to  FIGS. 5A and 5B , of the joining method that employs the surface activation process. 
     Referring to  FIG. 5A , both of the substrates  11 A and  2 A are cleaned through RCA cleaning or the like, so that impurities X 1  and X 2  including compounds and adsorbate that adhere to the surfaces, especially the joining surfaces, are removed (cleaning process). RCA cleaning is one of the techniques that utilize solutions such as a cleaning solution of ammonia, hydrogen peroxide, and water, mixed at a volume mixing ratio of 1:1-2:5-7, and a cleaning solution of hydrochloric acid, hydrogen peroxide, and water, mixed at a volume mixing ratio of 1:1-2:5-7. 
     After the cleaned substrates are dried (drying process), as shown in  FIG. 5B , the joining surfaces of the substrates  11 A and  2 A are exposed to ion beams, neutralized high-energy atom beams, or plasma of inert gas such as argon (Ar) or oxygen, so that residual impurities X 11  and X 21  are removed, and that the surfaces can be activated (activation process). The particle beams or plasma to be used are selected according to the materials of the substrates to be joined. For example, the surface activation process with inert gas is useful for many materials. Particularly, for silicon dioxide (SiO 2 ), ion beam or plasma of oxygen may also be used. 
     The piezoelectric substrate  11 A and the silicon substrate  2 A are then positioned and joined to each other (joining process) in such a manner that the metal films  16  and  4  are positioned and the electrode pads  14  and  5  are positioned. For most materials, this joining process may be carried out in a vacuum or in an atmosphere of a high purity gas such as an inert gas, though it may be carried out in the air. Also, it might be necessary to press the substrates  11 A and  2 A from both sides. This joining process can be carried out at room temperature or by heating the substrates  11 A and  2 A at a temperature of 100° C. or lower. The use of heating may increase the joining strength of the substrates  11 A and  2 A. 
     The present method does not need an annealing process at 1000° C. or higher after the substrates  11 A and  2 A are joined. Thus, the substrates  11 A and  2 A can be reliably joined without any damage. In addition, the method with the surface activation process does not need any adhesive agent such as resin or metal and realizes a height-reduced package, so that downsizing of package can be achieved. Further, a sufficient joining strength can be obtained by a smaller joining interface area than that for the adhesive, so that the package can be miniaturized. The joining process employed in the invention can be applied to the wafer. Thus, a large number of SAW devices  1  can be produced at a time by using a wafer-level piezoelectric substrate having multiple piezoelectric substrates integrally arranged in rows and columns and a wafer-level base substrate having multiple base substrates integrally arranged in rows and columns. This realizes a simplified production process and an improved yield. 
     When the metal films  4  and  16  contain gold, these films can be joined more tightly because gold is comparatively soft. The films  4  and  16  are joined via joining surfaces that contain gold by the surface activation process. Only one of the metal films  4  and  16  may contain gold. 
     Based on the above-mentioned concepts of the present invention, the cavity  9  that houses the IDT  13  can be minimized. The use of the surface activation process for joining the piezoelectric substrate  11 A and the base substrate  2 A realizes a reduced joining interface area while a sufficient joining strength can be secured. This contributes to downsizing the SAW device. The base substrate  2 A can be processed at the wafer level and may be made of silicon that is less expensive. This simplifies the fabrication process and produces the less-expensive SAW device at an improved yield. Now, a description will be given of embodiments of the present invention based on the above-mentioned concepts. 
     (First Embodiment) 
     A description will now be given of a first embodiment of the present invention.  FIGS. 6A ,  6 B,  7 A,  7 B,  7 C and  8  illustrate a SAW device  21  according to the first embodiment. More particularly,  FIG. 6A  is a plan view of a SAW chip  20  of the SAW device  21 , and  FIG. 6B  is a cross-sectional view taken along a line B-B shown in  FIG. 6A .  FIG. 7A  is a plan view of a base substrate  22  of the SAW device  21 ,  FIG. 7B  is a cross-sectional view taken along a line C-C shown in  FIG. 7A , and  FIG. 7C  is a bottom view of the base substrate  22 .  FIG. 8  is a cross-sectional view of the SAW device  21 , which corresponds to a cross section taken along the line B-B or C-C mentioned before. 
     As shown in  FIGS. 6A and 6B , the SAW chip  20  has an LT substrate  11  having the main surface on which IDTs  13  connected in ladder arrangement, electrode pads  14  and wiring patterns  15  that connect the IDTs  13  and the electrode pads  14 . The IDTs  13 , the electrode pads  14  and the wiring patterns  15  have been described previously. The metal film  16  is provided on the main surface so as to surround the IDTs  13  and the electrode pads  14 . The metal film  16  is connected to the electrode pads  14  via wiring patterns  17 , which have relatively high resistance values. 
     As is shown in  FIGS. 7A through 7C , the base substrate  22  may be a silicon substrate  2  having the main surface on which the electrode pads  5  are arranged so as to correspond to the electrode pads  14  in position. The electrode pads  5  have been described. 
     The metal film  4  is formed on the base substrate  22  so as to surround the electrode pads  5 . The metal film  4  corresponds to the metal film  16  in position. The metal film  4  is electrically extended to the backside of the silicon substrate  2  by means of the via conductors  7  that penetrate the silicon substrate  2 . The metal film  4  may be grounded on the backside of the silicon substrate  2  through the via conductors  7 . In the assembled state, the IDTs  13 , the electrode pads  14  and  5  and the metal films  16  and  4  are all grounded. 
     The SAW chip  20  is joined to the base substrate  22  so that the main surface of the SAW chip  20  faces the main surface of the base substrate  22 . That is, the SAW chip  20  is mounted in the facedown state. This joining results in the SAW device  21  shown in  FIG. 8 . The aforementioned surface activation process can be applied to the joining. The electrode pads  14  and  5  are joined at the time of joining the SAW chip  20  to the base substrate  22 . 
     A description will now be given of a method of fabricating the SAW device  21  with reference to  FIGS. 9A through 9J , and  FIGS. 10A through 10F .  FIGS. 9A through 9J  show a process of producing the SAW chip  20  of the SAW device  21 , and  FIGS. 10A through 10F  show a process of producing the base substrate  22 . 
     The step of  FIG. 9A  prepares the LT substrate  11 , which is, for example, 250 μm thick. Next, as shown in  FIG. 9B , an electrode film  13 A, which contains a major component of a metal of aluminum or the like, is formed on the main surface of the LT substrate  11 . The electrode film  13 A is an underlying layer of the IDTs  13 , the electrode pads  14 , the wiring patterns  15  and the metal film  16 . Then, as shown in  FIG. 9C , a mask  25  is provided on the electrode film  13 A. The mask  25  is photolithographically patterned into the IDTs  13 , the electrode pads  14 , the wiring patterns  15  and the metal film  16 . Thereafter, the electrode film  13 A is etched so that a patterned electrode film  13 B can be formed, as shown in  FIG. 9D . 
     The patterned film  13 B is the underlying layer of the IDTs  13 , the electrode pads  14 , the wiring patterns  15  and the metal film  16 . The mask  25  that remains after etching is removed, and an insulating film such as silicon oxide (SiO 2 ) is provided so as to cover the entire surface including the patterned electrode film  13 B. Then, as shown in  FIG. 9F , a patterned mask  27  for forming the high-resistance wiring patterns  17  is formed photolithographically. Then, as shown in  FIG. 9G , the insulating film  26  is etched with the mask  27 , so that the wiring patterns  17  can be formed. An insulation film  28  may be provided on the electrode film  13 B in order to protect it, as shown in  FIG. 9G . 
     Then, as shown in  FIG. 9H , a metal film  14 A is provided so as to cover the entire surface, and a mask  29  is photolithographically formed, as shown in  FIG. 9I . The mask  29  is used to partially remove the metal film  14 A for defining the IDTs  13 , the electrode pads  14  and the metal film  16 . Then, etching is carried out (liftoff), so that the IDTs  13 , the electrode pads  14 , the wiring patterns  17  and the metal film  16  can be defined, as shown in  FIG. 9J , in which only the pads  14  and metal film  16  are shown for the sake of simplicity. Preferably, the IDTs  13 , the electrode pads  14  and the wiring patterns  17  have almost the same thickness as the metal film  16 . This avoids problems that may be caused at the time of joining the base substrate  22  and the SAW chip  20 . If there is a considerable difference in thickness, the IDTs  13  may contact another element or the pads  14  may not contact the corresponding electrode pads  5 . 
     The electrode pads  14  and the metal film  16  are connected by the wiring patterns  17 . However, the wiring patterns  17  may be omitted when the LT substrate  11  has a resistivity as high as 10−14 to 10−7 Ω·m. This further facilitates to simplification of the production process. 
     The base substrate  22  is produced as follows. The step of  FIG. 10A  prepares the silicon substrate  2 , which is, for example, 250 μm thick. A metal film  4 A, from which the electrode pads  5  and the metal film  4  will be defined later, is formed on the main surface of the silicon substrate  2 . 
     Then, as shown in  FIG. 10C , a mask  35  used to shape the metal film  4 A into the electrode pads  5  and the metal film  4  is photolithographically formed, and etching is then carried out as shown in  FIG. 10D . The mask  35  includes patterns for defining the vias  6 a and  7 a, which electrically extend the electrode pads  5  and the metal film  4  to the backside of the silicon substrate  2 . 
     The vias  6 a and  7 a are formed as follows. A mask  36  patterned into the vias  6 a and  7 a is photolithographically formed, as shown in  FIG. 10E . Then, the silicon substrate  2  is subjected to reactive ion etching (RIE), preferably, deep-RIE, so that the vias  6 a and  7 a extending vertically can be formed. The mask  36  that remains after etching is removed. 
     The SAW chip  20  and the base substrate  22  thus produced are joined by the process that has been described with reference to  FIGS. 5A and 5B . This joining results in the SAW device  21 . The vias  6 a and  7 a are filled with a conductor such as metal bumps, so that the via-wiring lines  6  and  7  can be produced. The conductor may be applied to the vias  6 a and  7 a before or after joining the substrates  11  and  2 . 
     All the steps of  FIGS. 10A through 10F  are carried out from the main surface of the base substrate  22 . This holds true for even deep-RIE shown in  FIG. 10F . However, deep-RIE may be carried out from the backside of the silicon substrate  2  opposite to the front side on which the metal film  4 A is formed. This alternative process will now be described with reference to  FIGS. 11A through 11F . 
     The steps of  FIGS. 11A and 11B  are the same as those of  FIGS. 10A and 10B . The step of  FIG. 11C  photolithographically forms a mask  35 ′ for patterning the metal film  4 A into electrode pads  5 ′ and an electrode film  4 ′. Then, as shown in  FIG. 1D , etching is carried out with the mask  35 ′, so that the pads  5 ′ and the metal film  4 ′ can be formed. The mask  35 ′ does not have any pattern for defining the vias  6 a and  7 a. 
     Then, as shown in  FIG. 11F , a mask  36 ′ is formed on the backside of the silicon substrate  2 .  FIGS. 11E and 11F  illustrate the silicon substrate  2  that is turned upside down. The silicon substrate  2  is then etched by RIE, preferably deep-RIE, so that vias  6 a and  7 a can be formed, as shown in  FIG. 11F . The mask  36 ′ that remains after etching is removed. 
     The above process does not each the metal film  4 ′ and the electrode patterns  5 ′, so that the metal films  4 ′ and  16  and the electrode pads  5 ′ and  14  can be self-aligned in joining. This simplifies the production process greatly. In the above-mentioned alternative process, the SAW chip  20  produced by the process shown in  FIGS. 9A through 9J  can be used. 
     The above-mentioned fabrication methods complete the SAW chip  20  and the base substrate  22  separately, and then join them. Besides, some process may be applied after the SAW chip  20  and the base substrate  22  are joined. For example, the vias  6 a and  7 a may be formed in the silicon substrate  2  after joining. This will now be described with reference to  FIGS. 12A through 12G . The following process uses the SAW chip prepared by the process described with reference to  FIGS. 9A through 9J . 
     The steps of  FIGS. 12A through 12D  are the same as those of  FIGS. 11A through 11D . The subsequent step of  FIG.12E  joins the SAW chip  20  to the main surface of the silicon substrate  2 . Then, as shown in  FIG. 12F , a mask  36 ′ is formed on the backside of the silicon substrate  2 , which is then subjected to RIE, preferably, deep-RIE. This results in the vias  6 a and  7 a in the silicon substrate  2 , as shown in  FIG. 12G . 
     The above process does not etch the metal film  4 ′ and the electrode pads  5 ′. Thus, the metal films  4 ′ and  16  and the electrode pads  5 ′ and  14  can be self-aligned at the time of joining. This simplifies the production process. The SAW device  21  thus produced has the aforementioned structure and effects. 
     (Second Embodiment) 
       FIGS. 13A through 13C  show a base substrate  32  employed in a SAW device according to a second embodiment of the present invention. More particularly,  FIG. 13A  is a plan view of the base substrate  32 ,  FIG. 13B  is a cross-sectional view taken along a line D-D shown in  FIG. 13A , and  FIG. 13C  is a backside view of the base substrate  32 . The SAW chip used in the second embodiment may be the same as the SAW chip  20  used in the first embodiment. 
     A given electric element is formed on the main surface of the base substrate  32 . The electric element may, for example, be a matching circuit, which changes the input impedance of the SAW chip  20  so as to make impedance matching with an external circuit (impedance conversion). In  FIG. 13A , the impedance matching circuit is composed of an inductor L 1  and a capacitor C 1 .  FIG. 14  shows a circuit configuration of the impedance matching circuit. The inductor L 1  is provided between an input line extending from an input end and ground, and the capacitor C 1  is provided between lines connected to two output ends. The impedance matching circuit thus formed prevents degradation due to impedance mismatch with an external circuit. The electric element mountable on the base substrate  32  is not limited to the impedance matching circuit but may be any component, which may be selected in terms of objects, applications and characteristics required. 
     The electric element may be simultaneously formed along with the electrode pads  5  and the metal film  4  or may be formed before or after these patterns are formed. The electric element may be made of copper (Cu), aluminum (Al) or gold (Au) deposited by sputtering or the like. 
     The SAW device includes the electric element so that it does not need it externally. The SAW device is thus usable to various applications. The other structures, fabrication method and effects of the SAW device according to the second embodiment are the same as those of the first embodiment. 
     (Third Embodiment) 
       FIG. 15A  is a plan view of a SAW chip  40  of a SAW device according to a third embodiment of the present invention, and  FIG. 15B  is a cross-sectional view taken along a line E-E shown in  FIG. 15A . 
     The SAW chip  40  has a piezoelectric substrate  41 a like an LT substrate, to the backside of which is joined another substrate  41 b made of a material different from the piezoelectric substrate  41 a. The substrate  41 b serves as a support substrate, and may, for example, be a silicon substrate. The substrates  41 a and  41 b form a joined substrate. 
     Preferably, the support substrate  41 b has a smaller Young&#39;s modulus and a smaller linear expansion coefficient than those of the piezoelectric substrate  41 a. A sapphire substrate or silicon substrate may be used as the supporting substrate  41 b. The use of the above support substrate  41 b restricts thermal expansion of the piezoelectric  41 a, and reinforces the strength thereof so that the required strength of the piezoelectric substrate can be achieved by the support substrate. Thus, the joined substrate can be made thinner than the piezoelectric substrate conventionally used, so that the SAW chip can be thinned. When the support substrate  41 b is made of silicon, which is easily processible, the SAW device can be produced more easily and precisely. Further, the wafer-level process can be used, so that the productivity can be improved. From the aforementioned viewpoints, preferably, the support substrate  41  is a silicon substance that has a resistivity as low as 1000 Ω·m or greater in order to avoid degradation of the filter characteristic stemming from the resistance of silicon. 
     It is preferable that the piezoelectric substrate  41 a and the support substrate  41 b are joined by the joining method based on the surface activation process. Thus, the substrates  41 a and  41 b can be joined more strongly and even at room temperature. This prevents occurrence of any damages during process and degradation of the characteristic. Improved joining strength enables a reduced joining interface area, so that the SAW chip  40  can be downsized. Further, improved joining strength effectively restricts thermal expansion of the LT substrate  41 a by the silicon substrate  41 b, so that the frequency stability for temperature variation can be improved. 
     The SAW chip  40  can be produced as shown in  FIGS. 16A and 16B .  FIG. 16A  shows a step of joining an LT substrate  41 A and a silicon substrate  41 B. For example, the LT substrate  41 A is 250 μm thick, and the silicon substrate  41 B is also 250 μm thick. Preferably, the substrates  41 A and  41 B are joined by using the surface activation process. However, an adhesive such as resin may be used for joining. 
     The joined substrate is grinded and polished from both sides thereof, so that the joined substrate  41  composed of the substrates  41 a and  41 b can be produced. The joined substrate  41  is thinner than the LT substrate alone. Then, the joined substrate  41  is processed in such a manner as shown in  FIGS. 9A through 9J , wherein the joined substrate  41  is substituted for the LT substrate  11 . The silicon substrate  41 a may be grinded and polished before or after the IDTs  13 , the pads  14 , the wiring patterns  15  and the metal film  16  are formed on the LT substrate  41 a, and before or after joining. 
     (Fourth Embodiment) 
     A fourth embodiment of the present invention is directed to fabricating a large number of SAW devices at a time. For this purpose, substrates  50 A and  52 A respectively shown in  FIGS. 17A and 17B  are used. The substrate  50 A has a large number of SAW chips  20  that are integrally arranged in rows and columns. The substrate  52 A has a large number of base substrates  22  that are integrally arranged in rows and columns. The substrates  50 A and  52 A are joined and divided into SAW devices by a dicing process with a dicing blade or laser beam. The use of the substrates  50 A and  52 A reduces the cost. 
     Holes for dicing may be formed simultaneously when the vias  6 a and  7 a are formed in the step of  FIG. 11F  or  FIG. 12G . The use of holes for dicing enables rapid and accurate dicing work. The other structures, fabrication method and effects of the fourth embodiment are the same as those of the previous embodiments. 
     (Fifth Embodiment) 
     The SAW device of the third embodiment may be produced by a process similar to that of the fourth embodiment. In this case, a substrate  60 A as shown in  FIG. 18  is used. The substrate  60 A has SAW chips  40  integrally arranged in rows and columns. The piezoelectric substrate  41 a of the substrate  60 A is supported by the support substrate  41 b. The base substrate used in the fourth embodiment may be used in the fifth embodiment. 
     The other structures, fabrication method and effects of the fifth embodiment are the same as those of the previous embodiments. 
     (Sixth Embodiment) 
     A sixth embodiment of the present invention is directed to joining the base substrate  22  or  42  directly to a substrate of low-temperature co-fired ceramics (LTCC) or a printed-circuit board.  FIG. 19  is a plan view of an LTCC substrate  72 A on which a chip  81  for a transmit circuit, a chip  82  for a receive circuit, and an RF circuit  83  are mounted. Base substrates  72 a and  72 b, which correspond to, for example, the aforementioned base substrates  22 , are provided on the LTCC substrate  72 A and are positioned on transmission lines that connect the RF circuit  83  to the chips  81  and  82 . The base substrates  72 a and  72 b have pads connected to the transmission lines. The SAW chips  20  are joined to the base substrates  72 a and  72 b so that the metal films of the chips  20  and the base substrates  72 a and  72 b are joined together. 
     (Seventh Embodiment) 
     A seventh embodiment of the present invention is a SAW device equipped with two or more SAW filters, whereas any of the aforementioned embodiments is equipped with only one SAW filter.  FIG. 20A  shows a SAW chip that is a duplexer  90 , which has a transmit filter  90 a and a receive filter  90 b. 
       FIG. 20B  shows a SAW device equipped with the duplexer  90  and a matching circuit interposed between a common input terminal and the receive filter  90 b. The matching circuit shown in  FIG. 20B  is a low-pass filter made up of capacitors C 2  and C 3  and an inductor L 2 . The capacitors C 2  and C 3  are connected between ends of the inductor L 2  and ground. The low-pass filter may be provided between the common input terminal and the transmit filter  90 a instead of or in addition to the low-pass filter for the receive filter  90 b. For example, the low-pass filter may be applied to only the higher frequency side. The matching circuit is not limited to the low-pass filter. 
     The present invention is not limited to the specifically disclosed embodiments, and other embodiments, variations and modifications may be made without departing from the scope of the present invention. 
     The present application is based on Japanese Patent Application No. 2003-096577 filed on Mar. 31, 2003, the entire disclosure of which is hereby incorporated by reference.