Patent Publication Number: US-11664381-B2

Title: Capacitor cell and structure thereof

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This application is a Continuation of application Ser. No. 16/591,064, filed on Oct. 2, 2019, now U.S. Pat. No. 10,971,495, which is a Continuation of U.S. application Ser. No. 15/495,106, filed on Apr. 24, 2017, now U.S. Pat. No. 10,475,793, the entirety of which are incorporated by reference herein. 
    
    
     BACKGROUND 
     Power supply lines in an integrated circuit (IC) can supply current to charge and discharge active and passive devices in the IC. For example, digital complementary metal-oxide-semiconductor (CMOS) circuits draw current when the clock makes a transition. During operation of circuits, the power supply lines supply transient currents with a relatively high intensity, which can result in voltage noise in the power supply lines. The voltage in the power supply line will fluctuate when the fluctuation time of the transient current is short or when its parasitic inductance or parasitic resistance is large. 
     The operational frequency of the IC may be on the order of several hundreds of mega-hertz (MHz) to several giga-hertz (GHz). In such circuits, the rising time of clock signals is very short, and voltage fluctuations in the supply line may be very large. Undesired voltage fluctuations in the power supply line powering a circuit can cause noise on its internal signals and degrade noise margins. The degradation of noise margins can reduce circuit reliability or even cause circuit malfunction. 
     To reduce the magnitude of voltage fluctuations in the power supply lines, filtering or de-coupling capacitors are usually used between the different power supply lines or between the power supply line and the ground line. De-coupling capacitors act as charge reservoirs that additionally supply currents to circuits to prevent momentary drops in supply voltage. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It should be noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. 
         FIG.  1    shows a capacitor cell, in accordance with some embodiments of the disclosure. 
         FIG.  2 A  shows a top view of the capacitor cell of  FIG.  1   , in accordance with some embodiments of the disclosure. 
         FIG.  2 B  shows a cross-sectional view along line A-AA of  FIG.  2 A . 
         FIG.  3    shows a capacitor cell, in accordance with some embodiments of the disclosure. 
         FIG.  4 A  shows a top view of the capacitor cell of  FIG.  3   , in accordance with some embodiments of the disclosure. 
         FIG.  4 B  shows a cross-sectional view along line B-BB of  FIG.  4 A . 
         FIG.  5 A  shows a capacitor cell, in accordance with some embodiments of the disclosure. 
         FIG.  5 B  shows a top view of the capacitor cell of  FIG.  5 A , in accordance with some embodiments of the disclosure. 
         FIG.  5 C  shows a cross-sectional view along line C-CC of  FIG.  5 B . 
         FIG.  6 A  shows a capacitor cell, in accordance with some embodiments of the disclosure. 
         FIG.  6 B  shows a top view of the capacitor cell of  FIG.  6 A , in accordance with some embodiments of the disclosure. 
         FIG.  6 C  shows a cross-sectional view along line D-DD of  FIG.  6 B . 
         FIG.  7 A  shows a power noise triggered equivalent circuit of a silicon-controlled rectifier (SCR) in the capacitor cell of  FIG.  1   . 
         FIG.  7 B  shows a cross-sectional view illustrating the SCR of  FIG.  7 A . 
         FIG.  8 A  shows a ground noise triggered equivalent circuit of a SCR in the capacitor cell of  FIG.  1   . 
         FIG.  8 B  shows a cross-sectional view illustrating the SCR of  FIG.  8 A . 
     
    
    
     DETAILED DESCRIPTION 
     The following disclosure provides many different embodiments, or examples, for implementing different features of the subject matter provided. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. In some embodiments, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. 
     Some variations of the embodiments are described. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements. It should be understood that additional operations can be provided before, during, and/or after a disclosed method, and some of the operations described can be replaced or eliminated for other embodiments of the method. 
       FIG.  1    shows a capacitor cell  100 A, which may serve as a de-coupling capacitor, in accordance with some embodiments of the disclosure. The capacitor cell  100 A is capable of providing the capacitance for decreasing noise in the power supply lines in an integrated circuit (IC). 
     The capacitor cell  100 A includes a PMOS transistor MP 1  and an NMOS transistor MN 1 . The PMOS transistor MP 1  is coupled between a power supply VDD and a first node n 1 A, and a gate of the PMOS transistor MP 1  is coupled to a second node n 2 A. The NMOS transistor MN 1  is coupled between a ground VSS and the second node n 2 A, and a gate of the NMOS transistor MN 1  is coupled to the first node n 1 A. The PMOS transistor MP 1  and the NMOS transistor MN 1  form a cross-coupled de-coupling structure, which provides the MOS capacitance with a series channel-resistance for increasing the electrostatic discharge (ESD) protection and decreasing gate leakage current. 
     The capacitor cell  100 A further includes a PMOS transistor MP 2  and an NMOS transistor MN 2 . The PMOS transistor MP 2  is coupled between the first node n 1 A and the second node n 2 A, and a gate of the PMOS transistor MP 2  is coupled to the drain of the NMOS transistor MN 1  via the second node n 2 A. The NMOS transistor MN 2  is also coupled between the first node n 1 A and the second node n 2 A, and a gate of the NMOS transistor MN 2  is coupled to the drain of the PMOS transistor MP 1  via the first node n 1 A. 
     In some embodiments, in the capacitor cell  100 A, bulks of the PMOS transistors MP 1  and MP 2  are coupled to the power supply VDD, and bulks of the NMOS transistors MN 1  and MN 2  are coupled to the ground VSS. In some embodiments, the bulks of the PMOS transistors MP 1  and MP 2  and the bulks of the PMOS transistors MP 1  and MP 2  are coupled to the other voltages. For example, the bulks of the PMOS transistors MP 1  and MP 2  are both coupled to other voltage, or the bulks of the PMOS transistors MP 1  and MP 2  are coupled to different voltages. 
       FIG.  2 A  shows a top view of the capacitor cell  100 A of  FIG.  1   , in accordance with some embodiments of the disclosure, and  FIG.  2 B  shows a cross-sectional view along line A-AA of  FIG.  2 A . 
     Referring to  FIG.  1   ,  FIG.  2 A  and  FIG.  2 B  together, an array of transistors in an N-type well  110  on a P-type substrate  115  form the PMOS transistors MP 1  and MP 2 . An N+ doped region  140  is formed in the N-type well  110  and between two isolation regions  130 A and  130 B, such as a shallow trench isolation (STI). In some embodiments, the N-type well  110  is coupled to the power supply VDD via the N+ doped region  140 , and the N-type well  110  forms a bulk (or a base) B of the PMOS transistors MP 1  and MP 2 . In order to simplify the description, the contacts, vias and metals between the N+ doped region  140 , the P+ doped regions  150 A- 150 C, the first node n 1 A, the second node n 2 A and the power supply VDD are omitted. 
     The P+ doped regions  150 A,  150 B and  150 C are formed in the N-type well  110 , and the P+ doped region  150 B is disposed between the P+ doped regions  150 A and  150 C. The gate metals  210 A and  210 B are formed on the N-type well  110 . 
     The gate metal  210 A is disposed between the P+ doped regions  150 A and  150 B. In some embodiments, the gate metal  210 A and the P+ doped regions  150 A and  150 B form the PMOS transistor MP 1 . The P+ doped region  150 A is coupled to the power supply VDD, and forms a source region S for the PMOS transistor MP 1 . The P+ doped region  150 B is coupled to the first node n 1 A, and P+ doped region  150 B forms a drain region D for the PMOS transistor MP 1 . For the PMOS transistor MP 1 , the gate metal  210 A is coupled to the second node n 2 A, and an active region (e.g. a channel) of the PMOS transistor MP 1  is formed between the P+ doped regions  150 A and  150 B. In some embodiments, the PMOS transistor MP 1  is formed by multiple PMOS transistors coupled in parallel, and the configurations of the PMOS transistors coupled in parallel are similar to that of the PMOS transistor MP 1 . 
     The gate metal  210 B is disposed between the P+ doped regions  150 B and  150 C. In some embodiments, the gate metal  210 B and the P+ doped regions  150 B and  150 C form the PMOS transistor MP 2 . The P+ doped region  150 B is coupled to the first node n 1 A, and P+ doped region  150 B forms a drain region D for the PMOS transistor MP 2 . The P+ doped region  150 C is coupled to the second node n 2 A, and P+ doped region  150 C forms a source region Sc for the PMOS transistor MP 2 . For the PMOS transistor MP 2 , the gate metal  210 B is coupled to the second node n 2 A, and an active region (e.g. a channel) of the PMOS transistor MP 2  is formed between the P+ doped regions  150 B and  150 C. In some embodiments, the PMOS transistor MP 2  is formed by multiple PMOS transistors coupled in parallel, and the configurations of the PMOS transistors coupled in parallel are similar to that of the PMOS transistor MP 2 . 
     An array of transistors in a P-type well  120  on the P-type substrate  115  forms the NMOS transistors MN 1  and MN 2 . A P+ doped region  150  is formed in the P-type well  120  and between two isolation regions  130 D and  130 E, such as an STI. In some embodiments, the P-type well  120  is coupled to the ground VSS via the P+ doped region  150 , and the P-type well  120  forms a bulk (or a base) B of the NMOS transistors MN 1  and MN 2 . In order to simplify the description, the contacts, vias and metals between the P+ doped region  150 , the N+ doped regions  140 A- 140 C, the first node n 1 A, the second node n 2 A, and the ground VSS are omitted. 
     The N+ doped regions  140 A,  140 B and  140 C are formed in the P-type well  120 , and the N+ doped region  140 B is disposed between the N+ doped regions  140 A and  140 C. The gate metals  220 A and  220 B are formed on the P-type well  120 . 
     The gate metal  220 A is disposed between the N+ doped regions  140 A and  140 B. In some embodiments, the gate metal  220 A and the N+ doped regions  140 A and  140 B form the NMOS transistor MN 1 . The N+ doped region  140 A is coupled to the ground VSS, and N+ doped region  140 A forms a source region S for the NMOS transistor MN 1 . The N+ doped region  140 B is coupled to the second node n 2 A, and N+ doped region  140 B forms a drain region D for the NMOS transistor MN 1 . For the NMOS transistor MN 1 , the gate metal  220 A is coupled to the first node n 1 A, and an active region (e.g. a channel) of the NMOS transistor MN 1  is formed between the N+ doped regions  140 A and  140 B. In some embodiments, the NMOS transistor MN 1  is formed by multiple NMOS transistors coupled in parallel, and the configurations of the NMOS transistors coupled in parallel are similar to that of the NMOS transistor MN 1 . 
     The gate metal  220 B is disposed between the N+ doped regions  140 B and  140 C. In some embodiments, the gate metal  220 B and the N+ doped regions  140 B and  140 C form the NMOS transistor MN 2 . The N+ doped region  140 B is coupled to the second node n 2 A, and N+ doped region  140 B forms a drain region D for the NMOS transistor MN 2 . The N+ doped region  140 C is coupled to the first node n 1 A, and N+ doped region  140 C forms a source region Sc for the NMOS transistor MN 2 . Furthermore, the source region Sc (e.g. the N+ doped region  140 C) of the NMOS transistor MN 2  is separated from the source region Sc (e.g. the P+ doped region  150 C) of the PMOS transistor MP 2  by the isolation region  130 C. For the NMOS transistor MN 2 , the gate metal  220 B is coupled to the first node n 1 A, and an active region (e.g. a channel) of the NMOS transistor MN 2  is formed between the N+ doped regions  140 B and  140 C. In some embodiments, the NMOS transistor MN 2  is formed by multiple NMOS transistors coupled in parallel, and the configurations of the NMOS transistors coupled in parallel are similar to that of the NMOS transistor MN 2 . 
     In such embodiments, the source regions S/Sc and the drain regions D are interlaced to form an array or a row of the PMOS transistors in the N-type well  110 , and the source regions S/Sc and the drain regions D are interlaced to form an array or a row of the NMOS transistors in the P-type well  120 . In some embodiments, the number of PMOS transistors is identical to the number of NMOS transistors. In some embodiments, the PMOS transistors in the N-type well  110  and the NMOS transistors in the P-type well  120  are arranged in the same row. In some embodiments, the PMOS transistors in the N-type well  110  and the NMOS transistors in the P-type well  120  are arranged in adjacent rows. 
     In some embodiments, the source region S of the PMOS transistor MP 1  is coupled to the power supply VDD, and the source region Sc of the PMOS transistor MP 2  is coupled to the drain region D of the NMOS transistor MN 1  via the second node n 2 A. Therefore, the configurations of the source regions S and Sc are different for the PMOS transistors MP 1  and MP 2 . Furthermore, the gates of the PMOS transistors MP 1  and MP 2  are coupled to the drain region D of the NMOS transistor MN 1  via the second node n 2 A. The drain regions D of the PMOS transistors MP 1  and MP 2  are coupled to the gate of the NMOS transistors MN 1  and MN 2  via the first node n 1 A. 
     Similarly, the source region S of the NMOS transistor MN 1  is coupled to the ground VSS, and the source region Sc of the NMOS transistor MN 2  is coupled to the drain region D of the PMOS transistor MP 1  via the first node n 1 A. Therefore, the configurations of the source regions S and Sc are different for the NMOS transistors MN 1  and MN 2 . Furthermore, the gates of the NMOS transistors MN 1  and MN 2  are coupled to the drain region D of the PMOS transistor MP 1  via the first node n 1 A. The drain regions D of the NMOS transistors MN 1  and MN 2  are coupled to the gate of the PMOS transistors MP 1  and MP 2  via the second node n 2 A. 
     In some embodiments, the PMOS transistors MP 1  and MP 2  are formed by multiple PMOS transistors coupled in parallel in the array of transistors in the N-type well  110 . Similarly, the NMOS transistors MN 1  and MN 2  are formed by multiple NMOS transistors coupled in parallel in the array of transistors in the P-type well  120 . 
       FIG.  3    shows a capacitor cell  100 B, which may serve as a de-coupling capacitor, in accordance with some embodiments of the disclosure. The capacitor cell  100 B is capable of providing capacitance for decreasing noise in the power supply. 
     The capacitor cell  100 B includes a PMOS transistor MP 1  coupled between a power supply VDD and a first node n 1 B, and an NMOS transistor MN 1  coupled between a ground VSS and a second node n 2 B. A gate of the PMOS transistor MP 1  is coupled to the second node n 2 B, and a gate of the NMOS transistor MN 1  is coupled to the first node n 1 B. The PMOS transistor MP 1  and the NMOS transistor MN 1  form a cross-coupled de-coupling structure for increasing the ESD protection and decreasing gate leakage current. 
     The capacitor cell  100 B further includes a PMOS transistor MP 3  and an NMOS transistor MN 3 . The PMOS transistor MP 3  is coupled between the power supply VDD and the second node n 2 B, and a gate of the PMOS transistor MP 3  is coupled to the second node n 2 B. The NMOS transistor MN 3  is coupled between the first node n 1 B and the ground VSS, and a gate of the NMOS transistor MN 3  is coupled to the first node n 1 B. 
     In some embodiments, the PMOS transistors MP 1  and MP 3  are formed by multiple PMOS transistors coupled in parallel, and the NMOS transistors MN 1  and MN 3  are formed by multiple NMOS transistors coupled in parallel. For example, the PMOS transistor MP 3  is formed by the PMOS transistors MP 3 _ 1  and MP 3 _ 2  coupled in parallel (MP 3 _ 1 //MP 3 _ 2 ), and the NMOS transistor MN 3  is formed by the NMOS transistors MN 3 _ 1  and MN 3 _ 2  coupled in parallel (MN 3 _ 1 //MN 3 _ 2 ). The PMOS transistors MP 3 _ 1  and MP 3 _ 2  and the NMOS transistors MN 3 _ 1  and MN 3 _ 2  will be discussed in details later. 
     In the capacitor cell  100 B, bulks of the PMOS transistors MP 1  and MP 3  are coupled to the power supply VDD, and bulks of the NMOS transistors MN 1  and MN 3  are coupled to the ground VSS. 
       FIG.  4 A  shows a top view of the capacitor cell  100 B of  FIG.  3   , in accordance with some embodiments of the disclosure, and  FIG.  4 B  shows a cross-sectional view along line B-BB of  FIG.  4 A . 
     Referring to  FIG.  3   ,  FIG.  4 A  and  FIG.  4 B  together, an array of transistors in an N-type well  110  on a P-type substrate  115  form the PMOS transistors MP 1 , and MP 3  in which MP 3  is formed by MP 3 _ 1  and MP 3 _ 2  coupled in parallel. An N+ doped region  140  is formed in the N-type well  110  and between two isolation regions  130 A and  130 B, such as an STI. In some embodiments, the N-type well  110  is coupled to the power supply VDD via the N+ doped region  140 , and the N-type well  110  forms a bulk B (or a base) of the PMOS transistors MP 1 , MP 3 _ 1  and MP 3 _ 2 . In order to simplify the description, the contacts, vias and metals between the N+ doped region  140 , the P+ doped regions  150 A_ 1 ,  150 A_ 2 ,  150 B and  150 D, the first node n 1 B, the second node n 2 B, and the power supply VDD are omitted. 
     The P+ doped regions  150 A_ 1 ,  150 A_ 2 ,  150 B and  150 D are formed in the N-type well  110 . The P+ doped region  150 D is disposed between the P+ doped regions  150 A_ 1  and  150 A_ 2 , and the P+ doped region  150 A_ 2  is disposed between the P+ doped regions  150 D and  150 B. The gate metals  210 C,  210 D and  210 A are formed on the N-type well  110 . 
     The gate metal  210 C is disposed between the P+ doped regions  150 A_ 1  and  150 D. In some embodiments, the gate metal  210 C and the P+ doped regions  150 A_ 1  and  150 D form a PMOS transistor MP 3 _ 1 . The P+ doped region  150 A_ 1  is coupled to the power supply VDD, and P+ doped region  150 A_ 1  forms a source region S for the PMOS transistor MP 3 _ 1 . The P+ doped region  150 D is coupled to the second node n 2 B, and P+ doped region  150 D forms a drain region Dc for the PMOS transistor MP 3 _ 1 . For the PMOS transistor MP 3 _ 1 , the gate metal  210 C is coupled to the second node n 2 B, and an active region (e.g. a channel) of the PMOS transistor MP 3 _ 1  is formed between the P+ doped regions  150 A_ 1  and  150 D. 
     The gate metal  210 D is disposed between the P+ doped regions  150 D and  150 A_ 2 . In some embodiments, the gate metal  210 D and the P+ doped regions  150 D and  150 A_ 2  form the PMOS transistor MP 3 _ 2 . The P+ doped region  150 D is coupled to the second node n 2 B, and P+ doped region  150 D forms a drain region Dc for the PMOS transistor MP 3 _ 2 . The P+ doped region  150 A_ 2  is coupled to the power supply VDD, and P+ doped region  150 A_ 2  forms a source region S for the PMOS transistor MP 3 _ 2 . For the PMOS transistor MP 3 _ 2 , the gate metal  210 D is coupled to the second node n 2 B, and an active region (e.g. a channel) of the PMOS transistor MP 3 _ 2  is formed between the P+ doped regions  150 D and  150 A_ 2 . 
     The gate metal  210 A is disposed between the P+ doped regions  150 A_ 2  and  150 B. In some embodiments, the gate metal  210 A and the P+ doped regions  150 A_ 2  and  150 B form the PMOS transistor MP 1 . The P+ doped region  150 A_ 2  is coupled to the power supply VDD, and P+ doped region  150 A_ 2  forms a source region S for the PMOS transistor MP 1 . The P+ doped region  150 B is coupled to the first node n 1 B, and P+ doped region  150 B forms a drain region D for the PMOS transistor MP 1 . For the PMOS transistor MP 1 , the gate metal  210 A is coupled to the second node n 2 B, and an active region (e.g. a channel) of the PMOS transistor MP 1  is formed between the P+ doped regions  150 B and  150 A_ 2 . 
     An array of transistors in a P-type well  120  on the P-type substrate  115  forms the NMOS transistors MN 1 , and MN 3  in which MN 3  is formed by MN 3 _ 1  and MN 3 _ 2  coupled in parallel. A P+ doped region  150  is formed in the P-type well  120  and between two isolation regions  130 D and  130 E, such as an STI. In some embodiments, the P-type well  120  is coupled to the ground VSS via the P+ doped region  150 , and the P-type well  120  forms a bulk (or a base) B of the NMOS transistors MN 1  and MN 3 . In order to simplify the description, the contacts, vias and metals between the P+ doped region  150 , the N+ doped regions  140 A_ 1 ,  140 A_ 2 ,  140 B and  140 D, the first node n 1 B, the second node n 2 B, and the ground VSS are omitted. 
     The N+ doped regions  140 A_ 1 ,  140 A_ 2 ,  140 B and  140 D are formed in the P-type well  120 . The N+ doped region  140 A_ 2  is disposed between the N+ doped regions  140 B and  140 D, and the N+ doped region  140 D is disposed between the N+ doped regions  140 A_ 2  and  140 A_ 1 . The gate metals  220 C,  220 D and  220 A are formed on the P-type well  120 . 
     The gate metal  220 C is disposed between the N+ doped regions  140 A_ 1  and  140 D. In some embodiments, the gate metal  220 C and the N+ doped regions  140 A_ 1  and  140 D form the NMOS transistor MN 3 _ 1 . The N+ doped region  140 A_ 1  is coupled to the ground VSS, and N+ doped region  140 A_ 1  forms a source region S for the NMOS transistor MN 3 _ 1 . The N+ doped region  140 D is coupled to the first node n 1 B, and N+ doped region  140 D forms a drain region Dc for the NMOS transistor MN 3 _ 1 . For the NMOS transistor MN 3 _ 1 , the gate metal  220 C is coupled to the first node n 1 B, and an active region (e.g. a channel) of the NMOS transistor MN 3 _ 1  is formed between the N+ doped regions  140 A_ 1  and  140 D. 
     The gate metal  220 D is disposed between the N+ doped regions  140 D and  140 A_ 2 . In some embodiments, the gate metal  220 D and the N+ doped regions  140 D and  140 A_ 2  form the NMOS transistor MN 3 _ 2 . The N+ doped region  140 D is coupled to the first node n 1 B, and N+ doped region  140 D forms a drain region Dc for the NMOS transistor MN 3 _ 2 . The N+ doped region  140 A_ 2  is coupled to the ground VSS, and N+ doped region  140 A_ 2  forms a source region S for the NMOS transistor MN 3 _ 2 . For the NMOS transistor MN 3 _ 2 , the gate metal  220 D is coupled to the first node n 1 B, and an active region (e.g. a channel) of the NMOS transistor MN 3 _ 2  is formed between the N+ doped regions  140 D and  140 A_ 2 . 
     The gate metal  220 A is disposed between the N+ doped regions  140 A_ 2  and  140 B. In some embodiments, the gate metal  220 A and the N+ doped regions  140 A_ 2  and  140 B form the NMOS transistor MN 1 . The N+ doped region  140 A_ 2  is coupled to the ground VSS, and N+ doped region  140 A_ 2  forms a source region S for the NMOS transistor MN 1 . The N+ doped region  140 B is coupled to the second node n 2 B, and N+ doped region  140 B forms a drain region D for the NMOS transistor MN 1 . For the NMOS transistor MN 1 , the gate metal  220 A is coupled to the first node n 1 B, and an active region (e.g. a channel) of the NMOS transistor MN 1  is formed between the N+ doped regions  140 A_ 2  and  140 B. 
     In such embodiments, the source regions S and the drain regions D/Dc are interlaced to form an array or a row of the PMOS transistors in the N-type well  110 , and the source regions S and the drain regions D/Dc are interlaced to form an array or a row of the NMOS transistors in the P-type well  120 . In some embodiments, the number of PMOS transistors is identical to the number of NMOS transistors. In some embodiments, the PMOS transistors in the N-type well  110  and the NMOS transistors in the P-type well  120  are arranged in the same row. In some embodiments, the PMOS transistors in the N-type well  110  and the NMOS transistors in the P-type well  120  are arranged in the adjacent rows. 
     In some embodiments, the drain region D of the PMOS transistor MP 1  is coupled to the gate of the NMOS transistor MN 1  via the first node n 1 B, and the drain region Dc of the PMOS transistor MP 3  (e.g. MP 3 _ 1 //MP 3 _ 2 ) are coupled to the drain region D of the NMOS transistor MN 1 . Therefore, the configurations of the drain regions D and Dc are different for the PMOS transistors MP 1  and MP 3  (e.g. MP 3 _ 1 //MP 3 _ 2 ). Furthermore, the gates of the PMOS transistors MP 1  and MP 3  are coupled to the drain region D of the NMOS transistor MN 1  via the second node n 2 B. The source regions S of the PMOS transistors MP 1  and MP 3  are coupled to the power supply VDD. 
     Similarly, the drain region D of the NMOS transistor MN 1  is coupled to the gate of the PMOS transistor MP 1  via the second node n 2 B, and the drain region Dc of the NMOS transistor MN 3  (e.g. MN 3 _ 1 //MN 3 _ 2 ) is coupled to the drain region D of the PMOS transistor MP 1  via the first node n 1 B. Therefore, the configurations of the drain regions D and Dc are different for the NMOS transistors MN 1  and MN 3 . Furthermore, the gates of the NMOS transistors MN 1  and MN 3  are coupled to the drain region D of the PMOS transistor MP 1  via the first node n 1 B. The source regions S of the NMOS transistors MN 1  and MN 3  are coupled to the ground VSS. 
     In some embodiments, the PMOS transistors MP 1  and MP 3  are formed by multiple PMOS transistors coupled in parallel in the array of transistors in the N-type well  110 . Similarly, the NMOS transistors MN 1  and MN 3  are formed by multiple NMOS transistors coupled in parallel in the array of transistors in the P-type well  120 . 
       FIG.  5 A  shows a capacitor cell  100 C, which may serve as a de-coupling capacitor, in accordance with some embodiments of the disclosure. The capacitor cell  100 C is capable of providing the capacitance for decreasing noise in a power supply. 
     The capacitor cell  100 C includes a PMOS transistor MP 1  coupled between a power supply VDD and a first node n 1 C and an NMOS transistor MN 1  coupled between a ground VSS and a second node n 2 C. A gate of the PMOS transistor MP 1  is coupled to the second node n 2 C, and a gate of the NMOS transistor MN 1  is coupled to the first node n 1 C. The PMOS transistor MP 1  and the NMOS transistor MN 1  form a cross-coupled de-coupling structure for increasing the ESD protection and decreasing gate leakage current. 
     The capacitor cell  100 C further includes a PMOS transistor MP 2  and an NMOS transistor MN 3  in which MN 3  is formed by MN 3 _ 1  and MN 3 _ 2  coupled in parallel. The PMOS transistor MP 2  is coupled between the first node n 1 C and the second node n 2 C, and a gate of the PMOS transistor MP 2  is coupled to the second node n 2 C. The NMOS transistor MN 3  is coupled between the first node n 1 C and the ground VSS, and a gate of the NMOS transistor MN 3  is coupled to the first node n 1 C. Furthermore, the bulks of the PMOS transistors MP 1  and MP 2  are coupled to the power supply VDD, and the bulks of the NMOS transistors MN 1  and MN 3  are coupled to the ground VSS. 
       FIG.  5 B  shows a top view of the capacitor cell  100 C of  FIG.  5 A , in accordance with some embodiments of the disclosure, and  FIG.  5 C  shows a cross-sectional view along line C-CC of  FIG.  5 B . 
     In  FIG.  5 B  and  FIG.  5 C , configurations of the PMOS transistors MP 1  and MP 2  are similar to that of the PMOS transistors MP 1  and MP 2  in  FIG.  2 A  and  FIG.  2 B . Furthermore, configurations of the NMOS transistors MN 1  and MN 3  are similar to that of the NMOS transistors MN 1  and MN 3  in  FIG.  4 A  and  FIG.  4 B . For simplicity, the configurations of the PMOS transistors MP 1  and MP 2  and the NMOS transistors MN 1  and MN 3  will not be described. 
       FIG.  6 A  shows a capacitor cell  100 D, which may serve as a de-coupling capacitor, in accordance with some embodiments of the disclosure. The capacitor cell  100 D is capable of providing capacitance for decreasing noise in the power supply. 
     The capacitor cell  100 D includes a PMOS transistor MP 1  coupled between a power supply VDD and a first node n 1 D and an NMOS transistor MN 1  coupled between a ground VSS and the node n 2 D. A gate of the PMOS transistor MP 1  is coupled to a second node n 2 D, and a gate of the NMOS transistor MN 1  is coupled to the first node n 1 D. The PMOS transistor MP 1  and the NMOS transistor MN 1  form a cross-coupled de-coupling structure for increasing the ESD protection and decreasing gate leakage current. 
     The capacitor cell  100 D further includes a PMOS transistor MP 3  in which MP 3  is formed by MP 3 _ 1  and MP 3 _ 2  coupled in parallel, and an NMOS transistor MN 2 . The PMOS transistor MP 3  is coupled between the power supply VDD and the second node n 2 D, and a gate of the PMOS transistor MP 3  is coupled to the second node n 2 D. The NMOS transistor MN 2  is coupled between the first node n 1 D and the second node n 2 D, and a gate of the NMOS transistor MN 2  is coupled to the first node n 1 D. Furthermore, the bulks of the PMOS transistors MP 1  and MP 3  are coupled to the power supply VDD, and the bulks of the NMOS transistors MN 1  and MN 2  are coupled to the ground VSS. 
       FIG.  6 B  shows a top view of the capacitor cell  100 D of  FIG.  6 A , in accordance with some embodiments of the disclosure, and  FIG.  6 C  shows a cross-sectional view along line D-DD of  FIG.  6 B . 
     In  FIG.  6 B  and  FIG.  6 C , configurations of the PMOS transistors MP 1  and MP 3  are similar to that of the PMOS transistors MP 1  and MP 3  in  FIG.  4 A  and  FIG.  4 B . Furthermore, configurations of the NMOS transistors MN 1  and MN 2  are similar to that of the NMOS transistors MN 1  and MN 2  in  FIG.  2 A  and  FIG.  2 B . For simplicity, the configurations of the PMOS transistors MP 1  and MP 3  and the NMOS transistors MN 1  and MN 2  will not be described. 
     A latch-up is a type of short circuit which can occur in an integrated circuit (IC). More specifically it is the inadvertent creation of a low-impedance path that causes high currents conducted between the power supply VDD and the ground VSS via a parasitic structure (e.g. a PNPN structure) in the IC. Latch-up may cause the IC to cease functioning and even to be destroyed. The parasitic PNPN structure acts as a PNP transistor and an NPN transistor stacked next to each other. When one of the PNP and NPN transistors is conducting, the other one begins conducting too, and an undesired latch-up occurs. Then the PNP and NPN transistors keep each other in saturation for as long as the structure is forward-biased and high current flows through the parasitic PNPN structure. In the embodiments, the capacitor cells  100 A- 100 D can form the low resistance paths for enhancing latch-up immunity, and the low resistance paths will be described below. 
       FIG.  7 A  shows a power noise triggered equivalent circuit of a semiconductor-controlled rectifier (SCR)  300 A in the capacitor cell  100 A of  FIG.  1   , and  FIG.  7 B  shows a cross-sectional view illustrating the SCR  300 A of  FIG.  7 A . 
     Referring to  FIG.  7 A  and  FIG.  7 B  together, the SCR  300 A includes two bipolar junction transistors (BJTs) Q 1  and Q 2 , and the resistors Rw and Rs. The BJT Q 1  is a PNP bipolar transistor formed by the P+ doped region  150 A (e.g. the source region S of the PMOS transistor MP 1 ), the N-type well  110 , and the P-type substrate  115 . The BJT Q 2  is an NPN bipolar transistor formed by the N-type well  110 , the P-type substrate  115 , and the N+ doped region  140 A (e.g. the source region S of the NMOS transistor MN 1 ). The resistor Rw represents an equivalent resistance of the N-type well  110 , and the resistor Rs represents an equivalent resistance of P-type substrate  115 . 
     When the base-emitter junction of the BJT Q 1  is forward-biased by a current or voltage noise from the power supply VDD, the BJT Q 1  is turned on, and causes a collector current I 1  of the BJT Q 1 . If the current I 1  is large enough to turn on the BJT Q 2 , more current will be injected into the base region of the BJT Q 1 . Therefore, the BJTs Q 1  and Q 2  are in saturation mode and facilitate high current conduction from the power supply VDD to the ground VSS. 
     By adding the PMOS transistor MP 2  and the NMOS transistors MN 2  in the cross-coupled de-coupling structure formed by the PMOS transistor MP 1  and the NMOS transistor MN 1  in the capacitor cell  100 A, a low resistance path Path 1  is formed to discharge minority carriers in the base region of the BJTs Q 1  and Q 2  in the SCR  300 A, and the resistor R Path1  represents an equivalent resistance of the low resistance path Path 1 . When the BJT Q 1  is turned on, a shunting current I 2  is provided by the active collector of the BJT Q 1  to discharge minority carriers injected by the base-emitter junction of the BJT Q 1 , thereby the current I 1  from the BJT Q 1  is decreased. Therefore, it uses higher collector current to turn on the BJT Q 2 . Furthermore, the base-emitter voltage V BE  of the BJT Q 1  for turning on the SCR  300 A is increased. 
     In some embodiments, the low resistance path Path 1  is provided by an N-channel conduction of one or more NMOS transistors within an array of transistors in the P-type well  120  via the source region Sc and/or the drain region Dc of one or more PMOS transistors within an array of transistors in the N-type well  110 . 
     Taking the capacitor cell  100 A having the source region Sc (e.g. P+ doped region  150 C) in the N-type well  110  as an example, the low resistance path Path 1  is formed from the N-type well  110  to the ground VSS through the P+ doped region  150 C, the second node n 2 A, the N+ doped region  140 B, the active region (e.g. N-channel) corresponding to the gate metal  220 A, and the N+ doped region  140 A in sequence. Therefore, the source region Sc or the drain region Dc of the PMOS transistor coupled to the drain region D of the NMOS transistor will form the low resistance path Path 1  to discharge minority carriers in the base region of the BJT Q 1 , thereby the holding voltage and the trigger current that cause latch-up can be increased for latch-up protection, and the latch-up immunity is improved. 
       FIG.  8 A  shows a ground noise triggered equivalent circuit of a SCR  300 B in the capacitor cell  100 A of  FIG.  1   , and  FIG.  8 B  shows a cross-sectional view illustrating the SCR  300 B of  FIG.  8 A . 
     Referring to  FIG.  8 A  and  FIG.  8 B  together, when the base-emitter junction of the BJT Q 2  is forward-biased by a current or voltage noise from the ground VSS, the BJT Q 2  is turned on, and causes a collector current I 3  of the BJT Q 2 . If the current I 3  is large enough to turn on the BJT Q 1 , more current will be injected into the base region of the BJT Q 2 . Therefore, the BJTs Q 1  and Q 2  are in saturation mode and facilitate high current conduction from the power supply VDD to the ground VSS. 
     By adding the PMOS transistor MP 2  and the NMOS transistors MN 2  in the cross-coupled de-coupling structure formed by the PMOS transistor MP 1  and the NMOS transistor MN 1  in the capacitor cell  100 A, a low resistance path Path 2  is formed to discharge minority carriers in the base region of the BJTs Q 1  and Q 2  in the SCR  300 B, and the resistor R Path2  represents an equivalent resistance of the low resistance path Path 2 . When the BJT Q 2  is turned on, a shunting current I 4  is provided by the active collector of the BJT Q 2  to discharge minority carriers injected by the base-emitter junction of the BJT Q 2 , thereby the current I 3  from the BJT Q 2  is decreased. Therefore, it requires higher collector current to turn on the BJT Q 1 . Furthermore, the required base-emitter voltage V BE  of the BJT Q 2  for turning on the SCR  300 B is increased. 
     In some embodiments, the low resistance path Path 2  is provided by a P-channel conduction of one or more PMOS transistors within an array of transistors in the N-type well  110  via the source region Sc and/or the drain region Dc of one or more NMOS transistors within an array of transistors in the P-type well  120 . 
     Taking the capacitor cell  100 A having the source region Sc (e.g. N+ doped region  140 C) in the P-type well  120  as an example, the low resistance path Path 2  is formed from the P-type well  120  to the power supply VDD through the N+ doped region  140 C, the first node n 1 A, the P+ doped region  150 B, the active region (e.g. P-channel) corresponding to the gate metal  210 A, and the P+ doped region  150 A in sequence. Therefore, the source region Sc or the drain region Dc of the NMOS transistor coupled to the drain region D of the PMOS transistor will form the low resistance path Path 2  to discharge minority carriers in the base region of the BJT Q 2 , thereby the holding voltage and the trigger current that cause latch-up can be increased for latch-up protection, and the latch-up immunity is improved. 
     For the PMOS transistor MP 1  in the N-type well  110  and the NMOS transistor MN 1  in the P-type well  120 , the gates of the PMOS transistor MP 1  and the NMOS transistor MN 1  are coupled to the drains of the NMOS transistor MN 1  and the PMOS transistor MP 1 , respectively. Both the source region S and the bulk of the PMOS transistor MP 1  are coupled to the power supply VDD, and both the source region S and the bulk of the NMOS transistor MN 1  are coupled to the ground VSS. The configurations of the PMOS transistor MP 1  and the NMOS transistor MN 1  make it so the gate voltage can turn on the channel-conduction of the transistors, and the channel resistance is series connected with the gate of the PMOS transistor MP 1  and the NMOS transistor MN 1 . Therefore, the MOS capacitance with series channel-resistance is provided to increase the ESD protection and decrease the gate-leakage current for the power supply VDD and the ground VSS. 
     For the PMOS transistors MP 2  and MP 3  in the N-type well  110  and the NMOS transistor MN 2  and MN 3  in the P-type well  120 , the configurations of the source region Sc and the drain region Dc can provide embedded P+ and N+ active collectors in the N-type well  110  and the P-type well  120 , respectively. For the P+ active collector in the PMOS transistors MP 2  and MP 3 , the source region Sc or the drain region Dc in the N-type well  110  is coupled to the ground VSS through the low resistance path (e.g. Path 1  of  FIG.  7 B ), and the low resistance path can be n-channel conduction in the NMOS transistor MN 1 . Similarly, For the N+ active collector in the NMOS transistors MN 2  and MN 3 , the source region Sc or the drain region Dc in the P-type well  120  is coupled to the power supply VDD through the low resistance path (e.g. Path 2  of  FIG.  8 B ), and the low resistance path can be P-channel conduction in the PMOS transistor MP 1 . Therefore, the high-conductive paths are provided to discharge minority carriers in the base region of BJT Q 1  and Q 2  in the parasitic PNPN structure. Consequently, the active collectors form the shunting paths from the base regions of the BJT Q 1 /Q 2  to the ground VSS and the power supply VDD. The shunting paths can improve the required base-emitter voltage of the BJT Q 1 /Q 2  for turning on the SCR structure, thereby avoiding the undesired latch-up. Therefore, the intrinsic latch-up immunity of the capacitor cell is enhanced and the holding voltage and trigger current of the SCR are increased in the ICs. 
     Embodiments for capacitor cells and structures thereof are provided. The capacitor cell has a cross-coupled de-coupling structure formed by the PMOS transistor MP 1  and the NMOS transistor MN 1 , and the cross-coupled de-coupling structure is capable of providing the MOS capacitance for reducing the power supply noise. Furthermore, the capacitor cells further have two types of source/drain configurations, e.g. S/D and Sc/Dc capable of providing greater robustness against ESD stress and Latch-up. The source/drain configuration S/D provides the channel-conduction resistance to connect with the MOS capacitance, which can improve the ESD level and reduce the gate-leakage. Furthermore, the source/drain configuration Sc/Dc provides embedded active collectors in the well-region of MOS transistors, which can improve the latch-up immunity of capacitor cells. Therefore, the capacitor cell can protect itself from the high current conduction (Latch-up) condition triggered by the noise sources in the power supply lines in an IC. Moreover, the capacitor cell can have lower layout area requirement for latch-up protection schemes such as strap density, spacing between PMOS and NMOS, and quard-rings placement. Consequently, chip area of the IC is decreased. 
     In some embodiments, a capacitor cell is provided. A first PMOS transistor is coupled between a power supply and a first node, and has a gate connected to a second node. A first NMOS transistor is coupled between a ground and the second node, and has a gate connected to the first node. A second PMOS transistor is coupled between the second node and the power supply, and has a gate connected to the second node. A second NMOS transistor is coupled between the first node and the ground, a gate connected to the first node, and has a gate connected to the first node. A first N+ doped region is formed in an N-type well region and coupled to the power supply. A first P+ doped region is formed in a P-type well region and coupled to the ground. A first isolation region is formed between the second PMOS transistor and the first N+ doped region. A second isolation region is formed between the second NMOS transistor and the first P+ doped region. A third isolation region is formed between the P-type well region and the N-type well region. Sources of the first and second PMOS transistors share a second P+ doped region in the N-type well region, and the first PMOS transistor is disposed between the second PMOS transistor and the first and second NMOS transistors. 
     In some embodiments, a capacitor cell is provided. A first PMOS transistor is coupled between a power supply and a first node, and has a gate connected to a second node. A first NMOS transistor is coupled between a ground and the second node, and has a gate connected to the first node. A second PMOS transistor is coupled between the power supply and the second node, and has a gate connected to the second node. A second NMOS transistor is coupled between the first node and the ground, and has a gate connected to the first node. The first and second PMOS transistors on an N-type well region and the first and second NMOS transistors on a P-type well region are arranged in the same row. The second NMOS transistor is formed by a third NMOS transistor and a fourth NMOS transistor coupled in parallel. Sources of the first and third NMOS transistors share a first N+ doped region in the P-type well region, and drains of the third and fourth NMOS transistors share a second N+ doped region in the P-type well region. 
     In some embodiments, a capacitor cell is provided. An N-type well region is formed on a semiconductor substrate. A P-type well region is formed on the semiconductor substrate, and the P-type well region is in contact with the N-type well region. A first P+ doped region is formed in the N-type well region and coupled to a power line. A second P+ doped region is formed in the N-type well region. A first active region is formed between the first and second P+ doped regions in the N-type well region. A first N+ doped region is formed in the P-type well region and coupled to a ground. A second N+ doped region is formed in the P-type well region and coupled to the first active region. A second active region is formed between the first and second N+ doped regions in the P-type well region and coupled to the second P+ doped region. A third N+ doped region is formed in the P-type well region and coupled to the second active region. A fourth N+ doped region is formed in the N-type well region and coupled to the power line. A third P+ doped region is formed in the P-type well region and coupled to the ground. A first isolation region is formed between the first P+ doped region and the fourth N+ doped region. A second isolation region is formed between the first N+ doped region and the third P+ doped. A third isolation region is formed between the P-type well region and the N-type well region. A first discharge path is formed from the P-type well region to the power line through the third N+ doped region, the second P+ doped region, the first active region, and the first P+ doped region in sequence. 
     The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.