Patent Publication Number: US-11664774-B2

Title: Operational amplifier using single-stage amplifier with slew-rate enhancement and associated method

Description:
CROSS REFERENCE TO RELATED APPLICATION 
     This application is a continuation application of U.S. application Ser. No. 16/921,922, filed on Jul. 6, 2020, which claims the benefit of U.S. Provisional Application No. 62/898,121, filed on Sep. 10, 2019. The contents of these applications are incorporated herein by reference. 
    
    
     BACKGROUND 
     The present invention relates to amplifying an input signal to generate an output signal, and more particularly, to an operational amplifier using a single-stage amplifier with slew-rate enhancement (e.g., Class-AB slew-rate enhancement) and an associated method. 
     It will be appreciated that, generally speaking, the most efficient type of operational amplifier is a single-stage amplifier with a single pole. High bandwidth and low noise can be easily implemented by the single-stage amplifier. However, the single-stage amplifier has limitations in slew rate. The slew rate of an operational amplifier represents the maximum rate of change of a signal at any point in the circuit. In other words, limitations in slew rate may result in non-linear effects that may significantly distort an amplifier output if an amplifier input is at a frequency exceeding the slew rate limitation of the operational amplifier. 
     SUMMARY 
     One of the objectives of the claimed invention is to provide an operational amplifier using a single-stage amplifier with slew-rate enhancement (e.g., Class-AB slew-rate enhancement) and an associated method. 
     According to a first aspect of the present invention, an exemplary operational amplifier is disclosed. The exemplary operational amplifier includes a single-stage amplifier and a current controller. The single-stage amplifier is arranged to receive an input signal and amplify the input signal to generate an output signal, wherein the single-stage amplifier comprises a voltage controlled current source circuit that operates in response to a bias voltage input. The current controller, coupled to the voltage controlled current source circuit, wherein the current controller is arranged to receive the input signal, and generate the bias voltage input according to the input signal. The bias voltage input includes a first bias voltage, a second bias voltage, a third bias voltage, and a fourth bias voltage. None of the first bias voltage, the second bias voltage, the third bias voltage, and the fourth bias voltage is directly set by the input signal of the single-stage amplifier. 
     According to a second aspect of the present invention, an exemplary signal amplification method is disclosed. The exemplary signal amplification method includes: generating a bias voltage input according to an input signal; and amplifying, by a single-stage amplifier, the input signal to generate an output signal, wherein the single-stage amplifier comprises a voltage controlled current source circuit that operates in response to the bias voltage input. The bias voltage input includes a first bias voltage, a second bias voltage, a third bias voltage, and a fourth bias voltage. None of the first bias voltage, the second bias voltage, the third bias voltage, and the fourth bias voltage is directly set by the input signal of the single-stage amplifier. 
     These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG.  1    is a diagram illustrating an operational amplifier according to an embodiment of the present invention. 
         FIG.  2    is a diagram illustrating a telescopic amplifier according to an embodiment of the present invention. 
         FIG.  3    is a diagram illustrating a current controller according to an embodiment of the present invention. 
         FIG.  4    is a diagram illustrating the current controller shown in  FIG.  3    that operates under a condition that a voltage level of a positive signal is lower than a voltage level of a negative signal. 
         FIG.  5    is a diagram illustrating the telescopic amplifier shown in  FIG.  2    that operates under a condition that the voltage level of the positive signal is lower than the voltage level of the negative signal. 
         FIG.  6    is a diagram illustrating the current controller shown in  FIG.  3    that operates under a condition that the voltage level of the positive signal is higher than the voltage level of the negative signal. 
         FIG.  7    is a diagram illustrating the telescopic amplifier shown in  FIG.  2    that operates under a condition that the voltage level of the positive signal is higher than the voltage level of the negative signal. 
         FIG.  8    is a diagram illustrating a common-mode feedback circuit according to an embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION 
     Certain terms are used throughout the following description and claims, which refer to particular components. As one skilled in the art will appreciate, electronic equipment manufacturers may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not in function. In the following description and in the claims, the terms “include” and “comprise” are used in an open-ended fashion, and thus should be interpreted to mean “include, but not limited to . . . ”. Also, the term “couple” is intended to mean either an indirect or direct electrical connection. Accordingly, if one device is coupled to another device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections. 
       FIG.  1    is a diagram illustrating an operational amplifier according to an embodiment of the present invention. The operational amplifier  100  includes a single-stage amplifier  102 , a current controller  104 , and a common-mode feedback circuit (CMFB)  106 . The common-mode feedback circuit  106  may be optional. For example, when the single-stage amplifier  102  is a single-ended amplifier, the common-mode feedback circuit  106  may be omitted. For better understanding of technical features of the present invention, the following assumes that the single-stage amplifier  102  is a fully differential amplifier. 
     The single-stage amplifier  102  is arranged to receive an input signal and amplify the input signal to generate an output signal. For example, the single-stage amplifier  102  is a differential amplifier, such that the input signal is a differential signal consisting of a positive signal IN+ and a negative signal IN−, and the output signal is a differential signal consisting of a positive signal OUT+ and a negative signal OUT−. In some embodiments of the present invention, the single-stage amplifier  102  may be implemented by a telescopic amplifier. 
       FIG.  2    is a diagram illustrating a telescopic amplifier according to an embodiment of the present invention. The single-stage amplifier  102  shown in  FIG.  1    may be implemented by the telescopic amplifier  200  shown in  FIG.  2   . As shown in  FIG.  2   , the telescopic amplifier  200  includes P-channel metal-oxide semiconductor (PMOS) transistors MP 1 , MP 2 , MP 3 , MP 4 , MP 5 , MP 6  and N-channel metal-oxide semiconductor (NMOS) transistors MN 1 , MN 2 , MN 3 , MN 4 , MN 5 , MN 6 . The PMOS transistors MP 1 , MP 3 , MP 5  and NMOS transistors MN 1 , MN 3 , MN 5  are cascoded between two reference voltages including a supply voltage VDD and a ground voltage GND, where VDD&gt;GND. In addition, the PMOS transistors MP 2 , MP 4 , MP 6  and NMOS transistors MN 2 , MN 4 , MN 6  are cascoded between two reference voltages including the supply voltage VDD and the ground voltage GND. 
     A source node of the PMOS transistor MP 1  is arranged to receive one reference voltage (e.g., supply voltage VDD), and a gate node of the PMOS transistor MP 1  is arranged to receive a bias voltage VTP 1 . A source node of the PMOS transistor MP 2  is arranged to receive one reference voltage (e.g., supply voltage VDD), and a gate node of the PMOS transistor MP 2  is arranged to receive a bias voltage VTP 2 . A source node of the NMOS transistor MN 1  is arranged to receive another reference voltage (e.g., ground voltage GND), and a gate node of the NMOS transistor MN 1  is arranged to receive a bias voltage VTN 1 . A source node of the NMOS transistor MN 2  is arranged to receive another reference voltage (e.g., ground voltage GND), and a gate node of the NMOS transistor MN 2  is arranged to receive a bias voltage VTN 2 . 
     A gate node of the PMOS transistor MP 3  is arranged to receive a positive signal P+ (P+=IN+), and a gate node of the PMOS transistor MP 4  is arranged to receive a negative signal P− (P−=IN−), where the positive signal P+ and the negative signal P− form one differential signal. In addition, a gate node of the NMOS transistor MM 3  is arranged to receive a positive signal N+ (N+=IN+), and a gate node of the NMOS transistor MN 4  is arranged to receive a negative signal N− (N−=IN−), where the positive signal N+ and the negative signal N− form one differential signal. As shown in  FIG.  1   , the positive signals P+ and N+ are derived from the same positive signal IN+ via coupling capacitors C 1  and C 2 , and the negative signals P− and N− are derived from the same negative signal IN− via coupling capacitors C 3  and C 4 . Ideally, coupling capacitors C 1 -C 4  may be identical capacitors. 
     A gate node of the PMOS transistor MP 5  and a gate node of the NMOS transistor MN 5  are arranged to receive bias voltages Vbp 1  and Vbn 1 , respectively, and a drain node of the PMOS transistor MP 5  and a drain node of the NMOS transistor MN 5  are both coupled to the negative signal OUT− of the differential amplifier output. In addition, a gate node of the PMOS transistor MP 6  and a gate node of the NMOS transistor MN 6  are arranged to receive bias voltages Vbp 2  and Vbn 2 , respectively, and a drain node of the PMOS transistor MP 6  and a drain node of the NMOS transistor MN 6  are both coupled to the positive signal OUT+ of the differential amplifier output. 
     The telescopic amplifier  200  has a voltage controlled current source  202 , where the voltage controlled current source  202  includes a top current source  204  and a tail current source  206 . The voltage controlled current source  202  operates in response to a bias voltage input that includes bias voltages VTP 1 , VTP 2 , VTN 1 , and VTN 2 , where the top current source  204  is controlled by bias voltages VTP 1  and VTP 2 , and the tail current source  206  is controlled by bias voltages VTN 1  and VTN 2 . In this embodiment, the current controller  104  shown in  FIG.  1    is coupled to the voltage controlled current source circuit  202 , and is arranged to receive the input signal (which includes positive signal IN+ and negative signal IN−, where IN+=P+=N+ and IN−=P−=N−), and generate the bias voltage input (which includes bias voltages VTP 1 , VTP 2 , VTN 1 , and VTN 2 ) according to the input signal (which includes positive signal IN+ and negative signal IN−, where IN+=P+=N+ and IN−=P−=N−). Hence, the bias voltage input {VTP 1 , VTP 2 , VTN 1 , VTN 2 } is not fixed, and is dynamically adjusted in response to the input signal {IN+, IN−}. 
       FIG.  3    is a diagram illustrating a current controller according to an embodiment of the present invention. The current controller  104  shown in  FIG.  1    may be implemented by the current controller  300 . The bias voltage input dynamically adjusted by the current controller  300  enables Class-AB slew-rate enhancement for the voltage controlled current source circuit  202  of the telescopic amplifier  200  that is a single-stage amplifier. 
     Please refer to  FIG.  4    in conjunction with  FIG.  5   .  FIG.  4    is a diagram illustrating the current controller  300  operating under a condition that a voltage level of the positive signal IN+ is lower than a voltage level of the negative signal IN−.  FIG.  5    is a diagram illustrating the telescopic amplifier  200  operating under a condition that the voltage level of the positive signal IN+ is lower than the voltage level of the negative signal IN−. Suppose that the single-stage amplifier  102  shown in  FIG.  1    is implemented by the telescopic amplifier  200  shown in  FIG.  2   , and the current controller  104  shown in  FIG.  1    is implemented by the current control  300  shown in  FIG.  3   . When the voltage level of the positive signal IN+ becomes lower than the voltage level of the negative signal IN−, a voltage level of the positive signal P+ and a voltage level of the positive signal N+ are decreased, and a voltage level of the negative signal P− and a voltage level of the negative signal N− are increased. Hence, a voltage at a gate node of the PMOS transistor MP 7  shown in  FIG.  4    is decreased and a voltage at a gate node of the NMOS transistor MN 7  shown in  FIG.  4    is decreased due to IN+=P+=N+, and a voltage at a gate node of the PMOS transistor MP 8  shown in  FIG.  4    is increased and a voltage at a gate node of the NMOS transistor MN 8  shown in  FIG.  4    is increased due to IN−=P−=N−. The current passing through the PMOS transistor MP 7  is increased, while the PMOS transistor MP 8  may be turned off. In addition, the current passing through the NMOS transistor MN 8  is increased, while the NMOS transistor MN 7  may be turned off. Hence, the bias voltages VTP 1  and VTN 1  are pushed up, and the bias voltages VTP 2  and VTN 2  are pulled down. To put it simply, when the voltage level of the positive signal IN+ is lower than the voltage level of the negative signal IN−, the current controller  300  is arranged to increase the bias voltages VTP 1  and VTN 1  and decrease the bias voltages VTP 2  and VTN 2 . 
     As shown in  FIG.  5   , the PMOS transistor MP 1  may be turned off due to the increased bias voltage VTP 1 , the PMOS transistor MP 4  may be turned off due to the increased voltage of the positive signal P−, the NMOS transistor MN 3  may be turned off due to the decreased voltage of the positive signal N+, and the NMOS transistor MN 2  may be turned off due to the decreased bias voltage VTN 2 . An output node of the negative signal OUT− may drain large current IP 1  from the supply voltage VDD due to the decreased bias voltage VTP 2  at the gate node of the PMOS transistor MP 2  and the decreased voltage of the positive signal P+ at the gate node of the PMOS transistor MP 3 . In addition, large current IN 1  is drained from an output node of the positive signal OUT+ to the ground voltage GND due to the increased bias voltage VTN 1  at the gate node of the NMOS transistor MN 1  and the increased voltage of the negative signal N− at the gate node of the NMOS transistor MN 4 . The bias voltages VTP 1 , VTP 2 , VTN 1 , and VTN 2  are not fixed, and are dynamically adjusted by the current controller  300 . With the help of the current controller  300 , large current IP 1  and IN 1  can be provided to enhance the slew rate of the telescopic amplifier  200  under a condition that the voltage level of the positive signal IN+ is lower than the voltage level of the negative signal IN−. 
     Please refer to  FIG.  6    in conjunction with  FIG.  7   .  FIG.  6    is a diagram illustrating the current controller  300  operating under a condition that a voltage level of the positive signal IN+ is higher than a voltage level of the negative signal IN−.  FIG.  7    is a diagram illustrating the telescopic amplifier  200  operating under a condition that the voltage level of the positive signal IN+ is higher than the voltage level of the negative signal IN−. Suppose that the single-stage amplifier  102  shown in  FIG.  1    is implemented by the telescopic amplifier  200  shown in  FIG.  2   , and the current controller  104  shown in  FIG.  1    is implemented by the current control  300  shown in  FIG.  3   . When the voltage level of the positive signal IN+ becomes higher than the voltage level of the negative signal IN−, a voltage level of the positive signal P+ and a voltage level of the positive signal N+ are increased, and a voltage level of the negative signal P− and a voltage level of the negative signal N− are decreased. Hence, a voltage at a gate node of the PMOS transistor MP 7  shown in  FIG.  6    is increased and a voltage at a gate node of the NMOS transistor MN 7  shown in  FIG.  6    is increased due to IN+=P+=N+, and a voltage at a gate node of the PMOS transistor MP 8  shown in  FIG.  6    is decreased and a voltage at a gate node of the NMOS transistor MN 8  shown in  FIG.  6    is decreased due to IN−=P−=N−. The current passing through the PMOS transistor MP 8  is increased, while the PMOS transistor MP 7  may be turned off. In addition, the current passing through the NMOS transistor MN 7  is increased, while the NMOS transistor MN 8  may be turned off. Hence, the bias voltages VTP 1  and VTN 1  are pulled down, and the bias voltages VTP 2  and VTN 2  are pushed up. To put it simply, when the voltage level of the positive signal IN+ is higher than the voltage level of the negative signal IN−, the current controller  300  is arranged to decrease the bias voltages VTP 1  and VTN 1  and increase the bias voltages VTP 2  and VTN 2 . 
     As shown in  FIG.  7   , the PMOS transistor MP 2  may be turned off due to the increased bias voltage VTP 2 , the PMOS transistor MP 3  may be turned off due to the increased voltage of the positive signal P+, the NMOS transistor MN 4  may be turned off due to the decreased voltage of the negative signal N−, and the NMOS transistor MN 1  may be turned off due to the decreased bias voltage VTN 1 . An output node of the positive signal OUT+ may drain large current IP 2  from the supply voltage VDD due to the decreased bias voltage VTP 1  at the gate node of the PMOS transistor MP 1  and the decreased voltage of the positive signal P− at the gate node of the PMOS transistor MP 4 . In addition, large current IN 2  is drained from an output node of the negative signal OUT− to the ground voltage GND due to the increased bias voltage VTN 2  at the gate node of the NMOS transistor MN 2  and the increased voltage of the positive signal N+ at the gate node of the NMOS transistor MN 3 . The bias voltages VTP 1 , VTP 2 , VTN 1 , and VTN 2  are not fixed, and are dynamically adjusted by the current controller  300 . With the help of the current controller  300 , large current IP 2  and IN 2  can be provided to enhance the slew rate of the telescopic amplifier  200  under a condition that the voltage level of the positive signal IN+ is higher than the voltage level of the negative signal IN−. 
     In this embodiment, PMOS transistors MP 1 , MP 2  and NMOS transistors MN 1 , MN 2  shown in  FIG.  2    are biased via a floating gate current source of the current controller  300  shown in  FIG.  3   . As shown in  FIG.  5    and  FIG.  7   , the class-AB control includes PMOS transistors MP 3 , MP 4  and NMOS transistors MN 3 , MN 4 , and operates in response to the input signal {IN+=P+=N+, IN−=P−=N−}. As shown in FIG. and  FIG.  6   , the floating gate current source includes PMOS transistors MP 7 , MP 8  and NMOS transistors MN 7 , MN 8 , and operates in response to the input signal {IN+=P+=N+, IN−=P−=N−}. The floating gate current source has the same structure and the same supply voltage dependency as the class-AB control, resulting in quiescent currents of PMOS transistors MP 1 , MP 2  and NMOS transistors MN 1 , MN 2  which are independent of the supply voltage. 
     When the single-stage amplifier  102  is implemented by a fully differential amplifier, the common-mode feedback circuit  106  may be employed to minimize an offset of a common-mode voltage of a differential output {OUT+, OUT−} generated from the single-stage amplifier  102 .  FIG.  8    is a diagram illustrating a common-mode feedback circuit according to an embodiment of the present invention. The common-mode feedback circuit  106  shown in  FIG.  1    may be implemented by the common-mode feedback circuit  800 . The common-mode feedback circuit  800  is arranged to monitor a common-mode voltage of the positive signal OUT+ and the negative signal OUT−, and compare the common-mode voltage with a reference voltage VCM to generate a feedback control voltage VFBP. For example, the reference voltage VCM may be equal to half of the supply voltage VDD. Considering a case where the current controller  104  is implemented by the current controller  300  shown in  FIG.  3   , the current controller  300  includes a PMOS transistor MP 9 , and a gate node of the PMOS transistor MP 9  is arranged to receive the feedback control voltage VFBP generated from the common-mode feedback circuit  800 . In other words, the current controller  300  is further arranged to receive the feedback control voltage VFBP, and affect the bias voltage input {VTP 1 , VTP 2 , VTN 1 , VTN 2 } in response to the feedback control voltage VFBP. 
     Considering a case where the common-mode voltage is higher than the reference voltage VCM, the feedback control voltage VFBP is decreased by the common-mode feedback circuit  800 , and current passing through the PMOS transistor MP 9  of the current controller  300  is increased, thereby further increasing the bias voltages VTP 1 , VTP 2 , VTN 1 , and VTN 2 . With regard to the scenario shown in  FIG.  5   , the current IP 1  passing through the PMOS transistor MP 2  is decreased, while the current IN 1  passing through the NMOS transistor MN 4  is increased. With regard to the scenario shown in  FIG.  7   , the current IP 2  passing through the PMOS transistor MP 1  is decreased, while the current IN 2  passing through the NMOS transistor MN 2  is increased. In each of the scenarios, the common-mode voltage is decreased. 
     Considering another case where the common-mode voltage is lower than the reference voltage VCM, the feedback control voltage VFBP is increased by the common-mode feedback circuit  800 , and current passing through the PMOS transistor MP 9  of the current controller  300  is decreased, thereby further decreasing the bias voltages VTP 1 , VTP 2 , VTN 1 , and VTN 2 . With regard to the scenario shown in  FIG.  5   , the current IP 1  passing through the PMOS transistor MP 2  is increased, while the current IN 1  passing through the NMOS transistor MN 4  is decreased. With regard to the scenario shown in  FIG.  7   , the current IP 2  passing through the PMOS transistor MP 1  is increased, while the current IN 2  passing through the NMOS transistor MN 2  is decreased. In each of the scenarios, the common-mode voltage is increased. 
     The common-mode feedback circuit  800  may include an optional Miller compensation circuit that is coupled between the output signal {OUT+, OUT-} and the bias voltage input {VTP 1 , VTP 2 , VTN 1 , VTN 2 } for stability compensation of common-mode feedback loop. In this embodiment, the Miller compensation circuit may include Miller capacitors CM 5 , CM 6 , CM 7 , CM 8 , CM 9 , CM 10 , CM 11 , and CM 12 . In addition, Miller compensation may also be applied to the single-stage amplifier  102  by using Miller capacitors CM 1 , CM 2 , CM 3 , and CM 4 , as shown in  FIG.  1   . However, these are for illustrative purposes only, and are not meant to be limitations of the present invention. 
     With regard to a typical single-stage amplifier without the proposed Class-AB slew-rate enhancement scheme, it may achieve a high signal-to-noise and distortion ratio (SDNR) (e.g., 106 dB) by consuming large quiescent current (e.g., 4000 uA). Compared to the typical single-stage amplifier, the operational amplifier  100  (which includes the single-stage amplifier  102  with the proposed Class-AB slew-rate enhancement scheme) can achieve a higher SDNR (e.g., 110 dB) by consuming much less quiescent current (e.g., 740 uA), where the quiescent current of the single-stage amplifier  102  may be 640 uA, and the quiescent current of the current controller  104  may be 100 uA. 
     Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.