Patent Publication Number: US-6992444-B2

Title: Plasma display panel including partition wall member

Description:
BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   This invention relates to a panel structure for surface-discharge-type AC plasma display panels. 
   The present application claims priority from Japanese Application No. 2003-137270, the disclosure of which is incorporated herein by reference. 
   2. Description of the Related Art 
   Surface-discharge-type AC plasma display panels (hereinafter referred to as “PDP”) have recently gained the spotlight as types of large-sized slim color display apparatuses and are becoming increasingly common in homes and the like. 
   Such known surface-discharge-type AC PDP includes a three-electrode reflection-type PDP. 
   The structure of the three-electrode reflection-type PDP is described here. The front glass substrate is placed opposite the back glass substrate with a discharge-gas-filled discharge space in between. On the inner surface of the front glass substrate, a plurality of row electrode pairs and a dielectric layer overlying the row electrode pairs are provided. Each of the row electrode pairs is constituted of paired row electrodes (discharge sustaining electrodes) extending in the row direction and arranged parallel to another row electrode pair to form a display line. On the inner surface of the back glass substrate, a plurality of column electrodes (addressing electrodes) extends in the column direction. Discharge cells (unit light emission areas) are provided at each of the intersections of the column electrode and the row electrode pair in the discharge space. Further red-, green-, and blue-colored phosphor layers are provided individually in each discharge cell. 
   For the generation of an image on the three-electrode reflection-type PDP, first, an addressing discharge is caused selectively between the column electrode and one row electrode in the row electrode pair to generate a wall charge on the dielectric layer overlying the row electrode pairs or alternatively to erase the wall charge accumulated thereon. As a result, the discharge cells having the wall charge generated on the dielectric layer (lighted cells) and the discharge cells having no wall charge (non-lighted cells) a redistributed over the panel surface in accordance with the received image signal. After that, in each lighted cell, a sustain discharge is produced between the row electrodes in each row electrode pair. By means of this sustain discharge, vacuum ultraviolet light is emitted from xenon included in the discharge gas, and excites each of the red-, green- and blue-colored phosphor layers formed in the individual lighted cells to emit visible light for the generation of the image in a matrix display. 
   The conventional three-electrode reflection type PDP as structured in this manner is described in Japanese Patent Laid-open Application No. 10-321145. 
   The conventional structure of the three-electrode reflection-type PDP as described above requires a complicated manufacturing process for forming the electrodes separately on the front glass substrate and the back glass substrate, and a high degree of accuracy of the positional relationship of the electrodes between the front glass substrate and the back glass substrate. Therefore, this conventional PDP has the problem of the entailing high manufacturing costs and a further increase in costs due to the large number of components formed on each substrate. 
   On this account, a PDP having the row electrodes and the column electrodes both formed on a single glass substrate has been proposed for the achievement of cost cutting and of a finer resolution of the image display. 
   In the proposed PDP, a glass substrate placed opposite another glass substrate having a phosphor layer formed thereon has the double-layer structure of the row electrode pairs and the column electrodes which extend in a direction at right angles to the row electrode pairs being formed with the dielectric layer in between. 
     FIG. 1  is a front view showing the structure of a conventional PDP having the row electrode pairs and the column electrodes both formed on a single substrate. 
   In  FIG. 1 , on the inner surface of one of the substrates (not shown) of the PDP, row electrode pairs (X, Y) each constituted of the paired row electrodes X and Y extend in the row direction and are regularly arranged in plurality in the column direction. The row electrode pairs (X, Y) are covered with a first dielectric layer (not shown). On the inner surface of the first dielectric layer, bodies Da of a plurality of column electrodes D extend in the column direction and are arranged at regular intervals in the row direction. The bodies Da of the column electrodes D are covered with a second dielectric layer (not shown). 
   Each of the column electrodes D has discharge portions Db formed in the first dielectric layer, so that each of the discharge portions Db is flush with and opposite the row electrode X or Y of the row electrode pair (X, Y) to cause an addressing discharge in association therewith. 
   Discharge cells C are formed in each position opposite the area surrounded by the paired row electrodes X and Y and the two bodies Da of the adjacent column electrodes D, inside a discharge space defined between the two substrates. 
   Each of the row electrode pairs (X, Y) forms a display line L. 
   The foregoing surface-discharge-type AC PDP generates images as follows. 
   In a reset period, a reset discharge is produced simultaneously in each discharge cell C between one row electrode in the row electrode pair (X, Y) (in this case, the row electrode Y) and the discharge portion Db of the column electrode D. Then in the subsequent addressing period, an addressing discharge is produced selectively in the discharge cells C between the row electrode Y and the discharge portion Db of the column electrode D, whereby the lighted cells (the discharge cells C having wall charges generated on the dielectric layer) and the non-lighted cells (the discharge cells C having no wall charges generated on the dielectric layer) are distributed over the panel surface in accordance with the image to be displayed. 
   After the completion of the addressing period, a discharge-sustaining pulse is alternately applied, simultaneously in all the display lines L, to the row electrodes X and Yin each row electrode pair. Thereupon, due to the wall charges accumulated on the dielectric layer, a sustain discharge is produced between the row electrodes X and Y in each lighted cell with every application of the discharge-sustaining pulse. 
   As a result of the sustain discharge, ultraviolet light is generated from the discharge gas in each light cell, and excites each of the red (R), green (G) and blue (B) colored phosphor layers formed in the individual discharge cells C, to emit visible light for the generation of the images. 
   The conventional surface-discharge-type AC PDP structured as described hitherto has the following problems. 
   The reset discharge, the addressing discharge and the sustain discharge are all produced in the same discharge cell. Under these circumstances, the reset discharge and the addressing discharge excite the red (R), green (G) and blue (B) phosphor layers and therefore light emission from the phosphor is repeated. This light emission raises the brightness level when the display is black, which is a factor that lowers the light-dark contrast. 
   Further, the sustain discharge for visible light emission must be produced in the same discharge cell as that in which the reset discharge and addressing discharge preparatory to the light emission are produced. When the cell structure is designed, the necessity for compatibility between those discharges gives rise to considerable restrictions. This involves the problem of difficulties arising in providing the adequate discharge characteristics in any discharge. 
   In addition, in the conventional PDP, the addressing discharge produced in the same discharge cell C as that in which the sustain discharge is produced is affected by: the discharge characteristics varying among the individual phosphor materials of the colors of the phosphor layers formed in the respective discharge cells C; the change in discharge voltage traceable to the phosphor layers, for example, that is caused by variations in the layer thickness of the phosphor layers occurring when the phosphor layers are formed in the manufacturing process; and the like. For this reason, the conventional PDP has the problem of significant difficulties arising in providing equal addressing discharge characteristics in all the discharge cells C. 
   SUMMARY OF THE INVENTION 
   The present invention is essentially designed to solve the problems associated with the conventional surface-discharge-type AC plasma display panels as described hitherto. 
   It is, therefore, an object of the present invention to provide a plasma display panel having row electrode pairs and column electrodes formed on a single substrate, and capable of making the addressing discharge characteristics in all discharge cells uniform and improving the dark-light contrast. 
   To achieve this object, the plasma display panel according to the present invention comprises: a pair of substrates opposite each other with a discharge space in between; a plurality of row electrode pairs extending in a row direction and regularly arranged in a column direction on the rear-facing face of one substrate in the pair of substrates to respectively form display lines; a dielectric layer overlying the row electrode pairs; a plurality of column electrodes extending in the column direction and regularly arranged in the row direction within the dielectric layer, and formed in a different plane from that in which the row electrode pairs are formed within the dielectric layer; unit light-emission areas individually formed in the discharge space in the proximity of intersections of the row electrode pairs and the column electrodes; a partition wall member provided for individually surrounding and defining each of the unit light emission areas; and a dividing wall provided for further partitioning each of the unit light emission areas so defined into a first discharge area and a second discharge area. The first discharge area faces mutually opposing portions of the respective row electrodes constituting each row electrode pair and is provided for producing a discharge between the row electrodes concerned. The second discharge area faces a portion of each of the column electrodes opposing a portion of one row electrode in each row electrode pair and is provided for producing a discharge between the portion of the column electrode and the portion of the row electrode. The plasma display panel also comprises communicating elements each provided between the first discharge area and the second discharge area for communication from the second discharge area to the first discharge area. 
   In this plasma display panel, for the generation of an image, a reset discharge is caused, in each second discharge area facing the portion of the column electrode, between the portion of the column electrode and the portion of the row electrode in the row electrode pair formed on the same substrate as the column electrode is formed on. This reset discharge triggers the generation/erasure of a wall charge on/from the dielectric layer facing the first discharge area by way of the communicating element provided between the second discharge area and the first discharge area. 
   Next, an addressing discharge generated selectively between the portion of the column electrode and the portion of the row electrode in the row electrode pair is produced in the second discharge area facing the portion of the column electrode. Charged particles generated in the second discharge area by means of the addressing discharge flow into the first discharge area through the communicating element. Thus, the first discharge areas having a wall charge (lighted cells) and the first discharge areas having no wall charge (non-lighted cells) are distributed over the panel surface in accordance with the image to be generated. 
   Then, in each of the first discharge area having a wall charge (i.e. in each of the lighted cells), a sustain discharge for light emission for the generation of the image is produced between the mutually facing portions of the row electrodes constituting the row electrode pair. 
   With the foregoing plasma display panel, because the row electrode pairs and the column electrodes are formed on one of the pair of substrates facing each other with the discharge space in between, it is possible to simplify the manufacturing process to substantially reduce the manufacturing costs. 
   Because the reset discharge and the addressing discharge are caused in the second discharge area which is formed independently of the first discharge area which is provided for producing the sustain discharge for light emission for the generation of the image, it is possible to employ a configuration capable of preventing the emissions caused by the reset discharge and the addressing discharge from leaking toward the display screen of the panel for the prevention of a reduction in the dark-light contrast of the image. 
   Further, there is no need to provide a phosphor layer in the second discharge area in which the addressing discharge is produced. This makes it possible to avoid the effects of the phosphor layer on: the discharge characteristics varying among the individual phosphor materials of the colors of the phosphor layers; a change in discharge voltage caused by the phosphor layer, for example, caused by variations in the thickness of the phosphor layer occurring when the phosphor layer is formed in the manufacturing process; and the like. This ensures the uniformity of the addressing discharge characteristics in each second discharge area, to improve a margin in the addressing discharge. 
   Still further, the first discharge area is only required to produce the sustain discharge. For this reason, the limitations imposed on the structure of the first discharge area are decreased, resulting in the possibility of optimizing the structure of the first discharge area for the sustain discharge. 
   These and other objects and features of the present invention will become more apparent from the following detailed description with reference to the accompanying drawings. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a front view of the structure of a conventional PDP. 
       FIG. 2  is a schematic front view illustrating a first embodiment according to the present invention. 
       FIG. 3  is a sectional view taken along the V 1 —V 1  line in  FIG. 2 . 
       FIG. 4  is a sectional view taken along the V 2 —V 2  line in  FIG. 2 . 
       FIG. 5  is a sectional view taken along the W 1 —W 1  line in  FIG. 2 . 
       FIG. 6  is a sectional view taken along the W 2 —W 2  line in  FIG. 2 . 
       FIG. 7  is a schematic front view illustrating a second embodiment according to the present invention. 
       FIG. 8  is a sectional view taken along the V 3 —V 3  line in  FIG. 7 . 
       FIG. 9  is a sectional view taken along the V 4 —V 4  line in  FIG. 7 . 
       FIG. 10  is a sectional view taken along the W 3 —W 3  line in  FIG. 7 . 
       FIG. 11  is a sectional view taken along the W 4 —W 4  line in  FIG. 7 . 
       FIG. 12  is a schematic front view illustrating a third embodiment according to the present invention. 
       FIG. 13  is a sectional view taken along the V 5 —V 5  line in  FIG. 12 . 
       FIG. 14  is a sectional view taken along the V 6 —V 6  line in  FIG. 12 . 
       FIG. 15  is a sectional view taken along the W 5 —W 5  line in  FIG. 12 . 
       FIG. 16  is a sectional view taken along the W 6 —W 6  line in  FIG. 12 . 
   

   DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
   Preferred embodiments according to the present invention will be described below in detail with reference to the accompanying drawings. 
     FIG. 2  to  FIG. 6  are diagrams illustrating a first embodiment of a plasma display panel (hereinafter referred to as “PDP”) according to the present invention:  FIG. 2  is a schematic front view of the PDP and  FIGS. 3 ,  4 ,  5  and  6  are sectional views respectively taken along the V 1 —V 1  line, the V 2 —V 2  line, the W 1 —W 1  line and the W 2 —W 2  line as shown in  FIG. 2 . 
   In  FIG. 2  to  FIG. 6 , a plurality of row electrode pairs (X 1 , Y 1 ) each extending in the row direction of a front glass substrate  1  (i.e. the right-left direction in  FIG. 2 ) are arranged parallel to each other on the rear-facing face of the front glass substrate  1  serving as the display screen. 
   The row electrode X 1  is composed of a black- or dark-colored bus electrode X 1   a  formed of a metal film extending in the row direction of the front glass substrate  1 , and T-shaped transparent electrodes X 1   b  formed of a transparent conductive film made of ITO or the like. The transparent electrodes X 1   b  are lined up along the bus electrode X 1   a  at regular intervals, and connected to the bus electrode X 1   a  at the proximal ends (corresponding to the foot of the T shape) of thereof. 
   Likewise, the row electrode Y 1  is composed of a black- or dark-colored bus electrode Y 1   a  formed of a metal film extending in the row direction of the front glass substrate  1 , and T-shaped transparent electrodes Y 1   b  formed of a transparent conductive film made of ITO or the like. The transparent electrodes Y 1   b  are lined up along the bus electrode Y 1   a  at regular intervals, and connected to the bus electrode Y 1   a  at the proximal ends (corresponding to the foot of the T shape) of thereof. 
   The row electrodes X 1  and Y 1  are arranged in alternate positions in the column direction of the front glass substrate  1  (i.e. the vertical direction in  FIG. 2 ). The transparent electrodes X 1   b  and Y 1   b  which are lined up along the corresponding bus electrodes X 1   a  and Y 1   a  in each row electrode pair at regular intervals extend in the direction toward its counterpart in the row electrode pair, such that the two distal widened-ends (corresponding to the head of the T shape) of the transparent electrodes X 1   b  and Y 1   b  face each other with a discharge gap g having a required width in between. 
   Each of the row electrode pairs (X 1 , Y 1 ) forms a display line L 1  of the panel. A required spacing, described later, is provided between the row electrodes X 1  and Y 1  positioned back to back in between the adjacent display lines L. 
   A first dielectric layer  2  is provided on the rear-facing face of the front glass substrate  1  so as to cover the row electrode pairs (X 1 , Y 1 ). 
   On the rear-facing face of the first dielectric layer  2 , strip-shaped column-electrode bodies D 1   a  each forming part of a column electrode D 1  each extend in a direction at right angles to the bus electrodes X 1   a , Y 1   a  (i.e. the column direction) and are arranged parallel to each other at regular intervals. Each of the column-electrode bodies D 1   a  is positioned opposite to a strip extending through mid-positions between the transparent electrodes X 1   b , Y 1   b  which are regularly spaced in the row direction along the corresponding bus electrodes X 1   a , Y 1   a  of the row electrodes X 1 , Y 1 . 
   On the rear-facing face of the first dielectric layer  2 , further, bar-shaped column-electrode projections D 1   b  forming part of the column electrode D 1  are formed integrally with each of the column-electrode bodies D 1   a , and each extend from a long side of the column-electrode body D 1   a  in the row direction such that the leading end thereof is positioned opposite a mid-position of the spacing between the row electrodes X 1  and Y 1  which are positioned back to back in between the adjacent display lines L. 
   A second dielectric layer  3  is formed on the rear-facing face of the first dielectric layer  2  so as to cover the column-electrode bodies D 1   a  and the column-electrode projections D 1   b  of the column electrodes D 1 . 
   Strip-shaped first additional dielectric layers  4  project from the rear-facing face of the second dielectric layer  3 . Each of the additional dielectric layers  4  extends in the row direction along the bus electrodes X 1   a , Y 1   a  positioned back to back in between the adjacent display lines L, in a position opposite to the back-to-back bus electrodes X 1   a  and Y 1   a  and the area between the bus electrodes X 1   a  and Y 1   a  concerned. 
   The first additional dielectric layer  4  is constituted of a light absorption layer including a black- or dark-colored pigment. 
   A second additional dielectric layer  5  projects from the rear-facing face of each of the first additional dielectric layers  4 , and extends parallel to the bus electrode Y 1   a  and the column-electrode body D 1   a  in the portion of the rear-facing face of the first additional dielectric layer  4  opposite to the bus electrode X 1   a  and to a portion of the column-electrode body D 1   a  between the bus electrodes X 1   a  and Y 1   a  which are positioned back to back in between the adjacent display lines L 1 . 
   Further, an MgO made protective layer (not shown) is formed on the rear-facing faces of the second dielectric layer  3 , the first additional dielectric layers  4  and the second additional dielectric layers  5 . 
   The front glass substrate  1  is opposite to a back glass substrate  6  with a discharge space in between. A protective layer (dielectric layer)  7  is formed on the front-facing face (inner face) of the back glass substrate  6 . On the protective layer  7 , a partition wall member  8  is formed in a form as follows. 
   When viewed from the front glass substrate  1 , the partition wall member  8  is composed of first transverse walls  8 A, second transverse walls  8 B and vertical walls  8 C. Each of the first transverse walls  8 A extends opposite and parallel to the bus electrode X 1   a  of each row electrode X 1  in the row direction. Each of the second transverse walls  8 B extends opposite and parallel to the bus electrode Y 1   a  of each row electrode Y 1  in the row direction. Each of the vertical walls  8 C extends opposite and parallel to the column-electrode body D 1   a  of each column electrode D 1  in the column electrode. 
   The height of each of the first transverse wall  8 A, second transverse wall  8 B and vertical wall  8 C is designed to be equal to a distance between the protective layer covering the rear-facing face of the second additional dielectric layer  5  and the protective layer  7  formed on the back glass substrate  6 . 
   With this design, the front-facing face (the upper face in  FIG. 3 ) of the first transverse wall  8 A, and the front-facing face of the portion of the vertical wall  8 C extending between the adjacent display lines L 1  are in contact with the rear-facing face of the protective layer covering the second additional dielectric layer  5 . The second additional dielectric layer  5  is not formed between the second transverse wall  8 B and the first additional dielectric layer  4 , so that a clearance r 1  is formed between the front-facing face of the second transverse wall  8 B and the protective layer covering the first additional dielectric layer  4  (see  FIG. 3 ). 
   The first additional dielectric layer  4  and the second additional dielectric layer  5  are not similarly formed between the portion of the vertical wall  8 C extending between the row electrodes X 1  and Y 1  of each row electrode pair (X 1 , Y 1 ) and the second dielectric layer  3 . Hence, a clearance r 2  is formed between the front-facing face of the vertical wall  8 C and the protective layer covering the second dielectric layer  3  (see  FIGS. 4 to 6 ). 
   The first transverse walls  8 A, second transverse walls  8 B and vertical walls  8 C of the partition wall member  8  partition the discharge space defined between the front and back glass substrates  1  and  6  into areas. In each of the partitioned areas, a display discharge cell C 1  facing the opposed transparent electrodes X 1   b  and Y 1   b  paired with each other is formed. Further, the discharge space corresponding to the strip-shaped area between the first transverse wall  8 A and the second transverse wall  8 B and also between the back-to-back bus electrodes X 1   a  and Y 1   a  of the adjacent row electrode pairs (X 1 , Y 1 ) is partitioned by the vertical walls  8 C to form addressing discharge cells C 2 . As a result, the display discharge cells C 1  and the addressing discharge cells C 2  are arranged in alternate positions in the column direction. 
   The display discharge cell C 1  and the addressing discharge cell C 2  adjacent to each other on both sides of the second transverse wall  8 B communicate by means of the clearance r 1  formed between the front-facing face of the second transverse wall  8 B and the protective layer covering the first additional dielectric layer  4 . 
   In each display discharge cell C 1 , a phosphor layer  9  covers almost all five faces facing the discharge space, i.e. the face of the protective layer  7  and the side faces of the first transverse wall  8 A, second transverse wall  8 B, and vertical walls  8 C of the partition wall member  8 . The red (R), green (G) and blue (B) colors are individually applied to the phosphor layers  9  in such a manner so that the red, green and blue display discharge cells C 1  are arranged in order in the row direction. 
   In each addressing discharge cell C 2 , a high γ material layer  10  covers almost all five faces facing the discharge space, i.e. the face of the protective layer  7  and the side faces of the first transverse wall  8 A, second transverse wall  8 B and vertical walls  8 C of the partition wall member  8 . The high γ material layer  10  is formed of a high γ material of a relative dielectric constant ∈ equal to or higher than 50 (from 50 to 250). 
   The high ∈ materials used for the high γ material layer  10  include SrTiO 3 , for example. 
   The display discharge cells C 1  and the addressing discharge cells C 2  in the discharge space are filled with a xenon-including discharge gas. 
   The aforementioned PDP generates images as follows. 
   First, in a reset period, a reset pulse is applied to the row electrode Y 1  and the column electrode D 1  in each addressing discharge cell C 2 , in order to cause a reset discharge between the bus electrode Y 1   a  of the row electrode Y 1  and the column-electrode projection D 1   b  of the column electrode D 1 . This reset discharge triggers the generation of a wall charge on (or alternatively the erasure of the wall charge from) the first dielectric layer  2  and the second dielectric layer  3  facing the display discharge cell C 1  by way of the clearance r 1 . 
   In the subsequent addressing period, a scan pulse is sequentially applied to the row electrodes Y 1 , and a data pulse is applied selectively to the column electrodes D 1  in accordance with the image signal. 
   Thereupon, in the addressing discharge cell C 2 , an addressing discharge is generated between the bus electrode Y 1   a  of the row electrode Y 1  receiving the application of the scan pulse, and the column-electrode projection D 1   b  of the column electrode D 1  receiving the application of the data pulse and positioned opposite the bus electrode Y 1   a  concerned when viewed from the front glass substrate  1 . 
   At this point, with the formation of the high γ material layer  10  in the addressing discharge cell C 2 , the addressing discharge is started at a voltage lower than that when the high γ material layer  10  is not formed. 
   Then, charged particles generated by the addressing discharge in the addressing discharge cell C 2  flow through the clearance r 1  formed between the second transverse wall  8 B and the first additional dielectric layer  4  into the display discharge cell C 1  paired with the addressing discharge cell C 2  on both sides of the second transverse wall  8 B. Thereby, the wall charges accumulated on the portion of the first dielectric layer  2  and the second dielectric layer  3  opposite the display discharge cell C 1  are selectively erased therefrom (or alternatively wall charges are generated on the first dielectric layer  2  and the second dielectric layer  3 ). As a result, lighted cells (the display discharge cells C 1  having the wall charges generated on the first dielectric layer  2  and the second dielectric layer  3 ) and non-lighted cells (the display discharge cells C 1  having no wall charges generated on the first dielectric layer  2  and the second dielectric layer  3 ) are distributed in all the display lines L 1  in accordance with the image to be generated. 
   In a sustaining emission period subsequent to the addressing period, a discharge-sustaining pulse is applied, simultaneously in all the display lines L 1 , alternately to the row electrodes X 1  and Y 1  in the row electrode pair (X 1 , Y 1 ) Thereupon, in each lighted cell, a sustain discharge is produced between the transparent electrodes X 1   b  and Y 1   b  facing each other with every application of the discharge-sustaining pulse. 
   As a result of the sustain discharge, ultraviolet light is generated from xenon Xe in the discharge gas and excites each of the red (R), green (G) and blue (B) phosphor layers  9  facing the individual display discharge cells C 1  to allow the phosphor layers  9  to emit visible light for the generation of the image. 
   In the PDP in the first embodiment, by forming both the row electrode pairs (X 1 , Y 1 ) and the column electrodes D 1  on the front glass substrate  1 , the distance between the bus electrode Y 1   a  of the row electrode Y 1  and the column-electrode projection D 1   b  between which the addressing discharge is generated is shortened. For this reason, the addressing discharge is caused at a low discharge-starting voltage. 
   Further, the PDP does not requires in the manufacturing process a high degree of accuracy of the alignment between the front glass substrate  1  and the back glass substrate  6 , the height of the wall partition wall member, and the like, leading to the simplification of the manufacturing process. 
   In the foregoing PDP, the addressing discharge cell C 2  for producing the reset discharge and the addressing discharge is separated from the display discharge cell C 1  for producing the sustain discharge. The black- or dark-colored first additional dielectric layer  4  is formed over the addressing discharge cell C 2  on the panel screen side of the addressing discharge cell C 2 . For the reasons, the light generated by the reset discharge and the addressing discharge in the addressing discharge cell C 2  is blocked by the first additional dielectric layer  4  to be prevented from leaking toward the front glass substrate  1 . 
   Accordingly the panel display surface is prevented from shining every time the reset discharge and the addressing discharge which are not a discharge for emitting light for the image generation are produced. Thereby, it is possible to prevent a decrease in light-dark contrast in the image caused by the reset discharge and the addressing discharge. 
   Further, because a phosphor layer is not provided in the addressing discharge cell C 2  in which the addressing discharge is produced, the phosphor layer has no effects on: the discharge characteristics varying among the individual phosphor materials of the colors of the phosphor layers; variations in discharge voltage caused by the phosphor layer, for example, by variations in the thickness of the phosphor layer occurring when the phosphor layer is formed in the manufacturing process; and the like. This ensures the uniformity of the addressing discharge characteristics in each addressing discharge cell C 2 , to improve a margin in the addressing discharge. 
   Still further, the display discharge cell C 1  is only required to produce the sustain discharge. For this reason, the limitations imposed on the structure of the display discharge cell are eliminated, resulting in the possibility of optimizing the structure of the display discharge cell C 1  for the sustain discharge. 
     FIG. 7  to  FIG. 11  are diagrams illustrating a second embodiment of the PDP according to the present invention:  FIG. 7  is a schematic front view of the PDP and  FIGS. 8 ,  9 ,  10  and  11  are sectional views respectively taken along the V 3 —V 3  line, the V 4 —V 4  line, the W 3 —W 3  line and the W 4 —W 4  line as shown in  FIG. 7 . 
   In  FIG. 7  to  FIG. 11 , a plurality of row electrode pairs (X 2 , Y 2 ) each extending in the row direction of a front glass substrate  1  (i.e. the right-left direction in  FIG. 7 ) are arranged parallel to each other on the rear-facing face of the front glass substrate  1  serving as the display screen. 
   The row electrode X 2  is composed of a bus electrode X 2   a  formed of a black- or dark-colored metal film extending in the row direction of the front glass substrate  1 , and T-shaped transparent electrodes X 2   b  formed of a transparent conductive film made of ITO or the like. The transparent electrodes X 2   b  are lined up along the bus electrode X 2   a  at regular intervals, and connected to the bus electrode X 2   a  at the leg portion X 2   b   1  of a small width thereof. 
   Likewise, the row electrode Y 2  is composed of a black- or dark-colored bus electrode Y 2   a  formed of a metal film extending in the row direction of the front glass substrate  1 , and T-shaped transparent electrodes Y 2   b  formed of a transparent conductive film made of ITO or the like. The transparent electrodes Y 2   b  are lined up along the bus electrode Y 2   a  at regular intervals, and connected to the bus electrode Y 2   a  at the leg portion Y 2   b   1  of a small width thereof. 
   The small-width leg-portion Y 2   b   1  of each of the transparent electrodes Y 2   b  of the row electrode Y 2  is greater in length than that of the small-width leg-portion X 2   b   1  of each transparent electrode X 2   b  of the row electrode X 2 . 
   The row electrodes X 2  and Y 2  are arranged in alternate positions in the column direction of the front glass substrate  1  (i.e. the vertical direction in  FIG. 7 ). The transparent electrodes X 2   b  and Y 2   b  which are regularly spaced along the corresponding bus electrodes X 2   a  and Y 2   a  in each row electrode pair extend in the direction toward its counterpart in the row electrode pair, such that the two tops (of a large width) of the transparent electrodes X 2   b  and Y 2   b  face each other with a discharge gap g having a required width in between. 
   A first dielectric layer  12  is provided on the rear-facing face of the front glass substrate  1  so as to cover the row electrode pairs (X 2 , Y 2 ). 
   On the rear-facing face of the first dielectric layer  12 , strip-shaped column-electrode bodies D 2   a  each forming part of a column electrode D 2  each extend a direction at right angles to the bus electrodes X 2   a , Y 2   a  (i.e. in the column direction) and are arranged parallel to each other at regular intervals. Each of the column-electrode bodies D 2   a  is positioned opposite to a strip extending through mid-positions between the transparent electrodes X 2   b , Y 2   b  which are regularly spaced in the row direction along the corresponding bus electrodes X 2   a , Y 2   a  of the row electrodes X 2 , Y 2 . 
   On the rear-facing face of the first dielectric layer  12 , further, bar-shaped column-electrode projections D 2   b  forming part of the column electrode D 2  are formed integrally with each of the column-electrode bodies D 2   a . Each of the column-electrode projections D 2   b  extends from a long side of the column-electrode body D 2   a  in the row direction along the long side of the bus electrode Y 2   a  facing toward the row electrode X 2  paired therewith. The leading end of the column-electrode projection D 2   b  intersects the leg portion Y 2   b   1  of the transparent electrode Y 2   b  in the proximity of the connection portion of the bus electrode Y 2   a  to the transparent electrode Y 2   b  when viewed from the front substrate  1 . 
   A second dielectric layer  13  is formed on the rear-facing face of the first dielectric layer  12  so as to cover the column-electrode bodies D 2   a  and the column-electrode projections D 2   b  of the column electrodes D 2 . 
   Strip-shaped first additional dielectric layers  4  project from the rear-facing face of the second dielectric layer  13 . Each of the additional dielectric layer  4  extends in the row direction along the bus electrodes X 2   a , Y 2   a  positioned back to back in between the adjacent display lines L 1 , in a position opposite to: the back-to-back bus electrodes X 2   a  and Y 2   a ; the column-electrode projections D 2   b  extending along the bus electrode Y 2   a ; and a strip area of a required width from the long side of the column-electrode projection D 2   b  in the direction toward the large-width top of the transparent electrode Y 2   b  intersecting the column-electrode projection D 2   b  concerned. 
   The first additional dielectric layer  4  is constituted of a light absorption layer including a black- or dark-colored pigment. 
   A second additional dielectric layer  5  projects from the rear-facing face of each of the first additional dielectric layers  4 . The second additional dielectric layer  5  is provided on the strip portion of the rear-facing face of the first additional dielectric layer  4  opposite the bus electrode X 2   a . Further, the second additional dielectric layer  5  is provided on the strip portion extending from one long side of the first additional dielectric layer  4  to the other long side in the column direction, that is, from a position opposite the bus electrode X 2   a , through a position opposite the bus electrode Y 2   a  positioned back to back with the bus electrode X 2   a  and in the adjacent display line, then through each of the column-dielectric bodies D 2   a , to the other long side of the first additional dielectric layer  4 . 
   Further, an MgO made protective layer (not shown) is formed on the rear-facing faces of the second dielectric layer  13 , the first additional dielectric layers  4  and the second additional dielectric layers  5 . 
   The front glass substrate  1  is opposite to a back glass substrate  6  with a discharge space in between. A protective layer (dielectric layer)  7  is formed on the front-facing face (inner face) of the back glass substrate  6 . On the protective layer  7 , a partition wall member  8  is formed in a form as follows. 
   When viewed from the front glass substrate  1 , the partition wall member  8  is composed of first transverse walls  8 A, second transverse walls  8 B and vertical walls  8 C. Each of the first transverse walls  8 A extends opposite and parallel to the bus electrode X 2   a  of each row electrode X 2  in the row direction. Each of the second transverse walls  8 B extends in the row direction opposite the long side of the first additional dielectric layer  4  facing toward the large-width tops of the transparent electrodes Y 2   b  of each row electrode Y 2  intersecting the column electrode projections D 2   b . Each of the vertical walls  8 C extends opposite and parallel to the column-electrode body D 2   a  of each column electrode D 2  in the column direction. 
   The height of each of the first transverse wall  8 A, second transverse wall  8 B and vertical wall  8 C is designed to be equal to a distance (or length) between the protective layer covering the rear-facing face of the second additional dielectric layer  5  and the protective layer  7  formed on the back glass substrate  6 . 
   With this design, the front-facing face (the upper face in  FIG. 8 ) of the first transverse wall  8 A, and the front-facing face of the portion of the vertical wall  8 C extending from the first transverse wall  8 A to the second transverse wall  8 B positioned close to the bus electrode Y 2   a  in the adjacent display line L 1  are in contact with the rear-facing face of the protective layer covering the second additional dielectric layer  5  (see  FIGS. 8 and 9 ). The second additional dielectric layer  5  is not formed between the second transverse wall  8 B and the first additional dielectric layer  4 , so that a clearance r 1  is formed between the front-facing face of the second transverse wall  8 B and the protective layer covering the first additional dielectric layer  4  (see  FIG. 8 ). 
   The first additional dielectric layer  4  and the second additional dielectric layer  5  are not similarly formed between the second dielectric layer  13  and the portion of the vertical wall  8 C extending between the second transverse wall  8 B and the first transverse wall  8 A positioned close to the transparent electrode X 2   b  paired with the transparent electrode Y 2   b  intersecting the second transverse wall  8 B concerned when viewed from the front glass substrate  1 . 
   Hence, a clearance r 2  is formed between the front-facing face of the vertical wall  8 C and the protective layer covering the second dielectric layer  13  (see  FIGS. 9 to 11 ). 
   The first transverse walls  8 A, second transverse walls  8 B and vertical walls  8 C of the partition wall member  8  partition the discharge space defined between the front and back glass substrates  1  and  6  into areas. In each of the partitioned areas, a display discharge cell C 1  facing the opposed transparent electrodes X 2   b  and Y 2   b  paired with each other is formed. Further, the vertical walls  8 C partitions the space corresponding to the strip-shaped area defined between the first transverse wall  8 A and the second transverse wall  8 B and facing the bus electrodes Y 2   a  of the row electrode Y 2  and the column-electrode projections D 2   b  of the column electrodes D 2  to from addressing discharge cells C 2 . As a result, the display discharge cells C 1  and the addressing discharge cells C 2  are arranged in alternate position in the column direction. 
   The display discharge cell C 1  and the addressing discharge cell C 2  adjacent to each other on both sides of the second transverse wall  8 B in the column direction communicate by means of the clearance r 1  formed between the front-facing face of the second transverse wall  8 B and the protective layer covering the first additional dielectric layer  4 . 
   In each display discharge cell C 1 , a phosphor layer  9  covers almost all five faces facing the discharge space, i.e. the face of the protective layer  7  and the side faces of the first transverse wall  8 A, second transverse wall  8 B, and vertical walls  8 C of the partition wall member  8 . The red (R), green (G) and blue (B) colors are individually applied to the phosphor layers  9  in such a manner so that the red, green and blue display discharge cells C 1  are arranged in order in the row direction. 
   In each addressing discharge cell C 2 , a high γ material layer  10  covers almost all five faces facing the discharge space, i.e. the face of the protective layer  7  and the side faces of the first transverse wall  8 A, second transverse wall  8 B and vertical walls  8 C of the partition wall member  8 . The high γ material layer  10  is formed of a high γ material of a relative dielectric constant ∈ equal to or higher than 50 (from 50 to 250). 
   The high ∈ materials used for the high γ material layer  10  include SrTiO 3 , for example. 
   The display discharge cells C 1  and the addressing discharge cells C 2  in the discharge space are filled with a xenon-including discharge gas. 
   The aforementioned PDP generates images as follows. 
   First, in a reset period, a reset pulse is applied to the row electrode Y 2  and the column electrode D 2  in each addressing discharge cell C 2 , in order to cause a reset discharge between the bus electrode Y 2   a  and transparent electrode Y 2   b  of the row electrode Y 2  and the column-electrode body D 2   a  of the column electrode D 2 . This reset discharge triggers the generation of a wall charge on (or alternatively the entire erasure of the wall charge from) the first dielectric layer  12  and the second dielectric layer  13  facing the display discharge cell C 1  by way of the clearance r 1 . 
   In the subsequent addressing period, a scan pulse is sequentially applied to the row electrodes Y 2 , and a data pulse is applied selectively to the column electrodes D 2  in accordance with the image signal. 
   Thereupon, in the addressing discharge cell C 2 , an addressing discharge is generated between the bus electrode Y 2   a  and transparent electrode Y 2   b  of the row electrode Y 2  receiving the application of the scan pulse, and the column-electrode projection D 2   b  of the column electrode D 2  receiving the application of the data pulse, the column-electrode projection D 2   b  intersecting the transparent electrode Y 2   b  when viewed from the front glass substrate  1 . 
   At this point, with the formation of the high γ material layer  10  in the addressing discharge cell C 2 , the addressing discharge is started at a voltage lower than that when the high γ material layer  10  is not formed. 
   Then, charged particles generated by the addressing discharge in the addressing discharge cell C 2  flow through the clearance r 1  formed between the second transverse wall  8 B and the first additional dielectric layer  4  into the display discharge cell C 1  paired with the addressing discharge cell C 2  concerned on both sides of the second transverse wall  8 B. Thereby, the wall charges accumulated on the portion of the first dielectric layer  12  and the second dielectric layer  13  opposite the display discharge cell C 1  are selectively erased therefrom (or alternatively wall charges are generated on the first dielectric layer  12  and the second dielectric layer  13 ). As a result, lighted cells (the display discharge cells C 1  having the wall charges generated on the first dielectric layer  12  and the second dielectric layer  13 ) and non-lighted cells (the display discharge cells C 1  having no wall charges generated on the first dielectric layer  12  and the second dielectric layer  13 ) are distributed in all the display lines L 1  in accordance with the image to be generated. 
   In a sustaining emission period subsequent to the addressing period, a discharge-sustaining pulse is applied, simultaneously in all the display lines L 1 , alternately to the row electrodes X 2  and Y 2  in the row electrode pair (X 2 , Y 2 ). Thereupon, in each lighted cell, a sustain discharge is produced between the transparent electrodes X 2   b  and Y 2   b  facing each other with every application of the discharge-sustaining pulse. 
   As a result of the sustain discharge, ultraviolet light is generated from xenon Xe in the discharge gas and excites each of the red (R), green (G) and blue (B) phosphor layers  9  facing the individual display discharge cells C 1  to allow the phosphor layers  9  to emit visible light for the generation of the image. 
   In the PDP in the second embodiment, as in the case of the first embodiment, by forming both the row electrode pairs (X 2 , Y 2 ) and the column electrodes D 2  on the front glass substrate  1 , the distance between the bus electrode Y 2   a  and transparent electrode Y 2   b  of the row electrode Y 2  and the column-electrode projection D 2   b  between which the addressing discharge is generated is shortened. For this reason, the addressing discharge is caused at a low discharge-starting voltage. 
   The PDP in the second embodiment, when compared to the first embodiment, a discharge starting voltage of the addressing discharge is further reduced because the column-electrode projection D 2   b  is formed in a position intersecting the transparent electrode Y 2   b  of the row electrode Y 2 . 
   Further, the PDP does not requires in the manufacturing process a high degree of accuracy of the alignment between the front glass substrate  1  and the back glass substrate  6 , the height of the wall partition wall member, and the like, leading to the simplification of the manufacturing process. 
   In the foregoing PDP, the addressing discharge cell C 2  for producing the reset discharge and the addressing discharge is separated from the display discharge cell C 1  for producing the sustain discharge. The black- or dark-colored first additional dielectric layer  4  is formed over the addressing discharge cell C 2  on the panel screen side of the addressing discharge cell C 2 . Hence, the light generated by the reset discharge and the addressing discharge in the addressing discharge cell C 2  is blocked by the first additional dielectric layer  4  to be prevented from leaking toward the front glass substrate  1 . 
   Accordingly the panel display surface is prevented from shining every time the reset discharge and the addressing discharge which are not a discharge for emitting light for the image generation are produced. Thereby, it is possible to prevent a decrease in light-dark contrast in the image due to the reset discharge and the addressing discharge. 
   Further, a phosphor layer is not provided in the addressing discharge cell C 2  in which the addressing discharge is produced. There is no effects of the phosphor layer on: the discharge characteristics varying among the individual phosphor materials of the colors of the phosphor layers; variations in discharge voltage caused by the phosphor layer, for example, by variations in the thickness of the phosphor layer occurring when the phosphor layer is formed in the manufacturing process; and the like. This ensures the uniformity of the addressing discharge characteristics in each addressing discharge cell C 2 , to improve a margin in the addressing discharge. 
   Still further, the display discharge cell C 1  is only required to produce the sustain discharge. For this reason, the limitations imposed on the structure of the display discharge cell are eliminated, resulting in the possibility of optimizing the structure of the display discharge cell C 1  for the sustain discharge. 
     FIG. 12  to  FIG. 16  are diagrams illustrating a third embodiment of the PDP according to the present invention:  FIG. 12  is a schematic front view of the PDP and  FIGS. 13 ,  14 ,  15  and  16  are sectional views respectively taken along the V 5 —V 5  line, the V 6 —V 6  line, the W 5 —W 5  line and the W 6 —W 6  line as shown in  FIG. 12 . 
   In  FIG. 12  to  FIG. 16 , row electrodes X 3  and row electrodes Y 3  each extending in the row direction of a front glass substrate  1  (i.e. the right-left direction in  FIG. 12 ) are regularly arranged in alternate positions at required intervals in the column direction on the rear-facing face of the front glass substrate  1  serving as the display screen. 
   The row electrode X 3  is composed of a bus electrode X 3   a  formed of a black- or dark-colored metal film extending in the row direction of the front glass substrate  1 , and transparent electrodes X 3   b  formed of a transparent conductive film made of ITO or the like. The transparent electrodes X 3   b  are lined up along the bus electrode X 3   a  at regular intervals. Each of the transparent electrodes X 3   b  extends from both long sides of the bus electrode X 3   a  in the column direction and is connected to the bus electrode X 3   a  intersecting at right angles thereto. 
   Each of the transparent electrodes X 3   b  is composed of a T-shaped first transparent electrode portion X 3   b   1  extending from the bus electrode X 3   a  upward in  FIG. 12 , and a T-shaped second transparent electrode portion X 3   b   2  extending downward in  FIG. 12 . 
   In each transparent electrode X 3   b , the small-width leg of the first transparent electrode portion X 3   b   1  is longer in length than that of the second transparent electrode portion X 3   b   2 . 
   Likewise, the row electrode Y 3  is composed of a bus electrode Y 3   a  formed of a black- or dark-colored metal film extending in the row direction of the front glass substrate  1 , and transparent electrodes Y 3   b  formed of a transparent conductive film made of ITO or the like. The transparent electrodes Y 3   b  are lined up along the bus electrode Y 3   a  at regular intervals. Each of the transparent electrodes Y 3   b  extends from both long sides of the bus electrode Y 3   a  in the column direction and is connected to the bus electrode Y 3   a  intersecting at right angles thereto. 
   Each of the transparent electrodes Y 3   b  is composed of a T-shaped first transparent electrode portion Y 3   b   1  extending from the bus electrode Y 3   a  upward in  FIG. 12 , and a T-shaped second transparent electrode portion Y 3   b   2  extending downward in  FIG. 12 . 
   In each transparent electrode Y 3   b , the small-width leg of the first transparent electrode portion Y 3   b   1  is longer in length than that of the second transparent electrode portion Y 3   b   2 . 
   Regarding the row electrodes X 3  and Y 3 , the top (of a large width) of the second transparent electrode portion X 3   b   2  and the top (of a large width) of the first transparent electrode portion Y 3   b   1  are positioned opposite to each other as a pair with a discharge gap g 1  in between. Likewise, the large-width top of the first transparent electrode portion X 3   b   1  and the large-width top of the second transparent electrode portion Y 3   b   2  are positioned opposite to each other as a pair with a discharge gap g 1  in between. 
   A row of the second transparent electrode portions X 3   b   2  and the first transparent electrode portions Y 3   b   1  facing each other as a pair forms each display line L 2 , and similarly a row of the first transparent electrode portions X 3   b   1  and the second transparent electrode portions Y 3   b   2  facing each other as a pair forms each display line L 2 . 
   A first dielectric layer  22  is provided on the rear-facing face of the front glass substrate  1  so as to cover the row electrode X 3  and Y 3 . 
   On the rear-facing face of the first dielectric layer  22 , strip-shaped column-electrode bodies D 3   a  each forming part of a column electrode D 3  each extend a direction at right angles to the bus electrodes X 3   a , Y 3   a  (i.e. in the column direction) and are arranged parallel to each other at regular intervals. Each of the column-electrode bodies D 3   a  is positioned opposite to a strip extending through mid-positions between the transparent electrodes X 3   b , Y 3   b  which are regularly spaced in the row direction along the corresponding bus electrodes X 3   a , Y 3   a  of the row electrodes X 3 , Y 3 . 
   When viewed from the front glass substrate  1 , each of the column electrodes D 3  has further bar-shaped column-electrode projections D 3   b  formed integrally with the column-electrode body D 3   a . Each of the column-electrode projections D 3   b  extends from a long side of the column-electrode body D 3   a  in the row direction along and in the proximity of the upper long side (in  FIG. 12 ) of each of the bus electrodes X 3   a  and Y 3   a.    
   The leading end of the column-electrode projection D 3   b  is positioned to intersect the first transparent electrode portion X 3   b   1  in the proximity of the connection portion of the bus electrode X 3   a  to the leg of the first transparent electrode portion X 3   b   1  of the transparent electrode X 3   b , or to intersect the first transparent electrode portion Y 3   b   1  in the proximity of the connection portion of the bus electrode Y 3   a  to the leg of the first transparent electrode portion Y 3   b   1  of the transparent electrode Y 3   b.    
   A second dielectric layer  23  is formed on the rear-facing face of the first dielectric layer  22  so as to cover the column-electrode bodies D 3   a  and the column-electrode projections D 3   b  of the column electrodes D 3 . 
   Strip-shaped first additional dielectric layers  24  extend in the row direction along the bus electrodes X 3   a , Y 3   a  and project from the rear-facing face of the second dielectric layer  23 . The additional dielectric layer  24  is opposite to a strip area of a width ranging from a point at a required distance from the intersection between the first transparent electrode portion X 3   b   1  of the transparent electrode X 3   b  and the column-electrode projection D 3   b  toward the top of the first transparent electrode portion X 3   b   1 , to a point at a required distance from the connection portion of the second transparent electrode portion X 3   b   2  with the bus electrode X 3   a  toward the top of the second transparent electrode portion X 3   b   2 . 
   The first additional dielectric layer  24  is also opposite to a strip area of a width ranging from a point at a required distance from the intersection between the first transparent electrode portion Y 3   b   1  of the transparent electrode Y 3   b  and the column-electrode projection D 3   b  toward the top of the first transparent electrode portion Y 3   b   1 , to a point at a required distance from the connection portion of the second transparent electrode portion Y 3   b   2  with the bus electrode Y 3   a  toward the top of the second transparent electrode portion Y 3   b   2 . 
   The first additional dielectric layer  24  is constituted of a light absorption layer including a black- or dark-colored pigment. 
   A second additional dielectric layer  25  projects from the rear-facing face of each of the first additional dielectric layers  24 . The second additional dielectric layer  25  is provided on: a strip portion of the first additional dielectric layer  24  extending in the row direction opposite a strip area having a required width ranging from the intersection between the first transparent electrode portion X 3   b   1  of the transparent electrode X 3   b  and the column-electrode projection D 3   b  to a some point positioned in the direction of the top of the first transparent electrode portion X 3   b   1 ; and another strip portion thereof extending in the column direction opposite a portion of the column electrode body D 3   a , the portion ranging from the above strip area to a position at a required distance between a point corresponding to the connection portion of the second transparent electrode portion X 3   b   2  with the bus electrode X 3   a  and a some point positioned in the direction of the top of the second transparent electrode portion X 3   b   2 . 
   The second additional dielectric layer  25  is also provided on: a strip portion of the first additional dielectric layer  24  extending in the row direction opposite a strip area having a required width ranging from the intersection between the first transparent electrode portion Y 3   b   1  of the transparent electrode Y 3   b  and the column-electrode projection D 3   b  to a some point positioned in the direction of the top of the first transparent electrode portion Y 3   b   1 ; and a strip portion of the same extending in the column direction opposite a portion of the column electrode body D 3   a , the portion ranging from the above strip area to a position at a required distance between a point corresponding to the connection portion of the second transparent electrode portion Y 3   b   2  with the bus electrode Y 3   a  and a some point positioned in the direction of the top of the second transparent electrode portion Y 3   b   2 . 
   Further, an MgO made protective layer (not shown) is formed on the rear-facing faces of the second dielectric layer  23 , the first additional dielectric layers  24  and the second additional dielectric layers  25 . 
   The front glass substrate  1  is opposite to a back glass substrate  6  with a discharge space in between. A protective layer (dielectric layer)  7  is formed on the front-facing face (inner face) of the back glass substrate  6 . On the protective layer  7 , a partition wall member  8  is formed in a form as follows. 
   The partition wall member  8  is composed of first transverse walls  8 A, second transverse walls  8 B and vertical walls  8 C. The first transverse wall  8 A extends in the row direction opposite the strip-shaped portion of the second additional dielectric layer  25  extending in the row direction. The second transverse wall  8 B extends in the row direction opposite an area having a required width and including the vicinity of the connection portion of each second transparent electrode portion X 3   b   2  of the transparent electrode X 3   b  with the bus electrode X 3   a . The second transverse wall  8 B also extends in the row direction opposite an area having a required width and including the vicinity of the connection portion of each second transparent electrode portion Y 3   b   2  of the transparent electrode Y 3   b  with the bus electrode Y 3   a . The vertical wall  8 C is opposite and parallel to the column-electrode body D 3   a  of each column electrode D 3  in the column direction. 
   The first transverse walls  8 A, second transverse walls  8 B and vertical walls  8 C of the partition wall member  8  partition the discharge space defined between the front and back glass substrates  1  and  6  into areas to form display discharge cells C 1  and addressing discharge cells C 2  arranged in alternate positions in the column direction with the first transverse wall  8 A or second transverse wall  8 B being interposed between the cells C 1  and C 2 . 
   The display discharge cell C 1  faces the second transparent electrode portion X 3   b   2  and the first transparent electrode portion Y 3   b   1  which are opposite each other as a pair, and another display discharge cell C 1  faces the second transparent electrode portion Y 3   b   2  and the first transparent electrode portion X 3   b   1  which are opposite each other as a pair. 
   The addressing discharge cell C 2  faces the bus electrode X 3   a  of the row electrode X 3  and the column-electrode projection D 3   b  of the column electrode D 3 , and another addressing discharge cell C 2  faces the bus electrode Y 3   a  of the row electrode Y 3  and the column-electrode projection D 3   b  of the column electrode D 3 . 
   The height of each of the first transverse wall  8 A, second transverse wall  8 B and vertical wall  8 C is designed to be equal to a distance (or length) between the protective layer covering the rear-facing face of the second additional dielectric layer  25  and the protective layer  7  formed on the back glass substrate  6 . 
   With this design, the front-facing face (the upper face in  FIG. 13 ) of the first transverse wall  8 A and the front-facing face of the portion of the vertical wall  8 C which extends from the first transverse wall  8 A through the bus electrode X 3   a  or bus electrode Y 3   a  to the second transverse wall  8 B are in contact with the rear-facing face of the protective layer covering the second additional dielectric layer  25  (see  FIGS. 13 and 14 ). The second additional dielectric layer  25  is not formed between the second transverse wall  8 B and the first additional dielectric layer  24 , so that a clearance r 1  is formed between the front-facing face of the second transverse wall  8 B and the protective layer covering the first additional dielectric layer  24  (see  FIG. 13 ). 
   The first additional dielectric layer  24  and the second additional dielectric layer  25  is not formed between the second dielectric layer  23  and the portion of the vertical wall  8 C between the second transverse wall  8 B and the first transverse wall  8 A which are on opposite sides of the display discharge cell C 1 . Hence, a clearance r 2  is formed between the front-facing face of the above portion of the vertical wall  8 C and the protective layer covering the second dielectric layer  23  (see  FIGS. 14 to 16 ). 
   The display discharge cell C 1  and the addressing display cell C 2  adjacent to each other on both sides of the second transverse wall  8 B in the column direction communicate by means of the clearance r 1 . 
   In each display discharge cell C 1 , a phosphor layer  9  covers almost all five faces facing the discharge space, i.e. the face of the protective layer  7  and the side faces of the first transverse wall  8 A, second transverse wall  8 B, and vertical walls  8 C of the partition wall member  8 . The red (R), green (G) and blue (B) colors are individually applied to the phosphor layers  9  in such a manner so that the red, green and blue display discharge cells C 1  are arranged in order in the row direction. 
   In each addressing discharge cell C 2 , a high γ material layer  10  covers almost all five faces facing the discharge space, i.e. the face of the protective layer  7  and the side faces of the first transverse wall  8 A, second transverse wall  8 B and vertical walls  8 C of the partition wall member  8 . The high γ material layer  10  is formed of a high γ material of a relative dielectric constant ∈ equal to or higher than 50 (from 50 to 250). 
   The high ∈ materials used for the high γ material layer  10  include SrTiO 3 , for example. 
   The display discharge cells C 1  and the addressing discharge cells C 2  in the discharge space are filled with a xenon-including discharge gas. 
   The aforementioned PDP generates images as follows. 
   First, in a reset period, a reset pulse is applied to the row electrodes X 3 , Y 3  and the column electrode D 3  in each addressing discharge cell C 2 , in order to cause a reset discharge between the bus electrode X 3   a  and first transparent electrode portion X 3   b   1  and the column-electrode projection D 3   b  of the column electrode D 3 , and a reset discharge between the bus electrode Y 3   a  and first transparent electrode portion Y 3   b   1  and the column-electrode projection D 3   b  of the column electrode D 3 . This reset discharge triggers the generation of a wall charge on (or alternatively the erasure of the wall charge from) the portions of the first dielectric layer  22  and the second dielectric layer  23  facing the display discharge cell C 1  by way of the clearance r 1 . 
   In the subsequent addressing period, a scan pulse is sequentially applied to the row electrodes X 3  and Y 3 , and a data pulse is applied selectively to the column electrodes D 3  in accordance with the image signal. 
   Thereupon, in the addressing discharge cell C 2 , an addressing discharge is generated between the bus electrode X 3   a  and first transparent electrode portion X 3   b   1  of the row electrode X 3  (or the bus electrode Y 3   a  and first transparent electrode portion Y 3   b   1  of the row electrode Y 3 ) receiving the application of the scan pulse, and the column-electrode projection D 3   b  of the column electrode D 3  receiving the application of the data pulse. 
   At this point, with the formation of the high γ material layer  10  in the addressing discharge cell C 2 , the addressing discharge is started at a voltage lower than that when the high  7  material layer  10  is not formed. 
   Then, charged particles generated by the addressing discharge in the addressing discharge cell C 2  flow through the clearance r 1  formed between the second transverse wall  8 B and the first additional dielectric layer  24  into the display discharge cell C 1  paired with the addressing discharge cell C 2  on both sides of the second transverse wall  8 B. Thereby, the wall charges accumulated on the portion of the first dielectric layer  22  and the second dielectric layer  23  opposite the display discharge cell C 1  are selectively erased therefrom (or alternatively wall charges are generated on the first dielectric layer  22  and the second dielectric layer  23 ). 
   As a result, lighted cells (the display discharge cells C 1  having the wall charges generated on the first dielectric layer  22  and the second dielectric layer  23 ) and non-lighted cells (the display discharge cells C 1  having no wall charges generated on the first dielectric layer  22  and the second dielectric layer  23 ) are distributed in all the display lines L 2  in accordance with the image to be generated. 
   In a sustaining emission period subsequent to the addressing period, a discharge-sustaining pulse is applied, simultaneously in all the display lines L 2 , alternately to the row electrodes X 3  and Y 3 . Thereupon, in each lighted cell, a sustain discharge is produced between the first transparent electrode portion X 3   b   1  and the second transparent electrode portion Y 3   b   2  facing each other as a pair, or between the second transparent electrode portion X 3   b   2  and the first transparent electrode portion Y 3   b   1  facing each other as a pair, with every application of the discharge-sustaining pulse. 
   As a result of the sustain discharge, ultraviolet light is generated from xenon Xe in the discharge gas and excites each of the red (R), green (G) and blue (B) phosphor layers  9  facing the individual display discharge cells C 1  to allow the phosphor layers  9  to emit visible light for the generation of the image. 
   In the PDP in the third embodiment, as in the case of the first embodiment, by forming both the row electrodes X 3 , Y 3  and the column electrodes D 3  on the front glass substrate  1 , the distance between the column electrode D 3  and the portions of the row electrodes X 3  and Y 3  which are used for producing the addressing discharge is generated is shortened. For this reason, the addressing discharge is caused at a low discharge-starting voltage. 
   The PDP in the third embodiment, when compared to the first embodiment, a discharge starting voltage of the addressing discharge is further reduced because the column-electrode projection D 3   b  is formed in a position intersecting the transparent electrode X 3   b  of the row electrode X 3  and the transparent electrode Y 3   b  of the row electrode Y 3 . 
   Further, the PDP does not requires in the manufacturing process a high degree of accuracy of the alignment between the front glass substrate  1  and the back glass substrate  6 , the height of the wall partition wall member, and the like, leading to the simplification of the manufacturing process. 
   In the foregoing PDP, the addressing discharge cell C 2  for producing the reset discharge and the addressing discharge is separated from the display discharge cell C 1  for producing the sustain discharge. The black- or dark-colored first additional dielectric layer  24  is formed over the addressing discharge cell C 2  on the panel screen side of the addressing discharge cell C 2 . Hence, the light generated by the reset discharge and the addressing discharge in the addressing discharge cell C 2  is blocked by the first additional dielectric layer  24  to be prevented from leaking toward the front glass substrate  1 . 
   Accordingly the panel display surface is prevented from shining every time the reset discharge and the addressing discharge which are not a discharge for emitting light for the image generation are produced. Thereby, it is possible to prevent a decrease in light-dark contrast in the image due to the reset discharge and the addressing discharge. 
   Further, a phosphor layer is not provided in the addressing discharge cell C 2  in which the addressing discharge is produced. There is no effects of the phosphor layer on: the discharge characteristics varying among the individual phosphor materials of the colors of the phosphor layers; variations in discharge voltage caused by the phosphor layer, for example, by variations in the thickness of the phosphor layer occurring when the phosphor layer is formed in the manufacturing process; and the like. This ensures the uniformity of the addressing discharge characteristics in each addressing discharge cell C 2 , to improve a margin in the addressing discharge. 
   Still further, the display discharge cell C 1  is only required to produce the sustain discharge. For this reason, the limitations imposed on the structure of the display discharge cell are eliminated, resulting in the possibility of optimizing the structure of the display discharge cell C 1  for the sustain discharge. 
   In the foregoing embodiments, the high γ material layer is provided in the addressing discharge cell C 2 . However, instead of the high γ material layer, a secondary electron emissive layer (MgO layer) may be provided. 
   The formation of the secondary electron emissive layer (MgO layer) allows to ensure an adequate amount of charged particles for a supply from the addressing discharge cell C 2  to the display discharge cell C 1 . 
   The first, second and third embodiments have described a PDP based on the superior idea that: substrates in a pair face each other with a discharge space in between; a plurality of row electrode pairs extend in a row direction and are regularly arranged in a column direction on the rear-facing face of one substrate in the pair of substrates to respectively form display lines; a dielectric layer overlays the row electrode pairs; a plurality of column electrodes extend in the column direction and are regularly arranged in the row direction within the dielectric layer, and formed in a different plane from that in which the row electrode pairs are formed within the dielectric layer; unit light-emission areas are individually formed in the discharge space in the proximity of intersections of the row electrode pairs and the column electrodes; a partition wall member is provided for individually surrounding and defining each of the unit light emission areas; a dividing wall is provided for further partitioning each of the unit light emission areas so defined into a first discharge area and a second discharge area, the first discharge area faces mutually opposing portions of the respective row electrodes constituting each row electrode pair and is provided for producing a discharge between the row electrodes concerned, and the second discharge area faces a portion of each of the column electrodes opposing a portion of one row electrode in each row electrode pair and is provided for producing a discharge between the portion of the column electrode and the portion of the row electrode; and communicating elements are each provided between the first discharge area and the second discharge area for communication from the second discharge area to the first discharge area. 
   In the PDP structure based on this superior idea, for the generation of an image, a reset discharge is caused, in each second discharge area facing the portion of the column electrode, between the portion of the column electrode and the portion of the row electrode in the row electrode pair formed on the same substrate as the column electrode is formed on. 
   This reset discharge triggers the generation/erasure of a wall charge on/from the dielectric layer facing the first discharge area by way of the communicating element provided between the second discharge area and the first discharge area. 
   Next, an addressing discharge generated selectively between the portion of the column electrode and the portion of the row electrode in the row electrode pair is produced in the second discharge area facing the portion of the column electrode. Charged particles generated in the second discharge area by means of the addressing discharge flow into the first discharge area through the communicating element. Thus, the first discharge areas having a wall charge (lighted cells) and the first discharge areas having no wall charge (non-lighted cells) are distributed over the panel surface in accordance with the image to be generated. 
   Then, in each of the first discharge area having a wall charge (i.e. in each of the lighted cells), a sustain discharge for light emission for the generation of the image is produced between the mutually facing portions of the row electrodes constituting the row electrode pair. 
   With the foregoing PDP, because the row electrode pairs and the column electrodes are formed on one of the pair of substrates facing each other with the discharge space in between, it is possible to simplify the manufacturing process to substantially reduce the manufacturing costs. 
   Because the reset discharge and the addressing discharge are caused in the second discharge area which is formed independently of the first discharge area which is provided for producing the sustain discharge for light emission for the generation of the image, it is possible to employ a configuration capable of preventing the emissions caused by the reset discharge and the addressing discharge from leaking toward the display screen of the panel for the prevention of a reduction in the dark-light contrast of the image. 
   Further, there is no need to provide a phosphor layer in the second discharge area in which the addressing discharge is produced. This makes it possible to avoid the effects of the phosphor layer on: the discharge characteristics varying among the individual phosphor materials of the colors of the phosphor layers; a change in discharge voltage caused by the phosphor layer, for example, caused by variations in the thickness of the phosphor layer occurring when the phosphor layer is formed in the manufacturing process; and the like. This ensures the uniformity of the addressing discharge characteristics in each second discharge area, to improve a margin in the addressing discharge. 
   Still further, the first discharge area is only required to produce the sustain discharge. For this reason, the limitations imposed on the structure of the first discharge area are decreased, resulting in the possibility of optimizing the structure of the first discharge area for the sustain discharge. 
   The terms and description used herein are set forth by way of illustration only and are not meant as limitations. Those skilled in the art will recognize that numerous variations are possible within the spirit and scope of the invention as defined in the following claims.