Patent Publication Number: US-10783933-B2

Title: Semiconductor memory device

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application is a continuation of U.S. patent application Ser. No. 15/909,502, filed on Mar. 1, 2018, which is based upon and claims the benefit of priority from Japanese Patent Application No. 2017-060041, filed Mar. 24, 2017, and Japanese Patent Application No. 2017-161382, filed Aug. 24, 2017, the entire contents of each of which are incorporated herein by reference. 
    
    
     FIELD 
     Embodiments described herein relate generally to a semiconductor memory device. 
     BACKGROUND 
     A magnetic random access memory (MRAM) is a memory device in which a magnetic element having magnetoresistive effect is used in a memory cell storing information and is gaining attention as a next-generation memory device having characteristics of high-speed operation, a large capacity, and non-volatility. Research and development in terms of replacing a volatile memory such as the DRAM and the SRAM with the MRAM is progressing. In this case, causing the MRAM to be operated by the same specifications as those of the DRAM and the SRAM is desirable for reducing development cost and allowing replacement of the DRAM and the SRAM to be performed smoothly. 
    
    
     
       DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a block diagram illustrating a semiconductor memory device according to a first embodiment. 
         FIG. 2  is a block diagram illustrating a bank of the semiconductor memory device according to the first embodiment. 
         FIG. 3  is a block diagram illustrating a memory cell MC of the semiconductor memory device according to the first embodiment. 
         FIG. 4  is a block diagram illustrating a sense circuit of the semiconductor memory device according to the first embodiment. 
         FIG. 5  is another block diagram illustrating the sense circuit of the semiconductor memory device according to the first embodiment. 
         FIG. 6  is a layout diagram illustrating wiring of power source lines of the semiconductor memory device according to the first embodiment. 
         FIG. 7  is a cross-sectional view taken along the A-A line of  FIG. 6 . 
         FIG. 8  is a cross-sectional view taken along the B-B line of  FIG. 6 . 
         FIG. 9  is a flowchart illustrating a read operation of the semiconductor memory device according to the first embodiment. 
         FIG. 10  is a waveform diagram illustrating a voltage waveform at the time of the read operation of the semiconductor memory device according to the first embodiment. 
         FIG. 11  is a layout diagram illustrating wiring of power source lines of a semiconductor memory device according to a comparative example of the first embodiment. 
         FIG. 12  is a timing diagram illustrating a read operation carried out in two blocks of a semiconductor memory device. 
         FIG. 13  is a waveform diagram illustrating a voltage waveform at the time of the read operation of the semiconductor memory device according to the comparative example of the first embodiment. 
         FIG. 14  is another waveform diagram illustrating the voltage waveform at the time of the read operation of the semiconductor memory device according to the comparative example of the first embodiment. 
         FIG. 15  is a layout diagram illustrating wiring of power source lines of a semiconductor memory device according to a modification example 1 of the first embodiment. 
         FIG. 16  is a layout diagram illustrating wiring of power source lines of a semiconductor memory device according to a modification example 2 of the first embodiment. 
         FIG. 17  is a layout diagram illustrating wiring of power source lines of a semiconductor memory device according to a modification example 3 of the first embodiment. 
         FIG. 18  is a layout diagram illustrating wiring of power source lines of a semiconductor memory device according to a modification example 4 of the first embodiment. 
         FIG. 19  is a layout diagram illustrating wiring of power source lines of a semiconductor memory device according to a modification example 5 of the first embodiment. 
         FIG. 20  is a layout diagram illustrating wiring of power source lines of a semiconductor memory device according to a second embodiment. 
         FIG. 21  is a cross-sectional view taken along the C-C line of  FIG. 20 . 
         FIG. 22  is a cross-sectional view taken along the D-D line of  FIG. 20 . 
         FIG. 23  is a layout diagram illustrating wiring of power source lines of a semiconductor memory device according to a modification example 1 of the second embodiment. 
         FIG. 24  is a layout diagram illustrating wiring of power source lines of a semiconductor memory device according to a modification example 2 of the second embodiment. 
         FIG. 25  is a layout diagram illustrating wiring of power source lines of a semiconductor memory device according to a modification example 3 of the second embodiment. 
         FIG. 26  is a layout diagram illustrating wiring of power source lines of a semiconductor memory device according to a modification example 4 of the second embodiment. 
         FIG. 27  is a layout diagram illustrating wiring of power source lines of a semiconductor memory device according to a modification example 5 of the second embodiment. 
         FIG. 28  is a block diagram illustrating a controller of a semiconductor memory device according to a third embodiment. 
         FIG. 29  is a waveform diagram illustrating waveforms of a read operation carried out normally in the semiconductor memory device according to the third embodiment. 
         FIG. 30  is a waveform diagram illustrating waveforms of a read operation subject to instantaneous stopping in the semiconductor memory device according to the third embodiment. 
         FIG. 31  is a block diagram illustrating a sense amplifier/write driver of a semiconductor memory device according to a fourth embodiment. 
         FIG. 32  is a circuit diagram illustrating a relationship between a memory array and a write driver of the semiconductor memory device according to the fourth embodiment. 
         FIG. 33  is a circuit diagram illustrating the write driver of the semiconductor memory device according to the fourth embodiment. 
         FIG. 34  is a waveform diagram illustrating waveforms in a write operation of the semiconductor memory device according to the fourth embodiment. 
         FIG. 35  is a circuit diagram illustrating a write driver of a semiconductor memory device according to a comparative example of the fourth embodiment. 
         FIG. 36  is a waveform diagram illustrating waveforms in a write operation of the semiconductor memory device according to the comparative example of the fourth embodiment. 
         FIG. 37  is a circuit diagram illustrating a write driver of a semiconductor memory device according to a modification example of the fourth embodiment. 
         FIG. 38  is a waveform diagram illustrating waveforms in a write operation of the semiconductor memory device according to the modification example of the fourth embodiment. 
         FIG. 39  is a waveform diagram illustrating waveforms in a case where voltages of bit lines BL and source lines SL related to the fourth embodiment are caused to be in a floating state in a period during which a write operation and a read operation are not performed. 
         FIG. 40  is another waveform diagram illustrating waveforms in a case where voltages of bit lines BL and source lines SL related to the fourth embodiment are caused to be in a floating state in a period during which a write operation and a read operation are not performed. 
         FIG. 41  is another waveform diagram illustrating waveforms in a case where voltages of bit lines BL and source lines SL related to the fourth embodiment are caused to be in a floating state in a period during which a write operation and a read operation are not performed. 
     
    
    
     DETAILED DESCRIPTION 
     In general, according to one embodiment, a semiconductor memory device includes a power source pad, a first bank that includes a plurality of memory cells, a second bank that includes a plurality of memory cells, wherein the first bank is between the power source pad and the second bank, first power supply lines that are connected to the power source pad and supply power to the first bank and not to the second bank, and second power supply lines that are connected to the power source pad, pass over the first bank, and supply power to the second bank and not to the first bank. 
     In the following, description will be made of embodiments with reference to the drawings. In the following description, elements having substantially the same function and configuration are assigned the same reference numerals. The “_number” after the reference numeral is used for distinguishing elements having the same function and configuration from each other. In a case where there is no need to distinguish elements, these elements are referenced by the reference numeral without the suffix “_number”. For example, in a case where there is no need to distinguish elements  10 _ 1  and  10 _ 2 , these elements are collectively referenced as element  10 . 
     The drawings are schematic and it is to be noted that a relationship between a thickness and plane dimension, a ratio of thickness of each layer, and the like are different from actual ones. Accordingly, a specific thickness or dimension should be determined after taking into account the following description. Also, the dimension relationship and ratios in the drawings may be different in different figures. 
     In the present specification, for convenience of explanation, an XYZ orthogonal coordinate system is introduced. In the coordinate system, two directions parallel to an upper surface of a semiconductor substrate and perpendicular to each other are set as the X-direction (D 1 ) and the Y-direction (D 2 ), and a direction perpendicular to both of the X-direction and the Y-direction, that is, a stacking direction of respective layers is set as the Z-direction (D 3 ). 
     1 First Embodiment 
     1-1 Configuration 
     1-1-1 Semiconductor Memory Device 
     First, a basic configuration of a semiconductor memory device according to a first embodiment will be schematically described using  FIG. 1 . 
     A semiconductor memory device  1  according to the first embodiment includes a core circuit  10   a  and a peripheral circuit  10   b.    
     The core circuit  10   a  includes a memory area  11 , a column decoder  12 , a word line driver  13 , and a row decoder  14 . The memory area  11  includes a plurality of banks BK (two banks of BK 0  and BK 1  in the example of  FIG. 1 ). In one example, the banks BK 0  and BK 1  are capable of being independently activated. Also, in a case where the banks BK 0  and BK 1  are not distinguished from each other, they are simply referred to as bank BK. Details of the bank BK will be described later. 
     The column decoder  12  recognizes a command or an address by a command address signal CA and controls selection of a bit line BL and a source line SL based on an external control signal. 
     The word line driver  13  is disposed on at least one side of the bank BK. The word line driver  13  is configured to apply a voltage to a selected word line WL through a main word line MWL at the time of data read or data write. 
     The row decoder  14  decodes an address of the command address signal CA supplied from the command address input circuit  15 . More specifically, the row decoder  14  supplies the decoded row address to the word line driver  13 . With this, the word line driver  13  can apply a voltage to the selected word line WL. 
     The peripheral circuit  10   b  includes the command address input circuit  15 , a controller  16 , and an IO circuit  17 . 
     Various external control signals, for example, a chip select signal CS, the clock signal CK, a clock enable signal CKE, a command address signal CA, and the like are input to the command address input circuit  15  from a memory controller (also referred to herein as a host device)  2 . The command address input circuit  15  transfers the command address signal CA to the controller  16 . 
     The controller  16  identifies the command and the address. The controller  16  controls the semiconductor memory device  1 . 
     The IO circuit  17  temporarily stores input data input from a memory controller  2  through a data line DQ or output data read from a selected bank onto the data line DQ. The input data is written into a memory cell of the selected bank. 
     1-1-2 Bank BK 
     A basic configuration of a bank BK of the semiconductor memory device according to the first embodiment will be described using  FIG. 2 . 
     The bank BK includes a memory array  20   a , a sense amplifier/write driver (SA/WD)  20   b , and a page buffer  20   c.    
     The memory array  20   a  is configured in such a way that a plurality of memory cells MC are arranged in a matrix pattern. In the memory array  20   a , a plurality of word lines WL 0  to WLi−1 (i is an integer of 2 or more), a plurality of bit lines BL 0  to BLj−1 (j is an integer of 2 or more), and a plurality of source lines SL 0  to SLj−1 are provided. One row of the memory array  20   a  is connected to a single word line WL and one column of the memory array  20   a  is connected to a pair of lines that include one bit line BL and one source line SL. 
     The memory cell MC is configured with a magnetic tunnel junction (MTJ) element  30  and a selection transistor  31 . The selection transistor  31  is an N-channel MOSFET. 
     One end of the MTJ element  30  is connected to the bit line BL and the other end thereof is connected to the drain of the selection transistor  31 . The gate of the selection transistor  31  is connected to the word line WL and the source thereof is connected to the source line SL. 
     The sense amplifier/write driver  20   b  is disposed in a bit line direction of the memory array  20   a . The sense amplifier/write driver  20   b  includes a sense amplifier and a write driver. The sense amplifier/write driver  20   b  detects the current flowing in the memory cell MC that is connected to the bit line BL through a global bit line GBL and to a selected word line WL through a main word line MWL, to read data stored in the memory cell. The write driver causes the current to flow in the memory cell MC that is connected to the bit line BL through the global bit line GBL, to the source line SL through the global source line GSL and to the selected word line WL through the main word line MWL, to allow data to be written. The sense amplifier/write driver  20   b  controls the bit line BL and the source line SL based on a control signal from the controller  16 . Data transfer between the sense amplifier/write driver  20   b  and the data line DQ is performed through the IO circuit  17 . 
     The page buffer  20   c  temporarily holds data read from the memory array  20   a  or write data received from memory controller  2 . Writing of data into the memory array  20   a  is performed in units of a plurality of memory cells known as a “page”. As such, the unit of writing into the memory array  20   a  is a page. The page buffer  20   c  according to the first embodiment is provided for each bank BK and has a storage capacity enough to temporarily store data of all pages of the bank BK. 
     Also, the configuration of the bank BK described above is an example and the bank BK may adopt other configurations. 
     1-1-3 Memory Cell MC 
     Next, a configuration of a memory cell MC of the semiconductor memory device according to the first embodiment will be schematically described using  FIG. 3 . As illustrated in FIG.  3 , one end of the MTJ element  30  of the memory cell MC according to the first embodiment is connected to the bit line BL and the other end thereof is connected to one end of the selection transistor  31 . The other end of the selection transistor  31  is connected to the source line SL. The MTJ element  30  that employs the tunneling magnetoresistive (TMR) effect has a stacked structure including two ferromagnetic layers F and P and a nonmagnetic layer (e.g., tunnel insulating film) B sandwiched between the ferromagnetic layers, and stores digital data by magnetoresistance change due to spin-polarized tunneling effects. The MTJ element  30  can take a low resistance state and a high resistance state by magnetization alignment of two ferromagnetic layers F and P. For example, when the low resistance state is defined as data “0” and the high resistance state is defined as data “1”, 1-bit data can be recorded in the MTJ element  30 . Alternatively, the low resistance state may be defined as data “1” and the high resistance state may be defined as data “0”. 
     For example, the MTJ element  30  is formed by sequentially stacking a fixed layer (also referred to as a pinning layer) P, a tunnel barrier layer B, and a recording layer (also referred to as a free layer) F. The pinning layer P and the free layer F are formed of the ferromagnetic materials and the tunnel barrier layer B is an insulating film (for example, Al 2 O 3 , MgO). The pinning layer P is a layer of which a magnetization alignment direction is fixed, and the magnetization alignment direction of the free layer F is variable and data is stored depending on the direction of magnetization alignment direction of the free layer F. 
     When the current is made to flow in the direction of the arrow A 1  at the time of write, the direction of magnetization of the free layer F becomes anti-parallel with respect to the direction of magnetization of the pinning layer P and MTJ element  30  goes into a high resistance state (data “1”). When the current is made to flow in the direction of the arrow A 2  at the time of write, the directions of magnetization of the pinning layer P and the free layer F become parallel, and MTJ element  30  goes into a low resistance state (data “0”). As such, the MTJ element  30  is able to write different pieces of data by the direction in which the current flows. 
     1-1-4 Sense Amplifier/Write Driver 
     A sense amplifier/write driver  20   b  of the semiconductor memory device according to the first embodiment will be described using  FIG. 4 . 
     As illustrated in  FIG. 4 , the sense amplifier/write driver  20   b  includes a plurality of sense circuits  200 . The plurality of sense circuits  200  are provided for each global bit line. Each of the plurality of sense circuits  200  includes a pre-amplifier  210  and a sense amplifier (SA)  220 . 
     The pre-amplifier  210  supplies the cell current to the memory cell MC through the global bit line and the bit line and generates voltages V 1   st  and V 2   nd  based on the cell current. 
     The sense amplifier  220  determines data (DO, DOB) based on the voltages V 1   st  and V 2   nd  generated by the pre-amplifier  210 . 
     The pre-amplifier  210  and the sense amplifier  220  operate based on voltages VDD and VSS applied through a pad (not illustrated). 
     A further specific example of the sense amplifier/write driver  20   b  of the semiconductor memory device according to the first embodiment will be described using  FIG. 5 . A configuration of the sense amplifier/write driver  20   b  is not limited to that of  FIG. 5 . 
     As illustrated in  FIG. 5 , in the sense amplifier/write driver  20   b , a write driver (WD)  230  is connected to the bit line and the source line (which are denoted as “Cell Path”). 
     The sense circuit  200  includes, for example, transistors  221  and  223 , a first sample and hold circuit  222 , a second sample and hold circuit  224 , and a sense amplifier  225 . The sense amplifier  220  of  FIG. 4  corresponds to the sense amplifier  225 . 
     The first sample and hold circuit  222  holds the voltage acquired by the pre-amplifier  210  at the time of a first read operation (details will be described later). 
     The second sample and hold circuit  224  holds the voltage acquired by the pre-amplifier  210  at the time of a second read operation (details will be described later). 
     The sense amplifier  225  outputs data DO based on an output voltage V 1   st  from the first sample and hold circuit  222  and an output voltage V 2   nd  from the first sample and hold circuit  224 . As will be described later, the sense amplifier  225  determines data based on the first read operation and the second read operation. In a case where data of “0” is read at the time of the first read operation and also in a case where data of “0” is read at the time of the second read operation, the sense amplifier  225  performs the determination by providing an offset in determining data so that data of “0” can be correctly determined. 
     1-1-5 Layout 
     1-1-5-1 Wiring Layout 
     A power source wiring layout of the semiconductor memory device according to the first embodiment will be described using  FIG. 6 . Here, for simplicity, the pad for supplying the voltage VDD, the wiring for supplying the voltage VDD, the memory array  20   a , and the sense amplifier/write driver  20   b  are only illustrated. 
     As illustrated in  FIG. 6 , a bank BK 0  is provided so as to be adjacent in the D 2  direction to the power source pad PDV that supplies the voltage VDD. The bank BK 0  is sandwiched between the power source pad PDV and the bank BK 1  in the D 2  direction. That is, the bank BK 0  is provided in the vicinity of the power source pad PDV and the bank BK 1  is provided far away from the power source pad PDV. 
     The power source pad PDV supplies the voltage VDD to the sense amplifier/write driver  20   b  through the power source wiring VDL. 
     The power source wiring VDL connected to the sense amplifier/write driver  20   b  of the bank BK 0  will be described. 
     The power source pad PDV is connected to a power source wiring VDL 0  through a contact C 0 . 
     The power source wiring VDL 0  extends in the D 1  direction. The power source wiring VDL 0  is connected to power source wirings VDL 1 _ 0  to VDL 1 _ x  through contacts C 1 _ 0  to C 1 _ x  (x is an integer). 
     The power source wirings VDL 1 _ 0  to VDL 1 _ x  extend in the D 2  direction. The power source wirings VDL 1 _ 0  to VDL 1 _ x  are connected to the power source wiring VDL 3  through the contacts C 3 _ 0  to C 3 _ x.    
     The power source wiring VDL 3  extends in the D 1  direction. The power source wiring VDL 3  is connected to the sense amplifier/write driver  20   b  of the bank BK 0  through a contact (not illustrated). 
     The power source wiring VDL connected to the sense amplifier/write driver  20   b  of the bank BK 1  will be described. 
     The power source wiring VDL 0  is connected to respective power source wirings VDL 2 _ 0  to VDL 2 _ x  through respective contacts C 2 _ 0  to C 2 _ x.    
     The power source wirings VDL 2 _ 0  to VDL 2 _ x  extend in the D 2  direction so as to be connected to the sense amplifier/write driver  20   b  of the bank BK 1  without being connected to the bank BK 0 . The power source wirings VDL 2 _ 0  to VDL 2 _ x  are connected to the power source wiring VDL 6  through contacts C 7 _ 0  to C 7 _ x.    
     The power source wiring VDL 6  extends in the D 1  direction. The power source wiring VDL 6  is connected to the sense amplifier/write driver  20   b  of the bank BK 1  through a contact (not illustrated). 
     The power source wirings VDL 2 _ 0  to VDL 2 _ x  are connected to power source wirings VDL 4 _ 0  to VDL 4 _ x  through contacts C 4 _ 0  to C 4 _ x , respectively. 
     The power source wirings VDL 4 _ 0  to VDL 4 _ x  extend in the D 1  direction. The power source wirings VDL 4 _ 0  to VDL 4 _ x  are connected to power source wirings VDL 5 _ 0  to VDL 5 _ x  through contacts C 5 _ 0  to C 5 _ x , respectively. 
     The power source wirings VDL 5 _ 0  to VDL 5 _ x  extend in the D 2  direction. The power source wirings VDL 5 _ 0  to VDL 5 _ x  are connected to a power source wiring VDL 6  through contacts C 6 _ 0  to C 6 _ x , respectively. 
     1-1-5-2 Cross-Section Taken Along A-A 
     Cross-section taken along A-A of  FIG. 6  will be described using  FIG. 7 . Here, for simplicity, the insulating layer covering respective wirings is not illustrated. Elements depicted in  FIG. 7  that are obscured by objects in the cross-section taken along A-A of  FIG. 6 , are illustrated by a broken line. 
     First, the memory array  20   a  of the block BK 0  will be described. As described above, the memory array  20   a  of the block BK 0  includes a plurality of memory cells. Here, for simplicity, only a single memory cell provided in the memory array  20   a  of the block BK 0  is illustrated. 
     Specifically, impurity regions  101   a  and  101   b  are provided in a surface region of the semiconductor substrate  100   a . A channel region is provided between a region sandwiched between the surface region of the semiconductor substrate  100   a  and the impurity regions  101   a  and  101   b . An insulating film  102  is provided above the channel region and a control gate electrode  103  (word line WL) is provided above the insulating film  102 . As such, the selection transistor  31  is configured with the impurity regions  101   a  and  101   b , the channel region, the insulating film  102 , and the control gate electrode  103 . 
     A layer in which the word line WL is provided is denoted as a first wiring layer (1st ML). 
     A contact  104  made of a conductor is provided on the impurity region  101   a  and the MTJ element  30  is provided on the contact  104 . A contact  105  made of a conductor is provided on the MTJ element  30  and a wiring layer  106  (bit line BL) made of a conductor and extending in the D 2  direction is provided on the contact  105 . A contact  107  made of a conductor is provided on the impurity region  101   b  and a wiring layer (source line SL) made of a conductor and extending in the D 2  direction is provided on the contact  107 . As such, the memory cell MC is configured with the selection transistor  31 , the contact  104 , the MTJ element  30 , the contact  105 , and the contact  107 . 
     A layer in which the bit line BL and the source line SL is provided is denoted by a second wiring layer (2nd ML). The second wiring layer is located at a position higher than the first wiring layer in the D 3  direction. 
     Above the wiring layer  106 , the wiring layer  108  (main word line MWL) extending in the direction D 1  is provided. 
     A layer in which the main word line MWL is provided is denoted by a third wiring layer (3rd ML). The third wiring layer is located at a position higher than the second wiring layer in the D 3  direction. 
     Here, for simplicity, description is given for a single memory cell MC. However, the plurality of memory cells MC as described above are provided in the memory array  20   a  of the block BK 0 . 
     Subsequently, the sense amplifier/write driver  20   b  of the block BK 0  will be described. Here, for simplicity, a single transistor provided in the sense amplifier/write driver  20   b  of the block BK 0  is illustrated. 
     Specifically, impurity regions  101   c  and  101   d  are provided in surface region of the semiconductor substrate  100   a . A channel region is provided between a region sandwiched between the surface region of the semiconductor substrate  100   a  and the impurity regions  101   c  and  101   d . An insulating film  109  is provided on the channel region and a control gate electrode  110  is provided on the insulating film  109 . As such, the transistor is configured with the impurity regions  101   c  and  101   d , the channel region, the insulating film  109 , and the control gate electrode  110 . 
     A contact  111  made of a conductor is provided on the impurity region  101   c . A wiring layer  112  made of a conductor is provided on the contact  111 . The wiring layer  112  is located at the second wiring layer. A contact  113  made of a conductor is provided on the wiring layer  112  and a wiring layer  114  made of a conductor is provided on the contact  113 . The wiring layer  114  is located at the third wiring layer. A contact  115  made of a conductor is provided on a wiring layer  114  and a wiring layer  116  (power source wiring VDL 1 ) made of a conductor and extend in the D 2  direction is provided on the contact  115 . 
     A layer in which a power source wiring VDL 1  is provided is denoted as a fourth wiring layer (4th ML). The fourth wiring layer is located at a position higher than the third wiring layer in the D 3  direction. 
     In the above-description, description was made on the memory array  20   a  and the sense amplifier/write driver  20   b  of the block BK 0 . 
     A similar configuration may also be adopted for the memory array  20   a  and the sense amplifier/write driver  20   b  of the block BK 1 . 
     In the above-description, when the semiconductor substrate  100   a  is replaced with the semiconductor substrate  100   b  and the power source wiring VDL 1  is replaced with the power source wiring VDL 5 , the above-description applies to that for the memory array  20   a  and the sense amplifier/write driver  20   b  of the block BK 1 . 
     As illustrated in  FIG. 6  and  FIG. 7 , the power source wiring VDL 1  and the power source wiring VDL 5  are electrically connected to each other in the power source wiring VDL 0 , but are not directly connected to each other. 
     1-1-5-3 Cross-Section Taken Along B-B 
     Cross-section taken along B-B of  FIG. 6  will be described using  FIG. 8 . Here, for simplicity, the insulating layer covering respective wirings is not illustrated. Elements depicted in  FIG. 8  that are obscured by objects in the cross-section taken along B-B of  FIG. 6 , are illustrated by a broken line. 
     Basic description of the block BK 0  and the block BK 1  is similar to that described in conjunction with  FIG. 7 . A difference between  FIG. 7  and  FIG. 8  is that the power source wiring VDL 2  passes over the block BK 0 , but is not directly connected to the block BK 0 . 
     As illustrated in  FIG. 6  to  FIG. 8 , the power source wiring connected to the bank BK 0  and the power source wiring connected to the bank BK 1  are connected in the vicinity of the power source pad PDV. For that reason, the noise generated in the sense amplifier/write driver  20   b  of the bank BK 0  is absorbed by the power source pad PDV and does not influence on the sense amplifier/write driver  20   b  of the bank BK 1 . Similarly, the noise generated in the sense amplifier/write driver  20   b  of the bank BK 1  is absorbed by the power source pad PDV and does not influence on the sense amplifier/write driver  20   b  of the bank BK 0 . 
     A distance from the bank BK 1  to the power source pad PDV is longer compared to that from the bank BK 0  thereto. For that reason, the number of the power source wirings connected to the bank BK 1  is twice the number of the power source wirings connected to the bank BK 0  so that the voltage supplied to the bank BK 1  is not lower than the voltage supplied to the bank BK 0 . In the first embodiment, for simplicity, the number of the power source wirings connected to the bank BK 1  is set to twice the number of the power source wirings connected to the bank BK 0 . However, a configuration in which the number of power source wirings connected to the bank BK 1  is greater by any amount than the number of power source wirings connected to the bank BK 0  may be employed. 
     1-2 Operation 
     As described above, the MTJ element of the semiconductor memory device according to the first embodiment stores data using change in a resistance value. In a case where information stored in such a MTJ element is read, the semiconductor memory device causes a read current (also denoted by a cell current) to flow to the MTJ element. The semiconductor memory device converts a resistance value of the MTJ element into a current value or a voltage value and compares the converted voltage or current value with a reference value so as to make it possible to determine a resistance state. 
     However, when variation in resistance of the MTJ element is increased, there is a possibility that intervals of resistance value distributions of “0” state and “1” state are made narrower. For that reason, in a read method in which a reference value is set between the resistance value distributions and a state of the MTJ element is determined based on magnitude with respect to the reference value, a read margin is remarkably reduced. 
     Here, with respect to such an event, as a read method, there is a self-reference read method in which its own data is rewritten to generate a reference signal and data read is performed based on the generated signal. 
     In the following embodiment, in a case where the self-reference read method is used as a read method, a read operation of the semiconductor memory device will be described. 
     1-2-1 Outline of Read Operation 
     An outline of a read operation of a memory system according to the first embodiment will be described using  FIG. 9 . In the present description,  FIG. 4  and  FIG. 5  will be referenced. 
     [Step S 1001 ] 
     The memory controller  2  issues an activate command and a read command to the semiconductor memory device  1 . 
     When the activate command and the read command are received from the memory controller  2 , the semiconductor memory device  1  performs a first read operation (1st READ) on a read target memory cell. The sense circuit  200  stores a resistance state of the read target memory cell, by the first read operation, as voltage information (signal voltage) V 1   st.    
     [Step S 1002 ] 
     The semiconductor memory device  1  performs a write operation of “0” (WRITE “0”) on the memory cell which is a target of the first read operation. With this, the memory cell which is the target of the first read operation is overwritten by data of “0”. This operation generates V 2   nd , which will be described later, and thus the memory cell is set to a reference state (here, “0”). That is, the write operation may be described as a referencing operation. 
     [Step S 1003 ] 
     The semiconductor memory device  1  performs a second read operation (2nd READ) on the memory cell which is the target of the first read operation. The sense circuit  200  generates signal voltage V 2   nd  by the second read operation. 
     [Step S 1004 ] 
     The sense circuit  200  determines a result of the V 1   st  generated by Step S 1001  based on the V 2   nd  generated by Step S 1003 . Specifically, the sense circuit  200  compares the V 1   st  and the V 2   nd  to determine data stored in the memory cell. 
     After data stored in the memory cell is determined, the controller  16  writes back data to the memory cell. With this, it is possible to restore data stored in the memory cell from the beginning in the memory cell. 
     1-2-2 Waveform of Voltage 
     Waveforms of the voltage at the time of the read operation will be described using  FIG. 10 . 
     As illustrated in  FIG. 10 , in the semiconductor memory device  1 , when the first read operation is performed, the first read result is stored in the first sample and hold circuit  222  and the voltage of V 1   st  is raised (time T 0  to time T 1 ). 
     The semiconductor memory device  1  performs the write operation of “0” after the first read operation (time T 1  to time T 2 ). 
     In the semiconductor memory device  1 , a second read result is stored in the second sample and hold circuit  224  and the voltage of V 2   nd  is raised (time T 2  to time T 3 ). 
     The sense amplifier  225  performs determination of data based on the voltages V 1   st  and V 2   nd  (time T 4 ). 
     As described above, data is determined by performing the read operation twice in the read operation of the memory system according to the first embodiment. 
     1-3 Effect 
     According to the embodiment described above, the power source wiring connected to the bank BK 0  and the power source wiring connected to the bank BK 1  are connected in the vicinity of the power source pad PDV. For that reason, the noise generated in the sense amplifier/write driver  20   b  of the bank BK 0  or the bank BK 1  is absorbed by the power source pad PDV and does not influence on the sense amplifier/write driver  20   b  of another bank BK. 
     Here, the comparative example will be described in order to make it easy to understand the effect of the first embodiment. 
     A power source wiring layout of a semiconductor memory device according to a comparative example will be described using  FIG. 11 . Here, for simplicity, the pad for supplying the voltage VDD, the wiring for supplying the voltage VDD, the memory array, and the sense amplifier/write driver  20   b  are only illustrated. 
     As illustrated in  FIG. 11 , the power source wiring VDL 7 _ 0  to VDL 7 _ x  extend in the D 2  direction. The power source wirings VDL 7 _ 0  to VDL 7 _ x  are connected to the power source wiring VDL 3  through the contacts C 3 _ 0  to C 3 _ x . The power source wirings VDL 7 _ 0  to VDL 7 _ x  are connected to the power source wiring VDL 6  through the contacts C 6 _ 0  to C 6 _ x.    
     As such, the power source wiring connected to the bank BK 0  and the power source wiring connected to the bank BK 1  are used in common in the semiconductor memory device according to the comparative example. 
     In the meantime, different banks BK may be operated simultaneously in the semiconductor memory device. 
     For example, as illustrated in  FIG. 12 , timing of the second read operation for the bank BK 0  and timing of the first second read operation for the bank BK 1  overlap each other. 
     In this case, there is a possibility that the noise occurs in the bank BK 1  during the operation of the bank BK 0 . Similarly, there is a possibility that the noise occurs in the bank BK 0  during the operation of the bank BK 1 . 
     Here, waveforms in a case where noise is received from an adjacent bank during a read operation will be described. 
     In  FIG. 13 , waveforms in a case where the adjacent bank is activated during the first read operation are illustrated. 
     As illustrated in  FIG. 13 , in a case where the adjacent bank is activated during the first read operation, as shown by the broken line in  FIG. 13 , a voltage value is stored in the sample and hold circuit  222  while the V 1   st  is lowered. In this case, there is a possibility that the sense amplifier  225  is not able to properly determine data. 
     In  FIG. 14 , waveforms in a case where the adjacent bank is activated during the second read operation are illustrated. 
     As illustrated in  FIG. 14 , in a case where the adjacent bank is activated during the second read operation, as shown by the broken line in  FIG. 14 , a voltage value is stored in the sample and hold circuit  224  while the V 2   nd  is lowered. In this case, there is a possibility that the sense amplifier  225  is not able to properly determine data. 
     As such, in the semiconductor memory device according to the comparative example, there is a possibility that data is not able to be correctly determined, due to the influence by the adjacent bank. 
     As described above, in the semiconductor memory device, the read operation is performed twice in order to read data from the memory cell. For that reason, the first read operation and the second read operation preferably operate in the same operation environment. 
     However, when only the operation of either of the first read operation and the second read operation is influenced by the noise generated by another adjacent bank, there is a possibility that data is not able to be properly read. 
     In the semiconductor memory device according to the embodiment described above, the power source wiring connected to the bank BK 0  and the power source wiring connected to the bank BK 1  are connected in the vicinity of the power source pad PDV. The power source pad PDV is able to absorb the noise and thus, power source noise generated by the bank BK does not influence on another adjacent bank BK. For that reason, even when the operation illustrated in  FIG. 12  is performed, the read operation can be favorably performed. 
     1-4 Modification Example 
     1-4-1 Modification Example 1 
     A power source wiring layout of the semiconductor memory device according to the modification example 1 of the first embodiment will be described using  FIG. 15  of the modification example 1. 
     The difference between the power source wiring layout of the semiconductor memory device according to the modification example 1 of the first embodiment and the power source wiring layout of the semiconductor memory device according to the first embodiment is that a power supply circuit  300  is further added. 
     Specifically, as illustrated in  FIG. 15 , a power supply circuit  300   a  is provided between the power source wiring VDL 0  and the power source wiring VDL 1 . A power supply circuit  300   b  is provided between the power source wiring VDL 0  and the power source wiring VDL 2 . 
     Any configuration of the power supply circuit  300   a  may be employed as long as it allows the power source voltage to be transferred from the power source wiring VDL 0  to the power source wiring VDL 1 . Similarly, any configuration of the power supply circuit  300   b  may be employed as long as it allows the power source voltage to be transferred from the power source wiring VDL 0  to the power source wiring VDL 2 . 
     1-4-2 Modification Example 2 
     A power source wiring layout of a semiconductor memory device according to the modification example 2 of the first embodiment will be described using  FIG. 16 . 
     A layout illustrated in  FIG. 16  may be employed. In  FIG. 15 , a single power source wiring VDL 1  is connected to a single power supply circuit  300   a . However, as illustrated in  FIG. 16 , a plurality of power source wirings VDL 1  may be connected to a single power supply circuit  300   a . Similarly, as illustrated in  FIG. 16 , a plurality of power source wirings VDL 2  may be connected to a single power supply circuit  300   b.    
     1-4-3 Modification Example 3 
     A power source wiring layout of a semiconductor memory device according to the modification example 3 of the first embodiment will be described using  FIG. 17 . 
     The difference between the power source wiring layout of the semiconductor memory device according to the modification example 3 of the first embodiment and the power source wiring layout of the semiconductor memory device according to the first embodiment is that the power source pad for the bank BK 0  and the power source pad for the bank BK 1  are electrically separated from each other. 
     As illustrated in  FIG. 17 , the first power source pad PDV 1  supplies the voltage VDD to the sense amplifier/write driver  20   b  of the bank BK 0  through the power source wiring VDL. 
     The first power source pad PDV 1  is connected to the power source wiring VDL 0 _ 0  through the contact C 0 _ 0 . 
     The power source wiring VDL 0 _ 0  extends in the D 1  direction. The power source wiring VDL 0 _ 0  is connected to respective power source wirings VDL 1 _ 0  to VDL 1 _ x  through respective contacts C 10 _ 0  to C 10 _ x.    
     As illustrated in  FIG. 17 , the second power source pad PDV 2  supplies the voltage VDD to the sense amplifier/write driver  20   b  of the bank BK 1  through the power source wiring VDL. 
     The second power source pad PDV 2  is connected to the power source wiring VDL 0 _ 1  through the contact C 0 _ 1 . 
     The power source wiring VDL 0 _ 1  extends in the D 1  direction. The power source wiring VDL 0 _ 1  is connected to respective power source wirings VDL 2 _ 0  to VDL 2 _ x  through respective contacts C 11 _ 0  to C 11 _ x.    
     1-4-4 Modification Example 4 
     A power source wiring layout of a semiconductor memory device according to the modification example 4 of the first embodiment will be described using  FIG. 18 . 
     The difference between the power source wiring layout of the semiconductor memory device according to the modification example 4 of the first embodiment and the power source wiring layout of the semiconductor memory device according to the modification example 3 of the first embodiment is that the power supply circuit  300  is further added. 
     Specifically, as illustrated in  FIG. 18 , the power supply circuit  300   a  is provided between the power source wiring VDL 0 _ 0  and the power source wiring VDL 1 . The power supply circuit  300   b  is provided between the power source wiring VDL 0 _ 1  and the power source wiring VDL 2 . 
     Any configuration of the power supply circuit  300   a  may be employed as long as it allows the power source voltage to be transferred from the power source wiring VDL 0 _ 0  to the power source wiring VDL 1 . Similarly, any configuration of the power supply circuit  300   b  may be employed as long as it allows the power source voltage to be transferred from the power source wiring VDL 0 _ 1  to the power source wiring VDL 2 . 
     1-4-5 Modification Example 5 
     A power source wiring layout of a semiconductor memory device according to the modification example 5 of the first embodiment will be described using  FIG. 19 . 
     A layout illustrated in  FIG. 19  may be employed. In  FIG. 18 , a single power source wiring VDL 1  is connected to a single power supply circuit  300   a . However, as illustrated in  FIG. 19 , a plurality of power source wirings VDL 1  may be connected to a single power supply circuit  300   a . Similarly, as illustrated in  FIG. 19 , a plurality of power source wirings VDL 2  may be connected to a single power supply circuit  300   b.    
     2 Second Embodiment 
     Description will be made on a second embodiment. In the second embodiment, another example of the power source wiring layout of the semiconductor memory device will be described. The basic operations of the semiconductor memory device according to the second embodiment are the same as those of the semiconductor memory device according to the first embodiment described above. Accordingly, description of the first embodiment that also applies to the second embodiment and matters that are capable of being analogized from the description of the first embodiment above will be omitted. 
     2-1 Layout 
     2-1-1 Wiring Layout 
     A power source wiring layout of the semiconductor memory device according to the second embodiment will be described using  FIG. 20 . Here, for simplicity, the pad for supplying the voltage VDD, the wiring for supplying the voltage VDD, the memory array  20   a , and the sense amplifier/write driver  20   b  are only illustrated. 
     As illustrated in  FIG. 20 , the bank BK 0  is provided so as to be adjacent in the D 2  direction to the power source pad PDV that supplies the voltage VDD. The bank BK 0  is sandwiched between the power source pad PDV and the bank BK 1  in the D 1  direction. That is, the bank BK 0  is provided in the vicinity of the power source pad PDV and the bank BK 1  is provided far away from the power source pad PDV. 
     The power source pad PDV supplies the voltage VDD to the sense amplifier/write driver  20   b  through the power source wiring VDL. 
     The power source wiring VDL connected to the sense amplifier/write driver  20   b  of the bank BK 0  will be described. 
     The power source pad PDV is connected to a power source wiring VDL 20  through a contact C 20 . 
     The power source wiring VDL 20  extends in the D 2  direction. The power source wiring VDL 20  is connected to power source wirings VDL 21 _ 0  to VDL 21 _ y  through contacts C 21 _ 0  to C 21 _ y  (y is an integer). 
     The power source wirings VDL 21 _ 0  to VDL 21 _ y  extend in the D 1  direction. The power source wiring VDL 21 _ 0  is connected to the power source wirings VDL 25 _ 0  to VDL 25 _ z  through the contacts C 23 _ 0 - 0  to C 23 _ 0 - z  (z is an integer). Similarly, the power source wiring VDL 21 _ y  is connected to the power source wirings VDL 25 _ 0  to VDL 25 _ z  through the contacts C 23 _ y - 0  to C 23 _ y - z . At least one of the power source wirings VDL 21 _ 0  to VDL 21 _ y  is preferably provided above the sense amplifier/write driver  20   b . In the present example, the power source wiring VDL 21 _ y  is provided above the sense amplifier/write driver  20   b.    
     The power source wirings VDL 25 _ 0  to VDL 25 _ z  extend in the D 2  direction. The power source wirings VDL 25 _ 0  to VDL 25 _ z  are connected to the power source wiring VDL 26  through the contacts C 28 _ 0  to C 28 _ z.    
     The power source wiring VDL 26  extends in the D 1  direction. The power source wiring VDL 26  is connected to the sense amplifier/write driver  20   b  of the bank BK 0  through a contact (not illustrated). 
     The power source wiring VDL connected to the sense amplifier/write driver  20   b  of the bank BK 1  will be described. 
     The power source wiring VDL 20  is connected to respective power source wirings VDL 22 _ 0  to VDL 22 _ y  through respective contacts C 22 _ 0  to C 22 _ y.    
     The power source wirings VDL 22 _ 0  to VDL 22 _ y  extend in the D 1  direction so as to be connected to the bank BK 1  without being connected to the bank BK 0 . The power source wiring VDL 22 _ 0  is connected to the power source wirings VDL 27 _ 0  to VDL 27 _ z  through contacts C 27 _ 0 - 0  to C 27 _ 0 - z . Similarly, the power source wiring VDL 22 _ y  is connected to the power source wirings VDL 27 _ 0  to VDL 27 _ z  through contacts C 27 _ y - 0  to C 27 _ y - z . At least one of the power source wirings VDL 22 _ 0  to VDL 22 _ y  is preferably provided above the sense amplifier/write driver  20   b . In the present example, the power source wiring VDL 22 _ y  is provided above the sense amplifier/write driver  20   b.    
     The power source wirings VDL 27 _ 0  to VDL 27 _ z  extend in the D 2  direction. The power source wirings VDL 27 _ 0  to VDL 27 _ z  are connected to the power source wiring VDL 28  through the contacts C 29 _ 0  to C 29 _ z.    
     The power source wiring VDL 28  extends in the D 1  direction. The power source wiring VDL 28  is connected to the sense amplifier/write driver  20   b  of the bank BK 1  through a contact (not illustrated). 
     The power source wirings VDL 22 _ 0  to VDL 22 _ y  are connected to respective power source wirings VDL 23 _ 0  to VDL 23 _ y  through respective contacts C 24 _ 0  to C 24 _ y    
     The power source wirings VDL 23 _ 0  to VDL 23 _ y  extend in the D 2  direction. The power source wiring VDL 23 _ 0  is connected to the power source wirings VDL 24 _ 0  to VDL 24 _ y  through contacts C 25 _ 0  to C 25 _ 0 . 
     The power source wirings VDL 24 _ 0  to VDL 24 _ y  extend in the D 1  direction. The power source wiring VDL 24 _ 0  is connected to the power source wirings VDL 27 _ 0  to VDL 27 _ z  through contacts C 26 _ 0 - 0  to C 26 _ 0 - z . Similarly, the power source wiring VDL 24 _ y  is connected to the power source wirings VDL 27 _ 0  to VDL 27 _ z  through contacts C 26 _ y - 0  to C 26 _ y - z . At least one of the power source wirings VDL 24 _ 0  to VDL 24 _ y  is preferably provided above the sense amplifier/write driver  20   b . In the present example, the power source wiring VDL 24 _ y  is provided above the sense amplifier/write driver  20   b.    
     2-1-2 Cross-Section Taken Along C-C 
     Cross-section taken along C-C of  FIG. 20  will be described using  FIG. 21 . Here, for simplicity, the insulating layer covering respective wirings is not illustrated. Elements depicted in  FIG. 21  that are obscured by objects in the cross-section taken along C-C of  FIG. 20 , are illustrated by a broken line. 
     Basic description on the block BK 0  is substantially similar to that described in  FIG. 6 .  FIG. 21  differs from  FIG. 7  in that the power source wiring and the main word line MWL are alternately provided in the third wiring layer. 
     2-1-3 Cross-Section Taken Along D-D 
     Cross-section taken along D-D of  FIG. 20  will be described using  FIG. 22 . Here, for simplicity, the insulating layer covering respective wirings is not illustrated. Elements depicted in  FIG. 22  that are obscured by objects in the cross-section taken along D-D of  FIG. 20 , are illustrated by a broken line. 
     In  FIG. 21 , only the power source wiring VDL 21  is connected to the power source wiring VDL 25 . However, in  FIG. 22 , two groups of wirings of the power source wirings VDL 22  and VDL 24  are connected to the power source wiring VDL 27 . 
     2-2 Effect 
     As illustrated in  FIG. 20  to  FIG. 22 , the power source wiring connected to the bank BK 0  and the power source wiring connected to the bank BK 1  are connected in the vicinity of the power source pad PDV. The number of the power source wirings connected to the bank BK 1  is twice the number of the power source wirings connected to the bank BK 0  so that the voltage supplied to the bank BK 1  is not lower than the voltage supplied to the bank BK 0 . In the first embodiment, for simplicity, the number of the power source wirings connected to the bank BK 1  is set to twice the number of the power source wirings connected to the bank BK 0 . However, a configuration in which the number of power source wirings connected to the bank BK 1  is greater by amount than the number of power source wirings connected to the bank BK 0  may be employed. 
     For that reason, the same effect as that of the first embodiment described above can be obtained. 
     2-3 Modification Example 
     2-3-1 Modification Example 1 
     A power source wiring layout of the semiconductor memory device according to the modification example 1 of the second embodiment will be described using  FIG. 23 . 
     The difference between the power source wiring layout of the semiconductor memory device according to the modification example 1 of the second embodiment and the power source wiring layout of the semiconductor memory device according to the second embodiment is that the power supply circuit  300  is further added. 
     Specifically, as illustrated in  FIG. 23 , the power supply circuit  300   a  is provided between the power source wiring VDL 20  and the power source wiring VDL 21 . The power supply circuit  300   b  is provided between the power source wiring VDL 20  and the power source wiring VDL 22 . 
     Any configuration of the power supply circuit  300   a  may be employed as long as it allows the power source voltage to be transferred from the power source wiring VDL 20  to the power source wiring VDL 21 . Similarly, any configuration of the power supply circuit  300   b  may be employed as long as it allows the power source voltage to be transferred from the power source wiring VDL 20  to the power source wiring VDL 22 . 
     2-3-2 Modification Example 2 
     A power source wiring layout of the semiconductor memory device according to the modification example 2 of the second embodiment will be described using  FIG. 24 . 
     A layout illustrated in  FIG. 24  may be employed. In  FIG. 23 , a single power source wiring VDL 21  is connected to a single power supply circuit  300   a . However, as illustrated in  FIG. 24 , a plurality of power source wirings VDL 21  may be connected to a single power supply circuit  300   a . Similarly, as illustrated in  FIG. 24 , a plurality of power source wirings VDL 22  may be connected to a single power supply circuit  300   b.    
     2-3-3 Modification Example 3 
     A power source wiring layout of a semiconductor memory device according to the modification example 3 of the second embodiment will be described using  FIG. 25 . 
     The difference between the power source wiring layout of the semiconductor memory device according to the modification example 3 of the second embodiment and the power source wiring layout of the semiconductor memory device according to the second embodiment is that the power source pad for the bank BK 0  and the power source pad for the bank BK 1  are electrically separated from each other. 
     As illustrated in  FIG. 25 , the first power source pad PDV 1  supplies the voltage VDD to the sense amplifier/write driver  20   b  of the bank BK 0  through the power source wiring VDL. 
     The first power source pad PDV 1  is connected to the power source wiring VDL 20 _ 0  through the contact C 20 _ 0 . 
     The power source wiring VDL 20 _ 0  extends in the D 2  direction. The power source wiring VDL 20 _ 0  is connected to respective power source wirings VDL 21 _ 0  to VDL 21 _ y  through respective contacts C 21 _ 0  to C 21 _ y.    
     The second power source pad PDV 2  is connected to the power source wiring VDL 20 _ 1  through the contact C 20 _ 1 . 
     The power source wiring VDL 20 _ 1  extends in the D 2  direction. The power source wiring VDL 20 _ 1  is connected to respective power source wirings VDL 22 _ 0  to VDL 22 _ y  through respective contacts C 22 _ 0  to C 22 _ y.    
     2-3-4 Modification Example 4 
     A power source wiring layout of a semiconductor memory device according to the modification example 4 of the second embodiment will be described using  FIG. 26 . 
     The difference between the power source wiring layout of the semiconductor memory device according to the modification example 4 of the second embodiment and the power source wiring layout of the semiconductor memory device according to the modification example 3 of the second embodiment is that the power supply circuit  300  is further added. 
     Specifically, as illustrated in  FIG. 26 , the power supply circuit  300   a  is provided between the power source wiring VDL 20 _ 0  and the power source wiring VDL 21 . The power supply circuit  300   b  is provided between the power source wiring VDL 20 _ 1  and the power source wiring VDL 22 . 
     Any configuration of the power supply circuit  300   a  may be employed as long as it allows the power source voltage to be transferred from the power source wiring VDL 20 _ 0  to the power source wiring VDL 21 . Similarly, any configuration of the power supply circuit  300   b  may be employed as long as it allows the power source voltage to be transferred from the power source wiring VDL 20 _ 1  to the power source wiring VDL 22 . 
     2-3-5 Modification Example 5 
     A power source wiring layout of a semiconductor memory device according to the modification example 5 of the second embodiment will be described using  FIG. 27 . 
     A layout illustrated in  FIG. 27  may be employed. In  FIG. 26 , a single power source wiring VDL 21  is connected to a single power supply circuit  300   a . However, as illustrated in  FIG. 27 , a plurality of power source wirings VDL 21  may be connected to a single power supply circuit  300   a . Similarly, as illustrated in  FIG. 27 , a plurality of power source wirings VDL 22  may be connected to a single power supply circuit  300   b.    
     3 Third Embodiment 
     Description will be made on a third embodiment. In the third embodiment, a controller will be described. The basic operations of the semiconductor memory device according to the third embodiment are the same as those of the semiconductor memory device according to the first embodiment described above. Accordingly, description of the first embodiment that also applies to the second embodiment and matters that are capable of being easily analogized from the description of the first embodiment above will be omitted. 
     3-1 Controller 
     A controller of the semiconductor memory device according to the third embodiment will be described using  FIG. 28 . 
     Here, description will be made on the controller  16  that cuts a current path of a power source between the inside (e.g., semiconductor memory device) and the outside (e.g., memory controller), performs an operation up to a proper time point without using the power source voltage from the outside, and properly ends the operation at the time of instantaneous stopping of the memory controller. 
     In  FIG. 28 , a portion of the controller  16  is illustrated. As illustrated in  FIG. 28 , the controller  16  includes a voltage drop detector  40 , a voltage generation circuit  41 , a command system circuit  42 , and stabilizing capacitor  43 . 
     In a case where it is determined that “internal voltage VDD*int&lt;external voltage VDD*ext”, the voltage drop detector  40  determines that the external voltage has not dropped. In contrast, in a case where it is determined that “external voltage VDD*ext&lt;internal voltage VDD*int”, the voltage drop detector  40  determines that the external voltage has dropped. In a case where it is determined that the external voltage has dropped, the voltage drop detector  40  supplies a voltage drop detection signal of “H” level to the voltage generation circuit  41  and the command system circuit  42 . The internal voltage VDD*int is a voltage across the stabilizing capacitor  43 . The external voltage VDD*ext is a voltage supplied from the memory controller  2 . The external voltage VDD*ext is input to a non-inversion input terminal of the voltage drop detector  40  through a resistive element R 1  and a node N 1 . The internal voltage VDD*int is input to an inversion input terminal of the voltage drop detector  40  through a resistive element R 3  and a node N 2 . 
     The voltage generation circuit  41  generates the internal voltage VDD*int based on the external voltage VDD*ext. When the voltage drop detection signal of “H” level is received from the voltage drop detector  40 , the voltage generation circuit  41  blocks a current path through which the external voltage VDD*ext is received. With this, the voltage generation circuit  41  is able to prevent the internal voltage VDD*int from flowing back to a power source pad which supplies the external voltage VDD*ext. 
     The stabilizing capacitor  43  is sized such that it holds a sufficient amount of charge to allow, for example, a single read (which includes first read operation, write operation, second read operation, determination operation) to be performed even when the external voltage VDD*ext is not supplied. 
     The command system circuit  42  generates a signal for causing the sense circuit  200  or a write driver to operate. When the voltage drop detection signal of “H” level is received from the voltage drop detector  40 , the command system circuit  42  operates the semiconductor memory device  1  until the operation successfully completes. The command system circuit  42  operates so as block a command from being received until the operation successfully completes. 
     3-2 Operation 
     3-2-1 Normal Operation 
     A normal operation of the controller of the semiconductor memory device according to the third embodiment will be described using  FIG. 29 . In  FIG. 29 , the external voltage VDD*ext, the internal voltage VDD*int, an activate command (ACT) and a write command (Write) supplied from the memory controller  2 , a voltage drop detection signal, a signal SA Act for causing the sense circuit  200  to operate, and a signal WD Act for causing the write driver to operate are illustrated. Description will be made on a case where the external voltage VDD*ext does not drop. 
     When the activate command is received from the memory controller  2 , the controller  16  makes the signal SA Act go to the “H” level and operates the sense circuit  200  (time T 20  to time T 21 ). During the period of time T 20  to time T 21 , when a read command is received from the memory controller  2 , the controller  16  performs the first read operation. 
     Subsequently, when the activate command is received from the memory controller  2 , the controller  16  makes the signal SA Act go to the “H” level and operates the sense circuit  200  (time T 22  to time T 23 ). Thereafter, when a write command is received from the memory controller  2 , the controller  16  makes the signal WD Act go to the “H” level and operates the write driver (time T 23  to time T 25 ) to perform the write of “0”. 
     Thereafter, the controller  16  performs the second read operation and then the determination operation to end the read. 
     3-2-2 Operation at the Time of Instantaneous Stopping 
     An operation at the time of instantaneous stopping of the controller of the semiconductor memory device according to the third embodiment will be described using  FIG. 30 . 
     When the activate command is received from the memory controller  2 , the controller  16  makes the signal SA Act go to the “H” level and operates the sense circuit  200  (time T 30  to time T 31 ). During the period of time T 30  to time T 31 , when a read command is received from the memory controller  2 , the controller  16  performs the first read operation. 
     At time T 31 , instantaneous stopping occurs and the external voltage VDD*ext drops. With this, at time T 32 , the voltage drop detector  40  detects drop of the external voltage VDD*ext and makes the voltage drop detection signal go to the “H” level. When the voltage drop detection signal of “H” level is received from the voltage drop detector  40 , the command system circuit  42  operates the semiconductor memory device  1  until the operation successfully completes. At the time point of time T 32 , an operation to be performed next is the write operation of “0”. The write operation of “0” is an operation to overwrite data of the memory cell MC and destroy data stored in the memory cell. For that reason, when the write operation of “0” is performed under the condition that the external voltage VDD*ext is not supplied to the semiconductor memory device  1  and the internal voltage VDD*int cannot be generated, there is a risk that data stored originally in the memory cell is lost. For that reason, the command system circuit  42  blocks the command from being received from the memory controller  2 . With this, the controller  16  is able to prevent breakage of data stored in the memory cell. Here, although not illustrated, for example, when the external voltage VDD*ext drops after the write operation of “0”, the command system circuit  42  controls such that a data write back operation is performed. With this, the controller  16  is able to prevent breakage of data stored in the memory cell. 
     3-3 Effect 
     According to the embodiment described above, the controller is configured to determine instantaneous stopping of the memory controller, cut the current path between the semiconductor memory device and the memory controller, and properly end the operation without using the power source voltage from the memory controller. 
     For that reason, it is possible to prevent breakage of data even in the semiconductor memory device for performing the read operation of the self-reference method. 
     4 Fourth Embodiment 
     Description will be made on a fourth embodiment. In the fourth embodiment, a write driver will be described. The basic operations of the semiconductor memory device according to the fourth embodiment are the same as those of the semiconductor memory device according to the first to third embodiments described above. Accordingly, description of the first to third embodiments that also applies to the second embodiment and matters that are capable of being easily analogized from the description of the first to third embodiments will be omitted. 
     4-1 Configuration 
     4-1-1 Sense Amplifier/Write Driver 
     The sense amplifier/write driver  20   b  of the semiconductor memory device according to the fourth embodiment will be described using  FIG. 31 . 
     As illustrated in  FIG. 31 , the sense amplifier/write driver  20   b  includes the sense circuit  200  and the write driver  230  for each group of the global bit line and the global source line. The write driver  230  is connected to the global bit line and the global source line, and two power source voltages including the same voltage as the power source voltage VDD to be supplied to the pre-amplifier  210  and the sense amplifier  220  and power source voltage VDD 2 , are supplied to the write driver  230 . 
     4-1-2 Memory Array and Write Driver 
     The memory array  20   a  described in the first embodiment will be described in more detail. 
     As illustrated in  FIG. 32 , the memory array  20   a  includes a plurality of sub-memory areas (not illustrated). The sub-memory area includes a memory cell array  20   d , a first column selection circuit  20   e , a second column selection circuit  20   f , and a read current sink  20   g . Here, for simplicity, a group of the memory cell array  20   d , the first column selection circuit  20   e , the second column selection circuit  20   f , and the read current sink  20   g  will be described. 
     The configuration of the memory cell array  20   d  is the same as the memory array  20   a  described using  FIG. 2  and thus, description thereof will be omitted. 
     The first column selection circuit  20   e  is connected to the memory cell array  20   d  through a plurality of bit lines BL_ 0  to BL_j−1. The bit line BL is selected based on first column selection signals CSL 1 _ 0  to CSL 1 _ j −1 received from the column decoder  12 . In the following description where the first column selection signals CSL 1 _ 0  to CSL 1 _ j −1 are not distinguished from one another, the first column selection signal is simply referred to as CSL 1 . 
     The first column selection circuit  20   e  includes a transistor  21  of which one end is connected to each bit line BL. The other end of the transistor  21  is connected to the global bit line GBL and each of the column selection signals CSL 1 _ 0  to CSL 1 _ j −1 is connected to a gate electrode thereof. 
     The second column selection circuit  20   f  is connected to the memory cell array  20   d  through a plurality of source line SL_ 0  to SL_j−1. The source line SL is selected based on second column selection signal CSL 2 _ 0  to CSL 2 _ j −1 received from the column decoder  12 . In the following description where the second column selection signal CSL 2 _ 0  to CSL 2 _ j −1 are not distinguished from one another, the second column selection signal is simply referred to as CSL 2 . 
     The second column selection circuit  20   f  includes a transistor  22  of which one end is connected to each source line SL. The other end of the transistor  22  is connected to the global source line GSL and each of the column selection signals CSL 2 _ 0  to CSL 2 _ j −1 is connected to a gate electrode thereof. 
     The read current sink  20   g  is connected to the second column selection circuit  20   f  through the global source line GSL. The read current sink  20   g  drives a voltage of any source line SL to VSS based on a control signal RDS received from the controller  16  and the column decoder  12 . 
     The write driver  230  is connected to the first column selection circuit  20   e  through the global bit line GBL. The write driver  230  is connected to the second column selection circuit  20   f  through the global source line GSL. The write driver  230  causes the current to flow in the memory cell MC connected to the selected word line WL based on the control signal received from the controller  16  and write data received through the IO circuit  17  and allows data to be written. 
     4-1-3 Write Driver 
     The write driver  230  of the semiconductor memory device according to the fourth embodiment will be described using  FIG. 33 . 
     As illustrated in  FIG. 33 , the write driver  230  includes NAND operation circuits  23   a ,  23   b ,  23   c ,  23   f ,  23   g , and  23   h , a NOR operation circuit  23   d , an inverter  23   e , PMOS transistors  23   j ,  23   k ,  23   m , and  23   n , NMOS transistors  23   i ,  23   l ,  23   o , and  23   p.    
     The NAND operation circuit  23   a  receives a signal WEN_ 1  (which is a write enable signal) through a first input terminal, receives a signal WDATA (which contains write data) through a second input terminal, and outputs a NAND operation result of the signal WEN_ 1  and the signal WDATA to a node N 11 . The signal WEN_ 1  is supplied from the controller  16 . The signal WDATA is supplied from the IO circuit  17 . 
     The NAND operation circuit  23   b  receives a signal WEN_ 2  (which is a write enable signal) through a first input terminal and receives the signal WDATA through a second input terminal, and outputs a NAND operation result of the signal WEN_ 2  and the signal WDATA to a node N 12 . The signal WEN_ 2  is supplied from the controller  16 . 
     The NAND operation circuit  23   c  receives an output signal of the NAND operation circuit  23   a  through a first input terminal, receives an output signal of the NAND operation circuit  23   b  through a second input terminal, and outputs a NAND operation result of the received signals to a node N 13 . 
     The NOR operation circuit  23   d  receives the signal WEN_ 1  through a first input terminal, receives the signal WEN_ 2  through a second input terminal, receives a PCHGOFF (which is a pre-charge off signal) through a third input terminal, and outputs a NOR operation result of the signal WEN_ 1 , the signal WEN_ 2 , and the signal PCHGOFF to a node N 16 . 
     The inverter  23   e  outputs a signal BWDATA obtained by inverting the signal WDATA to a node N 17 . 
     The NAND operation circuit  23   f  receives a signal WEN_ 1  through a first input terminal, receives the signal BWDATA through a second input terminal, and outputs a NAND operation result of the signal WEN_ 1  and the signal BWDATA to a node N 18 . 
     The NAND operation circuit  23   g  receives the signal WEN_ 2  through a first input terminal and receives the signal BWDATA through a second input terminal, and outputs a NAND operation result of the signal WEN_ 2  and the signal BWDATA to a node N 19 . 
     The NAND operation circuit  23   h  receives an output signal of the NAND operation circuit  23   f  through a first input terminal, receives an output signal of the NAND operation circuit  23   g  through a second input terminal, and outputs a NAND operation result of the received signals to a node N 20 . 
     The PMOS transistor  23   j  supplies a voltage Vwrt 1  to a node N 21  (which is a node of global bit line GBL) based on the output signal of the NAND operation circuit  23   a . The voltage Vwrt 1  corresponds to the voltage VDD used in the sense circuit  200  and may also be applied in the power source wiring layout described in the first embodiment or the second embodiment. The PMOS transistor  23   j  is used as a transistor for charging the global bit line GBL. 
     The PMOS transistor  23   k  supplies a voltage Vwrt 2  to the node N 21  based on the output signal of the NAND operation circuit  23   b . The voltage Vwrt 2  is, for example, a voltage dedicated to the write driver  230  and is depicted in  FIG. 31  as VDD 2 . The voltage Vwrt 2  is a voltage of which impedance from the power source pad is higher than the voltage Vwrt 1 . Here, a level of the voltage value between the voltage Vwrt 1  and the voltage Vwrt 2  is not defined. However, effect to be described later can be obtained irrespective of a magnitude relationship of a voltage value between the voltage Vwrt 1  and the voltage Vwrt 2 . 
     The NMOS transistor  23   l  discharges the node N 21  based on the output signal of the NAND operation circuit  23   h.    
     The NMOS transistor  23   o  discharges the node N 21  based on the output signal of the NOR operation circuit  23   d.    
     The PMOS transistor  23   m  supplies a voltage Vwrt 1  to a node N 22  (which is a node of global source line GSL) based on the output signal of the NAND operation circuit  23   f . The PMOS transistor  23   m  is used as a transistor for charging the global source line GSL. 
     The PMOS transistor  23   n  supplies a voltage Vwrt 2  to the node N 22  based on the output signal of the NAND operation circuit  23   g.    
     The NMOS transistor  23   i  discharges the node N 22  based on the output signal of the NAND operation circuit  23   c.    
     The NMOS transistor  23   p  discharges the node N 22  based on the output signal of the NOR operation circuit  23   d.    
     4-2 Operation 
     Next, description will be made on waveforms at the time of write operation of the semiconductor memory device according to the fourth embodiment using  FIG. 34 . Here, a write operation to be described in this section does not correspond to a write operation to be performed at the time of the read operation described above, but correspond to a general write operation. The write operation may also correspond to the write operation to be performed at the time of the read operation. Description will be made by using a case where voltages of bit lines BL and source lines SL are set as the VSS in a period during which a write operation to and a read operation with respect to a cell are not performed. 
     [time T 40 ] to [time T 41 ] 
     The row decoder  14  makes a voltage of the word line WL go to a “L” level. The column decoder  13  makes the voltages of the signals CSL 1  and CSL 2  go to the “L” level. The controller  16  makes the voltages of the signals WEN 1  and WEN 2  go to the “L” level and makes the signal PCHGOFF (not illustrated) go to the “L” level. 
     Here, operations of the write driver  230  will be described using  FIG. 33 . 
     The NAND operation circuit  23   a  supplies the signal of “H” level based on received signals. Similarly, the NAND operation circuit  23   b  supplies the signal of “H” level based on received signals. The NAND operation circuit  23   c  supplies the signal of “H” level based on received signals. The NOR operation circuit  23   d  supplies the signal of “H” level based on received signals. The NAND operation circuit  23   f  supplies the signal of “H” level based on received signals. Similarly, the NAND operation circuit  23   g  supplies the signal of “H” level based on received signals. The NAND operation circuit  23   h  supplies the signal of “L” level based on received signals. 
     With this, the PMOS transistors  23   j ,  23   k ,  23   m , and  23   n  and the NMOS transistors  23   i  and  23   l  enter the OFF state and the NMOS transistors  23   o  and  23   p  enter the ON state. As a result, the global bit line GBL and the global source line GSL are discharged. 
     [time T 41 ] to [time T 42 ] 
     The row decoder  14  makes a voltage of the selected word line WL go to a “H” level according to a row address. The column decoder  13  makes the voltages of the selected signal CSL 1  and selected signal CSL 2  go to the “H” level according to a column address. 
     [time T 42 ] to [time T 43 ] 
     The controller  16  makes a voltage of the signal WEN 1  go to the “H” level. At this time point, the signal WDATA is also input. In a case where it is intended to write data of “1” into the memory cell MC, the signal WDATA becomes “H” level. In a case where it is intended to write data of “0” into the memory cell MC, the signal WDATA becomes “L” level. 
     Here, the operation of the write driver  230  in a case where the signal WDATA is the “H” level (a case of WDATA=1) will be described. 
     As illustrated in  FIG. 33 , the NAND operation circuit  23   a  supplies the signal of “L” level based on received signals. The NAND operation circuit  23   b  supplies the signal of “H” level based on received signals. The NAND operation circuit  23   c  supplies the signal of “H” level based on received signals. The NOR operation circuit  23   d  supplies the signal of “L” level based on received signals. The NAND operation circuit  23   f  supplies the signal of “H” level based on received signals. Similarly, the NAND operation circuit  23   g  supplies the signal of “H” level based on received signals. The NAND operation circuit  23   h  supplies the signal of “L” level based on received signals. 
     With this, the PMOS transistor  23   j  and the NMOS transistor  23   i  enter the ON state. As a result, the voltage Vwrt 1  is applied to the global bit line GBL and the global source line GSL is discharged. 
     With this, as illustrated in  FIG. 34 , the selected bit line BL is charged to the “H” level and the source line SL becomes the “L” level. 
     The voltage Vwrt 1  is a voltage of which impedance from the power source pad is lower than that of the voltage Vwrt 2  and thus, the selected bit line BL is charged at a high speed. 
     The operation of the write driver  230  in a case where the signal WDATA is the “L” level (a case of WDATA=0) will be described. 
     As illustrated in  FIG. 33 , the NAND operation circuit  23   a  supplies the signal of “H” level based on received signals. The NAND operation circuit  23   b  supplies the signal of “H” level based on received signals. The NAND operation circuit  23   c  supplies the signal of “L” level based on received signals. The NOR operation circuit  23   d  supplies the signal of “L” level based on received signals. The NAND operation circuit  23   f  supplies the signal of “L” level based on received signals. The NAND operation circuit  23   g  supplies the signal of “H” level based on received signals. The NAND operation circuit  23   h  supplies the signal of “H” level based on received signals. 
     With this, the PMOS transistor  23   m  and the NMOS transistor  23   l  enter the ON state. As a result, the voltage Vwrt 1  is applied to the global source line GSL and the global bit line GBL is discharged. 
     With this, as illustrated in  FIG. 34 , the selected source line SL is charged to the “H” level and the bit line BL becomes the “L” level. 
     The voltage Vwrt 1  is a voltage of which impedance from the power source pad is lower than that of the voltage Vwrt 2  and thus, the selected source line SL is charged at a high speed. 
     [time T 43 ] to [time T 44 ] 
     The controller  16  makes the voltage of the signal WEN 1  go to the “L” level and makes the voltage of the signal WEN 2  go to the “H” level. 
     Here, the operation of the write driver  230  in the case where the signal WDATA is the “H” level (a case of WDATA=1) will be described. 
     As illustrated in  FIG. 33 , the NAND operation circuit  23   a  supplies the signal of “H” level based on received signals. The NAND operation circuit  23   b  supplies the signal of “L” level based on received signals. The NAND operation circuit  23   c  supplies the signal of “H” level based on received signals. The NOR operation circuit  23   d  supplies the signal of “L” level based on received signals. The NAND operation circuit  23   f  supplies the signal of “H” level based on received signals. Similarly, the NAND operation circuit  23   g  supplies the signal of “H” level based on received signals. The NAND operation circuit  23   h  supplies the signal of “L” level based on received signals. 
     With this, the PMOS transistor  23   k  and the NMOS transistor  23   i  enter the ON state. As a result, the voltage Vwrt 2  is applied to the global bit line GBL and the global source line GSL is discharged. 
     With this, as illustrated in  FIG. 34 , the selected bit line BL maintains the “H” level and the source line SL becomes the “L” level. 
     The voltage Vwrt 2  is a voltage of which impedance from the power source pad is higher than the voltage Vwrt 1  but the selected bit line BL is already charged at time T 42  to time T 43 . For that reason, even when it is switched to a voltage of which impedance from the power source pad is high at time T 43  to time T 44 , the voltage drop accompanying charging of the global source line GSL and source line SL does not occur. Accordingly, the write operation to the memory cell is not influenced. 
     The operation of the write driver  230  in the case where (the case of WDATA=0) the signal WDATA is the “L” level will be described. 
     As illustrated in  FIG. 33 , the NAND operation circuit  23   a  supplies the signal of “H” level based on received signals. The NAND operation circuit  23   b  supplies the signal of “H” level based on received signals. The NAND operation circuit  23   c  supplies the signal of “L” level based on received signals. The NOR operation circuit  23   d  supplies the signal of “L” level based on received signals. The NAND operation circuit  23   f  supplies the signal of “H” level based on received signals. The NAND operation circuit  23   g  supplies the signal of “L” level based on received signals. The NAND operation circuit  23   h  supplies the signal of “H” level based on received signals. 
     With this, the PMOS transistor  23   n  and the NMOS transistor  23   l  enter the ON state. As a result, the voltage Vwrt 2  is applied to the global source line GSL and the global bit line GBL is discharged. 
     With this, as illustrated in  FIG. 34 , the selected bit source line SL maintains the “H” level and the bit line BL becomes the “L” level. 
     The voltage Vwrt 2  is the voltage of which impedance from the power source pad is higher than the voltage Vwrt 1  but the selected source line SL already charged during time T 42  to time T 43 . For that reason, even when it is switched to a voltage of which impedance from the power source pad is high during time T 43  to time  144 , the voltage drop accompanying charging of the global source line GSL and the source line SL does not occur. Accordingly, the write operation to the memory cell is not influenced. 
     [time T 44 ] to [time T 45 ] 
     The controller  16  makes the voltage of the signal WEN 2  go to the “L” level to end the write operation. The NOR operation circuit  23   d  supplies the signal of “L” level based on the received signals. With this, the NMOS transistors  23   o  and  23   p  enter the ON state. As a result, the global bit line GBL and the global source line GSL are discharged. 
     4-3 Effect 
     4-3-1 Outline 
     According to embodiment described above, the global bit line GBL or the global source line GSL is charged by a first power source of which impedance from the first power source pad is relatively low in a first period during which the global bit line GBL or the global source line GSL is charged. After the global bit line GBL or the global source line GSL is charged and in the write operation period, the voltage of the global bit line GBL or the global source line GSL is maintained at a second power source of which impedance from the first power source pad is higher than the first power source. With this, it is possible to properly perform the write operation. 
     4-3-2 Comparative Example 
     Here, a comparative example will be described in order to make it easy to understand effect of the embodiment described above. 
     4-3-2-1 Write Driver 
     The write driver  230  of a semiconductor memory device according to a comparative example of the fourth embodiment will be described using  FIG. 35 . 
     As illustrated in  FIG. 35 , the write driver  230  includes NAND operation circuits  24   a  and  24   f , a NOR operation circuit  24   d , inverters  24   c ,  24   e , and  24   h , PMOS transistors  24   b  and  24   g , and NMOS transistors  24   i ,  24   j ,  24   k , and  24   l.    
     The NAND operation circuit  24   a  receives a signal WEN (which is a write enable signal) through a first input terminal, receives a signal WDATA through a second input terminal, and outputs a NAND operation result of the signal WEN and the signal WDATA to a node N 32 . 
     The inverter  24   c  outputs a signal obtained by inverting the output signal of the NAND operation circuit  24   a.    
     The NOR operation circuit  24   d  receives the signal WEN through a first input terminal, receives a PCHGOFF through a second input terminal, and outputs a NOR operation result of the signal WEN and the signal PCHGOFF a node N 33 . 
     The inverter  24   e  outputs a signal BWDATA obtained by inverting the signal WDATA. 
     The NAND operation circuit  24   f  receives the signal WEN through a first input terminal, receives the signal BWDATA through a second input terminal, and outputs a NAND operation result of the signal WEN and the signal BWDATA to a node N 34 . 
     The inverter  24   h  outputs a signal obtained by inverting the output signal of the NAND operation circuit  24   f.    
     The PMOS transistor  24   b  supplies a voltage Vwrt to a node N 35  (which is a node of global bit line GBL) based on the output signal of the NAND operation circuit  24   a . The voltage Vwrt corresponds to the voltage Vwrt 2  of the embodiment described above. 
     The NMOS transistor  24   i  discharges the node N 35  based on the output signal of the inverter  24   h.    
     The NMOS transistor  24   k  discharges the node N 35  based on the output signal of the NOR operation circuit  24   d.    
     The PMOS transistor  24   g  supplies the voltage Vwrt to a node N 36  (which is a node of global source line GSL) based on the output signal of the NAND operation circuit  24   f.    
     The NMOS transistor  24   j  discharges the node N 36  based on the output signal of the inverter  24   c.    
     The NMOS transistor  24   l  discharges the node N 36  based on the output signal of the NOR operation circuit  24   d.    
     4-3-2-2 Operation 
     Here, description will be made on waveforms in (=at the time of) a write operation of the semiconductor memory device according to the fourth embodiment using  FIG. 36 . Description will be made by using a case where voltages of bit lines BL and source lines SL are set as the VSS in a period during which a write operation with respect to a cell and a read operation are not performed. 
     [time T 50 ] to [time T 51 ] 
     The row decoder  14  makes a voltage of the word line WL go to a “L” level. The column decoder  13  makes the voltages of the signals CSL 1  and CSL 2  go to the “L” level. The controller  16  makes the voltage of the signals WEN go to the “L” level and makes the signal PCHGOFF (not illustrated) go to the “L” level. 
     Here, operations of the write driver  230  will be described using  FIG. 35 . 
     The NAND operation circuit  24   a  supplies the signal of “H” level based on the received signals. The NOR operation circuit  24   d  supplies the signal of “H” level based on the received signals. The NAND operation circuit  24   f  supplies the signal of “H” level based on the received signals. 
     With this, the NMOS transistors  24   i  and  24   j  enter the OFF state and the NMOS transistors  24   k  and  24   l  enter the ON state. As a result, the global bit line GBL and the global source line GSL are discharged. 
     [time T 51 ] to [time T 52 ] 
     The row decoder  14  makes a voltage of the selected word line WL go to a “H” level according to a row address. The column decoder  13  makes the voltages of the selected signal CSL 1  and selected signal CSL 2  go to the “H” level according to a column address. 
     [time T 52 ] to [time T 53 ] 
     The controller  16  makes a voltage of the signal WEN go to the “H” level. At this time point, the signal WDATA is also input. 
     Here, the operation of the write driver  230  in a case where the signal WDATA is the “H” level (a case of WDATA=1) will be described. 
     As illustrated in  FIG. 35 , the NAND operation circuit  24   a  supplies the signal of “L” level based on the received signals. The NOR operation circuit  24   d  supplies the signal of “L” level based on the received signals. The NAND operation circuit  24   f  supplies the signal of “H” level based on the received signals. 
     With this, the PMOS transistor  24   b  and the NMOS transistor  24   j  enter the ON state. As a result, the voltage Vwrt is applied to the global bit line GBL and the global source line GSL is discharged. 
     A wiring length of the global bit line GBL is long and the capacitance thereof is large. For that reason, in a case where the global bit line GBL is charged with the voltage Vwrt having the same impedance from the power source pad as that of the voltage Vwrt 2  described above, there is a possibility of a voltage drop of the voltage Vwrt due to the current peak. As a result, as illustrated in  FIG. 36 , there is a possibility that a charging time of the global bit line GBL becomes long. In this case, there is a possibility that an effective writing time to the memory cell MC is reduced and defective writing is caused. 
     The operation of the write driver  230  in a case where the signal WDATA is the “L” level (a case of WDATA=0) will be described. 
     As illustrated in  FIG. 35 , the NAND operation circuit  24   a  supplies the signal of “H” level based on the received signals. The NOR operation circuit  24   d  supplies the signal of “L” level based on the received signals. The NAND operation circuit  24   f  supplies the signal of “L” level based on the received signals. 
     With this, the PMOS transistor  24   g  and the NMOS transistor  24   i  enter the ON state. As a result, the voltage Vwrt is applied to the global source line GSL and the global bit line GBL is discharged. 
     Also, in a case where the signal WDATA is the “L” level, the same problem as that described above is likely to occur. 
     4-3-3 Summary 
     According to the embodiment described above, the global bit line GBL or the global source line GSL is charged using the voltage of which impedance from the power source pad is low in the first period during which the global bit line GBL or the global source line GSL is charged. The power source of which impedance from the power source pad is low is not influenced by the voltage drop due to the peak of a charging current described above, in the first period. For that reason, it is possible to charge the global bit line GBL or the global source line GSL at a high speed. With this, it is possible to suppress the increase of the ratio of defective writing caused by the voltage drop. Furthermore, as described in the first to third embodiments, the power source noise is minimally propagated between different banks. For that reason, it is possible to suppress operational malfunction due to the power source noise of another bank. 
     4-4 Modification Example 
     4-4-1 Write Driver 
     The write driver  230  of the semiconductor memory device according to the modification example of the fourth embodiment will be described using  FIG. 37 . 
     As illustrated in  FIG. 37 , the write driver  230  includes NAND operation circuits  25   a , and  25   f , a NOR operation circuit  25   d , inverters  25   c ,  25   e , and  25   h , PMOS transistors  25   b ,  25   g ,  25   m , and  25   n , and NMOS transistors  25   i ,  25   j ,  25   k , and  25   l.    
     The NAND operation circuit  25   a  receives a signal WEN through a first input terminal, receives a signal WDATA through a second input terminal, and outputs a NAND operation result of the signal WEN and the signal WDATA to a node N 42 . The signal WEN is supplied from the controller  16 . 
     The inverter  25   c  outputs a signal obtained by inverting the output signal of the NAND operation circuit  25   a.    
     The NOR operation circuit  25   d  receives the signal WEN through a first input terminal, receives a PCHGOFF through a second input terminal, and outputs a NOR operation result of the signal WEN and the signal PCHGOFF to a node N 43 . 
     The inverter  25   e  outputs a signal BWDATA obtained by inverting the signal WDATA. 
     The NAND operation circuit  25   f  receives the signal WEN through a first input terminal, receives the signal BWDATA through a second input terminal, and outputs a NAND operation result of the signal WEN and the signal BWDATA to a node N 44 . 
     The inverter  25   h  outputs a signal obtained by inverting the output signal of the NAND operation circuit  25   f.    
     The PMOS transistor  25   m  supplies a voltage Vwrt 1  to a node N 47  based on a signal EN_ 1 . 
     The PMOS transistor  25   n  supplies a voltage Vwrt 2  to a node N 47  based on a signal EN_ 2 . 
     The PMOS transistor  25   b  supplies the voltage Vwrt 1  or Vwrt 2  to a node N 45  (which is a node of global bit line GBL) based on the output signal of the NAND operation circuit  25   a.    
     The NMOS transistor  25   i  discharges the node N 45  based on the output signal of the inverter  25   h.    
     The NMOS transistor  25   k  discharges the node N 45  based on the output signal of the NOR operation circuit  25   d.    
     The PMOS transistor  25   g  supplies the voltage Vwrt 1  or Vwrt 2  to a node N 46  (which is a node of global source line GSL) based on the output signal of the NAND operation circuit  25   f.    
     The NMOS transistor  25   j  discharges the node N 46  based on the output signal of the inverter  25   c.    
     The NMOS transistor  25   l  discharges the node N 46  based on the output signal of the NOR operation circuit  25   d.    
     4-4-2 Operation 
     Here, description will be made on waveforms in at the time of a write operation of the semiconductor memory device according to the modification example of the fourth embodiment using  FIG. 38 . 
     [time T 60 ] to [time T 61 ] 
     The row decoder  14  makes a voltage of the word line WL go to a “L” level. The column decoder  13  makes the voltages of the signals CSL 1  and CSL 2  go to the “L” level. The controller  16  makes the voltage of the signals WEN and the PCHGOFF (not illustrated) go to the “L” level and makes the signals EN_ 1  and EN_ 2  go to the “H” level. 
     Here, the operation of the write driver  230  will be described using  FIG. 37 . Description will be made by using a case where voltages of bit lines BL and source lines SL are set as the VSS in a period during which a write operation to a cell and a read operation are not performed. 
     The NAND operation circuit  25   a  supplies the signal of “H” level based on the received signals. The NOR operation circuit  25   d  supplies the signal of “H” level based on the received signals. The NAND operation circuit  25   f  supplies the signal of “H” level based on the received signals. 
     With this, the PMOS transistors  25   b ,  25   g ,  25   m , and  25   n  and the NMOS transistors  25   i  and  25   j  enter the OFF state and the NMOS transistors  25   k  and  25   l  enter the ON state. As a result, the global bit line GBL and the global source line GSL are discharged. 
     [time T 61 ] to [time T 62 ] 
     The row decoder  14  makes a voltage of the selected word line WL go to a “H” level according to a row address. The column decoder  13  makes the voltages of the selected signal CSL 1  and selected signal CSL 2  go to the “H” level according to a column address. 
     [time T 62 ] to [time T 63 ] 
     The controller  16  makes the voltage of the signal WEN 1  go to the “H” level, and makes the signal EN_ 1  go to the “L” level. At this time point, the signal WDATA is also input. 
     Here, the operation of the write driver  230  in a case where the signal WDATA is the “H” level (a case of WDATA=1) will be described. 
     As illustrated in  FIG. 37 , the NAND operation circuit  25   a  supplies the signal of “L” level based on the received signals. The NOR operation circuit  25   d  supplies the signal of “L” level based on the received signals. The NAND operation circuit  25   f  supplies the signal of “H” level based on the received signals. 
     With this, the PMOS transistors  25   b  and  25   m  and the NMOS transistor  25   j  enter the ON state. As a result, the voltage Vwrt 1  is applied to the global bit line GBL and the global source line GSL is discharged. 
     With this, the global bit line GBL is charged at a high speed, similarly as in the first embodiment. 
     Furthermore, the operation of the write driver  230  in a case where the signal WDATA is the “L” level (a case of WDATA=0) will be described. 
     As illustrated in  FIG. 37 , the NAND operation circuit  25   a  supplies the signal of “H” level based on the received signals. The NOR operation circuit  25   d  supplies the signal of “L” level based on the received signals. The NAND operation circuit  25   f  supplies the signal of “L” level based on the received signals. 
     With this, the PMOS transistors  25   g  and  25   m  and the NMOS transistor  25   i  enter the ON state. As a result, the voltage Vwrt 1  is applied to the global source line GSL and the global bit line GBL is discharged. 
     With this, the global source line GSL is charged at a high speed, similarly as in the first embodiment. 
     [time T 62 ] to [time T 63 ] 
     The controller  16  makes the signal EN_ 1  go to the “H” level and makes the signal EN_ 2  go to the “L” level. 
     Here, the operation of the write driver  230  in a case where the signal WDATA is the “H” level (a case of WDATA=1) will be described. 
     As illustrated in  FIG. 37 , the NAND operation circuit  25   a  supplies the signal of “L” level based on the received signals. The NOR operation circuit  25   d  supplies the signal of “L” level based on the received signals. The NAND operation circuit  25   f  supplies the signal of “H” level based on the received signals. 
     With this, the PMOS transistors  25   b  and  25   n  and the NMOS transistor  25   j  enter the ON state. As a result, the voltage Vwrt 2  is applied to the global bit line GBL and the global source line GSL is discharged. 
     With this, the voltage of the global bit line GBL is maintained, similarly as in the first embodiment. 
     Furthermore, the operation of the write driver  230  in a case where the signal WDATA is the “L” level (a case of WDATA=0) will be described. 
     As illustrated in  FIG. 37 , the NAND operation circuit  25   a  supplies the signal of “H” level based on the received signals. The NOR operation circuit  25   d  supplies the signal of “L” level based on the received signals. The NAND operation circuit  25   f  supplies the signal of “L” level based on the received signals. 
     With this, the PMOS transistors  25   g  and  25   n  and the NMOS transistor  25   i  enter the ON state. As a result, the voltage Vwrt 2  is applied to the global source line GSL and the global bit line GBL is discharged. 
     With this, the voltage of the global source line GSL is maintained, similarly as in the first embodiment. 
     4-4-3 Effect 
     As described above, in the write driver illustrated in  FIG. 37 , the same effect as that of the fourth embodiment can also be obtained. In the embodiment described above, although description is made by using a case where voltages of bit lines BL and source lines SL are set as the VSS in a period during which the write operation and the read operation with respect to the cell are not performed, the same effect can also be obtained in a case where the voltages of bit lines BL and source lines SL are in a floating state. In a case where the voltages of bit lines BL and source lines SL are caused to be in a floating state, for example, the waveform diagrams corresponding to  FIG. 34  of the fourth embodiment are represented by  FIG. 39 . That is, as illustrated in  FIG. 39 , after time T 44 , the voltages of the bit line BL and the source line SL of WDATA=“1” approach each other and maintain a value of a voltage level, which is between the voltage levels of the bit line BL and the source line SL, between time T 43  and time T 44 . Also, after time T 44 , the voltages of the bit line BL and the source line SL of WDATA=“0” approach each other and maintain a value of a voltage level, which is between the voltage levels of the bit line BL and the source line SL, between time T 43  and time T 44 . Similarly, also in  FIG. 36  of the comparative example of the fourth embodiment, in a case where the voltages of bit lines BL and source lines SL are caused to be in a floating state, as illustrated in  FIG. 40 , after time T 54 , the voltages of the bit line BL and the source line SL of WDATA=“1” approach each other and maintain a value of a voltage level, which is between the voltage levels of the bit line BL and the source line SL, between time T 53  and time T 54 . Also, after time T 54 , the voltages of the bit line BL and the source line SL of WDATA=“0” approach each other and maintain a value of a voltage level, which is between the voltage levels of the bit line BL and the source line SL. Similarly, also in  FIG. 38  of the comparative example of the fourth embodiment, in a case where the voltages of bit lines BL and source lines SL are caused to float, as illustrated in  FIG. 41 , after time T 64 , the voltages of the bit line BL and the source line SL of WDATA=“1” approach each other and maintain a value of a voltage level, which is between the voltage levels of the bit line BL and the source line SL, between time T 63  and time  164 . Also, after time T 64 , the voltages of the bit line BL and the source line SL of WDATA=“0” approach each other and maintain a value of a voltage level, which is between the voltage levels of the bit line BL and the source line SL, between time T 63  and time  164 . 
     5 Others 
     A term during which connection is made in respective embodiments described above includes a state in which connected elements are indirectly connected by interposing any other element therebetween, for example, a transistor or a resistor. 
     Here, although the MRAM that stores data using the magnetoresistive effect element (magnetic tunnel junction (MTJ) element) as a resistance change element is described by way of an example, but the exemplary embodiment is not limited thereto. 
     For example, the exemplary embodiment can be applied to the semiconductor memory device having an element which stores data using resistance change, like a resistance change type memory, for example, ReRAM or PCRAM, which is similar to the MRAM. 
     The exemplary embodiment can be applied to the semiconductor memory device having an element which stores data by resistance change according to application of a current or a voltage or reading stored data by converting a resistance difference according to resistance change into a current difference or a voltage difference, irrespective of a volatile memory or a non-volatile memory. 
     In the respective embodiments described above, for convenience, a bit line pair is referred to as the bit line BL and source line SL, but is not limited thereto, and may also be referred to as, for example, the first bit line and second bit line. 
     While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.