Patent Publication Number: US-2022231597-A1

Title: Control circuit and method for bus voltage variation in power converters

Description:
CROSS REFERENCE TO RELATED APPLICATION 
     This application claims priority to U.S. Provisional Patent Application No. 62/865,776 filed on Jun. 24, 2019, naming Zheyu Zhang et al. as inventors, and titled “Control Circuit and Method for Bus Voltage Variation in Power Converters,” the entire contents of which are hereby incorporated by reference herein. 
    
    
     BACKGROUND 
     The field of the disclosure relates generally to power converters and, more particularly, to a control circuit and method under bus voltage variation events in power converters. 
     Many known converter circuits, such as those in DC-DC converters, include multiple DC-DC converters coupled in parallel between a first bus and a second bus, or between an input bus and an output bus. The DC-DC converters generally include various switches, or switching circuits, controlled in a manner to produce a conversion from one DC level to another DC level, e.g., a buck-boost converter. In the alternative, at least some other converter circuits may similarly control switching to produce an AC to DC or a DC to AC conversion. 
     When an electrical event occurs on the input bus of a power converter, such as a transient voltage rise or other high dV/dt event, the converter may not detect the event quickly enough to moderate its control, e.g., feedback control or feedforward compensation, and, consequently, over-current protection may engage and disable the power converter. It would be desirable to improve high dV/dt event detection and response in power converters. 
     BRIEF DESCRIPTION 
     In one aspect, a control circuit for a power converter is provided. The control circuit includes a pulse width modulator, a current feedback loop, a bus voltage feedforward path, and a logic circuit. The pulse width modulator is configured to generate a control signal for the power converter to regulate a load current through the power converter. The current feedback loop is configured to control the pulse width modulator to converge the load current through the power converter to a demanded current. The bus voltage feedforward path is configured to measure a bus voltage supplied to the power converter at an input bus and, in combination with the current feedback loop, control the pulse width modulator to regulate the load current based on the bus voltage. The logic circuit is configured to collect load current measurements and determine, based at least partially thereon, a voltage variation event has occurred on the input bus. The logic circuit is configured to disable the control signal for the power converter in response to determining the voltage variation event has occurred. 
     In another aspect, a power converter is provided. The power converter includes an input bus, an output bus, a plurality of semiconductor switches, and a control circuit. The plurality of semiconductor switches is coupled between the input bus and the output bus. The plurality of semiconductor switches is configured to commutate at a switching frequency to regulate a load current from the input bus to the output bus. The control circuit is configured to control commutation of the plurality of semiconductor switches to converge the load current to a demanded current and regulate the load current based on a measured bus voltage at the input bus. The control circuit includes a logic circuit configured to collect load current measurements and determine, based at least partially thereon, a voltage variation event has occurred on the input bus, and disable a control signal for operating the plurality of semiconductor switches in response to determining the voltage variation event has occurred. 
     In yet another aspect a method of controlling a power converter during a bus voltage variation event is provided. The method includes generating a pulse width modulated (PWM) control signal for commutating a plurality of semiconductor switches of the power converter to converge a load current provided through the power converter to a demanded current. The method includes sampling a bus voltage supplied to the power converter at an input bus at a frequency of at least twice a switching frequency at which the plurality of semiconductor switches is commutated. The method includes modifying the PWM control signal based on the bus voltage to regulate the load current. The method includes collecting load current measurements and determining, based at least partially on the load current measurements, a voltage variation event has occurred on the input bus. The method includes disabling the PWM control signal for the power converter in response to determining the voltage variation event has occurred. 
     In at least some embodiments, the method further includes comparing the bus voltage to a subsequent bus voltage to determine a change in bus voltage over time, and re-enabling the PWM control signal for the power converter when the change in bus voltage over time falls below a voltage change threshold. 
    
    
     
       DRAWINGS 
       These and other features, aspects, and advantages of the present disclosure will become better understood when the following detailed description is read with reference to the accompanying drawings in which like characters represent like parts throughout the drawings, wherein: 
         FIG. 1  is a schematic block diagram of an exemplary power system; 
         FIG. 2  is a schematic diagram an exemplary power converter for use in the power system shown in  FIG. 1 ; 
         FIG. 3  is a schematic diagram of a known control circuit for a power converter; 
         FIG. 4  is a schematic diagram of a control circuit for the power converter shown in  FIG. 2 ; 
         FIG. 5  is a plot of voltage and current in a power converter from a simulation illustrating a method of using the control circuit shown in  FIG. 4  during a voltage variation event; and 
         FIG. 6  is a flow diagram of an example method of controlling a power converter. 
     
    
    
     Unless otherwise indicated, the drawings provided herein are meant to illustrate features of embodiments of this disclosure. These features are believed to be applicable in a wide variety of systems comprising one or more embodiments of this disclosure. As such, the drawings are not meant to include all conventional features known by those of ordinary skill in the art to be required for the practice of the embodiments disclosed herein. 
     DETAILED DESCRIPTION 
     In the following specification and the claims, a number of terms are referenced that have the following meanings. 
     The singular forms “a,” “an,” and “the” include plural references unless the context clearly dictates otherwise. 
     “Optional” or “optionally” means that the subsequently described event or circumstance may or may not occur, and that the description includes instances where the event occurs and instances where it does not. 
     Approximating language, as used herein throughout the specification and claims, may be applied to modify any quantitative representation that could permissibly vary without resulting in a change in the basic function to which it relates. Accordingly, a value modified by a term or terms, such as “about,” “approximately,” and “substantially,” are not to be limited to the precise value specified. In at least some instances, the approximating language may correspond to the precision of an instrument for measuring the value. Here and throughout the specification and claims, range limitations may be combined and/or interchanged; such ranges are identified and include all the sub-ranges contained therein unless context or language indicates otherwise. 
     Some embodiments involve the use of one or more electronic processing or computing devices. As used herein, the terms “processor” and “computer” and related terms, e.g., “processing device,” “computing device,” and “controller” are not limited to just those integrated circuits referred to in the art as a computer, but broadly refers to a processor, a processing device, a controller, a general purpose central processing unit (CPU), a graphics processing unit (GPU), a microcontroller, a microcomputer, a programmable logic controller (PLC), a reduced instruction set computer (RISC) processor, a field programmable gate array (FPGA), a digital signal processing (DSP) device, an application specific integrated circuit (ASIC), and other programmable circuits or processing devices capable of executing the functions described herein, and these terms are used interchangeably herein. The above embodiments are examples only, and thus are not intended to limit in any way the definition or meaning of the terms processor, processing device, and related terms. 
     In the embodiments described herein, memory may include, but is not limited to, a non-transitory computer-readable medium, such as flash memory, a random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), and non-volatile RAM (NVRAM). As used herein, the term “non-transitory computer-readable media” is intended to be representative of any tangible, computer-readable media, including, without limitation, non-transitory computer storage devices, including, without limitation, volatile and non-volatile media, and removable and non-removable media such as a firmware, physical and virtual storage, CD-ROMs, DVDs, and any other digital source such as a network or the Internet, as well as yet to be developed digital means, with the sole exception being a transitory, propagating signal. Alternatively, a floppy disk, a compact disc-read only memory (CD-ROM), a magneto-optical disk (MOD), a digital versatile disc (DVD), or any other computer-based device implemented in any method or technology for short-term and long-term storage of information, such as, computer-readable instructions, data structures, program modules and sub-modules, or other data may also be used. Therefore, the methods described herein may be encoded as executable instructions, e.g., “software” and “firmware,” embodied in a non-transitory computer-readable medium. Further, as used herein, the terms “software” and “firmware” are interchangeable, and include any computer program stored in memory for execution by personal computers, workstations, clients and servers. Such instructions, when executed by a processor, cause the processor to perform at least a portion of the methods described herein. Furthermore, as used herein, the term “real-time” refers to at least one of the time of occurrence of the associated events, the time of measurement and collection of predetermined data, the time to process the data, and the time of a system response to the events and the environment. In the embodiments described herein, these activities and events occur substantially instantaneously. 
     Embodiments of the present disclosure relate to a control circuit and method for a bus voltage variation event in a power converter. The control circuits and methods described herein improve the speed of detection of high dV/dt events by enabling high dl/dt detection as a leading indicator of the high dV/dt event, and by increasing the sensing frequency of bus voltage supplied to the power converter to enhance feedforward compensation and improve disturbance rejection capability of current control. Generally, current sensing, or detection, may be carried out at a significantly higher bandwidth than voltage sensing. For example, current sensing may be carried out at a frequency above a switching frequency for the semiconductor switches of the power converter. More specifically, in certain embodiments, current sensing may be carried out at a bandwidth of ten-times the switching frequency. 
       FIG. 1  is a schematic block diagram of an exemplary power system  100 . Power system  100  includes an electric grid  102  that can be supplied power from, for example, a photovoltaic (PV) string  104  or a battery  106 , or any other suitable renewable or non-renewable energy source. Generally, electric grid  102  is an alternating current (AC) grid operating at various voltage levels for the purpose of power transmission. Accordingly, power supplied, for example, by PV string  104  or battery  106  is converted to line-frequency power by an inverter  108  and, typically, stepped up by a transformer  110 . In alternative embodiments, transformer  110  may step down the AC voltage to suit a given distribution line within electric grid  102 . 
     PV string  104  produces DC power at a nominal direct current (DC) voltage for a DC bus  112  that connects PV string  104  to inverter  108 . This nominal DC voltage at which DC bus  112  operates is referred to as the bus voltage. Likewise, battery  106 , or any other energy storage device, produces DC power at an operating voltage for battery  106 , which is then converted to the bus voltage by a power converter  200 , such as a buck-boost converter. Power converter  200  converts DC power sourced by battery  106  from the operating voltage to the bus voltage on DC bus  112  when supplying power to inverter  108  and electric grid  102 , or any other electrical load. Conversely, when battery  106  is not supplying power to inverter  108  and electric grid  102 , battery  106  may be charged from DC bus  112 . In such a scenario, power converter  200  converts DC power from the bus voltage on DC bus  112  to the operating voltage for battery  106  to charge battery  106 . 
     Power system  100  may occasionally experience a voltage variation event, such as a grid fault. When this occurs, inverter  108  no longer delivers active power, resulting in a power imbalance on DC bus  112 , because PV string  104  continues supplying power based on the current bus voltage on DC bus  112 . Accordingly, the bus voltage on DC bus  112  increases rapidly until it approaches an open circuit voltage of PV string  104 , and may lead to a transient high dV/dt event, e.g., a voltage increase of up to 200 Volts per millisecond (V/ms). Under certain circumstances, where the additional power is not supplied through inverter  108  to electric grid  102 , the increase in bus voltage presents to power converter  200  and, potentially, battery  106  as a bus voltage variation event. 
       FIG. 2  is a schematic diagram of an exemplary power converter  200  for use in power system  100  shown in  FIG. 1 . Power converter  200  is one example of power converter architecture and, more specifically, is illustrated as a flying capacitor power converter. Power converter  200  includes an input bus, or bus side  202 , and an output bus, or battery side  204 . Bus side  202  is configured to be coupled to DC bus  112  (shown in  FIG. 1 ) and is, accordingly, supplied the bus voltage, which is applied across a bus capacitor  206  and a switching circuit  208 , including a plurality of semiconductor switches  210  and a flying capacitor  212 . Battery side  204  is coupled to battery  106  and provides a battery voltage across an output capacitor  214 . Battery side  204  includes a switching circuit  216 , including a plurality of semiconductor switches  218  and a flying capacitor  220 . Generally, semiconductor switches  210  and  218  are controlled by a processor (not shown) according to one or more pulse width modulated (PWM) control signals to affect the conversion from the bus voltage to the battery voltage, or from the battery voltage to the bus voltage. Power converter  200  includes an inductor  222  spanning between bus side  202  and battery side  204 , and functions to stabilize current (I L ) through power converter  200 , i.e., provides a desired substantially constant current. 
     When power system  100 , for example, experiences a voltage variation event, control of semiconductor switches  210  and  218  is modified to control the current (I L ) through power converter  200 . If current (I L ) is not moderated properly, an over-current protection may engage and disable power converter  200 . Such moderating is traditionally achieved by monitoring the bus voltage on DC bus  112  and using a feedforward control loop together with a current feedback control loop, implemented in a processor, for example, to moderate current (I L ) through power converter  200  by adjusting the PWM control signals that control semiconductor switches  210  and  218 . However, such traditional protection generally is delayed and may result in engaging the over-current protection for power converter  200 . 
       FIG. 3  is a schematic diagram of a known control circuit  300  for a power converter, such as power converter  200  (shown in  FIG. 2 ). Generally, control circuit  300  produces a PWM control signal  302  for controlling the various semiconductor switches in the power converter. Control circuit  300  uses measured current (I L ) and measured bus voltage (F bus ) to make adjustments to the PWM control signal  302  over time, which will eventually converge on, for example, a demanded current (I L  *). Control circuit  300  responds to changes in demanded current (I L  *) and small variations in bus voltage (V bus ) over a given period of time by further adjusting the PWM control signal  302  and converging on a new level of output, or current (I L ). However, when, for example, the bus voltage (V bus ) increases rapidly, e.g., 200 V/ms, control circuit  300  typically does not detect and respond (e.g., reduce current throughput) quickly enough to avoid engaging over-current control and disabling the power converter. 
     Control circuit  300  embodies the control functionality in a current feedback loop  304  and a bus voltage feedforward path  306 . Current feedback loop  304  computes a current error  308  that is a difference between demanded current (I L  *) and actual, or measured, current (I L ). Current feedback loop  304  also includes a proportional-integral (PI) controller  310  that aims to minimize the current error  308  and produces an output signal that is modulated by a PWM modulator  312  to produce the PWM control signal  302 . Bus voltage feedforward path  306  utilizes a measured bus voltage (V bus ) on, for example, DC bus  112 , to adjust a duty cycle signal  314  representing a duty cycle at which PWM modulator  312  is to generate PWM control signal  302 . The measured bus voltage (V bus ) is generally gained  316  before being combined with the output signal of PI controller  310  to produce the duty cycle signal  314 . Generally, the detection of a high dV/dt event by bus voltage feedforward path  306  is too delayed to properly moderate duty cycle signal  314  and, therefore, PWM control signal  302 , resulting in a potential over-current in the power converter as a result of the high dV/dt event. 
       FIG. 4  is a schematic diagram of an exemplary control circuit  400  disclosed herein for power converter  200  shown in  FIG. 2 . Control circuit  400  may be embodied in one or more processors or other suitable processing device. Generally, control circuit  400  produces a PWM control signal  402  for controlling the various semiconductor switches in power converter  200 . Control circuit  400 , like control circuit  300  (shown in  FIG. 3 ) uses measured current (I L ) and measured bus voltage (V bus ) to make adjustments to the PWM control signal  402  over time, which will eventually converge on, for example, a demanded current (I L  *). In contrast to control circuit  300  of  FIG. 3 , control circuit  400  utilizes both bus voltage feedforward control and current monitoring to provide fast-response protection in control circuit  400  in the event of a high dV/dt event in power converter  200 , and, in certain embodiments, enables restart of power converter  200  when the voltage variation subsides. Current monitoring, or current sensing, enables fast-response protection by carrying out current measurements at a frequency of at least the switching frequency and, in certain embodiments, for example, at a frequency of ten-times the switching frequency of the semiconductor switches. 
     Control circuit  400  includes a current feedback loop  404  and a bus voltage feedforward path  406 . Current feedback loop  404  computes a current error  408  that is a difference between a demanded current (I L *) for power converter  200  and the actual current (I L ) through power converter  200 . Feedback loop  404  includes, in certain embodiments, for example, a PI controller  410  that aims to minimize the current error  408  and produces an output signal that is modulated by a PWM modulator  412  to produce PWM control signal  402  for one or more of semiconductor switches  210  and  218  of power converter  200 . PI controller  410  should generally have a high gain (G fb ). For example, in certain embodiments, the gain (G fb ) of PI controller  410  is at least 20 dB in the frequency range at which the voltage variation event occurs, e.g., around 200 Hz. 
     Bus voltage feedforward path  406  utilizes a measured bus voltage (V bus ) on DC bus  112  (shown in  FIG. 1 ) to adjust a duty cycle signal  414  representing a duty cycle at which PWM modulator  412  is to generate PWM control signal  402 . The measured bus voltage (V bus ) is generally gained  416  (e.g., with a gain of G if ) before being combined with the output signal of PI controller  410  to produce the duty cycle signal  414 . Bus voltage feedforward path  406  should have a high bandwidth, e.g., at least 1000 Hz, and a high sampling rate to reduce lag in the feedforward response through control circuit  400 . The sampling rate, or sampling frequency, in certain embodiments, for bus voltage feedforward path  406  should be several times the frequency at which semiconductor switches  210  and  218  are switched. For example, in certain embodiments, where the switching frequency is about 30 KHz, the sampling frequency for bus voltage feedforward path  406  should be at least 240 KHz. If bus voltage feedforward path  406  detects a voltage variation event, its output will result in an adjustment of PWM control signal  402  generated by control circuit  400 , and a corresponding regulation of current (I L ) through power converter  200 . 
     Control circuit  400  includes a fast-response protection path  418  that includes a logic circuit  420  for monitoring current (I L ) through power converter  200  for rapid changes, resulting in a fast-response current control signal  422  that is applied directly to PWM control signal  402  to enable/disable PWM control signal  402 . Generally, because the current sensing bandwidth is higher than voltage sensing bandwidth, current sensing enables monitoring of current (I L ) through power converter  200  to be a leading indicator of a voltage variation event. Current monitoring further enables improvement in the response rate at which control circuit  400  can operate. In one embodiment, logic circuit  420  evaluates the measured current (I L ) through power converter  200  in a series of logical evaluations in the context of demanded current (I L *) and the bus voltage on DC bus  112  (shown in  FIG. 1 ). More specifically, in one embodiment, the current error  408  is computed and compared to a current error threshold. If current error exceeds a threshold, logic circuit  420  proceeds to a second evaluation of whether the current error is, for example, increasing. If the current error is increasing over time, logic circuit  420  proceeds to a third evaluation of whether the demanded current (I L *) is changing in a manner, e.g., rapidly, such that it would account for the significant change in current error over time. If the change in demanded current (I L *) is below a demanded current change threshold (i.e., the change in measured current (I L ) is not due to a change in demanded current (I L  *)), then fast-response current control signal  422  operates to disable PWM control signal  412  and, consequently, the output of power converter  200 . 
     Logic circuit  420 , in certain embodiments, may further include a restart logical evaluation to enable the PWM control signal  402  when the bus voltage stabilizes. In such embodiments, logic circuit  420  evaluates whether the change in bus voltage over time, positive or negative, falls below a voltage change threshold for restarting, or re-enabling, power converter  200 . 
     The above described logical evaluation in logic circuit  420  is only one example of the one or more logical tests that may be incorporated into logic circuit  420  for the purpose of producing fast-response current control signal  422 . Likewise, the current error threshold, the demanded current change threshold, and the voltage change threshold may be customized for a given power converter  200  and application, such as power system  100 . 
       FIG. 5  is a plot  500  of voltage and current in a power converter, such as power converter  200  (shown in  FIG. 2 ) from a simulation illustrating a method of using control circuit  400  (shown in  FIG. 4 ) during a voltage variation event. Plot  500  includes current plots  502  for a PHASE 1 and a PHASE 2 (shown in light and dark grey, respectively) in power converter  200 . Current plots  502  illustrate current expressed in amperes (A) along a vertical axis  504  versus time expressed in tenths of a second (tenths) along a horizontal axis  506 . Current ranges from just above 0 A to just below −60 A. Time ranges from just before 4.00 tenths to about 4.03 tenths. Plot  500  also includes a bus voltage plot  508  illustrating a high dV/dt event experienced on DC bus  112  (shown in  FIG. 1 ). Bus voltage plot  508  illustrates voltage expressed in volts (V) along a vertical axis  510  versus time (tenths) on horizontal axis  506 . Voltage ranges from about 800 V to about 1200 V. 
     Plot  500  illustrates the occurrence of a high dV/dt event at a time of approximately 4.00 tenths, shown by a first vertical marker  512 , or dashed line. During a first period of time between first vertical marker  512  and a second vertical marker  514 , current feedback loop  404  and bus voltage feedforward path  406  combine to detect the change in bus voltage and attempt to restrict the current throughput of power converter  200 , illustrated by PHASE 1 and PHASE 2 current plots  502 , which is increasing rapidly with the voltage ramp illustrated in bus voltage plot  508  from a demanded current value (about −20 A). At a time corresponding to second vertical marker  514  (about 300 microseconds after the high dV/dt event began), fast-response protection path  418  detects the high dV/dt event using current monitoring and logic circuit  420 , resulting in a disabling of current output by power converter  200 . The disabling is illustrated by a sharp reduction of PHASE 1 and PHASE 2 currents to 0 A in current plots  502 . At a third vertical marker  516  (about 3 ms after the high dV/dt event began), fast-response protection path  418  determines, based on the sensed bus voltage, the high dV/dt event has lapsed and current output by power converter  200  may be restarted, although the bus voltage itself is much higher (about 1200 V) than before the high dV/dt event. The restarting of current output from power converter  200  is illustrated in current plots  502  re-converging on the prior demanded current value (about −20 A). 
       FIG. 6  is a flow diagram of a method  600  of controlling power converter  200  (shown in  FIGS. 1 and 2 ) during a bus voltage variation event using, for example, control circuit  400  (shown in  FIG. 4 ). The method includes generating  602  PWM control signal  402  for commutating a plurality of semiconductor switches  210  and  218  of power converter  200  to converge a load current provided through power converter  200  to a demanded current. The bus voltage supplied to power converter  200  at input bus  202  is sampled  604  at a frequency of at least twice a switching frequency at which semiconductor switches  210  and  218  are commutated. PWM control signal  402  is modified  606  based on the bus voltage to regulate the load current. Control circuit  400  collects  608  load current measurements and then determines  610 , using logic circuit  420  based at least partially on the load current measurements, a voltage variation event has occurred on input bus  202 . In response, control circuit  400  disables  612  PWM control signal  402  for power converter  200 . 
     In at least some embodiments, method  600  further includes comparing, by logic circuit  420 , the bus voltage to a subsequent bus voltage to determine a change in bus voltage over time, and re-enabling PWM control signal  402  for power converter  200  when the change in bus voltage over time falls below a voltage change threshold. 
     The above described embodiments of a control circuit and method under a bus voltage variation event for a power converter. The control circuits and methods described herein improve the speed of detection of high dV/dt events by enabling high dl/dt detection as a leading indicator of the high dV/dt event, and by increasing the sensing frequency of bus voltage supplied to the power converter to enhance feedforward compensation and improve disturbance rejection capability of current control. 
     An exemplary technical effect of the methods, systems, and apparatus described herein includes at least one of: (a) improving detection of high dV/dt events on an input bus for a power converter; (b) utilizing high dl/dt detection as a leading indicator for a high dV/dt event; (c) improving speed of feedforward compensation of power conversion to the output bus of the power converter; (d) enabling restart to resume normal operation after the high dV/dt event. 
     Exemplary embodiments of methods, systems, and apparatus for switching circuits are not limited to the specific embodiments described herein, but rather, components of systems and/or steps of the methods may be utilized independently and separately from other components and/or steps described herein. For example, the methods may also be used in combination with other non-conventional switching circuits, and are not limited to practice with only the systems and methods as described herein. Rather, the exemplary embodiment can be implemented and utilized in connection with many other applications, equipment, and systems that may benefit from reduced cost, reduced complexity, commercial availability, improved manufacturability, and reduced product time-to-market. 
     Although specific features of various embodiments of the disclosure may be shown in some drawings and not in others, this is for convenience only. In accordance with the principles of the disclosure, any feature of a drawing may be referenced and/or claimed in combination with any feature of any other drawing. 
     This written description uses examples to disclose the embodiments, including the best mode, and also to enable any person skilled in the art to practice the embodiments, including making and using any devices or systems and performing any incorporated methods. The patentable scope of the disclosure is defined by the claims, and may include other examples that occur to those skilled in the art. Such other examples are intended to be within the scope of the claims if they have structural elements that do not differ from the literal language of the claims, or if they include equivalent structural elements with insubstantial differences from the literal language of the claims.