Patent Publication Number: US-2011068756-A1

Title: Band-gap reference voltage generation circuit

Description:
The present application claims priority under 35 U.S.C. 119 to Korean Patent Application No. 10-2008-0134206 (filed on Dec. 26, 2008) which is hereby incorporated by reference in its entirety. 
     BACKGROUND 
     Embodiments relate to a semiconductor device. Some embodiments relate to a band-gap reference voltage generation circuit which may substantially compensate for process variation, and methods thereof. 
     In a semiconductor memory device, currents output from transistors may be varied in accordance with a variation in temperature. The performance of a circuit constituted by transistors may be varied. For example, an increase in temperature may occur such that transistors may exhibit a relative decrease in mobility upon relatively strong inversion thereof. Currents output from transistors may be minimized, and/or operating speed of a circuit may be minimized. 
     To offset a performance variation of a semiconductor device which may be caused by a variation in temperature, a technique to vary a reference voltage in accordance with a variation in temperature may be used. In such a technique, a reference voltage may be relatively increased at a relatively high temperature, which may relatively increase current, whereas a reference voltage may be relatively decreased at a relatively low temperature, which may relatively reduce current. Thus, current output from each transistor may be maintained in a desired amount, irrespective of a variation in temperature, and/or it may be possible to secure a desired performance of a semiconductor device irrespective of a variation in temperature. 
     A band-gap reference voltage generation circuit may be used in a method of varying a reference voltage in accordance with a variation in temperature. Referring to example  FIG. 1 , a circuit diagram illustrates a band-gap reference voltage generation circuit. Reference voltage V ref  may be provided as a reference voltage for a circuit to generate an internal supply voltage. Current I PTAT  may be generated in a circuit indicated by a dotted-line box. Generated current I PTAT  may be mirrored into transistor M 3 , and/or may be supplied to a resistor R 1 . A positive temperature coefficient (TC) voltage may be generated. At node Z, a positive TC voltage, which may be generated by current I PTAT , may be added to a base-emitter voltage of transistor Q 3 , namely, a negative TC voltage. Therefore, a band-gap reference voltage may be generated. 
     In a band-gap reference voltage generation circuit, there may be an offset of an input of an operational amplifier (OP-AMP) due to a process variation occurring in a manufacture of a chip. An offset voltage generated may be V os , such that a resultant band-gap reference voltage may have an error corresponding to approximately 20×V os . Accordingly, there is a need for a band-gap reference voltage generation circuit, and methods thereof, which may be capable of being substantially stable irrespective of process variation. 
     SUMMARY 
     Embodiments relate to a band-gap reference voltage generation circuit and methods thereof. According to embodiments, a band-gap reference voltage generation circuit may substantially compensate for process variation. 
     According to embodiments, a band-gap reference voltage generation circuit may include a current generator generating a first current and/or a second current. In embodiments, a band-gap reference voltage generation circuit may include a current controller including a first resistor, through which a first current may flow. In embodiments, a band-gap reference voltage generation circuit may include a first bipolar transistor connected with a first resistor at an emitter of a first bipolar transistor, and/or connected with a node at a base of a first bipolar transistor. In embodiments, a band-gap reference voltage generation circuit may include a second bipolar transistor connected with a node at a base of a second bipolar transistor. 
     According to embodiments, a band-gap reference voltage generation circuit may include a current controller configured to generate a proportional to absolute temperature (PTAT) current at a first resistor. In embodiments, a band-gap reference voltage generation circuit may include a feedback unit configured to control first and/or second currents to be substantially equal. In embodiments, a band-gap reference voltage generation circuit may include a band-gap voltage output unit configured to generate a reference voltage in response to a PTAT current. 
     According to embodiments, a band-gap reference voltage generation circuit may include first and second bipolar transistors connected with each other between bases of first and second bipolar transistors. In embodiments, a band-gap reference voltage generation circuit may include a first bipolar transistor having an emitter area n times as large as an emitter area of a second bipolar transistor. In embodiments, a band-gap reference voltage generation circuit may include a first resistor, through which a first current may flow, and/or a first resistor connected with an emitter of a first bipolar transistor. In embodiments, a band-gap reference voltage generation circuit may include a feedback unit connected with a second bipolar transistor, which may be configured to control a second current flowing through a collector of a second bipolar transistor, such that a second current may be substantially equal to a first current. 
    
    
     
       DRAWINGS 
       Example  FIG. 1  is a circuit diagram illustrating a band-gap reference voltage generation circuit. 
       Example  FIG. 2  is a circuit diagram illustrating a band-gap reference voltage generation circuit in accordance with embodiments. 
     
    
    
     DESCRIPTION 
     Embodiments relate to a band-gap reference voltage generation circuit and methods thereof. Referring to example  FIG. 2 , a circuit diagram illustrates a band-gap reference voltage generation circuit in accordance with embodiments. According to embodiments, a band-gap reference voltage generation circuit may include current generator  110 , feedback unit  120 , current controller  130  and/or band-gap voltage output unit  140 . In embodiments, current generator  110  may include PMOS transistor M 3 , bipolar transistor Q 1  and/or bipolar transistor Q 2 . In embodiments, PMOS transistor M 3  may receive, at a source thereof, a supply voltage VDD. In embodiments, PMOS transistor M 3  may be connected, at a drain thereof, to emitters of bipolar transistor Q 1  and/or bipolar transistor Q 2 . In embodiments, bases of bipolar transistor Q 1  and bipolar transistor Q 2  may be connected with each other. In embodiments, a base and a collector of a bipolar transistor Q 1  may be connected with each other. 
     According to embodiments, current generator  110  may generate first current I Q1  and/or second current I Q2 . In embodiments, first current I Q1  may include a proportional to absolute temperature (PTAT) current, which may flow through first resistor R 1 . In embodiments, first current I Q1  may flow through a collector of bipolar transistor Q 1 , and/or second current I Q2  may flow through a collector of bipolar transistor Q 2 . 
     According to embodiments, feedback unit  120  may include capacitor C 1 , bipolar transistor Q 7  and/or PMOS transistor M 2 . In embodiments, feedback unit  120  may control voltage V fb , which may substantially equalize first current I Q1  and second current I Q2 . In embodiments, feedback unit  120  may substantially equalize first current I Q1  and second current I Q2  using a negative feedback. In embodiments, feedback unit  120  may include PMOS transistor M 2  having a gate voltage varying in accordance with second current I Q2 . 
     According to embodiments, current controller  130  may include bipolar transistors Q 3 , Q 4  and/or Q 5 . In embodiments, first resistor R 1  may be included in current controller  130 . In embodiments, a base and a collector of bipolar transistor Q 3  may be connected with a drain of PMOS transistor Q 2 . In embodiments, bases of bipolar transistor Q 3  and bipolar transistor Q 4  may be connected with a drain of PMOS transistor M 2 . In embodiments, bases of bipolar transistor Q 3  and bipolar transistor Q 4  may be connected with the same node, such that substantially the same current may be applied to the bases. In embodiments, first resistor R 1  may be connected with an emitter of bipolar transistor Q 3 . In embodiments, base voltages of bipolar transistor Q 3  and bipolar transistor Q 4  may be substantially equal. In embodiments, current I PTAT  output from current controller  130  may correspond to V BE2 −V BE1 /R 1 , and/or may be substantially equal to first and/or second currents I Q1  and/or I Q2 , for example I Q1 =I Q2 =I PTAT =(V BE2 −V BE1 )/R 1 . 
     According to embodiments, band-gap reference voltage output unit  140  may output band-gap reference voltage V band-gap  by mirroring first current I Q1  generated as described, namely, a PTAT current. In embodiments, generated PTAT current I PTAT  may be mirrored through PMOS transistors M 2  and/or M 4 , and/or may be applied to second resistor R 2 . In embodiments, a positive temperature coefficient (TC) voltage may be generated. In embodiments, at a node Z, a positive TC voltage, which may be generated by current I PTAT , may be added to a base-emitter voltage of a transistor Q 4 , namely, a negative TC voltage. In embodiments, band-gap reference voltage V band-gap  may be generated. In embodiments, an offset may not be generated when a PTAT current may be generated, since bases of bipolar transistors Q 3  and Q 4  may be connected with the same node, and/or since a condition of V BE2 =I PTAT /R 1 =V BE1  may be established. 
     According to embodiments, band-gap reference voltage V band-gap  generated from a band-gap reference voltage generation circuit may be expressed as follows: 
     Embodiments including substantially no mismatch: 
     
       
      
       I 
       Q1 
       =nI 
       s 
       e 
       V 
       
         BE1 
       
       /V 
       
         T  
       
      
     
     
       
      
       I 
       Q2 
       =nI 
       s 
       e 
       V 
       
         BE2 
       
       /V 
       
         T  
       
      
     
       I Q1 I Q2    
       ∴ V   BE2   −V   BE2   =V   T   *In ( n )
 
       V X =V Y    
       ∴ V   BE2   =I   Q1   *R 1+ V   BE1  
 
         I   Q1   =I   PTAT   =V   T   *In ( n )/ R 1 
       ∴ V   Z   =V   BE4 +( R 2/ R 1)* V   T   *In ( n )
 
     Embodiments including mismatch, assuming I mismatch  and α may be generated due to a mismatch: 
         I   Q1   ′=I   Q1   +I   mismatch =( n +α) I   s   e   V     BE1     /V     T    
 
         I   Q1   ′=I   Q1   +I   mismatch =( n +α) I   s   e   V     BE1     /V     T    
 
     
       
      
       I 
       Q2 
       ′=I 
       Q2 
       −I 
       mismatch 
       =I 
       s 
       e 
       V 
       
         BE2 
       
       /V 
       
         T  
       
      
     
         I   Q1 ′=(1.02)* I   Q2 ′ (For example,  I   mismatch =0.01* I   Q1 )
 
       ∴ V   BE2   −V   BE2   =V   T   *[In ( n +α)− In (1.02)]
 
       V X =V Y    
       ∴ V   BE2   =I   Q1   *R 1+ V   BE1  
 
         I   Q1   =I   PTAT   =[V   T   *In ( n +α)− In (1.02)]/ R 1
 
       ∴ V   Z   =V   BE4 +( R 2/ R 1)* V   T   *[In ( n+α )+( R 2/ R 1)* V   T   *In (1.02)
 
     According to embodiments, a mismatch may occur due to process variation. In embodiments, first and second currents may be different from each other, for example I Q1 ≠I Q2 , and/or a size (nA) of an emitter of bipolar transistor Q 3  may not be substantially equal to n times the size (A) of an emitter of bipolar transistor Q 4 . In embodiments, such errors caused by mismatch may be as low as approximately 1/10 or less of the errors generated in other structures. In embodiments, a band-gap reference voltage generation circuit in accordance with embodiments may substantially prevent generation of an offset, for example using a feedback circuit. In embodiments, it may be possible to minimize voltage dispersion which may be caused by process variation. 
     It will be obvious and apparent to those skilled in the art that various modifications and variations can be made in the embodiments disclosed. Thus, it is intended that the disclosed embodiments cover the obvious and apparent modifications and variations, provided that they are within the scope of the appended claims and their equivalents.