Patent Publication Number: US-8536013-B2

Title: Forming phase change memory cells

Description:
BACKGROUND 
     1. Technical Field 
     The present invention relates generally to phase change memories that use chalcogenide materials. 
     2. Description of the Related Art 
     Phase change memory devices use phase change materials, i.e., materials that may be electrically switched between a generally amorphous and a generally crystalline state, for electronic memory application. One type of memory element utilizes a phase change material that may be, in one application, electrically switched between a structural state of generally amorphous and generally crystalline local order or between different detectable states of local order across the entire spectrum between completely amorphous and completely crystalline states. The state of the phase change materials is also non-volatile in that, when set in either a crystalline, semi-crystalline, amorphous, or semi-amorphous state representing a resistance value, that value is retained until changed by another programming event, as that value represents a phase or physical state of the material (e.g., crystalline or amorphous). The state is unaffected by removing electrical power. 
     Scaling of phase change memory cells is often limited by registration requirements for lithography pattern transfer over multiple critical layers for the memory cell construction. 
     Thus, it would be desirable to devise a process for manufacturing phase change memory cells that potentially reduces the number of critical lithography steps. 
     BRIEF SUMMARY 
     One embodiment is a process for manufacturing a phase-change memory device that potentially allows to reduce the number of critical layers. 
     The description refers to two schemes wherein the memory regions are formed on top of segmented heater walls, with a sub-lithographic heater/chalcogenide interface area defined by using a spacer technique. 
     One embodiment uses metallic spacers instead a metallic cap layer, e.g., of Ti/TiN, created in prior art methods using lithography and etch steps. 
     Another embodiment utilizes etch-back of chalcogenide material combined with deposition and planarization of a metallic cap layer through CMP (Chemical Mechanical Polishing). 
    
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
         FIGS. 1 ,  2  are enlarged, cross-sectional views of one embodiment in two manufacturing steps along a direction X; 
         FIG. 3  is an enlarged cross-sectional view of one embodiment, along a direction Y; 
         FIG. 4  is a top plan view; 
         FIG. 5  is an enlarged cross-sectional view in a subsequent manufacturing step along direction X; 
         FIG. 6  is an enlarged cross-sectional view of one embodiment, along direction Y; 
         FIG. 7  is an enlarged cross-sectional view in a subsequent manufacturing step along the direction X; 
         FIG. 8  is an enlarged cross-sectional view of one embodiment, along direction Y; 
         FIGS. 9-10  are enlarged cross-sectional views in subsequent manufacturing steps along direction X; 
         FIG. 11  is a top plan view; 
         FIGS. 12-16  are enlarged cross-sectional views in subsequent manufacturing steps along direction X; and 
         FIGS. 17-20  are enlarged, cross-sectional views at subsequent manufacturing steps along direction X in accordance with another embodiment. 
     
    
    
     DETAILED DESCRIPTION 
     In accordance with one embodiment, a raised emitter array may be formed in between bases to form a bipolar junction transistor select device. However, in other embodiments, other select devices may be utilized, including chalcogenide select devices, such as ovonic threshold switches, diode select devices, and transistor select devices. 
     Referring to  FIG. 1 , a base substrate  10  has active areas  11  therein accommodating electric components. Raised emitters  12  and raised bases  14  are formed on the substrate. An intervening dielectric material  24  may separate the raised bases and emitters. A salicide  16  may be formed over the raised bases  14  and raised emitters  12 . 
     Thereover, a silicon nitride layer  1  and an oxide layer  2  are deposited. Then,  FIGS. 2-4 , heater trenches  4  are opened in the oxide layer  2  and in the silicon nitride layer  1 . The heater trenches  4  are substantially rectilinear and extend e.g., in the row direction X, exposing only about half of the raised bases  14  and of the raised emitters  12 . In particular, each heater trench  4  exposes the facing portions of the raised bases  14  and emitters  12  belonging to two adjacent rows and covers the other two portions of the same raised bases  14  and emitters  12 , as disclosed in, e.g., U.S. Pat. No. 7,422,926. 
     Then,  FIGS. 5-6 , a heater layer  18  and, optionally, a dielectric sheath layer  19 , both having sublithographic thickness, are conformally deposited. The heater layer  18  may be formed, for example, from titanium silicon nitride. However, other heater materials may also be used. Moreover, preferably, the thickness of the heater layer  18  is in the range of 5-20 nm. 
     The heater layer  18  and the sheath layer  19  are etched back and flat portions thereof are removed from the bottom of the heater trench  4  ( FIG. 8 ). In practice, vertical portions of the heater layer  18  and of the sheath layer  19  adhering to sides of the heater trenches  4  are separated from each other and define L-shaped heater walls  18  running parallel to the row direction X. A filling layer  8  (e.g., oxide) is deposited on the wafer  100 . Then, the excess filling layer  8  and the oxide layer  2  are etched back down to the nitride layer  1 , as shown in  FIGS. 7 and 8 . 
     Thereover,  FIG. 9 , a stop layer  20  and a sacrificial layer  22  are formed. 
     The stop layer  20  may be formed of a variety of insulating materials. In one embodiment, the stop layer  20  may be oxide, in another embodiment, the stop layer  20  is of nitride and oxide. In one embodiment, the sacrificial layer  22  is a nitride layer. The sacrificial layer  22  can be any material that is selectively etchable with respect to the stop layer  20 . 
     In accordance with  FIGS. 10 and 11 , a segmented heater lithography and etch is done to segment the heater walls  18  on top of the emitters and bases, landing on the emitter base salicide  16 .  FIG. 11  shows the segmented heater mask  50 , overlaid to a MBIT mask  51  used to form the heater trenches  4  of  FIGS. 3-4 . Also shown are an emitter mask  52  and a base mask  53 . In the embodiment, the segmented heater mask  50  extends transversely to the MBIT mask  51 . For example, it is perpendicular. The sacrificial layer  22  may be patterned and etched to serve as a mask when etching the heater walls  18  and the stop layer  20 . The etch proceeds all the way down to the emitter base structure. As a result, the heater layer  18  is now segmented to define segmented heaters  18 . 
     Then, referring to  FIG. 12 , a passivation layer  28  may be deposited to protect the exposed heater edge along the segmented heater stack. The passivation layer  28  may be an insulator such as nitride. Then, a dielectric fill  30  may be done, followed by chemical mechanical planarization to planarize the surface, stopping on the sacrificial layer  22 . 
     Turning now to  FIG. 13 , the sacrificial layer  22  may be removed, stopping on the stop layer  20 . 
     Then, in  FIG. 14 , metallic spacers  32  may be formed by depositing a suitable metal, such as tungsten, and performing an anisotropic spacer formation etch. The metal spacers  32  land on the stop layer  20 . 
     Then, as shown in  FIG. 15 , the stop layer  20  is mostly etched away, exposing the segmented heaters  18  through a sublithographic width pore  34 . By “sublithographic” it is intended to refer to a dimension which is smaller than what can be formed with lithographic techniques. Currently, lithographic techniques can form dimensions of about 45 nanometers. In one embodiment, the width of the pore  34  may be on the order of 10 to 20 nanometers. 
     Then, turning to  FIG. 16 , a chalcogenide layer  36  may be deposited and planarized. The chalcogenide layer  36 , in one embodiment, may be the phase change material sometimes referred to as GST, including germanium, antimony, and tellurium. 
     Finally, conventional process steps may be utilized to complete the memory. For instance, a dielectric layer (not shown) that is a composite layer of nitride and oxide may be deposited. A contact (not shown) may be dropped at a strap region, landing on the shoulder of the metallic spacer  32 . Separate lithography and etch steps may be used to drop contacts to the raised bases  14 . 
     In accordance with a different embodiment, the sequence illustrated in  FIGS. 1-13  may be repeated. Then, a dielectric spacer  32   a  ( FIG. 17 ) may be formed. The spacer  32   a  may be formed of nitride instead of the metallic spacer  32  of  FIG. 14 . Then, using the dielectric spacer  32   a  as a mask (instead of the metallic spacer  32 ), the stop layer  20  is etched to form the sublithographic aperture  34 , as shown in  FIG. 17 . 
     Then, as shown in  FIG. 18 , a chalcogenide layer  36  is deposited and then brought back below the spacer top surface. In one embodiment, an etch-back of the chalcogenide  34  may use a dry etch back process. 
     Referring next to  FIG. 19 , a metallic cap layer  38  may be deposited and planarized. The cap layer  38  may be a Ti/TiN composite layer, as one example. 
     The remaining process steps may be as conventional. For example, a dielectric layer (not shown) that is a composite of nitride and oxide may be deposited. A contact may be dropped to a strap region, landing on the metallic cap layer. Separate lithography and etch steps may be used to drop contacts to bases. 
     In some embodiments, three critical lithography steps of prior art methods can be reduced to one lithography step combined with self-aligned features. Phase change memory cells may be closer to a four F 2  cell area plus the base contact area overhead because the cell width is defined by 2F in the segmented heater process, while cell height is defined by another 2F in the shallow trench isolation region between base diffusion strips. 
     Programming of the chalcogenide material  36  to alter the state or phase of the material may be accomplished by applying voltage potentials through a select device, formed on a substrate, thereby generating a voltage potential across the memory element. When the voltage potential is greater than the threshold voltage of memory element, then an electrical current may flow through the chalcogenide material  36  in response to the applied voltage potentials, and may result in heating of the chalcogenide material  36  by the segmented heater  18 . 
     This heating may alter the memory state or phase of the chalcogenide material  36 . Altering the phase or state of the chalcogenide material  36  may alter the electrical characteristic of memory material, e.g., the resistance of the material may be altered by altering the phase of the memory material. Memory material may also be referred to as a programmable resistive material. 
     In the “reset” state, memory material  36  may be in an amorphous or semi-amorphous state and in the “set” state, memory material may be in a crystalline or semi-crystalline state. Both “reset” and “set” states can exist without any energy (electrical, optical, mechanical) applied to bistable chalcogenide. The resistance of memory material in the amorphous or semi-amorphous state may be greater than the resistance of memory material in the crystalline or semi-crystalline state. It is to be appreciated that the association of reset and set with amorphous and crystalline states, respectively, is a convention and that at least an opposite convention may be adopted. 
     Using electrical current, memory material  36  may be heated to a relatively higher temperature to amorphosize the memory material and “reset” the memory material (e.g., program the memory material to a logic “0” value). Heating the volume of memory material to a relatively lower crystallization temperature may crystallize the memory material and “set” the memory material (e.g., program the memory material to a logic “1” value). Various resistances of the memory material may be achieved to store information by varying the amount of current flow and duration through the volume of memory material. 
     Turning to  FIG. 20 , a portion of a system  500  in accordance with an embodiment of the present invention is described. System  500  may be used in wireless or mobile devices such as, for example, a personal digital assistant (PDA), a laptop or portable computer with wireless capability, a web tablet, a wireless telephone, a pager, an instant messaging device, a digital music player, a digital camera, or other devices that may be adapted to transmit and/or receive information wirelessly. System  500  may be used in any of the following systems: a wireless local area network (WLAN) system, a wireless personal area network (WPAN) system, a cellular network, although the scope of the present invention is not limited in this respect. 
     System  500  may include a controller  510 , an input/output (I/O) device  520  (e.g., a keypad, display), static random access memory (SRAM)  560 , a memory  530 , and a wireless interface  540  coupled to each other via a bus  550 . A battery  580  may be used in some embodiments. It should be noted that the scope of the present invention is not limited to embodiments having any or all of these components. 
     Controller  510  may comprise, for example, one or more microprocessors, digital signal processors, microcontrollers, or the like. Memory  530  may be used to store messages transmitted to or by system  500 . Memory  530  may also optionally be used to store instructions that are executed by controller  510  during the operation of system  500 , and may be used to store user data. Memory  530  may be provided by one or more different types of memory. For example, memory  530  may comprise any type of random access memory, a volatile memory, a non-volatile memory such as a flash memory and/or a memory such as memory discussed herein. 
     I/O device  520  may be used by a user to generate a message. System  500  may use wireless interface  540  to transmit and receive messages to and from a wireless communication network with a radio frequency (RF) signal. Examples of wireless interface  540  may include an antenna or a wireless transceiver, although the scope of the present invention is not limited in this respect. 
     References throughout this specification to “one embodiment” or “an embodiment” mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one implementation encompassed within the present invention. Thus, appearances of the phrase “one embodiment” or “in an embodiment” are not necessarily referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be instituted in other suitable forms other than the particular embodiment illustrated and all such forms may be encompassed within the claims of the present application. 
     The various embodiments described above can be combined to provide further embodiments. All of the U.S. patents, U.S. patent application publications, U.S. patent applications, foreign patents, foreign patent applications and non-patent publications referred to in this specification and/or listed in the Application Data Sheet are incorporated herein by reference, in their entirety. Aspects of the embodiments can be modified, if necessary to employ concepts of the various patents, applications and publications to provide yet further embodiments. 
     These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.