Patent Publication Number: US-6338127-B1

Title: Method and apparatus for resynchronizing a plurality of clock signals used to latch respective digital signals, and memory device using same

Description:
TECHNICAL FIELD 
     The present invention relates generally to integrated circuit devices, and more particularly to resynchronizing a plurality of internal clock signals derived from respective external clock signals to ensure the internal clock signals can be used in latching respective external digital signals at the optimum times. 
     BACKGROUND OF THE INVENTION 
     Conventional computer systems include a processor (not shown) coupled to a variety of memory devices, including read-only memories (“ROMs”) which traditionally store instructions for the processor, and a system memory to which the processor may write data and from which the processor may read data. The processor may also communicate with an external cache memory, which is generally a static random access memory (“SRAM”). The processor also communicates with input devices, output devices, and data storage devices. 
     Processors generally operate at a relatively high speed. Processors such as the Pentium® and Pentium II® microprocessors are currently available that operate at clock speeds of at least 400 MHz. However, the remaining components of existing computer systems, with the exception of SRAM cache, are not capable of operating at the speed of the processor. For this reason, the system memory devices, as well as the input devices, output devices, and data storage devices, are not coupled directly to the processor bus. Instead, the system memory devices are generally coupled to the processor bus through a memory controller, bus bridge or similar device, and the input devices, output devices, and data storage devices are coupled to the processor bus through a bus bridge. The memory controller allows the system memory devices to operate at a lower clock frequency that is substantially lower than the clock frequency of the processor. Similarly, the bus bridge allows the input devices, output devices, and data storage devices to operate at a substantially lower frequency. Currently, for example, a processor having a 300 MHz clock frequency may be mounted on a mother board having a 66 MHz clock frequency for controlling the system memory devices and other components. 
     Access to system memory is a frequent operation for the processor. The time required for the processor, operating, for example, at 300 MHz, to read data from or write data to a system memory device operating at, for example, 66 MHz, greatly slows the rate at which the processor is able to accomplish its operations. Thus, much effort has been devoted to increasing the operating speed of system memory devices. 
     System memory devices are generally dynamic random access memories (“DRAMs”). Initially, DRAMs were asynchronous and thus did not operate at even the clock speed of the motherboard. In fact, access to asynchronous DRAMs often required that wait states be generated to halt the processor until the DRAM had completed a memory transfer. However, the operating speed of asynchronous DRAMs was successfully increased through such innovations as burst and page mode DRAMs which did not require that an address be provided to the DRAM for each memory access. More recently, synchronous dynamic random access memories (“SDRAMs”) have been developed to allow the pipelined transfer of data at the clock speed of the motherboard. However, even SDRAMs are incapable of operating at the clock speed of currently available processors. Thus, SDRAMs cannot be connected directly to the processor bus, but instead must interface with the processor bus through a memory controller, bus bridge, or similar device. The disparity between the operating speed of the processor and the operating speed of SDRAMs continues to limit the speed at which processors may complete operations requiring access to system memory. 
     A solution to this operating speed disparity has been proposed in the form of a computer architecture known as a synchronous link architecture. In the synchronous link architecture, the system memory may be coupled to the processor either directly through the processor bus or through a memory controller. Rather than requiring that separate address and control signals be provided to the system memory, synchronous link memory devices receive command packets that include both control and address information. The synchronous link memory device then outputs or receives data on a data bus that may be coupled directly to the data bus portion of the processor bus. 
     An example of a computer system  10  using the synchronous link architecture is shown in FIG.  1 . The computer system  10  includes a processor  12  having a processor bus  14  coupled through a memory controller  18  and system memory bus  22  to three packetized or synchronous link dynamic random access memory (“SLDRAM”) devices  16   a-c . The computer system  10  also includes one or more input devices  20 , such as a keypad or a mouse, coupled to the processor  12  through a bus bridge  22  and an expansion bus  24 , such as an industry standard architecture (“ISA”) bus or a peripheral component interconnect (“PCI”) bus. The input devices  20  allow an operator or an electronic device to input data to the computer system  10 . One or more output devices  30  are coupled to the processor  12  to display or otherwise output data generated by the processor  12 . The output devices  30  are coupled to the processor  12  through the expansion bus  24 , bus bridge  22  and processor bus  14 . Examples of output devices  24  include printers and a video display units. One or more data storage devices  38  are coupled to the processor  12  through the processor bus  14 , bus bridge  22 , and expansion bus  24  to store data in or retrieve data from storage media (not shown). Examples of storage devices  38  and storage media include fixed disk drives floppy disk drives, tape cassettes and compact-disk read-only memory drives. 
     In operation, the processor  12  sends a data transfer command via the processor bus  14  to the memory controller  18 , which, in turn, communicates with the memory devices  16   a-c  via the system memory bus  22  by sending the memory devices  16   a-c  command packets that contain both control and address information. Data is coupled between the memory controller  18  and the memory devices  16   a-c  through a data bus portion of the system memory bus  22 . During a read operation, data is transferred from the SLDRAMs  16   a-c  over the memory bus  22  to the memory controller  18  which, in turn, transfers the data over the processor  14  to the processor  12 . The processor  12  transfers write data over the processor bus  14  to the memory controller  18  which, in turn, transfers the write data over the system memory bus  22  to the SLDRAMs  16   a-c . Although all the memory devices  16   a-c  are coupled to the same conductors of the system memory bus  22 , only one memory device  16   a-c  at a time reads or writes data, thus avoiding bus contention on the memory bus  22 . Bus contention is avoided by each of the memory devices  16   a-c  on the system memory  22  having a unique identifier, and the command packet contains an identifying code that selects only one of these components. 
     The computer system  10  also includes a number of other components and signal lines that have been omitted from FIG. 1 in the interests of brevity. For example, as explained below, the memory devices  16   a-c  also receive a master clock signal to provide internal timing signals, a data clock signal clocking data into and out of the memory device  16 , and a FLAG signal signifying the start of a command packet. 
     A typical command packet CA&lt; 0 : 39 &gt; for an SLDRAM is shown in FIG.  2  and is formed by 4 packet words CA&lt; 0 : 9 &gt;, each of which contains 10 bits of data. As will be explained in more detail below, each packet word CA&lt; 0 : 9 &gt; is applied on a command address bus CA including 10 lines CA 0 -CA 9 . In FIG. 2, the four packet words CA&lt; 0 : 9 &gt; comprising a command packet CA&lt; 0 : 39 &gt; are designated PW 1 -PW 4 . The first packet word PW 1  contains 7 bits of data identifying the packetized DRAM  16   a-c  that is the intended recipient of the command packet. As explained below, each of the packetized DRAMs is provided with a unique ID code that is compared to the 7 ID bits in the first packet word PW 1 . Thus, although all of the packetized DRAMs  16   a-c  will receive the command packet, only the packetized DRAM  16   a-c  having an ID code that matches the 7 ID bits of the first packet word PW 1  will respond to the command packet. 
     The remaining 3 bits of the first packet word PW 1  as well as 3 bits of the second packet word PW 2  comprise a 6 bit command. Typical commands are read and write in a variety of modes, such as accesses to pages or banks of memory cells. The remaining 7 bits of the second packet word PW 2  and portions of the third and fourth packet words PW 3  and PW 4  comprise a 20 bit address specifying a bank, row and column address for a memory transfer or the start of a multiple bit memory transfer. In one embodiment, the 20-bit address is divided into 3 bits of bank address, 10 bits of row address, and 7 bits of column address. Although the command packet shown in FIG. 2 is composed of 4 packet words PW 1 -PW 4  each containing up to 10 bits, it will be understood that a command packet may contain a lesser or greater number of packet words, and each packet word may contain a lesser or greater number of bits. 
     The memory device  16   a  is shown in block diagram form in FIG.  3 . Each of the memory devices  16   a-c  includes a clock generator circuit  40  that receives a command clock signal CCLK and generates a large number of other clock and timing signals to control the timing of various operations in the memory device  16   a . The memory device  16   a  also includes a command buffer  46  and an address capture circuit  48  which receive an internal clock signal ICLK, a command packet CA&lt; 0 : 9 &gt; on a 10 bit command-address bus CA, and a terminal  52  receiving a FLAG signal. A memory controller (not shown) or other device normally transmits the command packet CA&lt; 0 : 9 &gt; to the memory device  16   a  in synchronism with the command clock signal CCLK. As explained above, the command packet, which generally includes four 10-bit packet words PW 1 -PW 4 , contains control and address information for each memory transfer. The FLAG signal identifies the start of a command packet, and also signals the start of an initialization sequence. The command buffer  46  receives the command packet from the command-address bus CA, and compares at least a portion of the command packet to identifying data from an ID register  56  to determine if the command packet is directed to the memory device  16   a  or some other memory device  16   b, c . If the command buffer  46  determines that the command is directed to the memory device  16   a , it then provides the command to a command decoder and sequencer  60 . The command decoder and sequencer  60  generates a large number of internal control signals to control the operation of the memory device  16   a  during a memory transfer. 
     The address capture circuit  48  also receives the command packet from the command-address bus CA and outputs a 20-bit address corresponding to the address information in the command packet. The address is provided to an address sequencer  64 , which generates a corresponding 3-bit bank address on bus  66 , a 10-bit row address on bus  68 , and a 7-bit column address on bus  70 . The row and column addresses are processed by row and column address paths, as will be described in more detail below. 
     One of the problems of conventional DRAMs is their relatively low speed resulting from the time required to precharge and equilibrate circuitry in the DRAM array. The SLDRAM  16   a  shown in FIG. 3 largely avoids this problem by using a plurality of memory banks  80 , in this case eight memory banks  80   a-h . After a read from one bank  80   a , the bank  80   a  can be precharged while the remaining banks  80   b-h  are being accessed. Each of the memory banks  80   a-h  receives a row address from a respective row latch/decoder/driver  82   a-h . All of the row latch/decoder/drivers  82   a-h  receive the same row address from a predecoder  84  which, in turn, receives a row address from either a row address register  86  or a refresh counter  88  as determined by a multiplexer  90 . However, only one of the row latch/decoder/drivers  82   a-h  is active at any one time as determined by bank control logic  94  as a function of a bank address from a bank address register  96 . 
     The column address on bus  70  is applied to a column latch/decoder  100 , which supplies I/O gating signals to an I/O gating circuit  4102 . The I/O gating circuit  4102  interfaces with columns of the memory banks  80   a-h  through sense amplifiers  104 . Data is coupled to or from the memory banks  80   a-h  through the sense amps  104  and I/O gating circuit  4102  to a data path subsystem  108  which includes a read data path  110  and a write data path  112 . The read data path  110  includes a read latch  120  that stores data from the I/O gating circuit  4102 . In the memory device  16   a  shown in FIG. 3, 64 bits of data are stored in the read latch  120 . The read latch then provides four 16-bit data words to an output multiplexer  122  that sequentially supplies each of the 16-bit data words to a read FIFO buffer  124 . Successive 16-bit data words are clocked into the read FIFO buffer  124  by a clock signal RCLK generated from the internal clock signal ICLK. The 16-bit data words are then clocked out of the read FIFO buffer  124  by a clock signal obtained by coupling the RCLK signal through a programmable delay circuit  126 . The programmable delay circuit  126  is programmed during initialization of the memory device  16   a  so that the data from the memory device is received by a memory controller, processor, or other device (not shown in FIG. 3) at the proper time. The FIFO buffer  124  sequentially applies the 16-bit data words to a driver circuit  128  which, in turn, applies the 16-bit data words to a data bus DQ forming part of the processor bus  14  (see FIG.  1 ). The driver circuit  128  also applies one of two data clock signals DCLK 0  and DCLK 1  to respective data clock lines  132  and  133 . The data clocks DCLK 0  and DCLK 1  enable a device, such as the processor  12 , reading the data on the data bus DQ to be synchronized with the data. Particular bits in the command portion of the command packet CA 0 -CA 9  determine which of the two data clocks DCLK 0  and DCLK 1  is applied by the driver circuit  128 . It should be noted that the data clocks DCLK 0  and DCLK 1  are differential clock signals, each including true and complementary signals, but for ease of explanation, only one signal for each clock is illustrated and described. 
     The write data path  112  includes a receiver buffer  140  coupled to the data bus  130 . The receiver buffer  140  sequentially applies 16-bit data words from the data bus DQ to four input registers  142 , each of which is selectively enabled by a signal from a clock generator circuit  144 . The clock generator circuit  144  generates these enable signals responsive to the selected one of the data clock signals DCLK 0  and DCLK 1 . The memory controller or processor determines which data clock DCLK 0  or DCLK 1  will be utilized during a write operation using the command portion of a command packet applied to the memory device  16   a . As with the command clock signal CCLK and command packet, the memory controller or other device (not shown) normally transmits the data to the memory device  16   a  in synchronism with the selected one of the data clock signals DCLK 0  and DCLK 1 . The clock generator  144  is programmed during initialization to adjust the timing of the clock signal applied to the input registers  142  relative to the selected one of the data clock signals DCLK 0  and DCLK 1  so that the input registers  142  can capture the write data at the proper times. In response to the selected data clock DCLK 0  or DCLK 1 , the input registers  142  sequentially store four 16-bit data words and combine them into one 64-bit data word applied to a write FIFO buffer  148 . The write FIFO buffer  148  is clocked by a signal from the clock generator  144  and an internal write clock WCLK to sequentially apply 64-bit write data to a write latch and driver  150 . The write latch and driver  150  applies the 64-bit write data to one of the memory banks  80   a-h  through the I/O gating circuit  4102  and the sense amplifiers  104 . 
     As mentioned above, an important goal of the synchronous link architecture is to allow data transfer between a processor and a memory device to occur at a significantly faster rate. However, as the rate of data transfer increases, it becomes more difficult to maintain synchronization between signals transmitted to the memory device  16   a . For example, as mentioned above, the command packet CA&lt; 0 : 39 &gt; is normally transmitted to the memory device  16   a  in synchronism with the command clock signal CCLK, and the data is normally transmitted to the memory device  16   a  in synchronism with the selected one of the data clock signals DCLK 0  and DCLK 1 . However, because of unequal signal delays and other factors, the command packet CA&lt; 0 : 39 &gt; may not arrive at the memory device  16   a  in synchronism with the command clock signal CCLK, and the data may not arrive at the memory device  16   a  in synchronism with the selected data clock signal DCLK 0  or DCLK 1 . Moreover, even if these signals are actually coupled to the memory device  16   a  in synchronism with each other, they may loose synchronism once they are coupled to circuits within the memory device. For example, internal signals require time to propagate to various circuitry in the memory device  16   a , differences in the lengths of signal routes can cause differences in the times at which signals reach the circuitry, and differences in capacitive loading of signal lines can also cause differences in the times at which signals reach the circuitry. These differences in arrival times can become significant at high speeds of operation and eventually limit the operating speed of memory devices. 
     The problems associated with varying arrival times are exacerbated as timing tolerances become more restricted with higher data transfer rates. For example, if the internal clock ICLK derived from the command clock CCLK does not latch each of the packet words CA&lt; 0 : 9 &gt; comprising a command packet CA&lt; 0 : 39 &gt; at the proper time, errors in the operation of the memory device may result. Similarly, data errors may result if internal signals developed responsive to the data clocks DCLK 0  and DCLK 1  do not latch data applied on the data bus DQ at the proper time. Moreover, even if these respective clocks are initially synchronized, this synchronism may be lost over time during normal operation of the SLDRAM  16   a . Loss in synchronism may result from a variety of factors, including temperature variations in the environment in which the SLDRAM  16   a  is operating, or drift in operating parameters of components within the SLDRAM  16   a . Thus, the command clock CCLK and data clocks DCLK 0  and DCLK 1  must occasionally be resynchronized to ensure synchronism is maintained. 
     One skilled in the art will understand that when synchronization of the clock signals CCLK, DCLK 0 , and DCLK 1  is discussed, this means the adjusting of the timing of respective internal clock signals derived from these respective external clock signals so the internal clock signals can be used to latch corresponding digital signals at optimum times. For example, the command clock signal CCLK is synchronized when the timing of the internal clock signal ICLK relative to the command clock signal CCLK causes packet words CA&lt; 0 : 9 &gt; to be latched at the optimum time. 
     There is a need for maintaining synchronism between clock signals and the associated digital signals being latched responsive to such clock signals during normal operation of an SLDRAM. Moreover, although the foregoing discussion is directed to synchronizing clock signals in SLDRAMs, similar problems exist in other synchronous and asynchronous DRAMs, which must latch address, data, and control signals at increasingly high rates of speed. 
     SUMMARY OF THE INVENTION 
     According to one aspect of the present invention, the phases of a plurality of internal clock signals are adaptively adjusted where each respective internal clock signal causes a corresponding signal to be stored responsive to the respective internal clock signal. A system embodying the present invention may include a plurality of clock control circuits, each controlling the phase of a respective internal clock signal relative to a corresponding external clock signal in response to a respective phase command signal. At least one evaluation circuit is coupled to latches that are corresponding signals responsive to respective internal clock signals. Each evaluation circuit is adapted to receive a plurality of signals sequentially stored in the corresponding latch and generate a results signal indicating whether each of the signals has an expected value. A phase selector circuit operates in a storage mode to sequentially develop a plurality of phase command signals on an output and store corresponding result signals sequentially received on an input. The phase selector circuit further operates in an analysis mode to develop on the output a final phase command signal determined from the stored result signals. 
     A plurality of storage circuits are coupled to respective clock control circuits and to the output of the phase selector circuit. Each storage circuit stores the final phase command signal responsive to a corresponding clock domain signal. A clock-domain control circuit is adapted to receive a synchronization signal. When the synchronization signal is active, the clock-domain control circuit sequentially applies the result signals generated by respective evaluation circuits to the phase selector circuit and develops the clock domain signals to store the resulting final phase command signals in the corresponding storage circuits. The clock-domain control circuit further operates when the synchronization signal goes inactive before final phase command signals have been determined for each internal clock signal to, when the synchronization signal again goes active, sequentially apply result signals such that final phase command signals are determined only for those internal clock signals not synchronized during the previous cycle of the synchronization signal. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram of a conventional computer system using a plurality of SLDRAM packetized memory devices. 
     FIG. 2 is diagram showing a typical command packet received by the SLDRAMs of FIG.  1 . 
     FIG. 3 is a block diagram of a conventional packetized DRAM used in the computer system of FIG.  1 . 
     FIG. 4 is block diagram of a partial resynchronization circuit usable in each of the SLDRAMs of FIG. 3 according to one embodiment of the present invention. 
     FIG. 5 is a schematic of the clock-domain control circuit of FIG. 4 according to one embodiment of the present invention. 
     FIG. 6 is a more detailed block diagram of one embodiment of the initialization sequencer of FIG.  4 . 
     FIG. 7 is a schematic of one embodiment of the strobe generator of FIG.  6 . 
     FIG. 8 is a schematic of one embodiment of the phase compare counter of FIG.  10 . 
     FIG. 9 is a schematic of one embodiment of the compare control circuit of FIG.  6 . 
     FIG. 10 is a schematic of one embodiment of the multiplexer of FIG.  6 . 
     FIG. 11 is a schematic of one embodiment of the pattern generator clocking circuit of FIG.  6 . 
     FIG. 12 is a more detailed block diagram of an embodiment of one of the variable-phase clock generation circuits of FIG.  4 . 
     FIG. 13 is a more detailed block diagram of an embodiment of one of the evaluation circuits of FIG.  4 . 
     FIG. 14 is a more detailed block diagram of one embodiment of the compare circuit of FIG.  13 . 
     FIG. 15 is more detailed block diagram of an embodiment of the multiplexers of FIG.  4 . 
     FIG. 16 is a detailed schematic of an embodiment of one of the phase select latches of FIG.  4 . 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     FIG. 4 is a schematic block diagram of a partial resynchronization circuit  410  according to one embodiment of the present invention. Typically, the partial resynchronization circuit  410  is contained in the command buffer  46  and the clock generation circuit  40  of the SLDRAM  16   a  and synchronizes external clock signals CCLK, DCLK 0 , and DCLK 1  during an initialization mode of the SLDRAM  16   a , as will be explained in more detail below. Components and signals that were previously described with reference to FIG. 3 have been given the same designations in FIG. 4, and will not be described in further detail. 
     The partial resynchronization circuit  410  includes three variable-phase clock generation circuits  418 ,  419 , and  423 , (FIG. 4B) that generate internal clock signals ICLK, IDCLK 0 , and IDCLK 1 , respectively. The clock generation circuit  418 , which is part of the clock generation circuit  40  of FIG. 3, generates the internal command clock signal ICLK in response to the command clock signal CCLK. The phase of the internal command clock signal ICLK relative to the command clock signal CCLK is controlled by a phase command CCMDPH&lt; 0 : 3 &gt; applied to the clock generation circuit  418 . Similarly, the clock generation circuit  419  generates the internal data clock signal IDCLK 0  having a phase relative to the data clock signal DCLK 0  that is determined by a phase command DOCMDPH&lt; 0 : 3 &gt;, and the clock generation circuit  423  generates the clock signal IDCLK 1  having a phase relative to the clock signal DCLK 1  that is determined by a phase command DICMDPH&lt; 0 : 3 &gt;. During the initialization procedure, the resynchronization circuit  410  determines the optimum values for the phase commands CCMDPH&lt; 0 : 3 &gt;, DOCMDPH&lt; 0 : 3 &gt;, and DICMDPH&lt; 0 : 3 &gt;, as will be explained in more detail below. 
     The partial resynchronization circuit  410  includes command packet circuitry  411  (FIG. 4A) comprising a shift register  412  receiving command packets CA&lt; 0 : 39 &gt; applied on the command-address bus CA. The width of the command-address bus CA corresponds to the width of the shift register  412 , and the number of packet words CA&lt; 0 : 9 &gt; in the command packet CA&lt; 0 : 39 &gt; corresponds to the number of stages of the shift register  412 . In the embodiment of FIG. 4, the shift register  412  has four stages, each of which is 10 bits wide. Thus, the shift register  412  sequentially receives four 10-bit packet words CA&lt; 0 : 9 &gt;. Each of the four packet words CA&lt; 0 : 9 &gt; is shifted into the shift register  412 , and from one shift register stage to the next, responsive to each transition of the internal clock signal ICLK. The shift register  412  also latches the FLAG signal applied on the flag line  52  coincident with each packet word CA&lt; 0 : 9 &gt;. Coincident with the start of each command packet CA&lt; 0 : 39 &gt; during normal operation of the memory device  16   a , the FLAG signal transitions high for one-half of the period of the internal clock signal ICLK. The shift register  412  shifts high FLAG signal through each of the four stages of the shift register  412  responsive to each transition of the ICLK signal. During normal operation, the latched high FLAG signal is used to generate a plurality of control signals as it is shifted through stages of the shift register  412 . Once four packet words CA&lt; 0 : 9 &gt;, which correspond to a single command packet CA&lt; 0 : 39 &gt;, are shifted into the shift register  412 , the shift register generates a command trigger signal CTRIGGER. In response to the CTRIGGER signal, a storage register  414  loads the 44 bit contents of the shift register  412 . In the embodiment shown in FIG. 4 in which four 10-bit packet words C&lt; 0 : 9 &gt; and 4 FLAG bits are shifted into the shift register  412 , the storage register  414  receives and stores a 40-bit command word C&lt; 0 : 39 &gt;, and a 4 bit flag-latched word FLAT&lt; 0 : 3 &gt;. However, in the more general case, the shift register  412  has N+1 stages, each of which has a width of M bits, and the storage register  414  loads an M*N bit command word. After the storage register  414  has been loaded, it continuously outputs the 40 bit command word C&lt; 0 : 39 &gt; and 4 bit flag-latched word FLAT&lt; 0 : 3 &gt;. 
     The initialization mode of the SLDRAM  16   a  is signaled by a FLAG signal that is twice the width of the normal FLAG signal, i.e., a FLAG signal having a duration equal to the period of the ICLK signal. In response to the double-width FLAG signal, the shift register  412  activates a calibration signal CAL, causing the resynchronization circuit  410  to execute an initialization procedure to synchronize the CCLK, DCLK 0 , and DCLK 1  clock signals, as will be explained in more detail below. Thus, there will be at least two transitions of the ICLK signal during the initialization FLAG signal. During the initialization procedure, the shift register  412  once again generates the CTRIGGER signal after four packet words CA&lt; 0 : 9 &gt; are shifted into the shift register  412 . In response to the active CTRIGGER signal, the storage register  414  again loads the latched command packet CA&lt; 0 : 39 &gt; and flag latched word FLAT&lt; 0 : 3 &gt;. 
     One embodiment of the shift register  412  that may be utilized in the resynchronization circuit  410  is described in more detail in U.S. patent application Ser. No. 08/994,461 to Manning, which is incorporated herein by reference. The detailed circuitry of the shift register  412  will not be discussed in further detail since such circuitry and operation is slightly tangential to the present invention. One skilled in the art will realize, however, the shift register  412  must be capable a latching packet words CA&lt; 0 : 9 &gt; received at very high rates during operation of the resynchronization circuit  410 , and during normal operation of the memory device  16   a  containing the circuit  410 . For example, in one embodiment the command clock CCLK has a frequency of 200 MHz, requiring the shift register circuit  412  to store one packet word CA&lt; 0 : 9 &gt; every 2.5 ns (i.e., one packet word in response to each falling and rising edge of the CCLK signal). 
     The partial resynchronization circuit  410  further includes an evaluation circuit  420  receiving the command word C&lt; 0 : 39 &gt; and the flag-latched word FLAT&lt; 0 : 3 &gt; from the storage register  414 . The evaluation circuit  420  further receives an initialization strobe signal INITSTRB, enable calibration signal ENCAL, and synchronization sequence word SYNCSEQ&lt; 0 : 3 &gt; generated by an initialization sequencer  430  (FIG.  4 B), and a command initialization signal CINIT developed by a clock-domain control circuit  422 . As will be discussed in more detail below, the clock-domain control circuit  422  and initialization sequencer  430  generate a plurality of control signals to control operation of the resynchronization circuit  410 . In response to the INITSTRB, ENCAL, and CINIT signals, the evaluation circuit  420  compares each bit of the captured command word C&lt; 0 : 39 &gt; and flag-latched word FLAT&lt; 0 : 3 &gt; to expected values determined by the SYNCSEQ&lt; 0 : 3 &gt; word and generates a command initialization results signal CINITRES in response to these comparisons. When the bits of the command word C&lt; 0 : 39 &gt; and flag-latched word FLAT&lt; 0 : 3 &gt; have their expected values, the evaluation circuit  20  drives the CINITRES signal high, indicating the command packet CA&lt; 0 : 39 &gt; and latched FLAG bits were successfully captured. In contrast, when at least one of the bits in the command word C&lt; 0 : 39 &gt; or flag-latched word FLAT&lt; 0 : 3 &gt; does not have its expected value, the evaluation circuit  420  drives the CINITRES signal inactive low, indicating the command packet CA&lt; 0 : 39 &gt; and latched FLAG bits were not successfully captured. 
     The partial resynchronization circuit  410  further includes data packet circuitry  424  (FIG. 4A) that operates in a manner analogous to the command packet circuitry  411  in capturing and evaluating data packet words D&lt; 0 : 15 &gt; applied on the data bus DQ. An input buffer  426  transfers data packet words D&lt; 0 : 15 &gt; received on the data bus DQ to the input registers  142 , which latch the sequentially applied data packet words D&lt; 0 : 15 &gt; in response to a clock signal applied by a multiplexer  421 . The multiplexer  421  applies either an internal data clock signal IDCLK 0  or an internal data clock signal IDCLK 1  to the input registers  142  in response to a select clock signal SELCLK generated by the time-domain control circuit  422  (FIG.  4 B). The IDCLK 0  and IDCLK 1  clock signals are internal data clock signals generated by the variable-phase clock generation circuits  419  and  423 , respectively, in response to the respective data clocks DCLK 0  and DCLK 1 , as will be explained in more detail below. After four data packet words D&lt; 0 : 15 &gt; have been latched in the input registers  142 , the write buffer  148  (FIG. 3) latches the four data packet words D&lt; 0 : 15 &gt; comprising the data packet in response to a load signal LDCD generated by the clock generator  144  (FIG.  3 ). In the embodiment of FIG. 4, each data word D&lt; 0 : 15 &gt; includes 16 bits, which is the width of the data bus DQ. Thus, the write buffer  148  stores and outputs 64 bits of data as a data word D&lt; 1 : 60 &gt; and a data word D 0 L&lt; 3 : 0 &gt;. The data word D 0 L&lt; 3 : 0 &gt; corresponds to the four bits of data sequentially latched on the DQO line of the data bus DQ, and the data word D&lt; 1 : 60 &gt; corresponds to the other 60 bits of data latched on the lines DQ 1 -DQ 15  of the data bus DQ during the latching of the data packets. The data word D 0 L&lt; 3 : 0 &gt; is analogous to the flag-latched word FLAT&lt; 0 : 3 &gt;, and the function of both of these words will be described in more detail below. 
     An evaluation circuit  428  receives the D&lt; 1 : 60 &gt; and D 0 L&lt; 3 : 0 &gt; data words from the write buffer  148  and operates in a manner analogous to that previously described for the evaluation circuit  420  to compare these captured bits to expected data determined by the SYNCSEQ&lt; 0 : 3 &gt; word generated by the initialization sequencer  30 . The evaluation circuit  28  develops a data initialization results signal DINITRES indicating whether each of the bits in the D&lt; 1 : 60 &gt; and D 0 L&lt; 3 : 0 &gt; words have their expected values. When the bits in the captured data words D&lt; 1 : 60 &gt; and D 0 L&lt; 3 : 0 &gt; all have their expected values, the evaluation circuit  428  activates the DINITRES signal, and deactivates this signal when any of these bits does not have its expected value. The evaluation circuit  428  receives the INITSTRB and ENCAL signals and SYNCSEQ&lt; 0 : 3 &gt; word from the initialization sequencer  430 , and also receives an enable signal {overscore (ENABLE)} generated by a NOR gate  32  in response to D 0 INIT and D 1 INIT signals generated by the clock-domain control circuit  422 . When either the D 0 INIT or D 1 INIT signals are active high, the NOR gate  432  drives the {overscore (ENABLE)} signal active low, which, in turn, activates the evaluation circuit  428 . 
     A multiplexer  446  receives the CINITRES or DINITRES signals output by the evaluation circuits  420  and  428 , respectively, and the CTRIGGER and LDCD signals. In response to the CINIT signal, the multiplexer  446  applies one of the CINITRES and DINITRES signals on a first output and one of the CTRIGGER or LDCD signals on a second output. When the CINIT signal is active high, the multiplexer  446  applies the CINITRES and CTRIGGER signals on its first and second outputs, respectively, if the CINIT signal is inactive low, the multiplexer  446  applies the DINITRES and LDCD signals on its respective first and second outputs. 
     An initialization phase selector  436  receives either the CINITRES or DINITRES signal output by the multiplexer  446 . The initialization phase selector  436  further receives the CAL signal, a latch results signal LATRES, and a phase signal PHASEOK generated by the initialization sequencer  30 . A multiplexer  438  applies either the ICLK signal generated by the variable-phase clock generation circuit  418  or the WCLK signal generated by the clock generator  40  (see FIG. 3) to clock the initialization phase selector  436 . The multiplexer  438  applies the ICLK signal to clock the initialization phase selector  436  when the CINIT signal is active high, and applies the WCLK signal when the CINIT signal is inactive low. 
     In response to these various signals, the initialization phase selector  436  develops an initialization phase word INITPH&lt; 0 : 3 &gt;, a phase select done signal PHSELDONE, and a phase ready signal PHREADY, which are applied to a number of components in the partial resynchronization circuit  410  as shown. This initialization phase word INITPH&lt; 0 : 3 &gt; is applied to the inputs of three phase select latches  440 ,  442 , and  444  receiving the CINIT, D 0 INIT, and D 1 INIT signals, respectively. Each of the phase select latches  440 - 444  operates in either a transfer mode or a storage mode in response to the corresponding one of the CINIT, D 0 INIT, and D 1 INIT signals output by the clock-domain control circuit  422 . The phase select latches  440 - 444  each operate in the same way in response to the corresponding signals, and thus, for the sake of brevity, only the operation of the phase select latch  440  will now be described in more detail. The phase select latch  440  operates in the transfer mode when the CINIT signal is active high. In the transfer mode, the phase select latch  440  outputs the current value of the INITPH&lt; 0 : 3 &gt; word as the phase command CCMDPH&lt; 0 : 3 &gt; to the variable-phase clock generation circuit  418 , and latches the INITPH&lt; 0 : 3 &gt; word present on its input in response to the PHSELDONE signal going active high. When the CINIT signal goes inactive low, the phase select latch  440  operates in the storage mode, outputting the latched value of INITPH&lt; 0 : 3 &gt; word as the phase command CCMDPH&lt; 0 : 3 &gt; to the clock generation circuit  418 . 
     The operation of the initialization phase selector  436  in determining the optimum phase command CCMDPH&lt; 0 : 3 &gt;, D 0 CMDPH&lt; 0 : 3 &gt;, or D 1 CMDPH&lt; 0 : 3 &gt; for the one of the clock signals CCLK, DCLK 0 , and DCLK 1  being synchronized by the resynchronization circuit  410  will now be described in more detail before describing the overall operation of the resynchronization circuit  410 . One procedure that may be executed by the initialization phase selector  436  in determining each of these optimum phase commands is described in U.S. patent application Ser. No. 08/994,461 to Manning, which is incorporated herein by reference. 
     Briefly, according to this procedure, the initialization phase selector  436  operates in two modes in determining each optimum phase command, namely a load mode and an analysis mode. In the load mode, the initialization phase selector  436  sequentially increments the initialization phase word INITPH&lt; 0 : 3 &gt; to sequentially increment the phase of the one of the clock signals ICLK, D 0 CLK, or D 1 CLK being synchronized. For example, assume the CINIT signal is active high indicating the CCLK clock signal is being synchronized. When the CINIT signal is high, the phase select latch  440  applies INITPH&lt; 0 : 3 &gt; word as the phase command CCMDPH&lt; 0 : 3 &gt; to the clock generator  418 . In this situation, as the initialization phase selector  436  sequentially increments the INITPH&lt; 0 : 3 &gt; word, the clock generation circuit  418  sequentially increments the phase of the ICLK signal. The shift register  412  attempts to accurately capture each initialization command packet responsive to the respective internal clock signals ICLK that sequentially vary in their timing relationship to the initialization command packets. During the load mode, the initialization phase selector  436  stores or load values for the CINITRES signal developed by the evaluation circuit  420  at corresponding phases of the ICLK signal. Recall, when a command packet is successfully captured the CINITRES signal has a binary “1” value, and otherwise is a binary “0.” The initialization phase selector  436  stores a value for the CINITRES signal at each value of the phase command CCMDPH&lt; 0 : 3 &gt;, and identifies which phase commands CMDPH&lt; 0 : 3 &gt; caused ICLK to clock the shift register  12  at the proper time to successfully capture these initialization command packets (i.e., which phase commands resulted in a binary 1 for the CINITRES signal). 
     In the analysis mode, the initialization phase selector  436  evaluates the stored values for the CINITRES signals at each value of the phase command CCMDPH&lt; 0 : 3 &gt;. More specifically, a single phase command CMDPH&lt; 0 : 3 &gt; that is most likely to be able to successfully capture packet words in an initialization command packet is selected from all the phase commands CCMDPH&lt; 0 : 3 &gt; that successfully captured the initialization command packets. This selected phase command CMDPH&lt; 0 : 3 &gt; is the command that is thereafter latched by the phase select latch  440  and applied to the clock generation circuit  418  to generate the ICLK signal during normal operation. 
     In operation, when the SLDRAM  16   a  containing the partial resynchronization circuit  410  operates in the initialization mode, which is initiated by the FLAG signal going active high for one cycle of the ICLK signal, the partial resynchronization circuit  410  synchronizes the CCLK, DCLK 0 , and DCLK 1  clock signals, as will now be explained in more detail. In synchronizing these clock signals, the partial resynchronization circuit  410  operates in two submodes, a power-up synchronization submode and a partial synchronization submode. The power-up synchronization submode is initiated by a reset signal {overscore (RESET)} going active low, which typically occurs, for example, upon power-up of the computer system  10  (see FIG. 1) including the SLDRAM  16   a . In response to the low {overscore (RESET)} signal, the clock-domain control circuit  422  drives the CINIT, D 0 INIT, D 1 INIT, and SO signals inactive low, and the memory controller (FIG. 1) applies a 15-bit repeating pseudo-random bit sequence on each line of the command-address bus CA, data bus DQ, and on line  52  receiving the FLAG signal. The 15-bit repeating pseudo-random synchronization bit sequence applied on these lines is shown in Table 1 below. 
     
       
         
           
               
               
               
               
               
               
               
               
               
               
               
               
               
               
               
               
             
               
                 TABLE 1 
               
               
                   
               
             
            
               
                 FLAG 
                 1 
                 1 
                 1 
                 1 
                 0 
                 1 
                 0 
                 1 
                 1 
                 0 
                 0 
                 1 
                 0 
                 0 
                 0 
               
               
                 CA&lt;9&gt; 
                 0 
                 0 
                 0 
                 0 
                 1 
                 0 
                 1 
                 0 
                 0 
                 1 
                 1 
                 0 
                 1 
                 1 
                 1 
               
               
                 CA&lt;8&gt; 
                 1 
                 1 
                 1 
                 1 
                 0 
                 1 
                 0 
                 1 
                 1 
                 0 
                 0 
                 1 
                 0 
                 0 
                 0 
               
               
                 CA&lt;7&gt; 
                 0 
                 0 
                 0 
                 0 
                 1 
                 0 
                 1 
                 0 
                 0 
                 1 
                 1 
                 0 
                 1 
                 1 
                 1 
               
               
                 M 
                 M 
                 M 
                 M 
                 M 
                 M 
                 M 
                 M 
                 M 
                 M 
                 M 
                 M 
                 M 
                 M 
                 M 
                 M 
               
               
                 CA&lt;0&gt; 
                 1 
                 1 
                 1 
                 1 
                 0 
                 1 
                 0 
                 1 
                 1 
                 0 
                 0 
                 1 
                 0 
                 0 
                 0 
               
               
                 DQ&lt;15&gt; 
                 0 
                 0 
                 0 
                 0 
                 1 
                 0 
                 1 
                 0 
                 0 
                 1 
                 1 
                 0 
                 1 
                 1 
                 1 
               
               
                 DQ&lt;14&gt; 
                 1 
                 1 
                 1 
                 1 
                 0 
                 1 
                 0 
                 1 
                 1 
                 0 
                 0 
                 1 
                 0 
                 0 
                 0 
               
               
                 M 
                 M 
                 M 
                 M 
                 M 
                 M 
                 M 
                 M 
                 M 
                 M 
                 M 
                 M 
                 M 
                 M 
                 M 
                 M 
               
               
                 DQ&lt;0&gt; 
                 1 
                 1 
                 1 
                 1 
                 0 
                 1 
                 0 
                 1 
                 1 
                 0 
                 0 
                 1 
                 0 
                 0 
                 0 
               
               
                   
               
            
           
         
       
     
     As seen from Table 1, the 15-bit pseudo-random bit sequence is complemented on adjacent lines of the command-address bus CA and data bus DQ. Thus, for example, the sequence starts with 0000 on line CA&lt; 9 &gt;, 1111 on CA&lt; 8 &gt;, 0000 on CA&lt; 7 &gt;, and so on such that the sequence applied on each line is the complement of the sequence applied on adjacent lines. 
     In response to the 15-bit pseudo-random bit sequence, the partial resynchronization circuit  410  places the SLDRAM  16   a  in the synchronization mode of operation. More specifically, as shown in Table 1,the pseudo-random bit sequence begins with consecutive 1&#39;s for the FLAG signal. As previously described, in response to two consecutive 1&#39;s latched for the FLAG signal, the shift register  12  activates the CAL signal to place the partial resynchronization circuit  410  in the initialization mode of operation. 
     When the CAL signal goes active high, the clock-domain control circuit  422  initially activates the CINIT signal and maintains the SO, D 0 INIT, and D 1 INIT signals inactive low. In response to the CINIT signal going active high, the multiplexer  446  applies the CINITRES signal to the initialization phase selector  436  and the CTRIGGER signal to the initialization sequencer  430 . In addition, in response to the active high CINIT signal, the phase select latch  440  applies the initialization phase word INITPH&lt; 0 : 3 &gt; output by the initialization phase selector  436  as the phase command CCMDPH&lt; 0 : 3 &gt; to the variable-phase clock generation circuit  418 . The multiplexer  38  applies the ICLK signal to clock the initialization phase selector  436  in response to the active CINIT signal. 
     When the CINIT signal is active, the partial resynchronization circuit  410  synchronizes the ICLK signal. To begin synchronizing the ICLK signal, the initialization phase selector  436  outputs an initialization phase word INITPH&lt; 0 : 3 &gt; through the phase select latch  440  as the phase command CCMDPH&lt; 0 : 3 &gt; to the variable-phase clock generation circuit  418 . In response to the phase command CCMDPH&lt; 0 : 3 &gt;, the clock generation circuit  418  generates the ICLK signal having an initial phase relative to the CCLK signal that corresponds to the phase command CCMDPH&lt; 0 : 3 &gt;. The shift register  412  then latches four packet words CA&lt; 0 : 9 &gt; applied on the command-address bus CA in response to the ICLK signal. After four packet words CA&lt; 0 : 9 &gt; have been latched, the shift register  412  outputs the latched command word C&lt; 0 : 39 &gt; along with the flag-latched word FLAT&lt; 0 : 3 &gt; to the storage register  414  and generates the CTRIGGER pulse. In response to the CTRIGGER pulse, the storage register  414  latches and outputs the command word C&lt; 0 : 39 &gt; and flag-latched word FLAT&lt; 0 : 3 &gt;. The evaluation circuit  420  receives the latched C&lt; 0 : 39 &gt; and FLAT&lt; 0 : 3 &gt; words, and compares these words to expected values determined by the SYNCSEQ&lt; 0 : 3 &gt; word from the initialization sequencer  430 . The initialization sequencer  430  generates the SYNCSEQ&lt; 0 : 3 &gt; word in response to the FLAT&lt; 0 : 3 &gt; word, as will be described in more detail below. The evaluation circuit  420  compares the latched command word C&lt; 0 : 39 &gt; and flag-latched word FLAT&lt; 0 : 3 &gt; to their expected values determined by the SYNCSEQ&lt; 0 : 3 &gt; word and activates the CINITRES signal when these words have their expected values. If any of the bits in the C&lt; 0 : 39 &gt; and FLAT&lt; 0 : 3 &gt; words does not have its expected value, the evaluation circuit  420  drives the CINITRES signal inactive, indicating the capture of these words at the current phase of the ICLK signal was unsuccessful. 
     The CINITRES signal is applied through the multiplexer  446  to the input of the initialization phase selector  436 , which latches the value of the CINITRES signal in response to the LATRES signal developed by the initialization sequencer  430 . In the embodiment of FIG. 4, the initialization sequencer  430  pulses the LATRES signal once for every eight comparisons made by the evaluation circuit  420  as long as the CINITRES signal is active high. In this way, for a given phase of the ICLK signal, eight command packets CA&lt; 0 : 39 &gt; may be latched and subsequently compared by the evaluation circuit  420  to their corresponding expected values as long as the CINITRES signal remains active high. After the eighth comparison, the initialization sequencer  430  pulses the LATRES signal causing the initialization phase selector  436  to latch the CINITRES signal. 
     If any command packet CA&lt; 0 : 39 &gt; or flag-latched word FLAT&lt; 0 : 3 &gt; is latched unsuccessfully, however, the evaluation circuit  20  detects the error and drives the CINITRES signal inactive low. As soon as the CINITRES signal goes inactive low, the initialization sequencer  430  pulses the LATRES signal causing the initialization phase selector  436  to latch the low CINITRES signal. Thus, if all command packets are captured successfully, eight command packets will be captured at a given phase of the ICLK signal and a high CINITRES signal, indicating successful capture of the command packets, will be stored by the initialization phase selector  436 . In contrast, if any one of the comparisons by the evaluation circuit  420  indicates the command packet was captured unsuccessfully, which is indicated by the CINITRES signal going low, comparisons at that phase of the ICLK signal are immediately terminated and the initialization phase selector  436  stores a low value for the CINITRES signal, indicating command packets were unsuccessfully captured at that particular phase of the ICLK signal. 
     As previously described, the initialization phase selector  436  latches the value of the CINITRES signal in response to the LATRES pulse. In addition, the initialization phase selector  436  also increments the value of the initialization phase word INITPH&lt; 0 : 3 &gt; in response to the pulsed LATRES signal. This new value of the INITPH&lt; 0 : 3 &gt; word is once again applied through the phase select latch  440  to the clock generation circuit  18  and corresponds to the new phase of the ICLK signal that is applied to the shift register  412  and used in latching packet words CA&lt; 0 : 9 &gt; applied on the command-address bus CA. Once again, the latched command packet CA&lt; 0 : 39 &gt; is applied to the evaluation circuit  420 , which compares each bit of the latched command packet to an expected value determined by the SYNCSEQ&lt; 0 : 3 &gt; word. In response to this comparison, the evaluation circuit  20  once again develops the CINITRES signal having a value indicating whether the command packet CA&lt; 0 : 39 &gt; was successfully captured. The initialization phase selector  436  operates as previously described in latching a value for the CINITRES signal indicating whether command packets were successfully captured at the new phase of the ICLK signal. After latching a value for the CINITRES signal, the initialization phase selector  436  again increments the value of the INITPH&lt; 0 : 3 &gt; word which, once again, is applied through the phase select latch  440  as the phase command CCMDPH&lt; 0 : 3 &gt; to the clock generation circuit  418  which, in turn, generates the ICLK signal having a new phase relative to the ICLK signal. This process is repeated until the initialization phase selector  436  has stored a predetermined number of values for the CINITRES signal, each value corresponding to a different phase of the ICLK signal that was utilized in latching command packets CA&lt; 0 : 39 &gt; supplied on the command-address bus CA. In one embodiment, the initialization phase selector  436  latches 16 values of the CINITRES signal. In other words, 16 different phases of the ICLK signal are utilized to capture command packets CA&lt; 0 : 39 &gt; applied on the command-address bus CA. 
     After the initialization phase selector  436  has stored 16 values for the CINITRES signal, the selector operates in the analysis mode to determine which of the 16 phases for the ICLK signal will be utilized to capture command packets CA&lt; 0 : 39 &gt; applied to the SLDRAM  16   a  during normal operation. Recall, for each phase of the ICLK signal that successfully captured command packets CA&lt; 0 : 39 &gt;, the initialization phase selector  436  stored a binary 1 for the CINITRES signal. A binary 0 was stored for the CINITRES signal for all phases of the ICLK signal where the command packets were not successfully captured. Thus, the initialization phase selector  436  selects one of the phases for the ICLK signal that resulted in a binary 1 for the CINITRES signal. One process that may be utilized by the initialization phase selector  436  in determining the optimum phase for the ICLK signal is described in more detail in U.S. patent application Ser. No. 08/890,055 to Baker et al., which is incorporated herein by reference. After having determined the optimum phase for the ICLK signal, the initialization phase selector  436  outputs the initialization phase word INITPH&lt; 0 : 3 &gt; corresponding to this phase, and activates the PHSELDONE signal. In response to the active PHSELDONE signal, the phase select latch  440  latches the initialization phase word INITPH&lt; 0 : 3 &gt; corresponding to the optimum phase for the ICLK signal. The phase select latch  440  thereafter continuously outputs this value as the phase command word CCMDPH&lt; 0 : 3 &gt; to the clock generation circuit  418 , which generates the ICLK signal having the corresponding phase. The phase select latch  440  actually does not output the latched initialization phase word INITPH&lt; 0 : 3 &gt; until the clock-domain control circuit  422  deactivates the CINIT signal, which occurs shortly after the phase selector  436  activates the PHSELDONE signal, as will be described in more detail below. 
     In response to the active PHSELDONE signal output by the initialization phase selector  436 , the clock-domain control circuit  422  deactivates the CINIT signal, indicating an optimum phase for the ICLK signal has been determined and the synchronization of the CCLK signal is therefore completed. Coincident with deactivating the CINIT signal, the clock-domain control circuit  422  activates the D 0 INIT signal indicating the DCLK 0  signal will now be synchronized. In response to the active D 0 INIT signal, the phase select latch  442  places the initialization phase word INITPH&lt; 0 : 3 &gt; output by the initialization phase selector  436  on its output as the phase command D 0 CMDPH&lt; 0 : 3 &gt; to the variable-phase clock generation circuit  419 . In addition, when the CINIT signal goes inactive low, the multiplexer  446  applies the DINITRES signal to the initialization phase selector  436  and the LDCD signal to clock the initialization sequencer  430 . In addition, the multiplexer  438  applies the clock signal WCLK to clock the phase selector  436  in response to the low CINIT signal. When the D 0 INIT signal is active, the SELCLK signal goes active causing the multiplexer  421  to apply the clock signal IDCLK 0  to clock the input registers  142 , and in this way the IDCLK 0  signal is utilized to capture data packets placed on the data bus DQ. The NOR gate  432  also activates the ENABLE signal in response to the active D 0 INIT signal to thereby enable the evaluation circuit  428 . 
     The initialization phase selector  436  thereafter operates as previously described to latch  16  values for the DINITRES signal developed in response to corresponding phases of the IDCLK 0  signal, and then determines the optimum value for the phase command D 0 CMDPH&lt; 0 : 3 &gt; to be applied to the variable-phase clock generation circuit  419 . Once again, after the initialization phase selector  436  has determined the optimum value for the D 0 CMDPH&lt; 0 : 3 &gt; word, the selector again generates the PHSELDONE pulse. In response to the PHSELDONE pulse, clock-domain control circuit  422  deactivates the D 0 INIT signal and activates the D 1 INIT signal, indicating synchronization of the IDCLK 0  signal has been completed and synchronization of the IDCLKl signal will now begin. It should be noted that the NOR gate  432  maintains the {overscore (ENABLE)} signal applied to the evaluation circuit  428  active in response to the active high D 1 INIT signal. The evaluation circuit  428  and initialization phase selector  436  thereafter operate identically to the manner previously described for synchronization of the IDCLK 0  signal in determining the optimum phase command D 1 CMDPH&lt; 0 : 3 &gt; to be applied to the variable phase clock generation circuit  423  and thus, will not be described in further detail. 
     Once the initialization phase selector  436  has determined the optimum phase command D 1 CMDPH&lt; 0 : 3 &gt; to synchronize the IDCLK 1  signal, the selector once again generates the PHSELDONE pulse. In response to the PHSELDONE pulse, the clock-domain control circuit  422  deactivates the D 1 INIT signal and activates the SO signal, indicating all three clock signals, ICLK, IDCLK 0 , and IDCLK 1 , have now been synchronized. The active high SO signal is typically applied as the SI signal to another SLDRAM and enables initialization and synchronization of the next SLDRAM to begin. 
     During the power-up submode of operation, the resynchronization circuit  410  synchronizes all three of the clock signals ICLK, IDCLK 0 , and IDCLK 1 . After this has been done, the clock-domain control circuit  422  operates in the partial synchronization submode. In the partial synchronization submode, the resynchronization circuit  410  synchronizes only those clock signals not synchronized during the previous active cycle of the CAL signal. The resynchronization circuit  410  enters the partial synchronization submode when the shift register  412  activates the CAL signal in response to the FLAG signal going high for one period of the ICLK signal. During the partial synchronization submode, the clock-domain control circuit  422  develops the CINIT, D 0 INIT, and D 1 INIT signals so that the clock signals ICLK, DCLK 0 , and DCLK 1  may be partially synchronized during a single active cycle of the CAL signal, meaning less than all the clock signals may be synchronized during a given synchronization cycle, and only those clock signals not synchronized during the previous active cycle of the CAL signal are then synchronized during a subsequent synchronization cycle or cycles. 
     For example, assume the CAL signal goes active and the resynchronization circuit  410  begins synchronizing the clock signals ICLK, IDCLK 0 , and IDCLK 1 . Now assume that the CAL signal goes inactive low after the circuit  410  has synchronized the ICLK signal (i.e., after new phase command CCMDPH&lt; 0 : 3 &gt; for the ICLK signal has been determined), but before the DCLK 0  signal has been synchronized (i.e., before the phase command D 0 CMDPH&lt; 0 : 3 &gt; has been determined). The next time the CAL signal goes active, placing the circuit  410  in the partial synchronization submode, the clock-domain control circuit  422  activates the D 0 INIT signal so that synchronization begins with the IDCLK 0  signal. In other words, the ICLK signal is not again synchronized since it was successfully synchronized during the previous cycle. 
     This process continues during active cycles of the CAL signal until all three clock signals ICLK, IDCLK 0 , and IDCLK 1  have been synchronized. At this point, during the next active cycle of the CAL signal, the ICLK signal is again synchronized. The operation of the resynchronization circuit  410  in both the power-up and partial synchronization submodes will be discussed further below when the clock-domain control circuit  422  is described in more detail. 
     The overall operation of the partial resynchronization circuit  410  and general operation of several components within that circuit have now been described with reference to FIG.  4 . At this point, several components of the partial resynchronization circuit  410  will now be described in more detail, along with exemplary embodiments of these components. 
     FIG. 5 is a schematic of the clock-domain control circuit  422  according to one embodiment of the present invention. As previously described, the clock-domain control circuit  422  sequentially activates the CINIT, D 0 INIT, and D 1 INIT signals in response to a number of signals to control synchronization of the three clock domains defined by the clock signals CCLK, DCLK 0 , and DCLK 1 , as will now be explained in more detail. The clock-domain control circuit  422  includes a NOR gate  2000  having its output coupled through series connected inverters  2002  and  2004  to develop the CINIT signal. The CAL signal is applied through an inverter  206  to a first input of the NOR gate  2000 , and a register  2008  applies its output to a second input of the NOR gate  2000 . When the CAL signal is active high and the output of the register  2008  is low, the NOR gate  2000  drives its output high which, in turn, drives the CINIT signal active high. The clock-domain control circuit  422  further includes registers  2010  and  2012 , with the registers  2008 - 2012  having their inputs and outputs coupled in series between a supply voltage source V cc  and an input of an inverter  2018 . 
     A NAND gate  2022  has its output coupled through an inverter  2023  to develop the D 0 INIT signal. The NAND gate  2022  receives the output of the register  2008  on a first input, the CAL signal on a second input, the output of a NAND gate  2014  on a third input, and the output of the register  2012  coupled through the inverter  2018  on a fourth input. If all these inputs are high, the NAND gate  2022  drives its output low and the inverter  2023 , in turn, drives the D 0 INIT signal active high. The NAND gate  2014  has its output coupled through an inverter  2016  to develop the D 1 INIT signal in response to the output of the inverter  2018 , the CAL signal, and the output of the register  2010  applied on respective inputs. When all these inputs are high, the NAND gate  2014  drives its output low causing the inverter  2016  to drive the D 1 INIT signal active high. 
     A pulse generator  2024  applies its output directly and through an inverter  2026  to clock the registers  2008 - 2012 . The pulse generator  2024  receives the PHSELDONE signal on its input and generates a positive pulse of a fixed duration on its output in response to the falling-edge transition of the PHSELDONE signal. Recall, the PHSELDONE signal is generated by the initialization phase selector  436  (FIG. 4) whenever the phase selector has determined the optimum phase for the clock domain currently being synchronized. The registers  2008 - 2012  are reset in response to an output of a positive-edge delay circuit  2032 . The registers  2008 - 2012  are conventional registers that drive their outputs low in response to the signals on their reset terminals going active low, and circuitry for implementing the function of these registers is well understood by those skilled in the art. A NAND gate  2028  applies its output through an inverter  2030  to the input of the positive-edge delay circuit  2032 . The positive-edge delay circuit  2032  drives its output high a predetermined time after a positive edge transition on the output of the inverter  2030 , and drives its output low without such a delay in response to a falling-edge transition on the output of the inverter  2030 . The NAND gate  2028  receives three inputs and whenever one or more of these inputs goes inactive low the NAND gate  2028  drives its output high resetting the registers  2008 - 2012 . The positive-edge delay circuit  2032  ensures that the reset signal applied to the registers  2008 - 2012  stays active low for at least its delay time, even if the output of the NAND gate  2028  remains high for a shorter duration. 
     A NAND gate  2034  applies its output to one input of the NAND gate  2028 , and receives the inverted CAL signal from the inverter  2006  on a first input and the output of the register  2012  on a second input. When the CAL signal is inactive low and the output of the register  2012  is high the NAND gate  2034  applies a low output to the NAND gate  2028  which, in turn, drives its output high resetting the registers  2008 - 2010 . A NOR gate  2036  applies its output through an inverter  2038  to a second input of the NAND gate  2028 . The NOR gate  2036  receives the CAL signal on a first input and a never calibrated signal {overscore (NEVCAL)} on a second input. The {overscore (NEVCAL)} signal is generated by an RS flip-flop  2004  including cross-coupled NAND gates  2042  and  2044 . When both the CAL and {overscore (NEVCAL)} signals are low, the NOR gate  2036  drives its output high causing the inverter  2038  to apply a low signal to the NAND gate  2028  which, in turn, drives its output high resetting the registers  2008 - 2012 . A NAND gate  2046  applies its output to an inverter  2048  which, in turn, applies an internal reset signal {overscore (IRESET)} to the final input of the NAND gate  2028 . The NAND gate  2046  receives a reset signal {overscore (RESET)} and power up signal {overscore (PWRUP)} on respective inputs, and drives its output high when either of the signals goes active low. In response to the output of the NAND gate  2046  going high, the inverter  2048  drives the {overscore (IRESET)} signal active low causing the NAND gate  2028  to drive its output high, resetting the registers  2008 - 2012 . 
     The clock-domain control circuit  422  further includes an inverter  2050  that develops the select output signal SO in response to the output from a NAND gate  2052 . As mentioned above, the SO signal goes active high once all three clock domains CCLK, DCLK 0 , and DCLK 1  have been successfully synchronized. The NAND gate  2052  receives the {overscore (NEVCAL)} signal on a first input, a select input signal SI on a second input, and the output from a NAND gate  2054  on a third input. When all of its inputs are high, the NAND gate  2052  applies a low output to the inverter  2050  which, in turn, activates the SO signal. The RS flip-flop  2040  develops the {overscore (NEVCAL)} signal in response to an output of a NAND gate  2056  applied on its set input and the {overscore (IRESET)} signal from the inverter  2048  applied on its reset input. When the {overscore (IRESET)} signal goes active low, which occurs when either or both of the {overscore (RESET)} or {overscore (PWRUP)} signals applied to the NAND gate  2046  go active low, the RS flip-flop  2040  latches the {overscore (NEVCAL)} signal active low. Conversely, the RS flip-flop  2040  latches the {overscore (NEVCAL)} signal inactive high to enable the NAND gate  2052  when the NAND gate  2056  drives its output low, which occurs when both the output of the register  2012  and the SI signal are high. 
     The NAND gate  2054  drives its output high, enabling the NAND gate  2052  when either of respective outputs from NAND gates  2058  and  2060  is low. The NAND gate  2058  is enabled by the CAL signal, and receives a current calibration done signal {overscore (CCD)} from an RS flip-flop  2062  including cross-coupled NAND gates  2064  and  2066 . The RS flip-flop  2062  receives a set input from the NAND gate  2056 , the {overscore (IRESET)} signal on a first reset input, and a second reset input from a pulse generator  2068  and applied through an inverter  2070 . The CAL signal is applied through an inverter  2072  to the input of the pulse generator  2068 , which generates a positive pulse having a fixed duration in response to a falling-edge transition on the output of the inverter  2072 . In operation, the RS flip-flop  2062  is reset, latching the CCD signal inactive low when either the CAL signal goes active high or the {overscore (IRESET)} signal goes active low. The RS flip-flop  2062  latches the CCD signal active high when the output of the NAND gate  2056  goes low. 
     The NAND gate  2060  receives the CAL signal applied through the inverter  2006  and the output of an RS flip-flop  2074  including cross-coupled NAND gates  2076  and  2078 . An identification valid signal IDVALID is applied through an inverter  2080  to the set input of the RS flip-flop  2074 , and the inverter  2048  applies the reset input to the RS flip-flop  2074 . When the {overscore (IRESET)} signal goes active low, the RS flip-flop  2074  latches its output low, and thereafter, in response to an active high IDVALID signal, the inverter  2080  outputs an active low set input causing the RS flip-flop  2074  to latch its output high. The RS flip-flop  2074  maintains its output high until reset by the {overscore (INTRES)} signal going active low, which does not occur during normal operation of the clock-domain control circuit  422 . Once the RS flip-flop  2074  has been set, this output enables the NAND gate  2060  which then drives its output low and high responsive to the CAL signal going low and high, respectively. 
     The overall operation of the clock-domain control circuit  422  will now be described in more detail. In operation, the clock-domain control circuit  422  operates in one of two modes, a reset mode and synchronization mode. The reset mode of operation is characterized by one or both of the {overscore (RESET)} and {overscore (PWRUP)} signals going active low which, in turn, drives the {overscore (IRESET)} signal active low. In addition, it is assumed that coincident with one or both of the {overscore (RESET)} and {overscore (PWRUP)} signals going active low, circuitry (not shown in FIG. 20) drives the CAL and IDVALID signals inactive low. In response to the {overscore (IRESET)} signal going low, the NAND gate  2028  drives its output high resetting the registers  2008 - 2012  such that each register drives its corresponding output low. In response to the respective low outputs from the registers  2008  and  2010 , the NAND gates  2022  and  2014  drive their respective outputs high deactivating the D 0 INIT and D 1 INIT signals. Furthermore, in response to the low CAL signal, the NOR gate  2000  drives its output low deactivating the CINIT signal. In addition, the low {overscore (IRESET)} signal resets the RS flip-flops  2040 ,  2062 , and  2074  which, in turn, disable the NAND gates  2052 ,  2058 , and  2060  respectively. At this point, the disabled NAND gate  2052  drives its output high deactivating the SO signal. In summation, during the reset mode of operation, the clock-domain control circuit  422  resets the registers  2008 - 2012  and the RS flip-flops  2040 ,  2062 ,  2074 , and also deactivates all of the CINIT, D 0 INIT, D 1 INIT, and SO signals. 
     During the synchronization mode, the clock-domain control circuit  422  sequentially activates the CINIT, D 0 INIT, and D 1 INIT signals in response to the PHSELDONE signal, and thereafter activates the SO signal once all three clock domains have been synchronized, as will now be explained in more detail. The clock-domain control circuit  422  operates in two submodes during the synchronization mode, an initial synchronization submode and a partial synchronization submode. The clock-domain control circuit  422  operates in the initial synchronization submode immediately after operation in the reset mode, and thereafter operates in the partial synchronization submode. After operating in the reset mode, the clock-domain control circuit  422  enters the initial synchronization submode in response to circuitry (not shown in FIG. 20) in the SLDRAM  16   a  (FIG. 3) activating the CAL, SI and IDVALID signals. The high IDVALID signal sets the RS flip-flop  2074 , enabling the NAND gate  2060 . The high SI signal enables the NAND gate  2056  and also enables the NAND gate  2052  to operate responsive to the signals applied on its other two inputs. In response to the high CAL signal, the NOR gate  2000  drives its output high activating the CINIT signal. In addition, the high CAL signal enables a number of components within the clock-domain control circuit  422 , and also causes the pulse generator  2068  to generate a pulse that resets the RS flip-flop  2062  if that flip-flop was previously set. During the initial synchronization submode, which by definition immediately follows the reset mode, this pulse generated by the pulse generator  2068  has no effect on the RS flip-flop  2062  since that flip-flop has just been reset during the reset mode. The generation of the pulse by the pulse generator  2068  in response to the CAL signal going high will be described in more detail below with reference to the partial synchronization submode of operation. 
     At this point, the clock-domain control circuit  422  applies the active high CINIT signal to a variety of components within the partial resynchronization circuit  410  (FIG. 4) and that circuit operates as previously described to synchronize the ICLK signal. As previously described with reference to FIG. 4, once the initialization phase selector  436  determines the optimum initialization phase word INITPH&lt; 0 : 3 &gt; to synchronize the ICLK signal, the initialization phase selector  436  pulses the PHSELDONE signal. In response to the falling edge of the PHSELDONE pulse, the pulse generator  2024  generates a pulse that clocks the registers  2008 - 2012 , shifting the high signal applied on the input of the register  2008  to the output of that register. In response to the output of the register  2008  going high, the NOR gate  2000  drives its output low deactivating the CINIT signal. In addition, when the output of the register  2008  goes high, the NAND gate  2022 , whose other three inputs were already high, drives its output low activating the D 0 INIT signal. 
     In response to the D 0 INIT signal going high, the partial resynchronization circuit  410  (FIG. 4) synchronizes the IDCLK 0  signal as previously described. Once again, when the initialization phase selector  436  (FIG. 4) determines the optimum initialization phase word INITPH&lt; 0 : 3 &gt; to synchronize the IDCLK 0  signal, the phase selector generates the PHSELDONE pulse. In response to the PHSELDONE pulse, the pulse generator  2024  once again clocks the registers  2008 - 2012 , shifting the high on the input of the register  2010  to the output of that register. When the output of the register  2010  goes high, the NAND gate  2014 , whose other two inputs are already high, drives its output low activating the D 1 INIT signal. Further in response to the output of the NAND gate  2014  going low, the NAND gate  2022  drives its output high deactivating the D 0 INIT signal. At this point, the partial resynchronization circuit  410  (FIG. 4) operates as previously described to synchronize the IDCLK 1  signal and, once the signal has been synchronized, the initialization phase selector  436  (FIG. 4) applies the PHSELDONE pulse to the pulse generator  2024 . 
     In response to the PHSELDONE pulse, the pulse generator  2024  once again clocks the registers  2008 - 2012 , shifting the high on the output of the register  2010  to the output of the register  2012 . In response to the output of the register  2012  going high, which indicates all three clock domains have now been synchronized, the inverter  2018  applies a low to the NAND gate  2014  which, in turn, drives its output high deactivating the D 1 INIT signal. Further in response to the output of the register  2012  going high, the NAND gate  2056 , which now receives two high inputs, drives its output low causing the RS flip-flop  2040  to latch the {overscore (NEVCAL)} signal high and the RS flip-flop  2062  to latch the CCD signal high. In response to the CCD signal going high, the NAND gate  2058 , which now receives two high inputs, drives its output low causing the NAND gate  2054  to apply a high output to the NAND gate  2052 . At this point, all three inputs of the NAND gate  2052  are high, and the NAND gate  2052  accordingly drives its output low activating the SO signal which indicates all three clock domains have now been successfully synchronized. 
     The high output from the register  2012  also enables the NAND gate  2034  which, while the CAL signal remains active high, maintains its output high. When the CAL signal goes inactive low, the inverter  2006  drives its output high causing the NAND gate  2034  to drive its output low. In response to the output of the NAND gate  2034  going low, the NAND gate  2028  drives its output high, resetting the registers  2008 - 2012 , in anticipation of the next active cycle of the CAL signal. 
     The clock-domain control circuit  422  continues operating in the initial synchronization submode until successfully synchronizing all three clock domains during a single active cycle of the CAL signal, which may hereinafter be referred to as a synchronization cycle. During the initial synchronization submode, if the CAL signal goes inactive low before all three clock domains have been synchronized, the registers  2008 - 2012  are reset causing the clock-domain control circuit  422  to commence operation during the next active cycle of the CAL signal by again first activating the CINIT signal such that the partial resynchronization circuit  410  (FIG. 4) again starts by synchronizing the ICLK clock signal first. As a result, even if during a given active cycle of the CAL signal, both the ICLK and IDCLK 0  have been successfully synchronized, if the CAL signal then goes inactive before synchronization of the IDCLK 1  signal is complete, the clock-domain control circuit  422  nonetheless starts the next active cycle of the CAL signal by again synchronizing the ICLK signal. 
     This operation is understood by noting that the RS flip-flop  2040  latches the {overscore (NEVCAL)} signal active low until reset by a low output from the NAND gate  2056 , which occurs in response to a high output from the register  2012  indicating all three clock domains have been successfully synchronized. The {overscore (NEVCAL)} signal is applied to one input of the NOR gate  2036  and the CAL signal is applied to the other input of this NOR gate. Thus, when the CAL signal is active high, the NOR gate  2036  drives this output low, causing the inverter  2038  to apply a high signal to the NAND gate  2028 . When the CAL signal goes low before the RS flip-flop  2040  has set the {overscore (NEVCAL)} signal high, the NOR gate  2036  receives two low inputs once the CAL signal does go low. In response to these two low inputs, the NOR gate  2036  drives its output high causing the inverter  2038  to apply a low signal to the NAND gate  2028  which, in turn, drives its output high resetting the registers  2008 - 2012  as previously described. In other words, before the RS flip-flop  2040  is set to latch the {overscore (NEVCAL)} signal high, every time the CAL signal goes low, the NOR gate  2036  drives its output high which results in the registers  2008 - 2012  being reset. 
     Once all three clock domains ICLK, IDCLK 0  and IDCLK 1  have been successfully synchronized during the initial synchronization submode, the clock-domain control circuit  422  operates in the partial synchronization submode. During the partial synchronization submode, the clock-domain control circuit  422  synchronizes only those clock domains not successfully synchronized during the previous active cycle or cycles of the CAL signal. For example, during the partial synchronization submode, if the ICLK clock domain was successfully synchronized and the partial resynchronization circuit  410  (FIG. 4) was in the process of synchronizing the IDCLK 0  clock domain when the CAL signal goes inactive low, during the next active cycle of the CAL signal, the clock-domain control circuit  422  does not again synchronize the ICLK clock domain but instead starts by synchronizing the IDCLK 0  clock domain. In this way, the clock-domain control circuit  422  does not unnecessarily resynchronize clock domains synchronized during previous active cycles of the CAL signal. 
     The operation of the clock-domain control circuit  422  during the partial synchronization submode will now be described in more detail. For the following description, it is assumed that the initial synchronization submode has just synchronized the three clock signals ICLK, IDCLK 0  and IDCLK 1  during the previous active cycle of the CAL signal. At this point, when the CAL signal goes active, the clock-domain control circuit  422  commences operation in the partial synchronization submode. If the CAL signal does not go inactive low before all of the three clock signals ICLK, IDCLK 0  and IDCLK 1  have been successfully synchronized, then the operation of the clock-domain control circuit  422  is identical to that previously described during the initial synchronization submode, except that the RS flip-flop  2040  has already latched the {overscore (NEVCAL)} signal inactive high. When the CAL signal goes low before all three clock domains have been synchronized, however, the registers  2008 - 2102  are not reset so that during the next active cycle of the CAL signal, the partial resynchronization circuit  410  (FIG. 4) begins synchronizing the clock domain that was in the process of being synchronized during the previous active cycle of the CAL signal but which was not successfully synchronized during that cycle. For example, assume that the CAL signal goes active, placing the clock-domain control circuit  422  in the partial synchronization submode. Further assume that the ICLK signal has been successfully synchronized and that the partial resynchronization circuit  410  is in the process of synchronizing the IDCLK 0  signal. As previously described, when the IDCLK 0  signal is being synchronized, the clock-domain control circuit  422  activates the D 0 INIT signal and deactivates the CINIT, D 1 INIT, and SO signals. At this point, the output of the register  2008  is high while the outputs of the registers  2010  and  2012  are low. 
     Now assume that while the partial resynchronization circuit  410  (FIG. 4) is synchronizing the IDCLK 0  signal in response to the active high D 0 INIT signal, the CAL signal goes low before this synchronization is complete. In this situation, unlike the previous situations where either all three clock domains had been synchronized or the {overscore (NEVCAL)} signal was active low, the registers  2008 - 2012  are not reset in response to the low CAL signal, as will now be explained in more detail. Recall that the {overscore (NEVCAL)} signal is high, since all three clock domains were synchronized during the previous initial synchronization submode. The high {overscore (NEVCAL)} signal disables the NOR gate  2036  so that it maintains its output low when the CAL signal goes low. As a result, the inverter  2038  maintains its output high and does not, as previously described, go low causing the NAND gate  2028  to drive its output high to reset the registers  2008 - 2012 . In addition, the output of the register  2012  is at this point low, and this low output disables the NAND gate  2034 , which maintains its output high when the CAL signal goes low. Thus, during the partial synchronization submode, when the CAL signal goes low, the registers  2008 - 2012  are not reset. In addition, note that the low CAL signal is also applied to the NAND gate  2022 . In response to the low CAL signal, the NAND gate  2022  drives its output high deactivating the D 0 INIT signal which, in turn, disables synchronization of the IDCLK 0  signal currently being executed by the partial resynchronization circuit  410  (FIG.  4 ). It should be noted that the CAL signal is applied directly to the NAND gates  2022  and  2014 , and through the inverter  2006  to the NOR gate  2000 , disabling all these gates when it is low. As a result, whichever one of the CINIT, D 0 INIT, and D 1 INIT signals is active when the CAL signal goes low, the associated one of these gates deactivates that signal in response to the low CAL signal. 
     At this point, assume the CAL signal again goes high signaling the start of another synchronization cycle. The high CAL signal enables the NAND gate  2022  which, because its three other inputs are still high as they were at the end of the previous synchronization cycle, drives its output low once again activating the D 0 INIT signal. In response to the D 0 INIT signal again going active high, the partial resynchronization circuit  410  (FIG. 4) once again begins synchronizing the IDCLK 0  signal as previously described. With reference to FIG. 4, it should be noted that the initialization phase selector  436  also receives the CAL signal and resets itself in response to that signal going inactive low. Accordingly, the synchronization of the IDCLK 0  starts over at the beginning and the initialization phase selector  436  must again store 16 DINITRES signals, each corresponding to a particular phase of the IDCLK 0  signal, and thereafter select the optimum phase as previously described. In other words, if 8 of the required 16 samples of the DINITRES signal were stored when CAL went inactive low, these 8 values are discarded and the initialization phase selector  436  starts at the beginning and stores a new value for the first stored DINITRES signal. 
     The clock-domain control circuit  422  repeats this process as many times as required to synchronize all three of the clock domains ICLK, IDCLK 0  and IDCLK 1 . Once all three clock domains have been synchronized, the registers  2008 - 2012  are reset as previously described so that during the next synchronization cycle, the clock-domain control circuit  422  activates the CINIT signal to again start by synchronizing the ICLK signal. Recall, that once all three clock domains have been synchronized, the register  2016  latches its output high enabling the NAND gate  2034  so that next time the CAL signal goes low, the NAND gate  2034  drives its output low causing the NAND gate  2028  to drive its output high which, in turn, resets the registers  2008 - 2012 . 
     The partial synchronization submode of operation reduces the time required for the clock-domain control circuit  422  to synchronize all three clock domains when the synchronization cycle is interrupted before synchronization of all three domains is complete. Referring back to FIG. 1, this allows the memory controller  18  to synchronize the SLDRAMs  16   a-   16   c , each containing the partial resynchronization circuit  410 , while the computer system  10  is in operation. The memory controller  18  may initiate a synchronization cycle and thereafter, in response to, for example, a data request from the processor  12 , may then terminate the synchronization cycle, retrieve the requested data, and transfer that data to the processor  12 . Once that data transfer is complete, the memory controller  18  may once again initiate a synchronization cycle and the partial resynchronization circuits  410  in the SLDRAMs  16   a-   16   c  being synchronized thereafter synchronize only those clock domains not synchronized during the previous synchronization cycle. 
     The operation of the initialization sequencer  430  of FIG. 4 in controlling the partial resynchronization circuit  410  of FIG. 4 will now be described in more detail with reference to FIGS. 4 and 6. FIG. 6 is a more detailed functional block diagram of the initialization sequencer  430 . The initialization sequencer  430  includes an initialization strobe generator  2100  that generates a plurality of control signals in response to either the CTRIGGER or LDCD signals output by the multiplexer  446 . As previously described, the CTRIGGER pulse is generated after the four packet words CA&lt; 0 : 9 &gt; applied on the command-address bus CA have been latched and stored in the storage register  414  (FIG.  4 ), and the LDCD pulse is generated after four data packets DQ&lt; 0 : 15 &gt; applied on the data bus DQ have been latched. Furthermore, as previously described, the multiplexer  446  outputs the CTRIGGER signal when the ICLK signal is being synchronized and the LDCD pulse when either of the IDCLK 0  or IDCLK 1  signals is being synchronized. 
     A phase compare counter  2104  is clocked by the initialization strobe generator  2100  and develops a three bit phase compare count S&lt; 0 : 2 &gt; indicating the number of comparisons performed by the evaluation circuits  420 ,  428  (FIG. 4) at a given phase of the clock domain being synchronized. A compare control circuit  2106  receives the phase compare count S&lt; 0 : 2 &gt; and the one of the CINITRES or DINITRES signals corresponding to the clock domain currently being synchronized. In the following description, it is assumed to ICLK signal is being synchronized, so the CINITRES signal is applied to the compare control circuit  2106 . In response to these applied signals, the compare control circuit  2106  applies the latched results pulse LATRES to the initialization phase selector  436  (FIG.  4 ), causing the initialization phase selector  436  to latch the value of the CINITRES signal. The compare control circuit  2106  generates the LATRES pulse when either the CINITRES signal is inactive low, or the count S&lt; 0 : 2 &gt; equals 111. Thus, the compare control circuit  2106  generates the LATRES pulse after eight successful comparisons at a given phase of the clock domain being synchronized, or when the CINITRES signal indicates an unsuccessful comparison. In addition, when either the count S&lt; 0 : 2 &gt; equals 111 or the CINITRES signal goes low, the compare control circuit  2106  deactivates the ENCAL signal applied to the evaluation circuits  420  and  428  (FIG. 4) to thereby reset these evaluation circuits in anticipation of evaluating packet words CA&lt; 0 : 9 &gt; captured at the next phase of the clock domain being synchronized. The compare control circuit  2106  also outputs the phase signal PHASEOK signal to the phase compare counter  2104  and initialization strobe generator  2100 . The compare control circuit  2106  deactivates the PHASEOK signal when either the count S&lt; 0 : 2 &gt; equals 111 or the CINITRES signal goes low. In response to the PHASEOK signal going low, the phase compare counter  2104  resets the count S&lt; 0 : 2 &gt; to 000 and generates a count reset pulse {overscore (CNTREST)} indicating comparisons of packet words captured at a given phase of the clock domain being synchronized are complete. In addition, the low PHASEOK signal disables the initialization strobe generator  2100  until that signal again goes active high. 
     The initialization sequencer  430  further includes a pattern generator  2108  receiving either the flag-latched word FLAT&lt; 0 : 3 &gt; or latched word D 0 L&lt; 0 : 3 &gt; from a multiplexer  2110 , and utilizes the applied word to develop the synchronization sequence word SYNCSEQ&lt; 0 : 3 &gt;. As previously described, the SYNCSEQ&lt; 0 : 3 &gt; word is applied to the evaluation circuits  420  and  428  (FIG. 4) to determine the expect data for these circuits. The multiplexer  2110  applies the FLAT&lt; 0 : 3 &gt; word when the ICLK clock domain is being synchronized, and otherwise applies the D 0 L&lt; 0 : 3 &gt; word when either the IDCLK 0  or IDCLK 1  clock domains are being synchronized. A pattern generator clocking circuit  2112  clocks the pattern generator  2108  with a pair of complementary seed clock signals SCLK, {overscore (SCLK)}, and also applies a seed signal SEED to the pattern generator  2108 . In response to these signals, the pattern generator  2108  utilizes the FLAT&lt; 0 : 3 &gt; or D 0 L&lt; 0 : 3 &gt; word output by the multiplexer  2110  to develop the synchronization sequence word SYNCSEQ&lt; 0 : 3 &gt; which, as previously described, is applied to the evaluation circuits  420  and  428  (FIG. 4) to determine expect data for these circuits. The pattern generator clocking circuit  2112  is controlled by the initialization strobe generator  2100  and reset in response to the {overscore (CNTRESET)} signal generated by the phase compare counter  2104 . 
     The pattern generator  2108  may be a conventional pattern recognition circuit which, upon receiving the FLAT&lt; 0 : 3 &gt; or D 0 L&lt; 0 : 3 &gt; word equal to 1111, thereafter generates the predetermined sequence of values defined by the repeating 15 bit pseudo-random bit sequence applied on FLAG, CA, and DQ lines (see Table 1). In other words, the pseudo-random bit sequences starts with 1111 applied for the FLAG bit. The next four FLAG bits that are captured, one coincident with each packet word CA&lt; 0 : 9 &gt;, are 0101, followed by 1001, and so on as seen in Table 1. Thus, the pattern generator  2108  merely starts generating the expected values 0101, 1001, and so on for the SYNCSEQ&lt; 0 : 3 &gt; word after receiving the FLAT&lt; 0 : 3 &gt; or DOC&lt; 0 : 3 &gt; word equal to 1111. One skilled in the art will understand circuitry that may be utilized to develop the predetermined sequence of SYNCSEQ&lt; 0 : 3 &gt; words generated by the pattern generator  2108 , such as a state machine formed from appropriate logic circuitry. 
     FIG. 7 is a more detailed schematic of one embodiment of the initialization strobe generator  2100  of FIG.  6 . The initialization strobe generator  2100  includes a NAND gate  2200  that develops an active signal {overscore (ACTIVE)} on its output in response to either the CTRIGGER or LDCD signal applied on a first input. The PHASEOK signal enables the NAND gate  2200  when active high. A pulse generator  2202  generates a low output pulse having a predetermined duration in response to a falling-edge of the {overscore (ACTIVE)} signal. The output pulse of the pulse generator  2202  is applied through an inverter  2204  to develop a pulse trigger signal PTRIGGER. A NAND gate  2206  is enabled by an enable initialization strobe signal ENINITSTRB received on a first input, and receives the PTRIGGER signal on a second input. When enabled, the NAND gate  2206  outputs a complementary initialization strobe signal {overscore (INITSTRB)}, which is applied through an inverter  2208  to develop an initialization strobe signal INITSTRB. A pulse generator  2210  generates a negative pulse on its output in response to a falling-edge of the INITSTRB signal, and this output pulse is applied through a first inverter  2212  to develop a pulse initialization strobe signal PINITSRB and through a second inverter  2214  to develop a complementary pulse initialization strobe {overscore (PINITSTRB)}. 
     In operation, the initialization strobe generator  2100  is enabled when the PHASEOK and ENINITSTRB signals are active high. When enabled, the NAND gate  2200  drives the {overscore (ACTIVE)} signal active low in response to the CTRIGGER signal going active high. In response to the {overscore (ACTIVE)} signal going low, the pulse generator  2202  generates a low pulse on its output which is applied through the inverter  2204  to develop the PTRIGGER signal. In the embodiment of FIG. 7, the pulse generator  2202  generates a 2 nanosecond low pulse so the PTRIGGER signal is accordingly a 2 nanosecond high pulse. In response to the high PTRIGGER pulse, the NAND gate  2206  pulses its output low and thereby develops the INITSTRB, {overscore (INITSTRB)} pulses. In response to the falling-edge of the INITSTRB pulse, the pulse generator  2210  generates a 1 nanosecond low pulse on its output which is applied through the inverters  2212  and  2214  to develop the PINITSTRB, {overscore (PINITSTRB)} pulses. Note that when the PHASEOK signal is inactive low, the NAND gate  2200  is disabled, driving the {overscore (ACTIVE)} and PTRIGGER inactive high and thereby inhibiting development of the INITSTRB, {overscore (INITSTRB)} and PINITSTRB, {overscore (PINITSTRB)} signals. Similarly, when the ENINITSTRB signal is inactive low, the NAND gate  2206  is disabled preventing development of the INITSTRB, {overscore (INITSTRB)} and PINITSTRB, {overscore (PINITSTRB)} signals. 
     FIG. 8 is a more detailed schematic of the phase compare counter  2104  of FIG.  6 . The phase compare counter  2104  includes three registers  2300 - 2304  that develop the respective count bits S&lt; 0 &gt;, S&lt; 1 &gt;, and S&lt; 2 &gt;. A NOR gate  2306  has its output coupled directly and through an inverter  2308  to clock the registers  2300 - 2304  with complementary clock signals CLK, {overscore (CLK)}, which are generated in response to the {overscore (PINITSTRB)} pulse received on a first input of the NOR gate  2306 . The NOR gate  2306  is enabled by a NAND gate  2310  receiving the CAL and PHASEOK signals on respective inputs. The output of the NAND gate  2310  is further applied through an inverter  2312  which develops a count reset signal {overscore (CNTRESET)} to reset the registers  2300 - 2304  when either or both of the CAL and PHASEOK signals go inactive low. The count bits S&lt; 0 &gt;-S&lt; 2 &gt; are fed back to the inputs of the respective registers  2300 - 2304  in order to cause the counter  2104  to increment its three bit binary count as it is clocked by the clock signals CLK, {overscore (CLK)}. Accordingly, the bit S&lt; 0 &gt; is fed back through an inverter  2304  to the input of the register  2300 . An XOR gate  2316  receives the bits S&lt; 0 &gt; and S&lt; 1 &gt; on the respective inputs and applies its output to the input of the register  2302 . An XOR gate  2318  applies its output to the input of the register  2304  in response to the S&lt; 2 &gt; bit applied on a first input and the logical AND of the S&lt; 0 &gt; and S&lt; 1 &gt; bits applied to a NAND gate  2320  an output through an inverter  2322  to the second input of the XOR gate  2318 . 
     In operation, the phase compare counter  2104  operates in a conventional manner to increment the count S&lt; 0 : 2 &gt; from 000 to 111 as the registers  2300 - 2304  are clocked by the CLK, {overscore (CLK)} signals. During normal operation, the CAL and PHASEOK signals are active high, causing the NAND gate  2310  to enable the NOR gate  2306  and also causing the inverter  2312  to drive the {overscore (CNTRESET)} signal inactive high. At this point, the CLK, {overscore (CLK)} signals are generated in response to each {overscore (PINITSTRB)} pulse and thereby cause the registers  2300 - 2304  to increment the count S&lt; 0 : 2 &gt; from 000 to 111. If either the CAL or PHASEOK signals goes inactive low while the count S&lt; 0 : 2 &gt; is being developed, the NAND gate  2310  drives its output high, causing the inverter  2312  to drive the {overscore (CNTRESET)} signal active low resetting the count S&lt; 0 : 2 &gt; to 000. As previously described, the PHASEOK signal goes inactive low if a particular command or data packet was not successfully captured. Thus, the phase compare counter  2104  resets its count S&lt; 0 : 2 &gt; to 000 whenever a command or data packet is unsuccessfully captured, in anticipation of comparing 8 command or data packets captured at the next phase of the clock domain being synchronized. 
     FIG. 9 is a detailed schematic of one embodiment of the compare control circuit  2106  of FIG.  6 . In the compare control circuit  2106 , a pulse generator  2400  generates a low output pulse in response to a falling-edge transition of either the CTRIGGER or LDCD signal, depending upon which of the clock domains is being synchronized. The output of the pulse generator  2400  is applied through an inverter  2402  to a NAND gate  2404  which is enabled by the PHREADY signal developed by the initialization phase selector  436  (FIG.  4 ). The PHREADY signal is developed by the initialization phase selector  436  to allow for settling time of the clock signal being synchronized after adjusting the phase of that clock signal, as will be understood by one skilled in the art. An RS flip-flop  2406  includes cross-coupled NAND gates  2408  and  2410  and receives the output of the NAND gate  2404  on a set input. 
     A NOR gate  2412  applies the reset input to the RS flip-flop  2406  in response to the output of an AND gate  2414  applied on a first input and the output of a NAND gate  2416  applied through an inverter  2418  to a second input. The AND gate  2414  receives the PINITSTRB signal on a first input and either the CINITRES or DINITRES signal applied through an inverter  2420  on a second input. When the output of the AND gate  2414  is high, the NOR gate  2412  drives its output low resetting the RS flip-flop  2406 , which occurs when the PINITSTRB signal is high and the applied one of the CINITRES or DINITRES signals is inactive low. As previously discussed, when the applied one of the CINITRES or DINITRES signals is inactive low, a command or data packet has been unsuccessfully captured, and thus the RS flip-flop  2406  is reset in this situation. The NOR gate  2412  also drives its output low, resetting the RS flip-flop  2406 , when the inverter  2418  drives its output high, which occurs when the NAND gate  2416  drives its output low. The NAND gate  2416  receives the PTRIGGER signal on one input and the count S&lt; 0 : 2 &gt; output by the phase compare counter  2104  (FIG. 23) on their respective inputs. When the count S&lt; 0 : 2 &gt; equals 111, and the PTRIGGER signal is high, the NAND gate  2416  drives its output low causing the inverter  2418  to drive its output high and the NOR gate  2412 , in turn, to drive its output low resetting the RS flip-flop  2406 . 
     The output of the RS flip-flop  2406  is applied through series connected inverters  2422 ,  2424  to generate the PHASEOK signal. The output of the inverter  2422  is further applied directly to one input of a NAND gate  2426  and indirectly through the delay and pulse generation circuitry  2425  to a second input of the NAND gate  2426 . More specifically, the output of the inverter  2422  is input to a positive-edge delay circuit  2428  that develops a positive-edge transition on its output a predetermined time after receiving a positive-edge transition on its input. In response to a negative-edge transition on its input, the positive-edge delay circuit  2428  develops a negative-edge transition on its output without any such delay. The output of the positive-edge delay circuit  2428  is applied through an inverter  2430  to an input of a pulse generator  2432 . The pulse generator  2432  operates as do previously described pulse generators, developing a low pulse on its output in response to a falling-edge transition on its input. 
     The output of the pulse generator  2432  is applied through three series connected inverters  2434 - 2438  to develop the latched results pulse LATRES. As explained above, the initialization phase selector  436  latches the value of either the CINITRES or DINITRES signal present on its input in response to the LATRES pulse. The LATRES pulse is also applied to one input of a positive-edge delay circuit  2440  having its other input coupled to the supply voltage V cc . The positive-edge delay circuit  2440  develops a positive-edge transition on its output a predetermined time after receiving a positive-edge transition of the LATRES pulse, and develops a negative-edge transition on its output without such delay in response to a negative-edge transition of the LATRES pulse. A NAND gate  2442  is enabled by the CAL signal on a first input and receives the output of a NAND gate  2426  on a second input. The output of a NAND gate  2442  is coupled through an inverter  2444  to develop the ENCAL signal which, as described above with reference to FIG. 4, enables the evaluation circuits  420  and  428  (FIG. 4) when active high, and resets these circuits when inactive low. When the CAL signal is active high, the NAND gate  2442  drives its output low, in response to the output of the NAND gate  2426  going high, and drives its output high in response to the output of the NAND gate  2426  going low. 
     The overall operation of the compare control circuit  2106  will now be described in more detail. In the following description, it will be assumed the compare control circuit  2106  receives the CTRIGGER and CINITRES signals, corresponding to the situation when the ICLK clock domain is being synchronized, as previously described above. When the PHREADY signal is active high, the falling edge of the CTRIGGER pulse generates a low output pulse causing the NAND gate  2404  to drive its output low which, in turn, resets the RS flip-flop  2406 , thereby driving the output of the NAND gate  2408  high. In response to the high output of the NAND gate  2408 , the PHASEOK signal goes active high, and the inverter  2422  applies a low output to the NAND gate  2426  which, in turn, drives its output high. At this point, the NAND gate  2442  receives two high inputs and drives its output low causing the inverter  2444  to activate the ENCAL signal. In addition, note that the low output of the inverter  2422  does not cause the pulse generator  2432  to generate a low pulse, but instead the pulse generator  2432  drives its output high resulting in the inverter  2438  driving the LATRES signal inactive low. The low LATRES signal is applied through the positive-edge delay circuit  2440  to the NAND gate  2426  which, at this point, receives two low inputs. 
     After the RS flip-flop  2406  has been set in response to the falling-edge of the CTRIGGER signal, the compare control circuit  2106  maintains the PHASEOK and ENCAL signals active high, and the LATRES signal inactive low. The compare control circuit  2106  maintains these signal values until one of two events resets the RS flip-flop  2406 . The RS flip-flop  2406  is reset when the NOR gate  2412  drives its output low, which occurs when either the AND gate  2414  drives its output high or the NAND gate  2416  drives its output low. The AND gate  2414  drives its output high when the PINITSTRB signal is high and the CINITRES signal is low. As previously described, the CINITRES signal is low when the evaluation circuit  420  (FIG. 4) determines the bits in the captured command packet do not match their expected data, meaning the command packet was unsuccessfully captured. Thus, when a command packet is unsuccessfully captured, the resulting low CINITRES signal causes the AND gate  2414  to drive its output high, and the NOR gate  2412 , in turn, to drive its output low resetting the RS flip-flop  2406 . 
     When the RS flip-flop  2406  is reset, the NAND gate  2408  drives its output low causing the inverter  2424  to drive the PHASEOK signal inactive low. In response to the low output from the NAND gate  2408 , the inverter  2422  applies a high input to the NAND gate  2426 . At this point, the other input of the NAND gate  2426  remains low and thus the NAND gate  2422  maintains its output low causing the inverter  2444  to maintain the ENCAL signal active high. When the output of the inverter  2422  goes high, the positive-edge delay circuit  2428  drives its output high after the predetermined delay time, which in one embodiment of a compare control circuit  2106  is 2 nanoseconds. In response to the output of the positive-edge delay circuit  2428  going high, the inverter  2430  drives its output low causing the pulse generator  2432  to output a low pulse, which has a duration of 3 nanoseconds in one embodiment of the compare control circuit  2106 . In response to the low pulse generated by the pulse generator  2432 , the inverter  2438  drives the LATRES signal active high causing the initialization phase selector  436  (FIG. 4) to latch the value of the CINITRES signal applied on its input, as previously described. When the LATRES signal goes active high, the positive-edge delay circuit  2440  drives its output high the predetermined time later, which is 0.5 nanoseconds in one embodiment of the compare control circuit  2106 . At this point, the NAND gate  2426  receives two high inputs and drives its output low causing the NAND gate  2442  to drive its output high and the inverter  2444 , in turn, to drive the ENCAL signal inactive low. As described above, when the ENCAL signal goes inactive low, the evaluation circuit  420  is reset in anticipation of comparing the next captured command packet to the associated expect data. 
     The second condition that resets the RS flip-flop  2406  occurs when the output of the NAND gate  2416  goes low causing the inverter  2418  to drive its output high and the NOR gate  2412 , in turn, to drive its output low, resetting the RS flip-flop  2406 . The NAND gate  2416  drives its output low when the PTRIGGER signal is active high, and the compare count S&lt; 0 : 2 &gt; developed by the phase compare counter (FIG. 21) equals 111. When this occurs, all inputs to the NAND gate  2416  are high, causing it to drive its output low and thereby reset the RS flip-flop  2406 . Once reset, the compare control circuit  2106  operates as previously described to deactivate the PHASEOK and ENCAL signals and activate the LATRES signal. In sum, the PHASEOK and ENCAL signals are deactivated and the LATRES signal activated when either the compare count S&lt; 0 : 2 &gt; equals 111, or the CINITRES signal goes low. 
     FIG. 10 is a more detailed schematic of one embodiment of the multiplexer  2110  of FIG.  6 . The multiplexer  2110  includes first and second pass gates  2500  and  2502  that operate in a complementary manner to apply either the latched FLAT&lt; 0 : 3 &gt; or D 0 L&lt; 3 : 0 &gt; word as a seed word A&lt; 0 : 3 &gt; to the pattern generator  2108  (FIG.  6 ). A NAND gate  2504  has its output applied directly and through an inverter  2506  to control the pass gate  2500 , and a NAND gate  2508  has its output applied directly and through an inverter  2510  to control the pass gate  2502 . The CINIT signal is applied directly to a first input of the NAND gate  2504 , and is applied through an inverter  2512  to a first input of the NAND gate  2508 . The NAND gates  2504  and  2508  are enabled by the CAL signal applied on respective second inputs. 
     In operation, when the CAL signal is inactive low, both NAND gates  2504  and  2508  drive their respective outputs high turning off pass gates  2500  and  2502  so that neither the FLAT&lt; 0 : 3 &gt; or D 0 L&lt; 3 : 0 &gt; words are output. When the CAL signal is active high, which of the FLAT&lt; 0 : 3 &gt; D 0 L&lt; 3 : 0 &gt; words are output as the seed word A&lt; 0 : 3 &gt; depends upon the state of the CINIT signal. When the CINIT signal is active high, the NAND gate  2504  drives its output low turning ON the pass gate  2500  which, in turn, outputs the FLAT&lt; 0 : 3 &gt; word as the seed word A&lt; 0 : 3 &gt;. In response to the high CINIT signal, the inverter  2512  drives its output low causing the NAND gate  2508  to drive its output high which, in turn, turns OFF the pass gate  2502 . 
     When the CINIT signal is low, the NAND gate  2504  drives its output high turning OFF the pass gate  2500  and the NAND gate  2508  drives its output low turning ON the pass gate  2502  and thereby coupling the D 0 L&lt; 3 : 0 &gt; word to its output as the seed word A&lt; 0 : 3 &gt;. From the above description, recall that when the CINIT signal is active high, the ICLK clock domain is being synchronized, and when the CINIT signal is inactive low, either the IDCLK 0  IDCLK 1  clock domains are being synchronized. Thus, when the CINIT signal is active high during synchronization of the ICLK clock domain, the multiplexer  2110  outputs the FLAT&lt; 0 : 3 &gt; word as the seed word A&lt; 0 : 3 &gt; to the pattern generator  2108  (FIG.  6 ). If either the IDCLK 0  or IDCLK 1  clock domains are being synchronized, the multiplexer  2110  applies the D 0 L&lt; 3 : 0 &gt; word as the seed word A&lt; 0 : 3 &gt; to the pattern generator  2108 . 
     FIG. 11 is a detailed schematic of one embodiment of the pattern generator clocking circuit  2112  of FIG.  6 . The pattern generator clocking circuit  2112  includes an RS flip-flop  2600  comprising cross-coupled NAND gates  2602  and  2604  and having its output coupled through an inverter  2608  to develop the SEED signal. As previously explained, the SEED signal enables the pattern generator  2108  (FIG. 21) to store either the FLAT&lt; 0 : 3 &gt; or D 0 L&lt; 3 : 0 &gt; word output by the multiplexer  2110 . A NOR gate  2610  has its output coupled through an inverter  2612  to apply a set input to the RS flip-flop  2600 . The NOR gate  2610  has one input coupled to ground and receives the {overscore (CNTRESET)} signal on a second input. When the {overscore (CNTRESET)} signal goes active low, the NOR gate  2610  drives its output high and the inverter  2612  drives its output low, resetting the RS flip-flop  2600  which causes the NAND gate  2604  to drive its output low and the inverter  2608  to drive the SEED signal active high. A pulse generator  2614  generates a low output pulse that is applied through series connected inverters  2616  and  2618  to the reset input of the RS flip-flop  2600 . The pulse generator  2614  receives its input from a NAND gate  2620  and generates the low pulse on its output in response to a falling-edge transition on the output of the NAND gate  2620 . In response to the low pulse output by the pulse generator  2614 , the inverter  2618  drives the reset input low, resetting the RS flip-flop  2600  and thereby causing the NAND gate  2604  to drive its output high and the inverter  2608  to drive the SEED signal inactive low. In addition, note that the output of the NAND gate  2602  develops the enable initialization strobe signal ENINITSTRB which, when high, enables circuitry in the initialization strobe generator  2100  (FIG.  6 ). 
     The pattern generator clocking circuit  2112  couples the output of the NAND gate  2620  through inverters  2622  and  2624  to develop the pair of complementary seed clock signals SCLK, {overscore (SCLK)} which, as previously described above, clock the pattern generator  2108  (FIG. 6) to generate sequential SYNCSEQ&lt; 0 : 3 &gt; words as it is clocked, each of the SYNCSEQ&lt; 0 : 3 &gt; words representing expect data corresponding to a particular captured command or data packet. A pulse generator  2626  applies a low output pulse through series connected inverters  2628  and  2630  to a first input of the NAND gate  2620 . The pulse generator  2626  generates the low output pulse in response to a falling-edge transition from a NOR gate  2632 . The NOR gate  2632  has one input coupled to ground and a second input coupled to the output of an RS flip-flop  2634  including cross-coupled NAND gates  2636  and  2638 . The RS flip-flop  2634  receives the {overscore (ACTIVE)} signal on a set input and the {overscore (CNTREST)} signal on a reset input. In response to the {overscore (CNTREST)} signal going low, the RS flip-flop  2634  is reset, driving the output of the NAND gate  2636  low which, in turn, causes the NOR gate  2632  to drive its output high. Once reset, the RS flip-flop  2634  is set in response to the {overscore (ACTIVE)} signal going active low, causing the NAND gate  2636  to drive its output high which, in turn, causes the NOR gate  2632  to drive its output low. 
     The pattern generator clocking circuit  2112  further includes a NAND gate  2640  receiving the {overscore (INITSTRB)} signal on a first input and an output from a positive-edge delay circuit  2642  on a second input. The positive-edge delay circuit  2642  has its input coupled to the output of the inverter  2630  and develops a positive-edge transition on its output a predetermined time after receiving a positive-edge transition on its input, and develops a falling-edge transition on its output in response to a falling-edge transition on its input without such delay. The output of the NAND gate  2640  is applied to an input of a pulse generator  2644  which develops a low output pulse in response to a falling-edge transition on its input. A NAND gate  2646  has one input coupled to the supply voltage V cc  and a second input coupled to the output of the pulse generator  2644 . When the pulse generator  2644  develops the low pulse on its output, the NAND gate  2646  drives its output high, causing an inverter  2648  to apply a low signal on a second input of the NAND gate  2620 . In contrast, when the output of the pulse generator  2644  is high, the NAND gate  2646  drives its output low, causing the inverter  2648  to apply a high output to the NAND gate  2620 . 
     In operation, the pattern generator clocking circuit  2112  operates in two modes, a seed mode and an expect data generation mode. For the following description, assume the {overscore (CNTREST)} signal has just pulsed active low, resetting the RS flip-flop  2634  and RS flip-flop  2600 . When the RS flip-flop  2600  is reset, the NAND gate  2604  drives its output low, causing the inverter  2608  to drive the SEED signal active high. When the RS flip-flop  2634  is reset, the NAND gate  2636  drives its output low, causing the NOR gate  2632  to drive its output high. At this point, the pulse generator  2626  maintains its output high and this high output is applied through the inverters  2628  and  2630  to the NAND gate  2620 . In addition, the positive-edge delay circuit  2642  applies a high output to the NAND gate  2640  in response to the high output from the inverter  2630 . At this point, the NAND gate  2640  receives two high inputs so its output is low, but it is assumed the pulse generator  2644  has already generated its low output pulse in response to the falling-edge transition from the NAND gate  2640 . Thus, the pulse generator  2644  maintains its output high and the NAND gate  2646 , in turn, drives its output low, causing the inverter  2648  to apply a high output to the NAND gate  2620 . The NAND gate  2620  likewise also receives two high inputs at this point and accordingly drives its output low, causing the inverters  2622  and  2624  to drive the SCLK signal high and SCLK signal low, respectively. 
     The initialization strobe generator  2100  (FIG. 6) then drives the {overscore (ACTIVE)} and {overscore (INITSTRB)} signals active low. In response to the {overscore (INITSTRB)} signal going active low, the NAND gate  2640  drives its output high and the pulse generator  2644  maintains its output high in response to this positive-edge transition on its input. In response to the {overscore (ACTIVE)} signal going active low, the RS flip-flop  2634  is set, causing the NAND gate  2636  to drive its output high. In response to the high output from the NAND gate  2636 , the NOR gate  2632  drives its output low, causing the pulse generator  2626  to generate a low pulse on its output. This low pulse output by the pulse generator  2626  is applied through the inverters  2628  and  2630  to the NAND gate  2620 . In response to the low pulse from the inverter  2630 , the NAND gate  2620  drives its output high, causing the inverters  2622  and  2624  to clock the SCLK signal low and {overscore (SCLK)} high, respectively. Notice that also in response to the output of the inverter  2630  going low, the positive-edge delay circuit  2642  outputs a low to the NAND gate  2640 , which already has a high output in response to the low {overscore (INITSTRB)} signal. At this point, when the low pulse output by the pulse generator  2626  terminates, the pulse generator again drives its output high and this high output is applied through the inverters  2628  and  2630  to the input of the NAND gate  2620 . In response to the output from the inverter  2630  going high, the NAND gate  2620  again drives its output low, causing the inverters  2622  and  2624  to clock the SCLK signal high and {overscore (SCLK)} low, respectively. At this point, the pattern generator clocking circuit  2112  has generated a single SCLK, {overscore (SCLK)} clock pulse in response to the {overscore (ACTIVE)} signal setting the RS flip-flop  2634 . 
     After the RS flip-flop  2634  has been set, the initialization strobe generator  2100  (FIG. 6) drives the {overscore (INITSTRB)} signal inactive high. In response to the {overscore (INITSTRB)} signal going active high, the NAND gate  2640 , which now receives two high inputs, drives its output low. When the output of the NAND gate  2640  goes low, the pulse generator  2644  generates a low output pulse. In response to the low output pulse from the pulse generator  2644 , the NAND gate  2646  drives its output high, causing the inverter  2648  to drive its output low. At this point, the NAND gate  2620  receives a high from the inverter  2630  and a low pulse from the inverter  2648  and accordingly drives its output high in response to the low output pulse from the inverter  2648 . When the NAND gate  2620  drives its output high, the inverters  2622  and  2624  again drive the SCLK signal low and {overscore (SCLK)} high, respectively. Upon termination of the pulse generated by the pulse generator  2644 , the NAND gate  2646  again drives its output low, causing the inverter  2648  to again apply a high output to the NAND gate  2620  which, in turn, now receives two high inputs and accordingly drives its output low. In response to the low output from the NAND gate  2620 , the inverters  2622  and  2624  clock the SCLK signal high and the {overscore (SCLK)} low, respectively. 
     The pattern generator clocking circuit  2112  thereafter clocks the SCLK, {overscore (SCLK)} signals in response to pulses of the {overscore (INITSTRB)} signal. This is true because once the RS flip-flop  2634  is set by the {overscore (ACTIVE)} signal going active low, the pulse generator  2626  does not generate another pulse until the RS flip-flop  2634  is first reset by the {overscore (CNTREST)} signal and then again set by the {overscore (ACTIVE)} signal. Thus, the pulse generator  2626  generates a single pulse in response to the RS flip-flop  2634  being set. Thereafter, the NAND gate  2620  is enabled by the high output from the inverter  2630  and clocks the SCLK, {overscore (SCLK)} signals in response to each pulse generated by the pulse generator  2644 . The pulse generator  2644  generates a pulse in response to each low transition output by the NAND gate  2640 , which occurs when the low {overscore (INITSTRB)} terminates (i.e., when the {overscore (INITSTRB)} signal goes high). 
     FIG. 12 is a functional block diagram of one embodiment of the variable-phase clock generation circuit  418  of FIG.  4 . Typically, the variable-phase clock generation circuits  418 ,  419 , and  423  are identical, and thus, for the sake of brevity, only the clock generation circuit  418  will be described in more detail with reference to FIG.  12 . The variable-phase clock generation circuit  418  includes a delay-locked loop  500  that develops a plurality of clock signals  502   a-n  in response to the CCLK signal. The clock signals  502   a-n  have phase shifts, designated φ 1 -φ N , respectively, relative to the CCLK signal. In the embodiment of FIG. 12, the delay-locked loop  500  develops 16 clock signals  502   a-n  and maintains a phase shift of 180° between the clock signals  502   a  and  502   n . Thus, in this embodiment, the phases of the clock signals  502   a-n  increase in increments of 11.25° from the phase φ 1  to φ 16 . In other words, the clock signal  502   a  has a phase φ 1  relative to the CCLK signal, and each of the clock signals  502   b-n  has a phase 11.25° greater than the preceding phase such that the clock signal  502   n  has the phase φ 16  that is 180° greater than the phase φ 1 . 
     The clock signals  502   a-n  are applied to respective inputs of a multiplexer  504  that also receives the phase command word CCMDPH&lt; 0 : 3 &gt;. In response to the phase command word CCMDPH&lt; 0 : 3 &gt;, the multiplexer  504  couples one of the clock signals  502   a-n  to an output and through a buffer  506  to generate the ICCLK signal. The value of the phase command word CCMDPH&lt; 0 : 3 &gt; determines which of the clock signals  502   a-n  is used to generate the ICCLK signal and thereby determines the phase of the ICCLK signal relative to the CCLK signal. A more detailed description of one embodiment of the variable-phase clock generation circuit  418  is described in the Baker patent application that was previously referenced, and which has been incorporated herein by such reference. 
     FIG. 13 illustrates one embodiment of the evaluation circuit  420  of FIG. 4, which, as previously described, compares the command word C&lt; 0 : 39 &gt; and flag-latched word FLAT&lt; 0 : 3 &gt; to expected values determined by the SYNCSEQ&lt; 0 : 3 &gt; word, and generates the CINITRES signal having a value indicating the result of this comparison. The evaluation circuit  420  includes a PMOS reset transistor  600  coupled between a supply voltage source V cc  and a sensing node  602  and receiving an enable calibration signal ENCAL on its gate. A latch  604  including two cross-coupled inverters  606 ,  608  has its input coupled to the sensing node  602  and its output coupled to an input of an inverter  610  which develops the CINITRES signal on its output in response to the output of the latch  604 . 
     The evaluation circuit  420  further includes a compare circuit  612  coupled between the sensing node  602  and an enable node  614 . The compare circuit  612  receives the latched command word C&lt; 0 : 39 &gt; and flag-latched word FLAT&lt; 0 : 3 &gt; corresponding to the captured command packet received on the command-address bus CA and latched FLAG bits received on the flag line  52 , as previously described. In addition, the compare circuit  612  further receives a plurality of signals derived from the synchronization sequence word SYNCSEQ&lt; 0 : 3 &gt; generated by the initialization sequencer  430 . More specifically, each bit of the synchronization sequence word SYNCSEQ&lt; 0 : 3 &gt; is coupled through an inverter  616  to generate a complementary synchronization sequence word {overscore (SYNCSEQ)}&lt; 0 : 3 &gt; which, in turn, is further coupled through an inverter  618  to generate a buffered synchronization sequence word SYNCSEQBUF&lt; 0 : 3 &gt;. The {overscore (SYNCHSEQ)}&lt; 0 : 3 &gt; and SYNCHSEQBUF&lt; 0 : 3 &gt; words are utilized by the compare circuit  612  in determining whether each of the bits in the command word C&lt; 0 : 39 &gt; and latched FLAG word FLAT&lt; 0 : 3 &gt; has its expected value, as will be explained in more detail below. 
     The evaluation circuit  420  further includes an enable transistor  620  coupled between the enable node  614  and ground. An inverter  628  has its output applied through a transmission gate  622  to the gate of the enable transistor  620 . The CINIT signal is applied directly and through an inverter  624  to the control terminals of the transmission gate  622 . The output of the inverter  624  is further applied to a gate of a transistor  626  coupled between the gate of the enable transistor  620  and ground. When the CINIT signal goes active high, the inverter  624  drives its output low turning OFF the transistor  626  and turning ON the transmission gate  622  and thereby coupling the output of the inverter  628  to the gate of the enable transistor  620 . Thus, when the CINIT signal is active high, the level at the output of the inverter  628  determines whether the enable transistor  620  turns ON or OFF. A pulse generator  630  provides a pulse signal to the input of the inverter  628  in response to the INITSTRB signal applied through an inverter  632  to its input. When the INITSTRB signal goes active high, the inverter  632  drives its output low causing the pulse generator  630  to apply a low pulse signal on the input of the inverter  628 , which, in turn, drives its output high for the duration of this pulse. This high output from the inverter  628  is coupled through the transmission gate  622 , when activated, turning ON the enable transistor  622 . 
     The output of the inverter  628  is further coupled through an inverter  634  to one input of a NAND gate  636  receiving the ENCAL signal on a second input. The output of the NAND gate  636  is applied directly and through an inverter  638  to enable terminals of a buffer  640  coupled between the output of the latch  604  and the sensing node  602  as shown. When the output of the NAND gate  636  goes low, the buffer  640  is enabled and applies the inverse of the signal on the output of the latch  604  on the sensing node  602 . If the output of the NAND gate  636  is high, the buffer  640  is disabled, placing its output in a high impedance state. 
     FIG. 14 is a more detailed schematic of the compare circuit  612  of FIG. 13 including a plurality of bit compare circuits BCC 1 -BCCN. There is one bit compare circuit BCC 1 -BCCN for each bit compared by the compare circuit  612 . In the embodiment of FIG. 6, the compare circuit  612  includes  44  bit compare circuit BCC 1 -BCC 44 , one for each bit of the command word C&lt; 0 : 39 &gt; and flag-latched word FLAT&lt; 0 : 3 &gt;. All the bit compare circuits BCC 1 -BCCN are identical, and thus, for the sake of brevity, only the bit compare circuit BCC 1  will be described in more detail. The bit compare circuit BCC 1  receives the bit C&lt; 0 &gt; of the command word C&lt; 0 : 39 &gt;, and applies this bit through a first inverter  700  to an input of a first transmission gate  702 , an through the first inverter  700  and a second inverter  704  to the input of a second transmission gate  706 . The transmission gates  702  and  706  receive the {overscore (SYNCSEQ)}&lt; 0 &gt; and SYNCSEQBUF&lt; 0 &gt; signals on their respective control terminals as shown, and are activated in a complementary manner in response to the values of these signals. When the {overscore (SYNCSEQ)}&lt; 0 &gt; signal is high and SYNCSEQBUF&lt; 0 &gt; signal is low, the transmission gate  702  turns ON and transmission gate  706  turns OFF, and when the signals {overscore (SYNCSEQ)}&lt; 0 &gt; and SYNCSEQBUF&lt; 0 &gt; are low and high, respectively, the transmission gate  706  turns ON and transmission gate  702  turns OFF. The outputs of the transmission gates  702  and  706  are applied to a gate of a comparison transistor  708  coupled between the sensing node  602  and the enable node  614 . 
     In operation, the bit compare circuit BCC 1  compares the value of the bit C&lt; 0 &gt; to its expected value determined by the values of the bits {overscore (SYNCSEQ)}&lt; 0 &gt; and SYNCSEQBUF&lt; 0 &gt; and activates the compare transistor  708  when the bit C&lt; 0 &gt; does not have its expected value, as will now be explained in more detail. The initialization sequencer  430  (see FIG. 4) determines an expected value for the command bit C&lt; 0 &gt; from the latched FLAG word FLAT&lt; 0 : 3 &gt; as previously mentioned, and as will be discussed in more detail below. When the expected value of the command bit C&lt; 0 &gt; is high, the {overscore (SYNCSEQ)}&lt; 0 &gt; and SYNCSEQBUF&lt; 0 &gt; bits are driven high and low, respectively, turning ON transmission gate  702  and turning OFF transmission gate  706 . The command bit C&lt; 0 &gt; is then applied through the inverter  700  and through the turned ON transmission gate  702  to the gate of the compare transistor  708 . If the command bit C&lt; 0 &gt; is high as expected, the inverter  700  applies a low signal through the transmission gate  702  to the gate of the compare transistor  708 , turning OFF this transistor. In contrast, if the command bit C&lt; 0 &gt; is a binary 0 instead of a binary 1 as expected, the inverter  700  drives its output high and this high output is applied through the transmission gate  702  to the gate of the transistor  708 . In response to the high signal on its gate, the transistor  708  turns ON, coupling the sensing node  602  to the enable node  614 . 
     When the expected value of the command bit C&lt; 0 &gt; is a binary 0, the {overscore (SYNCSEQ)}&lt; 0 &gt; and SYNCSEQBUF&lt; 0 &gt; are driven low and high, respectively, turning ON the transmission gate  706  and turning OFF the transmission gate  702 . The command bit C&lt; 0 &gt; is then applied through the inverters  700  and  704  and through the turned ON transmission gate  706  to the gate of the compare transistor  708 . If the command bit C&lt; 0 &gt; is a binary 0 as expected, the inverter  704  drives its output low, turning OFF the transistor  708  and isolating the sensing node  602  from the enable node  614 . In contrast, if the command bit C&lt; 0 &gt; is not a binary 0 as expected but is instead a binary 1, the inverter  704  drives its output high, turning ON the transistor  708  which couples the sensing node  602  to the enable node  614 . 
     Returning now to FIG. 13, the overall operation of the evaluation circuit  420  in comparing the value of each bit in the command word C&lt; 0 : 39 &gt; and flag-latched word FLAT&lt; 0 : 3 &gt; to its expected value will now be described in more detail. When the CINIT signal is inactive low, the transmission gate  622  turns OFF and the transistor  626  turns ON. The turned ON transistor  626  couples the gate of the enable transistor to ground, turning OFF the enable transistor  620  which isolates the enable node  614  from ground. In this situation, the evaluation circuit  420  is deactivated and does not evaluate the command word C&lt; 0 : 39 &gt; and flag-latched word FLAT&lt; 0 : 3 &gt;. 
     In operation, the evaluation circuit  420  is enabled when the CINIT signal is active high turning ON the transmission gate  622  and enable transistor  620 , which couples the enable node  614  to approximately ground. The ENCAL signal goes inactive low before evaluation of a particular command word C&lt; 0 : 39 &gt; and flag-latched word FLAT&lt; 0 : 3 &gt;. In response to the low ENCAL signal, the transistor  600  turns ON, coupling the sensing node  602  to approximately the supply voltage V cc . In response to the high on the sensing node  602 , the latch  604  drives its output low and the inverter  610 , in turn, drives the CINITRES signal on its output high. At this point, the INITSTRB signal is inactive low and the pulse generator  630  drives its output high causing the inverter  628  to drive its output low. The low output from the inverter  628  is applied through the turned ON transmission gate  622  to the gate of the enable transistor  620 , turning OFF this transistor and thereby isolating the enable node  614  from ground. 
     In operation, before the evaluation circuit begins comparing latched command words C&lt; 0 : 39 &gt; and flag-latched words FLAT&lt; 0 : 3 &gt;, the ENCAL signal goes inactive low to reset the evaluation circuit  420  by turning ON the transistor  600  to drive the sensing node  602  to approximately the supply voltage V cc . In response to the high voltage on the sensing node  602 , the latch  604  drives its output low causing the inverter  610 , in turn, to drive the CINITRES signal active high. It should be noted that when the ENCAL signal goes inactive low, the NAND gate  636  deactivates the buffer  640  enabling the transistor  600  to more easily drive the sensing node  602  high. The ENCAL signal thereafter goes active high, enabling the evaluation circuit  420  to begin comparing latched command words C&lt; 0 : 39 &gt; and flag-latched words FLAT&lt; 0 : 3 &gt;. At this point, the synchronization sequence word SYNCSEQ&lt; 0 : 3 &gt; is applied to the evaluation circuit  420  and the corresponding {overscore (SYNCSEQ)}&lt; 0 : 3 &gt; and SYNCSEQBUF&lt; 0 : 3 &gt; words are, in turn, applied to the compare circuit  612 , indicating the expected value for each of the bits in the latched C&lt; 0 : 39 &gt; and FLAT&lt; 0 : 3 &gt; words. At this point, the expected data in the form of the {overscore (SYNCSEQ)}&lt; 0 : 3 &gt; and SYNCSEQBUF&lt; 0 : 3 &gt; words and the latched data in the form of the C&lt; 0 : 39 &gt; and FLAT&lt; 0 : 3 &gt; words are applied to the compare circuit  612 , but the compare circuit  612  is not yet enabled since the transistor  620  is turned OFF. The INITSTRB signal then goes active high and the pulse generator  630 , in turn, generates the low pulse on its output, causing the inverter  628  to pulse its output high and thereby turn ON the enable transistor  620  so that the compare circuit  612  compares the latched command word C&lt; 0 : 39 &gt; and flag-latched word FLAT&lt; 0 : 3 &gt; to the expected data. 
     As previously described with reference to FIG. 14, when each bit of the command word C&lt; 0 : 39 &gt; and flag-latched word FLAT&lt; 0 : 3 &gt; has its expected value, the corresponding compare transistor  708  coupled between the sensing node  602  and enable node  614  does not turn ON. Thus, when the latched command words C&lt; 0 : 39 &gt; and FLAT&lt; 0 : 3 &gt; have their expected values, none of the transistors  708  in the compare circuit  612  turns ON and the sensing node  602  remains at approximately the supply voltage V cc . Thus, when the words C&lt; 0 : 39 &gt; and FLAT&lt; 0 : 3 &gt; have their expected values, the voltage on the sensing node  602  remains high such that the latch  604  maintains its output low and the inverter  610  continues driving the CINITRES signal active high indicating the latched words C&lt; 0 : 39 &gt; and FLAT&lt; 0 : 3 &gt; were successfully captured. If any of the bits in the words C&lt; 0 : 39 &gt; and FLAT&lt; 0 : 3 &gt; does not have its expected value, the corresponding compare transistor  708  turns ON, coupling the sensing node  602  to approximately ground. When the sensing node  602  goes low, the latch  604  drives its output high causing the inverter  610  to drive the CINITRES signal low, indicating the C&lt; 0 : 39 &gt; and FLAT&lt; 0 : 3 &gt; words were not successfully captured. 
     It should be noted that the low pulse on the output of the pulse generator  630  results in the inverter  634  also pulsing its output low, which causes the NAND gate  636  to drive its output high for the duration of this pulse. As previously described, when the output of the NAND gate  636  goes high, the buffer  640  is disabled to enable the sensing node  602  to be more easily driven low if any of the bits were not successfully captured. After the end of the pulse generated by the pulse generator  630 , the NAND gate  636  again drives its output low enabling the buffer  640  to drive the sensing node  602  to its desired value. As will be understood by one skilled in the art, the sensing node  602  may present a rather large capacitance due to all the components coupled in parallel to this node, and the buffer  640  includes transistors sized such that the buffer may drive this relatively large capacitance to its desired voltage and in this way assists the inverter  606  which typically has smaller sized transistors. 
     One embodiment of the multiplexer circuit  446  of FIG. 4 is illustrated in FIG.  15 . The multiplexer  446  includes four transmission gates  802 - 808  receiving the CTRIGGER, LDCD, CINITRES, and DINITRES signals on their inputs, respectively. The CINIT signal is applied directly and through an inverter  810  to the control terminals of the transmission gates  802 - 808  as shown. In response to the CINIT signal, the transmission gates  802  and  804  operate in a complementary manner to couple either the CTRIGGER or LDCD signal through a pair of series connected inverters  812  and  814  to an output terminal  816 . Similarly, the transmission gates  806  and  808  operate in a complementary manner in response to the CINIT signal, coupling either the CINITRES or DINITRES signal through series connected inverters  818  and  820  to an output terminal  822 . In operation, when the CINIT signal is active high, the multiplexer  446  outputs the CTRIGGER and CINITRES signals on the output terminals  816  and  822 , respectively. When the CINIT signal is inactive low, the multiplexer  446  outputs the LDCD and DINITRES signals on the terminals  816  and  822 , respectively. In this way, the multiplexer  446  applies the CTRIGGER pulse to clock the initialization sequencer  430  (FIG. 4) and the CINITRES signal to the phase selector  436  (FIG. 4) when the command clock signal CCLK is being synchronized (i.e., CINIT signal is high). In contrast, the multiplexer  446  applies the LDCD and DINITRES signals to the sequencer  430  and selector  436 , respectively, when either of the data clocks DCLK 0  or DCLK 1  is being synchronized (i.e., CINIT signal is low). 
     FIG. 16 is a more detailed schematic of the phase select latch  440  of FIG.  4 . All the phase select latches  440 - 444  are identical, and thus, for the sake of brevity, only the latch  440  will be described in more detail with reference to FIG.  16 . The INITPH&lt; 0 : 3 &gt; signals are applied to respective latch circuits  1600 - 1606 . The outputs of the latch circuits  1600 - 1606  are applied to respective pass gates  1608 - 1614  which are coupled to respective inverter pairs  1616 - 1622 . The latch circuits  1600 - 1606  may be selectively bypassed by respective pass gates  1624 - 1630 . The pass gates  1608 - 1614  and the pass gates  1624 - 1630  are connected to each other so that the pass gates  1608 - 1614  are enabled alternately with the pass gates  1624 - 1630  in response to the CINIT signal applied directly and through an inverter  1638  to the control terminals of these pass gates. 
     As explained earlier, in the storage mode during synchronization of the ICLK signal, the CINIT signal high, thereby enabling the pass gates  1624 - 1630  directly. As a result, the latches  1600 - 1606  are bypassed in the storage mode so that the phase command INITPH&lt; 0 : 3 &gt; is applied to the variable-phase clock generation circuit  418  (FIG. 4) to determine the phase of the ICLK signal relative to the CCLK signal. However, once the analysis mode has determined the optimum value for the phase command INITPH&lt; 0 : 3 &gt;, the PHSELDONE signal goes active high. The PHSELDONE signal is applied to one input of a NAND gate  1644 , which is enabled by the CINIT signal. In response to the active high PHSELDONE signal, the NAND gate  1644  drive its output low, thereby triggering a pulse generator  1642 . The pulse generated by the pulse generator  1642  is applied through an inverter  1646  to S inputs of the latch circuits  1600 - 1606 , and an inverter  1647  applies the complement of this signal to the S input of the latch circuits  1600 - 1606 . The latch circuits  1600 - 1606  then store the INITPH&lt; 0 : 3 &gt; signals that correspond to the optimum phase for the ICLK signal. When the CINIT signal goes low, which occurs a short time after the PHSELDONE signal goes active high, the INITPH&lt; 0 : 3 &gt; signals stored in the latch circuits  1600 - 1606  are then coupled through the inverter pairs  1616 - 1622  by the pass gates  1608 - 1614  and output as the phase command CCMDPH&lt; 0 : 3 &gt;. The latch circuits  1600 - 1606  store the CCMDPH&lt; 0 : 3 &gt; signals until either new CCMDPH&lt; 0 : 3 &gt; signals are stored in the latch circuits  1600 - 1606  during a synchronization cycle, or they are reset by the {overscore (RESET)} signal applied to reset inputs of the latches  1600 , 1602 , and  1606 , and through an inverter  1649  to the set input of the latch  1604 . By coupling the {overscore (RESET)} signal in this way, the latches reset the stored INITPH&lt; 0 : 3 &gt; signals to 1101 when the {overscore (RESET)} signal goes active low. As previously described, the stored CCMDPH&lt; 0 : 3 &gt; is applied to the clock generator  418  (FIG. 4) to thereby set the phase of the ICLK signal to an optimum value for use in capturing command packets applied on the command-address bus CA. A variety of different circuits may be utilized to perform the functions of the latches  1600 - 1606 , and such circuits are understood by one skilled in the art. 
     It is to be understood that even though various embodiments and advantages of the present invention have been set forth in the foregoing description, the above disclosure is illustrative only, and changes may be made in detail, and yet remain within the broad principles of the invention. Therefore, the present invention is to be limited only by the appended claims.