Patent Publication Number: US-8115552-B2

Title: Amplifier circuit with step gain

Description:
TECHNICAL FIELD 
     The present invention relates to an amplifier circuit that can provide a high step gain with reduced current consumption, with little or no distortion to RF signal transmission at low gain state. 
     BACKGROUND OF THE INVENTION 
     Amplifier circuits with gains are well known in the art. See for example, U.S. Pat. Nos. 4,366,450; 5,355,096; 5,661,437; 7,046,081; 6,906,595; 7,332,964; 6,522,195; 6,977,552; 7,423,487; and USP publication 2009/0015334. Typically, the prior art amplifier circuit comprises an amplifier with a feedback circuit. The feedback circuit can be with either active elements or with passive elements. One prior art amplifier circuit with an amplifier and an active feedback circuit is shown in FIG. 9 of U.S. Pat. No. 5,661,437. The problem with this amplifier circuit is that the variable gain step is as small as 14 dB. The amplifier circuit has very low gain due to the fact that both of the high gain and low gain have negative values of −2.5 dB and −16.5 dB respectively. Another prior art amplifier circuit with an amplifier and a bias circuit with switches as the active feedback elements is shown in FIG. 1 of U.S. Pat. No. 6,977,552. In this prior art circuit, the manufacturing cost is believed to be high because there are two types of transistors used. The gain step of the amplifier circuit is also limited by the gain of the amplifier, because the RF signal is only bypassed by the switches at a low gain mode. Moreover, the output power ability and linearity are limited by the switches. 
     It is therefore desirable to have an amplifier system with a high step gain with reduced current consumption, with little or no distortion to RF signal transmission at low gain state. 
     SUMMARY OF THE INVENTION 
     Accordingly, in the present invention, an amplifier system comprises an amplifier having an input and an output, and a bias circuit. A passive feedback circuit having only passive elements connects the output to the input. A control circuit is connected to the bias circuit. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a schematic block level diagram of the amplifier system of the present invention. 
         FIG. 2  is a circuit diagram of a first embodiment of the amplifier system of the present invention. 
         FIG. 3  is a circuit diagram of a second embodiment of the amplifier system of the present invention 
         FIG. 4  is a circuit diagram of a third embodiment of the amplifier system of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Referring to  FIG. 1  there is shown a block level diagram of an amplifier system  10  of the present invention. The amplifier system  10  comprises a basic amplifier  12  having an input  14  and an output  16 . The input  14  can receive. RF signals thereby providing amplified RF signals at the output  16 . The amplifier  12  is supplied with a voltage Vcc, as well as a reference voltage Vref. In addition, the amplifier system  10  also comprises a passive feedback circuit  18 , which is connected to the output  16  at one end and to the input  14  at another end. Thus, the passive feedback circuit  18  connects the output  16  of the amplifier  12  with the input  14  of the amplifier  12 . As will be described in greater detail hereinafter, the passive feedback circuit  18  consists only of passive elements, i.e. resistors, capacitors and inductors. Finally, as will be shown the amplifier  12  has a bias circuit, and a bias node  20 . A control circuit  22  is connected to the bias node  20 . The control circuit  22  receives a control signal Vattn. 
     Referring to  FIG. 2  there is shown a circuit diagram of a first embodiment of the amplifier system  110  of the present invention. Where similar parts are described like numerals will be used. The amplifier system  110  comprises a basic amplifier  12 . The basic amplifier  12  comprises a first n-p-n bipolar transistor T 31 . However, as it will be clear to those in the art, the first n-p-n transistor T 31  need not be limited to n-p-n type (for example, it can be p-n-p) nor is it limited to bipolar (e.g. it can be an FET type transistor). Nevertheless, for explanation of the invention, reference will be made to the first transistor T 31  as being of n-p-n bipolar type. As is well known to those skilled in the art, a n-p-n type bipolar transistor, has an emitter, a collector and a base. The base of the first n-p-n transistor T 31  is connected to the RF input  14  node. The collector of the first n-p-n transistor T 31  supplies the RF output node  16 . The emitter of the first transistor T 31  is connected to ground. The collector of the first transistor T 31  is also connected to a voltage source Vcc through an inductor L 31 . In addition, the collector of the first transistor T 31  is connected to the passive feedback circuit  18 , which comprises a resistor R 31  connected in series with a capacitor C 31 , and to the input  14 . Finally, the basic amplifier  12  comprises a bias circuit  30  connected to the base of the first transistor T 31 . The bias circuit  30  comprises a second n-p-n bipolar transistor T 32 . The base of the second transistor T 32  is connected to its collector terminal as well as to the base of the first transistor T 31  through a resistor R 34 . The emitter of the second transistor T 32  is connected to ground. The collector of the second transistor T 32  is also connected the bias node  20  as well as through a resistor R 32  to a voltage source Vref Finally, the control circuit  22  of the amplifier system  110  comprises a resistor R 33 , which is connected to the bias node  20 , and receives the signal Vattn. 
     In the operation of the amplifier system  110  of the present invention, the capacitor C 31  in the passive feedback circuit  18  acts as a DC block to block DC signals. Thus, the feedback value of the amplifier system  110  is determined by the resistor R 31 . The bias circuit  30 , which consists of second transistor T 32 , resistors R 32  and R 34  acts as a current mirror to the first transistor T 31 . In the operation of the amplifier system  110 , when Vattn is at a high level, such as 2V, first transistor T 31  is turned on. The RF signal supplied at the input node  14  is amplified by first transistor T 31  with the feedback provided by the feedback circuit  18 . However, the total close-loop gain of the amplifier system  10  is still high because of the high resistance of resistor R 31 . The close loop gain of the amplifier system  10  can be calculated as:
 
 GH (Closed Loop Gain)= Go (Gain of amplifier 12)1(1+ Go/R 31))
 
     When Vattn is at a low level, such as 0 volts, and Vref maintains high voltage, the voltage of the bias node  20  become low level. The current mirror circuit or bias circuit  30  is turned off. Thus, first transistor T 31  is turned off. The RF signal provided at the input node  14  is not passed through the amplifier  12 . Instead, the RF signal is passed to the RF output node  16  through the passive feedback circuit  18 . However, since the resistance of R 31  is high, there will be a large loss for the RF signal. In addition, the first transistor T 31  is turned off, and the current mirror circuit or the bias circuit  30  is also turned off, current consumption is reduced in this low gain state. In addition, in this low gain state, because the RF signal goes through the passive elements of C 31  and R 31  there is no distortion of the RF signal. 
     As between the high gain state and the low gain state, there is a large gain difference between the two states. Thus, the amplifier system  10  is able to achieve a high gain step. 
     Referring to  FIG. 3  there is shown a second embodiment of the amplifier system  210  of the present invention. Again, same numerals will be used for like parts. The amplifier system  210  comprises a basic amplifier  12 . The basic amplifier  12  includes a bias circuit  30 , and a first transistor T 41 . Again, in this embodiment, the first transistor T 41  is shown as a n-p-n bipolar transistor. However, the invention is not so limited. The first transistor T 41  has a collector which is connected to the RF output node  16 . In addition, the collector is connected through an inductor L 41  to a voltage source Vcc. The first transistor T 41  has an emitter connected through a resistor R 48  to ground. Finally, the first transistor T 41  has a base, which is connected through a resistor R 47  to the RF input node  14 . 
     The bias circuit  30 , also functions as a current mirror circuit to the transistor T 41 , the bias circuit  30  comprises a second n-p-n bipolar transistor T 42 , and a third n-p-n bipolar transistor T 43 . The emitter of the second transistor T 42  is connected to ground. The collector of the second transistor T 42  is connected to the base of the third transistor T 43 . The base of the second transistor T 42  is connected to the emitter of the third transistor T 43  and through a resistor R 46  to resistor R 47 , and into the base of the first transistor T 41 . The collector of the third transistor T 43  is connected to Vcc. The base of the third transistor T 43  is connected through resistor R 44  and into Vref. The base of the third transistor T 43  is also connected to the control circuit  22  at the bias node  20 . 
     The control circuit  22  comprises a fourth bipolar transistor D 41 . The base of the fourth transistor  1341  is connected to its emitter which is also connected to the bias node  20 . The collector of the fourth transistor D 41  is connected through a resistor R 45  and receives the control signal Vattn. 
     The passive feedback circuit  18  comprises a first capacitor C 42  connected to a resistor R 43  in series, and in series with a resistor R 41  in series with a second capacitor C 41 . The first capacitor C 42  is also connected to the collector of the first transistor T 41 . The second capacitor C 41  is connected to the RF input node  14 . A resistor R 42  connects the junction of the resistor R 41  and R 43  to ground. 
     In the operation of the amplifier system  210  of the present invention, the connection of the resistors R 41 , R 42  and R 43  in the passive feedback circuit  18  provides better impedance matching. The resistors R 47  and R 48  provide DC ballast for the first transistor T 41 . Finally, the third transistor T 43  provides increased current mirror capability to the bias circuit  30 . 
     When the signal Vattn is high, the fourth transistor D 41  is off. The first transistor T 41  is biased to amplify. When Vattn is low, the fourth transistor D 41  is on. However, first transistor T 41  is turned off. The fourth transistor D 41  removes the influence of the bias from the control voltage, when Vattn is at a high level. 
     Referring to  FIG. 4  there is shown a third embodiment of the amplifier system  310  of the present invention. Again like parts will be designated by the same numerals. The amplifier system  310  comprises a basic amplifier  12 . The basic amplifier  12  includes a bias circuit  30 , and a first transistor T 51 . Again, in this embodiment, the first transistor T 51  is shown as a n-p-n bipolar transistor. However, the invention is not so limited. The first transistor T 51  has a collector which is connected to the RF output node  16 . In addition, the collector is connected through an inductor L 51  to a voltage source Vcc. The first transistor T 51  has an emitter connected through a resistor R 59  to ground. Finally, the first transistor T 51  has a base, which is connected through a resistor R 58  to a capacitor C 53 . 
     The bias circuit  30 , also functions as a current mirror circuit to the transistor T 51 . The bias circuit  30  comprises a second n-p-n bipolar transistor T 52 , and a third n-p-n bipolar transistor T 53 . The emitter of the second transistor T 52  is connected to ground. The collector of the second transistor T 52  is connected to the base of the third transistor T 53 . The base of the second transistor T 52  is connected to the emitter of the third transistor T 53  and through a resistor R 57  through resistor R 58 , into the base of the first transistor T 51 . The collector of the third transistor T 53  is connected to Vcc. The base of the third transistor T 53  is connected through resistor R 55  and into Vref. The base of the third transistor T 53  is also connected to the bias node  20  and into the control circuit  22 . 
     The control circuit  22  comprises a fourth bipolar transistor D 52 . The base of the fourth transistor D 52  is connected to its emitter which is also connected to the bias node  20 . The collector of the fourth transistor D 52  is connected through a resistor R 56  and receives the control signal Vattn. 
     The capacitor C 53  is also connected to the control circuit  22 . The control circuit  22  receives the RF input signal at the node  14 . The RF input signal is supplied to the collector of the fourth n-p-n bipolar transistor D 52 . In addition, the RF input signal is also supplied to the base of a fifth transistor D 51 . Finally, the RF signal at the input node  14  is connected to the passive feedback circuit  18 . The emitter of the fifth transistor D 51  is also connected to the base of the fifth transistor D 51 . The collector of the fifth transistor D 51  is connected the capacitor C 53  and is also connected to ground through transistor R 54 . 
     The passive feedback circuit  18  is similar to the feedback circuit  18  described in the second embodiment of the amplifier system  210  shown in  FIG. 3 . The feedback circuit  18  comprises a first capacitor C 52  connected to a resistor R 53  in series, and in series with a resistor R 51  in series with a second capacitor C 51 . The first capacitor C 52  is also connected to the collector of the first transistor T 51 . The second capacitor C 41  is connected to the RF input node  14 . A resistor R 52  connects the junction of the resistor R 41  and R 43  to ground. 
     In the operation of the amplifier system  310 , when Vattn is at a high level, the fifth transistor D 51  is turned on and the fourth transistor D 52  is turned off Thus, the RF signal supplied on the input node  14  is supplied to the transistor T 51 , via the low impedance of the fifth transistor D 51 , and is amplified by the first transistor T 51 . When Vattn is at low level and Vref maintains high voltage, fifth transistor D 51  is turned off, fourth transistor D 52  is turned on, and current mirror bias circuit  30  is turned off. The RF signal received at the input node  14  will be met by the high impedance of the turned off transistor D 51 . In addition first transistor T 51  will be turned off by the shunt bias. Thus, the input RF signal must pass through the passive feedback circuit  18 . Further, in this state, the fifth transistor D 51  isolates the RF input signal from the first transistor T 51 . 
     From the foregoing it can be seen, that an amplifier system with a high step gain is achieved, with low current consumption in the low gain state, and having low RF distortion at high power input in the low gain state.