Patent Publication Number: US-6661713-B1

Title: Bandgap reference circuit

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates to a circuit and a method for generating a bandgap reference voltage for integrated circuits. 
     More particularly this invention relates to providing bandgap reference voltage which is temperature, process and power supply independent. In addition, this invention relates to the ability to generate lower reference voltages which are compatible with the advances in integrated circuits. 
     2. Description of Related Art 
     FIG. 1 shows a prior art bandgap reference circuit. A differential amplifier is made up of two p-channel metal oxide semiconductor field effect transistors PMOS FETs MP 1   180  and MP 2   150 . It is also made up of the two n-channel metal oxide semiconductor FETs MN 1   170  and MN 2   160 . Finally, the differential amplifier is made up of a current source  135  which connects to the common sources of the two NMOS FETs of the differential amplifier and sinks the current from them. 
     FIG. 1 also shows a first input path that drives the first differential input Vb  165 . The first input path contains resistor R 3   120  and PN diode Q 2   130 . PN diode Q 2   130  is constructed from a PNP bipolar junction transistor, BJT, Q 2   130 . The BJT  130  has its base and collector tied in common to ground  140 . The emitter of Q 2   130  is tied to the resistor R 3   120 . In the prior art in FIG. 1, some implementations utilize multiple PN diodes in the first input path as represented by  145 . 
     FIG. 1 also shows a second input path that drives the second differential input Va  175 . The second input path contains PN diode Q 1   125 . PN diode Q 1   125  is constructed from a PNP bipolar junction transistor, BJT, Q 1   125 . The BJT  125  has its base and collector tied in common to ground  140 . The emitter of Q 1   125  is tied to the input Va  175 . 
     FIG. 1 also shows a first feedback path that contains a first feedback resistor, R 2   110 . This R 2  resistor is connected between the first differential input Vb  165  and the differential output VBP  155 . 
     FIG. 1 also shows a second feedback path that contains a second feedback resistor, R 1   115 . This R 1  resistor is connected between the second differential input Va  175  and the differential output VBP  155 . 
     FIG. 1 also shows a third PMOS FET, MP 3   190 . This device is used to drive the differential output VBP  155 . Also, the PMOS FET, MP 3   190  is used to isolate the differential output VBP  155  from the internal differential amplifier node  171 . MP 2   150  and MP 1   180  are a current mirror. They are uses as the active load of MN 2   160  and MN 1   170 . 
     U.S. Pat. No. 6,281,743 B1 (Doyle) “Low Supply Voltage Sub-Bandgap Reference Circuit ” describes a reference circuit which results in a reference voltage which is smaller than the bandgap voltage of silicon. The circuit is temperature compensated. 
     U.S. Pat. No. 6,204,724 (Kobatake) “Reference Voltage Generation Circuit Providing a Stable Output Voltage” discloses a reference voltage generation circuit which utilizes two current mirrors circuits. This invention produces a stable output voltage. 
     U.S. Pat. No. 5,796,244 (Chen, et al.) “Bandgap Reference Circuit” discloses a voltage reference circuit, which is incorporated within an integrated circuit and which minimizes currents into the substrate. 
     U.S. Pat. No. 5,900,773 (Susak) “Precision Bandgap Reference Circuit” discloses a precision bandgap reference circuit. The circuit has an output stage which is biased with Proportional To Absolute Temperature (PTAT) current which is well controlled. 
     U.S. Pat. No. 6,150,872 (McNeill, et al.) “CMOS Bandgap Voltage Reference” discloses a bandgap reference circuit, which uses Proportional To Absolute Temperature (PTAT) voltage. The circuit can generate voltages below 1.24 volts. The invention utilized a start-up circuit to force the reference circuit into a known state. 
     BRIEF SUMMARY OF THE INVENTION 
     It is the objective of this invention to provide a circuit and a method for generating a bandgap reference voltage. 
     It is further an object of this invention to provide a bandgap reference circuit and method which provide a stable bandgap reference voltage which is immune to temperature, process and power supply variations. 
     It is further an object of this invention to provide the ability to generate lower reference voltages which are compatible with the advances in integrated circuits. 
     The objects of this invention are achieved by a bandgap reference circuit made up of a differential amplifier whose two inputs are compared to produce a difference signal and whose output is fed back to two input resistors of different values, a first differential input path which contains a first input bias resistance one end of which is connected to the first differential input, the other end of this first bias resistance is connected to the P-side of a first diode whose N-side is connected to ground, a second differential input path which contains a second input bias resistance one end of which is connected to the second differential input, the other end of this second bias resistance is connected to the P-side of a second diode whose N-side is connected to ground, a path parallel to said second differential input path which contains a capacitor connected between the second differential input and ground, a first feedback path from the differential output to a first feedback resistor whose other side is connected to said first differential input, a second feedback path from the differential output to a second feedback resistor whose other side is connected to the second differential input, and a differential output node which is driven by an MOS FET. 
     The bandgap reference circuits differential amplifier contains two P-channel metal oxide semiconductor P-MOSFET devices whose sources are connected to the Vdd supply voltage and are used as load devices and for current mirroring, two NMOS FETs whose inputs are connected to the two inputs which are to be compared, and a current source whose constant current flows from the commonly connected sources of said two NMOS FETs to ground. The bandgap reference circuit&#39;s first differential input path contains a first bias resistance which is composed of two series connected parts, a constant part and a variable part. The bandgap reference circuit&#39;s variable part of the first input bias resistance is a function of the resistance of the first feedback path. The bandgap reference circuits second differential input path contains a second bias resistance which is composed of two series connected parts, a constant part and a variable part. 
     The bandgap reference circuit&#39;s variable part of the second input bias resistance is a function of the resistance of the second feedback path. The bandgap reference circuit&#39;s path parallel to the second differential input path which contains a capacitor C which is connected between the second differential input and ground. The bandgap reference circuit&#39;s first feedback path contains a first feedback resistance. The bandgap reference circuit&#39;s first feedback resistance has a design value which is a function of said variable component of the first input bias resistance. The bandgap reference circuit&#39;s second feedback path contains a second feedback resistance. The bandgap reference circuit&#39;s second feedback resistance has a design value which is a function of the variable component of the second input bias resistance. The bandgap reference circuit&#39;s differential output is driven by a third PMOS FET device. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 shows a prior art bandgap reference circuit diagram. 
     FIG. 2 gives a bandgap reference circuit diagram which illustrates the main embodiment of this invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     FIG. 2 shows an embodiment of the bandgap reference circuit of this invention. A differential amplifier is made up of two p-channel metal oxide semiconductor field effect transistors PMOS FETs MP 1   270  and MP 2   250 . It is also made up of the two n-channel metal oxide semiconductor FETs MN 1   280  and MN 2   260 . Finally, the differential amplifier is made up of a current source  290  which connects to the common sources of the two NMOS FETs of the differential amplifier and sinks the current from them. 
     FIG. 2 also shows a first input path that drives the first differential input Vb  275 . The first input path contains resistor R 3   230  and PN diode Q 2   240 . PN diode Q 2   240  is constructed from a PNP bipolar junction transistor, BJT, Q 2   240 . The BJT  240  has its base and collector tied in common to ground  295 . The emitter of Q 2   240  is tied to the resistor R 3   230 . As is illustrated in FIG. 2, some implementations utilize multiple PN diodes in the first input path as represented by  255 . The first input path also contains resistor aR 2   220  which is connected between resistor R 3   230  and the first differential input  275 . 
     FIG. 2 also shows a second input path that drives the second differential input Va  223 . The second input path contains PN diode Q 1   231 . PN diode Q 1   231  is constructed from a PNP bipolar junction transistor, BJT, Q 1   231 . The BJT  231  has its base and collector tied in common to ground  295 . The emitter of Q 1   231  is tied to the input Va  223 . The second input path also contains resistor aR 1   235  connected between the emitter of Q 1   231  and the second differential input  223 . 
     FIG. 2 also shows a first feedback path that contains a first feedback resistor, ( 1 −a)R 2   210 . This ( 1 −a)R 2  resistor is connected between the first differential input Vb  275  and the differential output VBP  265 . 
     FIG. 2 also shows a second feedback path that contains a second feedback resistor, ( 1 −a)R 1   225 . This ( 1 −a)R 1  resistor is connected between the second differential input Va  223  and the differential output VBP  265 . 
     FIG. 2 also shows a third PMOS FET, MP 3   215 . This device is used to drive the differential output VBP  265 . Also, the PMOS FET, MP 3   215  is used to isolate the differential output VBP  265  from the internal differential amplifier node  213 . 
     The threshold voltage, Vth of 2.5 volt and 3.3 volt devices are 0.55 volt and 0.62 volt respectively. Q 1   125  and Q 2   130  in FIG. 1 are bipolar transistors whose base-emitter voltage drop, VEB is around 0.56 volt at high temperature. In FIG. 1, in the prior art, therefore, it is difficult to turn ON MN 1   170  and MN 2   160  at high temperature because the Vth of these two devices, Vth, is larger than VEB of the bipolar transistors, Q 1  and Q 2 . 
     In FIG. 2 which shows the main embodiment of this invention, it is easy to turn ON MN 1   280  and MN 2   260  at higher temperatures. This is true since this invention uses two resistors, aR 2   220  and aR 1   235  to raise the voltage level of the first and second differential inputs, Vb and Va by I*aR where (0&lt;a&lt;1). Therefore, the voltage level of Va  223  and Vb  275  is VEB+I *aR which is larger than Vth of MN 2   260  and MN 1   280 . 
     Below is a derivation of the output voltage produced by the bandgap reference circuit of this invention. The derivation can be followed by referring to the devices in FIG.  2 . 
     
       
         Assume  R 1 =R 2 =R  and 0 &lt;a &lt;1 
       
     
     
       
           Va=Vb  and  I 1 =I 2 
       
     
     
       
         Then  Va 1 =Vb 1 =VEB 1 
       
     
     
       
           VEB 1 −VEB 2 =Vt*In{[N *(1 −a ) R  1]/(1 −a ) R 2 }=Vt*In N   
       
     
     
       
           I 1 =I 2=( Vb 1 −VEB 2)/ R 3=( VEB  1 −VEB 2)/ R 3=( Vt*In N )/ R 3 
       
     
     
       
           VBP=I 1*(1 −a ) R 1+( I 1 *aR  1)+ VEB 1 =VEB 1+( I 1 *R  1)= VEB 1+( R 1 /R 3)*( Vt*InN ) 
       
     
     The advantage of this invention is the use of extra resistors in the two differential input paths. These added resistors allow the circuit of the invention to easily turn ON MN 1  and MN 2  at higher temperatures. 
     While this invention has been particularly shown and described with Reference to the preferred embodiments thereof, it will be understood by those Skilled in the art that various changes in form and details may be made without Departing from the spirit and scope of this invention.