Patent Publication Number: US-2010117699-A1

Title: PWM Controller with Frequency Jitter Functionality and Related Method

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a pulse width modulation (PWM) controller with frequency jitter functionality and related method for reducing electromagnetic interference (EMI) of a switching power supply. 
     2. Description of the Prior Art 
     Power supplies, converting an AC mains voltage to a DC voltage, are wildly used in integrated electronic devices. The power supplies are required to maintain the output voltage, current or power within a regulated range for efficient and safe operation of the electronic device, and thus switches that operate according to a pulse width modulated (PWM) control are employed. 
     Please refer to  FIG. 1 .  FIG. 1  is a schematic diagram of a traditional power supply  10 . Generally, the power supply  10  includes a transformer  100 , a transistor  102 , a PWM controller  104 , an opto-coupler  106  and an error amplifier  108 . The PWM controller  104  generates a switching signal V PWM  for switching the transformer  100  via the transistor  102 . The duty cycle of the switching signal V PWM  determines the power delivered from a primary winding Np to a second winding Ns of the transformer  100 , and thus, in order to keep the secondary DC voltage within a regulated range, a feedback loop including the opto-coupler  106  and the error amplifier  108  provides a feedback voltage VFB to vary the duty cycle of the switching signal V PWM . 
     A problem of utilizing PWM controllers is that they operate at a relatively high frequency compared to the frequency of the AC mains voltage, which results in a high frequency signal being generated by the power supply. This high frequency signal is injected back into the AC mains input and becomes a component of the AC mains signal. The high frequency signal and its harmonics are also radiated by the power supply as electromagnetic waves, which in fact are the largest contributors to the Electromagnetic Interference (EMI) of the power supply. The EMI generated by the power supply can cause problems for communication devices in the vicinity of the power supply, and the high frequency signal which becomes a component of the AC mains signal will be provided to other devices in the power grid, which also causes noise problems for those devices. Further, the radiated EMI by the power supply can interfere with radio and television transmissions that are transmitted over the air by various entities. 
     Thus, in order to combat the EMI problem, a jittered clock source is often utilized to be the operation frequency of the PWM switch, which allows the switching frequency spreading over a larger bandwidth, so as to minimize the peak value of the EMI generated by the power supply. However, since the jittered clock source is generally generated by adding a time-varying signal such as a time-varying current or a time-varying capacitance to an oscillation frequency of an oscillator, external frequency generation circuits in addition to the oscillator are required to generate the time-varying signal in the PWM controllers. Therefore, the size and cost of the power supply are increased. 
     SUMMARY OF THE INVENTION 
     It is therefore an objective of the present invention to provide a PWM controller with frequency jitter functionality to reduce EMI of a power supply. 
     According to the present invention, a PWM controller with frequency jitter functionality is disclosed. The PWM controller includes an oscillator and a threshold voltage generator. The oscillator is utilized for generating a switching frequency signal according to an upper threshold voltage and a lower threshold voltage. The threshold voltage generator is coupled to the oscillator, and is utilized for generating the upper threshold voltage and the lower threshold voltage and modulating at least one of the upper threshold voltage and the lower threshold voltage to vary over time for jittering the switching frequency signal. 
     According to the present invention, a PWM controller with frequency jitter functionality is further disclosed. The PWM controller includes an oscillator and a voltage divider. The oscillator is utilized for generating a switching frequency signal according to an upper threshold voltage and a lower threshold voltage. The voltage divider is coupled to the oscillator, and is utilized for performing a voltage-dividing operation on a power supply voltage to generate the upper threshold voltage and the lower threshold voltage, and modulating both of the upper threshold voltage and the lower threshold voltage to vary over time due to glitches of the power supply voltage those suddenly drop by charging or discharging rear end loads in order for jittering the switching frequency signal. 
     According to the present invention, a frequency jitter method for a PWM controller is further disclosed. The frequency jitter method includes the steps of generating a switching frequency signal according to an upper threshold voltage and a lower threshold voltage of an oscillator, and modulating at least one of the upper threshold voltage and the lower threshold voltage to vary over time for jittering the switching frequency signal. 
     These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a schematic diagram of a traditional power supply. 
         FIG. 2  is a schematic diagram of a PWM controller with frequency jitter functionality according to an embodiment of the present invention. 
         FIG. 3  shows an exemplary embodiment of the threshold voltage generator in  FIG. 2 . 
         FIG. 4  is a timing diagram of an upper threshold voltage, a lower threshold voltage, a saw-tooth wave and a switching frequency signal related to  FIG. 3 . 
         FIG. 5  shows another exemplary embodiment of the threshold voltage generator in  FIG. 2 . 
         FIG. 6  also shows an exemplary embodiment of the threshold voltage generator in  FIG. 2 . 
         FIG. 7  is a timing diagram of an upper threshold voltage, a lower threshold voltage, a saw-tooth wave and a switching frequency signal related to  FIG. 5  and  FIG. 6 . 
         FIG. 8  is a schematic diagram of a frequency jitter process for a PWM controller according to an embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION 
     Please refer to  FIG. 2 .  FIG. 2  is a schematic diagram of a pulse width modulation (PWM) controller  20  with frequency jitter functionality according to an embodiment of the present invention. The PWM controller  20  is utilized for controlling a switching power supply, and includes an oscillator  21  and a threshold voltage generator  22 . The oscillator  21  is utilized for generating a switching frequency signal osc_out according to an upper threshold voltage V H  and a lower threshold voltage V L , and includes a saw-tooth wave generator  212 , a first comparator  214 , a second comparator  216  and an RS latch  218 . The saw-tooth wave generator  212  is utilized for generating a saw-tooth wave V SAW . The first comparator  214  has a positive input terminal coupled to the upper threshold voltage V H  and a negative input terminal coupled to the saw-tooth wave generator  212 , and is utilized for generating a reset signal V rst  when the saw-tooth wave V SAW  rises to the upper threshold voltage V H . The second comparator  216  has a positive input terminal coupled to the saw-tooth wave generator  212  and a negative input terminal coupled to the lower threshold voltage V L , and is utilized for generating a set signal V set  when the saw-tooth wave V SAW  descends to the lower threshold voltage V L . The RS latch  218  has a reset terminal coupled to the first comparator  214  and a set terminal coupled to the second comparator  216 , and is utilized for generating the switching frequency signal osc_out according to the reset signal V rst  and the set signal V set . More specifically, the switching frequency signal osc_out is low when the reset signal V rst  is received, and is high when the set signal V set  is received. In addition, the switching frequency signal osc_out is further fed back to the saw-tooth wave generator  212  for controlling the generation of the saw-tooth wave V SAW . Detailed operations of the oscillator  21  are well-known by those skilled in the art, and not narrated herein. 
     The threshold voltage generator  22  is coupled to the oscillator  21 , and is utilized for generating the upper threshold voltage V H  and the lower threshold voltage V L  of the oscillator  21 . Furthermore, the threshold voltage generator  22  modulates at least one of the upper threshold voltage V H  and the lower threshold voltage V L  to vary over time for jittering the switching frequency signal osc_out generated by the oscillator  21 . In other words, by modulating the threshold voltages of the oscillator  21  to vary over time, the time that the saw-tooth wave V SAW  takes to reach the threshold voltage also changes as long as the rising or descending slope of the saw-tooth wave V SAW  is kept the same, so the frequency generated by the oscillator  21  is also changed. In this case, the operation frequency of the PWM controller  20  can be jittered and spread over a larger bandwidth, so as to minimize the peak value of electromagnetic interference (EMI) generated by a switching power supply. 
     Preferably, the threshold voltage generator  22  can simply be a voltage divider. Please refer to  FIG. 3 , which shows an exemplary embodiment of the threshold voltage generator  22  of the present invention. As shown in  FIG. 3 , the threshold voltage generator  22  is a resistance voltage divider, and performs a voltage-dividing operation on a power supply voltage VDD to generate the upper threshold voltage V H  and the lower threshold voltage V L . Since the power supply voltage VDD may have some glitches when charging or discharging rear end loads, both of the upper threshold voltage V H  and the lower threshold voltage V L  are then varied over time by those sudden drops. Therefore, the switching frequency generated by the oscillator  21  can be jittered by the time-varying threshold voltages. Related timing of the upper threshold voltage V H , the lower threshold voltage V L , the saw-tooth wave V SAW  and the switching frequency signal osc_out are shown in  FIG. 4 . 
     Thus, by taking advantages of the glitches of the power supply voltage VDD, the switching frequency generated by the oscillator  21  can be jittered by the time-varying threshold voltages, and no external frequency generation circuits in addition to the oscillator  21  are required in the PWM controller. Therefore, the size and cost of the power supply can be significantly reduced. 
     Certainly, the threshold voltage generator  22  can also be realized by other schemes, providing that at least one of the upper threshold voltage V H  and the lower threshold voltage V L  being varied over time, so as to jitter the switching frequency signal osc_out generated by the oscillator  21 .  FIG. 5  shows another exemplary embodiment of the threshold voltage generator  22  of the present invention. The threshold voltage generator  22  is a signal converter, performing signal conversion on controllable inputs b 0 ˜b n  in order to generate at least one of the time-varying upper threshold voltage V H  and the time-varying lower threshold voltage V L . In  FIG. 5 , the threshold voltage generator  22  is implemented with a digital-to-analog converter as an example, and the controllable inputs b 0 ˜b n  are produced by a digital code generator (not shown in  FIG. 5 ). 
     On the other hand, the threshold voltages of the oscillator  21  can also be generated and modulated in analog manners. Please refer to  FIG. 6 , which also shows an exemplary embodiment of the threshold voltage generator  22  of the present invention. As shown in  FIG. 6 , the threshold voltage generator  22  includes a first current source  61 , a second current source  62 , a charge switch  63 , a discharge switch  64  and a capacitor C 1 . The first current source  61  and the second current source  62  are utilized for providing a charge current I 1  and a discharge current I 2 , respectively. The charge switch  63  and the discharge switch  64  are shorted alternatively by control signals clk and clkB those have opposite phases. The capacitor C 1  is then charged by the charge current I 1  via the charge switch  63  and discharged by the discharge current I 2  via the discharge switch  64  to generate at least one of the upper threshold voltage V H  and the lower threshold voltage V L . In this case, a smoothly time-varying upper threshold voltage V H , for example, can be generated in a triangular wave form by the fixed charge and discharge currents I 1  and I 2 , so as to jitter the switching frequency signal osc_out generated by the oscillator  21 . 
     Please further refer to  FIG. 7 .  FIG. 7  is a timing diagram of the upper threshold voltage V H , the lower threshold voltage V L , the saw-tooth wave V SAW  and the switching frequency signal osc_out related to  FIG. 5  and  FIG. 6 , in which only the upper threshold voltage V H  is varied over time while the lower threshold voltage V L  has a fixed value. Likewise, in other embodiments of the present invention, the lower threshold voltage V L  can also be modulated to vary over time while the upper threshold voltage V H  is fixed, by which the switching frequency of the oscillator  21  can also be jittered. 
     Please note that the above embodiments of the threshold voltage generator  22  are merely exemplary illustrations of the present invention, those skilled in the art can certainly make appropriate modifications according to practical demands, such as modulating the threshold voltages of the oscillator in other waveform shapes, which also belongs to the scope of the present invention. 
     In addition, please refer to  FIG. 8 .  FIG. 8  is a schematic diagram of a frequency jitter process  80  for a PWM controller according to an embodiment of the present invention. The frequency jitter process  80  is utilized for implementing the above PWM controller  20 , and includes the following steps: 
     Step  800 : Start. 
     Step  810 : Generate a switching frequency signal according to an upper threshold voltage and a lower threshold voltage of an oscillator. 
     Step  820 : Modulate at least one of the upper threshold voltage and the lower threshold voltage to vary over time for jittering the switching frequency signal. 
     Step  830 : End. 
     According to the frequency jitter process  80 , the switching frequency signal is generated according to the upper threshold voltage and the lower threshold voltage of the oscillator. Then, by modulating at least one of the upper threshold voltage and the lower threshold voltage to vary over time, the switching frequency signal can further be jittered and spread over a larger bandwidth, so as to reduce the EMI generated by a PWM controller. Detailed operations of the PWM controller are already described above, and not narrated again herein. 
     As mentioned above, by modulating the threshold voltages of the oscillator to vary over time, the operation frequency of the PWM controller can be jittered and spread over a larger bandwidth, so as to minimize the peak value of EMI generated by a switching power supply. 
     Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention.