Patent Publication Number: US-3972033-A

Title: Parity check system in a semiconductor memory

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates to a new arrangement of parity check bits in a semiconductor memory in data processing electronic apparatus. 
     In recent times, semiconductor storage systems have been largely employed as the main memories in data processing apparatus. These memories which are produced as large-scale integrated circuits having high density and a high number of elements, have shown remarkable advantages over the usual memories employing magnetic elements, with regard to operating speed, fabrication costs, and reliability. However, their operation requires particular care, especially with regard to the very high precision needed in the control times of different operations and, therefore, in the intervals between subsequent timing clock pulses. 
     These memories are produced by arranging integrated memory circuital units on printed-circuit cards together with the related control and address circuits, thus building modules having a predetermined partial capacity, these modules being duplicated until the planned whole capacity of the memory is reached. 
     The so-called &#34;check bit&#34;, or &#34;parity bit&#34;, method for detecting an error in the recording of an information bit of a word has been long known and is in general use. It consists in appending to the information bits of the word a check bit, whose binary value is so chosen, that, for example, the number of the bits of value ONE is always even. If this condition is not satisfied, at the end of an operation, this means that a bit is affected by error. 
     This technique as it is employed in the present state of the art, usually is unable to detect a cause of error affecting not a single bit, but the whole word including the check bit: for instance, a false addressing, causing the whole word, and its check bit, to be written at a wrong address, or, as it may happen in semiconductor memories, when a wrong time interval between two clock signals may alter the recording of a whole word in the same way for all bits, including the check bit. This is important because, in the prior art, the control and address circuits are assembled on the same printed card carrying the integrated memory units wherein all information and check bits of a word are recorded. Thus, it may happen that any cause of malfunction of the circuits on the card, such as an assembling mistake, a faulty contact, noise, and so on, affecting, for instance, an address amplifier, may cause a wrong addressing of the whole word or, affecting a clock circuit, may cause the wrong recording of a whole word. These errors, being common both to the information bits and to the check bits, cannot be detected by the parity check. 
     SUMMARY OF THE INVENTION 
     The arrangement according to the invention obviates these drawbacks of the prior art by separating the causes of errors which may affect the addressing and the recording of the information bits from the ones which may affect the check bits, thus making possible the detection of errors due to these causes. 
     The invention is described as applied to a semiconductor memory wherein the recording words comprise sixteen information bits and are divided into two &#34;bytes&#34; of eight bits each. Each byte is provided with its own check bit; therefore, the memory may record two half-words of nine bits at the same address. The minimal modular assembling unit in this memory is the so-called &#34;submodule&#34; comprising two printed-circuit cards. According to the invention, the first card carries the integrated memory units wherein, for each word, the information bits of the first byte and the check bit of the second byte are recorded; the second card carries the memory units wherein the information bits of the second byte and the check bit of the first byte are recorded. Therefore, an error cause, which may affect the control or the addressing circuits mounted on a card, does not affect the recording and the addressing circuits of the second card. There will thus be a difference in the recording or in the addressing of the information bits with respect to the related check bit, thus allowing the detection of the presence of an error. 
     In the preferred embodiment described hereinafter, it is required that both bytes may be written or read out separately; therefore, the arrangement according to the invention provides means for sending the writing or the reading-out signal of the information bits independently from the writing or reading signal of the check bits, for both cards. Thus, if the second byte, in contrast with conventional practice, is written on the first card, the related check bit is written at the same address, but on the second card. 
     It should be noted that the time interval between two consecutive clock signals, that is, the enable clock and the precharge clock, as explained later, which is of essential importance for the correct operation of the memory, is obtained by the use of a delay line mounted on the same card which supports the integrated memory units. Therefore, any cause of error that may affect this delay line and the associated amplifiers, and thereby the time interval between these clock signals, may affect only the recording of the information bits or, alternatively, only the recording of the check bit of the byte having the information bits recorded by the memory units mounted on the same card as the delay line and associated amplifiers, which may be the cause of the error or may be affected by a common cause or error. Hence, the error which takes place in the information bits, or, respectively, in the check bit, will be detected by the parity check. 
     It is apparent that the principle of the invention may also find application in those cases in which each memory word is divided into more than two &#34;partial words&#34;, or bytes, each one provided with its check bit. The check bits of each byte will be controlled, according to the invention, by circuits different from those controlling the information bits of the same byte. To obtain this, the integrated memory unit recording the information bits of a given byte will be conveniently mounted on cards different from the cards supporting the related check bit. 
     These and other advantages and features of the invention will appear clearly from a detailed description of a preferred embodiment thereof, and from the attached drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a simplified diagram of an integrated semiconductor memory unit of known type; 
     FIG. 2 is a simplified wiring diagram of the assembly of a number of said integrated units and part of its control circuits on a printed circuit card according to the invention; 
     FIG. 3 is a wiring diagram of a group of clock amplifiers and of the delay line according to the invention; 
     FIG. 4 is a schematic wiring diagram of a printed circuit card for integrated semiconductor memory elements, and of the related control circuits, according to the invention; 
     FIG. 5 shows a simplified wiring diagram of the memory refreshing circuit; and 
     FIG. 6 is a schematic block diagram or the general layout of a memory module, and its interface with the central processor unit, according to the invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     The semiconductor memory to which the present invention is applied is a memory organized for a maximal planned number (in the example, four) of memory &#34;modules&#34;. The modules effectively installed may be less than four, according to the required capacity of the memory. Each module comprises a variable number (in the example, one to eight) of &#34;submodules&#34;. According to the preferred embodiment, each submodule comprises two printed-circuit cards, on which the integrated memory units and the control circuits needed for their operation are mounted. 
     Each memory card carries 36 integrated memory units, having a capacity of 1024 bits each. The 36 units are arranged in four rows of nine each. Each one of the first eight integrated units of each row is intended for recording the bits of the same order of 1024 eight-bit half-words (bytes). The ninth unit of each row is intended to record the 1024 parity check bits assigned to each half-word. Each card therefore may record 4096 bytes, and each submodule 4096 words having 16 information bits and two check bits. The submodule, the capacity of which approximates 4000 words, is the minimum modular unit of the memory: the memory capacity may therefore range from a minimum of 4000 words to a maximum of four modules each having a 32,000 word capacity -- that is, a maximum of 128,000 words each having 16 information bits. 
     For a better understanding of the invention, the layout and the operation of a 1024 bit integrated semiconductor memory unit, including the built-in control, selection and clock circuits is hereafter described. Such integrated memory units are available on the market, under code number 1103, from the Intel Corporation, Santa Clara, California, and are fully described both by the technical papers of the producers, and, for instance, in the article &#34;Application Considerations for Read-Write Memory,&#34; M. E. Hoff, appearing in the book Semiconductor Memories, published by Wiley-Interscience in 1971. It is, on the other hand, apparent that the application of the invention is not limited to the integrated memory units of the cited producer, but that it may be carried out on memories employing semiconductor units having substantially equivalent features by applying such modifications as are known to anyone skilled in the art. 
     FIG. 1 shows the wiring block diagram of such an integrated memory unit, comprising 32 rows and 32 columns of elementary memory cells. Only the blocks representing the first and the last cells of the first and of the last row are shown therein, the simplified circuit of a cell being shown in the interior of the first block of the first row. The cell comprises three field effect transistors Q 1 , Q 2  and Q 3 , each one of these having a source terminal S, a drain terminal D, and a gate terminal G. When a positive voltage V SS  (in the example, +16 V.) is applied to the S terminal, while the D terminal is at a voltage V DD  = 0 V., the transistor conducts between S and D if the G terminal is at a voltage V DD  = 0V., and does not conduct if the G terminal is at a voltage of V SS  = 16 V. The voltage V SS  = 16 V. corresponds to binary ZERO, the voltage V DD  =  0V. to binary ONE. 
     To prevent secondary effects, the semiconductor substrate on which the integrated circuit is deposited, is kept at a positive voltage V BB  approximately equal to 20 V. For simplicity, in FIG. 1, V BB  is assumed to be equal to V SS . 
     The information is recorded in the stray capacity CM between the substrate and the load connecting the D terminal of Q 1  to the G terminal of Q 2 . If the registered information is ONE, this lead is at voltage V DD  (0 V.), the capacitor CM is charged, the G terminal of Q 2  is at  0 V., and Q 2  is conducting. If the information is ZERO, the capacity is not charged, and Q 2  does not conduct. The cell has four control terminals SR (Read Selection), RD (Data Read), WD (Data Write), and SW (Write selection) and a free terminal V SS . 
     In order to read the information recorded in the cell, the terminal RD is &#34;precharged&#34;, that is, brought to V DD  for a suitable time interval (about 125 nanoseconds). Then the voltage V DD  is cut out, and the transistor Q 3  is made conductive by applying a ONE signal (V DD ) to the terminal SR. If the recorded information is ONE, Q 2  conducts, the terminal RD is connected to V SS  through Q 2 , and Q 3  and goes over the voltage V SS , that is, to binary ZERO. If the recorded information is ZERO, Q 2  does not conduct, and RD remains at V DD , that is, at binary ONE. The output is read out by sensing the voltage of terminal RD in a very short time interval (50 ns.) following the end of the precharge and is inverted with respect to the recorded information. 
     To write, a voltage V DD  or V SS , according to whether a ONE or a ZERO is to be written, is applied to terminal WD; and a signal ONE is applied to SW, thus making Q 1  conductive and therefore charging or discharging the capacitor CM. 
     As may be seen, the reading out, in itself is not destructive of the recorded information; however, due to the low insulation of the capacitor CM, it is necessary to rewrite the recorded information periodically, and this is done every time the information is read out. It is prescribed that this rewriting, or &#34;refreshing&#34;, of the information must take place within a maximum time interval of two milliseconds from the last read-write operation. 
     The various operations are controlled by three clock signals, that is, the precharge clock CP, the enable clock CE, and the write clock CW. The first two clocks are perodically sent to the memory at each memory cycle and control the read and refresh operations; the third is sent to the memory only during the write cycles. 
     The 32 read selection (SR) terminals of each row are connected to a single row read selection lead SRL, and each one of these leads is connected to one of 32 output terminals of a row decoder DCR, which has five inputs, to which the five bits, forming the row address code BA 12  to BA 6 , are applied. The decoder is enabled by the enable clock signal CE. 
     Also the 32 write selection terminals SW of each row are connected to a single one of 32 write row selection leads SWL, each one of which is connected to one of 32 output terminals of the same row decoder DCR. This decoder may therefore enable all the 32 memory cells of a selected row, both for reading and for writing. 
     The 32 data read terminals RD of each column are connected to a single one of 32 data read leads RDL, one for each column. Each one of these is connected to an output of a precharge switch IPC, controlled by a common lead PCA connected to the output of a precharge control switch CPC, which in turn is controlled by the precharge clock CP and the enable clock CE. The lead PCA goes over to binary ONE when, CE being at ZERO, CP goes to ONE. In this condition, the switches IPC apply the voltage V DD  to the leads RDL, thus starting the precharge process. 
     The precharge ends when CE goes to ONE and PCA to ZERO. During the interval between this instant and the subsequent going to ZERO of CP, the lead RDL is at binary ZERO or ONE according to the information recorded in the cell. This value, which is inverted with respect to the recorded information, is applied to the input of a refresh inverter amplifier AIR controlled by clocks CP and CW. The output of the inverter amplifier AIR is enabled only if CW is ZERO, that is, only during the reading and refreshing cycles, but not during the write cycles. The output of each amplifier AIR is connected to the write lead WDL to which the WD terminals of the corresponding column are connected. Therefore, the voltage corresponding to the inverted information recorded in the cell is applied to these terminals; and, as only the date write terminals of the selected row are enabled, the recorded information is rewritten in the selected cell. 
     The output of the amplifier AIR and the data write lead WDL of each column are connected to an input terminal of a column write-read switch CWR which is selected by one of 32 column selection leads SCC connected to the output terminals of a column decoder DCC, which has five input terminals to which the five column address bits of the address code BA 7  to BA 11  are applied. The switches CWR are controlled by the clock CW, which, when it is at ZERO, enables the read-out data to be applied to an input-output circuit IOC during the read cycles, and to be available on the data write lead TUD. The input data are applied at the data input terminal TID, and through the same input-output circuit IOC to the CWR switch of the selected column. They are transmitted to the write column lead WDL only if CW is at ONE, that is, during a write cycle. As said, the signal CW at level ONE inhibits the refresh amplifier AIR and therefore the read-out data are not transferred to the write input of the selected cell. 
     It may be noted from the aforesaid that, in the first place, the precision of the time interval occurring between the going over to ONE of the clock CE and the following return to ZERO of the clock CP is important, because it is during this interval that the data read terminal of the selected cell applies to the input of the amplifier AIR the inverted value of the read out information. In the considered example, this interval must be shorter than 75 ns. and longer than 25 ns. In the second place, it may be seen that the refreshing of the recording information in every cell of each row takes place every time a cell of the same row is read out. However, a row refresh operation differs from a cell read-out operation only by the circumstance that in the former case no column is selected for reading out. 
     Each integrated unit has the following eighteen terminals: three for the feeding voltages V SS , VDD and V CC  ; ten for the address bits BA 7  to BA 16  ; three for the clock signals CP, CE, and CW; one for the data input; and one for the data output. 
     Each memory card (FIG. 2), corresponding to a half-submodule, carriers four rows of nine integrated units each, and may record 1024 half-words of eight information bits and a check bit. The 16 information bits and the two check bits of a word are recorded in the cells of the same address of the units of the same row; the bits 0-7 of a word are recorded in the first eight units of a row of the first card, the bits 8-15 of the same word are recorded in the first eight units of the same row of the second card. The last units of both rows record the check bit, the check bit of the first half-word being recorded by the last unit of the second card, and the check bit of the second half-word being recorded by the last unit of the first card. This is done to increase the error detecting efficiency of the check bits. An error generated, for instance, by the address amplifiers of a card could in effect cause a half-word and its check bit to be written at a wrong address. Such an error could not be detected by the parity check if the same set of address amplifiers would control both the information bits and the check bit. The same could happen for an error due to malfunctioning of the devices controlling the read-write operations. 
     By this arrangement, that is, by locating the check bit recording units on a card different from the one for the information bits, the error may affect either the former or the latter only, and may be detected by the parity check. As the computer is able, according to the conditions, to write either a single half-word at a time, or both half-words in a single operation, the read-write control signal of the check bits must be independent from the read-write control signals for the information bits. As a matter of fact, if, for instance, the first half-word is written, and not the second one, the write control signal of the check bit of the first half-word, which is recorded on the second card, must be emitted even if the write control signal for the information bits of the second card is not emitted. 
     FIG. 2 shows the layout and the connections of the integrated units arranged in four rows on a card. The eight integrated units of the first row, intended for recording the information bits, are indicated by RUI 00  to RUI 07 , and the integrated unit of this row intended for recording the check bits is indicated by RUC 0 . Similarly, RUI 10  to RUI 17  and RUC 1  indicate respectively the information bit recording units and the check bit recording unit of the second row; and RU 20  to RU 27  and RUC 2 , and RU 30  to RU 37  and RUC 3  to the corresponding units respectively of the third and fourth row. Each one of the ten address terminals (BA 7  to BA 16 ) of each integrated unit is connected to all the homologous terminals of the other units by &#34;bus&#34; leads which are not shown in the drawing. The same holds for the feed terminals V SS , V DD  and V BB . The terminals CP and CE, for the precharge and enable clock signals of the integrated units of each row are parallel connected to the leads CP 0 , CP 1 , CP 2 , and CP 3 , and respectively, CE 0 , CE 1 , CE 2 , and CE 3 . 
     For each row, two leads are assigned to the clocks CWI (write clock for the information bits) and CWC (write clock for the check bits); more precisely, the leads CWI 0  to CWI 3  are connected to the CW terminals of the information recording integrated units (RUI) of the respective rows; and the leads CWC 0  and CWC 3  are connected to the terminals CW of the integrated units for the check bits of the respective rows. 
     These four clock leads of each row are connected to the four outputs of a group of controlled amplifiers, respectively indicated by CAR 0  to CAR 3 . The four clock signals are parallel applied to the four inputs of each group through four common terminals CWC&#39;, CWI&#39;n, CP&#39; and CE&#39;. For each operation, only one of the four amplifier groups is enabled by a row selecting signal, respectively, SAR 0  to SAR 3 . 
     The row selecting signals and the clock signals applied to the inputs of these controlled amplifiers must be consistent with the standards adopted for the computer circuits; for instance, as in the example considered, the transistor transistor logic (TTL), which uses, for binary ONE, +3.5 V., and for the ZERO, 0 V. The output signal of each amplifier must be consistent with the standard required for field effect transistors, also called MOS (metal-oxide semiconductor), standard. This standard calls for 0 V. as binary ONE and +16 V. as binary ZERO. 
     FIG. 3 shows in better detail the connections of the amplifiers of a CAR group, and illustrates an arrangement adopted in order to guarantee the precision of the time interval between going over to ONE of the clock CE and the falling to ZERO of the clock CP, which defines the reading time for the data output. The write clocks, CWI&#39; for information bits, and CWC&#39; for check bits, generated by the clock generating circuit of the module, (see later), are amplified and transformed into MOS standard by the controlled amplifiers ACWI and ACWC, which may be enabled by the row selecting signal SAR, and are available at the outputs CWI and CWC. The controlled amplifier ACE, which is enabled by the row selection signal, transforms the clock CE from TTL to MOS standard and makes it available at the output terminal CE. This clock signal is also applied to the input of an amplifier BCE which retransforms it to TTL standard and applies the same to the input of a delay line LIR. The precharge clock signal emitted by the clock generator is applied, through the CP&#39; terminal, to a controlled amplifier ACP which may be enabled by the row selection signal and inhibited by the signal at the output of the delay line LIR. The precharge clock signal from the clock generator is so adjusted, as to be somewhat longer than the maximum required value. Therefore, the output CP returns to ZERO after a time interval, from the going over to ONE of the enable clock CE, due to the propagation time of the delay line. This time interval, during which both clocks CP and CE are at ONE, is defined by the propagation time and by the response times of the amplifiers BCE and ACE with a precision higher than the one attainable if both clock signal were delivered directly by the clock generator of the module. 
     FIG. 4 shows the devices and the circuits mounted on a card. Reference letter RUI indicate the four rows of eight integrated units each for information bits, and RUC indicate the four units for check bits. The data input terminals of the integrated units of each column are parallel connected to one of the eight leads ID 0  to ID 7  to which the eight information bits to be written in the memory are applied; the data output terminals of the units of each column are similarly parallel connected to one of the eight leads UD 0  to UD 7 , on which the eight read out information bits are available. The check bits at the input and at the output are respectively carried by leads IC and UC connected to the data input and data output terminals of the integrated units RUC 0  to RUC 3 . CAR denotes the aggregated four groups of controlled amplifiers CAR 0  to CAR 3  of FIG. 2. They provide the ability to transfer the clock signals CP&#39;, CE&#39;, CWI&#39; and CWC&#39;  on the row selected by the row selection line SAR 0  to SAR 3  on which appears a signal ONE. 
     Each row selecting lead is connected respectively to the output lead of AND gate (PAD 0  to PAD 3 ) whose first input is connected to the row selection terminal (SAR&#39; 0  to SAR&#39; 3 ), to which the signal indicating the selected row is applied. The second inputs of these gates are connected in common to the output of a submodule selector SSM, having six inputs to which the direct and inverse values of the three submodule selection bits BA 2 , BA 3 , and BA 4  are applied. The submolule selector SSM enables the PAD gates only when a specific pattern of direct and inverse values of these three bits, forming the submodule address, is applied thereto, and, in addition, also when all six inputs are at value ONE. In this case, all the connected submodules are enabled. 
     The outputs of the four gates PAD 0  to PAD 3  are connected to the inputs of an OR gate POR whose output, on the one hand, enables the data output amplifiers AUD 0  to AUD 7  and AUC (as explained further on), and, on the other hand, connected to an output terminal ECD, producing a signal (called the ECO signal) which confirms to the central processor that the selected submodule is connected and operating. 
     The eight data inputs AID 0  to AID 7  amplify the input data and transform them from TTL to MOS standard. Their outputs are parallel connected to the data input terminals of the four integrated units of each column. The eight data output amplifiers AUD 0  to AUD 7  have their inputs connected to all the data output terminals of the four integrated units of each column; they amplify the data output signals and transform them from MOS to TTL standard. The same functions are performed, with respect to the input and output check bits, respectively, by the input amplifier AIC and the output amplifier AUC. 
     The ten address bits BA 7  to BA 16 , which select a single cell within each integrated unit, are amplified and transformed from TTL to MOS standard by the ten address amplifiers AIA 0  to AIA 9 . 
     In the example under consideration, the refreshing of the memory is obtained by means of 32 refreshing cycles effected in succession; each of the cycles provides for refreshing one of the 32 rows of all the connected integrated units for the whole memory capacity installed. During each cycle, the five row address bits BA 12  to BA 16  are replaced by five bits generated by a counter, which generates, in sequence, the 32 address codes for the 32 rows. A refreshing logic circuit, shown in FIG. 5, may receive from the central processor the following signals: a STR start signal, indicating that the central processor requires that a memory cycle be effected; a RCC refreshing signal, indicating that the requested cycle must be a refreshing cycle; a RST reset signal, which is intended for suspending the operation of the central processor and for resetting to zero all the registers of the computer. In this case, as the memory content must not get lost, the refreshing logic circuit generates a periodical internal start signal, which is provided to carry on the refreshing operation even in the presence of the reset signal. 
     The refreshing logic circuit may send to the central processor either one or the other of two interrupt signals IBP and IAP, requesting the stopping of every other operation of the central processor and the emission of the ATR and RCC signals required for effecting a refreshing cycle. The first interrupt signal IBP has a relatively low priority level and may be disregarded if the central processor is busy with higher priority operations (such as disk operations). The high priority interrupt signal IAP is sent out if the first interrupt signal has not been responded to, that is, if the requested signals have not been emitted. Since interrupt signal IAP has absolute highest priority, it causes these signals to be unconditionally emitted. 
     The refreshing logic circuit is mounted on each memory module for 32,000 words. However, if more than one of these modules are installed, the refreshing operations are controlled by a single one of these circuits, to prevent an excess of refreshing requests. 
     The 32 refreshing cycles, continuing approximately 1 microsecond each, are not effected in immediate succession at the end of the allowed maximum interval of 2 milliseconds as required for preventing any loss of information, but at intervals of approximately 31 microseconds; therefore each row is refreshed, in normal operation, after about one millisecond. 
     However, if the low priority interrupt signal has not been responded to, during the following 31 microsecond interval the high priority interrupt request is sent out; and this signal is responded to without fail. Therefore, in the most unfavorable case, when the high priority signal must always be sent, the memory is refreshed every 2 milliseconds approximately, or more precisely, every 32 times 62 microseconds (1,984 microseconds or 1.984 milliseconds). 
     The refreshing logic circuit, as shown by the wiring diagram of FIG. 5, comprises an asymmetric wave generator, including two one-shot circuits 203 and 204, having different operating times. The one-shot 203, for instance, has, at rest conditions, its output at ZERO level, goes over to ONE level when a falling front (a transition from ONE to ZERO) is applied at its input, and returns to the rest condition after 27 microseconds. The falling front on the output lead, applied to the input of the one-shot 204, brings its output to ONE; this output returns to ZERO after 4 microseconds. This latter falling front, in turn, is applied to the input of the one-shot 203 through an OR gate 205, bringing its output to ONE, and the process is repeated indefinitely. At the output of the one-shot 203 there is a sequence of square wave signals of level ONE, during 27 microseconds, separated by intervals of level ZERO during 4 microseconds: the complete cycle has a period of 31 microseconds. 
     The output of the one-shot 203 is directly connected to the clock input C of a flip-flop 212, and, through the inverter 211, to the clock input C of a second flip-flop 213. These flip-flops are of the so-called J-K type and are designed to be controlled by a falling front (from ONE to ZERO) applied to the clock input C. In response to this front, the direct output of the flip-flop goes over to level ONE, if at input J there is applied a level ONE, and at input K a level ZERO. If at both inputs a level ZERO is applied, the output remains at ZERO. There is, in addition, a reset input R which resets the flip-flop to rest conditions (ZERO level) when a signal ONE is applied thereto. 
     The input J of the flip-flop 213 is permanently kept at level ONE, whereas the input J of flip-flop 212 is connected to the output U of flip-flop 213. The inputs K of both flip-flops are permanently at ZERO. The direct outputs U of flip-flops 213 and 212 provide, respectively, the low priority (IBP) and the high priority (IAP) interrupt requests. 
     Both reset inputs R are connected to the output of the OR gate 214, having an input connected to the RST signal terminal and the other input to the output of an AND gate 216 having its inputs connected to the STR and RCC signal inputs. 
     The start signal STR emitted by the central processor is applied, through an OR gate 202, to a clock generator 201 (not described, but of known type), which generates the clock signals needed for the operation of the memory, that is, the CP and CE signals, and, in case of write operations, the signal CW, in response to the start signal. The signal CW is emitted or not, according to the value of the signal SRW sent by the central processor, that is according to whether the memory cycle must be a write cycle or a read or refreshing cycle. The start signal STR may be emitted by the central processor either independently, according to the requirements of the data processing under way, or in response to an interrupt signal of low or high priority IBP or IAP, requesting a refresh cycle. In this case, the start signal is accompanied by a refresh signal RCC, which appears at the same time as STR, but is longer and encompasses the latter. Therefore, when a start signal STR and a refresh signal RCC reach the refreshing logic circuit, a signal STRC (refresh start signal) appears at the output of the AND gate 216; it is identical to the signal STR but is conditioned by the presence of the refresh signal RCC. 
     The reset signal RST, in general, has the functions of resetting to zero all registers and of interrupting the operation of the central processor. As this signal may last more than two milliseconds, and the memory contents must not get lost, an internal start signal STI is generated, during the reset signal, by the one-shot circuit 210, which has its input connected to the output of the AND gate 209 controlled by the RST signal. The other input of the gate 209 is connected to the output of the one-shot 203. When the signal RST is at level ONE, the falling fronts of the oscillator formed by the one-shots 203 and 204 trigger the one-shot 210, which, therefore, emits every 31 microseconds, a signal of suitable length replacing the start signal. This is applied to an input of the OR gate 215, to one input of the OR gate 202, and, thereby, to the input of the clock generator 201. 
     The output of the one-shot 203 is also applied to the input of the one-shot 206 having an operation time longer than the 31 microsecond period, for instance, an operation time of 100 microseconds. This one-shot, therefore, is set in &#34;up&#34; condition by the first falling front at the output of the one-shot 203 and remains in this condition as long as the oscillator is operating, because the falling fronts therefrom, which follow at 31 microsecond intervals, retrigger it, and do not allow it to go down to rest condition. 
     The reset signal is applied to an input of the AND gate 208 having its other input connected through the inverter 207 to the output of the one-shot 206. The output of the AND gate 208 is connected through the OR gate 205, to the input of the one-shot 203. Therefore, when the computer is being energized, and all one-shots 203, 204, and 206 are in rest condition, a reset signal, which is automatically emitted, triggers the one-shot 203 and starts the oscillator: the one-shot 206 goes to &#34;up&#34; condition, and its output signal, inverted by the inverter 207, inhibits the AND gate 208 preventing any other reset signal from possibly disturbing its operation. Usually, the oscillator 203-204 is steadily operating: if, for any reason, it stops, the sending of the reset signals permits it to resume its operation. 
     The internal start signal STI and the refresh start signal STRC are mutually exclusive. They are applied by the OR gate 215 to the one-shot 225 which delivers at its output a prolonged start signal having a duration somewhat longer than a memory cycle. This signal is applied to a row addressing circuit 221, which comprises a counter 220 which counts the pulses applied at its input, and gives out, at its five outputs, an ordered sequence of 32 five-bit codes. It comprises also two sets of AND gates 219 and 217, an inverter 218 and a set of OR gates 222. The prolonged start signal lets the counter advance a step at a time, and alternatively, when it is at ONE value, enables the set of gates 219 and inhibits the set of gates 217; thus, the five-bit code generated by the counter 220 is applied through these gates and the set of OR gates 222 to the row address leads AR. Alternatively, when it is at ZERO value, the gates 219 are inhibited, the gates 217 are enabled, and therefore the five row addressing bits BA 12  to BA 16 , emitted by the central processor, and applied to the inputs of the set of gates 217, may reach the row addressing leads AR through the OR gates 222. Summing up, the row addressing leads AR, which deliver the row addressing code to all the integrated units, are normally fed by the five-bit row address emitted by the central processor, but, during the refreshing cycles are fed by the addresses generated by the counter 220. 
     The operation of the refreshing logic circuit is as follows. The oscillator 203-204 delivers the square waves of 31 microsecond period: the rising fronts which take place at the beginning of the period are applied, through the inverter 211, to the clock input of the flip-flop 213 and, as the J input of the same is always at ONE level, they cause the emission of the low-priority interrupt signals IBP. In normal operation, the central processor answers this request by emitting the STR and RCC signals which, through the gates 216 and 214, reset the flip-flop 213. Twenty seven microseconds after the beginning of the period, the oscillator emits a falling front which, applied to the clock input of flip-flop 212, sets it to &#34;up&#34; condition; but, as the flip-flop 213 has already been reset, its output applies to the J input of flip-flop 212 a ZERO value and the output of 212 remains therefore at ZERO. No high priority request signal IAP is emitted. 
     On the other hand, if the low priority signal has failed to cause the emission of the signals STR and RCC, the flip-flop 213 remains in the &#34;up&#34; condition, its output remains at level ONE, and the falling front, applied to the clock input of flip-flop 212 causes its output to go over to ONE, producing the high priority request signal IAP. This causes the unconditioned emission of the signals STR and RCC. In any case, the emission of these signals causes the emission of the prolonged start signal which, as already explained, lets the counter 220 step-on, inhibits the gates 217, and enables the gates 219, thus replacing the address delivered by the central processor by the address generated by the counter 220. This process is repeated 32 times per millisecond, at intervals which may be 31 or 62 microseconds until after 32 refreshing cycles, each one lasting one microsecond, all rows of the integrated units of the memory have been refreshed. 
     During the reset signal, the AND gate 209 is enabled; and the falling fronts generated by the wave generator, trigger the one-shot 210 every 31 microseconds which emits the internal start signal STI. This is transmitted through the gate 215 to the one-shot 225 and produces the same effects as the STR signal. 
     FIG. 6 is the schematic block diagram of the general layout of a memory module and its interface with the central processor. As stated above, each module comprises up to 8 submodules, and each submodule comprises two printed circuit cards. In FIG. 6, the reference numerals 1 and 2 indicate respectively the first and the second card of the first submodule, 3 and 4 those of the second submodule, and so on; 15 and 16 indicate the first and second card of the last submodule. 
     The words recorded in the memory are made up of 16 information bits, consisting in two 8-bit half-words (bytes). The first half-word comprises the eight information bits BD 0  to BD 7  and is checked by the check bit BC 1  ; the second half-word comprises the eight information bits BD 8  to BD 15  and is checked by the check bit BC 2 . In each submodule, the information bits of the first byte and the check bit of the second byte are recorded on the first card; and the information bits of the second byte and the check bit of the first byte are recorded on the second card. 
     FIG. 6 indicates by reference numeral 21 a terminal set of data registers connected to the central processor by a bidirectional channel BD foor data interchange. The register set 21 is connected to the different parts of the memory by the following connections: a first half-channel BD 1  carrying the data of the first byte, the lead BC 1  for the check bit of the first byte, which is connected to second cards of the submodules, the second half-channel BD 2  for the data of the second byte, the lead BC 2  for the check bit of the second byte, connected to the first cards of the submodules. The half channels BD 1  and BD 2  pass through the switching device 22, controlled by a signal SSB from the central processor, and by the 18th address bit BA 17 . Then the signal SSB is at ZERO, the first and the second bytes are written or read out, at the same time, respectively, at the first and second card of the addressed submodule. When the signal SSB, which has the meaning &#34;write single byte&#34;, is at ONE, the reading takes place at the same time for both bytes from both cards; but the writing is carried out for the first byte only; and this first byte is written either on the first card or on the second card according to whether the address bit BA 17  is ONE or ZERO. Accordingly, the write clocks for the information bits of each card are controlled by the signal SSB and the bit BA 17 , in a way not shown in the drawing and not described here in detail, independently from the write clocks of the check bits of the same card. A detailed description of this feature is irrelevant to an understanding of the invention, such feature being readily implemented by those skilled in the art. 
     Reference numeral 26 indicates the address register, connected to the central processor by an unidirectional 16-line channel BA. The full address of each memory position comprises 17 bits: the first two, BA 0  and BA 1 , select the module in the central processor and are not sent to the selected module. The channel BA therefore carries the remaining 15 address bits BA 2  to BA 16 , the card addressing bit for single byte writing BA 17 , and a check bit. As aforesaid, the bits BA 2 , BA 3 , and BA 4  are sent through the channel 40 to the circuit 24 which generates the direct and inverted values of these bits, which are sent by channel 41 to the submodule selectors of each submodule card. The circuit 24 is controlled by the signal CRC generated by the refreshing logic circuit and may bring all the six leads of channel 41 to value ONE, for enabling all submodules during refreshing cycles. 
     Bits BA 5  and BA 6  are decoded by decoder 25, controlled by the signal CEC, and produce four signals for selecting the row on all cards which are carried by the channel 42. They may all be brought to the value ONE during the refreshing cycle. 
     Bits BA 7  to BA 11 , transmitted by channel 44, select the cell column of the integrated units. The bits BA 12  to BA 16  select the cell row and may be replaced by the row address generated by the counter 220 of FIG. 5, being part of the device 221 controlled by the prolonged start signal as explained before. As aforesaid, the bit B 17  addresses the first or the second card of the submodules during the single byte writing. 
     The reference numeral 23 indicates a circuit which is substantially the same as that of FIG. 5, comprising the clock generator and the refreshing logic circuit. It receives the signals indicated therein from the central processor and emits, in addition to the already indicated signals, a CRC signal (practically coincident with the prolonged start signal) for controlling the devices 24 and 25 and a read/write signal CRW, depending on the SRW signal, for controlling the switching from sending to receiving of the set of data registers 21. The clock signals CP, CE and CW are sent to the submodules by the channel 43. 
     The data read out from the memory submodules are transmitted by the channels 30 and 31 to a diagnostic device 32, which, being irrelevant to an understanding of the invention is not described herein. The ECD signal from each card is sent separately to the diagnostic device, and all of them are sent, on a single lead ECD to the central processor. The diagnostic device may send to the central processor an error signal ERR, and the central processor may send to the module a signal SOD causing the module to operate in a diagnostic mode in place of the normal mode; a signal SSJ for enabling a predetermined submodule to take over the particular function of a reserve or &#34;jolly&#34; submodule, in the case of memory reconfiguration; and a signal SRE for resetting to ZERO all the output registers facing the central processor, before beginning a new data transmission. Lastly, a signal SMP is provided for signalling to the central processor the presence and the operating condition of the module. 
     While a preferred embodiment of the invention has been shown and described, it will be apparent to those skilled in the art that changes can be made without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims.