Patent Publication Number: US-7212046-B2

Title: Power-up signal generating apparatus

Description:
FIELD OF THE INVENTION 
   The present invention relates to semiconductor design technique; and, more particularly, to a power-up signal generating apparatus. 
   BACKGROUND OF THE INVENTION 
   Generally, a semiconductor memory device starts its operation after a power voltage level rises up to a certain level instead of starting in response to the level of the power voltage immediately after the power voltage is externally supplied. For this reason, the semiconductor memory device usually includes a power-up circuit. 
   The power-up circuit prohibits the entire memory device from damaged due to latch-up when the internal circuit of the device is operated before the power voltage is stabilized after the power voltage is supplied externally so that chip level reliability can be improved. Such a power-up circuit detects the rise of the power voltage that is supplied externally when the power voltage is supplied initially so as to output a power-up signal in ‘low’ state till a certain level of the power voltage and then make a transition of the power-up signal to ‘high’ state after the power voltage is stabilized over the certain level. On the contrary, when the power voltage falls, the power-up circuit outputs the power-up signal in ‘high’ state till the certain level of the power voltage and then outputs the power-up signal in ‘low’ state again after the power voltage level falls down under the certain level. The power-up signal is outputted as ‘high’ after the power voltage is stabilized and operated independently in a unit of pipe within the memory inner circuit to be used mostly for circuits which require initialization operation. 
     FIG. 1  is a circuit diagram of a power-up signal generating apparatus in prior art. 
   Referring to  FIG. 1 , the power-up signal generating apparatus comprises a bias signal generating unit  10  for generating a bias signal bias, a sensing level adjusting unit  11  for sensing rising of a power supply voltage VDD to adjust an voltage level of an output node ND 2 , and an output signal forming unit  12  for outputting the voltage on the output node ND 2  as a power-up signal pwrup. 
   The bias signal generating unit  10  includes a PMOS transistor PM 1  having a ground voltage VSS as its gate input and a source-drain path between the power supply voltage VDD and a node ND 1 , and an NMOS transistor NM 1  having a drain coupled to its gate and a drain-source path between the node ND 1  and the ground voltage VSS to output the voltage on the node ND 1  as the bias signal bias. 
   When the power supply voltage VDD exceeds the threshold voltage Vt of the NMOS transistor NM 1  while rising, the NMOS transistor NM 1  is turned on so as to output the bias signal bias having a certain level. 
   Further, the sensing level adjusting unit  11  includes two serially coupled PMOS transistors PM 2 , PM 3  between the power supply voltage VDD and the output node ND 2 , each transistor having a drain coupled to the corresponding gate. 
   The output signal forming unit  12  includes an NMOS transistor NM 2  having the bias signal as its gate input and a drain-source path between the output node ND 2  and the ground voltage VSS, an inverter I 1  for inverting the output node ND 2 , a PMOS transistor PM 4  having the output signal of the inverter I 1  as its gate input and a source-drain path between the power supply voltage VDD and the output node ND 2 , and an inverter I 2  for inverting the output of the inverter I 1  to output as the power-up signal pwrup 
   Next, it will be described for the operation of the conventional power-up signal generating apparatus. 
   First, as the power supply voltage VDD rises up to lead rising of the voltage level on the node ND 1 , the NMOS transistor NM 1  becomes active so that the bias signal generating unit  10  outputs the bias signal bias having a stable level. In turn, the NMOS transistor NM 2  having the bias signal bias as its gate input is turned on so that the output node ND 2  can has a certain portion of the power supply voltage VDD that is obtained by voltage dividing with the PMOS transistors PM 2 , PM 3  in the sensing level adjusting unit  11  and the voltage level on the output node ND 2  rises up due to the rise of the power supply voltage VDD. The inverter  11  inverts the voltage on the output node ND 2 . Because the PMOS transistor PM 4  that has the output of the inverter I 1  as its gate input inputs the power supply voltage VDD to the output node ND 2  in response to falling of the output of the inverter I 1  so as to increase the voltage level on the output node ND 2  more rapidly. The inverter I 2  inverts the output signal of the inverter I 1  to output it as the power-up signal pwrup. 
   For the reference, the sensing level adjusting unit  11  makes the voltage level on the output node ND 2  have the certain portion of the power supply voltage VDD so as to adjust the active point of the power-up signal by varying that amount of the portion. Further, the output signal forming unit  12  forms the power-up signal pwrup by using the inverter chain I 1 , I 2  because the voltage level on the output node ND 2  comes from voltage dividing of the power supply voltage VDD. 
   On the other hand, the conventional power-up signal generating apparatus is sensitive to surrounding temperature around the semiconductor, which will be described as follows. 
     FIG. 2  shows a waveform diagram for operation of a circuit in  FIG. 1 , which presents the active point of the power-up signal versus temperature. 
   First, X axis depicts time and Y axis depicts voltage. The waveform of ‘b’ shows the case when the surrounding temperature around the semiconductor is room temperature, ‘a’ shows the case when the surrounding temperature around the semiconductor is higher than room temperature, and ‘c’ shows the case when the surrounding temperature around the semiconductor is lower than room temperature. 
   Referring to  FIG. 2 , it can be seen that the active point of the power-up signal pwrup depends on the surrounding temperature around the semiconductor. That is, in the case of ‘a’ when the surrounding temperature is higher than room temperature, the power-up signal pwrup becomes active at lower voltage level than in the case of ‘b’. On the contrary, in the case of ‘c’, the power-up signal pwrup becomes active at a higher voltage level than in the case of ‘b’. 
   As the surrounding temperature around the semiconductor rises, the threshold voltage Vt of the MOS transistor becomes lower so that the NMOS transistor NM 1  can be turned on before the power supply voltage VDD rises up enough to make the voltage level of the bias signal bias becomes lower. Accordingly, the turn-on resistance of the NMOS transistor NM 2  that is controlled by the bias signal bias rises up and, in turn, the voltage on the output node ND 2  is increased so that the power-up signal pwrup can be active before the power supply voltage VDD rises up enough. 
   On the contrary, when the surrounding temperature falls down, the threshold voltage Vt of the NMOS transistor NM 1  rises up so that the voltage level of the bias signal bias becomes higher. Accordingly, the turn-on resistance of the NMOS transistor NM 2  is reduced and, in turn, the voltage level on the output node ND  2  falls down so that the power-up signal becomes active at higher power supply voltage VDD. 
   As described above, the conventional power-up signal generating apparatus is so sensitive to the surrounding temperature around the semiconductor, which makes the power-up signal pwrup active at irregular levels of the power supply voltage VDD and, as a result, leads failure of initialization operation of a chip and deterioration of chip reliability. 
   When the power-up signal becomes active before the power supply voltage VDD rises up to a certain level due to rising of the surrounding temperature, chip initialization is failed. On the other hand, when the activation of the power-up signal is lagged due to falling of the surrounding temperature, the semiconductor device operates abnormally in a low voltage region. 
   Similarly, such phenomena as described above can be seen in case of process changes. 
   SUMMARY OF THE INVENTION 
   It is, therefore, a primary object of the present invention to provide a power-up signal generating apparatus for improving chip reliability. 
   In accordance with the present invention, there is provided a power-up signal generating apparatus which comprises a reference voltage generating unit for generating a reference voltage, a bias level adjusting unit receiving the reference voltage as its input for controlling a voltage level of a bias signal to have a constant level, a bias signal generating unit for generating the bias signal under control of the bias level adjusting unit; and a signal outputting unit for outputting a power-up signal depending on the voltage level of the bias signal. 

   
     BRIEF DESCRIPTION OF THE DRAWING 
     The above and other objects and features of the present invention will become apparent from the following description of preferred embodiments given in conjunction with the accompanying drawings, in which: 
       FIG. 1  provides a circuit diagram of a power-up signal generating apparatus in prior art; 
       FIG. 2  shows a waveform diagram for operation of a circuit in  FIG. 1 ; and 
       FIG. 3  represents a circuit diagram of a power-up signal generating apparatus in accordance with one embodiment of the present invention. 
   

   DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
   Hereinafter, with reference to the accompanying drawings, a preferred embodiment of the present invention will be explained in detail. 
   In the present invention, a voltage level of a bias signal is increased when temperature rises up to reduce increase of resistance of an NMOS transistor due to rising of temperature so as to reduce impact of temperature on the power-up signal. Further, the voltage level of the bias signal is reduced when temperature falls down to reduce reduction of the resistance of the NMOS transistor due to falling of temperature. As such, the active point of the power-up signal can be adjusted. 
     FIG. 3  represents a circuit diagram of a power-up signal generating apparatus in accordance with one embodiment of the present invention. 
   Referring to  FIG. 3 , the power-up signal generating apparatus comprises a reference voltage generating unit  30  for generating a reference voltage Vref, a current supplying unit  31  for receiving the reference voltage Vref and a portion of a voltage on a node ND 1  of a bias signal generating unit  10  to supply a current to the node ND 1 , a current sinking unit  32  for receiving the reference voltage Vref and a portion of the voltage on the node ND 1  to sink the current from the node ND 1 , the bias signal generating unit  10  for generating a bias signal bias under control of the current supplying unit  31  and the current sinking unit  32 , and a sensing level adjusting unit  11  for adjusting a voltage level of an output node ND 2  for sensing rising of the power supply voltage VDD, and output signal generating unit  12  for outputting the voltage on the output node ND 2  as a power-up signal pwrup. 
   It can be noticed that the power-up signal generating apparatus according to the present invention as shown in  FIG. 3  further comprises the reference voltage generating unit  30 , the current supplying unit  31  and the current sinking unit  32  compared to the conventional power-up signal generating apparatus as shown in  FIG. 1 . 
   It will be described for the inner circuit of each block and its operation. 
   First, the current supplying unit  31  includes a supply feedback signal generating unit  312  for outputting the portion of the voltage on the node ND 1  as a feedback signal fd 1 , a supply comparing unit  310  for comparing the reference voltage Vref to the feedback signal fd 1  to output a control signal ctr 1 , and a supply driver  311  for supplying the current to the node ND 1  in response to the control signal ctr 1 . 
   Further, the supply comparing unit  310  of the current supplying unit  31  includes an NMOS transistor NM 3  having the reference voltage Vref as its gate input and a drain-source path between a node a and a ground voltage VSS to output the voltage on the node a as the control signal ctr 1 , an NMOS transistor NM 4  having the feedback signal fd 1  as its gate input and a drain-source path between a node b and the ground voltage VSS, a PMOS transistor PM 6  having a drain coupled to its gate input and a source-drain path between the power supply voltage VDD and the node b, and a PMOS transistor PM 5  having the voltage on the gate of the PMOS transistor PM 6  as its gate input and a source-drain path between the power supply voltage VDD and the node a. The supply driver  311  includes a PMOS transistor PM 7  having the control signal ctr 1  as its gate input and a source-drain path between the power supply voltage VDD and a node c. The supply feedback signal generating unit  312  includes a resistor R 1  between the node c and a node d, a PMOS transistor PM 8  having a drain coupled to its gate input and a source-drain path between the node d and the ground voltage VSS to output the voltage on the node d as the feedback signal fd 1 . 
   Next, the current sinking unit  32  includes a sink feedback generating unit  322  for outputting the portion of the voltage on the node ND 1  as a feedback signal fd 2 , a sink comparing unit  320  for comparing the reference voltage Vref to the feedback signal fd 2  to output a control signal ctr 2 , and a sink driver  321  to sink the current from the node ND 1  in response to the control signal ctr 2 . 
   The current comparing unit  320  of the current sinking unit  32  includes a PMOS transistor PM 9  having the reference voltage Vref as its gate input and a source-drain path between the power supply voltage VDD and a node e to output the voltage on the node e as the control signal ctr 2 , a PMOS transistor PM 10  having the feedback signal fd 2  as its gate input and a source-drain path between the power supply voltage VDD and a node f, an NMOS transistor NM 6  having a drain f coupled to its gate input and a drain-source path between the node f and the ground voltage VSS, and an NMOS transistor NM 5  having the voltage on the gate of the NMOS transistor NM 6  as its gate input and a drain-source path between the node e and the ground voltage VSS. The sink feedback signal generating unit  322  includes a resistor R 2  between the power supply voltage VDD and a node g to output the voltage on the node g as the feedback signal fd 2 , and a PMOS transistor PM 11  having a drain coupled to its gate input and a source-drain path between the node g and the node h. The sink driver  321  includes an NMOS transistor NM 7  having the control signal ctr 2  as its gate input and a drain-source path between the node h and the ground voltage VSS. 
   For the reference, the node c and the node h are the same node as the node ND 1 . The reference voltage generating unit  30  is formed by a BJT(Bipolar Junction Transistor) so as to supply the reference voltage Vref having a constant level regardless of the surrounding temperature. 
   Table 1 shows change on each node in the power-up signal generating apparatus versus temperature. 
   
     
       
         
             
             
             
             
             
           
             
                 
               TABLE 1 
             
           
          
             
                 
                 
             
             
                 
               Current supplying unit 
               Current sinking unit 
                 
               Resistance 
             
          
         
         
             
             
             
             
             
             
             
             
             
             
          
             
               Temperature 
               Vfd1 
               Vctr1 
               i PM7   
               Vfd2 
               Vctr2 
               i NM7   
               Vbias 
               PM2, PM3 
               NM2 
             
             
                 
             
             
               increase 
               dec 
               dec 
               inc 
               dec 
               dec 
               dec 
               inc 
               dec 
               dec 
             
             
               (inc) 
             
             
               decrease 
               inc 
               inc 
               dec 
               inc 
               inc 
               inc 
               dec 
               inc 
               inc 
             
             
               (dec) 
             
             
                 
             
          
         
       
     
   
   Referring to Table 1, it will be described for the operation of the power-up signal generating apparatus in accordance with one embodiment of the present invention. 
   When the voltage levels of the reference voltage Vref and the feedback signals fd 1 , fd 2  are equal to each other, the current supplying unit  31  and the current sinking unit  32  are deactivated so that the bias signal is outputted having a certain level by the NMOS transistor NM 2 . 
   First, it will be described for the operation when the surrounding temperature around the semiconductor device is higher than room temperature. 
   Due to rising of the surrounding temperature, the level of the threshold voltage Vt of the MOS transistor falls down so that the voltage levels of the feedback signals fd 1 , fd 2  fall under the reference voltage Vref. Each of the comparing units  310 ,  320  for comparing the feedback signals fd 1 , fd 2  to the reference voltage, respectively, decrease the voltage levels of the control signals ctr 1 , ctr 2 . In turn, the supply driver PM 7  under control of the control signal ctr 1  responds to the control signal ctr 1  to supply more amount of the current i PM7  to the node ND 1 , while the sink driver NM 7  under control of the control signal ctr 2  sinks less amount of the current i NM7  from the node ND 1 . Because more amount of the current i PM7  is supplied to the node ND 1  by the supply driver PM 7  while less amount of the current i NM7  is sunk from the node ND 1  by the sink driver NM 7 , the voltage level on the node ND 1  is increased, accordingly. That is, the voltage level of the bias signal rises. Accordingly, increase of the turn-on resistance of the NMOS transistor NM 2  having the bias signal as its gate input is reduced to activate the power-up signal pwrup at a certain level. 
   Further, when the surrounding temperature is lower than room temperature, the level of the threshold voltage Vt of the MOS transistor rises up so that the voltage levels of the feedback signals fd 1 , fd 2  are made to be higher than the reference voltage Vref. The comparing units  310 ,  320  for comparing the feedback signals fd 1 , fd 2  to the reference voltage, respectively, increases the voltage levels Vctr 1 , Vctr 2  of the control signals ctr 1 , ctr 2 . In turn, the supply driver  311  under control of the control signal ctr 1  supplies less amount of the current i PM7  to the node ND 1 , while the sink driver NM 7  under control of the control signal ctr 2  sinks more amount of the current i NM7  from the node ND 1 . Accordingly, the voltage level on the node ND 1  is decreased. That is, the voltage level of the bias signal falls down. 
   Accordingly, the turn-on resistance of the NMOS transistor NM 2 , which fell down due to the surrounding temperature, is increased. 
   For the reference, when temperature rises up, the turn-on resistance values of the PMOS transistors PM 2 , PM 3  in the sensing level adjusting unit  11  are decreased due to the level variation of the threshold voltage Vt of the MOS transistor because of change of the surrounding temperature. On the contrary, when temperature falls down, the turn-on resistance values of the PMOS transistors PM 2 , PM 3  are increased. 
   As described above, the power-up generating apparatus in accordance with one embodiment of the present invention generates the reference voltage Vref that is not impacted by the surrounding temperature variation and adjusts the voltage level Vbias of the bias signal by controlling the amount of the current i PM7 , i NM7  that are supplied to the node ND 1  through the current supplying unit  31  and the current sinking unit  32  depending on the surrounding temperature. Therefore, the power-up signal pwrup is activated at a certain level of the power supply voltage VDD by adjusting the turn-on resistance value of the NMOS transistor NM 2  so that the chip reliability can be improved. 
   The present application contains subject matter related to Korean patent application No. 2003-76906, filed in the Korean Patent Office on Oct. 31, 2003, the entire contents of which being incorporated herein by reference. 
   Although the preferred embodiments of the invention have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims.