Patent Publication Number: US-2022230682-A1

Title: Phase change memory device, system including the memory device, and method for operating the memory device

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is a continuation of U.S. patent application Ser. No. 17/119,979, filed Dec. 11, 2020, which application claims the benefit of Italian Application No. 102019000024253, filed on Dec. 17, 2019, which applications are hereby incorporated herein by reference. 
    
    
     TECHNICAL FIELD 
     The present invention relates to a phase-change memory device, to a system that includes the phase-change memory device, and to a method for operating the phase-change memory device. 
     BACKGROUND 
     Non-volatile phase-change memories (PCMs) are known, in which for storing information the characteristics of materials that present the property of switching between phases that have different electrical characteristics are exploited. For instance, such materials are able to switch between a disorderly, amorphous phase and an orderly, crystalline or polycrystalline phase, and the two phases are associated with resistivities having considerably different values, and consequently with different values of a datum stored. For instance, the elements of Group VI of the Periodic Table, such as tellurium (Te), selenium (Se), or antimony (Sb), referred to as chalcogenides or chalcogenic materials, may advantageously be used for the production of phase-change memory cells. Phase-changes are obtained by locally increasing the temperature of the cells of chalcogenic material, through resistive electrodes (generally known as heaters) arranged in contact with respective regions of chalcogenic material. Selection devices (for example, MOSFETs) are connected to the heaters and enable passage of an electric programming current through a respective heater. The electric current, by the Joule effect, generates the temperatures necessary for phase-change. During reading, the state of the chalcogenic material is detected by applying a voltage that is sufficiently low as not to cause a considerable heating, and then by reading the value of the current that flows in the cell. Given that the current is proportional to the conductivity of the chalcogenic material, it is possible to determine in which state the material is, and therefore to arrive at the datum stored in the memory cell. 
     SUMMARY 
     In a known way, non-volatile memories comprise an array of memory cells organised in rows (wordlines) and columns (bitlines). Each memory cell is constituted, in the case of PCMs, by a phase-change storage element and a selector transistor, connected in series. A column decoder and a row decoder enable selection, on the basis of address logic signals received at input and more or less complex decoding schemes, of the memory cells, and in particular of the corresponding wordline and bitline each time addressed. 
     The column decoder comprises a plurality of analog selection switches (implemented by transistors), which receive at their respective control terminals the address signals. The selection switches are organized according to a tree structure in hierarchical levels, and their number in each hierarchical level is linked to the organization and size of the memory array. The selection switches, when enabled, make it possible to bring the bitline selected to a definite value of voltage and/or current, according to the operations that are to be implemented. In particular, a current path is created between a programming stage or a reading stage and the bitline selected. The current path is defined by the series of a certain number of selection switches. In a known way, sense amplifiers carry out reading of the data stored in the memory cells, comparing the current that flows in the memory cell selected (or an electrical quantity correlated thereto) with a reference current that flows in a reference cell (so-called double-ended reading) or else with a reference current supplied by a reference-current generator (so-called single-ended reading). Single-ended reading is typically used during verification that programming of the cell has occurred or during testing, whereas double-ended reading is typically used during normal use of the memory to read the logic datum stored in the cell that is to be read. 
     To carry out single-ended reading, an input of the sense amplifier receives the current of the memory cell that is to be read, while the other input of the sense amplifier receives the reference current supplied by the reference-current generator. 
     In both of the modalities referred to it is expedient to guarantee, as far as possible, for the sense amplifier similar working conditions, with particular attention paid to the capacitive load at the two inputs thereof. This need, however, is unlikely to be met in single-ended reading systems in so far as, in a way in itself evident, the capacitance associated to a reference-current generator used in single-ended reading is different from the capacitance that derives from the bitline used for carrying the current signal of the cell that is to be read. 
     In addition, it may be noted that the effective value of capacitance associated to the bitline is affected by a series of factors that are unforeseeable, such as the manufacturing process spread. Consequently, fluctuations may arise that do not render convenient the use of a pre-set capacitance associated to the reference-current generator. 
     To overcome these drawbacks, it is known to connect the input of the sense amplifier that receives the reference current also to a de-selected memory cell (i.e., a cell that is turned off), through the respective bitlines. In this way, it is possible to guarantee a comparable capacitive load at the two inputs of the sense amplifier both in the operation of single-ended reading (reading of a logic datum stored in a memory cell by comparison with a current reference) and in the operation of double-ended reading (reading of a logic datum stored in a memory cell by comparison with a further memory cell). 
     In particular, in the case of single-ended reading of a memory cell selected via the corresponding wordline and coupled to a local bitline of a memory sector, the sense amplifier will have, on a first input thereof, the capacitance associated to the local bitline plus the capacitance associated to a first main bitline to which the local bitline is connected. In addition, the sense amplifier will receive, on a second input thereof, the reference current used for the comparison but also a capacitance associated to a further main bitline, which, during this operation, is decoupled from local bitlines. In other words, the sense amplifier receives capacitive loads of a similar amount on both of the inputs. 
     Illustrated schematically in  FIG. 1  and designated as a whole by the reference number  1  is a portion of a non-volatile memory device, in particular of a PCM type, limitedly to just the parts necessary for an understanding of the present disclosure. 
     In particular, the non-volatile memory device  1  comprises a memory array  2 , constituted by a plurality of first memory cells  3  (each including a phase-change region  3   a  and a local selection transistor  3   b ), and by a plurality of second memory cells  3 ′ (each including a phase-change region  3   a ′ and a local selection transistor  3   b ′), which can be selected by local wordlines WL and local bitlines BL. In a way in itself known, the second memory cells  3 ′ correspond, as regards number and manufacturing characteristics, to the first memory cells  3  and, in use, store a logic datum complementary to that of the first memory cells  3 . The second memory cells  3 ′ are queried, during double-ended reading of the first memory cells  3 , to read the logic datum stored in the first memory cells  3  by comparison with the logic datum stored in respective second memory cells  3 ′. 
       FIG. 1  illustrates first memory cells  3  (“direct” cells) operatively coupled to respective local wordlines WL&lt; &gt; (WL&lt; 0 &gt;, WL&lt; 1 &gt;, . . . ) and to respective local bitlines BL L &lt; &gt; (BL L &lt; 0 &gt;, BL L &lt; 1 &gt;, . . . ), etc. Likewise shown are second memory cells  3 ′ (“complementary” cells), operatively coupled to the local wordlines WL&lt; &gt;, designated in  FIG. 1  as WL&lt; 0 &gt;, WL&lt; 1 &gt;, . . . , and to respective local bitlines BL R &lt; &gt;, designated in  FIG. 1  as BL R &lt; 0 &gt;, BL R &lt; 1 &gt;, . . . , etc. 
     The local bitlines BL L &lt; &gt; and the first memory cells  3  form a first memory portion  2   a . The local bitlines BL R &lt; &gt; and the second memory cells  3 ′ form a second memory portion  2   b.    
     The phase-change element  3   a ,  3   a ′ includes a phase-change material (for example, a chalcogenide), and is therefore able to store data in the form of levels of resistance associated to the different phases assumed by the phase-change material. The selector element  3   b ,  3   b ′ is, for example, a PMOS transistor having its gate terminal connected to the respective wordline WL&lt; &gt;, a first conduction terminal connected to the phase-change element, and a second conduction terminal connected to a reference potential (for example, ground). The selector element is controlled so as to enable, when selected (i.e., switched on by the signal of the respective local wordline WL&lt; &gt; to which it is coupled), passage of a reading current through the phase-change element during an operation of reading of the logic datum stored therein. 
     The non-volatile memory device  1  further comprises a row decoder (here not illustrated), adapted to select the local wordline WL&lt; &gt; corresponding to the memory cell  3 ,  3 ′ each time to be addressed. 
     As represented schematically in  FIG. 1 , the memory array  2  is organized in a plurality of sectors (shown by way of example in the figure are only four sectors S 1 -S 4 ). Each sector comprises respective local bitlines BL&lt; &gt; (direct bitlines BL L &lt; &gt; and complementary bitlines BL R &lt; &gt;), which can be addressed by a local column decoder  5  dedicated to each sector. The local bitlines BL&lt; &gt; of the sectors S 1  and S 2  can be addressed by an even number of addresses, and the respective sectors S 1  and S 2  may in what follows be referred to as “even sectors”. The local bitlines BL&lt; &gt; of the sectors S 3  and S 4  can be addressed by an odd number of addresses, and the respective sectors S 3  and S 4  may in what follows be referred to as “odd sectors”. 
     Given the matrix structure, activation of a local wordline WL&lt; &gt; and of a local bitline BL L,R &lt; &gt; enables unique selection of only one memory cell  3 ,  3 ′. 
     A reading stage  7 , of a type in itself known, is provided with a first sense amplifier  6   a  and a second sense amplifier  6   b . The presence of two sense amplifiers  6   a ,  6   b  is dictated by the particular organization of the memory  1  where, to increase the reading speed, simultaneous reading of data different from one another is carried out (according to the even and odd division, mentioned previously and illustrated more fully hereinafter) by the two amplifiers  6   a ,  6   b.    
     The reading stage  7  is coupled to the local bitlines BL L,R &lt; &gt; by main bitlines MBL L &lt; &gt; (in the portion  2   a ) and main bitlines MBL R &lt; &gt; (in the portion  2   b ). 
     A global column decoder  4  is adapted to select the main bitline to which the memory cell  3 ,  3 ′ to be addressed is coupled. The global column decoder  4  comprises, in an embodiment provided by way of example: a plurality of main selection switches  12   a - 12   d  coupled to main bitlines MBL L &lt; &gt; of the memory portion  2   a ; and a plurality of main selection switches  12   e - 12   h  coupled to main bitlines MBL R &lt; &gt; of the memory portion  2   b.    
     A first main bitline MBL L &lt; 0 &gt;, belonging to the memory portion  2   a , connects the local bitlines BL L &lt; &gt; of the first sector S 1  to the global column decoder  4  and, via the latter, to the reading stage  7 . In detail, the first main bitline MBL L &lt; 0 &gt; extends between a terminal of the main selection switch  12   a  and a node A common to all the local bitlines BL L &lt; &gt; belonging to the sector S 1  in the first memory portion  2   a  (direct cells). The other terminal of the main selection switch  12   a  is coupled to a first input  6   a ′ of the sense amplifier  6   a.    
     A second main bitline MBL L &lt; 1 &gt;, belonging to the memory portion  2   a , connects the local bitlines BL L &lt; &gt; of the second sector S 2  to the global column decoder  4  and, via the latter, to the reading stage  7 . In detail, the second main bitline MBL L &lt; 1 &gt; extends between a terminal of the main selection switch  12   b  and a node B common to all the local bitlines BL L &lt; &gt; belonging to the sector S 2  in the first memory portion  2   a  (direct cells). The other terminal of the main selection switch  12   b  is coupled to the first input  6   a ′ of the sense amplifier  6   a.    
     A third main bitline MBL L &lt; 2 &gt;, belonging to the memory portion  2   a , connects the local bitlines BL L &lt; &gt; of the third sector S 3  to the global column decoder  4  and, via the latter, to the reading stage  7 . In detail, the third main bitline MBL L &lt; 2 &gt; extends between a terminal of the main selection switch  12   c  and a node C common to all the local bitlines BL L &lt; &gt; belonging to the sector S 3  in the first memory portion  2   a  (direct cells). The other terminal of the main selection switch  12   c  is coupled to a first input  6   b ′ of the sense amplifier  6   b.    
     A fourth main bitline MBL L &lt; 3 &gt;, belonging to the memory portion  2   a , connects the local bitlines BL L &lt; &gt; of the fourth sector S 4  to the global column decoder  4  and, via the latter, to the reading stage  7 . In detail, the fourth main bitline MBL L &lt; 3 &gt; extends between a terminal of the main selection switch  12   d  and a node D common to all the local bitlines BL L &lt; &gt; belonging to the sector S 4  in the first memory portion  2   a  (direct cells). The other terminal of the main selection switch  12   d  is coupled to the first input  6   b ′ of the sense amplifier  6   b.    
     The memory portion  2   b  (complementary cells) is organized in a way similar to the memory portion  2   a  of the direct cells, as described hereinafter. 
     There is thus present a fifth main bitline MBL R &lt; 0 &gt;, belonging to the memory portion  2   b , which connects the local bitlines BL R &lt; &gt; of the first sector S 1  to the global column decoder  4  and, via the latter, to the reading stage  7 . In detail, the fifth main bitline MBL R &lt; 0 &gt; extends between a terminal of the main selection switch  12   e  and a node E common to all the local bitlines BL R &lt; &gt; belonging to the sector S 1  in the second memory portion  2   b  (complementary cells). The other terminal of the main selection switch  12   e  is coupled to a second input  6   a ″ of the sense amplifier  6   a.    
     A sixth main bitline MBL R &lt; 1 &gt;, belonging to the memory portion  2   b , connects the local bitlines BL R &lt; &gt; of the second sector S 2  to the global column decoder  4  and, via the latter, to the reading stage  7 . In detail, the sixth main bitline MBL R &lt; 1 &gt; extends between a terminal of the main selection switch  12   f  and a node F common to all the local bitlines BL R &lt; &gt; belonging to the sector S 2  in the second memory portion  2   b  (complementary cells). The other terminal of the main selection switch  12   f  is coupled to the second input  6   a ″ of the sense amplifier  6   a.    
     A seventh main bitline MBL R &lt; 2 &gt;, belonging to the memory portion  2   b , connects the local bitlines BL R &lt; &gt; of the third sector S 3  to the global column decoder  4  and, via the latter, to the reading stage  7 . In detail, the seventh main bitline MBL R &lt; 2 &gt; extends between a terminal of the main selection switch  12   g  and a node G common to all the local bitlines BL R &lt; &gt; belonging to the sector S 3  in the second memory portion  2   b  (complementary cells). The other terminal of the main selection switch  12   g  is coupled to a second input  6   b ″ of the sense amplifier  6   b.    
     An eighth main bitline MBL R &lt; 3 &gt;, belonging to the memory portion  2   b , connects the local bitlines BL R &lt; &gt; of the fourth sector S 4  to the global column decoder  4  and, via the latter, to the reading stage  7 . In detail, the fourth main bitline MBL L &lt; 3 &gt; extends between a terminal of the main selection switch  12   d  and a node D common to all the local bitlines BL R &lt; &gt; belonging to the sector S 4  in the first memory portion  2   a  (direct cells). The other terminal of the main selection switch  12   d  is coupled to the first input  6   b ′ of the sense amplifier  6   b.    
     Each local bitline BL L &lt; &gt; of the sector S 1  of the first memory portion  2   a  is electrically coupled to the node A by a respective local selection switch  13   a  (in the example of  FIG. 1 , local selection switches  13   a  are present in the form of PMOS transistors). Likewise, each local bitline BL R &lt; &gt; of the sector S 1  of the second memory portion  2   b  is electrically coupled to the node E by a respective local selection switch  13   b  (in this example, PMOS transistors). 
     Likewise, each local bitline BL L &lt; &gt; of the sector S 2  of the first memory portion  2   a  is electrically coupled to the node B by a respective local selection switch  13   a  (in the example of  FIG. 1 , local selection switches  13   a  are present in the form of PMOS transistors). Likewise, each local bitline BL R &lt; &gt; of the sector S 2  of the second memory portion  2   b  is electrically coupled to the node F by a respective local selection switch  13   b  (in this example, PMOS transistors). 
     The same structure is replicated in a similar way, and not described any further herein, for the remaining local bitlines BL L,R &lt; &gt; of the sectors S 3  and S 4 . 
     The local selection switches  13   a ,  13   b  form part of the respective local column decoders  5 . 
     During use, the local column decoder  5  receives at input address-selection signals (also known as Decoded Address Signals, or DASs) S YO &lt; &gt; (in particular, S YO &lt; 0 &gt;, . . . , S YO &lt; 1 &gt;, . . . ) for selecting a respective local bitline BL L &lt; &gt; (BL L &lt; 0 &gt;, BL L &lt; 1 &gt;, . . . ) and/or BL R &lt; &gt; (BL R &lt; 0 &gt;, BL R &lt; 1 &gt;, . . . ) in order to access the first memory cells  3  and/or the second memory cells  3 ′. 
     The signals S YO &lt; &gt; are low-voltage signals, i.e., operating in the range of logic voltages [GND, VDD], where VDD is, for example, comprised between 1V and 1.4 V and GND is a ground reference voltage, for example 0 V. 
     As mentioned previously, to increase the reading parallelism, the sense amplifier  6   a  is coupled to a subset of so-called even bitlines BL&lt; &gt; (i.e., indexed by an even index, such as BL&lt; 0 &gt;, BL&lt; 2 &gt;, BL&lt; 4 &gt;, etc.) belonging to the sectors S 1 , S 2 , while the sense amplifier  6   b  is coupled to a subset of so-called odd bitlines BL&lt; &gt; (i.e., indexed by an odd index, such as BL&lt; 1 &gt;, BL&lt; 3 &gt;, BL&lt; 5 &gt;, etc.) belonging to the sectors S 3 , S 4 . The reading operation is carried out at the same time by the sense amplifier  6   a  and  6   b  for the respective memory cells  3 ,  3 ′ coupled, respectively, to the even and odd bitlines BL&lt; &gt;. 
     The local column decoder  5  is configured so as to generate a current path between an even direct bitline selected from BL L &lt; 0 &gt;, BL L &lt; 2 &gt;, etc. (belonging to the portion  2   a ) and the first input  6   a ′ of the sense amplifier  6   a , and between an even complementary bitline selected from BL R &lt; 0 &gt;, BL R &lt; 2 &gt;, etc. (belonging to the portion  2   b ) and the second input  6   a ″ of the sense amplifier  6   a.    
     Furthermore, the local column decoder  5  is configured so as to generate a current path between an odd direct bitline selected from BL L &lt; 1 &gt;, BL L &lt; 3 &gt;, etc. (belonging to the portion  2   a ) and the first input  6   b ′ of the sense amplifier  6   b , and between an odd complementary bitline selected from BL R &lt; 1 &gt;, BL R &lt; 3 &gt;, etc. (belonging to the portion  2   b ) and the second input  6   b ″ of the sense amplifier  6   b.    
     It may be noted that also the organization in sectors S 1 -S 4  takes into account the reading division between even and odd. In fact, the sectors S 1  and S 2  group together bitlines that can be selected by even addresses, whereas the sectors S 3  and S 4  group together bitlines that can be selected by odd addresses. The main bitlines MBL L,R &lt; 0 , 1 &gt; access even sectors S 1  and S 2 ; the main bitlines MBL L,R &lt; 2 , 3 &gt; access odd sectors S 3  and S 4 . 
     In effect, the global column decoder  4  comprises two distinct read-decoding circuits, adapted to generate a respective current path between memory cells  3  of the portion  2   a  and the respective input  6   a ′,  6   b ′ of the sense amplifiers  6   a ,  6   b , and between second memory cell  3 ′ of the portion  2   b  and the respective input  6   a ″,  6   b ″ of the sense amplifiers  6   a ,  6   b . The current paths thus generated are completely distinct and separate from one another. 
     The two aforementioned read-decoding circuits of the global column decoder  4  present a specular circuit structure. The number of selection switches that form the global column decoder  4  depends upon the size of the memory array  2  and/or of the sectors of the memory array  2 , as well as upon the hierarchical organization of the column selectors. 
     The read-decoding circuits of the global column decoder  4  moreover comprise buffers (not illustrated) that drive the selection switches  12   a - 12   h . Each buffer  9   a  receives a control signal S YN  and supplies to the control terminals of the respective selection switches  12   a - 12   h  a column-decoding signal YN. 
     Moreover, a plurality of local buffers (not illustrated) is present. Bitlines BL L &lt; &gt; belonging to the first portion  2   a  and corresponding to respective bitlines BL R &lt; &gt; of the second portion  2   b  of the memory array  2  (i.e., the bitlines selected by a same signal S YO &lt; &gt;) can share a same local buffer. The local buffers are configured to receive a respective control signal S YO &lt; &gt; and supply to the control terminals of the respective local selection switches  13   a ,  13   b  column-decoding signals YO L &lt; &gt;, YO R &lt; &gt;. 
     The selection switches of the circuit of  FIG. 1  are implemented by PMOS transistors, which have a control terminal (gate) that receives the respective column-decoding signals YN, YO L &lt; &gt;, YO R &lt; &gt;, which is a logic signal “o” that switches on the respective transistor, or else “1” that switches off the respective transistor. In use, the signals S YO &lt; &gt; and S YN  are low-voltage signals, and one of the operations carried out by the buffers is to raise the voltage by generating a voltage signal adequate for driving the respective PMOS transistor. 
     The non-volatile memory device  1  further comprises a first reference branch  20  including a reference generator  21 , configured to generate a reference current i REF , electrically coupled to the second input  6   a ″ of the sense amplifier  6   a  by a selection switch  22 . The selection switch  22  is driven by a signal S i ′, configured to switch on and switch off the selection switch  22  in respective operating modes of the non-volatile memory device  1  in order to set up or interrupt an electrical path for the reference current i REF  towards the second input  6   a ″ of the sense amplifier  6   a.    
     The non-volatile memory device  1  further comprises a second reference branch  23  including a reference generator  24 , configured to generate a reference current i REF , electrically coupled to the second input  6   b ″ of the sense amplifier  6   b  by a selection switch  25 . The selection switch  25  is driven by a signal S i ″, configured to switch on and switch off the selection switch  25  in respective operating modes of the non-volatile memory device  1  in order to set up or interrupt an electrical path for the reference current i REF  towards the second input  6   b ″ of the sense amplifier  6   b.    
     During use of the non-volatile memory device  1  in double-ended reading, the reference generators  21 ,  24  are off. Reading is therefore performed by each sense amplifier  6   a ,  6   b  by receiving at the respective inputs a datum (value of voltage/current) stored in a direct cell and a datum stored in a complementary cell. During reading of a datum, the respective (direct and complementary) cells that are being read belong to a same sector S 1 -S 4 , but to respective memory portions  2   a ,  2   b . The connections between the memory cells and the sense amplifiers have been described previously. 
     Conversely, during use of the non-volatile memory device  1  in single-ended reading, the reference generators  21 ,  24  are on, and reading is performed by comparing the current that flows in the memory cell selected with the reference current i REF . In this reading mode, in order to maintain a same (capacitive) load on both of the inputs of the sense amplifiers  6   a ,  6   b , the global column decoder  4  is controlled so as to connect the inputs  6   a ″,  6   b ″ of the sense amplifiers  6   a ,  6   b  to a respective main bitline MBL R &lt; &gt; belonging to the memory portion  2   b . In addition, the local column decoder  5  is controlled so as to connect the respective main bitlines MBL R &lt; &gt; to the local bitlines BL R &lt; &gt; of the respective memory sectors S 1 -S 4 . However, the wordlines WL&lt; &gt; are de-selected so that no specific memory cell  3 ′ is in effect addressed. In this way, the only current that flows at the input  6   a ″,  6   b ″ of the sense amplifiers  6   a ,  6   b  is the respective reference current i REF . The capacitive load is, instead, given by the sum of the capacitances associated to the respective main and local bitlines that have been connected to the input  6   a ″,  6   b ″ of the sense amplifier  6   a ,  6   b.    
     To clarify the foregoing more fully, an example is proposed, with reference to  FIG. 2 . 
       FIG. 2  corresponds, where not otherwise specified, to  FIG. 1 . 
     To read in single-ended mode a direct memory cell belonging to the sector S 1 , the corresponding local selection switch  13   a  (delimited by a dashed circle in the sector S 1 , portion  2   a ) is switched on and the cell to be read is selected by activating the respective wordline WL (WL&lt; 0 &gt; in  FIG. 2 ). Therefore, the main selector  12   a  is switched on, thus connecting the input  6   a ′ of the amplifier  6   a  to the main bitline MBL L &lt; 0 &gt;. In this way, an electrical connection is set up between the memory cell  3  to be read and the sense amplifier  6   a . As has been said, supplied at the input  6   a ″ is a reference current signal i REF . To provide at the input  6   a ″ a capacitive load comparable with the one present at the input  6   a ′, the local selection switch  13   b  delimited by a dashed circle in the sector S 2 , portion  2   b , is switched on, but no complementary memory cell is selected by the respective wordline WL&lt; &gt; (which remains de-selected). Moreover, the main selector  12   f  is switched on to connect the main bitline MBL R &lt; 1 &gt; to the local bitline BL R &lt; &gt; selected via the local selection switch that has been switched on. The other selectors  12   b - 12   d ,  12   e ,  12   g ,  12   h  remain off. It should be noted that the choice of switching on the selector  12   f  is dictated by the fact that this selector is coupled to the main bitline MBL R &lt; 1 &gt;, which is in turn connected to the sector S 2 , i.e., to the sector physically “closest” to the sector S 1  to which the direct memory cell to be read belongs. In this way, since the two memory portions  2   a ,  2   b  are specular, we have the best guarantee of having a match that is as accurate as possible between the capacitive loads at the inputs  6   a ′ and  6   a ″. In fact, the capacitance associated to the main bitlines MBL L,R &lt; &gt; depends directly upon the length of the main bitlines MBL L,R &lt; &gt;. It may be noted that it would not be possible to connect the main bitline MBL R &lt; 0 &gt; to the input  6   a ″ by switching on the selector  12   e  in so far as the wordline WL&lt; &gt; selected for accessing the memory cell  3  to be read is common to the entire sector S 1 , both in the portion  2   a  and in the portion  2   b . Consequently, this condition is not practicable in single-ended reading. 
     A similar situation occurs for the reading performed by the sense amplifier  6   b.    
     The present applicant has found that, to reduce the total area occupied by the memory array  2 , it would be expedient to group memory sectors S 1 , S 2 , . . . , etc. physically together. For instance, by grouping together the memory sector S 2  and the memory sector S 1 , a new memory sector S 1 ′ would be obtained having a size equal to the sum of the sizes of the sectors S 1  and S 2  prior to grouping. In this way, there would be a saving of area given by the elimination of the local column decoders  5  associated to the sectors that have been eliminated (i.e., grouped together). In this example, the local column decoders  5  dedicated to the sector S 2  would be eliminated. The entire new sector S 1 ′ would be handled by a local column decoder thereof. 
     However, grouping together of the sectors S 2  and S 1  would no longer make it possible, in the single-ended reading mode, to address properly the memory cell  3  to be read and at the same time to guarantee the desired capacitive load at the input  6   a ″ of the sense amplifier  6   a  that receives the reference current i REF  (as for the amplifier  6   b ). In fact, since it is not possible in this situation to connect the input  6   a ″ with the main bitline MBL R &lt; 1 &gt; of the second sector S 2  (which has been eliminated), it would be necessary to use a further and different main bitline MBL R &lt; &gt;, losing at least in part the condition of matching of capacitances seen at the inputs of the sense amplifier  6   a  (likewise  6   b ). In fact, this grouping of sectors involves the use of a single column decoder for both of the sectors, which would therefore be addressed simultaneously. 
     Furthermore, by replicating the concept set forth above for all the even sectors and for all the odd sectors (i.e., by creating a single even sector accessible by just one local column decoder and a single odd sector accessible by just one, respective, local column decoder), it would not be possible to implement the strategy described above with reference to  FIG. 2 , in so far as there would cease to be a de-selected sector to be used in single-ended reading to replicate the capacitive load at the terminal that receives the reference current i REF . 
     The aim of the present invention is consequently to provide a PCM device that will make it possible to solve, either totally or in part, the aforementioned problems, and that will be optimized as regards the characteristics of capacitive load seen by the sense amplifier in both the single-ended reading mode and the double-ended reading mode. The aim of the present invention is likewise to disclose a method for operating the PCM device. 
     According to the present invention, a phase-change memory device, a system including the phase-change memory device, and a method for operating the phase-change memory device are consequently provided, as defined in the annexed claims. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       For a better understanding of the present invention, preferred embodiments thereof are now described, purely by way of non-limiting example, with reference to the attached drawings, wherein: 
         FIG. 1  is a schematic illustration of a portion of a non-volatile memory device, in particular of a PCM type, according to an embodiment that does not form part of the present invention; 
         FIG. 2  shows the memory device of  FIG. 1  in an operating condition; 
         FIG. 3  is a schematic illustration of a portion of a non-volatile memory device, in particular of a PCM type, according to an embodiment of the present invention; 
         FIGS. 4-6  represent the memory device of  FIG. 3  in respective operating conditions of the present invention; and 
         FIG. 7  is a simplified block diagram of an electronic system incorporating the non-volatile memory device, in an embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS 
     Illustrated schematically in  FIG. 3  and designated as a whole by the reference number  100  is a portion of a non-volatile memory device, in particular of a PCM type, limitedly to just the parts necessary for an understanding of the present disclosure. 
     Elements of the memory device  100  already described with reference to  FIG. 1  are not described any further here and are designated by the same reference numbers. 
     The non-volatile memory device  100  comprises a memory array  102 , constituted by a plurality of first memory cells  3  and by a plurality of second memory cells  3 ′, which can be selected by local wordlines WL and local bitlines BL. In a way in itself known, the second memory cells  3 ′ correspond, in number and manufacturing characteristics, to the first memory cells  3  and, in use, store a logic datum complementary to that of the first memory cells  3 . The second memory cells  3 ′ are queried during double-ended reading of the first memory cells  3  to read the logic datum stored in the first memory cells  3  by comparison with the logic datum stored in respective second memory cells  3 ′. 
     The local bitlines BL L &lt; &gt; and the first memory cells  3  form a first memory portion  102   a . The local bitlines BL R &lt; &gt; and the second memory cells  3 ′ form a second memory portion  102   b.    
     The memory array  102  is organized in at least a first sector S 101  and a second sector S 102 . Each sector comprises respective local bitlines BL&lt; &gt; (direct bitlines BL L &lt; &gt;, and complementary bitlines BL R &lt; &gt;), which can be addressed by a local column decoder  5  for each sector. The local bitlines BL&lt; &gt; of the sector S 101  can be addressed via an even address number (S 101  is therefore also referred to as “even sector”), and the local bitlines BL&lt; &gt; of the sector S 102  can be addressed via an odd address number (S 102  is therefore also referred to as “odd sector”). 
     Given the matrix structure, activation of a local wordline WL&lt; &gt; and of a local bitline BL L,R &lt; &gt; enables unique selection of only one memory cell  3 ,  3 ′. 
     The reading stage  7  corresponds to what has already been described with reference to  FIG. 1 . The reading stage  7  is coupled to the local bitlines BL L,R &lt; &gt; by main bitlines MBL L &lt; &gt; (for the portion  2   a ) and main bitlines MBL R &lt; &gt; (for the portion  2   b ). 
     The global column decoder  4  corresponds to what has already been described with reference to  FIG. 1  and is adapted to select the main bitline to which the memory cell  3 ,  3 ′ to be addressed is coupled. 
     Here, a first main bitline MBL L &lt; 0 &gt;, belonging to the memory portion  2   a , connects the local bitlines BL L &lt; &gt; of the sector S 101  to the global column decoder  4  and, via the latter, to the reading stage  7 . The first main bitline MBL L &lt; 0 &gt; is connected to a node A common to all the local bitlines BL L &lt; &gt; belonging to the sector S 101  in the first memory portion  2   a  (direct cells). As regards the global column decoder  4 , both of the main selection switches  12   a  and  12   d  have a respective terminal connected to the first main bitline MBL L &lt; 0 &gt;. In other words, the first main bitline MBL L &lt; 0 &gt; extends between the node A and a node A′, from which there branch off the connections towards the respective terminals of the main selection switches  12   a  and  12   d . The other terminal of the main selection switch  12   a  is connected to the first input  6   a ′ of the sense amplifier  6   a . The other terminal of the main selection switch  12   d  is, instead, connected to the first input  6   b ′ of the sense amplifier  6   b.    
     A second main bitline MBL L &lt; 1 &gt;, belonging to the memory portion  2   a , connects the local bitlines BL L &lt; &gt; of the second sector S 102  to the global column decoder  4  and, via the latter, to the reading stage  7 . The second main bitline MBL L &lt; 1 &gt; is connected to a node B common to all the local bitlines BL L &lt; &gt; belonging to the sector S 102  in the first memory portion  2   a  (direct cells). As regards the global column decoder  4 , both of the main selection switches  12   b  and  12   c  have a respective terminal connected to the second main bitline MBL L &lt; 1 &gt;. In other words, the second main bitline MBL L &lt; 1 &gt; extends between the node B and a node B′, from which there branch off the connections towards the respective terminals of the main selection switches  12   b  and  12   c . The other terminal of the main selection switch  12   b  is connected to the first input  6   a ′ of the sense amplifier  6   a . The other terminal of the main selection switch  12   c  is, instead, connected to the first input  6   b ′ of the sense amplifier  6   b.    
     The memory portion  2   b  (complementary cells) is organized in a way similar to the memory portion  2   a  of the direct cells, as described hereinafter. 
     There is thus present a third main bitline MBL R &lt; 0 &gt;, belonging to the memory portion  2   b , which connects the local bitlines BL R &lt; &gt; of the first sector S 101  to the global column decoder  4  and, via the latter, to the reading stage  7 . In detail, the third main bitline MBL R &lt; 0 &gt; is connected to a node E common to all the local bitlines BL R &lt; &gt; belonging to the sector S 101  in the second memory portion  2   b  (complementary cells). As regards the global column decoder  4 , both of the main selection switches  12   e  and  12   h  have a respective terminal connected to the third main bitline MBL R &lt; 0 &gt;. In other words, the third main bitline MBL R &lt; 0 &gt; extends between the node E and a node E′, from which there branch off the connections towards the respective terminals of the main selection switches  12   e  and  12   h . The other terminal of the main selection switch  12   e  is connected to the second input  6   a ″ of the sense amplifier  6   a . The other terminal of the main selection switch  12   h  is, instead, connected to the second input  6   b ″ of the sense amplifier  6   b.    
     A fourth main bitline MBL R &lt; 1 &gt;, belonging to the memory portion  2   b , connects the local bitlines BL R &lt; &gt; of the second sector S 102  to the global column decoder  4  and, via the latter, to the reading stage  7 . In detail, the fourth main bitline MBL R &lt; 1 &gt; is connected to a node G common to all the local bitlines BL R &lt; &gt; belonging to the sector S 102  in the second memory portion  2   b  (complementary cells). As regards the global column decoder  4 , both of the main selection switches  12   g  and  12   f  have a respective terminal connected to the fourth main bitline MBL R &lt; 1 &gt;. In other words, the fourth main bitline MBL R &lt; 1 &gt; extends between the node G and a node G′, from which there branch off the connections towards the respective terminals of the main selection switches  12   f  and  12   g . The other terminal of the main selection switch  12   f  is connected to the second input  6   a ″ of the sense amplifier  6   a . The other terminal of the main selection switch  12   g  is, instead, connected to the second input  6   b ″ of the sense amplifier  6   b.    
     Each local bitline BL L &lt; &gt; of the sector S 101  of the first memory portion  2   a  is electrically coupled to the node A by a respective local selection switch  13   a  (here, a respective PMOS transistor). Likewise, each local bitline BL R &lt; &gt; of the sector S 101  of the second memory portion  2   b  is electrically coupled to the node E by a respective local selection switch  13   b  (in this example, a respective PMOS transistor). 
     Likewise, each local bitline BL L &lt; &gt; of the sector S 102  of the first memory portion  2   a  is electrically coupled to the node B by a respective local selection switch  13   a  (here, a respective PMOS transistor). Likewise, each local bitline BL R &lt; &gt; of the sector S 102  of the second memory portion  2   b  is electrically coupled to the node G by a respective local selection switch  13   b  (here, a respective PMOS transistor). 
     The local selection switches  13   a ,  13   b  form part of the respective local column decoders  5 . In use, the local column decoder  5  receives at input address-selection signals (DAS) S YO &lt; &gt;, as already described with reference to  FIG. 1  and therefore not described any further here. 
     As described with reference to  FIG. 1 , also in this case the sense amplifier  6   a  is coupled to a subset of bitlines BL&lt; &gt; referred to as even bitlines (i.e., indexed by an even index, such as BL&lt; 0 &gt;, BL&lt; 2 &gt;, BL&lt; 4 &gt;, etc.) belonging to the sector  101 , while the sense amplifier  6   b  is coupled to a subset of bitlines BL&lt; &gt; referred to as odd bitlines (i.e., indexed by an odd index, such as BL&lt; 1 &gt;, BL&lt; 3 &gt;, BL&lt; 5 &gt;, etc.). The double-ended reading operation is carried out simultaneously by the sense amplifier  6   a  and  6   b  for the respective memory cells  3 ,  3 ′ coupled, respectively, to the even and odd bitlines BL&lt; &gt;. The double-ended reading operation is carried out in accordance with the prior art, and is described by way of example hereinafter with reference to  FIG. 6 . 
     As regards reading in single-ended mode, the memory device  100  further comprises a first reference branch  20 , which includes the reference generator  21 , configured to generate the reference current i REF  to be supplied to the second input  6   a ″ of the sense amplifier  6   a  by the selection switch  22 . The memory device  100  further comprises a second reference branch  23 , which includes the reference generator  24 , configured to generate a reference current i REF , and is electrically coupled to the second input  6   b ″ of the sense amplifier  6   b  by the selection switch  25 . 
     During use of the memory device  100  in single-ended reading mode, the reference generators  21 ,  24  are on, and reading is performed by comparing the current that flows in the memory cell selected with the reference current i REF . 
     In this reading mode, in order to maintain a same capacitive load on both of the inputs of the sense amplifiers  6   a ,  6   b , the global column decoder  4  is controlled so as to connect the second inputs  6   a ″,  6   b ″ of the sense amplifiers  6   a ,  6   b  to a respective main bitline MBL R &lt; &gt; belonging to the memory portion  2   b.    
     In this embodiment, however, simultaneous reading of the even sector S 101  and of the odd sector S 102  is not possible, in so far as there would cease to be a de-selected sector to be used for capacitive matching. 
     Consequently, to read a datum from a memory cell  3  of the sector S 101 , the sector S 102  is de-selected (i.e., no wordline of the sector S 102  is selected), and the selection switches  12   b - 12   d ,  12   e ,  12   g ,  12   h  are switched off. The selection switches  12   a ,  12   f  are, instead, switched on. Reading is carried out by the sense amplifier  6   a.    
     As illustrated graphically in  FIG. 4 , reading of the logic datum stored in the memory cell  3  delimited by a dashed circle in the sector S 101  is performed by connecting the memory cell  3  to the input  6   a ′ of the sense amplifier  6   a  and enabling an electrical path between the memory cell  3  and the input  6   a ′ (i.e., by selecting the corresponding wordline WL&lt; 0 &gt; by switching on the switch  13   a  of the bitline BL&lt; &gt; coupled to the memory cell  3  to be read and switching on the selection switch  12   a ). The path of the reading current is indicated in  FIG. 4  with a thick solid line P 1 . The input  6   a ″ receives the reference current i REF  from the generator  21 . 
     In order to provide at the input  6   a ″ the required capacitive load, the input  6   a ″ is connected to the main bitline MBL R &lt; 1 &gt; via the switch  12   f , which is switched on. Moreover, one of the switches  13   b  connected to the node G is also switched on, in particular the switch  13   b  for the bitline BL&lt; &gt; physically arranged so as to approximate as closely as possible the electrical path (and therefore the capacitive load) of the memory cell  3  to be read. Since all the wordlines WL&lt; &gt; of the sector S 102  are de-selected, activation of the aforementioned electrical path does not generate a transfer of current towards the input  6   a ″, but represents a capacitive load for the input  6   a ″. The path that constitutes the capacitive load is indicated in  FIG. 4  with a thick dashed line P 2 . It may be noted that, in this reading condition, the sense amplifier  6   b  is off and does not receive any datum/current signal at its inputs  6   b ′,  6   b″.    
     Reading of a logic datum stored in a memory cell  3  of the sector S 102  (odd sector) occurs in a way equivalent to what has been described with reference to  FIG. 4 . Also, in this case, simultaneous reading of the even sector S 101  and of the odd sector S 102  is not possible in so far as there would cease to be a de-selected sector to be used for capacitive matching. 
     Consequently, to read a datum from a memory cell  3  of the sector S 102 , the sector S 101  is de-selected (i.e., no wordline of the sector S 101  is selected), and the selection switches  12   a ,  12   b ,  12   d ,  12   e - 12   g  are switched off. The selection switches  12   c ,  12   h  are instead switched on. Reading is carried out by the sense amplifier  6   b.    
     As illustrated graphically in  FIG. 5 , reading of the logic datum stored in the memory cell  3  delimited by a dashed circle in the sector S 102  occurs by connecting the memory cell  3  to the input  6   b ′ of the sense amplifier  6   b  and enabling an electrical path between the memory cell  3  and the input  6   b ′ (i.e., by selecting the corresponding wordline WL&lt; &gt; by switching on the switch  13   a  of the bitline BL&lt; &gt; coupled to the memory cell  3  to be read and switching on the selection switch  12   c ). The path of the reading current is indicated in  FIG. 5  with a thick solid line P 3 . The input  6   b ″ receives the reference current i REF  from the generator  24 . 
     In order to provide at the input  6   b ″ the required capacitive load, the input  6   b ″ is connected to the main bitline MBL R &lt; 0 &gt; via the switch  12   h , which is switched on. In addition, also one of the switches  13   b  connected to the node E is switched on, in particular the switch  13   b  for the bitline BL&lt; &gt; physically arranged so as to approximate as closely as possible the electrical path (and therefore the capacitive load) of the memory cell  3  to be read. Since all the wordlines WL&lt; &gt; of the sector S 101  are de-selected, activation of the aforementioned electrical path does not generate a transfer of current towards the input  6   b ″, but represents a capacitive load for the input  6   b ″. The path that forms the capacitive load is indicated in  FIG. 5  with a thick solid line P 4 . It may be noted that, in this reading condition, the sense amplifier  6   a  is off and does not receive any datum/current signal at its inputs  6   a ′,  6   a″.    
     During use of the memory device  100  in double-ended reading mode, the reference generators  21 ,  24  are off. As regards the main selection switches, the double-ended reading mode envisages ( FIG. 6 ) simultaneously switching on the selection switches  12   a ,  12   c ,  12   e ,  12   g , and keeping the remaining switches  12   b ,  12   d ,  12   f ,  12   h  off. 
     In this way, by selecting (activating) the appropriate wordlines WL&lt; &gt; in both of the sectors S 101 , S 102  (in order to select the direct memory cell to be read and, simultaneously, the respective complementary memory cell), it is possible to set up the desired current paths towards: the input  6   a ′ (path L 1  in  FIG. 6 ); the input  6   a ″ (path L 2  in  FIG. 6 ); the input  6   b ′ (path L 3  in  FIG. 6 ); and the input  6   b ″ (path L 4  in  FIG. 6 ). 
     The operations of activation or selection of the main and local bitlines, as likewise of the wordlines, to implement the single-ended and double-ended reading operations according to the present invention are carried out by a controller appropriately configured for this purpose, in a way in itself evident to the person skilled in the art. The controller governs the selectors (switches, which are constituted, in particular, by transistors) described previously, sending signals for switching them on and for switching them off so as to create the appropriate electrical connections with the inputs of the sense amplifiers  6   a ,  6   b . Buffers (not illustrated in detail) are typically present to adapt the level of the (voltage/current) signal to the level accepted at input by the control terminal (gate) of the selectors. A controller  201  is illustrated by way of example in  FIG. 7 . 
       FIG. 7  illustrates a portion of an electronic system  200 , according to a further embodiment of the present invention. The electronic system  200  may be used in electronic devices, such as: a PDA (Personal Digital Assistant); a portable or fixed computer, possibly with the capacity of wireless data transfer; a mobile phone; a digital audio player; a photographic camera or video camera; or further devices capable of processing, storing, transmitting, and receiving information. 
     In detail, the electronic system  200  comprises a controller  201  (for example, provided with a microprocessor, a DSP, or a microcontroller), and the memory device  100 , provided with the array of memory cells of the phase-change type, described previously. In addition, and optionally, the electronic system  200  further comprises one or more from among an input/output device  202  (for example, provided with a keypad and a display) for entering and displaying data, a wireless interface  204 , for example an antenna, for transmitting and receiving data through a wireless communication radiofrequency network, and a RAM  205 , all of which are coupled through a bus  206 . A battery  207  can be used as electrical supply source in the electronic system  200 , which may moreover be provided with a photographic camera or video camera  208 . 
     From what has been described and illustrated previously, the advantages that the column decoder according to the invention affords are evident. 
     In particular, the silicon area required for providing a non-volatile memory (in particular, a PCM) operating as described and having the circuit structure described is minimized. 
     The architecture proposed moreover makes it possible to guarantee a good matching between the capacitive load and the inputs of the sense amplifier, both during single-ended reading and during double-ended reading. 
     Finally, it is clear that modifications and variations may be made to what has been described and illustrated herein, without thereby departing from the scope of the present invention, as defined in the annexed claims. 
     What has been described applies, in a similar way, to single-ended reading or double-ended reading of any other memory cell  3 . What has been described likewise applies, in a similar way, to verification in single-ended reading mode of the memory cells  3 ′, using a current reference supplied to the input  6   a ′/ 6   b ′ of the sense amplifier  6   a / 6   b.    
     It may be noted that, during single-ended reading of the sector S 101  (memory portion  102   a ), the selection switches  13   b  of the sector S 102  could be off, whereas for reading of a memory cell of the sector S 102  those of the sector S 101  could be off. In fact, the most important capacitive component in PCMs is represented by the main bitline (which is typically obtained in the form of a conductive metal path with a length of 2 mm and a width of 1 μm). Consequently, also by turning off the switches  13   b , there would in any case be guaranteed a comparable capacitive load on both of the inputs of the sense amplifier involved in the reading process. 
     Moreover, the invention described and illustrated can be advantageously applied also to other types of memory devices, for example flash memory devices. 
     It is evident that a different number of selection switches may be provided in the column decoder, and a different organization thereof in hierarchical levels. 
     In addition, the present invention has been described with reference to just two sense amplifiers  6   a ,  6   b . It is evident that a PCM device typically comprises a plurality of sense amplifiers higher than two (e.g.,  128 ,  256 , etc.), each dedicated to reading in parallel of respective data coming from memory cells  3  and  3 ′ (in the case of double-ended reading), or from a memory cell  3  and from a current reference (in the case of single-ended reading). 
     Furthermore, one of the reference-current generators  21  and  24  may be omitted, and during single-ended reading the reference current i REF  is supplied (alternatively) at the inputs  6   a ″,  6   b ″ by a single reference-current generator  21  or  24 .