Patent Publication Number: US-2011068382-A1

Title: Two-dimensional time delay integration visible cmos image sensor

Description:
CLAIM OF PRIORITY UNDER 35 U.S.C. §120   
     This application is a continuation of and claims the benefit and priority of U.S. application Ser. No. 11/683,811, entitled “TWO-DIMENSIONAL TIME DELAY INTEGRATION VISIBLE CMOS IMAGE SENSOR,” filed on Aug. 3, 2007, which is assigned to the assignee hereof and hereby expressly incorporated by reference herein. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The invention relates generally to a Complementary Metal Oxide Semiconductor (CMOS) image sensor. More particularly, the invention relates to two-dimensional time delay integration visible CMOS image sensor. 
     2. Description of Related Art 
     Unmanned Aerial Vehicles (UAVs) are remotely piloted or self-piloted aircrafts that can carry cameras, sensors, and other communication equipment. UAVs may be remotely controlled (e.g. flown by a pilot at a ground control station) or fly autonomously based on pre-programmed flight plans or more complex dynamic automation systems. UAVs are typically used for reconnaissance and intelligence-gathering, and for more challenging roles, including combat missions. 
     Ideally, an image taken from a camera onboard the UAV should be clear to provide accurate intelligence-gathering and determine appropriate targets. However, since UAVs shake from wind gusts during their flight operation, the image received from UAV is not clear enough to accurately identify targets on the ground. Consequently, there is a low signal to noise ratio due to wind and mechanical vibrations of the camera. This problem is compounded with moving scene imagery. 
     To improve signal to noise ratio, prior art stabilizers were integrated with the gimbal assembly of high speed cameras onboard the UAVs. The stabilizers reduce interferences caused by wind or mechanical vibrations. Additionally, the signal to noise ratio may be improved using Charge-Coupled Devices (CCDs) with Time Delay Integration (TDI). CCDs with TDI technology allow an image in a charge domain to move at about the same speed as the moving scene or target. However, CCDs with TDI are one dimensional and require multiple chip systems. 
     Conventional CMOS integrated circuits can achieve TDI in one dimension. The CMOS integrated circuits provide TDI using a switch matrix or a transistor chain CCD equivalent. The switch matrix typically accumulates additional noise and the signal to noise ratio improvement is less than proportional to the square root of the number of TDI channels. The transistor chain CCD equivalent cannot have high QE photodiode and is not a mainstream CMOS or CMOS Image Sensor (CIS) process. 
     With an ever increasing demand for improved imaging sensors, there remains a need for a two dimensional TDI visible CMOS image sensor that allow a charge to move at the same speed and follow a similar path in the charge domain as the moving image so that more charge from the scene can be integrated resulting in an improved signal to noise ratio. If readout noise is dominant, the signal to noise ratio improvement is proportional to the number of TDI channels. 
     SUMMARY OF THE INVENTION 
     The present invention fills this need by providing a time delay integration CMOS image sensor having a first pinned photodiode and a second pinned photodiode, the first pinned photodiode collects a charge when light strikes the first pinned photodiode, the second pinned photodiode receives the charge from the first pinned photodiode, and a plurality of electrodes in series located between the first and the second pinned photodiodes, the plurality of electrodes are configured to transfer the charge from the first pinned photodiode to the second pinned photodiode. The plurality of electrodes may be activated consecutively at different cycles. 
     In one embodiment, the time delay integration CMOS image sensor may include a plurality of readout nodes coupled to the second pinned photodiode via address lines. The number of readout nodes may be equal to the number of pinned photodiodes. The plurality of electrodes, the plurality of readout nodes and the address lines may form an orthogonal or hexagonal grid around the perimeter of each pinned photodiode. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The exact nature of this invention, as well as the objects and advantages thereof, will become readily apparent from consideration of the following specification in conjunction with the accompanying drawings in which like reference numerals designate like parts throughout the figures thereof and wherein: 
         FIG. 1  is a prior art pinned photodiode with transfer gate and floating diffusion. 
         FIG. 2  illustrates the charge transport from the prior art pinned photodiode to the floating diffusion. 
         FIG. 3  is a timing diagram of the logic level for the transfer gate in  FIG. 2 . 
         FIGS. 4-8  illustrate charge transport in a CMOS image sensor, according to an embodiment of the invention. 
         FIG. 9  is a timing diagram of the logic level for the first electrode in  FIGS. 4-8 . 
         FIG. 10  is a timing diagram of the logic level for the second electrode in  FIGS. 4-8 . 
         FIG. 11  is a two dimensional time delay integration visible CMOS image sensor, according to an embodiment of the invention. 
         FIG. 12  is a two dimensional time delay integration visible CMOS image sensor, according to an embodiment of the invention. 
         FIG. 13  illustrates lateral charge transport in a two dimensional time delay integration visible CMOS image sensor, according to an embodiment of the invention. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Photodiodes are widely used in digital imaging devices to convert optical signals into electrical signals. Photodiodes may be arranged in linear or planar arrays with a plurality of photosensitive sensors, generally designated as pixels, on a semiconductor chip. Each pixel generates an output signal representing the amount of light incident on the pixel. 
     A pinned photodiode (PPD) is used to produce and integrate photoelectric charges generated in CCD or CMOS image sensors.  FIG. 1  is a prior art pinned photodiode  11  with transfer gate  13  and floating diffusion  15 . The pinned photodiode  11  generates a charge  17  while maintaining a fixed or pinned Fermi level  19 . Regardless of the potential next to the Fermi level  19  of the pinned photodiode  11 , the Fermi level  19  of the pinned photodiode  11  does not change. 
     Using the pinned photodiode  11  with transfer gate  13  allows for complete charge removal from light sensing area to the floating diffusion  15 .  FIG. 2  illustrates the charge transport from the pinned photodiode  11  to the floating diffusion  15 .  FIG. 3  is a corresponding timing diagram of the logic level for the transfer gate  13 . In the first state  21 , the charge  17  is collected by the pinned photodiode  11 . The voltage on transfer gate  13  is zero in the first state  21 . Next, in the second state  23 , a positive voltage is applied to the transfer gate  13 . This applied voltage attracts the charge  17  to move underneath the transfer gate  13 , as shown in  FIG. 2 . Since the applied voltage decreases the quasi-Fermi level  19  underneath the transfer gate  13 , charge  17  cannot move back to the pinned photodiode  11 . In the third state  25 , the applied voltage on transfer gate  13  is set to zero. Since the floating diffusion  15  has a quasi-Fermi level  19  that is lower than the Fermi level  19  of pinned photodiode  11 , the charge  17  will move across to the floating diffusion  15 . 
     Combining two transfer gates or electrodes in series provides charge transport from one pixel to the next.  FIGS. 4-8  illustrate charge transport in a CMOS image sensor  27 , according to an embodiment of the invention. The CMOS image sensor  27  has two or more electrodes  29  between pinned photodiodes  31 . By using two or more electrodes  29 , charge  36  can be moved from one pinned photo photodiode  31  to another. Preferably, the charge  36  moves at about the same speed as a moving image scene. 
       FIG. 4  shows a first electrode  32  and a second electrode  34  between pinned photodiodes  31 . The CMOS image sensor  27  may have a plurality of pinned photodiodes  31  with electrodes  32  and  34  in between. Control logic may be used to operate the first electrode(s)  32  simultaneously. Control logic may also be used to operate the second electrode(s)  34  simultaneously and consecutive to the operation of the first electrode(s)  32 .  FIGS. 9 and 10  is an exemplary timing diagram of the logic level for the first electrode(s)  32  and second electrode(s)  34 , respectively. 
     In operation, the CMOS image sensor  27  allows charge(s)  36  to travel from one pinned photo photodiode  31  to another. Initially, in  FIG. 4 , pinned photodiode  31  collects charge(s)  36  while maintaining a fixed or pinned Fermi level  38 . Regardless of the potential next to the Fermi level  38  of the pinned photodiode  31 , the Fermi level  38  of the pinned photodiode  31  does not change. No voltage is applied to the first and second electrodes  32  and  34 . 
     Next, in  FIG. 5 , the first electrode  32  is activated by applying a voltage for a predetermined period. This voltage attracts the charge  36  to move underneath the first electrode  32 . Since the applied voltage decreases the quasi-Fermi level  38  of the first electrode  32  by creating a well, charge  36  cannot move back to the pinned photodiode  31 . 
     In  FIG. 6 , the second electrode  34  is activated by applying a positive voltage for a predetermined period. The voltage applied to the second electrode  34  is preferably greater than or equal to the voltage applied to the first electrode  32 . The voltage applied to the second electrode  34  attracts the charge  36  to move underneath the second electrode  34  as well. The applied voltage decreases the quasi-Fermi level  38  of the second electrode  34  to allow charge  36  to distribute under both electrodes  32  and  34 . 
     In  FIG. 7 , the applied voltage for the first electrode  32  is set to zero. This resets the potential of the first electrode  32  and collapses the well underneath the first electrode  32 . Since the second electrode  34  is still activated, the quasi-Fermi level  38  of the second electrode  34  will be lower than the quasi-Fermi level  38  underneath first electrode  32  and photodiode  31 . Consequently, the charge  36  that was underneath the first electrode  32  will move across and remain underneath the second electrode  34 . 
     In  FIG. 8 , the applied voltage for the second electrode  34  is set to zero. This resets the potential of the second electrode  34  and collapses the well underneath the second electrode  34 . Since the pinned photodiode  31  has a predetermined fixed Fermi level  31 , the charge  36  underneath the second electrode  34  will move across to the adjacent pinned photodiode  31 . Consequently, lateral charge  36  transport occurs in the CMOS image sensor  27 . 
     According to an embodiment of the invention, the lateral charge  36  transport occurs over a 4 cycle period, as shown in  FIGS. 9 and 10 . A person skilled in the art would appreciate that different cycles may be used without departing from the spirit of the invention. In the first cycle, the first electrode  32  is activated by applying a positive voltage. In the second cycle, the second electrode  34  is activated as well by applying a voltage. In the third cycle, the first electrode  32  is deactivated by setting the voltage applied to the first electrode  32  to zero. In the fourth cycle, the second electrode  34  is deactivated by setting the voltage applied to the second electrode  34  to zero. 
     As shown in  FIGS. 4-8 , the CMOS image sensor  27  has a plurality of pinned photodiodes  31  with at least two electrodes  32  and  34  in between. Electrodes  32  operate at a different phase than electrodes  34  to allow charge  36  to move from underneath one electrode to the other. The phase relationship between electrodes  32  and electrodes  34  defines the transport direction of the charge  36 . For example, control logic may be used to alternate the phase shift between the electrodes  34  and  34  such that the charge  36  moves from photodiode  31  adjacent to the second electrode  34 , to underneath second electrode  34 , to underneath first electrode  32 , and finally to the photodiode  31  adjacent to the first electrode  32 . 
       FIG. 11  is a two dimensional time delay integration visible CMOS image sensor  40 , according to an embodiment of the invention. The sensor  40  has an active array of pixels  42 , each pixel  42  may include a pinned photodiode  44  with four orthogonal electrodes  46 ,  47 ,  48  and  49 . The pixels  42  are interconnected in a grid with readout nodes  50  and address lines  52 . The address lines  52  control the voltage on electrodes  46 ,  47 ,  48  and  49 . Through an additional transfer gate (not shown) between photodiode  44  and readout node  50 , the signal charge can be transferred to the readout node  50  at the end of a TDI cycle. In one embodiment, the sensor  40  has a readout node  50  for every photodiode  44 . 
     With moving scene imagery, pinned photodiode  44  of the time delay integration visible CMOS image sensor  40  generates a charge that moves in two dimensions at about the same speed and follows a similar path as the moving image. Similarly, mechanical vibrations of a camera cause random walk of any image point on the sensor  40 .  FIG. 11  illustrates the two dimensional charge transport directions  54  and  56 . The charge moves laterally from one photodiode  44  to another. This lateral movement of charge provides improved charge integration from the moving scene. Since there are multiple readout nodes  50  distributed evenly in the sensor  40 , photo-generated signals may be read at any point in the array closest to the readout node  50 , rather than transporting the charge for readout down or up stream. This provides high frame rate capability with improved signal to noise ratio for the sensor  40 . 
     To better approximate the curved random walk of a scene, the sensor may be configured to allow for charge transport in three or more directions.  FIG. 12  illustrates charge transport in three directions  62 ,  64  and  66  for a two dimensional time delay integration visible CMOS image sensor  60 , according to an embodiment of the invention. The sensor  60  has an active array of pixels  68 , each pixel  68  may include a pinned photodiode  70  with six electrodes  72 ,  74 ,  76 ,  78 ,  80  and  82 . The pixels  68  are interconnected in a polygonal grid, such as a hexagonal grid, with readout nodes  84  and address lines  86 . The address lines  86  control the voltage on the electrodes  72 ,  74 ,  76 ,  78 ,  80  and  82 . Through an additional transfer gate (not shown) between photodiode  70  and readout node  84 , the signal charge can be transferred to the readout node  70  at the end of a TDI cycle. In one embodiment, the sensor  60  has a readout node  84  for every photodiode  70 . 
     With moving scene imagery, pinned photodiode  70  of the time delay integration visible CMOS image sensor  60  generates a charge that moves in two dimensions at about the same speed and follows a similar path as the moving image. Similarly, mechanical vibrations of a camera cause random walk of any image point on the sensor  40 .  FIG. 13  illustrates lateral charge transport in sensor  60 . Due to the hexagonal grid configuration, the charge travels in a smooth path  88  that follows the moving image. This lateral movement of charge provides improved charge integration from the moving scene. Since there are multiple readout nodes  84  distributed evenly in the sensor  60 , photo-generated signals may be read at any point in the array closest to the readout node  84 . This provides high frame rate capability with improved signal to noise ratio for the sensor  60 . 
     A person skilled in the art would appreciate the potential applications of the two dimensional time delay integration visible CMOS image sensor of the present invention. The sensor may be used for translational image stabilization during single frame integration time. For example, very high bandwidth of translational vibrations can be stabilized from about 30 Hz to about 1 MHz. The maximum translational vibration amplitude may be limited by imager resolution. The sensor may also be used for rotational image stabilization during single frame integration time. For example, very high bandwidth of rotational movement can be stabilized from about 30 Hz to about 1 MHz. The maximum rotational vibration amplitude may be limited by pixel size and tolerable distortions. 
     Other applications of the sensor include residue light photography without tripod or flash, TDI camera with increased alignment tolerance and flow cytometry for capturing images of moving cells in fluids. The sensor may also be used, in combination with a stabilized gimbal, to enhance pointing accuracy to a few tens of grads. Additionally, the sensor may be used with Inertial Measurement Unit (IMU) to suppress random motion. Depending on frame rate, IMU may be replaced with processing algorithm. 
     While certain exemplary embodiments have been described and shown in the accompanying drawings, it is to be understood that such embodiments are merely illustrative of and not restrictive on the broad invention, and that this invention not be limited to the specific constructions and arrangements shown and described, since various other changes, combinations, omissions, modifications and substitutions, in addition to those set forth in the above paragraphs, are possible. Those skilled in the art will appreciate that various adaptations and modifications of the just described preferred embodiment can be configured without departing from the scope and spirit of the invention. Therefore, it is to be understood that, within the scope of the appended claims, the invention may be practiced other than as specifically described herein.