Patent Publication Number: US-7590721-B2

Title: Reordering sequence based channels

Description:
RELATED APPLICATION INFORMATION 
   This patent is a continuation of application Ser. No. 10/295,399 filed Nov. 14, 2002. 

   FIELD OF THE INVENTION 
   The present invention is related generally to the operation of switching networks, and more particularly, to a system for reordering sequence based packet segments in a switching network. 
   BACKGROUND OF THE INVENTION 
   Communications networks now require the handling of data at very high data rates. For example, 10 gigabits per second (Gbps) is common. When it is required to process data at these speeds, multiple high-speed parallel connections may be used to increase the effective bandwidth. However, this may result in one or more transmission problems, since the data streams must be divided to be distributed over the multiple parallel connections, and at some point after parallel transmission, recombined to form the original streams. 
     FIG. 1  shows a block diagram  100  of a typical network structure for transmitting data frames (or data packets) from source processors  102  to a destination processor  104  via network fabrics  106 . The data streams include frames that may comprise a fixed amount of data. For example, stream A may include frames A 0 , A 1 , and A 2  that are received by the source processor A and transmitted to each of the fabrics as shown. The stream B may include frames B 0 , B 1  and B 2  that are transmitted to the fabrics by source processor B as shown, and the stream C may include frames C 0 , C 1  and C 2  that are transmitted to the fabrics by source processor C as shown. 
   Once the frames are received by the fabrics, they are transmitted to the destination processor  104 . The destination processor receives the frames in the order they arrive and combines them for transmission to another network entity, as shown by stream D. 
   A significant problem that exists with current transmission systems, such as the system shown in  FIG. 1 , is that the frames may end up in the wrong order when transmitted from the destination processor D. For example, the frames may be output in the order shown at  108 . In this case, frame B 2  is output before frame B 1 , and frame C 2  is output before frame C 1 . Thus, the frames received from source processors B and C are transmitted from the destination processor  104  out of order. In such a case, it may be necessary to discard the out of order frames of data and request a new transmission of those frames. As a result, additional overhead will be used and a corresponding loss of transmission bandwidth will be realized. 
   Additional problems can occur in systems where the transmitted data frames have been segmented before transmission. In these systems, it is possible that both the frames and/or individual segments of each frame are transmitted out of order. Thus, even if the frames maintain the correct order with respect to a transmitting source processor, segments within the frames may be out of order. 
   Therefore, it would be desirable to have a way to reorder frames of data in a transmission system so that the frames are output in the correct order, thereby improving transmission efficiency. Furthermore, it would also be desirable to have a way to reorder frame segments so that both the frames and their corresponding segments are output in the correct order. 
   SUMMARY OF INVENTION 
   The present invention includes a system for reordering sequence based packet segments in a switching network. For example, in one embodiment of the invention, a reordering system is provided that receives packet segments from multiple sources and reorders the received packet segments based on sequence information associated with each segment so that both the segments, and frames constructed from the segments, are output from a destination processor in the correct order. 
   In one embodiment included in the present invention, a system is provided for reordering packet segments in a packet switch network, wherein a plurality of source processors transmit the packet segments to a destination processor via one or more network fabrics. The system comprises encoder logic at each source processor that operates to associate a unique segment identifier with each of the packet segments before they are transmitted. The system also comprises a memory and map logic located at the destination processor that operate to receive the packet segments, map the segment identifier associated with each of the packet segments to a memory region in the memory, and store each received packet at its respective memory region. The system also comprises a Dequeue processor coupled to the memory and operable to determine when enough packet segments are stored in the memory to form a complete data frame. When enough packets are received, the Dequeue processor operates to output the packet segments that form the complete data frame. 
   In another embodiment included in the present invention, a method is provided for reordering packet segments in a packet switch network, wherein a plurality of source processors transmit the packet segments to a destination processor via one or more network fabrics. The method comprises steps of: including a segment identifier with each of the packet segments before they are transmitted from the source processors; defining one or more memory regions in a memory located at the destination processor; mapping the segment identifier associated with each received packet segment to a selected memory region, wherein the received packet segment is stored at the selected memory region; updating a memory map; identifying when enough packet segments have been received to form a complete data frame; and outputting the complete data frame. 

   
     BRIEF DESCRIPTION OF DRAWINGS 
     The foregoing aspects and the attendant advantages of this invention will become more readily apparent by reference to the following detailed description when taken in conjunction with the accompanying drawings wherein: 
       FIG. 1  shows a block diagram of a typical network structure for transmitting data frames from source processors to destination processors; 
       FIG. 2  shows a diagram showing one embodiment of a system for reordering segments constructed in accordance with the present invention; 
       FIG. 3  shows a diagram of one embodiment of a segment encoder for use in a source processor; 
       FIG. 4  shows a diagram of one embodiment of a reordering system constructed in accordance with the present invention; 
       FIG. 5  shows one embodiment of a memory for use in the reordering system of  FIG. 4 ; 
       FIG. 6  shows a diagram of one embodiment of a mapping system for use in the reordering system of  FIG. 4 ; 
       FIG. 7  shows one embodiment of a memory map for use in the reordering system of  FIG. 4 ; and 
       FIG. 8  shows a flow diagram for reordering segments in accordance with the present invention. 
   

   DETAILED DESCRIPTION OF PREFERRED EMBODIMENT 
   The present invention includes a system for reordering sequence based packet segments in a switching network. For example, in one embodiment of the invention, a reordering system is provided that receives packet segments from multiple sources and reorders the received packet segments based on the transmitting source, a sequence number, and a priority level associated with each segment. Thus, various embodiments of the system included in the present invention are discussed in detail in the following text. 
   Exemplary Embodiment 
     FIG. 2  shows a diagram of one embodiment of a reordering system  200  constructed in accordance with the present invention for reordering packet segments in a switching network. The system  200  includes source processors  204  that each include a segment encoder  202  that operates to segment data frames included in the streams received by each source processor, and encode each segment in accordance with the present invention. 
   During operation of the system  200 , the source processors  204  receive data streams containing data frames. The segment encoders  202  operate to segment each of the data frames into packet segments and encode a unique sequence identifier for each segment prior to transmitting them to one or more fabrics  206 . In one embodiment of the invention, the segment encoders  202  also assign a priority to each segment in addition to the sequence identifier. Thus, each segment that is transmitted to the fabrics  210  includes a sequence identifier, and optionally, priority information. Furthermore, an identifier that identifies the transmitting source processor is included with each segment. The addition of the source identifier to the segments may be part of the operation of the source processors  204 , or may be part of the operation of the segment encoders  202 . 
   Any technique can be used to include sequence identifiers and/or priority levels with the packet segments. For example, the segment encoders can encode sequential sequence numbers into header information included with each segment. The priority indicator can be selected from one of several priority levels and also encoded into segment header information. Thus, any suitable technique can be used within the scope of the invention to associate a sequence identifier and priority information with each data segment. 
   The system  200  also includes a segment reordering system  206  at a destination processor  208 . The reordering system  206  operates to receive the packet segments from the fabrics  210  and process the segments based on their respective sequence identifiers and priorities to reorder the segments, and thereby the frames, into the same order as when transmitted by the source processors. Thus, frames are reordered so that with respect to each source processor, the frames are placed in an identical order as when transmitted. 
   In  FIG. 2 , frames A, B, and C are transmitted from the source processors to the destination processor via the network fabrics. Each frame includes one or more segments that have been encoded with sequence numbers by the segment encoders associated with the source processors. Although  FIG. 2  shows that each frame is transmitted to the destination via a selected network fabric, it is also possible that the segments within a frame are transmitted to the destination using multiple fabrics. Thus, the frames and corresponding segments may be transmitted to the destination using one or multiple fabrics, and the segment reordering system located at the destination will reorder the segments and frames to have the same order as when transmitted by their respective source processors. Therefore, the stream D includes all the frames in correct order, as shown at  212 , and each frame includes segments that also have the correct order. 
   The destination processor may operate on the reordered data frames and segments in other ways to facilitate their transmission, but these other processes are not essential to the operation of one or more embodiments of the invention, and so will not be described in detailed. For example, the destination processor may serialize the frames for transmission, or provide known error detection and correction processes that are independent from the reordering system. 
     FIG. 3  shows a diagram of one embodiment of a segment encoder  202  constructed in accordance with the present invention, for use in a source processor  204 . A source receiver  302  receives a data stream  304  that contains frames of data. The source receiver transfers the received stream to segmentation logic  306 . The segmentation logic  306  segments the frames of data into frame or packet segments. For example, the data frames included in the stream are segmented into 64-byte segments. 
   The segmented frames are transferred to sequence and priority logic  308 . The logic  308  operates to associate a sequence identifier with each of the segments it receives. For example, the sequence identifier may be a 10-bit sequence number and the segments are encoded with a consecutive sequence numbers. Furthermore, the logic  308  optionally operates to associate a priority indicator with each segment, where all segments within a frame are given the same priority level. For example, a 3-bit priority level indicator provides eight priority levels. However, any number of priority levels is suitable for use with the present invention. 
   Once the segments have been processed to include sequence identifiers, and optionally, a priority indicator, they are transferred to a source transmitter  310  where they are transmitted from the source processor to a destination processor via one or more network fabrics. As part of the transmission process, each segment will include a transmitting source identifier. 
     FIG. 4  shows a diagram of one embodiment of a segment reordering system  206  constructed in accordance with the present invention for use in a destination processor, for example, the destination processor  208  in  FIG. 2 . 
   The basic function of the segment reordering system  206  is to keep track of the order of all of the segments as they are received at the destination processor. In one or more embodiments, a combination of the source identifier, unique sequence number, and priority assigned to each segment and inserted into the segment header prior to transmission from the source processors are used to track the segments. At the reordering system, the transmitting source identifier and the priority will be used to sort and store the segments into one of 320 reorder queues (assuming 64 source processors and 5 priority levels). The unique sequence number, associated with a particular queue, will be used to index a segment into its proper location in a memory. The segment reordering system also reassembles the segments into frames before sending them on to a transmitter for transmission to other network entities. 
   A segment receiver  402  receives one or more data streams  412  that are transmitted to the destination processor via one or more network fabrics. For example, the receiver  402  receives the streams  412  via the fabrics  210 . The receiver  402  is coupled to a memory  404  and segment processing logic  406 . The segment processing logic  406  operates to process the source identifier, the sequence identifier, and the priority level associated with each segment to determine a free memory location in the memory  404  where each segment will be stored. The processing logic  406  also operates to update a memory map  414  that indicates used and unused portions of the memory  404 . Another function of the processing logic is to update and maintain a set of pointers  418  that are used to indicate the segments that have been received. If there are enough received segments to form a complete frame, the complete frame is transmitted to another destination. The processing logic  406  may comprise any suitable hardware such as a CPU, gate array or other hardware logic, and may also include any suitable software to operate in conjunction with the hardware. 
   The memory  404  may comprise any suitable memory type or technology, such as RAM, DRAM or FLASH memory. Included in the memory  404  is the memory map  414  that is used to indicate used and unused portions of the memory. The memory map  414  allows the memory  404  to be efficiently utilized, and thus minimize the required total memory. The memory is designed to allow high-speed operation of the network fabrics. In one embodiment, the memory has a size of four megabytes (4M), however, larger or smaller memories may be used in accordance with the present invention. A more detailed discussion of the memory  404  and the memory map  414  is provided in another section of this document. 
   Segment Dequeue logic  408  is coupled to the memory  404  via control channel  422  and operates to control the output of reordered segments into reassembled frames. For example, in one embodiment, the Dequeue logic  408  operates to control the transfer of segments from the memory to the segment transmitter  410  based on block values it receives from the memory map  414  and the pointers  418 . A communication channel  420  couples the Dequeue logic  408  with the segment processing logic  406  so that the Dequeue logic can access the pointers  418 . The pointers  418  ( FIG. 4 ) are used to provide an indication of the segments that have been received and stored in the memory  404 . The pointers are also used to remove the segments from the memory to perform the reordering process and reassembly of frames. The pointers are updated as each received segment is stored in the memory  404 . The Dequeue logic may comprise any suitable hardware such as a CPU, gate array or other hardware logic, and may also include any suitable software to operate in conjunction with the hardware. 
   A segment transmitter  410  receives segments transferred from the memory  404  by the Dequeue logic  408  and transmits these segments, and the reassembled frames they comprise, in the correct order to other entities in the network via a transmitter output  416 . Thus, the reordering system  206  operates to perform reordering of segments and the reassembly of frames in accordance with the present invention. 
     FIG. 5  shows one embodiment of a memory structure  500  included in the memory  404  for use in a reordering system in accordance with the present invention. The memory structure  500  represents one memory structure, however, other memory structures are suitable for use in accordance with the present invention. Thus,  FIG. 5  is exemplary and not intended to limit the scope of the invention to a particular memory structure. 
   The memory structure  500  includes a segment memory  502  coupled to a memory controller  504 . The segment memory comprises a 64K portion of memory for each transmitting source. The 64K portion of memory is grouped into 16 blocks ( 0 - 15 ) with each block having the capacity to store 64 segments each having 64-bytes. 
   The memory controller  504  is coupled to all the 64K portions of memory so that segment data  506  may be stored and retrieved from any memory location based on a received memory address  508 . The memory controller comprises any suitable hardware logic and/or associated software to access the memory  502 . 
   In one embodiment, each memory portion comprises a total of 65536 (64K) bytes of storage that is dedicated to each transmitting source processor. If there are sixty-four source processors transmitting segment data, the memory  404  is sized to have a capacity of 4,194,304 bytes (4 Mbytes). 
     FIG. 6  shows a diagram of one embodiment of the memory map  414  that includes segment processing logic  650  and map tables  652  constructed in accordance with the present invention for use in the reordering system of  FIG. 4 . The segment processing logic  650  includes a segment decoder  603  that receives segment data from the segment receiver  402  and operates to decode sequence  604 , priority  606 , and transmitting source  608  information for each received segment. The sequence identifier  604 , priority  606 , and source identifier  608  are input to a map processor  602  that operates to output a memory address  508  that is formed from a portion of the sequence identifier  612 , a memory block address  614  that is obtained from the map tables  652 , and the source identifier  608 . The map processor  602  also includes an interface  642  to the map tables  652 . The map processor  602  may comprise any suitable hardware such as a CPU, gate array or other hardware logic, and may also include any suitable software that operates in conjunction with the hardware. 
   The map processor  602  is coupled to the memory tables  652  via a bus  618 . The memory tables include a free list FIFO  620 , a priority  0  table list  622 , a priority  1  table list  624 , a priority  2  table list  626 , a priority  3  table list  628 , and a priority  4  table list  630 . 
   Associated with each priority table list is a valid list that contains valid bits. For example, the table list  622  is associated with valid list  632 , the table list  624  is associated with valid list  634 , the table list  626  is associated with valid list  636 , the table list  628  is associated with valid list  638 , and the table list  630  is associated with the valid list  640 . 
   The group of memory lists are used to store the indirect location of the selected memory block  502  where the segment data is written. A set of these same lists exists for each source processor that is transmitting segment data to the destination. Therefore, if there are sixty-four source processors transmitting segment data, there will be sixty-four groups of memory lists. For example, as shown at  642 , there are sixty-four bus connections that connect the map processor  602  to sixty-four groups of lists that are used to store segment data from sixty-four transmitting source processors. Although the memory lists shown are based on five priority levels, more or less priority levels may be used and result in a corresponding number of memory lists. 
   The map processor  602  operates to map segment data into the memory  404  for storage. The map processor uses the source identifier  608  to select which group of lists to use to map the segment data. For example, if the source identifier is twenty-three, the group of lists used may be the group of lists shown in  FIG. 6 . The map processor  602  uses the priority information included with each segment to selected one of the priority table lists. For example, if the priority associated with a segment is priority  1 , then the map processor uses priority table list  1 , shown at  624 , to map the segment data. 
   The map processor  602  uses the sequence identifier included with each segment to indirectly map a block in the selected priority table list to a block in the memory  404  where the segment will be stored. For example, the map processor uses the upper four bits of the sequence identifier to select one of sixteen entries in the selected priority table list. The contents of the entry in the selected priority table list will be used as the block address  614 . 
   However, if the entry in the selected priority list contains an invalid block address, then the map processor operates to obtain an available block memory address from the free block list  620 . The map processor enters this newly obtained block address into the entry in the selected priority table list, and validates the valid bit. Thereafter, sequence numbers whose upper bits point to this entry in the selected priority table list will obtain this block address to be used to store the segment data. The valid lists contain bits that indicate whether an address in the corresponding priority table lists is valid. These bits are validated or invalidated depending if the specific block of memory is being used or if all of the segments in that block have been sent. 
   An example of the mapping process will now be described. Assume the memory  404  is configured to have a total of four Megabytes of storage. This allocation will support segments transmitted from sixty-four source processors; each allocated 64 k bytes to store all of their incoming segments. These 64 k bytes will be further subdivided into 16 blocks representing a total of 1024 segment storage locations. Each segment storage location contains a block of 64 bytes of data. The incoming segment will be stripped of its segment header and CRC, and the remaining 64-byte segment payload will fit within the 64-byte block. 
   The 16 blocks (or groups) representing a total of 1024 segment storage locations can be dynamically allocated to any of the segment priorities as needed. The four MSB&#39;s of the sequence number included with each segment indirectly maps into one of these 16 blocks of memory. The mapping is stored in the priority lists and any unused groups are stored in the free list FIFO  620 . 
   The free list FIFO  620  hold 16 group addresses. Each group address is 4-bits wide and directly maps to a memory address as the block address  614 . There are a total of 64 free list FIFOs, one for each transmitting source. 
   There are 5 priority table lists and each can store up to 16 block addresses. The valid bit associated with each entry will determine if a valid block address is stored in that entry. After initialization or reset, the free list FIFO  620  will contain all 16 block addresses and all of the valid bits associated with the priority table lists will be cleared to indicate that no entries in the lists are valid. 
   When a segment arrives, the four most significant bits (MSB) of the sequence number  604  are used to find the block address  614  that the segment should be written to in the memory  404 . The source  608  and priority  606  of the segment will determine which priority table list to use, and the four MSB&#39;s of the sequence number  604  will be used to address into that table to find a selected entry. 
   First, the valid bit for the selected entry will be checked to determine if a group has already been assigned to the sequence number. If a group has been assigned, the valid bit will be a one, and the contents of that entry will be used as the block address  614  for addressing the memory  404 . If the valid bit is not set, then a new group will be obtained from the free list FIFO  620 , inserted into the table list at the selected entry, and the corresponding valid bit will be set to a one. Thus, segments that follow having the same source, priority, and four MSB sequence number will use this new group address. 
   In this example, it will be assumed that a segment is received from a source processor having a source identifier  608  of twenty-three with a priority of zero, and the four MSB&#39;s of the sequence number are 0011. A check in the priority  0  table list  622  at entry three shows that the valid bit is zero, as indicated at  644 . A new address group is needed and the map processor operates to obtain it from the free list FIFO  620 . The new address group has the value 0111 and is inserted into the table list  622  at entry three and will also be used as block address  614  to access the memory  404 . The valid bit at entry three will then be set to a one to indicate that the address is valid (not shown in the  FIG. 6 ). 
   The lower 6 bits of the sequence number  604  are directly mapped into one of the 64 memory blocks as the sequence address  612 . If another segment comes in from transmitting source twenty-three with a sequence number of (0100xxxxxx binary) and a priority of two, the map processor  602  will map a value of 1111 to the block address  614 . This value is determined from the priority  2  table list as shown at  626 . Also shown is the control channel  422  that allows information from the map processor to flow to the Dequeue logic during the dequeue process. 
     FIG. 7  shows one embodiment of the pointers  418  for use in a reordering system in accordance with the present invention. The pointers  418  include a map list  702  and a map pointer  704  for each priority level transmitted by each source processor. Therefore, since there are five priority levels in the present example, there are five map lists  702 ( 1 - 5 ) and five map pointers  704 ( 1 - 5 ) per transmitting source processor. In a system where there are sixty-four transmitting source processors and five priority levels, the total number of map list  702  and associated map pointer  704  sets will be  320 . 
   The map list  702  includes a current frame segment (CFS) pointer  706  and a first invalid segment (FIS) pointer  708 . The CFS pointer is the location of a segment that contains the start (head) of a frame currently being stored in the memory  404 . The FIS pointer  708  is the first location, relative to the CFS, indicating where a segment has not yet arrived. In other words, it is the next missing segment in a series of segments starting from the CFS pointer. Values for both the CFS and FIS pointers are entered into the map pointer  704 . 
   The map pointer  704  also includes a length value  710  and an offset value  712 . The length value is the total length of the single frame (in bytes), whose head is located at the CFS pointer. The length value can be found at the head of a segment or it may be embedded within a segment if the frame ends within the segment and the next frame is packed at the tail of the ending frame. The offset value, measured in bytes, determines where the frame head starts within a segment. Again, the offset value can be found at the head of a segment, for example, by receiving a segment with an offset of zero or extracted from a segment while de-queuing. 
   The map list  702  keeps track of all the segments that have arrived and are ready to be reordered. For one source/priority, the corresponding map list contains 1024 bits of data. These bits directly map to the 1024 segment storage locations in the memory  404 . The sequence number is used to directly map the bits in the map list to the segments that are stored in memory. As a result, a bit in the map list will be set valid when a segment arrives, and cleared when the segment is de-queued. 
     FIG. 8  shows a flow diagram  800  for reordering segments in accordance with the present invention. At block  802 , data frames are received at one or more source processors for transmission to a destination processor via one or more network fabrics. 
   At block  804 , the frames are segmented and are encoded with a sequence identifier, a priority value and a source identifier. In one embodiment, the segment data payload is 64-bytes long. At block  806 , the segments are transmitted to a destination processor via one or more network fabrics. 
   At block  808 , the transmitted segments are received at a destination processor. The destination processor receives segments from one or more transmitting source processors via the network fabrics. 
   At block  810 , the source identifier, priority level, and sequence identifier are extracted from each received segment. For example, the segment decoder  603  extracts this information from each received segment. At block  812 , the extracted information is used to determine a memory address in a memory where each segment is stored. For example, as shown in  FIG. 6 , the map processor  602  operates to use the extracted information received from the decoder  603  to index into the map  414  to determine at least a portion of the memory address where a received segment will be stored. 
   At block  814 , each received segment is stored into memory at the address determined from the previous step. At block  816 , the pointers  418  are updated to reflect how many segments have been received. 
   The above steps describe the flow of segment data from transmitting source processors to a destination processor via one or more network fabrics. Once the segments are received at the destination processor, they are stored into a memory in accordance with the above steps. The following steps are used to unload the segments from the memory for transmission to another network entity. In the process of unloading the segments, the segments and corresponding data frames are reordered in accordance with the invention. It should be noted that the reception, reordering, and transmission of frames as described by the reordering process of  FIG. 8  is a continuous process. Therefore, frames may continue to be received during the reorder and transmission processes. 
   At block  818 , a frame check is performed to determine if enough segments have been received and stored into the memory to form a complete frame. For example, as segments are received and stored in the memory, and map lists are used to keep track of the sequential number of segments that have been received. For example, if the memory map as provided in  FIG. 7  is used, the CFS pointer, the FIS pointer, the table entries, the length, and the offset values are used to calculate if a frame is contained within the two pointers. If it is determined that a complete frame has been received and is stored in the memory, a ready flag that is associated with the context that was just checked is activated to indicate that a frame can be dequeued. 
   At block  820 , assuming a complete frame has been received the completed frame is unloaded from the memory. The logic reads the CFS and FIS pointers and length from the associated context that was selected and dequeues the associated frame. 
   At block  822 , a test is performed after the current frame is unloaded to determine if there are enough segments in memory to unload another frame. For example, there may be another frame beginning with the next segment directly after the current frame that was unloaded. In another situation, there may be another frame that is partially packed within the last segment of the current frame. For example, the header for the next frame is packed into the last segment of the current frame. If there are no other complete frames to unload, the method proceeds to block  824 . If there is another frame to unload, the method proceeds back to block  820 . 
   When the frames are being unloaded, the CFS pointer will be updated to the point where the last frame ended to become the new CFS pointer. If another frame is found, the length of that next frame, the FIS pointer, and the new CFS pointer are used to determine if next frame can be dequeued. This process will continue until there are no more frames that can be dequeued. 
   At block  824 , when there are no more frames to be dequeued, the Dequeue logic writes back the new CFS pointer, length and offset to the Context Memory. The new CFS pointer will be pointing to indicate the location of the start of the next frame in memory. 
   At block  826  the memory usage maps are updated. For example, the last function that is performed is that all of the valid bits from the old CFS pointer to the new CFS pointer are cleared, and if any memory blocks need to be de-allocated, they are put back onto the free list FIFO  620  so that they may be reused to store additional received segments. The method then continues at block  818 . 
   In accordance with the present invention, segments transmitted from a particular source are reordered to have the same order as when initially transmitted. Therefore, one or more embodiments included in the present invention provide a system for reordering segments in a switching network. After the context is dequeued, and there are no more frames that can be dequeued from that context, the Dequeue logic clears the selected ready flag. The segments associated with the frame are read out of the memory. The frames are then passed to the segment transmitter  410  and the frames/segments are sent on to the next destination in the system. 
   Thus, the present invention includes a system for reordering packet segments in a packet switch network. The embodiments described above are illustrative of the present invention and are not intended to limit the scope of the invention to the particular embodiments described. Accordingly, while several embodiments of the invention has been illustrated and described, it will be appreciated that various changes can be made therein without departing from the spirit or essential characteristics thereof. Accordingly, the disclosures and descriptions herein are intended to be illustrative, but not limiting, of the scope of the invention, which is set forth in the following claims.