Patent Publication Number: US-7218169-B2

Title: Reference compensation circuit

Description:
FIELD OF THE INVENTION 
   The present invention relates generally to integrated circuit (IC) devices, and more particularly to improved techniques for compensating a circuit for variations in at least semiconductor process, voltage and/or temperature. 
   BACKGROUND OF THE INVENTION 
   Circuit designers often find it necessary to utilize high speed buffer circuits (e.g., input/output (IO) buffers) to meet increasing demands for speed and performance in IC devices. However, it has become more difficult to design faster buffer circuits due, at least in part, to significant variations in buffer circuit performance over different process, voltage and temperature (PVT) ranges. Such PVT variations can affect the stability of, for example, a slew rate and/or an output impedance in a pre-driver and output section, respectively, of the buffer circuit. The slew rate of a buffer circuit is generally defined as a maximum rate of change of output voltage level for a step change at the input (e.g., rate of change from a logical 0 state to a logical 1 state, or vice versa, at the output of a circuit). To ensure signal integrity and slew rate stability, the buffer circuit is typically designed to operate well below some predefined minimum acceptable slew rate. 
   Under normal operating conditions, a buffer circuit may be subjected to variations in supply voltage and/or temperature, among other factors. In many applications, the buffer circuits are expected to operate over a relatively wide temperature range, such as, for example, −55 degrees Celsius (° C.) to 125° C. Generally, slew rate falls significantly as temperature rises. Power supply variations in a range of about ±10 percent may also be expected and can contribute to instability in the buffer circuit. Process variations resulting from IC fabrication can affect various characteristics of the buffer circuit including, but not limited to, threshold voltage, channel length and width, electron mobility, etc. Such characteristics may even vary among two different transistors manufactured on the same semiconductor wafer. 
   Previous solutions to compensate for PVT variations in a buffer circuit are described in, for example, U.S. Pat. No. 5,869,983 to Ilkbahar et al. entitled “Method and Apparatus for Controlling Compensated Buffers,” U.S. Pat. No. 5,898,321 to Ilkbahar et al. entitled “Method and Apparatus for Slew Rate and Impedance Compensating Buffer Circuits,” U.S. Pat. No. 6,040,737 to Ranjan et al. entitled “Output Buffer Circuit and Method that Compensate for Operating Conditions and Manufacturing Processes,” and U.S. Pat. No. 6,429,710 to Ting et al. entitled “Input Buffer with Compensation for Process Variation.” These known approaches, however, have several disadvantages associated therewith, including, but not limited to, inherent inaccuracies in the compensation technique and considerable complexity and/or cost. 
   There exists a need, therefore, for more accurate and cost effective buffer circuit compensation techniques that do not suffer from one or more of the problems exhibited by conventional methodologies. 
   SUMMARY OF THE INVENTION 
   The present invention meets the above-noted need by providing, in an illustrative embodiment, techniques for more accurately compensating for at least one of process, voltage and temperature variations in a circuit by generating one or more compensation signals based on characteristic information from both PMOS and NMOS devices. The PMOS and NMOS devices used to generate the compensation signal are preferably substantially matched to one or more PMOS and NMOS devices in the circuit to be compensated such that the compensation signal more accurately tracks PVT variations in the circuit. 
   In accordance with one aspect of the invention, a compensation circuit comprises a reference circuit including a reference NMOS device and a reference PMOS device. The reference circuit is operative to generate a first reference signal and a second reference signal, the first reference signal being a function of at least one of a process characteristic, a voltage characteristic and a temperature characteristic of the reference NMOS device, and the second reference signal being a function of at least one of a process characteristic, a voltage characteristic and a temperature characteristic of the reference PMOS device. The compensation circuit further comprises a control circuit connected to the reference circuit. The control circuit is operative to receive the first and second reference signals and to generate one or more output signals for compensating for a variation in at least one of a process characteristic, a voltage characteristic and a temperature characteristic of at least one NMOS device and at least one PMOS device in a circuit to be compensated, which is connectable to the control circuit, in response to the first and second reference signals, respectively. 
   In accordance with another aspect of the invention, the reference circuit is configurable for receiving a control signal, the reference circuit being operative in at least one of a first mode and a second mode in response to the control signal. In the first mode of operation, the reference circuit generates the first reference signal, and in the second mode of operation, the reference circuit generates the second reference signal. 
   These and other features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a schematic diagram depicting an illustrative reference circuit which may be modified to implement the techniques of the present invention. 
       FIG. 2  is a block diagram illustrating an illustrative compensated buffer circuit which may be modified to implement the techniques of the present invention. 
       FIG. 3  is a schematic diagram depicting an exemplary reference compensation circuit, formed in accordance with one embodiment of the present invention. 
       FIG. 4  is a block diagram depicting an exemplary compensated buffer circuit including the reference compensation circuit of  FIG. 3 , formed in accordance with another embodiment of the present invention. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
   The present invention will be described herein in the context of an illustrative buffer circuit including a reference circuit configured for compensating for PVT variations in the buffer circuit. It should be understood, however, that the present invention is not limited to this or any particular buffer circuit. Rather, the invention is more generally applicable to any circuit arrangement in which it is desirable to provide improved compensation techniques for accurately compensating for at least process, voltage and/or temperature variations in the circuit. Moreover, although implementations of the present invention are described herein with specific reference to a complementary metal-oxide-semiconductor (CMOS) fabrication process and to NMOS and PMOS transistor devices, it is to be appreciated that the invention is not limited to such a fabrication process and/or such transistor devices, and that other suitable process technologies, such as, but not limited to, bipolar, bipolar CMOS (BiCMOS), etc., and/or transistor devices, such as, but not limited to, bipolar junction transistors (BJTs), etc., may be similarly employed, as will be understood by those skilled in the art. 
   One method for compensating for PVT variations in a buffer circuit is to generate a reference voltage based on an n-type metal-oxide-semiconductor (NMOS) device. The reference voltage is compared against a predetermined set of voltage levels in a control block and digital bits are generated which represent the state of the NMOS device under that particular PVT point. These digital bits are then used to compensate for PVT variations in both p-type metal-oxide-semiconductor (PMOS) devices and NMOS devices in the buffer circuit. Thus, compensation information derived from an NMOS device is used to compensate for characteristic variations in a PMOS device. Unfortunately, using modern deep sub-micron semiconductor technology, the properties of PMOS and NMOS devices can vary significantly. Compensating PMOS devices based only on NMOS device characteristics is thus inherently inaccurate. For many standard applications, this compensation methodology may be sufficient. However, as buffer circuit tolerances become more and more stringent, it becomes increasingly more difficult to meet buffer specifications under all PVT corner points using this compensation scheme. 
     FIG. 1  is a schematic diagram depicting an illustrative semiconductor reference circuit  100  that can be modified to implement the methodologies of the present invention. The illustrative reference circuit  100  comprises an NMOS transistor NM 1  having drain (D), gate (G) and source (S) terminals. The source terminal of transistor NM 1  is connected to a negative voltage supply, which may be VSS, and the gate terminal of NM 1  is preferably connected to a control signal SIG 1  which is used to control a current Inmos in the transistor NM 1 . 
   The drain terminal of transistor NM 1  is preferably connected to a current mirror formed of PMOS transistors PM 1  and PM 2 , each having drain (D), gate (G) and source (S) terminals. Transistor PM 1  is connected in a diode arrangement, with its gate and drain terminals coupled together and its source terminal connected to a positive voltage supply, which may be VDD. The gate terminals of transistors PM 1  and PM 2  are connected together at node N 1  and the source terminals of transistors PM 1  and PM 2  are connected together at the positive voltage supply. The drain terminal of transistor PM 2  is connected to an output node  110  of the reference circuit  100 . The output node  110  is preferably coupled to a bond pad  112  of the IC, to which a load resistor  114  is preferably connected. 
   The current mirror comprised of transistors PM 1  and PM 2  preferably generates a current Iref in transistor PM 2  that is substantially matched to the current Inmos in transistor PM 1 . A voltage Vref will be generated at output node  110  that is a function of the current Iref and a resistance value Rref of resistor  114  such that Vref=Iref×Rref. Assuming an ideal current mirror, the voltage Vref generated at the output  110  of the reference circuit  100  will vary primarily as a function of the PVT variations of NMOS transistor NM 1 . 
     FIG. 2  depicts an illustrative compensated buffer circuit  200  which can be modified to implement the techniques of the present invention. The illustrative buffer circuit  200  includes the reference circuit  100  described above in conjunction with  FIG. 1 , an analog-to-digital (A/D) converter  202  coupled to the reference circuit  100 , and an IO buffer  204  coupled to the A/D converter. The A/D converter  202  is configured to receive as an input the analog reference voltage Vref generated at the output  110  of the reference circuit  100  and convert the analog input voltage into a digital output signal. The output signal generated by the A/D converter  202  comprises a plurality of digital bits  206  representing the analog input voltage Vref. 
   The reference voltage Vref generated at the output  110  of the reference circuit  100  is compared against a pre-defined set of voltage levels in the A/D converter  202  and digital bits  206  are generated to represent a state of the NMOS device NM 1  under that particular PVT condition. These digital bits  206  are subsequently used to compensate for the characteristic variations in both PMOS and NMOS transistor devices in a pre-driver and output section (not shown) of the IO buffer circuit  204  to control, for example, slew rate and/or output impedance of the IO buffer  220 . Thus, compensation information based on the NMOS device is also used for the PMOS devices. 
   Since the output voltage Vref generated at the output  110  of the reference circuit  100  is based primarily on characteristics of NMOS transistor NM 1 , the digital bits  206  generated by the A/D converter  202  will also vary as a function of PVT variations of the NMOS transistor NM 1 . Accordingly, NMOS transistor devices present in the IO buffer  204  maybe operatively compensated for such PVT variations. However, PMOS transistor devices present in the buffer  204 , which generally do not track PVT variations in an NMOS device, cannot be accurately compensated based on NMOS characteristic information alone. 
     FIG. 3  illustrates an exemplary reference circuit  300 , formed in accordance with one embodiment of the present invention. The exemplary reference circuit  300  comprises an NMOS compensation portion  302  and a PMOS compensation portion  304 . The NMOS and PMOS compensation portions  302 ,  304  are preferably coupled together at an output node N 4  of the reference circuit  300 . Node N 4  maybe connected to a bond pad  306  so that an external resistor  308 , having a value Rref, can be connected to node N 4  for setting the output voltage Vref of the reference circuit  300  as desired. 
   The NMOS compensation portion  302  may be formed in a manner similar to the reference circuit  100  shown in  FIG. 1 . Specifically, NMOS compensation portion  302  preferably comprises an NMOS transistor NM 1  having drain (D), gate (G) and source (S) terminals. The source terminal of NM 1  is connected to the negative voltage supply, which is preferably VSS, and the gate terminal of NM 1  is coupled to a control signal SIG 1  for controlling a current Inmos flowing in NM 1 . The drain terminal of NM 1  is preferably coupled to a current mirror  310 . 
   Current mirror  310  may comprise a first PMOS transistor PM 1  and a second PMOS transistor PM 2 , each having drain (D), gate (G) and source (S) terminals. Transistor PM 1  is preferably connected in a diode configuration with its gate and drain terminals connected together and the source terminal of PM 1  connected to the positive voltage supply, preferably VDD. The drain terminals of PM 1  and NM 1  are connected together, and thus the current Inmos flowing in NM 1  also flows in PM 1 . The gate terminal of transistor PM 2  is connected to the gate terminal of PM 1  at node N 1  and the source terminal of PM 2  is connected to the positive voltage supply VDD. Since the gate-to-source voltage of transistor PM 1  will be the same as the gate-to-source voltage for transistor PM 2 , the drain current Inmos in PM 1  will be substantially matched to the drain current I PM2  in PM 2 . The current Inmos may be referred to as a reference current of current mirror  310  and the current I PM2  may be referred to as an output current of the current mirror  310 . 
   The NMOS compensation portion  302  of reference circuit  300  preferably includes a mechanism for selectively enabling the current mirror  310 . This mechanism may comprise, for example, a switch PSW 1  connected between the positive voltage supply VDD and node N 1 . When the switch PSW 1  is in a first (closed) state, the voltage across the source and gate terminals of transistors PM 1  and PM 2  will be zero, and thus the current mirror  310  will be disabled. Likewise, when the switch PSW 1  is in a second (open) state, the current mirror  310  will be enabled. The switch PSW 1  is preferably controlled by a control signal, which may be SIG 1 . Switch PSW 1  is preferably configured such that when SIG 1  is at a logic high level, the switch will be open and when SIG 1  is at a logic low level, the switch will be closed. In a preferred embodiment of the invention, switch PSW 1  may comprise a PMOS transistor having a source terminal connected to the positive voltage supply VDD, a drain terminal connected to node N 1  and a gate terminal connected to control signal SIG 1 . Alternative switch arrangements are similarly contemplated by the present invention, as will be apparent to those skilled in the art. 
   Current mirror  310  preferably generates a current I PM2  in transistor PM 2  that is substantially matched to the current Inmos in transistor NM 1 , although the two currents I PM2  and Inmos may be scaled relative to one another, as will be understood by those skilled in the art. In either instance, assuming that current mirror  310  is substantially ideal, in a first state (e.g., when control signal SIG 1  is at a logic high level), the voltage Vref generated at the output node N 4  of the reference circuit  300  will vary primarily as a function of the PVT variations of NMOS transistor NM 1 . Therefore, this output voltage can be used to accurately compensate for PVT variations in one or more NMOS devices which may reside external to the reference circuit  300 . 
   The PMOS compensation portion  304  of exemplary reference circuit  300  preferably comprises a PMOS transistor PM 3  having drain (D), gate (G) and source (S) terminals. The source terminal is preferably connected to the positive voltage supply VDD and the gate terminal is connected to a control signal SIG 1 , which may be the same signal presented to the gate terminal of transistor NM 1 . As in the case of transistor NM 1 , control signal SIG 1  applied to the gate terminal of PM 3  is preferably used to control a current Ipmos in transistor PM 3 . The drain terminal of transistor PM 3  is connected to a first current mirror  314 . 
   First current mirror  314  may be implemented as a simple mirror comprising NMOS transistors NM 2  and NM 3 , each having drain (D), gate (G) and source (S) terminals. Transistor NM 2  is connected in a diode configuration, with its gate and drain terminals connected together at node N 3  and its source terminal connected to the negative voltage supply VSS. The drain terminals of NM 2  and PM 3  are connected together, and thus the current Ipmos flowing in PM 3  also flows in NM 2 . The gate terminal of transistor NM 3  is connected to the gate terminal of NM 2  at node N 3  and the source terminal of NM 3  is connected to the negative voltage supply VSS. Since the gate-to-source voltage of transistor NM 2  will be the same as the gate-to-source voltage for transistor NM 3 , the drain current Ipmos in NM 2  will be substantially matched to a drain current INM 3  in NM 3 . The current Ipmos may be referred to as the reference current of current mirror  314  and the current I NM3  may be referred to as the output current of the current mirror  314 . The drain terminal of transistor NM 3  is preferably connected to a second current mirror  312 . 
   PMOS compensation portion  304  of reference circuit  300  preferably includes a mechanism for selectively enabling the current mirror  314 . This mechanism may comprise, for example, a switch NSW 1  connected between node N 3  and the negative voltage supply VSS. When the switch NSW 1  is in a first (closed) state, the voltage across the source and gate terminals of transistors NM 2  and NM 3  will be zero, thereby disabling the current mirror  314 . Likewise, when the switch NSW 1  is in a second (open) state, the current mirror  314  will be enabled. The switch NSW 1  is preferably controlled by a control signal, which may be SIG 1 . Switch NSW 1  is preferably configured such that when SIG 1  is at a logic high level, the switch will be closed and when SIG 1  is at a logic low level, the switch will be open. In a preferred embodiment of the invention, switch NSW 1  may comprise an NMOS transistor having a source terminal connected to the negative voltage supply VSS, a drain terminal connected to node N 3  and a gate terminal connected to control signal SIG 1 . 
   Current mirror  312 , like current mirror  310 , preferably comprises a pair of PMOS transistors PM 4  and PM 5 , each having drain (D), gate (G) and source (S) terminals. Transistor PM 4  is preferably connected in a diode configuration, with its gate and drain terminals connected together at node N 2  and its source terminal connected to the positive voltage supply VDD. The drain terminals of transistors PM 4  and NM 3  may be connected together, and therefore the current I NM3  flowing in NM 3  will also flow in PM 4 . The gate terminal of transistor PM 5  is connected to the gate terminal of PM 4  at node N 2  and the source terminal of PM 5  is connected to the positive voltage supply VDD. Since the gate-to-source voltage of transistor PM 5  will be the same as the gate-to-source voltage for transistor PM 4 , the drain current I NM3  in PM 4  will be substantially matched to a drain current I PM5  in PM 5 . The current I NM3  may be referred to as the reference current of current mirror  312  and the current I PM5  may be referred to as the output current of the current mirror  312 . 
   A switch PSW 2  is preferably connected between the positive voltage supply VDD and node N 2  for selectively enabling current mirror  312 . When the switch PSW 2  is in a first (closed) state, the voltage across the source and gate terminals of transistors PM 4  and PM 5  will be zero, thereby disabling current mirror  312 . Likewise, when the switch PSW 2  is in a second (open) state, the current mirror  312  will be enabled. Switch PSW 2  is preferably controlled by a control signal, which may be an inverted version of SIG 1 , namely, SIG 1 _NOT. Switch PSW 2  is preferably configured such that when SIG 1 _NOT is at a logic high level (i.e., when SIG 1  is low), the switch will be open and when SIG 1 _NOT is at a logic low level (i.e., when SIG 1  is high), the switch will be closed. In a preferred embodiment of the invention, switch PSW 2  may comprise a PMOS transistor having a source terminal connected to the positive voltage supply VDD, a drain terminal connected to node N 2  and a gate terminal connected to control signal SIG 1 _NOT. Alternatively, switch PSW 2  may comprise a combination of PMOS and NMOS transistors, as will be understood by those skilled in the art. 
   Current mirror  312  preferably generates a current I PM5  in transistor PM 5  that is substantially matched to the current Ipmos in transistor PM 3 , although the two currents I PM5  and Ipmos may be scaled relative to one another, as will be understood by those skilled in the art. In either case, assuming that current mirrors  312  and  314  are substantially ideal, in a second state (e.g., when control signal SIG 1  is at a logic low level), the voltage Vref generated at the output node N 4  of the reference circuit  300  will vary primarily as a function of the PVT variations of PMOS transistor PM 3 . Therefore, this output voltage can be used to accurately compensate for PVT variations in one or more PMOS devices which may reside external to the reference circuit  300 . 
   It is to be understood that, while current mirrors  310 ,  312  and  314  are shown connected in a simple current mirror configuration, one or more of the current mirrors may be implemented using an alternative circuit arrangement, including, but not limited to, a cascode current mirror, Wilson current mirror, etc., as known by those skilled in the art. These alternative current mirror configurations may provide improved matching between the reference current and corresponding output current. Furthermore, in accordance with another aspect of the invention, one or more of the current mirrors  310 ,  312  and  314  may provide current scaling, such as, for example, by appropriately sizing corresponding transistors (e.g., PM 1 /PM 2 ) in the respective current mirrors. Although the current mirrors are depicted comprising NMOS and PMOS transistor devices, one or more of the current mirrors may alternatively be implemented using NPN and PNP BJT devices, respectively. 
   The drain terminals of transistors PM 2  and PM 5  are connected together at node N 4 , which forms an output of the exemplary reference circuit  300 , as previously explained. The reference circuit  300  is preferably configured such that an output current Iref is selectively determined either by the NMOS compensation portion  302  in a first state, and is thus substantially equal to the current I PM2  in transistor PM 2 , or by the PMOS compensation portion  304  in a second state, and is thus substantially equal to the current I PM5  in transistor PM 5 , depending upon the logical state of the control signal SIG 1 . Thus, when the reference circuit  300  is in the first state (e.g., when control signal SIG 1  is at a logic high), the output voltage Vref can be used for NMOS device compensation. Likewise, when the reference circuit  300  is in the second state (e.g., when control signal SIG 1  is at a logic low), the output Vref can be used for PMOS device compensation. A more detailed description of the operation of exemplary reference circuit  300  will be presented herein below, by way of example only. 
   During an NMOS compensation mode, signal SIG 1  is brought to a logic high level (e.g., VDD), turning on NMOS transistor NM 1 . A quantity of current Inmos is generated based primarily on the PVT conditions of transistor NM 1 . The current Inmos is mirrored, and possibly scaled, by devices PM 1  and PM 2  in current mirror  310  to generate output current I PM2 . This output current I PM2  is passed through external resistor  308  to generate the output voltage Vref at node N 4 . A reference voltage is thereby generated across the resistor  308  that is a function of the state of the NMOS device NM 1  for a given PVT condition. 
   During the NMOS compensation mode, switch PSW 1  is open. Device PM 3  is gated by the same control signal SIG 1 . Since SIG 1  is a logic high during this mode, transistor PM 3  will be turned off, and therefore current Ipmos will be substantially zero. Switch NSW 1 , which is also controlled by signal SIG 1 , will be closed, thereby pulling node N 3  to the negative voltage supply VSS and disabling current mirror  314  by turning off transistors NM 2  and NM 3 . Switch PSW 2 , which is controlled by signal SIG 1 _NOT, an inverted version of SIG 1 , will be closed, thereby pulling node N 2  to the positive voltage supply VDD and disabling current mirror  312  by turning off transistors PM 4  and PM 5 . The external resistor  308  therefore receives only the current contribution I PM2  from the NMOS compensation portion  302  of the reference circuit  300 . 
   During a PMOS compensation mode, signal SIG 1  is brought to a logic low level (e.g., VSS). This turns on PMOS transistor PM 3  and establishes a current Ipmos based primarily on the PVT conditions of transistor PM 3  at that particular instance. The current Ipmos is mirrored, and possibly scaled, by transistors NM 2  and NM 3  in current mirror  314  and transistors PM 4  and PM 5  in current mirror  312  to generate output current I PM5 . This output current I PM5  is passed through the external resistor  308  to generate the output voltage Vref at node N 4 . A reference voltage is thereby generated across the resistor  308  that is a function of the state of the PMOS device PM 3  for a given PVT condition. 
   During the PMOS compensation mode, both switches NSW 1  and PSW 2  are open, thus enabling current mirrors  314  and  312 , respectively, in the PMOS compensation portion  304  of reference circuit  300 . Since control signal SIG 1  is a logic low level during this mode, NMOS transistor NM 1  is turned off and thus generates substantially no current. Switch PSW 1  will be closed, thereby pulling node N 1  to the positive voltage supply VDD and disabling current mirror  310  by turning off transistors PM 1  and PM 2 . The external resistor  308  therefore receives only the current contribution I PM5  from the PMOS compensation portion  304  of the reference circuit  300 . 
   In accordance with another aspect of the invention, additional circuitry (not shown) may be included in the exemplary reference circuit  300  for turning off all current mirrors  310 ,  312  and  314  during a low power (e.g., power down) mode of operation. In this manner, the overall current consumption in the reference circuit  300  will be substantially zero during low power mode. 
   In a preferred embodiment of the invention, the currents I PM2  and I PM5  are adjusted, for example by appropriately scaling the transistor devices in current mirrors  310 ,  312 ,  314 , such that the output voltage Vref generated during the NMOS compensation mode is substantially the same as the output voltage generated during the PMOS compensation mode under normal operating conditions. 
   A clock signal, which may be supplied internally or externally to the reference circuit  300 , is preferably employed to generate the control signals SIG 1  and SIG 1 _NOT for selectively switching between modes of operation of the reference circuit. A frequency of the clock is preferably chosen such that the current mirrors  310 ,  312 ,  314  in the reference circuit  300  are allowed ample time to substantially settle to their respective steady state values. The amount of time which the reference circuit is operable in the NMOS compensation mode compared to the PMOS compensation mode need not be equal, and thus the duty cycle of the clock signal is not required to be 50 percent. In fact, since the number of circuit nodes in the PMOS compensation portion  304  of the reference circuit  300  is greater than the number of nodes in the NMOS compensation portion  302 , and therefore the reference circuit may take longer to settle in the PMOS compensation mode, it may be desirable to at least slightly offset the duty cycle of the clock signal (e.g., 40–60 duty cycle) to allow more time per clock period for the PMOS compensation mode. By doing so, the maximum frequency of the clock signal may be able to be advantageously increased. 
   It is to be understood that, although the exemplary reference circuit  300  is depicted as being operable in a PMOS compensation mode and an NMOS compensation mode, the reference circuit, in an alternative embodiment of the invention, may include separate reference outputs corresponding to the NMOS compensation portion  302  and the PMOS compensation portion  304 . In this instance, the reference circuit  300  may be configured so as to provide NMOS and PMOS compensation information substantially concurrently, thereby eliminating the need to selectively switch between two or more operating modes of the circuit. 
     FIG. 4  is a block diagram illustrating an exemplary compensated buffer circuit  400 , formed in accordance with one embodiment of the invention. The exemplary compensated buffer circuit  400  comprises reference circuit  300 , described above in conjunction with  FIG. 3 , an A/D converter and control block  402  coupled to the reference circuit  300 , and an IO buffer circuit  404  coupled to the A/D converter and control block. While the compensated buffer circuit  400  is shown as including separate function blocks, it is to be appreciated that one or more of these functional blocks may be combined, or one or more of the blocks may be divided into additional blocks, with or without modifications thereto. In the compensated buffer circuit  400 , the control signal SIG 1  for selectively controlling the mode of operation of the reference circuit  300  is generated by the A/D converter and control block  402 . It is to be appreciated, however, that this control signal may be generated by an alternative control circuit. 
   The reference voltage Vref generated during the NMOS and PMOS compensation phases of the control signal SIG 1  are received by the A/D converter and control block  402 , which preferably generates two sets of digital bits  406  and  408  corresponding to the PMOS compensation mode and NMOS compensation mode, respectively. The two sets of digital bits  406 ,  408  are sent to the IO buffer circuit  404  (e.g., in serial, parallel, etc.) for separately compensating for at least PVT variations in one or more PMOS and NMOS devices, respectively, in the IO buffer circuit. In a preferred embodiment of the invention, the A/D converter and control block  402  includes a latch, or alternative storage circuit (e.g., random access memory, etc.), for at least temporarily storing the two sets of digital bits  406 ,  408  while the PMOS and NMOS compensation information is at least periodically updated by the A/D converter and control block. 
   For improved PMOS and NMOS device compensation, the PMOS devices in the IO buffer circuit  404  are preferably formed on the same semiconductor die and/or in close relative proximity to at least the PMOS device PM 3  in the reference circuit  300 . Likewise, the NMOS devices in the IO buffer circuit  404  are preferably formed on the same semiconductor die and/or in close relative proximity to at least the NMOS device NM 1  in the reference circuit  300 . In this manner, PVT variations in the PMOS and NMOS devices in the IO buffer circuit  404  may be more accurately compensated. 
   Although illustrative embodiments of the present invention have been described herein with reference to the accompanying drawings, it is to be understood that the invention is not limited to those precise embodiments, and that various other changes and modifications may be made therein by one skilled in the art without departing from the scope of the appended claims.