Patent Publication Number: US-7913138-B2

Title: Semiconductor integrated circuit

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is based upon and claims the benefit of priority from prior Japanese Patent Application No. 2008-54413 filed on Mar. 5, 2008, the entire contents of which are incorporated herein by reference. 
     BACKGROUND 
     1. Field 
     Aspects of the present invention relate to semiconductor integrated circuits having a test function. 
     2. Description of Related Art 
     The structure of semiconductor devices, such as transistors, has been miniaturized and the degree of integration of circuits mounted on one chip has been increasing. Accordingly, a system large-scale integrated circuit (LSI) that realizes functions of a system with one chip has been developed. Generally, a system LSI has a function block (hard macro), such as a memory and a controller, and a user block (user logic) connected to the function block in order to realize functions unique to a user. 
     An amount of time for testing a system LSI increases in proportion to an increase in the number of logic gates. Such an increase in time leads to an increase in the test cost. Japanese Patent Laid-Open No. 2006-4509 discloses various testing methods for reducing the test cost. To test a user block designed uniquely to a user (to detect a stuck-at fault), a scan path test using daisy-chained flip-flops has been proposed. In addition, to test a function block, such as a memory macro, a method for including a built-in self test (BIST) circuit in a system LSI has been proposed. As described above, an improvement in the efficiency of the test of the user block and the test of the function block is attempted independently. 
     SUMMARY 
     According to aspects of an embodiment, a semiconductor integrated circuit includes: a data input unit for receiving an input data signal to be supplied to an external data input terminal; a storage unit for storing the input data signal received by the data input unit; a timing generating unit for generating a timing signal in response to an output request signal; a data output unit for outputting, in synchronization with the timing signal, the input data signal stored in the storage unit as an output data signal; a test output control unit for outputting, in synchronization with the timing signal, the input data signal received by the data input unit; and a data selector for outputting the output data signal supplied from the data output unit to the external data output terminal in a normal operation mode and outputting the input data signal supplied from the test output control unit to the external data output terminal in a test mode. 
     The object and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the claims. It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are not restrictive of the invention, as claimed. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  shows a memory macro according to aspects of one embodiment; 
         FIG. 2  shows an example of a system on which the memory macro shown in  FIG. 1  is mounted; 
         FIG. 3  shows a detailed view of major parts of the system shown in  FIG. 2 ; 
         FIG. 4  shows a detailed view of registers REG 4 -REG 6  shown in  FIG. 3 ; 
         FIG. 5  shows an operation of the memory macro shown in  FIG. 1  performed in a normal operation mode; 
         FIG. 6  shows an operation of a memory macro performed to test the user logic circuit L 4  in a logic test mode; 
         FIG. 7  shows an operation of the system shown in  FIG. 3  performed in a normal operation mode; 
         FIG. 8  shows an overview of an operation for testing the user logic unit UL 1  shown in  FIG. 3 ; 
         FIG. 9  shows an overview of an operation for testing the user logic unit UL 2  shown in  FIG. 3 ; 
         FIG. 10  shows an overview of an operation test of the memory macro shown in  FIG. 1 ; 
         FIG. 11  shows a memory macro employed before the proposal of the memory macro shown in  FIG. 1 ; 
         FIG. 12  shows an overview of an operation for testing a user logic unit UL 2  in a system including the memory macro shown in  FIG. 11 ; 
         FIG. 13  shows an example of a memory macro according to aspects of another embodiment; 
         FIG. 14  shows an operation of a memory macro MM performed to test a user logic circuit L 4  in the memory macro shown in  FIG. 13  in a logic test mode; 
         FIG. 15  shows a detailed view of major parts of a system according to aspects of another embodiment; 
         FIG. 16  shows a detailed view of the memory macro shown in  FIG. 15 ; and 
         FIG. 17  shows an overview of an operation performed to test the user logic unit UL 2  shown in  FIG. 15 . 
     
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Aspects of certain embodiments will be described below using the accompanying drawings. A thick line indicates a plurality of signal lines in the drawings. In addition, some of blocks connected to a thick line may have a plurality of circuits. The same reference as a name of a signal is used to represent a signal line that the signal propagates through. A signal having a name starting from “/” indicates a negative logic signal. A doubled-lined rectangle represents an external terminal in the drawings. The external terminal may be, for example, a terminal of a hard macro, a pad mounted on a semiconductor chip, or a lead of a package storing a semiconductor chip. The same reference as a name of an external terminal is used to represent a signal to be supplied through the external terminal. 
       FIG. 1  shows a memory macro MM according to one embodiment. For example, the memory macro MM is designed as a hard macro (function block). As shown in  FIG. 2 , the memory macro MM and user logic units UL 1  and IL 2  are mounted on a system SYS (semiconductor integrated circuit chip). The memory macro MM includes an address selector  10 , a command decoder  12 , a timing generator  14 , a data input buffer  16 , a flip-flop F/F, a data selector DSEL, and a memory core CORE. 
     The address selector  10  receives an input address signal IA in synchronization with a timing signal RAS. The address selector  10  outputs the input address signal IA to the memory core CORE as an internal address signal ADD. The address selector  10  may have a function for decoding the address signal IA (a function of an address decoder). In this case, the internal address signal ADD is a decoded address signal. The address decoder may be provided in the memory core CORE. In addition, the address selector  10  may receive the input address signal IA through an address buffer that operates in synchronization with a clock signal CK. 
     The command decoder  12  receives, in synchronization with the clock signal CK, a write enable signal /WE. The command decoder  12  outputs, in synchronization with the timing signal RAS, an active signal ACTP and a read/write control signal RWP. More specifically, the memory macro MM executes, for each cycle of the clock signal CK, a write operation or a read operation. The active signal ACTP is a high-level pulse signal. The read/write control signal RWP is changed to a high level in response to a write command and to a low level in response to a read command. 
     A clock enable signal CKE, not shown, may be supplied to the memory macro MM and the command decoder  12  may operate while the level of the clock enable signal CKE is high. In this case, the command decoder  12  stops outputting the timing signal RAS, the active signal ACTP, and the read/write control signal RWP while the level of the clock enable signal CKE is low. More specifically, the signals RAS, ACTP, and RWP are kept at the low level while the level of the clock enable signal CKE is low. The memory macro MM executes, for each cycle of the clock signal CK, a write operation or a read operation while the level of the clock enable signal CKE is high. While the level of the clock enable signal CKE is low, the memory macro MM is set in a standby state and is prohibited from executing a write operation and a read operation. 
     The timing generating unit  14  has delay circuits IDLY and ODLY for outputting an input data latch signal IDLAT and an output data latch signal ODLAT (timing signals), respectively. The lengths of rectangular frames representing the delay circuits IDLY and ODLY indicate relative delay time lengths. When the level of the write enable signal /WE is low, the delay circuit IDLY delays the active signal ACTP for a predetermined period and outputs the active signal ACTP as the input data latch signal IDLAT. When the level of the write enable signal /WE is high, the delay circuit ODLY delays the active signal ACTP for a predetermined period and outputs the active signal ACTP as the output data latch signal ODLAT. The high-level active signal ACTP and the low-level write enable signal /WE indicate a write command (input request signal). The high-level active signal ACTP and the high-level write enable signal /WE indicate a read command (output request signal). The timing generator  14  also outputs, in accordance with the active signal ACTP and the read/write control signal RWP, an operation control signal OPCNT (a word line activation signal or a bit line pre-charge stop signal) for operating a memory cell array ARY. 
     The data input buffer  16  (data input unit) receives, in synchronization with the clock signal CK, an input data signal ID (write data) with an external data input terminal ID and outputs the received signal as an internal input data signal DIN. 
     The flip-flop F/F (test output control unit) latches, in synchronization with the output data latch signal ODLAT, a logic level of the internal input data signal DIN having received by the data input buffer  16  and outputs the logic level as a test output data signal TDOUT. The flip-flop F/F latches at least one bit of the internal input data signal DIN composed of a plurality of bits. The flip-flop F/F may operate in response to the output data latch signal ODLAT only during a test mode. The power consumption can be reduced by prohibiting input of the output data latch signal ODLAT during the normal operation mode. 
     When the level of a bypass mode signal BP is low (“0”), the data selector DSEL outputs an output data signal DOUT (read data) supplied from a read amplifier RA to an external data output terminal OD. When the level of the bypass mode signal BP is high (“1”) (i.e., during a test mode), the data selector DSEL outputs the test output data signal TDOUT (i.e., internal input data signal DIN) supplied from the flip-flop F/F to the external data output terminal OD. The bypass mode signal BP is set to be high at the time of execution of a bypass test, which will be described later. When the flip-flop F/F receives one bit of the internal input data signal DIN, the data selector DSEL receives one bit of the corresponding output data signal DOUT and the test output data signal TDOUT (one bit). In this case, the other bits of the output data signal DOUT are not supplied to the data selector DSEL but are directly supplied to the external data output terminal OD. 
     The memory core CORE has a memory cell array ARY (storage unit), a write amplifier WA, and the read amplifier RA. The memory cell array ARY has a plurality of memory cells MC that is arranged in a matrix form and holds the input data signal ID. For example, each of the memory cells MC has a latch. The memory cell array ARY operates as a static random access memory (SRAM). Although not shown in the drawing, the memory cell array ARY has, for example, word lines each connected to a respective row of the memory cells MC arranged in the horizontal direction in the drawing and bit lines each connected to a respective column of the memory cells MC arranged in the vertical direction in the drawing. A sense amplifier for amplifying a data signal read out from the memory cell MC through the bit line may be formed at an end of the memory cell array ARY (on the upper or lower side in the drawing). 
     The memory cell array ARY starts operating in accordance with an operation control signal OPCNT output from the timing generator  14  in response to a read command. More specifically, the memory cell array ARY stops pre-charging of the bit lines in response to the operation control signal OPCNT, activates a word line selected by the address signal ADD, and outputs data stored in the memory cell MC that is connected to the activated word line to the bit line. The data signal output to the bit line is transferred to the read amplifier RA. The memory cell array ARY operates in accordance with the operation control signal OPCNT asynchronously with the clock signal CK. Accordingly, an operation performed between reception of the read command and output of the read data from the read amplifier RA is performed asynchronously with the clock signal CK. 
     The write amplifier WA latches, in synchronization with the input data latch signal IDLAT, a logic level of the internal input data signal DIN and writes the latched signal in the memory cells MC. The read amplifier RA (data output unit) amplifies an output data signal read out from the memory cell MC, latches and stores a logic level of the amplified signal in synchronization with the output data latch signal ODLAT, and outputs the stored signal as the output data signal DOUT. When the memory cell array ARY has a sense amplifier, the sense amplifier amplifies a voltage value of the data signal read output from the memory cell MC to the bit line. The read amplifier RA, in turn, amplifies the signal level (drive capability) of the data signal supplied from the sense amplifier in order to output the data signal having a large load to the output data signal line DOUT. 
     In this embodiment, for example, the load of an output data signal line TDOUT (test signal line) that transfers the output data signal TDOUT (i.e., the input data signal DIN) from the flip-flop F/F to the data selector DSEL is designed to be equal to the load of an output data signal line DOUT (normal signal line) that transfers the output data signal DOUT from the read amplifier RA to the data selector DSEL. For example, the signal lines TDOUT and DOUT have the same structure and the lengths thereof are equal. With such a configuration, the timing of the test output data signal TDOUT arriving at the data selector DSEL can be set equal to the timing of the output data signal DOUT arriving at the data selector DSEL. Accordingly, as shown in  FIGS. 5 and 6 , an identical access time TA (operation timing) of the memory macro MM can be set in the user mode (normal operation mode) and the logic test mode. That is, the memory macro MM can be operated in a simulated manner using simple test patterns. 
       FIG. 2  shows an example of a system SYS on which the memory macro MM shown in  FIG. 1  is mounted. For example, the system SYS is formed in one chip (semiconductor integrated circuit) as a system on chip SoC (system LSI). The system SYS has user logic units UL 1  and UL 2  (user blocks), the memory macro MM, a memory test unit MTST, and a test control unit TCNT.  FIG. 2  shows aspects of a minimum configuration of the embodiment. In addition to a configuration shown in  FIG. 2 , the SoC may include other hard macros, such as a central processing unit (CPU), a direct memory access controller (DMAC), and a memory controller. 
     The user logic units UL 1  and UL 2  are logic circuits designed uniquely for a user. Each of the user logic units UL 1  and UL 2  has a plurality of daisy-chained scan registers (represented by rectangles with “x”). Each scan register includes a flip-flop. The flip-flops are connected to a scan path SP 1  and sequentially transfer serial test data output from the test control unit TCNT during a test mode. A user circuit designed by a user may be used as the flip-flops or the flip-flops may be included in the user logic units UL 1  and UL 2  as test circuits. 
     The memory test unit MTST includes control circuits (PATG and CHK shown in  FIG. 3 ) for testing the memory macro MM and a plurality of daisy-chained scan registers (represented by rectangles with x) for testing the user logic units UL 1  and UL 2 . Flip-flops of the scan registers are connected to a scan path SP 2  and sequentially transfer serial test data output from the test control unit TCNT during the test mode. The scan paths SP 1  and SP 2  may be connected in series. 
     The test control unit TCNT has a control circuit for testing the user logic units UL 1  and UL 2 . For example, during a logic test mode for testing the user logic units UL 1  and UL 2 , the test control unit TCNT receives signals /WE, IA, and ID, stored in output registers REG 4 -REG 6  shown in  FIG. 3 , through the scan path SP 2 . The test control unit TCNT detects a defect of the user logic unit UL 1  by comparing the received signal values with expected values. During the logic test mode, the test control unit TCNT also sets test input data signals in input registers REG 1 -REG 3  shown in  FIG. 3  through the scan path SP 1 . During the logic test mode, the test control unit TCNT receives a user output signal OD 0 , stored in an output register REG 8  shown in  FIG. 3 , through the scan path SP 1  and detects a defect of the user logic unit UL 2  by comparing the received signal value with an expected value. During the logic test mode, the test control unit TCNT can detect a defect of the memory macro MM by receiving a data output signal OD, stored in a register REG 7  shown in  FIG. 3 , through the scan path SP 2 . 
     In this example, the bypass mode signal BP is supplied from outside of the SoC. The bypass mode signal BP is used only when the SOC is tested. More specifically, the bypass mode signal BP is output from a test system, such as an LSI tester, or a function block (macro) test control circuit included in the system SYS along with the SoC. The SoC is tested in the process of manufacture of the SoC. By selecting defect-free products, the SoC is manufactured. The test of the SoC may be performed on the system SYS after the SoC is mounted on the system SYS. After the completion of the test, a bypass mode terminal BP is connected to, for example, a ground line on a system substrate. 
       FIG. 3  shows a detailed view of major parts of the system SYS shown in  FIG. 2 . The user logic unit UL 1  has the scan registers REG 1 -REG 3  connected to the scan path SP 1 , selectors S 1 -S 3 , and user logic circuits (input user logic circuits) L 1 -L 3 . Although connections between the registers REG 1 -REG 3  and the scan path SP 1  are simplified in the drawing, the registers REG 1 -REG 3  are connected in series through the scan path SP 1  as in the case of the registers REG 4 -REG 6  of the memory test unit MTST. As in the case of the registers REG 4 -REG 6  ( FIG. 4 ), each of the registers REG 1 -REG 3  has a scan multiplexer and a flip-flop. 
     The registers REG 1 -REG 3  (input registers) are used to store test input signals (test patterns) during a test of the user logic circuits L 1 -L 3 , respectively. More specifically, during a logic test mode, the register REG 1  operates as a test circuit that stores and outputs a logic level of a control signal WE 0  to generate the write enable signal /WE using the user logic circuit L 1 . The register REG 2  operates as a test circuit that stores and outputs a logic level of a control signal IA 0  to generate the address signal IA using the user logic circuit L 2 . The register REG 3  operates as a test circuit that stores and outputs a logic level of a control signal ID 0  to generate the data signal ID using the user logic circuit L 3 . For example, during the logic test mode, the user logic circuit L 3  operates in response to the test input signal (ID 0 ) supplied from the register REG 3  to generates the input data signal ID, and outputs the generated input data signal ID to an external data input terminal ID through a selector S 6 . 
     The logic levels stored in the registers REG 1 -REG 3  may be directly supplied to the external input terminal of the memory macro MM instead of supplying them through the user logic circuits L 1 -L 3 , respectively. In this case, a user logic circuit L 4  can be tested by directly supplying the signal values stored in the registers REG 1 -REG 3  to the memory macro MM. The selectors S 1 -S 3  select the outputs of the registers REG 1 -REG 3  during the logic test mode and select outputs of other circuits, not shown, during a normal operation mode. The user logic circuits L 1 -L 3  may receive signals other than signals WE 0 , IA 0 , and ID 0  supplied from the registers REG 1 -REG 3 , respectively. 
     The memory test unit MTST (BIST circuit) has the pattern generating circuit PATG, selectors S 4 -S 7 , the scan registers REG 4 -REG 7 , and the check circuit CHK. The pattern generating circuit PATG generates a test pattern for testing the memory macro MM. More specifically, during a macro test mode, the pattern generating circuit PATG generates, as a test pattern, the write enable signal /WE, the address signal IA, and the write data signal ID. 
     During the normal operation mode or the logic test mode, the selectors S 4 -S 7  supply the signals fed from the user logic unit UL 1  to the memory macro MM. During the macro test mode for testing the memory macro MM, the selectors S 4 -S 7  supply a test pattern fed from the pattern generating circuit PATG to the memory macro MM. 
     The registers REG 4 -REG 7  are connected to the scan path SP 2 . During the logic test mode, the registers REG 4 -REG 6  store output signals supplied from the user logic unit UL 1  in order to detect a defect of signal lines connected to the user logic unit UL 1  and the user logic circuit L 1 . During the logic test mode, the register REG 7  stores an input test pattern to be supplied to the user logic unit UL 2 , whereas, during the macro test mode, the register REG 7  stores a read data signal supplied from the memory macro MM. The information stored in the registers REG 4 -REG 7  is transferred to the test control unit TCNT through the scan path SP 2  and is compared with an expected value. In addition, the input test pattern set in the register REG 7  is transferred from the test control unit TCNT through the scan path SP 2 . 
     The length of a signal line between the user logic circuit L 1  and the memory macro MM is designed to be equal to the length of a signal line between the user logic circuit L 1  and the register REG 4 . The length of a signal line between the user logic circuit L 2  and the memory macro MM is designed to be equal to the length of a signal line between the user logic circuit L 2  and the register REG 5 . Similarly, the length of a signal line between the user logic circuit L 3  and the memory macro MM is designed to be equal to the length of a signal line between the user logic circuit L 3  and the register REG 6 . With this configuration, the registers REG 4 -REG 6  can receive signals output from the user logic circuits L 1 -L 3  at the same timing as the timing of the memory macro MM receiving these signals, respectively. 
     During the macro test mode, the check circuit CHK compares the read data OD, read out from the memory macro MM and stored in the register REG 7 , with an expected value to detect a defect of the memory macro MM. The comparison result is sent to outside of the system SYS through a dedicated terminal or is sent to outside of the system SYS through the test control unit TCNT. 
     The user logic unit UL 2  has the user logic circuit L 4  (output user logic circuit) and the scan register (output register) REG 8  connected to the scan path SP 1 . The user logic circuit L 4  operates in response to the output data signal OD output from an external data output terminal OD of the memory macro MM to generate a user output signal OD 0 . The user logic circuit L 4  may receive signals other than the output data signal OD. The register RED 8  stores the user output signal OD 0  supplied from the user logic unit UL 2  in order to detect a defect of signal lines connected to the user logic unit UL 2  and the user logic circuit L 2  during the logic test mode. The information stored in the register REG 8  is transferred to the test control unit TCNT through the scan path SP 1  and is compared with an expected value. 
     Hereinafter, the propagation delay time of each of the user logic circuits L 1 -L 3 , the access time of the memory macro MM, and the propagation delay time of the user logic circuit L 4  are referred to as IPATH, MPATH, and OPATH, respectively. Although the propagation delay time of the user logic circuits L 1 -L 3  actually differs from one another, a description will be given for a case where the propagation delay time is the same. The IPATH is substantially equal to propagation delay time between output of signals from the registers REG 1 -REG 3  and input of the signals to the memory macro MM. The OPATH is substantially equal to the propagation delay time between output of a signal from the memory macro MM to input of the signal to the register REG 8 . 
       FIG. 4  shows a detailed view of the registers REG 4 -REG 6  shown in  FIG. 3 . Each register REG (REG 4 -REG 6 ) has a scan multiplexer SM (SM 4 -SM 6 ) and a flip-flop F/F (F/F 4 -F/F 6 ). The scan multiplexer SM selects the scan path SP 2  when transferring information stored in the flip-flops F/F 4 -F/F 6  to the test control unit TCNT through the scan path SP 2 . In other cases, the scan multiplexer SM selects outputs of the selectors S 1 -S 3  shown in  FIG. 3 . The flip-flop F/F latches, in synchronization with a rising edge of the clock signal CK, a logic level of a signal output from the scan multiplexer SM and outputs the latched signal. 
       FIG. 5  shows an operation of the memory macro MM shown in  FIG. 1  performed in the normal operation mode. In the normal operation mode, the memory macro MM is accessed to realize functions of the system SYS. During the normal operation mode, the bypass mode signal BP is fixed to a low level L. 
     In this example, a write command WR 1  and read commands RD 1  and RD 2  are sequentially supplied to the memory macro MM. The command decoder  12  recognizes the write command WR 1  when the level of the write enable signal /WE is low at a rising edge of the clock signal CK. The command decoder  12  also recognizes the read command RD 1  or RD 2  when the level the write enable signal /WE is high at a rising edge of the clock signal CK. The command decoder  12  outputs the active signal ACTP (pulse signal) every time the command decoder  12  receives the write command or the read command ((a), (b), (c) in  FIG. 5 ). 
     An address signal A 1  and write data D 1  are supplied to the memory macro MM along with the write command WR 1  ((d) in  FIG. 5 ). The data input buffer  16  outputs the write data D 1  to the write amplifier WA as the internal input data signal DIN ((e) in  FIG. 5 ). The timing generator  14  outputs, in synchronization with the active signal ACTP, the input data latch signal IDLAT (pulse signal) ((f) in  FIG. 5 ). The write amplifier WA receives, in synchronization with the input data latch signal IDLAT, the data signal DIN and writes the data signal in the memory cells MC. 
     The address signal A 1  is supplied to the memory macro MM along with the read command RD 1  ((g) in  FIG. 5 ). At this time, the data input buffer  16  outputs a given data signal DX ((h) in  FIG. 5 ). The address signal A 1  indicates the same value as that supplied along with the write command WR 1 . The timing generator  14  outputs, in synchronization with the active signal ACTP, the output data latch signal ODLAT (pulse signal) ((i) in  FIG. 5 ). The read amplifier RA latches, in synchronization with the output data latch signal ODLAT, a logic level of the data signal D 1  supplied from the memory cell MC and outputs the data signal D 1  as the output data signal DOUT ((j) in  FIG. 5 ). 
     The flip-flop F/F shown in  FIG. 1  latches, in synchronization with the output data latch signal ODLAT, a logic level of the given data signal DX and outputs the logic level as the test output data signal TDOUT ((k) in  FIG. 5 ). Since the level of the bypass mode signal BP is low, the data selector DSEL outputs the read data D 1  supplied from the memory core CORE to the data output terminal OD ((l) in  FIG. 5 ). The access time between reception of the read command RD 1  and output of the read data D 1  is equal to TA. An address signal A 2  is then supplied to the memory macro MM along with the read command RD 2  and a next read operation is executed. 
       FIG. 6  shows an operation of the memory macro MM performed in the logic test mode for testing the user logic circuit L 4 . As in the case shown in  FIG. 5 , in this example, the write command WR 1  and the read commands RD 1  and RD 2  are sequentially supplied to the memory macro MM. However, the level of the address signal IA may be high H or low L ((a) in  FIG. 6 ). As described above, during the logic test mode, the commands WR 1 , RD 1 , and RD 2  are supplied through the user logic circuits L 1 -L 3  on the basis of values set in the registers REG 1 -REG 3 , respectively. 
     The data signal ID is supplied asynchronously with the write command WR 1 . Accordingly, a given write data signal ID is written in the memory macro MM in synchronization with the write command WR 1  ((b) in  FIG. 6 ). The write command WR 1  does not have to be supplied to the memory macro MM. That is, the read command RD 1  may be supplied to the memory macro MM first. Alternatively, the address signal IA and the data signal ID may be supplied to the memory macro MM in synchronization with the write command WR 1  and the data may be written in a predetermined memory cell MC. 
     A data signal ID is then supplied, in synchronization with the read command RD 1 , to the memory macro MM ((c) in  FIG. 6 ). The memory cell array ARY executes a read operation in response to the read command RD 1 . The read amplifier RA outputs, in synchronization with the output data latch signal ODLAT, the output data signal DOUT ((d) in  FIG. 6 ). However, since the address signal IA is supplied asynchronously with the read command RD 1 , the output data signal DOUT has a given value DX. The flip-flop F/F shown in  FIG. 1  latches, in synchronization with the output data latch signal ODLAT, a logic level of the data signal D 1  supplied from the data input buffer  16  and outputs the test output data signal TDOUT ((e) in  FIG. 6 ). The output timing of the test output data signal TDOUT is the same as that of the output data signal DOUT supplied from the read amplifier RA described with reference to  FIG. 5 . 
     Since the level of the bypass mode signal BP is high, the data selector DSEL outputs the test output data signal TDOUT (D 1 ) to the data output terminal OD ((f) in  FIG. 6 ). That is, the data selector DSEL masks the output data signal DOUT supplied from the read amplifier RA. 
     Since the length of an output data signal line DOUT is the same as that of a test output data signal line TDOUT, the access time between reception of the read command RD 1  and output of the read data D 1  is equal to TA, which is the same as a case shown in  FIG. 5 . More specifically, when the level of the bypass mode signal BP is high in the logic test mode, the read data signal D 1  is output from the memory macro MM at the same delay time as that employed in the normal operation mode. Accordingly, the test pattern can be supplied to the user logic unit UL 2  at the same timing as that employed in the normal operation mode without using a complicated test pattern. 
       FIG. 7  shows an operation of the system SYS shown in FIG.  3  performed in the normal operation mode. A write command WR 1  and a read command RD 1 , which are enclosed by rectangles in the drawing, indicate timing of the user logic circuit L 1  receiving a control signal WE 0 , from which the write command WR 1  and the read command RD 1  are generated, respectively. In this example, the write command WR 1  and the read command RD 1  are sequentially supplied to the memory macro MM ((a) and (b) in  FIG. 7 ). An operation of the memory macro MM performed in response to the write command WR 1  and the read command RD 1  is the same as that shown in  FIG. 5 . 
     First, the user logic circuit L 1  receives, in synchronization with a first rising edge of the clock signal CK, the control signal WE 0  ((c) in  FIG. 7 ). After the delay time IPATH corresponding to the logic of the user logic circuit L 1 , the level of the write enable signal /WE changes to low ((d) in  FIG. 7 ). Similarly, the user logic circuit L 3  receives, in synchronization with the first rising edge of the clock signal CK, the control signal ID 0  ((e) in  FIG. 7 ). After the delay time IPATH corresponding to the logic of the user logic circuit L 3 , the level of the input data signal ID changes to high ((f) in  FIG. 7 ). 
     The delay time IPATH is designed to be shorter than one cycle of the clock signal CK. Accordingly, the write enable signal /WE and the input data signal ID are supplied to the memory macro MM so that sufficient setup time TS 1  is provided relative to a second rising edge of the clock signal CK ((g) in  FIG. 7 ). A write operation of the memory macro MM is then executed. 
     The user logic circuit L 1  receives, in synchronization with the second rising edge of the clock signal CK, the control signal WE 0  ((h) in  FIG. 7 ). The level of the write enable signal /WE changes to high in accordance with the logic of the user logic circuit L 1  ((i) in  FIG. 7 ). The high-level write enable signal /WE is supplied to the memory macro MM so that the sufficient setup time TS 1  is provided relative to a third rising edge of the clock signal CK ((j) in  FIG. 7 ). A write operation of the memory macro MM is then executed. 
     After the access time TA, the memory macro MM outputs the output data signal OD ((k) in  FIG. 7 ). A user logic circuit L 4  receives the output data signal OD and outputs the control signal OD 0  after the delay time OPATH corresponding to the logic of the user logic circuit L 4  (( 1 ) in  FIG. 7 ). The sum of the access time TA and the delay time IPATH is designed to be shorter than one cycle of the clock signal CK. Accordingly, the control signal OD 0  is output to a following user logic circuit from the user logic circuit L 4  so that sufficient setup time TS 2  is provided relative to a fourth rising edge of the clock signal CK. A user logic circuit, not shown, connected to the output terminal of the user logic circuit L 4  receives the control signal OD 0  in synchronization of the fourth rising edge of the clock signal CK. 
       FIG. 8  shows an overview of an operation performed when the user logic unit UL 1  shown in  FIG. 3  is tested. The test is carried out in the logic test mode. In the logic test mode, the registers REG 1  and REG 3  are set using the scan path SP 1 . The selectors S and S 3  select outputs of the registers REG 1  and REG 3 . Since the memory macro MM is not accessed in the test of the user logic unit UL 1 , the level of the bypass mode signal BP may be set high H or low L. 
     After the start of the test, the user logic circuit L 1  receives, in synchronization with a first rising edge of the clock signal CK, the control signal WE 0  supplied from the register REG 1  ((a) in  FIG. 8 ). After the delay time IPATH corresponding to the logic of the user logic circuit L 1 , the level of the write enable signal /WE changes to, for example, low ((b) in  FIG. 8 ). Similarly, the user logic circuit L 3  receives, in synchronization with the first rising edge of the clock signal CK, the control signal ID 0  ((c) in  FIG. 8 ). After the delay time IPATH corresponding to the logic of the user logic circuit L 3 , the level of the input data signal ID changes to, for example, high ((d) in  FIG. 8 ). 
     When the user logic unit UL 1  operates correctly, the write enable signal /WE and the input data signal ID are supplied to the registers REG 4  and REG 6 , respectively, so that sufficient set time TS 1  is provided relative to a second rising edge of the clock signal CK. The registers REG 4  and REG 6  latch, in synchronization with the second rising edge of the clock signal CK, the logic levels of the write enable signal /WE and the input data signal ID, respectively ((e) and (f) in  FIG. 8 ). The timing of the registers REG 4  and REG 6  latching the logic levels are the same as the timing of the command decoder  12  and the data input buffer  16  of the memory macro MM latching the write enable signal /WE and the input data signal ID, respectively. The test control unit TCNT then reads out the information stored in the registers REG 4  and REG 6  using the scan path SP 2  and compares the information with an expected value. 
     As described above, the length of the signal line between the user logic circuit L 1  and the memory macro MM is designed to be equal to the length of the signal line between the user logic circuit L 1  and the register REG 4 . Similarly, the length of the signal line between the user logic circuit L 3  and the memory macro MM is designed to be equal to the length of the signal line between the user logic circuit L 3  and the register REG 6 . Accordingly, whether a signal output from the user logic unit UL 1  is supplied to the memory macro MM at correct timing can be tested in the test shown in  FIG. 8 . That is, operation timing of the user logic unit UL 1  can be evaluated or a stuck-at fault of the user logic unit UL 1  can be detected. 
     A test of the user logic circuit L 2  for outputting the input address signal IA can be executed in a manner similar to that of the tests of the user logic circuits L 1  and L 3 . At the time of the test of the user logic circuit L 1 , the level of the write enable signal /WE may be changed to high. At the time of the test of the user logic circuit L 2 , the level of the input data signal ID may be changed to low. 
       FIG. 9  shows an overview of an operation performed when the user logic unit UL 2  shown in  FIG. 3  is tested. The test is carried out in the logic test mode. In the logic test mode, a test signal is supplied to the memory macro MM using the user logic unit UL 1  and the output data signal OD fed from the memory macro MM is supplied to the user logic unit UL 2 . The bypass mode signal BP is set to the high level H. 
     First, the registers REG 1  and REG 3  are set using the scan path SP 1 . The selectors S 1  and S 3  select outputs of the registers REG 1  and REG 3 , respectively. The user logic circuit L 1  receives, in synchronization with a first rising edge of the clock signal CK, the control signal WE 0  supplied from the register REG 1  ((a) in  FIG. 9 ). After the delay time IPATH, the level of the write enable signal /WE changes to, for example, high ((b) in  FIG. 9 ). Similarly, the user logic circuit L 3  receives, in synchronization with the first rising edge of the clock signal CK, the control signal ID 0  ((c) in  FIG. 9 ) and changes the level of the input data signal ID to, for example, high after the delay time IPATH ((d) in  FIG. 9 ). 
     The memory macro MM receives, in synchronization with a second rising edge of the clock signal CK, the high-level write enable signal /WE and the high-level input data signal ID ((e) and (f) in  FIG. 9 ). More specifically, the read command RD 1  is supplied to the memory macro MM together with the input data signal ID. Since the level of the bypass mode signal BP is high, the input data signal ID received with the read command RD 1  is output as the output data signal OD after the read access time TA as shown in  FIG. 6  ((g) in  FIG. 9 ). 
     The output data signal OD is supplied to the user logic circuit L 4  (output user logic circuit). The control signal OD 0  is output from the user logic circuit L 4  after the delay time OPATH corresponding to the logic of the user logic circuit L 4  ((h) in  FIG. 9 ). When the user logic circuit L 4  operates correctly, the control signal OD 0  is supplied to the register REG 8  so that the sufficient setup time TS 2  is provided relative to a third rising edge of the clock signal CK. 
     The register REG 8  latches, in synchronization with the third rising edge of the clock signal CK, the logic level of the control signal OD 0 . The information stored in the register REG 8  is then read out by the test control unit TCNT using the scan path SP 1  and is compared with an expected value. When the information read out from the register REG 8  differs from the expected value, a defect of the user logic circuit L 4  (a stuck-at fault or a timing margin fault) is detected. 
     As described above, in this embodiment, a transition delay test of the user logic circuit L 4  including a test of operation timing of the memory macro MM can be executed using simple test patterns and simple test circuits (the flip-flop F/F and the data selector DSEL shown in  FIG. 1 ). Furthermore, since the test patterns are simple, the test patterns can be generated using an automatic test pattern generation (ATPG) method generally employed in a logic circuit fault detection test. As a result, the test cost can be reduced. 
       FIG. 10  shows an overview of an operation test of the memory macro MM shown in  FIG. 1 . The operation test of the memory macro MM is executed using the pattern generating circuit PATG and the check circuit CHK in a macro test mode. 
     For example, the pattern generating circuit PATG outputs, in synchronization with a first rising edge of the clock signal CK, the low-level write enable signal WE 0  (write command WR 1 ), the write address signal IA 0  (A 1 ), and the write data signal ID 0  (D 1 ) ((a), (b), and (c) in  FIG. 10 ). The signals WE 0 , IA 0 , and ID 0  are supplied to the memory macro MM as the write enable signal /WE, the address signal IA (A 1 ), and the input data signal ID (D 1 ) through the selectors S 4 , S 5 , and S 6 , respectively ((d), (e), and (f) in  FIG. 10 ). 
     Since no delay element, such as a logic circuit, is present between the pattern generating circuit PATG and the memory macro MM, the write enable signal /WE is supplied so that sufficient setup time TS 3  is provided relative to a second rising edge of the clock signal CK. The memory macro MM receives, in synchronization with the second rising edge of the clock signal CK, the low-level write enable signal /WE and executes a write operation ((g) in  FIG. 10 ). 
     The pattern generating circuit PATG then outputs, in synchronization with the second rising edge of the clock signal CK, the high-level write enable signal WE 0  (read command RD 1 ) and the read address signal IA 0 , for example ((h) and (i) in  FIG. 10 ). The memory macro MM receives, in synchronization with a third rising edge of the clock signal CK, the high-level write enable signal /WE and executes a read operation ((j) in  FIG. 10 ). After the access time TA, the memory macro MM outputs the output data signal OD (read data) ((k) in  FIG. 10 ). 
     The register REG 7  latches, in synchronization with the fourth rising edge of the clock signal CK, the output data signal OD ((l) in  FIG. 10 ). Since no delay element, such as a logic circuit, is present between the memory macro MM and the register REG 7 , the output data signal OD is supplied so that sufficient setup time TS 4  is provided relative to the fourth rising edge of the clock signal CK. The signal latched by the register REG 7  is supplied to the check circuit CHK. That is, the scan paths SP 1  and SP 2  are not used. The check circuit CHK compares a logic level of the output data signal OD with an expected value to detect whether the memory macro MM has a defect. In this manner, since the operation test of the memory macro MM is executed using dedicated test circuits (the pattern generating circuit PATG and the check circuit CHK) without using the user logic circuits L 1 -L 4 , time taken for the test can be shortened. 
       FIG. 11  shows a memory macro MM employed before the memory macro MM shown in  FIG. 1  is proposed. The memory macro MM shown in  FIG. 11  is not widely known. Referring to  FIG. 11 , the flip-flop F/F, the data selector DSEL, and the bypass mode terminal BP are omitted from the memory macro shown in  FIG. 1 . The remaining configuration is the same as that shown in  FIG. 1 . A system SYS has the same configuration as that shown in  FIGS. 2 and 3 . 
       FIG. 12  shows an overview of an operation performed when the user logic unit UL 2  is tested in a system having the memory macro MM shown in  FIG. 11 . The test is executed in the logic test mode. In the logic test mode, a register REG 7  is set using the scan path SP 2 . The selector S 4  selects an output of the register REG 7 . Since the memory macro MM is not accessed in this test, the level of the bypass mode signal BP may be high H or low L. 
     A user logic circuit L 4  receives, in synchronization with a first rising edge of a clock signal CK, a control signal DMY from the register REG 7  ((a) in  FIG. 12 ). The level of the control signal OD 0  changes to, for example, high after the delay time OPATH corresponding to the logic of the user logic circuit L 4  ((b) in  FIG. 12 ). In the example shown in  FIG. 11 , the access time TA of the memory macro MM is not included in a first clock cycle of the clock signal CK. Accordingly, a register REG 8  latches the control signal OD 0  so that sufficient setup time TS 5  is provided relative to a second rising edge of the clock signal CK. The setup time TS 5  is much longer than the setup time TS 2  shown in  FIG. 9 . As a result, a stuck-at fault of the user logic circuit L 4  can be detected but operation timing of the user logic circuit L 4  may not be evaluated. 
     As described above, in this embodiment, the input data signal ID received with the data input terminal ID of the memory macro MM can be output, in synchronization with actual operation timing of the memory cell array ARY, to the data output terminal OD as the output data signal OD during the test mode. The memory macro MM can be operated in a simulated manner using a small number of input signals and simple test circuits (the flip-flop F/F and the data selector DSEL) and the output data signal OD can be generated without writing the data in the memory cell MC. 
     Accordingly, the test of the user logic circuit L 4  that operates in response to the output data signal OD can be executed using simple test patterns. That is, a timing test of the user logic circuit L 4  including a test if operation timing of the memory macro MM can be executed using simple test patterns. As a result, the test cost can be reduced. The operation timing of the memory cell array ARY that operates asynchronously with the clock signal CK can be realized using simple test circuits (the flip-flop F/F and the data selector DSEL). 
     The input data signal ID to be supplied to the memory macro MM is stored in the register REG 3  through the scan path SP 1 . The user output signal OD 0  that is output from the user logic circuit L 4  and is stored in the register REG 8  is transferred to the test control unit TCNT through the scan path SP 1 . With this configuration, the timing test of the user logic circuit L 4 , including the test of the operation timing of the memory macro MM, can be readily executed, thus leading to a decrease in the test cost. In particular, when the user logic circuit L 3  is inserted between the register REG 3  and the memory macro MM, the operation test of the user logic circuit L 4 , including the test of the operation timing of the memory macro MM, can be executed using simple test patterns. 
       FIG. 13  shows an example of a memory macro MM according to another embodiment. The similar or like references designate elements commonly described in the above embodiment and a detailed description thereof is omitted. The configuration other than the configuration of the memory macro MM is the same as that employed in the above-described embodiment. More specifically, the memory macro MM is mounted on the system SYS shown in  FIGS. 2 and 3 . 
     The memory macro MM has a timing generator  14 A instead of the timing generator  14  shown in  FIG. 1 . In addition, a data output buffer (data output unit)  18 A is provided between a read amplifier RA and a data selector DSEL. The other configuration of the memory macro MM is the same as that shown in  FIG. 1 . 
     A load of a test output data signal line TDOUT is designed to be equal to a load of an output data signal line DOUT 1  connected to an output terminal of the data output buffer  18 A. For example, the signal lines TDOUT and DOUT 1  have the same structure and the lengths thereof are equal to each other. With such a configuration, output timing of a test output data signal TDOUT from a flip-flop F/F and output timing of an output data signal DOUT 1  from the data output buffer  18 A can be set equal. Accordingly, as in the case of the above-described embodiment, the access time TA of the memory macro MM in a normal operation mode can be set equal to the access time TA of the memory macro MM in a logic test mode. Accordingly, the memory macro MM can be operated in a simulated manner using simple test patterns. 
     Generally, the length of the signal line (DOUT 1 ) extending from the data output buffer  18 A to the data output terminal OD is shorter than the length of the output data signal line DOUT extending from the read amplifier RA to the data output buffer  18 A. In addition, when the data output terminal OD has a plurality of signal lines corresponding to a plurality of bits, a variance in the lengths of the signal lines (DOUT 1 ) is smaller than a variance in the lengths of the output data signal lines DOUT because the lengths of the memory cell array ARY and the read amplifier RA in the horizontal direction of the drawing are longer. Accordingly, in this embodiment, the length of the test output data signal line TDOUT can be set shorter than that shown in  FIG. 1 . As a result, an area where the test output data signal lines TDOUT are disposed can be reduced and the size of the memory macro MM can be decreased. In addition, since the variance in the loads of the test output data signal lines TDOUT relative to the respective output data signal lines DOUT can be minimized, the read access time TA can be very accurately set equal to the read access time TA of the normal operation mode in the logic test mode, in which the level of the bypass mode signal BP is set to high when the test output data signal lines TDOUT corresponding to a plurality of bits are provided. 
     In addition to functions of the timing generator  14  shown in  FIG. 1 , the timing generator  14 A additionally has a function for outputting an output data enable signal ODEN. When the level of a write enable signal /WE is high, a delay circuit ENDLY changes the level of the output data enable signal ODEN to high after a predetermined time has passed since a rising edge of an active signal ACTP. The delay time of the delay circuit ENDLY is slightly longer than that of a delay circuit ODLY. The delay circuit ENDLY keeps the output data enable signal ODEN at the high level for a predetermined period (approximately one clock cycle). 
     While the level of the output data enable signal ODEN is high, the data output buffer  18 A outputs an output data signal DOUT supplied from the read amplifier RA as an output data signal DOUT 1 . In this embodiment, the flip-flop F/F latches, in synchronization with the output data enable signal ODEN instead of the output data latch signal ODLAT, a logic level of the input data signal DIN and outputs the logic level as a test output data signal TDOUT. 
       FIG. 14  shows an operation of the memory macro MM shown in  FIG. 13  performed in a logic test mode for testing a user logic circuit L 4 . In this embodiment, the test output data signal TDOUT and the output data signal OD are output in synchronization with a rising edge of the output data enable signal ODEN. The other operations are the same as those shown in  FIG. 6 . Since the lengths of the output data signal line DOUT 1  and the test output data signal line TDOUT shown in  FIG. 13  are the same, the read access time between reception of a read command RD and output of read data D 1  is equal to TA shown in  FIGS. 5 and 6 . 
     As described above, advantages similar to those provided by the above-described embodiment can be obtained in this embodiment. Furthermore, since the area where the test output data signal line TDOUT is disposed can be reduced in this embodiment, the size of the memory macro MM can be decreased. When the test output data signal lines TDOUT corresponding to a plurality of bits are provided, the read access time TA can be highly accurately set equal to the read access time TA of the normal operation mode in the test mode, in which the level of the bypass mode signal BP is set to high. As a result, the test of the user logic circuit L 4  can be executed using the same timing margin as that of an actual operation of the memory macro MM. 
       FIG. 15  shows a detailed view of major parts of a system SYS according to another embodiment. The similar or like references designate elements commonly described in the above embodiment and a detailed description thereof is omitted. In this embodiment, the system SYS has registers REG 11 -REG 13  instead of the registers REG 4 -REG 6  shown in  FIG. 3 . The registers REG 11 -REG 13  are formed in the memory macro MM. The registers REG 11 -REG 13  have the same configuration as that of the registers REG 4 -REG 6  ( FIG. 4 ). The remaining configuration of the system SYS is the same as that shown in  FIGS. 2 and 3  except that an external terminal for a scan path SP 2  is formed in the memory macro MM. 
       FIG. 16  shows a detailed view of the memory macro MM shown in  FIG. 15 . The memory macro MM has a command decoder  12 B instead of the command decoder  12  shown in  FIG. 1 . Since the register REG 13  has a function of a data input buffer, the data input buffer  16  shown in  FIG. 1  is omitted. The remaining configuration is the same as that shown in  FIG. 11  except that the registers REG 11 -REG 13  are formed. The major parts of the memory macro MM may have the configuration shown in  FIG. 13  instead of the configuration shown in  FIG. 1 . More specifically, the memory macro MM may include the data output buffer  18 A. 
     Each register REG (REG 11 -REG 13 ) has a scan multiplexer SM (SM 11 -SM 13 ) and a flip-flop F/F (F/F 11 -F/F 13 ). An operation of the registers REG 11 -REG 13  is the same as that of the registers REG 4 -REG 6  described with reference to  FIG. 4 . The flip-flop F/F 13  of the register REG 13  is connected to a scan path SP 2  and operates as a holding unit for holding an input data signal ID. 
     The command decoder  12 B has the same function as the command decoder  12  shown in  FIG. 1  except for operating asynchronously with a clock signal CK. In this embodiment, the register REG 11  latches, in synchronization with the clock signal CK, a write enable signal /WE. Accordingly, the command decoder  12 B has to operate asynchronously with the clock signal CK. That is, the register REG 11  and the command decoder  12 B realize the function of the command decoder  12  shown in  FIG. 1 . 
       FIG. 17  shows an overview of an operation performed when user logic units UL 1  and UL 2  shown in  FIG. 15  are tested. In this embodiment, a test of the user logic unit UL 1  can be executed during execution of the test shown in  FIG. 9 . The level of the bypass mode signal BP is set to high. Accordingly, a logic level of an input data signal DIN is directly output to a data output terminal OD as an output data signal OD using the flip-flop F/F in a read operation. The period when the level of a signal SM is high corresponds to a period (scan shift periods SS 1  and SS 2 ) when a scan multiplexer SM selects the scan paths SP 1  and SP 2 . The period when the level of the signal SM is low corresponds to a period (test period TEST) when the scan multiplexer SM selects signal lines connected to the user logic units UL 1  and UL 2 . 
     During the scan shift period SS 1 , input patterns (test input signals) for testing a user logic unit UL 1  are sequentially set in the registers REG 1 -REG 3  using the scan paths SP 1  and SP 2 . In addition, input patterns (test input signals) for testing the user logic unit UL 2  are sequentially set in the registers REG 11 -REG 13  (flip-flops F/F 11 -F/F 13 ). 
     The test control unit TCNT then sets the level of the signal SM to low. The test patterns set in the registers REG 1 -REG 3  and REG 11 -REG 13  are supplied to the user logic circuits L 1 -L 3 , the memory macro MM, and the user logic circuit L 4 . In this manner, the user logic circuits L 1 -L 3  operate in accordance with the input patterns set in the registers REG 1 -REG 3 , respectively. The memory macro MM operates in accordance with the input patterns set in the registers REG 11 -REG 13 . The user logic circuit L 4  operates in accordance with the output data signal OD that is output from the data output terminal OD of the memory macro MM. 
     The registers REG 11 -REG 13  latch, in synchronization with a fourth rising edge of the clock signal CK, output signals supplied from the user logic circuits L 1 -L 3 , respectively. The register REG 7  latches a signal output from the memory macro MM, whereas the register REG 8  latches a signal output from the user logic circuit L 4 . 
     The test control unit TCNT then sets the level of the signal SM to high. Information stored in the registers REG 11 -REG 13  and REG 8 , which are shown with thick frames in the drawing, is transferred to the test control unit TCNT through the scan path SP 2  and is compared with an expected value. When the information read out from the registers REG 11 -REG 13  differs from the expected value, a defect (a stuck-at fault or a timing margin fault) of the user logic circuits L 1 -L 3  is detected. When the information read out from the register REG 8  differs from the expected value, a defect (a stuck-at fault or a timing margin fault) of the user logic circuit L 4  is detected. In this manner, tests of the user logic units UL 1  and UL 2  can be simultaneously executed during one clock cycle. 
     The information stored in the register REG 7  is transferred to the test control unit TCNT through the scan path SP 2  and is compared with an expected value. In this manner, whether the fault caused in the test of the user logic unit UL 2  results from the memory macro MM or the user logic circuit L 4  can be identified. 
     As described above, advantages similar to those provided by the above-described embodiments can be obtained in this embodiment. Furthermore, in this embodiment, the tests of the user logic units UL 1  and UL 2  can be executed at the same time during one clock cycle. In particular, the test patterns (test input signals) for testing the user logic circuit L 4  can be set in the registers REG 11 -REG 13  using the scan path SP 2  without supplying the test patterns through the user logic circuits L 1 -L 3 . Accordingly, the test of the user logic circuit L 4  can be executed using simple test patterns. That is, test patterns can be generated using an automatic test pattern generation (ATPG) method generally used in a logic circuit fault detection test. As a result, the test cost can be reduced. 
     In the above-described embodiments, the description has been given for the example in which test circuits (the flip-flop F/F and the data selector DSEL) are provided in the memory macro MM for outputting data signals stored in the memory cells MC after a predetermined time has passed since reception of a read command and the user logic unit UL 2  is tested using the test circuits. However, test circuits (the flip-flop F/F and the data selector DSEL) may be provided in another function macro (a data processing macro, such as a CPU macro and an MPEG macro) for outputting a stored data signal after a predetermined time has passed since reception of a read command and the user logic unit UL 2  may be tested using these test circuits. 
     The features and advantages of the embodiments become apparent from the detailed description given above. It is intended that the attached claims include the features and advantages of the above-described embodiments without departing from the spirit and scope thereof. In addition, various improvements and alternations should easily occur to those skilled in the art and it should be understood that the scope of the embodiments having the inventive step is not limited to the above-described embodiments but can include appropriate improvements and equivalences thereof included in the scope disclosed in the embodiments.