Patent Publication Number: US-5832033-A

Title: Clock disturbance detection based on ratio of main clock and subclock periods

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the invention 
     The present invention generally relates to a clock monitor circuit, and in particular to a circuit for detecting a clock disturbance which occurs due to the mixing of similar pulses into or lack of necessary pulses of a bipolar clock signal. 
     2. Description of the Related Art 
     A bipolar clock generally consists of a pulse stream with the polarity alternating in time as follows: +1, 0, -1, 0, +1, and so on. However, it is well known as a bipolar violation method that the polarity alternation order is violated in a predetermined period like this: +1, 0, +1, 0, -1, 0, and so on. Such a bipolar violation method is frequently employed to superimpose a subclock on a main clock. A clock extractor extracts the subclock from the bipolar clock and supplies it as a reference phase clock to a data processing circuit. For such a clock extractor, a clock monitor circuit is necessary to avoid recognizing a pulse disturbance as the bipolar violation. 
     A clock extracting circuit employing the bipolar violation method is disclosed in Japanese Patent Unexamined Publication No. 3-272245. Referring to FIG. 1, a positive-polarity pulse detector 1 detects a positive-pulse signal S1 from the bipolar clock signal by comparing the bipolar clock signal with a first reference voltage Ref-p. Similarly, a negative-polarity pulse detector 2 detects a negative-pulse signal S2 from the bipolar clock signal by comparing the bipolar clock signal with a second reference voltage Ref-n. After the bipolar clock signal has been divided into the positive-pulse signal S1 and the negative-pulse signal S2, a bipolar violation detector 3 receives them to detect the subclock signal. The clock extracting circuit further includes a clock monitor circuit comprising two counters 4 and 5 and a comparator 6. The respective counters 4 and 5 count pulses of the positive-pulse signal S1 and the negative-pulse signal S2 while concurrently reset in a predetermined period. The comparator 6 compares the resultant count values of the counters 4 and 5 in the predetermined period and produces an alarm signal when the count difference is larger than predetermined. 
     However, the conventional clock monitor circuit cannot detect a clock disturbance in cases where equal numbers of pulses are mixed into or removed from both the positive-pulse signal S1 and the negative-pulse signal S2, because the conventional clock monitor circuit detects the clock disturbance based on the count difference between the counters 4 and 5 separately counting positive pulses and negative pulses, respectively. 
     SUMMARY OF THE INVENTION 
     An object of the present invention is to provide a clock monitor circuit which detects a clock disturbance with reliability. 
     Another object of the present invention is to provide a clock disturbance detecting circuit and method which properly detect a clock disturbance such as a case where the positive- and negative-pulses both change in number. 
     According to the present invention, a first-polarity pulse signal and a second-polarity pulse signal are produced from a bipolar pulse signal including a main pulse signal and a subpulse signal. The period of the subpulse signal is a predetermined integral multiple of that of the main pulse signal. A first disturbance is detected from the first-polarity pulse signal by checking whether a first pulse signal coincides with a second pulse signal using said second-polarity pulse signal as a first timing signal. The first pulse signal corresponds to the first-polarity pulse signal at a first timing instant and the second pulse signal corresponds to the first-polarity pulse signal at a second timing instant. The timing difference between the first and second timing instants corresponds to the period ratio of the main pulse signal and the subpulse signal. The first disturbance is detected when the first pulse signal does not coincide with the second pulse signal. 
     According to an aspect of the present invention, a circuit is comprised of a shift register which shifts first data corresponding to the first-polarity pulse signal in accordance with the first timing signal to produce the first pulse signal and the second pulse signal. The circuit is further comprised of a coincidence checking circuit which checks whether the first pulse signal coincides with the second pulse signal to produce a first detection signal indicating the first disturbance when the first pulse signal is not identical with the second pulse signal. 
     According to another aspect of the present invention, the circuit is further comprised of a shift register which shifts second data corresponding to the second-polarity pulse signal using the second-polarity pulse signal as a second timing signal and produces the third pulse signal and the fourth pulse signal. The circuit is still further comprised of a coincidence checking circuit which checks whether the third pulse signal coincides with the fourth pulse signal to produce a second detection signal indicating the second disturbance when the third pulse signal is not identical with the fourth pulse signal. The circuit is still more further comprised of an output circuit for producing a detection signal of the bipolar pulse disturbance based on the first disturbance and the second disturbance. For instance, the output circuit is a logical-OR circuit which receives the first disturbance and the second disturbance. 
     In cases where no bipolar pulse disturbance occurs, since the shift register shifts the data according to the second-polarity pulse signal and the data stored in the shift register always has a predetermined repetition period of the subpulse, the first data and the second data are identical at all times. 
     On the contrary, once an extra pulse is added to or a necessary pulse slips away from the bipolar pulse signal, the pulse repetition order is vanished, resulting in non-coincidence between the first data and the second data of the shift register. Therefore, the disturbance signal is produced by the comparator when a bipolar pulse disturbance occurs. Since the logical-OR circuit receives the first disturbance signal and the second disturbance signal, the circuit detects the bipolar pulse disturbance when at least one of the first disturbance signal and the second disturbance signal occurs. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram showing a clock extracting circuit employing a conventional clock monitor circuit; 
     FIG. 2 is a block diagram showing a clock extracting circuit employing a clock monitor circuit according to an embodiment of the present invention; 
     FIG. 3 is a detailed block diagram showing the clock monitor circuit according to the embodiment; and 
     FIG. 4 is a timing chart showing an operation of the clock monitor circuit as shown in FIG. 3. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Referring to FIG. 2, a clock extractor according to an embodiment of the present invention receives a bipolar clock signal BCL including a main clock of a period T m  and a subclock of a period T sub  superimposed on the main clock and produces the subclock and an alarm signal which indicates a clock disturbance. 
     The clock extractor is comprised of a unipolar signal extractor 100 including a positive-polarity pulse detector 101 and a negative-polarity pulse detector 102 which receive the bipolar clock signal BCL and produce a positive-polarity pulse signal SP and a negative-polarity pulse signal SN, respectively. As described above, the positive-polarity pulse detector 101 detects the positive-polarity pulse signal SP from the bipolar clock signal BCL by comparing the bipolar clock signal BCL with the first reference voltage Ref-p. Similarly, the negative-polarity pulse detector 102 detects the negative-polarity pulse signal SN from the bipolar clock signal BCL by comparing the bipolar clock signal BCL with the second reference voltage Ref-n. As well known, the positive-polarity and negative-polarity pulse detectors 101 and 102 are both formed with a differential amplifier. A bipolar violation detector 103 receives the positive-polarity and negative-polarity pulse signals SP and SN and reproduces the subclock signal superimposed on the bipolar clock signal BCL. 
     The clock extractor is further provided with a first error detector 104, a second error detector 105, and an OR circuit 106. The first error detector 104 and the second error detector 105 receive the positive-polarity and negative-polarity pulse signals SP and SN, respectively, and output a first error signal E1 and a second error signal E2 to the OR circuit 106. The OR circuit produces the alarm signal when receiving at least one of the first error signal E1 and the second error signal E2. 
     The first error detector 104 is comprised of a frequency divider 201, a shift register 202, and a non-coincidence determination circuit 203. The frequency divider 201 divides the positive-polarity pulse signal SP in frequency to output the divided signal SPd to the shift register 202. Receiving the divided signal SPd as data, the shift register 202 shifts the data in accordance with the negative-polarity pulse signal SN which is received as a shift clock from the negative-polarity pulse detector 102. The shift register 202 outputs first data shifted by i bits and second data shifted by j bits to the non-coincidence determination circuit 203, where i and j are a positive integer and are determined based on a ratio of the periods T m  and T sub  of the main clock and the subclock as described later. The non-coincidence determination circuit 203 receives the first data and the second data from the shift register 202 and outputs the error signal E1 to the OR circuit 106 when the first data is not identical with the second data. 
     Similarly, the second error detector 105 is comprised of a frequency divider 301, a shift register 302, and a non-coincidence determination circuit 303. The frequency divider 301 divides the negative-polarity pulse signal SN in frequency to output the divided signal SNd to the shift register 302. Receiving the divided signal SNd as data, the shift register 302 shifts the data in accordance with the positive-polarity pulse signal SP which is received as a shift clock from the positive-polarity pulse detector 101. The shift register 302 outputs third data shifted by k bits and fourth data shifted by l bits to the non-coincidence determination circuit 303, where k and l are a positive integer and are determined based on a ratio of the periods T m  and T sub  of the main clock and the subclock as described later. The non-coincidence determination circuit 303 receives the third data and the fourth data from the shift register 302 and outputs the error signal E2 to the OR circuit 106 when the third data and the fourth data are not identical. 
     Referring to FIG. 3, a more detailed circuit arrangement of the clock monitor circuit will be described hereinafter. In the first error detector 104, the frequency divider 201 divides the positive-polarity pulse signal SP in frequency by two and outputs the divided signal SPd to the serial input terminal of the shift register 202. The shift register 202 has two parallel output terminals corresponding to the i-bit shift and the (i+8)-bit shift, respectively. In this case, it is assumed that the period T sub  of the subclock is 8 times the period T m  of the main clock. The stored data is shifted in accordance with the negative-polarity pulse signal SN which is received as a shift clock from the negative-polarity pulse detector 102. The shift register 202 outputs the first data shifted by i bits and the second data shifted by i+8 bits in parallel to an exclusive-OR circuit 203 which serves as the non-coincidence determination circuit. Receiving the first data and the second data from the shift register 202, the exclusive-OR circuit 203 outputs the error signal E1 to the OR circuit 106 when the first data is not identical with the second data. 
     The second error detector 105 has the same circuit configuration as the first error detector 104 except that the shift register 302 operates in accordance with the positive-polarity pulse signal SP serving as a shift clock. The shift register 302 outputs the third data shifted by k bits and the fourth data shifted by k+8 bits in parallel to an exclusive-OR circuit 303 which outputs the error signal E2 to the OR circuit 106 when the third data is not identical with the fourth data. Taking the second error detector 105 as an example, an operation of the clock monitor circuit will be described hereinafter. 
     As illustrated in FIG. 4, it is assumed that the bipolar clock BCL has the main clock period T m  and the subclock period T sub  (=8T m ) with the bipolar violation occurring in period T sub  (F a , F b , F c , and so on) and the integer numbers i and k are set at 1. Since the ratio of the subclock period T sub  to the main clock period T m  is 8, the shift-bit difference between the parallel output terminals is also set at 8 in each of the shift registers 202 and 203. It is needless to say that the shift-bit difference may be set at an integral multiple of 8. The positive-polarity pulse signal SP and the negative-polarity pulse signal SN each having a repetition period 2T sub  are output to the frequency dividers 201 and 301, respectively. The frequency divider 301 divides the negative-polarity pulse signal SN in frequency by two to output the divided pulse signal SNd to the shift register 302. 
     In cases where no clock disturbance occurs, since the shift register 302 shifts the data according to the positive-polarity pulse signal SP and the divided-by-2 pulse signal SNd always has the repetition period 2T sub , the third data shifted by 1 bit and the fourth data shifted by 1+8 bits are identical at all times as shown in FIG. 4. On the contrary, once an extra pulse is added or a necessary pulse slips away, the pulse repetition order is vanished, resulting in non-coincidence between the 1-bit-shift data and the (1+8)-bit-shift data of the shift register 302. Therefore, the error signal E2 of a logical high value is output from the exclusive-OR circuit 303 to the OR circuit 106 when a clock disturbance occurs. 
     Needless to say, the first error detector 104 performs the similar operation to the second error detector 105. Since the OR circuit 106 outputs a clock disturbance detection signal of a logical high value when at least one of the error signals E1 and E2 goes high, a bipolar clock disturbance can be detected with reliability even when the same clock disturbance occurs in both the positive-polarity and the negative-polarity pulses.