Patent Publication Number: US-11650940-B2

Title: Storage device including reconfigurable logic and method of operating the storage device

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This is a Continuation of U.S. application Ser. No. 17/080,614, filed Oct. 26, 2020, which is a Continuation of U.S. application Ser. No. 16/363,791, filed Mar. 25, 2019, issued as U.S. Pat. No. 10,817,440 on Oct. 27, 2020, and a claim of priority under 35 U.S.C. § 119 is made to Korean Patent Application No. 10-2018-0058641, filed on May 23, 2018 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. 
    
    
     BACKGROUND 
     1. Technical Field 
     The present disclosure relates to storage devices. More particularly, the present disclosure relates to a storage device that includes a reconfigurable logic circuit, and a method of operating the storage device. 
     2. Description of Related Art 
     Storage systems may include a host and a storage device. To increase a processing speed of storage systems, the storage systems may further include an accelerator that helps a calculation of the host by performing some of the calculations performed by the host. When the accelerator is disposed outside a storage device, the time taken for a calculation operation of the accelerator may increase according to the time taken to input or output data between the host, the storage device, and the accelerator. 
     The accelerator may be classified as a dedicated hardware accelerator that performs a set function, or a reconfigurable accelerator that is reconfigurable according to a design file, such as a field programmable gate array (FPGA) image. Recently, because the host is required to perform various applications and process each application at high speed, a reconfigurable accelerator, such as an FPGA, reconfigurable to correspond to the various applications is in high demand. 
     SUMMARY 
     The present disclosure provides a storage device, a storage system including the storage device, and a method of operating the storage device. The storage device includes a reconfigurable logic circuit that is adaptively reconfigurable according to a function required by a host during an operation of the storage device. 
     According to an aspect of the present disclosure, a storage device includes a reconfigurable logic circuit, a control logic circuit, and non-volatile memory. The storage device is capable of communicating with a host. The reconfigurable logic circuit is changeable from a first accelerator to a second accelerator during an operation of the storage device. The control logic circuit is configured to receive, from the host, a host command including information about a function required by the host and dynamically reconfigure the reconfigurable logic circuit such that the reconfigurable logic circuit performs the function according to the received host command. The non-volatile memory is connected to the control logic circuit. 
     According to another aspect of the present disclosure, a storage system includes a storage device and a host. The storage device includes a reconfigurable logic circuit. The host is capable of executing multiple applications and is configured to decide reconfiguration of the reconfigurable logic circuit such that the reconfigurable logic circuit operates as a first accelerator corresponding to a first application from among the applications. The host is also configured to transmit a first host command including information about the first application to the storage device. The reconfigurable logic circuit is reconfigured to the first accelerator according to the first host command. 
     According to another aspect of the present disclosure, storage device includes a reconfigurable logic circuit. A method of operating the storage device includes receiving, by the storage device from a host, a host command including information about a function required by the host. The method of operating the storage device also includes the storage device dynamically reconfiguring the reconfigurable logic circuit to correspond to the function, by downloading, into the reconfigurable logic circuit, a design file for implementing the function into the reconfigurable logic circuit, according to the host command. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Embodiments of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings in which: 
         FIG.  1    is a block diagram illustrating a storage system according to an embodiment of the present disclosure; 
         FIG.  2    is a block diagram illustrating a storage system according to another embodiment of the present disclosure; 
         FIG.  3    is a flowchart illustrating a method of operating a storage device, according to an embodiment of the present disclosure; 
         FIG.  4    is a block diagram illustrating an example in which a reconfigurable logic circuit included in a storage device included in the storage system of  FIG.  1    is reconfigured to a first accelerator; 
         FIG.  5    is a block diagram illustrating an example in which a reconfigurable logic circuit included in a storage device included in the storage system of  FIG.  1    is reconfigured to a second accelerator; 
         FIG.  6    is a flowchart illustrating an operation between a host, a control logic circuit, and a reconfigurable logic circuit according to an embodiment of the present disclosure; 
         FIG.  7    is a block diagram illustrating an example of a storage device according to an embodiment of the present disclosure; 
         FIG.  8    is a block diagram illustrating another example of a storage device according to an embodiment of the present disclosure; 
         FIG.  9    is a block diagram illustrating a first data path in a storage system according to an embodiment of the present disclosure; 
         FIG.  10    is a flowchart illustrating an example of an operation between a host, a control logic circuit, and a reconfigurable logic circuit included in the storage system of  FIG.  9   ; 
         FIG.  11    is a flowchart illustrating another example of an operation between a host, a control logic circuit, and a reconfigurable logic circuit included in the storage system of  FIG.  9   ; 
         FIG.  12    is a block diagram illustrating a second data path in a storage system according to an embodiment of the present disclosure; 
         FIG.  13    is a flowchart illustrating an example of an operation between a host, a control logic circuit, and a reconfigurable logic circuit included in the storage system of  FIG.  12   ; 
         FIG.  14    is a block diagram illustrating a third data path in a storage system according to an embodiment of the present disclosure; 
         FIG.  15    is a block diagram illustrating various data paths in a storage system according to an embodiment of the present disclosure; 
         FIG.  16 A  illustrates a mapping table for non-volatile memory according to an embodiment of the present disclosure; 
         FIG.  16 B  illustrates a mapping table for volatile memory according to an embodiment of the present disclosure; 
         FIG.  17    is a block diagram illustrating a server according to an embodiment of the present disclosure; 
         FIG.  18    is a block diagram illustrating a network system according to an embodiment of the present disclosure; and 
         FIG.  19    is a block diagram illustrating a network system according to an embodiment of the present disclosure. 
     
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
       FIG.  1    is a block diagram illustrating a storage system  10  according to an embodiment of the present disclosure. 
     Referring to  FIG.  1   , the storage system  10  may include a storage device  100  and a host  200 , and the storage device  100  may include a control logic  110 , an NVM  120  (non-volatile memory), and a reconfigurable logic  130 . The reconfigurable logic  130  may be an accelerator that helps a calculation of the host  200  by performing some of the calculations performed by the host  200 . For example, the reconfigurable logic  130  may be a field programmable gate array (FPGA). However, the reconfigurable logic  130  is not limited thereto, and the reconfigurable logic  130  may be a programmable logic device (PLD) or a complex PLD (CPLD). In other words, references to logic such as control logic  110  and reconfigurable logic  130  herein are references to a circuit of one or more circuit elements such as a FPGA, a PLD, a CPLD, and/or a processor including an application-specific integrated circuit (ASIC). Moreover, in FIGS. herein including  FIG.  1   , circuitry may be shown as, for example, a “decider”, a “decoder”, a “controller”, an “accelerator”, and a “processor”. As is traditional in the field of the inventive concept(s) described herein, examples may be described and illustrated in terms of blocks which carry out a described function or functions. These blocks, which may be referred to herein as a decider, a decoder, a controller, an accelerator, and a processor (in addition to those referred to as logic), or the like, are physically implemented by analog and/or digital circuits such as logic gates, integrated circuits, microprocessors, microcontrollers, memory circuits, passive electronic components, active electronic components, optical components, hardwired circuits and the like, and may optionally be driven by firmware and/or software. The circuits may, for example, be embodied in one or more semiconductor chips, or on substrate supports such as printed circuit boards and the like. The circuits constituting a block may be implemented by dedicated hardware, or by a processor (e.g., one or more programmed microprocessors and associated circuitry), or by a combination of dedicated hardware to perform some functions of the block and a processor to perform other functions of the block. Each block of the examples may be physically separated into two or more interacting and discrete blocks without departing from the scope of the inventive concepts. Likewise, the blocks of the examples may be physically combined into more complex blocks without departing from the scope of the inventive concepts. 
     According to an embodiment, the control logic  110  may be implemented as a first chip, the reconfigurable logic  130  may be implemented as a second chip, and the first chip and the second chip may be mounted on a single board and may be electrically connected to each other. According to an embodiment, the control logic  110  may be implemented as a first chip, the reconfigurable logic  130  may be implemented as a second chip, and the first chip and the second chip may constitute a package-on-package (POP). For example, the control logic  110  may be implemented using an application specific integrated circuit (ASIC) chip, and the reconfigurable logic  130  may be implemented using an FPGA. 
     The reconfigurable logic  130  may be reconfigured according to a host command CMD including information about a function required by the host  200 . According to an embodiment, the host command CMD may include information about an application that is executed by the host  200 . According to an embodiment, the host command CMD may include design file information corresponding to an application that is executed by the host  200 . 
     In detail, the control logic  110  may download or program, in the reconfigurable logic  130 , a design file for programming the reconfigurable logic  130 , based on the host command CMD. For example, when the reconfigurable logic  130  is an FPGA, the design file may be an FPGA image, and the control logic  110  may reconfigure the reconfigurable logic  130  by downloading the FPGA image into the reconfigurable logic  130 . 
     The design file may define a connection between logic blocks included in the reconfigurable logic  130 , interconnections, and input/output (I/O) cells. The design file may be implemented in a Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL), or a Hardware Description Language (HDL) such as Verilog. In detail, the design file may be generated by a synthesis via a register transfer level (RTL) design or may be generated via a top-level compile after coding of a software kernel and a hardware kernel by using an Open Computing Language (CL). 
     According to the type of design file downloaded by the reconfigurable logic  130 , the type of calculation performed by the reconfigurable logic  130  may vary. For example, when a first design file is downloaded into the reconfigurable logic  130 , the reconfigurable logic  130  may operate as a first accelerator, and, when a second design file is downloaded into the reconfigurable logic  130 , the reconfigurable logic  130  may operate as a second accelerator. According to an embodiment, the reconfigurable logic  130  may be reconfigured according to the host command CMD during an operation of the storage system  10 . 
     According to an embodiment, the reconfigurable logic  130  may perform multimedia transcoding or eraser coding. According to an embodiment, the reconfigurable logic  130  may perform a machine learning algorithm, such as a convolutional neural network (CNN) or a recurrent neural network (RNN). For example, the reconfigurable logic  130  may be configured to perform video transcoding and may be reconfigured to perform a CNN according to a host command CMD for instructing the CNN, during an operation of the storage system  10 . 
     For example, the reconfigurable logic  130  may perform inline processing, pre-processing, pre-filtering, cryptography, compression, protocol bridging, and the like. For example, the reconfigurable logic  130  may perform at least one of a sorting operation, a searching operation, a logic operation, and an arithmetic operation. The logic operation may represent a calculation performed by any of various logic gates, such as an AND gate, an OR gate, an XOR gate, a NOR gate, a NAND gate, or a combination of two or more of these calculations. Examples of the calculations performed by the reconfigurable logic  130  are not limited thereto, and calculations performed by the reconfigurable logic  130  may be arbitrary calculations corresponding to some of the calculations performed by the host  200 . That is, calculations performed by the reconfigurable logic  130  may be calculations that can be, may be, and sometimes or otherwise are performed by the host  200 , but that are performed by the reconfigurable logic  130  dynamically and on-demand based on the host command CMD. 
     The host  200  may communicate with the storage device  100  via any of various interfaces. For example, the host  200  may be implemented using an application processor (AP) or a System-On-a-Chip (SoC). The host  200  may execute various applications including a first application (APP1)  210   a  and a second application (APP2)  210   b . Additionally, the host may include a reconfiguration decider  220 . The type of application that is executed by the host  200  may be determined by a user input. For example, the first application APP1  210   a  and the second application APP2  210   b  may be a multimedia reproducing application, an image recognition application, a voice recognition application, an encryption application, a search application, and the like. 
     The reconfiguration decider  220  may decide reconfiguration or non-reconfiguration of the reconfigurable logic  130  according to an application that the host  200  desires to execute. The reconfiguration decider  220  may generate a host command CMD including information about an application the host  200  desires to execute, a function corresponding to the application, or a design file corresponding to the application. This host command CMD may be referred to as a reconfiguration command. 
     The host  200  may transmit, to the storage device  100 , a design file for reconfiguring the reconfigurable logic  130 . The host  200  may transmit, to the storage device  100 , control signals for controlling the reconfigurable logic  130 . The host  200  may transmit, to the storage device  100 , data on which a calculation is to be performed by the reconfigurable logic  130 . The host  200  may receive, from the storage device  100 , data generated by the calculation of the reconfigurable logic  130 . 
     The control logic  110  may reconfigure the reconfigurable logic  130  in response to the host command CMD received from the host  200 . The control logic  110  of the storage device  100  may include a command decoder  111  and a configuration controller  112 . The command decoder  111  and the configuration controller  112  may be implemented using hardware, software, or firmware. The command decoder  111  may be referred to as a command detector. The configuration controller  112  may be referred to as a design file downloader, an image downloader, or a programming circuit. 
     The command decoder  111  may receive the host command CMD and may detect a function required by the host  200  from the received host command CMD. According to an embodiment, the command decoder  111  may determine whether a design file currently programmed in the reconfigurable logic  130  corresponds to the function required by the host  200 . According to an embodiment, the command decoder  111  may determine whether a design file corresponding to the detected function has been stored in the NVM  120 . 
     The host  200  be configured to transmit, to the control logic  110  of the storage device  100 , a design file for programming the reconfigurable logic  130 . The configuration controller  112  may receive the design file corresponding to the function required by the host  200  from the host  200  and may reconfigure the reconfigurable logic  130  by downloading or programming the received design file into the reconfigurable logic  130 . The configuration controller  112  may program, in the reconfigurable logic  130 , the received design file in order to implement the function into the reconfigurable logic  130 . That is, the configuration controller  112  is configured to dynamically reconfigure the reconfigurable logic  130 , by programming, in the reconfigurable logic  130 , the design file for implementing the function into the reconfigurable logic  130 . According to an embodiment, the configuration controller  112  may receive a design file from the host  200 . According to an embodiment, the configuration controller  112  may receive a design file from the NVM  120 . 
     The reconfigurable logic  130  may operate as an accelerator corresponding to an application that is executed by the host  200 , by being reconfigured according to the host command CMD. Accordingly, the reconfigurable logic  130  may receive data from the host  200  or the NVM  120  and may perform a calculation on the received data according to the function required by the host  200 . Then, the reconfigurable logic  130  may provide a result of the calculation to the host  200  or the NVM  120 . 
     The host  200  may transmit a read request to the storage device  100 , and the storage device  100  may read data from the NVM  120  in response to the read request. The control logic  110  may control data to be written to the NVM  120  in response to a write request received from the host  200 . Alternatively, the control logic  110  may control data to be read from the NVM  120  in response to the read request received from the host  200 . 
     The NVM  120  may include a memory cell array including multiple memory cells. According to an embodiment, the NVM  120  may include a flash memory device, for example, a NAND flash memory device. However, the NVM  120  is not limited thereto, and the NVM  120  may include a resistive memory device, such as resistive random-access memory (ReRAM), phase change RAM (PRAM), or magnetic RAM (MRAM). 
     According to an embodiment, the storage device  100  may be a block storage device that manages data in units of blocks. According to an embodiment, the storage device  100  may be an object storage device that manages data in units of objects. For example, the storage device  100  may be a key-value storage device. The key-value storage device fast and simply processes data by using a key-value pair. The key-value pair is a pair of a key having uniqueness and a value, which is data corresponding to the key, and may be referred to as a tuple or a key-value tuple. In the key-value pair, the key may be expressed as an arbitrary string, such as a file name, a uniform resource identifier (URI) or a hash, and the value may be any type of data, such as an image or a user preference file or document. 
     The storage system  10  may be implemented using, for example, a personal computer (PC), a data server, a network-coupled storage, an Internet of Things (IoT) device, or a portable electronic apparatus. The portable electronic apparatus may be a laptop computer, a mobile telephone, a smartphone, a tablet PC, a personal digital assistant (PDA), an enterprise digital assistant (EDA), a digital still camera, a digital video camera, an audio player, a portable multimedia player (PMP), a personal navigation device (PND), an MP3 player, a handheld game console, an e-book, a wearable apparatus, or the like. 
     According to some embodiments, the storage device  100  may be internal memory embedded in an electronic apparatus. For example, the storage device  100  may be a solid-state drive (SSD), an embedded Universal Flash Storage (UFS) memory device, or an embedded Multi-Media Card (eMMC). According to some embodiments, the storage device  100  may be external memory detachable from an electronic apparatus. For example, the storage device  100  may be a UFS memory card, a Compact Flash (CF) card, a Secure Digital (SD) card, a Micro-SD card, a Mini-SD card, an extreme Digital (xD) card or Memory Stick. 
       FIG.  2    is a block diagram illustrating a storage device  100 ′ according to another embodiment of the present disclosure. 
     Referring to  FIG.  2   , the storage device  100 ′ may include a control logic  110 ′ and the NVM  120 . The storage device  100 ′ corresponds to a modification of the storage device  100  of  FIG.  1   , and only differences between the storage device  100 ′ and the storage device  100  of  FIG.  1    are described. 
     According to the present embodiment, the control logic  110 ′ may include the command decoder  111 , the configuration controller  112 , and a reconfigurable logic  130 ′. According to an embodiment, the control logic  110 ′ may be implemented as a first chip, for example, an ASIC chip, and the reconfigurable logic  130 ′ may be embedded into the first chip. That is, the control logic  110 ′ and the reconfigurable logic  130 ′ may be implemented in a single chip. According to an embodiment, the control logic  110 ′ may be implemented using an FPGA. Various embodiments to be described below are applicable to the storage device  100  of  FIG.  1    and the storage device  100 ′ of  FIG.  2   . 
       FIG.  3    is a flowchart illustrating a method of operating a storage device, according to an embodiment of the present disclosure. 
     Referring to  FIG.  3   , the method of operating a storage device, according to the present embodiment, may be a method of reconfiguring a reconfigurable logic included in the storage device, and may include, for example, operations that are sequentially performed in the storage device  100  of  FIG.  1   . This will now be described in greater detail with reference to  FIGS.  1  and  3   . 
     In operation S 110 , the storage device  100  receives the host command CMD including the information about the function required by the host  200 . Operation S 110  may be performed during an operation of the storage device  100 , in other words, during runtime. However, operation S 110  is not limited thereto, and operation S 110  may be performed at a time point when the storage device  100  is supplied with power or at a time point when the storage device  100  is reset. 
     In operation S 130 , the storage device  100  dynamically reconfigures the reconfigurable logic  130  by downloading a design file into the reconfigurable logic  130 . As such, a trigger condition for reconfiguring the reconfigurable logic  130  is the host command CMD provided by the host  200 , and the reconfigurable logic  130  may be reconfigured according to the host command CMD to perform a function corresponding to an application that is executed by the host  200 . 
     In the related art, an FPGA image is programmed to an FPGA only at the moment when a system is supplied with power or reset. In other words, a trigger condition for FPGA reconfiguration is power supply or resetting, and a condition for re-programming or re-downloading an FPGA image into an FPGA is very limited. Accordingly, a very large and expensive FPGA is used to pre-program all functions required by a host to the FPGA. 
     However, according to the present embodiment, the storage device  100  may receive the host command CMD while the storage device  100  is operating, and may reconfigure the reconfigurable logic  130  in real time according to the host command CMD. Accordingly, all functions required by the host  200  do not need to be previously programmed to the reconfigurable logic  130 , and a function currently required by the host  200  may be re-programmed to the reconfigurable logic  130  in real time. Thus, hardware resources for implementing the reconfigurable logic  130  may be reduced, and power consumption, an implementation area, and implementation costs associated with the reconfigurable logic  130  may be lowered. 
       FIG.  4    is a block diagram illustrating an example in which the reconfigurable logic  130  included in the storage device  100  of  FIG.  1    is reconfigured to a first accelerator  130   a.    
     Referring to  FIG.  4   , when the first application APP1  210   a  is executed, the reconfiguration decider  220  may decide reconfiguration of the reconfigurable logic  130  so that the reconfigurable logic  130  may perform a function corresponding to the first application APP1  210   a . Accordingly, the reconfigurable logic  130  may be reconfigured to the first accelerator  130   a  for the first application APP1  210   a.    
     For example, the first application APP1  210   a  may be a voice or image recognition application, and the first accelerator  130   a  may perform a CNN necessary for voice or image recognition. As noted previously, the storage device  100  may include a control logic  110 , and the control logic  110  may include a configuration controller  112 . According to an embodiment, the host  200  may provide the storage device  100  with a first design file for reconfiguring the reconfigurable logic  130  to the first accelerator  130   a . That is, the host  200  may be configured to transmit, to the storage device  100 , the first design file for programming the reconfigurable logic  130  into the first accelerator  130   a . The configuration controller  112  of the control logic  110  of the storage device  100  may be configured to dynamically reconfigure the reconfigurable logic  130 , by programming, in the reconfigurable logic  130 , the first design file for programming the reconfigurable logic into the first accelerator  130   a  according to a first host command. 
       FIG.  5    is a block diagram illustrating an example in which the reconfigurable logic  130  included in the storage device  100  of  FIG.  1    is reconfigured to a second accelerator  130   b.    
     Referring to  FIG.  5   , when the second application APP2  210   b  is executed, the reconfiguration decider  220  may decide reconfiguration of the reconfigurable logic  130  so that the reconfigurable logic  130  may perform a function corresponding to the second application APP2  210   b . Accordingly, the reconfigurable logic  130  may be reconfigured to the second accelerator  130   b  with respect to the second application APP2  210   b.    
     For example, the second application APP2  210   b  may be a multimedia reproducing application, and the second accelerator  130   b  may perform transcoding necessary for multimedia reproduction. The transcoding means an operation of converting a file format, a resolution, and an image quality of multimedia content. According to an embodiment, the host  200  may provide the storage device  100  with a second design file for reconfiguring the reconfigurable logic  130  to the second accelerator  130   b . That is, the host  200  may be configured to transmit, to the storage device  100 , the second design file for programming the reconfigurable logic  130  into the second accelerator  130   b.    
       FIG.  6    is a flowchart illustrating an operation between the host  200 , the control logic  110 , and the reconfigurable logic  130 , according to an embodiment of the present disclosure. 
     Referring to  FIG.  6   , the operation between the host  200 , the control logic  110 , and the reconfigurable logic  130  corresponds to the embodiments of  FIGS.  4  and  5   . In operation S 200 , the host  200  decides that the reconfigurable logic  130  is reconfigured to the first accelerator  130   a  for the first application APP1  210   a  and generates the host command CMD. For example, the first application APP1  210   a  may be a multimedia reproducing application, and the host command CMD may include a transcoding request. In operation S 205 , the host  200  transmits the host command CMD to the control logic  110 . 
     In operation S 210 , the control logic  110  detects the host command CMD and controls the reconfigurable logic  130  to be reconfigured. For example, the command decoder  111  may detect the transcoding request from the host command CMD. According to an embodiment, the command decoder  111  may determine whether a first design file corresponding to the transcoding request has been programmed in the reconfigurable logic  130 . According to an embodiment, the command decoder  111  may determine whether the first design file corresponding to the transcoding request has been stored in a memory included in the storage device  100 . 
     In operation S 220 , the control logic  110  transmits a first design file corresponding to the first application APP1  210   a  to the reconfigurable logic  130 . In operation S 230 , the reconfigurable logic  130  is configured to have a function corresponding to the first application APP1  210   a , by downloading the first design file. Accordingly, the reconfigurable logic  130  may be implemented using the first accelerator  130   a . For example, the reconfigurable logic  130  may perform transcoding corresponding to the multimedia reproducing application by downloading a first design file corresponding to transcoding. In operation S 240 , the reconfigurable logic  130  transmits a response message indicating reconfiguration completion to the control logic  110 . In operation S 245 , the control logic  110  transmits the response message indicating reconfiguration completion to the host  200 . 
     In operation S 250 , the host  200  decides that the reconfigurable logic  130  is reconfigured to the second accelerator  130   b  for the second application APP2  210   b  and generates the host command CMD. For example, the second application APP2  210   b  may be a voice recognition application, and the host command CMD may include a CNN request. In operation S 255 , the host  200  transmits the host command CMD to the control logic  110 . 
     In operation S 260 , the control logic  110  detects the host command CMD and controls the reconfigurable logic  130  to be reconfigured. For example, the command decoder  111  may detect the CNN request from the host command CMD. According to an embodiment, the command decoder  111  may determine whether a second design file corresponding to the CNN request has been programmed in the reconfigurable logic  130 . According to an embodiment, the command decoder  111  may determine whether the second design file corresponding to the CNN request has been stored in the memory included in the storage device  100 . 
     In operation S 270 , the control logic  110  transmits the second design file corresponding to the second application APP2  210   b  to the reconfigurable logic  130 . In operation S 280 , the reconfigurable logic  130  is configured to have a function corresponding to the second application APP2  210   b , by downloading the second design file. Accordingly, the reconfigurable logic  130  may be implemented using the second accelerator  130   b . For example, the reconfigurable logic  130  may perform a CNN corresponding to a voice recognition application by downloading the second design file corresponding to a CNN. In operation S 290 , the reconfigurable logic  130  transmits a response message indicating completion of reconfiguration to the control logic  110 . In operation S 295 , the control logic  110  transmits the response message indicating completion of reconfiguration to the host  200 . 
     As described above with reference to  FIGS.  4  through  6   , according to the present embodiment, when an application executed by the host  200  is changed, the host  200  may provide a host command CMD to the storage device  100 , and the reconfigurable logic  130  may be changed from the first accelerator  130   a  to the second accelerator  130   b  according to the host command CMD. However, the inventive concept(s) of the present disclosure are not limited thereto, and the reconfigurable logic  130  may be partially reconfigured according to the host command CMD. 
     The reconfigurable logic  130  may also be reconfigured to perform more calculations according to hardware resources. For example, when the reconfigurable logic  130  has sufficiently many hardware resources, the reconfigurable logic  130  may further perform a calculation corresponding to the second accelerator  130   b  according to the host command CMD while operating as the first accelerator  130   a , and, accordingly, the reconfigurable logic  130  may be reconfigured to perform calculations corresponding to the first accelerator  130   a  and the second accelerator  130   b.    
       FIG.  7    is a block diagram illustrating a storage device  100   a , which is an example of a storage device according to an embodiment of the present disclosure. 
     Referring to  FIG.  7   , the storage device  100   a  may include a control logic  110   a , the reconfigurable logic  130 , and a memory MEM. The control logic  110   a  may include the command decoder  111 , the configuration controller  112 , a memory controller  113 , and a buffer  114 . The storage device  100   a  corresponds to a modification of the storage device  100  of  FIG.  1   , and redundant descriptions thereof will now be omitted. 
     The command decoder  111  may receive the host command CMD and may decode the received host command CMD to thereby detect information about a function required by the host  200 . According to an embodiment, the command decoder  111  may determine whether a design file currently programmed in the reconfigurable logic  130  corresponds to the function required by the host  200 . The command decoder  111  may load a design file received from the host  200  to the buffer  114 . 
     According to an embodiment, the command decoder  111  may determine whether a design file corresponding to the detected information has been stored in the memory MEM, by referring to a mapping table. When it is determined that the design file has been stored in the memory MEM, the command decoder  111  may output a control signal instructing a control operation of the memory controller  113 . On the other hand, when it is determined that the design file has not been stored in the memory MEM, the command decoder  111  may transmit a response message to the host  200 . 
     The memory controller  113  may receive the control signal from the command decoder  111  and may control a read operation with respect to the memory MEM in response to the received control signal. That is, the memory controller  113  may be configured to control the read operation for reading the design file from the NVM  120 . The memory controller  113  may provide the read design file to the configuration controller via the buffer  114 . In detail, the memory controller  113  may transmit a read command to the memory MEM. The memory MEM may store a design file DF for reconfiguring the reconfigurable logic  130 . According to an embodiment, the memory MEM may be the NVM  120  of  FIG.  1   . According to an embodiment, the memory MEM may be, for example, volatile memory such as DRAM. The memory MEM may output the design file DF by performing a read operation in response to the read command. The memory controller  113  may receive the design file DF from the memory MEM and may load the received design file DF into the buffer  114 . 
     The buffer  114  may buffer the design file DF received from the host  200  or the memory MEM and may provide the buffered design file DF to the configuration controller  112 . For example, the buffer  114  may be Static Random-Access Memory (SRAM) or a First In First Out (FIFO) buffer. For example, the buffer  114  may be implemented using volatile memory, such as DRAM, or non-volatile memory, such as PRAM or flash memory. According to an embodiment, when an operating speed of the memory controller  113  is greater than that of the configuration controller  112 , the memory controller  113  may buffer the design file DF in the buffer  114 . According to an embodiment, the memory controller  113  may provide the design file DF directly to the configuration controller  112 , rather than via the buffer  114 . 
     The configuration controller  112  may download or program the design file DF into the reconfigurable logic  130 . Although the configuration controller  112  is illustrated as being included in the control logic  110   a , the configuration controller  112  is not limited thereto. According to some embodiments, the configuration controller  112  may be implemented to be included in the reconfigurable logic  130 , for example, may be implemented in an FPGA. 
       FIG.  8    is a block diagram illustrating a storage device  100   b , which is another example of a storage device according to an embodiment of the present disclosure. 
     The storage device  100   b  of  FIG.  8    corresponds to a modification of the storage device  100   a  of  FIG.  7   , and only differences between the storage device  100   b  and the storage device  100   a  of  FIG.  7    are described. The storage device  100   b  may further include a buffer  131  and a data sync up logic  132 , in addition to the components of the storage device  100   a  of  FIG.  7   . The buffer  131  may be a dedicated buffer of the reconfigurable logic  130  and may buffer a result of a calculation of the reconfigurable logic  130 . Because the reconfigurable logic  130  may perform a calculation at high speed, the buffer  131  may be implemented to be adjacent to the reconfigurable logic  130 , for example, may be implemented in an FPGA, thereby preventing performance degradation of the reconfigurable logic  130 . 
     The data sync up logic  132  may sync up data necessary for a calculation operation of the reconfigurable logic  130 . For example, when the reconfigurable logic  130  is configured to a first accelerator, for example, the first accelerator  130   a  of  FIG.  4   , data used in the first accelerator  130   a  may also be needed when the reconfigurable logic  130  has been reconfigured to a second accelerator, for example, the second accelerator  130   b  of  FIG.  5   . Accordingly, the data sync up logic  132  may sync up the data used in the first accelerator  130   a  with data that is to be used in the second accelerator  130   b . For example, the data sync up logic  132  may be implemented using a portion of an FPGA. For example, the data sync up logic  132  may include memory. 
       FIG.  9    is a block diagram illustrating a first data path DP 1  in a storage system  10   c  according to an embodiment of the present disclosure. 
     Referring to  FIG.  9   , a host  200   a  corresponds to a modification of the host  200  of  FIG.  1    and may further include a buffer  230  that stores the design file DF, compared with the host  200  of  FIG.  1   . The buffer  230  may buffer multiple design files respectively corresponding to applications executable by the host  200   a.    
     The host  200   a  may provide the design file DF to the storage device  100 . The design file DF may be provided to the reconfigurable logic  130  along the first data path DP 1 . In detail, the design file DF may be provided from the buffer  230  of the host  200   a  to the reconfigurable logic  130  via the configuration controller  112 . According to some embodiments, the design file DF may be provided to the reconfigurable logic  130  via a buffer (for example, the buffer  114  of  FIG.  7   ) and the configuration controller  112  within the control logic  110 . 
       FIG.  10    is a flowchart illustrating an example of an operation between the host  200   a , the control logic  110 , and the reconfigurable logic  130  of  FIG.  9   . 
     Referring to  FIG.  10   , the host  200   a  decides reconfiguration of an accelerator, namely, the reconfigurable logic  130 , in operation S 300 . For example, the reconfiguration decider  220  may decide reconfiguration of the reconfigurable logic  130  according to the type of application that is executed by the host  200   a . In operation S 310 , the host  200   a  generates a host command CMD including information about a function required by the host  200   a , information about an application executed by the host  200   a , or information about a design file corresponding to the application executed by the host  200   a . In operation S 320 , the host  200   a  transmits the host command CMD to the control logic  110 . In operation S 330 , the control logic  110  detects the information about the function required by the host  200   a  from the host command CMD and transmits a response message to the host  200   a.    
     According to an embodiment, the control logic  110  may determine whether the detected function has been programmed in the reconfigurable logic  130 . According to an embodiment, the control logic  110  may include a table that stores a design file currently programmed in the reconfigurable logic  130 . The control logic  110  may detect, from the table, the design file currently programmed in the reconfigurable logic  130 . Then, the control logic  110  may determine whether the detected design file corresponds to the function detected from the host command CMD. When it is determined that the detected design file corresponds to the function detected from the host command CMD, the control logic  110  may transmit, to the host  200   a , a response message indicating that the function required by the host  200   a  has been implemented in the reconfigurable logic  130 , in operation S 335 . On the other hand, when it is determined that the detected design file does not correspond to the function detected from the host command CMD, the control logic  110  may transmit, to the host  200   a , a response message requesting the host  200   a  to transmit a design file, in operation S 335 . 
     According to an embodiment, the control logic  110  may determine whether the design file corresponding to the detected function has been stored in the storage device  100 , by referring to a mapping table. When it is determined that the design file has not been stored in the storage device  100 , the control logic  110  may transmit, to the host  200   a , a response message requesting the host  200   a  to transmit a design file, in operation S 335 . However, the inventive concept(s) of the present disclosure are not limited thereto. In operation S 335 , the control logic  110  may simply transmit a response message including only a result of the determination to the host  200   a.    
     According to an embodiment, the control logic  110  may not determine whether the design file has been stored in the storage device  100 . When decoding of the host command CMD is completed, the control logic  110  may transmit, to the host  200   a , a response message requesting the host  200   a  to transmit a design file, in operation S 335 . However, the control logic  110  is not limited thereto. In operation S 335 , the control logic  110  may transmit, to the host  200   a , a response message indicating that decoding of the host command CMD has been completed, in operation S 335 . 
     In operation S 340 , the host  200   a  transmits a design file to the control logic  110 . In operation S 350 , the control logic  110  controls reconfiguration with respect to the reconfigurable logic  130 , based on the design file. In operation S 360 , the control logic  110  transmits the design file to the reconfigurable logic  130 . In operation S 370 , the reconfigurable logic  130  may be reconfigured to a component corresponding to the design file, by downloading the design file. In operation S 380 , the reconfigurable logic  130  transmits, to the control logic  110 , a response message indicating that the reconfiguration has been completed. In operation S 390 , the control logic  110  transmits, to the host  200   a , the response message indicating that the reconfiguration has been completed. 
       FIG.  11    is a flowchart illustrating another example of an operation between the host  200   a , the control logic  110 , and the reconfigurable logic  130  of  FIG.  9   . 
     Referring to  FIG.  11   , the host  200   a  decides reconfiguration of an accelerator, namely, the reconfigurable logic  130 , in operation S 400 . In operation S 410 , the host  200   a  generates a host command CMD including information about a function required by the host  200   a  and a design file corresponding to the function. In operation S 420 , the host  200   a  transmits the host command CMD including the design file to the control logic  110 . 
     In operation S 430 , the control logic  110  receives the host command CMD and detects the information about the function required by the host  200   a  from the received host command CMD. The control logic  110  may buffer the design file in a buffer (for example, the buffer  114  of  FIG.  7   ). In operation S 440 , the control logic  110  controls reconfiguration with respect to the reconfigurable logic  130 , based on the design file. In operation S 450 , the control logic  110  transmits the design file to the reconfigurable logic  130 . In operation S 460 , the reconfigurable logic  130  may be reconfigured to a component corresponding to the design file, by downloading the design file. In operation S 470 , the reconfigurable logic  130  transmits, to the control logic  110 , a response message indicating that the reconfiguration has been completed. In operation S 480 , the control logic  110  transmits, to the host  200   a , the response message indicating that the reconfiguration has been completed. 
       FIG.  12    is a block diagram illustrating a second data path DP 2  in a storage system  10   d  according to an embodiment of the present disclosure. 
     Referring to  FIG.  12   , the NVM  120  may store a design file DF. The host  200  may previously transmit multiple design files to the storage device  100 , in order to reconfigure the reconfigurable logic  130  in real time. Accordingly, the NVM  120  may store multiple design files respectively corresponding to applications executable by the host  200 . 
     The design file DF may be provided to the reconfigurable logic  130  along the second data path DP 2 . In detail, the design file DF may be provided from the NVM  120  to the reconfigurable logic  130  via the configuration controller  112 . According to some embodiments, the design file DF may be provided to the reconfigurable logic  130  via a buffer (for example, the buffer  114  of  FIG.  7   ) and the configuration controller  112  within the control logic  110 . 
       FIG.  13    is a flowchart illustrating an example of an operation between the host  200 , the control logic  110 , the NVM  120 , and the reconfigurable logic  130  of  FIG.  12   . 
     Referring to  FIG.  13   , the host  200  decides reconfiguration of an accelerator, namely, the reconfigurable logic  130 , and transmits a host command CMD including information about a function required by the host  200  to the control logic  110 , in operation S 500 . In operation S 510 , the control logic  110  detects the information about the function required by the host  200  from the received host command CMD. 
     In operation S 520 , the control logic  110  determines whether a design file DF corresponding to the detected function has been stored in the NVM  120 , by referring to a mapping table. When it is determined that the design file DF has not been stored in the NVM  120 , the control logic  110  transmits a response message to the host  200 , in operation S 530 . According to an embodiment, operations S 340  through S 390  of  FIG.  10    may be performed after operation S 530 . 
     On the other hand, when it is determined that the design file DF has been stored in the NVM  120 , the control logic  110  transmits a read command to the NVM  120 , in operation S 540 . The NVM  120  performs a read operation in response to the read command, in operation S 550 , and transmits the design file DF to the control logic  110 , in operation S 555 . In operation S 560 , the control logic  110  controls reconfiguration with respect to the reconfigurable logic  130 , based on the design file DF. 
     In operation S 570 , the control logic  110  transmits the design file DF to the reconfigurable logic  130 . In operation S 580 , the reconfigurable logic  130  may be reconfigured to a component corresponding to the design file DF, by downloading the design file DF. In operation S 590 , the reconfigurable logic  130  transmits, to the control logic  110 , a response message indicating that the reconfiguration has been completed. In operation S 595 , the control logic  110  transmits, to the host  200 , the response message indicating that the reconfiguration has been completed. 
       FIG.  14    is a block diagram illustrating a third data path DP 3  in a storage system  10   e  according to an embodiment of the present disclosure. 
     Referring to  FIG.  14   , a storage device  100   c  corresponds to a modification of the storage device  100  of  FIG.  1    and may further include VM  140  (volatile memory), compared with the storage device  100  of  FIG.  1   . The VM  140  may store a design file DF. The host  200  may previously transmit multiple design files to the storage device  100   c , in order to reconfigure the reconfigurable logic  130  in real time. Accordingly, the VM  140  may store multiple design files respectively corresponding to applications executable by the host  200 . 
     The design file DF may be provided to the reconfigurable logic  130  along the third data path DP 3 . In detail, the design file DF may be provided from the VM  140  to the reconfigurable logic  130  via the configuration controller  112 . According to some embodiments, the design file DF may be provided to the reconfigurable logic  130  via a buffer (for example, the buffer  114  of  FIG.  7   ) and the configuration controller  112  in the control logic  110 . 
       FIG.  15    is a block diagram illustrating various data paths in a storage system  10   f  according to an embodiment of the present disclosure. 
     Referring to  FIG.  15   , a control logic  110   b  may include the command decoder  111 , the configuration controller  112 , the buffer  114 , a processor  115 , a mapping table  116 , a host interface (IF)  117 , and an NVM IF  118 , which communicate with each other via a bus  119 . The control logic  110   b  may correspond to a modification of the control logic  110   a  of  FIG.  8   , and repeated descriptions thereof will be omitted. 
     The processor  115  may include a central processing unit or a micro-processor. Additionally, the processor may control an overall operation of the control logic  110   b . According to an embodiment, the processor  115  may be implemented using a multi-core processor, for example, a dual core processor or a quad core processor. 
     The mapping table  116  may store physical addresses at which multiple design files have been written. According to an embodiment, the mapping table  116  may store physical addresses of the NVM  120  at which design files have been written. This will be described in greater detail below with reference to  FIG.  16 A . According to an embodiment, the mapping table  116  may store physical addresses of VM (for example, the VM  140  of  FIG.  14   ) at which design files have been written. This will be described in greater detail below with reference to  FIG.  16 B . The mapping table  116  may be loaded into memory. 
     The host IF  117  may provide an IF between the host  200  and the control logic  110   b , for example, a Universal Serial Bus (USB), an MMC, PCIExpress (PCI-E), AT Attachment (ATA), Serial AT Attachment (SATA), Parallel AT Attachment (PATA), a Small Computer System Interface (SCSI), a Serial Attached SCSI (SAS), an Enhanced Small Disk Interface (ESDI), and an IF based on Integrated Drive Electronics (IDE) or the like. 
     The NVM IF  118  may provide an IF between the control logic  110   b  and the NVM  120 . According to an embodiment, the memory controller  113  of  FIG.  8    may be implemented in the NVM IF  118 . For example, a read command, a write command, or data may be transmitted or received between the control logic  110   b  and the NVM  120  via the NVM IF  118 . According to an embodiment, a number of NVM IFs may correspond to the number of channels between the control logic  110   b  and the NVM  120 . 
     According to an embodiment, the host IF  117  may receive a design file from the host  200  and provide the received design file to the configuration controller  112 , and the configuration controller  112  may program the design file into the reconfigurable logic  130 . According to an embodiment, the buffer  114  may provide a design file to the configuration controller  112 , and the configuration controller  112  may program the design file into the reconfigurable logic  130 . According to an embodiment, the NVM IF  118  may receive a design file from the NVM  120  and provide the received design file to the configuration controller  112 , and the configuration controller  112  may program the design file into the reconfigurable logic  130 . 
       FIG.  16 A  illustrates a mapping table  116   a  for non-volatile memory NVM according to an embodiment of the present disclosure. 
     Referring to  FIG.  16 A , the mapping table  116   a  may store physical addresses at which first through third design files DF 1   a , DF 2   a , and DF 3   a  have been stored. For example, the mapping table  116   a  may be stored in the control logic  110  of  FIG.  12   . For example, according to the mapping table  116   a , the first design file DF 1   a  may be stored at a first physical address PPN 1   a  of NVM (for example, the NVM  120  of  FIG.  12   ), the second design file DF 2   a  may be stored at a second physical address PPN 2   a  of the NVM, and the third design file DF 3   a  may be stored at a third physical address PPN 3   a  of the NVM. 
       FIG.  16 B  illustrates a mapping table  116   b  for volatile memory VM according to an embodiment of the present disclosure. 
     Referring to  FIG.  16 B , the mapping table  116   b  may store physical addresses at which first through third design files DF 1   b , DF 2   b , and DF 3   b  have been stored. For example, the mapping table  116   b  may be stored in the control logic  110  of  FIG.  14   . For example, according to the mapping table  116   b , the first design file DF 1   b  may be stored at a first physical address PPN 1   b  of VM, the second design file DF 2   b  may be stored at a second physical address PPN 2   b  of the VM, and the third the design file DF 3   b  may be stored at a third physical address PPN 3   b  of the VM. 
       FIG.  17    is a block diagram illustrating a storage system  10   g  according to an embodiment of the present disclosure. 
     Referring to  FIG.  17   , the storage system  10   g  may include a storage device  100   d , the host  200 , and a HW accelerator  300  (hardware accelerator), which may communicate with each other via a bus  400 . For example, the storage system  10   g  may be a server or a data center. The storage device  100   d  may include a storage ST and a reconfigurable accelerator RA. As such, the storage system  10   g  may include both the HW accelerator  300  and the reconfigurable accelerator RA. In this case, the reconfigurable accelerator RA may be implemented within the storage device  100   d.    
     The HW accelerator  300  may help a calculation of the host  200  by performing a pre-determined calculation from among calculations that are performed by the host  200 . For example, the HW accelerator  300  may be a graphics processing unit (GPU). The reconfigurable accelerator RA may perform a calculation corresponding to an application that is currently executed by the host  200 , by being reconfigured in real time according to the type of calculation performed by the host  200 . As such, a calculation performed by the HW accelerator  300  is not changed during an operation of the storage system  10   g , whereas a calculation performed by the reconfigurable accelerator RA may be changed during an operation of the storage system  10   g.    
     According to the present embodiment, the storage device  100   d  may function as an existing storage device by including the storage ST, and the storage device  100   d  may also function as an accelerator for helping a calculation of the host  200 , by further including the reconfigurable accelerator RA. In this case, due to the inclusion of the storage ST and the reconfigurable accelerator RA within the storage device  100   d , a data processing speed between the storage ST and the reconfigurable accelerator RA may be increased. 
       FIG.  18    is a block diagram illustrating a network system  1000  according to an embodiment of the present disclosure. 
     Referring to  FIG.  18   , the network system  1000  may include a server system  1100 , and multiple terminals  1210  through  1230  communicating with the server system  1100  via a network NET. The server system  1100  may include a server  1110  and an SSD  1120 . The SSD  1120  may correspond to the storage devices  100 ,  100 ′,  100   a ,  100   b ,  100   c , and  100   d  according to the above-described embodiments. According to some embodiments, the SSD  1120  may be implemented using the embodiments described above with reference to  FIGS.  1  through  17   . 
       FIG.  19    is a block diagram illustrating a network system  2000  according to an embodiment of the present disclosure. 
     Referring to  FIG.  19   , the network system  2000  may include a client group  2100  and a data center  2200 . The client group  2100  may include client devices C that communicate with the data center  2200  via a first network NET 1 , for example, the Internet. The data center  2200  is a facility that collects various types of data and provides a service, and may include an application server group  2210 , a DB server group  2220  (database server group), and an object cache server group  2230  that communicate with each other via a second network NET 2 , for example, a local area network (LAN) or Intranet. 
     The application server group  2210  may include application server devices AS, and the application server devices AS may process requests received from the client group  2100  and may access the DB server group  2220  or the object cache server group  2230  according to the requests of the client group  2100 . The DB server group  2220  may include DB server devices DS that store pieces of data processed by the application server devices AS. The object cache server group  2230  may include object cache server devices OCS that temporarily store the data stored in the DB server devices DS or data read from the DB server devices DS, and accordingly, may function as a cache between the application server devices AS and the DB server devices DS. According to an embodiment, the DB server devices DS may be implemented using the embodiments described above with reference to  FIGS.  1  through  17   . 
     While the inventive concept(s) of the present disclosure have been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope as defined by the following claims.