Patent Publication Number: US-11393875-B2

Title: Semiconductor device and method for manufacturing the same

Description:
BACKGROUND OF THE INVENTION 
     Field of the Invention 
     The invention relates in general to a semiconductor device, and more particularly to a three-dimensional semiconductor device. 
     Description of the Related Art 
     Recently, as the demand for more excellent memory elements has gradually increased, various three-dimensional (3D) memory devices have been provided. Generally speaking, the 3D memory device includes a memory array area composed of a plurality of memory cells. However, the current memory array area still has a problem of current leakage, which prevents the 3D memory element from performing its normal operation. Therefore, there is a need to propose an improved three-dimensional memory device and its manufacturing method to solve the problems faced by the conventional technology. 
     SUMMARY OF THE INVENTION 
     The present invention relates to a semiconductor device. Since the semiconductor device of the present application includes a salicide layer, the salicide layer can form a Schottky diode with the conductive layer, and the Schottky diode can be used as a selector so that the selector is electrically connected to the conductive layer and the memory layer, and can provide rectifier property in the memory array. The Schottky diode (selector) can perform unipolar operation on the memory to avoid reverse current conditions, so the sneak path in the memory array can be eliminated, and the problem of current leakage faced by the conventional technique can be solved. 
     According to one embodiment, a semiconductor device is provided. The semiconductor device includes a substrate, a stack, a conductive pillar, a memory layer, and a salicide layer. The stack is disposed on the substrate, wherein the stack includes a plurality of insulating layers and a plurality of conductive layers that are alternately stacked along a first direction. The conductive pillar penetrates the stack along the first direction. The memory layer surrounds the conductive pillar. The salicide layer surrounds the conductive pillar, wherein the memory layer is disposed between the conductive pillar and the salicide layer. 
     According to another embodiment, a method for manufacturing a semiconductor device is provided. The method includes the following steps. Firstly, a substrate is provided. Then, a stack is formed on the substrate. The stack includes a plurality of insulating layers and a plurality of conductive layers that are alternately stacked along a first direction. A conductive pillar is formed, wherein the conductive pillar penetrates the stack along the first direction. A memory layer is formed, wherein the memory layer surrounds the conductive pillar. Thereafter, a salicide layer is formed, wherein the salicide layer surrounds the conductive pillar; wherein the memory layer is disposed between the conductive pillar and the salicide layer. 
     The above and other aspects of the invention will become better understood with regard to the following detailed description of the preferred but non-limiting embodiment(s). The following description is made with reference to the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1A  is a partial top view of a semiconductor device according to an embodiment of the present invention; 
         FIG. 1B  shows a cross-sectional view taken along the line A-A′ of  FIG. 1A ; 
         FIGS. 2A ˜ 2 H illustrate a manufacturing flow chart of a semiconductor device according to an embodiment of the present invention; 
         FIG. 2I  illustrates another embodiment of the step in  FIG. 2F ; 
         FIG. 3A  is a partial top view of a semiconductor device according to an embodiment of the present invention; 
         FIG. 3B  shows a cross-sectional view taken along the line A-A′ of  FIG. 3A ; 
         FIGS. 4A-4B  illustrate a manufacturing flowchart of a semiconductor device according to an embodiment of the present invention; 
         FIG. 5  is a cross-sectional view of a semiconductor device according to an embodiment of the present invention; and 
         FIG. 6  shows an equivalent circuit diagram of a semiconductor device according to an embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       FIG. 1A  illustrates a partial top view of a semiconductor device  10  according to an embodiment of the present invention.  FIG. 1B  shows a cross-sectional view taken along the line A-A′ of  FIG. 1A .  FIG. 1A  shows a cross section corresponding to the line B-B′ in  FIG. 1B . 
     Referring to  FIGS. 1A and 1B , the semiconductor device  10  includes a substrate  110 , a stack S 1 , a plurality of conductive pillars  120 , a plurality of memory layers  122 , and a plurality of salicide layers  124 . The stack S 1  is disposed on an upper surface  110   a  of the substrate  110 , wherein the stack S 1  includes a plurality of insulating layers  112  and a plurality of conductive layers  114  that are alternately stacked along a first direction (for example, the Z direction). In the present embodiment, the thickness of the lowest insulating layer  112  is greater than the thickness of other insulating layers  112 , but the invention is not limited thereto. In the present embodiment, only five insulating layers  112  and four conductive layers  114  are illustrated, but the amount of insulating layers  112  and conductive layers  114  is not limited thereto. 
     The conductive pillar  120  penetrates the stack S 1  along the first direction. There may be a gap between the bottom of the conductive pillar  120  and the upper surface  110   a  of the substrate  100 . The memory layers  122  respectively surround the conductive pillars  120 . The salicide layers  124  surround the conductive pillar  120 , and the memory layers  122  are disposed between the conductive pillar  120  and the salicide layer  124 . The trench p 3  penetrates the stack S 1  and extends along a second direction (for example, the X direction), dividing the stack S 1  into a plurality of sub-stacks SS 1 , SS 2  . . . In some embodiments, a plurality of bit lines BL may extend along a third direction (for example, the Y direction), and the conductive pillars  120  may be electrically connected to the corresponding bit lines BL, respectively. 
     In one embodiment, the substrate  110  and the insulating layer  112  may be formed of oxide, such as silicon dioxide. 
     In one embodiment, the conductive layer  114  may be formed of a semiconductor material, such as doped or undoped polysilicon; in particular, it may be p-type or n-type doped polysilicon. In one embodiment, the conductive layer  114  can serve as a word line. 
     In one embodiment, the material of the conductive pillar  120  is, for example, polysilicon, amorphous silicon, tungsten (W), cobalt (Co), aluminum (Al), tungsten silicide (WSi X ), cobalt silicide (CoSi X ) or other suitable materials. The cross points between the conductive pillar  120  and each of the memory layers  122  may form a memory cell; a plurality of memory cells arranged along the conductive pillar  120  may form a memory string; and a plurality of memory strings may form a memory array. 
     In one embodiment, the memory layer  122  includes a resistive memory material, such as a variable resistance random access memory material or a phase change memory material. When the memory layer  122  includes a variable resistance random access memory material, the material of the memory layer  122  is, for example, titanium silicon oxide (TiSi X O Y ) or other suitable variable resistance random access memory material, in order to form a variable resistance random access memory cell at the cross points of the conductive pillar  120  and each of the memory layers  122 . When the memory layer  122  includes a phase change memory material, the material of the memory layer  122  is, for example, germanium antimony tellurium (Ge2Sb2Te5 (GST)) or other suitable phase change memory materials, so that phase change memories are formed between the conductive pillar  120  and each of the memory layers  122 . In the embodiment, the plurality of memory layers  122  are separated from each other by the insulating layers  112 , for example, discontinuously surrounding the conductive pillar  120  in the first direction, but the invention is not limited thereto. 
     In one embodiment, the material of the salicide layer  124  is, for example, titanium silicide (TiSi X ), cobalt silicide (CoSi X ) or other suitable salicide. In one embodiment, the salicide layer  124  and each corresponding conductive layer  114  form a Schottky diode, and the Schottky diode can be used as a selector. Since the salicide layer  124  of the present application can form a Schottky diode with the conductive layer  114 , and the Schottky diode can be used as a selector, so that the selector is electrically connected to the conductive layer  114  and the memory layer  122 , so it can provide the rectifier property in the memory array. The Schottky diode (selector) can perform unipolar operation on the memory to avoid reverse current, so the sneak path in the memory array can be reduced or eliminated, and the problem of current leakage faced by the conventional technique can be solved. In addition, Schottky diodes have very fast switching speeds for the memory operations. 
       FIGS. 2A to 2H  illustrate a manufacturing flowchart of a semiconductor device  10  according to an embodiment of the present invention, for example, corresponding to the position of the cross section taken along the line A-A′ in  FIG. 1A . 
     Referring to  FIG. 2A , a substrate  110  is provided, and a stack S 1  is formed on the substrate  110  (for example, on the upper surface  110   a  of the substrate  110 ). The stack S 1  includes a plurality of insulating layers  112  and a plurality of conductive layers  114  that are alternately stacked along a first direction (for example, the Z direction). In the present embodiment, the thickness of the lowest insulating layer  112  is greater than the thickness of other insulating layers  112 , but the invention is not limited thereto. In one embodiment, the substrate  110  and the insulating layer  112  may be formed of oxide, such as silicon dioxide. The conductive layers  114  can be formed of a semiconductor material, such as doped or undoped polysilicon; in particular, it can be p-type or n-type doped polysilicon. 
     Referring to  FIG. 2B , vertical openings p 1  are formed, and the vertical openings p 1  the stack S 1 , and the bottom of the vertical openings p 1  can be stopped in the lowest insulating layer  112  without exposing the upper surface  110   a  of the substrate  110 . In other words, the bottom of the vertical opening p 1  may have a gap with the substrate  110 . 
     Referring to  FIG. 2C , portions of the conductive layers  114  are removed through the vertical opening p 1 , to form a plurality of first lateral openings p 2 , wherein the first lateral openings p 2  communicate with the vertical opening p 1 . 
     Referring to  FIG. 2D , a metal layer  116  is deposited along the sidewalls of the vertical opening p 1  and the first lateral openings p 2  (for example, by a chemical vapor deposition (CVD)). The material of the metal layer  116  is, for example, titanium (Ti), cobalt (Co), or other suitable metals. 
     Thereafter, referring to  FIG. 2E , a rapid thermal annealing (RTA) process is performed to form a salicide layer  124  on contact surfaces between the metal layer  116  and each of the conductive layers  114 . The material of the salicide layer  124  is, for example, titanium silicide (TiSi X ), cobalt silicide (CoSi X ) or other suitable metal silicide. In some embodiments, the rapid thermal annealing process may be performed twice, but the invention is not limited thereto. 
     Referring to  FIG. 2F , after the salicide layer  124  is formed, the metal layer  116  is removed by a selective etching process, such as a wet etching process. 
     Referring to  FIG. 2G , after removing the metal layer  116 , an oxidation process is performed to form the memory layers  122  between the vertical opening p 1  and the salicide layers  124 ; alternatively, a deposition process (such as chemical vapor deposition process) can be performed, so that the memory material is deposited in the space between the vertical opening p 1  and the salicide layers  124  to form the memory layers  122  between the vertical opening p 1  and the salicide layers  124 . In one embodiment, when the memory layers  122  are formed by an oxidation process, the memory layers  122  includes a resistive random-access memory material, wherein the memory layers  122  may be oxides of the salicide layers  124 . For example, when the salicide layers  124  include titanium silicide (TiSi X ), the memory layers  122  may include titanium silicon oxide (TiSi X O Y ). In another embodiment, when the memory layers  122  are formed by a deposition process, the memory layers  122  include a phase change memory material. The material of the memory layers  122  are, for example, Ge2Sb2Te5 (GST) or other suitable phases change memory materials. In some embodiments, an etching process may be performed after the memory layers  122  are formed, to remove excess memory material. 
     Referring to  FIG. 2H , after forming the memory layers  122 , a conductive material is filled in the vertical openings p 1  to form the conductive pillars  120 . The material of the conductive pillars  120  are, for example, platinum (Pt), tungsten (W), cobalt (Co), aluminum (Al), tungsten silicide (WSi X ), cobalt silicide (CoSi X ), or other suitable materials. 
     After forming the conductive pillars  120 , a trench p 3  penetrating the stack S 1  and extending along a second direction (for example, the X direction) is formed, where the second direction and the first direction are intersected with each other, and the trench p 3  divide the stack S 1  into two sub-stacks SS 1  and SS 2  to form the semiconductor device  10 , as shown in  FIGS. 1A and 1B .  FIGS. 1A-1B  only exemplarily show one trench p 3  and two sub-stacks, but the invention is not limited thereto, the amount of trenches p 3  may be greater than 1, and the amount of sub-stacks may be greater than 2. 
     In some embodiments, an insulating material may be filled in the trench p 3 . 
     Optionally, after the step of forming the trench p 3 , a doping process (for example, a plasma doping process) may be further performed to the conductive layers  114 , so that each of the conductive layers  114  is doped with a dopant (for example, a p-type or n-type dopant), the dopant has a first concentration C 1  in the region adjacent to the salicide layer  124 , and has a second concentration C 2  in the region away from the salicide layer  124 , the second concentration C 2  is greater than the first concentration C 1 . In other words, the second concentration C 2  of the dopant in the conductive layer  114  adjacent to the trench p 3  is greater than the first concentration C 1  of the dopant in the conductive layer  114  away from the trench p 3 , as shown in  FIG. 1B , but the invention is not limited thereto. 
       FIG. 2I  illustrates another embodiment of the step in  FIG. 2F . 
     In some embodiments, after the step of the metal layer  116  removed by the selective etching process, a portion of the metal layer  116  is remained in the first lateral openings p 2 , as shown in  FIG. 2I . Other steps followed by  FIG. 2I  are identical or similar to the steps shown in  FIGS. 2G-2H . 
       FIG. 3A  illustrates a partial top view of a semiconductor device  20  according to an embodiment of the present invention.  FIG. 3B  shows a cross-sectional view taken along the line A-A′ of  FIG. 3A .  FIG. 3A  shows a cross section corresponding to the B-B′ line in  FIG. 3B . 
     Referring to  FIG. 3A , the semiconductor device  20  is similar to the semiconductor device  10 , the difference is in that the semiconductor device  20  further includes sidewall conductor layers  226  adjacent to the conductive layers  114 , and other identical or similar elements use the same or similar numerals, and it will not be described in detail herein. The electrical conductivity of the sidewall conductor layers  226  is greater than that of the conductive layers  114 . The sidewall conductor layers  226  are disposed on opposite sides of the trench p 3 . The sidewall conductor layers  226  between different layers are separated from each other by the insulating layers  112  (as shown in  FIG. 4C ). Compared with the semiconductor device  10 , since the semiconductor device  20  has the sidewall conductor layers  226 , which can reduce the resistance value of the conductive layers  114 , a better ohmic contact can be formed at positions adjacent to the trench p 3  in the subsequent process. 
     In the present embodiment, the conductive layers  114  may be doped with a dopant (which may be p-type or n-type), and the dopant in the conductive layers  114  has a concentration gradient distribution. For example, the dopant has a first concentration C 1  in a region adjacent to the salicide layer  124 , and has a second concentration C 2  in a region away from the salicide layer  124 , and the second concentration C 2  is greater than the first concentration C 1 . In other words, in the conductive layer  114 , the dopant (which may be p-type or n-type) has a first concentration C 1  in a region away from the trench p 3 , and a second concentration C 2  in a region adjacent to the trench p 3 , and the second concentration C 2  is greater than the first concentration C 1 , but the invention is not limited thereto. In other embodiments, the dopants in the conductive layer  114  may have the same concentration without the above-mentioned phenomenon of concentration gradient distribution. 
       FIGS. 4A-4B  illustrate a manufacturing flowchart of a semiconductor device  20  according to an embodiment of the present invention. 
     Portions of the manufacturing process of the semiconductor device  20  is similar to the manufacturing process of the semiconductor device  10 , after performing the process steps shown in  FIGS. 2A-2H , referring to  FIG. 4A , portions of the conductive layers  114  can be removed through the trench p 3 , to form a plurality of second lateral openings p 4 , wherein the second lateral openings p 4  communicate with the trench p 3 . Thereafter, a doping process (for example, a plasma doping process) is performed to the conductive layers  114 , so that each of the conductive layers  114  is doped with a dopant (for example, p-type or n-type dopant), and the dopant in a region adjacent to the salicide layer  124  has a first concentration C 1 , and the dopant in a region away from the salicide layer  124  has a second concentration C 2 , the second concentration C 2  is greater than the first concentration C 1 , that is, in the conductive layer  114 , the second concentration C 2  of the dopant (which may be p-type or n-type) in the region adjacent to the trench p 3  may be greater than the first concentration C 1  of the dopant in the region away from the trench p 3 . 
     Since the concentration of the dopant in the conductive layer  114  adjacent to the salicide layer  124  is low, it is advantageous to form a Schottky diode; the concentration of the dopant in the conductive layer  114  adjacent to the trench p 3  is high, and it is beneficial to form a better ohmic contact at a position adjacent to the trench p 3  (as shown in  FIG. 3 ) in the subsequent process. 
     Thereafter, referring to  FIG. 4B , a conductive material is filled in the second lateral openings p 4  to form a plurality of sidewall conductor layers  226 , wherein the sidewall conductor layers  226  are adjacent to the conductive layers  114 , and the electrical conductivity of the sidewall conductor layers  226  is greater than the electrical conductivity of the conductive layers  114 . The material of the sidewall conductor layers  226  is, for example, tungsten (W), cobalt (Co), aluminum (Al), tungsten silicide (WSi X ), or cobalt silicide (CoSi X ). Since the sidewall conductor layers  226  are adjacent to the conductive layers  114 , and the electrical conductivity of the sidewall conductor layers  226  is greater than the electrical conductivity of the conductive layers  114 , it is more advantageous to form a better ohmic contact at a position adjacent to the trench p 3  in the subsequent process. 
     Thereafter, portions of the sidewall conductor layers  226  may be removed by an etch-back process to form a plurality of third lateral openings p 5 . The third lateral openings p 5  may communicate with the trench p 3 , and semiconductor device  20  is formed, as shown in  FIG. 3B . In one embodiment, the outer sidewall SW 1  of the insulating layer  112  is farther away from the conductive pillar  120  than the outer sidewall SW 2  of the sidewall conductor layer  226 . 
     In some embodiments, an insulating material may be filled in the trench p 3  and the third lateral openings p 5 . 
       FIG. 5  is a cross-sectional view of a semiconductor device  30  according to an embodiment of the present invention. The semiconductor device  30  is similar to the semiconductor device  20 , except for the structure of the memory layer  322 . The same elements use the same numerals and it will not be described in detail herein. 
     Referring to  FIG. 5 , the memory layer  322  surrounds the conductive pillar  120 ; extends along the first direction and corresponds to the plurality of conductive layers  114 . For example, the memory layer  322  continuously extends between the stack S 1  and the conductive pillar  120  and has the same height as the conductive pillar  120  in the first direction. The material of the memory layer  322  is, for example, a resistive random access memory material, but the present invention is not limited thereto. The memory layer  322  may include titanium silicon oxide (TiSi X O Y ), cobalt silicide (CoSi X O Y ), or other suitable materials. Compared with the comparative example in which the memory layer does not extend along the first direction, the manufacturing process of the present embodiment is simpler. 
       FIG. 6  illustrates an equivalent circuit diagram of semiconductor devices  10  to  30  according to an embodiment of the invention. 
     Referring to  FIG. 6 , it exemplarily shows two memory strings, and two conductive pillars  120  are respectively electrically connected to the bit lines BL 1  and BL 2 , and four conductive layers  114  can be used as word lines WL 1  to WL 4 , respectively. Each of the cross points between the conductive layers  114  and the conductive pillar  120  has a schottky diode SD (for example, used as a selector) and a memory RM (for example, resistive memory) connected to each other. 
     According to one embodiment, a semiconductor device is provided. The semiconductor device includes a substrate, a stack, a conductive pillar, a memory layer, and a salicide layer. The stack is disposed on the substrate, wherein the stack includes a plurality of insulating layers and a plurality of conductive layers that are alternately stacked along a first direction. The conductive pillar penetrates the stack along the first direction. The memory layer surrounds the conductive pillar. The salicide layer surrounds the conductive pillar, wherein the memory layer is disposed between the conductive pillar and the salicide layer. 
     Since the salicide layer of the present invention can form Schottky diode with the conductive layer, and the Schottky diode can be used as a selector, so that the selector is electrically connected to the conductive layer and the memory layer, it can provide rectifier property in the memory array. The Schottky diodes (selectors) can perform unipolar operation on the memory to avoid reverse currents. Therefore, the sneak path in the memory array can be reduced or eliminated, and the problem of current leakage faced by the known technique can be solved. In addition, the Schottky diode have very fast switching speeds for memory operations. 
     While the invention has been described by way of example and in terms of the preferred embodiment(s), it is to be understood that the invention is not limited thereto. On the contrary, it is intended to cover various modifications and similar arrangements and procedures, and the scope of the appended claims therefore should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements and procedures.