Patent Publication Number: US-8972769-B2

Title: Data processing apparatus and control method for controlling clock frequency based on calculated frequency-to-response-time ratios

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a data processing apparatus and control method thereof and, more particularly, to a technique for reducing power consumption while suppressing the processing response performance of multi-core processing from lowering. 
     2. Description of the Related Art 
     As described in Japanese Patent Laid-Open No. 2006-285719, in a ring type bus connection system having a plurality of processing execution modules, the respective processing execution modules include local memories to avoid occurrence of access wait statuses to the memories. With this arrangement, data processing can be efficiently executed with small power consumption. 
     However, in the arrangement of Japanese Patent Laid-Open No. 2006-285719, when a processing response time difference is generated between the processing execution modules, a module having a shorter processing response time completes processing earlier than a module having a longer processing response time. In this case, for example, generation of a leakage current in an idle time results in wasteful power consumption. Also, in the arrangement of Japanese Patent Laid-Open No. 2006-285719, in order to attain a further power consumption reduction, the operating frequency of the overall system has to be lowered. However, when the operating frequency of the overall system is lowered, the performance of the entire system is also lowered. 
     SUMMARY OF THE INVENTION 
     The present invention has been made in consideration of the aforementioned problems, and aims to provide a technique to reduce power consumption while suppressing the multi-core processing performance of a data processing circuit from lowering. 
     According to one aspect of the present invention, a data processing apparatus includes: a plurality of processing units adapted to process data according to input operation clocks; and a control unit adapted to measure response times of the plurality of processing units when the operation clocks of a common frequency are supplied to the plurality of processing units, and to control a frequency of the operation clocks to be supplied to at least one of the plurality of processing units so that a plurality of measured response times become closer to each other. 
     According to another aspect of the present invention, a data processing apparatus in which a plurality of data processing modules which execute data processing in a pre-set order are connected in a ring shape, includes: a measurement unit adapted to measure a response time of the data processing in association with each of the plurality of data processing modules; a calculation unit adapted to calculate a frequency-to-response time ratio as a ratio of an operating frequency to the measured response time of the data processing module of interest in association with each of the plurality of data processing modules; and a control unit adapted to control the operating frequencies of the plurality of data processing modules based on the calculated frequency-to-response time ratios, wherein the control unit controls the operating frequencies of other data processing modules so that the frequency-to-response time ratios of other data processing modules become closer to the data processing modules of the data processing module corresponding to the largest measured response time of the plurality of data processing modules. 
     According to still another aspect of the present invention, a control method of a data processing apparatus in which a plurality of data processing modules which execute data processing in a pre-set order are connected in a ring shape, includes: a measurement step of controlling a measurement unit to measure a response time of the data processing in association with each of the plurality of data processing modules; a calculation step of controlling a calculation unit to calculate a frequency-to-response time ratio as a ratio of an operating frequency to the measured response time of the data processing module of interest in association with each of the plurality of data processing modules; and a control step of controlling a control unit to control the operating frequencies of the plurality of data processing modules based on the calculated frequency-to-response time ratios, wherein in the control step, the operating frequencies of other data processing modules are controlled so that the frequency-to-response time ratios of other data processing modules become closer to the data processing modules of the data processing module corresponding to the largest measured response time of the plurality of data processing modules. 
     Further features of the present invention will become apparent from the following description of exemplary embodiments (with reference to the attached drawings). 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a block diagram showing the arrangement of a data processing subsystem; 
         FIG. 2  is a flowchart showing the basic processing sequence for supplying optimized frequencies; 
         FIG. 3  is a flowchart showing the processing sequence when a hold status has occurred; and 
         FIG. 4  is a flowchart showing the processing sequence when a hold status has occurred according to the fourth embodiment. 
     
    
    
     DESCRIPTION OF THE EMBODIMENTS 
     Embodiments of the present invention will be described in detail hereinafter with reference to the accompanying drawings. 
     &lt;First Embodiment&gt; 
     (Data Processing Subsystem) 
     Basic explanations about individual components of a data processing subsystem according to this embodiment, a mutual relationship with peripheral components, and the data processing sequence will be given first.  FIG. 1  is a block diagram showing the arrangement of a data processing subsystem  1  as a data processing apparatus according to this embodiment. 
     The data processing subsystem  1  includes a communication path  10 , communication processors  101 ,  102 ,  103 , and  104 , data processors (data processing modules)  111  to  114 , response time measuring units  121  to  124 , and response time controller  131 . As shown in  FIG. 1 , in the data processing subsystem  1 , the plurality of data processors for executing data processing in a pre-set order are connected to the communication processors  101  to  104 , which are connected in a ring shape to have one-to-one correspondence with each other. When the plurality of data processors execute data processing in the pre-set order, the data processing subsystem  1  can implement multi-core processing by assigning respective stages of pipeline processing to the respective data processors. 
     Each of the communication processors  101  to  104  executes format conversion of information between the communication path  10  and a corresponding one of the data processors  111  to  114 , and exchanges information between the communication path  10 , another communication processor, and the corresponding data processor. Each of the data processors  111  to  114  executes predetermined data processing for the received information, and passes the processing result to a corresponding one of the communication processors  101  to  104 . Each of the data processors  111  to  114  executes processing in accordance with supplied operation clocks. 
     The data processor  112  exchanges data with the corresponding communication processor  102 . Likewise, the data processors  113  and  114  exchange data with the corresponding communication processors  103  and  104 , respectively. Note that the data processor  111  as data input and output terminals with an external system receives data from the outside of the data processing subsystem  1 , and passes the data to the communication processor  101  after data processing. Also, the data processor  111  receives data from the communication processor  101 , and outputs the data to the outside of the data processing subsystem  1  after data processing. 
     Data input from the data processor  111  is passed to the communication processor  101 , and is converted into information in a format that flows on the communication path  10 . The converted information is then transferred in a ring shape like the communication processor  101 → 102 → 103 → 104 → 101 → . . . . During this process, the data is passed from the communication processor to the data processor, and undergoes data processing. The processed data is passed to the communication processor again. In this sequence, the data processing is executed. Each of the communication processors  101  to  104  has a flip-flop (not shown) having a FIFO arrangement, and shifts data to the communication processor in the direction of an arrow for each cycle time. Hence, paying attention to the communication processors  101  to  104 , they serve as a ring type shift register. As an example of the conversion format of the data processor  111 , data may be divided into those each having a predetermined data size, or transmission information may be appended to data to packetize the data. In the subsequent example, the following description will be given using an example in which data is divided into those each having a fixed length for the sake of descriptive simplicity. 
     When data is passed from the communication processor to the data processor, the data processor may fail to receive the next data since processing of the previously received data is still underway. A status of the data processor at that time is called a hold status. 
     The response time measuring unit  121  measures, as a response time, a time from a timing at which the data processor receives data from the communication processor and starts data processing until a timing at which the data processor completes the data processing. In this way, the response time measuring unit  121  measures a response time of the data processor  111 . Likewise, the response time measuring units  122 ,  123 , and  124  respectively measure response times of the corresponding data processors  112 ,  113 , and  114 . 
     The response time controller  131  controls operating frequencies to be supplied to the data processors  111  to  114 , and acquires hold statuses of the data processors  111  to  114 . Also, the response time controller  131  acquires the response times from the response time measuring units  121  to  124 . 
     (Operating frequency Control) 
     The operating frequency control of the data processors  111  to  114  by the response time controller  131  will be described below. Immediately after the data processing subsystem  1  is started up, the response time controller  131  supplies an identical frequency to the data processors  111  to  114 . The frequency to be commonly supplied to all the data processors  111  to  114  at the startup timing is called a reference frequency Fbase. Therefore, letting fn be an individual frequency to be supplied to a data processor n ( 111 ≦n≦ 114 ), fn=Fbase immediately after the data processing subsystem  1  is started up. 
     The response time measuring units  121  to  124  respectively calculate response times rn ( 111 ≦n≦ 114 ) of the data processors  111  to  114  in this state, and transfer them to the response time controller  131 . In this case, assume that the response times are varied for respective data processors, and a response time r 111  of the data processor  111 =R, a response time r 112  of the data processor  112 =R, a response time r 113  of the data processor  113 =2R, and a response time r 114  of the data processor  114 =4R. 
     The response time controller  131  calculates frequency-to-response time ratios fn/rn for the respective data processors, and derives a minimum ratio fn/rn (to be referred to as a minimum frequency-to-response time ratio (f/r)min hereinafter) from these ratios. In case of this embodiment, f 111 /r 111 =Fbase/R, f 112 /r 112 =Fbase/R, f 113 /r 113 =Fbase/2R, and f 114 /r 114 =Fbase/4R. Therefore, (f/r)min=f 114 /r 114 =Fbase/4R. 
     Next, the response time controller  131  calculates an optimized frequency fn′ for each of the ratios fn/rn other than (f/r)min, so that the frequency-to-response time ratio assumes a neighborhood value of the minimum frequency-to-response time ratio like fn′/rn≈(f/r)min by decreasing the value of fn. Then, the response time controller  131  supplies the optimized frequency fn′ as an operating frequency of each data processor again. In this embodiment, the response time controller  131  supplies f 111 ′=Fbase/4 to the data processor  111 , f 112 ′=Fbase/4 to the data processor  112 , and f 113 ′=Fbase/2 to the data processor  113 . 
     (Basic Processing) 
     The sequence of basic processing from when the response time controller  131  in the data processing subsystem of this embodiment sets the reference frequency Fbase until it re-sets the respective optimized frequencies fn′ will be described below with reference to  FIG. 2 .  FIG. 2  is a flowchart showing the sequence of the basic processing by the response time controller  131  and the response time measuring units  121  to  124 . 
     In step S 201 , the response time controller  131  commonly supplies the reference frequency Fbase to the data processors  111  to  114 . In step S 202 , the response time measuring units  121  to  124  calculate response times rn of the data processors  111  to  114 , and transfer them to the response time controller  131 . In step S 203 , the response time controller  131  calculates frequency-to-response time ratios fn/rn for the respective data processors  111  to  114 . In step S 204 , the response time controller  131  derives a minimum ratio (f/r)min from all the ratios fn/rn. In step S 205 , the response time controller  131  calculates optimized frequencies fn′ for the ratios fn/rn other than the radio (f/r)min so that each frequency-to-response time ratio assumes a neighborhood value of the minimum frequency-to-response time ratio like fn′/rn≈(f/r)min by reducing the value of fn. Furthermore, the response time controller  131  supplies the calculated frequencies fn′ to the data processors  111  to  114 . In this way, the basic processing ends. 
     As described above, according to this embodiment, when respective processing execution modules have processing response time differences, the optimized frequencies fn′ with which the frequency-to-response time ratios assume neighborhood values of the minimum value are calculated for the respective data processors, and are supplied to the respective data processors. That is, when pipeline processing is executed using a plurality of data processing modules having various processing performances, the operating frequencies of other data processing modules are reduced in correspondence with the operation performance of the data processing module having the lowest processing performance. For this reason, according to this embodiment, the consumption power can be reduced while suppressing the processing response performance of a pipeline processing circuit from lowering. 
     &lt;Second Embodiment&gt; 
     Another embodiment associated with frequency control in the response time controller  131  when a hold status has occurred in one (the data processor  113  in this embodiment) of the data processors connected in a ring shape will be described below. Note that the basic arrangement of the system of this embodiment is the same as that of the first embodiment, and the processing until the settings of the optimized frequencies fn′ is complete. 
     Information of a hold status which has occurred in the data processor  113  is sent to the response time controller  131 . The response time controller  131  compares the frequency f 113 =Fbase/2 of the data processor  113  with Fbase. In the above example, since f 113 &lt;Fbase, the response time controller  131  temporarily supplies Fbase to the data processor  113 . 
     As described above, in this embodiment, when the operating frequencies of the data processing modules are controlled, and when a hold status has occurred in one of the data processing modules, the operating frequency of that data processing module is controlled to be the reference frequency until the hold status is released. For this reason, the data processing module (data processor  113 ) that has caused the hold status can execute data processing quicker, thus shortening the hold status. 
     After the hold status is released, the response time controller  131  supplies the optimized frequency f 113 =Fbase/2 to the data processor  113  again. For this reason, the processing response performance of the pipeline processing circuit can be dynamically suppressed from being lowered, as compared with the first embodiment. Also, at the same time, the operating frequencies of the processing modules located on the upstream of the processing module that has caused the hold status may be suppressed. In this way, occurrence of a new hold status can be suppressed, and the power consumption of the upstream processing modules can be reduced. When the hold status is released, the suppressed operating frequencies are reverted to the original operating frequencies. 
     &lt;Third Embodiment&gt; 
     Still another embodiment associated with frequency control in the response time controller  131  when a hold status has occurred in the data processor  114  will be described below. Note that the basic arrangement of the system of this embodiment is the same as that of the first embodiment, and the processing until the settings of the optimized frequencies fn′ is complete. 
     Information of a hold status that has occurred in the data processor  114  is sent to the response time controller  131 . The response time controller  131  compares the frequency f 114 =Fbase of the data processor  114  with Fbase. Since f 114 =Fbase, the response time controller  131  cannot raise clocks supplied to the data processor  114  any more. 
     In this case, the response time controller  131  temporarily supplies clocks whose frequencies are further reduced from their optimized frequencies fn′ to the data processors (those other than the data processor  114  in this embodiment) on the upstream of the data processor  114  (that which has caused the hold status). In this way, since the processing of the upstream data processors is slowed down, occurrence of a new hold status in the data processor  114  can be suppressed, and the data processing efficiency can be relatively improved although the processing speed of the data processor  114  itself remains unchanged, thus shortening the hold status. After the hold status is released, the response time controller  131  supplies the optimized frequencies fn′ to the upstream data processors (those other than the data processor  114 ) again. 
       FIG. 3  is a flowchart showing the sequence of the processing of both the second and third embodiments. Step S 301  shows, as a subroutine, that processing is executed until supply of the optimized frequencies fn′ in the first embodiment, for the sake of convenience. 
     The response time controller  131  monitors in step S 302  if a hold status occurs. If a hold status has occurred in one of the data processors, the process advances to step S 303 . In step S 303 , the response time controller  131  compares the frequency fn supplied to the data processor which has caused the hold status with Fbase. If fn&lt;Fbase (YES in step S 303 ), the process advances to step S 304 ; if fn=Fbase (NO in step S 303 ), the process advances to step S 307 . 
     In step S 304 , the response time controller  131  supplies Fbase to the data processor which has caused the hold status. The response time controller  131  monitors in step S 305  if the hold status of the data processor which has caused the hold status is released. If the hold status is released, the process advances to step S 306 . In step S 306 , the response time controller  131  supplies the optimized frequency fn′ to the data processor which has caused the hold status again, thus ending the flowchart. 
     On the other hand, in step S 307  the response time controller  131  supplies a frequency which is further reduced from the optimized frequency fn′ to each data processor on the upstream of the data processor which has caused the hold status. The response time controller  131  monitors in step S 308  if the hold status of the data processor which has caused the hold status is released. If the hold status is released, the process advances to step S 309 . In step S 309 , the response time controller  131  supplies, again, the optimized frequency fn′ to each data processor on the upstream of the data processor which has caused the hold status, thus ending the flowchart. 
     As described above, in this embodiment, when the operating frequencies of the data processing modules are controlled, and when a hold status has occurred in one of the data processing modules, it is determined whether or not the operating frequency of that data processing module is less than the reference frequency. If the operating frequency is less than the reference frequency, since the operating frequency of the data processing module of interest is controlled to be the reference frequency until the hold status is released as in the second embodiment, the hold status can be shortened. On the other hand, if the operating frequency is equal to the reference frequency, the operating frequency of each data processing module on the upstream of the data processing module, which has caused the hold state, is reduced. Note that when data is not output to the data processing modules on the downstream of the data processing module that has caused the hold status, the operating frequency of each downstream data processing module may be reduced in addition to the upstream data processing modules. In this case, since the number of data processing modules whose operating frequencies are to be reduced is increased, the power consumption can be further reduced. 
     As described above, according to this embodiment, when a hold status has occurred in the data processing module, the power consumption can be reduced by adaptively changing the operating frequency while shortening a recovery time from the hold status. 
     &lt;Fourth Embodiment&gt; 
     Yet another embodiment associated with frequency control of the response time controller  131  when a hold status has occurred in the data processor  113  will be described below. Note that the basic arrangement of the system of this embodiment is the same as that of the first embodiment, and the processing until the settings of the optimized frequencies fn′ is complete. Assume that in this embodiment, the data processors  112  and  114  are not used, and no clocks (or power supply voltages) are supplied to these two data processors  112  and  114 . 
     Information of the hold status which has occurred in the data processor  113  is sent to the response time controller  131 . The response time controller  131  replaces the reference frequency Fbase by an upper limit Fmax of an operable frequency. The upper limit Fmax of the operable frequency is calculated from values (table) or coefficients described in, for example, a ROM (not shown) at the time of delivery inspection of a chip based on the temperature or power consumption of the chip. In this embodiment, since the two data processors  112  and  114  are inactive, as described above, and the power consumption (temperature) of the chip lowers, the upper limit Fmax of the operable frequency assumes a slightly large value. 
     On the other hand, the response time controller  131  temporarily supplies clocks whose frequency is further reduced from the optimized frequency fn′ to the data processor (the data processor  111  in this embodiment; note that no clocks are supplied to the data processor  112  since it is inactive) on the upstream of the data processor  113  which has caused the hold status. As a result, since the processing of the upstream data processor is slowed down, occurrence of a new hold status in the data processor  113  can be suppressed, and the data processing efficiency can be relatively improved, thus shortening the hold status. After the hold status is released, the response time controller  131  supplies the optimized frequency fn′ to the upstream data processor (data processor  111 ) again, and restores the reference frequency from Fmax to Fbase. 
       FIG. 4  is a flowchart showing the sequence of the processing of the fourth embodiment. Step S 401  shows, as a subroutine, that processing is executed until supply of the optimized frequencies fn′ in the first embodiment, for the sake of convenience. 
     The response time controller  131  monitors in step S 402  if a hold status occurs in each of the data processors. If a hold status has occurred, the process advances to step S 403 . In step S 403 , the response time controller  131  supplies clocks of the frequency Fmax to the data processor which has caused the hold status. On the other hand, the response time controller  131  reduces the clock frequency of the data processor (the data processor  111  in this embodiment) located on the upstream (S 404 ). 
     The response time controller  131  monitors in step S 405  if the hold status of the data processor, which has caused the hold status, is released. If the hold status is released, the process advances to step S 406 . In step S 406 , the response time controller  131  supplies the original optimized frequency fn′ as the clock frequency of the data processor which has caused the hold status again. Also, the response time controller  131  reverts the clock frequency of the upstream data processor (the data processor  111  in this embodiment) to the original frequency (S 407 ). After all the frequencies are reverted, the processing ends. 
     In this embodiment, when the operating frequencies of the data processing modules are controlled, and when a hold status has occurred in one of the data processing modules, the operating frequency of that data processing module is set to be the upper limit Fmax of the operable frequency. For this reason, the hold status can be further shortened. On the other hand, the operating frequency of the data processor on the upstream of the data processor which has caused the hold status is reduced. This suppresses occurrence of a new hold status, and reduces the power consumption of the upstream processing module. Note that when data is not output to the data processing modules on the downstream of the data processing module which has caused the hold status, the operating frequency of each downstream data processing module may be reduced in addition to the upstream data processing modules. In this case, since the number of data processing modules whose operating frequencies are to be reduced is increased, the power consumption can be further reduced. 
     &lt;Other Embodiments&gt; 
     In the aforementioned embodiments, the present invention uses the ring type pipeline processing circuit in the description. The present invention may be applied to line type pipeline processing in place of the ring type processing, thus obtaining the same effects. The present invention is not limited to the pipeline processing, and it may be applied to a circuit which divides processing parallelly and executes distributed processing in respective cores, thus obtaining the same effects. The present invention can be applied to a case in which a plurality of cores which have an input/output dependence execute processing in this way. The effects can be expected when the present invention is applied to at least two processing modules in place of all the processing modules. The response time controller  131  may have a quartz oscillator as a clock generator by itself, or may be a circuit which supplies, to the data processors, externally input clocks intact or after they are frequency-divided or multiplied by n. Alternatively, the response time controller  131  may be a circuit which decimates clocks at an appropriate ratio. 
     Settings of the optimized frequencies fn′ may be stored in the response time controller  131  or a storage device outside the data processing subsystem, and the stored settings may be reflected at the second startup timing. In this case, such embodiment is applied to only a case in which the data processing subsystem executes the same processing. In the description of the above embodiments, the frequency-to-response time ratios are controlled to be closer to each other. Since the operation clocks and response time have a correlation, for example, a response time can be controlled to be longer by reducing the operation clocks. Therefore, power savings can be attained by reducing the frequency of the operation clocks to be supplied to at least one of the plurality of processing modules so that the plurality of measured response times become closer to each other. 
     According to the present invention, the power consumption can be reduced while suppressing the processing performance of a data processing circuit having multi-cores from lowering. 
     Aspects of the present invention can also be realized by a computer of a system or apparatus (or devices such as a CPU or MPU) that reads out and executes a program recorded on a memory device to perform the functions of the above-described embodiment(s), and by a method, the steps of which are performed by a computer of a system or apparatus by, for example, reading out and executing a program recorded on a memory device to perform the functions of the above-described embodiment(s). For this purpose, the program is provided to the computer for example via a network or from a recording medium of various types serving as the memory device (for example, computer-readable medium). 
     While the present invention has been described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. The scope of the following claims is to be accorded the broadest interpretation so as to encompass all such modifications and equivalent structures and functions. 
     This application claims the benefit of Japanese Patent Application Nos. 2010-026998, filed on Feb. 9, 2010 and 2010-252956, filed Nov. 11, 2010, which are hereby incorporated by reference herein in their entirety.