Patent Publication Number: US-9893213-B2

Title: Method of forming a wire bond sensor package

Description:
RELATED APPLICATIONS 
     This application is a divisional application of U.S. application Ser. No. 14/809,921, filed Jul. 27, 2015, which claims the benefit of U.S. Provisional Application No. 62/038,429, filed Aug. 18, 2014, and which is incorporated herein by reference. 
    
    
     FIELD OF THE INVENTION 
     The present invention relates to packaged integrated circuit (semiconductor) chips. 
     BACKGROUND OF THE INVENTION 
     An integrated circuit chip mounted on a substrate with the use of wire bonding to connect the integrated circuit chip to the substrate has been a staple practice in the chip packaging industry. As the consumer demand grows for more slim mobile devices, chip-packaging structures must also reduce in size, especially the package height, to meet the slim device trend. 
     A conventional packaging solution is disclosed in U.S. Published Application 2003/0201535, and is shown in  FIG. 1 . The package  1  includes an image sensor chip  2  bonded to an organic package substrate  3 , where the chip  2  is electrically connected to the substrate  3  by bond wires  4 . The bond wires  4  are encapsulated by resin  5  and then again by an encapsulant  6 , while leaving the active area  7  of chip  2  exposed. The active area  7  is enclosed by a transparent element  8 . The image sensor chip  2  is affixed to substrate  3  by adhesive  9 . Off package electrical conductivity is achieved using solder balls  10 . 
     The problem with this package configuration is that its size, and its height in particular, cannot be scaled down as desired. 
     BRIEF SUMMARY OF THE INVENTION 
     The aforementioned problems and needs are addressed by a method of forming a packaged chip assembly, which includes providing a semiconductor chip, providing a second substrate, securing them together, and electrically connecting them together. The semiconductor chip includes a first substrate of semiconductor material having first top and first bottom surfaces, a semiconductor device integrally formed on or in the first top surface, and first bond pads at the first top surface electrically coupled to the semiconductor device. The second substrate includes second top and second bottom surfaces, a first aperture extending between the second top and second bottom surfaces, one or more second apertures extending between the second top and second bottom surfaces, second bond pads at the second top surface, third bond pads at the second bottom surface, and conductors electrically coupled to the second bond pads and the third bond pads. The securing includes securing the first top surface to the second bottom surface such that the semiconductor device is aligned with the first aperture, and each of the first bond pads is aligned with one of the one or more second apertures. The electrically connecting includes electrically connecting each of a plurality of wires between one of the first bond pads and one of the second bond pads, wherein each of the plurality of wires passes through one of the one or more second apertures. 
     A method of forming a packaged chip assembly includes providing a semiconductor chip (which includes a first substrate of semiconductor material having first top and first bottom surfaces, a semiconductor device integrally formed on or in the first top surface, and first bond pads at the first top surface electrically coupled to the semiconductor device), forming one or more trenches into the first top surface, forming a plurality of conductive traces each having a first portion electrically connected to one of the first bond pads, a second portion extending over and insulated from the first top surface, and a third portion extending down into one of the one or more trenches, providing a second substrate (which includes second top and second bottom surfaces, second bond pads at the second top surface, third bond pads at the second bottom surface, and conductors electrically coupled to the second bond pads and to the third bond pads), securing the first bottom surface to the second top surface, and electrically connecting each of a plurality of wires between one of the third portions of one of the plurality of conductive traces and one of the second bond pads. 
     Other objects and features of the present invention will become apparent by a review of the specification, claims and appended figures. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a side cross sectional view of a conventional semiconductor package. 
         FIGS. 2A-2I  are side cross sectional views illustrating the steps in forming the packaged chip assembly of the present invention. 
         FIG. 3A  illustrates the correlation of elements of the packaged chip assembly as viewed from side and top cross sectional directions. 
         FIG. 3B  illustrates the correlation of elements of the packaged chip assembly as viewed from side and bottom cross sectional directions. 
         FIG. 4  is a side cross sectional view illustrating the package chip assembly mounted to a host substrate. 
         FIGS. 5A-5M  are side cross sectional views illustrating the steps in forming an alternate embodiment of the packaged chip assembly of the present invention. 
         FIG. 6  is a side cross sectional view illustrating the alternate embodiment of the package chip assembly mounted to a host substrate. 
         FIGS. 7 and 8  are top views illustrating the alternate embodiment of the package chip assembly mounted to a host substrate. 
         FIG. 9  is a side cross sectional view illustrating the alternate embodiment of the package chip assembly mounted to a host substrate. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The present invention is a packaged chip assembly that offers substantial thickness advantages over existing packaging solutions. The overall package height can be reduced by optimizing bond wire loop height through an improved fan-out package structure and a modification to the die geometry. 
       FIGS. 2A-2I  illustrate the formation of the packaged chip assembly, which begins with fabricating or providing a fan out substrate  20 , which can be made of rigid or flexible material such as ceramic, polyimide, FR4, BT, semiconductor silicon, glass, or any other well-known interposer substrate material. Substrate  20  can be single or multi-layer with at least one electrical routing layer containing electrical conductors  22 . Layout/design of electrical conductors  22  can be random or pseudo-random, and largely dependent of the die layout/design. The electrical routing conductors  22  electrically connect wire bond pads  24  on the substrate&#39;s top surface to interconnect (bond) pads  26  on the substrate&#39;s bottom surface, as illustrated in  FIG. 2A . If the substrate  20  is made of conductive material, then conductors  22  and pads  24 / 26  are insulated from the substrate material by an insulation material. 
     An active area aperture  28  is formed through substrate  20  (which will be aligned with the active area of the semiconductor chip discussed below). A plurality of bond pad apertures  30  are also formed through the substrate  20  (which will be aligned with the bond pads of the semiconductor chip discussed below). Preferably the apertures  28  and  30  do not impinge upon any of the conductors  22 , wire bond pads  24  and interconnect pads  26 , as illustrated in  FIG. 2B . Apertures  28 ,  30  can be formed using a hole puncher, CNC router, etching or any other appropriate cutting method. The apertures  28 ,  30  can have tapered or vertical side walls.  FIGS. 2C and 2D  illustrate two different layout configurations for the apertures and pads of substrate  20 . In each configuration, each bond pad aperture  30  will be aligned with multiple bond pads of the semiconductor chip. 
     A substrate  32  is attached to the substrate  20  using adhesive  34 . Substrate  32  extends over aperture  28 , as illustrated in  FIG. 2E . Substrate  32  can be optically transparent or semitransparent for semiconductor chips having optical active areas (discussed below). For such applications, substrate  32  can be a poly (methyl methacrylate), glass, sapphire, polycarbonate or any other transparent or semitransparent material. Preferably, the substrate is optically transparent glass. A preferred thickness of the substrate  32  is in range of 50 μm to 1000 μm. The substrate  32  can be coated with scratch and impact resistant coating, oleophobic resistant coating, one or more optical layers such as IR, AR or any other appropriate optical layers. Substrate  32  can be cut to the proper size (preferably slightly larger in size than aperture  28 ) by applying dicing tape over the substrate  32  (which protects the substrate  32  and holds it during the dicing process), and singulating the substrate using mechanical dicing, etching, laser or any other well-known singulation methods. The singulated substrate  32  can be detached from the dicing tape by UV deactivation and pick and place process. Adhesive  34  can be a polymer, epoxy, resin or any other appropriate bonding agent. For example, epoxy based adhesive material can be dispensed using a syringing system on to the substrate  32 . A pick and place system can be used to place substrate  32  onto substrate  20 . 
     A semiconductor chip  36  is next provided, as shown in  FIG. 2F . Chip  36  includes a semiconductor substrate  38 , and an active area  40  at the substrate&#39;s upper (top) surface containing a semiconductor device  42  such as an image sensor, an infrared sensor, a light sensor, etc. Bond pads  44  at the substrate&#39;s top surface are directly or indirectly electrically coupled to the semiconductor device  42  (i.e. for off chip conductivity). The chip  36  can be made, for example, from a wafer containing multiple semiconductor devices  42 , where dicing tape is applied over the top surface of the wafer after which the wafer can be thinned (from bottom surface etching—the wafer is preferably thinned to 150 μm or less) before the wafer is singulated into individual chips  36 . Chips such as chip  36  are well known in the art and not further described herein. 
     Adhesive  46  is then deposited on substrate  20  and/or substrate  38 . Adhesive  46  can be polymer, epoxy, resin, die attach tape, or any other appropriate bonding agents or methods that are well known in the art. For example, epoxy based adhesive can be dispensed onto the substrate  20  using a syringing system. Chip  36  is picked and placed onto the substrate  20  by using pick and place process, whereby adhesive  46  secures the bottom surface of the substrates  20  to the top surface of chip  36  so that a hermetically sealed cavity  48  is formed between the active area  40  and substrate  32 . The resulting structure is shown in  FIG. 2G . 
     Wires  50  are used to connect the chip  36  to the substrate  20  as shown in  FIG. 2H . Specifically, each wire  50  has one end connected to one of the bond pads  24  (of substrate  20 ) and the other end connected to one of the bond pads  44  (of the chip  36 ). These connections provide the signals from device  42  to conductors  22  and on to interconnect pads  26 . A loop height (i.e. highest point of the looped wire  50  above the upper surfaces of substrates  20 / 38 ) is preferably lower than the top surface of substrate  32 . Encapsulant  52  is then deposited over the wires  50  and bond pads  24 / 44 . Preferably, the upper surface of encapsulant material  52  is higher than the loop height of the wires  50  yet lower than the top surface of the substrate  32 . Preferably encapsulant  52  is also deposited over the perimeter of the chip substrate  38  and on the bottom surface of substrate  20 . The purpose of the encapsulant  52  is to seal and protect the structure underneath. Interconnects  54  are then formed on the interconnect pads  26  of substrate  20 . Interconnects  54  can be for example ball grid array (BGA), land grid array (LGA), or any other appropriate interconnect methods. BGA is one of the preferred interconnect types and is shown in the figures. BGA interconnects  54  can be formed on the substrate  20  by using a solder ball jetting process or solder ball drop process. The BGA interconnect  54  should extend down lower than the bottom surface of chip  36  and the encapsulant  52  thereon, to enable easy connection to BGA interconnect  54 . The resulting packaged chip assembly  56  is shown in  FIG. 2I . 
       FIG. 3A  shows the correlation of elements of the packaged chip assembly  56  as viewed from side and top cross sectional views.  FIG. 3B  shows the correlation of elements of the packaged chip assembly  56  as viewed from the side and the bottom.  FIG. 4  shows the packaged chip assembly  56  mounted to a host substrate  58  (e.g. using an SMT process). The host substrate  58  can be a rigid or flexible printed circuit board or any other type of host substrate having contact pads  60  (in electrical contact with interconnects  54  and conductors  62 ). 
     With the packaged chip assembly  56 , the semiconductor chip  36  is attached to the substrate  20 , whereby the chip&#39;s electrical signals on contact pads  44  are routed via wires  50  to bond pads  24 , through conductors  22 , to interconnect pads  26  and interconnects  54  connected thereto. Substrate  20  includes apertures  30  for leaving the bond pads  44  of chip  36  exposed for allowing the wire bonding process. The substrate  20  also includes the active area aperture  28  for leaving the active area  40  of chip  36  exposed for allowing the active area  40  (and the semiconductor device  42  therein) to receive light or other sensed energy. The substrate  32  is attached over the topside of substrate  20 , therefore hermetically sealing and protecting the chip active area  40 . The substrate  20  has interconnects  26  on the bottom side for mounting the package chip assembly  56  to host substrate  58 . Because the chip  36  is bonded to the bottom side of the substrate  20  taking up part of the space that is normally wasted when mounting the assembly to a host substrate using interconnects such as BGA, substantial height reduction can be achieved. Further, the bond wires  50  pass through the substrate  20 , therefore reducing the height profile even more in comparison to existing packaging solutions. This structure is especially ideal for image sensors, IR sensors, light sensors or any other optical related sensors. 
       FIGS. 5A-5M  illustrate the formation of an alternate embodiment of the packaged chip assembly. Comparable or similar components will be indicated with the same element numbers. The formation begins with the provision of semiconductor chip  36  discussed above except while still in wafer form (i.e. a plurality of chips  36  formed on a single wafer substrate  38 , after optional thinning, and before singulation), as illustrated in  FIG. 5A . Photoresist  70  is deposited on the active side of the substrate  38 , covering the active area  40  and the bond pads  44 . Photoresist  70  can be deposited with spin coating, spray coating, dry film or any other appropriate photoresist deposition method. Photoresist  70  is developed (i.e. exposed and selectively removed using a photolithographic exposure and etch process) which patterns the photoresist to expose the silicon substrate  38  between two adjacent dies (but without exposing the active areas  40  and bond pads  44 ), as shown in  FIG. 5B . 
     The exposed portions of substrate  38  are etched using an anisotropic dry etch to form trenches  72  into the top surface of substrate  38 . The enchant can be for example CF 4 , SF 6  or any other appropriate etchant. The walls of trench  72  preferably, but not necessarily, are tapered. Trenches  72  can be formed on all four sides, three sides, two sides or a single side of the active area  40  and its associated bond pads  44 . Preferably, the depth of trenches  72  do not exceed 75% of the vertical height of substrate  38 .  FIG. 5C  shows the resulting structure, after photoresist  70  is removed. 
     Photoresist  74  is then deposited on the active side of the substrate  38 , and is developed (i.e. exposed and selectively removed) which patterns the photoresist  74  to expose the silicon substrate  38  (but leaving photo resist  74  disposed just over the active areas  40  and bond pads  44  and not the areas in-between), as shown in  FIG. 5D . Passivation (i.e. insulation material)  76  is deposited on the structure. The passivation  76  can be silicon dioxide, silicon nitride, titanium, a combination of aforementioned passivation or any other appropriate silicon passivation electrical insulation material. Passivation  76  can be and preferably is deposited using physical vapor deposition (PVD). The resulting structure is shown in  FIG. 5E  (after removal of photoresist  74 ). 
     Photoresist  78  is then deposited on the active side of the semiconductor device wafer, and is developed (i.e. exposed and selectively removed) leaving photoresist  78  only over the active areas  40 . A layer of electrically conductive material  80  is deposited over the passivation layer  76  and photoresist  78 . The conductive material layer  80  can be copper, aluminum or any other appropriate conductive material(s), and can be deposited using physical vapor deposition (PVD), plating or any other appropriate deposition method(s). Preferably, the electrically conductive material layer  80  is copper and is deposited by sputtering and then plating. Photoresist  82  is then deposited over conductive layer  80 , and is developed (i.e. exposed and selectively removed) leaving photoresist  82  intact except for over the active areas  40  and at or near the centers of trenches  72 , as shown in  FIG. 5F . An etch is then used to remove the exposed portions of conductive layer  80 , leaving traces  80  of the conductive material each extending from one of the bond pads  44  down into one of the trenches  72 , as shown in  FIG. 5G  (after photoresist  82  and  78  are removed). Traces  80  are in electrical contact with bond pads  44 , but are insulated from substrate  38  by passivation layer  76 , thus electrically routing the bond pads  44  into trenches  72 . 
     Substrate  32  is attached directly over the active area  40 , as shown in  FIG. 5H . As stated above, substrate  32  can be a poly (methyl methacrylate), glass, sapphire, polycarbonate or any other appropriate material, can be optically transparent or semitransparent, and can be treated with scratch and impact resistant coating, oleophobic resistant coating, one or more optical layers such as IR, AR or any other appropriate optical layers. Substrate  32  is attached using a bonding adhesive  84  which can be optically transparent/semitransparent. Adhesive  84  can be deposited either on the active area  40  or on the substrate  32  using a syringing deposition process, and then the substrate  32  is directly attached to the active area  40 . There is no gap or cavity between substrate  32  and active area  40  as in the previously described embodiment. 
     Given the direct mounting of the substrate  32  to the active area  40 , substrate  32  can be sapphire, and more specifically multiple sheets of single crystal sapphire layered in different crystal plane orientations. The many layers of sapphire sheets are bonded using fusion, adhesion or any other appropriate bonding techniques. Optionally, the multilayer sapphire substrate  32  can contain a conductive grid, a conductive mesh, or a suspended conductive particle layer. This conductive layer can be connected to a grounding element to prevent electrostatic discharge (ESD) damage to the semiconductor device  42 . This conductive layer can also be designed to enhance the thermal dissipation rate of the device. Sapphire can be desirable because of its hardness, durability and scratch resistance. These strengths can be enhanced when sheets of sapphire are stacked in different plane orientation. 
     Because of these strengths, the silicon die can be better protected from physical forces such as a finger press. The superior strength of sapphire allows it to be thinner than other materials such as glass. The sapphire substrate thickness can be 100 μm to 1000 μm and still provide sufficient protection to the chip  36 . The thinner sapphire allows for an overall thinner device, and allows the active area  40  to be more sensitive. This can be especially important where the semiconductor device  42  is a capacitive sensor used for fingerprint recognition, where the closer the finger to the active area  40  the better. Sapphire is preferably singulated using a laser-cutting process before mounting to the chip  36 . 
       FIG. 5I  shows an alternate embodiment for mounting substrate  32  onto chip  36 , where no adhesive is deposited between substrate  32  and the active area  40  of chip  36 , which would improve the active area sensitivity, reduce optical or tactile loss, and reduce overall device height. The substrate  32  is attached at its sides with encapsulant/adhesive material  86  deposited by syringing method, preferably deposited under vacuum. The material  86  is preferably lower than the top surface of the substrate  32 . 
     Wafer level dicing/singulation is then performed along scribe lines  88  that pass through trenches  72 , resulting in individual semiconductor chips  36  as shown in  FIG. 5J . Singulation can be performed by mechanical dicing, laser cutting, chemical etching or any other appropriate processes. The singulated chip  36  is then bonded to the top surface of the substrate  20  discussed above, but in this embodiment substrate  20  does not contain the apertures  28  and  30  and chip  36  is not bonded to the bottom surface of substrate  20 . Wires  50  are used to connect the chip  36  to the substrate  20 . Specifically, each wire  50  has one end connected to one of the bond pads  24  (of substrate  20 ) and the other end connected to one of the traces  80  (of the chip  36 ) in one of the trenches  72 . These connections provide the signals from device  42 , through bond pads  42 , traces  80 , wires  50 , bond pads  24 , conductors  22  and on to interconnect pads  26 . A loop height (i.e. highest point of the looped wire  50 ) is preferably lower than the top surface of substrate  32 . The loop height can be made lower given the depth of trenches  72  (as compared to having to run wires  50  from bond pads  44  and/or any portion of the traces  80  running along the top surface of substrate  38 ). Encapsulant  52  is then deposited over the wires  50 , bond pads  24  and traces  80 . Preferably, the top surface of the encapsulant material  52  is lower than the top surface of the substrate  32 , but higher than the peak height of the wires  50  by a certain amount (e.g., 5μm), as shown in  FIG. 5K . Encapsulant  52  can be deposited using syringing, injection molding or any other appropriate encapsulation processes that are well known in the art. Preferably, the deposition method is injection molding. 
     Interconnects  54  are then formed on the interconnect pad  26  of substrate  20 . Interconnects  54  can be for example gall grid array (BGA) as shown in  FIG. 5L , land grid array (LGA) as shown in  FIG. 5M , or any other appropriate interconnect technique. The packaged chip assembly  56  is then mounted on host substrate  58  (e.g. using an SMT process), as shown in  FIG. 6 .  FIGS. 7 and 8  show examples of other components that can be mounted/connected to the host substrate  58 , including electrical devices  90  such as processors, memory, capacitors, etc., and connectors  92  for the substrate  58 . This embodiment structure is ideal for biometric identification semiconductor devices given the contact of the substrate  32  and semiconductor device  42  (either directly or via adhesive  84 ). 
       FIG. 9  illustrates an alternate embodiment to that shown in  FIG. 2I . Instead of substrate  20  including electrical routing conductors  22  therein (for electrically connecting wire bond pads  24  on the substrate&#39;s top surface to interconnect (bond) pads  26  on the substrate&#39;s bottom surface), substrate  20  could be made of a solid material such a conductive semiconductor material or a glass material. The substrate  20  in this embodiment includes holes  96  that extend between the top and bottom surfaces of substrate  20 . Conductive material is deposited in holes  96  to form electrical interconnects  98  that extend through substrate  20 . Wires  50  connect to the electrical interconnects  98  near the top surface of substrate  20  (either directly or using bond pads  100 ), and interconnects  54  connect to the electrical interconnects  98  near the bottom surface of the substrate (either directly or using bond pads  102 ). 
     The electrical interconnects  98  are insulated from the substrate  20  by a layer of compliant dielectric material  104 . A compliant dielectric is a relatively soft material (e.g. solder mask) that exhibits compliance in all three orthogonal directions, and can accommodate the coefficient of thermal expansion (CTE) mismatch between a substrate material such as semiconductor crystalline (˜2.6 ppm/° C.) and interconnect material such as Cu (˜17 ppm/° C.). Compliant dielectric material  104  is preferably a polymer, such as BCB (Benzocyclobutene), solder mask, solder resist, FR4, mold compound, or BT epoxy resin. The compliant dielectric material  104  serves to electrically insulate the electrical interconnects  98  from the substrate  20  in the case where substrate  20  is made of a conductive semiconductor material (so the two do not electrically short together). Compliant dielectric material  104  serves to reduce metal stresses on the substrate  20  in the case where substrate  20  is made of glass. 
     It is to be understood that the present invention is not limited to the embodiment(s) described above and illustrated herein, but encompasses any and all variations falling within the scope of the appended claims. For example, references to the present invention herein are not intended to limit the scope of any claim or claim term, but instead merely make reference to one or more features that may be covered by one or more of the claims. Materials, processes and numerical examples described above are exemplary only, and should not be deemed to limit the claims. Further, as is apparent from the claims and specification, not all method steps need be performed in the exact order illustrated or claimed, but rather in any order that allows the proper formation of the packaged chip assembly of the present invention. Lastly, single layers of material could be formed as multiple layers of such or similar materials, and vice versa. 
     It should be noted that, as used herein, the terms “over” and “on” both inclusively include “directly on” (no intermediate materials, elements or space disposed therebetween) and “indirectly on” (intermediate materials, elements or space disposed therebetween). Likewise, the term “adjacent” includes “directly adjacent” (no intermediate materials, elements or space disposed therebetween) and “indirectly adjacent” (intermediate materials, elements or space disposed there between), “mounted to” includes “directly mounted to” (no intermediate materials, elements or space disposed there between) and “indirectly mounted to” (intermediate materials, elements or spaced disposed there between), and “electrically coupled” includes “directly electrically coupled to” (no intermediate materials or elements there between that electrically connect the elements together) and “indirectly electrically coupled to” (intermediate materials or elements there between that electrically connect the elements together). For example, forming an element “over a substrate” can include forming the element directly on the substrate with no intermediate materials/elements therebetween, as well as forming the element indirectly on the substrate with one or more intermediate materials/elements therebetween.