Patent Publication Number: US-7590771-B2

Title: Chip with IDE host and IDE slave and corresponding self-debugging function

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application claims the priority benefits of U.S. provisional application titled “DVD APPARATUS AND OPERATION” filed on Nov. 22, 2004, Ser. No. 60/630,533. All disclosure of this application is incorporated herein by reference. This application also claims the priority benefit of Taiwan application serial no. 94138540, filed on Nov. 3, 2005. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a chip with IDE (Integrated Drive Electronics) debugging function. More particularly, the present invention relates to a chip with an IDE host and an IDE slave, and self-debugging function. 
     2. Description of the Related Art 
     In some devices such as DVD (digital versatile disc) players, some functions come from the cooperation of a front-end and a backend. The front-end is a DVD servo module, which provides MPEG (motion picture expert group) bit streams obtained from a DVD disc. The backend is an MPEG decoder, which decodes MPEG bit streams into video and audio signals. Usually, the front-end is an IDE slave and the backend is an IDE host. 
     For reasons such as lower cost and smaller chip size, it is desirable to fabricate an IDE host and an IDE slave on the same chip. One related problem is, in such chips, that the host and the slave have to be debugged together. Without isolated debugging, the debugging process tends to be complex and difficult. Therefore, it is desirable to have a chip, which has an IDE host and an IDE slave fabricated together, and offers isolated debugging of the IDE host and the IDE slave. 
     SUMMARY OF THE INVENTION 
     Accordingly, the present invention is directed to a chip that simplifies IDE debugging by offering separate debugging modes for an IDE host and an IDE slave on the same chip. 
     According to an embodiment of the present invention, a chip with IDE host and IDE slave and corresponding self-debugging function is provided. The chip comprises a front-end and a backend. The front-end provides output data of an internal IDE slave or provides output data of an external IDE slave in response to a host debug enable signal. The backend is coupled to the front-end. The backend provides functions of an internal IDE host according to the output data of the internal IDE slave or the external IDE slave, and directs the output data of the internal IDE slave to an external IDE host in response to a slave debug enable signal. 
     In an embodiment of the present invention, the backend further comprises a first switch and the internal IDE host. The first switch directs the output data of the internal IDE slave to the internal IDE host or to the external IDE host in response to the slave debug enable signal. The internal IDE host provides its functions according to the output data of the internal IDE slave received from the first switch and the output data of the external IDE slave received from the front-end. 
     In an embodiment of the present invention, the front-end further comprises the internal IDE slave and a second switch. The internal IDE slave provides its output data to the backend. The second switch provides the output data of the external IDE slave to the backend in response to the host debug enable signal. 
     In an embodiment of the present invention, when the chip is in an integrated mode, the internal IDE host receives the output data of the internal IDE slave. 
     In an embodiment of the present invention, when the chip is in a slave debug mode, the external IDE host receives the output data of the internal IDE slave. 
     In an embodiment of the present invention, when the chip is in a host debug mode, the internal IDE host receives the output data of the external IDE slave. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. 
         FIG. 1  is a schematic diagram showing a chip with IDE host and IDE slave and corresponding self-debugging function according to an embodiment of the present invention. 
         FIG. 2  is a schematic diagram showing the data flow of the chip in  FIG. 1  when the chip is in the integrated mode. 
         FIG. 3  is a schematic diagram showing the data flow of the chip in  FIG. 1  when the chip is in the slave debug mode. 
         FIG. 4  is a schematic diagram showing the data flow of the chip in  FIG. 1  when the chip is in the host debug mode. 
     
    
    
     DESCRIPTION OF THE EMBODIMENTS 
     Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts. 
     Please refer to  FIG. 1 .  FIG. 1  is a schematic diagram showing the chip  100  with IDE host and IDE slave and corresponding self-debugging function according to an embodiment of the present invention. The chip  100  comprises the backend  101  and the front-end  102 , which are fabricated together on the chip  100 . In brief, the front-end  102  provides output data of the internal IDE slave  106  and/or provides output data of the external IDE slave  108  in response to the host debug enable signal HOSTDEN. The backend  101  is coupled to the front-end  102 . The backend  101  provides functions of the internal IDE host  104  according to the output data of the internal IDE slave  106  and/or the external IDE slave  108 . The backend  101  also directs the output data of the internal IDE slave  106  to the external IDE host  103  in response to the slave debug enable signal SLAVEDEN. 
     The front-end  102  comprises the internal IDE slave  106  and the switch  107 . The internal IDE slave  106  provides its output data to the backend  101 . The switch  107  provides the output data of the external IDE slave  108  to the backend  101  in response to the host debug enable signal HOSTDEN. In this embodiment, the switch  107  provides the output data of the external IDE slave  108  when the host debug enable signal HOSTDEN is high, and ignores the output data of the external IDE slave  108  when the host debug enable signal HOSTDEN is low. 
     The backend  101  comprises the switch  105  and the internal IDE host  104 . The switch  105  directs the output data of the internal IDE slave  106  to the internal IDE host  104  or to the external IDE host  103  in response to the slave debug enable signal SLAVEDEN. In this embodiment, the switch  105  directs the output data of the internal IDE slave  106  to the external IDE host  103  when the slave debug enable signal SLAVEDEN is high, and directs the output data of the internal IDE slave  106  to the internal IDE host  104  when the slave debug enable signal SLAVEDEN is low. The internal IDE host  104  provides its functions according to the output data of the internal IDE slave  106  received from the switch  105  and the output data of the external IDE slave  108  received from the front-end  102 . 
     In this embodiment, the internal IDE host  104  and the external IDE host  103  are MPEG decoders, which decode MPEG bit streams. The internal IDE slave  106  is a DVD servo module. The external IDE slave  108  is a DVD-ROM player. Both the internal IDE slave  106  and the external IDE slave  108  provide MPEG bit streams read from storage media such as DVD. 
     Apart from normal operation, the chip  100  has to offer two separate debugging modes, one for the internal IDE slave  106 , and the other for the internal IDE host  104 . Therefore, the chip  100  has three operating modes: the integrated mode, the slave debug mode and the host debug mode. In short, the integrated mode is the normal operation. The slave debug mode is for the separate debugging of the internal IDE slave  106 . The host debug mode is for the separate debugging of the internal IDE host  104 . The operating modes are described in details below. 
     When the chip  100  is in the integrated mode, the slave debug enable signal SLAVEDEN is low, and the host debug enable signal HOSTDEN is also low. The data flow is shown in  FIG. 2 . In the integrated mode, the switch  105  switches the MPEG bit stream from the internal IDE slave  106  to the internal IDE host  104 , and the external IDE slave  108  is inactive. Therefore, the internal IDE host  104  receives and decodes the MPEG bit stream from the internal IDE slave  106 . This is the normal operation of the chip  100 . No debugging is involved. 
     When the chip  100  is in the slave debug mode, the slave debug enable signal SLAVEDEN is high, and the host debug enable signal HOSTDEN is low. The data flow is shown in  FIG. 3 . In the slave debug mode, the switch  105  switches the MPEG bit stream from the internal IDE slave  106  to the external IDE host  103 , and the external IDE slave  108  is inactive. Therefore, the external IDE host  103  receives and decodes the output data of the internal IDE slave  106 . As long as the external IDE host  103  functions correctly, the internal IDE slave  106  can be debugged separately without the interference of the internal IDE host  104 . 
     When the chip  100  is in the host debug mode, the slave debug enable signal is SLAVEDEN low, and the host debug enable signal HOSTDEN is high. The data flow is shown in  FIG. 4 . In the host debug mode, the switch  107  switches the MPEG bit stream from the external IDE slave  108  to the internal IDE host  104 , and the internal IDE slave  106  is inactive. Therefore, the internal IDE host  104  receives and decodes the output data of the external IDE slave  108 . As long as the external IDE slave  108  functions correctly, the internal IDE host  104  can be debugged separately without the interference of the internal IDE slave  106 . 
     As can be seen in the discussions above, the chip  100  in this embodiment of the present invention provides separate debugging modes for an IDE host and an IDE slave on the same chip. It is the separate debugging modes that simplifies IDE debugging. Clearly, the separate debugging modes provide the way to separately debug different parts of a chip which has an IDE host and an IDE slave fabricated together, and then the debugging process tends to be simple and easy. 
     It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.