Patent Publication Number: US-10778170-B2

Title: Automatic gain control for passive optical network

Description:
FIELD OF THE INVENTION 
     The present invention relates in general to a passive optical network and, more particularly, to fast automatic gain control for a burst mode transimpedance amplifier. 
     BACKGROUND OF THE INVENTION 
     A gigabit passive optical network (GPON) provides high speed data communications, over a fiber optical cable, between an internet service provider (ISP) and end user. A GPON uses point-to-multipoint architecture (1:32) with a fiber optic splitter to serve multiple end-points from a single optical source. For example, the GPON includes an optical line terminal (OLT) at the ISP central office or switching center and a plurality of optical network units (ONU) or optical network terminals (ONT) located near the end users. Each ONU serves an individual end user. The GPON is a shared network, in that the OLT sends a stream of data packets as downstream traffic that is seen by all ONUs. Each ONU reads the content of the data packets that correspond to the particular ONU address. Encryption prevents eavesdropping on downstream traffic. GPON does not need to provision individual fibers between the hub and customer. 
     The OLT may include a burst mode (BM) transimpedance amplifier (TIA) with an automatic gain control (AGC) in the data receive channel.  FIG. 1  shows a conventional TIA  10  within the OLT and including front-end amplifier  12 , single-ended to differential (SE2DIFF) amplifier  14 , and common mode level (CML) driver  16  in the data receive channel. AGC  20  has an input coupled to the output of SE2DIFF amplifier  14  and an output controlling the gain of front-end amplifier  12 . AGC  20  detects the signal level after SE2DIFF amplifier  14  and sets the gain of TIA  10 . 
     Each data packet transfer through the OLT and ONU includes a guard time, followed by a preamble, and then the data payload. A settling time is needed for each data packet after the start of the preamble for TIA  10  to achieve lock or reach steady state operation. AGC  20  typically include circuits with low-pass filtering having a long time constant. As data speeds increase, the time contestant of conventional AGC  20  may exceed the time allocated for TIA  10  to reach steady state during the preamble. A faster AGC is needed for higher data speeds. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  illustrates a conventional transimpedance amplifier with automatic gain control; 
         FIG. 2  illustrates a gigabit passive optical network with OLT, optical splitter, and a plurality of ONUs; 
         FIG. 3  illustrates further detail of the OLT of the GPON; 
         FIG. 4  illustrates an automatic gain control for the BM TIA within the OLT; and 
         FIG. 5  illustrates a timing diagram of the automatic gain control. 
     
    
    
     DETAILED DESCRIPTION OF THE DRAWINGS 
     The present invention is described in one or more embodiments in the following description with reference to the figures, in which like numerals represent the same or similar elements. While the invention is described in terms of the best mode for achieving the invention&#39;s objectives, those skilled in the art will appreciate that the description is intended to cover alternatives, modifications, and equivalents as may be included within the spirit and scope of the invention as defined by the appended claims and the claims&#39; equivalents as supported by the following disclosure and drawings. 
       FIG. 2  illustrates GPON  100  providing high speed data communications, over fiber optical cable, between an ISP and end users. GPON  100  includes OLT  102  located within the ISP home office or switching center. OLT  102  makes connection with the internet. OLT  102  is coupled through fiber optical cable  104  to optical splitter  106 , which provides multiple identical optical signal paths through fiber optical cables  108  to ONU  110 ,  112 , and  114  located near end users. In one embodiment, optical splitter  106  connects up to 32 ONUs and brings optical fiber cabling and signals to the end user. GPON  100  is a shared network, in that OLT  102  sends a stream of data packets as downstream traffic through fiber optical cables  104  and  108  to ONU  110 - 114 . Each ONU  110 - 114  reads the content of the data packets that correspond to the particular ONU address. Encryption prevents eavesdropping on downstream traffic. 
       FIG. 3  shows further detail of OLT  102  including triplexer optics  120  coupled to the internet and electro-absorption modulator laser (EML) driver  122 . EML driver  122  can also use an externally modulated laser or distributed feedback laser. An input of EML driver  122  is coupled to the transmit (Tx-in) channel from ONU  110 - 114 . EML driver  122  operates up to  10  gigabits per second (10 G) and uses clock and data recovery (CDR) for the Tx-in channel. Triplexer optics  120  is further coupled to an input of burst mode (BM) transimpedance amplifier (TIA)  124 . In one embodiment, BM TIA  124  operates up to 10 G. Alternatively, BM TIA  124  operates up to 1.25 G or 2.5 G. The output of BM TIA  124  is coupled to an input of BM limiting amplifier (LAM)  126 , and the output of BM LAM  126  is coupled to the receive (Rx-out) channel to ONU  110 - 114 . OLT  102  further includes a micro-control unit for controlling the data transfer. 
       FIG. 4  illustrates further detail of BM TIA  124  with AGC  130 . BM TIA  124  includes terminal  148  from triplexer optics  120  coupled to an input of front-end transimpedance amplifier  150 . The input of front-end transimpedance amplifier  150  receives an input current I IN  and the output provides an output voltage V 180  at node  180  that changes with the magnitude of the input current I IN , although the relative polarities can be changed. In one embodiment, voltage V 180  decreases with an increasing input current I IN . The output of front-end transimpedance amplifier  150  is coupled to an input of single-ended to differential (SE2DIFF) amplifier  152 . SE2DIFF amplifier  152  has differential outputs coupled to the differential inputs of common mode level (CML) driver  154 . The differential outputs of CML driver  154 , shown as terminals  156 , are coupled to the input of BM LAM  126  in the Rx-out channel. 
     AGC  130  includes front-end dummy amplifier  160  configured to operate in a similar manner as front-end amplifier  150  and provides a stable reference voltage, which is approximately the same as V 180 , given zero input current I IN . An output of front-end dummy amplifier  160  is coupled through resistor divider network  162 ,  164 ,  166 ,  168 , and  170  to power supply terminal  172  operating at ground potential. 
     Peak detector  182  monitors the voltage V 180  at node  180 . The output of peak detector  182  is coupled to an inverting input of comparators  184 ,  186 ,  188 , and  190 . The node between resistors  162  and  164  is coupled to a non-inverting input of comparator  184 . The node between resistors  164  and  166  is coupled to a non-inverting input of comparator  186 . The node between resistors  166  and  168  is coupled to a non-inverting input of comparator  188 . The node between resistors  168  and  170  is coupled to a non-inverting input of comparator  184 . 
     The output of comparator  184  is coupled to a data input of latch  192 , and the output of latch  192  is coupled to an input of pulse generator  194 . The output of comparator  186  is coupled to a data input of latch  196 , the output of comparator  188  is coupled to a data input of latch  198 , and the output of comparator  190  is coupled to a data input of latch  200 . The output of latch  196  is coupled to an enable input of comparator  188 , and the output of latch  198  is coupled to an enable input of comparator  190 . Pulse generator  194  provides an enable signal to latches  196 ,  198 , and  200 . RESET at terminal  201  is coupled to the reset inputs of latches  192 ,  196 ,  198 , and  200 . 
     The output of latch  196  is further coupled to the gate of metal oxide semiconductor (MOS) transistor  202 , the output of latch  198  is coupled to the gate of MOS transistor  204 , and the output of latch  200  is coupled to the gate of MOS transistor  206 . Resistors  210 ,  212 ,  214 , and  216  are coupled in series between the input of front-end amplifier  150  and node  180 . The drain of transistor  202  is coupled to the node between resistors  210  and  212 , the drain of transistor  204  is coupled to the node between resistors  212  and  214 , and the drain of transistor  206  is coupled to the node between resistors  214  and  216 . The sources of transistors  202 - 206  are commonly coupled to node  180 . 
     AGC  130  detects the peak voltage at node  180 , and corresponding peak input current I IN , and sets the gain of TIA  124  during a burst cycle. AGC  130  provides multiple stages of digital gain control for BM TIA  124 , while providing a fast settling time. In the present example, AGC  130  provides four levels of gain control. Devices  190 ,  200 , and  206  represent a first gain stage, devices  188 ,  198 , and  204  represent a second gain stage, and devices  186 ,  196 , and  202  represent a third gain stage. Additional gain stages, like  190 ,  200 , and  206 , provide more levels of gain control. Front-end dummy amplifier  160  mimics front-end amplifier  150  (provides same output voltage as node  180  at zero input current I IN ) and sets the AGC threshold levels for comparators  184 - 190 . 
     That is, front-end dummy amplifier  160  establishes reference voltages for comparators  184 - 190 . In one embodiment, front-end dummy amplifier  160  provides 1.7 volts to generate references voltages ranging from 40-800 millivolts (mv) for comparators  184 - 190 . In 2.5 G and 10 G applications, resistors  162 - 168  are selected to generate references voltages of 40 mv, 200 mv, 250 mv, and 350 mv for comparators  184 - 190 , respectively. In 1.25 G applications, resistors  162 - 168  are selected to generate references voltages of 40 mv, 300 mv, 500 mv, and 800 mv for comparators  184 - 190 , respectively. 
     Consider the operation of BM TIA  124  with AGC  130  during one burst mode data packet, see  FIGS. 4 and 5 . Time t 0  marks the start of a data packet. At time t 0 , the RESET signal at terminal  201  goes to logic one and resets latches  192 ,  196 ,  198 , and  200  to logic zero during guard time t 0 -t 1  of the input signal  148  during the burst mode data packet, see waveforms  230  and  232 . RESET  201  returns to logic zero before time t 1 . The output of comparator  184  has a logic one when the output signal of peak detector  182  exceeds the reference voltage V 162 . The output of comparator  186  is logic zero otherwise. The output of comparator  186  has a logic one when the output signal of peak detector  182  exceeds its reference voltage. The output of comparator  186  is logic zero otherwise. The output of comparator  188  has a logic one when enabled and the output signal of peak detector  182  exceeds its reference voltage. The output of comparator  188  is logic zero otherwise. The output of comparator  190  has a logic one when enabled and the output signal of peak detector  182  exceeds its reference voltage. The output of comparator  190  is logic zero otherwise. 
     Front-end transimpedance amplifier  150  receives input current I IN  and provides a corresponding voltage V 180  to SE2DIFF amplifier  152  starting at time t 1 . Times t 1 -t 2  is the preamble portion of the burst mode data packet. Peak detector  182  is an input of AGC  130  and monitors V 180  to provide a voltage to the first inputs of comparators  184 - 190  corresponding to the peak value of V 180 . Comparators  184 - 190  compare the output of peak detector  182  with reference voltages developed by resistors  162 - 170 . 
     If I IN  is less than 50 μa, then there is no data signal and AGC  130  continues to wait until the next RESET cycle. In the present example, peak detector  182  determines that the magnitude of input current I IN  is greater than 50 μa, which causes the output voltage of peak detector  182  to exceed the 40 mv threshold of comparator  184 . The output signal of comparator  184  goes to logic one. Latch  192  stores the logic one from comparator  184  and triggers pulse generator  194  to generate a 25 ns pulse as AGC CONTROL waveform  234  in  FIG. 5 . AGC CONTROL (output of pulse generator  194 ) enables latches  196 ,  198 , and  200 . Assuming the output voltage of peak detector  182  is less than the thresholds of comparators  186 - 190 , then the output of comparators  186 - 190  is logic zero and the output of latches  196 - 200  is logic zero, and transistors  202 - 206  are all non-conductive. The resistance across front-end amplifier  150  is the series sum of resistors  210 - 216 , i.e., R 210 +R 212 +R 214 +R 216 . Front-end amplifier  150  has maximum gain given by the feedback resistance R 210 +R 212 +R 214 +R 216  corresponding to the minimum input current I IN . 
     If the magnitude of input current I IN  is greater than 150 μa, then the output voltage of peak detector  182  exceeds the 200 mv threshold of comparator  186 . The output of comparator  186  goes to logic one, which is stored in latch  196 . Assume the output voltage of peak detector  182  does not exceed the thresholds of comparators  188  and  190 . The logic one from latch  196  turns on transistor  202 , and the logic zeros from latches  198  and  200  turn off transistors  204 - 206 . The conductive transistor  202  disables resistor  210 , i.e., the conductive path through resistor  210  is shorted by the low drain-source resistance of transistor  202 . The resistance across front-end amplifier  150  is the series sum of resistors  212 - 216 , i.e., R 212 +R 214 +R 216 . Front-end amplifier  150  has a lesser gain given by the feedback resistance R 212 +R 214 +R 216  corresponding to the larger magnitude of input current I IN . 
     If the magnitude of input current I IN  is greater than 300 μa, then the output voltage of peak detector  182  exceeds the 250 mv threshold of comparator  188 . The output of comparator  188  goes to logic one, which is stored in latch  198 . Assume the output voltage of peak detector  182  does not exceed the thresholds of comparator  190 . The logic one from latches  196  and  198  turn on transistors  202  and  204 , and the logic zero from latch  200  turns off transistor  206 . The conductive transistor  204  disables resistor  212 , i.e., the conductive path through resistor  212  is shorted by the low drain-source resistance of transistor  204 . The resistance across front-end amplifier  150  is the series sum of resistors  214 - 216 , i.e., R 214 +R 216 . Front-end amplifier  150  has a lesser gain given by the feedback resistance R 214 +R 216  corresponding to a larger magnitude of input current I IN . 
     If the magnitude of input current I IN  is greater than 500 μa, then the output voltage of peak detector  182  exceeds the 350 mv threshold of comparator  188 . The output of comparator  190  goes to logic one, which is stored in latch  200 . The logic one from latches  196 - 200  turn on transistors  202 - 206 . The conductive transistor  206  disables resistor  214 , i.e., the conductive path through resistor  214  is shorted by the low drain-source resistance of transistor  206 . The resistance across front-end amplifier  150  is the resistor  216 , i.e., R 216 . Front-end amplifier  150  has a minimum gain given by the feedback resistance R 216  corresponding to the maximum input current I IN . 
     When AGC CONTROL goes to logic zero in  FIG. 5  (end of 25 ns pulse from  194 ), AGC  130  is locked with the proper gain, given the input current I IN . The input current I IN    148  is processed through BM TIA  124 , with the proper gain for the given speed, during the payload portion of the burst mode data packet after time t 2 . AGC  130  is reset for the next burst mode during the guard time and the proper gain for the given speed is again set, as described above. The time required to set the gain of AGC  130  is 25.6 ns for 10 G mode and 12.8 ns for 2.5 G mode, which is faster than the prior art implementations. AGC  130  supports the lock time requirements of GPON  100 , i.e., BM TIA  124  settles within 25 ns after time t 1 , during the preamble portion of the burst mode data packet. AGC  130  provides stable operation of BM TIA  124 . AGC  130  is shown with four gain stages, although additional gain stages like  190 ,  200 ,  206 , and  216  can be added. 
     While one or more embodiments of the present invention have been illustrated in detail, the skilled artisan will appreciate that modifications and adaptations to those embodiments may be made without departing from the scope of the present invention as set forth in the following claims.