Patent Publication Number: US-11652029-B2

Title: 3-D package structure for isolated power module and the method thereof

Description:
FIELD 
     The present invention relates to semiconductor packages, and more particularly relates to isolated power module package structures. 
     BACKGROUND 
     Isolated power module packages comprise a transformer, an IC die, capacitors and other components. The IC die which contains a voltage regulator is typically placed side by side with the transformer on a printed circuit board, which enlarges the package size. In addition, air cored transformers without magnets are adopted, which is weak in power rating and EMI performance. 
     Thus, efforts are needed in the field to provide a better package structure. 
     SUMMARY 
     It is an object of the present invention to provide an improved package structure, which solves the above problems. 
     In accomplishing the above and other objects, there has been provided, in accordance with an embodiment of the present invention, a 3-D package structure, comprising: a support layer, configured to contain metal traces; a first magnetic layer, attached to a first surface of the support layer; an up board, stacked on the support layer; a second magnetic layer, attached between a second surface of the support layer and the up board, the first surface and the second surface of the support layer being opposite to each other; and an IC die, stacked on the up board, the IC die being configured to contain a voltage regulator. 
     In addition, there has been provided, in accordance with an embodiment of the present invention, a 3-D package structure, comprising: a support layer, configured to contain metal traces; a first magnetic layer and a second magnetic layer, attached respectively on a first surface and a second surface of the support layer, the first surface and the second surface are opposite to each other; and an IC die, assembled above the first magnetic layer, the IC die being configured to contain a voltage regulator. 
     Furthermore, there has been provided, in accordance with an embodiment of the present invention, 3-D packaging method, comprising: attaching a first magnetic layer to a first surface of a support layer, the support layer containing metal traces; attaching a second magnetic layer between a second surface of the support layer and an up board, the up board being stacked above the support layer, and the first surface and the second surface of the support layer are opposite to each other; stacking an IC die on the up board, the IC die being configured to contain a voltage regulator; and assembling other passive components on the up board. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG.  1    schematically shows a 3-D packaging structure  100  in accordance with an embodiment of the present invention. 
         FIG.  2    schematically shows a 3-D packaging structure  200  in accordance with an embodiment of the present invention. 
         FIG.  3    schematically shows a 3-D packaging structure  300  in accordance with an embodiment of the present invention. 
         FIG.  4    schematically shows a flowchart  400  of a 3-D packaging method in accordance with an embodiment of the present invention. 
     
    
    
     The use of the similar reference label in different drawings indicates the same of like components. 
     DETAILED DESCRIPTION 
     Embodiments of circuits for a 3-D package structure are described in detail herein. In the following description, some specific details, such as example circuits for these circuit components, are included to provide a thorough understanding of embodiments of the invention. One skilled in relevant art will recognize, however, that the invention can be practiced without one or more specific details, or with other methods, components, materials, etc. 
     The following embodiments and aspects are illustrated in conjunction with circuits and methods that are meant to be exemplary and illustrative. In various embodiments, the above problem has been reduced or eliminated, while other embodiments are directed to other improvements. 
       FIG.  1    schematically shows a 3-D package structure  100  in accordance with an embodiment of the present invention. In the example of  FIG.  1   , the 3-D package structure  100  comprises: a support layer  103 , configured to contain metal traces  110  (e.g. copper traces, shown as dashed line); a first magnetic layer  101  and a second magnetic layer  102 , attached respectively on a first surface  1031  and a second surface  1032  of the support layer  103 ; and an IC die  104 , assembled above the first magnetic layer  101 , the IC die  104  being configured to contain a voltage regulator. The first surface  1031  and the second surface  1032  are opposite to each other. 
     One skilled in the art should realize that the so-called 3-D in the present invention refers to three dimensions, i.e., x, y, and z directions. 
     In one embodiment of the present invention, the first magnetic layer  101  and the second magnetic layer  102  may be respectively attached to the support layer  103  by way of an adhesive layer. 
     In another embodiment of the present invention, the first magnetic layer  101  and the second magnetic layer  102  may be embedded into the support layer  103 . 
     In one embodiment of the present invention, the package structure  100  may be assembled at a lead frame  120 , e.g., the support layer  103  and the IC die  104  may be coupled to the lead frame by bonding wires. 
     In one embodiment of the present invention, the support layer  103  may comprise a substrate board, and the metal traces may be embedded in the substrate board. 
     In one embodiment of the present invention, the support layer  103  includes multiple layers, e.g., the support layer  103  may comprise a multilayer substrate. 
       FIG.  2    schematically shows a 3-D package structure  200  in accordance with an embodiment of the present invention. In the example of  FIG.  2   , the 3-D package structure  200  comprises: a support layer  103 , configured to contain metal traces  110 ; a first magnetic layer  101 , attached to a first surface of the support layer  103 ; an up board  105 , stacked on the support layer  103 ; a second magnetic layer  102 , attached between a second surface of the support layer  103  and the up board  105 ; and an IC die  104 , stacked on the up board  105 , the IC die  104  being configured to contain a voltage regulator. The first surface and the second surface of the support layer  103  are opposite to each other. 
     In one embodiment of the present invention, the up board  105  includes multiple layers, e.g., the up board  105  may comprise a multilayer substrate. 
     In one embodiment of the present invention, the IC die  104  may comprise a flip chip, electrically coupled to the up board  105  by way of contacts (e.g., metal contacts, or contact bumps). 
     In one embodiment of the present invention, the support layer  103  may comprise a substrate board, and the metal traces may be embedded in the substrate board. 
     In the example of  FIG.  2   , the up board  105  is electrically coupled to the support layer  103  and the lead frame  120  by bonding wires. 
     In one embodiment of the present invention, the IC die  104  may comprise other package types. It may have ball grid array (BGA), or land grid array (LGA), or quad flat no-leads package (QFN), or chip scale package (CSP). 
       FIG.  3    schematically shows a 3-D package structure  300  in accordance with an embodiment of the present invention. In the example of  FIG.  3   , the 3-D package structure  300  is similar to the 3-D package structure  200  in  FIG.  2   , with a difference that the IC die  104  in the 3-D package structure  300  is coupled to the up board  105 , the support layer  103  and the lead frame  120  by way of bonding wires. 
     In the embodiments of  FIG.  2    and  FIG.  3   , other passive components (e.g. capacitors) may be assembled on the up board  105 . 
       FIG.  4    schematically shows a flowchart  400  of a 3-D packaging method in accordance with an embodiment of the present invention. The method comprising: 
     Step  401 : attaching a first magnetic layer to a first surface of a support layer, the support layer containing metal traces. 
     Step  402 : attaching a second magnetic layer between a second surface of the support layer and an up board, the up board being stacked above the support layer, and the first surface and the second surface of the support layer are opposite to each other. 
     Step  403 , stacking an IC die on the up board, the IC die being configured to contain a voltage regulator. And 
     Step  404 : assembling other passive components on the up board. 
     In one embodiment of the present invention, the method further comprising: assembling the package on a lead frame. 
     In one embodiment of the present invention, the IC die comprises a flip chip, electrically coupled to the up board by way of contacts; and the support layer and the up board may be electrically coupled to the lead frame by way bonding wires. 
     In another embodiment of the present invention, the IC die may be electrically coupled to the up board, the support layer and the lead frame by way of bonding wires. 
     In one embodiment of the present invention, the support layer and the up board may respectively comprise a multilayer substrate, and the metal traces are embedded into the support layer. 
     Several embodiments of the foregoing 3-D package structure provide better transformer design. Unlike the conventional technology, several embodiments of the foregoing 3-D package structure have the metal traces be covered by magnetic films from both sides, thus an effective transformer is formed, which doubles the power throughput and attenuates the radiation emission from transformer windings. In addition, because IC die, the supported layer, the magnetic layers, and the up board are stacked in vertical direction, the size is significantly reduced. 
     It is to be understood in these letters patent that the meaning of “A” is coupled to “B” is that either A and B are connected to each other as described below, or that, although A and B may not be connected to each other as described above, there is nevertheless a device or circuit that is connected to both A and B. This device or circuit may include active or passive circuit elements, where the passive circuit elements may be distributed or lumped-parameter in nature. For example, A may be connected to a circuit element that in turn is connected to B. 
     This written description uses examples to disclose the invention, including the best mode, and also to enable a person skilled in the art to make and use the invention. The patentable scope of the invention may include other examples that occur to those skilled in the art.