Patent Publication Number: US-6988207-B2

Title: Scan insertion testing of ASICs

Description:
TECHNICAL FIELD 
   The present invention relates generally to application specific integrated circuits (ASICs) and, in particular, to scan insertion testing in ASICs. 
   BACKGROUND 
   Application Specific Integrated Circuits (ASICs) often have an internally generated clock, such as divide-down clock  102  shown in  FIG. 1 , that activates the internal logic of the ASIC. Internally generated clocks are generated from an external functional clock, e.g., functional clock  104 . Frequently, the frequency of the functional clock is reduced using a frequency divider, e.g., frequency divider  106 , which divides the frequency by x, where x is a numerical value greater than one. The division is performed to accommodate specific internal clock requirements. 
   In many instances, ASICs are tested for faults, such as stuck-at faults, e.g., stuck flip-flops. Flip-flops generate a stable one or zero signal depending on inputs. If flip-flops are stuck, problems occur with signal generation. Although there are multiple methods for design for testability (DFT), one of the most popular methods to test for stuck-at faults is scan insertion. Basically, flip-flops in the ASIC are replaced with scan flip-flops. These scan flip-flops have a multiplexer in front of the flip-flop that allows a selection between normal functional data or specially generated test patterns. The selector to the multiplexer is a scan enable signal that determines which data goes to the input of the flip-flop. 
   One problem when inserting scan flip-flops is how to control the clocks that drive the flip-flops. A popular method is to add a multiplexer, e.g., multiplexer  108 , to the ASIC clock circuitry. An input pin of a multiplexer  108  is connected to an output of frequency divider  106 , and another input pin of multiplexer  108  is connected to a test clock, e.g., test clock  110  shown in  FIG. 1. A  scan-insertion test signal, e.g., scan-tester  110 , is connected to a select pin of multiplexer  108 . Scan-tester  112  switches the ASIC between a functional mode and a test mode, selecting the functional clock for normal operation and the test clock for a testing operation. In functional mode, divide-down clock  102  (whose source is the output of frequency divider  106 ) drives the internal logic of the ASIC. In test mode, test clock  112  is now connected to divide-down clock  102  to drive the internal logic of the ASIC to test the operation of the ASIC. 
   Another problem associated with existing scan insertion ASIC testing is that the internally generated divide-down clock can be skewed relative to the functional clock, because the clocks are independent. Skewing is compounded between the functional clock and the internally generated divide-down clock because of the multiplexer added to control the scan flip-flops. The effect of the skew often causes timing issues that can lead to set-up and hold violations during testing. 
   For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for eliminating the skew between the functional clock and the internally generated divide-down clock used in existing scan insertion ASIC testing. 
   SUMMARY 
   The above-mentioned problems with skewing between a functional clock and internally generated divide-down clocks used in existing scan insertion ASIC testing and other problems are addressed by embodiments of the present invention and will be understood by reading and studying the following specification. Some embodiments of the present invention eliminate skewing between the functional clock and internally generated divide-down clocks used in existing scan insertion ASIC testing by providing a circuit and method that eliminates the use of internally generated divide-down clocks during scan testing. 
   More particularly, in one embodiment, the circuit has an input port connected to a functional clock and the input of a tri-state output port that is controlled by a tester signal. The tri-state output port connected to the tester signal is configured to receive that tester control signal to selectively block and unblock the input connected to the functional clock. In addition, this tri-state output port is part of a bi-directional buffer that is connected to a second clock. The input port of the bi-directional buffer has an output that drives the internal logic of the ASIC. When the tri-state output port connected to the functional clock is blocked (tri-stated), the second clock (e.g. a test clock) can now drive the internal logic of the ASIC via the input port of the bi-directional buffer. When the tri-state output port connected to the functional clock is unblocked (not tri-stated), the functional clock transmits a clock signal to the internal logic of the ASIC via the input port of the bi-directional buffer. In this mode the functional clock can also be used to drive logic external to the ASIC if needed. 
   Another embodiment provides a test method that includes receiving a control signal at a circuit and selectively blocking a first clock signal received at the circuit based on the control signal. The method includes receiving a second clock signal at a bi-directional port of the circuit and transmitting the second clock signal when the first clock signal is blocked. Moreover, the method includes transmitting the first clock signal when the first clock signal is not blocked. 
   Other embodiments are described and claimed. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a diagram of a prior art circuit. 
       FIG. 2  is a circuit diagram according to the teachings of one embodiment of the present invention. 
       FIG. 3  is a flow chart diagram of a method according to another embodiment of the present invention. 
       FIG. 4  is a flow chart diagram of a method according to another embodiment of the present invention. 
   

   DETAILED DESCRIPTION 
   In the following detailed description, reference is made to the accompanying drawings that form a part hereof, and in which is shown by way of illustration specific illustrative embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other embodiments may be utilized and that logical, mechanical and electrical changes may be made without departing from the spirit and scope of the present invention. The following detailed description is, therefore, not to be taken in a limiting sense. 
   Embodiments of the present invention eliminate skewing between a functional clock and internally generated divide-down clocks used in existing scan insertion ASIC testing by providing a circuit and method that eliminates the use of internally generated divide-down clocks during scan testing. Embodiments of the present invention replace internally generated divide-down clocks with externally controlled clocks that are connected to a bi-directional port. 
     FIG. 2  illustrates a circuit  200 , according to one embodiment of the present invention. Circuit  200 , in one embodiment, is a part of ASIC  201 . Circuit  200  receives a control signal from a scan-tester, e.g., scan-tester  204 , and a clock signal from output port  206  of frequency divider  208 . Circuit  200  outputs a signal to internal logic devices and flip-flops of an ASIC, for example, ASIC  201 , where, in one embodiment, scan-tester  204  and frequency divider  208  are part of ASIC  201 . Frequency divider  208  is connected to an output  210  of functional clock  212  and divides a clock signal generated by functional clock  212  by x, where x, in one embodiment, is a number greater than one. Divide down by frequency divider  208  is performed to supply a suitable clock frequency to circuit  200 . In one embodiment, functional clock  212  is a part of ASIC  201 . 
   In another embodiment, a circuit  200  is provided that receives a control signal from output port  202  of scan-tester  204 , a clock signal from output port  206  of frequency divider  208 , and a clock signal from divide/test clock  214  via bi-directional port  216 . In this embodiment, the circuit  200  outputs a signal to the internal logic devices and flip-flops of ASIC  201 . The signal from divide/test clock  214  tests the ASIC for faults. In one embodiment, divide/test clock  214  is a part of ASIC  201 . 
   Circuit  200  includes tri-state output buffer  218  having inputs  220  and  222  respectively connected to output  202  of scan-tester  204  and output  206  of frequency divider  208 . Circuit  200  includes divide/test clock  214 . Divide/test clock  214  is connected to output  224  of tri-state output buffer  218  via a bi-directional port  216 . Circuit  200  further includes input buffer  226  having an input  228  and an output  230 . Output  230  of input buffer  226  is connected to the internal logic and flip-flops of an ASIC, e.g., ASIC  201 . Input  228  of input buffer  226  is connected to output  224  of tri-state output buffer  218  and to bi-directional port  216 . 
   In operation, circuit  200  is selectively switched between a functional mode and a test mode by a scan-test signal, or control signal, from scan-tester  204 . In the functional mode, the control signal is low, or inactive. Circuit  200  receives a divided-clock signal from frequency divider  208 . When the control signal is low, the divided-clock signal flows through tri-state output buffer  218  and directly into input buffer  226 . The divided-clock signal then flows from input buffer  226  to the internal logic and flip-flops of ASIC  201 . This enables functional clock  212  to activate and operate the internal logic of the ASIC directly, eliminating the need for the multiplexer  108  of FIG.  1 . In one embodiment, the divided clock can be sent off chip to drive external logic, if needed. 
   A test mode is initiated when the tri-state output buffer  218  receives a high, or active, control signal from scan-tester  204 . The active control signal instructs the tri-state output buffer  218  to block the divided-clock signal from frequency divider  208 . Meanwhile, the divide/test clock  214  sends a clock signal to the internal logic and flip-flops of ASIC  201  via bi-directional port  216  and input buffer  226  to test the ASIC for faults, e.g., stuck flip-flops. This eliminates the clock skewing associated with using test clocks multiplexed in conjunction with internally generated clocks, such as test clock  110  and functional clock  104  of FIG.  1 . 
     FIG. 3  is a flow chart of an embodiment of a test method  300  according to the teachings of the present invention. Test method  300  includes receiving a control signal indicative of an active or inactive test mode of a circuit at block  302 . In one embodiment, the control signal is received at a circuit, such as circuit  200 , from a scan-tester, such as scan-tester  204 . The control signal is evaluated at decision block  304 . If the test mode is inactive, a first external clock is connected through the circuit through a buffer at block  306 . In one embodiment, this includes coupling a functional clock, such as functional clock  210 , and a frequency divider, such as frequency divider  208 , through a circuit through an output buffer. If the test mode is active, a second external clock is connected through the circuit through a bi-directional port and an input buffer at block  308 . In one embodiment, this includes coupling a divide/test clock, such as divide/test clock  214 , through a circuit, such as circuit  200 , through a bi-directional port and an input buffer. 
     FIG. 4  is a flow chart of an embodiment of another test method  400  according to the teachings of the present invention. Test method  400  includes receiving a control signal at a circuit at block  402 . In one embodiment, the control signal is received at a circuit, such as circuit  200 , from a scan-tester, such as scan-tester  204 . The control signal is evaluated at decision block  404 . If the control signal is active, a first clock signal received at the circuit is blocked in block  406 . In one embodiment, the active control signal instructs an output buffer, such as output buffer  218 , to block the divided-clock signal from a frequency divider, such as frequency divider  208 . A second clock signal is received at a bi-directional port of the circuit at block  408  and is transmitted at block  410 . In one embodiment, the second clock signal is received at a bi-directional port, such as bi-directional port  216 , from a divide/test clock, such as divide/test clock  214 . The second clock signal is transmitted to internal logic and flip-flops of an ASIC through an input buffer to test the ASIC for faults, e.g., stuck flip-flops. If the control signal is inactive, the first clock signal is transmitted at block  412 . In one embodiment, the first clock signal is a divided-clock signal that flows through an output buffer, into an input buffer, and to internal logic and flip-flops of an ASIC. 
   CONCLUSION 
   Embodiments of the present invention have been described. The embodiments eliminate skewing between functional clocks and internally generated divide-down clocks used in existing scan insertion ASIC testing by providing, in various embodiments, circuits and methods that eliminate the use of internally generated divide-down clocks for scan testing. Embodiments of the present invention replace internally generated divide-down clocks with external test clocks that are connected to a bi-directional port and that are independent of any functional clocks. 
   Although specific embodiments have been illustrated and described in this specification, it will be appreciated by those of ordinary skill in the art that any arrangement that is calculated to achieve the same purpose may be substituted for the specific embodiment shown.