Patent Publication Number: US-7898901-B2

Title: Method for controlling clock cycle time for reduced power consumption in a semiconductor memory device

Description:
This application is a Divisional of U.S. application Ser. No. 12/368,148, filed Feb. 9, 2009 now U.S. Pat. No. 7,729,197, which is a Divisional of U.S. application Ser. No. 11/458,631, filed Jul. 19, 2006, now U.S. Pat. No. 7,489,587, which is a Continuation of U.S. application Ser. No. 10/147,146, filed May 16, 2002, now U.S. Pat. No. 7,319,728, all of which are incorporated herein by reference. 
    
    
     FIELD 
     The embodiments of the invention relate generally to integrated circuits, and in particular to delay locked loops. 
     BACKGROUND 
     Delay locked loops (DLL) reside in many integrated circuits for delaying an external signal to obtain an internal signal. The internal signal usually serves as a reference signal for the integrated circuits instead of the external signal because the internal signal matches internal operating conditions of the integrated circuits, such as process, voltage, and temperature, better than the external signal does. 
     A typical DLL has number of delay elements, forming a delay line. The external signal propagates through a certain number of activated delay elements in the delay line to become the internal signal. The activated delay elements toggle (switch) in every cycle of the external signal. Each delay element consumes power when it toggles. The power consumption is proportional to the number of toggles. In some cases, improving the power consumed by the DLL is necessary. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  shows a delay locked loop circuit according to an embodiment of the invention. 
         FIG. 2  shows an example of a timing diagram for  FIG. 1 . 
         FIG. 3  shows more detail of the delay locked loop circuit of  FIG. 1 . 
         FIG. 4  is a timing diagram of various signals of the DLL of  FIG. 3 . 
         FIG. 5  shows a delay line and an adjusting unit of  FIG. 3 . 
         FIG. 6  shows a variation of the delay line and the adjusting unit of  FIG. 5 . 
         FIG. 7  shows a phase detector according to an embodiment of the invention. 
         FIG. 8  shows an input cycle controller according to an embodiment of the invention. 
         FIG. 9  is a timing diagram for  FIG. 8 . 
         FIG. 10  shows an output cycle controller according to an embodiment of the invention. 
         FIG. 11  is a timing diagram for  FIG. 10 . 
         FIG. 12  shows an output cycle controller according to another embodiment of the invention 
         FIG. 13  is a timing diagram for  FIG. 12 . 
         FIG. 14  shows a memory device according to an embodiment of the invention. 
         FIG. 15  shows a system according to an embodiment of the invention. 
     
    
    
     DESCRIPTION OF EMBODIMENTS 
     The following description and the drawings illustrate specific embodiments of the invention sufficiently to enable those skilled in the art to practice the embodiments of the invention. Other embodiments may incorporate structural, logical, electrical, process, and other changes. Examples merely typify possible variations. Portions and features of some embodiments may be included in or substituted for those of others. The scope of the invention encompasses the full ambit of the claims and all available equivalents. 
       FIG. 1  shows a DLL according to an embodiment of the invention. DLL  100  includes a forward path  106  for receiving an external signal XCLK to generate an internal signal DLLCLK. A feedback path  108  provides a feedback signal CLKFB based on a signal from forward path  106 . A delay controller  110  compares the XCLK and CLKFB signals to keep the XCLK and DLLCLK signals synchronized. 
     Forward path  106  has a delay line  112  for applying a delay to an input signal CLKIN to produce an output signal CLKOUT. An input cycle controller  116  controls a cycle time of the CLKIN signal, entering delay line  112 . An output cycle controller  118  modifies a cycle time of the CLKOUT signal, exiting delay line  112 . Controlling the cycle time of the CLKIN signal controls the power consumption of delay line  112 . 
     Input cycle controller  116  controls the cycle time of the CLKIN signal by increasing the cycle time of the XCLK signal. This reduces the number of edges of the CLKIN signal propagating through delay line  112 . When the number of edges is reduced, the number of toggles of delay elements in delay line  112  is decreased. When the number of toggles decreases, the power consumption of delay line  112  decreases. 
     In some embodiments, output cycle controller  118  decreases the cycle time of the CLKOUT signal to restore the cycle time of the XCLK signal so that the DLLCLK and XCLK signals have an equal cycle time. 
     Feedback path  108  has a delay model  114  for delaying the DLLCLK signal to provide a feedback signal CLKFB. This feedback signal is a version of the DLLCLK signal. 
     Delay controller  110  compares the XCLK and CLKFB signals to determine a delay between the XCLK and DLLCLK signals. Based on the comparison, delay controller  110  selects tap lines  115 . 1 - 115 . n  to adjust the delay. Each tap line corresponds to a different delay. When the XCLK and DLLCLK signals are synchronized, delay controller  110  stops adjusting the delay and locks the DLL to keep the XCLK and DLLCLK signals synchronized. 
       FIG. 2  shows an example of a timing diagram for  FIG. 1 . At time T 0 , delay controller  110  compares (COMPARE) the edges of the XCLK and CLKFB signals and detects a delay D. The presence of delay D indicates that the XCLK and DLLCLK signals are not synchronized. At time T 1 , delay controller  110  selects an appropriate tap to adjust (ADJUST) the delay applied by delay line  112  to change the timing of the DLLCLK and the CLKFB signals. Between times T 2  and T 4 , delay controller  110  compares the XCLK and CLKFB signals again to adjust the delay to reduce delay D. The comparison and adjustment process repeats between times T 4  and T 5 . At time T 5 , the XCLK and DLLCLK signals are synchronized. Delay controller  110  sets DLL  100  in a locked position. 
       FIG. 3  shows more detail of the DLL of  FIG. 1 . Delay line  112  includes a plurality of delay elements  302 . 1 - 302 . n , each connecting to a corresponding tap line among the tap lines  115 . 1 - 115 . n . Each delay element delays a signal for a unit time delay. The delay applied by delay line  112  equals the product of the unit time delay and the number of activated delay elements. When a delay element is activated, it toggles at each edge of the CLKIN signal, allowing the CLKIN signal to propagate through. The CLKIN becomes the CLKOUT signal after propagating through a certain number of activated delay elements. The CLKIN and CLKOUT signals have an equal cycle time. 
     Delay controller  110  includes a phase detector  304  and an adjusting unit  306 . Phase detector  304  compares the XCLK and CLKFB signals and activates shifting signals SR and SL when the XCLK and CLKFB signals are not synchronized. When activated, the SR or SL signal allows adjusting unit  306  to perform a shifting operation for selecting one of the tap lines  115 . 1 - 115 . n  to adjust a delay of delay line  112 . In some embodiments, adjusting unit  306  increases the delay when the SR signal is activated and decreases the delay when the SL signal is activated. In other embodiments, adjusting unit  306  acts in the opposite direction, decreasing the delay when the SR signal is activated and increasing the delay when the SL signal is activated. Adjusting unit  306  adjusts the delay until the SR and SL signals are deactivated and the XCLK and CLKFB signals are synchronized. 
     Delay model  114  is modeled after a combination of input and output cycle controllers  116  and  118  so that when the XCLK and CLKFB signals are synchronized, the XCLK and DLLCLK signals are also synchronized. Delay model  114  has a time delay equal to the sum of a time delay of input cycle controller  116  and a time delay of output cycle controller  118 . In some embodiments, delay model  114  has a construction that is identical to the combined constructions of input and output cycle controllers  116  and  118 . Since a combination of input and output cycle controllers  116  and  118  and delay model  114  have equal time delay, the CLKFB is a version of the DLLCLK signal. Thus, when the XCLK and CLKFB signals are synchronized, the XCLK and DLLCLK signals are also synchronized. 
     Input and output cycle controllers  116  and  118  form cycle control circuitry for controlling a cycle time of the CLKIN and DLLCLK signals. Input cycle controller  116  modifies the cycle time of the XCLK signal to control the cycle time of the CLKIN signal. Output cycle controller  118  modifies the cycle time of the CLKOUT signal to control the cycle time of the DLLCLK signal. 
     Input cycle controller  116  increases the cycle time of the XCLK signal such that the cycle time of the CLKIN signal is greater than the cycle time of the XCLK signal. In some embodiments, input cycle controller  116  increases the cycle time of the XCLK signal such that the cycle time of the CLKIN signal is a multiple of the cycle time of the XCLK signal. Since the cycle time of the CLKIN signal is greater than the cycle time of the XCLK signal, the number of edges of the CLKIN signal is less than the number of edges of the XCLK signal. Hence, the CLKIN signal causes the activated delay elements to toggle fewer times than the XCLK signal would. Thus, propagating the CLKIN signal instead of the XCLK signal into delay line  112  generates fewer number of toggles, thereby reducing the power consumption. 
     In some embodiments, output cycle controller  118  decreases the cycle time of the CLKOUT signal such that the cycle time of the DLLCLK signal is smaller than the cycle time of the CLKOUT signal. Since the CLKIN and CLKOUT have an equal cycle time, the cycle time of the DLLCLK signal is also smaller than the cycle time of the CLKIN signal. In some embodiments, output cycle controller  118  decreases the cycle time of the CLKOUT signal such that the cycle time of the DLLCLK signal is equal to the cycle time of the XCLK signal. 
       FIG. 4  is a timing diagram of various signals of the DLL of  FIG. 3 . For the purposes of comparison among the cycle times, the signals are lined up in  FIG. 4 . The XCLK and DLLCLK signals have an equal cycle time of T CK . The CLKIN and CLKOUT signals have an equal cycle time of xT CK. , where x is greater than one. Therefore, xT CK  is greater than T CK . In some embodiments, x is an integer. Thus, xT CK  is a multiple of T CK . In  FIG. 4 , x is two. Hence, xT CK  is twice T CK . 
     Since xT CK  is greater than T CK , the number of edges of the CLKIN signal is less than the number of edges of the XCLK signal within every cycle of the CLKIN signal. Therefore, propagating the CLKIN signal instead of the XCLK signal into delay line  112  generates fewer number of toggles. 
       FIG. 5  shows delay line  112  and adjusting unit  306  of  FIG. 3 . Adjusting unit  306  includes a shift register  504  having a plurality of register cells (R)  504 . 1 - 504 . n . Shift register  504  controls the contents of the register cells based on the SR and SL signals to activate the signals on tap lines  515 . 1 - 515 . n . A select logic circuit  506  has a plurality of latches (L)  508 . 1 - 508 . n , each connecting to a corresponding shift line. The signal on each shift line controls the content of a corresponding latch. Select logic circuit  506  selects tap lines  115 . 1 - 115 . n  based on the contents of latches  508 . 1 - 508 . n  to adjust the delay applied by delay line  112 . 
     The CLKOUT signal exits delay line  112  at a fixed exit point from the output of delay element  302 . n . The CLKIN signal is present at all of the delay elements, but only one of the delay elements allows it to enter at one entry point based on one of the selected tap lines  115 . 1 - 115 . n . For example, when tap line  115 . 3  is selected, delay element  302 . 3  allows the CLKIN signal to enter delay line  112  at an entry point E. The CLKIN signal propagates from delay element  302 . 3  to delay element  302 . n  and becomes the CLKOUT signal. The entry point E moves along the inputs of delay elements  302 . 1 - 302 . n  when adjusting unit  306  adjusts the delay. The entry point E remains at the same position while the XCLK and DLLCLK ( FIG. 3 ) are synchronized. 
     In the above example, delay elements  302 . 3  through  302 . n  are activated delay elements; they toggle at each edge of the CLKIN signal. The number of activated delay elements varies when the entry point E moves to a different position. The number of activated delay elements is fixed while the XCLK and DLLCLK are synchronized. 
       FIG. 6  shows a variation of the delay line and the adjusting unit of  FIG. 5 . Delay line  112  and adjusting unit  306  of  FIG. 5  and  FIG. 6  have similar elements. In  FIG. 6 , The CLKOUT signal exits delay line  112  at any one of the exit points from the outputs of delay elements  302 . 1 .- 302 . n  based on one of the selected tap lines  115 . 1 - 115 . n . The CLKIN signal enters delay line  112  at a fixed point at delay element  302 . 1 . For example, tap line  115 . 3  selects delay element  302 . 3  to allow the CLKOUT to exit delay line  112  at an exit point X. The CLKIN signal propagates from delay element  302 . 1  to delay element  302 . 3  and becomes the CLKOUT signal. The exit point X moves along the outputs of delay elements  302 . 1 - 302 . n  when adjusting unit  306  adjusts the delay. The exit point X remains at the same position while the XCLK and DLLCLK ( FIG. 3 ) are synchronized. 
     In the example in  FIG. 6 , delay elements  302 . 1  through  302 . 3  are activated delay elements and toggle at each edge of the CLKIN signal. The number of activated delay elements varies when the exit point X moves to a different position. The number of activated delay elements is fixed while the XCLK and DLLCLK are synchronized. 
       FIG. 7  shows a phase detector according to an embodiment of the invention. Phase detector  304  includes flip flops  702  and  704 , each having inputs D and CK and outputs Q and Q*. In some embodiments, flip flops  702  and  704  are D-Q flip flops. Input D of flip flop  702  receives the CLKFB signal and input D of flip flop  704  receives a delay version of the CLKFB signal through a delay  706 . Both outputs Q connect to an AND gate  708 . Both outputs Q* connect to an AND gate  710 . Both inputs CK of the flip flops receive the XCLK signal. In some embodiments, delay  706  has a delay equal to the delay of each of delay elements  302 . 1 - 302 . n  ( FIG. 3 ). 
     Flip flops  702  and  704 , delay  706 , and AND gates  708  and  710  form a comparator for comparing the XCLK and CLKFB signals to activate the SR and SL signals. The SR signal is activated when the rising edges of the XCLK and CLKFB signals are separated by more than 180 degrees and less than 360 degrees. The SL signal is activated when the rising edges of the XCLK and CLKFB signals are separated by more than zero degree and less than or equal to 180 degrees. 
       FIG. 8  shows an input cycle controller according to an embodiment of the invention. Input cycle controller  116  includes an input frequency modifier  802  and a selector  816 . Input frequency modifier  802  has a plurality of flip flops  814 . 1  through  814 . n  forming a frequency divider to divide the frequency of the XCLK signal. 
     Each of the flip flops  814 . 1 - 814 . n  has two input nodes CLK and D, and two output nodes Q and Q*. In some embodiments, each of the flip flops  814 . 1 - 814 . n  is a D-Q flip flop. Flip flops  814 . 1 - 814 . n  divide the XCLK signal into a plurality of selectable start signals CLKIN 1 -CLKINn, Each succeeding selectable start signal has a cycle time equal to twice the cycle time of the preceding selectable start signal. The CLKINn signal has a cycle time equaled to 2 n  times the cycle time of the XCLK signal, where n is the total number of flip flops  814 . 1 - 814 . n.    
     A selector  816  selects one of the CLKIN 1 -CLKINn signals as the CLKIN signal based on a combination of select signals SEL 1 -SELy. In some embodiments, selector  816  is a n:1 multiplexor. A programming circuit  818  sets the combination of the SEL 1 -SELy signals. Programming circuit  818  includes fuse devices, electrical fuse devices, laser fuse devices, storage elements, or other programmable elements. These elements are programmed to set a combination of the SEL 1 -SELy signals. 
       FIG. 9  is a timing diagram for  FIG. 8 . For clarity,  FIG. 9  shows only the CLKIN 1 , CLKIN 2 , CLKIN 3 , and CLKINn signals. The XCLK signal has a cycle time T CK . The CLKIN 1  signal has a cycle time equaled to 2 1  times T CK  (2 T CK ). The CLKIN 2  signal has a cycle time equaled to 2 2  times T CK  (4 T CK ). The CLKIN 3  signal has a cycle time equaled to 2 3  times T CK  (8 T CK ). The CLKINn has a cycle time of 2 n  times T CK . In embodiments represented by  FIG. 9 , the CLKIN signal is selected from the CLKIN 2  signal as an example. In other embodiments, the CLKIN signal can be selected from any one of the CLKIN 1 -CLKINn signals. 
       FIG. 10  shows an output cycle controller according to an embodiment of the invention. Output cycle controller  118  includes an output frequency modifier  1002  for modifying the frequency of the CLKOUT signal. Output frequency modifier  1002  has a delay component  1010  and an exclusive OR gate  1012  forming a frequency multiplier to multiply the frequency of the CLKOUT signal to generate the DLLCLK signal. The delay of delay component  1010  can be selected such that the cycle time of the DLLCLK signal is smaller than the cycle time of the CLKOUT signal. 
       FIG. 11  is a timing diagram for cycle controller  118  of  FIG. 10 . T CLKOUT  is the cycle time of the CLKOUT signal. T DLLCLK  is the cycle time of the DLLCLK signal; T DLLCLK  is smaller than T CLKOUT . T S  indicates a time that the DLLCLK signal is at a certain signal level. In  FIG. 11 , T S  indicates a time that the DLLCLK signal is high. In some embodiments, T S  indicates a time that the DLLCLK signal is low. 
     T S  can be adjusted by selecting the delay of delay component  1010  ( FIG. 10 ). In some embodiments, the delay of delay component  1010  is selected such that T S  is one-half of T DLLCLK  so that the DLLCLK signal has a 50% duty cycle. In other embodiments, the delay of delay component  1010  can be selected such that T S  equals a fraction of T DLLCLK  other than one-half T DLLCLK . 
       FIG. 12  shows an output cycle controller according to another embodiment of the invention. Output cycle controller  118  includes an output frequency modifier  1202  for modifying the frequency of the CLKOUT signal. Output frequency modifier  1202  has a plurality of delay components  1210 . 1 - 1210 .X and a plurality of exclusive OR gates  1212 . 1 - 1212 .X. These delay components and gates form a frequency multiplier for multiplying the frequency of the CLKOUT signal to generate a plurality of selectable internal signals DLLCLK 1 -DLLCLKX; each succeeding selectable internal signal has a cycle time that is less than the cycle time of the preceding selectable internal signal. The DLLCLKX signal has a cycle time equaled to (½ X ) times the cycle time of the CLKOUT signal, where X is the total number of gates  1212 . 1 - 1212 .X. 
     A selector  1216  selects one of the DLLCLK 1 -DLLCLKX signals as the DLLCLK signal based on a combination of select signals S 1 -Sm. In some embodiments, selector  1216  is a X:1 multiplexor. A programming circuit  1218  sets the combination of the S 1 -Sm signals. Programming circuit  1218  includes fuse devices, electrical fuse devices, laser fuse devices, storage elements, or other programmable elements. These elements are programmed to set a combination of the S 1 -Sm signals. 
       FIG. 13  is a timing diagram for  FIG. 12 . For clarity,  FIG. 13  shows only the DLLCK 1 , DLLCLK 2 , and DLLCLKX signals. The CLKOUT signal has a cycle time T CLKOUT . The DLLCLK 1  signal has a cycle time equaled to ½ T CLKOUT . The DLLCLK 2  signal has a cycle time equaled to ¼ T CLKOUT . The DLLCLKX signal has a cycle time equaled to ½ X  T CLKOUT . In embodiments represented by  FIG. 13 , the DLLCLK signal is selected from the DLLCLK 2  signal as an example. In this example, the cycle time of the DLLCLK signal, T DLLCLK , equals ¼ T CLKOUT . In other embodiments, the DLLCLK signal can be selected from any one of the DLLCLK 1 -DLLCLKX signals. 
     T S  indicates a time that the DLLCLK signal is at a certain signal level. T S  can be adjusted by selecting the delays of delay components  1210 . 1 - 1210 .X ( FIG. 12 ). For example, the delays of delay components  1210 . 1 - 1210 .X can be selected such that T S  is one-half of T DLLCLK  so that the DLLCLK signal has a 50% duty cycle. As another example, the delays of delay components  1210 . 1 - 1210 .X can be selected such that T S  equals a fraction of T DLLCLK  other than one-half T DLLCLK . 
       FIG. 14  shows a memory device according to an embodiment of the invention. Memory device  1400  includes a main memory  1402  having a plurality of memory cells arranged in rows and columns. The memory cells are grouped into a plurality of memory banks indicated by bank  0  through bank M. Row decode  1404  and column decode  1406  access the memory cells in response to address signals A 0  through AX (A 0 -AX) on address lines (or address bus)  1408 . A data input path  1414  and a data output path  1416  transfer data between banks  0 -M and data lines (or data bus)  1410 . Data lines  1410  carry data signals DQ 0  through DQN. A memory controller  1418  controls the modes of operations of memory device  1400  based on control signals on control lines  1420 . The control signals include, but are not limited to, a Chip Select signal CS*, a Row Access Strobe signal RAS*, a Column Access Strobe CAS* signal, a Write Enable signal WE*, and an external clock signal XCLK. 
     Memory device  1400  further includes a DLL  1415  having a delay line for receiving the XCLK signal to generate an internal signal DLLCLK. The DLLCLK signal serves as a clock signal to control a transfer of data on data output path  1416 . DLL  1415  includes cycle control circuitry for controlling the cycle time of the signal entering the delay and the cycle time of the signal exiting the delay line. DLL  1415  includes embodiments of DLL  100  ( FIG. 1  and  FIG. 3 ). 
     In some embodiments, memory device  1400  is a dynamic random access memory (DRAM) device. In other embodiments, memory device  1400  is a static random access memory (SRAM), or flash memory. Examples of DRAM devices include synchronous DRAM commonly referred to as SDRAM (synchronous dynamic random access memory), SDRAM II, SGRAM (synchronous graphics random access memory), DDR SDRAM (double data rate SDRAM), DDR II SDRAM, and Synchlink or Rambus DRAMs. Those skilled in the art recognize that memory device  1400  includes other elements, which are not shown for clarity. 
       FIG. 15  shows a system  1500  according to an embodiment of the invention. System  1500  includes a first integrated circuit (IC)  1502  and a second IC  1504 . IC  1502  and IC  1504  can include processors, controllers, memory devices, application specific integrated circuits, and other types of integrated circuits. In  FIG. 15 , IC  1502  represents a processor and IC  1504  represents a memory device. Processor  1502  and memory device  1504  communicate using address signals on lines  1508 , data signals on lines  1510 , and control signals on lines  1520 . 
     Memory device  1504  includes embodiments of memory device  1400  ( FIG. 14 ) including DLL  1415 , which corresponds to DLL  100  ( FIG. 1  and  FIG. 3 ). 
     System  1500  includes computers (e.g., desktops, laptops, hand-helds, servers, Web appliances, routers, etc.), wireless communication devices (e.g., cellular phones, cordless phones, pagers, personal digital assistants, etc.), computer-related peripherals (e.g., printers, scanners, monitors, etc.), entertainment devices (e.g., televisions, radios, stereos, tape and compact disc players, video cassette recorders, camcorders, digital cameras, MP3 (Motion Picture Experts Group, Audio Layer 3) players, video games, watches, etc.), and the like. 
     CONCLUSION 
     Various embodiments of the invention provide circuits and methods to operate a DLL more efficiently. In one aspect, the DLL includes a forward path for receiving an external signal to generate an internal signal. The forward path includes a delay line for applying a delay to an input signal derived from the external signal to output an output signal. An input cycle controller controls a time interval between edges of the input signal. An output cycle controller modifies a time interval between edges of the output signal. The DLL also includes a feedback path and a delay controller. The feedback path provides a feedback signal derived from the output signal. The delay controller adjusts the delay based on the feedback and input signals to synchronize the external and internal signals. In another aspect, a method of processing signals includes modifying a cycle time of an external signal to produce an input signal. The method also applies a delay to the input signal to produce an output signal. An internal signal is generated based on the output signal. The method further adjusts the delay to synchronize the external and internal signals. Other embodiments are described and claimed. 
     Although specific embodiments are described herein, those skilled in the art recognize that other embodiments may be substituted for the specific embodiments shown to achieve the same purpose. This application covers any adaptations or variations of the embodiments of the invention. Therefore, the embodiments of the invention are limited only by the claims and all available equivalents.