Patent Publication Number: US-2023163031-A1

Title: Fin field effect transistor (finfet) device structure with dummy fin structure

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This application is a Continuation application of U.S. patent application Ser. No. 17/031,023, filed on Sep. 24, 2020, which is a Continuation application of U.S. patent application Ser. No. 16/730,320, filed on Dec. 30, 2019, which is a Divisional application of U.S. patent application Ser. No. 15/692,768, filed on Aug. 31, 2017, the entire of which is incorporated by reference herein. 
    
    
     BACKGROUND 
     Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic equipment. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductive layers of material over a semiconductor substrate, and patterning the various material layers using lithography to form circuit components and elements thereon. Many integrated circuits are typically manufactured on a single semiconductor wafer, and individual dies on the wafer are singulated by sawing between the integrated circuits along a scribe line. The individual dies are typically packaged separately, in multi-chip modules, or in other types of packaging, for example. 
     As the semiconductor industry has progressed into nanometer technology process nodes in pursuit of higher device density, higher performance, and lower costs, challenges from both fabrication and design issues have resulted in the development of three-dimensional designs, such as the fin field effect transistor (FinFET). FinFETs are fabricated with a thin vertical “fin” (or fin structure) extending from a substrate. The channel of the FinFET is formed in this vertical fin. A gate is provided over the fin. Advantages of the FinFET may include reducing the short channel effect and higher current flow. 
     Although existing FinFET devices and methods of fabricating FinFET devices have been generally adequate for their intended purpose, they have not been entirely satisfactory in all aspects. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It should be noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. 
         FIGS.  1 A- 1 E  show three-dimensional representations of forming a fin field effect transistor (FinFET) device structure, in accordance with some embodiments of the disclosure. 
         FIGS.  2 A- 2 H  show cross-sectional representations of forming a fin field effect transistor (FinFET) device structure, in accordance with some embodiments of the disclosure. 
         FIG.  3    shows a three-dimensional representation of the fin field effect transistor (FinFET) device structure of  FIG.  2 H . 
         FIGS.  4 A- 4 D  show cross-sectional representations of forming a fin field effect transistor (FinFET) device structure, in accordance with some embodiments of the disclosure. 
         FIGS.  5 A- 5 D  show cross-sectional representations of forming a fin field effect transistor (FinFET) device structure, in accordance with some embodiments of the disclosure. 
         FIGS.  6 A- 6 D  show cross-sectional representations of forming a fin field effect transistor (FinFET) device structure, in accordance with some embodiments of the disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. 
     Some variations of the embodiments are described. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements. It is understood that additional operations can be provided before, during, and after the method, and some of the operations described can be replaced or eliminated for other embodiments of the method. 
     Embodiments for forming a fin field effect transistor (FinFET) device structure are provided.  FIGS.  1 A- 1 E  show three-dimensional representations of forming a fin field effect transistor (FinFET) device structure, in accordance with some embodiments of the disclosure. 
     As shown in  FIG.  1 A , the FinFET device structure includes a substrate  102 . The substrate  102  includes a first region  11  and a second region  12 . The substrate  102  may be made of silicon or other semiconductor materials. Alternatively or additionally, the substrate  102  may include other elementary semiconductor materials such as germanium. In some embodiments, the substrate  102  is made of a compound semiconductor such as silicon carbide, gallium arsenic, indium arsenide, or indium phosphide. In some embodiments, the substrate  102  is made of an alloy semiconductor such as silicon germanium, silicon germanium carbide, gallium arsenic phosphide, or gallium indium phosphide. In some embodiments, the substrate  102  includes an epitaxial layer. For example, the substrate  102  has an epitaxial layer overlying a bulk semiconductor. 
     In some embodiments, a well portion (not shown) may be formed on the substrate  102  in the first region  11  or the second region  12 . An ion implantation process is performed on the substrate  102  form the well portion. In some embodiments, the well portion may be doped with arsenic (As) or phosphorous (P) ions to form the N-well portion. In some embodiments, the well portion is doped with boron (B) ions to form the P-well portion. 
     Afterwards, a dielectric layer  104  and a mask layer  106  are formed over the substrate  102 , and a photoresist layer  108  is formed over the mask layer  106 . The photoresist layer  108  is patterned by a patterning process. The patterning process includes a photolithography process and an etching process. The photolithography process includes photoresist coating (e.g., spin-on coating), soft baking, mask aligning, exposure, post-exposure baking, developing the photoresist, rinsing and drying (e.g., hard baking). The etching process may include a dry etching process or a wet etching process. 
     The dielectric layer  104  is a buffer layer between the substrate  102  and the mask layer  106 . In addition, the dielectric layer  104  is used as a stop layer when the mask layer  106  is removed. The dielectric layer  104  may be made of silicon oxide. The mask layer  106  may be made of silicon oxide, silicon nitride, silicon oxynitride, or another applicable material. In some other embodiments, more than one mask layer  106  is formed over the dielectric layer  104 . 
     The dielectric layer  104  and the mask layer  106  are formed by deposition processes, such as a chemical vapor deposition (CVD) process, a high-density plasma chemical vapor deposition (HDPCVD) process, a spin-on process, a sputtering process, or another applicable process. 
     Afterwards, as shown in  FIG.  1 B , after the photoresist layer  108  is patterned, the dielectric layer  104  and the mask layer  106  are patterned by using the patterned photoresist layer  108  as a mask, in accordance with some embodiments. As a result, a patterned dielectric layer  104  and a patterned mask layer  106  are obtained. Afterwards, the patterned photoresist layer  108  is removed. 
     Afterwards, an etching process is performed on the substrate  102  to form a number of first fin structures  110   a , and a number of second fin structures  110   b  by using the patterned dielectric layer  104  and the patterned mask layer  106  as a mask. The first fin structures  110   a  are formed in the first region  11 . The second fin structures  110   b  are formed in the second region  12 . 
     In some embodiments, each of the first fin structures  110   a  and each of the second fin structures  110   b  has a width that gradually increases from the top portion to the bottom portion. In other words, each of the first fin structures  110   a  and each of the second fin structures  110   b  has a tapered fin width which tapers gradually from the bottom portion to the top portion. 
     The etching process may be a dry etching process or a wet etching process. In some embodiments, the substrate  102  is etched using a dry etching process. The dry etching process includes using a fluorine-based etchant gas, such as SF 6 , C x F y , NF 3  or a combination thereof. The etching process may be a time-controlled process, and continue until the first fin structures  110   a  and the second fin structures  110   b  reach a predetermined height. 
     As shown in  FIG.  1 C , after the first fin structures  110   a  and the second fin structures  110   b  are formed, a liner layer  112  is formed on the first fin structures  110   a  and the second fin structures  110   b . More specifically, the liner layer  112  is conformally formed on the sidewall surfaces, top surface of the first fin structures  110   a , the second fin structures  110   b  and on the mask layer  106 . 
     The liner layer  112  is used to protect the first fin structures  110   a , the second fin structures  110   b  from being damaged by the following processes (such as an anneal process or an etching process). Therefore, the profiles or shapes of the first fin structures  110   a  and the second fin structures  110   b  are maintained or preserved by the protection of the liner layer  112 . In some embodiments, the liner layer  112  has a thickness in a range from about 2 nm to about 5 nm. 
     In some embodiments, the liner layer  112  is made of silicon nitride (SixNy). In some embodiments, the liner layer  112  is not made of oxide, such as silicon oxide. If the liner layer  112  made of silicon oxide, the liner layer  112  is not robust enough to protect the first fin structures  110   a  and the second fin structures  110   b , especially when the first fin structures  110   a , the second fin structures  110   b , include silicon germanium (SiGe). 
     Afterwards, as shown in  FIG.  1 D , an isolation layer  114  is formed to cover the first fin structures  110   a  and the second fin structures  110   b  over the substrate  102 , in accordance with some embodiments. 
     In some embodiments, the isolation layer  114  is made of silicon oxide, silicon nitride, silicon oxynitride, fluoride-doped silicate glass (FSG), or another low-k dielectric material. The isolation layer  114  may be deposited by a deposition process, such as a chemical vapor deposition (CVD) process, a spin-on-glass process, or another applicable process. 
     In some embodiments, the isolation layer  114  is formed by a flowable chemical vapor deposition (FCVD) process. The isolation layer  114  is solidified by a UV curing process. Afterwards, an annealing process is performed on the isolation layer  114  to improve the quality of the isolation layer  114 . In some embodiments, the annealing process is performed at a temperature in a range from about 400 degrees to about 700 degrees. The patterned mask layer  106  and the liner layer  112  both are used to protect the substrate  102  from being damaged during the annealing process, and therefore the profiles of the top portion of the first fin structures  110   a  and the second fin structures  110   b  are not damaged by the high temperature. 
     Next, as shown in  FIG.  1 E , the isolation layer  114  is thinned or planarized to expose the top surface of the patterned mask layer  106 , in accordance with some embodiments. In some embodiments, the isolation layer  114  is thinned by a chemical mechanical polishing (CMP) process. 
       FIGS.  2 A- 2 H  show cross-sectional representations of forming a fin field effect transistor (FinFET) device structure, in accordance with some embodiments of the disclosure.  FIG.  2 A  is cross-sectional representation taken along a-a′ line of  FIG.  1 E .  FIGS.  2 B- 2 H  show subsequent fabrication steps after the step of  FIG.  1 E . 
     As shown in  FIG.  2 A , after the planarizing process, the top surface of the patterned mask layer  106  is level with the top surface of the isolation layer  114 . 
     Afterwards, as shown in  FIG.  2 B , a photoresist layer  210  is formed over the patterned mask layer  106 , the isolation layer  114  and the liner layer  112 , in accordance with some embodiments of the disclosure. The photoresist layer  210  includes a bottom anti-reflective coating (BARC) layer  202 , a middle layer  204  and a top layer  206 . Afterwards, the top layer  206  is patterned to form a patterned top layer  206 . 
     In some embodiments, the BARC layer  202  is made of silicon oxynitride (SiON), silicon rich oxide, or silicon oxycarbide (SiOC). In some embodiments, the middle layer  204  is made of silicon nitride, silicon oxynitride or silicon oxide. In some embodiments, the top layer  206  is made of Poly (methyl methacrylate) (PMMA), Poly (methyl glutarimide) (PMGI), Phenol formaldehyde resin (DNQ/Novolac) or SU-8. 
     Next, as shown in  FIG.  2 C , the middle layer  204 , the BARC layer  202  are patterned by using the patterned top layer  206  as the mask layer to form a patterned middle layer  204  and a patterned BARC layer  202 , in accordance with some embodiments of the disclosure. A portion of the patterned mask layer  106  and a portion of the patterned dielectric layer  104  are removed to form a recess  115 . The recess  115  is directly above the top surface of the second fin structures  110   b  in the second region  12 . Afterwards, the patterned photoresist layer  210  is removed. 
     Afterwards, as shown in  FIG.  2 D , a portion of the second fin structures  110   b  is removed along the recess  115  to form a trench  117 , in accordance with some embodiments of the disclosure. As a result, the second fin structures  110   b  in the second region  12  are lower than the first fin structures  110   a  in the first region  11 . Since most of the second fin structures  110   b  is removed, the second fin structures  110   b  are called as dummy second fin structures  110   b . The dummy second fin structures  110   b  do not perform any function. 
     The trench  117  has a tapered width from bottom to top. The bottom surface of the trench  117  has a concave surface, and the concave surface has a lowest point at the middle portion. The liner layer  112  is not removed and remaining on sidewalls of the trench  117 . 
     When a portion of the second fin structures  110   b  is removed, the liner layer  112  and the patterned mask layer  106  are not removed since the liner layer  112  is made of a higher etching resistant material with respect to the second fin structures  110   b.    
     The term of “selectivity” or “etching selectivity” is defined as the ratio of etching rate of one material (the reference material) relative to another material (the material of interest). An increase in etch selectivity means that the selected material, or material of interest, is harder to etch. A decrease in etch selectivity means that the selected material is easier to etch. The etching selectivity of the liner layer  112  with respect to the second fin structures  110   b  is high, and therefore the second fin structures  110   b  are removed by the etching process while the liner layer  112  is not removed. 
     The trench  117  has a depth D 1  which is measured from a top surface of the isolation layer  114  to a bottom surface of the trench  117 . The lowest point of the trench  117  is lower than the top surface of the isolation structure  140  (shown in  FIG.  2 G ). The trench  117  will be filled with a filling layer  118  (shown in  FIG.  2 G ), and the dummy second fin structures  110   b  are covered by the filling layer  118 . In some embodiments, the depth D 1  of the trench  117  is within a range from about 110 nm to about 120 nm. When the depth D 1  of the trench  117  is within the above-mentioned range, isolation effect is improved, and the S/D structure (formed later) will not be formed from the remaining second fin structures  110   b.    
     Next, as shown in  FIG.  2 E , a filling layer  118  is formed in the trench  117  and on the patterned mask layer  106 , in accordance with some embodiments of the disclosure. The filling layer  118  and the isolation layer  114  are made of different materials. In addition, the filling layer  118  and the second fin structures  110   b  are made of different materials. Therefore, there is a distinguishable interface between the top surface of the second fin structures  110   b  and the bottom surface of the filling layer  118 . 
     In some embodiments, the filling layer  118  is made of silicon nitride, silicon oxynitride (SiON) or a combination thereof. In some embodiments, the filling layer  118  is formed by a deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or another applicable process. 
     Afterwards, as shown in  FIG.  2 F , the filling layer  118  and the patterned mask layer  106  are thinned or planarized to expose the top surface of each of the dielectric layer  104 , in accordance with some embodiments. In some embodiments, the filling layer  118  and the patterned mask layer  106  are thinned by a chemical mechanical polishing (CMP) process. 
     Since the trench  117  has a high aspect ratio, the trench  117  is hard to be completely filled with the filling layer  118 . Therefore, a void  121  is formed in a bottom portion of the filling layer  118 . The void  121  is enclosed by the filling layer  118 . 
     Next, as shown in  FIG.  2 G , the patterned dielectric layer  104  is removed, and then an upper portion of the isolation layer  114 , an upper portion of the liner layer  112  and an upper portion of the filling layer  118  are simultaneously removed by an etching process, in accordance with some embodiments. As a result, an isolation structure  140  is obtained. The first fin structures  110   a  extend above the top surface of the isolation structure  140 , but the second fin structures  110   b  is below the top surface of the isolation structure  140 . 
     In some embodiments, the liner layer  112  is made of silicon nitride (SixNy), the filling layer  118  is made of silicon oxynitride (SiON), and there is a distinguishable interface between the liner layer  112  and the filling layer  118 . 
     The etching selectivity of the filling layer  118  with respect to the isolation layer  114  is slightly high, and therefore the remaining filling layer  118  protrudes above the top surface of the isolation structure  140 . In other words, the top surface of the filling layer  118  is higher than the top surface of the isolation structure  140  after the etching process. 
     Each of the first fin structures  110   a  has a width W 1  and a fin height H 1 . There is a space S 1  between two adjacent first fin structures  110   a . In some embodiments, the width W 1  is in a range from about 5 nm to about 10 nm. In some embodiments, the fin height H 1  is in a range from about 50 nm to about 60 nm. In some embodiments, the space S 1  is in a range from about 15 nm to about 25 nm. 
     Next, as shown in  FIG.  2 H , a dummy gate dielectric layer  160  and a dummy gate electrode layer  162  are formed on the isolation structure  140 , the filling layer  118  and the liner layer  112 , in accordance with some embodiments.  FIG.  3    shows a three-dimensional representation of the fin field effect transistor (FinFET) device structure of  FIG.  2 H .  FIG.  2 H  is cross-sectional representation taken along b-b′ line of  FIG.  3   . 
     As shown in  FIG.  2 H  and  FIG.  3   , the dummy gate structure  170  is formed on the middle portion of the first fin structures  110   a . The middle portion of the first fin structures  110   a  which is surrounded or wrapped by the dummy gate structure  170  is the channel region. The dummy gate dielectric layer  160  is formed between the liner layer  112  and the dummy gate electrode layer  162 . 
     In some embodiments, the dummy gate dielectric layer  160  is made of dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, dielectric material with high dielectric constant (high-k), or a combination thereof. The dummy gate dielectric layer  160  is formed by a deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), high density plasma CVD (HDPCVD), metal organic CVD (MOCVD), or plasma enhanced CVD (PECVD). 
     In some embodiments, the dummy gate electrode layer  162  is made of conductive or non-conductive materials. In some embodiments, the dummy gate electrode layer  162  is made of polysilicon. The dummy gate electrode layer  162  is formed by a deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), high density plasma CVD (HDPCVD), metal organic CVD (MOCVD), or plasma enhanced CVD (PECVD). 
     Afterwards, a portion of the first fin structures  110   a  adjacent to the dummy gate structure  170  is removed to form a recess (not shown), and a source/drain (S/D) structure is formed in the recess. In some embodiments, the source/drain structures include silicon germanium (SiGe), germanium (Ge), indium arsenide (InAs), indium gallium arsenide (InGaAs), indium antimonide (InSb), gallium arsenide (GaAs), gallium antimonide (GaSb), indium aluminum phosphide (InAlP), indium phosphide (InP), or a combination thereof. 
     Afterwards, the ILD structure (not shown) is formed on the dummy gate structure  170  and the source/drain structures. Next, the dummy gate structure  170  is removed to form a trench, and a gate dielectric layer and a gate electrode layer are formed in the trench. In some embodiments, the gate dielectric layer is made of high-k dielectric layer and the gate electrode layer is made of metal gate electrode layer. As a result, the high-k gate dielectric layer is over the filling layer  118 , and a distinguishable interface between the high-k gate dielectric layer  118  and the filling layer since the high-k gate dielectric layer and the filling layer  118  are made of different materials. Note that the trench is not completely filled with the high-k gate dielectric layer, and a void is in the trench. 
     It should be noted that when the annealing process is performed on the isolation layer  114  (in  FIG.  1 D ), the deformations of existing fin structures occur. For example, the isolation layer  114  may shrink after the annealing process, and the space between fin structures may be reduced. If a portion of the fin structures is removed before the annealing process (e.g. fin removal process is performed before the annealing process), the space between every two adjacent fin structures may be different. The different space may cause fin bending. In this embodiment, the fin removal process is performed after the annealing process, and therefore the space between every two adjacent fin structures is maintained, and the performance of the FinFET device structure is improved. 
     If a portion of the fin structures are removed before formation of isolation layer is called as a fin cut first process. The fin cut first process is formed by using a number of the photoresist strips with uneven space. When the underlying layers (e.g. the dielectric layer, the mask layer and the substrate) are etched by using the patterned photoresist layer as a mask, the fin structures will have different fin widths due to the loading effect. In contract to the fin cut first process, the fin cut last process is used in this disclosure. The patterned photoresist layer  108  with a number of photoresist strips with a regular space are formed first, and then the first fin structures  110   a  and the second fin structures  110   b  are formed by using the patterned photoresist layer  108  as a mask. Therefore, each of the first fin structures  110   a  and the second fin structures  110   b  has a regular fin width and fin size. Afterwards, a top portion of the second fin structures  110   b  are removed to form the dummy second fin structures  110   b . Therefore, variation in fin width is reduced. Furthermore, the performance of the fin field effect transistor (FinFET) device structure is improved. 
       FIGS.  4 A- 4 D  show cross-sectional representations of forming a fin field effect transistor (FinFET) device structure, in accordance with some embodiments of the disclosure. Some processes and materials used to form the FinFET device structure in  FIGS.  4 A- 4 D  are similar to, or the same as, those used to form the FinFET structure in  FIGS.  2 A- 2 H  and are not repeated herein. 
     The structure of  FIG.  4 A  is similar to the structure of  FIG.  2 A , the difference is that the top portions of the first fin structures  110   a  and the top portions of the second fin structures  110   b  are replaced by the material layer  103  in  FIG.  4 A . 
     As shown in  FIG.  4 A , each of the first fin structures  110  and each of the second fin structures  110   b  has a top portion and a bottom portion. The top portion is made of material layer  103 . 
     The material layer  103  is formed over the substrate  102 , and the material layer  103  and the substrate  102  are made of different materials. In some embodiments, the material layer  103  is made of silicon germanium (SiGe), and the substrate  102  is made of silicon (Si). The material layer  103  is formed by an epitaxial process. The epitaxial process may include a selective epitaxy growth (SEG) process, CVD deposition techniques (e.g., vapor-phase epitaxy (VPE) and/or ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy, or other suitable epi processes. 
     It should be noted that when the material layer  103  is made of silicon germanium (SiGe), silicon germanium (SiGe) is easily oxidized to form germanium oxide (GeOx) during the subsequent annealing process. Once the germanium oxide (GeOx) is formed, it is easily removed by the etching process. Therefore, the liner layer  112  is formed on sidewalls of each of the top portion of the first fin structures  110   a  and the second fin structures  110   b  to protect the material layer  103  from being damaged by the subsequent processes. Furthermore, the profiles of the top portion of the first fin structures  110  and the second fin structures  110   b  may be preserved. 
     Afterwards, as shown in  FIG.  4 B , a portion of the patterned mask layer  106 , a portion of patterned dielectric layer  104 , a portion of the second fin structure  110   b  are removed to form the trench  117 , in accordance with some embodiments of the disclosure. Although the portion of the second fin structure  110   b  is removed, the liner layer  112  is not removed since the liner layer  112  has a higher etching resistance. Therefore, the liner layer  112  is exposed by the trench  117 . The trench  117  has a tapered width from bottom to top. 
     The bottom surface of the trench  117  is lower than the interface between the top portion (made of material layer  103 ) and the bottom portion of each of the first fin structures  110   a . In other words, the top surface of each of the second fin structures  110   b  is lower than the interface between the top portion and the bottom portion of the first fin structures  110   a.    
     Afterwards, as shown in  FIG.  4 C , the trench  117  is filled with the filling layer  118 , and a top portion of the filling layer  118  is removed, in accordance with some embodiments of the disclosure. In addition, the patterned mask layer  106 , the patterned dielectric layer  104 , and a portion of the isolation layer  114  are sequentially removed. 
     The top surface of the filling layer  118  is higher than the interface between the top portion and the bottom portion of each of the first fin structures  110   a . Since the trench  117  is not completely filled with the filling layer  118 , the void  121  is formed in the trench  117 . 
     Next, as shown in  FIG.  4 D , the dummy gate dielectric layer  160  and the dummy gate electrode layer  162  are formed on the isolation structure  140  and the liner layer  112 , in accordance with some embodiments. Afterwards, the FinFET device structure continues to form other devices. 
       FIGS.  5 A- 5 D  show cross-sectional representations of forming a fin field effect transistor (FinFET) device structure, in accordance with some embodiments of the disclosure. Some processes and materials used to form the FinFET device structure in  FIGS.  5 A- 5 D  are similar to, or the same as, those used to form the FinFET structure in  FIGS.  2 A- 2 H  and are not repeated herein. 
     As shown in  FIG.  5 A , the isolation structure  140  is formed by forming an isolation layer over the first fin structures  110   a , the second fin structures  110   b , performing an annealing process and a removing process. The first fin structures  110   a , the second fin structures  110   b  extend above the isolation structure  140 . The liner layer  112  is formed on sidewalls of the bottom portion of the first fin structures  110   a , the second fin structures  110   b . A number of trenches  111  are formed between two adjacent fin structures  110   a ,  110   b.    
     Afterwards, as shown in  FIG.  5 B , the photoresist layer  210  is formed in the trenches  111 , and over the patterned mask layer  106  and the liner layer  112 , in accordance with some embodiments of the disclosure. The photoresist layer  210  includes the bottom anti-reflective coating (BARC) layer  202 , the middle layer  204  and the top layer  206 . Afterwards, the top layer  206  is patterned to form a patterned top layer  206 . 
     Next, as shown in  FIG.  5 C , the middle layer  204  and the top layer  206  are patterned by using the patterned top layer  206  as a mask, in accordance with some embodiments of the disclosure. Next, a portion of the second fin structures  110   b  is removed to form a recess  119 . The recess  119  is formed on the top surface of each of the second fin structures  110   b , and the recess  119  is lower than a top surface of the isolation structure  140 . Since most of the second fin structures  110   b  is removed, the second fin structures  110   b  are called as dummy fin structures  110   b.    
     The recess  119  has a concave top surface, and the concave top surface has a middle lowest point. The recess  119  has a depth D 2  which is measured from the top surface of the isolation structure  140  to a bottom surface of the recess  119 . The lowest point of the recess  119  is lower than the top surface of the isolation structure  140 . In some embodiments, the depth D 2  of the recess  119  is in a range from about 15 nm to about 20 nm. If the depth D 2  of the recess  119  is smaller than 15 nm, the S/D structure may be formed in the recess  119  to degrade the performance of the FinFET device structure. If the depth D 2  of the recess  119  is greater than 20 nm, it is difficult to fill the dummy gate dielectric layer  160  (formed later) into the recess  119 . 
     Afterwards, as shown in  FIG.  5 D , the dummy gate dielectric layer  160  and the dummy gate electrode layer  162  are formed in the recess  119 , and on the isolation structure  140  and the liner layer  112 , in accordance with some embodiments. 
     The dummy gate dielectric layer  160  and the isolation structure  140  are made of different materials. In some embodiments, the dummy gate dielectric layer  160  is made of silicon oxynitride, the isolation structure  140  is made of silicon oxide, and there is a distinguishable interface between the dummy gate dielectric layer  160  and the isolation structure  140 . 
     The recess  119  is filled with the gate dielectric layer  160 , but it is not completely filled with the gate dielectric layer  160 . Therefore, the void  121  is formed in the recess  119 . The dummy gate dielectric layer  160  includes a first portion which is directly over the first fin structures  110   a  and a second portion which is directly over the second fin structures  110   b , and the second portion is lower than the first portion. 
     Afterwards, the ILD structure (not shown) is formed on the dummy gate structure  170  and the source/drain structures. Next, the dummy gate structure  170  is removed to form a trench, and a high-k gate dielectric layer dielectric layer and a metal gate electrode layer are formed in the trench. As a result, the recess  119  is filled with the high-k dielectric layer, and there is a distinguishable interface between the high-k gate dielectric layer and the isolation structure  140 . 
     In this embodiment, the first fin structures  110   a  and the second fin structures  110   b  are first formed, and then a portion of the second fin structures  110   b  is removed to form the dummy second fin structures  110   b . Since the first fin structures  110   a  and the second fin structures  110   b  are formed with regular fin width and fin size, the first fin structures  110   a  still have constant fin width after the portion of the second fin structures  110   b  is removed. Therefore, the variation in fin width is reduced. Furthermore, the second fin structures  110   b  is removed after the annealing process for the isolation layer  114 , and therefore the space between every two adjacent fin structures is maintained. Therefore, the performance of the fin field effect transistor (FinFET) device structure is improved. 
       FIGS.  6 A- 6 D  show cross-sectional representations of forming a fin field effect transistor (FinFET) device structure, in accordance with some embodiments of the disclosure. Some processes and materials used to form the FinFET device structure in  FIGS.  6 A- 6 D  are similar to, or the same as, those used to form the FinFET structure in  FIGS.  2 A- 2 H  and are not repeated herein. 
     The structure of  FIG.  6 A  is similar to the structure of  FIG.  5 A , the difference is that the top portions of the first fin structures  110   a  and the top portions of the second fin structures  110   b  are replaced by the material layer  103  in  FIG.  6 A . 
     As shown in  FIG.  6 A , each of the first fin structures  110  and each of the second fin structures  110   b  has a top portion and a bottom portion. The top portion is made of material layer  103 . In some embodiments, the material layer  103  is made of silicon germanium (SiGe), and the substrate  102  is made of silicon (Si). A number of trenches  111  are formed between two adjacent fin structures  110   a ,  110   b.    
     Next, as shown in  FIG.  6 B , the photoresist layer  210  is formed in the trenches  111 , and over the patterned mask layer  106  and the liner layer  112 , in accordance with some embodiments of the disclosure. The top layer  206  is patterned to form a patterned top layer  206 . 
     Next, as shown in  FIG.  6 C , the middle layer  204  and the top layer  206  are patterned by using the patterned top layer  206  as a mask, in accordance with some embodiments of the disclosure. Next, a portion of the second fin structures  110   b  is removed to form the recess  119 . The recess  119  is formed on the top surface of each of the second fin structures  110   b , and the recess  119  is lower than the top surface of the isolation structure  140 . The recess  119  is lower than the interface between the top portion and the bottom portion of each of the first fin structures  110   a.    
     Afterwards, as shown in  FIG.  6 D , the dummy gate dielectric layer  160  and the dummy gate electrode layer  162  are formed in the recess  119 , and on the isolation structure  140  and the liner layer  112 , in accordance with some embodiments. 
     The first fin structures  110   a  and the second fin structures  110   b  are formed first, and then a top portion of the second fin structures  110   b  is removed to form the dummy fin structures  110   b . A material layer (such as filling layer  118  or the dummy gate dielectric layer  160 ) is formed over the dummy second fin structures  110   b , and the material layer and the isolation structure are made of different materials. In some embodiments, as shown in  FIG.  2 H , the filling layer  118  is directly formed on the dummy second fin structures  110   b , and the filling layer  118  extends above the top surface of the isolation structure  140 . In some other embodiments, as shown in  FIG.  5 D , the gate dielectric layer  160  is directly formed on the dummy second fin structures  110   b.    
     Embodiments for forming a fin field effect transistor (FinFET) device structure are provided. A number of first fin structures and a number of second fin structures are formed, and then a portion of the second fin structures are removed by a removal process to form the dummy second fin structures. The removal process is performed after an annealing process on the isolation layer. Therefore, the space between every two adjacent fin structures is maintained. In addition, each of the first fin structures and the second fin structures has a regular fin width before the removal process. The variation in fin width is reduced. Therefore, the performance of the fin field effect transistor (FinFET) device structure is improved. 
     In some embodiments, a fin field effect transistor (FinFET) device structure is provided. The FinFET device structure includes an isolation structure over a substrate, and a first fin structure extended above the isolation structure. The FinFET device structure includes a second fin structure embedded in the isolation structure, and a liner layer formed on sidewalls of the first fin structures and sidewalls of the second fin structures. The FinFET device structure includes a material layer formed over the second fin structures, and the material layer and the isolation structure are made of different materials. 
     In some embodiments, a fin field effect transistor (FinFET) device structure is provided. The FinFET device structure includes an isolation structure over a substrate, and a first fin structure extended above the isolation structure. The FinFET device structure also includes a second fin structure, and a top surface of the second fin structure is lower than a top surface of the isolation structure. The FinFET device structure includes a material layer formed over the second fin structures, and the material layer has a tapered with form bottom to top. 
     In some embodiments, a fin field effect transistor (FinFET) device structure is provided. The FinFET device structure includes an isolation structure over a substrate, and a first fin structure extended above the isolation structure. The FinFET device structure also includes a second fin structure, and a top surface of the second fin structure is lower than a top surface of the isolation structure. The FinFET device structure includes a gate dielectric layer formed over the second fin structure, and a portion of the gate dielectric layer has a recessed bottom surface. 
     In some embodiments, a fin field effect transistor (FinFET) device structure is provided. The fin field effect transistor (FinFET) device structure includes an isolation structure over a substrate, and a first fin structure extended above the isolation structure. The fin field effect transistor (FinFET) device structure includes a second fin structure adjacent to the first fin structure, and a material layer formed over the fin structure. The material layer and the isolation structure are made of different materials, the material layer has a top surface with a top width and a bottom surface with a bottom width, and the bottom width is greater than the top width. 
     In some embodiments, a fin field effect transistor (FinFET) device structure is provided. The fin field effect transistor (FinFET) device structure includes a first fin structure formed over a substrate, and a second fin structure adjacent to the first fin structure. A top surface of the second fin structure is lower than a top surface of the isolation structure. The fin field effect transistor (FinFET) device structure includes a material layer formed over the second fin structure, and the top surface of the material layer is lower than a top surface of the first fin structure. 
     In some embodiments, a fin field effect transistor (FinFET) device structure is provided. The fin field effect transistor (FinFET) device structure includes an isolation structure over a substrate, and a first fin structure extended above the isolation structure. The fin field effect transistor (FinFET) device structure includes a second fin structure adjacent to the first fin structure, and a top surface of the second fin structure is lower than a top surface of the isolation structure. The fin field effect transistor (FinFET) device structure includes a material layer formed over the second fin structure, wherein a sidewall of the material layer does not extend beyond a sidewall of the second fin structure. 
     In some embodiments, a fin field effect transistor (FinFET) device structure is provided. The fin field effect transistor (FinFET) device structure includes an isolation structure over a substrate. The fin field effect transistor (FinFET) device structure includes a first fin structure formed above the isolation structure, and a second fin structure adjacent to the first fin structure. The fin field effect transistor (FinFET) device structure includes a filling layer forming on the second fin structure, and a top surface of the isolation structure is higher than a top surface of the second fin structure and lower than a top surface of the filling layer. 
     In some embodiments, a fin field effect transistor (FinFET) device structure is provided. The fin field effect transistor (FinFET) device structure includes a first fin structure formed over a substrate, and the first fin structure includes a top portion and a bottom portion, the top portion and the bottom portion made of different materials and an interface between the top portion and the bottom portion. The fin field effect transistor (FinFET) device structure includes a second fin structure adjacent to the first fin structure, and a filling layer formed over and in direct contact with an entirety of a top surface of the second fin structure, wherein a top surface of the filling layer is higher than the interface. 
     In some embodiments, a fin field effect transistor (FinFET) device structure is provided. The fin field effect transistor (FinFET) device structure includes an isolation structure over a substrate, and a first fin structure extended above the isolation structure. The fin field effect transistor (FinFET) device structure includes a second fin structure adjacent to the first fin structure, and a gate dielectric layer formed over the second fin structure. An entirety of a top surface of the second fin structure is in direct contact with the gate dielectric layer. The fin field effect transistor (FinFET) device structure includes a liner layer formed on outer sidewall surfaces of the second fin structure, and a top surface of the liner layer is higher than a bottommost surface of the gate dielectric layer. 
     The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.