Patent Publication Number: US-8120340-B2

Title: Control device for an interleaving power factor corrector

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The invention relates to a control device, more particularly to a control device for an interleaving power factor corrector. 
     2. Description of the Related Art 
     Referring to  FIG. 1 , a conventional interleaving power factor corrector  900  is shown to include first and second control modules  910 ,  920 , first and second power switches  930 ,  940 , and an interleaving circuit  950 . The first control module  910  outputs a first control signal (V D1 ) based on a current (I L1 ) flowing through an inductor (L 1 ) such that the first power switch  930  is operable between an ON-mode and an OFF-mode in response to the first control signal (V D1 ) from the first control module  910 . When the first control module  910  detects that the current (I L1 ) is zero, the first control signal (V D1 ) outputted by the first control module  910  has a high level such that the first power switch  930  is switched to the ON-mode. The second control module  920  outputs a second control signal (V D2 ) based on a current (I L2 ) flowing through an inductor (L 2 ) such that the second power switch  940  is operable between an ON-mode and an OFF-mode in response to the second control signal (V D2 ) from the second control module  920 . When the second control module  920  detects that the current (I L2 ) is zero, the second control signal (V D2 ) outputted by the second control module  920  has a high level such that the second power switch  930  is switched to the ON-mode. The first and second control modules  910 ,  920  are controlled by the interleaving circuit  950  so that the first and second control signals (V D1 , V D2 ) outputted respectively thereby have a phase difference of T/2 therebetween, i.e., 180°, where T is a cycle period of the current (I L1 ), as shown in  FIG. 2   a.    
     Referring to  FIGS. 2   a  to  2   e ,  FIG. 2   a  illustrates waveforms of the currents (I L1 , I L2 ), wherein S 1  and S 2  represent respectively the current (I L1 , I L2 ) in an ideal condition, S 3  represents the current (I L2 ) having a lead zero point, and S 4  represent the current (I L2 ) having a lag zero point.  FIG. 2   b  illustrates a waveform of the first control signal (V D1 ) corresponding to S 1  of  FIG. 2   a .  FIG. 2   c  illustrates a waveform of the second control signal (V D2 ) corresponding to S 2  of  FIG. 2   a .  FIGS. 2   d  and  2   e  illustrate waveforms of the second control signal (V D2 ) corresponding respectively to S 3  and S 4  of  FIG. 2   a . S 1  of  FIG. 2   a  indicates that the current (I L2 ) has a zero point at t 0  in the ideal condition. However, the zero point of the current (I L2 ) may drift as a result of external interference. For example, S 3  of  FIG. 2   a  indicates that the current (I L2 ) has a lead zero point at t 2 , and S 4  of  FIG. 2   a  indicates that the current (I L2 ) has a lag zero point at t 1 . Therefore, drift of the zero point of the current (I L2 ) incurs apparent variation of the duty cycle of the second control signal (V D2 ), as shown in  FIG. 2   d , or the diverged duty cycle of the second control signal (V D2 ), as shown in Figure and  2   e . Therefore, the conventional interleaving power factor corrector  900  cannot provide a stable voltage output to the load. 
     SUMMARY OF THE INVENTION 
     Therefore, an object of the present invention is to provide a control device for an interleaving power factor corrector that can overcome the aforesaid drawbacks of the prior art. 
     According to one aspect of the present invention, there is provided a control device for interleavingly driving first and second converting circuits of an interleaving power factor corrector such that the interleaving power factor corrector generates a voltage output (Vo). Each of the first and second converting circuits includes a combination of an inductor and a power switch. The power switches of the first and second converting circuits have control ends for receiving respectively first and second control signals such that the power switch of each of the first and second converting circuits is operable between an ON-mode and an OFF-mode in response to a corresponding one of the first and second control signals. The control device comprises: 
     a first control module adapted for detecting a current flowing through the inductor of the first converting circuit, outputting a feedback compensation signal (Vcomp) based on the voltage output (Vo) generated by the interleaving power factor corrector, and generating a first driving signal (Q_master) corresponding to the first control signal based on a result of current detection performed thereby and the feedback compensation signal (Vcomp), the first control module further outputting an inverted first driving signal (Qn_master); 
     a second control module adapted for detecting a current flowing through the inductor of the second converting circuit, receiving the inverted first driving signal (Qn_master) from the first control module, outputting a first reset signal (S_syn) based on the inverted first driving signal (Qn_master) received thereby, and generating a second driving signal (Q_slave) corresponding to the second control signal based on a result of current detection performed thereby, the first reset signal (S_syn) and a second reset signal (S_PTCL), the second control module further outputting an inverted second driving signal (Qn_slave); and 
     a phase modulating module including
         a reference signal generator coupled to the first and second control modules, receiving the inverted first driving signal (Qn_master) and the feedback compensation signal (Vcomp) from the first control module, and the first reset signal (S_syn) from the second control module, and generating a reference signal (Sref) based on the inverted first driving signal (Qn_master), the feedback compensation signal (Vcomp) and the first reset signal (S_syn) received thereby,   a ramp generator coupled to the second control module, receiving the inverted second driving signal (Qn_slave) from the second control module, and generating a first ramp signal (Sramp 1 ) based on the inverted second driving signal (Qn_slave) received thereby, and   a comparator unit coupled to the reference signal generator and the ramp generator for receiving respectively the reference signal (Sref) and the first ramp signal (Sramp 1 ) therefrom, comparing the reference signal (Sref) and the first ramp signal (Sramp 1 ) received thereby, and outputting the second reset signal (S_PTCL) that has a predetermined level when a level of the first ramp signal (Sramp 1 ) is greater than that of the reference signal (Sref);       

     When one of the first and second reset signals (S_syn, S_PTCL) has the predetermined level, the second driving signal (Q_slave) generated by the second control module has a level for switching the power switch of the second converting circuit to the OFF-mode. 
     According to another aspect of the present invention, an interleaving power factor corrector comprises: 
     first and second converting circuits each including a combination of an inductor and a power switch, the power switches of the first and second converting circuits having control ends for receiving respectively first and second control signals such that the power switch of each of the first and second converting circuits is operable between an ON-mode and an OFF-mode in response to a corresponding one of the first and second control signals; and 
     a control device for interleavingly driving the first and second converting circuits such that the interleaving power factor corrector outputs a voltage output (Vo), the control device including
         a first control module coupled to the first converting circuit, detecting a current flowing through the inductor of the first converting circuit, outputting a feedback compensation signal (Vcomp) based on the voltage output (Vo), and generating a first driving signal (Q_master) corresponding to the first control signal based on a result of current detection performed thereby and the feedback compensation signal (Vcomp), the first control module further outputting an inverted first driving signal (Qn_master),   a second control module coupled to the second converting circuit, detecting a current flowing through the inductor of the second converting circuit, receiving the inverted first driving signal (Qn_master) from the first control module, outputting a first reset signal (S_syn) based on the inverted first driving signal (Qn_master) from the first control module, and generating a second driving signal (Q_slave) corresponding to the second control signal based on a result of current detection performed thereby, the first reset signal (S_syn) and a second reset signal (S_PTCL), the second control module further outputting an inverted second driving signal (Qn_slave), and   a phase modulating module including
           a reference signal generator coupled to the first and second control modules, receiving the inverted first driving signal (Qn_master) and the feedback compensation signal (Vcomp) from the first control module, and the first reset signal (S_syn) from the second control module, and generating a reference signal (Sref) based on the inverted first driving signal (Qn_master), the feedback compensation signal (Vcomp) and the first reset signal (S_syn) received thereby,   a ramp generator coupled to the second control module for receiving the inverted second driving signal (Qn_slave) therefrom, and generating a first ramp signal (Sramp 1 ) based on the inverted second driving signal (Qn_slave) received thereby, and   a comparator unit coupled to the reference signal generator and the ramp generator for receiving respectively the reference signal (Sref) and the first ramp signal (Sramp 1 ) therefrom, comparing the reference signal (Sref) and the first ramp signal (Sramp 1 ) received thereby, and outputting the second reset signal (S_PTCL) that has a predetermined level when a level of the first ramp signal (Sramp 1 ) is greater than that of the reference signal (Sref).   
               

     When one of the first and second reset signals (S_syn, S_PTCL) has the predetermined level, the second driving signal (Q_slave) generated by the second control module has a level for switching the power switch of the second converting circuit to the OFF-mode. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Other features and advantages of the present invention will become apparent in the following detailed description of the preferred embodiment with reference to the accompanying drawings, of which: 
         FIG. 1  is a schematic circuit block diagram illustrating a conventional interleaving power factor corrector; 
         FIG. 2   a  illustrates waveforms of currents (I L1 , I L2 ) flowing respectively through first and second inductors of the conventional interleaving power factor corrector, wherein S 1  and S 2  represent respectively the current (I L1 , I L2 ) in an ideal condition, and S 3  and S 4  represent the current (I L2 ) in non-ideal conditions; 
         FIG. 2   b  illustrates a waveform of a first control signal (V D1 ) outputted by a first control module of the conventional interleaving power factor corrector and corresponding to S 1  of  FIG. 2   a;    
         FIG. 2   c  illustrates a waveform of a second control signal (V D2 ) outputted by a second control module of the conventional interleaving power factor corrector and corresponding to S 2  of  FIG. 2   a;    
         FIGS. 2   d  and  2   e  illustrate waveforms of the second control signal (V D2 ) corresponding respectively to S 3  and S 4  of  FIG. 2   a;    
         FIG. 3  is a schematic circuit block diagram illustrating the preferred embodiment of an interleaving power factor corrector according to the present invention; 
         FIGS. 4   a  to  4   d  illustrate respectively waveforms of a ramp signal (Vr), an activating signal (ZCD_master), a reset signal (Rm) and a first driving signal (Q_master) generated by a first control module of the preferred embodiment; 
         FIG. 5  is a schematic electrical circuit diagram illustrating a phase modulating module of the preferred embodiment; 
         FIGS. 6   a  and  6   b  illustrate respectively waveforms of a second driving signal (Q_slave) and an inverted second driving signal (Qn_slave) generated by a second control module of the preferred embodiment; 
         FIG. 6   c  illustrates a waveform of a first ramp signal (Sramp 1 ) generated by a ramp generator of the phase modulating module based on the inverted second driving signal (Qn_slave) of  FIG. 6   b;    
         FIGS. 7   a  and  7   b  illustrate respectively waveforms of a first reset signal (S_syn) generated by a second control module of the preferred embodiment, and an inverted first driving signal (Qn_master) generated by the first control module; 
         FIGS. 7   c  and  7   d  illustrate respectively waveforms of a second ramp signal (Sramp 2 ) and a reference signal (Sref) generated by the phase modulating module based on the first reset signal (S_syn) of  FIG. 7   a  and the inverted second driving signal (Qn_slave) of  FIG. 7   b;    
         FIG. 8  illustrates waveforms of the first driving signal (Q_master), the inverted first driving signal (Qn_master), the first reset signal (S_syn), an activating signal (ZCD_slave) generated by the second control module, the first ramp signal (Sramp 1 ), the reference signal (Sref), a second reset signal (S_PTCL) and an output signal (Rs) generated by the phase modulating module, and the second driving signal (Q_slave) when the preferred embodiment is operated in an ideal condition; and 
         FIGS. 9 and 10  illustrate waveforms of the first driving signal (Q_master), the inverted first driving signal (Qn_master), the first reset signal (S_syn), an activating signal (ZCD_slave) generated by the second control module, the first ramp signal (Sramp 1 ), the reference signal (Sref), a second reset signal (S_PTCL) and an output signal (Rs) generated by the phase modulating module, the second driving signal (Q_slave), and a current (I L2 ) flowing through an inductor of a second converting circuit of the preferred embodiment when the preferred embodiment is operated in non-ideal conditions. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Referring to  FIG. 3 , the preferred embodiment of an interleaving power factor corrector  100  according to the present invention is shown to include an EMI filter  40 , a bridge rectifier  50 , a first converting circuit  10 , a second converting circuit  20 , and a control device  30 . In this embodiment, the interleaving power factor corrector  100  is a boundary condition mode (BCM) power factor corrector. 
     The filter  40  is adapted to be coupled to a voltage source  101  for filtering a voltage input therefrom to eliminate electromagnetic interference. 
     The bridge rectifier  50  is coupled to the filter  40  for rectify the voltage input filtered by the filter  40 . 
     In this embodiment, the first and second converting circuits  10 ,  20  are coupled in parallel each other. Each of the first and second converting circuits  10 ,  20  includes a combination of an inductor (L 1 , L 2 ) and a power switch  11 ,  12 . The power switched  11 ,  12  of the first and second converting circuits  10 ,  20  have control ends for receiving respectively first and second control signals such that the power switch  11 ,  12  of each of the first and second converting circuits  10 ,  20  is operable between an ON-mode and an OFF-mode in response to a corresponding one of the first and second control signals. 
     The control device  30  interleavingly drives the first and second converting circuits  10 ,  20  such that the first and second converting circuits  10 ,  20  provide a current output to charge a capacitor (C). Thus, a voltage across the capacitor (C) serves as a voltage output (Vo) that is adapted to be applied to a load  60 . The control device  30  includes a first control module  31 , a second control module  32 , and a phase modulating module  33 . 
     In this embodiment, the first control module  31  includes a voltage divider  311 , a feedback amplifier unit, a comparator  314 , a zero-current detector  316 , an RS latch  317 , a ramp generator  315 , and a driver  318 . The voltage divider  311  receives the voltage output (Vo), and generates a divided voltage in accordance with the voltage output (Vo). The feedback amplifier unit includes an amplifier  312  and a compensation circuit  313 . The amplifier  312  has an inverting input end serving as a first input and coupled to the voltage divider for receiving the divided voltage therefrom, a non-inverting input end serving as a second input for receiving a reference voltage (Vref), and an output. The compensation circuit  313  is coupled between the first input and the output of the amplifier  312  such that the feedback amplifier unit outputs a feedback compensation signal (Vcomp) at the output of the amplifier  312 . The feedback compensation signal (Vcomp) is a voltage of 2.5V in this embodiment. The comparator  314  has an inverting input end coupled to the output of the amplifier  412  for receiving the feedback compensation signal (Vcomp) therefrom, a non-inverting input end for receiving a ramp signal (Vr), as shown in  FIG. 4   a,  and an output end. The comparator  314  compares the feedback compensation signal (Vcomp) and the ramp signal (Vr) received thereby, and outputs a reset signal (Rm) based on a comparison result made thereby. The zero-current detector  316  is coupled to the inductor (L 1 ) of the first converting circuit  10  for detecting a current (I L1 ) flowing therethrough, and generates an activating signal (ZCD_master), as shown in  FIG. 4   b,  upon detecting that the current (I L1 ) flowing through the inductor (L 1 ) of the first converting circuit is zero. The RS latch  317  has a set input coupled to the zero-current detector  316  for receiving the activating signal (ZCD_master) therefrom, a reset input coupled to the output end of the comparator  314  for receiving the reset signal (Rm) therefrom, a data output for outputting a first driving signal (Q_master) corresponding to the first control signal, and an inverted data output for outputting an inverted first driving signal (Qn_master). The ramp generator  315  is coupled to the inverted data output of the SR latch  317  and the non-inverting input end of the comparator  314 , receives the inverted first driving signal (Qn_master) from the inverted data output of the SR latch  317 , and output the ramp signal (Vr) to the non-inverting input end of the comparator  314  based on the inverted first driving signal (Qn_master) received thereby. The driver  318  is coupled to the data output of the RS latch  317  and the control end of the power switch  11  of the first converting circuit  10 , receives the first driving signal (Q_master) from the data output of the RS latch  317 , and outputs the first control signal to the control end of the power switch  11  of the first converting circuit  10  based on the first driving signal (Q_master) received thereby. Referring to  FIGS. 4   a  to  4   d , when the activating signal (ZCD_master) generated by the zero-current detector  316  has a high level, the first driving signal (Q_master) has a high level until the ramp signal (Vr) generated by the ramp generator  315  is greater than the feedback compensation signal (Vcomp), i.e., 2.5V, such that the reset signal (Rm) outputted at the output of comparator  314  has a high level. Then, the first driving signal (Q_master) is switched from the high level to a low level. 
     In this embodiment, the second control module  32  includes an off-time synchronizer  321 , a zero-current detector  322 , an RS latch  323 , and a driver  324 . The off-time synchronizer  321  is coupled to the inverted data output of the RS latch  317  of the first control module  31  for receiving the inverted first driving signal (Qn_master) therefrom, and outputs a first reset signal (S_syn) upon detecting that the inverted first driving signal (Qn_master) has a predetermined level for a predetermined duration. In this embodiment, the predetermined level is a high level, and the predetermined duration is T S /2, where T S  is the time period of a previous cycle of the first driving signal (Q_master), as shown in  FIG. 8 . The zero-current detector  322  is coupled to the inductor (L 2 ) of the second converting circuit  20  for detecting a current (I L2 ) flowing therethrough, and generates an activating signal (ZCD_slave) upon detecting that the current (I L2 ) flowing through the inductor (L 2 ) of the second converting circuit  20  is zero. The RS latch  323  has a set input coupled to the zero-current detector  322  for receiving the activating signal (ZCD_slave) therefrom, a reset input for receiving an output signal (Rs), a data output for outputting a second driving signal (Q_slave), and an inverted data output for outputting an inverted second driving signal (Qn_slave). The driver  324  is coupled to the data output of the RS latch  323  and the control end of the power switch  21  of the second converting circuit  20 , receives the second driving signal (Q_slave) from the data output of the RS latch  323 , and outputs the second control signal to the control end of the power switch  21  of the second converting circuit  20  based on the second driving signal (Q_slave) received thereby. 
     The phase modulating module  33  includes a reference signal generator  37 , a ramp generator  36 , a comparator unit  38 , and a logic gate  35 . 
     The ramp generator  36  is coupled to the inverted data output of the RS latch  323  of the second control module  32  for receiving the inverted second driving signal (Qn_slave) therefrom, and generates a first ramp signal (Sramp 1 ) based on the inverted second driving signal (Qn_slave) received thereby. Referring further to  FIG. 5 , in this embodiment, the ramp generator  36  includes a current source  361 , and a parallel connection of a switch (Sw 1 ) and a capacitor  362  coupled between the current source  361  and a reference node, such as ground. The switch (Sw 1 ) has a control end  365  coupled to the inverted data output of the SR latch  323  of the second control module  32  for receiving the inverted second driving signal (Qn_slave) therefrom. A voltage across the capacitor  362  serves as the first ramp signal (Sramp). Referring to  FIGS. 6   b  and  6   c , when the inverted second driving signal (Qn_slave) has a low level, the switch (Sw 1 ) is in an OFF-mode such that the capacitor  362  is charged by a current (Is) from the current source  361  to a level equal to that of the feedback compensation signal (Vcomp), thereby obtaining the first ramp signal (Sramp). Thus, a charge period (T ON ) of the capacitor  362  is represented as follows: 
                       Cs   ·   Vcomp     =     Is   ·     T   ON         ⁢     
     ⁢       T   ON     =       Cs   ·   Vcomp     Is               (     Equation   ⁢           ⁢   1     )               
where Cs is the capacitance of the capacitor  362 . In this embodiment, the charge period (T ON ) of the capacitor  362  serves as the duty cycle of the second driving signal (Q_slave).
 
     The reference signal generator  37  is coupled to the first and second control modules  31 ,  32 , receives the inverted first driving signal (Qn_master) and the feedback compensation signal (Vcomp) from the first control module  31 , and generates a reference signal (Sref) based on the inverted first driving signal (Qm_master), the feedback compensation signal (Vcomp) and the first reset signal (S_syn) received thereby. As shown in  FIG. 5 , in this embodiment, the reference signal generator  37  includes a ramp circuit  371  and a buffer  372 . The ramp circuit  371  includes a series connection of a first current source  374 , a first switch (Sw 2 ), a second switch (Sw 3 ) and a second current source  375 , a capacitor  376 , a third switch (Sw 4 ), a fourth switch (Sw 5 ), and an SR latch  373 . Each of the first and second switches (Sw 2 , Sw 3 ) has a control end. The capacitor  376  is coupled between a first common node (n 1 ) of the first and second switches (Sw 2 , Sw 3 ), and the second current  375 . The third switch (Sw 4 ) is coupled in parallel to the capacitor  376 , and has a control end coupled to the off-time synchronizer  321  for receiving the first reset signal (S_syn) therefrom. The fourth switch (Sw 5 ) is coupled to the first common node (n 1 ), and has a control end. The RS latch  373  has a set input coupled to the off-time synchronizer  321  of the second control module  32  for receiving the first reset signal (S_syn) therefrom, a reset input coupled to the inverted data output of the RS latch  317  of the first control module  31  for receiving the inverted first driving signal (Qn_master) therefrom, a data output coupled to the control end of the first switch (Sw 2 ), and an inverted data output coupled to the control ends of the second and fourth switches (Sw 3 , Sw 5 ). The buffer  372  is a unity gain buffer in this embodiment, and has a non-inverting input serving as a first input and coupled to the output of the amplifier  312  of the first control module  31  for receiving the feedback compensation signal (Vcomp) therefrom, and a second input and an output coupled to a common node (n 2 ) of the second current source  375  and the capacitor  376 . A second ramp signal (Sramp 2 ) is generated at the first common node (n 1 ), and serves as the reference signal (Sref) when the fourth switch (Sw 5 ) is in an ON-mode. Referring to  FIGS. 7   a  to  7   d,  during a period from t 1  to t 2 , when the first reset signal (S_syn) has a high level, the first and fourth switches (Sw 2 , Sw 5 ) conduct and the second and third switches (Sw 3 , Sw 4 ) do not conduct such that the capacitor  376  is charged by a current (Is 2 ) from the first current source  374  for the period from t 1  to t 2 . Thus, a voltage (Vn) across the capacitor  376  is represented as follows: 
                         C     S   ⁢           ⁢   2       ·   Vn     =       I     S   ⁢           ⁢   2       ·     1   2     ·   Ts       ⁢     
     ⁢     Vn   =       1   2     ·       I     S   ⁢           ⁢   2         C     S   ⁢           ⁢   2         ·   Ts               (     Equation   ⁢           ⁢   2     )               
where C S2  is the capacitance of the capacitor  376 , and Ts is the cycle of the first driving signal (Q_master). The potential at the second common node (n 2 ) maintains a level equal to that of the feedback compensation signal (Vcomp). In this case, the reference signal (Sref) has a level equal to that of the feedback compensation signal (Vcomp). On the other hand, during a period from t 2  to t 3 , when the inverted first driving signal (Qn_master) has a high level, the first and fourth switches (Sw 2 , Sw 5 ) do not conduct and the second and third switches (Sw 3 , Sw 4 ) conduct such that the capacitor  376  discharges through the second switch (Sw 3 ). In this case, the second ramp signal (Sramp 2 ) serves as the reference signal (Sref).
 
     The comparator unit  38  is coupled to the reference signal generator  37  and the ramp generator  36  for receiving respectively the reference signal (Sref) and the first ramp signal (Sramp 1 ) therefrom, compares the reference signal (Sref) and the first ramp signal (Sramp 1 ) received thereby, and outputs the second reset signal (S_PTCL) that has a predetermined level when a level of the first ramp signal (Sramp 1 ) is greater than that of the reference signal (Sref). In this embodiment, the predetermined level is a high level. As shown in  FIG. 5 , the comparator unit  38  includes a comparator  381  and a one-shot circuit  382 . The comparator  381  has first and second input ends, such as inverting and non-inverting input ends, coupled respectively to the reference signal generator  37  and the ramp generator  36  for receiving respectively the reference signal (Sref) and the first ramp signal (Sramp 1 ) therefrom, and an output end for outputting an output based on the reference signal (Sref) and the first ramp signal (Sramp 1 ) received thereby. The one-shot circuit  382  is coupled to the output end of the comparator, receives the output from the output end of the comparator  381 , and converts the output received thereby in the form of a pulse. The output converted by the one-shot circuit serves as the second reset signal (S_PTCL). 
     As shown in  FIGS. 3 and 5 , the logic gate  35  is an OR gate in this embodiment, and has first and second inputs  351 ,  352  coupled respectively to the one-shot circuit  381  of the comparator unit  38  and the off-time synchronizer  321  of the second control module  32  for receiving respectively the second and first reset signals (S_PTCL, S_syn) therefrom, and an output  353  coupled to the reset input of the RS latch  323  of the second control module  32  for outputting the output signal (Rs) therero. Therefore, when one of the first and second reset signals (S_syn, S_PTCL) has the predetermined level, i.e., the high level, the second driving signal (Q_slave) has a level, i.e., a low level, for switching the power switch  21  of the second converting circuit  20  to the OFF-mode. 
       FIG. 8  illustrates waveforms of the first driving signal (Q_master), the inverted first driving signal (Qn_master), the first reset signal (S_syn), the activating signal (ZCD_slave), the first ramp signal (Sramp 1 ), the reference signal (Sref), the second reset signal (S_PTCL), the output signal (Rs) and the second driving signal (Q_slave) when the preferred embodiment is operated in an ideal condition, where delay on the zero-current detector  322  of the second control module  32  does not occur and there is no external noise interference in the current (I L2 ) flowing through the inductor (L 2 ). Referring to  FIGS. 3 ,  5  and  8 , during an n th  cycle period of the first driving signal (Q_master), i.e., Ts(n), the inverted first driving signal (Qn_master) is switched to a high level at t 1 . When the inverted first driving signal (Qn_master) maintains the high level for half the period (Ts(n−1)) of an (n−1) th  cycle of the first driving signal (Q_master), the off-time synchronizer  321  outputs the first reset signal (S_syn) having a high level at t 5 . The activating signal (ZCD_slave) outputted by the zero-current detector  322  of the second control module  32  has a high level at t 3  such that the second driving signal (Q_slave) is switched to a high level at t 3  and that the inverted second driving signal (Qn_slave) has a low level at t 3 . Thus, the capacitor  362  of the ramp generator  36  is charged to the level of feedback compensation signal (Vcomp) during a period from t 3  to t 5 . In other words, the first ramp signal (Sramp 1 ) gradually increases during the period from t 3  to t 5 . Since the inverted first driving signal (Qn_master) is switched to the high level at t 1 , the capacitor  367  of the ramp circuit  371  discharges through the second switch (Sw 3 ) during a period of t 1  to t 5  such that the reference signal (Sref) gradually decreases to the level of the feedback compensation signal (Vcomp) during the period from t 1  to t 5 . The second reset signal (S_PTCL) maintains a low level during the period from t 1  to t 5  because the first ramp signal (Sramp 1 ) is not greater than the reference signal (Sref), and the first reset signal (S_syn) is switched to the high level at t 5  such that the output signal (Rs) is switched to a high level at t 5 . Thus, the second driving signal (Q_slave) is switched from the high level to a low level at t 5 . 
     In this embodiment, the first driving signal (Q_master) has a frequency that varies with the load  60 . Therefore, a time point at which the activating signal (ZCD_slave) is triggered to have the high level will change. 
       FIG. 9  illustrates waveforms of the first driving signal (Q_master), the inverted first driving signal (Qn_master), the first reset signal (S_syn), the activating signal (ZCD_slave), the first ramp signal (Sramp 1 ), the reference signal (Sref), the second reset signal (S_PTCL), the output signal (Rs), the second driving signal (Q_slave), and the current (I L2 ) when the preferred embodiment is operated in a lead condition, where a time point at which the current (I L2 ) becomes zero leads that in the ideal condition. 
     Referring to  FIGS. 3 ,  5  and  9 , during an n th  cycle period (Ts(n)) of the first driving signal (Q_master), the activating signal (ZCD_slave) generated by the zero-current detector  322  is triggered to have the high level at t 2  earlier to t 3  at which the activating signal (ZCD_slave), as indicated by dotted lines, is triggered to have the high level in the ideal condition. As a result, a charging period of the capacitor  362 , i.e., a period from t 2  to t 5 , is longer than that in the ideal condition, i.e., the period from t 3  to t 5 , such that the first ramp signal (Sramp 1 ) is greater than the reference signal (Sref) at t 4 . Thus, the second reset signal (S_PTCL) is triggered to have a high level at t 4  such that the output signal (Rs) is switched to a high level, and the second driving signal (Q_slave) is switched from a high level to a low level at t 4  earlier to t 5  at which the second driving signal (Q_slave), as indicated by dotted lines, is switched from a high level to a low level in the ideal condition. In this case, the current (I L2 ) does not diverge. 
       FIG. 10  illustrate waveforms of the first driving signal (Q_master), the inverted first driving signal (Qn_master), the first reset signal (S_syn), the activating signal (ZCD_slave), the first ramp signal (Sramp 1 ), the reference signal (Sref), a second reset signal (S_PTCL), the output signal (Rs), the second driving signal (Q_slave), and the current (I L2 ) when the preferred embodiment is operated in a lag condition, where a time point at which the current (I L2 ) becomes zero lags that in the ideal condition as a result of interference. 
     Referring to  FIGS. 3 ,  5  and  10 , during an n th  cycle period (Ts(n)) of the first driving signal (Q_master), the activating signal (ZCD_slave) is triggered to have the high level at t 3 ′ later to t 3  at which the activating signal (ZCD_slave), as indicated by dotted lines, is triggered to have the high level in the ideal condition. As a result, a charging period of the capacitor  362 , i.e., a period from t 3 ′ to t 5 , is shorter than that in the ideal condition, i.e., the period from t 3  to t 5 , such that the first ramp signal (Sramp 1 ) is not greater than the reference signal (Sref) during the period from t 3 ′ to t 5 . Thus, the second reset signal (S_PTCL) maintains a low level during Ts(n). The output signal (Rs) is switched to a high level at t 5  in response to the first reset signal (S_syn). It is noted that the second driving signal (Q_slave) has a duty cycle, i.e., the period from t 3 ′ to t 5 , that is shorter than that in the ideal condition, i.e., the period from t 3  to t 5 . Therefore, the current (I L2 ) has a maximum at t 5  smaller than that in the ideal condition. In other words, energy stored in the inductor (L 2 ) of the second converting circuit  20  is less than that in the ideal condition. 
     During an (n+1) th  cycle period (Ts(n+1)) of the first driving signal (Q_master), the activating signal (ZCD_slave) is triggered to have the high level at t 12  earlier to t 13  at which the activating signal (ZCD_slave), as indicated by dotted lines, is triggered to have the high level in the ideal condition. As a result, a charging period of the capacitor  362 , i.e., a period from t 12  to t 15 , is longer than that in the ideal condition, i.e., the period from t 13  to t 15 , such that the first ramp signal (Sramp 1 ) is greater than the reference signal (Sref) at t 14 . Thus, the second reset signal (S_PTCL) is switched to a high level at t 14  such that the output signal (Rs) is switched to a high level at t 14  in response to the second reset signal (S_PTCL), and the second driving signal (Q_slave) is switched from a high level to a low level at t 14  earlier to t 5  at which the second driving signal (Q_slave), as indicated by dotted lines, is switched from a high level to a low level in the ideal condition. It is noted that a duty cycle of the second driving signal (Q_slave) in the (n+1) th  cycle, i.e., the period from t 12  to t 14 , is greater than that in the n th  cycle, i.e., the period from t 3 ′ to t 5 . Therefore, the current (I L2 ) has a value at t 14  larger than that at t 5 . In other words, energy stored in the inductor (L 2 ) of the second converting circuit  20  during the (n+1) th  cycle period (Ts(n+1)) is greater than that during the n th  cycle period (Ts(n)). 
     Similarly, During an (n+2) th  cycle period (Ts(n+2)) of the first driving signal (Q_master), the second driving signal (Q_slave) is switched to a high level at t 22  earlier to t 23  in the ideal condition. During an (n+3) th  cycle period (Ts(n+3)) of the first driving signal (Q_master), the second driving signal (Q_slave) is switched to a high level at t 32  earlier to t 33  in the ideal condition. It is noted that a period from t 32  to t 33  is less than a period from t 22  to t 23  that is less than a period from t 12  to t 13 . Therefore, the phase modulating module  33  is operable so that the second driving signal (Q_slave) gradually converges to approach that in the ideal condition. 
     In sum, no matter whether drift of the activating signal (ZCD_slave) occurs, i.e., the zero point of the current (I L2 ) drifts, the phase modulating module  33  is operable to control the duty cycle of the second driving signal (Q_slave) using the first reset signal (S_syn) or the second reset signal (S_PTCL). Therefore, the second driving signal (Q_slave) can follow variance of the first driving signal (Q_master) even though the duty cycle of the first driving signal (Q_master) varies with the load  60 , thereby ensuring a stable current (I L2 ). Thus, the interleaving power factor corrector  100  of this invention can ensure the stable voltage output (Vo). 
     While the present invention has been described in connection with what is considered the most practical and preferred embodiment, it is understood that this invention is not limited to the disclosed embodiment but is intended to cover various arrangements included within the spirit and scope of the broadest interpretation so as to encompass all such modifications and equivalent arrangements.