Patent Publication Number: US-11043045-B2

Title: Monitoring device and motor vehicle including the same

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2017-208246, filed on Oct. 27, 2017, the entire contents of which are incorporated herein by reference. 
     TECHNICAL FIELD 
     The present disclosure relates to a monitoring device, and a motor vehicle including the monitoring device. 
     BACKGROUND 
     Conventionally, monitoring devices (e.g., monitoring ICs) for monitoring various voltages and clock signals to detect abnormality thereof are used in various applications. 
     However, in the aforementioned conventional monitoring device, there is still room for further improvement in increasing a failure detection rate. 
     In recent years, it is required for in-vehicle ICs to comply with ISO 26262 (international standard for the functional safety related to the electric/electronic of a motor vehicle). Even in in-vehicle monitoring ICs, reliability design considering a fail-safe mechanism is required. 
     SUMMARY 
     The present disclosure provides some embodiments of a monitoring device having a high failure detection rate. 
     According to one embodiment of the present disclosure, there is provided a monitoring device, including: a monitoring part configured to detect an abnormality of a monitoring target; a self-diagnosis part configured to diagnose whether or not the monitoring part operates normally during a period from a startup time point of a power supply to an elapse time point at which a reset release waiting time elapses; and a reset control part configured to release a reset of a reset output signal on or after the elapse time point (first configuration). 
     In the device of the first configuration, the self-diagnosis part is further configured to repeatedly diagnose the monitoring part until the self-diagnosis part determines that the monitoring part operates normally (second configuration). 
     In the device of the first configuration, while sequentially switching a diagnosis target, to which a test signal is inputted, from among a plurality of monitoring mechanisms included in the monitoring part, the self-diagnosis part is further configured to determine whether or not an output signal from a monitoring mechanism serving as the diagnosis target matches a first expected value and also to determine whether or not an output signal from each of the plurality of monitoring mechanisms other than the monitoring mechanism serving as the diagnosis target matches a second expected value (third configuration). 
     In the device of the first configuration, the monitoring part includes an upper comparator configured to detect whether or not an input signal is higher than an upper threshold value; and a lower comparator configured to detect whether the input signal is lower than a lower threshold value, and the self-diagnosis part is further configured to determine whether or not an output signal of each of the upper comparator and the lower comparator matches an expected value, while sequentially switching the input signal among a first test signal higher than the upper threshold value, a second test signal lower than the upper threshold value and higher than the lower threshold value, and a third test signal lower than the lower threshold value (fourth configuration). 
     In the device of the first configuration, the self-diagnosis part is further configured to store an error flag for indicating an object in which an error occurs (fifth configuration). 
     According to another embodiment of the present disclosure, there is provided a monitoring device, including: a monitoring part configured to detect an abnormality of a monitoring target; an input terminal to which an enable signal for switching between validity and invalidity of the monitoring part is inputted; and an output terminal configured to output a status signal for notifying validity or invalidity of the monitoring part (sixth configuration). 
     In the device of the sixth configuration, the monitoring part includes a watchdog timer configured to detect a frequency abnormality of a monitoring target signal (seventh configuration). 
     According to a further embodiment of the present disclosure, there is provided a monitoring device, including: a first oscillator configured to generate a first clock signal having a first oscillation frequency; a second oscillator configured to generate a second clock signal having a second oscillation frequency lower than the first oscillation frequency; a frequency divider configured to divide the first oscillation frequency of the first clock signal to generate a third clock signal having a third oscillation frequency lower than the second oscillation frequency; a first low frequency abnormality detection part configured to detect a low frequency abnormality of the third clock signal using the second clock signal; and a second low frequency abnormality detection part configured to detect a low frequency abnormality of the second clock signal using the first clock signal (eighth configuration). 
     In the device of the eighth configuration, the first clock signal is a clock signal for digital processing, and the second clock signal is a clock signal for a watchdog timer (ninth configuration). 
     The device of the ninth configuration further includes: a reset control part configured to latch a plurality of abnormality signals and output an output signal in synchronization with the first clock signal; and a logic gate configured to set a reset output signal to a logic level indicated at the time of abnormality detection by ignoring the output signal of the reset control part when an abnormal stop of the first clock signal is detected (tenth configuration). 
     According to a still further embodiment of the present disclosure, there is provided an electronic device including the monitoring device of the first configuration (eleventh configuration). 
     According to a yet still further embodiment of the present disclosure, there is provided a motor vehicle including the electronic device of the eleventh configuration (twelfth configuration). 
    
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         FIG. 1  is a block diagram showing an overall configuration of an electronic device. 
         FIG. 2  is a block diagram showing an internal configuration of a monitoring IC. 
         FIG. 3  is a schematic diagram showing a first startup sequence. 
         FIG. 4  is a schematic diagram showing a second startup sequence. 
         FIG. 5  is a timing chart showing the second startup sequence. 
         FIG. 6  is a state transition diagram showing the second startup sequence. 
         FIG. 7  is a circuit diagram showing a configuration example of a test circuit. 
         FIG. 8  is a timing chart showing a first embodiment of a BIST. 
         FIG. 9  is a timing chart showing a second embodiment of the BIST. 
         FIG. 10  is a timing chart showing an example of a diagnosis result in a first embodiment. 
         FIG. 11  is a timing chart showing another example of the diagnosis result in the first embodiment. 
         FIG. 12  is a timing chart showing an example of a diagnosis result in a second embodiment. 
         FIG. 13  is a timing chart showing another example of the diagnosis result in the second embodiment. 
         FIG. 14  is a timing chart showing an operation of generating a BIST error signal. 
         FIG. 15  is a register map showing a storage area of a BIST error flag. 
         FIG. 16  is a diagram showing how one-way communication is performed between a monitoring IC and a microcomputer. 
         FIG. 17  is a diagram showing how bidirectional communication is performed between the monitoring IC and the microcomputer. 
         FIG. 18  is a timing chart showing an operation of generating a status signal. 
         FIG. 19  is a correlation diagram of an enable signal, a status signal and a terminal state. 
         FIG. 20  is a block diagram showing a first configuration example of a clock detection part. 
         FIG. 21  is a diagram showing a determination operation of the clock detection part. 
         FIG. 22  is a block diagram showing a second configuration example of the clock detection part. 
         FIG. 23  is a diagram showing a determination operation of a first low frequency abnormality detection part. 
         FIG. 24  is a diagram showing a determination operation of a second low frequency abnormality detection part. 
         FIG. 25  is a diagram showing a first configuration example of a digital processing part. 
         FIG. 26  is a diagram showing a second configuration example of the digital processing part. 
         FIG. 27  is a timing chart showing an example of a reset output operation. 
         FIG. 28  is an external view of a motor vehicle. 
     
    
    
     DETAILED DESCRIPTION 
     One embodiment of the present disclosure will now be described in detail with reference to the drawings. 
     &lt;Electronic Device&gt; 
       FIG. 1  is a block diagram showing an overall configuration of an electronic device. The electronic device  1  of the present configuration example includes a monitoring IC  100 , a power management IC  200  and a microcomputer  300 . The electronic device  1  further includes resistors R 1  to R 16  and a capacitor C 1  as discrete components externally attached to the aforementioned semiconductor devices such as the monitoring IC  100 , the power management IC  200 , and/or the microcomputer  300 . 
     The monitoring IC  100  is a semiconductor integrated circuit device that operates by receiving a power supply voltage VDD (i.e., output voltage VO 1 ) from the power management IC  200 . The monitoring IC  100  monitors various output voltages of the power management IC  200  and the output frequency of the microcomputer  300  to detect abnormality thereof. The monitoring IC  100  includes a plurality of external terminals (a VDD pin, a GND pin, an RSTIN pin, an RSTOUT pin, DIN 1  to DIN 4  pins, PG 1  to PG 4  pins, a RTW pin, a WDIN pin, a WDEN pin and a WDOUT pin) as a means for establishing electrical connection with the outside of the IC. 
     The power management IC  200  is a semiconductor integrated circuit device that operates by receiving a battery voltage VBAT. The power management IC  200  generates a plurality of output voltages VO 1  to VO 5  and supplies them to each part of the electronic device  1 . Instead of the power management IC  200 , it is also possible to use a discrete DC/DC converter, an LDO (Low Drop-Out) regulator, or the like. 
     The microcomputer  300  is a semiconductor integrated circuit device that operates by receiving a power supply voltage VDD (i.e., output voltage VO 1 ) from the power management IC  200 . The microcomputer  300  comprehensively controls the operation of the entire electronic device  1  including the monitoring IC  100  and the power management IC  200 . 
     The microcomputer  300  is reset by a reset output signal RSTOUT inputted from the monitoring IC  100 . More specifically, the microcomputer  300  comes into a reset state (i.e., disable state) when the reset output signal RSTOUT is at a low level, and comes into a reset release state (i.e., enable state) when the reset output signal RSTOUT is at a high level. 
     Further, the microcomputer  300  has a function of determining whether or not the output voltage VOx of the power management IC  200  is normal according to the logic level of a power good signal PGx (where x=1, 2, 3, 4, which may apply in the following description) inputted from the monitoring IC  100 . More specifically, the microcomputer  300  determines that the output voltage VOx is normal when the power good signal PGx is at the high level, and determines that the output voltage VOx is abnormal (for example, an overvoltage abnormality or a low voltage abnormality) when the power good signal PGx is at the low level. 
     Moreover, the microcomputer  300  has a function of outputting a watchdog input signal WDIN (a reset pulse signal of several tens Hz) and a watchdog enable signal WDEN to the WDIN pin and the WDEN pin of the monitoring IC  100 , respectively. Furthermore, the microcomputer  300  also has a function of determining a match between the logic level of the watchdog enable signal WDEN set by the microcomputer  300  and the logic level of the watchdog output signal WDOUT returned from the WDOUT pin of the monitoring IC  100 . These functions will be described later in detail. 
     The resistors R 1  and R 2  are connected in series between the output terminal of the output voltage VO 1  and the ground terminal, and serve as a voltage dividing circuit for the output voltage VO 1 . The connection node (i.e., the output terminal of the voltage dividing circuit) between the resistors R 1  and R 2  is connected to the RSTIN pin of the monitoring IC  100 . 
     The resistors R 3  and R 4  are connected in series between the output terminal of the output voltage VO 2  and the ground terminal, and serve as a voltage dividing circuit for the output voltage VO 2 . The connection node (i.e., the output terminal of the voltage dividing circuit) between the resistors R 3  and R 4  is connected to the DIN 1  pin of the monitoring IC  100 . 
     The resistors R 5  and R 6  are connected in series between the output terminal of the output voltage VO 3  and the ground terminal, and serve as a voltage dividing circuit for the output voltage VO 3 . The connection node (i.e., the output terminal of the voltage dividing circuit) between the resistors R 5  and R 6  is connected to the DIN 2  pin of the monitoring IC  100 . 
     The resistors R 7  and R 8  are connected in series between the output terminal of the output voltage VO 4  and the ground terminal, and serve as a voltage dividing circuit for the output voltage VO 4 . The connection node (i.e., the output terminal of the voltage dividing circuit) between the resistors R 7  and R 8  is connected to the DIN 3  pin of the monitoring IC  100 . 
     The resistors R 9  and R 10  are connected in series between the output terminal of the output voltage VO 5  and the ground terminal, and serve as a voltage dividing circuit for the output voltage VO 5 . The connection node (i.e., the output terminal of the voltage dividing circuit) between the resistors R 9  and R 10  is connected to the DIN 4  pin of the monitoring IC  100 . 
     The resistor R 11  is connected between the RTW pin of the monitoring IC  100  and the ground terminal, and serves as an oscillation frequency setting element for an oscillator. 
     The resistor R 12  is connected between the RSTOUT pin and the power supply terminal of the monitoring IC  100 , and serves as a pull-up resistor for lifting the reset output signal RSTOUT, which is sent from the monitoring IC  100  to the microcomputer  300 , to the power supply voltage VDD. 
     The resistor R 13  is connected between the PG 1  pin of the monitoring IC  100  and the power supply terminal, and serves as a pull-up resistor for lifting the power good signal PG 1 , which is sent from the monitoring IC  100  to the microcomputer  300 , to the power supply voltage VDD. 
     The resistor R 14  is connected between the PG 2  pin of the monitoring IC  100  and the power supply terminal, and serves as a pull-up resistor for lifting the power good signal PG 2 , which is sent from the monitoring IC  100  to the microcomputer  300 , to the power supply voltage VDD. 
     The resistor R 15  is connected between the PG 3  pin of the monitoring IC  100  and the power supply terminal, and serves as a pull-up resistor for lifting the power good signal PG 3 , which is sent from the monitoring IC  100  to the microcomputer  300 , to the power supply voltage VDD. 
     The resistor R 16  is connected between the PG 4  pin of the monitoring IC  100  and the power supply terminal, and serves as a pull-up resistor for lifting the power good signal PG 4 , which is sent from the monitoring IC  100  to the microcomputer  300 , to the power supply voltage VDD. 
     The capacitor C 1  is connected between the output terminal of the output voltage VO 1  and the ground terminal, and serves as a smoothing means of the output voltage VO 1  (i.e., power supply voltage VDD). 
     &lt;Monitoring IC&gt; 
       FIG. 2  is a block diagram showing the internal configuration of the monitoring IC  100 . The monitoring IC  100  of this configuration example includes a reference voltage generation part  111 , a sub-reference voltage generation part  112 , a reference voltage detection part  120 , a UVLO [Under Voltage Locked-Out] part  130 , threshold voltage generation parts  140  to  149 , comparators  150  to  159 , oscillators  161  and  162 , a digital processing part  170 , N channel type MOS [Metal Oxide Semiconductor] field effect transistors  180  to  184 , and a buffer  190 , which are integrated. 
     The reference voltage generation part  111  generates a predetermined reference voltage VREF from the power supply voltage VDD inputted to the VDD pin. 
     The sub-reference voltage generation part  112  generates a predetermined sub reference voltage VREF 2  from the power supply voltage VDD. 
     The reference voltage detection part  120  operates by receiving the power supply voltage VDD, and generates a reference voltage detection signal VREF_DET by detecting whether the reference voltage VREF and the sub reference voltage VREF 2  are normally rising. The reference voltage detection signal VREF_DET has a low level when both the reference voltage VREF and the sub reference voltage VREF 2  are normally rising, and has a high level when at least one of the reference voltage VREF and the sub reference voltage VREF 2  does not normally rise. In addition, a BIST [Built-In Self-Test] enable signal BIST_EN is inputted to the reference voltage detection part  120 . That is, the reference voltage detection part  120  corresponds to a monitoring part (or one of a plurality of monitoring mechanisms included in the monitoring part) to be self-diagnosed at the time of startup of the monitoring IC  100 . 
     The UVLO part  130  detects a low voltage abnormality of the power supply voltage VDD and outputs a low voltage abnormality signal UVLO. The low voltage abnormality signal UVLO becomes high level when the power supply voltage VDD is higher than a low voltage abnormality release value UVLO_OFF, and becomes low level when the power supply voltage VDD is lower than a low voltage abnormality detection value UVLO_ON. 
     Each of the threshold voltage generation parts  140  and  141  divides the reference voltage VREF to generate an upper threshold voltage Vth 0 H (for example, 0.88 V) and a lower threshold voltage Vth 0 L (for example, 0.72 V). 
     Each of the threshold voltage generation parts  142  and  143  divides the reference voltage VREF to generate an upper threshold voltage Vth 1 H (for example, 0.88 V) and a lower threshold voltage Vth 1 L (for example, 0.72 V). 
     Each of the threshold voltage generation parts  144  and  145  divides the reference voltage VREF to generate an upper threshold voltage Vth 2 H (for example, 0.88 V) and a lower threshold voltage Vth 2 L (for example, 0.72 V). 
     Each of the threshold voltage generation parts  146  and  147  divides the reference voltage VREF to generate an upper threshold voltage Vth 3 H (for example, 0.88 V) and a lower threshold voltage Vth 3 L (for example, 0.72 V). 
     Each of the threshold voltage generation parts  148  and  149  divides the reference voltage VREF to generate an upper threshold voltage Vth 4 H (for example, 0.88 V) and a lower threshold voltage Vth 4 L (for example, 0.72 V). 
     The comparator  150  operates by receiving the power supply voltage VDD and generates a comparison signal RSTOVD by comparing the input voltage V 0  inputted to a non-inverting input terminal (+) from the RSTIN pin and the upper threshold voltage Vth 0 H inputted to an inverting input terminal (−) from the threshold voltage generation part  140 . The comparison signal RSTOVD becomes a high level when V 0 &gt;Vth 0 H, and becomes a low level when V 0 &lt;Vth 0 H. 
     The comparator  151  operates by receiving the power supply voltage VDD and generates a comparison signal RSTUVD by comparing the input voltage V 0  inputted to an inverting input terminal (−) from the RSTIN pin and the lower threshold voltage Vth 0 L inputted to a non-inverting input terminal (+) from the threshold voltage generation part  141 . The comparison signal RSTUVD becomes a low level when V 0 &gt;Vth 0 L, and becomes a high level when V 0 &lt;Vth 0 L. 
     The comparator  152  operates by receiving the power supply voltage VDD and generates a comparison signal DIN 1 OVD by comparing the input voltage V 1  inputted to a non-inverting input terminal (+) from the DIN 1  pin and the upper threshold voltage Vth 1 H inputted to an inverting input terminal (−) from the threshold voltage generation part  142 . The comparison signal DIN 1 OVD becomes a high level when V 1 &gt;Vth 1 H, and becomes a low level when V 1 &lt;Vth 1 H. 
     The comparator  153  operates by receiving the power supply voltage VDD and generates a comparison signal DIN 1 UVD by comparing the input voltage V 1  inputted to an inverting input terminal (−) from the DIN 1  pin and the lower threshold voltage Vth 1 L inputted to a non-inverting input terminal (+) from the threshold voltage generation part  143 . The comparison signal DIN 1 UVD becomes a low level when V 1 &gt;Vth 1 L, and becomes a high level when V 1 &lt;Vth 1 L. 
     The comparator  154  operates by receiving the power supply voltage VDD and generates a comparison signal DIN 2 OVD by comparing the input voltage V 2  inputted to a non-inverting input terminal (+) from the DIN 2  pin and the upper threshold voltage Vth 2 H inputted to an inverting input terminal (−) from the threshold voltage generation part  144 . The comparison signal DIN 2 OVD becomes a high level when V 2 &gt;Vth 2 H, and becomes a low level when V 2 &lt;Vth 2 H. 
     The comparator  155  operates by receiving the power supply voltage VDD and generates a comparison signal DIN 2 UVD by comparing the input voltage V 2  inputted to an inverting input terminal (−) from the DIN 2  pin and the lower threshold voltage Vth 2 L inputted to a non-inverting input terminal (+) from the threshold voltage generation part  145 . The comparison signal DIN 2 UVD becomes a low level when V 2 &gt;Vth 2 L, and becomes a high level when V 2 &lt;Vth 2 L. 
     The comparator  156  operates by receiving the power supply voltage VDD and generates a comparison signal DIN 3 OVD by comparing the input voltage V 3  inputted to a non-inverting input terminal (+) from the DIN 3  pin and the upper threshold voltage Vth 3 H inputted to an inverting input terminal (−) from the threshold voltage generation part  146 . The comparison signal DIN 3 OVD becomes a high level when V 3 &gt;Vth 3 H, and becomes a low level when V 3 &lt;Vth 3 H. 
     The comparator  157  operates by receiving the power supply voltage VDD and generates a comparison signal DIN 3 UVD by comparing the input voltage V 3  inputted to an inverting input terminal (−) from the DIN 3  pin and the lower threshold voltage Vth 3 L inputted to a non-inverting input terminal (+) from the threshold voltage generation part  147 . The comparison signal DIN 3 UVD becomes a low level when V 3 &gt;Vth 3 L, and becomes a high level when V 3 &lt;Vth 3 L. 
     The comparator  158  operates by receiving the power supply voltage VDD and generates a comparison signal DIN 4 OVD by comparing the input voltage V 4  inputted to a non-inverting input terminal (+) from the DIN 4  pin and the upper threshold voltage Vth 4 H inputted to an inverting input terminal (−) from the threshold voltage generation part  148 . The comparison signal DIN 4 OVD becomes a high level when V 4 &gt;Vth 4 H, and becomes a low level when V 4 &lt;Vth 4 H. 
     The comparator  159  operates by receiving the power supply voltage VDD and generates a comparison signal DIN 4 UVD by comparing the input voltage V 4  inputted to an inverting input terminal (−) from the DIN 4  pin and the lower threshold voltage Vth 4 L inputted to a non-inverting input terminal (+) from the threshold voltage generation part  149 . The comparison signal DIN 4 UVD becomes a low level when V 4 &gt;Vth 4 L, and becomes a high level when V 4 &lt;Vth 4 L. 
     The BIST enable signal BIST_EN is inputted to each of the comparators  151  to  159 . That is, each of the comparators  151  to  159  corresponds to a monitoring part (or one of a plurality of monitoring mechanisms included in the monitoring part) which becomes a self-diagnosis target at the startup time of the monitoring IC  100 . 
     The oscillator  161  operates by receiving the power supply voltage VDD and the reference voltage VREF, and generates a clock signal CLK 1  having an oscillation frequency f 1  (for example, f 1 =2.2 MHz) used in the digital processing part  170 . 
     The oscillator  162  operates by receiving the power supply voltage VDD and the reference voltage VREF, and generates a clock signal CLK 2  having an oscillation frequency f 2  (for example, f 2 =500 kHz) used in the digital processing part  170  (particularly the watchdog timer  173 ). The oscillation frequency f 2  of the clock signal CLK 2  can be arbitrarily adjusted by the resistor R 11  (see  FIG. 1 ) externally attached to the RTW pin. 
     Each of the oscillators  161  and  162  is reset by the low voltage abnormality signal UVLO. More specifically, each of the oscillators  161  and  162  comes into a reset state (i.e., disable state) when the low voltage abnormality signal UVLO is at a low level, and comes into a reset release state (i.e., enable state) when the low voltage abnormality signal UVLO is at a high level. 
     The digital processing part  170  operates by receiving the power supply voltage VDD, and performs a process of monitoring various input signals and a process of generating various output signals. Furthermore, the digital processing part  170  is reset by the low voltage abnormality signal UVLO. More specifically, the digital processing part  170  comes into a reset state (i.e., disable state) when the low voltage abnormality signal UVLO is at a low level, and comes into a reset release state (i.e., enable state) when the low voltage abnormality signal UVLO is at a high level. The internal configuration and operation of the digital processing part  170  will be described later. 
     The transistor  180  is connected between the RSTOUT pin (i.e., the output terminal of the reset output signal RSTOUT) and the ground terminal, and is turned on and off in response to a gate signal G 0  inputted from the digital processing part  170 . The reset output signal RSTOUT is at a low level (i.e., logic level at the time of reset) when the transistor  181  is turned on, and is at a high level (i.e., logic level at the time of reset release) when the transistor  181  is turned off. 
     The transistor  181  is connected between the PG 1  pin (i.e., the output terminal of the power good signal PG 1 ) and the ground terminal, and is turned on and off in response to a gate signal G 1  inputted from the digital processing part  170 . The power good signal PG 1  is at a low level (i.e., logic level at the abnormal time) when the transistor  181  is turned on, and is at a high level (i.e., logic level at the normal time) when the transistor  181  is turned off. 
     The transistor  182  is connected between the PG 2  pin (i.e., the output terminal of the power good signal PG 2 ) and the ground terminal, and is turned on and off in response to a gate signal G 2  inputted from the digital processing part  170 . The power good signal PG 2  is at a low level (i.e., logic level at the abnormal time) when the transistor  182  is turned on, and is at a high level (i.e., logic level at the normal time) when the transistor  182  is turned off. 
     The transistor  183  is connected between the PG 3  pin (i.e., the output terminal of the power good signal PG 3 ) and the ground terminal, and is turned on and off in response to a gate signal G 3  inputted from the digital processing part  170 . The power good signal PG 3  is at a low level (i.e., logic level at the abnormal time) when the transistor  183  is turned on, and is at a high level (i.e., logic level at the normal time) when the transistor  183  is turned off. 
     The transistor  184  is connected between the PG 4  pin (i.e., the output terminal of the power good signal PG 4 ) and the ground terminal, and is turned on and off in response to a gate signal G 4  inputted from the digital processing part  170 . The power good signal PG 4  is at a low level (i.e., logic level at the abnormal time) when the transistor  184  is turned on, and is at a high level (i.e., logic level at the normal time) when the transistor  184  is turned off. 
     The buffer  190  operates by receiving the power supply voltage VDD, buffers an input signal (i.e., internal watchdog enable signal WDEN 2  described later) inputted from the digital processing part  170 , and outputs the input signal to the WDOUT pin (i.e., output terminal of watchdog output signal WDOUT). 
     &lt;Digital Processing Part&gt; 
     Subsequently, the internal configuration of the digital processing part  170  will be described with reference to  FIG. 2 . The digital processing part  170  of this configuration example includes a self-diagnosis part  171 , a clock detection part  172 , a watchdog timer  173 , filters FLT 0  to FLT 4 , counters CNT 0  to CNT 5 , OR gates OR 0  to OR 4  and OR 10  to OR 14 , an AND gate AND 1 , and an inverter INV 1 . 
     When the monitoring IC  100  is started up, the self-diagnosis part  171  checks each of the reference voltage detection signal VREF_DET and the comparison signals (RSTOVD, RSTUVD, DINxOVD and DINxUVD), whereby the self-diagnosis part  171  performs a self-diagnosis operation (hereinafter abbreviated as BIST) as to whether or not each of the reference voltage detection part  120  and the comparators  150  to  159  is functioning or operating normally and generates a BIST error signal BIST_ERROR. The BIST error signal BIST_ERROR becomes a high level when an abnormality is detected in any one of the reference voltage detection part  120  and the comparators  150  to  159 . 
     In addition, the self-diagnosis part  171  generates a BIST enable signal BIST_EN and sends it to each of the reference voltage detection part  120  and the comparators  150  to  159 . The BIST enable signal BIST_EN is at a high level during execution of the BIST. 
     The clock detection part  172  detects a frequency abnormality of the clock signals CLK 1  and CLK 2  and generates a clock detection signal CLK_DET. The clock detection signal CLK_DET is at a high level when the frequency abnormality of the clock signal CLK 1  or CLK 2  is detected. 
     The watchdog timer  173  counts the number of pulses of the clock signal CLK 2 , and raises the watchdog detection signal WDT_DET to a high level (i.e., logic level at the abnormal time) when the counter value reaches a SLOW abnormality detection threshold value. However, the counter value of the watchdog timer  173  is reset by the pulse of the watchdog input signal WDIN inputted from the WDIN pin. Therefore, as long as the pulse of the watchdog input signal WDIN is periodically inputted until the counter value of the watchdog timer  173  reaches the SLOW abnormality detection threshold value, the watchdog detection signal WDT_DET is kept at a low level (i.e., logic level at the normal time). The watchdog timer  173  also has a function of detecting a FAST abnormality of the watchdog input signal WDIN. More specifically, when the counter value does not reach a FAST abnormality detection threshold value (&lt;SLOW abnormality detection threshold value) during the pulse period of the watchdog input signal WDIN, the watchdog timer  173  raises the watchdog detection signal WDT_DET to a high level. The WDIN pin is pulled down inside the monitoring IC  100 . 
     The OR gate OR 0  performs an OR operation of the comparison signals RSTOVD and RSTUVD. Therefore, the output signal of the OR gate OR 0 becomes a high level when at least one of the comparison signals RSTOVD and RSTUVD is at a high level, and becomes a low level when both the comparison signals RSTOVD and RSTUVD are at a low level. 
     The OR gate OR 1  performs an OR operation of the comparison signals DIN 1 OVD and DIN 1 UVD. Therefore, the output signal of the OR gate OR 1  becomes a high level when at least one of the comparison signals DIN 1 OVD and DIN 1 UVD is at a high level, and becomes a low level when both the comparison signals DIN 1 OVD and DIN 1 UVD are at a low level. 
     The OR gate OR 2  performs an OR operation of the comparison signals DIN 2 OVD and DIN 2 UVD. Therefore, the output signal of the OR gate OR 2  becomes a high level when at least one of the comparison signals DIN 2 OVD and DIN 2 UVD is at a high level, and becomes a low level when both the comparison signals DIN 2 OVD and DIN 2 UVD are at a low level. 
     The OR gate OR 3  performs an OR operation of the comparison signals DIN 3 OVD and DIN 3 UVD. Therefore, the output signal of the OR gate OR 3  becomes a high level when at least one of the comparison signals DIN 3 OVD and DIN 3 UVD is at a high level, and becomes a low level when both the comparison signals DIN 3 OVD and DIN 3 UVD are at a low level. 
     The OR gate OR 4  performs an OR operation of the comparison signals DIN 4 OVD and DIN 4 UVD. Therefore, the output signal of the OR gate OR 4  becomes a high level when at least one of the comparison signals DIN 4 OVD and DIN 4 UVD is at a high level, and becomes a low level when both the comparison signals DIN 4 OVD and DIN 4 UVD are at a low level. 
     Each of the filters FLT 0  to FLT 4  performs a predetermined filtering process on the output signals of the OR gates OR 0  to OR 4  and outputs the result to a subsequent stage. However, the filters FLT 0  to FLT 4  are not indispensable components. When there is no concern of noise or the like, the filters FLT 0  to FLT 4  may be omitted and the output signals of the OR gates OR 0  to OR 4  may be passed to the subsequent stage. 
     Each of the counters CNT 0  to CNT 4  performs a predetermined counter process on the output signals of the filters FLT 0  to FLT 4  and outputs the result to a subsequent stage. The output signal of the counter CNT 0  is outputted to the OR gate OR 10  as a reset input detection signal RST_IN. However, the counters CNT 0  to CNT 4  are not indispensable components. When there is no concern of noise or the like, the counters CNT 0  to CNT 4  may be omitted and the output signals of the OR gates OR 0  to OR 4  (or the output signals of the filters FLT 0  to FLT 4 ) may be passed to a subsequent stage. 
     The OR gate OR 10  performs a logical sum operation of the reference voltage detection signal VREF_DET, the reset input detection signal RSTIN_DET, the BIST abnormality detection signal BIST_ERROR, the watchdog detection signal WDT_DET and the clock detection signal CLK_DET, thereby generating a reset output detection signal RSTOUT_DET. Therefore, the reset output detection signal RSTOUT_DET becomes a high level when any one of a plurality of input signals is at a high level, and becomes a low level when all of them are at a low level. The reset output detection signal RSTOUT_DET is outputted to the gate of the transistor  180  as the aforementioned gate signal G 0 . 
     The OR gates OR 11  to OR 14  generate power good detection signals PG 1 _DET to PG 4 _DET, respectively, by performing a logical sum operation of the output signals of the counters CNT 1  to CNT 4  and the reference voltage detection signal VREF_DET. Therefore, when the reference voltage detection signal VREF_DET is at a low level, the output signals of the counters CNT 1  to CNT 4  are directly outputted as the power good detection signals PG 1 _DET to PG 4 _DET. On the other hand, when the reference voltage detection signal VREF_DET is at a high level, all the power good detection signals PG 1 _DET to PG 4 _DET are fixed or set to a high level irrespective of the output signals of the counters CNT 1  to CNT 4 . The power good detection signals PG 1 _DET to PG 4 _DET are outputted to the gates of the transistors  181  to  184  as the aforementioned gate signals G 1  to G 4 , respectively. 
     The counter CNT 5  performs a predetermined counter process on the watchdog enable signal WDEN inputted from the WDEN pin and outputs the result. The WDEN pin is pulled down inside the monitoring IC  100 . However, the counter CNT 5  is not an indispensable component. When there is no concern of noise or the like, the counter CNT 5  may be omitted and the watchdog enable signal WDEN may be passed to a subsequent stage. 
     The inverter INV 1  logically inverts the reset output detection signal RSTOUT_DET and outputs the same. Therefore, the output signal of the inverter INV 1  becomes a low level when the reset output detection signal RSTOUT_DET is at a high level (i.e., logic level at the time of abnormality detection), and becomes a high level when the reset output detection signal RSTOUT_DET is at a low level (i.e., logic level at the time of non-detection of abnormality). 
     The AND gate AND 1  performs a logical product operation of the output signal of the counter CNT 5  and the output signal of the inverter INV 1 , and outputs the result to the watchdog timer  173  as an internal watchdog enable signal WDEN 2 . Therefore, when the output signal of the inverter INV 1  is at a high level, the output signal of the counter CNT 5  is directly outputted as the internal watchdog enable signal WDEN 2 . On the other hand, when the output signal of the inverter INV 1  is at a low level, the internal watchdog enable signal WDEN 2  is fixed or set to a low level irrespective of the output signal of the counter CNT 5 . 
     The watchdog timer  173  becomes valid (i.e., enable state) when the internal watchdog enable signal WDEN 2  is at a high level, and becomes invalid (i.e., disable state) when the internal watchdog enable signal WDEN 2  is at a low level. 
     The internal watchdog enable signal WDEN 2  is outputted to the WDOUT pin (i.e., the output terminal of the watchdog output signal WDOUT) via the buffer  190 . That is, the watchdog output signal WDOUT is a binary signal equivalent to the internal watchdog enable signal WDEN 2 , and serves as a status signal for notifying the microcomputer  300  of the validity/invalidity of the watchdog timer  173 . 
     The monitoring IC  100  having the above configuration has a self-diagnosis function of the monitoring mechanism, a self-monitoring function of the internal clock, a monitoring function of the control terminal, and the like in order to increase the failure detection rate. In the following, these new functions will be specifically described one by one. 
     &lt;Startup Sequence&gt; 
       FIG. 3  is a schematic diagram showing a first startup sequence (i.e., general startup sequence) in the electronic device  1 . In the startup sequence of this figure, after the power supply is started up by the power management IC  200 , the monitoring IC  100  and the microcomputer  300  start their respective operations in response to the reset release from the power management IC  200 . 
     Thus, the general startup sequence is not intended for the monitoring IC  100  with a self-diagnosis function. Therefore, the execution timing of the BIST in the monitoring IC  100  is after the reset release from the power management IC  200 , consequently affecting the startup time of the entire electronic device  1 . Moreover, the microcomputer  300  cannot determine the execution timing of the BIST. In the following, a second startup sequence that can solve such problems is suggested. 
       FIG. 4  is a schematic diagram showing a second startup sequence (i.e., new startup sequence) in the electronic device  1 . In the startup sequence of this figure, after the power supply is started up by the power management IC  200 , a BIST is performed in the monitoring IC  100  until a predetermined reset release waiting time t 1  (to be described in detail later) elapses. Then, if no abnormality is detected in the monitoring IC  100 , a monitoring operation is promptly started. Furthermore, the reset release of the microcomputer  300  is performed when the reset release waiting time t 1  elapses (e.g., on or after the elapse time point). As a result, the operation of the microcomputer  300  is started. 
     As described above, the monitoring IC  100  is provided with both the self-diagnosis function and the reset output function. By adopting such a configuration, the BIST can be performed without any influence on the operation start timing of the microcomputer  300 , so that the electronic device  1  can be started up at the same timing as before. 
     In addition, the monitoring IC  100  can start the original monitoring operation after self-diagnosing whether or not the monitoring IC  100  operates normally. Therefore, it is possible to increase the failure detection rate. 
       FIG. 5  is a timing chart for more specifically explaining the above-described second startup sequence. From the upper stage to the middle stage of this figure, the self-monitoring states of the operation state (STATE) of the monitoring IC  100 , the power supply voltage VDD, the reset input signal RSTIN (i.e., corresponding to the input voltage V 0  in  FIG. 2 ), the reset output signal RSTOUT, the low voltage abnormality signal UVLO, various detection signals (VREF_DET, RSTIN_DET and PGx_DET) in a normal mode, various detection signals (VREF_DET, RSTIN_DET and PGx_DET) in a BIST mode and the clock signals CLK 1  and CLK 2  are depicted sequentially from the upper side. 
     In the lower stage of the figure, the operation start behaviors (STATE, WDEN and WDT) of the watchdog timer  173  are divisionally depicted as a first case (i.e., for example, a case where the WDEN pin is short-circuited to the VDD pin outside the IC and a second case (i.e., a case where the WDEN pin is controlled by the microcomputer  300 ). 
     The signals hatched in the figure indicate that the respective detection operations (or the generation operations) are active. 
     When the power management IC  200  is started up to supply the power supply voltage VDD to the monitoring IC  100 , the detection operation of the low voltage abnormality signal UVLO becomes active. If the power supply voltage VDD rises to the low voltage abnormality release value UVLO_OFF, the monitoring IC  100  is shifted from an OFF state to a STBY state. The OFF state corresponds to a state in which all the circuit parts except the UVLO part  130  are shut down. On the other hand, the STBY state corresponds to a state in which UVLO is released and the oscillators  161  and  162  are starting their respective oscillation operations. In the STBY state, the detection operations of the reference voltage detection signal VREF_DET and the reset input detection signal RSTIN_DET become active. The low voltage abnormality release value UVLO_OFF may be set based on the minimum operable voltage of the monitoring IC  100 . 
     Thereafter, if the reset input signal RSTIN (i.e., the divided voltage of the power supply voltage VDD) rises to the reset release value RST_OFF, the monitoring IC  100  is shifted from the STBY state to the BIST state. Then, the self-monitoring operation of the clock signals CLK 1  and CLK 2  becomes active. Simultaneously with the shift from the STBY state to the BIST state, the count of the reset release waiting time t 1  (for example, 10 ms) is started. The reset release value RST_OFF may be set based on the minimum operable voltage of the microcomputer  300 . 
     The BIST state may be subdivided into three states, i.e., a BIST_STBY state (corresponding to the start standby state of the BIST), a BIST_WORK state (corresponding to the execution state of the BIST) and a BIST_STBY2 state (corresponding to the result determination state of the BIST). 
     In particular, in the BIST_WORK state, the detection operations of the reference voltage detection signal VREF_DET, the reset input detection signal RSTIN_DET and the power good detection signal PGx_DET are sequentially made active. The method of BIST will be described in detail later with specific examples. 
     In addition, the BIST required time t 2  for circulating the above three states is sufficiently shorter than the above-described reset release waiting time t 1  (may be, for example, about 1 ms). 
     When the BIST normally comes to an end, the monitoring IC  100  is shifted from the BIST state to the ON 1  state. Then, all the detection operations of the reference voltage detection signal VREF_DET, the reset input detection signal RSTIN_DET and the power good detection signal PGx_DET (i.e., the original monitoring operations) are made active. The ON 1  state corresponds to a state available until the BIST normally comes to an end and the reset of the reset output signal RSTOUT is released. 
     Thereafter, when the reset release waiting time t 1  elapses, the monitoring IC  100  is shifted from the ON 1  state to the ON 2  state, the reset output signal RSTOUT rises to a high level, and the reset of the microcomputer  300  is released. However, at this point in time, the watchdog timer  173  remains invalid. In this manner, the ON 2  state corresponds to a state available until the watchdog timer  173  starts the detection operation after the reset of the microcomputer  300  is released. 
     As shown in the first case, when the WDEN pin is short-circuited to the VDD pin outside the monitoring IC  100  and when the watchdog enable signal WDEN is at a high level before the shift to the ON 2  state, the monitoring IC  100  is shifted from the ON 2  state to the ON 3  state at the time at which a predetermined watchdog waiting time t 3  (for example, 500 ms) elapses after the reset output signal RSTOUT is raised to a high level. The watchdog timer  173  starts the detection operation. 
     On the other hand, as shown in the second case, when the watchdog enable signal WDEN is controlled by the microcomputer  300  and when the watchdog enable signal WDEN is set to a high level after the shift to the ON 2  state, the monitoring IC  100  is shifted from the ON 2  state to the ON 3  state without delay at the time at which the watchdog enable signal WDEN is raised to a high level. The watchdog timer  173  starts the detection operation. 
     As described above, the monitoring IC  100  includes a monitoring part (i.e., the reference voltage detection part  120  and the comparators  150  to  159 ) for detecting an abnormality of a monitoring target, a self-diagnosis part  171  for diagnosing whether or not the monitoring part is normally functioning during a period from the start of the power supply to the elapse of the reset release waiting time t 1 , and a reset control part (see the reset control part CTRL in  FIGS. 25 and 26 ) for releasing the reset of the reset output signal RSTOUT after the reset release waiting time t 1  elapses. By adopting such a configuration, it is possible to increase the failure detection rate without affecting the startup timing of the electronic device  1 . 
     The monitoring IC  100  performs the BIST until a predetermined reset release waiting time t 1  elapses after the reset input signal RSTIN reaches a reset release value RST_OFF. After confirming that its own monitoring function is normal, the monitoring IC  100  releases the reset of the reset output signal RSTOUT. The microcomputer  300  does not merely incorporate the conventional power-on reset function (i.e., the function of immediately releasing the reset when the monitoring target voltage reaches a predetermined value). 
       FIG. 6  is a state transition diagram (i.e., state machine diagram) showing the second startup sequence. Various states (OFF, STBY, BIST, ON 1 , ON 2  and ON 3 ) in this figure correspond to the various states shown in  FIG. 5 . 
     Briefly, the OFF state is shifted to the STBY state by UVLO=H. The STBY state is shifted to the BIST state by VREF_DET=RSTIN_DET=L. The BIST state is shifted to the ON 1  state by OK determination. The ON 1  state is shifted to the ON 2  state by RSTOUT=H. The ON 2  state is shifted to the ON 3  state by WDOUT=H and is shifted to the ON 1  state by RSTOUT=L. The ON 3  state is shifted to the ON 2  state by WDOUT=L and is shifted to the BIST state by RSTOUT=L. 
     Incidentally, as the number of diagnosis targets of the BIST (the reference voltage detection part  120  and the comparators  150  to  159  in the present configuration example) increases, an unintended NG determination is likely to occur in the BIST state due to a transient external factor such as noise or the like. If such an NG determination is trusted with ease and a subsequent process is stopped, it is impossible to normally start up the monitoring IC  100 , which is very inconvenient. 
     Therefore, the self-diagnosis part  171  repeats the diagnosis until it is confirmed that the diagnosis target of the BIST is functioning normally. That is, as shown in  FIG. 6 , the BIST state is repeated any number of times as long as the NG determination is made. At this time, as a matter of course, the reset output signal RSTOUT is kept at a low level. In addition, the self-diagnosis part  171  raises the BIST error signal BIST_ERROR to a high level and stores a BIST error flag in a register (details of which will be described later). 
     By adopting such a startup sequence, even if a transient abnormality occurs in the diagnosis result of the BIST, a true diagnosis result can be obtained by repeating the BIST. Accordingly, it is possible to improve the noise immunity of the monitoring IC  100 . 
     As described above, the BIST required time t 2  is sufficiently shorter than the reset release waiting time t 1 . Therefore, even if the BIST is repeated twice or three times, the reset release timing of the microcomputer  300  is not delayed. 
     &lt;Test Circuit&gt; 
       FIG. 7  is a circuit diagram showing a configuration example of a test circuit. As shown in the figure, the monitoring IC  100  incorporates a plurality of test circuits (T 1 , T 2  and T 10  to T 14 ) as a means for implementing the BIST described above. 
     The test circuits T 1  and T 2  are attached to the reference voltage detection part  120 . More specifically, the reference voltage detection part  120  includes divided voltage generation parts  121  and  122 , and comparators  123  and  124 . The test circuits T 1  and T 2  are connected to the divided voltage generation parts  121  and  122 , respectively. 
     The divided voltage generation part  121  generates divided voltages Vd 1 H and Vd 1 L (where Vd 1 H&gt;Vd 1 L) from the reference voltage VREF. 
     The divided voltage generation part  122  generates divided voltages Vd 2 H and Vd 2 L (where Vd 2 H&gt;Vd 2 L) from the sub reference voltage VREF 2 . 
     The comparator  123  generates a comparison signal VRDET 1  by comparing the divided voltage Vd 2 H inputted to a non-inverting input terminal (+) and the divided voltage Vd 1 L inputted to an inverting input terminal (−). The comparison signal VRDET 1  becomes a high level when Vd 2 H&gt;Vd 1 L, and becomes a low level when Vd 2 H&lt;Vd 1 L. 
     The comparator  124  generates a comparison signal VRDET 2  by comparing the divided voltage Vd 1 H inputted to a non-inverting input terminal (+) and the divided voltage Vd 2 L inputted to an inverting input terminal (−). The comparison signal VRDET 2  becomes a high level when Vd 1 H&gt;Vd 2 L, and becomes a low level when Vd 1 H&lt;Vd 2 L. 
     The test circuit T 1  is connected to a midpoint node A (i.e., an intermediate node sandwiched between the output terminals of the divided voltages Vd 1 H and Vd 1 L) of the divided voltage generation part  121 . The test circuit T 1  switches the voltage value of the midpoint node A in response to the control signal VRDET 1 SW. More specifically, the test circuit T 1  opens the midpoint node A when VRDET 1 SW=L, and short-circuits the midpoint node A to the ground terminal when VRDET 1 SW=H. 
     The test circuit T 2  is connected to a midpoint node B (i.e., an intermediate node sandwiched between the output terminals of the divided voltages Vd 2 H and Vd 2 L) of the divided voltage generation part  122 . The test circuit T 2  switches the voltage value of the midpoint node B in response to the control signal VRDET 2 SW. More specifically, the test circuit T 2  opens the midpoint node B when VRDET 2 SW=L, and short-circuits the midpoint node B to the ground terminal when VRDET 2 SW=H. 
     The test circuit T 10  is connected to the input terminal of the input voltage V 0 . The test circuit T 10  switches the voltage value of the input voltage V 0  in response to the control signals RSTSW 1  to RSTSW 4  (i.e., binary signals alternatively set to a high level). More specifically, the test circuit T 10  sets V 0  to RSTIN when RSTSW 1 =H, sets V 0  to V 0 H (for example, 1.04 V) when RSTSW 2 =H, sets V 0  to V 0 M (for example, 0.8 V) when RSTSW 3 =H, and sets V 0  to V 0 L (for example, 0.56 V) when RSTSW 4 =H. The three test input voltages (V 0 H, V 0 M and V 0 L) may be respectively generated by dividing the reference voltage VREF. 
     The test circuit T 11  is connected to the input terminal of the input voltage V 1 . The test circuit T 11  switches the voltage value of the input voltage V 1  in response to the control signals DIN 1 SW 1  to DIN 1 SW 4  (i.e., binary signals alternatively set to a high level). More specifically, the test circuit T 11  sets V 1  to DIN 1  when DIN 1 SW 1 =H, sets V 1  to V 1 H (for example, 1.04 V) when DIN 1 SW 2 =H, sets V 1  to V 1 M (for example, 0.8 V) when DIN 1 SW 3 =H, and sets V 1  to V 1 L (for example, 0.56 V) when DIN 1 SW 4 =H. The three test input voltages (V 1 H, V 1 M and V 1 L) may be respectively generated by dividing the reference voltage VREF. 
     The test circuit T 12  is connected to the input terminal of the input voltage V 2 . The test circuit T 12  switches the voltage value of the input voltage V 2  in response to the control signals DIN 2 SW 1  to DIN 2 SW 4  (i.e., binary signals alternatively set to a high level). More specifically, the test circuit T 12  sets V 2  to DIN 2  when DIN 2 SW 1 =H, sets V 2  to V 2 H (for example, 1.04 V) when DIN 2 SW 2 =H, sets V 2  to V 2 M (for example, 0.8 V) when DIN 2 SW 3 =H, and sets V 2  to V 2 L (for example, 0.56 V) when DIN 2 SW 4 =H. The three test input voltages (V 2 H, V 2 M and V 2 L) may be respectively generated by dividing the reference voltage VREF. 
     The test circuit T 13  is connected to the input terminal of the input voltage V 3 . The test circuit T 13  switches the voltage value of the input voltage V 3  in response to the control signals DIN 3 SW 1  to DIN 3 SW 4  (i.e., binary signals alternatively set to a high level). More specifically, the test circuit T 13  sets V 3  to DIN 3  when DIN 3 SW 1 =H, sets V 3  to V 3 H (for example, 1.04 V) when DIN 3 SW 2 =H, sets V 3  to V 3 M (for example, 0.8 V) when DIN 3 SW 3 =H, and sets V 3  to V 3 L (for example, 0.56 V) when DIN 3 SW 4 =H. The three test input voltages (V 3 H, V 3 M and V 3 L) may be respectively generated by dividing the reference voltage VREF. 
     The test circuit T 14  is connected to the input terminal of the input voltage V 4 . The test circuit T 14  switches the voltage value of the input voltage V 4  in response to the control signals DIN 4 SW 1  to DIN 4 SW 4  (i.e., binary signals alternatively set to a high level). More specifically, the test circuit T 14  sets V 4  to DIN 4  when DIN 4 SW 1 =H, sets V 4  to V 4 H (for example, 1.04 V) when DIN 4 SW 2 =H, sets V 4  to V 4 M (for example, 0.8 V) when DIN 4 SW 3 =H, and sets V 4  to V 4 L (for example, 0.56 V) when DIN 4 SW 4 =H. The three test input voltages (V 4 H, V 4 M and V 4 L) may be respectively generated by dividing the reference voltage VREF. 
     &lt;BIST&gt; 
       FIG. 8  is a timing chart showing a first embodiment of the BIST. The power supply voltage VDD, the reset input signal RSTIN, the reset output signal RSTOUT, the operation state (STATE) of the monitoring IC  100 , the BIST enable signal BIST_EN, the counter value (COUNT) of the clock signal CLK 1 , various control signals (VRDET 1 SW, VRDET 2 SW, RSTSW 1  to RSTSW 4 , DIN 1 SW 1  to DIN 1 SW 4 , DIN 2 SW 1  to DIN 2 SW 4 , DIN 3 SW 1  to DIN 3 SW 4  and DIN 4 SW 1  to DIN 4 SW 4 ), the counter value COUNT (the same as the previous one), various detection signals (VRDET 1 , VRDET 2 , RSTOVD, RSTUVD, DIN 1 OVD, DIN 1 UVD, DIN 2 OVD, DIN 2 UVD, DIN 3 OVD, DIN 3 UVD, DIN 4 OVD and DIN 4 UVD) are depicted sequentially from the upper side. 
     At the increment timing of the counter value COUNT, the upward arrows attached to the various detection signals indicate the comparison timing for determining the match/mismatch of the detected value and the expected value. 
     As shown in this figure, the detection operation of the BIST is sequentially advanced in synchronization with the counter value COUNT of the clock signal CLK 1 . The rising timing of the BIST enable signal BIST_EN and the increment timing of the counter value COUNT are asynchronous with each other. Therefore, the delay time t 11  from the rise of the BIST enable signal BIST_EN to the high level to the start of the increment of the counter value COUT is 0 μs at the minimum and is equal to the increment period t 12  (for example, several tens μs) of the counter value COUNT at the maximum. 
     When COUNT=“1”, the control signals (RSTSW 1 , DIN 1 SW 1 , DIN 2 SW 1 , DIN 3 SW 1  and DIN 4 SW 1 ) among the various control signals are at a high level, and all other control signals are at a low level. Therefore, both the nodes A and B in  FIG. 7  are opened. In addition, V 0 =RSTIN, V 1 =DIN′, V 2 =DIN 2 , V 3 =DIN 3 , and V 4 =DIN 4 . 
     When COUNT=“2”, the control signals (RSTSW 3 , DIN 1 SW 3 , DIN 2 SW 3 , DIN 3 SW 3  and DIN 4 SW 3 ) among the various control signals are at a high level, and all other control signals are at a low level. Therefore, both the nodes A and B in  FIG. 7  are kept opened. In addition, V 0 =V 0 M, V 1 =V 1 M, V 2 =V 2 M, V 3 =V 3 M, and V 4 =V 4 M. At this time, if the monitoring part (the reference voltage detection part  120  and the comparators  150  to  159 ) to be diagnosed by the BIST is normal, all the detection signals should be at a low level. 
     When COUNT=“3”, the control signal VRDET 1 SW goes to a high level while taking the state of COUNT=“2” as a base. Therefore, the node A in  FIG. 7  is short-circuited to the ground terminal. At this time, if the monitoring part is normal, only the detection signal VRDET 1  is at a high level and all other detection signals should be at a low level. 
     When COUNT=“4”, the control signal VRDET 2 SW goes to a high level while taking the state of COUNT=“2” as a base. Therefore, the node B in  FIG. 7  is short-circuited to the ground terminal. At this time, if the monitoring part is normal, only the detection signal VRDET 2  is at a high level and all other detection signals should be at a low level. 
     When COUNT=“5”, the control signal RSTSW 2  goes to a high level and the control signal RSTSW 3  goes to a low level while taking the state of COUNT=“2” as a base. Therefore, V 0 =V 0 H. At this time, if the monitoring part is normal, only the detection signal RSTOVD is at a high level and all other detection signals should be at a low level. 
     When COUNT=“6”, the control signal RSTSW 4  goes to a high level and the control signal RSTSW 3  goes to a low level while taking the state of COUNT=“2” as a base. Therefore, V 0 =V 0 L. At this time, if the monitoring part is normal, only the detection signal RSTUVD is at a high level and all other detection signals should be at a low level. 
     When COUNT=“7”, the state is returned to the same state as the state of COUNT=“2”. Therefore, if the monitoring part is normal, all the detection signals should be at a low level. 
     When COUNT=“8”, the control signal DIN 1 SW 2  goes to a high level and the control signal DIN 1 SW 3  goes to a low level while taking the state of COUNT=“7” as a base. Therefore, V 1 =V 1 H. At this time, if the monitoring part is normal, only the detection signal DIN 1 OVD is at a high level and all other detection signals should be at a low level. 
     When COUNT=“9”, the control signal DIN 1 SW 4  goes to a high level and the control signal DIN 1 SW 3  goes to a low level while taking the state of COUNT=“7” as a base. Therefore, V 1 =V 1 L. At this time, if the monitoring part is normal, only the detection signal DIN 1 UVD is at a high level and all other detection signals should be at a low level. 
     When COUNT=“A”, the state is returned to the same state as the state of COUNT=“7”. Therefore, if the monitoring part is normal, all the detection signals should be at a low level. 
     When COUNT=“B”, the control signal DIN 2 SW 2  goes to a high level and the control signal DIN 2 SW 3  goes to a low level while taking the state of COUNT=“A” as a base. Therefore, V 2 =V 2 H. At this time, if the monitoring part is normal, only the detection signal DIN 2 OVD is at a high level and all other detection signals should be at a low level. 
     When COUNT=“C”, the control signal DIN 2 SW 4  goes to a high level and the control signal DIN 2 SW 3  goes to a low level while taking the state of COUNT=“A” as a base. Therefore, V 2 =V 2 L. At this time, if the monitoring part is normal, only the detection signal DIN 2 UVD is at a high level and all other detection signals should be at a low level. 
     When COUNT=“D”, the state is returned to the same state as the state of COUNT=“A”. Therefore, if the monitoring part is normal, all the detection signals should be at a low level. 
     When COUNT=“E”, the control signal DIN 3 SW 2  goes to a high level and the control signal DIN 3 SW 3  goes to a low level while taking the state of COUNT=“D” as a base. Therefore, V 3 =V 3 H. At this time, if the monitoring part is normal, only the detection signal DIN 3 OVD is at a high level and all other detection signals should be at a low level. 
     When COUNT=“F”, the control signal DIN 3 SW 4  goes to a high level and the control signal DIN 3 SW 3  goes to a low level while taking the state of COUNT=“D” as a base. Therefore, V 3 =V 3 L. At this time, if the monitoring part is normal, only the detection signal DIN 3 UVD is at a high level and all other detection signals should be at a low level. 
     When COUNT=“10”, the state is returned to the same state as the state of COUNT=“D”. Therefore, if the monitoring part is normal, all the detection signals should be at a low level. 
     When COUNT=“11”, the control signal DIN 4 SW 2  goes to a high level and the control signal DIN 4 SW 3  goes to a low level while taking the state of COUNT=“10” as a base. Therefore, V 4 =V 4 H. At this time, if the monitoring part is normal, only the detection signal DIN 4 OVD is at a high level and all other detection signals should be at a low level. 
     When COUNT=“12”, the control signal DIN 4 SW 4  goes to a high level and the control signal DIN 4 SW 3  goes to a low level while taking the state of COUNT=“10” as a base. Therefore, V 4 =V 4 L. At this time, if the monitoring part is normal, only the detection signal DIN 4 UVD is at a high level and all other detection signals should be at a low level. 
     When COUNT=“13” to “16”, the state is returned to the same state as the state of COUNT=“10”, and is then returned to the same state as the state of COUNT=“1”, whereby a series of BIST comes to an end. 
     By the way, in the BIST of the present embodiment, attention is paid only to the detection signal of the comparator to which the test input voltage is inputted, and the match/mismatch of the detected value and the expected value is determined. For example, when COUNT=“8”, the test input voltage V 1 H higher than the upper threshold voltage Vth 1 H is inputted as the input voltage V 1  to the comparator  152 . Therefore, only the detection signal DIN 1 OVD is compared with the expected value. These features may apply to other counter values in the same manner. 
     In such a BIST method, due to the layout factor of the monitoring IC  100  or the like, there is a possibility that, even if a plurality of comparators have an abnormality called “caught detection”, this abnormality may be overlooked. In the following, the “caught detection” will be considered by taking, as an example, a case where the input terminals of the input voltages V 1  and V 2  are short-circuited to each other. 
     For example, in the case of COUNT=“8”, when V 1 =V 1 H, it is originally required that V 2 =V 2 M. However, V 2  becomes substantially equal to V 1 H through a short path between V 1  and V 2 . As a result, not only the detection signal DIN 1 OVD but also the detection signal DIN 2 OVD is caught to become a high level. 
     However, in the case of COUNT=“8”, only the detection signal DIN 1 OVD is compared with the expected value. Therefore, when the detection value of the detection signal DIN 1 OVD matches the expected value, even if the detection value of the detection signal DIN 2 OVD does not match the expected value, the diagnosis result of the BIST is “OK”. 
     On the other hand, in the case of COUNT=“B”, when V 2 =V 2 H, it is originally required that V 1 =V 1 M. However, V 1  becomes substantially equal to V 2 H through a short path between V 1  and V 2 . As a result, not only the detection signal DIN 2 OVD but also the detection signal DIN 1 OVD is caught to become a high level. 
     However, in the case of COUNT=“B”, only the detection signal DIN 2 OVD is compared with the expected value. Therefore, when the detection value of the detection signal DIN 2 OVD matches the expected value, even if the detection value of the detection signal DIN 1 OVD does not match the expected value, the diagnosis result of the BIST is “OK”. 
     As described above, in the BIST of the first embodiment, both of the detection signals DIN 1 OVD and DIN 2 OVD are diagnosed as “OK”. Therefore, the “caught detection” caused by a short-circuit abnormality between V 1  and V 2  is overlooked. 
     In the above description, only the short-circuit abnormality between V 1  and V 2  has been taken as an example. However, in plural embodiments, abnormal patterns of “caught detection” exist just as much as the number of combinations of a plurality of channels. In particular, at the latter stage side (the inside of the chip of the monitoring IC  100 ) of each of the test circuits T 10  to T 14 , the wiring spacing becomes very narrow. Therefore, in terms of layout, there is a high possibility of short-circuiting between the wirings. Ultimately, the “caught detection” is likely to occur. 
     Therefore, in order to improve the reliability of the monitoring IC  100 , it is extremely important to correctly diagnose the “caught detection” described above. In the following, consideration will be given to a second embodiment of the BIST that can solve such a problem. 
       FIG. 9  is a timing chart showing a second embodiment of the BIST. The driving method of various control signals is the same as that of  FIG. 8  described above. However, unlike the first embodiment described above, in the BIST of the present embodiment, the match/mismatch of the detected value and the expected value is determined with respect to not only the comparator to which the test input voltage is inputted but also all the comparators. 
     That is, while serially and sequentially switching diagnosis targets to be inputted with test input signals from among a plurality of monitoring mechanisms (for example, comparators  151  to  159 ) included in the monitoring part, the self-diagnosis part  171  determines whether or not the output signal of the monitoring mechanism serving as a diagnosis target matches the expected value and also determines whether or not the output signal of each of the monitoring mechanisms other than the monitoring mechanism serving as the diagnosis target matches the expected value. 
     For example, when COUNT=“8”, the test input voltage V 1 H is inputted to the comparator  152 . However, with respect to not only the detection signal DIN 1 OVD outputted from the comparator  152  but also other detection signals, the detected value and the expected value are compared one by one. 
     Similarly, when COUNT=“B”, the test input voltage V 2 H is inputted to the comparator  152 . However, with respect to not only the detection signal DIN 1 OVD outputted from the comparator  154  but also other detection signals, the detected value and the expected value are compared one by one. 
     According to such a BIST method, for example, even if the aforementioned “caught detection” has occurred due to the short-circuit abnormality between V 1  and V 2 , it is possible to diagnose the “caught detection” as an abnormality and to make an NG determination. Therefore, it is possible to enhance the reliability of the monitoring IC  100 . 
     However, when a plurality of comparators are inspected at the same time (for example, when V 1 =V 1 H and V 2 =V 2 H at the same timing), even if the output evaluation of all the comparators is performed at all comparison timings, it is impossible to correctly determine the “caught detection”. For this reason, as a solution to the “caught detection”, it is important to evaluate the output of all the comparators at all comparison timings while inspecting the respective comparators one by one. 
     In the above description, the advantage of the second embodiment has been described by paying attention to the “caught detection” occurring between channels. Hereinafter, from a different point of view, the difference between the first embodiment ( FIG. 8 ) and the second embodiment ( FIG. 9 ) will be described. 
       FIG. 10  is a timing chart showing an example of the diagnosis result (without H fixation) obtained by the BIST of the first embodiment ( FIG. 8 ), in which the input voltage V 1  and the detection signals DIN 1 OVD and DIN 1 UVD are depicted sequentially from the upper side. 
     As shown in this figure, for example, when the BIST is executed using the comparators  152  and  153  of  FIG. 7  as diagnosis targets, the self-diagnosis part  171  determines whether or not the detected value of each of the detection signals DIN 1 OVD and DIN 1 UVD matches the expected value, while sequentially switching three test input voltages V 1 H, V 1 M and V 1 L (where V 1 L&lt;Vth 1 L&lt;V 1 M&lt;Vth 1 H&lt;V 1 H) as the input voltage V 1 . 
     In the BIST of the first embodiment ( FIG. 8 ), as indicated by the upward arrows in the figure, only the expected value determination as to whether or not DIN 1 OVD=H is performed during the input period of the test input voltage V 1 H, and only the expected value determination as to whether or not DIN 1 UVD=H is performed during the input period of the test input voltage V 1 L. As a matter of course, if the logic levels of the detection signals DIN 1 OVD and DIN 1 UVD are properly changed in response to the change of the input voltage V 1 , no particular problem occurs even with such a BIST method. 
     However, when the detection signals DIN 1 OVD and DIN 1 UVD are fixed at a high level (i.e., logic level at the abnormal time), an erroneous BIST diagnosis result is obtained. In the following, such a problem will be described in detail. 
       FIG. 11  is a timing chart showing another example of the diagnosis result (with H fixation) obtained by the BIST of the first embodiment ( FIG. 8 ), in which, as in  FIG. 10 , the input voltage V 1  and the detection signals DIN 1 OVD and DIN 1 UVD are depicted sequentially from the upper side. 
     In the example of this figure, both the detection signals DIN 1 OVD and DIN 1 UVD are fixed at a high level (i.e., logic level at the abnormal time). Therefore, if the expected value determination for each of the detection signals DIN 1 OVD and DIN 1 UVD is individually performed during the input period of each of the test input voltages V 1 H and V 1 L, each determination result is “OK”. Therefore, the high-level fixation of the detection signals DIN 1 OVD and DIN 1 UVD may be overlooked. On the other hand, in the BIST of the second embodiment ( FIG. 9 ), the above problem is solved. Hereinafter, description will be made on how to solve the problem. 
       FIG. 12  is a timing chart showing another example of the diagnosis result (without H fixation) obtained by the BIST of the second embodiment, in which as in  FIGS. 10 and 11 , the input voltage V 1  and the detection signals DIN 1 OVD and DIN 1 UVD are depicted sequentially from the upper side. 
     As indicated by the upward arrows in the figure, in the BIST of the second embodiment, the expected value determination of both the detection signals DIN 1 OVD and DIN 1 UVD is performed each time when the voltage value of the input voltage V 1  is switched. More specifically, an expected value determination as to whether or not DIN 1 OVD=H and DIN 1 UVD=L is performed during the input period of the test input voltage V 1 H, and an expected value determination as to whether or not DIN 1 OVD=L and DIN 1 UVD=H is performed during the input period of the test input voltage V 1 L. In addition, an expected value determination as to whether or not DIN 1 OVD=DIN 1 UVD=L is performed during the input period of the test input voltage V 1 M. 
     By performing such an expected value determination, when the detection signals DIN 1 OVD and DIN 1 UVD are not fixed or set at a high level (i.e., logic level indicated at the time of abnormality), the result of the expected value determination becomes “OK” at all timings. 
       FIG. 13  is a timing chart showing another example of the diagnosis result (with H fixation) obtained by the BIST of the second embodiment, in which as in  FIGS. 10 to 12 , the input voltage V 1  and the detection signals DIN 1 OVD and DIN 1 UVD are depicted sequentially from the upper side. 
     As shown in the figure, when the detection signals DIN 1 OVD and DIN 1 UVD are fixed or set at a high level (i.e., logic level indicated at the abnormal time), the expected value determination result becomes “NG” at the timing at which the detection signal DIN 1 OVD or DIN 1 UVD should originally be at a low level. Accordingly, the high-level fixation of the detection signals DIN 1 OVD and DIN 1 UVD is not overlooked. It is therefore possible to increase the failure detection rate of the monitoring IC  100 . 
     &lt;BIST Error Flag&gt; 
       FIG. 14  is a timing chart showing an operation of generating a BIST error signal BIST_ERR. The BIST enable signal BIST_EN, the counter value COUNT, various control signals (VRDET 1 SW, VRDET 2 SW, RSTSW 1  to RSTSW 4 , DIN 1 SW 1  to DIN 1 SW 4 , DIN 2 SW 1  to DIN 2 SW 4 , DIN 3 SW 1  to DIN 3 SW 4 , and DIN 4 SW 1  to DIN 4 SW 4 ), the counter value COUNT (similar to the previous one), various detection signals (VRDET 1 , VRDET 2 , RSTOVD, RSTUVD, DIN 1 OVD, DIN 1 UVD, DIN 2 OVD, DIN 2 UVD, DIN 3 OVD, DIN 3 UVD, DIN 4 OVD, and DIN 4 UVD), and the BIST error signal BIST_ERR are depicted sequentially from the upper side. 
     In this figure, the BIST error signal BIST_ERR rises to a high level (see a circle mark in the figure) as the expected value determination for the detection signal DIN 4 UVD becomes “NG” in a first round BIST. 
     Furthermore, in this figure, a second round BIST is repeated in response to BIST_ERR=H. As a result, the BIST error signal BIST_ERR falls to a low level as the expected value determination of the detection signal DIN 4 UVD becomes “OK”. 
     In this way, by repeating the BIST until BIST_ERR=L, a true diagnosis result can be obtained regardless of a transient external factor such as noise or the like. It is therefore possible to improve the noise immunity of the monitoring IC  100 . This point is the same as described with reference to  FIG. 6 . 
     In addition, the self-diagnosis part  171  raises the BIST error signal BIST_ERROR to a high level when an error is detected in any one of the monitoring targets, and stores a BIST error flag in a register map for specifying the error location or indicating the error object. 
       FIG. 15  is a register map showing a storage area of the BIST error flag. As shown in this figure, in the resister map, the BIST error flags of all the detection signals (DIN 1 OVD, DIN 2 OVD, DIN 3 OVD, DIN 4 OVD, DIN 1 UVD, DIN 2 UVD, DIN 3 UVD, DIN 4 UVD, RSTOVD, RSTUVD, VRDET 1 , VRDET 2 ), which become the monitoring targets of the BIST, are stored in individual addresses. 
     For example, in  FIG. 14  described above, the expected value determination for the detection signal DIN 4 UVD is “NG”. Therefore, the determination result is latched and then written in a predetermined address of the register map (address “D 7 ” of the register name “ERR_BCHECK1”) at a predetermined timing. 
     The BIST error flag can be arbitrarily read from the outside of the monitoring IC  100  by, for example, SPI (Serial Peripheral Interface) communication. With such a configuration, when an error is detected in the BIST, it is possible to specify the error location afterward. By applying the present disclosure to a Q &amp; A method, it is also possible to increase the failure detection rate of the monitoring IC  100 . 
     The aforementioned Q &amp; A method will be supplementarily described. As a future development of the monitoring IC  100 , for example, a system capable of removing a PGx pin and reading a BIST error flag via a communication interface such as an I 2 C (Inter-Integrated Circuit) or an SPI (Serial Peripheral Interface) is conceivable. 
     In this case, when receiving a question signal (question: a command to read the BIST error flag written in the ∘∘ register) from the microcomputer  300  while performing a BIST or an ordinary operation, the monitoring IC  100  transmits an answer signal (answer: BIST error flag requested to be read) responding to the question signal. 
     By periodically performing such Q &amp; A, it is possible for the microcomputer  300  to freely read out where an abnormality is in the monitoring IC  100 . 
     &lt;WDEN-WDOUT&gt; 
       FIG. 16  is a diagram showing a state in which the unidirectional communication of the watchdog enable signal WDEN is performed between the monitoring IC  100  and the microcomputer  300 . In this case, when the watchdog enable signal WDEN generates a power supply short-circuit (i.e., short-circuit to a power supply terminal or a high-potential terminal equivalent thereto), a ground terminal short-circuit (i.e., short-circuit to a ground terminal or a low-potential terminal equivalent thereto), an opening abnormality, and the like, the microcomputer  300  cannot recognize these abnormalities. 
     Therefore, even though the microcomputer  300  intends to operate the monitoring function (in this case, the watchdog timer  173 ) of the monitoring IC  100 , in plural embodiments, the monitoring function may not be operated properly, whereby the failure detection rate of the monitoring IC  100  may decrease. In the following, a novel configuration adopted in the monitoring IC  100  in order to solve such a problem is proposed. 
       FIG. 17  is a diagram showing a state in which the bidirectional communication of a watchdog enable signal WDEN and a watchdog output signal WDOUT is performed between the monitoring IC  100  and the microcomputer  300 . That is, the monitoring IC  100  includes a watchdog timer  173  for monitoring the frequency of a watchdog input signal WDIN, an input terminal (i.e., WDEN pin) to which a watchdog enable signal WDEN for switching the validity and invalidity of the watchdog timer  173  is inputted, and an output terminal (i.e., WDOUT pin) for outputting a watchdog output signal WDOUT (i.e., corresponding to a status signal) for notifying the microcomputer  300  of the validity and invalidity of the watchdog timer  173 . 
     By adopting such a configuration, it is possible for the microcomputer  300  to confirm whether or not the operation control of the watchdog timer  173  can be correctly performed using the watchdog enable signal WDEN. Therefore, it is possible to prevent the monitoring missing (i.e., a state in which the watchdog timer  173  does not operate contrary to the intention) at the time of occurrence of an abnormality of the WDEN pin. 
       FIG. 18  is a timing chart showing an operation of generating a watchdog output signal WDOUT (i.e., status signal). The power supply voltage VDD, the reset input signal RSTIN, the clock signals CLK 1  and CLK 2 , the BIST enable signal BIST_EN, the reset output signal RSTOUT, the monitoring target voltage DINx, the power good signal PGx, the watchdog input signal WDIN, the watchdog enable signal WDEN, the operation state of the watchdog timer  173  and the watchdog output signal WDOUT are depicted sequentially from the upper side. 
     After the power supply is turned on by the power management IC  200 , if the power supply voltage VDD rises to a low voltage abnormality release value UVLO_OFF, an operation of generating each of the clock signals CLK 1  and CLK 2  is started. However, at this time point, the watchdog enable signal WDEN is maintained at a low level. Therefore, the watchdog timer  173  is disabled. In addition, the watchdog output signal WDOUT is maintained at a low level just like the watchdog enable signal WDEN accepted by the monitoring IC  100 . 
     Thereafter, if the reset input signal RSTIN (i.e., the divided voltage of the power supply voltage VDD) rises to a reset release value RST_OFF, the BIST enable signal BIST_EN rises to a high level and the BIST is started. 
     If the diagnosis result of the BIST is “OK”, the reset output signal RSTOUT rises to a high level (see the solid line of RSTOUT) after the reset release waiting time t 1  elapses. On the other hand, if the diagnosis result of the BIST is “NG”, the BIST is repeated (see the two-dot chain line of RSTOUT) while the reset output signal RSTOUT is maintained at a low level. 
     When the monitoring target voltage DINx rises to the lower threshold voltage VthxL after the reset output signal RSTOUT is raised to a high level, the power good signal PGx is raised to a high level (see the solid lines of DINx and PGx) at the timing when a predetermined delay time td has elapsed from the point of time at which DINx=VthxL. 
     On the other hand, if the monitoring target voltage DINx rises to the lower threshold voltage VthxL before the reset output signal RSTOUT is raised to a high level, the power good signal PGx is raised to a high level (see the one-dot chain lines of DINx and PGx) at the timing when a predetermined delay time td has elapsed from the point of time at which the BIST normally comes to an end. 
     In addition, when the reset output signal RSTOUT rises to a high level, the reset of the microcomputer  300  is released. Accordingly, thereafter, the watchdog input signal WDIN (i.e., the monitoring target of the watchdog timer  173 ) is inputted from the microcomputer  300  to the monitoring IC  100 . 
     Furthermore, after the output of the watchdog input signal WDIN is started, the microcomputer  300  raises the watchdog enable signal WDEN to a high level. As a result, the watchdog timer  173  shifts from a disabled state to an enabled state (i.e., a state in which the frequency of the watchdog input signal WDIN is monitored). 
     At this time, if there is no abnormality (such as a power supply short-circuit, a ground terminal short-circuit, an opening abnormality, etc.) at the WDEN pin, the watchdog output signal WDOUT is raised to a high level just like the watchdog enable signal WDEN accepted by the monitoring IC  100 . 
     Therefore, by determining the match/mismatch of the watchdog enable signal WDEN outputted to the monitoring IC  100  and the watchdog output signal WDOUT inputted from the monitoring IC  100 , the microcomputer  300  can confirm whether or not the enable control of the watchdog timer  173  can be correctly performed using the watchdog enable signal WDEN (details of which will be described later). 
     When the reset input signal RSTIN is decreased to the reset detection value RST_ON, the reset output signal RSTOUT falls to a low level. As a result, the microcomputer  300  is reset and, therefore, the output of the watchdog input signal WDIN is stopped. In addition, the watchdog enable signal WDEN falls to a low level and, therefore, the watchdog timer  173  is disabled. At this time, the watchdog output signal WDOUT also falls to a low level. 
     Thereafter, when the power supply voltage VDD is decreased to the low voltage abnormality detection value UVLO_ON, the operation of generating each of the clock signals CLK 1  and CLK 2  is stopped, and the power good signal PGx falls to a low level. 
       FIG. 19  is a correlation diagram showing the watchdog enable signal WDEN, the watchdog output signal WDOUT (i.e., status signal) and the terminal state of the WDEN pin. 
     The logic level of the watchdog enable signal WDEN in this figure is not the actual logic level inputted to the monitoring IC  100  but is the original logic level set inside the microcomputer  300 . On the other hand, the logic level of the watchdog output signal WDOUT indicates the actual logic level inputted to the microcomputer  300 . In this case, for simplicity of explanation, no consideration is given to the abnormality (the power supply short-circuit, the ground terminal short-circuit, the opening abnormality, etc.) of the watchdog output signal WDOUT. 
     If WDOUT=H is inputted to the microcomputer  300  while outputting WDEN=H, it can be confirmed that the watchdog timer  173  is in an enabled state as intended by the microcomputer  300 . 
     Likewise, if WDOUT=L is inputted to the microcomputer  300  while outputting WDEN=L, it can be confirmed that the watchdog timer  173  is in a disabled state as intended by the microcomputer  300 . 
     On the other hand, if WDOUT=L is inputted to the microcomputer  300  despite the fact that the microcomputer  300  is outputting WDEN=H, it can be confirmed that the WDEN pin has an abnormality such as a ground terminal short-circuit or the like and the watchdog timer  173  is in a disabled state contrary to the intention of the microcomputer  300 . 
     In addition, if WDOUT=H is inputted to the microcomputer  300  despite the fact that the microcomputer  300  is outputting WDEN=L, it can be confirmed that the WDEN pin has an abnormality such as a power supply short-circuit or the like and the watchdog timer  173  is in an enabled state contrary to the intention of the microcomputer  300 . 
     &lt;Clock Detection Part&gt; 
       FIG. 20  is a block diagram showing a first configuration example of the clock detection part  172 . The clock detection part  172  of the present configuration example includes high frequency abnormality detection parts  172   a  and  172   b , low frequency abnormality detection parts  172   c  and  172   d , and an oscillator  172   e.    
     The high frequency abnormality detection part  172   a  detects a high frequency abnormality of the clock signal CLK 1  (oscillation frequency f 1 ) using a clock signal CLK 0  (oscillation frequency f 0 ). 
     The high frequency abnormality detection part  172   b  detects a high frequency abnormality of the clock signal CLK 2  (oscillation frequency f 2 ) using the clock signal CLK 0 . 
     The low frequency abnormality detection part  172   c  detects a low frequency abnormality of the clock signal CLK 1  using the clock signal CLK 0 . 
     The low frequency abnormality detection part  172   d  detects a low frequency abnormality of the clock signal CLK 2  using the clock signal CLK 0 . 
     The oscillator  172   e  generates a clock signal CLK 0  having an oscillation frequency f 0  (&gt;f 1 &gt;f 2 ) higher than the oscillation frequencies f 1  and f 2  of the clock signals CLK 1  and CLK 2 . 
       FIG. 21  is a diagram showing an example of a determination operation by the clock detection part  172  of the first configuration example. In the following description, the number of pulses of the clock signal CLK 0  during one period of the clock signal CLK 1  (or CLK 2 ) is denoted by CNT, and the high frequency abnormality detection value and the low frequency abnormality detection value are denoted by CNTf and CNTs (where CNTf&lt;CNTs), respectively. 
     As shown in the upper stage of this figure, when CNTf&lt;CNT&lt;CNTs, it is determined that the oscillation frequency f 1  of the clock signal CLK 1  (or the oscillation frequency f 2  of the clock signal CLK 2 ) is normal. 
     On the other hand, as shown in the middle stage of this figure, when CNT&lt;CNTf, it is determined that the oscillation frequency f 1  of the clock signal CLK 1  (or the oscillation frequency f 2  of the clock signal CLK 2 ) is a high frequency abnormality. 
     As shown in the lower stage of the figure, when CNTs&lt;CNT, it is determined that the oscillation frequency f 1  of the clock signal CLK 1  (or the oscillation frequency f 2  of the clock signal CLK 2 ) is a low frequency abnormality. 
     As described above, in order to monitor the oscillation frequencies f 1  and f 2  of the clock signals CLK 1  and CLK 2 , it is necessary for the clock detection part  172  of the first configuration example to prepare the clock signal CLK 0  having a higher oscillation frequency f 0  (&gt;f 1 &gt;f 2 ). Furthermore, in order to increase the detection accuracy of the clock detection part  172 , it is necessary to ensure that the oscillation frequency f 0  of the clock signal CLK 0  is accurate. Thus, the circuit size increases. In the following, a clock detection part  172  of a second configuration example capable of solving such a problem is proposed. 
       FIG. 22  is a block diagram showing a second configuration example of the clock detection part  172 . As shown in the figure, the clock detection part  172  of the present configuration example includes a frequency divider  172   f  and low frequency abnormality detection parts  172   g  and  172   h.    
     The frequency divider  172   f  divides the frequency of the clock signal CLK 1  having the oscillation frequency f 1  to generate a clock signal CLK 3  having an oscillation frequency f 3  (&lt;f 2 ). 
     The low frequency abnormality detection part  172   g  detects a low frequency abnormality of the clock signal CLK 3  using the clock signal CLK 2  having the oscillation frequency f 2 . 
     The low frequency abnormality detection part  172   h  detects a low frequency abnormality of the clock signal CLK 2  using the clock signal CLK 1 . 
     As described above, in the clock detection part  172  of the present configuration example, the introduction of the frequency divider  172   f  makes it possible to realize frequency monitoring between the clock signals CLK 1  and CLK 2  without having to prepare the clock signal CLK 0  having a high frequency (see  FIG. 20 ). Hereinafter, the determination operation of each of the low frequency abnormality detection parts  172   g  and  172   h  will be individually and concretely described. 
       FIG. 23  is a diagram showing a determination operation of the low frequency abnormality detection part  172   g . In the following description, the number of pulses of the clock signal CLK 2  during one period of the clock signal CLK 3  is denoted by CNT and the low frequency abnormality detection value is denoted by CNTs. 
     As shown in the upper stage of the figure, when CNT&lt;CNTs, it is determined that the clock signals CLK 2  and CLK 3  (and ultimately the clock signal CLK 1 ) are normal. 
     On the other hand, as shown in the middle and lower stages of this figure, when CNTs&lt;CNT, it is determined that the low frequency abnormality of the clock signal CLK 3  (and ultimately the clock signal CLK 1 ) or the high frequency abnormality of the clock signal CLK 2  has occurred. 
     In this manner, the low frequency abnormality detection part  172   g  can detect the low frequency abnormality of the monitored-side clock signal CLK 3  (and ultimately the clock signal CLK 1 ) and, conversely, can also detect the high frequency abnormality of the monitoring-side clock signal CLK 2 . Therefore, it is possible to contribute to the reduction in the circuit size of the clock detection part  172 . 
       FIG. 24  is a diagram showing a determination operation of the low frequency abnormality detection part  172   h . In the following description, the number of pulses of the clock signal CLK 1  during one period of the clock signal CLK 2  is denoted by CNT and the low frequency abnormality detection value is denoted by CNTs. 
     As shown in the upper stage of this figure, when CNT&lt;CNTs, it is determined that the clock signals CLK 1  and CLK 2  are normal. 
     On the other hand, as shown in the middle and lower stages of this figure, when CNTs&lt;CNT, it is determined that the low frequency abnormality of the clock signal CLK 2  or the high frequency abnormality of the clock signal CLK 1  has occurred. 
     In this manner, the low frequency abnormality detection part  172   h  can detect the low frequency abnormality of the monitored-side clock signal CLK 2  and, conversely, can also detect the high frequency abnormality of the monitoring-side clock signal CLK 1 . Therefore, it is possible to contribute to the reduction in the circuit size of the clock detection part  172 . 
     &lt;Digital Processing Part&gt; 
       FIG. 25  is a diagram showing a first configuration example of the digital processing part  170  (only the main part configuration relating to the reset output operation). The digital processing part  170  of the present configuration example includes a reset control part CTRL as well as the clock detection part  172  and the OR gate OR 10  described above. 
     The reset control part CTRL latches an OR signal S 1  of the OR gate OR 10  in synchronization with the clock signal CLK 1  and outputs a latched output signal S 2  (i.e., the reset output detection signal RSTOUT_DET or the gate signal G 0  described above) to the gate of the transistor  180 . The reset control part CTRL has a timer function for counting the reset release waiting time t 1  and the like. In  FIG. 2  described above, the reset control part CTRL is not shown. In plural embodiments, as shown in  FIG. 25 , the reset control part CTRL may be provided between the OR gate OR 10  and the transistor  180 . 
     However, in the digital processing part  170  of the present configuration example, if an abnormality occurs in the oscillator  161  and the clock signal CLK 1  stops, the reset control part CTRL cannot perform a reset output operation and the reset output signal RSTOUT may not correctly fall to a low level. In the following, a digital processing part  170  of a second configuration example capable of solving such a problem is proposed. 
       FIG. 26  is a diagram showing a second configuration example of the digital processing part  170 . The digital processing part  170  of the present configuration example is based on the first configuration example ( FIG. 25 ) and further includes an OR gate OR 20 . In addition, the clock detection part  172  generates not only a clock detection signal CLK_DET but also a clock stop signal CLK_DET 2 . 
     As described above, the clock detection signal CLK_DET goes to a high level when the frequency abnormality of each of the clock signals CLK 1  and CLK 2  is detected. On the other hand, the clock stop signal CLK_DET 2  goes to a high level when an abnormal stop of the clock signal CLK 1  (or a low frequency abnormality equivalent thereto) is detected. 
     The OR gate OR 20  performs a logical sum operation for the latch output signal S 2  inputted from the clock control part CTRL and the clock stop signal CLK_DET 2  inputted from the clock detection part  172 , and outputs an OR signal S 3  (i.e., the reset output detection signal RSTOUT_DET or the gate signal G 0  described above) to the gate of the transistor  180 . 
     When the clock stop signal CLK_DET 2  is at a low level, the latch output signal S 2  is outputted as an OR signal S 3 . On the other hand, when the clock stop signal CLK_DET 2  is at the high level, the OR signal S 3  is fixed at a high level without depending on the logic level of the latch output signal S 2 . 
     That is, when the abnormal stop of the clock signal CLK 1  is detected, the reset output signal RSTOUT is fixed at a high level (i.e., the logic level at the time of abnormality detection) by ignoring the latch output signal S 2  of the reset control part CTRL. In other words, the reset output signal RSTOUT is directly controlled using the clock stop signal CLK_DET 2 . 
     With such a configuration, even when the clock signal CLK 1  abnormally stops and the reset control part CTRL cannot perform the reset output operation, the reset output signal RSTOUT can reliably be set to a low level, which makes it possible to safely stop the electronic device  1 . 
       FIG. 27  is a timing chart showing an example of a reset output operation in the digital processing part  170  of the second configuration example ( FIG. 26 ). The clock signal CLK 1 , the clock detection signal CLK_DET, the clock stop signal CLK_DET 2  and the reset output signal RSTOUT are depicted sequentially from the upper side. 
     Since the clock signal CLK 1  is normal at times t 21  to t 22 , both the clock detection signal CLK_DET and the clock stop signal CLK_DET 2  are at a low level. Therefore, the reset output signal RSTOUT goes to a high level (i.e., logic level at the time of reset release) as long as no other abnormality is detected. 
     At times t 22  to t 23 , the clock detection signal CLK_DET goes to a high level as the low frequency abnormality of the clock signal CLK 1  is detected. However, the clock signal CLK 1  is not completely stopped. Therefore, the reset output operation of the reset control part CTRL is valid. Accordingly, the reset output signal RSTOUT falls to a low level (i.e., logic level at the time of reset) in response to the latch output signal S 2  (i.e., H) outputted from the reset control part CTRL. 
     At times t 23  to t 24 , the clock stop signal CLK_DET 2  goes to a high level as the abnormal stop of the clock signal CLK 1  is detected. In this state, the reset control part CTRL cannot perform the reset control operation. Accordingly, the reset output signal RSTOUT is fixed at a low level in response to the clock stop signal CLK_DET 2  (i.e., H) outputted from the clock detection part  172 . 
     At times t 24  to t 25 , the abnormal stop of the clock signal CLK 1  has been resolved, but the low frequency abnormality has been detected. Therefore, the clock detection signal CLK_DET is at a high level. However, the clock signal CLK 1  is not completely stopped. Therefore, the reset output operation of the reset control part CTRL is valid. Thus, similar to the previous times t 22  to t 23 , the reset output signal RSTOUT is continuously maintained at the low level in response to the latch output signal S 2  (i.e., H) outputted from the reset control part CTRL. 
     At times t 25  to t 26 , the clock signal CLK 1  has returned to a normal state. Therefore, both the clock detection signal CLK_DET and the clock stop signal CLK_DET 2  are at a low level. Accordingly, the reset output signal RSTOUT rises to a high level (i.e., logic level at the time of reset release) as long as no other abnormality is detected. 
     As described above, according to the digital processing part  170  of the second configuration example, even if the oscillation frequency f 1  of the clock signal CLK 1  fluctuates, it is possible to perform an appropriate reset output operation depending on the oscillation state of the clock signal CLK 1 . 
     &lt;Application to Motor Vehicle&gt; 
       FIG. 28  is an external view showing a configuration example of a motor vehicle X. The motor vehicle X of the present configuration example is equipped with various electronic devices (in-vehicle devices) X 11  to X 18  that operate by receiving power supply from a battery. For the sake of convenience in illustration, the mounting positions of the electronic devices X 11  to X 18  in this figure may be different from the actual positions. 
     The electronic device X 11  is an engine control unit that performs engine-related control (injection control, electronic throttle control, idling control, oxygen sensor heater control, auto cruise control, etc.). 
     The electronic device X 12  is a lamp control unit that performs on/off control of a HID (high intensity discharged lamp) or a DRL (daytime running lamp). 
     The electronic device X 13  is a transmission control unit that performs transmission-related control. 
     The electronic device X 14  is a braking unit that performs control related to the motion of the motor vehicle X (ABS [anti-lock brake system] control, EPS [electric power steering] control, electronic suspension control, etc.). 
     The electronic device X 15  is a security control unit that performs drive control of a door lock, a security alarm or the like. 
     The electronic device X 16  is standard equipment or a manufacturer option item such as a wiper, an electric door mirror, a power window, a damper (shock absorber), an electric sunroof, an electric seat or the like. The electronic device X 16  is an electronic device incorporated in the motor vehicle X at the factory shipment stage. 
     The electronic device X 17  is an electronic device that is arbitrarily mounted on the motor vehicle X as a user option item such as an in-vehicle A/V (audio/visual) device, a car navigation system, an electronic toll collection system (ETC) or the like. 
     The electronic device X 18  is an electronic device including a high-pressure-resistant motor such as an in-vehicle blower, an oil pump, a water pump, a battery cooling fan or the like. 
     The monitoring IC  100  described above can be incorporated in any one of the electronic devices X 11  to X 18 . 
     &lt;Other Modifications&gt; 
     In the above-described embodiments, the monitoring IC mounted in the in-vehicle device has been taken as an example. However, the application target thereof is not limited thereto. The monitoring IC can be widely applied to all electronic devices. 
     Apart from the above-described embodiments, various technical features disclosed in this specification can be variously modified without departing from the gist of the technical creation thereof. That is, it is to be noted that the above-described embodiment are exemplary in all respects and are not limitative. The technical scope of the present disclosure is not limited to the above-described embodiments. It is to be understood that the technical scope of the present disclosure encompasses all changes falling within the meaning and range equivalent to the claims. 
     The present disclosure can be used for, e.g., an in-vehicle millimeter wave radar module, an in-vehicle camera or an in-vehicle power supply module. 
     According to the present disclosure in some embodiments, it is possible to provide a monitoring device having a high failure detection rate. 
     While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the disclosures. Indeed, the novel methods and apparatuses described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the disclosures. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the disclosures.