Patent Publication Number: US-11050457-B2

Title: Circuits for continuous-time clockless analog correlators

Description:
CROSS REFERENCE TO RELATED APPLICATION 
     This application claims the benefit of U.S. Provisional Patent Application No. 62/855,853, filed May 31, 2019, which is hereby incorporated by reference herein in its entirety. 
    
    
     STATEMENT REGARDING GOVERNMENT FUNDED RESEARCH 
     This invention was made with government support under grant 1309721 awarded by the National Science Foundation. The government has certain rights in the invention. 
    
    
     BACKGROUND 
     Typical IoT wake-up receivers operating with less than 1 μW demodulate a radio-frequency (RF) signal using a non-linear energy detector (ED). This imposes limits on their sensitivity and, their range for a given peak transmit power. Improving range and the receiver&#39;s sensitivity requires integrating data pulses for a longer duration of time, and thus decreasing the data-rate of the data-pulses and increasing the latency of the wake-up operation. Typical ED wake-up receivers use On-Off Keying (OOK) modulation and respond to a wake-up code ranging between 10 to 32 bits. Typical ED wake-up receivers use a clocked, digital correlator after a baseband comparator to detect a wake-up code, requiring synchronization with the incoming signal or two-times oversampling. In the presence of in-band, amplitude modulated (AM) interference the frequency-domain selectivity is limited, and the receiver can get blocked. 
     Accordingly, new circuits for correlators are desirable. 
     SUMMARY 
     In accordance with some embodiments, circuits for continuous-time, clockless analog correlators are provided. In some embodiments, circuits for a continuous-time analog correlators are provided, the circuits comprising: a first voltage-controlled oscillator (VCO) that receives an input signal and that outputs a first pulse frequency modulated (PFM) output signal; a second VCO that receives a reference signal and that outputs a second PFM output signal; a first phase frequency detector (PFD) that receives the first PFM output signal and the second PFM output signal and that produces a first PFD output signal; a first delay cell that receives the first PFM output signal and that produces a first delayed signal; a second delay cell that receives the second PFM output signal and that produces a second delayed signal; a second PFD that receives the first delayed signal and the second delayed signal and that produces a second PFD output signal; and a capacitor-digital-to-analog converter (capacitor-DAC) that receives the first PFD output signal and the second PFD output signal and that produces a correlator output. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1A  is an example of a block diagram of a receiver in accordance with some embodiments. 
         FIG. 1B  is an example of a 5-bit Barker code that can be used with the block diagram of  FIG. 1A  in accordance with some embodiments. 
         FIG. 1C  is an example of an ideal correlator response to the Barker code of  FIG. 1B  in accordance with some embodiments. 
         FIG. 2A  is an example of a block diagram of a correlator with comparator in accordance with some embodiments. 
         FIG. 2B  is an example of a simplified block diagram of a correlator with comparator in accordance with some embodiments. 
         FIG. 3A  is an example of 1-bit correlator in accordance with some embodiments. 
         FIG. 3B  is an example of a timing diagram of the 1-bit correlator of  FIG. 3A  in accordance with some embodiments. 
         FIG. 4  is an example of delay-PFD-DAC element including sub-delay elements in accordance with some embodiments. 
         FIG. 5A  is an example of a sub-delay element including sub-sub-delay elements in accordance with some embodiments. 
         FIG. 5B  is an example of a schematic for a sub-sub-delay element in accordance with some embodiments. 
         FIG. 5C  is an example of a timing diagram for a sub-sub-delay element in accordance with some embodiments. 
         FIG. 6  is an example of a schematic of a receiver in accordance with some embodiments. 
         FIG. 7A  is an example of a schematic diagram for swapping inputs to a PFD in accordance with some embodiments. 
         FIG. 7B  is an example of a schematic diagram for swapping inputs to a capacitor-DAC in accordance with some embodiments. 
         FIG. 8A  is an example of a process for calibrating a delay cell in accordance with some embodiments. 
         FIG. 8B  is an example of a timing diagram for calibrating a delay cell in accordance with some embodiments. 
     
    
    
     DETAILED DESCRIPTION 
     In accordance with some embodiments, continuous-time (CT), clockless analog correlators are provided. 
       FIG. 1A  shows an example  100  of a block diagram of a receiver including a five-bit CT, clockless analog correlator in accordance with some embodiments. As illustrated, this receiver includes an antenna  101 , a matching network  102 , a 40-stage self-mixer  104 , an amplifier  106 , an integrator  108 , a clock-less, CT correlator  110 , a comparator  126 , and a threshold reference  128 . 
     During operation, an RF signal received by antenna  101  can be provided to matching network  102 , which in turn provides it to self-mixer  104 . The self-mixer down converts the signal and provides it to amplifier  106 . The amplifier amplifies the signal and provides it to intergrator  108 . The integrator integrates the signal over time t-τ 1  to t. The integrated signal then propagates through delay cells  111 - 114 . The outputs of the delay cells are the multiplied by predetermined code bits h[ 0 ], h[ 1 ], h[ 2 ], and h[ 3 ] by multipliers  116 - 119 , respectively. The output of the integrator is also multiplied by predetermined code bit h[ 4 ] by multiplier  120 . The outputs of multipliers  116 - 120  are added-up by adders  122 - 125  and then provided to comparator  126 . The comparator then compares the output of the adders to a threshold voltage provided by threshold reference  128  to provide a wake-up signal when the output of the adders exceeds the threshold voltage. 
     In some embodiments, the analog correlator can suppress unwanted codes and thereby provide code-domain selectivity and enable simultaneous wake-up with code-domain multiple access. In some embodiments, a ‘1’, ‘0’ encoded On-Off Keying (OOK) wake-up code can be used (e.g., if all the wake-up receivers use the same code). In some embodiments, for simultaneous wake-up using different wake-up codes, ‘1’ ‘−1’ encoded orthogonal wake-up codes, which can provide better selectivity with respect to unwanted codes, can be used. 
     In some embodiments, the correlator can be configured to detect a five-bit (or any other suitable number) code input, such as the Barker code shown in  FIG. 1B . When this input is received, an ideal correlator can provide an output as shown in  FIG. 1C  in accordance with some embodiments. 
     Additionally, return-to-zero (RZ) encoded symbols can be used in some embodiments so that all desired codes can pass through a DC feedback loop described below. 
     In accordance with some embodiments, the output, v corr (t), of an ideal n-bit clockless correlator with rectangular bits with a period of τ 1  can be written as:
 
 v   corr ( t )=∫ τ=−nτ     1     v   in ( t −τ) h [τ] dτ   (1)
 
where v in (t) is the input signal and h[τ] is a piecewise linear function representing the correlation coefficients. h[τ] is defined for n time periods corresponding to the correlation sequence. Here, the processing gain is max(|v out,corr (t)|)/max(v in,corr (t)). Assuming the signal uses ‘1’, ‘−1’ On-Off Keying (OOK) encoding, during integration of the signal for N-bits, the signal adds in magnitude while the noise adds in power, thus, the analog correlator provides a processing gain of 10 log(N) for the SNR. Instead, if the signal uses ‘1’, ‘0’ encoding, assuming the number of ‘1’s in the code is L, the corresponding processing gain is 10 log(L).
 
     The output of an ideal correlator for an N-bit sequence given in (1) can be rewritten as: 
     
       
         
           
             
               
                 
                   
                     
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     For an analog signal encoded in time domain, e.g., with pulse-position modulation (PPM) or pulse width modulation (PWM), digital-style delays can be utilized to realize the CT delays in a clockless analog correlator. 
     The ideal analog correlator response (3) can further be written as: 
                       v     out   ,   corr   ,   1       ⁡     (   t   )       =         ∫     -   ∞     0     ⁢       ∑     k   =   1               ⁢   N       ⁢           ⁢         v     in   ,   corr       ⁡     (     t   -     k   ⁢           ⁢   τ       )       ⁢     h   ⁡     [     k   ⁢           ⁢   τ     ]       ⁢   d   ⁢           ⁢   τ         -       ∫     -   ∞       -     τ   1         ⁢       ∑     k   =   1     N     ⁢           ⁢         v     in   ,   corr       ⁡     (     t   -     k   ⁢           ⁢   τ       )       ⁢     h   ⁡     [     k   ⁢           ⁢   τ     ]       ⁢   d   ⁢           ⁢   τ                   (   4   )               
with the equivalent block diagram in  FIG. 2A . Since, the signals in the ∫ −∞   t−τ     1    branch (top branch  201  shown in  FIG. 2A ) can be tapped from ∫ −∞   t  branch (bottom branch  202  shown in  FIG. 2A ) with a delay τ 1  as shown by the dashed lines in  FIG. 2A , the much more compact block diagram shown in  FIG. 2B  can be used in some embodiments. This more compact block diagram can operate as an analog correlator providing the FIR response for the desired code in some embodiments.
 
     In some embodiments: the integration  203  can be implemented using a voltage controlled oscillator (VCO) outputting pulse-frequency modulated (PFM) signals; these signals can easily be delayed using latch-based delays for delays  204 - 208 ; and the delayed signals can then be correlated with the code and summed using a capacitor DAC. 
     For a 1-bit matched filter, (3) can be rewritten as:
 
 v   corr,1 ( t )=∫ −∞   0   v   in ( t −τ) h [τ] dτ−∫   −∞   0   v   in ( t −τ) h [τ] dτ   (5)
 
where h[τ] is 1 or −1 depending on the data-bit being received.  FIGS. 3A and 3B  show an example of the implementation of a 1-bit matched filter in accordance with some embodiments. As illustrated, the front end of the correlator of  FIG. 3A  includes two VCOs with a center frequency f 0 : (1) a signal VCO  302  which converts the input signal, v in,corr (t), into a pulse frequency modulated (PFM) output; and (2) a reference VCO  304  which converts a DC reference V OSC_REF  with frequency f 0  into a PFM output. The pulse output positions in v sig &lt;0&gt; relative to the pulse positions in v 0,ref &lt;0&gt; provide
 
∫ −∞   t   K   vco [( V   in,corr (τ)− V   OSC,REF )] dτ   (6)
 
where K vco  is the voltage-to-frequency conversion gain of the VCOs. The relative pulse positions are compared with a phase-frequency detector (PFD)  306  and fed to an adder implemented using capacitor-DAC  308  to convert the signal back to voltage domain. This evaluates the first term in (5).
 
     The output pulses of the VCOs are also delayed using latch-based delay cells  310  and  312  with delay τ 1  and the relative position is again evaluated using a PFD  314 , thus evaluating the second term in (5). 
     The output is subtracted using capacitor-DAC  308 . This provides a CT windowed integrator response for a window of time τ 1  provided by the delay cell. 
     As shown in  FIG. 4 , in some embodiments, N delay-PFD-DAC elements  402 ,  404 , and  406  can be cascaded to keep track of v in  for the past N τ     1    duration. As also shown in  FIG. 4 , in some embodiments, each delay-PFD-DAC element  402 ,  404 , and  406  can include a delay element τ 1    408  (that includes eight (or any other suitable number) τ d  delay cells  411 - 418  cascaded in series and two multiplexers  420  and  422  (for each side of a differential signal as shown in  FIG. 4 , in some embodiments)), PFDs  424  and  426  to evaluate relative position of pulses, and parts of capacitor-DAC  428  to convert the signal back to the voltage domain. A weighted sum can performed using the capacitor-DACs with weights as the {−1,+1} correlator coefficients h[τ], implemented by swapping the input signals to the PFDs. This can be performed in any suitable manner, such as by using multiplexers as shown in  FIG. 7A , in some embodiments. Alternatively, in some embodiments, each part of the capacitor-DAC can be weighted by a corresponding correlator coefficient h[τ] by swapping the input signals to the part of the capacitor-DAC. This can be performed in any suitable manner, such as by using multiplexers as shown in  FIG. 7B , in some embodiments. Eleven such delay-PFD-DAC elements can be connected in series and the outputs of the DACs can be connected together to evaluate the correlator output v corr (t) in some embodiments. 
     Multiplexers  420  and  422  can be used to select different delays for delay element τ 1    408  in some embodiments. These multiplexers can be controlled in any suitable manner in some embodiments. For example, these multiplexers can be controlled by a hardware processor (not shown) that oversees the operation of a receiver including an analog correlator incorporating elements  402 ,  404 , and/or  406 , in some embodiments. 
     Calibration multiplexers  432  and  434  can be provided in some embodiments to facilitate injecting calibration pulses into elements  402 ,  404 , and/or  406 . An example of the calibration operation is described further below in connection with  FIGS. 8A and 8B  in some embodiments. 
     In some embodiments, as shown in  FIG. 5A , each delay element τ d    500  can include three (or any other suitable number) τ g  delay cells  501 ,  502 , and  503 , each as shown in  FIG. 5B . These τ g  delay cells can be cascaded by connecting the “Out” signals of the first and second τ g  delay cells  501  and  502  to the “In” of the second and third τ g  delay cells  502  and  503 , respectively. 
     As shown in  FIGS. 5B and 5C , an input falling edge at “In” sets SR latch  505  to discharge C 1 , until it reaches a threshold to turn T 3  on. Once T 3  is triggered, it delivers a falling edge pulse at the output “Out” and resets the latch. The delay τ g  is controlled by current source I 1 , current mirror T 1  and T 2 , MIM-cap C 1 , and the T 3  threshold. Variations in transistors can be controlled using current mirror trimming, in some embodiments. For example, in some embodiments, six bits can be used to trim the current mirror T 1  and T 2 . This can be done in any suitable manner, such as by including a set of six parallel transistors (one for each bit) in series with different fingers of T 2  and properly sized to allow different amounts of current to flow through T 2  based on the values of the bits. 
     In some embodiments, current source I 1  can be mirrored from an 8 pA (or any other suitable size) core current mirror  608  having 6-bit (or any other suitable number) trim to provide a 30% (or any other suitable number) tuning range to compensate for current mirror and delay cell mismatches. In some embodiments, the core current mirror can also have a 50% (or any other suitable number) tuning range to set the average delay and compensate for process variations. The delay cell calibration can be used to set the delays in some embodiments. 
     In some embodiments, the minimum pulse width (τ pulse ) required for the input pulse is decided by the setup time of SR latch  502 . The maximum pulse width should be less than the delay of the unit cell, in some embodiments. Therefore, in some embodiments, the input-pulse instantaneous frequency must be less than (1/(τ g +τ pulse )). For τ 1 =10 msec, τ g =10,000 μsec/24=416 μsec. This leads to a maximum input-pulse frequency of 2.3 kHz in some embodiments. Due to the variations in the current mirrors controlling the delay cells and the added jitter, the operating frequency of the reference VCO can be set to 1.1 kHz in some embodiments. 
       FIG. 6  shows an example  600  of a wake-up receiver using an analog correlator for code-domain matched filtering in accordance with some embodiments. In some embodiments, this receiver can be targeted to operate in 434 MHz ISM band, use an 11-bit wake-up code at a data rate of 100 bps. 
     As shown, the RF front end includes a matching network  604  connected to an antenna  602  at its input and a self-mixer  606  at its output. The matching network matches the impedance of self-mixer  606  to antenna  602 . Any suitable matching network can be used in some embodiments. For example, in some embodiments, the matching network can match the impedance of self-mixer  606  to antenna  602  at 450.8 MHz. More particularly, for example, in some embodiments, matching network  604  can include a 132-10SM inductor L ind =111 nH available from COILCRAFT of Cary, Ill. and a capacitor C 1 =14 pF. 
     Self-mixer  606  can receive the signal output by matching network  604 . Any suitable self-mixer can be used in some embodiments. For example, a 40-stage gate-biased energy detector (ED) with an input resistance of 200 kΩ can be used as self-mixer  606 . 
     The output of self-mixer  606  is amplified using amplifier  612 . Any suitable amplifier can be used in some embodiments. For example, in some embodiments, a one-stage current-reuse amplifier can be used as amplifier  612 . As a more particular example, in some embodiments, the amplifier can be a current-reuse baseband inverting amplifier with a gain (A v,amp ) of 26 dB and a 1 dB baseband noise figure relative to the noise contributed by the self-mixer. A PMOS transistor in the amplifier (as shown in  FIG. 6 ) can be current biased using a current mirror with AC coupling while an NMOS transistor in the amplifier (as shown in  FIG. 6 ) can be biased through a DC feedback loop including PFDs  638  and  644  and charge pumps  640  and  646 . 
     The output of amplifier  612  is provided to CT, clockless analog correlator  613 . In some embodiments, correlator  613  can include VCOs  614  and  616  that integrate and encode the input signal into a pulse-position modulated (PPM) signal, delay lines  622 ,  624 , and  626 , PFD  630 , and parts of capacitor-DAC  632  that correlate received pulses with the desired code, and a 4-phase filter  634  that suppresses the VCO frequency and its harmonics. 
     In some embodiments, VCOs  614  and  616  can be implemented using 4-phase current-starved ring oscillators operating at 1.1 kHz with conversion gain K vco =25 kHz/V. As described below, the average frequency of signal VCO  614  can be locked to f 0  using a PLL. This sets the DC potential at v in,corr  equal to V OSC,REF . 
     At the input and the output of each delay element τ 1    622 ,  624 , and  626 , a PFD  630  is used to evaluate the relative position of pulses. The outputs of the twenty-two PFDs  630  are sent to the corresponding parts of capacitor-DAC  632  to implement eleven matched filters for an 11-bit code. A weighted sum can performed using the capacitor-DACs with weights as the {−1,+1} correlator coefficients h[τ], implemented by swapping the input signals to the PFDs. This can be performed in any suitable manner, such as by using multiplexers as shown in  FIG. 7A , in some embodiments. Alternatively, in some embodiments, each part of the capacitor-DAC can be weighted by a corresponding correlator coefficient h[τ] by swapping the input signals to the part of the capacitor-DAC. This can be performed in any suitable manner, such as by using multiplexers as shown in  FIG. 7B , in some embodiments. The weighted sum provides the output of correlator  613 . 
     In some embodiments, the output of correlator  613  can have strong signal components at f 0  and its harmonics that need to be filtered out. These strong signal components and harmonics can be filtered out using a 4-phase filter  634  in some embodiments. 4-phase filter  634  uses the 4-phases of the reference VCO to sample the correlator output and averages the output over one VCO period to suppress the outputs at f VCO  and its harmonics. Four phases φ 1-4  of the f 0  with 20% duty-cycle can be used to sample the signal at the output of the correlator. A series resistor is used to provide a low-pass frequency response, a nonoverlapping phase φ 5  with 5% duty-cycle is used to average the four samples. 
     In some embodiments, on average, the frequency of signal VCO  614  needs to be locked to the frequency of reference VCO  616  for glitch-free operation of the correlator. In some embodiments, this can be ensured using a phase locked loop (PLL). In order to do so, in some embodiments, the outputs of the VCOs can be compared with PFD  638  and fed to a charge pump (CP)  640  with current I CP  that drives a 10 pF capacitor C LOOP    642 . The feedback loop has two poles at DC, and needs to be compensated to achieve stability. The VCO outputs delayed by τ d  can also drive a second PFD  644  with the inputs swapped for sign inversion. The Up/Down pulses from the second PFD drive a second charge pump  646  connected to C LOOP    642  with a current cI CP , where c is a scaling constant 0&lt;=c&lt;=1. This introduces a zero, and stabilizes the loop. In some embodiments, this PLL additionally provides a high-pass response in the signal path and rejects the low-frequency flicker noise added by the amplifier. 
     The output of the correlator is fed to a comparator  636  that decides if the receiver should wake up. Any suitable comparator can be used in some embodiments. For example, in some embodiments, a dynamic latched comparator clocked at frequency f 0  from the reference VCO can be used to compare the correlator output to detect the wake-up signal. 
     In some embodiments, a data rate of 100 bps can be used. Hence, a bit period τ 1  can be 10 ms, and a required false-alarm rate &lt;=1/h and an MDR &lt;=10 −3 . This is equivalent to a receiver with a sampling rate of f s =1/τ 1 . Since there are (3600 s·f s ) samples in an hour, the probability of a comparator being triggered due to noise P(1|0) has to be &lt;=1/(3600·f s ). If the RMS noise measured at v out,corr  is σ=3.4 mVrms, the required comparator threshold is then 4.6σ (16 mV) where σ is the root-mean square (RMS) noise at the correlator output for a false alarm rate less than one per hour. The signal needs to be 3.1σ above the threshold (i.e., total 7.7σ) for successful detection with an MDR &lt;=10 −3 . The required SNR at the correlator output is thus 17.7 dB in some embodiments. 
     In some embodiments, a threshold of 20 mV can be used to provide tolerance to glitches. In some embodiments, the comparator can be PMOS triggered with mismatched transistor sizes for a negative threshold of −20 mV. 
     In accordance with some embodiments, a ‘1’ and ‘−1’ encoded On-Off Keying (OOK) symbol can be realized by transmitting peak or no power respectively, while transmitting symbol ‘0’ with half the power when no symbol is being transmitted. This can ensure a linear voltage at the self-mixer output, in some embodiments. During the vast majority of the time that the receiver is expected to receive no data, a corresponding transmitter can be configured to not transmit and the receiver will observe a ‘0’. In some embodiments, when the transmitter transmits a wake-up code, the DC feedback loop will provide high pass filtering at baseband, the receiver will adjust its ‘0’ level to transmitter half-power. A preamble with half-power can be used in some embodiments to provide appropriate settling time for the DC feedback loop. For example, in some embodiments, for a DC-feedback-loop settling time of 25 ms, the preamble may be required to be 2.5-bits. This leads to an additional 25 ms latency compared to a ‘1’ ‘0’ encoding, in some embodiments. 
     As mentioned above, in some embodiments, all delay cells can be controlled by a core current source which has a 6-bit trim setting to account for process variations. Calibrating the mismatch between the delay cells can be used in some embodiments to avoid cycle slipping and enable operation at maximum dynamic range. In some embodiments, each delay element τ 1  can include a 6-bit trimming register to account for these mismatches. An example calibration process to set the delays is shown in  FIGS. 8A and 8B . For example, in some embodiments, to calibrate a τ 1  delay cell in the reference delay line, the VCO output can be bypassed using multiplexer  620  and falling edge pulses (Cal_Pulses) with frequency 1/(τ 1 ) can be fed at the input of the delay cell. The corresponding delay element in the signal delay line can be bypassed using multiplexer  628  and Cal_Pulses can be fed to the PFD. Thus, the PFD at the output of the delay cells can compare τ 1  to the period of the Cal_Pulses. Up/Down pulses provide feedback to increase/decrease the delay control code to set the delay. In some embodiments, calibration is required for all eleven τ 1  delay cells. In some embodiments, to reduce the need for calibration, the device sizes can be increased to reduce mismatch, however, this may lead to an increase in power consumption. 
     In some embodiments, to tolerate higher drift in delays, either a temperature compensated oscillator on-chip or a crystal reference can be used. During large temperature changes, these can be turned on as a reference for re-calibration of the delay cells. 
     In some embodiments, the outputs of the PFDs may saturate with increasing input signal strength due to the limited maximum pulse position difference which is limited to the VCO period 1/f 0 . At higher input signal strength, the frequency variations on the VCOs can be large which leads to cycle slipping and the bits to show a +/−correlation, which leads to a non-monotonic processing gain degradation. In some embodiments, adaptive gain control techniques can be used to increase the dynamic range further. 
     In some embodiments, UP/Down counters at the output of the PFDs that are controlled by the states in the PFD can be used to enable multi-level digital output and to further enhance the dynamic range. 
     In some embodiments and instances, a receiver can issue a false wake-up in the presence of a short burst of interference. Assuming that the self-mixer response to a bursty AM interferer is an impulse, the output of the correlator can be its impulse response which is exactly the code it is configured for. In some embodiments, finite state machines can be used to detect such code and prevent a false wake-up. 
     In some embodiments, preamble sampling or bit-level duty cycling can be used with RF front-end amplifiers to achieve better sensitivity at the cost of relatively higher power consumption for similar latency. 
     As described above, in some embodiments, continuous-time (CT), clockless analog correlators can be located in a receiver before the receiver&#39;s baseband comparator and can perform matched filtering (MF). In some embodiments, continuous-time (CT), clockless analog correlators eliminate the synchronization challenges experienced by digital correlators and can provide an improved output signal-to-noise ratio (SNR), and thus sensitivity, with the same data rate and latency compared to digital correlators. In some embodiments, continuous-time (CT), clockless analog correlators can provide code-domain filtering for enhanced selectivity and suppress AM interference. The wake-up codes can be treated as direct sequence code-division multiple-access (DS-CDMA) signals in some embodiments. Using direct sequence code-division multiple access (DS-CDMA) can allow for simultaneous wake-up of different receivers each programmed to wake-up with its own unique code in some embodiments. The code-domain filtering offered by analog correlators enables the wake-up receivers to detect their code while other unwanted codes get suppressed even when used in the same time slot in some embodiments. 
     The provision of the examples described herein (as well as clauses phrased as “such as,” “e.g.,” “including,” and the like) should not be interpreted as limiting the claimed subject matter to the specific examples; rather, the examples are intended to illustrate only some of many possible aspects. 
     Although the invention has been described and illustrated in the foregoing illustrative embodiments, it is understood that the present disclosure has been made only by way of example, and the numerous changes in the details of implementation of the invention can be made without departing from the spirit and scope of the invention, which is limited only by the claims that follow. Features of the disclosed embodiments can be combined and rearranged in various ways.