Patent Publication Number: US-10763260-B2

Title: Semiconductor device and method of manufacturing a semiconductor device

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This application is a continuation application and claims the benefit of U.S. non-provisional application Ser. No. 15/854,827, which was filed on Dec. 27, 2017 and is incorporated herein by reference. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates generally to a semiconductor device, more specifically, to a semiconductor device with low-K materials to reduce parasitic capacitance. 
     2. Description of the Prior Art 
     Semiconductor devices are widely used in an electronic industry because of their small size, multi-function and/or low manufacture costs. Semiconductor devices are categorized as semiconductor devices storing logic data, semiconductor logic devices processing operations of logical data, hybrid semiconductor devices having both the function of semiconductor memory devices and the function of semiconductor logic devices and/or other semiconductor devices. 
     Semiconductor devices may generally include vertically stacked patterns and contact plugs electrically connecting the stacked patterns to each other. As semiconductor devices have been highly integrated, a space between the patterns and/or a space between the pattern and the contact plug have been reduced. Thus, a parasitic capacitance between the patterns and/or between the pattern and the contact plug may be increased. The parasitic capacitance may cause performance deterioration (e.g., reduction of an operating speed) of semiconductor devices. For this reason, how to reduce parasitic capacitance in semiconductor devices is an urgent task to research and develop in the semiconductor industry. 
     SUMMARY OF THE INVENTION 
     The purpose of the present invention is to provide a method of manufacturing a semiconductor device. The method features the low-K dielectric layer disposed along two sides of bit lines and surrounding storage nodes to effectively reduce the parasite capacitance in devices, and the process steps of the present invention may be integrated with the process steps of logic devices in peripheral regions without additional process cost or time. 
     To achieve the above-mentioned purpose, a semiconductor device is provided in one embodiment of the present invention. The semiconductor device includes a memory region, a plurality of bit lines in the memory region, a first low-k dielectric layer on each sidewall of each bit line, a plurality of storage node regions between the bit lines, and a second low-k dielectric layer surrounding each storage node region. 
     To achieve the above-mentioned purpose, a method of manufacturing a semiconductor device is provided in one embodiment of the present invention. The steps of the method include providing a substrate with a memory region and a logic region thereon, forming bit lines and logic gates respectively in the memory region and the logic region, wherein storage node regions are defined between bit lines, forming a first low-K dielectric layer on sidewalls of bit lines, forming doped-silicon layer in each storage node region between bit lines, wherein the top surface of doped-silicon layer is lower than the top surface of bit lines, forming a second low-K dielectric layer on sidewalls of the storage node regions, and filling up the storage node regions in the memory region with metal plugs. 
     These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The accompanying drawings are included to provide a further understanding of the embodiments, and are incorporated in and constitute apart of this specification. The drawings illustrate some of the embodiments and, together with the description, serve to explain their principles. In the drawings: 
         FIGS. 1-11  are cross-sectional views schematically showing the process flow of manufacturing a semiconductor device in accordance with one embodiment of the present invention; and 
         FIG. 12  is a top view of a semiconductor device in accordance with one embodiment of the present invention. 
     
    
    
     It should be noted that all the figures are diagrammatic. Relative dimensions and proportions of parts of the drawings have been shown exaggerated or reduced in size, for the sake of clarity and convenience in the drawings. The same reference signs are generally used to refer to corresponding or similar features in modified and different embodiments. 
     DETAILED DESCRIPTION 
     In the following detailed description of the present invention, reference is made to the accompanying drawings which form a part hereof and is shown by way of illustration and specific embodiments in which the invention may be practiced. These embodiments are described in sufficient details to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present invention. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims. 
     It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer and/or section from another. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the disclosure. 
     The terminology used herein to describe embodiments of the inventive concepts is not intended to limit the scope of the inventive concepts. The use of the singular form in the present document should not preclude the presence of more than one referent. In other words, elements of the inventive concepts referred to in the singular may number one or more, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and/or “including,” when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. 
     The process flow of manufacturing a semiconductor device of the present invention will be described hereinafter with reference to  FIG. 1  to  FIG. 11  in sequence. Please refer to  FIG. 1 . According the method of manufacturing a semiconductor device in the present invention, a semiconductor substrate  100  is first prepared to serve as the base for components to be disposed thereon. The semiconductor substrate may include silicon substrate, silicon-germanium (SiGe) substrate, or silicon-on-insulator (SOI) substrate, etc, wherein a memory region  10  is defined thereon for disposing memory arrays consisting of multiple memory cells, and a logic region  20  is defined thereon surrounding the memory region  10  for disposing other logic or functional circuits, such as sense amplifier, address buffer, and address decoder, etc. Some process steps described in following embodiments are only performed in one of the memory region  10  and the logic region  20 , while others may be performed in both regions. 
     The semiconductor substrate  100  includes active regions  102  and field oxide regions  104  (or shallow trench isolations, STI). Field oxide region  104  may be formed by filling up the preformed field oxide trenches with field insulating material, such as silicon oxide. The active regions  102  are defined by the surrounding field oxide region  104 . The memory region  10  and logic region  20  of the semiconductor substrate  100  are pre-formed respectively with bit lines  110  and logic gates  210  thereon, wherein the bit line  110  may include from bottom to top a bit line contact plug  112  (ex. a doped poly-silicon layer or an amorphous silicon layer extending into the semiconductor substrate  100  and connecting the active region thereunder), a bit line electrode  114  (ex. Ti/TiN/W multilayer metal structure), and a hard mask  116  (ex. a silicon nitride layer). A metal silicide layer  118  may be further formed between bit line contact plug  112  and bit line electrode  114 , for example, by the reaction of lowest portions of bit line electrode with the silicon surface, to connecting the bit line electrode  114  and the bit line contact plug  112 . In the manufacturing process, trenches  106  may be formed between two sides of bit line gate  110  and substrate since the width of opening of bit line contact formed in previous etch process is larger than the width of bit line  110  itself. 
     Refer again to  FIG. 1 . The logic gate  210  on the logic region  20  of semiconductor substrate  100  may include agate dielectric layer  212  (ex. a silicon oxide layer), a gate electrode layer  214  (ex. a poly-silicon layer), and a capping layer  216  (ex. a silicon nitride layer). In the embodiment of present invention, the logic gate  210  on the logic region  20  and the bit line gate  110  on the memory region  10  are formed in different processes. However, in other embodiment, the logic gate  210  on the logic region  20  and the bit line gate  110  on the memory region  10  may be formed in the same process. 
     Please refer to  FIG. 2 . After bit lines  110  and logic gates  210  are formed, a first spacer layer  120  and a second spacer layer  122  are conformally formed on the memory region  10  and logic region  20  and completely cover thereon, wherein the first spacer layer  120  may be a silicon nitride layer or a silicon carbon nitride layer plus an oxide layer to function as a barrier layer for bit lines. The second spacer layer  120  may be another silicon nitride layer with distinctive etch selectivity compared to the oxide layer of first spacer layer  120 . The first spacer layer  120  and the second spacer layer  122  would fill up the trenches  106  at both sides of the bit line  110 . Alternatively, in some embodiment, the trench  106  is not filled up on purpose to form gap inside. 
     Please refer to  FIG. 3 . After the first spacer layer  120  and second spacer layer  122  are formed, a third spacer material are formed in the logic region  20  and then are performed with an anisotropic etch process to form spacers  218  at both sides of the logic gates  210 , wherein the spacer  218  is made up of the first spacer layer  120 , the second spacer layer  122  and the third spacer layer  124 . Please note that there is no third spacer layer  124  remaining in the memory region  10  in this stage. The third spacer layer  124  may be selectively removed from memory region  10  by using photoresist and buffered oxide etch (BOX) process. Furthermore, the portion of second spacer layer  122  not covered by the third spacer layer  124  on the memory region  10  is then removed by using other etchants with appropriate etch selectivity. Thus, only the portion of second spacer layer  122  inside the trenches may remain and the first spacer layer  120  is exposed. 
     Please refer to  FIG. 4 . After the second spacer  122  is removed, a first low-K dielectric layer  126  is formed conformally on the memory region  10  and completely covers the bit lines  110 . The example of low-K material may include, but not limited to, hydrogen silsesquioxane (HSQ), methyl-silsesquioxane (MSQ), polyphenylene oligomer, methyl doped silica, organo-silicate glass, or porous silicide, etc. Please note that the first low-K dielectric layer  126  is not formed on the logic region  20  in this embodiment. On the other hand, an ion implantation process is performed on the logic region  20  to form source/drain  220  between the spacers  218  and outer field oxide region  104  formed in previous processes. 
     Please refer to  FIG. 5 . After the first low-K dielectric layer  126  is formed, an anisotropic etch process is performed to remove the first low-K dielectric layer  126  and the first spacer layer  120  on the surface of memory region  10 , so that only the first low-K dielectric layer  126  on sidewalls of the bit lines  110  remains and the active regions  102  of memory region  10  are exposed. In this embodiment, storage node regions  127  are defined between bit lines  110  to be preserved for disposing the storage node structures of the memory cells. In the embodiment of the present invention, The approach of forming the first low-K dielectric layer  126   a  on sidewalls of the bit lines may help to reduce the parasite capacitance induced by close spacing between bit lines and storage node therearound, thereby improving the device&#39;s performance. 
     Please refer to  FIG. 6 . A contact etch stop layer (CESL)  128 , such as a silicon nitride layer, is then formed conformally on the memory region  10  and logic region  20 . The material of contact etch stop layer  128  has good etch selectivity compared to the material of interlayer dielectric (ILD) to be formed in later process. 
     Please refer to  FIG. 7 . After the contact etch stop layer  128  is formed, an interlayer dielectric  130  is blanket-deposited on the memory region  10  and the logic region  20 , and a chemical mechanical polishing (CMP) process is performed to the process surface until the top surfaces of bit lines  110  and logic gates  210  are flush. The interlayer dielectric  130  would fill up the storage node regions  127  between bit line gates  110 . 
     Please refer to  FIG. 8 . After the interlayer dielectric  130  is formed, the interlayer dielectric  130  in the memory region  10  is removed by using the etchants dedicated for silicon oxide material. An anisotropic etch process is further performed to remove the contact etch stop layer  128  on the surface of memory region  10 , so that only the contact etch stop layer  128   a  on sidewalls of bit lines  110  remains and the active regions  102  in the memory region  10  are exposed. In this way, the storage node regions  127  would be preserved again for the components of storage nodes. 
     Please refer to  FIG. 9 . The doped silicon layer  132 , such as a phosphorus-doped silicon layer, is then formed in the storage node regions  127  between bit lines  110  in the memory region  10 , to function as a lower storage node structure. The top surface of the doped silicon layer  132  would be lower than the top surface of surrounding bit line gates  110 , so that the storage node region  127  is not filled up by the doped silicon layer  132 . The doped silicon layer  132  may be formed by following processes: first, covering a doped silicon material on the memory region  10 . The doped silicon material would fill up the storage node regions  127  between bit lines  110 . An etch back process is then performed to remove the doped silicon material outside the storage node regions  127  until the top surface of doped silicon material reaches a predetermined level lower than the top surface of surrounding bit lines  110 . The lower storage node structure is therefore completed. The remaining space on the storage node regions  127  may be preserved for the formation of upper storage node structure. Please note that in this embodiment, there is no doped silicon layer formed in the logic region  20 . 
     Please refer to  FIG. 10 . After the doped silicon layer  132  is formed in the storage node regions  127 , a second low-K dielectric layer  134  is then conformally formed on the memory region  10 . The second low-K dielectric layer  134  covers the surface of bit line gates  110  and remaining storage node regions  127 . The material of second low-K dielectric layer  134  may be the same as the one of first low-K dielectric layer  126 , which may include, but not limited to, hydrogen silsesquioxane (HSQ), methyl-silsesquioxane (MSQ), polyphenylene oligomer, methyl doped silica, organo-silicate glass, or porous silicide, etc. Please note that in this embodiment, no second low-K dielectric layer  134  is formed on the logic region  20 . 
     Please refer to  FIG. 11 . After the second low-K dielectric layer  134  is formed, an etch back process is then performed to remove the second low-K dielectric layer  134  on the top surface of bit lines  110  and on the bottom surface of storage node region  127 . Only the portion of second low-K dielectric layer  134   a  on sidewalls between bit lines remains in the region, so that the doped silicon layers  132  in the storage node regions  127  are exposed. In addition, a photolithographic process and an etch process are further performed on the logic region  20  to form contact holes  222  extending downward to the source/drain  220  below in the interlayer dielectric  130 . 
     Refer again to  FIG. 11 . The remaining storage node regions  127  in the memory region  20  and the contact holes  222  in the logic region  10  are filled up with metal to form contact plugs  136  and  224  respectively. The contact plugs  136  and  224  may include multilayer structure such as Ti/TiN/W and connect electrically and respectively with the doped silicon layer  132  and the source/drain  220  thereunder. The contact plug  136  on the memory region  20  is connected with the doped silicon layer  132  to function as an upper storage node structure. In addition, a metal silicide process may be performed before the filling process of contact plugs, to form metal silicide layers on exposed surfaces of the doped silicon layer  132  and source/drain  220  and thereby establishing good electrical connection with the contact plugs to be filled in later process. 
     Please refer to  FIG. 12 , which is a schematic top view of a semiconductor device in accordance with one embodiment of the present invention. In the embodiment of the present invention, the first low-K dielectric layer  126   a  formed along the sidewalls of bit lines  110  in early step of the process flow may effectively reduce the parasite capacitance induced by close spacing between bit lines and surrounding storage nodes. Furthermore, since the second low-K dielectric layer  134   a  is formed and disposed on the sidewalls surrounding the storage node regions  127  defined by bit lines  110  (horizontal direction) and the word lines  310  (vertical direction) in late step of the process flow, the entire storage node region may be enclosed by the second low-K dielectric layer  134   a , so that the issue of parasite capacitance may be further improved. 
     Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.