Patent Publication Number: US-2023139612-A1

Title: Semiconductor die, a semiconductor die stack, a semiconductor module, and methods of forming the semiconductor die and the semiconductor die stack

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     The present application claims priority to Korean Patent Application No. 10-2021-0146778, filed on Oct. 29, 2021, which is herein incorporated by reference in its entirety. 
     BACKGROUND 
     1. Field 
     The present disclosure provides a semiconductor die having support patterns, a semiconductor die stack having the semiconductor die, a semiconductor module having the semiconductor die stack, a method of manufacturing the semiconductor die, and a method of manufacturing a semiconductor module having the semiconductor die stack. 
     2. Description of the Related Art 
     A semiconductor die stack and a semiconductor module including stacked semiconductor dies have been proposed. 
     SUMMARY 
     In accordance with an aspect of the present disclosure, a semiconductor die stack includes a base die and core dies stacked over the base die. Each of the base die and the core dies include a semiconductor substrate, a first side passivation layer formed over a first side of the semiconductor substrate, a second side passivation layer over a second side of the semiconductor substrate, a through-via vertically penetrating the semiconductor substrate and the first side passivation layer, and a bump, a support pattern, and a bonding insulating layer formed over the first side passivation layer. Top surfaces of the bump, the support pattern, and the bonding insulating layer are co-planar. The bump is vertically aligned with the through-via. The support pattern is spaced apart from the through-via and the bump. The support pattern includes a plurality of first bars that extend in parallel with each other in a first direction and a plurality of second bars that extend in parallel with each other in a second direction. 
     In accordance with another aspect of the present disclosure, a semiconductor module includes an interposer and a logic device and a semiconductor die stack mounted over the interposer. The semiconductor die stack includes a base die, a lower core die stacked over the base die, an intermediate core die stacked over the lower core die, an upper core die stacked over the intermediate core die, and a top die stacked over the upper core die. The base die and the lower core die are bonded and stacked in a face-to-face method. The intermediate die, the upper core die, and the top die are stacked in a face-down method. 
     In accordance with another aspect of the present disclosure, a method of manufacturing a semiconductor die stack includes forming a first side passivation layer over a first side of the semiconductor substrate, forming a through-via that penetrates the semiconductor substrate, forming a bump and a support pattern over the first side passivation layer, forming a bonding insulating layer over the first side passivation layer to surround the bump and the support pattern, forming a second side passivation layer over a second side of the semiconductor substrate to form a base die, a lower core die, an intermediate core die, and an upper core die, stacking the lower core die over the base die in a face-to-face method, and stacking the intermediate core die and the upper core die over the lower core die in a face-down method. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG.  1    is a perspective view schematically illustrating a semiconductor module according to an embodiment of the present disclosure. 
         FIG.  2 A  is a longitudinal cross-sectional view schematically illustrating the semiconductor die stack according to an embodiment of the present disclosure. 
         FIG.  2 B  is a longitudinal cross-sectional view schematically illustrating the semiconductor dies being stacked. 
         FIG.  3 A  is a longitudinal cross-sectional view schematically illustrating the base die according to an embodiment of the present disclosure. 
         FIG.  3 B  is a longitudinal cross-sectional view schematically illustrating the core dies according to an embodiment of the present disclosure. 
         FIG.  3 C  is a longitudinal cross-sectional view schematically illustrating the top die according to an embodiment of the present disclosure. 
         FIGS.  4 A to  4 F  are top views of semiconductor dies in accordance with various embodiments of the present disclosure. 
         FIGS.  5 A to  5 G  illustrate methods of forming a semiconductor die according to an embodiment of the present disclosure. 
         FIG.  6    is a view illustrating a method of forming a base die according to an embodiment of the present disclosure. 
         FIGS.  7 A to  7 F  are views illustrating a method of forming a semiconductor die stack according to an embodiment of the present disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     Exemplary embodiments of the present disclosure will be described below in more detail with reference to the accompanying drawings. The present disclosure may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art. Throughout the disclosure, like reference numerals refer to like parts throughout the various figures and embodiments of the present disclosure. 
     It will be understood that, although the terms “first” and/or “second” may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element, from another element. For instance, a first element discussed below could be termed a second element without departing from the teachings of the present disclosure. Similarly, the second element could also be termed the first element. 
     Other expressions that explain the relationship between elements, such as “between”, “directly between”, “adjacent to” or “directly adjacent to” should be construed in the same way. 
     The drawings are not necessarily to scale and in some instances, proportions may have been exaggerated in order to clearly illustrate features of the embodiments. When a first layer is referred to as being “on” a second layer or “on” a substrate, it not only refers to a case where the first layer is formed directly on the second layer. 
       FIG.  1    is a perspective view schematically illustrating a semiconductor module  100  according to an embodiment of the present disclosure. Referring to  FIG.  1   , a semiconductor module  100  may include a logic device  20  and a semiconductor die stack  40  that are disposed on an interposer  10 . In an embodiment, the semiconductor module  100  may include a logic device  20  that is disposed on a central area of the interposer  10  and semiconductor die stacks  40  that are disposed on sides of the logic device  20 . The interposer  10  may include silicon, ceramics, a prepreg, or a PCB (printed circuit board). The interposer  10  may include metal interconnections for electrically connecting the logic device  20  and the semiconductor die stack  40 . The logic device  20  may include a microprocessor. The semiconductor die stack  40  may include a plurality of semiconductor dies  41 ,  43   a - 43   c , and  45 , which are vertically stacked. The logic device  20  and the semiconductor die stack  40  may be electrically connected to each other through electrical interconnections in the interposer  10 . The plurality of semiconductor dies  41 ,  43   a - 43   c , and  45  may include a memory semiconductor device, respectively. Accordingly, since the semiconductor module  100  includes a plurality of stacked memory semiconductor dies  41 ,  43   a - 43   c , and  45 , the semiconductor module  100  can provide a high-capacity memory. Since the semiconductor module  100  includes the semiconductor dies  41 ,  43   a - 43   c , and  45  positioned near the logic device  20 , communication between the logic device  20  and the semiconductor dies  41 ,  43   a - 43   c , and  45  in the semiconductor module  100  can operate in high speed. That is, the semiconductor module  100  may provide a high bandwidth memory (HBM) module. 
       FIG.  2 A  is a longitudinal cross-sectional view schematically illustrating the semiconductor die stack  40  according to an embodiment of the present disclosure, and  FIG.  2 B  is a longitudinal cross-sectional view schematically illustrating the semiconductor dies  41 ,  43   a - 43   c , and  45  being stacked. Referring to  FIGS.  2 A and  2 B , a semiconductor die stack  40  may include a base die  41  that is mounted on an interposer  10 , and a plurality of core dies  43   a - 43   c  that are stacked on the base die  41 , and a top die  45  that is stacked on the core dies  43   a - 43   c . 
     The base die  41  and a lower core die  43   a  may be stacked in a face-to-face method. For example, a front side S 1  of the base die  41  and a front side S 1  of the lower core die  43  may be bonded and stacked to face each other. Bumps  71  of the base die  41  and bumps  71  of the lower core die  43  may be directly bonded. Support patterns  73  of the base die  41  and support patterns  73  of the lower core die  43   a  may be directly bonded. A bonding insulating layer  67  of the base die  41  and a bonding insulating layer  67  of the lower core die  43   a  may be directly bonded. 
     The core dies  43   a - 43   c  may be stacked in a face-down method. That is, the core dies  43   a - 43   c  may be bonded and stacked so that the front sides S 1  face downward and the back sides S 2  face upward. For example, an intermediate core die  43   b  may be bonded and stacked on the lower core die  43   a  so that the back side S 2  of the lower core die  43   a  and the front side S 1  of the intermediate core die  43   b  may face each other. The upper core die  43   c  may be bonded and stacked on the intermediate core die  43   b  so that the back side S 2  of the intermediate core die  43   b  and the front side S 1  of the upper core die  43   c  may face each other. Accordingly, upper ends of the through-vias  62  of the lower core die  43   a  and the bumps  71  of the intermediate core die  43   b  may be directly bonded with each other, upper ends of the through-vias  62  of the intermediate core die  43   b  and the bumps  71  of the upper core die  43   c  may be directly bonded with each other, and upper ends of the through-vias  62  of the upper core die  43   c  and the bumps  71  of the top die  45  may be directly bonded with each other. In addition, a back side passivation layer  69  of the lower core die  43   a  may be in direct contact with the bonding insulating layer  67  and the support patterns  73  of the intermediate core die  43   b , a back side passivation layer  69  of the intermediate core die  43   b  may be in direct contact with the bonding insulating layer  67  and the support patterns  73  of the upper core die  43   c , and a back side passivation layer  69  of the upper core die  43   c  may be in direct contact with the bonding insulating layer  67  and the support patterns  73  of the top die  45 . 
     For the sake of lower power consumption with high-speed operation, the vertical thickness of the semiconductor die stack  40  has been gradually decreasing. To achieve this, the present disclosure decreases the vertical thickness of the semiconductor dies  41 ,  43   a - 43   c , and  45 . In addition, the present disclosure reduces the bonding distance between the semiconductor dies  41 ,  43   a - 43   c , and  45 . 
     If the thickness of the semiconductor dies  41 ,  43   a - 43   c , and  45  is reduced, during a bonding process and a stacking process, the semiconductor dies  41 ,  43   a - 43   c , and  45  cannot withstand heat and pressure for bonding and the semiconductor dies  41 ,  43   a - 43   c , and  45  may be bent or broken. In addition, if the solder bumps are omitted to reduce the bonding gap between the semiconductor dies  41 ,  43   a - 43   c , and  45 , an underfill or epoxy mold compound (EMC) cannot be sufficiently filled between the semiconductor dies  41 ,  43   a - 43   c , and  45 , so that physical and mechanical strength of the semiconductor die stack  40  may be weakened. 
     According to the present disclosure, in order to reduce the height of the semiconductor die stack  40 , the vertical thickness of the semiconductor dies  41 ,  43   a - 43   c , and  45  can be reduced, and the spacing between the semiconductor dies  41 ,  43   a - 43   c , and  45  can be minimized. 
     Specifically, the bumps  71  of the base die  41  and the bumps  71  of the lower core die  43   a  may be directly bonded without solder bumps. The through-vias  62  and the bumps  71  of the core dies  43   a - 43   c  and the top die  45  can be directly bonded without solder bumps and additional bumps. 
     The bonding insulating layer  67  and the back side passivation layer  69  may include the same material. Accordingly, chemically and physically strong bonding of the bonding insulating layer  67  and the back side passivation layer  69  can be achieved. A strong and stable bonding between the semiconductor dies  41 ,  43   a - 43   c , and  45  can be provided. 
     According to the present disclosure, since the bonding insulating layers  67  of the base die  41  and the lower core die  43   a  are directly contacted and bonded, an underfill or EMC might not be required, no void may be present, and a physically strong bond may be obtained. Since the back side passivation layers  69  and the bonding insulating layers  67  of the core dies  43   a - 43   c  and the bonding insulating layer  67  of the top die  45  are directly contacted and bonded, the underfill or EMC might not be required, no void may be present and a physically strong bond may be obtained. 
     According to the present disclosure, the support patterns  73  that are formed on the front side S 1  of the semiconductor substrate  60  can spread and dissipate the heat of the semiconductor dies  41 ,  43   a - 43   c , and  45 , and can physically support the semiconductor dies  41 ,  43   a - 43   c , and  45 . For example, with the heat that is generated during the bonding process, the support patterns  73  can decrease the amount of heat that is transferred to the electrical circuits in the semiconductor substrate  60 . Furthermore, the support patterns  73  can physically support the semiconductor dies  41 ,  43   a - 43   c , and  45  from the pressure that is applied during the bonding process. 
       FIG.  3 A  is a longitudinal cross-sectional view schematically illustrating the base die  41  according to an embodiment of the present disclosure. Referring to  FIG.  3 A , the base die  41  may include the semiconductor substrate  60 , the front side passivation layer  61 , the bumps  71  and the support patterns  73  on the seed layer  64 , the bonding insulating layer  67 , the through-vias  62 , the back side passivation layer  69 , and the pad patterns  75 . 
     The semiconductor substrate  60  of the base die  41  may include a silicon wafer and an interface circuit, a control circuit, and a test circuit that are formed on the silicon wafer. Each circuit may include transistors, conductive interconnections, conductive vias, capacitors, and multiple insulating layers. 
     The front side passivation layer  61  may be entirely formed on the front side S 1  of the semiconductor substrate  60 . The front side passivation layer  61  may physically and electrically protect electrical circuits in the semiconductor substrate  60 . The front side passivation layer  61  may insulate the electrical elements and the support patterns  73  in the semiconductor substrate  60 . The front side passivation layer  61  may include at least one of silicon nitride, polyimide, or other inorganic insulating materials. 
     Each the through-vias  62  may vertically penetrate the central portion of the semiconductor substrate  60  and the front side passivation layer  61 . The through-vias  62  may include metal pillars, such as copper (Cu). The through-vias  62  may be electrically connected to electrical circuits in the semiconductor substrate  60 . 
     The bumps  71  including the seed layers  64  may be formed on the front side passivation layer  61  to be vertically aligned with the through-vias  62 . The seed layers  64  may include a barrier metal layer, such as titanium nitride (TiN), and a seed metal layer, such as copper (Cu) or nickel (Ni). The bumps  71  may include a metal, such as copper (Cu). The bumps  71  may be electrically connected to the through-vias  62 . In an embodiment, input/output pads (not shown) may be disposed between the through-vias  62  and the seed layers  64  of the bumps  71 . The input/output pads may include a metal, such as aluminum (Al). 
     The support patterns  73  may be formed on the front side passivation layer  61 . The support patterns  73  may be electrically insulated from the through-vias  62  and any conductive elements in the semiconductor substrate  60 . That is, the support patterns  73  might not transmit electrical signals. The support patterns  73  may have the same vertical thickness as the bumps  71 . For example, top surfaces of the support patterns  73  and top surfaces of the bumps  71  may be co-planar. 
     The bonding insulating layer  67  may be formed on the front side passivation layer  61  to surround the bumps  71  and the support patterns  73 . The bonding insulating layer  67  may prevent atomic diffusion from the bumps  71  and the support patterns  73  during a bonding process. The bonding insulating layer  67  may include silicon nitride (SiN). A top surface of the bonding insulating layer  67  may be co-planar with the top surfaces of the bumps  71  and the support patterns  73 . In an embodiment, the top surface of the bonding insulating layer  67  may be recessed to be lower than the top surfaces of the bumps  71  and the support patterns  73 . 
     The back side passivation layer  69  may be conformally formed on the back side S 2  of the semiconductor substrate  60 . The back side passivation layer  69  may include the same material as the bonding insulating layer  67 . 
     The pad patterns  75  may be formed on the back side S 2  of the semiconductor substrate  60  to be vertically aligned with the through-vias  62 . The pad patterns  75  may include a metal, such as copper (Cu). 
       FIG.  3 B  is a longitudinal cross-sectional view schematically illustrating the core dies  43   a - 43   c  according to an embodiment of the present disclosure. Referring to  FIG.  3 B , the core dies  43   a - 43   c  may include the semiconductor substrate  60 , the front side passivation layer  61 , the bumps  71  and the support patterns  73  having the seed layers  64 , the bonding insulating layer  67 , the through-vias  62 , and the back side passivation layer  69 . The front side passivation layer  61 , the seed layers  64 , the bumps  71 , the support patterns  73 , and the bonding insulating layer  67  may be formed on the top surface of the semiconductor substrate  60 . The through-vias  62  may vertically penetrate the semiconductor substrate  60 . The back side passivation layer  69  may be formed on the bottom surface of the semiconductor substrate  60 . For example, the core dies  43   a - 43   c  may include a memory device, such as a DRAM. The semiconductor substrate  60  of the core dies  43   a - 43   c  may include a silicon wafer and memory circuits that are formed on the silicon wafer. The memory circuits may include transistors, conductive interconnections, conductive vias, capacitors, and a plurality of insulating layers. Compared to the base die  41  of  FIG.  3 A , the pad patterns  75  on the back side S 2  of the semiconductor substrate  60  may be omitted. 
       FIG.  3 C  is a longitudinal cross-sectional view schematically illustrating the top die  45  according to an embodiment of the present disclosure. Referring to  FIG.  3 C , the top die  45  may include the semiconductor substrate  60 , the front side passivation layer  61 , the bumps  71  and support patterns  73  having the seed layers  64 , and the bonding insulating layer  67 . Compared to the base die  41  and the core die  43   a - 43   c , shown in  FIGS.  3 A and  3 B , the through-vias  62  may be omitted. Also, the back side passivation layer  69  may be omitted. The semiconductor substrate  60  of the top die  45  may be thicker than the semiconductor substrate  60  of the core dies  43   a - 43   c . The top die  45  may include a memory device that is functionally same as the core die  43   a - 43   c . For example, the semiconductor substrate  60  of the top die  45  may include a silicon wafer and memory circuits formed on the silicon wafer. In an embodiment, the top die  45  may further include through-vias  62 . In an embodiment, the top die  45  may further include the back side passivation layer  69  of  FIG.  2 B . 
       FIGS.  4 A to  4 F  are top views of semiconductor dies  41 ,  43   a - 43   c , and  45  in accordance with various embodiments of the present disclosure. Referring to  FIGS.  4 A to  4 F , the semiconductor dies  41 ,  43   a - 43   c , and  45  may include the bumps  71 , the support patterns  73 , and the bonding insulating layer  67  that is disposed on the top surfaces thereof. The bumps  71  may be arranged to form at least one row in the central area of the semiconductor dies  41 ,  43   a - 43   c , and  45 . For example, in the drawings, the bumps  71  are arranged in two rows. The plurality of bumps  71  may be spaced apart from each other. The support patterns  73  may include edge support patterns  73   a  and center support patterns  73   b . The edge support patterns  73   a  may be disposed to be adjacent to edges of the semiconductor dies  41 ,  43   a - 43   c , and  45 , respectively. The center support patterns  73   b  may be disposed in central areas of the semiconductor dies  41 ,  43   a - 43   c , and  45 , respectively. As mentioned above, each of the center support patterns  73   b  may be spaced apart from the bumps  71 . 
     Referring to  FIG.  4 A , each of the edge support patterns  73   a  may have a line shape or a frame shape that extends along the edge of each of the semiconductor dies  41 ,  43   a - 43   c , and  45 . In an embodiment, each of the edge support patterns  73   a  may have a half-frame shape. In an embodiment, each of the edge support patterns  73   a  may have a quarter-frame shape. Each of the center support patterns  73   b  may have a bar shape that extends from each of the edge support patterns  73   a  to the central area of each of the semiconductor dies  41 ,  43   a - 43   c , and  45 . For example, each of the center support patterns  73   b  may include a first bar that extends in a first direction or a second bar that extends in a second direction. More specifically, the first bar may be a row bar that extends in a row direction, and the second bar may be a column bar that extends in a column direction. Each of the edge support patterns  73   a  and each of the center support patterns  73   b  may be connected to each other. 
     Referring to  FIG.  4 B , each of the center support patterns  73   b  may have a serpentine shape that extends from each of the edge support patterns  73   a  to the central area of each of the semiconductor dies  41 ,  43   a - 43   c , and  45 . For example, each of the center support patterns  73   b  may have first segments that extend in the first direction and second segments that extend in the second direction. More specifically, the first segments may be row segments that extend in the row direction, and the second segments may be column segments that extend in the column direction. 
     Referring to  FIGS.  4 C and  4 D , each of the edge support patterns  73   a  may be separated into a plurality of edge support patterns  73   a . For example, each of the separated edge support patterns  73   a  may have a bar shape or a segment shape. 
     Referring to  FIG.  4 E , each of the edge support patterns  73   a  may have a bar shape or a segment shape, and each of the center support patterns  73   b  may have a first bar shape and a second bar shape (i.e., a row bar shape and a column bar shape). Some of the center support patterns  73   b  may be connected to the edge support patterns  73   a , and some of the center support patterns  73   b  might not be connected to the edge support patterns  73   a . In an embodiment, with further reference to  FIGS.  4 A to  4 C , each of the edge support patterns  73   a  may have a half-frame shape or a quarter-frame shape. The center support patterns  73   b  may include a plurality of row bars and a plurality of column bars that are alternately arranged. 
     Referring to  FIG.  4 F , each of the center support patterns  73   b  may have a square shape. Each of the center support patterns  73   b  may be connected to the edge support patterns  73   a . 
     In an embodiment, the edge support patterns  73   a  may be omitted in  FIGS.  4 A to  4 F . 
     Referring to 4A to 4F, the support patterns  73  may include the plurality of edge support patterns  73   a  and the plurality of center support patterns  73   b  that extend in the row direction and the column direction. Accordingly, the physical pressure in the row direction and the column direction of the semiconductor dies  41 ,  43   a - 43   c , and  45  can be relieved, and warping or cracking of the semiconductor dies  41 ,  43   a - 43   c , and  45  can be prevented. 
     The support patterns  73  may include a plurality of separated edge support patterns  73   a  and a plurality of separated center support patterns  73   b . Alternatively, the support patterns  73  may have a serpentine shape. For example, one end of the row bars (or row segments) of the support patterns  73  may be connected to one end of the column bars (or column segments) of the support pattern  73  so that each of the support patterns  73  may have a serpentine shape. Accordingly, the edge support patterns  73   a  and the center support patterns  73   b  may have flexibility to withstand thermal and physical pressure in the row direction and the column direction and may have resistance to cracks. 
     The total surface area and total volume of the support patterns  73  may be sufficiently greater than the total surface area and total volume of the bumps  71 . Accordingly, heat that is generated from the semiconductor dies  41 ,  43   a - 43   c , and  45  may be effectively spread and dissipated through the support patterns  73 . 
       FIGS.  5 A to  5 E  illustrate a method of forming a semiconductor die according to an embodiment of the present disclosure. Referring to  FIG.  5 A , a method of forming a semiconductor die may include preparing a semiconductor substrate  60  having electrical circuits and insulating layers that are formed on a silicon wafer, forming through-vias  62  that vertically penetrate the semiconductor substrate  60 , and forming a front side passivation layer  61  on a front side S 1  of the semiconductor substrate  60 . Forming the front side passivation layer  61  may include performing a deposition process or a coating process to form at least one of silicon nitride (SiN) layer, a polyimide layer, or another inorganic insulating layer on the front side S 1  of the semiconductor substrate  60 . Forming the through-vias  62  may include forming a deep hole in the semiconductor substrate  60 , filling a conductive material in the hole, and thinning the semiconductor substrate  60 . Accordingly, the through-vias  62  may penetrate the semiconductor substrate  60 . Forming the through-vias  62  may include performing a plating process to form copper (Cu) pillars. Input/output pads (not shown) may be further formed on upper ends of the through-vias  62 . The input/output pads may be exposed on the front side passivation layer  61 . Lower ends of the through-vias  62  may also be exposed on the back side S 2  of the substrate  60 . 
     Referring to  FIG.  5 B , the method may further include forming a seed layer  64  on the front side passivation layer  61  and forming a plating mask pattern M on the front side passivation layer  61 . The seed layer  64  may be electrically connected to the upper ends of the through-vias  62 . The seed layer  64  may include a barrier metal layer and a plating metal layer. For example, the barrier metal layer may include a titanium (Ti) layer of titanium nitride (TiN) layer, and the plating metal layer may include a copper (Cu) layer. In an embodiment, the plating metal layer may include a nickel (Ni) layer or a titanium (Ti) layer. The plating mask pattern M may include a photoresist. The plating mask pattern M may include a plurality of holes H that expose the seed layer  64 . 
     Referring to  FIG.  5 C , the method may further include performing a plating process to form bumps  71  and support patterns  73  in the holes H. That is, the bumps  71  and the support patterns  73  may be formed at the same time and may include the same material. For example, the bumps  71  and the support patterns  73  may include copper (Cu). Top surfaces of the bumps  71  and the support patterns  73  may be co-planar. 
     Referring to  FIG.  5 D , the method may further include performing a strip process or an ashing process to remove the plating mask pattern M and performing an etching process to remove the seed layer  64  that is buried under the plating mask pattern M. The seed layer  64  may remain only under the bumps  71  and the support patterns  73 . The front side passivation layer  61  may be exposed between the bumps  71  and the support patterns  73 . 
     Referring to  FIG.  5 E , the method may further include performing a deposition process and a planarization process to form a bonding insulating layer  67  between the bumps  71 . The bonding insulating layer  67  may be formed by performing a deposition process, such as a chemical vapor deposition (CVD) process or a physical vapor deposition (PVD) process, to form an insulating material that covers the bumps  71  and the support patterns  73  on the front side passivation layer  61 , and by performing a planarization process, such as chemical mechanical polishing (CMP) or an etching process. The bonding insulating layer  67  may include silicon nitride (SiN). Since the bumps  71  and the support patterns  73  include copper, the bonding insulating layer  67  might not include silicon oxide (SiO 2 ). 
     In an embodiment, referring to  FIG.  5 F , the method may further include performing a CMP process or an etch-back process to recess a top surface of the bonding insulating layer  67 . The top surface of the bonding insulating layer  67  may be lower than the top surfaces of the bumps  71  and the support patterns  73 . 
     Referring to  FIG.  5 G , the method may further include forming a back side passivation layer  69  on a back side S 2  of the semiconductor substrate  60 . The back side passivation layer  69  may include the same material as the bonding insulating layer  67 . The back side passivation layer  69  may include silicon nitride (SiN). Forming the back side passivation layer  69  may include partially recessing the lower portion of the semiconductor substrate  60  so that the lower ends of the through-vias  62  protrudes from the semiconductor substrate  60 , forming a back side passivation material layer on the lower surface of the  60  to surround the lower ends of the through-vias  62 , and performing a planarization process, such as CMP or an etching process, to expose the lower ends of the through-vias  62 . The core dies  43   a - 43   c  may be formed by performing the processes that are described with reference to  FIGS.  5 A to  5 G . 
       FIG.  6    is a view illustrating a method of forming a base die  41  according to an embodiment of the present disclosure. Referring to  FIG.  6   , a method of forming a base die  41  may include forming pad patterns  75  that are aligned with the through-vias  62  on the back side passivation layer  69  on the bottom surface of the die described with reference to  FIGS.  5 A- 5 G . Forming the pad patterns  75  may include performing the processes that are described with reference to  FIGS.  3 A to  3 C . For example, the pad patterns  75  may also include a seed material and copper (Cu). The base die  41  may be formed by performing the processes that are described with reference to  FIGS.  5 A to  5 G  and  FIG.  6   . 
       FIGS.  7 A to  7 E  are views illustrating a method of forming a semiconductor die stack  40  according to an embodiment of the present disclosure. Referring to  FIG.  7 A , a method of forming a semiconductor die stack  40  may include treating surfaces of the bonding insulating layers  67 , the bumps  71 , and the support patterns  73  of the base die  41  and the lower core die  43   a  by performing a plasma treatment process. The plasma treatment may include processing the surface of the bonding insulating layer  67  at a temperature of substantially 100° C. to 400° C. by using a gas combination including at least one of nitrogen (N 2 ), oxygen (O 2 ), or (H 2 ). Through the plasma treatment, the adhesive force of the bonding insulating layer  67  of the base die  41  and the bonding insulating layer  67  of the lower core die  43   a  may be strengthened. Referring to  FIG.  7 B , the method may further include performing a first bonding process to bond and adhere the front side S 1  of the lower core die  43   a  to the front side S 1  of the base die  41  in a face-to-face method. The first bonding process may include heating and pressing the lower core die  43   a  to bond the front side S 1  of the lower core die  43   a  to the front side S 1  of the base die  41 . The bumps  71  of the base die  41  and the bumps  71  of the lower core die  43   a  may be directly bonded to each other, and the support patterns  73  of the base die  41  and the support patterns  73  of the lower core die  43   a  may be directly bonded to each other. In addition, the bonding insulating layer  67  of the base die  41  and the bonding insulating layer  67  of the lower core die  43   a  may be directly bonded to each other. 
     Referring to  FIG.  7 C , the method may further include treating the back side passivation layer  69  of the lower core die  43   a  and the front side passivation layer  61  of the intermediate core die  43   b  by performing the plasma treatment process. 
     Referring to  FIG.  7 D , the method may further include performing a second bonding process to bond and stack the front side S 1  of the intermediate core die  43   b  on the back side S 2  of the lower core die  43   a . The second bonding process may include heating and pressing the intermediate core die  43   b  to bond the front side S 1  of the intermediate core die  43   b  to the back side S 2  of the lower core die  43   a . 
     Referring to  FIG.  7 E , the method may include bonding and stacking the upper core die  43   c  on the intermediate core die  43   b  and bonding and stacking the top die  45  on the upper core die  43   c  by referring to the processes that are described with reference to  FIGS.  7 A to  7 D . The semiconductor die stack  40  may be formed by performing the processes that are described with reference to  FIGS.  7 A to  7 E . 
       FIG.  7 F  is a longitudinal cross-sectional view illustrating that the semiconductor die stack  40  according to an embodiment of the present disclosure is mounted on the interposer  10 . Referring to  FIG.  7 F , the semiconductor die stack  40  may be mounted on the interposer  10 . Connection pads  12  of the interposer  10  and the pad patterns  75  of the base die  41  of the semiconductor die stack  40  may be electrically connected to each other through solder bumps 15. Underfill or EMC (Epoxy Molding Compound) may be filled between the interposer  10  and the semiconductor die stack  40 . 
     According to the present disclosure, the bonding insulating layer of the base die and the bonding insulating layer of the lower core die are directly contacted and bonded. Accordingly, underfill or EMC are not required, there is no void, and a physically strong bonding can be obtained. 
     The back side passivation layers and the bonding insulating layers of the core dies and the bonding insulating layer of the top die may be directly contacted and bonded. Accordingly, the underfill or the EMC might not be required, no void may be present, and a physically strong bonding may be obtained. 
     According to the present disclosure, heat of the semiconductor dies may be spread and dissipated by the support patterns formed on the front side of the semiconductor substrate. The semiconductor dies may be physically supported by the support patterns formed on the front side of the semiconductor substrate. 
     Accordingly, with the heat that is generated during the bonding process, the support patterns can decrease the amount of heat that is transferred to the electrical circuits in the semiconductor substrate, and the semiconductor dies may be physically supported against the pressure that is applied during the bonding process. 
     According to the embodiments of the present disclosure, off-current and leakage current of the transistor can be reduced, and data retention of the semiconductor device can be improved. 
     Although the present disclosure has been specifically described according to the above-described preferred embodiments, it should be noted that the above-described embodiments are for the purpose of explanation and not for the limitation thereof. In addition, it will be appreciated by person having ordinary skill in the art that various embodiments are possible within the scope of the present disclosure.