Patent Publication Number: US-7592688-B2

Title: Semiconductor package

Description:
RELATED APPLICATION 
     This application is based on and claims priority to the of U.S. Provisional Application Ser. No. 60/758,764, filed on Jan. 13, 2006, entitled Semiconductor Package, to which a claim of priority is hereby made and the disclosure of which is incorporated by reference. 
    
    
     BACKGROUND OF THE INVENTION 
     To integrate a semiconductor component into an electronic circuit, the component must be packaged.  FIG. 1  shows the cross-section of a typical, multi-chip package  5 , which includes substrate  6 , semiconductor components  7 , and molded housing  8 . It should be noted that semiconductor components are interconnected inside the package and to external connectors (not shown) by connectors such as bond wires  9 A and in some cases conductive clips, e.g.  9 B. 
     Such semiconductors add to the overall resistance and inductance of the package, and cause undesirable effects such as ringing. 
     Furthermore, if the package contains heat generating components, in a conventional package such as package  5 , a heatsink (not shown) may be thermally coupled to substrate  6  to dissipate the generated heat. The size of the heatsink typically depends on the amount of heat generated. Thus, a large amount of heat would require a larger heatsink. Therefore, heat generation has a bearing on the size of the package. 
     U.S. Pat. No. 7,045,884, which is assigned to the assignee of the present invention disclosed a package which overcomes the drawbacks of the prior art as set forth above. Referring to  FIG. 2 , semiconductor package  10  according to U.S. Pat. No. 7,045,884 includes first circuit board  12 , and second circuit board  14  which is assembled over first circuit board  12 . Circuit boards  12 ,  14  are of the thermally conductive variety such as insulated metal substrate (IMS), or Direct-bonded copper (DBC). Such circuit boards include a thermally conductive, but electrically insulating body which can have conductive patterns formed over at least one of its surfaces. In the one disclosed embodiment, first circuit board  12  includes a plurality of external connectors  16  which serve as input and output connectors to the elements disposed between first circuit board  12  and second circuit board  14 . 
     Referring next to  FIG. 3 , semiconductor package  10  includes a plurality of power MOSFETs T 1 , T 2 , T 3 , T 4 , T 5 , T 6  which are interconnected to form three parallel-connected half-bridge circuits, each for driving a respective phase of a three-phase motor. 
     As is well known in the art, each half-bridge circuit includes a high side MOSFET, T 3 , T 2 , T 1  and a low side MOSFET T 4 , T 5 , T 6 . When power MOSFETs are used to form half-bridge circuits, the source contact of the high side MOSFET, e.g. T 1 , is series connected to the drain contact of the low side MOSFET e.g. T 6 , while the drain contact of the high side MOSFET is connected to the input power V +  and the source contact of the low side MOSFET is connected to the ground G. Referring to  FIG. 3 , in the first embodiment of the present invention MOSFET T 3 , forms a half-bridge with MOSFET T 4 , MOSFET T 2 forms a half-bridge with MOSFET T 5 , and MOSFET T 1  forms a half-bridge with MOSFET T 6 . As is well known the output of each half-bridge circuit A, B, C is taken from the connection point of its high side MOSFET to its respective low side MOSFET as shown by  FIG. 3 . To operate each MOSFET T 1 , T 2 , T 3 , T 4 , T 5 , T 6 , a gate signal is sent by a control circuit (not shown) through a respective gate connection G 1 , G 2 , G 3 , G 4 , G 5 , G 6 . 
     Referring now to  FIG. 4 , first circuit board  12  includes a plurality of source conductive pads  18   T1 ,  18   T2 ,  18   T3  for receiving source contacts of high side MOSFETS T 1 , T 2 , T 3 , respectively, and drain conductive pads  20   T6 ,  20   T5 ,  20   T4  for receiving the drain contacts of low side MOSFETs T 6 , T 5 , T 4 , respectively. Each conductive pad is an area on a conductive track which has been exposed through an opening in a solder passivation layer formed on the conductive track. The conductive track is itself disposed on the thermally conductive body of a circuit board  12 ,  14 . Specifically, each conductive track is a layer of conductive material, such as copper or aluminum, which is patterned to a desired configuration. Conductive tracks are covered with solder passivation material, and openings are formed in the solder passivation material to expose portions of the conductive tracks to serve as conductive pads. 
     Source conductive pad  18   T1  is connected electrically through a conductive trace  22  on circuit board  12  to conductive pad  20   T6 , and then connected to external connector  16   A  through another conductive trace  22  on circuit board  12 . Each conductive trace  22  is essentially a portion of the conductive track which electrically connects conductive pads together or to an external connection. Specifically, for example, as will be shown, source conductive pad  18   T1 , drain conductive pad  20   T2 , and traces  22 , and external connector  16   A  form a conductive track that provides an output connection for the half-bridge circuit that is formed by MOSFETs T 1  and T 6 . 
     Conductive pads  18   T2 , and  18   T3  are similarly connected to conductive pads  20   T5  and  20   T4  and then to external connectors  16   B  and  16   C  in a similar manner. As a result, source contacts of high side MOSFETs T 1 , T 2 , T 3  are electrically connected to drain contacts of respective low side MOSFETs T 6 , T 5 , T 4  and then connected to external connectors  16   A ,  16   B ,  16   C , which serve as output connections for each half-bridge circuit without using any wirebonds. 
     First circuit board  12  also includes gate conductive pads  24   T1 ,  24   T2 ,  24   T3  each for receiving a respective gate contact of high side MOSFETs T 1 , T 2 , T 3 . Gate conductive pad  24   T1  is connected via a trace  22  to external connector  16   G1 , which serves as the gate connection for receiving a gate signal for high side MOSFET T 1 . Similarly, gate pads  24   T2  and  24   T3  are connected to output connectors  16   G2  and  16   G3  respectively via traces  22 . Connectors  16   G2 ,  16   G3  serve as gate connections for high side MOSFETs T 2 , T 3 . 
     Referring now to  FIG. 5 , second circuit board  14  includes drain conductive pads  20   T1 ,  20   T2 ,  20   T3  for receiving drain contacts of high side MOSFETs T 1 , T 2 , T 3 . Second circuit board  14  also includes interconnect conductive pads  28   V+  and  28   Vground . Drain conductive pads  20   T1 ,  20   T2 ,  20   T3  are formed on the same conductive trace as interconnect conductive pads  28   V+ . Interconnect pads  28   V+  are electrically connectable to interconnect pad  29   V+  on first circuit board  12 , which is electrically connected to external connector  16   V+  via a trace  22 . As a result drain contacts of high side MOSFET T 1 , T 2 , T 3  will be connected electrically to external connector  16   V+ . External connector  16   V+  in the first embodiment of the present invention serves as the connection to the input power V + , when second circuit board  14  is disposed over first circuit board  12 . 
     Second circuit board  14  also includes gate conductive pads  24   T4 ,  24   T5 ,  24   T6  for receiving gate contacts of low side MOSFETs T 4 , T 5 , T 6 . Each gate conductive pad  24   T4 ,  24   T5 ,  24   T6  is electrically connected to gate interconnect pads  28   G4 ,  28   G5 ,  28   G6  via a respective trace  22 . Each gate interconnect pad  28   G4 ,  28   G5 ,  28   G6  is then connected to a corresponding gate interconnect pad  29   G4 ,  29   G5 ,  29   G6  on first circuit board  12 , and thereby electrically connected via a respective trace  22  to a corresponding gate connector  16   G4 ,  16   G5 ,  16   G6 . 
     Also disposed on second circuit board  14  are source conductive pads  18   T4 ,  18   T5 ,  18   T6 , and ground interconnect pads  28   ground . Source conductive pads  18   T4 ,  18   T5 ,  18   T6  and ground interconnect pads  28   ground  are formed on a common conductive track and, therefore, are electrically connected together. Ground interconnect pads  28   ground  on second circuit board  14  are connected to corresponding ground interconnect pads  29   ground  on first circuit board  12 , which are in turn connected via a common trace  32  to external ground connector  16   ground . As a result, source contacts of low side MOSFETs T 4 , T 5 , T 6  are connectable to a ground connection via external connector  16   ground . 
     Referring now to  FIGS. 6 and 7 , source contact, e.g. ST 1 , of each high side MOSFET T 1 , T 2 , T 3  is electrically connected to a corresponding source conductive pad  18   T1 ,  18   T2 ,  18   T3 , and each gate contact, e.g. GT 1 , of each high side MOSFET T 1 , T 2 , T 3  is electrically connected to a corresponding gate conductive pad  24   T1 ,  24   T2 ,  24   T3 . Also, each drain contact, e.g. DT 6 , of each low side MOSFET T 4 , T 5 , T 6  is electrically connected to its corresponding drain conductive pad, e.g.  20   T6 , on first circuit board  12 . Electrical connection in each case is made by a layer of conductive adhesive  33  such as solder or conductive epoxy. It should be noted that source contact and the gate contact of each MOSFET are exposed through a solder passivation  19  (shown by crossing lines in  FIG. 6 ) layer which prevents the solder (or any other conductive adhesive) from shorting the gate contact to the source contact. 
     Referring now specifically to  FIG. 7 , second circuit board  14  is assembled opposite first circuit board  12  such that drain contact, e.g. DT 1  of each high side MOSFET T 1 , T 2 , T 3  is electrically connected via a layer of conductive adhesive  33  to its corresponding drain conductive pad, e.g.  20   T1 , on second circuit board  14 . Similarly, source contact, e.g. ST 6 , of each low side MOSFET T 4 , T 5 , T 6  is electrically connected via a layer of conductive adhesive  33  to its corresponding source conductive pad, e.g.  18 T 6  on second circuit board  14 , and gate contact, e.g. GT 6 , of each low side MOSFET, T 4 , T 5 , T 6 , is electrically connected to its corresponding gate conductive pad, e.g.  24   T6 , via a layer of conductive adhesive  33 . 
     Also shown in  FIG. 7 , is interconnect  35  which electrically connects ground conductive pad  29   ground  on first circuit board  12  to ground conductive pad  28   ground  on second circuit board  14 . Interconnect  35  is connected to each conductive pad via a layer of conductive adhesive  33 . Interconnect  35  may be any conductive body such as a copper slug. 
       FIG. 7  shows that low side MOSFET T 6 , high side MOSFET T 1  and interconnect  35  are connected between first circuit board  12  and second circuit board  14 . The remaining high side MOSFETs T 2 , T 3  and low side MOSFETs T 4 , T 5  are connected in the same manner as that of high side MOSFET T 1  and low side MOSFET T 6 . Furthermore, interconnects are used to connect internal gate conductive pads  28   G4 ,  28   G5 ,  28   G6  to internal conductive pads  29   G4 ,  29   G5 ,  29   G6 , and internal conductive pads  28   V+  to conductive pads  29   V+  in the same manner as described for interconnect  35  above. 
     Referring now to  FIG. 8 , once second circuit board  14  is assembled over first circuit board  12 , an epoxy underfilling  37  is provided in the spaces between first circuit board  12  and second circuit board  14 . The purpose of epoxy underfilling  37  is to protect MOSFETs from environmental conditions such as moisture. As shown by  FIG. 8 , a heatsink  40  may be thermally coupled to second circuit board  14  to assist in heat dissipation. Heatsink  40  may also be coupled to first circuit board  12  without deviating from the present invention. 
     Each circuit board  12 ,  14  may receive a heatsink to effect double-sided cooling. Advantageously, because of double-sided cooling, smaller heatsinks can be used (instead of one large heatsink) thereby reducing the overall size of the package. 
     Referring now to  FIGS. 9A-9D , semiconductor package  10  is manufactured according to the following process. First, solder paste (shown by slanted lines) or some other conductive adhesive is printed on the conductive pads on first circuit board  12 . Next, as illustrated by  FIG. 9B , high side MOSFETs T 1 , T 2 , T 3  and low side MOSFETs T 4 , T 5 , T 6  are placed on their respective positions on first circuit board  12 . Thereafter, as illustrated by  FIG. 9C , solder paste (shown by slanted lines) or some other conductive adhesive is printed on the conductive pads on second circuit board  14 , and, as shown by  FIG. 9D , second circuit board  14  is placed over first circuit and then the entire structure is heated to cause the solder paste to be reflown. Thereafter, epoxy is disposed to fill the space between first circuit board  12  and second circuit board  14 . 
     A plurality of first circuit boards  12  may be linked together to form a large panel and MOSFETs T 1 , T 2 , T 3 , T 4 , T 5 , T 6  and second circuit boards  14  may be placed by a pick-and-place machine. Then, first circuit boards  12  are cut from the large panel to form individual packages after epoxy underfilling has been applied. 
     A multi-chip package according to the present invention includes several improvements to the package described above with reference to  FIG. 1-9 . 
     A package according to the present invention, for example, includes a metallic body extending over preferably the entire free surface of one of the two circuit boards. Furthermore, a package according to the present invention includes at least one external connector which is raised to be coplanar with the metallic body. The external connector may be a copper slug which is electrically connected to a respective conductive track on one of the circuit boards. In one preferred embodiment a package according to the present invention includes elements of only a single half bridge. 
     A package according to the present invention may further include a dielectric underfilling disposed between the circuit boards and around the semiconductor devices disposed therebetween. 
     To optimize the performance of a package according to the present invention at least one of the semiconductor devices contained therein may be rectangular (rather than square) with a long and thin aspect ratio in order to 
     a) minimize adverse thermal characteristics; 
     b) increase switching speed; 
     c) max out the solderable area to further improved thermal performance. 
     A package according to the present invention may be further improved by using a monolithic integrated MOSFET and schottky component, instead of a packaged device containing a discreet MOSFET and a discreet schottky. 
     Other features and advantages of the present invention will become apparent from the following description of the invention which refers to the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  shows a cross-sectional view of a semiconductor package according to the prior art; 
         FIG. 2  shows the top plan view of a semiconductor package according to the prior art; 
         FIG. 3  shows the circuit diagram for the components disposed within a package according to  FIG. 2 ; 
         FIG. 4  shows a top plan view of a circuit board used in a package according to the prior art; 
         FIG. 5  shows a top plan view of another circuit board used in a package according to the prior art; 
         FIG. 6  shows a top plan view of the circuit board shown by  FIG. 4  which includes a plurality of semiconductor switching devices; 
         FIG. 7  shows a cross-sectional view of a package taken along line  7 - 7  in  FIG. 2  viewed in the direction of the arrows; 
         FIG. 8  shows a side view of a package according to the prior art which has a heatsink mounted on one side thereof; 
         FIGS. 9A-9D  illustrate the processing steps taken for the manufacture of a package according to the prior art; 
         FIG. 10  illustrates a circuit diagram for a single half-bridge; 
         FIG. 11  shows a top plan view of a package according to the present invention. 
         FIG. 12  shows a cross-sectional view of a package according to the present invention along line  12 - 12  viewed in the direction of the arrows. 
         FIGS. 13A-13C  illustrate selected steps in the assembly of a package according to the present invention. 
         FIG. 14  shows a top plan view of a novel semiconductor device configuration that may be used in an embodiment of the present invention. 
         FIG. 15  shows a top plan view of a package according to another embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE FIGURES 
     A package according to the preferred embodiment of the present invention includes only a single (as opposed to several) half-bridge circuit elements. Referring to  FIG. 10 , a single half-bridge includes a high side switch  100  and a low side switch  102 . Preferably, switches  100 ,  102  are N-channel MOSFETs each including a gate electrode G 1 , G 2 , a source electrode S 1 , S 2  and a drain electrode D 1 , D 2 . To form a half-bridge, drain electrode D 2  of low side MOSFET  102  is connected to source electrode S 1  of high side MOSFET  100 , drain electrode D 1  of high side MOSFET  100  is connected to the power input V +  and source electrode S 2  of low side MOSFET  102  is connected to the ground G. As is well known, the output  104  may be taken from the connection point of low side MOSFET  102  and high side MOSFET  100 . The half-bridge circuit in a package according to the present invention may be used for controlling power that is fed to, for example, a phase of a motor, or the half-bridge may be configured to serve in the power stage of a power converter, such as a buck converter. When used in a buck converter or the like high side MOSFET  100  may be configured to serve as the control switch and low side MOSFET  102  may be configured to serve as the synchronous switch. 
     Referring now to  FIGS. 11 and 12 , a package according to the present invention includes a first circuit board  106 , and a second circuit board  108 . Each circuit board  106 ,  108  may be an IMS, DBC or the like material. To enhance thermal performance, circuit boards comprising of AlSiC or Cu—Mo—Cu may be used. Circuit board  106  includes one conductive track  110  which electrically connects source electrode S 1  of high side MOSFET  102 . Specifically, source electrode S 1  is electrically and mechanically coupled to conductive track  110  through a conductive adhesive body  112 , and drain electrode D 2  is electrically and mechanically coupled to track  110  through another conductive adhesive body  112 . Conductive adhesive body  112  as referred to herein may be solder or a conductive epoxy or the like. 
     Circuit board  108  also includes a conductive track  114  which is electrically and mechanically coupled to drain electrode D 1  of MOSFET  100  through a conductive adhesive body  112 . Track  114  is in turn connected to conductive track  116  on circuit board  106  through an interconnect  118 , which may be a metallic slug, e.g. a copper slug. Note that a conductive adhesive is also used to couple interconnect  118  between track  114 ,  116 . Further note that track  116  is for receiving power input V + . 
     Source electrode S 2  and gate electrode G 2  are both electrically connected to respective tracks  120 , and track  122  by a conductive adhesive body  112 . Gate electrode G 1  is also electrically connected to respective conductive track  124  through a conductive adhesive body  112 . 
     Track  110 , which serves to connect source electrode S 1  and drain electrode D 2 , serves as the output node  104  of the half-bridge. 
     According to one aspect of the invention, circuit board  108  includes a metallic body  126  (e.g. copper) spread across preferably the entire exterior surface thereof. Metallic body  126  can serve as a heat spreader, or it may be a base for thermal connection to a heatsink or the like body. 
     According to another aspect of the present invention, each track includes a metallic connector  128 , which serves as a lead connected to the end thereof. Metallic connector  128  may be formed of copper or a copper alloy, and is electrically and mechanically coupled to a respective track using a conductive adhesive body  112 . Note that the free end of connector  128  is coplanar with metallic body  126  on circuit board  108 . Thus, together, when a package according to the present invention is mounted on a circuit board or the like connectors  128  can be connected to respective pads on the circuit board, while metallic body  126  can be thermally connected to for example a heatsink or the like embedded in the circuit board. 
     Note that in one preferred embodiment a dielectric underfilling  103  may be disposed between circuit boards  106 ,  108  and around MOSFETs  100 ,  102 . Dielectric underfilling  103  may be a conductive epoxy or the like material, and can be used to improve the thermal performance of the package, protect the die, and improve the mechanical integrity of the package. 
     Referring now to  FIGS. 13A-13C , to fabricate a package according to the present invention source S 1  of high side MOSFET  100  is disposed over receiving areas  130  of track  110 , and drain electrode D 2  of low side MOSFET  102  is disposed over receiving area  132  of track  110 . Note that a conductive adhesive may be pre-applied to either electrodes S 1 , D 2  or to receiving areas  130 ,  132  before the disposition of the MOSFETs thereon. Similarly, gate electrode G 1  is disposed over receiving area  134  of track  124 , with a conductive adhesive either pre-applied to the gate electrode or the receiving area  134 . Note also that (although not shown specifically) at this stage dielectric underfilling  103  may be applied around MOSFETs  100 ,  102 . The result is shown by  FIG. 13B . 
     Next, interconnects  118  may be disposed over respective receiving areas  136  of tracks  116 ,  138 . Note that track  138  will serve to connect the ground to source electrode S 2 . Note also that a conductive adhesive is applied between each interconnect  118  and a receiving area  136 . Thereafter, circuit board  108  is assembled. Specifically, circuit board  108  includes track  140  which includes area  142  for electrical connection to drain D 1  and receiving areas  144  for electrical connection to interconnects  118  that are disposed over receiving areas  136  on track  138 . Circuit board  108  further includes track  146 . Track  146  includes receiving areas  148  for connection to source electrodes S 2 , and receiving areas  150  for electrical connection to interconnects  118  that are disposed over receiving areas  136  of track  138 . Furthermore, circuit board  108  includes track  122  which include a receiving area  154  for electrical connection to gate electrode G 2 . Track  152  includes a connection area  156  which is electrically connected to the connection surface  158  of track  152  on circuit board  106 . Electrical connection in each instance may be realized through a conductive adhesive. 
     Note that connectors  126  may be electrically and mechanically coupled to respective tracks as described above to realize a package according to the present invention. The following table discloses the designation for each track. 
     
       
         
           
               
               
             
               
                   
               
               
                 TRACK 
                 DESIGNATION 
               
               
                   
               
             
            
               
                 152 
                 G 2   
               
               
                 124 
                 G 1   
               
               
                 138 
                  G (ground) 
               
               
                 110 
                 104 (output) 
               
               
                 116 
                 V +  (input) 
               
               
                   
               
            
           
         
       
     
     Referring now to  FIG. 14 , according to another embodiment, one of said MOSFETs  100 ,  102 , or both can be rectangular (having a length that is longer than a width thereof) as opposed to being square (which is the conventional configuration). Thus, for example, when the package is a half-bridge, low side MOSFET  102  may be rectangular, or when the package includes a half-bridge for a buck converter MOSFET  102 , which serves as the synchronous FET, may be rectangular. Note that the use of a rectangular MOSFET is not limited to a single half-bridge/single phase package. Rather, such a die may be used in a multi-phase package according to the prior art as described herein. 
     Referring now to  FIG. 15 , in another embodiment of the present invention, connectors  128  may be disposed at opposing edges of circuit board  106 , instead of being disposed at one edge thereof. Such an arrangement may further render stability to the package when it is surface mounted. 
     In all the embodiments disclosed herein an IC, and passive components may be integrated with the power MOSFETs between the two circuit boards to obtain a multi-chip fully integrated power module assembly. 
     Although the present invention has been described in relation to particular embodiments thereof, many other variations and modifications and other uses will become apparent to those skilled in the art. It is preferred, therefore, that the present invention be limited not by the specific disclosure herein, but only by the appended claims.