Patent Publication Number: US-10321560-B2

Title: Dummy core plus plating resist restrict resin process and structure

Description:
CROSS-REFERENCE TO RELATED APPLICATION(S) 
     This application claims priority under 35 U.S.C. § 119(a)-(d) of the Chinese Patent Application No: 201510770530.9, filed Nov. 12, 2015 and titled, “DUMMY CORE PLUS PLATING RESIST RESTRICT RESIN PROCESS AND STRUCTURE,” which is hereby incorporated by reference in its entirety for all purposes. 
     FIELD OF THE INVENTION 
     The present invention is generally directed to printed circuit boards. More specifically, the present invention is directed to printed circuit boards having select exposure of inner layer circuitry. 
     BACKGROUND OF THE INVENTION 
     A printed circuit board (PCB) mechanically supports and electrically connects electronic components using conductive traces, pads and other features etched from electrically conductive sheets, such as copper sheets, laminated onto a non-conductive substrate. Multi-layered printed circuit boards are formed by stacking and laminating multiple such etched conductive sheet/non-conductive substrate. Conductors on different layers are interconnected with plated-through holes called vias. 
     A printed circuit board includes a plurality of stacked layers, the layers made of alternating non-conductive layers and conductive layers. The non-conductive layers can be made of prepreg or base material that is part of a core structure, or simply core. Prepreg is a fibrous reinforcement material impregnated or coated with a thermosetting resin binder, and consolidated and cured to an intermediate stage semi-solid product. Prepreg is used as an adhesive layer to bond discrete layers of multilayer PCB construction, where a multilayer PCB consists of alternative layers of conductors and base materials bonded together, including at least one internal conductive layer. A base material is an organic or inorganic material used to support a pattern of conductor material. A core is a metal clad base material where the base material has integral metal conductor material on one or both sides. A laminated stack is formed by stacking multiple core structures with intervening prepreg and then laminating the stack. A via is then formed by drilling a hole through the laminated stack and plating the wall of the hole with electrically conductive material, such as copper. The resulting plating interconnects the conductive layers. In some applications, the plating extends uninterrupted through the entire thickness of the via and each conductive layer is connected to the plating, thereby providing a common interconnection with each and every conductive layer. In other applications, it may be desired that only certain conductive layers be commonly interconnected by the plating within the via. 
     SUMMARY OF THE INVENTION 
     Embodiments are directed to a printed circuit board having multiple layers, where select portions of inner layer circuitry, referred to as inner core circuitry, are exposed from the remaining layers. The printed circuit board having an exposed inner core circuitry is formed using a dummy core plus plating resist process. The select inner core circuitry is part of an inner core. During manufacturing of the printed circuit board, a plating resist is applied over the select inner core circuitry and a dummy core is applied over the plating resist. The plating resist and the dummy core protect the select inner core circuitry during subsequent process steps and also enable exposure of the select inner core circuitry as described in detail below. In some embodiments, the inner core corresponding to the exposed inner core circuitry forms a semi-flexible, or semi-flex, PCB portion. The semi-flex PCB portion is an extension of the remaining adjacent multiple layer PCB. The remaining portion of the multiple layer PCB is rigid, referred to as the rigid PCB portion. The inner core is a layer(s) of the printed circuit board and is therefore common to both the semi-flex PCB portion and the remaining rigid PCB portion. The semi-flex PCB portion can be formed as an interior portion of the printed circuit board such that a rigid PCB portion is coupled to either end of the semi-flex PCB portion. In other embodiments, the portion of the printed circuit board corresponding to the exposed inner core circuitry is rigid, referred to as a rigid exposed circuitry PCB portion. The rigid exposed circuitry PCB portion can be formed at the perimeter of the printed circuit board such that one end of the rigid exposed circuitry PCB portion is coupled to a rigid PCB portion and the other end of the rigid exposed circuitry PCB portion is uncoupled, for example forming one or more recessed gold finger connectors. 
     In an aspect, a printed circuit board is disclosed. The printed circuit board includes a rigid printed circuit board portion and a semi-flexible printed circuit board portion. The rigid printed circuit board portion includes a laminated stack of a plurality of non-conducting layers and a plurality of conductive layers, wherein the laminated stack further includes a first portion of an inner core structure. The semi-flexible printed circuit board portion includes a second portion of the inner core structure, wherein the inner core structure is a continuous structure that extends through both the rigid printed circuit board portion and the semi-flexible printed circuit board portion, further wherein the second portion of the inner core structure includes exposed inner core circuitry and plating resist material. In some embodiments, each of the conductive layers is pattern etched. In some embodiments, the printed circuit board also includes one or more plated through hole vias in the rigid printed circuit board portion. In some embodiments, the rigid printed circuit board portion includes a first rigid printed circuit board portion, further wherein the printed circuit board further includes a second rigid printed circuit board portion including a second laminated stack of a plurality of non-conducting layers and a plurality of conductive layers, wherein the second laminated stack further includes a third portion of an inner core structure. In some embodiments, the inner core structure includes an inner core non-conductive layer having a first surface and a first conductive layer positioned on the first surface of the inner core non-conductive layer. In some embodiments, the first conductive layer of the inner core structure includes the inner core circuitry in the second portion of the inner core structure. In some embodiments, the inner core non-conductive layer has a second surface opposing the first surface, further wherein the inner core structure further includes a second conductive layer positioned on the second surface of the inner core non-conductive layer. In some embodiments, the second conductive layer of the inner core structure includes the inner core circuitry in the second portion of the inner core structure. 
     In another aspect, a printed circuit board set form is disclosed. The printed circuit board set form comprises a plurality of printed circuit boards and a breakaway substrate. The plurality of printed circuit boards are aligned within a common plane, wherein each printed circuit board is mechanically connected by a common substrate. Each printed circuit board comprises a rigid printed circuit board portion and a semi-flexible printed circuit board portion. The rigid printed circuit board portion comprises a laminated stack of a plurality of non-conducting layers and a plurality of conductive layers, wherein the laminated stack further comprises a first portion of an inner core structure. The semi-flexible printed circuit board portion comprises a second portion of the inner core structure, wherein the inner core structure is a continuous structure that extends through both the rigid printed circuit board portion and the semi-flexible printed circuit board portion, further wherein the second portion of the inner core structure comprises exposed inner core circuitry and plating resist material. The breakaway substrate is aligned within the common plane and is mechanically connected around a perimeter of the connected plurality of printed circuit boards, wherein the breakaway substrate includes a dummy core portion. In some embodiments, the breakaway substrate provides lateral structural stability to the connected plurality of printed circuit boards. In some embodiments, the plurality of printed circuit boards are electrically isolated from each other. In some embodiments, each of the conductive layers is pattern etched. In some embodiments, the printed circuit board set form further comprises one or more plated through hole vias in the rigid circuit board portion. In some embodiments, the rigid printed circuit board portion comprises a first rigid printed circuit board portion, further wherein the printed circuit board further comprises a second rigid printed circuit board portion comprising a second laminated stack of a plurality of non-conducting layers and a plurality of conductive layers, wherein the second laminated stack further comprises a third portion of an inner core structure. In some embodiments, the inner core structure comprises an inner core non-conductive layer having a first surface and a first conductive layer positioned on the first surface of the inner core non-conductive layer. In some embodiments, the first conductive layer of the inner core structure comprises the inner core circuitry in the second portion of the inner core structure. In some embodiments, the inner core non-conductive layer has a second surface opposing the first surface, further wherein the inner core structure further comprises a second conductive layer positioned on the second surface of the inner core non-conductive layer. In some embodiments, the second conductive layer of the inner core structure comprises the inner core circuitry in the second portion of the inner core structure. 
     In yet another aspect, a method of manufacturing a printed circuit board is disclosed. The method comprises forming an inner core structure having an inner core circuitry on at least one surface of the inner core structure, applying a plating resist over the inner core circuitry, and forming a printed circuit board stack up, wherein the printed circuit board stack up comprises the inner core structure, a dummy core, one or more non-conductive layers and one or more conductive layers. The dummy core is stacked on the plating resist. The method further comprises laminating the printed circuit board stack up, thereby forming a laminated stack, forming a depth controlled rout from a surface of the laminated stack to the dummy core and around a perimeter of the dummy core, wherein a portion of the laminated stack within the perimeter of the rout and to a depth including the dummy core forms a laminated stack cap. The method further comprises removing the laminated stack cap, thereby exposing the plating resist, and stripping the plating resist, thereby exposing the inner core circuitry. In some embodiments, stripping the plating resist leaves a residual portion of plating resist. In some embodiments, the perimeter of the dummy core corresponds to a perimeter of the inner core circuitry. In some embodiments, the method further comprises forming the dummy core, wherein the dummy core comprises a non-conductive layer and a conductive layer. In some embodiments, the dummy core is stacked on the plating resist such that the conductive layer of the dummy core contacts the plating resist. In some embodiments, the method further comprises forming at least one plated through hole via in the laminated stack prior to forming the depth controlled rout, wherein the at least one plated through hole via is not aligned within the inner core circuitry. In some embodiments, the method further comprises pattern etching the conductive layers in the laminated stack prior to forming the printed circuit board stack up. In some embodiments, forming the inner core structure comprises applying a first conductive layer on a first surface of a non-conductive layer and applying a second conductive layer on a second surface of the non-conductive layer. In some embodiments, the first conductive layer is pattern etched and the second conductive layer is pattern etched. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Several example embodiments are described with reference to the drawings, wherein like components are provided with like reference numerals. The example embodiments are intended to illustrate, but not to limit, the invention. The drawings include the following figures: 
         FIG. 1  illustrates a perspective top view of various layers included in a printed circuit board prior to stacking and lamination according to some embodiments. 
         FIG. 2  illustrates an exemplary PCB stack-up  24  according to some embodiments. 
         FIG. 3  illustrates a cut out side view of a portion of the PCB-stack-up shown in  FIG. 2  as a lamination step is performed. 
         FIG. 4  illustrates a cut out side view of the PCB stack-up of  FIG. 3  after lamination. 
         FIGS. 5-14  illustrate various steps in the process used to manufacture a printed circuit board according to some embodiments. 
         FIGS. 15-24  illustrate various steps in the process used to manufacture a printed circuit board according to other embodiments. 
         FIG. 25  illustrates an exemplary PCB set form according to an embodiment. 
         FIG. 26  illustrates a perspective side view of the PCB set form  30  of  FIG. 25 . 
     
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
     Embodiments of the present application are directed to a printed circuit board. Those of ordinary skill in the art will realize that the following detailed description of the printed circuit board is illustrative only and is not intended to be in any way limiting. Other embodiments of the printed circuit board will readily suggest themselves to such skilled persons having the benefit of this disclosure. 
     Reference will now be made in detail to implementations of the printed circuit board as illustrated in the accompanying drawings. The same reference indicators will be used throughout the drawings and the following detailed description to refer to the same or like parts. In the interest of clarity, not all of the routine features of the implementations described herein are shown and described. It will, of course, be appreciated that in the development of any such actual implementation, numerous implementation-specific decisions must be made in order to achieve the developer&#39;s specific goals, such as compliance with application and business related constraints, and that these specific goals will vary from one implementation to another and from one developer to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking of engineering for those of ordinary skill in the art having the benefit of this disclosure. 
       FIG. 1  illustrates a perspective top view of various layers included in a printed circuit board prior to stacking and lamination according to some embodiments. An inner core  2  includes multiple layers (not shown). In some embodiments, the inner core  2  includes a non-conductive layer, such as prepreg or a base material, and a conductive layer on each surface of the non-conductive layer. It is understood that alternative inner core structures can be use which include a conductive layer on only one surface of the non-conductive layer. The conductive layers are patterned and etched to form conductive interconnects. Select portions of the conductive interconnects, referred to as inner core circuitry, are to be part of semi-flex PCBs. Each select portion is coated by plating resist  4 . 
     The dummy core  6  protects the select inner core circuitry covered by the applied plating resist. In some embodiments, the dummy core  6  is a two-layer structure. A first layer is a non-conductive layer, such as a base material. The second layer is a conductive layer, such as a copper foil. The dummy core  6  is shaped similar to an inverted stencil where the stencil pattern is formed of the dummy core material and the area surrounding the pattern is free of material. The pattern of the dummy core  6  includes overlay portions  8  that have substantially the same shape and size as the areas of applied plating resist  4 . The pattern of the dummy core  6  also includes interconnect portions  10  that connect the overlay portions  8  and an outer perimeter portion  12 . The interconnect portions  10  and the outer perimeter portion  12  of the dummy core pattern provide a stable framework for accurately placing the overlay portions  8  relative to the plating resist  4 . 
     A layer  14  is a non-conductive, insulating layer, such as prepreg. A layer  16  is a conductive layer, such as copper foil or laminate, where a laminate is similar in structure to the inner core  2  and includes a non-conductive layer such as base material and a conductive layer on one or both sides of non-conductive layer. In some embodiments, the layer  16  is representative of a multilayer buildup that can include many interspersed conductive and non-conductive layers. 
     A PCB stack-up is formed by stacking various combinations of the layers, or similar to the layers, shown in  FIG. 1 .  FIG. 2  illustrates an exemplary PCB stack-up  24  according to some embodiments. The stack-up  24  includes the inner core  2 , the dummy core pattern  6 , the non-conductive layer  14 , the conductive layer  16 , a dummy core pattern  18 , a non-conductive layer  20  and a conductive layer  22 . The dummy core pattern  18  can be patterned the same as the dummy core pattern  6  or differently depending on the inner core circuitry and plating resist patterns applied on a back side (not shown) of the inner core  2 . The non-conductive layer  20  can be similar to the non-conductive layer  14 . The conductive layer  22  can have the same or different patterned interconnects as the conductive layer  16 . The conductive layer  16  can represent a single layer or a multilayer buildup, and the conductive layer  22  can represent a single layer or multilayer buildup independently configured than the conductive layer  16 . 
     A laminated stack is formed by laminating the PCB stack-up shown in  FIG. 2 . Any conventional lamination technique can be used.  FIG. 3  illustrates a cut out side view of a portion of the PCB-stack-up shown in  FIG. 2  as a lamination step is performed. The portion of the PCB stack-up shown in  FIG. 3  coincides with an overly portion  8  of the dummy core pattern  6  and a plating resist portion  4  applied over inner core circuitry of the inner core  2 . An overlay portion  8 ′ of the dummy core pattern  18  of  FIG. 2  and a plating resist portion  4 ′ applied over backside inner core circuitry of the inner core  2  is also shown. With the dummy core positioned on the plating resist, the dummy core touches firmly with the plating resist under lamination pressure. A total thickness of the dummy core and plating resist is thicker than an adjacent area such that prepreg resin flows into the adjacent area under lower pressure. Prepreg resin flow into the inner core circuitry is restricted by the dummy core and plating resist as well as the higher pressure. The plating resist and the dummy core provide structural support during the lamination step so as to provide protection to the inner core circuitry.  FIG. 4  illustrates a cut out side view of the PCB stack-up of  FIG. 3  after lamination. 
       FIGS. 5-14  illustrate various steps in the process used to manufacture a printed circuit board according to some embodiments. The printed circuit board manufactured using the various steps shown in  FIGS. 5-14  is similar to and shares features of the printed circuit boards and constituent layers shown in  FIGS. 1-4 . Each of the  FIGS. 5-14  illustrate a cut out side view of the printed circuit board according to the various process steps. In  FIG. 5 , an exemplary inner core structure is shown. The inner core structure is a metal clad base material including a non-conductive base material layer  102  and conductive layers  104 ,  106  formed on both opposing surfaces. It is understood that an alternative inner core structure can be used which includes a conductive layer on only one surface of the non-conductive layer. 
     In  FIG. 6 , the conductive layers  104  and  106  are selectively pattern etched to form inner core circuitry  108  and  110 , respectively. Alternatively, the conductive layers  104 ,  106  are already pattern etched during fabrication of the inner core structure in  FIG. 5 . It is understood that  FIG. 5-14  only show a portion of the printed circuit board and in particular only show a portion of the inner core structure. Additional interconnects and circuitry may be formed on portions of the inner core structure not shown in  FIGS. 5-14 , those portions to be included as part of a rigid PCB portion of the printed circuit board. 
     In  FIG. 7 , plating resist  112 ,  114 , such as liquid photoimageable plating resist, is applied on the inner core circuitry  108  and  110 , respectively. The resulting structure forms an inner core assembly. It is understood that other types of plating resist can be used that have a low adhesion to a conductive layer, such as copper, of a dummy core as described in detail below. In some embodiments, a portion of the plating resist  112 ,  114  may extend beyond the outer edges of the inner core circuitry  108 ,  110  so as to encapsulate the inner core circuitry  108 ,  110 . For example, the plating resist  112  may extend more laterally than shown in  FIG. 7  so as to encapsulate inner core circuitry  108  similar to the manner that inner core circuitry  110  is shown in  FIG. 7  to be encapsulated. 
     In  FIG. 8 , additional core structures and dummy core structures are fabricated, and the core structures, the inner core assembly and the dummy core structures are stacked with intervening non-conductive layers. The additional core structures are similar to the inner core structure of  FIG. 5  with the conductive layers pattern etched accordingly. However, the conductive layers of the additional core structures are formed such that the resulting interconnects will be positioned in a rigid PCB portion of the resulting printed circuit board. In the exemplary configuration shown in  FIG. 8 , two additional core structures are included. A first core structure  122  includes a non-conductive layer  124  and conductive layers  126  and  128 . The conductive layers  126  and  128  are selectively pattern etched. As shown in  FIG. 8 , the portions of the conductive layers  126  and  128  aligned with the inner core circuitry  108  are removed. However, removal of the conductive layers  126  and  128  is optional and in other embodiments these portions of the conductive layers  126  and  128  may remain. A second core structure  130  includes a non-conductive layer  132  and conductive layers  134  and  136 . The conductive layers  134  and  136  are selectively pattern etched. As shown in  FIG. 8 , the portions of the conductive layers  134  and  136  aligned with the inner core circuitry  110  are removed. However, removal of the conductive layers  134  and  136  is optional and in other embodiments these portions of the conductive layers  134  and  136  may remain. 
     A dummy core  120  is positioned on the plating resist  112  of the inner core assembly and a dummy core  121  is positioned on the plating resist  114  of the inner core assembly. The dummy core  120  includes a conductive layer  118  and a non-conductive layer  116 , the dummy core  120  is oriented such that the conductive layer  118  is positioned against the plating resist  112 . The type of plating resist used has a low adhesion to the material type of the conductive layer  118 . This low adhesion enables removal of the dummy core  120  from the inner core assembly during a subsequent decap step shown and described in relation to  FIG. 13 . The dummy core  121  includes a conductive layer  119  and a non-conductive layer  117 , the dummy core  121  is oriented such that the conductive layer  119  is positioned against the plating resist  114 . The type of plating resist used has a low adhesion to the material type of the conductive layer  119 . This low adhesion enables removal of the dummy core  121  from the inner core assembly during the subsequent decap step. 
     An intervening non-conductive layer  140  is positioned between the dummy core  120  and the core structure  122 , and an intervening non-conductive layer  142  is positioned between the dummy core  121  and the core structure  130 . In the exemplary configuration shown in  FIG. 8 , additional conductive layer  146  and intervening non-conductive layer  138  are added to the top of the stack and additional conductive layer  148  and intervening non-conductive layer  144  are added to the bottom of the stack, where the terms top and bottom are used only in relation to the orientation shown in  FIG. 8 . A single lamination step results in the laminated stack shown in  FIG. 8 . 
     In  FIG. 9 , selective holes are drilled through the laminated stack of  FIG. 8  to form vias, such as via  150 . Vias are formed in those portions of the printed circuit board that will be rigid PCB portions. 
     In  FIG. 10 , a desmear process is performed to remove residue, such as residual particles from the drilling of via  150 . Next, an electroless plating process is performed to form plating  152  on the side walls of the via  150 . In some embodiments, copper is used as the plating material. It is understood that other plating materials can be used. The plating  152  forms an interconnect with various conductive layers in the stack. 
     In  FIG. 11 , an outer conducting layer etching process is performed. The additional conductive layers  146  and  148  on the top and bottom, respectively, of the laminated stack are pattern etched to form patterned conductive layers  146 ′ and  148 ′. In particular, the portions of the conductive layers  146  and  148  aligned with the dummy cores  120  and  121 , respectively, are removed. 
     In  FIG. 12 , a depth controlled rout step is performed. In some embodiments, a routing tool having a rout bit is used form a rout into the laminated stack to a depth of the conductive layer on the respective dummy core. As shown in  FIG. 12 , a rout  154  is made from the non-conductive layer  138  to the conductive layer  118  of the dummy core  120 , and a rout  155  is made from the non-conductive layer  144  to the conductive layer  119  of the dummy core  121 .  FIG. 12  shows a two dimensional view of the rout  154  and  155 . In three-dimensions, the routs  154  and  155  are formed at an outer perimeter of the dummy cores  120  and  121 , respectively. A lateral rout is also performed such that the conductive layers  118  and  119  are free from surrounding prepreg material 
     In  FIG. 13 , a plug  156  is removed and a plug  157  is removed, thereby exposing the plating resist  112  and  114 , respectively. The plug  156  is the area within the rout  154  perimeter and between the non-conducive layer  138  and the conductive layer  118  of the dummy core  120 . The plug  157  is the area within the rout  155  perimeter and between the non-conductive layer  144  and the conductive layer  119  of the dummy core  121 . Removal of the plugs  156  and  157  is referred to as a decap process. The low adhesion between the conductive layer  118  and the plating resist  112 , and between the conductive layer  119  and the plating resist  114  enables the plugs to simply be pulled apart from the plating resist. 
     In  FIG. 14 , a plating resist stripping process is performed. During the plating resist stripping process, the plating resist  112  and the plating resist  114  are removed. In some embodiments, trace amounts of the plating resist remain at the boundaries, such as the plating resist  112 ′ and  114 ′ shown in  FIG. 14 . During the lamination process, such as in  FIG. 8 , prepreg resin binds to plating resist such that it is not easy to remove plating resist completely without long stripping time. However, long stripping time could damage proximal non-conductive layers. Therefore a shorter stripping time is used which results in trace amount of plating resist left behind. The remaining plating resist does not affect finished printed circuit board functionality. 
     It is understood that the various structural configurations and the position of the inner core assembly shown in the embodiments of  FIGS. 5-14  can be interchanged according to a specific application and application requirement. 
       FIGS. 2-14  show an exemplary configuration where both sides of the inner core circuitry are protected using plating resist and dummy core, and subsequently exposed. This is referred to as a double-sided configuration In other embodiments, only one side of the inner core circuitry is protected using plating resist and dummy core, and subsequently exposed. This is referred to as a single-sided configuration. In such a single-sided application, plating resist and a dummy core are only applied over the one side of the inner core circuitry to be exposed, and the corresponding single plug is removed.  FIGS. 15-24  illustrate various steps in the process used to manufacture a printed circuit board according to other embodiments. The printed circuit board manufactured using the various steps shown in  FIGS. 15-24  is similar to and shares features of the printed circuit board and constituent layers shown in  FIGS. 5-14  except that the  FIGS. 15-24  are directed to a single-sided process. Each of the  FIGS. 15-24  illustrate a cut out side view of the printed circuit board according to the various process steps. 
     In  FIG. 15 , an exemplary inner core structure is shown. The inner core structure is a metal clad base material including a non-conductive base material layer  202  and conductive layers  204  and  206  formed on both opposing surfaces. It is understood that an alternative inner core structure can be used which includes a conductive layer on only one surface of the non-conductive layer. 
     In  FIG. 16 , the conductive layers  204  and  206  are selectively pattern etched to form inner core circuitry  208  and  210 , respectively. Alternatively, the conductive layers  204 ,  206  are already pattern etched during fabrication of the inner core structure in  FIG. 15 . It is understood that  FIG. 15-24  only show a portion of the printed circuit board and in particular only show a portion of the inner core structure. Additional interconnects and circuitry may be formed on portions of the inner core structure not shown in  FIGS. 15-24 , those portions to be included as part of a rigid PCB portion of the printed circuit board. 
     In  FIG. 17 , plating resist  212 , such as liquid photoimageable plating resist, is applied on the inner core circuitry  208 . In the single-sided embodiment, only the one side of the inner core circuitry, the inner core circuitry  208  is to be subsequently exposed, whereas the other side of the inner core circuitry, the inner core circuitry  210  is to remain embedded in the subsequent laminated stack. The resulting structure forms an inner core assembly. It is understood that other types of plating resist can be used that have a low adhesion to a conductive layer, such as copper, of a dummy core as described in detail below. In some embodiments, a portion of the plating resist  212  may extend beyond the outer edges of the inner core circuitry  208  so as to encapsulate the inner core circuitry  208 . 
     In  FIG. 18 , additional core structures and a dummy core structure are fabricated, and the core structures, the inner core assembly and the dummy core structure are stacked with intervening non-conductive layers. The additional core structures are similar to the inner core structure of  FIG. 15  with the conductive layers pattern etched accordingly. However, the conductive layers of the additional core structures positioned are formed such that the resulting interconnects will be positioned in a rigid PCB portion of the resulting printed circuit board. In those additional core structures that include portions of a subsequent plug to be removed during a decap process, the corresponding conductive layer portions can be etched away or left intact. In the exemplary configuration shown in  FIG. 18 , two additional core structures are included. A first core structure  222  includes a non-conductive layer  224  and conductive layers  226  and  228 . The conductive layers  226  and  228  are selectively pattern etched. As shown in  FIG. 18 , the portions of the conductive layers  226  and  228  aligned with the inner core circuitry  208  are removed. Alternatively, the portions of the conductive layers  226  and  228  aligned with the inner core circuitry  208  can be left intact. A second core structure  230  includes a non-conductive layer  232  and conductive layers  234  and  236 . The conductive layers  234  and  236  are selectively pattern etched. As shown in  FIG. 18 , the portions of the conductive layers  234  and  236  aligned with the inner core circuitry  210  may include patterned interconnects. 
     A dummy core  220  is positioned on the plating resist  212  of the inner core assembly. The dummy core  220  includes a conductive layer  218  and a non-conductive layer  216 . The dummy core  220  is oriented such that the conductive layer  218  is positioned against the plating resist  212 . The type of plating resist used has a low adhesion to the material type of the conductive layer  218 . This low adhesion enables removal of the dummy core from the inner core assembly during a subsequent decap step shown and described in relation to  FIG. 23 . 
     An intervening non-conductive layer  240  is positioned between the dummy core  220  and the core structure  222 , and an intervening non-conductive layer  242  is positioned between the inner core circuitry  210  and the core structure  230 . In the exemplary configuration shown in  FIG. 18 , additional conductive layer  246  and intervening non-conductive layer  238  are added to the top of the stack and additional conductive layer  248  and intervening non-conductive layer  244  are added to the bottom of the stack, where the terms top and bottom are used only in relation to the orientation shown in  FIG. 18 . A single lamination step results in the laminated stack shown in  FIG. 18 . 
     In  FIG. 19 , selective holes are drilled through the laminated stack of  FIG. 18  to form vias, such as via  250 . Vias are formed in those portions of the printed circuit board that will be rigid PCB portions. 
     In  FIG. 20 , a desmear process is performed to remove residue, such as residual particles from the drilling of via  250 . Next, an electroless plating process is performed to form plating  252  on the side walls of the via  250 . In some embodiments, copper is used as the plating material. It is understood that other plating materials can be used. The plating  252  forms an interconnect with various conductive layers in the stack. 
     In  FIG. 21 , an outer conducting layer etching process is performed. The additional conductive layers  246  and  248  on the top and bottom, respectively, of the laminated stack are pattern etched to form patterned conductive layers  246 ′ and  248 ′. In particular, the portion of the conductive layers  246  aligned with the dummy core  220  is removed. 
     In  FIG. 22 , a depth controlled rout step is performed. As shown in  FIG. 22 , a rout  254  is made from the non-conductive layer  238  to the conductive layer  218  of the dummy core  220 . 
       FIG. 22  shows a two dimensional view of the rout  154 . In three-dimensions, the rout  154  is formed at an outer perimeter of the dummy core  220 . 
     In  FIG. 23 , a plug  256  is removed, thereby exposing the plating resist  212 . The plug  256  is the area within the rout  254  perimeter and between the non-conducive layer  238  and the conductive layer  218  of the dummy core  220 . The low adhesion between the conductive layer  218  and the plating resist  212  enables the plug to simply be pulled apart from the plating resist. 
     In  FIG. 24 , a plating resist stripping process is performed. During the plating resist stripping process, the plating resist  212  is removed. In some embodiments, trace amounts of the plating resist remain at the boundaries, such as the plating resist  212 ′ shown in  FIG. 24 . 
     It is understood that the various structural configurations and the position of the inner core assembly shown in the embodiments of  FIGS. 15-24  can be interchanged according to a specific application and application requirement. 
     In some manufacturing processes, multiple PCBs are manufactured as discrete portions of a single substrate, which are separated into individual PCBs at the end of the manufacturing process. Such a single substrate configuration is referred to as a PCB set form.  FIG. 25  illustrates an exemplary PCB set form according to an embodiment. The exemplary PCB set form  30  includes four PCBs  32 ,  34 ,  36 ,  38 . It is understood that PCB set forms can include more or less than the exemplary four PCBs shown in  FIG. 25 . The PCBs  32 ,  34 ,  36 ,  38  are connected physically but not electrically. Each PCB  32 ,  34 ,  36 ,  38  includes exposed inner core circuitry  48 ,  50 ,  52 ,  54 , respectively. In some embodiments, an additional routing step is applied to an outer perimeter portion of a PCB set form. The additional routing step can be performed at any point in the printed circuit board manufacturing process after the lamination step is performed. For example, in the printed circuit board manufacturing process shown in  FIGS. 5-14 , the additional routing step can be performed at any point after the lamination step shown in  FIG. 8 . The additional routing step removes a perimeter portion of the laminated PCB stack up including the outer perimeter portion of the dummy core pattern, such as the outer perimeter portion  12  of  FIG. 1 . A resulting perimeter area surrounding the PCBs  32 ,  34 ,  36 ,  38  in the PCB set form  30  is shown in  FIG. 25  as breakaway area  46 . 
     The PCBs  32 ,  34 ,  36 ,  38  are ready for surface components to be mounted on select areas, such as through a surface mount technology (SMT) process. After the components are mounted, the PCBs are separated for subsequent installation into other devices. Separating the PCBs can be performed using any conventional process including, but not limited to, cutting the PCB set form  30  along etched lines  40 ,  42 ,  44 . Cutting along the perimeter etch lines  44  separates the breakaway area  46  from the PCBs  32 ,  34 ,  36 ,  38 , and cutting along the etch lines  40 ,  42  separates the PCBs  32 ,  34 ,  36 ,  38  from each other. 
       FIG. 26  illustrates a perspective side view of the PCB set form  30  of  FIG. 25 . The breakaway area  46  includes a dummy core portion  60 , which is a remnant of a dummy core pattern used to form the exposed inner core circuitry  50  in the PCB  34 . As exemplified in  FIG. 1 , a dummy core pattern can include an interconnect portion, such as the interconnect portion  10  of the dummy core pattern  6  in  FIG. 1 , a portion of which coincides with the breakaway area of a PCB set form, such as the breakaway area  46  in  FIG. 26 . As such, although the outer perimeter portion of the dummy core pattern, such as the outer perimeter portion  12  in  FIG. 1 , as well as the overlay portions of the dummy core pattern that are applied over the plating resist and corresponding inner core circuitry, such as the overlay portions  8  in  FIG. 1 , are removed during the PCB manufacturing process, the interconnect portions that connect to the outer perimeter portion of the dummy core pattern remain. 
     In some embodiments, the semi-flex PCB portions can be formed as connector sections between rigid PCB portions, such as the configuration shown in  FIG. 25 . The semi-flex PCB portion is flexible thereby enabling two adjoining rigid PCB portions to rotate, or pivot, relative to each other In other embodiments, the portion of the printed circuit board corresponding to the exposed inner core circuitry is rigid, referred to as a rigid exposed circuitry PCB portion. The rigid exposed circuitry PCB portion can be formed as the outer perimeter of a rigid PCB portion, such as the formation of recessed gold fingers used for subsequent interconnection with other devices. Gold fingers are elongated conductors. The recessed gold fingers can be formed using either the single sided configuration or the double sided configuration. 
     An advantage of using the plating resist and dummy core in the manufacturing process is that relatively early in the manufacturing process a final circuit surface, for example the inner core circuitry, can be prepared and protected during subsequent process steps. The final circuit surface can be re-exposed later in the process without having been contaminated. 
     The present application has been described in terms of specific embodiments incorporating details to facilitate the understanding of the principles of construction and operation of the printed circuit board. Many of the components shown and described in the various figures can be interchanged to achieve the results necessary, and this description should be read to encompass such interchange as well. As such, references herein to specific embodiments and details thereof are not intended to limit the scope of the claims appended hereto. It will be apparent to those skilled in the art that modifications can be made to the embodiments chosen for illustration without departing from the spirit and scope of the application.