Patent Publication Number: US-2023146321-A1

Title: Semiconductor device

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This application is a continuation of U.S. Application No. 17/123,078 filed on Dec. 15, 2020, which is a U.S. continuation application of PCT International Patent Application Number PCT/JP2019/046029 filed on Nov. 25, 2019, claiming the benefit of priority of Japanese Patent Application Number 2018-234349 filed on Dec. 14, 2018, the entire contents of which are hereby incorporated by reference. 
    
    
     BACKGROUND 
     1. Technical Field 
     The present disclosure relates to semiconductor devices. 
     2. Description of the Related Art 
     Semiconductor light-emitting elements such as light-emitting diodes (LEDs) are used as light sources for various devices. For example, the LEDs are used as vehicle-mounted light sources for vehicle-mounted lighting devices such as daytime running lights (DRLs) and headlamps (HLs). In particular, the market is growing for vehicle-mounted light sources including high-power LEDs with at least 1-watt light output, leading to a rapid increase in replacement of halogen lamps and high-intensity discharge (HID) lamps with LEDs. 
     For the vehicle-mounted light sources, there are increasing demands for saving space and design improvement, and thus the LEDs are becoming more compact and integrated with larger electric current. Consequently, it is important to dissipate heat generated at the LEDs to secure the reliability required for the LEDs. 
     As a technique for bonding a semiconductor chip such as an LED chip and a mounting substrate together to make the semiconductor chip more compact and integrated with larger electric current, the flip-chip bonding for bonding the semiconductor chip face down to the mounting substrate is known. In this technique, the semiconductor chip is flipped (turned upside down) so that an electrode of the mounting substrate and an electrode of the semiconductor chip are directly bonded together using a metal bump, meaning that this technique is less dependent on the wire diameter or the wire routing than in the case where the semiconductor chip is bonded to the mounting substrate by a face-up method for wiring the semiconductor chip with its electrode forming surface directed upward; thus, the flip-chip bonding is suitable for highly integrated semiconductor chips with large electric current and therefore is used for vehicle-mounted light sources as a mounting method for high-output applications. 
     A conventional semiconductor device of this type is disclosed in Japanese Unexamined Patent Application Publication No. 2011-009429. Japanese Unexamined Patent Application Publication No. 2011-009429 discloses a technique for densely arranging a plurality of metal bumps between a semiconductor element and a mounting substrate at the time of bonding the semiconductor element and the mounting substrate together for the purpose of improving heat dissipation properties. 
     SUMMARY 
     However, in the semiconductor device disclosed in Japanese Unexamined Patent Application Publication No. 2011-009429, a mounting load that is placed when the semiconductor element is mounted on the mounting substrate via the discrete metal bumps is locally concentrated on the contact surface between each of the electrodes of the semiconductor element and the mounting substrate and the metal bumps, resulting in damage to the electrodes of the semiconductor element and the mounting substrate. This causes the problem of mounting damage such as electrode failures, leading to reduced long-term reliability. 
     The present disclosure aims to provide a semiconductor device exceptionally reliable in the long run by reducing mounting damage. 
     A semiconductor device according to one aspect of the present disclosure includes: a first electrode provided on a semiconductor multilayer structure; a second electrode provided on a substrate; and a bonding metal layer that bonds the first electrode and the second electrode together. The bonding metal layer includes a gap inside. The first electrode includes a p-side electrode and an n-side electrode. A proportion of an area taken up by the gap in a plan view is lower in a region close to a p-n electrode opposed portion than in a region away from the p-n electrode opposed portion. The p-n electrode opposed portion is a portion across which the p-side electrode and the n-side electrode are opposed to each other. 
     According to the present disclosure, the mounting damage can be reduced, and thus it is possible to provide a semiconductor device exceptionally reliable in the long run. 
    
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
       The figures depict one or more implementations in accordance with the present teaching, by way of examples only, not by way of limitations. In the figures, like reference numerals refer to the same or similar elements. 
         FIG.  1 A  is a cross-sectional view of a semiconductor device according to Embodiment 1 taken along line IA-IA in  FIG.  2 B ; 
         FIG.  1 B  is a cross-sectional view of a semiconductor device according to Embodiment 1 taken along line IB-IB in  FIG.  2 B ; 
         FIG.  2 A  is a cross-sectional view of a semiconductor device according to Embodiment 1 in a T cross section obtained when cut along dashed line T in  FIG.  1 B ; 
         FIG.  2 B  is a cross-sectional view of a semiconductor device according to Embodiment 1 in an M cross section obtained when cut along dashed line M in  FIG.  1 B ; 
         FIG.  2 C  is a cross-sectional view of a semiconductor device according to Embodiment 1 in a B cross section obtained when cut along dashed line B in  FIG.  1 B ; 
         FIG.  3 A  is a diagram illustrating the process of preparing a substrate in a first step in a method for manufacturing a semiconductor device according to Embodiment 1; 
         FIG.  3 B  is a diagram illustrating the process of forming a multilayer semiconductor structure in a first step in a method for manufacturing a semiconductor device according to Embodiment 1; 
         FIG.  4 A  is a diagram illustrating the process of etching a multilayer semiconductor structure in a second step in a method for manufacturing a semiconductor device according to Embodiment 1; 
         FIG.  4 B  is a diagram illustrating the process of forming an insulating film in a second step in a method for manufacturing a semiconductor device according to Embodiment 1; 
         FIG.  4 C  is a diagram illustrating the process of forming an ohmic contact layer and a barrier electrode of a first n-side electrode in a second step in a method for manufacturing a semiconductor device according to Embodiment 1; 
         FIG.  4 D  is a diagram illustrating the process of forming a reflective electrode of a first p-side electrode in a second step in a method for manufacturing a semiconductor device according to Embodiment 1; 
         FIG.  4 E  is a diagram illustrating the process of forming a barrier electrode of a first p-side electrode in a second step in a method for manufacturing a semiconductor device according to Embodiment 1; 
         FIG.  4 F  is a diagram illustrating the process of forming a seed film in a second step in a method for manufacturing a semiconductor device according to Embodiment 1; 
         FIG.  4 G  is a diagram illustrating the process of forming a resist in a second step in a method for manufacturing a semiconductor device according to Embodiment 1; 
         FIG.  4 H  is a diagram illustrating the process of forming cover electrodes of a first p-side electrode and a first n-side electrode in a second step in a method for manufacturing a semiconductor device according to Embodiment 1; 
         FIG.  4 I  is a diagram illustrating the process of removing a resist in a second step in a method for manufacturing a semiconductor device according to Embodiment 1; 
         FIG.  5 A  is a diagram illustrating the process of forming a resist having an opening in a third step in a method for manufacturing a semiconductor device according to Embodiment 1; 
         FIG.  5 B  is a diagram illustrating the process of forming a gold-plated film in a third step in a method for manufacturing a semiconductor device according to Embodiment 1; 
         FIG.  5 C  is a diagram illustrating the process of removing a resist in a third step in a method for manufacturing a semiconductor device according to Embodiment 1; 
         FIG.  5 D  is a diagram illustrating the process of pn isolation of an electrode by removing a portion of a seed film in a third step in a method for manufacturing a semiconductor device according to Embodiment 1; 
         FIG.  5 E  is a diagram illustrating the process of performing heat treatment in a third step in a method for manufacturing a semiconductor device according to Embodiment 1; 
         FIG.  6 A  is a diagram illustrating the process of placing a semiconductor element on a mounting substrate in a fourth step in a method for manufacturing a semiconductor device according to Embodiment 1; 
         FIG.  6 B  is a diagram illustrating the process of mounting a semiconductor element on a mounting substrate and ultrasonically bonding the semiconductor element and the mounting substrate together in a fourth step in a method for manufacturing a semiconductor device according to Embodiment 1; 
         FIG.  7 A  is an enlarged view of region VIIA in  FIG.  5 D ; 
         FIG.  7 B  is an enlarged view of region VIIB in  FIG.  5 E ; 
         FIG.  7 C  illustrates crystal grains resulting from further coarsening of crystal grains in  FIG.  7 B ; 
         FIG.  8    illustrates a method for measuring a crystal grain size; 
         FIG.  9    illustrates the relationship between the average crystal grain size of a gold-plated film and the hardness of a single-layered gold-plated film; 
         FIG.  10    is a timing chart for a bonding process according to Embodiment 1 when mounting a semiconductor element on a mounting substrate; 
         FIG.  11 A  is a cross-sectional view schematically illustrating metal bumps and a second electrode of a mounting substrate before a bonding process for a semiconductor element and the mounting substrate; 
         FIG.  11 B  is a cross-sectional view schematically illustrating metal bumps and a second electrode of a mounting substrate at the start of a bonding process for a semiconductor element and the mounting substrate; 
         FIG.  11 C  is a cross-sectional view schematically illustrating metal bumps and a second electrode of a mounting substrate that are bonded together at the transition from STEP 1 to STEP 2 in  FIG.  10    (approximately 100 milliseconds later after the start of the process); 
         FIG.  11 D  is a cross-sectional view schematically illustrating metal bumps and a second electrode of a mounting substrate that are bonded together in the middle of STEP 2 in  FIG.  10    (approximately 300 milliseconds later after the start of the process and approximately 200 milliseconds later after the start of ultrasonic vibration); 
         FIG.  11 E  is a cross-sectional view schematically illustrating metal bumps and a second electrode of a mounting substrate that are bonded together at the end of STEP 2 in  FIG.  10    (approximately 400 milliseconds later after the start of the process and approximately 300 milliseconds later after the start of ultrasonic vibration); 
         FIG.  12    is a cross-sectional view illustrating a method for manufacturing a conventional semiconductor device disclosed in Japanese Unexamined Patent Application Publication No. 2011-009429; 
         FIG.  13    is a diagram illustrating the configurations of a semiconductor device according to Embodiment 1 before and after mounting; 
         FIG.  14 A  is a diagram illustrating a gap pattern of a bonding metal layer in a semiconductor device according to Variation 1 of Embodiment 1; 
         FIG.  14 B  is a diagram illustrating a gap pattern of a bonding metal layer in a semiconductor device according to Variation 2 of Embodiment 1; 
         FIG.  14 C  is a diagram illustrating a gap pattern of a bonding metal layer in a semiconductor device according to Variation 3 of Embodiment 1; 
         FIG.  14 D  is a diagram illustrating a gap pattern of a bonding metal layer in a semiconductor device according to Variation 4 of Embodiment 1; 
         FIG.  14 E  is a diagram illustrating a gap pattern of a bonding metal layer in a semiconductor device according to Variation 5 of Embodiment 1; 
         FIG.  14 F  is a diagram illustrating a gap pattern of a bonding metal layer in a semiconductor device according to Variation 6 of Embodiment 1; 
         FIG.  14 G  is a diagram illustrating a gap pattern of a bonding metal layer in a semiconductor device according to Variation 7 of Embodiment 1; 
         FIG.  14 H  is a diagram illustrating a gap pattern of a bonding metal layer in a semiconductor device according to Variation 8 of Embodiment 1; 
         FIG.  14 I  is a diagram illustrating a gap pattern of a bonding metal layer in a semiconductor device according to Variation 9 of Embodiment 1; 
         FIG.  14 J  is a diagram illustrating a gap pattern of a bonding metal layer in a semiconductor device according to Variation 10 of Embodiment 1; 
         FIG.  14 K  is a diagram illustrating a gap pattern of a bonding metal layer in a semiconductor device according to Variation 11 of Embodiment 1; 
         FIG.  14 L  is a diagram illustrating a gap pattern of a bonding metal layer in a semiconductor device according to Variation 12 of Embodiment 1; 
         FIG.  14 M  is a diagram illustrating a gap pattern of a bonding metal layer in a semiconductor device according to Variation 13 of Embodiment 1; 
         FIG.  14 N  is a diagram illustrating a gap pattern of a bonding metal layer in a semiconductor device according to Variation 14 of Embodiment 1; 
         FIG.  140    is a diagram illustrating a gap pattern of a bonding metal layer in a semiconductor device according to Variation 15 of Embodiment 1; 
         FIG.  15    is a cross-sectional view illustrating the configurations of a semiconductor device according to Embodiment 2 before and after mounting; 
         FIG.  16    is an enlarged view of the M cross section in (b) in  FIG.  15   ; 
         FIG.  17    is a diagram illustrating a gap pattern of a bonding metal layer in a semiconductor device according to Variation 1 of Embodiment 2; 
         FIG.  18    is a diagram illustrating a gap pattern of a bonding metal layer in a semiconductor device according to Variation 2 of Embodiment 2; 
         FIG.  19    is a cross-sectional view illustrating the configurations of a semiconductor device according to Variation 3 of Embodiment 2 before and after mounting; 
         FIG.  20    is a cross-sectional view illustrating the configurations of a semiconductor device according to Embodiment 3 before and after mounting; 
         FIG.  21    is a cross-sectional view illustrating the configurations of a semiconductor device according to Variation 1 of Embodiment 3 after mounting; 
         FIG.  22    is a cross-sectional view illustrating the configurations of a semiconductor device according to Variation 2 of Embodiment 3 after mounting; and 
         FIG.  23    is a cross-sectional view illustrating the configurations of a semiconductor device according to Variation 3 of Embodiment 3 after mounting. 
     
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS EMBODIMENTS 
     Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. Note that each of the embodiments described below shows a specific example of the present disclosure. Thus, the numerical values, shapes, materials, structural elements, and the arrangement and connection of the structural elements, steps, the processing order of the steps etc., shown in the following embodiments are mere examples, and are not intended to limit the present disclosure. 
     Note that the figures are schematic diagrams and are not necessarily precise illustrations. Therefore, scale reduction, etc., in the figures are not necessarily the same. In the figures, substantially identical elements are assigned the same reference signs, and overlapping description will be omitted or simplified. 
     EMBODIMENT 1 
     Semiconductor Device 
     First, the configuration of semiconductor device  1  according to Embodiment 1 will be described with reference to  FIG.  1 A ,  FIG.  1 B , and  FIG.  2 A  to  FIG.  2 C .  FIG.  1 A  and  FIG.  1 B  are cross-sectional views of semiconductor device  1  according to Embodiment 1.  FIG.  2 A  is a cross-sectional view of semiconductor device  1  in a T cross section obtained when cut along dashed line T in  FIG.  1 B .  FIG.  2 B  is a cross-sectional view of semiconductor device  1  in an M cross section obtained when cut along dashed line M in  FIG.  1 B .  FIG.  2 C  is a cross-sectional view of semiconductor device  1  in a B cross section obtained when cut along dashed line B in  FIG.  1 B . Note that  FIG.  1 A  is a cross-sectional view taken along line IA-IA in  FIG.  2 B  and  FIG.  1 B  is a cross-sectional view taken along line IB-IB in  FIG.  2 B . In  FIG.  2 A  to  FIG.  2 C , each of dashed lines T, M, B indicates a plane perpendicular to the thickness direction (height direction) of bonding metal layer  30 . Dashed line M indicates a plane passing through gap  33  and is located between dashed line T and dashed line B. 
     As illustrated in  FIG.  1 A  and  FIG.  1 B , semiconductor device  1  according to Embodiment 1 includes semiconductor element  10 , mounting substrate  20 , and bonding metal layer  30  for bonding semiconductor element  10  and mounting substrate  20  together. 
     Semiconductor element  10  is disposed on mounting substrate  20 . Specifically, semiconductor element  10  is bonded to mounting substrate  20  via bonding metal layer  30  and is thus mounted on mounting substrate  20 . In the present embodiment, semiconductor element  10  is a light-emitting diode (LED) chip. Thus, semiconductor device  1  is a semiconductor light-emitting device including the LED chip. 
     Semiconductor element  10  includes semiconductor multilayer structure  11  and first electrode E 1  provided on semiconductor multilayer structure  11 . Specifically, semiconductor element  10  includes, as first electrode E 1 , first p-side electrode  12  and first n-side electrode  13  formed on semiconductor multilayer structure  11 . Each of first p-side electrode  12  and first n-side electrode  13  is made up of at least two layers including a surface layer made of gold in contact with bonding metal layer  30 . 
     Note that in the present description, first p-side electrode  12  and first n-side electrode  13  may be collectively referred to as first electrode E 1  when there is no need to differentiate these electrodes. In other words, first electrode E 1  represents at least one of first p-side electrode  12  and first n-side electrode  13 . 
     Semiconductor multilayer structure  11  includes substrate  11   a , n-type semiconductor layer  11   b  (first conductivity-type semiconductor layer), active layer  11   c , and p-type semiconductor layer  11   d  (second conductivity-type semiconductor layer). N-type semiconductor layer  11   b , active layer  11   c , and p-type semiconductor layer  11   d  constitute a semiconductor layered body in contact with substrate  11   a  and are stacked in the stated order from substrate  11   a . Specifically, n-type semiconductor layer  11   b , active layer  11   c , and p-type semiconductor layer  11   d  are stacked on substrate  11   a  in the stated order in a direction away from substrate  11   a . 
     First p-side electrode  12  and first n-side electrode  13  are formed on semiconductor multilayer structure  11 . First p-side electrode  12  is formed on p-type semiconductor layer  11   d . First n-side electrode  13  is formed on n-type semiconductor layer  11   b . Specifically, first n-side electrode  13  is formed in an exposed region that is a portion of n-type semiconductor layer  11   b  exposed by removing a portion of each of p-type semiconductor layer  11   d  and active layer  11   c . 
     In the present embodiment, oxide film  14  is formed on semiconductor multilayer structure  11  as an insulating film. First p-side electrode  12  is formed on p-type semiconductor layer  11   d  exposed in an opening of oxide film  14 , and first n-side electrode  13  is formed on n-type semiconductor layer  11   b  exposed in an opening of oxide film  14 . 
     First p-side electrode  12  includes reflective electrode  12   a , barrier electrode  12   b , seed layer  12   c , and cover electrode  12   d  stacked sequentially from semiconductor multilayer structure  11 . Specifically, reflective electrode  12   a , barrier electrode  12   b , seed layer  12   c , and cover electrode  12   d  are stacked on semiconductor multilayer structure  11  in the stated order. In first p-side electrode  12 , reflective electrode  12   a , which is a metal film that reflects light from active layer  11   c  of semiconductor multilayer structure  11 , is disposed in contact with p-type semiconductor layer  11   d  (second conductivity-type semiconductor layer) of semiconductor multilayer structure  11 . 
     First n-side electrode  13  includes ohmic contact layer  13   a , barrier electrode  13   b , seed layer  13   c , and cover electrode  13   d  stacked sequentially from semiconductor multilayer structure  11 . 
     In first p-side electrode  12  and first n-side electrode  13 , cover electrodes  12   d ,  13   d  are surface layers made of gold in contact with bonding metal layer  30 . Specifically, cover electrodes  12   d ,  13   d  are gold-plated films formed using seed layers  12   c ,  13   c  as undercoat layers. 
     Mounting substrate  20  includes substrate  21  and second electrode E 2  provided on substrate  21 . Specifically, mounting substrate  20  includes, as second electrode E 2 , second p-side electrode  22  and second n-side electrode  23   formed on one surface of substrate  21 . Each of second p-side electrode  22  and second n-side electrode  23  is a lead-out electrode for passing an electric current to semiconductor element  10 . 
     Second p-side electrode  22  is bonded to first p-side electrode  12  of semiconductor element  10  via bonding metal layer  30 . The same applies to the n side; second n-side electrode  23  is bonded to first n-side electrode  13  of semiconductor element  10  via bonding metal layer  30 . 
     Note that in the present description, second p-side electrode  22  and second n-side electrode  23  may be collectively referred to as second electrode E 2  when there is no need to differentiate these electrodes. In other words, second electrode E 2  represents at least one of second p-side electrode  22  and second n-side electrode  23 . 
     Bonding metal layer  30  bonds semiconductor element  10  and mounting substrate  20  together. In other words, bonding metal layer  30  joins semiconductor element  10  and mounting substrate  20  together. Specifically, bonding metal layer  30  connects first electrode E 1  provided on semiconductor multilayer structure  11  and second electrode E 2  provided on substrate  21 . 
     In the present embodiment, bonding metal layer  30  includes first bonding metal layer  31  and second bonding metal layer  32 . First bonding metal layer  31  is located between first p-side electrode  12  of semiconductor element  10  and second p-side electrode  22  of mounting substrate  20  and bonds first p-side electrode  12  and second p-side electrode  22  together. Second bonding metal layer  32  is located between first n-side electrode  13  of semiconductor element  10  and second n-side electrode  23  of mounting substrate  20  and bonds first n-side electrode  13  and second n-side electrode  23  together. 
     First bonding metal layer  31  and second bonding metal layer  32  include the same material. In the present embodiment, each of first bonding metal layer  31  and second bonding metal layer  32  is formed of a gold-plated film. 
     As illustrated in  FIG.  1 A ,  FIG.  1 B , and  FIG.  2 A  to  FIG.  2 C , there is gap  33  inside bonding metal layer  30 . Gap  33  is present surrounded by bonding metal layer  30  along the perimeter. Specifically, gap  33  is present in bonding metal layer  30  in such a manner as to be embedded in bonding metal layer  30  without contacting first electrode E 1  or second electrode E 2 . In the present embodiment, gap  33  is present in first bonding metal layer  31 , does not contact first p-side electrode  12  or first n-side electrode  13 , and is located in the vicinity of a center portion of first bonding metal layer  31  in the thickness direction. Gap  33  is a hollow cavity in the present embodiment. Thus, gap  33  is a layer of air, meaning that air exists in gap  33 . 
     As illustrated in  FIG.  2 B , gap  33  extends linearly along the outer side of first electrode E 1  in a plan view of bonding metal layer  30 . Specifically, gap  33  is parallel to the outer side of first electrode E 1 . In the present embodiment, gap  33  is formed in a grid pattern. 
     As illustrated in  FIG.  1 A , height H of gap  33  may be at least 10% of the height of bonding metal layer  30 . Note that the upper limit of height H of gap  33  is not particularly limited and, for example, may be 90%. 
     Although details will be described later, bonding metal layer  30  is formed as a result of a plurality of metal bumps between semiconductor element  10  and mounting substrate  20  being connected to each other when semiconductor element  10  is mounted on mounting substrate  20 . At this time, gap  33  is formed inside bonding metal layer  30 . In other words, gap  33  is formed when semiconductor element  10  is mounted on mounting substrate  20  via the plurality of metal bumps. Hereinafter, a method for manufacturing semiconductor device  1  including a process in which gap  33  is formed will be described in detail. 
     Method for Manufacturing Semiconductor Device 
     The method for manufacturing semiconductor device  1  according to Embodiment 1 includes: a first step ( FIG.  3 A  and  FIG.  3 B ) for forming semiconductor multilayer structure  11  of semiconductor element  10 ; a second step ( FIG.  4 A  to  FIG.  4 I ) for forming the first electrode of semiconductor element  10 ; a third step ( FIG.  5 A  to  FIG.  5 E ) for forming metal bump  30 Y on semiconductor element  10 ; and a fourth step ( FIG.  6 A  and  FIG.  6 B ) for mounting semiconductor element  10  on mounting substrate  20  by flip-chip bonding. 
     First Step (Step for Forming Semiconductor Multilayer Structure) 
     First, semiconductor multilayer structure  11  of semiconductor element  10  is formed according to the flow illustrated in  FIG.  3 A  and  FIG.  3 B .  FIG.  3 A  and  FIG.  3 B  are diagrams illustrating the flow for forming semiconductor multilayer structure  11  of semiconductor element  10 . 
     Specifically, as illustrated in  FIG.  3 A , substrate  11   a  is prepared first. In the present embodiment, a wafer made of GaN (GaN substrate) is used for substrate  11   a  as a light-transmissive substrate formed of a semiconductor. 
     Next, as illustrated in  FIG.  3 B , n-type semiconductor layer  11   b , active layer  11   c , and p-type semiconductor layer  11   d  are sequentially stacked on substrate  11   a  by the metalorganic vapor-phase epitaxy (MOVPE) to form semiconductor multilayer structure  11 . 
     In the present embodiment, n-type semiconductor layer  11   b  is an n-type nitride semiconductor layer (for example, a GaN layer), active layer  11   c  is a nitride semiconductor light-emitting layer, and p-type semiconductor layer  11   d  is p-type nitride semiconductor layer. The nitride semiconductor light-emitting layer constituting active layer  11   c  contains at least Ga and N and an appropriate amount of In is added thereto as necessary so that a desired light-emission wavelength can be obtained. In the present embodiment, active layer  11   c  is an InGaN layer, and the composition ratio of In is set so that active layer  11   c  has a light-emission peak wavelength of 450 nm. 
     Second Step (Step for Forming First Electrode) 
     Next, first electrode E 1  (first p-side electrode  12 , first n-side electrode  13 ) of semiconductor element  10  is formed according to the flow illustrated in  FIG.  4 A  to  FIG.  4 I .  FIG.  4 A  to  FIG.  4 I  are diagrams illustrating the flow for forming first electrode E 1  of semiconductor element  10 . 
     Specifically, first, as illustrated in  FIG.  4 A , dry etching is performed to remove p-type semiconductor layer  11   d , active layer  11   c , and a portion of n-type semiconductor layer  11   b  from semiconductor multilayer structure  11  formed in the first step described above, and thus a portion of n-type semiconductor layer  11   b  is exposed from p-type semiconductor layer  11   d  and active layer  11   c . This makes it possible to form an exposed region in a portion of n-type semiconductor layer  11   b . 
     Next, as illustrated in  FIG.  4 B , oxide film  14  is deposited as an insulating film on the entire upper surface of semiconductor multilayer structure  11  including the exposed region of n-type semiconductor layer  11   b . 
     Thereafter, although not illustrated in the drawings, a resist is applied to oxide film  14 , an opening is formed in the resist by photolithography at a position corresponding to the exposed region of n-type semiconductor layer  11   b , and oxide film  14  in the opening of the resist is removed by etching using hydrofluoric acid. 
     Next, an n-side electrode forming material for forming first n-side electrode  13  of first electrode E 1  is deposited by the electron-beam (EB) evaporation, the resist and an excess of the n-side electrode forming material are removed by the resist lift-off process, and thus a portion of first n-side electrode  13  is formed in a region from which oxide film  14  has been removed, as illustrated in  FIG.  4 C . 
     In the present embodiment, as the n-side electrode forming material, an Al layer (having a thickness of 0.3 µm) that is to become ohmic contact layer  13   a  and a Ti layer (having a thickness of 0.1 µm) that is to become barrier electrode  13   b  are deposited in ascending order of distance from n-type semiconductor layer  11   b . Thus, as a portion of first n-side electrode  13 , laminated layers of ohmic contact layer  13   a  formed of the Al layer and barrier electrode  13   b  formed of the Ti layer can be formed. 
     Note that the Al layer of the first n-side electrode  13  directly stacked on n-type semiconductor layer  11   b  functions as an ohmic contact layer for n-type semiconductor layer  11   b . The material of the ohmic contact layer can be, for example, Ti, V, Al, or an alloy containing at least one of these metals. Furthermore, the Ti layer used in barrier electrode  13   b  functions as a barrier for preventing reaction between the lower layer, i.e., the Al layer, and the upper layer i.e., an Au layer, to be formed in a subsequent step. 
     Thereafter, although not illustrated in the drawings, a resist is applied so as to cover first n-side electrode  13  and oxide film  14 , an opening is formed in the resist ofp-type semiconductor layer  11   d  by photolithography, and oxide film  14  in the opening of the resist is removed by etching using hydrofluoric acid. 
     Next, a p-side electrode forming material for forming first p-side electrode  12  of first electrode E 1  is deposited by the EB evaporation, the resist and an excess of the p-side electrode forming material are removed by the resist lift-off process, and thus reflective electrode  12   a , which is a portion of first p-side electrode  12 , is formed in a region on p-type semiconductor layer  11   d  from which oxide film  14  has been removed, as illustrated in  FIG.  4 D . 
     In the present embodiment, as reflective electrode  12   a  (p-side electrode forming material) formed of an Ag layer, an Ag layer having a thickness of 0.2 µm is deposited. At this time, reflective electrode  12   a  is formed apart from oxide film  14 . Stated differently, reflective electrode  12   a  is formed so as to expose p-type semiconductor layer  11   d  between reflective electrode  12   a  and oxide film  14 . 
     Note that a metal film made of a metal material having a high reflectivity and including Ag, Al, and Rh may be used as reflective electrode  12   a  in order to reflect light from active layer  11   c . The method for depositing reflective electrode  12   a  is not limited to the EB evaporation and may be sputtering. 
     Next, as illustrated in  FIG.  4 E , barrier electrode  12   b  is formed so as to cover an upper surface and side surfaces of reflective electrode  12   a . In the present embodiment, a Ti layer having a thickness of 0.8 µm is formed by sputtering as barrier electrode  12   b . As the material of barrier electrode  12   b , Ti, Ni, Pt, TiW, or the like may be used in order to protect reflective electrode  12   a . At this time, barrier electrode  12   b  is formed so as to cover p-type semiconductor layer  11   d  exposed between oxide film  14  and reflective electrode  12   a  and an end of oxide film  14  that is located on n-type semiconductor layer  11   b . 
     Next, as illustrated in  FIG.  4 F , seed film  12 S is formed by the EB evaporation on the entire surface of the wafer having barrier electrode  12   b  of first p-side electrode  12  and barrier electrode  13   b  of first n-side electrode  13  formed thereon. Seed film  12 S, which is a metal film that is to become seed layer  12   c  of first p-side electrode  12  and seed layer  13   c  of first n-side electrode  13 , is used as a gold-plated undercoat electrode. In the present embodiment, seed film  12 S is laminated layers of the Ti layer and the Au layer stacked in a direction away from barrier electrodes  12   b ,  13   b . 
     Next, as illustrated in  FIG.  4 G , resist  15  is formed on seed film  12 S in a boundary region between barrier electrode  12   b  corresponding to first p-side electrode  12  and barrier electrode  13   b  corresponding to first n-side electrode  13 . 
     Next, as illustrated in  FIG.  4 H , in a region on the wafer in which resist  15  has not been formed (non-resist region), cover electrodes  12   d ,  13   d , which are gold-plated films, are formed by metal deposition resulting from electroplating over seed film  12 S as an undercoat electrode. Cover electrode  12   d  is formed on seed film  12 S on barrier electrode  12   b , and cover electrode  13   d  is formed on seed film  12 S on barrier electrode  13   b . As an example of the conditions for forming the plated films as cover electrodes  12   d ,  13   d , a non-cyanic Au plating solution having a plating temperature of 50° C. is used, and the rate of deposition is set to 0.5 µm/min; thus, the gold-plated films having a thickness of 1.0 µm are formed as cover electrodes  12   d ,  13   d . 
     Here, Au or a material containing Au is used as cover electrodes  12   d ,  13   d  in order to improve resistance to corrosion. In a plan view of semiconductor element  10  on the cover electrode  12   d  (cover electrode  13   d ) side, cover electrode  12  encapsulates barrier electrode  12   b , and cover electrode  13   d  encapsulates barrier electrode  13   b . Note that oxide film  14  is located between cover electrode  12   d  and cover electrode  13   d  on the semiconductor multilayer structure  11  side. 
     Next, as illustrated in  FIG.  4 I , resist  15  is removed. For example, resist  15  on seed film  12 S is removed using an organic solvent or the like. 
     Third Step (Step for Forming Metal Bump) 
     Next, metal bump  30 Y is formed on semiconductor element  10  according to the flow illustrated in  FIG.  5 A  to  FIG.  5 E .  FIG.  5 A  to  FIG.  5 E  are diagrams illustrating the flow for forming metal bump  30 Y on semiconductor element  10 . 
     Metal bump  30 Y described below includes: a first bump on the p side that corresponds to first p-side electrode  12 ; and a second bump on the n side that corresponds to first n-side electrode  13 . The first bump is formed on first p-side electrode  12 , and the second bump is formed on first n-side electrode  13 . In the present embodiment, metal bump  30 Y is a gold-plated bump formed by gold-plating. Metal bump  30 Y includes a plurality of metal layers and has a laminated structure in which at least two layers of gold-plated films having different crystal grain sizes are stacked. Hereinafter, a method for forming metal bump  30 Y will be described in detail. 
     After the second step described above, first, a resist for photolithography is applied so as to cover the entire surfaces of cover electrodes  12   d ,  13   d , and the resist is cured by approximately 20-minute heat treatment at 140° C. Thereafter, as illustrated in  FIG.  5 A , opening  16   a  is formed in resist  16  in a predetermined region of first electrode E 1  in which metal bump  30 Y is to be formed. Specifically, a plurality of openings  16   a  are formed by photolithography in resist  16  in predetermined regions of cover electrode  12   d  of first p-side electrode  12  and cover electrode  13   d  of first n-side electrode  13  in which metal bumps  30 Y are to be formed. 
     Note that in the present embodiment, nine total metal bumps  30 Y are illustrated as a schematic diagram, but there are actually cases where nine or more metal bumps  30 Y are formed. As one example, in semiconductor element  10  according to the present embodiment that is 800 µm square and 100 µm thick, approximately 1,000 metal bumps  30 Y each in the shape of a rectangular prism having an upper rectangular surface with a side length of 25 µm may be formed. Note that the size, the shape, the number, etc., of metal bumps  30 Y are not particularly limited and may be individually and specifically set according to the size of semiconductor element  10  and the area, the shape, etc., of each of first electrode E 1  and second electrode E 2 , for example. For example, the number of metal bumps  30 Y may be less than nine or may be a few tens or a few hundreds. 
     Next, as illustrated in  FIG.  5 B , gold-plated film  30 X, which is to become metal bump  30 Y, is formed by metal deposition in opening  16   a  of resist  16  that results from gold electroplating. Specifically, gold-plated films  30 X are simultaneously formed on cover electrode  12   d  of first p-side electrode  12  and cover electrode  13   d  of first n-side electrode  13  that are exposed in openings  16   a  of resist  16 . As an example of the conditions for forming gold-plated film  30 X, a non-cyanic Au plating solution having a plating temperature of 50° C. is used, and the rate of deposition is set to 0.5 µm/min; thus, gold-plated film  30 X having a height (thickness) of 8 µm is formed. The crystal structure of gold-plated film  30 X immediately after formation is an aggregate of fine crystal grains overall. 
     Next, as illustrated in  FIG.  5 C , resist  16  is removed. For example, resist  16  is removed using an organic solvent or the like. Thus, the plurality of gold-plated films  30 X each in the shape of a rectangular prism are formed in predetermined regions on cover electrode  12   d  of first p-side electrode  12  and cover electrode  13   d  of first n-side electrode  13 . 
     In this case, the distance between adjacent gold-plated films  30 X is the distance between adjacent metal bumps  30 Y and is set to such a level that adjacent metal bumps  30 Y contact each other when semiconductor element  10  is mounted on mounting substrate  20 . For example, in the case of forming a plurality of gold-plated films  30 X each in the shape of a rectangular prism having a height of 8 µm and an upper rectangular surface with a side length of 25 µm, the distance between adjacent gold-plated films  30  is, for example, 6 µm. 
     Next, as illustrated in  FIG.  5 D , a portion of seed film  12 S on oxide film  14  located between barrier electrode  12   b  of first p-side electrode  12  and barrier electrode  13   b  of first n-side electrode  13  is removed. In the present embodiment, since seed film  12 S has a laminated structure of the Au layer and the Ti layer, first, the upper layer, i.e., the Au layer, of seed film  12 S is removed using an iodine solution, and then the lower layer, i.e., the Ti layer, of seed film  12 S is removed using dilute hydrofluoric acid, resulting in exposure of oxide film  14 . This enables pn isolation of first electrode E 1  by splitting seed film  12 S as p-side seed layer  12   c  and n-side seed layer  13   c  on oxide film  14 . Specifically, first electrode E 1  divided as first p-side electrode  12 , which has a laminated structure of reflective electrode  12   a , barrier electrode  12   b , seed layer  12   c , and cover electrode  12   d , and first n-side electrode  13 , which has a laminated structure of ohmic contact layer  13   a , barrier electrode  13   b , seed layer  13   c , and cover electrode  13   d , can be formed. 
     Next, as illustrated in  FIG.  5 E , one-hour heat treatment is performed in an air atmosphere at 150° C. on the wafer having gold-plated film  30 X formed thereon. This heat treatment changes the crystal grain size of each of a lower region of gold-plated film  30 X and cover electrodes  12   d ,  13   d . Accordingly, metal bump  30 Y including two layers, namely, first layer  30   a  and second layer  30   b , with the same composition, but different crystal grain sizes can be obtained. In metal bump  30 Y, first layer  30   a , which is close to semiconductor multilayer structure  11 , has a larger crystal grain size than the crystal grain size of second layer  30   b , which is far from semiconductor multilayer structure  11 . The crystal grain size of crystals included in first layer  30   a  of metal bump  30 Y is equal to the crystal grain size of crystals included in cover electrodes  12   d ,  13   d . 
     Thus, semiconductor element  10  including first electrode E 1  having the plurality of metal bumps  30 Y formed thereon can be obtained. Specifically, semiconductor element  10  including first p-side electrode  12  having the plurality of metal bumps  30 Y formed thereon and first n-side electrode  13  having metal bump  30 Y formed thereon can be obtained. 
     Note that in the present embodiment, the plurality of metal bumps  30 Y  are arranged in a matrix. The distance between the plurality of metal bumps  30 Y is set to such a level that adjacent metal bumps  30 Y contact each other by the process of mounting semiconductor element  10  on mounting substrate  20 . 
     Here, changes in the crystal grain size by the heat treatment in  FIG.  5 E  will be described in detail with reference to  FIG.  7 A  to  FIG.  7 C .  FIG.  7 A  is an enlarged view of region VIIA in  FIG.  5 D .  FIG.  7 B  is an enlarged view of region VIIB in  FIG.  5 E .  FIG.  7 C  illustrates crystal grains resulting from further coarsening of crystal grains in  FIG.  7 B .  FIG.  7 A  to  FIG.  7 C  each illustrate a region corresponding to single gold-plated film  30 X or metal bump  30 Y on first p-side electrode  12  of first electrode E 1  and a portion of cover electrode  12   d  of first p-side electrode  12  that is located below said single gold-plated film  30 X or metal bump  30 Y. 
       FIG.  7 A  illustrates a cross section of gold-plated film  30 X immediately after formation of gold-plated film  30 X. As illustrated in  FIG.  7 A , gold-plated film  30 X immediately after formation is an aggregate of fine crystal grains overall. 
     After the heat treatment using a hot plate starts on the wafer having gold-plated film  30 X formed thereon, heat efficiently transfers from the first p-side electrode  12  (cover electrode  12   d ) side to gold-plated film  30 X in the direction of the arrow, as illustrated in  FIG.  7 B . The heat transferred to gold-plated film  30 X serves as driving energy for recrystallizing gold included in gold-plated film  30 X, and thus the crystal grains on the first p-side electrode  12  side grow significantly. As the heat treatment continues, the crystal grains are coarsened from the first p-side electrode  12  side toward the tip of gold-plated film  30 X, and eventually coarsened crystal grains are spread all over gold-plated film  30 X, as illustrated in  FIG.  7 C . The crystal grains are further coarsened with increasing heat treatment temperature or increasing heat treatment time. 
     The heat treatment conditions (one-hour heat treatment at 150° C.) for forming metal bump  30 Y in the present embodiment are not conditions for coarsening gold-plated film  30 X up to the tip thereof by recrystallization as illustrated in  FIG.  7 C , but are conditions for stopping the coarsening of the crystal grains along the way in gold-plated film  30 X as illustrated in  FIG.  7 B . In other words, as a result of performing the one-hour heat treatment on gold-plated film  30 X in the air atmosphere at 150° C., metal bump  30 Y, which has substantially two-layer structure when classified by the crystal grain size, is formed. Specifically, metal bump  30 Y including: first layer  30   a  located close to first p-side electrode  12  and having coarsened crystal grains; and second layer  30   b  located opposite to first p-side electrode  12  and having relatively small crystal grains is formed. 
     It is not only gold-plated film  30 X formed on first p-side electrode  12  of first electrode E 1  that have crystal grains changed; the crystal grains in gold-plated film  30 X formed on first n-side electrode  13  of first electrode E 1  also change as in gold-plated film  30 X formed on first p-side electrode  12 . Specifically, the one-hour heat treatment at 150° C. causes gold-plated film  30 X formed on first n-side electrode  13  to change into two layers having different crystal grain sizes, resulting in formation of metal bump  30 Y including: first layer  30   a  located close to first n-side electrode  13  and having coarsened crystal grains; and second layer  30   b  located opposite to first n-side electrode  13  and having relatively small crystal grains, as illustrated in  FIG.  7 B . 
     Thus, metal bump  30 Y includes first layer  30   a  and second layer  30   b  having different metal crystal grain sizes. Specifically, in metal bump  30 Y, the average crystal grain size of the crystals included in first layer  30   a  is larger than the average crystal grain size of the crystals included in second layer  30   b . 
     Here, the relationship between the crystal grain size and the hardness of a metal will be described. Generally, there is a negative correlation between the crystal grain size and the hardness of a metal. In other words, the hardness increases as the crystal grain size is reduced. Conversely, the hardness is reduced as the crystal grain size increases. This is because the hardness of a metal depends on the amount of plastic deformation of the metal that occurs when a load is placed thereon, and the amount of plastic deformation is affected by obstacles against multiplication and migration of dislocation, slip plane length and metal crystal orientation. 
     The slip plane of metal crystals is fixed in a specific direction of a crystal lattice; when stress is exerted, slip occurs in that direction, causing plastic deformation of the metal. In other words, a metal crystalline body having a large crystal grain size has a long slip line and when stress is exerted, the stress is concentrated on crystal boundaries, and thus plastic deformation is likely to occur around the crystal boundaries. This means that the metal crystalline body having a large crystal grain size is soft. 
     In contrast, an individual grain of a metal crystalline body having a small crystal grain size has a short slip plane and when stress is exerted, there are many slip planes that do not match the direction of the stress. Therefore, such crystals serve as resistance to reduce slip, lowering the likelihood of the plastic deformation of the metal. This means that the metal crystalline body having a small crystal grain size is hard. 
     The above relationship between the crystal grain size and the hardness is also true for a gold-plated film. Specifically, there is a negative correlation between the crystal grain size and the hardness of metal bump  30 Y including gold-plated film  30 X. In other words, as the average crystal grain size of the crystals included in gold-plated film  30 X increases, the hardness is reduced. 
     Furthermore, in metal bump  30 Y according to the present embodiment, first layer  30   a  has crystal grains coarsened due to recrystallization with heat as a result of the heat treatment of gold-plated film  30 X. Specifically, in metal bump  30 Y, first layer  30   a , which includes crystals having a relatively large average crystal grain size, is softer than second layer  30   b , which includes crystals having a relatively small average crystal grain size. 
     Furthermore, a method for measuring the crystal grain sizes of gold-plated film  30 X and metal bump  30 Y used in the present embodiment will be described below. In the present embodiment, a cross section of gold-plated film  30 X or metal bump  30 Y is formed using a focused ion beam (FIB), then the intercept method is applied to an observation region observed in a scanning ion microscopy image (SIM image) from a scanning microscope, and thus the crystal grain size is measured. 
     At this time, as illustrated in  FIG.  8   , when there are n crystals having average crystal grain size d per side of a square with each side of length L, the area of the square is L 2 , and the area of one crystal grain size is π(d/2) 2 . Furthermore, when the observation region is relatively large for the crystal grains, since there are n 2  crystal grains in the square, the area occupied by all the crystal grains is n 2  × π(d/2)  2 , resulting in the area of the square = the area occupied by all the crystal grains, which is L 2  = n 2  × π(d/2) 2 . Using d, this is expressed as the following relational expression: d = 2L / n / (π) ½ . According to the relational expression, a straight line (the dashed-dotted line in  FIG.  8   ) is drawn on observation region L × L, and assuming that the number of grain boundaries crossing the straight line is number n of crystals, average crystal grain sizes d of gold-plated film  30 X and metal bump  30 Y in the horizontal and height directions are determined. 
     In this case, the horizontal direction is parallel to the upper surfaces of cover electrodes  12   d ,  13   d , and the height direction is perpendicular to the upper surfaces of cover electrodes  12   d ,  13   d . Note that in  FIG.  8   , the dashed-dotted straight line crosses six grain boundaries, and thus n = 6. 
     In the present embodiment, metal bump  30 Y including first layer  30   a  and second layer  30   b  having different crystal grain sizes has the cross section illustrated in  FIG.  7 B . In this case, the crystal grain sizes of metal bump  30 Y are measured by the above-described method; the average crystal grain size of first layer  30   a  in the horizontal direction is 8 µm, the average crystal grain size of second layer  30   b  in the horizontal direction is 1 µm, the average crystal grain size of first layer  30   a  in the height direction is 3 µm, and the average crystal grain size of second layer  30   b  in the height direction is 2 µm. 
     An experiment was conducted to demonstrate the relationship between the average crystal grain size of a gold-plated film and the hardness of a single-layered gold-plated film; the result of this experiment will be described with reference to  FIG.  9   .  FIG.  9    illustrates the relationship between the average crystal grain size of a gold-plated film and the hardness of a single-layered gold-plated film. 
     In this experiment, a gold-plated films having a thickness of 10 µm was prepared using a non-cyanic Au plating solution having a plating temperature of 50° C. by setting the rate of deposition to 0.5 µm/min. The average crystal grain size is controlled by changing the heat treatment conditions for the single-layered gold-plated film; the relationship between the average crystal grain size of the gold-plated film after the heat treatment and the hardness of the single-layered gold-plated film before the heat treatment was monitored. The average crystal grain size of the gold-plated film was measured using the above-described method for measuring a crystal grain size. In this case, the average crystal grain size in the horizontal direction was measured. Regarding the hardness of the single-layered gold-plated film, the hardness was measured through the Vickers hardness test. Note that in the following description, unless otherwise noted, the average crystal grain size represents the average crystal grain size in the horizontal direction. 
     As illustrated in  FIG.  9   , there is a negative correlation between the average crystal grain size of the gold-plated film and the hardness of the single-layered gold-plated film. In other words, the hardness increases as the average crystal grain size of the crystals included in the gold-plated film is reduced. Conversely, the hardness is reduced as the average crystal grain size of the crystals included in the gold-plated film increases. Thus, the hardness of the gold-plated film is reduced with an increase in the average crystal grain size of the gold-plated film, and increases with a decrease in the average crystal grain size of the gold-plated film. 
     For example, as illustrated in  FIG.  9   , when the average crystal grain size of the crystals included in the gold-plated film is 8 µm, the hardness of the gold-plated film is approximately 0.8 GPa. Specifically, in metal bump  30 Y formed under the above-described heat treatment conditions, first layer  30   a  having an average crystal grain size of 8 µm is approximately 0.8 GPa. 
     When the average crystal grain size of the crystals included in the gold-plated film is 1 µm, the hardness of the gold-plated film is approximately 1.9 GPa. Specifically, in metal bump  30 Y formed under the above-described heat treatment conditions, second layer  30   b  having an average crystal grain size of 1 µm is approximately 1.9 GPa. 
     Thus, the average crystal grain sizes are compared, and a film having a larger crystal grain size becomes a soft layer while a film having a smaller crystal grain size becomes a hard layer. Specifically, a gold-plated film having an average crystal grain size of 8 µm (first layer  30   a ) is softer than a gold-plated film having an average crystal grain size of 1 µm (second layer  30   b ). [Fourth Step (Step for Mounting Semiconductor Element on Mounting substrate)] 
     Next, semiconductor element  10  is mounted on mounting substrate  20  via metal bumps  30 Y by flip-chip bonding according to the flow illustrated in  FIG.  6 A  and  FIG.  6 B .  FIG.  6 A  and  FIG.  6 B  are diagrams illustrating the flow for mounting semiconductor element  10  on mounting substrate  20  via metal bumps  30 Y by flip-chip bonding. 
     First, mounting substrate  20  on which semiconductor element  10  is to be mounted is prepared. Specifically, substrate  21  having second p-side electrode  22  and second n-side electrode  23  formed thereon as second electrode E 2  is prepared as mounting substrate  20 . In the present embodiment, substrate  21  is a ceramic substrate made from a sintered body of AlN. Second p-side electrode  22  and second n-side electrode  23 , which are gold-plated films, were formed using a non-cyanic Au plating solution. Although not illustrated in the drawings, a seed layer divided by second p-side electrode  22  and second n-side electrode  23  may be formed between substrate  21  and second p-side and n-side electrodes  22 ,  23 . 
     Subsequently, as illustrated in  FIG.  6 A , semiconductor element  10  having metal bumps  30 Y formed thereon in advance is prepared, and holing metal tube  40  of a mounter picks up and carries semiconductor element  10  by vacuum suction in such a manner that the metal bump  30 Y side faces mounting substrate  20 . Note that in the present embodiment, 800 µm square and 100 µm thick semiconductor element  10  is used. 
     Next, as illustrated in  FIG.  6 B , metal bump  30 Y of semiconductor element  10  and second electrode E 2  (second p-side electrode  22  and second n-side electrode  23 ) of mounting substrate  20  are brought into contact with each other and heated to approximately 200° C. in this state, and ultrasonic vibration is applied to mounting substrate  20  in the horizontal direction (the direction of arrow Y in the figure; the second direction) for 200 milliseconds while a  30 N load is placed on mounting substrate  20  in the vertical direction (the direction of arrow X in the figure; the first direction) using holding metal tube  40 ; thus, metal bump  30 Y and second electrode E 2  (second p-side electrode  22  and second n-side electrode  23 ) of mounting substrate  20  are ultrasonically bonded together. 
     A change occurring in metal bump  30 Y when ultrasonically bonding metal bump  30 Y and the second electrode of mounting substrate  20  together will be described in detail with reference to  FIG.  10    and  FIG.  11 A  to  FIG.  11 E . 
       FIG.  10    is a timing chart for a bonding process according to Embodiment 1 when mounting semiconductor element  10  on mounting substrate  20 . In  FIG.  10   , the horizontal axis represents time, and the vertical axis represents a load. Note that in the horizontal axis, time on the negative side of 0 milliseconds represents a point in time before the start of the processing, and 0 milliseconds represents the point in time of the start of the processing. 
     As illustrated in  FIG.  10   , the load gradually increases in the period of 100 milliseconds (STEP 1) after the start of the bonding process for semiconductor element  10  and mounting substrate  20 . In STEP 1, no ultrasonic waves are applied, but only the load is placed. In the period between 100 milliseconds and 400 milliseconds (STEP 2), ultrasonic waves are applied while the load is maintained at a constant level. Semiconductor element  10  and mounting substrate  20  are ultrasonically bonded via metal bump  30 Y through such a bonding process illustrated in the timing chart. 
     In this case,  FIG.  11 A  to  FIG.  11 E  illustrate cross sections of portions of semiconductor element  10  and mounting substrate  20  that are bonded together, specifically, portions of two adjacent metal bump  30 Y and the second electrode of mounting substrate  20  that are bonded together, at a point in time before the start of the bonding process for semiconductor element  10  and mounting substrate  20  and 0 milliseconds, 100 milliseconds, 300 milliseconds, and 400 milliseconds after the start of the bonding process. Although  FIG.  11 A  to  FIG.  11 E  illustrate only the bonded portions on second p-side electrode  22  of second electrode E 2  of mounting substrate  20 , the same is true for the bonded portions on second n-side electrode  23  of second electrode E 2 . 
       FIG.  11 A  illustrates metal bumps  30 Y and second electrode E 2  of mounting substrate  20  before the bonding process for semiconductor element  10  and mounting substrate  20 . As illustrated in  FIG.  11 A , the crystal grains of gold (Au) included in first layer  30   a  and second layer  30   b  of each metal bump  30 Y have approximately the same grain size in each layer. Note that metal bumps  30 Y have the same shape, specifically, the shape of a rectangular prism. 
       FIG.  11 B  illustrates metal bumps  30 Y and second electrode E 2  of mounting substrate  20  at the start (0 milliseconds) of the bonding process for semiconductor element  10  and mounting substrate  20 . Specifically,  FIG.  11 B  illustrates the state where the tip surface of metal bump  30 Y formed on semiconductor element  10  is brought into contact with second electrode E 2  of mounting substrate  20 . As illustrated in  FIG.  11 B , at the start of the process (0 milliseconds), first layer  30   a  and second layer  30   b  of each metal bump  30 Y have approximately the same grain size as in  FIG.  11 A . 
     Subsequently, after the plurality of metal bumps  30 Y formed on semiconductor element  10  are brought into contact with second electrode E 2  of mounting substrate  20 , the process in STEP 1 in  FIG.  10    is performed. Specifically, in STEP 1, a load (mounting load) is placed on semiconductor element  10  and mounting substrate  20 , between which the plurality of metal bumps  30 Y are sandwiched, in a direction perpendicular to the principal surface of mounting substrate  20 . 
     As illustrated in  FIG.  10   , the load gradually increases in STEP 1. Accordingly, as the load is placed, entire first layer  30   a , which is relatively softer than second layer  30   b , is deformed and spread horizontally. At this time, second layer  30   b , which is relatively harder than first layer  30   a , is not deformed, but maintains approximately the same shape as that before the start of the process. As a result, the shape of each metal bump  30 Y becomes an approximate wide top shape with horizontally spreading first layer  30   a , as illustrated in  FIG.  11 C . Note that the second electrode (second p-side electrode  22  and second n-side electrode  23 ) of mounting substrate  20  maintains the same surface shape as that before the start of the process. 
     As a result of entire first layer  30   a  of each metal bump  30 Y being deformed and spread horizontally, adjacent metal bumps  30 Y are brought into contact with each other, as illustrated in  FIG.  11 C . Specifically, first layers  30   a  of adjacent metal bumps  30 Y come into contact with each other. Note that second layers  30   b  of adjacent metal bumps  30 Y are not in contact with each other. 
       FIG.  11 C  illustrates metal bumps  30 Y and second electrode E 2  of mounting substrate  20  that are bonded together at the transition from STEP 1 to STEP 2 in  FIG.  10    (approximately 100 milliseconds later after the start of the process). Although the load increases from load 0 N to load 30 N in the form of a linear function in a 100-millisecond period in STEP 1 in the present embodiment, this is not limiting. 
     Subsequently, after adjacent metal bumps  30 Y come into contact with each other, the transition occurs from STEP 1 to STEP 2, as illustrated in  FIG.  10   . In STEP 2, as illustrated in  FIG.  11 D , a predetermined load is placed on semiconductor element  10  and mounting substrate  20 , between which metal bumps  30 Y are sandwiched, in a direction perpendicular to the principal surface of mounting substrate  20  (the direction of arrow X in the figure), and ultrasonic waves are applied in a direction horizontal to the principal surface of mounting substrate  20  (the direction of arrow Y in the figure). In the present embodiment, ultrasonic vibration is applied in the state where the same load as the last load in STEP 1 is placed on semiconductor element  10  and mounting substrate  20  between which the plurality of metal bumps  30 Y are sandwiched. 
     Note that  FIG.  11 D  illustrates metal bumps  30 Y and second electrode E 2  of mounting substrate  20  that are bonded together in the middle of STEP 2 in  FIG.  10    (approximately 300 milliseconds later after the start of the process and approximately 200 milliseconds later after the start of the ultrasonic vibration). 
     As a result of such ultrasonic wave application while placing the load, metal bump  30 Y vibrates in the direction horizontal to mounting substrate  20 , and the interface at which second layer  30   b  of metal bump  30 Y and second electrode E 2  of mounting substrate  20  are in contact is heated by friction, leading to solid-phase bonding and integration of metal bump  30 Y and second electrode E 2  of mounting substrate  20 . Specifically, the ultrasonic vibration with the load being placed causes metal bump  30 Y to rub against second electrode E 2 , and thus a portion at the interface between metal bump  30 Y and second electrode E 2  is recrystallized. At this time, there are cases where some of the Au crystal grains in a surface layer of second electrode E 2  and the Au crystal grains in second layer  30   b  of metal bump  30 Y may be integrated without maintaining their original shapes and the boundary between second layer  30   b  of metal bump  30 Y and second electrode E 2  may become unclear. 
     Subsequently, as the load and ultrasonic wave application continues, the recrystallized portion at the interface between each metal bump  30 Y and second electrode E 2  becomes softer. Therefore, when semiconductor element  10  is pushed down with the load, a portion of second layer  30   b  of each metal bump  30 Y at the interface between second layer  30   b  and second electrode E 2  is deformed and spread horizontally. As a result, each metal bump  30 Y is approximately in the shape of an hourglass with entire first layer  30   a  spreading horizontally and a portion of second layer  30   b  that is bonded to second electrode E 2  spreading horizontally, as illustrated in  FIG.  11 E . In other words, each metal bump  30 Y has a constricted shape with a center portion narrowing along the entire perimeter. 
     Furthermore, as a result of the recrystallized portion at the interface between second layer  30   b  of metal bump  30 Y and second electrode E 2  being deformed and spread horizontally, adjacent metal bumps  30 Y come into contact with each other not only in first layers  30   a , but also partially in second layers  30   b , as illustrated in  FIG.  11 E . Specifically, aside from entire first layers  30   a  of adjacent metal bumps  30 Y, portions of second layers  30   b  of adjacent metal bumps  30 Y that are bonded to second electrode E 2  come into contact with each other. 
       FIG.  11 E  illustrates metal bumps  30 Y and second electrode E 2  of mounting substrate  20  that are bonded together at the end of STEP 2 in  FIG.  10    (approximately 400 milliseconds later after the start of the process and approximately 300 milliseconds later after the start of the ultrasonic vibration). 
     In this manner, as the load and ultrasonic wave application continues, Au crystal grains originated from second layer  30   b  and Au crystal grains originated from second electrode E 2  are integrated at the bonding interface between second layer  30   b  of metal bump  30 Y and second electrode E 2  of mounting substrate  20 . Furthermore, as illustrated in  FIG.  11 E , third layer  30   c  is formed in a portion of second layer  30   b  of metal bump  30 Y as a layer including coarsened Au crystal grains resulting from integration of the Au crystal grains from second layer  30   b  and the Au crystal grains from second electrode E 2 . 
     As a result, metal bump  30 Y in which first layer  30   a  and third layer  30   c  have greater widths (diameters) than second layer  30   b  is formed, first layers  30   a  of adjacent metal bumps  30 Y are connected to each other, and third layers  30   c  of adjacent metal bumps  30 Y are connected to each other. Thus, the plurality of metal bumps  30 Y formed between semiconductor element  10  and mounting substrate  20  are coupled to each other, not at center portions, but at upper and lower portions only, resulting in bonding metal layer  30  having hollow gap  33 . 
     In the above-described manner, semiconductor device  1  in which first electrode E 1  of semiconductor element  10  and second electrode E 2  of mounting substrate  20  are bonded together by bonding metal layer  30 , as illustrated in  FIG.  6 B , can be manufactured. Thus, bonding metal layer  30  in semiconductor device  1  is a metal layer obtained by deforming and integrating the plurality of metal bumps  30 Y. Specifically, bonding metal layer  30  is formed by connecting first layers  30   a  of metal bumps  30 Y to each other and connecting third layers  30   c  of metal bumps  30 Y to each other, as illustrated in  FIG.  11 E . Gap  33  inside bonding metal layer  30  is a hollow region formed as a result of second layers  30   b  of metal bumps  30 Y failing to be connected to each other. 
     Working Effects, Etc. 
     Next, working effects of semiconductor device  1  according to the present embodiment will be described in comparison to conventional semiconductor device  100 .  FIG.  12    is a cross-sectional view illustrating a method for manufacturing conventional semiconductor device  100  disclosed in Japanese Unexamined Patent Application Publication No. 2011-009429.  FIG.  13    is a diagram illustrating the configurations of semiconductor device  1  according to Embodiment 1 before and after mounting. In  FIG.  13 ,( a )  is a cross-sectional view in which semiconductor element  10  has not yet been mounted on mounting substrate  20 , and (b) is a cross-sectional view in which semiconductor element  10  has already been mounted on mounting substrate  20 . 
     As illustrated in  FIG.  12   , conventional semiconductor device  100  is manufactured by bonding, via the plurality of metal bumps  300 Y, semiconductor element  10  including semiconductor multilayer structure  11  and first electrode E 1  and mounting substrate  20  including substrate  21  and second electrode E 2 . Specifically, semiconductor element  10  having the plurality of metal bumps  300 Y formed thereon is mounted on mounting substrate  20 . 
     At this time, upon deforming of metal bumps  300 Y with load for mounting (mounting load), the mounting load is locally concentrated on contact surface S 1  between first electrode E 1  of semiconductor element  10  and metal bumps  300 Y and the mounting substrate, and the mounting load is locally concentrated on contact surface S 2  between second electrode E 2  of mounting substrate  20  and metal bumps  300 Y. This may result in damage to each of first electrode E 1  of semiconductor element  10  and second electrode E 2  of mounting substrate  20  due to metal bumps  300 Y, causing a risk of electrode failures of first electrode E 1  and second electrode E 2 . 
     In contrast, in semiconductor device  1  according to the present embodiment, at the time of mounting of semiconductor element  10  having the plurality of metal bumps  30 Y formed thereon on mounting substrate  20 , bonding metal layer  30  is formed so as to include gap  33  inside, as illustrated in  FIG.  13   . 
     Specifically, at the time of mounting semiconductor element  10  on mounting substrate  20  by placing the load, the plurality of metal bumps  30  are deformed in such a manner that upper portions of adjacent metal bumps  30 Y come into contact with each other, lower portions of adjacent metal bumps  30 Y  come into contact with each other, and hollow gap  33  is left, as illustrated in  FIG.  11 A  to  FIG.  11 E  referred to above. This makes it possible to evenly distribute the load for mounting that is placed on each of the entire surface of first electrode E 1  of semiconductor element  10  and the entire surface of second electrode E 2  of mounting substrate  20 . As a result, localized stress that metal bumps  30 Y give to first electrode E 1  and second electrode E 2  at the time of mounting can be made small, and thus it is possible to reduce damage to first electrode E 1  and second electrode E 2  that may be caused by metal bumps  30 Y. 
     Thus, with semiconductor device  1  according to the present embodiment, mounting damage due to electrode failures of first electrode E 1  and second electrode E 2  can be reduced; therefore, it is possible to provide semiconductor device  1  exceptionally reliable in the long run. 
     Furthermore, in semiconductor device  1  according to the present embodiment, gap  33  inside bonding metal layer  30  extends linearly along the outer side of first electrode E 1  of semiconductor element  10 . 
     Thus, when gap  33  of bonding metal layer  30  extends along the outer side of first electrode E 1  of semiconductor element  10 , it is considered that the plurality of metal bumps  30 Y, which become bonding metal layer  30 , have been arranged neatly in a matrix before mounting. In addition, when metal bumps  30 Y are arranged neatly in a matrix, the load for mounting that is placed on the entire surface of each of first electrode E 1  and second electrode E 2  can be evenly distributed as compared to the case where metal bumps  30 Y are arranged at random. Accordingly, localized stress that metal bumps  30 Y give to first electrode E 1  and second electrode E 2  can be made small, and thus it is possible to reduce damage to first electrode E 1  and second electrode E 2  that may be caused by metal bumps  30 Y. 
     Note that in the present description, regarding the wording “gap  33   extends along the outer side of first electrode E1”, it is sufficient that gap  33  generally extend along the outer side of first electrode E 1 ; for example, even if the outer side of first electrode E 1  are not perfectly linear with small dents in a part of the outer side, linear gap  33  can be described as extending along the outer side of first electrode E 1 . In other words, as long as gap  33  extends along the outer side of first electrode E 1  from a broad perspective, such a situation is included in the concept of gap  33  extending along the outer side of first electrode E 1 . 
     Furthermore, in semiconductor device  1  according to the present embodiment, gap  33  inside bonding metal layer  30  is parallel to the outer side of first electrode E 1 . 
     Thus, when gap  33  of bonding metal layer  30  is parallel to the outer side of first electrode E 1 , it is considered that metal bumps  30 Y having the same width have been arranged neatly in a matrix before bonding. In addition, when metal bumps  30 Y having the same width are arranged neatly in a matrix, the load for mounting that is placed on the entire surface of each of first electrode E 1  and second electrode E 2  can be evenly distributed as compared to the case where metal bumps  30 Y having different widths are arranged. Accordingly, localized stress that metal bumps  30 Y give to first electrode E 1  and second electrode E 2  can be made small, and thus it is possible to reduce damage to first electrode E 1  and second electrode E 2  that may be caused by metal bumps  30 Y. 
     Furthermore, in semiconductor device  1  according to the present embodiment, height H of gap  33  inside bonding metal layer  30  is at least 10% of the height of bonding metal layer  30 . 
     When the height of gap  33  is set to at least 10% of the height of bonding metal layer  30  as mentioned above, the size of gap  33  can be maintained to some extent. With this, the load for mounting can be effectively distributed, and thus it is possible to effectively reduce localized stress that metal bumps  30 Y give to first electrode E 1  and second electrode E 2 . 
     Here, other shapes of gap  33  of bonding metal layer  30  will be described with reference to  FIG.  14 A  to  FIG.  140   .  FIG.  14 A  to  FIG.  140    are cross-sectional views each illustrating a portion of a cross section in the M cross section in  FIG.  13    [AFTER MOUNTING]. 
     As illustrated in  FIG.  2 B , in Embodiment 1 described above, gap  33  inside bonding metal layer  30  is a continuous void, but this is not limiting. 
     For example, as illustrated in  FIG.  14 A , gap  33 A inside bonding metal layer  30  may include a plurality of voids  33   a  in the form of dots (spots). Specifically, gap  33 A may include first direction void L 1  made up of a plurality of voids  33   a  arranged linearly along a first direction (for example, the row direction). In  FIG.  14 A , first direction void L 1  is made up of the plurality of voids  33   a  arranged in a straight line. In this case, the plurality of voids  33   a  included in gap  33 B may have different shapes, as illustrated in  FIG.  14 B . For example, the plurality of voids  33   a  are not required to be continuous; each of the plurality of voids  33   a  may be partially in the form of a line, a dot, or the like. 
     Note that in  FIG.  14 A  and  FIG.  14 B , gaps  33 A,  33 B in first direction void L 1  extend linearly along the outer side of first electrode E 1 . Specifically, gaps  33 A,  33 B are in the form of a dashed line and are parallel to one outer side of first electrode E 1 . 
     Alternatively, gap  33 C inside bonding metal layer  30  may have first direction void L 1  that is one continuous void, as illustrated in  FIG.  14 C . Note that also in  FIG.  14 C , gap  33 C extends linearly along the outer side of first electrode E 1 . Specifically, gap  33 C in first direction void L 1  is in the form of a straight line and is parallel to one outer side of first electrode E 1 . Furthermore, an end of gap  33 C may be exposed from the outer side of first electrode E 1 . 
     In Embodiment 1 described above, gap  33  inside bonding metal layer  30  is made up of voids in the form of two orthogonal straight lines, but this is not limiting. For example, gap  33 D inside bonding metal layer  30  may be made up of two or more orthogonal straight lines, as illustrated in  FIG.  14 D . Specifically, gap  33 D may include: first direction void L 1  formed linearly along the first direction; and second direction void L 2  formed linearly along a second direction (for example, the column direction) different from the first direction. In  FIG.  14 D , first direction void L 1  is in the form of a straight line along the first direction, and second direction void L 2  is in the form of a straight line along the second direction that is orthogonal to the first direction. 
     Also in  FIG.  14 D , gap  33 D extends linearly along the outer side of first electrode E 1 . Specifically, gap  33 D in first direction void L 1  is in the form of a straight line and is parallel to one outer side of first electrode E 1 . Gap  33 D in second direction void L 2  is in the form of a straight line and is parallel to another outer side of first electrode E 1 . 
     Furthermore, in  FIG.  14 D , gap  33 D includes a plurality of lines of gaps at a fixed interval. Specifically, gap  33 D in first direction void L 1  forms two or more lines at a fixed interval. Gap  33 D in second direction void L 2  forms two or more lines at a fixed interval. 
     Although the first direction in first direction void L 1  and the second direction in second direction void L 2  are orthogonal in  FIG.  14 D , this is not limiting as long as the first direction and the second direction intersect with each other. In this case, the plurality of voids in the form of straight lines included in first direction void L 1  and the plurality of voids in the form of straight lines included in second direction void L 2  are not required to be all in the same direction (in other words, in parallel), but some of the plurality of voids in the form of straight lines may extend in a different direction. 
     Furthermore, in  FIG.  14 D , gap  33 D is made up of the plurality of voids formed along both the first and second directions, but this is not limiting. For example, gap  33 E may be made up of a plurality of voids formed along only one of the first and second directions, as illustrated in  FIG.  14 E . 
     Furthermore, as in  FIG.  14 C , an end of gap  33 D may be exposed from the outer side of first electrode E 1 . All the ends of gap  33 D may be exposed from the outer side of first electrode E 1 , or some of the ends of gap  33 D may be exposed from the outer side of first electrode E 1 . 
     In  FIG.  14 E , gap  33 E includes only first direction void L 1  made up of voids in the form of straight lines extending in the first direction. In this case, a portion of gap  33 E may include a plurality of voids  33   a  having a width different from the width of a straight portion, as illustrated in  FIG.  14 E . In other words, the voids in the form of straight lines may include a portion having a different width. 
     Note that also in  FIG.  14 E , gap  33 E extends linearly along the outer side of first electrode E 1 . Specifically, gap  33 E in first direction void L 1  is in the form of a straight line and is parallel to one outer side of first electrode E 1 . Furthermore, also in  FIG.  14 E , gap  33 E includes a plurality of lines of gaps at a fixed interval. Specifically, gap  33 E in first direction void L 1  forms two or more lines at a fixed interval. Furthermore, as in  FIG.  14 D , an end of gap  33 E may be exposed from the outer side of first electrode E 1 . All the ends of gap  33 E may be exposed from the outer side of first electrode E 1 , or some of the ends of gap  33 E may be exposed from the outer side of first electrode E 1 . 
     In  FIG.  14 D  and  FIG.  14 E , gaps  33 D,  33 E are a combination of voids in the form of straight lines, but this is not limiting. For example, gap  33 F may be made up of a plurality of voids  33   a  aligned in the form of dots, as illustrated in  FIG.  14 F . Specifically, gap  33 F may include: first direction void L 1  made up of a plurality of voids  33   a  arranged linearly along the first direction; and second direction void L 2  made up of a plurality of voids  33   a  arranged linearly along the second direction that is orthogonal to the first direction. In  FIG.  14 F , each of first direction void L 1  and second direction void L 2  is made up of the plurality of voids  33   a  arranged in a straight line. 
     Note that also in  FIG.  14 F , gap  33 F extends linearly along the outer side of first electrode E 1 . Specifically, gap  33 F in first direction void L 1  is in the form of a straight line and is parallel to one outer side of first electrode E 1 . Gap  33 F in second direction void L 2  is in the form of a straight line and is parallel to another outer side of first electrode E 1 . Furthermore, also in  FIG.  14 F , gap  33 F includes a plurality of lines of gaps at a fixed interval. Specifically, gap  33 F in first direction void L 1  forms two or more lines at a fixed interval. Gap  33 F in second direction void L 2  forms two or more lines at a fixed interval. 
     As to gap  33 F illustrated in  FIG.  14 F , the plurality of lines of first line voids L 1  and the plurality of lines of second line voids L 2  are each present at the fixed interval, but this is not limiting; only either the plurality of rows of first line voids L 1  or the plurality of columns of second line voids L 2  may be present at the fixed interval, as with gap  33 G illustrated in  FIG.  14 G . Note that in the case of gap  33 G illustrated in  FIG.  14 G , only the plurality of lines of first direction voids L 1  are present at the fixed interval. 
     All the plurality of voids  33   a  included in gap  33 F are in the form of dots as illustrated in  FIG.  14 F , but this is not limiting; the plurality of voids  33   a  included in gap  33 H may have different shape, as illustrated in  FIG.  14 H . For example, the plurality of voids  33   a  are not required to be continuous; each of the plurality of voids  33   a  may be partially in the form of a line, a dot, or the like. 
     Bonding metal layer  30  according to Embodiment 1 described above is formed by deforming and integrating the plurality of metal bumps  30 Y each in the shape of a rectangular prism, as illustrated in  FIG.  2 B , but this is not limiting. 
     For example, bonding metal layer  30  may be formed by deforming and integrating the plurality of metal bumps  30 Y each in the shape of a circular column, as illustrated in  FIG.  14 I  to  FIG.  14 M . Specifically, bonding metal layer  30  in  FIG.  14 I  to  FIG.  14 K  is formed by deforming and integrating the plurality of metal bumps  30 Y each in the shape of a circular column and aligned in a grid pattern. As one example, metal bump  30 Y in the shape of a circular column is formed of a gold-plated film in the shape of a circle having a diameter of 25 µm as seen from the top with a height of 8 µm. 
     In this case, gap  33 I may be made up of voids in a grid pattern of two orthogonal straight lines, as illustrated in  FIG.  14 I . Note that also in  FIG.  14 I , gap  33 I extends linearly along the outer side of first electrode E 1 . Specifically, gap  33 I in first direction void L 1  is in the form of a straight line and is parallel to one outer side of first electrode E 1 . Gap  33 I in second direction void L 2  is in the form of a straight line and is parallel to another outer side of first electrode E 1 . 
     Gap  33 J may be made up of a plurality of voids, as illustrated in  FIG.  14 J . Note that also in  FIG.  14 J , gap  33 J extends linearly along the outer side of first electrode E 1 . Specifically, gap  33 I in first direction void L 1  is in the form of a straight line and is parallel to one outer side of first electrode E 1 . Gap  33 J in second direction void L 2  is in the form of a plurality of dots and is parallel to another outer side of first electrode E 1 . 
     Gap  33 K may be made up of voids  33   a  in the form of a plurality of dots aligned in a matrix, as illustrated in  FIG.  14 K . Note that also in  FIG.  14 K , gap  33 K extends linearly along the outer side of first electrode E 1 . Specifically, in  FIG.  14 K , first direction gap L 1  and second direction gap L 2  are made up of the plurality of voids  33   a  arranged in the form of a dashed line. Gap  33 K in first direction void L 1  is parallel to one outer side of first electrode E 1 , and gap  33 K in second direction void L 2  is parallel to another outer side of first electrode E 1 . 
     Bonding metal layer  30  may be formed by deforming and integrating the plurality of metal bumps  30 Y each in the shape of a circular column and aligned in a staggered pattern, as illustrated in  FIG.  14 L  and  FIG.  14 M . 
     In this case, gap  33 L may be made up of voids in a staggered grid pattern, as illustrated in  FIG.  14 L . Note that also in  FIG.  14 L , gap  33 L extends linearly along the outer side of first electrode E 1 . Specifically, gap  33 L in first direction void L 1  is in the form of a straight line and is parallel to one outer side of first electrode E 1 . Gap  33 L in second direction void L 2  is in the form of a dashed line and is parallel to another outer side of first electrode E 1 . 
     Gap  33 M may be made up of voids  33   a  in the form of a plurality of dots aligned in a matrix, as illustrated in  FIG.  14 M . Note that also in  FIG.  14 M , gap  33 M extends linearly along the outer side of first electrode E 1 . Specifically, in  FIG.  14 M , first direction gap L 1  and second direction gap L 2  are made up of the plurality of voids  33   a  arranged in the form of a dashed line. Gap  33 M in first direction void L 1  is parallel to one outer side of first electrode E 1 , and gap  33 M in second direction void L 2  is parallel to another outer side of first electrode E 1 . 
     In  FIG.  14 I  and  FIG.  14 M , bonding metal layer  30  is formed by deforming and integrating the plurality of metal bumps  30 Y each in the shape of a circular column, but this is not limiting. 
     For example, bonding metal layer  30  may be formed by deforming and integrating the plurality of metal bumps  30 Y each in the shape of a hexagonal column, as illustrated in  FIG.  14 N  and  FIG.  140   . Specifically, bonding metal layer  30  in  FIG.  14 N  and  FIG.  140    is formed by deforming and integrating the plurality of metal bumps  30 Y each in the shape of a hexagonal column and aligned in a staggered pattern. 
     In this case, gap  33 N may be made up of voids in a staggered grid pattern, as illustrated in  FIG.  14 N . Note that also in  FIG.  14 N , gap  33 N extends linearly along the outer side of first electrode E 1 . Specifically, gap  33 N in first direction void L 1  is in the form of a dashed line and is parallel to one outer side of first electrode E 1 . 
     Gap  330  may be made up of voids  33   a  in the form of a plurality of dots, as illustrated in  FIG.  140   . Note that also in  FIG.  140   , gap  330  extends linearly along the outer side of first electrode E 1 . Specifically, first direction gap L 1  is made up of the plurality of voids  33   a  arranged in the form of a dashed line. Gap  330  in first direction void L 1  is parallel to one outer side of first electrode E 1 . 
     Note that also in  FIG.  14 I  to  FIG.  140   , gap  33 I to gap  330  include a plurality of lines of gaps at a fixed interval. Specifically, gap  33 I to gap  330  in at least one of first direction void L 1  and second direction void L 2  form two or more lines at a fixed interval. 
     Thus, when gap  33 D to gap  330  are parallel to the outer side of first electrode E 1  and form two or more lines at a fixed interval, as illustrated in  FIG.  14 D  to  FIG.  140   , it is considered that metal bumps  30 Y having the same shape have been arranged neatly in a repeating pattern. In addition, when metal bumps  30 Y having the same shape are arranged neatly in a repeating pattern, the load for mounting that is placed on the entire surface of each of first electrode E 1  and second electrode E 2  can be evenly distributed as compared to the case where metal bumps  30 Y having different shapes are arranged. Accordingly, localized stress that metal bumps  30 Y give to first electrode E 1  and second electrode E 2  can be made small, and thus it is possible to reduce damage to first electrode E 1  and second electrode E 2  that may be caused by metal bumps  30 Y. 
     As described above, with semiconductor device  1  according to the present embodiment, for example, in the case of applying a plating bump technique with high design flexibility for the thickness and the bonding area, it is possible to lessen damage to first electrode E 1  of semiconductor element  10  and second electrode E 2  of mounting substrate  20  at the time of mounting semiconductor element  10  on mounting substrate  20  by flip-chip bonding. This makes it possible to reduce mounting damage including electrode failures such as damage or peeling of first electrode E 1  and second electrode E 2  at the time of mounting semiconductor element  10  on mounting substrate  20 . Thus, semiconductor device  1  exceptionally reliable in the long run can be obtained. 
     Note that such semiconductor device  1  exceptionally reliable in the long run is suitable as a compact, highly integrated vehicle-mounted light source with large electric current. 
     Embodiment 2 
     Next, semiconductor device  2  according to Embodiment 2 will be described with reference to  FIG.  15   .  FIG.  15    is a cross-sectional view illustrating the configurations of semiconductor device  2  according to Embodiment 2 before and after mounting. In  FIG.  15 , ( a )  is a cross-sectional view in which semiconductor element  10  has not yet been mounted on mounting substrate  20 , and (b) is a cross-sectional view in which semiconductor element  10  has already been mounted on mounting substrate  20 . In (a) and (b) in  FIG.  15   , the left diagram is a cross-sectional view taken along line X-X in the right diagram. 
     As illustrated in  FIG.  2 B , in semiconductor device  1  according to Embodiment 1 described above, the outer side of first electrode E 1  of semiconductor element  10  is a straight line only, but, as illustrated in  FIG.  15   , in semiconductor device  2  according to the present embodiment, the outer side of first electrode E 1  of semiconductor element  10  at least partially includes a curved section. 
     Specifically, in semiconductor device  2  according to the present embodiment, the outer side of first p-side electrode  12  includes arc-shaped curved sections at four corners, and the outer sides of four island-shaped first n-side electrodes  13  on the first p-side electrode  12  side include arc-shaped curved sections. 
     With the outer side of first electrode E 1  being bent in a curve as mentioned above, electric field concentration can be less than that with first electrode E 1  being bent at a right angle. Accordingly, electric current concentration can be reduced. 
     Furthermore, in semiconductor device  2  according to the present embodiment, at the time of mounting semiconductor element  10  having the plurality of metal bumps  30 Y formed thereon on mounting substrate  20 , the plurality of metal bumps  30 Y are deformed and integrated to form bonding metal layer  30  including gap  33  inside, as in semiconductor device  1  according to Embodiment 1 described above. 
     With this, it is possible to evenly distribute the load for mounting that is placed on first electrode E 1  of semiconductor element  10  and second electrode E 2  of mounting substrate  20 , and thus localized stress that metal bumps  30 Y give to first electrode E 1  and second electrode E 2  at the time of mounting can be made small. As a result, it is possible to reduce damage to first electrode E 1  and second electrode E 2  that may be caused by metal bumps  30 Y. Accordingly, with semiconductor device  2  according to the present embodiment, mounting damage due to electrode failures of first electrode E 1  and second electrode E 2  can be reduced; therefore, it is possible to provide semiconductor device  2   exceptionally reliable in the long run. 
     Furthermore, the pattern of gap  33  according to the present embodiment can improve heat dissipation properties. This point will be described below with reference to  FIG.  16   .  FIG.  16    is an enlarged view of the M cross section in (b) in  FIG.  15   . 
     As illustrated in  FIG.  16   , in semiconductor device  2  according to the present embodiment, the proportion of the area taken up by gap  33  in a plan view is lower in a region close to p-n electrode opposed portion PN across which first p-side electrode  12  and first n-side electrode  13  are opposed to each other than in a region away from p-n electrode opposed portion PN. The region close to p-n electrode opposed portion PN is a region located at distance D of between 50 µm and 100 µm, inclusive, from p-n electrode opposed portion PN in the present embodiment. 
     The amount of heat generated at p-n electrode opposed portion PN is largest; with p-n electrode opposed portion PN as a reference, a region located at distance D of between 50 µm and 100 µm, inclusive, from p-n electrode opposed portion PN becomes a heat-concentrated region. 
     Here, what is meant by gap  33  in a region close to p-n electrode opposed portion PN having a low area proportion is that metal bump  30 Y present in the region close to p-n electrode opposed portion PN, which becomes a heat-concentrated region, is large in size, resulting in high heat conduction. 
     Thus, with the proportion of the area taken up by gap  33  being lower in a region close to p-n electrode opposed portion PN than in a region away from p-n electrode opposed portion PN, it is possible to obtain semiconductor device  2  having superior heat dissipation properties. 
     Note that in the present embodiment, gap  33  inside bonding metal layer  30  is a combination of voids in the form of straight lines, but this is not limiting. For example, gap  33  may be made up of a plurality of voids  33   a  aligned in the form of dots, as illustrated in  FIG.  17   . Gap  33  illustrated in  FIG.  17    is formed by deforming metal bumps  30 Y more heavily than when forming gap  33  illustrated in  FIG.  16   . Specifically, even in the case where a gap between adjacent metal bumps  30 Y is linear before mounting, when metal bumps  30 Y are deformed intentionally heavily or ended up being deformed too much, gap  33  may be formed into the shape of a dot instead of a line. 
     Furthermore, in the present embodiment, first electrode E 1  includes four first n-side electrodes  13  in the form of islands, but this is not limiting. For example, first n-side electrode  13  may be provided along the entire perimeter of the electrode forming surface of semiconductor element  10  so as to surround entire first p-side electrode  12 , as illustrated in  FIG.  18   . Note that first n-side electrode  13  in such a pattern may be used in another embodiment. 
     Variation of Embodiment 2 
     Next, semiconductor device  2 A according to a variation of Embodiment 2 will be described with reference to  FIG.  19   .  FIG.  19    is a cross-sectional view illustrating semiconductor device  2 A according to the variation of Embodiment 2. In  FIG.  19   , (a) is a cross-sectional view in which semiconductor element  10  has not yet been mounted on mounting substrate  20 , and (b) is a cross-sectional view in which semiconductor element  10  has already been mounted on mounting substrate  20 . In (a) and (b) in  FIG.  19   , the left diagram is a cross-sectional view taken along line X-X in the right diagram. 
     As illustrated in  FIG.  19   , in semiconductor device  2 A according to the present variation, the outer side of first electrode E 1  of semiconductor element  10  at least partially includes a curved section, as in semiconductor device  2  illustrated in  FIG.  15   . 
     Furthermore, in semiconductor device  2 A according to the present variation, gap  33  inside bonding metal layer  30  extends linearly along the outer side of first electrode E 1  in a plan view of bonding metal layer  30 . Specifically, gap  33  is in the form of an arc-shaped curve and extends along the curved section provided on the outer side at a corner of first p-side electrode  12 . 
     Thus, when gap  33  of bonding metal layer  30  extends along the outer side of first electrode E 1  of semiconductor element  10 , it is considered that the plurality of metal bumps  30 Y, which become bonding metal layer  30 , have been arranged neatly before mounting. When metal bumps  30 Y are arranged neatly, the load for mounting that is placed on the entire surface of each of first electrode E 1  and second electrode E 2  can be evenly distributed as compared to the case where metal bumps  30 Y are arranged at random. Accordingly, localized stress that metal bumps  30 Y give to first electrode E 1  and second electrode E 2  can be made small, and thus it is possible to reduce damage to first electrode E 1  and second electrode E 2  that may be caused by metal bumps  30 Y. Thus, semiconductor device  2 A exceptionally reliable in the long run can be obtained. 
     Embodiment 3 
     Next, semiconductor device  3  according to Embodiment 3 will be described with reference to  FIG.  20   .  FIG.  20    is a cross-sectional view illustrating the configurations of semiconductor device  3  according to Embodiment 3 before and after mounting. In  FIG.  20   , (a) is a cross-sectional view in which semiconductor element  10  has not yet been mounted on mounting substrate  20 , and (b) is a cross-sectional view in which semiconductor element  10  has already been mounted on mounting substrate  20 . In (a) and (b) in  FIG.  20   , the left diagram is a cross-sectional view taken along line X-X in the right diagram. 
     Semiconductor device  3  according to the present embodiment is different from semiconductor device  2  according to Embodiment 2 described above in that gap  33  inside bonding metal layer  30  has a different shape in a plan view. Specifically, in semiconductor device  3  according to the present embodiment, gap  33  is at least partially radial in shape in a plan view of bonding metal layer  30 . 
     Specifically, as illustrated in the M cross section in  FIG.  20   , gap  33  is made up of a plurality of voids in the form of straight lines radially extending from a center portion of one side of first p-side electrode  12  of first electrode E 1  toward the opposite side. 
     As described above, in semiconductor device  3  according to the present embodiment, at the time of mounting semiconductor element  10  having the plurality of metal bumps  30 Y formed thereon on mounting substrate  20 , bonding metal layer  30  is formed by deforming the plurality of metal bumps  30 Y so as to include gap  33  inside, as in semiconductor device  2  according to Embodiment 2 described above. Accordingly, mounting damage due to electrode failures of first electrode E 1  and second electrode E 2  can be reduced; therefore, it is possible to provide semiconductor device  3  exceptionally reliable in the long run. 
     Furthermore, in semiconductor device  3  according to the present embodiment, gap  33  is at least partially radial in shape. With this, at the time of sealing entire semiconductor device  30  using resin, gap  33  can be easily filled with the resin. This means that gap  33  may be at least partially filled with resin  34  as in semiconductor device  3 A illustrated in  FIG.  21   . 
     Specifically, since gap  33  is made up of radial voids, when drops of resin  34  in the form of liquid are supplied around semiconductor device  3  to fill the space between semiconductor element  10  and mounting substrate  20  with resin  34  after semiconductor device  10  is mounted on mounting substrate  20 , the supplied drops of resin  34  infiltrate into gap  33  radially from one point at which ends of the plurality of radial voids are gathered. Thus, the distance of infiltration of resin  34  can be made shortest, meaning that the occurrence of incomplete filling of gap  33  with resin  34  can be reduced and all the voids included in gap  33  can be easily filled with resin  34 , as in semiconductor device  3 A illustrated in  FIG.  21   . Note that after drops of resin  34  in form of liquid are supplied, resin  34  can be thermally cured, for example, by one-hour heating at 150° C. 
     Resin  34  which fills gap  33  may have thermal conductivity higher than the thermal conductivity of air. For example, a silicone rein can be used a resin  34 . Furthermore, microparticles having high thermal conductivity or light-reflective microparticles may be dispersed in resin  34 . For example, titanium oxide (TiO 2 ) microparticles can be used as light-reflective microparticles having high thermal conductivity. 
     In this manner, it is possible to improve the heat dissipation properties of semiconductor device  3  by filling gap  33  with resin  34 . Thus, semiconductor device  3  more exceptionally reliable in the long run can be obtained. 
     Note that in  FIG.  20    and  FIG.  21   , gap  33  is made up of the plurality of voids in the form of straight lines radially extending from the center portion of one side of first p-side electrode  12 , but this is not limiting. 
     For example, gap  33  may be made up of a plurality of voids in the form of straight lines radially extending in every direction from the center portion of first p-side electrode  12 , as illustrated in  FIG.  22   . Regarding the pattern of gap  33  illustrated in  FIG.  22   , as in semiconductor device  2  illustrated in  FIG.  15   , the proportion of the area taken up by gap  33  is lower in a region close to p-n electrode opposed portion PN than in a region away from p-n electrode opposed portion PN. With this, it is possible to improve heat dissipation properties, and thus semiconductor device  3  yet more exceptionally reliable in the long run can be obtained. 
     Furthermore, as illustrated in  FIG.  23   , gap  33  may include a void branching from a portion of a plurality of radially extending voids or some or all of the plurality of radially extending voids in gap  33  may be curved. 
     Variations 
     Although the semiconductor devices according to the present disclosure have been described based on Embodiments 1 to 3, the present disclosure is not limited to the above-described embodiments. 
     For example, in each of the above embodiments, first electrode E 1  of semiconductor element  10  is configured in such a manner that the electrode area of first p-side electrode  12  is larger than the electrode area of first n-side electrode  13 , but this is not limiting. Specifically, the electrode area of first n-side electrode  13  may be larger than the electrode area of first p-side electrode  12 . However, in the case where semiconductor element  10  is a LED chip, the p-side tends to have a higher temperature than the n-side, and thus the electrode area of first p-side electrode  12  may be set larger than the electrode area of first n-side electrode  13 . 
     Furthermore, in each of the above embodiments, gap  33  formed inside bonding metal layer  30  is present in only first bonding metal layer  31  among first bonding metal layer  31  and second bonding metal layer  32 , but this is not limiting. For example, gap  33  may be present in both first bonding metal layer  31  and second bonding metal layer  32  or may be present in only second bonding metal layer  32  among first bonding metal layer  31  and second bonding metal layer  32 . In this case, regarding the plurality of metal bumps  30 Y for forming gap  33 , the plurality of metal bumps  30 Y may be provided on only the p side as in each of the above embodiments, but the plurality of metal bumps  30 Y may be provided on both the n side and the p side or may be provided on only the n side. 
     Furthermore, in each of the above embodiments, the shape, the number, etc., of gaps  33 ,  33 A to  330  are not particularly limited. Moreover, the vertical positions of gaps  33 ,  33 A to  330  are not particularly limited. For example, in the case where the gap is made up of a plurality of voids aligned in the form of dots in a plan view, the voids in each place may be in layers in the thickness direction of bonding metal layer  30 . 
     Furthermore, although the LED chip is exemplified as semiconductor element  10  in each of the above embodiments, this is not limiting; other solid-state light-emitting elements such as a laser element may be used. In addition, semiconductor element  10  is not limited to a light-emitting element. For example, semiconductor element  10  may be a power semiconductor element such as a compound field effect transistor using GaN, SiC, or the like. 
     Note that forms obtained by various modifications to the above-described embodiments that can be conceived by a person of skill in the art as well as forms realized by arbitrarily combining structural elements and functions in the embodiments which are within the scope of the essence of the present disclosure are included in the present disclosure. 
     INDUSTRIAL APPLICABILITY 
     The semiconductor device according to the present disclosure is exceptionally reliable in the long run and is useful for various devices including vehicle-mounted application.