Patent Publication Number: US-2023147947-A1

Title: Systems and Methods for Measurement of a Parameter of a DUT

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application is a continuation-in-part of U.S. patent application Ser. No. 17/124,580, entitled “Systems and Methods for Duty Cycle Measurement,” filed Dec. 17, 2020, which claims priority from U.S. Provisional Application No. 62/982,176, filed Feb. 27, 2020, entitled “All Digital Solution for Duty-Cycle Measurement and Process Indicator.” This application further claims priority from U.S. Provisional Application No. 6/407,232, filed Sep. 16, 2022. All of these are incorporated herein by reference in their entireties. 
    
    
     BACKGROUND 
     Duty cycle refers to the percentage of time that a periodic digital signal exhibits a high state during a full signal cycle or period. For example, a signal that exhibits a logic high state for 50% of the signal period has a 50% duty cycle. Similarly, for instance, a signal that exhibits a logic high state for 40% of a signal period has a 40% duty cycle. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It should be noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. 
         FIG.  1    depicts a block diagram of a circuit for determining a duty cycle of a periodic input signal, in accordance with some embodiments. 
         FIG.  2 A  depicts a first waveform representative of a periodic input signal and a second waveform representative of an output of a divider circuit, in accordance with some embodiments. 
         FIG.  2 B  depicts a first waveform representative of a periodic input signal and a second waveform representative of an output of an inverter circuit, in accordance with some embodiments. 
         FIG.  2 C  depicts a first waveform representative of an inverted version of a periodic input signal and a second waveform representative of an inverted version of the first waveform, in accordance with some embodiments. 
         FIG.  3    depicts a schematic diagram of a circuit for determining a duty cycle of a periodic input signal, in accordance with some embodiments. 
         FIG.  4    depicts a schematic diagram illustrating a pattern generator module with selection module and 2-bit counter used to measure high, low, and full periods of a periodic input signal, in accordance with some embodiments. 
         FIG.  5    depicts a schematic diagram illustrating a data strobe and period calculation module, in accordance with some embodiments. 
         FIG.  6    depicts a timing diagram illustrating a measurement of high, low, and full periods of a periodic input signal, in accordance with some embodiments. 
         FIG.  7    depicts operations of an example method for determining a duty cycle of a periodic input signal, in accordance with some embodiments. 
         FIG.  8    depicts waveforms representative of a clock input signal, a data input signal, and a data output signal when a device under test (DUT) is in a stable state, in accordance with some embodiments. 
         FIG.  9    depicts waveforms representative of a clock input signal, a data input signal, and a data output signal when a DUT is in a metastable state, in accordance with some embodiments 
         FIG.  10    depicts a block diagram of a circuit for facilitating measurement of a parameter of a DUT, in accordance with some embodiments. 
         FIG.  11    depicts a schematic diagram of a circuit for facilitating measurement of a parameter of a DUT, in accordance with some embodiments. 
         FIG.  12    depicts a metastability window of a DUT, in accordance with some embodiments. 
         FIG.  13    depicts a metastability window of a DUT, in accordance with some embodiments. 
         FIG.  14    depicts operations of an example method for facilitating measurement of a parameter of a DUT, in accordance with some embodiments. 
         FIG.  15    depicts a block diagram of a circuit for facilitating measurement of a parameter of a DUT, in accordance with some embodiments. 
         FIG.  16    depicts a schematic diagram of a circuit for facilitating measurement of a parameter of a DUT, in accordance with some embodiments. 
         FIG.  17    depicts a metastability window of a DUT, in accordance with some embodiments. 
         FIG.  18    depicts a metastability window of a DUT, in accordance with some embodiments. 
         FIG.  19    depicts operations of an example method for facilitating measurement of a parameter of a DUT, in accordance with some embodiments. 
     
    
    
     Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the embodiments and are not necessarily drawn to scale. 
     DETAILED DESCRIPTION 
     The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in some various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between some various embodiments and/or configurations discussed. 
     Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature&#39;s relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. 
     Some embodiments of the disclosure are described. Additional operations can be provided before, during, and/or after the stages described in these embodiments. Some of the stages that are described can be replaced or eliminated for different embodiments. Additional features can be added to the semiconductor device. Some of the features described below can be replaced or eliminated for different embodiments. Although some embodiments are discussed with operations performed in a particular order, these operations may be performed in another logical order. 
     Duty cycle refers to the percentage of time that a periodic digital signal exhibits a high state during a full signal cycle or period. It can be challenging to monitor a relatively fast periodic signal (e.g., a multi-GHz signal) and determine its duty cycle via direct measurements. These challenges may result from bandwidth limitations of test equipment and associated accessories, such as cables. 
     Conventional solutions to determining the duty cycle of a periodic signal are often based in analog technology. In some of the conventional solutions, the periodic signal is converted into a current using an analog circuit, and then the current is converted into a voltage using a low-bandwidth filter or other analog circuitry. The voltage of the signal is measured, and the duty cycle for the periodic signal can be determined based on the measured voltage. A problem with the conventional methods is that the analog circuits used to generate the currents can introduce distortions and inaccuracies into the measurements. These distortions and inaccuracies are especially problematic when the periodic signal is relatively fast (e.g., in the GHz range). The conventional solutions also often require an analog-to-digital converter (ADC) to convert the analog voltages to digital values, which can introduce additional error and inaccuracy into the duty cycle determination. Further, the conventional solutions are also inconvenient because they often require an analog voltage meter to perform the voltage measurements, and such analog voltage meters require additional space and cost. 
     The approaches of the instant disclosure enable the determination of duty cycles of periodic signals in a manner that is more accurate than the conventional solutions. For example, as explained below, the approaches of the instant disclosure account for unknown variables in the duty cycle determination that can otherwise cause inaccuracies in the calculation. In some embodiments, duty cycles are determined using a delay locked loop (DLL) that delays the periodic signal based on digital control words received from digital circuitry. In addition to being more accurate than the conventional solutions, the approaches of the instant disclosure are also more convenient, space-efficient, and cost-effective because they do not require the use of an analog voltage meter and other components that consume circuit space and add additional cost. These advantages and others of the instant disclosure are described in detail below. 
       FIG.  1    is a block diagram of a circuit for determining a duty cycle  116  of a periodic input signal  102 , in accordance with some embodiments. As seen in this figure, the circuit includes a delay circuit  104  that receives the periodic input signal  102 . In some embodiments, the delay circuit  104  includes a DLL as described in further detail below. The delay circuit  104  is configured to delay the periodic input signal  102  based on digital control words received from a digital circuit  110 . Specifically, the delay circuit  104  delays the periodic input signal  102  based on a first digital control word OTW FULL    112   a , a second digital control word OTW HIGH    112   b , and a third digital control word OTW LOW    112   c , as shown in  FIG.  1   . 
     In some embodiments, the digital circuit  110  generates the three distinct digital control words OTW FULL    112   a , OTW HIGH    112   b , and OTW LOW    112   c  that cause the delay circuit  104  to delay the periodic input signal  102  by three different amounts of time. The first digital control word OTW FULL    112   a  generated by the digital circuit  110  causes the delay circuit  104  to delay the periodic input signal  102  by a first amount of time that corresponds to a full period of the periodic input signal  102 . The second digital control word OTW HIGH    112   b  generated by the digital circuit  110  causes the delay circuit  104  to delay the periodic input signal  102  by a second amount of time that corresponds to a portion of the period that the periodic input signal  102  has a logic-level high value. The third digital control word OTW LOW    112   c  generated by the digital circuit  110  causes the delay circuit  104  to delay the periodic input signal  102  by a third amount of time that corresponds to a portion of the period that the periodic input signal  102  has a logic-level low value. 
     A phase detector  108  generates signals that are used by the digital circuit  110  in generating the first digital control word OTW FULL    112   a , the second digital control word OTW HIGH    112   b , and the third digital control word OTW LOW    112   c . Specifically, as seen in  FIG.  1   , the phase detector  108  receives (i) a reference signal  106  that is equivalent to the periodic input signal  102 , and (ii) a delayed version of the periodic input signal  102  from the delay circuit  104 . The phase detector  108  determines when an edge (e.g., a rising edge, a falling edge) of the reference signal  106  is aligned with an edge of the delayed version of the periodic input signal  102  and outputs a signal to the digital circuit  110  that is indicative of the alignment or lack thereof. The digital circuit  110  generates the first digital control word OTW FULL    112   a , the second digital control word OTW HIGH    112   b , and the third digital control word OTW LOW    112   c  based on the signals received from the phase detector  108 . 
     The output of the phase detector  108  thus provides a feedback loop to the digital circuit  110  that enables the digital circuit  110  to modify the first digital control word OTW FULL    112   a , the second digital control word OTW HIGH    112   b , and the third digital control word OTW LOW    112   c  until the periodic input signal  102  has been delayed the correct amount of time. For instance, in generating the first digital control word OTW FULL    112   a , the digital circuit  110  can modify the control word based on feedback from the phase detector  108  until a control word that results in the delay circuit  104  delaying the periodic digital signal  102  by the first amount of time is determined. Likewise, in generating the second digital control word OTW HIGH    112   b , the digital circuit  110  can modify the control word based on feedback from the phase detector  108  until a control word that results in the delay circuit  104  delaying the periodic digital signal  102  by the second amount of time is determined. Similarly, in generating the third digital control word OTW LOW    112   c , the digital circuit  110  can modify the control word based on feedback from the phase detector  108  until a control word that results in the delay circuit  104  delaying the periodic digital signal  102  by the third amount of time is determined. 
     In some embodiments, to generate the first digital control word OTW FULL    112   a  that causes the periodic input signal  102  to be delayed the first amount of time, a divider circuit is utilized.  FIG.  2 A  shows (i) a waveform  1302  representative of the periodic input signal  102 , (ii) a waveform  1303  representative of an output of the divider circuit, where the divider circuit divides the periodic input signal  102  by two (2) to generate the slower waveform  1303 , and (iii) a waveform  1301  representative of an inverted version of the waveform  1303 . In the example of  FIG.  2 A , after one or more cycles, rising edges of the waveform  1301  and the waveform  1303  are aligned, indicating that the periodic input signal  102  has been delayed the first amount of time corresponding to the full period of the periodic input signal  102 . The phase detector  108  of  FIG.  1    detects this alignment of edges and generates an appropriate output signal that is received by the digital circuit  110 . The first digital control word OTW FULL    112   a  is the digital control word that causes the alignment between the edges of waveforms  1301 ,  1303  as seen in  FIG.  2 A . Divider circuits that can be used in generating the waveforms  1301 ,  1302  are described below with reference to  FIG.  3   . 
     In some embodiments, to generate the second digital control word OTW HIGH    112   b  that causes the periodic input signal  102  to be delayed the second amount of time, an inverter circuit is utilized.  FIG.  2 B  shows (i) a waveform  1102  representative of the periodic input signal  102 , and (ii) a waveform  1101  representative of an output of the inverter circuit, where the inverter circuit inverts the periodic input signal  102  to generate the waveform  1101 . As further shown in  FIG.  2 B , after one or more cycles, rising edges of the waveform  1102  and the waveform  1101  are aligned, indicating that the periodic input signal  102  has been delayed the second amount of time corresponding to the portion of the periodic input signal  102  that has the logic-level high value. The phase detector  108  of  FIG.  1    detects this alignment of edges and generates an appropriate output signal that is received by the digital circuit  110 . The second digital control word OTW HIGH    112   b  is the digital control word that causes the alignment between the waveforms  1101 ,  1102  as seen in  FIG.  2 B . Inverter circuits that can be used in generating the waveform  1101  are described below with reference to  FIG.  3   . 
     In some embodiments, to generate the third digital control word OTW LOW    112   c  that causes the periodic input signal  102  to be delayed the third amount of time, multiple inverter circuits are utilized.  FIG.  2 C  shows (i) a waveform  1202  representative of an inverted version of the periodic input signal  102 , and (ii) a waveform  1201  representative of an inverted version of the waveform  1202 . As further shown in  FIG.  2 C , after one or more cycles, rising edges of the waveform  1201  and the waveform  1202  are aligned, indicating that the periodic input signal  102  has been delayed the third amount of time corresponding to the portion of the periodic input signal  102  having the logic-level low value. The phase detector  108  of  FIG.  1    detects this alignment of edges and generates an appropriate output signal that is received by the digital circuit  110 . The third digital control word OTW LOW    112   c  is the digital control word that causes the alignment between the waveforms  1201 ,  1202  seen in  FIG.  2 C . Inverter circuits that can be used in generating the waveforms  1201 ,  1202  are described below with reference to  FIG.  3   . 
     With reference again to  FIG.  1   , a controller  114  receives the first digital control word OTW FULL    112   a , the second digital control word OTW HIGH    112   b , and the third digital control word OTW LOW    112   c  and determines the duty cycle  116  of the periodic input signal  102  based on these three digital control words. Specifically, in some embodiments, the controller  114  determines the duty cycle  116  by solving Equation 1: 
     
       
         
           
             
               
                 
                   
                     
                       
                         O 
                         ⁢ 
                         T 
                         ⁢ 
                         
                           W 
                           FULL 
                         
                       
                       - 
                       
                         O 
                         ⁢ 
                         T 
                         ⁢ 
                         
                           W 
                           
                             L 
                             ⁢ 
                             O 
                             ⁢ 
                             W 
                           
                         
                       
                     
                     
                       
                         2 
                         × 
                         O 
                         ⁢ 
                         T 
                         ⁢ 
                         
                           W 
                           FULL 
                         
                       
                       - 
                       
                         O 
                         ⁢ 
                         T 
                         ⁢ 
                         
                           W 
                           HIGH 
                         
                       
                       - 
                       
                         O 
                         ⁢ 
                         T 
                         ⁢ 
                         
                           W 
                           
                             L 
                             ⁢ 
                             O 
                             ⁢ 
                             W 
                           
                         
                       
                     
                   
                   , 
                 
               
               
                 
                   ( 
                   
                     Equation 
                     ⁢ 
                         
                     1 
                   
                   ) 
                 
               
             
           
         
       
     
     where OTW FULL  is the first digital control word  112   a , OTW HIGH  is the second digital control word  112   b , and OTW LOW  is the third digital control word  112   c.    
     In some embodiments, the delay circuit  104  is configured to delay the periodic input signal  102  in accordance with a step size ΔT representing a minimum incremental amount of delay that can be applied by the delay circuit  104 . The step size ΔT of a delay circuit (e.g., a DLL-based delay circuit, as described herein) is generally an unknown value that cannot be controlled in the fabrication process. However, in embodiments of the present disclosure, the controller  114  is configured to determine the step size ΔT of the delay circuit  104  based on the duty cycle  116  and the digital control words OTW FULL    112   a , OTW HIGH    112   b , and OTW LOW    112   c . Specifically, in some embodiments, the controller determines the step size ΔT by solving Equation 2: 
     
       
         
           
             
               
                 
                   
                     1 
                     
                       
                         F 
                         DUT 
                       
                       × 
                       
                         ( 
                         
                           
                             2 
                             × 
                             O 
                             ⁢ 
                             T 
                             ⁢ 
                             
                               W 
                               FULL 
                             
                           
                           - 
                           
                             O 
                             ⁢ 
                             T 
                             ⁢ 
                             
                               W 
                               HIGH 
                             
                           
                           - 
                           
                             O 
                             ⁢ 
                             T 
                             ⁢ 
                             
                               W 
                               
                                 L 
                                 ⁢ 
                                 O 
                                 ⁢ 
                                 W 
                               
                             
                           
                         
                         ) 
                       
                     
                   
                   , 
                 
               
               
                 
                   ( 
                   
                     Equation 
                     ⁢ 
                         
                     2 
                   
                   ) 
                 
               
             
           
         
       
     
     where F DUT  represents a frequency corresponding to the duty cycle (e.g., the duty cycle divided by the pulse width of the periodic input signal  102 ), OTW FULL  represents the first digital tuning word  112   a , OTW HIGH  represents the second digital tuning word  112   b , and OTW LOW  represents the third digital tuning word  112   c . The step size ΔT determined by solving Equation 2 may provide useful process information (e.g., the step size ΔT may serve as a process indicator indicative of one or more processes used in forming the component for which a duty cycle is being measured). 
     Equations 1 and 2, used by the controller  114  in calculating the duty cycle  116  and step size ΔT, respectively, can be determined as follows. As explained above, the first digital control word OTW FULL    112   a  causes the delay circuit  104  to delay the periodic input signal  102  the first amount of time corresponding to the full period of the periodic input signal  102 . The relationship between the first amount of time and the first digital control word OTW FULL    112   a  can be represented by Equation 3: 
       Full=intr dly +(Δ T )( OTW   FULL ),  (Equation 3)
 
     where Full is the first amount of time, intr dly  is an intrinsic delay of the delay circuit  104 , OTW FULL  is the first digital control word  112   a , and ΔT is the step size described above. In embodiments where the delay circuit  104  uses a delay train or other types of delay elements (e.g., delay elements containing logic gates, etc.), the intr dly  term represents the intrinsic delay of such delay elements. The intrinsic delay intr dly  and the step size ΔT are both non-controllable, unknown parameters in silicon. In order to accurately calculate the duty cycle  116 , embodiments of the present disclosure remove the intr dly  and ΔT terms via mathematical manipulation, as described below. 
     The second digital control word OTW HIGH    112   b  causes the delay circuit  104  to delay the periodic input signal  102  the second amount of time corresponding to the portion of the period that the periodic input signal  102  has a logic-level high value, as explained above. The relationship between the second amount of time and the second digital control word OTW HIGH  can be represented by Equation 4: 
         Hi =intr dly +(Δ T )( OTW   HIGH ),  (Equation 4)
 
     where Hi is the second amount of time, intr dly  is the intrinsic delay of the delay circuit  104 , OTW HIGH  is the second digital control word  112   b , and ΔT is the step size described above. 
     The third digital control word OTW LOW    112   c  causes the delay circuit  104  to delay the periodic input signal  102  the third amount of time corresponding to the portion of the period that the periodic input signal  102  has a logic-level low value. The relationship between the third amount of time and the third digital control word OTW LOW  can be represented by Equation 5: 
         Lo =intr dly +(Δ T )( OTW   LOW )  (Equation 5)
 
     where Lo is the third amount of time, intr dly  is the intrinsic delay of the delay circuit  104 , OTW LOW  is the third digital control word  112   c , and ΔT is the step size as described above. 
     The intr dly  term can be removed by manipulating Equations 3-5 using subtraction operations: 
         Hi ′=Full− Lo =(Δ T )( OTW   FULL   −OTW   LOW ),  (Equation 6)
 
         Lo ′=Full− Hi =(Δ T )( OTW   FULL   −OTW   HIGH ),  (Equation 7)
 
       Full′= Hi′+Lo ′=(Δ T )((2* OTW   FULL )− OTW   HIGH   −OTW   LOW ),  (Equation 8)
 
     As seen above, Equation 8 represents the first amount of time (i.e., an amount of time equal to a full period of the periodic input signal  102 ) but does not depend on the intrinsic delay term intr dly . Likewise, Equations 6 and 7 represent the second and third amounts of time, respectively, but do not depend on the intrinsic delay term intr dly . Accordingly, Equations 6-8 show that the intrinsic delay term intr dly  has been removed by mathematical manipulation. Further, with the intrinsic delay term intr dly  removed, Equations 6-8 are free of process, voltage, and temperature (PVT) artifact fluctuations. 
     Equation 1, used in calculating the duty cycle  116 , can be derived by dividing Equation 6 by Equation 8: 
     
       
         
           
             
               
                 
                   Duty 
                   = 
                   
                     
                       
                         Hi 
                         ′ 
                       
                       
                         Full 
                         ′ 
                       
                     
                     = 
                     
                       
                         
                           OTW 
                           FULL 
                         
                         - 
                         
                           OTW 
                           
                             L 
                             ⁢ 
                             O 
                             ⁢ 
                             W 
                           
                         
                       
                       
                         
                           2 
                           × 
                           
                             OTW 
                             
                               F 
                               ⁢ 
                               U 
                               ⁢ 
                               L 
                               ⁢ 
                               L 
                             
                           
                         
                         - 
                         
                           OTW 
                           HIGH 
                         
                         - 
                         
                           OTW 
                           LOW 
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   
                     Equation 
                     ⁢ 
                         
                     9 
                   
                   ) 
                 
               
             
           
         
       
     
     As seen above, by dividing the equations for Hi′ by Full′, the step size term ΔT is removed via the division operation. This is evident from Equation 1, above, which enables the calculation of the duty cycle  116  using only the digital control words OTW FULL    112   a , OTW HIGH    112   b , and OTW LOW    112   c , and does not depend on the step size term ΔT. After the duty cycle  116  is determined, the step size term ΔT can be calculated via Equation 2 to obtain useful process information, as explained above. 
     As is further explained below with reference to  FIGS.  3 - 6   , embodiments of the instant disclosure utilize a DLL to delay a periodic input signal by the three amounts of time described above (i.e., a first amount of time that corresponds to a full period of the periodic input signal, a second amount of time that corresponds to a portion of the period that the periodic input signal has a logic-level high value, and a third amount of time that corresponds to a portion of the period that the periodic input signal has a logic-level low value). In some embodiments, the three amounts of delay time are achieved using three different patterns of signals generated by a pattern generator. A controller processes the digital control words OTW FULL , OTW HIGH , and OTW LOW  to determine the duty cycle and the step size ΔT. Further, embodiments of the present disclosure use mathematical operations as detailed above to remove uncertainty terms (e.g., intrinsic delay of the DLL, step size ΔT), thus enabling the calculation of duty cycle in a manner that is more accurate than previous approaches. 
     Embodiments described below with reference to  FIGS.  3 - 6    implement the approaches of the instant disclosure via low complexity circuits that enable easy process migration. The low complexity circuits described herein include components (e.g., delay train, XOR gate, D flip flops, and dividers) that can be easily fabricated and designed. Portions of the example architectures described herein may be created via register level transfer (RTL) design and then implemented by auto place and route (APR). Further, as detailed herein, embodiments of the instant disclosure provide the measured results of duty cycle and process information (e.g., step size ΔT) in a digital format. The digital output provides efficiency and convenience for automatic test equipment (ATE) testing and digital signal processing (DSP). Other advantages of the instant approaches are explained throughout this disclosure. 
       FIG.  3    is a schematic diagram of a circuit for determining a duty cycle  3116  of a periodic input signal  3002 , in accordance with some embodiments. The circuit of  FIG.  3    includes components that implement one or more of the functionalities discussed above with reference to  FIGS.  1 ,  2     a ,  2   b , and  2   c . The periodic input signal  3002  is labeled “DUT-IN” in this figure, reflecting the fact that the periodic input signal  3002  may in some instances be a periodic signal generated by a device under test (DUT). However, the embodiments of the instant disclosure are not limited to scenarios where the periodic input signal is generated by a DUT. As seen in  FIG.  3   , the circuit includes a delay locked loop (DLL) having a delay train  3134  and phase detector  3131 . The delay train  3134  is configured to delay the periodic input signal  3002  based on digital control words (labeled “OTW” in  FIG.  3   ) generated by a digital circuit  3240 . 
     In some embodiments, the digital control words generated by the digital circuit  3240  include the three distinct digital control words OTW FULL , OTW HIGH , and OTW LOW  described above with reference to  FIGS.  1 ,  2     a ,  2   b , and  2   c . A first digital control word OTW FULL  generated by the digital circuit  3240  causes the delay train  3134  to delay the periodic input signal  3002  by a first amount of time that corresponds to a period of the periodic input signal  3002 . The second digital control word OTW HIGH  generated by the digital circuit  3240  causes the delay train  3134  to delay the periodic input signal  3002  a second amount of time that corresponds to a portion of the period that the periodic input signal  3002  has a logic-level high value. The third digital control word OTW LOW  generated by the digital circuit  3240  causes the delay train  3134  to delay the periodic input signal  3002  a third amount of time that corresponds to a portion of the period that the periodic input signal  3002  has a logic-level low value. 
     The circuit of  FIG.  3    uses digital signals Sw, Xor to determine which of the first, second, and third digital control words (e.g., OTW FULL , OTW HIGH , or OTW LOW ) is being generated at a given time: 
     
       
         
           
               
               
             
               
                   
               
               
                 {Sw, Xor} 
                 Functions 
               
               
                   
               
             
            
               
                 {0 0} 
                 Measuring high period of period clock signal 
               
               
                 {0 1} 
                 Measuring low period of period clock signal 
               
               
                 {1 0} 
                 Measuring full period of period clock signal 
               
               
                   
               
            
           
         
       
     
     As shown in the table above, when Sw=1 and Xor=0, the first digital control word OTW FULL  used in delaying the periodic input signal  3002  the first amount of time is generated. When Sw=0 and Xor=0, the second digital control word OTW HIGH  used in delaying the periodic input signal  3002  the second amount of time is generated. When Sw=0 and Xor=1, the third digital control word OTW LOW  used in delaying the periodic input signal  3002  the third amount of time is generated. Accordingly, by progressing through the different combinations of Sw and Xor, the circuit of  FIG.  3    can generate the digital control words OTW FULL , OTW HIGH , and OTW LOW  and then use the three digital control words to calculate the duty cycle  3116  according to Equation 1 above. Components for generating and processing the Sw and Xor digital signals are described in further detail below. 
     The phase detector  3131  generates signals that are used by the digital circuit  3240  in generating the first, second, and third digital control words OTW FULL , OTW HIGH , and OTW LOW . Specifically, as seen in  FIG.  3   , the phase detector  3131  receives (i) a reference signal that is equivalent to the periodic input signal  3002  at an input “C” (e.g., a clock input), and (ii) a delayed version of the periodic input signal  3002  from the delay train  3134  at an input “D” (e.g., a data input). The phase detector  3131  determines when edges (e.g., rising edges, falling edges, as described above) of the received signals are aligned and generates the first, second, and third digital control words OTW FULL , OTW HIGH , and OTW LOW  based on the alignment of these signals. This is described above with reference to  FIGS.  2   a ,  2   b , and  2   c    and in further detail below. 
     To generate the first digital control word OTW FULL  that causes the periodic input signal  3002  to be delayed the first amount of time, a divider circuit  3111  and XOR gate  3113  are utilized, among other components. The divider circuit  3111  divides the periodic input signal  3002  by two (2) to generate a slower, divided version of the periodic input signal. The divided version of the periodic input signal and the undivided periodic input signal  3002  are received at inputs of a multiplexer  3112 , which selects one of the two received signals and propagates the selected signal. 
     The XOR gate  3113  ( i ) functions as an inverter when the Xor signal is equal to a first value (e.g., 1′b1), and (ii) does not invert a received input signal when the Xor signal is equal to a second value (e.g., 1′b0). Accordingly, when the multiplexer  3112  propagates the divided version of the periodic input signal and the XOR gate  3113  inverts that divided signal, the output of the XOR gate  3113  is a divided, inverted version of the periodic input signal, similar to the waveform  1301  described above with reference to  FIG.  2 A . In some embodiments, both the periodic input signal  3002  and the divided, inverted version of it are received at delay line and phase detector module  3130 . The phase detector  3131  determines when edges of the periodic input signal  3002  and the divided, inverted version of the periodic input signal are aligned, where the alignment of the edges indicates that the periodic input signal  3002  has been delayed the first amount of time, as described above with reference to  FIG.  2 A . An output of the phase detector  3131  is coupled to the digital circuit  3240 , thus providing a feedback loop that enables the digital circuit  3240  to modify the first digital control word OTW FULL  until the periodic input signal  3002  has been delayed the first amount of time. 
     To generate the second digital control word OTW HIGH  that causes the periodic input signal  3002  to be delayed the second amount of time, the XOR gate  3113  is utilized, among other components. As explained above, the XOR gate  3113  functions as an inverter when the Xor signal is equal to the first value. Accordingly, when the multiplexer  3112  propagates the periodic input signal  3002  and the XOR gate  3113  inverts that signal, the output of the XOR gate  3113  is an inverted version of the periodic input signal  3002 , similar to the waveform  1101  described above with reference to  FIG.  2 B . In some embodiments, both the periodic input signal  3002  and the inverted version of it are received at the delay line and phase detector module  3130 . The phase detector  3131  determines when edges of the periodic input signal  3002  and the inverted version of the periodic input signal are aligned, where the alignment of the edges indicates that the periodic input signal  3002  has been delayed the second amount of time, as described above with reference to  FIG.  2 B . The output of the phase detector  3131  is coupled to the digital circuit  3240 , and this provides a feedback loop that enables the digital circuit  3240  to modify the second digital control word OTW HIGH  until the periodic input signal  3002  has been delayed the second amount of time. 
     To generate the third digital control word OTW LOW  that causes the periodic input signal  3002  to be delayed the third amount of time, the XOR gate  3113  is again utilized as an inverter, among other components. Specifically, in some embodiments, the XOR gate  3113  is used to propagate (i) a first waveform representative of an inverted version of the periodic input signal  3002  (e.g., waveform  1202  shown in  FIG.  2 C ), and (ii) a second waveform representative of an inverted version of the first waveform (e.g., waveform  1201  shown in  FIG.  2 C ). The propagated signals are received at the delay line and phase detector module  3130 . The phase detector  3131  determines when edges of the periodic input signal  3002  and the inverted version of the periodic input signal are aligned, where the alignment of the edges indicates that the periodic input signal  3002  has been delayed the third amount of time, as described above with reference to  FIG.  2 C . The output of the phase detector  3131  is coupled to the digital circuit  3240 , and this provides a feedback loop that enables the digital circuit  3240  to modify the third digital control word OTW LOW  until the periodic input signal  3002  has been delayed the third amount of time. 
     In the circuit of  FIG.  3   , a controller  3230  receives the digital control words from the digital circuit  3240  and determines the duty cycle  3116  based on the first, second, and third digital control words OTW FULL , OTW HIGH , OTW LOW . In some embodiments, the controller  3230  determines the duty cycle  3116  by solving Equation 1, as detailed above. 
     Along with the features described above, the circuit of  FIG.  3    also includes an analog block  3100  and a digital block  3200  that are electrically connected to each other. The analog block  3100  includes a selection module  3110  and the aforementioned delay line and phase detector module  3130 , which are electrically connected to each other as seen in  FIG.  3   . The delay line and phase detector module  3130  includes the delay train  3134  and phase detector  3130  described above. In some embodiments, the phase detector  3130  is implemented using a sensed amplifier flip flop (SAFF). 
     In  FIG.  3   , the digital block  3200  includes a two-bit counter  3210 , a reset block  3250  for generating reset signals, the digital circuit  3240 , and the controller  3230  for calculating the duty cycle  3116 . In some embodiments, the reset block  3250  is implemented as a part of the controller  3230 . The digital block  3200  also includes a clock generation module  3220  for generating a system clock f sys  that is utilized as a timing signal by the digital circuit  3240 , controller  3230 , and reset module  3250 . In some embodiments, the clock generation module  3220  generates the system clock f sys  by dividing the periodic input signal  3002  using a divider  3221  that divides by sixteen (16). Accordingly, the system clock f sys  is slower than the periodic input signal  3002  due to the division. A retime block  3222  of the digital block  3200  re-samples the output of the phase detector  3131  to avoid meta problems. 
     The selection module  3110  of the analog block  3100  includes divider  3111 , multiplexer  3112 , XOR gate  3113 , and two D flip flops  3114 ,  3115 . In the analog block  3100 , the periodic input signal  3002  is received by the divider  3111  and a first input pin of the multiplexer  3112 . An output of the divider  3111  is electrically connected to a second input pin of the multiplexer  3112 , and a control pin of the multiplexer  3112  for determining the multiplexer&#39;s selection is connected to an output of the D flip flop  3114 . Further, the output of the multiplexer  3112  is connected to a first input of the XOR gate  3113 , and an output of the D flip flop  3115  is connected to a second input of the XOR gate  3113 . 
     In  FIG.  3   , the output of the selection module  3110  is the output of the XOR gate  3113 , and this output is received as an input at the delay train  3134 . The delay train  3134  includes a programmable delay line  3132  and an inverter  3133 . The programmable delay line  3132  is controlled by the digital block  3200  and in particular the digital circuit  3240  that generates the digital control words. The inverter  3133  is used to invert the output of the selection module  3110 . As seen in  FIG.  3   , an output of the programmable delay line  3132  connects to the input labeled “D” (e.g., data input) of the phase detector  3131 , and an output of the inverter  3133  connects to the input labeled “C” (e.g., clock input) of the phase detector  3131 . An output of the phase detector  3131  is electrically connected to the digital block  3200  to provide phase information as described herein. In some embodiments, the output of the phase detector  3131  connects to a D flip flop  3222  of the digital block  3200  to enable retiming of the phase information by the system clock f sys . 
     The 2-bit counter  3210  generates three distinct outputs (e.g., 2′b00, 2′b01 and 2′b10), which are used to control the selection module  3110  for generating three patterns. The combination of the selection module  3110  and the 2-bit counter  3210  may be understood as making up a pattern generator module  4000 , as labeled in  FIG.  4   . As described above, the digital circuit  3240  traces the period of the periodic input signal  3002  by increasing or decreasing the digital control word OTW based on the output from the phase detector  3131 . In some embodiments, the period trace is completed when the output of the phase detector  3131  toggles between 1 and 0, at which point the digital circuit  3240  outputs a locking signal LD. 
     The locking signal LD is received by D flip flops  3232 ,  3233 , which sample the LD signal twice. In some embodiments, the first sampling turns the locking signal LD into a strobe clock f STROBE , and the second sampling turns the locking signal LD into a triggering event to trigger the reset block  3250  and the 2-bit counter  3210 . The strobe clock f STROBE  drives the D flip flops  3232 ,  3233  to store the digital control word generated by the digital circuit  3240  and divide-by-3 block  3231 . In some embodiments, another strobe clock f STROBE_DIV3  generated by the divide-by-3 block  3231  is used by the controller  3230  to latch the three digital control words OTW FULL , OTW HIGH  AND OTW LOW . 
     As explained above, the second sampling of the locking signal LD turns the signal LD into a triggering event to trigger the reset block  3250  and the 2-bit counter  3210 . The triggering event has one clock latency compared to f STROBE , and as a result, the reset block  3250  sends a reset signal to the digital circuit  3240  after finishing the storage of the digital control words from the digital circuit  3240 . The triggering event also drives the 2-bit counter  3210  for changing the output state. In some embodiments, the three outputs of the 2-bit counter  3210  represent high period measurement in 2′b00, low period measurement in 2′b01, and full period measurement in 2′b10. 
     In the embodiment of  FIG.  3   , the controller  3230  determines that the measurement is completed by receiving the locking signal LD having a high level and then turning the locking signal LD to the strobe clock f STROBE . As explained above, the strobe clock f STROBE  triggers D flip flops  3232 ,  3233  to latch the digital control words OTW and drives the divide-by-3 block  3231  to generate the strobe clock f STROBE_DIV3 . The strobe clock f STROBE  also drives the reset block  3250  and pattern generator module  4000 . The reset block  3250  sends a reset signal to the digital circuit  3240  to restart period tracking, and the pattern generator module  4000  changes the measured pattern for new period tracking. In some embodiments, the strobe clock f STROBE_DIV3  drives the D flip flops  3237 ,  3238 , and  3239  to latch the three different digital control words OTW FULL , OTW HIGH , OTW LOW , which are generated by executing three patterns. The latched digital control words OTW FULL , OTW HIGH , OTW LOW  are used by the controller  3230  for generating the duty cycle  3116  according to Equation 1. 
       FIG.  4    is a schematic diagram illustrating the pattern generator module  4000  with selection module  3110  and 2-bit counter  3210  used to measure high, low, and full periods of the periodic input signal  3002 , according to some embodiments. The switchovers of high, low, and full are controlled by the pattern generator module  4000 , which is driven by the locking signal LD generated by the digital circuit  3240 . As explained above, the selection module  3110  includes the divider  3111 , multiplexer  3112 , XOR gate  3113 , and two D flip flops  3114 ,  3115 . The XOR gate  3113  provides a non-inverted clock when xor=1′b0 and an inverted clock when xor=1′b1. The divider  3111  is implemented to measure the “full” period with xor=1′b0 and sw=1′b1. According to some embodiments, all switching signals (e.g., Sw and Xor) are resampled by falling edge clocks  4001 ,  4002 , and  4003  to avoid clock glitch. 
     In some embodiments, the 2-bit counter  3210  generates three states: 2b′00, 2′b01 and 2′b10. The MSB (most significant bit) of 2-bit output is denoted “Sw,” and the LSB (least significant bit) is denoted “Xor.” According to some embodiments, the signal Xor controls the XOR-gate  3113  to either invert the periodic input signal  3002  or not (e.g., “1” means to invert the periodic input signal  3002 , and “0” means to propagate the periodic input signal  3002  without inversion). According to some embodiments, the signal Sw controls the multiplexer  3112  to choose either the periodic input signal  3002  or the version of the periodic input signal  3002  that has been divided by two (2), as generated by divider  3111 . 
       FIG.  5    is a schematic diagram illustrating a data strobe and period calculation module, according to some embodiments. The controller  3230  includes first and second D flip flops  3232 ,  3233  as shown in  FIGS.  3  and  5   . Both of the D flip flops  3232 ,  3233  receive the system clock f SYS  from the clock generation module  3220 , which divides the periodic input signal  3002  by 16 using the divider  3231 . The D flip flop  3233  receives the locking signal LD from the controller  3230 , and the D flip flop  3232  transmits the locking signal LD with a second retime (LD NEG ) to the two-bit counter  3210 . In some embodiments, the D flip flops  3234 ,  3235 , and  3236  are connected together to supply f STROBE  to the divider  3231 , which divides f STROBE  by three to provide f STROBE_DIV3  to D flip flops  3237 ,  3238 , and  3239 . 
     In some embodiments, the locking signal LD from the digital circuit  3240  is resampled by the system clock f SYS  at a falling edge to generate the strobe clock f STROBE  used in capturing the digital control words OTW FULL , OTW HIGH , and OTW LOW . The reset block  3250  is triggered by the locking signal LD via a second sampling that is required to reset the digital circuit  3240  for a new period measurement. One additional cycle delay, however, can ensure that the digital control word data is stored before the reset of digital circuit  3240 . In some embodiments, the first sampling of OTW FULL , OTW HIGH , and OTW LOW  via f STROBE  is captured by a low-speed clock (where f STROBE_DIV3  is f STROBE  divided by 3) for the calculation of the final period of Hi′ and Full′ free of PVT artifact fluctuations. 
       FIG.  6    is a timing diagram illustrating a measurement of high, low, and full periods of the periodic input signal  3002 , according to some embodiments. In some embodiments, the system clock f SYS  of the digital block  3200  is the periodic input signal  3002  divided by 16 to enable lower digital power consumption. The locking signal LD that is sampled by the falling edge of f SYS  becomes the strobe clock to capture the digital control word generated by the digital circuit  3240  (labeled OTW DLL  in  FIG.  6   ). The locking signal LD with a second retime (labeled LD NEG  in  FIG.  6   ) triggers the reset block  3250  to reset the digital circuit  3240  and change the pattern of [Sw, Xor]. In some embodiments, when the pattern of [Sw, Xor] changes from [0,0] to [1,0], the measurements of high/low/full periods are completed by changing pattern of [Sw, Xor] from [0,0] to [1,0]. 
     Example sequences of timing diagrams are illustrated in  FIG.  6   . According to some embodiments, the state of “Sw”  6010  and “Xor”  6009  starts from 2′b00, and the periodic input signal  3002  is propagated directly through the selection module  3110  to the delay train  3134 . The digital circuit  3240  releases the locking signal LD  6004  having a high level for completing period tracking. The f STROBE    6005  drives D flip flops  3232 ,  3233  to store the digital control word for the high period. The 2-bit counter  3210  increases value from 2′b00 to 2′b01 to turn the state of “Sw”  6010  and “Xor”  6009  to 2′b01. The reset block  3250  sends a reset signal to the digital circuit  3240  to turn locking signal LD  6004  to low and restart period tracking. In some embodiments, the state of “Sw”  6010  and “Xor”  6009  becomes 2′b01. The selection module  3110  inverts the periodic input signal  3002  and outputs it to the delay train  3134 . The locking signal LD  6004  of the digital circuit  3240  becomes high again to drive D flip flops  3232 ,  3233  of the controller  3230  to store the digital control word OTW LOW  for low period. 
     Reset block  3250  sends a signal to the digital circuit  3240  to drop down the locking signal LD  6004  and restart period tracking, and the 2-bit counter  3210  changes state to 2′b10 from 2′b01. In some embodiments, the state of “Sw”  6010  and “Xor”  6009  becomes 2′b10, and the periodic input signal  3002  is provided to the divider  3111 . The digital circuit  3240  implements the same procedure as discussed above to complete period tracking and generate “H” in the locking signal LD. The f STROBE    6005  drives D flip flops  3232 ,  3233  to store OTW FULL , and the rising edge of f STROBE_DIV3    6007  drives the D flip flops  3237 ,  3238 , and  3239  to latch the three different digital control words OTW (e.g., OTW FULL , OTW HIGH , OTW LOW , as described herein). These control words are used in calculating the duty cycle and step size ΔT. According to some embodiments, the 2-bit counter  3210  receives trigger event to change the state from 2′b10 to 2b′00 for the calculation. 
       FIG.  7    depicts operations of an example method  7000  for determining a duty cycle of a periodic input signal, in accordance with some embodiments.  FIG.  7    is described with reference to  FIG.  1    above for ease of understanding. But the process of  FIG.  7    is applicable to other circuits as well. At  7002 , the periodic input signal (e.g., periodic input signal  102 ) is received at a delay circuit (e.g., delay circuit  104 ) configured to delay the periodic input signal based on a digital control word. At  7004 , a first digital control word (e.g., OTW FULL    112   a ) used to delay the periodic input signal a first amount of time corresponding to a period of the periodic input signal is generated. At  7006 , a second digital control word (e.g., OTW HIGH    112   b  used to delay the periodic input signal a second amount of time corresponding to a portion of the period that the periodic input signal has a logic-level high value is generated. At  7008 , a third digital control word (e.g., OTW LOW    112   c ) used to delay the periodic input signal a third amount of time corresponding to a portion of the period that the periodic input signal has a logic-level low value. In the example of  FIG.  1   , the digital circuit  110  generates the first, second, and third digital control words. At  7010 , the duty cycle (e.g., duty cycle  116 ) of the periodic input signal is determined based on the first, second, and third digital control words. In the example of  FIG.  1   , the controller  114  generates the duty cycle. 
     As described above, the circuit of  FIG.  1    may be used to measure a first parameter, e.g., a duty cycle of a periodic input signal, of a first DUT. As will be described in detail below, the circuit of  FIG.  1    may be used with another circuit to facilitate measurement of a second parameter of a second DUT. The second DUT may be a D-type flip-flop, a set-reset (SR) type flip-flop, a JK-type flip-flop, a T-type flip-flop, any suitable latch circuit, or a combination thereof.  FIG.  8    depicts waveforms representative of a clock input signal  810 , a data input signal  820 , and a data output signal  830  when a D-type flip-flop is in a stable state, in accordance with some embodiments. As seen in this figure, the D-type flip-flop sends a data input signal  820  from a data input (D) thereof to a data output (Q) thereof when a clock input signal  810  at a clock input (CK) thereof is at a triggering edge (e.g., a rising edge or a falling edge). For example, when the data input signal  820  is a logic-level high value and the clock input signal  810  is at a triggering edge, the data output signal  830  at the data output (Q) is also a logic-level high value. Conversely, when the data input signal  820  is a logic-level low value and the clock input signal  810  is at a triggering edge, the data output signal  830  is also a logic-level low value. 
     The D-type flip-flop performs reliably as described above when the data input signal  820  is a logic-level high/low for a first minimum amount of time before (and a second minimum amount of time after) each triggering edge of the clock input signal  810 . These first and second minimum amounts of time are referred to as a set-up time and a hold time of the D-type flip-flop, respectively. 
       FIG.  9    depicts waveforms representative of a clock input signal  910 , a data input signal  920 , and a data output signal  930  when the D-type flip-flop is in a metastable state, in accordance with some embodiments. As seen in this figure, while each of the clock input signal  910  at the clock input (CK) and the data input signal  920  at the data input (D) transitions between logic-level high and low values, the data output signal  930  at the data output (Q) is neither a logic-level high nor low value, but is a logic-level value between high and low, i.e., substantially flat. This occurs when the data input signal  920  transitions from one logic-level value to another after the set-up time of the D-type flip-flop starts and/or before the hold time of the D-type flip-flop ends. At this time, the D-type flip-flop is said to be in a metastable state. The period of time, during which the D-type flip-flop is in the metastable state, is referred to as the metastability window of the D-type flip-flop. 
       FIG.  10    depicts a block diagram of a circuit  1000  for facilitating measurement of a parameter, e.g., metastability window, of a D-type flip-flop  1030 , in accordance with some embodiments. As seen in this figure, the circuit  1000  includes a first circuit  1010  and a second circuit  1020 . The first circuit  1010  includes a delay circuit, a phase detector, a digital circuit, and a controller similar to the delay circuit  104 , the phase detector  108 , the digital circuit  119 , and the controller  114 , respectively. For example, the first circuit  1010  receives a periodic input signal  102  at an input of the circuit  1000  and generates a step size (ΔT) at an output of the circuit  1000  based on the periodic input signal  102  received thereby, in a manner described above with reference to  FIG.  1   . As will be shown later, the step size (ΔT) is associated with a parameter, e.g., metastability window, of the D-type flip-flop  1030 . 
     The second circuit  1020  is configured to receive the periodic input signal  102  and to generate a clock input signal  1040  and a data input signal  1050  at outputs of the circuit  1000  based on the periodic input signal  102  received thereby. The D-type flip-flop  1030  receives the clock input signal  1040  at the clock input (CK) thereof and the data input signal  1050  at the data input (D) thereof to generate a data output signal  1060  at the data output (Q) thereof. 
     In further detail,  FIG.  11    depicts a schematic diagram of the circuit  1000 , in accordance with some embodiments. As seen in this figure, the second circuit  1020  includes a first divider circuit  1110 , a first delay circuit  1120 , a second divider circuit  1130 , and a second delay circuit  1140 . The first divider circuit  1110  is configured to receive the periodic input signal  102  and to divide the periodic input signal  102  received thereby by a first predetermined number (X) so as to generate a first input signal  1150 . In this exemplary embodiment, the first predetermined number (X) is greater than 2, e.g., 16. 
     The first delay circuit  1120  is configured to receive the first input signal  1150  and a fixed digital control word  1120 ′ so as to delay the first input signal  1150  by a fixed amount of time based on the fixed digital control word  1120 ′, generating a delayed version of the first input signal  1150 . The delayed version of the first input signal  1150  serves as the clock input signal  1040 . 
     The second divider circuit  1130  is configured to receive the first input signal  1150  and to divide the first input signal  1150  by a second predetermined number (Y) so as to generate a second input signal  1160 . In this exemplary embodiment, the second predetermined number (Y), e.g., 2, is less than the first predetermined number (X). 
     The second delay circuit  1140  is configured to receive the second input signal  1160  and a variable digital control word  1140 ′ so as to delay the second input signal  1160  by different amounts of time based on the variable digital control word  1140 ′, generating different delayed versions of the second input signal  1160 . Each delayed version of the second input signal  1160  serves as the data input signal  1050 . 
     In operation, when it is desired to determine a parameter, e.g., metastability window, of the D-type flip-flop  1030 , the fixed digital control word  1120 ′ is adjusted at a fixed value to generate the delayed version  1040  of the first input signal  1150 . Next, the variable digital control word  1140 ′ is adjusted at different values to generate the delayed versions  1050  of the second input signal  1160 . 
     Next, the values of the variable digital control word  1140 ′ at which the D-type flip-flop  1030  enters and leaves the metastable state are obtained based on the data output signal  1060  of the D-type flip-flop  1030 . For example,  FIG.  12    depicts a metastability window of the D-type flip-flop  1030 , in accordance with some embodiments. As seen in this figure, when the variable digital control word  1140 ′ is in the ranges from 1 to 10 and from 20 to 26, each data output signal  1060  of the D-type flip-flop  1030  corresponds to the data output signal  830  of  FIG.  8   . That is, in these ranges, the D-type flip-flop  1030  is in a stable state. On the other hand, when the variable digital control word  1140 ′ is in the range from 11 to 19, each data output signal  1060  at the D-type flip-flop  1030  corresponds to the data output signal  930  of  FIG.  9   . That is, in this range, the D-type flip-flop  1030  is in a metastable state. 
     Next, the step size (ΔT) generated by the first circuit  1010  is obtained at the output of the circuit  1000 . Thereafter, the metastability window of the D-type flip-flop  1030  is determined by solving Equation 10: 
       ( V   1   −V   2   +V   3 )×Δ T   (Equation 10)
 
     where V 1  is the value of the variable digital control word  1140 ′ at which the D-type flip-flop  1030  leaves the metastable state, V2 is the value of the variable digital control word  1140 ′ at which the D-type flip-flop  1030  enters the metastable state, V3 is the value by which the variable digital control word  1140 ′ is incremented, and ΔT is the step size. Thus, in the example of  FIG.  12   , at a step size (ΔT) of 1.26 ps, the metastability window of the D-type flip-flop  1030  is (19-11+1)×1.26 ps or 11.34 ps. 
       FIG.  13    depicts a metastability window of the D-type flip-flop  1030 , in accordance with some embodiments. As seen in this figure, when the variable digital control word  1140 ′ is in the ranges from 1 to 10 and from 20 to 26, in which the D-type flip-flop  1030  is in a stable state, the D-type flip-flop  1030  generates a first current, e.g., about 30 uA. On the other hand, when the variable digital control word  1140 ′ is in the range from 11 to 19, in which the D-type flip-flop  1030  is in a metastable state, the D-type flip-flop  1030  generates a second current, e.g., about 10 uA, less than the first current. Thus, current generated by the D-type flip-flop  1030  is also associated the metastability window of the D-type flip-flop  1030 . Such current may be measured by an ammeter connected to the D-type flip-flop  1030 . 
       FIG.  14    depicts operations of an example method  1400  for facilitating measurement of a parameter, e.g., metastability window, of the D-type flip-flop  1030 , in accordance with some embodiments.  FIG.  14    is described with reference to  FIGS.  10 - 13    above for ease of understanding. But the process of  FIG.  14    is applicable to other circuit as well. At  1410 , the first circuit  1010  receives a periodic input signal  102  and generates a step size (ΔT) based on the periodic input signal  102  received thereby, in a manner described above with reference to  FIG.  1   . At  1420 , the first divider circuit  1110  receives the periodic input signal  102  and divides the periodic input signal  102  received thereby by a first predetermined number (X) to generate a first input signal  1150 . At  1430 , the first delay circuit  1120  receives the first input signal  1150  and a fixed digital control word  1120 ′ to delay the first input signal  1150  by a fixed amount of time based on the fixed digital control word  1130 ′, generating a delayed version  1040  of the first input signal  1150  at an output thereof. 
     At  1440 , the second divider circuit  1120  receives the first input signal  1150  and divides the first input signal  1150  received thereby by a second predetermined number (Y) to generate a second input signal  1160 . At  1450 , the second delay circuit  1140  receives the second input signal  1160  and a variable digital control word  1140 ′ to delay the second input signal  1160  by different amounts of time based on the variable digital control word  1140 ′, generating different delayed versions  1050  of the second input signal  1160  at an output thereof. 
     The D-type flip-flop  1030  generates a data output signal  1060  at the data output (Q) thereof based on the clock input signal  1040  at the clock input (CK) thereof and the data input signal  1050  at the data input (D) thereof. The metastability window of the D-type flip-flop  1030  may be determined as described above with reference to  FIGS.  10 - 13   . 
     In an alternative embodiment, the circuit  1000  is dispensed with the first circuit  1010  and the step size (ΔT) is obtained from a circuit external to the circuit  1000 . 
       FIG.  15    depicts a block diagram of a circuit  1500  for facilitating measurement of a parameter, e.g., metastability window, of a D-type flip-flop  1530 , in accordance with some embodiments. As seen in this figure, the circuit  1500  includes a first circuit  1510  and a second circuit  1520 . The first circuit  1510  includes a delay circuit, a phase detector, a digital circuit, and a controller similar to the delay circuit  104 , the phase detector  108 , the digital circuit  119 , and the controller  114 , respectively. For example, the first circuit  1510  receives a periodic input signal  102  at an input of the circuit  1500  and generates a step size (ΔT) at an output of the circuit  1500  based on the periodic input signal  102  received thereby, in a manner described above with reference to  FIG.  1   . As will be shown later, the step size (ΔT) is associated with a parameter, e.g., metastability window, of the D-type flip-flop  1530 . 
     The second circuit  1520  is configured to receive the periodic input signal  102  and to generate a clock input signal  1540  at an output of the circuit  1500  based on the periodic input signal  102  received thereby. The D-type flip-flop  1530  receives the clock input signal  1540  at the clock input (CK) thereof and a data input signal  1550  at the data input (D) thereof to generate a data output signal  1560  at the data output (Q) thereof. 
     In further detail,  FIG.  16    depicts a schematic diagram of the circuit  1500 , in accordance with some embodiments. As seen in this figure, the second circuit  1520  includes a divider circuit  1610 , a first delay circuit  1620 , a second delay circuit  1630 , and a pulse width modulator  1640 . The divider circuit  1610  is configured to receive the periodic input signal  102  and to divide the periodic input signal  102  received thereby by a predetermined number (Z) so as to generate an input signal  1650 . 
     The first delay circuit  1620  is configured to receive the input signal  1650  and a fixed digital control word  1620 ′ so as to delay the input signal  1650  by a fixed amount of time based on the fixed digital control word  1620 ′, generating a delayed version  1660  of the input signal  1650 . 
     The second delay circuit  1630  is configured to receive the input signal  1650  and a variable digital control word  1630 ′ so as to delay the input signal  1650  by different amounts of time based on the variable digital control word  1630 ′, generating different delayed versions  1670  of the input signal  1650 . 
     The pulse width modulator (PWM)  1640  is configured to receive the delayed version  1660  of the input signal  1650  and the different delayed versions  1670  of the input signal  1650  so as to generate a plurality of PWM signals, each of which has a distinct duty cycle. Each PWM signal serves as a clock input signal  1540  at the clock input (CK) of the D-type flip-flop  1530 . 
     In this exemplary embodiment, the PWM  1640  includes one or more logic gates, one or more latch circuits, or a combination thereof. For example, the PWM  1640  includes an AND gate and an inverter. The AND gate has a first input connected to the first delay circuit  1620  and an output connected to the clock input (CK) of the D-type flip-flop  1530 . The inverter is connected between the second delay circuit  1630  and a second input of the AND gate. 
     In operation, when it is desired to determine a parameter, e.g., metastability window, of the D-type flip-flop  1530 , the fixed digital control word  1620 ′ is adjusted at a fixed value to generate the delayed version  1660  of the input signal  1650 . Next, the variable digital control word  1630 ′ is adjusted at different values to generate the delayed versions  1670  of the input signal  1650 , whereby the PWM  1640  generates the PWM signals  1540 . 
     Next, the values of the variable digital control word  1630 ′ at which the D-type flip-flop  1530  enters and leaves the metastable state are obtained based on the data output signal  1560  of the D-type flip-flop  1530 . For example,  FIG.  17    depicts a metastability window of the D-type flip-flop  1530 , in accordance with some embodiments. As seen in this figure, when the variable digital control word  1630 ′ is in the range from 15 to 26, each data output signal  1560  of the D-type flip-flop  1530  corresponds to the data output signal  830  of  FIG.  8   . That is, in this range, the D-type flip-flop  1530  is in a stable state. On the other hand, when the variable digital control word  1630 ′ is in the range from 1 to 14, each data output signal  1560  of the D-type flip-flop  1530  corresponds to the data output signal  930  of  FIG.  9   . That is, in this range, the D-type flip-flop  1530  is in a metastable state. 
     Next, the step size (ΔT) generated by the first circuit  1510  is obtained at the output of the circuit  1500 . Thereafter, the metastability window of the D-type flip-flop  1530  is determined by solving equation 10 described above. Thus, in the example of  FIG.  17   , at a step size (ΔT) of 1.26 ps, the metastability window of the D-type flip-flop  1530  is (14-1+1)×1.26 ps or 17.64 ps. 
       FIG.  18    depicts a metastability window of the D-type flip-flop  1530 , in accordance with some embodiments. As seen in this figure, when the variable digital control word  1630 ′ is in the range from 15 to 26, in which the D-type flip-flop  1530  is in a stable state, the D-type flip-flop  1530  generates a first current, e.g., about 30 uA. On the other hand, when the variable digital control word  1630 ′ is in the range from 1 to 14, in which the D-type flip-flop  1530  is in a metastable state, the D-type flip-flop  1530  generates a second current, e.g., about 0 to about 15 uA, less than the first current. Thus, current generated by the D-type flip-flop  1530  is also associated with the metastability window of the D-type flip-flop  1530 . Such current may be measured by an ammeter connected to the D-type flip-flop  1530 . 
       FIG.  19    depicts operations of an example method  1900  for facilitating measurement of a parameter, e.g., metastability window, of the D-type flip-flop  1530 , in accordance with some embodiments.  FIG.  19    is described with reference to  FIGS.  15 - 18    above for ease of understanding. But the process of  FIG.  19    is applicable to other circuit as well. At  1910 , the first circuit  1510  receives a periodic input signal  102  and generates a step size (ΔT) based on the periodic input signal  102  received thereby in a manner described above with reference to  FIG.  1   . At  1920 , the divider circuit  1610  receives the periodic input signal  102  and divides the periodic input signal  102  received thereby by a predetermined number (Z) to generate an input signal  1650 . At  1930 , the first delay circuit  1620  receives the input signal  1650  and a fixed digital control word  1620 ′ to delay the input signal  1650  by a fixed amount of time based on the fixed digital control word  1620 ′, generating a delayed version  1660  of the input signal  1650 . 
     At  1940 , the second delay circuit  1630  receives the input signal  1650  and a variable digital control word  1630 ′ to delay the input signal  1650  by different amounts of time based on the variable digital control word  1630 ′, generating different delayed versions  1670  of the input signal  1650 . 
     At  1950 , the PWM  1640  receives the delayed version  1660  of the input signal  1650  and the different delayed versions  1670  of the input signal  1650  to generate a plurality of PWM signals  1540 , each of which has a distinct duty cycle. 
     The D-type flip-flop  1530  generates a data output signal  1560  at the data output (Q) thereof based on the clock input signal  1540  at the clock input (CK) thereof and the data input signal  1550  at the data input (D) thereof. The metastability window of the D-type flip-flop  1530  may be determined as described above with reference to  FIGS.  15 - 18   . 
     In an alternative embodiment, the circuit  1500  is dispensed with the first circuit  1510  and the step size (ΔT) is obtained from a circuit external to the circuit  1500 . 
     In some embodiments, the DUT  1530  is a memory circuit. In such some embodiments, the circuit  1500  may be used to determine a parameter associated with a read/write operation of the memory circuit. 
     The present disclosure is directed to circuits, methods, and devices for determining a duty cycle of a periodic input signal. In an example method for determining a duty cycle of a periodic input signal, the periodic input signal is received at a delay circuit configured to delay the periodic input signal based on a digital control word. A first digital control word is generated, where the first digital control word is used to delay the periodic input signal a first amount of time corresponding to a period of the periodic input signal. A second digital control word is generated, where the second digital control word is used to delay the periodic input signal a second amount of time corresponding to a portion of the period that the periodic input signal has a logic-level high value. A third digital control word is generated, where the third digital control word is used to delay the periodic input signal a third amount of time corresponding to a portion of the period that the periodic input signal has a logic-level low value. The duty cycle of the periodic input signal is determined based on the first, second, and third digital control words. 
     An example circuit for determining a duty cycle of a periodic input signal includes a delay element configured to delay the periodic input signal based on a digital control word. A digital circuit is configured to generate a first digital control word used to delay the periodic input signal a first amount of time corresponding to a period of the periodic input signal. The digital circuit is also configured to generate a second digital control word used to delay the periodic input signal a second amount of time corresponding to a portion of the period that the periodic input signal has a logic-level high value. The digital circuit is further configured to generate a third digital control word used to delay the periodic input signal a third amount of time corresponding to a portion of the period that the periodic input signal has a logic-level low value. The example circuit also includes a controller configured to determine the duty cycle of the periodic input signal based on the first, second, and third digital control words. 
     An example circuit for determining a duty cycle of a periodic input signal includes a delay locked loop with a delay train and a phase detector. The delay locked loop being configured to receive the periodic input signal. The circuit also includes a digital circuit configured to receive an output of the phase detector indicating an alignment between the periodic input signal and a delayed version of the periodic input signal. The digital circuit is also configured to generate digital control words for controlling an amount of delay applied by the delay train. The digital control words include a first digital control word used to delay the periodic input signal a first amount of time corresponding to a period of the periodic input signal, a second digital control word used to delay the periodic input signal a second amount of time corresponding to a portion of the period that the periodic input signal has a logic-level high value, and a third digital control word used to delay the periodic input signal a third amount of time corresponding to a portion of the period that the periodic input signal has a logic-level low value. The circuit also includes a controller configured to determine the duty cycle of the periodic input signal based on the first, second, and third digital control words. 
     The present disclosure is further directed to circuits, methods, and devices for facilitating measurement of a parameter of a DUT. An example circuit configured to facilitate measurement of a parameter of a DUT includes a first divider circuit, a first delay circuit, a second divider circuit, and a second delay circuit. The first divider circuit is configured to divide a periodic input signal by a first predetermined number so as to generate a first input signal. The first delay circuit is configured to generate a delayed version of the first input signal. The second divider circuit is configured to divide the first input signal by a second predetermined number so as to generate a second input signal. The second delay circuit is configured to generate different delayed versions of the second input signal. The parameter of the DUT is determined based on the delayed version of the first input signal and the different delayed versions of the second input signal. 
     An example circuit configured to facilitate measurement of a parameter of DUT includes a divider circuit, a first delay circuit, and a second delay circuit. The divider circuit is configured to divide a periodic input signal by a predetermined number so as to generate an input signal. The first delay circuit is configured to generate a delayed version of the input signal. The second delay circuit is configured to generate different delayed versions of the input signal. The delayed version of the input signal and the different delayed versions of the input signal are associated with the parameter of the DUT. 
     A method for facilitating measurement of a parameter of a device under test (DUT) includes the steps of: receiving a periodic input signal; dividing the periodic input signal by a first predetermined number to generate a first input signal; dividing the first input signal by a second predetermined number to generate a second input signal; and delaying the second input signal to generate different delayed versions of the second input signal. The different delayed versions of the second input signal are associated with the parameter of the DUT. 
     The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.