Patent Publication Number: US-8120067-B1

Title: Power and ground routing of integrated circuit devices with improved IR drop and chip performance

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This is a continuation application of U.S. patent application Ser. No. 12/883,163 filed Sep. 15, 2010, which itself is a continuation application of U.S. patent application Ser. No. 12/052,735 filed Mar. 21, 2008, now U.S. Pat. No. 7,821,038. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The invention relates generally to the integrated circuit power and ground routing and, more particularly, to a novel power and ground routing of integrated circuit (IC) chip devices that utilizes aluminum layer to form power or ground lines for distributing power across the IC from an off chip source to various blocks within the IC, thereby reducing the IR drop (or voltage drop) of the integrated circuit chip devices and improving the chip performance. 
     2. Description of the Prior Art 
     In the processes for designing a large-scale integrated semiconductor circuit device, respective blocks of the device are generally designed in parallel to complement device characteristics with one another. During the designing the large-scale device, the building-block type of method is utilized, in which the circuit of the device is divided into a plurality of circuit blocks and each of the circuit blocks is thus designed at the same time. The overall design of the device is then carried out by integrating these constituent blocks. 
     An integrated circuit (IC) usually has a larger number of circuit blocks and multiple levels of conductors are used to distribute power and signals from off the IC to the circuit blocks within the IC, between the circuit blocks, and between cells within each circuit block. 
     The conductors are formed by lithographically patterning a layer of conductive material to form conductive lines as viewed from above the IC substrate. The conductive layers with conductive lines formed therein are isolated by an insulating layer so that lines of one layer which cross another layer do not physically or electrically contact each other. When it is desired to electrically connect a conductive line formed in one layer to a conductive line formed in another layer, a conductive via is formed extending through the insulating layer between the two conductors. 
     The conductive layers typically have different sheet resistances, with the lowest level (layer  1  or M 1 ) having the highest sheet resistance and the highest level having the lowest sheet resistance. This is due to technological processing constraints such as smaller thickness at the lower layers. The different sheet resistances have influenced routing, for example, with the higher sheet resistance, lower layers generally being used to make connections which are relatively close (e.g. within cells or blocks) while the higher level, lower sheet resistance layers are used to make longer connections, such as between points in different blocks. 
       FIG. 1  is an enlarged top view of a conventional IC chip device with six levels of copper metal layers, wherein merely a small part of a particular circuit block of the IC chip device is illustrated for the sake of simplicity. As shown in  FIG. 1 , a circuit block  10  has power (V DD ) ring  12  and ground (V SS ) ring  14  disposed along its perimeter. The power ring  12  and ground ring  14  are either formed in the sixth-level metal layer (hereinafter M 6 ) or the copper metal layer that is one level lower than M 6 , i.e., M 5 . By way of example, the power ring  12  is formed in M 6 , while the ground ring  14  is formed in M 5 . In such case, some of the other lower levels of copper metal layers, for example, from the second-level copper metal layer, i.e., M 2 , to the fourth-level copper metal layer, i.e., M 4 , may be used for signal routing. 
     Within a center region of the circuit block  10  that is surrounded by the power ring and ground ring, a so-called “mesh” interconnection network  20  is provided. The mesh interconnection network  20  consists of a plurality of substantially orthogonal horizontal lines  22  and longitudinal lines  24 . Through the mesh interconnection network  20  and respective via stacks  32  and  34 , the power or ground signals are provided from respective power or ground rings to the cell level devices such as transistors or regions which are fabricated in or on the main surface of the semiconductor substrate (not shown) and are not equally spaced from the ring. The horizontal lines  22  and longitudinal lines  24  of the mesh interconnection network  20  are respectively formed in either M 5  or M 6  in this exemplary case. 
     In addition, in current copper processes, a layer of aluminum disposed under a passivation layer is mainly used to provide a bondable interface, an aluminum bond pad, atop a copper bond pad formed in the topmost copper metal layer of the integrated circuit chip in order to prevent oxidation of the underlying copper bond pad. In some cases, the layer of aluminum disposed under the passivation layer may be used to form so-called re-distributed layer (RDL) to re-distribute the aluminum bond pad to other location primarily for flip-chip applications. 
     The prior art approach of using the topmost two levels of the copper metal layers, i.e., M 5  and M 6 , for power and ground routing induces that the voltage drop (or IR drop) is unavoidably high. This is partly due to that M 5  and M 6  have different thicknesses and different sheet resistances (Rs). Typically, M 5  is much thinner than M 6 , and thus has a higher sheet resistance (roughly about two times of the sheet resistance of M 6 ). 
     Therefore, there is a strong need in this industry to provide an improved power and ground routing for the integrated circuit chip devices that is capable of reducing the IR drop, thus improving the chip performance. 
     SUMMARY OF THE INVENTION 
     It is one object of the invention to provide an improved power and ground routing for the integrated circuit chip devices that is capable of reducing the IR drop and improving the chip performance. 
     It is another object of the invention to provide an integrated circuit chip device that utilizes aluminum layer over passivation to form power or ground lines, thereby reducing the IR drop of the integrated circuit chip device and improving the performance thereof. 
     According to the claimed invention, an integrated circuit chip includes a semiconductor substrate having thereon a plurality of inter-metal dielectric (IMD) layers and a plurality of first conductive layers embedded in respective the plurality of IMD layers, wherein the first conductive layers comprise copper; a first passivation layer overlying the plurality of IMD layers and the plurality of first conductive layers; a plurality of first power/ground mesh wiring lines, formed in a second conductive layer overlying the first passivation layer, for distributing power signal or ground signal, wherein the second conductive layer comprise aluminum; and a second passivation layer covering the second conductive layer and the first passivation layer. 
     From one aspect of this invention, an integrated circuit chip includes a semiconductor substrate having thereon a plurality of inter-metal dielectric (IMD) layers and a plurality of first conductive layers embedded in respective the plurality of IMD layers, wherein the first conductive layers comprise copper; a first passivation layer overlying the plurality of IMD layers and the plurality of first conductive layers; a first power/ground ring, formed in a second conductive layer overlying the first passivation layer, for distributing power signal or ground signal, wherein the second conductive layer comprise aluminum; and a second passivation layer covering the second conductive layer and the first passivation layer. 
     From another aspect of this invention, an integrated circuit chip includes a semiconductor substrate having thereon a plurality of inter-metal dielectric (IMD) layers and a plurality of first conductive layers embedded in respective IMD layers, wherein the first conductive layers comprise copper; a first insulating layer overlying the plurality of IMD layers and the plurality of first conductive layers; a plurality of first power/ground mesh wiring lines, formed in a second conductive layer overlying the first insulating layer, for distributing power signal or ground signal, wherein the second conductive layer comprise aluminum; and a second insulating layer covering the second conductive layer and the first insulating layer. 
     These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings: 
         FIG. 1  is an enlarged top view of a conventional integrated circuit chip device with six levels of copper metal layers; 
         FIG. 2  is a schematic, cross-sectional diagram illustrating a germane portion of the exemplary integrated circuit chip that is fabricated with six levels of copper metal layers in accordance with one preferred embodiment of this invention; 
         FIG. 3  is a schematic, cross-sectional diagram illustrating the second preferred embodiment of the invention; and 
         FIG. 4  is a schematic diagram showing the layout in accordance with the second preferred embodiment of this invention. 
     
    
    
     DETAILED DESCRIPTION 
     The invention pertains to a novel power and ground routing capable of improving the performance of the integrated circuit chip. The invention utilizes a layer of aluminum in a passivation layer of the integrated circuit chip to form the power or ground ring and/or mesh interconnection network instead of the copper metal layer (Mn−1) that is just one level lower than the topmost copper metal layer (Mn) of the integrated circuit chip. Therefore, one of the topmost two levels of the copper metal layers that used to be formed into power and ground rings and mesh interconnection network can thus be eliminated or be spared for signal routing. Alternatively, the replaced Mn−1 copper layer can be skipped for saving photomask and cost. The invention can increase signal routing source and increase the flexibility of placement and routing. 
     The preferred embodiments of this invention will now be explained with the accompanying figures. Throughout the specification and drawings, the symbol “Mn” refers to the topmost level of the copper metal layers fabricated in the integrated circuit chip, while “Mn−1” refers to the copper metal layer that is just one level lower than the topmost copper metal layer and so on, wherein, preferably, n ranges between 5 and 8 but not limited thereto. The symbol “V” refers to the via plug between two adjacent conductive metal layers. For example, V 5  refers to the via plug interconnecting M 5  to M 6 . 
       FIG. 2  is a schematic, cross-sectional diagram illustrating a germane portion of the exemplary integrated circuit chip  1   a  that is fabricated with six levels of copper metal layers (M 1 -M 6 ) in accordance with one preferred embodiment of this invention. As shown in  FIG. 2 , the exemplary integrated circuit chip  1   a  includes a semiconductor substrate  100  such as a silicon substrate, a silicon-on-insulator (SOI) substrate, SiGe substrate or the like. A plurality of inter-metal dielectric (IMD) layers  110 - 132  are deposited over the semiconductor substrate  100 . Circuit elements  101  such as transistors, capacitors or memory cells are fabricated on the main surface of the semiconductor substrate  100 . The IMD layers  110 - 132  may be formed of low dielectric constant (low-k) materials or ultra low-k materials, but not limited thereto. The IMD layers  110 - 132  may comprise conventional dielectric layer such as silicon oxide, silicon nitride, silicon carbide or silicon oxy-nitride. The low-k or ultra low-k materials described herein may be either organic (e.g., SILK) or inorganic (e.g., HSQ) and may be of a porous or non-porous nature. 
     According to this invention, M 1 -M 6  and respective vias V 1 ˜V 5  are fabricated using copper damascene processes or dual damascene processes, which are well known in the art and are thus not discussed further. The first level of the copper metal layers, i.e., M 1  is fabricated in the IMD layer  112 . A contact plug  220 , typically tungsten plug, is formed in the IMD layer  110  to interconnect M 1  to the circuit elements  101 . The second level of the copper metal layers, i.e., M 2  is fabricated in the IMD layer  116 . A via plug V 1 , typically damascened copper plug integrated with M 2 , is formed in the IMD layer  114  to interconnect M 1  to M 2 . The third level of the copper metal layers, i.e., M 3  is fabricated in the IMD layer  120 . A via plug V 2  is formed in the IMD layer  118  to interconnect M 2  to M 3 . The fourth level of the copper metal layers, i.e., M 4  is fabricated in the IMD layer  124 . A via plug V 3  is formed in the IMD layer  122  to interconnect M 3  to M 4 . The fifth level of the copper metal layers, i.e., M 5  is fabricated in the IMD layer  124 . A via plug V 4  is formed in the IMD layer  122  to interconnect M 4  to M 5 . The topmost level of the copper metal layers, i.e., M 6  is fabricated in the IMD layer  132 . A via plug V 5  is formed in the IMD layer  130  to interconnect M 5  to M 6 . 
     A first passivation layer  140  is deposited on the IMD layer  132  and covers the exposed M 6  layer. The first passivation layer  140  may comprise silicon oxide, silicon nitride, polyimide or other suitable materials. 
     The integrated circuit chip  1   a  further comprises a bonding area  300 . An aluminum pad  302  is formed on the first passivation layer  140  within the bonding area  300 . The aluminum pad  302  is electrically connected with the underlying copper pad  304  that is formed in M 6  layer through via  306 . This aluminum pad  302  prevents oxidation of the underlying copper pad  304 . The aluminum pad  302  may be part of a power or ground ring surrounding a circuit block of the integrated circuit chip  1   a.    
     The aluminum pad  302  is covered with a second passivation layer  142 . The second passivation layer  142  may comprise silicon oxide, silicon nitride, polyimide or other suitable materials. An opening or window  308  is provided in the second passivation layer  142  to expose a portion of the top surface of the aluminum pad  302 . The opening  308  may be formed by conventional lithographic and etching methods. 
     The integrated circuit chip  1   a  depicted in  FIG. 2  is fabricated based on a so-called 1P6M scheme (one polysilicon layer and six copper metal layers). However, this invention is also applicable to other interconnection schemes such as 1P3M, 1P4M, 1P5M, 1P7M or 1P8M etc. 
     As previously described, the topmost level of the copper metal layers, i.e., M 6  is much thicker than M 5 , and thus M 5  has a higher sheet resistance (Rs). For example, M 6  has a thickness t 1  of about 0.85 micrometers (line width=0.36 micrometers; Rs=0.0212 Ω/cm2), and M 5  has a thickness t 2  of about 0.29 micrometers (line width=0.18 micrometers; Rs=0.0779 Ω/cm2). 
     Still referring to  FIG. 2 , the integrated circuit chip  1   a  further comprises a power or ground ring  402  that is formed in the aluminum layer over the first passivation layer  140 . The aluminum pad  302  and the aluminum power or ground ring  402  can be formed concurrently. The thickness t 3  of the aluminum power or ground ring  402  is ordinarily about 1.45 micrometers, which is much thicker than M 6  layer. Preferably, to efficiently distributing power, it is recommended that the line width (L) of the power or ground ring  402  is about 3.0 micrometers with a spacing (S) of about 2.0 micrometers (L/S=3/2). The line width of the aluminum power or ground ring  402  may range between 3 micrometers and 30 micrometers. 
     Since the aluminum power or ground ring  402  is thick, the sheet resistance of the aluminum power or ground ring  402  can be as low as about 0.0212 Ω/cm2 which is close to M 6  layer. The aluminum power or ground ring  402  may be electrically connected to the underlying copper trace line  404  through via  406 . According to the preferred embodiment of this invention, the via  406  preferably has a dimension of 3 micrometers or 3-micrometer×3-micrometer to efficiently distributing power. The copper trace line  404  is formed in M 6  layer and may function as part of the mesh interconnection network (not explicitly shown) for distributing power or ground signals to a circuit element  101  by way of, for example, the via stack  502 . 
     The mesh interconnection network, as previously mentioned, includes a plurality of orthogonal horizontal trace lines and longitudinal trace lines across the circuit block. According to the preferred embodiment, the aluminum layer over the passivation layer  140  may be utilized to define either the horizontal trace lines or longitudinal trace lines of the mesh interconnection network. 
     It is one kernel feature of this invention that the power or ground rings for distributing power or ground signals to a circuit block of the integrated circuit chip  1   a  are formed merely in the topmost level of the copper metal layers and in the aluminum layer over the passivation layer  140 . The aluminum layer over the passivation layer  140  is not only utilized to be a RDL for flip-chip or bump applications, but also is further utilized to form the power or ground signal routing. By doing this, M 5  layer can be eliminated or be spared for flexible signal routing. The sheet resistance of the Al layer over the passivation  140  is much lower than M 5  layer; thereby the IR drop is reduced. 
       FIG. 3  is a schematic, cross-sectional diagram illustrating the second preferred embodiment of the invention, wherein the same numerals designate like elements, layers or regions with the similar material and function. As shown in  FIG. 3 , likewise, the integrated circuit chip  1   b  comprises a semiconductor substrate  100 . Circuit elements (not explicitly shown in  FIG. 3 ) such as transistors, capacitors or memory cells are formed on the semiconductor substrate  100 . A number of inter-metal dielectric (IMD) layers are deposited over the semiconductor substrate  100 . For the sake of simplicity, only IMD layers  128 - 132  are shown. A first passivation layer  140  is deposited on the IMD layer  132  and covers the exposed Mn layer. 
     The integrated circuit chip  1   b  comprises n layers of copper metal interconnection (M 1 -Mn) and respective vias (V 1 -V n-1 ) which are fabricated using copper damascene processes or dual damascene processes, which are well known in the art and are thus not discussed further. A power/ground ring  502  is formed in combination with the Al layer and the Mn layer. A power/ground ring  602  is formed in the Mn−1 layer. The IR drop is reduced by parallel connecting the Al layer  504  with the underlying Mn layer  508  through the Al via  506 . By doing this, the sheet resistance of the power/ground ring  502  is decreased. 
       FIG. 4  is a schematic diagram showing the layout in accordance with the second preferred embodiment of this invention, wherein the same numerals designate like elements, layers or regions with similar material and function. As shown in  FIG. 4 , an integrated circuit chip  1   c  comprises a ground ring  508   a  for distributing V SS  signal and a power ring  508   b  for distributing V DD  signal. The parallel ground ring  508   a  and the power ring  508   b  are both formed in the Mn layer, i.e., the topmost copper metal layer of the integrated circuit chip  1   c.    
     Two exemplary tracing lines  702  and  802  of a mesh interconnection network, which are orthogonal to the ground ring  508   a  and the power ring  508   b , are formed in the Mn−1 layer. The orthogonal tracing line  702  is electrically connected to the overlying ground ring  508   a  through via  706 , which is formed between Mn−1 layer and Mn layer. The orthogonal tracing line  802  is electrically connected to the overlying power ring  508   b  through via  806 , which is formed between Mn−1 layer and Mn layer. 
     Aluminum wiring lines  504   a  is deposed right above and parallel to ground ring  508   a ; and aluminum wiring lines  504   a  is connected to ground ring  508   a  through via  506   a . Aluminum wiring lines  504   b  is deposed right above and parallel to power ring  508   b ; and aluminum wiring lines  504   b  is connected to power ring  508   b  through via  506   b . Preferably, the line width of the aluminum wiring lines  504   a  and  504   b  ranges between 3 micrometers and 30 micrometers with a spacing of about 20 micrometers. Preferably, the vias  506   a  and  506   b  have a dimension of 3-micrometer×3-micrometer, and the spacing between two adjacent vias  506   a  is about 3 micrometers. A first passivation layer (not explicitly shown in  FIG. 4 ) is interposed between the aluminum wiring lines and the power/ground ring. A second passivation layer such as silicon nitride or polyimide covers the aluminum wiring lines  504   a  and  504   b  and the first passivation layer. 
     Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.