Patent Publication Number: US-2023154921-A1

Title: Air spacer and capping structures in semiconductor devices

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is a divisional of U.S. patent application Ser. No. 17/006,167, titled “Air Spacer and Capping Structures in Semiconductor Devices,” filed Aug. 28, 2020, which claims the benefit of U.S. Provisional Patent Application No. 63/002,036, titled “Isolation Structures of Semiconductor Devices,” filed Mar. 30, 2020, each of which is incorporated by reference herein in its entirety. 
    
    
     BACKGROUND 
     With advances in semiconductor technology, there has been increasing demand for higher storage capacity, faster processing systems, higher performance, and lower costs. To meet these demands, the semiconductor industry continues to scale down the dimensions of semiconductor devices, such as metal oxide semiconductor field effect transistors (MOSFETs), including planar MOSFETs and fin field effect transistors (finFETs). Such scaling down has increased the complexity of semiconductor manufacturing processes. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Aspects of this disclosure are best understood from the following detailed description when read with the accompanying figures. 
         FIG.  1 A  illustrates an isometric view a semiconductor device with air spacer and capping structures, in accordance with some embodiments. 
         FIGS.  1 B- 1 I  illustrate cross-sectional views a semiconductor device with air spacer and capping structures, in accordance with some embodiments. 
         FIG.  2    is a flow diagram of a method for fabricating a semiconductor device with air spacer and capping structures, in accordance with some embodiments. 
         FIGS.  3 A- 18 C  illustrate top views and cross-sectional views of a semiconductor device with air spacer and capping structures at various stages of its fabrication process, in accordance with some embodiments. 
     
    
    
     Illustrative embodiments will now be described with reference to the accompanying drawings. In the drawings, like reference numerals generally indicate identical, functionally similar, and/or structurally similar elements. 
     DETAILED DESCRIPTION 
     The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the process for forming a first feature over a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. As used herein, the formation of a first feature on a second feature means the first feature is formed in direct contact with the second feature. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition does not in itself dictate a relationship between the various embodiments and/or configurations discussed. 
     Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper,” and the like may be used herein for ease of description to describe one element or feature&#39;s relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. 
     It is noted that references in the specification to “one embodiment,” “an embodiment,” “an example embodiment,” “exemplary,” etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Further, when a particular feature, structure or characteristic is described in connection with an embodiment, it would be within the knowledge of one skilled in the art to effect such feature, structure or characteristic in connection with other embodiments whether or not explicitly described. 
     It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by those skilled in relevant art(s) in light of the teachings herein. 
     As used herein, the term “high-k” refers to a high dielectric constant. In the field of semiconductor device structures and manufacturing processes, high-k refers to a dielectric constant that is greater than the dielectric constant of SiO 2  (e.g., greater than 3.9). 
     As used herein, the term “p-type” defines a structure, layer, and/or region as being doped with p-type dopants, such as boron. 
     As used herein, the term “n-type” defines a structure, layer, and/or region as being doped with n-type dopants, such as phosphorus. 
     As used herein, the term “nanostructured” defines a structure, layer, and/or region as having a horizontal dimension (e.g., along an X- and/or Y-axis) and/or a vertical dimension (e.g., along a Z-axis) less than, for example, 100 nm. 
     In some embodiments, the terms “about” and “substantially” can indicate a value of a given quantity that varies within 5% of the value (e.g., ±1%, ±2%, ±3%, ±4%, ±5% of the value). These values are merely examples and are not intended to be limiting. The terms “about” and “substantially” can refer to a percentage of the values as interpreted by those skilled in relevant art(s) in light of the teachings herein. 
     The fin structures disclosed herein may be patterned by any suitable method. For example, the fin structures may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Double-patterning or multi-patterning processes can combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fin structures. 
     The reliability and performance of semiconductor devices with FETs (e.g., finFETs or GAA FETs) have been negatively impacted by the scaling down of semiconductor devices. The scaling down has resulted in smaller electrical isolation regions (e.g., spacers and capping structures) between gate structures and source/drain (S/D) contact structures and/or between gate structures and interconnect structures. Such smaller electrical isolation regions may not adequately reduce parasitic capacitance between the gate structures and the S/D contact structures and/or between the gate structures and the interconnect structures. Further, the smaller electrical isolation regions may not adequately prevent current leakage between the gate structures and the S/D contact structures and/or between the gate structures and the interconnect structures, which can lead to degradation of the semiconductor device reliability and performance. 
     The present disclosure provides example semiconductor devices with FETs (e.g., finFETs or GAA FETs) having air spacers and air caps and provides example methods of forming such semiconductor devices. In some embodiments, the air spacers can be disposed between the sidewalls of the gate structures and the S/D contact structures and can extend along the width of the gate structures. In some embodiments, the air caps can be disposed between the conductive structures (e.g., metal lines and/or metal vias) of the interconnect structures and the underlying top surfaces of the gate structures. The air spacers and air caps provide electrical isolation between the gate structures and the S/D contact structures and/or between the gate structures and the interconnect structures with improved device reliability and performance. The low dielectric constant of air in air spacers and air caps can reduce the parasitic capacitance by about 20% to about 50% compared to semiconductor devices without air spacers and air caps. Further, the presence of air spacers and air caps minimizes current leakage paths between the gate structures and the S/D contact structures and/or between the gate structures and the interconnect structures. Reducing the parasitic capacitance and/or current leakage in the semiconductor devices can improve the device reliability and performance compared to semiconductor devices without air spacers and air caps. 
     A semiconductor device  100  having FETs  102 A- 102 B is described with reference to  FIGS.  1 A- 1 I , according to some embodiments.  FIG.  1 A  illustrates an isometric view of semiconductor device  100 , according to some embodiments.  FIG.  1 B  and  FIG.  1 C  illustrate cross-sectional views along respective lines A-A and B-B of semiconductor device  100  of  FIG.  1 A , according to some embodiments. Semiconductor device  100  can have different cross-sectional views along line A-A of  FIG.  1 A  as illustrated in  FIGS.  1 B and  1 D- 1 I , according to various embodiments. The discussion of elements in  FIGS.  1 A- 1 I  with the same annotations applies to each other, unless mentioned otherwise. The discussion of FET  102 A applies to FET  102 B, unless mentioned otherwise. FETs  102 A- 102 B can be n-type, p-type, or a combination thereof. 
     Semiconductor device  100  can be formed on a substrate  106 . Substrate  106  can be a semiconductor material, such as silicon, germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), silicon germanium carbide (SiGeC), and a combination thereof. Further, substrate  106  can be doped with p-type dopants (e.g., boron, indium, aluminum, or gallium) or n-type dopants (e.g., phosphorus or arsenic). 
     Referring to  FIGS.  1 A- 1 C , FET  102 A can include (i) a fin structure  108  extending along an X-axis, (ii) a gate structure  112  extending along a Y-axis, (iii) epitaxial regions  110 , (iv) inner spacers  114  having first and second inner spacers  113 A- 113 B, (v) outer spacers  116 , (vi) air spacers  118 , (vii) air cap  120 , (viii) air spacer seals  122 , (ix) air cap seal  124 , (x) source/drain (S/D) contact structures  126 , (xi) S/D capping layer  128 , and (xii) via structure  130 . Fin structure  108  can include fin recessed regions  108 A underlying epitaxial regions  110  and a fin raised region  108 B underlying gate structure  112 . In some embodiments, fin structure  108  can include a material similar to substrate  106 . 
     Epitaxial regions  110  can be grown on fin recessed regions  108 A and can be S/D regions of FET  102 A. Epitaxial regions  110  can include epitaxially-grown semiconductor material that can include the same material or a different material from the material of substrate  106 . Epitaxial regions  110  can be p- or n-type. In some embodiments, n-type epitaxial regions  110  can include SiAs, SiC, or SiCP and p-type epitaxial regions  110  can include SiGe, SiGeB, GeB, SiGeSnB, a III-V semiconductor compound, or a combination thereof. 
     S/D contact structures  126  can be disposed on epitaxial regions  110  and can be configured to electrically connect epitaxial regions  110  to other elements of FET  102 A and/or of the integrated circuit (not shown) through via structure  130 . In some embodiments, via structure  130  can be disposed on one of S/D contact structures  126  and S/D capping layer  128  can be disposed on another of S/D contact structures  126 . S/D capping layer  128  can electrically isolate S/D contact structure  126  from other overlying elements of FET  102 A. Each of S/D contact structures  126  can include a S/D contact plug  126 A and a silicide layer  126 B. S/D contact plugs  130  can include conductive materials, such as ruthenium (Ru), iridium (Ir), nickel (Ni), Osmium (Os), rhodium (Rh), Al, molybdenum (Mo), tungsten (W), cobalt (Co), and copper (Cu). In some embodiments, via structure  130  can include conductive materials, such as Ru, Co, Ni, Al, Mo, W, Ir, Os, Cu, and Pt. 
     In some embodiments, S/D capping layer  128  can include dielectric materials, such as silicon nitride (SiN), zirconium silicide (ZrSi), silicon carbon nitride (SiCN), zirconium aluminum oxide (ZrAlO), titanium oxide (TiO 2 ), tantalum oxide (Ta 2 O 5 ), zirconium oxide (ZrO 2 ), lanthanum oxide (La 2 O 3 ), zirconium nitride (ZrN), silicon carbide (SiC), zinc oxide (ZnO), silicon oxycarbide (SiOC), hafnium oxide (HfO 2 ), aluminum oxide (Al 2 O 3 ), silicon oxycarbonitride (SiOCN), Si, hafnium silicide (HfSi 2 ), aluminum oxynitride (AlON), yttrium oxide (Y 2 O 3 ), tantalum carbon nitride (TaCN), and silicon oxide (SiO 2 ). In some embodiments, S/D capping layer  128  can have a thickness along a Z-axis in a range from about 1 nm to about 50 nm. Below this range of thickness, S/D capping layer  128  may not adequately provide electrical isolation between S/D contact structure  126  and other overlying elements of FET  102 A. On the other hand, if the thickness is greater than 50 nm, the processing time (e.g., deposition time, polishing time, etc.) of S/D capping layer increases, and consequently increases device manufacturing cost. 
     Gate structure  112  can include a high-k gate dielectric layer  112 A and a conductive layer  112 B disposed on high-k gate dielectric layer  112 A. Conductive layer  112 B can be a multi-layered structure. The different layers of conductive layer  112 B are not shown for simplicity. Conductive layer  112 B ca include a work function metal (WFM) layer disposed on high-k dielectric layer  112 A, and a gate metal fill layer on the WFM layer. High-k gate dielectric layer can include a high-k dielectric material, such as HfO 2 , TiO 2 , hafnium zirconium oxide (HfZrO), Ta 2 O 3 , hafnium silicate (HfSiO 4 ), ZrO 2 , and zirconium silicate (ZrSiO 2 ). The WFM layer can include titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), tantalum aluminum (TaAl), tantalum aluminum carbide (TaAlC), and a combination thereof. The gate metal fill layer can include a suitable conductive material, such as W, Ti, silver (Ag), Ru, Mo, Cu, Co, Al, Ir, Ni, and a combination thereof. 
     Gate structure  112  can be electrically isolated from adjacent S/D contact structures  126  and/or via structure  130  by first inner spacers  113 A, outer spacers  116 , and air spacers  118 , as shown in  FIG.  1 B . Further, gate structure  112  can be electrically isolated from adjacent epitaxial regions  110  by first and second inners spacers  113 A- 113 B, as shown in  FIG.  1 C . In some embodiments, gate structure  112  can be further electrically isolated from overlying interconnect structures (e.g. metal line  142  as shown in  FIG.  1 H ) by air cap  120  and air cap seal  124 . 
     Each of inner spacers  113 A- 113 B, outer spacers  116 , and air spacers  118  extends along the width of gate structure  112  along a Y-axis. First inner spacers  113 A can be disposed on and in physical contact with the sidewalls of gate structure  112  and outer spacers  116  can be disposed on first inner spacers  113 A. In some embodiments, outer spacers  116  can be disposed on and in physical contact with the sidewalls of gate structure  112  when inner spacers  113 A- 113 B are not included in FET  102 A. Air spacers  118  can be interposed between outer spacers and etch stop layers (ESLs)  134 , which are configured to protect gate structure  112  and/or epitaxial regions  110  during processing of FET  102 A. 
     Air spacers  118  are cavities filled with air formed between outer spacers  116  and ESLs  134 . In some embodiments, the cavities of air spacers  118  can be sealed by air spacer seals  122 . Air spacer seals  122  can prevent materials from entering the cavities of air spacers  118  during the formation of layers overlying air spacers  118 . Similarly, air cap  120  is a cavity filled with air formed between gate structure  112  and air cap seal  124 . Air cap seal  124  can prevent materials from entering the cavity of air cap  120  during the formation of layers overlying air cap  120 . In some embodiments, air spacer seals  122  can extend into air cap  120  and can be suspended over gate structure  112 , as shown in  FIGS.  1 B- 1 C  or can be disposed on disposed on gate structure  112 , as shown in  FIG.  1 D . The different configurations of air spacer seals  122  within air cap  120  can be used to adjust the volume of air cap  120 . In some embodiments, portions of air spacer seals  122  can be disposed on ESLs  134  and the top surfaces of these portions of air spacer seals  122  can be substantially coplanar with the top surfaces of S/D capping layer  128  and via structure  130 , as shown in  FIGS.  1 B- 1 D . In some embodiments, these portions of air spacer seals  122  may be absent and the top surfaces of ESLs  134  is substantially coplanar with the top surfaces of S/D capping layer  128  and via structure  130 , as shown in  FIG.  1 E . 
     In some embodiments, S/D capping layer  128 , inner spacers  113 A- 113 B, outer spacers  116 , air spacer seals  122 , air cap seal  124 , and ESLs  134  can include an insulating material similar to or different from each other. In some embodiments, the insulating material can include SiN, ZrSi, SiCN, ZrAlO, TiO 2 , Ta 2 O 5 , ZrO 2 , La 2 O 3 , ZrN, SiC, ZnO, SiOC, (HfO 2 , Al 2 O 3 , SiOCN, Si, HfSi 2 , AlON, Y 2 O 3 , TaCN, SiO 3 , or a combination thereof. In some embodiments, each of first inner spacers  113 A, outer spacers  116 , and ESLs  134  can have a thickness along an X-axis substantially equal to or different from each other. In some embodiments, each of air spacers  118  can have a thickness along an X-axis equal to or greater than the thickness of each of first inner spacers  113 A, outer spacers  116 , and/or ESLs  134  along the X-axis. In some embodiments, each of air spacers  118  can have a thickness along an X-axis twice the thickness of each of outer spacers  116  along the X-axis. The thickness of each of first inner spacers  113 A, outer spacers  116 , air spacers  118 , and ESLs  134  can range from about 1 nm to about 10 nm. In some embodiments, air spacers  118  can have a height along a Z-axis equal to or greater than a height of gate structure  112  along the Z-axis and the height of air spaces  118  can range from about 1 nm to about 50 nm. 
     In some embodiments, the thickness of air spacer seals  122  disposed above air spacers  118  is substantially equal to the thickness of air spacers  118  along an X-axis. In some embodiments, the thickness of air spacer seals  122  disposed above ESLs  134  and within air cap  120  can be substantially equal to or greater than the thickness of ESLs  134  along an X-axis and can range from about 1 nm to about 15 nm. In some embodiments, air cap  120  can have a thickness T 1  substantially equal to or smaller than thickness T 2  of air cap seal  124 . Thickness T 1  can range from about 1 nm to about 15 nm and thickness T 2  can range from about 1 nm to about 25 nm. 
     The above discussed dimension ranges of first inner spacers  113 A, outer spacers  116 , air spacers  118 , air cap  120 , air spacer seals  122 , air cap seal  124 , and/or ESLs  134  provide adequate electrical isolation between gate structure and adjacent epitaxial regions  110 , S/D contact structure  126 , via structure  130 , and/or interconnect structures ((e.g. metal line  142  as shown in  FIG.  1 H ). Below the dimension ranges, first inner spacers  113 A, outer spacers  116 , air spacers  118 , air cap  120 , air spacer seals  122 , air cap seal  124 , and/or ESLs  134  may not adequately provide the electrical isolation to gate structure  112 . On the other hand, if the dimensions are higher than the above discussed ranges, the processing time (e.g., deposition time, etching time, etc.) for forming first inner spacers  113 A, outer spacers  116 , air spacers  118 , air cap  120 , air spacer seals  122 , air cap seal  124 , and/or ESLs  134  increases, and consequently increases device manufacturing cost. 
     In some embodiments, air spacers  118 , air cap  120 , air spacer seals  122 , and air cap seal  124  can have the structures shown in  FIG.  1 F  instead of the structures shown in  FIG.  1 B .  FIG.  1 F  illustrates the region of FET  102 A within area  103 A of  FIG.  1 B  for different configurations of air spacers  118 , air cap  120 , air spacer seals  122 , and air cap seal  124 . Air spacer seals  122  on ESLs  134  and air cap  120  can have rounded corners  122   c  with a radius of curvature of about 0.5 nm to about 5 nm, which can be a result of the etching rate used during the formation of air spacer seals  122 , which is described in further detail below. Air spacer seals  122  surrounding air spacers  118  can have thicknesses T 3  of about 0.5 nm to about 10 nm and seams  122   s  with lengths of about 0.5 nm to about 5 nm, which can be a result of the deposition rate used during the formation of air spacer seals  122 , which is described in further detail below. The deposition rate used for forming air spacer seals  122  can also form “necks”  122   n  with lengths of about 0.5 nm to about 5 nm along a Z-axis prior to forming seams  122   s . Similarly, the deposition rates used for forming air cap seal  124  can form “necks”  124   n  with lengths of about 0.5 nm to about 5 nm along a Z-axis prior to forming seams  124   s , as shown in  FIG.  1 F . 
     In some embodiments, FET  102 A can have nanostructured channel regions  138  with gate structure  112  surrounding each of nanostructured channel regions  138 , as shown in  FIG.  1 G , instead of raised fin region  108 B and gate structure  112  of  FIGS.  1 B- 1 F and  1 H- 1 I . Such gate structure  112  can be referred to as “gate-all-around (GAA) structure  112 ” and FET  102 A with GAA structure  112  can be referred to as “GAA FET  102 A.” Nanostructured channel regions  138  can include (i) an elementary semiconductor, such as Si or Ge; (ii) a compound semiconductor including a III-V semiconductor material; (iii) an alloy semiconductor including SiGe, germanium stannum, or silicon germanium stannum; or (iv) a combination thereof. The portions of gate structure  112  surrounding nanostructured channel regions  138  can be electrically isolated from adjacent epitaxial regions  110  by spacers  140 . Spacers  140  can include a material similar to outer spacers  116 . 
     In some embodiments, the structure of  FIG.  1 B  can have a metal line  142  of an interconnect structure, as shown in  FIG.  1 H  when via structure  130  is present or can have a dielectric layer  144  of the interconnect structure, as shown in  FIG.  1 I  when via structure  130  is not disposed on S/D structure  126 . 
     Semiconductor device  100  can further include interlayer dielectric (ILD) layer  132  and shallow trench isolation (STI) regions  136 . ILD layer  118  can be disposed on ESLs  134  and can include a dielectric material. STI regions  136  can include an insulating material. 
       FIG.  2    is a flow diagram of an example method  200  for fabricating FET  102 A of semiconductor device  100 , according to some embodiments. For illustrative purposes, the operations illustrated in  FIG.  2    will be described with reference to the example fabrication process for fabricating FET  102 A as illustrated in  FIGS.  3 A- 18 C .  FIGS.  3 A- 18 A  are top views of FET  102 A at various stages of fabrication, according to some embodiments.  FIGS.  3 B- 18 B and  3 C- 18 C  are views of regions  103 A- 103 B of  FIGS.  1 B- 1 C  at various stages of fabrication, according to some embodiments. Operations can be performed in a different order or not performed depending on specific applications. It should be noted that method  200  may not produce a complete FET  102 A. Accordingly, it is understood that additional processes can be provided before, during, and after method  200 , and that some other processes may only be briefly described herein. Elements in  FIGS.  3 A- 18 C  with the same annotations as elements in  FIGS.  1 A- 1 I  are described above. 
     In operation  205 , a polysilicon structure and epitaxial regions are formed on a fin structure and inner spacers are formed on the polysilicon structure. For example, as shown in  FIGS.  3 A- 3 C , a polysilicon structure  312  and a hard mask layer  346  can be formed on fin structure  108 . During subsequent processing, polysilicon structure  312  can be replaced in a gate replacement process to form gate structure  112 . Following the formation of spacers  114  along the sidewalls of polysilicon structure  312 , epitaxial regions  110  can be selectively formed on recessed fin regions  108 B, as shown in  FIG.  1 B . 
     Referring to  FIG.  2   , in operation  210 , outer spacers and sacrificial spacers are formed on the inner spacers. For example, as shown in  FIGS.  5 A- 5 C , outer spacers  116  and sacrificial spacers  518  can be formed on inner spacers  114 . The formation of outer spacers and sacrificial spacers can include sequential operations of (i) selectively etching portions of second inner spacers  113 B that are above fin structure  108 , as shown in  FIGS.  4 A- 4 C , (ii) selectively thinning down portions of first inner spacers  113 A that are above fin structure  108 , as shown in  FIGS.  4 A- 4 C , (iii) depositing and patterning outer spacers  116  on the structures of  FIGS.  4 A- 4 C , and (iv) depositing and patterning sacrificial spacers  518  on outer spacers  116  to form the structures of  FIGS.  5 A- 5 C . During subsequent processing, sacrificial spacers  518  are removed to form air spacers  118 . The patterning of outer spacers  116  and sacrificial spacers  518  can include a dry etching process with etchants, such as chlorine-based gas, oxygen, hydrogen, bromine-based gas, and a combination thereof. Sacrificial spacers  518  can include an insulating material different from the insulating material of first inner spacers  113 A, outer spacers  116 , S/D capping layers  128 , ILD layer  132 , and ESLs  134 . In some embodiments, portions of outer spacers on epitaxial regions  110  can have a thickness T 4  smaller than thickness T 5  of portions of outer spacers on first inner spacers  113 A. Thickness T 4 -T 5  can range from about 0.5 nm to about 10 nm. 
     Referring to  FIG.  2   , in operation  215 , an ILD layer and ESLs are formed on the sacrificial spacers. For example, as shown in  FIGS.  6 A- 6 C , ILD layer  132  and ESLs  134  can be formed on outer spacers  116 . The formation of ILD layer  132  and ESLs  134  can include sequential operations of (i) depositing ESLs  134  on the structures of  FIGS.  5 A- 5 C  using a chemical vapor deposition (CVD) process, (ii) depositing ILD layer  132  on ESLs  134  using a CVD process or a suitable dielectric material deposition process, and (iii) performing a chemical mechanical polishing (CMP) process to remove hard mask layer  346  and substantially coplanarize the top surfaces of polysilicon structure  312 , first inner spacers  113 A, outer spacers  116 , sacrificial spacers  518 , ESLs  134 , and ILD layer  132  with each other, as shown in  FIGS.  6 A- 6 C . 
     Referring to  FIG.  2   , in operation  220 , the polysilicon structure is replaced with a gate structure and a sacrificial cap is formed on the gate structure. For example, as shown in  FIGS.  7 A- 7 C , polysilicon structure  312  can be replaced with gate structure  112  and a sacrificial cap  720  can be formed on gate structure  112 . The formation of gate structure  112  can include sequential operations of (i) etching polysilicon structure  312  to form a cavity (not shown), (ii) depositing high-k gate dielectric layer  112 A within the cavity using a CVD process, an atomic layer deposition (ALD) process, or a suitable high-k dielectric material deposition process, (iii) depositing conductive layer  112 B on high-k gate dielectric layer  112 A using a CVD process, an atomic layer deposition (ALD) process, or a suitable conductive material deposition process, (iv) performing a CMP process to substantially coplanarize the top surface of gate structure  112  with the top surfaces of polysilicon structure  312 , first inner spacers  113 A, outer spacers  116 , sacrificial spacers  518 , ESLs  134 , and ILD layer  132 , and (v) etching back gate structure  112 , as shown in  FIGS.  7 B- 7 C . The etching back can include a dry etching process with etchants that have a higher etch selectivity for the materials of gate structure  112  than the materials of first inner spacers  113 A, outer spacers  116 , sacrificial spacers  518 , and ESLs  134 . The etchants can include chlorine-based gas, methane (CH 4 ), boron chloride (BCL 3 ), oxygen, or a combination thereof. 
     The formation of sacrificial cap  720  can include sequential operations of (i) etching back first inner spacers  113 A, outer spacers  116 , sacrificial spacers  518 , and ESLs  134 , as shown in  FIGS.  7 B- 7 C , (ii) depositing the material of sacrificial cap  720  on ILD layer  132  and the etched back gate structure  112 , first inner spacers  113 A, outer spacers  116 , sacrificial spacers  518 , and ESLs  134  using a CVD process or a suitable insulating material deposition process, and (iii) performing a CMP process to substantially coplanarize the top surface of sacrificial cap  720  with the top surface of ILD layer  132  to form the structures of  FIGS.  7 B- 7 C . The etching back can include a dry etching process with etchants that have a higher etch selectivity for the materials of first inner spacers  113 A, outer spacers  116 , sacrificial spacers  518 , and ESLs  134  than the materials of gate structure  112 . The etchants can include a hydrogen fluoride (HF) based gas, a carbon fluoride (C x F y ) based gas, or a combination thereof. 
     Referring to  FIG.  2   , in operation  225 , S/D contact structures are formed on the epitaxial regions. For example, as shown in  FIGS.  8 A- 8 C , S/D contact structures  126  can be formed on epitaxial regions  110 . The formation of S/D contact structures  126  can include sequential operations of (i) etching portions of ILD layer  132 , ESLs  134  outer spacers  116  and epitaxial regions  110  to form contact openings (not shown), (ii) forming silicide layers  126 B within the contact openings, as shown in  FIGS.  8 B- 8 C , (iii) filling the contact openings with the material(s) of S/D contact plugs  126 B using a CVD process or a suitable conductive material deposition process, (iv) performing a CMP process to substantially coplanarize the top surface of S/D contact plugs  126 B with the top surface of sacrificial cap  720  (not shown in  FIGS.  8 A- 8 C ; shown in  FIGS.  17 A- 17 C ), and (v) etching back S/D contact plugs  126 B to form S/D contact structures  126  shown in  FIGS.  8 B- 8 C . The etching back can include a dry etching process with etchants, such as chlorine-based gas, methane (CH 4 ), boron chloride (BCL 3 ), oxygen, and a combination thereof. 
     S/D contact structures  126  of  FIGS.  17 A- 17 C  are formed if S/D capping layers  128  and/or via structure  130  are not subsequently formed. On the other hand, S/D contact structures of  FIGS.  8 A- 8 C  are formed if S/D capping layers  128  and via structure  130  are subsequently formed. The formation of S/D capping layers  128  and via structure  130  can include sequential operations of (i) depositing the material of S/D capping layers  128  on the etched back S/D contact plugs  126 B using a CVD process or a suitable insulating material deposition process, (ii) performing a CMP process to substantially coplanarize the top surface of S/D capping layers  128  with the top surface of sacrificial cap  720 , (iii) etching a portion of S/D capping layers  128  to form a via opening (not shown), (iv) depositing the material of via structure  130  within the via opening using a CVD process, an atomic layer deposition (ALD) process, or a suitable conductive material deposition process, and (v) performing a CMP process to substantially coplanarize the top surface of via structure  130  with the top surface of sacrificial cap  720 , as shown in  FIGS.  8 A- 8 C . 
     Referring to  FIG.  2   , in operation  230 , air spacers are formed between the outer spacers and the ESLs. For example, as shown in  FIGS.  10 A- 10 C , air spacers  118  can be formed between outer spacers  116  and the ESLs  134 . The formation of air spacers can include sequential operations of (i) etching back sacrificial cap  720 , as shown  FIGS.  9 A- 9 C  and (ii) removing sacrificial spacers  518 , as shown in  FIGS.  10 A- 10 C . In some embodiments, the etching back of sacrificial cap  720  and the removal of sacrificial spacers  518  can include using a chemical etching process with similar etchants, such as chlorine-based gas, hydrogen, oxygen, fluorine-based gas, and a combination thereof, but with different concentrations of the etchants and at different etching temperatures. The etch selectivity of the etchants for the materials of sacrificial cap  720  and sacrificial spacers  518  are dependent on the etchant concentration and etching temperature. The etchants used for selectively etching sacrificial cap  720  have a lower hydrogen concentration than the etchants used for selectively removing sacrificial spacers  518 . In addition, the temperature (e.g., between about 30° C. and about 150° C.) used for selectively etching sacrificial cap  720  is lower than the temperature used for selectively removing sacrificial spacers  518 . In some embodiments, the removal of sacrificial spacers  518  can include using a chemical etching process with etchants, such as helium, hydrogen, oxygen, fluorine-based gas, and a combination thereof. 
     Referring to  FIG.  2   , in operation  235 , air spacer seals are formed on the air spacers, the sacrificial cap, and the ESLs. For example, as shown in  FIGS.  12 A- 12 C , air spacer seals  122  can be formed on air spacers  118 , sacrificial cap  720 , and ESLs  134 . The formation of air spacer seals  122  can include sequential operations of (i) depositing the material of air spacer seals  122  on the structures of  FIGS.  10 A- 10 C  to form a sealing layer  122 *, as shown in  FIGS.  11 A- 11 C  and (ii) etching sealing layer  122 * to form the structures of  FIGS.  12 A- 12 C . In some embodiments, the deposition of sealing layer  122 * is performed at a deposition rate of about 1 nm/min to about 5 nm/min and at a deposition temperature of about 100° C. to about 400° C. to prevent any conformal deposition of the material of air spacer seals  122  within air spacers  118 . If the material of air spacer seals  122  is deposited at a deposition rate slower than about 1 nm/min and at a deposition temperature lower than about 100° C., air seals  122  may be formed within air spacers  118  as discussed above with reference to  FIG.  1 F . In some embodiments, the etching of sealing layer  122 * can include an anisotropic dry etching process at a temperature of about 50° C. to about 100° C. with etchants, such as chlorine-based gas, fluorine-based gas, oxygen, and a combination thereof. 
     Referring to  FIG.  2   , in operation  240 , an air cap and an air cap seal are formed on the gate structure. For example, as shown in  FIGS.  14 A- 14 C , air cap  120  and air cap seal  124  can be formed on gate structure  112 . The formation of air cap  120  can include removing sacrificial cap  720  to form the structures of  FIGS.  13 A- 13 C . In some embodiments, the removal of sacrificial cap  720  can include using an isotropic chemical etching process with etchants, such as chlorine-based gas, hydrogen, oxygen, fluorine-based gas, and a combination thereof at an etching temperature of about 30° C. to about 150° C. 
     The formation of air cap seal  124  can include sequential operations of (i) depositing the material of air cap seal  124  on the structures of  FIGS.  12 A- 12 C  and (ii) performing a CMP process to substantially coplanarize the top surface of air cap seal  124  with the top surface of ILD layer  132 , as shown in  FIGS.  14 A- 14 C . Similar to the deposition of the material of air spacer seals  122 , the material of air cap seal  124  can be deposited at a deposition rate of about 1 nm/min to about 5 nm/min and at a deposition temperature of about 100° C. to about 400° C. to prevent any conformal deposition of the material within air cap  120 . 
     In some embodiments, the structures of  FIGS.  15 A- 15 C  with the top surfaces of ESLs  134  substantially coplanar with the top surfaces of ILD layer  132  can be formed if ESLs  134  are not etched back during the formation of sacrificial cap  720  in operation  220 . 
     In some embodiments, the structures of  FIGS.  16 A- 16 C  with cylindrical via structure  130  can be formed if cylindrical via openings are formed within S/D capping layer  128  during the formation of via structure  130  in operation  225 . 
     In some embodiments, the structures of  FIGS.  17 A- 17 C  with the top surfaces of S/D contact plugs  126 A substantially coplanar with the top surfaces of ILD layer  132  and air cap seal  124  can be formed if S/D capping layer  128  and via structure  130  are not formed in operation  225 . 
     In some embodiments, the structures of  FIGS.  18 A- 18 C  with air spacer seals  122  disposed on gate structure  112  can be formed if sacrificial cap  720  is removed instead of etching back during the formation of air spacers  118  in operation  230 . 
     The present disclosure provides example semiconductor devices (e.g., semiconductor device  100 ) with FETs (e.g., FET  102 A or GAA FET  102 A) having air spacers (e.g., air spacers  118 ) and air caps (e.g., air cap  120 ) and provides example methods (e.g., method  200 ) of forming such semiconductor devices. In some embodiments, the air spacers can be disposed between the sidewalls of gate structures (e.g., gate structure  112 ) and S/D contact structures (e.g., S/D contact structures  126 ) and can extend along the width of the gate structures. In some embodiments, the air caps can be disposed between the conductive structures (e.g., metal line  142 ) of the interconnect structures and the underlying top surfaces of the gate structures. The air spacers and air caps provide electrical isolation between the gate structures and the S/D contact structures and/or between the gate structures and the interconnect structures with improved device reliability and performance. The low dielectric constant of air in air spacers and air caps can reduce the parasitic capacitance by about 20% to about 50% compared to semiconductor devices without air spacers and air caps. Further, the presence of air spacers and air caps minimizes current leakage paths between the gate structures and the S/D contact structures and/or between the gate structures and the interconnect structures. Reducing the parasitic capacitance and/or current leakage in the semiconductor devices can improve the device reliability and performance compared to semiconductor devices without air spacers and air caps. 
     In some embodiments, a semiconductor device includes a substrate and a fin structure disposed on the substrate. The fin structure includes a first fin portion and a second fin portion. The semiconductor device further includes a source/drain (S/D) region disposed on the first fin portion, a contact structure disposed on the S/D region, a gate structure disposed on the second fin portion, an air spacer disposed between a sidewall of the gate structure and the contact structure, a cap seal disposed on the gate structure, and an air cap disposed between a top surface of the gate structure and the cap seal. 
     In some embodiments, a semiconductor device includes a substrate, a fin structure with first and second fin portions disposed on the substrate, a nanostructured channel region disposed on the first fin portion, a gate-all-around (GAA) structure surrounding the nanostructured channel region, a source/drain (S/D) region disposed on the second fin portion, an interlayer dielectric (ILD) layer disposed on the S/D region, an air spacer disposed between the gate structure and the ILD layer, a cap seal disposed on the gate structure, wherein top surfaces of the cap seal and the ILD layer are substantially coplanar with each other, and an air cap disposed between a top surface of the gate structure and the cap seal. 
     In some embodiments, a method includes forming a polysilicon structure on a fin structure, forming an epitaxial region on the fin structure, replacing the polysilicon structure with a gate structure, forming a contact structure on the epitaxial region, forming an air spacer between the gate structure and the contact structure, forming a spacer seal on the air spacer, forming an air cap on the gate structure, and forming a cap seal on the air cap and the spacer seal. 
     The foregoing disclosure outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.