Patent Publication Number: US-2021175368-A1

Title: Transient-voltage-suppression diode structure and manufacturing method thereof

Description:
FIELD OF THE INVENTION 
     The present disclosure relates to a diode structure, and more particularly to a transient-voltage-suppression diode structure and a manufacturing method thereof. 
     BACKGROUND OF THE INVENTION 
     A transient-voltage-suppression diode, also called as a TVS diode, is an electronic device used to protect electronics from voltage spikes induced on connected wires. In recent years, as the development of electronic systems has become more sophisticated, the demand for TVS device has become more and more urgent. 
     A conventional TVS device includes a Zener diode utilized to conduct the current when the device is collapsed, so that the current does not flow into the protected circuit. The Zener diode has characteristics such as large leakage current and large junction capacitance. For being applicable of the TVS device, the Zener diode tends to develop in low voltage applications. 
       FIG. 1  is a cross sectional view illustrating a conventional TVS diode structure. In the embodiment, a Zener diode is served as a protection mechanism for the transient-voltage-suppression device. As shown, the TVS device  1  includes a bottom metal layer  11  connected to a ground terminal GND, a P+ type base layer  12 , an N type epitaxial layer  13 , an N+ type buried layer  14 , an N− type epitaxial layer  15 , an interlayer dielectric (ILD) layer  16 , a top metal layer  17  and a passivation layer  18  stacked sequentially. The top metal layer  17  is configured to form an input-and-output terminal I/O and a working-voltage terminal Vcc. An N+ type implant layer  20  and a P+ type implant layer  21  spatially corresponding to the input-and-output terminal I/O are embedded in the N− type epitaxial layer  15  and are connected to the input-and-output terminal I/O. An N+ type implant layer  22  and a deep N+ type implant layer  23  spatially corresponding to the working-voltage terminal Vcc are embedded in the N− type epitaxial layer  15  and are isolated through an oxide isolation portion  19 . Notably, in the conventional TVS device  1 , the voltage of the working-voltage terminal Vcc is related to the Zener diode constructed by the P+ type base layer  12  and the N type epitaxial layer  13 . However, when the thickness of the N− type epitaxial layer  15  is very thick, it is difficult to increase the concentration of the N+ type implant layer  22  and the deep N+ type implant layer  23  by a general doping and drive-in procedure. Thus, it is difficult to obtain a Zener diode structure having a low breakdown voltage. 
     Therefore, there is a need of providing a transient-voltage-suppression diode structure and a manufacturing method thereof to address the above issues encountered by the prior arts and obtain a Zener diode structure having a low breakdown voltage. 
     SUMMARY OF THE INVENTION 
     An object of the present disclosure is to provide a transient-voltage-suppression diode structure and a manufacturing method thereof. By utilizing a plurality of polycrystalline plugs, it is beneficial to solve the problem that it is difficult to control and increase the concentration in the transient-voltage-suppression diode structure by the general doping and drive-in procedure. The structure of the polycrystalline plugs is helpful to reduce the distance of deep implantation and avoid the problem of concentration reduction after drive-in procedure. The difficulty of the manufacturing process is reduced effectively. In addition, the structure of the plurality of polycrystalline plugs is further helpful to reduce the parasitic resistance of, for example the N− type epitaxial layer, so as to improve the performance of the transient-voltage-suppression diode structure. 
     In accordance with an aspect of the present disclosure, a transient-voltage-suppression diode structure is provided and includes a substrate, at least one N− type epitaxial layer, a first metal layer, a first N+ type implant layer, a deep N+ type implant layer and a plurality of polycrystalline plugs. The at least one N− type epitaxial layer is disposed on the substrate. The first metal layer is disposed on the at least one N− type epitaxial layer and is configured to form a working-voltage terminal. The first N+ type implant layer spatially corresponds to the working-voltage terminal and is embedded in the at least one N− type epitaxial layer. The first N+ type implant layer is configured to connect to the working-voltage terminal of the first metal layer. The deep N+ type implant layer spatially corresponds to the working-voltage terminal and is embedded in the at least one N− type epitaxial layer. The deep N+ type implant layer is spaced apart from the first N+ type implant layer at a separation distance. The plurality of polycrystalline plugs spatially corresponds to the working-voltage, are embedded in the at least one N− type epitaxial layer, and pass through the first N+ type implant layer. Each polycrystalline plug includes a first end and a second end opposite to each other. The first end is in contact with the working-voltage terminal, and the second end at least partially passes through the deep N+ type implant layer and is in contact with the deep N+ type implant layer. 
     In an embodiment, the substrate includes a P+ type base layer and an N type epitaxial layer. The N type epitaxial layer is disposed on the P+ type base layer and connected to the at least one N− type epitaxial layer. 
     In an embodiment, the substrate further includes a second metal layer connected to the P+ type base layer and opposite to the first metal layer, wherein the second metal layer is configured to form a ground terminal. 
     In an embodiment, the transient-voltage-suppression diode structure further includes an interlayer dielectric layer disposed between the at least one N− type epitaxial layer and the first metal layer. 
     In an embodiment, the first metal layer is further configured to form an input-and-output terminal, and the transient-voltage-suppression diode structure further includes a second N+ type implant layer and a P+ type implant layer embedded in the at least one N− type epitaxial layer, respectively. The input-and-output terminal passes through the interlayer dielectric layer and is connected to the second N+ type implant layer and the P+ type implant layer, respectively. 
     In an embodiment, the transient-voltage-suppression diode structure further includes an N+ type buried layer disposed between the N type epitaxial layer and the at least one N− type epitaxial layer. The N+ type buried layer spatially corresponds to the P+ type implant layer and the plurality of polycrystalline plugs. 
     In an embodiment, the transient-voltage-suppression diode structure further includes a passivation layer disposed on the first metal layer and partially exposing the first metal layer to define the working-voltage terminal and the input-and-output terminal. 
     In an embodiment, at least one oxide isolation portion is disposed between the second N+ type implant layer and the P+ type implant layer. The at least one oxide isolation portion passes through the at least one N− type epitaxial layer, the N type epitaxial layer and a part of the P+ type base layer. 
     In accordance with another aspect of the present disclosure, a manufacturing method of a transient-voltage-suppression diode structure is provided and incudes steps of: (a) providing a substrate; (b) forming at least one N− type epitaxial layer disposed on the substrate; (c) forming a first N+ type implant layer embedded in the at least one N− type epitaxial layer; (d) partially etching the at least one N− type epitaxial layer and the first N+ type implant layer to form a plurality of trenches passing through the first N+ type implant layer and a part of the at least one N− type epitaxial layer; (e) forming a deep N+ type implant layer embedded in the at least one N− type epitaxial layer and spaced apart from the first N+ type implant layer at a separation distance; (f) filling the plurality of trenches with a polycrystalline material to form a plurality of polycrystalline plugs, which are embedded in the at least one N− type epitaxial layer and pass through the first N+ implant layer; and (g) forming a first metal layer disposed on the at least one N− type epitaxial layer, wherein a part of the first metal layer spatially corresponding to the first N+ type implant layer, the plurality of crystalline plugs and the deep N+ type implant layer is configured to form a working-voltage terminal, wherein each polycrystalline plug comprises a first end and a second end opposite to each other, wherein the first end is in contact with the working-voltage terminal, and the second end at least partially passes through the deep N+ type implant layer and is in contact with the deep N+ type implant layer. 
     In an embodiment, the step (b) further includes a step of (b0) forming an N+ type buried layer, wherein the N+ type buried layer is disposed between the substrate and the at least one N− type epitaxial layer. 
     In an embodiment, the step (c) further includes a step of (c0) forming a second N+ type implant layer and a P+ type implant layer, respectively, which are embedded in the at least one N− type epitaxial layer, wherein a part of the first metal layer spatially corresponding to the second N+ type implant layer and the P+ type implant layer is configured to form an input-and-output terminal, wherein the input-and-output terminal passes through an interlayer dielectric layer and is connected to the second N+ type implant layer and the P+ type implant layer, respectively. 
     In an embodiment, the manufacturing method of the transient-voltage-suppression diode structure further includes a step of (h) forming a passivation layer disposed on the first metal layer and partially exposing the first metal layer to define the working-voltage terminal and the input-and-output terminal. 
     In an embodiment, the substrate includes a P+ type base layer and an N type epitaxial layer, wherein the N type epitaxial layer is disposed on the P+ type base layer and connected to the at least one N− type epitaxial layer. 
     In an embodiment, the step (d) further includes a step of (d0) partially etching the at least one N− type epitaxial layer and the substrate and filling with an oxide material to form at least one oxide isolation portion, wherein the at least one oxide isolation portion passes through the at least one N− type epitaxial layer, the N type epitaxial layer and a part of the P+ type base layer. 
     In an embodiment, the step (d) further includes a step of (d1) forming an interlayer dielectric layer disposed on the at least one N− type epitaxial layer. 
     In an embodiment, the manufacturing method of the transient-voltage-suppression diode structure further includes a step of (i) forming a second metal layer connected to the P+ type base layer, wherein the second metal layer is opposite to the first metal layer and is configured to form a ground terminal. 
     The above contents of the present disclosure will become more readily apparent to those ordinarily skilled in the art after reviewing the following detailed description and accompanying drawings, in which: 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a cross sectional view illustrating a conventional TVS diode structure; 
         FIG. 2  is a cross sectional view illustrating a transient-voltage-suppression diode structure according to an embodiment of the present disclosure; 
         FIGS. 3A to 3I  are cross sectional views illustrating the transient-voltage-suppression diode structure at several manufacturing stages according to the embodiment of the present disclosure; and 
         FIGS. 4A and 4B  are a flow chart showing a manufacturing method of a transient-voltage-suppression diode structure according to an embodiment of the present disclosure. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     The present disclosure will now be described more specifically with reference to the following embodiments. It should be noted that the following descriptions of preferred embodiments of this disclosure are presented herein for purpose of illustration and description only. It is not intended to be exhaustive or to be limited to the precise form disclosed. 
       FIG. 2  is a cross sectional view illustrating a transient-voltage-suppression diode structure according to an embodiment of the present disclosure. In the embodiment, the transient-voltage-suppression diode structure  3  includes a substrate  30 , at least one N− type epitaxial layer  35 , a first metal layer  37 , a first N+ type implant layer  42 , a deep N+ type implant layer  43  and a plurality of polycrystalline plugs  44 . The at least one N− type epitaxial layer  35  is disposed on the substrate  30 . Preferably but not exclusively, in the embodiment, the substrate  30  includes a P+ type base layer  32  and an N type epitaxial layer  33 . The N type epitaxial layer  33  is disposed on the P+ type base layer  32  and connected to the at least one N− type epitaxial layer  35 . In addition, the transient-voltage-suppression diode structure  3  further includes an N+ type buried layer  34  disposed between the N type epitaxial layer  33  and the at least one N− type epitaxial layer  35 . The first metal layer  37  is disposed on the at least one N− type epitaxial layer  35  and is configured to form a working-voltage terminal Vcc and an input-and-output terminal I/O, respectively. In the embodiment, the transient-voltage-suppression diode structure  3  further includes an interlayer dielectric layer  36  disposed between the first metal layer  37  and the at least one N− type epitaxial layer  35 . 
     In the embodiment, the transient-voltage-suppression diode structure  3  further includes a passivation layer  38  disposed on the first metal layer  37  and partially exposing the first metal layer  37  to define the working-voltage terminal Vcc and the input-and-output terminal I/O, respectively. Certainly, the present disclosure is not limited thereto. In the embodiment, the structures of the first N+ type implant layer  42 , the deep N+ type implant layer  43  and the plurality of polycrystalline plugs  44  are all corresponding to the working-voltage terminal Vcc of the first metal layer  37 . Preferably but not exclusively, the first N+ type implant layer  42  spatially corresponding to the working-voltage terminal Vcc is embedded in the at least one N− type epitaxial layer  35 , to connect to the working-voltage terminal Vcc of the first metal layer  37 . The deep N+ type implant layer  43  spatially corresponding to the working-voltage terminal Vcc is embedded in the at least one N− type epitaxial layer  35 , and is connected with the N+ type buried layer  34 . Moreover, the deep N+ type implant layer  43  is spaced apart from the first N+ type implant layer  42  at a separation distance D. In other words, comparing to the first N+ type implant layer  42 , the deep N+ type implant layer  43  is further embedded in the at least one N− type epitaxial layer  35  with a depth equal to the separation distance D, and is connected to the N+ type buried layer  34 . 
     Notably, the plurality of polycrystalline plugs  44  spatially correspond to the working-voltage terminal Vcc of the first metal layer  37  and are embedded in the at least one N− type epitaxial layer  35 . Moreover, the plurality of polycrystalline plugs  44  pass through the interlayer dielectric layer  36  and the first N+ type implant  42 . In the embodiment, each polycrystalline plug  44  includes a first end  44   a  and a second end  44   b  opposite to each other. The first end  44   a  is in contact with the working-voltage terminal Vcc, and the second end  44   b  at least partially passes through the deep N+ type implant layer  43  and is in contact with the deep N+ type implant layer  43 . Since the structure of the plurality of polycrystalline plugs  44  pass through the first N+ implant layer  42 , it is beneficial to control and increase the concentration of the deep N+ type implant layer  43  relative to the at least one N− type epitaxial layer  35  by a general doping and drive-in procedure, so as to obtain a Zener diode structure having a low breakdown voltage. In addition, the deep N+ type implant layer  43  is further electrically connected through the plurality of polycrystalline plugs  44 , and it is beneficial to reduce the parasitic resistance of the at least one N− type epitaxial layer  35 . Namely, by utilizing a plurality of polycrystalline plugs  44 , it is beneficial to solve the problem that it is difficult to control and increase the concentration for example of the deep N+ type implant layer  43  in the transient-voltage-suppression diode structure  3  by the general doping and drive-in procedure. At the same time, the structure of the polycrystalline plugs  44  is helpful to reduce the distance of deep implantation for the deep N+ type implant layer  43 , and avoid the problem of concentration reduction after drive-in procedure. The difficulty of the manufacturing process is reduced effectively. In addition, the structure of the plurality of polycrystalline plugs  44  is further helpful to reduce the parasitic resistance of, for example the at least one N− type epitaxial layer  35 , so as to improve the performance of the transient-voltage-suppression diode structure  3 . 
     In the embodiment, the substrate  30  further includes a second metal layer  31  connected to the P+ type base layer  32  and opposite to the first metal layer  37 . The second metal layer  31  is configured to form a ground terminal GND. On the other hand, it is noted that the transient-voltage-suppression diode structure  3  further includes a second N+ type implant layer  40  and a P+ type implant layer  41  spatially corresponding to the input-and-output terminal I/O of the first metal layer  37 . The second N+ type implant layer  40  and the P+ type implant layer  41  are embedded in the at least one N− type epitaxial layer  35 , respectively. The input-and-output terminal I/O passes through the interlayer dielectric layer  36  and is connected to the second N+ type implant layer  40  and the P+ type implant layer  41 , respectively. Moreover, the N+ type buried layer  34  spatially corresponds to the P+ implant layer  41  and the plurality of polycrystalline plugs  44 . In the embodiment, at least one oxide isolation portion  39  is disposed between the second N+ type implant layer  40  and the P+ type implant layer  41 . The at least one oxide isolation portion  39  passes through the at least one N− type epitaxial layer  35 , the N type epitaxial layer  33  and a part of the P+ type base layer  32 . In addition, preferably but not exclusively, the at least one oxide isolation portion  39  is served as a boundary to define the transient-voltage-suppression diode structure  3 . It is not an essential feature to limit the present disclosure, and not redundantly described herein. Notably, the numbers and the arrangement of the P+ type implant layer  41 , the second N+ type implant layer  40 , the plurality of polycrystalline plugs  44  and the oxide isolation portion  39  are adjustable according to the practical requirements. The present disclosure is not limited thereto. 
     According to the aforementioned transient-voltage-suppression diode structure  3 , the present disclosure also discloses a manufacturing method of the transient-voltage-suppression diode structure  3 .  FIGS. 3A to 3I  are cross sectional views illustrating the transient-voltage-suppression diode structure at several manufacturing stages according to the embodiment of the present disclosure.  FIGS. 4A and 4B  are a flow chart showing a manufacturing method of a transient-voltage-suppression diode structure according to an embodiment of the present disclosure. Please refer to  FIGS. 2, 3A to 31  and  FIGS. 4A and 4B . Firstly, in the step S 1 , a substrate  30  is provided. As shown in  FIG. 3A , the substrate  30  includes a P+ type base layer  32  and an N type epitaxial layer  33 . The N type epitaxial layer  33  is disposed on the P+ type base layer  32 . Then, in the step S 2 , an N+ type buried layer  34  is formed on the N type epitaxial layer  33  by for example but not limited to an implantation and drive-in procedure, as shown in  FIG. 3B . In the step S 3 , at least one N− type epitaxial layer  35  is formed and disposed on the N type epitaxial layer  33  of the substrate  30 , so that the N+ type buried layer  34  is disposed between the N type epitaxial layer  33  of the substrate and the at least one N− type epitaxial layer  35 , and the N type epitaxial layer  33  is connected to the at least one N− type epitaxial layer  35 , as shown in  FIG. 3C . 
     Thereafter, in the step S 4 , a first N+ type implant layer  42 , a second N+ type implant layer  40  and a P+ type implant layer  41  are formed in the at least one N− type epitaxial layer  35  by for example but not limited to an implantation procedure, respectively, so as to be embedded in the at least one N− type epitaxial layer  35 , as shown in  FIG. 3D . In the embodiment, the first N+ type implant layer  42  spatially corresponds to a working-voltage terminal Vcc. The second N+ type implant layer  40  and the P+ type implant layer  41  spatially correspond to an input-and-output terminal I/O (referred to  FIG. 2 ). In the step S 5 , both of the at least one N− type epitaxial layer  35  and the substrate  30  are partially etched by an etching procedure and an oxide material is filled, so as to form at least one oxide insulation portion  39 , as shown in  FIG. 3E . Preferably but not exclusively, in the embodiment, the at least one oxide insulation portion  39  passes through the at least one N− type epitaxial layer  35 , the N+ type buried layer  34 , the N type epitaxial layer  33  and a part of the P+ type base layer  32 . Moreover, in the embodiment, an interlayer dielectric layer  36  is further formed on the at least one N− type epitaxial layer  35 . The interlayer dielectric layer  36  is formed to define the connection regions of the first N+ type implant layer  42 , the second N+ type implant layer  40  and the P+ type implant layer  41 . The present disclosure is not limited thereto and not redundantly described herein. 
     Then, in the step S 6 , both of the at least one N-type epitaxial layer  35  and the first N+ type implant layer  42  are partially etched by an etching procedure to form a plurality of trenches  44   c  passing through the first N+ type implant layer  42  and a part of the at least one N− type epitaxial layer  35 , as shown in  FIG. 3F . In the step S 7 , an implantation procedure is performed through the plurality of trenches  44   c , and a deep N+ type implant layer  43  is formed at the bottom end of the plurality of trenches  44   c . Consequently, the deep N+ type implant layer  43  is embedded in the at least one N− type epitaxial layer  35  and is spaced apart from the first N+ type implant layer  42  at a separation distance D, as shown in  FIG. 3G . Notably, since the implantation procedure is performed through the plurality of trenches  44   c , it is helpful to reduce the distance of deep implantation for the deep N+ type implant layer  43 , and solves the problem of controlling and increasing the implant concentration. At the same time, the problem of concentration reduction after drive-in procedure is avoided. The difficulty of the manufacturing process is reduced effectively. Thereafter, in the step S 8 , the plurality of trenches are filled with a polycrystalline material to form a plurality of polycrystalline plugs  44 , which are embedded in the at least one N− type epitaxial layer  35  and pass through the first N+ implant layer  42 , as shown in  FIG. 3H . Preferably but not exclusively, in the embodiment, a drive-in procedure for the deep N+ type implant layer  43 , the first N+ type implant layer  42 , the second N+ type implant layer  40  and P+ type implant layer  41  is performed after the plurality of polycrystalline plugs  44  are formed. The present disclosure is not limited thereto. It is noted that the plurality of polycrystalline plugs  44  are connected between the deep N+ type implant layer  43  and the first N+ implant layer  42 , it is helpful to reduce the parasitic resistance of the at least one N− type epitaxial layer  35 , so as to improve the performance of the transient-voltage-suppression diode structure  3 . 
     Finally, in the step S 9 , a first metal layer  37  is formed and disposed on the at least one N− type epitaxial layer and the interlayer dielectric layer  36 . In the embodiment, a part of the first metal layer  37  spatially corresponding to the first N+ implant layer  42 , the plurality of polycrystalline plugs  44  and the deep N+ type implant layer  43  is configured to form the working-voltage terminal Vcc. In the embodiment, each polycrystalline plug  44  includes a first end  44   a  and a second end  44   b  opposite to each other. The first end  44   a  is in contact with the working-voltage terminal Vcc, and the second end  44   b  at least partially passes through the deep N+ type implant layer  43  and is in contact with the deep N+ type implant layer  43 . In other embodiment, the interlayer dielectric layer  36  is formed before the first metal layer  37 , so as to define the connection regions of the first metal layer  37 , which are connected to the first N+ type implant layer  42 , the second N+ type implant layer  40  and the P+ type implant layer  41 . The present disclosure is not limited thereto. 
     In the embodiment, the manufacturing method of the transient-voltage-suppression diode structure  3  further includes a step S 10 . In the step S 10 , a passivation layer  38  is formed and disposed on the first metal layer  37  and partially exposing the first metal layer  37  to define the working-voltage terminal Vcc and the input-and-output terminal I/O, as shown in  FIG. 3I . In addition to the first metal layer  37 , a second metal layer  31  is further formed on another side opposite to the first metal layer  37 . The second metal layer  31  is connected to the P+ type base layer  32  of the substrate  30  and is configured to form the ground terminal GND, as shown in  FIG. 2 . Certainly, the forming procedures of the interlayer dielectric layer  36 , the first metal layer  37 , the passivation layer  38  and the second metal layer  31  are adjustable according to the practical requirement. The present disclosure is not limited thereto, and not be redundantly described herein. 
     In summary, the present disclosure provides a transient-voltage-suppression diode structure and a manufacturing method thereof. By utilizing a plurality of polycrystalline plugs, it is beneficial to solve the problem that it is difficult to control and increase the concentration in the transient-voltage-suppression diode structure by the general doping and drive-in procedure. The structure of the polycrystalline plugs is helpful to reduce the distance of deep implantation and avoid the problem of concentration reduction after drive-in procedure. The difficulty of the manufacturing process is reduced effectively. In addition, the structure of the plurality of polycrystalline plugs is further helpful to reduce the parasitic resistance of, for example the N− type epitaxial layer, so as to improve the performance of the transient-voltage-suppression diode structure. 
     While the disclosure has been described in terms of what is presently considered to be the most practical and preferred embodiments, it is to be understood that the disclosure needs not be limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims which are to be accorded with the broadest interpretation so as to encompass all such modifications and similar structures.