Patent Publication Number: US-11646662-B2

Title: Reference buffer

Description:
BACKGROUND 
     Successive approximation register (SAR) analog-to-digital converters (ADCs) are common in multi-channel data acquisition systems, such as ultrasound and other medical imaging systems, manufacturing inspection and quality control systems, and temperature and stress sensing systems, among others. In an SAR ADC, a reference voltage output by a buffer is used to charge capacitors during a HOLD or CONVERT phase, which can cause the reference voltage to dip rather than maintain a constant value. Some reference buffers include an error amplifier and a capacitor to help correct for the dips in the reference voltage and to help maintain the level or DC reference voltage with the desired accuracy. However, the error amplifier and capacitor occupy a large area of the integrated circuit and consume large amounts of power. In addition, the error amplifier adjusts the level or DC value of the reference voltage based on the time average value of the reference voltage, which includes transient dips. Because the transient dips contain signal and harmonic content, the error amplifier&#39;s adjustments to the level or DC value of the reference voltage based on the time average value of the reference voltage can introduce fundamental and harmonic errors into the ADC output. 
     SUMMARY 
     A feedback loop comprises a comparator, a digital-to-analog converter (DAC), and a switched capacitor accumulator. The comparator has a first input for a reference voltage input, a second input for a feedback input, and a third input for a control signal. The DAC is coupled to an output of the comparator, and the switched capacitor accumulator is coupled to an output of the DAC. In some implementations, a digital filter is coupled between the output of the comparator and an input of the DAC. In some examples, the feedback loop is coupled to a buffer that is configured to output the feedback input and a reference voltage for an analog-to-digital converter (ADC). 
     In some examples, multiple feedback loops share a common comparator. A first feedback loop receives a second control signal, and a second feedback loop receives a third control signal. A buffer is coupled to an output of the first feedback loop. A selector logic circuit receives the reference voltage input and an output of the buffer and outputs the feedback input. A control input of the selector logic circuit receives the second control signal. The second feedback loop outputs an offset correction signal for the comparator. 
     In some implementations in which multiple feedback loops share a common comparator, a first feedback loop receives a first clock signal and a second feedback loop receives a second clock signal. A first buffer coupled to an output of the first feedback loop outputs a first reference voltage output, and a second buffer coupled to an output of the second feedback loop outputs a second reference voltage output. A selector logic circuit receives the first and second reference voltage outputs and outputs the feedback input. A control input of the selector logic circuit receives the first clock signal. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       For a detailed description of various examples, reference will now be made to the accompanying drawings in which: 
         FIG.  1 A  illustrates a graph of SAMPLE and CONVERT control signals in an analog-to-digital converter (ADC) and a reference voltage provided to the ADC. 
         FIG.  1 B  illustrates an example reference voltage generator configured to provide the reference voltage shown in  FIG.  1 A . 
         FIG.  2 A  illustrates a reference voltage generator with a one-bit digital feedback loop. 
         FIG.  2 B  illustrates a graph of control signals in the reference voltage generator shown in  FIG.  2 A . 
         FIG.  3    illustrates a reference voltage generator with a one-bit digital feedback loop and biasing voltages. 
         FIG.  4    illustrates a reference voltage generator with a one-bit digital feedback loop, biasing voltages, and a digital filter. 
         FIG.  5 A  illustrates a reference voltage generator with a shared comparator for multiple reference voltage outputs. 
         FIG.  5 B  illustrates a graph of control signals and reference voltage outputs in the reference voltage generator shown in  FIG.  5 A . 
         FIG.  6 A  illustrates a reference voltage generator with autozeroing. 
         FIG.  6 B  illustrates a graph of control signals in the reference voltage generator shown in  FIG.  6 A . 
     
    
    
     The same reference numerals are used in the drawings to designate the same or similar (by function and/or structure) features. 
     DETAILED DESCRIPTION 
     The disclosed digital feedback loops include a comparator, a one-bit digital-to-analog converter (DAC), and a switched capacitor accumulator. The circuitry of some example embodiments occupy less area and consume less power than conventional analog error amplifiers and capacitors. In addition, because the feedback loop is digital rather than analog, the feedback loop adjusts the reference voltage output based on the settled value of the reference voltage rather than the time average value of the reference voltage. In some examples, the digital feedback loop also includes a digital filter to reduce noise from the comparator and biasing voltages to improve the direct current (DC) gain. 
       FIG.  1 A  illustrates a graph of SAMPLE and CONVERT control signals in an analog-to-digital converter (ADC) and a reference voltage provided to the ADC. The control signal SAMPLE  105  and the control signal CONVERT  110  are inverted relative to one another. In a successive approximation register (SAR) ADC, the reference buffer output REF_OUT  130  charges capacitors during the CONVERT phase, which can cause REF_OUT  130  to dip rather than maintain a constant value. 
     Some conventional reference buffers maintain the time average VREF_AVERAGE  115  of REF_OUT  130  to be approximately equal to the input reference voltage. The settled value VREF_SETTLED  120  of REF_OUT  130  is not equal to the input reference voltage and includes signal and harmonic content that causes the SAR ADC to have signal gain errors and harmonic errors. Additional SAR comparison cycles, referred to as dynamic error correction cycles, can be inserted during the CONVERT phase to reduce the impact of transient dips in REF_OUT  130 . Dynamic error correction cycles allow the reference voltage generator for the ADC to set the settled value VREF_SETTLED  120 , rather than the time average VREF_AVERAGE  115 , equal to the input reference voltage. 
       FIG.  1 B  illustrates a reference voltage generator  100  with a digital feedback loop  140  that corrects for errors in VREF_SETTLED  120  rather than VREF_AVERAGE  115 . For ease of illustration, reference voltage generator  100  is described herein with reference to  FIG.  1 A  and includes the low-bandwidth, high gain digital feedback loop  140  and a buffer stage  170 . The digital feedback loop  140  has a smaller area (e.g. an area on a semiconductor substrate) than an analog feedback loop with a high gain amplifier and a capacitor. In some example embodiments, feedback loop  140  is implemented with an ADC  150 , a DAC  155 , and a switched capacitor accumulator  160 . Buffer stage  170  is a high bandwidth buffer stage for fast settling and implemented with a flipped voltage follower in this example, but any appropriate buffer stage may be used. 
     The ADC  150  in digital feedback loop  140  can be any appropriate type of ADC or multi-bit digitizer, and receives the reference voltage input VREF_IN  144 , a clock input LATP  148 , and a reference feedback signal REF_FB  195 . The output of ADC  150  is provided to DAC  155 , which also receives SAMPLE  105 . The analog output of DAC  155  is provided to the switched capacitor accumulator  160 , which includes a switch  164  and an accumulating capacitor CD  168 . One terminal of the switch  164  is coupled to the input of switched capacitor accumulator  160 , and switch  164  is controlled by CONVERT  110 . Capacitor CD  168  is coupled between the other terminal of switch  164  and a common potential (e.g. ground)  194 . The voltage VSTG 1  is the output of the digital feedback loop  140  integrated over CD  168 , and provided to an input of buffer stage  170 . 
     Buffer stage  170  is a flipped voltage follower in this example, and includes transistors M 1 -M 2 , a current source  175 , two resistors  180  and  185  having a resistance R 1  and R 2 , respectively, and a capacitor  190  having a capacitance C. The transistors M 1 -M 2  are metal oxide semiconductor field-effect transistors (MOSFETs). M 1 -M 2  are p-type MOSFETs (PMOS) in this example. In other examples, one or more of M 1 -M 2  are n-type MOSFETs (NMOS) or bipolar junction transistors (BJTs). A BJT includes a base corresponding to the gate terminal, and a collector and an emitter corresponding to the drain and source terminals of a MOSFET. The base of a BJT and the gate terminal of a MOSFET are also called control inputs. The collector and emitter of a BJT and the drain and source terminals of a MOSFET are also called current terminals. 
     A source terminal of M 1  is coupled to a supply voltage rail VDD  198  (e.g., 5 volts), and a drain terminal of M 1  is coupled to a source terminal of M 2 . A drain terminal of M 2  and a gate terminal of M 1  is coupled to an input of the current source  175 , which is further coupled to ground  194 . A gate terminal of M 2  is coupled to the output of digital feedback loop  140 . Resistor  180  has a first terminal coupled to the drain terminal of M 1  and the source terminal of M 2  and a second terminal coupled to an output of the buffer stage  170  configured to provide the reference voltage REF_OUT  130 . 
     Resistor  185  has a first terminal coupled to the output of the buffer stage  170  and the second terminal of resistor  180  and a second terminal coupled to a first terminal of the capacitor  190 . A second terminal of capacitor  190  is coupled to ground  194 . The reference feedback signal REF_FB  195  is output from between the drain terminal of M 1  and the source terminal of M 2  to ADC  150 , and the reference voltage output REF_OUT  130  is output from buffer stage  170  to the ADC. 
     M 1  and M 2  act as analog amplifiers and cause the voltage at the first terminal of resistor  180  to be approximately equal to the voltage VSTG 1  plus a threshold voltage of M 2 . A voltage across current source  175  causes M 1  to act as a closed switch, and current flows through M 1  and across resistors  180  and  185  and capacitor  190  to generate the output reference voltage REF_OUT  130  from buffer stage  170 . In response to the voltage VSTG 1  being greater than a threshold voltage Vth of M 2 , M 2  acts as a closed switch. While M 2  acts as a closed switch, current through M 1  flows through M 2  and current source  175  as well as through the resistors  180  and  185  and capacitor  190 , changing the value of the output reference voltage REF_OUT  130  to be equal to the input reference voltage VREF_IN  144 . 
       FIG.  2 A  illustrates a reference voltage generator  200  with a one-bit digital feedback loop. For ease of illustration, reference voltage generator  200  is described herein with reference to  FIGS.  1 A and  1 B  and includes a comparator  225 , a one-bit DAC  255  and the switched capacitor accumulator  160 . The DAC  255  is a one-bit DAC in this example embodiment, but any appropriate number N of bits N-bit DAC can be used. A one-bit DAC reduces the power consumption and area used by the DAC  255  relative to larger values of N-bit DACs. In addition, a one-bit DAC allows the ADC  150  shown in  FIG.  1 B  to be implemented with a comparator  225 . The comparator  225  receives the reference voltage input VREF_IN  144 , a clock input LATP  148 , and a reference feedback signal REF_FB  195 . Comparator  225  outputs a first output BIT and an inverted output BITZ to DAC  255 . 
     The one-bit DAC  255  includes four switches  232 ,  234 ,  236 , and  238  and a sampling capacitor Cs  240 . Switch  232  is coupled to a supply voltage rail configured to receive a supply voltage VDD  198  (e.g. 5 volts) and controlled by SAMPLE  105 . Switch  234  is coupled to switch  232  and controlled by the first output BIT of comparator  225 . Switch  236  is coupled to switch  234  and controlled by the inverted output BITZ of comparator  225 . Switch  238  is coupled to switch  236  and to a supply voltage rail configured to receive a supply voltage VSS  210  (e.g. −5 volts). Switch  238  is controlled by SAMPLE  105 . Cs  240  is coupled between switches  234  and  236  and to a common potential (e.g. ground)  194 . The switched capacitor accumulator  160  is coupled to an output of the one-bit DAC  255  and to an input of buffer stage  170 . Buffer stage  170  outputs the reference feedback signal REF_FB  195  and the output reference voltage REF_OUT  130 . 
       FIG.  2 B  illustrates a graph of control signals SAMPLE  105 , CONVERT  110 , and LATP  148  in the reference voltage generator  200  shown in  FIG.  2 A . Comparator  225  outputs a difference between the reference voltage input VREF_IN  144  and the reference feedback signal REF_FB  195  at a time indicated by the clock input LATP  148 . The reference feedback signal REF_FB  195  from the buffer stage  170  represents the output reference voltage REF_OUT  130 . The clock input LATP  148  causes the comparator  225  to sample the output reference voltage REF_OUT  130  at a time during the SAMPLE phase at which it is settled at the settled value VREF_SETTLED  120 . As such, the comparator  225  outputs a difference BIT between the reference voltage input VREF_IN  144  and the settled value VREF_SETTLED  120  rather than the time average value VREF_AVERAGE  115 . 
     The comparator  225  outputs the difference BIT and an inverse BITZ of the difference BIT. For example, the comparator  225  outputs a difference BIT of logical one and an inverse BITZ of logical zero while the settled value VREF_SETTLED  120  is less than the reference voltage input VREF_IN  144 . Conversely, the comparator  225  outputs a difference BIT of logical zero and an inverse BITZ of logical one while the settled value VREF_SETTLED  120  is greater than the reference voltage input VREF_IN  144 . 
     Within the one-bit DAC  255 , switches  232  and  238  are closed during a SAMPLE phase of operation. LATP  148  is configured to cause the comparator  225  to output BIT and BITZ during the SAMPLE phase of operation, and switches  234  and  236  open and close based on the values of BIT and BITZ, respectively, coupling one of the supply voltages VDD  198  or VSS  210  to the sampling capacitor Cs  240 . The sampling capacitor Cs  240  is charged by VDD  198  or discharged by VSS  210  during the SAMPLE phase of operation. 
     During the CONVERT phase of operation, switches  232  and  238  are open, uncoupling the supply voltages VDD  198  and VSS  210  from the sampling capacitor Cs  240 . Switch  164  in the switched capacitor accumulator  160  is closed, coupling the sampling capacitor Cs  240  to the accumulating capacitor CD  168 . Charge from sampling capacitor Cs  240  is transferred to the accumulating capacitor CD  168 , adjusting the voltage VSTG 1  on the output of the digital feedback loop  140 . 
     The comparator  225  and one-bit DAC  255  act as a transconductor with an output current I  260  that can be represented as: 
                     I   ⁢   260     =       (         (   k   )     ⁢     (     VREF_IN   -   REF_FB     )       σ     )     ⁢     (   VSTEP   )     ⁢     (   Cs   )     ⁢     (   Fs   )               (   1   )               
where σ represents the standard deviation of the comparator noise, k represents a constant associated with the type of noise distribution of the comparator noise, VSTEP represents the voltage step generated by the one-bit DAC  255  and Fs represents the sampling frequency of the ADC. VSTEP is the difference between the supply voltage VDD  198  and VSTG 1  on the output of the digital feedback loop  140 .
 
     If the value of VSTEP is independent of VSTG 1 , the direct current (DC) gain of comparator  225  with DAC  255  is very high, resulting in low DC offset. However, since VSTEP depends on VSTG 1 , the DC gain is reduced (e.g. around 60 dB) thereby reducing DC reference voltage accuracy. The voltage VSTG 1  on the output of the digital feedback loop  140  is provided to the buffer stage  170 , which outputs the reference voltage REF_OUT  130  and the reference feedback signal REF_FB  195 . 
       FIG.  3    illustrates a reference voltage generator  300  with a digital feedback loop  140  and biasing voltages. Reference voltage generator  300  is similar to reference voltage generator  200  described herein with reference to  FIG.  2 A . Reference voltage generator  300  includes one-bit DAC  355 , which, in some example embodiments, is a low bandwidth, high gain stage that includes switches  332 ,  334 ,  336 ,  338 , and  360  and buffer  340  in addition to the switches  232 ,  234 ,  236 , and  238  and sampling capacitor Cs  240  included in one-bit DAC  255  in reference voltage generator  200 . 
     Switch  332  is coupled to the supply voltage rail configured to receive VDD  198  and controlled by CONVERT  110 . Switch  334  is coupled to switch  332  and controlled by the first output BIT of comparator  225 . Switch  336  is coupled to switch  334  and controlled by the inverted output BITZ of comparator  225 . Switch  338  is coupled to switch  336  and to the supply voltage rail configured to receive VSS  210 . Switch  338  is controlled by CONVERT  110 . A first terminal of capacitor Cs  240  is coupled between switches  234  and  236  and between switches  334  and  336  and a second terminal of capacitor Cs  240  is coupled to switched capacitor accumulator  160 . 
     One terminal of switch  360  is coupled between Cs  240  and switch  255  and the other terminal of switch  360  is coupled to the output of buffer  340 . Switch  360  is controlled by SAMPLE  105 . Buffer  340  is configured to receive a biasing voltage VBIAS  350  which is approximately equal to the value of VSTG 1  as set by the digital feedback loop  140 . During the SAMPLE phase of operation, switches  232 ,  234 ,  236 , and  238  operate as described herein with reference to  FIGS.  2 A and  2 B . In addition, switch  360  is closed, coupling the biasing voltage VBIAS  350  from buffer  340  to the second terminal of Cs  240 . 
     During the CONVERT phase of operation, switch  360  is open and disconnects the buffer  340  from the second terminal of Cs  240 . Switches  332  and  338  are closed. Switches  334  and  336  open and close based on the values of BIT and BITZ, respectively, coupling one of the supply voltages VDD  198  or VSS  210  to the sampling capacitor Cs  240 . The sampling capacitor Cs  240  is charged by VDD  198  via switch  332  or discharged by VSS  210  via switch  338  during the SAMPLE phase of operation. 
     The modifications in one-bit DAC  355  relative to one-bit DAC  255  shown in  FIG.  2 A  bias Cs  240  and make VSTEP independent of VSTG 1 . The reference voltage generator  300  improves the DC accuracy compared to reference voltage generator  200 . Stability of reference voltage generator  300  is improved by keeping the delay of buffer  170  less than the digital delay. That is, the bandwidth of buffer  170  is chosen such that the inverse of the bandwidth is much less than a clock period. 
       FIG.  4    illustrates a reference voltage generator  400  with a digital feedback loop  140 , biasing voltages, and a digital filter. Reference voltage generator  400  is similar to reference voltage generator  300  described herein with reference to  FIG.  3    but also includes a digital filter  410  coupled between comparator  225  and one-bit DAC  355  with voltage biasing. Digital filter  410  can bandlimit or low pass filter the one-bit comparator output signal to omit noise frequencies introduced by the comparator  225 . Digital filter  410  can be any appropriate digital filter taking into account the comparator noise and the noise requirements of the particular implementation. 
     For example, the digital filter  410  can be a one-bit accumulator that averages the comparator output signal over a number M of clock cycles, and the filter output toggles the one-bit DAC  355  once in M clock cycles. In another example, the digital filter  410  can be a finite impulse response filter with a number N of taps. Digital filter  410  takes up less area and uses less power than the capacitors used to bandlimit noise in conventional reference buffers with high gain amplifiers and capacitors. In addition, digital filter  410  offers fine control over the noise transfer function and as a result, better filtering. 
       FIG.  5 A  illustrates a reference voltage generator  500  with a shared comparator  225  for multiple reference voltage outputs REF_OUT 1   130 A and REF_OUT 2   130 B. The output of comparator  225  is coupled to a first signal chain  540 A and to a second signal chain  540 B. Each of signal chains  540 A and  540 B includes a D flip-flop  505  as well as a one-bit DAC and switched capacitor accumulator  510  as shown in  FIG.  2 A . In some implementations, the DAC and accumulators  510  also include voltage biasing as described herein with reference to  FIG.  3    and/or digital filters as described herein with reference to  FIG.  4   . Signal chains  540 A and  540 B include D flip-flops in this example but any appropriate circuit may be used, such as an SR latch and the like. 
     In signal chain  540 A, D flip-flop  505 A receives the difference BIT output from comparator  225  and is controlled by SAMPLE 1   105 A. D flip-flop  505 A outputs BIT 1  and BIT 1 Z to DAC and accumulator  510 A, which is controlled by SAMPLE 1   105 A and CONVERT 1   110 A. The output of DAC and accumulator  510 A is provided to buffer  170 A, which outputs REF_OUT 1   130 A. In signal chain  540 B, D flip-flop  505 B receives the difference BIT output from comparator  225  and is controlled by SAMPLE 2   105 B. D flip-flop  505 B outputs BIT 2  and BIT 2 Z to DAC and accumulator  510 B, which is controlled by SAMPLE 2   105 B and CONVERT 2   110 B. The output of DAC and accumulator  510 B is provided to buffer  170 B, which outputs REF_OUT 2   130 B. 
     REF_OUT 1   130 A and REF_OUT 2   130 B are provided to the ADC (not shown) and to a multiplexor  570 , which selectively outputs REF_OUT 1   130 A or REF_OUT 2   130 B based on SAMPLE 1   105 A. In this example, a multiplexor is used but any appropriate selector logic circuit may be used. The output of multiplexor  570  is the REF_FB  195  provided to comparator  225 . 
     In some ADCs, multiple voltage references may be used (e.g. a coarse reference voltage for initial decisions and a fine reference voltage for final decisions). If multiple references are used, they should be matched, and, therefore, comparator  225  may be shared between the two reference generators. For example, signal chain  540 B and buffer  170 B can be a coarse reference voltage buffer that is used for the initial CONVERT stage during which the largest capacitors are charged, and the majority of the signal dependent load current is supplied. 
     Signal chain  540 A and buffer  170 A can be a fine reference voltage buffer that is used for the final SAR decisions after a dynamic error correction cycle to supply a largely signal-independent current. Any errors introduced by shared comparator  225  are present in both REF_OUT 1   130 A and REF_OUT 2   130 B, such that DAC and accumulators  510 A and  510 B are matched. In this example, only two reference voltage output chains are shown but any appropriate number may be used. 
       FIG.  5 B  illustrates a graph of control signals in the reference voltage generator  500  shown in  FIG.  5 A . SAMPLE 1   105 A and SAMPLE 2   105 B are shown here as two unique control signals for ease of explanation. In other implementations, a single control signal SAMPLE  105  is used, and signal chains  540 A and  540 B operate on alternate SAMPLE phases. Similarly, CONVERT 1   110 A and CONVERT 2   110 B are shown here as two unique control signals for ease of illustration. In other implementations, a single control signal CONVERT  110  is used, and signal chains  540 A and  540 B operate on alternate CONVERT phases. LATP  148  is configured such that the logic high of LATP  148  occurs during the logic highs of SAMPLE 1   105 A and SAMPLE 2   105 B, and comparator  225  samples the settled values of REF_OUT 1   130 A and REF_OUT 2   130 B output from multiplexor  570 . 
     The multiplexor  570  and comparator  225  can be used to sample REF_OUT 1   130 A and REF_OUT 2   130 B on alternate SAMPLE phases and adjust the two reference output chains  540 A and  540 B independently. For example, in a first CONVERT phase of operation while CONVERT 1   110 A is logic high and SAMPLE 1   105 A is logic low, multiplexor  570  outputs REF_OUT 1   130 A as the feedback signal REF_FB  195 . Comparator  225  samples the REF_OUT 1   130 A based on the trigger signal LATP  148  and adjusts the value of VSTG 1  at the output of DAC and accumulator  510 A. REF_OUT 2   130 B is output as a coarse reference voltage. In a second CONVERT phase of operation while CONVERT 2   110 B is logic high, SAMPLE 2   105 B is logic low, and SAMPLE 1   105 A is logic low, multiplexor  570  outputs REF_OUT 2   130 B as the feedback signal REF_FB  195 . Comparator  225  samples the REF_OUT 2   130 B based on the trigger signal LATP  148  and adjusts the value of VSTG 2  at the output of DAC and accumulator  510 B. REF_OUT 1   130 A is output as a fine reference voltage. 
       FIG.  6 A  illustrates a reference voltage generator  600  with autozeroing capabilities. That is, the reference voltage generator  600  is able to compensate for comparator drift due to changes in temperature and the like by shorting the inputs of comparator  225  together and generating a voltage offset VCTRL_OFFSET  630  for comparator  225 . Outputs of shared comparator  225  are coupled to a first signal chain  640 A and a second signal chain  640 B. Each of signal chains  640 A and  640 B includes a D flip-flop  605  and a DAC and switched capacitor accumulator  610  as shown in  FIG.  2 A . In some implementations, the DAC and accumulators  610  also include voltage biasing as described herein with reference to  FIG.  3    and/or digital filters as described herein with reference to  FIG.  4   . 
     Signal chain  640 A outputs a control signal VCTRL_OFFSET  630  to comparator  225  to compensate for comparator drift. The output of signal chain  640 B is provided to a buffer  170 , which outputs the reference voltage REF_OUT  130  to the ADC (not shown) and to a multiplexor  650 . Multiplexor  650  selectively outputs REF_OUT  130  or VREF_IN  144  based on SAMPLE 1   105 A. In this example, a multiplexor is used but any appropriate selector logic circuit may be used. The output of multiplexor  650  is the REF_FB  195  provided to comparator  225 . Reference voltage generator  600  operates similarly to the operation of reference voltage generator  500  as described herein with reference to  FIG.  5 B , but instead of signal chain  540 A and buffer  170 A outputting REF_OUT  130 A, the output of signal chain  640 A is provided to comparator  225  as a control signal to compensate for comparator drift. 
     The comparator  225  can be autozeroed during a SAMPLE phase during which both comparator inputs receive VREF_IN  144  and the signal chain  640 A generates the offset correction voltage VCTRL_OFFSET  630 . The comparator  225  can be autozeroed in approximately a nanosecond, compared to the microseconds used to autozero analog error amplifiers. Autozeroing of the comparator can reduce phase noise. In addition, the bandwidth of comparator  225  can be dynamically modified or multiple comparator decisions can be made during the autozeroing phase to reduce thermal noise contributions. 
     In this description, the term “couple” may cover direct and indirect connections, communications, or signal paths that enable a functional relationship consistent with this description. For example, if device A generates a signal to control device B to perform an action: (a) in a first example, device A is coupled to device B by direct connection; or (b) in a second example, device A is coupled to device B through intervening component C if intervening component C does not alter the functional relationship between device A and device B, such that device B is controlled by device A via the control signal generated by device A. 
     The uses of the phrase “ground voltage potential” in this description include a chassis ground, an Earth ground, a floating ground, a virtual ground, a digital ground, a common ground, and/or any other form of ground connection applicable to, or suitable for, the teachings of this description. Unless otherwise stated, “about”, “approximately”, or “substantially” preceding a value means+/−10 percent of the stated value. 
     As used herein, the terms “terminal”, “node”, “interconnection” and “pin” are used interchangeably. Unless specifically stated to the contrary, these terms are generally used to mean an interconnection between or a terminus of a device element, a circuit element, an integrated circuit, a device or other electronics or semiconductor component. 
     Modifications are possible in the described embodiments, and other embodiments are possible, within the scope of the claims.