Patent Publication Number: US-2022231165-A1

Title: High-Voltage Semiconductor Devices

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application claims priority to and the benefit of Taiwan Application Series Number 110101789 filed on Jan. 18, 2021, which is incorporated by reference in their entirety. 
     BACKGROUND 
     The present disclosure relates generally to high-voltage semiconductor devices that can endure high-voltage stress during operation. 
     To achieve high-speed computation and compact product size, semiconductor devices become more and more complex and vulnerable. Furthermore, in order to be suitable for specific applications, some semiconductor devices must equip with delicate abilities. For example, some integrated circuit chips are used for high power operation that involves networks with power switches, inductors, and capacitors, so the input or output pins of the integrated circuit need to sustain tremendous voltage or current surges. The semiconductor devices connected to the input or output pins always give challenges to designers who are responsible for the structure of semiconductor devices to fulfill new requirements. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Non-limiting and non-exhaustive embodiments of the present invention are described with reference to the following drawings. In the drawings, like reference numerals refer to like parts throughout the various figures unless otherwise specified. These drawings are not necessarily drawn to scale. Likewise, the relative sizes of elements illustrated by the drawings may differ from the relative sizes depicted. 
       The invention can be more fully understood by the subsequent detailed description and examples with references made to the accompanying drawings, wherein: 
         FIG. 1  demonstrates a semiconductor device; 
         FIG. 2A  demonstrates a cross-sectional view of a semiconductor device according to embodiments of the invention; 
         FIG. 2B  demonstrates conductive channel PTH in the semiconductor device in  FIG. 2A ; 
         FIG. 2C  demonstrates a symbol representing the semiconductor device in  FIG. 2A ; 
         FIGS. 3 and 4  demonstrate cross-sectional views of semiconductor devices according to embodiments of the invention; 
         FIG. 5A  demonstrates a cross-sectional view of another semiconductor device according to embodiments of the invention; 
         FIG. 5B  demonstrates a symbol representing the semiconductor device in  FIG. 5A ; and 
         FIG. 6  demonstrates a cross-sectional view of another semiconductor device according to embodiments of the invention. 
     
    
    
     DETAILED DESCRIPTION 
       FIG. 1  demonstrates semiconductor device  100 , equivalent to a n-type junction field effect transistor (JFET) formed on p-type substrate  102 . A p-type material means that the material is conductive and the conductivity of the material is supported by holes with positive charges. A n-type material is also conductive, but its conductivity is supported by electrons with negative charges. Semiconductor device  100  has drain electrode DRAIN, source electrode SOURCE, gate electrode GATE, and substrate electrode SUB. Drain electrode DRAIN can sustain high-voltage input as high as hundreds or tens voltages. 
     Formed on p-type substrate  102  is p-type epitaxy layer  104 , on the surface of which are field isolation layers  112   a ,  112   b  and  112   c , each for separating different active regions. Gate structures, source doped layers, and drain doped layers of metal-oxide-semiconductor transistors for example can be formed inside an active region. Field isolation layer  112   a  separates p-type heavily doped layer  111   a  from n-type heavily doped layer  113   a . P-type heavily doped layer  111   a  physically contacts and electrically connects to p-type well layer  108   b , while n-type heavily doped layer  113   a  to n-type well layer  110 . Field isolation layer  112   b  is between p-type heavily doped layer  111   b  and n-type heavily doped layer  113   a , and field isolation layer  112   c  between gate oxide layer  114  and n-type heavily doped layer  113   b . P-type heavily doped layer  111   b  physically contacts and electrically connects to p-type well layer  108   a , and n-type heavily doped layer  113   b  to n-type deep well layer  106  thereunder. N-type deep well layer  106  can be formed by lightly doping n-type impurity into a selected area of p-type epitaxy layer  104 . The bottom of n-type deep well layer  106  shown  FIG. 1  does not touch P-type substrate  102 , but it could optionally do in other embodiments. 
     Stacking on gate oxide layer  114  and field isolation layer  112   c  is polysilicon layer  116 , which electrically connects via contact plugs  118  to metal strip  120   c  and  p -type heavily doped layer  111   b . Metal strip  120   c  and related contact plugs  118  serve as gate electrode GATE of semiconductor device  100  and as a metal interconnection capable of connecting to other electric circuitry on p-type substrate  102 . Analogously, metal strip  120   b  and related contact plugs  118  serve as source electrode SOURCE of semiconductor device  100 , and metal strip  120   d  and related contact plugs  118  as drain electrode DRAIN. Metal strip  120   a  and contact plug  118  thereunder are substrate electrode SUB electrically connected to substrate  102 . According to an embodiment of the invention, substrate electrode SUB connects to a ground voltage of a power supply. 
     Gate-to-source voltage V GS , the voltage difference between gate electrode GATE and source electrode SOURCE, can control the width of the depletion region over the PN junction between p-type well layer  108   a  and n-type deep well layer  106 , and accordingly controls the channel in n-type deep well layer  106  that electrically connects n-type heavily doped layer  113   b  to n-type well layer  110 . Polysilicon layer  116  on both gate oxide layer  114  and field isolation layer  112   c  can also act as a field plate to fine tune the electric field distribution inside n-type deep well layer  106 , to enhance the drain-to-source breakdown voltage of semiconductor device  100 . 
     An inherent issue occurs to semiconductor device  100  in  FIG. 1 : gate leakage to gate electrode GATE. During operation, once the voltage at source electrode SOURCE happens to suddenly drop way below the voltage at gate electrode GATE, the PN junction between p-type well layer  108   a  and n-type deep well layer  106  becomes forward biased, causing current surge flowing from gate electrode GATE to source electrode SOURCE. This current surge is called as gate leakage, and is not allowable in some applications. 
       FIG. 2A  demonstrates a cross-sectional view of semiconductor device  200   a  according to embodiments of the invention, having drain electrode DRAIN, source electrode SOURCE, gate electrode GATE, and substrate electrode SUB. Some structures or connections shown in  FIG. 2A  are similar or the same with those in  FIG. 1 , and are not detailed hereinafter because they are comprehensible in view of the teaching to  FIG. 1 . 
     N-type deep well layer  206  has surface FS, on which field isolation layers  212   a ,  212   b  and  212   c  are formed. Field isolation layer  212   a  separates active region OD 4  from active region OD 3 , field isolation layer  212   b  active region OD 3  from active region OD 2 , and field isolation layer  212   c  active region OD 2  from active region OD 1 . Each active region shown in  FIG. 2A  has only one heavily doped layer formed within, but this invention is not limited to however. An active region according to embodiment of the invention can have, among others, several heavily doped layers and/or several gate oxide layers formed within. 
     P-type heavily doped layer  211   b  is formed inside active region OD 4  and on a surface of p-type well layer  208   b , to provide electric connection from p-type well layer  208   b, p -type epitaxy layer  204  and p-type substrate  202  to metal strip  220   a . Metal strip  220   a  and contact plug  218  thereunder are substrate electrode SUB, electrically connecting to p-type substrate  202  and to a ground voltage of a power supply according to embodiments of the invention. 
     Formed within active region OD 3  is n-type heavily doped layer  213   a , which contacts a contact plug  218  to form an ohmic contact providing electric connection to n-type well layer  210  formed on surface FS of n-type deep well layer  206 . Formed within active region OD 2  is p-type heavily doped layer  211   a , which contacts a contact plug  218  to form an ohmic contact providing electric connection between metal strip  220   b  and  p -type well layer  208   a .  FIG. 2A  shows that a portion of p-type well layer  208   a  is under field isolation layer  212   c . From a top view that can be witnessed by  FIG. 2A , a portion of p-type well layer  208   a  overlaps with field isolation layer  212   c , and another portion is located between field isolation layer  212   c  and n-type heavily doped layer  213   a . N-type heavily doped layer  213   a  electrically shorts to p-type heavily doped layer  211   a  via contact plugs  218  and metal strip  220   b . Metal strip  220   b  and associated contact plugs  218  are deemed as a source metal interconnection, acting as source electrode SOURCE of semiconductor device  200   a . Source metal interconnection equivalently contacts a surface of p-type well layer  208   a . Active region OD 3  can be deemed as a source active region. According to other embodiments of the invention, field isolation layer  212   b  in  FIG. 2A  is omitted, and active regions OD 3  and OD 2  merge to be a common source active region, within which p-type heavily doped layer  211   a  and n-type heavily doped layer  213   a  are formed. 
     Formed within active region OD 1  is n-type heavily doped layer  213   b , contacting with a contact plug  218  to form an ohmic contact that electrically shorts metal strip  220   d  to n-type deep well layer  206 . Metal strip  220   d  and the contact plug  218  thereunder in combination construct a drain metal interconnection that contacts n-type heavily doped layer  213   b  in active region OD 1 , and acts as drain electrode DRAIN of semiconductor device  200   a . Analogously, active region OD 1  can be deemed as a drain active region. 
     Polysilicon layer  216 , acting as a control gate, is formed on field isolation layer  212   c , and electrically connects to metal strip  220   c  via a contact plug  218 . Metal strip  220   c  and the contact plug  218  thereunder in combination are deemed as a gate metal interconnection, acting as gate electrode GATE of semiconductor device  200   a . According to embodiments of the invention, gate oxide layer  114  in  FIG. 1  does not happen under polysilicon layer  216  in  FIG. 2A , so the gate-to-source breakdown voltage of semiconductor device  200   a  could be higher because field isolation layer  212   c  can sustain a higher breakdown voltage than gate oxide layer  114  in  FIG. 1  does. 
     At bottom BS of n-type deep well layer  206  is buried p-type bottom layer  222 . As shown in  FIG. 2A , p-type bottom layer  222  occupies a bottom portion of n-type deep well layer  206 , and a top portion of p-type substrate  202 . As demonstrated by  FIG. 2A , p-type bottom layer  222  overlaps at least partially with field isolation layer  212   c , and keeps distance CR away from active region OD 1 . In other words, p-type bottom layer  222  does not overlap with active region OD 1 . P-type bottom layer  222  in  FIG. 2A  also partially overlaps with p-type well layer  208   a . For example, a predetermined top area of p-type substrate  202  is doped with p-type impurity before the formation of p-type epitaxy layer  204 , and a thermal process after the formation of p-type epitaxy layer  204  can drive and diffuse the p-type impurity to form p-type bottom layer  222 . 
       FIG. 2B  demonstrates conductive channel PTH in semiconductor device  200   a , that n-type deep well layer  206  provides to electrically connect drain and source electrodes DRAIN and SOURCE. Conductive channel PTH goes from drain electrode DRAIN, through a gap between p-type well layer  208   a  and  p -type bottom layer  222 , through n-type well layer  210 , and to source electrode SOURCE.  FIG. 2B  also demonstrates edges BTP and BBT of depletion regions, that substantially determine the width of conductive channel PTH. When edges BTP and BBT touch each other, it is the condition of channel pinch-off or current cut-off, implying that current flowing through conductive channel PTH becomes about constant even if the drain-to-source voltage of semiconductor device  200   a  is further increased. The voltage at gate electrode GATE can control the location of edge BTP. For example, when the voltage at gate electrode GATE becomes more negative in respect to that at source electrode SOURCE, the depletion region under the bottom of field isolation layer  212   c  is wider, making edge BTP closer to edge BBT. P-type well layer  208   a  could reduce the surface electric field of n-type deep well layer  206 , enhancing drain-to-source breakdown voltage of semiconductor device  200   a . The location, the size, and the impurity concentration of p-type bottom layer  222  could determine the formation of edge BBT in  FIG. 2B , to adjust the pinch-off voltage, the drain-to-source voltage when edges BTP and BBT merge. In other words, p-type bottom layer  222  could also improve drain-to-source breakdown voltage of semiconductor device  200   a.    
       FIG. 2C  demonstrates a symbol representing semiconductor device  200   a , which is a depletion-mode metal-oxide-semiconductor (MOS) transistor. Gate electrode GATE, electrically connecting to polysilicon layer  216  on field isolation layer  212   c  in  FIG. 2A , controls conductive channel PTH within n-type deep well layer  206 . When gate-to-source voltage of semiconductor device  200   a  is 0V, edges BTP and BBT do not merge and conductive channel PTH conducts current, so semiconductor device  200   a  is a depletion-mode device using thick field isolation layer  212   c  as its gate oxide. 
     Semiconductor device  200   a  in  FIG. 2A  does not have gate leakage, the inherent issue occurring to semiconductor device  100  in  FIG. 1 . P-type well layer  208   a  electrically shorts to n-type well layer  210  via source metal interconnection, which includes metal strip  220   b  and related contact plugs  218 . Therefore, p-type well layer  208   a  and n-type well layer  210  have a substantially common voltage, which is the present source voltage of semiconductor device  200   a . The gate voltage applied to gate electrode GATE can reach polysilicon layer  216  on field isolation layer  212   c , but cannot reach p-type well layer  208   a . Therefore, in semiconductor device  200   a , even if the gate voltage at gate electrode GATE briefly exceeds the source voltage at source electrode SOURCE, there will be no gate leakage from gate electrode GATE to source electrode SOURCE in condition that field isolation layer  212   c  does not break down. 
       FIG. 3  demonstrates a cross-sectional view of semiconductor device  200   b  according to embodiments of the invention.  FIG. 3  has structures or connections similar or the same with those shown by semiconductor devices  100  and  200   a  in  FIGS. 1 and 2A , and these structures or connections are not detailed herein because they are comprehensible in view of the teaching to  FIGS. 1 and 2A . Unlike the single p-type bottom layer  222  of semiconductor device  200   a  in  FIG. 2A , semiconductor device  200   b  in  FIG. 3  has several p-type bottom layers  222   a ,  222   b  and  222   c , each at least partially overlapping with field isolation layer  212   c . None of p-type bottom layers  222   a ,  222   b  and  222   c  overlaps with active region OD 1  however. Fine tuning the number, the size, the location of the p-type bottom layers could enhance the drain-to-source breakdown voltage of semiconductor device  200   b.    
       FIG. 4  demonstrates a cross-sectional view of semiconductor device  200   c  according to embodiments of the invention.  FIG. 4  has structures or connections similar or the same with those shown by semiconductor devices  100 ,  200   a  and  200   b  in  FIGS. 1, 2A and 3 , and these structures or connections are not detailed herein because they are comprehensible in view of the teaching to  FIGS. 1, 2A and 3 . Unlike p-type well layer  208   a  of semiconductor device  200   a  in  FIG. 2A  that electrically shorts to n-type well layer  210 , p-type well layer  208   a  in  FIG. 4  is electrically floating, meaning that p-type well layer  208   a  does not connect to any metal interconnection or, if it connects to a metal interconnection the metal interconnection does not provide any fixed voltage to p-type well layer  208   a . Even though p-type well layer  208   a  is electrically floating, the voltage of p-type well layer  208   a  could be substantially equal to that of n-type deep well layer  206  in the long run, due to the very little PN junction leakage through the PN junction between p-type well layer  208   a  and n-type deep well layer  206 . P-type well layer  208   a  in  FIG. 4  could also reduce the surface electric field of n-type deep well layer  206 , enhancing drain-to-source breakdown voltage of semiconductor device  200   c.    
       FIG. 5A  demonstrates a cross-sectional view of semiconductor device  200   d  according to embodiments of the invention.  FIG. 5A  has structures or connections similar or the same with those shown by semiconductor devices  100 ,  200   a ,  200   b  and  200   c , and these structures or connections are not detailed herein because they are comprehensible in view of the teaching to  FIGS. 1, 2A, 3 and 4 . The drain electrode DRAIN of semiconductor device  200   a  in  FIG. 2A  electrically shorts to n-type deep well layer  206  via n-type heavily doped layer  213   b . Semiconductor device  200   d  in  FIG. 5A , unlike semiconductor device  200   a  in  FIG. 2A , has the contact plug  218  of drain electrode DRAIN directly contact with a surface of n-type deep well layer  206  inside active region OD 1 , to form Schottky contact DS. In the cross-sectional view of  FIG. 5A , Schottky contact DS is sandwiched by two p-type lightly-doped layers  226   a  and  226   b , both electrically connecting to drain electrode DRAIN. In a top view of semiconductor device  200   d , two p-type lightly-doped layers  226   a  and  226   b  might belong to a common p-type lightly-doped region that surrounds Schottky contact DS. These p-type lightly-doped layers  226   a  and  226   b  could form ohmic contact with contact plugs  218  to electrically connect drain electrode DRAIN.  FIG. 5B  demonstrates a symbol representing semiconductor device  200   d , which consists of a depletion-mode metal-oxide-semiconductor (MOS) transistor and Schottky diode DDS connected in series, where Schottky contact DS embodies Schottky diode DDS. Schottky diode DDS prevents reverse current flowing from source electrode SOURCE to drain electrode DRAIN, and provides a less forward voltage that consumes less power when positive biased. P-type lightly-doped layers  226   a  and  226   b  can enhance the breakdown voltage of Schottky diode DDS. 
     Features in the aforementioned embodiments could be combined in one embodiment of the invention.  FIG. 6  demonstrates a cross-sectional view of semiconductor device  200   e  according to embodiments of the invention. Semiconductor device  200   e  has several p-type bottom layers  222   a ,  222   b  and  222   c , electrically-floating p-type well layer  208   a , and Schottky contact DS, and could be comprehensible in view of the teaching regarding to semiconductor devices  100 ,  200   a ,  200   b ,  200   c  and  200   d.    
     While the invention has been described by way of example and in terms of preferred embodiment, it is to be understood that the invention is not limited thereto. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.