Patent Publication Number: US-11043426-B2

Title: Dummy MOL removal for performance enhancement

Description:
REFERENCE TO RELATED APPLICATIONS 
     This Application is a Divisional of U.S. application Ser. No. 16/154,035, filed on Oct. 8, 2018, which is a Continuation of U.S. application Ser. No. 15/148,274, filed on May 6, 2016 (now U.S. Pat. No. 10,096,522, issued on Oct. 9, 2018). The contents of the above-referenced Patent Applications are hereby incorporated by reference in their entirety. 
    
    
     BACKGROUND 
     Over the last four decades the semiconductor fabrication industry has been driven by a continual demand for greater performance (e.g., increased processing speed, memory capacity, etc.), a shrinking form factor, extended battery life, and lower cost. In response to this demand, the industry has continually reduced a size of semiconductor device components, such that modern day integrated chips may comprise millions or billions of semiconductor devices arranged on a single semiconductor die. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. 
         FIG. 1  illustrates three-dimensional view of some embodiments of a substrate having a middle-of-the-line (MOL) layer arranged at an irregular pitch to reduce parasitic capacitance. 
         FIG. 2  illustrates a cross-sectional view of some embodiments of a substrate having a MOL layer that is arranged at an irregular pitch to reduce parasitic capacitance. 
         FIGS. 3A-3B  illustrates some embodiments of a NAND gate having a MOL layer that is arranged at an irregular pitch. 
         FIGS. 4A-4B  illustrates some embodiments of a NOR gate having a MOL layer that is arranged at an irregular pitch. 
         FIG. 5  illustrates a three-dimensional view of some embodiments of a substrate having a MOL layer arranged at an irregular pitch between gate structures within FinFET devices. 
         FIGS. 6A-6B  illustrates some embodiments of a NAND gate having a MOL layer that is arranged at an irregular pitch between gate structures within FinFET devices. 
         FIGS. 7-11  illustrate top-views and cross-sectional views corresponding to some embodiments of a method of forming an integrated chip having a MOL layer arranged at an irregular pitch. 
         FIG. 12  illustrates a flow diagram of some embodiments of a method of forming an integrated chip having a MOL layer arranged at an irregular pitch. 
     
    
    
     DETAILED DESCRIPTION 
     The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. 
     Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature&#39;s relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. Moreover, it will be appreciated that the fill and colors used in the illustrated layers are similar throughout the disclosure (e.g., the fill and color used in the layers shown in  FIG. 2  are similar to the fill and colors used in the layers shown in  FIGS. 3A-3B ). 
     In emerging technology nodes the small size of transistor components may cause restrictive topology choices for back-end-of-the-line (BEOL) metal layer routing. To alleviate the metal line routing problems, middle-of-the-line (MOL) local interconnection layers may be used. MOL local interconnect layers are conductive metal layers that are vertically positioned between the front-end-of-line (FEOL) and the BEOL. MOL local interconnect layers can provide very high-density local routing that avoids consumption of scarce routing resources on the lower BEOL metal layers. 
     Typically, MOL local interconnect layers comprise MOL structures that are formed over a well region at a constant (i.e., regular) pitch to improve a lithographic process window. Conductive contacts are subsequently formed onto some of the MOL structures that are needed in a design to form an electrical connection with overlying metal wire layers. This results in dummy MOL structures, which are the MOL structures that have no electrical connection to overlying metal wire layers. It has been appreciated that in emerging technology nodes (e.g., 14 nm, 10 nm, 7 nm, etc.) the small size between MOL structures and gate structures is becoming small enough to produce a parasitic capacitance that significantly degrades transistor device performance. 
     The present disclosure relates to a method of forming an integrated chip that removes unnecessary MOL dummy structures to reduce parasitic capacitance and to form MOL structures at an irregular pitch, and an associated apparatus. In some embodiments, the integrated chip comprises a well region comprising a plurality of source/drain regions. A plurality of gate structures are arranged over the well region at a regular pitch. A plurality of middle-of-the-line (MOL) structures are laterally interleaved between some of the plurality of gate structures and are arranged over the well region at an irregular pitch comprising a first pitch that is larger than the regular pitch. By having the MOL structures arranged at an irregular pitch that comprises a first pitch that is larger than the regular pitch, one or more of the plurality of gate structures are spaced apart from a closest gate or MOL structure by a relatively large space that provides for a relatively low parasitic capacitance. 
       FIG. 1  illustrates three-dimensional view of some embodiments of an integrated chip  100  having a middle-of-the-line (MOL) layer arranged at an irregular pitch to reduce parasitic capacitance. 
     The integrated chip  100  comprises a well region  103  comprising a plurality of source/drain regions  104  (to simplify the illustration, a single source/drain region  104  is labeled with a reference numeral in  FIG. 1 .) arranged within the semiconductor substrate  102  along a first direction  116 . In some embodiments, the well region  103  may have a doping type opposite the source/drain regions  104  (e.g., a PMOS active area formed within a p-type substrate may comprise p-type source/drain regions arranged within an n-type well region  103 ). The plurality of source/drain regions  104  comprise highly doped regions (e.g., having a doping concentration greater than that of the surrounding semiconductor substrate  102 ) that are laterally separated by channel regions  105 . A plurality of gate structures  106  are arranged over the channel regions  105  and extend over the well region  103  along a second direction  118  that is perpendicular to the first direction  116 . The plurality of gate structures  106  are arranged in a repeating pattern that extends along the first direction  116 . Within the repeating pattern, the plurality of gate structures  106  are arranged at a regular pitch  110  (i.e., a spacing is substantially the same between left edges of the gate structures or between right edges of the gate structure). 
     A plurality of middle-of-the-line (MOL) structures  108  are arranged over the well region  103  at locations between adjacent ones of the plurality of gate structures  106 . The plurality of MOL structures  108  are in electrical contact with the source/drain regions  104  and are configured to provide for lateral routing (e.g., in the first direction  116  and/or the second direction  118 ) between the source/drain regions  104  and an overlying conductive contact (not shown). Two or more of the plurality of MOL structures  108  are arranged over the well region  103  at a pitch  112  larger than the regular pitch  110 . 
     Since the pitch  112  is larger than the regular pitch  110 , at least two adjacent ones of the plurality of MOL structures  108  are laterally separated by a second distance greater than the regular pitch. However, since the plurality of gate structures  106  are arranged at the regular pitch, this means that some of the plurality of gate structures  106  are not separated by an intervening MOL structure. By having some of the plurality of gate structures  106  not separated by a MOL structure  108 , the parasitic capacitance on the gate structures  106  is reduced. Reducing the parasitic capacitance (e.g., an unwanted capacitance between conductive components because of their proximity to one another) on the gate structures  106  improves performance of transistors associated with the gate structures  106 . 
     It will be appreciated that the term “regular pitch”, as used herein, means a substantially regular pitch within tolerances due to misalignment errors. For example, the regular pitch may have values between different pairs of gate structures that vary due to misalignment errors by approximately 5% (e.g., a first pitch Pa of a first pair of gate structures may be between 0.95 and 1.05 times a second pitch Pb of a second pair of gate structures). 
       FIG. 2  illustrates a cross-sectional view of some embodiments of an integrated chip  200  having MOL structures arranged at an irregular pitch. With respect to the embodiment of  FIG. 1 , like elements in the cross-sectional view  200  are designated with the same reference numbers for ease of understanding. 
     The integrated chip  200  comprises a well region  103  arranged within a semiconductor substrate  102 . The well region  103  comprises a plurality of source/drain regions  104  that are laterally separated by channel regions  105 . A plurality of gate structures  106  are arranged over the channel regions  105  at a regular pitch  110 . In some embodiments, the plurality of gate structures  106  may respectively comprise a gate electrode  204  separated from the semiconductor substrate  102  by way of a gate dielectric  202 . In various embodiments, the gate electrode  204  may comprise polysilicon or a metal (e.g., aluminum). In various embodiments, the gate dielectric  202  may comprise an oxide (e.g., silicon dioxide) or a high-k material. 
     A plurality of MOL structures  108  are arranged over source/drain regions  104  at a location laterally adjacent to the gate structures  106 . The plurality of MOL structures  108  may contact the underlying semiconductor substrate  102 . In various embodiments, the plurality of MOL structures  108  may comprise a conductive metal (e.g., tungsten, copper, cobalt, etc.). In some embodiments, the plurality of gate structures  106  and the plurality of MOL structures  108  may have an approximately same height h. 
     The plurality of MOL structures  108  are arranged at an irregular pitch having more than one pitch. For example, a first MOL structure  108   a  and a second MOL structure  108   b  may be arranged at a first pitch  206 , while the second MOL structure  108   b  and a third MOL structure  108   c  may be arranged at a second pitch  208  that is different than the first pitch  206 . The irregular pitch causes different ones of the plurality of MOL structures  108  to be separated from an adjacent one of the plurality of MOL structures  108  by different spaces, and also causes a gate structure  106  to be separated from adjacent MOL or gate structures by different spaces. For example, a gate structure  106  may have a first side separated from a neighboring MOL structure  108  by a first distance s 1  and an opposite second side that is separated from an adjacent gate structure  106  by a second distance s 2  that is larger than the first distance s 1 . Since capacitance (C) is inversely proportional to a distance (d) between conductive elements (e.g., C ∝ 1/d), the larger second distance s 2  reduces the parasitic capacitance on the gate structures  106  and improves performance of transistors associated with the gate structures  106 . 
     The irregular pitch also causes one or more of the plurality of gate structures  106  to laterally neighbor a MOL structure  108  and a gate structure  106  on opposing sides. In other words, the one or more MOL structures  108  are laterally interleaved between a subset of the plurality of gate structures  106 , so that the plurality of gate structures  106  and the one or more MOL structures  108  are arranged over the well region  103  in a pattern in which two or more of the plurality of gate structures  106  neighbor each other (i.e., are not separated by an interleaved MOL structure  108 ). 
     A first inter-level dielectric (ILD) layer  210   a  is arranged over the semiconductor substrate  102  at locations laterally between the plurality of gate structures  106  and the plurality of MOL structures  108 . A second ILD layer  210   b  is arranged over the first ILD layer  210   a . A plurality of conductive contacts  214  are arranged within the second ILD layer  210   b  at locations over the plurality of MOL structures  108 . The plurality of conductive contacts  214  are configured to electrically couple the plurality of MOL structures  108  to an overlying metal wire layer  216  arranged within a third ILD layer  210   c  overlying the second ILD layer  210   b . In some embodiments, the first ILD layer  210   a  may be vertically separated from the second ILD layer  210   b  by a first etch stop layer  212   a , and the second ILD layer  210   b  may be vertically separated from the third ILD layer  212   c  by a second etch stop layer  212   b.    
     In some embodiments, the conductive contacts  214  may comprise tungsten and the overlying metal wire layer  216  may comprise copper. In some embodiments, all of the plurality of MOL structures  108  over the well region  103  are electrically coupled to a conductive contact  214 . In various embodiments, the ILD layers  210   a - 210   c  may comprise a low-k dielectric layer, an ultra low-k dielectric layer, an extreme low-k dielectric layer, and/or a silicon dioxide layer. In various embodiments, the etch stop layers  212   a - 212   b  may comprise a nitride, such as silicon nitride, for example. 
       FIG. 3A  illustrates a top-view  300  of some embodiments of a NAND gate having a MOL layer arranged at an irregular pitch.  FIG. 3B  illustrates a corresponding schematic diagram  314  of the NAND gate of  FIG. 3A . 
     As shown in top-view  300 , the NAND gate comprises a first well region  302  and a second well region  312 . The first well region  302  comprises a plurality of source/drain regions having p-type dopants. The second well region  312  comprises a plurality of source/drain regions having n-type dopants. 
     A first gate structure  304   a  and a second gate structure  304   b  extend over the first well region  302  to form a first PMOS transistor T 1  and a second PMOS transistor T 2  arranged in parallel between a node ZN and a source voltage V DD . A first plurality of MOL structures  306   a - 306   c  are arranged over the first well region  302  at a first pitch p 1  that causes the gate structures  304   a - 304   b  to be separated from the first plurality of MOL structures  306   a - 306   c  on opposing sides by an equal space. 
     The first plurality of MOL structures comprise a first MOL structure  306   a , a second MOL structure  306   b , and a third MOL structure  306   c . The first MOL structure  306   a  and the second MOL structure  306   b  extend from over the first well region  302  to under a first metal wire structure  308   a  (illustrated as transparent to show the underlying layers). The first MOL structure  306   a  and the second MOL structure  306   b  are connected to the first metal wire structure  308   a  by way of conductive contacts  310  (to simplify the illustration, a single conductive contact  310  is labeled with a reference numeral in  FIGS. 3A-3B ). The third MOL structure  306   c  is connected to a second metal wire structure  308   b  by a conductive contact  310 . 
     The first gate structure  304   a  and the second gate structure  304   b  also extend over the second well region  312  to form a first NMOS transistor T 3  and a second NMOS transistor T 4  arranged in series between node ZN and a ground voltage V SS . A second plurality of MOL structures  306   d - 306   e  are arranged over the second well region  312  at a second pitch p 2  that is greater than the first pitch p 1 , and which causes the gate structures  304   a - 304   b  to be separated from the second plurality of MOL structures  306   d - 306   e  on opposing sides by unequal spaces. 
     The second plurality of MOL structures  306   d - 306   e  comprise a fourth MOL structure  306   d  and a fifth MOL structure  306   e . The fourth MOL structure  306   d  extends from over the second well region  312  to under a third overlying metal wire structure  308   c  and is connected to the third overlying metal wire structure  308   c  by way of a conductive contact  310 . The fifth MOL structure  306   e  is connected to a fourth overlying metal wire structure  308   d  by a conductive contact  310 . 
       FIG. 4A  illustrates a top-view  400  of some embodiments of a NOR gate having a MOL layer arranged at an irregular pitch.  FIG. 4B  illustrates a corresponding schematic diagram  414  of the NOR gate of  FIG. 4A . 
     As shown in top-view  400 , the NOR gate comprises a first well region  402  and a second well region  412 . The first well region  402  comprises a plurality of source/drain regions having n-type dopants. The second well region  412  comprises a plurality of source/drain regions having p-type dopants. 
     A first gate structure  404   a  and a second gate structure  404   b  extend over the first well region  402  to form a first PMOS transistor T 1  and a second PMOS transistor T 2  arranged in series between a node ZN and a source voltage V DD . A first plurality of MOL structures  406   a - 406   b  are arranged over the first well region  402  at a first pitch p 1 ′ that causes the gate structures  404   a - 404   b  to be separated from the first plurality of MOL structures  406   a - 406   b  on opposing sides by unequal spaces. 
     The first plurality of MOL structures comprise a first MOL structure  406   a  and a second MOL structure  406   b . The first MOL structure  406   a  extends from over the first well region  402  to under a first metal wire structure  408   a  (illustrated as transparent to show the underlying layers). The first MOL structure  406   a  is connected to the first metal wire structure  408   a  by a conductive contact  410  (to simplify the illustration, a single conductive contact  410  is labeled with a reference numeral in  FIGS. 3A-3B ). The second MOL structure  406   b  is connected to a second metal wire structure  408   b  by way of a conductive contact  410 . 
     The first gate structure  404   a  and the second gate structure  404   b  also extend over the second well region  412  to form a first NMOS transistor T 3  and a second NMOS transistor T 4  arranged in parallel between node ZN and a ground voltage V SS . A second plurality of MOL structures  406   c - 406   e  are arranged over the second well region  412  at a second pitch p 2 ′ that is less than the first pitch p 1 ′, and which causes the gate structures  404   a - 404   b  to be separated from the second plurality of MOL structures  406   c - 406   e  on opposing sides by an equal space. 
     The second plurality of MOL structures  406   c - 406   e  comprise a third MOL structure  406   c , a fourth MOL structure  406   d , and a fifth MOL structure  406   e . The third MOL structure  406   c  and the fourth MOL structure  406   d  extend from over the second well region  412  to under a third overlying metal wire  408   c  and are connected to the third MOL structure  406   c  by way of conductive contacts  410 . The fifth MOL structure  406   e  is connected to a fourth overlying metal wire structure  408   d  by a conductive contact  410 . 
     It has been appreciated that the use of a MOL layer having an irregular pitch may be especially useful in multi-gate device (e.g., double gate FinFETs, tri-gate FinFETs, omega FET, Gate all around (GAA), vertical GAA, etc.).  FIG. 5  illustrates three-dimensional view of some embodiments of an integrated chip  500  having a MOL layer arranged at an irregular pitch between gate structures of multi-gate devices (e.g., a FinFET devices). Elements in the three-dimensional view of  FIG. 5  that are described in previous embodiments have been designated with the same reference numbers for ease of understanding. 
     The integrated chip  500  comprises a plurality of fins of semiconductor material  502  protruding outward from a semiconductor substrate  102  (e.g., from a well region  103  doped opposite the semiconductor substrate  102 ) and extending along a first direction  116 . The plurality of fins of semiconductor material  502  extend between epitaxial source/drain regions  504  (to simplify the illustration, a single source/drain region  504  is labeled with a reference numeral in  FIG. 5 ). The epitaxial source/drain regions  504  are shared between adjacent fins of semiconductor material  502  (e.g., so that a same epitaxial source/drain region  504  extends between a first fin and a second fin). The epitaxial source/drain regions  504  are arranged on the fins of semiconductor material  502  and comprise highly doped regions of semiconductor material (e.g., having a doping concentration greater than that of the semiconductor substrate  102 ), so that a channel region may be formed within the plurality of fins of semiconductor material  502 . In some embodiments, the plurality of fins of semiconductor material  502  may be laterally separated by an isolation layer  501  (e.g., comprising STI regions). 
     A plurality of gate structures  506  are arranged over the plurality of fins of semiconductor material  502  along a second direction  118  that is perpendicular to the first direction  116  (to simplify the illustration, a single gate structure  506  is labeled with a reference numeral in  FIG. 5 ). The plurality of gate structures  506  are arranged in a repeating pattern that extends along the first direction  116 . Within the repeating pattern, the plurality of gate structures  506  are arranged at a regular pitch  110 . 
     A plurality of middle-of-the-line (MOL) structures  508  are arranged over the plurality of fins of semiconductor material  502  at locations between adjacent ones of the plurality of gate structures  506  (to simplify the illustration, a single MOL structure  508  is labeled with a reference numeral in  FIG. 5 ). In some embodiments, the plurality of MOL structures  508  may be arranged onto an insulating layer (not shown) surrounding the plurality of fins of semiconductor material  502 . The plurality of MOL structures  508  are in electrical contact with the plurality of source/drain regions  504  and are configured to provide for lateral routing to an overlying conductive contact  510  (to simplify the illustration, a single conductive contact  510  is labeled with a reference numeral in  FIG. 5 ). Two or more of the plurality of MOL structures  508  are arranged at a pitch  112  larger than the regular pitch  110 . 
       FIG. 6A  illustrates a top-view  600  of some embodiments of a NAND gate having a MOL layer arranged at an irregular pitch between gate structures within FinFET devices.  FIG. 6B  illustrates a corresponding schematic diagram  614  of the NAND gate of  FIG. 6A . 
     As shown in top-view  600 , the NAND gate comprises a first well region  602  and a second well region  612 . The first well region  602  comprises first and second fins of semiconductor material,  603   a  and  603   b , arranged between source and drain regions (not shown) having p-type dopants. The second well region  612  comprises first and second fins of semiconductor material,  613   a  and  613   b , arranged between source and drain regions (not shown) having n-type dopants. 
     A first gate structure  604   a  and a second gate structure  604   b  extend over the first well region  602  to form a first PMOS transistor T 1  and a second PMOS transistor T 2  arranged in parallel between a node ZN and a source voltage V DD . A first plurality of MOL structures  606   a - 606   c  are arranged over the first well region  602  at a first pitch p 1  that causes the gate structures  604   a - 604   b  to be separated from MOL structures  606   a - 606   c  on opposing sides by an equal space. The first gate structure  604   a  and the second gate structure  604   b  also extend over the second well region  612  to form a first NMOS transistor T 3  and a second NMOS transistor T 4  arranged in series between node ZN and a ground voltage V SS . A second plurality of MOL structures  606   d - 606   e  are arranged over the second well region  612  at a second pitch p 2  that is greater than the first pitch p 1 , and which causes the gate structures  604   a - 604   b  to be separated from MOL structures  606   d - 606   e  on opposing sides by unequal spaces. 
       FIGS. 7-11  illustrates top-views and corresponding cross-sectional views corresponding to some embodiments of a method of forming an integrated chip that reduces parasitic capacitance by removing unnecessary MOL dummy structures. It will be appreciated that elements in  FIGS. 7-11  that have been described in previous embodiments have been designated with the same reference numbers for ease of understanding. Furthermore, to simplify the illustrations, elements shown multiple times within a figure are labeled with a reference numeral a single time (e.g., although multiple gate structures are shown in  FIGS. 7-11 , a single gate structure  106  is labeled). 
     As shown in top-view  700  and cross-sectional view  706  of  FIG. 7  a plurality of gate structures  106  are formed over a semiconductor substrate  102  at a regular pitch  110 . The plurality of gate structures  106  comprise a gate electrode  204  separated from the semiconductor substrate  102  by a gate dielectric layer  202 . An well region  103  comprising a plurality of source/drain regions  104  is also formed within the semiconductor substrate  102 . In some embodiments, the well region  103  (within which the source/drain regions  104  are disposed) is formed prior to the formation of the plurality of gate structures  106 . The well region may be formed by selectively implanting a dopant species into the semiconductor substrate  103  (e.g., an n-well may be formed within a p-type substrate, to form a PMOS active area, by implanting a p-type dopant into the substrate prior to the formation of the gate structures). 
     In various embodiments, the semiconductor substrate  102  may comprise any type of semiconductor body (e.g., silicon/CMOS bulk, SiGe, SOI, etc.) such as a semiconductor wafer or one or more die on a wafer, as well as any other type of semiconductor and/or epitaxial layers formed thereon and/or otherwise associated therewith. In some embodiments, the plurality of gate structures  106  may be formed by forming a gate dielectric layer over the semiconductor substrate  102 , and subsequently forming a gate electrode layer over the gate dielectric layer. The gate dielectric layer and the gate electrode layer are subsequently patterned according to photolithography process to form a plurality of gate structures  106 . 
     In some embodiments, the plurality of source/drain regions  104  may be formed by an implantation process that implants a dopant species  708  into the semiconductor substrate  102 . In various embodiments, the dopant species  708  may comprise a p-type dopant (e.g., boron, gallium, etc.) or an n-type dopant (e.g., phosphorus, arsenic, etc.). In some embodiments, the dopant species  708  may be driven into the semiconductor substrate  102  by performing a subsequent high-temperature anneal. In some alternative embodiments, the source/drain regions  104  may be formed by an epitaxial growth process at a location within or overlying the semiconductor substrate  102 . 
     As shown in top-view  800  and cross-sectional view  804  of  FIG. 8 , a plurality of MOL structures,  802   a  and  802   b , are formed over the semiconductor substrate  102  at locations laterally interleaved between the plurality of gate structures  106 . The plurality of MOL structures comprise MOL active structures  802   a  (i.e., MOL structures that are subsequently connected to an overlying conductive contact within an electrical path) and MOL dummy structures  802   b  (i.e., electrically inactive MOL structures that are not subsequently connected to an overlying conductive contact). The plurality of MOL structures,  802   a  and  802   b , are arranged at a first pitch  206 . In some embodiments, the regular pitch  110  and the first pitch  206  are substantially equal. 
     As shown in top-view  900  and cross-sectional view  904  of  FIG. 9 , a cut mask  902  is used in a patterning process that selectively removes parts of the MOL structures,  802   a  and/or  802   b . In some embodiments, the patterning process patterns a masking layer  906  overlying the semiconductor substrate  102  to form openings  908  within the masking layer  906  that arranged over the MOL dummy structures  802   b . In some embodiments, the masking layer  906  may comprise a photoresist layer. In such embodiments, the masking layer  906  may be patterned by selectively exposing the masking layer  906  to radiation  910  according to the cut mask  902 , and subsequently developing the masking layer  906  to form the openings  908 . 
     In some embodiments, the location of cut regions  901  within the cut mask  902  may be limited by design rules. For example, in some embodiments, the cut mask  902  may not be able to remove MOL dummy structures  802   b  that are separated by an insufficient spacing (e.g., if the spacing between edges of the cuts is smaller than that allowed by design rules). In such embodiments, the cut mask  902  may be configured to remove a part of a MOL dummy structure  802   b  that is allowed by design rules. For example, as shown in boxes  912  of top-view  900 , MOL dummy structures  802   b  are aligned so that the cut mask  902  would have cuts that are separated by a space that is smaller than that allowed by design rules. Therefore, a part of the MOL dummy structures  802   b  is removed, and a reminder of the MOL dummy structures  802   b  is left. By removing a part of the MOL dummy structures  802   b , the parasitic capacitance of the design is reduced without violating design rules that may lead to high cost mask construction. 
     As shown in top-view  1000  and cross-sectional view  1002  of  FIG. 10 , an etching process is used to selectively remove the MOL dummy structures  802   b  according to the openings  908  in the masking layer  906 . The etching process exposes the MOL dummy structures  802   b  underlying the openings  908  to an etchant  1004 , which selectively cuts or trims the MOL dummy structures  802   b  over some parts of the well region  103 . In some embodiments, the etchant  1004  may be selective to a material of the MOL structures,  802   a  and  802   b , so that the gate structure  106  is not cut. In various embodiments, the etchant  1004  may comprise a dry etchant (e.g., a plasma etch with tetrafluoromethane (CF 4 ), sulfur hexafluoride (SF 6 ), nitrogen trifluoride (NF 3 ), etc.) or a wet etchant (e.g., hydroflouric (HF) acid). 
     The etching process causes the plurality of MOL structures,  802   a  and  802   b , overlying the well region  103  to have an irregular pitch. The irregular pitch causes some of the plurality of MOL structures,  802   a  and  802   b , to be arranged at the first pitch  206 , while others of the plurality of MOL structures,  802   a  and  802   b , are arranged at a second pitch  208  that is larger than the first pitch  206 . 
     While  FIGS. 9-10  illustrate the use of a ‘cut last’ technique that cuts the MOL dummy structures  802   b , it will be appreciated that other cut techniques may be used. For example, in some alternative embodiments, a ‘cut first’ technique may be used to form a material on cut regions so that the MOL dummy structures  802   b  will be excluded from being formed in the cut regions. 
     As shown in cross-sectional view  1100  and cross-sectional view  1102  of  FIG. 11 , an ILD layer  1104  is formed over the semiconductor substrate  102 . The ILD layer  1104  laterally separates the gate structures  106  and the MOL structures  108 . Conductive contacts  214  are subsequently formed in the ILD layer  1104 . The conductive contacts  214  electrically connect the MOL structures  108  to an overlying metal wire layer  216  arranged in an overlying ILD layer  1106 . 
     In some embodiments, the ILD layer  1104  may be deposited over the semiconductor substrate  102  by way of vapor deposition techniques (e.g., physical vapor deposition, chemical vapor deposition, etc.). The ILD layer  1104  is selectively etched to form a contact hole extending from an upper surface of the ILD layer  1104  and the MOL structure  108 . The contact hole is then filled with a metal (e.g., tungsten), and a first planarization process is performed to form a conductive contact  214 . In some embodiments, the overlying metal wire layer  216  may be formed by depositing the overlying ILD layer  1106  over the ILD layer  1104  using a vapor deposition process. The overlying ILD layer  1106  is selectively etched to form a trench, which is subsequently filled with a metal (e.g., copper). A second planarization process may be subsequently performed to form the overlying metal wire layer  216 . 
       FIG. 12  illustrates a flow diagram of some embodiments of a method  1200  of forming an integrated chip that reduces parasitic capacitance by removing unnecessary MOL dummy structures to form MOL structures at an irregular pitch. 
     While the disclosed method  1200  is illustrated and described herein as a series of acts or events, it will be appreciated that the illustrated ordering of such acts or events are not to be interpreted in a limiting sense. For example, some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein. In addition, not all illustrated acts may be required to implement one or more aspects or embodiments of the description herein. Further, one or more of the acts depicted herein may be carried out in one or more separate acts and/or phases. 
     At  1202 , a plurality of fins of semiconductor material may be formed to protrude from a semiconductor substrate in some embodiments. 
     At  1204 , a plurality of gate structures are formed over the semiconductor substrate at a regular pitch. In some embodiments, the plurality of gate structures may be formed over the plurality of fins of semiconductor material. In other embodiments, the plurality of gate structures may be formed on a planar surface of the semiconductor substrate.  FIG. 7  illustrates some embodiments corresponding to act  1204 . 
     At  1206 , a well region is formed. The well region comprises a plurality of source/drain regions. The well region may extend along a direction that intersects the plurality of gate structures.  FIG. 7  illustrates some embodiments corresponding to act  1206 . 
     At  1208 , an original MOL layer is formed having a plurality of MOL structures overlying the well region and interleaved between the plurality of gate structures at a first pitch.  FIG. 8  illustrates some embodiments corresponding to act  1208 . 
     At  1210 , part of the original MOL layer overlying the well region is removed to form a modified MOL layer having an irregular pitch. The irregular pitch may comprise the first pitch, and a second pitch that is larger than the first pitch.  FIGS. 9-10  illustrate some embodiments corresponding to act  1210 . 
     At  1212 , conductive contacts are formed on one or more MOL structures overlying the well region.  FIG. 11  illustrates some embodiments corresponding to act  1212 . 
     Therefore, the present disclosure relates to a method of forming integrated chip that reduces parasitic capacitance by removing unnecessary MOL dummy structures to form MOL structures at an irregular pitch, and an associated apparatus. 
     In some embodiments, the present disclosure relates to an integrated chip. The integrated chip comprises a well region comprising a plurality of source/drain regions, and a plurality of gate structures arranged over the well region at a substantially regular pitch. The integrated chip comprises a plurality of middle-of-the-line (MOL) structures laterally interleaved between some of the plurality of gate structures and arranged over the well region at an irregular pitch comprising a first pitch that is larger than the substantially regular pitch. 
     In other embodiments, the present disclosure relates to an integrated chip. The integrated chip comprises a well region having a plurality of source/drain regions. The integrated chip further comprises a plurality of gate structures arranged over the well region and laterally separated from one another by a first distance, and a plurality of middle-of-the-line (MOL) structures arranged over the well region at positions laterally interleaved between two of the plurality of gate structures. At least two adjacent ones of the plurality of MOL structures are laterally separated by a second distance greater than the first distance. 
     In yet other embodiments, the present disclosure relates to a method of forming an integrated chip. The method comprises forming a plurality of gate structures over a semiconductor substrate, and forming a well region comprising a plurality of source/drain regions, wherein the well region underlies the plurality of gate structures. The method further comprises forming an original middle-of-the-line (MOL) layer having a plurality of MOL structures laterally interleaved between the plurality of gate structures and overlying the well region. The method further comprises removing a part of the original MOL layer overlying the well region to form a modified MOL layer. 
     The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.