Patent Publication Number: US-7223680-B1

Title: Method of forming a dual damascene metal trace with reduced RF impedance resulting from the skin effect

Description:
This is a divisional application of U.S. Pat. No. 6,703,710 issued on Mar. 9, 2004. 

   BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention relates to metal traces and, more particularly, to a dual damascene metal trace with reduced RF impedance resulting from the skin effect. 
   2. Description of the Related Art 
   Metal traces are common integrated circuit elements that are used in a multi-level interconnect structure to connect together various elements of a circuit. In addition, a metal trace can be used to form an integrated circuit inductor by forming the trace to have a number of coils or loops. Inductors are common circuit elements in radio frequency (RF) applications, such as digital cellular telephones. 
     FIGS. 1A–1D  show views that illustrates a prior art integrated circuit inductor  100 .  FIG. 1A  shows a plan view.  FIG. 1B  shows a cross- sectional view taken along lines  1 B— 1 B of  FIG. 1A .  FIG. 1C  shows a cross-sectional view taken along lines  1 C— 1 C of  FIG. 1A .  FIG. 1D  shows a cross-sectional view taken along lines  1 D— 1 D of  FIG. 1A . 
   As shown in  FIGS. 1A–1D , inductor  100  is formed on top of a four metal layer interconnect structure that includes a fourth layer of insulation material I 4 , and a metal trace  110  that is formed on insulation layer I 4  from a fourth metal layer M 4 . In addition, the metal interconnect structure includes a fifth layer of insulation material I 5  that is formed on metal trace  110 , and a via  112  that is formed through insulation layer I 5  to make an electrical connection with metal trace  110 . 
   As further shown in  FIGS. 1A–1D , inductor  100  includes a metal trace  114  that is formed on top of the fifth layer of insulation material I 5  from a fifth metal layer M 5 . Metal trace  114 , which has a width W and a depth D, has a first end  120  that is formed over via  112  to make an electrical connection with via  112 , and a second end  122 . Metal trace  114 , which makes one and a half loops in the same plane, is typically formed on top of the metal interconnect structure to avoid inducing currents in the substrate. 
   One important measure of a metal trace is the RF impedance of the trace, which affects the quality factor or Q of an inductor formed from the metal trace. High Q inductors are desirable in a number of RF circuits, such as resonant circuits. The Q of an inductor is a measure of the ratio of magnetic energy stored in the inductor versus the total energy fed into the inductor, and is given by equation (EQ.) 1 as:
 
 Q=ωL/Z,   EQ. 1
 
where ω is related to the frequency f of the signal applied to the inductor (ω=2(pi)(f)), L represents the inductance of the inductor, and Z represents the RF impedance of the inductor. (Impedance is the vector sum of resistance and reactance, and introduces a phase shift.) Thus, as indicated by EQ. 1, the smaller the impedance, the higher the Q of the inductor.
 
   One problem with metal traces is that when gigahertz-frequency signals are placed on the trace, the skin effect causes current to flow primarily at the surface. This effectively increases the RF impedance of the trace which, in turn, lowers the Q of an inductor formed from the trace. 
   One common approach to reducing the impedance of an integrated circuit inductor is to increase the size of the metal trace. However, in integrated circuit applications, there are practical limitations to the size of the metal trace. As a result, there is a need for a metal trace with reduced RF impedance which, in turn, allows a high Q integrated circuit inductor to be realized from the trace. 
   SUMMARY OF THE INVENTION 
   The present invention provides a dual damascene metal trace that has reduced RF impedance at gigahertz frequencies. When the metal trace is formed to have a number of loops, the looping metal trace forms an integrated circuit inductor, while the reduced RF impedance increases the Q of the inductor. 
   A semiconductor structure in accordance with the present invention includes a layer of insulation material that is formed over a semiconductor substrate. In addition, the semiconductor structure includes a metal trace that is formed in the layer of insulation material. The metal trace has a base region and a plurality of spaced-apart fingers that extend away from the base region. The metal trace can be formed to have a number of loops, and the loops can be formed to lie substantially in the same plane. 
   The present invention also includes a method of forming a semiconductor structure that includes the step of forming a layer of insulation material over a semiconductor substrate. The method further includes the step of etching the layer of insulation material to form a plurality of first trenches in the layer of insulation material. The trenches have a first bottom surface that is vertically spaced a first distance apart from the top surface. 
   The method additionally includes the step of etching the layer of insulation material to form a second trench in the layer of insulation material. The second trench has the plurality of first trenches, and the first trenches have a second bottom surface that is vertically spaced a second distance apart from the top surface. The second distance is greater than the first distance. 
   The method also includes the steps of forming a layer of conductive material on the layer of insulation material to fill up the second trench and the first trenches, and planarizing the layer of conductive material to form a trace. 
   A better understanding of the features and advantages of the present invention will be obtained by reference to the following detailed description and accompanying drawings that set forth an illustrative embodiment in which the principles of the invention are utilized. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIGS. 1A–1D  are views illustrating a prior art integrated circuit inductor  100 .  FIG. 1A  is a plan view.  FIG. 1B  is a cross-sectional view taken along lines  1 B— 1 B of  FIG. 1A .  FIG. 1C  is a cross-sectional view taken along lines  1 C— 1 C of  FIG. 1A .  FIG. 1D  is a cross-sectional view taken along lines  1 D— 1 D of  FIG. 1A . 
       FIGS. 2A–2B  are views illustrating an integrated circuit structure  200  in accordance with the present invention.  FIG. 2A  is a plan view, while  FIG. 2B  is a cross-sectional view taken along line  2 B— 2 B of  FIG. 2A . 
       FIGS. 3A–3D  are views illustrating an integrated circuit inductor  300  in accordance with the present invention.  FIG. 3A  is a plan view, while  FIG. 3B  is a cross-sectional view taken along lines  3 B— 3 B of  FIG. 3A .  FIG. 3C  is a cross-sectional view taken along lines  3 C— 3 C of  FIG. 3A .  FIG. 3D  is a cross-sectional view taken along lines  3 D— 3 D of  FIG. 3A . 
       FIGS. 4A–4D  are cross-sectional drawings illustrating an example of a method of forming a metal trace in accordance with the present invention. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
     FIGS. 2A–2B  show views that illustrate an integrated circuit structure  200  in accordance with the present invention.  FIG. 2A  shows a plan view, while  FIG. 2B  shows a cross-sectional view taken along line  2 B— 2 B of  FIG. 2A . As described in greater detail below, structure  200  utilizes a metal line that has been formed to have an increased surface area. The increased surface area, in turn, reduces the impedance of the line at gigahertz frequency levels. 
   As shown in  FIGS. 2A–2B , structure  200  includes a first circuit  210  that operates on a gigahertz frequency signal, and a second circuit  212  that operates on a gigahertz frequency signal. In addition, structure  200  includes a metal trace  214  that is electrically connected to circuits  210  and  212 . Metal trace  214 , which is formed in a layer of insulation material  216 , passes gigahertz frequency signals between circuits  210  and  212 . 
   As further shown in  FIG. 2B , metal trace  214  has a width W (of approximately four microns) and a depth D (of approximately four microns). Metal trace  214  also has a base region  220  with a top side  220 A and a bottom side  220 B, and a number of spaced-apart fingers  222  that extend away from bottom side  220 A. Fingers  222 , in turn, substantially increase the surface area of metal trace  214  when compared to a conventional metal trace that has the same width W and depth D, such as metal trace  114 . 
   In operation, when a signal in the gigahertz frequency range is placed on metal trace  214  by circuit  210  or circuit  212 , current flows primarily at the surface of metal trace  214  due to the skin effect. Thus, in accordance with the present invention, since current flows primarily at the surface and fingers  222  substantially increase the surface area of metal trace  214 , fingers  222  allow more current to flow. As a result, fingers  222  effectively reduce the RF impedance of metal trace  214 . 
   Thus, the present invention reduces the RF impedance of a metal trace that interconnects two gigahertz frequency devices. (The metal trace connecting together two gigahertz frequency devices can be formed from any one of the layers of metal used to form the metal interconnect structure, such as the first layer of metal, or a combination of metal layers and vias.) 
     FIGS. 3A–3D  are views that illustrate an integrated circuit inductor  300  in accordance with the present invention.  FIG. 3A  shows a plan view.  FIG. 3B  shows a cross-sectional view taken along lines  3 B— 3 B of  FIG. 3A .  FIG. 3C  shows a cross-sectional view taken along lines  3 C— 3 C of  FIG. 3A .  FIG. 3D  shows a cross-sectional view taken along lines  3 D— 3 D of  FIG. 3A . 
   As described in greater detail below, inductor  300  is formed from a metal trace that has been formed to have an increased surface area. The increased surface area, in turn, reduces the RF impedance of the metal trace when gigahertz-frequency signals are placed on the trace. As a result, the metal trace of the present invention can be used to form integrated circuit inductors with an increased Q. 
   In the example shown in  FIGS. 3A–3D , like inductor  100 , inductor  300  is formed on top of a four metal layer interconnect structure. The interconnect structure includes a fourth layer of insulation material I 4 , and a metal trace  310  that is formed in insulation layer I 4  from a fourth metal layer M 4 . In addition, the metal interconnect structure includes a fifth layer of insulation material I 5  that is formed on insulation layer I 4  and metal trace  310 , and a via  312  that is formed through insulation layer I 5  to make an electrical connection with metal trace  310 . 
   As further shown in  FIGS. 3A–3D , inductor  300  includes a metal trace  314  that is formed in the fifth layer of insulation material  15  from a fifth metal layer M 5 . (Metal trace  314  can be formed from any metal layer, including the first metal layer. The fifth metal layer of the present example is but one possibility. By forming inductor  300  on top of a metal interconnect structure, however, induced substrate currents are minimized). 
   In addition, metal trace  314  has a first end  320  that is formed over via  312  to make an electrical connection with via  312 , and a second end  322 . (In this example, second end  322  can be connected to a via connected to a metal-4 trace, or a via connected to a pad or another overlying metal trace.) 
   Metal trace  314  also has a width W (of approximately four microns) and a depth D (of approximately four microns). Further, metal trace  314  makes one and a half loops in the same plane. (Trace  314  is not limited to one and a half loops, but can be formed with a different number of loops.) 
   As further shown in  FIG. 3B , metal trace  314  has a base region  324  with a top side  324 A and a bottom side  324 B, and a number of spaced-apart fingers  326  that extend away from bottom side  324 B. Fingers  326 , in turn, substantially increase the surface area of metal trace  314  when compared to a conventional metal trace that has the same width W and depth D, such as metal trace  114 . 
   In operation, when a signal in the gigahertz frequency range is input to inductor  300 , current flows primarily at the surface of metal trace  314  due to the skin effect. Thus, in accordance with the present invention, since current flows primarily at the surface and fingers  326  substantially increase the surface area of metal trace  314 , fingers  326  allow more current to flow. 
   As a result, fingers  326  effectively reduce the RF impedance of metal trace  314 , thereby increasing the Q of inductor  300 . In addition, as illustrated by  FIG. 3C , metal trace  310  can be formed as metal trace  214 , thereby providing a low RF impedance pathway from inductor  300  (a first gigahertz frequency device) to another gigahertz frequency device. 
     FIGS. 4A–4D  show cross-sectional drawings that illustrate an example of a method of forming a metal trace in accordance with the present invention. As shown in  FIG. 4A , the method utilizes a layer of insulation material  410  that has been formed over a semiconductor integrated circuit device. Insulation layer  410 , in turn, has a number of contacts or vias that have been formed through insulation layer  410 . 
   In addition, insulation layer  410  can be formed on the surface of the substrate of the device, or on top of a metal trace that is formed from any of the layers of metal that are used to form the metal interconnect structure of the device. For example, when a semiconductor integrated circuit is fabricated with a five layer metal process, insulation layer  410  can be formed on the metal-4 layer. 
   As further shown in  FIG. 4A , the method of the present invention begins by forming a first layer of masking material  412  on insulation layer  410 . First layer of masking material  412  is then patterned to expose lines on the surface of insulation layer  410 . The exposed regions of insulation layer  410  are then anisotropically etched to form trenches  414 . Following this, masking material  412  is removed. 
   Next, as shown in  FIG. 4B , a second layer of masking material  416  is formed on insulation layer  410 . Second layer of masking material  416  is then patterned to expose trenches  414 . The exposed regions of insulation layer  410  are then anisotropically etched to form a trench  420 . As further shown, trench  420  includes trenches  414  that extend away from the bottom side of trench  420 . Trenches  414 , in turn, define a number of to-be-formed fingers. 
   Trenches  414  and  420  can be formed to have a number of loops that lie substantially in the same plane to form an inductor. In addition, trenches  414  and  420  can expose a contact or a via formed in insulation material  410 . (Trenches  414  and  420  can expose more than one contact or via, or no vias if an overlying metal layer and vias are used to make an electrical connection to the trace that is to be formed in trenches  414  and  420 ). Once trenches  414  and  420  have been formed, masking material  416  is removed. Masking materials  412  and  416  can be implemented with a soft mask material (photoresist) or a hard mask material (nitride). 
   As shown in  FIG. 4C , once masking material  416  has been removed, a layer of conductive material  422  is deposited on insulation layer  410  to fill up trenches  414  and  420 , and form the damascene structure. Conductive layer  422  can include, for example, a layer of diffusion barrier material and an overlying layer of metal. 
   The layer of diffusion barrier material can be formed from, for example, a metal nitride such as titanium nitride (TiN) or tungsten nitride (WN). The layer of metal can be formed from, for example, aluminum or copper. When copper is utilized, a seed layer of copper can be deposited on the layer of diffusion barrier material. After this, a layer of copper is electroplated over the seed layer. 
   Next, as shown in  FIG. 4D , after conductive layer  422  has been formed, conductive layer  422  is planarized using conventional processes, such as chemical-mechanical polishing, until conductive layer  422  has been removed from the top surface of insulation layer  410 . The planarizing step forms a dual damascene trace  424  that has a bottom surface  426 , and a number of fingers  430  that extend away from bottom surface  426 . After the planarizing step has been completed, the method continues with conventional steps. 
   It should be understood that the above descriptions are examples of the present invention, and that various alternatives of the invention described herein may be employed in practicing the invention. Thus, it is intended that the following claims define the scope of the invention and that structures and methods within the scope of these claims and their equivalents be covered thereby.