Patent Publication Number: US-8126089-B2

Title: Method and apparatus for providing frame synchronization in a digital communication system that supports multiple modulation formats

Description:
FIELD OF THE INVENTION 
     The invention relates to the field of digital communication systems and, in particular, to frame synchronization in optical digital communication systems. 
     BACKGROUND OF THE INVENTION 
     In digital communication systems (e.g., high-speed optical communication systems) information sequences and control information are commonly transmitted in the form of repetitive structures referred to as “frames”. Such systems require synchronization between a transmitter and a receiver in order to recognize the presence and alignment of the frames at the receiver before any further decoding can take place. The transmitter inserts a frame alignment sequence (FAS), typically at the beginning of a frame, to determine the position of the frame in the received digitized stream. In the receiver, a frame synchronization module, referred to hereafter as “framer”, detects the FAS and monitors frame alignment once initial frame acquisition has been accomplished. 
     Typically, optical communication systems use an ON/OFF Keying (OOK) modulation format, and framers for such systems are known in the art. In the field of high-speed optical communication, Differential Phase Shift Keying (DPSK) and Duobinary Signaling (DBS) modulation formats can offer significant advantages over the OOK format. To provide frame synchronization and determine the intended polarity of the transmitted stream, these modulation formats require specialized frame synchronization algorithms. However, in a communication network, multiple modulation formats may be used by component digital communication systems, and it is highly desirable to have the algorithmic behavior of the framers to be independent from and cross-compatible with multiple modulation formats. 
     Therefore, there is a need in the art for an improved method and apparatus for frame synchronization in digital communication systems that supports multiple modulation formats. 
     SUMMARY OF THE INVENTION 
     The present invention comprises a method and apparatus for frame synchronization in a digital communication system that may use one of several modulation formats. 
     In a first aspect of the invention, there is provided a method for frame synchronization. In one embodiment, the method performs a search for a frame alignment sequence (FAS) and the inverted FAS to provide frame synchronization and determines the polarity of the transmitted digital streams when Differential Phase Shift Keying (DPSK) or Duobinary Signaling (DBS) modulation formats are used. 
     In a second aspect of the invention, there is provided an apparatus for frame synchronization using the inventive method. In one embodiment, the apparatus comprises a multiplexer to collectively switch a digital stream, a controller of the multiplexer, a memory element that stores the FAS, and at least one frame synchronization module (i.e., framer). Embodiments of the apparatus provide frame synchronization and determine the polarity of the transmitted digital streams when DPSK or DBS modulation formats are used, and they are also compatible with digital streams that have been transmitted using an ON/OFF Keying (OOK) modulation format. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The teachings of the present invention can be readily understood by considering the following detailed description in conjunction with the accompanying drawings, in which: 
         FIG. 1  depicts a schematic diagram of a receiver of an exemplary optical digital communication system in accordance with one embodiment of the present invention; 
         FIG. 2  depicts a flow diagram of a method for frame synchronization in the receiver of  FIG. 1  in accordance with one embodiment of the present invention; 
         FIG. 3  depicts a schematic diagram of a frame synchronization apparatus of the receiver of  FIG. 1  in accordance with one embodiment of the present invention; 
         FIG. 4  depicts a schematic diagram of a frame synchronization apparatus of the receiver of  FIG. 1  in accordance with another embodiment of the present invention; and 
         FIG. 5  depicts a schematic diagram of a frame synchronization apparatus of the receiver of  FIG. 1  in accordance with yet another embodiment of the present invention. 
     
    
    
     To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. 
     It is to be noted, however, that the appended drawings illustrate only exemplary embodiments of this invention and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments. 
     DETAILED DESCRIPTION OF THE INVENTION 
     The present invention advantageously provides a method and apparatus for frame synchronization in a digital communication system using multiple modulation formats, such as a Differential Phase Shift Keying (DPSK) modulation format, a Duobinary Signaling (DBS) modulation format, and an ON/OFF Keying (OOK) modulation format. 
     In  FIG. 1  and in  FIGS. 3-5  below, similar components are identified using the same reference numerals, except that the alphabetical suffixes are added, when appropriate, to differentiate between specific devices. Such components may also be referred to by their reference numeral without any appended suffix. 
       FIG. 1  depicts a schematic diagram of a receiver  100  of an exemplary optical communication system (not shown) having a bit rate of about 10 Gb/s or 40 Gb/s in accordance with one embodiment of the present invention. In one embodiment, the receiver  100  includes an opto-electronic converter  104 , a multi-format frame synchronization apparatus (MFSA)  110 , and a data processing unit  112 . In an alternate embodiment (not shown), the MFSA  110  may be a portion of the data processing unit  112 . An optical signal input of the opto-electronic converter  104  is illustratively coupled to an output fiber  102  of the optical communication system. The opto-electronic converter  104  transforms a modulated optical signal in a digital stream (in particular, a binary stream) that, via an electrical interface  106 , is provided to the MFSA  110 . 
     The MFSA  110  searches for and detects a frame alignment sequence (FAS) and/or the inverted FAS in the received digital stream. In case of the DPSK and DBS modulation formats, the MFSA  110  additionally determines the otherwise ambiguous polarity of the received digital stream. From the MFSA  110 , the frame-aligned digital stream is forwarded, via a bus  108 , to the data processing unit  112 . An output of the data processing unit  112  is coupled, using a communication link  114  (e.g., wired or wireless link, gateway to the Internet, and the like), to the recipients (not shown) of the received information. 
     Herein, the polarity of the digital stream is defined as “0” when the MFSA  110  detects the FAS in the received stream. Accordingly, ”when the MFSA  110  detects the inverted FAS in the received digital stream, the polarity of the received stream is defined as “1”. The digital streams that are transmitted using DPSK or DBS modulation may have either polarity at the receiver, whereas the polarity of digital streams that are transmitted using OOK modulation is always “0”. In one embodiment, the MFSA  110  inverts the bits in the received digital streams having polarity “1” before outputting such streams to the data processing unit  112 . 
       FIG. 2  depicts a flow diagram of one embodiment of the inventive method for frame synchronization in the receiver  100  of  FIG. 1  as a process  200 . The process  200  includes the steps performed to acquire frame synchronization of incoming digital streams that have been modulated using one of several modulation formats. In one embodiment, such processing steps are sequentially performed in the depicted order. In alternate embodiments, at least two of these processing steps may be performed contemporaneously or in a different order. The process  200  starts at step  202  and proceeds to step  204 . At step  204 , the FAS (e.g., a 48-bit binary sequence) and the inverted FAS (i.e., bit-inverted FAS) are supplied to one or more framers of the MFSA  110 . In one embodiment, such framers are configured for providing frame synchronization in the received streams in a system that uses the OOK modulation format, i.e., the framers have an industry-standard configuration. When the MFSA  110  includes one framer, the FAS and the inverted FAS may intermittently be provided to the framer. At step  206 , in the out-of-frame state, the framers search the incoming digital stream for the FAS and the inverted FAS. 
     At step  208 , the process  200  queries if the FAS has been detected. If the query of step  208  is affirmatively answered, the process  200  proceeds to step  210 . At step  210 , the received digital stream is frame-synchronized and polarity “0” is assigned to the received digital stream. At step  211 , the process proceeds to an in-frame monitoring state, where the input sequence is tested periodically for the presence of the FAS at the expected positions. At step  212 , the process  200  queries if the FAS is found periodically at the expected positions in the received stream. If the query of step  212  is answered negatively once or a predetermined number of times, the system is considered to be out-of-frame and the process  200  proceeds to step  206 . If the query of step  212  is affirmatively answered, the process returns to step  211 . 
     If the query of step  208  is negatively answered, the process  200  ends to step  212 . At step  214 , the process  200  queries if the inverted FAS has been detected. If the query of step  214  is affirmatively answered, the process  200  proceeds to step  216 . At step  216 , the received digital stream is frame-synchronized and polarity “1” is assigned to the received digital stream. Additionally, at step  216 , such data stream is bit-inverted. At step  217 , the process proceeds to an in-frame monitoring state, where the input sequence is tested periodically for the presence of the inverted FAS at the expected positions. At step  218 , the process  200  queries if the inverted FAS is found at the expected positions in the received stream. If the query of step  218  is answered negatively once or a predetermined number of times, the system is considered to be out-of-frame and the process  200  proceeds to step  206 . If the query of step  218  is affirmatively answered, the process  200  returns to step  217 . 
     If the query of step  214  is negatively answered, the process  200  proceeds to step  206  to repeat the search for the FAS and the inverted FAS until frame synchronization (i.e., in-frame state) is accomplished. In further embodiments, steps  214  may be performed before step  208  or steps  208  and  214  may be performed simultaneously. 
     For best understanding of embodiments discussed below in reference to  FIGS. 3-5 , the reader should refer simultaneously to  FIG. 1 . 
       FIG. 3  depicts a schematic diagram of a frame synchronization apparatus  110 A in accordance with one embodiment of the present invention. The frame synchronization apparatus  110 A generally comprises framers  310  and  312 , a multiplexer  314  of a digital stream, a memory  316 , and a controller  318 . In one embodiment, the framers  310  and  312  have the same internal architecture and built-in frame synchronization algorithm as receivers of the digital communication systems using the OOK modulation format. 
     Data inputs, or nodes,  311  of the framers  310  and  312  are coupled the interface  106 , and a data output (or node)  313  of each framer  310 ,  312  is coupled to a respective selectable port of the multiplexer  314 . Specifically, the data output of the framer  310  is coupled to a non-inverting port  325 , and the data output of the framer  312  is coupled to an inverting port  327  of the multiplexer  314 . Herein, the terms “input” and “node”, as well as the terms “output” and “node”, are used interchangeably. 
     The memory  316  provides the FAS and the inverted FAS to configuration inputs  315  of the framer  310  and the framer  312 , respectively. Arbitrarily, in the depicted embodiment, the memory  316  illustratively comprises a non-inverting output  331  for outputting the FAS and an inverting output  333  FAS for outputting the inverted FAS. Alternatively, when the memory  316  comprises only the non-inverting output  331 , such an output may be coupled, through an inverter (not shown) to the configuration input  315  of the framer  312 . Similarly, when the memory  316  comprises only the inverting output  333 , such an output may be coupled, through an inverter (not shown), to the configuration input  315  of the framer  310 . 
     The framers  310  and  312  independently search for the FAS (framer  310 ) and the inverted FAS (framer  312 ). Once a framer detects the FAS or the inverted FAS, the framer facilitates frame synchronization in the received digital stream. Each framer selectively communicates to the controller  318  when the FAS (framer  310 ) or the inverted FAS (framer  312 ) are detected and, as such, the digital stream is frame-synchronized. Such information is provided from status outputs  317  of the framers to the respective status inputs  319  and  321  of the controller  318 . 
     An output  323  of the controller  318  is coupled to a selecting port  335  of the multiplexer  314 . Once the FAS or the inverted FAS has been detected by one of the framers, the controller  318  sets the multiplexer  314  to provide connectivity between the data output  313  of that framer to the output  329  of the multiplexer  314  and, as such, to the bus  108 . 
     For example, when the framer  310  detects the FAS, the controller  318  sets the multiplexer  314  to provide connectivity between the non-inverting selectable port  325  and the output  329 . This setting of the multiplexer  314  corresponds to the in-frame state of the received digital streams that have been transmitted using OOK modulation or one of the DPSK or DBS modulation formats with the polarity “0”. 
     Accordingly, when the framer  312  detects the inverted FAS, the controller  318  sets the multiplexer  314  to provide connectivity between the inverting selectable port  327  and the output  329 . This setting corresponds to the in-frame state of the received digital streams having one of the DPSK and DBS modulation formats with the polarity “1”. 
     In one embodiment, in the in-frame state, a portion of electronic circuits in the framers  310  and  32  may by switched off to reduce power consumption in the framers. In the depicted embodiment, the controller  318 , via an interface  340 , is coupled to an optional synchronization monitoring unit (not shown) that may also control on/off state of such circuits of the framers. 
     When the DPSK or DBS modulation formats are not used in the digital communication system, the framer  312  may be disabled (e.g., turned off) and the multiplexer  314  set to provide connectivity between the non-inverting selectable port  325  and the output  329 . 
       FIG. 4  depicts a frame synchronization apparatus  110 B in accordance with another embodiment of the present invention. The frame synchronization apparatus  110 B generally comprises the framer  310 , the multiplexer  314 , the memory  316 , a multiplexer  402 , and a controller  404 . 
     The data input  311  of the framer  310  is coupled to the interface  106  and the data output  313  of the framer is coupled, in parallel, to the non-inverting port  325  and the inverting port  327  of the multiplexer  314 . 
     The memory  316  provides the FAS and the inverted FAS to selectable inputs  401  and  403  of the multiplexer  402  which output  405  is coupled to the configuration input  315  of the framer  310 . When the memory  316  comprises only the non-inverting output  331  or only the inverting output  333 , such an output may be coupled, through an inverter (not shown) to one of selectable inputs of the multiplexer  402  or, alternatively, the multiplexer  402  may comprise an inverting selectable input (e.g., input  403 ). 
     The controller  404  includes a timer  406  and, in operation, defines the settings of the multiplexer  314  and  402 . Similar to the controller  318  (discussed in reference to  FIG. 3  above), the controller  404  is also coupled, via the interface  340 , to the optional synchronization monitoring unit. In an out-of-frame mode, the controller  404 , via an output  409  coupled to a selecting port  407  of the multiplexer  402 , intermittently provides, for a duration of a pre-determined time interval ΔT, or equivalently, a given number of incoming symbols, one of the FAS and the inverted FAS to the configuration input  315  of the framer  310 . The duration of the time interval ΔT is controlled using the timer  406  and, generally, comprises several frame periods (e.g. 2-5 frame periods), while the minimal duration of the time interval ΔT is equal to duration of one frame period in the received digital stream. 
     The search the FAS and the inverted FAS (i.e., cyclical switching the selectable ports  410  and  403  of the multiplexer  402 ) is repeated until the in-frame state is accomplished. Similarly, in operation, such a search is repeated when the frame synchronization is lost and should be restored. 
     The status output  317  of the framer  310  is coupled to a status input  411  of the controller  404 , and an output  413  of the controller  404  is coupled to a selecting port  329  of the multiplexer  314 . The framer  310  communicated to the controller  404  when the in-frame state is established, while the controller keeps track if that happened when the FAS or the inverted FAS was supplied to the framer  310 . 
     When the frame synchronization is accomplished during the time of supplying the FAS to the framer  310 , the controller  310  sets the multiplexer  314  to provide connectivity between the non-inverting selectable port  325  and the output  329 . This setting of the multiplexer  314  corresponds to the frame-synchronized digital streams that were transmitted using OOK modulation or one of the DPSK and DBS modulation formats with the polarity “0”. 
     Oppositely, when the frame synchronization is accomplished during the time of supplying the inverted FAS to the framer  310 , the controller  310  sets the multiplexer  314  to provide connectivity between the inverting selectable port  327  and the output  329 . This setting corresponds to the frame-synchronized digital streams having one of the DPSK or DBS modulation formats with the polarity “1”. 
     When the DPSK or DBS modulation formats are not used in the digital communication system, the multiplexer  314  may be set to supply only the FAS to the framer  310 . 
       FIG. 5  depicts a frame synchronization apparatus  110 C in accordance with yet another embodiment of the present invention. The frame synchronization apparatus  110 C generally comprises the framer  310 , the multiplexer  314 , the memory  316 , and the controller  404 . The interface  106  in coupled, in parallel, to the selectable inputs  325  and  327  of the multiplexer  314 , while the output  329  of the multiplexer and the bus  108  are coupled to the data input  311  and the data output  313  of the framer  310 , respectively. 
     In this embodiment, the output  409  of the controller  404  is coupled to the selecting port  335  of the multiplexer  314 . In operation, in the out-of-frame state, the controller  404  intermittently connects, for the duration of the time interval ΔT, the data input  311  of the framer  310  to non-inverted and inverted the received digital streams provided by the interface  106 . 
     The search for the FAS and the inverted FAS (i.e., cyclical switching the selectable ports of the multiplexer  314 ) is repeated until the in-frame state is accomplished. Similarly, in operation, such a search is repeated when frame synchronization is lost and should be restored. The framer  310  communicates to the controller  404  when the in-frame state is established, while the controller keeps track if that happened when the non-inverted or the inverted digital streams were supplied to the framer  310 . 
     Similar to the apparatus  110 B (discussed in reference to  FIG. 4  above), the duration of the time interval ΔT is controlled using the timer  406 . Generally, such duration comprises several frame periods (e.g. 2-5 frame periods), while the minimal duration of the time interval ΔT is equal to duration of one frame period. 
     When the frame synchronization is accomplished during the time of supplying the non-inverted digital stream to the framer  310 , the controller  310  sets the multiplexer  314  to provide, in operation, connectivity between the non-inverting selectable port  325  and the output  329 . This setting of the multiplexer  314  corresponds to the frame-synchronized digital streams having been transmitted using the OOK modulation format or one of the DPSK and DBS modulation formats, and detected with the polarity “0”. 
     Oppositely, when the frame synchronization is accomplished during the time of supplying the inverted bit sequences to the framer  310 , the controller  310  sets the multiplexer  314  to provide, in operation, connectivity between the inverting selectable port  327  and the output  329 . This setting corresponds to the frame-synchronized digital streams having one of the DPSK and DBS modulation formats with the polarity “1”. 
     When the DPSK or DBS modulation formats are not used in the digital communication system, the multiplexer  314  may be set to provide connectivity between the non-inverting selectable port  325  and the output  329 . 
     In one illustrative embodiment, the apparatuses  100 A- 100 C were reduced to practice using framers commercially available from Broadcom Corporation of Irvine, Calif. and other suppliers. 
     The invention is described above as using specific functions and devices. It will be appreciated by those skilled in the art that a large number of functions and devices that may alternatively be employed, either individually or in combination, to achieve the objects of the invention described herein are within the scope of the invention. 
     While the forgoing is directed to various embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof. As such, the appropriate scope of the invention is to be determined according to the claims, which follow.