Patent Publication Number: US-11658392-B2

Title: Package structure

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application is a continuation application of and claims the priority benefit of a prior application Ser. No. 16/671,182, filed on Nov. 1, 2019 and now allowed. The prior application Ser. No. 16/671,182 is a continuation application of and claims the priority benefit of a prior application Ser. No. 15/879,456, filed on Jan. 25, 2018 and now allowed, which claims the priority benefit of U.S. provisional application Ser. No. 62/565,107, filed on Sep. 29, 2017. The entirety of each of the above-mentioned patent applications is hereby incorporated by reference herein and made a part of this specification. 
    
    
     BACKGROUND 
     Semiconductor devices and integrated circuits used in a variety of electronic applications, such as cell phones and other mobile electronic equipment, are typically manufactured on a single semiconductor wafer. The dies of the wafer may be processed and packaged with other semiconductor devices (e.g. antenna) or dies at the wafer level, and various technologies have been developed for the wafer level packaging. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. 
         FIG.  1 A  is a schematic three-dimensional side-view diagram of a package structure according to some exemplary embodiments of the present disclosure. 
         FIG.  1 B  is a schematic cross-sectional view of the package structure depicted in  FIG.  1 A . 
         FIG.  1 C  is a schematic explosive view illustrating the package structure depicted in  FIG.  1 A . 
         FIG.  2 A  is a schematic three-dimensional side-view diagram of a package structure according to some exemplary embodiments of the present disclosure. 
         FIG.  2 B  is a schematic cross-sectional view of the package structure depicted in  FIG.  2 A . 
         FIG.  2 C  is a schematic explosive view illustrating the package structure depicted in  FIG.  2 A . 
         FIG.  3 A  is a schematic three-dimensional side-view diagram of a package structure according to some exemplary embodiments of the present disclosure. 
         FIG.  3 B  is a schematic cross-sectional view of the package structure depicted in  FIG.  3 A . 
         FIG.  3 C  is a schematic explosive view illustrating the package structure depicted in  FIG.  3 A . 
         FIG.  4 A  is a schematic three-dimensional side-view diagram of a package structure according to some exemplary embodiments of the present disclosure. 
         FIG.  4 B  is a schematic cross-sectional view of the package structure depicted in  FIG.  4 A . 
         FIG.  4 C  is a schematic explosive view illustrating the package structure depicted in  FIG.  4 A . 
         FIG.  5 A  is a schematic three-dimensional side-view diagram of a package structure according to some exemplary embodiments of the present disclosure. 
         FIG.  5 B  is a schematic cross-sectional view of the package structure depicted in  FIG.  5 A . 
         FIG.  5 C  is a schematic explosive view illustrating the package structure depicted in  FIG.  5 A . 
     
    
    
     DETAILED DESCRIPTION 
     The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components, values, operations, materials, arrangements, or the like, are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. Other components, values, operations, materials, arrangements, or the like, are contemplated. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. 
     Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature&#39;s relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. 
     In addition, terms, such as “first,” “second,” “third,” “fourth,” “fifth,” and the like, may be used herein for ease of description to describe similar or different element(s) or feature(s) as illustrated in the figures, and may be used interchangeably depending on the order of the presence or the contexts of the description. 
     Other features and processes may also be included. For example, testing structures may be included to aid in the verification testing of the 3D packaging or 3DIC devices. The testing structures may include, for example, test pads formed in a redistribution layer or on a substrate that allows the testing of the 3D packaging or 3DIC, the use of probes and/or probe cards, and the like. The verification testing may be performed on intermediate structures as well as the final structure. Additionally, the structures and methods disclosed herein may be used in conjunction with testing methodologies that incorporate intermediate verification of known good dies to increase the yield and decrease costs. 
       FIG.  1 A  is a schematic three-dimensional side-view diagram of a package structure according to some exemplary embodiments of the present disclosure.  FIG.  1 B  is a schematic cross-sectional view of the package structure depicted in  FIG.  1 A .  FIG.  1 C  is a schematic explosive view illustrating the package structure depicted in  FIG.  1 A .  FIG.  1 B  is the schematic cross sectional view taken along a section line A-A′ depicted in  FIG.  1 C . Some components shown in  FIG.  1 B  is omitted in  FIG.  1 A  and  FIG.  1 C  to show concise, schematic explosive views. The embodiments are intended to provide further explanations but are not used to limit the scope of the present disclosure. In  FIG.  1 A  to  FIG.  1 C , only one die, three first antennas and three second antennas are presented for illustrative purposes; however, it should be noted that one or more dies, one or more first antennas, and one or more second antennas may be provided. 
     Referring to  FIG.  1 A ,  FIG.  1 B  and  FIG.  1 C , in some embodiments, a package structure  10  includes a redistribution structure  110 , at least one through interlayer via (TIV)  120 , a semiconductor die  130 , an insulating encapsulation  140 , a first isolation layer  152 , a second isolation layer  154 , first antennas  160   a , second antennas  160   b , and conductive elements  180 . As shown in  FIG.  1 A  to  FIG.  1 C , in some embodiments, the semiconductor die  130 , the first antennas  160   a , and the second antennas  160   b  are at different levels and are encapsulated in the insulating encapsulation  140 . In some embodiments, from bottom to top (e.g., along a direction Z), the stacking order is, for example, the semiconductor die  130 , the second antennas  160   b , and the first antennas  160   a.    
     Referring to  FIG.  1 A  and  FIG.  1 B , in some embodiments, the insulating encapsulation  140  includes a first portion  142 , a second portion  144 , and a third portion  146 , where the second portion  144  is sandwiched between the first portion  142  and the third portion  146 . In some embodiments, the semiconductor die  130  is encapsulated in the first portion  142  of the insulating encapsulation  140 , the first antennas  160   a  are encapsulated in the third portion  146  of the insulating encapsulation  140 , and the second antennas  160   b  are encapsulated in the second portion  144  of the insulation encapsulation  140 . The insulating encapsulation  140  includes, for example, an epoxy resin, or any other suitable type of encapsulating material, where the disclosure is not limited thereto. Depending on the frequency range of the antenna applications, suitable materials of the insulating encapsulation  140  may be selected based on the required electrical properties of the package structure. In certain embodiments, the materials of the first portion  142 , the second portion  144  and the third portion  146  of the insulating encapsulation  140  may be the same. However, in an alternative embodiment, the materials of the first portion  142 , the second portion  144  and the third portion  146  of the insulating encapsulation  140  may be different. The disclosure is not limited thereto. 
     Referring to  FIG.  1 B , in some embodiments, the semiconductor die  130  includes an active surface  130   a , a plurality of pads  130   b  distributed on the active surface  130   a , a passivation layer  130   c  covering the active surface  130   a  and a portion of the pad  130   b , a plurality of conductive pillars  130   d  connecting to the pads  130   b , a dielectric layer  130   e , and a backside surface  130   f  opposite to the active surface  130   a . The pads  130   b  are partially exposed by the passivation layer  130   c , the conductive pillars  130   d  are disposed on and electrically connected to the pads  130   b , and the dielectric layer  130   e  covers the passivation layer  130   c  and exposes the conductive pillars  130   d . The pads  130   b  may be aluminum pads or other suitable metal pads, for example. The conductive pillars  130   d  may be copper pillars, copper alloy pillars or other suitable metal pillars, for example. In some embodiments, the passivation layer  130   c  and the dielectric layer  130   e  may be a polybenzoxazole (PBO) layer, a polyimide (PI) layer or other suitable polymer layers. In some alternative embodiments, the passivation layer  130   c  and the dielectric layer  130   e  may be made of inorganic materials, such as silicon oxide, silicon nitride, silicon oxynitride, or any suitable dielectric material. The material of the passivation layer  130   c  can be the same or different from the material of the dielectric layer  130   e , for example. In an alternative embodiment, the semiconductor die  130  may include the pads  130   b  distributed on the active surface  130   a , the passivation layer  130   c  covering the active surface  130   a  and a portion of the pad  130   b , the backside surface  130   f  opposite to the active surface  130   a , where the conductive pillars  130   d  and the dielectric layer  130   e  may be omitted. As shown in  FIG.  1 A  to  FIG.  1 C , only one semiconductor die is presented for illustrative purposes, however, it should be noted that one or more semiconductor dies may be provided. In some embodiments, the semiconductor die  130  described herein may be referred as a chip or an integrated circuit (IC). In certain embodiments, the semiconductor die  130  may further include additional chip(s) of the same type or different types. For example, in an alternative embodiment, more than one semiconductor die  130  is provided, and the semiconductor dies  130 , except for including at least one wireless and RF chip, may include the same or different types of chips selected from digital chips, analog chips, mixed signal chips, application-specific integrated circuit (“ASIC”) chips, sensor chips, memory chips, logic chips or voltage regulator chips. 
     Referring to  FIG.  1 B , in some embodiments, the first isolation layer  152  and the redistribution structure  110  are located at two opposite sides of the semiconductor die  130 . The first isolation layer  152  is sandwiched between the first portion  142  of the insulating encapsulation  140  and the second portion  144  of the insulating encapsulation  140 . In some embodiments, the first isolation layer  152  is located between a first polymer dielectric layer PD1 and a second polymer dielectric layer PD2. The first polymer dielectric layer PD1, the first isolation layer  152  and the second polymer dielectric layer PD2 are sequentially stacked one over another, and are located between the first portion  142  of the insulating encapsulation  140  and the second portion  144  of the insulating encapsulation  140 . In some embodiments, the first polymer dielectric layer PD1 is located between the first isolation layer  152  and the first portion  142  of the insulating encapsulation  140 , while the second polymer dielectric layer PD2 is located between the second portion  144  of the insulating encapsulation  140  and the first isolation layer  152 . The disclosure is not limited thereto, for example, in one embodiment, the first polymer dielectric layer PD1 may be optionally omitted. In an alternative embodiment, the second polymer dielectric layer PD2 may be optionally omitted. In some embodiments, the material of the first isolation layer  152  may include aluminum, titanium, copper, nickel, tungsten, and/or alloys thereof. In some embodiments, the materials of the first polymer dielectric layer PD1 and the second polymer dielectric layer PD2 may include polyimide, benzocyclobutene (BCB), polybenzooxazole (PBO), or any other suitable polymer-based dielectric material. In one embodiment, the material of the first polymer dielectric layer PD1 may be the same as the material of the second polymer dielectric layer PD2. In an alternative embodiment, the material of the first polymer dielectric layer PD1 may be different from the material of the second polymer dielectric layer PD2. 
     In certain embodiments, a die attach film DA is provided between the backside surface  130   f  of the semiconductor die  130  and the first polymer dielectric layer PD1, as shown in  FIG.  1 B . In some embodiments, due to the die attach film DA provided between the semiconductor die  130  and the first polymer dielectric layer PD1, the semiconductor die  130  is stably adhered to the first polymer dielectric layer PD1. 
     Referring to  FIG.  1 B , in some embodiments, the redistribution structure  110  includes one or more metallization layers and one or more polymer-based dielectric layers. As seen in  FIG.  1 B , the redistribution structure  110  includes a first polymer dielectric material layer  112   a , a first metallization layer  114   a , a second polymer dielectric material layer  112   b , a second metallization layer  114   b , and a third polymer dielectric material layer  112   c . The first metallization layer  114   a  is sandwiched between the second polymer dielectric material layer  112   b  and the first polymer dielectric material layer  112   a , and the second metallization layer  114   b  is sandwiched between the third polymer dielectric material layer  112   c  and the second polymer dielectric material layer  112   b . In certain embodiments, a top surface of the first metallization layers  114   a  is exposed by the first polymer dielectric material layers  112   a , and a bottom surface of the second metallization layers  114   b  is exposed by the third polymer dielectric material layers  112   c.    
     In some embodiments, the active surface  130   a  of the semiconductor die  130  faces the redistribution structure  110 , and the backside surface  130   f  of the semiconductor die  130  faces the first isolation layer  152 . In one embodiment, the exposed top surface of the first metallization layer  114   a  is connected to the conductive pillars  130   d  located on the active surface  130   a  of the semiconductor die  130  so as to electrically connect the semiconductor die  130  to the redistribution structure  110 , and the exposed bottom surface of the second metallization layer  114   b  is connected to the conductive elements  180 . In an alternative embodiment, the exposed bottom surface of the second metallization layer  114   b  is connected to the conductive elements  180  (e.g., conductive balls, such as solder balls) and semiconductor elements  190  (e.g., passive components or active components according to the product requirements). As shown in  FIG.  1 B , the redistribution structure  110  is located between the semiconductor die  130  and the conductive elements  180  and between the semiconductor die  130  and semiconductor elements  190 . 
     In some embodiments, the materials of the first metallization layer  114   a  and the second metallization layer  114   b  may include aluminum, titanium, copper, nickel, tungsten, and/or alloys thereof. In some embodiments, the materials of the first polymer dielectric material layers  112   a , the second polymer dielectric material layers  112   b  and the third polymer dielectric material layer  112   c  may include polyimide, benzocyclobutene (BCB), polybenzooxazole (PBO), or any other suitable polymer-based dielectric material. It should be noted that the redistribution structure  110  is not limited to include three polymer dielectric material layers and/or two metallization layers, i.e., the number of dielectric layer(s) and/or metallization layer(s) is not limited to what is disclosed herein according to the present disclosure. 
     In certain embodiments, a plurality of under-ball metallurgy (UBM) patterns u1, u2 are formed on the exposed bottom surface of the second metallization layers  114   b  of the redistribution structure  110  for electrically connecting with the conductive elements  180  and/or the semiconductor elements  190 , respectively. As shown in  FIG.  1 B , for example, the under-ball metallurgy patterns u1 are located between the conductive elements  180  and the exposed bottom surface of the second metallization layers  114   b , and the under-ball metallurgy patterns u2 are located between the semiconductor elements  190  and the exposed bottom surface of the second metallization layers  114   b , however, the disclosure is not limited thereto. Due to the under-ball metallurgy patterns u1 and u2 are formed on the exposed bottom surface of the second metallization layers  114   b  of the redistribution structure  110 , the later-formed conductive elements  180  and/or the semiconductor elements  190  can be accurately located on the under-ball metallurgy patterns u1 and u2 with better fixation, and the ball drop yield and reliability of the package structure  10  are improved. In some embodiments, the under-ball metallurgy patterns u1 and u2 may include copper, nickel, titanium, a combination thereof or the like, and are formed by, e.g., an electroplating process. 
     Referring to  FIG.  1 B , in some embodiments, the second isolation layer  154  is sandwiched between the third portion  146  of the insulating encapsulation  140  and the second portion  144  of the insulating encapsulation  140 . In some embodiments, the second isolation layer  154  is located between a third polymer dielectric layer PD3 and a fourth polymer dielectric layer PD4. The third polymer dielectric layer PD3, the second isolation layer  154  and the fourth polymer dielectric layer PD4 are sequentially stacked one over another, and are located between the third portion  146  of the insulating encapsulation  140  and the second portion  144  of the insulating encapsulation  140 . In some embodiments, the third polymer dielectric layer PD3 is located between the second isolation layer  154  and the second portion  144  of the insulating encapsulation  140 , while the fourth polymer dielectric layer PD4 is located between the third portion  146  of the insulating encapsulation  140  and the second isolation layer  154 . The disclosure is not limited thereto, for example, in one embodiment, the third polymer dielectric layer PD3 may be optionally omitted. In an alternative embodiment, the fourth polymer dielectric layer PD4 may be optionally omitted. In some embodiments, the material of the second isolation layer  154  may include aluminum, titanium, copper, nickel, tungsten, and/or alloys thereof. In some embodiments, the materials of the third polymer dielectric layer PD3 and the fourth polymer dielectric layer PD4 may include polyimide, benzocyclobutene (BCB), polybenzooxazole (PBO), or any other suitable polymer-based dielectric material. In one embodiment, the material of the third polymer dielectric layer PD3 may be the same as the material of the fourth polymer dielectric layer PD4. In an alternative embodiment, the material of the third polymer dielectric layer PD3 may be different from the material of the fourth polymer dielectric layer PD4. 
     In certain embodiments, the materials of the first isolation layer  152  and the second isolation layer  154  may be the same or different. In certain embodiments, the materials of the first polymer dielectric layer PD1, the second polymer dielectric layer PD2, the third polymer dielectric layer PD3 and the fourth polymer dielectric layer PD4 may be the same or different. The disclosure is not limited thereto. The first isolation layer  152  and the second isolation layer  154  function as shielding layers of an electric signal or radiating wave to prevent the semiconductor die  130  being affected by either the first antennas  160   a  or the second antennas  160   b  and/or to prevent the first antennas  160   a  or the second antennas  160   b  being affected by each other or by the semiconductor die  130 . Furthermore, in some embodiments, the first isolation layer  152  and the second isolation layer  154  may include isolation layers having patterns, where portions of each of the first isolation layer  152  and the second isolation layer  154  are electrically connected to the semiconductor die  130  and serve as signal patterns, and other portions of each of the first isolation layer  152  and the second isolation layer  154  are electrically isolated to the semiconductor die  130  and serve as antenna ground. 
     Referring to  FIG.  1 B , in some embodiments, the at least one TIV  120  includes a first TIV  122  and a second TIV  124 . In some embodiments, the first TIV  122  and the second TIV  124  may be through integrated fan-out (InFO) vias. For simplification, only one first TIV  122  and one second TIV  124  are presented for illustrative purposes, however, it should be noted that more than two first TIV and/or second TIV may be formed; the disclosure is not limited thereto. The numbers of the first TIV  122  and the second TIV  124  can be selected based on the demand. 
     In some embodiments, the first TIV  122  is encapsulated in the first portion  142  of the insulating encapsulation  140 . In some embodiments, a first end  122   a  of the first TIV  122  is connected to the exposed top surface of the first metallization layer  114   a  of the redistribution structure  110  so as to electrically connect to the semiconductor die  130 , and a second end  122   b  of the first TIV  122  is connected to the first isolation layer  152  exposed by an opening O 1  of the first polymer dielectric layer PD1, where the first end  122   a  is opposite to the second end  122   b . In some embodiments, the second TIV  124  is encapsulated in the second portion  144  of the insulating encapsulation  140 . In some embodiments, as shown in  FIG.  1 B , a first end  124   a  of the second TIV  124  is connected to the first isolation layer  152  exposed by an opening O 2  of the second polymer dielectric layer PD2 so as to electrically connect to the first isolation layer  152 , and a second end  124   b  of the second TIV  124  is connected to the second isolation layer  154  exposed by an opening O 3  of the third polymer dielectric layer PD3, where the first end  124   a  is opposite to the second end  124   b . In certain embodiments, the first TIV  122  and the second TIV  124  are electrically connected to the redistribution structure  110 . As shown in  FIG.  1 B , the first TIV  122  is electrically connected to the semiconductor die  130  through the redistribution structure  110 , and the second TIV  124  is electrically connected to the semiconductor die  130  through the first isolation layer  152 , the first TIV  122 , and the redistribution structure  110 . In one embodiment, the material of the first TIV  122  and the second TIV  124  may include a metal material such as copper or copper alloys, or the like. 
     Referring to  FIG.  1 C , in some embodiments, each of the first antennas  160   a  include a first reflector  162   a , a pair of first drivers  164   a , and first directors  166   a . As shown in  FIG.  1 B , in some embodiments, the first reflector  162   a  and the first drivers  164   a  of each first antenna  160   a  are respectively connected to the second isolation layer  154  exposed by an opening O 5  and an opening O 6  of the fourth polymer dielectric layer PD4 so as to electrically connect to the second isolation layer  154 . In other words, the first antennas  160   a  are electrically connected to the semiconductor die  130  through the second isolation layer  154 , the second TIV  124 , the first isolation layer  152 , the first TIV  122 , and the redistribution structure  110 . In some embodiments, the first antennas  160   a  generate an electromagnetic wave (such as microwaves) propagating along a first direction X, where the first reflector  162   a , the first drivers  164   a , and the first directors  166   a  are sequentially arranged along the first direction X and are separated apart from each other. The first drivers  164   a  are arranged in parallel along a second direction Y and are located between the first reflector  162   a  and the first directors  166   a  along the first direction X, where the first direction X is different from the second direction Y. In other words, as the first reflector  162   a  and the first drivers  164   a  are connected to the second isolation layer  154 , and the first drivers  164   a  are located between the first reflector  162   a  and the first directors  166   a  along the first direction X (which is a propagating direction of the electromagnetic wave generated by the first antennas  160   a ), where the first reflectors  162   a  and the first drivers  164   a  are overlapped with the second isolation layer  154  along the direction Z. In other words, the first reflectors  162   a  and the first drivers  164   a  stand on the second isolation layer  154 , for example. In certain embodiments, the first direction X is perpendicular to the second direction Y, as shown in  FIG.  1 C . In certain embodiments, the direction Z is perpendicular to the first direction X and the second direction Y, as shown in  FIG.  1 C . In some embodiments, as shown in  FIG.  1 C , three first directors  166   a  are included in one first antenna  160   a ; however, the disclosure is not limited. In an alternative embodiment, the number of the first directors  166   a  may be one. 
     Referring to  FIG.  1 C , in some embodiments, each of the second antennas  160   b  includes a second reflector  162   b , a pair of second drivers  164   b , and second directors  166   b . As shown in  FIG.  1 B , in some embodiments, the second reflector  162   b  and the second drivers  164   b  of each second antenna  160   b  are connected to the first isolation layer  152  exposed by an opening O 4  of the second polymer dielectric layer PD2 so as to electrically connect to the first isolation layer  152 . In other words, the second antennas  160   b  are electrically connected to the semiconductor die  130  through the first isolation layer  152 , the first TIV  122 , and the redistribution structure  110 . In some embodiments, the second antennas  160   b  generate an electromagnetic wave (such as microwaves) propagating along the second direction Y, where the second reflector  162   b , the second drivers  164   b , and the second directors  166   b  are sequentially arranged along the second direction Y and are separated apart from each other. The second drivers  164   b  are arranged in parallel along the first direction X and are located between the second reflector  162   b  and the second directors  166   b  along the second direction Y. In other words, the second reflector  162   b  and the second drivers  164   b  are connected to the first isolation layer  152 , and the second drivers  164   b  are located between the second reflector  162   b  and the second directors  166   b  along the second direction Y (which is a propagating direction of the electromagnetic wave generated by the second antennas  160   b ), where the second reflectors  162   b  and the second drivers  164   b  are overlapped with the first isolation layer  152  along the direction Z. In some embodiments, as shown in  FIG.  1 C , three second directors  166   b  are included in one second antenna  160   b ; however, the disclosure is not limited. In an alternative embodiment, the number of the second directors  166   b  may be one, less than three or more than three. 
     In some embodiments, the first antennas  160   a  and the second antennas  160   b  are configured as Yagi-Uda antennas. In some embodiments, the first antennas  160   a  and the second antennas  160   b  may be end-fire antennas or polarized end-fire antennas (such as horizontal polarized end-fire antennas as shown in  FIG.  1 C  or vertical polarized end-fire antennas (not shown)), but the disclosure is not limited thereto. In one embodiment, the first antennas  160   a  and the second antennas  160   b  may have the same structure or different structures. Owing to such configuration, the first antennas  160   a  and the second antennas  160   b  are capable of generating electromagnetic waves according to electric signals transmitted from the semiconductor die  130  and/or receiving electromagnetic waves to be processed by the semiconductor die  130 . In some embodiments, the first antennas  160   a  and the second antennas  160   b  may also be employed to receive electromagnetic waves. That is to say, the first antennas  160   a  and the second antennas  160   b  may be configured to generate electromagnetic waves in a first time period, and then the first antennas  160   a  and the second antennas  160   b  may be re-assigned to be configured to receive electromagnetic waves in a second time period. Owing to the first antennas  160   a  and the second antennas  160   b , a coverage range of the electromagnetic waves generated from the package structure  10  is increased, and thus the efficiency of the antenna application of the package structure  10  is enhanced. In an alternative embodiment, the first antennas  160   a  may be configured to generate electromagnetic waves while the second antenna  160   b  may be configured to receive electromagnetic waves, or vice versa. 
       FIG.  2 A  is a schematic three-dimensional side-view diagram of a package structure according to some exemplary embodiments of the present disclosure.  FIG.  2 B  is a schematic cross-sectional view of the package structure depicted in  FIG.  2 A .  FIG.  2 C  is a schematic explosive view illustrating the package structure depicted in  FIG.  2 A .  FIG.  2 B  is the schematic cross sectional view taken along a section line B-B′ depicted in  FIG.  2 C . Some components shown in  FIG.  2 B  is omitted in  FIG.  2 A  and  FIG.  2 C  to show concise, schematic explosive views. The embodiments are intended to provide further explanations but are not used to limit the scope of the present disclosure. In  FIG.  2 A  to  FIG.  2 C , only one die, four first antennas and four second antennas are presented for illustrative purposes; however, it should be noted that one or more dies, one or more first antennas, and one or more second antennas may be provided. 
     Referring to  FIG.  1 A  to  FIG.  1 C  and  FIG.  2 A  to  FIG.  2 C  together, the package structure  10  depicted in  FIG.  1 A  to  FIG.  1 C  and the package structure  20  depicted in  FIG.  2 A  to  FIG.  2 C  has elements similar to or substantially the same, the elements depicted in  FIG.  2 A  to  FIG.  2 C  similar to or substantially the same as the elements described above in  FIG.  1 A  to  FIG.  1 C  will use the same reference numbers, and certain details or descriptions of the same elements will not be repeated herein, for simplicity. 
     Referring to  FIG.  2 A ,  FIG.  2 B  and  FIG.  2 C , in some embodiments, a package structure  20  includes a redistribution structure  110 , at least one TIV  120 , a semiconductor die  130 , an insulating encapsulation  140 , a first isolation layer  152 , first antennas  160   a , second antennas  160   b , a first through interlayer via (TIV) wall  172 , a second TIV wall  174 , and conductive elements  180 . 
     Referring to  FIG.  2 A  and  FIG.  2 B , in some embodiments, the insulating encapsulation  140  includes a first portion  142  and a second portion  144 . In some embodiments, the semiconductor die  130 , a portion of the first antennas  160   a  and a portion of the second antennas  160   b  are encapsulated in the first portion  142  of the insulating encapsulation  140 , and another portion of the first antennas  160   a  and another portion of the second antennas  160   b  are encapsulated in the second portion  144  of the insulation encapsulation  140 . 
     Referring to  FIG.  2 B , in some embodiments, the semiconductor die  130  includes an active surface  130   a , a plurality of pads  130   b  distributed on the active surface  130   a , a passivation layer  130   c  covering the active surface  130   a  and a portion of the pad  130   b , a plurality of conductive pillars  130   d  connecting to the pads  130   b , a dielectric layer  130   e , and the backside surface  130   f  opposite to the active surface  130   a . The pads  130   b  are partially exposed by the passivation layer  130   c , the conductive pillars  130   d  are disposed on and electrically connected to the pads  130   b , and the dielectric layer  130   e  covers the passivation layer  130   c  and exposes the conductive pillars  130   d . In an alternative embodiment, the semiconductor die  130  may include the pads  130   b  distributed on the active surface  130   a , the passivation layer  130   c  covering the active surface  130   a  and a portion of the pad  130   b , the backside surface  130   f  opposite to the active surface  130   a , where the conductive pillars  130   d  and the dielectric layer  130   e  may be omitted. As shown in  FIG.  2 A  to  FIG.  2 C , only one semiconductor die is presented for illustrative purposes, however, it should be noted that one or more semiconductor dies may be provided. 
     Referring to  FIG.  2 B , in some embodiments, the first isolation layer  152  and the redistribution structure  110  are located at two opposite sides of the semiconductor die  130 . The first isolation layer  152  is sandwiched between the first portion  142  of the insulating encapsulation  140  and the second portion  144  of the insulating encapsulation  140 . In some embodiments, the first isolation layer  152  is located between a first polymer dielectric layer PD1 and a second polymer dielectric layer PD2. The first polymer dielectric layer PD1, the first isolation layer  152  and the second polymer dielectric layer PD2 are sequentially stacked one over another, and are located between the first portion  142  of the insulating encapsulation  140  and the second portion  144  of the insulating encapsulation  140 . In some embodiments, the first polymer dielectric layer PD1 is located between the first isolation layer  152  and the first portion  142  of the insulating encapsulation  140 , while the second polymer dielectric layer PD2 is located between the second portion  144  of the insulating encapsulation  140  and the first isolation layer  152 . The disclosure is not limited thereto, for example, in one embodiment, the first polymer dielectric layer PD1 may be optionally omitted. In an alternative embodiment, the second polymer dielectric layer PD2 may be optionally omitted. The first isolation layer  152  functions as a shielding layer of an electric signal or radiating wave to prevent the semiconductor die  130  being affected by either the first antennas  160   a  and/or the second antennas  160   b  and/or to prevent the first antennas  160   a  or the second antennas  160   b  being affected by each other or by the semiconductor die  130 . Furthermore, in some embodiments, the first isolation layer  152  may include an isolation layer having patterns, where portions of the first isolation layer  152  are electrically connected to the semiconductor die  130  and serve as signal patterns, and other portions of the first isolation layer  152  are electrically isolated to the semiconductor die  130  and serve as antenna ground. 
     In certain embodiments, a die attach film DA is provided between the backside surface  130   f  of the semiconductor die  130  and the first polymer dielectric layer PD1, as shown in  FIG.  2 B . In some embodiments, due to the die attach film DA provided between the semiconductor die  130  and the first polymer dielectric layer PD1, the semiconductor die  130  is stably adhered to the first polymer dielectric layer PD1. 
     Referring to  FIG.  2 B , in some embodiments, the redistribution structure  110  includes one or more metallization layers and one or more polymer-based dielectric layers. In some embodiments, the redistribution structure  110  includes a first polymer dielectric material layer  112   a , a first metallization layer  114   a , a second polymer dielectric material layer  112   b , a second metallization layer  114   b , and a third polymer dielectric material layer  112   c . The first metallization layer  114   a  is sandwiched between the second polymer dielectric material layer  112   b  and the first polymer dielectric material layer  112   a , and the second metallization layer  114   b  is sandwiched between the third polymer dielectric material layer  112   c  and the second polymer dielectric material layer  112   b . In certain embodiments, a top surface of the first metallization layers  114   a  is exposed by the first polymer dielectric material layers  112   a , and a bottom surface of the second metallization layers  114   b  is exposed by the third polymer dielectric material layers  112   c . It should be noted that the redistribution structure  110  is not limited to include three polymer dielectric material layers and/or two metallization layers, i.e., the number of dielectric layer(s) and/or metallization layer(s) is not limited to what is disclosed herein according to the present disclosure. 
     In some embodiments, the exposed top surface of the first metallization layer  114   a  is connected to the conductive pillars  130   d  located on the active surface  130   a  of the semiconductor die  130  so as to electrically connect the semiconductor die  130  to the redistribution structure  110 , and the exposed bottom surface of the second metallization layer  114   b  is connected to the conductive elements  180 . In an alternative embodiment, the exposed bottom surface of the second metallization layer  114   b  is connected to the conductive elements  180  and the semiconductor elements  190 . As shown in  FIG.  2 B , the redistribution structure  110  is located between the semiconductor die  130  and the conductive elements  180 , and between the semiconductor die  130  and the semiconductor elements  190 . 
     In certain embodiments, a plurality of under-ball metallurgy (UBM) patterns u1, u2 is formed on the exposed bottom surface of the second metallization layers  114   b  of the redistribution structure  110  for electrically connecting with the conductive elements  180  and/or the semiconductor elements  190 , respectively. As shown in  FIG.  2 B , for example, the under-ball metallurgy patterns u1 are located between the conductive elements  180  and the exposed bottom surface of the second metallization layers  114   b , and the under-ball metallurgy patterns u2 are located between the semiconductor elements  190  and the exposed bottom surface of the second metallization layers  114   b , however, the disclosure is not limited thereto. Due to the under-ball metallurgy patterns u1 and u2 are formed on the exposed bottom surface of the second metallization layers  114   b  of the redistribution structure  110 , the later-formed conductive elements  180  and/or the semiconductor elements  190  can be accurately located on the under-ball metallurgy patterns u1 and u2 with better fixation, and the ball drop yield and reliability of the package structure  20  are improved. 
     Referring to  FIG.  2 B , in some embodiments, the at least one TIV  120  includes a first TIV  122 . In some embodiments, the first TIV  122  is a through integrated fan-out (InFO) via. For simplification, only one first TIV  122  is presented for illustrative purposes, however, it should be noted that more than two first TIV may be formed; the disclosure is not limited thereto. The number of the first TIV  122  can be selected based on the demand. 
     In some embodiments, the first TIV  122  is encapsulated in the first portion  142  of the insulating encapsulation  140 . In some embodiments, a first end  122   a  of the first TIV  122  is connected to the exposed top surface of the first metallization layer  114   a  of the redistribution structure  110  so as to electrically connect to the semiconductor die  130 , and a second end  122   b  of the first TIV  122  is connected to the first isolation layer  152  exposed by an opening O 1  of the first polymer dielectric layer PD1, where the first end  122   a  is opposite to the second end  122   b . As shown in  FIG.  2 B , for example, the first TIV  122  is electrically connected to the semiconductor die  130  through the redistribution structure  110 . 
     Referring to  FIG.  2 C , in some embodiments, each of the first antennas  160   a  includes a first reflector  162   a , a pair of first drivers  164   a , and first directors  166   a . In some embodiments, the first reflector  162   a  and the first drivers  164   a  of each of the first antennas  160   a  encapsulated in the first portion  142  of the insulating encapsulation  140  are connected to the exposed top surface of the first metallization layer  114   a  of the redistribution structure  110 . In other words, the first antennas  160   a  encapsulated in the first portion  142  of the insulating encapsulation  140  are electrically connected to the semiconductor die  130  through the redistribution structure  110 . In some embodiments, the first reflector  162   a  and the first drivers  164   a  of each of the first antennas  160   a  encapsulated in the second portion  144  of the insulating encapsulation  140  are connected to the first isolation layer  152  exposed by an opening O 2  of the second polymer dielectric layer PD2. In other words, the first antennas  160   a  encapsulated in the second portion  144  of the insulating encapsulation  140  are electrically connected to the semiconductor die  130  through the first isolation layer  152 , the first TIV  122 , and the redistribution structure  110 . 
     In some embodiments, the first antennas  160   a  encapsulated in the first portion  142  of the insulating encapsulation  140  generate an electromagnetic wave (such as microwaves) propagating along the first direction X. For the first antennas  160   a  encapsulated in the first portion  142  of the insulating encapsulation  140 , the first reflector  162   a , the first drivers  164   a , and the first directors  166   a  of the first antennas  160   a  encapsulated in the first portion  142  of the insulating encapsulation  140  are sequentially arranged along the first direction X and are separated apart from each other. The first drivers  164   a  are arranged in parallel along the second direction Y and are located between the first reflector  162   a  and the first directors  166   a  along the first direction X. In other words, for each first antenna  160   a  encapsulated in the first portion  142  of the insulating encapsulation  140 , the first reflector  162   a  and the first drivers  164   a  are connected to the redistribution structure  110 , and the first drivers  164   a  are located between the first reflector  162   a  and the first directors  166   a  along the first direction X (which is a propagating direction of the electromagnetic wave generated by the first antennas  160   a  encapsulated in the first portion  142  of the insulating encapsulation  140 ), where the first reflector  162   a  and the first drivers  164   a  are overlapped with the redistribution structure  110  along the direction Z. In other words, the first reflectors  162   a  and the first drivers  164   a  of the first antennas  160   a  encapsulated in the first portion  142  stand on the redistribution structure  110 , for example. 
     On the other hand, the first antennas  160   a  encapsulated in the second portion  144  of the insulating encapsulation  140  generate an electromagnetic wave (such as microwaves) propagating along a direction X′, where the direction X′ is opposite to the first direction X. The first reflector  162   a , the first drivers  164   a , and the first directors  166   a  of the first antennas  160   a  encapsulated in the second portion  144  of the insulating encapsulation  140  are sequentially arranged along the direction X′, and are separated apart from each other. For the first antennas  160   a  encapsulated in the second portion  144  of the insulating encapsulation  140 , the first drivers  164   a  are arranged in parallel along the second direction Y and are located between the first reflector  162   a  and the first directors  166   a  along the direction X′. In other words, for each first antenna  160   a  encapsulated in the second portion  144  of the insulating encapsulation  140 , the first reflector  162   a  and the first drivers  164   a  are connected to the first isolation layer  152 , and the first drivers  164   a  are located between the first reflector  162   a  and the first directors  166   a  along the direction X′ (which is a propagating direction of the electromagnetic wave generated by the first antennas  160   a  encapsulated in the second portion  144  of the insulating encapsulation  140 ), where the first reflector  162   a  and the first drivers  164   a  are overlapped with the first isolation layer  152  along the direction Z. In other words, the first reflectors  162   a  and the first drivers  164   a  of the first antennas  160   a  encapsulated in the second portion  144  stand on the first isolation layer  152 , for example. In some embodiments, as shown in  FIGS.  2 A and  2 C , two first directors  166   a  are included in one first antenna  160   a ; however, the disclosure is not limited. In an alternative embodiment, the number of the first directors  166   a  may be less than two or more than two. 
     Referring to  FIG.  2 C , in some embodiments, each of the second antennas  160   b  includes a second reflector  162   b , a pair of second drivers  164   b , and second directors  166   b . In some embodiments, as shown in  FIG.  2 B , the second reflector  162   b  and the second drivers  164   b  of each of the second antennas  160   b  encapsulated in the first portion  142  of the insulating encapsulation  140  are connected to the exposed top surface of the first metallization layer  114   a  of the redistribution structure  110 . In other words, the second antennas  160   b  encapsulated in the first portion  142  of the insulating encapsulation  140  are electrically connected to the semiconductor die  130  through the redistribution structure  110 . In some embodiments, the second reflector  162   b  and the second drivers  164   b  of each of the second antenna  160   b  encapsulated in the second portion  144  of the insulating encapsulation  140  are connected to the first isolation layer  152  exposed by an opening (not shown) of the second polymer dielectric layer PD2 so as to electrically connect to the first isolation layer  152 . In other words, the second antennas  160   b  encapsulated in the second portion  144  of the insulating encapsulation  140  are electrically connected to the semiconductor die  130  through the first isolation layer  152 , the first TIV  122 , and the redistribution structure  110 . 
     In some embodiments, the second antennas  160   b  encapsulated in the first portion  142  of the insulating encapsulation  140  generate an electromagnetic wave (such as microwaves) propagating along the second direction Y, where the second reflector  162   b , the second drivers  164   b , and the second directors  166   b  of the second antennas  160   b  encapsulated in the first portion  142  of the insulating encapsulation  140  are sequentially arranged along the second direction Y and are separated apart from each other. For the second antennas  160   b  encapsulated in the first portion  142  of the insulating encapsulation  140 , the second drivers  164   b  are arranged in parallel along the first direction X and are located between the second reflector  162   b  and the second directors  166   b  along the second direction Y. In other words, for each second antenna  160   b  encapsulated in the first portion  142  of the insulating encapsulation  140 , the second reflector  162   b  and the second drivers  164   b  are connected to the redistribution structure  110 , and the second drivers  164   b  are located between the second reflector  162   b  and the second directors  166   b  along the second direction Y (which is a propagating direction of the electromagnetic wave generated by the second antennas  160   b  encapsulated in the first portion  142  of the insulating encapsulation  140 ), where the second reflector  162   b  and the second drivers  164   b  are overlapped with the redistribution structure  110  along the direction Z. In other words, the second reflector  162   b  and the second drivers  164   b  of the second antennas  160   b  encapsulated in the first portion  142  stand on the redistribution structure  110 , for example. 
     On the other hand, the second antennas  160   b  encapsulated in the second portion  144  of the insulating encapsulation  140  generate an electromagnetic wave (such as microwaves) propagating along a direction Y′, where the direction Y′ is opposite to the second direction Y. The second reflector  162   b , the second drivers  164   b , and the second directors  166   b  of the second antennas  160   b  encapsulated in the second portion  144  of the insulating encapsulation  140  are sequentially arranged along the direction Y′, and are separated apart from each other. For the second antennas  160   b  encapsulated in the second portion  144  of the insulating encapsulation  140 , the second drivers  164   b  are arranged in parallel along the first direction X and are located between the second reflector  162   b  and the second directors  166   b  along the direction Y′. In other words, for each second antenna  160   b  encapsulated in the second portion  144  of the insulating encapsulation  140 , the second reflector  162   b  and the second drivers  164   b  are connected to the first isolation layer  152 , and the second drivers  164   b  are located between the second reflector  162   b  and the second directors  166   b  along the direction Y′ (which is a propagating direction of the electromagnetic wave generated by the second antennas  160   b  encapsulated in the second portion  144  of the insulating encapsulation  140 ), where the second reflector  162   b  and the second drivers  164   b  are overlapped with the first isolation layer  152  along the direction Z. In other words, the second reflector  162   b  and the second drivers  164   b  of the second antennas  160   b  encapsulated in the second portion  144  stand on the first isolation layer  152 , for example. In some embodiments, as shown in  FIGS.  2 A and  2 C , two second directors  166   b  are included in one second antenna  160   b ; however, the disclosure is not limited. In an alternative embodiment, the number of the second directors  166   b  may be less than two or more than two. 
     In one embodiment, the first metallization layer  114   a  and the second metallization layer  114   b  of the redistribution structure  110  presented immediately below the first directors  166   a  and/or second directors  166   b  may be optionally omitted to further prevent the first antennas  160   a  and/or the second antenna  160   b  being affected by the redistribution structure  110 . The disclosure is not limited thereto. 
     In some embodiments, the first antennas  160   a  and the second antennas  160   b  are configured as Yagi-Uda antennas. In some embodiments, the first antennas  160   a  and the second antennas  160   b  may be end-fire antennas or polarized end-fire antennas (such as horizontal polarized end-fire antennas as shown in  FIG.  2 C  or vertical polarized end-fire antennas (not shown)), the disclosure is not limited thereto. In one embodiment, the first antennas  160   a  and the second antennas  160   b  may have the same structure or different structures. Due to the configuration of the first antennas  160   a  and the second antennas  160   b  as shown in  FIG.  2 A  to  FIG.  2 C , a coverage range of the electromagnetic waves generated from the package structure  20  is further increased, and thus the efficiency of the antenna application of the package structure  20  is enhanced. 
     Referring to  FIG.  2 C , in some embodiments, the first TIV wall  172  is encapsulated in the first portion  142  of the insulating encapsulation  140 . In certain embodiments, the first TIV wall  172  is located between the redistribution structure  110  and the first isolation layer  152 . The first TIV wall  172  is connected to the first reflector  162   a  of one of the first antennas  160   a  encapsulated in the first portion  142  of the insulating encapsulation  140  and the second reflector  162   b  of one of the second antennas  160   b  encapsulated in the first portion  142  of the insulating encapsulation  140 . In some embodiments, the first TIV wall  172  is connected to the first metallization layer  114   a  of the redistribution structure  110  as shown in  FIG.  2 C . In some embodiments, the first antennas  160   a  encapsulated in the first portion  142  of the insulating encapsulation  140  and the second antennas  160   b  encapsulated in the first portion  142  of the insulating encapsulation  140  are separated by the first TIV wall  172 . Due to the presence of the first TIV wall  172 , the interference between the first antennas  160   a  encapsulated in the first portion  142  of the insulating encapsulation  140  and the second antennas  160   b  encapsulated in the first portion  142  of the insulating encapsulation  140  is suppressed. 
     In some embodiments, the second TIV wall  174  is encapsulated in the second portion  144  of the insulating encapsulation  140 . In certain embodiments, the second TIV wall  174  is located on the first isolation layer  152 . The second TIV wall  174  is connected to the first reflector  162   a  of one of the first antennas  160   a  encapsulated in the second portion  144  of the insulating encapsulation  140  and the second reflector  162   b  of one of the second antennas  160   b  encapsulated in the second portion  144  of the insulating encapsulation  140 . In some embodiments, the second TIV wall  174  is connected to the first isolation layer  152  as shown in  FIG.  2 B . In one embodiment, the first antennas  160   a  encapsulated in the second portion  144  of the insulating encapsulation  140  and the second antennas  160   b  encapsulated in the second portion  144  of the insulating encapsulation  140  are separated by the second TIV wall  174 . Due to the presence of the second TIV wall  174 , the interference between the first antennas  160   a  encapsulated in the second portion  144  of the insulating encapsulation  140  and the second antennas  160   b  encapsulated in the second portion  144  of the insulating encapsulation  140  is suppressed. 
       FIG.  3 A  is a schematic three-dimensional side-view diagram of a package structure according to some exemplary embodiments of the present disclosure.  FIG.  3 B  is a schematic cross-sectional view of the package structure depicted in  FIG.  3 A .  FIG.  3 C  is a schematic explosive view illustrating the package structure depicted in  FIG.  3 A .  FIG.  3 B  is the schematic cross sectional view taken along a section line C-C′ depicted in  FIG.  3 C . Some components shown in  FIG.  3 B  is omitted in  FIG.  3 A  and  FIG.  3 C  to show concise, schematic explosive views. The embodiments are intended to provide further explanations but are not used to limit the scope of the present disclosure. In  FIG.  3 A  to  FIG.  3 C , only one die, two first antennas, three second antennas are presented for illustrative purposes; however, it should be noted that one or more dies, one or more first antennas, and one or more second antennas may be provided. 
     Referring to  FIG.  1 A  to  FIG.  1 C  and  FIG.  3 A  to  FIG.  3 C  together, the package structure  10  depicted in  FIG.  1 A  to  FIG.  1 C  and the package structure  30  depicted in  FIG.  3 A  to  FIG.  3 C  has elements similar to or substantially the same, the elements depicted in  FIG.  3 A  to  FIG.  3 C  similar to or substantially the same as the elements described above in  FIG.  1 A  to  FIG.  1 C  will use the same reference numbers, and certain details or descriptions of the same elements will not be repeated herein, for simplicity. 
     Referring to  FIG.  3 A ,  FIG.  3 B  and  FIG.  3 C , in some embodiments, a package structure  30  includes a redistribution structure  110 , at least one TIV  120 , a semiconductor die  130 , an insulating encapsulation  140 , a first isolation layer  152 , a second isolation layer  154 , first antennas including a first antenna component  160   a  and a second antenna component  160   b , and second antennas including a third antenna component  160   c , a fourth antenna component  160   d  and a fifth antenna component  160   e , and conductive elements  180 . 
     Referring to  FIG.  3 A  and  FIG.  3 B , in some embodiments, the insulating encapsulation  140  includes a first portion  142 , a second portion  144 , and a third portion  146 , where the second portion  144  is sandwiched between the first portion  142  and the third portion  146 . In some embodiments, the semiconductor die  130  is encapsulated in the first portion  142  of the insulating encapsulation  140 , the first antenna component  160   a  and the second antenna component  160   b  are encapsulated in the third portion  146  of the insulating encapsulation  140 , and the third antenna component  160   c , the fourth antenna component  160   d  and the fifth antenna component  160   e  are encapsulated in the second portion  144  of the insulation encapsulation  140 . 
     Referring to  FIG.  3 B , in some embodiments, the semiconductor die  130  includes an active surface  130   a , a plurality of pads  130   b  distributed on the active surface  130   a , a passivation layer  130   c  covering the active surface  130   a  and a portion of the pad  130   b , a plurality of conductive pillars  130   d  connecting to the pads  130   b , a dielectric layer  130   e , and the backside surface  130   f  opposite to the active surface  130   a . The pads  130   b  are partially exposed by the passivation layer  130   c , the conductive pillars  130   d  are disposed on and electrically connected to the pads  130   b , and the dielectric layer  130   e  covers the passivation layer  130   c  and exposes the conductive pillars  130   d . In an alternative embodiment, the semiconductor die  130  may include the pads  130   b  distributed on the active surface  130   a , the passivation layer  130   c  covering the active surface  130   a  and a portion of the pad  130   b , the backside surface  130   f  opposite to the active surface  130   a , where the conductive pillars  130   d  and the dielectric layer  130   e  may be omitted. As shown in  FIG.  3 A  to  FIG.  3 C , only one semiconductor die is presented for illustrative purposes, however, it should be noted that one or more semiconductor dies may be provided. 
     Referring to  FIG.  3 B , in some embodiments, the first isolation layer  152  and the redistribution structure  110  are located at two opposite sides of the semiconductor die  130 . The first isolation layer  152  is sandwiched between the first portion  142  of the insulating encapsulation  140  and the second portion  144  of the insulating encapsulation  140 . In some embodiments, the first isolation layer  152  is located between a first polymer dielectric layer PD1 and a second polymer dielectric layer PD2. The first polymer dielectric layer PD1, the first isolation layer  152  and the second polymer dielectric layer PD2 are sequentially stacked one over another, and are located between the first portion  142  of the insulating encapsulation  140  and the second portion  144  of the insulating encapsulation  140 . In some embodiments, the first polymer dielectric layer PD1 is located between the first isolation layer  152  and the first portion  142  of the insulating encapsulation  140 , while the second polymer dielectric layer PD2 is located between the second portion  144  of the insulating encapsulation  140  and the first isolation layer  152 . The disclosure is not limited thereto, for example, in one embodiment, the first polymer dielectric layer PD1 may be optionally omitted. In an alternative embodiment, the second polymer dielectric layer PD2 may be optionally omitted. 
     In certain embodiments, a die attach film DA is provided between the backside surface  130   f  of the semiconductor die  130  and the first polymer dielectric layer PD1, as shown in  FIG.  3 B . In some embodiments, due to the die attach film DA provided between the semiconductor die  130  and the first polymer dielectric layer PD1, the semiconductor die  130  is stably adhered to the first polymer dielectric layer PD1. 
     Referring to  FIG.  3 B , in some embodiments, the redistribution structure  110  includes one or more metallization layers and one or more polymer-based dielectric layers. As seen in  FIG.  3 B , the redistribution structure  110  includes a first polymer dielectric material layer  112   a , a first metallization layer  114   a , a second polymer dielectric material layer  112   b , a second metallization layer  114   b , and a third polymer dielectric material layer  112   c . The first metallization layer  114   a  is sandwiched between the second polymer dielectric material layer  112   b  and the first polymer dielectric material layer  112   a , and the second metallization layer  114   b  is sandwiched between the third polymer dielectric material layer  112   c  and the second polymer dielectric material layer  112   b . In certain embodiments, a top surface of the first metallization layers  114   a  is exposed by the first polymer dielectric material layers  112   a , and a bottom surface of the second metallization layers  114   b  is exposed by the third polymer dielectric material layers  112   c . It should be noted that the redistribution structure  110  is not limited to include three polymer dielectric material layers and/or two metallization layers, i.e., the number of dielectric layer(s) and/or metallization layer(s) is not limited to what is disclosed herein according to the present disclosure. 
     In one embodiment, the exposed top surface of the first metallization layer  114   a  is connected to the conductive pillars  130   d  located on the active surface  130   a  of the semiconductor die  130  so as to electrically connect the semiconductor die  130  to the redistribution structure  110 , and the exposed bottom surface of the second metallization layer  114   b  is connected to the conductive elements  180 . In an alternative embodiment, the exposed bottom surface of the second metallization layer  114   b  is connected to the conductive elements and semiconductor elements  190 . As shown in  3 B, the redistribution structure  110  is located between the semiconductor die  130  and the conductive elements  180 , and between the semiconductor die  130  and the semiconductor elements  190 . 
     In certain embodiments, a plurality of under-ball metallurgy (UBM) patterns u1, u2 is formed on the exposed bottom surface of the second metallization layers  114   b  of the redistribution structure  110  for electrically connecting with the conductive elements  180  and/or the semiconductor elements  190 , respectively. As shown in  FIG.  3 B , for example, the under-ball metallurgy patterns u1 are located between the conductive elements  180  and the exposed bottom surface of the second metallization layers  114   b , and the under-ball metallurgy patterns u2 are located between the semiconductor elements  190  and the exposed bottom surface of the second metallization layers  114   b , however, the disclosure is not limited thereto. Due to the under-ball metallurgy patterns u1 and u2 are formed on the exposed bottom surface of the second metallization layers  114   b  of the redistribution structure  110 , the later-formed conductive elements  180  and/or the semiconductor elements  190  can be accurately located on the under-ball metallurgy patterns u1 and u2 with better fixation, and the ball drop yield and reliability of the package structure  30  are improved. 
     Referring to  FIG.  3 B , in some embodiments, the second isolation layer  154  is sandwiched between the third portion  146  of the insulating encapsulation  140  and the second portion  144  of the insulating encapsulation  140 . In some embodiments, the second isolation layer  154  is located between a third polymer dielectric layer PD3 and a fourth polymer dielectric layer PD4. The third polymer dielectric layer PD3, the second isolation layer  154  and the fourth polymer dielectric layer PD4 are sequentially stacked one over another, and are located between the third portion  146  of the insulating encapsulation  140  and the second portion  144  of the insulating encapsulation  140 . In some embodiments, the third polymer dielectric layer PD3 is located between the second isolation layer  154  and the second portion  144  of the insulating encapsulation  140 , while the fourth polymer dielectric layer PD4 is located between the third portion  146  of the insulating encapsulation  140  and the second isolation layer  154 . The disclosure is not limited thereto, for example, in one embodiment, the third polymer dielectric layer PD3 may be optionally omitted. In an alternative embodiment, the fourth polymer dielectric layer PD4 may be optionally omitted. The first isolation layer  152  and the second isolation layer  154  function as shielding layers of an electric signal or radiating wave to prevent the semiconductor die  130  being affected by either the first antennas or the second antennas and/or to prevent the first antennas or the second antennas being affected by each other or by the semiconductor die  130 . Furthermore, in some embodiments, the first isolation layer  152  and the second isolation layer  154  may include isolation layers having patterns, where portions of each of the first isolation layer  152  and the second isolation layer  154  are electrically connected to the semiconductor die  130  and serve as signal patterns, and other portions of each of the first isolation layer  152  and the second isolation layer  154  are electrically isolated to the semiconductor die  130  and serve as antenna ground. 
     Referring to  FIG.  3 B , in some embodiments, the at least one TIV  120  includes a first TIV  122  and a second TIV  124 . In some embodiments, the first TIV  122  and the second TIV  124  are through integrated fan-out (InFO) vias. For simplification, only one first TIV  122  and one second TIV  124  are presented for illustrative purposes, however, it should be noted that more than two first TIV and/or second TIV may be formed; the disclosure is not limited thereto. The numbers of the first TIV  122  and the second TIV  124  can be selected based on the demand. 
     In some embodiments, the first TIV  122  is encapsulated in the first portion  142  of the insulating encapsulation  140 . In some embodiments, a first end  122   a  of the first TIV  122  is connected to the exposed top surface of the first metallization layer  114   a  of the redistribution structure  110  so as to electrically connect to the semiconductor die  130 , and a second end  122   b  of the first TIV  122  is connected to the first isolation layer  152  exposed by an opening O 1  of the first polymer dielectric layer PD1, where the first end  122   a  is opposite to the second end  122   b . In some embodiments, the second TIV  124  is encapsulated in the second portion  144  of the insulating encapsulation  140 . In some embodiments, as shown in  FIG.  3 B , a first end  124   a  of the second TIV  124  is connected to the first isolation layer  152  exposed by an opening O 2  of the second polymer dielectric layer PD2 so as to electrically connect to the first isolation layer  152 , and a second end  124   b  of the second TIV  124  is connected to the second isolation layer  154  exposed by an opening O 3  of the third polymer dielectric layer PD3, where the first end  124   a  is opposite to the second end  124   b . In certain embodiments, the first TIV  122  and the second TIV  124  are electrically connected to the redistribution structure  110 . As shown in  FIG.  3 B , for example, the first TIV  122  is electrically connected to the semiconductor die  130  through the redistribution structure  110 , and the second TIV  124  is electrically connected to the semiconductor die  130  through the first isolation layer  152 , the first TIV  122 , and the redistribution structure  110 . 
     Referring to  FIG.  3 C , in some embodiments, the first antennas includes one first antenna component  160   a  and one second antenna component  160   b , and the second antennas include one third antenna component  160   c , one fourth antenna component  160   d , and one fifth antenna component  160   e . The numbers of the first, second, third, fourth and fifth antenna components  160   a - 160   e  are not limited to one, the numbers of the first, second, third, fourth and fifth antenna components  160   a - 160   e  may be more than one, the disclosure is not limited thereto. 
     In some embodiments, the first antenna component  160   a  includes a first reflector  162   a , a pair of first drivers  164   a , and first directors  166   a . In some embodiments, the first reflector  162   a  and the first drivers  164   a  of the first antenna component  160   a  are respectively connected to the second isolation layer  154  exposed by an opening O 4  and an opening O 5  of the fourth polymer dielectric layer PD4 so as to electrically connect to the second isolation layer  154 . In other words, the first antenna component  160   a  is electrically connected to the semiconductor die  130  through the second isolation layer  154 , the second TIV  124 , the first isolation layer  152 , the first TIV  122 , and the redistribution structure  110 . In some embodiments, the first antenna component  160   a  generates an electromagnetic wave (such as microwaves) propagating along a first direction X, where the first reflector  162   a , the first drivers  164   a , and the first directors  166   a  are sequentially arranged along the first direction X and are separated apart from each other. The first drivers  164   a  are arranged in parallel along a second direction Y and are located between the first reflector  162   a  and the first directors  166   a  along the first direction X. In other words, as the first reflector  162   a  and the first drivers  164   a  are connected to the second isolation layer  154 , and the first drivers  164   a  are located between the first reflector  162   a  and the first directors  166   a  along the first direction X (which is a propagating direction of the electromagnetic wave generated by the first antenna component  160   a ), where the first reflectors  162   a  and the first drivers  164   a  are overlapped with the second isolation layer  154  along the direction Z. In other words, the first reflectors  162   a  and the first drivers  164   a  stand on the second isolation layer  154 , for example. In some embodiments, as shown in  FIG.  3 C , two first directors  166   a  are included in one first antenna component  160   a ; however, the disclosure is not limited. In an alternative embodiment, the number of the first directors  166   a  may be less than two or more than two. 
     In some embodiments, the second antenna component  160   b  includes a second reflector  162   b , a pair of second drivers  164   b , and second directors  166   b . In some embodiments, the second reflector  162   b  and the second drivers  164   b  of the second antenna component  160   b  are connected to the second isolation layer  154  exposed by an opening (not shown) of the fourth polymer dielectric layer PD4 so as to electrically connect to the second isolation layer  154 . In other words, the second antennas  160   b  are electrically connected to the semiconductor die  130  through the second isolation layer  154 , the second TIV  124 , the first isolation layer  152 , the first TIV  122 , and the redistribution structure  110 . In some embodiments, the second antenna component  160   b  generates an electromagnetic wave (such as microwaves) propagating along the second direction Y, where the second reflector  162   b , the second drivers  164   b , and the second directors  166   b  are sequentially arranged along the second direction Y and are separated apart from each other. The second drivers  164   b  are arranged in parallel along the first direction X and are located between the second reflector  162   b  and the second directors  166   b  along the second direction Y. In other words, the second reflector  162   b  and the second drivers  164   b  are connected to the second isolation layer  154 , and the second drivers  164   b  are located between the second reflector  162   b  and the second directors  166   b  along the second direction Y (which is a propagating direction of the electromagnetic wave generated by the second antenna component  160   b ), where the second reflector  162   b  and the second drivers  164   b  are overlapped with the second isolation layer  154  along the direction Z. In other words, the second reflector  162   b  and the second drivers  164   b  stand on the second isolation layer  154 , for example. In some embodiments, as shown in  FIG.  3 C , two second directors  166   b  are included in one second antenna component  160   b ; however, the disclosure is not limited. In an alternative embodiment, the number of the second directors  166   b  may be less than two or more than two. 
     In some embodiments, the third antenna component  160   c  includes a third reflector  162   c , a pair of third drivers  164   c , and third directors  166   c . In some embodiments, the third reflector  162   c  and the third drivers  164   c  of the third antenna component  160   c  are respectively connected to the first isolation layer  152  exposed by openings (not shown) of the second polymer dielectric layer PD2 so as to electrically connect to the first isolation layer  152 . In other words, the third antenna component  160   c  are electrically connected to the semiconductor die  130  through the first isolation layer  152 , the first TIV  122 , and the redistribution structure  110 . In some embodiments, the third antenna component  160   c  generates an electromagnetic wave (such as microwaves) propagating along the third direction U, where the third reflector  162   c , the third drivers  164   c , and the third directors  166   c  are sequentially arranged along the third direction U and are separated apart from each other. The third drivers  164   c  are arranged in parallel along a direction perpendicular to the third direction U, and are located between the third reflector  162   c  and the third directors  166   c  along the third direction U. In other words, the third reflector  162   c  and the third drivers  164   c  are connected to the first isolation layer  152 , and the third drivers  164   c  are located between the third reflector  162   c  and the third directors  166   c  along the third direction U (which is a propagating direction of the electromagnetic wave generated by the third antenna component  160   c ), where the third reflector  162   c  and the third drivers  164   c  are overlapped with the first isolation layer  152  along the direction Z. In other words, the third reflector  162   c  and the third drivers  164   c  stand on the first isolation layer  152 , for example. In some embodiments, as shown in  FIG.  3 C , two third directors  166   c  are included in one third antenna component  160   c ; however, the disclosure is not limited. In an alternative embodiment, the number of the third directors  166   c  may be less than two or more than two. 
     In some embodiments, the fourth antenna component  160   d  includes a fourth reflector  162   d , a pair of fourth drivers  164   d , and fourth directors  166   d . In some embodiments, the fourth reflector  162   d  and the fourth drivers  164   d  of the fourth antenna component  160   d  are respectively connected to the first isolation layer  152  exposed by openings (not shown) of the second polymer dielectric layer PD2 so as to electrically connect to the first isolation layer  152 . In other words, the fourth antenna component  160   d  are electrically connected to the semiconductor die  130  through the first isolation layer  152 , the first TIV  122 , and the redistribution structure  110 . In some embodiments, the fourth antenna component  160   d  generates an electromagnetic wave (such as microwaves) propagating along the fourth direction V, where the fourth reflector  162   d , the fourth drivers  164   d , and the fourth directors  166   d  are sequentially arranged along the fourth direction V and are separated apart from each other. The fourth drivers  164   d  are arranged in parallel along a direction perpendicular to the fourth direction V, and are located between the fourth reflector  162   d  and the fourth directors  166   d  along the fourth direction V. In other words, the fourth reflector  162   d  and the fourth drivers  164   d  are connected to the first isolation layer  152 , and the fourth drivers  164   d  are located between the fourth reflector  162   d  and the fourth directors  166   d  along the fourth direction V (which is a propagating direction of the electromagnetic wave generated by the fourth antenna component  160   d ), where the fourth reflector  162   d  and the fourth drivers  164   d  are overlapped with the first isolation layer  152  along the direction Z. In other words, the fourth reflector  162   d  and the fourth drivers  164   d  stand on the first isolation layer  152 , for example. In some embodiments, as shown in  FIG.  3 C , two fourth directors  166   d  are included in one fourth antenna component  160   d ; however, the disclosure is not limited. In an alternative embodiment, the number of the fourth directors  166   d  may be less than two or more than two. 
     In some embodiments, the fifth antenna component  160   e  includes a fifth reflector  162   e , a pair of fifth drivers  164   e , and fifth directors  166   e . In some embodiments, the fifth reflector  162   e  and the fifth drivers  164   e  of the fifth antenna component  160   e  are respectively connected to the first isolation layer  152  exposed by an opening O 6  and an openings O 7  of the second polymer dielectric layer PD2 so as to electrically connect to the first isolation layer  152 . In other words, the fifth antenna component  160   e  are electrically connected to the semiconductor die  130  through the first isolation layer  152 , the first TIV  122 , and the redistribution structure  110 . In some embodiments, the fifth antenna component  160   e  generates an electromagnetic wave (such as microwaves) propagating along the fifth direction W, where the fifth reflector  162   e , the fifth drivers  164   e , and the fifth directors  166   e  are sequentially arranged along the fifth direction W and are separated apart from each other. The fifth drivers  164   e  are arranged in parallel along a direction perpendicular to the fifth direction W, and are located between the fifth reflector  162   e  and the fifth directors  166   e  along the fifth direction W. In other words, the fifth reflector  162   e  and the fifth drivers  164   e  are connected to the first isolation layer  152 , and the fifth drivers  164   e  are located between the fifth reflector  162   e  and the fifth directors  166   e  along the fifth direction W (which is a propagating direction of the electromagnetic wave generated by the fifth antenna component  160   e ), where the fifth reflector  162   e  and the fifth drivers  164   e  are overlapped with the first isolation layer  152  along the direction Z. In other words, the fifth reflector  162   e  and the fifth drivers  164   e  stand on the first isolation layer  152 , for example. In some embodiments, as shown in  FIG.  3 C , two fifth directors  166   e  are included in one fifth antenna component  160   e ; however, the disclosure is not limited. In an alternative embodiment, the number of the fifth directors  166   e  may be less than two or more than two. 
     In some embodiments, as shown in  FIGS.  3 A and  3 C , the third direction U, the fourth direction V, and the fifth direction W are different from the first direction X, the direction X′ opposite to the first direction X, the second direction Y, and the direction Y′ opposite to the second direction Y. In some embodiments, the first antennas (e.g. the first antenna component  160   a  and the second antenna component  160   b ) and the second antennas (e.g. the third antenna component  160   c , the fourth antenna component  160   d , and the fifth antenna component  160   e ) are configured as Yagi-Uda antennas. In some embodiments, the first antennas (e.g. the first antenna component  160   a  and the second antenna component  160   b ) and the second antennas (e.g. the third antenna component  160   c , the fourth antenna component  160   d , and the fifth antenna component  160   e ) may be end-fire antennas or polarized end-fire antennas (such as horizontal polarized end-fire antennas as shown in  FIG.  3 C  or vertical polarized end-fire antennas (not shown)), the disclosure is not limited thereto. In one embodiment, the first antennas (e.g. the first antenna component  160   a  and the second antenna component  160   b ) and the second antennas (e.g. the third antenna component  160   c , the fourth antenna component  160   d , and the fifth antenna component  160   e ) may be the same or different. Owing to the configuration of the first antenna component  160   a , the second antenna component  160   b , the third antenna component  160   c , the fourth antenna component  160   d  and the fifth antenna component  160   e , a coverage range of the electromagnetic waves generated from the package structure  30  is further increased, and thus the efficiency of the antenna application of the package structure  30  is enhanced. 
       FIG.  4 A  is a schematic three-dimensional side-view diagram of a package structure according to some exemplary embodiments of the present disclosure.  FIG.  4 B  is a schematic cross-sectional view of the package structure depicted in  FIG.  4 A .  FIG.  4 C  is a schematic explosive view illustrating the package structure depicted in  FIG.  4 A .  FIG.  4 B  is the schematic cross sectional view taken along a section line D-D′ depicted in  FIG.  4 C . Some components shown in  FIG.  4 B  is omitted in  FIG.  4 A  and  FIG.  4 C  to show concise, schematic explosive views. The embodiments are intended to provide further explanations but are not used to limit the scope of the present disclosure. In  FIG.  4 A  to  FIG.  4 C , only one die, four first antennas and four second antennas are presented for illustrative purposes; however, it should be noted that one or more dies, one or more first antennas, and one or more second antennas may be provided. 
     Referring to  FIG.  1 A  to  FIG.  1 C  and  FIG.  4 A  to  FIG.  4 C  together, the package structure  10  depicted in  FIG.  1 A  to  FIG.  1 C  and the package structure  40  depicted in  FIG.  4 A  to  FIG.  4 C  has elements similar to or substantially the same, the elements depicted in  FIG.  4 A  to  FIG.  4 C  similar to or substantially the same as the elements described above in  FIG.  1 A  to  FIG.  1 C  will use the same reference numbers, and certain details or descriptions of the same elements will not be repeated herein, for simplicity. 
     Referring to  FIG.  4 A ,  FIG.  4 B  and  FIG.  4 C , in some embodiments, a package structure  40  includes a redistribution structure  100 , a redistribution structure  110 , at least one TIV  120 , a semiconductor die  130 , an insulating encapsulation  140 , first antennas  160   a  including a first group  160   a   1  and a second group  160   a   2 , second antennas  160   b  including a first group  160   b   1  and a second group  160   b   2 , and conductive elements  180 . 
     Referring to  FIG.  4 A  and  FIG.  4 B , in some embodiments, the semiconductor die  130 , the first group  160   a   1  of the first antennas  160   a  and the first group  160   b   1  of the second antennas  160   b  are encapsulated in the insulating encapsulation  140 , and the second group  160   a   2  of the first antennas  160   a  and the second group  160   b   2  of the second antennas  160   b  are included in the redistribution structure  100 . 
     Referring to  FIG.  4 B , in some embodiments, the semiconductor die  130  includes an active surface  130   a , a plurality of pads  130   b  distributed on the active surface  130   a , a passivation layer  130   c  covering the active surface  130   a  and a portion of the pad  130   b , a plurality of conductive pillars  130   d  connecting to the pads  130   b , a dielectric layer  130   e , and the backside surface  130   f  opposite to the active surface  130   a . The pads  130   b  are partially exposed by the passivation layer  130   c , the conductive pillars  130   d  are disposed on and electrically connected to the pads  130   b , and the dielectric layer  130   e  covers the passivation layer  130   c  and exposes the conductive pillars  130   d . In an alternative embodiment, the semiconductor die  130  may include the pads  130   b  distributed on the active surface  130   a , the passivation layer  130   c  covering the active surface  130   a  and a portion of the pad  130   b , the backside surface  130   f  opposite to the active surface  130   a , where the conductive pillars  130   d  and the dielectric layer  130   e  may be omitted. As shown in  FIG.  4 A  to  FIG.  4 C , only one semiconductor die is presented for illustrative purposes, however, it should be noted that one or more semiconductor dies may be provided. 
     Referring to  FIG.  4 B , in some embodiments, the insulating encapsulation  140  is located between the redistribution structure  100  and the redistribution structure  110 . In other words, the redistribution structure  100  and the redistribution structure  110  are located at two opposite sides of the semiconductor die  130 . 
     In some embodiments, the redistribution structure  100  includes an isolation layer  152 , a first polymer dielectric layer PD1, a second polymer dielectric layer PD2, the second group  160   a   2  of the first antennas  160   a , and the second group  160   b   2  of the second antennas  160   b . In some embodiments, the isolation layer  152  is located between a first polymer dielectric layer PD1 and a second polymer dielectric layer PD2, e.g. the first polymer dielectric layer PD1, the isolation layer  152  and the second polymer dielectric layer PD2 are sequentially stacked one over another. In some embodiments, the second group  160   a   2  of the first antennas  160   a  and the second group  160   b   2  of the second antennas  160   b  is located between a first polymer dielectric layer PD1 and a second polymer dielectric layer PD2, e.g. the first polymer dielectric layer PD1, the second group  160   a   2  of the first antennas  160   a /the second group  160   b   2  of the second antennas  160   b  and the second polymer dielectric layer PD2 are sequentially stacked one over another. In some embodiments, the first polymer dielectric layer PD1 is located between the isolation layer  152  and the insulating encapsulation  140 . The disclosure is not limited thereto, for example, in one embodiment, the first polymer dielectric layer PD1 may be optionally omitted. In an alternative embodiment, the second polymer dielectric layer PD2 may be optionally omitted. The isolation layer  152  functions as a shielding layer of an electric signal or radiating wave to prevent the semiconductor die  130  being affected by either the first antennas  160   a  and/or the second antennas  160   b  and/or to prevent the first antennas  160   a  or the second antennas  160   b  being affected by each other or by the semiconductor die  130 . Furthermore, in some embodiments, the first isolation layer  152  may include an isolation layer having patterns, where portions of the first isolation layer  152  are electrically connected to the semiconductor die  130  and serve as signal patterns, and other portions of the first isolation layer  152  are electrically isolated to the semiconductor die  130  and serve as antenna ground. 
     In certain embodiments, a die attach film DA is provided between the backside surface  130   f  of the semiconductor die  130  and the first polymer dielectric layer PD1, as shown in  FIG.  4 B . In some embodiments, due to the die attach film DA provided between the semiconductor die  130  and the first polymer dielectric layer PD1, the semiconductor die  130  is stably adhered to the first polymer dielectric layer PD1. 
     Referring to  FIG.  4 B , in some embodiments, the redistribution structure  110  includes one or more metallization layers and one or more polymer-based dielectric layers. In some embodiments, the redistribution structure  110  includes a first polymer dielectric material layer  112   a , a first metallization layer  114   a , a second polymer dielectric material layer  112   b , a second metallization layer  114   b , and a third polymer dielectric material layer  112   c . The first metallization layer  114   a  is sandwiched between the second polymer dielectric material layer  112   b  and the first polymer dielectric material layer  112   a , and the second metallization layer  114   b  is sandwiched between the third polymer dielectric material layer  112   c  and the second polymer dielectric material layer  112   b . In certain embodiments, a top surface of the first metallization layers  114   a  is exposed by the first polymer dielectric material layers  112   a , and a bottom surface of the second metallization layers  114   b  is exposed by the third polymer dielectric material layers  112   c . It should be noted that the redistribution structure  110  is not limited to include three polymer dielectric material layers and/or two metallization layers, i.e., the number of dielectric_layer(s) and/or metallization layer(s) is not limited to what is disclosed herein according to the present disclosure. 
     In some embodiments, the exposed top surface of the first metallization layer  114   a  is connected to the conductive pillars  130   d  located on the active surface  130   a  of the semiconductor die  130  so as to electrically connect the semiconductor die  130  to the redistribution structure  110 , and the exposed bottom surface of the second metallization layer  114   b  is connected to the conductive elements  180 . In an alternative embodiment, the exposed bottom surface of the second metallization layer  114   b  is connected to the conductive elements  180  and the semiconductor elements  190 . As shown in  FIG.  4 B , the redistribution structure  110  is located between the semiconductor die  130  and the conductive elements  180 , and between the semiconductor die  130  and the semiconductor elements  190 . 
     In certain embodiments, a plurality of under-ball metallurgy (UBM) patterns u1, u2 is formed on the exposed bottom surface of the second metallization layers  114   b  of the redistribution structure  110  for electrically connecting with the conductive elements  180  and/or the semiconductor elements  190 , respectively. As shown in  FIG.  4 B , for example, the under-ball metallurgy patterns u1 are located between the conductive elements  180  and the exposed bottom surface of the second metallization layers  114   b , and the under-ball metallurgy patterns u2 are located between the semiconductor elements  190  and the exposed bottom surface of the second metallization layers  114   b , however, the disclosure is not limited thereto. Due to the under-ball metallurgy patterns u1 and u2 are formed on the exposed bottom surface of the second metallization layers  114   b  of the redistribution structure  110 , the later-formed conductive elements  180  and/or the semiconductor elements  190  can be accurately located on the under-ball metallurgy patterns u1 and u2 with better fixation, and the ball drop yield and reliability of the package structure  40  are improved. 
     Referring to  FIG.  4 B , in some embodiments, the at least one TIV  120  includes a first TIV  122 . In some embodiments, the first TIV  122  is a through integrated fan-out (InFO) via. For simplification, only one first TIV  122  is presented for illustrative purposes, however, it should be noted that more than two first TIV may be formed; the disclosure is not limited thereto. The number of the first TIV  122  can be selected based on the demand. 
     In some embodiments, the first TIV  122  is encapsulated in the insulating encapsulation  140 . In some embodiments, a first end  122   a  of the first TIV  122  is connected to the exposed top surface of the first metallization layer  114   a  of the redistribution structure  110  so as to electrically connect to the semiconductor die  130 , and a second end  122   b  of the first TIV  122  is connected to the isolation layer  152  of the redistribution structure  100  exposed by an opening O 1  of the first polymer dielectric layer PD1, where the first end  122   a  is opposite to the second end  122   b . As shown in  FIG.  4 B , for example, the first TIV  122  is electrically connected to the semiconductor die  130  through the redistribution structure  110 . In some embodiments, the isolation layer  152  of the redistribution structure  100  is electrically connected to the semiconductor die  130  through the first TIV  122  and the redistribution structure  110 . 
     Referring to  FIG.  4 C , in some embodiments, each of the first group  160   a   1  of the first antennas  160   a  encapsulated in the insulating encapsulation  140  includes a first reflector  162   a   1 , a pair of first drivers  164   a   1 , and first directors  166   a   1 . In some embodiments, the first reflector  162   a   1  and the first drivers  164   a   1  are connected to the exposed top surface of the first metallization layer  114   a  of the redistribution structure  110 . In other words, the first antennas  160   a  encapsulated in the insulating encapsulation  140  (e.g. the first group  160   a   1  of the first antennas  160   a ) are electrically connected to the semiconductor die  130  through the redistribution structure  110 . On the other hand, in some embodiments, each of the second group  160   a   2  of the first antennas  160   a  included in the redistribution structure  100  includes a first reflector  162   a   2 , a pair of first drivers  164   a   2 , and first directors  166   a   2 . In some embodiments, the first reflector  162   a   2  and the first drivers  164   a   2  are connected to the isolation layer  152 . In certain embodiments, the first reflector  162   a   2  is a part of the isolation layer  152 , and each of the first drivers  164   a   2  is in form of a L-shape (see  FIG.  4 C ). In other words, the first antennas  160   a  included in the redistribution structure  100  (e.g. the second group  160   a   2  of the first antennas  160   a ) are electrically connected to the semiconductor die  130  through the isolation layer  152 , the first TIV  122 , and the redistribution structure  110 . 
     In some embodiments, the first group  160   a   1  of the first antennas  160   a  encapsulated in the insulating encapsulation  140  generates an electromagnetic wave (such as microwaves) propagating along the first direction X. For the first group  160   a   1  of the first antennas  160   a  encapsulated in the insulating encapsulation  140 , the first reflector  162   a   1 , the first drivers  164   a   1 , and the first directors  166   a   1  are sequentially arranged along the first direction X and are separated apart from each other. The first drivers  164   a   1  are arranged in parallel along the direction Z, and are located between the first reflector  162   a   1  and the first directors  166   a   1  along the first direction X. In other words, for the first group  160   a   1  of the first antennas  160   a  encapsulated in the insulating encapsulation  140 , the first reflector  162   a   1  and the first drivers  164   a   1  are connected to the redistribution structure  110 , and the first drivers  164   a   1  are located between the first reflector  162   a   1  and the first directors  166   a   1  along the first direction X (which is a propagating direction of the electromagnetic wave generated by the first antennas  160   a  encapsulated in the insulating encapsulation  140 ), where the first reflector  162   a   1  and the first drivers  164   a   1  are overlapped with the redistribution structure  110  along the direction Z. In other words, the first reflector  162   a   1  and the first drivers  164   a   1  stand on the redistribution structure  110 , for example. 
     In some embodiments, the second group  160   a   2  of the first antennas  160   a  included in the redistribution structure  100  generates an electromagnetic wave (such as microwaves) propagating along the first direction X. For the second group  160   a   2  of the first antennas  160   a  included in the redistribution structure  100 , the first reflector  162   a   2 , the first drivers  164   a   2 , and the first directors  166   a   2  are sequentially arranged along the first direction X and are separated apart from each other. The first drivers  164   a   2  are arranged in parallel along the second direction Y, and are located between the first reflector  162   a   2  and the first directors  166   a   2  along the first direction X. In other words, for the second group  160   a   2  of the first antennas  160   a  included in the redistribution structure  100 , the first reflector  162   a   2  and the first drivers  164   a   2  are connected to the isolation layer  152 , and the first drivers  164   a   2  are located between the first reflector  162   a   2  and the first directors  166   a   2  along the first direction X (which is a propagating direction of the electromagnetic wave generated by the first antennas  160   a  included in the redistribution structure  100 ), where the first reflector  162   a   2  is a part of the isolation layer  152 . 
     In some embodiments, as shown in  FIG.  4 C , two first directors are included in each of the first antennas  160   a ; however, the disclosure is not limited. In an alternative embodiment, the number of the first directors may be less than two or more than two. In some embodiments, the first group  160   a   1  of the first antennas  160   a  includes vertical polarized antennas (where a maximum size of the first group  160   a   1  of the first antennas  160   a  is obtained at the direction Z), while the second group  160   a   2  of the first antennas  160   a  includes horizontal polarized antennas (where a maximum size of the second group  160   a   2  of the first antennas  160   a  is obtained at the second direction Y), see  FIG.  4 C . 
     In some embodiments, the first group  160   b   1  of the second antennas  160   b  encapsulated in the insulating encapsulation  140  generates an electromagnetic wave (such as microwaves) propagating along the second direction Y. For the first group  160   b   1  of the second antennas  160   b  encapsulated in the insulating encapsulation  140 , the second reflector  162   b   1 , the second drivers  164   b   1 , and the second directors  166   b   1  are sequentially arranged along the second direction Y and are separated apart from each other. The second drivers  164   b   1  are arranged in parallel along the direction Z, and are located between the second reflector  162   b   1  and the second directors  166   b   1  along the second direction Y. In other words, for the first group  160   b   1  of the second antennas  160   b  encapsulated in the insulating encapsulation  140 , the second reflector  162   b   1  and the second drivers  164   b   1  are connected to the redistribution structure  110 , and the second drivers  164   b   1  are located between the second reflector  162   b   1  and the second directors  166   b   1  along the second direction Y (which is a propagating direction of the electromagnetic wave generated by the second antennas  160   b  encapsulated in the insulating encapsulation  140 ), where the second reflector  162   b   1  and the second drivers  164   b   1  are overlapped with the redistribution structure  110  along the direction Z. In other words, the second reflector  162   b   1  and the second drivers  164   b   1  stand on the redistribution structure  110 , for example. 
     In some embodiments, the second group  160   b   2  of the second antennas  160   b  included in the redistribution structure  100  generates an electromagnetic wave (such as microwaves) propagating along the second direction Y. For the second group  160   b   2  of the second antennas  160   b  included in the redistribution structure  100 , the second reflector  162   b   2 , the second drivers  164   b   2 , and the second directors  166   b   2  are sequentially arranged along the second direction Y and are separated apart from each other. The second drivers  164   b   2  are arranged in parallel along the first direction X, and are located between the second reflector  162   b   2  and the second directors  166   b   2  along the second direction Y. In other words, for the second group  160   b   2  of the second antennas  160   b  included in the redistribution structure  100 , the second reflector  162   b   2  and the second drivers  164   b   2  is connected to the isolation layer  152 , and the second drivers  164   b   2  are located between the second reflector  162   b   2  and the second directors  166   b   2  along the second direction Y (which is a propagating direction of the electromagnetic wave generated by the second antennas  160   b  included in the redistribution structure  100 ), where the second reflector  162   b   2  is a part of the isolation layer  152 . 
     In one embodiment, the first metallization layer  114   a  and the second metallization layer  114   b  of the redistribution structure  110  presented immediately below the first directors  166   a  and/or second directors  166   b  may be optionally omitted to further prevent the first antennas  160   a  and/or the second antenna  160   b  being affected by the redistribution structure  110 . The disclosure is not limited thereto. 
     In some embodiments, as shown in  FIG.  4 C , two first directors are included in each of the second antennas  160   b ; however, the disclosure is not limited. In an alternative embodiment, the number of the first directors may be less than two or more than two. In some embodiments, the first group  160   b   1  of the second antennas  160   b  includes vertical polarized antennas (where a maximum size of the first group  160   b   1  of the second antennas  160   b  is obtained at the direction Z), while the second group  160   b   2  of the second antennas  160   b  includes horizontal polarized antennas (where a maximum size of the second group  160   b   2  of the second antennas  160   b  is obtained at the first direction X), see  FIG.  4 C . In some embodiments, the first antennas  160   a  and the second antennas  160   b  are configured as Yagi-Uda antennas. In certain embodiments, the first group  160   a   1  of the first antennas  160   a  is considered as vertical polarized Yagi-Uda antennas, and the second group  160   a   2  of the first antennas  160   a  is considered as horizontal polarized Yagi-Uda antennas. That is to say, in certain embodiments, as shown in  FIG.  4 C , the first group  160   b   1  of the second antennas  160   b  is considered as vertical polarized Yagi-Uda antennas, and the second group  160   b   2  of the second antennas  160   b  is considered as horizontal polarized Yagi-Uda antennas. Owing to the configuration of the first antennas  160   a  (including the first group  160   a   1  and the second group  160   a   2 ) and the second antennas  160   b  (including the first group  160   b   1  and the second group  160   b   2 ), a channel capacity of the electromagnetic waves generated from the package structure  40  is increased and the form factor of the package structure  40  is decreased, and thus the efficiency of the antenna application of the package structure  40  is enhanced. 
     In an alternative embodiment, the pair of the first drivers  164   a   1  of each of the first group  160   a   1  of the first antennas  160   a  encapsulated in the insulating encapsulation  140  may be replaced with a first driver and a dummy first driver (not shown). In certain embodiments, the first driver is connected to the redistribution structure  110  and has a similar dimensional size to the first directors  166   a   1 , and the dummy first driver is a part of the first metallization layer  114   a  or the second metallization layer  114   b  of the redistribution structure  110 , where the dummy first driver correspondingly has a symmetric mirror pattern of the first driver. In an alternative embodiment, in some embodiments, the pair of the second drivers  164   b   1  of each of the first group  160   b   1  of the second antennas  160   b  encapsulated in the insulating encapsulation  140  may be replaced with a second driver and a dummy second driver (not shown). In certain embodiments, the second driver is connected to the redistribution structure  110  and has a similar dimensional size to the second directors  166   b   1 , and the dummy second driver is a part of the first metallization layer  114   a  or the second metallization layer  114   b  of the redistribution structure  110 , where the dummy second driver correspondingly has a symmetric mirror pattern of the second driver. The disclosure is not limited thereto. 
       FIG.  5 A  is a schematic three-dimensional side-view diagram of a package structure according to some exemplary embodiments of the present disclosure.  FIG.  5 B  is a schematic cross-sectional view of the package structure depicted in  FIG.  5 A .  FIG.  5 C  is a schematic explosive view illustrating the package structure depicted in  FIG.  5 A .  FIG.  5 B  is the schematic cross sectional view taken along a section line E-E′ depicted in  FIG.  5 C . Some components shown in  FIG.  5 B  is omitted in  FIG.  5 A  and  FIG.  5 C  to show concise, schematic explosive views. The embodiments are intended to provide further explanations but are not used to limit the scope of the present disclosure. In  FIG.  5 A  to  FIG.  5 C , only one die, four first antennas and four second antennas are presented for illustrative purposes; however, it should be noted that one or more dies, one or more first antennas, and one or more second antennas may be provided. 
     Referring to  FIG.  4 A  to  FIG.  4 C  and  FIG.  5 A  to  FIG.  5 C  together, the package structure  40  depicted in  FIG.  4 A  to  FIG.  4 C  and the package structure  50  depicted in  FIG.  5 A  to  FIG.  5 C  is similar, the difference is that, the package structure  50  depicted in  FIG.  5 A  to  FIG.  5 C  further includes a redistribution structure  200  and a dielectric layer  210  located between the redistribution structure  200  and the redistribution structure  100 . The elements depicted in  FIG.  5 A  to  FIG.  5 C  similar to or substantially the same as the elements described above in  FIG.  4 A  to  FIG.  4 C  will use the same reference numbers, and certain details or descriptions of the same elements will not be repeated herein, for simplicity. 
     Referring to  FIG.  5 A  to  FIG.  5 C , in some embodiments, the redistribution structure  200  is located above the redistribution structure  100  and located on the dielectric layer  210 . In some embodiments, the dielectric layer  210  is located between the redistribution structure  200  and the redistribution structure  100 . In some embodiments, the redistribution structure  100  is located between the dielectric layer  210  and the insulating encapsulation  140  and between the dielectric layer  210  and the semiconductor die  130 . In some embodiments, the dielectric layer  210  may include a molding compound, such as plastic materials, epoxy resin, polyimide, polyethylene terephthalate (PET), polyvinyl chloride (PVC), polymethylmethacrylate (PMMA), polymer components doped with fillers including fiber, clay, ceramic, inorganic particles, or combination thereof, the disclosure is not limited thereto. 
     In some embodiments, the redistribution structure  200  includes antennas AP, a third polymer dielectric layer PD3 and a fourth polymer dielectric layer PD4, where the antennas AP are located between the third polymer dielectric layer PD3 and the fourth polymer dielectric layer PD4. In certain embodiments, the third polymer dielectric layer PD3 is located between the antennas AP and the dielectric layer  210 . In some embodiments, the isolation layer  152  is overlapped with the antennas AP, and the antennas AP are electrically coupled with the isolation layer  152 . The disclosure is not limited thereto, for example, in one embodiment, the third polymer dielectric layer PD3 may be optionally omitted. In an alternative embodiment, the fourth polymer dielectric layer PD4 may be optionally omitted. The isolation layer  152  overlapped with the antennas AP and electrically isolated from the first TIV  122  serves as a ground plate, and the isolation layer  152  connected to the first TIV  122  serves as a feed-line. In some embodiments, a part of the isolation layer  152  is referred as the ground plate of antennas AP, and another part of the isolation layer  152  is referred as the feed line of antennas AP. 
     In some embodiments, the material of the antennas AP includes aluminum, titanium, copper, nickel, tungsten, and/or alloys thereof. In certain embodiments, the antennas AP are arranged in form of a matrix, such as the N×N array or N×M arrays (N, M&gt;0, N may or may not be equal to M). In some embodiments, the antennas AP may include patch antennas. Owing to the configuration of the first antennas  160   a  (including the first group  160   a   1  and the second group  160   a   2 ), the second antennas  160   b  (including the first group  160   b   1  and the second group  160   b   2 ) and the antennas AP, a coverage range of the electromagnetic waves generated from the package structure  50  is further increased, and thus the efficiency of the antenna application of the package structure  50  is enhanced. As shown in  FIG.  5 A  and  FIG.  5 C , in some embodiments, the package structure  50  includes the antennas AP arranged in form of an array, such as a 2×2 array, however, the disclosure is not limited thereto. The size of the array for the antennas AP can be designated and selected based on the demand. 
     According to some embodiments, a package structure includes an insulating encapsulation, at least one semiconductor die, at least one first antenna and at least one second antenna. The insulating encapsulation includes a first portion, a second portion and a third portion, wherein the second portion is located between the first portion and the third portion. The at least one semiconductor die is encapsulated in the first portion of the insulating encapsulation. The at least one first antenna is electrically connected to the at least one semiconductor die and encapsulated in the third portion of the insulating encapsulation. The at least one second antenna is electrically connected to the at least one semiconductor die and encapsulated in the second portion of the insulating encapsulation. 
     According to some embodiments, a package structure includes an insulating encapsulation, at least one semiconductor die, first antennas, and second antennas. The insulating encapsulation includes a first portion and a second portion stacked on the first portion. The at least one semiconductor die is encapsulated in the first portion of the insulating encapsulation, and the second portion and the third portion are stacked on the at least one semiconductor die. The first antennas are electrically connected to the at least one semiconductor die, wherein a portion of the first antenna is encapsulated in the first portion of the insulating encapsulation, and an another portion of the first antenna is encapsulated in the second portion of the insulating encapsulation. The second antennas are electrically connected to the at least one semiconductor die, wherein a portion of the second antennas is encapsulated in the first portion of the insulating encapsulation, and an another portion of the second antenna is encapsulated in the second portion of the insulating encapsulation. 
     According to some embodiments, a package structure includes an insulating encapsulation, a first redistribution structure, at least one semiconductor die, first antennas, and second antennas. The first redistribution structure is located on the insulating encapsulation. The at least one semiconductor die is encapsulated in the insulating encapsulation and electrically connected to the first redistribution structure. The first antennas are electrically connected to the at least one semiconductor die, wherein a first group of the first antennas is encapsulated in the insulating encapsulation, and a second group of the first antennas is located in the first redistribution structure. The second antennas are electrically connected to the at least one semiconductor die, wherein a first group of the second antennas is encapsulated in the insulating encapsulation, and a second group of the second antennas is located in the first redistribution structure. 
     According to some embodiments, a package structure includes a first redistribution circuit structure, a semiconductor die, first antennas and second antennas. The semiconductor die is located on and electrically connected to the first redistribution circuit structure. The first antennas and the second antennas are located over the first redistribution circuit structure, and are electrically connected to the semiconductor die through the first redistribution circuit structure. A first group of the first antennas are located at a first position, a first group of the second antennas are located at a second position, and the first position is different from the second position in a stacking direction of the first redistribution circuit structure and the semiconductor die. 
     According to some embodiments, a package structure includes a semiconductor die, a first redistribution circuit structure, a second redistribution circuit structure, a plurality of first antennas, and a plurality of second antennas. The first redistribution circuit structure and the second redistribution circuit structure are electrically connected to the semiconductor die, wherein the semiconductor die are between the first redistribution circuit structure and the second redistribution circuit structure. The plurality of first antennas are electrically connected to the semiconductor die, wherein a first group of the first antennas is located aside of the semiconductor die and a second group of the first antennas is located on the semiconductor die. The plurality of second antennas are electrically connected to the semiconductor die, wherein a first group of the second antennas is located aside of the semiconductor die and a second group of the second antennas is located on the semiconductor die. 
     According to some embodiments, a package structure includes a redistribution circuit structure, a semiconductor die, and a plurality of antennas. The semiconductor die is located on and electrically connected to the redistribution circuit structure. The plurality of antennas are electrically connected to the semiconductor die and over the redistribution circuit structure, wherein the antennas are arranged into a first tier and a second tier stacked thereon. In a vertical projection on the redistribution circuit structure, a projection of the semiconductor die is aside of projections of the antennas. 
     The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.