Patent Publication Number: US-2023154892-A1

Title: Semiconductor package structure and method for forming the same

Description:
PRIORITY CLAIM AND CROSS-REFERENCE 
     The present application claims priority of U.S. Provisional Patent Application Ser. No. 63/280,276, filed on Nov. 17, 2021, the entirety of which is incorporated by reference herein. 
    
    
     BACKGROUND 
     Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic equipment. Semiconductor devices are fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers over a semiconductor substrate, and patterning the various material layers using lithography and etching processes to form circuit components and elements thereon. Many integrated circuits (ICs) are typically manufactured on a single semiconductor wafer, and individual dies on the wafer are singulated by sawing between the integrated circuits along a scribe line. The individual dies are typically packaged separately, in multi-chip modules, for example, or in other types of packaging. 
     A package (structure) not only provides protection for semiconductor devices from environmental contaminants, but also provides a connection interface for the semiconductor devices packaged therein. Smaller package structures, which take up less area or are lower in height, have been developed to package the semiconductor devices. 
     Although existing packaging structures and methods for fabricating package structure have generally been adequate for their intended purposes, they have not been entirely satisfactory in all respects. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. 
         FIG.  1 A  is a schematic view of a semiconductor package structure, in accordance with some embodiments of the present disclosure. 
         FIG.  1 B  is a top view illustrated along line A′-A′ in  FIG.  1 A , in accordance with some embodiments of the present disclosure. 
         FIG.  2 A  is a schematic view of a semiconductor package structure, in accordance with some embodiments of the present disclosure. 
         FIG.  2 B  is a schematic view of a semiconductor package structure, in accordance with some embodiments of the present disclosure. 
         FIG.  3 A  is a schematic view of a semiconductor package structure, in accordance with some embodiments of the present disclosure. 
         FIG.  3 B  is a schematic view of a semiconductor package structure, in accordance with some embodiments of the present disclosure. 
         FIG.  3 C  is a schematic view of a semiconductor package structure, in accordance with some embodiments of the present disclosure. 
         FIG.  4 A  is a schematic view of a semiconductor package structure, in accordance with some embodiments of the present disclosure. 
         FIG.  4 B  is a schematic view of a semiconductor package structure, in accordance with some embodiments of the present disclosure. 
         FIG.  5 A  to  FIG.  5 L  show a process flow of forming the semiconductor package structure, in accordance with some embodiments of the present disclosure. 
         FIG.  6 A  to  FIG.  6 K  show a process flow of forming the semiconductor package structure, in accordance with some embodiments of the present disclosure. 
         FIG.  7 A  is a schematic view of a semiconductor package structure, in accordance with some embodiments of the present disclosure. 
         FIG.  7 B  is a top view illustrated along line C′-C′ in  FIG.  7 A , in accordance with some embodiments of the present disclosure. 
         FIG.  7 C  is a schematic view of a semiconductor package structure, in accordance with some embodiments of the present disclosure. 
         FIG.  7 D  is a schematic view of a semiconductor package structure, in accordance with some embodiments of the present disclosure. 
         FIG.  8 A  is a schematic view of a semiconductor package structure, in accordance with some embodiments of the present disclosure. 
         FIG.  8 B  is a schematic view of a semiconductor package structure, in accordance with some embodiments of the present disclosure. 
         FIG.  8 C  is a schematic view of a semiconductor package structure, in accordance with some embodiments of the present disclosure. 
         FIG.  8 D  is a schematic view of a semiconductor package structure, in accordance with some embodiments of the present disclosure. 
         FIG.  9    is a schematic view of a semiconductor package structure, in accordance with some embodiments of the present disclosure. 
         FIG.  10    is a schematic view of a semiconductor package structure, in accordance with some embodiments of the present disclosure. 
         FIG.  11 A  to  FIG.  11 L  show a process flow of forming the semiconductor package structure, in accordance with some embodiments of the present disclosure. 
         FIG.  12 A  to  FIG.  12 K  show a process flow of forming the semiconductor package structure, in accordance with some embodiments of the present disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. 
     Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature&#39;s relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. 
     The term “substantially” in the description, such as in “substantially flat” or in “substantially coplanar”, etc., will be understood by the person skilled in the art. In some embodiments the adjective substantially may be removed. Where applicable, the term “substantially” may also include embodiments with “entirely”, “completely”, “all”, etc. Where applicable, the term “substantially” may also relate to 90% or higher, such as 95% or higher, especially 99% or higher, including 100%. Furthermore, terms such as “substantially parallel” or “substantially perpendicular” are to be interpreted as not to exclude insignificant deviation from the specified arrangement and may include for example deviations of up to 10°. The word “substantially” does not exclude “completely” e.g. a composition which is “substantially free” from Y may be completely free from Y. 
     Terms such as “about” in conjunction with a specific distance or size are to be interpreted so as not to exclude insignificant deviation from the specified distance or size and may include for example deviations of up to 10%. The term “about” in relation to a numerical value x may mean x ±5 or 10%. The terms “each” in the description are to be interpreted so as not to exclude variations among units and not to exclude an omission of a part of the units. 
     Embodiments will be described with respect to a specific context, namely a packaging technique with an interposer substrate or other active chip in a two and a half dimensional integrated circuit (2.5DIC) structure or a three dimensional IC (3DIC) structure. Embodiments discussed herein are to provide examples to enable making or using the subject matter of this disclosure, and a person having ordinary skill in the art will readily understand modifications that can be made while remaining within contemplated scopes of different embodiments. Although method embodiments may be discussed below as being performed in a particular order, other method embodiments contemplate steps that are performed in any logical order. 
     A semiconductor package structure and the method for forming the same are provided in accordance with various embodiments. Some variations of some embodiments are discussed. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements. In accordance with some embodiments of the present disclosure, a semiconductor package structure having an interposer substrate is provided. In some embodiments, a recess is formed on the interposer substrate, and a connecting element, such as a silicon bridge, is disposed in the recess. In some embodiments, the connecting element allows semiconductor devices in the semiconductor package structure connect each other with finer pitch electrical connection through high density silicon interconnects, thereby improves the electrical performance of die-to-die connections, and maintains the interposer substrate routability and bump density. In some embodiments, the connecting element enables vertical connection of the elements above and below the connecting element. 
     In some embodiments, an accommodating space is formed on the interposer substrate, and a connecting element is disposed on the accommodating space, such as enclosed in the accommodating space. Therefore, the connecting element is separated from an underfill layer in contact with semiconductor devices above the interposer substrate by the interposer substrate. In some embodiments, the connecting element allows the semiconductor devices in the semiconductor package structure connect each other, thereby improves the electrical performance of die-to-die connections, and maintains the interposer substrate routability and bump density. In some embodiments, the connecting element enables vertical connection of the elements above and below the connecting element. In some embodiments, the connecting element is sandwiched between two portions of the interposer substrate, one portion is above the connecting element, and another portion is below the connecting element, so the mechanical strength of the interposer substrate may be maintained. 
     FIG. lA is a schematic view of a semiconductor package structure  100 A, in accordance with some embodiments of the present disclosure. As shown in  FIG.  1 A , the semiconductor package structure  100 A mainly includes a carrier substrate  110 , an interposer substrate  120 , a connecting element  130 , a first semiconductor device  142 , a second semiconductor device  144 , an underfill layer  150 , a molding layer  160 , and an underfill layer  170 , in accordance with some embodiments of the present disclosure. 
     In some embodiments, the carrier substrate  110  is a semiconductor substrate. By way of example, the material of the carrier substrate  110  may include elementary semiconductor such as silicon or germanium; a compound semiconductor such as silicon germanium, silicon carbide, gallium arsenic, gallium phosphide, indium phosphide or indium arsenide; or combinations thereof. Alternatively, the carrier substrate  110  may be a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, or the like. In some other embodiments, the carrier substrate  110  is a printed circuit board (PCB), a ceramic substrate, or another suitable package substrate. The carrier substrate  110  may be a core or a core-less substrate, in accordance with some embodiments. 
     In some embodiments, the interposer substrate  120  is disposed on the carrier substrate  110 , such as connected to the carrier substrate  110  by conductive structures  180 . An underfill layer  170  is provided to surround and protect the conductive structures  180 , in accordance with some embodiments of the present disclosure. In some embodiments, the interposer substrate  120 , such as an organic interposer, includes a board  122  and conductive features  124 . The conductive features  124  may be made of or include copper, aluminum, cobalt, nickel, gold, silver, tungsten, one or more other suitable materials, or a combination thereof. The board  122  may be made of or include a polymer material, a ceramic material, a metal material, a semiconductor material, one or more other suitable materials, or a combination thereof. For example, the board  122  includes resin, prepreg, glass, and/or ceramic. In the embodiments that the board  122  includes organic materials, the coefficient of thermal expansion (CTE) mismatch issue between the board  122  and other elements may be mitigated, which reduces the stress between the elements. In cases where the board  122  is made of a metal material or a semiconductor material, dielectric layers may be formed between the board  122  and the conductive features  124  to prevent short circuiting. In some embodiments, the conductive features  124  include circuits with pitches between about 2 μm to about 20 μm. In some embodiments, the conductive features  124  include circuits with linewidths between about 1 μm to about 10 μm. 
     In some embodiments, the conductive structures  180  may include conductive pillars, solder bumps, one or more other suitable bonding structures, or a combination thereof. The conductive structures  180  are made of a solder material, such as Sn and Ag or another suitable conductive material (e.g., gold), in accordance with some embodiments. The conductive structures  180  are solder balls, in accordance with some embodiments. A reflow process (not shown) may be performed to make the metallurgical connections between the carrier substrate  110 , the conductive structures  180 , and the interposer substrate  120 , in accordance with some embodiments of the present disclosure. 
     In some embodiments, the underfill layer  170  is dispensed (e.g., by a dispenser (not shown)) into the space between the interposer substrate  120  and the carrier substrate  110  and the space between adjacent conductive structures  180 , and then cured (e.g., ultraviolet (UV) or thermally cured) to harden. The underfill layer  170  may be configured to provide a stronger mechanical connection and a heat bridge between the interposer substrate  120  and the carrier substrate  110 , to reduce cracking in the conductive structures  180  caused by thermal expansion mismatches between the interposer substrate  120  and the carrier substrate  110 , and to protect the joints from contaminants, thereby improving reliability of the fabricated semiconductor package structure  100 A. In some embodiments, the underfill layer  170  includes liquid epoxy, deformable gel, silicon rubber, or the like. 
     In cases where the board  122  is made of or includes a polymer material, the board  122  may further include fillers that are dispersed in the polymer material. The polymer material may be made of or include epoxy-based resin, polyimide-based resin, one or more other suitable polymer materials, or a combination thereof. The examples of the fillers may include fibers (such as silica fibers and/or carbon-containing fibers), particles (such as silica particles and/or carbon-containing particles), or a combination thereof. 
     In some embodiments, a recess is formed in the interposer substrate  120 , and the connecting element  130  is disposed in the recess of the interposer substrate  120 . In some embodiments, a portion of the interposer substrate  120  extends between the connecting element  130  and the carrier substrate  110 . In some embodiments, the first semiconductor device  142  and the second semiconductor device  144  are connected to the connecting element  130  through conductive structures  134 . Therefore, the first semiconductor device  142  is electrically connected to the second semiconductor device  144  through the connecting element  130 . The connecting element  130  may be a silicon bridge, which enables direct fine pitch electrical connection through high density silicon interconnects of the connecting element  130 , in accordance with some embodiments of the present disclosure. 
     In some embodiments, the first semiconductor device  142  or the second semiconductor device  144  may be a functional integrated circuit (IC) die such as a semiconductor die, an electronic die, a Micro-Electro Mechanical Systems (MEMS) die, or a combination thereof. The functional IC die may include one or more application processors, logic circuits, memory devices, power management integrated circuits, analog circuits, digital circuits, mixed signal circuits, one or more other suitable functional integrated circuits, or a combination thereof, depending on actual needs. In some alternative embodiments, the first semiconductor device  142  or the second semiconductor device  144  may be a package module that has one or more semiconductor dies and an interposer substrate carrying these semiconductor dies. These structures of the first semiconductor device  142  or the second semiconductor device  144  are well known in the art and therefore not described herein. The first semiconductor device  142  or the second semiconductor device  144  can be fabricated by various processes such as deposition, etching, implantation, photolithography, annealing, and/or other suitable processes. 
     In some embodiments, the connecting element  130  includes a passive device (such as a capacitor, a resistor, etc.), a transistor, a memory device, etc. disposed in a dielectric element  137  of the connecting element  130 . In some embodiments, conductive structures  132  may be disposed below the connecting element  130 , and disposed between the interposer substrate  120  and the connecting element  130 . In some embodiments, conductive features  136  and conductive features  138  may be provided in the dielectric element  137  of the connecting element  130 , such as embedded in the dielectric element  137 . In some embodiments, a portion of the conductive features  136  is exposed from the dielectric element  137 , such as in contact with the conductive structures  132  for electrical conduction. In some embodiments, the conductive features  136  may be through silicon vias (TSV) and vertically pass through the dielectric element  137  of the connecting element  130  to provide electrical connection in the vertical direction. In some embodiments, the material of the conductive features  136  may include metal, such as Cu, Al, W, or another suitable conductive material. In some embodiments, the dielectric element  137  includes dielectric materials, such as silicon or another suitable dielectric material. In some embodiments, the material of the conductive features  138  may include metal, such as Cu, Al, W, or another suitable conductive material. In some embodiments, the conductive features  138  include circuits with pitches between about 0.8 μm and about 2 μm. In some embodiments, the conductive features  138  include circuits with linewidths between about 0.4 μm and about 1 μm. 
     For example, the conductive features  136  may in contact with the conductive structures  132  below the connect element  30  and the conductive structures  134  above the connecting element  130 . Therefore, electrical signal may be transported vertically from the first semiconductor device  142  or the second semiconductor device  144  through the conductive structures  134  above the connecting element  130 , the conductive features  136  in the connecting element  130 , and the conductive structures  132  under the connecting element  130  to the interposer substrate  120 , in accordance with some embodiments of the present disclosure. As a result, electrical signal can be transmitted to the first semiconductor device  142  or the second semiconductor device  142  in a shorter path, in accordance with some embodiments of the present disclosure. 
     In some embodiments, the conductive features  138  may be a redistribution layer to connect the conductive features  136 , so that the first semiconductor device  142  may be electrically connected to the second semiconductor device  144  through the conductive features  136  and the conductive features  138 . Therefore, the signal transport speed of the semiconductor package structure  100 A may be increased by the connecting element  130 , in accordance with some embodiments of the present disclosure. Moreover, using the connecting element  130  for signal transmission reduces the number of required through silicon vias (TSVs), which reduces overall cost and preserves low resistance for high frequency signals, in accordance with some embodiments of the present disclosure. 
     In some embodiments, as shown in  FIG.  1 A , the interposer substrate  120  has a thickness T 1 , and the recess has a depth T 2 . In some embodiments, a ratio of the thickness T 2  of the interposer substrate  120  to the depth T 1  of the recess is between 1.2 and 2. In other words, a ratio of the thickness T 3  of the portion of the interposer substrate  120  under the connecting element  130  to the depth T 2  of the recess is between 1:1 and 1:5. Therefore, enough space is provided for the connecting element  130 , so that the connecting element  130  can provide better electrical connection for the first semiconductor device  142  and the second semiconductor device  144 , in accordance with some embodiments of the present disclosure. 
     Moreover, the conductive features  124  may be provided in the portion of the interposer substrate  120  under the connecting element  130  as well, so the routability of the interposer substrate  120  can be maintained, in accordance with some embodiments of the present disclosure. Moreover, more conductive structures  180  may be provided on the interposer substrate  120 , such as may be provided on the portion of the interposer substrate  120  under the recess, in accordance with some embodiments of the present disclosure. The interposer substrate  120  and the connecting element  130  have substantially coplanar top surfaces, in accordance with some embodiments of the present disclosure. In some embodiments, the connecting element  130  is thinner than the interposer substrate  120  to achieve miniaturization. 
     In some embodiments, the conductive structures  132  may include conductive pillars, solder bumps, one or more other suitable bonding structures, or a combination thereof. The conductive structures  132  are made of a solder material, such as Sn and Ag or another suitable conductive material (e.g., gold), in accordance with some embodiments. The conductive structures  132  are solder balls, in accordance with some embodiments. A reflow process (not shown) may be performed to make the metallurgical connections between the interposer substrate  120  and the connecting element  130 , in accordance with some embodiments of the present disclosure. 
     In some embodiments, the first semiconductor device  142  and the second semiconductor device  144  are bonded onto the conductive structures  134  and conductive structures  146 . The conductive structures  134  and the conductive structures  146  may include conductive pillars, solder bumps, one or more other suitable bonding structures, or a combination thereof, in accordance with some embodiments of the present disclosure. The conductive structures  134  and the conductive structures  146  are made of a solder material, such as Sn and Ag or another suitable conductive material (e.g., gold), in accordance with some embodiments of the present disclosure. The conductive structures  134  and the conductive structures  146  are solder balls, in accordance with some embodiments. A reflow process (not shown) may be performed to make the metallurgical connections between the interposer substrate  120 , the connecting element  130 , the first semiconductor device  142 , the second semiconductor device  144 , the conductive structures  134 , and the conductive structures  146 , in accordance with some embodiments of the present disclosure. 
     In some embodiments, an underfill layer  150  is dispensed (e.g., by a dispenser (not shown)) into the space between the interposer substrate  120 , the connecting element  130 , the first semiconductor device  142 , and the second semiconductor device  144 , and then cured (e.g., ultraviolet (UV) or thermally cured) to harden. The underfill layer  150  may be configured to provide a stronger mechanical connection and a heat bridge between the interposer substrate  120 , the connecting element  130 , the first semiconductor device  142 , and the second semiconductor device  144  to reduce cracking in the conductive structures  134  and the conductive structures  146  caused by thermal expansion mismatches between the interposer substrate  120 , the connecting element  130 , the first semiconductor device  142 , and the second semiconductor device  144 , and to protect the joints from contaminants, thereby improving reliability of the fabricated semiconductor package structure  100 A, in accordance with some embodiments of the present disclosure. In some embodiments, the underfill layer  150  includes liquid epoxy, deformable gel, silicon rubber, or the like. 
     In some embodiments, a molding layer  160  is provided to fill gaps between the first semiconductor device  142  and the second semiconductor device  144 , in accordance with some embodiments. The molding layer  160  in the gaps surrounds the first semiconductor device  142  and the second semiconductor device  144 , in accordance with some embodiments. The molding layer  160  may be configured to provide package stiffness, a protective or hermetic shielding, and/or provide a heat conductive path to prevent chip overheating, in accordance with some embodiments of the present disclosure. The molding layer  160  may be formed by a spin-on coating process, an injection molding process, or the like, in accordance with some embodiments of the present disclosure. 
     The molding layer  160  includes a polymer material, in accordance with some embodiments. The term “polymer” here can represent thermosetting polymers, thermoplastic polymers, or any mixtures thereof, in accordance with some embodiments. The polymer material can include, for example, plastic materials, epoxy resin, polyimide, polyethylene terephthalate (PET), polyvinyl chloride (PVC), polymethylmethacrylate (PMMA), polymer components doped with specific fillers including fiber, clay, ceramic, inorganic particles, or any combinations thereof. In other embodiments, the molding layer  160  can be made of epoxy resin, such as epoxy cresol novolac (ECN), biphenyl epoxy resin, multifunctional liquid epoxy resin, or any combinations thereof, in accordance with some embodiments. In still other embodiments, the molding layer  160  can be made of epoxy resin optionally including one or more fillers to provide the composition with any of a variety of desirable properties. Examples of fillers can be aluminum, titanium dioxide, carbon black, calcium carbonate, silica, or any combinations thereof, in accordance with some embodiments. A thermal process is performed on the molding layer  160  to cure the molding layer  160 , in accordance with some embodiments of the present disclosure. 
     In some embodiments, the connecting element  130  and the interposer substrate  120  are separated by the underfill layer  150 . For example,  FIG.  1 B  is a top view illustrated along line A′-A′ in  FIG.  1 A , in accordance with some embodiments of the present disclosure. In some embodiments, the connecting element  130  is surrounded by the interposer substrate  120 , and the underfill layer  150  fills the gap between the connecting element  130  and the interposer substrate  120 . In some embodiments, the conductive structures  134  overlap the connecting element  130 , and the conductive structures  146  overlap the interposer substrate  120 . In other words, the conductive structures  146  are separated from the connecting element  130  in the top view, in accordance with some embodiments of the present disclosure. 
     In some embodiments, the conductive structures  132  may be omitted. For example,  FIG.  2 A  is a schematic view of a semiconductor package structure  100 B, in accordance with some embodiments of the present disclosure. In  FIG.  2 A , the connecting element  130  is in contact with a bottom surface of the recess (e.g. see  FIG.  6 B ) of the interposer substrate  120 . In some embodiments, the connecting element  130  is not directly electrically connected to the interposer substrate  120  through the contact area between the interposer substrate  120  and the connecting element  130 . Therefore, the process steps and costs may be reduced. 
       FIG.  2 B  is a schematic view of a semiconductor package structure  100 C, in accordance with some embodiments of the present disclosure. In some embodiments, the connecting element  130  is separated from the interposer substrate  120 , and the underfill layer  150  fills the space between the interposer substrate  120  and the connecting element  130 . Since in the semiconductor package structure  100 C, no conductive structure is provided between the interposer substrate  120  and the connecting element  130  in the recess of the interposer substrate  120 , the process steps and costs may be reduced, in accordance with some embodiments of the present disclosure. 
       FIG.  3 A  is a schematic view of a semiconductor package structure  100 D, in accordance with some embodiments of the present disclosure. In the semiconductor package structure  100 D, the first semiconductor device  142  and the second semiconductor device  144  may be chip packages. For example, the first semiconductor device  142  includes a chip  142 A, conductive structures  142 B under the chip  142 A, and an underfill layer  142 C under the chip  142 A and surrounding the conductive structures  142 B, in accordance with some embodiments of the present disclosure. 
     The second semiconductor device  144  includes a chip  144 A, conductive structures  144 B under the chip  144 A, and an underfill layer  144 C under the chip  144 A and surrounding the conductive structures  144 B, in accordance with some embodiments of the present disclosure. A molding structure  145  is provided to continuously surround the first semiconductor device  142  and the second semiconductor device  144 , in accordance with some embodiments of the present disclosure. In some embodiments, a third semiconductor device  148  is provided in the semiconductor package structure  100 D. In some embodiments, the third semiconductor device  148  is connected to the interposer substrate  120 , and is surrounded by the underfill layer  150  and the molding layer  160 . In some embodiments, the chip  142 A, the chip  144 A, and the third semiconductor device  148  have different heights or functions. For example, the heights the conductive structures  142 B and conductive structures  144 B are adjustable for chips with different heights. 
       FIG.  3 B  is a schematic view of a semiconductor package structure  100 E, in accordance with some embodiments of the present disclosure. The semiconductor package structure  100 E is similar to the previous embodiment, and the difference is that the molding structures  145  surrounding the first semiconductor device  142  and the second semiconductor device  144  are separated from each other, in accordance with some embodiments of the present disclosure. In other words, a portion of the underfill layer  150  and a portion of the molding layer  160  extend between the molding structures  145 . 
       FIG.  3 C  is a schematic view of a semiconductor package structure  100 F, in accordance with some embodiments of the present disclosure. The semiconductor package structure  100 F is similar to the previous embodiment, and the difference is that an underfill  135  is provided between the connecting element  130 , the first semiconductor device  142 , and the second semiconductor device  144  to surround and protect the conductive structures  134 . In some embodiments, the underfill  135  and the underfill layer  150  are made from different material. Therefore, the conductive structures  134  are further protected from being damaged. 
     In accordance with some embodiments of the present disclosure,  FIG.  4 A  and  FIG.  4 B  are schematic views of a semiconductor package structure  100 G and a semiconductor package structure  100 H, respectively. In some embodiments, the connecting element  130  in the semiconductor package structure  100 G and the semiconductor package structure  100 H are in contact with the interposer substrate  120 , and the underfill  135  is provided in the semiconductor package structure  100 H to surround the conductive structures  134 . 
       FIG.  5 A  to  FIG.  5 L  show a process flow of forming the semiconductor package structure  100 A, in accordance with some embodiments of the present disclosure. In  FIG.  5 A , the interposer substrate  120  is provide on a first carrier  190 , in accordance with some embodiments of the present disclosure. In some embodiments, the interposer substrate includes a recess  126 . In some embodiments, conductive features  124  are disposed in the portion of the interposer substrate  120  under the recess  126 . In some embodiments, a die attach film (DAF) is provided between the first carrier  190  and the interposer substrate  120  to attach the first carrier  190  onto the interposer substrate  120 , in accordance with some embodiments of the present disclosure. 
     In  FIG.  5 B , conductive structures  132  are disposed in the recess  126  of the interposer substrate  120 , in accordance with some embodiments of the present disclosure. In some embodiments, the conductive structures  132  are electrically connected to the conductive features  124  in the portion of the interposer substrate  120  under the recess  126 . In  FIG.  5 C , the connecting element  130  is provided in the recess  126  and disposed on the conductive structures  132 , in accordance with some embodiments of the present disclosure. In some embodiments, the connecting element  130  protrudes from the recess  126 . In other words, the top surface of the connecting element  130  is higher than the top surface of the interposer substrate  120 . 
     In  FIG.  5 D , an underfill element  150 A is provided to fill the space in the recess  126 , such as the space between the connecting element  130  and the interposer substrate  120 . In some embodiments, the underfill element  150 A surrounds the conductive structures  132 . A molding compound  128  is provided to cover the interposer substrate  120 , the connecting element  130 , and the underfill element  150 A, in accordance with some embodiments of the present disclosure. In some embodiments, the underfill element  150 A and the molding compound  128  may include different materials, such as different kinds of epoxy with different compositions and additives. 
     The molding compound  128  includes a polymer material, in accordance with some embodiments. The term “polymer” here can represent thermosetting polymers, thermoplastic polymers, or any mixtures thereof, in accordance with some embodiments. The polymer material can include, for example, plastic materials, epoxy resin, polyimide, polyethylene terephthalate (PET), polyvinyl chloride (PVC), polymethylmethacrylate (PMMA), polymer components doped with specific fillers including fiber, clay, ceramic, inorganic particles, or any combinations thereof. In other embodiments, the molding compound  128  can be made of epoxy resin, such as epoxy cresol novolac (ECN), biphenyl epoxy resin, multifunctional liquid epoxy resin, or any combinations thereof, in accordance with some embodiments. In still other embodiments, the molding compound  128  can be made of epoxy resin optionally including one or more fillers to provide the composition with any of a variety of desirable properties. Examples of fillers can be aluminum, titanium dioxide, carbon black, calcium carbonate, silica, or any combinations thereof, in accordance with some embodiments. A thermal process is performed on the molding compound  128  to cure the molding compound  128 , in accordance with some embodiments of the present disclosure. 
     In  FIG.  5 E , the molding compound  128  and a portion of the connecting element  130  are removed (e.g. by grinding), so that the connecting element  130  and the interposer substrate  120  have substantially coplanar top surfaces, in accordance with some embodiments of the present disclosure. In some embodiments, a portion of the interposer substrate  120  is removed as well. 
     In  FIG.  5 F , the conductive structures  134  are provided on the connecting element  130 , and the conductive structures  146  are provided on the interposer substrate  120 , in accordance with some embodiments of the present disclosure. In some embodiments, the size of the conductive structures  134  and the conductive structures  146  may be identical or different. For example, the size of the conductive structures  134  may be smaller than the size of the conductive structures  146 , in accordance with some embodiments of the present disclosure. 
     In  FIG.  5 G , the first semiconductor device  142  and the second semiconductor device  144  are provided on the conductive structures  134  and the conductive structures  146 , in accordance with some embodiments of the present disclosure. In some embodiments, the connecting element  130  is exposed from the interposer substrate  120  when the first semiconductor device  142  and the second semiconductor device  144  are provided on the interposer substrate  120 . In some embodiments, an underfill element  150 B provided on the interposer substrate  120  and the underfill element  150 A, and between the first semiconductor device  142  and the second semiconductor device  144 . In some embodiments, the underfill element  150 A and the underfill element  150 B form the underfill layer  150 . Therefore, the underfill layer  150  continuously extends between the interposer substrate  120 , the connecting element  130 , first semiconductor device  142 , and the second semiconductor device  144 . In some embodiments, the molding layer  160  is provided to cover and surround the first semiconductor device  142  and the second semiconductor device  144 . 
     In  FIG.  5 H , a second carrier  192  is provided on the molding layer  160 . In some embodiments, the first carrier  190  and the second carrier  192  are disposed on opposite sides of the interposer substrate  120 . In some embodiments, a die attach film (DAF) is provided between the second carrier  192  and the molding layer  160  to attach the second carrier  192  onto the molding layer  160 , in accordance with some embodiments of the present disclosure. In  FIG.  5 I , the whole structure is flipped, and the first carrier  190  is removed in some embodiments. 
     In  FIG.  5 J , holes are formed on the interposer substrate  120  (e.g. by etching) to expose the conductive features  124 , and conductive structures  180  are formed on the interposer substrate  120  and partially formed in the holes of the interposer substrate  120  to in contact with the conductive features  124  in the interposer substrate  120 , in accordance with some embodiments of the present disclosure. 
     In  FIG.  5 K , the second carrier  192  is removed. In  FIG.  5 L , a dicing process is performed to let the molding layer  160  and the interposer substrate  120  have a straight sidewall, and then the carrier substrate  110  is connected to the interposer substrate  120  by the conductive structures  180 , in accordance with some embodiments of the present disclosure. The underfill layer  170  is provided to surround the conductive structures  180 , in accordance with some embodiments of the present disclosure. In some embodiments, a portion of the molding layer  160  is removed to expose the top surface of the first semiconductor device  142  and/or the top surface of the second semiconductor device  144 , such as by grinding in some embodiments of the present disclosure. Therefore, the semiconductor package structure  100 A is formed, in accordance with some embodiments of the present disclosure. 
       FIG.  6 A  to  FIG.  6 K  show a process flow of forming the semiconductor package structure  100 B, in accordance with some embodiments of the present disclosure. In  FIG.  6 A , the interposer substrate  120  is provide on a first carrier  190 , in accordance with some embodiments of the present disclosure. In some embodiments, the interposer substrate includes a recess  126 . In some embodiments, conductive features  124  are formed in the portion of the interposer substrate  120  under the recess  126 . In some embodiments, a die attach film (DAF) is provided between the first carrier  190  and the interposer substrate  120  to attach the first carrier  190  onto the interposer substrate  120 , in accordance with some embodiments of the present disclosure. 
     In  FIG.  6 B , the connecting element  130  is provided in the recess  126 , in accordance with some embodiments of the present disclosure. In some embodiments, the connecting element  130  protrudes from the recess  126 . In other words, the top surface of the connecting element  130  is higher than the top surface of the interposer substrate  120 . In some embodiments, the connecting element  130  is in contact with a bottom surface  126 A of the recess  126 . 
     In  FIG.  6 C , an underfill element  150 A is provided to fill the space in the recess  126 , such as the space between the connecting element  130  and the interposer substrate  120 . In some embodiments, the underfill element  150 A surrounds the connecting element  130 . A molding compound  128  is provided to cover the interposer substrate  120 , the connecting element  130 , and the underfill element  150 A, in accordance with some embodiments of the present disclosure. In some embodiments, the underfill element  150 A and the molding compound  128  may include different materials, such as different kinds of epoxy with different compositions and additives. 
     In  FIG.  6 D , the molding compound  128  and a portion of the connecting element  130  are removed (e.g. by grinding), so that the connecting element  130  and the interposer substrate  120  have substantially coplanar top surfaces, in accordance with some embodiments of the present disclosure. In some embodiments, a portion of the interposer substrate  120  is removed as well. 
     In  FIG.  6 E , conductive structures  134  are provided on the connecting element  130 , and the conductive structures  146  are provided on the interposer substrate  120 , in accordance with some embodiments of the present disclosure. In some embodiments, the size of the conductive structures  134  and the conductive structures  146  may be identical or different. For example, the size of the conductive structures  134  may be smaller than the size of the conductive structures  146 , in accordance with some embodiments of the present disclosure. 
     In  FIG.  6 F , the first semiconductor device  142  and the second semiconductor device  144  are provided on the conductive structures  134  and the conductive structures  146 , in accordance with some embodiments of the present disclosure. In some embodiments, the connecting element  130  is exposed from the interposer substrate  120  when the first semiconductor device  142  and the second semiconductor device  144  are provided on the interposer substrate  120 . In some embodiments, an underfill element  150 B provided on the interposer substrate  120  and the underfill element  150 A, and between the first semiconductor device  142  and the second semiconductor device  144 . In some embodiments, the underfill element  150 A and the underfill element  150 B form the underfill layer  150 . Therefore, the underfill layer  150  continuously extends between the interposer substrate  120 , the connecting element  130 , first semiconductor device  142 , and the second semiconductor device  144 . In some embodiments, the molding layer  160  is provided to cover and surround the first semiconductor device  142  and the second semiconductor device  144 . 
     In  FIG.  6 G , a second carrier  192  is provided on the molding layer  160 . In some embodiments, the first carrier  190  and the second carrier  192  are disposed on opposite sides of the interposer substrate  120 . In some embodiments, a die attach film (DAF) is provided between the second carrier  192  and the molding layer  160  to attach the second carrier  192  onto the molding layer  160 , in accordance with some embodiments of the present disclosure. In  FIG.  6 H , the whole structure is flipped, and the first carrier  190  is removed in some embodiments. 
     In  FIG.  61   , holes are formed on the interposer substrate  120  (e.g. by etching) to expose the conductive features  124 , and conductive structures  180  are formed on the interposer substrate  120  and partially formed in the holes of the interposer substrate  120  to in contact with the conductive features  124  in the interposer substrate  120 , in accordance with some embodiments of the present disclosure. 
     In  FIG.  6 J , the second carrier  192  is removed. In  FIG.  6 K , a dicing process is performed to let the molding layer  160  and the interposer substrate  120  have a straight sidewall, and then the substrate  10  is connected to the interposer substrate  120  by the conductive structures  180 , in accordance with some embodiments of the present disclosure. In some embodiments, the connecting element  130  and the conductive structures  180  are disposed on opposite sides of the interposer substrate  120 . In some embodiments, the underfill layer  170  is provided to surround the conductive structures  180 . In some embodiments, a portion of the molding layer  160  is removed to expose the top surface of the first semiconductor device  142  and/or the top surface of the second semiconductor device  144 , such as by grinding in some embodiments of the present disclosure. Therefore, the semiconductor package structure  100 B is formed, in accordance with some embodiments of the present disclosure. 
       FIG.  7 A  is a schematic view of a semiconductor package structure  200 A, in accordance with some embodiments of the present disclosure. As shown in  FIG.  7 A , the semiconductor package structure  200 A mainly includes a carrier substrate  210 , an interposer substrate  220 , a connecting element  230 , a first semiconductor device  242 , a second semiconductor device  244 , an underfill layer  250 , a package layer  260 , and an underfill layer  270 , in accordance with some embodiments of the present disclosure. 
     In some embodiments, the carrier substrate  210  is a semiconductor substrate. By way of example, the material of the carrier substrate  210  may include elementary semiconductor such as silicon or germanium; a compound semiconductor such as silicon germanium, silicon carbide, gallium arsenic, gallium phosphide, indium phosphide or indium arsenide; or combinations thereof. Alternatively, the carrier substrate  210  may be a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, or the like. In some other embodiments, the carrier substrate  210  is a printed circuit board (PCB), a ceramic substrate, or another suitable package substrate. The carrier substrate  210  may be a core or a core-less substrate, in accordance with some embodiments. 
     In some embodiments, the interposer substrate  220  is disposed on the carrier substrate  210 , such as connected to the carrier substrate  210  by conductive structures  280 . An underfill layer  270  is provided to surround and protect the conductive structures  280 , in accordance with some embodiments of the present disclosure. For example, a sidewall of the package layer  260  is in contact with the underfill layer  270 , in accordance with some embodiments of the present disclosure. In some embodiments, the interposer substrate  220  includes a board  222  and conductive features  224 . In some embodiments the board  222  has a first portion  222 A and a second portion  222 B disposed on opposite sides of the connecting element  230 . In some embodiments, conductive features  224  have a first conductive feature  224 A, a second conductive feature  224 B, third conductive features  224 C, and fourth conductive features  224 D. In some embodiments, the first conductive feature  224 A and the third conductive features  224 C are in the first portion  222 A, and the second conductive feature  224 B and the fourth conductive feature  224 D are in the second portion  222 B. In some embodiments, the first conductive feature  224 A and the second conductive feature  224 B are wirings, and the third conductive features  224 C and fourth conductive features  224 D are vias. 
     The conductive features  224  may be made of or include copper, aluminum, cobalt, nickel, gold, silver, tungsten, one or more other suitable materials, or a combination thereof. The board  222  may be made of or include a polymer material, a ceramic material, a metal material, a semiconductor material, one or more other suitable materials, or a combination thereof. In the embodiments that the board  222  includes organic materials, the coefficient of thermal expansion (CTE) mismatch issue between the board  222  and other elements may be mitigated, which reduces the stress between the elements. For example, the board  222  includes resin, prepreg, glass, and/or ceramic. In cases where the board  222  is made of a metal material or a semiconductor material, dielectric layers may be formed between the board  222  and the conductive features  224  to prevent short circuiting. In some embodiments, the conductive features  224  include circuits with pitches between about 2 μm to about 20 μm. In some embodiments, the conductive features  224  include circuits with linewidths between about 1 μm to about 10 μm. 
     In some embodiments, the conductive structures  280  may include conductive pillars, solder bumps, one or more other suitable bonding structures, or a combination thereof. The conductive structures  280  are made of a solder material, such as Sn and Ag or another suitable conductive material (e.g., gold), in accordance with some embodiments. The conductive structures  280  are solder balls, in accordance with some embodiments. A reflow process (not shown) may be performed to make the metallurgical connections between the carrier substrate  210 , the conductive structures  280 , and the interposer substrate  220 , in accordance with some embodiments of the present disclosure. 
     In some embodiments, the underfill layer  270  is dispensed (e.g., by a dispenser (not shown)) into the space between the interposer substrate  220  and the carrier substrate  210  and the space between adjacent conductive structures  280 , and then cured (e.g., ultraviolet (UV) or thermally cured) to harden. The underfill layer  270  may be configured to provide a stronger mechanical connection and a heat bridge between the interposer substrate  220  and the carrier substrate  210 , to reduce cracking in the conductive structures  280  caused by thermal expansion mismatches between the interposer substrate  220  and the carrier substrate  210 , and to protect the joints from contaminants, thereby improving reliability of the fabricated semiconductor package structure  200 A. In some embodiments, the underfill layer  270  includes liquid epoxy, deformable gel, silicon rubber, or the like. 
     In cases where the board  222  is made of or includes a polymer material, the board  222  may further include fillers that are dispersed in the polymer material. The polymer material may be made of or include epoxy-based resin, polyimide-based resin, one or more other suitable polymer materials, or a combination thereof. The examples of the fillers may include fibers (such as silica fibers and/or carbon-containing fibers), particles (such as silica particles and/or carbon-containing particles), or a combination thereof. 
     In some embodiments, an accommodating space is formed in the interposer substrate  220 , and the connecting element  230  is disposed in the accommodating space of the interposer substrate  220 . In some embodiments, a portion of the interposer substrate  220  extends between the connecting element  230  and the carrier substrate  210 . In some embodiments, a portion of the interposer substrate  220  extends between the connecting element  230  and the first semiconductor device  242 , and between the connecting element  230  and the second semiconductor device  244 . In some embodiments, the first semiconductor device  242  and the second semiconductor device  244  are connected to the connecting element  230  through the fourth conductive features  224 D and the conductive structures  234 . Therefore, the first semiconductor device  242  is electrically connected to the second semiconductor device  244  through the connecting element  230 . The connecting element  230  may be a silicon bridge, which enables direct fine pitch electrical connection through high density silicon interconnects of the connecting element  230 , in accordance with some embodiments of the present disclosure. 
     In some embodiments, the first semiconductor device  242  or the second semiconductor device  244  may be a functional integrated circuit (IC) die such as a semiconductor die, an electronic die, a Micro-Electro Mechanical Systems (MEMS) die, or a combination thereof. The functional IC die may include one or more application processors, logic circuits, memory devices, power management integrated circuits, analog circuits, digital circuits, mixed signal circuits, one or more other suitable functional integrated circuits, or a combination thereof, depending on actual needs. In some alternative embodiments, the first semiconductor device  242  or the second semiconductor device  244  may be a package module that has one or more semiconductor dies and an interposer substrate carrying these semiconductor dies. These structures of the first semiconductor device  242  or the second semiconductor device  244  are well known in the art and therefore not described herein. The first semiconductor device  242  or the second semiconductor device  244  can be fabricated by various processes such as deposition, etching, implantation, photolithography, annealing, and/or other suitable processes. 
     In some embodiments, the connecting element  230  includes a passive device (such as a capacitor, a resistor, etc.), a transistor, a memory device, etc. disposed in a dielectric element  237  of the connecting element  230 . In some embodiments, conductive structures  232  may be disposed below the connecting element  230 , and disposed between the interposer substrate  220  and the connecting element  230 . In some embodiments, conductive features  236  and conductive features  238  may be provided in the dielectric element  237  of the connecting element  230 , such as embedded in the dielectric element  237 . In some embodiments, a portion of the conductive features  236  is exposed from the dielectric element  237 , such as in contact with the conductive structures  232  for electrical conduction. In some embodiments, the conductive features  236  may be through silicon vias (TSV) and vertically pass through the dielectric element  237  of the connecting element  230  to provide electrical connection in the vertical direction. For example, the connecting element  230  may be disposed between the first interposer element  220 A and the second interposer element  220 B in some embodiments. In some embodiments, the connecting element  230  has a first surface  230 A facing away from the carrier substrate  210 , and a second surface  230 B facing away from the first surface  230 A. In accordance with some embodiments, the conductive features  236  may extend across the first surface  230 A and the second surface  230 B, and in contact with the conductive structures  232  below the connecting element  230  and the conductive features  224  above the connecting element  230 , such as the fourth conductive features  224 D. Therefore, electrical signal may be transported vertically from the first semiconductor device  242  or the second semiconductor device  244  through the conductive structures  234  and the conductive features  224  above the connecting element  230 , the conductive features  236  in the connecting element  230 , and the conductive structures  232  under the connecting element  230  to the interposer substrate  220 , in accordance with some embodiments of the present disclosure. As a result, electrical signal can be transmitted to the first semiconductor device  242  or the second semiconductor device  244  in a shorter path, in accordance with some embodiments of the present disclosure. 
     In some embodiments, the material of the conductive features  236  may include metal, such as Cu, Al, W, or another suitable conductive material. In some embodiments, the dielectric element  237  includes dielectric materials, such as silicon or another suitable dielectric material. In some embodiments, the material of the conductive features  238  may include metal, such as Cu, Al, W, or another suitable conductive material. In some embodiments, the conductive features  238  include circuits with pitches between about 0.8 μm and about 2 μm. In some embodiments, the conductive features  238  include circuits with linewidths between about 0.4 μm and about 1 μm. 
     In some embodiments, the conductive features  238  may be a redistribution layer to connect the conductive features  236 , so that the first semiconductor device  242  may be electrically connected to the second semiconductor device  244  through the conductive features  236  and the conductive features  238 . Therefore, the signal transport speed of the semiconductor package structure  200 A may be increased by the connecting element  230 , in accordance with some embodiments of the present disclosure. Moreover, using the connecting element  230  for signal transmission reduces the number of required through silicon vias (TSVs), which reduces overall cost and preserves low resistance for high frequency signals, in accordance with some embodiments of the present disclosure. 
     In some embodiments, as shown in  FIG.  7 A , the interposer substrate  220  includes a first interposer element  220 A and a second interposer element  220 B, and the interface between the first interposer element  220 A and the second interposer element  220 B is indicated by the line B-B. In some embodiments, the interposer substrate  220  further includes a bottom surface  221  and a top surface  223 . In some embodiments, the bottom surface  221  faces the carrier substrate  210 , and the top surface faces the first semiconductor device  242  and the second semiconductor device  244 . In some embodiments, the accommodating space has a bottom surface  226 A. In some embodiments, a distance D is between the bottom surface  221  of the interposer substrate  220  and the bottom surface  226 A of the accommodating space, a height H of the accommodating space in the interposer substrate  220  is greater than the distance D, and greater than a thickness T of the second interposer element  220 B. In some embodiments, the distance D and the thickness T are substantially identical. In some embodiments, the height H is greater than the distance D or the thickness T. For example, in some embodiments, a ratio of T:H:D is between 1:5:1 and 2:3:2. Therefore, in some embodiments, a ratio between the height H of the accommodating space and a sum of the distance D and the thickness T of the second portion is between 0.75 and 2.5. Therefore, enough space is provided for the connecting element  230 , so that the connecting element  230  can provide better electrical connection for the first semiconductor device  242  and the second semiconductor device  244 , in accordance with some embodiments of the present disclosure. 
     Moreover, the conductive features  224  are provided with the first conductive feature  224 A and the third conductive features  224 C below the connecting element  230 , and the second conductive feature  224 B and the fourth conductive features  224 D above the connecting element  230 , which means the connecting element  230  is between the first conductive feature  224 A and the second conductive feature  224 B in a vertical direction, so the routability of the interposer substrate  220  can be maintained, in accordance with some embodiments of the present disclosure. In some embodiments, the connecting element  230  is sandwiched between the first portion  222 A and the second portion  222 B of the board  222 , so the mechanical strength of the interposer substrate  220  can be maintained when the connecting element  230  is provide in the space of the interposer substrate  220 . For example, the portions of the interposer substrate  220  above and below the connecting element  230  prevent imbalance thermal expansion, in accordance with some embodiments of the present disclosure. Moreover, more conductive structures  280  may be provided on the interposer substrate  220 , such as may be provided on the portion of the interposer substrate  220  under the recess, in accordance with some embodiments of the present disclosure. In some embodiments, the connecting element  230  is thinner than the interposer substrate  220  to achieve miniaturization. 
     In some embodiments, the conductive structures  232  may include conductive pillars, solder bumps, one or more other suitable bonding structures, or a combination thereof. The conductive structures  232  are made of a solder material, such as Sn and Ag or another suitable conductive material (e.g., gold), in accordance with some embodiments. The conductive structures  232  are solder balls, in accordance with some embodiments. A reflow process (not shown) may be performed to make the metallurgical connections between the interposer substrate  220  and the connecting element  230 , in accordance with some embodiments of the present disclosure. 
     In some embodiments, the first semiconductor device  242  and the second semiconductor device  244  are bonded onto the conductive structures  234  and the conductive structures  246 . The conductive structures  234  and the conductive structures  246  may include conductive pillars, solder bumps, one or more other suitable bonding structures, or a combination thereof, in accordance with some embodiments of the present disclosure. The conductive structures  234  and the conductive structures  246  are made of a solder material, such as Sn and Ag or another suitable conductive material (e.g., gold), in accordance with some embodiments of the present disclosure. The conductive structures  234  and the conductive structures  246  are solder balls, in accordance with some embodiments. A reflow process (not shown) may be performed to make the metallurgical connections between the interposer substrate  220 , the first semiconductor device  242 , the second semiconductor device  244 , the conductive structures  234 , and the conductive structures  246 , in accordance with some embodiments of the present disclosure. 
     In some embodiments, an underfill layer  250  is dispensed (e.g., by a dispenser (not shown)) into the space between the interposer substrate  220 , the first semiconductor device  242 , and the second semiconductor device  244 , and then cured (e.g., ultraviolet (UV) or thermally cured) to harden. In some embodiments, the underfill layer  250  is separated from the connecting element  230  by the interposer substrate  220 . The underfill layer  250  may be configured to provide a stronger mechanical connection and a heat bridge between the interposer substrate  220 , the first semiconductor device  242 , and the second semiconductor device  244  to reduce cracking in the conductive structures  234  and the conductive structures  246  caused by thermal expansion mismatches between the interposer substrate  220 , the first semiconductor device  242 , and the second semiconductor device  244 , and to protect the joints from contaminants, thereby improving reliability of the fabricated semiconductor package structure  200 A, in accordance with some embodiments of the present disclosure. In some embodiments, the underfill layer  250  includes liquid epoxy, deformable gel, silicon rubber, or the like. In some embodiments, an underfill element  252  is filled in the accommodating space of the interposer substrate  220 , and may be in contact with the connecting element  230  and the conductive structures  232 . The material and the forming process of the underfill element  252  may be similar to that of the underfill layer  250 , and is not repeated. In some embodiments, the underfill layer  250  is separated from the underfill element  252  by the interposer substrate  220 . 
     In some embodiments, a molding layer  260  fills gaps between the first semiconductor device  242  and the second semiconductor device  244 , in accordance with some embodiments. The molding layer  260  in the gaps surrounds the first semiconductor device  242  and the second semiconductor device  244 , in accordance with some embodiments. The molding layer  260  may be configured to provide package stiffness, a protective or hermetic shielding, and/or provide a heat conductive path to prevent chip overheating, in accordance with some embodiments of the present disclosure. The molding layer  260  may be formed by a spin-on coating process, an injection molding process, or the like, in accordance with some embodiments of the present disclosure. 
     The molding layer  260  includes a polymer material, in accordance with some embodiments. The term “polymer” here can represent thermosetting polymers, thermoplastic polymers, or any mixtures thereof, in accordance with some embodiments. The polymer material can include, for example, plastic materials, epoxy resin, polyimide, polyethylene terephthalate (PET), polyvinyl chloride (PVC), polymethylmethacrylate (PMMA), polymer components doped with specific fillers including fiber, clay, ceramic, inorganic particles, or any combinations thereof. In other embodiments, the molding layer  260  can be made of epoxy resin, such as epoxy cresol novolac (ECN), biphenyl epoxy resin, multifunctional liquid epoxy resin, or any combinations thereof, in accordance with some embodiments. In still other embodiments, the molding layer  260  can be made of epoxy resin optionally including one or more fillers to provide the composition with any of a variety of desirable properties. Examples of fillers can be aluminum, titanium dioxide, carbon black, calcium carbonate, silica, or any combinations thereof, in accordance with some embodiments. A thermal process is performed on the molding layer  260  to cure the molding layer  260 , in accordance with some embodiments of the present disclosure. 
     In some embodiments, the connecting element  230  and the interposer substrate  220  are separated by the underfill layer  250 . For example,  FIG.  7 B  is a top view illustrated along line C′-C′ in  FIG.  7 A , in accordance with some embodiments of the present disclosure. In some embodiments, the connecting element  230  is surrounded by the interposer substrate  220 , and the underfill element  252  fills the gap between the connecting element  230  and the interposer substrate  220  in the accommodating space. In some embodiments, the connecting structures  34  overlap the connecting element  230 , and the connecting structures  246  overlap the interposer substrate  220 . In other words, the conductive structures  246  are separated from the connecting element  230  in the top view, in accordance with some embodiments of the present disclosure. 
       FIG.  7 C  is a schematic view of a semiconductor package structure  200 B, in accordance with some embodiments of the present disclosure. Elements in the semiconductor package structure  200 B that are similar to the elements in the semiconductor package structure  200 A are not described again. As shown in  FIG.  7 C , the second conductive feature  224 B (e.g. wirings) above the connecting element  230  in  FIG.  7 A  may be omitted, and the fourth conductive features  224 D (e.g. vias) may be remained. 
       FIG.  7 D  is a schematic view of a semiconductor package structure  200 C, in accordance with some embodiments of the present disclosure. Elements in the semiconductor package structure  200 C that are similar to the elements in the semiconductor package structure  200 A are not described again. As shown in  FIG.  7 D , the first conductive feature  224 A (e.g. wirings) above the connecting element  230  in  FIG.  7 A  may be omitted, and the third conductive features  224 C (e.g. vias) may be remained. 
     In some embodiments, the conductive structure  232  may be omitted.  FIG.  8 A  is a schematic view of a semiconductor package structure  200 D, in accordance with some embodiments of the present disclosure. In some embodiments, the connecting element  230  is separated from the first interposer element  220 A of the interposer substrate  220 , and the underfill element  252  fills the space between the interposer substrate  220  and the connecting element  230 . Therefore, the connecting element  230  is not directly electrically connected to the first interposer element  220 A. Since in the semiconductor package structure  200 D, no conductive structure is provided between the interposer substrate  220  and the connecting element  230  in the recess of the interposer substrate  220 , the process steps and costs may be reduced, in accordance with some embodiments of the present disclosure. 
       FIG.  8 B  is a schematic view of a semiconductor package structure  200 E, in accordance with some embodiments of the present disclosure. Elements in the semiconductor package structure  200 E that are similar to the elements in the semiconductor package structure  200 D are not described again. As shown in  FIG.  8 B , the second conductive feature  224 B (e.g. wirings) above the connecting element  230  in  FIG.  8 A  may be omitted, and the fourth conductive features  224 D (e.g. vias) may be remained. 
       FIG.  8 C  is a schematic view of a semiconductor package structure  200 F, in accordance with some embodiments of the present disclosure. Elements in the semiconductor package structure  200 F that are similar to the elements in the semiconductor package structure  200 D are not described again. As shown in  FIG.  8 C , the first conductive feature  224 A (e.g. wirings) above the connecting element  230  in  FIG.  8 A  may be omitted, and the third conductive features  224 C (e.g. vias) may be remained. 
       FIG.  8 D  is a schematic view of a semiconductor package structure  200 G, in accordance with some embodiments of the present disclosure. In  FIG.  8 D , the connecting element  230  is in direct contact with the first interposer element  220 A of the interposer substrate  220 , in accordance with some embodiments of the present disclosure. In some embodiments, the conductive features  236  are in direct contact with the third conductive features  224 C in the first interposer element  220 A to allow vertical electrical connection. Therefore, the path for signal transmission path may be reduced. 
       FIG.  9    is a schematic view of a semiconductor package structure  200 H, in accordance with some embodiments of the present disclosure. In the semiconductor package structure  200 H, the first semiconductor device  242  and the second semiconductor device  244  may be chip packages. For example, the first semiconductor device  242  includes a chip  242 A, conductive structures  242 B under the chip  242 A, and an underfill layer  242 C under the chip  242 A and surrounding the conductive structures  242 B, in accordance with some embodiments of the present disclosure. The second semiconductor device  244  includes a chip  244 A, conductive structures  244 B under the chip  244 A, and an underfill layer  244 C under the chip  244 A and surrounding the conductive structures  244 B, in accordance with some embodiments of the present disclosure. A molding structure  245  is provided to continuously surround the first semiconductor device  242  and the second semiconductor device  244 , in accordance with some embodiments of the present disclosure. In some embodiments, a third semiconductor device  248  is provided in the semiconductor package structure  200 H. In some embodiments, the third semiconductor device  248  is connected to the interposer substrate  220 , and is surrounded by the underfill layer  250  and the molding layer  260 . In some embodiments, the chip  242 A, the chip  244 A, and the third semiconductor device  248  have different heights or functions. For example, the heights the conductive structures  242 B and conductive structures  244 B are adjustable for chips with different heights. 
     In accordance with some embodiments of the present disclosure,  FIG.  10    is schematic views of a semiconductor package structure  2001 . Elements in the semiconductor package structure  2001  that are similar to the elements in the semiconductor package structure  200 H are not described again. As shown in  FIG.  10   , the conductive structure  232  may be omitted, and the connecting element  230  is not directly electrically connected to the interposer substrate  220  through the third conductive features  224 C under the connecting element  230 , in accordance with some embodiments of the present disclosure. 
       FIG.  11 A  to  FIG.  11 L  show a process flow of forming the semiconductor package structure  200 A, in accordance with some embodiments of the present disclosure. In  FIG.  11 A , the first interposer element  220 A is provide on a first carrier  290 , in accordance with some embodiments of the present disclosure. In some embodiments, the interposer substrate includes a recess  226 . In some embodiments, conductive features  224  are disposed in the portion of the first interposer element  220 A under the recess  226 . In some embodiments, a die attach film (DAF) is provided between the first carrier  290  and the first interposer element  220 A to attach the first carrier  290  onto the first interposer element  220 A, in accordance with some embodiments of the present disclosure. 
     In  FIG.  11 B , conductive structures  232  are disposed in the recess  226  of the first interposer element  220 A, in accordance with some embodiments of the present disclosure. In some embodiments, the conductive structures  232  are electrically connected to the conductive features  224  in the portion of first interposer element  220 A under the recess  226 . In  FIG.  11 C , the connecting element  230  is provided in the recess  226  and disposed on the conductive structures  232 , in accordance with some embodiments of the present disclosure. In some embodiments, the connecting element  230  protrudes from the recess  226 . In other words, the top surface of the connecting element  230  is higher than the top surface of the first interposer element  220 A. 
     In  FIG.  11 D , an underfill element  252  is provided to fill the space in the recess  226 , such as the space between the connecting element  230  and the first interposer element  220 A. In some embodiments, the underfill element  252  surrounds the conductive structures  232 . A molding compound  228  is provided to cover the first interposer element  220 A, the connecting element  230 , and the underfill element  252 , in accordance with some embodiments of the present disclosure. In some embodiments, the underfill element  252  and the molding compound  228  may include different materials, such as different kinds of epoxy with different compositions and additives. 
     The molding compound  228  includes a polymer material, in accordance with some embodiments. The term “polymer” here can represent thermosetting polymers, thermoplastic polymers, or any mixtures thereof, in accordance with some embodiments. The polymer material can include, for example, plastic materials, epoxy resin, polyimide, polyethylene terephthalate (PET), polyvinyl chloride (PVC), polymethylmethacrylate (PMMA), polymer components doped with specific fillers including fiber, clay, ceramic, inorganic particles, or any combinations thereof. In other embodiments, the molding compound  228  can be made of epoxy resin, such as epoxy cresol novolac (ECN), biphenyl epoxy resin, multifunctional liquid epoxy resin, or any combinations thereof, in accordance with some embodiments. In still other embodiments, the molding compound  228  can be made of epoxy resin optionally including one or more fillers to provide the composition with any of a variety of desirable properties. Examples of fillers can be aluminum, titanium dioxide, carbon black, calcium carbonate, silica, or any combinations thereof, in accordance with some embodiments. A thermal process is performed on the molding compound  228  to cure the molding compound  228 , in accordance with some embodiments of the present disclosure. 
     In  FIG.  11 E , the molding compound  228  and a portion of the connecting element  230  are removed (e.g. by grinding), so that the connecting element  230  and the first interposer element  220 A have substantially coplanar top surfaces, in accordance with some embodiments of the present disclosure. In some embodiments, a portion of the first interposer element  220 A is removed as well. 
     In  FIG.  11 F , a second interposer element  220 B is provided on the first interposer element  220 A, and the conductive structures  234  and the conductive structures  246  are provided on the second interposer element  220 B, in accordance with some embodiments of the present disclosure. The conductive structures  234  are provided above the connecting element  230  (e.g. overlap the connecting element  230  in the vertical direction), and the conductive structures  246  are separated from the connecting element  230  in the vertical direction, in accordance with some embodiments of the present disclosure. In some embodiments, the size of the conductive structures  234  and the conductive structures  246  may be identical or different. For example, the size of the conductive structures  234  may be smaller than the size of the conductive structures  246 , in accordance with some embodiments of the present disclosure. In some embodiments, the recess  226  of the first interposer element  220 A is covered by the second interposer element  220 B to form the accommodating space. 
     In  FIG.  11 G , the first semiconductor device  242  and the second semiconductor device  244  are provided on the conductive structures  234  and the conductive structures  246 , in accordance with some embodiments of the present disclosure. In some embodiments, the connecting element  230  is enclosed in the interposer substrate  220  when the first semiconductor device  242  and the second semiconductor device  244  are provided on the interposer substrate  220 . In some embodiments, the underfill layer  250  is provided on the interposer substrate  220 , and between the first semiconductor device  242  and the second semiconductor device  244 . Therefore, the underfill layer  250  continuously extends between the interposer substrate  220 , the first semiconductor device  242 , and the second semiconductor device  244 . In some embodiments, the molding layer  260  is provided to cover and surround the first semiconductor device  242  and the second semiconductor device  244 . 
     In  FIG.  11 H , a second carrier  292  is provided on the molding layer  260 . In some embodiments, the first carrier  290  and the second carrier  292  are disposed on opposite sides of the interposer substrate  220 . In some embodiments, a die attach film (DAF) is provided between the second carrier  292  and the molding layer  260  to attach the second carrier  292  onto the molding layer  260 , in accordance with some embodiments of the present disclosure. In  FIG.  111   , the whole structure is flipped, and the first carrier  290  is removed in some embodiments. 
     In  FIG.  11 J , holes are formed on the interposer substrate  220  (e.g. by etching) to expose the conductive features  224 , and conductive structures  280  are formed on the interposer substrate  220  and partially formed in the holes of the interposer substrate  220  to in contact with the conductive features  224  in the interposer substrate  220 , in accordance with some embodiments of the present disclosure. 
     In  FIG.  11 K , the second carrier  292  is removed. In  FIG.  11 L , a dicing process is performed to let the molding layer  260  and the interposer substrate  220  have a straight sidewall, and then the carrier substrate  210  is connected to the interposer substrate  220  by the conductive structures  280 , in accordance with some embodiments of the present disclosure. In some embodiments, the underfill layer  270  is provided to surround the conductive structures  280 . In some embodiments, a portion of the molding layer  260  is removed to expose the top surface of the first semiconductor device  242  and/or the top surface of the second semiconductor device  244 , such as by grinding in some embodiments of the present disclosure. Therefore, the semiconductor package structure  200 A is formed, in accordance with some embodiments of the present disclosure. 
       FIG.  12 A  to  FIG.  12 K  show a process flow of forming the semiconductor package structure  200 B, in accordance with some embodiments of the present disclosure. In  FIG.  12 A , the first interposer element  220 A is provide on a first carrier  290 , in accordance with some embodiments of the present disclosure. In some embodiments, the first interposer element  220 A includes a recess  226 . In some embodiments, conductive features  224  are formed in the portion of the first interposer element  220 A under the recess  226 . In some embodiments, a die attach film (DAF) is provided between the first carrier  290  and the first interposer element  220 A to attach the first carrier  290  onto the first interposer element  220 A, in accordance with some embodiments of the present disclosure. 
     In  FIG.  12 B , the connecting element  230  and the underfill element  252  are provided in the recess  226 , in accordance with some embodiments of the present disclosure. In some embodiments, the connecting element  230  protrudes from the recess  226 . In other words, the top surface of the connecting element  230  is higher than the top surface of the first interposer element  220 A. In some embodiments, the underfill element  252  is formed in the recess  226  before providing the connecting element  230  in the recess  226 . 
     In  FIG.  12 C , a molding compound  228  is provided to cover the first interposer element  220 A, the connecting element  230 , and the underfill element  252 , in accordance with some embodiments of the present disclosure. In some embodiments, the underfill element  252  and the molding compound  228  may include different materials, such as different kinds of epoxy with different compositions and additives. 
     In  FIG.  12 D , the molding compound  228  and a portion of the connecting element  230  are removed (e.g. by grinding), so that the connecting element  230  and the first interposer element  220 A have substantially coplanar top surfaces, in accordance with some embodiments of the present disclosure. In some embodiments, a portion of the first interposer element  220 A is removed as well. 
     In  FIG.  12 E , a second interposer element  220 B is provided on the first interposer element  220 A, and the conductive structures  234  and the conductive structures  246  are provided on the second interposer element  220 B, in accordance with some embodiments of the present disclosure. The conductive structures  234  are provided above the connecting element  230  (e.g. overlap the connecting element  230  in the vertical direction), and the conductive structures  246  are separated from the connecting element  230  in the vertical direction, in accordance with some embodiments of the present disclosure. In some embodiments, the size of the conductive structures  234  and the conductive structures  246  may be identical or different. For example, the size of the conductive structures  234  may be smaller than the size of the conductive structures  246 , in accordance with some embodiments of the present disclosure. 
     In  FIG.  12 F , the first semiconductor device  242  and the second semiconductor device  244  are provided on the conductive structures  234  and the conductive structures  246 , in accordance with some embodiments of the present disclosure. In some embodiments, the connecting element  230  is enclosed in the interposer substrate  220  when the first semiconductor device  242  and the second semiconductor device  244  are provided on the interposer substrate  220 . In some embodiments, an underfill layer  250  is provided on the interposer substrate  220 , and between the first semiconductor device  242  and the second semiconductor device  244 . Therefore, the underfill layer  250  continuously extends between the interposer substrate  220 , the first semiconductor device  242 , and the second semiconductor device  244 . In some embodiments, the molding layer  260  is provided to cover and surround the first semiconductor device  242  and the second semiconductor device  244 . 
     In  FIG.  12 G , a second carrier  292  is provided on the molding layer  260 . In some embodiments, the first carrier  290  and the second carrier  292  are disposed on opposite sides of the interposer substrate  220 . In some embodiments, a die attach film (DAF) is provided between the second carrier  292  and the molding layer  260  to attach the second carrier  292  onto the molding layer  260 , in accordance with some embodiments of the present disclosure. In  FIG.  12 H , the whole structure is flipped, and the first carrier  290  is removed in some embodiments. In  FIG.  121   , holes are formed on the interposer substrate  220  (e.g. by etching) to expose the conductive features  224 , and conductive structures  280  are formed on the interposer substrate  220  and partially formed in the holes of the interposer substrate  220  to in contact with the conductive features  224  in the interposer substrate  220 , in accordance with some embodiments of the present disclosure. 
     In  FIG.  12 J , the second carrier  292  is removed. In  FIG.  12 K , a dicing process is performed to let the molding layer  260  and the interposer substrate  220  have a straight sidewall, and then the carrier substrate  210  is connected to the interposer substrate  220  by the conductive structures  280 , in accordance with some embodiments of the present disclosure. In some embodiments, the connecting element  230  and the conductive structures  280  are disposed on opposite sides of the interposer substrate  220 . In some embodiments, the underfill layer  270  is provided to surround the conductive structures  280 . In some embodiments, a portion of the molding layer  260  is removed to expose the top surface of the first semiconductor device  242  and/or the top surface of the second semiconductor device  244 , such as by grinding in some embodiments of the present disclosure. Therefore, the semiconductor package structure  200 B is formed, in accordance with some embodiments of the present disclosure. 
     In summary, a semiconductor package structure having a connecting element disposed in the recess of the interposer substrate for connecting semiconductor devices and a semiconductor package structure having a connecting element disposed in the accommodating space of the interposer substrate for connecting semiconductor devices are provided in some embodiments of the present disclosure. Such configuration allows signal of the semiconductor devices being transmitted faster, keeps the routability of the interposer substrate, and saves space for bumps on the interposer substrate. Therefore, the total cost is reduced, and miniaturization may be achieved. Moreover, providing the interposer substrate on both sides of the connecting elements keeps the mechanical strength of the interposer substrate, so the reliability of the semiconductor package structure may be enhanced. 
     A semiconductor package structure is provided in some embodiments, The semiconductor package structure includes a carrier substrate, an interposer substrate, a first semiconductor device, a second semiconductor device, a first underfill layer, and a package layer. The interposer substrate is disposed on the carrier substrate. The connecting element is disposed in the interposer substrate, wherein the connecting element includes a dielectric element and first conductive features disposed in the dielectric element. The first semiconductor device and the second semiconductor device are disposed on the interposer substrate, wherein the first semiconductor device is electrically connected to the second semiconductor device through the connecting element. The first underfill layer is disposed between the first semiconductor device, the second semiconductor device, and the interposer substrate. The package layer surrounds the first semiconductor device, the second semiconductor device, and the first underfill layer. 
     A method for forming a semiconductor package structure is provided in some embodiments of the present disclosure. The method includes providing an interposer substrate. The method further includes providing a connecting element in the interposer substrate, wherein the connecting element includes a dielectric element and conductive features disposed in the dielectric element. The method further includes providing a first semiconductor device and a second semiconductor device on the interposer substrate, wherein the first semiconductor device and the second semiconductor device are electrically connected to the connecting element. The method further includes bonding the interposer substrate to a carrier substrate. 
     A method for forming a semiconductor package structure is provided in some embodiments of the present disclosure. The method includes providing an interposer substrate. The method further includes providing a connecting element in the interposer substrate, wherein the connecting element includes a dielectric element and conductive features disposed in the dielectric element. The method further includes providing a first semiconductor device and a second semiconductor device on the interposer substrate, wherein the first semiconductor device and the second semiconductor device are electrically connected to the connecting element. The method further includes forming a first underfill layer between the first semiconductor device, the second semiconductor device, and the interposer substrate. The method further includes forming a package layer surrounding the first semiconductor device, the second semiconductor device, and the first underfill layer. The method further includes bonding a carrier substrate to the interposer substrate. The method further includes forming a second underfill layer between the carrier substrate and the interposer substrate. 
     The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.