Patent Publication Number: US-9405145-B2

Title: Thin film transistor array panel for a display and manufacturing method thereof

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application claims priority to Korean Patent Application No. 10-2013-0106748 filed in the Korean Intellectual Property Office on Sep. 5, 2013, the disclosure of which is incorporated by reference herein in its entirety. 
     TECHNICAL FIELD 
     The present invention relates to a thin film transistor array panel for a display device and a manufacturing method of a display panel. 
     DISCUSSION OF THE RELATED ART 
     A liquid crystal display includes two panels. One of the panels may include gate lines, data lines, pixel electrodes, and thin film transistors, and the other may include a common electrode, color filters, and light blocking members. Such display structure may not provide the best aperture ratio. 
     SUMMARY 
     According to an exemplary embodiment of the present invention, a thin film transistor array panel according to an exemplary embodiment of the present invention includes a substrate. A data line is formed on the substrate. A color filter covers at least a portion of the data line. A shielding electrode is formed on the color filter and is disposed over the data line. A pixel electrode is formed on the color filter and is separated from the shielding electrode. The shielding electrode has a low reflection characteristic. 
     The shielding electrode may include a copper (Cu) layer, an indium zinc oxide (IZO) layer, and a titanium (Ti) layer that are formed one over another. 
     The shielding electrode may include a HASTELLOY® alloy. HASTELLOY is a registered trademark of Haynes International, Inc. 
     A reflectivity of the shielding electrode may be in a range from about 5 to about 10%. 
     The indium zinc oxide (IZO) layer may be replaced with a transparent conductive material including zinc oxide (ZnO), gallium zinc oxide (GZO), zinc indium oxide (ZIO), or zinc aluminum oxide (ZAO). 
     A thickness of the titanium layer may be in a range from about 70 Å to about 200 Å. 
     A thickness of the indium zinc oxide layer may be in a range from about 400 Å to about 1000 Å. 
     A thickness of the copper layer may be in a range from about 500 Å to about 1000 Å. 
     According to an exemplary embodiment of the present invention, a method of manufacturing a display panel according to an exemplary embodiment of the present invention includes sequentially depositing a copper layer on a substrate, an indium zinc oxide layer on the copper layer, and a titanium layer on the indium zinc oxide layer. The deposited copper, indium zinc oxide, and titanium layer are etched, forming a shielding electrode. A transparent conductive material is formed on the substrate including the shielding electrode. The transparent conductive material is etched, forming a pixel electrode separated from the shielding electrode and removing the transparent conductive material formed on the shielding electrode. 
     The indium zinc oxide (IZO) layer may be replaced with a transparent conductive material including zinc oxide (ZnO), gallium zinc oxide (GZO), zinc indium oxide (ZIO), or zinc aluminum oxide (ZAO). 
     Etching the shielding electrode may include using a titanium etchant or a copper etchant. 
     A thickness of the copper layer may be in a range from about 500 Å to about 1000 Å. 
     A thickness of the indium zinc oxide layer may be in a range from about 400 Å to about 1000 Å. 
     A thickness of the titanium layer may be in a range from about 70 Å to about 200 Å. 
     According to an exemplary embodiment of the present invention, a display panel comprises a substrate. A data line is formed on the substrate. A color filter covers at least a portion of the data line. A shielding electrode is formed on the color filter. The shielding electrode overlaps at least a portion of the data line. A pixel electrode is formed on the color filter and is electrically separated or floats from the shielding electrode. 
     A common voltage is applied to the shielding electrode. The display panel further comprises an overcoat layer between the color filter and the shielding electrode. The shielding electrode includes a triple-layered structure. The shielding electrode includes three layers that are respectively formed of different materials from each other, the materials having low reflectivity. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       A more complete appreciation of the present disclosure and many of the attendant aspects thereof will be readily obtained as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings, wherein: 
         FIG. 1  is a cross-sectional view of a thin film transistor array panel according to an exemplary embodiment of the present invention; 
         FIG. 2  to  FIG. 4  are views showing a process of manufacturing a shielding electrode according to an exemplary embodiment of the present invention; 
         FIG. 5  is an equivalent circuit diagram of one pixel of a liquid crystal display according to an exemplary embodiment of the present invention; 
         FIG. 6  is a layout view of two pixels of a liquid crystal display according to an exemplary embodiment of the present invention; and 
         FIG. 7  is a cross-sectional view taken along line VII-VII of  FIG. 6 , according to an exemplary embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF EMBODIMENTS 
     Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. The present invention, however, may be modified in various different ways, and should not be construed as limited to the embodiments set forth herein. Like reference numerals may designate like or similar elements throughout the specification and the drawings. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on,” “connected to,” “coupled to,” or “adjacent to” another element, it can be directly on, connected, coupled, or adjacent to the other element or intervening elements may also be present. 
       FIG. 1  is a cross-sectional view of a thin film transistor array panel according to an exemplary embodiment of the present invention. 
     Referring to  FIG. 1 , a thin film transistor array panel according to an exemplary embodiment includes a gate line (not shown) and a storage electrode  131  formed on an insulation substrate  110 . The gate line includes a gate electrode. A gate insulating layer  140  covers the gate line and the storage electrode  131 . A semiconductor layer  151 , a data line  171 , and a drain electrode (not shown) are disposed on the gate insulating layer  140 . The semiconductor layer  151  may be disposed under the data line  171  and the drain electrode. The data line  171  includes a source electrode (not shown). The gate electrode, the source electrode, the drain electrode, and a portion of the semiconductor layer  151  form a thin film transistor. 
     A color filter  230  is disposed on the data line  171  and the gate insulating layer  140 . Color filters  230  of different colors are disposed at left and right sides with respect to the data line  171 , and the color filters  230  of the different colors overlap each other on the data line  171 . 
     An overcoat layer  30  is disposed on the color filter  230 , and a pixel electrode  191  and a shielding electrode  88  are disposed on the overcoat layer  30 . The color filter  230  and the overcoat layer  30  may have a contact hole (not shown) exposing the drain electrode, and the pixel electrode  191  is electrically connected to the drain electrode through the contact hole thereby receiving a data voltage. 
     The shielding electrode  88  is disposed on a portion corresponding to the data line  171 , is separated from the pixel electrode  191 , and may be electrically floating or may be applied with a predetermined voltage such as a common voltage. 
     The shielding electrode  88  is formed of a low reflection material having low reflectivity. The low reflection material according to an exemplary embodiment of the present invention may have a triple structure, as shown in  FIG. 1 . The shielding electrode  88  according to an exemplary embodiment of the present invention includes a first electrode layer  88   a , a second electrode layer  88   b  disposed on the first electrode layer  88   a , and a third electrode layer  88   c  disposed on the second electrode layer  88   b.    
     The first electrode layer  88   a  may be made of copper (Cu), and a thickness of the first electrode layer  88   a  may be in a range from about 500 Å to about 1000 Å. When the thickness of the first electrode layer  88   a  is thinner, light may be transmitted through the first electrode layer  88   a , and thus, the first electrode layer  88   a  cannot function as a light blocking member. The shielding electrode  88  may function as a light blocking member, and thus, a separate light blocking member might not be formed. 
     The second electrode layer  88   b  may be made of a transparent conductive material, such as IZO, ZnO, GZO, ZIO, and ZAO, and a thickness of the second electrode layer  88   b  may be in a range from about 400 Å to about 1000 Å. 
     The third electrode layer  88   c  may be made of titanium (Ti), and a thickness of the third electrode layer  88   c  may be in a range from about 70 Å to about 200 Å. In this thickness range, the titanium layer  88   c  may have a transflective characteristic. 
     The shielding electrode  88  has low reflectivity because the second electrode layer  88   b  and the third electrode layer  88   c  block light reflected by the first electrode layer  88   a  that is formed of copper, and thus, a deterioration of a contrast ratio due to the reflection of external light that penetrates into the thin film transistor array panel may be prevented. As such, light coming to the inside of the display panel is blocked by using the shielding electrode  88  in an exemplary embodiment of the present invention, thus preventing a deterioration of the contrast ratio of the display panel and eliminating the need for a light blocking member. 
     In an exemplary embodiment of the present invention, the shielding electrode  88  includes the first electrode layer  88   a , the second electrode layer  88   b , and the third electrode layer  88   c , however exemplary embodiments of the present invention are not limited thereto. Alternatively, a single layer or a deposition layer having as high reflectivity as the triple-layered shielding electrode may be used. A HASTELLOY® alloy may be included in the single layer or the deposition layer. 
       FIG. 2  to  FIG. 4  are views sequentially showing a method of manufacturing a shielding electrode according to an exemplary embodiment of the present invention. 
     Referring to  FIG. 2 , a gate line (not shown) including a gate electrode and a storage electrode  131  are formed on an insulation substrate  110 , and a gate insulating layer  140  covers the gate line and the storage electrode  131 . A semiconductor layer  151 , a data line  171 , and a drain electrode (not shown) are formed on the gate insulating layer  140 . 
     The semiconductor layer  151  is formed under the data line  171  including the source electrode and the drain electrode. The gate electrode, the source electrode, the drain electrode, and the portion of the semiconductor layer  151  form a thin film transistor. 
     Color filters  230  of different colors are formed at the right and left side with respect to the data line  171  on the gate insulating layer  140  and the data line  171 , and the color filters  230  of the different colors overlap each other on the data line  171 . 
     An overcoat layer  30  is formed on the color filter  230 . A pixel electrode  191  and a shielding electrode  88  are formed on the overcoat layer  30 . The color filter  230  and the overcoat layer  30  may have a contact hole (not shown) exposing the drain electrode. The pixel electrode  191  is electrically connected to the drain electrode and receives a data voltage. 
     A first metal electrode layer  88   a , a second electrode layer  88   b , and a third electrode layer  88   c  are sequentially formed on the overcoat layer  30 .
         The first electrode layer  88   a  may be formed of copper (Cu), and the thickness of the first electrode layer  88   a  may be in a range from about 500 Å to about 1000 Å.       

     The second electrode layer [[ 80   b ]] 88   b  may be formed of a transparent conductive material including IZO, ZnO, GZO, ZIO, and ZAO, and the thickness of the second electrode layer  88   b  may be in a range from about 400 Å to about 1000 Å. 
     The third electrode layer  88   c  may be formed of titanium (Ti), and the thickness of the third electrode layer  88   c  may be in a range from about 70 Å to about 200 Å. 
     In an exemplary embodiment of the present invention, the shielding electrode  88  includes the first electrode layer  88   a , the second electrode layer  88   b , and the third electrode layer  88   c . However, exemplary embodiments of the present invention are not limited thereto. Alternatively, a single layer or a deposition layer having as high reflectivity as the shielding electrode of the triple layer may be used. A HASTELLOY® alloy may be included in the single layer or deposition layer. 
     Referring to  FIG. 3 , the first electrode layer  88   a , the second electrode layer  88   b , and the third electrode layer  88   c  are etched by using an etchant, thus forming the shielding electrode  88 . The shielding electrode  88  includes the first electrode layer  88   a , the second electrode layer  88   b  disposed on the first electrode layer  88   a , and the third electrode layer  88   c  disposed on the second electrode layer  88   b.    
     The etchant may be a titanium etchant or a copper etchant. 
     Referring to  FIG. 4 , an IZO layer is formed on the shielding electrode  88  and the overcoat layer  30 , as shown in  FIG. 1 . The IZO layer on the shielding electrode  88  and the overcoat layer  30  is etched, forming a pixel electrode  191 . 
     The etching of the IZO layer may be performed by using an IZO etchant. 
     The titanium etchant or the copper etchant etches the IZO layer. The IZO etchant does not affect the titanium layer and the copper layer, and thus, the shielding electrode  88  is formed and then the pixel electrode  191  is formed. 
       FIG. 5  is an equivalent circuit diagram of one pixel of a liquid crystal display according to an exemplary embodiment of the present invention. 
     Referring to  FIG. 5 , one pixel PX of the liquid crystal display according to an exemplary embodiment of the present invention includes a plurality of signal lines including a gate line GL for transferring a gate signal, a data line DL for transferring a data signal, and a storage electrode line RL for transferring a divided reference voltage, first, second, and third switching elements Qa, Qb, and Qc connected to the plurality of signal lines, and first and second liquid crystal capacitors Clca and Clcb. 
     The first and second switching elements Qa and Qb are connected to the gate line GL and the data line DL, respectively, and the third switching element Qc is connected to an output terminal of the second switching element Qb and the storage electrode line RL. 
     The first switching element Qa and the second switching element Qb are three-terminal elements such as thin film transistors, and the first and second switching elements Qa and Qb have control terminals connected to the gate line GL and input terminals connected to the data line DL. An output terminal of the first switching element Qa is connected to the first liquid crystal capacitor Clca, and an output terminal of the second switching element Qb is connected to the input terminals of the second liquid crystal capacitor Clcb and the third switching element Qc. 
     The third switching element Qc may be a three-terminal element such as a thin film transistor, and the third switching element Qc has a control terminal connected to the gate line GL, an input terminal connected to the second liquid crystal capacitor Clcb, and an output terminal connected to the storage electrode line RL. 
     When a gate-on signal is applied to the gate line GL, the first switching element Qa, the second switching element Qb, and the third switching element Qc which are connected to the gate line GL are turned on. Thus, a data voltage is applied via the data line DL to a first subpixel electrode PEa and a second subpixel electrode PEb through the turned-on first switching element Qa and second switching element Qb. In this case, the data voltages applied to the first subpixel electrode PEa and the second subpixel electrode PEb are the same, and the first liquid crystal capacitor Clca and the second liquid crystal capacitor Clcb are charged with a difference voltage between the common voltage and the data voltage. Substantially simultaneously, the charged voltage in the second liquid crystal capacitor Clcb is divided through the turned-on third switching element Qc. Thus, a charged voltage in the second liquid crystal capacitor Clcb is decreased by a difference between the common voltage and the divided reference voltage. For example, the charged voltage in the first liquid crystal capacitor Clca is higher than the charged voltage in the second liquid crystal capacitor Clcb. 
     As such, the charged voltage in the first liquid crystal capacitor Clca and the charged voltage in the second liquid crystal capacitor Clcb are different from each other. The voltage of the first liquid crystal capacitor Clca and the voltage of the second liquid crystal capacitor Clcb are different from each other, and thus, the tilting angle of liquid crystal molecules in the first subpixel is rendered different from the tilting angles of liquid crystal molecules in the second subpixel. The luminance of the first subpixel is accordingly rendered different from the luminance of the second subpixel. Accordingly, by controlling the voltage of the first liquid crystal capacitor Clca and the voltage of the second liquid crystal capacitor Clcb, an image viewed from the side of the liquid crystal display may be rendered similar to an image viewed from the front of the liquid crystal display, thus increasing side visibility. 
     The third switching element Qc is connected to the second liquid crystal capacitor Clcb and the storage electrode line RL, and thus, the voltage charged in the first liquid crystal capacitor Clca is rendered different from the voltage charged in the second liquid crystal capacitor Clcb. Alternatively, the second liquid crystal capacitor Clcb may be connected to a step-down capacitor. For example, the third switching element may include a first terminal connected to a step-down gate line, a second terminal connected to the second liquid crystal capacitor Clcb, and a third terminal connected to the step-down capacitor, and, a portion of the electric charge charged in the second liquid crystal capacitor Clcb may be charged in the step-down capacitor. Accordingly, the voltage charged in the first liquid crystal capacitor Clcb may be rendered different from the voltage charged in the second liquid crystal capacitor Clcb. In an exemplary embodiment of the present invention, the first liquid crystal capacitor Clcb and the second liquid crystal capacitor Clcb may be connected to different data lines, respectively, and receive different data voltages, respectively. Accordingly, the voltage charged in the first liquid crystal capacitor Clcb may be rendered different from the voltage charged in the second liquid crystal capacitor Clcb. However, exemplary embodiments of the present invention are not limited thereto. Various methods may be used to make the voltage charged in the first liquid crystal capacitor Clcb different from the voltage charged in the second liquid crystal capacitor Clcb. 
       FIG. 6  is a layout view of two pixel of a liquid crystal display according to an exemplary embodiment of the present invention.  FIG. 7  is a cross-sectional view taken along line VII-VII of  FIG. 6 . 
     The liquid crystal display according to an exemplary embodiment includes a lower panel and an upper panel facing each other, a liquid crystal layer interposed between the two panels, and a pair of polarizers respectively attached to outer sides of the panels. 
     A gate conductor including a gate line  121  and a storage electrode line  131  is formed on an insulation substrate  110  made of transparent glass or plastic. 
     The gate line  121  includes a first gate electrode  124   a , a second gate electrode  124   b , a third gate electrode  124   c , and a wide end portion for connection with another layer or an external driving circuit. 
     The storage electrode line  131  includes first storage electrodes  135  and  136  and a reference electrode. Second storage electrodes  138  and  139  are not connected to the storage electrode line  131  and overlap the second subpixel electrode. The second storage electrodes  138  and  139  may be connected to the first storage electrodes  135  and  136  of an underneath adjacent pixel. 
     A gate insulating layer  140  is formed on the gate line  121  and the storage electrode line  131 . 
     A first semiconductor  154   a , a second semiconductor  154   b , and a third semiconductor  154   c  are positioned on the gate insulating layer  140 . 
     A plurality of ohmic contacts is positioned on the semiconductors  154   a ,  154   b , and  154   c.    
     A data conductor including a plurality of data lines  171  including a first source electrode  173   a  and a second source electrode  173   b , a first drain electrode  175   a , a second drain electrode  175   b , a third source electrode  173   c , and a third drain electrode  175   c  is positioned on the ohmic contacts and the gate insulating layer  140 . 
     The data conductor, the semiconductor positioned below the data conductor, and the ohmic contact may be substantially simultaneously formed using one mask. 
     The data line  171  includes a wide end portion for connection with another layer or an external driving circuit. 
     The first gate electrode  124   a , the first source electrode  173   a , and the first drain electrode  175   a , together with the first semiconductor  154   a , form a first thin film transistor (TFT) Qa, and a channel of the thin film transistor is formed in the semiconductor  154   a  between the first source electrode  173   a  and the first drain electrode  175   a . The second gate electrode  124   b , the second source electrode  173   b , and the second drain electrode  175   b , together with the second semiconductor  154   b , form a second thin film transistor Qb, and a channel is formed in the semiconductor  154   b  between the second source electrode  173   b  and the second drain electrode  175   b . The third gate electrode  124   c , the third source electrode  173   c , and the third drain electrode  175   c , together with the third semiconductor  154   c , form a third thin film transistor Qc, and a channel is formed in the semiconductor  154   c  between the third source electrode  173   c  and the third drain electrode  175   c.    
     The second drain electrode  175   b  includes a wide extension  177  connected to the third source electrode  173   c.    
     A first passivation layer  180   p  is positioned on the data conductors  171 ,  173   c ,  175   a ,  175   b , and  175   c  and the exposed portion of the semiconductors  154   a ,  154   b , and  154   c . The first passivation layer  180   p  may include an inorganic insulating layer made of silicon nitride, silicon oxide, or the like. The first passivation layer  180   p  may prevent a pigment of the color filter  230  from flowing into the exposed portion of the semiconductors  154   a ,  154   b , and  154   c.    
     A color filter  230  is positioned on the first passivation layer  180   p . The color filter  230  extends along two adjacent data lines. 
     A second passivation layer is formed on the color filter  230  and the first light blocking member  230 . 
     The second passivation layer may include an inorganic insulating layer made of silicon nitride, silicon oxide, or the like. The second passivation layer prevents the color filter  230  from being lifted and the liquid crystal layer from being contaminated by an inflow of an organic material such as a solvent from the color filter  230 . 
     The first passivation layer  180   p  and the second passivation layer have a first contact hole  185   a  and a second contact hole  185   b  exposing the first drain electrode  175   a  and the second drain electrode  175   b.    
     In the first passivation layer  180   p  and the second passivation layer, and the gate insulating layer  140 , a third contact hole  185   c  exposing a part of the reference electrode and a part of the third drain electrode  175   c  is positioned, and the third contact hole  185   c  is covered by a connecting member. The connecting member electrically connects the reference electrode and the third drain electrode  175   c  exposed by the third contact hole  185   c.    
     A plurality of pixel electrodes  191  are positioned on the second passivation layer  180   q . Each pixel electrode  191  includes a first subpixel electrode and a second subpixel electrode which are separated from each other with the gate line  121  positioned therebetween. The first and second subpixel electrodes are positioned adjacent to each other in a column direction. The pixel electrode  191  may be made of a transparent material such as ITO or IZO. The pixel electrode  191  may be made of a transparent conductive material such as ITO or IZO, or a reflective metal such as aluminum, silver, chromium, or an alloy thereof. 
     The first subpixel electrode and the second subpixel electrode are physically and electrically connected to the first drain electrode  175   a  and the second drain electrode  175   b  through the first contact hole  185   a  and the second contact hole  185   b , respectively receiving data voltages from the first drain electrode  175   a  and the second drain electrode  175   b . In this case, a part of the data voltage applied to the second drain electrode  175   b  is divided by the third source electrode  173   c , and accordingly, a magnitude of the voltage applied to the first subpixel electrode is larger than a magnitude of the voltage applied to the second subpixel electrode. 
     The first subpixel electrode and the second subpixel electrode to which the data voltages are applied and a common electrode  270  of the upper panel generate an electric field, determining directions of the liquid crystal molecules of the liquid crystal layer  3  between the two electrodes. The luminance of light passing through the liquid crystal layer  3  varies according to the determined directions of the liquid crystal molecules. 
     The common electrode  270  is positioned on an insulation substrate  210 . An upper alignment layer is positioned on the common electrode  270 . The upper alignment layer may be a vertical alignment layer. 
     The liquid crystal layer has negative dielectric anisotropy, and the liquid crystal molecules of the liquid crystal layer are aligned so that long axes thereof are substantially perpendicular to the surfaces of the two panels in the absence of an electric field. 
     Referring to  FIG. 7 , in the liquid crystal display according to an exemplary embodiment of the present invention, a shielding electrode  88  is positioned on the data line  171 . The shielding electrode  88  may receive a common voltage and may block electrical interference between the data line  171  and the pixel electrode  191  and between the data line  171  and the common electrode  270 , and thus, a voltage distortion of the pixel electrode  191  and the signal delay of the data voltage transmitted by the data line  171  may be reduced. 
     The thin film transistor array panel according to an exemplary embodiment of the present invention includes the shielding electrode instead of the light blocking member, and thus, a light leakage of the front viewing angle may be prevented. A low reflection metal layer is used as the shielding electrode is used, and thus a deterioration of the contrast ratio may be reduced. 
     While this invention has been shown and described in connection with exemplary embodiments thereof, it is to be understood by those of ordinary skill in the art that various changes in form and detail may be made thereto without departing from the spirit and scope of the present invention as defined by the following claims.