Patent Publication Number: US-6657480-B2

Title: CMOS compatible band gap reference

Description:
CROSS-REFERENCES TO RELATED APPLICATIONS 
     This application claims priority from U.S. Provisional Patent Application No. 60/220,068, filed Jul. 21, 2000, which is incorporated by reference herein. 
    
    
     BACKGROUND OF THE INVENTION 
     The present invention relates to band gap reference circuits, and more particularly, to band gap reference circuits that maintain a constant output voltage over a range of temperature and bias current. 
     A band gap reference circuit provides a constant output reference voltage V REF . Problems may arise if the output reference voltage V REF  varies even by a small amount such as a few hundred millivolts over a range of temperature or bias current. Therefore, it is desirable to provide a band gap reference circuit that provides an output reference voltage V REF  that is substantially constant over a range of temperature and bias current. 
     Previously known standard CMOS band gap reference circuits typically include an amplifier that comprises a differential pair of p-channel MOS transistors. V REF  is determined by the voltage at the gate of one of the p-channel MOS transistors. Excess charge carriers can become trapped in the silicon to silicon dioxide (SiO 2 ) interface in MOS transistors. The excess charge may cause variations in the threshold voltages of the MOS transistors in the differential pair of the amplifier. For example, the threshold voltages of the two MOS transistors in the differential pair may differ by more than 5 mV. This difference introduces an offset voltage into the amplifier which appears at V REF  of the band gap reference circuit. The offset voltage can prevent the band gap reference circuit from being adjusted with trimming resistors so that V REF  remains constant with temperature changes. 
     In addition, the charge trapped in the silicon/SiO 2  interface of the differential pair MOS transistors in the band gap reference amplifier can vary over time causing V REF  to change over time even at a constant temperature. These variations in V REF  cause undesirable 1/f output noise. Also, the p-channel MOS transistors in the differential pair may introduce thermal noise at V REF  due to the nature of MOS transistors, which is also undesirable. 
     A further disadvantage of previously known standard CMOS band gap reference circuits is that they are sensitive to relatively small changes in the supply voltage V CC . Small changes in V CC  cause variations in the bias current through the band gap reference circuit, which can cause undesirable changes in V REF . 
     It would therefore be desirable to provide a less noisy band gap reference circuit in CMOS technology that provides a substantially constant output reference voltage V REF  over a range of supply voltage and a range of temperature. 
     BRIEF SUMMARY OF THE INVENTION 
     The present invention provides CMOS low noise band gap reference circuits that output a substantially constant reference voltage V REF . Band gap reference circuits of the present invention have an amplifier that includes a differential pair of bipolar junction transistors. Each of the bipolar junction transistors are coupled to a first or a second plurality of bipolar junction transistors or a first and second plurality of diodes. The first and second plurality of transistors or diodes are coupled to a plurality of resistors. When the temperature of the circuit varies over a range, the change in the voltage drop across the resistors compensates for the change in the voltage drop across the transistors or the diodes so that V REF  remains substantially constant. 
     A feedback circuit is coupled to the amplifier. The feedback circuit adjusts its current to compensate for variations in the supply current so that the V REF  remains substantially constant. The band gap reference circuits of the present invention provide a output reference voltage V REF  that is substantially constant with variations over a range of temperature and supply voltage. Band gap reference circuits of the present invention may be fabricated using standard CMOS process techniques. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG.  1 . is a schematic of an embodiment of a band gap reference circuit of the present invention; 
     FIGS. 2A-2B illustrate top down and cross sectional layout views, respectively, of a CMOS compatible lateral PNP bipolar junction transistor in accordance with the principles of the present invention; 
     FIG. 2C illustrates a schematic of the lateral PNP BJT of FIGS. 2A-2B; 
     FIGS. 3A-3B illustrate top down and cross sectional layout views, respectively, of a CMOS compatible vertical PNP bipolar junction transistor in accordance with the principles of the present invention; 
     FIG. 3C illustrates a schematic of the vertical PNP bipolar junction transistor of FIGS. 3A-3B; and 
     FIG. 4 is a schematic of another embodiment of a band gap reference circuit of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Band gap reference circuit  10  shown in FIG. 1 is an embodiment of the present invention. Reference circuit  10  receives supply voltage V CC  from an external voltage source. Bias current source  11 , which has a finite impedance, provides a reference current source that outputs a current equal to 15I to reference circuit  10 . For example, 15I may represent 150 μA at 25° C. Bias current source  11  is proportional to absolute temperature. Therefore, changes in the temperature of circuit  10  or changes in V CC  cause the current through current source  11  to vary. 
     The current through bias current source  11  is divided through p-channel MOS transistors M 1 -M 8  and M 11  according to the predetermined proportions which are determined by the relative channel width-to-length (W/L) ratios of MOSFET transistors M 1 -M 8  and M 11 . For example, the W/L ratio of transistors M 1 :M 2 :M 3 :M 4 :M 5 :M 6 :M 7 :M 8  may be 4:1:1:1:1:1:1:1 which provides a current ratio of 4I:I:I:I:I:I:I:I as shown in FIG.  1 . MOS transistor M 11  has a W/L that is eight times the W/L of MOS transistors M 9  and M 10 . Other suitable transistor ratios may be used, if desired, according to the principles of the present invention. In a further embodiment of the present invention, MOSFET transistors M 1 -M 8  may be replaced with PNP bipolar junction transistors that are sized to provide the desired bias current ratio in circuit  10 . 
     Band gap reference circuit  10  includes PNP bipolar junction transistors (BJTs) Q 1  and Q 2 , which from a differential pair for an amplifier. When the voltages at the bases of Q 1  and Q 2  are equal, a current equal to one half of current I (I′/2) flows through both Q 1  and Q 2 , and n-channel MOS transistors M 9  and M 10 , which form a current mirror. 
     Circuit  10  also includes PNP BJTs Q 4 -Q 9 . The base of transistor Q 2  is coupled to the output reference voltage Vref, which is determined by the equation (1). 
     
       
           V   REF   =V   R2   +V   BE-Q9   +V   BE-Q7   +V   BE-Q5   (1)  
       
     
     V R2  is the voltage drop across R 2 , V BE-Q9  equals the base-emitter voltage drop across Q 9 , V BE-Q7  equals the base-emitter voltage drop across Q 7 , and V BE-Q5  equals the base-emitter voltage drop across Q 5 . The voltage at the base of transistor Q 1  is determined by equation (2). 
     
       
           V   Q1   =V   R1   +V   R2   +V   BE-Q8   +V   BE-Q6   +V   BE-Q4   (2)  
       
     
     V Q1  is the base voltage of transistor Q 1 , V R1  is the voltage drop across resistor R 1 , V BE-Q8  equals the base-emitter voltage drop across Q 8 , V BE-Q6  equals the base-emitter voltage drop across Q 6 , and V BE-Q4  equals the base-emitter voltage drop across Q 4 . 
     BJTs Q 1 -Q 9  may be CMOS compatible lateral PNP bipolar junction transistors. FIGS. 2A-2B illustrate top down and cross sectional views of an embodiment of a CMOS compatible lateral PNP bipolar junction transistor that may be used to form BJTs Q 1 -Q 9 . FIG. 2C illustrates a schematic of a lateral PNP BJT. The lateral PNP BJT shown in FIGS. 2A-2B includes a P+ emitter diffusion region, an N-well base region, and a P+ lateral collector diffusion region. The lateral PNP BJT of FIGS. 2A-2B can be made using standard CMOS process techniques that are used to form a p-channel MOSFET transistor. No new layers or process steps are required. The gate terminal in FIGS. 2A-2B is biased so that the parallel PMOS device is kept off. The vertical collector terminal is not used. Lateral PNP BJTs have a relatively high base-to-collector current gain β (e.g., 100). 
     In a further embodiment, BJTs Q 4 -Q 9  may be compatible vertical PNP bipolar junction transistors. FIGS. 3A-3B illustrate top down and cross sectional views of an embodiment of a CMOS compatible vertical PNP bipolar junction transistor that may be used to form BJTs Q 4 -Q 9 . FIG. 3C illustrates a schematic of a vertical PNP BJT. The PNP transistor in FIGS. 3A-3B includes an emitter P+diffusion region, an N-well base region, and a P+ collector region coupled to the P-substrate. Thus, the collector of the vertical PNP BJT is coupled to the P-substrate. Transistors Q 4 -Q 9  can be vertical PNP BJTS, because their collectors are coupled directly to ground. Transistors Q 1 -Q 3  cannot be vertical PNP BJTS, because their collectors are not coupled directly to ground. The vertical PNP BJT of FIGS. 2A-2B can be made using standard CMOS process techniques that are used to form a p-channel MOSFET transistor. Vertical PNP BJTs have a relatively high base-to-collector current gain β (e.g., 500). 
     BJTs Q 4 , Q 6 , and Q 8  have base-emitter junction areas that are 8 times the base emitter junction areas of BJTs Q 5 , Q 7 , and Q 9 . Therefore, base-emitter voltage V BE  of each of transistors Q 4 , Q 6 , and Q 8  are 26 mV·ln(8)=54 mV greater than the base-emitter voltages V BE  of each of transistors Q 5 , Q 7 , and Q 9 . The total voltage drop of V BE-Q8 +V BE-Q6 +V BE-Q4  is 162 mV greater than the total voltage of V BE-Q9 +V BE-Q7 +V BE-Q5 . Therefore, the resistance of resistor R 1  should be selected so that the voltage drop across R 1  equals 162 mV so that the voltage at the base of Q 1  equals the voltage at the base of Q 2 . For example, the voltage drop across R 1  is 162 mV when R 1  is 4.05 kΩ and the current of through R 1  is 40 μA. When the voltages at the bases of Q 1  and Q 2  are equal, circuit  10  is in an equilibrium state and outputs a constant output voltage V REF . 
     When the temperature of circuit  10  increases, the base-emitter junction voltage drops across the bipolar junction transistors Q 5 , Q 7 , and Q 9  decreases, and the voltage drop across resistors R 1  and R 2  increases. When the temperature of circuit  10  decreases, the voltage drop across base-emitter junctions of BJTs Q 5 , Q 7 , and Q 9  increases, and the voltage drop across R 1  and R 2  decreases. If a temperature change in circuit  10  causes a voltage change in V REF  away from a desired value (e.g., 3.6 volts), a trimming resistor can be added in series or in parallel with resistor R 2  to bring V REF  back up to the desired value. The trimming resistor can be coupled to R 2  using fusible links that are isolated with respect to ground to reduce parasitic capacitance. 
     Once circuit  10  has been adjusted to reach a balance point (so that V REF  is at the desired value), then temperature changes over a range (e.g., −40° C.−125° C.) in circuit  10  do not cause voltage changes in V REF . At the balance point of circuit  10 , a change in the voltage drop across the base-emitter junctions of BJTs Q 5 , Q 7 , and Q 9  is offset by a change in the voltage drop across resistor R 1  when the temperature of circuit  10  changes such that the voltage of V REF  remains substantially constant (e.g., within a few millivolts). Therefore, trimming resistance may be added to circuit  10  to achieve a zero temperature coefficient. If desired, resistor R 1  can be selected at a single temperature to achieve the balance point at which V REF  remains constant despite changes in temperature. Highly accurate measurements of resistances may be needed to achieve this result in one step. 
     The base-emitter threshold voltages of BJTs Q 1  and Q 2  are the substantially the same, and therefore a low offset voltage is introduced into V REF . Variations in the base-emitter threshold voltages of BJTs are on the order of 100-1000 times less than variations in the threshold voltages of MOS transistors. Circuit  10  uses triple emitter followers Q 4 /Q 6 /Q 8  and Q 5 /Q 7 /Q 9  that provide a three times increase in the delta V BE  (e.g., 3·54 mV) which reduces the effect of the small input offset voltages and noise voltages that are introduced by Q 1  and Q 2  into V REF . 
     Thus, triple emitter followers Q 4 /Q 6 /Q 8  and Q 5 /Q 7 /Q 9  as shown in FIG. 1 is preferred. However, in a further embodiment, a first double emitter follower is coupled to the base of Q 1  (e.g., by eliminating transistors Q 4  and M 2  in circuit  10 ), and a second double emitter follower is coupled to the base of Q 2  (e.g., by eliminating transistors Q 5  and M 8 ). Also, in another embodiment, only a single BJT is coupled between the base of Q 1  and R 1 , and a single BJT is coupled between the base of Q 2  and R 2  (e.g., by eliminating transistors Q 4 , Q 5 , Q 6 , Q 7 , M 2 , M 3 , M 7  and M 8  in circuit  10 ). 
     BJTs Q 1  and Q 2  emit low thermal noise, and therefore, circuit  10  exhibits noise performance levels comparable with bipolar band-gap reference circuits. In addition, BJTs Q 1  and Q 2  do not contain the trapped charge that often exists in prior art MOS differential pairs. Therefore, V REF  in circuit  10  is stable with time and past use history, and does not contain long term drift components that cause the noise problems associated with variations in trapped charge over time that are caused by MOS differential pairs. 
     In prior art band gap reference circuits that used an amplifier with a p-channel MOS differential pair, an offset voltage may be included in the value of V REF  due to variations in the threshold voltages of the differential pair MOS transistors. V REF  in these circuits is determined by the base-emitter voltage drop across a BJT and the voltage drop across a resistor. When the temperature of the prior art band reference circuit changes, the voltage of V REF  changes from a desired value due to changes in the voltage drops across the resistor and the BJT. The prior art circuits do not reach a balance point when trimming resistors are added to bring V REF  back up to the desired value, because the offset voltage introduced by differential pair MOS transistors is included in V REF . 
     V REF  in the prior art reference circuit cannot remain substantially constant with changing temperature, because it does not reach a point at which the decrease in the voltage drop across the BJT cancels out the increase in voltage drop across the resistor when V REF  is set at the desired value. The offset in V REF  introduced by the differential pair MOS transistors may cause a designer to add trimming resistance that cause V REF  to reach the desired value, but that is to much or too little trimming resistance to reach the balance point at which the effect of temperature changes are canceled out and no longer effect V REF . 
     Circuit  10  of the present invention is also substantially resistant to small first order variations in supply voltage V CC . When V CC  increases, the current output of bias current source  11  increases. A small increase in the current through resistors R 1  and R 2  causes an increase in voltages at the bases of Q 1  and Q 2 . However, the voltage at the base of Q 1  increases more than Q 2 , because the increase in the voltage drop at the base of Q 4  is greater than the voltage drop at the base of Q 5 . Therefore, the current through Q 1  decreases below the current through Q 2 , causing both the gate voltage of M 11  and the current through M 11  to increase. Diode coupled BJT Q 3  is coupled to transistor Ml  11 . The channel width-to-length (W/L) ratio of transistors M 9  and M 10  are designed to be equal. By scaling W/L of M 11  to be eight times the W/L of M 9  or M 10 , VDS of M 10  substantially matches VDS Of M 9 , so that the collector current of Q 3  is approximately eight times larger than the collector current of Q 2  or Q 1 , minimizing any imbalance of Q 1  and Q 2  in the feedback loop. 
     The current through M 11  is several times the magnitude of the current through M 10  and M 9 . The current through M 11  increases as much as the current through current source  11  increases. Therefore, all of the excess current through current source  11  flows through M 11 , and the current through transistors M 1 -M 8  and resistors R 1  and R 2  remains substantially constant. 
     In a further embodiment of the present invention, the ratio of the current through transistor M 11  with respect to the current through transistors M 9 /M 10  may be selected to be any suitable value. For example, MOS transistor M 11  may have a W/L that is 20 times the W/L of MOS transistors M 9  and M 10 . In this embodiment, the current through M 11  is 20 times the current through M 9  and M 10 . 
     When V CC  decreases, the current output of bias current source  11  decreases. The current through M 11  decreases by the same amount that the current through current source  11  decreases. Substantially all of the current drop through current source  11  is subtracted from the current through M 11 , and the current through transistors M 1 -M 8  and resistors R 1  and R 2  again remain substantially constant. Therefore, transistor M 11  is a feedback circuit that regulates its current so that the current through R 1 /R 2  and Q 4 -Q 9  are substantially constant. This is advantageous, because the feedback circuit causes the voltage drop across resistors R 1  and R 2  to remain substantially constant (e.g., 162 mV), the base voltages of Q 1  and Q 2  to remain substantially equal to each other, and the output voltage V REF  to remain substantially constant despite small, first order changes in the current through current source  11 . Thus, circuit  10  is desensitized from first order variations in V CC . 
     With respect to base currents of Q 4  and Q 5 , the base current of Q 4  tends to cancel some but not all of the base current of Q 5 . Therefore, the base current of Q 5  does introduce an error term into the circuit  10  with respect to reaching the balance point at which a zero temperature coefficient is achieved. However, the error term introduced by the base current of Q 5  is relatively small and does effect the zero temperature coefficient much. To further ensure that the error term introduced by the base of Q 5  is small, the impedances of R 1  and R 2  should be low relative to the base current of Q 5 , as is the case in the embodiment of FIG.  1 . Also, Q 5  can be a vertical PNP BJT, which has a relatively high base-to-collector current gain (β), which further reduces the error term introduced by the base current of Q 5 . 
     Parasitic capacitance in the feedback loop of circuit  10  provide sufficient compensation for the loop such that additional frequency compensation need not be added. However, an additional capacitor may be from the base of Q 2  to ground to provide additional noise rejection in V REF . 
     Band gap reference circuit  40  shown in FIG. 4 is a further embodiment of the present invention. Circuit  40  includes p-channel MOSFETs M 4 -M 6 , n-channel MOSFETs M 9 -M 11 , resistors R 1  and R 2 , current source  11 , and PNP BJTs Q 1  and Q 2 , as with the embodiment of FIG.  1 . Circuit  40  also includes diodes  41 - 46  in place of BJTs Q 4 -Q 9 . Current source  11  outputs a current equal to 7I. Current source  11  provides a current I to each of MOSFETs M 4 -M 6 . A current substantially equal to I flows through diodes  41 - 43  and resistors R 1  and R 2 . A current substantially equal to I also flows through diodes  44 - 46  and resistor R 2 . A total current of  2 I flows through R 2 . 
     In circuit  40 , diodes  41 - 43  have P-N junction areas that are eight times the P-N junction areas of diodes  44 - 46 . Also, Q 1  has a base-emitter junction area that is eight times the base emitter junction area of Q 2 . Therefore, R 1  should be selected to have a voltage drop of 54 mV·4=216 mV to compensate for the fact that the voltage drop across Q 1  and diodes  41 - 43  is 216 mV greater than the voltage drop across Q 2  and diodes  44 - 46 . 
     A current of  4 I flows through transistor M 11 . Transistor M 11  has a W/L ratio that is eight times the W/L ratio of each of transistors M 9  and M 10 . The feedback circuit comprising M 11  and Q 3  ensure that a current equal to I/2 flows through each of transistors M 9  and M 10 . 
     The resistance at R 2  may be selected to achieve a desired value at V REF . R 2  may be trimmed to achieve a zero temperature coefficient at which point output signal V REF  remains constant over a range of temperature as discussed above with respect to FIG.  1 . 
     In a further embodiment of the present invention, diodes  43  and  46  in circuit  40  may be eliminated, so that the base of Q 1  is coupled directly to diode  42  and the base of Q 2  is coupled directly to diode  45 . In another further embodiment of the present invention, diodes  42 - 43  and diodes  45 - 46  may be eliminated, so that the base of Q 1  is coupled directly to diode  41 , and the base of Q 2  is coupled directly to the diode  44 . In still a further embodiment of the present invention, transistor Q 4  in circuit  10  may be replaced with diode  41 , eliminating transistor M 1 , and transistor Q 5  in circuit  10  may be replaced with diode  44 . 
     In still a further embodiment of the present invention, PNP BJTs Q 1 -Q 2  and BJTs Q 4 -Q 9  may be replaced with NPN bipolar junction transistors. PNP BJT Q 3  may also be replaced with a NPN BJT. 
     While the present invention has been described herein with reference to particular embodiments thereof, a latitude of modification, various changes and substitutions are intended in the foregoing disclosure, and it will be appreciated that in some instances some features of the invention will be employed without a corresponding use of other features without departing from the scope of the invention as set forth. Therefore, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from the essential scope and spirit of the present invention. It is intended that the invention not be limited to the particular embodiments disclosed, but that the invention will include all embodiments and equivalents falling within the scope of the claims.