Patent Publication Number: US-2023162674-A1

Title: Pixel circuit, driving method, display substrate and display device

Description:
TECHNICAL FIELD 
     The present disclosure relates to the field of display technologies, and in particular to a pixel circuit, a driving method, a display substrate, and a display device. 
     BACKGROUND 
     As the active matrix organic light emitting diode (Active Matrix Organic light Emitting Diode, AMOLED) display technology continuously develops, in order to adapt to a more complex display environment, pixel definition layers (PDL) are gradually increased, resulting in gradually decreased gaps (PDL Gap) among the pixel definition layers. In addition, efficiency of the organic light emitting diode (OLED) device is gradually improved and its turn-on voltage is reduced. The above factors cause the anode node of the OLED device to get more and more attention. 
     SUMMARY 
     In an aspect, embodiments of the present disclosure provide a pixel circuit, including a driving circuit, a first light-emitting control circuit, a light-emitting element, a first initialization circuit, and a second initialization circuit; 
     where the driving circuit is configured to generate, under the control of a control terminal of the driving circuit, a driving current for driving the light-emitting element, and a cathode of the light-emitting element is electrically connected to a first voltage line;   where the first light-emitting control circuit is electrically connected to a light-emitting control line, the driving circuit, and an anode of the light-emitting element, and is configured to control, under the control of a light-emitting control signal provided by the light-emitting control line, the driving circuit to be connected to or disconnected from the anode of the light-emitting element;   where the first initialization circuit is electrically connected to a first initialization control line, the control terminal of the driving circuit, and an initialization voltage line, and is configured to write, under the control of a first initialization control signal provided by the first initialization control line, an initialization voltage provided by the initialization voltage line, to the control terminal of the driving circuit;   where the second initialization circuit is electrically connected to a second initialization control line, the anode of the light-emitting element, and an initial data line, and is configured to write, under the control of a second initialization control signal provided by the second initialization control line, an initial data voltage provided by the initial data line, to the anode of the light-emitting element.   

     Optionally, the second initialization circuit includes a first transistor; 
     where a gate electrode of the first transistor is electrically connected to the second initialization control line, a first electrode of the first transistor is electrically connected to the initial data line, and a second electrode of the first transistor is electrically connected to the anode of the light-emitting element. 
     Optionally, the first initialization circuit includes a second transistor; 
     where a gate electrode of the second transistor is electrically connected to the first initialization control line, a first electrode of the second transistor is electrically connected to the initialization voltage line, and a second electrode of the second transistor is electrically connected to the control terminal of the driving circuit. 
     Optionally, the pixel circuit described in at least one embodiment of the present disclosure further includes a second light-emitting control circuit, a storage circuit, a data writing circuit, and a compensation circuit, where the first light-emitting control circuit is electrically connected to a second terminal of the driving circuit; 
     where the second light-emitting control circuit is electrically connected to the light-emitting control line, a second voltage line, and a first terminal of the driving circuit, and is configured to control, under the control of the light-emitting control signal, the first terminal of the driving circuit to be connected to or disconnected from the second voltage line;   where the storage circuit is electrically connected to the control terminal of the driving circuit, and is configured to maintain a potential of the control terminal of the driving circuit;   where the data writing circuit is electrically connected to the gate line, a display data line, and the first terminal of the driving circuit, and is configured to write, under the control of a gate driving signal, a display data voltage on the display data line, to the first terminal of the driving circuit;   where the compensation circuit is electrically connected to the gate line, the control terminal of the driving circuit, and the second terminal of the driving circuit, and is configured to control, under the control of the gate driving signal, the control terminal of the driving circuit to be connected to or disconnected from the second terminal of the driving circuit.   

     Optionally, the driving circuit includes a driving transistor, a gate electrode of the driving transistor is the control terminal of the driving circuit, a first electrode of the driving transistor is the first terminal of the driving circuit, and a second electrode of the driving transistor is the second terminal of the driving circuit; 
     where the first light-emitting control circuit includes a third transistor; a gate electrode of the third transistor is electrically connected to the light-emitting control line, a first electrode of the third transistor is electrically connected to the second electrode of the driving transistor, and a second electrode of the third transistor is electrically connected to the anode of the light-emitting element;   where the second light-emitting control circuit includes a fourth transistor, a gate electrode of the fourth transistor is electrically connected to the light-emitting control line, a first electrode of the fourth transistor is electrically connected to the second voltage line, and a second electrode of the fourth transistor is electrically connected to the first electrode of the driving transistor;   where the storage circuit includes a storage capacitor, a first electrode plate of the storage capacitor is electrically connected to the gate electrode of the driving transistor, and a second electrode plate of the storage capacitor is electrically connected to the second voltage line;   where the data writing circuit includes a fifth transistor, a gate electrode of the fifth transistor is electrically connected to the gate line, a first electrode of the fifth transistor is electrically connected to the display data line, and a second electrode of the fifth transistor is electrically connected to the first electrode of the driving transistor;   where the compensation circuit includes a sixth transistor, a gate electrode of the sixth transistor is electrically connected to the gate line, a first electrode of the sixth transistor is electrically connected to the gate electrode of the driving transistor, and a second electrode of the sixth transistor is electrically connected to the second electrode of the driving transistor.   

     In a second aspect, embodiments of the present disclosure also provide a driving method, which is applied to the above-mentioned pixel circuit, and the driving method includes: 
     writing, by the first initialization circuit, under the control of the first initialization control signal, the initialization voltage provided by the initialization voltage line, to the control terminal of the driving circuit; and writing, by the second initialization circuit, under the control of the second initialization control signal, the initial data voltage provided by the initial data line, to the anode of the light-emitting element. 
     Optionally, the pixel circuit further includes a data writing circuit, the pixel circuit is included in a display panel, and the driving method further includes: writing, by the data writing circuit, a display data voltage on a display data line to the driving circuit, under the control of a gate driving signal on a gate line; wherein: 
     a minimum display data voltage among all display data voltage connected to all pixel circuits in the display panel is greater than a predetermined gray-scale voltage, and the initial data voltage is the same as a first voltage provided by the first voltage line; or,   a minimum display data voltage among all display data voltage connected to all pixel circuits in the display panel is less than a predetermined gray-scale voltage, the initial data voltage is different from a first voltage provided by the first voltage line, an absolute value of a difference between the initial data voltage and the first voltage is less than a predetermined voltage value, the difference between the initial data voltage and the first voltage is smaller than a turn-on voltage of the light-emitting element, and the predetermined voltage value is a positive value.   

     In a third aspect, embodiments of the present disclosure also provide a display substrate, which includes a base substrate and the above-mentioned pixel circuit on the base substrate. 
     Optionally, the pixel circuit includes a driving transistor and a storage capacitor, and the display substrate further includes an initial data line on the base substrate; 
     where a gate electrode of the driving transistor is further used as a first electrode plate of the storage capacitor;   where the initial data line and the gate electrode of the driving transistor are in a same layer and are made of a same material, or, the initial data line and a second electrode plate of the storage capacitor are in a same layer and are made of a same material.   

     Optionally, the display substrate further includes a gate line on the base substrate; 
     where an extension direction of the initial data line is the same as an extension direction of the gate line. 
     Optionally, the display substrate further includes a display data line on the base substrate; 
     where the initial data line and the display data line are in a same layer and are made of a same material, or, the initial data line is on a side of the display data line away from the base substrate. 
     Optionally, an extension direction of the initial data line is the same as an extension direction of the display data line. 
     Optionally, the pixel circuit includes a first transistor, and the display substrate further includes the second initialization control line and the initial data line on the base substrate; 
     where a gate electrode of the first transistor and a gate electrode of the driving transistor are in a same layer and are made of a same material, and the gate electrode of the first transistor is electrically connected to the second initialization control line;   where a first electrode of the first transistor, a second electrode of the first transistor, a first electrode of the driving transistor, and a second electrode of the driving transistor are in a same layer and are made of a same material;   where the first electrode of the first transistor is electrically connected to the initial data line, and the second electrode of the first transistor is electrically connected to the anode of the light-emitting element.   

     Optionally, the pixel circuit includes a driving transistor and a storage capacitor; 
     where a gate electrode of the driving transistor is further used as a first electrode plate of the storage capacitor;   where the initialization voltage line and the gate electrode of the driving transistor are in a same layer and are made of a same material, or, the initialization voltage line and a second electrode plate of the storage capacitor are in a same layer and are made of a same material.   

     Optionally, the display substrate further includes a gate line on the base substrate; 
     where an extension direction of the initialization voltage line is the same as an extension direction of the gate line. 
     In a fourth aspect, embodiments of the present disclosure also provide a display device including the above-mentioned display substrate. 
     Optionally, the display device described in at least one embodiment of the present disclosure further includes a driving chip and an initial data wire, a first voltage line and a second voltage wire, where the initial data wire, the first voltage line and the second voltage wire are outside an active area of the base substrate; 
     where the initial data wire includes a first initial data wire portion directly electrically connected to the driving chip;   where the first voltage line includes a first voltage line portion directly electrically connected to the driving chip, and the second voltage wire includes a first voltage wire portion directly electrically connected to the driving chip;   where the first initial data wire portion is between the first voltage line portion and the first voltage wire portion.   

     Optionally, the first initial data wire portion, the first voltage line portion, and the first voltage wire portion all extend in a second direction; 
     where the second direction is a direction in which the display data line extends. 
     Optionally, the display device according to at least one embodiment of the present disclosure further includes a driving chip, an initial data wire, an initialization voltage wire, a first voltage line, and a second voltage wire, where the initial data wire, the initialization voltage wire, the first voltage line, and the second voltage wire are outside an active area of the base substrate; 
     where the initial data wire includes a first initial data wire portion directly electrically connected to the driving chip;   where the initialization voltage wire includes a first initialization voltage wire portion directly electrically connected to the driving chip;   where the first voltage line includes a first voltage line portion directly electrically connected to the driving chip, and the second voltage wire includes a first voltage wire portion directly electrically connected to the driving chip;   where the first initialization voltage wire portion, the first initial data wire portion, the first voltage line portion, and the first voltage wire portion are sequentially in a direction toward the active area.   

    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG.  1    is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; 
         FIG.  2    is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; 
         FIG.  3    is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; 
         FIG.  4    is a schematic diagram of layout of a pixel circuit according to at least one embodiment of the present disclosure; 
         FIG.  5    is a structural diagram of an active layer in  FIG.  4   ; 
         FIG.  6    is a structural diagram of a first gate metal layer in  FIG.  4   ; 
         FIG.  7    is a structural diagram of a second gate metal layer in  FIG.  4   ; 
         FIG.  8    is a schematic diagram of a via hole in  FIG.  4   ; 
         FIG.  9    is a schematic diagram of a structure of a first source and drain metal layer in  FIG.  4   ; 
         FIG.  10    is a schematic diagram of layout of a pixel circuit according to at least one embodiment of the present disclosure; 
         FIG.  11    is a structural diagram of a second gate metal layer in  FIG.  10   ; 
         FIG.  12    is a schematic diagram of an via hole in  FIG.  10   ; 
         FIG.  13    is a structural diagram of a second source and drain metal layer in  FIG.  10   ; 
         FIG.  14    is a structural diagram of a display device according to at least one embodiment of the present disclosure; and 
         FIG.  15    is a structural diagram of a display device according to at least one embodiment of the present disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     Technical solutions of the embodiments of the present disclosure will be clearly and completely described hereinafter with reference to the accompanying drawings of the embodiments of the present disclosure. Apparently, the described embodiments are a part rather than all of the embodiments of the present disclosure. Based on the described embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative efforts fall within the protection scope of the present disclosure. 
     Transistors used in all the embodiments of the present disclosure may be triodes, thin film transistors or field effect transistors or other devices with the same characteristics. In the embodiments of the present disclosure, in order to distinguish two electrodes of a transistor other than a control electrode, one of the two electrodes is referred to as a first electrode, and the other of the two electrodes is referred to as a second electrode. 
     In actual operations, when the transistor is a triode, the control electrode may be a base electrode, the first electrode may be a collector electrode, and the second electrode may be an emitter electrode; or, the control electrode may be a base electrode, the first electrode may be an emitter electrode, and the second electrode may be a collector electrode. 
     In actual operations, when the transistor is a thin film transistor or a field effect transistor, the control electrode may be a gate electrode, the first electrode may be a source electrode, and the second electrode may be a drain electrode; or, the control electrode may be a gate electrode, the first electrode may be a drain electrode, and the second electrode may be a source electrode. 
     As shown in  FIG.  1   , a pixel circuit according to at least one embodiment of the present disclosure includes a driving circuit  11 , a first light-emitting control circuit  12 , a light-emitting element EL, a first initialization circuit  13 , and a second initialization circuit  14 . 
     The driving circuit  11  is configured to generate, under the control of a control terminal of the driving circuit, a driving current for driving the light-emitting element EL, and a cathode of the light-emitting element is electrically connected to a first voltage line V 1 . 
     The first light-emitting control circuit  12  is electrically connected to a light-emitting control line E 1 , the driving circuit  11 , and an anode of the light-emitting element EL, and is configured to control, under the control of a light-emitting control signal provided by the light-emitting control line E 1 , the driving circuit  11  to be connected to or disconnected from the anode of the light-emitting element EL. 
     The first initialization circuit  13  is electrically connected to a first initialization control line R 1 , the control terminal of the driving circuit  11 , and an initialization voltage line I 1 , and is configured to write, under the control of a first initialization control signal provided by the first initialization control line R 1 , an initialization voltage provided by the initialization voltage line I 1 , to the control terminal of the driving circuit  11 . 
     The second initialization circuit  14  is electrically connected to a second initialization control line R 2 , the anode of the light-emitting element EL, and an initial data line D 02 , and is configured to write, under the control of a second initialization control signal R 2  provided by the second initialization control line, an initial data voltage provided by the initial data line D 02 , to the anode of the light-emitting element EL. 
     In the pixel circuit described in at least one embodiment of the present disclosure, the initialization voltage is written to the control terminal of the driving circuit  11  via the first initialization circuit  13 , to initialize the control terminal of the driving circuit  11 , and the initial data voltage is written to the anode of the light-emitting element EL via the second initialization circuit  14 , to initialize the anode of the light-emitting element EL. By adjusting the initial data voltage, light emission of the light-emitting element from a leakage current, and lateral leakage at low gray scales, which are caused when initializing the anode of the light-emitting element, can be prevented. 
     Optionally, the first initialization control line and the second initialization control line may be a same initialization control line; or, the first initialization control line and the second initialization control line may be different. 
     In at least one embodiment of the present disclosure, the pixel circuit is included in a display substrate, and the display substrate includes a base substrate, multiple rows of gate lines, multiple columns of display data lines, and multiple rows and multiple columns of pixel circuits, where the multiple rows of gate lines, the multiple columns of display data lines, and the multiple rows and multiple columns of pixel circuits are provided on the base substrate; 
     the n-th row of pixel circuits is electrically connected to the n-th row of first initialization control line and the n-th row of gate line; n is a positive integer; the n-th row of first initialization control line and the n-th row of second initialization control line are a same initialization control line;   the n-th row of first initialization control signal on the n-th row of first initialization control line is the same as the (n-1)-th row of gate driving signal on the (n-1)-th row of gate line;   n is a positive integer.   

     In at least one embodiment of the present disclosure, the pixel circuit is included in a display substrate, and the display substrate includes a base substrate, multiple rows of gate lines, multiple columns of display data lines, and multiple rows and multiple columns of pixel circuits, where the multiple rows of gate lines, the multiple columns of display data lines, and the multiple rows and multiple columns of pixel circuits are provided on the base substrate; 
     the n-th row of pixel circuits is electrically connected to the n-th row of first initialization control line, the n-th row of the second initialization control line, and the n-th row of gate line; n is a positive integer; the n-th row of first initialization control line and the n-th row of second initialization control line are different initialization control lines;   the n-th row of first initialization control signal on the n-th row of first initialization control line is the same as the (n-1)-th row of gate driving signal on the (n-1)-th row of gate line;   the n-th row of second initialization control signal on the n-th row of second initialization control line is the same as the n-th row of gate driving signal on the n-th row of gate line;   n is a positive integer.   

     In specific implementations, the rows of pixel circuits included in the display substrate may be sequentially arranged along an extension direction of the display data lines. For example, the rows of pixel circuits may be sequentially arranged in a direction toward a side of the display substrate where the driving chip is provided, and the present disclosure is not limited thereto. 
     Optionally, the first voltage line may be a ground line or a low-voltage signal line, and the present disclosure is not limited thereto. 
     In at least one embodiment of the present disclosure, the light-emitting element EL may be an OLED (Organic Light-Emitting Diode), and the present disclosure is not limited thereto. 
     Optionally, the second initialization circuit includes a first transistor; 
     a gate electrode of the first transistor is electrically connected to the second initialization control line, a first electrode of the first transistor is electrically connected to the initial data line, and a second electrode of the first transistor is electrically connected to the anode of the light-emitting element. 
     Optionally, the first initialization circuit includes a second transistor; 
     a gate electrode of the second transistor is electrically connected to the first initialization control line, a first electrode of the second transistor is electrically connected to the initialization voltage line, and a second electrode of the second transistor is electrically connected to the control terminal of the driving circuit. 
     As shown in  FIG.  2   , based on at least one embodiment of the pixel circuit shown in  FIG.  1   , the pixel circuit further includes a second light-emitting control circuit  21 , a storage circuit  22 , a data writing circuit  23 , and a compensation circuit  24 , where the first light-emitting control circuit  12  is electrically connected to a second terminal of the driving circuit  11 . 
     The second light-emitting control circuit  21  is electrically connected to the light-emitting control line E 1 , a second voltage line V 2 , and a first terminal of the driving circuit  11 , and is configured to control, under the control of the light-emitting control signal, the first terminal of the driving circuit  11  to be connected to or disconnected from the second voltage line V 2 . 
     The storage circuit  22  is electrically connected to the control terminal of the driving circuit  11 , and is configured to maintain a potential of the control terminal of the driving circuit  11 . 
     The data writing circuit  23  is electrically connected to the gate line G 0 , a display data line D 01 , and the first terminal of the driving circuit  11 , and is configured to write, under the control of a gate driving signal, a display data voltage on the display data line D 01 , to the first terminal of the driving circuit  11 . 
     The compensation circuit  24  is electrically connected to the gate line G 0 , the control terminal of the driving circuit  11 , and the second terminal of the driving circuit  11 , and is configured to control, under the control of the gate driving signal, the control terminal of the driving circuit  11  to be connected to or disconnected from the second terminal of the driving circuit  11 . 
     In at least one embodiment of the present disclosure, the second voltage line may be a high-voltage signal line, and the present disclosure is not limited thereto. 
     The pixel circuit described in at least one embodiment of the present disclosure may further include the second light-emitting control circuit  21 , the storage circuit  22 , the data writing circuit  23 , and the compensation circuit  24 . The second light-emitting control circuit  21  controls the first terminal of the driving circuit  11  to be connected to or disconnected from the second voltage line V 2 , the storage circuit  22  maintains the potential of the control terminal of the driving circuit  11 , the data writing circuit  23  controls the writing of the display data voltage to the first terminal of the driving circuit  11 , and the compensation circuit  24  controls the compensation of the threshold voltage of the driving transistor included in the driving circuit  11 . 
     Optionally, the driving circuit includes a driving transistor, a gate electrode of the driving transistor is the control terminal of the driving circuit, a first electrode of the driving transistor is the first terminal of the driving circuit, and a second electrode of the driving transistor is the second terminal of the driving circuit; 
     the first light-emitting control circuit includes a third transistor; a gate electrode of the third transistor is electrically connected to the light-emitting control line, a first electrode of the third transistor is electrically connected to the second electrode of the driving transistor, and a second electrode of the third transistor is electrically connected to the anode of the light-emitting element;   the second light-emitting control circuit includes a fourth transistor, a gate electrode of the fourth transistor is electrically connected to the light-emitting control line, a first electrode of the fourth transistor is electrically connected to the second voltage line, and a second electrode of the fourth transistor is electrically connected to the first electrode of the driving transistor;   the storage circuit includes a storage capacitor, a first electrode plate of the storage capacitor is electrically connected to the gate electrode of the driving transistor, and a second electrode plate of the storage capacitor is electrically connected to the second voltage line;   the data writing circuit includes a fifth transistor, a gate electrode of the fifth transistor is electrically connected to the gate line, a first electrode of the fifth transistor is electrically connected to the display data line, and a second electrode of the fifth transistor is electrically connected to the first electrode of the driving transistor;   the compensation circuit includes a sixth transistor, a gate electrode of the sixth transistor is electrically connected to the gate line, a first electrode of the sixth transistor is electrically connected to the gate electrode of the driving transistor, and a second electrode of the sixth transistor is electrically connected to the second electrode of the driving transistor.   

     As shown in  FIG.  3   , based on at least one embodiment of the pixel circuit shown in the figure, the light-emitting element is an organic light emitting diode O 1 ; the driving circuit  11  includes a driving transistor T 7 . 
     The second initialization circuit includes a first transistor T 1 . 
     A gate electrode G 1  of the first transistor T 1  is electrically connected to the second initialization control line R 2 , a first electrode S 1  of the first transistor T 1  is electrically connected to the initial data line D 02 , and a second electrode D 1  of the first transistor T 1  is electrically connected to the anode of O 1 . 
     The first initialization circuit includes a second transistor T 2 . 
     A gate electrode G 2  of the second transistor T 2  is electrically connected to the first initialization control line R 1 , a first electrode S 2  of the second transistor T 2   is electrically connected to the initialization voltage line I 1 , and a second electrode D 2  of the second transistor T 2  is electrically connected to the control terminal of the driving circuit. 
     A gate electrode G 7  of the driving transistor T 7  is the control terminal of the driving circuit  11 , a first electrode S 7  of the driving transistor T 7  is the first terminal of the driving circuit  11 , and a second electrode D 7  of the driving transistor T 7  is the second terminal of the driving circuit  11 . 
     The first light-emitting control circuit includes a third transistor T 3 . 
     A gate electrode G 3  of the third transistor T 3  is electrically connected to the light-emitting control line E 1 , a first electrode S 3  of the third transistor T 3  is electrically connected to the second electrode D 7  of the driving transistor T 7 , and a second electrode D 3  of the third transistor T 3  is electrically connected to the anode of O 1 . 
     The second light-emitting control circuit includes a fourth transistor T 4 . 
     A gate electrode G 4  of the fourth transistor T 4  is electrically connected to the light-emitting control line E 1 , a first electrode S 4  of the fourth transistor T 4  is electrically connected to the second voltage line V 2 , and a second electrode D 4  of the fourth transistor T 4  is electrically connected to the first electrode S 7  of the driving transistor T 7 . 
     The storage circuit includes a storage capacitor C 1 , a first electrode plate C 1   a  of the storage capacitor C 1  is electrically connected to the gate electrode G 7  of the driving transistor T 7 , and a second electrode plate C 1   b  of the storage capacitor C 1  is electrically connected to the second voltage line V 2 . 
     The data writing circuit includes a fifth transistor T 5 , a gate electrode G 5  of the fifth transistor T 5  is electrically connected to the gate line G 0 , a first electrode of the fifth transistor is electrically connected to the display data line D 01 , and a second electrode of the fifth transistor is electrically connected to the first electrode of the driving transistor. 
     The compensation circuit includes a sixth transistor T 6 , a gate electrode G 6  of the sixth transistor T 6  is electrically connected to the gate line G 0 , a first electrode S 6  of the sixth transistor T 6  is electrically connected to the gate electrode G 7  of the driving transistor T 7 , and a second electrode D 6  of the sixth transistor T 6  is electrically connected to the second electrode D 7  of the driving transistor T 7 . 
     In at least one embodiment of the pixel circuit shown in  FIG.  3   , all the transistors are p-type thin film transistors, and the present disclosure is not limited thereto. 
     In at least one embodiment of the pixel circuit shown in  FIG.  3   , the second initialization control signal on R 2  is the same as the gate driving signal on G 0 , and the present disclosure is not limited thereto. 
     When at least one embodiment of the pixel circuit shown in  FIG.  3    of the present disclosure is in operation, a display period includes an initialization phase, a data writing phase, and a light-emitting phase that are sequentially arranged. 
     In the initialization phase, R 1  provides a low-voltage signal, E 1 , G 0 , and R 2  each provide a high-voltage signal, T 2  is turned on, T 1 , T 5 , T 3 , T 4 , T 6  are all turned off, and I 1  provides the initialization voltage signal to the gate electrode of T 7  to cause T 7  to be turned off. 
     In the data writing phase, R 1  provides a high-voltage signal, G 0  and R 2  each provide a low-voltage signal, E 1  provides a high-voltage signal, T 1 , T 5  and T 6  are all turned on, T 2 , T 3  and T 4  are all turned off, and D 02  provides the initial data voltage to the anode of O 1  to cause O 1  not to emit light; D 01  provides the display data voltage Vd to S 7 , and the connection between G 7  and D 7  is turned on, to perform data voltage writing and compensation of the threshold voltage of T 7 . 
     In the light-emitting phase, R 1 , G 0 , and R 2  each provide a high-voltage signal, E 1  provides a low-voltage signal, T 1 , T 2 , T 5 , and T 6  are all turned off, T 3  and T 4  are turned on, and T 7  drives O 1  to emit light. 
     A driving method described in at least one embodiment of the present disclosure is applied to the above-mentioned pixel circuit, and the driving method includes: 
     writing, by the first initialization circuit, under the control of the first initialization control signal, the initialization voltage provided by the initialization voltage line, to the control terminal of the driving circuit; and   writing, by the second initialization circuit, under the control of the second initialization control signal, the initial data voltage provided by the initial data line, to the anode of the light-emitting element.   

     In the driving method described in at least one embodiment of the present disclosure, the initialization voltage is written to the control terminal of the driving circuit  11  via the first initialization circuit to initialize the control terminal of the driving circuit, and the initial data voltage is written to the anode of the light-emitting element via the second initialization circuit to initialize the anode of the light-emitting element. By adjusting the initial data voltage, light emission of the light-emitting element from a leakage current, and lateral leakage at low gray scales, which are caused when initializing the anode of the light-emitting element, can be prevented. 
     In specific implementations, the pixel circuit may further include a data writing circuit, and the pixel circuit is included in a display panel (the display panel may include the display substrate), and the driving method may further include: 
     writing, by the data writing circuit, a display data voltage on a display data line to the first terminal of the driving circuit, under the control of a gate driving signal;   a minimum display data voltage among all display data voltage connected to all pixel circuits in the display panel is greater than a predetermined gray-scale voltage, and the initial data voltage is the same as a first voltage provided by the first voltage line; or,   a minimum display data voltage among all display data voltage connected to all pixel circuits in the display panel is less than a predetermined gray-scale voltage, the initial data voltage is different from a first voltage provided by the first voltage line, an absolute value of a difference between the initial data voltage and the first voltage is less than a predetermined voltage value, the difference between the initial data voltage and the first voltage is smaller than a turn-on voltage of the light-emitting element, and the predetermined voltage value is a positive value.   

     In at least one embodiment of the present disclosure, the predetermined gray-scale voltage and the predetermined voltage value may be selected according to actual conditions. For example, the predetermined gray-scale voltage may be a gray-scale voltage corresponding to L 32 , and the present disclosure is not limited thereto. 
     In at least one embodiment of the present disclosure, the initial data voltage is set according to the minimum display data voltage connected to the pixel circuits of the display panel. 
     When the minimum display data voltage is relatively large, the initial data voltage is set to be the same as the first voltage. In this way, when initializing the anode of the light-emitting element, it can be ensured that the light-emitting element does not emit light, which prevents light emission of the light-emitting element caused by leakage. 
     When the minimum display data voltage is relatively small, according to the actual situation, the initial data voltage is set to be slightly larger than the first voltage, or, the initial data voltage is set to be slightly smaller than the first voltage, to improve the situation of lateral leakage in the case of low gray scales, and the difference between the initial data voltage and the first voltage is less than the turn-on voltage of the light-emitting element, to ensure that the light-emitting element does not emit light when initializing the anode of the light-emitting element. 
     In the embodiments of the present disclosure, a display period may include an initialization phase, a data writing phase, and a light-emitting phase that are sequentially arranged. 
     When R 1  and R 2  are different initialization control lines, in the initialization phase, the first initialization circuit controls, under the control of the first initialization control signal, the initialization voltage provided by the initialization voltage line, to be written to the control terminal of the driving circuit; in the data writing phase, the second initialization circuit controls, under the control of the second initialization control signal, the initial data voltage provided by the initial data line, to be written to the anode of the light-emitting element, and the data writing circuit writes, under the control of the gate driving signal, the display data voltage on the display data line, to the first terminal of the driving circuit. 
     When R 1  and R 2  are the same initialization control line, in the initialization phase, the first initialization circuit controls, under the control of the first initialization control signal, the initialization voltage provided by the initialization voltage line, to be written to the control terminal of the driving circuit, the second initialization circuit controls, under the control of the second initialization control signal, the initial data voltage provided by the initial data line, to be written to the anode of the light-emitting element; in the data writing stage, the data writing circuit writes, under the control of the gate driving signal, the display data voltage on the display data line, to the first terminal of the driving circuit. 
     A display substrate according to at least one embodiment of the present disclosure includes a base substrate and the above-mentioned pixel circuit provided on the base substrate. 
     Optionally, the pixel circuit includes a driving transistor and a storage capacitor, and the display substrate further includes an initial data line arranged on the base substrate. 
     A gate electrode of the driving transistor is also used as a first electrode plate of the storage capacitor. 
     The initial data line and the gate electrode of the driving transistor are arranged in a same layer and are made of a same material, or, the initial data line and a second electrode plate of the storage capacitor are arranged in a same layer and are made of a same material. 
     In at least one embodiment of the present disclosure, the display substrate may include an active layer, a first gate metal layer, a second gate metal layer, and a first source and drain metal layer that are sequentially disposed on the base substrate. 
     A patterning process may be performed on the first gate metal layer to form the gate lines and the gate electrode of each transistor, and a patterning process may be performed on the second gate metal layer to form the second electrode plate of the storage capacitor; the initial data line and the gate electrode of each transistor may be arranged in a same layer and made of a same material, or, the initial data line and the second electrode plate of the storage capacitor may be arranged in a same layer and made of a same material. That is, the initial data line may be formed in the first gate metal layer or the second gate metal layer. 
     In specific implementations, when the initial data line is formed in the first gate metal layer or the second gate metal layer, the display substrate further includes a gate line disposed on the base substrate. 
     An extension direction of the initial data line is the same as an extension direction of the gate line. 
     In at least one embodiment of the present disclosure, the extension direction of the initial data line being the same as the extension direction of the gate line may refer to that: the extension direction of the initial data line is exactly the same as the extension direction of the gate line, or, an angle between the extension direction of the initial data line and the extension direction of the gate line is less than a predetermined angle to cause the extension direction of the initial data line to be substantially the same as the extension direction of the gate line; and the present disclosure is not limited thereto. 
     Optionally, the display substrate further includes a display data line arranged on the base substrate. 
     The initial data line and the display data line are arranged in a same layer and made of a same material, or, the initial data line is arranged on a side of the display data line facing away from the base substrate. 
     In at least one embodiment of the present disclosure, the display substrate may include an active layer, a first gate metal layer, a second gate metal layer, and a first source and drain metal layer that are sequentially disposed on the base substrate. A patterning process may be performed on the first source and drain metal layer to form the display data line and the initial data line, and the initial data line and the display data line may be arranged in a same layer and made of a same material, that is, the initial data line is formed in the first source and drain metal layer; or, 
     the display substrate may include an active layer, a first gate metal layer, a second gate metal layer, a first source and drain metal layer, and a second source and drain metal layer that are sequentially disposed on the base substrate. A patterning process may be performed on the first source and drain metal layer to form the display data line, and a patterning process may be performed on the second source and drain metal layer to form the initial data line, that is, the initial data line is disposed on a side of the display data line facing away from the base substrate, and the initial data line is formed in the second source and drain metal layer. 
     In specific implementations, when the initial data line is formed in the first source and drain metal layer or the second source and drain metal layer, an extension direction of the initial data line may be the same as an extension direction of the display data line. 
     In at least one embodiment of the present disclosure, the extension direction of the initial data line being the same as the extension direction of the display data line may refer to that: the extension direction of the initial data line is completely the same as the extension direction of the display data line, or, an angle between the extension direction of the initial data line and the extension direction of the display data line is less than a predetermined angle to cause the extension direction of the initial data line to be substantially the same as the extension direction of the display data line; and the present disclosure is not limited thereto. 
     Optionally, the pixel circuit includes a first transistor, and the display substrate further includes the second initialization control line and the initial data line provided on the base substrate; 
     a gate electrode of the first transistor and a gate electrode of the driving transistor are in a same layer and made of a same material, and the gate electrode of the first transistor is electrically connected to the second initialization control line;   a first electrode of the first transistor, a second electrode of the first transistor, a first electrode of the driving transistor, and a second electrode of the driving transistor are arranged in a same layer and made of a same material;   the first electrode of the first transistor is electrically connected to the initial data line, and the second electrode of the first transistor is electrically connected to the anode of the light-emitting element.   

     In at least one embodiment of the present disclosure, the second initialization control line and the gate line may be arranged in a same layer and made of a same material, and the second initialization control signal on the second initialization control line may be the same as the gate driving signal on the gate line. 
     Optionally, the pixel circuit may include a driving transistor and a storage capacitor; 
     a gate electrode of the driving transistor is also used as a first electrode plate of the storage capacitor;   the initialization voltage line and the gate electrode of the driving transistor are arranged in a same layer and made of a same material, or, the initialization voltage line and a second electrode plate of the storage capacitor are arranged in a same layer and made of a same material.   

     In specific implementations, the initialization voltage line may be formed in the first gate metal layer, or, the initialization voltage line may be formed in the second gate metal layer, and the present disclosure is not limited thereto. 
     Optionally, the display substrate may further include a gate line arranged on the base substrate; 
     an extension direction of the initialization voltage line is the same as an extension direction of the gate line. 
     In at least one embodiment of the present disclosure, the extension direction of the initialization voltage line being the same as the extension direction of the gate line may refer to that: the extension direction of the initialization voltage line is exactly the same as the extension direction of the gate line, or, an angle between the extension direction of the initialization voltage line and the extension direction of the gate line is less than a predetermined angle to cause the extension direction of the initialization voltage line to be substantially the same as the extension direction of the gate line; and the present disclosure is not limited thereto. 
       FIG.  4    is a schematic diagram of the layout of the pixel circuit according to at least one embodiment of the present disclosure. The pixel circuit is arranged in the active area of the display substrate. 
     In  FIG.  4   , I 11  is a first initialization voltage line portion included in the initialization voltage line, D 021  is a first initial data line portion included in the initial data line, I 12  is a second initialization voltage line portion included in the initialization voltage line, and D 022  is a second initial data line portion included in the initial data line; I 11 , I 12 , D 021  and D 022  may be set in the active area; each of I 11  and I 12  may be electrically connected to the initialization voltage wire outside the active area, I 11  and I 12  are electrically connected to each other, each of D 021  and D 022  may be electrically connected to the initial data wire outside the active area, and D 021  and D 022  are electrically connected to each other; and the present disclosure is not limited thereto. 
     In at least one embodiment of the present disclosure, the display substrate includes multiple rows and multiple columns of pixel circuits disposed on the base substrate, each row of pixel circuits is electrically connected to the same row of gate line, and the same column of pixel circuits are electrically connected to the same column of display data line. When the pixel circuit adopts the structure shown in  FIG.  4   , the initialization voltage line includes multiple initialization voltage line portions extending in the first direction, each row of pixel circuits is electrically connected to the corresponding initialization voltage line portion, the initial data line includes multiple initial data line portions extending in the first direction, and each row of pixel circuits is electrically connected to the corresponding initial data line portion. 
     The same row of pixel circuits may be electrically connected to the same initialization voltage line portion, and the same row of pixel circuits may be electrically connected to the same initial data line portion. 
     In addition, the initial data wire and the initialization voltage wire are provided outside the active area of the display substrate, the initialization voltage wire is used to provide the initialization voltage to each of the initialization voltage line portions, the initial data line is used to provide the initial data voltage to each of the initial data line portions, the initialization voltage line portions are electrically connected to each other, and the initial data line portions are electrically connected to each other. 
     In  FIG.  4   , R 1  is the first initialization control line, G 0  is the gate line, C 1   b  is the second electrode plate of the storage capacitor in the pixel circuit, E 1  is the light-emitting control line, D 01  is the display data line, and R 2  is the second initialization control line. 
     The second initialization control signal provided to the second initialization control line R 2  is the same as the gate driving signal provided to G 0 . 
     In at least one embodiment corresponding to  FIG.  4   , on the base substrate, an active layer, a first gate metal layer, a second gate metal layer, and a first source and drain metal layer are sequentially arranged along a direction leaving the base substrate. 
     A patterning process is performed on the first gate metal layer to form the gate line G 0 , the first initialization control line R 1 , the second initialization control line R 2 , the light-emitting control line E 1 , and the gate electrode of each transistor in the pixel circuits. 
     A patterning process is performed on the second gate metal layer to form the initial data line, the initialization voltage line, and the second electrode plate of the storage capacitor in the pixel circuit. 
     In at least one embodiment shown in  FIG.  4   , the initial data line and the initialization voltage line are formed in the second gate metal layer, the extension direction of the initial data line is the same as the extension direction of the gate line G 0 , and the extension direction of the initialization voltage line is the same as the extension direction of the gate line G 0 . 
     In at least one embodiment shown in  FIG.  4   , the extension direction of G 0  may be a first direction, the first direction may be, for example, a horizontal direction, the extension direction of D 01  may be a second direction, and the second direction may be, for example, a vertical direction; and the present disclosure is not limited thereto. 
     In at least one embodiment of the present disclosure, the extension direction of the gate line may be the first direction, the extension direction of the display data line may be the second direction, and the first direction and the second direction intersect; and the present disclosure is not limited thereto. 
     As shown in  FIG.  5   , the pattern of the active layer in  FIG.  4    includes the first electrode S 1  of the first transistor, the second electrode D 1  of the first transistor, the first electrode S 2  of the second transistor, the second electrode D 2  of the second transistor, the first electrode S 4  of the fourth transistor, the first electrode S 5  of the fifth transistor, the second electrode D 5  of the fifth transistor, and the second electrode D 6  of the sixth transistor. 
     In at least one embodiment corresponding to  FIGS.  4  and  5   , the second electrode D 2  of the second transistor is also used as the first electrode of the sixth transistor, the second electrode D 5  of the fifth transistor is also used as the second electrode of the fourth transistor, the second electrode D 5  of the fifth transistor is also used as the first electrode of the driving transistor, and the second electrode D 6  of the sixth transistor is also used as the second electrode of the driving transistor. 
     As shown in  FIG.  6   , T 2  is a dual gate transistor, G 21  is the first gate electrode pattern included in the gate electrode of the second transistor, and G 22  is the second gate electrode pattern included in the gate electrode of the second transistor; 
     G 5  is the gate electrode of the fifth transistor;   T 6  is a dual gate transistor, G 61  is the third gate electrode pattern included in the gate electrode of the sixth transistor, and G 62  is the fourth gate electrode pattern included in the gate electrode of the sixth transistor;   G 3  is the gate electrode of the third transistor, G 4  is the gate electrode of the fourth transistor, and G 1  is the gate electrode of the first transistor;   G 7  is the gate electrode of the driving transistor, and G 7  is also used as the first electrode plate of the storage capacitor in the pixel circuit.   

     As shown in  FIG.  7   , C 1   b  is the second electrode plate of the storage capacitor, H 0  is the connecting hole provided in C 1   b , and D 2  is electrically connected to G 2  through the connecting hole H 0 . 
     After the active layer, the first gate metal layer and the second gate metal layer are arranged in sequence, an interlayer dielectric layer may be provided, and after the interlayer dielectric layer is provided, via holes may be formed. As shown in  FIG.  8   , H 1  is the first via hole, H 2  is the second via hole, H 3  is the third via hole, H 4  is the fourth via hole, H 5  is the fifth via hole, H 6  is the sixth via hole, H 7  is the seventh via hole, H 8  is the eighth via hole, H 9  is the ninth via hole, H 10  is the tenth via hole, H 11  is the eleventh via hole, H 12  is the twelfth via hole, H 13  is the thirteenth via hole, H 14  is the fourteenth via hole, and H 15  is the fifteenth via hole. 
     As shown in  FIG.  9   , the pattern of the first source and drain metal layer includes the display data line D 01 , the second voltage line, the first conductive connection portion L 1 , the second conductive connection portion L 2 , the third conductive connection portion L 3 , the fourth conductive connection portion L 3 , the conductive connection portion L 4 , the fifth conductive connection portion L 5 , and the sixth conductive connection portion L 6 . In  FIG.  8   , V 21  is the first voltage line portion included in the second voltage line. 
     When the pixel circuit adopts the structure shown in  FIG.  4   , the second voltage line includes multiple voltage line portions extending in the second direction, and each column of pixel circuits is electrically connected to the corresponding voltage line portion; a second voltage wire is provided outside the active area, the second voltage wire is used to provide the second voltage signal to each of the voltage line portions included in the second voltage line, and the voltage line portions included in the second voltage line are electrically connected to each other. 
     As shown in  FIGS.  4  to  9   , S 2  is electrically connected to the first conductive connection portion L 1  through the fourth via hole H 4 , and L 1  is electrically connected to I 11  through the first via hole H 1 , so that S 2  and I 11  are electrically connected, that is, S 2  is electrically connected to the initialization voltage line; 
     S 1  is electrically connected to L 6  through H 14 , and L 6  is electrically connected to D 022  through H 11 , so that S 1  is electrically connected to D 022 , that is, S 1  is electrically connected to the initial data line;   D 2  is electrically connected to L 3  through H 7 , and L 3  is electrically connected to G 7  through H 0 ;   S 5  is electrically connected to D 01  through H 3 ;   S 4  is electrically connected to V 21  through H 8 ;   D 1  is electrically connected to L 4  through H 9 , and L 4  is electrically connected to the anode layer through a via hole.   

     When manufacturing the display substrate, after fabricating the first source and drain metal layer, the first planarization layer and the anode layer are manufactured in sequence. The anode layer includes multiple mutually independent anodes. L 4  may be electrically connected to the anode through a via hole penetrating through the first planarization layer. After the anode layer is fabricated, a PDL layer (pixel definition layer), an organic light-emitting function layer, and a cathode layer may be fabricated in sequence. 
     In at least one embodiment of the present disclosure, the cathode layer may cover the entire active area, and the cathode layer may bond, in the non-display area of the display substrate, with the first voltage line through the anode layer, so that the cathode of the light-emitting element is electrically connected to the first voltage line; and the present disclosure is not limited thereto. Optionally, the first voltage line may be arranged around the active area, and the present disclosure is not limited thereto. 
     In at least one embodiment of the present disclosure, a first gate insulating layer may be provided between the active layer and the first gate metal layer, a second gate insulating layer may be provided between the first gate metal layer and the second gate metal layer, and an interlayer dielectric layer may be provided between the second gate metal layer and the first source and drain metal layer; and the present disclosure is not limited thereto. 
     In at least one embodiment shown in  FIG.  4   , both the initial data line and the initialization voltage line are formed in the second gate metal layer, and the present disclosure is not limited thereto. 
     When the display substrate includes at least one embodiment of the pixel circuit as shown in  FIG.  4   , both the initial data line and the initialization voltage line extend in the first direction. For example, the first direction may be a horizontal direction. Then the multiple rows of initial data line portions included in the initial data line also extend in the first direction, and the multiple rows of initialization voltage line portions included in the initialization voltage line also extend in the first direction. Outside the active area of the display substrate, the initial data wire providing the initial data voltage and the initialization voltage wire providing the initialization voltage may be provided, and the initial data wire and the initialization voltage wire may be arranged at the first side and/or the second side (the first side may be the left side, and the second side may be the right side) of the display substrate. At least part of wires included in the initial data wire and at least part of wires included in the initialization voltage wire may extend in the second direction (the second direction may be, for example, the vertical direction), each row of initial data line portion may extend in the first direction until it is electrically connected to the initial data wire, and each row of initialization voltage line portion may extend in the first direction until it is electrically connected to the initialization voltage wire. 
     In at least one embodiment shown in  FIG.  4   , the second voltage line extends in the second direction, and the multiple voltage line portions included in the second voltage line extend in the second direction, so the second voltage wire used for providing the second voltage signal may be arranged at a side of the active area of the display substrate that is close to the driving chip. For example, the second voltage wire may be arranged at the lower side of the display substrate; and the present disclosure is not limited thereto. 
     Optionally, the second voltage wire may include a second voltage wire portion extending in the first direction and a first voltage wire portion extending in the second direction. The second voltage wire portion is used for electrically connecting the multiple voltage line portions included in the second voltage line (for example, when the second voltage wire is disposed at the lower side of the display substrate, each voltage line portion included in the second voltage line may extend downward, in the second direction, so as to be electrically connected to the second voltage wire portion), the first terminal of the first voltage wire portion is electrically connected to the second voltage wire portion, and the second terminal of the first voltage wire portion is directly electrically connected to the driving chip to receive the second voltage signal provided by the driving chip. 
     In at least one embodiment shown in  FIG.  4   , R 1  and R 2  are different initialization control lines. In actual operations, R 1  and R 2  may be the same initialization control line. 
     The difference between at least one embodiment of the pixel circuit shown in  FIG.  10    and at least one embodiment of the pixel circuit shown in  FIG.  4    is that: a second source and drain metal layer is further provided on a side of the first source and drain metal layer away from the base substrate, and the initial data line extends in the second direction, that is, the extension direction of the initial data line is the same as the extension direction of the display data line, and a patterning process is performed on the second source and drain metal layer to form each initial data line portion included in the initial data line. In  FIG.  10   , D 021  is the first initial data line portion included in the initial data line. 
     The structure diagram of the active layer in  FIG.  10    is shown in  FIG.  5   , the structure diagram of the first gate metal layer in  FIG.  10    is shown in  FIG.  6   , and the structure diagram of the second gate metal layer in  FIG.  10    is shown in  FIG.  11   , the schematic diagram of the via holes in  FIG.  10    is shown in  FIG.  12   , the structure diagram of the first source and drain metal layer in  FIG.  10    is shown in  FIG.  9   , and the structure diagram of the second source and drain metal layer in  FIG.  10    is shown in  FIG.  13   . 
     As shown in  FIG.  9    and  FIGS.  10 - 13   , L 6  is electrically connected to D 021  through H 11 . As shown in  FIG.  10   , the extension direction of D 021  is the same as the extension direction of D 01 . 
     The connection relationship of other components in  FIG.  10    is the same as the connection relationship of components in  FIG.  4   . 
     When the display substrate includes multiple rows and multiple columns of pixel circuits according to at least one embodiment shown in  FIG.  10   , the same column of the pixel circuits may be electrically connected to the same initial data line portion, and the same row of the pixel circuits may be electrically connected to the same initialization voltage line portion. 
     In at least one embodiment shown in  FIG.  10   , R 1  and R 2  are different initialization control lines. In actual operations, R 1  and R 2  may be the same initialization control line. 
     A display device according to the embodiments of the present disclosure includes the above-mentioned display substrate. 
     In specific implementations, the display device described in at least one embodiment of the present disclosure may further include a driving chip and an initial data wire, a first voltage line and a second voltage wire, where the initial data wire, the first voltage line and the second voltage wire are outside an active area of the base substrate; 
     the initial data wire includes a first initial data wire portion directly electrically connected to the driving chip; 
     the first voltage line includes a first voltage line portion directly electrically connected to the driving chip, and the second voltage wire includes a first voltage wire portion directly electrically connected to the driving chip; 
     the first initial data wire portion is between the first voltage line portion and the first voltage wire portion. 
     In at least one embodiment of the present disclosure, the first initial data wire portion is disposed between the first voltage line portion and the first voltage wire portion, the first voltage line portion is used to provide the first voltage signal, the first voltage wire portion is used to provide the second voltage signal, and the first voltage signal and the second voltage signal are both direct-current voltage signals, so that interference may not be caused for the initial data voltage on the first initial data wire portion. 
     Optionally, the driving chip may be arranged on a COF (chip on film) or directly bound to the base substrate, and the COF may be attached to a side of the display substrate; and the present disclosure is not limited thereto. The driving chip may be used to provide the first voltage signal, the second voltage signal, the initialization voltage, and the initial data voltage. 
     In at least one embodiment of the present disclosure, the base substrate may be a flexible substrate or a rigid substrate, and the driving chip may use COP (Chip On Pi, COP is a technology in which the chip is bound on a flexible substrate) technology or COG (Chip On Glass, COG is a technology in which the chip is directly bound on the glass surface) technology so as to be bound on the base substrate. 
     Optionally, the first initial data wire portion, the first voltage line portion, and the first voltage wire portion all extend in the second direction, and the present disclosure is not limited thereto. 
     The second direction is a direction in which the display data line extends. 
     In at least one embodiment of the present disclosure, the display device may further include a driving chip, an initial data wire, an initialization voltage wire, a first voltage line, and a second voltage wire, where the initial data wire, the initialization voltage wire, the first voltage line, and the second voltage wire are outside an active area of the base substrate; 
     the initial data wire includes a first initial data wire portion directly electrically connected to the driving chip;   the initialization voltage wire includes a first initialization voltage wire portion directly electrically connected to the driving chip;   the first voltage line includes a first voltage line portion directly electrically connected to the driving chip, and the second voltage wire includes a first voltage wire portion directly electrically connected to the driving chip;   the first initialization voltage wire portion, the first initial data wire portion, the first voltage line portion, and the first voltage wire portion are sequentially in a direction toward the active area.   

     In specific implementations, if the space is limited, the first initial data wire portion may be arranged between the first initialization voltage wire portion and the first voltage line portion. 
     As shown in  FIG.  14   , when the extension direction of the initialization voltage line and the extension direction of the initial data line are both the same as the extension direction of the gate line (the extension direction of the gate line is the first direction), the display substrate according to at least one embodiment of the present disclosure further includes the initial data wire, the initialization voltage wire, the gate driving circuit  140 , the first voltage line, and the second voltage wire that are arranged outside the active area A 0 . 
     The second voltage wire includes the second voltage wire portion L 22  extending in the first direction and the first voltage wire portion L 21  extending in the second direction. The second voltage wire portion L 22  is used to electrically connect the multiple voltage line portions included in the second voltage line (when the second voltage wire is disposed at the lower side of the display substrate, each voltage line portion included in the second voltage line may extend downward, in the second direction, so as to be electrically connected to the second voltage wire portion). The first terminal of the first voltage wire portion L 21  is electrically connected to the second voltage wire portion L 22 , and the second terminal of the first voltage wire portion L 21  is directly electrically connected to the driving chip  141  to receive the second voltage signal provided by the driving chip  141 . 
     The initial data wire includes the first initial data wire portion L 31  extending in the second direction, the second initial data wire portion L 32  disposed on the left side of the active area A 0 , and the third initial data wire portion L 33  used for electrically connecting L 31  and L 32 ; L 32  may extend in the second direction; each initial data line portion included in the initial data line is directly electrically connected to the second initial data wire portion L 32 ; L 31 , L 32  and L 33  are an integrated structure; L 31  is directly electrically connected to the driving chip  141  to receive the second voltage signal provided by the driving chip  141 . 
     The initialization voltage wire includes the first initialization voltage wire portion L 41  extending in the second direction, and the second initialization voltage wire portion L 42  arranged on the left side of the active area A 0 , where L 41  is directly electrically connected to L 42 ; L 41  and L 42  are an integrated structure; L 41  is directly electrically connected to the driving chip  141 , and the driving chip  141  is used to provide the initialization voltage to L 41 ; L 42  also extends in the second direction. 
     The gate driving circuit  140  is arranged on a side of L 42  away from the active area A 0 ; the gate driving circuit  140  may be electrically connected to multiple rows of gate lines. 
     The first voltage line includes the first voltage line portion L 51  directly electrically connected to the driving chip  141 , the second voltage line portion L 52  provided on the left side of the active area A 0 , and the third initial data wire portion L 53  used for electrically connecting L 51  and L 52 ; L 51  and L 52  extend in the second direction, and L 53  extends in the first direction; the driving chip  141  provides the first voltage signal to L 51 . 
     In actual operations, the first voltage line may be arranged on each of sides of the display substrate where the driving chip is not provided, and the first voltage line is electrically connected to the driving chip for receiving the first voltage signal provided by the driving chip; and the present disclosure is not limited thereto. 
     In addition, the initial data wire, the initialization voltage wire, and the second voltage wire may also be provided on the right side of the active area, and the present disclosure is not limited thereto. 
     In at least one embodiment of the present disclosure, the initialization voltage wire and the initialization voltage line may be arranged in a same layer and made of a same material, the initial data wire and the initial data line may be arranged in a same layer and made of a same material, and the second voltage wire and the second voltage line may be arranged in a same layer and made of a same material; and the present disclosure is not limited thereto. 
     In at least one embodiment of the present disclosure, the first voltage line may be made of the first source and drain metal layer or the second source and drain metal layer, and the present disclosure is not limited thereto. 
     In at least one embodiment shown in  FIG.  14   , L 42  and L 32  may be arranged in a same layer and made of a same material, and L 42  is electrically connected to the initialization voltage line in the active area through a jumper wire, to avoid a connection line between L 42  and the initialization voltage line in the active area bonding with L 32  so as to avoid short circuit. 
     As shown in  FIG.  15   , when the extension direction of the initialization voltage line is the same as the extension direction of the gate line, and the extension direction of the initial data line is the same as the extension direction of the display data line (the extension direction of the gate line is the first direction, and the extension direction of the display data line is the second direction), the display substrate according to at least one embodiment of the present disclosure further includes the initial data wire, the initialization voltage wire, the gate driving circuit  140 , the first voltage line and the second voltage wire that are arranged outside the active area A 0 . 
     The initial data wire is arranged below the active area A 0  (that is, the initial data wire is arranged on the lower side of the display substrate). 
     The initial data wire includes the first initial data wire portion L 31  extending along the second direction, the second initial data wire portion L 32  extending along the first direction, and the third initial data wire portion L 32  for electrically connecting L 31  and L 32 ; L 33  extends in the second direction; L 31  is directly electrically connected to the driving chip  141  to receive the second voltage signal provided by the driving chip  141 . 
     The second voltage wire is arranged below the active area A 0  (that is, the second voltage wire is arranged on the lower side of the display substrate), the second voltage wire includes the second voltage wire portion L 22  extending along the first direction and the first voltage wire portion L 21  extending in the second direction, the second voltage wire portion L 22  is used to electrically connect the multiple voltage line portions included in the second voltage line, the first terminal of the first voltage wire portion L 21  is electrically connected to the second voltage wire portion L 22 , and the second terminal of the first voltage wire portion L 21  is directly electrically connected to the driving chip  141  to receive the second voltage signal provided by the driving chip  141 ; the second voltage wire portion L 22  may be electrically connected to the voltage line portions included in the second voltage line in the active area A 0  through jumper wires, so as to avoid short circuit caused by bonding with L 32 . 
     The initialization voltage wire includes the first initialization voltage wire portion L 41  extending in the second direction, the second initialization voltage wire portion L 42  provided on the left side of the active area A 0 , and the third initialization voltage wire portion L 43  that is used for electrically connecting L 41  and L 42  and extends in the first direction; L 41  is directly electrically connected to the driving chip  141 , and the driving chip  141  is used to provide the initialization voltage to L 41 ; L 42  also extends in the second direction. 
     The gate driving circuit  140  is arranged on a side of L 41  away from the active area A 0 ; the gate driving circuit  140  may be electrically connected to multiple rows of gate lines. 
     The first voltage line includes the first voltage line portion L 51  directly electrically connected to the driving chip  141 , the second voltage line portion L 52  provided on the left side of the active area A 0 , and the third initial data wire portion L 53  for electrically connecting L 51  and L 52 ; L 51  and L 52  extend in the second direction, and L 53  extends in the first direction; the driving chip  141  provides the first voltage signal to L 51 . 
     In actual operations, the first voltage line may be arranged on each of sides of the display substrate where the driving chip is not provided, and the first voltage line is electrically connected to the driving chip for receiving the first voltage signal provided by the driving chip; and the present disclosure is not limited thereto. 
     In addition, the initialization voltage wire and the second voltage wire may also be provided on the right side of the active area, and the present disclosure is not limited thereto. 
     The display device provided by the embodiments of the present disclosure may be any product or component with a display touch function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, or the like. 
     The above descriptions illustrate preferred implementations of the present disclosure. It should be noted that for those skilled in the art, without departing from the principles of the present disclosure, various improvements and polishments may be made. These improvements and polishments shall fall within the protection scope of the present disclosure.