Patent Publication Number: US-11031911-B2

Title: Envelope tracking integrated circuit and related apparatus

Description:
RELATED APPLICATIONS 
     This application claims the benefit of provisional patent application Ser. No. 62/842,486, filed May 2, 2019, the disclosure of which is hereby incorporated herein by reference in its entirety. 
    
    
     FIELD OF THE DISCLOSURE 
     The technology of the disclosure relates generally to an envelope tracking (ET) radio frequency (RF) power amplifier apparatus. 
     BACKGROUND 
     Mobile communication devices, such as smartphones, have become increasingly common in current society for providing wireless communication services. The prevalence of these mobile communication devices is driven in part by the many functions that are now enabled on such devices. Increased processing capabilities in such devices means that mobile communication devices have evolved from being pure communication tools into sophisticated mobile multimedia centers that enable enhanced user experiences. 
     The redefined user experience has also led to the rise of so-called wearable devices, such as smartwatches. Over time, the wearable devices have evolved from simple companion devices to the mobile communication devices into full-fledged multi-functional wireless communication devices. Nowadays, most of the wearable electronic devices are often equipped with digital and analog circuitries capable of communicating a radio frequency (RF) signal(s) in a variety of wireless communication systems, such as long-term evolution (LTE), Wi-Fi, Bluetooth, and so on. Like mobile communication devices, wearable devices often employ sophisticated power amplifiers to amplify the RF signal(s) to help improve coverage range, data throughput, and reliability of the wearable devices. 
     Envelope tracking (ET) is a power management technology designed to improve efficiency levels of the power amplifiers. In this regard, it may be desirable to employ ET across the variety of wireless communication technologies to help reduce power consumption and thermal dissipation in the wearable devices. Notably, the RF signal(s) communicated in different wireless communication systems may correspond to different modulation bandwidths (e.g., from 80 KHz to over 200 MHz). Further, the power amplifiers can be associated with different load-line impedances and/or subject to different voltage standing wave ratios (VSWRs), which measure how efficiently the power amplifiers can transfer the RF signal to a load (e.g., an antenna). As such, it may be desirable to ensure that the power amplifiers can maintain optimal efficiency across a wide range of modulation bandwidth and in face of different load-line impedances. 
     SUMMARY 
     Embodiments of the disclosure relate to an envelope tracking (ET) integrated circuit (IC) (ETIC). The ETIC is configured to generate an ET voltage based on a supply voltage(s) and provide the ET voltage to an amplifier circuit(s) for amplifying a radio frequency (RF) signal(s). Notably, the RF signal(s) may be modulated in different modulation bandwidths and the amplifier circuit(s) may correspond to different load-line impedances. Accordingly, the ETIC may need to adapt the ET voltage such that the ETIC and the amplifier circuit(s) can operate at higher efficiencies. In examples discussed herein, the ETIC is configured to determine a time-variant peak of the ET voltage and adjust the supply voltage(s) accordingly. As a result, it may be possible to improve operating efficiency of the ETIC in face of a wide range of bandwidth and/or load-line requirements. 
     In one aspect, an ETIC is provided. The ETIC includes an ET voltage circuit configured to generate an ET voltage based on at least one supply voltage. The ETIC also includes a supply voltage circuit configured to generate the at least one supply voltage based on at least one supply target voltage. The ETIC also includes a control circuit. The control circuit is configured to determine a peak of the ET voltage. The control circuit is also configured to adjust the at least one supply target voltage based on the determined peak of the ET voltage to cause the supply voltage circuit to adjust the at least one supply voltage. 
     In another aspect, an ET apparatus is provided. The ET apparatus includes an ETIC. The ETIC includes an ET voltage circuit configured to generate an ET voltage based on at least one supply voltage. The ETIC also includes a supply voltage circuit configured to generate the at least one supply voltage based on at least one supply target voltage. The ETIC also includes a control circuit. The control circuit is configured to determine a peak of the ET voltage. The control circuit is also configured to adjust the at least one supply target voltage based on the determined peak of the ET voltage to cause the supply voltage circuit to adjust the at least one supply voltage. The ET apparatus also includes a transceiver circuit coupled to the ETIC. 
     Those skilled in the art will appreciate the scope of the present disclosure and realize additional aspects thereof after reading the following detailed description of the preferred embodiments in association with the accompanying drawing figures. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWING FIGURES 
       The accompanying drawing figures incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure. 
         FIG. 1  is a schematic diagram of an exemplary ETIC configured according to an embodiment of the present disclosure to maintain a higher operating efficiency in face of a wide range of bandwidth and/or load-line requirements 
         FIG. 2A  is a schematic diagram providing an exemplary illustration of a voltage amplifier in the ETIC of  FIG. 1 ; 
         FIG. 2B  is a schematic diagram providing an exemplary illustration of an output stage in the voltage amplifier of  FIG. 2A ; and 
         FIG. 3  is a graphic diagram providing an exemplary illustration of the ETIC of  FIG. 1  configured to maintain the higher operating efficiency on a periodic basis. 
     
    
    
     DETAILED DESCRIPTION 
     The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims. 
     It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. 
     It will be understood that when an element such as a layer, region, or substrate is referred to as being “on” or extending “onto” another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being “over” or extending “over” another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly over” or extending “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. 
     Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures. 
     The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and/or “including” when used herein specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. 
     Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. 
     Embodiments of the disclosure relate to an envelope tracking (ET) integrated circuit (IC) (ETIC). The ETIC is configured to generate an ET voltage based on a supply voltage(s) and provide the ET voltage to an amplifier circuit(s) for amplifying a radio frequency (RF) signal(s). Notably, the RF signal(s) may be modulated in different modulation bandwidths and the amplifier circuit(s) may correspond to different load-line impedances. Accordingly, the ETIC may need to adapt the ET voltage such that the ETIC and the amplifier circuit(s) can operate at higher efficiencies. In examples discussed herein, the ETIC is configured to determine a time-variant peak of the ET voltage and adjust the supply voltage(s) accordingly. As a result, it may be possible to improve operating efficiency of the ETIC in face of a wide range of bandwidth and/or load-line requirements. 
     In this regard,  FIG. 1  is a schematic diagram of an exemplary ETIC  10  configured according to an embodiment of the present disclosure to maintain a higher operating efficiency in face of a wide range of bandwidth and/or load-line requirements. The ETIC  10  includes an ET voltage circuit  12  configured to generate an ET voltage V CC  based on a lower supply voltage V SUP-L  or a higher supply voltage V SUP-H  (collectively referred to as “at least one supply voltage”). The ETIC  10  also includes a supply voltage circuit  14  configured to generate the lower supply voltage V SUP-L  or the higher supply voltage V SUP-H . The supply voltage circuit  14  may be configured to receive a lower supply target voltage V SUPPL-TGT  or a higher supply target voltage V SUPH-TGT  (collectively referred to as “at least one supply target voltage”). In a non-limiting example, the supply voltage circuit  14  can be configured to generate the lower supply voltage V SUP-L  in response to receiving the lower supply target voltage V SUPL-TGT  and generate the higher supply voltage V SUP-H  in response to receiving the higher supply target voltage V SUPH-TGT . In this regard, the lower supply voltage V SUP-L  may be proportionally related to the lower supply target voltage V SUPL-TGT  and the higher supply voltage V SUP-H  may be proportionally related to the higher supply target voltage V SUPH-TGT . As such, it may be possible to cause an adjustment in the lower supply voltage V SUP-L  by adjusting the lower supply target voltage V SUPL-TGT . Likewise, it may be possible to cause an adjustment in the higher supply voltage V SUP-H  by adjusting the higher supply target voltage V SUPH-TGT . 
     In a non-limiting example, the ET voltage circuit  12  includes a voltage amplifier  16  and an offset capacitor  18 . The voltage amplifier  16  is configured to generate an initial ET voltage V AMP  based on the lower supply voltage V SUP-L  or the higher supply voltage V SUP-H . The offset capacitor  18  may be configured to raise the initial ET voltage V AMP  by an offset voltage V OFF  (e.g., 0.8 V) to generate the ET voltage V CC  at an output port  20  (V CC =V AMP +V OFF ). By employing the offset capacitor  18  to raise the initial ET voltage V AMP , it may be possible to ease the burden of the voltage amplifier  16  when the ET voltage approaches a peak, thus making it possible to improve operating efficiency of the voltage amplifier  16 . 
     The ETIC  10  may be coupled to an amplifier circuit  22  configured to amplify an RF signal  24  based on the ET voltage V CC . Notably, the amplifier circuit  22  may exhibit different load-line impedances to the ETIC  10  and the RF signal  24  may correspond to different modulation bandwidths. As such, the ETIC  10  may be required to adapt the ET voltage V CC  accordingly to help improve operating efficiency of the amplifier circuit  22 . 
     In a non-limiting example, the supply voltage circuit  14  is configured to provide the higher supply voltage V SUP-H  to the voltage amplifier  16  to help avoid amplitude clipping when the ET voltage is near the peak. Alternatively, the supply voltage circuit  14  may be configured to provide the lower supply voltage V SUP-L  to the voltage amplifier  16  to help improve operating efficiency of the voltage amplifier  16  when the ET voltage is close to an average. Typically, the voltage amplifier  16  will be more efficient when operating based on the lower supply voltage V SUP-L  than operating based on the higher supply voltage V SUP-H . Given that the voltage amplifier is less efficient when operating based on the higher supply voltage V SUP-H , it may be desirable to improve overall efficiency of the voltage amplifier  16  at the higher supply voltage V SUP-H . 
     In this regard, the ETIC  10  is further configured to include a control circuit  26 , which can be a microprocessor, a microcontroller, or a field-programmable gate array (FPGA), as an example. In examples discussed herein, the control circuit  26  is configured to determine the peak of the ET voltage V CC , for example on a periodic basis. Accordingly, the control circuit  26  can be configured to dynamically adjust the higher supply target voltage V SUPH-TGT  based on the determined peak of the ET voltage V CC  to cause the supply voltage circuit  14  to adjust the higher supply voltage V SUP-H . As such, it may be possible to opportunistically adapt the higher supply voltage V SUP-H  when the ET voltage V CC  is at or near the peak, thus making it possible to improve overall operating efficiency of the voltage amplifier  16  in face of the wide range of modulation bandwidths and/or load-line impedances. 
     To help understand how the control circuit  26  can influence the higher supply voltage V SUP-H , it may be necessary to further explain the inner structure of the voltage amplifier  16  in the ET voltage circuit  12 . In this regard,  FIG. 2A  is a schematic diagram providing an exemplary illustration of the voltage amplifier  16  in the ETIC  10  of  FIG. 1 . Common elements between  FIGS. 1 and 2A  are shown therein with common element numbers and will not be re-described herein. 
     The voltage amplifier  16  includes at least one input stage  28  and at least one output stage  30 . The input stage  28  may be configured to receive an ET target voltage V TGT  and the output stage  30  is configured to receive the lower supply voltage V SUP-L  or the higher supply voltage V SUP-H . Collectively, the input stage  28  and the output stage  30  cause the voltage amplifier  16  to generate the initial ET voltage V AMP  based on the ET target voltage V TGT  and one of the lower supply voltage V SUP-L  and the higher supply voltage V SUP-H . The input stage  28  may be further configured to receive a feedback voltage V CCFB , which is proportional to the ET voltage V CC , such that the ET voltage circuit  12  can generate the ET voltage V CC  based on a closed-loop envelope tracking mechanism. In addition to generating the initial ET voltage VAMP, the voltage amplifier  16  may also source or sink a high-frequency current l AC  (e.g., an alternating current) depending on the modulation bandwidth of the RF signal  24 . 
       FIG. 2B  is a schematic diagram providing an exemplary illustration of the output stage  30  in the voltage amplifier  16  of  FIG. 2A . Common elements between  FIGS. 2A and 2B  are shown therein with common element numbers and will not be re-described herein. 
     In a non-limiting example, the output stage  30  includes a p-type field-effect transistor (PFET) stack  32  and an n-type field-effect transistor (NFET) stack  34 . The PFET stack  32  may include at least one PFET  36  and corresponds to an equivalent resistance R PFET . The NFET stack  34  may include at least one NFET  38  and corresponds to an equivalent resistance R NFET . The PFET stack  32  may be coupled to the supply voltage circuit  14  to receive the lower supply voltage V SUP-L  or the higher supply voltage V SUP-H . In addition, the PFET stack  32  may be configured to source the high-frequency current l AC , for example, when the RF signal  24  exhibits a higher peak-to-average ratio (PAR). The NFET stack  34  may be coupled between the PFET stack  32  and a ground (GND). The NFET stack  34  may be configured to sink the high-frequency current l AC , for example, when the RF signal  24  exhibits a lower PAR. 
     With reference back to  FIG. 1 , the supply voltage circuit  14  may be configured to generate the higher supply voltage V SUP-H  based on the equation (Eq. 1) below.
 
 V   SUP-H   =V   CC-MAX   −V   OFF   +P   headroom   (Eq. 1)
 
     In the equation (Eq. 1) above, V CC-MAX  represents the peak of the ET voltage V CC  and P headroom  represents a defined headroom voltage corresponding to the PAR of the RF signal  24 . In this regard, it may be possible to adjust the higher supply voltage V SUP-H  by adjusting the P headroom , which may be further determined based on the equation (Eq. 2) below.
 
 P   headroom   =R   PFET   *I   AC-MAX   (Eq. 2)
 
     In the equation (Eq. 2) above, R PFET  represents the equivalent resistance of the PFET stack  32  in the output stage  30  of the voltage amplifier  16 . I AC-MAX  represents a peak of the high-frequency current l AC , which typically coincides with the peak of the ET voltage V CC , sourced by the voltage amplifier  16 . In this regard, to effectively control the higher supply voltage V SUP-H  on an ongoing basis to improve the operating efficiency near the peak of the ET voltage V CC , the control circuit  26  may be configured to periodically determine a headroom voltage variation ΔP headroom  relative to the defined headroom voltage P headroom . Accordingly, the control circuit  26  may adjust the higher supply target voltage V SUPH-TGT  to cause the supply voltage circuit  14  to adjust the higher supply voltage V SUP-H . In a non-limiting example, the control circuit  26  can determine the headroom voltage variation ΔP headroom  based on the equation (Eq. 3) below.
 
Δ P   headroom   =R   PFET *( I   AC-MAX-REF   −I   AC-MAX )  (Eq. 3)
 
     In the equation (Eq. 3) above, I AC-MAX-REF  represents the peak of the high-frequency current l AC  corresponding to the defined headroom voltage P headroom  and I AC-MAX  represents a presently determined peak of the high-frequency current I AC  corresponding to a presently determined peak of the ET voltage V CC . In a non-limiting example, I AC-MAX-REF  corresponds to the peak of the high-frequency current l AC  in a first duration and l AC-MAX  corresponds to the peak of the high-frequency current l AC  in a second duration succeeding the first duration, as illustrated in  FIG. 3 . 
     In this regard,  FIG. 3  is a graphic diagram providing an exemplary illustration of the ETIC  10  of  FIG. 1  configured to maintain the higher operating efficiency on a periodic basis. In a non-limiting example, the first duration and the second duration can correspond to a timeslot N and a timeslot N+1, among a number of continuous timeslots. In this regard, I AC-MAX-REF  corresponds to the peak of the high-frequency current l AC  in the timeslot N and I AC-MAX  corresponds to the peak of the high-frequency current I AC  in the timeslot N+1, which immediately succeeds the timeslot N. 
     During the timeslot N, the control circuit  26  may determine the headroom voltage variation ΔP headroom . The control circuit  26  may determine the higher supply target voltage V SUPH-TGT  based on the headroom voltage variation ΔP headroom . The control circuit  26  may subsequently provide the updated higher supply target voltage V SUPH-TGT  to the supply voltage circuit  14 . Accordingly, the supply voltage circuit  14  may generate the updated higher supply voltage V SUP-H  in the succeeding timeslot N+1. By effectuating the updated higher supply voltage V SUP-H  in the succeeding timeslot N+1, as opposed to the present timeslot N, it may be possible to avoid unintended disruption to the voltage amplifier  16 . 
     With reference back to  FIG. 1 , the voltage amplifier  16  may be configured to generate a sense current I SNS  that is proportionally related to the high-frequency current I AC  sourced by the voltage amplifier  16 . In this regard, the control circuit  26  may be configured to determine the peak of the high-frequency current I AC-MAX , and thus the headroom voltage variation ΔP headroom , based on the sense current I SNS . 
     The ETIC  10  may be configured to include a headroom adjuster  40  coupled between the control circuit  26  and the supply voltage circuit  14 . In a non-limiting example, the headroom adjuster  40  can be configured to determine the headroom voltage variation ΔP headroom  based on the sense current I SNS . Accordingly, the headroom adjuster  40  may adjust the higher supply target voltage V SUPH-TGT  based on the headroom voltage variation ΔP headroom  to cause the supply voltage circuit  14  to adjust the higher supply voltage V SUP-H . 
     The ETIC  10  can be further configured to include a multi-level charge pump (MCP)  42  and a power inductor  44 . The MCP  42  may be configured to generate a low-frequency voltage V DC  (e.g., a constant voltage) based on a battery voltage V BAT . The power inductor  44  may be configured to induce a low-frequency current I DC  (e.g., a direct current) based on the low-frequency voltage V DC . The power inductor  44  may be coupled to the output port  20  to provide the low-frequency current I DC  to the output port  20 . In this regard, the amplifier circuit  22  receives an ET current I CC  from the output port  20  that is a combination of the low-frequency current I DC  generated by the power inductor  44  and the high-frequency current I AC  sourced by the voltage amplifier  16  (I CC =I DC +I AC ). 
     The ETIC  10  may be coupled to a transceiver circuit  46 , which is configured to generate and provide the RF signal  24  to the amplifier circuit  22 . In an alternative embodiment, the transceiver circuit  46  may be configured to generate and provide the lower supply target voltage V SUPL-TGT  and/or the higher supply target voltage V SUPH-TGT  to the supply voltage circuit  14 . In this regard, the control circuit  26  can be configured to provide the headroom voltage variation ΔP headroom  (e.g., via an indication signal  48 ) to the transceiver circuit  46 . Accordingly, the transceiver circuit  46  may adjust the higher supply target voltage V SUPH-TGT  to cause the supply voltage circuit  14  to adjust the higher supply voltage V SUP-H . 
     As mentioned earlier in  FIG. 3 , the ETIC  10  may be configured to effectuate the updated higher supply voltage V SUP-H  in the succeeding timeslot N+1, as opposed to the present timeslot N, to avoid unintended disruption to the voltage amplifier  16 . In this regard, the transceiver circuit  46  may be configured to provide a boundary indication signal  50  configured to indicate the boundary between the timeslot N and the timeslot N+1. In a non-limiting example, the ETIC  10 , the amplifier circuit  22 , and the transceiver circuit  46  may be integrated into an ET apparatus  52 . 
     Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.