Patent Publication Number: US-2022238278-A1

Title: Ceramic electronic component, circuit board arrangement, and method of manufacturing ceramic electronic component

Description:
TECHNICAL FIELD 
     The present invention relates to ceramic electronic components, circuit board arrangements, and methods of manufacturing ceramic electronic components. 
     RELATED ART 
     Multilayer ceramic capacitors are used in high frequency communication systems, such as mobile phones, for purposes, such as noise reduction. Applications of multilayer ceramic capacitors have been expanding to include automotive applications. Higher reliability for ceramic capacitors is necessary. 
     Patent document 1 discloses a technique of including an element that reacts with hydrogen to form a covalent hydride between a plating layer that is the outermost layer constituting an external electrode and a dielectric layer constituting a ceramic element body in order to reduce the effect of hydrogen generated in a plating process and to minimize degradation of insulation resistance.
     Patent Document 1: JP-A-2016-58719   

     SUMMARY OF THE INVENTION 
     In the technology disclosed in Patent Document 1, certain types of elements could not be effective in preventing diffusion of hydrogen from the plating layer into the ceramic element body. 
     Accordingly, it is an object of the present invention to provide a ceramic electronic component, a circuit board arrangement, and a method of manufacturing a ceramic electronic component that can more effectively minimize diffusion of hydrogen into an element body. 
     According to one aspect of the present invention, there is provided a ceramic electronic component including an element body including a dielectric and internal electrodes; and external electrodes formed on the element body. Each of the external electrodes may include an electrical conductive layer connected to the internal electrodes, the electrical conductive layer having an outer side and an inner side, the outer side being farther from the element body than the inner side, the outer side having more voids than the inner side. 
     Each of the external electrodes may further include a plating layer formed outside the electrical conductive layer and containing Ni. 
     The voids in the electrical conductive layer may be located in a range from 0.1 μm to 3.0 μm from an outer surface of the electrical conductive layer in a thickness direction of the electrical conductive layer. 
     Each of the voids may have a length in a thickness direction of the electrical conductive layer and a length in a surface direction of the electrical conductive layer, and the length of the voids in the surface direction may be greater than the length of the voids in the thickness direction. 
     Each of the voids may have a length in a thickness direction of the electrical conductive layer and a length in a surface direction of the electrical conductive layer, and the electrical conductive layer may have more voids of which the length in the surface direction is greater than the length in the thickness direction than voids of which the length in surface directions is less than the length in the thickness direction. 
     The voids may have a longitudinal length in a longitudinal direction thereof, and the longitudinal length may be from 0.5 μm to 6.5 μm. 
     Each of the voids may have a length in a thickness direction of the electrical conductive layer and a length in a surface direction of the electrical conductive layer, and the electrical conductive layer may have voids of which the length in the surface direction is four times or more than the length in the thickness direction accounting for at least 50% of all of the voids in the electrical conductive layer. 
     The electrical conductive layer may have metal oxide portions, and the metal oxide portions may be disposed at positions inside the voids or being in contact with the voids. 
     The electrical conductive layer may include a base layer formed on the element body and connected to the internal electrodes, the base layer containing a conductor; and an innermost plating layer formed on the base layer, the innermost plating layer having an outer side and an inner side, the outer side of the innermost plating layer being farther from the element body than the inner side of the innermost plating layer, the outer side of the innermost plating layer having more voids than the inner side of the innermost plating layer. 
     A main component of a material of the innermost plating layer may be a metal selected from Cu, Fe, Zn, Sn, Pb, and Cr, or an alloy containing at least a metal selected from Cu, Fe, Zn, Sn, Pb, and Cr. 
     The main component of the material of the innermost plating layer may be Cu. 
     In this case, a main component of a material of the base layer of each of the external electrodes may be Ni. Each of the external electrodes may include a Ni plating layer formed outside the innermost plating layer and containing Ni; and a Sn plating layer formed on the Ni plating layer and containing Sn. 
     In another embodiment, the electrical conductive layer may include a base layer formed on the element body and connected to the internal electrodes. The base layer may have an outer side and an inner side, the outer side of the base layer being farther from the element body than the inner side of the base layer, the outer side of the base layer having more voids than the inner side of the base layer. 
     Furthermore, a main component of a material of the base layer of each of the external electrodes may be Cu. Each of the external electrodes may include a Ni plating layer formed outside the base layer and containing Ni; and a Sn plating layer formed on the Ni plating layer and containing Sn. 
     Each of the external electrodes may further include an electrical conductive resin layer formed on the electrical conductive layer. 
     In this case, the electrical conductive layer may include a base layer formed on the element body and connected to the internal electrodes, the base layer including Ni; and a Cu plating layer formed on the base layer, the Cu plating layer having an outer side and an inner side, the outer side of the Cu plating layer being farther from the element body than the inner side of the Cu plating layer, the outer side of the Cu plating layer having more voids than the inner side of the Cu plating layer. Each of the external electrodes may include a Ni plating layer formed on the electrical conductive resin layer and containing Ni; and a Sn plating layer formed on the Ni plating layer and containing Sn. 
     Alternatively, the electrical conductive layer may include a base layer formed on the element body and connected to the internal electrodes, the base layer containing Cu, the base layer having an outer side and an inner side, the outer side of the base layer being farther from the element body than the inner side of the base layer, the outer side of the base layer having more voids than the inner side of the base layer. Each of the external electrodes may include a Ni plating layer formed on the electrical conductive resin layer and containing Ni; and a Sn plating layer formed on the Ni plating layer and containing Sn. 
     According to another aspect of the present invention, there is provided a circuit board arrangement including a circuit board; and any of the above-described ceramic electronic component mounted on the circuit board. The ceramic electronic component may be connected to the circuit board via solder layers adhered to the external electrodes. 
     According to another aspect of the present invention, there is provided a method of manufacturing a ceramic electronic component. The method may include forming an element body that includes a dielectric and internal electrodes; forming electrical conductive layers on the element body, the electrical conductive layers being connected to the internal electrodes, each of the electrical conductive layers having an outer side and an inner side, the outer side being farther from the element body than the inner side, the outer side having more voids than the inner side; and forming a plating layer containing Ni outside each of the electrical conductive layers. 
     Forming the electrical conductive layers may include applying a base material for external electrodes to multiple surfaces of the element body, the base material containing a metal; sintering the base material to form base layers forming the electrical conductive layers of the external electrodes, each of the base layers having an outer side and an inner side; oxidizing the metal of the base layers to form metal oxide portions in the base layers in such a manner that the outer side of each of the base layers are exposed to an oxidizing atmosphere, so that the outer side has more metal oxide portions than the inner side; and forming voids in the base layer by removing metal oxide from the metal oxide portions. 
     Forming the electrical conductive layers may include forming base layers of the electrical conductive layers of the external electrodes; forming innermost plating layers on the base layers, the innermost plating layers containing a metal, each of the innermost plating layers having an outer side and an inner side; oxidizing the metal of the innermost plating layers to form metal oxide portions in the innermost plating layers in such a manner that the outer side of each of the innermost plating layers are exposed to an oxidizing atmosphere, so that the outer side has more metal oxide portions than the inner side; and forming voids in the innermost plating layer by removing metal oxide from the metal oxide portions. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a perspective view showing a multilayer ceramic capacitor according to a first embodiment of the present invention; 
         FIG. 2A  is a cross-sectional view of the multilayer ceramic capacitor of  FIG. 1  taken along the longitudinal direction thereof; 
         FIG. 2B  is a cross-sectional view showing another example of the multilayer ceramic capacitor of  FIG. 1  taken along the longitudinal direction thereof; 
         FIG. 3  is a flowchart showing a method of manufacturing a multilayer ceramic capacitor according to the first embodiment; 
         FIGS. 4A to 4L  are cross-sectional views used for describing the method of manufacturing the multilayer ceramic capacitor according to the first embodiment; 
         FIG. 5  is a cross-sectional view showing a circuit board arrangement according to a second embodiment of the present invention, on which a multilayer ceramic capacitor is mounted; 
         FIG. 6  is a cross-sectional view showing a multilayer ceramic capacitor according to a third embodiment of the present invention taken along the longitudinal direction thereof; 
         FIG. 7  is a flowchart showing a method of manufacturing a multilayer ceramic capacitor according to the third embodiment; 
         FIG. 8  is a cross-sectional view showing a multilayer ceramic capacitor according to a fourth embodiment of the present invention taken along the longitudinal direction thereof; 
         FIG. 9  is a cross-sectional view showing a multilayer ceramic capacitor according to a fifth embodiment of the present invention taken along the longitudinal direction thereof; and 
         FIG. 10  is a perspective view showing a ceramic electronic component according to a sixth embodiment of the present invention. 
     
    
    
     DESCRIPTION OF EMBODIMENTS 
     Embodiments of the present invention will now be described with reference to the accompanying drawings. The following embodiments are not intended to limit the present invention. The combination of all the features described in each of the embodiments is not absolutely necessary for the present invention. The configuration of each embodiment may be modified and/or changed depending upon designs, specifications, and various conditions of an apparatus and a device to which the present invention is applied (use conditions, use environment, and the like). The technical scope of the invention is defined by the appended claims and is not limited by the following embodiments. Furthermore, parts, components, and elements shown in the drawings used in connection with the following description may be different from actual parts, components, and elements in the structure, scale, and shape for the sake of easier understanding of the parts, components, and elements. 
     First Embodiment 
       FIG. 1  is a perspective view showing a multilayer ceramic capacitor  1 A according to a first embodiment of the present invention.  FIG. 2A  is a cross-sectional view of the multilayer ceramic capacitor  1 A of  FIG. 1  taken along the longitudinal direction thereof. In  FIG. 1 , an area R 1  of an innermost plating layer  9 A is shown in enlargement. In  FIG. 2A , a cross sectional region R 2  of an external electrode  6 A is shown in enlargement. In this embodiment, a multilayer ceramic capacitor is taken as an example as a ceramic electronic component. 
     In  FIGS. 1 and 2A , the multilayer ceramic capacitor  1 A includes an element body (element assembly)  2  and external electrodes (outer electrodes)  6 A and  6 B. The element body  2  has a laminate (or stack)  2 A, a lower cover layer  5 A, and an upper cover layer  5 B. The laminate  2 A has internal electrode layers (inner electrode layers)  3 A, other internal electrode layers  3 B, and dielectric layers  4  interposed between neighboring internal electrode layers  3 A and  3 B. 
     The lowermost layer of the laminate  2 A is covered with the lower cover layer  5 A, and the uppermost layer of the laminate  2 A is covered with the upper cover layer  5 B. The internal electrode layers  3 A and  3 B are alternately stacked in such a manner that the dielectric layers  4  are interposed therebetween. Although  FIGS. 1 and 2A  show an example in which eleven internal electrode layers  3 A and  3 B are stacked, the number of stacked internal electrode layers  3 A and  3 B is not limited. The shape of the element body  2  may be a substantially rectangular parallelepiped shape, and the shape of the laminate  2 A may also be a substantially rectangular parallelepiped shape. 
     In the following description, the direction perpendicularly passing through the two side surfaces of the element body  2  may be referred to as a longitudinal direction DL, the direction perpendicularly passing through the front and rear surfaces of the element body  2  may be referred to as a width direction DW, and the direction perpendicularly passing through the top and bottom surfaces of the element body  2  may be referred to as a stacking direction (height direction) DS. The lower surface of the element body  2  can face the mounting surface of a circuit board to which the multilayer ceramic capacitor  1 A is mounted. The element body  2  may be chamfered along the respective edges of the element body  2 . In this case, the element body  2  has curved surfaces R at the edges chamfered. 
     The external electrodes  6 A and  6 B are located on opposite sides of the element body  2 , respectively, so that the external electrodes  6 A and  6 B are spaced apart (separated) from each other. Each of the external electrodes  6 A and  6 B continuously covers the top surface, the side surface, and the bottom surface of the element body  2 . Each of the external electrodes  6 A and  6 B may also cover the front surface and the rear surface of the element body  2 . 
     In the longitudinal direction DL, the internal electrode layers  3 A and  3 B are arranged alternately at different positions in the laminate  2 A. The internal electrode layers  3 A can be closer to the left side surface of the element body  2  than the internal electrode layers  3 B, whereas the internal electrode layers  3 B can be closer to the right side surface of the element body  2  than the internal electrode layers  3 A. Left ends of the internal electrode layers  3 A are exposed at the left ends of the dielectric layers  4  and at the left side surface in the longitudinal direction DL of the element body  2  and are connected to the external electrode  6 A. Right ends of the internal electrode layers  3 B are exposed at the right ends of the dielectric layers  4  and at the right side surface in the longitudinal direction DL of the element body  2  and are connected to the external electrode  6 B. 
     On the other hand, in the width direction DW, which is perpendicular to the longitudinal direction DL perpendicularly passing through the two side surfaces of the element body  2 , ends of the internal electrode layers  3 A and  3 B are covered with the dielectric material that forms the dielectric layers  4 . In the width direction DW, both ends of the internal electrode layers  3 A may be aligned with both ends of the internal electrode layers  3 B. 
     The thickness of each of the internal electrode layers  3 A, the internal electrode layers  3 B, and the dielectric layers  4  in the stacking direction DS may be in a range from 0.05 μm to 5 μm for example, may be 0.3 μm. 
     The material of the internal electrode layers  3 A and  3 B may be a metal, for example, Cu (copper), Fe (iron), Zn (zinc), Al (aluminum), Sn (tin), Ni (nickel), Ti (titanium), Ag (silver), Au (gold), Pt (platinum), Pd (palladium), Ta (tantalum), or W (tungsten), or may be an alloy containing at least one of the metals. 
     The main component of the material of the dielectric layers  4  may be, for example, a ceramic material having a perovskite structure. The main component may be contained in a ratio of 50 at % or more. The ceramic material of the dielectric layers  4  may be, for example, barium titanate, strontium titanate, calcium titanate, magnesium titanate, barium strontium titanate, barium calcium titanate, calcium zirconate, barium zirconate, calcium titanate zirconate, or titanium oxide. 
     The main component of the material of the lower cover layer  5 A and the upper cover layer  5 B may be, for example, a ceramic material. The main component of the ceramic material of the lower cover layer  5 A and the upper cover layer  5 B may be the same as the main component of the ceramic material of the dielectric layers  4 . 
     The thicknesses of the lower cover layer  5 A and the upper cover layer  5 B are preferably 5 μm or more and 30 μm or less. 
     The external electrode  6 A is connected to the internal electrode layers  3 A, whereas the external electrode  6 B is connected to the internal electrode layers  3 B. 
     Each of the external electrodes  6 A and  6 B has an electrical conductive layer  8  and a plating layer  9  that includes Ni. The conductive layer  8  has many voids KJ in such a manner that the outer side M 2  farther from the element body  2  includes more voids KJ than the inner side M 1  closer to the element body  2  as shown in the cross section of  FIG. 2A . In other words, the voids KJ can be distributed non-uniformly in the single conductive layer  8 . The inner side M 1  is adjacent to the boundary between the conductive layer  8  and the element body  2 , whereas the outer side M 2  is adjacent to the boundary between the conductive layer  8  and the plating layer  9 . The plating layer  9  is formed on the conductive layer  8 . The conductive layer  8  has a base layer  7  and an innermost plating layer  9 A having the outer side M 2  in which more voids KJ are disposed. The plating layer  9  has an intermediate plating layer  9 B including Ni and an outermost plating layer  9 C that is solder-wettable. 
     The base layers  7  of the external electrodes  6 A and  6 B are formed on opposite surfaces of the element body  2  so as to be separated from each other in the longitudinal direction DL. Each of the base layers  7  continuously covers the top surface, the side surface, and the bottom surface of the element body  2 . Each of the base layers  7  may also cover the front surface and the rear surface of the element body  2 . 
     The electrical conductive material of the base layer  7  may be a metal, for example, Cu, Fe, Zn, Al, Ni, Pt, Pd, Ag, Au, and Sn, or may be an alloy containing at least one of the metals. The base layer  7  may further include co-material particles. Here, the term “particle” is meant to include not only an individual small particle, but also a block formed by a combination of multiple small particles after the sintering process, which will be described later. The co-material in the base layer  7  reduces the difference in thermal expansion coefficients of the element body  2  and the base layer  7  to alleviate thermal stress exerted in the base layer  7 . The main component of the co-material is, for example, a ceramic component that is the same as the main component of the material of the dielectric layers  4 . The base layer  7  may also include a glass component. The glass in the base layer  7  component can densify the base layer  7 . The glass component may be, for example, an oxide of Ba (barium), Ca (calcium), Zn, Al, Si (silicon), Mg (magnesium), B (boron), or the like. 
     The base layer  7  is preferably composed of a sintered metal that was sintered after a metal paste (material of the base layer  7 ) is applied to the element body  2 . This enables the base layer  7  to have a large thickness while ensuring the adhesiveness between the element body  2  and the base layer  7 , and ensures the strength of external electrode  6 A and  6 B while ensuring the electrical conductivity of the external electrodes  6 A and  6 B connected to the internal electrode layers  3 A and  3 B. In a case in which the base layer  7  is sintered simultaneously with the element body  2 , Ni is preferable for the main component of the material of the base layer  7 . However, the base layer  7  may be formed by sintering the metal paste (material of the base layer  7 ) after the element body  2  is sintered. 
     An innermost plating layer  9 A is formed on the base layer  7 . Multiple voids KJ are provided in the innermost plating layer  9 A and can be distributed over surface directions of the innermost plating layer  9 A entirely. In cross sections as shown in  FIG. 2A , each void KJ is surrounded by the material of the innermost plating layer  9 A. The voids KJ may be distributed on the outer side  9 Ao of the innermost plating layer  9 A in a layered manner over surface directions entirely. The voids KJ in the innermost plating layer  9 A can be provided in opposite sides for the element body  2 . That is to say, the voids KJ can be provided on the two sides in the stacking direction DS, the two sides in the longitudinal direction DL, and the two sides in the width direction DW in  FIG. 1 . The outer side  9 Ao of the innermost plating layer  9 A is the farther side (i.e., the opposite side) from the element body  2 , on which the intermediate plating layer  9 B is formed. Accordingly, the void KJ may be provided not only on the two outer sides  9 Ao in the longitudinal direction DL, but also on the two outer sides in the width direction DW, and on the two outer sides in the stacking direction DS. The conductive layer  8  may also include an oxide of the material of the conductive layer  8  disposed at positions inside the voids KJ or being in contact with the voids KJ. 
     Before the intermediate plating layer  9 B is formed on the external surface of the innermost plating layer  9 A, the metal contained in the innermost plating layer  9 A is non-uniformly oxidized while exposing the external surface of the innermost plating layer  9 A to an oxidizing atmosphere, and then, the oxide of the metal is removed, so that the voids KJ are formed on the outer side  9 Ao of the innermost plating layer  9 A. In order to non-uniformly oxidize the metal contained in the innermost plating layer  9 A, the outer side  9 Ao of the innermost plating layer  9 A can be rapidly oxidized. The voids KJ can be distributed in a spongy or porous manner on the outer side  9 Ao of the innermost plating layer  9 A. That is, the outer side  9 Ao includes more voids KJ than the inner side  9 Ai in the innermost plating layer  9 A. 
     The main component of the material of the innermost plating layer  9 A can be a metal, for example, Cu, Fe, Zn, Sn, Pb, or Cr, or may be an alloy containing at least one of the metals. The innermost plating layer  9 A is, for example, a Cu plating layer. The Cu plating layer  9 A can improve the adhesion of the plating layer  9  to the base layer  7  and can ensure good electrical conductivity. In addition, by using a Cu plating layer as the innermost plating layer  9 A, voids KJ can be formed easily on the outer side  9 Ao of the innermost plating layer  9 A. 
     The thickness of the innermost plating layer  9 A is preferably from 2 μm to 15 μm. The voids KJ are preferably located in a range from 0.1 μm to 3.0 μm in the thickness direction from the external surface of the innermost plating layer  9 A. It is preferable that the length of each void KJ in surface directions be greater than the length thereof in the thickness direction of the innermost plating layer  9 A. In addition, it is preferable that the innermost plating layer  9 A include more voids KJ of which the length in surface directions is greater than that in the thickness direction than voids KJ of which the length in surface directions is less than that in the thickness direction. The length of the voids KJ in the longitudinal direction thereof is preferably from 0.5 μm to 6.5 μm. It is preferable that, in the innermost plating layer  9 A, voids KJ of which the length in surface directions is four times or more than the length in the thickness direction account for at least 50% of all of the voids KJ. 
     The intermediate plating layer  9 B is formed on the innermost plating layer  9 A. The intermediate plating layer  9 B is, for example, a Ni plating layer. The Ni plating layer  9 B can improve the heat resistance of the external electrode  6 A and  6 B during soldering. 
     The outermost plating layer  9 C is formed on the intermediate plating layer  9 A. The outermost plating layer  9 C is, for example, a Sn plating layer. The Sn plating layer  9 C can improve wettability of the solder for the plating layer  9 . 
     In the embodiment, by providing voids KJ on the outer side  9 Ao of the innermost plating layer  9 A, diffusion of hydrogen generated when forming the intermediate plating layer  9 B on the innermost plating layer  9 A can be blocked by the voids KJ. Hydrogen diffuses from the intermediate plating layer  9 B, but is unlikely to pass through the voids KJ in the innermost plating layer  9 A, so that hydrogen is unlikely to reach the element body  2 . Thus, it is possible to prevent the hydrogen generated when forming the intermediate plating layer  9 B on the innermost plating layer  9 A from diffusing into the element body  2 , to reduce the hydrogen reduction at the dielectric layers  4  between the internal electrode layers  3 A and  3 B, and to minimize deterioration of electrical insulation of the dielectric layers  4 . 
     In addition, by disposing the voids KJ in a range from 0.1 micrometers to 3.0 micrometers in the thickness direction from the external surface of the innermost plating layer  9 A (more voids KJ are disposed in the outer side  9 Ao of the innermost plating layer  9 A than the inner side  9 Ai), the diffusion of hydrogen can be effectively blocked at the positions of the voids KJ while restricting increase in the thickness of the external electrodes  6 A and  6 B. Since the concentration of hydrogen is higher in the outer side  9 Ao near the intermediate plating layer  9 B than the inner side  9 Ai near the element body  2 , the diffusion of hydrogen can be effectively reduced by arranging the voids KJ in the outer side  9 Ao. 
     In addition, by making the length of the voids KJ in surface directions greater than the length thereof in the thickness direction of the innermost plating layer  9 A, the diffusion of hydrogen from the side on the intermediate plating layer  9 B to the element body  2  can be effectively blocked by the voids KJ. 
       FIG. 2B  is a cross-sectional view showing another example of the multilayer ceramic capacitor of  FIG. 1  taken along the longitudinal direction thereof. 
     As shown in  FIG. 2B , the multilayer ceramic capacitor  1 Z has external electrodes  6 ZA and  6 ZB instead of the external electrodes  6 A and  6 B of the multilayer ceramic capacitor  1 A of  FIG. 2A . Each of the external electrodes  6 ZA and  6 ZB has an electrical conductive layer  8 Z instead of the electrical conductive layer  8  in  FIG. 2A . The conductive layer  8 Z has an innermost plating layer  9 ZA instead of the innermost plating layer  9 A of  FIG. 2A . 
     The innermost plating layer  9 ZA has multiple voids KZ and multiple metal oxide portions MZ. Multiple voids KJ are provided in the innermost plating layer  9 ZA and can be distributed over surface directions of the innermost plating layer  9 ZA entirely. In cross sections as shown in  FIG. 2B , each void KJ is surrounded by the material of the innermost plating layer  9 ZA. The voids KJ may be distributed on the outer side  9 Ao of the innermost plating layer  9 ZA in a layered manner over surface directions entirely. The voids KJ in the innermost plating layer  9 ZA can be provided in opposite sides for the element body  2 . That is to say, the voids KJ can be provided on the two sides in the stacking direction DS, the two sides in the longitudinal direction DL, and the two sides in the width direction DW in  FIG. 1 . 
     The metal oxide portions MZ are formed of an oxide of a metal contained in the innermost plating layer  9 ZA. For example, in a case in which the innermost plating layer  9 ZA is made from Cu, the metal oxide portions MZ are made from CuO or Cu 2 O. The metal oxide portions MZ are disposed at positions inside the voids KJ or being in contact with the voids KJ. The metal oxide portions MZ inside the voids KJ or in contact with the voids KJ captures hydrogen and further reduces diffusion of hydrogen into the element body  2 . 
       FIG. 3  is a flowchart showing a method of manufacturing a multilayer ceramic capacitor according to the first embodiment.  FIGS. 4A to 4L  are cross-sectional views showing an exemplary method of manufacturing the multilayer ceramic capacitor according to the first embodiment. For the sake of illustration,  FIG. 4C  to  FIG. 4L  show only three internal electrode layers  3 A and three internal electrode layers  3 B laminated alternately in such a manner that the dielectric layers  4  are interposed therebetween. In  FIGS. 4I to 4K , a cross sectional region R 2 ′ of the conductive layer  8  is shown in enlargement. In  FIG. 4L , a cross sectional region R 2  of the external electrode  6 A is shown in enlargement. 
     In Step S 1  of  FIG. 3  (mixing step), an organic binder and an organic solvent, as a dispersant and a forming aid, are added to a dielectric material powder, and pulverized and mixed to produce a muddy slurry. The dielectric material powder includes, for example, a ceramic powder. The dielectric material powder may include an additive or additives. The additive(s) may be, for example, Mg, Mn, V, Cr, Y, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Co, Ni, Li, B, Na, K or Si oxide, or glass. The organic binder is, for example, a polyvinyl butyral resin or a polyvinyl acetal resin. The organic solvent is, for example, ethanol or toluene. 
     Next, in Step S 2  of  FIG. 3  (slurry application step), as shown in  FIG. 3A , a green sheet  24  is manufactured. Specifically, the slurry containing the ceramic powder is applied onto a carrier film in a sheet form and dried to manufacture the green sheet  24 . The carrier film is, for example, a PET (polyethylene terephthalate) film. The application of the slurry can be conducted with the use of, for example, a doctor blade method, a die coater method, or a gravure coater method. Step S 2  is repeated to prepare a plurality of green sheets  24 . 
     Next, in Step S 3  of  FIG. 3  (printing step), as shown in  FIG. 4B , a conductive paste, which will become an internal electrode layer, is applied in a predetermined pattern onto each of the green sheets  24 , on which internal electrode layers  3 A or  3 B shown in  FIG. 1  are to be placed, among the green sheets prepared in Step S 1  to form internal electrode patterns  23  on the green sheets  24 . In Step S 3 , it is possible to form a plurality of internal electrode patterns  23  on each single green sheet  24  such that the internal electrode patterns  23  are separated from each other in the longitudinal direction of the green sheet  24 . 
     The conductive paste for the internal electrode layers includes a powder of the metal used as the material of the internal electrode layers  3 A and  3 B. For example, if the metal used as the material of the internal electrode layers  3 A and  3 B is Ni, the conductive paste for the internal electrode layers includes a powder of Ni. The conductive paste for the internal electrode layers also includes a binder, a solvent, and, if necessary, an auxiliary agent. The conductive paste for the internal electrode layers may include, as a co-material, a ceramic material having a main component that has the same composition as that of the main component of the material of the dielectric layers  4 . 
     The application of the conductive paste for the internal electrode layers may be conducted with the use of a screen printing method, an inkjet printing method, or a gravure printing method. Thus, Step S 3  may be referred to as a printing step. In this manner, a plurality of green sheets  24  that have the internal electrode patterns  23  thereon are prepared. 
     Next, in Step S 4  of  FIG. 3  (laminating step), as shown in  FIG. 4C , the green sheets  24  on which the internal electrode patterns  23  are formed and the green sheets  25 A and  25 B on which the internal electrode patterns  23  are not formed are laminated in a predetermined order to create a block  30  of the green sheets. The green sheets  25 A and  25 B on which the internal electrode patterns  23  are not formed are used as the outer layers (the lower cover layer  5 A and the upper cover layer  5 B). The thickness of the green sheets  25 A and  25 B is greater than that of the green sheets  24 . 
     The green sheets  24  having the internal electrode patterns  23 A or  23 B thereon are classified into two groups, i.e., the green sheets  24  having the internal electrode patterns  23 A (which will form the internal electrode layer  3 A) thereon and the green sheets  24  having the internal electrode patterns  23 B (which will form the internal electrode layer  3 B) thereon. The green sheets  24  having the internal electrode patterns  23 A thereon and the green sheets  24  having the internal electrode patterns  23 B thereon are stacked alternately in the laminating direction such that the internal electrode patterns  23 A on the green sheet  24  and the internal electrode patterns  23 B on the next or adjacent green sheet  24  are alternately shifted in the longitudinal direction of the green sheet  24 . 
     Furthermore, three types of portions are defined in the green sheet block  30 . Specifically, the green sheet block  30  includes a portion in which only the internal electrode patterns  23 A are stacked in the stacking direction, a portion in which the internal electrode patterns  23 A and  23 B are stacked alternately in the stacking direction, and a portion in which only the internal electrode patterns  23 B are stacked in the stacking direction. 
     Next, in Step S 5  of  FIG. 3  (pressure bonding step), as shown in  FIG. 4D , the laminate block  30  obtained in the laminating step of Step S 4  of  FIG. 3  is pressed such that the green sheets  24 ,  25 A, and  25 B are pressure-bonded. Pressing the laminate block  30  may be conducted by, for example, hydrostatically pressing the laminate block  30 . 
     In Step S 6  of  FIG. 3  (cutting step), as shown in  FIG. 4E , the pressed laminate block  30  is cut such that the block  30  is separated into a plurality of element bodies, each of which has a rectangular parallelepiped shape. Each element body has six surfaces. The cutting of the laminate block  30  is conducted at the portions in which only the internal electrode patterns  23 A are stacked in the stacking direction, and the portions in which only the internal electrode patterns  23 B are stacked in the stacking direction, as indicated by a plurality of vertical broken lines  27 . The cutting of the laminate block  30  may be conducted by, for example, blade dicing or a similar method. The resulting element bodies  2 ′ are shown in  FIG. 4F . 
     As illustrated in  FIG. 4F , the internal electrode layers  3 A and  3 B are alternately laminated in such a manner that the dielectric layers  4  are interposed therebetween in each of the individual element bodies  2 ′. In addition, each element body  2 ′ has the lower cover layer  5 A and the upper cover layer  5 B. The internal electrode layers  3 A are exposed on one side surface of each element body  2 ′, and the internal electrode layers  3 B are exposed on the other side surface of each element body  2 ′. In  FIG. 4F , an element body  2 ′ is enlarged in the longitudinal direction. 
     In Step S 7  of  FIG. 3  (chamfering step), as shown in  FIG. 4Q  corners of each element body  2 ′ are chamfered, so that the element body  2  having curved surfaces R at corners are formed. For example, barrel polishing can be used for chamfering the element bodies  2 ′. 
     Next, in Step S 8  of  FIG. 3  (binder removing step), the binder contained in each of the element bodies  2  obtained in Step S 7  of  FIG. 3  is removed. The removal of the binder is conducted by, for example, heating the element bodies  2  in an N 2  atmosphere at about 350 degrees Celsius. 
     Next, in Step S 9  of  FIG. 3  (step of applying a paste for the base layers), a conductive paste for the base layers (underlayers)  7  is applied to both side surfaces of each element body  2  from which the binder is removed in Step S 8  of  FIG. 3  and is applied to the remaining four surfaces (upper, lower, front, and rear surfaces) of the element body  2 , which are adjacent to the respective side surfaces. For example, a dipping method can be used to apply the conductive paste for the base layers. Then, the conductive paste is dried. The conductive paste for the base layers  7  includes a powder or filler of the metal used as the conductive material of the base layers  7 . For example, when the metal used as the conductive material of the base layers  7  is Ni, the conductive paste for the base layers includes a powder or filler of Ni. The conductive paste for the base layers also includes, as the co-material, a ceramic component, which is the main component of the material of the dielectric layers  4 , for example. Particles of oxide ceramics mainly composed of barium titanate (0.8 micrometers to 4 micrometers in D50 particle diameter), for example, are mixed in the conductive paste for the base layers, as the co-material. The conductive paste for the base layers further includes a binder and a solvent. 
     Next, in Step S 10  of  FIG. 3  (sintering step), as shown in  FIG. 4H , the element bodies  2 , on which the conductive paste for the base layers was applied in Step S 9  of  FIG. 3 , undergo the sintering process such that the internal electrode layers  3 A and  3 B are integrated with the dielectric layers  4  in each element body  2  and the base layers  7  are cured and integrated with the element body  2 . The sintering of the element bodies  2  is conducted in, for example, a sintering furnace in a temperature range from 1000 degrees Celsius to 1400 degrees Celsius for ten minutes to two hours. 
     If a base metal such as Ni or Cu is used as the material of the internal electrode layers  3 A and  3 B, the sintering process may be conducted in the sintering furnace while the interior of the sintering furnace is kept to a reducing atmosphere in order to prevent oxidation of the internal electrode layers  3 A and  3 B. 
     Next, in Step S 11  of  FIG. 3  (step of forming the innermost plating layers), as shown in  FIG. 4I , the innermost plating layers  9 A are formed on the base layers  7 . In this case, the innermost plating layers  9 A can be formed by that the element body  2 , on which the base layers  7  are formed, is housed in a barrel and immersed in a plating solution in the barrel, and the barrel is rotated and energized. 
     Then, in Step S 12  of  FIG. 3  (surface oxidation step), as shown in  FIG. 4J , each element body  2 , in which the innermost plating layers  9 A are formed on the base layers  7 , is heated under a non-oxidizing atmosphere, and then exposed to an oxidizing atmosphere while maintaining the high temperature. Then, each element body  2  is returned to the non-oxidizing atmosphere and cooled. By such treatment, the outer side  9 Ao of each innermost plating layer  9 A is rapidly oxidized under the high temperature, and thus the metal oxide portions MZ are formed on the outer side  9 Ao of the innermost plating layer  9 A. The time and temperature for exposing the innermost plating layer  9 A to the oxidizing atmosphere can be set so that the outer side  9 Ao of the innermost plating layer  9 A is non-uniformly oxidized. Accordingly, the process can be stopped before the outer side  9 Ao of the innermost plating layer  9 A is oxidized uniformly. 
     For example, in the oxidation process of the outer side  9 Ao of the innermost plating layer  9 A, each element body  2  is heated to 500 degrees Celsius under an N 2  atmosphere, and then exposed to the atmosphere Earth for two minutes while maintaining this temperature. Then, each element body  2  is returned to the N 2  atmosphere and cooled. 
     Next, in Step S 13  of  FIG. 3  (void forming step), as shown in  FIG. 4K , the metal oxide in the portions MZ on the outer side  9 Ao of the innermost plating layer  9 A is removed by a scheme such as wet etching. In wet etching of the metal oxide in the portions MZ, for example, a dilute sulfuric acid solution can be used. Since the metal oxide portions MZ not only exist on the outer surface of the innermost plating layer  9 A, but also intersect one another in the innermost plating layer  9 A, the voids KJ can be formed in the innermost plating layer  9 A by removing the metal oxide from the portions MZ. 
     However, the metal oxide may be partially left as shown in  FIG. 2A . In a case in which the metal oxide portions MZ are disposed inside the voids KJ or are in contact with the voids KJ, the metal oxide portions MZ can capture hydrogen and further reduces diffusion. 
     The size of the voids KJ can be from 0.5 micrometers to 6.5 micrometers. The distance in the thickness direction from the outer surface of the innermost plating layer  9 A to the voids KJ can be from 0.1 micrometers to 3.0 micrometers. The percentage of void in the outer side  9 Ao is greater than that in the inner side  9 Ai in the innermost plating layer  9 A. The ratio of the length of the voids KJ in surface directions to the length of the voids KJ in the thickness direction of the innermost plating layer  9 A can be from one to ten. That is to say, the innermost plating layer  9 A includes more voids KJ of which the length in parallel to the outer and inner surfaces of the innermost plating layer  9 A is greater than the length perpendicular to the outer and inner surfaces of the innermost plating layer  9 A than voids KJ of which the length in in parallel to the outer and inner surfaces of the innermost plating layer  9 A is less than the length perpendicular to the outer and inner surfaces of the innermost plating layer  9 A. 
     Next, in Step S 14  of  FIG. 3  (step of forming intermediate and outermost plating layers), as shown in  FIG. 4L , the intermediate plating layer  9 B and the outermost plating layer  9 C are sequentially formed on each innermost plating layer  9 A. The intermediate plating layers  9 B can be formed by immersing the element body  2 , on which the innermost plating layers  9 A having the voids KJ are formed, in a Ni plating solution in a barrel and by energizing and rotating the barrel. The outermost plating layers  9 C can be formed by immersing the element body  2 , on which the intermediate plating layers  9 B are formed, in a Sn plating solution in a barrel and by energizing and rotating the barrel. 
     By providing voids KJ on the outer side  9 Ao of the innermost plating layer  9 A, the hydrogen generated when forming the intermediate plating layer  9 B containing Ni can be effectively prevented from diffusing into the element body  2 , and the degradation of insulation of the dielectric layers  4  can be minimized. Such an effect of blocking the diffusion of hydrogen is achieved not only during the process of forming the intermediate plating layer  9 B, but also achieved for the hydrogen remaining in the intermediate plating layer  9 B after forming the intermediate plating layer  9 B. Although some portions of the intermediate plating layer  9 B may enter into some portions of the voids KJ, there is no problem in performance of the product. 
     Second Embodiment 
       FIG. 5  is a cross-sectional view showing a circuit board arrangement according to a second embodiment of the present invention, on which a multilayer ceramic capacitor is mounted. The circuit board arrangement includes a circuit board  11  and the multilayer ceramic capacitor  1 A mounted on the circuit board  11 . 
     As shown in  FIG. 5 , land electrodes  12 A and  12 B are formed on the circuit board  11 . The circuit board  11  may be a printed circuit board or a semiconductor board formed from, for example, Si. The multilayer ceramic capacitor  1 A is connected to the land electrodes  12 A and  12 B via solder layers  13 A and  13 B attached to the outermost plating layers  9 C of the external electrodes  6 A and  6 B, respectively. 
     By providing voids KJ in the innermost plating layers  9 A, stress exerted in the exterior electrodes  6 A and  6 B can be absorbed by the voids KJ. Therefore, when external stress is applied to the external electrodes  6 A and  6 B due to deflection or expansion and contraction of the circuit board  11 , transmission of the stress to the element body  2  through the external electrodes  6 A and  6 B can be minimized, so that cracking of the element body  2  can be minimized. 
     Third Embodiment 
       FIG. 6  is a cross-sectional view showing a multilayer ceramic capacitor according to a third embodiment of the present invention taken along the longitudinal direction thereof. In  FIG. 6 , a cross sectional region R 3  of an external electrode  6 A′ is shown in enlargement. 
     In  FIG. 6 , the multilayer ceramic capacitor  1 B has external electrodes  6 A′ and  6 B′ instead of the external electrodes  6 A and  6 B of  FIG. 2A . 
     The external electrodes  6 A′ and  6 B′ are located on opposite sides of the element body  2 , respectively, so that the external electrodes  6 A′ and  6 B′ are spaced apart (separated) from each other. Each of the external electrodes  6 A′ and  6 B′ continuously covers the top surface, the side surface, and the bottom surface of the element body  2 . Each of the external electrodes  6 A′ and  6 B′ may also cover the front surface and the rear surface of the element body  2 . 
     The external electrode  6 A′ is connected to the internal electrode layers  3 A, whereas the external electrode  6 B′ is connected to the internal electrode layers  3 B. 
     Each of the external electrodes  6 A and  6 B has a base layer  7 ′ that is an electrical conductive layer, a plating layer  9 B′ that includes Ni, and an outermost plating layer  9 C′ that is solder-wettable. The base layer  7 ′ has many voids KJ′ in such a manner that the outer side M 2 ′ farther from the element body  2  includes more voids KJ′ than the inner side M 1 ′ closer to the element body  2  as shown in the cross section of  FIG. 6 . The inner side M 1 ′ is adjacent to the boundary between the base layer  7 ′ and the element body  2 , whereas the outer side M 2 ′ is adjacent to the boundary between the base layer  7 ′ and the plating layer  9 B′. 
     The base layers  7 ′ of the external electrodes  6 A′ and  6 B′ are formed on opposite surfaces of the element body  2  so as to be separated from each other in the longitudinal direction DL. Each of the base layers  7 ′ continuously covers the top surface, the side surface, and the bottom surface of the element body  2 . Each of the base layers  7 ′ may also cover the front surface and the rear surface of the element body  2 . 
     Multiple voids KJ′ are provided in the base layer  7 ′ and can be distributed over surface directions of the base layer  7 ′ entirely. The voids KJ may be distributed on the outer side  7   o ′ of the base layer  7 ′ in a layered manner over surface directions entirely. The base layer  7 ′ can include a metal capable of forming an oxide corresponding to the shapes of the voids KJ′. The voids KJ in the base layer  7 ′ can be provided in opposite sides for the element body  2 . The outer side  7   o ′ of the base layer  7 ′ is the side on which the plating layer  9 B′ is formed. Accordingly, the void KJ may be provided not only on the two outer sides  7   o ′ in the longitudinal direction DL, but also on the two outer sides in the width direction DW, and on the two outer sides in the stacking direction DS. 
     Before the plating layer  9 B′ is formed on the outer surface of the base layer  7 ′, the metal contained in the base layer  7 ′ is non-uniformly oxidized while exposing the external surface of the base layer  7 ′ to an oxidizing atmosphere, and then, the oxide of the metal is removed, so that the voids KJ′ are formed on the outer side  7   o ′ of the base layer  7 ′. In order to non-uniformly oxidize the metal contained in the base layer  7 ′, the outer side  7   o ′ of the base layer  7 ′ can be rapidly oxidized. The voids KJ′ can be distributed in a spongy or porous manner on the outer side  7   o ′ of the base layer  7 ′. That is, the outer side  7   o ′ includes more voids KJ than the inner side  7   i ′ in the base layer  7 ′. 
     The main component of the material of the base layer  7 ′ can be a metal, for example, Cu, Fe, Zn, Sn, Pb, or Cr, or may be an alloy containing at least one of the metals. The base layer  7 ′ is, for example, a Cu plating layer. The Cu base layer  7 ′ can improve the adhesion of the plating layer  9 B′ to the base layer  7  and can ensure good electrical conductivity. In addition, by using a Cu layer as the base layer  7 ′, voids KJ′ can be formed easily on the outer side  7   o ′ of the base layer  7 ′. 
     The base layer  7 ′ may further include co-material particles. The main component of the co-material is, for example, a ceramic component that is the same as the main component of the material of the dielectric layers  4 . The base layer  7 ′ may include a glass component. The base layer  7 ′ is preferably a sintered layer that was sintered after a metal paste (material of the base layer  7 ′) is applied to the element body  2 . 
     The thickness of the base layer  7 ′ is preferably from 2 micrometers to 50 micrometers. The voids KJ′ are preferably located in a range from 0.1 micrometers to 3.0 micrometers in the thickness direction from the external surface of the base layer  7 ′. It is preferable that the length of each void KJ′ in surface directions be greater than the length thereof in the thickness direction of the base layer  7 ′. In addition, it is preferable that the base layer  7 ′ include more voids KJ′ of which the length in surface directions is greater than that in the thickness direction than voids KJ′ of which the length in surface directions is less than that in the thickness direction. The length of the voids KJ′ in the longitudinal direction thereof is preferably from 0.5 micrometers to 6.5 micrometers. It is preferable that, in the base layer  7 ′, voids KJ′ of which the length in surface directions is four times or more than the length in the thickness direction account for at least 50% of the total voids KJ′. 
     The plating layer  9 B′ is formed on the base layer  7 ′. The plating layer  9 B′ is, for example, a Ni plating layer. 
     The outermost plating layer  9 C′ is formed on the plating layer  9 B′. The outermost plating layer  9 C′ is, for example, a Sn plating layer. 
     In the embodiment, by providing voids KJ′ on the outer side  7   o ′ of the base layer  7 ′, diffusion of hydrogen generated when forming the plating layer  9 B′ on the base layer  7 ′ can be blocked by the voids KJ′. Hydrogen diffuses from the plating layer  9 B′, but is unlikely to pass through the voids KJ′ in the base layer  7 ′, so that hydrogen is unlikely to reach the element body  2 . Thus, it is possible to prevent the hydrogen generated when forming the plating layers  9 B′ on the base layers  7 ′ from diffusing into the element body  2 , to reduce the hydrogen reduction at the dielectric layers  4  between the internal electrode layers  3 A and  3 B, and to minimize deterioration of electrical insulation of the dielectric layers  4 . 
       FIG. 7  is a flowchart showing a method of manufacturing a multilayer ceramic capacitor according to the third embodiment. 
     As shown in Steps S 21  to S 28  of  FIG. 7 , the element body  2  from which the binder has been removed is fabricated in the same manner as in Steps S 1  to S 8  of  FIG. 3 . 
     Next, as shown in Step S 29  of  FIG. 7  (sintering step), each element body  2 , from which the binder has been removed in Step S 28 , is sintered to integrate the internal electrode layers  3 A and  3 B with the dielectric layers  4 . The sintering of the element bodies  2  is conducted in, for example, a sintering furnace in a temperature range from 1000 degrees Celsius to 1350 degrees Celsius for ten minutes to two hours. 
     Next, in Step S 30  of  FIG. 7  (step of applying a paste for the base layers), a conductive paste for the base layers (underlayers)  7 ′ is applied to both side surfaces of each sintered element body  2  and is applied to the remaining four surfaces (upper, lower, front, and rear surfaces) of the element body  2 , which are adjacent to the respective side surfaces. Then, the conductive paste is dried. The conductive paste for the base layers  7 ′ includes a powder or filler of the metal used as the conductive material of the base layers  7 ′. For example, when the metal used as the conductive material of the base layers  7 ′ is Cu, the conductive paste for the base layers includes a powder or filler of Cu. Cu is preferred for the base layers  7 ′ because it provides good electrical conductivity. The conductive paste for the base layers may also include, as the co-material, a ceramic component, which is the main component of the material of the dielectric layers  4 , for example. The conductive paste for the base layers further includes a binder and a solvent. 
     Next, in Step S 31  of  FIG. 7  (step of forming the base layers), the element bodies  2 , on which the conductive paste for the base layers was applied, undergo a sintering process such that the base layers  7 ′ are cured and integrated with the element body  2 . The sintering of the element bodies  2  is conducted in, for example, a sintering furnace at a temperature of 850 degrees Celsius for 15 minutes or more. 
     Then, in Step S 32  of  FIG. 7  (surface oxidation step), each element body  2 , on which the base layers  7 ′ were formed, is heated under a non-oxidizing atmosphere, and then exposed to an oxidizing atmosphere while maintaining the high temperature. Then, each element body  2  is returned to the non-oxidizing atmosphere and cooled. By such treatment, the outer side  7   o ′ of each base layer  7 ′ is rapidly oxidized under the high temperature, and thus metal oxide portions are formed on the outer side  7   o ′ of the base layers  7 ′. The time and temperature for exposing the base layers  7 ′ to the oxidizing atmosphere can be set so that the outer side  7   o ′ of the base layers  7 ′ is non-uniformly oxidized. Accordingly, the process can be stopped before the outer side  7   o ′ of the base layers  7 ′ is oxidized uniformly. 
     For example, in the oxidation process of the outer side  7   o ′ of the base layers  7 ′, each element body  2  is heated to 500 degrees Celsius under an N 2  atmosphere, and then exposed to the atmosphere Earth for two minutes while maintaining this temperature. Then, each element body  2  is returned to the N 2  atmosphere and cooled. 
     Next, in Step S 33  of  FIG. 7  (void forming step), the metal oxide distributed in the outer side  7   o ′ of the base layers  7 ′ is removed by a scheme such as wet etching. In wet etching of the metal oxide, for example, a dilute sulfuric acid solution can be used. Since the metal oxide not only exists on the outer surface of the base layers  7 ′, but also intersect one another in the base layers  7 ′, the voids KJ′ can be formed in the base layer  7 ′ by removing the metal oxide. 
     However, the metal oxide may be partially left as similar to  FIG. 2A . In a case in which the metal oxide portions are disposed inside the voids KJ′ or are in contact with the voids KJ′, the metal oxide portions can capture hydrogen and further reduces diffusion. 
     The size of the voids KJ′ can be from 0.5 micrometers to 6.5 micrometers. The distance in the thickness direction from the outer surface of the base layer  7 ′ to the voids KJ′ can be from 0.1 micrometers to 3.0 micrometers. The percentage of void in the outer side  7   o ′ is greater than that in the inner side  7   i ′ in the base layer  7 ′. The ratio of the length of the voids KJ′ in surface directions to the length of the voids KJ′ in the thickness direction of the base layers  7 ′ can be from one to four. That is to say, the base layers  7 ′ includes more voids KJ′ of which the length in parallel to the outer and inner surfaces of the base layers  7 ′ is greater than the length perpendicular to the outer and inner surfaces of the base layers  7 ′ than voids KJ′ of which the length in in parallel to the outer and inner surfaces of the base layers  7 ′ is less than the length perpendicular to the outer and inner surfaces of the base layers  7 ′. 
     Next, in Step S 34  of  FIG. 7  (plating step), the plating layer  9 B′ and the outermost plating layer  9 C′ are sequentially formed on each base layer  7 ′. The plating layers  9 B′ can be formed by immersing the element body  2 , on which the base layers  7 ′ having the voids KJ′ are formed, in a Ni plating solution in a barrel and by energizing and rotating the barrel. The outermost plating layers  9 C can be formed by immersing the element body  2 , on which the plating layers  9 B′ are formed, in a Sn plating solution in a barrel and by energizing and rotating the barrel. 
     The plating layer  9 B′ is, for example, a Ni plating layer, and the outermost plating layer  9 C′ is, for example, a Sn plating layer. Although some portions of the plating layer  9 B′ may enter into some portions of the voids KJ′, there is no problem in performance of the product. 
     Fourth Embodiment 
       FIG. 8  is a cross-sectional view showing a multilayer ceramic capacitor according to a fourth embodiment of the present invention taken along the longitudinal direction thereof. In  FIG. 8 , a cross sectional region R 4  of an external electrode  6 JA is shown in enlargement. 
     In  FIG. 8 , the multilayer ceramic capacitor  1 C has external electrodes  6 JA and  6 JB instead of the external electrodes  6 A and  6 B of  FIG. 2A . 
     The external electrodes  6 JA and  6 JB are located on opposite sides of the element body  2 , respectively, so that the external electrodes  6 JA and  6 JB are spaced apart (separated) from each other. Each of the external electrodes  6 JA and  6 JB continuously covers the top surface, the side surface, and the bottom surface of the element body  2 . Each of the external electrodes  6 JA and  6 JB may also cover the front surface and the rear surface of the element body  2 . 
     The external electrode  6 JA is connected to the internal electrode layers  3 A, whereas the external electrode  6 JB is connected to the internal electrode layers  3 B. 
     Each of the external electrodes  6 JA and  6 JB has an electrical conductive layer  8 J, an electrical conductive resin layer  9 D, and a plating layer  9 J that includes Ni. The conductive layer  8 J has many voids KJ in such a manner that the outer side MJ 2  farther from the element body  2  includes more voids KJ than the inner side MJ 1  closer to the element body  2  as shown in the cross section of  FIG. 6 . The inner side MJ 1  is adjacent to the boundary between the conductive layer  8 J and the element body  2 , whereas the outer side MJ 2  is adjacent to the boundary between the conductive layer  8 J and the conductive resin layer  9 D. 
     The conductive layer  8 J has a base layer  7 J formed on the element body  2  and an innermost plating layer  9 JA having the outer side MJ 2  in which more voids KJ are disposed. The plating layer  9 J has an intermediate plating layer  9 JB including Ni and an outermost plating layer  9 JC that is solder-wettable. 
     The base layer  7 J and the innermost plating layer  9 JA can be formed in the same manner as the base layer  7  and the innermost plating layer  9 A of  FIG. 2A . However, the base layer  7 J and the base layer  9 JA extend more widely on the top and bottom surfaces and the front and rear surfaces of the element body  2 . 
     In a case in which the base layer  7 J is a sintered layer having Ni as a main component, the edge angle α of the base layer  7 J can be adjusted by adjusting the viscosity of the Ni paste, the ratio of the co-material, and/or the ratio of the additive, and also by adjusting the temperature change during sintering. 
     In a case in which the innermost plating layer  9 JA is an electrolytic plating layer containing Cu, the edge angle β of the innermost plating layer  9 A can be adjusted by adjusting the plating conditions, such as the pH of the plating solution, the temperature of the plating solution, the plating current density, and/or the plating time. 
     The conductive resin layer  9 D is located between the conductive layer  8 J and the plating layer  9 J. The thickness of the conductive resin layer  9 D is preferably from 2 micrometers to 40 micrometers. 
     The main component of the material of the conductive resin layer  9 D is a mixture of a thermosetting resin, for example, an epoxy resin, a phenol resin, a urethane resin, a silicone resin, and a polyimide resin; and a conductive filler made from a metal, for example, copper, tin, nickel, silver, gold, and zinc, or from an alloy containing at least one of the metals. The form of the conductive filler is spherical, flattened or fibrous, but is not particularly limited as long as the form can ensure conductivity. The conductive resin layer  9 D can be formed by applying the conductive resin paste so that the innermost plating layer  9 JA is covered by the dip method or the printing method and thermally curing it. The material of the conductive filler is preferably one containing silver in terms of conductivity. 
     The intermediate plating layer  9 JB is formed on the conductive resin layer  9 D. The outermost plating layer  9 JC is formed on the intermediate plating layer  9 JB. 
     The intermediate plating layer  9 JB and the outermost plating layer  9 JC can be formed in the same manner as the intermediate plating layer  9 B and the outermost plating layer  9 C of  FIG. 2A . For example, the intermediate plating layer  9 JB is a Ni plating layer and the outermost plating layer  9 JC is a Sn plating layer. 
     In the embodiment, by providing voids KJ on the outer side of the innermost plating layer  9 JA, diffusion of hydrogen generated when forming the intermediate plating layer  9 JB on the conductive resin layer  9 D can be blocked by the voids KJ. The outer side of the innermost plating layer  9 JA is the side on which the conductive resin layer  9 D is formed. Hydrogen diffuses from the intermediate plating layer  9 JB, but is unlikely to pass through the voids KJ in the innermost plating layer  9 JA, so that hydrogen is unlikely to reach the element body  2 . Thus, it is possible to prevent the hydrogen generated when forming the intermediate plating layer  9 JB on the conductive resin layer  9 D from diffusing into the element body  2  to reduce the hydrogen reduction at the dielectric layers  4  between the internal electrode layers  3 A and  3 B, and to minimize degradation of electrical insulation of the dielectric layers  4 . The features and effects regarding the voids KJ are the same as those described in conjunction with the first embodiment. 
     In addition, by providing the conductive resin layer  9 D between the conductive layer  8 J and the intermediate plating layer  9 J, stress exerted in the external electrodes  6 JA and  6 JB can be absorbed by the conductive resin layer  9 D. Therefore, when external stress is applied to the external electrodes  6 JA and  6 JB due to deflection or expansion and contraction of the circuit board on which the multilayer ceramic capacitor  1 C is mounted, transmission of the stress to the element body  2  through the external electrodes  6 JA and  6 JB can be minimized, so that cracking of the element body  2  can be minimized. 
     Fifth Embodiment 
       FIG. 9  is a cross-sectional view showing a multilayer ceramic capacitor according to a fifth embodiment of the present invention taken along the longitudinal direction thereof. In  FIG. 9 , a cross sectional region R 5  of an external electrode  6 JA′ is shown in enlargement. 
     In  FIG. 9 , the multilayer ceramic capacitor  1 D has external electrodes  6 JA′ and  6 JB′ instead of the external electrodes  6 A′ and  6 B′ of  FIG. 6 . 
     The external electrodes  6 JA′ and  6 JB′ are located on opposite sides of the element body  2 , respectively, so that the external electrodes  6 JA′ and  6 JB′ are spaced apart (separated) from each other. Each of the external electrodes  6 JA′ and  6 JB′ continuously covers the top surface, the side surface, and the bottom surface of the element body  2 . Each of the external electrodes  6 JA′ and  6 JB′ may also cover the front surface and the rear surface of the element body  2 . 
     The external electrode  6 JA′ is connected to the internal electrode layers  3 A, whereas the external electrode  6 JB′ is connected to the internal electrode layers  3 B. 
     Each of the external electrodes  6 JA′,  6 JB′ has a base layer  7 J′, an electrical conductive resin layer  9 D′, a plating layer  9 JB′ that includes Ni, and an outermost plating layer  9 JC′ that is solder-wettable. The base layer  7 J′ has many voids KJ′ in such a manner that the outer side MJ 2 ′ farther from the element body  2  than the inner side MJ 1 ′ closer to the element body  2  as shown in the cross section of  FIG. 9 . The inner side MJ 1 ′ is adjacent to the boundary between the base layer  7 J′ and the element body  2 , whereas the outer side MJ 2 ′ is adjacent to the boundary between the base layer  7 J′ and the conductive resin layer  9 D′. 
     The base layer  7 ′ is formed on the element body  2 , the conductive resin layer  9 D′ is formed on the base layer  7 ′, and the plating layer  9 JB′ is formed on the conductive resin layer  9 D′. 
     The base layer  7 J′ can be formed in the same manner as the base layer  7 ′ of  FIG. 6 . However, the base layer  7 J′ extends more widely on the top and bottom surfaces and the front and rear surfaces of the element body  2 . It is preferable that the thickness of the base layer  7 J′ be from 2 micrometers to 40 micrometers. 
     In a case in which the base layer  7 J′ is a sintered layer having Cu as the main component, the edge angle γ can be adjusted by adjusting the viscosity of the Cu paste, the ratio of the co-material, and/or the ratio of the additive, and also by adjusting the temperature change during sintering. 
     The conductive resin layer  9 D′ is located between the base layer  7 J′ and the plating layer  9 JB′. The conductive resin layer  9 D′ can be formed in the same manner as the conductive resin layer  9 D of  FIG. 8 . 
     The plating layer  9 JB′ is formed on the conductive resin layer  9 D′. The outermost plating layer  9 JC′ is formed on the plating layer  9 JB′. The plating layer  9 JB′ and the outermost plating layer  9 JC′ can be formed in the same manner as the intermediate plating layer  9 JB and the outermost plating layer  9 JC in  FIG. 8 . For example, the plating layer  9 JB′ is a Ni plating layer and the outermost plating layer  9 JC′ is a Sn plating layer. 
     In the embodiment, by providing voids KJ′ on the outer side of the base layer  7 J′, diffusion of hydrogen generated when forming the plating layer  9 JB′ on the conductive resin layer  9 D′ can be blocked by the voids KJ′. The outer side of the base layer  7 J′ is the side on which the conductive resin layer  9 D′ is formed. Hydrogen diffuses from the plating layer  9 JB′, but is unlikely to pass through the voids KJ′ in the base layer  7 J′, so that hydrogen is unlikely to reach the element body  2 . Thus, it is possible to prevent the hydrogen generated when forming the plating layer  9 JB′ on the conductive resin layer  9 D′ from diffusing into the element body  2  to reduce the hydrogen reduction at the dielectric layers  4  between the internal electrode layers  3 A and  3 B, and to minimize degradation of electrical insulation of the dielectric layers  4 . The features and effects regarding the voids KJ′ are the same as those described in conjunction with the third embodiment. 
     In addition, by providing a conductive resin layer  9 D′ between the base layer  7 J′ and the plating layer  9 JB′, stress exerted in the external electrodes  6 JA′ and  6 JB′ can be absorbed by the conductive resin layer  9 D′. Therefore, when external stress is applied to the external electrodes  6 JA′ and  6 JB′ due to deflection or expansion and contraction of the circuit board on which the multilayer ceramic capacitor  1 D is mounted, transmission of the stress to the element body  2  through the external electrodes  6 JA′ and  6 JB′ can be minimized, so that cracking of the element body  2  can be minimized. 
     Sixth Embodiment 
       FIG. 10  is a perspective view showing a ceramic electronic component according to a sixth embodiment of the present invention. In  FIG. 10 , a chip inductor is taken as an example as a ceramic electronic component. 
     The chip inductor  21  includes an element body  22  and two external electrodes  26 A and  26 B. The element body  22  includes a coil pattern  123  that includes two terminal segments  123 A and  123 B formed at both ends thereof and a magnetic material  124 . The magnetic material  124  is used as a dielectric to insulate the internal electrode layers  123 A and  123 B. The shape of the element body  22  may be a substantially rectangular parallelepiped shape. 
     The external electrodes  26 A and  26 B are located on opposite sides of the element body  22 , respectively, so that the external electrodes  26 A and  26 B are spaced (separated) from each other. Each of the external electrodes  26 A and  26 B continuously extends from the side surface of the element body  22  to the front and rear surfaces and the top and bottom surfaces. 
     The coil pattern  123  is covered with magnetic material  124 . However, the terminal segment  123 A is exposed from the magnetic material  124  on one side of the element body  22  and is connected to the external electrode  26 A, whereas the terminal segment  123 B is exposed from the magnetic material  124  on the other side of the element body  22  and is connected to the external electrode  26 B. 
     The material of the coil pattern  123  and the terminal segments  123 A and  123 B may be, for example, a metal such as Cu, Fe, Zn, Al, Sn, Ni, Ti, Ag, Au, Pt, Pd, Ta, and W, or an alloy containing at least one of these metals. The magnetic material  124  is, for example, a ferrite. 
     Each of the external electrodes  26 A and  26 B can be configured in the same manner as that of the external electrodes  6 A and  6 B in  FIG. 1 . In other words, each of the external electrodes  26 A and  26 B has an electrical conductive layer and a plating layer that includes Ni. The electrical conductive layers of the external electrodes  26 A and  26 B are connected to the terminal segments  123 A and  123 B, respectively. The electrical conductive layer of each of the terminal segments  123 A and  123 B has many voids in such a manner that the outer side farther from the element body  22  includes more voids than the inner side closer to the element body  22 . Consequently, diffusion of hydrogen generated when forming the plating layer on the conductive layer can be blocked by the voids, and it is possible to prevent hydrogen from diffusing into the element body  22 . 
     However, each of the external electrodes  26 A and  26 B may be configured in the same manner as the external electrodes  6 A′ and  6 B′ of  FIG. 6 , the external electrodes  6 JA and  6 JB of  FIG. 8 , or the external electrodes  6 JA′ and  6 JB′ of  FIG. 9 . 
     In the above-described embodiments, the multilayer ceramic capacitors and the chip inductor are taken as examples as electronic components, but the electronic components may include a chip resistor or a sensor chip. In the above-described embodiments, each of the electronic components includes two external electrodes, but the electronic component may include three or more external electrodes. 
     For each embodiment, the size, location, percentage, etc. of the voids can be checked by measuring them of, for example, 20 voids randomly selected from one or more cross-sectional areas of the external electrode, and by averaging the measured values. 
     Experiments 
     The multilayer ceramic capacitors  1 A to  1 D (samples 1 to 4) shown in  FIGS. 2A, 6, 8, and 9  were subjected to a highly accelerated life test (HALT) under a high temperature of 150 degrees Celsius and a high electric field of 40 volts per micrometer, and the Mean Time To Failure (MTTF) was measured for each sample. 
     In the experiments, a Cu base layer, a Ni plating layer and a Sn plating layer were used as the base layer  7 ′, the plating layer  9 B′, and the outermost plating layer  9 C′ in  FIG. 6 , respectively. A comparative sample was prepared in which the Cu base layer was not oxidized, and thus the oxide removal was not conducted. 
     The following results were obtained for the above samples 1 to 4 and the comparative sample. 
     MTTF of sample 1: 450 min 
     MTTF of sample 2: 350 min 
     MTTF of sample 3: 470 min 
     MTTF of sample 4: 390 min 
     MTTF of the comparative sample: 275 min 
     From the above results, it was found that in any of samples 1 to 4, MTTF can be increased by providing voids in the inner layer for the plating layer including Ni, compared with the configuration (comparative sample) in which there are no voids in the inner layer for the plating layer including Ni. 
     It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention cover modifications and variations that come within the scope of the appended claims and their equivalents. In particular, it is explicitly contemplated that any part or whole of any two or more of the embodiments and their modifications described above can be combined and regarded within the scope of the present invention. 
     REFERENCE SYMBOLS 
     
         
           1 A,  1 B,  1 C,  1 D: Multilayer Ceramic Capacitor 
           2 : Element body 
           2 A: Laminate 
           3 A,  3 B: Internal electrode layer 
           4 : Dielectric layer 
           5 A,  5 B: Cover Layer 
           6 A,  6 B,  6 A′,  6 B′,  6 JA,  6 JB,  6 JA′,  6 JB′: External electrode 
           7 ,  7 ′,  7 J,  7 J′: Base layer 
           8 ,  8 Z,  8 J: Electrical conductive layer 
           9 : Plating layer