Patent Publication Number: US-10784886-B1

Title: Segmented digital to analog converter

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application claims the priority under 35 U.S.C. § 119 of China application no. 201910931505.2, filed on 27 Sep. 2019, the contents of which are incorporated by reference herein. 
     BACKGROUND 
     The present disclosure generally relates to digital-to-analog converters (DACs), and, more particularly, to a segmented Resistive DAC (R-DAC). 
     Basically, DACs are required to be both monotonic and accurate. Developments on DACs further require high conversion speeds and low power consumptions.  FIG. 1  is a schematic diagram of a conventional DAC having three sub-DACs.  FIG. 1  is based on FIG. 3 of U.S. Pat. No. 10,110,244, the teachings of which are incorporated herein by reference in its entirety. The DAC  100  of  FIG. 1  includes sub-DACs  18 ,  32 ,  16 , and binary-to-thermometer decoders  12 ,  30 ,  14  that are coupled with the respective sub-DACs. The binary-to-thermometer decoders  12 ,  30 ,  14  receive a portion of a digital input, D, and provide a thermometer vector T to the corresponding sub-DACs  18 ,  32 ,  16 , respectively. Each of the sub-DACs  18 ,  32 , and  16  includes an array of resistors, each having a unit resistance of R. A scaling resistor  29  is coupled between the sub-DACs  18  and  32 . Between the sub-DACs  32  and  16 , another scaling resistor  38  is coupled. Each of the sub-DACs  18 ,  32 ,  16  has a corresponding switch bank  22 ,  34 ,  20  that couples the resistors in the arrays to a high reference voltage V refh  or a low reference voltage V refl . The sub-DAC  18  further includes a termination resistor  24  having the unit resistance of R. 
     The resistors of the DAC of  FIG. 1  have the same resistance that is easy to configure, and avoids mismatching among the sub-DACs. However, the resistors with the same resistance consume a relatively large area. Typically, the DAC implemented on an SoC (system on chip) has a matrix size of around 240,000 μm 2 . 
     It would be advantageous to have a DAC which has an efficient layout area while keeping accurate and monotonic. 
     SUMMARY 
     This summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This summary is not intended to identify key or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter. 
     In one embodiment, the present invention provides a digital to analog converter which receives a binary coded digital input and converts the digital input into an analog signal. The binary coded digital input consists of most significant bits, least significant bits, and remaining bits. The digital to analog converter includes a first, a second, and a third binary-to-thermometer decoders, and a first, a second, and a third sub-DACs. The first binary-to-thermometer decoder receives the least significant bits and decodes the least significant bits into first thermometer code bits. The second binary-to-thermometer decoder receives the most significant bits and decodes the most significant bits into second thermometer code bits. The third binary-to-thermometer decoder receives the remaining bits and decodes the remaining bits into third thermometer code bits. The first sub-DAC includes multiple first resistors and multiple first switches each connected to a respective first resistor. Each of the first resistors has a common first resistance. Each of the first switches receives a respective bit of the first thermometer code bits, and is controlled by the respective bit to connect the respective first resistor to a high reference voltage or a low reference voltage. The second sub-DAC includes multiple second resistors and multiple second switches each connected to a respective second resistor. Each of the second resistors has a common second resistance. Each of the second switches receives a respective bit of the second thermometer code bits, and is controlled by the respective bit to connect the respective second resistor to the high reference voltage or the low reference voltage. The third sub-DAC includes multiple third resistors and multiple third switches each connected to a respective third resistor. Each of the third resistors has a common third resistance. Each of the third switches receives a respective bit of the third thermometer code bits, and is controlled by the respective bit to connect the respective third resistor to the high reference voltage or the low reference voltage. The first and third resistances are lower than the second resistance. 
     In another embodiment, the present invention provides a digital to analog converter which converts a digital input into an analog output. The digital input consists of first least significant bits, second most significant bits, and third middle significant bits. The digital to analog converter includes a first, a second, and at least a third sub-DACs. The first sub-DAC receives the first least significant bits by way of a first binary-to-thermometer decoder, and includes first resistors each contributing a respective voltage, to provide a first output as a response. The second sub-DAC receives the second most significant bits by way of a second binary-to-thermometer decoder, and includes second resistors each contributing a respective voltage, to provide a second output as an output of the digital to analog converter. The third sub-DAC is connected to the first sub-DAC to receive the first output, and receives the third middle significant bits by way of a third binary-to-thermometer decoder, and includes third resistors each contributing a respective voltage, to provide a third output to the second sub-DAC. The first and third resistors each has a physical area less than an area of each second resistor. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       So that the manner in which the above recited features of the present disclosure can be understood in detail, a more detailed description is given below, with reference to embodiments, some of which are illustrated in the appended drawings. The appended drawings illustrate only typical embodiments of the disclosure and should not be interpreted as limiting the scope of the disclosure, as the disclosure may have other embodiments, which may be equally effective. The drawings are for facilitating an understanding of the disclosure and thus are not necessarily drawn to scale. Advantages of the subject matter claimed will become apparent to those skilled in the art upon reading this description in conjunction with the accompanying drawings, in which like reference numerals have been used to designate like elements, and in which: 
         FIG. 1  is a schematic diagram of a conventional DAC having three sub-DACs; 
         FIG. 2  is a schematic diagram of a digital-to-analog converter (DAC) in accordance with an embodiment; and 
         FIG. 3  is a schematic diagram depicting a more general segmented DAC according to an embodiment. 
     
    
    
     DETAILED DESCRIPTION 
       FIG. 2  shows a schematic diagram of a digital-to-analog converter (DAC) in accordance with an embodiment of the present disclosure. The DAC  200  includes a first sub-DAC  210 , a second sub-DAC  220 , and a third sub-DAC  230 , wherein the third sub-DAC  230  is connected between the first sub-DAC  210  and the second sub-DAC  220 . The DAC  200  receives a digital input of binary codes, and converts the digital input into an analog output voltage V out . As depicted in  FIG. 2 , the DAC  200  includes first, second, and third binary-to-thermometer decoders  240 ,  250 , and  260 . Each binary-to-thermometer decoder corresponds to a sub-DAC, the function of which is to control the switches using thermometer bits decoded from the binary bits, so as to couple resistors of the sub-DACs to either a high reference voltage V H  or a low reference voltage V L , in a similar way to that depicted in  FIG. 1 . 
     According to the present embodiment, the first binary-to-thermometer decoder  240  receives first least significant bits (LSBs) of the digital input, and converts these first LSBs into thermometer bits that are further provided to the first sub-DAC  210 . It is understood that, a value of the digital input binary bits received by the binary-to-thermometer decoder corresponds to a quantity of bit “1” in the thermometer codes provided by converting those digital input bits. For example, if the binary value is a 2-bit value, the decoder will convert the 2-bit digital input into a 3-bit thermometer code vector, and if the input binary value is a 3-bit value, the thermometer code vector would be 7 bits. For example, if the binary input is “00”, then the converted thermometer code vector would be “000”. Similarly, a binary input of “01” would provide a thermometer code vector as “100”, a binary input of “10” would provide a thermometer code vector as “110”, and a binary input of “11” would provide a thermometer code vector as “111”. If the binary input is “001”, then the thermometer code vector is “1000000”, and if the binary input is “100”, then the thermometer code vector is “1111000”, and if the binary input is “110”, then the thermometer code vector is “1111110”. That is, the binary-to-thermometer decoder receives a digital input data in binary format and provide vector bits with the number of vector bits set to 1 equal to the digital input data starting at bit 0. 
     In the embodiment, the first LSBs of the digital input received by the first binary-to-thermometer decoder  240  are converted into a thermometer code vector which is then provided to the first sub-DAC  210 . Similarly, the second binary-to-thermometer decoder  250  receives binary coded second most significant bits (MSBs) of the digital input, and the third binary-to-thermometer decoder  260  receives binary coded third middle significant bits (middle-SBs) of the digital input. It is hereby easily understood that, the LSBs, the middle-SBs, and the MSBs of the digital input are different from each other, and collectively consist the digital input. Accordingly, when the LSBs and the MSBs are determined, the middle-SBs are the remaining bits of the digital input that are to be provided to at least one sub-DAC other than the first and second binary-to-thermometer decoders  240  and  250 . Correspondingly, the first sub-DAC  210  includes first switches  211  each receiving a bit of the thermometer code vector provided by the first binary-to-thermometer decoder  240 , the second sub-DAC  220  includes second switches  221  each receiving a bit of the thermometer code vector provided by the second binary-to-thermometer decoder  250 , and the third sub-DAC  230  includes third switches  231  each receiving a bit of the thermometer code vector provided by the third binary-to-thermometer decoder  260 . 
     The first sub-DAC  210  includes first resistors  212  each having a first terminal  213  and a second terminal  214 . The first terminals  213  of the first resistors  212  each connects to a corresponding first switch  211 . The first switches  211  thereby connects the first resistors  212  to the high reference voltage V H  or the low reference voltage V L , according to and under control of the applying bit of the thermometer code vector provided by the first binary-to-thermometer decoder  240 . In this way, the first resistors  212  each contributes a respective voltage to a first output voltage of the first sub-DAC  210 . The first sub-DAC  210  further includes a termination resistor  215  having a first terminal  216  connecting to the second terminals  214  of the first resistors  212 . The other terminal of the termination resistor  215  connects to the low reference voltage V L . The first sub-DAC  210  includes a first scaling resistor  217  having a first terminal  218  connecting to the second terminals  214  of the first resistors  212 , and a second terminal  219  providing the first output voltage of the first sub-DAC  210 . 
     Similarly, the third sub-DAC  230  includes third resistors  232  each having a first terminal  233  and a second terminal  234 . The first terminals  233  of the third resistor  232  each connects to a corresponding third switch  231 . The third switches  231  thereby connects the third resistors  232  to the high reference voltage V H  or the low reference voltage V L , according to and controlled by the applying bit of the thermometer code vector provided by the third binary-to-thermometer decoder  260 . In this way, the third resistors  232  each contributes a respective voltage to a third output voltage of the third sub-DAC  230 . The third sub-DAC  230  further includes a third scaling resistor  235  having a first terminal  236  connecting to the second terminals  234  of the third resistors  232 , and a second terminal  237  providing the third output voltage of the third sub-DAC  230 . 
     Similarly, the second sub-DAC  220  includes second resistors  222  each having a first terminal  223  and a second terminal  224 . The first terminals  223  of the second resistor  222  each connects to a corresponding second switch  221 . The second switches  221  thereby connects the second resistors  222  to the high reference voltage V H  or the low reference voltage V L , according to and under control of the applying bit of the thermometer code vector provided by the second binary-to-thermometer decoder  250 . In this way, the second resistors  222  each contributes a respective voltage to a second output voltage of the second sub-DAC  220 . The second sub-DAC  220  further includes a second scaling resistor  225  having a first terminal  226  connecting to the third sub-DAC  230 , and a second terminal  227  connected to the second terminals  224  of the second resistors  222 , to provide the second output voltage of the second sub-DAC  220 . 
     According to the present embodiment, the termination resistor  215  has a resistance 2R L  equal to the resistance 2R L  of each of the first and third resistors  212  and  232 . If the first binary-to-thermometer decoder  240  receives a 4-bit binary code of the digital input, and the third binary-to-thermometer decoder  260  also receives a 4-bit binary code of the digital input, the first and third scaling resistors  217  and  235  each has a resistance which is 15/16 of the resistance of each of the first and third resistors  212  and  232 , which is 
                   1   ⁢   5       1   ⁢   6       ×   2   ⁢     R   L       ,         
so that an equivalent resistance of the first sub-DAC  210  seen from the third sub-DAC  230  equals to 2R L , and an equivalent resistance of the third sub-DAC  230  seen from the second sub-DAC  220  also equals to 2R L . On the other hand, the second resistors  222  each has a resistance of 2R M  which is proportional to the resistance 2R L  of each of the first and third resistors  212  and  232 , depending upon an equation 2R M =α×2R L , for which α will be described later. The second scaling resistor  225  has a resistance of 2R M -2R M , which is a difference between resistances of the first resistors  212  and the second resistors  222 .
 
     It is mentioned herein that, the DAC  200  readily includes the first sub-DAC  210  to receive the LSBs of the digital input, and the second sub-DAC  220  to receive the MSBs of the digital input. Although it is depicted in  FIG. 2  that the DAC  200  includes the third sub-DAC  230  to receive the middle-SBs of the digital input, in alternative embodiments, the DAC  200  can include more sub-DACs that are similar to the third sub-DAC  230  for which the number of switches and corresponding resistors are configurable to reflect the received bits of the digital input.  FIG. 3  is a schematic diagram depicting part of a more general segmented DAC according to an embodiment of the present invention. The DAC  300  includes a first binary-to-thermometer decoder  310  which receives L-bit first LSBs of a digital input and converts the L-bit first LSBs into a first thermometer code vector T 1  of 2 L −1 bits. Correspondingly, the DAC  300  includes a first sub-DAC  320  connected to the first binary-to-thermometer decoder  310  to receive the bits of the first thermometer code vector T 1 , namely b 1   T     1    to b 2     L     −1   T     1   . Besides, the DAC  300  includes a second binary-to-thermometer decoder  330  which receives M-bit second MSBs of the digital input and converts the M-bit second MSBs into a second thermometer code vector T i+2  of 2 M −1 bits. Correspondingly, the DAC  300  includes a second sub-DAC  340  connected to the second binary-to thermometer decoder  330  to receive the bits of the second thermometer code vector T i+2 , namely b 1   T     i+2    to b 2     M     −1   T     i+2   . Similar to the first sub-DAC  210  of  FIG. 2 , first resistors  322  of the first sub-DAC  320  have resistances of 2R L , and the termination resistor  324  of the first sub-DAC  320  also has a resistance of 2R L . A first scaling resistor  326  of the first sub-DAC  320  has a resistance of 
                   2   L     -   1       2   L       ×   2   ⁢       R   L     .           
similar to the second sub-DAC  220  of  FIG. 2 , second resistors  342  of the second sub-DAC  340  have resistances of 2R M , where an equation 2R M =α×2R L  applies, and for which α will be described later. A second scaling resistor  344  of the second sub-DAC  340  also has a resistance of 2R M -2R L , which is similar to the second scaling resistor  225  of the second sub-DAC  220  of  FIG. 2 .
 
     As depicted in  FIG. 3 , the DAC  300  includes a third binary-to-thermometer decoders  350  and a fourth binary-to-thermometer decoder  370  that collectively receive third middle-SBs that are the remaining bits other than the first LSBs and the second MSBs of the digital input. The third and fourth sub-DACs  360  and  380  respectively connect to the third and fourth binary-to-thermometer decoders  350  and  370 . The third binary-to-thermometer decoder  350  is configured to receive S 1  bits of the third middle significant bits of the digital input, and to decode the received S 1 -bit binary code into a third thermometer code vector T 2  of 2 S     1   −1 bits, namely b 1   T     2    to b 2     S       1     −1   T     2   , each being provided to a corresponding third switch of the third sub-DAC  360 . Similar to the third sub-DAC  230  of  FIG. 2 , third resistors  362  of the third sub-DAC  360  have resistances of 2R L , and third scaling resistor  364  of the third sub-DAC  360  has a resistance of 
                   2     S   1       -   1       2     S   1         ×   2   ⁢       R   L     .           
The fourth binary-to-thermometer decoder  370  is configured to receive S i  middle significant bits of the digital input, and to decode the received S i  binary coded bits into 2 S     i   −1 bits of thermometer code vector T i+1 , namely b 1   T     i+1    to b 2     S       1     −1   T     2   , each being provided to a corresponding switch of the fourth sub-DAC  380 . Similar to the third sub-DAC  230  of  FIG. 2  and the third sub-DAC  360 , fourth resistors  382  of the fourth sub-DAC  380  have resistances of 2R L , and fourth scaling resistor  384  of the fourth sub-DAC  380  has a resistance of
 
     
       
         
           
             
               
                 
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     To keep the DAC monotonic, resistances of the resistors should be kept stable, to enable a one-bit change in the digital input to be correctly transferred into the output voltage. Resistor mismatch reflects the resistance stability of the resistor, and the deviation of the resistance from the designed resistance. For example, the resistors of a DAC receiving 4 bits of binary code input should have the mismatches less than 1/2 4  so that a one-bit change in the input can be correctly transferred into the output voltage. Each additional bit of accuracy requirement translates into a mismatch requirement which is narrowed by half, which means that the resistor mismatch should be lowered by half. 
     In fabricating the DAC, the resistors are fabricated integrally with the others of the device, that is to say they are “on chip” rather than discrete components, and occupy space on the integrated circuit (IC) chip. The physical area that a resistor occupies has an inverse relationship to the mismatch of the resistor. Specifically, the mismatch is inversely proportional to the square root of the area: 
                 δ   ⁢           ⁢   R     =       1     Area_R       ×   k       ,         
wherein Area_R is the physical area that the resistor consumes, k is a sloping factor, and δR is the mismatch of the resistor. A higher resistor mismatch allows the resistor area to be saved. According to what is described above, lowering the monotonic requirement by one bit can reduce the resistor area requirement by a factor of 4, to as little as ¼ the original area. Referring back to the embodiment of  FIG. 2 , in the case that the first sub-DAC  210  and the third sub-DAC  230  respectively each receive 4 bits of the digital input, the second sub-DAC  220  is required to have an accuracy which is at least 4-bit+4-bit, that is to say an accuracy of at least 8-bits, to ensure that the second sub-DAC  220  is correctly operated with a one-bit turn-over of the 8 bits input into the first sub-DAC  210  and the third sub-DAC  230 . Preferably, in some embodiments, the second sub-DAC  220  has an accuracy of 9-bit, that is to say it includes one more bit as a design margin. However, for the third sub-DAC  230 , an accuracy of—at most—only 5 bits is required. The area of the third resistors  232  is configured as
 
                 Area_   ⁢   2   ⁢     R   L       =         Area_   ⁢   2   ⁢     R   M         4     9   -   5         =       Area_   ⁢   2   ⁢     R   M         2   ⁢   5   ⁢   6           ,         
wherein Area_2R M  is the area of the second resistors  222  of the second sub-DAC  220 . The first resistors  212  and the termination resistor  215  of the first sub-DAC  210  can have the same configuration as the third resistors  232  of the third sub-DAC  230 , which saves the areas of the resistors in the first and third sub-DACs  210  and  230  to be only 1/256 of the areas of the second resistors  222  in the second sub-DAC  220 .
 
     To be more general, referring to  FIG. 3 , the area of each of the first resistors  322 , the third resistors  362 , and the fourth resistors  382  is 
             1     4       S   1     +     S   i               
of the area of each second resistors  342 , wherein S 1  is at least 1. Accordingly, the resistance of each of the first resistors  322 , the third resistors  362 , and the fourth resistors  382  is less than that of the resistance of each second resistors  342 . In the embodiment where the resistance of resistors is dominantly determined by the area the resistors occupy, the factor α in the above equation 2R M =α×2R L  is at least 4. However, other fraction ratios are applicable, such as a is preferably between 2 and 8, which can both save the resistor area in the sub-DACs receiving the LSB and middle-SB and ensure the accuracy.
 
     Referring back to  FIG. 2 , the DAC  200  may further include an operational amplifier (op-amp)  270  having a non-inverting input terminal  272  connected to the output of the second sub-DAC  220  and an inverting input terminal  274  connected to an output terminal  276  of the operational amplifier  270 . The DAC  200  includes the op-amp  270  to operate as an unbuffered voltage mode DAC. In other embodiments, the DAC  200  includes an alternative operational amplifier  280  instead of the op-amp  270 . The op-amp  280  has a non-inverting input terminal  282  connected to a reference voltage which is an average of the high reference voltage V H  and the low reference voltage V L , an inverting input terminal  284  which is connected to the output of the second sub-DAC  220 , and an output terminal  286  connected to the inverting input terminal  284  by way of a feedback resistor  288 . The feedback resistor  288  has, in this case, a resistance of 
                 1     6   ⁢   4       ×   2   ⁢     R   M       ,         
wherein 64 is 2 6 , 6 being the number of bits of the MSBs provided to the second sub-DAC  220 , and 2R M  is the resistance of the second resistors  222  of the second sub-DAC  220 . The DAC  200  includes the alternative op-amp  280  to operate as a buffered voltage mode DAC. In  FIG. 2 , dashed lines between third sub-DAC  230  and the op-amps  270  and  280  show possible connections.
 
     The DAC as described in the embodiments includes a first sub-DAC to receive a thermometer code vector converted from the LSBs of the digital input, and a second sub-DAC to receive a thermometer code vector converted from the MSBs of the digital input. Further, the DAC includes at least a third sub-DAC connecting between the first and second sub-DACs to receive a thermometer code vector converted from the middle-SBs of the digital input. Each of the first to third sub-DACs includes multiple switches receiving corresponding bits of the respectively received thermometer code vector. Each of the first to third sub-DACs further includes multiple resistors each connected to a corresponding switch. The switches are controlled by the bits of the thermometer code vectors to connect the corresponding resistors to a high reference voltage or a low reference voltage. Each resistor in the first sub-DAC and the third sub-DAC has a resistance which is less than that of the resistor in the second sub-DAC. Accordingly, the resistors in the first sub-DAC and third sub-DAC consume reduced area, while keep the DAC monotonic and accurate. 
     The use of the terms “a” and “an” and “the” and similar referents in the context of describing the subject matter (particularly in the context of the following claims) are to be construed to cover both the singular and the plural, unless otherwise indicated herein or clearly contradicted by context. The terms “coupled” and “connected” both mean that there is an electrical connection between the elements being coupled or connected, and neither implies that there are no intervening elements. In describing transistors and connections thereto, the terms gate, drain and source are used interchangeably with the terms “gate terminal”, “drain terminal” and “source terminal”. Recitation of ranges of values herein are intended merely to serve as a shorthand method of referring individually to each separate value falling within the range, unless otherwise indicated herein, and each separate value is incorporated into the specification as if it were individually recited herein. Furthermore, the foregoing description is for the purpose of illustration only, and not for the purpose of limitation, as the scope of protection sought is defined by the claims set forth hereinafter together with any equivalents thereof entitled to. The use of any and all examples, or exemplary language (e.g., “such as”) provided herein, is intended merely to better illustrate the subject matter and does not pose a limitation on the scope of the subject matter unless otherwise claimed. The use of the term “based on” and other like phrases indicating a condition for bringing about a result, both in the claims and in the written description, is not intended to foreclose any other conditions that bring about that result. No language in the specification should be construed as indicating any non-claimed element as essential to the practice of the invention as claimed. 
     Preferred embodiments are described herein, including the best mode known to the inventor for carrying out the claimed subject matter. Of course, variations of those preferred embodiments will become apparent to those of ordinary skill in the art upon reading the foregoing description. The inventor expects skilled artisans to employ such variations as appropriate, and the inventor intends for the claimed subject matter to be practiced otherwise than as specifically described herein. Accordingly, this claimed subject matter includes all modifications and equivalents of the subject matter recited in the claims appended hereto as permitted by applicable law. Moreover, any combination of the above-described elements in all possible variations thereof is encompassed unless otherwise indicated herein or otherwise clearly contradicted by context.