Patent Publication Number: US-2009236688-A1

Title: Semiconductor device having fuse pattern and methods of fabricating the same

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     The above-referenced application is a Divisional of U.S. Ser. No. 11/387,158, filed on Mar. 22, 2006, now pending, which claims priority under 35 U.S.C. § 119 from Korean Patent Application Nos. 10-2005-0023828, filed Mar. 22, 2005 and 10-2005-118854, filed on Dec. 7, 2005, the disclosure of which are hereby incorporated by reference in its entirety. 
    
    
     BACKGROUND OF INVENTION 
     1. Technical Field 
     This disclosure relates to a semiconductor device and a method of fabricating the same, and more particularly, to a semiconductor device having a fuse pattern and methods of fabricating the same. 
     2. Discussion of the Related Art 
     Semiconductor memory devices formed on a semiconductor substrate are electrically tested prior to an assembly process. As a result, semiconductor memory devices are classified as bad chips or good chips. When a chip includes at least one bad cell, the bad cell may be replaced with a redundant cell though a repair process. The repair process includes a laser beam irradiation operation blowing predetermined fuses such that the redundant cell has an address of the bad cell in a write mode and a read mode. The fuses are generally formed, concurrently with a bit line or an interconnection pattern within a semiconductor memory device. 
     Because of the current high-density integration and multi-layer structure of a semiconductor device, the thickness of an oxide layer to be etched to form a fuse window is larger than in the past. Thus, it is difficult to form a fuse and a bit line concurrently. Research has been conducted for a metal fuse to be formed at the same time of forming the interconnection pattern. To lower the resistance, the interconnection pattern is formed to be greater in thickness than the bit line. Thus, since the metal fuse patterned and formed with the interconnection pattern concurrently is also formed with a thickness greater than that of the bit line fuse, a high energy is required for blowing the metal fuse. After blowing the metal fuse, the residual matter of the metal fuse may cause a bridge with an adjacent metal fuse due to the thick thickness of the metal fuse. As a result, there remains a need for a thinner metal fuse to reduce the chance of a bridge forming with adjacent metal fuses and to reduce the energy required for blowing the fuse. 
       FIGS. 1A through 1D  are cross-sectional views for explaining a method of fabricating a conventional semiconductor device. In  FIGS. 1A through 1D , the portions indicated by reference numbers “I 0 ”, “F 0 ” and “P 0 ” represent an interconnection region, a fuse region and a pad region, respectively. 
     Referring to  FIG. 1A , a first interlayer insulating layer  115  is formed on a semiconductor substrate  110 . A barrier layer  120 , a conductive layer  123  and a capping layer  125  are sequentially formed on the first interlayer insulating layer  115 . The barrier layer  120  can be formed of a titanium nitride layer, or a titanium layer and a titanium nitride layer, which are sequentially stacked. The conductive layer  123  is formed of an aluminum layer. The capping layer  125  can be formed of a titanium layer, or a titanium layer and a titanium nitride layer, which are sequentially stacked. 
     Referring to  FIG. 1B , preliminary fuse patterns  127   a  are formed of a barrier pattern  120   a , a conductive pattern  123   a,  and a capping pattern  125   a,  which are sequentially stacked within the fuse region F 0  by patterning the capping layer  125 , the conductive layer  123  and the barrier layer  120  sequentially. Similarly, first interconnection patterns  127   b  include a barrier pattern  120   b,  a conductive pattern  123   b,  and a capping pattern  125   b,  which are sequentially stacked within the interconnection region I 0 . 
     A second interlayer insulating layer  133  is formed on the semiconductor substrate  110  having the preliminary fuse patterns  127   a  and the first interconnection patterns  127   b.  Via contact plugs  134  may be formed to penetrate the second interlayer insulating layer  133 , and to be electrically connected with the first interconnection patterns  127   b.  An upper barrier layer, an upper conductive layer and an upper capping layer are sequentially formed on the substrate having the via contact plugs  134 . Second interconnection patterns  140  are formed on the second interlayer insulating layer  133  within the interconnection region I 0 , by patterning the upper capping layer, the upper conductive layer and the upper barrier layer in turn, and concurrently, a pad  140   p  is formed on the second interlayer insulating layer  133  within the pad region P 0 . 
     Each of the second interconnection patterns  140  may be formed of an upper barrier pattern  135 , an upper conductive pattern  137 , and an upper capping pattern  139 , which are sequentially stacked. The second interconnection patterns  140  are electrically connected with the first interconnection patterns  127   b  respectively, through the via contact plugs  134 . The pad  140   p  includes a pad conductive pattern  138   p  and a pad capping pattern  139   p,  which are sequentially stacked, and the pad conductive pattern  138   p  is formed of a pad barrier pattern  135   p  and a pad conductive pattern  137   p,  which are sequentially stacked. 
     A passivation layer  143  is formed on the substrate having the second interconnection patterns  140  and the pad  140   p.  The passivation layer  143  may include a plasma oxide layer  141  and a plasma nitride layer  142 , which are sequentially stacked. 
     Referring to  FIG. 1C , a fuse window  145   f  exposing the capping patterns  125   a  is formed by etching the passivation layer  143  within the fuse region FO and partially etching the second interlayer insulating layer  133  positioned below the passivation layer  143 , by using a photolithograph process and an etch process. Then, fuse patterns  127   a ′ which are thinner in thickness than the preliminary fuse patterns  127   a  are formed by etching and removing the exposed capping patterns  125   a  and partially etching the conductive patterns  123   a  positioned below the capping patterns  125   a.  Each of the fuse patterns  127   a ′ is formed of the barrier pattern  120   a  and the partially etched conductive pattern  123   a ′, which are sequentially stacked. Concurrently, a pad window  145   p  exposing the pad conductive pattern  138   p  is formed by sequentially etching predetermined portions of the passivation layer  143  and the pad capping pattern  139   p  within the pad region P 0 . At this time, the pad conductive pattern  137   p  may be partially etched. 
     A conformal fuse protecting layer  147  is formed on the substrate having the fuse patterns  127   a ′. As a result, the fuse protecting layer  147  is formed to cover the whole surfaces of the upper surface of the passivation layer  143 , the inside of the fuse window  145   f  and the inside of the pad window  145   p.  The fuse protecting layer  147  may include a silicon nitride layer. The fuse protecting layer  147  is formed to protect the exposed fuse patterns  127   ′.    
     Referring to  FIG. 1D , the pad conductive pad  138   p  positioned below the pad window  145   p  is exposed by selectively patterning the fuse protecting layer  147 . Then, a polyimide layer is formed on the substrate where the pad conductive pattern  138   p  is exposed, and a polyimide pattern  150  having a fuse window opening  150   f  and a pad window opening  150   p  to expose the fuse window  145   f  and the pad window  145   p,  respectively, is formed by an exposure process and a developing process. The semiconductor device is electrically tested prior to the assembly process, and as a result, with respect to bad cells, a laser beam is irradiated through the fuse window opening  150   f  and the fuse window  145   f  for the repair process. Then, in the assembly process, a pad bonding work is performed through the pad window opening  150   p  and the pad window  145   p.    
     According to the above-described related art, the preliminary fuse patterns  127   a  may be unevenly etched while the second interlayer insulating layer  133  is etched. As a result, as shown in  FIG. 1C , the upper surface of the fuse patterns  127   a ′ may not be even by the non-uniform etching and may be uneven in thickness. Furthermore, the thickness of the fuse patterns  127   a ′ may be different from each other in a wafer, because of the non-uniform etching of the preliminary fuse patterns  127   a.  For example, a fuse pattern A 0  may be greater in thickness that a fuse pattern B 0 . As a result, when the same energy is used for blowing the fuse patterns, the fuse pattern B 0  is blown. However, a residual pattern may exist with respect to the fuse pattern A 0  because the fuse pattern A 0  is greater in thickness than the fuse pattern B 0 . 
     Furthermore, as the fuse protecting layer  147  is formed after the fuse patterns  127   a ′ are formed, a photoresist process is added to expose the pad conductive pattern  138   p.  The process of forming the polyimide pattern  150  is also separately performed. Consequently, since the processes with respect to the fuse window, the pad window and the polyimide pattern are separately performed, the photolithography process is performed three times, thereby increasing production costs. 
     Thus, there remains a need for a method of fabricating a semiconductor device having a fuse pattern, each pattern having a flat upper surface and improving a thickness uniformity of the fuse patterns in a wafer and simplifying the photolithography process. 
     SUMMARY 
     An embodiment includes a semiconductor device including a semiconductor substrate having a fuse region and an interconnection region, a first insulating layer formed in the fuse region and the interconnection region, a fuse pattern formed on the first insulating layer in the fuse region, the fuse pattern including a first conductive pattern and a first capping pattern, an interconnection pattern formed on the first insulating layer in the interconnection region, including a second conductive pattern and a second capping pattern, and having a thickness greater than the thickness of the fuse pattern, and a second insulating layer formed on the first insulating layer and covering the fuse pattern. 
     A further embodiment includes a semiconductor device including a semiconductor substrate having a fuse region and an interconnection region, a first insulating layer formed in the fuse region and the interconnection region, fuse patterns formed on the first insulating layer in the fuse region, each fuse pattern including a first conductive pattern and a first capping pattern, and the fuse patterns having substantially uniform thicknesses, an interconnection pattern formed on the first insulating layer in the interconnection region, including a second conductive pattern and a second capping pattern, and having a thickness greater than the thickness of the fuse patterns, and a second insulating layer formed on the first insulating layer and covering the fuse patterns. 
     A further embodiment includes a method of fabricating a semiconductor device including providing a semiconductor substrate having a fuse region and an interconnection region, forming a conductive layer on the semiconductor substrate, partially etching the conductive layer inside the fuse region to form a fuse conductive layer having a thickness thinner than a thickness of the conductive layer outside of the fuse region, and patterning the conductive layer and the fuse conductive layer to form a first conductive pattern inside the fuse region and a second conductive pattern inside the interconnection region. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS  
       The above and other features and advantages will become more apparent to those of ordinary skill in the art by describing in detail preferred embodiments thereof with reference to the attached drawings in which: 
         FIGS. 1A through 1D  are cross-sectional views illustrating a conventional method of fabricating a semiconductor device; 
         FIG. 2  is a plan view illustrating a semiconductor device according to an embodiment; 
         FIGS. 3A through 3F  are cross-sectional views taken along a line I-I′ of  FIG. 2  illustrating a method of fabricating a semiconductor device according to an embodiment; and 
         FIGS. 4A through 4C  are cross-sectional views illustrating a method of fabricating a semiconductor device according to another embodiment. 
     
    
    
     DETAILED DESCRIPTION  
     Embodiments will now be described more fully hereinafter with reference to the accompanying drawings. Embodiments may take many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the following claims to those skilled in the art. In the drawings, the thicknesses of layers and regions may be exaggerated for clarity. Like numbers refer to like elements throughout the specification. 
       FIG. 2  is a plan view illustrating a semiconductor device according to an embodiment, and  FIGS. 3A through 3F  are cross-sectional views taken along line I-I′ of  FIG. 2  illustrating a method of fabricating a semiconductor device according to an embodiment. In  FIGS. 2 , and  3 A through  3 F, regions indicated by reference numbers “I 1 ”, “F 1 ” and “P 1 ” represent an interconnection region, a fuse region, and a pad region respectively. 
     Referring to  FIGS. 2 and 3A , a first interlayer insulating layer  15  is formed on a semiconductor substrate  10 . Before the first interlayer insulating layer  15  is formed, various discrete elements, for example, transistors and resistors may be formed on the semiconductor substrate  10 . A conductive layer  24  is formed on the first interlayer insulating layer  15 . The conductive layer  24  may include a barrier layer  20  and a conductive layer  23 , which are sequentially stacked. The barrier layer  20  may be omitted. The barrier layer  20  may include a titanium nitride layer, or may include a titanium layer and a titanium nitride layer, which are sequentially stacked. The conductive layer  23  may include one material layer selected from the group consisting of an aluminum layer, a tungsten layer, a copper layer, and combinations thereof. 
     A lower interface layer  25  and a lower capping layer  26  may be sequentially formed on the conductive layer  24 . The lower interface layer  25  may include a titanium layer, and the lower capping layer  26  may include a titanium nitride layer. The lower capping layer  26  may be an anti-reflective layer. 
     Referring to  FIGS. 2 and 3B , a photoresist pattern (not shown) exposing the fuse region F 1  is formed on the substrate  10  having the lower capping layer  26 . The lower capping layer  26  and the lower interface layer  25  inside the fuse region F 1  are sequentially etched and removed, using the photoresist pattern as an etch mask. Further, the conductive layer  24  is partially etched to form a fuse conductive layer  24   a  having a thickness thinner than that of the conductive layer  24 . The fuse conductive layer  24   a  may include the barrier layer  20  and a partially-etched conductive layer  23   a,  which are sequentially stacked. When the fuse conductive layer  24   a  is partially etched using the photoresist pattern as an etch mask, it may have a substantially uniform thickness. 
     Then, the photoresist pattern is removed. An upper capping layer  27  may be formed on the substrate  10  having the fuse conductive layer  24   a.  The upper capping layer  27  may include the same material layer as that of the lower capping layer  26 . The upper capping layer  27  may be used as an anti-reflective layer during a subsequent patterning process. A process of forming the upper capping layer  27  may be omitted. 
     Referring to  FIGS. 2 and 3C , the upper capping layer  27  and the fuse conductive layer  24   a  inside the fuse region F 1  are sequentially patterned, using a photolithography process and an etch process, thereby forming fuse patterns  31   a.  Each of the fuse patterns  31   a  may include a first conductive pattern  24   a ′ and a first upper capping pattern  27   a,  which are sequentially stacked. The first conductive pattern  24   a ′ may include a first barrier pattern  20   a  and a first conductive pattern  23   a ′, which are sequentially stacked. The fuse pattern  31   a  may be formed with a thickness of about 3000 Å or less. 
     Concurrently, the upper capping layer  27 , the lower capping layer  26 , the interface layer  25 , and the conductive layer  24  inside the interconnection region I 1  are sequentially patterned, thereby forming first interconnection patterns  31   b.  Each of the first interconnection patterns  31   b  may include a second conductive pattern  24   b,  a lower interface pattern  25   b,  and a capping pattern  30   b,  which are sequentially stacked. The second conductive pattern  24   b  may include a second barrier pattern  20   b  and a second conductive pattern  23   b,  which are sequentially stacked. The capping pattern  30   b  may include a lower capping pattern  26   b  and a second upper capping pattern  27   b,  which are sequentially stacked. The thickness of the fuse pattern  31   a  is thinner than that of the first interconnection pattern  31   b.  Since the fuse patterns  31   a  are patterned using a photolithography process and an etch process, they can have flat upper surfaces. 
     Referring to  FIGS. 2 and 3D , a second interlayer insulating layer  33  is formed on the substrate  10  having the fuse patterns  31   a  and the first interconnection patterns  31   b . The second interlayer insulating layer  33  may include a material layer selected from the group consisting of a tetra ethyl ortho silicate (TEOS) layer, a flowable oxide (FOX) layer, a plasma enhanced-TEOS (PE-TEOS) layer, a boron phosphorous silicate glass (BPSG) layer and combinations thereof. For example, the second interlayer insulating layer  33  may include a TEOS layer, a FOX layer, and a TEOS layer, which are sequentially stacked. Since a portion between the patterns  31   a  and  31   b  is filled with the FOX layer, the upper surface of the second interlayer insulating layer  33  may be planarized. 
     Via holes  34   h  may be formed to penetrate the second interlayer insulating layer  33  inside the interconnection region I 1  and expose predetermined portions of the first interconnection patterns  31   b . Then, via contact plugs  34  may be formed to fill the via holes  34   h  and be electrically connected to the first interconnection patterns  31   b . Then, an upper barrier layer, an upper conductive layer, and an upper capping layer are sequentially formed on the substrate having the via contact plugs  34 . The upper capping layer, the upper conductive layer, and the upper barrier layer are sequentially patterned, thereby forming second interconnection patterns  40  on the second interlayer insulating layer  33  inside the interconnection region I 1 , and concurrently, forming a pad  40   p  on the second interlayer insulating layer  33  inside the pad region P 1 . 
     Each of the second interconnection patterns  40  may include an upper barrier pattern  35 , an upper conductive pattern  37 , and an upper capping pattern  39 , which are sequentially stacked. The second interconnection patterns  40  may be electrically connected to the first interconnection patterns  31   b  through the via contact plugs  34 . The pad  40   p  may include a pad conductive pattern  38   p  and a pad capping pattern  39   p,  which are sequentially stacked, and the pad conductive pattern  38   p  may include a pad barrier pattern  35   p  and a pad conductive pattern  37   p,  which are sequentially stacked. 
     Referring to  FIGS. 2 and 3E , a passivation layer  43  is formed on the substrate having the second interconnection patterns  40  and the pad  40   p.  The passivation layer  43  may include a plasma oxide layer  41  and a plasma nitride layer  42 , which are sequentially stacked. Then, after a polyimide layer is formed on the substrate having the passivation layer  43 , an exposure process and a developing process are performed, thereby forming a polyimide pattern  50  having a fuse window opening  50   f  and a pad window opening  50   p  exposing a predetermined portion of the fuse region F 1  and a predetermined portion of the pad region P 1 , respectively. 
     Referring to  FIGS. 2 and 3F , the passivation layer  43  inside the fuse region F 1  is etched through the fuse window opening  50   f,  using the polyimide pattern  50  as an etch mask, and the second interlayer insulating layer  33  below the passivation layer  43  is partially etched with a predetermined thickness remaining on the fuse patterns  31   a , thereby forming a fuse window  53   f . As a result, a second interlayer insulating layer  33   a  inside the fuse region F 1  is formed with a thin thickness. Since the thin second interlayer insulating layer  33   a  covering the fuse patterns  31   a  includes an oxide layer such as a TEOS layer, a FOX layer, or a BPSG layer, a lower energy is required to blow the fuse patterns  31   a  as compared to the energy required in the conventional case of a silicon nitride layer used as a fuse protecting layer. Concurrently, a predetermined portion of the passivation layer  43  and a predetermined portion of the pad capping pattern  39   p  inside the pad region P 1  are etched through the pad window opening  50   p,  thereby forming a pad window  53   p  exposing the pad conductive pattern  38   p.    
     In some embodiments, the passivation layer  43  is selectively etched through the fuse window opening  50   f  and the pad window opening  50   p  during the formation of the fuse window  53   f  and the pad window  53   p,  so as to expose the second interlayer insulating layer  33  of the fuse region F 1  and the pad capping pattern  39   p  of the pad region P 1 . Then, the exposed pad capping pattern  39   p  is etched so as to expose a pad conductive pattern  38   p  of the pad region I 1 , and then, the exposed second interlayer insulating layer  33  of the fuse region F 1  may be partially etched. 
     The semiconductor device is electrically tested before an assembly process, and a repair process is performed by irradiating a laser beam through the fuse window opening  50   f  and the fuse window  53   f.  Then, a pad bonding operation is performed through the pad window opening  50   p  and the pad window  53   pp  in the assembly process. 
     As described above, each of the fuse patterns  31   a  has a thickness thinner than that of the first interconnection pattern  31   b . Since the fuse patterns  31   a  are formed by patterning during the photolithography process and the etch process, each of the fuse patterns  31   a  can have a flat upper surface. Furthermore, as explained in reference to  FIG. 3B , since the fuse conductive layer  24   a  is formed with a thin thickness by a partial etching in advance using the photoresist pattern as an etch mask, the uniformity of thickness of the fuse patterns  31   a  within a single wafer can be improved. Therefore, an error rate in a fuse blowing operation can be reduced. 
     Furthermore, since the fuse window  53   f  and the pad window  53   p  are formed using the polyimide pattern  50  as a mask, the number of the photolithography processes, which is three in the related art, can be reduced to one according to an embodiment. Therefore, when considering the photolithography process added in the operation of partially etching the conductive layer  24  in  FIG. 3B , the number of the photolithography processes can be shortened to one as compared to the conventional method. 
       FIGS. 4A through 4C  are cross-sectional views illustrating a method of fabricating a semiconductor device according to another embodiment. In  FIGS. 4A through 4C , regions indicated by reference numbers “I 1 ”, “F 1 ” and “P 1 ” represent an interconnection region, a fuse region, and a pad region, respectively. 
     Referring to  FIG. 4A , a first interlayer insulating layer  15  is formed on the semiconductor substrate  10 . Before the first interlayer insulating layer  15  is formed, various discrete elements, for example, transistors and resistors may be formed on the semiconductor substrate  10 . A conductive layer  24  is formed on the first interlayer insulating layer  15 . The conductive layer  24  may include a barrier layer  20  and a conductive layer  23 , which are sequentially stacked. The barrier layer  20  may be omitted. The barrier layer  20  may include a titanium nitride layer, or may include a titanium layer and a titanium nitride layer, which are sequentially stacked. The conductive layer  23  may include a material layer selected from the group consisting of an aluminum layer, a tungsten layer, and a copper layer and combinations of thereof. 
     Referring to  FIG. 4B , a photoresist pattern exposing the fuse region F 1  is formed on the substrate having the conductive layer  24 . The conductive layer  24  is partially etched, using the photoresist pattern as an etch mask, thereby forming a fuse conductive layer  24   a  having a thickness thinner than that of the conductive layer  24 . The fuse conductive layer  24   a  may include the barrier layer  20  and a partially-etched conductive layer  23   a,  which are sequentially stacked. When the fuse conductive layer  24   a  is partially etched, using the photoresist pattern as an etch mask, it may have a uniform thickness. 
     Then, the photoresist pattern is removed. An upper interface layer  28  and an upper capping layer  29  may be sequentially formed on the substrate having the fuse conductive layer  24   a.  The upper interface layer  28  may include a titanium layer, and the upper capping layer  29  may include a titanium nitride layer. The upper capping layer  29  may be used as an anti-reflective layer during a subsequent patterning process. 
     Referring to  FIG. 4C , the upper capping layer  29 , the upper interface layer  28 , and the fuse conductive layer  24   a  inside the fuse region F 1  are sequentially patterned using a photolithography process and an etch process, thereby forming fuse patterns  31   a ′. Each of the fuse patterns  31   a ′ may include a first conductive pattern  24   a ′, a first upper interface pattern  28   a , and a first upper capping pattern  29   a,  which are sequentially stacked. The first conductive pattern  24   a ′ may include a first barrier pattern  20   a  and a first conductive pattern  23   a ′, which are sequentially stacked. The fuse pattern  31   a ′ may be formed with a thickness of about 3000 Å or less. 
     Concurrently, the upper capping layer  29 , the upper interface layer  28 , and the conductive layer  24  inside the interconnection region I 1  are sequentially patterned, thereby forming first interconnection patterns  31   b ′. Each of the first interconnection patterns  31   b ′ may include a second conductive pattern  24   b,  a second upper interface pattern  28   b,  and a second upper capping pattern  29   b,  which are sequentially stacked. The second conductive pattern  24   b  may include a second barrier pattern  20   b  and a second conductive pattern  23   b,  which are sequentially stacked. 
     The thickness of the fuse pattern  31   a ′ is thinner than that of the first interconnection pattern  31   b ′. Since the fuse patterns  31   a ′ are patterned using a photolithography process and an etch process, they can have flat upper surfaces. Furthermore, as explained in reference to  FIG. 4B , since the fuse conductive layer  24   a  is formed with a thin thickness by a partial etching in advance, using the photoresist pattern as an etch mask, a thickness uniformity of the fuse patterns  31   a ′ within a single wafer can be improved. Therefore, an error rate in a fuse blowing operation can be reduced. 
     Then, the same processes as those as explained in reference to  FIGS. 3D through 3F  are performed, thereby forming a fuse window and a pad window. 
     A semiconductor device according to an embodiment will be explained referring to  FIGS. 2 and 3F  again. In  FIGS. 2 and 3F , regions indicated by reference numbers “I 1 ”, “F 1 ” and “P 1 ” represent an interconnection region, a fuse region, and a pad region, respectively. 
     Referring to  FIGS. 2 and 3F , a first interlayer insulating layer  15  is disposed on a semiconductor substrate  10 . Various discrete elements, for example, transistors and resistors may be disposed between the semiconductor substrate  10  and the first interlayer insulating layer  15 . Fuse patterns  31   a ′ are disposed on the first interlayer insulating layer  15  inside the fuse region F 1 . Each of the fuse patterns  31   a ′ may include a first conductive pattern  24   a ′, and a first upper capping pattern  27   a,  which are sequentially stacked. The first conductive pattern  24   a ′ may include a first barrier pattern  20   a  and a first conductive pattern  23   a ′, which are sequentially stacked. The first upper capping pattern  27   a  may be omitted. The fuse pattern  31   a ′ may be formed with a thickness of about 3000 Å or less. 
     First interconnection patterns  31   b  are disposed on the first interlayer insulating layer  15  inside the interconnection region I 1 , and a thickness of the first interconnection pattern  31   b  is greater than that of the fuse pattern  31   a.  Each of the first interconnection patterns  31   b  may include a second conductive pattern  24   b,  a lower interface pattern  25   b,  and a capping pattern  30   b,  which are sequentially stacked. The second conductive pattern  24   b  may include a second barrier pattern  20   b  and a second conductive pattern  23   b,  which are sequentially stacked. The capping pattern  30   b  may include a lower capping pattern  26   b  and a second upper capping pattern  27   b,  which are sequentially stacked. The second upper capping pattern  27   b  may be omitted. 
     The first conductive pattern  24   a ′ has a thickness thinner than that of the second conductive pattern  24   b.  The first conductive pattern  23   a ′ and the second conductive pattern  23   b  may be the same material layer. The first conductive pattern  23   a ′ and the second conductive pattern  23   b  may be at least one material layer selected from the group consisting of an aluminum layer, a tungsten layer, and a copper layer and combinations thereof. The first and second upper capping patterns  27   a  and  27   b  may have a same thickness and may be a same material layer. The lower capping pattern  26   b  may be the same material layer as that of the second upper capping pattern  27   b.  The capping patterns  26   b,    27   a,  and  27   b  may be a titanium nitride layer. The capping patterns  26   b,    27   a,  and  27   b  may be an anti-reflective layer. The lower interface pattern  25   b  may be a titanium layer. The first and second barrier patterns  20   a  and  20   b  may be the same material layer, and may have the same thickness. The barrier patterns  20   a  and  20   b  may be a titanium nitride layer, or may be a composite layer including a titanium layer and a titanium nitride layer, which are sequentially stacked. The barrier patterns  20   a  and  20   b  may be omitted. 
     Since the first conductive pattern  23   a ′ has a thickness thinner than that of the second conductive pattern  23   b,  the fuse pattern  31   a  has a thickness thinner than that of the first interconnection pattern  31   b.  Each of the fuse patterns  31   a  may have a substantially flat upper surface. The flatness may be a result of the photolithography process and an etch process. Furthermore, the fuse patterns  31   a  may substantially have a uniform thickness within a wafer. Therefore, an error rate in a fuse blowing operation can be reduced. 
     Alternatively, as illustrated in  FIG. 4C , fuse patterns  31   a ′ may be disposed inside the fuse region F 1 , and each of the fuse patterns  31   a ′ may include a first conductive pattern  24   a ′, a first upper interface pattern  28   a,  and a first upper capping pattern  29   a,  which are sequentially stacked. The first conductive pattern  24   a ′ may include a first barrier pattern  20   a  and a first conductive pattern  23   a ′, which are sequentially stacked. The fuse pattern  31   a ′ may have a thickness of about 3000 Å or less. Furthermore, first interconnection patterns  31   b ′ may be disposed inside the interconnection region I 1 , and each of the first interconnection patterns  31   b ′ may include a second conductive pattern  24   b,  a second upper interface pattern  28   b,  and a second upper capping pattern  29   b,  which are sequentially stacked. The second conductive pattern  24   b  may include a second barrier pattern  20   b  and a second conductive pattern  23   b,  which are sequentially stacked. The first conductive pattern  24   a ′ has a thickness thinner than that of the second conductive pattern  24   b.  The fuse pattern  31   a ′ has a thickness thinner than that of the first interconnection pattern  31   b ′. The first and second upper capping patterns  29   a  and  29   b  may be an anti-reflective layer. 
     Referring again to  FIG. 3F , a second interlayer insulating layer  33  is disposed on the substrate having the fuse patterns  31   a  and the first interconnection patterns  31   b.  The second interlayer insulating layer  33  may be a material layer selected from the group consisting of a tetra ethyl ortho silicate (TEOS) layer, a flowable oxide (FOX) layer, a plasma enhanced-TEOS (PE-TEOS) layer, a boron phosphorous silicate glass (BPSG) layer, and combinations thereof. For example, the second interlayer insulating layer  33  may be a TEOS layer, a FOX layer, and a TEOS layer, which are sequentially stacked. Since a portion between the patterns  31   a  and  31   b  is filled with the FOX layer, the second interlayer insulating layer  33  may have a flat upper surface. 
     Via holes  34   h  may be disposed penetrating the second interlayer insulating layer  33  inside the interconnection region I 1  and exposing predetermined portions of the first interconnection patterns  31   b . Via contact plugs  34  may fill the via holes  34   h.  The via hole  34   h  may expose the inside of the capping pattern  30   b,  or may penetrate the capping pattern  30   b  so as to expose the lower interface pattern  25   b.    
     Second interconnection patterns  40  may be disposed on the second interlayer insulating layer  33  inside the interconnection region I 1 . The second interconnection pattern  40  may include an upper barrier pattern  35 , an upper conductive pattern  37 , and an upper capping pattern  39 , which are sequentially stacked. Each of the second interconnection patterns  40  may be electrically connected to each of the first interconnection patterns  31   b  through each of the via contact plugs  34 . A pad  40   p  is disposed on the second interlayer insulating layer  33  inside the pad region P 1 . The pad  40   p  may include a pad conductive pattern  38   p  and a pad capping pattern  39   p,  which are sequentially stacked, and the pad conductive pattern  38   p  may include a pad barrier pattern  35   p  and a pad conductive pattern  37   p,  which are sequentially stacked. 
     A passivation layer  43  may be disposed on the substrate having the second interconnection patterns  40  and the pad  40   p.  The passivation layer  43  may be a composite layer including a plasma oxide layer  41  and a plasma nitride layer  42 , which are sequentially stacked. A polyimide pattern  50  may be disposed on the substrate having the passivation layer  43 , and the polyimide pattern  50  has a fuse window opening  50   f  and a pad window opening  50   p  exposing a predetermined portion of the fuse region F 1  and a predetermined portion of the pad region P 1  respectively. 
     A fuse window  53   f  is disposed penetrating the passivation layer  43  below the fuse window opening  50   f  inside the fuse region F 1 , and penetrating to a predetermined depth in the second interlayer insulating layer  33  below the passivation layer  43 . A thin second interlayer insulating layer  33   a  covering the fuse patterns  31   a  is disposed below the fuse window  53   f.  Since the thin second interlayer insulating layer  33   a  covering the fuse patterns  31   a  is an oxide layer, a lower energy is required to blow the fuse patterns  31   a  than the energy required in the related art, in which a silicon nitride layer is used as a fuse-protecting layer. 
     A pad window  53   p  is disposed to penetrate predetermined portions of the passivation layer  43  and the pad capping pattern  39   p  below the pad window opening  50   p  inside the pad region P 1 , and expose the pad conductive pattern  38   p.    
     As described above, according to embodiments, after a conductive layer is formed, a fuse conductive layer having a thickness thinner than that of the conductive layer is formed by partially etching. By patterning the conductive layer and the fuse conductive layer, first interconnection patterns and fuse patterns are concurrently formed respectively. As a result, each of the fuse patterns can have a thickness thinner than that of each of the first interconnection patterns, and can have a flat upper surface since the fuse patterns are formed to be patterned through a photolithography process and an etch process. Furthermore, since the fuse conductive layer having a thickness thinner than that of the conductive layer is formed by partially etching in advance, a thickness uniformity of the fuse patterns over a single wafer can be improved. Therefore, the fuse patterns can be blown using a uniform low energy, and since the fuse patterns are formed thin in thickness, an amount of the residual material of the fuse patterns by the blowing of the fuse patterns can be reduced, thereby reducing a bridge with the adjacent metal fuse. 
     Furthermore, since a fuse window and a pad window are formed using a polyimide pattern as an etch mask, the number of the photolithography processes used can be shortened to one, reducing production costs. 
     Although particular embodiments have been described, one of ordinary skill in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of the following claims.