Patent Publication Number: US-8116717-B2

Title: Self-calibrating direct conversion transmitter with converting/steering device

Description:
CROSS REFERENCE TO RELATED APPLICATION 
     The present application is a Continuation Application of U.S. patent application Ser. No. 11/467,831 now U.S. Pat. No. 7,881,681, which was filed on Aug. 28, 2006, and is incorporated by reference in its entirety. 
    
    
     TECHNICAL FIELD OF THE INVENTION 
     The present invention relates to a direct conversion transmitter (DCT), more particularly, to a steering and mixing module. 
     BACKGROUND OF THE INVENTION 
     Direct conversion transmitters are widely used in the field of wireless communication. In a direct conversion transmitter, baseband in-phase (I) and quadrature-phase (Q) signals are up-converted into radio frequency (RF) signals with a carrier provided by a local oscillator. Then the up-converted I signal and Q signal are then summed, amplified as an output signal and the output signal is transmitted via an antenna. 
     Carrier leakage caused by local oscillator error, baseband mismatch etc. is a concerned issue for the direct convention transmitter. To eliminate or reduce carrier leakage, a common solution is to detect an output of the direct conversion transmitter when no I and Q signals are input thereto, so as to obtain the leakage, and generate a compensation signal based on the detected leakage, led to reduce or even eliminate the leakage. The detection and compensation procedures can be repeated until the leakage is minimized. 
     For some applications, such as WCDMA, it is necessary to provide an RF variable gain amplifier (VGA) on a signal output path of the direct conversion transmitter to adjustably generate an output signal with a variable gain under a transmission condition. Further, under a calibration condition, before detecting the output signal for leakage upon no I and Q input signals fed into the transmitter, it is optimal to down-convert the leakage at radio frequency (RF) into a lowered frequency, such as an intermediate frequency (IF) or a baseband (BB) frequency for the convenience of process in the subsequent steps. 
     SUMMARY OF THE INVENTION 
     A first aspect of the present invention is to provide a steering and mixing module. The steering and mixing module comprises a double balanced switch quad and a steering quad. The double balanced switch quad and the steering quad share an output pair. 
     A second aspect of the present invention is to provide a steering and mixing module. The steering and mixing module comprises a double balanced switch quad and a steering quad. The double balanced switch quad comprises a first output pair, and the first output pair is coupled to a first load stage. The steering quad comprises a second output pair, and the second output pair is coupled to a second load stage. The double balanced switch quad and the steering quad share an input pair. 
     A third aspect of the present invention is to provide a steering and mixing module. The steering and mixing module comprises a double balanced switch quad and a steering quad. The steering quad is activated in a first mode, and the double balanced switch quad is activated in a second mode. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The present invention will be further described in detail in conjunction with the accompanying drawings, wherein: 
         FIG. 1  is a block diagram schematically showing a direct conversion transmitter in accordance with the present invention; 
         FIG. 2  is a block diagram schematically showing the converting/steering device in  FIG. 1 ; 
         FIG. 3  is a schematic circuit diagram of a merged mixer/VGA in accordance with an embodiment of the present invention; 
         FIG. 4  is a block diagram schematically showing the mode controller in  FIG. 2 ; and 
         FIG. 5  is a schematic circuit diagram of a merged mixer/VGA in accordance with another embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       FIG. 1  is a block diagram schematically showing a direct conversion transmitter in accordance with the present invention.  FIG. 1  roughly illustrates only the essential elements for the sake of simplification and clarification. 
     When the direct conversion transmitter is under a transmission condition, an in-phase (I) baseband signal Ibb and a quadrature-phase (Q) baseband signal Qbb are up-converted into a radio frequency (RF) I and Q signals with an I component and Q component of a first local oscillator (LO) signal LO 1  from an first local oscillator  20 , respectively, by up-mixers  21  and  23 . Then the RF I and Q signals are summed by a summing device  30  into a combined RF signal. The combined RF signal is adjusted with a variable gain by a converting/steering device  40  which is switched to a normal mode, and then is amplified by a power amplifier  60  and transmitted via an antenna  70 . 
     When the direct conversion transmitter is under a calibration condition, no baseband signals Ibb and Qbb are input to the transmitter. A leakage signal, which may be generated due to the local oscillator  20  or other sources, is easy to be detected in this condition. The converting/steering device  40  is switched to a calibration mode and operates as a down-mixer to down-convert the leakage signal into a lowered frequency with a second local oscillator (LO) signal LO 2  provided by a second local oscillator  50 . It is noted that the first and second local oscillators  20 ,  50  can be combined as a single module in some applications. The LO signals LO 1  and LO 2  can be provided by any proper method. The down-converted leakage signal is then detected by a calibration detection/determination unit  81 . Analog to digital conversion is preferably done after leakage-signal detection. The calibration detection/determination unit  81  determines and generates a compensation signal based on the detected leakage signal according to a calibration algorithm stored therein. 
     Any proper calibration algorithm can be used in the present invention, for example, a binary tree search algorithm is preferred, referring to “Carrier leakage suppression in direct-conversion WCDMA transmitters” G. Brenna, D. Tschopp, and Q. Huang, IEEE ISSCC Dig. Tech. Papers, pp. 270-271, San Francisco, Calif., February 2003; and “A 2-Ghz carrier leakage calibrated direct-conversion WCDMA transmitter in 0.13-_m CMOS”, G. Brenna et al., IEEE J. Solid-State Circuit, vol. 39, pp. 1253-1262, August 2004. 
     The calibration detection/determination unit  81  provides a calibration compensation unit  83  with the compensation signal, and the compensation unit  83  feeds the compensation signal to summing devices  11  and  12 , so that the compensation signal is incorporated into each of the input I and Q signals Ibb and Qbb by the summing devices  11 ,  12  in the transmission condition, so as to eliminate or reduce the leakage. Digital to analog conversion is done before the compensation signal is fed to the summing device  11  or  12 . 
     The calibration detection/determination unit  81  and the calibration compensation unit  83  can be combined as a single calibration processing unit (not shown). 
     As mentioned above, the converting/steering device  40  has two modes including a normal mode and a calibration mode. In the normal mode, the converting/steering device  40  operates as a variable gain amplifier to adjust the output signal with a variable gain. In the calibration mode, the converting/steering device  40  operates as a down-mixer to down-convert the RF leakage signal to the lowered frequency. 
       FIG. 2  is a block diagram schematically showing the converting/steering device  40 . As shown in this drawing, the converting/steering device  40  preferably comprises a steering and mixing module, which is implemented by a merged mixer/variable gain amplifier (VGA)  43 . In addition, the device  40  also has a mode controller  45 . The merged mixer/VGA  43  has a mixing stage  431  and an amplifying stage  433  (detailed later). The mode controller  45  receives a mode selection signal SEL and switches the merged mixer/VGA  43  to be in one of the normal mode and calibration mode. 
     In a preferred embodiment, when the DCT is under the transmission condition, the mode controller  45  controls DC biases of the merged mixer/VGA  43  to switch the merged mixer/VGA  43  into the normal mode, and blocks the second local oscillator signal LO 2  generated by the second local oscillator  50  from entering into the merged mixer/VGA  43 , so that the amplifying stage  433  operates as an RF VGA, while the mixing stage  431  does not work. 
     When the DCT is under the calibration condition, the mode controller  45  controls DC biases of the merged mixer/VGA  43  to switch the merged mixer/VGA  43  into the calibration mode, and allows the second local oscillator (LO) signal LO 2  generated by the second local oscillator  50  to enter into the merged mixer/VGA  43 , so that the mixing stage  431  operates as a down-mixer, while the amplifying stage  433  can be deactivated or operate as an amplifier to amplify the down-converted leakage, so that it is easy to detect the amplified leakage. The details concerning this matter will be further described. 
       FIG. 3  illustrates a merged mixer/VGA  43  in accordance with an embodiment of the present invention. The merged mixer/VGA  43  of  FIG. 3  includes the mixing stage  431  implemented by a double balanced switch quad having four transistors Q 1 , Q 2 , Q 3  and Q 4 , which are connected to form a double balanced mixer, and the amplifying stage  433  implemented by a steering quad having four transistors Q 5 , Q 6 , Q 7  and Q 8 , which are connected to form an RF VGA. 
     The bases of transistors Q 1 , Q 2 , Q 3  and Q 4  are LO/DC inputs. In the calibration mode, differential local oscillator components LO P  and LO N  of the local oscillator signal LO 2 , as well as differential components of a DC bias signal are fed into the mixing stage  431  via the LO/DC inputs, that is, the bases of transistors Q 1 , Q 2 , Q 3  and Q 4  as shown. 
     In the normal (transmission) mode, the DC bias signal is controlled to turn off the transistors Q 1 , Q 2 , Q 3  and Q 4 . Accordingly, the mixing stage  431  does not operate. In addition, no LO signal components are fed to the bases of transistors Q 1 , Q 2 , Q 3  and Q 4 . 
     The bases of transistors Q 5  and Q 8  are connected together at a node N 1 , and the bases of transistors Q 6  and Q 7  are connected together at a node N 2 . Control signals VC P  and VC N  are applied to the amplifying stage  433  from the nodes N 1  and N 2 , respectively. The operation and gain of the amplifying stage  433  can be controlled by adjusting the control signals VC P  and VC N . 
     The emitters of transistors Q 1 , Q 2 , Q 5  and Q 6  are connected together as an input port, while the emitters of transistors Q 3 , Q 4 , Q 7  and Q 8  are connected together as another input port. The pair of input ports are connected to an input stage  435 , which is known in this field, and the description thereof is omitted herein. 
     In the normal mode, a signal to be processed is input into the merged mixer/VGA  43  from the input ports, and is steered with a predetermined gain by the amplifying stage  433 . In the calibration mode, a leakage is input into the merged mixer/VGA device  43  from the input ports, and is down-converted by the mixing stage  431  with the local oscillator components LO P  and LO N  of the second LO signal LO 2 . 
     The collectors of transistors Q 1 , Q 3  and Q 8  are connected together as an output port, and the collectors of transistors Q 2 , Q 4  and Q 5  are connected together as another output port. The gain-steered or down-converted signal is output from the pair of output ports. The output ports are connected to a load stage  437 , which is formed by shunted resistors, for instance. The collectors of transistors Q 6  and Q 7  are connected to a power source VCC. 
     As mentioned above and shown in the  FIG. 3 , the amplifying stage  433  have the four transistors Q 5 , Q 6 , Q 7  and Q 8  connected as an RF VGA. The amplifying stage  433  including these four transistors Q 5 , Q 6 , Q 7  and Q 8  is referred to a single stage RF VGA circuit. 
     In another embodiment, an RF VGA circuit with two or more stages can be used. One stage of the RF VGA circuits is merged with the mixing stage  431  as illustrated in  FIG. 3 , while the other stage(s) is/are connected with the merged stage in a cascade form. It is noted that only the merged stage RF VGA is used as the amplifying stage  433  in accordance with the present invention, while the other stage(s) is/are used as normal RF VGA(s). 
     The controls of DC bias, LO and control signals are performed by the mode controller  45 . The mode controller  45  receives a mode selection signal SEL indicating the operation condition of the direct conversion transmitter and selects either the normal (transmission) mode or calibration mode accordingly. 
     The mode controller  45  includes a DC control unit  451  and a LO control unit  453 . 
     The DC bias signal for the mixing stage  431  and the control signals VC P , VC N  for the amplifying stage  433  are controlled by DC control unit  451  of the mode controller  45 . 
     In the normal mode, the control signals VC P  and VC N  for the amplifying stage  433  are applied via a normal path other than the mode controller  45 . The DC bias signals of the mixing stage  431  are controlled so that the current is forced to flow through the amplifying stage  433  rather than the mixing stage  431 . For example, the DC control unit  451  may pull-down the level of the DC bias signal of the mixing stage  431  to zero so that transistors Q 1 , Q 2 , Q 3  and Q 4  are turned off. Alternatively, the level of DC bias of the mixing stage  431  can be dropped lower than the control signals VC P , VC N , whereby the current is forced to flow through the amplifying stage  433 . In addition, the LO control unit  453  blocks the second LO signal LO 2  generated by the second local oscillator  50 , so that no LO signal enters into the mixing stage  431 . 
     In the calibration mode, the DC control unit  451  of the mode controller  45  controls the level of the DC bias for the mixing stage  431  to be higher than the control signals VC P , VC N , so that the current is forced to flow through the mixing stage  431 . It is preferred that the control signals VC P , VC N  are also controlled by the mode controller  45  in the calibration mode to ensure that a great portion or all of the current flow through the mixing stage  431 . In this manner, the down-conversion function can be performed smoothly. Furthermore, the LO control unit  453 , which receives the second LO signal LO 2  from the second local oscillator  50 , passes the second LO signal LO 2  to the mixing stage  431 , that is, the bases of transistors Q 1 , Q 2 , Q 3  and Q 4  in the calibration mode. Accordingly, the mixing stage  431  can mix the input signal fed through the input ports with the LO N , LO P , the differential components of the second LO signal LO 2 , to generate a down-converted output signal. 
       FIG. 5  illustrates a merged mixer/VGA  43 ′ in accordance with another embodiment of the present invention. The structure of the merged mixer/VGA  43 ′ is similar to that of the merged mixer VGA  43  in  FIG. 3 . A mixing stage of the merged mixer/VGA  43 ′ comprises transistors Q 1 , Q 2 , Q 3  and Q 4  constituting a double balanced switch quad; and an amplifying stage thereof comprises transistors Q 5 , Q 6 , Q 7  and Q 8  constituting a steering quad. The pair of input ports of the merged mixer/VGA  43 ′ are connected to an input stage  535 . The pair of input ports of the merged mixer/VGA  43 ′ are respective the connection of the emitters of transistors Q 1 , Q 2 , Q 5  and Q 6  and the connection of the emitters of transistors Q 3 , Q 4 , Q 7  and Q 8 . As described, the mixer/VGA  43  in  FIG. 3  has only one pair of output ports (the collectors of transistors Q 1 , Q 3  Q 8  and the collectors of transistors Q 2 , Q 4 , Q 5 ) and the one pair of output ports are connected to the load stage  437 . Different from the mixer/VGA  43 , the mixer/VGA  43 ′ has two pairs of output ports. A first pair of output ports Out 1 _p and Out 1 _n are respectively the collectors of transistors Q 5  and Q 8 . A second pair of output ports Out 2 _p and Out 2 _n are respectively the collector connection of transistors Q 2 , Q 4  and the collector connection of transistors Q 1 , Q 3 . In addition, the first pair of output ports are connected to a first load stage (Load  1 )  537 , while the second pair of output ports are connected to a second load stage (Load  2 )  539 . 
     In the embodiments of the present invention, the transistors Q 1  to Q 8  are implemented by bipolar junction transistors (BJTs). However, other types of transistors, such as CMOS, also can be used. 
     While the preferred embodiment of the present invention has been illustrated and described in detail, various modifications and alterations can be made by persons skilled in this art. The embodiment of the present invention is therefore described in an illustrative but not restrictive sense. It is intended that the present invention should not be limited to the particular forms as illustrated, and that all modifications and alterations which maintain the spirit and realm of the present invention are within the scope as defined in the appended claims.