Patent Publication Number: US-7718467-B2

Title: Memory device

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This is a Continuation of co-pending U.S. patent application Ser. No. 11/120,007, filed on May 2, 2005, assigned to the assignee of the present invention and incorporated herein by reference. 
    
    
     BACKGROUND 
     Semiconductor chips provide memory storage for electronic devices and have become very popular in the electronic products industry. In general, many semiconductor chips are typically formed (or built) on a silicon wafer. The semiconductor chips are individually separated from the wafer for subsequent use as memory in electronic devices. In this regard, the semiconductor chips define memory cells that are configured to store retrievable data, often characterized by the logic values of 0 and 1. 
     Phase change memory cells are one type of memory cell capable of storing retrievable data between two or more separate states (or phases). The phase change memory cells have a structure that can generally be switched between states. For example, the atomic structure of one type of phase change memory cells can be switched between an amorphous state and one or more crystalline states. In this regard, the atomic structure can be switched between a general amorphous state and multiple crystalline states, or the atomic structure can be switched between a general amorphous state and a uniform crystalline state. In general terms, the amorphous state can be characterized as having more electrical resistivity than the crystalline state(s), and typically includes a disordered atomic structure. In contrast, the crystalline state(s) generally has a highly ordered atomic structure and is associated with having a higher electrical conductivity than the amorphous state. 
     Materials that exhibit this phase change memory characteristic include the elements of Group VI of the periodic table (and their alloys), such as Tellurium and Selenium, referred to as chalcogenides or chalcogenic materials. Other non-chalcogenide materials also exhibit phase change memory characteristics. One characteristic of chalcogenides is that the electrical resistivity varies between the amorphous state and the crystalline state(s), and this characteristic can be beneficially employed in two level or multiple level systems where the resistivity is either a function of the bulk material or a function of the partial material. As a point of reference, it is relatively easy to change a chalcogenide between the amorphous state (exhibiting a disordered structure, for example, like a frozen liquid) and the crystalline state(s) (exhibiting a regular atomic structure). In this manner, manipulating the states of the chalcogenide permits a selective control over the electrical properties of the chalcogenide, which is useful in the storage and retrieval of data from the memory cell containing the chalcogenide. 
     The atomic structure of the chalcogenide can be selectively changed by the application of energy. With regard to chalcogenides in general, at below temperatures of approximately 150 degrees Celsius both the amorphous and crystalline states are stable. A nucleation of crystals within the chalcogenide can be initiated when temperatures are increased to the crystallization temperature for the particular chalcogenide (approximately 200 degrees Celsius). In particular, the atomic structure of a chalcogenide becomes highly ordered when maintained at the crystallization temperature, such that a subsequent slow cooling of the material results in a stable orientation of the atomic structure in the highly ordered (crystalline) state. To achieve the amorphous state in the chalcogenide material, the local temperature is generally raised above the melting temperature (approximately 600° C.) to achieve a highly random atomic structure, and then rapidly cooled to “lock” the atomic structure in the amorphous state. 
     In one known structure of a phase change memory cell, the memory cell is formed at the intersection of a phase change memory material (chalcogenide) and a resistive electrode. Passing an electrical current of an appropriate value through the resistive electrode heats the phase change memory cell, thus affecting a phase change in its atomic structure by the principals described above. In this manner, the phase change memory cell can be selectively switched between logic states 0 and 1, and/or selectively switched between multiple logic states. 
     With the above background in mind, the known lithographic techniques for forming phase change memory cells can be improved upon. In particular, the known lithographic techniques for forming phase change memory cells result in large contact areas between the resistive electrode and the phase change memory material such that temperature induced changes between logic states is not optimum. 
     SUMMARY 
     One embodiment of the present invention provides a phase change memory cell. The phase change memory cell comprises a first thin film spacer and a second thin film spacer. The first thin film spacer defines a sub-lithographic dimension and is electrically coupled to a first electrode. The second thin film spacer defines a sub-lithographic dimension and is electrically coupled between a second electrode and the first thin film spacer. In this regard, the phase change memory cell is formed at a boundary where the first thin film spacer electrically contacts the second thin film spacer. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Embodiments of the invention are better understood with reference to the following drawings. The elements of the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding similar parts. 
         FIG. 1  illustrates a perspective view of one embodiment of a memory wafer including a plurality of memory chips. 
         FIG. 2  illustrates a top view of one embodiment of a memory device illustrating an array of phase change memory cells disposed on a chip separated from the memory wafer. 
         FIG. 3  illustrates a simplified cross-sectional view of one embodiment of the memory device illustrated in  FIG. 2 . 
         FIG. 4  illustrates a simplified cross-sectional view of one embodiment of a series of plugs disposed in a field of dielectric material. 
         FIG. 5  illustrates a simplified cross-sectional view of one embodiment of a photoresist layer disposed on an insulating layer as illustrated in  FIG. 4 . 
         FIG. 6  illustrates a simplified cross-sectional view of one embodiment of a step having edges that lie on adjacent plugs. 
         FIG. 7  illustrates a top view of steps disposed to lie on adjacent plugs as illustrated in  FIG. 6 . 
         FIG. 8  illustrates a simplified cross-sectional view of one embodiment of a spacer material deposited over a top portion of the step illustrated in  FIG. 6 . 
         FIG. 9  illustrates a simplified cross-sectional view of one embodiment of spacers extending across a plurality of rows of plugs. 
         FIG. 10  illustrates a simplified cross-sectional view of one embodiment of a dielectric disposed over the spacers illustrated in  FIG. 9 . 
         FIG. 11  illustrates a simplified cross-sectional view of one embodiment of the spacers illustrated in  FIG. 9  after a planarization step. 
         FIG. 12  illustrates a simplified cross-sectional view of one embodiment of an array of plugs. 
         FIG. 13  illustrates a simplified cross-sectional view of one embodiment of a photoresist layer disposed upon adjacent rows of plugs within the array as illustrated in  FIG. 12 . 
         FIG. 14  illustrates a simplified cross-sectional view of one embodiment of an oxide step having edges that lie on adjacent plugs in rows of the array. 
         FIG. 15  illustrates a simplified cross-sectional view of one embodiment of a deposition of spacer material across rows of the arrays. 
         FIG. 16  illustrates a simplified cross-sectional view of one embodiment of spacers extending across columns and centered on rows of plugs. 
         FIG. 17  illustrates a simplified cross-sectional view of one embodiment of a deposition of a dielectric over the spacers illustrated in  FIG. 16 . 
         FIG. 18  illustrates a simplified cross-sectional view of one embodiment of spacers extending across columns of an array after a planarization step. 
         FIG. 19  is a top view of one embodiment of an array of non-parallel spacers. 
         FIG. 20  is a top view of one embodiment of the array of non-parallel spacers separated into memory cells after an etch step. 
         FIG. 21  illustrates a top schematic view of one embodiment of a memory device illustrating an array of phase change memory cells disposed on a chip. 
         FIG. 22  illustrates a perspective view of one embodiment of a first spacer tilted relative to a second spacer and showing a sub-lithographic contact area. 
         FIG. 23  illustrates a perspective view of one embodiment of the memory device illustrated in  FIG. 21  after subsequent back end processing steps. 
         FIG. 24  illustrates an electronic system including an electronic device electrically connected to the memory device illustrated in  FIG. 23 . 
     
    
    
     DETAILED DESCRIPTION 
       FIG. 1  is a perspective view of a simplified memory wafer  40  according to one embodiment of the present invention. The memory wafer  40  includes a silicon wafer  42  having a plurality of separable memory chips  44  disposed thereon. Each of the separable memory chips  44  include an array of memory cells formed as described below. 
       FIG. 2  is a top view of a memory device  50  including an array  52  of phase change memory cells  54   a - 54   e  disposed on a chip  44  separated from the memory wafer  40 . Array  52  of phase change memory cells  54  is defined by a plurality of first spacers  58   a ,  58   b ,  58   c  deposited to extend in a first direction across array  52 , and a plurality of second spacers  60   a ,  60   b ,  60   c  deposited to extend in a second direction across array  52  non-parallel to the first direction. In this regard, each of first spacers  58   a ,  58   b ,  58   c  and second spacers  60   a ,  60   b ,  60   c  define at least one sub-lithographic dimension such that second spacers  60   a ,  60   b ,  60   c  electrically contact the first spacers  58   a ,  58   b , and  58   c  across a sub-lithographically small contact area. A phase change memory cell, for example phase change memory cell  54   a , is formed at each intersection at each of the first spacers  58   a ,  58   b ,  58   c , with each of the second non-parallel spacers  60   a ,  60   b ,  60   c  (and specifically, in this instance, first spacer  58   a  and second spacer  60   a ). As described below, in one embodiment an etch process is employed to separate the intersecting plurality of first spacers  58   a ,  58   b ,  58   c  and second spacers  60   a ,  60   b ,  60   c  into an array of mutually related, but separate, memory cells. 
     In addition,  FIG. 2  illustrates that memory device  50  defines a plurality of plugs  62   a ,  62   b ,  62   c ,  62   d ,  62   e  disposed within a dielectric field  70 . As a point of reference, dielectric field  70  can be an oxide field, a nitride field, or other dielectric having suitable thermal etch and electrical characteristics. In one embodiment, the plugs  62   a - 62   e  are electrically conductive and form a first electrode for each of the respective phase change memory cells  54   a - 54   e . In this regard, plugs  62   a - 62   e  define electrical contact, and can be formed of material including, but not limited to, tungsten, copper, or any other suitable plug material. 
     It is to be understood that chip  44  illustrates but a limited portion of array  52  and in this regard shows only a limited number of the phase change memory cells  54 . In addition, one with skill in the art will recognize that spacers  60   a ,  60   b ,  60   c  can exhibit a range of electrical resistance properties depending upon factors such as material properties and physical structure. In this regard, in one embodiment first spacers  58   a ,  58   b ,  58   c  are “resistive,” wherein the electrical resistance of first spacers  58   a ,  58   b ,  58   c  is, in general, greater than the electrical resistance of second spacers  60   a ,  60   b ,  60   c . In another embodiment, first spacers  58   a ,  58   b ,  58   c  are “conductive” spacers. 
     As a point of reference, array  52  comprises rows and columns of memory cells  54 . In this regard, memory cells  54   a ,  54   b ,  54   c  are defined to be in separate columns of array  52 , and memory cells  54   c ,  54   d ,  54   e  are defined to be in separate rows of array  52 . To this end, an exemplary embodiment of processing a plurality of first spacers  58   a ,  58   b ,  58   c  intersecting with a plurality of second non-parallel spacers  60   a ,  60   b ,  60   c  that enables large areas of memory device  50  to be “block exposure” processed in a contemporaneous manner to include an array  52  of phase change memory cells  54  having sub-lithographic dimensions is described below. 
       FIG. 3  is a cross-sectional view of a portion of memory device  50  illustrating columns of plugs  62   a ,  62   b ,  62   c  (i.e., conductive electrodes) disposed in dielectric field  70  and including columns of first spacers  58   a ,  58   b ,  58   c , and one row of a second spacer  60   a  (illustrated by dotted line) in electrical contact with spacers  58   a ,  58   b , and  58   c , according to one embodiment of the present invention. An exemplary block exposure process to achieve the structure illustrated in  FIG. 3  will be described with reference to the following figures. 
       FIG. 4  is a simplified cross-sectional view of a substrate  72  of wafer  42  including a silicon nitride layer  80  according to one embodiment of the present invention. Substrate  72  includes columns of plugs  62   a ,  62   b ,  62   c  disposed in dielectric field  70  in an initial stage of front end processing. As a point of reference, substrate  72  also includes lower wafer levels that are not shown for ease of illustration. Substrate  72  is built up with subsequent process steps in forming memory device  50  ( FIG. 2 ). In this regard, a first process step includes depositing silicon nitride layer  80  across substrate  72 . 
       FIG. 5  illustrates a first photoresist layer  90  extending across adjacent plugs  62   a ,  62   b  and a second photoresist layer  92  centered on a column of plugs  62   c  according to one embodiment of the present invention. Photoresist layers  90 ,  92  extend along rows of array  52  ( FIG. 2 ) and span adjoining plugs. Photoresist layers  90 ,  92  are patterned directly onto silicon nitride layer  80  via, for example, a photolithography step, and can include spin-coated photoresist materials as known to one of skill in the art. 
       FIG. 6  illustrates silicon nitride layer  80  ( FIG. 5 ) after etching and stripping photoresist layers  90 ,  92  wherein silicon nitride layer  80  is partially removed to expose steps  80   a ,  80   b  of silicon nitride having edges lying on adjacent columns of plugs  62   a ,  62   b , and  62   c . Specifically, silicon nitride step  80   a  spans and is centered on tungsten plug  62   a ,  62   b.    
       FIG. 7  illustrates a top view of silicon nitride steps  80   a ,  80   b  disposed atop dielectric field  70  such that edges of steps  80   a ,  80   b  lie on adjacent plugs  62   a ,  62   b , and  62   c  (and hence, edges of steps  80   a ,  80   b  are configured to lie on adjacent plugs).  FIG. 7  illustrates a building block geometry that enables block exposure deposition of materials onto wafer  42  ( FIG. 1 ) that permits large areas of rows and columns of memory cells to be processed at the same time, while also minimizing deleterious edge effects that can result in delays in temperature-induced changes between logic states. 
       FIG. 8  illustrates a deposition of spacer material  100  extending across silicon nitride steps  80   a ,  80   b  according to one embodiment of the present invention. The spacer material  100  can be selected from a variety of materials in accordance with the present invention. Generally, chalcogenide alloys comprising one or more elements of Column IV-VI of the periodic table are useful as spacer material. In one embodiment, spacer material  100  is a chalcogenide alloy comprising GeSbTe (GST), for example Ge 2 Sb 2 Te, or AgInSbTe. In one embodiment, spacer material  100  is titanium nitride having a resistivity of between 30-70 ohm-cm and a melting point of 2950 degrees Celsius. 
     Spacer material  100  is preferably deposited to have a sub-lithographic thickness of less than approximately 50 nanometers, more preferably the spacer material  100  is deposited to have a thickness of less than approximately 30 nanometers, and most preferably spacer material  100  is deposited to have a sub-lithographic thickness of approximately 20 nanometers. Spacer material  100  can be deposited by chemical vapor deposition (CVD), atomic layer deposition (ALD), metal organic chemical vapor deposition (MOCVD), plasma vapor deposition (PVD), jet vapor deposition (JVD), or any other suitable deposition technique. In this manner, a block exposure deposition of spacer material  100  having sub-lithographic dimensions is formed over a large area of wafer  42  ( FIG. 1 ). 
       FIG. 9  illustrates spacers  100   a ,  100   b ,  100   c  disposed in columns and extending across rows of substrate  72  according to one embodiment of the present invention after a reactive ion etch. The reactive ion etch removes selective portions of spacer material  100  ( FIG. 8 ) resulting in spacers  100   a ,  100   b ,  100   c  remaining attached to steps  80   a ,  80   b , respectively. As a point of reference, spacers  100   a ,  100   b ,  100   c  after the reactive ion etch define sub-lithographic dimensions characterized by the thickness of the deposition layer, which in one embodiment is approximately 20 nanometers. In this regard, the reactive ion etch enables large areas of wafer  42  ( FIG. 1 ) to be block exposure processed with columns of spacers, for example columns of spacers  100   a ,  100   b ,  100   c  that are insensitive to an angular orientation of adjacent steps  80   a ,  80   b  to which spacers  100   a ,  100   b ,  100   c  are adhered to. Thus, the reactive ion etch is a time-efficient and robust process for the bulk formation of spacers on substrate  72 . 
       FIG. 10  is a cross-sectional view illustrating a bulk silicon nitride deposition  110  extending over spacers  100   a ,  100   b , and  100   c  according to one embodiment of the present invention. In one embodiment, the bulk deposition  110  is on the order of several hundred nanometers thick. As a point of reference, nitride deposition  110  can be a dielectric, in general, having suitable thermal etch and electrical characteristics. 
       FIG. 11  illustrates silicon nitride deposition  110  ( FIG. 10 ) after a chemical mechanical polishing (CMP) processing step (i.e., a planarization step) according to one embodiment of the present invention. Silicon nitride deposition  110  has been removed such that spacers  100   a ,  100   b ,  100   c  are sandwiched between silicon nitride. In particular, spacer  100   a  is sandwiched between step  80   a , and step  110   a , and spacer  100   b  is sandwiched between step  80   a  and step  110   b . Consequently, spacers  100   a ,  100   b ,  100   c  extend in separate columns across rows of substrate  72  and are in electrical contact with conductive electrode plugs  62   a ,  62   b ,  62   c , respectively. 
       FIG. 12  illustrates substrate  72  rotated by 90 degrees such that a view along rows of plugs  62   c ,  62   d ,  62   e  is provided (see  FIG. 2 ). In particular, step  80   b  is illustrated extending across substrate  72  such that spacers  100   a ,  100   b ,  100   c  are not visible in the view of  FIG. 12 . In addition,  FIG. 12  illustrates a dielectric layer  120 , for example an oxide layer  120 , disposed over spacers  100   a ,  100   b ,  100   c  and steps  80   a ,  80   b ,  110   a , and  110   b  illustrated in  FIG. 10 . To this end, when viewed down rows  62   c ,  62   d , and  62   e , oxide layer  120  is in contact with step  80   b . As a point of reference, dielectric layer  120  can be any suitable layer of dielectric material, and is referred to hereafter for purposes of descriptive clarity as an oxide layer  120 . 
       FIG. 13  illustrates a patterned photoresist layer according to one embodiment of the present invention. Photoresist layers  130   a ,  130   b  are patterned directly onto oxide layer  120  via, for example, a photolithography step, and can include spin-coated photoresist materials as known to one of skill in the art. A first photoresist layer  130   a  is patterned to extend over adjacent rows of plugs  62   c ,  62   d . A second photoresist layer  130   b  is patterned over and centered on a row of plugs  62   e.    
       FIG. 14  illustrates substrate  72  after etching and stripping photoresist layers  130   a ,  130   b  according to one embodiment of the present invention. In particular, the photoresist layers  130   a ,  130   b  ( FIG. 13 ), and portions of exposed oxide layer  120  have been removed to expose oxide steps  120   a ,  120   b  centered on rows of plugs  62   c ,  62   d ,  62   e  of substrate  72 . 
       FIG. 15  illustrates spacer material  140  deposited to extend over an entirety of exposed substrate  72  according to one embodiment of the present invention. In one embodiment, spacer material  140  is deposited to have a thickness of less than approximately 60 nanometers. Preferably, spacer material  140  is deposited over exposed portions of substrate  72  and has a sub-lithographic thickness of less than 50 nanometers, more preferably the thickness of spacer material  140  is less than 30 nanometers, and most preferably the thickness of spacer material  140  is approximately 20 nanometers. In this regard, spacer material  140  can be deposited by CVD, ALD, MOCVD, PVD, or JVD processes (described above), or any other suitable deposition process. In one embodiment, spacer material  140  includes a chalcogenic phase change material layer that extends approximately uniformly over oxide steps  120   a ,  120   b  and silicon nitride portion  80   b.    
     In the case where spacer material  140  is a phase change memory material, spacer material  140  is in one embodiment selected to be a chalcogenide that can comprise elements, and their alloys, as found in the periodic table of the elements in Column IV-VI. For example, in one embodiment spacer material  140  is an alloy of germanium, antimony, and tellurium having a chemical structure Ge 2 Sb 2 Te 5 . In addition, spacer material  140  can include stratified layers of chalcogenic material characterized by a variation in electrical resistivity across the stratified layers. In this manner, the electrical properties of phase change layer  140  can be selectively controlled. 
       FIG. 16  illustrates portions of spacer material  140  ( FIG. 14 ) selectively removed by a reactive ion etch process according to one embodiment of the present invention. In particular, portions of spacer material  140  have been removed from the relative horizontal portions of substrate  72  such that spacers  140   a ,  140   b ,  140   c  remain exposed and disposed along edges of oxide steps  120   a ,  120   b . As a point of reference, spacer material  140  can be deposited at sub-lithographic dimensions of approximately 20 nanometers in thickness. 
       FIG. 17  illustrates a bulk oxide layer  150  deposited to extend over exposed spacers  140   a ,  140   b , and  140   c  according to one embodiment of the present invention. In one embodiment, bulk oxide layer  150  is deposited on the order of several hundred nanometers thick. As a point of reference, oxide layer  150  can be an oxide, a nitride, or other dielectric having suitable thermal etch and electrical characteristics. 
       FIG. 18  illustrates substrate  72  after a chemical mechanical polishing of oxide layer  150  according to on embodiment of the present invention. In this regard, each of respective spacers  140   a ,  140   b , and  140   c  is disposed between oxide portions. For example, spacer  140   a  is disposed between oxide portion  120   a  and oxide portion  150   a , whereas spacer  140   b  is disposed between oxide portion  120   a  and oxide portion  150   b . To this end, spacers  140   a ,  140   b ,  140   c  are spaced in separate rows to extend along columns of substrate  72 . 
       FIG. 19  is a simplified top view of a portion of a memory device  160  defining an array of intersecting spacers  100   a ,  100   b ,  100   c  and spacers  140   a ,  140   b ,  140   c . Spacers  100   a ,  100   b ,  100   c  are non-parallel to spacers  140   a ,  140   b ,  140   c  and extend across memory chip  44 . 
       FIG. 20  is a top view of a portion of the memory device  160  after a separation etch process where portions of spacers  100   a ,  100   b ,  100   c  and spacers  140   a ,  140   b ,  140   c  have been removed to provide a first thin film spacer  100   a  defining a sub-lithographic dimension and electrically coupled to a first electrode (plug  62   a  of  FIG. 7 ), and a second thin film spacer  140   a  defining a sub-lithographic dimension and electrically coupled to a second electrode (see electrode  190  in  FIG. 23 ) and deposited non-parallel to the first thin film spacer  100   a , where a phase change memory cell is formed at a boundary of the first thin film spacer  100   a  in electrical contact with the second thin film spacer  140   a.    
     As a point of reference, at least one of spacer material  100  and spacer material  140  comprises phase change memory material. In this regard, in one embodiment the phase change memory material comprises a chalcogenide, for example, a chalcogenide alloy comprising GeSbTe (GST), such as Ge 2 Sb 2 Te, or an alloy such as AgInSbTe. In one embodiment, the phase change memory material is a non-chalcogenide, or “chalcogenide-free.” In one embodiment, for example, spacer  100   a  is a resistive “heater” spacer comprising titanium nitride and spacer  140   a  is a phase change memory spacer comprising Ge 2 Sb 2 Te, such that a phase change memory cell is provided at an intersection of spacer  100   a  and spacer  140   a . In another embodiment, spacer  100   a  is a conductive spacer and spacer  140   a  is a phase change memory spacer. In another embodiment, spacer  100   a  is a phase change memory spacer and spacer  140   a  is a conductive spacer. 
       FIG. 21  illustrates a simplified top dashed-line view of a portion of a memory device  160  highly similar to the view of  FIG. 20 . The portion of memory device  160  defines an array  162  of phase change memory cells  164  according to one embodiment of the present invention. In this regard, the memory device  160  is highly similar to the memory device  50  ( FIG. 2 ) where the first spacers  58   a ,  58   b , and  58   c  are analogous to spacers  100   a ,  100   b , and  100   c , and second spacers  60   a ,  60   b , and  60   c  are analogous to spacers  140   a ,  140   b , and  140   c , respectively. With this in mind, a plurality of first spacers  100   a ,  100   b , and  100   c  have been formed to extend in a first direction across array  162 , and a plurality of second spacers  140   a ,  140   b , and  140   c  have been formed to extend in a second direction across array  162  non-parallel to the first direction. First spacers  100   a ,  100   b ,  100   c  extend along separate columns of array  162  and intersect with second spacers  140   a ,  140   b ,  140   c . A phase change memory cell  164  is formed at each intersection of each of the first spacers  100   a ,  100   b , and  100   c  with each of the second non-parallel spacers  140   a ,  140   b ,  140   c.    
     Specifically, for example, a phase change memory cell  164   a  is formed at the intersection of first spacer  100   a  with second spacer  140   a . In a like manner, a phase change memory cell  164   e  is formed at the intersection of spacer  100   c  with spacer  140   c . In this manner, a phase change memory cell  164  is formed at each intersection of each of the first spacers  100   a ,  100   b , and  100   c  with each of the second non-parallel spacers  140   a ,  140   b ,  140   c , such that first spacers and second spacers are non-parallel and contact across a sub-lithographic dimensional area. 
       FIG. 22  illustrates spacer  100   a  and spacer  140   a  isolated from their conductive electrodes and from array  162  for ease of illustration. During processing of the spacers  100   a ,  140   a , for example, it is desired to minimize a contact area between spacer  100   a  and spacer  140   a  (having phase change memory material) such that temperature induced changes between logic states of memory cell  164   a  are rapid. With this in mind, it is generally desired that spacer  100   a  be orthogonal to spacer  140   a , and further, that a plane of spacer  100   a  be perpendicular to a plane of spacer  140   a . However, during processing, slight variations in the formation of oxide step  120   a  ( FIG. 16 ), for example, can result in a plane of spacer  140   a  being “tilted” relative to a plane of spacer  100   a , even though the respective longitudinal axes of spacer  100   a  and spacer  140  intersect at right angles. Conventional phase change memory cells that are tilted relative to one another are generally associated with inefficient current spreading and are said to be sensitive to sidewall angles. In contrast, embodiments of the present invention accommodate variations in spacer orientation such that the spacers are insensitive to variations in sidewall angles. 
     In this regard, spacer  100   a  defines a first sidewall  166  plane and spacer  140   a  defines a second sidewall  168  plane (hereafter sidewall  166  and sidewall  168 ). In one embodiment, spacer  140   a  is tilted relative to spacer  100   a  such that tilt angle A represents an orientation of spacer  140   a  relative to spacer  100   a  due to a variation in an orientation of oxide step  80   a  relative to oxide step  120   a  (See  FIGS. 9 and 16 ). In this regard, tilt angle A represents a variation in an orientation of step  80   a  relative to oxide step  120   a , otherwise referred to as a sidewall variation. Tilt angle A approximates 90 degrees, but in practice, can range between 70 degrees and 110 degrees. 
     Angle B is a crossing angle. In one embodiment, angle B is selected such that spacer  100   a  is non-parallel to spacer  140   a . In this regard, angle B is between 1 degree and 179 degrees, preferably angle B is between 30 degrees and 150 degrees, and more preferably, angle B is approximately 90 degrees. In one embodiment, sidewall  168  is tilted at angle A relative to spacer  100   a  and sidewall  166  is oriented relative to sidewall  168  as represented by angle B. 
     For example, and with additional reference to  FIG. 9  and  FIG. 16 , first spacers  100   a  and  100   b  are oriented relative to step  80   a  and second spacers  140   a  and  140   b  are oriented relative to oxide step  120   a . In this regard, and in general, first spacers  100   a ,  100   b , and  100   c  and second spacers  140   a ,  140   b ,  140   c  are oriented relative to each other, respectively, based upon an orientation of sidewalls of step  80   a  and oxide step  120   a , such that first spacers and second spacers contact along a sub-lithographic dimension that is relatively insensitive to angles (or variations) formed by sidewalls of step  80   a  and step  120   a.    
     In particular, in the case where step  80   a  is orthogonal to oxide step  120   a  such that the crossing angle B is 90 degrees, and where steps  80   a  and  120   a  are oriented at a tilt angle A of 90 degrees (i.e., not tilted), first spacers  100   a ,  100   b  and second spacers  140   a ,  140   b  contact across a sub-lithographic area of approximately 20 nanometers square. Moreover, in the case where spacer  140   a  is tilted at an angle A of approximately 78 degrees relative to spacer  100   a , it has been determined that spacer  100   a  contacts spacer  140   a  across an area of approximately 19 nanometers square, indicating that an orientation of first spacers  100   a ,  100   b , and  100   c  relative to second spacers  140   a ,  140   b ,  140   c  is insensitive to a variation in sidewall angles for steps  80   a  and  120   a  between approximately 70-110 degrees. In this manner, the contact area between respective ones of first spacers  100   a ,  100   b , and  100   c  and second spacers  140   a ,  140   b ,  140   c  is a sub-lithographic boundary having a dimension of between approximately 18-22 nanometers square, even for relatively large variations in the relative tilt of steps  80   a  and  120   a.    
       FIG. 23  illustrates a perspective view of memory device  160  after subsequent back end processing steps according to one embodiment of the present invention. In particular, memory device  160  illustrated in  FIG. 21  is now illustrated in  FIG. 23  to include a titanium nitride layer  170  disposed over second spacers  140   a ,  140   b ,  140   c . In addition, after appropriate lithographic separation and etch separation steps, an insulating layer  180  is disposed over the titanium nitride layer  170 . Second conductive electrodes  190   a ,  190   b ,  190   c ,  190   d , and  190   e  extend through the titanium nitride layer  170  and the insulating layer  180  to electrically connect memory cells  154  ( FIG. 18 ) of the memory device  160 . In one embodiment, second conductive electrodes  190   a ,  190   b ,  190   c ,  190   d , and  190   e  are tungsten plugs that extend through the titanium nitride layer  170  and the insulating layer  180  to electrically contact second spacers  140   a ,  140   b ,  140   c  of memory cells  154 . However, one with skill in the memory wafer art will recognize that electrodes  190   a - 190   e  can comprise any suitable conductive electrode material, including, but not limited to tungsten and copper. In this regard, a via is defined photolithographically through at least insulating layer  180  and filled with conductive plug material, for example tungsten, to form electrodes  190   a ,  190   b ,  190   c ,  190   d , and  190   e . In one embodiment, conductive vias electrically connect between the memory cells  164  (this connection is not shown for ease of illustration). 
       FIG. 24  illustrates an electronic system  200  according to one embodiment of the present invention. Electronic system  200  includes an electronic device  202  electrically coupled to memory device  160  and a controller  204 . In this regard, controller  204  is configured to address phase change memory cells  164  ( FIG. 21 ) of memory device  160  to access and/or store information. Phase change memory cells  164  store retrievable data that can be accessed, changed, and stored by electronic system  200  through controller  204  that selectively changes a logic state of memory cells  164  by switching memory cells  164  between amorphous and crystalline atomic structures, as described above. 
     Embodiments of the present invention have been described that provide a phase change memory cell formed at a boundary where a first thin film spacer electrically contacts a non-parallel second thin film spacer across a sub-lithographic contact area such that temperature induced changes between logic states of the memory is rapid. In this regard, various embodiments have been described employing large area lithography (i.e., “big block” lithography) that is highly cost effective in a manufacturing setting. To this end, the big block lithography described herein has the potential to reduce mask costs. 
     In addition, the big block exposures described above permit variations in processing dimensions, and this broader process tolerance ultimately has little or no effect on a critical dimension (CD) of the device. That is to say, the patterning need not be exactly centered over the plugs, and as long as the CD variations are smaller than the overlay tolerances, there will be minimal effect on the CD of the device.