Patent Publication Number: US-2023154799-A1

Title: Method for manufacturing semiconductor structure

Description:
PRIORITY CLAIM AND CROSS-REFERENCE 
     This present application is a continuation application of U.S. patent application Ser. No. 17/079,044, filed Oct. 23, 2020, now U.S. Pat. No. 11,551,979, issued Jan. 10, 2023, which is a continuation application of U.S. patent application Ser. No. 14/738,527, filed Jun. 12, 2015, now U.S. Pat. No. 10,818,558, issued Oct. 27, 2020, which claims priority to U.S. Provisional Application Ser. No. 62/152,192, filed Apr. 24, 2015, all of which are herein incorporated by reference in their entireties. 
    
    
     BACKGROUND 
     The present disclosure relates generally to semiconductor devices, and more specifically to fin type field effect transistors (FinFETs). 
     Double-gate metal-oxide-semiconductor field-effect transistors (Double-gate MOSFETs) are MOSFETs that incorporate two gates into a single device. These devices are also known as fin type field effect transistors (FinFETs) due to their structure including a thin “fin” extending from a substrate. The double gate is in that there is a gate on both sides of the channel allowing gate control of the channel from both sides. Furthermore, FinFETs can reduce the short channel effect and provide higher current flow. Other FinFET architectures may include three or more effective gates as well. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. 
         FIG.  1    is a flowchart of a method for manufacturing a semiconductor structure in accordance with some embodiments of the present disclosure. 
         FIGS.  2 - 9    are cross-sectional views of the semiconductor structure at various stages in accordance with some embodiments of the present disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. 
     Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature&#39;s relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated  90  degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. 
       FIG.  1    is a flowchart of a method for manufacturing a semiconductor structure in accordance with some embodiments of the present disclosure.  FIGS.  2 - 9    are cross-sectional views of the semiconductor structure at various stages in accordance with some embodiments of the present disclosure. The method begins with block  10  in which a hard mask layer  110  is formed on a substrate  120  (as shown in  FIG.  2   ). The method continues with block  20  in which trenches  122  are formed in the substrate  120  (as shown in  FIG.  3   ). The method continues with block  30  in which the substrate  120  are hydrogen annealed (as shown in  FIG.  3   ). The method continues with block  40  in which a first liner layer  130  is formed on sidewalls S and bottom surfaces B of the trenches  122  (as shown in  FIG.  4   ). The method continues with block  50  in which a second liner layer  140  is formed on the first liner layer  130  (as shown in  FIG.  5   ). The method continues with block  60  in which a dielectric material  150  overfills the trenches  122  (as shown in  FIG.  6   ). The method continues with block  70  in which the excess dielectric material  150  outside of the trenches  122  is removed (as shown in  FIG.  7   ). The method continues with block  80  in which the hard mask layer  110  is removed (as shown in  FIG.  8   ). The method continues with block  90  in which the dielectric material  150  in the trenches  122  is recessed (as shown in  FIG.  9   ). 
     Reference is made to  FIG.  2   . A hard mask layer  110  is formed on a substrate  120  and has openings  112  therein to define fins which will be formed in the followings steps. The substrate  120  is made of a semiconductor material, such as diamond, silicon (Si), germanium (Ge), silicon carbide (SiC), silicon-germanium (SiGe), or combinations thereof. The substrate  120  is, for example, doped or undoped bulk silicon (Si). Other substrates that may be used include multi-layered substrates, gradient substrates, or hybrid orientation substrates. 
     The hard mask layer  110  is made of a material which can be a barrier against water molecules (H 2 O) and oxygen (O). In some embodiments, the hard mask layer  110  is made of, for example, silicon nitride (Si 3 N 4 ). The hard mask layer  110  has a thickness in a range from about 400 angstroms to about 2000 angstroms. The hard mask layer  110  is formed by, for example, chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), or other deposition processes. 
     The terms “about” may be applied to modify any quantitative representation which could permissibly vary without resulting in a change in the basic function to which it is related. For example, the hard mask layer  110  as disclosed herein having a thickness in a range from about 400 angstroms to about 2000 angstroms may permissibly have a thickness somewhat less than 400 angstroms if its barrier capability is not materially altered. 
     A barrier layer  115  may be formed on the substrate  120  before the hard mask layer  110  is formed. The barrier layer  115  is made of a material which can enhance an adhesion between the hard mask layer  110  and the substrate  120 . In some embodiments, the barrier layer  115  is made of, for example, silicon oxide (SiO 2 ). The barrier layer  115  has a thickness in a range from about 50 angstroms to about 200 angstroms. The barrier layer  115  is formed by, for example, thermal oxidation, chemical vapor deposition (CVD), or other deposition processes. 
     Although  FIG.  2    shows the barrier layer  115  is sandwiched between the hard mask layer  110  and the substrate  120 , the barrier layer  115  could permissibly be omitted. In some embodiments, the hard mask layer  110  can be formed on the substrate  120  in absence of the barrier layer  115  if the adhesion between the hard mask layer  110  and the substrate  120  is at an acceptable level. 
     The hard mask layer  110  and the barrier layer  115  are patterned to form the openings  112  therein to expose portions of the substrate  120  where trenches will be formed in the followings steps. The hard mask layer  110  and the barrier layer  115  are patterned by a photolithography and etching process. The photolithography and etching process includes photoresist application, exposure, developing, etching, and photoresist removal. The photoresist is applied onto the hard mask layer  110  by, for example, spin coating. The photoresist is then prebaked to drive off excess photoresist solvent. After prebaking, the photoresist is exposed to a pattern of intense light. The exposure to light causes a chemical change that allows some of the photoresist soluble in a photographic developer. A post-exposure bake (PEB) may be performed before developing to help reduce standing wave phenomena caused by the destructive and constructive interference patterns of the incident light. The photographic developer is then applied onto the photoresist to remove the some of the photoresist soluble in the photographic developer. The remaining photoresist is then hard-baked to solidify the remaining photoresist. Portions of the hard mask layer  110  and the barrier layer  115  which are not protected by the remaining photoresist are etched to form the openings  112 . The etching of the hard mask layer  110  and the barrier layer  115  may be, for example, reactive-ion etching (RIE). 
     The Reactive-ion etching (RIE) is a type of dry etching which has different characteristics than wet etching. Reactive-ion etching (RIE) uses chemically reactive plasma to form the openings  112 . The plasma is generated under low pressure (vacuum) by an electromagnetic field. High-energy ions from the chemically reactive plasma attack the hard mask layer  110  and the barrier layer  115  and react with them. In some embodiments, fluorocarbon or hydrofluorocarbon based reactive-ion etching (RIE) can be used to form the openings  112 . 
     After etching the hard mask layer  110  and the barrier layer  115 , the photoresist is removed from the hard mask layer  110  by, for example, plasma ashing or stripping. Plasma ashing uses a plasma source to generate a monatomic reactive species, such as oxygen or fluorine. The reactive species combines with the photoresist to form ash which is removed with a vacuum pump. Stripping uses a photoresist stripper, such as acetone or a phenol solvent, to remove the photoresist from the hard mask layer  110 . 
     A cleaning process may be performed to remove a native oxide of the substrate  120  after the hard mask layer  110  and the barrier layer  115  are patterned. In some embodiments, the native oxide of the substrate  120  can be removed by hydrofluoric acid (HF) when the substrate  120  is made of silicon (Si). The cleaning process is optional. In some embodiments, the cleaning process can be omitted if the native oxide of the substrate  120  is at an acceptable level. 
     Reference is made to  FIG.  3   . Trenches  122  are formed in the substrate  120 . The trenches  122  define the fins  124 . That is, the trenches  122  separate the fins  124  from one another. The exposed portions of the substrate  120  through the openings  112  are removed by an etching process, such as reactive-ion etching (RIE), in order to form the trenches  122  in the substrate  120 . 
     In some embodiments, chlorine (Cl) or bromine (Br) based reactive-ion etching (RIE) can be used to form the trenches  122 . At least one of the trenches  122  has a depth in a range from about 0.3 μm to about 0.5 μm. At least one of the trenches  122  has at least one sidewall S, a bottom surface B, and a taper angle a between the sidewall S and a plane extending from the bottom surface B. The taper angle a of the trench  122  is in a range from about 78° to about 88°. 
     After the formation of the fins  124 , the fins  124  and the substrate  120  are hydrogen annealed to smooth the sidewalls S and the bottom surfaces B of the trenches  122 . That is, the fins  124  and substrate  120  are annealed in an atmosphere including a hydrogen containing gas. The hydrogen containing gas includes, for example, steam (H 2 O), ammonia (NH 3 ), or combinations thereof. In some embodiments, a temperature for the hydrogen containing gas annealing is in a range from about 500 degrees Celsius to about 1100 degrees Celsius. If the temperature for the hydrogen containing gas annealing is lower than about 500 degrees Celsius, then the hydrogen containing gas annealing may not smooth the sidewalls S and the bottom surfaces B of the trenches  122 . If the temperature for the hydrogen containing gas annealing is higher than about 1100 degrees Celsius, then the hydrogen containing gas annealing may significantly increase the thermal budget of the semiconductor structure fabrication. In some embodiments, the temperature for the hydrogen containing gas annealing is in a range from about 790 degrees Celsius to about 950 degrees Celsius. A partial pressure for the hydrogen is in a range from about 1 torr to about 900 torr. 
     The terms “about” may be applied to modify any quantitative representation which could permissibly vary without resulting in a change in the basic function to which it is related. For example, the temperature for the hydrogen containing gas annealing as disclosed herein in a range from about 500 degrees Celsius to about 1100 degrees Celsius may permissibly be somewhat lower than 500 degrees Celsius if its smoothing capability is not materially altered. 
     The hydrogen containing gas annealing transforms at least one portion of the sidewalls S and the bottom surfaces B of the trenches  122  into a hydrogen-terminated surface. The hydrogen-terminated surface has at least one dangling bond terminated with at least one hydrogen atom. When the substrate  120  and/or the fins  124  are made of silicon (Si), the hydrogen-terminated surface has at least one silicon to hydrogen (Si—H) bond. 
     The hydrogen containing gas annealing can repair structural damage incurred in the substrate  120  and/or the fins  124  by the etching process for forming the trenches  122  and thus smooth the sidewalls S and the bottom surfaces B of the trenches  122 . If the sidewalls S and the bottom surfaces B of the trenches  122  are rough, corners or tips created by the rough surfaces may act as stress concentrators within the fins  124  causing them to crack. In some embodiments, since the sidewalls S and the bottom surfaces B of the trenches  122  are smoothed by the hydrogen containing gas annealing, when a bending force is applied on the fins  124 , the force is evenly distributed over the fins  124 , and thus cracks can be prevented from initiating and growing. In some embodiments, the sidewalls S and the bottom surfaces B of the trenches  122  may be smooth to an atomic level when the substrate  120  and/or the fins  124  are made of silicon (Si). 
     Reference is made to  FIG.  4   . A first liner layer  130  is formed on the sidewalls S and the bottom surfaces B of the trenches  122 . In some embodiments, the first liner layer  130  is made of, for example, silicon oxide (SiO 2 ). The first liner layer  130  has a thickness in a range from about 5 angstroms to about 100 angstroms. The first liner layer  130  may be formed by, for example, thermal oxidation with in-situ generated steam (ISSG). In some embodiments, a temperature for the formation of the first liner layer  130  is in a rage from about 800 degrees Celsius to about 1200 degrees Celsius. 
     Although  FIG.  4    shows the first liner layer  130  is formed on the sidewalls S and the bottom surfaces B of the trenches  122 , the first liner layer  130  could permissibly be omitted. In some embodiments, a dielectric material can be formed in the trenches  122  in absence of the first liner layer  130  if the structural damage incurred in the substrate  120  and/or the fins  124  are acceptable. 
     After the formation of the first liner layer  130 , the substrate  120  and the fins  124  are annealed to further repair the structural damage incurred in the substrate  120  and/or the fins  124  by the etching process for forming the trenches  122 . In some embodiments, the substrate  120  and the fins  124  are annealed in an oxygen-free environment. In some embodiments, a temperature for annealing the substrate  120  and the fins  124  is in a range from about 900 degrees Celsius to about 1200 degrees Celsius. In some embodiments, a process time for annealing the substrate  120  and the fins  124  is in a range about 15 minutes to about 60 minutes. This annealing process is optional. In some embodiments, the annealing process can be omitted if the structural damage incurred in the substrate  120  and/or the fins  124  are acceptable. 
     Reference is made to  FIG.  5   . A second liner layer  140  is formed on the first liner layer  130 . In some embodiments, the second liner layer  140  is made of, for example, silicon oxide (SiO 2 ). The second liner layer  140  has a thickness in a range from about 10 angstroms to about 100 angstroms. The second liner layer  130  may be formed by, for example, chemical vapor deposition (CVD) or, more specifically, plasma enhanced atomic layer deposition (PEALD). 
     Although  FIG.  5    shows the second liner layer  140  is formed on the first liner layer  130 , the second liner layer  140  could permissibly be omitted. In some embodiments, a dielectric material can be formed in the trenches  122  in absence of the second liner layer  140  if the structural damage incurred in the substrate  120  and/or the fins  124  are acceptable. 
     Reference is made to  FIG.  6   . A dielectric material  150  overfills the trenches  122 . The dielectric material  150  includes, for example, silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), silicon oxynitride (SiO x N y ), or combinations thereof. In some embodiments, the dielectric material  150  is formed by, for example, chemical vapor deposition (CVD). In some other embodiments, the dielectric material  150  includes a flowable dielectric material to improve trench fill capability. The flowable dielectric material includes, for example, hydrogen sisesquioxane (HSQ), poly-arylene ethers (PAE), porous silicon oxide (i.e. the xerogel or the aerogel), methyl silsesquioxane (MSQ), methyl silsesquioxane (MSQ)/hydrogen sisesquioxane (HSQ), perhydrosilazane (TCPS), perhydro-polysilazane (PSZ), silicate, siloxane, or combinations thereof. The flowable dielectric material is formed by, for example, spin coating. 
     Then, a curing process is performed on the flowable dielectric material. In the curing process, the flowable dielectric material is baked to drive off excess solvent and to cure the flowable dielectric material. In some embodiments, a temperature for the curing process is in a range from about 150 degrees Celsius to about 500 degrees Celsius. 
     Reference is made to  FIG.  7   . The excess dielectric material  150  outside of the trenches  122  is removed through a removal process. In some embodiments, the dielectric material  150  over burden is removed by a chemical mechanical polishing (CMP) process. In some embodiments, a combination of a plasma etch-back followed by the chemical mechanical polishing (CMP) process is used. The hard mask layer  110  acts as a polish stop layer to protect the underlying fins  124  from chemical mechanical polishing (CMP) damage. 
     Reference is made to  FIG.  8   . The hard mask layer  110  is removed by an etching process, such as a wet etching process. In some embodiments, the hard mask layer  110  can be removed by hot phosphoric acid (H 3 PO 4 ) when the hard mask layer  110  is made of silicon nitride (Si 3 N 4 ). 
     Reference is made to  FIG.  9   . The dielectric material  150  in the trenches  122  is recessed. That is, an upper portion of the dielectric material  150  in the trenches  122  is removed. The recessing of the dielectric material  150  may be performed by, for example, a wet etching process. In some embodiments, the dielectric material  150  can be recessed by hydrofluoric acid (HF) when the dielectric material  150  is made of silicon oxide (SiO 2 ). 
     At least one of the sidewalls S of the trenches  122  is separated into an upper portion US and a buried portion BS. In the recessing of the dielectric material  150 , the first liner layer  130 , the second liner layer  140 , and the dielectric material  150  on the upper portions US of the sidewalls S of the trenches  122  are removed. Furthermore, the barrier layer  115  may be removed in the recessing of the dielectric material  150  as well when the barrier layer  115 , the first liner layer  130 , the second liner layer  140 , and the dielectric material  150  are made of substantially the same material, such as silicon oxide (SiO 2 ). Therefore, after the recessing of the dielectric material  150 , the upper portions US of the sidewalls S of the trenches  122  are exposed from the first liner layer  130 , the second liner layer  140 , and the dielectric material  150  while the buried portions BS of the sidewalls S of the trenches  122  are covered by the first liner layer  130 , the second liner layer  140 , and/or the dielectric material  150 . 
     Since the fins  124  and substrate  120  are hydrogen containing gas annealed before the formations of the first liner layer  130 , an interface between the first liner layer  130  and an combination of the fins  124  and substrate  120  are hydrogen-terminated. That is, the interface between the first liner layer  130  and the combination of the fins  124  and substrate  120  has at least one dangling bond terminated with at least one hydrogen atom. When the fins  124  and substrate  120  are made of silicon (Si), the interface between the first liner layer  130  and the combination of the fins  124  and substrate  120  has at least one silicon to hydrogen (Si—H) bond. Furthermore, when the fins  124  and substrate  120  are made of silicon (Si), the interface between the first liner layer  130  and the combination of the fins  124  and substrate  120  may be smooth to the atom level. 
     In  FIG.  9   , at least one of the buried portions BS of the sidewalls S and the bottom surfaces  150  of the trenches  122  is a hydrogen-terminated surface. That is, at least one of the buried portions BS of the sidewalls S of the trenches  122  has at least one dangling bond terminated with at least one hydrogen atom, and/or at least one of the bottom surfaces B of the trenches  122  has at least one dangling bond terminated with at least one hydrogen atom. When the fins  124  and/or substrate  120  are made of silicon (Si), at least one of the buried portions BS of the sidewalls S of the trenches  122  has at least one silicon to hydrogen (Si—H) bond, and/or at least one of the bottom surfaces B of the trenches  122  has at least one silicon to hydrogen (Si—H) bond. Furthermore, when the fins  124  and/or substrate  120  are made of silicon (Si), at least one of the buried portions BS of the sidewalls S of the trenches  122  may be smooth to the atom level, and/or at least one of the bottom surfaces B of the trenches  122  may be smooth to the atom level. 
     In  FIG.  9   , at least one of the upper portions US of the sidewalls S of the trenches  122  may be a hydrogen-terminated surface. That is, at least one of the upper portions US of the sidewalls S of the trenches  122  may have at least one dangling bond terminated with at least one hydrogen atom. When the fins  124  are made of silicon (Si), at least one of the upper portions US of the sidewalls S of the trenches  122  may have at least one silicon to hydrogen (Si—H) bond. Furthermore, when the fins  124  are made of silicon (Si), at least one of the upper portions US of the sidewalls S of the trenches  122  may be smooth to the atom level. 
     In some embodiments, the removals of the hard mask layer  110  and the barrier layer  115  may be performed after the recessing of the dielectric material  150 . That is, the first liner layer  130 , the second liner layer  140 , and the dielectric material  150  on the upper portions US of the sidewalls S of the trenches  122  are removed first, and then the hard mask layer  110  and the barrier layer  115  are removed. 
     It is understood that for the embodiments shown above, additional steps may be performed to complete the fabrication of a fin type field effect transistor device (FinFET device). For example, these additional steps may include formation of gate dielectrics, formation of gates, formation of source and drain regions, formation of contacts, formation of interconnect structures (e.g., lines and vias, metal layers, and interlayer dielectric that provide electrical interconnection to the FinFET device), formation of passivation layers, and packaging of the FinFET device. 
     In order to repair structural damage incurred in the fins  124  by the etching process for forming the trenches  122 , a hydrogen containing gas annealing process is performed on the fins  124 . The hydrogen containing gas annealing process can smooth the sidewalls S and the bottom surfaces B of the trenches  122 . Since the sidewalls S and the bottom surfaces B of the trenches  122  are smoothed by the hydrogen containing gas annealing process, when a bending force is applied on the fins  124 , the force is evenly distributed over the fins  124 , and thus cracks can be prevented from initiating and growing. 
     According to some embodiments, a method includes forming patterned masks over a semiconductor substrate; etching the semiconductor substrate using the patterned masks as an etch mask to form semiconductor fins with a trench between the semiconductor fins; performing an annealing process using a hydrogen containing gas to smooth surfaces of the semiconductor fins; after performing the annealing process, selectively forming a first liner on the smoothed surfaces of the semiconductor fins, while leaving surfaces of the patterned masks exposed by the first liner; filling the trench with a dielectric material; and etching back the first liner and the dielectric material to form an isolation structure between the semiconductor fins. 
     According to some embodiments, a method includes forming patterned masks over a semiconductor substrate; etching the semiconductor substrate using the patterned masks as an etch mask to form semiconductor fins with a trench between the semiconductor fins; forming a first liner on exposed surfaces of the semiconductor fins and the substrate; forming a second liner over the first liner, wherein the surfaces of the patterned masks are exposed by the first and second liners; filling the trench with a dielectric material; and etching back the first liner, the second liner, and the dielectric material to form an isolation structure between the semiconductor fins. 
     According to some embodiments, a method includes forming patterned masks over a semiconductor substrate; etching the semiconductor substrate using the patterned masks as an etch mask to form semiconductor fins with a trench between the semiconductor fins; forming a first liner on exposed surfaces of the semiconductor fins and the substrate; after forming the first liner, performing a first annealing process in an oxygen-free environment; after performing the first annealing process, forming a second liner over the first liner; filling the trench with a dielectric material; and etching back the first liner, the second liner, and the dielectric material to form an isolation structure between the semiconductor fins. 
     The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.