Patent Publication Number: US-RE36191-E

Title: Configuration data loopback in a bus bridge circuit

Description:
This is a continuation of U.S. application Ser. No. 07/894,108 filed Jun. 5, 1992, now abandoned. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates to the field of computer system architecture. More particularly, this invention relates to accessing configuration registers in a bus bridge circuit. 
     2. Background 
     In a computer system, peripheral components, such as disk drive controllers, network controllers, and graphics controllers, may be coupled to peripheral component buses separate from a host, or CPU bus. There are several reasons a system might employ peripheral component buses. For example, it may be desirable to isolate slower speed devices from higher bandwidth buses and peripherals. Also, an intelligent peripheral component may have a local peripheral component bus. Moreover, the system may have more peripheral components than can be reliably placed on the host bus, due to electrical loading effects. 
     In such a system, a host bridge circuit enables communication between the peripheral component bus and the host bus. The host bridge circuit enables an access request that initiates on the host bus to have a destination on the peripheral component bus, and enables an access request that initiates on the peripheral component bus to have a destination on the host bus. The host bridge circuit can also enable access to a shared resource from both buses. Typically, the host bridge circuit contains a set of configuration registers that define parameters for processing access cycles between the buses, and for controlling the shared resource. System I/O software performs reads and writes to the configuration registers in order to define the parameters. 
     However, integrated circuit subsystems in the host bridge circuit require enough signal lines to communicate address, data, and control information for both the host bus and the peripheral component bus. The resulting large packages sizes of the integrated circuit devices greatly increases the system cost. Moreover, the host bridge devices must process memory accesses to the shared resource as well as I/O access of configuration registers, which increases the complexity of logic implemented in the host bridge devices. 
     As will be described, the present method and apparatus reduces cost and complexity of devices for a bus bridge circuit by dividing address and data paths between separate devices to reduce pin count, and by looping back &#34;bridged&#34; configuration data to access configuration registers. 
     SUMMARY OF THE INVENTION 
     A method and apparatus is disclosed for reducing cost and complexity of devices in a bus bridge circuit by dividing address and data paths between separate devices to reduce pin count, and by looping back &#34;bridged&#34; configuration data to access configuration registers. The bridge circuit is comprised primarily of two integrated circuit devices: a cache DRAM controller (CDC), and a data path unit (DPU). 
     The host bridge circuit &#34;bridges&#34; all I/O accesses received over a host bus directly to a peripheral component bus without the need for any address decoding. The CDC receives addresses for I/O accesses over an address portion of the host bus, and the DPU receives corresponding data for the I/O accesses over a data portion of the host bus. The CDC also receives control signals over the host bus indicating an I/O access cycle. 
     To bridge I/O access cycles, the host bridge circuit translates the host bus I/O access cycles into I/O access cycles for the peripheral component bus. The CDC generates an I/O access cycle on the peripheral component bus by assuming the role of bus initiator on the peripheral component bus, generating control signals indicating an I/O access cycle, and transferring the address received over the address portion of the host bus to the peripheral component bus. The CDC also generates control signals, which cause the DPU to transfer data received over the data portion of the host bus to the peripheral component bus. 
     To loop back configuration data, the host bridge circuit &#34;bridges&#34; the host bus I/O access cycles targeted for the configuration registers of the CDC. The CDC bus initiator on the peripheral component bus initiates and drives the I/O access cycle targeted for the configuration registers. However, the CDC also monitors the peripheral component bus as a bus target. The CDC decodes the control signals on the peripheral component bus indicating an I/O access, and decodes the address transmitted on the peripheral component bus. If the address corresponds to a configuration register, the CDC receives the data as a target on the peripheral component bus. Thus, for I/O access cycles generated by the host bridge circuit and targeted for a configuration register, the CDC is both initiator and target for the peripheral component bus I/O access cycle. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 illustrates an example computer system employing the teachings of the present invention, including a hierarchical arrangement of buses comprising a host bus, a host bridge circuit, a peripheral component bus, and an ISA bus. 
     FIG. 2 is a more detailed illustration of the host bridge circuit, which is comprised primarily of two integrated circuit devices: a cache DRAM controller (CDC), and a data path unit (DPU). 
     FIG. 3 shows the coupling of the host bridge circuit to the host bus and the memory bus, and shows the bus signals implemented on the peripheral component bus. 
     FIG. 4 illustrates the timing of an I/O write cycle targeted for a configuration register of the CDC. The I/O write cycle originates on the host bus and is looped back over the peripheral component bus to the CDC. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     A method and apparatus is disclosed for reducing cost and complexity of devices in a bus bridge circuit by dividing address and data paths between separate devices to reduce pin count, and by looping back &#34;bridged&#34; configuration data to access configuration registers. In the following description, for purposes of explanation, specific circuit devices, circuit architectures and components are set forth in order to provide a more thorough understanding of the present invention. However, it will be apparent to one skilled in the art that the present invention may be practiced without these specific details. In other instances, well known circuits and devices are shown in schematic form in order not to obscure the present invention unnecessarily. 
     Referring now to FIG. 1, an example computer system employing the teachings of the present invention is illustrated. A CPU 15 and a cache subsystem 16 are shown coupled for communication over a host bus 18. In the current embodiment, the host bus 18 provides a 32 bit memory address space and a 16 bit I/O address space. 
     A host bridge circuit 30 enables communication between bus agents coupled to the host bus 18, and bus agents coupled to a peripheral component bus 19. An ISA bridge circuit 35 enables communication between bus agents coupled to the peripheral component bus 19, and bus agents coupled to an ISA bus 20. 
     Peripheral components 40-42 are bus agents coupled for communication over the peripheral component bus 19. In addition, the host bridge circuit 30 and the ISA bridge circuit 35 are coupled as bus agents for communication over the peripheral component bus 19. The host bridge circuit 30 and the ISA bridge circuit 35 have the capability to be initiators and targets for access cycles over the peripheral component bus 19. 
     In the current embodiment, the peripheral component bus 19 comprises 32 bit memory address and 32 bit I/O address spaces, with the addresses and data multiplexed over the same bus lines. For further discussion of a peripheral component bus consistent with the teachings of the present invention, refer to related U.S application Ser. No. 07/876,577, filed on Apr. 30, 1992, entitled A Signalling Protocol for a Peripheral Component Interconnect, and incorporated fully herein by reference. 
     Bridge circuits, such as the host bridge circuit 30 and the ISA bridge circuit 35, are each coupled to a primary bus and a secondary bus. A bridge circuit enables an access request that initiates on the primary bus to have a destination on the secondary bus, and enables an access request that initiates on the secondary bus to have a destination on the primary bus. 
     For example, the host bridge circuit 30 receives access requests over the host bus 18, and initiates peripheral component bus 19 access requests to communicate with the peripheral components 40-42, and bus agents on the ISA bus 20 through the ISA bridge circuit 35. Also, the host bridge circuit 30 receives access requests over the peripheral component bus 19, and initiates host bus 18 access requests to communicate over the host bus 18. 
     Similarly, the ISA bridge circuit 35 receives access requests over the ISA bus 20, and initiates peripheral component bus 19 access requests to communicate with the peripheral components 40-42, and the host bridge circuit 30. Also, the ISA bridge circuit 35 receives access requests over the peripheral component bus 19, and initiates ISA bus 20 access requests to communicate over the ISA bus 20. 
     In the current embodiment, the host bridge circuit 30 enables access to a shared DRAM subsystem 36. The host bridge circuit 30 receives access requests for the DRAM subsystem 36 over the host bus 18, and the peripheral component bus 19. Bus initiators coupled to the peripheral component bus 19 access the DRAM subsystem 36 by initiating an access cycle on the peripheral component bus 19, and by broadcasting an address within a range of addresses allocated to the DRAM subsystem 36. The peripheral components 40-42, and the ISA bridge circuit 35 can each assume the role of bus initiator and access the DRAM subsystem 36 over the peripheral component bus 19, through the host bridge circuit 30. 
     FIG. 2 is a more detailed illustration of the host bridge circuit 30, which is comprised primarily of two integrated circuit devices: a cache DRAM controller (CDC) 41, and a data path unit (DPU) 42. To reduce the number of pins for the CDC 41 and the DPU 42, the address and data paths of the host bus 18 are divided. The CDC 41 is coupled to transfer addresses for memory and I/O accesses over the address portion of the host bus 18, and the DPU 42 is coupled to transfer data for memory and I/O access over the data portion of the host bus 18. The CDC 41 is also coupled to transfer control signals over a control portion (not shown) of the host bus 18. 
     Moreover, the CDC 41 is a full function initiator and target on she peripheral component bus 19. The CDC 41 is coupled to transfer addresses, data and control signals for memory and I/O accesses over the peripheral component bus 19. The DPU 42 is coupled to transfer data for memory and I/O accesses over the peripheral component bus 19. 
     When the host bridge circuit 30 is the initiator for a bus cycle over the peripheral component bus 19, the DPU 42 drives out the data during the data phase of the bus cycle. The DPU 42 also receives data during the data phase of bus cycles over the peripheral component bus 19 when the host bridge circuit 30 is the target for the bus cycle. However, the CDC 41 receives data during the data phase of bus cycles over the peripheral component bus 19 for internal configuration of the CDC 41. 
     The CDC 41 is a memory controller for the DRAM subsystem 36, and a cache controller for the cache subsystem 16. The DPU 42 switches data flow through the host bridge circuit 30 according to control signals 51 received from the CDC 41. 
     The CDC 41 contains a set of configuration registers which define parameters for host bridge circuit 30 functions. For example, in the current embodiment, the CDC 41 contains registers defining a memory address mapping for the DRAM subsystems 36 and the cache subsystem 16, as well as control parameter information for the DRAM and cache controller of the CDC 41. The CDC 41 also contains registers for controlling the bandwidth of burst accesses of the DRAM subsystem 36 over the peripheral component bus 19. 
     The CDC 41 and the DPU 42 enable dual port access to the DRAM subsystem 36 from the host bus 18 and the peripheral component bus 19. To access the DRAM subsystem 36 over the host bus 18, the CPU 15, or another bus initiator coupled to the host bus 18, broadcasts a memory address over the address portion of the host bus 18 within the range of memory address mapped to the DRAM subsystem 36. The CDC 41 receives the memory addresses over the address portion of the host bus 18. If the memory addresses are allocated to the DRAM subsystem 36, the CDC 41 issues control signals 51, which cause the DPU 42 to transfer data between the data portion of the host bus 18 and the DRAM subsystem 36. 
     If the control signals on the control bus of the host bus 18 indicated a read memory cycle, then the control signals 51 cause the DPU 42 to read data from the DRAM subsystem 36 over the memory bus 22, and transfer the data over the data portion of the host bus 18. On the other hand, if the control signals on the control bus of the host bus 18 indicated a write memory cycle, then the control signals 51 cause the DPU 42 to transfer data from the data portion of the host bus 18 to the DRAM subsystem 36. 
     Similarly, bus initiators coupled to the peripheral component bus 19 access the DRAM subsystem 36 by initiating a memory access cycle on the peripheral component bus 19, and by broadcasting an address within a range of addresses mapped to the DRAM subsystem 36. The CDC 41 receives the memory addresses over a multiplexed address/data portion (AD) of the peripheral component bus 19. The AD portion of the peripheral component bus 19 has an address phase and a data phase. If the memory address broadcast in the address phase is allocated to the DRAM subsystem 36, the CDC 41 issues control signals 51, which cause the DPU 42 to transfer data between the DRAM subsystem 36 and the AD portion of the peripheral component bus 19 during the data phases. 
     During a memory read cycle on the peripheral component bus 19, the control signals 51 cause the DPU 42 to read data from the DRAM subsystem 36 over the memory bus 22, and transfer the data over the peripheral component bus 19 during the data phase. During a write memory cycle on the peripheral component bus 19, the control signals 51 cause the DPU 42 to transfer data from the AD portion of the peripheral component bus 19 during the data phase to the DRAM subsystem 36. 
     To reduce the complexity of logic implemented in the CDC 41 and the DPU 42, the host bridge circuit 30 &#34;bridges&#34; all I/O accesses received over the host bus 18 directly to the peripheral component bus 19 without any address decoding. The host bridge circuit 30 translates the host bus 18 I/O accesses into I/O accesses for the peripheral component bus 19. 
     To translate I/O accesses, the CDC 41 receives the addresses for I/O accesses over the address portion of the host bus 18, and the DPU 42 receives the corresponding data for the I/O accesses over the data portion of the host bus 18. The CDC 41 also receives control signals over the host bus 18 indicating an I/O access cycle. 
     The host bridge circuit 30 generates corresponding I/O access cycles over the peripheral component bus 19. To generate an I/O access cycle on the peripheral component bus 19, the CDC 41 assumes the role of bus initiator on the peripheral component bus 19, generates control signals indicating an I/O access cycle on the peripheral component bus 19, and transfers the addresses for I/O accesses received over the address portion of the host bus 18 to the multiplexed AD portion of the peripheral component bus 19 during the address phase. Also, the CDC 41 generates control signals 51, which causes the DPU 42 to transfer data corresponding to the I/O accesses received over the data portion of the host bus 18 to the multiplexed AD portion of the peripheral component bus 19 during the data phase. 
     In the current embodiment, system I/O software executed by the CPU 15 controls the host bridge 30 functions by programming the configuration registers of the CDC 41. In the current embodiment, the configuration registers of the CDC 41 are mapped to the I/O address space of the host bus 18. For example, the system I/O software allocates an address mapping for the DRAM subsystem 36 by programming the appropriate configuration registers in the CDC 41 using I/O write cycles over the host bus 18. 
     To loop back configuration data, the host bridge circuit 30 &#34;bridges&#34; the host bus 18 I/O access cycles targeted for the configuration registers of the CDC 41 to the peripheral component bus 19 as corresponding I/O access cycles. The CDC 41 bus initiator on the peripheral component bus 19 initiates and drives the I/O access cycle targeted for the configuration registers. However, the CDC 41 also monitors the peripheral component bus 19 as a bus target. The CDC 41 decodes the control signals on the peripheral component bus 19 indicating an I/O access or configuration space access, and decodes the address transmitted on the AD portion of the peripheral component bus 19 during the address phase. If the address corresponds to a configuration register of the CDC 41, then the CDC 41 receives the data as a target on the peripheral component bus 19. Thus, for I/O access cycles generated by the host bridge circuit 30 and targeted for a configuration register of the CDC 41, the CDC 41 is both initiator and target for the peripheral component bus 19 I/O access cycle. 
     FIG. 3 shows the coupling of the host bridge circuit 30 to the host bus 18 and the memory bus 22, and shows the bus signals implemented on the peripheral component bus 19. Bus signals 110 comprise the peripheral component bus 19. Addresses and data are multiplexed over the 32 AD bus lines. The C/BE bus lines indicate bus command and byte enable information. Basic control information is transferred over a FRAME#, a TRDY#, an IRDY#, a STOP#, and a LOCK# bus signal. Bus arbitration and selection functions are provided by a REQ#, a GNT#, an IDSEL# and a DEVSEL# bus signal. Synchronization is provided by a CLK bus signal. For a detailed description of these bus signals refer to related U.S. application Ser. No. 07/876,577, filed on Apr. 30, 1992, entitled A Signalling Protocol for a Peripheral Component Interconnect. 
     FIG. 4 illustrates the timing of an I/O write cycle targeted for a configuration register of the CDC 41. The I/O write cycle originates on the host bus 18 and is looped back over the peripheral component bus 19 to the CDC 41. In the current embodiment, I/O access cycles targeted for the configuration registers of the CDC 41 are generated by system I/O software executed by the CPU 15. The host bridge circuit 30 translates the I/O write cycle on the host bus 18 into an I/O access or configuration space access cycle on the peripheral component bus 19, and the host bridge circuit 30 loops back the cycle on the peripheral component bus 19 into the appropriate configuration register of the CDC 41. 
     The I/O write cycle on the host bus 18 begins between times 1 and 2 when the CPU 15 transmits an address (ADDR) corresponding to an internal configuration register of the CDC 41, over the address portion of the host bus 18. Between times 2 and 3, the CPU 15 asserts an address strobe signal (ADS) indicating that a valid address is being transmitted over the address portion of the host bus 18. The CPU 15 also asserts control signals (not shown) over the host bus 18 indicating an I/O write cycle. 
     Thereafter, between times 3 and 4, the CPU 15 transmits the data (DATA) for the I/O write cycle over the data portion of the host bus 18. The CDC 41 translates the I/O write cycle on the host bus 18 into an I/O write cycle on the peripheral component bus 19 by first asserting the FRAME# signal to indicate the start of an access cycle on the peripheral component bus 19. The CDC 41 signals an I/O write cycle over the C/BE# signal lines of the peripheral component bus 19. Also between times 3 and 4, the CDC 41 transfers the address received over the address portion of the host bus 18 to the AD portion of the peripheral component bus 19 during the address phase. 
     The CDC 41 asserts the IRDY#signal between times 4 and 5, and the TRDY#signal between times 5 and 6 to signal both &#34;initiator ready to send&#34; and &#34;target ready to receive&#34; during the data phase portion of the peripheral component bus 19. Also between times 5 and 6, the CDC 41 issues control signals 51, which causes the DPU 42 to transfer the data received over the data portion of the host bus 18 to the AD portion of the peripheral component bus 19 during the data phase. The CDC 41 then transfers the data from the AD portion of the peripheral component bus 19 to the appropriate configuration register. Also between times 5 and 6, the CDC 41 asserts an RDY signal on the control portion of the host bus 18 to signal the CPU 15 that data for the I/O write cycle has been accepted. 
     In the foregoing specification, the invention has been described with reference to specific exemplary embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention as set forth in the independent claims. The specification and drawings are accordingly to be regarded as an illustrative, rather than in a restrictive sense.