Patent Publication Number: US-2023163778-A1

Title: Analog digital converter and method for analog to digital converting in the analog digital converter

Description:
This U.S. non-provisional patent application claims priority under 35 U.S.C. 119 to Korean Patent Application No. 10-2021-0164213 filed on Nov. 25, 2021, and Korean Patent Application No. 10-2022-0021205 filed on Feb. 18, 2022 in the Korean Intellectual Property Office, the disclosures of which are incorporated by reference in their entirety herein. 
     1. TECHNICAL FIELD 
     The present disclosure relates to an analog-to-digital converter and a method for analog-to-digital conversion of an analog-to-digital converter. 
     2. DISCUSSION OF RELATED ART 
     Analog signals can be continuous and provide a large number of different voltage or current values. However, digital circuits that process data may operate on binary signals that have two discrete states such as a logic “1” (HIGH) or a logic “0” (LOW). Accordingly, an electronic circuit is needed to convert between the two different domains of continuously changing analog signals and discrete digital signals. An analog-to-digital converter (ADC) may be used to generate a sequence of digital code representing signal levels of an analog signal. 
     A successive-approximation-register (SAR) analog-to-digital converter (ADC) is a type of analog-to-digital converter that converts a continuous analog waveform into a discrete digital representation (i.e., the sequence of digital code) using a binary search through all possible quantization levels before finally conversing upon a digital output for each conversion. 
     However, the SAR ADC consumes a great deal of power in the process of converting a signal. 
     SUMMARY 
     An object of the present disclosure is to provide an analog-to-digital converter with reduced operational power consumption. 
     An object of the present disclosure is to provide an analog-to-digital conversion method of an analog-to-digital converter with reduced operational power consumption. 
     According to an embodiment of the present disclosure, an analog-to-digital converter includes a comparator, a control logic, and a reference voltage adjustment circuit. The comparator includes a first input node receiving an output of a plurality of first unit capacitors and a second input node receiving an output of a plurality of second unit capacitors. The control logic is configured to output first and second control signals on the basis of an output signal of the comparator. The reference voltage adjustment circuit configured is to adjust an output voltage provided to the comparator on the basis of the first and second control signals. The reference voltage adjustment circuit includes a first pull-up circuit configured to apply a first reference voltage to each of the plurality of first unit capacitors and a first pull-down circuit configured to apply a second reference voltage to each of the plurality of second unit capacitors, based on the first and second controls signals. 
     According to an embodiment of the present disclosure, there is provided an analog-to-digital converter including a first capacitor array, a second capacitor array, and control logic. The first capacitor array includes a plurality of thermometer code-based first unit capacitors used to determine upper bits of a digital output signal corresponding to an analog input signal. The second capacitor array includes a plurality of binary-weighted second unit capacitors used to determine lower bits of the digital output signal. The control logic is configured to receive a reference voltage from the first and second capacitor arrays and output first and second control signals. The first and second capacitor arrays include first and second operation switches configured to apply first and second reference voltages on the basis of the first and second control signals, respectively. 
     According to an embodiment of the present disclosure, there is provided a method of performing analog-to-digital conversion using an analog-to-digital converter including a comparator including a plurality of nodes to which outputs of a plurality of first unit capacitors and outputs of a plurality of second unit capacitors are connected, a control logic, and a pull-up circuit and a pull-down circuit. The method includes: the control logic outputting first and second control signals on the basis of an output signal of the comparator; and adjusting by the pull-up circuit and the pull-down circuit a reference voltage applied to the plurality of first unit capacitors and the plurality of second unit capacitors on the basis of the first and second control signals. The adjusting includes the pull-up circuit applying a first reference voltage to each of the plurality of first unit capacitors, and the pull-down circuit applying a second reference voltage to each of the plurality of second unit capacitors that is different from the first reference voltage. 
     The technical objects of the present disclosure are not limited to those described above, and other objects that are not described herein will be apparently understood by those skilled in the art from the following description. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The above and other aspects and features of the present disclosure will become more apparent by describing exemplary embodiments thereof in detail with reference to the attached drawings, in which: 
         FIG.  1    is a block diagram of a semiconductor device according to an example embodiment of the inventive concept; 
         FIG.  2    is an exemplary circuit diagram of a pull-up circuit included in the reference voltage adjustment circuit of  FIG.  1    according to an example embodiment of the inventive concept; 
         FIG.  3    is an exemplary circuit diagram of a pull-down circuit included in the reference voltage adjustment circuit of  FIG.  1    according to an example embodiment of the inventive concept; 
         FIG.  4    is a diagram illustrating an operation in a sampling phase of the reference voltage adjustment circuit of  FIG.  1    according to an example embodiment of the inventive concept; 
         FIG.  5    is a diagram illustrating an operation in a conversion phase of the reference voltage adjustment circuit of  FIG.  1    according to an example embodiment of the inventive concept; 
         FIG.  6    is a diagram for describing an effect of a semiconductor device according to some embodiments. 
     
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
     Hereinafter, embodiments according to the technical spirit of the present disclosure will be described below with reference to the accompanying drawings. 
       FIG.  1    is a block diagram of a semiconductor device according to some embodiments. 
     Referring to  FIG.  1   , a semiconductor device  1  may include a successive-approximation-register digital-to-analog converter (SAR DAC)  100 , a reference voltage generator  200 , a comparator  300  (e.g., a comparison circuit), a first SAR logic  410  (e.g., a first logic circuit), a second SAR logic  420  (e.g., a second logic circuit), and a control logic  400  (e.g., a control logic circuit). 
     In some embodiments, the semiconductor device  1  may be, for example, an analog-to-digital converter that converts analog input signals V INP  and V INN  into corresponding digital output signals D OUT . In an embodiment, an input signal is output to the SAR DAC using differential signaling using two complementary signals, namely analog input signals V INP  and V INN . For example, the input signal may be an analog signal sensed by a sensor. In detail, the semiconductor device  1  may be, for example, a successive-approximation-register analog-to-digital converter (SAR ADC) that converts analog input signals V INP  and V INN  provided through a successive approximation scheme into a digital output signal of q bits (where q is a natural number). 
     Hereinafter, the technical spirit of the present disclosure will be described by assuming that the semiconductor device  1  is a SAR ADC, but the present disclosure is not limited thereto. In other embodiments, the semiconductor device  1  may be implemented as an analog-to-digital converter other than a SAR ADC or may be implemented as a semiconductor device  1  other than an analog-to-digital converter. 
     Referring to  FIG.  1   , the SAR DAC  100  may include a first capacitor array  110 , a second capacitor array  120 , and a differential reference voltage generator  130 . 
     The SAR DAC  100  may adjust first and second output voltages VTP and VTN provided to the comparator  300  on the basis of first and second control signals SC 1  and SC 2  received from the control logic  400  which will be described below. When the semiconductor device  1  is a SAR ADC, a reference voltage adjustment circuit may include a digital-to-analog converter (DAC) configured to adjust a reference voltage received from the reference voltage generator  200  according to a digital signal and output the adjusted reference voltage. 
     The SAR DAC  100  may receive analog input signals V INP  and V INN . The SAR DAC  100  may sample and hold the analog input signals V INP  and V INN . The SAR DAC  100  may store the analog input signals V INP  and V INN  using a predetermined storage device in to provide first and second output voltages VTP and VTN based on the analog input signals V INP  and V INN  to the comparator  300 . 
     The SAR DAC  100  may receive a first reference voltage V REFP , a common mode voltage W CM , and a second reference voltage V REFN  from the reference voltage generator  200 . The common mode voltage W CM  may be, for example, an intermediate value between the first reference voltage V REFP  and the second reference voltage V REFN . In an embodiment, the first reference voltage V REFP  is larger than the second reference voltage V REFN . 
     The differential reference voltage generator  130  may generate a first differential reference voltage V DREFP  obtained by dividing the first reference voltage V REFP  and a second differential reference voltage V DREFN  obtained by dividing the second reference voltage V REFN . 
     A first input node of the comparator  300  may be connected to an output of the SAR DAC  100  to receive the first output voltage VTP from the first capacitor array  110 . The first capacitor array  110  may include a plurality of unit capacitors. A second input node of the comparator  300  may be connected to an output of the SAR DAC  100  to receive a second output voltage VTN from the second capacitor array  120 . The second capacitor array  120  may include a plurality of unit capacitors. 
     The comparator  300  may compare the first output voltage VTP of the first capacitor array  110  and the second output voltage VTN of the second capacitor array  120  to generate and output a comparison signal V COMP . When the first output voltage VTP is higher than the second output voltage VTN, the comparator  300  may output a comparison signal V COMP  having a first level. When the first output voltage VTP is lower than the second output voltage VTN, the comparator  300  may output a comparison signal V COMP  having a second level different from the first level. 
     The control logic  400  may include a first SAR logic  410  and a second SAR logic  420 . Although not specifically shown, the first SAR logic  410  and the second SAR logic  420  may be operated by a control signal provided from the control logic  400 . The first SAR logic  410  and the second SAR logic  420  may receive a comparison signal V COMP  from the comparator  300  and may determine bits of the digital output signal D OUT  corresponding to the analog input signals V INP  and V INN  on the basis of the received comparison signal V COMP . For example, the control logic  400  could interpret a value of the analog input signal to be a logic high when the comparison signal V COMP  has the first level and to be a logic low when the comparison signal V COMP  has the second level. 
     The first SAR logic  410  may output a first control signal SC 1  to the first capacitor array  110  on the basis of the comparison signal V COMP . The second SAR logic  420  may output a second control signal SC 2  to the second capacitor array  120  on the basis of the comparison signal V COMP . 
     Although the first SAR logic  410  and the second SAR logic  420  are illustrated as separate logics in the drawing, the present disclosure is not limited thereto. It will be appreciated that the first SAR logic  410  and the second SAR logic  420  may be implemented as a single logic circuit. 
     The SAR DAC  100  may adjust the first output voltage VTP provided to the comparator  300  on the basis of the first control signal SC 1 . The SAR DAC  100  may adjust the second output voltage VTN provided to the comparator  300  on the basis of the second control signal SC 2 . Specifically, the SAR DAC  100  may adjust the levels of the first output voltage VTP and the second output voltage VTN provided to the comparator  300  according to the first control signal SC 1  and the second control signal SC 2 . The SAR DAC  100  may control a plurality of unit capacitors and a plurality of switches included in the first capacitor array  110  according to the first control signal SC 1  to generate the first output voltage VTP and may output the first output voltage VTP to the comparator  300 . Also, the SAR DAC  100  may control a plurality of unit capacitors and a plurality of switches included in the second capacitor array  120  according to the second control signal SC 2  to generate the second output voltage VTN and may output the second output voltage VTN to the comparator  300 . 
     The control logic  400  controls the operation of the first SAR logic  410  and the operation of the second SAR logic  420 . For example, the control logic  400  may control the operation timing of the first SAR logic  410  and the second SAR logic  420 . 
     In an embodiment, the control logic  400  merges bits determined in the first SAR logic  410  and the second SAR logic  420  to generate the digital output signal D our  and outputs the digital output signal D OUT . 
       FIG.  2    is an exemplary circuit diagram of a pull-up circuit included in the reference voltage adjustment circuit of  FIG.  1   .  FIG.  3    is an exemplary circuit diagram of a pull-down circuit included in the reference voltage adjustment circuit of  FIG.  1   .  FIG.  4    is a diagram illustrating an operation in a sampling phase of the reference voltage adjustment circuit of  FIG.  1   .  FIG.  5    is a diagram illustrating an operation in a conversion phase of the reference voltage adjustment circuit of  FIG.  1   . 
     Referring to  FIGS.  1 ,  4  and  5   , the SAR DAC  100  may include a first capacitor array  110  including a plurality of first unit capacitors  2   N-n-2 CU 1 ,  2   N-n-2 CU 2 ,  2   N-n-2 CU 3 ,  2   N-n-2 CU 4 , CU 1 , and  2 CU 2  and a second capacitor array  120  including a plurality of second unit capacitors  2   N-n-2 CU 5 ,  2   N-n-2 CU 6 ,  2   N-n-2 CU 7 ,  2   N-n-2 CU 8 , CU 3 , and  2 CU 4 . In some embodiments, the number of unit capacitors is not limited to those shown in  FIGS.  4  and  5   . Here, N denotes a total number of bits, and n denotes a number of bits in a binary-weighted capacitor array. 
     The SAR DAC  100  may include a first-A capacitor array  100 A including a plurality of thermometer code-based unit capacitors and a first-B capacitor array  100 B including a plurality of unit capacitors having a binary weight structure. 
     The first capacitor array  110  may include a first_ 1  capacitor array  110 _ 1  including a plurality of thermometer code-based unit capacitors and a first_ 2  capacitor array  110 _ 2  including a plurality of binary-weighted unit capacitors. The second capacitor array  120  may include a second_ 1  capacitor array  120 _ 1  including a plurality of thermometer code-based unit capacitors and a second_ 2  capacitor array  120 _ 2  including a plurality of binary-weighted unit capacitors. 
     The first-A capacitor array  100 A including the plurality of thermometer code-based unit capacitors may be used to determine higher N−n bits of a digital output signal corresponding to a provided analog input signal. The first-B capacitor array  100 B including the plurality of binary-weighted unit capacitors may be used to determine n lower bits of a digital output signal. 
     A plurality of first lower unit capacitors CU 1  and  2 CU 2  and a plurality of second lower unit capacitors CU 3  and  2 CU 4  may each have a capacitance that is 2 n  times the capacitance of the unit capacitor. For example, the plurality of first lower unit capacitors CU 1  and  2 CU 2  and the plurality of second lower unit capacitors CU 3  and  2 CU 4  may each have a capacitance that is 2° times or 2 1  times the capacitance of the unit capacitor. That is, the capacitance of the plurality of first lower unit capacitors CU 1  and  2 CU 2  and the plurality of second lower unit capacitors CU 3  and  2 CU 4  may have a binary weight structure. 
     A plurality of first upper unit capacitors  2   N-n-2 CU 1 ,  2   N-n-2 CU 2 ,  2   N-n-2 CU 3 ,  2   N-n-2  CU 4 , and a plurality of second upper unit capacitors  2   N-n-2 CU 5 ,  2   N-n-2 CU 6 ,  2   N-n-2 CU 7 , and  2   N-n-2 CU 8  may each have a capacitance that is 2 N-n-2  times the capacitance of the unit capacitor. In this case, the plurality of first upper unit capacitors  2   N-n-2 CU 1 ,  2   N-n-2 CU 2 ,  2   N-n-2 CU 3 , and  2   N-n-2 CU 4  and the plurality of second upper unit capacitors  2   N-n-2 CU 5 ,  2   N-n-2 CU 6 ,  2   N-n-2 CU 7 , and  2   N-n-2 CU 8  may each have a structure of a plurality of thermometer code-based unit capacitors. 
     The plurality of first upper unit capacitors  2   N-n-2 CU 1 ,  2   N-n-2 CU 2 ,  2   N-n-2 CU 3 , and  2   N-n-2 CU 4  and the plurality of second upper unit capacitors  2   N-n-2 CU 5 ,  2   N-n-2 CU 6 ,  2   N-n-2 CU 7 , and  2   N-n-2 CU 8  may be used to receive a common mode voltage W CM , a first reference voltage V REFP , and a second reference voltage V REFN  and determine upper bits of a digital output signal D OUT . 
     The plurality of first lower unit capacitors CU 1  and  2 CU 2  and the plurality of second lower unit capacitors CU 3  and  2 CU 4  may be used to receive a common mode voltage W CM , a first reference voltage V REFP , and a second reference voltage V REFN  and determine lower bits of a digital output signal D OUT . 
     The first capacitor array  110  may include the plurality of first upper unit capacitors  2   N-n-2 CU 1 ,  2   N-n-2 CU 2 ,  2   N-n-2 CU 3 , and  2   N-n-2 CU 4  and the plurality of first lower unit capacitors CU 1  and  2 CU 2 . A first terminal of each of the plurality of first upper unit capacitors  2   N-n-2 CU 1 ,  2   N-n-2 CU 2 ,  2   N-n-2 CU 3 , and  2   N-n-2 CU 4  and the plurality of first lower unit capacitors CU 1  and  2 CU 2  may be connected to a first input node of the comparator  300 . The second capacitor array  120  may include the plurality of second upper unit capacitors  2   N-n-2 CU 5 ,  2   N-n-2 CU 6 ,  2   N-n-2 CU 7 , and  2   N-n-2 CU 8  and the plurality of second lower unit capacitors CU 3  and  2 CU 4 . A first terminal of each of the plurality of second upper unit capacitors  2   N-n-2 CU 5 ,  2   N-n-2 CU 6 ,  2   N-n-2 CU 7 , and  2   N-n-2 CU 8  and the plurality of second lower unit capacitors CU 3  and  2 CU 4  may be connected to a second input node of the comparator  300 . 
     For example, the first terminal may refer to a top plate of a capacitor, and the second terminal may refer to a bottom plate thereof. 
     The second terminal of each of the plurality of first upper unit capacitors  2   N-n-2 CU 1 ,  2   N-n-2 CU 2 ,  2   N-n-2 CU 3 , and  2   N-n-2 CU 4  and the plurality of second upper unit capacitors  2   N-n-2 CU 5 ,  2   N-n-2 CU 6 ,  2 ′ −2 CU 7 , and  2   N-n-2 CU 8  may be connected to one of a node receiving the analog input signal V INN , a node receiving the analog input signal V INP , a node receiving the first reference voltage V REFP , and a node receiving the second reference voltage V REFN  by a plurality of switches S_ 1 , RFC_ 1 , S_ 2 , and RFC_ 2 . 
     The second terminal of each of the plurality of first lower unit capacitors CU 1  and  2 CU 2  and the plurality of second lower unit capacitors CU 3  and  2 CU 4  may be connected to one of a node receiving the analog input signal V INN , a node receiving the analog input signal V INP , a node receiving the first reference voltage V REFP , and a node receiving the second reference voltage V REFN  by the plurality of switches Si, RFC_ 1 , S_ 2 , and RFC_ 2 . 
     A third sampling switch S_ 3  may be connected between the first input node of the comparator  300  and the plurality of unit cells included in the first capacitor array  110 . A fourth sampling switch S_ 4  may be connected between the second input node of the comparator  300  and the plurality of unit cells included in the second capacitor array  120 . 
     In an embodiment, a unit cell refers to a cell including a pull-up circuit or a pull-down circuit, which will be described below. In this case, referring to  FIGS.  2  to  5   , the pull-up circuit may include a first unit capacitor CU_ 1 , a first sampling switch S_ 1 , and a first reference voltage adjustment switch RFC_ 1 . Referring to  FIG.  2   , the first reference voltage adjustment switch RFC_ 1  may include first and second reference voltage switches RF_ 1  and RF_ 2  and a first SAR operation switch SAR_ 1 . 
     Referring to  FIG.  3   , the pull-down circuit may include a second unit capacitor CU_ 2 , a second sampling switch S_ 2 , and a second reference voltage adjustment switch RFC_ 2 . The second reference voltage adjustment switch RFC_ 2  may include third and fourth reference voltage switches RF_ 3  and RF_ 4  and a second SAR operation switch SAR_ 2 . 
     In this case, the first and second unit capacitors CU_ 1  and CU_ 2  of  FIGS.  2  and  3    may correspond to one of the plurality of unit capacitors CU 1 ,  2 CU 2 , CU 3 ,  2 CU 4 ,  2   N-n-2 CU 1 ,  2   N-n-2 CU 2 ,  2   N-n-2 CU 3 ,  2   N-n-2 CU 4 ,  2   N-n-2 CU 5 ,  2   N-n-2 CU 6 ,  2   N-n-2 CU 7 , and  2   N-n-2 CU 8  of  FIGS.  4  and  5   . Specific details thereof will be described below. 
     The first terminals of the plurality of unit capacitors CU 1 ,  2 CU 2 ,  2   N-n-2 CU 1 ,  2   N-n-2 CU 2 ,  2   N-n-2 CU 3 , and  2   N-n-2 CU 4  included in the first capacitor array  110  may be connected to a node receiving the first reference voltage V REFP  by the third sampling switch S_ 3 . The first terminals of the plurality of unit capacitors CU 3 ,  2 CU 4 ,  2   N-n-2 CU 5 ,  2   N-n-2 CU 6 ,  2   N-n-2 CU 7 , and  2   N-n-2 CU 8  included in the second capacitor array  120  may be connected to a node receiving the first reference voltage V REFP  by the fourth sampling switch S_ 4 . 
     However, the technical spirit of the present disclosure is not limited thereto, and the first terminals may be connected to a node receiving a voltage different from the first reference voltage V REFP , e.g., the common mode voltage V CM , by the third and fourth sampling switches S_ 3  and S_ 4 . The third and fourth sampling switches S_ 3  and S_ 4  may be controlled by the first control signal SC 1  and the second control signal SC 2  output from the first SAR logic  410  and the second SAR logic  420 . 
     Referring to  FIG.  2   , the SAR DAC  100  may include a first pull-up circuit for applying the first reference voltage V REFP  to the first unit capacitor CU_ 1  on the basis of a first switch control signal SW_CTRL_ 1 . The first switch control signal SW_CTRL_ 1  may be a signal received from the control logic  400 . 
     The first pull-up circuit may include a first sampling switch Si configured to receive the first input signals V INP  and V INN , first and second reference voltage switches RF_ 1  and RF_ 2  configured to receive the first switch control signal SW_CTRL_ 1  and apply the first and second reference voltages V REFP  and V REFN , and a first SAR operation switch SAR_ 1  disposed between the first and second reference voltage switches RF_ 1  and RF_ 2 . For example, when the first and second reference voltage switches RF_ 1  and RF_ 2  are implemented by a transistor, the first switch control signal SW_CTRL_ 1  may be applied to a gate terminal of the transistor. 
     In some embodiments, the first pull-up circuit may refer to a circuit in which a resistance component is disposed closer to a power supply voltage than to a ground voltage. In this case, although not specifically illustrated, the ground voltage may correspond to the second reference voltage V REFN , and the power supply voltage may be correspond to the first reference voltage V REFP . 
     The first sampling switch Si may function as a bootstrap switch. In this case, a change in the on-resistance of the sampling switch, which is dependent on the input signals V INP  and V INN , may be made constant. 
     Referring to  FIGS.  2  and  4   , when a sampling operation is performed, the third sampling switch S_ 3  may be turned on, and then the first sampling switch Si may be turned on by receiving a first signal of a first sampling clock signal SAMP_CLK_ 1 , i.e., an operation signal. 
     For example, when the first sampling switch Si is implemented by a transistor, the first sampling clock signal SAMP_CLK_ 1  may be applied to a gate terminal of the transistor. Subsequently, the first SAR operation switch SAR_ 1  may be turned off by receiving a first signal of the first SAR clock signal SAR_CLK_ 1 . For example, when the first SAR operation switch SAR_ 1  is implemented by a transistor, the first SAR clock signal SAR_CLK_ 1  may be applied to a gate terminal of the transistor. Subsequently, the first reference voltage switch RF_ 1  may be turned off by receiving a first signal of the first switch control signal SW_CTRL_ 1 , and thus the first input signals V INP  and V INN  may be sampled in the first unit capacitor CU_ 1  of the first pull-up circuit. For example, when the first reference voltage switch RF_ 1  is implemented by a transistor, the first switch control signal SW_CTRL_ 1  may be applied to a gate terminal of the transistor. In an embodiment, the first sampling clock signal SAMP_CLK_ 1 , the first SAR clock signal SAR_CLK_ 1 , and the first switch control signal SW_CTRL_ 1  is generated based on the first control signal SC 1 . 
     Referring to  FIGS.  2  and  5   , when a conversion operation is performed, the third sampling switch S_ 3  may be turned off, and then the first sampling switch Si may be turned off by receiving a second signal of the first sampling clock signal SAMP_CLK_ 1 . Subsequently, the first SAR operation switch SAR_ 1  may be turned on by receiving a second signal of the first SAR clock signal SAR_CLK_ 1 , i.e., an operation signal. Subsequently, one of the first and second reference voltage switches RF_ 1  and RF_ 2  may be turned on by receiving a second signal of the first switch control signal SW_CTRL_ 1 , and thus the first reference voltage V REFP  may be applied to the first unit capacitor CU_ 1  of the first pull-up circuit. Specifically, by receiving the second signal of the first switch control signal SW_CTRL_ 1 , the first reference voltage switch RF_ 1  may be turned on, and the second reference voltage switch RF_ 2  may be turned off. Thus, the first reference voltage V REFP  may be applied to the first unit capacitor CU_ 1  of the first pull-up circuit. 
     In this case, while the first input signals V INP  and V INN  are being applied to the first unit capacitor CU_ 1  of the first pull-up circuit, neither of the first and second reference voltages V REFP  and V REFN  are applied. Also, while the first input signals V INP  and V INN  are being applied to the first unit capacitor CU_ 1 , only one of the first and second reference voltages V REFP  and V REFN  are applied. 
     That is, by the operation of the first SAR operation switch SAR_ 1  and the operations of the first and second reference voltage switches RF_ 1  and RF_ 2  being controlled by the first SAR clock signal SAR_CLK_ 1  and the first switch control signal SW_CTRL_ 1  in the first pull-up circuit, the first reference voltage V REFP  may be applied to the first unit capacitor CU_ 1 . 
     Referring to  FIG.  3   , the SAR DAC  100  may include a first pull-down circuit for applying the second reference voltage V REFN  to the second unit capacitor CU_ 2  on the basis of a second switch control signal SW_CTRL_ 2 . The second switch control signal SW_CTRL_ 2  may be a signal received from the control logic  400 . 
     The first pull-down circuit may include a second sampling switch S_ 2  configured to receive the second input signals V INP  and V INN , third and fourth reference voltage switches RF_ 3  and RF_ 4  configured to receive the second switch control signal SW_CTRL_ 2  and apply the first and second reference voltages V REFP  and V REFN , and a second SAR operation switch SAR_ 2  disposed between the third and fourth reference voltage switches RF_ 3  and RF_ 4 . 
     In some embodiments, the first pull-down circuit may refer to a circuit in which a resistance component is disposed closer to a ground voltage than to a power supply voltage. In this case, although not specifically illustrated, the ground voltage may correspond to the second reference voltage V REFN , and the power supply voltage may correspond to the first reference voltage V REFP . 
     The second sampling switch S_ 2  may function as a bootstrap switch. In this case, a change in the on-resistance of the sampling switch, which is dependent on the input signals V INP  and V INN , may be made constant. 
     Referring to  FIGS.  3  and  4   , when a sampling operation is performed, the fourth sampling switch S_ 4  may be turned on, and then the second sampling switch S_ 2  may be turned on by receiving a first signal of a second sampling clock signal SAMP_CLK_ 2 , i.e., an operation signal. Subsequently, the second SAR operation switch SAR_ 2  may be turned off by receiving a first signal of the second SAR clock signal SAR_CLK_ 2 . Subsequently, the fourth reference voltage switch RF_ 4  may be turned off by receiving a first signal of the second switch control signal SW_CTRL_ 2 , and thus the second input signals V INP  and V INN  may be sampled in the second unit capacitor CU_ 2  of the first pull-down circuit. 
     Referring to  FIGS.  3  and  5   , when a conversion operation is performed, the fourth sampling switch S_ 4  may be turned off, and then the second sampling switch S_ 2  may be turned off by receiving a second signal of the second sampling clock signal SAMP_CLK_ 2 . In an embodiment, the second sampling clock signal SAMP_CLK_ 2 , the second SAR clock signal SAR_CLK_ 2 , and the second switch control signal SW_CTRL_ 2  is generated based on the first control signal SC 1 . Subsequently, the second SAR operation switch SAR_ 2  may be turned on by receiving a second signal of the second SAR clock signal SAR_CLK_ 2 , i.e., an operation signal. Subsequently, one of the third and fourth reference voltage switches RF_ 3  and RF_ 4  may be turned on by receiving a second signal of the second switch control signal SW_CTRL_ 2 , and thus the second reference voltage V REFN  may be applied to the second unit capacitor CU_ 2  of the first pull-down circuit. Specifically, by receiving the second signal of the second switch control signal SW_CTRL_ 2 , the fourth reference voltage switch RF_ 4  may be turned on, and the third reference voltage switch RF_ 3  may be turned off. Thus, the second reference voltage V REFN  may be applied to the second unit capacitor CU_ 2  of the first pull-down circuit. 
     In this case, while the second input signals V INT  and V INN  are being applied to the second unit capacitor CU_ 2  of the first pull-down circuit, neither of the first and second reference voltages V REFP  and V REFN  are applied. Also, while the second input signals V INP  and V INN  are being applied to the second unit capacitor CU_ 2 , only one of the first and second reference voltages V REFP  and V REFN  is applied. 
     That is, by the operation of the second SAR operation switch SAR_ 2  and the operations of the third and fourth reference voltage switches RF_ 3  and RF_ 4  being controlled by the second SAR clock signal SAR_CLK_ 2  and the second switch control signal SW_CTRL_ 2  in the first pull-down circuit, the second reference voltage V REFP  may be applied to the second unit capacitor CU_ 2 . 
     Referring to  FIGS.  4  and  5   , the first pull-up circuit configured to apply the first reference voltage V REFP  and the first pull-down circuit configured to apply the second reference voltage V REFN  may be alternately disposed. In an embodiment, the first reference voltage V REFP  is a positive voltage, and the second reference voltage V REFN  is a negative voltage. However, the technical spirit of the present disclosure is not limited thereto. The first pull-up circuit and the first pull-down circuit included in the first capacitor array  110  may provide a first output voltage VTP to the comparator  300 . 
     Also, the SAR DAC  100  may further include a second pull-up circuit and a second pull-down circuit configured to provide a second output voltage VTN, which is equal in magnitude but opposite in sign to the first output voltage VTP. The second pull-up circuit and the second pull-down circuit included in the second capacitor array  120  may be alternately disposed. 
     With the split-capacitor switching scheme according to some embodiments, the first reference voltage V REFP  may be applied to one region obtained by dividing the capacitance of the capacitor  2   n - 1 C in half, and the second reference voltage V REFN  may be applied to the other region. As a result, the same effect as in the case of passively applying the common mode voltage W CM  can be obtained. Also, when the conversion operation is sequentially performed from the most significant bit to the least significant bit, it is possible to minimize the power consumed by switching by making a change in reference voltage based on the first or second reference voltages V REFP  and V REFN  rather than based on the common mode voltage. That is, with the split-capacitor switching scheme according to some embodiments, it is possible to minimize the power consumed by switching by reducing the size of the capacitor to ½ and reducing the change in voltage to ¼ compared to the related art. Also, by not using a conventional logic circuit for adjusting the reference voltage, it is possible to further reduce the dynamic power consumed due to an increase in the number of digital logics and switches. 
     The comparator  300  may compare the first output voltage VTP and the second output voltage VTN to perform an operation of approximating the switching operation to digital values. Referring to  FIG.  6   , the first output voltage VTP and the second output voltage VTN denote graphs indicating the switching operation according to some embodiments, and a first_ 1  output voltage VTP_ 1  and a secondi output voltage VTN_ 1  denote graphs indicating the conventional switching operation that does not use a pull-up circuit and a pull-down circuit. In this case, it can be seen that the time required to determine one bit is shorter than that when the conventional switching scheme is used. That is, since the reference voltage can be applied more quickly than in the related art, it is possible to reduce dynamic power consumption. 
     Although exemplary embodiments of the present disclosure have been described above with reference to the accompanying drawings, the present disclosure is not limited to the above embodiments and may be implemented in a variety of different forms. Also, those skilled in the art will appreciate that various modifications and alterations may be made therein without departing from the spirit of the present disclosure. Therefore, the above embodiments are to be regarded as illustrative rather than restrictive.