Patent Publication Number: US-5891800-A

Title: Method for depositing a flow fill layer on an integrated circuit wafer

Description:
This is a continuation in part of U.S. patent application Ser. No. 08/778,074 filed Jan. 7, 1997, now abandoned which is a continuation in part of U.S. patent application Ser. No. 08/769,853 filed Dec. 19, 1996, now U.S. Pat. No. 5,691,247, issued Nov. 25, 1997. 
    
    
     FIELD AND BACKGROUND OF THE INVENTION 
     The present invention relates to the fabrication of ultra large scale integrated circuits and, more particularly, to an improved method for depositing a flow fill intermetallic dielectric on a wafer bearing these circuits. 
     The latest ultra large scale integrated circuits include features as small as about 0.5 microns and smaller. To effect contact with these features, the metallic contacts in the chip that contains the circuits must be stacked in three or more levels. These contacts are formed by a process that includes lithography and etch, and are separated by an intermetallic dielectric, typically SiO 2 . For successful lithography and etch in the formation of a second or subsequent level of metal, the substrate above which they are deposited must be substantially flat. 
     A process for depositing an SiO2 intermetallic dielectric with a substantially flat upper surface is described in C. D. Dobson. A. Kiermasz, K. Beekman and R. J. Wilby, Advanced SiO 2  planarization using silane and H 2  O 2 , Semiconductor International, December 1994, pp. 85-88; in M. Matsuura, Y. Hayashide, H. Kotani, T. Nishimura, H. Iuchi, C. D. Dobson. A. Kiemasz, K. Beekmann and R. Wilby,; and in A. Kiermasz, C. D. Dobson, K. Beekmann add A. H. Bar-Ilan, Planarization for sub-micron devices utilizing a new chemistry, DUMIC Conference, Feb. 21-22, 1995, pp. 94-100. These references are incorporated by reference for all purposes as if fully set forth herein. FIG. 1 schematically shows the &#34;flow fill layer&#34; 30 thus deposited between and around metallic contacts 22. Flow fill layer 30 includes a base layer 32, a flowlayer 34, and a cap layer 36. The essence of the process is the deposition of flowlayer 34, by reacting SiH 4  and H 2  O 2  at 0° C. to form a liquid layer, believed to be primarily Si(OH) 4  in composition. The liquid flows around and above metallic contacts 22, providing a dielectric layer with a substantially flat top surface. Base layer 32 of SiO 2  is deposited, prior to the deposition of flowlayer 34, by plasma enhanced chemical vapor deposition (PECVD), to provide a surface to which flowlayer 34 adheres well. Cap layer 36 of SiO 2  is deposited over flowlayer 34, also by PECVD, to protect flowlayer 34 in the final step: baking the wafer at a temperature of between 400° C. and 450° C. to transform flowlayer 34 from Si(OH) 4  to SiO 2 . 
     It is important that flowlayer 34 not have cracks. The transformation of Si(OH) 4  to SiO 2  involves the evaporation of water as steam, which may induce the formation of cracks in flowlayer 34 as flowlayer 34 is transformed from a liquid to a solid. One of the purposes of cap layer 36 is to prevent the formation of these cracks. Cap layers 36 deposited by the processes known in the art have not been entirely successful in preventing crack formation. It also is important that the top surface of flow layer 30 be relatively flat. The processes known in the art have not entirely succeeded in achieving the desired degree of flatness. 
     There is thus a widely recognized need for, and it would be highly advantageous to have, a method of depositing a flow layer with a flatter top surface and less crack formation than in the prior art processes. 
     SUMMARY OF THE INVENTION 
     According to the present invention there is provided a process for depositing a flow fill layer on an integrated circuit wafer, including the steps of: (a) depositing a first flowlayer on the wafer; and (b) planarizing the first flowlayer. 
     According to the present invention, two flowlayers and two cap layers are deposited. The first cap layer is deposited above the first flowlayer; the second flowlayer is deposited above the first cap layer; and the second cap layer is deposited above the second flowlayer. Preferably, the wafer is warmed in-between the deposition of the first cap layer and the deposition of the second flowlayer, to evaporate water from the first flowlayer. It is preferable but not essential that both cap layers be deposited essentially as described in U.S. Pat. No. 5,691,247. 
     Most preferably, after each flowlayer is deposited and before the corresponding cap layer is deposited, H 2  O 2  is flowed onto the flowlayer, in a planarization step. These planarization steps have been found to greatly improve the global planarization of the flow fill layer. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The invention is herein described, by way of example only, with reference to the accompanying drawings, wherein: 
     FIG. 1 (prior art) is a schematic cross-section through a prior art flow fill layer; 
     FIG. 2 is a schematic cross-section through a flow fill layer of the present invention, formed without planarization of the flowlayers; 
     FIG. 3 is a schematic cross-section through a flow fill layer of the present invention, formed with planarization of the flowlayers. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The present invention is of a method for depositing a flow fill layer. Specifically, the present invention can be used to improve the flatness of the upper surface of the flow fill layer and to inhibit crack formation in the flow fill layer. 
     The principles of flow fill layer deposition according to the present invention may be better understood with reference to the drawings and the following description. The process parameters described herein are specific to the manufacture of a flow fill layer whose base layer 32 is 2000 Å thick, using a Planar 200 multi-chamber cluster tool manufactured by Electrotech of Bristol, UK; but it will be readily apparent to one ordinarily skilled in the art how to adjust the parameters for flow fill layers of other geometries and for other integrated circuit manufacturing devices. 
     The process parameters recommended by Electrotech are as follows: 
     
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Base Layer:
pressure               1400 mT
Nitrogen               1500 sccm
Nitrous Oxide          3500 sccm
SiH.sub.4              150 sccm
RF power               100 W
time                   38 seconds
Flowlayer:
pressure               850 mT
Nitrogen               300 sccm
SiH.sub.4              120 sccm
60% H.sub.2 O.sub.2    0.65 g/sec
time                   62 seconds
Cap Layer: Warm-up Step:
final temperature      300° C.
time                   90 seconds
Cap Layer: Deposition:
pressure               750 mT
Nitrogen               1000 sccm
Nitrous Oxide          2000 sccm
SiH.sub.4              100 sccm
RF power               500 W
time                   36 seconds
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     In the Electrotech warm-up step, the wafer is maintained at a temperature of 300° C. for about 90 seconds in order to start the evaporation water from flowlayer 34 before the actual deposition of the cap layer. 
     FIG. 2 is a schematic cross section of a flow fill layer 40 deposited between and around metallic contacts 22 according to the present invention, without the additional and most preferred steps of planarization of the flowlayers. FIG. 3 is a schematic cross section of a flow fill layer 40 deposited between and around contacts 22 according to the present invention including planarization of the flowlayers. Flow fill layer 40 includes a base layer 41 identical to base layer 32 of FIG. 1, and also two flowlayers 42 and 46, and two cap layers 44 and 48. Preferably, first flowlayer 42 is deposited to a thickness of between about 1000 Å and about 5000 Å, most preferably about 4000 Å. Then, first cap layer 44 is deposited to a thickness of between about 1000 Å and about 2000 Å, most preferably about 1500 Å, in two PECVD steps. The first PECVD step deposits between about 500 Å and about 1000 Å of first cap layer 44, most preferably about 500 Å. The second PECVD step also deposits between about 500 Å about 1000 Å of first cap layer 44, most preferably about 1000 Å. Then, second flowlayer 46 is deposited to a thickness of between about 3000 Å and about 7000 Å, most preferably about 6000 Å. Finally, second cap layer 48 is deposited to a thickness of between about 2000 Å and about 3000 Å, preferably about 2500 Å, also in two PECVD steps. The first PECDV step deposits between about 500 Å and about 1000 Å of second cap layer 48, most preferably about 1000 Å. The second PECVD step deposits between about 1000 Å and about 1500 Å of second cap layer 48, most preferably about 1500 Å. In between the deposition of first cap layer 44 and second flowlayer 46, the wafer is warmed to evaporate water from first flowlayer 42. 
     
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First Flowlayer: Deposition:
pressure                850 mT
Nitrogen                300 sccm
SiH.sub.4               120 sccm
60% H.sub.2 O.sub.2     0.65 g/sec
time                    28 seconds
First Flowlayer: Planarization:
pressure                850 mT
Nitrogen                300 sccm
60% H.sub.2 O.sub.2     0.65 g/sec
time                    30-150 seconds
First Cap Layer: First Step: Warm-up:
final temperature       300° C.-350° C.
time                    up to 10 seconds
First Cap Layer: First step: Deposition:
pressure                750 mT
Nitrogen                1000 sccm
Nitrous Oxide           2000 sccm
SiH.sub.4               100 sccm
RF power                500 W
time                    6 seconds
First Cap Layer: Second Step: Warm-up:
final temperature       300° C.-350° C.
time                    90-180 seconds
First Cap Layer: Second Step: Deposition:
pressure                750 mT
Nitrogen                1000 sccm
Nitrous Oxide           2000 sccm
SiH.sub.4               100 sccm
RF power                500 W
time                    18 seconds
Intermediate Warm-up:
final temperature       300° C.-350° C.
time                    up to 180 seconds
Second Flowlayer: Deposition:
pressure                850 mT
Nitrogen                300 sccm
SiH.sub.4               120 sccm
60% H.sub.2 O.sub.2     0.65 g/sec
time                    40 seconds
Second Flowlayer: Planarization:
pressure                850 mT
Nitrogen                300 sccm
60% H.sub.2 O.sub.2     0.65 g/sec
time                    30-150 seconds
Second Cap Layer: First Step: Warm-up:
final temperature       300° C.-350° C.
time                    up to 10 seconds
Second Cap Layer: First step: Deposition:
pressure                750 mT
Nitrogen                1000 sccm
Nitrous Oxide           2000 sccm
SiH.sub.4               100 sccm
RF power                500 W
time                    12 seconds
Second Cap Layer: Second Step: Warm-up:
final temperature       300° C.-350° C.
time                    90-180 seconds
Second Cap Layer: Second Step: Deposition:
pressure                750 mT
Nitrogen                1000 sccm
Nitrous Oxide           2000 sccm
SiH.sub.4               100 sccm
RF power                500 W
time                    12 seconds
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     It is to be understood that these parameters are illustrative only. The essence of the present invention is the deposition of two flow layers 42 and 46, the planarization of the two flow layers using H 2  O 2 , and the deposition of two cap layers 44 and 48, with partial evaporation of water from first flowlayer 42 after the deposition and planarization of first cap layer 44 and before the deposition of second flow layer 46. It will be apparent, to one ordinarily skilled in the art, how to adapt these parameter values for other applications. 
     While the invention has been described with respect to a limited number of embodiments, it will be appreciated that many variations, modifications and other applications of the invention may be made.