Patent Publication Number: US-9842775-B2

Title: Semiconductor device and method of forming a thin wafer without a carrier

Description:
CLAIM TO DOMESTIC PRIORITY 
     The present application is a division of U.S. patent application Ser. No. 13/933,406, now U.S. Pat. No. 9,443,762, filed Jul. 2, 2013, which is a continuation of U.S. patent application Ser. No. 12/412,279, now U.S. Pat. No. 8,531,015, filed Mar. 26, 2009, which applications are incorporated herein by reference. 
    
    
     FIELD OF THE INVENTION 
     The present invention relates in general to semiconductor devices and, more particularly, to a semiconductor device and method of forming a thin semiconductor wafer without a carrier. 
     BACKGROUND OF THE INVENTION 
     Semiconductor devices are commonly found in modern electronic products. Semiconductor devices vary in the number and density of electrical components. Discrete semiconductor devices generally contain one type of electrical component, e.g., light emitting diode (LED), transistor, resistor, capacitor, inductor, and power metal oxide semiconductor field effect transistor (MOSFET). Integrated semiconductor devices typically contain hundreds to millions of electrical components. Examples of integrated semiconductor devices include microcontrollers, microprocessors, charged-coupled devices (CCDs), solar cells, and digital micro-mirror devices (DMDs). 
     Semiconductor devices perform a wide range of functions such as high-speed calculations, transmitting and receiving electromagnetic signals, controlling electronic devices, transforming sunlight to electricity, and creating visual projections for television displays. Semiconductor devices are found in the fields of entertainment, communications, power generation, networks, computers, and consumer products. Semiconductor devices are also found in electronic products including military, aviation, automotive, industrial controllers, and office equipment. 
     Semiconductor devices exploit the electrical properties of semiconductor materials. The atomic structure of semiconductor material allows its electrical conductivity to be manipulated by the application of an electric field or through the process of doping. Doping introduces impurities into the semiconductor material to manipulate and control the conductivity of the semiconductor device. 
     A semiconductor device contains active and passive electrical structures. Active structures, including transistors, control the flow of electrical current. By varying levels of doping and application of an electric field, the transistor either promotes or restricts the flow of electrical current. Passive structures, including resistors, diodes, and inductors, create a relationship between voltage and current necessary to perform a variety of electrical functions. The passive and active structures are electrically connected to form circuits, which enable the semiconductor device to perform high-speed calculations and other useful functions. 
     Semiconductor devices are generally manufactured using two complex manufacturing processes, i.e., front-end manufacturing, and back-end manufacturing, each involving potentially hundreds of steps. Front-end manufacturing involves the formation of a plurality of die on the surface of a semiconductor wafer. Each die is typically identical and contains circuits formed by electrically connecting active and passive components. Back-end manufacturing involves singulating individual die from the finished wafer and packaging the die to provide structural support and environmental isolation. 
     One goal of semiconductor manufacturing is to produce smaller semiconductor devices. Smaller devices typically consume less power, have higher performance, and can be produced more efficiently. In addition, smaller semiconductor devices have a smaller footprint, which is desirable for smaller end products. A smaller die size may be achieved by improvements in the front-end process resulting in die with smaller, higher density active and passive components. Back-end processes may result in semiconductor device packages with a smaller footprint by improvements in electrical interconnection and packaging materials. 
     In many applications, semiconductor wafers are made as thin as possible to reduce package height. To reduce substrate thickness, the back surface of the wafer undergoes a thinning process such as back grinding or CMP. The thin wafer is susceptible to cracking and breakage during handling and manufacturing processes. To reduce the potential for damage, a carrier wafer is typically affixed to the thin wafer to provide additional structural support. The carrier wafer is removed after the manufacturing process. The need for a carrier wafer adds manufacturing complexity of process and cost. 
     SUMMARY OF THE INVENTION 
     A need exists to form a thin semiconductor substrate without a carrier. Accordingly, in one embodiment, the present invention is a method of making a semiconductor device comprising the steps of providing a semiconductor die, forming a conductive via partially through the semiconductor die, forming a first interconnect structure over a first surface of the semiconductor die, forming a first bump over the first interconnect structure, depositing an encapsulant over the first surface of the semiconductor die, and removing a portion of the semiconductor die to expose the conductive via. 
     In another embodiment, the present invention is a method of making a semiconductor device comprising the steps of providing a substrate, forming a conductive via partially through the substrate, forming a first bump over a first surface of the substrate, depositing an encapsulant over the first surface of the substrate, and removing a portion of the substrate to expose the conductive via. 
     In another embodiment, the present invention is a method of making a semiconductor device comprising the steps of providing a substrate, forming a conductive via partially through the substrate, forming a first interconnect structure over a first surface of the substrate, removing a portion of the substrate to expose the conductive via, and forming a second interconnect structure over a second surface of the substrate opposite the first surface of the substrate. 
     In another embodiment, the present invention is a method of making a semiconductor device comprising the steps of providing a substrate, forming a conductive via in a first surface of the substrate, forming a first interconnect structure over the first surface of the substrate, forming a bump over the first interconnect structure, and depositing an encapsulant over the first interconnect structure and bump. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  illustrates a printed circuit board (PCB) with different types of packages mounted to its surface; 
         FIGS. 2 a -2 c    illustrate further detail of the representative semiconductor packages mounted to the PCB; 
         FIGS. 3 a -3 h    illustrate a process of forming a thin semiconductor substrate without a carrier; 
         FIG. 4  illustrates forming RDL and bumps on a back surface of the thin substrate; 
         FIG. 5  illustrates forming UBM and bumps on a front surface of the thin substrate; 
         FIGS. 6 a -6 e    illustrate an alternate process of forming a thin semiconductor substrate without a carrier using bumps on the front surface; 
         FIGS. 7 a -7 h    illustrate another process of forming a thin semiconductor substrate without a carrier using bumps formed over the TSV; 
         FIG. 8  illustrates forming RDL and bumps on a back surface of the thin substrate; 
         FIG. 9  illustrates forming UBM and bumps on a front surface of the thin substrate; 
         FIGS. 10 a -10 e    illustrate an alternate process of forming a thin semiconductor substrate without a carrier using bumps on the front surface; and 
         FIG. 11  illustrates stacking the thin substrate packages. 
     
    
    
     DETAILED DESCRIPTION OF THE DRAWINGS 
     The present invention is described in one or more embodiments in the following description with reference to the Figures, in which like numerals represent the same or similar elements. While the invention is described in terms of the best mode for achieving the invention&#39;s objectives, it will be appreciated by those skilled in the art that it is intended to cover alternatives, modifications, and equivalents as may be included within the spirit and scope of the invention as defined by the appended claims and their equivalents as supported by the following disclosure and drawings. 
     Semiconductor devices are generally manufactured using two complex manufacturing processes: front-end manufacturing and back-end manufacturing. Front-end manufacturing involves the formation of a plurality of die on the surface of a semiconductor wafer. Each die on the wafer contains active and passive electrical components, which are electrically connected to form functional electrical circuits. Active electrical components, such as transistors, have the ability to control the flow of electrical current. Passive electrical components, such as capacitors, inductors, resistors, and transformers, create a relationship between voltage and current necessary to perform electrical circuit functions. 
     Passive and active components are formed over the surface of the semiconductor wafer by a series of process steps including doping, deposition, photolithography, etching, and planarization. Doping introduces impurities into the semiconductor material by techniques such as ion implantation or thermal diffusion. The doping process modifies the electrical conductivity of semiconductor material in active devices, transforming the semiconductor material into a permanent insulator, permanent conductor, or changing the semiconductor material conductivity in response to an electric field. Transistors contain regions of varying types and degrees of doping arranged as necessary to enable the transistor to promote or restrict the flow of electrical current upon the application of an electric field. 
     Active and passive components are formed by layers of materials with different electrical properties. The layers can be formed by a variety of deposition techniques determined in part by the type of material being deposited. For example, thin film deposition may involve chemical vapor deposition (CVD), physical vapor deposition (PVD), electrolytic plating, and electroless plating processes. Each layer is generally patterned to form portions of active components, passive components, or electrical connections between components. 
     The layers can be patterned using photolithography, which involves the deposition of light sensitive material, e.g., photoresist, over the layer to be patterned. A pattern is transferred from a photomask to the photoresist using light. The portion of the photoresist pattern subjected to light is removed using a solvent, exposing portions of the underlying layer to be patterned. The remainder of the photoresist is removed, leaving behind a patterned layer. Alternatively, some types of materials are patterned by directly depositing the material into the areas or voids formed by a previous deposition/etch process using techniques such as electroless and electrolytic plating. 
     Depositing a thin film of material over an existing pattern can exaggerate the underlying pattern and create a non-uniformly flat surface. A uniformly flat surface is required to produce smaller and more densely packed active and passive components. Planarization can be used to remove material from the surface of the wafer and produce a uniformly flat surface. Planarization involves polishing the surface of the wafer with a polishing pad. An abrasive material and corrosive chemical are added to the surface of the wafer during polishing. The combined mechanical action of the abrasive and corrosive action of the chemical removes any irregular topography, resulting in a uniformly flat surface. 
     Back-end manufacturing refers to cutting or singulating the finished wafer into the individual die and then packaging the die for structural support and environmental isolation. To singulate the die, the wafer is scored and broken along non-functional regions of the wafer called saw streets or scribes. The wafer is singulated using a laser cutting device or saw blade. After singulation, the individual die are mounted to a package substrate that includes pins or contact pads for interconnection with other system components. Contact pads formed over the semiconductor die are then connected to contact pads within the package. The electrical connections can be made with solder bumps, stud bumps, conductive paste, or wirebonds. An encapsulant or other molding material is deposited over the package to provide physical support and electrical isolation. The finished package is then inserted into an electrical system and the functionality of the semiconductor device is made available to the other system components. 
       FIG. 1  illustrates electronic device  10  having a chip carrier substrate or printed circuit board (PCB)  12  with a plurality of semiconductor packages mounted on its surface. Electronic device  10  may have one type of semiconductor package, or multiple types of semiconductor packages, depending on the application. The different types of semiconductor packages are shown in  FIG. 1  for purposes of illustration. 
     Electronic device  10  may be a stand-alone system that uses the semiconductor packages to perform an electrical function. Alternatively, electronic device  10  may be a subcomponent of a larger system. For example, electronic device  10  may be a graphics card, network interface card, or other signal processing card that can be inserted into a computer. The semiconductor package can include microprocessors, memories, application specific integrated circuits (ASICs), logic circuits, analog circuits, RF circuits, discrete devices, or other semiconductor die or electrical components. 
     In  FIG. 1 , PCB  12  provides a general substrate for structural support and electrical interconnect of the semiconductor packages mounted on the PCB. Conductive signal traces  14  are formed over a surface or within layers of PCB  12  using evaporation, electrolytic plating, electroless plating, screen printing, PVD, or other suitable metal deposition process. Signal traces  14  provide for electrical communication between each of the semiconductor packages, mounted components, and other external system components. Traces  14  also provide power and ground connections to each of the semiconductor packages. 
     In some embodiments, a semiconductor device has two packaging levels. First level packaging is a technique for mechanically and electrically attaching the semiconductor die to a carrier. Second level packaging involves mechanically and electrically attaching the carrier to the PCB. In other embodiments, a semiconductor device may only have the first level packaging where the die is mechanically and electrically mounted directly to the PCB. 
     For the purpose of illustration, several types of first level packaging, including wire bond package  16  and flip chip  18 , are shown on PCB  12 . Additionally, several types of second level packaging, including ball grid array (BGA)  20 , bump chip carrier (BCC)  22 , dual in-line package (DIP)  24 , land grid array (LGA)  26 , multi-chip module (MCM)  28 , quad flat non-leaded package (QFN)  30 , and quad flat package  32 , are shown mounted on PCB  12 . Depending upon the system requirements, any combination of semiconductor packages, configured with any combination of first and second level packaging styles, as well as other electronic components, can be connected to PCB  12 . In some embodiments, electronic device  10  includes a single attached semiconductor package, while other embodiments call for multiple interconnected packages. By combining one or more semiconductor packages over a single substrate, manufacturers can incorporate pre-made components into electronic devices and systems. Because the semiconductor packages include sophisticated functionality, electronic devices can be manufactured using cheaper components and a streamlined manufacturing process. The resulting devices are less likely to fail and less expensive to manufacture resulting in lower costs for consumers. 
       FIG. 2 a    illustrates further detail of DIP  24  mounted on PCB  12 . DIP  24  includes semiconductor die  34  having contact pads  36 . Semiconductor die  34  includes an active region containing analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed within semiconductor die  34  and are electrically interconnected according to the electrical design of the die. For example, the circuit may include one or more transistors, diodes, inductors, capacitors, resistors, and other circuit elements formed within the active region of die  34 . Contact pads  36  are made with a conductive material, such as aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), or silver (Ag), and are electrically connected to the circuit elements formed within die  34 . Contact pads  36  are formed by PVD, CVD, electrolytic plating, or electroless plating process. During assembly of DIP  24 , semiconductor die  34  is mounted to a carrier  38  using a gold-silicon eutectic layer or adhesive material such as thermal epoxy. The package body includes an insulative packaging material such as polymer or ceramic. Conductor leads  40  are connected to carrier  38  and wire bonds  42  are formed between leads  40  and contact pads  36  of die  34  as a first level packaging. Encapsulant  44  is deposited over the package for environmental protection by preventing moisture and particles from entering the package and contaminating die  34 , contact pads  36 , or wire bonds  42 . DIP  24  is connected to PCB  12  by inserting leads  40  into holes formed through PCB  12 . Solder material  46  is flowed around leads  40  and into the holes to physically and electrically connect DIP  24  to PCB  12 . Solder material  46  can be any metal or electrically conductive material, e.g., Sn, lead (Pb), Au, Ag, Cu, zinc (Zn), bismuthinite (Bi), and alloys thereof, with an optional flux material. For example, the solder material can be eutectic Sn/Pb, high-lead, or lead-free. 
       FIG. 2 b    illustrates further detail of BCC  22  mounted on PCB  12 . Semiconductor die  47  is connected to a carrier by wire bond style first level packaging. BCC  22  is mounted to PCB  12  with a BCC style second level packaging. Semiconductor die  47  having contact pads  48  is mounted over a carrier using an underfill or epoxy-resin adhesive material  50 . Semiconductor die  47  includes an active region containing analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed within semiconductor die  47  and are electrically interconnected according to the electrical design of the die. For example, the circuit may include one or more transistors, diodes, inductors, capacitors, resistors, and other circuit elements formed within the active region of die  47 . Contact pads  48  are made with a conductive material, such as Al, Cu, Sn, Ni, Au, or Ag, and are electrically connected to the circuit elements formed within die  47 . Contact pads  48  are formed by PVD, CVD, electrolytic plating, or electroless plating process. Wire bonds  54  and bond pads  56  and  58  electrically connect contact pads  48  of semiconductor die  47  to contact pads  52  of BCC  22  forming the first level packaging. Molding compound or encapsulant  60  is deposited over semiconductor die  47 , wire bonds  54 , contact pads  48 , and contact pads  52  to provide physical support and electrical isolation for the device. Contact pads  64  are formed over a surface of PCB  12  using evaporation, electrolytic plating, electroless plating, screen printing, PVD, or other suitable metal deposition process and are typically plated to prevent oxidation. Contact pads  64  electrically connect to one or more conductive signal traces  14 . Solder material is deposited between contact pads  52  of BCC  22  and contact pads  64  of PCB  12 . The solder material is reflowed to form bumps  66  which form a mechanical and electrical connection between BCC  22  and PCB  12 . 
     In  FIG. 2 c   , semiconductor die  18  is mounted face down to carrier  76  with a flip chip style first level packaging. BGA  20  is attached to PCB  12  with a BGA style second level packaging. Active region  70  containing analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed within semiconductor die  18  is electrically interconnected according to the electrical design of the die. For example, the circuit may include one or more transistors, diodes, inductors, capacitors, resistors, and other circuit elements formed within active region  70  of semiconductor die  18 . Semiconductor die  18  is electrically and mechanically attached to carrier  76  through a large number of individual conductive solder bumps or balls  78 . Solder bumps  78  are formed over bump pads or interconnect sites  80 , which are disposed on active region  70 . Bump pads  80  are made with a conductive material, such as Al, Cu, Sn, Ni, Au, or Ag, and are electrically connected to the circuit elements formed in active region  70 . Bump pads  80  are formed by PVD, CVD, electrolytic plating, or electroless plating process. Solder bumps  78  are electrically and mechanically connected to contact pads or interconnect sites  82  on carrier  76  by a solder reflow process. 
     BGA  20  is electrically and mechanically attached to PCB  12  by a large number of individual conductive solder bumps or balls  86 . The solder bumps are formed over bump pads or interconnect sites  84 . The bump pads  84  are electrically connected to interconnect sites  82  through conductive lines  90  routed through carrier  76 . Contact pads  88  are formed over a surface of PCB  12  using evaporation, electrolytic plating, electroless plating, screen printing, PVD, or other suitable metal deposition process and are typically plated to prevent oxidation. Contact pads  88  electrically connect to one or more conductive signal traces  14 . The solder bumps  86  are electrically and mechanically connected to contact pads or bonding pads  88  on PCB  12  by a solder reflow process. Molding compound or encapsulant  92  is deposited over semiconductor die  18  and carrier  76  to provide physical support and electrical isolation for the device. The flip chip semiconductor device provides a short electrical conduction path from the active devices on semiconductor die  18  to conduction tracks on PCB  12  in order to reduce signal propagation distance, lower capacitance, and improve overall circuit performance. In another embodiment, the semiconductor die  18  can be mechanically and electrically attached directly to PCB  12  using flip chip style first level packaging without carrier  76 . 
       FIGS. 3 a -3 h    show a process of forming a thin semiconductor wafer or substrate without a carrier. In  FIG. 3 a   , a substrate or wafer  100  is made with a semiconductor base material such as silicon, germanium, gallium arsenide, indium phosphide, or silicon carbide. In one embodiment, semiconductor wafer  100  is about 30.5 centimeters (cm) in diameter. One or more semiconductor die, as described above, are formed on or mounted to substrate  100 . Each semiconductor die includes analog or digital circuits implemented as active and passive devices, conductive layers, and dielectric layers formed over its active surface and electrically interconnected according to the electrical design of the die. For example, the circuit may include one or more transistors, diodes, and other circuit elements formed within the active surface to implement analog circuits or baseband digital circuits, such as digital signal processor (DSP), memory, or other signal processing circuit. The semiconductor die may also contain IPD, such as inductors, capacitors, and resistors, for RF signal processing. 
     A plurality of through silicon via (TSV)  102  is formed in a front surface of substrate  100  by etching or drilling a via through the silicon material of the substrate to a depth of 30-300 micrometers (μm). The via is filled with Al, Cu, Sn, Ni, Au, Ag, titanium (Ti), W, poly-silicon, or other suitable electrically conductive material using PVD, CVD, electrolytic plating, electroless plating process, or other suitable metal deposition process. 
     An electrically conductive layer  104  is patterned and deposited over substrate  100  and conductive TSV  102 . Conductive layer  104  can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. Conductive layer  104  is formed using PVD, CVD, electrolytic plating, electroless plating process, or other suitable metal deposition process. Conductive layer  104  is a metal pad having electrical connection to the active and passive devices, IPDs, and conductive layers disposed in the semiconductor die. Conductive layer  104  electrically contacts conductive TSV  102 . 
     A dielectric or insulating layer  106  is formed over substrate  100  and conductive layer  104 . The dielectric layer  106  can be one or more layers of silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), tantalum pentoxide (Ta2O5), zircon (ZrO2), aluminum oxide (Al2O3), polyimide, benzocyclobutene (BCB), polybenzoxazoles (PBO), or other material having suitable electrical insulating properties. The dielectric layer  106  is patterned or blanket deposited using PVD, CVD, printing, spin coating, sintering, or thermal oxidation. A portion of dielectric layer  106  is removed by an etching process to expose conductive layer  104 . 
     An electrically conductive layer  108  is patterned and deposited over dielectric layer  106  and conductive layer  104 . Conductive layer  108  can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. Conductive layer  108  is formed using PVD, CVD, electrolytic plating, electroless plating process, or other suitable metal deposition process. Conductive layer  108  operates as a runner or redistribution layer (RDL) to extend the interconnectivity of conductive layer  104 . 
     A passivation or insulating layer  110  is formed over dielectric layer  106  and conductive layer  108 . The passivation layer  110  can be one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, or other material having insulating and structural properties. The passivation layer  110  is patterned or blanket deposited using PVD, CVD, printing, spin coating, sintering, or thermal oxidation. A portion of passivation layer  110  is removed by an etching process to expose conductive layer  108 . 
     In  FIG. 3 b   , an electrically conductive layer  112  is patterned and deposited over passivation layer  110  and conductive layer  108 . Conductive layer  112  can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. Conductive layer  112  is formed using PVD, CVD, electrolytic plating, electroless plating process, or other suitable metal deposition process. Conductive layer  112  operates as an under bump metallization layer (UBM) or bump pad for conductive layer  108 . UBM  112  can be a multi-metal stack with adhesion layer, barrier layer, and seed or wetting layer. The adhesion layer is formed over conductive layer  108  and can be Ti, titanium nitride (TiN), titanium tungsten (TiW), Al, or chromium (Cr). The barrier layer is formed over the adhesion layer and can be made of Ni, nickel vanadium (NiV), platinum (Pt), palladium (Pd), TiW, or chromium copper (CrCu). The barrier layer inhibits the diffusion of Cu into the active area of the die. The seed layer can be Cu, Ni, NiV, Au, or Al. The seed layer is formed over the barrier layer and acts as an intermediate conductive layer between conductive layer  108  and subsequent bumps or other interconnect structure. UBM  112  provides a low resistive interconnect to conductive layer  108 , as well as a barrier to solder diffusion and seed layer for solder wettability. 
     The combination of conductive layers  104  and  108 , UBM  112 , and insulating layers  106  and  110  constitute a front side interconnect structure  113 . 
     In  FIG. 3 c   , an electrically conductive material is deposited over UBM  112  to form bumps  114  using an evaporation, electrolytic plating, electroless plating, ball drop, or screen printing process. The conductive material can be any metal such as Sn, Ni, Au, Ag, Pb, Bi, and alloys thereof, with an optional flux material. 
       FIG. 3 d    shows an encapsulant or molding compound  116  deposited over passivation layer  110  and bumps  114  using a paste printing, compressive molding, transfer molding, liquid encapsulant molding, vacuum lamination, or other suitable applicator. Encapsulant  116  can be polymer composite material, such as epoxy resin with filler, epoxy acrylate with filler, or polymer with proper filler. Encapsulant  116  is non-conductive and environmentally protects the semiconductor device from external elements and contaminants. 
     In  FIG. 3 e   , a portion of encapsulant  116  is removed by CMP, mechanical grinding, plasma etching, wet etch, dry etch, or another thinning process to expose bumps  114 . 
     In  FIG. 3 f   , a portion of a back surface of substrate  100  is removed to expose conductive TSV  102 . The silicon or other base semiconductor material  100  can be removed by CMP, mechanical grinding, plasma etching, wet etch, dry etch, or another thinning process. A back grinding tape can be used for structural support during the thinning process. The remaining portion of substrate  100  is relatively thin, having a thickness less than 100 micrometers (μm). Encapsulant  116  provides structural support for the thin substrate  100  during the thinning process, as well as later handling and processing. Encapsulant  116  eliminates the need for a separate wafer carrier.  FIG. 3 g    shows another embodiment with conductive TSV  102  extending or protruding from the back surface of substrate  100  after the thinning process. 
     In  FIG. 3 h   , an electrically conductive material is deposited over conductive TSV  102  using an evaporation, electrolytic plating, electroless plating, ball drop, or screen printing process. The conductive material can be any metal such as Sn, Ni, Au, Ag, Pb, Bi, and alloys thereof, with an optional flux material. The conductive material is reflowed by heating the material above its melting point to form spherical balls or bumps  118 . In some applications, bumps  118  are reflowed a second time to improve electrical contact to conductive TSV  102 . Bumps  118  represent one type of interconnect structure that can be formed over conductive TSV  102 . The interconnect structure can also use bond wires, 3-D interconnects, stud bump, micro bump, or other electrical interconnect. 
       FIG. 4  shows another embodiment with an electrically conductive layer  120  patterned and deposited over the back surface of substrate  100 . Conductive layer  120  can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. Conductive layer  120  is formed using PVD, CVD, electrolytic plating, electroless plating process, or other suitable metal deposition process. Conductive layer  120  operates as a runner or RDL to extend the interconnectivity of conductive TSV  102 . 
     A passivation or insulating layer  122  is formed over the back surface of substrate  100 , TSV  102 , and conductive layer  120 . The passivation layer  122  can be one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, or other material having insulating and structural properties. The passivation layer  122  is patterned or blanket deposited using PVD, CVD, printing, spin coating, sintering, or thermal oxidation. A portion of passivation layer  122  is removed by an etching process to expose conductive layer  120 . 
     An electrically conductive layer  124  is patterned and deposited over passivation layer  122  and conductive layer  120 . Conductive layer  124  can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. Conductive layer  124  is formed using PVD, CVD, electrolytic plating, electroless plating process, or other suitable metal deposition process. Conductive layer  124  operates as a UBM or bump pad for conductive layer  120 . 
     The combination of conductive layer  120 , UBM  124 , and insulating layer  122  constitute a back side interconnect structure  123 . 
     An electrically conductive material is deposited over UBM  124  using an evaporation, electrolytic plating, electroless plating, ball drop, or screen printing process. The conductive material can be any metal such as Sn, Ni, Au, Ag, Pb, Bi, and alloys thereof, with an optional flux material. The conductive material is reflowed by heating the material above its melting point to form spherical balls or bumps  126 . In some applications, bumps  126  are reflowed a second time to improve electrical contact to UBM  124 . Bumps  126  represent one type of interconnect structure that can be formed over UBM  124 . The interconnect structure can also use bond wires, 3-D interconnects, stud bump, micro bump, or other electrical interconnect. 
     In  FIG. 5 , an electrically conductive layer  130  is patterned and deposited over bump  114 . Conductive layer  130  can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. Conductive layer  130  is formed using PVD, CVD, electrolytic plating, electroless plating process, or other suitable metal deposition process. Conductive layer  130  operates as a UBM or bump pad for bump  114 . 
     An electrically conductive material is deposited over UBM  130  using an evaporation, electrolytic plating, electroless plating, ball drop, or screen printing process. The conductive material can be any metal such as Sn, Ni, Au, Ag, Pb, Bi, and alloys thereof, with an optional flux material. The conductive material is reflowed by heating the material above its melting point to form spherical balls or bumps  132 . In some applications, bumps  132  are reflowed a second time to improve electrical contact to UBM  130 . Bumps  132  represent one type of interconnect structure that can be formed over UBM  130  and bumps  114 . The interconnect structure can also use bond wires, 3-D interconnects, stud bump, micro bump, or other electrical interconnect. 
     An alternate process of forming the thin semiconductor substrate without a carrier is shown in  FIGS. 6 a -6 e   . From the structure set forth in  FIGS. 3 a  and 3 b   , an electrically conductive material is deposited over UBM  112  using an evaporation, electrolytic plating, electroless plating, ball drop, or screen printing process. The conductive material can be any metal such as Sn, Ni, Au, Ag, Pb, Bi, and alloys thereof, with an optional flux material. The conductive material is reflowed by heating the material above its melting point to form spherical balls or bumps  136 . In some applications, bumps  136  are reflowed a second time to improve electrical contact to UBM  112 . 
       FIG. 6 b    shows an encapsulant or molding compound  138  deposited over passivation layer  110  and bumps  136  using a paste printing, compressive molding, transfer molding, liquid encapsulant molding, vacuum lamination, or other suitable applicator. Encapsulant  138  can be polymer composite material, such as epoxy resin with filler, epoxy acrylate with filler, or polymer with proper filler. Encapsulant  138  is non-conductive and environmentally protects the semiconductor device from external elements and contaminants. 
     In  FIG. 6 c   , a portion of encapsulant  138  is removed by CMP, mechanical grinding, plasma etching, wet etch, dry etch, or another thinning process to expose bumps  136 . 
     In  FIG. 6 d   , a portion of substrate  100  is removed to expose conductive TSV  102 . The silicon or other base semiconductor material  100  can be removed by CMP, mechanical grinding, plasma etching, wet etch, dry etch, or another thinning process. A back grinding tape can be used for structural support during the thinning process. The remaining portion of substrate  100  is relatively thin, having a thickness less than 100 μm. Encapsulant  138  provides structural support for the thin substrate  100  during the thinning process, as well as later handling and processing. Encapsulant  138  eliminates the need for a separate wafer carrier. 
     An electrically conductive material is deposited over bump  136  using an evaporation, electrolytic plating, electroless plating, ball drop, or screen printing process. The conductive material can be any metal such as Sn, Ni, Au, Ag, Pb, Bi, and alloys thereof, with an optional flux material. The conductive material is reflowed by heating the material above its melting point to form spherical balls or bumps  140 . In some applications, bumps  140  are reflowed a second time to improve electrical contact to bumps  136 . Bumps  140  represent one type of interconnect structure that can be formed over bumps  136 . The interconnect structure can also use bond wires, 3-D interconnects, stud bump, micro bump, or other electrical interconnect. 
     An electrically conductive material is deposited over conductive TSV  102  using an evaporation, electrolytic plating, electroless plating, ball drop, or screen printing process. The conductive material can be any metal such as Sn, Ni, Au, Ag, Pb, Bi, and alloys thereof, with an optional flux material. The conductive material is reflowed by heating the material above its melting point to form spherical balls or bumps  142 . In some applications, bumps  142  are reflowed a second time to improve electrical contact to conductive TSV  102 . Bumps  142  represent one type of interconnect structure that can be formed over conductive TSV  102 . The interconnect structure can also use bond wires, 3-D interconnects, stud bump, micro bump, or other electrical interconnect. 
     Semiconductor substrate  100  is singulated in  FIG. 6 e    using a laser cutting device or saw blade  144  into individual semiconductor packages  148 . The vertical interconnect structure through semiconductor package  148  includes conductive layers  104  and  108 , UBM  112 , conductive TSV  102 , and bumps  136 ,  140 , and  142 . 
       FIGS. 7 a -7 h    show another process of forming a thin semiconductor substrate without a carrier. In  FIG. 7 a   , a substrate or wafer  150  is made with a semiconductor base material such as silicon, germanium, gallium arsenide, indium phosphide, or silicon carbide. One or more semiconductor die, as described above, are formed on or mounted to substrate  150 . Each semiconductor die includes analog or digital circuits implemented as active and passive devices, conductive layers, and dielectric layers formed over its active surface and electrically interconnected according to the electrical design of the die. For example, the circuit may include one or more transistors, diodes, and other circuit elements formed within the active surface to implement analog circuits or baseband digital circuits, such as DSP, memory, or other signal processing circuit. The semiconductor die may also contain IPD, such as inductors, capacitors, and resistors, for RF signal processing. 
     A plurality of TSV  152  is formed in a front surface of substrate  150  by etching or drilling a via through the silicon material of the substrate to a depth of 30-300 μm. The via is filled with Al, Cu, Sn, Ni, Au, Ag, Ti, W, poly-silicon, or other suitable electrically conductive material using PVD, CVD, electrolytic plating, electroless plating process, or other suitable metal deposition process. 
     An electrically conductive layer  154  is patterned and deposited over substrate  150  and TSV  152 . Conductive layer  154  can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. Conductive layer  154  is formed using PVD, CVD, electrolytic plating, electroless plating process, or other suitable metal deposition process. Conductive layer  154  is a metal pad having electrical connection to the active and passive devices, IPDs, and conductive layers disposed in the semiconductor die. Conductive layer  154  electrically contacts conductive TSV  152 . 
     A dielectric or insulating layer  156  is formed over substrate  150  and conductive layer  154 . The dielectric layer  156  can be one or more layers of SiO2, Si3N4, SiON, Ta2O5, ZrO2, Al2O3, polyimide, BCB, PBO, or other material having suitable electrical insulating properties. The dielectric layer  156  is patterned or blanket deposited using PVD, CVD, printing, spin coating, sintering, or thermal oxidation. A portion of dielectric layer  156  is removed by an etching process to expose conductive layer  154 . 
     An electrically conductive layer  158  is patterned and deposited over dielectric layer  156  and conductive layer  154 . Conductive layer  158  can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. Conductive layer  158  is formed using PVD, CVD, electrolytic plating, electroless plating process, or other suitable metal deposition process. Conductive layer  158  operates as a runner or RDL to extend the interconnectivity of conductive layer  154 . 
     A passivation or insulating layer  160  is formed over dielectric layer  156  and conductive layer  158 . The passivation layer  160  can be one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, or other material having insulating and structural properties. The passivation layer  160  is patterned or blanket deposited using PVD, CVD, printing, spin coating, sintering, or thermal oxidation. A portion of passivation layer  160  is removed by an etching process to expose a portion of conductive layer  158  over conductive TSV  152 . 
     In  FIG. 7 b   , an electrically conductive layer  161  is patterned and deposited over passivation layer  160  and the portion of conductive layer  158  over conductive TSV  152 . Conductive layer  161  can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. Conductive layer  161  is formed using PVD, CVD, electrolytic plating, electroless plating process, or other suitable metal deposition process. Conductive layer  161  operates as a UBM or bump pad for conductive layer  158 . UBM  161  can be a multi-metal stack with adhesion layer, barrier layer, and seed or wetting layer. The adhesion layer is formed over conductive layer  158  and can be Ti, TiN, TiW, Al, or Cr. The barrier layer is formed over the adhesion layer and can be made of Ni, NiV, platinum Pt, Pd, TiW, or CrCu. The barrier layer inhibits the diffusion of Cu into the active area of the die. The seed layer can be Cu, Ni, NiV, Au, or Al. The seed layer is formed over the barrier layer and acts as an intermediate conductive layer between conductive layer  158  and subsequent bumps or other interconnect structure. UBM  161  provides a low resistive interconnect to conductive layer  158 , as well as a barrier to solder diffusion and seed layer for solder wettability. 
     The combination of conductive layers  154  and  158 , UBM  161 , and insulating layers  156  and  160  constitute a front side interconnect structure  159 . 
     In  FIG. 7 c   , an electrically conductive material is deposited over UBM  161  to form bumps  162  using an evaporation, electrolytic plating, electroless plating, ball drop, or screen printing process. Bumps  162  are positioned directly over conductive TSV  152 . The conductive material can be any metal such as Sn, Ni, Au, Ag, Pb, Bi, and alloys thereof, with an optional flux material. 
       FIG. 7 d    shows an encapsulant or molding compound  164  deposited over passivation layer  160  and bumps  162  using a paste printing, compressive molding, transfer molding, liquid encapsulant molding, vacuum lamination, or other suitable applicator. Encapsulant  164  can be polymer composite material, such as epoxy resin with filler, epoxy acrylate with filler, or polymer with proper filler. Encapsulant  164  is non-conductive and environmentally protects the semiconductor device from external elements and contaminants. 
     In  FIG. 7 e   , a portion of encapsulant  164  is removed by CMP, mechanical grinding, plasma etching, wet etch, dry etch, or another thinning process to expose bumps  162 . 
     In  FIG. 7 f   , a portion of a back surface of substrate  150  is removed to expose conductive TSV  152 . The silicon or other base semiconductor material  150  can be removed by CMP, mechanical grinding, plasma etching, wet etch, dry etch, or another thinning process. A back grinding tape can be used for structural support during the thinning process. The remaining portion of substrate  150  is relatively thin, having a thickness less than 100 μm. Encapsulant  164  provides structural support for the thin substrate  150  during the thinning process, as well as later handling and processing. Encapsulant  164  eliminates the need for a separate wafer carrier.  FIG. 7 g    shows another embodiment with TSV  152  extending or protruding from the back surface of substrate  150  after the thinning process. 
     In  FIG. 7 h   , an electrically conductive material is deposited over conductive TSV  152  using an evaporation, electrolytic plating, electroless plating, ball drop, or screen printing process. The conductive material can be any metal such as Sn, Ni, Au, Ag, Pb, Bi, and alloys thereof, with an optional flux material. The conductive material is reflowed by heating the material above its melting point to form spherical balls or bumps  166 . In some applications, bumps  166  are reflowed a second time to improve electrical contact to conductive TSV  152 . Bumps  166  represent one type of interconnect structure that can be formed over conductive TSV  152 . The interconnect structure can also use bond wires, 3-D interconnects, stud bump, micro bump, or other electrical interconnect. 
       FIG. 8  shows another embodiment with an electrically conductive layer  168  patterned and deposited over the back surface of substrate  150 . Conductive layer  168  can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. Conductive layer  168  is formed using PVD, CVD, electrolytic plating, electroless plating process, or other suitable metal deposition process. Conductive layer  168  operates as a runner or RDL to extend the interconnectivity of conductive TSV  152 . 
     A passivation or insulating layer  170  is formed over the back surface of substrate  150 , TSV  152 , and conductive layer  168 . The passivation layer  170  can be one or more layers of SiO2, Si 3 N 4 , SiON, Ta2O5, Al2O3, or other material having insulating and structural properties. The passivation layer  170  is patterned or blanket deposited using PVD, CVD, printing, spin coating, sintering, or thermal oxidation. A portion of passivation layer  170  is removed by an etching process to expose conductive layer  168 . 
     An electrically conductive layer  172  is patterned and deposited over passivation layer  170  and conductive layer  168 . Conductive layer  172  can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. Conductive layer  172  is formed using PVD, CVD, electrolytic plating, electroless plating process, or other suitable metal deposition process. Conductive layer  172  operates as a UBM or bump pad for conductive layer  168 . 
     The combination of RDL  168 , UBM  172 , and insulating layer  170  constitute a back side interconnect structure  173 . 
     An electrically conductive material is deposited over UBM  172  using an evaporation, electrolytic plating, electroless plating, ball drop, or screen printing process. The conductive material can be any metal such as Sn, Ni, Au, Ag, Pb, Bi, and alloys thereof, with an optional flux material. The conductive material is reflowed by heating the material above its melting point to form spherical balls or bumps  174 . In some applications, bumps  174  are reflowed a second time to improve electrical contact to UBM  172 . Bumps  174  represent one type of interconnect structure that can be formed over UBM  172 . The interconnect structure can also use bond wires, 3-D interconnects, stud bump, micro bump, or other electrical interconnect. 
     In  FIG. 9 , an electrically conductive layer  175  is patterned and deposited over bump  162 . Conductive layer  175  can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. Conductive layer  175  is formed using PVD, CVD, electrolytic plating, electroless plating process, or other suitable metal deposition process. Conductive layer  175  operates as a UBM or bump pad for bump  162 . 
     An electrically conductive material is deposited over UBM  175  using an evaporation, electrolytic plating, electroless plating, ball drop, or screen printing process. The conductive material can be any metal such as Sn, Ni, Au, Ag, Pb, Bi, and alloys thereof, with an optional flux material. The conductive material is reflowed by heating the material above its melting point to form spherical balls or bumps  176 . In some applications, bumps  176  are reflowed a second time to improve electrical contact to UBM  175 . Bumps  176  represent one type of interconnect structure that can be formed over UBM  175  and bumps  162 . The interconnect structure can also use bond wires, 3-D interconnects, conductive, stud bump, micro bump, or other electrical interconnect. 
     An alternate process of forming a thin semiconductor substrate without a carrier is shown in  FIGS. 10 a -10 e   . From the structure set forth in  FIGS. 7 a  and 7 b   , an electrically conductive material is deposited over UBM  161  using an evaporation, electrolytic plating, electroless plating, ball drop, or screen printing process. The conductive material can be any metal such as Sn, Ni, Au, Ag, Pb, Bi, and alloys thereof, with an optional flux material. The conductive material is reflowed by heating the material above its melting point to form spherical balls or bumps  180 . In some applications, bumps  180  are reflowed a second time to improve electrical contact to UBM  161 . 
       FIG. 10 b    shows an encapsulant or molding compound  182  deposited over passivation layer  160  and bumps  180  using a paste printing, compressive molding, transfer molding, liquid encapsulant molding, vacuum lamination, or other suitable applicator. Encapsulant  182  can be polymer composite material, such as epoxy resin with filler, epoxy acrylate with filler, or polymer with proper filler. Encapsulant  182  is non-conductive and environmentally protects the semiconductor device from external elements and contaminants. 
     In  FIG. 10 c   , a portion of encapsulant  182  is removed by CMP, mechanical grinding, plasma etching, wet etch, dry etch, or another thinning process to expose bumps  180 . 
     In  FIG. 10 d   , a portion of substrate  150  is removed to expose conductive TSV  152 . The silicon or other base semiconductor material  100  can be removed by CMP, mechanical grinding, plasma etching, wet etch, dry etch, or another thinning process. A back grinding tape can be used for structural support during the thinning process. The remaining portion of substrate  150  is relatively thin, having a thickness less than 100 μm. Encapsulant  182  provides structural support for the thin substrate  150  during the thinning process, as well as later handling and processing. Encapsulant  182  eliminates the need for a separate wafer carrier. 
     An electrically conductive material is deposited over bump  180  using an evaporation, electrolytic plating, electroless plating, ball drop, or screen printing process. The conductive material can be any metal such as Sn, Ni, Au, Ag, Pb, Bi, and alloys thereof, with an optional flux material. The conductive material is reflowed by heating the material above its melting point to form spherical balls or bumps  184 . In some applications, bumps  184  are reflowed a second time to improve electrical contact to bumps  180 . Bumps  184  represent one type of interconnect structure that can be formed over bumps  180 . The interconnect structure can also use bond wires, 3-D interconnects, stud bump, micro bump, or other electrical interconnect. 
     An electrically conductive material is deposited over conductive TSV  152  using an evaporation, electrolytic plating, electroless plating, ball drop, or screen printing process. The conductive material can be any metal such as Sn, Ni, Au, Ag, Pb, Bi, and alloys thereof, with an optional flux material. The conductive material is reflowed by heating the material above its melting point to form spherical balls or bumps  186 . In some applications, bumps  186  are reflowed a second time to improve electrical contact to conductive TSV  152 . Bumps  186  represent one type of interconnect structure that can be formed over conductive TSV  152 . The interconnect structure can also use bond wires, 3-D interconnects, stud bump, micro bump, or other electrical interconnect. 
     Semiconductor substrate  150  is singulated in  FIG. 10 e    using a laser cutting device or saw blade  188  into individual semiconductor packages  190 .  FIG. 11  shows two stacked semiconductor packages  190  with a vertical interconnect structure including bumps  184  and  180 , UBM  161 , RDL  158 , conductive layer  154 , and TSV  152 . 
     While one or more embodiments of the present invention have been illustrated in detail, the skilled artisan will appreciate that modifications and adaptations to those embodiments may be made without departing from the scope of the present invention as set forth in the following claims.