Patent Publication Number: US-2010123693-A1

Title: Data line driver

Description:
CROSS REFERENCE TO RELATED APPLICATION 
     This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2008-292024, filed on Nov. 14, 2008, the entire contents of which are incorporated herein by reference. 
     FIELD OF THE INVENTION 
     The invention relates to a data line driver. 
     DESCRIPTION OF THE BACKGROUND 
     In recent years, liquid crystal displays (LCDs) of an active matrix drive type characterized by thinness, light-weight and low power consumption have been widely prevalent. LCDs of this type are widely used as displays of mobile appliances such as portable terminals, PDAs, and laptop PCs. Each of such liquid crystal displays (LCDs) includes a scanning line driver into which scanning line signals are inputted, and a data line driver into which data line signals are inputted. The data line driver drives data lines by use of multi-level gray-scale voltages corresponding to the number of gray scales, and includes a digital-to-analog converter (DAC) as a decoder that coverts video data to the gray-scale voltages. Japanese Patent Application Publication No. 2007-219091 discloses the digital-to-analog converter. 
     The data line driver driven to display data to be displayed has a problem that, as the number of gray-scale voltages increases in conjunction with enhancement of the image quality (increase in the number of colors), the circuit size of the digital-to-analog converter (DAC), or the chip area of the data line driver increase. 
     SUMMARY OF THE INVENTION 
     According to an aspect of the invention is provided a data line driver comprising a voltage generating circuit configured to receive a first reference voltage and a second reference voltage which is lower than the first reference voltage, the voltage generating circuit dividing a voltage difference between the first reference voltage and the second reference voltage by use of a plurality of ladder resistors and generating n voltages, where n is an integer not smaller than three; and a voltage selector including n switches having first ends to which the mutually different n voltages are respectively applied, the n switches being arranged in parallel to one another, a capacitor provided between second ends of the respective n switches and a lower voltage source, the capacitor being configured to hold electric charges, and a selector configured to generate n control signals to control ON and OFF of the n switches, respectively, wherein the voltage selector is configured to select two voltages from the n voltages and to make a control signal variable, the control signal being inputted into one of switches to which the two voltages are respectively applied, and the voltage selector generates k intermediate voltages, where k is an integer not smaller than one, and the voltage selector outputs the n voltages and the k intermediate voltages. 
     According to another aspect of the invention is provided a data line driver comprising a voltage generating circuit configured to receive a first reference voltage and a second reference voltage which is lower than the first reference voltage, the voltage generating circuit dividing a voltage difference between the first reference voltage and the second reference voltage by use of a plurality of ladder resistors and generating n voltages, where n is an integer not smaller than three; and a voltage selector including n switches having first ends to which the mutually different n voltages are respectively applied, the n switches being arranged in parallel to one another, a selector configured to generate n control signals to control ON and OFF of the n switches, respectively, a first sample hold circuit including a first capacitor provided on second end sides of the respective n switches, and having a first end connected to the second ends of the respective n switches and a second end connected to a lower voltage source, the first capacitor being configured to hold electric charges, and a first discharging portion having a first end connected to the first end of the first capacitor and a second end connected to the lower voltage source, the first discharging portion being configured to discharge electric charges from the first capacitor, the first sample hold circuit having a first time period for charging the first capacitor with electric charges, and a second time period for outputting a voltage based on the electric charges stored in the first capacitor, and a second sample hold circuit including a second capacitor provided on the second end sides of the respective n switches, and having a first end connected to the second ends of the n switches and a second end connected to the lower voltage source, the second capacitor being configured to hold electric charges, and a second discharging portion having a first end connected to the first end of the second capacitor and a second end connected to the lower voltage source, the second discharging portion being configured to discharge electric charges from the second capacitor, the second sample hold circuit having a third time period for charging the second capacitor with electric charges, and a fourth time period for outputting a voltage based on the electric charges stored in the second capacitor, the third time period overlapping the second time period, the fourth time period overlapping the first time period, wherein the voltage selector is configured to make an ON time period variable, the ON time period being for any one of the first discharging portion and the second discharging portion, and the voltage selector generates k intermediate voltages, where k denotes an integer not smaller than one, and the voltage selector outputs the n voltages and the k intermediate voltages. 
     According to further another aspect of the invention is provided A data line driver comprising a voltage generating circuit configured to receive a first reference voltage and a second reference voltage which is lower than the first reference voltage, the voltage generating circuit dividing a voltage difference between the first reference voltage and the second reference voltage by use of a plurality of ladder resistors and generating n voltages, where n is an integer not smaller than three; and a voltage selector including n switches having first ends to which the mutually different n voltages are respectively applied, the n switches being arranged in parallel to one another, a capacitor having a first end connected to second ends of the respective n switches and a second end connected to a lower voltage source, the capacitor being configured to hold electric charges, a selector configured to generate n control signals to control ON and OFF of the n switches, respectively, a first precharging portion provided between a higher voltage source and the first end of the capacitor, the first precharging portion being configured to precharge the capacitor to a voltage of the higher voltage source, and a second precharging portion provided between the first end of the capacitor and the lower voltage source, the second precharging portion being configured to precharge the capacitor to a voltage of the lower voltage source, wherein the voltage selector is configured to select one voltage from the n voltages and to make the control signal variable, the control signal being inputted into a switch connected to the selected voltage, and the voltage selector generates k intermediate voltages, where k is an integer not smaller than one, and the voltage selector outputs the n voltages and the k intermediate voltages. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a schematic block diagram showing a liquid crystal display according to a first embodiment of the invention. 
         FIG. 2  is a circuit diagram showing a data line driver according to the first embodiment of the invention. 
         FIG. 3  is a timing chart showing how the data line driver according to the first embodiment of the invention operates. 
         FIG. 4  is another timing chart showing how the data line driver according to the first embodiment of the invention operates. 
         FIG. 5  is a diagram showing how the data line driver according to the first embodiment of the invention operates in response to variations in a control signal S 2 . 
         FIG. 6  is a timing chart showing how the data line driver according to the first embodiment of the invention operates by use of the control signal S 2  having two high-level time periods. 
         FIG. 7  is a circuit diagram showing a data line driver according to a second embodiment of the invention. 
         FIG. 8  is a circuit diagram showing a data line driver according to a third embodiment of the invention. 
         FIG. 9  is a circuit diagram showing a data line driver according to a fourth embodiment of the invention. 
         FIG. 10  is a timing chart showing how the data line driver according to the fourth embodiment of the invention operates. 
         FIG. 11  is a circuit diagram showing a data line driver according to a fifth embodiment of the invention. 
         FIG. 12  is a timing chart showing how the data line driver according to the fifth embodiment of the invention operates. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Embodiments of the invention will be hereinbelow described with reference to the drawings. 
     A semiconductor integrated circuit according to a first embodiment of the invention will be described with reference to the drawings.  FIG. 1  is a schematic block diagram showing a liquid crystal display.  FIG. 2  is a circuit diagram showing a data line driver. A voltage selector increases the number of gray-scale voltages in the embodiment. 
     As shown in  FIG. 1 , a liquid crystal display  70  includes a display controller  1 , a DC-DC converter  2 , a display panel  3 , a data line driver  4  and a scanning line driver  5 . The liquid crystal display  70  is used for a display of a portable terminal, for example. 
     The data line driver  4  is termed as an X driver, a source driver or a display driver as well. The scanning line driver  5  is termed as a Y driver or a gate driver as well. 
     The display controller  1  integrally controls the entire liquid crystal display  70 . The display controller  1  receives display data and a synchronizing signal, as well as outputs image data and a control signal to the data line driver  4 . In addition, the display controller  1  receives data and a signal which are sent back from the data line driver  4 . 
     The DC-DC converter  2  receives an external power. The DC-DC converter  2  generates a raised power supply voltage, for example, which is needed to operate the data line driver  4  and the scanning line driver  5 , supplies the raised power supply voltage to the data line driver  4  and the scanning line driver  5 . 
     The data line driver  4  receives the image data and the control signal which are outputted from the display controller  1 , as well as the power which is supplied from the DC-DC converter  2 . The data line driver  4  outputs display data, which is needed to drive the display panel  3  for a display operation, to the display panel  3 . The data line driver  4  outputs a control signal, which is synchronized with the display data, to the scanning line driver  5 . 
     The scanning line driver  5  receives the control signal outputted from the data line driver  4 , and the power supplied from the DC-DC converter  2 . The scanning line driver  5  outputs control voltage information, which is needed to drive the display panel  3  for the display operation, to a gate of a thin film transistor (TFT) of the display panel  3 . 
     The display panel  3  includes TFTs, retention capacitors, pixel electrodes (liquid crystal cells) and scanning line loads, which are not illustrated. The display panel  3  receives M channels of display data outputted from the data line driver  4 , and N channels of control voltages for the corresponding TFTs which are outputted from the scanning line driver  5 . The display panel  3  displays an image which the display panel  3  is driven to display on the basis of the image data. 
     As shown in  FIG. 2 , the data line driver  4  includes a counter  6 , a data converter  7 , a gray-scale voltage generating circuit  11 , m voltage selectors (a voltage selector  12   a,  . . . , a voltage selector  12   m ) and m output circuits (an output circuit  13   a,  . . . , an output circuit  13   m ). 
     The voltage selector  12   a,  . . . , the voltage selector  12   m  have the same circuit configuration. The output circuit  13   a,  . . . , the output circuit  13   m  have the same circuit configuration. Each voltage selector is a decoder to convert video data to a gray-scale voltage. Each amplifier circuit is an amplifier to amplify the corresponding gray-scale voltage, and to output the amplified gray-scale voltage. Each voltage selector functions as a digital-to-analog converter (DAC) 
     The gray-scale voltage generating circuit  11  herein is configured to generate four gray-scale voltages (has three ladder resistors) for a simple explanation of the invention. In the case of a display of a full-color portable terminal device, for example, the number of ladder resistors needs to be increased so that the number of required gray-scales would correspond to the number of ladder resistors. 
     The gray-scale voltage generating circuit  11  includes resistors R 1  to R 3 . The gray-scale voltage generating circuit  11  receives a reference voltage Vref 1  and a reference voltage Vref 2 , and generates four gray-scale voltages by voltage-division using the resistors R 1  to R 3 . One end of the resistor R 1  is connected to a node N 1 , and the reference voltage Vref 1  is inputted to the one end of the resistor R 1 . The other end of the resistor R 1  is connected to a node N 2 . One end of the resistor R 2  is connected to the node N 2 , and the other end of the resistor R 2  is connected to a node N 3 . One end of the resistor R 3  is connected to the node N 3 , and the other end of the resistor R 3  is connected to a node N 4 . The reference voltage Vref 2  is inputted to the other end of the resistor R 3 . 
     A relationship between the reference voltage Vref 1  and the reference voltage Vref 2  is set in such a way as to satisfy 
       Vref1&gt;Vref2  Equation (1). 
     The reference voltage Vref 1  is set at 4V, for example. The reference voltage Vref 2  is set at 1V, for example. 
     A relationship among a resistance value r 1  of the resistor R 1 , a resistance value r 2  of the resistor R 2  and a resistance value r 3  of the resistor R 3  is set in such a way as to satisfy 
       r1=r2=r3  Equation (2). 
     As a result, a voltage V 0  as a gray-scale voltage at the node N 1  is set at 4V. A voltage V 1  as a gray-scale voltage at the node N 2  is set at 3V. A voltage V 2  as a gray-scale voltage at the node N 3  is set at 2V. A voltage V 3  as a gray-scale voltage at the node N 4  is set at 1V. 
     Here, the four gray-scale voltages are generated by use of the ladder resistors R 1  to R 3 . In a case where n ladder resistors are used, (n+1) gray-scale voltages can be generated. 
     The data converter  7  receives a gray-scale signal as a video data signal. The data converter  7  converts the gray-scale signal to a counter control signal, and outputs the counter control signal to a selector  21  of a corresponding one of the voltage selectors. 
     The counter  6  receives a clock signal. The counter  6  has multiple binary counters, for example. The counter  6  drops the frequency of the clock signal, and thus generates a count signal. The counter  6  outputs the count signal to the selector  21  of the voltage selector in an appropriate time period. 
     Each of the voltage selector  12   a , . . . , the voltage selector  12   m  includes a selector  21 , a capacitor C 1 , and transistors MT 1  to MT 4 . Each of the voltage selector  12   a,  . . . , the voltage selector  12   m  further generates intermediate gray-scale voltages which are different from the gray-scale voltages generated by the gray-scale voltage generating circuit  11 , and adds the intermediate gray-scale voltages to the gray-scale voltages. Each of the voltage selector  12   a,  . . . , the voltage selector  12   m  then outputs the gray-scale voltages and the intermediary gray-scale voltages to the corresponding output circuit. Detailed description will be given later. 
     The selector  21  is formed of multiple logic circuits, for example. The selector  21  receives the counter control signal outputted from the data converter  7 , and the count signal outputted from the counter  6 . The selector  21  performs a logical operation on the basis of the counter control signal and the count signal. The selector  21  generates control signals S 1  to S 4 . The control signal S 1  is a signal to control the ON and OFF of the transistor MT 1  functioning as a switch. The control signal S 2  is a signal to control the ON and OFF of the transistor MT 2  functioning as a switch. The control signal S 3  is a signal to control the ON and OFF of the transistor MT 3  functioning as a switch. The control signal S 4  is a signal to control the ON and OFF of the transistor MT 4  functioning as a switch. 
     The transistor MT 1  is provided between the node N 1  and a node N 5 . The control signal S 1  outputted from the selector  21  is inputted to the gate of the transistor MT 1 . The transistor MT 1  performs ON and OFF operations on the basis of the control signal S 1 . The transistor MT 2  is provided between the node N 2  and the node N 5 . The control signal S 2  outputted from the selector  21  is inputted to the gate of the transistor MT 2 . The transistor MT 2  performs ON and OFF operations on the basis of the control signal S 2 . The transistor MT 3  is provided between the node N 3  and the node N 5 . The control signal S 3  outputted from the selector  21  is inputted to the gate of the transistor MT 3 . The transistor MT 3  performs ON and OFF operations on the basis of the control signal S 3 . The transistor MT 4  is provided between the node N 4  and the node N 5 . The control signal S 4  outputted from the selector  21  is inputted to the gate of the transistor MT 4 . The transistor MT 4  performs ON and OFF operations on the basis of the control signal S 4 . 
     Here, the transistors MT 1  to MT 4  are N-channel insulated-gate field-effect transistors. Hereinbelow, all the transistors in use illustrated in the drawings are insulated-gate field-effect transistors. Each insulated-gate field-effect transistor is a MOSFET or a MISFET. 
     The capacitor C 1  is provided between the node N 5  and a lower voltage source VSS whose electric potential is a ground potential, and functions as a retention capacitor. The capacitor C 1  should preferably be such a capacitor that a film quality of a dielectric film constituting the capacitor is excellent, and that a leakage from the capacitor is very small in amount. In addition, the capacitor C 1  should preferably be such a capacitor that the charging of the capacitor with electric charges and the discharging of electric charges from the capacitor (the charge time, the discharge time, the charge transient characteristic, the discharge transient characteristic and the like) can recur. 
     Each of the output circuit  13   a,  . . . , the output circuit  13   m  includes an amplifier AMP 1  and an output terminal Pout 1 . 
     The amplifier AMP 1  is provided between the node N 5  and a node N 6 . An input-side plus port of the amplifier AMP 1  is connected to the node N 5 . As a feedback signal, a signal from the output side of the amplifier AMP 1  is inputted to an input-side minus port of the amplifier AMP 1 . The amplifier AMP 1  amplifies a gray-scale voltage at the node N 5 , and outputs the resultant gray-scale voltage, as a display data signal needed to operate the display panel  3  for the display operation, to the display panel  3  (illustrated in  FIG. 1 ) via the output terminal Pout 1 . 
     Next, descriptions will be provided for how the data line driver operates with reference to  FIGS. 3 to 6 .  FIGS. 3 and 4  are timing charts each showing how the data line driver  4  operates. Here, on the basis of the control signal S 1  and the control signal S 2  outputted from the selector  21 , the data line driver  4  generates four intermediate voltages V 10  to V 13  within a range between the gray-scale voltage V 0  and the gray-scale voltage V 1 , which are generated by the gray-scale voltage generating circuit  11 . In  FIG. 3 , a high-level time period for which the control signal S 2  is at a high level is made variable. In  FIG. 4 , a high-level time period for which the control signal S 1  is at a high level is made variable. 
     As shown in  FIG. 3 , by use of the high-level control signal S 1  for a high-level time period T 1 , the transistor MT 1  is tuned on for the high-level time period T 1 , thereby connecting the node N 1  to the node N 5 . Accordingly, a voltage of the node N 5  is set equal to the voltage V 0  (4V), and the capacitor C 1  is charged. As a result, a voltage of the node N 6  is set equal to the voltage V 0  (4V) (a voltage level of the display data signal is set at 4V) 
     A relationship between a time Tc 1  (not illustrated) for which the capacitor C 1  is charged by applying 4V to the capacitor C 1  and the high-level time period T 1  is set in such a way as to satisfy 
       T1&gt;&gt;Tc1  Equation (3). 
     The capacitor C 1  is fully charged with electric charges by applying 4V to the capacitor C 1 . 
     Subsequently, the control signal S 1  changes from the high level to a low level. By use of the high-level control signal S 2  for a relatively-short high-level time period T 2   a,  the transistor MT 2  is tuned on for the high-level period T 2   a,  thereby connecting the node N 2  to the node N 5 . Accordingly, the voltage of the node N 5  is set equal to the voltage V 1  (3V), and part of the electric charges which are stored in the capacitor C 1  is discharged from the capacitor C 1 . As a result, the voltage of the node N 6  is set equal to the voltage V 10  which is lower than the voltage V 0  (the voltage level of the display data signal is set at V 10 ). 
     Subsequently, by use of the high-level control signal S 1  for the high-level time period T 1 , the transistor MT 1  is turned on, thereby connecting the node N 1  to the node N 5 . Accordingly, the voltage of the node N 5  is set equal to the voltage V 0  (4V), and the capacitor C 1  is charged. Thereafter, by use of the high-level control signal S 2  for a high-level time period T 2   b  longer than the high-level time period Ta, the transistor MT 2  is turned on for the high-level time period T 2   b,  thereby connecting the node N 2  to the node N 5 . Accordingly, the voltage of the node N 5  is set equal to the voltage V 1  (3V), and part of the electric charges which are stored in the capacitor C 1  is discharged from the capacitor C 1 . As a result, the voltage of the node N 6  is set equal to the voltage V 11  which is lower than the voltage V 10  (the voltage level of the display data signal is set at V 11 ). 
     A relationship among a time Tc 2  (not illustrated) for which electric charges are discharged from the capacitor C 1  by applying 3V to the capacitor C 1 , the high-level time period T 2   a,  and the high-level time period T 2   b  are set in such a way as to satisfy 
       T2 a &lt;T2&lt;&lt;Tc2  Equation (4). 
     When the high-level time period T 2   a  and the high-level time period T 2   b  are respectively set at appropriate values, and when an amount of electric charges to be discharged from the capacitor C 1  is thus controlled, the voltages V 10  and V 11  can be respectively set at 3.8V and 3.6V, for example. 
     As shown in  FIG. 4 , by use of the high-level control signal S 1 , the transistor MT 1  is turned on. Subsequently, by use of the low-level control signal S 1 , the transistor MT 1  is turned off. Thereafter, by use of high-level the control signal S 2  for a high-level time period T 2 , the transistor MT 2  is turned on for the high-level time period T 2 , thereby connecting the node N 2  to the node N 5 . Accordingly, the voltage of the node N 5  is set equal to the voltage V 1  (3V), and the electric charges are discharged from the capacitor C 1  by applying 3V to the capacitor C 1 . As a result, the voltage of the node N 6  is set equal to the voltage V 1  (the voltage level of the display data signal is set at 3V). 
     A relationship among a time Tc 21  (not illustrated) for which electric charges are discharged from the capacitor C 1  by applying 3V to the capacitor C 1  and the high-level time period T 2  is set in such a way as to satisfy 
       T2&gt;&gt;Tc21  Equation (5). 
     Electric charges are discharged from the capacitor C 1 , and the capacitor C 1  accordingly stores only an amount of electric charges which are stored when 3V is applied to the capacitor C 1 . 
     Subsequently, once the control signal S 2  is changed from the high level to the low level, the transistor MT 1  is turned on for a high-level time period T 1   a  by use of the high-level control signal S 1  for the high-level time period T 1   a , thereby connecting the node N 1  to the node N 5 . Accordingly, the voltage of the node N 5  is set equal to the voltage V 0  (4V), and the capacitor C 1  is charged. As a result, the voltage of the node N 6  is set equal to the voltage V 13  which is higher than the voltage V 1  (the voltage level of the display data signal is set at V 13 ). 
     Subsequently, by use of the high-level control signal S 1 , the transistor MT 1  is turned on. Thereafter, by use of the low-level control signal S 1 , the transistor MT 1  is turned off. Afterward, by use of the high-level control signal S 2  for the high-level time period T 2 , the transistor MT 2  is turned on for the high-level time period T 2 , thereby connecting the node N 2  and the node N 5 . Accordingly, the voltage of the node N 5  is set equal to the voltage V 1  (3V), and part of the electric charges is discharged from the capacitor C 1  in order that the electric charges stored in the capacitor C 1  should correspond to the 3V. Afterward, by use of the high-level control signal S 1  for a high-level time period T 1   b  longer than the high-level time period T 1   a , the transistor MT 1  is turned on for the high-level time period T 1   b , thereby connecting the node N 1  and the node N 5 . Accordingly, the voltage of the node N 5  is set equal to the voltage V 0  (4V), and the capacitor C 1  is charged. As a result, the voltage of the node N 6  is set equal to a voltage V 12  which is higher than the voltage V 13  (the voltage level of the display data signal is set at V 12 ). 
     A relationship among a time Tc 12  for which the capacitor C 1  is charged by applying 4V to capacitor C 1 , the high-level time period T 1   a  and the high-level time period T 1   b  is set in such a way as to satisfy 
       T1a&lt;T1b&lt;Tc12  Equation (6). 
     When the high-level time period T 1   a  and the high-level time period T 1   b  are respectively set at appropriate values, and when an amount of electric charges with which to charge the capacitor C 1  is thus controlled, the voltages V 12  and V 13  can be respectively set at 3.4V and 3.2V, for example. 
     Note that four intermediate gray-scale voltages are similarly generated between the voltage V 1  and the voltage V 2 , as well as between the voltage V 2  and the voltage V 3  (the illustrations and descriptions will be omitted). 
     As a result, each voltage selector generates the gray-scale voltages (the 12 intermediate gray-scale voltages) which are different from the four gray-scale voltages generated by the gray-scale voltage generating circuit  11 , and adds the 12 intermediate gray-scale voltages to the four gray-scale voltages. Thereby, a display data signal representing the 16 gray scales is outputted from the output circuit to the display panel  3 . For this reason, even if the number of gray-scale voltages is increased, it is possible to suppress the enlargement of the circuit size of each of the gray-scale voltage generating circuit, the voltage selectors and the like. Accordingly, it is possible to suppress the increase in the chip area of the data line driver. In a case of 6 bits (64 gray scales), for example, the data line driver according to the embodiment can make the number of transistors smaller by 60% than a conventional data line driver in which each voltage selector generates no intermediate gray-scale voltages. Nevertheless, the circuit sizes of the control circuits including the counter circuit  6  and the like are slightly enlarged. 
     Here, the high-level time period for the control signal S 2  is made variable, so that the voltages V 10  and V 11  are generated, whereas the high-level time period for the control signal S 1  is made variable, so that the voltages V 12  and V 13  are generated. Nevertheless, the four voltages V 10  to V 13  may be generated by use of any other method. 
       FIG. 5  is a diagram showing how the data line driver operates in response to variations in the control signal S 2 . 
     As shown in  FIG. 5 , a relationship among the high-level time period T 2   a,  the high-level time period T 2   b,  a high-level time period T 2   c  and a high-level time period T 2   d  of the control signal S 2  and the time Tc 2  for which electric charges are discharged from the capacitor C 1  by applying 3V to the capacitor C 1 , for example, is set in such a way as to satisfy 
       T2a&lt;T2b&lt;T2c&lt;T2d&lt;&lt;Tc2  Equation (7). 
     Thereby, it is possible to generate the intermediate gray-scale voltages V 10  to V 13 . 
       FIG. 6  is a timing chart showing how the data line driver operates by use of the control signal S 2  which has two high-level time periods. As shown in  FIG. 6 , by use of the high-level control signal S 1  for the high-level time period T 1 , the transistor MT 1  for the high-level time period T 1  is turned on, thereby connecting the node N 1  to the node N 5 . Accordingly, the voltage of the node N 5  is set equal to the voltage V 0  (4V), and the capacitor C 1  is charged. Once the control signal S 1  is changed from the high level to the low level, the intermediate gray-scale voltage V 11  can be generated by use of the control signal S 2  having the high-level time period T 2   a  and a high-level time period T 2   bb  which is longer than the high-level time period T 2   a,  for example. By arbitrarily using the control signal S 2  having two high-level time periods, the intermediate gray-scale voltages V 10 , V 12  and V 13  can be generated similarly. 
     In the case of the semiconductor integrated circuit according to the embodiment, as described above, the liquid crystal display  70  includes the display controller  1 , the DC-DC converter  2 , the display panel  3 , the data line driver  4 , and the scanning line driver  5 . The data line driver  4  includes the counter  6 , the data converter  7 , the gray-scale voltage generating circuit  11 , the m voltage selectors, and the m output circuits. The gray-scale voltage generating circuit  11  includes the resistors R 1  to R 3 , and receives the reference voltage Vref 1  and the reference voltage Vref 2 . Thus, the gray-scale voltage generating circuit  11  generates the four gray-scale voltages V 0  to V 3  by voltage-division using the resistors R 1  to R 3 . Each voltage selector includes the selector  21 , the capacitor C 1 , and the transistors MT 1  to MT 4 . The selector  21  generates the control signals S 1  to S 4  to control the respective transistors MT 1  to MT 4 , on the basis of the counter control signal and the count signal. Each voltage selector selects two adjacent signals from the control signals S 1  to S 4 , and makes the high-level time period for one of the two signals variable. Thereby, the voltage selector generates the intermediate gray-scale voltages which are different from the gray-scale voltages V 0  to V 3 . Thus, each voltage selector outputs the 16 gray-scale voltages in total, which include the gray-scale voltages V 0  to V 3  and the 12 intermediate gray-scale voltages, to the corresponding output circuit. 
     This configuration makes it possible to suppress the enlargement of the circuit sizes of the voltage selectors as the DACs, even if the number of gray-scale voltages increases as the image quality is enhanced. In addition, this configuration makes it possible to suppress the enlargement of the circuit size of the gray-scale voltage generating circuit  11 . Accordingly, it is possible to reduce the chip area of the data line driver  4 , and to thereby reduce the space occupied by the liquid crystal display  70  and the costs. 
     Although the embodiment causes each voltage selector to generate the four intermediate gray-scale voltages on the basis of the two adjacent voltages selected out of the voltages outputted from the gray-scale voltage generating circuit  11 , the invention is not limited to this embodiment. Instead of the four intermediate gray-scale voltages, k intermediate gray-scale voltages (note that k denotes any number of 1, 2, 3 and 5 as well as an integer larger than 5) may be generated. Furthermore, the intermediate gray-scale voltages may be generated by use of two voltages which are not adjacent to each other, instead of the two adjacent voltages. 
     A semiconductor integrated circuit according to a second embodiment of the invention will be described with reference to the drawings.  FIG. 7  is a circuit diagram showing a data line driver. In the embodiment, the configuration of each voltage selector is changed. 
     Hereinbelow, the same portions as those of the first embodiment will be denoted by the same reference numerals. Descriptions for such portions will be omitted. Descriptions will be provided only for portions which are different from those of the first embodiment. 
     As shown in  FIG. 7 , a data line driver  4   b  includes the counter  6 , the data converter  7 , the gray-scale voltage generating circuit  11 , voltage selectors  12   bb  and the output circuits  13   a.  Note that m voltage selectors and m output circuits are provided, although not illustrated. Each voltage selector  12   bb  functions as a digital-to-analog converter (DAC) 
     Each voltage selector  12   bb  includes a selector  21   bb,  the capacitor C 1 , the transistors MT 1  to MT 4 , and a transistor MT 11 . Each voltage selector  12   bb  generates intermediate gray-scale voltages which are different from the gray-scale voltages generated by the gray-scale voltage generating circuit  11 , and adds the intermediate gray-scale voltages to the gray-scale voltages. Each voltage selector  12   bb  then outputs the gray-scale voltages and the intermediary gray-scale voltages to the corresponding output circuit. 
     The selector  21   bb  is formed of multiple logic circuits, for example. The selector  21   bb  receives the counter control signal outputted from the data converter  7 , and the count signal outputted from the counter  6 . The selector  21   bb  performs a logical operation on the basis of the counter control signal and the count signal. The selector  21   bb  generates the control signals S 1  to S 4 , and a control signal S 11 . The control signal S 1  is a signal to control the ON and OFF of the transistor MT 1  functioning as a switch. The control signal S 2  is a signal to control the ON and OFF of the transistor MT 2  functioning as a switch. The control signal S 3  is a signal to control the ON and OFF of the transistor MT 3  functioning as a switch. The control signal S 4  is a signal to control the ON and OFF of the transistor MT 4  functioning as a switch. The control signal S 11  is a signal to control the ON and OFF of the transistor MT 11  functioning as a switch. 
     The transistor MT 11  is an N-channel insulated-gate field-effect transistor. The drain of the transistor MT 11  is connected to the node N 5 , and the source of the. transistor MT 11  is connected to the lower voltage source VSS. The control signal S 11  outputted from the selector  21   bb  is inputted into the gate of the transistor MT 11 . The transistor MT 11  carries out ON and OFF operations on the basis of the control signal S 11 . The transistor MT 11  functions as discharging means for discharging electric charges which are stored in the capacitor C 1 . 
     By making the high-level time period for the control signal S 11  variable, the transistor MT 11  variably decreases the electric charges stored in the capacitor C 1  by an amount corresponding to the high-level time period. As a result, it is possible to apply a voltage correction to the intermediate gray-scale voltages which are generated by use of the transistor MT 1  to MT 4  and the capacitor C 1 . In addition, it is possible to increase the number of gray-scale voltages in comparison with that of the first embodiment. 
     In the embodiment, any two control signals are selected from the control signals S 1  to S 4 , and the voltage correction is applied to the intermediate gray-scale voltages by making the high-level time period for the transistor MT 11  variable. Instead, any one control signal maybe selected from the control signals S 1  to S 4  so that the intermediate gray-scale voltages are generated by making the high-level time period for the transistor MT 11  variable. 
     In the case of the semiconductor integrated circuit according to the embodiment, as described above, the data line driver  4   b  includes the counter  6 , the data converter  7 , the gray-scale voltage generating circuit  11 , the voltage selectors  12   bb  and the output circuits  13   a.  The gray-scale voltage generating circuit  11  includes the resistors R 1  to R 3 , and receives the reference voltage Vref 1  and the reference voltage Vref 2 . Thus, the gray-scale voltage generating circuit  11  generates the four gray-scale voltages V 0  to V 3  by voltage-division using the resistors R 1  to R 3 . Each voltage selector  12   bb  includes the selector  21   bb,  the capacitor C 1 , the transistors MT 1  to MT 4 , and the transistor MT 11 . The selector  21   bb  generates the control signals S 1  to S 4  and S 11  to control the respective transistors MT 1  to MT 4  and the transistor MT 11 , on the basis of the counter control signal and the count signal. Each voltage selector  12   bb  makes the high-level time period for any one of the control signals S 1  to S 4  variable to generate the intermediate gray-scale voltages which are different from the gray-scale voltages V 0  to V 3 . In addition, the voltage selector  12   bb  applies the correction to the intermediate gray-scale voltages by use of the transistor MT 11 . Thus, each voltage selector  12   bb  outputs the gray-scale voltages V 0  to V 3  and the intermediate gray-scale voltages to the corresponding output circuit. 
     For this reason, the embodiment can bring about the same effect as the first embodiment does, and additionally makes it possible to set finer intermediate gray-scale voltages. Accordingly, it is possible to achieve a reduction in the chip area of the data line driver  4   b,  as well as reductions in the space occupied by the liquid crystal display and the costs. 
     A semiconductor integrated circuit according to a third embodiment of the invention will be described with reference to the drawings.  FIG. 8  is a circuit diagram showing a data line driver. In the embodiment, multiple power supplies are provided in a lower voltage source-side of the output side of each voltage selector. 
     Hereinbelow, the same portions as those of the first embodiment will be denoted by the same reference numerals. Descriptions for such portions will be omitted. Descriptions will be provided only for portions which are different from those of the first embodiment. 
     As shown in  FIG. 8 , a data line driver  4   c  includes the counter  6 , the data converter  7 , the gray-scale voltage generating circuit  11 , voltage selectors  12   cc  and the output circuits  13   a.  As in the case of the first embodiment, m voltage selectors and m output circuits are provided, although not illustrated. Each voltage selector  12   cc  functions as a digital-to-analog converter (DAC). 
     Each voltage selector  12   cc  includes a selector  21   cc,  the capacitor C 1 , the transistors MT 1  to MT 4 , transistors MT 111  to transistors MT 11   n,  and power supplies  221  to  22   n.  Each voltage selector  12   cc  generates intermediate gray-scale voltages which are different from the gray-scale voltages generated by the gray-scale voltage generating circuit  11 , and adds the intermediate gray-scale voltages to the gray-scale voltages. Each voltage selector  12   cc  outputs the gray-scale voltages and the intermediary gray voltages to the corresponding output circuit. 
     The selector  21   cc  is formed of multiple logic circuits, for example. The selector  21   cc  receives the counter control signal outputted from the data converter  7 , and the count signal outputted from the counter  6 . The selector  21   cc  performs a logical operation on the basis of the counter control signal and the count signal. The selector  21   cc  generates the control signals S 1  to S 4 , and control signals S 111  to S 11   n.  The control signal S 1  is a signal to control the ON and OFF of the transistor MT 1  functioning as a switch. The control signal S 2  is a signal to control the ON and OFF of the transistor MT 2  functioning as a switch. The control signal S 3  is a signal to control the ON and OFF of the transistor MT 3  functioning as a switch. The control signal S 4  is a signal to control the ON and OFF of the transistor MT 4  functioning as a switch. The control signal S 111  is a signal to control the ON and OFF of the transistor MT 111 . The control signal S 11   n  is a signal to control the ON and OFF of the transistor MT 11   n.    
     Each of the transistors MT 111  to MT 11   n  is an N-channel insulated-gate field-effect transistor. Note that illustrations and descriptions of the transistors MT 112  to MT 11 ( n −1) and the control signals S 112  to S 11 ( n −1) are omitted. 
     The drain of the transistor MT 111  is connected to the node N 5 . The control signal S 111  outputted from the selector  21   cc  is inputted into the gate of the transistor MT 111 . A higher potential side of the power supply  221  is connected to the source of the transistor MT 111 , whereas a lower potential side of the power supply  221  is connected to the lower voltage source VSS. The drain of the transistor MT 11   n  is connected to the node N 5 . The control signal S 11   n  outputted from the selector  21   cc  is inputted into the gate of the transistor MT 11   n.  A higher potential side of the power supply  22   n  is connected to the source of the transistor MT 11   n,  whereas a lower potential side of the power supply  22   n  is connected to the lower voltage source VSS. 
     By making the high-level time period for the control signal S 111  variable, the transistor MT 111  sets the node N 5 -side of the capacitor C 1  equal to a voltage of the power supply  221  during the high-level time period. On the basis of this setup, the transistor MT 111  variably decreases or variably increases the electric charges stored in the capacitor C 1  by an amount corresponding to the high-level time period. By making the high-level time period for the control signal S 11   n  variable, the transistor MT 11   n  sets the node N 5 -side of the capacitor C 1  equal to a voltage of the power supply  22   n  during the high-level time period. On the basis of this setup, the transistor MT 11   n  variably decreases or variably increases electric charges stored in the capacitor C 1  by an amount corresponding to the high-level time period. 
     As a result, it is possible to apply voltage correction to the intermediate gray-scale voltages which are generated by use of the transistors MT 1  to MT 4  and the capacitor C 1 . In addition, it is possible to increase the number of gray-scale voltages in comparison with that of the first embodiment. 
     In the embodiment, any two control signals are selected from the control signals S 1  to S 4 , and the voltage correction is applied to the intermediate gray-scale voltages by making the high-level time period for anyone of the transistors MT 111  to MT 11   n  variable. Instead, any one control signal may be selected from the control signals S 1  to S 4  so that the intermediate gray-scale voltages are generated by making the high-level time period for any one of the transistors MT 111  to MT 11   n  variable. 
     In the case of the semiconductor integrated circuit according to the embodiment, as described above, the data line driver  4   c  includes the counter  6 , the data converter  7 , the gray-scale voltage generating circuit  11 , the voltage selectors  12   cc  and the output circuits  13   a.  The gray-scale voltage generating circuit  11  includes the resistors R 1  to R 3 , and receives the reference voltage Vref 1  and the reference voltage Vref 2 . Thus, the gray-scale voltage generating circuit  11  generates the four gray-scale voltages V 0  to V 3  by voltage-division using the resistors R 1  to R 3 . Each voltage selector  12   cc  includes the selector  21   cc,  the capacitor C 1 , the transistors MT 1  to MT 4 , the transistors MT 111  to MT 11   n,  and the power supplies  221  to  22   n.  The selector  21   cc  generates the control signals S 1  to S 4  and S 111  to S 11   n  to control the respective transistors MT 1  to MT 4 , and MT 111  to MT 11   n,  on the basis of the counter control signal and the count signal. Each voltage selector  12   cc  makes the high-level time period for any one of the control signals S 1  to S 4  variable. Thereby, the voltage selector  12   cc  generates the intermediate gray-scale voltages which are different from the gray-scale voltages V 0  to V 3 . In addition, the voltage selector  12   cc  turns on anyone of the transistors MT 111  to MT 11   n,  and thus applies the correction to the intermediate gray-scale voltages by use of any one of the transistors NT 111  to MT 11   n.  Each voltage selector  12   cc  outputs the gray-scale voltages V 0  to V 3  and the intermediary gray-scale voltages to the corresponding output circuit. 
     For this reason, the embodiment can bring about the same effect as the first embodiment does, and additionally makes it possible to set finer intermediate gray-scale voltages. Accordingly, the embodiment makes it possible to achieve a reduction in the chip area of the data line driver  4   c,  as well as reductions in the space occupied by the liquid crystal display and the costs. 
     A semiconductor integrated circuit according to a fourth embodiment of the invention will be described with reference to the drawings.  FIG. 9  is a circuit diagram showing a data line driver. In the embodiment, sample hold circuits are provided which are provided on the output side of each voltage selector. 
     Hereinbelow, the same portions as those of the first embodiment will be denoted by the same reference numerals. Descriptions for such portions will be omitted. Descriptions will be provided only for portions which are different from those of the first embodiment. 
     As shown in  FIG. 9 , a data line driver  4   d  includes the counter  6 , the data converter  7 , the gray-scale voltage generating circuit  11 , voltage selectors  12   dd  and the output circuits  13   a.  As in the case of the first embodiment, m voltage selectors and m output circuits are provided, although not illustrated. Each voltage selector  12   dd  functions as a digital-to-analog converter (DAC). 
     Each voltage selector  12   dd  includes a selector  21   dd,  a sample hold circuit  23   a,  a sample hold circuit  23   b,  and the transistors MT 1  to MT 4 . Each voltage selector  12   dd  generates intermediate gray-scale voltages which are different from the gray-scale voltages generated by the gray-scale voltage generating circuit  11 , and adds the intermediate gray-scale voltages to the gray-scale voltages. Each voltage selector  12   dd  outputs the gray-scale voltages and the intermediary gray-scale voltages to the corresponding output circuit. 
     The selector  21   dd  is formed of multiple logic circuits, for example. The selector  21   dd  receives the counter control signal outputted from the data converter  7 , and the count signal outputted from the counter  6 . The selector  21   dd  performs a logical operation on the basis of the counter control signal and the count signal. The selector  21   dd  generates the control signals S 1  to S 4 , a control signal S 21  and a control signal S 22 . The control signal S 1  is a signal to control the ON and OFF of the transistor MT 1  functioning as a switch. The control signal S 2  is a signal to control the ON and OFF of the transistor MT 2  functioning as a switch. The control signal S 3  is a signal to control the ON and OFF of the transistor MT 3  functioning as a switch. The control signal S 4  is a signal to control the ON and OFF of the transistor MT 4  functioning as a switch. The control signal S 21  is a signal to control the ON and OFF of the transistor MT 22  of the sample hold circuit  23   a.  The control signal S 22  is a signal to control the ON and OFF of a transistor MT 25  of the sample hold circuit  23   b.    
     The sample hold circuit  23   a  includes transistors MT 21  to MT 23  and a capacitor C 11 . The sample hold circuit  23   b  includes transistors MT 24  to MT 26  and a capacitor C 12 . Each of the sample hold circuits  23   a  and  23   b  plays a role of preventing voltage variations from being propagated to the output circuit while precharging the capacitors C 11  and C 12 , and while discharging electric charges from the capacitors C 11  and C 12 , respectively. The sample hold circuits  23   a  and  23   b  are configured in a way that one of the sample hold circuits  23   a  and  23   b  charges the corresponding capacitor with electric charges while the other outputs a voltage based on electric charges stored in the corresponding capacitor. The transistors MT 21  to MT 26  are N-channel insulated-gate field-effect transistors. 
     The drain of the transistor MT 21  is connected to the node N 5 , and the source of the transistor MT 21  is connected to anode N 11 . A control signal S 23  is inputted into the gate of the transistor MT 21 . The transistor MT 21  performs ON and OFF operations on the basis of the control signal S 23 . One end of the capacitor C 11  is connected to the node N 11 , and the other end of the capacitor C 11  is connected to the lower voltage source VSS. The capacitor C 11  functions as a retention capacitor. The drain of the transistor MT 22  is connected to the node N 11 , and the source of the transistor MT 22  is connected to the lower voltage source VSS. The control signal S 21  outputted from the selector  21   dd  is inputted into the gate of the transistor MT 22 . The transistor MT 22  performs ON and OFF operations on the basis of the control signal S 21 . The transistor MT 22  functions as discharging means for discharging electric charges which are stored in the capacitor  11 . The drain of the transistor MT 23  is connected to the node N 11 . The source of the transistor MT 23  is connected to a node N 12  located closer to the corresponding output circuit. A control signal S 23   a  which is an inversion signal of the control signal S 23  is inputted to the gate of the transistor MT 23 . The transistor MT 23  performs ON and OFF operations on the basis of the control signal S 23   a.    
     Here, LCD output drive signals (LOAD) used outside the data line driver  4   d  are respectively used as the control signals S 23  and S 23   a,  but may be generated inside the data line driver  4   d,  instead. 
     The drain of the transistor MT 24  is connected to the node. N 5 , and the source of the transistor MT 24  is connected to a node N 13 . The control signal S 23   a  is inputted into the gate of the transistor MT 24 . The transistor MT 24  performs ON and OFF operations on the basis of the control signal S 23   a.  One end of the capacitor C 12  is connected to the node N 13 , and the other end of the capacitor C 12  is connected to the lower voltage source VSS. The capacitor C 12  functions as a retention capacitor. The drain of the transistor MT 25  is connected to the node N 13 , and the source of the transistor MT 25  is connected to the lower voltage source VSS. The control signal S 22  outputted from the selector  21   dd  is inputted into the gate of the transistor MT 25 . The transistor MT 25  performs ON and OFF operations on the basis of the control signal S 22 . The transistor MT 25  functions as discharging means for discharging electric charges which are stored in the capacitor  12 . The drain of the transistor MT 26  is connected to the node N 13 . The source of the transistor MT 26  is connected to the node N 12  located closer to the corresponding output circuit. The gate of the control signal  23  is inputted to the transistor MT 26 . The transistor MT 26  performs ON and OFF operations on the basis of the control signal S 23 . 
     Next, how the data line driver operates will be described with reference to  FIG. 10 .  FIG. 10  is a timing chart showing how the data line driver operates. 
     As shown in  FIG. 10 , by use of the high-level control signal S 1  for the high-level time period T 1 , the transistor MT 1  is turned on only for the high-level time period T 1 . The transistor MT 21  of the sample hold circuit  23   a  is kept on during the high-level time period T 1 , because the control signal S 23  is at a high level. Consequently, electric charges are stored in the capacitor C 11  (the capacitor C 11  is precharged with electric charges). A voltage of the node N 11  is raised to the voltage V 0 . 
     Subsequently, the control signal S 1  is changed from the high level to a low level. The control signal S 21  is changed from a low level to a high level. During a high-level time period T 21   a,  the transistor MT 22  is turned on and part of the electric charges stored in the capacitor C 11  is thus discharged. For this reason, a voltage of the node N 11  is set at a voltage V 111  which is lower than the voltage V 0 . This means that the voltage V 111  is generated in the sample hold circuit  23   a  (as indicated by Vout Generation). 
     On the other hand, in the sample hold circuit  23   b,  the transistors MT 24  and MT 25  are turned off and the transistor MT 26  is turned on. Thus, a voltage corresponding to electric charges stored in the capacitor C 12  is outputted to the output circuit (as indicated by Vout Output). 
     Thereafter, the control signal S 23  is changed from the high level to a low level. In parallel, the control signal S 23   a  is changed from a low level to a high level. In the sample hold circuit  23   a,  the transistors MT 21  and MT 22  are turned off and the transistor MT 23  is turned on. Thus, the voltage V 111  corresponding to the electric charges stored in the capacitor C 11  is outputted to the output circuit (as indicated by Vout Output). 
     Afterward, the control signal S 3  is changed from a low level to a high level. During a high-level time period T 3  for the control signal S 3 , the transistor MT 3  is turned on. The transistor MT 24  is kept on, and the transistors MT 25  and MT 26  are kept off. For this reason, electric charges are stored in the capacitor C 12  (the capacitor C 12  is precharged with electric charges), and a voltage of the node N 13  is set equal to the voltage V 3 . 
     After that, the control signal S 3  is changed from the high level to the low level. The control signal S 22  is changed from a high level to a low level. During a high-level time period T 22   a,  the transistor MT 25  is turned on and part of the electric charges stored in the capacitor C 12  is thus discharged. Thus, a voltage of the node N 13  is set at a voltage V 311  which is lower than the voltage V 3 . This means that the voltage V 311  is generated in the sample hold circuit  23   b  (as indicated by Vout Generation). 
     Subsequently, the control signal S 23  is changed from the low level to the high level. In parallel, the control signal S 23   a  is changed from the high level to the low level. In the sample hold circuit  23   b,  the transistors MT 24  and MT 25  are turned off, and the transistor MT 26  is turned on. Thus, the voltage V 311  corresponding to the electric charges stored in the capacitor C 12  is outputted to the output circuit (as indicated by Vout Output). 
     Afterward, the control signal S 3  is changed from the low level to the high level. By use of the high-level control signal S 3  for the high-level time period T 3 , the transistor MT 3  is turned on during the high-level time period T 3 . Because the control signal S 23  is at the high level during this high-level time period T 3 , the transistor MT 21  of the sample hold circuit  23   a  is kept on. Accordingly, part of the electric charges stored in the capacitor C 11  is discharged, and the voltage of the node N 11  is dropped to the voltage V 3 . 
     After that, the control signal S 3  is changed from the high level to the low level. The control signal S 21  is changed from the low level to the high level. By use of the high-level control signal S 21  for a high-level time period T 21   b,  the transistor MT 22  is turned on during the high-level time period T 21   b.  For this reason, part of the electric charges stored in the capacitor C 11  is discharged, and the voltage of the node N 11  is thus dropped to a voltage V 112 . This means that the voltage V 112  is generated in the sample hold circuit  23   a  (as indicated by Vout Generation). 
     Subsequently, the control signal S 23  is changed from the high level to the low level. In parallel, the control signal S 23   a  is changed from the low level to the high level. In the sample hold circuit  23   a,  the transistors MT 21  and MT 22  are turned off and the transistor MT 23  is turned on. For this reason, the voltage V 112  corresponding to the electric charges stored in the capacitor C 11  is outputted to the output circuit (as indicated by Vout Output). 
     Thereafter, the control signal S 1  is changed from the low level to the high level. By use of the high-level control signal S 21  for the high-level time period T 1 , the transistor MT 1  is turned on during the high-level time period T 1 . During the high-level time period T 1 , the control signal S 23   a  is at the high level and thus the transistor MT 24  of the sample hold circuit  23   b  is kept on. Accordingly, the capacitor C 12  is charged with electric charges, and the voltage of the node N 13  is raised to the voltage V 0 . 
     Afterward, the control signal S 1  is changed from the high level to the low level. The control signal S 22  is changed from the low level to the high level. By use of the high-level control signal S 22  for a high-level time period T 22   b,  the transistor MT 25  is turned on during the high-level time period T 22   b.  Thus, part of the electric charges stored in the capacitor C 12  is discharged, and the voltage of the node N 13  is dropped to a voltage V 312  which is lower than the voltage V 0 . This means that the voltage V 312  is generated in the sample hold circuit  23   b  (as indicated by Vout Generation). 
     The Vout generation time period is alternately set between the sample hold circuits  23   a  and  23   b  and the Vout output time period alternately between the sample hold circuits  23   a  and  23   b,  and the high-level time periods for the control signals S 21  and S 22  are made variable. This makes it possible for the voltage selector  12   dd  to generate the intermediate gray-scale voltages which are different from the gray-scale voltages generated by the gray-scale voltage generating circuit  11 . 
     In the semiconductor integrated circuit according to the embodiment, as described above, the data line driver  4   d  includes the counter  6 , the data converter  7 , the gray-scale voltage generating circuit  11 , the voltage selectors  12   dd  and the output circuits  13   a.  The gray-scale voltage generating circuit  11  includes the resistors R 1  to R 3 , and receives the reference voltage Vref 1  and the reference voltage Vref 2 . Thus, the gray-scale voltage generating circuit  11  generates the four gray-scale voltages V 0  to V 3  by voltage-division using the resistors R 1  to R 3 . Each voltage selector  12   dd  includes the selector  21   dd,  the transistors MT 1  to MT 4 , the sample hold circuit  23   a,  and the sample hold circuit  23   b.  On the basis of the counter control signal and the count signal, the selector  21   dd  generates the control signals S 1  to S 4  to control the respective transistors MT 1  to MT 4 , the control signal S 21  to control the transistor MT 22  of the sample hold circuit  23   a,  and the control signal S 22  to control the transistor MT 25  of the sample hold circuit  23   b.  The sample hold circuits  23   a  and  23   b  play a role of preventing voltage variations from being propagated to the output circuit while precharging the capacitors C 11  and C 12  with electric charges, and while discharging electric charges from the capacitors C 11  and C 12 , respectively. The voltage selector  12   dd  makes the high-level time period for the control signal S 21  or S 22  variable, and thus generates the intermediate gray-scale voltages which are different from the gray-scale voltages V 0  to V 3 . 
     For this reason, the embodiment can bring about the same effect as the first embodiment does, and additionally makes it possible to suppress fluctuation of the gray-scale voltages which are outputted from each voltage selector  12   dd.  Accordingly, the embodiment makes it possible to achieve a reduction in the chip area of the data line driver  4   d,  as well as reductions in the space occupied by the liquid crystal display and the costs. 
     In the embodiment, the high-level time period for the control signal S 1  is set as the high-level time period T 1  for which the capacitor C 11  or the capacitor C 12  is fully charged with electric charges, and the high-level time period for the control signal S 3  is set as the high-level time period T 3  for which the capacitor C 11  or the capacitor C 12  is fully charged with electric charges. However, note that the invention is not necessarily limited to the embodiment. A high-level time period for which the capacitor C 11  or the capacitor C 12  is not fully charged with electric charges may be set depending on the necessity. 
     A semiconductor integrated circuit according to a fifth embodiment of the invention will be described with reference to the drawings.  FIG. 11  is a circuit diagram showing a data line driver. In the embodiment, a P-channel MOS transistor is provided on the higher voltage source side of the output side of each voltage selector, whereas an N-channel MOS transistor is provided on the lower voltage source side of the output side of each voltage selector. 
     Hereinbelow, the same portions as those of the first embodiment will be denoted by the same reference numerals. Descriptions for such portions will be omitted. Descriptions will be provided only for portions which are different from those of the first embodiment. 
     As shown in  FIG. 11 , a data line driver  4   e  includes the counter  6 , the data converter  7 , the gray-scale voltage generating circuit  11 , voltage selectors  12   ee  and the output circuits  13   a.  As in the case of the first embodiment, m data line driver  4   e  and  m  output circuits are provided, although not illustrated. Each voltage selector  12   ee  functions as a digital-to-analog converter (DAC). 
     Each voltage selector  12   ee  includes a selector  21   ee,  the capacitor C 1 , the transistors MT 1  to MT 4 , a P-channel MOS transistor PMT 1  and an N-channel MOS transistor NMT 1 . Each voltage selector  12   ee  generates intermediate gray-scale voltages which are different from the gray-scale voltages generated by the gray-scale voltage generating circuit  11 , and adds the intermediate gray-scale voltages to the gray-scale voltages. Each voltage selector  12   ee  outputs the gray-scale voltages and the intermediary gray-scale voltages to the corresponding output circuit. The voltage selector  12   ee  is precharged to the higher voltage source voltage in advance when the gray-scale voltages outputted from the voltage selector  12   ee  are intended to be set at a voltage higher than a half of the higher voltage source voltage. The voltage selector  12   ee  is precharged to the lower voltage source voltage in advance when the gray-scale voltages outputted from the voltage selector  12   ee  are intended to be set at a voltage lower than a half of the higher voltage source voltage. This setup scheme makes it possible to reduce the charging current and the discharging current in amount, and accordingly to reduce the consumed current of the data line driver  4   e  as compared with those of the first to fourth embodiments. 
     The selector  21   ee  is formed of multiple logic circuits, for example. The selector  21   ee  receives the counter control signal outputted from the data converter  7 , and the count signal outputted from the counter  6 . The selector  21   ee  performs a logical operation on the basis of the counter control signal and the count signal. The selector  21   ee  generates the control signals S 1  to S 4 , a control signal S 31  and a control signal S 32 . The control signal S 1  is a signal to control the ON and OFF of the transistor MT 1  functioning as a switch. The control signal S 2  is a signal to control the ON and OFF of the transistor MT 2  functioning as a switch. The control signal S 3  is a signal to control the ON and OFF of the transistor MT 3  functioning as a switch. The control signal S 4  is a signal to control the ON and OFF of the transistor MT 4  functioning as a switch. The control signal S 31  is a signal to control the ON and OFF of the P-channel MOS transistor PMT 1 . The control signal S 32  is a signal to control the ON and OFF of the N-channel MOS transistor NMT 1 . 
     Here, the P-channel MOS transistor PMT 1  and the N-channel MOS transistor NMT 1  are used. Instead, however, a P-channel MIS transistor and an N-channel MIS transistor may be used. 
     The source of the P-channel MOS transistor PMT 1  is connected to a higher voltage source VDD, and the drain of the P-channel MOS transistor PMT 1  is connected to the node N 5 . The control signal S 31  outputted from the selector  21   ee  is inputted into the gate of the P-channel MOS transistor PMT 1 . The P-channel MOS transistor PMT 1  performs ON and OFF operations on the basis of the control signal S 31 . The P-channel MOS transistor PMT 1  sets the node N 5  equal to a voltage of the higher voltage source VDD when the turned on. 
     The drain of the N-channel MOS transistor NMT 1  is connected to the node N 5  and the drain of the P-channel MOS transistor PMT 1 , and the source of the N-channel MOS transistor NMT 1  is connected to the lower voltage source VSS. The control signal S 32  outputted from the selector  21   ee  is inputted into the gate of the N-channel MOS transistor NMT 1 . The N-channel MOS transistor NMT 1  performs ON and OFF operations on the basis of the control signal S 32 . The N-channel MOS transistor NMT 1  sets the node N 5  equal to a voltage of the lower voltage source VSS when turned on. 
     Next, how the data line driver operates will be described with reference to  FIG. 12 .  FIG. 12  is a timing chart showing how the data line driver operates. 
     As shown in  FIG. 12 , when the gray-scale voltages outputted from each voltage selector  12   ee  are intended to be set higher than a half of the higher voltage source voltage (denoted by VDD/2), the control signal S 31  outputted from the selector  21   ee  is changed from a high level to a low level. By use of the low-level controls signal S 31  for a low-level time period T 31 , the P-channel MOS transistor PMT 1  is turned on during the low-level time period T 31 . The capacitor C 1  is precharged with electric charges, and a voltage of the node N 5  is raised. The node N 6  of the output circuit  13   a  is precharged to the voltage of the higher voltage source VDD. Note that the voltage of the higher voltage source VDD is set higher than the voltage V 0 . 
     Subsequently, the control signal S 31  is changed from the low level to the high level, and the control signal S 1  is changed from a low level to a high-level. By use of the high-level control signal S 1  for a high-level time period T 1   aa,  the transistor MT 1  is turned on during the high-level time period T 1   aa.  Part of electric charges stored in the capacitor C 1  is discharged, and a voltage of the node N 5  is dropped. Accordingly, a voltage of the node N 6  of the output circuit  13   a  is set equal to a voltage Vaa which is lower than the voltage of the higher voltage source VDD and the voltage V 0 . 
     Thereafter, the control signal S 1  is changed from the high level to the low level. The control signal S 32  is changed from a low level to a high level. By use of the high-level control signal S 32  for a high-level time period T 32 , the N-channel MOS transistor NMT 1  is turned on during the high-level time period T 32 . The electric charges stored in the capacitor C 1  are discharged, and the voltage of the node N 5  is dropped. Accordingly, the voltage of the node N 6  of the output circuit  13   a  is set equal to the voltage of the lower voltage source VSS (the node N 6  is precharged to the voltage of the lower voltage source VSS). 
     When the gray-scale voltages outputted from each voltage selector  12   ee  are intended to be set lower than a half of the higher voltage source voltage (denoted by VDD/2), the control signal S 3  is changed from a low level to a high level. By use of the high-level control signal S 3  for a high-level time period T 3   a  shorter than the high-level time period T 3 , the transistor MT 3  is turned on during the high-level time period T 3   a.  The capacitor C 1  is charged with electric charges, and the voltage of the node N 5  is raised. The voltage of the node N 6  of the output circuit  13   a  is set at a voltage Vbbwhich is lower than the voltage V 3 . 
     Next, when the gray-scale voltages outputted from the voltage selector  12   ee  are set higher than a half of the higher voltage source voltage (denoted by VDD/2), the control signal S 31  is changed from the high level to the low level. By use of the low-level control signal S 31  for a low-level time period T 31 , the P-channel MOS transistor PMT 1  is turned on during the low-level time period T 31 . Thus, the capacitor C 1  is precharged with electric charges, and the voltage of the node N 5  is raised. Accordingly, the node N 6  of the output circuit  13   a  is precharged to the voltage of the higher voltage source VDD. 
     Afterward, the control signal S 31  is changed from the low level to the high level. The control signal S 1  is changed from the low level to the high level. By use of the high-level control signal S 1  for a high-level time period T 1   bb  shorter than the high-level time period T 1   aa,  the transistor MT 1  is turned on during the high-level time period T 1   bb.  Part of the electric charges stored in the capacitor C 1  is discharged, and the voltage of the node N 5  is dropped. Accordingly, the node N 6  of the output circuit  13   a  is set at the voltage Vbb that is higher than the voltage Vaa and lower than the voltage of the higher voltage source VDD and the voltage V 0 . 
     The P-channel MOS transistor PMT 1  or the N-channel MOS transistor NMT 1  is turned on as appropriate. Any one of the control signals S 1  to S 4  is selected. By making the high-level time period for the selected signal variable, it is possible for the voltage selector  12   ee  to generate the intermediate gray-scale voltages which are different from the gray-scale voltages generated by the gray-scale voltage generating circuit  11 . 
     In the semiconductor integrated circuit according to the embodiment, as described above, the data line driver  4   e  includes the counter  6 , the data converter  7 , the gray-scale voltage generating circuit  11 , the voltage selectors  12   ee  and the output circuits  13   a.  The gray-scale voltage generating circuit  11  includes the resistors R 1  to R 3 , and receives the reference voltage Vref 1  and the reference voltage Vref 2 . Thus, the gray-scale voltage generating circuit  11  generates the four gray-scale voltages V 0  to V 3  by voltage-division using the resistors R 1  to R 3 . Each voltage selector  12   ee  includes the selector  21   ee,  the capacitor C 1 , the transistors MT 1  to MT 4 , the P-channel MOS transistor PMT 1  and the N-channel MOS transistor NMT 1 . On the basis of the counter control signal and the count signal, the selector  21   ee  generates the control signals S 1  to S 4  to control the respective transistors MT 1  to MT 4 , the control signal S 31  to control the P-channel MOS transistor PMT 1 , and the control signal S 32  to control the N-channel transistor NMT 1 . The P-channel MOS transistor PMT 1  functions as precharging means for precharging the capacitor C 1  to the voltage VDD. The N-channel MOS transistor NMT 1  functions as precharging means for precharging the capacitor C 1  to the voltage VSS. The voltage selector  12   ee  makes the high-level time period for any one of the control signals S 1  to S 4  variable, and thus generates the intermediate gray-scale voltages which are different from the gray-scale voltages V 0  to V 3 . 
     For this reason, the embodiment can bring about the same effect as the first embodiment does, and additionally makes it possible to cut down a mean consumed current as compared with that of the first embodiment because it is possible to reduce the voltage fluctuation to a level lower than “VDD/2.” Accordingly, the embodiment makes it possible to achieve a reduction in the chip area of the data line driver  4   e,  as well as reductions in the space occupied by the liquid crystal display and the costs. 
     The invention is not limited to the foregoing embodiments. The invention may be variously modified as long as the modification does not depart from the scope of the invention. 
     In the embodiments, the invention is applied to a data line driver of a liquid crystal display. Instead, however, the invention can be applied to a driver of a flat panel display (FPD) such as an organic light emitting diode (OLED) and a plasma display panel (PDP), for example. In addition, the invention can be applied to an electron volume, instead of a driver. Moreover, in the embodiments, the N-channel insulated-gate field-effect transistor is used as each of the transistors MT 1  to MT 4  provided in each voltage selector. Instead, however, a P-channel insulated-gate field-effect transistor, a transfer gate including an N-channel insulated-gate field-effect transistor and a P-channel insulated-gate field-effect transistor which are connected to each other in parallel, and the like may be used.