Patent Publication Number: US-2023164048-A1

Title: Multi-link receiving method and multi-link receiver

Description:
BACKGROUND 
     Technical Field 
     The disclosure relates to a multi-link communication mechanism. Particularly, the disclosure relates to a multi-link receiving method and a multi-link receiver. 
     Description of Related Art 
     A multi-link transmission mechanism achieves not only transmission of a relatively large bandwidth using a relatively low wire speed, but also link protection and load balance, and is thus widely used in communication systems. 
     With reference to  FIG.  1 A  to  FIG.  1 C ,  FIG.  1 A  is a diagram of a conventional multi-link transmission mechanism,  FIG.  1 B  is a schematic diagram of dividing data frames into data sections, and  FIG.  1 C  is a schematic diagram of transmitting data sections by multi-link channels. In  FIG.  1 A  to  FIG.  1 C , a multi-link channel  103  may be present between a multi-link transmitter  101  and a multi-link receiver  102 . In an embodiment, assuming that the multi-link channel  103  includes a total of an N number of link channels (where N is a positive integer), then when the multi-link transmitter  101  is to send a certain data frame (labeled with FX) to the multi-link receiver  102 , the multi-link transmitter  101  may divide the data frame into an N number of data sections link_ 1 [X] to link_N[X], and then send the N number of data sections to the multi-link receiver  102  respectively through the N number of link channels. 
     For example, assuming that the multi-link transmitter  101  is to send a data frame F 1  to the multi-link receiver  102 , the multi-link transmitter  101  may first divide the data frame F 1  into an N number of data sections link_ 1 [ 1 ] to link_N[ 1 ], and then send the data sections link_ 1 [ 1 ] to link_N[ 1 ] to the multi-link receiver  102  respectively through the N number of link channels. 
     Similarly, when the multi-link transmitter  101  is to send a data frame F 2 , the multi-link transmitter  101  may also divide the data frame F 2  into data sections link_ 1 [ 2 ] to link_N[ 2 ], and then send the data sections link_ 1 [ 2 ] to link_N[ 2 ] to the multi-link receiver  102  through the N number of link channels. In addition, when the multi-link transmitter  101  is to send a data frame FM, the multi-link transmitter  101  may also divide the data frame FM into data sections link_ 1 [M] to link_N[M], and then send the data sections link_ 1 [M] to link_N[M] to the multi-link receiver  102  through the N number of link channels. 
     With reference to  FIG.  2   ,  FIG.  2    is a schematic diagram of a multi-link receiving mechanism according to  FIG.  1 A  to  FIG.  1 C . In  FIG.  2   , the multi-link receiver  102  may include a receiving interface  102   a , a buffer  102   b , a recombining circuit  102   c , and a differential delay control management (DDCM) circuit  102   d . Generally speaking, data sections link_ 1 [X] to link_N[X] may arrive at the receiving interface  102   a  through different transmission paths. As a result, a difference (commonly known as a differential delay) may be present between times when the data sections link_ 1 [X] to link_N[X] arrives at the receiving interface  102   a . In this case, the buffer  102   b  may be configured to temporarily store the data sections link_ 1 [X] to link_N[X], while the recombining circuit  102   c  and the DDCM circuit  102   d  may work together to combine the data sections link_ 1 [X] to link_N[X] to restore a data frame FX. 
     According to the above, a DDCM mechanism may be important in a multi-link transmission system. However, since the DDCM mechanism may be complicated, a DDCM mechanism not performed properly may cause additional delay and packet loss. 
     SUMMARY 
     In view of this, the disclosure provides a multi-link receiving method and a multi-link receiver, which may be used to solve the above technical problems. 
     The disclosure provides a multi-link receiving method, adapted for a multi-link receiver. 
     The multi-link receiving method includes the following. in response to determining that a j-th data section belonging to an i-th data frame is received, a reference delay range of the j-th data section of the i-th data frame is determined according to a preset delay time and a receiving time point of the j-th data section of the i-th data frame, where the i-th data frame includes an N number of data sections, 1≤j≤N, i is an index value, and N is a positive integer; in response to determining that the j-th data section of the i-th data frame is first received among the N number of data sections of the i-th data frame, the reference delay range of the j-th data section of the i-th data frame is taken as a designated delay range corresponding to the i-th data frame; and in response to determining that receiving time points of the data sections of the i-th data frame are each within the designated delay range corresponding to the i-th data frame, the i-th data frame is restored based on the N number of data sections of the i-th data frame. 
     The disclosure provides a multi-link receiver, including a receiving circuit and a processing circuit. The receiving circuit receives a j-th data section belonging to an i-th data frame. The processing circuit is coupled to the receiving circuit, and is configured to: determine a reference delay range of the j-th data section of the i-th data frame according to a preset delay time and a receiving time point of the j-th data section of the i-th data frame, where the i-th data frame includes an N number of data sections, 1≤j≤N, i is an index value, and N is a positive integer; in response to determining that the j-th data section of the i-th data frame is first received among the N number of data sections of the i-th data frame, take the reference delay range of the j-th data section of the i-th data frame as a designated delay range corresponding to the i-th data frame; and in response to determining that receiving time points of the data sections of the i-th data frame are each within the designated delay range corresponding to the i-th data frame, restore the i-th data frame based on the N number of data sections of the i-th data frame. 
     To make the aforementioned more comprehensible, several embodiments accompanied with drawings are described in detail as follows. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The accompanying drawings are included to provide a further understanding of the disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the disclosure and, together with the description, serve to explain the principles of the disclosure. 
         FIG.  1 A  is a diagram of a conventional multi-link transmission mechanism. 
         FIG.  1 B  is a schematic diagram of dividing data frames into data sections. 
         FIG.  1 C  is a schematic diagram of transmitting data sections by multi-link channels. 
         FIG.  2    is a schematic diagram of a multi-link receiving mechanism according to  FIG.  1 A  to  FIG.  1 C . 
         FIG.  3    is a schematic diagram of a multi-link transmission system according to an embodiment of the disclosure. 
         FIG.  4    is a flowchart of a multi-link receiving method according to an embodiment of the disclosure. 
         FIG.  5    is a diagram of an application scenario according to an embodiment of the disclosure. 
         FIG.  6    is a diagram of another application scenario according to  FIG.  5   . 
         FIG.  7    is a schematic diagram of a multi-link receiver according to an embodiment of the disclosure. 
     
    
    
     DESCRIPTION OF THE EMBODIMENTS 
     With reference to  FIG.  3   ,  FIG.  3    is a schematic diagram of a multi-link transmission system according to an embodiment of the disclosure. In  FIG.  3   , a multi-link transmission system  30  includes, for example, the multi-link transmitter  101  and a multi-link receiver  310 . The multi-link transmitter  101  may send an N number of data sections divided from a data frame to the multi-link receiver  310  through the multi-link channel  103 . Reference may be made to the above description for the details of the multi-link transmitter  101  and the multi-link channel  103  of this embodiment, which will not be repeatedly described herein. 
     In an embodiment, the multi-link receiver  310  includes a receiving circuit  312  and a processing circuit  314 . The processing circuit  314  is coupled to the receiving circuit  312 . In the embodiments of the disclosure, the receiving circuit  312  and the processing circuit  314  may work together to perform a multi-link receiving method provided by the disclosure, details of which are described below. 
     With reference to  FIG.  4   ,  FIG.  4    is a flowchart of a multi-link receiving method according to an embodiment of the disclosure. The method of this embodiment may be performed by the multi-link receiver  310  of  FIG.  3   . Hereinafter, details of each step of  FIG.  4    accompanied with the elements as shown in  FIG.  3    will be described. In addition, to make the disclosure easier to understand, further description with the aid of  FIG.  5    will be provided below.  FIG.  5    is a diagram of an application scenario according to an embodiment of the disclosure. 
     First, in the scenario of  FIG.  5   , it is assumed that after the multi-link transmitter  101  divides an i-th data frame into an N number of data sections, the multi-link transmitter  101  sends the N number of data sections of the i-th data frame to the multi-link receiver  310  through the multi-link channel  103 . For ease of description below, it may be assumed that N is 3, and a j-th data section of the i-th data frame is expressed as link_j[i]. Nonetheless, the disclosure is not limited thereto. 
     In step S 410 , the receiving circuit  312  receives the j-th data section belonging to the i-th data frame. After that, in step S 420 , the processing circuit  314  determines a reference delay range of the j-th data section of the i-th data frame according to a preset delay time and a receiving time point of the j-th data section of the i-th data frame. 
     For example, in the scenario of  FIG.  5   , after the receiving circuit  312  receives a data section link_ 2 [ i ] (i.e., the second data section of the i-th data frame), the processing circuit  314  may determine a reference delay range R 2   i  of the data section link_ 2 [ i ] according to a preset delay time R and a receiving time point of the data section link_ 2 [ i ]. 
     In an embodiment, assuming that the preset delay time is R and the receiving time point of the data section link_ 2 [ i ] is T 2   i , then the processing circuit  314  may, for example, take T 2   i  and T 2   i +R as the lower limit and the upper limit of the reference delay range R 2   i  of the data section link_ 2 [ i ]. In different embodiments, designers may select the appropriate value of R as required. 
     In addition, for other data sections of the i-th data frame, the processing circuit  314  may also determine corresponding reference delay ranges for these data sections individually. For example, after the receiving circuit  312  receives a data section link_ 3 [ i ] (i.e., the third data section of the i-th data frame), the processing circuit  314  may determine a reference delay range R 3   i  of the data section link_ 3 [ i ] according to the preset delay time R and a receiving time point of the data section link_ 3 [ i ]. Assuming that the receiving time point of the data section link_ 3 [ i ] is T 3   i , then the processing circuit  314  may, for example, take T 3   i  and T 3   i +R as the lower limit and the upper limit of the reference delay range R 3   i  of the data section link_ 3 [ i ]. 
     After that, in step S 430 , in response to determining that the j-th data section of the i-th data frame is first received among the N number of data sections of the i-th data frame, the processing circuit  314  takes the reference delay range of the j-th data section of the i-th data frame as a designated delay range SR i  corresponding to the i-th data frame. In other words, the processing circuit  314  may find the data section first received by the multi-link receiver  310  among the N number of data sections of the i-th data frame, and then take the reference delay range corresponding to the data section as the designated delay range SR i  corresponding to the i-th data frame. 
     In the scenario of  FIG.  5   , assuming that the data section link_ 2 [ i ] is first received by the multi-link receiver  310  among the N number of data sections of the i-th data frame, then the processing circuit  314  may use the reference delay range R 2   i  of the data section link_ 2 [ i ] as the designated delay range SR i  corresponding to the i-th data frame. In other words, when the data section link_ 2 [ i ] precedes the other data sections (e.g., the data section link_ 3 [ i ]) of the i-th data frame, the processing circuit  314  may define the reference delay range R 2   i  of the data section link_ 2 [ i ] as the designed delay range SR i . 
     In other embodiments, if the data section link_ 3 [ i ] precedes the other data sections (e.g., the data section link_ 2 [ i ]) of the i-th data frame, the processing circuit  314  may define the reference delay range R 3   i  of the data section link_ 3 [ i ] as the designed delay range SR i . Nonetheless, the disclosure is not limited thereto. 
     After that, the processing circuit  314  may determine whether receiving time points of the data sections of the i-th data frame are each within the designated delay range SR i  corresponding to the i-th data frame. 
     In the scenario of  FIG.  5   , it is assumed that a first data section link_ 1 [ i ] (not shown) of the i-th data frame is not received by the receiving circuit  312  for some reason. In other words, the processing circuit  314  fails to obtain a receiving time point of the data section link_ 1 [ i ]. In this case, the processing circuit  314  may determine that the receiving time points of the data sections of the i-th data frame are not each within the designated delay range SR i  corresponding to the i-th data frame. In this case, the processing circuit  314  may ignore the data sections of the i-th data frame, and may not restore the i-th data frame. In addition, the processing circuit  314  may also generate an alarm corresponding to the i-th data frame, so as to record that the i-th data frame is not successfully recombined and restored. 
     In addition, in response to determining that the receiving time points of the data sections of the i-th data frame are each within the designated delay range SR i  corresponding to the i-th data frame, the processing circuit  314  may accordingly perform step S 440 . 
     In step S 440 , in response to determining that the receiving time points of the data sections of the i-th data frame are each within the designated delay range corresponding to the i-th data frame, the processing circuit  314  restores the i-th data frame based on the N number of data sections of the i-th data frame. 
     In an embodiment, assuming that the receiving time points of the data sections link_ 1 [ i ] and link_ 3 [ i ] are each within the designated delay range SR i , the processor  314  may then recombine the data sections link_ 1 [ i ] to link_ 3 [ i ] to restore the i-th data frame. 
     For data sections of other data frames from the multi-link transmitter  101 , the multi-link receiver  310  may also perform corresponding operations based on the above teachings. 
     For example, it is assumed that after the multi-link transmitter  101  divides an i+1-th data frame into an N number of data sections, the multi-link transmitter  101  sends the N number of data sections of the i+1-th data frame to the multi-link receiver  310  through the multi-link channel  103 . For ease of description below, it may be assumed that a j-th data section of the i+1th data frame is expressed as link_j[i+1]. Nonetheless, the disclosure is not limited thereto. 
     In the scenario of  FIG.  5   , the processing circuit  314  may determine corresponding reference delay ranges for data sections link_ 1 [ i+ 1] to link_ 3 [ i+ 1] received by the receiving circuit  312 . For example, after the receiving circuit  312  receives the data section link_ 1 [ i+ 1] (i.e., the first data section of the i+1-th data frame), the processing circuit  314  may determine a reference delay range R 1   i+1  of the data section link_ 1 [ i+ 1] according to the preset delay time R and a receiving time point of the data section link_ 1 [ i+ 1]. Assuming that the receiving time point of the data section link_ 1 [ i+ 1] is T 1   i+1 , then the processing circuit  314  may, for example, take T 1   i+1  and T 1   i+1 +R as the lower limit and the upper limit of the reference delay range R 1   i+1  of the data section link_ 1 [ i+ 1]. Based on a similar principle, the processing circuit  314  may accordingly determine reference delay ranges corresponding to the data sections link_ 2 [ i+ 1] and link_ 3 [ i+ 1]. 
     In the scenario of  FIG.  5   , since the data section link_ 1 [ i+ 1] is first received by the multi-link receiver  310  among the data sections link_ 1 [ i+ 1] to link_ 3 [ i+ 1], the processing circuit  314  may define the reference delay range R 1   i+1  of the data section link_ 1 [ i+ 1] as a designated delay range SR i+1  corresponding to the i+1-th data frame. After that, the processing circuit  314  may determine whether receiving time points of the data sections link_ 1 [ i+ 1] to link_ 3 [ i+ 1] are each within the designated delay range SR i+1 . 
     In  FIG.  5   , since the receiving time points of the data sections link_ 1 [ i+ 1] to link_ 3 [ i+ 1] are each within the designated delay range SR i+1 , the processing circuit  314  may accordingly recombine the data sections link_ 1 [ i+ 1] to link_ 3 [ i+ 1] to restore the i+1-th data frame. 
     In addition, for data sections link_ 1 [ i+ 2] to link_ 3 [ i+ 2] corresponding to an i+2-th data frame, the processing circuit  314  may define a reference delay range R 3   i+2  of the data section link_ 3 [ i+ 2] as a designated delay range SR i+2  corresponding to the i+2th data frame based on the above teachings. After that, the processing circuit  314  may determine whether receiving time points of the data sections link_ 1 [ i+ 2] to link_ 3 [ i+ 2] are each within the designated delay range SR i+2 . Since the receiving time points of the data sections link_ 1 [ i+ 2] to link_ 3 [ i+ 2] are each within the designated delay range SR i+2 , the processing circuit  314  may accordingly recombine the data sections link_ 1 [ i+ 2] to link_ 3 [ i+ 2] to restore the i+2-th data frame. Reference may be to the above embodiments for the relevant details, which will not be repeatedly described herein. 
     In an embodiment, the receiving circuit  312  may also receive an n-th data section belonging to an m-th data frame. The m-th data frame includes an N number of data sections, where 1≤n≤N, m is an index value, and m is greater than i. After that, the processing circuit  314  may determine whether a receiving time point of the n-th data section of the m-th data frame is within the designated delay range SR i  corresponding to the i-th data frame. 
     In an embodiment, in response to determining that the receiving time point of the n-th data section of the m-th data frame is within the designated delay range SR i  corresponding to the i-th data frame, the processing circuit  314  may ignore the data sections link_ 1 [ i ] to link_ 3 [ i ] of the i-th data frame. To make the aforementioned contents easier to understand, further description with the aid of  FIG.  6    will be provided below. 
     With reference to  FIG.  6   ,  FIG.  6    is a diagram of another application scenario according to  FIG.  5   . In  FIG.  6   , it is assumed that the considered value of m is i+1, but is not limited thereto. In this case, after the receiving circuit  312  receives any one of the data sections link_ 1 [ i+ 1] to link_ 3 [ i+ 1], the processing circuit  314  may determine whether any one of the receiving time points of the data sections link_ 1 [ i+ 1] to link_ 3 [ i+ 1] is within the designated delay range SR i  corresponding to the i-th data frame. 
     In the scenario of  FIG.  6   , assuming that the receiving time point (i.e., T 1   i+1 ) of the data section link_ 1 [ i+ 1] is within the designated delay range SR i , then the processing circuit  314  may ignore the data sections link_ 1 [ i ] to link_ 3 [ i ] of the i-th data frame, and may not restore the i-th data frame. In addition, the processing circuit  314  may also generate an alarm corresponding to the i-th data frame, so as to record that the i-th data frame is not successfully recombined and restored. 
     In brief, if a receiving time point of a data section of a following data frame falls into a designated delay range corresponding to a previous data frame, the processing circuit  314  may accordingly ignore data sections of the previous data frame and generate an alarm. Nonetheless, the disclosure is not limited thereto. 
     In other embodiments, in response to determining that the receiving time point of the n-th data section of the m-th data frame is not within the designated delay range SR i  corresponding to the i-th data frame, the processing circuit  314  may determine a reference delay range of the n-th data section of the m-th data frame according to the preset delay time (i.e., R) and the receiving time point of the n-th data section of the m-th data frame. 
     After that, in response to determining that the n-th data section of the m-th data frame is first received among the N number of data sections of the m-th data frame, the processing circuit  314  takes the reference delay range of the n-th data section of the m-th data frame as a designated delay range corresponding to the m-th data frame. Then, in response to determining that receiving time points of the data sections of the m-th data frame are each within the designated delay range corresponding to the m-th data frame, the processing circuit  314  restores the m-th data frame based on the N number of data sections of the m-th data frame. 
     In addition, in response to determining that the receiving time points of the data sections of the m-th data frame are not each within the designated delay range corresponding to the m-th data frame, the processing circuit  314  may ignore the N number of data sections of the m-th data frame. Nonetheless, the disclosure is not limited thereto. Reference may be made to the description in the above embodiments for the relevant details, which will not be repeatedly described herein. 
     With reference to  FIG.  7   ,  FIG.  7    is a schematic diagram of a multi-link receiver according to an embodiment of the disclosure. In  FIG.  7   , the receiving circuit  312  of the multi-link receiver  310  may include a receiving interface  71  and an N number of indicator generators  721  to  72 N. The processing circuit  314  may include an N number of first range determination circuits  731  to  73 N, a determining circuit  76 , a second range determination circuit  74 , and a restoring circuit  75 . 
     In  FIG.  7   , the indicator generators  721  to  72 N respectively correspond to the N number of data sections link_ 1 [ i ] to link_N[i] of the i-th data frame Fi. In an embodiment, the receiving interface  71  is coupled to the indicator generators  721  to  72 N, and after receiving the j-th data section belonging to the i-th data frame Fi from the multi-link transmitter  101 , triggers a j-th indicator generator among the indicator generators  721  to  72 N to generate an indicator. A time when the j-th indicator generator generates the indicator corresponds to the receiving time point of the j-th data section of the i-th data frame Fi. 
     For example, when the receiving interface  71  receives the data section link_ 1 [ i ] (i.e., the first data section of the i-th data frame Fi) from the multi-link transmitter  101 , the receiving interface  71  may trigger the indicator generator  721  (i.e., the first indicator generator among the indicator generators  721  to  72 N) to generate an indicator D 1   i . A generation time of the indicator D 1   i  may correspond to the receiving time point of the data section link_ 1 [ i ]. In addition, when the receiving interface  71  receives the data section link_ 2 [ i ] (i.e., the second data section of the i-th data frame Fi) from the multi-link transmitter  101 , the receiving interface  71  may trigger the indicator generator  722  (i.e., the second indicator generator among the indicator generators  721  to  72 N) to generate an indicator D 2   i . A generation time of the indicator D 2   i  may correspond to the receiving time point (e.g., T 2   i  in  FIG.  5   ) of the data section link_ 2 [ i ]. Furthermore, when the receiving interface  71  receives the data section link_N[i] (i.e., the N-th data section of the i-th data frame Fi) from the multi-link transmitter  101 , the receiving interface  71  may trigger the indicator generator  72 N (i.e., the N-th indicator generator among the indicator generators  721  to  72 N) to generate an indicator DNi. A generation time of the indicator DNi may correspond to the receiving time point of the data section link_N[i]. 
     In  FIG.  7   , the first range determination circuits  731  to  73 N are respectively coupled to the indicator generators  721  to  72 N. In an embodiment, in response to the indicator of the j-th indicator generator, a j-th range determination circuit among the first range determination circuits  731  to  73 N determines the reference delay range of the j-th data section of the i-th data frame Fi according to the preset delay time (i.e., R) and the receiving time point of the j-th data section of the i-th data frame Fi. 
     For example, in response to the indicator D 1   i  of the indicator generator  721 , the first range determination circuit  731  may determine the reference delay range R 1   i  of the data section link_ 1 [ i ] according to the preset delay time (i.e., R) and the receiving time point of the data section link_ 1 [ i ] of the i-th data frame Fi. In addition, in response to the indicator D 2   i  of the indicator generator  722 , the first range determination circuit  732  may determine the reference delay range (e.g., the reference delay range R 2   i  of  FIG.  5   ) of the data section link_ 1 [ i ] according to the preset delay time (i.e., R) and the receiving time point (e.g., T 2   i  in  FIG.  5   ) of the data section link_ 2 [ i ] of the i-th data frame Fi. Furthermore, in response to the indicator DNi of the indicator generator  72 N, the first range determination circuit  73 N may determine a reference delay range RN i  of the data section link_N[i] according to the preset delay time (i.e., R) and the receiving time point of the data section link_N[i] of the i-th data frame Fi. 
     In an embodiment, the determining circuit  76  is coupled to the indicator generators  721  to  72 N, and may find out the earliest generated indicator (which corresponds to the earliest received data section) based on the generation time points of the indicators D 1   i  to DNi (i.e., the receiving time points of the data sections link_ 1 [ i ] to link_N[i]). 
     In an embodiment, in response to determining that the j-th indicator generator generates the indicator before the other indicator generators, the determining circuit  76  may determine that the j-th data section of the i-th data frame Fi is first received among the N number of data sections link_ 1 [ i ] to link_N[i] of the i-th data frame Fi. 
     For example, assuming that the determining circuit  76  determines that the indicator generator  721  generates the indicator D 1   i  before the other indicator generators, then the determining circuit  76  may accordingly determine that the data section link_ 1 [ i ] is first received by the multi-link receiver  310  among the data sections link_ 1 [ i ] to link_N[i] (i.e., the data section link_ 1 [ i ] is received earliest by the multi-link receiver  310  among the data sections link_ 1 [ i ] to link_N[i]). For another example, assuming that the determining circuit  76  determines that the indicator generator  722  generates the indicator D 2   i  before the other indicator generators, then the determining circuit  76  may accordingly determine that the data section link_ 2 [ i ] is first received by the multi-link receiver  310  among the data sections link_ 1 [ i ] to link_N[i] (i.e., the data section link_ 2 [ i ] is received earliest by the multi-link receiver  310  among the data sections link_ 1 [ i ] to link_N[i]). In addition, assuming that the determining circuit  76  determines that the indicator generator  72 N generates the indicator DNi before the other indicator generators, then the determining circuit  76  may accordingly determine that the data section link_N[i] is first received by the multi-link receiver  310  among the data sections link_ 1 [ i ] to link_N[i] (i.e., the data section link_N[i] is received earliest by the multi-link receiver  310  among the data sections link_ 1 [ i ] to link_N[i]). 
     In an embodiment, the second range determination circuit  74  is coupled to the indicator generators  721  to  72 N, and after the determining circuit  76  determines that the j-th data section of the i-th data frame Fi is first received among the N number of data sections link_ 1 [ i ] to link-N[i] of the i-th data frame Fi, takes the reference delay range of the j-th data section as the designated delay range corresponding to the i-th data frame Fi. 
     Taking  FIG.  5    as an example, since the data section link_ 2 [ i ] is determined to be first received by the multi-link receiver  310  among the data sections link_ 1 [ i ] to link_N[i], the second range determination circuit  74  may use the reference delay range R 2   i  of the data section link_ 2 [ i ] as the designated delay range SR i  corresponding to the i-th data frame Fi. 
     After that, the second range determination circuit  74  may determine whether the receiving time points of the data sections link_ 1 [ i ] to link_N[i] of the i-th data frame Fi are each within the designated delay range SR i  corresponding to the i-th data frame Fi. If so, the second range determination circuit  74  may provide a first command C 1  to the restoring circuit  75 , and in the opposite case, the second range determination circuit  74  may provide a second command C 2  to the restoring circuit  75 . 
     In an embodiment, the restoring circuit  75  is coupled to the second range determination circuit  74  and the indicator generators  721  to  72 N, and in response to the first command C 1 , restores the i-th data frame Fi based on the data sections link_ 1 [ i ] to link_N[i] of the i-th data frame Fi. In addition, if the restoring circuit  75  receives the second command C 2  from the second range determination circuit  74 , in response to the second command C 2 , the restoring circuit  75  may ignore the data sections link_ 1 [ i ] to link_N[i] of the i-th data frame Fi and may provide a corresponding alarm ALM. Nonetheless, the disclosure is not limited thereto. 
     In the embodiments of the disclosure, reference may be made to the description in the above embodiments for the details of the operations performed by the first range determination circuits  731  to  73 N, the determining circuit  76 , the second range determination circuit  74 , and the restoring circuit  75 , which will not be repeatedly described herein. 
     In summary of foregoing, in the embodiments of the disclosure, after the multiple data sections belonging to the same data frame are received through multi-link transmission, the designed delay range corresponding to the data frame may be determined using the earliest received one of the data sections. After that, in the embodiments of the disclosure, when it is determined that the data sections belonging to the same data frame are received within the designated delay range, the data sections may be accordingly recombined to restore the data frame. In addition, in the embodiments of the disclosure, if the data sections belonging to the same data frame are not received within the designated delay range, the data sections may be ignored and a corresponding alarm may be provided accordingly. According to the above, the embodiments of the disclosure provide a DDCM mechanism that has a simple architecture and is easy to perform, which can easily achieve management of the differential delay in a multi-link transmission mechanism. 
     It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed embodiments without departing from the scope or spirit of the disclosure. In view of the foregoing, it is intended that the disclosure covers modifications and variations provided that they fall within the scope of the following claims and their equivalents.