Patent Publication Number: US-8975979-B2

Title: Transformer with bypass capacitor

Description:
This application is a continuation of U.S. patent application Ser. No. 12/963,701, filed Dec. 9, 2010, which is expressly incorporated by reference herein in its entirety. 
    
    
     FIELD 
     The disclosed system and method relate generally to transformers and balanced-to-unbalanced (balun) devices. More specifically, the disclosed system and method relate to on-chip symmetrical transformers and balun devices. 
     BACKGROUND 
     A transformer is a device that transfers electrical energy from one circuit to another through inductively coupled conductors—the transformer&#39;s windings. A varying current in the first or primary winding creates a varying magnetic field through the secondary winding. This varying magnetic field induces a varying electromotive force (EMF) or “voltage” in the secondary winding. This effect is called mutual induction. If a load is connected to the secondary winding, an electric current will flow in the secondary winding and electrical energy will be transferred from the primary circuit through the transformer to the load. 
     A balun is a type of transformer that can convert electrical signals that are balanced about ground (differential) to signals that are unbalanced (single-ended) and vice versa. A balun can be formed by connecting one port of a transformer to ground. Baluns are also often used for impedance matching. 
     Transformers and baluns are commonly used in wireless communications. For example, transformers and baluns are frequently used in transceivers in wireless communication devices. Conventional coplanar interleaved transformers used in such applications have the primary and secondary windings interleaved on the same integrated circuit layer. The primary and secondary windings are constructed of planar metal traces. The number of turns in each of the primary and secondary windings determines the ratio of the voltages in the windings. 
     While conventional coplanar transformers reduce the size and resistance, they suffer from low quality (Q) factors. One-turn transformers exhibit a low K (coupling coefficient) for millimeter-Wave circuit applications (for example, in the frequency range of 30 GHz-300 GHz). 
     Additionally, transformers in advanced technology nodes (e.g., 90 nanometer, 65 nanometer, or smaller critical dimensions) have lower Fsr (resonance frequency) than larger technology nodes. 
     Improved transformers are desired. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1A  is an isometric view of an example of a transformer having a generally rectangular shape. 
         FIG. 1B  is a plan view of a transformer having a generally octagonal shape. 
         FIG. 1C  is a top isometric view of another embodiment of the transformer. 
         FIG. 1D  is a bottom isometric view of the transformer of  FIG. 1C . 
         FIG. 2  is a side cross section of the transformer of  FIG. 1A , including metal-insulator-metal (MIM) or metal-oxide-metal (MOM) capacitors. 
         FIG. 3  is a side cross section of the transformer of  FIG. 1A , including metal-oxide-semiconductor capacitors, 
         FIG. 4  is a schematic diagram of the transformer of  FIG. 1A . 
         FIG. 5  is a schematic diagram of a variation of the transformer of  FIG. 4 . 
         FIG. 6  is a schematic diagram of a transceiver that includes the transformer of  FIG. 1A . 
         FIG. 7  is a schematic diagram of a receiver including the transformer of  FIG. 1A . 
         FIG. 8  is a schematic diagram of a voltage controlled oscillator (VCO) including the transformer of  FIG. 1A . 
         FIG. 9  is a flow chart of a fabrication method including MOS capacitor formation. 
         FIG. 10  is a flow chart of a fabrication method including MIM/MOM capacitor formation. 
     
    
    
     DETAILED DESCRIPTION 
     This description of the exemplary embodiments is intended to be read in connection with the accompanying drawings, which are to be considered part of the entire written description. In the description, relative terms such as “lower,” “upper,” “horizontal,” “vertical,”, “above,” “below,” “up,” “down,” “top” and “bottom” as well as derivative thereof (e.g., “horizontally,” “downwardly,” “upwardly,” etc.) should be construed to refer to the orientation as then described or as shown in the drawing under discussion. These relative terms are for convenience of description and do not require that the apparatus be constructed or operated in a particular orientation. 
       FIG. 1A  is an isometric view of an electronic device, which is a transformer or balun  100  for an integrated circuit (IC). The transformer/balun  100  has coils L 1 , L 2  and L 3  formed in a single-layer providing a coplanar symmetric transformer  100  having a 1:1 turn ratio. The transformer/balun  100  can be incorporated into IC designs without requiring changes to the process flow (e.g., CMOS process) or additional masks. 
     As shown in  FIG. 1A , the transformer  100  includes a primary winding L 13  and a secondary winding L 2 , which are both located on the same metal layer. This metal layer is referred to below as the “first metal layer”. It will be understood that in this description, any reference to the first metal layer is a general reference to the layer in which the windings L 1 , L 2 , L 3  are formed, and is not a specific reference to the M 1  metal layer. Similarly, any reference to a “second metal layer” is not a specific reference to the M 2  metal layer, but merely denotes one of the metal layers, other than the layer in which the windings L 1 , L 2 , L 3  are formed. 
     The primary winding L 13  comprises a first winding segment (or coil) L 1  and a second winding segment (or coil) L 3 . The first winding segment L 1  is adjacent a first portion of the second winding L 2 . The second winding segment L 3  is adjacent a second portion of the second winding L 2 . 
     One of the first L 1  and second L 3  segments of the first winding L 13  has a conductive connection to the second winding L 2  in the first metal layer, and the other of the first L 1  and second L 3  segments has a conductive connection to the second winding L 2  at least partially in a second metal layer other than the first metal layer. For example, in  FIG. 1A , the segment L 1  is connected to the secondary winding (or coil) L 2  by metal bridge B 2  formed on a separate metal layer and connecting vias (not shown in  FIG. 1A ). The segment L 3  is connected to the secondary winding L 2  by metal bridge B 1  formed on the same metal layer as the primary winding L 13  and secondary winding L 2 . In other embodiments, B 2  is formed in the same layer as the coils L 13  and L 2 , and B 1  is formed in another layer. 
     In the example of a 1:1 single turn device  100 , the secondary winding L 2  is comprised of a single segment, formed on the same metal layer as the segments L 1  and L 3  comprising the primary winding L 13 . In some embodiments, an optional center tap CT 1  is provided in the second winding L 2 . 
     The first L 1  and second L 3  winding segments each extend about halfway around the second winding L 2  on opposite sides of the second winding. The length of the first segment L 1  overlapping the second segment L 2  is slightly less than 0.5 the length of second segment L 2 , to provide a spacing between ports P 3  and P 4 , and a space between P 1  and P 2 . Similarly, the length of the second segment L 3  overlapping the second segment L 2  is slightly less than 0.5 the length of second segment L 2 . In some embodiments, L 2  is slightly smaller than the sum of L 1  and L 3 . For example the ratio L 2 /(L 1 +L 3 ) may be in the range from about 75% to about 95% due to the spacings between each of the turns. And L 1  may be equal to or different from L 3 . In some embodiments, L 1  differ from L 3  because of the location of the capacitors C 1  and C 2 . 
     Although the windings L 13  and L 2  of  FIG. 1A  are square in shape, the coils may have other shapes. For example,  FIG. 1B  shows a variation of the topology in which each winding L 13  and L 2  is octagonal. Components in  FIGS. 1A and 1B  having the same function are indicated by the same reference numeral (although performance may differ between these shapes). In some embodiments, winding L 13  is the primary winding, and L 2  is the secondary. In other embodiments, L 13  is the secondary winding and L 2  is the primary. 
       FIG. 4  is a schematic diagram of the transformer/balun  100  of  FIG. 1A ,  1 B or  1 C. The electronic device comprises first (L 1 ), second (L 2 ) and third (L 3 ) inductors connected in series and formed in a metal layer over a semiconductor substrate (shown in  FIG. 2 ). The first L 1  and second L 2  inductors have a mutual inductance with each other, designated M. The second L 2  and third L 3  inductors also have a mutual inductance with each other, designated M. The mutual inductance M is tunable by varying C 1  and/or C 2 , since the ratio of (k/M) is a fixed value for given inductance values of L 13  and L 2 . A first capacitor C 1  has a first electrode connected to a first node N 1 . The first node is conductively coupled between the first L 1  and second L 2  inductors. A second capacitor C 2  has a second electrode connected to a second node N 2 . The second node N 2  is conductively coupled between the second L 2  and third L 3  inductors. 
     The second winding L 2  is coupled between a first port P 1  of the device  100  and a second port P 2  of the device. The first capacitor C 1  is coupled between the second winding L 2  and the first port P 1 . The second capacitor C 2  is coupled between the second winding L 2  and the second port P 2 . The device  100  has a third port P 3  and a fourth port P 4 . The first winding segment (coil) L 1  is coupled between the first node N 1  and the third port P 3 . The second winding segment L 3  is coupled between the second node N 2  and the fourth port P 4 . 
     The coil L 2  is included in both the first and second windings of the transformer. Additionally, there is mutual inductance between the first winding L 13  and the second winding L 2 . This configuration allows the RF signals to pass directly from the first winding P 1 -L 2 -P 2  to the second winding P 3 -L 1 -L 2 -L 3 -P 4  by a real metal connection, as opposed to just by mutual coupling. Thus, there is an RF path from each port to each other port. By using a relatively large capacitor, this configuration provides capacitive coupling for DC blocking. 
       FIGS. 1C and 1D  show an alternative embodiment of a transformer  150  having three turns. Although the layout of transformer  150  differs from that of  FIG. 1A , transformer  150  is represented by the same schematic diagram in  FIG. 4  (described above), and corresponding elements are represented by like reference numerals. In  FIGS. 1C and 1D , the first segment L 1  and second segment L 3  of the first winding are each about 0.75 turns (270 degrees), and the second winding L 2  is 1.5 turns (540 degrees). Thus, L 1  includes about 0.5 turn in the outer turn and about 0.25 turn in the middle turn. Similarly, L 3  includes about 0.5 turn in the outer turn and about 0.25 turn in the middle turn. L 2  includes the full inner turn and about 0.5 turn in the middle turn. As best seen in  FIG. 1D , two additional bridge segments B 3  and B 4  in the first and second metal layers, respectively, provide additional connections between the portions of the second winding L 2  in the middle turn and the portions of L 2  in the inner turn. Additional Vias V are provided to connect the bridge segment B 4  to the L 2  portions in the middle and inner turns. One of ordinary skill can readily design other layouts having any desired number of turns (e.g., four, six or eight turns) according to the schematic of  FIG. 4 , or the schematic of  FIG. 5 , discussed below. 
       FIG. 5  is a schematic of a variation of the transformer of  FIG. 4 , in which a fourth coil L 4  connects a third node N 3  to a fourth node N 4 . The third node N 3  is between the first capacitor C 1  and the first port P 1 , and the fourth node N 4  is between the second capacitor C 2  and the second port P 2 . The fourth coil L 4  may optionally be included for providing a DC current path between P 1  and P 2  in the first winding, so that only AC current passes through the second winding. 
     In other embodiments, optional additional inductors (not shown) are provided between ports P 1  and P 2 , and between ports P 3  and P 4 , to provide a DC current path. 
     In some embodiments, L 1  is the same as L 3 , where, L 1 , L 3  are both approximately half of the outer turn (turns) and L 2  is the inductor of inner turn (turns). For example, using the configuration of  FIG. 1A , in a 60 GHz application, L 1 +L 2 +L 3  may be around 80 nH˜100 nH. In other embodiments (or if designed for use at other frequencies) L 1 , L 2 , L 3  might differ because of the layout shape. The capacitance of C 1 , C 2  is dependent on the varactor/MIM/MOM used. L 4  could be small around 80 pH˜100 pH for 60 GHz application. For example, In one embodiment, L 1 =L 3 =35 pH and L 2 =28 pH, L 4 =80 pH, C 1 =C 2 =2 pF. In other embodiments, the inductors and capacitors have larger or smaller values. 
     Alternatively, for operation at a lower frequency (e.g., 17 GHz), the inductances and capacitances may be L 1 =L 3 =115 pH, L 2 =97 pH. C 1 =C 2 &gt;1 pF. L 4 =97 pH. A transformer having these components could be substituted into a voltage controlled oscillator, such as a VCO described in Alan W. Ng et al, “A 1V 17 GHz 5 mW Quadrature CMOS VCO based on Transformer Coupling”, 2006 IEEE International Solid-State Circuits Conference, IEEE 2006, which is incorporated by reference herein in its entirety. 
     In some embodiments, the transformer  100  are tuned to have a different inductance by changing coil length and/or the spacing between turns. By varying the values of C 1 /C 2 , the input/output impedance, inductance and K value of this transformer are changed. 
     Although the examples discussed above include two capacitors C 1  and C 2 , in other embodiments, only one of the two capacitors is included, and the other one of the two capacitors is omitted. 
       FIG. 2  is a cross sectional view of the transformer/balun  100 . Referring to  FIG. 2 , the coils L 1 , L 2  and L 3  of transformer/balun  100  are formed in a metal layer above a semiconductor substrate  102 . For example, the substrate  102  may have a plurality of back-end-of-line (BEOL) interconnect layers, comprising inter-metal-dielectric (IMD) material  104  with several metal layers M 1 -M T  and via layers V 1 -V T  formed therein. In some embodiments, the transformer coils L 1 , L 2 , L 3  are formed in the metal-5 (M 5 ) or metal-6 (M 6 ) layer of the interconnect structure. In other embodiments, the coils L 1 , L 2  and L 3  may be formed in another metal layer. 
     In the embodiment of  FIG. 2 , the capacitors C 2  and C 1  (shown in  FIG. 4 ) are either metal-insulator-metal (MIM) capacitors or metal-oxide-metal (MOM) capacitors. 
     A MIM capacitor is formed between two metal layers, and has a thicker insulation layer with a higher dielectric constant (e.g., a silicon nitride layer). A MIM capacitor may provide a more accurate capacitance value. A MOM capacitor can use a silicon oxide layer as its dielectric, and has a thinner insulating layer. A MOM capacitor may occupy a smaller area for a given capacitance. One of ordinary skill can readily select an appropriate MIM or MOM capacitor for any given transformer design. 
       FIG. 2  shows the capacitor C 2  formed with its top electrode over one of the metal layers M N  and connected to the second segment L 3  (of the first winding L 13 ) and the second winding L 2  by way of vias in the V N  layer. Similarly, the bottom electrode of capacitor C 2  is formed in the metal layer M N , and is connected to the port P 2  by way of vias in the V N  layer. 
     In the embodiment of  FIG. 3 , the capacitors C 2  and C 1  (shown in  FIG. 4 ) are metal-oxide-semiconductor (MOScap) capacitors or varactors. Thus, the capacitor dielectric D is formed in the gate insulation layer, and the capacitor top electrode E T  is formed in the gate electrode (poly) layer. A plurality of contacts CO connect the capacitors C 1 , C 2  to the metal patterns in the interconnect layers M 1 -M T . Alternatively, the adjustable capacitors C 1 , C 2  may be any capacitor formed by the OD, the poly layer and the contact. The remaining connections in the BEOL layers between the capacitors and the ports P 1  and P 2  are determined in conjunction with the routing of the BEOL lines and vias for other circuit devices. 
     Because the capacitors C 1 , C 2  in  FIG. 3  are varactors, the thickness of the depletion zone varies with the applied bias voltage, so the capacitance can be varied. By varying the capacitance of C 1  and C 2 , the coupling coefficient k and the self-reflectance S 11  can also be adjusted. 
       FIG. 3  shows the capacitor C 2  formed with its top electrode E T  in the poly layer connected to the second segment L 3  (of the first winding L 13 ) and the second winding L 2  by way of vias in the V N  layer. The bottom electrode of capacitor C 2  is formed in the N well and is connected to the port P 2  by way of contacts CO, conductive patters in the metal layers and conductive vias in the via layers. Although  FIG. 3  only shows two of the metal layers M N-1  and M N , any number of metal layers may be included in the interconnect. 
     SPICE simulations were performed using the same winding configuration shown in  FIG. 1A , with different values of C 1  and C 2  from 0.5 to 25 picofarads, as well as a transformer without the capacitors C 1 , C 2 . Without the capacitors C 1 , C 2 , the coupling coefficient k ranged from about 0.4 to about 0.6 (depending on frequency). With the decoupling capacitors C 1 , C 2 , the coupling coefficient was at least about 0.78 throughout the frequency range up to 80 GHz, and a some frequencies approached 1.0. The Q value is also improved. In general, the smaller capacitance values provided higher k values. The increase in k of about 0.4 is achieved without increasing the area (footprint) of the transformer. At the same time, the real impedance of the coils L 1 , L 2 , L 3  is unchanged, so that the loss of the device is substantially the same when tuning the capacitance. 
     Although  FIG. 2  shows an embodiment in which capacitors C 1 , C 2  are all MIM or MOM capacitors, and  FIG. 3  shows an embodiment in which the capacitors are all MOScaps, other embodiments include a combination of varactor and MIM or MOM capacitors. For example, one or both of the capacitors C 1 , C 2  may include a MIM or MOM capacitor in parallel with a varactor, so the capacitance has a fixed component and a variable component. This allows a large capacitance with fine tuning capability. 
     Any of the transformers shown in  FIGS. 1A ,  1 B,  4  and  5  may be implemented using MIM or MOM capacitors as shown in  FIG. 2 , or with MOScap varactors as shown in  FIG. 3 . 
     Although  FIGS. 2 and 3  show the capacitors C 1 , C 2  directly under the coils L 1 , L 2 , L 3 , the physical location of the capacitors may vary, to accommodate the other devices and wirings of the IC. However, a surface mounted device (SMD) capacitor or capacitor produced by packaging method (e.g., the capacitor is formed or mounted on the package substrate or formed by a related method, such as a through-silicon via, TSV, process.) may also be used to provide C 1  and C 2 . For example, a TSV process a package solution that takes the place of bond wires. However, a TSV substrate mounted by micro-bumps with decoupling capacitors inside the inter-metal layers, may be used to provide the capacitors. 
       FIG. 9  is a flow chart of a method for forming the transformer  100 , using MOS capacitors. One of ordinary skill in the art is familiar with the basic CMOS process, and the basic steps are not described in detail herein. 
     A method for forming the IC includes first forming the active devices (transistors, diodes). At step  900 , the gate insulation layer is deposited over the substrate. 
     At step  902 , the dielectric layers of the first and second capacitors C 1 , C 2  are formed, during gate insulating layer patterning step. 
     At step  904 , the gate polysilicon layer is deposited. 
     At step  906  the capacitor top electrodes are formed during the gate electrode polysilicon patterning step. 
     At step  908 , the contacts CO are then formed. 
     At step  910 , the interconnect structure is formed. The connections between the contacts CO and the windings L 13  and L 2  are formed using conductive lines and vias in the various interconnect layers M 1 -M T  and V 1 -V T . The top electrode of the first capacitor C 1  is thus connected to the first node N 1 , which is to be conductively coupled between the first segment L 1  and the second coil L 2 . Similarly, the top electrode of the second capacitor C 2  is thus connected to the second node N 2 , which is to be conductively coupled between the second segment L 3  and the second coil L 2 . 
     At step  912 , while forming the interconnect layers, the bridge structures connecting the first winding L 13  and the second winding L 2  are formed. One of the first coil L 1  and the third coil L 3  has a connection to the second coil L 2  in a second metal layer (different from the first metal layer in which the coils L 1 , L 2  and L 3  are formed). This connection may be made through the metal and via layers below the first layer. Thus, at least one conductive line B 2  is formed in at least a second metal layer M N  between the substrate  102  and the first metal layer (which contains coils L 1 , L 2 , L 3 ). Then a plurality of conductive vias are formed in at least one via layer V N  to connect the bridge pattern B 2  to the second coil L 2  and one of the coils L 1  and L 3 . At least one of the vias contacts the at least one conductive line and the second coil L 2 , and at least one of the vias contacts the at least one conductive line and the one of the coils L 1 , L 3 . 
     At step  914 , the coils L 1 , L 2  and L 3  are formed in the first metal layer, with vias providing a conductive connection to the bridge pattern B 2 , and the connections from nodes N 1  and N 2  to the capacitors. 
       FIG. 10  is a flow chart of an exemplary method if MIM or MOM capacitors are used. At step  1000 , front-end-of-line (FEOL) processing is performed, including the active device layers and the first IMD layer. The active device layers are formed. 
     At step  1002 , the interconnect structure is formed, including lines in metal layers and conductive plugs in via layers. 
     At step  1004 , during interconnect structure processing, the capacitors C 1 , C 2  are formed within the interconnect structure (e.g., at the M 5  and M 6  layers). 
     At step  1006 , during interconnect structure processing, the connections between the capacitors and the windings L 13  and L 2  are also formed using conductive lines and vias in the various interconnect layers M 1 -M T  and V 1 -V T . Bridge patterns are formed to connect L 1  and L 2  in a second metal layer. 
     At step  1008 , the inductors L 1 , L 2  and L 3  are formed in the first metal layer. 
       FIGS. 6 ,  7  and  8  include non-limiting examples of circuits into which a transformer/balun  100  as described herein can be substituted.  FIG. 6  is a block diagram of a transceiver  300  that includes the transformer of  FIG. 1A , used as a matching network  100   a  and as a balun ( 100   b - 100   d ) to convert differential signals to single-ended signals. In  FIG. 6 , the transformer  100  is substituted for transformers shown in a transceiver described in Yoichi Kawano, et al., “A 77 GHz Transceiver in 90 nm CMOS” 2009 International Solid State Circuit Conference, IEEE 2009, which is incorporated by reference herein in its entirety. 
       FIG. 7  is a schematic diagram of a receiver  400  into which the transformer of  FIG. 1A  is substituted. In the receiver  400 , the second winding L 2  has: a first center tap connecting the second winding to ground, and a second center tap connecting the second node to VDD. For RF signals, VDD is also an AC ground. Thus, P 3  and P 4  are for the DC loop side; and P 1  and P 2  are only for RF signals. The remaining components of the receiver  400  are described in Daquan Huang et al., “A 60 GHz CMOS Differential Receiver Frong-End Using On-Chp Transformer for 1.2 Volt Operation with Enhanced Gain and Linearity,” 2006 Symposium on VLSI Circuits Digest of Technical Papers, IEEE 2006, which is incorporated by reference herein in its entirety. 
       FIG. 8  is a schematic diagram of a voltage controlled oscillator (VCO)  500  into which the transformer of  FIG. 1A  is substituted. In  FIG. 8  the transformer inputs P 1 , P 2  provide the divider outputs, and P 3  and P 4  are connected to the oscillator inputs. As in the example of  FIG. 7 , two center taps are provided. One center tap is connected to a 1.0V reference and is connected to P 3  and P 4 , and provide a DC current to drive the circuit. The other center tap connects P 1  or P 2  to ground. The remaining components of the VCO  500  are described in Takahiro Nakamura et al. “A 20-GHz 1-V VCO with Dual-Transformer Configuration and a Pseudo-Static Divider on Self-Stabilized Concept,” IEEE 2009, which is incorporated by reference herein in its entirety. 
     One of ordinary skill will recognize that these are only examples, and that the transformers described herein have many different applications. 
     In some embodiments, an electronic device comprises a first winding formed in a first metal layer above a semiconductor substrate, the first winding having first and second segments. A second winding is formed in the first metal layer. The first segment is adjacent a first portion of the second winding. The second segment is adjacent a second portion of the second winding. A first capacitor has a first electrode connected to a first node. The first node is conductively coupled between the first segment and the second winding. A second capacitor has a second electrode connected to a second node. The second node is conductively coupled between the second segment and the second winding. 
     In some embodiments, an electronic device comprises first, second and third inductors connected in series and formed in a metal layer over a semiconductor substrate. The first and second inductors have a mutual inductance with each other. The second and third inductors having a mutual inductance with each other. A first capacitor has a first electrode connected to a first node. The first node is conductively coupled between the first and second inductors. A second capacitor has a second electrode connected to a second node. The second node is conductively coupled between the second and third inductors. 
     In some embodiments, a method comprises forming a first coil, a second coil and a third coil in a first metal layer above a semiconductor substrate. The first coil is adjacent a first portion of the second coil. The third coil is adjacent a second portion of the second coil. A first capacitor is formed having a first electrode connected to a first node. The first node is conductively coupled between the first and second coils. A second capacitor is formed having a second electrode connected to a second node. The second node is conductively coupled between the second and third coils. 
     The transformers/baluns described herein solve the tradeoff between the coupling coefficient k and high resonance frequency. High values of k and Fsr can both be achieved, even for advanced technology nodes (with smaller critical dimensions such as mm wave). 
     Further the k value and mutual inductance M could be tunable, by using a varactor for the capacitors C 1 , C 2 . Further by tuning the capacitance, the reflectance parameter S is also tunable. Thus the transformer has applications for VCO and/or impedance matching. The transformer can be applied in higher frequency ranges for tuning mutual inductance. The transformer can advantageously be used for a transceiver, and may be injected from an antenna. Further, the transformer may be used for impedance matching, or as a band pass filter. 
     A circuit incorporating the transformer described herein as a balun (one port connected to ground) does not require a separate ESD protection circuit. The ESD is sinked to ground because one of the inductors is connected to the ground. 
     Although an example is provided above in which the primary winding L 13  has a single turn and the secondary L 2  has a single turn, in other embodiments, the primary and/or secondary may have more than one turn in the first metal layer, with additional bridges between turn segments of the first or second winding by way of vias and line patterns in the second (or another) metal layer. 
     Although the subject matter has been described in terms of exemplary embodiments, it is not limited thereto. Rather, the appended claims should be construed broadly, to include other variants and embodiments, which may be made by those skilled in the art.