Patent Publication Number: US-8125262-B2

Title: Low power and low noise switched capacitor integrator with flexible input common mode range

Description:
CROSS REFERENCE TO RELATED APPLICATION 
     This application claims priority under 35 U.S.C. §119 to U.S. Provisional Patent Application No. 61/235,226, filed Aug. 19, 2009 and entitled “Low Power and Low Noise Switched Capacitor Integrator with Flexible Input Common Mode Range,” which is herein incorporated by reference in its entirety. 
    
    
     BACKGROUND 
     Demand for low power electronic devices continues to grow. Circuit designers are increasingly lowering the power provided to electronic devices. However, lower power may have an adverse effect on the dynamic range of components of an electronic device. For example, if an amplifier or comparator device is powered by a lower supply voltage (e.g., 1.8 volts), or lower current supply it limits the range of input signals that can be applied to the device. In order to compensate for the lower power supply in an integrator circuit, for example, a feedback capacitor may need to be larger to accept higher input currents with such a low supply voltage. However, the larger feedback capacitor makes the integrator gain lower and, when the input current signal is lower, the output signal may not be large enough to be detected by a following stage. 
     Output noise may also be generated, for example, due to the thermal characteristics of the electrical components (e.g., transistors) of the amplifiers used in the electronic devices, such as integrators. The noise may be propagated upstream thereby causing unacceptable output noises. 
     Circuits that perform integration functions are known in the art as integrators. In a conventional integrator as shown in  FIG. 1 , the input current I IN  is integrated across the capacitor C FB . In other words, as I IN  changes over time, the voltage V OUT  changes inversely to the input current signal. 
     In more detail, when reset switch SW RESET  is CLOSED, the feedback capacitor C FB  is discharged, the voltage V IN  at the integrator input and output voltage V OUT  are reset to equal V REF  by the response of the amplifier A 1  (after reset V IN =V REF =V OUT ). 
     When integrating, the reset switch SW RESET  is OPEN, and the input signal I IN  is applied to the integrator input briefly causing voltage V IN  to fluctuate from voltage V REF . The amplifier A 1  responds to this fluctuation by outputting a signal to V OUT , so V IN  will return to the value V REF . At any time T during integration, the output voltage V OUT  may be approximately equal to V REF −(I IN *T/C FB ), where T is the time while integrating the current signal I IN . 
     Generally, the amplifier A 1  outputs an amplified voltage V OUT  proportional to the difference between V REF  and V IN . However, the amplified voltage output by the amplifier A 1  is limited by power supply voltage V DD  to the amplifier A 1 . Amplifier A 1  cannot output a voltage higher than V DD  or lower than ground as shown in  FIG. 1 . In other words, V OUT  will not be greater than V DD . 
     As mentioned above, circuit designers aim to design circuits having low power and low noise, e.g., thermal noise. The circuit designs require a tradeoff between low power and higher noise, because larger supply current is needed for reducing thermal noise associated with transistors within the amplifiers. Additionally, an external sensor, which may be the input current source I IN , may require higher voltage potentials for proper bias conditions. In the conventional integrator, such as those used in imaging applications, the input current is integrated over time and a representative output voltage is provided. Noise introduced by the amplifiers into the output voltage will be propagated to further devices. Therefore, it is desirable to reduce the amount of noise introduced by the amplifiers of the integrator. 
     Noise from amplifiers may result from higher temperatures. The higher temperature (for example, approximately 85 degrees C.) can increase thermal noise. One method of reducing thermal noise is to raise the supply current provided by the voltage source of V DD . The lower power consumption of the amplifier by using a lower supply voltage also results in lower noise due to a reduced temperature of the amplifier. 
     One known attempt to address this problem has been to put amplifiers in series as shown in  FIG. 2 . The integrator of  FIG. 2  includes a low noise amplifier (LNA) A 1 , a second amplifier A 2 , and a feedback capacitor C FB . The LNA A 1  that is coupled to a reference voltage V REF  on a first input and a current source I IN  on a second input. The voltage at the second input is labeled V IN . The LNA A 1  is powered by a voltage source V DDL . The second amplifier A 2  (not necessarily a low noise amplifier) has inputs coupled to the outputs of LNA A 1 , and is powered by a second voltage source V DDH . The feedback capacitor C FB  is connected to an output of the second amplifier A 2  and the V IN  node. 
     While amplifier A 2  may be a transconductance amplifier. However, the noise contribution of amplifier A 2  is divided by the gain of amplifier A 1 . Therefore, the noise generated by amplifier A 2  is not as problematic. Noise generated by amplifier A 1  may be propagated through to V OUT . The gain of amplifier A 1  may be between 5 and 20. The power supply voltage V DDL  may be less than 5 volts. 
     In contrast to amplifier A 1 , amplifier A 2  may be allowed to be a higher noise source by having a lower supply current and a higher supply voltage V DDH , which may be equal to or greater than 5 volts. The configuration shown in  FIG. 2  realizes lower power, and lower noise with a wider dynamic range than the conventional integrator of  FIG. 1 . However, the input common mode range, represented by V IN , is limited to a lower input potential because the amplifier A 1  is supplied with a lower supply voltage V DDL . 
     Since the supply voltage V DDL  of amplifier A 1  is low, the reference voltage V REF  must be either equal to or less than V DDL . In the integrator shown in  FIG. 2 , the input common mode range V IN  is dependent upon the value of V REF , which is limited by Supply voltage V DDL . Due to this limitation, the above configuration may not be suitable for use when the input voltage V IN  and the reference voltage V REF  need to be higher. For example, when input current source I IN  is an external sensor that requires higher potential for its proper bias condition, the integrator confirmation of  FIG. 2  that supplies the input current signal may not be appropriate. 
     The input device I IN  may be a customer device, such as a photodiode. A photodiode typically supplies between 0-5 volts. If 5 volts is applied to amplifier A 1 , V DDL  would have to supply at least that amount of voltage, which would result in higher power consumption of the circuit. In addition, the noise associated with amplifier A 1  may be dominated by thermal noise. The thermal noise of amplifier A 1  may be reduced if more supply current is consumed. Therefore, in order for amplifier A 1  to achieve both low power consumption and low noise, less voltage and more supply current, respectively, is needed to be supplied from V DDL . 
     Accordingly, another more flexible solution is needed. There is a need for a low power, low noise integrating device that provides acceptable bias conditions. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  illustrates a conventional integrator circuit. 
         FIG. 2  illustrates a conventional multi-stage integrator circuit. 
         FIG. 3  illustrates an exemplary circuit diagram according to an embodiment of the invention. 
         FIG. 4  illustrates an exemplary implementation of a pre-amplifier stage of an embodiment of the present invention. 
         FIG. 5  illustrates an exemplary implementation of a multipath amplifier stage of an embodiment of the present invention. 
         FIG. 6  illustrates an exemplary application according to an embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION 
     Embodiments of the present invention provide an integrator configuration that may include a level-shifting capacitor, a feedback capacitor, a switch module, a pre-amplifier stage and a multi-path amplifier module. The integrator may have inputs for connecting an input signal source to the level-shifting capacitor. The level-shifting capacitor may be connected to an input of a pre-amplifier stage of an integration signal path and to an input of the integrator circuit. The level-shifting capacitor may level shift the voltage at the input of the integrator circuit to a lower voltage at the input of the pre-amplifier stage. Thereby, the supply voltage to the pre-amplifier stage may be reduced as well as limiting power consumption, limiting temperature rise, and reducing noise attributed to any thermal effects on the amplifier. 
       FIG. 3  illustrates an exemplary circuit diagram according to an embodiment of the invention. The integrator  300  may include a pre-amplifier stage  310 , a level-shifting capacitor C LS    307 , a feedback capacitor C FB    303 , a multi-path amplifier module  320 , and a reset switches  323 A and  323 B. Reset switches  323 A and  323 B may be implemented using transistors. 
     The pre-amplifier stage  310  may include an amplifier  313 . The amplifier  313  may be a low noise amplifier, which may be characterized by a high supply current. In addition, the amplifier  313  can have a low thermal noise voltage density of about 2 nV/sqrt(Hz). The amplifier  313  may have a first input, a second input, a power supply input terminal, and a pair of outputs (a first output and a second output). The first input may be connected to a terminal of level shift capacitor C LS    307  and a first terminal of reset switch  323 A. The second input may be connected to a pre-amplifier stage reference voltage source V REF-LO  and to a second terminal of reset switch  323 A. The power supply input terminal may be connected to voltage source V DDL , which may be in the pre-amplifier stage  310  or may be an external voltage source. The pair of outputs may be connected to inputs of the amplifier module  320 . The pair of outputs may be differential outputs. 
     Multi-path amplifier module  320  may include a first amplifier A INT  and second amplifier A RESET . Amplifier A INT  may have inputs connected to A 1  the outputs of pre-amplifier stage  413 , a power supply input connected to voltage source V DDH , and an output connected to V OUT , the second terminal of feedback capacitor CFB  303  and second terminal of reset switch  323 B. 
     The supply voltage V DDL  to the pre-amplifier stage  310  may be lower than the supply voltage V DDH  to the multi-path amplifier module  320 . A higher input voltage up to the value of supply voltage V DDH  may be applied to the integrator  300 , while still utilizing the lower supply voltage V DDL  for the pre-amplifier  310 . Being able to use the lower supply voltage V DDL  may be facilitated by the inclusion of the level-shifting capacitor C LS    307  that reduces the input voltage to the pre-amplifier  310 . For example, the supply voltage V DDH  may be 5 volts, while the supply voltage V DDL  may be 1.8 volts. The supply voltage V DDL  may be lower than the input voltage V IN . The input voltage V IN  may be 4-5 volts. Generally, this allows supply voltage V DDL  to be set independent of V IN . 
     The level shifting capacitor C LS    307  may be connected to a first terminal of feedback capacitor C FB    303 , to reset switch  323 B and an input in the reset circuit path to amplifier A RESET  of the amplifier module  320 . The capacitor C LS    307  may also be connected to a signal input of the pre-amplifier stage  310  and reset switch  323 A. 
     The feedback capacitor C FB    303  may be connected to a first terminal of reset switch  323 B, the first terminal of level-shifting capacitor C LS    307 , and an input in the reset circuit path to amplifier A RESET  of the amplifier module  320 . Capacitor CFB  303  may also be connected to both the output V OUT  of amplifier module  320  and to a second terminal of the reset switch  323 B. As shown in  FIG. 3 , the reset switch  323 B is connected in parallel to the feedback capacitor C FB    303 . 
     Referring back to the multi-path amplifier module  320 , the inputs INP 1 /INN 1  of amplifier A INT  may receive respective differential signals output from amplifier  313  of the pre-amplifier stage  310 . 
     Amplifier A INT  may be a transconductance amplifier, and may have different circuit parameter than amplifier A RESET  because A INT  may have, for example, different electrical requirements. 
     Amplifier A RESET  may have its inputs connected to V REF-HI  and V IN , respectively; a power supply input connected to voltage source V DDH ; and an output connected to V OUT . The inputs INP 2 /INN 2  of amplifier A RESET  may receive respective signals V REF-HI  and V IN . Amplifier A RESET  may also be a transconductance amplifier. 
     The outputs of the amplifier A INT  and the amplifier A RESET  may be connected together at V OUT . The combined gain of the pre-amplifier  310  and amplifier A INT  may be greater than the gain of amplifier A RESET . 
     Amplifier power supply voltages V DDL  and V DDH  may be provided from external sources to facilitate the programmability of the integrator  300 . Optionally, voltage sources V DDL  and V DDH  may either be included in integrator  300  or externally, and have pre-determined settings or programmable settings. In either case, V DDL  may be set independent of the input signal source I IN    350  and its related V IN . 
     The foregoing embodiments permit the amplifier power supply voltages V DDL  and V DDH  to be set at different levels. The power supply voltage V DDL  may be set lower than V DDH . The configuration of the forgoing embodiments may provide a designer with the capability to set the integrator&#39;s input bias voltage independent of the power supply voltage V DDL  for the pre-amplifier stage thereby effectively balancing the need for a sufficiently high output voltage with the need for reduced power consumption and reduced noise characteristics. 
     In an embodiment, the reference voltage V REF-LO  may have a value of approximately 1.0 volt and reference voltage V REF-HI  can have a value as high as approximately 5 volts. The multipath amplifier  320  may have inputs INN 1  and INP 1  connected to outputs of the pre-amplifier  310 , and inputs INN 2  and INP 2  connected, respectively, to the input  390  of the integrator  300  and a reference voltage V REF-HI . 
     The integrator  300  may operate in either a reset mode or an integration mode. When in reset mode, the switches  323 A and  323 B may be CLOSED, and the circuit  300  resets the input voltage V IN  to reference voltage V REF-HI , and the voltage at the input of the pre-amplifier stage  310  may be reset to reference voltage V REF-LO . The capacitor C FB    303  may be discharged because of the short circuit created by the closed switch  323 B. The inputs to the pre-amplifier stage  310  are shorted, so amplifier  313  does not have an appreciable output, and the voltage at the inverting input of amplifier  313  may be reset to V REF-LO . Also at reset, the capacitor C LS    307  is charged to a value of V CLS , which may be equal to V REF-HI  minus V REF-LO . After completion of the above operations, the integrator  300  is now reset to integrate the next input signal. 
     In integration mode, the switches  323 A and  323 B are OPEN, and the integrator  300  functions as an integrator. A signal from an input current source I IN    350  may be applied to the integrator  300  at input  390 . The input current signal may be integrated over capacitor C FB    303  as previously explained. 
     The voltage V IN  may fluctuate from V REF-HI , in which case the pre-amplifier  310  and the multipath amplifier  320  respond to return, via the feedback path through feedback capacitor C FB    303 , the voltage V IN  to V REF-HI . The level shift capacitor C LS    307 , which may act as a floating voltage source, and has been charged to a voltage V CLS  at reset, may reduce the voltage V IN  to a voltage approximately equal to V IN -V CLS  that may be maintained at the inverting input of amplifier  313 . 
     The voltages V IN -V CLS  and V REF-LO  may be less than the power supply voltage of V DDL  of amplifier  313 . The amplifier  313  may output differential voltages to the inputs INN 1 /INP 1  of the multipath amplifier  320  representative of the difference between the values of V IN -V CLS  and V REF-LO . The differential voltages received on inputs INN 1 /INP 1  may be input into a transconductance amplifier A INT , which may output a gained current that may be proportional to the difference of the differential voltages received on inputs INN 1 /INP 1 . 
     Multipath amplifier  320  may also have inputs INN 2 /INP 2  that may receive the voltages V IN  and V REF-HI , respectively. The voltages on inputs INN 2 /INP 2  may be input into the transconductance amplifier A RESET , which may output a gained current proportional to the difference of the voltages V IN  and V REF-HI . The current outputs of the amplifiers A INT  and A RESET  may be connected together, so the outputs of each are combined, and output to V OUT . Via the feedback path through feedback capacitor C FB    303 , the voltage V IN  is returned to V REF-HI . After the input current signal from current source I IN    350  is integrated for a predetermined time period, the integrator  300  enters a reset mode, and is reset to a reference voltage as previously explained above. 
     Generally, V IN  may be approximately 4-5 volts, while the power supply voltage V DDL  to amplifier  313  may be approximately 1.8 volts. Consequently, the input voltage at the inverting input of amplifier  313  may be expected to be lower than or approximately equal to the voltage V DDL  due to the level-shifting of capacitor C LS    307 . The input to the inverting input of amplifier  313  may be maintained at a voltage of approximately V IN -V CLS , which may be approximately equal to V REF-LO . The voltage V CLS  may be expected to have minimal change from its voltage at reset. Thereby, the level-shift capacitor may reduces the voltage level of an input by the voltage V CLS  to a voltage level that is less than or equal to the supply voltage V DDL . Overall, the noise and the power consumption of the circuit  300  may be reduced in comparison to prior art systems because the lower supply voltage VDDL with a higher supply current may be used. 
     An exemplary circuit diagram of the pre-amplifier and the multipath amplifier are shown respectively in  FIGS. 4 and 5 .  FIG. 4  illustrates one of a plurality of exemplary configurations for a pre-amplifier stage according to an embodiment of the present invention. 
     The exemplary pre-amplifier stage may have multiple stages. For example, a first stage may have a P-channel input pair with Mp 1  and Mp 2 , and may have load resistors of Rn 1  and Rn 2 , to form a wide band amplifier with fixed gain. The gain may be given by gmp 1 *Rn 1  where gmp 1  represents a transconductance of the Mp 1  and the Mp 2 . For example, a second stage may have another P-channel input pair with Mp 5  and Mp 6  and may have current sources of Mn 1  and Mn 2 , to form a transconductance amplifier. The transconductance of this stage may be gmp 5 , which is the transconductance of the Mp 5  and the Mp 6 . 
     The exemplary first and second stage may operate in a reset mode and an integration mode. During the reset mode, switches Sw 3  and Sw 4 , driven by PIRST_B, may be open so that the pre-amplifier stage may be disconnected from the multipath amplifier. In the meantime, Sw 1  and Sw 2  may be closed to perform an auto-zero function, so that a null voltage is stored at auto-zero capacitors C 1  and C 2 . 
     During the integration mode, the switches Sw 1  and the Sw 2  may be open, and the null voltage at the capacitors C 1  and C 2  may be maintained to null out any offset current at the output terminal (OUTP/OUTN). The switches Sw 3  and the Sw 4  may be closed to connect to representative ones of the differential outputs OUTN and OUTP, which are connected to respective input terminals of the amplifier A 2  (INP 1 /INN 1 ). 
       FIG. 5  illustrates an embodiment of an exemplary multipath amplifier with multi-differential inputs according to an embodiment of the present invention. The exemplary multipath amplifier may receive differential input voltages on INN 1  and INP 1 . In  FIG. 5 , the multipath amplifier may have both an N-channel input pair with Mn 11 /Mn 12  and a P-channel input pair with Mp 11 /Mp 12 , to accommodate either higher or lower input common mode voltage at the INP 2 /INN 2  terminal. The multipath amplifier may employ a folded cascode stage to enhance the DC gain. A folded cascode stage may contain a PMOS current mirror (Mp 15 , Mp 16 , M 17 , and Mp 18 ), and a NMOS current sources (Mn 15 , Mn 16 , Mn 17 , and Mn 18 ). The multipath amplifier may have another differential input (INP 1 /INN 1 ) at the source of the Mn 17  and the Mn 18 , to receive the current signal from the A 1 . 
     In operation, the embodiment of  FIG. 5  may also operate in two modes: a reset mode and an integration mode. During the reset mode, the INP 1 /INN 1  may be isolated from amplifier A 1  and the inputs INP 2 /INN 2  may be the only active inputs. By the feedback operation, the voltage at the INN 2  and the OUT output voltage are forced to the voltage V REF-HI . During the integration mode, the INP 1 /INN 1  is connected to the output of the pre-amplifier stage of  FIG. 4  to receive its output current. 
     The open loop gain (AOL) equation of the multi-path amplifier is shown below in Equation 1 (Eq. 1), while amplifier A 1  may be associated with the path through INP 1 /INN 1  and the amplifier A 2  may be associated with the path through INP 2 /INN 2 . 
     
       
         
           
             
               
                 
                   
                     
                       
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       FIG. 5  is one of a plurality of exemplary configurations of the multipath amplifier stage, which, for example, may be used with the pre-amplifier stage shown in the  FIG. 4 . 
     The disclosed integration circuit may be employed in a plurality of applications. One such application is illustrated in  FIG. 6 .  FIG. 6  illustrates an exemplary implementation according to an embodiment of the present invention. 
     The disclosed integration circuit may be used, for example, as a digital X-ray analog front end (AFE). The AFE can act as a multi-channel data acquisition system, where one channel contains an embodiment of the disclosed integrator (INT) and a correlated double sampling stage (CDS). The INT may integrate the charge signal from the photodiode sensor. Any reset noise of the INT may be removed by the CDS stage. The acquired signals may be multiplexed and digitized by the MUX and the ADC. 
     Several features and aspects of the present invention have been illustrated and described in detail with reference to particular embodiments by way of example only, and not by way of limitation. Those of skill in the art will appreciate that alternative implementations and various modifications to the disclosed embodiments are within the scope and contemplation of the present disclosure.