Patent Publication Number: US-8115414-B2

Title: LED driver with segmented dynamic headroom control

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     The present application claims priority to U.S. Provisional Patent Application No. 61/036,053, filed Mar. 12, 2008 and having common inventorship, the entirety of which is incorporated by reference herein. The present application also claims priority to U.S. patent application Ser. No. 12/056,237 filed Mar. 26, 2008, which is now U.S. Pat. No. 7,825,610, the entirety of which is incorporated by reference herein. 
    
    
     FIELD OF THE DISCLOSURE 
     The present disclosure relates generally to light emitting diodes (LEDs) and more particularly to LED drivers. 
     BACKGROUND 
     Light emitting diodes (LEDs) often are used as light sources in liquid crystal displays (LCDs) and other displays. The LEDs often are arranged in parallel “strings” driven by a shared voltage source, each LED string having a plurality of LEDs connected in series. To provide consistent light output between the LED strings, each LED string typically is driven at a regulated current that is substantially equal among all of the LED strings. 
     Although driven by currents of equal magnitude, there often is considerable variation in the bias voltages needed to drive each LED string due to variations in the static forward-voltage drops of individual LEDs of the LED strings resulting from process variations in the fabrication and manufacturing of the LEDs. Dynamic variations due to changes in temperature when the LEDs are enabled and disabled also can contribute to the variation in bias voltages needed to drive the LED strings with a fixed current. In view of this variation, conventional LED drivers typically provide a fixed voltage that is sufficiently higher than an expected worst-case bias drop so as to ensure proper operation of each LED string. However, as the power consumed by the LED driver and the LED strings is a product of the output voltage of the LED driver and the sum of the currents of the individual LED strings, the use of an excessively high output voltage by the LED driver unnecessarily increases power consumption by the LED driver. Accordingly, an improved technique for driving LED strings would be advantageous. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The present disclosure may be better understood, and its numerous features and advantages made apparent to those skilled in the art by referencing the accompanying drawings. The use of the same reference symbols in different drawings indicates similar or identical items. 
         FIG. 1  is a diagram illustrating a light emitting diode (LED) system having dynamic power management in accordance with at least one embodiment of the present disclosure. 
         FIG. 2  is a flow diagram illustrating a method of operation of the LED system of  FIG. 1  in accordance with at least one embodiment of the present disclosure. 
         FIG. 3  is a flow diagram illustrating the method of  FIG. 2  in greater detail in accordance with at least one embodiment of the present disclosure. 
         FIG. 4  is a diagram illustrating an example implementation of a feedback controller of the LED system of  FIG. 1  in accordance with at least one embodiment of the present disclosure. 
         FIG. 5  is a flow diagram illustrating a method of operation of the example implementation of  FIG. 4  in accordance with at least one embodiment of the present disclosure. 
         FIG. 6  is a diagram illustrating another example implementation of the feedback controller of the LED system of  FIG. 1  in accordance with at least one embodiment of the present disclosure. 
         FIG. 7  is a flow diagram illustrating a method of operation of the example implementation of  FIG. 6  in accordance with at least one embodiment of the present disclosure. 
         FIG. 8  is a diagram illustrating another example implementation of the feedback controller of the LED system of  FIG. 1  in accordance with at least one embodiment of the present disclosure. 
         FIG. 9  is a flow diagram illustrating a method of operation of the example implementation of  FIG. 8  in accordance with at least one embodiment of the present disclosure. 
         FIG. 10  is a diagram illustrating another example implementation of the feedback controller of the LED system of  FIG. 1  in accordance with at least one embodiment of the present disclosure. 
         FIG. 11  is a flow diagram illustrating a method of operation of the example implementation of  FIG. 10  in accordance with at least one embodiment of the present disclosure. 
         FIG. 12  is a diagram illustrating an integrated circuit (IC)-based implementation of the LED system of  FIG. 1  in accordance with at least one embodiment of the present disclosure. 
         FIG. 13  is a diagram illustrating a segmented implementation of the feedback controller of the LED system of  FIG. 1  in accordance with at least one embodiment of the present disclosure. 
         FIG. 14  is a diagram illustrating another segmented implementation of the feedback controller of the LED system of  FIG. 1  in accordance with at least one embodiment of the present disclosure. 
         FIG. 15  is a diagram illustrating yet another segmented implementation of the feedback controller of the LED system of  FIG. 1  in accordance with at least one embodiment of the present disclosure. 
     
    
    
     DETAILED DESCRIPTION 
       FIGS. 1-15  illustrate example techniques for dynamic power management in a light emitting diode (LED) system having a plurality of LED strings. A voltage source provides an output voltage to drive the LED strings. A feedback controller of an LED driver monitors the tail voltages of the LED strings to identify the minimum, or lowest, tail voltage and adjusts the output voltage of the voltage source based on the lowest tail voltage. In at least one embodiment, the feedback controller adjusts the output voltage so as to maintain the lowest tail voltage at or near a predetermined threshold voltage so as to ensure that the output voltage is sufficient to properly drive each active LED string with a regulated current in view of pulse width modulation (PWM) timing requirements without excessive power consumption. Further, as described below with reference to  FIGS. 13-15 , the plurality of LED strings can be grouped into subsets and the feedback controller can be segmented such that, for a certain duration, a minimum tail voltage is determined for each subset, and then the minimum tail voltages of the subsets are used to determine the overall minimum tail voltage of the plurality of LED strings for the certain duration so as to control the output voltage provided to the plurality of LED strings in the following duration. In this way, the segments of the feedback controller can be implemented in separate integrated circuit (IC) packages, thereby allowing the LED system to adapt to different numbers of LED strings by integrating the corresponding number of IC packages. 
     The term “LED string,” as used herein, refers to a grouping of one or more LEDs connected in series. The “head end” of a LED string is the end or portion of the LED string which receives the driving voltage/current and the “tail end” of the LED string is the opposite end or portion of the LED string. The term “tail voltage,” as used herein, refers the voltage at the tail end of a LED string or representation thereof (e.g., a voltage-divided representation, an amplified representation, etc.). The term “subset of LED strings” refers to one or more LED strings. 
       FIG. 1  illustrates a LED system  100  having dynamic power management in accordance with at least one embodiment of the present disclosure. In the depicted example, the LED system  100  includes a LED panel  102 , a LED driver  104 , and a voltage source  112  for providing an output voltage VOUT to drive the LED panel  102 . The LED panel  102  includes a plurality of LED strings (e.g., LED strings  105 ,  106 , and  107 ). Each LED string includes one or more LEDs  108  connected in series. The LEDs  108  can include, for example, white LEDs, red, green, blue (RGB) LEDs, organic LEDs (OLEDs), etc. Each LED string is driven by the adjustable voltage V OUT  received at the head end of the LED string via a voltage bus  110  (e.g., a conductive trace, wire, etc.). In the embodiment of  FIG. 1 , the voltage source  112  is implemented as a boost converter configured to drive the output voltage V OUT  using an input voltage V IN . 
     The LED driver  104  includes a feedback controller  114  configured to control the voltage source  112  based on the tail voltages at the tail ends of the LED strings  105 - 107 . As described in greater detail below, the LED driver  104 , in one embodiment, receives pulse width modulation (PWM) data representative of which of the LED strings  105 - 107  are to be activated and at what times during a corresponding PWM cycle, and the LED driver  104  is configured to either collectively or individually activate the LED strings  105 - 107  at the appropriate times in their respective PWM cycles based on the PWM data. 
     The feedback controller  114 , in one embodiment, includes a plurality of current regulators (e.g., current regulators  115 ,  116 , and  117 ), a code generation module  118 , a code processing module  120 , a control digital-to-analog converter (DAC)  122 , an error amplifier (or comparator)  124 , and a data/timing control module  128  (illustrated in  FIG. 1  as part of the feedback controller  114 ). 
     In the example of  FIG. 1 , the current regulator  115  is configured to maintain the current I 1  flowing through the LED string  105  at or near a fixed current (e.g., 30 mA) when active. Likewise, the current regulators  116  and  117  are configured to maintain the current I 2  flowing through the LED string  106  when active and the current I n  flowing through the LED string  107  when active, respectively, at or near the fixed current. The current control modules  125 ,  126 , and  127  are configured to activate or deactivate the LED strings  105 ,  106 , and  107 , respectively, via the corresponding current regulators. 
     Typically, a current regulator, such as current regulators  115 - 117 , operates more optimally when the input of the current regulator is a non-zero voltage so as to accommodate the variation in the input voltage that often results from the current regulation process of the current regulator. This buffering voltage often is referred to as the “headroom” of the current regulator. As the current regulators  115 - 117  are connected to the tail ends of the LED strings  105 - 107 , respectively, the tail voltages of the LED strings  105 - 107  represent the amounts of headroom available at the corresponding current regulators  115 - 117 . However, headroom in excess of that necessary for current regulation purposes results in unnecessary power consumption by the current regulator. Accordingly, as described in greater detail herein, the LED system  100  employs techniques to provide dynamic headroom control so as to maintain the minimum tail voltage of the active LED strings at or near a predetermined threshold voltage, thus maintaining the lowest headroom of the current regulators  105 - 107  at or near the predetermined threshold voltage. The threshold voltage can represent a determined balance between the need for sufficient headroom to permit proper current regulation by the current regulators  105 - 107  and the advantage of reduced power consumption by reducing the excess headroom at the current regulators  105 - 107 . 
     The data/timing control module  128  receives the PWM data and is configured to provide control signals to the other components of the LED driver  104  based on the timing and activation information represented by the PWM data. To illustrate, the data/timing control module  128  provides control signals C 1 , C 2 , and C n  to the current control modules  125 ,  126 , and  127 , respectively, to control which of the LED strings  105 - 107  are active during corresponding portions of their respective PWM cycles. The data/timing control module  128  also provides control signals to the code generation module  118 , the code processing module  120 , and the control DAC  122  so as to control the operation and timing of these components. The data/timing control module  128  can be implemented as hardware, software executed by one or more processors, or a combination thereof. To illustrate, the data/timing control module  128  can be implemented as a logic-based hardware state machine. 
     The code generation module  118  includes a plurality of tail inputs coupled to the tail ends of the LED strings  105 - 107  to receive the tail voltages V T1 , V T2 , and V Tn  of the LED strings  105 ,  106 , and  107 , respectively, and an output to provide a code value C min     —     min . In at least one embodiment, the code generation module  118  is configured to identify or detect the minimum, or lowest, tail voltage of the LED strings  105 - 107  that occurs over a PWM cycle or other specified duration and generate the digital code value C min     —     min  based on the identified minimum tail voltage. In the disclosure provided herein, the following nomenclature is used: the minimum of a particular measured characteristic over a PWM cycle or other specified duration is identified with the subscript “min_min”, thereby indicating it is the minimum over a specified time span; whereas the minimum of a particular measured characteristic at a given point in time or sample point is denoted with the subscript “min.” To illustrate, the minimum tail voltage of the LED strings  105 - 107  at any given point in time or sample point is identified as V Tmin , whereas the minimum tail voltage of the LED strings  105 - 107  for a given PWM cycle (having one or more sample points) is identified as V Tmin     —     min . Similarly, the minimum code value determined at a given point in time or sample point is identified as C min , whereas the minimum code value for a given PWM cycle (having one or more sample points) is identified as C min     —     min . 
     The code generation module  118  can include one or more of a string select module  130 , a minimum detect module  132 , and an analog-to-digital converter (ADC)  134 . As described in greater detail below with reference to  FIGS. 4 ,  5 ,  8  and  9 , the string select module  130  is configured to output the minimum tail voltage V Tmin  of the LED strings  105 - 107  (which can vary over the PWM cycle), the ADC  134  is configured to convert the magnitude of the minimum tail voltage V Tmin  output by the string select module  130  to a corresponding code value C min  for each of a sequence of conversion points in the PWM cycle, the minimum detect module  132  is configured as a digital component to detect the minimum code value C min  from the plurality of code values C min  generated over the PWM cycle as the minimum code value C min     —     min  for the PWM cycle. Alternately, as described in greater detail below with reference to  FIGS. 6 and 7 , the minimum detect module  132  is configured as an analog component to determine the minimum tail voltage V Tmin     —     min  for the PWM cycle from the potentially varying magnitude of the voltage V Tmin  output by the string select module  130  over the PWM cycle, and the ADC  134  is configured to perform a single conversion of the voltage V Tmin     —     min  to the minimum code value C min     —     min  for the PWM cycle. As another embodiment, as described in greater detail below with reference to  FIGS. 10 and 11 , the string select module  130  is omitted and the ADC  134  can be configured as multiple ADCs. Each ADC is configured to repeatedly convert the tail voltage of a corresponding one of the LED strings  105 - 107  into a series of code values C i  (for a corresponding LED string i) having magnitudes representative of the magnitude of the tail voltage at the time of the conversion. In this instance, the minimum detect module  132  is configured as a digital component to determine the minimum of the code values C i  generated from all of the ADCs to identify the minimum code value C min     —     min  over the PWM cycle. 
     The code processing module  120  includes an input to receive the code value C min     —     min  and an output to provide a code value C reg  based on the code value C min     —     min  and either a previous value for C reg  from a previous PWM cycle or an initialization value. As the code value C min     —     min  represents the minimum tail voltage V Tmin     —     min  that occurred during the PWM cycle for all of the LED strings  105 - 107 , the code processing module  120 , in one embodiment, compares the code value C min     —     min  to a threshold code value, C thresh , and generates a code value C reg  based on the comparison. The code processing module  120  can be implemented as hardware, software executed by one or more processors, or a combination thereof. To illustrate, the code processing module  120  can be implemented as a logic-based hardware state machine, software executed by a processor, and the like. Example implementations of the code generation module  118  and the code processing module  120  are described in greater detail with reference to  FIGS. 4-11 . 
     In certain instances, none of the LED strings  105 - 107  may be enabled for a given PWM cycle. Thus, to prevent an erroneous adjustment of the output voltage V OUT  when all LED strings are disabled, in one embodiment the data/timing control module  128  signals the code processing module  120  to suppress any updated code value C reg  determined during a PWM cycle in which all LED strings are disabled, and instead use the code value C reg  from the previous PWM cycle. 
     The control DAC  122  includes an input to receive the code value C reg  and an output to provide a regulation voltage V reg  representative of the code value C reg . The regulation voltage V reg  is provided to the error amplifier  124 . The error amplifier  124  also receives a feedback voltage V fb  representative of the output voltage V OUT . In the illustrated embodiment, a voltage divider  126  implemented by resistors  129  and  131  is used to generate the voltage V fb  from the output voltage V OUT . The error amplifier  124  compares the voltage V fb  and the voltage V reg  and configures a signal ADJ based on this comparison. The voltage source  112  receives the signal ADJ and adjusts the output voltage V OUT  based on the magnitude of the signal ADJ. 
     As similarly described above, there may be considerable variation between the voltage drops across each of the LED strings  105 - 107  due to static variations in forward-voltage biases of the LEDs  108  of each LED string and dynamic variations due to the on/off cycling of the LEDs  108 . Thus, there may be significant variance in the bias voltages needed to properly operate the LED strings  105 - 107 . However, rather than drive a fixed output voltage V OUT  that is substantially higher than what is needed for the smallest voltage drop as this is handled in conventional LED drivers, the LED driver  104  illustrated in  FIG. 1  utilizes a feedback mechanism that permits the output voltage V OUT  to be adjusted so as to reduce or minimize the power consumption of the LED driver  104  in the presence of variances in voltage drop across the LED strings  105 - 107 , as described below with reference to the methods  200  and  300  of  FIG. 2  and  FIG. 3 , respectively. For ease of discussion, the feedback duration of this mechanism is described in the context of a PWM cycle-by-PWM cycle basis for adjusting the output voltage V OUT . However, any of a variety of durations may be used for this feedback mechanism without departing from the scope of the present disclosure. To illustrate, the feedback duration could encompass a portion of a PWM cycle, multiple PWM cycles, a certain number of clock cycles, a duration between interrupts, a duration related to video display such as video frame, and the like. 
       FIG. 2  illustrates an example method  200  of operation of the LED system  100  in accordance with at least one embodiment of the present disclosure. At block  202 , the voltage source  112  provides an initial output voltage V OUT . As the PWM data for a given PWM cycle is received, the data/timing control module  128  configures the control signals C 1 , C 2 , and C n  so as to selectively activate the LED strings  105 - 107  at the appropriate times of their respective PWM cycles. Over the course of the PWM cycle, the code generation module  118  determines the minimum detected tail voltage (V Tmin     —     min ) for the LED tails  105 - 107  for the PWM cycle at block  204 . At block  206 , the feedback controller  114  configures the signal ADJ based on the voltage V Tmin     —     min  to adjust the output voltage V OUT , which in turn adjusts the tail voltages of the LED strings  105 - 107  so that the minimum tail voltage V Tmin  of the LED strings  105 - 107  is closer to a predetermined threshold voltage. The process of blocks  202 - 206  can be repeated for the next PWM cycle, and so forth. 
     As a non-zero tail voltage for a LED string indicates that more power is being used to drive the LED string than is absolutely necessary, it typically is advantageous for power consumption purposes for the feedback controller  114  to manipulate the voltage source  112  to adjust the output voltage V OUT  until the minimum tail voltage V Tmin     —     min  would be approximately zero, thereby eliminating nearly all excess power consumption that can be eliminated without disturbing the proper operation of the LED strings. Accordingly, in one embodiment, the feedback controller  114  configures the signal ADJ so as to reduce the output voltage V OUT  by an amount expected to cause the minimum tail voltage V Tmin     —     min  of the LED strings  105 - 107  to be at or near zero volts. 
     However, while being advantageous from a power consumption standpoint, having a near-zero tail voltage (headroom voltage) on a LED string introduces potential problems. As one issue, the current regulators  115 - 117  may need non-zero tail voltages to operate properly. Further, it will be appreciated that a near-zero tail voltage provides little or no margin for spurious increases in the bias voltage needed to drive the LED string resulting from self-heating or other dynamic influences on the LEDs  108  of the LED strings  105 - 107 . Accordingly, in at least one embodiment, the feedback controller  114  can achieve a suitable compromise between reduction of power consumption and the response time of the LED driver  104  by adjusting the output voltage V OUT  so that the expected minimum tail voltage of the LED strings  105 - 107  or the expected minimum headroom voltage for the current regulators  115 - 117  is maintained at or near a non-zero threshold voltage V thresh  that represents an acceptable compromise between LED current regulation, PWM response time and reduced power consumption. The threshold voltage V thresh  can be implemented as, for example, a voltage between 0.1 V and 1 V (e.g., 0.5 V). 
       FIG. 3  illustrates a particular implementation of the process represented by block  206  of the method  200  of  FIG. 2  in accordance with at least one embodiment of the present disclosure. As described above, at block  204  ( FIG. 2 ) of the method  200 , the code generation module  118  monitors the tail voltages V T1 , V T2 , and V Tn  of the LED tails  105 - 107  to identify the minimum detected tail voltage V Tmin     —     min  for the PWM cycle. At block  302 , the code generation module  118  converts the voltage V Tmin     —     min  to a corresponding digital code value C min     —     min . Thus, the code value C min     —     min  is a digital value representing the minimum tail voltage V Tmin     —     min  detected during the PWM cycle. As described in greater detail herein, the detection of the minimum tail voltage V Tmin     —min    can be determined in the analog domain and then converted to a digital value, or the detection of the minimum tail voltage V Tmin     —     min  can be determined in the digital domain based on the identification of the minimum code value C min     —     min  from a plurality of code values C min  representing the minimum tail voltage V Tmin  at various points over the PWM cycle. 
     At block  304 , the code processing module  120  compares the code value C min     —     min  with a code value C thresh  to determine the relationship of the minimum tail voltage V Tmin     —     min  (represented by the code value C min     —     min ) to the threshold voltage V thresh  (represented by the code value C thresh ). As described above, the feedback controller  114  is configured to control the voltage source  112  so as to maintain the minimum tail voltage of the LED strings  105 - 107  at or near a threshold voltage V thresh  during the corresponding PWM cycle. The voltage V thresh  can be at or near zero volts to maximize the reduction in power consumption or it can be a non-zero voltage (e.g., 0.5 V) so as to comply with PWM performance requirements and current regulation requirements while still reducing power consumption. 
     The code processing module  120  generates a code value C reg  based on the relationship of the minimum tail voltage V Tmin     —     min  to the threshold voltage V thresh  revealed by the comparison of the code value C min     —     min  to the code value C thresh . As described herein, the value of the code value C reg  affects the resulting change in the output voltage V OUT . Thus, when the code value C min     —     min  is greater than the code value C thresh , a value for C reg  is generated so as to reduce the output voltage V OUT , which in turn is expected to reduce the minimum tail voltage V Tmin  closer to the threshold voltage V thresh . To illustrate, the code processing module  120  compares the code value C min     —     min  to the code value C thresh . If the code value C min     —     min  is less than the code value C thresh , an updated value for C reg  is generated so as to increase the output voltage V OUT , which in turn is expected to increase the minimum tail voltage V Tmin     —     min  closer to the threshold voltage V thresh . Conversely, if the code value C min     —     min  is greater than the code value C thresh , an updated value for C reg  is generated so as to decrease the output voltage V OUT , which in turn is expected to decrease the minimum tail voltage V Tmin min  closer to the threshold voltage V thresh . To illustrate, the updated value for C reg  can be set to 
     
       
         
           
             
               
                 
                   
                     
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     whereby R f1  and R f2  represent the resistances of the resistor  129  and the resistor  131 , respectively, of the voltage divider  126  and Gain_ADC represents the gain of the ADC (in units code per volt) and Gain DAC represents the gain of the control DAC  122  (in unit of volts per code). Depending on the relationship between the voltage V Tmin     —     min  and the voltage V thresh  (or the code value C min     —     min  and the code value C thresh ), the offset 1  value can be either positive or negative. 
     Alternately, when the code C min     —     min  indicates that the minimum tail voltage V Tmin     —     min  is at or near zero volts (e.g., C min     —     min =0) the value for updated C reg  can be set to
 
 C   reg (updated)= C   reg (current)+offset2   EQ. 3
 
     whereby offset 2  corresponds to a predetermined voltage increase in the output voltage V OUT  (e.g., 1 V increase) so as to affect a greater increase in the minimum tail voltage V Tmin     —     min . 
     At block  306 , the control DAC  122  converts the updated code value C reg  to its corresponding updated regulation voltage V reg . At block  308 , the feedback voltage V fb  is obtained from the voltage divider  126 . At block  310 , error amplifier  124  compares the voltage V reg  and the voltage V fb  and configures the signal ADJ so as to direct the voltage source  112  to increase or decrease the output voltage V OUT  depending on the result of the comparison as described above. The process of blocks  302 - 310  can be repeated for the next PWM cycle, and so forth. 
       FIG. 4  illustrates a particular implementation of the code generation module  118  and the code processing module  120  of the LED driver  104  of  FIG. 1  in accordance with at least one embodiment of the present disclosure. In the illustrated embodiment, the code generation module  118  includes an analog string select module  402  (corresponding to the string select module  130 ,  FIG. 1 ), an analog-to-digital converter (ADC)  404  (corresponding to the ADC  134 ,  FIG. 1 ), and a digital minimum detect module  406  (corresponding to the minimum detect module  132 ,  FIG. 1 ). The analog string select module  402  includes a plurality of inputs coupled to the tail ends of the LED strings  105 - 107  ( FIG. 1 ) so as to receive the tail voltages V T1 , V T2 , and V Tn . In one embodiment, the analog string select module  402  is configured to provide the voltage V Tmin  that is equal to or representative of the lowest tail voltage of the active LED strings at the corresponding point in time of the PWM cycle. That is, rather than supplying a single voltage value at the conclusion of a PWM cycle, the voltage V Tmin  output by the analog string select module  402  varies throughout the PWM cycle as the minimum tail voltage of the LED strings changes at various points in time of the PWM cycle. 
     The analog string select module  402  can be implemented in any of a variety of manners. For example, the analog string select module  402  can be implemented as a plurality of semiconductor p-n junction diodes, each diode coupled in a reverse-polarity configuration between a corresponding tail voltage input and the output of the analog string select module  402  such that the output of the analog string select module  402  is always equal to the minimum tail voltage V Tmin  where the offset from voltage drop of the diodes (e.g., 0.5 V or 0.7 V) can be compensated for using any of a variety of techniques. 
     The ADC  404  has an input coupled to the output of the analog string select module  402 , an input to receive a clock signal CLK 1 , and an output to provide a sequence of code values C min  over the course of the PWM cycle based on the magnitude of the minimum tail voltage V Tmin  at respective points in time of the PWM cycle (as clocked by the clock signal CLK 1 ). The number of code values C min  generated over the course of the PWM cycle depends on the frequency of the clock signal CLK 1 . To illustrate, if the clock signal CLK 1  has a frequency of 1000*CLK_PWM (where CLK_PWM is the frequency of the PWM cycle) and can convert the magnitude of the voltage V Tmin  to a corresponding code value C min  at a rate of one conversion per clock cycle, the ADC  404  can produce 1000 code values C min  over the course of the PWM cycle. 
     The digital minimum detect module  406  receives the sequence of code values C min  generated over the course of the PWM cycle by the ADC  404  and determines the minimum, or lowest, of these code values for the PWM cycle. To illustrate, the digital minimum detect module  406  can include, for example, a buffer, a comparator, and control logic configured to overwrite a code value C min  stored in the buffer with an incoming code value C min  if the incoming code value C min  is less than the one in the buffer. The digital minimum detect module  406  provides the minimum code value C min  of the series of code values C min  for the PWM cycle as the code value C min     —     min  to the code processing module  120 . The code processing module  120  compares the code value C min     —     min  to the predetermined code value C thresh  and generates an updated code value C reg  based on the comparison as described in greater detail above with reference to block  304  of  FIG. 3 . 
       FIG. 5  illustrates an example method  500  of operation of the implementation of the LED system  100  illustrated in  FIGS. 1 and 4  in accordance with at least one embodiment of the present disclosure. At block  502 , a PWM cycle starts, as indicated by the received PWM data ( FIG. 1 ). At block  504 , the analog string select module  402  provides the minimum tail voltage of the LED strings at a point in time of the PWM cycle as the voltage V Tmin  for that point in time. At block  506 , the ADC  404  converts the voltage V Tmin  to a corresponding code value C min  and provides it to the digital minimum detect  406  for consideration as the minimum code value C min     —     min  for the PWM cycle thus far at block  508 . At block  510 , the data/timing control module  128  determines whether the end of the PWM cycle has been reached. If not, the process of blocks  504 - 508  is repeated to generate another code value C min . Otherwise, if the PWM cycle has ended, the minimum code value C min  of the plurality of code values C min  generated during the PWM cycle is provided as the code value C min     —     min  by the digital minimum detect module  406 . In an alternate embodiment, the plurality of code values C min  generated during the PWM cycle are buffered and then the minimum value C min     —     min  is determined at the end of the PWM cycle from the plurality of buffered code values C min . At block  512  the code processing module  120  uses the minimum code value C min     —     min  to generate an updated code value C reg  based on a comparison of the code value C min     —     min  to the predetermined code value C thresh . The control DAC  122  uses the updated code value C reg  to generate the corresponding voltage V reg , which is used by the error amplifier  124  along with the voltage V fb  to adjust the output voltage V OUT  as described above. 
       FIG. 6  illustrates another example implementation of the code generation module  118  and the code processing module  120  of the LED driver  104  of  FIG. 1  in accordance with at least one embodiment of the present disclosure. In the illustrated embodiment, the code generation module  118  includes the analog string select module  402  as described above, an analog minimum detect module  606  (corresponding to the minimum detect module  132 ,  FIG. 1 ), and an ADC  604  (corresponding to the ADC  134 ,  FIG. 1 ). As described above, the analog string select module  402  continuously selects and outputs the minimum tail voltage of the LED strings  105 - 107  at any given time as the voltage V Tmin  for that point in time. The analog minimum detect module  606  includes an input coupled to the output of the analog string select module  402 , an input to receive a control signal CTL 3  from the data/timing control module  128  ( FIG. 1 ), where the control signal CTL 3  signals the start and end of each PWM cycle. In at least one embodiment, the analog minimum detect module  606  detects the minimum voltage of the output of the analog string select module  402  over the course of a PWM cycle and outputs the minimum detected voltage as the minimum tail voltage V Tmin     —     min . 
     The analog minimum detect module  606  can be implemented in any of a variety of manners. To illustrate, in one embodiment, the analog minimum detect module  606  can be implemented as a negative peak voltage detector that is accessed and then reset at the end of each PWM cycle. Alternately, the analog minimum detect module  606  can be implemented as a set of sample-and-hold circuits, a comparator, and control logic. One of the sample-and-hold circuits is used to sample and hold the voltage V Tmin  and the comparator is used to compare the sampled voltage with a sampled voltage held in a second sample-and-hold circuit. If the voltage of the first sample-and-hold circuit is lower, the control logic switches to using the second sample-and-hold circuit for sampling the voltage V Tmin  for comparison with the voltage held in the first sample-and-hold circuit, and so on. 
     The ADC  604  includes an input to receive the minimum tail voltage V Tmin     —     min  for the corresponding PWM cycle and an input to receive a clock signal CLK 2 . The ADC  604  is configured to generate the code value C min     —     min  representing the minimum tail voltage V Tmin     —     min  and provide the code value C min     —     min  to the code processing module  120 , whereby it is compared with the predetermined code value C thresh  to generate the appropriate code value C reg  as described above. 
       FIG. 7  illustrates an example method  700  of operation of the implementation of the LED system  100  illustrated in  FIGS. 1 and 6  in accordance with at least one embodiment of the present disclosure. At block  702 , a PWM cycle starts, as indicated by the received PWM data ( FIG. 1 ). At block  704 , the analog string select module  402  provides the lowest tail voltage of the active LED strings at a given point in time of the PWM cycle as the voltage V Tmin  for that point in time. At block  706 , the minimum magnitude of the voltage V Tmin  detected by the analog minimum detect module  606  is identified as the minimum tail voltage V Tmin     —     min  for the PWM cycle thus far. At block  708 , the data/timing control module  128  determines whether the end of the PWM cycle has been reached. If the PWM cycle has ended, the ADC  604  converts the minimum tail voltage V Tmin     —     min  to the corresponding code value C min     —     min . At block  712 , the code processing module  120  converts the code value C min     —     min  to an updated code value C reg  based on a comparison of the code value C min     —     min  to the predetermined code value C thresh . The control DAC  122  converts the updated code value C reg  to the corresponding voltage V reg , which is used by the error amplifier  124  along with the voltage V fb  to adjust the output voltage V OUT  as described above. 
     In the implementation of  FIGS. 4 and 5 , the voltage V Tmin  output by the analog string select module  402  was converted into a sequence of code values C min  based on the clock signal CLK 1  and the sequence of code values C min  was analyzed to determine the minimum code value of the sequence, and thus to determine the code value C min     —     min  representative of the minimum tail voltage V Tmin     —     min  occurring over a PWM cycle. Such an implementation requires an ADC  404  capable of operating with a high-frequency clock CLK 1 . The implementation of  FIGS. 6 and 7  illustrates an alternate with relaxed ADC and clock frequency requirements because the minimum tail voltage V Tmin     —     min  over a PWM cycle is determined in the analog domain and thus only a single analog-to-digital conversion is required from the ADC  604  per PWM cycle, at the cost of adding the analog minimum detect module  606 . 
       FIG. 8  illustrates yet another example implementation of the code generation module  118  and the code processing module  120  of the LED driver  104  of  FIG. 1  in accordance with at least one embodiment of the present disclosure. In the illustrated embodiment, the code generation module  118  includes a plurality of sample-and-hold (S/H) circuits, such as S/H circuits  805 ,  806 , and  807 , a S/H select module  802  (corresponding to the string select module  130 ,  FIG. 1 ), an ADC  804  (corresponding to the ADC  134 ,  FIG. 1 ), and the digital minimum detect module  406  (described above). 
     Each of the S/H circuits  805 - 807  includes an input coupled to the tail end of a respective one of the LED strings  105 - 107  ( FIG. 1 ) to receive the tail voltage of the LED string and an output to provide a sampled tail voltage of the respective LED string. In  FIG. 8 , the sampled voltages output by the S/H circuits  805 - 807  are identified as voltages V 1X , V 2X , and V nX , respectively. In at least one embodiment, a control signal for a corresponding S/H circuit is enabled, thereby enabling sampling of the corresponding tail voltage, when the corresponding LED string is activated by a PWM pulse. 
     The S/H select module  802  includes a plurality of inputs to receive the sampled voltages V 1X , V 2X , and V nX  and is configured to select the minimum, or lowest, of the sampled voltages V 1X , V 2X , and V nX  at any given sample period for output as the voltage level of the voltage V Tmin  for the sample point. The S/H select module  802  can be configured in a manner similar to the analog string select module  402  of  FIGS. 4 and 6 . The ADC  804  includes an input to receive the voltage V Tmin  and an input to receive a clock signal CLK 3 . As similarly described above with respect to the ADC  404  of  FIG. 4 , the ADC  804  is configured to output a sequence of code values C min  from the magnitude of the voltage V Tmin  using the clock signal CLK 3 . 
     As described above, the digital minimum detect module  406  receives the stream of code values C min  for a PWM cycle, determines the minimum code value of the stream, and provides the minimum code value as code value C min     —     min  to the code processing module  120 . The determination of the minimum code value C min     —     min  can be updated as the PWM cycle progresses, or the stream of code values C min  for the PWM cycle can be buffered and the minimum code value C min     —     min  determined at the end of the PWM cycle from the buffered stream of code values C min . The code processing module then compares the code value C min     —     min  to the predetermined code value C thresh  for the purpose of updating the code value C reg . 
       FIG. 9  illustrates an example method  900  of operation of the implementation of the LED system  100  illustrated in  FIGS. 1 and 8  in accordance with at least one embodiment of the present disclosure. At block  902 , a PWM cycle starts, as indicated by the received PWM data ( FIG. 1 ). At block  903 , the S/H circuit  805  samples and holds the voltage level of the tail end of the LED string  105  as the voltage V 1X  when the LED string  105  (e.g., when activated by a PWM pulse). Likewise, at block  904  the S/H circuit  806  samples and holds the voltage level of the tail end of the LED string  106  as the voltage V 2X  when the LED string  106  is activated by a PWM pulse, and at block  905  the S/H circuit  807  samples and holds the voltage level of the tail end of the LED string  107  as the voltage V nx  when the LED string  107  is activated by a PWM pulse. 
     At block  906 , the S/H select module  802  selects the minimum of the sampled voltages V 1X , V 2X , and V nX  for output as the voltage V Tmin . At block  908 , the ADC  804  converts the magnitude of the voltage V Tmin  at the corresponding sample point to the corresponding code value C min  and provides the code value C min  to the digital minimum detect module  406 . At block  910 , the digital minimum detect module  406  determines the minimum code value of the plurality of code values C min  generated during the PWM cycle thus far as the minimum code value C min     —     min . At block  912 , the data/timing control module  128  determines whether the end of the PWM cycle has been reached. If not, the process of blocks  903 ,  904 ,  905 ,  906 ,  908 , and  910  is repeated to generate another code value C min  and update the minimum code value C min     —     min  as necessary. Otherwise, if the PWM cycle has ended, at block  914 , the code processing module  120  converts the code value C min     —     min  to an updated code value C reg  based on a comparison of the code value C min     —     min  to the predetermined code value C thresh . The control DAC  122  converts the updated code value C reg  to the corresponding voltage V reg , which is used by the error amplifier  124  along with the voltage V fb  to adjust the output voltage V OUT  as described above. 
       FIG. 10  illustrates another example implementation of the code generation module  118  and the code processing module  120  of the LED driver  104  of  FIG. 1  in accordance with at least one embodiment of the present disclosure. In the illustrated embodiment, the code generation module  118  includes a plurality of ADCs, such as ADC  1005 , ADC  1006 , and ADC  1007  (corresponding to the ADC  134 ,  FIG. 1 ) and a digital minimum detect module  1004  (corresponding to both the string select module  130  and the minimum detect module  132 ,  FIG. 1 ). 
     Each of the ADCs  1005 - 1007  includes an input coupled to the tail end of a respective one of the LED strings  105 - 107  ( FIG. 1 ) to receive the tail voltage of the LED string, an input to receive a clock signal CLK 4 , and an output to provide a stream of code values generated from the input tail voltage. In  FIG. 10 , the code values output by the ADCs  1005 - 1007  are identified as code values C 1X , C 2X , and C nX , respectively. 
     The digital minimum detect module  1004  includes an input for each of the stream of code values output by the ADCs  1005 - 1007  and is configured to determine the minimum, or lowest, code value from all of the streams of code values for a PWM cycle. In one embodiment, the minimum code value for each LED string for the PWM cycle is determined and then the minimum code value C min     —     min  is determined from the minimum code value for each LED string. In another embodiment, the minimum code value of each LED string is determined at each sample point (e.g., the minimum of C 1X , C 2X , and C nX  at the sample point). The code processing module  120  then compares the code value C min     —     min  to the predetermined code value C thresh  for the purpose of updating the code value C reg . 
       FIG. 11  illustrates an example method  1100  of operation of the implementation of the LED system  100  illustrated in  FIGS. 1 and 10  in accordance with at least one embodiment of the present disclosure. At block  1102 , a PWM cycle starts, as indicated by the received PWM data ( FIG. 1 ). At block  1103 , the ADC  1005  converts the voltage V T1  at the tail end of the LED string  105  to a corresponding code value C 1X  when the LED string  105  (e.g., when activated by a PWM pulse). Likewise, at block  1004  the ADC  1006  converts the voltage V T2  at the tail end of the LED string  106  to a corresponding code value C 2X  when the LED string  106  is activated by a PWM pulse, and at block  1005  the ADC  1007  converts the voltage V Tn  at the tail end of the LED string  107  to a corresponding code value C nX  when the LED string  107  is activated by a PWM pulse. 
     At block  1106 , the digital minimum detect module  1004  determines the minimum code value C min     —     min  of the plurality of code values generated during the PWM cycle thus far, or, in an alternate embodiment, at the end of the PWM cycle from the code values generated over the entire PWM cycle. At block  1108 , the data/timing control module  128  determines whether the end of the PWM cycle has been reached. If not, the process of blocks  1103 ,  1104 ,  1105 ,  1106 , and  1108  is repeated to generate another set of code values from the tail voltages of the active LED strings and update the minimum code value C min     —     min  as necessary. Otherwise, if the PWM cycle has ended, at block  1110 , the code processing module  120  converts the code value C min     —     min  to an updated code value C reg  based on a comparison of the code value C min     —     min  to the predetermined code value C thresh . The control DAC  122  converts the updated code value C reg  to the corresponding voltage V reg , which is used by the error amplifier  124  along with the voltage V fb  to adjust the output voltage V OUT  as described above. 
       FIG. 12  illustrates an IC-based implementation of the LED system  100  of  FIG. 1  as well as an example implementation of the voltage source  112  in accordance with at least one embodiment of the present disclosure. In the depicted example, the LED driver  104  is implemented as an integrated circuit (IC)  1202  having the data/timing control module  128  and the feedback controller  114 . As also illustrated, some or all of the components of the voltage source  112  can be implemented at the IC  1202 . In one embodiment, the voltage source  112  can be implemented as a step-up boost converter, a buck-boost converter, and the like. To illustrate, the voltage source  112  can be implemented with an input capacitor  1212 , an output capacitor  1214 , a diode  1216 , an inductor  1218 , a switch  1220 , a current sense block  1222 , a slope compensator  1224 , an adder  1226 , a loop compensator  1228 , a comparator  1230 , and a PWM controller  1232  connected and configured as illustrated in  FIG. 12 . 
       FIGS. 13-15  illustrate various segmented implementations of the feedback controller  114  so as to permit a LED system to readily adapt to any number of LED strings. Further, as described below, the feedback controller  114  can be segmented such that the various segments each can be implemented in separate IC packages so as to permit expansion of the LED system by implementation of additional IC packages. For ease of illustration, the segmented implementations of  FIGS. 13-15  are described in an example context whereby the LED strings are separated into two subsets. However, the techniques described below can be implemented for any number of subsets using the guidelines provided herein. 
       FIG. 13  illustrates an example segmentation of a feedback controller  1314  (corresponding to the feedback controller  114  of  FIG. 1 ) of a LED driver of a LED system  1300  whereby a code value sequence is separately determined for each subset of LED strings and then the overall minimum code value for the plurality of LED strings is determined from the code value sequences of the subsets. The LED system  1300  includes a voltage source  1312  configured to drive an output voltage V OUT  to a plurality of LED strings  1341 - 1348  via a bus  1310 . In the illustrated example, the LED strings  1341 - 1348  are segmented into two subsets: subset A (LED strings  1341 - 1344 ) and subset B (LED strings  1345 - 1348 ). The voltage source  1312  is controlled via a signal ADJ generated by the feedback controller  1314 . 
     The feedback controller  1314  includes an output to provide the signal ADJ, an input to receive a feedback voltage V fb  via a voltage divider  1326  and a plurality of tail inputs adapted to be coupled to the tail ends of the LED strings  1341 - 1348 . In the depicted example, the feedback controller  1314  is segmented into a control segment  1350  and two subset segments  1352  and  1354  corresponding to subsets A and B, respectively. The subset segment  1352  includes current regulators  1361 - 1364  to regulate the currents through the LED strings  1341 - 1344 , respectively, based on received PWM data (not shown), an analog string select module  1372 , and an ADC  1374 . The subset segment  1354  is similarly configured and includes current regulators  1365 - 1368  to regulate the currents through the LED strings  1345 - 1348 , respectively, based on the received PWM data, an analog string select module  1376 , and an ADC  1378 . The control segment  1350  includes a group code processing module  1380 , a control DAC  1322  (corresponding to the control DAC  122 ,  FIG. 1 ), and an error amplifier  1324  (corresponding to the error amplifier  124 ). The control segment  1350  further can include a portion or the entirety of the voltage source  1312 , as similarly described above with respect to  FIG. 12 . 
     In operation, the subset segments  1352  and  1354  are configured to generate respective code value sequences  1382  and  1384  over a specified duration (e.g., a clock cycle, a PWM cycle, an image frame, etc). The group code processing module  1380  receives the code value sequences  1382  and  1384  and determines the overall minimum code value C min     —     min  from the code value sequences  1382  and  1384  for the specified duration. The group code processing module  1380  then generates the code value C reg  based on the code value C min     —     min  and provides the code value C reg  to the control DAC  1322  for generation of a corresponding voltage V reg  as described above. The error amplifier  1324  then compares the voltage V reg  with the voltage V fb  and configures the signal ADJ based on this relationship so as to control the output voltage V OUT  for the following duration. 
     To this end, the analog string select module  1372  of the subset segment  1352  continuously selects the minimum tail voltage V TminA  from the tail voltages V T1 , V T2 , V T3 , and V T4  of the LED strings  1341 - 1344 , respectively, and provides this minimum tail voltage V TminA  as a signal  1385  to the ADC  1374  as similarly described above with respect to the analog string select modules  402  of  FIGS. 4-7 . The ADC  1374  then samples the signal  1385  at corresponding points of time over the specified duration based on a clock signal (not shown) and generates a corresponding code value C A [x] for the code value sequence  1382  from each sampled voltage of the signal  1385  as it is sampled at point x. Likewise, the analog string select module  1376  of the subset segment  1354  continuously selects the minimum tail voltage V TminB  from the tail voltages V T5 , V T6 , V T7 , and V T8  of the LED strings  1345 - 1348 , respectively, and provides this minimum tail voltage V TminB  as a signal  1387  to the ADC  1378 . The ADC  1378  then samples the signal  1387  at various points of time over the specified duration based on a clock signal (not shown) and generates a corresponding code value C B [x] for the code value sequence  1384  from each sampled voltage of the signal  1387  as it is sampled at point x. 
     The illustrated segmentation of the feedback controller  1314  facilitates implementation of the feedback controller  1314  over a number of IC packages in a manner that permits the feedback controller  1314  to be expanded to accommodate a wide number of LED strings by adding additional IC packages. To illustrate, in one embodiment, the LED system  1300  includes an IC package  1391  in which the control segment  1350  is implemented and two IC packages  1392  in which the subset segments  1352  and  1354  are respectively implemented. In this manner, the feedback controller  1314  can be expanded to include additional subset of LED strings by adding another IC package  1392  to regulate the currents through the LED strings of the additional subset and to generate a code value sequence for use by the group code processing module  1380  in determining the overall minimum code value of the LED strings driven by the voltage source  1312 . Thus, assuming the group code processing module  1380  can process up to X code value sequences and each IC package  1392  is capable of supporting up to Y LED strings, the feedback controller  1314  can support up to X*Y LED strings (assuming the voltage source  1312  can provide sufficient power). 
       FIG. 14  illustrates an example segmentation of a feedback controller  1414  (corresponding to the feedback controller  114  of  FIG. 1 ) of a LED system  1400  whereby a minimum code value is separately determined for each subset of LED strings for a predetermined duration and then the overall minimum code value for the plurality of LED strings for the predetermined duration is determined from the minimum code values of the subsets. The example implementation of  FIG. 14  therefore differs from the example implementation of  FIG. 13  in that the minimum code value for each segment is separately determined and then transmitted to a group code processing module for use in determining the overall minimum code value. Accordingly, the implementation of  FIG. 14  can result in lower bandwidth requirements between the control segment and the subset segments. 
     The LED system  1400  of  FIG. 14  includes a voltage source  1412  configured to drive an output voltage V OUT  to a plurality of LED strings  1441 - 1448  via a bus  1410 . In the illustrated example, the LED strings  1441 - 1448  are segmented into two separate subsets: subset A (LED strings  1441 - 1444 ) and subset B (LED strings  1445 - 1448  ). The voltage source  1412  is controlled via a signal ADJ generated by the feedback controller  1414 . 
     The feedback controller  1414  includes an output to provide the signal ADJ, an input to receive a feedback voltage V fb  via a voltage divider  1426 , and a plurality of tail inputs coupled to the tail ends of the LED strings  1441 - 1448 . The feedback controller  1414  is segmented into a control segment  1450  and two subset segments  1452  and  1454  corresponding to subsets A and B, respectively. The subset segment  1452  includes current regulators  1461 - 1464  to regulate the currents through the LED strings  1441 - 1444 , respectively, based on received PWM data (not shown), an analog string select module  1472 , an ADC  1474 , and a digital minimum detect module  1475 . The subset segment  1454  is similarly configured and includes current regulators  1465 - 1468  to regulate the currents through the LED strings  1445 - 1448 , respectively, based on the received PWM data, an analog string select module  1476 , an ADC  1478 , and a digital minimum detect module  1479 . The control segment  1450  includes a group code processing module  1490 , a control DAC  1422  (corresponding to the control DAC  122 ,  FIG. 1 ), and an error amplifier  1424  (corresponding to the error amplifier  124  ). The control segment  1450  further can include a portion or the entirety of the voltage source  1412 , as similarly described above with respect to  FIG. 12 . 
     In operation, the subset segment  1452  is configured to generate a minimum code value C min     —     minA  representative of the minimum tail voltage of the tail voltages V T1 -V T4  of the LED strings  1441 - 1444 , respectively, over a specified duration (e.g., a clock cycle, a PWM cycle, an image frame, etc). Likewise, the subset segment  1454  is configured to generate a minimum code value C min     —     minB  representative of the minimum tail voltage of the tail voltages V T5 -V T8  of the LED strings  1441 - 1444 , respectively, over the specified duration. The group code processing module  1490  determines the overall minimum code value C min     —     min  for the specified duration as the lower code value of the minimum code values C min     —     minA  and C min     —     minB . The group code processing module  1490  then generates the code value C reg  based on the code value C min     —     min  and provides the code value C reg  to the control DAC  1422  for generation of a corresponding voltage V reg  as described above. The error amplifier  1424  then compares the voltage V reg  with the voltage V fb  and configures the signal ADJ based on this relationship so as to control the output voltage V OUT  for the following duration. 
     In order to determine the minimum code value C min     —     minA  of the subset A of LED strings for the specified duration, the analog string select module  1472  of the subset segment  1452  continuously selects the minimum tail voltage V TminA  from the tail voltages V T1 , V T2 , V T3 , and V T4  of the LED strings  1441 - 1444 , respectively, and provides this minimum tail voltage V TminA  as a signal  1485  to the ADC  1474  as similarly described above with respect to  FIG. 13 . The ADC  1474  then samples the signal  1485  at corresponding points of time over the specified duration based on a clock signal (not shown) and generates a corresponding code value C A [x] for a code value sequence  1482  from each sampled voltage of the signal  1485  as it is sampled at point x. The digital minimum detect module  1475  determines the lowest code value from the code value sequence  1482  generated by the ADC  1474  for the specified duration as the minimum code value C min     —     minA  for the subset A for the specified duration. 
     Likewise, the analog string select module  1476  of the subset segment  1454  continuously selects the minimum tail voltage V TminB  from the tail voltages V T5 , V T6 , V T7 , and V T8  of the LED strings  1445 - 1448 , respectively, and provides this minimum tail voltage V TminB  as a signal  1487  to the ADC  1478 . The ADC  1478  then samples the signal  1487  at various points of time over the specified duration based on a clock signal (not shown) and generates a corresponding code value C B [x] for the code value sequence  1484  from each sampled voltage of the signal  1487  as it is sampled at point x. The digital minimum detect module  1479  determines the lowest code value from the code value sequence  1484  generated by the ADC  1478  for the specified duration as the minimum code value C min     —     minB  for the subset B for the specified duration. 
     The illustrated segmentation of the feedback controller  1414  permits the feedback controller  1414  to be implemented over a number of IC packages in a manner that permits the feedback controller  1414  to be expanded to accommodate a wide number of LED strings by adding additional IC packages. To illustrate, in one embodiment, the LED system  1400  includes an IC package  1491  in which the control segment  1450  is implemented and two IC packages  1492  in which the subset segments  1452  and  1454  are respectively implemented. In this manner, the feedback controller  1414  can be expanded to include additional subset of LED strings by adding another IC package  1492  to regulate the currents through the LED strings of the additional subset and to generate minimum code value for the additional subset for use by the group code processing module  1490  in determining the overall minimum code value of the LED strings driven by the voltage source  1412 . Thus, assuming the group code processing module  1480  can support up to X IC packages  1492  and each IC package  1492  is capable of supporting up to Y LED strings, the feedback controller  1414  can support up to X*Y LED strings (assuming the voltage source  1412  can provide sufficient power). 
       FIG. 15  illustrates an example segmentation of a feedback controller  1514  (corresponding to the feedback controller  114  of  FIG. 1 ) of a LED system  1500  whereby a code value sequence is separately determined for each subset of LED strings for a predetermined duration and then the overall minimum code value for the plurality of LED strings for the predetermined duration is determined from the minimum code values of the subsets. The LED system  1500  includes a voltage source  1512  configured to drive an output voltage V OUT  to a plurality of LED strings  1541 - 1548  via a bus  1510 . In the illustrated example, the LED strings  1541 - 1548  are segmented into two separate subsets: subset A (LED strings  1541 - 1544 ) and subset B (LED strings  1545 - 1548 ). The voltage source  1512  is controlled via a signal ADJ generated by the feedback controller  1514 . 
     In the depicted embodiment, the feedback controller  1514  is a variation of the feedback controller  1514  such that the feedback controller  1514  is segmented into the control segment  1550  and two subset segments  1552  and  1554  corresponding to subsets A and B, respectively. The subset segment  1552  includes current regulators  1561 - 1564  to regulate the currents through the LED strings  1541 - 1544 , respectively, based on received PWM data (not shown), ADCs  1571 - 1574 , and a digital minimum detect module  1580 . The subset segment  1554  is similarly configured and includes current regulators  1565 - 1568  to regulate the currents through the LED strings  1545 - 1548 , respectively, based on the received PWM data, ADCs  1575 - 1578 , and a digital minimum detect module  1584 . 
     In operation, the subset segment  1552  is configured to generate a minimum code value C min     —     minA  representative of the minimum tail voltage of the tail voltages V T1 -V T4  of the LED strings  1541 - 1544 , respectively, over a specified duration (e.g., a clock cycle, a PWM cycle, an image frame, etc). Likewise, the subset segment  1554  is configured to generate a minimum code value C min     —     minB  representative of the minimum tail voltage of the tail voltages V T5 -V T8  of the LED strings  1541 - 1544 , respectively, over the specified duration. The group code processing module  1590  determines the overall minimum code value C min     —     min  for the specified duration as the lower code value of the minimum code values C min     —     minA  and C min     —     minB . The group code processing module  1590  then generates the code value C reg  based on the code value C min     —     min  and provides the code value C reg  to the control DAC  1522  for generation of a corresponding voltage V reg  as described above. The error amplifier  1524  then compares the voltage V reg  with the voltage V fb  (generated via, e.g., a voltage divider  1526 ) and configures the signal ADJ based on this relationship so as to control the output voltage V OUT  for the following duration. 
     In order to determine the minimum code value C min     —     minA  of the subset A of LED strings for the specified duration, the ADCs  1571 - 1574  of the subset segment  1552  each samples the tail voltages of the corresponding LED strings  1541 - 1544  at corresponding points of time over the specified duration to generate a corresponding set of code value sequences (identified as code value sequences C 1 [x], C 2 [x], C 3 [x], and C 4 [x], respectively). The digital minimum detect module  1580  determines the lowest code value from the code value sequences generated by the ADCs  1571 - 1574  for the specified duration and provides this lowest code value the code value C min     —     minA . The subset segment  1554  operates in a similar manner to determine the minimum code value C min     —     minB  from code value sequences C 5 [x], C 6 [x], C 7 [x], and C 8 [x] generated over the specified duration from the tail voltages V T5 -V T8  of the LED strings  1545 - 1548 , respectively. 
     The illustrated segmentation of the feedback controller  1514  permits the feedback controller  1514  to be implemented over a number of IC packages in a manner that permits the feedback controller  1514  to be expanded to accommodate a wide number of LED strings by adding additional IC packages. To illustrate, in one embodiment, the LED system  1500  includes an IC package  1591  in which the control segment  1550  is implemented and two IC packages  1592  in which the subset segments  1552  and  1554  are respectively implemented. In this manner, the feedback controller  1514  can be expanded to include additional subset of LED strings by adding another IC package  1592  to regulate the currents through the LED strings of the additional subset and to generate a code value sequence for the additional subset for use by the group code processing module  1590  in determining the overall minimum code value of the LED strings driven by the voltage source  1512 . Thus, assuming the group code processing module  1590  can support up to X IC packages  1592  and each IC package  1592  is capable of supporting up to Y LED strings, the feedback controller  1514  can support up to X*Y LED strings (assuming the voltage source  1512  can provide sufficient power). 
     The term “another”, as used herein, is defined as at least a second or more. The terms “including”, “having”, or any variation thereof, as used herein, are defined as comprising. The term “coupled”, as used herein with reference to electro-optical technology, is defined as connected, although not necessarily directly, and not necessarily mechanically. 
     Other embodiments, uses, and advantages of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. The specification and drawings should be considered exemplary only, and the scope of the disclosure is accordingly intended to be limited only by the following claims and equivalents thereof.