Patent Publication Number: US-3970867-A

Title: Synchronous counter/divider using only four NAND or NOR gates per bit

Description:
The present invention relates to electronic logic circuits and more particularly to so-called &#34;flip-flop&#34; circuits which change their state, from &#34;on&#34; to &#34;off&#34; or from off to on, in response to an input trigger pulse and applied control pulses. 
     Flip-flop circuits of various types are well-known in the prior art and belong generally to the class of circuits often called multivibrators which are used in large numbers in logic or control systems such as special or general-purpose digital computers, electronic calculators, digital electronic switching systems or digital electronic control systems. 
     The basic building blocks of any digital electronic system are a class of circuits known as &#34;gate&#34; circuits. These circuits are designed to provide an output in response to a specific set of signal conditions existing at their one or more inputs. Various gate circuits are designated according to the logic function performed such as, for example, AND, OR, NAND or NOR gates. 
     Although logic circuits and systems can be constructed from individual components such as signal translators (transistors or vacuum tubes), resistors, capacitors, etc. in modern practice they are embodied in integrated circuits wherein all elements of the circuit are formed in or on a small &#34;chip&#34; of semiconductor material. Often, many such circuits are formed on a single piece of semiconductor material to form a complete complex electronic system embodying hundreds or thousands of circuits. Such devices are commonly referred to as LSI (Large Scale Integration) devices. 
     In LSI devices, as in most electronic systems, reducing the number of elements required to perform a given function leads generally to reduced manufacturing cost, reduced operating cost and power consumption and, often, enhanced reliability. 
     By the present invention, a bistable multivibrator or flip-flop function is provided using only four gates together with a clock signal shaping circuit rather than the six or more gates commonly used to provide such a function in the prior art. The flip-flop of the present invention comprises a pair of NAND or NOR gates interconnected to form an output latch. Input to the latch is provided by two additional gates of the same type interconnected to provide set/reset gating steered by the output of the latch and a clock pulse generator. The clock pulse generator function can be supplied under most conditions by only one additional gate. 
     The novel flip-flop circuit of the present invention can be used to provide novel logic circuits such as counter/divider circuits, programmable dividers and others with saving in semiconductor chip size required in LSI devices approaching 33%. 
     In such a counter/divider circuit each stage consists of only four gates forming a flip-flop circuit of the type above-disclosed. All of the stages are triggered simultaneously from a common clock pulse generator while the preset or clear function signals are provided in parallel to all stages. By adding one loading gate per stage, one enable gate per stage for each bit over two and a JK flip-flop output stage to the counter/divider circuit a very fast low cost programmable divider circuit is provided. 
     Use of the novel flip-flop circuit of the present invention in integrated circuits and LSI devices results in significant savings in the manufacturing costs and enhances the reliability of such devices. 
    
    
     Further details and advantages of the present invention will become obvious from the following detailed description when read in connection with the accompanying drawings in which: 
     FIG. 1 is a schematic diagram depicting the novel flip-flop circuit of the present invention; 
     FIG. 2 is a pulse diagram helpful in understanding the operation of the circuit of FIG. 1; 
     FIG. 3 is a schematic diagram of a novel counter/divider circuit using the flip-flop circuit of FIG. 1; 
     FIG. 4 is a schematic diagram of a novel programmable divider circuit using the flip-flop circuit of FIG. 1; and 
     FIG. 5 is a pulse diagram helpful in understanding the operation of the circuit of FIG. 4. 
    
    
     The flip-flop circuit of the present invention is shown in FIG. 1. It comprises a simple inverter G 1 , two four-input NAND or inverting AND gates G 2  and G 3  and two three-input NAND or inverting AND gates G 4  and G 5 . The input and output terminals of the circuit are designated by standard nomenclature as input terminals CK (clock), J, K, CL (clear) and P (preset) and output terminals Q and Q. Clock input terminal CK is connected directly to the input 10 of gate G 1  and inputs 22 and 32 of gates G 2  and G 3  respectively. The output of inverter gate G 1  is connected directly to inputs 23 and 33 of gates G 2  and G 3  respectively. The J input terminal is connected directly to input 21 of gate G 2  and the K input is connected directly to input 31 of gate G 3 . 
     The outputs of inverting gates G 2  and G 3  are connected directly to inputs 42 and 52 respectively of gates G 4  and G 5 . The preset input terminal, P, is connected directly to input terminal 41 of gate G 4  and the clear input terminal CL is connected directly to input 51 of gate 5. The output of inverting gate G 5  is connected directly to the output terminal Q as well as to input terminals 43 of gate G 4  and 24 of gate G 2  while the output of inverting gate G 4  is connected directly to output terminal Q as well as to the input 53 of gate G 5  and input 34 of gate G 3 . The circuit of FIG. 1 constitutes an edge-triggered JK flip-flop. 
     Gates G 1  through G 5  may be of any known types especially those known to be well-adapted for use in semiconductor integrated circuits such as, for example, those types known as TTL (transistor transistor logic) or I 2  L (integrated injection logic). It is preferable that all of these gates be the same type construction so as to facilitate the embodiment of all of the gates in a single integrated circuit element. 
     The operation of the circuit of FIG. 1 is best explained with reference to the pulse diagram of FIG. 2. By standard positive logic nomenclature the output of each of the inverting AND gates G 2  through G 5  will be logic 1 or high when any one or more of its inputs is logic 0 or low. Only when all of the inputs to one of these gates are high or logic 1 will the output of that gate change to logic 0 or low. The output of gate G 1  is 1 when the input is 0 and 0 when the input is 1. The propagation delay time, hereinafter referred to as T pd  is the time required for a change in the gate input conditions to be manifested in a change in output conditions of that gate and for purposes of this invention is assumed to be the same for all gates of the circuit. 
     It will be assumed for purposes of explanation that a logic 1 is applied to terminals J, K, CL and P of the circuit of FIG. 1 and output Q is producing a logic 1 and Q is producing logic 0. A clock signal of the type indicated by pulse diagram 11 in FIG. 2 is applied to input CK and thus appears at gate inputs 10, 22 and 32 as indicated by 11 in FIG. 1. The resulting output signal of gate G 1  indicated by pulse diagram 12 in FIG. 2 is applied to inputs 23 and 33 of gates G 2  and G 3  respectively as indicated by 12 in FIG. 1. Output signals 13 and 14 of FIG. 2 are produced by gates G 3  and G 2  respectively and applied to inputs 52 and 42 of gates G 5  and G 4  respectively as indicated by 13 and 14 in FIG. 1. Gate G 5  produces output signal 15 of FIG. 2 which is applied to output terminal Q and gate inputs 24 and 43 as indicated by 15 . Gate G 4  produces output signal 15 of FIG. 2 which is applied to output terminal Q and gate inputs 34 and 53 as indicated by 16 . 
     As a starting point, explanation of the operation of the circuit of FIG. 1 will begin at a time designated T O  in FIG. 2. At time T O  signals 11 and 15 (Q) are 0 and signals 12, 13, 14 and 16 (Q) are 1. At T 1  clock signal 11 goes to 1. After the gate propagation delay time or 1T pd  the output of gate G 1  goes to 0 as shown at time T 2  in response to the 1 input to that gate. Thus, during the time period between T 1  and T 2  all inputs, 31, 32 (11), 33 (12) and 34 (Q) are at logic 1 level with the result that after 1T pd  period or at time T 2  the output signal of gate G 3  (13) will change from 1 to 0. Gate G 2  is unaffected by the changes to its inputs 22 and 23 at the time T 1  and T 2  since the Q signal to input 24 remains at 0 during this time holding gate G 2  output signal 14 at 1. 
     After one more propagation delay period, i.e. at T 3 , G 3  output signal 13 returns to 1 in response to signal 12 at input 33 dropping to 0 at T 2  as explained above. Also at T 3  output signal 15 (Q) of gate G 5  goes to 1 in response to input 52 (signal 13) dropping to 0 during the time T 2  to T 3 . At the time T 3  all three inputs 41, 42 and 43 become 1 and so after one T pd  or at T 4  output Q (signal 16) drops to 0. 
     The transition of the clock signal 11 from 1 to 0 at T 5  and the resulting transition of signal 12 from 0 to 1 at T 6  have no effect on the outputs of gates G 2  through G 5  since at least one input to each of gates G 2 , G 3  and G 5  will be at 0 from T 5  through T 7  and all inputs of G 4  remain at 1. 
     The next 0 to 1 transition of clock signal 11 at T 7  produces another &#34;toggle&#34; of the circuit outputs Q and Q. From FIG. 2 it can be seen that the output 12 of gate G 1  changes at T 8 , output 13 of gate G 3  is unaffected, output 14 of gate G 2  drops to 0 at T 8  and returns to 1 at T 9 , output 16 (Q) changes to 1 at T 9  and, finally, output 15 (Q) changes to 0 at T 10  thus completing one output cycle. The next transitions of signals 11 and 12 at T 11  and T 12  return the entire circuit to its assumed starting condition of T O . 
     From the diagrams of FIG. 2 it can be seen that the positive-going transition of the outputs Q and Q occur at T 3  or just two propagation delay periods after the positive-going transition of the input clock signal at T 1  while the negative-going transitions in the outputs of Q and Q occur at T 4  or just three T pd  after the positive-going transition of the input clock signal. Proper operation requires only that the next positive transition of the clock pulse does not occur before the negative-going transition of the output pulse at Q or Q which is in response to the previous positive clock pulse transition. Thus, clock frequencies as high as ##EQU1## may be used as input to the circuit of FIG. 1. 
     Further, those skilled in the art will recognize that NAND gates G 2 , G 3 , G 4  and G 5  may be replaced by NOR gates if the J and K inputs are replaced by J and K inputs respectively and the CL and P inputs are replaced by CL and P inputs respectively. In such a circuit toggle action would be initiated by the negative-going edge of the clock signal. 
     The flip-flop circuit of the present invention finds its most advantageous uses in LSI devices and systems such as, for example, counters and dividers. 
     Using the principles disclosed in connection with the construction of the flip-flop circuit of FIG. 1, a synchronous counter/divider provided with preset and clear inputs can be constructed using only four NAND or NOR gates per stage. Such a counter/divider is shown in FIG. 3. In the counter of FIG. 3 all counter stages are clocked simultaneously from the clock pulse generator 151. Use of this clock pulse generator in this manner allows elimination in each stage of the counter of one inverter gate (G 1  in FIG. 1) and two inputs (22 and 32) to each flip-flop. Although the clock pulse generator uses a Schmitt trigger circuit 152, and inverter 153 and a NOR gate 154 to generate the clock impulse inputs, its use provides a substantial savings in the area required on a semiconductor integrated circuit chip to provide a counter of a given length. For example, most present day counters use six gates per stage so the saving in area required per counter would be equal to the area of the two gates times the number of stages of the counter less the area for the clock pulse generator. In longer counters requiring a large number of stages, the area savings offered by the counter of FIG. 5 approaches 33% from present counters. 
     The clock pulse to be provided by the clock pulse generator, which must be negative-going for the NAND gate embodiment shown in FIG. 3 or positive-going for the NOR gate embodiment, must be of sufficient length to trigger one gate but less than two gate propagation delay times. A clock generator output pulse of from 1.2 to 1.8 T pd  has been found satisfactory. 
     Of course, the propagation delay times of different gates, even of the same construction on the same semiconductor chip, may be slightly different. Thus the minimum clock pulse width must be equal to or longer than the T pd  of the slowest gate in any driven flip-flop. The maximum clock pulse width must be equal to or shorter than the sum of the T pd  &#39;s of the two fastest gates in any driven flip-flop. 
     Thus, the inverter 153 may comprise a &#34;standard&#34; one input NAND gate with its propagation delay time lengthened about 40% by a change in resistor values from standard, by slight increase in transistor size or by the addition of a very small capacitance. The Schmitt trigger circuit is necessary only to insure constant rise times when the clock pulses are to be supplied from an unknown source and thus will have an unknown shape. If it is known that the clock pulses will be of a specified quality and of a sharp rise time, the Schmitt trigger 152 may be omitted. 
     Each stage of the circuit of FIG. 3 then operates in a manner similar to the circuit of FIG. 1. Use of the clock pulse generator, however, saves one gate and two gate inputs per stage and allows a clock frequency with a period as low as about 3 T pd . 
     Each stage of the counter of FIG. 3 is a four gate flip-flop circuit of the type shown in FIG. 1 with slight modifications. In Stage A, for example, the J and K inputs for gates G 2A  and G 3A  respectively are unnecessary and are therefore omitted. In Stage B the J and K inputs are connected together and constitute an &#34;enable&#34; input receiving the Q A  output over line 155. Stage C has additional J and K inputs connected together as an additional enable input receiving the output of Q B  on line 156. Both Q B  output and Q A  output, line 157, are required to enable Stage C. Additional enable inputs are required for each higher order stage of the counter. Preset and clear signals are supplied to all stages of the counter over lines 158 and 159 respectively. Clock pulses from the clock pulse generator 151 are fed to all stages of the counter simultaneously over line 160. Counter output is taken from the terminals Q A , Q B , Q C  . . . Q N . 
     Inspection of the circuit of FIG. 3 will show that Stage A is always enabled and will &#34;toggle&#34; or count at each clock pulse. Stage B is enabled only when the output of Stage A, Q A , is 1 and will therefore toggle or count every second clock pulse. Likewise, Stage C is enabled only when both Q A  and Q B  are 1 and will count only every fourth clock pulse. Thus, the binary count of outputs Q A , Q B , Q C . . . Q N  advances 1 with each input clock pulse in the well-known manner. 
     By adding a few input and enable gates together with an output flip-flop to the synchronous count of FIG. 3 a programmable divider is provided. 
     The programmable divider of FIG. 3 is a synchronous down counter comprised of the T flip-flops A , B , C , . . . N . Each of these flip-flops are of the type shown in FIG. 1 with the J and K inputs both connected to the T or enable input terminal. The counter is preset to the desired divisor by the gate G L  and the input D to each stage. (An inverter I is inserted between input D A  and gate G LA  for reasons to be explained later.) For example, if it is desired to divide the input clock frequency by five, a logic 1 is applied to the DA and the D C  inputs and logic 0 to all of the other D inputs. Thus, when the Q output of the output flip-flop S is logic 1, gate, G L  of each stage applies the D input either 1 or 0 to the P input of that stage with the exception of Stage A in which the D input is applied to the CL input. The counter then begins to count down from the loaded number (divisor). 
     When the counter has counted down to 0 . . . 002, the Q outputs of all of the counter stages except B go to 0 so that all of the J inputs, J 1 , J 2  and J 3  of the flip-flop S , become 1 at a time which is two T pd  after the positive transition of the clock pulse which brings the counter to the count 0002. 
     The next clock pulse brings the counter to 0001 and simultaneously sets the flip-flop S . Q of flip-flop S therefore goes high two T pd  after the positive edge of this clock pulse and Q S  goes low three T pd  after the positive edge of this clock pulse thus disabling flip-flop A . When Q S  goes high a 1 is applied through the load line to one of the inputs of each of the gates G LA  . . . N. Thus, one T pd  after the load line goes to 1 the appropriate inputs from the D terminals have been applied to all stages of the counter. By two T pd  later all of the flip-flops of the counter have latched to the output state depicting the D inputs or division number and the counter is again loaded. Thus, by five T pd  after the positive-going edge of the last or fifth clock pulse and before the positive-going edge of the next or first clock pulse the counter is again set to the prescribed divider ratio value. After one additional T pd  (for gates G E ) the T inputs of all the flip-flops are settled. The counter is enabled again two T pd  after the positive edge of the first clock pulse, i.e., when Q S  goes to 1, and the countdown cycle starts again. 
     The above sequence of events is depicted by the pulse diagram of FIG. 5 representing the logic states of various terminals of the counter set to divide the clock pulse rate by 5. At time T -   1 , just before the first clock pulse, the counter has been loaded to 5 (Q  A  = 1, Q B  = 0, Q C  = 1, remaining stage Q&#39;s equal 0). The clock pulse period for these diagrams is two T pd , the maximum. The clock frequency is 1/6 T pd . At T O  clock pulse 1 begins. The counter flip-flops are disabled, i.e., all T&#39;s equal 0, and therefore their outputs do not change. Since K is equal 1 flip-flop S toggles with Q S  and T A  becoming 1 at T 1  and Q S , K and the load line going to 0 one T pd  thereafter at T 2 . (Note the clear and preset inputs would be held for one additional T pd .) At the positive edge of the second clock pulse, T 3 , only counter stage A is enabled (T A  - 1) thus at T 4 , Q A , J 1  and T B  become 1, at T 5  Q A  becomes 0 and T C  becomes 1 resulting in a counter state of 0100 or 4. At T 6  the third clock pulse begins. Flip-flops A , B , and C all being enabled (T A , T B  and T C  = 1) will toggle with Q A  and Q B  becoming 1 at T 8  and Q A , J 1 , T  B , Q C  and T C  all becoming 0 at T 9 . At the same time J 3  becomes 1. The counter now registers 0011 or 3. 
     The positive edge of the fourth clock pulse occurs at T 10  when flip-flop A (only) is enabled (Q S  and T A  at 1; T B , T C , T D  at 0). In response to this clock pulse flip-flop A toggles and Q A , J 1  and T B  go to 1 at T 11  and Q A  to 0 at T 12  changing the counter output to 0010 or 2. At the positive edge of the fifth clock pulse at T 13 , J 1 , J 2  and J 3  are all at 1 as well as T A  and T B . Thus flip-flops A , B and S all toggle with Q A , Q S , K and the load line all becoming 1 at T 14 . One T pd  later at T 15  Q A , J 1 , T B , Q B , J 2 , Q S  and T A  all drop to 0. Immediately after T 15  the counter output is 0001, the output pulse at Q S , indicating that five clock pulses have occurred, has begun. Thus, the counting cycle is complete. 
     Between the time T 14  and the positive edge of the next clock pulse (the next T O ) the counter is again loaded with the divisor number (5) to begin the next counting cycle as follows. 
     At T 14  which is at or after the negative edge of the fifth clock pulse, the load line becomes 1 and one T pd  later Q S  goes to 0 disabling A . One T pd  after the load line becomes 1 the D inputs are applied through the gate G L  to the preset or clear inputs of the counter stages and after one additional T pd  the stage outputs which must change from 0 to 1 have been set. Thus, the counter has been reset to its &#34;initial&#34; condition by T O  &#39;. It should be recognized that if the divider ratio is an even number D A  will be 0 and therefore it will require a total line of six T pd  from the beginning of the &#34;last&#34; clock pulse for the T inputs of all the flip-flops to assume their correct condition for the next or &#34;first&#34; clock pulse at T O  &#39; to trigger correctly. 
     The load circuit of the programmable counter is much less complex and faster than comparable circuits for many present counters in that only one gate per stage is required. Since all stages of the counter except A will always be at 0 after the last clock pulse it is required only that the 1&#39;s at the D terminals be loaded and possibly a 0 to stage A depending on the divisor to be loaded. Thus, the outputs of B and all subsequent stages will be latched to the loaded divisor and ready to begin counting within 2 T pd  after the load pulse (Q S ) begins. Stage A will be loaded and latched within 3 T pd  after the load pulse begins but this longer time is not restrictive on the speed of the divider since stage A is disabled for the duration of the load pulse which overlaps the first clock pulse. 
     It should be noted that the timing shown in the pulse diagrams of FIG. 5 is applicable for T 2  L circuit construction in which NOR gates such as G L  have the same propagation delay time as the other gates. The timing would be slightly different were the counter of I 2  L construction in which the propagation delay time of NOR gates would be 0. 
     Thus, there have been disclosed novel logic circuits incorporating a novel four-gate flip-flop circuit which offers substantial savings in the space required to implement the circuit on integrated circuit semiconductor chips and, therefore, provides a substantial saving in manufacturing cost of such devices.