Patent Publication Number: US-7592789-B2

Title: Power supply and related circuits

Description:
RELATED APPLICATIONS 
   This application is a continuation in part of earlier filed U.S. patent application Ser. No. 11/261,661, entitled “DIGITAL CONTROLLER FOR A VOLTAGE REGULATOR MODULE,”, filed on Oct. 31, 2005 now U.S. Pat. No. 7,456,618, the entire teachings of which are incorporated herein by this reference. 
   This application is also a continuation in part of earlier filed U.S. patent application Ser. No. 11/261,660, entitled “DYNAMIC CONVERSION CIRCUIT FOR A VOLTAGE REGULATOR MODULE,” filed on Oct. 31, 2005, the entire teachings of which are incorporated herein by this reference. 

   FIELD OF INVENTION 
   The invention generally relates to a voltage regulator module (VRM), and particularly to control methods and devices for enhancing the transient response of a VRM under dynamic load conditions. 
   BACKGROUND 
   A voltage regulator module (VRM) is used to regulate a DC voltage supplied to a load, such as microprocessor. A VRM includes a power converter, such as a DC-DC converter, and may include other components such as a controller for controlling operation of the power converter. An example of a DC-DC converter is a synchronous buck converter, as shown in  FIG. 1 , which has minimal components, and therefore is widely used in VRM applications. In microprocessor applications, the input voltage to the VRM is typically 12V DC . The output voltage may be 5.0V DC , 3.3 V DC , or lower. 
   As microprocessors become more advanced, required supply voltages become lower. Supply voltages are expected to be as low as 0.5 V DC  in the near future, which will require currents up to 200 A or more. Currently, the CPU of a typical personal computer operates at 3 GHz, and operating frequencies are expected to reach 10 GHz in the near future. A consequence of the low supply voltage and high clock frequency is the high slew rate (di/dt) of the load current at power up. For example, when a microprocessor wakes from sleep mode to full operating mode, the step of the output current may be as high as 200 A, with a slew rate of 1,000 A/μs or higher. The slew rate may be over 1,000 A/μs in future designs. The voltage supplied to current microprocessors is required to be regulated within 2%, and 1% for future VRMs (“VRM 9.1 DC-DC converter design guidelines”, Intel Order Number 298646-001, January 2002). The absolute value of such voltage regulation is currently 30 mV and 10 mV for future designs. Such tight voltage regulation is required to maintain normal operation of CMOS transistors in the microprocessor under all conditions. For instance, under worst case (high slew rate of the output current) conditions, the output voltage should not drop by more than 30 mV to avoid abnormal operation of the CPU. However, the voltage drop of VRMs based on existing designs may be so large that the output voltage regulation limit may easily be exceeded. 
   Various VRM topologies and control methods have been proposed in an attempt to satisfy the transient response requirements of microprocessors. However, such designs are not well-suited to the harsher dynamic requirements of next generation microprocessors. 
   For example, simply increasing the output capacitance can reduce the output voltage ripple, and also help maintain the output voltage during a sudden load change. However, for a single phase 1.5 V DC /25 A VRM, for instance, a design that can meet the steady state and and transient voltage regulation specification typically requires at least 5,000 μF output capacitance. Such filter capacitors are bulky and expensive. It is estimated that for a VRM supplying 0.5 V DC  at 100 A, the required output capacitance would be more than 10,000 μF, and should have considerably lower equivalent series inductance (ESL) and equivalent series resistance (ESR) to be effective during load transients.  FIG. 2  (top curve only) shows such a relationship between the output capacitance and load current for typical prior VRMs. Although multiphase topology, which helps to reduce output capacitance, may be used for applications when the load current exceeds 20 A, the value of the capacitance is still exceedingly high at high load current. 
   Reducing the output inductance of a buck converter can improve its dynamic response. However, the inductance can not be reduced unbounded, otherwise the output voltage ripple will increase above acceptable limits (e.g., above 10 mV for next generation microprocessors). The increased voltage ripple will in turn reduce the room for the output voltage drop during load dynamics. In addition, a larger ripple current through the filter inductor implies a larger RMS current through the power switches, which will reduce the overall efficiency of the VRM under steady state operation. Moreover, even though the inductance can be reduced for a faster dynamic response, it is not enough to provide adequate response speed for future microprocessors if the output capacitance is required to be small to reduce cost and to satisfy size and volume constraints. 
   Multiphase interleaved VRM topology provides two or more power converters in parallel and shares the same output capacitors among converters. In each of the power converters (or each phase), the filter inductor can be smaller than that of a single phase VRM to achieve a faster dynamic response. The large output voltage ripple in each phase due to the small inductance can be cancelled by the ripple of other phases. The more phases are in parallel, the smaller the ripple will be, but at the expense of increased circuit cost. Multiphase topology can therefore enhance the output current capability of a VRM. However, if the output current can be provided by a single phase VRM or a VRM with fewer phases, then adopting a multiphase topology or adding extra phases in parallel solely for the purpose of reducing the ripple voltage adds considerable complexity, size, and cost. More importantly, it is very difficult for a conventionally-controlled multiphase VRM to achieve the dynamic response required by future microprocessors, without having very large output capacitance. 
   Current mode control has a faster dynamic response than that of conventional voltage mode control in situations where only a small perturbation such as a small load change occurs. However, its dynamic performance is not superior to that of voltage mode control when a large transient occurs. More importantly, in current mode control, the current is detected by employing a sensing resistor or a current transformer. However, for an output current of 100 A or higher, it would be impractical to use a resistor to accurately and efficiently sense the current. On the other hand, a current transformer is bulky and the sensed current must be averaged, resulting in further increases in the reaction time and drop in the output voltage when a large load step happens. 
   The voltage droop control method takes advantage of the upper and lower limits of the VRM output voltage to gain more room for dynamic responses. When the load current is low, the reference voltage is set to be higher than the nominal value but still within the specified upper limit. When a load step-up happens, the output voltage will drop but will have more room to drop than if it were starting from the nominal value. When the load current is high, the reference voltage is set to be low; thus when a load step-down happens, the output voltage has more room for the overshoot. However, this small room is far from being enough to handle the harsh dynamic requirements of next generation microprocessors. Moreover, the voltage droop control method also requires current sensing, which again is not very practical, as discussed above. 
   Operating the power converter at a very high frequency will improve the dynamic response of a VRM having a very small output capacitance. However, design of an efficient power converter operating at a very high frequency is difficult. Further, the efficiency of a power converter decreases eventually to an unacceptable or unsatisfactory level as its operating frequency increases. In general, increasing the switching frequency of a power converter solely for the purpose of improving the dynamic performance is not an optimum solution. 
   A stepping inductor method for fast transient response of switching converters is disclosed in U.S. Pat. No. 6,188,209, issued Feb. 13, 2001 to Poon et al. Relative to the basic buck converter, this design requires significantly more circuit components, which may be difficult and expensive to implement in a multiphase interleaved VRM, because all of the components need to be repeated for each phase. Moreover, the control circuit for load transients is analog based and the output voltage is compared to fixed hysteresis reference voltages to trigger and terminate the transient operation of the converter independently of the load current conditions. This implies that the transient circuit works the same way for a 25%, 50%, and 100% load step, for instance. Therefore, the voltage response during a load transient is not regulated and may exceed the specified limits of the output voltage during many load conditions. 
   A transient override circuit is proposed in U.S. Pat. No. 6,696,882, issued Feb. 24, 2004 to Markowski et al. This circuit detects the load voltage level to trigger a transient operation mode of the VRM. In transient operation mode, the power switch of a buck converter is forced to be turned on, and the synchronous power switch of the buck converter is turned off, to override the current through the output inductor. However, the circuit and control method are analog based, and, importantly, are not able to regulate the output voltage during the transient. 
   Peterchev et al. (“Architecture and IC implementation of a digital VRM controller”,  IEEE Transactions on Power Electronics,  18 (1):356-364, 2003) relates to a digital controller for a dc-dc switch mode converter. However, the reference focuses on digital control only for normal steady state operation. Saggini et al. (“An innovative digital control architecture for low-voltage, high current dc-dc converters with tight voltage regulation”,  IEEE Transactions on Power Electronics,  19 (1):210-218, 2004) addresses digital control for improving the transient response of a VRM. However, this reference teaches a variable frequency control method in combination with voltage droop control, which requires accurate sensing of the load current. U.S. Patent Publication No. 2004/015098, published Aug. 5, 2004, relates to a digital controller for a VRM; however, some of the operations carried out by this controller are effected through analog circuitry. 
   SUMMARY 
   According to one aspect of the invention there is provided a digital controller for a switching DC-DC converter of a voltage regulator module, comprising: a voltage sensor for sensing an output voltage of the DC-DC converter and generating a corresponding digital signal; means for determining an expected output current of the DC-DC converter from the digital signal; and means for generating at least one gate signal when: (i) the expected output current is greater than an operating current; and/or (ii) the sensed output voltage is less than a threshold output voltage; wherein the at least one gate signal is provided to at least one switch of the DC-DC converter, the at least one gate signal turning on a first switch that increases current output of the DC-DC converter and/or turning off a second switch that limits output current of the DC-DC converter. 
   In one embodiment, the means for generating at least one gate signal may generate a gate signal for each switch in the DC-DC converter. 
   The DC-DC converter may be of an isolated or a non-isolated topology, such as boost, buck, or buck-boost. In a preferred embodiment, the DC-DC converter is a buck converter. 
   In one embodiment, the voltage regulator module may include a dynamic conversion circuit, and the means for generating at least one gate signal generates a gate signal for at least one switch in the dynamic conversion circuit. In another embodiment the means for generating at least one gate signal may generate a gate signal for each switch in the dynamic conversion circuit and for at least one switch in the DC-DC converter. 
   The at least one gate signal may be a pulse train of higher frequency than a switching frequency of the DC-DC converter. The at least one gate signal may be pulse width modulated. 
   In a further embodiment, two or more switching DC-DC converter circuits may be included in the voltage regulator module, wherein the means for generating at least one gate signal comprises means for generating a gate signal for at least one switch of each DC-DC converter. The voltage regulator module may include a dynamic conversion circuit, and the means for generating at least one gate signal may comprise means for generating a gate signal for each switch in the dynamic conversion circuit and for at least one switch of each DC-DC converter. The two or more DC-DC converters may be of an isolated or a non-isolated circuit topology. Preferably, at least one DC-DC converter is a buck converter. 
   According to another aspect of the invention there is provided a method for digitally controlling a voltage regulator module including a switching DC-DC converter, comprising: sensing an output voltage of the DC-DC converter and generating a corresponding digital signal; determining an expected output current of the DC-DC converter from the digital signal; generating at least one gate signal when: (i) the expected output current is greater than an operating current; and/or (ii) the sensed output voltage is less than a threshold output voltage; and providing the at least one gate signal to at least one switch of the DC-DC converter of the voltage regulator module; wherein the at least one gate signal turns on a first switch that increases current output of the DC-DC converter and/or turns off a second switch that limits output current of the DC-DC converter. 
   In one embodiment, the method may further comprise generating a gate signal for each switch in the DC-DC converter. 
   In one embodiment, the voltage regulator module may include a dynamic conversion circuit, the method further comprising generating a gate signal for a switch of the dynamic conversion circuit. In another embodiment the method may further comprise generating a gate signal for a switch in the dynamic conversion circuit and for at least one switch of the DC-DC converter. 
   In accordance with the method, the DC-DC converter may be of an isolated or a non-isolated topology, such as buck, boost, or buck-boost. In a preferred embodiment, the DC-DC converter is a buck converter. 
   In one embodiment, the method may further comprise generating the gate signal as a pulse train of higher frequency than a switching frequency of the DC-DC converter. The method may further comprise pulse width modulating the gate signal. 
   In another embodiment, the voltage regulator module may include two or more DC-DC converters, the method further comprising generating at least one gate signal for at least one switch of each DC-DC converter. The method may further comprise generating a gate signal for each switch in each DC-DC converter. The voltage regulator module may include a dynamic conversion circuit, and may further comprise generating a gate signal for a switch in the dynamic conversion circuit. The method may further comprise generating a gate signal for at least one switch in each DC-DC converter and for a switch in the dynamic conversion circuit. Each DC-DC converter may be of an isolated or a non-isolated circuit topology, such as buck, boost, or buck-boost. At least one DC-DC converter can be a buck converter. 
   In some embodiments of the method, determining an expected output current of the DC-DC converter from the digital signal may comprise calculating the output current from a linear or a non-linear function. In other embodiments, determining an expected output current of the DC-DC converter from the digital signal may comprise determining a corresponding current value from a look-up table. 
   According to another aspect of the invention there is provided a voltage regulator module comprising at least one DC-DC power converter circuit and a digital controller as described herein. The voltage regulator module may further comprise a dynamic conversion circuit as described herein. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The foregoing and other objects, features, and advantages of the invention will be apparent from the following more particular description of preferred embodiments herein, as illustrated in the accompanying drawings in which like reference characters refer to the same parts throughout the different views. The drawings are not necessarily to scale, with emphasis instead being placed upon illustrating the embodiments, principles and concepts. 
       FIG. 1  is a schematic diagram of a prior art single phase synchronous buck converter; 
       FIG. 2  is a plot of estimated output capacitance versus load current for the invention compared with prior art VRMs; 
       FIG. 3  is a schematic diagram of a single phase VRM circuit including a digital controller according to an embodiment of the invention; 
       FIG. 4  is a block diagram of a digital controller for a single phase VRM according to the invention; 
       FIG. 5  is a plot of single phase VRM waveforms during the steady state and during a transient state according to the control method of the invention; 
       FIG. 6  is a flow chart of the control algorithm of an embodiment of a digital controller according to the invention; 
       FIG. 7  is a schematic diagram of a multiphase interleaved VRM with a dynamic conversion circuit and a digital controller according to the invention; 
       FIG. 8  is a block diagram a digital controller for a multiphase VRM embodiment; 
       FIG. 9  is a plot of multiphase VRM waveforms during steady state and during a transient state according to the control method of the invention; 
       FIG. 10  is a plot of the load current change ΔIo as a function of the output voltage slew rate dv/dt; and 
       FIG. 11  is a plot showing the results of a simulation comparing the output voltage waveforms of a VRM of the invention and a conventional voltage mode controlled VRM during a load transient, in which V g =12 V DC , V o =1.5 V, I o =25 A, C o =500 μF, f s =250 kHz, and the load steps from 0.5 A to 25 A. 
       FIG. 12  is an example diagram of a power supply system according to embodiments herein. 
       FIG. 13  is a diagram of an example circuit architecture for implementing power supply circuitry according to embodiments herein. 
       FIG. 14  is a diagram of an example flowchart for implementing a power supply system according to embodiments herein. 
       FIG. 15  is a diagram of an example power supply system in which the controller circuit and the dynamic power supply circuit reside in a corresponding integrated circuit according to embodiments herein. 
       FIG. 16  is a diagram of a power supply system in which the controller circuit, dynamic power supply circuit, and a load such as a microprocessor reside in a corresponding integrated circuit according to embodiments herein. 
   

   DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
   Digital control has many advantages over analog control in a power converter. One of the most important advantages relates to the flexibility of digital control. Various control schemes that may be difficult to implement in analog control become feasible when digital control is applied. However, no previous digital controllers for VRMs provide satisfactory solutions for transient load conditions, particularly the transients expected to be presented by future microprocessors. 
   A digital controller as described herein provides a novel solution to the control of a VRM during transients, by employing voltage sensing of the VRM output voltage. By sensing minute changes in the output voltage, and relating the output voltage to the corresponding required output current (e.g., predicting the output current from the sensed output voltage), a digital controller as described herein may respond quickly to sudden demands for current that would otherwise result in a substantial drop in output voltage, compromising performance of the load. As exemplified by the embodiments described herein, the digital controller of the invention has been optimized to work in conjunction with either a dynamic conversion circuit and a power converter, such as a buck converter, or with only a power converter, as use of the digital controller to enhance performance of any power converter may be accomplished with only minor modifications to the embodiments described herein. 
   By implementing the digital controller and the control method of the invention, increasing the switching frequency of the DC-DC converter is unnecessary, because an increased switching frequency does not further improve the dynamic response of the converter. The switching frequency may be kept below 500 kHz to achieve a higher efficiency and at the same time maintain a very fast dynamic response with greatly reduced output capacitance. The greatly reduced output capacitance enables the use of ceramic capacitors, which are smaller in size and have a much smaller equivalent series resistance (ESR). Consequently, a VRM according to the invention will require less space on a PCB and cost will be reduced. Further, the digital implementation offers great flexibility, including external programming, such that no analog components need to be substituted under different conditions. Factors such as tolerance, temperature, and aging of components have no effect on components such as the compensator due to the digital implementation. 
   According to one aspect of the invention there is provided a voltage regulator module, comprising a power conversion circuit, an optional dynamic conversion circuit, and a digital controller. The load may be of various devices that require tight output voltage regulation. A microprocessor is an example of such a load due to its large current consumption and the extreme load transients it presents to the VRM. For these reasons, a microprocessor will be considered as the load for the VRM in this disclosure. The power conversion circuit of the VRM is power converter, typically a DC-DC voltage converter such as a synchronous buck converter, but is not limited thereto. Other isolated and non-isolated power converter circuits, such as, for example, boost and buck-boost, may also be used. The power converter may be single phase or multiphase interleaved to regulate the output voltage, depending on how much load current is needed. 
   The dynamic conversion circuit is a circuit capable of responding rapidly to sudden changes in the load connected to the VRM output. A sudden change in the load, such as an increase in current consumption, results in a decrease in the output voltage from its nominal value. Such a load transient represents a deviation in output current of the power converter from its operating current (i.e., steady-state current). The dynamic conversion circuit responds to such transient decreases in output voltage by transiently increasing the output current of the DC-DC converter, thereby preventing further decreases in output voltage. Thus, the dynamic conversion circuit substantially improves the voltage regulation of the VRM under dynamic load conditions. An example of a suitable dynamic conversion circuit is set forth in our co-pending U.S. patent application Ser. Nos. 11/261,660 and 11/261,661, the entire teachings of are incorporated herein in their entirety. Such a dynamic conversion circuit may be used with any isolated or non-isolated switching DC-DC converter, such as, for example, buck, boost, or buck-boost, single phase or multiphase interleaved, for any load requiring tight voltage regulation under both steady-state and transient conditions. 
   In the embodiment shown in  FIG. 3 , a VRM comprises a buck converter  10 , an optional dynamic conversion circuit  20 , and a digital controller  30 , and the VRM is connected to a dynamic load  100  (e.g., a microprocessor). The power converter  10  includes switching power devices S 1  and S 2 , and an output filter inductor L o  and capacitor C o . The dynamic conversion circuit  20  includes an auxiliary power switch S aux  in series with an auxiliary inductor L aux . The dynamic conversion circuit is connected in parallel with the power converter  10 . In an alternative embodiment the dynamic conversion circuit  20  may be connected in parallel with only the output inductor L o  of the power converter  10 . In either case, the same configuration of digital controller  30  may be used. Further, other configurations of a dynamic conversion circuit may also be used. In various embodiments, the digital controller  30  may be used to control the gate signal of the power switches S 1  and/or S 2 , and/or the auxiliary switch S aux  during transients. 
   A block diagram of an embodiment of the digital controller  30  is shown in  FIG. 4 . This embodiment is for a single phase VRM having a single power converter, for example a buck converter, and an optional dynamic conversion circuit. The digital controller includes six major function blocks: 
   1) An analog-to-digital converter (ADC)  40  which senses the output voltage at the load and converts the analog voltage signal into digitized bits. The speed and resolution (e.g., number of bits) of the ADC may be specified according to the required performance and the design considerations. For example, we have found that a 12-bit, 125 MSPS (mega samples per second), ADC, part number AD9433-125, available from Analog Devices, is suitable. 
   2) A digital signal processing (DSP) block  50 , which receives the output from the ADC  40  and processes the sampled output voltage based on an algorithm, an example of which is discussed below with respect to  FIG. 6 ; 
   3) A digital pulse width modulation (PWM) block  60 , which receives output from the DSP block  50  and generates a digitized PWM gate signals for the switches of the power converter, and optionally for an auxiliary circuit if used; 
   4) A gate of power converter block  70 , which generates the synchronous gate signals for the two switches of the power converter; 
   5) An optional gate of dynamic converter block  80 , which generates the gate signal for the switch Saux of the optional dynamic conversion circuit; and 
   6) A gate drive block  90 , which drives the gates of the switches of the power converter and optional dynamic conversion circuit with the synchronized PWM signals. 
   Preferably the digital controller is implemented as an integrated circuit. However, the ADC and the gate drive block may not be necessarily integrated into the digital controller device; that is, either one or both of these blocks may be physically discrete from such an integrated digital controller device. 
   Operation of the digital controller will now be described with reference to  FIGS. 4 and 5 . In normal steady state operation of the power converter or when the load transient is within certain range, the pulse width of the gate signal is determined by the sensed load voltage, the nature of the power converter, and the way the system is compensated. The sampled load voltage is compared with a reference voltage in the DSP block  50  shown in  FIG. 4 . The discrete error signal is compensated by the compensator  52 , which may be a digitally-implemented compensator such as, for example, a proportional integral derivative (PID), PI, Type II, Type III, or proportional/differential (PD) lead compensator. The compensator is selected according to the power converter requirements, based on voltage mode control. The synchronous gate signals of one phase of the converter during steady state are shown in  FIG. 5  at time t o -t 2  and t 3 -∞, Normal Steady State Mode. The frequency of the gate signal is always fixed. The pulse width or duty cycle of the gate signal is also stabilized during steady state operation. At time t i  in  FIG. 5 , a load transient occurs. After a delay of t d , at time t 2 , the converter enters Dynamic Mode. The delay t d  is due to the sampling and processing time of the digital controller. Once a load transient occurs, the duty cycle of the synchronous gate signal is adjusted, determined by how the system is compensated, and relates to factors such as the crossover frequency and the gain of the compensator. However, without the digital controller of the invention, the change in the duty cycle of the gate signal is not sufficient to handle a dramatic load change. Under such circumstances the occurrence of the next gate pulse is limited by the switching frequency of the power converter, and does not occur fast enough to transfer power to the output and minimize the output voltage drop during a load transient. 
   In the DSP block  50  in  FIG. 4 , the sampled load voltage is sent to a digital filter  54  to filter out noise and then is processed at  56  to obtain the derivative of the output voltage. The derivative of the output voltage is sent to the PWM function  57  for further processing. The algorithm for dynamic function block  58  determines when the dynamic mode will be triggered and terminated. The steady state PWM gating and the dynamic gating generated in the digital PWM block  60  are combined to form the gate signal for one phase, which will then be shifted for multiphase switching power devices. This combined signal is thus for steady state operation and dynamic operation when a transient happens. 
   The dynamic gate pattern is generated according to the process given in the flow chart shown in  FIG. 6 , where reference numerals corresponding to those in  FIG. 4  indicate like steps. In the flow chart, the sampled voltage is filtered by a digital filter  54  to remove noise, and then is processed at  56  to obtain the derivative of the sampled voltage. 
   In one embodiment, the algorithm for dynamics  58  uses the derivative of the sampled voltage to calculate, at  58   a , the change in load current ΔI o  according to a linear or non-linear function (e.g., algebraic, trigonometric, exponential) (see equation (1)). The function is based on characteristics such as the output inductance, capacitance, equivalent series resistance (ESR), switching frequency, input/output voltage, and the parameters of the compensator. For example, the voltage vs. current relationship derived from equation (1) when ƒ is a linear function is plotted in  FIG. 10 . This plot shows that once the derivative of the output voltage is obtained, the load step can be predicted.
 
Δ I   o =ƒ( dV   o   /dt )  (1)
 
   In another embodiment, rather than calculate the change in output current, the algorithm for dynamics stores data relating to possible output currents for various output voltages, and looks up the appropriate output current for any given sensed voltage. The advantages of such a look-up table approach are improved speed and the ability to implement functions which might be difficult to model mathematically (e.g., using curve-fitting approximations). 
   Once the derivative of the output voltage exceeds a certain value, indicating that the load current step will exceed a certain threshold value, the algorithm for dynamics  58  ( FIGS. 4 and 6 ) will initiate a pulse for dynamic. Specifically, at steps  58   b  and  58   c  of  FIG. 6 , if the load current increase exceeds a threshold value, and/or the voltage drop exceeds a threshold value, the dynamic gate pulse will be started. However, if both the output voltage drop and the load current step do not exceed their given threshold values, the dynamic gate pulse will not be initiated, in which case the combined gate signal is the gate signal from the path of the steady state PWM for the main switch in the flow chart of  FIG. 6 . 
   The dynamic gate pulse remains high for a certain period of time. Theoretically, when the current through the output inductor L o  reaches the value that the output current should step to (e.g., according to equation (1)), the dynamic gate pulse should be turned off. However, in accordance with the invention it is not necessary to measure the current through the inductor to determine when to turn off the dynamic gate pulse. Rather, it is only necessary to turn off the dynamic gate pulse after a period of time t a  equal to that required for the output current to rise to the predicted value (e.g., according to equation (1)). The time t a  is calculated by the algorithm for dynamics  58  of the DSP block  50  of the digital controller. The time t a  is a function of one or more parameters of the power converter such as, for example, the output inductance, capacitance, equivalent series resistance (ESR) of the output capacitor, switching frequency, input/output voltage, and parameters of the compensator, and a function of the load current step. Equation (2) reveals the relationships to obtain the time t a . 
   
     
       
         
           
             
               
                 
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   As shown in  FIGS. 4 and 6 , the dynamic gate pulse of duration t a , determined at  58   e , is combined at  64  with the steady state PWM to form the gate signal of the power converter switch for both steady state and transient situations. The combination process is similar to an OR logic function. The waveform of the combined gate signals generated at  92  is shown in the flow chart in  FIG. 6  and in  FIG. 5 . Thus, during the dynamic mode, once a load transient is detected, the switch S 1  in  FIG. 3  will be turned on and kept on for a period of time t a , calculated by the digital controller, while the switch S 2  will be kept off during this period of time. Thus, with the digital controller, the gate pulse starts in time, and the pulse width is not limited by the bandwidth of the closed control loop and is wide enough to supply the current from the input to the output through the filter inductor L o  to help maintain the output voltage during the transient. 
   The optional dynamic conversion circuit may also be activated by the digital controller during the load transient. When switch S 1  is turned on and switch S 2  is turned off for a time period of t a , the switch S aux  of the dynamic conversion circuit is turned on and off by the gate signal generated at  94 . It is noted that the inductor L aux  in the dynamic conversion circuit has a substantially smaller value than that of L o , such that the power transferred from the input to the output of the VRM is further accelerated. Moreover, turning S aux  of the dynamic conversion on and off may comprise modulating (e.g., PWM) the gate of S aux  during a load transient. A PWM modulation block for the auxiliary switch is shown in  FIGS. 4 and 6 , and may provide a suitable pattern of gate switching such as, for example, those shown in  FIG. 5  and described below. 
   The first gate pattern of S aux  (option I in  FIG. 5 ) switches S aux  at a fixed switching frequency much higher than that of the main power converter circuit. For example, the switching frequency of S aux  may be 2 to 10 times, 2 to 100 times, or higher, than the switching frequency of the power converter, as may be possible to achieve with available technology. The pulse width of the gate signal is modulated as a constant, predetermined by the digital controller. 
   The second gate pattern of S aux  (option  2  in  FIG. 5 ) also switches S aux  at a fixed frequency much higher than that of the main power converter circuit. The gate signal is pulse width modulated based on voltage mode control. The output voltage of the VRM is sensed and compared with the reference voltage. The error between the sensed output voltage and the reference voltage is compensated by a compensator similar to the compensator of the main power circuit, but with a larger gain. The pulse width of the gate is varied according to how the loop is compensated. For example, the loop may be compensated by a Type III compensator with a high gain. 
   The third gate pattern of S aux  (option  3  in  FIG. 5 ) also switches S aux  at a fixed frequency much higher than that of the main power circuit. The pulse width of the gate signal is predefined to be large initially and then decreases linearly as a function of time. The decreasing rate of the duty cycle is also predefined or calculated by the digital controller. 
   The PWM modulated signal for the auxiliary switch S aux  is combined with the dynamic gate pulse at  68  to form the gate signal for S aux . The combination process is similar to an AND logic function, as shown in  FIGS. 4 and 6 . 
   In a second embodiment, shown in  FIG. 7 , the invention relates to a multiphase interleaved VRM with a dynamic conversion circuit and a digital controller.  FIG. 7  shows a multiphase interleaved VRM with four power converter phases, although more or fewer phases are possible, depending on the amount of output current required. Shown in the embodiment of  FIG. 7  are the main components of the interleaved VRM: the four power converter phases  210 , the dynamic conversion circuit  220 , and the digital controller  230 . In this example, the load  300  is a microprocessor. The switches S a1 , S b1  and the inductor L o1  form the first phase of the multiphase interleaved power converter, each parallel phase being a synchronous buck converter. Other power converters, such as boost, buck-boost, isolated, and non-isolated could also be used. All four phases share the same output capacitor C o . The auxiliary power switch S aux  and inductor L aux  form the optional dynamic converter of the VRM, which is connected in parallel with the four parallel power converters. 
   The digital controller  230  for the interleaved VRM is shown in the block diagram of  FIG. 8 . The digital controller  230  has the same components and functions in the same way as the digital controller  30  in the single phase VRM described above ( FIG. 4 ), except that the gate signal generation portion is now a multiphase gate generator  270 , which generates the gate signals for paralleled buck converters. The multiphase gate generator block  270  includes a phase shift generator  272  for receiving the gate signal from the digital PWM, and four synchronous gating circuits  274  to  277 , one for each of the four phases. Each synchronous gating circuit output is fed to a corresponding gate drive circuit in the gate drive block  290 . The gate drive block  290  drives and sends the phase-shifted PWM gate signals to the power switches of each paralleled branch of the power converter. Optionally, it also drives and sends the gate signal to the auxiliary switch of the dynamic conversion circuit. Operation of the digital controller is substantially the same as for the single phase embodiment (see  FIG. 6 ), in that the steady state PWM gating and the dynamic gating generated in the digital PWM block  260  are combined to form the gate signal for one phase. However, in the multiphase embodiment, this gate signal is then phase shifted by the phase shift generator  272  for multiphase switching power converters. Also, as in the single phase embodiment, the period t a  at which to turn off the dynamic gate pulse may be calculated by the DSP block  250  of the digital controller. The time t a  is a function of buck converter parameters such as output inductance, output capacitance, ESR of the output capacitor, switching frequency, input/output voltage, parameters of the compensator, as well as the load current step. Equation (3) describes the relationship to obtain the time t a . 
   
     
       
         
           
             
               
                 
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   The synchronous gate signals of one phase of the converter during steady state are shown in the period referred to as Normal Steady State Mode (t o -t 22  and t 3 -∞) in  FIG. 9 . The frequency of the gate signal is always fixed. The pulse width or duty cycle of the gate signal is also stabilized during steady state operation. At time t 1  in  FIG. 9 , a step load occurs. After a delay of t d , at time t 2 , the converter enters Dynamic Mode. The delay t d  is due to the sampling and processing time of the digital controller. Once a load transient occurs, the increment of the duty cycle of the synchronous gate signal is determined by how the system is compensated, and relates to factors such as the crossover frequency and the gain of the compensator. 
   During Dynamic Mode, the switches S a1 , S a2 , S a3 , and S a4  are turned on and kept on for a duration of time t a , as calculated by the digital controller, while the switches S b1 , S b2 , S b3 , and S b4  are kept off during this period of time. Thus the gate pulse starts in time and the pulse width will not be limited by the bandwidth of the closed control loop and will be wide enough to supply the current from the input to the output through the filter inductors L o1 , L o2 , L o3 , and L o4  to help maintain the output voltage during the transient. 
   The optional dynamic conversion circuit is also activated by the digital controller during the load transient. When switches S a1 , S a2 , S a3 , and S a4  are turned on and switches S b1 , S b2 , S b3  and S b4  are turned off for a time period of t a , the switch S aux  of the dynamic conversion circuit is turned on and off. In various embodiments the switch S aux  may be modulated according to a desired gate signal drive pattern, three examples of which are shown in  FIG. 9  as options  1  to  3 . Options  1  to  3  are the same as those shown in  FIG. 5  and described above with respect to the single phase VRM embodiment. 
   The invention is further illustrated by way of the following non-limiting example. 
   EXAMPLE 
   A voltage regulator module based on a buck converter and including a digital controller as described above and a dynamic conversion circuit was simulated in PSPICE v. 9.0 and its performance evaluated with respect to a VRM based on a typical buck converter. The input and output voltages of the two VRMs was 12 V dc  and 1.5 V dc  respectively, and the switching frequency of the two circuits was 250 kHz. The rated output current was A and the load transient was from 0.5 A to 25 A, at a slew rate of 1000 A/μs. The results of the simulation are shown in  FIG. 11 , where it can be seen that the voltage drop of the VRM of the invention was less than 10% of that of the typical VRM. According to the simulation, to avoid exceeding a 70 mV output voltage drop at a 100% load current transient (25 A), an output capacitance of only 500 μF was required. In contrast, the conventional voltage mode controlled single phase VRM needed at least 5000 μF output filter capacitance. This is an approximately 6-fold reduction in output capacitance, which represents substantial savings in space on the printed circuit board, and ultimately in cost. 
   All cited documents are incorporated herein by reference in their entirety. 
     FIG. 12  is an example diagram of a power supply system  1200  according to embodiments herein. As shown, power supply system  1200  includes a controller circuit  1206  that generates signals for controlling dynamic power supply circuit  1245  and voltage regulator circuit  1255 . Dynamic power supply circuit  1245  includes element  1272  such as a switch and element  1273  such as an inductor. Voltage regulator circuit  1255  includes element  1282  such as a switch and element  1283  such as an inductor. Controller circuit  1206  includes transient controller  1210  and main controller  1215 . Transient controller  1210  of controller circuit  1206  generates control signals to control dynamic power supply circuit  1245 . Main controller  1215  of controller circuit  1206  generates control signals to control voltage regulator circuit  1255 . The transient controller  1210  (and corresponding dynamic power supply circuit  1245 ) provides faster response to correct deviations in output voltage  1220  than main controller  1215  (and corresponding voltage regulator circuit  1255 ). 
   In one embodiment, the controller circuit  1206  in power supply system  1200  is configured to simultaneously control both a voltage regulator circuit and a dynamic power supply circuit as described herein. For example, the controller circuit  1206  monitors voltage  1220  produced by the voltage regulator circuit  1255  that is used to convey power from voltage source  1230  to load  1218  (e.g., a dynamic load such as a microprocessor system. Depending on a state (e.g., current value, trend, etc.) of the monitored voltage, the controller circuit  1206  can initiate activation of the dynamic power supply circuit in parallel with the voltage regulator circuit to selectively supply additional power to the load. In other words, controller circuit  1206  generates control signals via transient controller  1210  and main controller  1215  so that voltage regulator circuit  1255  produces a constant voltage such as 1.5 Volts DC, both during transients and under steady-state conditions. Controller circuit  1206  monitors the value of voltage  1220  and adjusts the control signals generated by main controller  1215  so that voltage regulator circuit produces a constant voltage applied to load even when the load  1218  happens to moderately increase or decrease at any given instant in time. That is, the main controller  1215  can react to changes in current demand by load  1218  such that the voltage  1220  remains at a relatively constant value. In general, however, voltage regulator circuit  1255  can maintain voltage  1220  at a constant value in the absence of excessive transients in which current requirements suddenly change on the order of several amperes. 
   For more substantial changes in load  1218  (e.g., drastic load changes in which load  1218  requires substantially more current at a given instant of time), the voltage regulator circuit  1255  may be unable to respond fast enough to convey power from the voltage source  1230  to the load  1218 . Under such circumstances, the controller circuit  1206  will detect that the voltage  1220  droops below a threshold value. Note that in one embodiment, the controller circuit  1206  identifies a change in current consumption by load  1218  based on changes in voltage  1220  over time. 
   In response to a more drastic voltage droop as a result of increased power consumption, the controller circuit  1206  enables transient controller  1210  to generate respective control signals to activate dynamic power supply circuit  1245 . For example, the transient controller  1210  portion of controller circuit  1206  can sense an increase in load  1218  and initiate successive, rapid opening and closing of element  1272  (see  FIG. 7  as an example) such that dynamic power supply circuit  1245  conveys power to load  1218  either in addition to or in lieu of voltage regulator circuit  1255  providing power to load  1218 . Accordingly, when load  1218  suddenly requires a substantial increase in power, the controller circuit  1206  deploys transient controller  1210  to prevent drooping of voltage  1220  by supplementing an amount of power (e.g., current) conveyed to load  1218 . In one embodiment, the controller circuit  1206  is configured to enable a switch (e.g., element  1272 ) in the dynamic power supply circuit  1245  to convey power from voltage source  1230  to the load  1218  at a same time that a switch (e.g., element  1282 ) in the voltage regulator circuit  1255  is enabled to supply power to the load. This is shown and discussed above with respect to  FIG. 7 . 
   Referring again to  FIG. 12 , in a similar vein as discussed above, note that the dynamic power supply circuit  1245  can include a switch device that sinks current or power (at a node between element  1272  and element  1273 ) to ground. The voltage regulator circuit  1255  can include a switch device that sinks current (at a node between element  1282  and element  1283 ) to ground. Controller circuit  1206  can initiate activation of either or both of such current sinks when the load substantially decreases at a given instant in time to prevent voltage  1220  from exceeding a threshold value. In an instance when the current draw or power consumption of load  1218  suddenly decreases, without implementing proper measures by controller circuit  1206 , the value of voltage  1220  may suddenly increase because voltage regulator circuit  1255  may be unable to react fast enough to account for the change. However, activation of one or both sink current devices (based on appropriate control signals produced by controller circuit  1206 ) prevents the voltage  1220  from increasing above an acceptable threshold value. As previously discussed, in one embodiment, the voltage regulator circuit  1255  can react fast enough to prevent low frequency spikes on voltage  1220 , whereas dynamic power supply circuit  1245  can react fast enough to prevent higher frequency voltage spikes. 
   Accordingly, the controller circuit  1206  can generate appropriate control signals such that voltage  1220  is maintained within an acceptable voltage range such as between 1.45 and 1.55 volts, even when there are moderate and/or substantial changes in power consumption by load  1218 . 
   Note that in one embodiment, the load  1218  in power supply system  1200  is a microprocessor device and the dynamic power supply circuit  1245  (e.g., power boost circuit) includes a switch (e.g., element  1272 ) that selectively conveys power from voltage source  1230  to the microprocessor during transient conditions when the load increases and requires more current (e.g., an additional number of amperes of current) to keep the voltage  1220  at a substantially constant value. 
   During operation (e.g., enabling current processor power from voltage source  1230  to load  1218 ), the respective elements  1273  and  1283  can be rapidly turned on and off at different duty cycles to control a rate of allowing current or power from voltage source  1230  to pass to the load  1218 . 
   In addition to controlling a duty cycle associated with rapid ON and OFF switching, the inductance associated with the filter elements (e.g., element  1273  and element  1283 ) can be selectively controlled for increased performance. For example, as previously discussed, in one embodiment, element  1273  is an inductor device having a lower inductance than element  1283 , which also is an inductor device. Accordingly, in such an embodiment, the dynamic power supply circuit  1245  is able to more quickly react to supplying extra needed current to load  1218  to prevent substantial drooping of voltage  1220  because it has a lower inductance than element  1283 . 
   Thus, one embodiment herein includes a controller circuit  1206  configured to drive the dynamic power supply circuit  1206 , which has a faster response time than voltage regulator circuit  1255  for more quickly supplying power to the load  1218 . In addition to a faster response time for supplying power to load  1218  because element  1273  has a smaller associated inductance than element  1283 , the controller circuit  1206  can be configured to drive the dynamic power supply circuit  1245  with higher frequency switching signals. In other words, the dynamic power supply circuit  1245  can be configured to operate at a higher switching rate than the voltage regulator circuit  1255  to supply power to the load  1218 . 
   In addition to the above embodiments, the controller circuit  1206  (e.g., digital controller circuit) can be further configured to set the voltage regulator circuit to a given operational mode of multiple operational modes. For example, as previously discussed with respect to  FIG. 7 , the controller circuit  1206  can turn element  1282  ON (as opposed to OFF) such that voltage regulator circuit  1255  conveys power from voltage source  1230  to load  1218 . While the voltage regulator circuit  1255  is set to this operational mode (e.g., element  1282  is ON) during a respective voltage droop detected on voltage  1220 , the controller circuit  1206  initiates activation (e.g., turns on element  1272 ) of the dynamic power supply circuit  1245  to supply power to the load  1218  in addition to the power currently conveyed to load  1218  via voltage regulator circuit  1255 . 
   Thus, the controller circuit  1206  can continue to generate control signals to control voltage regulator circuit  1255  and additionally activate dynamic power supply circuit  1245  when needed to prevent a droop or over-voltage condition. In one embodiment, the controller circuit  1206  only activates the dynamic power supply circuit  1245  for a predicted duration of time, t A , until the voltage regulator circuit  1255  is able to compensate for a change in the load  1218 . After such time, the dynamic power supply circuit  1245  can be disabled until another droop or over-voltage condition on voltage  1220  occurs. 
     FIG. 13  is a block diagram of an example architecture of a respective control system  1310  for implementing controller circuit  1206  according to embodiments herein. Control system  1310  can be a DSP (Digital Signal Processor), FPGA (Field Programmable Gate Array), micro-controller, etc. 
   As shown, control system  1310  of the present example includes an interconnect  1311  that couples a memory system  1115 , a processor  1110 , I/O interface  1314 , and a monitor circuit  1315 . Monitor circuit  1315  can include an analog-to-digital converter for monitoring voltage  1220  applied to load  1218 . 
   As shown, memory system  1115  can be encoded with a control application  1206 - 1  (e.g., control laws or rules) that enables control system  1310  to support generation of appropriate control signals to regulate voltage  1220  as discussed above and as discussed further below. Accordingly, control application  1206 - 1  can be embodied as software code such as data and/or logic instructions (e.g., code stored in the memory or on another computer readable medium such as a disk) that supports processing functionality according to different embodiments described herein. 
   During operation of one embodiment, processor  1110  accesses memory system  1115  via the use of interconnect  1311  in order to launch, run, execute, interpret or otherwise perform the logic instructions of the control application  1206 - 1 . Execution of the control application  1206 - 1  produces processing functionality in control process  1206 - 2 . In other words, the control process  1206 - 2  represents one or more portions of the control application  1206 - 1  performing within or upon the control system  1310 . 
   It should be noted that, in addition to the control process  1206 - 2  that carries out method operations as discussed herein, other embodiments herein include the control application  1206 - 1  itself (i.e., the un-executed or non-performing logic instructions and/or data). The control application  1206 - 1  may be stored on a computer readable medium (e.g., a repository) such as a floppy disk, hard disk or in an optical medium. According to other embodiments, the control application  1206 - 1  can also be stored in a memory type system such as in firmware, read only memory (ROM), or, as in this example, as executable code within the memory system  1115  (e.g., within Random Access Memory or RAM). 
   Functionality supported by controller circuit  1206  will now be discussed via flowchart  1400  in  FIG. 14 . For purposes of the following discussion, the controller circuit  1206  generally performs steps in the flowchart. Note that there will be some overlap with respect to concepts discussed above. Also, note that the steps in the below flowcharts need not always be executed in the order shown. 
     FIG. 14  is a flowchart  1400  illustrating a technique of supplying power according to embodiments herein. 
   In step  1310 , the controller circuit  1206  simultaneously controls both voltage regulator circuit  1255  and dynamic power supply circuit  1245  via generation of corresponding control signals. 
   In step  1320 , the controller circuit  1206  monitors a voltage  1220  produced by the voltage regulator circuit  1255  that is used to supply power to (dynamic) load  1218 . 
   In step  1330 , the controller circuit  1206  initiates activation of the dynamic power supply circuit  1245  in parallel with the voltage regulator circuit  1255  to selectively supply additional power to the dynamic load  1218  depending on a magnitude of the monitored voltage  1220 . 
     FIG. 15  is an example diagram illustrating an embodiment in which the controller circuit  1406  (including transient controller  1410  and main controller  1415 ) and the dynamic power supply circuit  1445 , except inductor  1473 , reside in integrated circuit  1402 . In other words, the controller circuit  1406  and the dynamic power supply circuit  1445 , except inductor  1473 , are packaged in an integrated circuit  1402  separate from a microprocessor chip  1418  and the voltage regulator circuit  1255 . Integrated circuit  1402  and inductor  1473  can be easily added to an existing power supply circuit including voltage regulator circuit  1255  (e.g., buck converter) that powers a load such as a microprocessor  1418 . 
     FIG. 16  is an example diagram illustrating an embodiment in which the controller circuit  1506  (including transient controller  1510  and main controller  1515 ), the dynamic power supply circuit  1545 , except inductor  1573 , all reside in a common integrated circuit  1502 . Together with the load such as microprocessor  1518  and inductor  1573 , the integrated circuit  1502  provides the same functionality as discussed above and. Such an embodiment can save printed circuit board real estate and thus reduce overall circuit size. 
   Note that techniques herein are well suited for use in power supply applications. However, it should be noted that embodiments herein are not limited to use in such applications and that the techniques discussed herein are well suited for other applications as well. 
   While this invention has been particularly shown and described with references to preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present application as defined by the appended claims. Such variations are intended to be covered by the scope of this present application. As such, the foregoing description of embodiments of the present application is not intended to be limiting. Rather, any limitations to the invention are presented in the following claims.