Patent Publication Number: US-2021191618-A1

Title: Apparatus and Method to Provide Cache Move with Non-Volatile Mass Memory System

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This is a continuation of and claims priority to commonly assigned, co-pending U.S. patent application Ser. No. 15/235,425 filed Aug. 12, 2016, which is a U.S. patent application Ser. No. 13/358,806, filed Jan. 26, 2012, now U.S. Pat. No. 9,417,998, which are incorporated herein by reference in their entirety. 
    
    
     TECHNICAL FIELD 
     The exemplary and non-limiting embodiments of this invention relate generally to memory storage systems, methods, devices and computer programs and, more specifically, relate to mass memory devices, such as those containing non-volatile flash memory. 
     BACKGROUND 
     This section is intended to provide a background or context to the invention that is recited in the claims. The description herein may include concepts that could be pursued, but are not necessarily ones that have been previously conceived, implemented or described. Therefore, unless otherwise indicated herein, what is described in this section is not prior art to the description and claims in this application and is not admitted to be prior art by inclusion in this section. 
     The following abbreviations that may be found in the specification and/or the drawing figures are defined as follows:
         ASIC application specific integrated circuit   CPU central processing unit   DMA direct memory access   eMMC embedded multimedia card   exFAT extended file allocation table   HW hardware   JEDEC Joint Electron Device Engineering Council   LBA logical block address   MMC MultiMediaCard   MRAM magnetic random access memory   RAM random access memory   SCSI small computer system interface   SD secure digital   SW software   UFS universal flash storage       

     Various types of flash-based mass storage memories currently exist. A basic premise of mass storage memory is to hide the flash technology complexity from the host system. A technology such as eMMC is one example. A managed NAND type of memory can be, for example, an eMMC, SSD, UFS or a microSD. 
       FIG. 1A  reproduces  FIG. 2  from JEDEC Standard, Embedded MultiMediaCard (eMMC) Product Standard, High Capacity, JESD84-A42, June 2007, JEDEC Solid State Technology Association, and shows a functional block diagram of an eMMC. The JEDEC eMMC includes, in addition to the flash memory itself, an intelligent on-board controller that manages the MMC communication protocol. The controller also handles block-management functions such as logical block allocation and wear leveling. The interface includes a clock (CLK) input. Also included is a command (CMD), which is a bidirectional command channel used for device initialization and command transfers. Commands are sent from a bus master to the device, and responses are sent from the device to the host. Also included is a bidirectional data bus (DAT[7:0]). The DAT signals operate in push-pull mode. By default, after power-up or RESET, only DAT0 is used for data transfer. The memory controller can configure a wider data bus for data transfer using either DAT[3:0] (4-bit mode) or DAT[7:0] (8-bit mode). 
     One non-limiting example of a flash memory controller construction is described in “A NAND Flash Memory Controller for SD/MMC Flash Memory Card”, Chuan-Sheng Lin and Lan-Rong Dung, IEEE Transactions of Magnetics, Vol. 43, No. 2, February 2007, pp. 933-935 (hereafter referred to as Lin et al.)  FIG. 1B  reproduces  FIG. 1  of Lin et al., and shows an overall block diagram of the NAND flash controller architecture for a SD/MMC card. The particular controller illustrated happens to use a w-bit parallel Bose-Chaudhuri-Hocquengham (BCH) error-correction code (ECC) designed to correct random bit errors of the flash memory, in conjunction with a code-banking mechanism. 
     SUMMARY 
     In a first aspect thereof the exemplary embodiments of this invention provide a method that comprises receiving a command originating from an initiator at a controller associated with a non-volatile mass memory coupled with a host device, the command being a command to write data that is currently resident in a memory of the host device to the non-volatile mass memory; moving the data that is currently resident in the memory of the host device from an original location to a portion of the memory allocated for use at least by the non-volatile mass memory; and acknowledging to the initiator that the command to write the data to the non-volatile mass memory has been executed. 
     In another aspect thereof the exemplary embodiments of this invention provide an apparatus that comprises a controller associated with a non-volatile memory module connected with a host device and an interface to the non-volatile mass memory module. The controller is configurable to process a command originating with an initiator, where the command is a command to write data that is currently resident in a memory of the host device to the non-volatile mass memory module. The controller is further configurable to move the data that is currently resident in the memory of the host device from an original location to a portion of the memory allocated for use at least by the non-volatile mass memory module; and to acknowledge to the initiator that the command to write the data to the non-volatile mass memory has been executed. 
     In another aspect thereof the exemplary embodiments of this invention provide a method that comprises providing a data processing system comprising at least one data processor and at least one memory comprised of dynamic random access memory, and autonomously performing an elementary memory operation in the memory. 
     In yet another aspect thereof the exemplary embodiments of this invention provide a memory module that comprises a controller; a non-volatile mass memory that is readable and writable by the controller; and an interface for connecting the memory module to a host device. The controller is configurable to receive a command originating from an initiator, where the command being a command to write data that is currently resident in a memory of the host device to the non-volatile mass memory module. The controller is further configurable to initiate the move of the data that is currently resident in the memory of the host device from an original location to a portion of the memory allocated for use at least by the non-volatile mass memory module; and to acknowledge to the initiator that the command to write the data to the non-volatile mass memory has been executed. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       In the attached Drawing Figures: 
         FIG. 1A  reproduces  FIG. 2  from JEDEC Standard, Embedded MultiMediaCard (eMMC) Product Standard, High Capacity, JESD84-A42, June 2007, JEDEC Solid State Technology Association, and shows a functional block diagram of an eMMC. 
         FIG. 1B  reproduces  FIG. 1  of Lin et al., and shows an example of an overall block diagram of a NAND flash controller architecture for a SD/MMC card. 
         FIG. 2  is a simplified block diagram of a host device connected with a mass storage memory device, and is helpful in describing the exemplary embodiments of this invention. 
         FIG. 3  is a signal/message flow diagram that describes an embodiment of the invention described in commonly-assigned U.S. patent application Ser. No. 12/455,763, where the mass storage memory device of  FIG. 2  can allocate, use and de-allocate RAM of the host device. 
         FIG. 4  is a signal/message flow diagram that describes another embodiment of the invention described in commonly-assigned U.S. patent application Ser. No. 12/455,763, where the mass storage memory device of  FIG. 2  has a built-in file system. 
         FIGS. 5A, 5B and 5C , collectively referred to as  FIG. 5 , show an embodiment of the host device and mass storage memory device of  FIG. 2  in accordance with embodiments of this invention. 
         FIG. 6  shows a block diagram of one exemplary embodiment of the host device when embodied as a wireless communication device. 
         FIG. 7  is a logic flow diagram that illustrates the operation of a method, and a result of execution of computer program instructions embodied on a computer readable memory, in accordance with the exemplary embodiments of this invention. 
         FIG. 8  is a logic flow diagram that illustrates the operation of a method, and a result of execution of computer program instructions embodied on a computer readable memory, further in accordance with the exemplary embodiments of this invention. 
     
    
    
     DETAILED DESCRIPTION 
     Of interest to the ensuing description of the exemplary embodiments of this invention is commonly-assigned U.S. patent application Ser. No. 12/455,763, filed Jun. 4, 2009, “Apparatus and Method to Share Host System RAM with Mass Storage Memory RAM”, Olli Luukkainen, Kimmo Mylly and Jani Hyvonen (US 2010/0312947 A1), incorporated by reference herein. Before describing in detail the exemplary embodiments of this invention it will be useful to review at least a portion of the description of this commonly-assigned U.S. patent application Ser. No. 12/455,763. 
     As is stated, at present most mass storage memories provide LBA-based access, e.g., eMMC and different types of external memory cards such as SD. However, it may also be the case that the entire file system (FS) SW is embedded in the mass storage memory device. 
     When a mass storage memory is used in a high volume consumer device, such as a mobile wireless communication device, one important consideration is cost, and one factor affecting the cost is the amount of RAM in the mass storage memory device itself. 
     Another important consideration is performance. The overall performance depends on many factors. For example, for lengthy (time consuming) operations (in particular if the mass storage memory device contains an entire file system SW) there would be an advantage to include a substantial amount of RAM in the mass storage memory device. However, this can have a negative impact on the cost. 
     It may be the case that system context (metadata) would be stored in the flash memory of the mass storage memory device. However, this approach has several associated disadvantages. For example, repeatedly writing the system context (metadata) to the mass storage memory device raises wearing issues that can impact the usable life of the mass storage memory device. Also, writing data to the flash memory can be a relatively slow process. 
     Another important consideration is the power efficiency. To provide good power efficiency the mass storage memories are preferably shutdown (powered-off) when not needed (meaning also that the internal RAM of the device is preferably shutdown as well). However, and assuming that the RAM is volatile in nature, then whatever data is stored in the RAM is lost when the power is removed from the RAM. To then perform re-initialization after power-up all needed information (e.g., logical-to-physical mapping information and/or file system structures) need to be restored. A full re-initialization of a LBA mass storage memory may require a substantial (and user-noticeable) amount of time (e.g., up to one second with an SD card), and entire file system initialization (if the file system is resident in the mass storage memory) may take even longer. Therefore, it is desirable to retain internal device context over the power-off/power-on cycle. 
       FIG. 2  shows is a simplified block diagram of a host system or device  10  connected with a mass storage memory  20  via a mass storage memory bus (MSMB)  18 . The MSMB  18  may be compatible with any suitable mass memory interface standard such as MMC or UFS, as two non-limiting examples. The MSMB  18  may include signal lines such as those shown in  FIG. 1A  for an eMMC embodiment. The host device  10  includes at least one controller, such as a CPU  12  that operates in accordance with stored program instructions. The program instructions may be stored in a RAM  14  or in another memory or memories. The CPU  12  is connected with the RAM  14  and a MSMB interface (I/F)  16  via at least one internal bus  17 . The MSMB interface  16  may include a memory controller (MC), or may be coupled with a MC unit associated with the CPU  12 . The host device  10  may be a computer, a cellular phone, a digital camera, a gaming device or a PDA, as several non-limiting examples. Note that the RAM  14  may be any read/write memory or memory device, such as semiconductor memory or a disk-based memory. 
     The mass storage memory  20  includes a microcontroller or, more simply, a controller  22  that is connected via at least one internal bus  27  with a volatile RAM  24 , a non-volatile mass memory  26  (e.g., a multi-gigabyte flash memory mass storage) and a MSMB interface (I/F)  28 . The controller  22  operates in accordance with stored program instructions. The program instructions may be stored in the RAM  24  or in a ROM or in the mass memory  26 . The mass storage memory  20  may be embodied as an MMC, eMMC or a SD device, as non-limiting examples, and may be external to (plugged into) the host device  10  or installed within the host device  10 . Note that the mass memory  26  may, in some embodiments, store a file system (FS)  26 A. In this case then the RAM  24  may store FS-related metadata  24 A, such as one or more data structures comprised of bit maps, file allocation table data and/or other FS-associated information. 
     The embodiments of the invention described in commonly-assigned U.S. patent application Ser. No. 12/455,763 provide a technique to share the RAM  14  of the host device  10  with the mass storage memory device  20 . It can be assumed that the host device  10  (e.g., a mobile computer, a cellular phone, a digital camera, a gaming device, a PDA, etc.) has the capability to allocate and de-allocate the RAM  14 . The allocation of the RAM  14  may be performed dynamically or it may be performed statically. The allocation of a portion of the RAM may be performed in response to a request received at the host device  10 , or at the initiative of the host device  10 . 
     In the embodiments of the invention described in commonly-assigned U.S. patent application Ser. No. 12/455,763 the RAM  14  allocation is provided for the mass storage memory  20  (connected via the MSMB  18  to the host CPU  12 ), if the mass storage memory  20  has a need to extend its own RAM  24  space and/or if the mass storage memory  20  has a need for non-volatile RAM (the contents of which are not lost when the mass storage memory  20  is powered-off). The mass storage memory  20  can also read and/or write (R/W) allocated RAM  14  in the host device  10 . The allocation/de-allocation and R/W access methods can be implemented by extensions to a command set used to communicate with the mass storage memory  20  via an applicable mass storage memory protocol. 
     In accordance with certain embodiments of the invention described in commonly-assigned U.S. patent application Ser. No. 12/455,763 the mass storage memory device  20  is provided with a mechanism to interrupt/send a message to host device  10  to initiate an allocation of space in the RAM  14 . The interrupt/message is sent over the MSMB  18 , and may be considered as an extension to current command sets. Referring to  FIG. 3 , an allocate memory command is sent during operation  3 - 1 . If the allocation request succeeds (indicated during operation  3 - 2 ) the controller  22  is enabled to extend its own RAM  24  with the RAM  14  of the host device  10 . The mass storage memory device  20  may store, for example, large tables into the RAM  14  using a RAM WRITE command or it may fetch data from the host device RAM  14  using a RAM READ command. The read or write operation is shown as interleaved operations  3 - 3 ,  3 - 4 ,  3 - 5 ,  3 - 6 , . . . ,  3 -(N−1),  3 -N. When the mass storage memory device  20  completes the operation with the RAM  14  it may free the host device RAM  14  using another command that requests that the host  10  RAM memory be de-allocated (operation  3 -(N+1)). 
       FIG. 4  illustrates a further exemplary embodiment described in commonly-assigned U.S. patent application Ser. No. 12/455,763 that utilizes the host system RAM  14  for the mass storage memory  26  having a built-in file system, such as the FS  26 A shown in  FIG. 2 . First the host system  10  sends a SHUTDOWN command to the mass storage memory device  20  (operation  4 - 1 ). Next the mass storage memory device  20  allocates RAM  14  from the host  10  and then loads (stores using a RAM WRITE command) all vital ‘static’ file system-related data (meta-data  24 A) into host RAM  14  (operation  4 - 2 ). ‘Static’ data in this context may be, for example, various bitmaps, such as an allocation bitmap in the exFAT or ext3 file systems. This data may be processed (e.g., at least one of sorted, arranged and filtered) by the CPU  12  (controller) of the host device, and may include data from a large number of sectors in the mass storage memory  26 . Mass memory storage device  20  may then send a shutdown OK indication (operation  4 - 3 ). The host  10  can remove power from the mass memory storage device  20 , and the device  20  may be physically removed from the MSMB  18 . Re-initialization (operations  4 - 4 ,  4 - 5 ,  4 - 6 ) of the mass storage memory device  20  is performed when host device  10  needs to get/put certain data from or into the mass storage memory device  20 . Re-initialization of the mass storage memory  26  (and the file system  26 A) may be sped up by using the sorted/arranged/filtered read data from the RAM  14 . When the re-initialization operation is completed the mass storage memory device  20  may de-allocate the used RAM  14  in the host device  10 , or the RAM  14  may not be de-allocated thereby reserving the RAM space for future use by the mass storage memory device  20 . 
     The allocation of host RAM  14  may occur differently in some embodiments. For example, the host device  10  may allocate RAM  14  dynamically and pass a ‘pointer’ to the allocated RAM to the mass storage memory device  20 . It is then up to the controller  22  of the mass storage memory device  20  how to utilize the allocated host RAM  14 . Note that in this embodiment an explicit allocation request from the mass storage memory device  20  may not be sent to the host device  10 . Instead, the host device  10  may on its own initiative allocate a portion of the RAM  14 , such as when it first detects the presence of the mass memory storage device  20 . Of course, subsequent signaling between the mass storage memory device  20  and the host device  10  may be used to change the size of the allocated RAM  14  if the initial allocation is not sufficient for the needs of the controller  22 . As another example of RAM  14  allocation, a portion of the RAM  14  may be allocated by the host  10  in a static manner and the mass storage memory device  20  then simply uses the same portion of the RAM  14  each time it needs to extend the RAM  24 . In this case the mass storage memory device  20  may already have knowledge of the location/size of the allocated RAM  14 , and a pointer is not needed to be sent from the host device  10 . 
     Note that while it may typically be the case that the mass storage memory device  20  will receive an allocation of host memory to store contents of the volatile RAM  24 , in general the allocation may be for storing data for any read/write memory contained within the mass storage memory device  20 . 
     Having thus provided an overview of various non-limiting and exemplary embodiments of the invention described in the commonly-assigned U.S. patent application Ser. No. 12/455,763, a description is now made of the exemplary embodiments of this invention. 
     In a managed NAND memory (e.g., eMMC, SSD, UFS, microSD) the memory controller (such as the controller  22  shown in  FIG. 2 ) takes care of the flash management functions such as bad block management and wear leveling. In a typical low cost implementation there is only a small input/output (IO) buffer SRAM in the managedNAND. Embedded in the controller in higher end managedNANDs such as SSDs there may be tens to hundreds of megabits of discrete DRAM as cache. In the future some new memory technologies such as MRAM could serve as very fast non-volatile cache also. 
     In a modern multi-tasking mobile device environment there may be many different types of accesses from different initiators that are queued to the mass storage at the same time. In the eMMC case the queued accesses would be served one-by-one since the eMMC device can only handle a single thread at a time. In the UFS case it is possible to send the accesses/commands to a UFS device queue. However, even though the commands can be queued this does not ensure that there necessarily are sufficient resources at the UFS device (especially in a cost optimized model) to immediately accommodate all of the data related to the queued accesses. 
     The above described commonly-assigned U.S. patent application Ser. No. 12/455,763 provides a model in which the mass storage memory  20  is provided with read/write access to the system DRAM  14 . This concept is extended by the exemplary embodiments of this invention to enable the mass storage memory  20  to move data within the system DRAM, either logically (by the use of pointers) or physically. The actual move could occur within the DRAM  14  or the data could travel back and forth over the system DRAM bus  17  (e.g., between the system DRAM  14  and a Mass Memory Host Controller  13  DMA buffer). The Mass Memory Host Controller  13 , shown in  FIG. 5A  and described in detail below, can be considered to function in this regard as a DMA master and thus can include its own associated DMA data buffers for this purpose. 
     The foregoing features can be realized through the use of several embodiments. 
     In a first embodiment a separate physical address space in the system DRAM  14  is reserved for the mass storage memory  20 , or a logical space is reserved if the system DRAM  14  operates in a logical address space. The mass storage memory (such as the UFS mass storage memory  20 ) can utilize this address space freely, and is responsible for the management functions of this address space such as allocation/deallocation functions and other functions. 
     Reference can be made to  FIG. 5  where those components described in reference to  FIG. 2  are numbered accordingly. In  FIGS. 5A, 5B and 5C  a portion  14 G of the system DRAM  14  is allocated for use by the mass memory module  20  (described here in a non-limiting embodiment as a UFS memory module). The host device  10  includes an application processor that can be embodied as the CPU  12 . Included with or coupled to the application processor  12  may be a DRAM controller  11 . Also present is the above-mentioned mass memory module (e.g., UFS) host controller  13 . The host controller  13  can be embodied as the CPU  12  or it can be embodied as a separate device.  FIG. 5B  shows that the system DRAM  14  stores an operating system (OS)  14 A and application programs (applications)  14 B. At least some of the applications  14 B generate data  14 B′. The system DRAM  14  also typically stores a file system cache  14 C associated with a file system (part of the OS  14 A). In the embodiment of  FIG. 5B  a portion of the system DRAM  14  is allocated as a transfer buffer  14 D to which the application data  14 B′ can be moved to become transfer buffer data  14 E. Another portion of the system DRAM  14  is allocated to store an access list  14 F. Also included is the DRAM portion  14 G that is allocated for the UFS memory module  20 , and into which the transfer buffer data  14 E can be moved to become data  14 E′. The operation of these components shown in  FIGS. 5A, 5B and 5C  is now described in further detail. 
     Assume that a source of data such as an application  14 B, or a file system cache, or a file cache entity (as non-limiting examples) has data  14 B′ to be stored into the mass memory module  20 . The data  14 B′ is moved to the transfer buffer  14 D as the transfer data  14 E by a file system/driver for subsequent delivery to the mass memory module  20 . Optionally, as shown in  FIG. 5C  and discussed in further detail below, the data  14 B′ could be moved directly from its original location thereby bypassing the transfer buffer  14 D. The access list  14 F is created in the system DRAM  14  for the application  14 B such as by an OS utility and points to the location of the data  14 E. Note in this regard that an “application” (if understood here in a conventional sense as a third party application) cannot itself create any access lists. Instead the application creates read/write accesses and functions as an initiator. The access lists are created typically by some OS services/memory subsystem (e.g. some driver layer or some OS utility) based on accesses coming through the file system layer. In effect the access lists are constructed or built for the application. An initiator may be, as anon-limiting example, an application, a file system, a driver or an OS utility. 
     In accordance with an aspect of this invention the data  14 E can be moved to the portion  14 G allocated for the mass memory (UFS) to become the data  14 E′ as described below. 
     An access may take place by the host device  10  as follows (it is assumed that the host device  10  has already correctly initiated the mass storage memory  20 ). 
     (1) An initiator, such as an application program  14 B resident in the system DRAM  14  that is being executed by the CPU  12 , has built for itself (e.g., by an OS utility) a table of accesses (access list  14 F) to the UFS memory module  20  in the system DRAM  14 . Assume for this example that the execution of these accesses would exhaust the resources of the UFS memory module  20  for some period of time. 
     (2) The initiator, such as the application program  14 B or the OS utility, informs the UFS host controller  13  of the presence of the table of accesses (access list  14 F) and the host controller  13  begins the delivery of the commands and any related data to the UFS memory module  20 . 
     (3) The same or another initiator, such as the same or a different application program  14 B, has built for itself another table of write accesses (another access list  14 F) to the UFS memory module  20  in the system DRAM  14  and the UFS host controller  13  is informed of the presence of the table of accesses. 
     (4) The UFS host controller  13  transfers this set of (write) commands to the UFS memory module  20 . Assume that the UFS memory module  20  determines that it is not currently able to handle the data related to the write commands locally in the UFS memory module  20 . Note in this regard that there could be, for example, a head of queue indication by the initiator related to the commands to emphasize the urgency for the execution of the write command(s), and the UFS memory module  20  determines that it is not currently able to meet the indicated level of urgency. 
     (5) Instead of receiving the data related to the write commands the UFS memory module  20  moves the data e.g. from the transfer buffer  14 D (or  14 B/ 14 C) to the reserved separate physical address space (allocated portion  14 G) of the system DRAM  14 . The move operation and the allocated portion  14 G of the system DRAM  14  is controlled by the UFS memory module  20  via the UFS host controller  13 . The UFS host controller  13  controls the system DRAM  14 , or the system DRAM controller  11 , to execute the move of the data  14 E from e.g. the transfer buffer  14 D to the allocated portion  14 G as the data  14 E′. The UFS host controller  13  can be assumed to perform this operation e.g. by means of operating as DMA master (of either a dedicated UFS DMA or system DMA) directly and can bypass the host CPU  12 . 
     (6) After the physical move of the data  14 E to the allocated portion  14 G occurs the UFS memory module  20  can respond to the original (write) command as though it had actually moved the data to the non-volatile memory (NVM), i.e., to the mass memory  26 . As a result the second initiator can consider that the write command(s) to the mass memory  20  have been executed and can continue its processing operations, even though the write data is currently resident as the data  14 E′ in the allocated portion  14 G of the system DRAM  14 . 
     (7) At some future time the UFS memory module  20  has sufficient resources to process the write command from the second initiator. At this time it independently fetches the data from the system DRAM  14  (from the allocated portion  14 G of the system DRAM  14 ) and stores it in the NVM mass memory  26 . From the point of view of the initiator or the file system layer of the OS  14 A this operation is transparent, and appears as though there is physical DRAM/SRAM cache within the UFS memory module  20 . That is, the external allocated portion  14 G of the system DRAM  14  can function in a manner analogous to a virtual DRAM/SRAM cache of the UFS memory module  20 . 
     Note that the UFS memory module  20  need not process received access commands sequentially. For example, before processing the write command from the second initiator if another write command having a higher indicated priority arrives from a third initiator, where the write data has also been stored in the allocated portion  14 G, the UFS memory module  20  could process the write command from the third initiator and then process the write command from the second initiator. 
     In another embodiment there need be no specific separate memory addresses reserved in the system DRAM  14  for the mass memory module  20 . Instead the mass memory module  20  can have access to any (or almost any) location in the system DRAM  14 . In this case instead of moving data physically in the system DRAM  14  the mass memory module  20  can control a list of memory pointers created by the host CPU  12 . By modifying the lists of pointers (one list of pointers for host and another for the mass memory module  20 ) the mass memory module  20  can virtually “move” data from host CPU-controlled logical memory space to space controlled by the mass memory module  20 . Note that in this case the transfer buffer  14 D will/may still be present, however there is no need for the physical portion  14 G allocated for the mass memory module  20 . 
     Alternatively, the mass memory module  20  can use header information created by the host CPU  12 . The header information can use separate bits for host valid/invalid, reserved and mass memory valid/invalid allocations and can be stored in the system DRAM  14 . In this case by modifying the header information (e.g., allocated/free) the mass memory module  20  could “move” data from host CPU  12  controlled addresses to addresses controlled by the mass memory module  20 . 
     Either or both of these operations can be mediated by the host controller  13 . 
     There can be a read command from an application to an address of which the data is still located in an area of the system DRAM  14  reserved for the non-volatile module  14 G, i.e. the data stored earlier was not yet moved by the non-volatile memory module  20  to the non-volatile memory  26 . In such a case the memory controller  22  would detect this read command and (instead of truly moving and storing the data into the non-volatile memory  26  before serving the read command) would copy (not move) the data from the memory area  14 G to the location reserved for it in the file cache/file system cache  14 C/transfer buffer  14 D or application area  14 B. The target address in the reserved location could be included in the access list  14 F so that it is at least known by the host controller  13 . 
     In the alternative embodiments related to modification of lists of pointers and headers correspondingly the above mentioned read case would be realized as copying of the data (related to the read request) to new target location and preparing the pointers/headers by the memory module/host controller so that the copied data will be immediately accessible and under control of the host system  10 . 
     In all of these read-related embodiments it should be appreciated that the read data is copied and the data  14 E′ still exists and will be written to the non-volatile memory  26  of the memory module  20  as soon as the memory controller  22  has the resources to perform the write operation. 
       FIG. 5C  shows an embodiment of this invention, as discussed above, where the access list  14 F references the data  14 B′, and the referenced data is then directly moved to the allocated portion (as data  14 E′) thereby bypassing the transfer buffer  14 D (i.e., the data  14 B′ after being moved directly becomes the data  14 E′). 
     It is also within the scope of the exemplary embodiments for the data to originate from a source other than the host CPU  12  (e.g., other than from the application processor). For example, the data could originate from an initiator that is embodied as a peripheral device  60  that is connected to the host device  10  either by a wired connection or a wireless connection. In this case instead of moving the data directly from the peripheral device  60  to the mass memory module  20  the mass memory module  20  causes the data to be stored in the system DRAM  14 , such as in the allocated portion  14 G. The data that originates at the peripheral device  60  is thus temporarily (and transparently to the peripheral device  60 ) cached in the system DRAM  14 . 
     Further in accordance with the exemplary embodiments of this invention the operation of the DRAM  14  is enhanced by providing additional functionality to locally perform operations in the DRAM  14 . 
     By way of introduction, one of the processing capacity bottlenecks of a wireless terminal (e.g., a smartphone) is the execution memory, especially the memory bus. While the execution memory, also known as work memory, is a separate component (e.g., external DRAM), it is connected to a host ASIC by a bus that has a limited transfer capacity (bandwidth). 
     The means of improving the memory bandwidth are limited. In most cases the cost of several memory buses and memory devices respectively is too high. Also the bus itself takes a major portion of the pin/pad budget of the host ASIC, meaning that at a given pad pitch, the package containing the host ASIC silicon, would became unnecessarily large with multiple buses, creating problems for miniaturization efforts. 
     A common problem is that the memory bandwidth, or transaction capacity, is not sufficient for many desired use cases. The host ASIC can contain several memory masters (e.g., processors, accelerators, and DMA engines) and one DRAM controller  11  that provides the external memory bus. At the other end of this bus is the memory device (DRAM component). Memory masters issue read and write requests to the memory. The DRAM is built of several banks (4 to 8 typically) that could operate in parallel. Thus, while parallelism exists at both ends of the memory bus, the memory bus itself is a single-threaded arrangement. 
     The exemplary aspects of this invention include providing a means to fully exploit the memory device by enabling internal operations to be performed locally. This improves the overall memory subsystem performance, enhances CPU capacity by off-loading some operations from the CPU, and decreases power consumption. The exemplary aspects of this invention provide for some elementary operations to be carried out by the memory device through the use of an enhanced command set. 
     It should be noted that while these aspects of the exemplary embodiments of this invention are described in the context of enhancing the operation of the system DRAM  14  these aspects of the invention could be applied as well to enhancing the operation of the mass storage memory device  20 . For example, the resident memory controller  22  of the memory module  20  could be modified so as to provide local autonomous operations within the mass memory  26 . 
     Further in accordance with the exemplary embodiments of this invention some basic, elemental functions such as memory fill and memory move are handled internally to the system DRAM  14 . These operations can be handled, for example, by system DRAM memory controller and/or by a control module or function  15  embedded in the system DRAM  14  (shown in  FIG. 5A ). 
     In this embodiment the system DRAM  14 , with or without assistance of the system DRAM memory controller  11 , can perform, for example, memory fill and move function(s) independently and autonomously without active intervention/control by the CPU  12 . This reduces the CPU  12  and system DRAM bus  17  load due at least to the mass memory module/mass memory host controller  13  controlling the physical data move from the buffer  14 B/ 14 D to the allocated portion  14 G. 
     It can be shown that many memory transactions are simple fills of memory address space with data (e.g., zeroes) or moving data chunks from one memory location into another memory location, where the locations can be inside the same physical memory device or inside two different memory devices. This conventionally requires activity at the CPU level, which means that system processing efficiency and power consumption are less than optimal. 
     In accordance with these further aspects of the invention at least some elementary in-memory operations are removed from the responsibility of the CPU  12  and transferred to the system DRAM  14 , such as to the controller  15  that can be embedded with the system DRAM  14 . 
     In this exemplary embodiment the controller  15  functionality includes “smart memory” features. Alternatively these smart memory features could be included in the host controller  13  shown in  FIG. 5A . Alternatively, and as was mentioned above, these smart memory features could also be included in the system DRAM memory controller  11  functionality for the system DRAM  14  of the host device  10   
     In these embodiments system DRAM controller  11  or the system DRAM module (control  15 ) may analyse commands issued for it and initiate a “smart memory” operation such as a memory fill or a memory move operation. 
     The additional functionality added to, for example, the controller  15  may include at least a data fill feature and a data move feature. The additional functionality optionally includes security functions for the system DRAM  14 , pack/unpack functions between the system DRAM  14  and the mass memory  26 , data transaction functions between the DRAM  14  and the mass memory  26  and, for example, mass memory related error detection and correction and wear levelling functions. 
     As an example of the use of the smart memory features, a memory block reset is typically performed by writing zeroes into the memory. In accordance with this invention a ‘data fill’ function supports at least a Fill operation using any specified bit pattern (e.g., Fill: Data), where Data could be any specified bit pattern such as ‘0000’, ‘1111’, ‘0101’, etc. 
     A Data Move operation can be a read/write (copy) sequence followed by a Fill operation to the region of system DRAM  14  from which the data was moved (read). The Fill operation could set the memory locations to some predetermined value (e.g., zero), or to a value specified by the Data Move operation command in a manner analogous to the Fill operation discussed above. The Fill operation can be optional, so that the Data Move operation functions as a Data Copy operation (i.e., the data is replicated to another location while the original data is unchanged). 
     A non-limiting example of the implementation of the smart memory functionality at the command level is as follows. 
     Low Power Double Data Rate (LPDDR1 (LP1)) as specified by JEDEC (e.g., see JEDEC Standard, Low Power Double Data Rate (LPDDR) SDRAM Standard, JESD209B, February 2010) does not provide a straightforward method of adding these types of smart features. An exemplary implementation may be to use a sequence of multiple conventional Mode Register Set (MRS) commands (MRS with bank address BA0=BA1=‘1’ is available) using address pins A 0 -Ax to deliver the following information to the memory device:
         1) Command type (move, fill);   2) Fill data (all 0, all 1, 01 sequence, . . . ), optional;   3) Target address (fill, move) and source address (move), address depends on implementation;   4) Operation size, granularity depends on implementation.       

     The number of needed MRS commands in the sequence is dependent on addressing, data granularity and operation size, which are implementation dependant factors. In LPDDR2 and LPDDR3 Mode Register Write commands could be used in a similar fashion. It should be understood that conventional LPDDRx solutions allow MRS and MRW operation only from DRAM idle state, but other solutions are technically possible. One such implementation may be to require that the data which is the source or the target of the move or fill operation is located in open DRAM pages. 
     It should also be understood that with future DRAM interfaces new dedicated commands are possible to be used for these operations—and these operations could be made much more efficient. Fundamentally from a system viewpoint some or all of the following operations may be delivered to the memory:
         1) Deliver command (fill0, fill1, . . . , fill_pattern, move);   2) Deliver target address (bank, row, column, byte);   3) Deliver source address (bank, row, column, byte);   4) Deliver operation size.       

     Full command and address delivery may occur in a single or a multiple command sequence—a certain command code may, for example, indicate multicycle delivery via cmd/address/data bus as suits the implementation. The particular implementation dictates the requirements for the data and address granularity, requirements for the memory state prior to and after the smart memory feature operations, whether the memory internally uses some intermediate buffers to move or fill the data or whether open rows (DRAM sense amps) are reserved during the entire operation, any timing requirements, etc. 
     The command could be issued by the, for example, the CPU  12  (e.g., by an OS or file system utility) or by the mass memory host controller  13  and then autonomously executed by the controller  15  associated with the system DRAM  14  or by the DRAM memory controller  11 . 
     There are a number of advantages and technical effects that can be realized by the use of the exemplary embodiments of this invention as described above. For example, a faster response to the initiator (Host CPU  12 , a process, an initiator, an application) can be provided that an access has been served (actually taken into the ManagedNAND side for further processing). This enhances the user experience. Further, no changes need be made to the upper layer software (e.g., file system and/or applications) as moving data occurs at a low layer of hardware/software. Further, the allocated portion  14 G of the system DRAM  14  for the ManagedNAND functionality need not be excessively large. For example, for many uses of interest some hundreds of kilobytes could be sufficient as in many cases it would be most advantageous to temporarily cache just small random accesses, and to store directly to the non-volatile mass memory  26  larger sequential accesses. In addition, the use of the further aspects of this invention enable certain elementary memory operations (e.g., fill, move) to be accomplished locally (e.g., within the system DRAM module  14 ) without active involvement of the CPU  12 . 
       FIG. 6  illustrates one non-limiting embodiment of the host device  10  used with the mass storage memory device  20 , referred to in  FIG. 6  simply as a memory card  20 . The mass storage memory device  20  can be removable or it can be embedded in the device  10 . In this exemplary embodiment the host device  10  is embodied as a user equipment (UE), shown in both plan view (left) and sectional view (right). In  FIG. 6  the host device (UE)  10  has a graphical display interface  120  and a user interface  122  illustrated as a keypad but understood as also encompassing touch screen technology at the graphical display interface  120  and voice recognition technology received at a microphone  124 . A power actuator  126  controls the device being turned on and off by the user. The exemplary UE  10  may have a camera  128  which is shown as being forward facing (e.g., for video calls) but may alternatively or additionally be rearward facing (e.g., for capturing images and video for local storage). The camera  128  is controlled by a shutter actuator  30  and optionally by a zoom actuator  32  which may alternatively function as a volume adjustment for the speaker(s)  34  when the camera  128  is not in an active mode. 
     As an example, image data captured by the camera  128  can be stored in the mass storage memory device  20  under control of a camera application and can thus benefit from the use of the embodiments of this invention. As another example, audio data captured by the microphone  124  can be stored in the mass storage memory device  20  under control of an audio application and can thus also benefit from the use of the embodiments of this invention. 
     Within the sectional view of  FIG. 6  are seen multiple transmit/receive antennas  36  that are typically used for cellular communication. The antennas  36  may be multi-band for use with other radios in the UE. The operable ground plane for the antennas  36  is shown by shading as spanning the entire space enclosed by the UE housing though in some embodiments the ground plane may be limited to a smaller area, such as disposed on a printed wiring board on which the power chip  38  is formed. The power chip  38  controls power amplification on the channels being transmitted and/or across the antennas that transmit simultaneously where spatial diversity is used, and amplifies the received signals. The power chip  38  outputs the amplified received signal to a radio frequency (RF) chip  40  which demodulates and downconverts the signal for baseband processing. A baseband (BB) chip  42  detects the signal which is then converted to a bit stream and finally decoded. Similar processing occurs in reverse for signals generated in the host device  10  and transmitted from it. 
     Signals going to and from the camera  128  may pass through an image/video processor  44  that encodes and decodes the various image frames. A separate audio processor  46  may also be present controlling signals to and from the speakers  34  and the microphone  124 . The graphical display interface  120  is refreshed from a frame memory  48  as controlled by a user interface chip  50  which may process signals to and from the display interface  20  and/or additionally process user inputs from the keypad  22  and elsewhere. 
     Certain embodiments of the UE  10  may also include one or more secondary radios such as a wireless local area network radio WLAN  37  and a Bluetooth7 radio  39 , which may incorporate an antenna on the chip or be coupled to an antenna off the chip. Throughout the apparatus are various memories such as random access memory RAM, which can include the system DRAM  14 , read only memory ROM  45 , and in some embodiments removable memory such as the illustrated memory card  20  on which various programs and data may be stored. All of these components within the UE  10  are normally powered by a portable power supply such as a battery  49 . 
     The processors  38 ,  40 ,  42 ,  44 ,  46 ,  50 , if embodied as separate entities in a UE  10 , may operate in a slave relationship to the main processor (CPU)  12 , which may then be in a master relationship to them. Certain embodiments may be disposed across various chips and memories as shown, or disposed within another processor that combines some of the functions described above for  FIG. 6 . Any or all of these various processors of  FIG. 6  access one or more of the various memories, which may be on chip with the processor or separate from the chip with the processor. Note that the various integrated circuits (e.g., chips  38 ,  40 ,  42 , etc.) that were described above may be combined into a fewer number than described and, in a most compact case, may all be embodied physically within a single chip. 
     In this exemplary embodiment the CPU  12  of the UE  10  (the host device) operates with the memory card  20  (the mass storage memory device) as described above with respect to  FIGS. 5A, 5B and 5C  so that the memory card  20  can be extended to use at least a portion of the system Dynamic RAM  14  of the UE  10  as described above. 
     An aspect of the exemplary embodiments of this invention is a method, shown in  FIG. 7 , that includes ( 7 A) receiving a command (the command can arrive, for example, via a file system layer (SW) and a driver layer (SW) and a host controller (HW)) originating from an initiator (e.g., an application, a file system, a driver or an OS utility) at a controller (e.g., a memory controller) associated with a non-volatile mass memory coupled with a host device. The command is a command to write data that is currently resident in a memory of the host device to the non-volatile mass memory. The memory of the host device may comprise, as non-limiting examples, DRAM, MRAM, PCM (phase change memory), RRAM (resistive random access memory), magnetic random access memory, ferroelectric random access memory and the like. The method further includes ( 7 B) moving the data that is currently resident in the memory of the host device from an original location to a portion of the memory allocated for use at least by the non-volatile mass memory. The method further includes ( 7 C) acknowledging to the initiator that the command to write the data to the non-volatile mass memory has been executed 
     In the method described in  FIG. 7  and the preceding paragraph, further comprising, subsequent to acknowledging, moving the data from the memory of the host device to the non-volatile mass memory. 
     In the method described in  FIG. 7  and the preceding paragraphs, where the data is physically moved to the portion of the memory that is allocated for use at least by the non-volatile mass memory. 
     In the method described in  FIG. 7  and the preceding paragraphs, where the data is logically moved to the portion of the memory that is allocated for use at least by the non-volatile mass memory by changing a value of a memory address pointer to the data or a value of a header of the data. 
     In the method described in  FIG. 7  and the preceding paragraphs where the data originates with the initiator and where the initiator is resident in the host device. 
     In the method described in  FIG. 7  and the preceding paragraph, where the initiator comprises at least one of an application program, a file system, a driver, and an operating system utility. 
     In the method described in  FIG. 7  and the preceding paragraphs, where the data originates with the initiator and where the initiator is external to the host device. 
     In the method described in  FIG. 7  and the preceding paragraph, where the initiator is embodied as a peripheral device that is connected with the host device. 
     In the method described in  FIG. 7  and the preceding paragraphs, where the memory of the host device comprises a dynamic random access memory, and further comprising autonomously performing an elementary memory operation in the memory of the host device. 
     In the method described in  FIG. 7  and the preceding paragraph, where the elementary memory operation is a data fill operation to set a specified plurality of memory locations to a specified value. 
     In the method described in  FIG. 7  and the preceding paragraphs, where the elementary memory operation is a data move operation to move data from a first specified plurality of memory locations to a second specified plurality of memory locations. 
     In the method described in  FIG. 7  and the preceding paragraph, where the data move operation further comprises setting the first specified plurality of memory locations to a predetermined value. 
     In the method described in  FIG. 7  and the preceding paragraphs, further comprising while the data is resident in the portion of the memory allocated for use at least by the non-volatile mass memory, responding to a read command for the data to read the data resident in the portion of the memory allocated for use by the non-volatile mass memory and copying the read data to an initiator of the read command. 
     In the method described in  FIG. 7  and the preceding paragraphs, where moving the data that is currently resident in the memory of the host device from an original location to a portion of the memory allocated for use at least by the non-volatile mass memory is initiated by the controller associated with the non-volatile mass memory. 
     In the method described in  FIG. 7  and the preceding paragraphs, where the method is performed as a result of execution of computer program instructions by the controller. 
       FIG. 8  is a logic flow diagram that illustrates the operation of a method, and a result of execution of computer program instructions embodied on a computer readable memory, further in accordance with the exemplary embodiments of this invention. In accordance with these exemplary embodiments a method performs, at Block  8 A, providing a data processing system comprising at least one data processor and at least one memory comprised of dynamic random access memory. At Block  8 B there is a step of autonomously performing an elementary memory operation in the memory. 
     In the method described in  FIG. 8  and the preceding paragraph, where the elementary memory operation is a data fill operation to set a specified plurality of memory locations to a specified value. 
     In the method described in  FIG. 8  and the preceding paragraphs, where the elementary memory operation is a data move operation to move data from a first specified plurality of memory locations to a second specified plurality of memory locations. 
     In the method described in  FIG. 8  and the preceding paragraph, where the data move operation further comprises setting the first specified plurality of memory locations to a predetermined value. 
     The various blocks shown in  FIGS. 7 and 8  may be viewed as method steps, and/or as operations that result from operation of computer program code, and/or as a plurality of coupled logic circuit elements constructed to carry out the associated function(s). 
     In general, the various exemplary embodiments may be implemented in hardware or special purpose circuits, software, logic or any combination thereof. For example, some aspects may be implemented in hardware, while other aspects may be implemented in firmware or software which may be executed by a controller, microprocessor or other computing device, although the invention is not limited thereto. While various aspects of the exemplary embodiments of this invention may be illustrated and described as block diagrams, flow charts, or using some other pictorial representation, it is well understood that these blocks, apparatus, systems, techniques or methods described herein may be implemented in, as non-limiting examples, hardware, software, firmware, special purpose circuits or logic, general purpose hardware or controller or other computing devices, or some combination thereof. 
     It should thus be appreciated that at least some aspects of the exemplary embodiments of the inventions may be practiced in various components such as integrated circuit chips and modules, and that the exemplary embodiments of this invention may be realized in an apparatus that is embodied as an integrated circuit. The integrated circuit, or circuits, may comprise circuitry (as well as possibly firmware) for embodying at least one or more of a data processor or data processors, a digital signal processor or processors, baseband circuitry and radio frequency circuitry that are configurable so as to operate in accordance with the exemplary embodiments of this invention. 
     An apparatus in accordance with the exemplary embodiments includes means for sending a command from a host device to a controller associated with a non-volatile mass memory coupled with the host device, the command being a command to write data that is currently resident in a memory of the host device to the non-volatile mass memory; means for moving the data that is currently resident in the memory of the host device from an original location to a portion of the memory allocated for use by the non-volatile mass memory; and means for acknowledging to the host device that the command to write the data to the non-volatile mass memory has been executed. 
     Various modifications and adaptations to the foregoing exemplary embodiments of this invention may become apparent to those skilled in the relevant arts in view of the foregoing description, when read in conjunction with the accompanying drawings. However, any and all modifications will still fall within the scope of the non-limiting and exemplary embodiments of this invention. 
     It should be noted that the terms “connected,” “coupled,” or any variant thereof, mean any connection or coupling, either direct or indirect, between two or more elements, and may encompass the presence of one or more intermediate elements between two elements that are “connected” or “coupled” together. The coupling or connection between the elements can be physical, logical, or a combination thereof. As employed herein two elements may be considered to be “connected” or “coupled” together by the use of one or more wires, cables and/or printed electrical connections, as well as by the use of electromagnetic energy, such as electromagnetic energy having wavelengths in the radio frequency region, the microwave region and the optical (both visible and invisible) region, as several non-limiting and non-exhaustive examples. 
     Furthermore, some of the features of the various non-limiting and exemplary embodiments of this invention may be used to advantage without the corresponding use of other features. As such, the foregoing description should be considered as merely illustrative of the principles, teachings and exemplary embodiments of this invention, and not in limitation thereof.