Patent Publication Number: US-11640278-B2

Title: Random number generation device and method of generating random numbers

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application is based upon and claims the benefit of priority of the prior Japanese Patent Application No. 2019475609, filed on Sep. 26, 2019, the entire contents of which are incorporated herein by reference. 
     FIELD 
     The embodiments discussed herein are related to a random number generation device and a method of generating random numbers, 
     BACKGROUND 
     A method is known in which, in a random number generation device that generates random numbers, an M-sequence cyclic code generator generates a seed value and sequentially supplies the seed value to a plurality of M-sequence cyclic code generators, thereby reducing the number of seed registers and suppressing an increase in the scale of hardware. In addition, a method is known in which bits of uniform random numbers generated by a plurality of uniform random number generators are rearranged to generate a plurality of uniform random numbers, and then the same terms of the uniform random numbers are summed to generate a normally distributed random numbers while avoiding correlation between sequences. 
     Related art is disclosed in Japanese Laid-open Patent Publication No. 2007-87064 and Japanese Laid-open Patent Publication No. 2005-38229. 
     SUMMARY 
     According to an aspect of the embodiments, a random number generation device includes: a plurality of first uniform random number generators configured to respectively generate a plurality of first uniform random numbers; a plurality of first normal random number generators configured to respectively generate a plurality of first normal random numbers based on the plurality of first uniform random numbers; a plurality of second uniform random number generators configured to perform a logical operation on bit values of two or more of the first uniform random numbers to respectively generate a plurality of second uniform random numbers; and at least one second normal random number generator configured to generate at least one second normal random number based on the plurality of second uniform random numbers. 
     The object and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the claims. 
     It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are not restrictive of the invention. 
    
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         FIG.  1    is a block diagram illustrating an example of a random number generation device according to an embodiment; 
         FIG.  2    is a block diagram illustrating an example of a system in which the random number generation device illustrated in.  FIG.  1    is installed; 
         FIG.  3    is a block diagram illustrating another example of the system in which the random number generation device illustrated in  FIG.  1    is installed; 
         FIG.  4    is a block diagram illustrating an example of a random number generation device according to another embodiment; 
         FIG.  5    is a block diagram illustrating an example of a random number generation device according to another embodiment; 
         FIG.  6    is a block diagram illustrating an example of the scale of a circuit used for generating a normal random number in the random number generation device illustrated in  FIG.  5   ; 
         FIG.  7    is a block diagram illustrating an example of a random number generation device according to another embodiment; 
         FIG.  8    is a block diagram illustrating an example of a random number generation device according to another embodiment; and 
         FIG.  9    is a block diagram illustrating an example of a random number generation device according to another embodiment. 
     
    
    
     DESCRIPTION OF EMBODIMENTS 
     Nowadays, in order to improve accuracy of calculation of various simulations and numerical analyses by the Monte Carlo method or the like, the number of normal random numbers used for calculation tends to increase, and the number of random number generation devices used for calculation tends to increase. As a result, the scale of the hardware of the random number generation devices mounted in the information processing apparatus that executes calculation such as simulation increases, and the cost for generating random numbers increases. 
     In one aspect, the present embodiment generates a larger number of normal random numbers while suppressing an increase in circuit scale. 
     Hereinafter, embodiments will be described with reference to the drawings. 
       FIG.  1    illustrates an example of a random number generation device according to an embodiment. The random number generation device  100  illustrated in  FIG.  1    includes a normal random number generation units NGEN (NGEN 1 , NGEN 2 , NGEN 3 ). The normal random number generation unit NGEN 1  includes a plurality of uniform random number generators  10  and a normal random number generator  11 . The normal random number generation unit NGEN 2  includes a plurality of uniform random number generators  20  and a normal random number generator  21 . The normal random number generation unit NGEN 3  includes a plurality of uniform random number generators  30  and a normal random number generator  31 . 
     The uniform random number generators  10  generate respective uniform random numbers URN 1 , and the normal random number generator  11  generates normal random numbers NRN 1  based on the uniform random numbers URN 1  generated by the respective uniform random number generators  10 . The uniform random number generators  20  generate respective uniform random numbers URN 2 , and the normal random number generator  21  generates normal random numbers NRN 2  based on the uniform random numbers URN 2  generated by the respective uniform random number generators  20 . 
     Each of the uniform random numbers URN 1 , URN 2  is an example of a first uniform random number, and each of the normal random numbers NRN 1 , NRN 2  is an example of a first normal random number. Uniform random numbers URN 3  are examples of a second uniform random number, and a normal random number NRN 3  is an example of a second normal random number. Each of the uniform random number generators  10 ,  20  is an example of a first uniform random number generator, and each of the normal random number generators  11 ,  21  is an example of a first normal random number generator. Each of the uniform random number generators  30  is an example of a second uniform random number generator, and the normal random number generator  31  is an example of a second normal random number generator. 
     The uniform random number generators  30  generate the respective uniform random numbers URN 3  based on two uniform random numbers URN 1 , URN 2  out of a plurality of uniform random numbers URN 1  and a plurality of uniform random numbers URN 2  generated by the uniform random number generators  10 ,  20 . Although the uniform random number generators  30  each receive a single uniform random number URN 1  and a single uniform random number URN 2  in  FIG.  1   , the uniform random number generator  30  may receive two uniform random numbers URN 1  or two uniform random numbers URN 2 . 
     For example, the uniform random number generators  30  each include a logical operation circuit (logical operation unit) that performs a bitwise bit operation on a plurality of bits of the uniform random numbers URN 1 , URN 2 . The normal random number generator  31  generates normal random numbers NRN 3  based on the uniform random numbers URN 3  generated by the respective uniform random number generators  30 . 
     For example, the random number generation device  100  includes twelve uniform random number generators  10 , twelve uniform random number generators  20 , and twelve uniform random number generators  30 . Thus, each of the normal random number generation units NGEN 1 , NGEN 2 , NGEN 3  are able to generate the normal random numbers NRN (NRN 1 , NRN 2 , NRN 3 ) from the plurality of uniform random numbers URN 1 , URN 2 , URN 3  in accordance with the central limit theorem. 
     In the random number generation device  100  illustrated in  FIG.  1   , the uniform random number generators  30  each generate the uniform random number URN 3  based on two uniform random numbers out of the uniform random numbers URN 1 , URN 2  generated by the uniform random number generators  10 ,  20 . However, the uniform random number generator  30  may generate the uniform random number URN 3  based on three or more uniform random numbers URN (URN 1 , URN 2 , or URN 1  and URN 2 ). 
     According to the present embodiment, the uniform random numbers URN 3  used to generate the normal random numbers NRN 3  are generated by using the uniform random numbers URN 1 , URN 2  generated by the uniform random number generators  10 ,  20 . Thus, the uniform random number generators  30  may be configured as a simple circuit compared to that of the uniform random number generators  10 ,  20 . This may allow downscaling of the circuit of the random number generation device  100  compared to that of other normal random number generation devices that generate the same number of normal random numbers NRN. For example, a larger number of normal random numbers NRN may be generated while suppressing the circuit scale of the random number generation device  100 . For example, when a circuit size (the number of logic gates or the like) usable for the random number generation device  100  is fixed, a large number of the normal random numbers NRN may be generated compared to other normal random number generation devices. 
       FIG.  2    illustrates an example of a system in which the random number generation device  100  illustrated in  FIG.  1    is installed. A system  210  illustrated in  FIG.  2    includes, for example, a server system  300  that functions as a cloud computer. The server system  300  includes a plurality of calculation servers  310  and a management server  320  that manages operations of the calculation servers  310 . The server system  300  is accessible from a plurality of user terminals  500  via a network NW such as the Internet. 
     Accordingly, for example, the user is able to cause the server system  300  to execute various types of information processing via the user terminal  500 . Examples of information processing executable by the server system  300  include, for example, numerical analyses, image processing, financial simulations, various simulations in the design of large-scale integration (LSI), and machine learning such as deep learning. The server system  300  may be used for Web search systems or cloud services. 
     For example, each of the calculation servers  310  includes a central processing unit (CPU), a plurality of graphics processing units (GPUs), and a plurality of field-programmable gate arrays (FPGAs). The calculation server  310  may include two or more CPUs mounted therein. For example, the GPUs and the FPGAs operate as accelerators based on instructions from the CPU. The calculation server  310  may include only FPGAs or may include FPGAs and a digital signal processor (DSP). 
     A plurality of random number generation devices  100  illustrated in  FIG.  1    are provided in the FPGA by transferring circuit information of the random number generation device  100  to one or more FPGAs. The normal random numbers NRN 1 , NRN 2 , NRN 3  generated by the random number generation device  100  are used for, for example, numerical analyses, image processing, or various simulations. 
     According to the present embodiment, the circuit scale of the random number generation device  100  that generates normal random numbers may be reduced compared to the circuit scale of other random number generation devices. Thus, for example, a larger number of the random number generation devices  100  may be installed in an area for the random number generation device  100  allocated in the FPGA. Accordingly, even when the number of normal random numbers used for calculation is increased for improvement of accuracy of numerical calculation or the like, a problem in that the number of normal random numbers to be generated is insufficient may be suppressed. The random number generation device  100  may be installed in application-specific integrated circuits (ASICs) or the like mounted on the calculation server  310 . 
     For example, in a financial simulation, the number of normal random numbers to be used exponentially increases by increasing the number of stock brands. In an LSI design simulation, the number of normal random numbers to be used exponentially increases by increasing the number of parameters. In a cloud service in which an FPGA is mounted, for example, when a Monte Carlo simulation is executed in parallel by a large number of users (user terminals  500 ), a large number of normal random numbers are used. 
       FIG.  3    illustrates another example of the system in which the random number generation device  100  illustrated in  FIG.  1    is installed. A system  220  illustrated in  FIG.  3    is a server system  400  that includes, for example, a plurality of calculation servers  410  and a management server  420 . The calculation servers  410  are coupled to each other via a system bus and coupled to the management server  420  via a management bus. 
     As is the case with the calculation servers  310  illustrated in  FIG.  2   , the calculation servers  410  each include a CPU, a plurality of FPGAs, and a plurality of GPUs that function as accelerators. The calculation server  410  may include a DSP. A plurality of random number generation devices  100  illustrated in  FIG.  1    are provided in the FPGA by transferring the circuit information of the random number generation device  100  to at least one FPGA, As is the case with the server system  300  illustrated in  FIG.  2   , the normal random numbers NRN generated by the random number generation device  100  are used for numerical analyses, image processing, financial simulations, various simulations in LSI design, and machine learning such as deep learning. 
     As described above, according to the embodiment illustrated in  FIGS.  1  to  3   , the uniform random number generator  30  may be configured as a simple circuit compared to the uniform random number generators  10 ,  20 . This may reduce the circuit scale of the random number generation device  100  compared to the circuit scale of other normal random number generation devices. For example, a larger number of normal random numbers NRN may be generated while suppressing the circuit scale of the random number generation device  100 . Since the normal random number generation unit NGEN 3  includes twelve uniform random number generators  30 , the normal random number generation unit NGEN 3  is able to generate the normal random number NRN 3  from the plurality of uniform random numbers URN 1 , URN 2  in accordance with the central limit theorem. 
       FIG.  4    illustrates an example of a random number generation device according to another embodiment. Detailed description of the same elements as those illustrated in  FIG.  1    is omitted. For example, a random number generation device  102  illustrated in  FIG.  4    is provided in the FPGA or an ASIC (not illustrated) of the calculation server  310  illustrated in  FIG.  2    or in the FPGA or an ASIC (not illustrated) of the calculation server  410  illustrated in  FIG.  3   . 
     The random number generation device  102  includes three normal random number generation units NGEN (NGEN 1 , NGEN 2 , NGEN 3 ). For example, the normal random number generation unit NGEN 1  includes twelve uniform random number generators  10  (# 1  to  12 ) and an adder  12 . For example, the normal random number generation unit NGEN 2  includes 12 uniform random number generators  20  (# 1  to  12 ) and an adder  22 . The adders  12 ,  22  are examples of the first normal random number generator. 
     For clear understanding of description,  FIG.  4    illustrates an example which the random number generation device  102  includes three normal random number generation units NGEN 1  to NGEN 3 . Actually, the random number generation device  102  includes a plurality of sets of three normal random number generation units NGEN 1  to NGEN 3  in accordance with a circuit area allocated in the FPGA. This allows the random number generation device  102  to generate a large number of normal random numbers NRN (NRN 1 , NRN 2 , NRN 3 ). 
     In the normal random number generation unit NGEN 1 , the uniform random number generators  10  (# 1  to  12 ) generate, based on seed values (not illustrated), twelve uniform random numbers URN 1  (# 1  to  12 ) that are different from each other. Since there are different seed values for the different uniform random number generators  10  (# 1  to  12 ), the twelve uniform random numbers URN 1  (# 1  to  12 ) are not correlated to each other. 
     The adder  12  adds up a plurality of uniform random numbers URN 1  to generate a normal random number NRN 1 . For example, the adder  12  adds up twelve uniform random numbers URN 1  (# 1  to  12 ) not correlated to each other. This allows generation of the normal random number NRN 1  by the central limit theorem. 
     In the normal random number generation unit NGEN 2 , the uniform random number generators  20  (# 1  to  12 ) generate, based on seed values (not illustrated), twelve uniform random numbers URN 2  (# 1  to  12 ) that are different from each other. Since there are different seed values for the different uniform random number generators  20  (# 1  to  12 ), the twelve uniform random numbers URN 2  (# 1  to  12 ) are not correlated to each other. 
     The adder  22  adds up a plurality of uniform random numbers URN 2  to generate a normal random number NRN 2 . For example, the adder  22  adds up twelve uniform random numbers URN 2  (# 1  to  12 ) not correlated to each other. This allows generation of the normal random number NRN 2  in accordance with the central limit theorem. 
     For example, the normal random number generation unit NGEN 3  includes twelve exclusive OR circuits XOR 1  (# 1  to  12 ) and an adder  32 . Each of the exclusive OR circuits XOR 1  is an example of the logical operation unit and an example of a first exclusive OR circuit. The adder  32  is an example of the second normal random number generator. Hereinafter, the exclusive OR circuit XOR 1  is also simply referred to as an XOR 1 . 
     Each of the XOR 1 s (# 1  to  12 ) performs a logical operation on two uniform random numbers URN 1  generated by two uniform random number generators  10  or two uniform random numbers URN 2  generated by two uniform random number generators  20 , thereby generating a uniform random number URN 3 . For example, each of the XOR 1 s performs a bit operation of an exclusive OR on a plurality of bits of two uniform random numbers URN 1  (or URN 2 ) bitwise, thereby generating the uniform random number URN 3 . For example, each of the XOR 1 s takes an exclusive OR of the bit values of the same bit numbers in two uniform random numbers URN 1  (or URN 2 ), thereby generating bit values of the uniform random number URN 3 . 
     For example, in  FIG.  4   , the XOR 1  (# 1 ) generates the uniform random number URN 3  (# 1 ) based on the uniform random numbers URN 1  (# 1 , # 2 ), and the XOR 1  (# 2 ) generates the uniform random number URN 3  (# 2 ) based on the uniform random numbers URN 1  (# 3 , # 4 ). The XOR 1  (# 6 ) generates the uniform random number URN 3  (# 6 ) based on the uniform random numbers URN 1  (# 11 /# 12 ). When the variable n is any of 1 to 6, the XOR 1  (#n) generates the uniform random number URN 3  (#n) based on the uniform random numbers URN 1  (# 2   n - 1 ) and URN 1  (# 2   n ). 
     The XOR 1  (# 7 ) generates the uniform random number URN 3  (# 7 ) based on the uniform random numbers URN 2  (# 1 , # 2 ), and the XOR 1  (# 8 ) generates the uniform random number URN 3  (# 8 ) based on the uniform random numbers URN 2  (# 3 , # 4 ). The XOR 1  (# 12 ) generates the uniform random number URN 3  (# 12 ) based on the uniform random numbers URN 2  (# 11 , # 12 ). When the variable n is any of 7 to 12, the XOR 1  (#n) generates the uniform random number URN 3  (#n) based on the uniform random numbers URN 2  (# 2 (n- 6 )- 1 ) and URN 2  (# 2 (n- 6 )). 
     The two uniform random numbers (URN 1  or URN 2 ) supplied to any one of the XOR 1 s (# 1  to  12 ) are generated based on different seed values, and accordingly, not correlated to each other. it has been confirmed that the XOR 1  (any one of # 1  to  12 ) generates the uniform random number URN 3  correlated to neither of two uniform random numbers when the two uniform random numbers having been input are not correlated to each other. 
     The adder  32  adds up a plurality of uniform random numbers URN 3  to generate a normal random number NRN 3 . For example, the adder  32  adds up twelve uniform random numbers URN 3  (# 1  to  12 ) not correlated to each other. This allows generation of the normal random number NRN 3  in accordance with the central limit theorem. 
     For example, the uniform random number generators  10 ,  20  are provided by utilizing Xorshift  128 , which is one of pseudorandom number generators. The uniform random number generators  10 ,  20  by the Xorshift  128  include, for example, four exclusive OR circuits (XORs) coupled in series. When the XOR includes four NAND gates, each of the uniform random number generators  10 ,  20  with Xorshift  128  includes 16 NAND gates. Accordingly, a logic scale of the normal random number generation unit NGEN 1  except for the logic of the adder  12  corresponds to a logic scale of 192 NAND gates. Likewise, a logic scale of the normal random number generation unit NGEN 2  except for the logic of the adder  22  corresponds to a logic scale of 192 NAND gates. 
     The normal random number generation unit NGEN 3  except for the logic of the adder  32  includes twelve XOR 1 s, corresponding to a logic scale of  48  NAND gates. Therefore, the logic scale of the uniform random number generator  10 ,  20  and the XOR 1 s of the random number generation device  102  is  432  (192+192+48) in terms of NAND gates. 
     When the normal random number generation unit NGEN 3  is configured with twelve uniform random number generators  10  as is the case with the normal random number generation unit NGEN 1 , the logic scale of the normal random number generation unit NGEN 3  except for the logic scale of the adder  32  corresponds to the logic scale of  192  NAND gates. In this case, the logic scale of the normal random number generation device including three normal random number generation units NGEN 1 , NGEN 2 , NGEN 3  of the same logic configurations is  576  (192+192+192) in terms of NAND gates. Accordingly, the logic scale of the random number generation device  102  except for the adders  12 ,  22 ,  32  is able to be reduced by 25% (( 576 - 432 )/ 576 ) compared to the logic scale of a normal random number generation device including three normal random number generation units that are identical to each other. 
     As has been described, according to the embodiment illustrated in  FIG.  4   , as is the case with the embodiment illustrated in  FIG.  1   , the uniform random numbers URN 1 , URN 2  generated by the uniform random number generators  10 ,  20  are used to generate the uniform random number URN 3  by using the XOR 1 s which are a type of the logical operation unit. Accordingly, the circuit scale of the uniform random number generators (XOR 1 s) that generate twelve uniform random numbers URN 3  to be supplied to the adder  32  is able to be reduced compared to the circuit scale of the twelve uniform random number generators  10  (or  20 ). As a result, a larger number of normal random numbers NRN 1 , NRN 2 , NRN 3  may be generated while suppressing the circuit scale of the random number generation device  102 . 
     According to the present embodiment, the uniform random numbers URN 1 , URN 2  generated by the uniform random number generators  10 ,  20  are used to generate the uniform random number URN 3  by using the XOR 1 s, and the normal random number NRN 3  is generated by adding up the uniform random numbers URN 1 , URN 2 , URN 3 . Thus, the normal random numbers NRN 3  conforming to a high-quality normal distribution may be generated in accordance with the central limit theorem. 
       FIG.  5    illustrates an example of a random number generation device according to another embodiment. Elements similar to or the same as those illustrated in  FIG.  4    are denoted by the same reference signs and detailed description thereof is omitted. For example, a random number generation device  104  illustrated in  FIG.  5    is provided in the FPGA or the ASIC (not illustrated) of the calculation server  310  illustrated in  FIG.  2    or in the FPGA or the ASIC (not illustrated) of the calculation server  410  illustrated in  FIG.  3   . The random number generation device  104  includes three normal random number generation units NGEN 1 , NGEN 2 , NGEN 3 . Since the normal random number generation units NGEN 1 , NGEN 2  have the same configuration as those of the normal random number generation units NGEN 1 , NGEN 2  illustrated in  FIG.  4   , illustration thereof is omitted. 
     For example, the normal random number generation unit NGEN 3  includes eight XOR 1 s, four XOR 2 s, and the adder  32 . Each of the XOR 1 s is an example of the first exclusive OR circuit, and each of the XOR 2 s is an example of a second exclusive OR circuit. For example, each of the XOR 1 s generates the uniform random number URN 3  based on two uniform random numbers URN 1  generated by two uniform random number generators  10  ( FIG.  4   ) or two uniform random numbers URN 2  generated by two uniform random number generators  20  ( FIG.  4   ). 
     Each of the XOR 2 s generates a uniform random number URN 4  based on two uniform random numbers URN 3  generated by 2 XOR 1 s. For example, each of the XOR 2 s performs a bit operation of an exclusive OR on a plurality of bits of two uniform random numbers URN 3  bitwise, thereby generating the uniform random number URN 4 . For example, each of the XOR 2 s takes an exclusive OR of the bit values of the same bit numbers in two uniform random numbers URN 3 , thereby generating bit values of the uniform random number URN 4 . 
     The adder  32  adds up a plurality of uniform random numbers URN 3 , URN 4  to generate the normal random number NRN 3 . For example, the adder  22  adds up twelve uniform random numbers URN 3 , URN 4  not correlated to each other. This allows generation of the normal random number NRN 3  in accordance with the central limit theorem. For example, it is confirmed in advance that the uniform random numbers URN 4  generated by the XOR 2 s are not correlated to the URN 3  generated by the XOR 1 s or any one of the URN 4  is not correlated to another UNR 4  by giving various seed values to the uniform random number generators  10 ,  20  ( FIG.  4   ). 
       FIG.  6    illustrates an example of the scale of the circuit used for generating the normal random number NRN 3  in the random number generation device  104  illustrated in  FIG.  5   .  FIG.  6    illustrates a configuration of a circuit that generates two normal random numbers NRN 1 , two normal random numbers NRN 2 , and three normal random numbers NRN 3 . In this case, the circuit scale of the  24  uniform random number generators  10 ,  24  uniform random number generators  20 , and 36 XOR 1 s and XOR 2 s included in the random number generation device  104  is  912  in terms of NAND gates. 
     When 36 uniform random number generators  10  are provided instead of the 36 XOR 1 s and XOR 2 s, the circuit scale of the random number generation device is  1344  in terms of NAND gates. Accordingly, the logic scale of the random number generation device  104  except for the adders  12 ,  22 ,  32  is able to be reduced by 32% (( 1344 - 912 ) 11344 ) compared to the logic scale of a normal random number generation device including seven normal random number generators that are identical to each other. 
     As has been described, according to the embodiment illustrated in  FIGS.  5  and  6   , a larger number of normal random numbers NRN may be generated while further suppressing the circuit scale of the random number generation device  104  compared to the embodiments illustrated in  FIGS.  1  and  4   . Furthermore, the normal random numbers NRN 3  conforming to a high-quality normal distribution may be generated in accordance with the central limit theorem when the uniform random numbers URN 3 , URN 4  used to generate the normal random numbers NRN 3  are generated by using the XOR 1 s and XOR 2 s. 
       FIG.  7    illustrates an example of a random number generation device according to another embodiment. Elements similar to or the same as those illustrated in  FIG.  4    are denoted by the same reference signs and detailed description thereof is omitted. For example, a random number generation device  106  illustrated in  FIG.  7    is provided in the FPGA or the ASIC (not illustrated) of the calculation server  310  illustrated in  FIG.  2    or in the FPGA or the ASIC (not illustrated) of the calculation server  410  illustrated in  FIG.  3   . The random number generation device  106  includes three normal random number generation units NGEN 1 , NGEN 2 , NGEN 3 . The normal random number generation units NGEN 1 , NGEN 2  have the same configuration as those of the normal random number generation units NGEN 1 , NGEN 2  illustrated in  FIG.  4   . 
     In the normal random number generation unit NGEN 3 , cyclic shifters CSFT 1  are coupled to inputs of each of the XOR 1 s of the normal random number generation unit NGEN 3  illustrated in  FIG.  4   . Each of the shifters CSFT 1  is an example of a first shifter. The configuration of the random number generation device  106  is similar to or the same as that of the random number generation device  102  illustrated in  FIG.  4    except for addition of the shifters CSFT 1 . 
     Each of the shifters CSFT 1  cyclically shifts the bits of the uniform random number URN 1  (or URN 2 ) output from the uniform random number generator  10  (or  20 ) and outputs the shifted uniform random number URN 1  (or URN 2 ) to the XOR 1 . The number of bits to be shifted in  24  shifters CSFT corresponding to a single adder  32  may be equal to each other or different from each other. 
     According to the present embodiment, the uniform random numbers URN 1  (or URN 2 ) are input to the XOR 1 s via the cyclic shifters CSFT. Accordingly, for example, even when the uniform random number generators  10  (or  20 ) generate the uniform random numbers URN 1  (or URN 2 ) based on the same seed value, twelve uniform random numbers URN 3  are able to be generated with the correlation therebetween abolished. The number of bits to be shifted by the shifters CSFT is predetermined so that the uniform random numbers URN 3  respectively generated by a plurality of the XOR 1 s are not correlate to each other. Thus, the normal random numbers NRN 3  conforming to a high-quality normal distribution may be generated in accordance with the central limit theorem, 
     With the shifters CSFT 1 , the circuit scale of the random number generation device  106  becomes larger than the circuit scale of the random number generation device  102  illustrated in  FIG.  4   . However, with the shifters CSFT 1 , for example, even when the uniform random number generators  10  (or  20 ) use a common seed value, the correlation between the uniform random numbers URN 1 , URN 2  used for generating the normal random numbers NRN 3  may be lowered. Thus, for example, a generation circuit that generates a plurality of seed values may be omitted, and a larger number of normal random numbers NRN 3  conforming to a high-quality normal distribution may be generated while suppressing an increase in the circuit scale when the entirety of the random number generation device  106  is seen. 
     As has been described, according to the embodiment illustrated in  FIG.  7   , for example, even when the uniform random numbers URN 1 , URN 2  are generated based on the same seed value, twelve uniform random numbers URN 3  the correlation between which are abolished may be generated by coupling the cyclic shifters CSFT to the inputs of the XOR 1 s. As a result, a larger number of normal random numbers NRN 3  conforming to a high-quality normal distribution may be generated while suppressing an increase in the circuit scale. 
       FIG.  8    illustrates an example of a random number generation device according to another embodiment. Elements similar to or the same as those of the above-described embodiments are denoted by the same reference signs and detailed description thereof is omitted. For example, a random number generation device  108  illustrated in  FIG.  8    is provided in the FPGA or the ASIC (not illustrated) of the calculation server  310  illustrated in  FIG.  2    or in the FPGA or the ASIC (not illustrated) of the calculation server  410  illustrated in  FIG.  3   . 
     In the normal random number generation unit NGEN 3 , cyclic shifters CSFT 2  are coupled to inputs of each of the XOR 2 s of the normal random number generation unit NGEN 3  illustrated in  FIG.  5   . Each of the shifters CSFT 2  is an example of a second shifter. The configuration of the random number generation device  108  is similar to or the same as that of the random number generation device  104  illustrated in  FIG.  5    except for addition of the shifters CSFT 2 . 
     Each of the shifters CSFT 2  cyclically shifts the bits of the uniform random number URN 3  output from the XOR 1  and outputs the shifted uniform random number URN 3  to the XOR 2 . The number of bits to be shifted in 16 shifters CSFT 1  and eight shifters CSFT 2  corresponding to a single adder  32  may be equal to each other or different from each other. The numbers of bits to be shifted by the shifters CSFT 1 , CSFT 2  are predetermined so that the uniform random numbers URN 3 , URN 4  respectively generated by a plurality of the XOR 1 s and a plurality of the XOR 2 s are not correlate to each other, Thus, the normal random numbers NRN 3  conforming to a high-quality normal distribution may be generated in accordance with the central limit theorem. 
     According to the present embodiment, as is the case with the random number generation device  106  illustrated in  FIG.  7   , even when the uniform random number generators  10 ,  20  generate the uniform random numbers URN 1 , URN 2  based on the same seed value, twelve uniform random numbers URN 3 , URN 4  are able to be generated with the correlation therebetween abolished. 
     As is the case with the random number generation device  104  illustrated in  FIG.  5   , each of the XOR 2 s generates a different uniform random number URN 4  by using the uniform random numbers URN 3  generated by the XOR 1 s. Thus, a larger number of uniform random numbers URN 3 , URN 4  may be generated by a small number of uniform random number generators  10 ,  20 . 
       FIG.  9    illustrates an example of a random number generation device according to another embodiment. Elements similar to or the same as those of the above-described embodiments are denoted by the same reference signs and detailed description thereof is omitted. For example, a random number generation device  110  illustrated in  FIG.  9    is provided in the FPGA or the ASIC (not illustrated) of the calculation server  310  illustrated in  FIG.  2    or in the FPGA or the ASIC (not illustrated) of the calculation server  410  illustrated in  FIG.  3   . 
     The normal random number generation unit NGEN 3  has a configuration in which the cyclic shifters CSFT 1  are, similarly to those illustrated in  FIG.  7   , added to inputs of each of the XOR 1 s of the normal random number generation unit NGEN 3  illustrated in  FIG.  8   . According to the present embodiment, the effects similar to those of the embodiments illustrated in  FIGS.  7  and  8    may be obtained. 
     Regarding the embodiments illustrated in  FIGS.  1  to  9   , the following appendices are further disclosed. 
     Features and advantages of the embodiments will be apparent from the foregoing detailed description. The scope of claims is intended to cover the features and advantages of the embodiments as described above without departing from the spirit and scope of the claims. Any person skilled in the art may readily conceive of any improvements and changes. Accordingly, there is no intention to limit the scope of the inventive embodiments to those described above, and it is possible to rely on appropriate modifications and equivalents included in the scope disclosed in the embodiments. 
     All examples and conditional language provided herein are intended for the pedagogical purposes of aiding the reader in understanding the invention and the concepts contributed by the inventor to further the art, and are not to be construed as limitations to such specifically recited examples and conditions, nor does the organization of such examples in the specification relate to a showing of the superiority and inferiority of the invention. Although one or more embodiments of the present invention have been described in detail, it should be understood that the various changes, substitutions, and alterations could be made hereto without departing from the spirit and scope of the invention.