Patent Publication Number: US-8525329-B2

Title: Component stacking for integrated circuit electronic package

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     Under 35 USC §120, this application is a continuation application and claims the benefit of priority to U.S. patent application Ser. No. 12/015,122, filed Jan. 16, 2008, entitled “Component Stacking for Integrated Circuit Electronic Package,” which in turn is a continuation of and claims the benefit of priority to U.S. patent application Ser. No. 11/314,674, filed Dec. 20, 2005, entitled “Component tacking for Integrated Circuit Electronic Package,” and is related to co-pending patent application Ser. No. 11/315,409, filed Dec. 22, 2005, entitled “Method and System for Increasing Circuitry Interconnection and Component Capacity in a Multi-Component package,” all of which are incorporated herein by reference in their entirety. 
    
    
     FIELD OF THE INVENTION 
     The present invention relates to integrated circuit electronics packages, and more particularly to the layout and packing density of components in an integrated circuit electronics package. 
     BACKGROUND OF THE INVENTION 
     A multi-component electronic package or module for integrated circuits typically includes one or more integrated circuit devices and discrete passive and active components. For example, the integrated circuit devices can be in the form of integrated circuit dice which include terminals that contact conductive pads of the package circuits using bonding wires, solder flip-chip attach, or other structures. The discrete components can include passive devices such as resistors, capacitors, and inductors, as well as active components such as memory devices, crystals (e.g., for clock signals), radios, or other devices. The discrete components are included in the same package as the integrated circuit die or dice to provide a multi-function module, or in some cases a complete system in a package (SIP). 
     In some integrated circuit packages, multiple dice are included. In a typical configuration, the first die is attached to the package substrate, e.g., using epoxy polymer as adhesive and wirebonding for electrical connections, or, alternatively using flip-chip technology to contact the substrate. Additional dice, of similar or dissimilar size, are stacked on top of the first die and on top of each other to increase the packing density of the package. 
     The discrete components of the integrated circuit package, however, are positioned along the sides of the dice and are attached to conductive pads. The positioning of the discrete components around the perimeter of the dice leads to wider and longer packages. Thus, packing density is overall decreased, and the packages use a large amount of area to house the discrete components. Furthermore, additional contact pads must be added on the substrate around the die so that the discrete components may be electrically attached to the package circuits. 
     Accordingly, what is needed is a method and system for reducing the package density of integrated circuit packages that include discrete components. The present invention addresses such a need. 
     SUMMARY OF THE INVENTION 
     The invention of the present application relates to stacking components to increase packing density in integrated circuit packages. In one aspect of the invention, an integrated circuit package includes a substrate, and a plurality of discrete components connected to the substrate and approximately forming a component layer parallel to and aligned with a surface area of the substrate. An integrated circuit die is positioned adjacent to the component layer such that a face of the integrated circuit die is substantially parallel to the surface area of the substrate. The face of the integrated circuit die is aligned with at least a portion of the component layer, and terminals of the integrated circuit die are connected to the substrate. 
     In another aspect of the invention, a method for forming an integrated circuit package includes placing a plurality of discrete components on a surface area of a substrate to approximately form a component layer parallel to the surface area of the substrate. An integrated circuit die is placed on the component layer such that a face of the integrated circuit die is substantially parallel to the surface area of the substrate, and the face of the integrated circuit die is aligned with at least a portion of the component layer. Terminals of the integrated circuit die are connected to the substrate. 
     In another aspect of the invention, an integrated circuit package includes a substrate; a plurality of discrete components connected to a surface of the substrate, and an integrated circuit die positioned over at least a portion of the discrete components, where terminals of the integrated circuit die are connected to the substrate. 
     The present invention provides a packing configuration that increases the packing density of an integrated circuit electronics package. By placing an integrated circuit die over or adjacent to a discrete component layer in the package, surface area of the package is saved, allowing smaller integrated circuit packages to be produced. 
    
    
     
       BRIEF DESCRIPTION OF THE FIGURES 
         FIGS. 1A and 1B  are top plan and side elevation views, respectively, of a portion of an integrated circuit package  10  according to the present invention; 
         FIGS. 2A and 2B  are top plan and side elevation views of the integrated circuit package of  FIGS. 1A-1B , including an integrated circuit die; 
         FIG. 3  is a side elevation view of the package of  FIGS. 2A and 2B , with the addition of a protective encasing provided over the package; and 
         FIG. 4  is a flow diagram illustrating a method of the present invention for increasing the packing density of an integrated circuit package by stacking components. 
     
    
    
     DETAILED DESCRIPTION 
     The present invention relates to integrated circuit electronics packages, and more particularly to the layout and packing density of components in an integrated circuit electronics package. The following description is presented to enable one of ordinary skill in the art to make and use the invention and is provided in the context of a patent application and its requirements. Various modifications to the preferred embodiment and the generic principles and features described herein will be readily apparent to those skilled in the art. Thus, the present invention is not intended to be limited to the embodiment shown but is to be accorded the widest scope consistent with the principles and features described herein. 
     The present invention is mainly described in terms of particular systems provided in particular implementations. However, one of ordinary skill in the art will readily recognize that this method and system will operate effectively in other implementations. The present invention will also be described in the context of particular methods having certain steps. However, the method and system operate effectively for other methods having different and/or additional steps not inconsistent with the present invention. 
     To more particularly describe the features of the present invention, please refer to  FIGS. 1 through 4  in conjunction with the discussion below. 
       FIGS. 1A and 1B  are top plan and side elevation views, respectively, of a portion of an integrated circuit package  10  according to the present invention. Package  10  includes a substrate  12  and discrete components  14 . Substrate  12  is the base on which the integrated circuit package is constructed, and can be made of silicon, gallium arsenide, or other material. A row  13  of pads or conductive elements can be positioned near the outer perimeter of the substrate  12  which is to be used to connect to the leads or terminals of the integrated circuit (IC) die that is to be included in the package  10  (shown in  FIGS. 2A-2B ). 
     Discrete components  14  are included in package  10  to provide additional functionality and support for the IC  18  and/or the IC die  50 . The components  14  are coupled to the substrate  12  via connection pads or terminals (not shown) on the substrate, for example using standard solder connections, ball grid array connections, etc. The connection pads are formed as part of the electronic package interconnects substrate  12  and can be made of conductive metal, conductive epoxy, or other conductive material. The discrete components  14  together approximately form a kind of “component layer” on the substrate  12  that is parallel to and aligned with the surface area of the substrate over which the discrete components are positioned. 
     Discrete components  14  can include passive components, such as resistors  16 . In the example shown, surface-mount resistors  16  are provided, each resistor including two terminals  17  which are soldered to connection pads underneath the resistors. In other embodiments, other passive components can alternatively or additionally be used, such as capacitors, inductors, baluns, switches, filters, etc. 
     The discrete components  14  may also include active components, including such devices as integrated circuit devices. In the example of  FIG. 1A , the active components include a radio chip  18 , a crystal  20 , and an Electrically Erasable Read Only Memory (EEPROM) device  22 . Radio chip  18  can perform radio functions, such as transmission and/or reception of radio signals, and process those signals. Crystal  20  can generate a clock signal for use with other components and circuits of the package  10 , such as radio chip  18 . EEPROM  22  can be used as memory for the integrated circuit die(s) of the package, and/or for other components if appropriate. Other types of memory can also be provided in package  10  as discrete components, such as Random Access Memory (RAM), Read-Only Memory (ROM), flash memory, etc. The active discrete components can be attached to the conductive pads of the substrate  14  using ball grid connections  23 , as shown, or other types of connections, such as wirebonding and conductive epoxy terminal connections. 
     The discrete components  14  of the package  10  are arranged in the present invention so as to provide a stable platform for an integrated circuit die that is placed over the discrete components (shown in  FIGS. 2A-2B ). 
     In the described embodiment, the tallest of the discrete components are placed in the four corners of the substrate  12  in accordance with the dimensions of the integrated circuit die, and within the rows  13  of conductive pads. In the described example, the crystal  20  component is the tallest of the discrete components  14 . If, for example, the face or area of the integrated circuit die is smaller than the area of the component layer, then the four tallest components are placed in the corners of an area the size of the integrated circuit die, and that area can be positioned anywhere within the component layer area, e.g., at the center, in a corner, or at the side of the component layer (the attachment pads  13  of the substrate may have to be adjusted in position to be close to the edges of the die). If there are greater than four tallest discrete components, the additional tallest components can be placed in additional areas such as the center or edges of the area to be covered by the die. 
     If there are less than four tallest discrete components of the same height in the component layer, then dummy spacers  26  can be positioned on the substrate  12  in corners of the substrate  12  to make up the difference. This allows four level surfaces to be positioned to receive the integrated circuit die, and forms a stable surface platform for the die. For example, in the example of  FIG. 1A-1B , there is a single tallest component, crystal  20 , which has been placed in one corner of the substrate. Spacers  26  having the same height as the tallest component (crystal  20 ) are positioned in the other three corners. Spacers  26  can be made of any suitable material compatible with the package  10 , e.g., silicon, copper, polymer material, etc. In other embodiments, none of the components  14  of the component layer need be used as supports for the die  50 , and only spacers  26  can provide the support for the die  50 . 
     If there are more discrete components  14  in the package  10  than can fit underneath the integrated circuit die  50 , then the components  14  can extend out past one or more sides of the die. In such a case, conductive contacts for the additional discrete components can be placed on the substrate  12  outside the perimeter of the attachment pads  13  for the die  50 . 
     In an alternate embodiment, the tallest of the components  14  and spacers  26  can be positioned in other configurations that allow a stable base to be formed for the integrated circuit die. For example, the tallest components  14  and spacers  26  can be positioned at or near the mid-point along each edge of the substrate, forming a cross-shaped configuration of dimensions suitable to support all sides of the integrated circuit die  50 . Other stable configurations can also be used. The end result is to provide a stable bonding support during wiring bonding operation from die  50  to pads  13  on the substrate  12 . 
       FIGS. 2A and 2B  are top plan and side elevation views of the integrated circuit package  10  of  FIGS. 1A-1B , including an integrated circuit die  50 . Die  50  has been positioned over and stacked on the discrete components  14  of the component layer in a “tent”-like configuration, in which a planar face of the die  50  rests on the surfaces of the tallest discrete components  14  and spacers  26  that are positioned on the substrate  12  such that the face of the die is substantially parallel to the surface of the substrate  12 . The face of the integrated circuit die  50  is over or aligned with at least a portion of the component layer and the substrate surface area covered by the component layer. In the described embodiment, the die  50  covers most of the component layer, as shown. In other embodiments, the die may cover a smaller portion of the component layer, or the die may extend over parts of the surface area of the substrate that do not include discrete components. 
     Since the components and spacers all have substantially the same height, the die is provided with a stable platform that will not allow any substantial rocking or similar cantilever movement of the die. Such a stable position is important during the bonding of wires to the die connections. The die can be attached to the top surfaces of the tallest components and spacers using standard adhesives. Examples or adhesives are epoxies and acrylics, and they can be conductive or non-conductive. Solder bonding can also be used for this attachment, provided the joint interfaces are compatible for soldering). 
     After die  50  has been attached, the die is wirebond connected to the connection rows of pads  13  of the substrate using bond wires  52  to complete the package circuits. This is accomplished using a standard wirebonding process to connect the pads of die  50  to the pads of substrate  12 . For example, bonding wires of 1-mil diameter can be used, or wires of an appropriate diameter for the package. 
     The resulting package provides a much higher packing density than the packages of the prior art, resulting in a smaller used substrate surface area and a smaller package size overall. The placement of discrete components under the integrated circuit die  50  permits effective package size reduction. The overall height of the package may be slightly greater than previous types of packages due to the stacked configuration, but this is not generally of concern for the small dimensions involved. 
     In alternate embodiments, additional dice similar to die  50  can be stacked on the die  50  using any of various well-known standard stacking configurations for dice. 
     In still another alternate embodiment, the integrated circuit die  50  can first be placed and connected to the substrate (via wirebonding or a flip-chip configuration, for example). In one such embodiment, the discrete components can be connected to an interconnect substrate that is positioned on the die between the die and the discrete components. Such an embodiment is described in greater detail in co-pending patent application Ser. No. 11/315,409, filed Dec. 22, 2005, entitled, “Method and System for Increasing Circuitry Interconnection and Component Capacity in a Multi-Component Package,” which is incorporated herein by reference in its entirety. 
       FIG. 3  is a side elevation view of the package  10  of  FIGS. 2A and 2B , with the addition of a protective encasing  60  provided over the die  50 , wires  52 , and substrate  12 . The encasing  60  protects the delicate bond wires  52  from any external forces or interference. In one embodiment, the encasing  60  is an over-molded encasing that is formed using a standard encapsulation process, which fills in all the space surrounding the die  50  and wires  52  with a material such as an epoxy compound, and secures the bonding wires in place. In other embodiments, the encasing  60  can take other forms, e.g., a cap made of metal or other material that protects the die and wire connections. 
       FIG. 4  is a flow diagram illustrating a method  100  of the present invention for increasing the packing density of an integrated circuit package by stacking components. The method starts at  102 , and in step  104 , discrete components and spacers are connected to the substrate  12  and arranged to provide stable surfaces for the integrated circuit (IC) die  50 . As described above, this can include positioning the tallest discrete components in the corners or along the edges of the substrate, and providing spacers  26  of the same height at any corners or edges not filled by the tallest components. 
     In step  106 , the integrated circuit die is attached to the package by placing it over or adjacent to the discrete component layer, and attaching it to the surfaces of the tallest discrete components and spacers by an appropriate adhesive. After the die is placed and secured, the connection wires  52  are wirebonded between terminals of the die  50  and the connection pads of the substrate  12  to complete the package circuits. In some embodiments, other elements (components, layer, etc.) can be placed between the component layer and the die  50 , but such elements can be considered part of the component layer so that the die  50  is still considered “adjacent” to the component layer. 
     In step  108 , the enclosure  60  is added to the package  10  to protect and stabilize the connections of the fragile bonding wires as well as protect the integrated circuit and other components of the package. The method is then complete at  110 . 
     In alternative embodiments, the steps of  FIG. 4  can be performed in a different order. For example, if the integrated circuit die  50  is positioned underneath the component layer, then the die can first be placed on the substrate, followed by placing an interconnect substrate onto the die, and the discrete components on the interconnect substrate. An IC die can then be placed on top of the tallest discrete components and then wirebonded down to the substrate bond pads. 
     It should be noted that the present invention can be suitable for a variety of different package configurations, discrete components, and integrated circuits of a package. Any system-in-chip package designs including discrete components can benefit from the increased packing density of the present invention. 
     Although the present invention has been described in accordance with the embodiments shown, one of ordinary skill in the art will readily recognize that there could be variations to the embodiments and those variations would be within the spirit and scope of the present invention. Accordingly, many modifications may be made by one of ordinary skill in the art without departing from the spirit and scope of the appended claims.