Patent Publication Number: US-2002013016-A1

Title: Method for fabricating semiconductor device

Description:
BACKGROUND OF THE INVENTION  
       [0001] 1. Field of the Invention  
       [0002] The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a method for fabricating a semiconductor device which improves reliability of the semiconductor device.  
       [0003] 2. Background of the Related Art  
       [0004] Generally, with reduction of the size of a semiconductor device, the areas of the source/drain regions are reduced. In this case, it is necessary to thinly form a junction between the source and drain, causing a high resistance region to be formed.  
       [0005] To essentially reduce the resistance between the source/drain regions and a polysilicon region, a silicide process in which a metal silicide is formed at a junction area between the source/drain regions and the polysilicon region has been suggested. The silicide process, whereby the source/drain regions and a gate silicide region are formed at the same time, and a sidewall spacer is aligned with a gate terminal, is sometimes called a salicide process.  
       [0006] The related art method for fabricating a semiconductor device will be described with the accompanying drawings.  
       [0007]FIGS. 1 a  to  1   g  are sectional views showing fabricating process steps of the related art semiconductor device.  
       [0008] As shown in FIG. 1 a , a device isolation region  12  having a shallow trench isolation (STI) structure is formed in a field region of a semiconductor substrate  11  in which the field region and an active region are defined. The device isolation region  12  is formed by forming a trench having a predetermined depth in the field region of the semiconductor substrate  11  and filling a gap-fill material inside the trench. Subsequently, n-type and p-type impurity ions are selectively injected into the active region of the semiconductor substrate  11  to form an N-well  13  and a P-well  14  in the semiconductor substrate  11 .  
       [0009] As shown in FIG. 1 b , a gate insulating film  15  is formed on the semiconductor substrate  11 , and an undoped polysilicon layer  16  is formed on the gate insulating film  15 . The n-type impurity ions are injected into the polysilicon layer  16  above the P-well  14  using a first photoresist (not shown) as a mask. The first photoresist is then removed, and the p-type impurity ions are injected into the polysilicon layer  16  above the N-well  13  using a second photoresist (not shown) as a mask. Afterwards, rapid thermal annealing (RTA) is performed in the polysilicon layer  16  on which the n-type and p-type impurity ions are doped, so as to improve doping efficiency of the impurity ions doped on the polysilicon layer  16 .  
       [0010] As shown in FIG. 1 c , the polysilicon layer  16  is selectively removed by photolithography and etching processes to selectively form a gate electrode  16   a  over a part of the semiconductor substrate  11  having the N-well  13  and the P-well  14  formed thereon.  
       [0011] Subsequently, lightly doped p-type and n-type impurity ions are selectively injected into the semiconductor substrate  11  using the gate electrode  16   a  as a mask to form lightly doped drain (LDD) regions  17  within the surface of the semiconductor substrate  11  at both sides of the gate electrode  16   a . In other words, the lightly doped p-type impurity ions are injected into the N-well  13  while the lightly doped n-type impurity ions are injected into the P-well  14 , so that the LDD regions  17  are formed.  
       [0012] As shown in FIG. 1 d , an oxide film  18  and a nitride film  19  are sequentially formed on an entire surface of the semiconductor substrate  11  including the gate electrode  16   a.    
       [0013] As shown in FIG. 1 e , the nitride film  19  and the oxide film  18  are etched back to form a sidewall spacer  20  including the oxide film  18  and the nitride film  19  at both sides of the gate electrode  16   a . Meanwhile, an edge portion of the device isolation region  12  is removed by the etch-back process when forming the sidewall spacer  20 .  
       [0014] As shown in FIG. 1 f , the surface of the semiconductor substrate  11  is cleaned and then a selective epitaxial growth (SEG) process is performed on the surfaces of the exposed semiconductor substrate  11  and the gate electrode  16   a  to selectively form an epitaxial layer  21  having a thickness of 300˜500Å. Subsequently, heavily doped p-type and n-type impurity ions for the source and drain are injected into the semiconductor substrate  11  to form source/drain impurity regions  22 , which are connected with the LDD region  17 , within the surface of the semiconductor substrate  11 .  
       [0015] As shown in FIG. 1 g , the epitaxial layer  21  is reacted with the semiconductor substrate  11  and the gate electrode  16   a  by the salicide process to form a salicide layer  23 .  
       [0016] Reference numeral  24  denotes a portion where the volume of the epitaxial layer  21  has expanded during the above described salicide process.  
       [0017] When a deep submicron Complementary Metal-Oxide-Semiconductor (CMOS) device is fabricated, the length of the gate becomes short. Accordingly, in order to improve process margin, it is necessary to lower the height of the gate stack. If the height of the gate stack is high, a shadow effect occurs during ion implantation due to an adjacent gate, thereby deteriorating the characteristics of the device.  
       [0018] However, the aforementioned related art method for fabricating a semiconductor device has several problems. First, the distance between the gate electrode and the epitaxial layer  21  grown in a diffusion region becomes too close due to the SEG process being performed on a gate stack having a limited height, thus increasing the probability of bridging therebetween. Furthermore, the volume of the epitaxial layer  21  undesirably expands during the salicide process, thus causing electrical shorts between the gate electrode and the source/drain regions, which is especially problematic when line widths need to be narrow.  
       SUMMARY OF THE INVENTION  
       [0019] The present invention solves at least the above problems and/or disadvantages and provides at least the advantages described hereinafter.  
       [0020] Also, the present invention provides a method for fabricating a semiconductor device that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.  
       [0021] Furthermore, the present invention provides a method for fabricating a semiconductor device in which an SEG process is performed effectively and safely to prevent electrical shorting and bridging from occurring between the gate electrode and the source/drain regions.  
       [0022] Additional advantages and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following disclosure or may be learned from practice of the invention. The advantages of the invention may be realized and attained as particularly pointed out in the appended claims.  
       [0023] To achieve at least these and other advantages in whole or in part, and in accordance with purposes of the present invention, as embodied and broadly described, a method for fabricating a semiconductor device according to the present invention includes the steps of: forming a gate insulating film on a semiconductor substrate; sequentially forming a gate electrode and a gate cap insulating film on some region of the gate insulating film; forming a lightly doped impurity region inside a surface of the semiconductor substrate at both sides of the gate electrode; sequentially forming a first insulating film and a second insulating film on an entire surface of the semiconductor substrate including the gate cap insulating film and the gate electrode; selectively removing the second insulating film and the first insulating film to form a sidewall spacer at both sides of the gate cap insulating film and the gate electrode; removing the gate cap insulating film to expose a surface of the gate electrode; forming a semiconductor layer on the surfaces of the exposed gate electrode and the semiconductor substrate; forming a heavily doped impurity region, which is connected with the lightly doped impurity region, inside the surface of the semiconductor substrate at both sides of the gate electrode; and reacting the semiconductor substrate with the semiconductor layer and the gate electrode by salicide process to form a salicide layer.  
       [0024] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed. 
     
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
     [0025] The invention will be described in detail with reference to the following drawings in which like reference numerals refer to like elements wherein:  
     [0026]Figs. 1 a  to  1   g  are sectional views showing fabricating process steps of a related art semiconductor device; and  
     [0027]FIGS. 2 a  to  2   g  are sectional views showing fabricating process steps of a semiconductor device according to the present invention.  
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS  
     [0028] Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings.  
     [0029] As shown in FIG. 2 a , a device isolation region  32  having a shallow trench isolation (STI) structure is formed in a field region of a semiconductor substrate  31  in which the field region and an active region are defined. The device isolation region  32  is formed by forming a trench having a predetermined depth in the field region of the semiconductor substrate  31  and filling a gap-fill material inside the trench. Subsequently, n-type and p-type impurity ions are selectively injected into the active region of the semiconductor substrate  31  to form an N-well  33  and a P-well  34  inside a surface of the semiconductor substrate  31 .  
     [0030] As shown in FIG. 2 b , a gate insulating film  35  is formed on the semiconductor substrate  31 , and an undoped polysilicon layer  36  and a first insulating film  37  are sequentially formed on the gate insulating film  35 . The gate insulating film  35  is formed by oxidizing the semiconductor substrate  31  or being deposited on the semiconductor substrate  31  by chemical vapor deposition (DVD) process. The n-type impurity ions are injected into the polysilicon layer  36  on the P-well  34  using a first photoresist (not shown) as a mask. The first photoresist is then removed, and the p-type impurity ions are injected into the polysilicon layer  36  on the N-well  33  using a second photoresist (not shown) as a mask. Afterwards, rapid thermal annealing (RTA) is performed in the polysilicon layer  36  on which the n-type and p-type impurity ions are doped, so as to improve doping efficiency of the impurity ions doped on the polysilicon layer  36 . The first insulating film  37  is formed by depositing an oxide film having a thickness of 300˜500Å. A material having a dry-etching ratio three times higher than that of the device isolation region  32  is used as the first insulating film  37 .  
     [0031] As shown in FIG. 2 c , the first insulating film  37 , the polysilicon layer  36  and the gate insulating film  35  are selectively removed by photolithography and etching processes to form a gate cap insulating film  37   a  and a gate electrode  36   a  in some region of the semiconductor substrate  31  in which the N-well  33  and the P-well  34  are formed.  
     [0032] Subsequently, lightly doped p-type and n-type impurity ions are selectively injected into the semiconductor substrate  31  using the gate cap insulating film  37   a  and the gate electrode  36   a  as masks to form LDD regions  38  inside the surface of the semiconductor substrate  31  at both sides of the gate electrode  36   a . In other words, the lightly doped p-type impurity ions are injected into the N-well  33  while the lightly doped n-type impurity ions are injected into the P-well  34 , so that the LDD regions  38  are formed.  
     [0033] As shown in FIG. 2 d , a second insulating film  39  and a third insulating film  40  are sequentially formed on an entire surface of the semiconductor substrate  31  including the gate cap insulating film  37   a.    
     [0034] The second insulating film  39  can be formed of an oxide film while the third insulating film  40  can be formed of a nitride film. That is to say, the second insulating film  39  and the third insulating film  40  are formed of materials having different etching ratios.  
     [0035] As shown in FIG. 2 e , the third insulating film  40  and the second insulating film  39  are etched back to form a sidewall spacer  41  including the second insulating film  39  and the third insulating film  40  at both sides of the gate cap insulating film  37   a  and the gate electrode  36   a.    
     [0036] As shown in FIG. 2 f , the gate cap insulating film  37   a  is removed by wet-etching process. At this time, the second insulating film  39  constituting the sidewall spacer  41  is formed of the same oxide film as the gate cap insulating film  37   a . Accordingly, an upper surface and both sides of the second insulating film  39  are selectively removed to form an under cut shape.  
     [0037] Meanwhile, the surface of the semiconductor substrate  31  is cleaned by a washing process and at the same time the gate cap insulating film  37   a  is removed.  
     [0038] As shown in FIG. 2 g , the SEG process is performed on the surfaces of the exposed semiconductor substrate  31  and the gate electrode  36   a  to form an epitaxial layer having a thickness of 300˜500Å.  
     [0039] Subsequently, heavily doped p-type and n-type impurity ions for a source and a drain are injected into the semiconductor substrate  31  to form source/drain impurity regions  42 , which are connected with the LDD regions  38 , inside the surface of the semiconductor substrate  31 . In other words, the heavily doped p-type impurity ions are injected into the N-well  33  while the heavily doped n-type impurity ions are injected into the P-well  34 , so that the source/drain impurity regions  42  are formed.  
     [0040] Thereafter, the epitaxial layer is reacted with the semiconductor substrate  31  and the gate electrode  36   a  by the salicide process to form a salicide layer  43 .  
     [0041] In summary, according to the present invention, after the gate cap insulating film  37   a  is formed on the gate electrode  36   a , the sidewall spacer  41  including the second insulating film  39  and the third insulating film  40  is formed. The gate cap insulating film  37   a  is removed by wet-etching process using the third insulating film  40  of the sidewall spacer  41  as a mask and at the same time the surface of the semiconductor substrate is cleaned by washing process. Finally, the SEG process and the salicide process are sequentially performed on the semiconductor substrate  31  to form an electrode metal of low resistance.  
     [0042] The aforementioned method for fabricating a semiconductor device according to the present invention has the following advantages.  
     [0043] First, since the under cut shape is formed by selectively removing the upper surface and both sides of the second insulating film, bridging that may be caused during the SEG process is prevented from occurring between the gate and the diffusion region. That is, bridging between the diffusion region and the epitaxial layer grown on the diffusion region due to overflow of the epitaxial layer grown on the gate is prevented from occurring. Furthermore, it is possible to prevent electrical shorts between the gate and the source/drain regions due to expansion of the epitaxial layer during the salicide process.  
     [0044] The foregoing embodiments and advantages are merely exemplary and are not to be construed as limiting the present invention. The present teachings can be readily applied to other types of apparatuses. The description of the present invention is intended to be illustrative, and not to limit the scope of the claims. Many alternatives, modifications, and variations will be apparent to those skilled in the art.