Patent Publication Number: US-2023146733-A1

Title: Semi-Floating Gate Memory Device and Method for Fabricating the Same

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application claims the priority to Chinese Patent Application No. 202111319362.3, filed on Nov. 9, 2021, the disclosure of which is incorporated herein by reference in its entirety. 
     TECHNICAL FIELD 
     The present application relates to integrated circuit manufacturing technology, in particular to a semi-floating gate memory device and a method for fabricating the same. 
     BACKGROUND 
     With the continuous reduction of the size of the semiconductor device to 28 nm and below-28 nm process nodes, the thickness of the transistor gate dielectric layer SiON is reduced to less than 2 nm, resulting in the increase of leakage current of the transistor device. The semiconductor industry uses high-K (dielectric constant) dielectric material HfO 2  to replace SiON as the gate oxide layer to reduce the quantum tunneling effect of the gate dielectric layer, so as to effectively improve the transistor gate leakage current and the power consumption caused thereby. 
     The semi-floating gate memory device is an alternative concept of Dynamic Random Access Memory (DRAM), which is different from the usual 1T1C structure. The semi-floating gate memory device is composed of a floating gate transistor, an embedded tunneling transistor and a PN junction. The floating gate of the floating gate transistor is subjected to writing-in and erasing operations through the channel of the embedded tunneling transistor and the PN junction. Also, the oxide/polysilicon gate of the control gate is replaced with a high-K/metal gate to reduce the gate leakage. 
     The structure of an existing semi-floating gate memory device is as illustrated in  FIG.  1   . A semi-floating gate well region  101  of a second doping type is formed on a silicon substrate  100  of a first doping type. A U-shaped groove  102  connected to the silicon substrate  100  is formed in the semi-floating gate well region  101 . 
     A floating gate polysilicon layer  103  is filled into the U-shaped groove  102  and above the semi-floating gate well region  101  covering the periphery of the U-shaped groove  102 . 
     The floating gate polysilicon layer  103  filled into the U-shaped groove  102  is isolated from the semi-floating gate well region  101  by a floating gate dielectric layer  104 ; 
     The floating gate polysilicon layer  103  above the semi-floating gate well region  101  covering the periphery of the U-shaped groove  102  is isolated from an upper surface of the semi-floating gate well region  101  by a floating gate dielectric layer  104 , and is in connective contact with the semi-floating gate well region  101  through an opening in the floating gate dielectric layer  104  covering the upper surface of the semi-floating gate well region  101  on a left side of the U-shaped groove  102 . 
     The floating gate dielectric layer  104  and the floating gate polysilicon layer  103  jointly form a floating gate stack layer. 
     A control gate polysilicon  105  is located on the floating gate polysilicon layer  103  and downwards extends from a left side of the floating gate polysilicon layer  103  to the top of the semi-floating gate well region  101 . The control gate polysilicon  105  is isolated from the floating gate polysilicon layer  103  and the semi-floating gate well region  101  by a dielectric layer. 
     Spacer  106  is respectively formed on a left side of the downwards extending part of the control gate polysilicon  105 , the control gate polysilicon  105  and a right side of the floating gate polysilicon layer  103 . 
     Ions are implanted into the semi-floating gate well region  101  on the left side of the left spacer and the right side of the right spacer to respectively form a source region  107  and a drain region  108 . 
     For the existing semi-floating gate storage devices, source and drain ion implantation requires a separate mask, so the cost is high. 
     BRIEF SUMMARY 
     The technical problem to be solved by the present application is to provide a semi-floating gate transistor and a method for fabricating the same. It has an epitaxial growth structure, can save the mask required for source and drain ion implantation, and is low in fabrication cost. 
     In order to solve the technical problem, the present application provides a semi-floating gate memory device, a semi-floating gate well region  101  of a second doping type being formed on a silicon substrate  100  of a first doping type, the first doping type being P-type and the second doping type being N-type, or the first doping type being N-type and the second doping type being P-type, wherein 
     a U-shaped groove  102  connected to the silicon substrate  100  is formed in the semi-floating gate well region  101 ;   a floating gate polysilicon layer  103  of the first doping type is filled into the U-shaped groove  102  and above the semi-floating gate well region  101  covering the periphery of the U-shaped groove  102 ;   the floating gate polysilicon layer  103  filled into the U-shaped groove  102  is isolated from the semi-floating gate well region  101  by a floating gate dielectric layer  104 ;   the floating gate polysilicon layer  103  above the semi-floating gate well region  101  covering the periphery of the U-shaped groove  102  is isolated from an upper surface of the semi-floating gate well region  101  by a floating gate dielectric layer  104 , and is in connective contact with the semi-floating gate well region  101  through an opening in the floating gate dielectric layer  104  covering the upper surface of the semi-floating gate well region  101  on a left side of the U-shaped groove  102 ;   a control gate oxide layer  110  covers an upper surface of the floating gate polysilicon layer  103 ;   a control gate polysilicon layer  111  covers an upper surface of the control gate oxide layer  110 ;   a metal gate  113  is located on a left part of the control gate polysilicon layer  111  and downwards extends from a left side of the control gate polysilicon layer  111  to an upper part of the semi-floating gate well region  101 , and the metal gate  113  is isolated from the control gate polysilicon layer  111  and the semi-floating gate well region  101  by a high-K dielectric layer  112 ;   spacer  106  is formed on the left side of the downwards extending part of the metal gate  113 , the right side of the part of the metal gate  113  above the control gate polysilicon layer  111 , the right side of the control gate polysilicon layer  111  ,and the right side of the floating gate polysilicon layer  103 ;   a source region  107  and a drain region  108  are respectively formed through silicon epitaxial growth on the semi-floating gate well region  101  outside the left spacer of the metal gate  113  and the semi-floating gate well region  101  outside the right spacer of the control gate polysilicon layer  111 ;   a control gate epitaxial silicon layer  114  is formed through silicon epitaxial growth on the control gate polysilicon layer  111 .   

     Further, the control gate epitaxial silicon layer  114  is lower than an upper surface of the metal gate  113 . 
     Further, the width of the metal gate  113  downwards extending to the top of the semi-floating gate well region  101  is 1-100 nm; 
     the width of the metal gate  113  covering the control gate polysilicon layer  111  is 1-100 nm. 
     Further, the width of the control gate polysilicon layer  111  not covered by the metal gate  113  is 1-100 nm; 
     the regional width of the control gate epitaxial silicon layer  114  is 1-100 nm;   the width of the source region  107  and the drain region  108  formed through silicon epitaxial growth is 1-100 nm.   

     Further, the high-K gate dielectric layer  112  is one or a combination of any of ZrO 2 , ZrON, ZrSiON, HfZrO, HfZrON, HfON, HfO 2 , HfAlO, HfAlON, HfSiO, HfSiON, HfLaO and HfLaON; 
     the metal gate  113  is one or a combination of any of TiN, TaN, MoN, WN, TaC and TaCN. 
     In order to solve the technical problem, the present application provides a method for preparing a semi-floating gate memory device, which includes the following steps: 
     S1: forming a semi-floating gate well region  101  of a second doping type on a silicon substrate  100  of a first doping type, and etching the semi-floating gate well region  101  to form a U-shaped groove  102  connected to the silicon substrate  100 , the first doping type being P-type and the second doping type being N-type, or the first doping type being N-type and the second doping type being P-type;   S2: forming a floating gate dielectric layer  104  on a surface of the U-shaped groove  102  and an upper surface of the semi-floating gate well region  101 ;   S3: etching the floating gate dielectric layer  104 , forming an opening  105  connected to the semi-floating gate well region  101  on the floating gate dielectric layer  104  on a left side of the U-shaped groove  103 , and exposing a part of the semi-floating gate well region  101 ;   S4: depositing a floating gate polysilicon layer  103 , performing a first doping type ion implantation and performing annealing for activation;   S5: depositing a control gate oxide layer  110  and a control gate polysilicon layer  111  on the floating gate polysilicon  103 ;   S6: performing etching to remove a vertical stack layer of the control gate polysilicon layer  111 , the control gate oxide layer  110 , the floating gate polysilicon layer  103  and the floating gate dielectric layer  104  outside a first set distance on the left side of the opening, and stopping at the semi-floating gate well region  101 ;   S7: forming a high-K dielectric layer  112  on a wafer;   S8: depositing a metal gate  113  on the high-K dielectric layer  112 ;   S9: performing metal gate  113  chemical-mechanical polishing;   S10: performing etching to remove a vertical stack layer of the metal gate  113  and the high-K dielectric layer  112  outside a second set distance on the left side of the opening, and stopping at the semi-floating gate well region  101 , the second set distance being greater than the first set distance; and performing etching to remove a vertical stack layer of the metal gate  113  and the high-K dielectric layer  112  on a right side of a left part of the opening, and stopping at the control gate polysilicon layer  111 ;   S11: performing etching to remove a vertical stack layer of the control gate polysilicon layer  111 , the control gate oxide layer  110 , the floating gate polysilicon  103  and the floating gate dielectric layer  104  outside a third set distance on a right side of the U-shaped groove  102 , and stopping at the semi-floating gate well region  101  to form a complete polysilicon control gate;   S12: forming gate spacer  106 ;   S13: simultaneously performing silicon epitaxial growth on the control gate polysilicon layer  111 , the semi-floating gate well region  101  outside the left spacer of the metal gate  113  and the semi-floating gate well region  101  outside the right spacer of the control gate polysilicon layer  111  to respectively form a control gate epitaxial silicon layer  114 , a source region  107  and a drain region  108 .   

     Further, in step S9, when the metal gate  113  chemical-mechanical polishing is performed, the stopped metal gate  113  is higher than the high-K dielectric layer  112 . 
     Further, in step S9, when the metal gate  113  chemical-mechanical polishing is performed, the stopped metal gate  113  is 0.1 nm-50 nm higher than the high-K dielectric layer  112 . 
     Further, in step S10, the second set distance is 1-100 nm larger than the first set distance, that is, the width of the metal gate  113  downwards extending to the top of the semi-floating gate well region  101  is 1-100 nm. 
     Further, after etching is performed to remove a vertical stack layer of the metal gate  113  and the high-K dielectric layer  112  on a right side of a left part of the opening, the width of the metal gate  113  covering the control gate polysilicon layer  111  is 1-100 nm. 
     Further, in step S11, after etching is performed to remove a vertical stack layer of the control gate polysilicon layer  111 , the control gate oxide layer  110 , the floating gate polysilicon  103  and the floating gate dielectric layer  104  outside a third set distance on the right side of the U-shaped groove  102 , the width of the control gate polysilicon layer  111  not covered by the metal gate  113  is 1-100 nm. 
     Further, the high-K gate dielectric layer  112  is one or a combination of any of ZrO 2 , ZrON, ZrSiON, HfZrO, HfZrON, HfON, HfO 2 , HfAlO, HfAlON, HfSiO, HfSiON, HfLaO and HfLaON; 
     the metal gate  113  is one or a combination of any of TiN, TaN, MoN, WN, TaC and TaCN. 
     For the semi-floating gate memory device and the method for fabricating the same provided by the present application, the semi-floating gate memory device is a double control gate semi-floating gate memory device with a high-K/metal gate and a silicon oxide/polysilicon gate. A control gate epitaxial silicon layer  114 , a source region  107  and a drain region  108  are formed by an epitaxial growth structure, separate source and drain ion implantation is not needed, the mask required for source and drain ion implantation is saved, and the fabrication cost is low. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       In order to more clearly describe the technical solution of the present application, the following will briefly introduce the drawings needed in the present application. It is obvious that the drawings in the following description are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained according to these drawings without contributing any inventive labor. 
         FIG.  1    illustrates a schematic diagram of a structure of an existing semi-floating gate memory device. 
         FIG.  2    illustrates a schematic diagram after forming a semi-floating gate well region in a method for fabricating a semi-floating gate memory device according to an embodiment of the present application. 
         FIG.  3    illustrates a schematic diagram after forming a floating gate dielectric layer in a method for fabricating a semi-floating gate memory device according to an embodiment of the present application. 
         FIG.  4    illustrates a schematic diagram after etching a floating gate dielectric layer to expose part of a semi-floating gate well region in a method for fabricating a semi-floating gate memory device according to an embodiment of the present application. 
         FIG.  5    illustrates a schematic diagram after depositing a floating gate polysilicon layer in a method for fabricating a semi-floating gate memory device according to an embodiment of the present application. 
         FIG.  6    illustrates a schematic diagram after depositing a control gate oxide layer and a control gate polysilicon layer in a method for fabricating a semi-floating gate memory device according to an embodiment of the present application. 
         FIG.  7    illustrates a schematic diagram after performing etching to remove a vertical stack layer of a control gate polysilicon layer, a control gate oxide layer, a floating gate polysilicon layer and a floating gate dielectric layer in a method for fabricating a semi-floating gate memory device according to an embodiment of the present application. 
         FIG.  8    illustrates a schematic diagram after forming a high-K dielectric layer in a method for fabricating a semi-floating gate memory device according to an embodiment of the present application. 
         FIG.  9    illustrates a schematic diagram after depositing a metal gate in a method for fabricating a semi-floating gate memory device according to an embodiment of the present application. 
         FIG.  10    illustrates a schematic diagram after performing metal gate chemical-mechanical polishing in a method for fabricating a semi-floating gate memory device according to an embodiment of the present application. 
         FIG.  11    illustrates a schematic diagram after performing etching to remove a vertical stack layer of a metal gate and a high-K dielectric layer in a method for fabricating a semi-floating gate memory device according to an embodiment of the present application. 
         FIG.  12    illustrates a schematic diagram after forming a complete polysilicon control gate and spacer in a method for fabricating a semi-floating gate memory device according to an embodiment of the present application. 
         FIG.  13    illustrates a schematic diagram after performing silicon epitaxial growth to respectively form a control gate epitaxial silicon layer, a source region and a drain region in a method for fabricating a semi-floating gate memory device according to an embodiment of the present application. 
     
    
    
     DETAILED DESCRIPTION 
     The technical solution of the present application will be clearly and completely described below with reference to the drawings. Obviously, the described embodiments are part of the embodiments of the present application, instead of all of them. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without contributing any inventive labor still fall within the scope of protection of the present application. 
     Embodiment 1 
     A semi-floating gate memory device is provided. Referring to  FIG.  13   , a semi-floating gate well region  101  of a second doping type is formed on a silicon substrate  100  of a first doping type. The first doping type is P-type and the second doping type is N-type, or the first doping type is N-type and the second doping type is P-type. 
     A U-shaped groove  102  connected to the silicon substrate  100  is formed in the semi-floating gate well region  101 . 
     A floating gate polysilicon layer  103  of the first doping type is filled into the U-shaped groove  102  and above the semi-floating gate well region  101  covering the periphery of the U-shaped groove  102 . 
     The floating gate polysilicon layer  103  filled into the U-shaped groove  102  is isolated from the semi-floating gate well region  101  by a floating gate dielectric layer  104 . 
     The floating gate polysilicon layer  103  above the semi-floating gate well region  101  covering the periphery of the U-shaped groove  102  is isolated from an upper surface of the semi-floating gate well region  101  by a floating gate dielectric layer  104 , and is in connective contact with the semi-floating gate well region  101  through an opening in the floating gate dielectric layer  104  covering the upper surface of the semi-floating gate well region  101  on a left side of the U-shaped groove  102 . 
     A control gate oxide layer  110  covers an upper surface of the floating gate polysilicon layer  103 . 
     A control gate polysilicon layer  111  covers an upper surface of the control gate oxide layer  110 . 
     A metal gate  113  is located on a left part of the control gate polysilicon layer  111  and downwards extends from a left side of the control gate polysilicon layer  111  to the top of the semi-floating gate well region  101 , and the metal gate  113  is isolated from the control gate polysilicon layer  111  and the semi-floating gate well region  101  by a high-K dielectric layer  112 . 
     Spacer  106  is formed on the left side of the downwards extending part of the metal gate  113 , the right side of the part of the metal gate  113  above the control gate polysilicon layer  111 , the right side of the control gate polysilicon layer  111  ,and the right side of the floating gate polysilicon layer  103 . 
     A source region  107  and a drain region  108  are respectively formed through silicon epitaxial growth on the semi-floating gate well region  101  outside the left spacer of the metal gate  113  and the semi-floating gate well region  101  outside the right spacer of the control gate polysilicon layer  111 . 
     A control gate epitaxial silicon layer  114  is formed through silicon epitaxial growth on the control gate polysilicon layer  111 . 
     The semi-floating gate memory device according to embodiment 1 is a double control gate semi-floating gate memory device with a high-K/metal gate and a silicon oxide/polysilicon gate. A control gate epitaxial silicon layer  114 , a source region  107  and a drain region  108  are formed by an epitaxial growth structure, separate source and drain ion implantation is not needed, the mask required for source and drain ion implantation is saved, and the fabrication cost is low. 
     Embodiment 2 
     Based on the semi-floating gate memory device according to embodiment 1, the control gate epitaxial silicon layer  114  is lower than an upper surface of the metal gate  113 . 
     Further, the width of the metal gate  113  downwards extending to the top of the semi-floating gate well region  101  is 1-100 nm; 
     Further, the width of the metal gate  113  covering the control gate polysilicon layer  111  is 1-100 nm. 
     Further, the width of the control gate polysilicon layer  111  not covered by the metal gate  113  is 1-100 nm, the regional width of the control gate epitaxial silicon layer  114  is 1-100 nm, and the width of the source region  107  and the drain region  108  formed through silicon epitaxial growth is 1-100 nm, so that a conducting wire can be led out for control. 
     Further, the high-K gate dielectric layer  112  is one or a combination of any of ZrO 2 , ZrON, ZrSiON, HfZrO, HfZrON, HfON, HfO 2 , HfAlO, HfAlON, HfSiO, HfSiON, HfLaO and HfLaON. 
     Further, the metal gate  113  is one or a combination of any of TiN, TaN, MoN, WN, TaC and TaCN. 
     Embodiment 3 
     A method for fabricating the semi-floating gate memory device according to embodiment 1 or 2 is provided. The method fabricating the semi-floating gate memory device includes the following steps:
     S1: forming a semi-floating gate well region  101  of a second doping type on a silicon substrate  100  of a first doping type, and etching the semi-floating gate well region  101  to form a U-shaped groove  102  connected to the silicon substrate  100 , the first doping type being P-type and the second doping type being N-type, or the first doping type being N-type and the second doping type being P-type, as illustrated in  FIG.  2   ;   S2: forming a floating gate dielectric layer  104  on a surface of the U-shaped groove  102  and an upper surface of the semi-floating gate well region  101 , as illustrated in  FIG.  3   ;   S3: etching the floating gate dielectric layer  104 , forming an opening  105  connected to the semi-floating gate well region  101  on the floating gate dielectric layer  104  on a left side of the U-shaped groove  103 , and exposing a part of the semi-floating gate well region  101 , as illustrated in  FIG.  4   ;   S4: depositing a floating gate polysilicon layer  103 , performing a first doping type ion implantation and performing annealing for activation, as illustrated in  FIG.  5   ;   S5: depositing a control gate oxide layer  110  and a control gate polysilicon layer  111  on the floating gate polysilicon  103 , as illustrated in  FIG.  6   ;   S6: performing etching to remove a vertical stack layer of the control gate polysilicon layer  111 , the control gate oxide layer  110 , the floating gate polysilicon layer  103  and the floating gate dielectric layer  104  outside a first set distance on the left side of the opening, and stopping at the semi-floating gate well region  101 , as illustrated in  FIG.  7   ;   S7: forming a high-K dielectric layer  112  on a wafer, as illustrated in  FIG.  8   ;   S8: depositing a metal gate  113  on the high-K dielectric layer  112 , as illustrated in  FIG.  9   ;   S9: performing metal gate  113  Chemical-Mechanical Polishing (CMP), as illustrated in  FIG.  10   ;   S10: performing etching to remove a vertical stack layer of the metal gate  113  and the high-K dielectric layer  112  outside a second set distance on the left side of the opening, and stopping at the semi-floating gate well region  101 , the second set distance being greater than the first set distance; and performing etching to remove a vertical stack layer of the metal gate  113  and the high-K dielectric layer  112  on a right side of a left part of the opening, and stopping at the control gate polysilicon layer  111 , as illustrated in  FIG.  11   ;   S11: performing etching to remove a vertical stack layer of the control gate polysilicon layer  111 , the control gate oxide layer  110 , the floating gate polysilicon  103  and the floating gate dielectric layer  104  outside a third set distance on a right side of the U-shaped groove  102 , and stopping at the semi-floating gate well region  101  to form a complete polysilicon control gate;   S12: forming gate spacer  106 , as illustrated in  FIG.  12   ;   S13: simultaneously performing silicon epitaxial growth on the control gate polysilicon layer  111 , the semi-floating gate well region  101  outside the left spacer of the metal gate  113  and the semi-floating gate well region  101  outside the right spacer of the control gate polysilicon layer  111  to respectively form a control gate epitaxial silicon layer  114 , a source region  107  and a drain region  108 , as illustrated in  FIG.  13   .   

     The method for fabricating the semi-floating gate memory device according to embodiment 3 can be used to fabricate a double control gate semi-floating gate memory device with a high-K/metal gate and a silicon oxide/polysilicon gate. In the fabricated semi-floating gate memory device, a control gate epitaxial silicon layer  114 , a source region  107  and a drain region  108  are formed by an epitaxial growth structure, separate source and drain ion implantation is not needed, the mask required for source and drain ion implantation is saved, and the fabrication cost is low. 
     Embodiment 4 
     Based on the method for fabricating the semi-floating gate memory device according to embodiment 3, in step S9, when the metal gate  113  Chemical-Mechanical Polishing (CMP) is performed, the stopped metal gate  113  is higher than the high-K dielectric layer  112 . 
     Further, in step S9, when the metal gate  113  Chemical-Mechanical Polishing (CMP) is performed, the stopped metal gate  113  is 0.1 nm-50 nm higher than the high-K dielectric layer  112 . 
     Further, in step S10, the second set distance is 1-100 nm larger than the first set distance, that is, the width of the metal gate  113  downwards extending to the top of the semi-floating gate well region  101  is 1-100 nm. 
     After etching is performed to remove a vertical stack layer of the metal gate  113  and the high-K dielectric layer  112  on a right side of a left part of the opening, the width of the metal gate  113  covering the control gate polysilicon layer  111  is 1-100 nm. 
     Further, in step S11, after etching is performed to remove a vertical stack layer of the control gate polysilicon layer  111 , the control gate oxide layer  110 , the floating gate polysilicon  103  and the floating gate dielectric layer  104  outside a third set distance on the right side of the U-shaped groove  102 , the width of the control gate polysilicon layer  111  not covered by the metal gate  113  is 1-100 nm. 
     Further, the high-K gate dielectric layer  112  is one or a combination of any of ZrO 2 , ZrON, ZrSiON, HfZrO, HfZrON, HfON, HfO 2 , HfAlO, HfAlON, HfSiO, HfSiON, HfLaO and HfLaON; 
     The metal gate  113  is one or a combination of any of TiN, TaN, MoN, WN, TaC and TaCN. 
     What are described above are only preferred embodiments of the present application and are not used to limit the present application. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application should be included in the scope of protection of the present application.