Patent Publication Number: US-3969716-A

Title: Generation of dot matrix characters on a television display

Description:
This invention relates to the generation of dot matrix characters on a television display. This technique is well known and employs a decoding circuit adapted to create a pulse in each of the cells of a matrix of cells (dot matrix) required to build up the selected character. A commonly used matrix is the 7 × 5 matrix with 7 rows and 5 columns of cells, which are typically square, but need not be. 
     A defect of dot matrix characters is that, although vertical and horizontal strokes can be correctly drawn to the full width or height of a cell, diagonal parts of the characters have coarsely serrated edges and their mean width is only 1/2 times the mean width of the horizontal and vertical strokes (assuming the cells to be square), leading to a reduction in brightness of about 30%. This defect is visually noticeable. 
     It is known to remedy this defect by an interpolation procedure, wherein the corner-wise opposed quarters of the cells to either side of a diagonal portion are filled in. This procedure is feasible because each cell actually consists of segments of two scanning lines; a quarter cell is filled in by a pulse in one line only and of half the duration of a pulse corresponding to a complete segment, this duration being referred to as a dot period. Known interpolation procedures are restricted to sequentially scanned displays, such as are used in data display equipment. The object of this invention is to provide apparatus usable with an interlaced scan, thereby enabling improved dot matrix characters to be displayed on monitors or receivers operating to broadcast television standards. 
     According to the invention there is provided interpolation apparatus responsive to a line- interlaced video signal having first fields alternating with second fields and representing a dot matrix character in a matrix of cells, each composed of segments of two lines adjacent each other in the interlaced picture, to establish four signals of which three are delayed by one dot period, by one line period, and by one line period plus one dot period respectively relative to the fourth signal, a logic circuit responsive to the four signals to detect diagonal portions of the character, and means controlled by the logic circuit to add half-dot period pulses in lines of the first fields and in lines of the second fields delayed by a line period, so as to fill in cornerwise opposed quarters of the cells to either side of a diagonal portion in the display of the character represented by the first fields and the line delayed second fields. 
     As will appear subsequently, the line delay applied to the second fields enables the interpolation to be effected in both the first and second fields in real time referred to the said fourth signal. 
    
    
     Two embodiments of the invention will now be described, by way of example, with reference to the accompanying drawings, in which: 
     FIG. 1(a) shows a letter &#34;S&#34; in a 7 × 5 dot matrix; 
     FIG. 1(b) shows the same letter with odd lines delayed by one line period and with quarter cell interpolation components added to improve the display; 
     FIG. 2(a) shows a right diagonal (sloping upwardly to the right) during an even field; 
     FIG. 2(b) shows a right diagonal during an odd field; 
     FIG. 3(a) shows a left diagonal during an even field; 
     FIG. 3(b) shows a left diagonal during an odd field; 
     FIG. 4 is a block diagram of the first embodiment of the invention; and 
     FIG. 5 is a block diagram of the second embodiment. 
    
    
     In FIGS. 1(a) and (b), heavy lines outline the dot cells, divided horizontally by lighter lines into segments pertaining to A (even) and B (odd) fields respectively. FIG. 1 (b) demonstrates that, provided in the original signal (FIG. 1(a)) the B lines precede the A lines in each cell, i.e. are above the A lines, the character is not distorted if the B lines are delayed by one line; the character is merely displaced downwardly by half the line pitch in a field. 
     In FIG. 1(b) the quarter cells, shown shaded, are necessary to improve the representation of the diagonal portions. Quarter cells 10, for example, are corner-wise opposed at a right diagonal while quarter cells 11 are cornerwise opposed at a left diagonal. 
     A right diagonal of FIG. 1(b) is analysed more closely in FIGS. 2(a) and (b). Four cells defining the diagonal are labelled 1 to 4. The segments which appear are hatched and the quarter cells to be added are cross hatched. The relative delays are as follows: 
     Cell 1 : undelayed (the abovementioned &#34;fourth signal&#34;); 
     Cell 2 : delayed by dot period; 
     Cell 3 : delayed by line period; 
     Cell 4 : delayed by line period plus dot period. 
     It can also be seen that the following logical conditions define a right diagonal: 
     Cell 1 : pulse absent; 
     Cell 2 : pulse present; 
     Cell 3 : pulse present; 
     Cell 4 : pulse absent. 
     Similarly, from FIGS. 3(a) and (b) a left diagonal is defined by: 
     Cell 1 : pulse present; 
     Cell 2 : pulse absent; 
     Cell 3 : pulse absent; 
     Cell 4 : pulse present. 
     Also, from FIGS. 2(a) and (b), detection of a right diagonal requires the addition of a quarter cell in cell 1 (the real time cell) in an A field and in cell 4 in a B field. From FIGS. 3(a) and (b), detection of a left diagonal requires the addition of a quarter cell in cells 2 and 3. 
     One circuit complying with the above requirements is shown in FIG. 4. Lines 1 to 4 carry the signals for cells 1 to 4 as defined above and lines 1 to 4 carry these signals inverted, AND gates 15 and 16 detect the left and right diagonals respectively, in accordance with the foregoing logical conditions. Since the actions required in A and B fields differ, three changeover switches 12, 13 and 14 are employed and are switched synchronously at field frequency. 
     Consider first FIG. 2(a), field A of a right diagonal, requiring a quarter dot to be inserted in the first half segment of cell 1. In FIG. 4 this requirement is met by the output of gate 16 (right diagonal) enabling an AND gate 17 which passes a square-wave clock signal whose period equals the dot period and which is true during the first half of this period. The quarter dot pulse thereby created is added to the main signal by an OR gate 18. A one dot delay 19 is required in the main signal path, for a reason which will appear subsequently. Another one dot delay 20 between the switch 14 and the gate 17 compensates for the effect of the delay 19. 
     FIG. 2(b) shows that, in field B of a right diagonal, a quarter cell is to be added in the latter half of the segment of cell 4. This (FIG. 4) the output of gate 16 enables a gate 21 via switch 13 in field B and gate 21 passes the inverted clock signal (which is true in the latter half of a dot period). There is no delay between switch 13 and gate 21, but the switch 12 now selects the output of the one line delay 22 (signal 3) and the main signal at gate 18 has a total delay of one line period plus one dot period and the signal from gate 21 therefore puts the quarter dot in cell 4, as required. 
     Conditions for a left diagonal may be tabulated more summarily: 
     Field A, FIG. 3(a): Gate 15 enables gate 21 via switch 13, putting quarter dot in latter half of cell 2 because only delay 19 is effective in the main path. 
     Field B, FIG. 3(b): Gate 16 enables gate 17 via switch 14, putting quarter dot in first half of cell 3 because delays 22 and 19 are in the main path but delay 20 cancels the effect of delay 19. 
     It can be seen that, in field A, gates 15 and 16 command a quarter dot in the first and second halves of a segment respectively, whereas in field B, gates 15 and 16 command a quarter dot in the second and first halves respectively; hence the need for switches 13 and 14. These switches may be removed if switching is placed on the input side of the detector gates so that, in field A, gates 15 and 16 are respectively left and right diagonal detectors, whereas in field B, gates 15 and 16 are respectively right and left diagonal detectors. It turns out that this leads to a simplification in that the switch 12 and the delay 19 are no longer required. The circuit is shown in FIG. 5 with just two switches 23 and 24. It can be seen from the circuit that the inputs to the gates 15 and 16 are as follows: 
     Gate 15, field A : 1 2 3 4 = left diagonal; 
     Gate 15, field B : 1 2 3 4 = right diagonal 
     Gate 16, field A : 1 2 3 4 = right diagonal; 
     Gate 16, field B : 1 2 3 4 = left diagonal. 
     One of the one dot delays, delay 25, used (as in FIG. 4) in creating the inputs to the detector gates, and the corresponding switch 23, now also provide the function of switch 12 and delay 19 in FIG. 4.