Patent Publication Number: US-4546330-A

Title: Phase-locked loop circuit

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a phase-locked loop (PLL) circuit in which the cutoff frequency or time constant of a low-pass filter is switched in multi-steps. 
     2. Description of the Prior Art 
     A PLL circuit is often used in communication systems, computer systems, and the like. For example, in order to read digital data out of a magnetic disk, a clock signal is necessary. Generally, the clock signal is extracted from the read data itself, and a PLL circuit is used as a clock extracting circuit. 
     A conventional PLL circuit comprises a voltage-controlled-oscillator, a phase comparator, and a low-pass filter associated with a pump circuit. The characteristics of such a PLL circuit must be such that the PLL circuit does not change with rapid fluctuation, such as jitter, included in an input signal after the PLL circuit locks with the input signal, i.e., after the feedback nature of the PLL circuit causes the voltage-controlled oscillator to synchronize with the input signal. To make certain that the stability of the PLL circuit does not deteriorate, the cutoff frequency of the low-pass filter is made high during the lock-in mode so as to enhance the response time of the PLL circuit. The cutoff frequency of the low-pass filter is made low after the lock-in mode so as to reduce the response time of the PLL circuit. 
     In the prior art, however, in order to switch the cutoff frequency of the low-pass filter, a switching transistor is provided within the low-pass filter, and, as a result, the saturated voltage of the transistor is applied as noise to the control voltage of the voltage-controlled oscillator during the lock-in mode, thereby deteriorating the characteristics of the PLL circuit. 
     SUMMARY OF THE INVENTION 
     It is an object of the present invention to provide a PLL circuit in which the cutoff frequency of a low-pass filter can be switched without using a switching transistor. 
     According to the present invention, a low-pass filter is comprised of a capacitor and a plurality of resistors connected in series. In addition, a plurality of pump circuits, which are the same in number as the above-mentioned resistors, are connected thereto. By selecting one of the pump circuits, the cutoff frequency of the low-pass filter is switched in multi-steps. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention will be more clearly understood from the description set forth below, in which the present invention is contrasted with the prior art and reference is made to the accompanying drawings, wherein: 
     FIG. 1 is a block diagram of a general magnetic disk system; 
     FIG. 2 is a block diagram of a general PLL circuit; 
     FIG. 3 is a circuit diagram of the low-pass filter of FIG. 2; 
     FIG. 4 is a circuit diagram of a portion of a prior art PLL circuit; 
     FIGS. 5A and 5B are equivalent circuit diagrams of the portion of the PLL circuit of FIG. 4 during the fast response mode; 
     FIGS. 6A and 6B are equivalent circuit diagrams of the portion of the PLL circuit of FIG. 4 during the slow response mode; 
     FIG. 7 is a circuit diagram of a first embodiment of a portion of a PLL circuit according to the present invention; 
     FIGS. 8A and 8B are equivalent circuit diagrams of the portion of the PLL circuit of FIG. 7 during the fast response mode; 
     FIGS. 9A and 9B are equivalent circuit diagrams of the portion of the PLL circuit of FIG. 7 during the slow response mode; 
     FIG. 10 is a circuit diagram of a second embodiment of a portion of the PLL circuit according to the present invention; 
     FIG. 11 is a circuit diagram of a third embodiment of a portion of a PLL circuit according to the present invention; and 
     FIG. 12 is a circuit diagram of a fourth embodiment of a portion of a PLL circuit according to the present invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     In FIG. 1, which is a magnetic disk system, a read signal or an input signal IN from a magnetic head (not shown) is supplied to a PLL circiut 1, which generates a synchronizing clock signal or an output signal OUT. The output signal OUT is supplied to a synchronous field detector 2, which detects a synchronous field which is located before or after each piece of data. The synchronous field detector 2 generates a control signal FAST to switch the response time of the PLL circuit 1, depending on whether or not the PLL circuit 1 locks with the input signal IN. Note that the actual data is reproduced by the input signal IN and the output signal OUT at a subsequent circuit (not shown). The PLL circuit 1 will now be explained in more detail. 
     In FIG. 2, which is a general PLL circuit, reference numeral 11 designates a voltage-controlled oscillator in which the free-running frequency is set to N times the frequency of the input signal IN; 12 designates a frequency divider, i.e., a counter, which may be omitted, for dividing the output signal OUT of the voltage-controlled oscillator 11 into 1/N; and 13 designates a phase comparator for phase comparing the output signal of the frequency divider 12 with the input signal IN. That is, the phase comparator 13 generates a pump-up output U or a pump-down output D to a pump circuit 14, depending on whether the input signal IN leads or lags behind the output signal OUT of the frequency divider 12. The pump circuit 14 charges a low-pass filter 15 upon receipt of the pump-up output U of the phase comparator 13 and discharges the low-pass filter 15 upon receipt of the pump-down output D of the phase comparator 13. The oscillating frequency of the voltage-controlled oscillator 11 is controlled by the direct-current output of the low-pass filter 15. 
     The characteristics of the PLL circuit 1 must be such that the PLL circuit 1 does not change with rapid fluctuation, such as jitter, included in the input signal IN after a lock-in operation is performed so as to lock the frequency of the voltage-controlled oscillator 11 with the input signal IN from the magnetic head. To make certain that the stability of the PLL circuit does not deteriorate, generally, the cutoff frequency of the low-pass filter 15 is made high during the lock-in mode so as to enhance the response time of the PLL circuit. The cutoff frequency of the low-pass filter 15 is made low after the lock-in mode so as to reduce the response time of the PLL circuit 1. Thus, the cutoff frequency or time constant of the low-pass filter 15 is switched so that the PLL circuit 1 changes only with fluctuation of the rotational disk, not with fluctuation, such as jitter, included in the input signal IN. 
     In FIG. 2, if it is assumed that the entire gain of the phase comparator 13 and the pump circuit 14 is K.sub.φ (V/rad), the gain of the low-pass filter 15 is K F , the gain of the voltage-controlled oscillator 11 is K v  (rad/sec/V), the division ratio of the frequency divider 12 is N, the phase of the output signal OUT is θ 0  (s), the phase of the input signal IN is θ i  (s), and s is a Laplace operator, then ##EQU1## 
     If the low-pass filter 15 is a passive filter having a primary delay and consists of resistors R 0  and R 1  and a capacitor C as shown in FIG. 3, then the gain K F  of the low-pass filter 15 is represented by ##EQU2## Therefor, from the formulae (1) and (2), ##EQU3## In the formula (3), if it is assume that the denominator=0, then the characteristic equation is as follows: 
     
         0=s.sup.2 NC(R.sub.0 +R.sub.1)+(K.sub.φ ·K.sub.V ·C·R.sub.1 +N)+K.sub.φ ·K.sub.V (4) 
    
     This formula (4) can be replaced by 
     
         0=s.sup.2 +2ξ·ω.sub.n ·s+ω.sub.n.sup.2 
    
     where ##EQU4## Note that ω n  and ξ are called natural angular frequency and dumping factor, respectively. 
     According to the formulae (5) and (6), if the resistors R 0  and R 1  are variable, ω n  is small if (R 0  +R 1 ) is large. In addition, in order to stabilize the PLL circuit 1, ξ should be definite, and, accordingly, R 0  should be large if R 1  is large. 
     FIG. 4 is a portion of the PLL circuit in FIG. 2 in which the cutoff frequency of the low-pass filter 15 is switched in two steps. Two pump circuits 14F and 14S, for attaining a fast and a slow response time, respectively, are provided. The pump circuit 14S is comprised of an AND circuit G 41 , and NAND circuit G 42 , resistors R 41  and R 42 , and diodes D 41  and D 42 . The pump circuit 14F is comprised of an AND circuit G 43 , a NAND circuit G 44 , resistors R 43  and R 44 , and diodes D 43  and D 44 . Note that the AND circuits G 41  and G 43  and the NAND circuits G 42  and G 44  are open-collector type circuits. Further, the low-pass filter 15 is comprised of a capacitor C, two resistors R 1  and R 2 , and a transistor Q 1 . 
     A circuit formed by a resistor R 45 , a diode D 45 , and the transistor Q 1  is a means for determining whether or not the resistor R 2  is connected in parallel to the resistor R 1 , depending on the control signal FAST. That is, when the potential of the control signal FAST is high, the resistor R 2  is connected in parallel to the resistor R 1 , and, simultaneously, the pump circuit 14F is selected by the signal FAST. However, when the potential of the control signal FAST is low, the resistor R 2  is in a floating state, and, simultaneouly, the pump circuit 14S is selected by an inverter circuit G 45  which inverts the control signal FAST. Note that the resistor R 1  or the resistors R 1  and R 2  in combination correspond to the resistor R 1  of FIG. 3 while one of the resistors R 41  through R 44  corresponds to the resistor R 0  of FIG. 3. 
     FIGS. 5A and 5B are equivalent circuit diagrams of the portion of the PLL circuit of FIG. 4 in which the potential of the control signal FAST is high so as to turn on the transistor Q 1 . Particularly, FIG. 5B corresponds to a case where the potential of the pump-up output U is high. (If the potential of the pump-down output D is high, the resistor R 43  of FIG. 5B is replaced by the resistor R 44  of FIG. 5A.) On the other hand, FIGS. 6A and 6B are equivalent circuit diagrams of the portion of the PLL circuit of FIG. 4 in which the potential of the control signal FAST is low so as to cut off the transistor Q 1 . Particularly, FIG. 6B corresponds to a case where the potential of the pump-up output U is high. (If the potential of the pump-down output D is high, the resistor R 41  of FIG. 6B is replaced by the resistor R 42  of FIG. 6A.) Note that V CC  is the potential of a power supply and V F  is the forward voltage of one of the diodes D 41  through D 44 . 
     In the portion of the PLL circuit of FIG. 4, assume that R 41  =R 42 , R 43  =R 44 , and R 41  &gt;R 43 . Of course, R 1  &gt;R 1  R 2  /(R 1  +R 2 ). When the potential of the control signal FAST is high, ω n  is so large as to enable a rapid lock-in operation. In addition, since ξ can be suitably selected by the resistors R 2 , R 41  (=R 42 ), and R 43  (=R 44 ) and, accordingly, can be definite during the lock-in mode and after the lock-in mode, the stability of the PLL circuit 1 cannot deteriorate. 
     In the portion of the PLL circuit of FIG. 4, however, since the resistor R 2  is connected in parallel to the resistor R 1  or is disconnected therefrom by using the switching transistor Q 1 , there is a problem in that the saturated voltage of the transistor Q 1  is applied as noise to the control voltage of the voltage-controlled oscillator 11 during the lock-in mode, thereby deteriorating the lock-in characteristics of the PLL circuit 1. 
     According to the present invention, the cutoff frequency or time constant of the low-pass filter 15 is switched during the lock-in mode and after the lock-in mode, i.e., during the stationary mode, without using a switching transistor. 
     In FIG. 7, which is a first embodiment of the present invention, the resistor R 2  is connected in series to the resistor R 1 . The transistor Q 1 , the resistor R 45 , and the diode D 45  of FIG. 4 are not included. The pump circuit 14F is connected to the resistor R 1 , more precisely, to the connection point of the resistors R 1  and R 2 , while the pump circuit 14S is connected to the resistor R 2 . That is, there are the same number of pump circuits as there are resistors connected in series. 
     FIGS. 8A and 8B are equivalent circuit diagrams of the portion of the PLL circuit of FIG. 7 in which the potential of the control signal FAST is high. Particularly, FIG. 8B corresponds to a case where the potential of the pump-up output U is high. In this case, the pump circuit 14S is in an off state. In addition, the resistor R 2  is interposed between the resistor R 1  and the voltage-controlled oscillator 11. This resistor R 2 , however, can be disregarded since the input impedance of the voltage-controlled oscillator 11 is high, i.e., 50 to 100 KΩ, while the resistance value of the resistor R 2  is low, i.e., several hundred ohms(Ω). Also, in the PLL circuit of FIG. 8B, if the potential of the pump-down output D is high, the resistor R 43  is replaced by the resistor R 44  of FIG. 8A. 
     FIGS. 9A and 9B are equivalent circuit diagrams of the portion of the PLL circuit of FIG. 7 in which the potential of the control signal FAST is low. Particularly, FIG. 9B corresponds to a case where the potential of the pump-up output U is high. In this case, the pump circuit 14F is in an off state. In addition, the resistor R 2  is effectively connected in series with the resistor R 1 . 
     In FIGS. 8B and 9B, R 41  &gt;R 43  and R 1  &gt;R 1  +R 2 , and, accordingly, the cutoff frequency or time constant of the low-pass filter 15, including the pump circuits, can be switched in the same manner as in FIG. 4. In addition, the values ω n  and ξ can be selected as desired in a case where the control signal FAST is high or in a case where the control signal FAST is low. Therefore, the stability of the PLL 1 circuit never deteriorates. Further, since the cutoff frequency of the low-pass filter 15 is switched without using a switching transistor, the lock-in characteristics never deteriorate due to noise applied to the control voltage of the voltage-controlled oscillator during switching. 
     In FIG. 10, which is a second embodiment of the present invention, G 101 , G 102 , G 105  and G 106  are AND circuits; G 103 , G 104 , G 107  and G 108  are complementary metal-oxide semiconductor (CMOS) tri-state circuits; and R 101  through R 104  are resistors. That is, the NAND circuits G 42  and G 44  of FIG. 7 are replaced by the AND circuits G 102  and G 106 , respectively, and the diodes D 41  through D 44  of FIG. 7 are replaced by the tri-state circuits G 103 , G 104 , G 107  and G 108 , respectively. However, the circuits G 101  and G 105  and the resistors R 101  through R 104  correspond to the circuits G 41  and G 43  and the resistors R 41  through R 44 , respectively, of FIG. 7. 
     In the second embodiment illustrated in FIG. 10, as compared with the first embodiment illustrated in FIG. 7, since diodes having nonlinear resistance characteristics are unnecessary, the cutoff frequency of the low-pass filter 15 is accurate. Accordingly, the cutoff frequency, if the pump-up output U is high, (i.e., the charging time constant of the low-pass filter 15 is large) is the same as the cutoff frequency if the pump-down output D is high (i.e., the discharging time constant of the low-pass filter 15 is large) when R 101  =R 102  and R 103  =R 104 . This is helpful in stabilizing the lock-in operation of the PLL circuit 1. In addition, the entire device can be easily constructed with an integrated circuit. 
     In FIG. 11, which is a third embodiment of the present invention, the charging time constant is made the same as the discharging time constant by using the single resistor per each pump circuit. A pump circuit 14S&#34; for achieving a slow response comprises an OR circuit G 111 , an AND circuit G 112 , a CMOS tri-state circuit G 113 , and a resistor R 111 . A pump circuit 14 F&#34; for achieving a fast response comprises an OR circuit G 114 , an AND circuit G 115 , a CMOS tri-state circuit G 116 , and a resistor R 112 . 
     In the above-mentioned embodiments illustrated in FIGS. 7, 10, and 11, the time constant of the low-pass filter is switched in two steps. However, the time constant of the low-pass filter can be switched in more than three steps, thereby smoothly changing the time constant. In FIG. 12, a pump circuit 14S&#39;&#34;, which is the same as the pump circuits 14S&#34; and 14F&#34; of FIG. 11, is added to the PLL circuit, and a resistor R 3  is also added. Only one of the pump circuits 14F&#34;, 14S&#34;, and 14S&#39;&#34; is selected by selection signals PUMP 1  through PUMP 3 . By developing such a circuit configuration, it is possible to switch the time constant of the low-pass filter multi-steps, i.e., in more than four steps, thereby more smoothly changing the time constant. 
     As is explained above, according to the present invention, since the time constant of the low-pass filter in a PLL circuit is switched without using a switching transistor, the lock-in characteristics of the PLL circuit according to the present invention never deteriorate due to noise applied to the control voltage of the voltage-controlled oscillator during switching.