Patent Publication Number: US-9419095-B2

Title: Method for manufacturing dummy gate in gate-last process and dummy gate in gate-last process

Description:
CROSS-REFERENCE OF RELATED APPLICATIONS 
     This application is the U.S. national phase of International Application No. PCT/CN2012/086397, filed on Dec. 12, 2012 and titled “METHOD FOR MANUFACTURING DUMMY GATE IN GATE-LAST PROCESS AND DUMMY GATE IN GATE-LAST PROCESS”, which claimed priority to Chinese application No. 201210509428.X filed on Dec. 3, 2012, which is incorporated herein by reference in its entirety. 
     FIELD OF THE INVENTION 
     The present invention relates to the field of semiconductor technologies, and in particular to a method for manufacturing a dummy gate in a gate-last process as well as a dummy gate in a gate-last process. 
     BACKGROUND OF THE INVENTION 
     With the continuous development in IC (integrated circuit) manufacturing technology, the feature size of a MOSFET (metal-oxide-semiconductor field-effect transistor) continuously shrinks. In order to reduce parasitic capacitance on the gate electrode of a MOSFET and increase device speed, a gate stack structure that includes a high-K (high dielectric constant) gate dielectric layer and a metal gate electrode is introduced to the MOSFET. In order to prevent the metal material of the metal gate electrode from affecting the other structures of the transistor, the gate stack structure including a metal gate electrode and a high-K gate dielectric layer is generally manufactured by a gate-last process. 
     The gate-last process includes: providing a semiconductor substrate, on which a dummy gate structure and an etch stopping layer covering the dummy gate structure are provided; forming an interlayer dielectric layer on the surface of the etch stopping layer; performing CMP (chemical-mechanical polishing) on the interlayer dielectric layer and the etch stopping layer by using the surface of the dummy gate structure as a stopping layer; removing the dummy gate structure to form a trench; filling in the trench with metal by PVD (physical vapor deposition) or sputtering the metal from a target to the trench, to form a metal gate electrode layer; and polishing the metal gate electrode layer by CMP until the interlayer dielectric layer is exposed, thereby a metal gate is formed. 
     Accordingly, in the gate-last process, the manufacture of the dummy gate is crucial. However, currently, due to the limitations in physical mechanism, processing technology, manufacturing techniques, etc., the critical dimension of the dummy gate and the profile of the dummy gate cannot be accurately controlled at the 22 nm node and beyond, which degrades gate LER (Line Edge Roughness), device performance and device reliability. 
     SUMMARY OF THE INVENTION 
     In view of the above, an embodiment of the present disclosure provides a method for manufacturing a dummy gate in a gate-last process. The method includes: 
     providing a semiconductor substrate; 
     growing a gate oxide layer on the semiconductor substrate; 
     depositing bottom-layer amorphous silicon (α-Si) on the gate oxide layer; 
     depositing an oxide-nitride-oxide (ONO) structured hard mask on the bottom-layer α-Si; 
     depositing top-layer α-Si on the ONO structured hard mask; 
     depositing a hard mask layer on the top-layer α-Si; 
     forming photoresist lines on the hard mask layer, and trimming the formed photoresist lines so that the trimmed photoresist lines a width less than or equal to 22 nm; and 
     etching the hard mask layer, the top-layer α-Si, the ONO structured hard mask and the bottom-layer α-Si in accordance with the trimmed photoresist lines, and removing the hard mask layer and the top-layer α-Si. 
     Preferably, the etching the hard mask layer, the top-layer α-Si, the ONO structured hard mask and the bottom-layer α-Si in accordance with the trimmed photoresist lines, and removing the trimmed photoresist lines, the hard mask layer and the top-layer α-Si may include: 
     etching the hard mask layer by using the trimmed photoresist lines as a mask for the hard mask layer, and removing the photoresist lines; 
     etching the top-layer α-Si by using the hard mask layer as a mask for the top-layer α-Si; 
     etching the ONO structured hard mask by using the hard mask layer and the top-layer α-Si as a mask for the ONO structured hard mask, and removing the hard mask layer; and 
     etching the bottom-layer α-Si by using the top-layer α-Si and the ONO structured hard mask as a mask for the bottom-layer α-Si, and removing the top-layer α-Si. 
     Preferably, the depositing bottom-layer α-Si on the gate oxide layer may include: 
     depositing the bottom-layer α-Si on the gate oxide layer by low-pressure chemical vapor deposition (LPCVD). 
     Preferably, the bottom-layer α-Si may have a thickness ranging from 600 Å to 1200 Å. 
     Preferably, the depositing an ONO structured hard mask on the bottom-layer α-Si may include: 
     depositing a bottom oxide film on the bottom-layer α-Si by plasma-enhanced chemical vapor deposition (PECVD); 
     depositing a nitride film on the bottom oxide film by low-pressure chemical vapor deposition (LPCVD); and 
     depositing a top oxide film on the nitride film by atmospheric pressure chemical vapor deposition (APCVD). 
     Preferably, the bottom oxide film may have a thickness ranging from 80 Å to 120 Å, the nitride film may have a thickness ranging from 160 Å to 240 Å, and the top oxide film may have a thickness ranging from 500 Å to 800 Å. 
     Preferably, the depositing the top-layer α-Si and the hard mask layer on the ONO structured hard mask may include: 
     depositing the top-layer α-si on the ONO structured hard mask by low-pressure chemical vapor deposition (LPCVD); and 
     depositing the hard mask layer on the top-layer α-Si by plasma-enhanced chemical vapor deposition (PECVD). 
     Preferably, the top-layer α-Si may have a thickness ranging from 300 Å to 400 Å, and the hard mask layer may have a thickness ranging from 300 Å to 400 Å. 
     Another embodiment of the present disclosure provides a dummy gate in a gate-last process, including: a semiconductor substrate, a gate oxide layer on a surface of the semiconductor substrate, an amorphous silicon (α-Si) layer on a surface of the gate oxide layer, and an oxide-nitride-oxide (ONO) structured hard mask on the α-Si layer, wherein the α-Si layer and the ONO structured hard mask each have a width less than or equal to 22 nm. 
     Preferably, the ONO structured hard mask may include a bottom oxide film, a nitride film and a top oxide film. 
     According to the method for manufacturing a dummy gate in a gate-last process provided by an embodiment of the present disclosure, the ONO structured hard mask is deposited on the α-Si; then in the etching stage the photoresist lines are trimmed so that the width of the photoresist lines is less than or equal to 22 nm; and the ONO structured hard mask is etched in accordance with the width. By using this method, at the 22 nm node and beyond, the critical dimension of the dummy gate and the profile of the dummy gate can be accurately controlled, and the gate LER can be effectively improved, thereby ensuring device performance and device reliability. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The accompany drawings used in the description of the embodiments and the prior art are briefly described as follows, allowing a more detailed description of the technical solutions provided by the embodiments of the present disclosure and the prior art. Clearly, the accompany drawings described below are merely some of the embodiments of the present disclosure; for those skilled in the art, other drawings can be obtained based on these accompany drawings without inventive effort. 
         FIG. 1  is a flowchart illustrating a method for manufacturing a dummy gate in a gate-last process according to an embodiment of the present disclosure; and 
         FIG. 2-1  to  FIG. 2-10  are structural diagrams illustrating the stages in manufacturing a dummy gate in a gate-last process by using the method as shown in  FIG. 1  according to the embodiment of the present disclosure. 
     
    
    
     REFERENCE NUMERALS 
       20 —semiconductor substrate,  22 —gate oxide,  24 —bottom-layer α-Si,  26 —ONO structured hard mask,  28 —top-layer α-Si,  30 —hard mask layer,  32 —photoresist line;  261 —bottom oxide film,  262 —nitride film,  263 —top oxide film. 
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
     For a better understanding of the technical solutions of the application by those skilled in the art, the technical solutions provided by the embodiments of the present disclosure will be described hereinafter in conjunction with the accompany drawings. It is clear that the embodiments described herein are merely part of the embodiments of the present disclosure. Any other embodiment obtained by those skilled in the art based on the embodiments described herein without inventive effort falls within the scope of protection of the present disclosure. 
     An embodiment of the present disclosure provides a method for manufacturing a dummy gate in a gate-last process. The method includes: providing a semiconductor substrate; growing a gate oxide layer on the semiconductor substrate; depositing bottom-layer α-Si on the gate oxide layer; depositing an ONO structured hard mask on the bottom-layer α-Si; depositing top-layer α-Si on the ONO structured hard mask; depositing a hard mask layer on the top-layer α-Si; forming photoresist lines on the hard mask layer, and trimming the formed photoresist lines so that the trimmed photoresist lines has a width less than or equal to 22 nm; and etching the hard mask layer, the top-layer α-Si, the ONO structured hard mask and the bottom-layer α-Si in accordance with the trimmed photoresist lines, and removing the photoresist lines, the hard mask layer and the top-layer α-Si. 
     In the method above for manufacturing a dummy gate in a gate-last process, the ONO structured hard mask is deposited on the α-Si; then in the etching stage the photoresist lines are trimmed so that the width of the photoresist lines is less than or equal to 22 nm; and the ONO structured hard mask is etched in accordance with the width. By using this method, at the 22 nm node and beyond, the critical dimension of the dummy gate and the profile of the dummy gate can be accurately controlled, and the gate LER can be effectively improved, thereby ensuring device performance and device reliability. 
     The above objects, features and advantages of the present disclosure will become more apparent when read in conjunction with the accompanying drawings and the following description of the embodiments of the present disclosure. In the detailed description of the embodiments of the present disclosure, for illustrative purposes, the section views illustrating the structure of a device are not drawn to scale. Moreover, the drawings are merely exemplary, and shall not be interpreted as limiting the scope of protection of the present disclosure. Furthermore, in an actual manufacture process, the three dimensions including length, width and depth should be included. 
       FIG. 1  is a flowchart illustrating a method for manufacturing a dummy gate in a gate-last process according to an embodiment, and  FIG. 2-1  to  FIG. 2-10  are structural diagrams illustrating the stages in manufacturing a dummy gate in a gate-last process by using the method as shown in  FIG. 1  according to the embodiment of the present disclosure. 
     As shown in  FIG. 1 , the method for manufacturing a dummy gate in a gate-last process includes the following steps. 
     Step S 1 : providing a semiconductor substrate  20 . 
     In this step, the substrate  20  may be of any semiconductor material, e.g., monocrystalline silicon, polycrystalline silicon, amorphous silicon, germanium, silicon-germanium (SiGe), silicon carbide, indium antimonide (InSb), lead telluride (PbTe), indium arsenide (InAs), indium phosphide (InP), gallium arsenide (GaAs) or gallium antimonide (GaSb), an alloy semiconductor, or some other compound semiconductor material. Moreover, the substrate may have a stack structure, e.g., Si/SiGe, silicon on insulator (SOI), or silicon-germanium on insulator (SGOI). In addition, the substrate may be a fin-type device, a normal planar CMOS device, a nanowire device or the like. In the embodiment of the present disclosure, as an example, the material of the substrate  20  is Si. It is noted that this is for illustrative purposes only, and the present disclosure is note limited to this specific example. 
     Step S 2 : growing a gate oxide layer  22  on the semiconductor substrate, and depositing bottom-layer α-Si  24  on the grown gate oxide layer. 
     In this step, a thermal oxidation process may be used for growing the gate oxide layer  22  on the semiconductor substrate  20 . Specifically, the thermal oxidation process may be a conventional thermal oxidation process performed in a furnace, an in-situ steam generation (ISSG) process, or a rapid thermal oxidation (RTO) process. The material of the gate oxide layer  22  may be silicon oxide, silicon oxynitride or the like. In addition, the material of the gate oxide layer  22  may also be some other material known by those skilled in the art. The thickness of the gate oxide layer  22  may range from 8 Angstroms (Å) to 40 Å. 
     Then, the bottom-layer α-Si  24  is deposited on the grown gate oxide layer  22 . This may be implemented with a chemical vapor deposition (CVD) process, e.g., LPCVD, APCVD, PECVD, or high-density plasma chemical vapor deposition (HDPCVD). The thickness of the deposited bottom-layer α-Si  24  may range from 600 Å to 1200 Å. 
     Step S 3 : depositing an ONO structured hard mask  26  on the deposited bottom-layer α-Si  24 . 
     In this step, the depositing the ONO structured hard mask  26  may include: depositing a bottom oxide film  261 , a nitride film  262  and a top oxide film  263  sequentially on the bottom-layer α-Si  24 . In the embodiment, the bottom oxide film  261  may be deposited by a PECVD process; the nitride film  262  may be deposited by an LPCVD process or a PECVD process; the top oxide film  263  may be deposited by an APCVD process, an LPCVD process or a PECVD process. Furthermore, the materials of the bottom oxide film  261  and the top oxide film  263  may be silicon oxide, and the thickness of the bottom oxide film  261  may range from 80 Å to 120 Å and the thickness of the top oxide film  263  may range from 500 Å to 800 Å. The material of the nitride film  262  may be silicon nitride, and its thickness may range from 160 Å to 240 Å. 
     Step S 4 : depositing top-layer α-Si  28  and a hard mask layer  30  on the ONO structured hard mask  26 . 
     In this step, the top-layer α-Si  28  may be deposited by a CVD process, an APCVD process, a PECVD process, an HDPCVD process or the like. The thickness of the deposited top-layer α-Si  28  may range from 300 Å to 400 Å. 
     Then, the hard mask layer  30  is deposited on the top-layer α-Si  28 . In the embodiment, the hard mask layer  30  may be an oxide film, and may be deposited by a PECVD process. The thickness of the hard mask layer  30  may range from 300 Å to 400 Å. 
     Step S 5 : forming photoresist lines  32  on the hard mask layer  30 . 
     In this step, the photoresist lines  32  may be formed by immersion lithography or electron beam direct writing. The present disclosure is not limited to these specific examples. Furthermore, the embodiment imposes no limitation on the width of the formed photoresist lines  32 . 
     Step S 6 : trimming the formed photeresist line  32 . 
     In this step, in order to form a dummy gate in a gate-last process having a width of 22 nm or less, the formed photoresist lines  32  are trimmed so that the width of the photoresist lines  32  is less than or equal to 22 nm. In the embodiment, the formed photoresist lines  32  may be trimmed in situ by using oxygen plasma. Specifically, oxygen gas is fed into a dry etch apparatus such as a reactive-ion etching (RIE) apparatus, and a radio-frequency power supply is applied to the etching apparatus, so that oxygen plasma is formed, and the photoresist lines  32  are trimmed by using the oxygen plasma. 
     Step S 7 : etching the hard mask layer  30 . 
     In this step, the hard mask layer  30  may be etched by a dry etching method using the formed photoresist lines  32  used as a mask. For example, the hard mask layer  30  may be etched by a RIE process. 
     Step S 8 : removing the photoresist lines  32 . 
     In this step, a dry photoresist-removing method may be used. For example, the photoresist lines  32  may be removed by using oxygen plasma. Specifically, the photoresist lines  32  may be removed by oxygen plasma filled in a plasma etch chamber. In order to completely remove the photoresist lines  32  and a polymer generated in the etching of the hard mask layer  30 , a method incorporating dry photoresist-removing and wet dry photoresist-removing may be used in this step. 
     Step S 9 : etching the top-layer α-Si  28 . 
     In this step, the top-layer α-Si  28  is etched by using the hard mask layer  30  as a mask for the top-layer α-Si  28 . In the embodiment, the top-layer α-Si  28  may be etched by a RIE process or the like, and the present disclosure is not limited to the specific example. 
     Step S 10 : etching the ONO structured hard mask  26 . 
     In this step, the ONO structured hard mask  26  is etched by using the hard mask layer  30  and the top-layer α-Si  28  as a mask. In the embodiment, the ONO structured hard mask  26  may be etched by a RIE process. Moreover, the hard mask layer  30  may be removed after the etching of the ONO structured hard mask  26 , which simplifies subsequent processes. 
     Step S 11 : etching the bottom-layer α-Si  24 . 
     In this step, the bottom-layer α-Si  24  is etched by using the top-layer α-Si  28  and the ONO structured hard mask  26  as a mask. In the embodiment, the bottom-layer α-Si  24  may be etched by a RIE process. Moreover, the top-layer α-Si  28  may be removed directly after the etching of the bottom-layer α-Si  24 . 
     Thus, a dummy gate in a gate-last process having a line width of 22 nm is manufactured. 
     In the method for manufacturing a dummy gate in a gate-last process provided by the embodiment of the present disclosure, the ONO structured hard mask is deposited on the α-Si; then in the etching stage the photoresist lines are trimmed so that the width of the photoresist lines is less than or equal to 22 nm; and the ONO structured hard mask is etched in accordance with the width. By using this method, at the 22 nm node and beyond, the critical dimension of the dummy gate and the profile of the dummy gate can be accurately controlled, and the gate LER can be effectively improved, thereby ensuring device performance and device reliability. 
     Another embodiment of the present disclosure provides a dummy gate structure formed by the method described above. As shown in  FIG. 2-10 , a section view of the structure of the dummy gate according to the embodiment of the present disclosure, the dummy gate structure includes: a semiconductor substrate  20 , a gate oxide layer  22  on a surface of the semiconductor substrate, an α-Si layer  24  on a surface of the gate oxide layer  22 , and an ONO structured hard mask  26  on the α-Si layer  24 . The widths of the α-Si layer  24  and the ONO structured hard mask  26  are less than or equal to 22 nm. 
     The ONO structured hard mask  26  includes: a bottom oxide film  261 , a nitride film  262  and a top oxide film  263 . The materials of the bottom oxide film  261  and the top oxide film  263  may be silicon oxide. The thicknesses of the bottom oxide film  261  may range from 80 Å to 120 Å, and the thickness of the top oxide film  263  may range from 500 Å to 800 Å. The material of the nitride film  262  may be silicon nitride, and its thickness may range from 160 Å to 240 Å. 
     The description of the embodiments disclosed herein enables those skilled in the art to implement or use the present invention. Various modifications to the embodiments may be apparent to those skilled in the art, and the general principle defined herein can be implemented in other embodiments without deviation from the scope of the present invention. Therefore, the present invention shall not be limited to the embodiments described herein, but in accordance with the widest scope consistent with the principle and novel features disclosed herein.