Patent Publication Number: US-6664588-B2

Title: NROM cell with self-aligned programming and erasure areas

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is a continuation application of U.S. Ser. No. 09/413,408, filed Oct. 6, 1999, now issued as U.S. Pat. No. 6,348,711, which is a continuation-in-part application of U.S. Ser. No. 09/082,280, filed on May 20, 1998, and now issued as U.S. Pat. No. 6,215,148. 
    
    
     FIELD OF THE INVENTION 
     The present invention relates to FLASH, electrically erasable, programmable read only memory (EEPROM) and nitride, programmable read only memory (NROM) cells in general. 
     BACKGROUND OF THE INVENTION 
     Dual bit cells are known in the art although they are not common. Some dual bit cells have multiple threshold voltage levels, where every two threshold voltage levels together store a different bit. Others store one bit on either side of the cell. A dual bit cell of the latter kind, known as nitride, programmable read only memory (NROM) cell, is disclosed in U.S. Pat. No. 6,011,725, assigned to the common assignee of the present invention. The disclosure of the above-identified patent is incorporated herein by reference. 
     FIGS. 1A,  1 B and  1 C, to which reference is now made, schematically illustrate the dual bit NROM cell. The cell has a single channel  100  between two bit lines  102  and  104  but two separated and separately chargeable areas  106  and  108 . Each area defines one bit. For the dual bit cell of FIGS. 1, the separately chargeable areas  106  and  108  are found within a nitride layer  110  formed in an oxide-nitride-oxide sandwich (layers  109 ,  110  and  111 ) underneath a polysilicon layer  112 . 
     To read the left bit, stored in area  106 , right bit line  104  is the drain and left bit line  102  is the source. This is known as the “read through” direction, to indicated by arrow  113 . To read the right bit, stored in area  108 , the cell is read in the opposite direction, indicated by arrow  114 . Thus, left bit line  102  is the drain and right bit line  104  is the source. 
     FIG. 1B generally indicates what occurs within the cell during reading of the left bit of area  106 . An analogous operation occurs when reading the right bit of area  108 . 
     To read the left bit in area  106 , the left bit line  102  receives the source voltage level V s , typically of 0V, and the right bit line  104  receives the drain voltage V d , typically of 2V. The gate receives a relatively low voltage V g , which typically is a low voltage of 3V. 
     The presence of the gate and drain voltages V g  and V d , respectively, induce a depletion layer  54  and an inversion layer  52  in the center of channel  100  The drain voltage V d  is large enough to induce a depletion region  55  near drain  104  which extends to the depletion layer  54  of channel  100 . This is known as “barrier lowering” and it causes “punch-through” of electrons from the inversion layer  52  to the drain  104 . The punch-through current is only minimally controlled by the presence of charge in right area  108  and thus, the left bit can be read irrespective of the presence or absence of charge in right area  108 . 
     Since area  106  is near left bit line  102  which, for this case, acts as the source (i.e. low voltage level), the charge state of area  106  will determine whether or not the inversion layer  52  is extended to the source  102 . If electrons are trapped in left area  106 , then the voltage thereacross will not be sufficient to extend inversion layer  52  to the source  102  and a “0” will be read. The opposite is true if area  106  has no charge. 
     Like floating gate cells, the cell of FIGS. 1A and 1B is erasable and programmable. Thus, the amount of charge stored in areas  106  and  108  can be controlled by the user. 
     For NROM cells, each bit is programmed in the direction opposite that of its reading direction. Thus, to program left bit in area  106 , left bit line  102  receives the high programming voltage (i.e. is the drain) and right bit line  104  is grounded (i.e. is the source). This is shown in FIG.  1 C. The opposite is true for programming area  108 . 
     The high programming voltage pulls electrons from the source  104 . As the electrons speed up toward the drain  102 , they eventually achieve enough energy to “jump” into the nitride layer  110 . This is known as “hot electron injection” and it only occurs in the area close to the drain  102 . When the drain voltage is no longer present, the oxide layer  109  prevents the electrons from moving back into the channel  100 . 
     The bits are erased in the same directions that they are programmed. However, for erasure, a negative erasure voltage is provided to the gate  112  and a positive voltage is provided to the bit line which is to be the drain. Thus, to erase the charge in left area  106 , the erase voltage is provided to left bit line  102 . The highly negative erase voltage creates an electric field in the area near the left bit line  102  which pulls the electrons stored in the area close to the drain. However, the electric field is strong only close to the drain and thus, the charge in right area  108  is not depleted. 
     Typically, programming and erasure are performed with pulses of voltage on the drain and on the gate. After each pulse, a verify operation occurs in which the threshold voltage level of the cell (i.e. the gate voltage level at which the cell becomes conductive) is measured. During programming, the threshold voltage level Vtp is steadily increased so that the cell will not pass any significant current during a read operation. During erasure, the opposite is true; the threshold voltage level Vte is decreased until a significant current is present in the cell during reading. 
     Unfortunately, multiple erase and programming cycles change the number of pulses needed to achieve the desired threshold voltage levels. For the pulses, either the voltage level can remain constant and the number of pulses can be increased or the voltage level can be increased until the desired threshold voltage level is achieved. 
     The cell will no longer be considered functional once the gate voltage required for erasure is too negative and/or the number of programming pulses is reduced to one. 
     FIGS. 2A,  2 B and  2 C present experimental results of multiple programming and erase cycles, on log-linear charts. In this experiment, the gate voltage level for erasure was increased, as necessary, and the cell ceased to function after 20,000 cycles. 
     FIG. 2A graphs the programming and erase threshold voltage levels for both bits. Curves  60  and  62  illustrate the programming threshold voltage levels for the left and right bits, respectively, where the threshold voltage level for the right bit is measured in the forward (and not the reverse) direction. Curves  64  and  66  illustrate the erase threshold voltage levels for the left and right bits, respectively. It is noted that all curves remain relatively constant until about 2000 cycles at which point the threshold voltage levels increase. It is also noted that the programming threshold voltage level for the left bit, read in the reverse direction, is significantly higher than that for the right bit. However, the erase threshold voltage levels of each bit are smaller than their programming threshold voltage levels. 
     FIG. 2B illustrates the read current Ir after programming (curve  70 ) and after erasure (curve  72 ). Both currents decrease strongly after about 4000 cycles. 
     FIG. 2C illustrates the number of programming pulses (curve  74 ) and the gate voltage during erasure (curve  76 ). The number of programming pulses drops to one and the gate voltage drops from −6V to −9V after about 3000 cycles. 
     SUMMARY OF THE INVENTION 
     An object of the present invention is to provide an improved NROM cell which can endure an increased number of programming and erase cycles. 
     There is therefore provided, in accordance with a preferred embodiment of the present invention, an NROM cell which has an oxide-nitride-oxide layer over at least a channel and a pocket implant self-aligned to at least one bit line junction. The cell also includes at least one area of hot electron injection within the ONO layer and over the pocket implant and at least one area of hot hole injection generally self-aligned to the area of hot electron injection. 
     Additionally, in accordance with a preferred embodiment of the present invention, the pocket implant can be a single or a double pocket implant. 
     There is also provided, in accordance with a preferred embodiment of the present invention, a method of erasing an NROM cell. The cell includes a channel, two diffusion areas on either side of the channel, each diffusion area having a junction with the channel, an oxide-nitride-oxide (ONO) layer at least over the channel, a pocket implant self-aligned to at least one of the junctions and at least one area of hot electron injection within the ONO layer and over the pocket implant. The method comprising the steps of generating holes at the intersection of one of the junctions, its neighboring pocket implant and a portion of the ONO layer near the junction, accelerating the holes along the surface of the channel and injecting the holes close to the area of electron injection. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention will be understood and appreciated more fully from the following detailed description taken in conjunction with the appended drawings in which: 
     FIGS. 1A,  1 B and  1 C are schematic illustrations of the operation of a prior art dual bit, nitride programmable read only memory (NROM) cell; 
     FIGS. 2A,  2 B and  2 C are graphical illustrations of experimental results of multiple programming and erase cycles, on log-linear charts; 
     FIGS. 3A and 3B are schematic illustrations of the state of the NROM cell of the prior art after the first cycle of programming and erasure, respectively; 
     FIGS. 3C and 3D are schematic illustrations of the state of the NROM cell of the prior art after the 20,000 th  cycle of programming and erasure, respectively; 
     FIGS. 4A and 4B are schematic illustrations of two alternative embodiments of an NROM cell, constructed and operative in accordance with a preferred embodiment of the present invention, wherein the cell of FIG. 4A has single pocket implants and the cell of FIG. 4B has double pocket implants; 
     FIGS. 5A and 5B are graphical illustrations of the lateral channel field and the channel potential for the cells of FIGS. 4A and 4B; 
     FIG. 6 is a graphical illustration of the general shape of the threshold voltage level for the cells of FIGS. 4A and 4B; 
     FIGS. 7A,  7 B,  7 C,  7 D,  7 E and  7 F are schematic illustrations of the manufacturing process for a row of NROM cells of the present invention; 
     FIGS. 8A and 8B are schematic illustrations of two single bit embodiments of an NROM cell, constructed and operative in accordance with a second preferred embodiment of the present invention, wherein the cell of FIG. 8A has a single pocket implant and the cell of FIG. 8B has a double pocket implant; 
     FIG. 9 is a schematic illustration of a hot hole injection mechanism in the cell of the present invention; 
     FIGS. 10A,  10 B and  10 C are schematic illustrations of areas of hot electron and hot hole injection for different implant doses in the cell of the present invention; and 
     FIGS. 11A,  11 B and  11 C are schematic illustrations of the charge distribution after erasure for FIGS. 10A,  10 B and  10 C, respectively. 
    
    
     DETAILED DESCRIPTION OF THE PRESENT INVENTION 
     Applicant believes that a significant source of the breakdown of the cell is charge trapped far from the relevant drain junction, which charge is hard to erase. This is shown in FIGS. 3A,  3 B,  3 C and  3 D, to which reference is now made. 
     FIGS. 3 show the charge stored in right area  108  of the nitride layer as a function of distance along the channel for one cell. FIG. 3A shows that, after the first cycle of programming, a significant amount of charge, labeled  80 , is stored close to the tight bit line, which is the drain for programming and erasure. As one moves away from the drain, the amount of charge reduces, eventually to zero. FIG. 3B shows the amount of charge, labeled  82 , left after the first erase cycle. The erase electric field is typically so effective that it removes extra electrons (more than were present in charge  80 ) such that section  82  is positive while section  80  is negative. Section  82  is thus, hatched, to indicate that it is positively charged. 
     FIGS. 3C and 3D parallel FIGS. 3A and 3B, respectively, but for after 20,000 cycles. After programming, there is a significant charge, labeled  84 , close to the drain, as in FIG.  3 A. However, there is also another section of charge, labeled  86 , further from the drain, which was injected far from the drain junction and was not erased during previous erase cycles. After the 20,000 th  erase cycle, the extra section  86  still remains and is negatively charged, though the previously programmed section  84  has become positively charged section  88 . 
     As can be understood from the above discussion, the diffused charge, in section  86 , is not erased during erasure operations and remains trapped there. Trapped charge  86  acts as partially programmed charge. It is due to trapped charge  86  that the fewer and fewer programming pulses are required to achieve the programmed threshold voltage level (since the bit is already, in effect, partially programmed) and that more and more erasure pulses are required to achieve the erase threshold voltage level (since trapped charge  86  is not removed). 
     Furthermore, the trapped charge  86  affects the reverse read (curves  60  and  64  of FIG. 2A) but not the forward read (curves  62  and  66 ), which is why the two sets of curves are so different. The negative charge far from the source affects the reverse read since the forward read punches through the region under the trapped charge  86 . 
     Applicant believes that the buildup of trapped charge  86  occurs due to slow hot electron programming in the areas away from the drain where the lateral electric field, though smaller, still is enough to inject electrons. Trapped charge  86  is not erased since the erase electric field is only strong enough to erase in the areas very close to the drain. 
     Applicant has realized that, to reduce the charge trapping “far” from the bit line junctions, the field far from the junctions must be reduced. However, this field reduction should not adversely affect the programming efficiency. Thus, the high field must be produced near the bit line junction only. 
     Reference is now made to FIGS. 4A and 4B which illustrate an NROM cell, constructed and operative in accordance with two preferred embodiments of the present invention. FIGS. 4A and 4B are similar to FIGS.  1  and thus, similar reference numerals refer to similar elements. Reference is also made to FIGS. 5A and 5B which are graphs of the lateral channel field and the distribution of channel potential, respectively, for the NROM cells of FIGS. 4A and 4B and for a prior art NROM cell. 
     The NROM cell comprises the channel  100  between the bit lines  102  and  104 , the oxide-nitride-oxide sandwich of layers  109 ,  110 ,  111 , respectively, and the polysilicon gate  112 . A blanket threshold implant is usually present in the channel, though not shown specifically. In addition, in accordance with preferred embodiments of the present invention, the NROM cell comprises either one or two extra implants self-aligned to each the junction of each bit line with the channel  100 . FIG. 4A shows a Boron implant  120  and FIG. 4B shows Boron implant  120  with a Phosphorous implant  122 . 
     The Boron implant  120  is designed to have a maximum concentration near the bit fine  102  or  104  while the Phosphorous implant  122  is designed to have a maximum concentration away from the bit line  102  or  104 . 
     The single pocket implant of Boron  120 , in the embodiment of FIG. 4A, increases the threshold voltage level and, correspondingly, the lateral field, of the cell in the area near each bit line. Since Boron creates holes and Phosphorous creates free electrons, the combined profile, in the embodiment of FIG. 4B, is the difference of the two concentrations throughout the channel. Thus, the “double pocket” implant heightens the lateral field near the bit lines  102  and  104  but significantly reduces the lateral field in the rest of the channel  100 . 
     In both embodiments, the implants are used to shape the lateral channel field so that it is high only close to the bit line junction and so that it drops significantly thereafter. This is shown in FIGS. 5A and 5B which graph of the channel field and potential, respectively, versus the location along the channel  100  for the right bit, for both embodiments and for the prior art. For these figures, the left bit line acts as the source and the right bit line acts as the drain. Position  130  is the location of the maximum concentration of Boron and position  132  is the location of the maximum concentration of the Phosphorous implant, if present. 
     In each Figure, three curves are shown. For FIG. 5A, curve  134  indicates the lateral field with only a blanket threshold Vt implant, curve  136  indicates the lateral field with a single pocket implant, and curve  138  indicates the lateral field with the double pocket implant. 
     As can be seen in curve  134 , when only a blanket Vt implant is present, the lateral field gently increases in the direction of the drain junction. Similarly for the lateral field of a cell with a single pocket implant, except that, as shown in curve  136 , the field is lower throughout most of the channel, increasing significantly in the vicinity of the Boron implant, near the drain junction. In fact, near the drain junction, the cell with the single pocket implant has a stronger lateral field than the cell with no pocket implants (curve  134 ). 
     For the double pocket implant, as seen in curve  138 , the lateral field has a sharp dip  139  in the vicinity of the maximum concentration  132  of the Phosphorous implant and increases sharply toward the drain junction. It is noted that the lateral field is higher near the drain for the double implant than for either the single implant or no implant. 
     Similarly, for the channel potential of FIG.  5 B. Curve  140  graphs the potential for an NROM cell without no implants, curve  141  graphs the potential of a cell with the single pocket implant and curve  142  graphs the potential of a cell with the double pocket implant. The channel potential starts at the 0V of the source and drops towards the negative Vd of the drain for all embodiments. 
     With the double pocket implant, the drain voltage is present only in the very close vicinity of the drain (curve  142 ). For the single pocket implant (curve  141 ), the drain voltage is spread over a slightly larger area near the drain while for the cell of no implants (curve  140 ), the drain voltage is spread over a significant area away from the drain. 
     As indicated by FIGS. 5A and 5B, the single and double pocket implants maintain the effect of the drain voltage (high lateral field and strongly negative voltage level) in the vicinity of the drain. For the double pocket implant, there is a sharp drop-off away from the drain. 
     For both embodiments, the generally thin area of effect forces the programmed charge to remain in a thin area of the nitride  110  (FIGS.  4 ). This improves programming speed when programming ‘this’ bit. Furthermore, since the programmed charge is maintained in an area near the drain, the erase voltage generally removes all of the charge for this bit. The thin area of effect also ensures effective punchthrough when reading the ‘other’ bit. 
     Reference is now made to FIG. 6 which illustrates the threshold voltage level throughout the cell after implantation. As can be seen, the threshold voltage level is low (labeled  150 ) throughout most of the channel with peaks  152  near the bit line junctions  102  and  104 . The height and width of the peaks  152  is a function of the number of implants (one or two) and the locations of maximum concentration of the implant or implants. In general, the general threshold voltage level  150  is at a low level, of about 1V, while the peaks  152  reach a much higher level, such as about 2V. 
     Thus, in the areas to be programmed, the threshold voltage level of the cell starts higher than the standard 1.5V, Furthermore, once a bit has been programmed, for example, with a single unit −Q of charge, the threshold voltage level in the area of interest rises to a programmed level  154 , such as of 3V The programmed threshold voltage level is indicated with dashed lines. 
     Upon erasure, the threshold voltage level of the cell, as indicated with dotted lines, drops to the general level  150  of the center of the cell. As this is below the original threshold voltage level  152  in the drain area, the cell is now erased to a positive charge level, for example of +Q, at least in the area near the bit line junction. To reprogram the cell, one must provide enough negative charge to counter the positive erase state and to bring the cell to the negative level of being programmed. This is opposed to the prior art which programs to the negative level of being programmed (e.g. −2Q) and erases to the initial non-charged state (e.g. 0). 
     It will be appreciated that measuring the change in state between the negative charge, such as −Q, of programming and the positive charge, such as +Q, of erasure is generally easier than measuring, as in the prior art, the difference between the negative charge −2Q of programming and the non-charged state of erasure 0Q It will further be appreciated that the ratio of positive to negative charge does not have to be equal; other ratios, such as 0.25:1.75 are also possible and are incorporated into the present invention. 
     It will still further be appreciated that the low amounts of charge (−1Q or −1.75Q vs. −2Q) reduce the size of the field caused by the presence of charge within the nitride layer. This reduced field helps retain the charge within its desired location. 
     Furthermore, since only the threshold voltage level of the peaks  152  is actively involved in the programming and erasure process, the general level  150  of the center of the cell can be set to any desired low level. 
     Reference is now made to FIGS. 7A,  7 B,  7 C,  7 D,  7 E and  7 F which illustrate an exemplary method of producing the cell of the present invention. 
     Initially, and as shown in FIG. 7A, the oxide, nitride and oxide layers  160 ,  162  and  164 , respectively, are grown on top of a substrate  166 , to form the basis of the ONO structure. Typical thicknesses of layers  160 ,  162  and  164  are 50-100 Å, 20-50 Å, 50-100 Å; respectively. If desired, a p-well or blanket threshold implant, of 5-10 3  per cm 3  can be provided to the substrate  166  prior to growing the ONO layers. 
     A bit line mask  168  is laid down next. The mask is formed of columns laid over the locations of the future channels. The bit lines are to be implanted between the columns  168  and are thus, self-aligned to the future channels. The bit line mask can be formed of a hardened photoresist or of a thick oxide. 
     In accordance with a preferred embodiment of the present invention, the bit line mask  168  is a layer of photoresist hardened with ultraviolet (UV) after being laid down. This makes a hard mask which is not removable using the standard photoresist removal solvents. 
     An alternative bit line mask  168  can be formed of a thick oxide layer, of a minimal thickness of 1000 Å. Such a mask is formed by first depositing a thick oxide layer, typically utilizing the low pressure, chemical vapor deposit (LPCVD) process. A layer of photoresist is then deposited in the desired column pattern after which the oxide found between the photoresist columns is etched away, typically using a dry etch process. The photoresist layer is removed and the thick oxide, bit line mask  168  remains. The thick oxide mask cannot be removed during standard, solvent, photoresist removal techniques. 
     As shown in FIG. 7B, the ONO layers are etched, using a dry etch or wet/dry combination, to remove the oxide and nitride layers between the columns of the bit line mask  168 . The lower oxide layer  160  remains between the columns of the bit line mask  168  to implant through the oxide. This is commonly performed in the art to reduce channeling. 
     The bit lines  104  are then implanted between the columns of the bit line mask  168 . Typically, the implant operation is 45 Kev of Arsenic, up to a dose of 2-6×10 15  per cm 2 . Other implants and dosage levels are also contemplated and are within the scope of the present invention. 
     At this point, the right and left bit line junctions of each cell are separately implanted. For each side, the same operation occurs. A threshold pocket implant, of one or two implant materials, is provided at an angle to the vertical, thereby implanting, in a self-aligned manner, into the bit line junctions as well as into part of the open bit lines near the bit line junctions. The process is then repeated for the other side. 
     FIG. 7C shows the operation for left bit line junctions  170  of one row of cells and indicates the threshold implant with arrows  172 . The implant can be any suitable threshold pocket implant. For a single implant, it can be Boron at 30-120 Kev up to a dose of 1-5×10 13  per cm 2 . The second implant, if there is one, can be Phosphorous at 30-100 Kev up to a dose of 0.5-2.5×10 13  per cm 2 . The remaining discussion of the manufacturing process will use the term “implant” to refer to either a single implant or a double implant unless otherwise stated. 
     The implant is at an angle of 15-45° to the right of vertical. Since the bit line mask  168  covers the channels of all cells, the implant has access only to the left bit line junctions. The implant is to the right of the vertical since the left bit line junctions are on the right of the open bit lines (which is to the left of the neighboring channel). As indicated by the arrows  172 , the angled implant accesses the left bit line junction and a portion of the open bit lines to the left of the junction. The implant is, thus, self-aligned to the left bit line junctions  170  of the channels. 
     The implant dosage must be high enough to ensure sufficient implantation into the channel portion of the bit line junction such that some implant remains even if the bit line later diffuses into the channel. The implant which reaches the rightmost portion of the bit line has no effect on the function of the cell; instead, the implant adds to the bit line implant dosage. Since the threshold implant dosage is two orders of magnitude lower than the bit line implant dosage, it does not affect the dosage within the bit line. 
     The choice of angle is typically based on the desired location of maximum concentration for each implant material and is typically 15-45°. The thickness of the bit line mask  168  affects the amount of shadowing and is a function of the angle of the implant, as follows: 
     Let S be the amount of the bit line  104 , from the bit line mask  168 , to be shadowed, let h 1  be the thickness of the bit line mask  168  and let α be the angle from the vertical of the implant, then: 
     
       
           S=h   1 *tanα 
       
     
     For example, if the desired shadowing S is 800 Å and the angle is 20°, then the thickness h 1  is 2197 Å. 
     FIG. 7D illustrates the threshold implant operation for the right bit line junctions  176 . The implant, labeled by arrows  174 , is at the same angle as before; however, for the right bit line junctions  176 , the implant angle is to the left of vertical. 
     It will be appreciated that the bit line mask  168  is both a bit line mask and a threshold pocket implant mask. Thus, the bit line implant can occur before the pocket implants, as shown, or afterwards. It will further be appreciated that the order for implanting the pocket implant into the right and left bit line junctions is not significant nor does it affect the self-alignment of the implants to the bit line junctions. 
     Once all of the relevant bit line junctions have been implanted, the bit line mask  168  is removed. For UV hardened photoresist, this process involves a plasma removal process of the top photoresist layer followed by standard solvent photoresist removal techniques. If the bit line mask  168  is formed of a thick oxide layer, it is removed with a standard wet etch. 
     Following removal of all of the photoresist elements, the sacrificial oxide layer  160  is removed using a wet etch. The result is shown in FIG.  7 E. Within substrate  166  are the bit lines  104  and the implanted bit line junctions  170  and  176 . If the bit line mask  168  is formed of a thick oxide layer, the sacrificial oxide layer  160  is removed together with the bit line mask. 
     The memory array is now finished in accordance with standard CMOS (complementary, metal-oxide semiconductor) process techniques. The two steps of interest are the gate oxide growth step and the polysilicon word line deposition. 
     A gate oxide layer is now thermally grown over the entire array using standard oxidation techniques. The gate oxide layer  20  is typically grown to a thickness of 30-150 Å over the channels  100 . 
     In the array, the oxidation step causes oxide, labeled  178  in FIG. 7F, to grow over the bit lines  104 . Due to the presence of the nitride in the ONO elements, little oxide is added onto the top of the ONO elements. Due to the presence of implant in the bit line, the oxide over the bit line is thick. If the bit line oxide must be even thicker, an oxidation step can also occur after the implant steps. 
     As noted hereinabove and as shown in FIG. 7F, when the gate oxide is grown, the gate oxide layer  20  is 2-3 times thicker over the bit lines  104  due to the presence therein of the bit line implant material. If the gate oxide is deposited, this is not true. 
     It is noted that the oxidation step occurs after the bit lines have been implanted. If the oxide is grown, the bit lines might diffuse outwardly for lack of an oxide cap. This can contaminate the CMOS area of the chip. In accordance with a preferred embodiment of the present invention, the oxide growth step provides a small amount of oxygen to the oven while slowly ramping the temperature therein, thereby capping the chip with a thin layer of oxide. The ramp typically begins at 700° C. Once the desired temperature is reached, the full amount of oxide should be placed in the oven. 
     The final step is the deposition of the polysilicon gates and word lines  22 , in accordance with standard deposition techniques. The result is the row shown in FIG.  7 E. 
     The standard CMOS backend continues at this point without any special mask to protect the array. 
     Reference is now briefly made to FIGS. 8A and 8B which show alternative embodiments of the present invention for single bit NROM cells. FIG. 8A shows an NROM cell having a single pocket implant  120  on the right side of the cell while FIG. 8B shows an NROM cell having two pocket implants  120  and  122  on the right side of the cell. 
     It will be appreciated that the two, single bit cells of FIGS. 8A and 8B have the same properties as the double bit cells of FIGS. 4A and 4B. Thus, the improved qualities of the lateral field and channel potential of FIGS. 5A and 5B, respectively, are applicable to the cells of FIGS. 8A and 8B during programming, when the right bit line  104  is the drain. 
     It will further be appreciated that the selective threshold levels of FIG. 6 are also applicable to the single bit cells of FIGS. 8A and 8B. Specifically, the threshold voltage level is low (labeled  150 ) throughout most of the channel with peaks  152  near the right bit line junction  104 . 
     Reference is now made to FIG. 9 that illustrates the effect of the pocket implant on the erase mechanism. When an erase voltage V BL  is provided to bit line  104 , holes R are created, by band-to-band tunneling, in the junction of the bit line  104  with the channel  100 . Pocket implant  120  increases the number of holes R created for a given amount of bit line voltage V BL . If the same number of holes is desired, a lower bit line voltage can be used, a generally desirable result. 
     As discussed with respect to FIG. 5A, pocket implant  120  also significantly increases the lateral field in the area of the pocket implant. The lateral field accelerates the holes R such that they become “hot holes”. The hot holes R remain along the surface, labeled  170 , of pocket implant  120 . 
     The vertical field generated by the voltage Vg on gate  112  then pulls the hot holes R into nitride layer  110 . Since the lateral field concentrates the hot holes R near the area of pocket implant  120 , the hot holes R are mainly injected into the portion of nitride  110  which is above the pocket  120 . This is the same area where hot electrons are injected during programming. This “self-aligned” hot hole injection ensures that erasure occurs generally where programming occurs. 
     Pocket implant  120  must be optimized to concentrate hot electron injection (e.g. programming) and hot hole injection (e.g. erasure) in the same area. This is illustrated in FIGS. 10A,  10 B and  10 C, to which reference is now made, where the solid line outlines the area of electron injection and the dashed line outlines the area of hot hole injection. Reference is also made to FIGS. 11A,  11 B and  11 C which illustrate the resultant charge distribution after erasure for FIGS. 10A,  10 B and  10 C, respectively. 
     In FIGS. 10A-10C, the vertical line indicates the edge of the drain junction. For all dosages, electron implantation occurs above the drain in addition to above the pocket implant. Charge stored above the drain (labeled  180  in FIGS. 11A-11C) does not affect the threshold voltage Vt of the channel and thus, does not need to be removed. 
     In FIG. 10A, the implant is of a low dosage. As a result, the hot hole injection is only in the center of the area of electron injection. For this dosage level, an area  182  (FIG. 11A) will remain with charge after erasure even though an area  184  close to the drain  104  will have no charge. This is known as “overprogramming”. 
     In FIG. 10B, the implant is of a high dosage. The area of hole injection extends beyond the area of electron injection. This area, labeled  186  in FIG. 11B, will have holes therein that do not combine with any electrons. This is “overerasure” and also not desirable. 
     In FIG. 10C, the implant is of a more optimal dosage. The area of hole injection ends where the area of electron injection ends. Thus, there are no overerasure or overprogramming areas in FIG.  11 C. There is an area  138 , next to the junction, where no hole injection occurs. This is not a problem, since the electrons in area  138  hardly affect the threshold voltage Vt of the cell. The self-alignment of electron and hole injection further from the junction is important since the presence of holes or electrons away from the junction strongly affects the threshold level when reading in the reverse direction (i.e. the “reverse Vt”). 
     Since the erase rate is a function of the amount of band-to-band tunneling and since pocket implant  120  increases the band-to-band tunneling, the dosage must also be optimized to provide maximal band-to-band tunneling to ensure a maximal erase rate. One dosage which optimizes the various desired characteristics, for 0.5 μm technology, is an implant of 1-4×10 13  per cm 2  of Boron at 60 KeV, provided at 20° from the vertical. 
     It will be appreciated by persons skilled in the art that the present invention is not limited by what has been particularly shown and described herein above. Rather the scope of the invention is defined by the claims that follow: