Patent Publication Number: US-9900978-B2

Title: Printed circuit boards and methods for manufacturing same

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This patent document is a 35 USC § 371 National Stage application of International Application No. PCT/CN2012/083704 filed Oct. 29, 2012, which claims the benefit of priority to China Patent Application No. 201110460708.1 filed Dec. 31, 2011. The disclosure of each of the prior applications is considered part of and is incorporated by reference in the present patent document. 
     TECHNICAL FIELD 
     The present application relates to a technical field of a Printed Circuit Board (PCB) and a method for manufacturing the same. 
     BACKGROUND 
     The Printed Circuit Board (PCB) is a type of important electronic component, and, in general, used to achieve electrical connection among various electronic components. In the PCB with multi-layers, electrical signal is transmitted among various conductive layers of the PCB via a through hole disposed in the PCB. For example, the electrical signal may be transmitted between wirings on two conductive layers of the PCB via the through hole. As shown in  FIG. 1 , the PCB includes two core boards a 1  and a 2  and two prepregs b 1  and b 2 , wherein core board a 1  includes two conductive layers a 11  and a 13  and an insulating layer a 12 , and wherein core board a 2  includes two conductive layers a 21  and a 23 , and an insulating layer a 22 . The through hole c of the PCB has an inner wall plated with a conductive material c 1 , which can transmit the electrical signal between the wiring on the conductive layer a 11  and the wiring on the conductive layer a 13  of the PCB. 
     In a process of manufacturing the PCB, after lamination of the PCB, the through hole is formed by a high speed drilling tool at a preset position on the PCB. The through hole is then metalized, that is to say, the inner wall of the through hole is deposited with copper and then is plated, so that the electrical signal may be transmitted among various conductive layers. In some of those PCBs, however, the through hole is merely used to transmit the electrical signal between the wirings on some of the conductive layers. For example, in the PCB as shown in  FIG. 1 , the through hole c is merely used to transmit the electrical signal between the wiring on the conductive layer a 11  and the wiring on the conductive layer a 13 , while portions of the through hole, which is throughout the prepregs b 1  and b 2  and the insulating layer a 22 , are not necessary for transmitting the electrical signal, and thus form a short line d (the short line refers to extra conductive materials in the through hole, which is not necessary for transmitting the electrical signal). 
     When the high speed electrical signal is transmitted via the through hole, it is easy to distort the electrical signal during transmission due to one or more short lines existing in the through hole in the PCB, which is called short-line effect. With the short-line effect, when the electrical signal is transmitted via the through hole, a part of the electrical signal will enter into one or more short lines of the through hole from a wiring connection on the conductive layer. This part of the electrical signal then may be reflected from an end of the short line to the wiring connection after a certain delay. This delayed reflection may make interference of the integrity of the electrical signal, and increase bit error rate of the electrical signal. In addition, attenuation of the electrical signal will increase as the length of the short line increases. As a result, in order to ensure the transmission of the electrical signal, the short-line effect should be eliminated. 
     Currently, in order to remove the short line of the through hole c in the PCB, the short line of the through hole is back drilled using a drilling tool in general. As shown in  FIG. 2 , a PCB which is back drilled to remove the short line d of  FIG. 1  is shown. A back-drilled hole h is formed at the position corresponding to the short line d as shown in  FIG. 1  after the back-drilling. Although a part of the short line is removed by back drilling, the short line cannot be removed completely since the drilling tool has a pointed tip. Then, parasitic capacitance, parasitic inductance and time delay affecting the integrity of the electrical signal cannot be eliminated completely, that is to say, the short-line effect cannot be eliminated completely. When the PCB is back drilled by using the drilling tool, it is necessary that the drilling tool must have relatively high accuracy. Since the accuracy of the drilling tool is not high, such as, the pointed tip of the drilling tool is too deep accidentally or off-center, it is easy to damage the functional portions (which function to transmit the electrical signal among different conductive layers) of the through hole while removing the short line, so that the PCB is scrapped. As a result, it causes a reduced yield but increased manufacturing cost for the PCB. 
     In view of the above, in the traditional method of removing the short line from the through hole in the PCB by a way of back-drilling, the short-line effect cannot be eliminated completely, and the PCB tends to be scrapped in the process. Consequently, it causes the reduced yield but increased manufacturing cost for the PCB. 
     SUMMARY 
     In embodiments of the present application, a printed circuit board and a method manufacturing same are provided to solve the problems of incompletely eliminated the short-line effect after drilling the PCB and the scrapped PCB easily caused during processes. 
     In an embodiment of the present application, a method for manufacturing a printed circuit board is provide, including: 
     drilling a target prepreg at a position corresponding to at least one preset hole therein so as to form a hole perforating through the target prepreg with an aperture greater than that of the preset hole, and the preset hole does not need to transmit electrical signal between layers; 
     filling the formed through hole with a plating resist ink to prevent the through holes from being plated with a conductive material; 
     laminating the target prepreg and core boards so as to form a multi-layer printed circuit board PCB, wherein some or all of the prepregs are the target prepregs; 
     drilling the multi-layer PCB to perforate the preset holes in the target prepregs; and 
     plating inner walls of holes formed by drilling the multi-layer PCB. 
     When there are a plurality of target prepregs, before drilling the target prepregs, the method further comprises: 
     selecting, from all of the target prepregs, a target prepreg adjacent to a hole in the PCB, which needs to transmit the electrical signal between the layers, as a target prepreg that needs to be drilled. 
     The method in the embodiment of the present application, after filling the through hole with the plating resist ink but before the lamination process, further comprises: 
     curing the plating resist ink; 
     The method in the embodiment of the present application, before drilling the target prepregs, further comprises: 
     covering both top and bottom surfaces of the target prepreg with protective films which prevents the target prepreg from damage during the drilling process, respectively; 
     wherein after curing the plating resist but before the laminating process, the method further comprises: 
     removing the protective films from the top and bottom surfaces of the target prepreg. 
     Preferably, the protective film is a polyester film. 
     Preferably, the plating resist ink is an insulating and hydrophobic resin material. 
     Preferably, the insulating and hydrophobic resin material includes compounds consisting of one or more materials selected from silicon resin, polyethylene resin, fluorocarbon resin, polyurethane resin and acrylic resin. 
     Preferably, the drilling process includes a laser drilling, a mechanical drilling and a punching. 
     Preferably, the filling the through hole with the plating resist ink comprises: 
     filling the through hole with the plating resist by a way of cavity filling; 
     filling the through hole with the plating resist by a way of template printing; or 
     filling the through hole with the plating resist by a way of screen printing. 
     In another embodiment of the present application, a printed circuit board is provided, comprising: 
     at least one target prepreg filled with a plating resist ink, 
     wherein there is a hole ring perforating through the target prepreg at a position corresponding to a preset hole in the target prepreg, 
     an inner hole of the hole ring is the preset hole, and the hole ring has an outer diameter equal to an aperture of the through hole, and is filled with the plating resist ink. 
     Preferably, the printed circuit board further comprises conductive layers, wherein, in a conductive layer of the conductive layers, which is adjacent to the target prepreg, there is conductive material at positions corresponding to the plating resist ink. 
     Preferably, the conductive layers are conductive layers adjacent to and on both sides of the target prepreg. 
     In the embodiments of the present application, the through holes are formed by drilling the target prepregs at the positions corresponding to the preset holes therein, and then the through holes are filled with the plating resist ink, so that the inner wall of the hole ring in the target prepreg will not be plated with the conductive material in the subsequent process of plating the hole formed by drilling the PCB. Then, the insulating portions that avoid the transmitting of the electrical signals are formed in the hole, as a result, the attenuation of the electrical signals is avoided, and the short-line effect is eliminated. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a schematic view showing a structure of a first PCB having un-eliminated short-line effect. 
         FIG. 2  is a schematic view showing a structure of a PCB after back drilled. 
         FIG. 3  is a flow chart showing a first method for manufacturing a first PCB according to an embodiment. 
         FIG. 4A  is a schematic view showing a structure of a second PCB having un-eliminated short-line effect. 
         FIG. 4B  is a schematic view showing a structure of a third PCB having un-eliminated short-line effect. 
         FIG. 4C  is a schematic view showing a structure of a fourth PCB having un-eliminated short-line effect. 
         FIGS. 5A to 5C  are schematic views showing structures of the first PCB while being manufactured according to the first method. 
         FIG. 6  is a flow chart showing a second method for manufacturing a PCB according to an embodiment of the present application. 
         FIG. 7  is a flow chart showing a method for manufacturing a target prepreg filled with a plating resist. 
         FIGS. 8A to 8E  are schematic views showing structures of the target prepreg filled with the plating resist during the manufacturing process according to embodiments of the present application. 
         FIG. 9  is a schematic view showing a structure of a first PCB manufactured by the method according to the embodiment of the present application. 
         FIG. 10  is a schematic view showing a structure of a second PCB manufactured by the method according to the embodiment of the present application. 
         FIG. 11  is a plan view showing the target prepreg filled with the plating resist. 
     
    
    
     DETAILED DESCRIPTION 
     In the present application, a through hole is perforated by drilling at a position corresponding to a preset hole in a target prepreg (PP), and the through hole is filled with a plating resist ink so as to form an insulating portion, such that the problems that the short line effect in the PCB after the back drilling and scrapped PCB easily caused during the process may be resolved. 
     In an embodiment of the present application, a core board is a basic part constituting the PCB. A core board includes two conductive layers and an insulating layer therebetween. In general, the conductive layers included in the core board are copper foil. The prepreg is used as a bonding material among various cores and as an interlayer insulation. It is made of a material selected from FR-4, epoxy glass, polyimide glass, ceramic hydrocarbon, polyimide film, resin impregnated glass cloth, film, resin impregnated matte material, or Kevlar etc. 
     In general, there are two common ways to laminate the PCB. One way is foil-lamination. That is to say, the PCB is constituted of one or more cores, prepregs and foils, wherein the foils are disposed as outermost layers of the PCB. For example, in a PCB constituted of four layers, the cascading order is: a foil layer→a prepreg layer→a core→a prepreg layer→a foil layer. The other way is core-lamination. That is to say, the PCB is constituted of two or more cores, and a prepreg between two adjacent cores. For example, in a PCB constituted of four layers, the order of the sequential lamination is: a core layer→a prepreg→a core layer. 
     It should be noted that the prepreg is made of electronic-grade glass fabric impregnating resin. Before the lamination, the resin in the prepreg is at B-stage (unsteady-state stage). After the lamination, the resin in the prepreg is converted into C-stage (steady-state stage). During the lamination, the core and the foil are bonded together via the prepreg. As such, a plurality of conductive layers and a plurality of insulating layers are processed into an integral structure, which is a foundation to manufacture the multi-layer PCB. In addition, after the lamination, the prepreg has the same insulating function as the insulating layer of the core boards. As a result, the prepreg is also referred as an insulating layer after the lamination. 
     Hereafter, embodiments of the present application are further described in detail with reference to the accompanying drawings. In the embodiments of the present application, the method for manufacturing a PCB by core-lamination is taken as an example. The method for manufacturing a PCB by foil-lamination is similar to core-lamination, and thus will not be described repeatedly herein. 
     As shown in  FIG. 3 , in an embodiment of the present application, the method for manufacturing a PCB includes the following steps. 
     A step S 301  of drilling the target prepreg at a position corresponding to at least one preset hole in the target prepreg to form a through hole perforating throughout the target prepreg, wherein an aperture of the hole is greater than that of the preset hole, and the preset hole does not need to transmit electrical signal; 
     A step S 302  of filling the through holes with the plating resist ink to prevent the through holes from being plated with the conductive material; 
     A step S 303  of laminating the prepregs and the core boards so as to form the multi-layer PCB, wherein some or all of the prepregs under the lamination are the target prepregs; 
     A step S 304  of drilling the multi-layer PCB and perforating through the preset holes in the target prepregs; and 
     A step S 305  of plating inner walls of the preset holes formed by drilling the multi-layer PCB. 
     In general, the PCB includes a plurality of holes for transmitting different electrical signal between different conductive layers. Said holes may be through holes or blind holes. In the present embodiment, the PCB includes one hole for transmitting different electrical signal between different conductive layers, said hole is a through hole and a channel for electrical signal is transmitted between layers. Besides, the method for manufacturing a PCB including a plurality of holes for transmitting different electrical signals between different conductive layers is similar to the method for manufacturing a PCB including one of such holes, and the method for manufacturing a PCB including a plurality of channels for electrical signals transmitted between different conductive layers is similar to the method for manufacturing a PCB including one of such channels for electrical signals, so they are not described repeatedly herein. The instance of which the blind hole is used to transmit different electrical signals between conductive layers is similar to the instance of which the through hole is used, and thus this instance is not repeatedly described herein. 
     It should be noted that a plurality of holes in the PCB for transmitting different electrical signals between different conductive layers are holes formed by drilling after the lamination. However, positions of the holes have been determined during an early design period of the PCB. 
     The preset holes in the target prepreg at step S 301  refer to the holes which do not need to transmit electrical signal between layers. That is to say, each of the preset holes is a portion of the hole for transmitting different electrical signals between different conductive layers, but does not need to transmit the electrical signals. 
     The target prepreg is where the portion of the hole, which does not need to transmit the electrical signal, is disposed. For example, in the PCB as shown in  FIG. 1 , only one channel for electrical signal is transmitted from the conductive layer a 11  to the conductive layer a 13  via the conductive material c 1  on the inner wall of the through hole c. Thus, in the PCB, portions of the through hole c within the prepregs b 1  and b 2  do not need to transmit the electrical signal. Thus, the prepregs b 1  and b 2  are the target prepregs, the portion of the through hole c within the prepreg b 1  is the preset hole in the target prepreg b 1 , and the portion of the through hole c within the prepreg b 2  is the preset hole in the target prepreg b 2 . 
     As another example, the PCB  1  as shown in  FIG. 4A  includes three core boards  10 ,  11  and  12 , and two prepregs  100   a  and  100   b , wherein the core board  10  includes conductive layers  10   a  and  10   c  and an insulating layer  10   b , the core board  11  includes conductive layers  11   a  and  11   c  and an insulating layer  11   b , and the core board  12  includes conductive layers  12   a  and  12   c  and an insulating layer  12   b . The PCB  1  includes one through hole  13  deposited and plated with conductive material  14 . The PCB  1  includes one channel for electrical signal  20  transmitted from the conductive  10   a  to the conductive  11   c  via the conductive material  14  on the inner wall of the through hole  13 . In the PCB  1 , portion of the through hole  13  which is within the prepreg  100   a  needs to transmit the electrical signal  20 , while portion of the through hole  13  which involved by the prepreg  100   b  does not need to transmit the electrical signal  20 . Thus, it is determined that the prepreg  100   b  is the target prepreg, and portion of the through hole  13  within the target prepreg  100   b  is the preset hole within the target prepreg  100   b.    
     As further shown in  FIG. 4B , the PCB  1  includes three core boards  10 ,  11  and  12 , and two prepregs  100   a  and  100   b . Since both portions of the through hole  13  involved by the prepregs  100   a  and  100   b  do not need to transmit the electrical signal, it is determined that the prepregs  100   a  and  100   b  are the target prepregs. And the portion of the through hole  13  within the prepreg  100   a  is the preset hole within the target prepreg  100   a , and that the portion of the through hole  13  within the target prepreg  100   b  is the preset hole within the target prepreg  100   b.    
     At step S 301 , a hole throughout the target prepreg is drilled at a position corresponding to the preset hole, with an aperture greater than that of the preset hole. 
     In particular, if the PCB includes only one target prepreg, a hole is formed by drilling at a position corresponding to the preset hole in the target prepreg. 
     If the PCB includes a plurality of target prepregs, holes are formed by drilling the target prepregs at positions corresponding to the preset holes in at least one of the plurality of target prepregs. 
     In particular, the holes may be formed by drilling the target prepregs at positions corresponding to the preset holes in one or more or all of the target prepregs. For example, in the PCB  1  shown in  FIG. 4B  including two target prepregs  100   a  and  100   b , the holes may be formed by drilling the target prepreg  100   a  the at a position corresponding to the preset hole in the target prepreg  100   a  and by drilling the target prepregs  100   b  at a position corresponding to the preset hole in the target prepreg  100   b , or by drilling the prepregs  100   a  and  100   b  at positions corresponding to the preset holes therein, respectively. 
     Preferably, when there is a plurality of target prepregs, before the drilling, the target prepregs adjacent to holes that need to transmit the electrical signal between layers in the PCB are selected from all of the target prepregs as the target prepregs to be drilled. 
     In particular, when there is a plurality of target prepregs, it is necessary to drill only the targets prepreg adjacent to the hole for transmitting the electrical signal between layers and to fill them with the plating resist ink, so as to achieve the effects of eliminating the short-line effect and preventing the electrical signal from attenuating without processing all of the target prepregs. As a result, the efficiency of processing the target prepregs is improved and the time for manufacturing the PCB is reduced while eliminating the short-line effect and preventing the electrical signal from attenuating. 
     With respect to the PCB  1  as shown in  FIG. 4B , a portion of the through hole  13 , which is used to transmit the electrical signal between layers, is located within the core board  10 . In addition, only the target prepreg  100   a  is adjacent to the portion of the through hole  13 , which is located within the core board  10 . Thus, a position corresponding to the preset hole in the target prepreg  100   a  is selected to be drilled so as to form a hole perforating throughout the selected target prepreg  100   a  and with an aperture greater than that the preset hole. 
     For another example, in the PCB  1  as shown in  FIG. 4C , if the electrical signal  20  is transmitted from the conductive layer  11   a  to the conductive layer  11   c  of the core board  11 , a portion of the through hole  13 , which needs to transmit the electrical signal between the layers, is only a portion of the through hole  13 , which is located within the core board  11 . And portions of the through hole  13 , which are not necessary to be used to transmit the electrical signal between the layers include: 
     a portion of the through hole  13 , which is located within the core board  10 , 
     a portion of the through hole  13 , which is located within the target prepreg  100   a,    
     a portion of the through hole  13 , which is located within the target prepreg  100   b  and 
     a portion of the through hole  13 , which is located within the core board  12 . 
     As a result, the target prepregs adjacent to the portion of the through hole  13 , which is used to transmit the electrical signal between layers, are the target prepreg  100   a  and the target prepreg  100   b.    
     Accordingly, if a position corresponding to the preset hole in the target prepreg  100   a  is only selected to be drilled and filled with the plating resist ink, after the lamination, the electrical signal  20  cannot be prevented from transmitting through the portions of the through hole  13  within the target prepreg  100   b  and the core board  12 , which causes the partial attenuation of the electrical signal  20  so that the short-line effect cannot be eliminated completely. Alternatively, when a position corresponding to the preset hole in the target prepreg  100   b  is only selected to be drilled, which causes the partial attenuation of the electrical signal  20  so that the short-line effect cannot be eliminated completely. Preferably, positions corresponding to the preset holes in the target prepreg  100   a  and the target pregpreg  100   b  are drilled, respectively, so that the attenuation of the electrical signal is avoided, and thus the short-line effect is eliminated completely. 
     The drilling process at step S 301  can be achieved by laser drilling, machine drilling or punching as required. 
     In order to prevent the target prepreg from damage (including wearing, deformation etc.) during the drilling process, both top and bottom surfaces of the target prepreg is covered with a layer of protective film, respectively, before the drilling process. 
     Preferably, the protective film is a polyester film, which has good thermal resistance, surface smoothness, transparency and mechanical flexibility. 
     Accordingly, before lamination, after the plating resist ink is filed the method further includes removing the protective films from the top and bottom surfaces of the target prepreg. 
     The plating resist ink used at step S 302  is an insulating and hydrophobic resin material. 
     Preferably, the insulating and hydrophobic resin material includes compound consisting of one or more materials selected from silicon resin, polyethylene resin, fluorocarbon resin, polyurethane resin and acrylic resin. 
     Further, the compound consists of one or more materials selected from silicon resin, polyethylene resin, fluorocarbon resin, polyurethane resin and acrylic resin may be an ointment or viscous liquid. 
     Filling the hole with the plating resist at step S 302  includes, but not limits to: 
     filling the through hole with the plating resist by way of cavity filling; 
     filling the through hole with the plating resist by way of template printing; or 
     filling the through hole with the plating resist by way of screen printing. 
     At step S 303 , the prepregs and the core boards are laminated so as to form the multi-layer PCB, wherein some or all the prepregs after the lamination are the target prepregs. 
     In particular, taking the PCB  1  as shown in  FIG. 4B  as an example, the prepreg filled with the plating resist ink  60  is the target prepreg  100   b , while the prepreg that is not filled with the plating resist ink  60  is the prepreg  100   a . As a result, all the prepregs  100   a  and  100   b  and the core boards  10  to  12  are laminated according to requirements on manufacturing the PCB  1  so as to form the multi-layer PCB, as shown in  FIG. 5A . 
     At step S 304 , the multi-layer PCB formed at step S 303  is drilled and the preset hole in the target prepreg is formed. 
     In particular, after drilling the multi-layer PCB, a through hole is formed throughout the multi-layer PCB. The through hole extends through the preset hole, with an inner diameter equal to that of the preset hole of the prepreg. Taking the PCB  1  as shown in  FIG. 5A  as an example, when the PCB  1  is drilled to form a through hole, the through hole  13  is formed to extend through the core boards  10  to  12 , the prepreg  100   a  and the target prepreg  100   b , and the hole of the target prepreg  100   b  filled with the plating resist ink  60  is drilled through to form the preset hole, as shown in  FIG. 5B . 
     At step S 305 , the inner wall of the hole formed by drilling the multi-layer PCB is plated. 
     In particular, the inner wall of the hole formed at step S 304  is deposited with copper and plated. After the plating process, the inner wall of the hole with the plating resist ink hasn&#39;t been plated with the conductive material and thus form an insulating portion. In contrast, the inner wall of the hole without the plating resist ink will be plated with the productive material and thus form a conductive portion. Consequently, the electrical signal is transmitted between layers via the conductive portion of the hole. 
     Taking the PCB as shown in  FIG. 5B  as an example, after the through hole  13  of the PCB  1  is deposited with copper and then plated, the inner wall of the through hole  13  without the plating resist ink is plated with the conductive material  14  so as to form the conductive portion, such as, portions of the through hole  13  within the core board  10 , within the prepreg  100   a , within the core boards  11  and  12 . In addition, the inner wall of the through hole  13  with the plating resist ink  60  hasn&#39;t been plated with the conductive material  14  so as to form the insulating portion, such as, the preset hole within the target prepreg  100   b . As shown in  FIG. 5C , the electrical signal  20  can only be transmitted between the wiring of the conductive layer  10   a  and the wiring of the conductive layer  11   c  via the conductive portions of the through hole  13  within the core board  10 , the prepreg  100   a  and the core board  11 , while being isolated from the insulating portions of the through hole  13  within the prepreg  100   b  and the conductive portions of the through hole  13  within the core board  11 . As a result, not only the short-line effect is eliminated but also the attenuation of the electrical signal  20  is avoided, so that the integrity of the electrical signal is ensured. 
     After step S 302  but before step S 303 , the method for manufacturing the PCB according the embodiment of the present application, as shown in  FIG. 6 , further comprises: 
     at step S 306 , curing the plating resist ink. 
     Hereafter, taking laser drilling as an example, a method for processing a target prepreg selected for drilling is described in detail, as shown in  FIG. 7 , comprising: 
     a step S 701  of covering the top and bottom surfaces of the target prepreg  100  with a protective film  50 , respectively, as shown in  FIG. 8A ; 
     a step S 702  of drilling the target prepreg  100  at a position corresponding to the preset hole therein by way of laser drilling, as shown in  FIG. 8B ; 
     a step S 703  of forming a hole  110  perforating throughout the target prepreg  100  and the protective films  50 , as shown in  FIG. 8C , which is carried out after the drilling; 
     a step S 704  of filling the hole  110  with the plating resist ink  60  and curing the plating resist ink  60 , as shown in  FIG. 8D ; and 
     a step S 705  of removing the protective films  50  from the top and bottom surfaces of the target prepreg  100 , as shown in  FIG. 8E . 
     According to an embodiment of the present application, a PCB manufactured according to the method described in the above embodiments of the present application is provided. The PCB includes at least one target prepreg filled with the plating resist ink. The PCB includes a hole ring perforating through the target prepreg at a position corresponding to a preset hole in the target prepreg. The hole ring has an inner hole as the preset hole. The hole ring has an outer diameter equal to that of the through hole. In addition, the hole ring is filled with the plating resist ink. 
     Taking the PCB as shown in  FIG. 1  as an example, a PCB manufactured by way according to an embodiment of the present application is shown in  FIG. 9 . The target prepreg b 1  is selected to be filled with the plating resist ink  60 , while the target prepreg b 2  is selected not to be filled with the plating resist ink  60 . Due to the insulating portion of the target prepreg b 1 , the electrical signal is only transmit from the conductive layer a 11  to the conductive layer a 13  via the conductive portion of the through hole c within the core board a 1 , being isolated from the insulating portion of the through hole c within the target prepreg b 1 , the conductive portion of the throughout c within the core board a 2 , and the conductive portion of the through hole c within the prepreg b 2 . Accordingly, the short-line effect is eliminated and thus the attenuation of the electrical signal is avoided. 
     Preferably, the PCB further includes conductive layers, wherein conductive material is left at position on the conductive layer adjacent to the target prepreg filled with the plating resist ink, the position corresponding to that of the plating resist ink. 
     Preferably, the conductive layers that are adjacent to the target prepreg filled with the plating resist ink refer to conductive layers adjacent to and on both sides of the target prepreg. 
     As shown in  FIG. 9 , the hole ring in the target prepreg b 1  of the PCB is filled with the plating resist ink. The conductive layers adjacent to the target prepreg b 1  refer to the conductive layer a 13  of the core board a 1  and the conductive layer a 21  of the core board a 2 . In addition, portions of the through hole c, which are within the conductive layer a 13  and the conductive layer a 21 , have inner walls filled with the conductive material. 
     In the PCB according to the above embodiment of the present application, in the conductive layers adjacent to and on both sides of the target prepreg filed with the plating resist ink, the inner walls of the holes at the positions corresponding to that of the inner hole (namely, the preset hole) of the hole ring is filled with the conductive material. For target prepreg b 1  as shown in  FIG. 9 , the conductive layers adjacent to and on both sides the target prepreg b 1  are the conductive layer a 13  of the core board a 1  and the conductive layer a 21  of the core board a 2 . 
     The conductive material (such as, copper sheet) at positions on the conductive layers a 13  and a 21 , wherein the positions correspond to those of the plating resist ink in the hole ring of the target pregpreg b 1 , such that the electrical signals can be transmitted from the conductive layer a 11  to the conductive layer a 13  via the through hole c, as shown in  FIG. 9 . Meanwhile, the electrical signal can be transmitted from the conductive layer a 21  to the conductive a 22  via the through hole c, as shown in  FIG. 10 . 
     The positions on the conductive layers a 13  and a 21  corresponding to that of the plating resist ink in the hole ring in the target prepreg b 1  refer to such positions on the conductive layer a 13  and a 21  that contact with the plating resist ink  60  in the hole ring in the target prepreg b 1 . 
     The target prepreg b 1  in  FIG. 11  is shown in  FIG. 9  as a top view. The target prepreg b 1  includes a hole ring b 11  perforating through the target prepreg b 1  at the position corresponding to the preset hole in the target prepreg b 1 . The hole ring b 11  has an inner hole as the preset hole. The hole ring b 11  has an outer diameter equal to that of the through hole. In addition, the hole ring b 2  is filled with the plating resist ink  60 . 
     It should be noted that the case where the PCB includes a channel for transmitting electrical signals between different conductive layers is taken as an example to illustrate the embodiments of the present application. When the PCB includes a plurality of channels for transmitting electrical signals, the PCB manufactured by way of the embodiments of the present application not only eliminates the short-line effect but also avoids interference between various channels of electrical signal, so the integrity of each channel of electrical signal is ensured. 
     According to the embodiments of the present application, the hole ring in the target prepreg is filled with the plating resist ink so that the portion of the through hole at the preset hole forms the insulating portion, which ensured that the PCB after the laminating process has smooth surface. Since the target prepreg has a thickness enough for effectively preventing the electrical signal from transmitting through the insulating portion, the attenuation of the electrical signals would be effectively avoided. 
     Although the present application is described with reference to preferable embodiments, once those skilled in the art learn basic inventive concept, they can make modifications and variants to these embodiments. Therefore, the appended claims are intended to be explained as including the preferable embodiments together with all modifications and variants falling within the script and scope of the present invention. 
     In the embodiments of the present application, the through holes are formed by drilling at the position corresponding to the preset hole in the target prepreg, and the through hole is filled with the plating resist ink, so that the inner wall of the hole ring in the target prepreg will not be plated with the conductive material in the subsequent process of plating the hole formed by drilling the PCB. As a result, the insulating portion for not transmitting the electrical signal is formed in the hole ring, so the attenuation of the electrical signal is avoided and the short-line effect is eliminated. 
     It is apparent to those skilled in the art to make various modifications and variants to the present application without departing from the sprit and scope of the present invention. As such, if these modifications and variants belong to the scope of the present invention and equivalents thereof, these modifications and variants are contained in the present invention.