Patent Publication Number: US-9843181-B2

Title: Semiconductor device including a control circuit

Description:
BACKGROUND 
     Semiconductor devices, e.g. IGBTs (insulated gate bipolar transistors), are typically based on field effect transistor cells that provide a large channel width to keep a voltage drop across the channel low for ensuring low losses in the conductive state. On the other hand, a large total channel width increases the short-circuit current and adversely affects the short circuit ruggedness of the semiconductor device. A high short circuit ruggedness is required in some applications, e.g. the controlling of the speed of electrical motors with an IGBT-equipped inverter. During short circuit, the IGBT actively limits the current flowing through the IGBT thus nearly the full supply voltage drops across the load terminals of the IGBT. During short circuit operation, the power dissipated in the IGBT is extremely high due to a high voltage and a high current at the load terminals at the same time. This energy dissipated leads to a strong increase of the device temperature since it can be drained to a heatsink only in a small portion. It is desirable to provide semiconductor devices with high short circuit ruggedness. 
     SUMMARY 
     According to an embodiment a semiconductor device includes a semiconductor portion with a main FET (field effect transistor) and a control circuit. The main FET includes a gate electrode to control a current flow through a body zone between a source zone and a drift zone. The control circuit receives a local drift zone potential of the main FET cell and outputs an output signal indicating when the local drift zone potential exceeds a preset threshold. 
     Those skilled in the art will recognize additional features and advantages upon reading the following detailed description and on viewing the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The accompanying drawings are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification. The drawings illustrate the embodiments of the present disclosure and together with the description serve to explain principles of the disclosure. Other embodiments and intended advantages will be readily appreciated as they become better understood by reference to the following detailed description. 
         FIG. 1  is a schematic circuit diagram of an IBGT device with a control circuit in accordance with an embodiment. 
         FIG. 2A  is a schematic circuit diagram of an IBGT device with a control circuit in accordance with an embodiment providing an auxiliary FET between the emitter and gate terminals. 
         FIG. 2B  is a cross-sectional view of a portion of the IGBT device of  FIG. 2A . 
         FIG. 3A  is a schematic circuit diagram of an IBGT device in accordance with an embodiment providing a control circuit with an enable input. 
         FIG. 3B  is a schematic cross-sectional view of the IBGT device of  FIG. 3A  through a first auxiliary transistor of the control circuit. 
         FIG. 3C  is a schematic cross-sectional view of the IBGT device of  FIG. 3A  through a second auxiliary transistor of the control circuit. 
         FIG. 3D  is a schematic plan view of a portion of the IBGT device of  FIG. 3A  including the control circuit. 
         FIG. 4  is a cross-sectional view of a portion of an IGBT device in accordance with an embodiment providing a control circuit in an isolated semiconductor region with modified cell trench structures providing the lateral isolation. 
         FIG. 5A  is a schematic circuit diagram of an IBGT device according to an embodiment providing an overcurrent indicator signal. 
         FIG. 5B  is a schematic circuit diagram of an IBGT device in accordance with an embodiment providing an enable input and an overcurrent indicator signal output. 
         FIG. 6  is a schematic circuit diagram of an IBGT device in accordance with an embodiment providing a diode between the control circuit and the gate electrode of the main FET. 
     
    
    
     DETAILED DESCRIPTION 
     In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which are shown by way of illustrations specific embodiments in which the disclosure may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. For example, features illustrated or described for one embodiment can be used on or in conjunction with other embodiments to yield yet a further embodiment. It is intended that the present disclosure includes such modifications and variations. The examples are described using specific language that should not be construed as limiting the scope of the appending claims. The drawings are not scaled and are for illustrative purposes only. For clarity, the same elements have been designated by corresponding references in the different drawings if not stated otherwise. 
     The terms “having”, “containing”, “including”, “comprising” and the like are open and the terms indicate the presence of stated structures, elements or features but not preclude the presence of additional elements or features. The articles “a”, “an” and “the” are intended to include the plural as well as the singular, unless the context clearly indicates otherwise. 
     The term “electrically connected” describes a permanent low-ohmic connection between electrically connected elements, for example a direct contact between the concerned elements or a low-ohmic connection via a metal and/or highly doped semiconductor. The term “electrically coupled” includes that one or more intervening element(s) adapted for signal transmission may exist between the electrically coupled elements, for example elements that temporarily provide a low-ohmic connection in a first state and a high-ohmic electric decoupling in a second state. 
     The Figures illustrate relative doping concentrations by indicating “−” or “+” next to the doping type “n” or “p”. For example, “n − ” means a doping concentration that is lower than the doping concentration of an “n”-doping region while an “n + ”-doping region has a higher doping concentration than an “n”-doping region. Doping regions of the same relative doping concentration do not necessarily have the same absolute doping concentration. For example, two different “n”-doping regions may have the same or different absolute doping concentrations. 
       FIG. 1  illustrates a semiconductor device  500  integrating a power switching device and a control circuit  520 . The illustrated embodiments refer to power switching devices including IGBTs  510 . The same considerations accordingly apply to IGFETs (insulated gate field effect transistors). 
     A circuit model of the IGBT  510  includes a main FET T 1  and a main BJT (bipolar junction transistor) T 2  arranged in a cascade connection. A drain current of the main FET T 1 , having source S that is electrically connected to an emitter terminal E and having gate Ga is electrically connected to a gate terminal G of the IGBT device  500 , controls the base current of the main BJT T 2 . An emitter-collector path is provided between the emitter terminal E and a collector terminal C of the IGBT device  500 . A signal applied to the gate electrode Ga of the main FET T 1  controls via the current flow between source S and drain D of the main FET T 1  the current flow through the main BJT T 2 . 
     The control circuit  520  may include a sense input SE receiving a sense signal, which represents a local drift zone potential of the main FET T 1 . The sense input SE is electrically connected with a sense section of a drift zone of the main FET T 1  close to or directly adjoining an interface between the drift zone and a body zone. The interface may be defined or controlled by a pn junction between the body and drift zones. 
     At a control output CO, the control circuit  520  outputs an output signal indicating whether or not the local drift zone potential exceeds a preset threshold. The preset threshold may indicate an overcurrent condition. The control circuit  520  either limits a short circuit current or limits the period of time during which a short circuit occurs or limits both to improve the short circuit ruggedness of the semiconductor device  500 . The output signal may partly or completely turn down the main FET T 1 . 
     According to an embodiment, the output signal may switch the main FET T 1  off when the local drift zone potential sensed at the sense input SE exceeds the preset threshold. The control output CO of the control circuit  520  may be electrically coupled, e.g. electrically connected, to the gate electrode Ga of the main FET T 1  and pulls the signal at the gate electrode Ga to a voltage below the threshold voltage of the main FET T 1  such that the main FET T 1  switches off irrespective of a signal level applied at the gate terminal G. A resistive element may be provided in the path between the gate terminal G and the network node shared by the control output CO and the gate electrode Ga. 
     According to another embodiment, the control output CO of the control circuit  520  is electrically coupled, e.g. electrically connected, to the gate electrode Ga of the main FET T 1  and pulls the signal at the gate electrode Ga to a voltage between the threshold voltage of the main FET T 1  and the voltage of the external gate drive connected to the terminal G such that the main FET T 1  limits the base current of the bipolar transistor T 2  and thus the overcurrent carried by the IGBT  510 . A resistive element may be provided in the path between the gate terminal G and the network node shared by the control output CO and the gate electrode Ga. 
     The control circuit  520  may include an enable input EN for temporally enabling/disabling the control output CO. In addition or alternatively, the control circuit  520  may have a sense output SO for signaling the overcurrent condition of the IGBT device  500 . 
     In the following, the mode of operation is described with reference to an n-IGBT with an n-FET as main FET T 1  and a pnp BJT as main BJT T 2 . Similar considerations apply to a p-IGBT with a p-FET as the main FET T 1  and an npn BJP as main BJT T 2 . 
     According to an embodiment, the local drift zone potential is the potential in a sense section of the drain zone close to the pn junction between the body and drift zones. In the conductive state, the local drift zone potential at the channel interface typically is below some 100 mV in the non-short-circuit or non-overcurrent conductive state, whereas under an overcurrent condition the local drain zone potential rises up to several Volts. The preset threshold voltage may be the threshold voltage of a field effect transistor at the sense input SE of the control circuit  520 , by way of example. If the local drain zone voltage exceeds the preset threshold, the control circuit  520  may pull the signal at the gate electrode Ga to a voltage below the threshold voltage of the main FET such that the main FET T 1  switches off irrespective of a signal externally applied to the gate terminal G. According to another embodiment, the signal at the gate electrode Ga may be pulled to a voltage between the threshold voltage of the main FET and the voltage supplied by an external gate control thus reducing the level of overcurrent and the power dissipation in the IGBT. This can extend the time until an external gate control senses the short circuit and turns off the IGBT. 
     The control circuit  520  is separated from the load and high voltage paths of the IGBT device  500  having further device parameters that remain unaffected by the control circuit  520 . Apart from the overcurrent behavior, the IGBT device  500  provides the same static and dynamic characteristics as without control circuit  520 , i.e. the static and dynamic characteristics of the IGBT  510 , whereas other methods limiting the short circuit, e.g. by using forward biased diodes, significantly change the static and dynamic characteristics of the concerned IGBT. 
     Switching off the gate signal reduces the conductivity of the channel such that at a preset load current both the voltage drop over the channel and the local drain zone potential increase. The increase of the local drift zone potential accelerates and stabilizes the process of switching off the main FET T 1 . Hence the process of switching off the IGBT device  500  through the control circuit  520  is self-amplifying. 
     With the main NET T 1  being switched off, the applied blocking voltage results in a potential well above the preset threshold voltage at the interface where the local drift zone potential is tapped. The short circuit protection mechanism thus inherently provides a hysteresis characteristic such that oscillations of the gate potential between the potential of the voltage forced by the control circuit  520  and the potential of the externally gate signal applied at the gate terminal G are reliably suppressed. 
       FIG. 2A  depicts the control circuit  520  including a first auxiliary transistor T 3  with the gate electrode receiving the local drift zone potential of the main FET T 1 . The threshold voltage of the first auxiliary transistor T 3  corresponds to the preset threshold. If the local drift zone potential of the IGBT  510  exceeds the threshold voltage of the first auxiliary transistor T 3 , the first auxiliary transistor T 3  supplies to the gate electrode Ga of the main FET T 1  a potential below the threshold voltage of the main FET T 1  irrespective of a signal externally applied to the gate terminal G of the IGBT device  500 . 
     According to an embodiment, the first auxiliary transistor T 3  electrically connects the gate electrode Ga of the main FET T 1  with the emitter terminal E of the IGBT device  500  when the local drift zone potential exceeds the preset threshold, and disconnects the gate electrode Ga from the emitter terminal E when the local drift zone potential falls below the preset threshold. 
     According to a further embodiment, a zener diode may be arranged in series with the first auxiliary transistor T 3 . The Zener diode bars the gate voltage from being lowered to 0V. 
       FIG. 2B  shows a portion of the IGBT device  500  with the IGBT  510  and the control circuit  520  integrated in the same semiconductor die. A semiconductor portion  100  of the semiconductor die is based on a single-crystalline semiconductor material, for example silicon Si, silicon carbide SiC, germanium Ge, a silicon germanium crystal SiGe, gallium nitride GaN or gallium arsenide GaAs. A distance between a first surface  101  of the semiconductor portion  100  and second surface  102 , which is parallel to the first surface  101 , may be at least 40 μm, for example at least 60 μm or at least 100 μm. The semiconductor portion  100  may have a rectangular shape with an edge length in the range of several millimeters. The normal to the first and second surfaces  101 ,  102  defines a vertical direction and directions orthogonal to the normal direction are lateral directions. 
     In an IGBT area  610  a plurality of parallel, vertical transistor cells  512  of a main FET T 1  are arranged adjoining to or close to the first surface  101 . In a conductive state of the main FET T 1 , vertical channels of the transistor cells  512  direct the on-state current in a vertical direction through body zones  115 . 
     The transistor cells  512  form the main FET T 1 , and may be, for example, an MOSFET (metal oxide semiconductor field effect transistor) of the enhancement type, wherein the usual meaning of the term MOSFET includes both FETs with metal gate electrodes and FETs with non-metal electrodes. The transistor cells  512  include gate electrode structures  150  formed in cell trench structures extending from the first surface  101  into the semiconductor portion  100 . The gate electrode structures  150  may be electrically connected with the gate terminal G of the IGBT device  500 . Gate dielectrics  210  dielectrically insulate the gate electrode structures  150  from the surrounding semiconductor material of the semiconductor portion  100 . 
     In semiconductor mesas between the cell trench structures, source zones  110  of a first conductivity type may directly adjoin the first surface  101 . Body zones  115  of a second, complementary conductivity type extend between neighboring cell trench structures and separate the source zones  110  from a drift layer  120  of the first conductivity type, wherein a pn junction between the body zones  115  and the drift layer  120  is in substance parallel to the first and second surfaces  101 ,  102 . Heavily doped contact zones  117  of the second conductivity type may extend between neighboring source zones  110  from the first surface  101  into body zones  115  and provide a low-ohmic connection of the body zones  115 . 
     A collector layer  130  of the second conductivity type separates the drift layer  120  from the second surface  102 . The drift layer  120  may include a low-doped drift zone  121  and a more heavily doped field stop zone  128 . A mean net impurity concentration in the collector layer  130  may be at least 1×10 16  cm −3 , for example at least 5×10 17  cm −3 . The mean net impurity concentration in the field stop zone  128  or buffer layer may be between 1×10 15  cm −3  and 5×10 16  cm −3  or even up to 1×10 18  cm −3  and may exceed at least five times the mean net impurity concentration in the drift zone  121 . According to an embodiment, the field stop zone  128  may have an inhomogeneous doping in a vertical direction exhibiting one or more local maxima and/or one or more local minima. At the local maxima, the peak doping may excess the mean net impurity concentration in the field stop zone  128  up to a factor of 100 while the local minima may exhibit an impurity concentration down to the doping concentration of the drift zone  121  or even below. The mean net impurity concentration in the drift zone  121  may be between 5×10 12  cm −3  and 5×10 14  cm −3 , by way of example. 
     A first electrode structure  310  is provided at the side of the first surface  101 . Contact structures  315  extend through openings in a dielectric layer  220  covering the trench cell structures at least down to the first surface  101  and may electrically connect the first electrode structure  310  with the source zones  110  and the contact zones  117 . According to other embodiments, the contact structures  315  fill contact grooves extending from a plane spanned by the first surface  101  into the semiconductor portion  100 . The first electrode structure  310  may form or may be electrically connected or coupled to an emitter terminal E of the IGBT device  500 . 
     A second electrode structure  320  directly adjoins the second surface  102  and is electrically connected to the collector layer  130 . The second electrode structure  320  may form or may be electrically connected or coupled to a collector terminal C of the IGBT device  500 . 
     In the following description, the first conductivity type is the n type and the second conductivity type is the p type. According to other embodiments, the first conductivity type may be the p type and the second conductivity type may be the n type. 
     The IGBT  510  may be modeled as an n type main FET T 1  having a drain current that supplies the base current of a pnp main BJT T 2 , wherein the body zone  115  and the collector layer  130  are effective as emitter and collector regions and the drift layer  120  provides a base region of the main BJT T 2 . 
     The control circuit  520  may be formed in an isolated semiconductor region  430  in a circuit area  690  of the semiconductor portion  100 . A dielectric shield structure  410  dielectrically insulates the isolated semiconductor region  430 , which comprises semiconductor elements of the control circuit  520 , at least in a vertical direction from the surrounding semiconductor material of the semiconductor portion  100  with the drift zone  121 . The dielectric shield structure  410  bars charge carriers flooding the drift layer  120  from adversely affecting the functionality of the semiconductor elements of the control circuit  520 . 
     According to an embodiment, the dielectric shield structure  410  includes a buried portion  411  separating the isolated semiconductor region  430  from the drift layer  120  in the vertical direction. The dielectric shield structure  410  may consist of or contain a semiconductor oxide layer, for example a silicon oxide layer and may include tubes  412  filled with a gaseous material such as oxygen, nitrogen, a noble gas or a mixture of these gases or containing a vacuum. According to an embodiment, the tubes  412  may be alternatively or additionally at least partially filled with conductive material. 
     According to the illustrated embodiment, the dielectric shield structure  410  further includes vertical portions  415  and forms a closed frame extending from the first surface  101  into the semiconductor portion  100 , wherein the closed frame completely surrounds the isolated semiconductor region  430 . 
     The isolated semiconductor portion  430  may have a main portion  438  of the second conductivity type, wherein wells of the first conductivity type extend from the first surface  101  into the main portion  438  and form source and drain zones  432 ,  436  of one or more auxiliary transistors or cathode zones of diodes electrically arranged between the IGBT  510  and the control circuit  520 . 
     The semiconductor elements forming the control circuit  520  may include one or more field effect transistors of a planar or vertical design. According to the illustrated embodiment, the control circuit  520  includes a first auxiliary transistor T 3 . The first auxiliary transistor T 3  may be a transistor with a vertical or a lateral channel. According to the illustrated embodiment, the first auxiliary transistor T 3  is a planar transistor with a gate structure  450  provided outside the semiconductor portion  100 . A gate dielectric  440  dielectrically insulates the gate structure  450  from a body zone formed by a section of the main portion  438  between the source and drain zones  432 ,  436 . A source electrode  318  directly adjoins the source zone  432  and a heavily doped contact zone  437  of the second conductivity type extending from the first surface  101  into the main portion  438 . The source zone  432  may be electrically connected with the first electrode structure  310  and the emitter terminal E. A drain electrode  340  directly adjoins the drain zone  436  and may be electrically connected with the gate electrode structures  150  of the IGBT  510  and the gate terminal G. A sense connection structure  330  may be electrically connected with both the gate structure  450  and a heavily doped sense contact zone  112  of the first conductivity type. 
     Each of the first and second electrode structures  310 ,  320 , the source and drain electrodes  318 ,  340  of the first auxiliary transistor T 3  and the sense connection structure  330  may consist of or contain, as main constituent(s) aluminum Al, copper Cu, or alloys of aluminum or copper, for example AlSi, AlCu or AlSiCu. According to other embodiments, one, more or all of the first and second electrode structures  310 ,  320 , the source and drain electrodes  318 ,  340  and the sense connection structure  330  may contain one or more layers with nickel Ni, titanium Ti, silver Ag, gold Au, platinum Pt, tungsten W, cobalt Co and/or palladium Pd as main constituent(s). For example, at least one of the cited structures  310 ,  320 ,  318 ,  340 ,  330  includes two or more sub-layers, at least one of the sub-layers containing one or more of Ni, Ti, Ag, Au, Pt, W, Co and Pd as main constituent(s), e.g., a silicide, a nitride and/or an alloy. 
     The sense contact zone  112  may be a one-part structure or may include several spatially separated portions. According to an embodiment, the sense contact zone  112  consists of or includes a portion directly adjoining an outermost one of cell trench structures arranged in a cell array. Further portions of the sense contact zone  112  may directly adjoin another cell trench structure of the cell array. The sense connection structure  330  directly adjoins and provides an ohmic contact with all portions of the sense contact zone  112 . 
     Between the pn junction formed between the body zone  115  and the drift zone  121  of the outermost transistor cell  512  and the sense contact zone  112  a contiguous path exists in semiconductor material of the first conductivity type along the outermost cell trench structure. 
     In the conductive state of the IGBT  510 , a positive voltage applied to the gate electrode structures  150  induces an electron accumulation channel  111  along the contour of the outermost cell trench structure between the pn junction and the sense contact zone  112 . The accumulation channel  111  taps the local drift zone potential close to the pn junction and at the end of an inversion channel in the body zone  115  of the outermost transistor cell  512  and supplies the local drift zone potential to the sense contact zone  112 . 
     The sense contact zone  112  is shielded by the adjoining cell trench structure and/or by neighboring impurity zones of the second conductivity type. Since the sense contact zone  112  is only connected to the gate structure  450  of the high-impedance auxiliary FET T 3 , the tapping of the local drift zone potential does not induce a current flow in the accumulation channel  111 . 
     In addition to the first auxiliary transistor T 3  of  FIGS. 2A and 2B , the control circuit of  FIG. 3A  includes a second auxiliary transistor T 4  providing an enable functionality. The signal at the gate electrode Ga of the main FET T 1  becomes inactive irrespective of a signal applied at the gate terminal G only when both the local drift zone potential indicates an overcurrent condition and an enable signal applied at the gate electrode of the second auxiliary transistor T 4  is active. The enable signal may be generated by a driver circuit integrated in the semiconductor portion  100  or may be externally applied through an enable terminal EN of the IGBT device  500 . 
     The first and second auxiliary transistors T 3 , T 4  may be arranged in series between the emitter terminal E and the gate electrode Ga of the main FET T 1 . By controlling adequately the enable signal the overcurrent protection mechanism may be temporally or permanently disabled or enabled. For example, a control unit supplying the enable signal may control the enable signal such that the overcurrent protection is disabled during switching periods during which the IGBT  510  is switched on or off. For example, the overcurrent protection mechanism may be activated some 10 ns, some 100 ns or some microseconds, at least less than 5 microseconds after the signal at the gate terminal G changes from inactive to active and remains activated until the gate terminal G changes back to inactive. According to another embodiment, the control circuit  520  may be disabled some 100 ns or some microseconds, at least less than 5 microseconds before the signal at the gate terminal G changes from active to inactive. 
       FIGS. 3B to 3D  show cross-sectional views of the IGBT device  500  of  FIG. 3A  according to an embodiment providing the first and second auxiliary transistors T 3 , T 4  as lateral transistors in an isolated semiconductor region  430 . 
       FIG. 3B  widely corresponds to the cross-sectional view of  FIG. 2B . Other than in the previous embodiment, the drain electrode  340  of the first auxiliary transistor T 3  is not electrically connected with the gate electrode structures  150  but is also effective as the source electrode of the second auxiliary transistor T 4  as shown in  FIG. 3D . 
     The second auxiliary transistor T 4  shown in  FIG. 3C  may be arranged in the same isolated semiconductor region  430  as the first auxiliary transistor T 3  and may be oriented parallel to the first auxiliary transistor T 3 . A further electric connection  375  may electrically connect a drain electrode  370  of the second auxiliary transistor T 4  with the gate electrode structures  150  of the IGBT  510 . A gate electrode  360  of the second auxiliary transistor T 4  may form or may be electrically connected or coupled to an enable terminal EN of the IGBT device  500  or an output of a driver circuit integrated in the semiconductor portion  100 . 
     As shown in  FIG. 3D , a shallow trench insulation  439  may separate the first and second auxiliary transistors T 3 , T 4 . Other embodiments may provide a pn separation of the first and second auxiliary transistors T 3 , T 4  using p-type sections of the main portion  438 . 
     Referring back to  FIG. 3B , the dielectric shield structure  410  may comprise a buried portion  411  including tubes  412  filled with a gaseous material such as, oxygen, nitrogen, a noble gas or a mixture of these gases or may contain a vacuum. According to an embodiment, the tubes  412  may be alternatively or additionally at least partially filled with conductive material. The tubes  412  are extending in a direction perpendicular to the cross-sectional plane and parallel to the cell trench structures. 
     According to an embodiment, the buried portion  411  of the dielectric shield structure  410  may be provided by introducing, from the first surface  101 , auxiliary trenches into the semiconductor portion  100  in an auxiliary trench field. The auxiliary trenches may be narrower and shallower than trenches for providing the cell trench structures. A wider circumferential trench may surround the auxiliary trench field. A thin thermal oxide may be grown and patterned by a lithographic process, such that the patterned thermal oxide exposes the auxiliary trench field and covers the area outside the auxiliary trench field. The auxiliary trench field is exposed to a heating process in a hydrogen ambient wherein in the area exposed by the patterned thermal oxide the semiconductor material liquefies and forms joint ridges arching over lower portions of the auxiliary trenches converted to tubes  412 . Outside the auxiliary trench field, the thin sacrificial oxide bars the semiconductor material from fluidifying. End portions of the tubes  412  may be exposed by a further auxiliary trench that may laterally enclose the ridges. A further oxidation process may oxidize the ridges such that the tubes  412  are separated by oxide. 
     Since the process of liquefying can be performed in an epitaxy reactor the process may be integrated with growing by epitaxy the isolated semiconductor region  438 . During the latter process the gate trenches for the cell trench structures may be filled with e.g. conductive polycrystalline semiconductor material, which also may cover the inner surface of the tubes  412  via the surrounding further auxiliary trench. The conductive material may be connected with the source or emitter connection E and thus shield the semiconductor material in the well from voltage fluctuations caused by the collector potential at the second surface  102  of the semiconductor portion  100 . 
     During turning-on and turning-off the main IGBT the voltage change at the collector potential leads to a capacitive coupling to the conductive structures in the tubes  412 . According to another embodiment, at least a part of the conductive structures in the tubes  412  embedded in the buried portion  411  may be connected to a sense terminal SNS as shown in  FIG. 3C  or to a sense transistor and is used to detect the voltage fluctuations at the collector terminal. 
     The resulting dielectric shield structure  410  dielectrically insulates an isolated semiconductor region provided within the frame-like dielectric shield structure  410  in the vertical and lateral directions. 
     The tubes  412  not completely filled with a solid dielectric but containing a gas, a vacuum and/or a conductor allow to control the thermomechanical stress caused by the buried portion  411  and thus allow thicker buried portions  411 . Thicker buried portions  411  reduce capacitive coupling between the voltage fluctuations at the collector terminal and the isolated semiconductor region  430 . Thicker buried portions  411  further allow higher voltage differences between the isolated semiconductor region  430  and the adjacent part of the drift zone  160 . 
     According to the embodiment illustrated in  FIG. 4 , the vertical portions  415  of the dielectric shield structure  410  are modified cell trench structures. The modified cell trench structures may include a fill structure  415   a  of a conductive material, for example heavily doped polycrystalline silicon. A dielectric liner corresponding to the gate dielectric  210  of  FIG. 2B  dielectrically separates the fill structure  415   a  from the material of the semiconductor portion  100  and the isolated semiconductor region  430 . The fill structure  415   a  may be electrically connected with the emitter terminal E. The main portion  438  of the isolated semiconductor region  430  may be doped in the same process as the body zones  115  of the IGBT  510 . The auxiliary transistors of the control circuit  520  may be lateral transistors with trench gates. 
       FIG. 4  shows the trench gate  450  for the first auxiliary transistor T 3  having a drain zone that is arranged in a direction perpendicular to the cross-section. For example the gate electrode  450  of the first auxiliary transistor T 3  is located in a trench reaching from the first surface  101  of the semiconductor material to the buried portion  411  and dielectrically insulated from the main portion  438  in the isolated semiconductor region  430  by a dielectric which may act as gate dielectric  440 . According to an embodiment, the source and drain connections of the first auxiliary transistor T 3  may be located on both sides of the gate trench  450  to increase channel width and current capability of the first auxiliary transistor T 3 . The second auxiliary transistor T 4  may be realized in the same way and is not shown in  FIG. 4  for more clarity. 
     According to an embodiment, the body zones  115  of both the first and second auxiliary transistors T 3 , T 4  are electrically connected with the emitter terminal E such that in the case of a n-IGBT the main portion  438  in the isolated semiconductor region  430  has the most negative potential in the IGBT device  500  and can be used for a pn isolation of semiconductor elements of the control circuit, e.g. the first and second auxiliary transistors T 3 , T 4  of  FIGS. 3A to 3D . According to an embodiment, the gate control voltage of the IGBT at the gate terminal G may be set to a negative voltage during off-state. In this case, the main portion  438  in the isolated semiconductor region  430  has to be set to the negative supply voltage of the gate control to fulfill the requirement of the most negative potential in the IGBT device  500 . 
     The IGBT device  500  illustrated in  FIG. 5A  provides a third auxiliary transistor T 5  for signalizing an overcurrent condition. The third auxiliary transistor T 5  widely corresponds to the first auxiliary transistor T 3  of  FIG. 2A . Other than the first auxiliary transistor T 3  of  FIG. 2A , the drain of the third auxiliary transistor T 5  is not electrically connected to the gate electrode Ga of the main FET T 1  but to a sense output terminal SO or to an input of a circuit integrated in the IGBT device  500 . The embodiment support applications subject to high safety and security standards, for example in the field of automotive, that require feedback information signalizing a switching state or a fail state of a switching device. 
     The feedback feature may be combined with any of the above-described embodiments.  FIG. 5B  combines the feedback feature with the self-sustaining shutdown feature implemented by the first auxiliary transistor T 3  and the enable feature for the self-sustained shutdown realized by the second auxiliary transistor T 4 . 
       FIG. 6  integrates a diode D between the gate terminal G and the control output of the control circuit  520 , e.g. the drain of the second auxiliary transistor T 4 , for allowing the self-sustained shutdown for externally applied gate voltages which are more negative than the potential applied at the emitter terminal E. 
     Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that this invention be limited only by the claims and the equivalents thereof.