Patent Publication Number: US-9431341-B2

Title: Semiconductor device having metal patterns and piezoelectric patterns

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2013-0139140 filed on Nov. 15, 2013, the disclosure of which is hereby incorporated by reference in its entirety. 
     BACKGROUND 
     1. Field 
     Embodiments of the inventive concept relate to a semiconductor device including a metal pattern and a piezoelectric pattern. 
     2. Description of Related Art 
     Methods for fabricating highly integrated semiconductor devices by forming a metal pattern on the semiconductor device, and directly connecting or bonding the metal patterns to each other, have been provided. Conventionally, a process of connecting or bonding the metal patterns to each other requires the semiconductor device to be heated at a high temperature. However, since the heat process may mechanically, physically, chemically, or electrically damage or break circuit patterns due to a heat budget exerted on fine circuit patterns of the semiconductor device, the conventional approach is problematic. 
     SUMMARY 
     Embodiments of the inventive concept provide a semiconductor device including a piezoelectric pattern. 
     Other embodiments of the inventive concept provide a method of fabricating a semiconductor device including a piezoelectric pattern. 
     In still other embodiments of the inventive concept provide a semiconductor device capable of bonding through-silicon-vias and/or pads, with no heat process. 
     In still other embodiments of the inventive concept provide bonding structures of semiconductor devices including piezoelectric patterns. 
     The technical aspects of the inventive concept are not limited to the above disclosure. Other inventive aspects may become apparent to those of ordinary skill in the art based on the following descriptions. 
     In accordance with an aspect of the inventive concept, a semiconductor device includes a passivation layer defining a metal pattern on a first surface of a substrate, an inter-layer insulating layer disposed on a second surface of the substrate, and a piezoelectric pattern formed between the metal pattern and the passivation layer on the first surface of the substrate. 
     In accordance with another aspect of the inventive concept, a semiconductor device includes a first passivation layer disposed on a first surface of a substrate, a second passivation layer disposed on a second surface of the substrate, a through-via structure vertically passing through the substrate and the first passivation layer, and a piezoelectric pattern formed between the through-via structure and the second passivation layer. 
     In accordance with another aspect of the inventive concept, a semiconductor device may include a front-side passivation layer disposed on a first surface of a substrate, a back-side passivation layer disposed on a second surface of the substrate, a through-via structure vertically passing through the substrate and the back-side passivation layer, a first piezoelectric pattern formed between the through-via structure and the back-side passivation layer, a pad structure formed on the first surface of the substrate, a wrapping layer formed on the front-side passivation layer, and a second piezoelectric pattern formed on the front-side passivation layer. The second piezoelectric pattern may be further formed between side surfaces of the pad structure and the wrapping layer. 
     Details of other embodiments are included in the detailed description and drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The foregoing and other features and advantages of the inventive concepts will be apparent from the more particular description of preferred embodiments of the inventive concepts, as illustrated in the accompanying drawings in which like reference numerals denote the same respective parts throughout the different views. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the inventive concepts. In the drawings: 
         FIGS. 1A to 1F , and  FIGS. 2A to 2C  are vertical cross-sectional views for describing semiconductor devices in accordance with various embodiments of the inventive concept; 
         FIGS. 3A to 3F  are schematic views illustrating bonding structures of various through-silicon-via structures in accordance with various embodiments of the inventive concept; 
         FIGS. 4A to 4F , and  FIGS. 5A to 5R  are schematic views illustrating bonding structures of through-silicon-via structures and pad structures in accordance with various embodiments of the inventive concept; 
         FIGS. 6A and 6B  are schematic views illustrating bonding structures of pad structures in accordance with embodiments of the inventive concept; 
         FIGS. 7A to 7T ,  FIGS. 8A to 8C ,  FIGS. 9A and 9B ,  FIGS. 10 to 13 ,  FIGS. 14A and 14B , and  FIG. 15  are vertical cross-sectional views showing methods of fabricating a semiconductor device in accordance with embodiments of the inventive concept; 
         FIGS. 16A to 16F  are schematic views illustrating bonding structures of metal interconnections in accordance with embodiments of the inventive concept; 
         FIGS. 17A to 17F  are schematic views illustrating bonding structures of metal lines in accordance with various embodiments of the inventive concept. 
         FIG. 18A  is a schematic view illustrating a semiconductor module in accordance with an embodiment of the inventive concept; and 
         FIGS. 18B and 18C  are block diagrams schematically showing electrical systems in accordance with embodiments of the inventive concept. 
     
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
     Various embodiments will now be described more fully with reference to the accompanying drawings in which some embodiments are shown. These inventive concepts may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure is thorough and complete and fully conveys the inventive concept to those skilled in the art. 
     The terminology used herein to describe embodiments of the invention is not intended to limit the scope of the invention. The articles “a,” “an,” and “the” are singular in that they have a single referent; however, the use of the singular form in the present document should not preclude the presence of more than one referent. In other words, elements of the invention referred to in the singular may number one or more, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and/or “including,” when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. 
     In the drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. It will be understood that when an element or layer is referred to as being “on,” “connected to,” or “coupled to” another element or layer, it can be directly on, connected or coupled to the other element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly connected to,” or “directly coupled to” another element or layer, there are no intervening elements or layers present. In the following explanation, the same reference numerals denote the same components throughout the specification. 
     Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper,” and the like may be used herein to describe the relationship of one element or feature to another, as illustrated in the drawings. It will be understood that such descriptions are intended to encompass different orientations in use or operation in addition to orientations depicted in the drawings. For example, if a device is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the term “below” is intended to mean both above and below, depending upon overall device orientation. 
     Embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments and intermediate structures. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. 
     It will be understood that, although the terms first, second, A, B, etc. may be used herein in reference to elements of the invention, such elements should not be construed as limited by these terms. For example, a first element could be termed a second element, and a second element could be termed a first element, without departing from the scope of the present invention. Herein, the term “and/or” includes any and all combinations of one or more referents. 
     Terms such as “front side” and “back side” may be used in a relative sense herein to facilitate easy understanding of the inventive concept. Accordingly, “front side” and “back side” may not refer to any specific direction, location, or component, and may be used interchangeably. For example, “front side” may be interpreted as “back side” and vice versa. Also, “front side” may be expressed as “first side,” and “back side” may be expressed as “second side,” and vice versa. However, “front side” and “back side” cannot be used interchangeably in the same embodiment. 
       FIGS. 1A to 1F  are vertical cross-sectional views showing semiconductor devices  10   a  to  10   f  in accordance with various embodiments of the inventive concept. 
     Referring to  FIG. 1A , a semiconductor device  10   a  in accordance with an embodiment of the inventive concept may include a substrate  100 , a transistor  110 , a lower inter-layer insulating layer  115 , a lower metal interconnection  130 , an intermediate inter-layer insulating layer  135 , an upper metal interconnection  140 , an upper inter-layer insulating layer  145 , a front-side passivation layer  146 , and a pad structure  150 , which are formed on a first surface of the substrate  100 . In addition, the semiconductor device  10   a  may include a through-silicon-via (TSV) structure  120  passing through the substrate  100 . Moreover, the semiconductor device  10   a  may include a back-side passivation layer  163  and a back-side piezoelectric pattern  170 , which are formed on a second surface of the substrate  100 . 
     The substrate  100  may include a single-crystalline silicon bulk wafer, a compound semiconductor wafer, or a silicon-on-insulator (SOI) wafer. 
     The transistor  110  may include a gate stack  110   g  and source/drain areas  110   s  and  110   d . The gate stack  110   g  may selectively include a stacked gate insulating layer  111 , gate electrode  112 , and gate capping layer  113 , and/or a gate spacer  114  surrounding the gate insulating layer  111 , the gate electrode  112 , and/or the gate capping layer  113 . The gate insulating layer  111  may include silicon oxide or a metal oxide. The gate electrode  112  may include a conductor, such as doped silicon, a silicide, a metal or a metal compound. The gate capping layer  113  may include silicon nitride. The gate spacer  114  may include silicon oxide and/or silicon nitride. The source/drain areas  110   s  and  110   d  may include at least one of boron (B), phosphorus (P), or arsenic (As) injected into the substrate  100 . Otherwise, the source/drain areas  110   s  and  110   d  may include a metal silicide. 
     The lower inter-layer insulating layer  115  may be formed on the substrate  100  to cover the transistor  110 . The lower inter-layer insulating layer  115  may include silicon oxide. 
     The lower metal interconnection  130  may include a through-silicon-via (TSV) pad  131 , a lower via plug  132 , and a lower metal line  133 , which are formed on the lower inter-layer insulating layer  115 . The TSV pad  131  may be vertically aligned with the TSV structure  120 . The lower via plug  132  may be disposed on the TSV pad  131 . In a plan view, the TSV pad  131  and the lower via plug  132  may have a circular or polygonal shape, and the lower metal line  133  may have a horizontally extending shape, such as a linear shape. As shown in  FIG. 1A , in a vertical cross-sectional view or a side view, the lower via plug  132  may have the shape of a pillar vertically passing through the intermediate inter-layer insulating layer  135 . The lower metal interconnection  130  may include one or more metals, such as tungsten (W), titanium (Ti), cobalt (Co), nickel (Ni), aluminum (Al), or copper (Cu). 
     The intermediate inter-layer insulating layer  135  may be formed on the lower inter-layer insulating layer  115  to cover the lower metal interconnection  130 . The intermediate inter-layer insulating layer  135  may include a silicon oxide. 
     The upper metal interconnection  140  may include an inter-via pad  141 , an upper via plug  142 , and an upper metal line  143 , which are formed on the intermediate inter-layer insulating layer  135 . The inter-via pad  141  may be vertically aligned with the lower via plug  132 . The upper via plug  142  may be disposed on the inter-via pad  141 . In a plan view, the inter-via pad  141  and the upper via plug  142  may have a circular or polygonal shape, and the upper metal line  143  may have a horizontally extending in a line shape. As shown in  FIG. 1A , in a cross-sectional view or a side view, the upper via plug  142  may have the shape of a pillar vertically passing through the upper inter-layer insulating layer  145 . The upper metal interconnection  140  may include one or more metals, such as tungsten (W), titanium (Ti), cobalt (Co), aluminum (Al), or copper (Cu). 
     The upper inter-layer insulating layer  145  may be formed on the intermediate inter-layer insulating layer  135  to cover the upper metal interconnection  140 . The upper inter-layer insulating layer  145  may include silicon oxide. 
     The front-side passivation layer  146  may be formed on the upper inter-layer insulating layer  145 . The front-side passivation layer  146  may include silicon nitride, silicon oxide, and/or polyimide. 
     The pad structure  150  may be aligned with the upper via plug  142 . A lower part of the pad structure  150  may vertically penetrate the front-side passivation layer  146  to be connected to the upper via plug  142 . The pad structure  150  may include a pad bather layer  152 , a pad seed layer  153 , and a pad core  154 . The pad barrier layer  152  may include one or more barrier metals or metal compounds, such as titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), titanium tungsten (TiW), or tungsten nitride (WN). The pad seed layer  153  may include one or more seed metals, such as copper (Cu), tungsten (W), or nickel (Ni). The pad core  154  may have a mesa shape. The pad core  154  may include copper (Cu) or nickel (Ni). The pad seed layer  153  and the pad core  154  may include the same metal. In other embodiments, the pad seed layer  153  and the pad core  154  may include a different metal. Accordingly, a boundary between the pad seed layer  153  and the pad core  154  is indicated by a solid line. The pad structure  150  may protrude from the front-side passivation layer  146 . 
     The back-side passivation layer  163  may be formed on a back-side of the substrate  100 . The back-side passivation layer  163  may include silicon nitride, silicon oxide, and/or polyimide. 
     The TSV structure  120  may vertically penetrate the substrate  100 , the lower inter-layer insulating layer  115 , and the back-side passivation layer  163 . An end portion of the TSV structure  120  may be exposed, and the other end portion of the TSV structure  120  may be in contact with the TSV pad  131 . The TSV structure  120  may penetrate the lower inter-layer insulating layer  115  to be in contact with the TSV pad  131 . The TSV structure  120  may include a TSV liner  121 , a TSV barrier layer  122 , and a TSV core  124 . The TSV core  124  may have a circular or polygonal shape in a plan view, and a pillar shape in a vertical cross-sectional view. The TSV barrier layer  122  may be formed on a side surface of the TSV core  124  to surround the TSV core  124 . The TSV liner  121  may be formed on an outer sidewall of the TSV barrier layer  122  to surround the TSV barrier layer  122 . The TSV liner  121  may include an insulating layer, such as silicon oxide or silicon nitride. The TSV barrier layer  122  may include one or more barrier metal or metal compounds, such as titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), titanium tungsten (TiW), or tungsten nitride (WN). The TSV core  124  may include copper (Cu). 
     The back-side piezoelectric pattern  170  may be formed on the back-side of the substrate  100  to surround side surfaces of the TSV structure  120 . For example, the back-side piezoelectric pattern  170  may partially surround a side surface of an end portion of the TSV core  124 . The back-side piezoelectric pattern  170 , in a plan view or a top view, may have the shape of a disk or ring surrounding the TSV core  124 . 
     Side and bottom surfaces of the back-side piezoelectric pattern  170  may be surrounded by a back-side lining layer  165 . Side surfaces of the back-side lining layer  165  may be surrounded by the back-side passivation layer  163 . For example, the back-side lining layer  165  may be interposed between the back-side piezoelectric pattern  170  and the back-side passivation layer  163 . The back-side lining layer  165  may have a shape of a single or double disk, a double disk, or a concentric circle in a plan view or a top view, and a U-shape in a vertical cross-sectional view. The back-side lining layer  165  may include a low-k insulating material, such as BLACKDIAMOND (a trade name, manufactured by Applied Materials, Inc.), SiCHO, porous SiO 2 , and/or SILK (a trade name, manufactured by Dow Chemical). In other embodiments, the back-side lining layer  165  may include silicon nitride. An end portion of the TSV structure  120 , for example, an end surface of the TSV core  124  may be co-planar with a top surface of the back-side piezoelectric pattern  170 . Moreover, the end surface of the TSV core  124  and the top surface of the back-side piezoelectric pattern  170  may be coplanar with a top surface of the back-side lining layer  165  and/or a top surface of the back-side passivation layer  163 . 
     Referring to  FIG. 1B , a semiconductor device  10   b  in accordance with an embodiment of the inventive concept may include a back-side buffer insulator  161 . The back-side buffer insulator  161  may be interposed between a back-side of the substrate  100  and the back-side passivation layer  163 . The back-side buffer insulator  161  may include silicon oxide and/or silicon nitride. The back-side buffer insulator  161  may partially surround a side surface of the back-side piezoelectric pattern  170 . For example, the back-side buffer insulator  161  may be in contact with a part of a side surface of a back-side lining layer  165 . Other elements of  FIG. 1B  are the same as or similar to elements of  FIG. 1A , and therefore, a detailed description of such elements is not repeated. 
     Referring to  FIG. 1C , a semiconductor device  10   c  in accordance with an embodiment of the inventive concept may include a back-side buffer insulator  161 . The back-side buffer insulator  161  may be interposed between a back-side of the substrate  100  and the back-side passivation layer  163 . The back-side buffer insulator  161  may include silicon oxide and/or silicon nitride. At least portions of the back-side buffer insulator  161  may be interposed between the substrate  100  and the back-side piezoelectric pattern  170 . For example, the back-side buffer insulator  161  may be in contact with a bottom surface, a side surface, and/or a top surface of a back-side lining layer  165 . Other elements of  FIG. 1C  are the same as or similar to elements of  FIG. 1A , and therefore, a detailed description of such elements is not repeated. 
     Referring to  FIG. 1D , a semiconductor device  10   d  in accordance with an embodiment of the inventive concept need not include the back-side lining layer  165 . Rather, the back-side passivation layer  163  may be in direct contact with side surfaces of the back-side piezoelectric pattern  170 . The back-side piezoelectric pattern  170  may be in direct contact with the TSV structure  120 . For example, parts of side surfaces of the TSV core  124  may be in direct contact with the back-side piezoelectric pattern  170 . Other elements of  FIG. 1D  are the same as or similar to elements of  FIG. 1A , and therefore, a detailed description of such elements is not repeated. 
     Referring to  FIG. 1E , a semiconductor device  10   e  in accordance with an embodiment of the inventive concept may include a back-side buffer insulator  161 , but need not include the back-side lining layer  165 . The back-side buffer insulator  161  may be interposed between a back-side of the substrate  100  and the back-side passivation layer  163 . The back-side buffer insulator  161  may include silicon oxide and/or silicon nitride. The back-side buffer insulator  161  may be in direct contact with the back-side piezoelectric pattern  170  to surround a part of a side surface thereof. Moreover, the back-side passivation layer  163  may be in direct contact with the back-side piezoelectric pattern  170  to surround another part of a side surface thereof. Other elements of  FIG. 1E  are the same as or similar to elements of  FIG. 1A , and therefore, a detailed description of such elements is not repeated. 
     Referring to  FIG. 1F , a semiconductor device  10   f  in accordance with an embodiment of the inventive concept may include a back-side buffer insulator  161 , but need not include the back-side lining layer  165 . The back-side buffer insulator  161  may be interposed between a back-side of the substrate  100  and the back-side passivation layer  163 . The back-side buffer insulator  161  may include silicon oxide and/or silicon nitride. The back-side buffer insulator  161  may be interposed between the substrate  100  and the back-side piezoelectric pattern  170 . For example, the back-side buffer insulator  161  may be in contact with a bottom surface, a side surface, and/or a top surface of the back-side piezoelectric pattern  170 . Other elements of  FIG. 1F  are the same as or similar to elements of  FIG. 1A , and therefore, a detailed description of such elements is not repeated. 
     In the semiconductor devices  10   a  to  10   f  in accordance with the various embodiments of the inventive concept, the TSV structure  120  can be bonded electrically and physically to another conductive element without causing damage by omitting a direct heat process and applying physical pressure on the back-side piezoelectric pattern  170 . Accordingly, since there is no heat budget applied to internal circuit elements of the semiconductor devices  10   a  to  10   f , the semiconductor devices  10   a  to  10   f  can be stably fabricated and operated. 
       FIGS. 2A to 2C  are vertical cross-sectional views showing semiconductor devices  20   a  to  20   c  in accordance with various embodiments of the inventive concept. 
     Referring to  FIG. 2A , a semiconductor device  20   a  in accordance with an embodiment of the inventive concept may include a wrapping layer  147 . The wrapping layer  147  may be formed on the front-side passivation layer  146  to surround side surfaces of the pad structure  150 . The wrapping layer  147  may include silicon oxide, silicon nitride, and/or polyimide. Other elements of  FIG. 2A  are the same as or similar to elements of  FIG. 1A , and therefore, a detailed description of such elements is not repeated. 
     Referring to  FIG. 2B , a semiconductor device  20   b  in accordance with an embodiment of the inventive concept may include a wrapping layer  147  and a front-side piezoelectric pattern  190  disposed on the front-side passivation layer  146 . The wrapping layer  147  may be formed on the front-side passivation layer  146  to surround side surfaces of the pad structure  150  and/or side surface of the front-side piezoelectric pattern  190 . 
     The front-side piezoelectric pattern  190  may be formed on a front-side of the substrate  100  and/or the front-side passivation layer  146  to surround side surfaces of the pad structure  150 . The front-side piezoelectric pattern  190  may have a disk shape or a ring shape in a plan view or a top view. 
     Side and bottom surfaces of the front-side piezoelectric pattern  190  may be surrounded by a front-side lining layer  185 . Side surfaces of the front-side lining layer  185  may be surrounded by the wrapping layer  147 . For example, a front-side lining layer  185  may be interposed between the front-side piezoelectric pattern  190  and the wrapping layer  147 . A bottom surface of the front-side lining layer  185  may be in contact with the front-side passivation layer  146 . The front-side lining layer  185  may have a single or double disk or a ring shape in a plan view or a top view, and a U shape in a vertical cross-sectional view. The front-side lining layer  185  may include a low-k insulating material, such as BLACKDIAMOND (a trade name, manufactured by Applied Materials, Inc.), SiCHO, porous SiO 2 , and/or SILK (a trade name, Dow Chemical). In other embodiments, the front-side lining layer  185  may include silicon nitride. 
     Other elements of  FIG. 2B  are the same as or similar to elements of  FIG. 1A , and therefore, a detailed description of such elements is not repeated. 
     Referring to  FIG. 2C , a semiconductor device  20   c  in accordance with an embodiment of the inventive concept may include a wrapping layer  147  and a front-side piezoelectric pattern  190  disposed on the front-side passivation layer  146 . The front-side piezoelectric pattern  190  may be formed on the front-side passivation layer  146  to directly surround side surfaces of the pad structure  150  and/or side surface of the front-side piezoelectric pattern  190 . A bottom surface of the front-side piezoelectric pattern  190  may be in direct contact with the front-side passivation layer  146 . The wrapping layer  147  may be formed on the front-side passivation layer  146  to directly surround side surfaces of the front-side piezoelectric pattern  190 . Other elements of  FIG. 2C  are the same as or similar to elements of  FIG. 1A , and therefore, a detailed description of such elements is not repeated. 
     Features of the back-side piezoelectric pattern  170  and back-side lining layers  165  of the semiconductor devices  10   a  to  10   f  illustrated and described in  FIGS. 1A to 1F , and features of the front-side piezoelectric pattern  190  and front-side lining layers  185  of the semiconductor devices  20   a  to  20   c  illustrated and described in  FIGS. 2A to 2C , can be combined in various ways. For example, the back-side piezoelectric pattern  170  and the back-side lining layer  165  illustrated in  FIGS. 2A to 2C  have the same shapes as those illustrated in  FIG. 1A , but can be substituted by the features illustrated and described in  FIGS. 1B to 1F . In other words, embodiments illustrated in  FIGS. 2A to 2C  can incorporate one or more features or elements from one or more embodiments illustrated in  FIGS. 1B to 1F . 
       FIGS. 3A to 3F  are schematic views illustrating various bonding structures  30   a  to  30   f  of TSV structures  120 U and  120 L in accordance with various embodiments of the inventive concept. 
     Referring to  FIG. 3A to 3F , the bonding structures  30   a  to  30   f  in accordance with various embodiments of the inventive concept may each include, with reference further to  FIGS. 1A to 1F , upper semiconductor devices  10 U and lower semiconductor devices  10 L, which may be bonded together. For example, the upper TSV structures  120 U of the upper semiconductor devices  10 U and lower TSV structures  120 L of the lower semiconductor devices  10 L may be directly bonded together. 
     The upper TSV structures  120 U and the lower TSV structures  120 L may respectively have a symmetrical shape or the same shape, and may be vertically aligned so as to be in direct contact with each other. In addition, upper back-side piezoelectric patterns  170 U and lower back-side piezoelectric patterns  170 L may be vertically aligned so as to be in direct contact with each other. Moreover, upper back-side lining layers  165 U and lower back-side lining layers  165 L may be vertically aligned so as to be in direct contact with each other. Since the same materials are in contact with each other, boundaries between the upper components  10 U,  120 U,  161 U,  165 U, and  170 U and the lower components  10 L,  120 L,  161 L,  165 L, and  170 L are indicated by dotted lines. The reference numerals of  FIGS. 3A to 3F  are the same as or similar to those of  FIGS. 1A to 1F  (e.g.,  163 U is similar to  163 ), and such sameness or similarity can indicate a correlation of the elements, layers, components, and the like. Therefore, a detailed description of such elements, layers, components, and the like, is not repeated. 
       FIGS. 4A to 4F  are schematic views illustrating various bonding structures  40   a  to  40   f  of TSV structures  120  and pad structures  150  in accordance with various embodiments of the inventive concept. 
     Referring to  FIGS. 4A to 4F , in the bonding structures  40   a  to  40   f  in accordance with various embodiments of the inventive concept, the TSV structures  120  and back-side piezoelectric patterns  170  of the semiconductor devices  10   a  to  10   f , and the pad structures  150  of the semiconductor devices  10   a  to  10   f , and  20   a  illustrated in  FIGS. 1A to 1F, and 2A , may be directly bonded together. For example, the back-side piezoelectric patterns  170  may be disposed on the pad core  154  of the pad structure  150 . Dotted lines represent that the same materials are in contact with each other, and solid lines represent that different materials may be in contact with each other. The reference numerals of  FIGS. 4A to 4F  are similar to or the same as those of  FIGS. 1A to 1F , and such sameness or similarity can indicate a correlation of the elements, layers, components, and the like. Therefore, a detailed description of such elements, layers, components, and the like, is not repeated. 
       FIGS. 5A to 5R  are schematic views illustrating various bonding structures  50   a  to  50   r  of TSV structures  120  and pad structures  150  in accordance with various embodiments of the inventive concept. 
     Referring to  FIG. 5A to 5R , in the bonding structures  50   a  to  50   r  in accordance with various embodiments of the inventive concept, the TSV structures  120  and back-side piezoelectric patterns  170  of the semiconductor devices  10   a  to  10   f  illustrated in  FIGS. 1A to 1F , and the pad structures  150  and front-side piezoelectric patterns  190  of the semiconductor devices  20   a  to  20   c  illustrated in  FIGS. 2A to 2C , are bonded in various ways. The TSV structures  120  and the pad structures  150  are assumed and described as being vertically aligned with each other. For example, it is assumed and described that the TSV cores  124  of the TSV structures  120  are aligned with the pad cores  154  of the pad structures  150 , and the back-side piezoelectric patterns  170  are aligned with the front-side piezoelectric patterns  190 . 
     The reference numerals of  FIGS. 5A to 5R  are similar to or the same as those of  FIGS. 1A to 1F  and/or  FIGS. 2A to 2C , and such sameness or similarity can indicate a correlation of the elements, layers, components, and the like. Therefore, a detailed description of such elements, layers, components, and the like, is not repeated. 
       FIGS. 6A and 6B  show bonding structures  60   a  and  60   b  of the pad structures  150  in accordance with embodiments of the inventive concept. 
     Referring to  FIGS. 6A and 6B , in the bonding structures  60   a  and  60   b  of the pad structures  150  in accordance with the embodiments of the inventive concept, with reference further to  FIGS. 2A to 2C , upper pad structures  150 U of the upper semiconductor devices  10 U and lower semiconductor devices  10 L of the lower pad structures  150 L may be respectively bonded together. 
     The reference numerals of  FIGS. 6A and 6B  are similar to or the same as those of  FIGS. 2A to 2C  (e.g.,  150 U is similar to  150 ), and such sameness or similarity can indicate a correlation of the elements, layers, components, and the like. Therefore, a detailed description of such elements, layers, components, and the like, is not repeated. 
       FIGS. 7A to 7T  are vertical cross-sectional views showing a method of fabricating a semiconductor device in accordance with an embodiment of the inventive concept. 
     Referring to  FIG. 7A , the method may include forming transistors  110  and a lower inter-layer insulating layer  115  on a substrate  100 . The substrate  100  may include a single-crystalline silicon bulk wafer, a compound semiconductor wafer, or a silicon-on-insulator (SOI) wafer. The transistors  110  may include gate stacks  110   g  and/or source/drain areas  110   s  and  110   d . The gate stack  110   g  may selectively include the gate insulating layer  111 , the gate electrode  112 , the gate capping layer  113 , and/or the gate spacer  114 . The gate insulating layer  111  may include silicon oxide or a metal oxide. The gate electrode  112  may include doped silicon, a silicide, a metal, or a metal compound. The gate capping layer  113  may include silicon nitride. The gate spacer  114  may include silicon oxide and/or silicon nitride. The source/drain areas  110   s  and  110   d  may include one of boron (B), phosphorus (P), and arsenic (As) injected into the substrate  100 . The source/drain areas  110   s  and  110   d  may include a metal silicide. The lower inter-layer insulating layer  115  may include silicon oxide. 
     Referring to  FIG. 7B , the method may include forming a TSV hole  120   h . The TSV hole  120   h  may vertically pass through the lower inter-layer insulating layer  115 , and extend into the substrate  100 . A bottom of the TSV hole  120   h  may be located inside the substrate  100 . 
     Referring to  FIG. 7C , the method may include forming a TSV liner  121 , a TSV barrier layer  122 , and a TSV seed layer  123  in the TSV hole  120   h . The TSV liner  121  may be formed using a sub-atmosphere chemical vapor deposition (SACVD) process or an atomic layered deposition (ALD) process. The TSV liner  121  may include silicon oxide and/or silicon nitride. The TSV bather layer  122  may be formed using a physical vapor deposition (PVD) process such as a sputtering process. The TSV barrier layer  122  may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), a titanium tungsten alloy (TiW), or another bather metal, an alloy, and/or metal compound. The TSV seed layer  123  may be formed using a PVD process such as a sputtering process. The TSV seed layer  123  may include copper, nickel, or another seed metal. 
     Referring to  FIG. 7D , the method may include forming a TSV core  124  and exposing the lower inter-layer insulating layer  115 . The TSV core  124  may be formed using a plating process. The TSV core  124  may include copper. For example, when the TSV seed layer  123  and the TSV core  124  include the same metal, a boundary therebetween may disappear. Accordingly, the boundary between the TSV seed layer  123  and the TSV core  124  is indicated by a dotted line in  FIG. 7D . The boundary between the TSV seed layer  123  and the TSV core  124  is omitted in drawings subsequent to  FIG. 7D . 
     The TSV liner  121 , the TSV bather layer  122 , the TSV seed layer  123 , and the TSV core  124 , which are disposed on the lower inter-layer insulating layer  115  can be removed by performing a planarization process such as a chemical mechanical polishing (CMP) process. In this process, the TSV structure  120  including the TSV liner  121 , TSV barrier layer  122 , TSV seed layer  123 , and TSV core  124  may be formed. 
     Referring to  FIG. 7E , the method may include forming a lower metal interconnection  130  and an intermediate inter-layer insulating layer  135  on the lower inter-layer insulating layer  115 . The lower metal interconnection  130  may include the TSV pad  131  and the lower metal lines  133 . For example, the lower metal interconnection  130  may include tungsten, copper, aluminum, or another metal. The intermediate inter-layer insulating layer  135  may include silicon oxide. 
     Referring to  FIG. 7F , the method may include forming a lower via plug  132  in the intermediate inter-layer insulating layer  135 , and forming an upper metal interconnection  140  and an upper inter-layer insulating layer  145  on the intermediate inter-layer insulating layer  135 . The lower via plug  132  may vertically penetrate the intermediate inter-layer insulating layer  135  to be connected to the TSV pad  131 . The upper metal interconnection  140  may include an inter-via pad  131  and upper metal lines  143 . The inter-via pad  141  may be aligned with and connected to the lower via plug  132 . The lower via plug  132  and the upper metal interconnection  140  may include tungsten, copper, aluminum, or another metal. The upper inter-layer insulating layer  145  may include silicon oxide. 
     Referring to  FIG. 7G , the method may include forming an upper via plug  142  in the upper inter-layer insulating layer  145 , and forming a front-side passivation layer  146  on the upper inter-layer insulating layer  145 . The upper via plug  142  may vertically pass through the upper inter-layer insulating layer  145  to be in contact with the inter-via pad  141 . The upper via plug  142  may include tungsten, copper, aluminum, or another metal. The front-side passivation layer  146  may include a pad hole PH exposing the upper via plug  142 . The front-side passivation layer  146  may include silicon oxide and/or silicon nitride. 
     Referring to  FIG. 7H , the method may include forming a pad barrier layer  152  and a pad seed layer  153  in the pad hole PH and on the front-side passivation layer  146 . The pad barrier layer  152  may be formed using a PVD process such as a sputtering process. The pad barrier layer  152  may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), a titanium tungsten alloy (TiW), or another barrier metal, an alloy and/or a metal compound. The pad seed layer  153  may be formed using a PVD process such as a sputtering process. The TSV seed layer  123  may include copper, nickel, or another seed metal. 
     Referring to  FIG. 7I , the method may include forming a pad mask PM on the pad seed layer  153 . The pad mask PM may include a mask hole MH, which is aligned with the upper via plug  142  and/or the pad hole PH, and exposes the pad seed layer  153 . The pad mask PM may include a photoresist or an organic polymeric material. 
     Referring to  FIG. 7J , the method may include forming a pad core  154  in the mask hole MH. The pad core  154  may be formed by a plating method. The pad core  154  may include copper. When the pad seed layer  153  and the pad core  154  include the same metal, a boundary therebetween may disappear. In order to exemplarily show that the pad seed layer  153  and the pad core  154  can include a different metal, the boundary between the pad seed layer  153  and the pad core  154  is shown in  FIG. 7J . 
     Referring to  FIG. 7K , the method may include removing the pad mask PM to expose the pad seed layer  153  and the pad barrier layer  152 . The pad mask PM may be removed by performing a sulfuric acid boiling process or an ashing process using oxygen plasma. 
     Referring to  FIG. 7L , the method may include removing the exposed pad seed layer  153  and the pad barrier layer  152 . The pad seed layer  153  may be removed by performing a wet etching process using a chemical solution including a hydrogen peroxide solution, citric acid, and water. The pad barrier layer  152  may be removed by performing a wet etching process using a chemical solution including a hydrogen peroxide solution, KOH, and water. Through the above-described processes, the pad structure  150  including the pad barrier layer  152 , pad seed layer  153 , and pad core  154  may be formed. 
     Referring to  FIG. 7M , the method may include overturning the substrate  100 . The pad structure  150  may be supported and protected by a wafer support carrier (WSC). 
     Referring to  FIG. 7N , the method may include recessing a back-side of the substrate  100  to expose an end portion of the TSV structure  120 . For example, the end portion of the TSV core  124  may protrude from the back-side of the substrate  100 . 
     Referring to  FIG. 7O , the method may include forming a back-side passivation layer  163  on the back-side of the substrate  100 . The back-side passivation layer  163  may include silicon oxide and/or silicon nitride formed in a CVD process. In other embodiments, an additional insulating layer may be interposed between the back-side of the substrate  100  and the back-side passivation layer  163 . 
     Referring to  FIG. 7P , the method may include forming a disk-shaped via-surrounding hole VSH by removing the back-side passivation layer  163  around the TSV core  124 . Surfaces of the substrate  100 , the TSV liner  121 , and/or the TSV barrier layer  122  may be exposed on a bottom of the via-surrounding hole VSH. 
     Referring to  FIG. 7Q , the method may include forming a back-side lining layer  165  on inner walls and bottom surface of the via-surrounding hole VSH, and a top surface of the back-side passivation layer  163 , using a CVD or ALD process. In some embodiments, the back-side lining layer  165  may be conformally formed on inner walls and bottom surface of the via-surrounding hole VSH. The back-side lining layer  165  may include a low-k insulating material, such as BLACKDIAMOND (a trade name, manufactured by Applied Materials, Inc.), SiCHO, porous SiO 2 , and SILK (a trade name, Dow Chemical). In other embodiments, the back-side lining layer  165  may include silicon nitride. 
     Referring to  FIG. 7R , the method may include forming a back-side piezoelectric material layer  170   a  to fill the via-surrounding hole VSH. The back-side piezoelectric material layer  170   a  may be formed in a variety of processes, such as a deposition process, a spin coating process, a dispensing process, and a pasting process, depending on a material. For example, the back-side piezoelectric material layer  170   a  may include one of a synthetic crystal materials including quartz analogic crystal, such as gallium orthophosphate (GaPO 4 ) or Langasite (La 3 Ga 5 SiO 14 ), a synthetic ceramic, such as barium titanate (BaTiO 3 ), potassium niobate (KNbO 3 ), lithium niobate (LiNbO 3 ), lithium tantalite (LiTaO 3 ), sodium tungstate (Na 2 WO 3 ), zinc oxide (ZnO), or barium sodium niobate (Ba 2 NaNb 5 O 5 ), a lead-free ceramic, such as sodium potassium niobate ((K,Na)NbO 3 ), bismuth ferrite (BiFeO 3 ), sodium niobate (NaNbO 3 ), bismuth titanate (Bi 4 Ti 3 O 12 ), or sodium bismuth titanate (Na 0.5 Bi 0.5 TiO 3 ), a polymeric material such as polyvinylidene fluoride (—(C 2 H 2 F 2 )N—) (PVDF), or an organic nanostructure such as self-assembled diphenylalanine peptide nanotubes (PNTs). 
     Referring to  FIG. 7S , the method may include performing an ion-implantation process to inject ions into the back-side piezoelectric material layer  170   a . The ions may include one or more among boron (B), phosphorus (P), and arsenic (As). For example, boron, phosphorus, or arsenic in an ionic state may be injected into the back-side piezoelectric material layer  170   a  using an electric field. In other embodiments, the method may include injecting ions into the back-side piezoelectric material layer  170   a  by performing a diffusion process using a gas source, without using the ion-implantation process. For example, the method may include loading a wafer having the back-side piezoelectric material layer  170   a  in a vacuum chamber, supplying one of di-borane (B 2 H 6 ), boron tribromide (BBr 3 i), phosphine (PH 3 ), phosphorous oxychloride (POCl 3 ), and arsenic trihydrogen (AsH 3 ) into the vacuum chamber, and diffusing the boron, phosphorus, or arsenic in the back-side piezoelectric material layer  170   a  by heating. 
     In still other embodiments, referring to  FIG. 7T , the method may include forming a diffusion source layer  175  containing boron, phosphorus, and/or arsenic, on the back-side piezoelectric material layer  170   a . The method may further include diffusing the boron, phosphorus, and/or arsenic in the diffusion source layer  175  into the back-side piezoelectric material layer  170   a  by performing a diffusion process. The diffusion source layer  175  may include boron silicate glass (BSG), phosphorous silicate glass (PSG), boron phosphorous silicate glass (BPSG), BN, P 2 O 5 , or Al 2 O 3  in a solid state, or AsCl 3  in a liquid state. 
     Next, referring to  FIG. 1A , the method may include removing the back-side piezoelectric material layer  170   a  on the back-side passivation layer  163  by performing a planarization process such as an etchback or CMP process, to form the back-side piezoelectric pattern  170  surrounding the TSV core  124 . In other embodiments, referring further to  FIG. 7T , the method may include removing the diffusion source layer  175  on the back-side piezoelectric material layer  170   a  by performing a planarization process. 
       FIGS. 8A to 8C  are vertical cross-sectional views showing a method of fabricating a semiconductor device in accordance with an embodiment of the inventive concept. Referring to  FIG. 8A , the method may include exposing the TSV structure  120  by performing the processes described with reference to  FIGS. 7A to 7N , and forming the back-side buffer insulator  161  and the back-side passivation layer  163  on the back-side of the substrate  100 . The back-side buffer insulator  161  may include silicon oxide, and the back-side passivation layer  163  may include silicon oxide and/or silicon nitride. 
     Referring to  FIG. 8B , the method may include forming a disk-shaped via-surrounding hole VSH by removing the back-side passivation layer  163  and the back-side buffer insulator  161  around the TSV core  124 . Surfaces of the substrate  100 , the TSV liner  121 , and/or the TSV bather layer  122  may be exposed on a bottom of the via-surrounding hole VSH. The back-side buffer insulator  161  may be exposed on an inner wall of the via-surrounding hole VSH. 
     Referring to  FIG. 8C , the method may include forming the back-side lining layer  165  on the inner wall and bottom of the via-surrounding hole VSH, and a top surface of the back-side passivation layer  163 , by performing the processes described with reference to  FIGS. 7Q to 7R , and forming the back-side piezoelectric material layer  170   a  to fill the via-surrounding hole VSH. Next, the method may further include injecting ions into the back-side piezoelectric material layer  170   a  by performing the processes described with reference to  FIG. 7S or 7T . Next, referring to  FIG. 1B , the method may include removing the back-side piezoelectric material layer  170   a  on the back-side passivation layer  163  by performing a planarization process such as an etchback or CMP process to form the back-side piezoelectric pattern  170  surrounding the TSV core  124 . The method may include, referring further to  FIG. 7T , removing the diffusion source layer  175  on the back-side piezoelectric material layer  170   a.    
       FIGS. 9A and 9B  are vertical cross-sectional views showing a method of fabricating a semiconductor device in accordance with an embodiment of the inventive concept. Referring to  FIG. 9A , the method may include performing the processes described with reference to  FIGS. 7A to 7N, and 8A , and forming a disk-shaped via-surrounding hole VSH by removing the back-side passivation layer  163  and the back-side buffer insulator  161  around the TSV core  124 . The back-side buffer insulator  161  may be exposed on a bottom of the via-surrounding hole VSH. 
     Referring to  FIG. 9B , the method may include forming a back-side lining layer  165  on inner walls and bottom of the via-surrounding hole VSH, and a top surface of the back-side passivation layer  163  by performing the processes described with reference to  FIGS. 7Q to 7R , and forming a back-side piezoelectric material layer  170   a  to fill the via-surrounding hole VSH. Next, the method may include injecting ions into the back-side piezoelectric material layer  170   a  by performing the processes described with reference to  FIG. 7S or 7T . Next, referring to  FIG. 1C , the method may include removing the back-side piezoelectric material layer  170   a  on the back-side passivation layer  163  by performing a planarization process such as an etchback or CMP process, to form a back-side piezoelectric pattern  170  surrounding the TSV core  124 . Referring further to  FIG. 7T , the method may include removing the diffusion source layer  175  on the back-side piezoelectric material layer  170   a.    
       FIG. 10  is a vertical cross-sectional view showing a method of fabricating a semiconductor device in accordance with an embodiment of the inventive concept. Referring to  FIG. 10 , the method may include performing the processes described with reference to  FIGS. 7A to 7P , and forming a back-side piezoelectric material layer  170   a  on the via-surrounding hole VSH and the back-side passivation layer  163 . For example, the back-side buffer insulator  161  shown in  FIG. 7Q  may be omitted. Next, the method may further include injecting ions into the back-side piezoelectric material layer  170   a  by performing the processes described with reference to  FIG. 7S or 7T , and removing the back-side piezoelectric material layer  170   a  on the back-side passivation layer  163  by performing a planarization process described with reference to  FIG. 1D , to form a back-side piezoelectric pattern  170  surrounding the TSV core  124 . 
       FIG. 11  is a vertical cross-sectional view showing a method of fabricating a semiconductor device in accordance with an embodiment of the inventive concept. Referring to  FIG. 11 , the method may include forming a via-surrounding hole VSH by performing the processes described with reference to  FIGS. 7A to 7N, 8A, and 8C , and then forming a back-side piezoelectric material layer  170   a  to fill the via-surrounding hole VSH. Next, the method may include injecting ions into the back-side piezoelectric material layer  170   a  by performing the processes described with reference to  FIG. 7S or 7T , and removing the back-side piezoelectric material layer  170   a  on the back-side passivation layer  163  by performing a planarization process described with reference to  FIG. 1E , to form a back-side piezoelectric pattern  170  surrounding the TSV core  124 . 
       FIG. 12  is a vertical cross-sectional view showing a method of fabricating a semiconductor device in accordance with an embodiment of the inventive concept. Referring to  FIG. 12 , the method may include forming a via-surrounding hole VSH by performing the processes described with reference to  FIGS. 7A to 7N, 9A, and 9B , and then forming a back-side piezoelectric material layer  170   a  to fill the via-surrounding hole VSH. Next, the method may include injecting ions into the back-side piezoelectric material layer  170   a  by performing the processes described with reference to  FIG. 7S or 7T , and removing the back-side piezoelectric material layer  170   a  on the back-side passivation layer  163  by performing a planarization process described with reference further to  FIG. 1F , to form a back-side piezoelectric pattern  170  surrounding the TSV core  124 . 
       FIG. 13  is a vertical cross-sectional view showing a method of fabricating a semiconductor device in accordance with an embodiment of the inventive concept. Referring to  FIG. 13 , the method may include forming a pad structure  150  by performing the processes described with reference to  FIGS. 7A to 7L , and then forming a wrapping layer  147 . The wrapping layer  147  may include an insulating material, such as silicon oxide, silicon nitride, and polyimide. Next, referring further to  FIG. 2A , the method may include performing a planarization process such as a CMP process to expose a surface of the pad structure  150 , and performing the processes described with reference to  FIGS. 7M to 7T . 
       FIGS. 14A and 14B  are vertical cross-sectional views showing a method of fabricating a semiconductor device in accordance with an embodiment of the inventive concept. Referring to  FIG. 14A , the method may include forming a pad structure  150  by performing the processes described with reference to  FIGS. 7A to 7L , forming a wrapping layer  147  by performing the processes described with reference to  FIG. 13 , exposing a surface of the pad structure  150 , and forming a pad-surrounding hole PSH exposing the pad structure  150 . 
     Referring to  FIG. 14B , the method may include forming a front-side lining layer  185  in the pad-surrounding hole PSH, and forming a front-side piezoelectric material layer  190   a  to fill the pad-surrounding hole PSH. In some embodiments, the front-side lining layer  185  may be conformally formed in the pad-surrounding hole PSH. The front-side piezoelectric material layer  190   a  may include the same material as the above-described back-side piezoelectric material layer  170   a . Next, referring further to  FIG. 2B , the method may include performing a planarization process such as a CMP process to expose a surface of the pad structure  150 , and performing the processes described with reference to  FIGS. 7M to 7T . 
       FIG. 15  is a vertical cross-sectional view showing a method of fabricating a semiconductor device in accordance with an embodiment of the inventive concept. Referring to  FIG. 15 , the method may include forming a pad structure  150  by performing the processes described with reference to  FIGS. 7A to 7L , forming a wrapping layer  147  by performing the processes described with reference to  FIG. 13 , exposing the pad structure  150 , forming a pad-surrounding hole PSH exposing the pad structure  150  by performing the process described with reference to  FIG. 14A , and forming a front-side piezoelectric material layer  190   a  to fill the pad-surrounding hole PSH. Next, the method may include performing a planarization process such as a CMP process described with reference further to  FIG. 2C  to expose a surface of the pad structure  150 , and performing the processes described with reference to  FIGS. 7M to 7T . 
       FIGS. 16A to 16F  are schematic views illustrating various bonding structures  70   a  to  70   f  of metal lines  220 U and  220 L in accordance with various embodiments of the inventive concept. 
     Referring to  FIGS. 16A to 16F , the bonding structure  70   a  to  70   f  in accordance with various embodiments of the inventive concept may include an upper semiconductor device  12 U and a lower semiconductor device  12 L, which can be bonded together. For example, an upper device metal pattern  220 U of the upper semiconductor device  12 U and a lower device metal pattern  220 L of the lower semiconductor device  12 L may be directed bonded together. 
     The upper semiconductor device  12 U may include an upper device passivation layer  263 U, an upper device metal pattern  220 U, and an upper device piezoelectric pattern  270 U, which are disposed on an upper device substrate  200 U. The lower semiconductor device  12 L may include a lower device passivation layer  263 L, a lower device metal pattern  220 L, and a lower device piezoelectric pattern  270 L, which are disposed on a lower device substrate  200 L. The upper device passivation layer  263 U may define the upper device metal pattern  220 U, and the lower device passivation layer  263 L may define the lower device metal pattern  220 L. For example, the upper device passivation layer  263 U may surround side surfaces of the upper device metal pattern  220 U, and the lower device passivation layer  263 L may surround side surfaces of the lower device metal pattern  220 L. 
     The upper device piezoelectric pattern  270 U surrounding the side surfaces of the upper device metal pattern  220 U may be formed between the upper device passivation layer  263 U and the upper device metal pattern  220 U. The lower device piezoelectric pattern  270 L surrounding the side surfaces of the lower device metal pattern  220 L may be formed between the lower device passivation layer  263 L and the lower device metal pattern  220 L. 
     Referring further to  FIGS. 16A, 16B, and 16C , the upper semiconductor device  12 U may include an upper device lining layer  265 U surrounding side and bottom surfaces of the upper device piezoelectric pattern  270 U. The lower semiconductor device  12 L may include a lower device lining layer  265 L surrounding side and bottom surfaces of the lower device piezoelectric pattern  270 L. 
     Referring further to  FIGS. 16B, 16C, 16E, and 16F , the upper semiconductor device  12 U may further include an upper device buffer insulating layer  261 U between the upper device substrate  200 U and the upper device passivation layer  263 U. The lower semiconductor device  12 L may further include a lower device buffer insulating layer  261 L between the lower device substrate  200 L and the lower device passivation layer  263 L. 
     Referring to  FIG. 16B , the upper device buffer insulating layer  261 U may be in contact with a side surface of the upper device lining layer  265 U. The lower device buffer insulating layer  261 L may be in contact with a side surface of the lower device lining layer  265 L. 
     Referring to  FIG. 16C , the upper device buffer insulating layer  261 U may be in contact with a bottom surface of the upper device lining layer  265 U. The lower device buffer insulating layer  261 L may be in contact with a bottom surface of the lower device lining layer  265 L. 
     Referring to  FIG. 16E , the upper device buffer insulating layer  261 U may be in contact with a side surface of the upper device piezoelectric pattern  270 U. The lower device buffer insulating layer  261 L may be in contact with a side surface of the lower device piezoelectric pattern  270 L. 
     Referring to  FIG. 16F , the upper device buffer insulating layer  261 U may be in contact with a bottom surface of the upper device piezoelectric pattern  270 U. The lower device buffer insulating layer  261 L may be in contact with a bottom surface of the lower device piezoelectric pattern  270 L. 
     The bonding structures  70   a  to  70   f  described in  FIGS. 16A to 16F  can be more specifically understood with reference to the various embodiments described in the specification and drawings. 
       FIGS. 17A to 17F  are schematic views illustrating bonding structures  80   a  to  80   f  of metal lines  320 U and  320 L in accordance with various embodiments of the inventive concept. 
     Referring to  FIGS. 17A to 17F , the bonding structures  80   a  to  80   f  in accordance with various embodiments of the inventive concept may include an upper semiconductor device  13 U and a lower semiconductor device  13 L, which can be bonded together. For example, an upper device metal pattern  320 U of the upper semiconductor device  13 U and a lower device metal pattern  320 L of the lower semiconductor device  13 L may be directly bonded together. 
     The upper semiconductor device  13 U may include an upper device passivation layer  363 U and an upper device metal pattern  320 U, which are disposed on an upper device substrate  300 U. The lower semiconductor device  13 L may include a lower device passivation layer  363 L, a lower device metal pattern  320 L, and a lower device piezoelectric pattern  370 L, which are disposed on a lower device substrate  300 L. 
     The lower device piezoelectric pattern  370 L surrounding the lower device metal pattern  320 L may be formed between the lower device passivation layer  363 L and the lower device metal pattern  320 L. 
     Referring further to  FIGS. 17A, 17B, and 17C , the lower semiconductor device  13 L may include a lower device lining layer  365 L surrounding side and bottom surfaces of the lower device piezoelectric pattern  370 L. 
     Referring further to  FIGS. 17B, 17C, 17E, and 17F , the lower semiconductor device  13 L may further include a lower device buffer insulating layer  361 L between the lower device substrate  300 L and the lower device passivation layer  363 L. 
     Referring to  FIG. 17B , the lower device buffer insulating layer  361 L may be in contact with a side surface of the lower device lining layer  365 L. 
     Referring to  FIG. 17C , the lower device buffer insulating layer  361 L may be in contact with a bottom surface of the lower device lining layer  365 L. 
     Referring to  FIG. 17E , the lower device buffer insulating layer  361 L may be in contact with the side surface of the lower device piezoelectric pattern  370 L. 
     Referring to  FIG. 17F , the lower device buffer insulating layer  361 L may be in contact with the bottom surface of the lower device piezoelectric pattern  370 L. 
     The bonding structures  80   a  to  80   f  described in  FIGS. 17A to 17F  can be more specifically understood with reference to the various embodiments described in the specification and drawings. 
       FIG. 18A  is a diagram showing a semiconductor module  2200  in accordance with an embodiment of the inventive concept. Referring to  FIG. 18A , the semiconductor module  2200  in accordance with the embodiment of the inventive concept may include a processor  2220  installed on a semiconductor module substrate  2210 , and semiconductor packages  2230 . The processor  2220  or the semiconductor packages  2230  may include at least one of the semiconductor devices  10   a  to  10   f , and  20   a  to  20   c , or the bonding structures  30   a  to  30   f ,  40   a  to  40   f ,  50   a  to  50   r ,  60   a  and  60   b ,  70   a  to  70   f , and  80   a  to  80   f , in accordance with various embodiments of the inventive concept. Input/output terminals  2240  may be arranged on at least one side of the module substrate  2210 . 
       FIGS. 18B and 18C  are block diagrams schematically showing electronic systems  2300  and  2400  in accordance with embodiments of the inventive concept. Referring to  FIG. 18B , the electronic system  2300  in accordance with the embodiment of the inventive concept may include a body  2310 , a display unit  2360 , and an external apparatus  2370 . The external apparatus  2370  may be connected to the body  2310  via an external conductor  2380  such as a bus, a wire, or the like. 
     The body  2310  may include a microprocessor unit  2320 , a power supply  2330 , a function unit  2340 , and/or a display controller unit  2350 . The body  2310  may include a system board or motherboard having a printed circuit board (PCB), and/or a case. The microprocessor unit  2320 , the power supply  2330 , the function unit  2340 , and the display controller unit  2350  may be installed or arranged on an upper surface or an inside of the body  2310 . A display unit  2360  may be arranged inside or outside of the body  2310 . 
     The display unit  2360  may display an image processed by the display controller unit  2350 . For example, the display unit  2360  may include a liquid crystal display (LCD), an active matrix organic light emitting diode (AMOLED), or various display panels. The display unit  2360  may include a touch-screen. Accordingly, the display unit  2360  may have an input/output function. 
     The power supply  2330  may supply a current or voltage to the microprocessor unit  2320 , the function unit  2340 , and the display controller unit  2350 , etc. The power supply  2330  may include a rechargeable battery, a socket for the battery, or a voltage/current converter. 
     The microprocessor unit  2320  may receive a voltage from the power supply  2330  to control the function unit  2340  and the display unit  2360 . For example, the microprocessor unit  2320  may include a CPU or an application processor (AP). 
     The function unit  2340  may perform various functions. For example, the function unit  2340  may include a touch-pad, a touch-screen, a volatile/nonvolatile memory, a memory card controller, a camera, a light, an audio and video playback processor, a wireless transmission/reception antenna, a speaker, a microphone, a USB port, and other units having various functions. 
     The microprocessor unit  2320  or the function unit  2340  may include at least one of the semiconductor devices  10   a  to  10   f , and  20   a  to  20   c , or the bonding structures  30   a  to  30   f ,  40   a  to  40   f ,  50   a  to  50   r ,  60   a  and  60   b ,  70   a  to  70   f , and  80   a  to  80   f  in accordance with various embodiments of the inventive concept. 
     Referring to  FIG. 18C , the electronic system  2400  may include a microprocessor  2414 , a memory system  2412 , and a user interface  2418 , which perform data communication using a bus  2420 . The microprocessor  2414  may include a CPU or AP. The electronic system  2400  may further include a RAM  2416 , which directly communicates with the microprocessor  2414 . The microprocessor  2414  and/or the RAM  2416  can be assembled in a single package. The user interface  2418  may be used to input/output information to/from the electronic system  2400 . For example, the user interface  2418  may include a touch-pad, a touch-screen, a keyboard, a scanner, a voice detector, a cathode ray tube (CRT) monitor, an LCD, an AMOLED, a plasma display panel (PDP), a printer, a light, or other various input/output devices. The memory system  2412  may store codes for operating the microprocessor  2414 , data processed by the microprocessor  2414 , or external input data. The memory system  2412  may include a memory controller, a hard-disk, or a solid state drive (SSD). The microprocessor  2414 , the RAM  2416 , and/or the memory system  2412  may include at least one of the semiconductor devices  10   a  to  10   f , and  20   a  to  20   c , or the bonding structures  30   a  to  30   f ,  40   a  to  40   f ,  50   a  to  50   r ,  60   a  and  60   b ,  70   a  to  70   f , and  80   a  to  80   f  in accordance with various embodiments of the inventive concept. 
     Semiconductor devices in accordance with various embodiments of the inventive concept may include piezoelectric patterns that surround through-silicon-vias or pads for bonding. Accordingly, in the semiconductor devices in accordance with the embodiments of the inventive concept, a through-silicon-via and/or a pad can be directly bonded to another through-silicon-via and/or another pad by applying pressure only, and without performing a heat process. Since the semiconductor devices in accordance with the embodiments of the inventive concept can be connected or bonded to each other with no heat budget, performance and life of the semiconductor devices is maintained. 
     The foregoing is illustrative of embodiments and is not to be construed as limiting thereof. Although a few embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible without materially departing from the novel teachings and advantages. Accordingly, all such modifications are intended to be included within the scope of this inventive concept as defined in the claims. In the claims, means-plus-function clauses are intended to cover the structures described herein as performing the recited function, and not only structural equivalents but also equivalent structures.