Patent Publication Number: US-9847712-B2

Title: Fault control for switched capacitor power converter

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This application is a National Stage of International Application No. PCT/US2013/078243 filed on Dec. 30, 2013, which is a continuation of U.S. application Ser. No. 13/838,681 filed Mar. 15, 2013, now U.S. Pat. No. 8,619,445, issued on Dec. 31, 2013. The contents of the aforementioned applications are hereby incorporated by reference in their entirety. 
    
    
     BACKGROUND 
     This invention relates to protection of switched capacitor power converters. 
     Various configurations of switched capacitor power conversion circuits provide voltage conversion (i.e., step up, step down, or bidirectional) between a high side voltage and a low side voltage through controlled transfers of charge between capacitors in the circuit. A Dickson charge pump is an example of such a conversion circuit. Control of the charge transfer between the capacitors generally makes use of circuit elements that act as “switches,” for example, diodes or FET transistors. 
     Some configurations of switch elements and capacitors limit the typical maximum voltage across the switch elements in normal operation. Such limited voltages permit use of switch elements that do not necessarily have to accommodate the full high side voltage or the difference between the high side and the low side voltages, thereby permitting use “low voltage” elements. For example, in a conventional Dickson charge pump performing a conversion between 20 volts and 5 volts in 4 stages, switch elements typically experience a maximum of 10 volts in operation and therefore require a rating (e.g., breakdown voltage rating) of 10 volts. 
     Charge pumps step up or step down an input voltage by storing a fraction of the input voltage across each capacitor. As the magnitude of the voltage conversion increases, the number of capacitors required increases. Switches on both terminals of each capacitor are necessary to perform the charge transfer, as well as configure the charge pump to provide a desired voltage conversion ratio. 
       FIGS. 1A-1B  show two charge pumps. The first in  FIG. 1A  is a 1:3 step-down configuration and the second in  FIG. 1B  is a 3:1 step-up configuration. The voltage labels on each node have two values, one for each stage of operation: voltage value during stage 1/voltage value during stage 2. Each switch needs to be turned on and off in a non-overlapping manner during stage 1 or stage 2. For either the step-up or step-down, the node labeled VX is the lowest charge pump voltage level: VX is typically the output of a step-down, and conversely the input of a step-up. VX also sets the unit voltage drop across each switch when the switch is off: the switches at the bottom of the capacitors each see a maximum voltage drop of VX, while the switches at the top of each capacitor see a maximum voltage drop of 2VX. This means that the transistors selected as switches at the top of the capacitors require a drain-to-source breakdown voltage (BV DSS ) above 2VX to avoid damage. In general the higher the BV DSS  of a MOS transistor, the larger the transistor area and capacitances for a given on-resistance which increases die cost and switching power loss. Therefore, it is desirable to use a transistor whose BV DSS  is close to the maximum voltage drop the transistor needs to support. 
       FIG. 2  shows an interleaved version of the step-down charge pump in  FIG. 1A  where the switches at the top of each capacitor now see a maximum voltage drop of only VX. It should be noted that the  FIG. 2  interleaved topology may reduce the maximum voltage drop seen across each switch, as simply cascoding each of the top switches (or using two series-connected transistors per top switch), although other approaches may also achieves this purpose. For most CMOS processes, the efficiency and die area gains from using the same low BV DSS  transistors are still advantageous enough to justify the higher transistor count and complexity. The complexity arises from having to control and operate these low-voltage transistors at various common-mode voltage multiples of VX. Referring to  FIG. 2  as an example, the switch that connects the top-most capacitor to VIN at 6V can be a 3.3V transistor since the transistor sees 2V differentially across its drain-to-source terminals when not conducting, despite the absolute voltage levels at the transistor drain and source terminals (4V or 6V depending on the stage of operation; 4V being the common-mode voltage level for this switch) exceeding 3.3V. This is because BV DSS  is a differential voltage constraint across the transistor drain-to-source terminal, rather than an absolute constraint at each of the transistor terminals. Although the drain and source terminals each have an absolute breakdown voltage to the silicon substrate, these absolute breakdown voltages are typically much higher than BV DSS  and therefore allow the transistor to be operated at a common-mode voltage level above B VDSS . 
     In addition to BV DSS , another differential voltage constraint for a MOS transistor is the maximum gate-to-source voltage (V GSmax ) which is determined by the gate-oxide breakdown voltage. Modern CMOS processes with small geometries and low-voltage transistors require thinner gate oxides to maintain performance, which results in lower V GSmax  ratings as well. This further complicates the design of a high voltage conversion ratio charge pump using low-voltage transistor switches, since care must be taken to avoid exceeding both gate-to-source and drain-to-source voltage constraints during switch operation. 
     Commonly available low-voltage transistor flavors such as the 1.8V, 3.3V and occasionally 5V transistors, usually specify a V GSmax  rating equal to the maximum operating drain-to-source voltage rating, V DSmax , where V DSmax &lt;BV DSS . For applications where the minimum VX voltage in the operating range is sufficiently above the transistor threshold voltage, it becomes practical and convenient to use the same VX voltage level for the transistor gate drivers, instead of generating separate internal supply rails for this purpose. This is due to the fact that a VX-level voltage is already generated and supported between each non-switching node (e.g. VIN, VX, 4V node between the capacitors in  FIG. 2 ) in the interleaved charge pump, inherent to the charge pump operation itself. Therefore, the gate driver for each transistor can be levelshifted to the common-mode voltage level of that transistor, use the same low-voltage transistors, and drive the transistor gate-to-source voltage between 0V and VX, as shown in  FIG. 3 . The nth section of an interleaved charge pump showing a pair of switches at the top of a capacitor, where n is an integer. An equivalent transistor-level representation is shown on the right with the gate drivers used to turn the transistors on and off. The transistors and the gate driver circuitry see a maximum of a VX voltage across them. The high-side switch shown is a PMOS transistor, but can also be an NMOS if its gate driver was bootstrapped between the capacitor node shown and an adjacent capacitor node that switches between V n+1  and V n+2    
     Charge-pumps step-down or step up an input voltage by storing a portion or multiples of the input voltage across capacitors. As the magnitude of the transformation increases, the number of capacitors used increases. Each capacitor helps create a unique intermediate voltage during part of the operating cycle. The switches used to re-arrange the capacitors into different configurations need to be powered by some energy source. 
     In  FIGS. 4A-B , a series-parallel and a Dickson charge pump in a 1:5 (step-down) configuration (or 5:1—step-up—if the power flow is reversed) are shown. The voltage labels on each node have two values: the first is the voltage value during stage 1 of operation; the second is the voltage value during stage 2 of operation. 
     In a Dickson charge-pump, each stage sees only a small fraction of the total voltage at the high voltage side of the charge-pump. This allows for using lower voltage rated devices and improves efficiency. However, if the high-voltage side should suddenly step up rapidly, it is possible for the low-voltage switches to experience temporary over-voltage stress that can result in damage. 
     In general, it is important to protect the switch elements from being exposed to voltages in excess of their breakdown voltages to prevent damage to the conversion circuit or faulty operation of the circuit. 
     SUMMARY 
     In one aspect, in general, transient or fault conditions for a switched capacitor power converter are detected by measuring one or more of internal voltages and/or currents associated with switching elements (e.g., transistors) or phase nodes, or voltages or currents at terminals of the converter, and based on these measurements detect that a condition has occurred when the measurements deviate from a predetermined range. Upon detection of the condition fault control circuitry alters operation of the converter, for example, by using a high voltage switch to electrically disconnect at least some of the switching elements from one or more terminals of the converter, or by altering timing characteristics of the phase signals. 
     In another aspect, in general, in the event that a capacitor is accidentally shorted to the next stage, across itself, or to ground (such as its bottom plate to ground), an over-voltage and under-voltage protection can be implemented. Each capacitor in the charge-pump is monitored to see if it is within an acceptable range given the charge-pump ratio. For example, if the output of the charge-pump should be 2V, than the capacitor closest to the output should also be approximately 2V. In adiabatic charging, the capacitor voltage can vary quite a bit during each cycle, so there needs to be sufficient margin in the over and under voltage protection to account for normal voltage variation. 
     In another aspect, in general, a switched capacitor power converter has a first terminal for coupling to a first external circuit at substantially a high voltage, and a second terminal for coupling to a second external circuit at substantially a low voltage lower than the high voltage. In operation of the power converter, charge passes on a charge transfer path between the first terminal and the second terminal. The converter includes a plurality of semiconductor switch elements. These switch elements include a first set of switch elements on the charge transfer path between the first terminal and the second terminal, wherein no switch element in the first set of switch elements is connected in series with either the first terminal or the second terminal to carry substantially all the current passing through said terminal, and wherein each switch element in the first set of switch elements is configured to form a controllable charge transfer path between a corresponding subset of a plurality of capacitors. The switch elements also include a second set of switch elements configured to form electrical connection of at least some of the capacitors to alternating reference voltages. The plurality of switch elements is configured to form said interconnections in successive states in operation. The converter further includes measurement circuitry configured to measure a voltage and/or a current characteristic of one or more switch elements of the first set of switch elements or the second set of switch elements, and fault control circuitry coupled to the measurement circuitry configured to alter operation of the power converter upon detection of a condition determined when the measured characteristics of the switch elements deviate from a predetermined range of said characteristics. 
     Aspects can include one or more of the following features. 
     The plurality of switch elements further includes a third set of switch elements on the charge transfer path between the first terminal and the second terminal connected in series with either the first terminal or the second terminal. 
     The second set of switch elements include switch elements that form electrical connection of at least some of the capacitors to the low voltage terminal during some states of operation (e.g., at “phase nodes” of the converter). 
     The stages of operation comprise a repeated sequence of clocked stages. 
     The converter further comprises the plurality of capacitors, with each capacitor having a terminal coupled to a terminal of at least one switch element of the plurality of switch elements. In some examples, the capacitors and switch elements are integrated in a monolithic device. 
     The converter comprises a Dickson charge pump. 
     The voltage and/or current characteristics of the one or more switch elements belong to a group consisting of:
         a voltage across terminals of a switch element of the first set of switch elements;   a current through a switch element of the first set of switch elements;   a voltage at a junction between a switch element of the first set of switch elements and a capacitor of the plurality of capacitors;   a voltage across terminals of a capacitor of the plurality of capacitors coupled to the switch element;   a voltage at a junction between a switch element of the second set of switch elements and a capacitor of the plurality of capacitors; and   a current through a switch element of the first set of switch elements.       

     The voltage and/or current characteristic of the switch element comprises a voltage across terminals of the switch element. 
     The voltage and/or current characteristic of the switch element comprises a current through the switch element. 
     The voltage and/or current characteristic of the switch element comprises a voltage at a terminal of the switch element. 
     The voltage and/or current characteristic of the switch element comprises a voltage across terminals of a capacitor of the plurality of capacitors coupled to the switch element. 
     The switch elements of the second set of switch elements form a phase generator, and wherein the voltage and/or current characteristic of the switch element comprises a voltage and/or current supplied by the phase generator. 
     Each of the semiconductor switch elements comprises a FET transistor for coupling at least two of the capacitors. 
     At least some of the semiconductor switch elements comprise a network of multiple FET transistors. 
     At least some of the switch elements of the first set of switch elements or the second set of switch elements have a maximum voltage rating less than the high voltage. 
     At least some of the switch elements of the first set of switch elements or the second set of switch elements have a maximum voltage rating less than the difference between the high voltage and the low voltage. 
     At least some of the switch elements of the first set of switch elements or the second set of switch elements have a maximum voltage rating no greater than a fraction 1/N, N&gt;1, of the difference between the high voltage and the low voltage. 
     The fault control circuitry comprises one or more switches each having maximum voltage rating greater than the voltage rating of at least some of the plurality of switches, the one or more switches being configured to electrically disconnecting or limit current flow through at least some switch elements of the plurality of switch elements. In some examples, the one or more switches comprise a switch coupled directly to the first terminal. In some examples, the one or more switches comprise a switch coupled between two switch elements of the plurality of switch elements. 
     The fault control circuitry is configured to modify the characteristics of the phases upon detection of the condition. In some examples, the characteristics of the phases belong to a group consisting of:
         a duty cycle of clocked phases;   a clocking frequency of the phases; and   a skipping of one or more clock cycles of clocked phases.       

    
    
     
       DESCRIPTION OF DRAWINGS 
         FIGS. 1A and 1B  are schematics of a 1:3 voltage conversion ratio (step-down) charge pump a 3:1 voltage conversion ratio (step-up) charge pump, respectively. 
         FIG. 2  is a schematic of an interleaved version of the step-down charge pump in  FIG. 1A . 
         FIG. 3  is a schematic of a transistor-level representation of a pair of switches. 
         FIGS. 4A-B  are schematics of a series-parallel and a Dickson charge pump, respectively. 
         FIG. 5  is a schematics of fault indicator circuit. 
         FIG. 6  is a schematic of charge pump with a fault detection circuit. 
         FIG. 7  is a schematic of charge pump with cascoded switches. 
         FIG. 8  is a schematic of charge pump with cascoded switches and detection circuitry. 
         FIG. 9  is a schematic of a charge pump with input control. 
         FIG. 10  is a schematic of a charge pump with input disconnect. 
         FIGS. 11A-B  are schematics of high-side and low-side switches for a step-down and a step-up, respectively. 
         FIGS. 12A-B  are schematics of current sensing circuits. 
         FIG. 13  is a schematic of a fault detector with a charge pump as shown in  FIG. 1A . 
         FIGS. 14-15  are schematics to current sensing and comparator circuits suitable for use in the circuit of  FIG. 13 . 
         FIG. 16  is a schematic including a step-down charge pump with fault detection circuitry. 
         FIGS. 17-20  are a schematics each including a missing or open terminal fault detector. 
     
    
    
     DESCRIPTION 
     1 Overview 
     A number of related approaches are described below for detection of faults (or potential faults or potential failures, exceeding device ratings, etc.) of switched capacitor power converters and/or circuitry coupled to such converters (e.g., load circuitry), and in some cases approaches for controlling operation of converters after detection of such faults, for example, to avoid failure within and external to the charge pump. These faults or failures may occur in operation, or in a shut-down (i.e., not actively operating as a power converter) but powered state. Note that the approaches described below may be used independently, and in general, may be used together in various combinations. Furthermore, it should be understood that although approaches described below may be illustrated in the context of a particular type of converter (e.g., a series/parallel or a Dickson), at least some of the approaches are applicable to a much wider range of converters. 
     A number of the approaches described below differ according to what is measured, and according to how the fault or failure is mitigated. Measurements can include one or more of
         voltage across the source and drain of a switching transistor   current through a switching transistor;   voltage at a terminal of a capacitor of the converter (e.g., at the terminal of a device to which an external capacitor is attached, at a terminal of a switching transistor is attached, etc.)   voltage and/or current at the high voltage or low voltage terminal of the converter   voltage and/or current at the output of a phase node, or at a terminal of a capacitor attached to a phase node
 
Approaches to mitigating the fault or failure can include one or more of:
   Suspending operation of the converter (e.g., suspending the clocked operation);   Modifying the clocking of the converter without suspending operation, for example, by increasing or slowing the clocking rate, changing the duty cycle, etc. to permit voltage equilibration within the converter, inhibiting all switching;   Restarting the converter (e.g., executing a startup operation sequence);   Controlling a high-voltage switch (transistor) at the high-voltage terminal of the converter, for example, to limit current flow through the converter (e.g., by opening the switch to stop current flow, or putting the switch in a constant current mode);   Decoupling the electrical path(s) through the converter with one or more switches (e.g., high-voltage switches), which may be on internal paths in the converter;   Generating a logic fault indicator that causes a pin transition or external interrupt signal so that the user is notified and can take corrective action (e.g. reducing the external load, suspending converter operation)   Changing the logic state of one or more bits in an internal register, according to the type of fault(s) detected, to assist the user in debugging the faults when the contents of this internal register are read back       

     In the discussion below, FET transistors are used as examples of semiconductor switch elements. Other types of devices (e.g., other types of transistors), and networks of multiple devices (e.g., series and/or parallel connections of transistors) can be used to form such switches. 
     Note that in some implementations, the converter may include a number of parallel converters operating out of phase with one another (e.g, two parallel converters 180 degrees out of phase, three converters 120 degrees out of phase with overlapping phases, etc.), and the detection and mitigation approaches may be performed independently for each phase, or can be coordinated. For example, during a recovery/restart of one of the parallel converters, the other converters may be reconfigured to operate in a manner to provide uninterrupted power conversion (e.g., by suitably adjusting their relative phase, over clocking rate, etc.). 
     2 Over/Under Voltage Sensing at Terminals 
     As introduced above, one approach generally uses sensed voltages at the terminals of the converter to detect over- or under-voltage conditions. In a number of embodiments, the charge pump is configured to prevent charge pump operation under atypical or fault conditions that would 
     a) exceed the V GSmax  and V DSmax  rating of the switching transistors, their gate drivers and associated control circuitry 
     b) operate the transistors in a weak state where functional or parametric misbehavior can occur 
     c) cause a subsystem connected in series with VX to operate outside of the normal range 
     If event (a) occurs, the damage to the charge pump can be immediate or long-term whereby the part may continue to operate but at a reduced robustness and performance level. Events (b) and (c) can cause abnormal operating behavior, which can also degrade part robustness and performance. Such events can occur since VX is likely to be a package pin, thereby exposed and vulnerable to physical contact by the user. Furthermore, the assembly process itself may cause shorts or opens to occur on a package pin or external component, or create shorts between adjacent pins or components. For instance, a user probing various nodes on the package or board while operating a step-down charge pump may inadvertently short VX to ground or to a supply rail. Or the user may unintentionally apply a larger than specified load current on VX, causing the VX voltage to drop below the normal operating range. When the capacitors are external to the charge pump die and package, an assembly process defect may leave out a capacitor or leave open one of the capacitor connections to the charge pump. If the charge pump was operated with a missing or open capacitor, the VX voltage would also drop. 
     In applications where the charge pump is operated in series with another subsystem such as an LDO or another switching converter (inductor- or capacitor-based), VX can either be the input that powers this subsystem or the subsystem output that powers the charge pump. In both cases, an under-voltage or over-voltage event at VX may be undesirable for the performance and robustness of the subsystem as well. 
     2.1 VX Under-Voltage and Over-Voltage Sensing and Lockout 
     In some embodiments the VX voltage is sensed during operation or in the shutdown-but-powered state, and an internal indicator is generated by circuitry in or associated with the charge pump to disable operation or prevent charge pump operation upon enable (lockout), whenever the VX voltage moves outside a predefined voltage window. When VX drops below the lower limit of the window, VX is under-voltage while VX is over-voltage when VX rises above the upper limit of the window. VX under-voltage (UVLO) and over-voltage (OVLO) sensing and lockout implements a first-order protection of the low-voltage transistors used in a high voltage conversion ratio charge pump, by preventing charge pump operation if the transistor absolute maximum voltage ratings are exceeded or if the transistor cannot switch reliably due to insufficient gate drive. 
     The OVLO threshold, or the upper limit of the VX-sensing window, should be set above the maximum operating VX level required by the application but below the V DSmax  rating of the transistors, to give margin for tolerances in the OVLO circuit and VX voltage transients. The UVLO threshold, or the lower limit of the VX-sensing window, is set, for example, below the minimum operating VX level including the largest VX ripple amplitude that would occur across the application space, but above the level where basic transistor functionality would fail or degrade to a point that would adversely affect the performance of the charge pump and/or the subsystem connected in series with VX. Examples of the latter constraint are the voltage at which the gate driver output fails to transition according to the gate driver input, or where the gate driver&#39;s propagation delay increases to an extent that would cause misbehavior elsewhere in the charge pump. Depending on the application space, there is usually more flexibility in setting the UVLO threshold versus the OVLO threshold, since the latter is constrained mainly by the voltage rating of the charge pump transistors. Instead of a fixed voltage level, the UVLO threshold can be variable as a function of the VX voltage level and the VX ripple amplitude, if such information was available to the charge pump through sensed inputs or internally programmed settings. For instance, the charge pump switching frequency and capacitor values could be internally programmed settings and these settings directly govern the VX ripple amplitude. 
       FIG. 5  shows a circuit example that implement UVLO and OVLO sensing at the VX node. The example uses two comparators whose outputs are combined by an OR gate to generate a logical fault indicator. The inputs to the comparators are VX or some fraction of VX generated using an internal voltage divider, and the thresholds V THuvlo  and V THovlo , which are scaled from the UVLO and OVLO threshold by the same fraction as the VX-based input to the comparator. For all practical purposes, V THovlo &gt;V THuvlo . When the VX voltage lies in between the UVLO and OVLO thresholds, the outputs of the comparators are both low and therefore the fault indicator is also a logic low. Otherwise the fault indicator will be a logic high and this logic state can be used to disable charge pump operation or enable. 
     Note that while most of the charge pump illustrations above are for a step-down configuration, this approach can also be applied in similar fashion to step-up configurations, since the one is a reverse-direction power flow version of the other. 
     3 Detection of Internal Voltage Deviations 
     Another approach detects deviations of voltage on capacitors in the converter outside their expected operating ranges. 
     3.1 Detection Scheme 1 
       FIG. 6  shows the basic technique applied to the detection of a fault condition on capacitor C 1 . A similar circuit is needed to monitor the voltages on C 2 , C 3  and C 4 . This example shows a 5:1 step-down Dickson charge pump, but can be similarly applied, as other examples, to a step-up configuration, to all possible charge pump ratios and to the Series-Parallel charge pump topology. 
     The charge pump operates in a substantially conventional manner, with the addition of PMOS device MP 1  (which has to be selected to operate at the higher voltage across C 1 ), together with resistors R 1  and R 2  as well as switch S 10  and comparators CMP 1  and CMP 2 . 
     Current I 1  is roughly proportional to the voltage across C 1  (the error is the source-gate voltage of MP 1 ). Current I 2  is very nearly identical to I 1 . By proper selection of R 2  the voltage across this resistor is, roughly, an analog of the voltage across C 1  and can be scaled as desired. Switch S 10 , along with capacitor Cfilter, is used to allow detection of the voltage on R 2  only when switch S 8  is on (switch S 9  forces the R 2  voltage to be 0). CMP 1  and CMP 2 , along with the Under Voltage and Over Voltage reference voltages form what is called a window comparator. Either the OV or UV outputs being asserted indicates a fault condition which then triggers one or several of the protection mechanisms implemented. 
     3.2 Detection Scheme 2 
       FIG. 7  shows a possibly more practical embodiment of the 5:1 Dickson charge pump. The additional switches are required because, with reference to the figure  FIG. 6 —switches S 2 , S 3  and S 4  are exposed, when in the off state, to twice the voltage across switches S 1  and S 5  in the off state. 
     For a given charge pump ratio and a fixed VIN, annotated voltages V 1 , V 2  and V 3  do not change appreciably.  FIG. 8  shows a detection scheme that relies on detecting a large change in voltage across the charge pump caps by means of a window comparator for each capacitor (previously described above). The input to this window comparator is an attenuated version of the charge pump capacitor voltages themselves. Resistor ratios R 1 /R 2 , R 3 /R 4  and R 5 /R 6  are chosen so as to appropriately scale those capacitor voltages. Comparator output signals OV —  and UV —  can be used to trigger any or all of the protection mechanisms being implemented. 
     4 High-Side Transient Protection 
     Referring to  FIG. 9 , another way of protecting from a transient fault is to use a high-voltage disconnect (SWINP) switch that performs as a voltage or current limiting device during a transient event. The method implemented in the circuit of  FIG. 9  controls the SWINP switch with one or a combination of several modes of operation.
         One possible mode is as a Low Drop Out (LDO) regulator.   A second mode is a Current Limited (CL) switch.   A third mode is a Transient Voltage Suppressor (TVS).       

     In LDO mode the voltage at N 1  has a maximum value. The CONTROL does not allow voltage on N 1  to exceed the maximum voltage that the charge-pump can sustain. In the condition where VIN is less than the maximum voltage the switch SWINP would be in a low impedance state. For example the maximum allowed voltage on N 1  is 22 volts. In normal operation the voltage on VIN is 20 volts. The voltage on N 1  is almost 20 volts. The VIN supply rises to 22 volts. The voltage on N 1  remains at 20 volts. 
     In CL mode there is a maximum current that SWINP will allow to pass through from VIN to N 1 . In the condition where N 1  is at or below the maximum voltage set by the LDO, the output current of SWINP is limited. For example in normal operation VIN=16 volts and voltage on N 1  is almost 16 volts. The current through SWINP is &lt;1 ampere. A situation arises where the current through SWINP would need to supply 3 amperes to maintain node N 1  at 16 volts. This 3 amperes is above the safe operating range on the switches. The CONTROL would limit the SWINP current to 2 amperes and the voltage on N 1  would decrease. Note that this mode is also useful to indirectly mitigate the effect of transient voltages on the terminals. 
     In TVS mode the voltage on N 1  is not allowed to change by more than a predefined rate. The voltage on N 1  is below the maximum allowed by the LDO, the current is below the maximum allowed by CL. The TVS will allow the charge-pump to redistribute the voltage from N 1  appropriately on the capacitors C_. For example in normal operation VIN=16 volts. The current through SWINP is &lt;1 ampere. A situation arises where the voltage on VIN rises to 18 volts in 10 −6  seconds (1 μs). The maximum voltage slew rate on N 1  is designed to be 0.100 volts per μs. The voltage on N 1  will rise to 18 volts, but the CONTROL would make it take 20 us to reach this new voltage level on N 1 . 
     4.1 High-Side Protection 
     In a conventional Dickson Charge-pump (see, e.g.,  FIG. 4B ), each stage sees only a small fraction of the total voltage at the high voltage side (VIN) of the charge-pump. In steady state operation the voltage across any of SW —  does not exceed VOUT. This allows for using lower voltage rated switches and improves efficiency. 
     Prior to power being applied to the circuit all nodes are at zero volts (GND) potential. When a voltage VIN is first applied to the circuit, the voltage across the capacitors C 1 , C 2 , C 3 , C 4  is still zero volts. This requires the switch SW 4  to be designed to support the full voltage of VIN. 
     The switches SW_ are all regularly toggled between a low impedance state and a high impedance state in a predefined sequence. Each switch SW_ has a gate capacitance. The charging and discharging of the gate capacitance is a power loss. When a switch is toggled there is a finite power loss. This power loss reduces the efficiency of the charge-pump. The power loss is dependent on the switch design. 
     A higher voltage rated switch will typically have much larger gate capacitance. The toggling power loss of a high voltage designed switch is significantly larger than the power loss from a low voltage designed switch of the same low impedance value. 
     It is advantageous to use an additional disconnect switch (SWINP) on the high-voltage side that is designed for high voltages, as shown in  FIG. 10 . Since this switch doesn&#39;t toggle periodically when the charge-pump is operating, its large gate capacitance doesn&#39;t affect performance. 
     During powerup the switch SWINP is able to manage the voltages applied to the remaining switches. The voltage on N 1  is managed such that the capacitors C —  can approach steady state voltages without over stressing the switches SW_. This allows the remaining switches to all remain low voltage designed switches. 
     There are several possible faults for a charge-pump power converter. Faults include both internal and external devices. Faults can occur prior to power being applied or during powered operation. A capacitor can become an electrical open or any two nodes can be electrically shorted. Common faults include assembly errors with too much or insufficient solder at the printed circuit board connections. When a fault does occur, this SWINP switch can then current limit or disconnect the high-voltage side from the charge-pump and help protect it from damaging current levels. 
     5 Phase Node Monitoring 
     A number of further approaches make use of monitoring current at the phase nodes of the converter. 
     Embodiments of such n approaches are described below and provide an efficient way to detect the numerous types of fault events that may affect both the charge pump and its capacitors. The detected fault events include phase node shorted to a fixed rail (ground or phase-pump supply); positive terminal of a capacitor shorted to a fixed rail (ground or input voltage VIN) or charge pump output voltage VOUT; positive terminal of a first capacitor shorted to the positive terminal of a second capacitor (the first capacitor being closest to input voltage VIN); missing capacitor or open capacitor terminal; and charge pump output shorted to ground or output over-current. 
     These fault events are most likely to occur when the charge pump uses external or non-integrated capacitors, since these components and their connections are exposed and vulnerable to physical contact by the user. Furthermore, the assembly process itself may cause shorts or opens to occur on a pin or component, or create shorts between adjacent pins or components. The fault events can either occur during start-up or normal operation. 
     Embodiments described below rely at least in part on the recognition that an extensive fault coverage for charge pumps in an efficient way (in terms of die area, quiescent current) can be achieved by sensing the current in the charge pump phase nodes. By sensing the current flow through each switch while the switch conducts, a fault event can be detected based on the switch current magnitude and polarity. 
     It is also possible to detect some of the aforementioned fault events by sensing the current through the input voltage VIN or through the switches at the positive terminal of each capacitor. However, the input voltage VIN and the positive terminals of each capacitor can operate at a high voltage depending on the charge pump configuration, thereby requiring the current-sense circuit to be designed using high-voltage devices or be powered between high-voltage rails. 
     Designing for high-voltage operation typically requires more die area and more quiescent current, compared to an equivalent circuit that is powered from the lowest charge pump voltage level, as would be used in the approach described here. Furthermore, this method can result in significantly higher die area and quiescent current savings when the phase nodes common to an operating state are shared since there would only be two phase nodes per charge pump, compared to current sensing at the switches of each capacitor&#39;s positive terminal where no node or pin sharing is possible. However, such sharing is not essential (e.g., with a separate phase node for each capacitor) to obtain the benefit of the approach. 
       FIG. 11A  defines the current flow polarity through the high-side and low-side switches for a step-down charge pump. Similarly,  FIG. 11B  defines the current flow polarity through the high-side and low-side switches for a step-up charge pump. The current flow polarity during normal operation is illustrated by the solid arrows, while the reverse current flow polarity that may occur upon a fault event is illustrated by the dashed arrows. 
     For some fault events, the conducting high-side or low-side switch sees only an atypical increase in the current magnitude compared to the magnitude in the absence of a fault. In other events, the conducting high-side or low-side switch sees both a reversal in the polarity of current flow and an increase in current magnitude. Since the state of every switch (conducting or not) in the charge pump is always known and well-controlled, it is not difficult to compare the switch current magnitude and/or polarity to a predefined level that signals a valid fault event. This predefined level can be fixed for all operating conditions of the charge pump, user-programmable or track specific signals like output load current, if such information were available to the charge pump. Upon the detection of the fault event, part damage or a “smoke-and-fire” occurrence can be prevented by immediately turning off all phase node switches and letting the phase nodes go high-impedance. Note that for protection against some types of faults, the switches controlling the phase nodes have to have a high voltage rating. 
     TABLE 1 summarizes the current flow polarity through the high-side and low-side switches of a step-down charge pump for the following fault events: A phase node shorted to ground, a phase node shorted to phase-pump supply, a positive terminal of a capacitor shorted to ground, a positive terminal of a capacitor shorted to the input voltage VIN, a positive terminal of a capacitor shorted to the output voltage VOUT, a positive terminal of a first capacitor shorted to a positive terminal of a second capacitor, and charge pump output shorted to ground or output over-current. For a step-up charge pump, the high-side and low-side switch current flow polarity would be the inverse of the step-down, except for the fault events denoted with an asterix. 
     
       
         
           
               
               
               
             
               
                 TABLE 1 
               
               
                   
               
               
                   
                 High-side 
                 Low-side 
               
               
                   
                 Switch 
                 Switch 
               
               
                   
                 Current Flow 
                 Current Flow 
               
               
                 Fault Event 
                 Polarity 
                 Polarity 
               
               
                   
               
             
            
               
                 (a) A phase node shorted to ground 
                 Reverse 
                 N/A 
               
               
                 (b) A phase node shorted to phase-pump 
                 N/A 
                 Reverse 
               
               
                 supply 
               
               
                 (c) A positive terminal of a capacitor 
                 Reverse 
                 Normal 
               
               
                 shorted to ground 
               
               
                 (d) A positive terminal of a capacitor 
                 Normal 
                 Reverse 
               
               
                 shorted to the input voltage VIN* 
               
               
                 (e) A positive terminal of a capacitor 
                 Reverse 
                 Normal 
               
               
                 shorted to the output voltage VOUT* 
               
               
                 (f) A positive terminal of the first 
                 Normal 
                 Reverse 
               
               
                 capacitor shorted to the positive terminal 
               
               
                 of the second capacitor* 
               
               
                 (g) Missing capacitor or open capacitor 
                 Normal 
                 Normal 
               
               
                 terminal 
               
               
                 (h) Charge pump output shorted to 
                 Normal 
                 Normal 
               
               
                 ground or output over-current 
               
               
                   
               
            
           
         
       
     
     With the exception of an output over-current, the faults listed in TABLE 1 are much less likely to occur when the capacitors are integrated on the same die as the charge pump, connected to the charge pump die using a through-silicon via process, or consist of discrete components co-packaged on top of the charge pump die within a single module. However, having fault detection can still be useful as a diagnostic tool or for preventing smoke-and-fire events when process defects (e.g. metal shorts or opens between adjacent on-chip capacitors) or co-packaging errors occur. 
       FIGS. 12A-B  illustrate two circuits that can be used to perform switch current sensing. Both circuits utilize a transconductance amplifier GM 1  to convert a voltage drop across either a switch or a sense resistor in series with the switch into a sense current ISEN, whose magnitude is proportional to the switch current ISW. The polarity of sense current ISEN in and out of the amplifier GM 1  follows the polarity of the switch current ISW. The sense current ISEN can then be directly compared with a current whose magnitude and polarity are consistent with the fault event to be detected, to generate a logic-level output fault indicator. 
     For example, if the transconductance of amplifier GM 1  in  FIG. 12A  is designed to be directly proportional to the switch conductance, then the sense current ISEN can be a direct multiple of the switch current ISW and no other variable to a first order. Alternatively in  FIG. 12B , the sense resistor in series with the switch can consist of the metal interconnect between the switch and the package pins, which can be on the same order of magnitude as the switch on-resistance. 
       FIG. 13  shows how an example of the fault detector can be coupled with the charge pump in  FIG. 1A . Across each of the four switches at the phase nodes P 1  and P 2  is a current sensing and comparator circuit: CS 1  senses the high-side switch current at phase node P 1 , CS 2  senses the high-side switch current at phase node P 2 , CS 3  senses the low-side switch current at phase node P 1 , and CS 4  senses the low-side switch current at phase node P 2 . Each of the four current sensing and comparator circuits has a logic output that is a logic-low when no fault is detected, and a logic-high when a fault is detected based on the switch current magnitude and polarity changes. If any one or more of the four current sensing and comparator circuits CS 1  to CS 4  has a logic-high output in the middle of charge pump operation, a logic gate OR 1  will output a logic-high signal that sets a set-reset latch SR 1 , thereby generating a latched logic signal that can be used to close all switches, shut down the charge pump immediately and generate a bus interrupt or toggle an output fault indicator pin. The charge pump then remains in shutdown until a fault reset signal is received by the set-reset latch SR 1 , at which point charge pump operation can resume. The fault reset signal can come from a supply undervoltage-lockout or a toggle on the charge pump enable input. 
       FIGS. 14 and 15  illustrate two circuits that implement the current sensing and comparator circuit in  FIG. 13 , where the same implementation can apply to all four current sensing and comparator circuits CS 1  to CS 4 . The current sensing portion of  FIGS. 14-15  can be implemented using either the circuit in  FIG. 12A  or  FIG. 12B , though only the circuit in  FIG. 12A  is shown. In  FIG. 14 , the sense current ISEN whose magnitude and polarity follows the switch current is mirrored into three separate currents ISEN 1  to ISEN 3  using a current mirror or a current amplifier, each equaling the sense current ISEN or its multiple. The currents ISEN 1  and ISEN 2  can be individually converted into voltages VSEN 1  and VSEN 2  using resistors, which are then compared against threshold voltages VTH 1  and VTH 2  using voltage comparators CP 1  and CP 2  respectively. The current ISEN 3  is fed into a single-ended current comparator ICP 1  (such as a Traff current comparator) used to determine current polarity: when the switch current polarity is normal, the sense current ISEN flows out of the transconductance amplifier GM 2  and the mirrored current ISEN 3  flows into the single-ended current comparator ICP 1  input terminal, causing the output voltage of ICP 1  to be a logic-low; conversely when the switch current polarity reverses upon a fault event, the sense current ISEN also reverses polarity and the mirrored current ISEN 3  flows out of the single-ended current comparator ICP 1  input terminal, causing the output voltage of ICP 1  to be a logic-high. The voltage comparators CP 1  and CP 2  are used to determine whether the magnitude of the normal polarity switch current exceeds a level consistent with a fault event. Different fault events can be associated with different switch current magnitudes, and can be detected and differentiated by using more than one comparator input voltage threshold (VTH 1 ≠VTH 2 ). The outputs of voltage comparators CP 1 , CP 2  and ICP 1  are combined in a logical OR operation by the logic gate OR 2  to generate a logical fault indicator that is logic-high whenever any one or more of the comparator outputs are logic-high. It should be noted that the comparators CP 1  and CP 2  do not have to be voltage comparators, but can also be differential current comparators, in which case the resistors are no longer needed and the voltage thresholds VTH 1  and VTH 2  should be replaced with current threshold levels consistent with each fault event to be detected. 
       FIG. 15  shows an alternate implementation of the current sensing and comparator circuit in  FIG. 4A , where instead of using a single-ended current comparator like ICP 1  in  FIG. 4B  to sense a reversal in switch current polarity, a voltage comparator CP 3  similar to voltage comparators CP 1  and CP 2  is used. The sense current ISEN is fed into a resistor divider network powered off a reference voltage, VREF, while a common voltage tap off the resistor divider network, VSEN, is compared by three voltage comparators CP 1  to CP 3 . The magnitude of the voltage tap VSEN is a function of both the magnitude and polarity of the sense current ISEN: when the switch current polarity is normal, the sense current ISEN flows out of the transconductance amplifier GM 2  and into the resistor divider network at the voltage tap point VSEN, thereby increasing the magnitude of VSEN above the level defined as VDIV that would ordinarily be determined by the value of the resistor divider ratio and the reference voltage, VREF. Therefore, the threshold voltages VTH 1  and VTH 2 , which correspond to fault events where the switch current magnitude is atypically elevated, should be set above VDIV. Upon a fault event where the switch current polarity reverses, the sense current ISEN flows into the transconductance amplifier GM 2  output, pulling the voltage tap VSEN below VDIV. Consequently, the threshold voltage VTH 3  should be set below VDIV. Like  FIG. 4B , the outputs of voltage comparators CP 1  to CP 3  are combined in a logical OR operation by the logic gate OR 2  to generate a logical fault indicator that is logic-high whenever any one or more of the comparator outputs are logic-high. 
     A missing capacitor or open capacitor terminal fault event typically does not result in immediate charge pump damage or a smoke-and-fire event. Nevertheless, it is desirable to detect this fault occurrence and take preventive measures such as shutting down the charge pump, otherwise the charge pump will continue to operate for several cycles before eventually exceeding specified tolerances. 
       FIG. 16  illustrates a step-down charge pump  50  with fault detection circuitry to detect an outer capacitor open terminal connection in the middle of operation. An outer capacitor is defined herein as the capacitor closest to the input voltage YIN or the output voltage VOUT. Whenever a charge pump has two or fewer capacitors as shown in  FIGS. 1A-1B , all the capacitors are outer capacitors. 
     Charge pump  50  has N capacitors, C 1  to C N , where N is an even integer number. The odd-numbered capacitors C 1 , C 3 , . . . C N-1  share a first phase node P 1  and the even-numbered capacitors C 2 , C 4 , . . . C N  share a second phase node P 2 . The first and second high-side switches HS 1 , HS 2  couple the first and second phase nodes P 1 , P 2  to the output voltage VOUT, respectively. Similarly, the first and second low-side switches LS 1 , LS 2  couple the first and second phase nodes P 1 , P 2  to ground, respectively. In this example, the outer capacitors are C 1  and C N . The load at the charge pump  50  output is a current source IOUT, which enables the charge transfer between the capacitors to take place via a smooth and steady charging current proportional to IOUT, in a process described as soft charging. 
     During normal steady-state operation with soft charging, the currents through the conducting phase switches in each state are equal in magnitude. For instance in a first state, the first high-side switch HS 1  and the second low-side switch LS 2  conduct current wherein both switches carry the same magnitude of current. Likewise in a second state, the second high-side switch HS 2  and the first low-side switch LS 1  conduct current wherein both switches carry the same magnitude of current. 
     If one terminal of either outer capacitor C 1  or C N  is disconnected in the middle of operation, the following occurs for several switching cycles before the charge pump output eventually collapses: the phase node currents become unbalanced in every other state or the current magnitude through one conducting high-side switch no longer matches the current magnitude through the other simultaneously conducting low-side switch. This fault can then be detected by simultaneously sensing and comparing the phase node switch currents during each state, and generating a logic flag whenever the current magnitudes become mismatched by more than a predefined offset. To avoid false positives, this logic flag should be set only if the current mismatch exceeds the predefined offset in at least multiple consecutive cycles, and the predefined offset should be large enough to ignore non-fault mismatches that can arise from mismatches in the outer capacitor values. 
       FIG. 16  also shows four current sensing and comparator circuits, CS 5 , CS 6 , CS 7 , CS 8 ; each across one of the four phase switches. The particular implementation of each current sensing and comparator circuit is similar to that in  FIG. 14  or  FIG. 15 . To detect a mismatch between the high-side and low-side switch currents in each state, one of the  FIG. 14  or  FIG. 15  voltage thresholds VTH 1  or VTH 2  can be designed to be a function of the switch current in that state. For example in the first state when the first high-side switch HS 1  and the second low-side switch LS 2  conduct, the voltage threshold VTH 1  in the current sensing and comparator circuit CS 5  should be proportional to the current magnitude of the low-side switch LS 2 , in order to sense the current mismatch magnitude between high-side switch HS 1  and low-side switch LS 2 . Similarly in the second state when the second high-side switch HS 2  and the first low-side switch LS 1  conduct, the voltage threshold VTH 1  in the current sensing and comparator circuit CS 6  should be proportional to the current magnitude of the low-side switch LS 1 , in order to sense the current mismatch magnitude between high-side switch HS 2  and low-side switch LS 1 . The proportion of the phase switch current magnitude used to generate the voltage threshold VTH 1  determines the predefined offset by which an open outer capacitor terminal fault can be detected and differentiated from non-fault mismatches. In addition, the comparator CP 1  should have a symmetrical input offset or hysteresis, or be a window comparator in order to detect a bidirectional current mismatch. 
     An example of a missing or open capacitor terminal fault detector can also be applied to a charge pump where the phase nodes and switches are not shared by the common-state capacitors, such as charge pump  60 A shown in  FIG. 17 . Like charge pump  50 A, there are N capacitors, C 1  to C N , in charge pump  60 A where N is an even integer number. Each capacitor has its own pair of phase switches that connect the capacitor negative terminal between ground and the output voltage VOUT. There are altogether N high-side switches and N low-side switches, instead of just 2 high-side switches and 2 low-side switches for the charge pumps in  FIGS. 13 and 16 . Across each phase switch is a current sensing circuit, shown in  FIG. 17  as HCS 1  to HCS N  for the high-side switches and LCS 1  to LCS N  for the low-side switches. The phase node current sensing scheme now applies to a greater number of switches at the expense of die area and quiescent current, but provides much more information on the current through each capacitor and wider fault coverage. In this case, an open capacitor terminal fault can be detected in any of the capacitors, not just the outer capacitors, by flagging a per-capacitor current level that is practically zero or significantly lower than that of the other capacitor current levels. 
       FIG. 18  shows a particular implementation of the fault detector for the high-side switches in  FIG. 17 . The current sensing circuit across each phase switch can be implemented using the circuits in either  FIG. 12A  or  FIG. 12B . As previously described, the output of each current sensing circuit is a current that represents the magnitude and polarity of the corresponding switch current. In  FIG. 18 , the current output of the first high-side switch current sensing circuit HCS 1  is first replicated into two current copies, ISEN HA1  and ISEN HB1 , using a current mirror or a current amplifier. The remaining current outputs of the odd-numbered high-side switch current sensing circuits HCS 3 , HCS 5  . . . HCS N-1  are summed together with ISEN HA1  to generate a total high-side switch current for the first state, ISEN H   _   STATE1 , that is equivalent to the high-side switch HS 1  current in  FIG. 16 . ISEN H   _   STATE1  can then be replicated using a second current mirror or current amplifier to implement the comparator schemes previously described in  FIGS. 4B-4C  to sense fault events that cause a switch current magnitude and polarity change. ISEN HB1  is used to detect a missing or open terminal fault at capacitor C 1  since the current magnitude through the first high-side switch and by extension that of ISEN HB1  will decrease to zero upon the fault: by connecting ISEN HB1  to the input of a current comparator ICP 3 , the comparator output logic level will be high if ISEN HB1  is detected to be close to zero, and low if ISEN HB1  is on the same order of magnitude as the other current outputs ISEN H1 , ISEN H3 , ISEN H5  . . . ISEN HN-1 . 
     Similarly in the second state,  FIG. 18  shows the current outputs of the even-numbered high-side switch current sensing circuits HCS 2 , HCS 4  . . . HCS N  summed together to generate a total high-side switch current for the second state ISEN H   _   STATE2 , that is equivalent to the high-side switch HS 2  current in  FIG. 16 . The resulting fault detection implementation using ISEN H   _   STATE2  is then similar to that used for ISEN H   _   STATE1 , and the individual logic fault signals for each state can be logically combined in an OR operation. 
       FIG. 19  shows a particular implementation of the fault detector for the low-side switches in  FIG. 17 . The current outputs of the even-numbered low-side switch current sensing circuits LCS 2 , LCS 4 , LCS 6 , . . . LCS N  are first replicated into two copies using a current mirror or a current amplifier during the first state. During the second state, the current outputs of the odd-numbered high-side switch current sensing circuits LCS 1 , LCS 3 , LCS 5  . . . LCS N-1  are similarly replicated using a current mirror or a current amplifier. For either state of operation, the first set of copied currents corresponding to each state (ISEN LA2 , ISEN LA4 , ISEN LA6  . . . ISEN LAN  in the first state; ISEN LA1 , ISEN LA3 , ISEN LA5  . . . ISEN LAN-1  in the second state) are summed together to generate a total low-side switch current, ISEN L   _   STATE1  and ISEN L   _   STATE2 , that is equivalent to the current in the  FIG. 5  low-side switches LS 2  and LS 1  respectively. The comparator schemes previously described in  FIGS. 14-15  can then be applied using ISEN L   _   STATE1  and ISEN L   _   STATE2 . 
     The missing or open capacitor terminal fault detector is slightly different from that used for the high-side switches as illustrated previously in  FIG. 18 . The second set of replicated currents corresponding to each state (ISEN LB2 , ISEN LB4 , ISEN LB6  . . . ISEN LBN  in the first state; ISEN LB1 , ISEN LB3 , ISEN LB5  . . . ISEN LBN-1  in the second state) are each connected to current comparators ICP L1  to ICP LN  to detect a missing or open terminal fault at any capacitor, by detecting when the current magnitudes are at or close to zero. This zero-current detector can actually be used for the high-side switch implementation ( FIG. 18 ) as well but it is unnecessary to use the zero-current detector for all the high-side and low-side switches since the  FIG. 17  capacitors C 2  to C N  are always connected in series with a low-side switch in both the first and second states; only the outer capacitor C 1  is not connected in series with a low-side switch during the first state. Therefore, a zero-current detector for only the first high-side switch is required as shown by the current comparator ICP 3  in  FIG. 18 . Conversely, the  FIG. 17  capacitors C 1  to C N-1  are always connected in series with a high-side switch in both the first and second states; only the outer capacitor C N  is not connected in series with a high-side switch during the first state. As an example,  FIGS. 18-19  shows the zero-current detector used for all the low-side switches and just the first high-side switch connected to capacitor C 1 , with both implementations together able to detect a missing or open terminal fault at any capacitor in the  FIG. 17  charge pump, and not just at the outer capacitors. 
       FIG. 20  shows an alternate method to detect a missing or open capacitor terminal fault at any capacitor for the charge pump in  FIG. 1A , although this method can also be applied in the same fashion to the charge pumps in  FIG. 1B ,  FIG. 16  and  FIG. 17 . One advantage of this method is that the charge pump does not have to be operated with soft charging for the fault detector to work. Upon the occurrence of a missing or open capacitor terminal fault event, either in the middle of charge pump operation or before charge pump operation begins, the charge pump will not be able to regulate the output VOUT to the target set by the charge pump conversion ratio and VOUT droops lower over consecutive switching cycles. By comparing the VOUT voltage level against a voltage threshold VUVLO using a voltage comparator CP 8 , the output of voltage comparator CP 8  can be used as a logical fault indicator that disables charge pump operation when VOUT droops below the voltage threshold VUVLO. The voltage threshold VUVLO should be set below the minimum operating VOUT level in the application, including the largest VOUT ripple amplitude that would occur across the application space but above a level where basic transistor functionality would fail or degrade to a point that would adversely affect the performance of the charge pump and/or a subsystem connected in series with VOUT. The voltage threshold VUVLO can be a fixed voltage level or variable as a function of the VOUT voltage level and the VOUT ripple amplitude, if such information was available to the charge pump through sensed inputs or internally programmed settings. For instance, the charge pump switching frequency and capacitor values could be internally programmed settings and these settings directly govern the VOUT ripple amplitude. 
     6 Implementations 
     Implementations of the approaches described above may be integrated into monolithic devices, using integrated and/or external (e.g., discrete) capacitors. Control logic for detecting and processing of the detected states may be integrated fully on the device, or may be implemented at least in part using external circuitry. This integrated and/or external circuitry can use dedicated logic circuitry (e.g., application specific integrated circuits, ASICs) and/or software implemented logic including a controller, processor, or some other software controlled element. Such software may be stored on a tangible machine-readable medium (e.g., semiconductor memory, optical disk, etc.). Instructions for controlling at least some stage of design or fabrication of a device implementing an approach described above may also be stored on a tangible machine-readable medium. 
     It is to be understood that the foregoing description is intended to illustrate and not to limit the scope of the invention, which includes the scope of the appended claims. Other embodiments are within the scope of the following claims.