Patent Publication Number: US-6335715-B1

Title: Circuit for preventing rush current in liquid crystal display

Description:
This application claims the benefit of Korean Patent Application No. 98-47566, filed on Nov. 6, 1998, which is hereby incorporated by reference. 
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a liquid crystal display, and more particularly, to a current preventing circuit for a liquid crystal display. 
     2. Description of the Related Art 
     A liquid crystal display (LCD) is, among other things, light weight, thin, and consumes low power. The LCD provides a highly enhanced picture quality owing to an improvement in a liquid crystal material and a development in the fine picture element (or pixel) treatment technique. Accordingly, the LCD has a wide range of applications. Such an LCD allows a picture corresponding to image signals to be displayed on a liquid crystal panel by controlling a light quantity passing through the liquid crystal panel based on the image signals. The liquid crystal panel of the LCD comprises a number of liquid crystal cells arranged in a matrix pattern, and a number of control switches such as thin film transistors (TFTs) for switching image signals to be applied to each liquid crystal cell. Further, the LCD includes a gate driver for driving the control switches. The gate driver consists of a plurality of gate drive integrated circuits, hereinafter referred to as “gate D-ICs”. 
     For example, as shown in FIG. 1, the conventional LCD includes 1st to nth gate D-ICs  4   a - 4   n  for respectively driving gate lines in a liquid crystal panel  6 . A timing controller  2  generates a row drive clock RCLK, a start pulse SP, and an output enable signal OE. The gate D-ICs  4   a - 4   n  respond to the start pulse from the timing controller  2  sequentially, and respond to the output enable signal OE and the row drive clock RCLK simultaneously. Each gate D-IC is provided with a shift register for shifting the start pulse SP by one bit in response to the row drive clock RCLK, and a level shifter array for level-shifting each logical signal at output channels from the shift register. The level shifter array responds to the output enable signal OE to apply the level-shifted signal to the gate line in the liquid crystal panel  6  as a scanning signal. Accordingly, the gate lines in the liquid crystal panel  6  are sequentially enabled for each horizontal synchronous interval by means of the gate D-ICs. 
     The gate D-ICs  4   a - 4   n  generate a rush current at the time of applying an initial power. This results from a reset function of the gate D-IC that is eliminated from the LCD to reduce the size of gate D-IC  4  and an error therein. More specifically, when an initial power is applied to the LCD, logical signals in an unknown state emerge at each output channel of the shift register included in the gate D-ICs  4 . These unknown state logical signals change a high logic into a low logic or vice versa whenever the row drive clock RCLK is applied to the gate D-ICs  4   a - 4   n . The unknown state logical signals are not eliminated until a ground logic of start signal is shifted into the last output channel of the last gate D-IC  4   n . Further, the unknown state logical signals are applied to the gate lines in the liquid crystal panel  6  after being level-shifted with the level shifter array. At this time, specific logic states (e.g., high logic) of the logical signals are level-shifted, so that the level shifter array can be latched up. Also, since a number of gate lines are enabled, an overcurrent, called “rush current” having several hundred times the value as compared with a normal value, flows at the gate D-ICs  4   a - 4   n . Such a rush current has an adverse effect on circuit devices within the LCD and gives rise to an abnormal operation in the circuit devices. This causes a deterioration in the LCD. 
     SUMMARY OF THE INVENTION 
     Accordingly, the present invention is directed to a circuit for preventing rush current in liquid crystal display that substantially obviates one or more of the problems due to limitations and disadvantages of the related art. 
     An object of the present invention is to provide a rush current preventing circuit for a liquid crystal display that is suitable for eliminating a rush current when an initial power is applied to the liquid crystal display. 
     Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings. 
     To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, a rush current preventing circuit for a liquid crystal display includes output enable signal generating means for generating an output enable signal to control outputs of gate drive integrated circuits; start output enable signal generating means for generating a start output enable signal having at least a desired interval of disable pulse at the time of applying an initial power; and output enable signal switching means for switching the output enable signal and the start output enable signal corresponding to the start output enable signal. 
     According to another aspect of the present invention, a rush current preventing circuit for a liquid crystal display includes start output enable signal generating means for generating a start output enable signal having at least a desired interval of disable pulse at the time of applying an initial power; and output enable signal combining means for combining an output enable signal with the start output enable signal and for applying the combined output enable signal to the gate drive integrated circuits. 
     It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention. 
     In the drawings: 
     FIG. 1 is a schematic view showing the configuration of a conventional liquid crystal display; 
     FIG. 2 is a block diagram of a rush current preventing circuit for a liquid crystal display according to an embodiment of the present invention; and 
     FIG. 3 shows a rush current preventing circuit for a liquid crystal display according to another embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Reference will now be made in detail to the preferred embodiment of the present invention, example of which is illustrated in the accompanying drawings. 
     Referring to FIG. 2, there is shown a rush current preventing circuit for a liquid crystal display according to an embodiment of the present invention. The rush current preventing circuit includes an output enable signal generator  14  for generating an output enable signal OE, a start output enable signal generator  18  for generating a start output enable signal SOE, and an output enable signal switch  16  for combining the start output enable signal SOE from the start output enable signal generator  18  with the output enable signal OE from the output enable signal generator  14 . The output enable signal generator  14 , the start enable signal generator  18 , and the output enable signal switch  16  are preferably included in a timing controller such as shown in FIG.  1 . In this case, the output enable signal switch  16  is commonly connected to the gate D-ICs  4   a - 4   n  shown in FIG. 1 to apply any one of the output enable signal OE and the start output enable signal SOE to the gate D-ICs  4   a - 4   n . The output enable signal OE generated at the output enable signal generator  14  has an enable pulse of low logic designating a time interval at which a scanning signal is output from the gate D-IC to a gate line in the liquid crystal panel  6  every horizontal synchronous interval. The start output enable signal SOE has a disable pulse of high logic which prevents a scanning signal from being applied from the gate D-IC to the gate line in the liquid crystal panel  6  during at least one vertical synchronous interval, preferably during an interval of 20 ms. This disable pulse is generated at a time point when power is applied to the LCD, or after a certain time from the time point. In order to generate the start output enable signal SOE, the start output enable signal generator  18  may include a counter for counting a row drive clock RCLK to set a width of the disable pulse, and a logical arithmetic unit for generating a logical signal from an output of the counter. An R-C integrator having resistors and capacitors can be used as the counter. A switching device or a comparator having a threshold voltage, such as a field effect transistor and the like, can be used as the logical arithmetic unit. The output enable signal switch  16  allows the start output enable signal SOE from the start output enable signal generator  18  to be applied to the gate D-ICs  4   a - 4   n  during a time interval when the start output enable signal SOE has a high logic of disable pulse. On the other hand, the output enable signal switch  16  allows the output enable signal OE from the output enable signal generator  14  to be transferred to the gate D-ICs  4   a - 4   n  during a time interval when the start output enable signal SOE does not have a high logic of disable pulse. To this end, the output enable signal switch  16  can include one control switch or two three-state buffers. Alternatively, the output enable signal switch  16  may include a logic gate, such as an OR gate, or a wired logic gate. 
     The gate D-ICs  4   a - 4   n  connected to the output enable signal switch  16  commonly respond to the start output enable signal SOE upon power-on. At this time, the level shifter array included in each gate D-IC does not output a scanning signal to the gate line in the liquid crystal panel  6  during at least one of vertical synchronous interval by a disable pulse of the start output enable signal SOE. Meanwhile, the shift register included in each the gate D-IC is initialized by shifting a ground logic state as a start signal with the aid of a row drive pulse. Accordingly, the level shifter array is not latched up even though the output enable signal OE is applied. Thus, a rush current is not generated at the gate D-ICs  4   a - 4   n . As a result, circuit devices within the LCD operate under stable conditions and the LCD performance is improved dramatically. 
     Referring now to FIG. 3, there is shown a rush current preventing circuit for a liquid crystal display according to another embodiment of the present invention. The rush current preventing circuit includes a start output enable signal generator  38  for generating a start output enable signal SOE, and an output enable signal combiner  36  for combining an output enable signal OE from a timing controller  12  with the start output enable signal SOE from the start output enable signal generator  38 . The rush current preventing circuit preferably includes an exterior block separated from the timing controller  12 , and which is connected between the output terminal of the timing controller  12  and the input terminals of gate D-ICs  34 ( a-n ) in the liquid crystal panel. In this case, the output terminal of the timing controller  12  is connected to a signal input line  30  of the rush current preventing circuit. A combined output enable signal COE generated at the output enable signal combiner  36  is commonly applied, via an output line  32 , to the gate D-ICs  34 . 
     Specifically, the start output enable signal generator  38  includes a fourth diode D 4  and a seventh resistor R 7  connected in series between a clock input line  28  and a first node  22 , a third capacitor C 3  connected between the first node  22  and a ground voltage source GND, a transistor Q having an emitter terminal and a collector terminal connected to the ground voltage source GND and a second node  24 , respectively, and a sixth resistor R 6  connected between the first node  22  and the base terminal of the transistor Q. The seventh resistor R 7  and the third capacitor C 3  is used as an R-C integrator which integrates a row drive clock signal RCLK from a clock input line  28 . The transistor Q is a switching device having a desired threshold voltage which generates a logical signal from an output signal of the R-C integrator. More specifically, the R-C integrator accumulates the row drive clock signal RCLK inputted via a fourth diode D 4  from the clock input line  28 . Such an accumulating operation in the R-C integrator occurs because a voltage charged in the third capacitor C 3  is prevented from being discharged into the clock input line  28  by the fourth diode D 4 . A time constant of the R-C integrator is set such that a voltage charged in the third capacitor C 3  arrives at the threshold voltage of the transistor Q after the lapse of at least one vertical synchronous interval, preferably an interval of  20 ms, from the time of power-on. In other words, the R-C integrator performs a counter function of counting one vertical synchronous interval from the time of power-on. The transistor Q compares a voltage level accumulated in the R-C integrator (i.e., the third capacitor C 3 ) with its threshold voltage and switches a current path between the second node  24  and the ground voltage source GND in accordance with the compared result, whereby a logical signal emerges at the second node  24 . When a voltage accumulated in the R-C integrator is higher than the threshold voltage of the transistor Q, the transistor Q is turned on to thereby bypass a voltage at the second node  24  into the ground voltage source GND. At this time, a start output enable signal SOE of a low logic state is generated at the second node  24 . On the other hand, when a voltage accumulated in the R-C integrator is lower than the threshold voltage of the transistor Q, the transistor Q is turned off to thereby maintain a voltage at the second node  24 . Thus, a start output enable signal SOE of a high logic state is generated at the second node  24 . As a result, a start output enable signal SOE is generated at the second node where the SOE has a high logic state which acts as a disable pulse to prevent a scanning signal from being applied from the gate D-ICs  34  to the gate line in the liquid crystal panel  20  during at least one vertical synchronous interval, preferably an interval of 20 ms, from the time of power-on. Meanwhile, a sixth resistor R 6  limits an over current applied to the base terminal of the transistor Q. 
     The start output enable signal generator  38  further includes a third diode D 3  and a third resistor R 3  connected in series between a supply voltage source VDD and a third node  26 , a fourth resistor R 4  and a second capacitor C 2  connected in parallel between the third node  26  and the ground voltage source GND, and a fifth resistor R 5  connected between the third node  26  and the second node  24 . The supply voltage source VDD applies a supply voltage VDD having a certain voltage level, via the third diode D 3  and the third resistor R 3 , to the third node  26 . This supply voltage VDD is generated at the supply voltage source VDD after the lapse of a very short interval (e.g., a period of row drive clock signal) from a time of power-on. The third diode D 3  prevents a voltage at the third node  26  from being reverse-applied to the supply voltage source VDD. The third and fourth resistors R 3  and R 4  and the second capacitor C 2  constitute a low pass filter (LPF) which filters a supply voltage VDD to be applied from the third diode D 3  to the fifth resistor R 5 . The LPF prevents a noise from being included in the supply voltage VDD transferred from the third diode D 3  to the fifth resistor R 5 . The fifth resistor R 5  limits a current flowing from the third node  26  into the second node  24 . The supply voltage applied to the second node  24  is selectively bypassed into the ground voltage source GND with the aid of the transistor Q to generate the start output enable signal SOE. 
     The output enable signal combiner  36  includes a second diode D 2  connected between the second node  24  and a signal output line  32 , a first resistor R 1  and a first diode D 1  connected in series between the signal input line  30  and the signal output line  32 , and a second resistor R 2  and a first capacitor C 1  connected in parallel between the signal output line  32  and the ground voltage source GND. The first resistor R 1  limits the amount of current of the output enable signal OE that is to be transferred from the timing controller  12 , via the signal input line  30 , to the first diode D 1 . The first diode D 1  passes the output enable signal OE from the first resistor R 1  to the output signal line  32  and, at the same time, prevents a signal from being reverse-applied from the output signal line  32  to the first resistor R 1 . The second resistor R 2  and the first capacitor C 1  constitute a single LPF to eliminate a radio frequency (RF) noise component in the output signal line  32 . The first diode D 1  configures an OR gate along with the second diode D 2 . This OR gate combines the output enable signal OE with the start output enable signal SOE to generate a combined output enable signal COE. The combined output enable signal COE is commonly applied, via the output signal line  32 , to the gate D-ICs  34 . At this time, the level shifter array included in each gate D-IC  34  does not output to the gate line in the liquid crystal panel  20  during at least one vertical synchronous interval with the aid of a disable pulse of the start output enable signal SOE. The shift register included in each gate D-IC shifts a start signal of a ground logic state with the aid of a row drive pulse to thereby initialize the same. Accordingly, the level shifter array included in the gate D-IC  34  is not latched up even though the output enable signal OE is applied, and thus a rush current is not generated at the gate D-ICs  34 . As a result, circuit devices within the LCD are operated under stable conditions and the reliability of the LCD is enhanced dramatically. 
     As described above, the rush current preventing circuit for the liquid crystal display according to the present invention generates the output enable signal having the disable pulse upon power-on, thereby preventing a scanning signal from being outputted at the gate line in the liquid crystal panel. Accordingly, a rush current is not generated at the liquid crystal display. As a result, the reliability of the liquid crystal display can be enhanced, and the liquid crystal display can perform a stable operation. 
     It will be apparent to those skilled in the art that various modifications and variation can be made in the circuit for preventing rush current in liquid crystal display of the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention cover the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.