Patent Publication Number: US-11664386-B2

Title: Display device and method of fabricating the same

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     The present application claims priority to and the benefit of Korean Patent Application No. 10-2019-0125912 filed on Oct. 11, 2019, in the Korean Intellectual Property Office, the entire content of which is incorporated herein by reference. 
     BACKGROUND 
     1. Field 
     Aspects of some example embodiments of the present disclosure relate to a display device and a method for fabricating the same. 
     2. Description of the Related Art 
     As the information-oriented society evolves, display devices may be more frequently utilized to display images and information. Accordingly, recent display devices include liquid-crystal displays (LCDs), plasma display panels (PDPs), organic light-emitting displays (OLEDs), micro light-emitting diode displays, etc. 
     The pixels of an organic light-emitting display device or a micro light-emitting diode display device may include a light-emitting diode, a first transistor for adjusting the amount of driving current supplied from a first supply voltage line to the light-emitting element according to a voltage of the gate electrode, and a scan transistor for applying a data voltage from a data line to the gate electrode of the first transistor in response to a scan signal from a scan line. 
     The driving voltage of the first transistor refers to the voltage applied to the gate electrode of the first transistor to allow the driving current to flow. The driving voltage range of the first transistor refers to a voltage range from a first voltage that allows a minimum driving current (e.g., a set or predetermined minimum driving current) to flow to a second voltage that allows a maximum driving current (e.g., a predetermined maximum driving current) to flow. 
     The driving voltage range of the first transistor can be widened by increasing the channel length of the first transistor. However, if the channel length of the first transistor is increased, the size of the first transistor may also be increased, such that the size of the pixels may be increased. As the size of pixels increases, it may be difficult to realize a high resolution display device and a high pixel per inch (PPI) display device. 
     The above information disclosed in this Background section is only for enhancement of understanding of the background and therefore the information discussed in this Background section does not necessarily constitute prior art. 
     SUMMARY 
     Aspects of some example embodiments of the present disclosure are directed to a display device capable of increasing a driving voltage range of a first transistor of each of the pixels. 
     Aspects of some example embodiments of the present disclosure are also directed to a method of fabricating a display device capable of increasing a driving voltage range of a first transistor of each of the pixels. 
     However, example embodiments of the present disclosure are not restricted to those set forth herein. The above and other aspects of some example embodiments of the present disclosure will become more apparent to one of ordinary skill in the art to which the present disclosure pertains by referencing the detailed description of the present disclosure given below. 
     According to some example embodiments of the present disclosure, a display device includes: a substrate; a first active layer of a first transistor and a second active layer of a second transistor on the substrate; a first gate insulating layer on the first active layer; a first gate electrode on the first gate insulating layer; a second gate insulating layer on the second active layer; and a second gate electrode on the second gate insulating layer. A hydrogen concentration of the first gate insulating layer is lower than a hydrogen concentration of the second gate insulating layer. 
     According to some example embodiments of the present disclosure, there is provided a display device comprising: a plurality of pixels connected to scan lines and data lines intersecting the scan lines. Each of pixels comprises a light-emitting element, a first transistor for controlling a driving current flowing to the light-emitting element according to a data voltage applied to a gate electrode thereof, and a second transistor that is turned on by a scan signal from a scan signal to apply a data voltage from the data line to the gate electrode of the first transistor. A driving voltage range of the first transistor is wider than a driving voltage range of the second transistor. 
     According to some example embodiments of the present disclosure, in a method of fabricating a display device, the method includes: forming a first active layer of a first transistor and a second active layer of a second transistor on a substrate; forming a first gate insulating layer on a first channel region of the first active layer, and a first gate electrode of the first transistor on the first gate insulating layer, the first gate electrode overlapping the first channel region in a first direction that is a thickness direction of the substrate; and forming a second gate insulating layer on a second channel region of the second active layer, and a second gate electrode of the second transistor on the second gate insulating layer, the second gate electrode overlapping the second channel region in the first direction. A hydrogen concentration of the first gate insulating layer is lower than a hydrogen concentration of the second gate insulating layer. 
     According to the aforementioned and other example embodiments of the present disclosure, the hydrogen concentration of a first gate insulating layer between a first active layer and a first gate electrode of a first transistor may be lower than the hydrogen concentration of a second gate insulating layer between a second active layer and a second gate electrode of a second transistor. The lower the hydrogen concentration of the first gate insulating layer is, the more electron traps by oxygen interstitial of the first gate insulating layer may be created. As a result, the driving voltage range of the first transistor can be widened. 
     In addition, the minimum thickness of the first gate insulating layer may be greater than the minimum thickness of the second gate insulating layer. As a result, the distance between the first gate electrode and the first active layer is increased, and thus the driving voltage range of the first transistor can be widened. 
     Other aspects and characteristics of some example embodiments may be more apparent from the following detailed description, the drawings, and the claims. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The above and other aspects of some example embodiments according to the present disclosure will become more apparent by describing in more detail example embodiments thereof with reference to the attached drawings, in which: 
         FIG.  1    is a perspective view of a display device according to some example embodiments of the present disclosure. 
         FIG.  2    is a plan view showing an example of a display panel according to some example embodiments of the present disclosure. 
         FIG.  3    is a circuit diagram showing an example of one of the sub-pixels of  FIG.  2   . 
         FIG.  4    is a cross-sectional view showing an example of the first transistor and the second transistor of  FIG.  3   . 
         FIG.  5    is a graph showing driving current curves of first transistors having different the hydrogen concentrations of the first gate insulating layers. 
         FIG.  6    is a table showing the driving current flowing at the turn-on voltage, the driving current flowing at the turn-off voltage, the electron mobility and the driving voltage range of each of the first transistor and the second transistor. 
         FIG.  7    is a cross-sectional view showing an example of the first transistor and the second transistor of  FIG.  3   . 
         FIG.  8    is a table showing the driving current flowing at the turn-on voltage, the driving current flowing at the turn-off voltage, the electron mobility and the driving voltage range of the first transistor. 
         FIG.  9    is a flowchart for illustrating a method of fabricating a display device according to some example embodiments of the present disclosure. 
         FIGS.  10  to  21    are cross-sectional views of a first transistor and a second transistor for illustrating a method of fabricating a display device according to some example embodiments of the present disclosure. 
         FIG.  22    is a flowchart for illustrating a method of fabricating a display device according to some example embodiments of the present disclosure. 
         FIGS.  23  to  25    are cross-sectional views of a first transistor and a second transistor in the operations S 201 , S 204 , and S 205  of  FIG.  22   . 
     
    
    
     DETAILED DESCRIPTION 
     Further details of some example embodiments of the present disclosure will now be described more fully hereinafter with reference to the accompanying drawings, in which some example embodiments of the disclosure are shown. Embodiments according to the present disclosure may, however, be embodied in different forms and should not be construed as being limited to the example embodiments set forth herein. Rather, these example embodiments are provided so that this disclosure will be more thorough and more complete, and will more fully convey the scope of embodiments according to the disclosure to those skilled in the art. The same reference numbers indicate the same components throughout the specification. In the attached figures, the thickness of layers and regions is exaggerated for clarity. 
     Hereinafter, aspects of some example embodiments of the present disclosure will be described with reference to the attached drawings. 
       FIG.  1    is a perspective view of a display device according to some example embodiments of the present disclosure.  FIG.  2    is a plan view showing an example of a display panel according to some example embodiments of the present disclosure. 
     As used herein, the terms “above,” “top” and “upper surface” refer to the upper side of the display panel  100 , i.e., the side indicated by the arrow in the z-axis direction, whereas the terms “below,” “bottom” and “lower surface” refer to the lower side of the display panel  100 , i.e., the opposite side in the z-axis direction. As used herein, the terms “left,” “right,” “upper” and “lower” sides indicate relative positions when the display panel  100  is viewed from the top. For example, the “left side” refers to the opposite direction indicated by the arrow of the x-axis, the “right side” refers to the direction indicated by the arrow of the x-axis, the “upper side” refers to the direction indicated by the arrow of the y-axis, and the “lower side” refers to the opposite direction indicated by the arrow of the y-axis. 
     A display device  10  is for displaying moving images or still images. The display device  1  may be used as the display screen of portable electronic devices such as a mobile phone, a smart phone, a tablet PC, a smart watch, a watch phone, a mobile communications terminal, an electronic notebook, an electronic book, a portable multimedia player (PMP), a navigation device and a ultra mobile PC (UMPC), as well as the display screen of various products such as a television, a notebook, a monitor, a billboard and the Internet of Things. 
     The display device  10  may be one of an organic light-emitting display device, a liquid-crystal display device, a plasma display device, a field emission display device, an electrophoretic display device, an electrowetting display device, a quantum dot light-emitting display device, a micro LED display device and the like. In the following description, an organic light-emitting display device is described as an example of the display device  10 . It is, however, to be understood that embodiments according to the present disclosure are not limited thereto. 
     Referring to  FIGS.  1  and  2   , the display device  10  according to some example embodiments includes a display panel  100 , a display driver  200 , and a circuit board  300 . 
     The display panel  100  may be formed in a rectangular plane having shorter sides in a first direction (x-axis direction) and longer sides in a second direction (y-axis direction) intersecting the first direction (x-axis direction). Each of the corners where the short side in the first direction (x-axis direction) meets the longer side in the second direction (y-axis direction) may be rounded with a curvature (e.g., a set or predetermined curvature) or may be a right angle. 
     The shape of the display panel  100  when viewed from the top is not limited to a quadrangular shape, but may be formed in a different polygonal shape, a circular shape, or an elliptical shape. The display panel  100  may be, but is not limited to being, formed to be flat. For example, the display panel  10  may include curved portions formed at left and right ends thereof and having a constant or varying curvature. In addition, the display panel  100  may be formed to be flexible so that it can be curved, bent, folded or rolled. 
     The display panel  100  may include a display area DA where sub-pixels PX are formed to display images, and a non-display area NDA, which is the peripheral area of the display area DA. When the display panel  100  includes a curved portion, the display area DA may be arranged on the curved portion. In such case, images of the display panel  100  can also be seen on the curved portion. 
     In the display area DA, scan lines SL, emission lines EL, data lines DL and first supply voltage lines VDDL connected to the sub-pixels PX may be arranged, in addition to the sub-pixels PX. The scan lines SL and the emission lines EL may be arranged in the first direction (x-axis direction), while the data lines DL may be arranged in the second direction (y-axis direction) intersecting the first direction (x-axis direction). The first supply voltage lines VDDL may be arranged in parallel in the second direction (y-axis direction) in the display area DA. The first supply voltage lines VDDL formed in parallel in the second direction (y-axis direction) in the display area DA may be connected to one another in the non-display area NDA. 
     Each of the sub-pixels PX may be connected to at least one of the scan lines SL, at least one of the data lines DL, at least one of the emission lines EL, and at least one of the first supply voltage lines VDDL. In the example shown in  FIG.  2   , each of the sub-pixels PX is connected to two scan lines SL, one data line DL, one emission line EL, and the first supply voltage line VDDL for convenience of illustration. It is, however, to be understood that embodiments according to the present disclosure are not limited thereto. For example, each of the sub-pixels PX may be connected to three scan lines SL rather than two scan lines SL. 
     Each of the sub-pixels PX may include a driving transistor, at least one switching transistor, a light-emitting element, and a capacitor. When the data voltage is applied to the gate electrode, the driving transistor DT may supply a driving current to the light-emitting element, so that light can be emitted. The driving transistor DT and the at least one transistor T may be thin-film transistors. The light-emitting element may emit light according to the driving current from the driving transistor DT. The light-emitting element may be an organic light-emitting diode including a first electrode, an organic emissive layer, and a second electrode. The capacitor can keep the data voltage applied to the gate electrode of the driving transistor DT constant. 
     The non-display area NDA may be defined as the area from the outer side of the display area DA to the edge of the display panel  100 . In the non-display area NDA, a scan driver  410  for applying scan signals to scan lines SL, and pads DP connected to the data lines DL may be arranged. Because the circuit board  300  is attached to the pads DP, the pads DP may be arranged on one edge of the display panel  100 , for example, the lower edge of the display panel  100 . 
     The scan driver  410  may be connected to the display driver  200  through a plurality of first scan control lines SCL 1 . The scan driver  410  may receive scan control signals from the pads DP through the plurality of first scan control lines SCL 1 . The scan driver  410  may generate scan signals according to the scan control signals and may sequentially output the scan signals to the scan lines SL. The sub-pixels PX to which the data voltages are supplied are selected by the scan signals of the scan driver  410  and the data voltages are supplied to the selected sub-pixels PX. 
     An emission control driver  420  may be connected to a display driving circuit  320  through a plurality of scan control lines SCL. The emission control driver  420  may receive scan control signals from the pads DP through the plurality of second scan control lines SCL 2 . The emission control driver  420  may generate emission control signals according to the emission control signals and may sequentially output the emission control signals to the emission lines EL. 
     Although the scan driver  410  is arranged at an outer side of the display area DA, and the emission control driver  420  is arranged at the opposite side of the display area DA in the example shown in  FIG.  2   , embodiments according to the present disclosure are not limited thereto. Both the scan driver  410  and the emission control driver  420  may be arranged on an outer side of the display area DA or may be arranged on each of the outer sides of the display area DA. 
     The display driver  200  receives digital video data and timing signals from external devices. The display driver  200  converts the digital video data into analog positive/negative data voltages and supplies them to the data lines DL. The display driver  200  generates and supplies scan control signals for controlling the operation timing of the scan driver  410  through the first scan control lines SCL 1 . The display driver  200  generates and supplies emission signals for controlling the operation timing of the emission control driver  420  through the second scan control lines SCL 2 . The display driver  200  may supply a first supply voltage to the first supply voltage lines VDDL. 
     The display driver  200  may be implemented as an integrated circuit (IC) and attached to the circuit board  300  by the chip-on-film (COF) technique. Alternatively, the display driver  200  may be attached to the display panel  100  by any suitable mounting technique, such as a chip-on-glass (COG) technique, a chip-on-plastic (COP) technique, or ultrasonic bonding. 
     The circuit board  300  may be attached to the pads DP using an anisotropic conductive film. In this manner, the lead lines of the circuit board  300  may be electrically connected to the pads DP. The circuit board  300  may be a flexible printed circuit board, a printed circuit board, or a flexible film such as a chip-on-film. 
       FIG.  3    is a circuit diagram showing an example of one of the sub-pixels of  FIG.  2   . 
     In the example shown in  FIG.  3   , the sub-pixel PX is connected to the (k−1) th  scan line Sk−1, the k th  scan line Sk, and the j th  data line Dj. 
     In the example shown in  FIG.  3   , the sub-pixel PX may overlap the (k−1) th  scan line S(k−1), the k th  scan line Sk, and the j th  data line Dj. In addition, the sub-pixel PX may be connected to a first supply voltage line VDDL to which the first supply voltage is applied, an initialization voltage line VIL to which an initialization voltage is applied, and a second supply voltage line VSSL to which a second supply voltage lower than the first supply voltage is applied. 
     The sub-pixel PX includes a driving transistor, a light-emitting element LE, switch elements and a first capacitor C 1 . The sub-pixel PX may include a first transistor T 1  as the driving transistor DT, and second to seventh transistors T 2 , T 3 , T 4 , T 5 , T 6  and T 7  as the switch elements. However, the sub-pixel PX of embodiments according to the present disclosure is not limited by one shown in  FIG.  3   . 
     The first transistor T 1  may include a first gate electrode, a first source electrode, and a first drain electrode. The drain-source current Ids (hereinafter referred to as “driving current”) of the first transistor T 1  is controlled according to the data voltage applied to the first gate electrode. The driving current Ids flowing through the channel of the first transistor T 1  is proportional to the square of the difference between the gate-source voltage Vgs (the voltage between the gate electrode and the first source electrode of the first transistor T 1 ) and the threshold voltage of the first transistor T 1 , as shown in Equation 1 below:
 
 Ids=k ′×( Vgs−Vth ) 2   [Equation 1]
 
where k′ denotes a proportional coefficient determined by the structure and physical properties of the first transistor T 1 , Vgs denotes the gate-source voltage of the first transistor T 1 , and Vth denotes the threshold voltage of the first transistor T 1 .
 
     An emission material layer EML emits light as the driving current Ids flows therein. The amount of the light emitted from the emission material layer EML may be proportional to the driving current Ids. The emission material layer EML may be an organic light-emitting diode including a first electrode, a second electrode, and an organic emissive layer located between the first electrode and the second electrode. 
     Alternatively, the emission material layer EML may be an inorganic light-emitting element including a first electrode, a second electrode, and an inorganic semiconductor located between the first electrode and the second electrode. Alternatively, the emission material layer EML may be an inorganic light-emitting element including a first electrode, a second electrode, and an inorganic semiconductor located between the first electrode and the second electrode. Alternatively, the emission material layer EML may be a quantum-dot light-emitting element including a first electrode, a second electrode, and a quantum-dot emissive layer located between the first electrode and the second electrode. Alternatively, the emission material layer EML may be a micro light-emitting diode. 
     The first electrode of the emission material layer EML may be connected to the second electrode of the fifth transistor T 5 , and the second electrode thereof may be connected to the second supply voltage line VSSL. A parasitic capacitance Cel may be formed between the anode electrode and the cathode electrode of the emission material layer EML. 
     The second transistor T 2  is turned on by the scan signal of the k th  scan line Sk to connect the first source electrode of the first transistor T 1  with the j th  data line Dj. The second transistor T 2  may include a second gate electrode, a second source electrode, and a second drain electrode. The second gate electrode may be connected to the k th  scan line Sk, the second source electrode may be connected to the first source electrode of the first transistor T 1 , and the second drain electrode may be connected to the data line Dj. 
     The third transistor T 3  may be implemented as a dual transistor including a (3-1) transistor T 3 - 1  and a (3-2) transistor T 3 - 2  connected in series between the gate electrode of the first transistor T 1  and a node between the first transistor T 1  and the fifth transistor T 5 . The (3-1) transistor T 3 - 1  and the (3-2) transistor T 3 - 2  are turned on by the scan signal from the k th  scan line Sk to connect the first gate electrode with the first drain electrode of the first transistor T 1 . That is to say, when the (3-1) transistor T 3 - 1  and the (3-2) transistor T 3 - 2  are turned on, the first gate electrode and the first drain electrode of the first transistor T 1  are connected to each other, and thus the first transistor T 1  operates as a diode (e.g., is diode-connected). The (3-1) transistor T 3 - 1  may include a (3-1) gate electrode, a (3-1) source electrode, and a (3-1) drain electrode. 
     The (3-1) gate electrode may be connected to the k th  scan line Sk, the (3-1) source electrode may be connected to the first drain electrode of the first transistor T 1 , and the (3-1) drain electrode may be connected to the (3-2) source electrode of the (3-2) transistor T 3 - 2 . The (3-2) transistor T 3 - 2  may include a (3-2) gate electrode, a (3-2) source electrode, and a (3-2) drain electrode. The (3-2) gate electrode may be connected to the k th  scan line Sk, the (3-2) source electrode may be connected to the (3-1) drain electrode of the (3-1) transistor T 3 - 1 , and the (3-2) drain electrode may be connected to the first gate electrode of the first transistor T 1 . 
     The fourth transistor T 4  may be implemented as a dual transistor including a (4-1) transistor T 4 - 1  and a (4-2) transistor T 4 - 2  connected in series between the third transistor T 3  and the initialization voltage line VIL. The (4-1) transistor T 4 - 1  and the (4-2) transistor T 4 - 2  are turned on by the scan signal from the (k−1) th  scan line Sk−1 to connect the first gate electrode of the first transistor T 1  with the initialization voltage line VIL. 
     Therefore, the first gate electrode of the first transistor T 1  may be discharged to the initialization voltage of the initialization voltage line VIL. The (4-1) transistor T 4 - 1  may include a (4-1) gate electrode, a (4-1) source electrode, and a (4-1) drain electrode. The (4-1) gate electrode may be connected to the (k−1) th  scan line Sk−1, the (4-1) source electrode may be connected to the first gate electrode of the first transistor T 1 , and the (4-1) drain electrode may be connected to the (4-2) source electrode of the (4-2) transistor T 4 - 2 . The (4-2) transistor T 4 - 2  may include a (4-2) gate electrode, a (4-2) source electrode, and a (4-2) drain electrode. The (4-2) gate electrode may be connected to the (k−1) th  scan line S(k−1), the (4-2) source electrode may be connected to the (4-1) drain electrode of the (4-1)transistor T 4 - 1 , and the (4-2) drain electrode may be connected to the initialization voltage line VIL. 
     The fifth transistor T 5  is connected between the first drain electrode of the first transistor T 1  and the anode electrode of the emission material layer EML. The fifth transistor T 5  is turned on by the emission control signal of the k th  emission line Ek to connect the first drain electrode of the first transistor T 1  with the anode electrode of the emission material layer EML. The fifth transistor T 5  may include a fifth gate electrode, a fifth source electrode, and a fifth drain electrode. The fifth gate electrode is connected to the k th  emission line Ek, the fifth source electrode is connected to the first drain electrode of the first transistor T 1 , and the fifth drain electrode is connected to the anode electrode of the emission material layer EML. 
     The sixth transistor T 6  is turned on by the emission control signal of the k th  emission line Ek to connect the first source electrode of the first transistor T 1  with the first supply voltage line VDDL. The sixth transistor T 6  may include a sixth gate electrode, a sixth source electrode, and a sixth drain electrode. The sixth gate electrode is connected to the k th  emission line Ek, the sixth source electrode is connected to the first supply voltage line VDDL, and the sixth drain electrode is connected to the first source electrode of the first transistor T 1 . When the fifth transistor T 5  and the sixth transistor T 6  both are turned on, the driving current Ids may be supplied to the emission material layer EML. 
     The seventh transistor T 7  is turned on by the scan signal of the k th  scan line Sk to connect the anode electrode of the emission material layer EML with the initialization voltage line VIL. The anode electrode of the emission material layer EML may be discharged to the initialization voltage. The seventh transistor T 7  may include a seventh gate electrode, a seventh source electrode, and a seventh drain electrode. The seventh gate electrode is connected to the k th  scan line Sk, the seventh source electrode is connected to the anode electrode of the emission material layer EML, and the seventh drain electrode is connected to the initialization voltage line Vini. 
     The first capacitor C 1  is formed between the first drain electrode of the first transistor T 1  and the first supply voltage line VDDL. One electrode of the first capacitor C 1  may be connected to the first drain electrode of the first transistor T 1  while the other electrode thereof may be connected to the first supply voltage line VDDL. 
     An active layer of each of the first to seventh transistors T 1 , T 2 , T 3 , T 4 , T 5 , T 6 , and T 7  may be made of an oxide semiconductor including indium (In), gallium (Ga) and oxygen (O). 
     Although the first to seventh transistors T 1 , T 2 , T 3 , T 4 , T 5 , T 6 , and T 7  are of p-type metal oxide semiconductor field effect transistors (MOSFETs), this is merely illustrative. They may be of n-type MOSFETs. 
       FIG.  4    is a cross-sectional view showing an example of the first transistor and the second transistor of  FIG.  3   . 
     Referring to  FIG.  4   , a substrate SUB may be a rigid substrate or a flexible substrate that can be bent, folded, rolled, and so on. The substrate SUB may be made of an insulating material such as glass, quartz and a polymer resin. 
     A buffer layer BF may be formed on the substrate SUB. The buffer layer BF may be formed on the substrate SUB to protect the thin-film transistors and an emissive layer  172  from moisture permeating through the substrate SUB that is susceptible to moisture permeation. The buffer layer BF may be made up of multiple layers in which one or more inorganic layers of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a titanium oxide layer and an aluminum oxide layer are alternately stacked on one another. For example, the buffer layer BF may be made up of multiple layers of a silicon nitride layer and a silicon oxide layer. In such case, the silicon oxide layer may be thicker than the silicon nitride layer. The buffer layer BF may be eliminated. 
     The first transistor T 1  and the second transistor T 2  may be formed on the buffer layer BF. The first transistor T 1  may include a first active electrode ACT 1 , a first gate electrode G 1 , a first source electrode S 1 , and a first drain electrode D 1 . The second transistor T 2  may include a second active electrode ACT 2 , a second gate electrode G 2 , a second source electrode S 2 , and a second drain electrode D 2 . 
     The first active layer ACT 1  and the second active layer ACT 2  may be formed on the buffer layer BF. The first active layer ACT 1  and the second active layer ACT 2  may be made of an oxide semiconductor including indium (In), gallium (Ga), and oxygen (O). For example, each of the first active layer ACT 1  and the second active layer ACT 2  may be made of IGZO (indium (In), gallium (Ga), zinc (Zn) and oxygen (O)), IGZTO (indium (In), gallium (Ga), zinc (Zn), tin (Sn) and oxygen (O)), or IGTO (indium (In), gallium (Ga), tin (Sn), and oxygen (O)). 
     A first gate insulating layer  131  may be formed on the first active layer ACT 1 . The first gate insulating layer  131  may be located on a portion of the first active layer ACT 1 . The first gate insulating layer  131  may be made of an inorganic layer, e.g., a silicon oxide layer. 
     The first gate electrode G 1  may be formed on the first gate insulating layer  131 . A portion of the first active layer ACT 1  overlapping the first gate electrode G 1  in a first direction DR 1  may be defined as the first channel region CP 1 . A first source region SP 1  may be located on one side of the first channel region CH 1  in a second direction DR 2  intersecting the first direction DR 1 , and the first drain region DP 1  may be located on the other side of the first channel region CH 1 . The first direction DR 1  may be the thickness direction of the substrate SUB, while the second direction DR 2  may be the direction perpendicular to the first direction DR 1 . The first gate electrode G 1  may be made up of a single layer or multiple layers of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) or an alloy thereof. 
     A second gate insulating layer  132  may be formed on the second active layer ACT 2  and the first gate electrode G 1 . The second gate insulating layer  132  may be located on a portion of the second active layer ACT 2 . The second gate insulating layer  132  may be located on the upper surface and side surfaces of the first gate electrode G 1 . The second gate insulating layer  132  may be located on the side surfaces of the first gate insulating layer  131 . The second gate insulating layer  132  may be located on a portion of the first source region SP 1  and a portion of the first drain region DP 1 . The portion of the first source region SP 1  and the portion of the first drain region DP 1  may be adjacent to the first channel region CP 1 . The second gate insulating layer  132  may be made of an inorganic layer, for example, a silicon oxide layer. 
     The second gate electrode G 2  and a capacitor electrode CE may be formed on the second gate insulating layer  132 . The second gate electrode G 2  and the capacitor electrode CE may be made up of a single layer or multiple layers of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or an alloy thereof. 
     A portion of the second active layer ACT 2  overlapping the second gate electrode G 2  in the first direction DR 1  may be defined as the second channel region CP 2 . The second source region SP 2  may be located on one side of the second channel region CP 2 , and the second drain region DP 2  may be located on the other side of the second channel region CP 2 . 
     The capacitor electrode CE may overlap with the first gate electrode G 1  in the first direction DR 1 . The capacitor electrode CE may be one electrode of the first capacitor C 1  connected to the first supply voltage line VDDL. The capacitor electrode CE may be located on the upper surface of the second gate insulating layer  132  located on the upper surface of the first gate electrode G 1 . The capacitor electrode CE may be located on the side surfaces of the second gate insulating layer  132  located on the side surfaces of the first gate electrode G 1 . The capacitor electrode CE may overlap with the upper surface of the first gate electrode G 1  in the first direction DR 1 . The capacitor electrode CE may overlap with the side surfaces of the first gate electrode G 1  in the second direction DR 2 . 
     Incidentally, the first transistor T 1  is a driving transistor, it is desired that the driving voltage range of the first transistor T 1  is wide. The driving voltage range of the first transistor T 1  ranges from a first voltage that allows a first driving current (e.g., a set or predetermined driving current) to flow to a second voltage that allows a second driving current (e.g., a set or predetermined driving current) to flow. The first driving current may be 1 nA, and the second driving current may be 500 nA. 
     Oxygen interstitial of the first gate insulating layer  131  can serve as a trap for electrons in the first channel region CP 1 . Because hydrogen in the first gate insulating layer  131  is combined with the oxygen interstitial, the lower the hydrogen concentration of the first gate insulating layer  131  is, the more electron traps caused by the oxygen interstitial may be in the first channel region CP 1 . In addition, the higher the hydrogen concentration of the first gate insulating layer  131  is, the less electron traps caused by oxygen interstitial may be in the first channel region CP 1 . 
     When the hydrogen concentration of the first gate insulating layer  131  is a first hydrogen concentration, electron traps due to oxygen interstitial increase, so that the slope of the driving current curve of the first transistor T 1  may be gentle as indicated by (a) in  FIG.  5 A . Therefore, the driving voltage range of the first transistor T 1  can be widened. 
     In contrast, when the hydrogen concentration of the first gate insulating layer  131  is a second hydrogen concentration which is higher than the first hydrogen concentration, electron traps due to oxygen interstitial decrease, so that the slope of the driving current curve of the first transistor T 1  may be steep as indicated by (b) in  FIG.  5   . Therefore, the driving voltage range of the first transistor T 1  can be narrowed. 
     Because the first transistor T 1  is a driving transistor, it is desired that the driving voltage range of the first transistor T 1  is wide. For this reason, the hydrogen concentration of the first gate insulating layer  131  may be less than 5×1,020 atom/cm 3 . 
     In contrast, the second transistor T 2  is a switching transistor, and accordingly the driving voltage range of the second transistor T 2  does not need to be wide. Therefore, the hydrogen concentration of the second gate insulating layer  132  may be 5×1,020 atom/cm 3  or more. That is to say, the hydrogen concentration of the first gate insulating layer  131  may be lower than the hydrogen concentration of the second gate insulating layer  132 . 
     In addition, as the distance between the first gate electrode G 1  and the first active layer ACT 1  increases, the driving voltage range of the first transistor T 1  may be widened. In contrast, the second transistor T 2  is a switching transistor, and accordingly the driving voltage range of the second transistor T 2  does not need to be wide. In addition, the minimum thickness d 1  of the first gate insulating layer  131  may be larger than the minimum thickness d 2  of the second gate insulating layer  132 . 
     An interlayer dielectric layer  140  may be formed on the second gate electrode G 2  and the capacitor electrode CE. The interlayer dielectric layer  132  may be arranged on a portion of the first source region SP 1  other than the portion and on a portion of the first drain region DP 1  other than the portion. The interlayer dielectric layer  140  may be arranged on the second source region SP 2  and the second drain region DP 2  of the second active layer ACT 2 . The interlayer dielectric layer  140  may be arranged on the buffer layer BF not covered by the first active layer ACT 1  and the second active layer ACT 2 . The interlayer dielectric layer  140  may be made of an inorganic layer, for example, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a titanium oxide layer, or an aluminum oxide layer. 
     The first source electrode S 1 , the first drain electrode D 1 , the second source electrode S 2 , the second drain electrode D 2  and the first supply voltage line VDDL may be formed on the interlayer dielectric layer  140 . The first source electrode S 1 , the first drain electrode D 1 , the second source electrode S 2  and the second drain electrode D 2  and the capacitor electrode CE may be made up of a single layer of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni) neodymium (Nd) and copper (Cu), and an alloy thereof, or multiple layers thereof. 
     The first contact hole CT 1  may be a hole penetrating through the interlayer dielectric layer  140  to expose the first source region SP 1  of the first active layer ACT 1 . The first source electrode S 1  may be connected to the first source region SP 1  through the first contact hole CT 1 . 
     The second contact hole CT 2  may be a hole that penetrates through the interlayer dielectric layer  140  to expose the first drain region DP 1  of the first active layer ACT 1 . The first drain electrode D 1  may be connected to the first drain region DP 1  through the second contact hole CT 2 . 
     The third contact hole CT 3  may be a hole that penetrates through the interlayer dielectric layer  140  to expose the capacitor electrode CE. The first supply voltage line VDDL may be connected to the capacitor electrode CE through the third contact hole CT 3 . 
     The fourth contact hole CT 4  may be a hole that penetrates through the interlayer dielectric layer  140  to expose the second source region SP 2  of the second active layer ACT 2 . The second source electrode S 2  may be connected to the second source region SP 2  through the fourth contact hole CT 4 . 
     The fifth contact hole CT 5  may be a hole that penetrates through the interlayer dielectric layer  140  to expose the second drain region DP 2  of the second active layer ACT 2 . The second drain electrode D 2  may be connected to the second drain region DP 2  through the fifth contact hole CT 5 . 
     A passivation layer  150  may be formed on the first source electrode S 1 , the first drain electrode D 1 , the second source electrode S 2 , the second drain electrode D 2  and the first supply voltage line VDDL. The passivation layer  150  may be made of an inorganic layer, for example, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a titanium oxide layer, or an aluminum oxide layer. 
     A planarization layer  160  may be formed on the passivation layer  150  to provide a flat surface over the first transistor T 1  and the second transistor T 2 . The planarization layer  160  may be formed of an organic layer such as an acryl resin, an epoxy resin, a phenolic resin, a polyamide resin and a polyimide resin. 
     Although the first transistor T 1  and the second transistor T 2  are implemented as top-gate transistors in the example shown in  FIG.  4   , it is to be understood that the present disclosure is not limited thereto. That is to say, the first transistor T 1  and the second transistor T 2  may be implemented as bottom-gate transistors in which the gate electrode is located below the active layer, or as double-gate transistors in which the gate electrodes are arranged above and below the active layer. 
     A first electrode  171  and a bank layer  180  of the emission material layer EML are formed on the planarization layer  160 . 
     A sixth contact hole may be formed through the planarization layer  160  to expose the fifth drain electrode of the fifth transistor T 5 . The first electrode  171  may be connected to the fifth drain electrode of the fifth transistor T 5  through the sixth contact hole. The first electrode  171  may be made of a metal material having a high reflectance in a top-emission structure in which light exits toward the second electrode  173  from the emissive layer  172 . For example, the first electrode  171  may be formed as a stack structure of aluminum and titanium (Ti/Al/Ti), a stack structure of aluminum and ITO (ITO/Al/ITO), an APC alloy and a stack structure of an APC alloy and ITO (ITO/APC/ITO). The APC alloy is an alloy of silver (Ag), palladium (Pd) and copper (Cu). Alternatively, the first electrode  171  may be made up of a single layer of molybdenum (Mo), titanium (Ti), copper (Cu), or aluminum (Al). 
     The bank layer  180  may be formed on the planarization layer  160  to partition the first electrode  171  in order to define an emission area of each of the sub-pixels PX. To this end, the bank layer  180  may be formed to cover the edge of the first electrode  171 . In the emission area EA of each of the sub-pixels, the first electrode  171 , the emissive layer  172  and the second electrode  173  are stacked on one another in this order, so that holes from the first electrode  171  and electrons from the second electrode  173  are combined with each other in the emissive layer  172  to emit light. The bank layer  180  may be formed of an organic layer such as an acryl resin, an epoxy resin, a phenolic resin, a polyamide resin, and a polyimide resin. 
     The emissive layer  172  is formed on the first electrode  171  and the bank layer  180 . The emissive layer  172  may include an organic material and emit light of a certain color. For example, the emissive layer  172  may include a hole transporting layer, an organic material layer, and an electron transporting layer. 
     The second electrode  173  is formed on the emissive layer  172 . The second electrode  173  may be formed to cover the emissive layer  172 . The second electrode  173  may be a common layer formed across the sub-pixels PX. A capping layer may be formed on the second electrode  173 . 
     In the top-emission organic light-emitting diode, the second electrode  173  may be formed of a transparent conductive material (TCP) such as ITO and IZO that can transmit light, or a semi-transmissive conductive material such as magnesium (Mg), silver (Ag) and an alloy of magnesium (Mg) and silver (Ag). When the second electrode  173  is formed of a semi-transmissive conductive material, the light extraction efficiency can be increased by using microcavities. 
     An encapsulation layer  190  may be formed on the second electrode  173 . The encapsulation layer  190  may include at least one inorganic layer to prevent or reduce oxygen, moisture, or other contaminants from permeating into the emissive layer  172  and the second electrode  173 . In addition, the encapsulation layer  190  may include at least one organic layer to protect the emissive layer  172  from foreign substances such as dust. 
     Alternatively, a substrate may be arranged on the second electrode  173  instead of the encapsulation layer  190 , such that the space between the second electrode and the substrate may be empty in a vacuum state or a filler film may be located therein. The filler film may be an epoxy filler film or a silicon filler film. 
     According to the example embodiment shown in  FIG.  4   , the hydrogen concentration of the first gate insulating layer  131  between the first active layer ACT 1  and the first gate electrode G 1  of the first transistor T 1  is lower than the hydrogen concentration of the second gate insulating layer  132  between the second active layer ACT 2  and the second gate electrode G 2  of the second transistor T 2 . As the hydrogen concentration of the first gate insulating layer is lower, the electron trap by oxygen interstitial of the first gate insulating layer can increase. Therefore, the driving voltage range of the first transistor T 1  can be widened. 
     In addition, according to the example embodiment shown in  FIG.  4   , the minimum thickness d 1  of the first gate insulating layer  131  may be larger than the minimum thickness d 2  of the second gate insulating layer  132 . As a result, the distance between the first gate electrode G 1  and the first active layer ACT 1  increases, are accordingly the driving voltage range of the first transistor T 1  can be widened. 
     The (3-1) transistor T 3 - 1 , the (3-2) transistor T- 2 , the (4-1) transistor T 4 - 1 , and the (4-2) transistor T 4 - 2 , the fifth transistor T 5 , the sixth transistor T 6  and the seventh transistor T 7  shown in  FIG.  3    may be substantially identical to the second transistor T 2  described above with reference to  FIG.  4   ; and, therefore, the redundant description will be omitted. 
       FIG.  6    is a table showing the driving current flowing at the turn-on voltage, the driving current flowing at the turn-off voltage, the electron mobility and the driving voltage range of each of the first transistor and the second transistor. 
     In  FIG.  6   , the turn-on voltage applied to the gate electrodes of the first transistor T 1  and the second transistor T 2  may be 15 V, and the turn-off voltage applied thereto may be 0 V. In  FIG.  6   , DR may refer to the driving voltage range of each of the first transistor T 1  and the second transistor T 2 . In  FIG.  6   , the threshold voltage may refer to the gate voltage applied to the gate electrode of the first transistor T 1  or the second transistor T 2  when the driving current of 10 nA is flowing through the first transistor T 1  or the second transistor T 2 . In  FIG.  6   , the channel length of the first channel region CP 1  of the first transistor T 1  and the channel length of the second channel region CP 2  of the second transistor T 2  may be 3.5 μm. 
     Referring to  FIG.  6   , when the turn-on voltage is applied to the first gate electrode G 1  of the first transistor T 1 , the driving current is 7.58×10 −6  A. When the turn-off voltage is applied to the first gate electrode G 1  of the first transistor T 1 , the driving current is 4.61×10 −11  A. In addition, the electron mobility of the first transistor T 1  may be 4.04 cm 2 /V×s, and the driving voltage range DR may be 3.12 V. The threshold voltage Vth of the first transistor T 1  may be 0.54 V. 
     When the turn-on voltage is applied to the second gate electrode G 2  of the second transistor T 2 , the driving current is 1.78×10 −5  A. When the turn-off voltage is applied to the second gate electrode G 2  of the second transistor T 2 , the driving current is 5.75×10 −11  A. The electron mobility of the second transistor T 2  may be 12.49 cm 2 /V×s, and the driving voltage range DR may be 1.88V. The threshold voltage Vth of the second transistor T 2  may be 0.30 V. 
     Because the hydrogen concentration of the first gate insulating layer  131  is lower than that of the second gate insulating layer  132 , there may be more electron traps by oxygen interstitial in the first channel region CP 1  of the first transistor T 1  than in the second channel region CP 2  of the transistor T 2 . Therefore, the electron mobility of the first transistor T 1  may be lower than the electron mobility of the second transistor T 2 . In addition, the slope of the driving current curve of the first transistor T 1  may be gentler than the slope of the driving current curve of the second transistor T 2 , and thus the driving voltage range DR of the first transistor T 1  may be wider than the driving voltage range DR of the second transistors T 2 . 
       FIG.  7    is a cross-sectional view showing an example of the first transistor and the second transistor of  FIG.  3   . 
     The example embodiment shown in  FIG.  7    is different from the example embodiment of  FIG.  4    in that a light shielding layer BML is formed on a substrate SUB, and that a source electrode S 1  of a first transistor T 1  is connected to the light shielding layer BML. 
     Referring to  FIG.  7   , a light shielding layer BML may be formed on the substrate SUB. The light shielding layer BML may overlap a first channel region CP 1  of a first active layer ACT 1  in the first direction DR 1 . By virtue of the light shielding layer BML, it may be possible to prevent or reduce light coming from the substrate SUB from being incident on the first channel region CP 1  of the first active layer ACT 1 . In this manner, it may be possible to prevent or reduce leakage current which otherwise flows in the first channel region CP 1  of the first active layer ACT 1  due to the light. The light shielding layer BML may be made up of a single layer or multiple layers of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) or an alloy thereof. A buffer layer BF may be formed on the light shielding layer BML. 
     The seventh contact hole CT 7  may be a hole that penetrates through the interlayer dielectric layer  140  and the buffer layer BF to expose the light shielding layer BML. The first source electrode S 1  may be connected to the light shielding layer BML through the seventh contact hole CT 7 . 
     When the first source electrode S 1  is connected to the light shielding layer BML through the seventh contact hole CT 7 , the light shielding layer BML and the first source electrode S 1  have the same voltage. When the light shielding layer BML and the first source electrode S 1  have the same potential, the first active layer ACT 1  adjacent to the light shielding BML in the first direction DR 1  may not be activated ACT 1  as much as the first active layer ACT 1  adjacent to the first gate electrode G 1  is. That is to say, the electron mobility of the first channel region CH 1  of the first active layer ACT 1  may be reduced, and the slope of the driving current curve of the first transistor T 1  may be decreased. Accordingly, when the first source electrode S 1  is connected to the light shielding layer BML through the seventh contact hole CT 7  as shown in  FIG.  8   , the driving voltage range DR of the first transistor T 1  can be widened, compared with the driving voltage range DR of the first transistor T 1  not including the light shielding BML as shown in  FIG.  4   . 
       FIG.  8    is a table showing the driving current flowing at the turn-on voltage, the driving current flowing at the turn-off voltage, the electron mobility and the driving voltage range of the first transistor. 
     In  FIG.  8   , the turn-on voltage applied to the gate electrode of the first transistor T 1  may be 15 V, and the turn-off voltage applied thereto may be 0 V. In  FIG.  8   , DR may refer to the driving voltage range of the first transistor T 1 . In  FIG.  8   , the threshold voltage may refer to the gate voltage when the driving current of 10 nA is flowing. In  FIG.  8   , the channel length of the first channel region CP 1  of the first transistor T 1  and the channel length of the second channel region CP 2  of the second transistor T 2  may be 3.5 μm. 
     Referring to  FIG.  8   , when the turn-on voltage is applied to the first gate electrode G 1  of the first transistor T 1 , the driving current is 6.33×10 −6  A. When the turn-off voltage is applied to the first gate electrode G 1  of the first transistor T 1 , the driving current is 2.54×10 −13  A. In addition, the electron mobility of the first transistor T 1  may be 3.20 cm 2 /V×s, and the driving voltage range DR may be 3.54 V. The threshold voltage Vth of the first transistor T 1  may be 1.07 V. 
     By connecting the light shielding layer BML located under the first channel region CP 1  of the first active layer ACT 1  with the first source electrode S 1 , the electron mobility of the first channel region CH 1  of the first active layer ACT 1  can be reduced, such that the slope of the driving current curve of the first transistor T 1  can be decreased. Accordingly, when the first source electrode S 1  is connected to the light shielding layer BML, the driving voltage range DR of the first transistor T 1  can be widened, compared with the driving voltage range DR of the first transistor T 1  not including the light shielding BML. 
       FIG.  9    is a flowchart for illustrating a method of fabricating a display device according to some example embodiments of the present disclosure.  FIGS.  10  to  19    are cross-sectional views of a first transistor and a second transistor for illustrating a method of fabricating a display device according to some example embodiments of the present disclosure. 
     Hereinafter, a method of fabricating a display device according to some example embodiments will be described in more detail with reference to  FIGS.  9  to  19   . 
     Firstly, as shown in  FIG.  10   , a buffer layer BF is formed on a substrate SUB, and a first active layer ACT 1  of a first transistor T 1  and a second active layer ACT 2  of a second transistor T 2  are formed on the buffer layer BF (step S 101  in  FIG.  9   ). 
     For example, the buffer layer BF may be formed by using plasma-enhanced chemical vapor deposition (PECVD) technique. 
     Subsequently, an active material layer may be formed on the buffer layer BF, and a photoresist pattern may be formed on the active material layer. The active material layer may be an oxide semiconductor including indium (In), gallium (Ga), and oxygen (O). For example, the active material layer may be made of IGZO (Indium (In), Gallium (Ga), Zinc (Zn) and Oxygen (O)), IGZTO (Indium (In), Gallium (Ga), Zinc (Zn), Tin (Sn) and Oxygen (O)) or IGTO (indium (In), gallium (Ga), tin (Sn) and oxygen (O)). The active material layer may be formed by using sputtering or metal-organic chemical vapor deposition (MOCVD) technique. 
     Subsequently, the active material layer not covered by the photoresist pattern is etched to form the first active layer ACT 1  and the second active layer ACT 2 . Subsequently, the photoresist pattern may be removed via a stripping process. 
     Secondly, as shown in  FIGS.  11  to  13   , a first gate insulating layer  131  is formed on a portion of the first active layer ACT 1  of the first transistor T 1 , and a first gate electrode G 1  is formed on the first gate insulating layer  131  (step S 102  in  FIG.  9   ). 
     For example, as shown in  FIG.  11   , a first gate insulating material layer  131 ′ may be formed on the first active layer ACT 1  and the second active layer ACT 2 . In addition, the first gate insulating material layer  131 ′ may be formed on a part of the buffer layer BF that is not covered by the first active layer ACT 1  and the second active layer ACT 2 . The first gate insulating material layer  131 ′ may be formed as an inorganic layer, for example, a silicon oxide layer. The first gate insulating material layer  131 ′ may be formed by using PECVD technique. 
     Subsequently, a first gate metal layer GM 1  may be formed on the first gate insulating material layer  131 ′. The first gate metal layer GM 1  may be made up of a single layer or multiple layers of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) or an alloy thereof. The first gate metal layer GM 1  may be formed by using sputtering or MOCVD technique. 
     Subsequently, a photoresist pattern PR 1  may be formed on first gate metal layer GM 1 . The photoresist pattern PR 1  may overlap with a portion of the first active layer ACT 1  in the first direction DR 1 . 
     Subsequently, as shown in  FIG.  12   , the first gate electrode G 1  may be formed by wet or dry etching the first gate metal layer GM 1  using the photoresist pattern PR 1  as a mask. Subsequently, the first gate insulating layer  131  may be formed by dry etching the first gate insulating material layer  131 ′ by using the first gate electrode G 1  as a mask. In doing so, a portion of the first active layer ACT 1  that is not covered by the first gate insulating layer  131  may be exposed to a plasma during the dry etching process and may become the first source region SP 1  having conductivity. In addition, another portion of the first active layer ACT 1  that is not covered by the first gate insulating layer  131  may be exposed to a plasma during the dry etching process and may become the first drain region DP 1  having conductivity. 
     Subsequently, as shown in  FIG.  13   , the photoresist pattern PR 1  may be removed via a stripping process. 
     Thirdly, as shown in  FIGS.  14  to  18   , a second gate insulating layer  132  and a second gate electrode G 2  are formed on a portion of the second active layer ACT 2  of the second transistor T 2 , and the second gate insulating layer  132  and a capacitor electrode CE are formed on the first gate electrode G 1  of the first transistor T 1  (step S 103  of  FIG.  9   ). 
     For example, as shown in  FIG.  14   , the second gate insulating material layer  132 ′ may be formed on the first gate electrode G 1 . In addition, the second gate insulating material layer  132 ′ may be formed on side surfaces of the first gate insulating layer  131 . In addition, the second gate insulating material layer  132 ′ may be formed on the first active layer ACT 1  not covered by the first gate insulating layer  131 . In addition, the second gate insulating material layer  132 ′ may be formed on the second active layer ACT 2 . In addition, the second gate insulating material layer  132 ′ may be formed on a part of the buffer layer BF that is not covered by the first active layer ACT 1  and the second active layer ACT 2 . The second gate insulating material layer  132 ′ may be formed as an inorganic layer, for example, a silicon oxide layer. The second gate insulating material layer  132 ′ may be formed by using PECVD technique. 
     Subsequently, as shown in  FIG.  14   , an oxygen supply layer  133  may be formed on the second gate insulating material layer  132 ′ as shown in  FIG.  14   . Oxygen is supplied to the second gate insulating material layer  132 ′ by an oxygen plasma during a process of depositing the oxygen supply layer  133 , and oxygen may be supplied to the second active layer ACT 2  via a heat treatment process after deposition of the oxygen supply layer  133 . By doing so, the second active layer ACT 2 , which has been exposed to the plasma during the dry etching process for forming the first gate insulating layer  131  to become a conductor, may become a semiconductor layer again. 
     The oxygen supply layer  133  may be made of the same material as the second active layer ACT 2 . The oxygen supply layer  133  may be an oxide semiconductor including indium (In), gallium (Ga), and oxygen (O). For example, the oxygen supply layer  133  may be made of IGZO (Indium (In), Gallium (Ga), Zinc (Zn) and Oxygen (O)), IGZTO (Indium (In), Gallium (Ga), Zinc (Zn), Tin (Sn) and Oxygen (O)) or IGTO (indium (In), gallium (Ga), tin (Sn) and oxygen (O)). The oxygen supply layer  133  may be formed by using sputtering or metal-organic chemical vapor deposition (MOCVD) technique. 
     Subsequently, the oxygen supply layer  133  is wet etched and removed as shown in  FIG.  15   . 
     Subsequently, as shown in  FIG.  16   , the second gate metal layer GM 2  may be formed on the second gate insulating material layer  132 ′. The second gate metal layer GM 2  may be made up of a single layer or multiple layers of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or an alloy thereof. The second gate metal layer GM 2  may be formed by using sputtering or MOCVD technique. 
     Subsequently, a photoresist pattern PR 2  may be formed on second gate metal layer GM 2 . The photoresist pattern PR 2  may overlap with a portion of the second active layer ACT 2  in the first direction DR 1 . The photoresist pattern PR 2  may overlap the first gate electrode G 1  in the first direction DR 1 . 
     Subsequently, as shown in  FIG.  17   , the second gate metal layer GM 2  not covered by the photoresist pattern PR 2  may be wet or dry etched to form the second gate electrode G 2  and the capacitor electrode CE. Subsequently, the second gate insulating layer  132  may be formed by dry etching the second gate insulating material layer  132 ′ by using the second gate electrode G 2  and the capacitor electrode CE as masks. In doing so, a portion of the second active layer ACT 2  that is not covered by the second gate insulating layer  132  may be exposed to a plasma during the dry etching process and may become the second source region SP 2  having conductivity. In addition, another portion of the second active layer ACT 2  that is not covered by the second gate insulating layer  132  may be exposed to a plasma during the dry etching process and may become the second drain region DP 2  having conductivity. 
     Subsequently, as shown in  FIG.  18   , the photoresist pattern PR 2  may be removed (e.g., by way of any suitable stripping process). 
     Fourthly, as shown in  FIG.  19   , an interlayer dielectric layer  140  is formed on the second gate electrode G 2  of the second transistor T 2  and the capacitor electrode CE, and contact holes CT 1 , CT 2 , CT 3 , CT 4  and CT 5  are formed in the interlayer dielectric layer  140  (step S 104  in  FIG.  9   ). 
     For example, as shown in  FIG.  19   , the interlayer dielectric layer  140  is formed on the second gate electrode G 2  of the second transistor T 2  and the capacitor electrode CE. In addition, the interlayer dielectric layer  140  is formed on side surfaces of the second gate insulating layer  132 . In addition, the interlayer dielectric layer  140  is formed on the first active layer ACT 1  and the second active layer ACT 2  not covered by the second gate insulating layer  132 . In addition, the interlayer dielectric layer  140  may be formed on the buffer layer BF not covered by the first active layer ACT 1  and the second active layer ACT 2 . The interlayer dielectric layer  140  may be formed as an inorganic layer, for example, a silicon oxide layer. The interlayer dielectric layer  140  may be formed by a PECVD technique. 
     Subsequently, a photoresist pattern may be formed on the interlayer dielectric layer  140 . Subsequently, the interlayer dielectric layer  140  may be etched to form contact holes CT 1 , CT 2 , CT 3 , CT 4  and CT 5 , and the photoresist pattern PR 2  may be removed via a stripping process. 
     The first contact hole CT 1  may be a hole penetrating through the interlayer dielectric layer  140  to expose the first source region SP 1  of the first active layer ACT 1 . The second contact hole CT 2  may be a hole that penetrates through the interlayer dielectric layer  140  to expose the first drain region DP 1  of the first active layer ACT 1 . The third contact hole CT 3  may be a hole that penetrates through the interlayer dielectric layer  140  to expose the capacitor electrode CE. The fourth contact hole CT 4  may be a hole that penetrates through the interlayer dielectric layer  140  to expose the second source region SP 2  of the second active layer ACT 2 . The fifth contact hole CT 5  may be a hole that penetrates through the interlayer dielectric layer  140  to expose the second drain region DP 2  of the second active layer ACT 2 . 
     Fifthly, as shown in  FIG.  20   , a first source electrode S 1  and a first drain electrode D 1  of a first transistor T 1 , a second source electrode S 2  and a second drain electrode D 2  of a second transistor T 2 , and a first supply voltage line VDDL may be formed on the interlayer dielectric layer  140  (step S 105  of  FIG.  9   ). 
     For example, a source-drain metal layer SDM is formed on the interlayer dielectric layer  140 . A source-drain metal layer SDM may be made up of a single layer or multiple layers of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or an alloy thereof. The source-drain metal layer SDM may be formed by using sputtering or MOCVD technique. 
     Subsequently, a photoresist pattern may be formed on the source-drain metal layer SDM. The source-drain metal layer SDM not covered by the photoresist pattern is etched to form the first source electrode S 1 , the first drain electrode D 1 , the second source electrode S 2 , the second drain electrode D 2  and the first supply voltage line VDDL, and the photoresist pattern may be removed via a stripping process. The first source electrode S 1  may be connected to the first source region SP 1  through the first contact hole CT 1 . The first drain electrode D 1  may be connected to the first drain region DP 1  through the second contact hole CT 2 . The first supply voltage line VDDL may be connected to the capacitor electrode CE through the third contact hole CT 3 . The second source electrode S 2  may be connected to the second source region SP 2  through the fourth contact hole CT 4 . The second drain electrode D 2  may be connected to the second drain region DP 2  through the fifth contact hole CT 5 . 
     Sixthly, as shown in  FIG.  21   , a passivation layer  150  and a planarization layer  160  are formed, a first electrode  171 , a bank layer  180 , an emissive layer  172  and a second electrode  173  are formed on the planarization layer  160 , and an encapsulation layer  190  is formed on the second electrode  173  (step S 106  in  FIG.  9   ). 
     For example, as shown in  FIG.  21   , the passivation layer  150  may be formed on the first source electrode S 1 , the first drain electrode D 1 , the second source electrode S 2 , the second drain electrode D 2  and the first supply voltage line VDDL. In addition, the passivation layer  150  may be formed on a pr of the interlayer dielectric layer  140  that is not covered by the first source electrode S 1 , the first drain electrode D 1 , the second source electrode S 2 , the second drain electrode D 2  and the first supply voltage line VDDL. The passivation layer  150  may be formed by a PECVD technique. 
     Subsequently, the planarization layer  160  is formed on the passivation layer  150 , and a sixth contact hole CT 6  is formed through the planarization layer  160  and the passivation layer  150  to expose the first drain electrode D 1 . 
     Subsequently, a first metal layer ML 1  is formed on the planarization layer  160 . In a top-emission structure, the first metal layer ML 1  may be formed as a stack structure of aluminum and titanium (Ti/Al/Ti), a stack structure of aluminum and ITO (ITO/Al/ITO), an APC alloy and a stack structure of an APC alloy and ITO (ITO/APC/ITO). Alternatively, the first metal layer ML 1  may be made up of a single layer of molybdenum (Mo), titanium (Ti), copper (Cu), or aluminum (Al). The first metal layer ML 1  may be formed by using sputtering or MOCVD technique. 
     Subsequently, a photoresist pattern may be formed on the first metal layer ML 1 . The first electrode  171  may be formed by etching the first metal layer ML 1  not covered by the photoresist pattern. The first electrode  171  may be connected to the fifth drain electrode of the fifth transistor T 5  through the sixth contact hole. 
     Subsequently, the bank layer  180  may be formed to cover the edge of the first electrode  171 . 
     Subsequently, the emissive layer  172  may be formed on the first electrode  171  which is not covered by the bank layer  180  and the bank layer  180 . The emissive layer  172  may include a hole transporting layer, an organic material layer, and an electron transporting layer. 
     Subsequently, the second electrode  173  may be formed on the emissive layer  172 . 
     Subsequently, an encapsulation layer  190  may be formed on the second electrode  173 . The encapsulation layer  190  may include at least one inorganic layer to prevent or reduce oxygen, moisture, or other contaminants from permeating into the emissive layer  172  and the second electrode  173 . In addition, the encapsulation layer  190  may include at least one organic layer to protect the emissive layer  172  from foreign substances such as dust. 
     Alternatively, a substrate may be located on the second electrode  173  instead of the encapsulation layer  190 , such that the space between the second electrode and the substrate may be empty in vacuum state or a filler film may be arranged therein. The filler film may be an epoxy filler film or a silicon filler film. 
       FIG.  22    is a flowchart for illustrating a method of fabricating a display device according to some example embodiments of the present disclosure.  FIGS.  23  to  25    are cross-sectional views of a first transistor and a second transistor in the steps S 201 , S 204 , and S 205  of  FIG.  22   . 
     Hereinafter, a method of fabricating a display device according to some example embodiments will be described in more detail with reference to  FIGS.  22  to  25   . 
     Firstly, as shown in  FIG.  23   , a light shielding layer BML is formed on a substrate SUB, a buffer layer BF is formed on the light shielding layer BML, and a first active layer ACT 1  of a first transistor T 1  and a second active layer ACT 2  of a second transistor T 2  are formed on the buffer layer BF (step S 201  in  FIG.  22   ). 
     For example, a light shielding material layer BML′ may be formed on a substrate SUB. The light shielding material layer BML′ may be made up of a single layer or multiple layers of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or an alloy thereof. The first gate metal layer GM 1  may be formed by using sputtering or MOCVD technique. 
     Subsequently, a photoresist pattern may be formed on the light shielding material layer BML′, and the light shielding material layer BML′ which is not covered by the photoresist pattern may be etched to form the light shielding layer BML. 
     Subsequently, the buffer layer BF may be formed on the light shielding layer BML. The buffer layer BF may be formed on the substrate SUB not covered by the light shielding layer BML. 
     The process of forming the first active layer ACT 1  of the first transistor T 1  and the second active layer ACT 2  of the second transistor T 2  on the buffer layer BF in step S 201  of  FIG.  22    is substantially identical to step S 101  of  FIG.  9   ; and, therefore, the redundant description will be omitted. 
     In addition, operations S 201 , S 202  and S 203  of  FIG.  22    are substantially identical to operations S 201 , S 202  and S 203  of  FIG.  9   ; and, therefore, some redundant description may be omitted. 
     Fourthly, as shown in  FIG.  24   , an interlayer dielectric layer  140  is formed on the second gate electrode G 2  of the second transistor T 2  and the capacitor electrode CE, and contact holes CT 1 , CT 2 , CT 3 , CT 4 , CT 5  and CT 7  are formed in the interlayer dielectric layer  140  (step S 204  in  FIG.  22   ). 
     Operation S 204  of  FIG.  22    is substantially identical to the operation S 104  of  FIG.  9    except for the seventh contact hole CT 7 . 
     The seventh contact hole CT 7  may be a hole that penetrates through the interlayer dielectric layer  140  and the buffer film BF to expose the light shielding layer BML. 
     Fifthly, as shown in  FIG.  25   , a first source electrode S 1  and a first drain electrode D 1  of a first transistor T 1 , a second source electrode S 2  and a second drain electrode D 2  of a second transistor T 2 , and a first supply voltage line VDDL may be formed on the interlayer dielectric layer  140  (operation S 205  of  FIG.  22   ). 
     The operation S 205  of  FIG.  22    is substantially identical to operation S 105  of  FIG.  9   ; and, therefore, some redundant description will be omitted. 
     In addition, operation S 206  of  FIG.  22    is substantially identical to the operation S 106  of  FIG.  9   ; and, therefore, some redundant description will be omitted. 
     Although aspects of some example embodiments of the present disclosure have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of embodiments according to the present disclosure as defined by the accompanying claims and equivalents thereof.