Patent Publication Number: US-9900539-B2

Title: Solid-state image pickup element, and image pickup system

Description:
BACKGROUND OF THE INVENTION 
     Field of the Invention 
     The present invention relates to a technology of reducing magnetic noise caused in ground wiring in a solid-state image pickup element. 
     Description of the Related Art 
     In recent years, higher and higher image quality is desired in a solid-state image pickup element. In order to realize high image quality, noise suppression is essential. As such a method of suppressing noise, a technology of suppressing noise caused by a power supply configured to drive the solid-state image pickup element is described in, for example, Japanese Patent Application Laid-Open No. 2008-85994. In the technology described in Japanese Patent Application Laid-Open No. 2008-85994, noise is suppressed through holding, in a hold capacitor, a reference signal of a readout circuit. 
     In the related art described in Japanese Patent Application Laid-Open No. 2008-85994, noise caused in a signal line of the readout circuit can be suppressed, but noise caused in ground wiring is not taken into consideration. However, when there is a magnetic field, the influence of magnetic noise on the ground wiring cannot be neglected. The reason is that, when the ground wiring, together with a substrate inside or outside the solid-state image pickup element, is in the shape of a loop, induced electromotive force by Faraday&#39;s Law is caused in the ground wiring, and appears on a sensor output image as magnetic noise. Therefore, the technology described in Japanese Patent Application Laid-Open No. 2008-85994 has a problem in that magnetic noise caused in the ground wiring cannot be reduced. 
     SUMMARY OF THE INVENTION 
     According to one embodiment of the present invention, there is provided a solid-state image pickup element, comprising: a semiconductor substrate including a pixel well region and a peripheral well region; a pixel ground wiring arranged on the pixel well region; a peripheral ground wiring arranged on the peripheral well region; a plurality of pixel well contacts connecting the pixel ground wiring and the pixel well region; a plurality of peripheral well contacts connecting the peripheral ground wiring and the peripheral well region; a plurality of pixels arranged in the pixel well region in a plurality of columns, each of the plurality of pixels being configured to output a pixel signal; a readout circuit arranged in the peripheral well region, the readout circuit including a first input terminal configured to receive the pixel signal from each of the plurality of pixels and a second input terminal configured to receive a reference signal; a reference signal circuit arranged in the peripheral well region, the reference signal circuit including a first electrode to which a ground voltage is supplied, and being configured to output the reference signal to the second input terminal of the readout circuit; and a wiring connecting the first electrode of the reference signal circuit and the pixel ground wiring, wherein a resistance value R 1  of an electrical path from one of the plurality of pixel well contacts to the first electrode and a resistance value R 2  of an electrical path from one of the plurality of peripheral well contacts closest to the first electrode to the first electrode satisfy a relationship of R 1 &lt;R 2 . 
     Further features of the present invention will become apparent from the following description of exemplary embodiments with reference to the attached drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a schematic illustration of a configuration of a solid-state image pickup element according to a first embodiment of the present invention. 
         FIG. 2  is a schematic plan view for illustrating a configuration of a hold capacitor according to the first embodiment of the present invention. 
         FIG. 3  is a schematic sectional view for illustrating the configuration of the hold capacitor according to the first embodiment of the present invention. 
         FIG. 4  is a schematic plan view for illustrating a configuration of a ground connecting part according to the first embodiment of the present invention. 
         FIG. 5  is a schematic sectional view for illustrating a configuration of a package including the solid-state image pickup element according to the first embodiment of the present invention. 
         FIG. 6  is a schematic illustration of an equivalent circuit of a ground loop and a ground voltage distribution in the solid-state image pickup element according to the first embodiment of the present invention. 
         FIG. 7  is a schematic plan view for illustrating a configuration of a ground connecting part according to a second embodiment of the present invention. 
         FIG. 8  is a schematic plan view for illustrating a configuration of a ground connecting part according to a third embodiment of the present invention. 
         FIG. 9  is a schematic plan view for illustrating a configuration of a ground connecting part according to a fourth embodiment of the present invention. 
         FIG. 10  is a schematic illustration of a configuration of a solid-state image pickup element according to a fifth embodiment of the present invention. 
         FIG. 11  is a schematic illustration of an equivalent circuit of a ground loop and a ground voltage distribution in the solid-state image pickup element according to the fifth embodiment of the present invention. 
         FIG. 12A  is a first graph for showing magnetic noise included in input to an AD converter according to the fifth embodiment of the present invention. 
         FIG. 12B  is a second graph for showing magnetic noise included in input to the AD converter according to the fifth embodiment of the present invention. 
         FIG. 12C  is a third graph for showing magnetic noise included in input to the AD converter according to the fifth embodiment of the present invention. 
         FIG. 13  is a schematic illustration of a configuration of a solid-state image pickup element according to a sixth embodiment of the present invention. 
         FIG. 14  is a schematic sectional view for illustrating a configuration of a solid-state image pickup element according to the sixth embodiment of the present invention. 
         FIG. 15  is a schematic illustration of an equivalent circuit of a ground loop and a ground voltage distribution in the solid-state image pickup element according to the sixth embodiment of the present invention. 
         FIG. 16  is an illustration of a configuration of an image pickup system according to a seventh embodiment of the present invention. 
     
    
    
     DESCRIPTION OF THE EMBODIMENTS 
     Preferred embodiments of the present invention will now be described in detail in accordance with the accompanying drawings. 
     First Embodiment 
     A solid-state image pickup device according to a first embodiment of the present invention is described with reference to  FIG. 1  to  FIG. 6 .  FIG. 1  is a schematic illustration of a configuration of a solid-state image pickup element  1  according to the first embodiment of the present invention. The solid-state image pickup element  1  illustrated in  FIG. 1  includes a pixel well region  101 , peripheral well regions  100 , a vertical scanning circuit  70 , and a peripheral circuit control unit  71 . Each of the pixel well region  101  and the peripheral well region  100  is a semiconductor region formed on a semiconductor substrate. Pixel ground wiring  51  is arranged so as to completely overlap the pixel well region  101  when the semiconductor substrate is seen in plan view. Peripheral ground wiring  50  is arranged so as to completely overlap the peripheral well region  100  when the semiconductor substrate is seen in plan view. A pixel array is arranged in the pixel well region  101  in which the pixel ground wiring  51  is arranged, and a plurality of pixels  10  are two-dimensionally arranged therein in a row direction and in a column direction. Each pixel  10  includes a photoelectric convertor and an amplifier unit configured to output a signal based on charge generated by the photoelectric convertor. A signal depending on light is output from each pixel  10 . The vertical scanning circuit  70  is, for example, a shift register, and controls drive of the pixels  10  row by row. The drive control includes reset operation of, accumulation operation in, and signal readout operation from the pixels  10 . 
     Differential amplifier circuits  30  are arranged in the peripheral well region  100  in which the peripheral ground wiring  50  is arranged. A plurality of differential amplifier circuits  30  are arranged correspondingly to a plurality of columns of the plurality of pixels  10 . The differential amplifier circuit  30  reads a signal from a plurality of pixels  10  included in a column corresponding thereto with reference to a reference signal. More specifically, the differential amplifier circuit  30  amplifies a difference between a signal that is input to a non-inverting input terminal (+) thereof and a signal that is input to an inverting input terminal (−) thereof and outputs the amplified signal to an image signal processing unit outside the solid-state image pickup element  1  (see  FIG. 13  referred to below). In this case, pixel signals from a plurality of pixels  10  in the same column are input to the inverting input terminal (−) via corresponding one of a plurality of vertical signal lines  20  formed for the columns, respectively. Meanwhile, a control electrode of a hold capacitor  200  is connected to the non-inverting input terminal (+) and the reference signal is input to the non-inverting input terminal (+) via a switch transistor  300 . A ground electrode of the hold capacitor  200  is connected to the pixel ground wiring  51 . The hold capacitor  200  and the switch transistor  300  form a reference signal circuit configured to output the reference signal to the non-inverting input terminal (+). A reference signal source configured to supply the reference signal may be arranged in the solid-state image pickup element  1 . Alternatively, the reference signal may be supplied from the outside of the solid-state image pickup element  1 . A feedback unit and the like of the differential amplifier circuit  30  are omitted in the illustration of  FIG. 1 . 
     Through turning off the switch transistor  300 , the hold capacitor  200  holds a reference signal Vref supplied from the reference signal source. Further, the switch transistor  300  is connected to the control electrode of the hold capacitor  200 , and charges and discharges charge depending on the reference signal Vref held by the hold capacitor  200  in accordance with a control pulse P 1  that is output from the peripheral circuit control unit  71  (see, for example, Japanese Patent Application Laid-Open No. 2008-85994). More specifically, when the switch transistor  300  is turned on before the operation of reading a signal from the pixel  10 , the reference signal Vref is output to the non-inverting input terminal (+) of the differential amplifier circuit  30 . At the same time, charge depending on the reference signal Vref is charged in the hold capacitor  200 . When charge depending on the reference signal Vref is charged in the hold capacitor  200 , even if the switch transistor  300  is turned off, the reference signal Vref for the operation of reading the signal from the pixel  10  is output from the hold capacitor  200 . Therefore, through turning off the switch transistor  300 , noise caused by the reference signal source can be reduced. 
     A plurality of peripheral well contacts  43  configured to connect the peripheral well region  100  and the peripheral ground wiring  50  are arranged on the peripheral well region  100 . The peripheral ground wiring  50  is electrically connected to an external ground voltage outside the solid-state image pickup element  1  via an external ground terminal  60 . On the other hand, a plurality of pixel well contacts  42  configured to connect the pixel well region  101  and the pixel ground wiring  51  are arranged on the pixel well region  101 . Further, the pixel ground wiring  51  is electrically connected to the peripheral ground wiring  50  via a ground connecting part  52 . Ground terminals of the photoelectric convertors and the amplifier units of the respective pixels  10  (hereinafter simply referred to as “ground terminals of the pixels  10 ”) are electrically connected to the pixel ground wiring  51  via the pixel well contacts  42 . The pixel well region  101  forms the ground terminals of the pixels  10 . The pixel well contacts  42  and the peripheral well contacts  43  are not necessarily required to be regularly arranged as illustrated in  FIG. 1 . 
       FIG. 2  is a schematic plan view for illustrating a configuration of the hold capacitor  200  according to the first embodiment of the present invention. Further,  FIG. 3  is a schematic sectional view for illustrating the configuration of the hold capacitor  200  according to the first embodiment of the present invention.  FIG. 3  is a sectional view taken along the dot-and-dash line L-L′ of  FIG. 2 . As illustrated in  FIG. 3 , the hold capacitor  200  includes a control electrode  54  and a ground electrode  53 . The control electrode  54  is supplied with the reference signal Vref from the reference signal source. The ground electrode  53  is connected to the pixel ground wiring  51  via a first contact  48 . Further, the control electrode  54  is connected to the switch transistor  300  via a second contact  47  and wiring  58 . 
     The ground electrode  53  and the control electrode are formed of a conductive material. Further, it is only necessary that the first contact  48  electrically connect the ground electrode  53  of the hold capacitor  200  to the pixel ground wiring  51 . The first contact  48  and the pixel ground wiring  51  may be connected to each other via separate additional wiring. In this embodiment, the material forming the ground electrode  53  and the material forming the first contact  48  are different from each other. An end of the ground electrode  53  may be defined by an interface with a different material. In general, a process of forming the ground electrode  53  and a process of forming the first contact  48  are different from each other. For example, the ground electrode  53  is formed by patterning a metal layer. On the other hand, the first contact  48  is formed by embedding metal in a through hole formed in an insulating layer. As a modified example, the ground electrode  53  and the first contact  48  may be formed of the same material. For example, when the wiring is formed by a dual damascene process, the ground electrode  53  and the first contact  48  can be formed of the same material. In this case, a conductive material different from the material of the ground electrode  53  and the first contact  48 , for example, a barrier metal may be arranged between the ground electrode  53  and the first contact  48 . A plurality of processes of forming channels having different widths in the dual damascene process, which is used when the wiring is formed, are herein treated as different processes. Alternatively, the ground electrode  53  and the pixel ground wiring  51  may be integral with each other in the same wiring layer. This can eliminate the first contact  48 . In this case, the ground electrode  53  is formed simultaneously with the pixel ground wiring  51 . Further, an end of the ground electrode  53  is defined by projecting an end of the control electrode  54 , which is opposite thereto, in a direction perpendicular to a surface of the semiconductor substrate. Further, an end of the pixel ground wiring  51  is defined by projecting the pixel well region  101  in the direction perpendicular to the surface of the semiconductor substrate. Further, through arranging the hold capacitor  200  in a well region separated from the peripheral well region  100 , it is possible to use the separated well region as the ground electrode  53 . In other words, the ground electrode  53  may be formed of a semiconductor region having a predetermined impurity concentration. 
     It is only necessary that the second contact  47  can electrically connect the control electrode  54  of the hold capacitor  200  to the wiring  58  to which the reference signal Vref is supplied. The second contact  47  can be eliminated through integrating the control electrode  54  with the wiring  58  to which the reference signal Vref is supplied. 
       FIG. 4  is a schematic plan view for illustrating a configuration of the ground connecting part  52  according to the first embodiment of the present invention. As illustrated in  FIG. 4 , the ground connecting part  52  according to this embodiment has a feature of including intermediate wiring  63  having a serpentine layout in the column direction and in the row direction. The column direction is a direction along columns of the plurality of pixels  10 . The row direction is a direction intersecting the columns of the plurality of pixels  10 . In general, such a wiring layout is not adopted for the reason that the layout needs a larger area. However, in this embodiment, the intermediate wiring  63  is intentionally laid out as described above. Consequently, the peripheral ground wiring  50  and the pixel ground wiring  51  are connected to each other with a high resistance to enable reduction of magnetic noise caused in the ground wiring as described later. An effect of this embodiment is described below. When the solid-state image pickup element  1  is applied to an image pickup system such as a camera, for example, a magnetic field generated by a motor for driving a lens of the camera is a magnetic noise source that affects the ground wiring. 
       FIG. 5  is a schematic sectional view for illustrating a configuration of a package including the solid-state image pickup element  1  according to the first embodiment of the present invention.  FIG. 5  is an illustration of a configuration in which the solid-state image pickup element  1  illustrated in  FIG. 1  is supported by a package  80 . In  FIG. 5 , the peripheral ground wiring  50 , the pixel ground wiring  51 , and the ground connecting part  52  illustrated in  FIG. 1  are collectively illustrated as single ground wiring  55 . The ground wiring  55  is electrically connected to external ground wiring  90 , which is inner layer wiring of the package, via the external ground terminal  60 , wire bonding  61 , and a through via  62  of the package. In this case, the wire bonding  61  connects the external ground terminal  60  to the through via  62 . In such a package configuration, the ground wiring  55  and the external ground wiring  90  form a loop (hereinafter referred to as “ground loop”). 
       FIG. 6  is a schematic illustration of an equivalent circuit of the ground loop and a ground voltage distribution in the solid-state image pickup element  1  according to the first embodiment of the present invention. In the upper part of  FIG. 6 , there is illustrated a circuit equivalent to the ground loop illustrated in  FIG. 5  for one column of pixels. In a field in which a magnetic field is present, when a magnetic flux B pierces the ground loop, an induced electromotive force V depending on change in the magnetic flux B over time is caused in the ground loop in accordance with Faraday&#39;s Law. The relationship between the induced electromotive force V that is caused and change ΔB in magnetic flux B in a micro time Δt is expressed as V=−ΔB/Δt. 
     When the magnetic flux B is in the opposite direction by 180°, the direction of the electromotive force and the direction of the current are in the opposite directions. Further, when the magnetic flux B is in a slanting direction with respect to a plane of the loop of the ground wiring, electromotive force is caused by a component of the magnetic flux B in a direction perpendicular to the plane of the loop. The electromotive force causes a voltage distribution in the ground loop in which the voltage is originally uniform, and the signal from the pixel  10  is influenced by the ground voltage distribution. This appears as pattern noise (magnetic noise) in an image output by the solid-state image pickup element  1 . The external ground wiring  90  is not necessarily required to be in the package. Even when the solid-state image pickup element  1  is connected to a PCB substrate, if the ground loop is formed as described above, electromotive force is caused. Further, the ground loop is not necessarily required to be an electrically closed loop. For example, even when there is a break in the external ground wiring  90 , the induced electromotive force V may be caused across the ground wiring  55  of the solid-state image pickup element  1 . 
     Correspondence between the configuration of the solid-state image pickup element  1  illustrated in  FIG. 1  and the equivalent circuit of the ground loop illustrated in  FIG. 6  is described below. First, points A to C,  0  to Q, S, and S′ on the ground loop illustrated in  FIG. 1  are described. As described above, the first contact  48  illustrated in  FIG. 3  connects the ground electrode  53  of the hold capacitor  200  to the pixel ground wiring  51  in the pixel well region  101 . A point of contact between the first contact  48  and the ground electrode  53  is referred to as the point A. The point A illustrated in  FIG. 1  is, strictly speaking, not on the ground loop, but is located on the first contact  48  that connects the ground electrode  53  of the hold capacitor  200  to the ground loop. However, in this embodiment, the components from the pixel ground wiring  51  to the hold capacitor  200  are connected with low resistance wiring, and thus, the voltage can be regarded as being approximately uniform. Therefore, in  FIG. 6 , the point A is illustrated on the ground loop. 
     Next, in the pixel well region  101 , among the plurality of pixel well contacts  42  connected to the pixel ground wiring  51 , a pixel well contact  42  having the smallest electrical resistance value to the point A is referred to as the point B. Similarly, in the peripheral well region  100 , among the plurality of peripheral well contacts  43  connected to the peripheral ground wiring  50 , a peripheral well contact  43  that is arranged closest to the ground electrode  53  is referred to as the point C. In this embodiment, when electrical resistance values from the plurality of peripheral well contacts  43 , respectively, to the ground electrode  53  are compared to each other, the electrical resistance value from the peripheral well contact  43  arranged at the point C to the ground electrode  53  is the smallest. The point A, the point B, and the point C are illustrated in  FIG. 1 . 
     Next, among the peripheral well contacts  43  connected to the ground terminals of the differential amplifier circuits  30 , a peripheral well contact  43  having the smallest electrical resistance value to the point A is referred to as the point Q. The ground terminal of the differential amplifier circuit  30  is, for example, a source region of a MOS transistor included in the differential amplifier circuit  30 . The ground terminal of the differential amplifier circuit  30  is connected to the peripheral ground wiring. Further, a pixel well contact  42  connected to the ground terminal of the pixel  10  that is the farthest from the differential amplifier circuit  30  in the same column as the differential amplifier circuit  30  is referred to as the point S. Similarly, a pixel well contact  42  connected to the ground terminal of the pixel  10  that is the closest to the differential amplifier circuit  30  in the same column as the differential amplifier circuit  30  is referred to as the point S′. When there are a plurality of points S or S′, a peripheral well contact  43  having the smallest electrical resistance value from the ground terminal of the pixel  10  is representatively referred to as the point S or the point S′. The point Q, the point S, and the point S′ are illustrated in  FIG. 1 . 
     Among the external ground terminals  60  connecting the peripheral ground wiring  50  to a reference voltage outside the solid-state image pickup element  1 , the external ground terminal  60  connected to the ground terminal of the differential amplifier circuit  30  without passing through the pixel ground wiring  51  is referred to as the point P. Further, the external ground terminal  60  connected to the ground terminal of the differential amplifier circuit  30  via the pixel ground wiring  51  is referred to as the point O. The point P and the point O are illustrated in  FIG. 1 . 
     Next, electrical resistance values between the respective points in the equivalent circuit of the ground loop illustrated in  FIG. 6  are described with reference to  FIG. 1  and  FIG. 6 . Like reference symbols are used to designate like elements in  FIG. 1  and  FIG. 6 . First, the electrical resistance between the points A and P is described. The electrical resistance value between the points A and C is represented by R 2 . In this embodiment, the intermediate wiring  63  has a large electrical resistance value, and thus, R 2  can be regarded as being approximately equal to the electrical resistance value of the intermediate wiring  63 . Further, the electrical resistance values between the points C and P and between the points C and Q are sufficiently small with respect to the electrical resistance value R 2 , and are thus ignorable on the equivalent circuit. Therefore, the electrical resistance value between the points A and P is approximated as R 2 . Similarly, the electrical resistance value from the point A to the peripheral ground wiring  50  is approximated as R 2 . Further, the electrical resistance value from the point A to any one of the peripheral well contacts  43  connected to the peripheral ground wiring  50  is approximated as R 2 . 
     Next, the electrical resistance between the points A and S is described. The electrical resistance value between the points A and B is represented by R 1  and the electrical resistance value between the points S′ and S is represented by R 11 . In this case, the point B and the point S′ are close to each other. The electrical resistance value between the points B and S′ is sufficiently small with respect to the electrical resistance value R 11  between the points S′ and S, and is thus ignorable on the equivalent circuit. Therefore, the electrical resistance value between the points A and S is approximated as R 11 +R 1 . 
     Next, the electrical resistance between the points S and  0  is described. A portion between the points S and  0  is equivalent to a portion between the points S′ and P in terms of the circuit, and thus, the portion between the points S and  0  can be regarded as being equivalent to a series connection between the points A and S′ (electrical resistance value R 1 ) and the points A and P (electrical resistance value R 2 ). Therefore, the electrical resistance value between the points S and  0  is approximated as R 1 +R 2 . 
     The pixel ground wiring  51  has an electrical resistance that is uniform within the plane, and thus, the electrical resistance value of the ground wiring is generally in proportion to the length of the wiring. It follows that, in general, R 11 &gt;R 1 . Further, R 1  actually includes the electrical resistance value of the wiring from the ground electrode  53  of the hold capacitor  200  to the pixel ground wiring  51 , but this electrical resistance value is sufficiently small with respect to R 11  and R 1 , and is thus ignorable on the equivalent circuit. 
     Taking the approximations described above into consideration, the electrical resistance values R 1 , R 11 +R 1 , and R 2  can be regarded as the electrical resistance value between the points A and S′, the electrical resistance value between the points A and S, and the electrical resistance value between the points A and Q, respectively, on the equivalent circuit. In other words, the electrical resistance values R 1  and R 11 +R 1  are approximated as the minimum value and the maximum value, respectively, of the electrical resistance values from the pixel well contacts  42 , which are connected to the ground terminals of the plurality of pixels  10  in the same column as the differential amplifier circuit  30 , to the first contact  48 . The electrical resistance values R 1  and R 11 +R 1  are resistance values of electrical paths on the pixel ground wiring  51 . Further, the electrical resistance value R 2  is approximated as the minimum value of the electrical resistance values from the peripheral well contacts  43  connected to the peripheral ground wiring  50  to the first contact  48 , that is, the electrical resistance value of the ground connecting part  52 . 
     In this embodiment, the relationship of R 1 &lt;R 2  is satisfied, and the following effect is provided. The relationship between the electrical resistance values between the respective points in the equivalent circuit of the ground loop illustrated in  FIG. 6  and the induced electromotive force is described. As described above, when the magnetic flux B pierces the ground loop, the induced electromotive force V depending on change in the magnetic flux B over time is caused in the ground loop.  FIG. 6  is an illustration of an induced voltage difference V 1  between the points A and S, an induced voltage difference V 2  between the points A and P, and an induced voltage difference V 3  between the points S and  0  of the induced electromotive force V caused in the ground loop. Those induced voltage differences V 1  to V 3  are the induced electromotive force V divided by the electrical resistance values in the corresponding portions, respectively, and thus, are expressed by Expressions (1) to (3) below.
 
 V 1= V ×( R 11+ R 1)/( R 11+2× R 1+2× R 2)  (1)
 
 V 2= V×R 2/( R 11+2× R 1+2× R 2)  (2)
 
 V 3= V ×( R 2+ R 1)/( R 11+2× R 1+2× R 2)  (3)
 
     The signal from the pixel  10  that is input to the inverting input terminal (−) of the differential amplifier circuit  30  includes, as magnetic noise, the induced voltage difference V 1 +V 2  at the point S at which the ground terminal of the pixel  10  is connected. On the other hand, the reference signal that is input to the non-inverting input terminal (+) of the differential amplifier circuit  30  includes, as magnetic noise, the induced voltage difference V 2  at the point A at which the ground electrode  53  of the hold capacitor  200  is connected. Therefore, a magnetic noise output Vout of the differential amplifier circuit  30  includes the induced voltage difference V 1  between the points A and S as expressed by Expression (4) below. 
     
       
         
           
             
               
                 
                   
                     
                       
                         Vout 
                         = 
                           
                         ⁢ 
                         
                           
                             ( 
                             
                               
                                 V 
                                 ⁢ 
                                 
                                     
                                 
                                 ⁢ 
                                 1 
                               
                               + 
                               
                                 V 
                                 ⁢ 
                                 
                                     
                                 
                                 ⁢ 
                                 2 
                               
                             
                             ) 
                           
                           - 
                           
                             ( 
                             
                               V 
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               2 
                             
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                         = 
                           
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     Therefore, when Expression (1) above is expressed as
 
 V 1= k×V   (1′)
 
where k=(R 11 +R 1 )/(R 11 + 2 ×R 1 +2×R 2 )&lt;1, it can be understood that the magnetic noise output Vout=k×V can be reduced through reducing the proportionality constant k by adjusting the electrical resistance values R 1 , R 11 , and R 2 . Thus, in this embodiment, through employing the serpentine layout of the intermediate wiring  63  in the column direction and in the row direction as illustrated in  FIG. 4 , the electrical resistance value R 2  of the ground connecting part  52  is increased so as to satisfy Expression (5) below.
 
 R 11+ R 1&lt; R 2  (5)
 
     When, for example, R 11 +R 1 &lt;R 2 , from Expressions (1) to (3) above, V 1 &lt;V 2  and V 1 &lt;V 3 , and thus, the magnetic noise output Vout (=V 1 ) can be reduced. 
     In the equivalent circuit illustrated in  FIG. 6 , the pixel  10  that is the farthest from the differential amplifier circuit  30  in the same column as the differential amplifier circuit  30  (having the electrical resistance value of R 11 +R 1 ) represents the pixel  10  connected to the inverting input terminal (−) of the differential amplifier circuit  30 , but other pixels  10  may be a representative. For example, the pixel  10  that is the closest to the differential amplifier circuit  30  in the same column as the differential amplifier circuit  30  (having the electrical resistance value of R 1 ) may represent the pixel  10  connected to the inverting input terminal (−). In this case, instead of Expression (5) above, Expression (6) below is applied.
 
 R 1&lt; R 2  (6)
 
     Also in this case, for example, when R 1 &lt;R 2 , similarly, V 1 &lt;V 2  and V 1 &lt;V 3 , and thus, the magnetic noise output Vout (=V 1 ) can be reduced. 
     As described above, a first feature of this embodiment is that the ground electrode  53  of the hold capacitor  200  is connected to the pixel ground wiring  51  via the first contact  48 . A second feature of this embodiment is that the electrical resistance value R 2  of the ground connecting part  52  that connects the pixel ground wiring  51  to the peripheral ground wiring  50  is set to be large so as to satisfy Expression (6) above. This can reduce magnetic noise caused in the ground wiring. 
     Here, a case in which the first feature of the present invention described above is not satisfied is considered. This is, for example, a case in which the ground electrode  53  of the hold capacitor  200  is connected not to the pixel ground wiring  51  (point A) but to the peripheral ground wiring  50  (point Q). In this case, the magnetic noise output Vout of the differential amplifier circuit  30  includes the induced voltage difference V 1 +V 2  between the points S and Q in the equivalent circuit illustrated in  FIG. 6  as expressed by Expression (7) below. 
     
       
         
           
             
               
                 
                   
                     
                       
                         Vout 
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                   7 
                   ) 
                 
               
             
           
         
       
     
     In this case, the electrical resistance values R 1 , R 11 , and R 2  are included both in the numerator and in the denominator of Expression (7) above, and thus, the magnetic noise output Vout cannot be reduced no matter how the electrical resistance values R 1 , R 11 , and R 2  are adjusted. 
     Next, a case in which the second feature of the present invention described above is not satisfied is considered. This is a case in which the electrical resistance value R 2  of the ground connecting part  52  does not satisfy Expression (5) or (6) and, for example, R 11 +R 1 &gt;&gt;R 2 . In this case, from (1) to (3), V 1 &gt;V 3 &gt;&gt;V 2 ≈0. Therefore, also in this case, the magnetic noise output Vout cannot be reduced. 
     As described above, in this embodiment, the readout circuit (differential amplifier circuit) is included that is arranged in the peripheral well region in which the peripheral ground wiring is arranged and that is configured to read a signal from a pixel in the same column with reference to the reference signal. Further, a first electrode (ground electrode) to which a ground voltage is supplied from the pixel ground wiring, a second electrode (control electrode) arranged so as to oppose the first electrode, and the reference signal circuit (hold capacitor) configured to output the reference signal to the readout circuit are included. Further, the minimum value R 2  of the electrical resistance values from the pixel ground wiring to the peripheral ground wiring is set to be large so as to satisfy Expression (6) above. Consequently, it is possible to obtain a solid-state image pickup element, a method of manufacturing a solid-state image pickup element, and an image pickup system that can reduce magnetic noise caused in the ground wiring without additionally providing a circuit for reducing the noise. 
     In  FIG. 4 , the ground connecting part  52  includes one intermediate wiring  63 , but the ground connecting part  52  may include a plurality of wirings. Further, it is only necessary that the ground connecting part  52  be electrically connected to the peripheral ground wiring  50  and the pixel ground wiring  51 . Further, a case is described in which each of the peripheral ground wiring  50  and the pixel ground wiring  51  is arranged in one layer, but the wirings may be arranged in a plurality of layers. Further, the peripheral ground wiring  50  and the pixel ground wiring  51  may have any shape. 
     Further, in  FIG. 1 , a layout is illustrated in which the peripheral well region  100  includes a first peripheral well region arranged on one side of the pixel well region  101  and a second peripheral well region arranged on another side thereof. However, the present invention is not limited to such a configuration. A similar effect can be obtained, for example, even when the first peripheral well region and the second peripheral well region are connected to each other around the pixel well region  101 , or even when the peripheral well region  100  includes only the first peripheral well region. 
     Second Embodiment 
     A solid-state image pickup device according to a second embodiment of the present invention is described with reference to  FIG. 7 .  FIG. 7  is a schematic plan view for illustrating a configuration of a ground connecting part  52   b  according to the second embodiment of the present invention. This embodiment is different from the first embodiment in that the ground connecting part  52   b  is electrically connected to the external ground voltage outside the solid-state image pickup element  1  via the external ground terminal  60 . Other points are the same as those of the first embodiment, and thus, description thereof is omitted. 
     In the ground connecting part  52   b  illustrated in  FIG. 7 , the intermediate wiring  63  according to the first embodiment illustrated in  FIG. 4  is electrically connected to the external ground voltage outside the solid-state image pickup element  1  via the external ground terminal  60 . Also in this case, similarly to the case of the first embodiment, the peripheral ground wiring  50  and the pixel ground wiring  51  are connected to each other with the large electrical resistance value R 2  depending on the length of the intermediate wiring  63 . Therefore, also in this embodiment, Expression (6) above is satisfied, and thus, magnetic noise caused in the ground wiring can be reduced. 
     The intermediate wiring  63  may be a plurality of wirings. Further, the intermediate wiring  63  may be connected to a connecting line configured to connect the peripheral ground wiring  50  to the external ground terminal  60  as illustrated in  FIG. 7 , or may be directly connected to the external ground terminal  60 . It is also possible to combine this embodiment with the first embodiment. 
     Third Embodiment 
     A solid-state image pickup device according to a third embodiment of the present invention is described with reference to  FIG. 8 .  FIG. 8  is a schematic plan view for illustrating a configuration of a ground connecting part  52   c  according to the third embodiment of the present invention. This embodiment is different from the first embodiment in that intermediate wiring  64  passes through a well region  102  that is different from any one of the pixel well region  101  and the peripheral well region  100 . Other points are the same as those of the first embodiment, and thus, description thereof is omitted. 
     The ground connecting part  52   c  illustrated in  FIG. 8  is configured such that the intermediate wiring  64  passes through the well region  102  that is different from any one of the pixel well region  101  and the peripheral well region  100  illustrated in  FIG. 1 . The well region  102  has no connection with the pixel well region  101  and the peripheral well regions  100  via a well. The well region  102  is connected to the peripheral ground wiring  50  and to the pixel ground wiring  51  via well contacts  44 , respectively. The well region  102  and the peripheral ground wiring  50 , and the well region  102  and the pixel ground wiring  51 , are not necessarily required to be connected to each other via a single well contact  44  as illustrated in  FIG. 8 . For example, the connection may be made via a plurality of well contacts  44 . 
     In the configuration described above, the peripheral well region  100  and the pixel well region  101  are connected to each other via the high resistance well region  102 . Consequently, Expression (6) is satisfied in this embodiment similarly to the case of the first embodiment, and thus, magnetic noise caused in the ground wiring can be reduced. The well region  102  may be a plurality of well regions insofar as the conditions described above are satisfied. It is also possible to combine this embodiment with the first and second embodiments. 
     Fourth Embodiment 
     A solid-state image pickup device according to a fourth embodiment of the present invention is described with reference to  FIG. 9 .  FIG. 9  is a schematic plan view for illustrating a configuration of a ground connecting part  52   d  according to the fourth embodiment of the present invention. This embodiment is different from the first embodiment in that the intermediate wiring  64  electrically connects different wiring layers via a well contact  45 . Other points are the same as those of the first embodiment, and thus, description thereof is omitted. 
     The intermediate wiring  64  illustrated in  FIG. 9  passes through the well contact  45  arranged between the peripheral ground wiring  50  and the pixel ground wiring  51  as illustrated in  FIG. 9 . The peripheral ground wiring  50  and the pixel ground wiring  51  are arranged in different layers. Consequently, the peripheral ground wiring  50  and the pixel ground wiring  51  are connected to each other via the high resistance well contact  45 . Also in this embodiment, with the configuration described above, Expression (6) above is satisfied similarly to the case of the first embodiment, and thus, magnetic noise caused in the ground wiring can be reduced. It is also possible to combine this embodiment with the first to third embodiments. 
     Fifth Embodiment 
     A solid-state image pickup device according to a fifth embodiment of the present invention is described with reference to  FIG. 10  and  FIG. 11  and  FIG. 12A  to  FIG. 12C .  FIG. 10  is a schematic illustration of a configuration of a solid-state image pickup element  1   b  according to the fifth embodiment of the present invention. In the first embodiment, a case is described in which the readout circuit includes the differential amplifier circuit  30  configured to amplify the signal from the pixel  10  with reference to a reference signal. On the other hand, in this embodiment, a case is described in which the readout circuit includes an analog-to-digital converter (AD converter)  31  configured to perform analog-to-digital conversion (A/D conversion) of the signal from the pixel  10  with reference to the reference signal. 
     In the solid-state image pickup element  1   b  according to this embodiment illustrated in  FIG. 10 , the differential amplifier circuits  30  according to the first embodiment illustrated in  FIG. 1  are replaced by the AD converters  31 . The AD converters  31  are arranged in the peripheral well region  100 , and read a signal from pixels  10  in the same column with reference to the reference signal. More specifically, through comparing the signal from the pixel  10  with a RAMP signal that is output from a ramp signal generating circuit  201 , the AD converter  31  performs A/D conversion of an analog signal from the pixel  10  into a digital signal. The AD converter  31  illustrated in  FIG. 10  is only conceptually illustrated and a peripheral circuit is omitted. 
     The ramp signal generating circuit  201  is arranged in a third well region  103  in which ground wiring  56  is arranged. The ground wiring  56  in the third well region  103  is connected to the pixel ground wiring  51  with low resistance. In other words, the third well region  103  can be regarded as sharing the pixel ground wiring  51  with the pixel well region  101 . A ground terminal of the ramp signal generating circuit  201  is connected, via well contacts  46 , to the ground wiring  56  that is connected to the pixel ground wiring  51 . Therefore, the RAMP signal that is output from the ramp signal generating circuit  201  is generated with the pixel ground wiring  51  being at the reference voltage. The AD converter  31  and the ramp signal generating circuit  201  are controlled by the peripheral circuit control unit  71 . 
     Here, comparison is made between the solid-state image pickup element  1  according to the first embodiment illustrated in  FIG. 1  and the solid-state image pickup element  1   b  according to this embodiment illustrated in  FIG. 10 . Then, it can be understood that, through regarding the well contact  46  illustrated in  FIG. 10  as the first contact  48 , the method in the first embodiment can be applied as it is. Therefore, in the description below of this embodiment, the well contact  46  is denoted as the first contact  46 , and a point of contact between the first contact  46  and the pixel ground wiring  51  is referred to as the point A. The first contact  46  may be a plurality of first contacts  46 . In this case, any one of the plurality of first contacts  46  is representatively referred to as the point A. 
       FIG. 11  is a schematic illustration of an equivalent circuit of the ground loop and a ground voltage distribution in the solid-state image pickup element  1   b  according to the fifth embodiment of the present invention. The equivalent circuit of the ground loop according to this embodiment illustrated in  FIG. 11  is the same as the equivalent circuit of the ground loop according to the first embodiment illustrated in  FIG. 6  except that the differential amplifier circuit  30  is replaced by the AD converter  31  and the hold capacitor  200  is replaced by the ramp signal generating circuit  201 . Therefore, the induced voltage differences V 1  to V 3  between the respective points on the ground loop are expressed by Expressions (1) to (3) above similarly to the case of the first embodiment. 
     As described above, also in this embodiment, a first feature is that the ground terminal of the ramp signal generating circuit  201  is connected to the pixel ground wiring  51  via the first contact  46 . Further, a second feature is that the electrical resistance value R 2  of the ground connecting part  52  that connects the pixel ground wiring  51  to the peripheral ground wiring  50  is set to be large so as to satisfy Expression (6) above. This can reduce magnetic noise caused in the ground wiring. 
       FIG. 12A  to  FIG. 12C  are graphs for showing magnetic noise included in input to the AD converter  31  according to the fifth embodiment of the present invention. The AD converter  31  according to this embodiment compares the signal from the pixel  10  with the reference signal and performs A/D conversion. In this case, the signal from the pixel  10  includes, as magnetic noise, the induced voltage difference V 1 +V 2  at the point S connected to the ground terminal of the pixel  10 . On the other hand, the reference signal includes, as magnetic noise, the induced voltage difference V 2  at the point A connected to the ground terminal of the ramp signal generating circuit  201 . Therefore, output of the AD converter  31  includes, as the magnetic noise output Vout, the induced voltage difference V 1  between the points A and S expressed by Expression (4) above as the difference of the induced voltage differences. In the description below, it is assumed that the magnetic flux B sinusoidally changes over time. 
       FIG. 12A  is a graph for showing waveforms that change over time of an ideal signal from the pixel  10  and an ideal RAMP signal when magnetic noise is not included in both of the signal from the pixel  10  and the reference signal. The AD converter  31  performs digital conversion of the signal from the pixel  10  at a time t 1  at which the signal from the pixel  10  and the RAMP signal are the same, and outputs the converted signal as a pixel signal. 
       FIG. 12B  is a graph for showing waveforms that change over time of a signal from the pixel  10  and a RAMP signal when magnetic noise is included only in the signal from the pixel  10 . This corresponds to the case in which the first feature of the present invention described above is not satisfied. Specifically, this is a case in which the ground terminal of the ramp signal generating circuit  201  illustrated in  FIG. 11  is connected not to the pixel ground wiring  51  (point A) but to the peripheral ground wiring  50  (point Q). In this case, the induced voltage difference V 1 +V 2  is caused at the point S connected to the ground terminal of the pixel  10 . On the other hand, almost no induced voltage is caused at the point Q connected to the ground terminal of the ramp signal generating circuit  201 . The AD converter  31  converts, into a digital signal, the signal from the pixel  10  at a time t 2  at which the signal from the pixel  10  and the RAMP signal are the same, and outputs the converted signal as a pixel signal. As a result, the signal has an error corresponding to a time t 1 -t 2  from the proper output signal. 
       FIG. 12C  is a graph for showing waveforms that change over time of a signal from the pixel  10  and a RAMP signal when magnetic noise is included in both of the signal from the pixel  10  and the reference signal. This corresponds to the case in which the first feature of the present invention described above is not satisfied. Specifically, this is a case in which the ground terminal of the ramp signal generating circuit  201  illustrated in  FIG. 11  is connected to the pixel ground wiring  51  (point A). In  FIG. 12C , the induced voltage difference V 1 +V 2  is caused at the point S connected to the ground terminal of the pixel  10 . On the other hand, the induced voltage difference V 2  is caused at the point A connected to the ground terminal of the ramp signal generating circuit  201 . The AD converter  31  converts, into a digital signal, the signal from the pixel  10  at a time t 3  at which the signal from the pixel  10  and the RAMP signal are the same, and outputs the converted signal as a pixel signal. As a result, the signal has an error corresponding to a time t 1 -t 3  from the proper output signal, but t 1 -t 3 &lt;t 1 -t 2 , and thus, magnetic noise caused in the ground wiring can be reduced. 
     The induced voltage difference V 1  caused at the electrical resistance value R 11 +R 1  is a factor of causing such an error of t 1 -t 3 . When the induced voltage difference V 1  is small enough to ignore, in other words, when the second feature of the present invention described above is further satisfied, the signal from the pixel  10  and the RAMP signal contain substantially the same sinusoidal waves. Under this condition, the errors corresponding to the time t 1 -t 3  of the signal from the pixel  10  and the RAMP signal respectively oscillate substantially in the same way with respect to the ideal signals shown in  FIG. 12A , and thus, the output signal of the AD converter  31  is a signal substantially corresponding to the time t 1 . 
     As described above, according to this embodiment, the readout circuit (AD converter) is included that is arranged in the peripheral well region in which the peripheral ground wiring is arranged and that is configured to read a signal from pixels in the same column with reference to the reference signal. Further, the reference signal circuit (ramp signal generating circuit) is included that has the ground terminal electrically connected to the pixel ground wiring via the first contact and that is configured to output the reference signal to the readout circuit. Further, the minimum value R 2  of the electrical resistance values from the pixel ground wiring to the peripheral ground wiring is set to be large so as to satisfy Expression (6) above. Consequently, it is possible to obtain a solid-state image pickup element, a method of manufacturing a solid-state image pickup element, and an image pickup system that can reduce magnetic noise caused in the ground wiring without additionally providing a circuit for reducing the noise. It is also possible to combine this embodiment with the second to fourth embodiments described above. 
     The ramp signal generating circuit  201  according to this embodiment is formed in the third well region  103 . The third well region  103  may be formed in the pixel well region  101  or the peripheral well region  100 . However, in this case, it is necessary that the third well region  103  in which the ramp signal generating circuit  201  is formed and the peripheral well region  100  be not connected to each other via a common well, that is, the two regions are required to be formed as well regions independent of each other. In this case, the third well region  103  serving as an external ground of the ramp signal generating circuit  201  is connected via low resistance wiring extended from the pixel ground wiring  51 . 
     Sixth Embodiment 
     A solid-state image pickup device according to a sixth embodiment of the present invention is described with reference to  FIG. 13  to  FIG. 15 .  FIG. 13  is a schematic illustration of a configuration of a solid-state image pickup element  1   c  according to the sixth embodiment of the present invention. In this embodiment, a case is described in which the pixel well region  101  and the peripheral well region  100  are arranged on different semiconductor substrates. 
     The solid-state image pickup element  1   c  according to this embodiment illustrated in  FIG. 13  is an example of a stacked type solid-state image pickup element including a semiconductor substrate  1000  and a semiconductor substrate  2000 . The semiconductor substrate  1000  and the semiconductor substrate  2000  are connected to each other via at least a connecting electrode  501 . In this embodiment, connecting electrode  500  and  502  are also used for connecting the semiconductor substrate  1000  and the semiconductor substrate  2000  to each other. Components relating to the pixels  10 , such as the pixel well region  101 , the vertical scanning circuit  70 , and the pixel ground wiring  51 , are included in the semiconductor substrate  1000 . On the other hand, components relating to the peripheral circuit, such as the peripheral well region  100 , the peripheral circuit control unit  71 , the differential amplifier circuit  30 , the peripheral ground wiring  50 , and the hold capacitor  200 , are included in the semiconductor substrate  2000 . 
     The connecting electrode  500  connects the pixel ground wiring  51  to the peripheral ground wiring  50 . The connecting electrode  501  connects the hold capacitor  200  to the pixel ground wiring  51 . The connecting electrode  502  connects the vertical signal line  20  to the inverting input terminal (−) of the differential amplifier circuit  30 . The connecting electrode  500  corresponds to the ground connecting part  52  in the first embodiment in terms of an equivalent circuit, and the connecting electrode  501  corresponds to the first contact  48  in the first embodiment in terms of an equivalent circuit. The pixel ground wiring  51  and the peripheral ground wiring  50  are connected to each other via a plurality of connecting electrodes  500  in order to reduce the wiring impedance of the power supply. In this embodiment, the wirings are connected to each other at two places. The peripheral ground wiring  50  is electrically connected to an external ground voltage outside the solid-state image pickup element  1   c  via the external ground terminal  60 . Other points are the same as those of the first embodiment, and thus, description thereof is omitted. 
       FIG. 14  is a schematic sectional view for illustrating a configuration of the solid-state image pickup element  1   c  according to the sixth embodiment of the present invention. The semiconductor substrate  1000  and the semiconductor substrate  2000  are connected to each other via the connecting electrodes  500 ,  501 , and  502  with an insulator  600  sandwiched between the substrates. In  FIG. 14 , the connecting electrodes  500 ,  501 , and  502  are collectively illustrated, but actually, the connecting electrodes  500  are arranged at two places, and the connecting electrodes  501  and  502  are arranged so as to correspond to the arranged pixels. The insulator  600  may be formed of an anti-magnetic material (material having a high permeability) except for portions thereof near the connecting electrodes  500 ,  501 , and  502 . 
       FIG. 15  is a schematic illustration of an equivalent circuit of the ground loop and a ground voltage distribution in the solid-state image pickup element  1   c  according to the sixth embodiment of the present invention. This is a case in which, different from the case illustrated in  FIG. 6 , a ground loop is formed by the semiconductor substrate  1000  and the semiconductor substrate  2000  via points U and T. Similarly to the case of the first embodiment, the induced voltage differences V 1  to V 3  are expressed by Expressions (8) to (10) below.
 
 V 1= V ×( R 11+ R 1)/( R 11+2× R 1+2× R 2)  (8)
 
 V 2= V×R 2/( R 11+2× R 1+2× R 2)  (9)
 
 V 3= V ×( R 2+ R 1)/( R 11+2× R 1+2× R 2)  (10)
 
     Also in this embodiment, the electrical resistance values R 1 , R 11 , and R 2  are set so as to satisfy Expression (5) and Expression (6) above. The resistance value R 1  of an electrical path from one of the plurality of pixel well contacts  42  to the ground electrode  53  and the resistance value R 2  of an electrical path from the peripheral well contact  43  closest to the ground electrode  53  (point C) to the ground electrode  53  satisfy the relationship of R 1 &lt;R 2 . Such a configuration can obtain an effect similar to that of the first embodiment. In other words, the ground electrode  53  of the hold capacitor  200  is connected to the pixel ground wiring  51 , and thus, magnetic noise caused in the ground wiring can be reduced. 
     As described above, in this embodiment, through forming the stacked type solid-state image pickup device using the connecting electrodes, the area relating to the peripheral circuit can be reduced, and thus, the chip size of the solid-state image pickup device can be reduced compared with that of the first embodiment. 
     Further, the electrical resistance values can be adjusted through adjusting the arrangement positions of the connecting electrodes  500  to  502  of the semiconductor substrates  1000  and  2000 , and the electrical resistance values R 1  and R 2  can be adjusted through appropriately selecting the materials of the connecting electrodes, and thus, the electrical resistance values can be designed with ease. Therefore, the design flexibility in reducing the proportionality constant k in Expression (1′) above is improved, and thus, an effect similar to that of the first embodiment can be obtained more effectively. The configuration of this embodiment can also be applied to the fifth embodiment. 
     Seventh Embodiment 
     In the following, an image pickup system according to a seventh embodiment of the present invention is described with reference to  FIG. 16 .  FIG. 16  is an illustration of a configuration of the image pickup system according to the seventh embodiment of the present invention. In this embodiment, a case of an image pickup system to which the configuration according to the first to sixth embodiments is applied is described. 
     An image pickup system  800  illustrated in  FIG. 16  includes, for example, an optical unit  810 , an image pickup apparatus  820 , a recording/communication unit  840 , a timing control unit  850 , a system control unit  860 , and a reproduction/display unit  870 . The image pickup apparatus  820  includes the solid-state image pickup element  1  (or  1   b  or  1   c , the same applies below) and an image signal processing unit  830 . The photoelectric conversion device described in the first to sixth embodiments is used as the solid-state image pickup element  1 . 
     The optical unit  810  serving as an optical system such as a lens collects light from an object onto a pixel array in which a plurality of pixels of the solid-state image pickup element  1  are two-dimensionally arranged, to thereby form an image of the object. The solid-state image pickup element  1  outputs a signal depending on the light collected onto the pixel array at a timing based on a signal from the timing control unit  850 . The signal that is output from the solid-state image pickup element  1  is input to the image signal processing unit  830 , and the image signal processing unit  830  performs signal processing in accordance with a method defined by a program or the like. A signal obtained through the processing by the image signal processing unit  830  is sent to the recording/communication unit  840  as image data. The recording/communication unit  840  sends a signal for forming an image to the reproduction/display unit  870  to cause the reproduction/display unit  870  to reproduce/display moving images or a still image. The recording/communication unit  840  also communicates, after receiving a signal from the image signal processing unit  830 , to/from the system control unit  860 , and records a signal for forming an image on a recording medium (not shown). 
     The system control unit  860  has centralized control over operation of the image pickup system  800 , and controls drive of the optical unit  810 , the timing control unit  850 , the recording/communication unit  840 , and the reproduction/display unit  870 . The optical unit  810  is driven by a motor (not shown), for example, and performs image stabilization and adjusts a focal position. In the first to sixth embodiments, a magnetic noise source that influences the ground wiring is, for example, a magnetic field generated by the motor. 
     Further, the system control unit  860  includes a storage device (not shown) that is, for example, a recording medium, and a program necessary for controlling operation of the image pickup system  800  and the like are stored in the storage device. Further, the system control unit  860  supplies, into the image pickup system  800 , for example, a signal for switching drive modes in response to operation by a user. Specific examples include change of a row to be read or a row to be reset, change in angle of view accompanying electronic zoom, and shift of the angle of view accompanying electronic vibration isolation. The timing control unit  850  controls drive timing of the solid-state image pickup element  1  and the image signal processing unit  830  based on control by the system control unit  860 . 
     While the present invention has been described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. The scope of the following claims is to be accorded the broadest interpretation so as to encompass all such modifications and equivalent structures and functions. 
     This application claims the benefit of Japanese Patent Application No. 2015-178247, filed Sep. 10, 2015, and Japanese Patent Application No. 2016-053833, filed Mar. 17, 2016, which are hereby incorporated by reference herein in their entirety.