Patent Publication Number: US-2023135172-A1

Title: Interconnect Structures and Methods of Forming the Same

Description:
PRIORITY CLAIM AND CROSS-REFERENCE 
     This application claims the benefit of U.S. Provisional Application No. 63/275,523, filed on Nov. 4, 2021, which application is hereby incorporated herein by reference. 
    
    
     BACKGROUND 
     Semiconductor devices are used in a variety of electronic applications, such as, for example, personal computers, cell phones, digital cameras, and other electronic equipment. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers of material over a semiconductor substrate, and patterning the various material layers using lithography to form circuit components and elements thereon. 
     The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continual reductions in minimum feature size, which allow more components to be integrated into a given area. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. 
         FIG.  1    illustrates an example of a nanostructure field-effect transistor (nano-FET) in a three-dimensional view, in accordance with some embodiments. 
         FIGS.  2 ,  3 ,  4 ,  5 ,  6 A,  6 B,  7 A,  7 B,  8 A,  8 B,  9 A,  9 B,  10 A,  10 B,  11 A,  11 B,  11 C,  12 A,  12 B,  12 C,  12 D ,  13 A,  13 B,  13 C,  14 A,  14 B,  15 A,  15 B,  16 A,  16 B,  17 A,  17 B,  18 A,  18 B,  19 A,  19 B,  19 C,  20 A,  20 B,  20 C,  21 A,  21 B,  21 C,  22 A,  22 B, and  22 C are cross-sectional views of intermediate stages in the manufacturing of nano-FETs, in accordance with some embodiments. 
         FIGS.  23 A,  23 B,  24 A,  24 B,  25 A,  25 B,  26 A,  26 B,  27 A,  27 B,  28 ,  29 ,  30 ,  31 ,  32 ,  33 ,  34 ,  35 , and  36    are cross-sectional views of intermediate stages in the manufacturing of interconnect structures for integrated circuits, in accordance with some embodiments. 
     
    
    
     DETAILED DESCRIPTION 
     The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. 
     Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature&#39;s relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. 
     Various embodiments provide methods for forming self-aligned structures in an improved interconnect structure, and semiconductor devices formed by the same. The improved interconnect structure may include a self-aligned etch-resistant layer and a self-aligned capping material. The method includes forming a plurality of first conductive features in a first dielectric layer. An inhibitor material may optionally be selectively deposited over the first conductive features, without being deposited on the first dielectric layer. An etch-resistant layer is selectively deposited over the first dielectric layer, without being deposited on the first conductive features or the inhibitor material, and the inhibitor material is then removed. A capping material is selectively deposited over the first conductive features, without being deposited on the first dielectric layer or the etch-resistant layer. An etch stop layer is deposited over the etch-resistant layer and the capping material. A second dielectric layer is formed over the etch stop layer and second conductive features are formed extending through the second dielectric layer and the etch stop layer. The second conductive features may be electrically coupled to the first conductive features. The second conductive features may include conductive vias and conductive lines, which extend through the second dielectric layer and the etch stop layer to contact the capping material. 
     Forming the inhibitor material over the first conductive features prevents the etch-resistant layer from being deposited over the first conductive features. This increases the contact area between the second conductive features and the first conductive features/the capping layer, which reduces contact resistance and improves device performance. The etch-resistant layer serves as an etch stop layer and prevents the underlying first dielectric layer from being damaged by the etch processes used to form openings in which the second conductive features are formed. This reduces leakage and prevents reliability issues, such as time-dependent dielectric breakdown (TDDB), electromigration (EM), and stress migration (SM). Protecting the first dielectric layer with the etch-resistant layer further allows the second dielectric layer and the etch stop layer to be sufficiently etched to expose the first conductive features without damaging the first dielectric layer, which allows for better contact to be made between the second conductive features and the first conductive features, reducing RC delay and improving device performance. Including the capping material over the first conductive features further improves the contact area between the second conductive features and the first conductive features, reduces RC delay, and improves device performance. 
     Embodiments are described below in a particular context, a die comprising nano-FETs. Various embodiments may be applied, however, to dies comprising other types of transistors (e.g., fin field effect transistors (FinFETs), planar transistors, or the like), or other types of integrated circuit devices (e.g., resistors, capacitors, diodes, or the like), in lieu of or in combination with the nano-FETs. 
       FIG.  1    illustrates an example of nanostructure FETs (e.g., nanowire FETs, nanosheet FETs (Nano-FETs), or the like) in a three-dimensional view. The nano-FETs comprise nanostructures  55  (e.g., nanosheets, nanowires, or the like) over fins  66  on a substrate  50  (e.g., a semiconductor substrate). The nanostructures  55  act as channel regions for the nanostructure FETs. The nanostructures  55  may include p-type nanostructures, n-type nanostructures, or a combination thereof. Isolation regions  68  are disposed between adjacent fins  66 . The fins  66  may protrude above and from between neighboring isolation regions  68 . Although the isolation regions  68  are described/illustrated as being separate from the substrate  50 , as used herein, the term “substrate” may refer to the semiconductor substrate alone or a combination of the semiconductor substrate and the isolation regions. Additionally, although a bottom portion of the fins  66  is illustrated as being a single, continuous material with the substrate  50 , the bottom portion of the fins  66  and/or the substrate  50  may comprise a single material or a plurality of materials. In this context, the fins  66  refer to the portion extending between the neighboring isolation regions  68 . 
     Gate dielectric layers  100  are over top surfaces and sidewalls of the fins  66  and along top surfaces, sidewalls, and bottom surfaces of the nanostructures  55 . Gate electrodes  102  are over the gate dielectric layers  100 . Epitaxial source/drain regions  92  are disposed on the fins  66  on opposing sides of the gate dielectric layers  100  and the gate electrodes  102 . 
       FIG.  1    further illustrates reference cross-sections that are used in later figures. Cross-section A-A′ is along a longitudinal axis of a gate electrode  102  and in a direction, for example, perpendicular to the direction of current flow between the epitaxial source/drain regions  92  of a nano-FET. Cross-section B-B′ is perpendicular to cross-section A-A′ and is parallel to a longitudinal axis of a fin  66  of the nano-FET and in a direction of, for example, the current flow between the epitaxial source/drain regions  92  of the nano-FET. Cross-section C-C′ is parallel to cross-section A-A′ and extends through the epitaxial source/drain regions  92  of the nano-FET. Subsequent figures refer to these reference cross-sections for clarity. 
     Some embodiments discussed herein are discussed in the context of nano-FETs formed using a gate-last process. In other embodiments, a gate-first process may be used. Some embodiments contemplate aspects used in planar devices, such as planar FETs or in fin field-effect transistors (FinFETs), or other integrated circuit devices, such as resistors, capacitors, diodes, or the like. 
       FIGS.  2  through  36    are cross-sectional views of intermediate stages in the manufacturing of nano-FETs, in accordance with some embodiments.  FIGS.  2 ,  3 ,  4 ,  5 ,  6 A ,  13 A,  14 A,  15 A,  16 A,  17 A,  18 A,  19 A,  20 A,  21 A,  22 A,  23 A,  24 A,  25 A,  26 A,  27 A,  28 ,  29 ,  30 ,  31 ,  32 ,  33 ,  34 ,  35 , and  36  illustrate reference cross-section A-A′ illustrated in  FIG.  1   .  FIGS.  6 B,  7 B,  8 B,  9 B,  10 B,  11 B,  11 C,  12 B,  12 D,  13 B,  14 B,  15 B,  16 B,  17 B,  18 B,  19 B,  20 B,  21 B,  22 B,  23 B,  24 B ,  25 B,  26 B, and  27 B illustrate reference cross-section B-B′ illustrated in  FIG.  1   .  FIGS.  7 A,  8 A,  9 A,  10 A,  11 A,  12 A,  12 C,  13 C,  19 C,  20 C,  21 C, and  22 C  illustrate reference cross-section C-C′ illustrated in  FIG.  1   . 
     In  FIG.  2   , a substrate  50  is provided. The substrate  50  may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p-type or an n-type dopant) or undoped. The substrate  50  may be a wafer, such as a silicon wafer. Generally, an SOI substrate is a layer of a semiconductor material formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is provided on a substrate, typically a silicon or glass substrate. Other substrates, such as a multi-layered or gradient substrate may also be used. In some embodiments, the semiconductor material of the substrate  50  may include silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including silicon-germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and/or gallium indium arsenide phosphide; or combinations thereof. 
     The substrate  50  has an n-type region  50 N and a p-type region  50 P. The n-type region  50 N can be for forming n-type devices, such as NMOS transistors, e.g., n-type nano-FETs. The p-type region  50 P can be for forming p-type devices, such as PMOS transistors, e.g., p-type nano-FETs. The n-type region  50 N may be physically separated from the p-type region  50 P (as illustrated by divider  20 ), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) may be disposed between the n-type region  50 N and the p-type region  50 P. Although one n-type region  50 N and one p-type region  50 P are illustrated, any number of n-type regions  50 N and p-type regions  50 P may be provided. 
     Further in  FIG.  2   , a multi-layer stack  64  is formed over the substrate  50 . The multi-layer stack  64  includes alternating layers of first semiconductor layers  51 A-C (collectively referred to as first semiconductor layers  51 ) and second semiconductor layers  53 A-C (collectively referred to as second semiconductor layers  53 ). For purposes of illustration and as discussed in greater detail below, the second semiconductor layers  53  will be removed and the first semiconductor layers  51  will be patterned to form channel regions of nano-FETs in the p-type region  50 P. The first semiconductor layers  51  will be removed and the second semiconductor layers  53  will be patterned to form channel regions of nano-FETs in the n-type region  50 N. Nevertheless, in some embodiments the first semiconductor layers  51  may be removed and the second semiconductor layers  53  may be patterned to form channel regions of nano-FETs in the n-type region  50 N, and the second semiconductor layers  53  may be removed and the first semiconductor layers  51  may be patterned to form channel regions of nano-FETs in the p-type region  50 P. 
     In some embodiments, the first semiconductor layers  51  may be removed and the second semiconductor layers  53  may be patterned to form channel regions of nano-FETS in both the n-type region  50 N and the p-type region  50 P. In some embodiments, the second semiconductor layers  53  may be removed and the first semiconductor layers  51  may be patterned to form channel regions of nano-FETs in both the n-type region  50 N and the p-type region  50 P. In such embodiments, the channel regions in both the n-type region  50 N and the p-type region  50 P may have a same material composition (e.g., silicon, or another semiconductor material) and be formed simultaneously.  FIGS.  22 A,  22 B, and  22 C  illustrate a structure resulting from such embodiments where the channel regions in both the p-type region  50 P and the n-type region  50 N comprise silicon, for example. 
     The multi-layer stack  64  is illustrated as including three layers of each of the first semiconductor layers  51  and the second semiconductor layers  53  for illustrative purposes. In some embodiments, the multi-layer stack  64  may include any number of the first semiconductor layers  51  and the second semiconductor layers  53 . Each of the layers of the multi-layer stack  64  may be epitaxially grown using a process such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), or the like. The first semiconductor layers  51  may be formed of a first semiconductor material suitable for p-type nanostructure FETs, such as silicon germanium or the like. The second semiconductor layers  53  may be formed of a second semiconductor material suitable for n-type nanostructure FETs, such as silicon, silicon carbon, or the like. The multi-layer stack  64  is illustrated as having a bottommost semiconductor layer suitable for p-type nanostructure FETs (e.g., the first semiconductor layers  51 ) for illustrative purposes. In some embodiments, the multi-layer stack  64  may be formed such that the bottommost layer is a semiconductor layer suitable for n-type nanostructure FETs (e.g., the second semiconductor layers  53 ). 
     The first semiconductor materials and the second semiconductor materials may be materials having a high etch selectivity to one another. As such, the first semiconductor layers  51  formed of the first semiconductor materials may be removed without significantly removing the second semiconductor layers  53  formed of the second semiconductor materials in the n-type region  50 N. This allows the second semiconductor layers  53  to be patterned to form channel regions of n-type nanostructure FETs. Similarly, the second semiconductor layers  53  formed of the second semiconductor materials may be removed without significantly removing the first semiconductor layers  51  formed of the first semiconductor materials in the p-type region  50 P. This allows the first semiconductor layers  51  to be patterned to form channel regions of p-type nanostructure FETs. 
     In  FIG.  3   , fins  66  are formed in the substrate  50  and nanostructures  55  are formed in the multi-layer stack  64 . In some embodiments, the nanostructures  55  and the fins  66  may be formed in the multi-layer stack  64  and the substrate  50 , respectively, by etching trenches in the multi-layer stack  64  and the substrate  50 . The etching may be any acceptable etch process, such as a reactive ion etch (RIE), neutral beam etch (NBE), the like, or a combination thereof. The etching may be anisotropic. Forming the nanostructures  55  by etching the multi-layer stack  64  may further define first nanostructures  52 A-C (collectively referred to as first nanostructures  52 ) from the first semiconductor layers  51  and define second nanostructures  54 A-C (collectively referred to as second nanostructures  54 ) from the second semiconductor layers  53 . The first nanostructures  52  and the second nanostructures  54  may be collectively referred to as nanostructures  55 . 
     The fins  66  and the nanostructures  55  may be patterned by any suitable method. For example, the fins  66  and the nanostructures  55  may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, a sacrificial layer may be formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers are used to pattern the fins  66 . 
       FIG.  3    illustrates the fins  66  in the n-type region  50 N and the p-type region  50 P as having substantially equal widths for illustrative purposes. In some embodiments, widths of the fins  66  in the n-type region  50 N may be greater than or less than widths of the fins  66  in the p-type region  50 P. Further, while each of the fins  66  and the nanostructures  55  are illustrated as having a consistent width throughout, in some embodiments, the fins  66  and/or the nanostructures  55  may have tapered sidewalls such that a width of each of the fins  66  and/or the nanostructures  55  continuously increases in a direction towards the substrate  50 . In such embodiments, each of the nanostructures  55  may have a different width and may be trapezoidal in shape. 
     In  FIG.  4   , shallow trench isolation (STI) regions  68  are formed adjacent the fins  66 . The STI regions  68  may be formed by depositing an insulation material over the substrate  50 , the fins  66 , and the nanostructures  55 , and between adjacent fins  66 . The insulation material may be an oxide (such as silicon oxide), a nitride, the like, or a combination thereof. The insulation material may be formed by high-density plasma CVD (HDP-CVD), flowable CVD (FCVD), the like, or a combination thereof. Other insulation materials formed by any acceptable process may be used. In the illustrated embodiment, the insulation material is silicon oxide formed by an FCVD process. An anneal process may be performed once the insulation material is formed. In an embodiment, the insulation material is formed such that excess insulation material covers the nanostructures  55 . Although the insulation material is illustrated as a single layer, some embodiments may utilize multiple layers. For example, in some embodiments, a liner (not separately illustrated) may be formed along surfaces of the substrate  50 , the fins  66 , and the nanostructures  55 . Thereafter, a fill material, such as those discussed above, may be formed over the liner. 
     A removal process is then applied to the insulation material to remove excess insulation material over the nanostructures  55 . In some embodiments, a planarization process, such as a chemical mechanical polish (CMP), an etch-back process, combinations thereof, or the like may be utilized. The planarization process exposes the nanostructures  55  such that top surfaces of the nanostructures  55  and the insulation material are level after the planarization process is complete. 
     The insulation material is then recessed to form the STI regions  68 . The insulation material is recessed such that the nanostructures  55  and upper portions of the fins  66  in the n-type region  50 N and the p-type region  50 P protrude from between neighboring STI regions  68 . Further, the top surfaces of the STI regions  68  may have a flat surface as illustrated, a convex surface, a concave surface (such as dishing), or a combination thereof. The top surfaces of the STI regions  68  may be formed flat, convex, and/or concave by an appropriate etch. The STI regions  68  may be recessed using an acceptable etch process, such as one that is selective to the material of the insulation material (e.g., etches the material of the insulation material at a faster rate than the material of the fins  66  and the nanostructures  55 ). An oxide removal using dilute hydrofluoric (dHF) acid may be used. 
     The process described above with respect to  FIGS.  2  through  4    is just one example of how the fins  66  and the nanostructures  55  may be formed. In some embodiments, the fins  66  and/or the nanostructures  55  may be formed using a mask and an epitaxial growth process. For example, a dielectric layer can be formed over a top surface of the substrate  50 , and trenches can be etched through the dielectric layer to expose the underlying substrate  50 . Epitaxial structures can be epitaxially grown in the trenches, and the dielectric layer can be recessed such that the epitaxial structures protrude from the dielectric layer to form the fins  66  and/or the nanostructures  55 . The epitaxial structures may comprise the alternating semiconductor materials discussed above, such as the first semiconductor materials and the second semiconductor materials. In some embodiments where epitaxial structures are epitaxially grown, the epitaxially grown materials may be in situ doped during growth. This may obviate prior and/or subsequent implantations, although in situ and implantation doping may be used together. 
     Additionally, the first semiconductor layers  51  (and resulting first nanostructures  52 ) and the second semiconductor layers  53  (and resulting second nanostructures  54 ) are illustrated and discussed herein as comprising the same materials in the p-type region  50 P and the n-type region  50 N for illustrative purposes only. As such, in some embodiments one or both of the first semiconductor layers  51  and the second semiconductor layers  53  may be different materials or formed in a different order in the p-type region  50 P and the n-type region  50 N. 
     Further in  FIG.  4   , appropriate wells (not separately illustrated) may be formed in the fins  66 , the nanostructures  55 , and/or the STI regions  68 . In embodiments with different well types, different implant steps for the n-type region  50 N and the p-type region  50 P may be achieved using a photoresist or other masks (not separately illustrated). For example, a photoresist may be formed over the fins  66 , the nanostructures, and the STI regions  68  in the n-type region  50 N and the p-type region  50 P. The photoresist is patterned to expose the p-type region  50 P. The photoresist can be formed by using a spin-on technique and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, an n-type impurity implant is performed in the p-type region  50 P, and the photoresist may act as a mask to prevent n-type impurities from being implanted into the n-type region  50 N. The n-type impurities may be phosphorus, arsenic, antimony, or the like implanted in the region to a concentration in a range from about 10 13  atoms/cm 3  to about 10 14  atoms/cm 3 . After the implant, the photoresist is removed, such as by an acceptable ashing process. 
     Following or prior to the implanting of the p-type region  50 P, a photoresist or other masks (not separately illustrated) is formed over the fins  66 , the nanostructures  55 , and the STI regions  68  in the p-type region  50 P and the n-type region  50 N. The photoresist is patterned to expose the n-type region  50 N. The photoresist can be formed by using a spin-on technique and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, a p-type impurity implant may be performed in the n-type region  50 N, and the photoresist may act as a mask to prevent p-type impurities from being implanted into the p-type region  50 P. The p-type impurities may be boron, boron fluoride, indium, or the like implanted in the region to a concentration in a range from about 10 13  atoms/cm 3  to about 10 14  atoms/cm 3 . After the implant, the photoresist may be removed, such as by an acceptable ashing process. 
     After the implants of the n-type region  50 N and the p-type region  50 P, an anneal may be performed to repair implant damage and to activate the p-type and/or n-type impurities that were implanted. In some embodiments, the grown materials of epitaxial fins may be in situ doped during growth, which may obviate the implantations, although in situ and implantation doping may be used together. 
     In  FIG.  5   , a dummy dielectric layer  70  is formed on the fins  66  and/or the nanostructures  55 . The dummy dielectric layer  70  may be, for example, silicon oxide, silicon nitride, a combination thereof, or the like, and may be deposited or thermally grown according to acceptable techniques. 
     A dummy gate layer  72  is formed over the dummy dielectric layer  70 , and a mask layer  74  is formed over the dummy gate layer  72 . The dummy gate layer  72  may be deposited over the dummy dielectric layer  70  and then planarized, such as by a CMP. The dummy gate layer  72  may be a conductive or non-conductive material and may be selected from a group including amorphous silicon, polycrystalline-silicon (polysilicon), poly-crystalline silicon-germanium (poly-SiGe), metallic nitrides, metallic silicides, metallic oxides, and metals. The dummy gate layer  72  may be deposited by physical vapor deposition (PVD), CVD, sputter deposition, or other techniques for depositing the selected material. The dummy gate layer  72  may be made of other materials that have a high etch selectivity from the etching of isolation regions. 
     The mask layer  74  may be deposited over the dummy gate layer  72 . The mask layer  74  may include, for example, silicon nitride, silicon oxynitride, or the like. In this example, a single dummy gate layer  72  and a single mask layer  74  are formed across the n-type region  50 N and the p-type region  50 P. It is noted that the dummy dielectric layer  70  is shown covering only the fins  66  and the nanostructures  55  for illustrative purposes only. In some embodiments, the dummy dielectric layer  70  may be deposited such that the dummy dielectric layer  70  covers the STI regions  68 . As such, the dummy dielectric layer  70  may extend between the dummy gate layer  72  and the STI regions  68 . 
       FIGS.  6 A through  22 C  illustrate various additional steps in the manufacturing of embodiment devices.  FIGS.  7 A,  8 A,  9 A,  10 A,  11 A,  12 A,  12 C,  13 A,  13 C,  14 A,  15 A,  19 C ,  20 C,  21 C and  22 C illustrate features in either the n-type regions  50 N or the p-type regions  50 P. In  FIGS.  6 A and  6 B , the mask layer  74  (see  FIG.  5   ) may be patterned using acceptable photolithography and etching techniques to form masks  78 . The pattern of the masks  78  then may be transferred to the dummy gate layer  72  and to the dummy dielectric layer  70  to form dummy gates  76  and dummy gate dielectrics  71 , respectively. The dummy gates  76  cover respective channel regions of the nanostructures  55 . The pattern of the masks  78  physically separates each of the dummy gates  76  from adjacent dummy gates  76 . The dummy gates  76  may also have a lengthwise direction substantially perpendicular to the lengthwise direction of respective fins  66 . The masks  78 , the dummy gates  76 , and the dummy gate dielectrics  71  may be collectively referred to as “dummy gate structures.” 
     In  FIGS.  7 A and  7 B , a first spacer layer  80  and a second spacer layer  82  are formed over dummy gate structures, the nanostructures  55 , and the STI regions  68 . The first spacer layer  80  and the second spacer layer  82  will be subsequently patterned to act as spacers for forming self-aligned source/drain regions. In  FIGS.  7 A and  7 B , the first spacer layer  80  is formed on top surfaces of the STI regions  68 ; top surfaces and sidewalls of the nanostructures  55  and the masks  78 ; and sidewalls of the dummy gates  76 , the dummy gate dielectrics  71 , and the fins  66 . The second spacer layer  82  is deposited over the first spacer layer  80 . The first spacer layer  80  may be formed of silicon oxide, silicon nitride, silicon oxynitride, or the like, using techniques such as thermal oxidation or deposited by CVD, ALD, or the like. The second spacer layer  82  may be formed of a material having a different etch rate than the material of the first spacer layer  80 , such as silicon oxide, silicon nitride, silicon oxynitride, or the like, and may be deposited by CVD, ALD, or the like. 
     After the first spacer layer  80  is formed and prior to forming the second spacer layer  82 , implants for lightly doped source/drain (LDD) regions (not separately illustrated) may be performed. In embodiments with different device types, similar to the implants discussed above in  FIG.  4   , a mask, such as a photoresist, may be formed over the n-type region  50 N, while exposing the p-type region  50 P. Appropriate type (e.g., p-type) impurities may be implanted into the exposed fins  66  and the nanostructures  55  in the p-type region  50 P. The mask may then be removed. Subsequently, a mask, such as a photoresist, may be formed over the p-type region  50 P while exposing the n-type region  50 N. Appropriate type impurities (e.g., n-type) may be implanted into the exposed fins  66  and the nanostructures  55  in the n-type region  50 N. The mask may then be removed. The n-type impurities may be the any of the n-type impurities previously discussed, and the p-type impurities may be the any of the p-type impurities previously discussed. The lightly doped source/drain regions may have a concentration of impurities in a range from about 1×10 15  atoms/cm 3  to about 1×10 19  atoms/cm 3 . An anneal may be used to repair implant damage and to activate the implanted impurities. 
     In  FIGS.  8 A and  8 B , the first spacer layer  80  and the second spacer layer  82  (see  FIGS.  7 A and  7 B ) are etched to form first spacers  81  and second spacers  83 . As will be discussed in greater detail below, the first spacers  81  and the second spacers  83  act to self-align subsequently formed source drain regions, as well as to protect sidewalls of the fins  66  and/or the nanostructures  55  during subsequent processing. The first spacer layer  80  and the second spacer layer  82  may be etched using a suitable etch process, such as an isotropic etch process (e.g., a wet etch process), an anisotropic etch process (e.g., a dry etch process), or the like. In some embodiments, the material of the second spacer layer  82  has a different etch rate than the material of the first spacer layer  80 , such that the first spacer layer  80  may act as an etch stop layer when patterning the second spacer layer  82  and the second spacer layer  82  may act as a mask when patterning the first spacer layer  80 . For example, the second spacer layer  82  may be etched using an anisotropic etch process wherein the first spacer layer  80  acts as an etch stop layer. Remaining portions of the second spacer layer  82  form second spacers  83 , as illustrated in  FIG.  8 A . The second spacers  83  then act as a mask while etching exposed portions of the first spacer layer  80 , thereby forming first spacers  81  as illustrated in  FIGS.  8 A and  8 B . 
     As illustrated in  FIG.  8 A , the first spacers  81  and the second spacers  83  are disposed on sidewalls of the fins  66  and/or the nanostructures  55 . As illustrated in  FIG.  8 B , in some embodiments, the second spacer layer  82  may be removed from over the first spacer layer  80  adjacent the masks  78 , the dummy gates  76 , and the dummy gate dielectrics  71 , and only the first spacers  81  are disposed on sidewalls of the masks  78 , the dummy gates  76 , and the dummy dielectric layers  60 . In some embodiments, a portion of the second spacer layer  82  may remain over the first spacer layer  80  adjacent the masks  78 , the dummy gates  76 , and the dummy gate dielectrics  71 . 
     It is noted that the above disclosure generally describes a process of forming spacers and LDD regions. Other processes and sequences may be used. For example, fewer or additional spacers may be utilized, different sequence of steps may be utilized (e.g., the first spacers  81  may be patterned prior to depositing the second spacer layer  82 ), additional spacers may be formed and removed, and/or the like. Furthermore, the n-type and p-type devices may be formed using different structures and steps. 
     In  FIGS.  9 A and  9 B , first recesses  86  are formed in the nanostructures  55 , the fins  66 , and the substrate  50 . Epitaxial source/drain regions will be subsequently formed in the first recesses  86 . The first recesses  86  may extend through the first nanostructures  52 , the second nanostructures  54 , and into the substrate  50 . As illustrated in  FIG.  9 A , top surfaces of the STI regions  68  may be level with bottom surfaces of the first recesses  86 . In various embodiments, the fins  66  may be etched such that bottom surfaces of the first recesses  86  are disposed above the top surfaces of the STI regions  68 , below the top surfaces of the STI regions  68 , or the like. The first recesses  86  may be formed by etching the nanostructures  55 , the fins  66 , and the substrate  50  using an anisotropic etch processes, such as RIE, NBE, or the like. The first spacers  81 , the second spacers  83 , and the masks  78  mask portions of the nanostructures  55 , the fins  66 , and the substrate  50  during the etch processes used to form the first recesses  86 . A single etch process or multiple etch processes may be used to etch each layer of the nanostructures  55 , the fins  66 , and/or the substrate  50 . Timed etch processes may be used to stop the etching of the first recesses  86  after the first recesses  86  reach a desired depth. 
     In  FIGS.  10 A and  10 B , portions of sidewalls of the layers of the multi-layer stack  64  formed of the first semiconductor materials (e.g., the first nanostructures  52 ) exposed by the first recesses  86  are etched to form sidewall recesses  88  in the n-type region  50 N, and portions of sidewalls of the layers of the multi-layer stack  64  formed of the second semiconductor materials (e.g., the second nanostructures  54 ) exposed by the first recesses  86  are etched to form sidewall recesses  88  in the p-type region  50 P. Although sidewalls of the first nanostructures  52  and the second nanostructures  54  adjacent the sidewall recesses  88  are illustrated as being straight in  FIG.  10 B , the sidewalls may be concave or convex. The sidewalls may be etched using isotropic etch processes, such as a wet etch or the like. The p-type region  50 P may be protected using a mask (not separately illustrated), while etchants selective to the first semiconductor materials are used to etch the first nanostructures  52 . As such, the second nanostructures  54  and the substrate  50  in the n-type region  50 N remain relatively un-etched as compared to the first nanostructures  52 . Similarly, the n-type region  50 N may be protected using a mask (not separately illustrated), while etchants selective to the second semiconductor materials are used to etch the second nanostructures  54 . As such, the first nanostructures  52  and the substrate  50  in the p-type region  50 P remain relatively un-etched as compared to the second nanostructures  54 . In an embodiment in which the first nanostructures  52  include, e.g., SiGe, and the second nanostructures  54  include, e.g., Si or SiC, a dry etch process with tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH 4 OH), or the like may be used to etch sidewalls of the first nanostructures  52  in the n-type region  50 N. A wet or dry etch process with hydrogen fluoride, another fluorine-based etchant, or the like may be used to etch sidewalls of the second nanostructures  54  in the p-type region  50 P. 
     In  FIGS.  11 A through  11 C , first inner spacers  90  are formed in the sidewall recesses  88 . The first inner spacers  90  may be formed by depositing an inner spacer layer (not separately illustrated) over the structures illustrated in  FIGS.  10 A and  10 B . The inner spacer layer may be deposited by a conformal deposition process, such as CVD, ALD, or the like. The inner spacer layer may comprise a material such as silicon nitride or silicon oxynitride, although any suitable material, such as low-dielectric constant (low-k) materials having a k-value less than about 3.5, may be utilized. The inner spacer layer may be anisotropically etched to form the first inner spacers  90 , using a process such as RIE, NBE, or the like. 
     Although outer sidewalls of the first inner spacers  90  are illustrated as being flush with sidewalls of the second nanostructures  54  in the n-type region  50 N and flush with the sidewalls of the first nanostructures  52  in the p-type region  50 P, the outer sidewalls of the first inner spacers  90  may extend beyond or be recessed from sidewalls of the second nanostructures  54  and/or the first nanostructures  52 . Moreover, although the outer sidewalls of the first inner spacers  90  are illustrated as being straight in  FIG.  11 B , the outer sidewalls of the first inner spacers  90  may be concave or convex. As an example,  FIG.  11 C  illustrates an embodiment in which sidewalls of the first nanostructures  52  are concave, outer sidewalls of the first inner spacers  90  are concave, and the first inner spacers  90  are recessed from sidewalls of the second nanostructures  54  in the n-type region  50 N. In  FIG.  11 C , sidewalls of the second nanostructures  54  are concave, outer sidewalls of the first inner spacers  90  are concave, and the first inner spacers  90  are recessed from sidewalls of the first nanostructures  52  in the p-type region  50 P. 
     The first inner spacers  90  act as isolation features between subsequently formed source/drain regions (such as the epitaxial source/drain regions  92 , discussed below with respect to  FIGS.  12 A through  12 D ) and gate structures (such as the gate structures including the gate dielectric layers  100  and the gate electrodes  102 , discussed below with respect to  FIGS.  17 A and  17 B ). The first inner spacers  90  may be also prevent damage to the epitaxial source/drain regions  92  by subsequent etching processes, such as etching processes used to form the gate structures including the gate dielectric layers  100  and the gate electrodes  102 . 
     In  FIGS.  12 A through  12 D , epitaxial source/drain regions  92  (which may include a first semiconductor material layer  92 A, a second semiconductor material layer  92 B, and a third semiconductor material layer  92 C) are formed in the first recesses  86  (illustrated in  FIGS.  11 B and  11 C ). In some embodiments, the epitaxial source/drain regions  92  may exert stress on the second nanostructures  54  in the n-type region  50 N and on the first nanostructures  52  in the p-type region  50 P, thereby improving performance. As illustrated in  FIG.  12 B , the epitaxial source/drain regions  92  are formed in the first recesses  86  such that each of the dummy gates  76  is disposed between respective neighboring pairs of the epitaxial source/drain regions  92 . In some embodiments, the first spacers  81  are used to separate the epitaxial source/drain regions  92  from the dummy gates  76  and the first inner spacers  90  are used to separate the epitaxial source/drain regions  92  from the nanostructures  55  by appropriate lateral distances to prevent shorts between the epitaxial source/drain regions  92  and subsequently formed gate structures (such as the gate structures including the gate dielectric layers  100  and the gate electrodes  102 , discussed below with respect to  FIGS.  17 A and  17 B ). 
     The epitaxial source/drain regions  92  in the n-type region  50 N, e.g., the NMOS region, may be formed by masking the p-type region  50 P, e.g., the PMOS region. Then, the epitaxial source/drain regions  92  are epitaxially grown in the first recesses  86  in the n-type region  50 N. The epitaxial source/drain regions  92  may include any acceptable material appropriate for n-type nanostructure FETs. For example, in embodiments in which the second nanostructures  54  are silicon, the epitaxial source/drain regions  92  may include materials exerting a tensile strain on the second nanostructures  54 , such as silicon, silicon carbide, phosphorous-doped silicon carbide, silicon phosphide, or the like. The epitaxial source/drain regions  92  may have surfaces raised from respective upper surfaces of the nanostructures  55  and may have facets. 
     The epitaxial source/drain regions  92  in the p-type region  50 P, e.g., the PMOS region, may be formed by masking the n-type region  50 N, e.g., the NMOS region. Then, the epitaxial source/drain regions  92  are epitaxially grown in the first recesses  86  in the p-type region  50 P. The epitaxial source/drain regions  92  may include any acceptable material appropriate for p-type nanostructure FETs. For example, in embodiments in which the first nanostructures  52  are silicon germanium, the epitaxial source/drain regions  92  may comprise materials exerting a compressive strain on the first nanostructures  52 , such as silicon-germanium, boron doped silicon-germanium, germanium, germanium tin, or the like. The epitaxial source/drain regions  92  may also have surfaces raised from respective surfaces of the nanostructures  55  and may have facets. 
     The epitaxial source/drain regions  92 , the nanostructures  55 , the fins  66 , and/or the substrate  50  may be implanted with dopants to form source/drain regions, similar to the process previously discussed for forming lightly-doped source/drain regions, followed by an anneal. The source/drain regions may have an impurity concentration of between about 1×10 19  atoms/cm 3  and about 1×10 21  atoms/cm 3 . The n-type and/or p-type impurities for the source/drain regions may be any of the impurities previously discussed. In some embodiments, the epitaxial source/drain regions  92  may be in situ doped during growth. 
     As a result of the epitaxy processes used to form the epitaxial source/drain regions  92  in the n-type region  50 N and the p-type region  50 P, upper surfaces of the epitaxial source/drain regions  92  have facets which expand laterally outward beyond sidewalls of the nanostructures  55 . In some embodiments, these facets cause adjacent epitaxial source/drain regions  92  of a same nanostructure FET to merge, as illustrated by  FIG.  12 A . In other embodiments, adjacent epitaxial source/drain regions  92  remain separated after the epitaxy process is completed, as illustrated by  FIG.  12 C . In the embodiments illustrated in  FIGS.  12 A and  12 C , the first spacers  81  may be formed extending to top surfaces of the STI regions  68 , thereby blocking the epitaxial growth. In some embodiments, the first spacers  81  may cover portions of the sidewalls of the nanostructures  55 , further blocking the epitaxial growth. In some embodiments, the spacer etch used to form the first spacers  81  may be adjusted to remove the spacer material, allowing the epitaxial source/drain regions  92  to extend to the surfaces of the STI regions  68 . 
     The epitaxial source/drain regions  92  may comprise one or more semiconductor material layers. For example, the epitaxial source/drain regions  92  may comprise a first semiconductor material layer  92 A, a second semiconductor material layer  92 B, and a third semiconductor material layer  92 C. Any number of semiconductor material layers may be used for the epitaxial source/drain regions  92 . Each of the first semiconductor material layer  92 A, the second semiconductor material layer  92 B, and the third semiconductor material layer  92 C may be formed of different semiconductor materials and may be doped to different dopant concentrations. In some embodiments, the first semiconductor material layer  92 A may have a dopant concentration less than the second semiconductor material layer  92 B and greater than the third semiconductor material layer  92 C. In embodiments in which the epitaxial source/drain regions  92  comprise three semiconductor material layers, the first semiconductor material layer  92 A may be deposited, the second semiconductor material layer  92 B may be deposited over the first semiconductor material layer  92 A, and the third semiconductor material layer  92 C may be deposited over the second semiconductor material layer  92 B. 
       FIG.  12 D  illustrates an embodiment in which sidewalls of the first nanostructures  52  in the n-type region  50 N and sidewalls of the second nanostructures  54  in the p-type region  50 P are concave, outer sidewalls of the first inner spacers  90  are concave, and the first inner spacers  90  are recessed from sidewalls of the second nanostructures  54  and the first nanostructures  52 . As illustrated in  FIG.  12 D , the epitaxial source/drain regions  92  may be formed in contact with the first inner spacers  90  and may extend past sidewalls of the second nanostructures  54  in the n-type region  50 N and past sidewalls of the first nanostructures  52  in the p-type region  50 P. 
     In  FIGS.  13 A through  13 C , a contact etch stop layer (CESL)  94  and a first interlayer dielectric (ILD)  96  are deposited over the epitaxial source/drain regions  92 , the dummy gate structures, the first spacers  81 , and the STI regions  68 . The CESL  94  may comprise a dielectric material, such as, silicon nitride, silicon oxide, silicon oxynitride, or the like, having a different etch rate than the material of the overlying first ILD  96 . The CESL  94  may be deposited by ALD, CVD, or the like. The CESL  94  may be optional and may be omitted in some embodiments. The first ILD  96  may be formed of a dielectric material, and may be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. Suitable dielectric materials may include phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped silicate glass (USG), or the like. Other insulation materials formed by any acceptable process may be used. 
     In  FIGS.  14 A and  14 B , a planarization process, such as a CMP, is performed to level top surfaces of the first ILD  96  with top surfaces of the dummy gates  76  or the masks  78 . The planarization process may also remove the masks  78  on the dummy gates  76 , and portions of the first spacers  81  along sidewalls of the masks  78 . After the planarization process, top surfaces of the dummy gates  76 , the first spacers  81 , the CESL  94 , and the first ILD  96  are level with one another (within process variations). Accordingly, the top surfaces of the dummy gates  76  are exposed through the first ILD  96  and the CESL  94 . In some embodiments, the masks  78  may remain, in which case the planarization process levels the top surfaces of the first ILD  96  and the CESL  94  with top surfaces of the masks  78  and the first spacers  81 . 
     In  FIGS.  15 A and  15 B , the dummy gates  76 , the dummy gate dielectrics  71 , and the masks  78 , if present, are removed, forming second recesses  98 . In some embodiments, the dummy gates  76  and the dummy gate dielectrics  71  are removed by one or more etch processes, such as anisotropic dry etch processes. The etch processes may include a dry etch process using reaction gas(es) that selectively etch the dummy gates  76  (at a faster rate than the first ILD  96 , the CESL  94 , or the first spacers  81 ). Each of the second recess  98  exposes and/or overlies portions of nanostructures  55 , which act as channel regions in subsequently completed nanostructure FETs. The portions of the nanostructures  55  that act as the channel regions are disposed between neighboring pairs of the epitaxial source/drain regions  92 . During the removal, the dummy gate dielectrics  71  may be used as etch stop layers when the dummy gates  76  are etched. The dummy gate dielectrics  71  may then be removed after the removal of the dummy gates  76 . 
     In  FIGS.  16 A and  16 B , the first nanostructures  52  in the n-type region  50 N and the second nanostructures  54  in the p-type region  50 P are removed extending the second recesses  98 . The first nanostructures  52  may be removed by forming a mask (not separately illustrated) over the p-type region  50 P and performing an isotropic etching process, such as wet etching or the like, using etchants which are selective to the materials of the first nanostructures  52 . The second nanostructures  54 , the fins  66 , the substrate  50 , the STI regions  68 , the first ILD  96 , and the CESL  94  remain relatively un-etched as compared to the first nanostructures  52 . In embodiments in which the first nanostructures  52  include, e.g., SiGe, and the second nanostructures  54  include, e.g., Si or SiC, tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH 4 OH), or the like may be used to remove the first nanostructures  52  in the n-type region  50 N. 
     The second nanostructures  54  in the p-type region  50 P may be removed by forming a mask (not separately illustrated) over the n-type region  50 N and performing an isotropic etching process such as wet etching or the like using etchants which are selective to the materials of the second nanostructures  54 . The first nanostructures  52 , the fins  66 , the substrate  50 , the STI regions  68 , the first ILD  96 , and the CESL  94  remain relatively un-etched as compared to the second nanostructures  54 . In embodiments in which the second nanostructures  54  include, e.g., SiGe, and the first nanostructures  52  include, e.g., Si or SiC, hydrogen fluoride, another fluorine-based etchant, or the like may be used to remove the second nanostructures  54  in the p-type region  50 P. 
     In other embodiments, the channel regions in the n-type region  50 N and the p-type region  50 P may be formed simultaneously. For example, the first nanostructures  52  in both the n-type region  50 N and the p-type region  50 P may be removed, or the second nanostructures  54  in both the n-type region  50 N and the p-type region  50 P may be removed. In such embodiments, channel regions of n-type nanostructure FETs and p-type nanostructure FETS may have a same material composition, such as silicon, silicon germanium, or the like.  FIGS.  22 A through  22 C  illustrate a structure resulting from embodiments in which channel regions in both the p-type region  50 P and the n-type region  50 N are provided by the second nanostructures  54  and comprise silicon. 
     In  FIGS.  17 A and  17 B , gate dielectric layers  100  and gate electrodes  102  are formed for replacement gates. The gate dielectric layers  100  are deposited conformally in the second recesses  98 . In the n-type region  50 N, the gate dielectric layers  100  may be formed on top surfaces and sidewalls of the fins  66  and on top surfaces, sidewalls, and bottom surfaces of the second nanostructures  54 . In the p-type region  50 P, the gate dielectric layers  100  may be formed on top surfaces and sidewalls of the fins  66 , on top surfaces and sidewalls of the first nanostructures  52 A, and on top surfaces, sidewalls, and bottom surfaces of the first nanostructures  52 B and  52 C. The gate dielectric layers  100  may also be deposited on top surfaces of the first ILD  96 , the CESL  94 , and the STI regions  68 ; on top surfaces and sidewalls of the first spacers  81 ; and on sidewalls of the first inner spacers  90 . 
     In some embodiments, the gate dielectric layers  100  comprise one or more dielectric layers, such as an oxide, a metal oxide, the like, or combinations thereof. For example, the gate dielectric layers  100  may comprise a silicon oxide layer and a metal oxide layer over the silicon oxide layer. In some embodiments, the gate dielectric layers  100  include a high-k dielectric material, and the gate dielectric layers  100  may have a k-value greater than about  7 . 0 . The gate dielectric layers  100  may include a metal oxide or a silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The structure of the gate dielectric layers  100  may be the same or different in the n-type region  50 N and the p-type region  50 P. The formation methods of the gate dielectric layers  100  may include molecular-beam deposition (MBD), ALD, PECVD, and the like. 
     The gate electrodes  102  are deposited over the gate dielectric layers  100  and fill remaining portions of the second recesses  98 . The gate electrodes  102  may include a metal-containing material such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multi-layers thereof. Although single-layer gate electrodes  102  are illustrated in  FIGS.  17 A and  17 B , the gate electrodes  102  may comprise any number of liner layers, any number of work function tuning layers, and a fill material. Any combination of the layers that make up the gate electrodes  102  may be deposited in the n-type region  50 N between adjacent ones of the second nanostructures  54  and between the second nanostructures  54 A and the fins  66 . Further, any combination of the layers that make up the gate electrodes  102  may be deposited in the p-type region  50 P between adjacent ones of the first nanostructures  52 . 
     The formation of the gate dielectric layers  100  in the n-type region  50 N and the p-type region  50 P may occur simultaneously, such that the gate dielectric layers  100  in each region are formed from the same materials. In some embodiments, the gate dielectric layers  100  in each region may be formed by distinct processes, such that the gate dielectric layers  100  may be different materials and/or have a different number of layers. The formation of the gate electrodes  102  in the n-type region  50 N and the p-type region  50 P may occur simultaneously such that the gate electrodes  102  in each region are formed from the same materials. The gate electrodes  102  in each region may be formed by distinct processes, such that the gate electrodes  102  may be different materials and/or have a different number of layers. Various masking steps may be used to mask and expose appropriate regions when using distinct processes. 
     After the second recesses  98  are filled, a planarization process, such as a CMP, may be performed to remove excess portions of the gate dielectric layers  100  and the material of the gate electrodes  102 , which excess portions are over top surfaces of the first ILD  96 , the CESL  94 , and the first spacers  81 . The remaining portions of material of the gate electrodes  102  and the gate dielectric layers  100  form replacement gate structures of the resulting nanostructure FETs. The gate electrodes  102  and the gate dielectric layers  100  may be collectively referred to as “gate structures.” The epitaxial source/drain regions  92 , the first nanostructures  52  or second nanostructures  54 , and the gate structures (including the gate dielectric layers  100  and the gate electrodes  102 ) may collectively be referred to as transistor structures  109 . 
     In  FIGS.  18 A and  18 B , the gate structures (including the gate dielectric layers  100  and the corresponding overlying gate electrodes  102 ) are recessed, so that recesses are formed directly over the gate structures and between opposing portions of first spacers  81 . An etch stop layer  103  may be deposited over the recessed gate structures. The etch stop layer  103  may include a conductive material, such as tungsten, ruthenium, cobalt, copper, molybdenum, nickel, combinations thereof, or the like. The etch stop layer  103  may have an etch rate different from that of a subsequently formed gate mask. The etch stop layer  103  may be deposited by ALD, CVD, PVD, or the like. In some embodiments, the etch stop layer  103  is formed of tungsten, such as fluorine-free tungsten (FFW), which is deposited by a selective deposition process, such as a selective CVD process. Because the etch stop layer  103  is formed of a conductive material, it can act to stop etching and to tune the contact resistance to the gate structures. In some embodiments, the etch stop layer  103  may include a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, or the like. 
     A gate mask  104  comprising one or more layers of dielectric material, such as silicon nitride, silicon oxynitride, or the like, is deposited over the etch stop layer  103  and fills the remainder of the recess. The deposition of the gate mask  104  may be followed by a planarization process to remove excess portions of the dielectric material, such as portions of the gate mask  104  extending over the first ILD  96 , the CESL  94 , and the first spacers  81 . Subsequently formed gate contacts (such as the gate contacts  118  and the butted contacts  120 , discussed below with respect to  FIGS.  21 A through  22 C ) penetrate through the gate mask  104  to contact top surfaces of the recessed etch stop layer  103 . 
     In  FIGS.  19 A through  19 C , silicide regions  106  and first source/drain contacts  108  are formed through the first ILD  96  and the CESL  94 . The first ILD  96  and the CESL  94  may be etched to form recesses exposing surfaces of the epitaxial source/drain regions  92 . The recesses may be formed by etching using anisotropic etch processes, such as RIE, NBE, or the like. In some embodiments, the recesses may be etched through the first ILD  96  using a first etch process and may then be etched through the CESL  94  using a second etch process. A mask, such as a photoresist, may be formed and patterned over the first ILD  96  to mask portions of the first ILD  96 , the CESL  94 , the first spacers  81 , and the gate mask  104  from the first etch process and the second etch process. In some embodiments, the etch processes may over-etch, and therefore, the recesses may extend into the epitaxial source/drain regions  92 . Bottom surfaces of the recesses may be level with (e.g., at a same level, or having a same distance from the substrate  50 ), or lower than (e.g., closer to the substrate  50 ) top surfaces of the epitaxial source/drain regions  92 . 
     After the recesses are formed, the silicide regions  106  may be formed over the epitaxial source/drain regions  92 . In some embodiments, the silicide regions  106  are formed by first depositing a metal (not separately illustrated) capable of reacting with the semiconductor materials of the underlying epitaxial source/drain regions  92  (e.g., silicon, silicon germanium, germanium, or the like) to form silicide or germanide regions, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other noble metals, other refractory metals, rare earth metals or their alloys, over the exposed portions of the epitaxial source/drain regions  92 . A thermal anneal process may then be performed to form the silicide regions  106 . Un-reacted portions of the deposited metal are removed by an etch process. Although referred to as silicide regions, the silicide regions  106  may be replaced by germanide regions, silicon germanide regions (e.g., regions comprising silicide and germanide), or the like. In an embodiment, the silicide regions  106  comprise TiSi, and have a thickness ranging from about 2 nm to about 10 nm. 
     The first source/drain contacts  108  are then formed over the silicide regions  106  and filling the recesses. The first source/drain contacts  108  may each comprise one or more layers, such as barrier layers, diffusion layers, and fill materials. For example, in some embodiments, the first source/drain contacts  108  each include a barrier layer and a conductive material over the conductive material. The conductive material of each of the first source/drain contacts  108  may be electrically coupled to the underlying epitaxial source/drain regions  92  through the silicide regions  106 . The barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material may be cobalt (Co), ruthenium (Ru), titanium (Ti), tungsten (W), copper (Cu), a copper alloy, silver (Ag), gold (Au), aluminum (Al), nickel (Ni), or the like. After the first source/drain contacts  108  are formed, a planarization process, such as a CMP, may be performed to remove excess material from surfaces of the first ILD  96 , the CESL  94 , the first spacers  81 , and the gate mask  104 . 
     In  FIGS.  20 A through  20 C , a second CESL  112  and a second ILD  114  are formed over the structures illustrated in  FIGS.  19 A through  19 C , respectively. The second CESL  112  may comprise a dielectric material, such as, silicon nitride, silicon oxide, silicon oxynitride, or the like, having a different etch rate than the material of the overlying second ILD  114 . The second CESL  112  may be deposited by a conformal deposition process, such as ALD, CVD, or the like. The second ILD  114  may be formed of a dielectric material, and may be deposited by any suitable method, such as CVD, PECVD, or FCVD. Suitable dielectric materials may include PSG, BSG, BPSG, USG, or the like. Other insulation materials formed by any acceptable process may be used. 
     In  FIGS.  21 A through  21 C , second source/drain contacts  116 , gate contacts  118 , and/or butted contacts  120  (each of which may also be referred to as contact plugs) are formed extending through the second ILD  114  and the second CESL  112 . Openings for the second source/drain contacts  116  are formed through the second ILD  114  and the second CESL  112 . Openings for the gate contacts  118  are formed through the second ILD  114 , the second CESL  112 , and the gate mask  104 . Openings for the butted contacts  120  are formed through the second ILD  114 , the second CESL  112 , and the gate mask  104 . The openings may be formed using acceptable photolithography and etching techniques. A liner, such as a diffusion barrier layer, an adhesion layer, or the like, and a conductive material are formed in the openings. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material may be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process, such as a CMP, may be performed to remove excess material from a surface of the second ILD  114 . The remaining liner and conductive material form the second source/drain contacts  116 , the gate contacts  118 , and the butted contacts  120  in the openings. The butted contacts  120  may be useful for forming circuitry in the various regions, such as in an SRAM cell. 
     The second source/drain contacts  116  are electrically coupled to the epitaxial source/drain regions  92  through the first source/drain contacts  108  and the silicide regions  106 . The gate contacts  118  are electrically coupled to the gate electrodes  102  through the etch stop layer  103 . The butted contacts  120  are electrically coupled to the epitaxial source/drain regions  92  through the first source/drain contacts  108  and the silicide regions  106  and to the gate electrodes  102  through the etch stop layer  103 . The second source/drain contacts  116 , the gate contacts  118 , and the butted contacts  120  may be formed in different processes, or may be formed in the same process. Although shown as being formed in the same cross-sections, it should be appreciated that each of the second source/drain contacts  116 , the gate contacts  118 , and the butted contacts  120  may be formed in different cross-sections, which may avoid shorting of the contacts. 
       FIGS.  22 A through  22 C  illustrate cross-sectional views of a device according to some alternative embodiments.  FIGS.  22 A  illustrates reference cross-section A-A′ illustrated in  FIG.  1   .  FIG.  22 B  illustrates reference cross-section B-B′ illustrated in  FIG.  1   . FIG.  22 C illustrates reference cross-section C-C′ illustrated in  FIG.  1   . In  FIGS.  22 A through  22 C , like reference numerals indicate like elements formed by like processes as the structure of  FIGS.  21 A through  21 C . However, in  FIGS.  22 A through  22 C , channel regions in the n-type region  50 N and the p-type region  50 P comprise a same material. For example, the second nanostructures  54 , which comprise silicon, provide channel regions for p-type nano-FETs in the p-type region  50 P and for n-type nano-FETs in the n-type region  50 N. The structure of  FIGS.  22 A through  22 C  may be formed, for example, by removing the first nanostructures  52  from both the p-type region  50 P and the n-type region  50 N simultaneously; depositing the gate dielectric layers  100  over top surfaces and side surfaces of the fins  66  and over top surfaces, side surfaces, and bottom surfaces of the second nanostructures  54  in the p-type region  50 P and the n-type region  50 N; and depositing gate electrodes  102 P (e.g., gate electrodes suitable for p-type nano-FETs) over the gate dielectric layers  100  in the p-type region  50 P and depositing gate electrodes  102 N (e.g., gate electrodes suitable for n-type nano-FETs) over the gate dielectric layers in the n-type region  50 N. Materials of the epitaxial source/drain regions  92  in the n-type region  50 N may be different from materials of the epitaxial source/drain regions  92  in the p-type region  50 P, as explained above. 
     In  FIGS.  23 A through  36   , a front-side interconnect structure  140  (illustrated in  FIGS.  27 A,  27 B,  28 ,  32 , and  36   ) is formed over the second ILD  114 , the second source/drain contacts  116 , the gate contacts  118 , and the butted contacts  120 , in accordance with some embodiments. The front-side interconnect structure  140  may be electrically coupled to the second source/drain contacts  116 , the gate contacts  118 , and/or the butted contacts  120 . In  FIGS.  23 A and  23 B , a first dielectric layer  122  and first conductive features  124  are formed over the second ILD  114 , the second source/drain contacts  116 , the gate contacts  118 , and the butted contacts  120 . The first dielectric layer  122  may comprise a dielectric material, such as a low-k dielectric material, an extra low-k (ELK) dielectric material, or the like. In some embodiments, the first dielectric layer  122  may comprise silicon carbonitride (SiCN), silicon oxycarbide (SiOC), silicon boron nitride (SiBN), silicon boron carbon nitride (SiBCN), boron nitride (BN), combinations or multiple layers thereof, or the like. The first dielectric layer  122  may be deposited using an appropriate process, such as, CVD, ALD, PVD, PECVD, or the like. 
     The first conductive features  124  may comprise conductive lines. The first conductive features  124  may be collectively referred to as metal layer MO. The first conductive features  124  may be formed through any acceptable process, such as, a damascene process, a dual damascene process, or the like. In some embodiments, the first conductive features  124  may be formed using a damascene process in which the first dielectric layer  122  is patterned utilizing a combination of photolithography and etching techniques to form trenches corresponding to the desired pattern of the first conductive features  124 . An optional diffusion barrier layer, an optional liner layer, and/or optional adhesion layer may be deposited and the trenches may then be filled with a conductive material. Suitable materials for the diffusion barrier layer include titanium, titanium nitride, titanium oxide, tantalum, tantalum nitride, titanium oxide, combinations thereof, or the like; suitable materials for the liner layer include cobalt, ruthenium, combinations thereof, or the like; and suitable materials for the conductive material include copper, silver, gold, tungsten, aluminum, cobalt, ruthenium, molybdenum, combinations thereof, or the like. In an embodiment, the first conductive features  124  may be formed by depositing a seed layer of copper or a copper alloy, and filling the trenches by electroplating. A CMP process or the like may be used to remove excess conductive material from a surface of the first dielectric layer  122  and to planarize surfaces of the first dielectric layer  122  and the first conductive features  124  for subsequent processing. The first conductive features  124  may be electrically coupled to the gate structures and/or the epitaxial source/drain regions  92  through the second source/drain contacts  116 , the gate contacts  118 , and the butted contacts  120 . 
     In  FIGS.  24 A and  24 B , an inhibitor material  125  is formed over the first conductive features  124  and an etch-resistant layer  126  is formed over the first dielectric layer  122 . The inhibitor material  125  may be selectively deposited over the first conductive features  124 , without being deposited on the first dielectric layer  122 . As illustrated in  FIGS.  24 A and  24 B , sidewalls of the inhibitor material  125  may be aligned with/coterminous with sidewalls of the first conductive features  124 . In some embodiments, the inhibitor material  125  may be a silane, a phosphonic acid, an organic polymer (such as a polyimide (PI), a polyamide, or the like), or the like. In some embodiments, the inhibitor material  125  may be formed of an organic compound having from  8  to  20  carbon atoms. Specific examples of materials that may be used for the inhibitor material  125  include dodecylsilane (C 12 H 28 Si), octadecylphosphonic acid (ODPA, C 18 H 39 O 3 P), pyromellitic dianhydride (C 10 H 2 O 6 ), 1,6-diaminohexane (H 2 N(CH 2 ) 6 NH 2 ), ethylenediamine (C 2 H 8 N 2 ), adipoyl chloride (C 6 H 8 Cl 2 O 2 ), or the like. The inhibitor material  125  may be deposited to a thickness ranging from about 10 Å to about 50 Å. The inhibitor material  125  may be deposited in a wet deposition process or a dry deposition process. The inhibitor material  125  may be deposited at a temperature ranging from about 40° C. to about 300° C., for a time ranging from about 30 seconds to about 30 minutes, at a dry pressure ranging from about 1 Torr to about 10 Torr. The inhibitor material  125  may be deposited before the etch-resistant layer  126  and may be used to prevent the etch-resistant layer  126  from being deposited on the first conductive features  124 . This improves the contact area between the first conductive features  124  and subsequently formed conductive features (such as the capping layer  128 , discussed below with respect to  FIGS.  25 A and  25 B , and the second conductive features  134 , discussed below with respect to  FIGS.  27 A and  27 B ), reduces contact resistance, and improves device performance. 
     The etch-resistant layer  126  is then selectively deposited over the first dielectric layer  122 , without being deposited on the inhibitor material  125 . As illustrated in  FIGS.  24 A and  24 B , sidewalls of the etch-resistant layer  126  may be aligned with/coterminous with sidewalls of the first dielectric layer  122 . The etch-resistant layer  126  may be deposited by CVD, ALD, or the like. The etch-resistant layer  126  may be a dielectric material, such as aluminum oxide (Al 2 O 3 ), silicon oxide (SiO 2 ), silicon nitride (SiN), silicon carbonitride (SiCN), silicon oxycarbide (SiOC), boron nitride (BN), silicon boron nitride (SiBN), yttrium oxide (Y 2 O 3 ), zirconium oxide (ZrO 2 ), combinations or multiple layers thereof, or the like. The etch-resistant layer  126  is formed of a material having a high etch selectivity to subsequently deposited dielectric layers (such as the second etch stop layer  130  and the second dielectric layer  132 , discussed below with respect to  FIGS.  26 A and  26 B ). As such, the etch-resistant layer  126  may be used to protect the underlying first dielectric layer  122  from subsequent etching of the second etch stop layer  130  and the second dielectric layer  132 . This prevents leakage issues and reliability issues (e.g., time-dependent dielectric breakdown (TDDB), electromigration (EM), stress migration (SM), and the like) caused by damage to the first dielectric layer  122 , reduces device defects, and improves device performance. 
     The etch-resistant layer  126  may be deposited to a thickness ranging from about 10 Å to about 30 Å. Forming the etch-resistant layer  126  to a thickness less than the prescribed range may be insufficient for the etch-resistant layer  126  to act as an etch stop layer and may provide inadequate protection for the underlying materials, such as the first dielectric layer  122 . This may lead to damage of the first dielectric layer  122  during subsequent etch processes, which causes leakage and reliability issues in the completed device. Forming the etch-resistant layer  126  to a thickness greater than the prescribed range may cause the etch-resistant layer  126  to extend onto the inhibitor material  125 . This may decrease the contact area between the first conductive features  124  and subsequently formed conductive features, which increases contact resistance and reduces device performance. 
     In  FIGS.  25 A and  25 B , the inhibitor material  125  is removed and a capping layer  128  is formed over the first conductive features  124  adjacent the etch-resistant layer  126 . The inhibitor material  125  may be removed by a wet etching process, a dry etching process, a plasma process, or the like. The processes used to remove the inhibitor material  125  may have a high etch selectivity with respect to the etch-resistant layer  126  and the first conductive features  124 , such that the inhibitor material  125  are removed without significantly removing the etch-resistant layer  126  or the first conductive features  124 . Top surfaces of the first conductive features  124  may be exposed after removing the inhibitor material  125 . 
     The capping layer  128  is then deposited over the first conductive features  124 . The capping layer  128  may be selectively deposited over the first conductive features  124 , without being deposited on the etch-resistant layer  126 . As illustrated in  FIGS.  25 A and  25 B , sidewalls of the capping layer  128  may be aligned with/coterminous with sidewalls of the first conductive features  124 . The capping layer  128  may comprise a conductive material, such as cobalt, ruthenium, or the like. In embodiments in which the capping layer  128  comprises cobalt, precursors used to deposit the capping layer  128  may include cyclopentadienylcobalt dicarbonyl ((C 5 H 5 )Co(CO) 2 , C p Co(CO) 2 ), bis(cyclopentadienyl)cobalt(II) (Co(C 5 H 5 ) 2 ), or the like. In embodiments in which the capping layer  128  comprises ruthenium, precursors used to deposit the capping layer  128  may include triruthenium dodecacarbonyl (Ru 3 (CO) 12 ), bis(ethylcyclopentadienyl)ruthenium(II) (C 7 H 9 RuC 7 H 9 ), cyclopentadienyl ethyl (dicarbonyl) ruthenium (C p Ru(CO) 2 Et), or the like. The capping layer  128  may be deposited at a temperature ranging from about 150° C. to about 350° C., for a time ranging from about 5 seconds to about 3 minutes, at a pressure ranging from about 1 Torr to about 20 Torr. The capping layer  128  may be deposited to a thickness ranging from about 10 Å to about 50 Å. The capping layer  128  may be used to provide electromigration protection. Forming the capping layer  128  to a thickness less than the prescribed range may be insufficient for the capping layer  128  to provide electromigration protection. Forming the capping layer  128  to a thickness greater than the prescribed range may increase RC delay, reducing device performance. 
     In  FIGS.  26 A and  26 B , a second etch stop layer  130  is deposited over the etch-resistant layer  126  and the capping layer  128  and a second dielectric layer  132  is deposited over the second etch stop layer  130 . The second etch stop layer  130  may comprise a dielectric material, such as aluminum nitride (AlN), aluminum oxide (Al2O3), silicon carbonitride (SiCN), silicon oxycarbide (SiOC), silicon boron nitride (SiBN), boron nitride (BN), combinations or multiple layers thereof, or the like. In some embodiments, the second etch stop layer  130  may be a monolayer, a bilayer, a trilayer, a quadruple layer, or may include any number of layers. The second etch stop layer  130  may be formed of a material having a different etch rate from the material of the overlying second dielectric layer  132 . The second etch stop layer  130  may be formed by a deposition process such as CVD, ALD, or the like. 
     The second dielectric layer  132  may comprise a dielectric material, such as a low-k dielectric material, an extra low-k (ELK) dielectric material, or the like. In some embodiments, the second dielectric layer  132  may comprise silicon carbonitride (SiCN), silicon oxycarbide (SiOC), silicon boron nitride (SiBN), silicon boron carbon nitride (SiBCN), boron nitride (BN), combinations or multiple layers thereof, or the like. The second dielectric layer  132  may be deposited using an appropriate process, such as, CVD, ALD, PVD, PECVD, or the like. A planarization process, such as a CMP, may be performed to planarize the second dielectric layer  132  after the second dielectric layer  132  is deposited. 
     In  FIGS.  27 A and  27 B , second conductive features  134  are formed extending through the second dielectric layer  132 , the second etch stop layer  130 , and the etch-resistant layer  126 . The first dielectric layer  122 , the first conductive features  124 , the etch-resistant layer  126 , the capping layer  128 , the second etch stop layer  130 , the second dielectric layer  132 , and the second conductive features  134  may collectively be referred to as front-side interconnect structure  140 . 
     The second conductive features  134  may be formed by first forming openings or trenches (not separately illustrated) extending through the second dielectric layer  132  and the second etch stop layer  130 . The openings may be etched using acceptable photolithography and etch processes. In some embodiments, the second conductive features  134  may be formed by a dual damascene process and the openings may be formed by a two-step etch process. The etch processes may include forming a first patterned etch mask (not separately illustrated), such as a first patterned photoresist, and then etching the second dielectric layer  132  using the first patterned photoresist as a mask. First openings may be formed extending partially through the second dielectric layer  132  using acceptable etch processes, such as wet or dry etching, RIE, NBE, the like, or a combination thereof. Timed etch processes may be used to form the first openings extending through upper portions of the second dielectric layer  132  to a desired depth. The first patterned photoresist may be removed and a second patterned photoresist may be formed over the second dielectric layer  132 . Portions of the first openings may then be extended through the second dielectric layer  132  and the second etch stop layer  130  using the acceptable etch processes to form second openings. The second patterned photoresist may then be removed. The etch-resistant layer  126 , formed of a material having a high etch selectivity to materials of the second dielectric layer  132  and the second etch stop layer  130 , protects the first dielectric layer from the etch processes used to form the openings through the second dielectric layer  132  and the second etch stop layer  130 . This reduces leakage and reliability issues, improving device performance and reducing device defects. 
     The second conductive features  134  are then formed in the openings, forming the front-side interconnect structure  140 . The second conductive features  134  include conductive via portions formed in lower portions of the second dielectric layer  132  and the second etch stop layer  130  and conductive line portions formed in upper portions of the second dielectric layer  132 . The second conductive features  134  may be formed by depositing a liner layer extending along top surfaces of the capping layer  128 , top surfaces and side surfaces of the second dielectric layer  132 , and side surfaces of the second etch stop layer  130 . A conductive fill material then fills the remainder of the openings. In some embodiments, the liner layer is a barrier layer, which may include titanium, titanium nitride, tantalum, tantalum nitride, or the like. In some embodiments, the liner layer may be formed of cobalt, ruthenium, or the like. The liner layer may be formed by a conformal deposition process, such as CVD, ALD, PVD, or the like. In some embodiments, the liner layer may further include a metal seed layer, which may include copper, and which may be formed by PVD or the like. 
     After forming the liner layer, the conductive fill material is deposited to fill the remainder of the openings. Excess material of the conductive fill material may also be formed along top surfaces of the liner layer over the second dielectric layer  132 . The conductive fill material may be a metallic material, which may include copper, a copper alloy, cobalt, ruthenium, tungsten, molybdenum, silver, gold, aluminum, manganese, alloys or combinations thereof, or the like. The conductive fill material may be deposited by electrochemical plating (ECP), electroless plating, CVD, PVD, ALD, or the like. A planarization process, such as a CMP, may be performed to remove excess material of the liner layer and the conductive fill material from surfaces of the second dielectric layer  132 . 
     The via portions of the second conductive features  134  formed in the lower portions of the second dielectric layer  132  and the etch stop layer  130  may be collectively referred to as via layer V 0 . The conductive line portions of the second conductive features  134  formed in the upper portions of the second dielectric layer  132  may be collectively referred to as metal layer M 1 . Any number of the via portions and the line portions may be located in a given cross-section in the n-type region  50 N and the p-type region  50 P. Further, although the above-described embodiments have been described in a particular context, metal layers M 0  and M 1 , via layer V 0 , and an interconnect structure formed over a die comprising nano-FETs, various embodiments may be applied to various metal layers and via layers of an interconnect structure and dies comprising other types of transistors (e.g., fin field effect transistors (FinFETs), planar transistors, or the like), or other types of integrated circuit devices (e.g., resistors, capacitors, diodes, or the like), in lieu of or in combination with the nano-FETs and to any layers of interconnect structures. 
     The above-described embodiment may achieve various advantages. For example, forming the inhibitor material  125  before forming the etch-resistant layer  126  prevents the etch-resistant layer  126  from extending over the first conductive features  124 , which improves contact between the capping layer  128  and the first conductive features  124 . This decreases contact resistance and improves device performance. Forming the etch-resistant layer  126  over the first dielectric layer  122  protects the first dielectric layer  122  from etch processes used to etch the second dielectric layer  132  and the second etch stop layer  130 , preventing damage to the first dielectric layer  122 . This reduces leakage and reliability issues, improving device performance and reducing device defects. 
       FIG.  28    illustrates an embodiment in which the second conductive features  134  are misaligned with the first conductive features  124  and the capping layer  128 . More specifically, the via portions of the second conductive features  134  are misaligned with the first conductive features  124  and the capping layer  128 . As illustrated in  FIG.  28   , even when the second conductive features  134  are misaligned with the first conductive features  124  and the capping layer  128 , the etch-resistant layer  126  protects the underlying first dielectric layer  122  from the etch processes used to form the openings in which the second conductive features  134  are formed. The etch-resistant layer  126  may be partially etched through by the etch processes used to form the openings in which the second conductive features  134  are formed. Using the etch-resistant layer  126  to protect the first dielectric layer  122  prevents damage to the first dielectric layer  122 , which reduces leakage, improves reliability, reduces device defects, and increases device performance. 
       FIGS.  29  through  36    illustrate embodiments in which either the first dielectric layer  122  is etched back to a greater extent than the first conductive features  124  (illustrated in  FIGS.  29  through  32   ) or the first conductive features  124  are etched back to a greater extent than the first dielectric layer  122  (illustrated in  FIGS.  33  through  36   ) during the CMP discussed above with respect to  FIGS.  23 A and  23 B . In  FIG.  29   , various CMP and cleaning processes may be performed on the first dielectric layer  122  and the first conductive features  124 . Following the CMP and cleaning processes, top surfaces of the first dielectric layer  122  are disposed below top surfaces of the first conductive features  124 . The top surfaces of the first dielectric layer  122  may be recessed below the top surfaces of the first conductive features  124  by a distance D 1  ranging from about 5 Å to about 20 Å. 
     In  FIG.  30   , an inhibitor material  125  is formed over the first conductive features  124  and an etch-resistant layer  126  is formed over the first dielectric layer  122 . The inhibitor material  125  may be formed of materials and by methods similar to or the same as those discussed above with respect to  FIGS.  24 A and  24 B . As illustrated in  FIG.  30   , sidewalls of the inhibitor material  125  may be aligned with/coterminous with sidewalls of the first conductive features  124 . The inhibitor material  125  may be deposited to a thickness ranging from about 10 Å to about 50 Å. The inhibitor material  125  may be selectively deposited over the first conductive features  124  before forming the etch-resistant layer  126 . The etch-resistant layer  126  may be formed of materials and by methods similar to or the same as those discussed above with respect to  FIGS.  24 A and  24 B . The etch-resistant layer  126  may be selectively deposited over the first dielectric layer  122  after forming the inhibitor material  125 . As illustrated in  FIG.  30   , sidewalls of the etch-resistant layer  126  may be aligned with/coterminous with sidewalls of the first dielectric layer  122 . As discussed previously, the inhibitor material  125  prevents the etch-resistant layer  126  from being deposited on the first conductive features  124 , which increases the contact area between the first conductive features  124  and subsequently formed conductive features (such as the second conductive features  134 , discussed below with respect to  FIG.  32   ). This reduces contact resistance and improves device performance. 
     The etch-resistant layer  126  may be deposited to a thickness ranging from about 10 Å to about 30 Å. Forming the etch-resistant layer  126  to a thickness less than the prescribed range may be insufficient for the etch-resistant layer  126  to act as an etch stop layer and may provide inadequate protection for the underlying materials, such as the first dielectric layer  122 . This may lead to damage of the first dielectric layer  122  during subsequent etch processes, which causes leakage and reliability issues in the completed device. Forming the etch-resistant layer  126  to a thickness greater than the prescribed range may cause the etch-resistant layer  126  to extend onto the inhibitor material  125 . This may decrease the contact area between the first conductive features  124  and subsequently formed conductive features, which increases contact resistance and reduces device performance. 
     In  FIG.  31   , the inhibitor material  125  is removed and a capping layer  128  is formed over the first conductive features  124 . The inhibitor material  125  may be removed by methods similar to or the same as those discussed above with respect to  FIGS.  25 A and  25 B . Top surfaces and side surfaces of the first conductive features  124  may be exposed after removing the inhibitor material  125 . The capping layer  128  may then be formed over the first conductive features  124 . The capping layer  128  may be formed of materials and by methods similar to or the same as those discussed above with respect to  FIGS.  25 A and  25 B . As illustrated in  FIG.  31   , the capping layer  128  may be selectively deposited on the first conductive features  124 , without being deposited on the etch-resistant layer  126 . As illustrated in  FIG.  31   , sidewalls of the capping layer  128  may be aligned with/coterminous with sidewalls of the first conductive features  124 . In the embodiment illustrated in  FIG.  31   , the capping layer  128  is deposited with top surfaces level with top surfaces of the etch-resistant layer  126 . However, in some embodiments, the top surfaces of the capping layer  128  may be disposed above or below the top surfaces of the etch-resistant layer  126 . The capping layer  128  may be deposited to a thickness ranging from about 10 Å to about 50 Å. The capping layer  128  may be used to provide electromigration protection. Forming the capping layer  128  to a thickness less than the prescribed range may be insufficient for the capping layer  128  to provide electromigration protection. Forming the capping layer  128  to a thickness greater than the prescribed range may increase RC delay, reducing device performance. 
     In  FIG.  32   , a second etch stop layer  130 , a second dielectric layer  132 , and second conductive features  134  are formed over the capping layer  128  and the etch-resistant layer  126 . The second etch stop layer  130  is formed over the capping layer  128  and the etch-resistant layer  126 . The second etch stop layer  130  may be formed of materials and by methods similar to or the same as those discussed above with respect to  FIGS.  26 A and  26 B . The second dielectric layer  132  is then formed over the second etch stop layer  130 . The second dielectric layer  132  may be formed of materials and by methods similar to or the same as those discussed above with respect to  FIGS.  26 A and  26 B . Openings are formed in the second dielectric layer  132  and the second etch stop layer  130 . The second conductive features  134  are then formed in the openings. The second conductive features  134  may be formed of materials and by methods similar to or the same as those discussed above with respect to  FIGS.  27 A and  27 B . 
     The embodiment illustrated in  FIGS.  29  through  32    may achieve various advantages. For example, forming the inhibitor material  125  before forming the etch-resistant layer  126  prevents the etch-resistant layer  126  from extending over the first conductive features  124 , which improves contact between the capping layer  128  and the first conductive features  124 . This decreases contact resistance and improves device performance. Forming the etch-resistant layer  126  over the first dielectric layer  122  protects the first dielectric layer  122  from etch processes used to etch the second dielectric layer  132  and the second etch stop layer  130 , preventing damage to the first dielectric layer  122 . This reduces leakage and reliability issues, improving device performance and reducing device defects. 
     In  FIG.  33   , various CMP and cleaning processes may be performed on the first dielectric layer  122  and the first conductive features  124 . Following the CMP and cleaning processes, top surfaces of the first conductive features  124  are disposed below top surfaces of the first dielectric layer. The top surfaces of the first conductive features  124  may be recessed below the top surfaces of the first dielectric layer  122  by a distance D 2  ranging from about 5 Å to about 20 Å. 
     In  FIG.  34   , an inhibitor material  125  is formed over the first conductive features  124  and an etch-resistant layer  126  is formed over the first dielectric layer  122 . The inhibitor material  125  may be formed of materials and by methods similar to or the same as those discussed above with respect to  FIGS.  24 A and  24 B . The inhibitor material  125  may be deposited to a thickness ranging from about 10 Å to about 50 Å. The inhibitor material  125  may be selectively deposited over the first conductive features  124  before forming the etch-resistant layer  126 . As illustrated in  FIG.  34   , sidewalls of the inhibitor material  125  may be aligned with/coterminous with sidewalls of the first conductive features  124 . The etch-resistant layer  126  may be formed of materials and by methods similar to or the same as those discussed above with respect to  FIGS.  24 A and  24 B . The etch-resistant layer  126  may be selectively deposited over the first dielectric layer  122  after forming the inhibitor material  125 . As illustrated in  FIG.  34   , sidewalls of the etch-resistant layer  126  may be aligned with/coterminous with sidewalls of the first dielectric layer  122 . As discussed previously, the inhibitor material  125  prevents the etch-resistant layer  126  from being deposited on the first conductive features  124 , which increases the contact area between the first conductive features  124  and subsequently formed conductive features (such as the second conductive features  134 , discussed below with respect to  FIG.  36   ). This reduces contact resistance and improves device performance. 
     The etch-resistant layer  126  may be deposited to a thickness ranging from about 10 Å to about 30 Å. Forming the etch-resistant layer  126  to a thickness less than the prescribed range may be insufficient for the etch-resistant layer  126  to act as an etch stop layer and may provide inadequate protection for the underlying materials, such as the first dielectric layer  122 . This may lead to damage of the first dielectric layer  122  during subsequent etch processes, which causes leakage and reliability issues in the completed device. Forming the etch-resistant layer  126  to a thickness greater than the prescribed range may cause the etch-resistant layer  126  to extend onto the inhibitor material  125 . This may decrease the contact area between the first conductive features  124  and subsequently formed conductive features, which increases contact resistance and reduces device performance. 
     In  FIG.  35   , the inhibitor material  125  is removed and a capping layer  128  is formed over the first conductive features  124 . The inhibitor material  125  may be removed by methods similar to or the same as those discussed above with respect to  FIGS.  25 A and  25 B . Top surfaces of the first conductive features  124  may be exposed after removing the inhibitor material  125 . The capping layer  128  may then be formed over the first conductive features  124 . The capping layer  128  may be formed of materials and by methods similar to or the same as those discussed above with respect to  FIGS.  25 A and  25 B . As illustrated in  FIG.  35   , the capping layer  128  may be selectively deposited on the first conductive features  124 , without being deposited on the etch-resistant layer  126 . As illustrated in  FIG.  35   , sidewalls of the capping layer  128  may be aligned with/coterminous with sidewalls of the first conductive features  124 . In the embodiment illustrated in  FIG.  31   , the capping layer  128  is deposited with top surfaces level with top surfaces of the first dielectric layer  122 . However, in some embodiments, the top surfaces of the capping layer  128  may be disposed above or below the top surfaces of the first dielectric layer  122 . The capping layer  128  may be deposited to a thickness ranging from about 10 Å to about 50 Å. The capping layer  128  may be used to provide electromigration protection. Forming the capping layer  128  to a thickness less than the prescribed range may be insufficient for the capping layer  128  to provide electromigration protection. Forming the capping layer  128  to a thickness greater than the prescribed range may increase RC delay, reducing device performance. 
     In  FIG.  36   , a second etch stop layer  130 , a second dielectric layer  132 , and second conductive features  134  are formed over the capping layer  128  and the etch-resistant layer  126 . The second etch stop layer  130  is formed over the capping layer  128  and the etch-resistant layer  126 . The second etch stop layer  130  may be formed of materials and by methods similar to or the same as those discussed above with respect to  FIGS.  26 A and  26 B . The second dielectric layer  132  is then formed over the second etch stop layer  130 . The second dielectric layer  132  may be formed of materials and by methods similar to or the same as those discussed above with respect to  FIGS.  26 A and  26 B . Openings are formed in the second dielectric layer  132  and the second etch stop layer  130 . The second conductive features  134  are then formed in the openings. The second conductive features  134  may be formed of materials and by methods similar to or the same as those discussed above with respect to  FIGS.  27 A and  27 B . 
     The embodiment illustrated in  FIGS.  33  through  36    may achieve various advantages. For example, forming the inhibitor material  125  before forming the etch-resistant layer  126  prevents the etch-resistant layer  126  from extending over the first conductive features  124 , which improves contact between the capping layer  128  and the first conductive features  124 . This decreases contact resistance and improves device performance. Forming the etch-resistant layer  126  over the first dielectric layer  122  protects the first dielectric layer  122  from etch processes used to etch the second dielectric layer  132  and the second etch stop layer  130 , preventing damage to the first dielectric layer  122 . This reduces leakage and reliability issues, improving device performance and reducing device defects. 
     Embodiments may achieve various advantages. For example, forming the inhibitor material before forming the etch-resistant layer prevents the etch-resistant layer from extending over the first conductive features, which improves contact between the capping layer and the first conductive features. This decreases contact resistance and improves device performance. Forming the etch-resistant layer over the first dielectric layer protects the first dielectric layer from etch processes used to etch the second dielectric layer and the second etch stop layer, preventing damage to the first dielectric layer. This reduces leakage and reliability issues, improving device performance and reducing device defects. 
     In accordance with an embodiment, a method includes forming a first dielectric layer over an integrated circuit device; forming a first conductive feature in the first dielectric layer; selectively depositing an inhibitor material over the first conductive feature; selectively depositing an etch-resistant layer over the first dielectric layer adjacent the inhibitor material; removing the inhibitor material to form a first opening exposing the first conductive feature; selectively depositing a capping layer over the first conductive feature; forming an etch stop layer over the etch-resistant layer and the capping layer; forming a second dielectric layer over the etch stop layer; etching the second dielectric layer and the etch stop layer to form a second opening exposing the capping layer; and forming a second conductive feature in the second opening and electrically coupled to the first conductive feature through the capping layer. In an embodiment, the inhibitor material includes an organic polymer including 8 to 20 carbon atoms. In an embodiment, the etch-resistant layer is deposited to a thickness ranging from 10 Å to 30 Å. In an embodiment, the etch-resistant layer is selectively deposited before selectively depositing the capping layer. In an embodiment, the etch-resistant layer includes a material selected from aluminum oxide (Al 2 O 3 ), silicon dioxide (SiO 2 ), silicon nitride (SiN), silicon carbonitride (SiCN), silicon oxycarbide (SiOC), boron nitride (BN), silicon boron nitride (SiBN), yttrium oxide (Y 2 O 3 ), or zirconium oxide (ZrO 2 ). In an embodiment, the capping layer includes cobalt or ruthenium. In an embodiment, the capping layer is selectively deposited from a precursor including cyclopentadienylcobalt dicarbonyl, bis(cyclopentadienyl)cobalt(II) triruthenium dodecacarbonyl, bis(ethylcyclopentadienyl)ruthenium(II), or cyclopentadienyl ethyl (dicarbonyl) ruthenium. 
     In accordance with another embodiment, a method includes depositing an inhibitor material over and in contact with a first metal feature, the first metal feature being disposed in a first dielectric layer; depositing an etch-resistant layer over and in contact with the first dielectric layer; removing the inhibitor material; depositing a capping layer over and in contact with the first metal feature; and forming a second metal feature over and in contact with the capping layer. In an embodiment, the etch-resistant layer is deposited after depositing the inhibitor material. In an embodiment, the inhibitor material is removed after depositing the etch-resistant layer. In an embodiment, the capping layer is deposited after depositing the etch-resistant layer and removing the inhibitor material. In an embodiment, the capping layer includes cobalt or ruthenium. In an embodiment, he method further includes depositing an etch stop layer over the capping layer and the etch-resistant layer; depositing a second dielectric layer over the etch stop layer; and etching the second dielectric layer and the etch stop layer to form an opening exposing the capping layer, the second metal feature being formed in the opening. In an embodiment, the inhibitor material, the etch-resistant layer, and the capping layer are deposited by selective deposition processes. 
     In accordance with yet another embodiment, a method includes providing a first conductive feature in a first dielectric layer; selectively depositing an etch-resistant layer over the first dielectric layer, a sidewall of the etch-resistant layer being coterminous with a sidewall of the first dielectric layer; after selectively depositing the etch-resistant layer, selectively depositing a capping layer over the first conductive feature adjacent the etch-resistant layer, a sidewall of the capping layer being coterminous with a sidewall of the first conductive feature; and forming a second conductive feature over the capping layer, the etch-resistant layer separating the second conductive feature from the first dielectric layer. In an embodiment, the first conductive feature and the first dielectric layer are provided over a substrate, and a distance between a top surface of the first conductive feature and the substrate is different from a distance between a top surface of the first dielectric layer and the substrate. In an embodiment, the capping layer is selectively deposited with a top surface level with a top surface of the etch-resistant layer. In an embodiment, the capping layer is selectively deposited with a top surface level with a top surface of the first dielectric layer. In an embodiment, the method further includes depositing an etch stop layer over the etch-resistant layer and the capping layer, the etch stop layer extending along a top surface of the capping layer, a top surface of the etch-resistant layer, and side surfaces of the etch-resistant layer. In an embodiment, the method further includes depositing a second dielectric layer over the etch stop layer; and etching the second dielectric layer and the etch stop layer to form an opening exposing the capping layer, the second conductive feature being formed in the opening. 
     The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.