Patent Publication Number: US-6983398-B2

Title: Testing processors

Description:
FIELD OF THE INVENTION 
     The present invention relates generally to processors and, more specifically, to testing such processors. 
     BACKGROUND OF THE INVENTION 
     Testing electronic devices usually requires automatic test equipment (ATE) that provides data to stimulate the device inputs and compares the test results against expected data. Generally, the tester provides appropriate test signals and controls the test operations. For example, in testing a memory device, the tester, via the input/output (I/O) pins of the memory device, writes various sets of data into the memory, and reads the data from the memory. If the data read from the memory is the same as the data written into the memory, then the memory is good, i.e., functions properly. In this example, the tester provides appropriate signals to put the memory in the write or read mode as desired. The tester also compares the data read from the memory to the expected data usually provided by a test engineer since the test engineer usually provides the data written into the memory. 
     However, a tester for testing complex devices such as processors, especially at high-speed, are expensive, and can cost millions of dollars. Low-speed testers are less expensive, but require longer test time. A built-in self-test (BIST) mechanism enables a device to test itself, but usually requires circuits including a self-test controller that add significant complexity to the device and also use resources that can otherwise be used for other purposes. Testing packaged devices is easier to handle than testing the device at the wafer level, e.g., pre-packaged, but can be expensive because of the packaging costs. For example, if the device is bad, then the device package is wasteful. Testing at the wafer level commonly requires a clean and controlled environment. Depending on how the tests are developed, a particular test may detect a design flaw, a manufacturing defect, an operation defect, etc. High-coverage testing can also be expensive. However, leaving a defect to be found when the products have been shipped to customers usually increases the cost significantly, and may result in losing customers. Recently, multiprocessors are commonly found on a chip, and they need to be tested efficiently in a relatively less expensive manner. 
     Based on the foregoing, it is desirable that mechanisms be provided to solve the above deficiencies and related problems. 
     SUMMARY OF THE INVENTION 
     The present invention, in various embodiments, provides techniques for testing devices. In one embodiment, the device under test is a chip including a plurality of processors and a memory structure that stores test programs. One or more processors execute the test programs and generate test results based on which the chip may be determined good or bad. In one embodiment, the processors execute the test programs independent of each other, and no external hardware and/or test controller is required during the test phase. Various embodiments include a first processor that controls the scan chain of a second processor; a first processor that provides test results that are used as inputs for further testing a second processor, etc. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The present invention is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings in which like reference numerals refer to similar elements and in which: 
         FIG. 1  shows a device upon which embodiments of the invention may be implemented; 
         FIG. 2A  shows a memory structure of the device in  FIG. 1 ; 
         FIG. 2B  shows a diagram used to illustrate first scan tests in accordance with one embodiment; 
         FIG. 2C  shows a diagram used to illustrate second scan tests in accordance with one embodiment; 
         FIG. 2D  shows a diagram used to illustrate scan tests of a combinational logic; 
         FIG. 2E  is used to illustrate how a register is converted to a scan register in accordance with one embodiment; and 
         FIG. 3  is a flowchart illustrating the steps in testing the device in  FIG. 1 . 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be apparent to one skilled in the art that the invention may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form in order to avoid obscuring the invention. 
       FIG. 1  shows a chip  100  upon which embodiments of the invention may be implemented. Chip  100  includes a plurality of processors or central processing units (CPUs)  110 - 1 ,  110 - 2 , . . . ,  110 -N, a memory structure  120 , and various input/output (I/O) pins  130 - 1 ,  130 - 2 , . . . ,  130 -M. Processors  110  communicate with memory structure  120  via bus  1100 . I/O pins  130  are connected to processors  110 , memory structure  120 , and bus  1100  in various ways. However, to avoid obscuring the drawing, the connections are not shown. 
     The I/O Pins 
     I/O pins  130  are any mechanism that allows chip  100  to communicate with elements outside of chip  100 , such as test equipment, probing stations, test data analyzers, etc. In various embodiments, test programs are transferred from, e.g., automated test equipment (ATE) through I/O pins  130  to memory structure  120 . Similarly, test results provided by processors  110  inside chip  100  may be sent through pins  130  to be analyzed outside chip  100 . Various embodiments include one or a combination that, as processors  110  execute the test programs, no I/O pin is exercised; during the test execution, additional test instructions and data are transferred via pins  130  to memory structure  120 ; as the test results are available, they are transferred outside chip  100  to be analyzed “off line” and/or in parallel with the test program executions. Pins  130  may use methods of communications such as conduction, radiation, convection, etc. For example, conduction may use the metal interconnects; radiation may use optical or wireless transceivers; convection may use detectable drafts of hot fluid, etc. 
     The Processors 
     Processors  110  are commonly found in computers and may be referred to as the brain of the computers. Generally, processors  110  execute instructions stored in memory structure  120 , control logic, process information, perform arithmetic and logical operations, etc. A processor  110  may be the same or different in many ways such as structures, functions, or methods of operation. Two processors  110  may have one or a combination of differences including, for example, different architectures, cache sizes, functional units, error correction capabilities, instruction sets, instruction issue capabilities, clock speeds, power consumption characteristics, operating voltages, word lengths, execution reordering capabilities, testing capabilities, circuit technologies, circuit layouts, etc. Normally, instruction issue capabilities refer to the number of instructions that can be issued for execution within a cycle; word length refers to the number of bits of data used as an input for most arithmetic operations; and execution reordering capabilities refer to the ability to conduct sequential work in parallel or non-sequential order. 
     One or a set of various processors  110  tests one or a set of processors  110 . One processor  110  may perform some tests while a processor  110  compares and analyzes the test results. Consequently, testing chip  100  may be referred to as “self-test” because chip  100  conducts tests using its own elements. Additionally, each processor  110  runs at its own clock frequency, which is usually much higher than that of the test equipment. For example, a tester can normally run at 1–10 MHz while processors  110  can run at the hundreds of Megahertz or Gigahertz ranges. Since test time is short, more tests may be implemented. In one embodiment, chip  100  is tested before being packaged, and thus reduces packaging costs via the elimination of defective chips prior to packaging. In an alternative embodiment, only a portion of the tests conducted on chip  100  uses the present invention. This reduces or supplements additional testing that does not utilize the invention. 
     A processor  110  may include configurable circuits such as field-programmable gate arrays (FPGAs), programmable logic devices (PLDs), programmable logic array (PLAs), generic array logics (GALs) and/or similar technologies. For example, FPGA cells are configured or programmed to perform the functions of a processor  110 . 
     The Memory Structure 
     Memory structure  120  is computer memory or storage area arranged in different ways accessible to processors  110 . Memory structure  120  commonly includes main memory and/or different various levels of caches. Generally, main memory stores instructions to be executed by processors  110 , and may be referred to as physical memory, random-access memory (RAM), dynamic random-access memory (DRAM), read-only memory (ROM), etc. Information in memory  120  is obtained from outside of chip  100  via pins  130 , is generated by processors  110  as part of the instructions that are executed by processors  110 , is loaded or generated from other circuits on chip such as built-in self-test (BIST) circuits, or is designed to already contain the information, e.g., in ROMs. 
     Cache is a high-speed storage mechanism for quickly providing information to processors  110 . In general, a cache stores commonly-used instructions or data, and thus saves times in fetching the data from main memory or other storage areas. A cache structure may include instruction caches for caching instructions, data caches for caching data, or general caches for caching both instructions and data. A cache may be individual, and thus private, to a processor  110 , or may be shared among the several processors  110 . A cache structure may include several levels, e.g., a first level, a second level, a third level, etc., wherein a lower level cache is commonly faster and/or is closer to processors  110  than a higher level cache. 
     Various embodiments of memory structure  120  include random-access memory (RAM), read-only memory (ROM), ROM shadowing, etc. In one embodiment, via ROM shadowing techniques and when appropriate, e.g., at system startup or when the test programs are first invoked, the test programs are copied from the slower ROM chips into faster memory or cache so that any access to the program code originally in the ROM will be faster. This is because, after the code has been copied to the faster memory, accessing the code accesses the faster memory, instead of the slower ROM. Techniques of the invention are not limited to a specific arrangement of cache or memory in memory structure  120 , but are applicable to various arrangements including one or a combination of main memory, private, shared, and different levels and types of caches, etc. 
     The Test Programs 
     In one embodiment, memory structure  120  stores test programs to test various elements and/or different portions of chip  100 . Exemplary elements of processors  110  to be tested include the arithmetic logic unit for mathematical calculations such as adding, subtracting, multiplying, etc., the control unit for decoding and executing instructions, the instruction fetch unit, the branch prediction units, the instruction queues, the floating point unit, etc. Exemplary elements of chip  100  to be tested include processors  110 , memory structure  120 , bus  1110  including data bus and instruction bus for processors  110  to communicate with each other and/or with memory structure  120 , power control/reduction circuitry and logic, clock generation circuitry, etc. When all elements and portions of chip  100  are tested, the whole chip  100  is tested. In one embodiment, a test program includes instructions and data to stimulate functional elements of processors  110  and of chip  100 . For example, if an adder is tested, then various values are provided to the inputs of the adder, which is then allowed to perform the adding function. If the result is as expected, i.e., it is the sum of the input values, then the adder is good. If bus structure  1110  is tested, then some data is provided to bus  1110  and the data should remain the same throughout bus  1110 , etc. If memory structure  120  is tested, then the data written into the memory and the data read from the memory should be the same, etc. 
     In one embodiment, a processor  110  corresponds to a test program, and each test program performs the same tests except for the locations for storing the test results for each processor. For example, processor  110 - 1 , processor  110 - 2 , . . . , processor  110 -N, etc., correspond to test programs  150 - 1 ,  150 - 2 , . . .  150 -N, respectively, which are shown in  FIG. 2A . Each test program in turns corresponds to a memory location, e.g., locations  1000 ,  2000 ,  3000 , etc. When appropriate, a processor  110  executes its corresponding test program, e.g., processor  110 - 1  executes test program  150 - 1 , processor  110 - 2  executes test program  150 - 2 , processor  110 - 3  executes test program  150 - 3 , etc. In one embodiment, a processor  110  also corresponds to a program counter pointing to the memory location storing the test program corresponding to the processor. At reset or when the test starts, a processor  110  starts its program pointed to by its corresponding program counter. Alternatively, each processor  110  is assigned a priority corresponding to a memory location or address. Processors  110  then execute the programs based on that priority. For example, three processors, e.g., processor  110 - 1 , processor  110 - 2 , and processor  110 - 3  are assigned priority one, priority two, and priority three, respectively. Processor  110 - 1 , processor  110 - 2 , and processor  110 - 3  then run the test programs for priority one, priority two, and priority three at, e.g., address  5000 ,  6000 , and  7000 , respectively. In one embodiment, the addresses for the lower priorities, e.g., priority two and priority three, are calculated based on the address of priority one. In the above example, for each priority, each  1000  is added to the address  5000 . In one embodiment, an arbitration unit assigns the priority for each processor  110  that visits the arbitration unit. For example, the arbitration unit assigns priority one to the first processor visiting the arbitration unit, assigns priority two to the second processor visiting the arbitration unit, assigns priority three to the third processor, etc. The arbitration unit then either communicates these priorities to the appropriate processors  110  or uses these priorities to determine the corresponding values for the program counters, and these values are communicated to the appropriate processors  110  for them to invoke the corresponding test programs. In assigning the priorities, the arbitration unit uses one of the various ways including, for example, increasing or decreasing a later-assigned priority from a prior-assigned priority. The arbitration unit can be at any convenient location such as coupling to bus  1110 . 
     In one embodiment, processors  110  use a dynamic synchronization technique to get the priorities in which a processor  110  communicates with another processor  110  to dynamically determine its priority. In one embodiment, the priority value is stored in a location, e.g., location  140  of memory structure  120 . For illustration purposes, this value is referred to as V 1 . Processors  110  that seek to acquire a priority conduct the following algorithm. Each processor  110  acquires value V 1  in location  140  and provides a new value, e.g., value V 2 , to replace value V 1 . At the time of attempting to store value V 2  to location  140 , if a processor, e.g., processor  110 - 1 , determines that from the time it acquired value V 1  to the time it is attempting to write location  140 , location  140  has not experienced a store, then value V 2  is stored in location  140 . The processor that successfully wrote V 2  into location  140 , e.g., processor  110 - 1 , in on embodiment, sets a flag associated with location  140  to indicate that a store has occurred to location  140 . This processor  110 - 1  then uses value V 1  to determine its priority. However, if from the time a processor, e.g., processor  110 - 1 , acquired value V 1  to the time it attempts to write value V 2  into location  140 , location  140  has experienced a store, then that processor  110 - 1 &#39;s write attempt is prevented, and that processor  110 - 1  starts the process of acquiring the value for determining its priority again. A processor  110  acquires value V 2  by various ways, including, for example, increasing or decreasing value V 1 , generating value V 2  using V 1  as an input in a mathematical calculation such as a modulus function, etc. The invention is not limited to how value V 2  is obtained from value V 1 . 
     In one embodiment, each processor  110  receives the priority or initial program counter value during its manufacturing process in which the priority and/or the program counter value is placed in firmware or hard coded to each processor  110 . 
     In one embodiment, a processor  110  executes its corresponding test program independent of other processors. Each processor  110  starts and/or stops its program any time, at irregular intervals, and/or without other processors knowing about it, as long as the test results are available to be analyzed when analyzing the test results starts. The processors&#39; system clocks do not have to be cycle locked, e.g., one clock does not depend on another clock, etc. For example, a processor  110 - 1  may run its program in series or in parallel with a processor  110 - 2 ; processor  110 - 1  may stat at time t 1  and stop at time t 2  while processor  110 - 2  starts at time t 3  and stops at time t 4  wherein times t 1 , t 2 , t 3 , and t 4  are different and independent of one another, etc. However, t 1  is less than or equal to t 2 . Similarly, t 3  is less than or equal to t 4 . Since, in one embodiment, each processor  110  corresponds to a test program and each test program can provide different tests, one processor  110  can run different tests from another processor  110  or analyze test results provided by other processors  110 . For example, a processor  110 - 1  is testing a floating-point unit for a processor  110 - 2 , while a processor  110 - 3  is testing an integer unit for a processor  110 - 4 , and processor  110 - 5  compares the test results provided by processors  110 - 2  and  110 - 3 , etc. In one embodiment, once a processor  110  finishes its test program, that processor sets a flag at a corresponding memory location so that other processors can take appropriate actions. For example, once each processor  110 - 1  and  110 - 2  finishes testing processor  110 - 3 , each processor  110 - 1  and  110 - 2  sets a flag corresponding to the programs that each has executed. Processor  110 - 4 , recognizing the flags of processors  110 - 1  and  110 - 2  have been set, starts running its program to analyze the test results provided by these processors  110 - 1  and  110 - 2 . In an alternative embodiment, a processor  110  sets a flag when some portions of the test programs were executed so that the completed test results may be analyzed while additional tests are being executed. 
     In one embodiment, processors  110  share the same test program, but each processor  110 , when executing the test program, provides its identification including its identity and/or priority. The test program uses this identity to recognize the processor  110  executing the test program so that each processor  110  can write into its corresponding memory location within memory structure  120  and/or can execute its program differently from the other processors  110 . In one embodiment, each processor  110  is given an identity during the manufacturing process. 
     In one embodiment, the test results of a test program are used as inputs for the test program of another processor. For example, processor  110 - 1 , via its program, multiplies by three the values in a range of memory locations, e.g., locations  1 , 000  to  1 , 999 , and stores the multiplication results in locations  10 , 000  to  10 , 999 . Processor  110 - 2 , executing its corresponding program, divides the values in these locations by 3 and stores them in locations  11 , 000  to  11 , 999 . Processor  110 - 3 , also executing its program, compares the values in locations  1 , 000  to  1 , 999  to those in locations  11 , 000  to  11 , 999 , etc. 
     Test programs are loaded into memory structure  120  in various ways, including, for example, using one or a combination of probe-test inputs, joint test action group (JTAG) inputs, input/output (I/O) ports, etc. In one embodiment, automatic test equipment (ATE) connected via pins  130  to chip  100 , transfers the test programs to memory structure  120 . In an alternative embodiment, the test programs are stored in the read-only memory (ROM) of memory structure  120 . 
     Test programs are initiated in various ways including, for example, initiating via resetting a “test” pin to a logic low or high, initiating the test mode after power up or after executing some instructions in boot-up programs, etc. After the test mode is invoked, each processor  110  starts its corresponding test program, and the test programs control the tests, e.g., control how each test tests some portions of chip  100  or of processor  110 . Alternatively, programs may be written to configure processors  110  to initiate the tests, execute the test programs, perform other functions, etc. Test programs are written in such a way that they cover desirable tests optionally including testing the whole chip  100 . 
     In one embodiment, while executing their test programs, processors  110  create additional tests, which supplement or enhance the current test program or create new test programs. In one embodiment, test programs are created when some conditions are met. For example, if a particular variable in a first test program has a value 1, then a test for a multiplication unit is created as part of the current test program or of a second test program. However, if the value is a 2, then a test for a division unit is created for a third and/or a fourth test program, etc. The newly-created test programs are stored in the corresponding memory locations to be executed by the corresponding processors. For example, if processor  110 - 2  is to test the multiplication unit while processor  110 - 3  is to test the division unit, then the second and the third test programs in the above example are stored in the memory locations corresponding to processors  110 - 2  and  110 - 3 , respectively. 
     In one embodiment, test programs are fed from outside chip  100  via pins  130  while other test programs are being executed. For example, while executing the first test program at location  1 , 000  to  1 , 999 , the test data and/or test instructions are being loaded to locations  10 , 000  to  10 , 999  for the second test program. Any processor  110  may execute the second test program based on the corresponding priority and/or the address of the test programs as discussed above. A processor  110 , before executing a test program, determines whether that test program is fully loaded, and, if so, executes that test program. In one embodiment, when each test program is fully loaded and thus ready to be executed, a corresponding flag in a memory location is set. 
     In the above discussion, the addresses of memory structure  120  are used as examples. The addresses in one example are independent of the addresses of other examples. 
     Programs, test programs and/or instructions executed by processors  110  may be stored in and/or carried through one or more computer-readable media, which refer to any medium from which a computer reads information. Computer-readable media may be, for example, a floppy disk, a hard disk, a zip-drive cartridge, a magnetic tape, or any other magnetic medium, a CD-ROM, a CD-RAM, a DVD-ROM, a DVD-RAM, or any other optical medium, paper-tape, punch-cards, or any other physical medium having patterns of holes, a RAM, a ROM, an EPROM, or any other memorychip or cartridge. Computer-readable media may also be coaxial cables, copper wire, fiber optics, acoustic or electromagnetic waves, capacitive or inductive coupling, etc. 
     The Test Results 
     Memory structure  120  also stores test results, which are the responses after processors  110  execute their test programs. For example, if a value one and a value two are provided to a two-input adder, and if the adder functions properly, then the response would be three, which is the result of adding one and two. If the adder functions improperly, then the result or the response could be any number. In one embodiment, a distinct section of memory structure  120  stores a set of test results for a processor  110 . For example, sections  160 - 1 ,  160 - 2 , . . .  160 -N in  FIG. 2A  store the test results for processors  110 - 1 ,  110 - 2 , . . . ,  110 -N, respectively. Each section  160  also corresponds to a memory location, e.g., locations  50000 ,  51000 ,  52000 , etc. 
     In one embodiment, test results are in the form of signatures that give hints as to whether a particular operation or a tested unit is bad. For example, if an operation multiplies an integer by three and adds all digits of the multiplication results, then the final result for the operation should be 0, 3, 6, or 9. The value 0, 3, 6, or 9 is the signature for the operation. In one embodiment, the test analysis uses the test signatures to determine whether the chip is good or bad. In the above example, if, for example, the operation produces a number 8, then the operation is bad because a correct operation would provide a number 0, 3, 6, or 9. In one embodiment, it is not necessary to determine whether the adding or multiplying operation and/or the corresponding unit is bad. If a unit is bad, then the whole chip  100  is bad. Various embodiments exist in which the tests provide signatures such that analyzing a test signature can give hints to whether a particular portion or element of chip  100 , e.g., a floating point, an ALU, a processor, etc., is bad. For example, summing all digits of a number multiplied by 9 provides a signature of 0 or 9. Similarly, summing the digits of a number multiplied by 3 provides a signature of 0, 3, 6, or 9. Further, multiplying a number by 9 and dividing the result of the multiplication by 3 provides the net effect of multiplying the same number by 3. Analyzing the signature of the multiplication and division provides hints as to whether the multiplication or the division unit is bad. For example, if a test analysis provides that the signature for the multiplication is good, e.g., a 0 or 9, while the signature for the division is bad, e.g., other than 0, 3, 6, or 9, then, the multiplication unit is good while the division unit is bad. In one embodiment, the test signature is provided via one or more pins  130  to be analyzed outside of chip  100 . 
     In one embodiment, one processor  110  analyzes the test results provided by all processors  110 . Alternatively, more than one processor  110  analyzes the test results. The more processors analyzing the test results, the higher the level of confidence that exists for the test results. For example, two processors  110  providing the same two sets of test analyses indicates that the test results are more probable to be accurate than just one processor  110  providing one set of test analyses. In one embodiment, two processors  110  perform the same test, and if the test results are the same for both processors  110 , then the test results show evidence towards a good chip  100 . However, if the test results are different, then the chip  100  is considered bad. 
     Test results can be used for detecting various types of defects, including, for example, manufacturing defects, design defects, operation defects, etc. 
     Test results can be on-chip or off-chip  100 . In one embodiment, a flag in the form of a bit is used to indicate whether chip  100  is good or bad. Alternatively, the test results may identify which processor  110  or which unit, e.g., a floating point, an integer unit, etc., of a processor  110  is bad. 
     In one embodiment, chip  100  is tested at desired temperatures. Mechanisms to control the test temperature include, for example, controlling the temperature of the testing room, controlling the temperature of the plate carrying the chip  100  by spraying chemicals, e.g., gas, liquid, freon, etc., on chip  100 . The cooling system may include sensing equipment, feedback control, etc. 
     Chip  100  shown in  FIG. 1  is used as an example. Various configurations of chip  100  are within the scope of the invention. For example, each processor  110  is directly connected to its own cache and/or memory or a shared cache; each processor  110  may have the same or different architecture; various processors  110  may be in a cluster sharing the same bus and/or memory or cache, etc. In one embodiment, chip  100  is in the form of a semiconductor die and/or includes configurable circuits. 
     Scan Tests within the Chip 
       FIG. 2B  shows a diagram used to illustrate a first embodiment of a scan test of chip  100 . In  FIG. 2B , a first processor, e.g., processor  110 - 1 , scan tests or controls the scan test of a second processor, e.g., processor  110 - 2 . Further, chip  100  includes a controller  210  for a test access port (TAP, not shown), an instruction register  220 , and scan registers or scan cells  230 - 1  to  230 -L. In one embodiment, the TAP accommodates scan pins including test clock (TCK), test mode select (TMS), and test reset (TRST). Additionally, the scan components  210 ,  220 , and  230 , etc., and thus the scan tests of processor  110 - 2  are in compliance with the IEEE 1149.1 standard. TAP controller  210  is a state machine and is programmed by the TMS and TCK inputs. TAP controller  210  controls the flow of data to instruction register  220  and data registers  230 . Instruction register  220  decodes the instructions to be performed by scan registers  230 , and selects scan registers  230  to be accessed. The TCK input provides the clock for the test logic and allows the serial test data path from TDI to TDO to be used independently of the system clock, e.g., the clock of processors  110  or of chip  100 . The TMS input, in conjunction with the TCK input, changes the states in TAP controller  210 , and also allows movement of data and TAP instructions. The TDI input provides serial inputs including both test instructions and test data. TDO is the serial output for test instructions and data from scan registers  230 . A clock provided at the TCK input shifts the data in the chain between TDI input and TDO output. The TRST input provides asynchronous initialization of TAP controller  210 , which in turns causes asynchronous initialization of other test logic. TRST, at reset, places processor  110 - 2  in the normal operating mode and inactivates scan registers  230 . 
     Scan registers  230  include elements of chip  100  and of processors  110  to be tested. These elements include, for example, registers in memory  120 , registers in the arbitration unit, registers in processors  110 , etc. Registers in memory  120  include registers in the memory controller, etc. Registers of processors  110  includes registers in the CPU, the arithmetic unit, the load/store unit, the instruction decode unit, etc. Registers  230  can be in one or more processors  110 . For example, the scan chain goes through registers  230  in processor  110 - 2 , then processor  110 - 3 , then processor  110 - 4 , etc. However, for illustration purposes,  FIG. 2B  shows that registers  230  are in only processor  110 - 2 . Observing and controlling the values held by registers  230  conduct the scan test. Scan registers  230  allow the test control via the scan pins, e.g., TDI, TCK, TMS, etc., to select whether registers  230  output the value the tested elements regularly hold or output the value provided from the scan path. 
     Processor  110 - 1  includes two registers  260  and  270 . Processor  110 - 1  can write values into register  260  and read values from register  270 . Register  260  includes bit — TDI, bit — TCK, bit — TMS, and bit — TRST each of which corresponds to each signal TDI, TCK, TMS, and TRST, respectively. Effectively, controlling register  260  via its bits controls the corresponding scan signals and thus the scan test of processor  110 - 2 . For example, each of bit — TMS, bit — TRST, and bit — TDI can be set to desirable values while bit — TCK is pulsed as a clock. In one embodiment, register  260  changes voltage values for bit — TCK in a monotonic way. Register  260  also includes bit — SLCT, which controls the selection of the inputs and outputs of multiplexers and de-multiplexer  2050 ,  2150 ,  2250 ,  2350 , and  2450 . Generally, when processor  110 - 1  controls the scan test of processor  110 - 2 , bit — SLCT is set so that bit — TDI, bit — TCK, bit — TMS, bit — TRST, and bit — TDO are connected to lines  2055 ,  2155 ,  2255 ,  2355 , and  2455 , respectively. 
     Register  270  includes bit — TDO, which corresponds to TDO. Reading values from register  270  allows observations of the scan chain data. In one embodiment, the value of bit — TDO is written into bit — TDI to recycle scan chain data. Alternatively, new data is written into bit — TDI to modify scan chain data, e.g., for scan chain testing. Two registers  260  and  270  are used as examples; one or more registers performing the same function of these two registers are sufficient. 
     Multiplexers  2050 ,  2150 ,  2250 ,  2350 , and de-multiplexer  2450  connect the appropriate inputs and outputs of the multiplexers and de-multiplexer. For example, multiplexer  2050  selects either TDI or bit — TDI to be output on line  2055 . Multiplexer  2150  selects either TCK or bit — TCK to be output on line  2155 . Multiplexer  2250  selects either TMS or bit — TMS to be output on line  2255 , etc. Multiplexers and de-multiplexer are used as examples, any mechanism connecting the appropriate inputs and outputs is effective. 
       FIG. 2C  shows a diagram used to illustrate a second embodiment of a scan test of chip  100 . In  FIG. 2C , a first processor, e.g., processor  110 - 1 , scan tests or controls the scan test of a second processor, e.g., processor  110 - 2 . Further, chip  100  includes scan registers or scan cells  330 - 1  to  330 -Q. In one embodiment, the scan test accommodates scan pins including a system clock (CPU 2   — CLK), scan clock A (SCAN — CLKA), and scan clock B (SCAN — CLKB). Additionally, the scan registers  330  and thus the scan tests of processor  110 - 2  are generally in compliance with the level sensitive scan design (LSSD) methodology. The PROC 2   — CLK is the clock for processor  110 - 2  for regular operation. SCAN — CLKA and SCAN — CLKB provide the clocks for the test logic and allow the serial test data path from SCAN — IN to SCAN — OUT to be used independently of PROC 2   — CLK. The SCAN — IN input provides serial inputs including both test instructions and test data. SCAN — OUT is the serial output for test instructions and data from scan registers  330 . SCAN — CLKA and SCAN — CLKB, which are two-phase, non overlapping shift clocks, shift the data in the chain between SCAN — IN input and SCAN — OUT output. 
     Scan registers  330  include elements of chip  100  and of processors  110  to be tested. These elements include, for example, registers in memory  120 , registers in the arbitration unit, registers in processors  110 , etc. Registers in memory  120  include registers in the memory controller, etc. Registers of processors  110  includes registers in the CPU, the arithmetic unit, the load/store unit, the instruction decode unit, etc. Registers  330  can be in one or more processors  110 . For example, the scan chain goes through registers  330  in processor  110 - 2 , then processor  110 - 3 , then processor  110 - 4 , etc. However, for illustration purposes,  FIG. 2C  shows that registers  330  are in only processor  110 - 2 . Observing and controlling the values held by registers  330  conduct the scan test. Scan registers  330  allow the test control via the scan pins, e.g., SCAN — CLKA, SCAN — CLKB, PROC 2   — CLK, etc., to select whether registers  330  output the value the tested elements regularly hold or output the value provided from the scan path. 
     Processor  110 - 1  includes two registers  360  and  370 . Processor  110 - 1  can write values into register  360  and read values from register  370 . Register  360  includes bit — SCAN — IN, bit — PROC 2   — CLK, bit — SCAN — CLKB, and bit — SCAN — CLKA each of which corresponds to each signal SCAN — IN, PROC 2   — CLK, SCAN — CLKB, and SCAN — CLKA, respectively. Effectively, controlling register  360  via its bits controls the corresponding scan signals and thus the scan test of processor  110 - 2 . For example, bit — SCAN — IN can be set to desirable values while bit — SCAN — CLKA, bit — SCAN — CLKB, and bit — PROC 2   — CLK are pulsed as clocks. In one embodiment, register  360  changes voltage values for bit — SCAN — CLKA, bit — SCAN — CLKB, and bit — PROC 2   — CLK in a monotonic way. Register  360  also includes bit — SLCT 2 , which controls the selection of the inputs and outputs of multiplexers and de-multiplexer  3050 ,  3150 ,  3250 ,  3350 , and  3450 . Generally, when processor  110 - 1  controls the scan test of processor  110 - 2 , bit — SLCT 2  is set so that bit — SCAN — IN, bit — PROC 2   — CLK, bit — SCAN — CLKB, bit — SCAN — CLKA, and bit — SCAN — OUT are connected to lines  3055 ,  3155 ,  3255 ,  3355 , and  3455 , respectively. 
     Register  370  includes bit — SCAN — OUT, which corresponds to SCAN — OUT. Reading values from register  370  allows observations of the scan chain data. In one embodiment, the value of bit — SCAN — OUT is written into bit — SCAN — IN to recycle scan chain data. Alternatively, new data is written into bit — SCAN — IN to modify scan chain data, e.g., for scan chain testing. Two registers  360  and  370  are used as examples; one or more registers performing the same function of these two registers are sufficient. 
     Multiplexers  3050 ,  3150 ,  3250 ,  3350 , and de-multiplexer  3450  connect the appropriate inputs and outputs of the multiplexers and de-multiplexer. For example, multiplexer  3050  selects either SCAN — IN or bit — SCAN — IN to be output on line  3055 . Multiplexer  3150  selects either PROC 2   — CLK or bit — PROC 2   — CLK to be output on line  3155 . Multiplexer  3250  selects either SCAN — CLKB or bit — SCAN — CLKB to be output on line  3255 , etc. Multiplexers and de-multiplexer are used as examples, any mechanism connecting the appropriate inputs and outputs is effective. 
       FIG. 2D  shows a diagram used to illustrate how a combinational logic in processor  110 - 2  is tested using the scan techniques described in  FIGS. 2B and 2C . For illustration purposes, the LSSD in  FIG. 2C  is used. Further, combinational logic  440  accepts inputs from two registers  430 - 1  and  430 - 2 , and places its output in register  430 - 3 . However, logic  440  may have zero, one, or multiple inputs and/or zero, one, or multiple outputs. Combinational logic  440  is part of the regular processing circuitry of processor  110 - 2 , but was not shown in  FIGS. 2B and 2C . To test logic  440 , registers  430 - 1 ,  430 - 2 ,  430 - 3  are replaced with LSSD registers  330 - 1 ,  330 - 2 , and  330 - 3 , respectively. These LSSD registers are connected to appropriate scan test signals SCAN — CLKA, SCAN — CLKB, PROC 2   — CLK, etc., in a scan chain as in  FIG. 2C . Controlling the values in registers  330 - 1  and  330 - 2  effectively controls the inputs to combinational logic  440 , while observing the value in register  330 - 3  allows observing the output of combinational logic  440 . 
       FIG. 2E  shows a register  430  being transformed into a register  330 , in accordance with one embodiment using the LSSD. Register  430  includes a clock CLK, an input DATA — IN, and an output DATA — OUT. Register  330  includes register  430 A and a “shift” register  435 . Register  430 A is similar to register  430 , but register  430 A includes an additional clock SCAN — CHAIN — CLKA and an input SCAN — CHAIN — IN. Register  435  includes a clock SCAN — CHAIN — CLKB, an input that is fed from output DATA — OUT, and an output SCAN — CHAIN — OUT. During regular operations when scan testing is not being conducted, input DATA — IN and output DATA — OUT are the normal input and output of register  430 . Lines SCAN — CHAIN — IN, SCAN — CHAIN — CLKA, SCAN — CHAIN — CLKB, and SCAN — CHAIN — OUT form the shift portion of register  330 . SCAN — CHAIN — IN is the shift data in and SCAN — CHAIN — OUT is the shift data out. SCAN — CHAIN — CLKA and SCAN — CHAIN — CLKB are the two-phase, non-overlapping shift clocks. Those skilled in the art will recognize that, for exemplary scan register  330 - 1 , SCAN — CHAIN — CLKA corresponds to line  3355 , SCAN — CHAIN — CLKB corresponds to line  3255 , CLK corresponds to line  3155 , SCAN — CHAIN — IN corresponds to line  3055 , and SCAN — CHAIN — OUT corresponds to line  3325  in  FIG. 2C . 
     In the above examples, a processor that scan tests another processor is used for illustration purposes. Various ways for using processors to scan test processors or other portions of chip  100  are within the scope of the invention. For example, a processor  110  scan tests more than one processor  110 ; a first processor scan tests a second processor, and the second processor scan tests the first processor; a first processor scan tests a second processor, the second processor scan tests a third processor, which may or may not scan test the first processor, etc. 
     Although in the above examples the processor  110 - 1  uses the scan chain to affect and/or observe registers in processor  110 - 2 , other methods are within the scope of the invention. One embodiment does not use registers  260 ,  270 ,  360 , or  370 , but instead uses a bus to access the registers in processor  110 - 2  that are being observed or affected. 
     Techniques disclosed in this document, e.g., techniques in the section “THE TEST PROGRAMS,” “THE TEST RESULTS,” etc., can be used in combination with this section “SCAN TESTS WITHIN THE CHIP.” For example, the program for processor  110 - 1  to scan test processor  110 - 2  can be selected from one or a combination of being loaded from external ATE, being loaded from memory, ROM or firmware, being generated while tests are executed, etc. 
     Method Steps 
       FIG. 3  is a flowchart illustrating the steps in testing chip  100  in accordance with one embodiment. 
     In step  304 , if the test programs haven&#39;t been in memory structure  120 , they are loaded into memory structure  120 . 
     In step  308 , processors  110  are put in the test mode for each processor to execute its corresponding test program. 
     In step  312 , each processor  110  stores its set of test results in the appropriate locations in memory structure  120 . 
     In step  316 , one or various processors analyze the sets of test results. How the test results are analyzed depend on how the tests were performed. For example, if processor  110 - 1  and processor  110 - 2  run identical tests, then a processor  110  compares the test results provided by the two processors  110 - 1  and  110 - 2 . If the two sets of test results are the same, then that provides evidence that chip  100  may be good. However, if two sets of test results are different, then chip  100  is bad. In embodiments where it is not necessary to determine what causes chip  100  to be bad, no further analysis of the test results is performed. 
     In step  320 , the processor analyzing the test results provides the result of the analysis, which, in one embodiment, is stored in memory structure  120 . Alternatively, the test analysis result is provided via one or more pins  130  to outside of chip  100 . 
     In the foregoing specification, the invention has been described with reference to specific embodiments thereof. However, it will be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention. Accordingly, the specification and drawings are to be regarded as illustrative rather than as restrictive.