Patent Publication Number: US-7218164-B2

Title: Emitter switching driving network to control the storage time

Description:
PRIORITY CLAIM 
   This application claims priority from European patent application No. 04425237.7, filed Mar. 31, 2004, which is incorporated herein by reference. 
   FIELD OF APPLICATION 
   The present invention relates to an Emitter-Switching circuit driving network wherein the emitter-switching circuit comprises a pair of cascode-configured transistors, one of the bipolar type and one of the MOS type and the driving network is of the type comprising a driving circuit for respective conduction terminals of said pair of transistors. 
   PRIOR ART 
   As it is well known, an emitter-switching-configured circuit consists of the cascode connection of a bipolar transistor having a high breakdown voltage and of a P-MOS low voltage transistor. 
     FIG. 1  shows a known driving block  2  for an emitter-switching configuration  1 . 
   The emitter-switching block  1  is comprised between a coil L connected to a first supply voltage VCC and a second supply voltage, particularly a ground GND; the block is operated by means of two control terminals B and G connected to the bipolar and MOS transistors respectively. 
   The driving block  2  comprises a base resistance RB connected to a capacitor CB and to a zener diode DZ, being parallel-configured and directly connected in turn to the ground GND. 
   The driving block  2  is connected to a control terminal B of the bipolar transistor of the emitter-switching circuit  1  to be driven, as well as to the control terminal G of the MOS transistor of said emitter-switching circuit, by means of a resistance RG. 
   The capacitor CB serves to store energy during the bipolar transistor turn-off, in order to reuse it during the following turn-on and conduction of the transistor itself; the zener diode DZ serves to avoid that the voltage of the transistor control terminal B exceeds a predetermined value. 
   As already mentioned, the configuration of the driving circuit  2  of  FIG. 1  is already known, but what makes it particularly interesting today is the current availability of bipolar transistors having a safety area for reverse squared biasing (RBSOA) (in the emitter-switching configuration) with a current close to the peak current and a voltage corresponding to the breakdown voltage between the collector and the emitter, the base being short-circuited with the emitter, indicated with BV CES , as well as of P-MOS transistors having a very low equivalent resistance in conduction R DSON  and, thus, almost comparable with ideal switches. 
   The main advantages of the driving circuit  2  shown in  FIG. 1  are the very low voltage drop in conduction which is typical of bipolar transistors and the turn-off speed thereof. In fact, during the turn-off, the base current IB is equal to the collector current IC, and it is very high. This determines a drastic reduction both of the storage and of the fall time, allowing the circuit to operate even at a frequency of 150 kHz. 
   The described driving circuit  2  for the emitter-switching block  1  is very useful and effective in all those cases wherein the current IC on the bipolar transistor during the turn-on is null or very low with respect to the nominal one. 
   An embodiment of the driving circuit  2  of  FIG. 1  is represented by converter devices of the “Flyback” type operating at a frequency of 100 kHz and having a null turn-on current, since the converter operates discontinuously.  FIG. 2  shows waveforms related to this kind of converter. 
   Unfortunately, the driving being described, although very useful in the case being considered in the circuit of  FIG. 1 , cannot practically be used when operation occurs with bipolar transistor turn-on current values being non-null and at relatively high frequencies (&gt;60 kHz), since, having to deal with a bipolar device, the dynamic V CESAT  phenomenon is emphasised. 
   For this reason, with the driving circuit  2  of  FIG. 1 , an excessive power dissipation would occur on turning on the bipolar transistor due to the fact that the collector-emitter voltage would require a relatively long time (higher or equal to 2 μs) to reach the saturation value. Always referring to the circuit of  FIG. 1 , a base voltage increase of the bipolar transistor would only partially reduce the dynamic V CESAT  problem, but it would excessively worsen performances when turning off. 
   A possible known technical solution to this problem is the driving circuit  2   I  of  FIG. 43 , whose components and signals being already present in the driving circuit  2  of  FIG. 1  and having the same structure and operation will be given the same previously used references. 
   The circuit  2   I  is suitable for applications having a non-null collector current IC at the bipolar transistor turn-on. 
   This circuit differs from the circuit  2  because of the optimization block  3  comprising, unlike what is shown in circuit  2  of  FIG. 1 , a capacitor CB I  arranged in series-configuration with the Zener diode DZ. 
   In summary, it can be said that the driving circuit  21  of  FIG. 3  conveniently modulates the bipolar transistor base current IB, optimizing the turn-on and turn-off steps thereof and allowing the lowest V CESAT  value to be reached. 
   An embodiment of the driving circuit  2   I  of  FIG. 3  is represented by “forward”-configured converter devices operating, for example, at a frequency being higher or equal to 100 kHz and wherein a modulation of the bipolar transistor base current IB is performed;  FIG. 4  shows the waveforms obtained from this kind of converter. 
   Unfortunately, in the case of applications with non-null collector currents, in the transistor turn-on step, and meanwhile with a variable value in a wide range, the circuit shown in  FIG. 3  must be sized taking into consideration the most stressful operating condition, i.e. what is reached with the highest collector current. 
   An example of this kind of application is represented by power factor controller stages PFC representing a resistive load for an alternate current source, receiving at the input an alternate current and outputting a direct current being regulated to be used as an ordinary converter input. 
   A correct saturation level V CESAT  should be ensured to the highest current value, by conveniently selecting a new base voltage value, but in so doing, for low collector current values, the device would operate in over-saturation, obtaining extremely long storage times. This would involve an excessive turn-off dissipation, as well as inaccurate control due to the fact that the actual device turn-off would occur with delay with respect to the signal provided by the controller. 
   The just described problem has been already faced and proportional driving solutions have been provided. 
   A first solution is implemented by providing a base current being proportional to the collector current. In practice, by means of a network sensing the collector current, a base current being proportional to the collector current is provided, setting a predetermined ratio between said base and collector currents. 
   A second proportional driving solution is represented by the driving circuit  2   II  shown in  FIG. 5 , wherein the components and signals being already in the driving circuits  2  and  2   I  and having the same structure and operation will be given the same previously used references. 
   In this figure, the driving circuit  2   II  implements a proportional driving solution, unlike the two known solutions of the driving circuits  2  and  2   I , by inserting a current transformer T 1  with a first winding L 1  connected to the bipolar transistor collector and a second winding L 2  connected to the base B of said bipolar transistor. In this latter case the IC/IB ratio between the base and collector currents is simply set by the turn ratio. 
   The bipolar transistor base terminal B is connected, by means of a base resistance RB, to a capacitor CB and to a block  4 , being parallel-configured and directly connected in turn to the ground GND, as well as to the MOS transistor control terminal G, by means of a resistance RG. The block  4  comprises, unlike what is shown in circuits  2  and  2   I , a diode D 1  connected in series with the second winding L 2  of the current transformer T 1 . 
   The proportional driving is a realization technique which is certainly valid for obtaining a reduced variation of the storage time between a highest collector current condition and a lowest collector current condition. 
   Unfortunately, even a limited storage time variation could make the cascode configuration non-applicable to last generation applications. In fact, these applications are characterized by a high operation frequency, but also by a wide collector current variation; examples of applications operating under these conditions and wherein up to now it has been impossible to use a bipolar transistor, in the CASCODE configuration and not, are:
         PFC (Power Factor Controller);   Switching power suppliers operating at a higher frequency than 100 kHz with a wide load variation;   Generally all applications having a higher switching frequency than 100 kHz and with a highly variable load (induction heating, welding . . . )       

   The cascode configuration storage time, besides being a delay time between the moment the gate signal cancels out and when the device effectively turns off, also highlights the actual device saturation level. 
   As it is well known by using the cascode configuration in switching applications, ensuring the correct device saturation level means optimizing the device switching performances. 
   From the practice it is evident that setting a storage time within the range of 150˜500 ns, according to the kind of device, is the best compromise to ensure that the device reaches a good saturation level in conduction and a not excessively long voltage rise time when turning off, thus reducing switching power dissipations when turning off. The device physical behavior changes when the collector current varies, as it is well highlighted by the traditional typical curve of the current gain variation hfe as a function of the current IC for a bipolar transistor, shown in  FIG. 6 . 
   It is clear that carrying out a proportional driving, i.e. setting a ratio between the base and collector currents for each collector current value, is not sufficient to ensure a constant storage time in the whole collector current variation range. 
   An ideal driving, i.e. a driving being capable of setting a constant storage time for each current IC value, would thus be the one fixing an IC/IB ratio being variable as a function of the collector current and being capable of following the current gain variation hfe law. 
   This problem is apparently complex since, besides succeeding in implementing a driving circuit following an IC/IB ratio, between the collector current and the base current, being variable as a function of a no more linear first order mathematical relationship, as it happens instead for the proportional driving, it would require such a network to be regulated each time as a function of the device being selected for the applications to be realized. 
   It must also be observed that sometimes the hfe spread variation of the devices on sale, although of the same type and by the same builder, is relatively high. 
   The technical problem of the present invention is to provide a driving network allowing the storage time of an emitter-switching circuit to be set and kept constant for the whole collector current variation range, overcoming the limitations and/or drawbacks affecting the prior art. 
   SUMMARY OF THE INVENTION 
   An aspect of the present invention is to realize a driving network allowing the bipolar transistor control terminal to be biased, wherein the parameter being controlled is the storage time. 
   The features and advantages of the system according to aspects of the invention will be apparent from the following description of an embodiment thereof given by way of non-limiting example with reference to the attached drawings. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     In these drawings: 
       FIG. 1  schematically shows a traditional emitter-switching driving circuit with a null turn-on current according to the prior art. 
       FIG. 2  schematically shows the wave forms of a discontinuous flyback converter with a null turn-on current according to the prior art. 
       FIG. 3  schematically shows an optimised emitter-switching driving circuit for a null current turn-on, according to the prior art. 
       FIG. 4  schematically shows the wave forms of a forward converter obtained with the driving circuit of  FIG. 3 , according to the prior art. 
       FIG. 5  schematically shows a proportional emitter-switching driving circuit with a current transformer, according to the prior art. 
       FIG. 6  shows a diagram of the current gain variation of a bipolar transistor as a function of the collector current, according to the prior art. 
       FIG. 7  schematically shows an emitter-switching driving network according to a first embodiment of the present invention. 
       FIGS. 8   a ,  8   b  schematically show the wave forms of a first block in the driving network of  FIG. 7  according to an embodiment of the present invention. 
       FIG. 9   a  schematically shows a second embodiment of the first block of  FIG. 7 . 
       FIG. 9   b  schematically shows the wave forms of the block of  FIG. 9   a.    
       FIG. 10  schematically shows a second block in the driving network of  FIG. 7  according to an embodiment of the present invention. 
       FIG. 11  schematically shows the wave forms drawn from the diagram of  FIG. 10 . 
       FIG. 12  schematically shows the wave forms of a third block in the driving network of  FIG. 7 , according to an embodiment of the present invention. 
       FIG. 13  schematically shows an emitter-switching driving network, according to a second embodiment of the present invention. 
       FIG. 14  shows a circuit diagram implementing the invention used in the tests on PFC according to an embodiment of the present invention. 
       FIGS. 15 to 21  show the wave forms of signals drawn by the embodiment of  FIG. 14 . 
   

   DETAILED DESCRIPTION 
   The following discussion is presented to enable a person skilled in the art to make and use the invention. Various modifications to the embodiments will be readily apparent to those skilled in the art, and the generic principles herein may be applied to other embodiments and applications without departing from the spirit and scope of the present invention. Thus, the present invention is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed herein. 
   With reference to the drawings, and particularly to  FIG. 7 , a first embodiment of a driving network  20  will now be described. 
   In  FIG. 7 , components and signals being already in prior art descriptions and having the same structure and operation will be marked with the same previously used labels. 
   The network  20  is intended to bias a bipolar transistor control terminal B of an emitter-switching block  1 . 
   A control voltage VB is provided to the bipolar transistor control terminal B output from a driving block  21  comprising a resistance RB comprised in turn between the control terminal B and a first circuit node N 1 , a first capacitor C 2  interposed between the first circuit node N 1  and the ground GND and a diode D 2 , allowing the current to flow only towards the bipolar transistor to be driven, interposed between said first circuit node N 1  and a second circuit node N 2  outside the block  21 . 
   The control terminal B and the first circuit node N 1 , of the driving block  21 , are the terminals of the resistance RB and they are connected to a first comparator block Hi of a negative feedback network NET-neg of the driving network  20 , getting two respective voltage values V 1  and V 2 . 
   The negative feedback network NET_neg of the driving network  20  also comprises a filtering block H 2 , an amplification block H 3 , a second comparator block H 4  and an output block Hout 1 . 
   The first comparator block H 1  comprises a differential amplifier  23  receiving at the input the two voltage values V 1  and V 2  at the inverting and non inverting terminals thereof, a third supply voltage V AL  to the power supply terminals, not shown in the drawing, being common also to all the other circuit amplifiers, and it outputs a comparative voltage signal V OUT1-H1 , which is low (0V) during the storage period and high (Vcc) in the remaining period portion. This signal is taken with reference to a third circuit node N 3 . 
   A filtering block H 2  receives at the input the comparative voltage signal V OUT1-H1  output from the first comparator block H 1 ; this block H 2  is composed of a circuit RC comprising a resistance Rf and a capacity Cf being respectively comprised between a fourth circuit node N 4  outside the block H 2  and the third node N 3 , and between the circuit node N 4  and a ground GND. 
   The filtering block H 2  simply serves to filter the harmonic components of the signal V OUT1-H1 , received from the comparator block H 1 , from the onward switching frequency, in order to obtain only the average value. 
   The filtering block H 2  outputs a filtered voltage signal V OUT-H2  in correspondence with the fourth node N 4 . 
   An amplification block H 3 , comprising a fedback differential amplifier  24 , receives at the input an input signal V IN4  and a voltage reference signal Vref, and it outputs an amplified voltage signal V OUT-H3 . The input signal V IN4  is obtained from the filtered voltage signal V OUT-H2 , under the effect of the voltage drop on an input resistance Ra and under of the effect of a resistance Rc on the feedback loop of the amplifier  24 . 
   The output block Hout 1  receives at the input the amplified voltage signal V OUT-H3 , an input voltage value VinSW 1  and it outputs a voltage value VB NEW  to bias the emitter-switching circuit  1 . 
   This output block comprises a second comparator block H 4  receiving at the input the amplified voltage signal V OUT-H3 , a triangular reference voltage signal Vramp and it outputs a signal PWM, indicated with V OUT-H4 . 
   Advantageously the output block Hout 1  further comprises a buck converter BUCK for a DC/DC conversion and outputting a voltage being lower than the voltage received at the input; this converter comprises in turn a switch SW 1 . The switch SW 1  receives at the input the signal VinSW 1 , the signal V OUT-H4  regulating the turn-on time thereof and thus regulating the duty-cycle of the converter BUCK, and it is output-connected to a fifth circuit node N 5 ; the converter BUCK further comprises a diode D 1  interposed between the fifth node N 5  and the ground GND, allowing the current to flow only towards said fifth node N 5  and an inductance L 3  interposed between the fifth circuit node and the second circuit node N 2  whereto a second capacitor C 1  is further connected, interposed in turn between the second circuit node N 2  and the ground GND. 
   The operation of the driving network  20  is now described, with reference to  FIGS. 7 ,  8 ,  9 . 
   Once a collector current IC in the bipolar transistor of the emitter-switching block  1  is set, the bias voltage VB variation under the effect of the voltage drop variation on the resistance RB, allows the base current IB value to be varied during the bipolar transistor operation step. 
   The base current IB value sets the bipolar transistor saturation level, corresponding to the setting of the transistor storage time. 
   The operating principle of the control diagram shown in  FIG. 7  is to measure the storage time indirectly by reading the voltage across the base resistance RB, to compare the value obtained with a reference value, and, by means of a negative feedback network NET_neg, to operate on the duty-cylce of the buck converter BUCK, in order to conveniently vary the bias voltage VB, thus keeping the storage time constant for any noise with respect to the reference value. 
   The voltage VRB across the base resistance RB is shown in  FIG. 8   a . Observing that the voltage VRB is negative only during the storage time, by applying this signal between the non inverting terminal and the inverting terminal of a simple comparator, such as, for example, the comparator  23  of the block H 1 , and by applying a non dual supply voltage VCC to the comparator power supply terminals, not shown in the figure, the signal V OUT     —     H1  output from the block H 1  will have a low value during the storage time (0V) and a high value during the remaining period portion (VCC). 
   By performing the harmonic breakdown of the signal V OUT     —     H1 , carried out by means of the filtering block H 2 , a signal is obtained, which is proportional to the storage time, with an average value Vmed being identified by a dotted line in  FIG. 8   b  and by the harmonic components with higher frequencies than the switching frequency. By filtering this signal by means of a low-pass filter with a lower cutting frequency than the switching frequency, a continuous voltage signal is definitely obtained whose value Vmed is proportional to the storage time. 
   Quantitatively, 
   
     
       
         
           
               
           
           ⁢ 
           
             Vmed 
             = 
             
               
                 
                   
                     
                       T 
                       S 
                     
                     - 
                     
                       t 
                       storage 
                     
                   
                   
                     T 
                     S 
                   
                 
                 ⁢ 
                 Vcc 
               
               = 
               
                 Vcc 
                 ⁡ 
                 
                   ( 
                   
                     1 
                     - 
                     
                       
                         t 
                         storage 
                       
                       
                         T 
                         S 
                       
                     
                   
                   ) 
                 
               
             
           
         
       
     
   
   The choice of connecting the comparator block H 1  so that the output signal V OUT-H1  is always high during the period, and low only during the storage time, originates from the need of having a continuous signal at the input of the amplification block H 3  with a higher value than a voltage V BE  calculated between the bipolar transistor base and emitter and thus sufficient to ensure the bias of the amplifier input stage. 
   The storage time could also be drawn from a voltage signal being proportional to the storage time itself exploiting, for example, the MOS transistor gate voltage value VG and the bipolar transistor collector voltage.  FIG. 9   a  shows the structure of the connections between the emitter-switching configuration circuit  1  and the comparator block H 1  in a portion of the driving network  20 , in order to read the storage time, exploiting the gate and collector signals respectively taken at the MOS transistor control terminal G and at the bipolar transistor conduction terminal C; as shown in  FIG. 9   b , the falling slope of the gate signal VG is the beginning of the storage time t storage  interval and it corresponds to a negative value of the base current IB, while the rising slope of the collector voltage V CS  detects the end of the storage time interval. 
   By exploiting the described gate and collector signal and by means of a logic network which can be easily formulated by a skilled in the art, a squared-wave signal can be obtained with the same features as the previous reading method, i.e. having always a high logic level except from during the storage time. 
   As a consequence, the same formula being previously cited for calculating the average value Vmed is still valid. 
   
     
       
         
           Vmed 
           = 
           
             
               
                 
                   
                     T 
                     S 
                   
                   - 
                   
                     t 
                     storage 
                   
                 
                 
                   T 
                   S 
                 
               
               ⁢ 
               Vcc 
             
             = 
             
               Vcc 
               ⁡ 
               
                 ( 
                 
                   1 
                   - 
                   
                     
                       t 
                       storage 
                     
                     
                       T 
                       S 
                     
                   
                 
                 ) 
               
             
           
         
       
     
   
   Alternatively, the just shown storage time reading method, consisting in drawing a voltage signal being proportional to the storage time, in a so-called time-voltage conversion, could also be realized by charging a capacitance at a constant current for the whole storage time, obtaining in practice a voltage value on the capacitance, at the end of the storage time, being proportional to the storage time itself, according to the same above-cited mathematical relationship. 
   In this case, a filtering block H 2   I  can be realized by means of the functional diagram of  FIG. 10 . 
   In this figure, a signal VH 2 -IN, corresponding to the V OUT-H1  signal output from the comparator block H 1 , is at the input of the filtering block H 2   I  and it is processed in order to generate two activation signals A and B for two generators GA and GB with the same current l; the generator GA is connected to the first voltage reference VCC and, by means of a circuit node NA, to a capacitor CA, connected in turn to the ground terminal GND; the generator GA is also connected, always by means of the circuit node NA, to a switch SWA, allowing or preventing the transmission of the generated signals, in order to let them go out of the filtering block H 2   I , passing through an output node Out. 
   The generator GB is connected to a supply voltage Vcc and, by means of a circuit node NB, to a capacitor CB, connected in turn to a ground terminal GND; the generator GB is also connected, always by means of the node NB, to a switch SWB, allowing or preventing the transmission of the signals output from the filtering block H 2   I , passing through an output node Out. 
   The capacitors CA and CB are alternately charged with a constant current I by respective current generators GA and GB, for a time interval corresponding to the storage time and they keep the charged voltage value for a period Ts. In this way, in each period one of the capacitors always carries the previous pulse storage time information by means of a signal, indicated with V H2     —     OUT  in  FIG. 10  being detected in the node Out and substantially coinciding with the fourth current node N 4 , which is used as an input for the amplification block H 3 . 
     FIG. 11  shows the signal trends on the capacitors CA and CB of  FIG. 10 , with reference to the MOS transistor control voltage VG. 
   The amplification block H 3  serves to amplify the voltage signal V H2     —     OUT  output from the block H 2   I  or the signal V OUT     —     H2  output from the block H 2  and to compare them with a reference signal Vref to output an amplified signal  VOUT     —     H3 . 
   The second comparator block H 4  serves as a PWM modulator. 
     FIG. 12  shows the wave forms of the signal V OUT     —     H3  and of a triangular reference signal V ramp , both at the input of the second comparator block H 4 ; this figure also shows the signal V OUT     —     H4  of the PWM type, output from said comparator. In practice, by comparing the triangular reference signal V ramp  with the signal V OUT     —     H3 , output from the differential amplifier of the amplification block H 3 , by means of the comparator block H 4 , comprised in the output block Hout 1 , a signal V OUT-H4  of the PWM type is obtained, which is directed towards the switch SW 1  of the converter BUCK of the output block Hout 1 , in order to regulate the voltage VB NEW  output from said block Hout 1 . 
   The driving network  20 , related to the first embodiment of the present invention, operates with standard operating currents; moreover, the insertion of the switch SW 1  allows the driving network to be used also when the operating currents become very high, for example in very high power applications. 
   In a second embodiment of the driving network, related to the present invention, the storage time is regulated by replacing the output block Hout 1  comprising the converter BUCK with a linear regulation block Hout 2 , as shown in  FIG. 13 . 
   This second embodiment is particularly suitable for low power applications. 
   This figure, wherein the components and signals being already in  FIG. 7  and having the same structure and operation will be marked with the same previously used labels, shows a driving network  30  performing a linear regulation of the voltage VB at the input of the bipolar transistor control terminal B of the emitter-switching circuit  1 . 
   The difference with respect to the first preferred embodiment is represented by the linear regulation block Hout 2  receiving at its input the output V OUT     —     H3  of the amplifier  24  of the block H 3 , as shown in  FIG. 13 , replacing the output block Hout 1  comprising the converter BUCK, shown in  FIG. 7 . 
   In the block Hout 2 , similarly to known linear regulation systems, a second bipolar transistor TR 3  of the PNP type is used, whose base current IB 3  is modulated by the storage time control circuit. 
   The block Hout 2  thus comprises the transistor TR 3  which is connected, by means of a control (base) terminal B 3  thereof to the output of the block H 3 , a first conduction terminal, particularly an emitter terminal E 3 , connected to an input terminal IN and a second conduction terminal, particularly a collector terminal C 3 , connected to the traditional driving block  21  coinciding with the second circuit node N 2 . A capacity C 1  is interposed between the collector terminal C 3  and the ground GND. 
   In this second preferred embodiment a modulation of the PWM type is no longer necessary; the output V OUT     —     H3  of the amplifier  24  of the block H 3 , in the absence of a following stage for amplifying the current, directly drives the base terminal B 3  of the bipolar transistor TR 3 ; by varying the current IB 3  output from the amplifier  24 , the voltage drop between the collector C 3  and the emitter E 3  of the transistor TR 3  varies, letting the latter vary a voltage VB NEW  output from the node N 2  with respect to an input signal VIN, at the emitter terminal E 3  thereof. The output voltage VB NEW  is then used as an input to the driving circuit  21  to bias the emitter-switching  1 . 
   Advantageously, the described driving network  30 , with a linear output, besides being a simpler solution from the circuit point of view than the first preferred embodiment of  FIG. 7 , also involves a lower cost and it provides greater integration opportunities. 
   In order to demonstrate the real operation of the driving circuit according to embodiments of the invention, a PFC application has been considered, wherein, even with a constant load, for the power factor correction role played by this application, the power device, in a period of 10 ms, sees the operating conditions vary from a null current to the highest current. As shown in the wave form of  FIG. 15 , the PFC is the worst case, since a variation of the operating conditions continuously occurs, and wherein without the driving network according to embodiments of the present invention the use of a cascode configuration could not be envisaged;  FIG. 15  shows the wave forms of the collector and base voltages IC and IB. 
   However it must be noticed that the driving network provided in the invention can be used in all those applications wherein, because of a load variation or because of an input variation, a variation of the power device operating conditions occurs. This network puts the cascode configuration in the optimum operating conditions, as previously explained. 
   For the PFC application, used as a testing means, the control method embodiment has been that of  FIG. 14 . This figure shows a testing driving network  40  wherein it has been chosen to read the storage time by means of the collector and gate signals, as previously described with reference to  FIGS. 9   a  and  9   b , and to use a linear regulation diagram, as the one described in the second preferred embodiment of the present invention, shown in  FIG. 13 . 
   In order to show the operation of the driving network  30 , referring to the component and signal references of  FIG. 13 , the wave forms of the base and collector currents IB and IC and of the collector voltage Vcc will be compared, both with a constant base power supply, i.e. with VB′=constant and with a power supply by means of the driving network  30 . 
   The power supply VB is chosen equal to 5V, while in the constant power supply case, the power supply VB′ was set to 3.5V. This value ensured the device operation at the highest operating current, with the same storage time which is set by the driver in the proposed solution. The optimum storage time is of about 500 ns. 
     FIGS. 16 and 19  show wave forms being respectively related to a constant bias of the base B and by means of the driving network  30 , in the high collector current IC case. 
   By comparing  FIG. 16  with  FIG. 19 , totally similar operating situations can be observed; in fact the collector current IC reaches about 10A and the storage time is almost equal in both figures. 
     FIGS. 17 and 20  show wave forms being respectively related to a constant bias of the base B and by means of the driving network  30 , in the average collector current IC case. 
   By comparing  FIG. 17  with  FIG. 20 , wherein the collector current is of about 7.5 A, it can be seen how in the constant base bias case, of  FIG. 17 , the storage time is of about 1.5 μs, while in  FIG. 20 , by using the driving network  30 , the storage time is constant. 
   Finally, in order to further emphasise the driver operation, the wave forms of  FIG. 18  and of  FIG. 21  are compared; in this case, in  FIG. 18 , it can be seen how the constant bias has created an excessive device saturation situation, and the storage time has become higher than the turn-off time t off , thus generating the loss of some switchings. This happens because the following gate pulse occurs even before the device is actually turned off. In  FIG. 21  it can be instead seen how also in this situation the driver keeps the storage time constant. 
   The storage time variation, in the constant power supply case, besides generating an application malfunction, for low current values, generates a device over-saturation which slows down the device during the turn-off step. 
   In fact, by comparing the collector voltage VCS trend in  FIGS. 17 and 20 , it can be seen how the Vcs during the turn-off step requires a longer time for passing from the saturation value Vcssat thereof to the 380V clamp voltage. 
   The slower turn-off creates greater power dissipations during the low-current turn-off step, this effect results in a device temperature increase in the application global operation. 
   In order to show this last aspect, in Table 1 below, once a same input power for the PFC operation is set, and keeping the same power device, i.e. an emitter-switching bipolar transistor, it can be observed how the constant bias makes the cascode configuration totally unsuitable for this kind of applications, while by introducing the driving network, subject-matter of embodiments of the present invention, good operating conditions can be reached. 
   
     
       
         
             
             
             
             
             
           
             
               TABLE 1 
             
             
                 
             
             
                 
                 
               Power 
                 
               Device 
             
             
               Bias method 
               Power Input 
               Output 
               IB average 
               temperature 
             
             
                 
             
           
          
             
               VB′ = 3.5 V 
               1000 W 
               837 W 
                0.5 A 
               &gt;110° 
             
             
               with driver 
               1000 W 
               850 W 
               0.15 A 
                  73° 
             
             
                 
             
          
         
       
     
   
   In conclusion, the driving network shown in the described embodiments of the present invention allows the following advantages to be reached:
     Correct bias of a bipolar transistor base in an emitter-switching configuration for each value of the collector current, optimizing the cascode configuration operating performances for each operating condition in applications with variable operating currents, and thus in the global application operation. In fact a system being capable to follow the current gain variation hfe law is obtained.   Automatic bias network regulation for each kind of hfe spread variation.   Fixed storage time, and regulated at the lowest value for each operating condition, and thus possibility of using the cascode configuration in high switching frequency applications.   

   From the foregoing it will be appreciated that, although specific embodiments of the invention have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the invention.