Patent Publication Number: US-6710659-B2

Title: Variable-gain amplifier with stepwise controller

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a variable-gain amplifier, i.e., an amplifier that permits its gain to be controlled, for use in an integrated circuit, and more particularly to a variable-gain amplifier for use in an integrated circuit for receiving digital satellite broadcasts. 
     2. Description of the Prior Art 
     FIG. 16 shows an example of the configuration of a conventional variable-gain amplifier. An input voltage signal V IN1  is fed to a terminal that is connected to the base of an NPN-type input transistor Q 1 , and an input voltage signal V IN2  is fed to a terminal that is connected to the base of an NPN-type input transistor Q 2 . The emitters of the input transistors Q 1  and Q 2  are connected together through a resistor RE 1 . The emitter of the input transistor Q 1  is grounded through a constant current source  1  that outputs a constant current I C , and the emitter of the input transistor Q 2  is grounded through a constant current source  2  that outputs a constant current I C . 
     To the collector of the input transistor Q 1 , the emitters of NPN-type transistors Q 3  and Q 4  are connected. To the collector of the input transistor Q 2 , the emitters of NPN-type transistors Q 5  and Q 6  are connected. 
     A constant voltage V CC  is supplied to a terminal that is connected to one end of a resistor RL 1 , to the collector of the transistor Q 4 , to the collector of the transistor Q 5 , and to one end of a resistor RL 2 . The other end of the resistor RL 1  is connected to the collector of the transistor Q 3  and to a terminal from which an output voltage signal V OUT1  is fed out, and the other end of the resistor RL 2  is connected to the collector of the transistor Q 6  and to a terminal from which an output voltage signal V OUT2  is fed out. 
     A reference voltage V B1  is supplied to a terminal that is connected to the base of the transistor Q 3  and to the base of the transistor Q 6 . A control voltage V C1  is supplied to a terminal that is connected to the base of the transistor Q 4  and to the base of the transistor Q 5 . 
     Next, the operation of the variable-gain amplifier of FIG. 16 will be described. When the levels of the input voltage signals V IN1  and V IN2  are low, the control voltage V C1  is reduced so that the base potential of the transistors Q 3  and Q 6  is higher than the base potential of the transistors Q 4  and Q 5 . As a result, almost no current flows through the transistors Q 4  and Q 5 , and most of the collector current of the input transistors flows through the transistors Q 3  and Q 6 . Accordingly, a large amount of current flows through the output load resistors RL 1  and RL 2 , yielding a high gain. 
     On the other hand, when the levels of the input voltage signals V IN1  and V IN2  are high, the control voltage V C1  is increased so that the base potential of the transistors Q 3  and Q 6  is lower than the base potential of the transistors Q 4  and Q 5 . As a result, most of the collector current of the input transistors flows through the transistors Q 4  and Q 5 , and almost no current flows through the transistors Q 3  and Q 6 . Accordingly, a small amount of current flows through the output load resistors RL 1  and RL 2 , yielding a low gain. Thus, the gain characteristic curve T 1  of the variable-gain amplifier of FIG. 16 with respect to the control voltage V C1  is as shown in FIG.  17 . In FIG. 17, the symbol V th1  represents the threshold level of the control voltage V C1  at which the variable-gain amplifier of FIG. 16 starts attenuating its gain. 
     When the variable-gain amplifier is used in a digital satellite broadcast system or terrestrial broadcast system, the input voltage signals V IN1  and V IN2  are high-frequency signals having frequencies of from about a few hundred MHz to a few GHz. Moreover, in a digital satellite broadcast system or terrestrial broadcast system, a wide dynamic range of typically 60 dB or over is required. 
     However, in the variable-gain amplifier of FIG. 16, when high-frequency signals are fed in, leak current flows through the collector-emitter parasitic capacitance (about a few tens of fF) of the transistors Q 3  and Q 6 . This causes saturation of gain attenuation, and thus the gain characteristic curve T 2  of the variable-gain amplifier with respect to the control voltage V C1  when high-frequency signals are fed in is as shown in FIG.  18 . 
     In this way, the variable-gain amplifier of FIG. 16 cannot attenuate its gain sufficiently when high-frequency signals are fed in, and thus, quite inconveniently, does not offer a wide input dynamic range as required in a digital satellite broadcast system or terrestrial broadcast system. 
     FIG. 19 shows another example of the configuration of a conventional variable-gain amplifier. The variable-gain amplifier of FIG. 19 is provided with a variable-gain amplifier circuit A 1  and a variable-gain amplifier circuit A 2 . 
     First, the configuration of the variable-gain amplifier circuit A 1  will be described. An input signal V in1  is fed to a terminal that is connected to the base of an NPN-type input transistor Q 21 , and an input signal V in2  is fed to a terminal that is connected to the base of an NPN-type input transistor Q 22 . The emitters of the input transistors Q 21  and Q 22  are connected together through a resistor R 7 . The emitter of the input transistor Q 21  is grounded through a constant current source  21  that produces a bias current I C , and the emitter of the input transistor Q 22  is grounded through a constant current source  22  that produces a bias current I C . 
     To the collector of the input transistor Q 21 , the emitters of NPN-type transistors Q 14  and Q 15  are connected. To the collector of the input transistor Q 22 , the emitters of NPN-type transistors Q 16  and Q 17  are connected. 
     A constant voltage V CC  is supplied to a terminal that is connected to the collectors of the transistors Q 15  and Q 16 . 
     A bias voltage V bias  is supplied to a terminal that is connected to the bases of the transistors Q 14  and Q 17 . A control voltage V AGC , which is a reference control voltage, is supplied to a terminal that is connected to the bases of the transistors Q 15  and Q 16 . 
     Next, the configuration of the variable-gain amplifier circuit A 2  will be described. The terminal to which the input signal V in1  is fed is connected to the base of an NPN-type input transistor Q 20 , and the terminal to which the input signal V in2  is fed is connected to the base of an NPN-type input transistor Q 23 . The emitters of the input transistors Q 20  and Q 23  are connected together through a resistor R 8 . The emitter of the input transistor Q 20  is grounded through a constant current source  20  that produces a bias current I C , and the emitter of the input transistor Q 23  is grounded through a constant current source  23  that produces a bias current I C . 
     To the collector of the input transistor Q 20 , the emitters of NPN-type transistors Q 12  and Q 13  are connected. To the collector of the input transistor Q 23 , the emitters of NPN-type transistors Q 18  and Q 19  are connected. 
     The terminal to which the constant voltage V CC  is supplied is connected to one end of an output load resistor R 5 , to the collector of the transistor Q 13 , to the collector of the transistor Q 18 , and to one end of an output load resistor R 6 . The other end of the output load resistor R 5  is connected to the collector of the transistor Q 12 , and the other end of the output load resistor R 6  is connected to the collector of the input transistor Q 19 . 
     The terminal to which the bias voltage V bias  is supplied is connected to the bases of the transistors Q 12  and Q 19 . The terminal to which the control voltage V AGC  is supplied is connected through a resistor R 3  to the bases of the transistors Q 13  and Q 18 . The node between the resistor R 3  and the transistors Q 3  and Q 8  is grounded through a resistor R 4 . 
     The variable-gain amplifier circuits A 1  and A 2  configured as described above are connected in parallel. Superficially, the collectors of the transistors Q 12  and Q 14  are both connected to a terminal from which an output signal V out1  is fed out, and the collectors of the transistors Q 17  and Q 19  are both connected to a terminal from which an output signal V out2  is fed out. 
     In the variable-gain amplifier circuits A 1  and A 2 , there is a tradeoff between noise factor and intermodulation distortion characteristics. Therefore, the variable-gain amplifier circuit A 1  is designed to offer good noise factor characteristics, and the variable-gain amplifier circuit A 2  is designed to offer good intermodulation distortion characteristics. 
     Next, the operation of the variable-gain amplifier of FIG. 19 will be described. When the levels of the input signals V in1  and V in2  are low, the control voltage V AGC  is reduced so that the base potential of the transistors Q 12 , Q 14 , Q 17 , and Q 19  is higher than the base potential of the transistors Q 13 , Q 15 , Q 16 , and Q 18 . As a result, almost no current flows through the transistors Q 13 , Q 15 , Q 16 , and Q 18 , and most of the collector current of the input transistors flows through the transistors Q 12 , Q 14 , Q 17 , and Q 19 . Accordingly, a large amount of current flows through the output load resistors R 5  and R 6 , and thus the variable-gain amplifier yields a high gain. 
     On the other hand, when the levels of the input signals V in1  and V in2  are high, the control voltage V AGC  is increased so that the base potential of the transistors Q 12 , Q 14 , Q 17 , and Q 19  is lower than the base potential of the transistors Q 13 , Q 15 , Q 16 , and Q 18 . As a result, most of the collector current of the input transistors flows through the transistors Q 13 , Q 15 , Q 16 , and Q 18 , and almost no current flows through the transistors Q 12 , Q 14 , Q 17 , and Q 19 . Accordingly, a small amount of current flows through the output load resistors R 5  and R 6 , and thus the variable-gain amplifier yields a low gain. 
     Moreover, since the control voltage V AGC  is applied to the bases of the transistors Q 15  and Q 16 , and a division voltage of the control voltage V AGC  is applied to the bases of the transistors Q 13  and Q 18 , the variable-gain amplifier circuits A 1  and A 2  start attenuating their gains at different threshold levels of the control voltage V AGC . Let the threshold level of the control voltage V AGC  at which the variable-gain amplifier circuit A 1  starts attenuating its gain be V b1 , and the threshold level of the control voltage V AGC  at which the variable-gain amplifier circuit A 2  starts attenuating its gain be V b2  (V b1 &lt;V b2 ). The potential difference between V b1  and V b2  equals the potential difference between the two ends of the resistor R 3 . 
     Since the variable-gain amplifier circuits A 1  and A 2  are connected in parallel, the gain G total  of the variable-gain amplifier of FIG. 19 equals the sum of the gain G A1  of the variable-gain amplifier circuit A 1  and the gain G A2  of the variable-gain amplifier circuit A 2 . Thus, the gain G total  of the conventional variable-gain amplifier with respect to the control voltage V AGC  shows a characteristic curve as shown in FIG.  20 . Here, in a region where the levels of the input signals are low, i.e., when the control voltage V AGC  is low, the G A1  of the variable-gain amplifier circuit A 1  is predominant, offering good noise figure characteristics; in a region where the levels of the input signals are high, i.e., when the control voltage V AGC  is high, the G A2  of the variable-gain amplifier circuit A 2  is predominant, offering good intermodulation distortion characteristics. 
     However, the variable-gain amplifier of FIG. 19 has the following two disadvantages. The first is the degradation of intermodulation distortion characteristics when high-frequency signals are fed in. The second is the voltage drops across output load resistors increasing as more and more variable-gain amplifier circuits are connected in parallel. 
     The cause of the first disadvantage, i.e., the degradation of intermodulation distortion characteristics when high-frequency signals are fed in, will be described. 
     In the variable-gain amplifier of FIG. 19, when the control voltage V AGC  becomes higher than the threshold level V b1  at which the variable-gain amplifier circuit A 1  starts attenuating its gain, the current flowing through the transistors Q 14  and Q 17  decreases, attenuating the gain of the variable-gain amplifier circuit A 1 . However, since the constant current sources  21  and  22  supply a constant bias current I C  irrespective of the level of the control voltage V AGC , the signal amplified by the input transistor Q 21  is fed to the emitter of the transistor Q 14 , and the signal amplified by the input transistor Q 22  is fed to the emitter of the transistor Q 17 . 
     When high-frequency signals are fed in, the signal amplified by the input transistor Q 21  leaks through the emitter-collector parasitic capacitance of the transistor Q 14  to the output load resistor R 5 , and the signal amplified by the input transistor Q 22  leaks through the emitter-collector parasitic capacitance of the transistor Q 17  to the output load resistor R 6 . 
     Thus, when high-frequency signals are fed in, even if the control voltage V AGC  is increased, the gain attenuation of the variable-gain amplifier circuit A 1  is saturated as shown in FIG.  21 . This makes the gain difference D between the variable-gain amplifier circuits A 1  and A 2  smaller in a range in which the control voltage V AGC  is high. When high-frequency signals are fed in, the gain attenuation of the variable-gain amplifier circuit A 2  also is saturated. However, when saturated, the gain of the variable-gain amplifier circuit A 2  almost equals zero, and therefore, in the following description, the gain attenuation of this variable-gain amplifier circuit A 2  is assumed not to be saturated. 
     Now, how the smaller gain difference D degrades intermodulation distortion characteristics will be described. FIG. 22 shows the input-output characteristics of the variable-gain amplifier circuit A 1 , the variable-gain amplifier circuit A 2 , and the variable-gain amplifier as a whole. In this figure, line (1)_ 1  represents the input-output characteristic of the variable-gain amplifier circuit A 1  with respect to the fundamental component, line (1)_ 3  represents the input-output characteristic of the variable-gain amplifier circuit A 1  with respect to the third-order harmonic component, line (2)_ 1  represents the input-output characteristic of the variable-gain amplifier circuit A 2  with respect to the fundamental component, line (2)_ 3  represents the input-output characteristic of the variable-gain amplifier circuit A 2  with respect to the third-order harmonic component, line t_ 1  represents the input-output characteristic of the variable-gain amplifier as a whole with respect to the fundamental component, and line t_ 3  represents the input-output characteristic of the variable-gain amplifier as a whole with respect to the third-order harmonic component. In the graph of FIG. 22, the input level is taken along the horizontal axis, and the output level is taken along the vertical axis, with both levels given in dB. 
     The input level that is supposed to cause the fundamental component and the third-order harmonic component to have equal output levels is called the input intercept point (IIP 3 ). The higher this value, the better the intermodulation distortion characteristics obtained. Let the input intercept point in the variable-gain amplifier circuit A 1 , in the variable-gain amplifier circuit A 2 , and in the variable-gain amplifier as a whole when the level of the input signal equals p be IIP3 — 1(p), IIP 3 _ 2 (p), and IIP 3 _total(p), respectively. Moreover, let the output level difference between the third-order harmonic component and the fundamental component in the variable-gain amplifier circuit A 1 , in the variable-gain amplifier circuit A 2 , and in the variable-gain amplifier as a whole when the level of the input signal equals p be IM 3 _ 1 (p), IM 3 _ 2 (p), and IM3_total(p), respectively. 
     FIG. 22 shows that the gradient of line (1)_ 1  is 1 and the gradient of line (1) — 3 is 3. Hence, 
     
       
           IIP 3   _ 1 ( p )= p+IM 3   _ 1 ( p )/2  (1) 
       
     
     Moreover, FIG. 22 shows that the gradient of line t_ 1  is 1 and the gradient of line t_ 3  is 3. Hence, 
       IIP 3_total( p )= p+{D+[IM 3 — 1( p )]}/2  (2) 
     From equations (1) and (2), IIP 3 _total(p) is given as 
     
       
           IIP 3   _total( p )= IIP 3   _ 1 ( p )+ D/ 2  (3) 
       
     
     Equation (3) shows that, to increase the input intercept point IIP 3  of the variable-gain amplifier as a whole, i.e., to obtain better intermodulation distortion characteristics, the gain difference D needs to be increased. However, as described above, in the variable-gain amplifier of FIG. 19, when high-frequency signals are fed in and their levels are high, it is not possible to obtain a sufficiently large gain difference D. This leads to degraded intermodulation distortion characteristics. 
     Next, the cause of the second disadvantage, i.e., the voltage drops across output load resistors increasing as more and more variable-gain amplifier circuits are connected in parallel, will be described. 
     To make the gain characteristic curve of the variable-gain amplifier with respect to the control voltage V AGC  smooth, it is advisable to connect a number of (n) variable-gain amplifier circuits in parallel as shown in FIG.  23 . In FIG. 23, such circuit elements and signals as are found also in FIG. 19 are identified with the same reference numerals and symbols, and their explanations will not be repeated. The variable-gain amplifier circuits A 3  to An are each configured in the same manner as the variable-gain amplifier circuit A 1 . 
     In the variable-gain amplifier of FIG. 23, through the output load resistors R 5  and R 6  flows n times the current that will flow through them in a configuration where only one variable-gain amplifier circuit is provided, causing, accordingly, n times the voltage drops across the output load resistors R 5  and R 6 . Therefore, unless the resistances of the output load resistors are reduced, or the bias current I C  output from the constant current sources is reduced, the transistors provided in the variable-gain amplifier may be saturated and cease to operate. However, since the amplitudes of the output signals equal the resistances of the output load resistors R 5  and R 6  multiplied by the current of the output signals, which are alternating currents, reducing the resistances of the output load resistors R 5  and R 6 , quite inconveniently, results in reducing the gain of the variable-gain amplifier. On the other hand, reducing the bias current I C  output from the constant current sources, also quite inconveniently, results in narrowing the input dynamic range. 
     SUMMARY OF THE INVENTION 
     An object of the present invention is to provide a variable-gain amplifier that offers a wide input dynamic range even when high-frequency signals are fed in. 
     To achieve the above object, according to one aspect of the present invention, a variable-gain amplifier is provided with a controller for controlling the operation of input transistors. This makes it possible to reduce the leak current that flows through transistors because of their collector-emitter parasitic capacitance when high-frequency signals are fed in and thereby prevent saturation of gain attenuation. 
     According to another aspect of the present invention, a variable-gain amplifier is provided with a plurality of variable-gain amplifier circuits connected in parallel and a current control circuit for controlling the bias current sources provided within each of the variable-gain amplifier circuits. This makes it possible to reduce the leak current that flows through transistors because of their collector-emitter parasitic capacitance when high-frequency signals are fed in and thereby prevent saturation of gain attenuation. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     This and other objects and features of the present invention will become clear from the following description, taken in conjunction with the preferred embodiments with reference to the accompanying drawings in which: 
     FIG. 1 is a diagram showing the configuration of the variable-gain amplifier of a first embodiment of the invention; 
     FIG. 2 is a graph showing the gain characteristic of the variable-gain amplifier of FIG. 1; 
     FIG. 3 is a graph showing the gain characteristic of the variable-gain amplifier of FIG. 1, with different settings of the subsidiary control voltage; 
     FIG. 4 is a graph showing the relationship between the control voltage and the subsidiary control voltage as observed when the subsidiary control voltage is varied stepwise; 
     FIG. 5 is a graph showing the gain characteristic of the variable-gain amplifier of FIG. 1 as observed when the subsidiary control voltage is varied stepwise, with different settings of the subsidiary control voltage; 
     FIG. 6 is a diagram showing the configuration of the variable-gain amplifier of a second embodiment of the invention; 
     FIG. 7 is a graph showing the resistance characteristic of the variable resistor provided in the variable-gain amplifier of FIG. 6; 
     FIG. 8 is a diagram showing the configuration of the variable-gain amplifier of a third embodiment of the invention; 
     FIG. 9 is a graph showing the output voltage characteristic of the variable voltage source provided in the variable-gain amplifier of FIG. 8; 
     FIG. 10 is a diagram showing the configuration of the variable-gain amplifier of a fourth embodiment of the invention; 
     FIG. 11A is a diagram showing the gain characteristic of the variable-gain amplifier of FIG. 10; 
     FIG. 11B is a diagram showing the bias current characteristic of each variable-gain amplifier circuit provided in the variable-gain amplifier of FIG. 10; 
     FIG. 12 is a diagram showing the configuration of the variable-gain amplifier of FIG. 10 when it is provided with a number of variable-gain amplifier circuits; 
     FIG. 13 is a diagram showing the configuration of the variable-gain amplifier of a fifth embodiment of the invention; 
     FIG. 14 is a diagram showing the configuration of the variable-gain amplifier of a sixth embodiment of the invention; 
     FIG. 15A is a diagram showing a practical example of the voltage shift operation circuit provided in the variable-gain amplifiers of the fifth and sixth embodiments; 
     FIG. 15B is a diagram showing another practical example of the voltage shift operation circuit provided in the variable-gain amplifiers of the fifth and sixth embodiments; 
     FIG. 16 is a diagram showing an example of the configuration of a conventional variable-gain amplifier; 
     FIG. 17 is a graph showing the gain characteristic of the variable-gain amplifier of FIG. 16; 
     FIG. 18 is a graph showing the gain characteristic of the variable-gain amplifier of FIG. 16 when high-frequency signals are fed in; 
     FIG. 19 is a diagram showing another example of the configuration of a conventional variable-gain amplifier; 
     FIG. 20 is a graph showing the gain characteristic of the variable-gain amplifier of FIG. 19; 
     FIG. 21 is a graph showing the gain characteristic of the variable-gain amplifier of FIG. 19 when high-frequency signals are fed in; 
     FIG. 22 is a graph showing the input-output characteristic of the variable-gain amplifier of FIG. 19; and 
     FIG. 23 is a diagram showing still another example of the configuration of a conventional variable-gain amplifier. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows the configuration of the variable-gain amplifier of a first embodiment of the invention. It is to be noted that such circuit elements and signals as are found also in FIG. 16 are identified with the same reference numerals and symbols, and their explanations will not be repeated. The emitter of an NPN-type transistor Q 7  is connected to the emitter of the input transistor Q 1 , and the emitter of an NPN-type transistor Q 8  is connected to the emitter of the input transistor Q 2 . The collectors of the transistors Q 7  and Q 8  are connected to the terminal to which the constant voltage V CC  is supplied. The bases of the transistors Q 7  and Q 8  are connected to a terminal to which a subsidiary control voltage V C2  is supplied. 
     Here, for simplicity&#39;s sake, it is assumed that the base-emitter voltages of all the transistors are equal, namely V BE . It is also assumed that, in setting the subsidiary control voltage V C2 , no consideration is given to the alternating-current components of the input voltage signals. 
     The levels of the reference voltage V B1  and of the direct-current bias voltage V B2  that is included in the input voltage signals V IN1  and V IN2  are so set as to fulfill formula (4) below. 
     
       
           V   B2   ≦V   B1   −V   BE   (4) 
       
     
     Hence, let the threshold level of the control voltage V C1  at which current starts flowing through the transistors Q 4  and Q 5  be V th1  and the threshold level of the subsidiary control voltage V C2  at which current starts flowing through the transistors Q 7  and Q 8  be V th2 , then formula (5) below holds. 
     
       
           V   th2   &lt;V   th1   (5) 
       
     
     Therefore, the subsidiary control voltage V C2  is so set as to fulfill formula (6) below, where α&gt;V th1 −V th2 . This makes the level of the control voltage V C1  at which current starts flowing through the transistors Q 7  and Q 8  higher than the level of the control voltage V C1  at which current starts flowing through the transistors Q 4  and Q 5 . 
     
       
           V   C2   =V   C1 −α  (6) 
       
     
     When the subsidiary control voltage V C2  is so set as to fulfill formula (6), the gain characteristic curve T 3  with respect to the control voltage V C1  when high-frequency signals are fed in is as shown in FIG.  2 . It is to be noted that the gain characteristic curve T 2  of the variable-gain amplifier of FIG. 16 when high-frequency signals are fed in is shown together. 
     In the region where V C1 &lt;V th1 , most of the current output from the input transistors flows through transistors Q 3  and Q 6 , and almost no current flows through the transistors Q 4  and Q 5 . In this state, since V C2 &lt;V th2 , almost no current flows through the transistors Q 7  and Q 8 . Thus, in the region where V C1 &lt;V th1 , the variable-gain amplifier offers its maximum gain. 
     In the region where V th1 &lt;V C1 &lt;V th2 +α, the transistors Q 4  and Q 5  operate, permitting current to flow through them. This current increases as the control voltage V C1  increases, and thus the gain decreases as the control voltage V C1  increases. In this state, since V C2 &lt;V th2 , almost no current flows through the transistors Q 7  and Q 8 . 
     Thus, in the region where V C1 &lt;V th2 +α, the gain characteristic curve T 3  of the variable-gain amplifier of the first embodiment coincides with the gain characteristic curve T 2  of the variable-gain amplifier of FIG.  16 . 
     In the region where V th2 +α&lt;V C1 , the transistors Q 3  and Q 6  are in an off state, and therefore through them flows only the current that leaks through their parasitic capacitance. Moreover, in this state, since V th2 &lt;V C2 , the transistors Q 7  and Q 8  operate, permitting current to flow through them. This current increases as the control voltage V C1  increases, and thus the current flowing through the input transistors Q 1  and Q 2  decreases as the control voltage V C1  increases. Accordingly, the levels of the signals output at the collectors of the input transistors Q 1  and Q 2  lower as the control voltage V C1  increases. As a result, the levels of the signals that leak through the parasitic capacitance of the transistors Q 3  and Q 6  decrease as the control voltage V C1  increases. In this way, the variable-gain amplifier of the first embodiment achieves sufficient gain attenuation even when high-frequency signals are fed in. Thus, the variable-gain amplifier of the first embodiment offers a wide input dynamic range even when high-frequency signals are fed in. 
     When the control voltage V C1  is made sufficiently high, the transistors Q 7  and Q 8  are brought into a saturated state. This makes the levels of the signals output at the collectors of the input transistors Q 1  and Q 2  as small as those of the signals that leak through the parasitic capacitance of the input transistors. 
     In formula (6) above, the value of α is usually so set that the value of V th2 +α is close to the level of the control voltage at which gain attenuation starts to be saturated in a conventional variable-gain amplifier when high-frequency signals are fed in (see FIG.  2 ). However, the value of α may be set to be smaller than the value so determined. 
     FIG. 3 shows the gain characteristic with respect to the control voltage V C1 , with different values of α. The gain characteristic curves T 5 , T 4 , and T 3  represent the gain characteristic curves observed when α=α 1 , α=α 2 , and α=α 3 , respectively. Here, α 1 &lt;α 2 &lt;α 3 , and it is assumed that, when α=α 3 , the value of V th2 +α is close to the level of the control voltage at which gain attenuation starts to be saturated. As will be clear from FIG. 3, the smaller the value of α, the higher the gain at which gain attenuation is started and the more steeply it is effected by the operation of the transistors Q 7  and Q 8 . That is, by making the value of a smaller, it is possible to heighten the gain at which the rate of gain attenuation with respect to the control voltage V C1  is switched, and also to increase the rate of gain attenuation with respect to the control voltage V C1  after the switching. 
     In the embodiment described above, the subsidiary control voltage V C2  is varied continuously according to the control voltage V C1  so as to fulfill the relationship of formula (6). However, it is also possible, as shown in FIG. 4, to vary the subsidiary control voltage V C2  stepwise according to the control voltage V C1  in the region where V th2 +α&lt;V C1 . Using the subsidiary control voltage V C2  varying stepwise in this way permits the transistors Q 7  and Q 8  to be controlled stepwise. In this case, the gain characteristic with respect to the control voltage V C1  is as shown in FIG.  5 . 
     This also makes it possible to achieve sufficient gain attenuation even when high-frequency signals are fed in, just as in a case where the subsidiary control voltage V C2  is varied continuously according to the control voltage V C1  so as to fulfill the relationship of formula (6). Moreover, by making the value of α smaller, it is possible to heighten the gain at which the rate of gain attenuation with respect to the control voltage V C1  is switched, and also to increase the rate of gain attenuation with respect to the control voltage V C1  after the switching. 
     In addition, since the subsidiary control voltage V C2  does not need to be varied continuously with respect to the control voltage V C1  so as to fulfill the relationship of formula (6), it is easy to produce the subsidiary control voltage V C2 . Moreover, in the region where V C1 &lt;V th2 +α, it is possible to reduce the subsidiary control voltage V C2  to zero. It is to be noted that, in the region where V th2 +α&lt;V C1 , the smaller the step width of the control voltage V C1  is made, the smoother the gain characteristic curve obtained, i.e., the closer to that shown in FIG.  3 . 
     Next, the variable-gain amplifier of a second embodiment of the invention will be described. FIG. 6 shows the configuration of the variable-gain amplifier of the second embodiment. It is to be noted that such circuit elements and signals as are found also in FIG. 16 are identified with the same reference numerals and symbols, and their explanations will not be repeated. 
     One end of a variable resistor  3  and one end of a variable resistor  4  are connected to the terminal to which the constant voltage V CC  is supplied. The other end of the variable resistor  3  is connected to the emitter of the input transistor Q 1 , and the other end of the variable resistor  4  is connected to the emitter of the input transistor Q 2 . 
     The resistances of the variable resistors  3  and  4  are controlled by the control voltage V C1 . FIG. 7 shows the resistance characteristic of the variable resistors  3  and  4  with respect to the control voltage V C1 . Here, the variable resistors  3  and  4  are assumed to have identical resistance characteristics. The maximum resistance R max  of the variable resistors  3  and  4  is so set as to fulfill the relationship represented by formula (7) below, where I p (R max ) represents the current that flows through the variable resistors  3  and  4  when their resistances equal R max . 
     
       
           V   CC   −R   max   ×I   p ( R   max )&lt;&lt; V   B2   −V   BE   (7) 
       
     
     By setting the maximum resistance R max  of the variable resistors  3  and  4  so as to fulfill the relationship of formula (7), it is possible to prevent the emitter potentials of the input transistors Q 1  and Q 2  from becoming higher than V B2 −V BE  when the control voltage V C1  is low. Thus, even when the control voltage V C1  is low, the current flowing through the input transistors Q 1  and Q 2  does not diminish in the region where V C1 &lt;V th2 +α. 
     On the other hand, in the region where V th2 +α&lt;V C1 , the resistances of the variable resistors  3  and  4  decrease steeply as the control voltage V C1  increases, and thus the current flowing through the variable resistors  3  and  4  increases steeply as the control voltage V C1  increases. As a result, the current flowing through the input transistors Q 1  and Q 2  decreases as the control voltage V C1  increases, and the levels of the signals output at the collectors of the input transistors Q 1  and Q 2  lower as the control voltage V C1  increases. Thus, the levels of the signals that leak through the parasitic capacitance of the transistors Q 3  and Q 6  decrease as the control voltage V C1  increases. 
     In this way, the variable-gain amplifier of the second embodiment exhibits the identical gain characteristic to that of the variable-gain amplifier of the first embodiment. That is, the variable-gain amplifier of the second embodiment achieves sufficient gain attenuation even when high-frequency signals are fed in. Thus, the variable-gain amplifier of the second embodiment offers a wide input dynamic range even when high-frequency signals are fed in. 
     Next, the variable-gain amplifier of a third embodiment of the invention will be described. FIG. 8 shows the configuration of the variable-gain amplifier of the third embodiment. It is to be noted that such circuit elements and signals as are found also in FIG. 16 are identified with the same reference numerals and symbols, and their explanations will not be repeated. 
     A variable voltage source  5  has its positive side connected to the emitter of the input transistor Q 1 , and has its negative side grounded. A variable voltage source  6  has its positive side connected to the emitter of the input transistor Q 2 , and has its negative side grounded. 
     The output voltages of the variable voltage sources  5  and  6  are controlled by a subsidiary control voltage V C2 . Moreover, it is assumed that, between the subsidiary control voltage V C2  and the control voltage V C1 , the relationship represented by formula (6) noted earlier holds. Here, however, as distinct from the variable-gain amplifier of the first embodiment, V th2  in formula (6) represents the threshold level of the subsidiary control voltage V C2  at which current starts flowing from the variable voltage sources  5  and  6 . 
     FIG. 9 shows the output voltage characteristic of the variable voltage sources  5  and  6  with respect to the control voltage V C1 . Here, the variable voltage sources  5  and  6  are assumed to have identical output voltage characteristics. 
     In the region where V C1 &lt;V th2 +α, the output voltages of the variable voltage sources  5  and  6  equal V B2 −V BE , and the emitter potentials of the input transistors remain equal to V B2 −V BE . Thus, the current flowing through the input transistors Q 1  and Q 2  does not decrease, and therefore no current flows out of the variable voltage sources  5  and  6 . 
     On the other hand, in the region where V th2 +α&lt;V C1 , the output voltages of the variable voltage sources  5  and  6  increase steeply, and the emitter potentials of the input transistors increase accordingly. As a result, the current flowing through the input transistors Q 1  and Q 2  decreases as the control voltage V C1  increases, and, to compensate for the decrease, current flows out of the variable voltage sources  5  and  6 . Thus, the levels of the signals output at the collectors of the input transistors Q 1  and Q 2  decrease as the control voltage V C1  increases, and accordingly the levels of the signals that leak through the parasitic capacitance of the transistors Q 3  and Q 6  lower as the control voltage V C1  increases. 
     In this way, the variable-gain amplifier of the third embodiment exhibits the identical gain characteristic to that of the variable-gain amplifier of the first embodiment. That is, the variable-gain amplifier of the third embodiment achieves sufficient gain attenuation even when high-frequency signals are fed in. Thus, the variable-gain amplifier of the third embodiment offers a wide input dynamic range even when high-frequency signals are fed in. 
     In the embodiments described thus far, in setting the subsidiary control voltage V C2 , no consideration is given to the alternating-current components included in the input voltage signals V IN1  and V IN2 . In practice, however, for example in a case where the input voltage signal V IN1  is a signal having a direct-current bias voltage added to an alternating-current component and the input voltage signal V IN2  is a signal including only a direct-current bias voltage, it is advisable to feed the transistor Q 7 , variable resistor  3 , or variable voltage source  5  with a subsidiary control voltage V C2 ′ obtained by compensating the subsidiary control voltage V C2  for the alternating-current component of the input voltage signal V IN1  and feed the transistor Q 8 , variable resistor  4 , or variable voltage source  6  with the subsidiary control voltage V C2 . 
     In the variable-gain amplifiers of the first to third embodiments described above, the two input transistors have their emitters connected together through a resistor. However, the present invention may be implemented with any other configuration. For example, it is also possible, in a variable-gain amplifier in which the emitters of two input transistors are both connected to a single constant current source, to provide a variable voltage source that supplies a voltage to the node at which the emitters of the input transistors are connected together. Providing a variable voltage source like this makes it possible to control the emitter potentials of the input transistors. This permits the collector current of the input transistors to be reduced, and thus makes it possible to achieve sufficient gain attenuation even when high-frequency signals are fed in. 
     Next, the variable-gain amplifier of a fourth embodiment of the invention will be described. FIG. 10 shows the configuration of the variable-gain amplifier of the fourth embodiment. It is to be noted that such circuit elements and signals as are found also in FIG. 19 are identified with the same reference numerals and symbols, and their explanations will not be repeated. 
     In the variable-gain amplifier of FIG. 10, the current sources provided in the variable-gain amplifier circuit A 1  are realized with a current mirror circuit that is composed of transistors Q 29 , Q 30 , and Q 33  and that outputs a bias current I A1 . That is, the constant current sources  21  and  22  in FIG. 19 are replaced with an NPN-type transistor Q 29  having its collector connected to the emitter of the transistor Q 21 , an NPN-type transistor Q 30  having its collector connected to the emitter of the transistor Q 22 , and an NPN-type transistor Q 33  having its base and collector connected to the bases of the transistors Q 29  and Q 30 . The emitters of the transistors Q 29 , Q 30 , and Q 33  are grounded. 
     Moreover, the variable-gain amplifier of FIG. 10 is provided with a differential amplifier circuit  11  that controls the collector current of the transistor Q 33 . The differential amplifier circuit  11  is composed of a PNP-type transistor Q 26  and a PNP-type transistor Q 27 . The emitters of the transistors Q 26  and Q 27  are connected together, and are connected to the collector of a PNP-type transistor Q 35 . The collector of the transistor Q 26  is grounded, and the collector of the transistor Q 27  is connected to the collector and base of the transistor Q 33 . 
     Furthermore, in the variable-gain amplifier of FIG. 10, the current sources provided in the variable-gain amplifier circuit A 2  are realized with a current mirror circuit that is composed of transistors Q 28 , Q 31 , and Q 32  and that outputs a bias current I A2 . That is, the constant current sources  20  and  23  in FIG. 19 are replaced with an NPN-type transistor Q 28  having its collector connected to the emitter of the transistor Q 20 , an NPN-type transistor Q 31  having its collector connected to the emitter of the transistor Q 23 , and an NPN-type transistor Q 32  having its base and collector connected to the bases of the transistors Q 28  and Q 31 . The emitters of the transistors Q 28 , Q 31 , and Q 32  are grounded. 
     Moreover, the variable-gain amplifier of FIG. 10 is provided with a differential amplifier circuit  12  that controls the collector current of the transistor Q 32 . The differential amplifier circuit  12  is composed of a PNP-type transistor Q 24  and a PNP-type transistor Q 25 . The emitters of the transistors Q 24  and Q 25  are connected together, and are connected to the collector of a PNP-type transistor Q 34 . The collector of the transistor Q 25  is grounded, and the collector of the transistor Q 24  is connected to the collector and base of the transistor Q 32 . 
     Furthermore, the variable-gain amplifier of FIG. 10 is provided with a current mirror circuit that supplies constant currents to the differential amplifier circuits  11  and  12 . This current mirror circuit is composed of transistors Q 34 , Q 35 , and Q 36 . The bases and collectors of all the transistors Q 34 , Q 35 , and Q 36  are connected to the terminal to which the constant voltage V CC  is supplied. The collector of the transistor Q 36  is grounded through constant current source  13 . 
     The bases of the transistors Q 24  and Q 26  are connected to the emitter of an NPN-type transistor Q 37 . The emitter of the transistor Q 37  is grounded through a resistor R 10 . The base and collector of the transistor Q 37  are connected together, and are connected to the bases of the transistors Q 12 , Q 14 , Q 17 , and Q 19  and also through a resistor R 9  to the terminal to which the constant voltage V CC  is supplied. 
     The base of the transistor Q 25  is connected to one end of a resistor R 1 , and the base of the transistor Q 27  is connected to the other end of the resistor R 1 . Also connected to the first end of the resistor R 1  is the emitter of an NPN-type transistor Q 11 , and the other end of the resistor R 1  is grounded through a resistor R 2 . The base and collector of the transistor Q 11  are connected together, and are connected to the terminal to which the control voltage V AGC  is supplied. 
     Next, the operation of the variable-gain amplifier of FIG. 10 configured as described above will be described. Let the base potential of the transistors Q 12 , Q 14 , Q 17 , and Q 19  be V bias1 , and the base potential of the transistors Q 24  and Q 26  be V bias2 . Between V bias1  and V bias2 , there is a potential difference equal to the base-emitter voltage of the transistor Q 37 . On the other hand, between the base potential of the transistors Q 15  and Q 16  and the base potential of the transistor Q 25 , there is a potential difference equal to the base-emitter voltage of the transistor Q 11 . Thus, if the resistances of the resistors R 1  and R 3  are equal, and the resistances of the resistors R 2  and R 4  are equal, the threshold level of the control voltage V AGC  at which the differential amplifier circuit composed of the transistors Q 14  and Q 15  and the differential amplifier circuit composed of the transistors Q 16  and Q 17  start gain attenuation is equal to the threshold level of the control voltage V AGC  at which the differential amplifier circuit  12  makes bias currents start flowing in the variable-gain amplifier circuit A 2 . Moreover, the threshold level of the control voltage V AGC  at which the differential amplifier circuit composed of the transistors Q 12  and Q 13  and the differential amplifier circuit composed of the transistors Q 18  and Q 19  start gain attenuation is equal to the threshold level of the control voltage V AGC  at which the differential amplifier circuit  11  makes bias currents almost stop flowing in the variable-gain amplifier circuit A 1 . Specifically, the gain characteristic and bias current characteristic with respect to the control voltage V AGC  are as shown in FIGS. 11A and 11B, respectively. 
     When V AGC &lt;V B1 , the base potentials of the transistors Q 13 , Q 15 , Q 16 , and Q 18  are lower than V bias1 , and therefore neither of the variable-gain amplifier circuits A 1  and A 2  perform gain attenuation. Thus, the variable-gain amplifier offers a high gain. Moreover, when V AGC &lt;V B1 , if only the base potentials of the transistors Q 12  to Q 19  are considered, both the variable-gain amplifier circuits A 1  and A 2  can be said to be operating, but, in reality, almost no bias current I A2  flows, and therefore only the variable-gain amplifier circuit A 1  is operating effectively, offering good noise figure characteristics. 
     When V B1 &lt;V AGC , as the control voltage V AGC  increases, the gain G A1  of the variable-gain amplifier circuit A 1  is attenuated, and the bias current I A1  decreases. Thus, the operation of the variable-gain amplifier circuit A 1  heads for a halt. Simultaneously, the bias current I A2  increases, and thus the current flowing through the transistors Q 28  and Q 31  increases, making the variable-gain amplifier circuit A 2  start operating. When the control voltage V AGC  further increases until V B2 &lt;V AGC , almost no bias current I A1  flows. Thus, the variable-gain amplifier circuit A 1  stops operating, and now only the variable-gain amplifier circuit A 2  is operating. In this state, the variable-gain amplifier circuit A 1  does not affect the G total  of the variable-gain amplifier, offering good intermodulation distortion characteristics. 
     Moreover, since only the variable gain amplifier circuit that is currently operating draws current through the output load resistors R 5  and R 6 , the voltage drops across the output load resistors R 5  and R 6  do not become unduly large. This prevents the transistors provided within the variable-gain amplifier from being saturated and ceasing to operate. Moreover, the bias currents I A1  and I A2  are not constant but are varied according to the control voltage V AGC  so as to be smaller than the bias current I C  in a conventional variable-gain amplifier. Thus, it is possible to reduce power consumption compared with the variable-gain amplifier of FIG.  19 . Moreover, there is secured a range of the control voltage V AGC  (V B1 &lt;V AGC &lt;V B2 ) in which, when the variable-gain amplifier circuits are switched from one to the other, the variable-gain amplifier circuit that is going to stop being operated and the variable-gain amplifier circuit that is going to start being operated both operate concurrently. This prevents the gain of the variable-gain amplifier from lowering when which variable-gain amplifier to operate is switched. 
     In the variable-gain amplifier of FIG. 10 described above, for simplicity&#39;s sake, two variable-gain amplifier circuits A 1  and A 2  are connected in parallel. In practice, however, to make the gain characteristic of the variable-gain amplifier with respect to the control voltage V AGC  smooth, it is preferable to connect more variable-gain amplifier circuits in parallel. FIG. 12 shows a variable-gain amplifier according to the invention in which a number of variable-gain amplifier circuits are connected in parallel. It is to be noted that such circuit elements and signals as are found also in FIG. 10 are identified with the same reference numerals and symbols, and their explanations will not be repeated. 
     The variable-gain amplifier of FIG. 12 is provided with a variable-gain amplifier circuit A 1 , a variable-gain amplifier circuit A 2 , variable-gain amplifier circuits A 3  to An each configured in the same manner as the variable-gain amplifier circuit A 1 , voltage shift circuits B 2  to Bn that supply the variable-gain amplifier circuits A 2  to An individually with control voltages, and a current control circuit  14  that controls the bias currents for the variable-gain amplifier circuits A 1  to An individually. The variable-gain amplifier circuits A 1  to An are connected in parallel. As described above, according to the present invention, only the variable-gain amplifier circuit that is currently operating draws current through the output load resistors, and thus the voltage drops across the output load resistors are small. This makes the present invention especially useful in variable-gain amplifiers having a number of variable-gain amplifier circuits connected in parallel. 
     Next, the variable-gain amplifier of a fifth embodiment of the invention will be described. FIG. 13 shows the configuration of the variable-gain amplifier of the fifth embodiment. It is to be noted that such circuit elements and signals as are found also in FIG. 10 are identified with the same reference numerals and symbols, and their explanations will not be repeated. 
     An A/D conversion circuit  15  converts the control voltage V AGC  as represented by an analog value into a voltage as represented by a digital value, and outputs the result to a voltage shift operation circuit  16 . The voltage shift operation circuit  16  shifts, by different predetermined values, the voltage as represented by the digital value output from the A/D conversion circuit  15  so as to output different voltages V D1  and V D2  as represented by digital values to a D/A conversion circuit  17 . The D/A conversion circuit  17  converts the voltages V D1  and V D2  as represented by the digital values into voltages V A1  and V A2  as represented by analog values, respectively, and outputs the voltage V A1  to the base of the transistor Q 27  and the voltage V A2  to the base of the transistor Q 25 . 
     Here, the predetermined values by which the voltage shift operation circuit  16  shifts the voltage fed to it to calculate the voltages V D1  and V D2  as represented by digital values are so set that the threshold level of the control voltage V AGC  at which the differential amplifier circuit composed of the transistors Q 14  and Q 15  and the differential amplifier circuit composed of the transistors Q 16  and Q 17  start gain attenuation is equal to the threshold level of the control voltage V AGC  at which the differential amplifier circuit  12  makes the bias current I A2  start flowing in the variable-gain amplifier circuit A 2 , and that the threshold level of the control voltage V AGC  at which the differential amplifier circuit composed of the transistors Q 12  and Q 13  and the differential amplifier circuit composed of the transistors Q 18  and Q 19  start gain attenuation is equal to the threshold level of the control voltage V AGC  at which the differential amplifier circuit  11  makes the bias current I A1  almost stop flowing in the variable-gain amplifier circuit A 1 . In this way, the variable-gain amplifier of the fifth embodiment operates in a similar manner to the variable-gain amplifier of the fourth embodiment, and in addition it operates with smaller errors in the bias currents I A1  and I A2  than in the variable-gain amplifier of the fourth embodiment. 
     Next, the variable-gain amplifier of a sixth embodiment of the invention will be described. FIG. 14 shows the configuration of the variable-gain amplifier of the sixth embodiment. It is to be noted that such circuit elements and signals as are found also in FIG. 13 are identified with the same reference numerals and symbols, and their explanations will not be repeated. 
     An A/D conversion circuit  15  converts the control voltage V AGC  as represented by an analog value into a voltage as represented by a digital value, and outputs the result to a voltage shift operation circuit  16 . The voltage shift operation circuit  16  shifts, by different predetermined values, the voltage as represented by the digital value output from the A/D conversion circuit  15  so as to output different voltages V D1 ′ and V D2 ′ as represented by digital values to a D/A conversion circuit  17 ′. The D/A conversion circuit  17 ′ is provided with voltage-to-current conversion amplifiers (not shown) so that it first converts the voltages V D1 ′ and V D2 ′ as represented by the digital values into voltages as represented by analog values, respectively, then converts, with the voltage-to-current conversion amplifiers (not shown), those voltages as represented by the analog values into currents I A1  and I A2  as represented by analog values, and then outputs the current I A1  to the collector of the transistor Q 33  and the current I A2  to the collector of the transistor Q 32 . 
     Here, the predetermined values by which the voltage shift operation circuit  16  shifts the voltage fed to it to calculate the voltages V D1 ′ and V D2 ′ as represented by digital values are so set that the threshold level of the control voltage V AGC  at which the differential amplifier circuit composed of the transistors Q 14  and Q 15  and the differential amplifier circuit composed of the transistors Q 16  and Q 17  start gain attenuation is equal to the threshold level of the control voltage V AGC  at which the bias current I A2  starts flowing in the variable-gain amplifier circuit A 2 , and that the threshold level of the control voltage V AGC  at which the differential amplifier circuit composed of the transistors Q 12  and Q 13  and the differential amplifier circuit composed of the transistors Q 18  and Q 19  start gain attenuation is equal to the threshold level of the control voltage V AGC  at which the bias current I A1  almost stops flowing in the variable-gain amplifier circuit A 1 . In this way, the variable-gain amplifier of the sixth embodiment operates in a similar manner to the variable-gain amplifiers of the fourth and fifth embodiments, and in addition it operates with smaller errors in the bias currents I A1  and I A2  than in the variable-gain amplifier of the fourth embodiment. 
     Now, practical examples of the voltage shift operation circuit  16  provided in the variable-gain amplifiers of the fifth and sixth embodiments described above will be described. FIG. 15A shows the voltage shift operation circuit  16  that is so configured as to perform different operations on a parallel basis, and FIG. 15B shows the voltage shift operation circuit  16  that is so configured as to perform different operations on a time division basis. 
     First, the voltage shift operation circuit shown in FIG. 15A will be described. The voltage as represented by the digital value output from the A/D conversion circuit  15  is fed to a terminal  60 . An operation circuit  61  performs digital operation to subtract a predetermined shift value ΔV 1  from the value of the voltage fed to the terminal  60 , and outputs the result of the operation to a terminal  63 . Moreover, an operation circuit  62  performs digital operation to subtract a predetermined shift value ΔV 2  from the value of the voltage fed to the terminal  60 , and outputs the result of the operation to a terminal  64 . 
     Next, the voltage shift operation circuit shown in FIG. 15B will be described. The voltage as represented by the digital value output from the A/D conversion circuit  15  is fed to a terminal  65 . A control circuit  67  controls the contact state of a switch  66 . This voltage shift operation circuit performs operation through the following procedure. First, the switch  66  is turned to a contact “a.” In this state, an operation circuit  68  performs digital operation to subtract a predetermined shift value ΔV 1  from the value of the voltage fed to the terminal  65 , and outputs the result of the operation to a terminal  69 . Thereafter, the switch  66  is turned to a contact “b.” In this state, the operation circuit  68  performs digital operation to subtract the predetermined shift value ΔV 1  from the value of the voltage that the operation circuit  68  itself has just output, that is, it performs digital operation to subtract twice the predetermined shift value ΔV 1  from the value of the voltage fed to the terminal  65 . Thereafter, the switch  66  is turned back to the contact “a” to end the operation. This configuration requires only one operation circuit, and thus helps reduce the circuit scale. This configuration is especially useful in a case where a number of variable-gain amplifier circuits are provided as described later. 
     When the voltage shift operation circuit  16  is so configured as to perform different operations on a time division basis as shown in FIG. 15B, it is advisable to configure also the D/A conversion circuit  17  or  17 ′ so as to perform conversion on a time division basis. This makes it possible to reduce also the circuit scale of the D/A conversion circuit  17  or  17 ′. 
     In the variable-gain amplifiers of the fifth and sixth embodiments described above, for simplicity&#39;s sake, two variable-gain amplifier circuits are connected in parallel. In practice, however, to make the gain characteristic with respect to the control voltage V AGC  smooth, it is preferable to connect more variable-gain amplifier circuits in parallel. Moreover, to reduce the error in the voltage fed to the bases of the transistors Q 13  and Q 18 , the voltage shift circuit composed of the resistors R 3  ad R 4  may be replaced with a voltage shift circuit composed of an A/D conversion circuit, a voltage shift operation circuit, and a D/A conversion circuit. 
     In the variable-gain amplifiers of the fourth to sixth embodiments described above, the bias currents I A1  and I A2  are controlled according to the control voltage V AGC . However, the present invention may be implemented with any other configuration. For example, it is also possible to control the bias currents I A1  and I A2  according to a control voltage fed from outside which is independent of the control voltage V AGC .