Patent Publication Number: US-9851921-B1

Title: Flash memory chip processing

Description:
RELATED APPLICATIONS 
     This application claims priority from U.S. provisional patent Ser. No. 62/188,672, filed on Jul. 5, 2015, which is incorporated herein by reference. 
    
    
     BACKGROUND 
     Nonvolatile flash memory devices (e.g. 2D NAND Flash or 3D NAND) store information in the form of charge in a flash memory cell. A flash memory cell has a transistor with an additional floating metal gate between the substrate and the transistors gate or a trapping area or any other mechanism to allow charge storage. The charge is stored in the transistor and is injected during an operation known as programming. The charge may be removed during an operation known as an erase operation. 
     As the charge in the transistor may vary contiguously, it is possible to store more than just one bit per flash transistor by using several charge levels to symbolize different sequences of bits. 
       FIG. 1  illustrates a prior art voltage level distribution  100  for a 3pbc (bits per cell) flash memory cell. The voltage level distribution includes eight lobes  101 - 108 . Each lobe represents a 3-bit value. 
     The voltage level distributions of  FIG. 1  illustrates non-overlapping lobes, however this is only schematic, and in practical cases the lobes may overlap. For NAND Flash devices, a stressed page, may introduce greater overlap between lobes than a new page, since after many program/erase (P/E) cycles or read disturb cycles the stress may introduce different noise sources. After a long duration, every lobe may have a larger standard deviation (std) and may have a different mean location. These effects are also known as retention. 
     The 3 bit-per-cell (bpc) cell includes a most significant bit (MSB), a central significant bit (CSB) and a least significant bit (LSB). A physical page of flash memory module may store three logical pages. This physical page is programmed one logical page after the other. The programming includes various types of programming such as MSB programming, CSB programming and LSB programming. Alternatively, all 3 pages in a row may be programmed at once in either a single stage or in several stages. For example, 3 stages may be used for programming such that all page types are associated with each stage. The logical pages are read by applying various types of read operations such as MSB read (e.g. in which a MSB threshold  111  and  115  are used), CSB read (in which two CSB thresholds  112   114  and  116  are used) and LSB read (in which four LSB thresholds  113  and  117  are used). 
       FIG. 2  shows similar distributions for the case of 2 bpc devices. Four lobes  201 ,  202 ,  203  and  204  as well as MSB threshold  212  and two LSB thresholds  211  and  312 . 
     As mentioned, the lobe distributions are not constant throughout the life of the flash and change under various stress conditions. With retention, the distribution become larger and shift towards the erase level. The higher the distribution the larger the shift. This effectively shrinks the effective working window. Both the shrinkage of the window and the fattening of the distributions contribute to the increase in number of errors after performing a page read.  FIG. 3  illustrates these effects. Spaced apart lobes  301  overlap and widen due to retention to provide threshold voltage distribution  302 . 
     These effects become significantly worse as the block P/E cycles increase and as the NAND Flash memory technology node shrink. 
     These stress factors (Node shrink, number of layers in 3D NAND, endurance retention, read disturb) affect reliability due to errors incurred by overlap of lobes. To overcome these issues more advanced memory controllers use advanced ECC and DSP algorithms to overcome the errors incurred by these errors. 
       FIG. 4  shows a typical prior art NAND flash string and the reading circuitry associated with it. A string is duplicated many times (say 147456 times) in a block and contains several (say 86) Flash memory cells. 
     Each of the flash memory cells  420  of a string is associated with a different wordline which connects all of the corresponding flash memory cells in the other strings of the block. When a block is chosen, each string is connected to a corresponding bitline by turning on the Bit Line Select and the Ground Select transistors. When a read operation is performed, a sense amplifier  440  is connected to the bit-line and after allowing some time (say 40 uS) for the bit-line voltage to settle, the result is stored by a latch  450 . Latch  450  is activated by latch enable (LE) signal.  FIG. 4  illustrates a string of thirty two flash memory cells, positioned between a bit line select transistor (for selecting the string) and a ground select transistor (for grounding the string). 
     In order to measure the charge in a certain cell within a string, all other cells are switched on by applying a high voltage on their gates (given by Vbias) and a comparison voltage, Vth, is applied to the gate of the selected cell. In  FIG. 4  the third flash memory cell  420 ( 3 ) is selected and wordline3 is provided with Vth. Other flash memory cells (1, 2 and 4-32) are fed with Vbias. 
     If the cell is charged and Vth is not high enough, the gate will not allow current to flow and the sense-amplifier will output a “0”. On the other hand, if the cell is not charge or Vth is high enough, current will flow and the sense-amplifier will output a “1”. Different schemes may exist where the cell being samples is biased with a constant voltage (say Vcc) but in the sense-simplifier a comparison against a reference string is performed which reference value may be determined by some external voltage, Vth. 
     The bit line and each flash memory cells have certain impedance and capacitance that need to be charged in order to converge to a desired voltage level. This is illustrated in  FIG. 5 . Curve  510  illustrate the charging of the capacitance of the bit line and/or the selected flash memory cell once the threshold voltage converges and stabilizes to a first target value  520  a single sampling is performed by the latch  450 . 
     The above sampling technique holds when a bit may be obtained only through a single threshold comparison. When more than a single threshold comparison is required, the above procedure may be performed for each threshold and the results may then be combined. 
     SUMMARY 
     According to an embodiment of the invention there may be provided a non-transitory computer readable medium that stores instructions that once executed by a computer cause the computer to sample a flash memory cell that belongs to a die, by attempting, during a gate voltage change period, to change a value of a gate voltage of the flash memory cell from a first value to a second value; sampling, by a sampling circuit that belongs to the die, an output signal of the flash memory cell multiple times during the voltage gate change period to provide multiple samples; defining a given sample of the multiple samples as a data sample that represents data stored in the flash memory cell; and determining, by a processor that belongs to the die, a reliability of the data sample based on one or more samples of the multiple samples that differ from the given sample. The processor may belong to the sampling circuit or may not belong to the sampling circuit. 
     According to an embodiment of the invention there may be provided a semiconductor die that may include a processor, a sampling circuit and a flash memory array; wherein the sampling circuit is configured to (a) attempt, during a gate voltage change period, to change a value of a gate voltage of the flash memory cell from a first value to a second value; and (b) sample an output signal of the flash memory cell multiple times during the voltage gate change period to provide multiple samples; wherein the processor is configured to define a given sample of the multiple samples as a data sample that represents data stored in the flash memory cell; and to determine a reliability of the data sample based on one or more samples of the multiple samples that differ from the given sample. 
     According to an embodiment of the invention there may be provided a method for sampling a flash memory cell that belongs to a die, the method may include attempting, during a gate voltage change period, to change a value of a gate voltage of the flash memory cell from a first value to a second value; sampling, by a sampling circuit that belongs to the die, an output signal of the flash memory cell multiple times during the voltage gate change period to provide multiple samples; defining a given sample of the multiple samples as a data sample that represents data stored in the flash memory cell; and determining, by a processor that belongs to the die, a reliability of the data sample based on one or more samples of the multiple samples that differ from the given sample. 
     The determining of the reliability may include searching for a difference between the multiple samples. 
     The determining of the reliability may include assigning a reliability score that is responsive to an order, within the multiple samples, of a first sample that differs from a preceding sample. 
     The method may include assigning a reliability score that represent a decrease in reliability with an increase in the order of the first sample. 
     The determining of the reliability may include assigning a first reliability score when all the samples have a same value; and assigning a second reliability score when one of the multiple samples differs from another sample; wherein the second reliability score is indicative of a lower reliability than the first reliability score. 
     The method further may include outputting, to a flash memory controller located outside the die, information about the reliability of the data sample. 
     The method may include decoding, by the processor, the data sample; wherein the decoding may include utilizing information, generated by the processor, related to the reliability of the data sample. 
     The method may include receiving, by the processor error correction information that was generated outside the die and relates to the data sample; and decoding, by the processor, the data sample; wherein the decoding may include (a) utilizing information, generated by the processor, related to the reliability of the data sample and (b) utilizing the error correction information. 
     The method may include controlling an execution of operations applied on the data sample in response to the reliability of the data sample. 
     The method may include preventing a copyback operation when the reliability of the data sample is below a reliability threshold. 
     The method may include selecting between an execution of a copyback operation and a provision of the data sample to an external flash memory controller based upon the reliability of the data sample. 
     The method may include determining an allocation of the flash memory cell based upon the reliability of the data sample. 
     According to an embodiment of the invention there may be provided a method for sampling a flash memory cell that belongs to a die, the method may include performing a first attempt, during a first gate voltage change period, to change a value of a gate voltage of the flash memory cell from a first value to a second value; sampling, by a sampling circuit that belongs to the die, an output signal of the flash memory cell multiple times during the first voltage gate change period to provide multiple first samples; defining a first given sample of the first multiple samples as a first data sample that represents data stored in the flash memory cell; determining, by a processor that belongs to the die, a reliability of the first data sample based on one or more samples of the first multiple samples that differ from the first given sample; performing a second attempt, during a second gate voltage change period, to change a value of a gate voltage of the flash memory cell from a first intermediate value to a third value; wherein the second attempt starts before a completion of the first attempt and when the gate voltage of the flash memory cell reached the first intermediate value; defining a second given sample of the second multiple samples as a second data sample that represents the data stored in the flash memory cell; and determining, by the processor, a reliability of the second data sample based on one or more samples of the second multiple samples that differ from the second given sample. 
     According to an embodiment of the invention there may be provided a non-transitory computer readable medium that stores instructions that once executed by a computer cause the computer to perform a first attempt, during a first gate voltage change period, to change a value of a gate voltage of the flash memory cell from a first value to a second value; sample an output signal of the flash memory cell multiple times during the first voltage gate change period to provide multiple first samples; define a first given sample of the first multiple samples as a first data sample that represents data stored in the flash memory cell; determine a reliability of the first data sample based on one or more samples of the first multiple samples that differ from the first given sample; perform a second attempt, during a second gate voltage change period, to change a value of a gate voltage of the flash memory cell from a first intermediate value to a third value; wherein the second attempt starts before a completion of the first attempt and when the gate voltage of the flash memory cell reached the first intermediate value; define a second given sample of the second multiple samples as a second data sample that represents the data stored in the flash memory cell; and determine a reliability of the second data sample based on one or more samples of the second multiple samples that differ from the second given sample. 
     According to an embodiment of the invention there may be provided a semiconductor die that may include a processor, a sampling circuit and a flash memory array; wherein the sampling circuit is configured to (a) perform a first attempt, during a first gate voltage change period, to change a value of a gate voltage of the flash memory cell from a first value to a second value; (b) sample an output signal of the flash memory cell multiple times during the first voltage gate change period to provide multiple first samples; wherein the processor is configured to (a) define a first given sample of the first multiple samples as a first data sample that represents data stored in the flash memory cell; (b) determine a reliability of the first data sample based on one or more samples of the first multiple samples that differ from the first given sample; (c) perform a second attempt, during a second gate voltage change period, to change a value of a gate voltage of the flash memory cell from a first intermediate value to a third value; wherein the second attempt starts before a completion of the first attempt and when the gate voltage of the flash memory cell reached the first intermediate value; (d) define a second given sample of the second multiple samples as a second data sample that represents the data stored in the flash memory cell; and (e) determine a reliability of the second data sample based on one or more samples of the second multiple samples that differ from the second given sample. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The subject matter regarded as the invention is particularly pointed out and distinctly claimed in the concluding portion of the specification. The invention, however, both as to organization and method of operation, together with objects, features, and advantages thereof, may best be understood by reference to the following detailed description when read with the accompanying drawings in which: 
         FIG. 1  illustrates a prior art threshold voltage distribution; 
         FIG. 2  illustrates a prior art threshold voltage distribution; 
         FIG. 3  illustrates a prior art threshold voltage distribution; 
         FIG. 4  illustrates a string of flash memory cells; 
         FIG. 5  illustrates a prior art sampling process; 
         FIG. 6  illustrates a sampling process according to an embodiment of the invention; 
         FIG. 7  illustrates a sampling process according to an embodiment of the invention; 
         FIG. 8  illustrates a sampling buffers according to an embodiment of the invention; 
         FIG. 9  illustrates a method according to an embodiment of the invention; 
         FIG. 10  illustrates a sampling process according to an embodiment of the invention; 
         FIG. 11  illustrates a die and a flash memory controller according to an embodiment of the invention; 
         FIG. 12  illustrates a method according to an embodiment of the invention 
         FIG. 13  illustrates a content of a page according to an embodiment of the invention; and 
         FIG. 14  illustrates a method according to an embodiment of the invention; 
         FIG. 15  illustrates a method according to an embodiment of the invention; and 
         FIG. 16  illustrates a method according to an embodiment of the invention. 
     
    
    
     DETAILED DESCRIPTION OF THE DRAWINGS 
     In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, it will be understood by those skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known methods, procedures, and components have not been described in detail so as not to obscure the present invention. 
     The subject matter regarded as the invention is particularly pointed out and distinctly claimed in the concluding portion of the specification. The invention, however, both as to organization and method of operation, together with objects, features, and advantages thereof, may best be understood by reference to the following detailed description when read with the accompanying drawings. 
     It will be appreciated that for simplicity and clarity of illustration, elements shown in the figures have not necessarily been drawn to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements for clarity. Further, where considered appropriate, reference numerals may be repeated among the figures to indicate corresponding or analogous elements. 
     Because the illustrated embodiments of the present invention may for the most part, be implemented using electronic components and circuits known to those skilled in the art, details will not be explained in any greater extent than that considered necessary as illustrated above, for the understanding and appreciation of the underlying concepts of the present invention and in order not to obfuscate or distract from the teachings of the present invention. 
     Any reference in the specification to a method should be applied mutatis mutandis to a system capable of executing the method and should be applied mutatis mutandis to a non-transitory computer readable medium that stores instructions that once executed by a computer result in the execution of the method. 
     Any reference in the specification to a system should be applied mutatis mutandis to a method that may be executed by the system and should be applied mutatis mutandis to a non-transitory computer readable medium that stores instructions that may be executed by the system. 
     Any reference in the specification to a non-transitory computer readable medium should be applied mutatis mutandis to a system capable of executing the instructions stored in the non-transitory computer readable medium and should be applied mutatis mutandis to method that may be executed by a computer that reads the instructions stored in the non-transitory computer readable medium. 
     The following invention presents a few schemes for obtaining more than a single bit sense output per cell, in order to allow soft information to be outputted. In addition, this invention also presents methods for internally utilizing this soft information to allow outputting only hard information from the NAND but with higher reliability. 
     The terms “sample”, “sampling point”, “latching point” and “latch” are used in an interchangeable manner. 
     The terms “process” and “method” are used in an interchangeable manner. 
     According to an embodiment of the invention a die that includes flash memory cells (such as NAND flash memory cells) includes a processor such as an internal sampling processor. 
     The processor may be configured to obtain “soft” samples regarding the state of the device. This enabling better reliability at the decoder. 
     The internal soft sampling schemes described below have advantages over external “soft” sampling scheme managed by a NAND controller ASIC. 
     It is shown that internal soft information can be generated without requiring additional threshold sampling times. This saves a considerable latency incurred by “soft” sampling in an external controller. For example, in an external controller “soft” sampling may incur 7 or 31 NAND read operations, each requiring 90 uS for the read operation and additional data transfer time. However, the suggested methods involve an internal soft sampling operation that is performed within a single read operation (90 uS) and then only relevant data need to be output (only equivalent to 3 or 5 reads). 
     Semi-Soft Sampling 
       FIGS. 6 and 7  illustrate a sampling process according to an embodiment of the invention. 
     In  FIG. 6  there are four samples and in  FIG. 7  there are more than four samples. The number of samples may be two or more, the spacing (time difference) between different samples may be the same but one or more spacing may differ from one or more other spacing. 
     Curve  510  of  FIG. 6  illustrates that multiple samples are taken at multiple latching points  541 ,  542  and  543  prior to full stabilization of the threshold voltage. An additional sample is taken at a last latching point  544 —when the threshold voltage is stabilized—reaches first target value  520 . 
     Curve  710  of  FIG. 7  illustrates an initial sampling point  741  followed by a plurality of additional sampling points  742 - 729 . 
     The samples may be used to obtain semi-soft information. The sense amplifiers of a row may be latched several times prior to full stabilization. 
     Depending on the sampling time, the sampling point can be referenced to a different gate voltage, thus equivalent to sampling with different thresholds. 
     Regardless of the actual voltage that is being sampled, it is clear that NAND strings that are latched (change their value) early on to their final values are likely to be more reliable than those that were only latched (changed their value) during the final stages. Therefore, the method can assign different reliability values depending on when the latched signals reached their final values—when a change occurred (or at an absence of change—the first sample may be regarded as very reliable). 
     One method of doing this is by holding a number of latch buffers. 
       FIG. 8  depicts multiple buffers according to an embodiment of the invention. 
     The buffers include an Initial Value Buffer ( 1001 ) that holds the data samples and Counter Buffers ( 1002 - 1003 ) that hold reliability information such as a reliability indicator. Each bit (bits  1001 ( 1 )- 1001 (K) of initial value buffer  1001 ; bits  1002 ( 1 )- 1002 (K) of counter buffer  1003  and bits  1003 ( 1 )- 1003 (K) of counter buffer  1003 ) in each of the buffers corresponds to a different NAND string and is intended to latch data which is a function of the corresponding NAND string sense amplifier value. The number of counter buffers is equal to the upper integer log 2 value of the number of sampling points. For example, if 4 sampling points are intended till gate stabilization, then we will use 2 counter buffers. 
     The latching procedure ( 1400 ) performed by the acquisition processor is illustrated in  FIG. 9  and includes: 
     Set Ref_Count to Max_Val and set target gate voltage. ( 1401 ). 
     On first latch occasion, the sense amplifier values are latched into the Initial Value Buffer ( 1401 ) and all Counter Buffers are set to Ref_Count. ( 1402 ). 
     Decrement Ref_Count. ( 1403 ). 
     On latch occasion compare corresponding sense amplifier with Initial Value Buffer and latch Ref_Count to Counter Buffers and the sense amplifier to the Initial Value Buffer only at locations corresponding to disagreeing values. ( 1404 ) 
     If Ref_Count&gt;0 return to step  1403 . ( 1405 ). 
     This latching procedure can be further extended to the case where more than a single threshold voltage is used. This is done by adding following steps: 
     Update a new set of buffers (Initial value buffer, new one for each threshold) intended to store intermediate threshold sampling results according to the Initial Value Buffer. ( 1406 ). 
     Set Ref_Count to Max_Val and next gate threshold. ( 1407 ). 
     On first latch occasion, the sense amplifier values are latched into the new Initial Value Buffer ( 1001 ). All Counter Buffers retain their previous value. ( 1408 ) Decrement Ref_Count. ( 1409 ). 
     On latch occasion compare corresponding sense amplifier with new Initial Value Buffer and latch minimum value of Ref_Count and current values of corresponding Counter Buffers to Counter Buffers and the sense amplifier to the new Initial Value Buffer only at locations corresponding to disagreeing values. ( 1410 ). 
     If Ref_Count&gt;0 return to step  1409 . ( 1411 ). 
     Update a new set of buffers intended to store intermediate threshold sampling results according to the Initial Value Buffer. ( 1412 ). 
     If another threshold needs to be updated, go to step  1407 . ( 1413 ) 
     The procedure so far mainly considered the case where the final setting voltage of the gate is the same as the reference voltage. However, we can also set the final setting voltage of the gate to be above the actual reference voltage such that the gate voltage crosses the reference voltage, starting from below and ending at a higher point. In that case, it is no longer correct to say that the earlier the sense amplifier reads are stabilized the more reliable the read is. In fact, now, the furthest the voltages stabilize compared to the point in time the gate voltage reaches the reference voltage, the more reliable the read is. 
     Thus, the following latching procedure can be applied: 
     The latching procedure ( 1400 ′) performed by the acquisition processor is illustrated in  FIG. 16  and includes: 
     Set Ref_Count to Max_Val and set target gate voltage. ( 1401 ). 
     On first latch occasion, the sense amplifier values are latched into the Initial Value Buffer ( 1401 ) and all Counter Buffers are set to Ref_Count. ( 1402 ). 
     Decrement Ref_Count. ( 1403 ). 
     On latch occasion compare corresponding sense amplifier with Initial Value Buffer and latch Ref_Count-Cross_Value to Counter Buffers and the sense amplifier to the Initial Value Buffer only at locations corresponding to disagreeing values. ( 1404 ′) 
     If Ref_Count&gt;0 return to step  1403 . ( 1405 ). 
     Note that the latched value now has a sign which indicates the hard decision value of the read. This signed value replaces the need to use the initial Value buffer for obtaining the read result sign. 
     This latching procedure can be further extended to the case where more than a single threshold voltage is used. This is done by adding following steps: 
     a. Update a new set of buffers (Initial value buffer, new one for each threshold) intended to store intermediate threshold sampling results according to the Initial Value Buffer. ( 1406 ). 
     b. Set Ref_Count to Max_Val and next gate threshold. ( 1407 ). 
     c. On first latch occasion, the sense amplifier values are latched into the new Initial Value Buffer ( 1001 ). All Counter Buffers retain their previous value. ( 1408 ) 
     d. Decrement Ref_Count. ( 1409 ). 
     e. On latch occasion compare corresponding sense amplifier with new Initial Value Buffer and latch minimum value of Ref_Count and current values of corresponding Counter Buffers to Counter Buffers and the sense amplifier to the new Initial Value Buffer only at locations corresponding to disagreeing values. ( 1410 ).
 
f. If Ref_Count&gt;0 return to step  1409 . ( 1411 ).
 
g. Update a new set of buffers intended to store intermediate threshold sampling results according to the Initial Value Buffer. ( 1412 ).
 
h. If another threshold needs to be updated, go to step  1407 . ( 1413 )
 
i. Combine all Initial Value Buffers to a single Value buffer using a table ( 1414 ). For example, for reading the middle page in  FIG. 1 , 3 thresholds are used, and assuming that the above scheme is used to read threshold one after the other, we can use the following table-describing the initial value buffer.
 
     
       
         
           
               
               
               
               
               
             
               
                   
                   
               
               
                   
                 A 
                 B 
                 C 
                 Final 
               
               
                   
                   
               
             
            
               
                   
                 0 
                 0 
                 0 
                 0 
               
               
                   
                 0 
                 0 
                 1 
                 1 
               
               
                   
                 0 
                 1 
                 0 
                 1 or 0 
               
               
                   
                 0 
                 1 
                 1 
                 0 
               
               
                   
                 1 
                 0 
                 0 
                 1 or 0 
               
               
                   
                 1 
                 0 
                 1 
                 1 
               
               
                   
                 1 
                 1 
                 0 
                 1 or 0 
               
               
                   
                 1 
                 1 
                 1 
                 1 
               
               
                   
                   
               
            
           
         
       
     
     It should be noted that here as well we can adapt the procedure to the case where the final gate voltage is set above the reference voltage. This is done by modifying step  10  such that we latch the minimum of Ref_Count−Cross_value and current counter buffers value only if abs(Ref_Count−Cross_value) is smaller than abs(current counter buffers). We need to save in the end the value of the sign that is latched 
     At the end of this process the bit value is stored in the new set of buffers intended to store intermediate threshold and the reliability score is stored at the Counter Buffers. These buffers can now be output to an external controller to be used during soft decoding. 
     In a nut shell, a data storing buffer such as initial value buffer  101  may store the data sampled from multiple flash memory cells during an initial sample (or any other selected sample) while one or more other buffers store reliability information such as a sample in which the value of a flash memory cell changed. 
       FIG. 11  illustrates die  900  and a flash memory controller  999  according to an embodiment of the invention. 
     The die  900  includes flash memory array  940 , sense amplifiers  930 , latches  920 , buffers  950  and processor  910 . 
     Sense amplifiers  930 , buffers  950  and latches  920  form a sampling circuit. The sampling circuit may include processor  920  but this is not necessarily so. 
     Processor  920  may be a sampling processor but may have other functionalities such as decoding (see decoder  912 ). 
     Processor  920  may determine the value of gate thresholds. 
     Buffers  950  may include buffers  1001 ,  1002  and  1003  of  FIG. 8  but may be other and/or additional buffers. Buffers  950  may store data samples and information about the reliability of the data samples. 
     Full Soft Sampling 
     The method can modify the NAND gate threshold values prior to gate voltage stabilization, while the voltage is still rising or dropping in a near linear manner. 
     By modifying the threshold (VT) voltage the method can keep the voltages continuously rising (dropping) nearly linearly in a region around the target threshold. Since the method can predict how the threshold change at each sample point we need to check whether the sense amplifier state changed from 0 to 1 and record the point at which it changed to 0 (or 1 if the voltages are dropping). 
     Thus, the flow (denoted  1500  in  FIG. 12 ) will work as follows: 
     Set Ref_Count to −Max_Val. ( 1501 ). 
     Set all counter buffers to Max_Val. ( 1502 ). 
     set target gate voltage. ( 1503 ). 
     On latch occasion, Counter buffers are set to (Sense Amplifier Value)*min(Counter Buffer value, Ref_Count)+(1−Sense Amplifier Value)*Counter Buffer value. ( 1504 ). 
     Increment Ref_Count. ( 1505 ). 
     If Need to set new gate target voltage, go to step  1503 . ( 1506 ) 
     If Ref_Count&lt;Max_Val return to step  1504 . ( 1507 ). 
     The method can modify the NAND gate voltages values prior to gate voltage stabilization, while the gate voltage is still rising or dropping in a near linear manner. 
     By modifying the gate voltage the method can keep the voltages continuously rising (dropping) nearly linearly in a region around the target threshold. Since the method can predict how the threshold change at each sample point we need to check whether the sense amplifier state changed from 0 to 1 and record the point at which it changed to 0 (or 1 if the voltages are dropping). 
     If few thresholds (not including the soft threshold mentioned above) are involved in the page read, then above procedure follows for all those thresholds but we output only the closest value to 0 of all reads. Note that all procedures may share the same Counter Buffers. 
       FIG. 10  illustrates three iterations of attempts to change a gate voltage and multiple sampling operations, wherein the second attempt starts before the first attempt is completed and the third attempt starts before the second attempt is completed. The may be two or more iterations. 
     The change of threshold voltage during the first attempt is denoted  811 . The change of threshold voltage during the second attempt is denoted  812 . The change of threshold voltage during the third attempt is denoted  813 . 
     The sampling points included in the first attempt are denoted  821 . 
     The sampling points included in the second attempt are denoted  822 . 
     The sampling points included in the third attempt are denoted  823 . 
     The time of convergence of the first attempt (it the first attempt was allowed to be completed) is denoted  851  and exceeds the beginning of the second attempt and even the beginning of the third attempt. 
     All procedures may be managed by processor  910  of  FIG. 11 . 
     It is noted that the aggregate duration (DT1) of multiple (N1) attempts is smaller than the aggregate duration (DT2) of the same number (N1) of prior art read cycle (such as illustrated in  FIG. 5 ). The ratio between DT2 and DT1 may range between about N1 and a fraction of N1. 
     Internal Partial Decoding Capability 
     On top of performing internal soft decoding the method can utilize it to perform at least partial soft decoding capabilities. There can be provided a sharing of some of the ECC bits with the external controller. By utilizing soft information the method can perform more reliable decoding, even with part of the ECC bits. Thus, decoding can be done internally, in the NAND device, possibly while outputting a codeword, and output only Hard information from the NAND device. This way, not only did we perform fast soft sampling but also, we only output hard data, which requires less traffic on the NAND channel, and allow the controller to perform hard decoding based on much more reliable bits. 
       FIG. 13  depicts an example of a page  1100  which is divided into payload bits  1110 , ECC bits A  1120  and ECC bits B  1130 . 
     The external controller may utilize both A and B bits for decoding when using soft and hard bits. However, internal to the NAND device we may utilize only some of the ECC bits (say ECC A) in order to support less complex decoding at the NAND that could be performed while data is being outputted or sampled. In case of failures, the external controller could access the soft information of all bits and decode based on all ECC bits. One example of such an encoding scheme may be that of product codes where ECC A bits may be those of columns or rows. And full decoding based on both A and B bits and would be performed in iterative manner. 
     In addition codewords used internally to the NAND may be longer than codewords used at the controller level without penalty of transferring the extra data on the NAND channel. 
     Internal Reliability Detection 
     The method can also use the internally obtained soft information to understand the page read reliability. If more bits were detected as not reliable, the method can enable a status on the NAND device indicating that the operation was not reliable. For this purpose the method can also use some of the ECC bits as described in the previous section. 
     This information on reliable reads could be used to enable more efficient read flows at the controller. For example, going directly into soft decode flow instead of first going through hard decode flow. 
     In addition this could indicate that a copyback operation is not reliable (for example from SLC to TLC) and the data should first go to the controller, be decoded and then written back to NAND device. 
     For example, the die may receive a request (from a flash memory controller outside the die) to execute a copyback operation (during which data is copied within the flash memory array without exiting the die) and the processor may refuse to execute the copyback operation. 
     Redundant Pages/Rows/Planes 
     On some NAND devices, some blocks exhibit redundant rows or redundant planes or even page types within a row. These redundant pages/rows/planes are typically found at the edges of the block and no data is stored on them because they are less reliable. These pages are less reliable because they may suffer from higher distortion or higher interference or edge effects. 
     However, with the higher reliability due to internal soft, the method can return to use these pages to store data. The method can also use lower coding rates on these pages to overcome some of the reliability issues. 
     This is illustrated, for example, by step  1246  of  FIG. 14  that includes determining an allocation of the flash memory cell based upon the reliability of the data sample. The determining may be executed by the processor and/or by a flash memory controller—in response to reliability information sent to the flash memory controller from the die. 
     Furthermore, we may use these pages not to increase capacity but to increase the overall redundancy in the system. Thus, though capacity increase may be little, the reliability improvement may be great. 
       FIG. 14  illustrates method  1200  according to an embodiment of the invention. 
     Method  1200  may start by steps  1210  and  1220 . 
     Step  1210  may include attempting, during a gate voltage change period (such as voltage change period  550 ), to change a value of a gate voltage of the flash memory cell from a first value to a second value. For example, a gate voltage of the flash memory cell has to be changed to a second value (such as first target value  520  of  FIG. 6 ). Due to the capacitance of a flash memory cell and the bitline the change of gate voltage takes time. 
     Step  1220  may include sampling, by a sampling circuit that belongs to the die, an output signal of the flash memory cell multiple times during the voltage gate change period to provide multiple samples. See, for example samples  541 ,  542 ,  543  and  544  of  FIG. 6 , initial sampling point  741  and additional sampling points  724 - 729  of  FIG. 7 . 
     Steps  1210  and  1220  may be followed by step  1230  of defining a given sample of the multiple samples as a data sample that represents data stored in the flash memory cell and determining, by a processor that belongs to the die, a reliability of the data sample based on one or more samples of the multiple samples that differ from the given sample. 
     Step  1230  may include at least one of the following: 
     a. Determining of the reliability comprises searching for a difference between the multiple samples. 
     b. Assigning a reliability score that is responsive to an order, within the multiple samples, of a first sample that differs from a preceding sample. 
     c. Assigning a reliability score that represents a decrease in a reliability with an increase in the order of the first sample. 
     d. Assigning a first reliability score when all the samples have a same value. 
     e. Assigning a second reliability score when one of the multiple samples differs from another sample. The second reliability score is indicative of a lower reliability than the first reliability score. 
     Step  1230  may be followed by steps  1210  and  1220 —for reading another flash memory cell. 
     Alternatively, steps  1210 ,  1220  and  1230  are executed in parallel on multiple flash memory cells (such as but not limited to a page of flash memory cells). Accordingly, method  1200  may include: 
     a. Step  1210  may include attempting, during a gate voltage change period (such as voltage change period  550 ), to change values of gate voltages of multiple flash memory cells from a first value to a second value. 
     b. Step  1220  may include sampling, by a sampling circuit that belongs to the die, each output signal of multiple output signals of the multiple flash memory cells multiple times during the voltage gate change period to provide multiple samples per flash memory cell.
 
c. Step  1230  of defining, for each of the multiple flash memory cells, a given sample of the multiple samples (of the flash memory cell) as a data sample that represents data stored in the flash memory cell and determining, by a processor that belongs to the die, a reliability of the data sample (of each flash memory cell) based on one or more samples of the multiple samples that differ from the given sample.
 
     Step  1230  may be followed by step  1240  of responding to the reliability of the data sample. 
     Step  1240  may include at least one of the following: 
     a. Decoding ( 1241 ), by the processor, the data sample. The decoding may include utilizing information, generated by the processor, related to the reliability of the data sample. The decoding usually takes place when multiple flash memory cells are read. 
     b. Receiving ( 1242 ), by the processor error correction information that was generated outside the die and relates to the data sample; and decoding, by the processor, the data sample. The decoding includes (a) utilizing information, generated by the processor, related to the reliability of the data sample and (b) utilizing the error correction information.
 
c. Controlling ( 1243 ) an execution of operations applied on the data sample in response to the reliability of the data sample.
 
     Step  1243  may include at least one out of: 
     a. Preventing a copyback operation when the reliability of the data sample is below a reliability threshold. ( 1244 ) 
     b. Selecting between an execution of a copyback operation and a provision of the data sample to an external flash memory controller based upon the reliability of the data sample ( 1245 ). 
     c. Determining an allocation of the flash memory cell based upon the reliability of the data sample ( 1246 ). 
       FIG. 15  illustrates method  1300  according to an embodiment of the invention. 
     Method  1300  may start by steps  1310  and  1320 . 
     Step  1310  may include performing a first attempt, during a first gate voltage change period, to change a value of a gate voltage of the flash memory cell from a first value to a second value. See, for example, an attempt to change the gate voltage to equal first target level  831  of  FIG. 9 . 
     Step  1310  may be followed by steps  1320  and  1330 . 
     Step  1320  may include sampling, by a sampling circuit that belongs to the die, an output signal of the flash memory cell multiple times during the first voltage gate change period to provide multiple first samples. See, for example sampling points  821  of  FIG. 9 . 
     Steps  1310  and  1320  may be followed by step  1330  of defining a first given sample of the first multiple samples as a first data sample that represents data stored in the flash memory cell and determining, by a processor that belongs to the die, a reliability of the first data sample based on one or more samples of the first multiple samples that differ from the first given sample. 
     Steps  1310  and  1320  (or step  1330 ) may be followed by steps  1410  and  1420 . 
     Step  1410  may include performing a second attempt, during a second gate voltage change period, to change a value of a gate voltage of the flash memory cell from a first intermediate value to a third value. The second attempt starts before a completion of the first attempt and when the gate voltage of the flash memory cell reached the first intermediate value. Referring to  FIG. 9 —the second attempt is denoted  812  and starts execution before the first attempt is completed (imaginary point in time  851 ). 
     Step  1420  may include sampling, by a sampling circuit that belongs to the die, an output signal of the flash memory cell multiple times during the second voltage gate change period to provide multiple second samples. 
     Steps  1410  and  1420  may be followed by step  1430  of defining a second given sample of the second multiple samples as a second data sample that represents the data stored in the flash memory cell and determining, by the processor, a reliability of the second data sample based on one or more samples of the second multiple samples that differ from the second given sample. 
     Steps  1410  and  1420  and/or step  1430  may be followed by steps  1410  and  1420  multiple times. 
     Step  1430  may be executed for multiple iterations of steps  1410  and  1420  after the completion of the multiple iterations or during the multiple iterations.  FIG. 10  illustrates a single addition repetition (curve  813 ) of steps  1410  and  1420 —each repetition starts before the previous repetition reaches the target gate voltage. 
     It is noted that step  1330  and/or step  1430  may be followed by step  1230  of responding to the reliability of the data sample taken during corresponding steps  1320  and  1420 . 
     Method  1300  may be executed for multiple flash memory cells—in a sequential and/or parallel manner. For example—flash memory cells of a row of flash memory cells of a flash memory cell array may be undergo method  1300  at the same time. 
     Each one of steps  1330  and  1430  may include at least one out of: 
     1) Determining of the reliability comprises searching for a difference between the multiple samples. 
     2) Assigning a reliability score that is responsive to an order, within the multiple samples, of a first sample that differs from a preceding sample. 
     3) Assigning a reliability score that represents a decrease in reliability with an increase in the order of the first sample. 
     4) Assigning a first reliability score when all the samples have a same value. Assigning a second reliability score when one of the multiple samples differs from another sample. The second reliability score is indicative of a lower reliability than the first reliability score. 
     The invention may also be implemented in a computer program for running on a computer system, at least including code portions for performing steps of a method according to the invention when run on a programmable apparatus, such as a computer system or enabling a programmable apparatus to perform functions of a device or system according to the invention. The computer program may cause the storage system to allocate disk drives to disk drive groups. 
     A computer program is a list of instructions such as a particular application program and/or an operating system. The computer program may for instance include one or more of: a subroutine, a function, a procedure, an object method, an object implementation, an executable application, an applet, a servlet, a source code, an object code, a shared library/dynamic load library and/or other sequence of instructions designed for execution on a computer system. 
     The computer program may be stored internally on a non-transitory computer readable medium. All or some of the computer program may be provided on computer readable media permanently, removably or remotely coupled to an information processing system. The computer readable media may include, for example and without limitation, any number of the following: magnetic storage media including disk and tape storage media; optical storage media such as compact disk media (e.g., CD-ROM, CD-R, etc.) and digital video disk storage media; nonvolatile memory storage media including semiconductor-based memory units such as FLASH memory, EEPROM, EPROM, ROM; ferromagnetic digital memories; MRAM; volatile storage media including registers, buffers or caches, main memory, RAM, etc. 
     A computer process typically includes an executing (running) program or portion of a program, current program values and state information, and the resources used by the operating system to manage the execution of the process. An operating system (OS) is the software that manages the sharing of the resources of a computer and provides programmers with an interface used to access those resources. An operating system processes system data and user input, and responds by allocating and managing tasks and internal system resources as a service to users and programs of the system. 
     The computer system may for instance include at least one processing unit, associated memory and a number of input/output (I/O) devices. When executing the computer program, the computer system processes information according to the computer program and produces resultant output information via I/O devices. 
     In the foregoing specification, the invention has been described with reference to specific examples of embodiments of the invention. It will, however, be evident that various modifications and changes may be made therein without departing from the broader spirit and scope of the invention as set forth in the appended claims. 
     Moreover, the terms “front,” “back,” “top,” “bottom,” “over,” “under” and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions. It is understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in other orientations than those illustrated or otherwise described herein. 
     Those skilled in the art will recognize that the boundaries between logic blocks are merely illustrative and that alternative embodiments may merge logic blocks or circuit elements or impose an alternate decomposition of functionality upon various logic blocks or circuit elements. Thus, it is to be understood that the architectures depicted herein are merely exemplary, and that in fact many other architectures may be implemented which achieve the same functionality. 
     Any arrangement of components to achieve the same functionality is effectively “associated” such that the desired functionality is achieved. Hence, any two components herein combined to achieve a particular functionality may be seen as “associated with” each other such that the desired functionality is achieved, irrespective of architectures or intermedial components. Likewise, any two components so associated can also be viewed as being “operably connected,” or “operably coupled,” to each other to achieve the desired functionality. 
     Furthermore, those skilled in the art will recognize that boundaries between the above described operations merely illustrative. The multiple operations may be combined into a single operation, a single operation may be distributed in additional operations and operations may be executed at least partially overlapping in time. Moreover, alternative embodiments may include multiple instances of a particular operation, and the order of operations may be altered in various other embodiments. 
     Also for example, in one embodiment, the illustrated examples may be implemented as circuitry located on a single integrated circuit or within a same device. Alternatively, the examples may be implemented as any number of separate integrated circuits or separate devices interconnected with each other in a suitable manner. 
     Also for example, the examples, or portions thereof, may implemented as soft or code representations of physical circuitry or of logical representations convertible into physical circuitry, such as in a hardware description language of any appropriate type. 
     Also, the invention is not limited to physical devices or units implemented in non-programmable hardware but can also be applied in programmable devices or units able to perform the desired device functions by operating in accordance with suitable program code, such as mainframes, minicomputers, servers, workstations, personal computers, notepads, personal digital assistants, electronic games, automotive and other embedded systems, cell phones and various other wireless devices, commonly denoted in this application as ‘computer systems’. 
     However, other modifications, variations and alternatives are also possible. The specifications and drawings are, accordingly, to be regarded in an illustrative rather than in a restrictive sense. 
     In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word ‘comprising’ does not exclude the presence of other elements or steps then those listed in a claim. Furthermore, the terms “a” or “an,” as used herein, are defined as one or more than one. Also, the use of introductory phrases such as “at least one” and “one or more” in the claims should not be construed to imply that the introduction of another claim element by the indefinite articles “a” or “an” limits any particular claim containing such introduced claim element to inventions containing only one such element, even when the same claim includes the introductory phrases “one or more” or “at least one” and indefinite articles such as “a” or “an.” The same holds true for the use of definite articles. Unless stated otherwise, terms such as “first” and “second” are used to arbitrarily distinguish between the elements such terms describe. Thus, these terms are not necessarily intended to indicate temporal or other prioritization of such elements The mere fact that certain measures are recited in mutually different claims does not indicate that a combination of these measures cannot be used to advantage. 
     While certain features of the invention have been illustrated and described herein, many modifications, substitutions, changes, and equivalents will now occur to those of ordinary skill in the art. It is, therefore, to be understood that the appended claims are intended to cover all such modifications and changes as fall within the true spirit of the invention.