Patent Publication Number: US-5252843-A

Title: Semiconductor device having overlapping conductor layers

Description:
This application is continuation of application Ser. No. 573,758 filed Aug. 28, 1990 now abandoned. 
    
    
     BACKGROUND OF THE INVENTION 
     The present invention generally relates to semiconductor devices and methods of producing semiconductor devices, and more particularly to a semiconductor device which uses a compound semiconductor such as GaAs and a method of producing such a semiconductor device. 
     Compared to the metal oxide semiconductor (MOS) semiconductor devices which use silicon, the semiconductor device which uses a compound semiconductor can operate at a high speed and there is active research on the semiconductor device which uses the compound semiconductor. The aim of the research is to shorten the gate length so as to increase the operation speed and to reduce the size of elements so as to improve the integration density. 
     For a digital circuit which is formed in the semiconductor device which uses the compound semiconductor, a direct coupled field effect transistor logic (DCFL) circuit is generally used to improve the integration density. An inverter circuit which forms a basic circuit of the DCFL circuit is shown in FIG. 1. 
     The inverter circuit shown in FIG.1 includes an enhancement type FET 2 and a depletion type FET 4 which is connected to the FET 2 as a load. A source S of the FET 2 is grounded, and a drain D of the FET 2 is connected to a source S of the FET 4. A gate G of the FET 4 is connected to the source S of the FET 4, and a power source voltage V DD  is applied to a drain D of the FET 4. An input signal V IN  is applied to a gate G of the FET 2, and an output signal V OUT  which is an inverted signal of the input signal V IN  is output from a node which connects the drain D of the FET 2 and the source S of the FET 4. 
     FIGS. 2A and 2B show the conventional inverter circuit shown in FIG. 1 with shortened gate length for the purpose of increasing the operation speed. FIG. 2A is a plan view of the conventional inverter circuit, and FIG. 2B is a cross sectional view along a line A--A&#39; in FIG. 2A. 
     In FIG. 2B, an intrinsic GaAs buffer layer 12 is formed on a semiinsulative GaAs substrate 10, and an n-type GaAs active layer 14 is formed on the intrinsic GaAs buffer layer 12. An element forming region is defined by an isolation region 16 which is formed by implanting oxygen ions. A source electrode 18, a common electrode 19 and a drain electrode 20 are formed on the n-type active layer 14. A gate electrode 22 of the enhancement type FET 2 is formed between the source electrode 18 and the common electrode 19, and a gate electrode 23 of the depletion type FET 4 is formed between the common electrode 19 and the drain electrode 20. The common electrode 19 is used as a drain electrode of the FET 2 and also as a source electrode of the FET 4. 
     The lower portions of the gate electrodes 22 and 23 have a recess structure in the n-type GaAs active layer 14. The recess of the gate electrode 22 is slightly deeper than the recess of the gate electrode 23. 
     In the conventional inverter circuit, the gate electrodes 22 and 23 are made narrow and the cross sectional areas thereof are small so as to shorten the gate length. On the other hand, in the DCFL circuit which can realize the high-speed operation and high integration density, a relative large current flows at the gate electrode 22. For this reason, the current density of the current flowing through the gate electrode 22 becomes extremely large when increasing the operation speed, and there is a problem in that the reliability of the element becomes poor. 
     In addition, as may be seen from FIG. 2A, various measures must be taken to input the input signal V IN  to the conventional inverter circuit. Such measures include extending the gate electrode 22 of the FET 2 outside the element forming region and forming a contact hole in the extended portion, providing an interconnection layer 24 outside the element forming region to connect the gate electrode 23 of the FET 4 and the common electrode 19, and forming a contact hole in the interconnection layer 24 for outputting the output signal V OUT . Hence, the conventional inverter circuit requires a region outside the element forming region for providing contact holes and interconnections, and there is a problem in that it is difficult to improve the integration density. 
     SUMMARY OF THE INVENTION 
     Accordingly, it is a general object of the present invention to provide a novel and useful semiconductor device and method of producing the semiconductor device, in which the problems described above are eliminated. 
     Another and more specific object of the present invention is to provide a semiconductor device comprising a semiconductor substrate, an active layer formed on the semiconductor substrate, a source electrode and a drain electrode respectively formed on the active layer, a gate electrode formed on the active layer between the source and drain electrodes, where the gate electrode includes a gate contact portion which makes contact with the active layer and has a thickness greater than those of the source and drain electrodes and an overgate portion which is connected to the gate contact portion and extends over at least a portion of one of the source and drain electrodes, and an insulator layer formed on the active layer and covering the source and drain electrodes and the gate contact portion, where the insulator layer has a contact hole through which the overgate portion connects to the one of the source and drain electrodes. According to the semiconductor device of the present invention, it is possible to increase the cross sectional area of the gate electrode having a short gate length without increasing the source resistance. It is also possible to reduce the current density of the current flowing through the gate without deteriorating the characteristic of the element. Furthermore, it is possible to connect the electrodes to desired interconection layers over the element forming region, without the need for a region exclusively for making the contacts. Therefore, it is possible to greatly improve the integration density of the semiconductor device. 
     Still another object of the present invention is to provide a semiconductor device comprising a semiconductor substrate, an active layer formed on the semiconductor substrate, first, second and third electrodes respectively formed on the active layer, a first gate electrode formed on the active layer between the first and second electrodes, the first gate electrode and the first and second electrodes forming electrodes of a first field effect transistor, where the first gate electrode includes a first gate contact portion which makes contact with the active layer and has a thickness greater than those of the first and second electrodes and a first overgate portion which is connected to the first gate contact portion and extends over at least a portion of the first electrode, a second gate electrode formed on the active layer between the second and third electrodes, where the second gate electrode and the second and third electrodes form electrodes of a depletion type field effect transistor and the second gate electrode includes a second gate contact portion which makes contact with the active layer and has a thickness greater than those of the second and third electrodes and a second overgate portion which is connected to the second gate contact portion and extends over at least a portion of the second electrode, and an insulator layer formed on the active layer and covering the first through third electrodes and the first and second gate contact portions, where the insulator layer has a contact hole through which the second overgate portion connects to the second electrode. 
     A further object of the present invention is to provide a method of producing a semiconductor device comprising the steps of preparing a stacked structure including a semiconductor substrate, an active layer formed on the semiconductor substrate, a source electrode and a drain electrode respectively formed on the active layer, a gate contact portion formed on the active layer between the source and drain electrodes, where the gate contact portion has a thickness greater than those of the source and drain electrodes, and an insulator layer formed on the active layer and covering the source and drain electrodes and a side surface of the gate contact portion so that a top surface of the gate contact portion is exposed, forming a first contact hole in the insulator layer directly above one of the source and drain electrodes, and forming an overgate portion on the insulator layer which extends over at least a portion of the other of the source and drain electrodes and connects to the one of the source and drain electrodes via the first contact hole, where the overgate portion is connected to the gate contact portion to form a gate electrode. According to the method of the present invention, it is possible to connect the electrodes to desired interconnection layers over the element forming region without the need to provide a special region exclusively for making the contacts. 
     Another object of the present invention is to provide a method of producing a semiconductor device comprising the steps of preparing a stacked structure including a semiconductor substrate, an active layer formed on the semiconductor substrate, first, second and third electrodes respectively formed on the active layer, first and second gate contact portions formed on the active layer respectively between the first and second electrodes and between the second and third electrodes, where the first and second gate contact portions have a thickness greater than those of the first through third electrodes, and an insulator layer formed on the active layer and covering the first through third electrodes and side surfaces of the first and second gate contact portions so that top surfaces of the first and second gate contact portions are exposed, forming a first contact hole in the insulator layer directly above the second electrode, and forming first and second overgate portions on the insulator layer, where the first overgate portion extends over at least a portion of the first electrode, the second overgate portion extends over at least a portion of the second electrode and connecting to the second electrode via the first contact hole, the first overgate portion is connected to the first gate contact portion to form a first gate electrode and the second overgate portion is connected to the second gate contact portion to form a second gate electrode. 
     Still another object of the present invention is to provide a method of producing a semiconductor device comprising the steps of forming a plurality of field effect transistor parts in an array on an active layer which is formed on a substrate, where each of the field effect transistors include a source electrode, a drain electrode and a gate contact portion, and coupling arbitrary ones of the field effect transistor parts by forming overgate portions which make contact with corresponding gate contact portions of the field effect transistor parts, where each of the overgate portions extend over at least a portion of one of the source and drain electrodes of a corresponding one of the field effect transistor parts. According to the method of the present invention, the present invention can be applied to a gate array type semiconductor device to increase the degree of freedom of designing interconnections to realize a desired function. 
     Other objects and further features of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a circuit diagram showing a conventional inverter circuit; 
     FIGS. 2A and 2B are a plan view and a cross sectional view respectively showing the conventional inverter circuit shown in FIG. 1; 
     FIG. 3A is a plan view showing an essential part of a first embodiment of a semiconductor device according to the present invention; 
     FIGS. 3B through 3D are cross sectional views respectively showing the first embodiment at various parts shown in FIG. 3A; 
     FIGS. 4A through 4L are cross sectional views for explaining a first embodiment of a method of producing a semiconductor device according to the present invention; 
     FIGS. 5A through 5B are cross sectional views for explaining a third embodiment of the method of producing the semiconductor device according to the present invention; 
     FIGS. 6A and 6B respectively are a circuit diagram and a plan view showing a second embodiment of the semiconductor device according to the present invention; 
     FIG. 7 is a plan view showing a conventional ring oscillator for comparing sizes with a ring oscillator realized in the second embodiment of the semiconductor device; 
     FIG. 8 is a plan view showing basic cells for explaining a third embodiment of the semiconductor device according to the present invention; 
     FIG. 9 is a circuit diagram showing a NAND circuit; 
     FIG. 10 is a plan view showing the NAND circuit realized by the third embodiment of the semiconductor device; 
     FIG. 11 is a circuit diagram showing a NOR circuit; 
     FIG. 12 is a plan view showing the NOR circuit realized by the third embodiment of the semiconductor device; and 
     FIG. 13 is a plan view showing a conventional NOR circuit for comparing sizes with the NOR circuit realized in the third embodiment of the semiconductor device. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     First, a description will be given of a first embodiment of a semiconductor device according to the present invention, by referring to FIGS. 3A through 3D. FIG. 3A is a plan view of the first embodiment. FIG. 3B is a cross sectional view of the first embodiment along a line C--C&#39; in FIG. 3A, FIG. 3C is a cross sectional view of the first embodiment along a line B--B&#39; in FIG. 3A, and FIG. 3D is a cross sectional view of the first embodiment along a line A--A&#39; in FIG. 3A. In FIGS. 3A through 3D, those parts which are basically the same as those corresponding parts in FIGS. 1, 2A and 2B are designated by the same reference numerals, and a detailed description thereof will be omitted. In this embodiment, the present invention is applied to the inverter having the circuit construction shown in FIG. 1. 
     In this embodiment, an intrinsic GaAs buffer layer 12 and an n-type GaAs active layer 14 are successively formed on a semiinsulative GaAs substrate 10, and an element forming region is defined by an isolation region 16. A gate electrode 30 is formed on the n-type GaAs active layer 14 between a source electrode 18 (first electrode) and a common electrode 19 (second electrode), and a gate electrode 31 is formed on the n-type GaAs active layer 14 between the common electrode 19 and a drain electrode 20 (third electrode). These gate electrodes 30 and 31 form an essential part of this embodiment. 
     The gate electrode 30 of an enhancement type FET 2 is made up of a gate contact portion 30a and an overgate portion 30b and has a T-shaped cross section. The gate contact portion 30a makes contact with the n-type GaAs active layer 14 between the source electrode 18 and the common electrode 19. The overgate portion 30b connects to an upper part of the gate contact portion 30a and extends mainly above the left source electrode 18 via an insulator layer 32. 
     The gate electrode 31 of a depletion type FET 4 is made up of a gate contact portion 31a and an overgate portion 31b and has a T-shaped cross section. The gate contact portion 31a makes contact with the n-type GaAs active layer 14 between the common electrode 19 and the drain electrode 20. The overgate portion 31b connects to an upper part of the gate contact portion 31a and extends above the common electrode 19 and the drain electrode 20 to the right and left via the insulator layer 32. 
     In this embodiment, a contact hole is formed in the insulator layer 32 above the common electrode 19 as shown in FIG. 3D, and the overgate portion 31b connects to the common electrode 19 via this contact hole. In other words, this embodiment is characterized in that the overgate portion 31b increases the cross sectional area of the gate electrode 31 and also connects the gate electrode 31 of the FET 4 to the common electrode 19 which is used as the source electrode of the FET 4. 
     An interconnection layer 36 is formed over the overgate portion 31b via an insulator layer 34. The interconnection layer 36 is made up of interconnection layers 36a, 36b and 36c. The interconnection layer 36a is provided to input the input signal and makes contact with the overgate portion 30b of the gate electrode 30 of the FET 2 as shown in FIG. 3B. The interconnection layer 36b is provided to apply the power source voltage V DD , and makes contact with the drain electrode 20 of the FET 4 as shown in FIG. 3C. The interconnection layer 36c is provided to output the output signal V OUT , and makes contact with the overgate portion 31b of the gate electrode 31 of the FET 4. In other words, because the overgate portions 30b and 31b of the respective gate electrodes 30 and 31 are wide in this embodiment, it is possible to make contact with the interconnection layer 36 via a contact hole above the element forming region. 
     For example, the electrodes 18, 19 and 20 may be made of a AuGe/Au layer having a thickness of 0.3 μm, where the AuGe and Au parts of the AuGe/Au layer respectively have thicknesses of 0.02 μm and 0.28 μm. The gate contact portions 30a and 31a may be made of an Al layer having a thickness of 0.6 μm. In addition, the overgate portions 30b and 31b may be made of a Ti/TiN/Pt/Au layer having a thickness of 0.3 μm, where the Ti, TiN, Pt and Au parts of the Ti/TiN/Pt/Au layer respectively have thicknesses of 0.02 μm, 0.07 μm, 0.01 μm and 0.2 μm. 
     According to this embodiment, the overgate portion of the gate electrode exists in a layer above the source electrode, the common electrode and the drain electrode. For this reason, there is no need to take measures so that the overgate portion does not make contact with the source electrode, the common electrode and the drain electrode. As a result, the source electrode, the common electrode and the drain electrode can be positioned close to the gate contact portion. Accordingly, even when the overgate portion is provided to increase the cross sectional area of the gate electrode, the source resistance will not increase to deteriorate the element characteristic. 
     In addition, according to this embodiment, it is possible to connect the gate electrode and the source electrode without providing a special region realizing the contact, because the overgate portion makes contact with the source electrode which is provided immediately below the overgate portion. 
     Furthermore, according to this embodiment, because the overgate portion of the gate electrode is wide, it is possible to make contact with the upper interconnection layer via a contact hole above the element forming region without the need to provide a special region for realizing the contact. 
     In this embodiment, it is assumed for the sake of convenience that the first electrode is the source electrode and the third electrode is the drain electrode. However, it is of course possible to consider the drain electrode as the first electrode and the source electrode as the third electrode. 
     Next, a description will be given of a first embodiment of a method of producing the semiconductor device according to the present invention, by referring to FIGS. 4A through 4L. In this embodiment of the method, the first embodiment of the semiconductor device shown in FIGS. 3A through 3D is produced. In FIGS. 4A through 4L, those parts which are the same as those corresponding parts in FIGS. 3A through 3D are designated by the same reference numerals, and a description thereof will be omitted. 
     As shown in FIG. 4A, the intrinsic GaAs buffer layer 12 having a thickness of approximately 10000 Å and the n-type GaAs active layer 14 having a thickness of approximately 2000 Å A and an impurity density of 5.0×10 17  cm -3  are successively grown epitaxially on the semiinsulative GaAs substrate 10. Next, the element forming region is masked by a resist layer 40 having a thickness of approximately 1.5 μm, and oxygen ions are implanted with a dosage of 2.0×10 12  cm -2  and a power of 150 keV so as to form the isolation region 16 outside the element forming region. 
     Then, as shown in FIG. 4B, a resist layer 42 is formed by coating a photoresist or an electron beam resist and this resist layer 42 is patterned into a predetermined shape. The patterned resist layer 42 is used as a mask for forming the source electrode ,(first electrode), the common electrode (second electrode) and the drain electrode (third electrode). A AuGe/Au layer 44 having a thickness of approximately 3000 Å is deposited by a vacuum vapor deposition. After the deposition of the AuGe/Au layer 44, the resist layer 42 is removed to lift off unwanted portions of the AuGe/Au layer 44. Thereafter, the remaining portions of AuGe/Au layer 44 are metallized by a thermal process at 450° for approximately 1 minute. As a result, the source electrode 18, the common electrode 19 and the drain electrode 20 which make ohmic contact with the n-type GaAs active layer 14 are formed. 
     Next, as shown in FIG. 4C, a resist layer 46 is formed by coating an electron beam resist, and an aperture pattern having a width of approximately 0.2 μm is made for the formation of the gate electrode 31 of the FET 4. Thereafter, the n-type GaAs active layer 14 is etched approximately 1000 Å using HF, H 2  O 2  and H 2  O as etchants so as to form a first recess at a portion where the gate electrode 31 is formed in a latter stage. The first recess may also be formed by a reactive ion etching (RIE) using flon 12 (CCl 2  F 2 ) as the etchant. 
     Then, as shown in FIG. 4D, the resist layer 46 is used as a mask, and an aluminum (Al) layer 48 is deposited to a thickness of approximately 6000 Å by a vapor deposition. The Al layer 48 is formed on the resist layer 46 and on the first recess portion of the n-type GaAs active layer 14. 
     When the resist layer 46 is removed to lift off unwanted portions of the Al layer 48, the gate contact portion 31a is formed as shown in FIG. 4E. A tip end of this gate contact portion 31a is located at a position higher that those of the source electrode 18, the common electrode 19 and the drain electrode 20. Then, a resist layer 50 is formed by coating an electron beam resist, and an aperture pattern having a width of approximately 0.2 μm is made for the formation of the gate electrode 30 of the FET 2. Thereafter, the n-type GaAs active layer 14 is etched approximately 1400 Å using HF, H 2  O 2  and H 2  O as etchants so as to form a second recess at a portion where the gate electrode 30 is formed in a latter stage. This second recess for the gate electrode 30 is slightly deeper than the first recess for the gate electrode 31. 
     Next, as shown in FIG. 4F, the resist layer 50 is used as a mask, and an Al layer 52 is deposited to a thickness of approximately 6000 Å by a vapor deposition. The Al layer 52 is formed on the resist layer 50 and on the second recess portion of the n-type GaAs active layer 14. 
     When the resist layer 50 is removed to lift off unwanted portions of the Al layer 52, the gate contact portion 30a is formed as shown in FIG. 4G. A tip end of this gate contact portion 30a is located at a position higher that those of the source electrode 18, the common electrode 19 and the drain electrode 20, similarly as in the case of the gate contact portion 31a. 
     The layer 52 is not limited to the Al layer. For example, a Ti/Pt/Au layer having a thickness of 1000/1000/400 Å or a Ti/Mo/Au layer having a thickness of 1000/1000/400 Å may be used as the layer 52. 
     Next, a silicon dioxide (SiO 2 ) layer 54 is formed by a chemical vapor deposition (CVD), and a resist layer 56 is formed on the SiO 2  layer 54 to flatten the surface as shown in FIG. 4H. 
     Then, a gas mixture of CF 4  and O 2  is used as an etching gas to etch back until only the tip ends of the gate contact portions 30a and 31a become exposed as shown in FIG. 41. This etch back is carried out under an etching condition such that the etching rates of the SiO 2  layer 54 and the resist layer 56 become the same. 
     Thereafter, a resist layer 58 is formed on the entire exposed surface and the resist layer 58 is patterned so as to form a contact hole in the SiO 2  layer 54 above the common electrode 19 as shown in FIG. 4J. 
     Furthermore, Ti/TiN/Pt/Au layer 60 is formed on the entire exposed surface to a thickness of approximately 2000 Å by a vapor deposition or sputtering as shown in FIG. 4K. It is of course possible to form a Ti/Pt/Au layer by a vapor deposition or sputtering. Then, a resist layer 62 is formed on the layer 60, and this resist layer 62 is patterned so that portions of the resist layer 62 remain at parts where the overgate portions 30b and 31b are to be formed in a latter stage. 
     The resist layer 62 is used as a mask when etching the layer 60, and the resist layer 62 is removed thereafter. As a result, the overgate portions 30b and 31b are formed as shown in FIG. 4L. As shown, the overgate portion 30b connects to the upper part of the gate contact portion 30a and extends to a part above the source electrode 18 on the SiO 2  layer 54. On the other hand, the overgate portion 31b connects to the upper part of the gate contact portion 31a and extends to a part above the common electrode 19 and the drain electrode 20 on the SiO 2  layer 54. The overgate portion 31b makes contact with the common electrode 19. 
     Next, the SiO 2  layer 34 is formed on the entire exposed surface by a CVD. A contact hole which reaches the overgate portion 30b as shown in FIG. 3B, a contact hole which reaches the drain electrode 20 as shown in FIG. 3C, and a contact hole which reaches the overgate portion 31b as shown in FIG. 3D are formed in the SiO 2  layer 34. Thereafter, the Ti/Pt/Au interconnection layer 36 is formed on the entire exposed surface by a vapor deposition or sputtering. The interconnection layer 36 is patterned by an Ar ion milling so as to form the interconnection layer 36a shown in FIG. 3B, the interconnection layer 36b shown in FIG. 3C and the interconnection layer 36c shown in FIG. 3D. 
     According to this embodiment of the method, the overgate portion is provided in a layer above the layer in which the source electrode, the common electrode and the drain electrode are provided. For this reason, it is possible to maintain a sufficiently large alignment margin, thereby facilitating the production of the semiconductor device. 
     Next, a description will be given of essential steps of a second embodiment of the method of producing the semiconductor device according to the present invention. In this second embodiment of the method, after forming the gate contact portions 30a and 31a as shown in FIG. 4G, an OCD resin layer, for example, is formed by a spin coating instead of forming the SiO 2  layer 54 in the steps shown in FIGS. 4H and 4I. The OCD resin layer is etched back until the tip ends of the gate contact portions 30a and 31a become exposed. The steps shown in FIG. 4J and after in this second embodiment are basically the same as those of the first embodiment of the method. 
     Next, a description will be given of essential steps of a third embodiment of the method of producing the semiconductor device according to the present invention. In this third embodiment of the method, after the step described in conjunction with FIG. 4B, the SiO 2  layer 54 is formed as shown in FIG. 5A and holes are formed in the SiO 2  layer 54 at the parts corresponding to the positions where the gate contact portions 30a and 31b are formed in a latter stage. Then, as shown in FIG. 5B, a tungsten (W) layer 64 is formed inside the holes by a CVD using a gas mixture of SiH 4  /WF 6  =1 at a total pressure of 0.3 Torr and a temperature of 250° C. This state shown in FIG. 5B is the same as the state shown in FIG. 41, and the steps shown in FIG. 4J and after in this third embodiment are basically the same as those of the first embodiment of the method. 
     Next, a description will be given of a second embodiment of the semiconductor device according to the present invention, by referring to FIGS. 6A and 6B. In this embodiment, the present invention is applied to a ring oscillator. FIG. 6A is a circuit diagram showing a ring oscillator, and FIG. 6B is a plan view of the ring oscillator shown in FIG. 6A. In FIGS. 6A and 6B, those parts which are essentially the same as those corresponding parts in FIGS. 3A through 3D are designated by the same reference numerals, and a detailed description thereof will be omitted. 
     The ring oscillator shown in FIG. 6A includes DCFL inverter circuits INV1 and INV2 which are connected in two stages. A node which connects the drain D of the enhancement type FET 2 and the source S of the depletion type FET 4 of the first stage is connected to a gate G of the enhancement type FET 2 of the second stage. In other words, the inverted output signal from the DCFL inverter circuit INV1 of the first stage is supplied as the input signal of the DCFL inverter circuit INV2 of the second stage, and an output signal of the DCFL inverter circuit INV2 of the second stage is obtained from a node which connects a drain of the enhancement type FET 2 and a source of the depletion type FET 4 of the second stage. 
     As shown in FIG. 6B, the DCFL inverter circuits INV1 and INV2 are formed between the interconnection layer 36b for supplying the power source voltage V DD  and a ground interconnection layer 100. A left part corresponds to the DCFL inverter circuit INV1, and a right part corresponds to the DCFL inverter circuit INV2. 
     The gate electrode 31 of the DCFL inverter circuit INV1 is coupled to the common electrode 19 via the overgate portion 31a. This overgate portion 31a is also used as the overgate portion 30a of the gate electrode 30 of the DCFL inverter circuit INV2. In other words, in this embodiment, the overgate portion 31a is used in common as the overgate portion 31a of the DCFL inverter circuit INV1 and the overgate portion 30a of the DCFL inverter circuit INV2. 
     For comparison purposes, FIG. 7 shows a plan view of a conventional ring oscillator. In FIG. 7, those parts which are basically the same as those corresponding parts in FIGS. 2A, 2B and 6B are designated by the same reference numerals, and a description thereof will be omitted. 
     In FIG. 7, the DCFL inverter circuits INV1 and INV2 are connected by the interconnection layer 24. Accordingly, the interconnection layer 24 must be formed outside the element forming region. As a result, a distance between an end B of the source electrode 18 of the first stage to an end B, of the source electrode 18 of the second stage is approximately 9.0 μm. 
     On the other hand, in the embodiment shown in FIG. 6B, a distance between an end A of the source electrode 18 of the first stage to an end A&#39; of the source electrode 18 of the second stage is approximately 7.5 μm which is small compared to the distance between the ends B and B, in FIG. 7. Hence, it may be seen that the area occupied by the semiconductor device can be reduced effectively according to this embodiment. In other words, since there is no need to provide special regions exclusively for connecting a plurality of circuits, it is possible to reduce the pitch with which the circuits are provided in the semiconductor device and therefore improve the integration density of the semiconductor device. 
     Next, a description will be given of a third embodiment of the semiconductor device according to the present invention, by referring to FIG. 8. In this embodiment, the present invention is applied to a gate array type semiconductor device. 
     FIG. 8 is a plan view showing basic cells of the semiconductor device. The basic cells include depletion type cells 201 and enhancement type cells 202. In FIG. 8, a region indicated by a phantom line corresponds to an active region. 
     When using the basic cells shown in FIG. 8 to realize a 2-input NAND circuit shown in FIG. 9, contact holes are selectively formed and the connections are made as indicated by hatchings in FIG. 10. In FIG. 9, the NAND circuit includes a depletion type FET 2011 and enhancement type FETs 202 1  and 202 2  which are connected as shown between the power source voltage V DD  and the ground GND. Two input signals V1 and V2 are applied to the gates of the respective FETs 20 2  and 202 2 , and an output signal OUT is obtained from a node which connects the FETs 201 1  and 202 1 . In FIG. 10, a contact hole is formed to connect the overgate portion of the gate electrode and the source electrode of the FET 201 1 . The overgate portion of the FET 201 1  connects to an upper interconnection layer (not shown) via a contact hole. An interconnection layer 203 is formed to connect the source electrode of the FET 202 1  to the drain electrode of the transistor 202 2  via respective contact holes. The source electrode of the FET 201 1  is used in common as the drain electrode of the FET 202 1 . It may be seen from FIG. 10 that the overgate portion of the FETs 201 1 , 202 1  and 202 2  are only formed partially on the respective gate contact portions so as to prevent unwanted contacts. 
     When using the basic cells shown in FIG. 8 to realize a 2-input NOR circuit shown in FIG. 11, contact holes are selectively formed and the connections are made as indicated by hatchings in FIG. 12. In FIG. 11, the NOR circuit includes the depletion type FET 201 1  and the enhancement type FETs 202 1  and 202 2  which are connected as shown between the power source voltage V DD  and the ground GND. Two input signals V1 and V2 are applied to the gates of the respective FETs 202 1  and 202 2 , and an output signal OUT is obtained from a node which connects the FETs 201 1 , 202 1  and 202 2 . In FIG. 12, a contact hole is formed to connect the overgate portion of the gate electrode and the source electrode of the FET 201 1 . An interconnection layer 204 is formed to connect the drain electrode of the FET 202 1  to the drain electrode of the transistor 202 2  via respective contact holes. The overgate portion of the FET 201 1  is also connected to the interconnection layer 204 via a contact hole. The source electrode of the FET 201 1  is used in common as the drain electrode of the FET 202 1 . It may be seen from FIG. 12 that the overgate portion of the FETs 201 1 , 202 1  and 202 2  are only formed partially on the respective gate contact portions so as to prevent unwanted contacts. 
     In FIGS. 10 and 12, the areas occupied by the NAND circuit and the NOR circuit respectively are approximately 78.75 μm 2  which is the area occupied by the basic cells shown in FIG. 8. But when a NOR circuit is formed by use of the conventional basic cells, the area occupied by the NOR circuit becomes approximately 146.25 μm as shown in FIG. 13 because special regions are required exclusively for making the desired contacts. In this embodiment, the degree of freedom of designing the interconnections is large compared to the conventional semiconductor device because there is no need to provide a contact pad for making contact with the upper interconnection layer. 
     Therefore, according to the present invention, the following advantageous effects are obtainable. First, because the gate of the FET has the T-shaped cross section, it is possible to reduce the current density of the current passing through the gate without deteriorating the characteristic of the FET, it is possible to shorten the distance between the gate and source and the distance between the gate and drain of the FET, and it is also possible to realize a satisfactory connection between the gate and the source or drain of the FET. It should be noted that a direct connection of the gate and source or drain of the FET is not possible because the gate is usually made of Al or the like and makes contact with the active layer while the source or drain is usually made of Au or the like and makes ohmic contact with the active layer. Second, since the gate, source and drain electrodes of the FET have the same thickness, it is possible to form the gate, source and drain electrodes by a common process to simplify the production process and also ensure consistent characteristics of the FETs. Third, because a contact hole may be selectively formed to connect the gate to the source or drain of the FET, there is no need to form a contact pad exclusively for making contact and the degree of freedom of designing the interconnections is large without increasing the area occupied by the semiconductor device. 
     In the described embodiments, the present invention is applied to the FET having the recess gate structure. However, the present invention may be applied similarly to any Schottky gate FET, that is, to any semiconductor device in which the current easily flows through the gate electrode. For example, the present invention may be applied to metal oxide semiconductor FETs (MOSFETs), metal semiconductor FETs (MESFETs), metal insulator FETs (MISFETs) and high electron mobility transistors (HEMTs). 
     Further, the present invention is not limited to these embodiments, but various variations and modifications may be made without departing from the scope of the present invention.