Patent Publication Number: US-4319873-A

Title: Flame detection and proof control device

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates to a flame detection and proof control device for detecting flame in a gas-fired system. It finds particular utility in use with a regulated sealed combustion heating system, but can be used in a wide variety of systems and appliances which require safety controls. 
     It is important for reasons of safety that gas appliances be equipped with a flame detection and control unit which will assure shut-off of gas when no flame is present. The control must also allow for a period for ignition when the gas is on even though there is no flame. When the gas has not been ignited, the system must operate to quickly close the gas valve. 
     There are a number of types of gas appliances, including heating and air conditioning systems, stoves, dryers, etc., for which such a flame detection and proof device is required. For many years, gas appliances have operated with a pilot light system which ignites the main gas jet when the appliance is turned on. However, in recent years it has been recognized that such systems are not fuel or energy efficient. Consequently, other systems have been introduced to replace the pilot light type of system. 
     Spark ignition systems have also been used which, in effect, ignite the gas by creating a spark across an ignition gap. These systems are more energy efficient than the pilot light type system, but have not been found to operate well with the regulated sealed combustion heating system. 
     In recent years flame igniters, usually comprised of silicon carbide, have been developed which can be heated rapidly by applying an AC voltage thereto. The igniters have provided an efficient way of providing ignition of the gas. 
     Control devices for the above types of ignition systems which have been used in the prior art with gas-fired systems have had certain disadvantages. Relatively high voltage power sources of the order of 220 volts have been required to operate the prior art safety controls. Also, such systems have not always given 100 percent protection in assuring that gas will be shut off if ignition is not effected. 
     SUMMARY OF THE INVENTION 
     The present invention overcomes the problems and disadvantages of the prior art by providing a flame detection and proof control device for use in a gas-fired system which comprises a probe for producing first and second signals respectively corresponding to no-flame and flame conditions, a detector circuit, relay means which is responsive to the detector circuit, circuit means including means for delaying the probe output signals a set time period connected to the input of the detector circuit and responsive to the probe output signals, and relay means responsive to the detector circuit to activate only during the set time period or when the probe output signal corresponds to a flame condition. More specifically, circuit means produces a first output signal during the set time period, produces a second output signal after completion of the set time period and during application of the first probe signal and produces the first output signal after completion of the set time period and during application of the second probe signal. 
     Redundancy is built into the flame detection and proof control device by including substantially duplicate circuits both of which must produce an output signal indicative of safe conditions for activation of the relay. 
     The flame detection and proof control device also includes a circuit breaker connecting the device to the power source and a control circuit responsive to circuit means to open the breaker when the circuit means produces an output signal indicative of a no-flame condition after the set time period. 
     This invention utilizes the features of NAND GATE logic implemented by CMOS technology. As a result, high reliability is achieved at low voltage levels. 
     The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate one embodiment of the invention and, together with the description, serve to explain the principles of the invention. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic functional diagram of the flame detection and proof control device in accordance with the present invention; 
     FIGS. 2A, 2B and 2C are portions of a single circuit diagram of the preferred embodiment of the present invention. 
    
    
     DESCRIPTION OF PREFERRED EMBODIMENTS 
     Reference will now be made in detail to the present preferred embodiment of the invention, an example of which is illustrated in the accompanying drawings. 
     The flame detection and proof control device of the present invention is depicted in the schematic diagram of FIG. 1. The device shown is designed to detect and prove the presence of flame in a gas-fired system. In accordance with the invention, the device operates at low voltages using redundant circuitry to achieve safe dependable control of gas appliances and other systems. 
     As here embodied, an AC power source is connected across lines 10, 12. In the preferred embodiment, a low voltage 24-volt power source is used. Circuit breaker 14 and regulated DC power source 16 are connected in series with the power source. DC power source 16, for example, typically produces a 12-volt DC output and provides all of the power for the circuitry of the flame detection and proof control device of the present invention. 
     Probe 18 can be a flame rod, well known in the art, in which current changes as a function of the presence of flame. Each of these types of flame-probes produces first and second signals corresponding respectively to no-flame and flame conditions. 
     In the preferred embodiment, an AC voltage signal tapped off at point A is applied through capacitor 20 to probe 18. DC terminal 22 may be grounded through resistance 24 and diode 26 for testing purposes. In the absence of flame, the AC input is not rectified and a first probe signal of zero volts is present at terminal 22. In the presence of flame, a second probe signal which is negative is produced by rectifying the AC input. 
     It is preferred that circuit means 28 comprise substantially identical circuits 30 and 30&#39;. They provide a redundancy which adds to the safety of the flame-proof control device, as will be described below. For convenience, circuit 30 is described below with the understanding that circuit 30&#39; has corresponding elements labeled identically. 
     As here embodied, inverter 32 is connected with DC terminal 22 of probe 18. The output of inverter 32 is connected to inverter 34, one input of NAND GATE 36 and the set terminal of flip-flop 38. The output of inverter 34 is connected to a first terminal of NAND GATE 40 and to a first terminal of NAND GATE 42. 
     As here embodied, delay circuit 44, which provides a start delay of a set time period to allow for ignition of the gas, is connected to the second input of NAND GATE 40, to the reset terminal of flip-flop 38 and to the set terminal of flip-flop 46. The time period is set typically at ten seconds to allow sufficient time for ignition of the gas. The timing of delay circuit 44 is initiated by turn-on of the power source. 
     The output of NAND GATE 40 is connected through capacitor 48 to the reset terminal of flip-flop 46. A 12-volt DC signal also is applied through resistance 50 to the set terminal of flip-flop 46. The second terminal of NAND GATE 36 is connected with the Q terminal of flip-flop 46. 
     Preferably, a circuit breaker control circuit is provided for opening breaker 14 if no flame is detected after the set time period. As here embodied, the control circuit includes a second delay circuit 52 connected to the output terminal of NAND GATE 42 which is connected to the input of inverter 54. The output of inverter 54 is connected to circuit breaker 14. The timing of delay circuit 52 is initiated by turn-on of the power source. 
     The respective Q and Q output terminals of flip-flops 46 and 38 are connected to the input terminals of NAND GATE 56, which in turn, has an output connected to NAND GATE 58. The second terminal of NAND GATE 58 is connected through resistance 60 to terminal A to which the AC voltage signal is applied. NAND GATE 58 is connected through amplifier 62 to detector circuit 64. First and second output signals of circuit means 28 are produced at the output of inverter 62. 
     As here embodied, detector circuit 64 is connected to relay 66. 
     The operation of the circuit of FIG. 1 will now be described. Upon application of power to terminals 10 and 12, relay 66 is activated, thereby operating on some element of the system such as opening a gas valve (not shown). The present invention will be discussed in terms of controlling the opening and closing of a gas valve, although it will be appreciated that other elements of a system such as a switch could be controlled by the present device. 
     If an input signal to circuit means 28 derived from probe 18 indicates a flame condition, relay 66 will remain energized holding such gas valve open until power is removed from terminals 10 and 12. If power is removed from the circuit, relay 66 is de-energized and the gas valve closed. 
     if the input signal derived from flame probe 18 indicates a no-flame condition after the set time period for ignition, relay 66 is deactivated, closing the gas valve and simultaneously the control circuit for circuit breaker 14 trips the breaker. By proper design and sizing of the elements of delay circuit 44 the delay time can be adjusted by typically is approximately 10 seconds. If, after ignition has been accomplished and the relay 66 has been activated beyond the set period of time, for any reason the flame is extinguished, relay 66 will deactivate, closing the gas valve and simultaneously the circuit breaker 14 responsive to the control circuit will open. 
     Referring to the schematic diagram shown in FIG. 1, the operation of this preferred embodiment can clearly be described. The AC voltage source is applied across lines 10 and 12, and the DC regulated power supply provides power to the circuit. During the set time delay provided by circuit 44 and while there is a no-flame indication at terminal 22 of probe 18, relay 66 is activated and the gas valve is opened. As here embodied, the no-flame signal at terminal 22 is a zero DC voltage. At this time, delay circuit 52 provides a low output on inverter 54 during the set time period for ignition. 
     Delay circuit 44 preferably assures a low input on the reset terminal of flip-flop 38, the set terminal of flip flop 46 and on one input to NAND GATE 40 during the set time period. During this initial ignition period, an AC voltage signal is applied to probe 18 through capacitor 20. The Q output of flip-flop 46 stays low for the set time period, i.e., approximately 10 seconds in the typical case, and the Q output of flip-flop 38 is locked low during the initial ignition period. Consequently, the output of NAND GATE 56 is high and a first signal output (high) is produced by circuit 30. The high signal is applied to detector 64 and relay 66 remains activated. 
     If during the ignition period, i.e., during the set time period of approximately 10 seconds set by delay circuit 44, flame is detected by probe 18, a negative voltage will appear at flame probe input 22. This causes the output of inverter 34 to go low and NAND GATE 40 to go high. However, since flip-flop 46 is timing under the control of timing circuit delay 44 there is no effect on the outputs of flip-flop 46. The Q output of flip-flop 46 stays low. 
     The low voltage at flame probe input 22 also causes the output of inverter 32 to go high, the output of NAND GATE 36 to go low and, as a consequence, the Q output of flip-flop 38 to latch high. Consequently, as long as the flame detection and proof control device detects flame, a first output signal (high) is produced by circuit 30 and relay 66 remains activated. 
     If after the completion of the set time period, no flame is detected by probe 18, flip-flop 46 will reset and the respective Q output will be high. As a consequence, the output of NAND GATE 56 would be low if the Q output of flip-flop 38 is high, indicating no flame. This causes deactivation of relay 66 and closing of the gas valve. The same action occurs if there was a flame but that flame was subsequently lost. 
     As here embodied, as long as there is a signal at probe input terminal 22 indicative of the presence of a flame, or flip-flop 46 is still timing responsive to delay circuit 44, a low is on one of the inputs of NAND GATE 42 and its output is high. But after the set time period for ignition is completed and flip-flop 46 is no longer timing, both inputs to NAND GATE 42 will be high if a no-flame condition is detected by probe 18 and zero volts appears at DC terminal 22. Relay 66 would then deactivate. After the set time period of delay circuit 52, the low output of NAND GATE 42 switches the output of inverter 54 high, thereby causing circuit breaker 14 to open. Thus, when there is a no-flame indication after the end of the set time period, relay 66 is deactivated closing the gas valve and circuit breaker 14 opens. 
     It is preferred that circuit 30, responsive to the probe output signals, produce a first output signal (high) during the set time period, produce a second output signal (low) after the set time period and during application of the first probe signal indicative of a no-flame condition and produce the first output signal (high) after the set time period and during application of the second probe signal indicative of a flame condition. Relay 66 is activated during the set time period to allow time for gas ignition. If for any reason, ignition is not effected during the set time period, relay 66 is deactivated and circuit breaker 14 is opened. 
     It will be understood that circuit 30&#39; operates in a manner identical to that of circuit 30 and builds a safety redundancy into the flame detection and proof control device. The first output signal (high) must appear at the respective outputs of circuits 30 and 30&#39; to activate relay 66 through detector circuit 64. Otherwise, it is deactivated and the associated gas valve is closed providing complete and safe operation. 
     Reference is now made to FIGS. 2A and 2B which show a circuit diagram of the preferred embodiment. It is to be understood that circuit connections are made between FIGS. 2A and 2B at those terminals labeled A, B, and C. It should further be understood that the circuit diagram of FIGS. 2A and 2B implement the functional block diagram of FIG. 1. 
     It is preferred that flame probe 102 be connected to the AC power source through capacitance 104. AC power is applied across lines 106 and 108 through transformer 110 and circuit breaker 112. The AC voltage signal is taken off at point C (FIG. 2B) and applied to flame probe 102 through capacitance 104. 
     As here embodied, probe 102 produces first and second signals corresponding respectively to no-flame and flame conditions at terminal 114. Probe 102 may be grounded through resistance 116 and diode 118 for testing purposes, if desired. The DC terminal 114 is connected to probe 102 through resistance 120 with capacitance 122 and resistance 124 connected to ground. 
     As here embodied, circuit means is comprised of substantially duplicate circuits 126 and 126&#39;. Such duplicate circuitry builds in redundancy to the circuit. For purposes of description, circuit 126 is described below. 
     Terminal 114 is connected to resistance 128. The other end of resistance 128 is connected to grounded capacitance 130 and diode 132. Diode 132 is connected through JFET 134 to resistance 136 and NAND GATE 138. It is preferred that NAND GATE 138 and the other NAND GATES included in the circuit means be implemented by CMOS devices such as the Motorola MC14011. NAND GATE 138 functions as an inverter. NAND GATE 138 is connected to the respective first terminals of NAND GATES 140 and 142. The second input terminal of NAND GATE 142 is connected to the junction of diodes 144 and 146 and capacitance 148. The second input terminal of NAND GATE 140 is connected to an input terminal of NAND GATE 150 of flip-flop 46. The output of NAND GATE 140 is connected at junction B of FIG. 2B. The second input terminal of NAND GATE 150 is connected through capacitance 152 to the output terminal of NAND GATE 142. 
     As here embodied, the output of JFET 134 is also connected to an input terminal of NAND GATE 154 and resistance 156. The second input terminal of NAND GATE 154 is connected to output terminal of NAND GATE 150 and to a terminal of delay circuit 44. Delay circuit 44 is comprised of serially connected resistance 158, capacitance 160 and resistance 162. 
     The output of NAND GATE 154 is connected to the reset terminal of flip-flop 38. Both terminals of NAND GATE 164 are connected through resistance 166 to the DC voltage source and through capacitance 168 to ground. The output of NAND GATE 164 is connected to delay circuit 44 through diode 170 and resistor 172. As here embodied, delay circuit 44 is comprised of resistances 158 and 162 and capacitance 160. 
     Flip-flop 46 is comprised of NAND GATES 150 and 174. Flip-flop 38 is comprised of NAND GATES 176 and 178. Each of these flip-flops is connected in a conventional manner. The respective Q terminal of flip-flop 38 and Q terminal of flip-flop 46 are connected to the inputs of NAND GATE 180. The output of NAND GATE 180 is connected to one terminal of NAND GATE 182, the other input terminal of which is connected through resistance 184 to the DC source and through resistance 186 to the AC signal at junction C on FIG. 2B. 
     The output of the circuit means comprised of circuits 126 and 126&#39; are respectively taken at the outputs of NAND GATES 182 and 182&#39;. These respective outputs are applied to detector circuit 64. As here embodied, detector circuit 64 is comprised of resistance 188 connected to transistor 190. Transistors 190 and 192 are connected in a current amplifier arrangement to amplify the current signal received from NAND GATE 182. Likewise, transistors 196 and 198 connected through resistance 188&#39; to the output of NAND GATE 182&#39; are connected in an inverted manner to act also as current amplifiers for current from NAND GATE 182&#39;. Resistances 200 and 202 limit current to protect the respective transistors. The junction of resistances 200 and 202 is connected to the output of detector circuit 64 through capacitance 204 and diode 206 to relay 66. 
     The redundant circuit 126&#39; in FIG. 2B performs in the same manner as does the previously-described circuit 126 seen in FIG. 2A. Furthermore, each primed element in circuit 126&#39; operates as its unprimed counterpart does in circuit 126. 
     Accordingly, the output of probe 102 at terminal 114 is connected to JFET 134&#39; by resistor 128&#39; and diode 132&#39;. Capacitor 130&#39; connects between the cathode of diode 132&#39; and ground. The source of JFET 134&#39; is connected to +D.C. by resistor 136&#39; and provides both inputs to NAND gate 138&#39;. The source of JFET 134&#39; is also an input to NAND gate 154&#39;, that input also being connected by resistor 156&#39; to delay circuit 44&#39;. 
     Delay circuit 44&#39; comprises diodes 146&#39; and 144&#39; connected in series, with the cathode of diode 144&#39; connected to +D.C. Delay circuit 44&#39; also includes resistor 147&#39;, which shunts diode 144&#39;, and capacitor 148&#39; which connects between ground and the junction of diodes 144&#39; and 146&#39;. 
     The other input of NAND gate 154&#39; is an output from flip-flop 46&#39;. The output of NAND gate 154&#39; is connected to the reset terminal of flip-flop 38&#39;, the set input of flip-flop 46&#39; is connected to the anode of diode 146&#39; in delay circuit 44&#39;. Flip-flop 38&#39; comprises cross-coupled NAND gates 176&#39; and 178&#39;. 
     The output of NAND gate 138&#39; referred to above, provides one input to NAND gate 142&#39;, the other input being the signal at the junction of diodes 144&#39; and 146&#39; in delay circuit 44&#39;. The output of NAND gate 142&#39; is connected through capacitor 152&#39; and a pullup resistor to the reset input of flip-flop 46&#39;. 
     Flip-flop 46&#39; comprises NAND gates 150&#39; and 174&#39;. The output of NAND gate 150&#39; is, as mentioned above, an input to NAND gate 154&#39;. The output of NAND gate 150&#39; is also connected to ground through a series circuit comprising resistor 158&#39;, capacitor 160&#39;, and resistor 162&#39;. 
     One input of NAND gate 174&#39; in flip-flop 46&#39; is the signal at the junction of diodes 144&#39; and 146&#39; in delay circuit 44&#39;. The other input is the signal at the output of NAND gate 164&#39; after it passes through diode 170&#39; and resistor 172&#39;. The inputs of NAND gate 164&#39; are connected to +D.C. through resistor 166&#39; and to ground through capacitor 168&#39;. 
     The Q output of flip-flop 46&#39; and the Q output of flip-flop 38&#39;, or the outputs of NAND gates 174&#39; and 176&#39;, respectively, are the inputs to NAND gate 180&#39;. The output of NAND gate 180&#39; is one input to NAND gate 182&#39;, whose other input is a node connected through resistor 184&#39; to +D.C. and through resistor 186&#39; to terminal C. 
     Referring now to the circuit portion shown in FIG. 2B, the power supply for the electronic circuit of this invention consists of diode 210, capacitor 212, resistance 214 and integrated circuit voltage regulator 216. The DC voltage, typically at 12 volts DC, is taken off at terminal 218 to be applied to the circuit where indicated. 
     As here embodied, the circuit breaker control circuit 219 controls the tripping of breaker 112. Delay circuits 52 and 52&#39; are respectively comprised of serially connected resistances 220 and 222 and capacitance 224 and resistances 220&#39; and 222&#39; and capacitance 224&#39;. The respective delay circuits 52 and 52&#39; are connected to NAND GATES 226 and 226&#39;. The outputs of NAND GATES 226 and 226&#39; are respectively connected to terminal 228 through diodes 230 and 230&#39;. Transistor 232, connected at terminal 228 through resistance 234, acts as a switch to trigger SCR 238. The emitter of transistor 232 is connected to resistance 240, whose second end is connected to the gate of SCR 238 and to resistance 242. The anode of SCR 238 is connected to resistance 244. 
     The operation of the circuit of FIGS. 2A and 2B is described below. DC voltage is applied to the circuit by the regulated source 216. Resistance 147 and capacitance 148 provide a very short time delay. Capacitance 148 holds the inputs of NAND GATES 142, 174 and 176 low during turn-on in order to assure positive outputs. After capacitance 148 charges, it triggers the input of NAND GATE 142, starting the timing sequence. Resistance 162 normally keeps the input at NAND GATE 174 low. Upon triggering, the output of NAND GATE 150 goes high and the high is applied to the input of NAND GATE 174 through resistance 158 and capacitance 160 and resistance 162. A high output of NAND GATE 176 is assured by a low on the input of NAND GATE 176 and a high on the input of NAND GATE 178 until a flame is detected and input to NAND GATE 178 goes low. Then NAND GATE 176 will switch low and stay low as long as the flame is detected. 
     The output of NAND GATE 140 cannot go low during the timing of the set time period or in the presence of a low signal input indicating the presence of flame. During the set time period and before flame detection, the input to NAND GATE 180 is held low by the output of flip-flop 46 which, in turn, keeps the output of NAND GATE 180 high. This allows the AC signal to control operation of NAND GATE 182. 
     NAND GATE 164 acts as a timer. The inputs are held low when supply voltage is applied and the output is held high for the set time period, typically ten seconds. The set time period is determined by the values of the elements of delay circuit 44. Diode 170 blocks this high from the input of NAND GATE 174. After the set time period, the output of NAND GATE 164 goes low, shunting resistance 162 with resistance 172 and creating a drop-out time of approximately 3 seconds, dependent on circuit element values, should a loss of flame detection occur. 
     As here embodied, the detector circuit 64 comprises transistors 180 and 192 connected in a current amplifier arrangement to amplify current from NAND GATE 182. Transistors 196 and 198 are similarly connected, only in an inverted arrangement. The resistances 200 and 202 limit current to protect the respective transistors. When both transistor arrangements are conductive, a first signal (high) is generated at junction 203. If either or both transistor arrangements are nonconductive, a second signal (low) is generated at junction 203. Capacitance 204 couples the amplified current to a voltage doubler comprised of diodes 206 and 208 which is filtered by capacitance 207. The voltage across capacitance 207 activates relay 66 upon turn-on of the supply voltage. 
     If a flame is detected during the set time period, a negative voltage is applied to the gate of JFET 134 causing it to stop conducting. Input to NAND GATES 154 and 176 then go positive. The output of NAND GATE 154 goes low setting the output of flip-flop 38 low. This assures a continued high on the output of NAND GATE 180 as long as flame is present and power is supplied. 
     It will be apparent to those skilled in the art that various modifications and variations could be made in the invention without departing from the scope or spirit of the invention.