Patent Publication Number: US-2023135057-A1

Title: Dual sided molded package with varying interconnect pad sizes and uniform exposed solderable area

Description:
INCORPORATION BY REFERENCE TO ANY PRIORITY APPLICATIONS 
     Any and all applications for which a foreign or domestic priority claim is identified in the Application Data Sheet as filed with the present application are hereby incorporated by reference under 37 CFR 1.57. 
     BACKGROUND 
     Technical Field 
     Embodiments of this disclosure relate to packaging of circuit devices, such as radio frequency modules that can be mounted on a circuit board, and more particularly to packaging of circuit devices with varying interconnect pad sizes. 
     Description of Related Technology 
     Circuit devices, such as radio frequency modules, can be implemented in a packaged module. Such devices can be connected to a mother board (e.g., of an electronic device) via solder balls. Drop tests are often performed to test the connection between the mother board and the circuit devices (e.g., the connection provided by the solder balls). As the size of the pads of circuit boards (e.g., mother boards) in electronic devices decrease (e.g., to decrease the size of the electronic device), which require a corresponding decrease in size of the connections in packages mounted to the circuit board, stresses during drop tests result in increased failure rate of packages. 
     SUMMARY OF CERTAIN INVENTIVE ASPECTS 
     The innovations described in the claims each have several aspects, no single one of which is solely responsible for its desirable attributes. Without limiting the scope of the claims, some prominent features of this disclosure will now be briefly described. 
     In accordance with one aspect of the disclosure, a packaged circuit device is provided with varying solder interconnect pad sizes that improve a drop test performance of the packaged circuit device. 
     In accordance with one aspect of the disclosure, a packaged circuit device is provided with a plurality of pads of varying size configured to receive solder interconnect members thereon. The package has one or more first pads that have a surface area (e.g., exposed or solderable surface area) that is larger than a surface area (e.g., exposed or solderable surface area) of the one or more second pads of the package. In one implementation, the one or more first pads are proximate the corners of the package. 
     In accordance with one aspect of the disclosure, a packaged circuit device is provided with a plurality of pads of varying size configured to receive solder interconnect members thereon. The package has one or more first pads that have a surface area (e.g., exposed or solderable surface area) that is larger than a surface area (e.g., exposed or solderable surface area) of the one or more second pads of the package. In one implementation, the one or more first pads are proximate the corners of the package. The package includes one or more first solder interconnect members configured attached to the one or more first pads and one or more second solder interconnect members attached to the one or more second pads, wherein the one or more first solder interconnect members have an exposed solderable area that is smaller than the surface area (e.g., exposed or solderable surface area) of the one or more first pads and wherein the one or more second solder balls have an exposed solderable area that is substantially equal to the surface area (e.g., exposed or solderable surface area) of the one or more second pads. 
     In accordance with one aspect of the disclosure, a packaged circuit device is provided with a plurality of pads of varying size configured to receive solder interconnect members thereon. The package has one or more first pads that have a surface area (e.g., exposed or solderable surface area) that is larger than a surface area (e.g., exposed or solderable surface area) of the one or more second pads of the package. In one implementation, the one or more first pads are proximate the corners of the package. The package includes one or more first solder interconnect members configured attached to the one or more first pads and one or more second solder interconnect members attached to the one or more second pads. The one or more first solder interconnect members have an exposed solderable area that is substantially equal to the surface area (e.g., exposed or solderable surface area) of the one or more first pads and wherein the one or more second solder interconnect members have an exposed solderable area that is substantially equal to the surface area (e.g., exposed or solderable surface area) of the one or more second pads. 
     In accordance with one aspect of the disclosure, a dual sided molded package is provided. The dual sided molded package comprises a substrate having a first side and an opposite second side. A plurality of pads are attached to the second side of the substrate and include one or more first pads having a first surface area and one or more second pads having a second surface area that is smaller than the first surface area. A plurality of electrically conductive interconnect members are attached to the plurality of pads and include one or more first interconnect members attached to the one or more first pads and having a first solderable area and one or more second interconnect members attached to the one or more second pads and having a second solderable area. The first solderable area is smaller than the first surface area and the second solderable area is substantially equal to the second surface area. 
     In accordance with another aspect of the disclosure, a wireless device is provided. The wireless device comprises a circuit board having a plurality of metal pads with a uniform surface area, and a dual sided molded package mounted on the circuit board. The dual sided molded package includes a substrate having a first side and an opposite second side. A plurality of pads are attached to the second side of the substrate and include one or more first pads having a first surface area and one or more second pads having a second surface area that is smaller than the first surface area. A plurality of electrically conductive interconnect members are attached to the plurality of pads and include one or more first interconnect members attached to the one or more first pads and having a first solderable area and one or more second interconnect members attached to the one or more second pads and having a second solderable area. The first solderable area is smaller than the first surface area and the second solderable area is substantially equal to the second surface area. The first interconnect members and the second interconnect members are connected to the plurality of metal pads of the circuit board, the first solderable area and the second solderable area being substantially equal to the uniform surface area of the plurality of metal pads. 
     In accordance with another aspect of the disclosure, a method of making a dual sided molded package is provided. The method includes forming or providing a substrate having a first side and an opposite second side. A plurality of pads are attached to the second side of the substrate and include one or more first pads having a first surface area and one or more second pads having a second surface area that is smaller than the first surface area. The method also includes depositing a plurality of electrically conductive interconnect members on the plurality of pads, including depositing first interconnect members on the first pads and second interconnect members on the second pads, the first interconnect members being larger than the second interconnect members. The method also includes removing a portion of an overmolding and a portion of the first interconnect members and a portion of the second interconnect members. The method also includes reflowing a remaining portion of the first interconnect members to form first final interconnect members having a first solderable area and reflowing a remaining portion of the second interconnect members to form second final interconnect members having a second solderable area, the first solderable area being smaller than the first surface area and the second solderable area being substantially equal to the second surface area. 
     In accordance with one aspect of the disclosure, a dual sided molded package is provided. The dual sided molded package comprises a substrate having a first side and an opposite second side. A plurality of pads are attached to the second side of the substrate and include one or more first pads having a first surface area and one or more second pads having a second surface area that is smaller than the first surface area. A plurality of electrically conductive interconnect members are attached to the plurality of pads and include one or more first interconnect members attached to the one or more first pads and having a first solderable area and one or more second interconnect members attached to the one or more second pads and having a second solderable area. The first solderable area is substantially equal to the first surface area and the second solderable area is substantially equal to the second surface area. 
     In accordance with another aspect of the disclosure, a wireless device is provided. The wireless device comprises a circuit board having a plurality of metal pads including one or more first metal pads and one or more second metal pads, the one or more first metal pads having a larger surface area than a surface area of the second metal pads, and a dual sided molded package mounted on the circuit board. The dual sided molded package includes a substrate having a first side and an opposite second side. A plurality of pads are attached to the second side of the substrate and include one or more first pads having a first surface area and one or more second pads having a second surface area that is smaller than the first surface area. A plurality of electrically conductive interconnect members are attached to the plurality of pads and include one or more first interconnect members attached to the one or more first pads and having a first solderable area and one or more second interconnect members attached to the one or more second pads and having a second solderable area. The first solderable area is substantially equal to the first surface area and the second solderable area is substantially equal to the second surface area. The first interconnect members and the second interconnect members are connected to the plurality of first metal pads and second metal pads, respectively, first solderable area being substantially equal to the surface area of the first metal pads, the second solderable area being substantially equal to the surface area of the second metal pads. 
     In accordance with another aspect of the disclosure, a method of making a dual sided molded package is provided. The method includes forming or providing a substrate having a first side and an opposite second side. A plurality of pads are attached to the second side of the substrate and include one or more first pads having a first surface area and one or more second pads having a second surface area that is smaller than the first surface area. The method also includes depositing a plurality of electrically conductive interconnect members on the plurality of pads, including depositing first interconnect members on the first pads and second interconnect members on the second pads, the first interconnect members being larger than the second interconnect members. The method also includes removing a portion of an overmolding and a portion of the first interconnect members and a portion of the second interconnect members. The method also includes reflowing a remaining portion of the first interconnect members to form first final interconnect members having a first solderable area and reflowing a remaining portion of the second interconnect members to form second final interconnect members having a second solderable area, the first solderable area being substantially equal to the first surface area and the second solderable area being substantially equal to the second surface area. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Embodiments of this disclosure will now be described, by way of non-limiting example, with reference to the accompanying drawings. 
         FIG.  1 A  is a schematic side view of a package following a bottom overmolding step. 
         FIG.  1 B  is a schematic side view of the package following removal of bottom overmolding. 
         FIG.  1 C  is a schematic side view of the package following reflow of solder interconnect members. 
         FIG.  2    is a schematic enlarged view of a solder interconnect members connected to a pad of the package in  FIG.  1 C . 
         FIG.  3    is a schematic side view of the solder interconnect members in  FIG.  2    opposite a pad on a mother board to which the solder interconnect members is connected. 
         FIG.  4    is a schematic bottom view of the package of  FIG.  1 C . 
         FIG.  5 A  is a schematic side view of two different sized solder interconnect members connected to different sized pads of a package following a bottom overmolding step. 
         FIG.  5 B  is a schematic side view of the different sized solder interconnect members and pads of the package in  FIG.  5 A  of the package following removal of bottom overmolding. 
         FIG.  5 C  is a schematic side view of the solder interconnect members and pads of  FIG.  5 B  following reflowing of the solder interconnect members, the solder interconnect members shown opposite pads on a mother board to which the solder interconnect members are connected. 
         FIG.  5 D  is a schematic plan view of a bottom of a substrate showing the pads on the substrate, in accordance with one implementation. 
         FIG.  5 E  is a schematic plan view of a bottom of a substrate showing the pads on the substrate, in accordance with one implementation. 
         FIG.  6    shows a process for forming the solder interconnect members in  FIG.  5 C . 
         FIG.  7 A  is a schematic side view of two different sized solder interconnect members connected to different sized pads of a package following a bottom overmolding step. 
         FIG.  7 B  is a schematic side view of the different sized solder interconnect members and pads of the package in  FIG.  7 A  of the package following removal of bottom overmolding. 
         FIG.  7 C  is a schematic side view of the solder interconnect members and pads of  FIG.  7 B  following reflowing of the solder interconnect members, the solder interconnect members shown opposite pads on a mother board to which the solder interconnect members are connected. 
         FIG.  8    shows a process for forming the solder interconnect members in  FIG.  7 C . 
         FIG.  9    is a is a schematic bottom view of a package having the solder interconnect members in  FIG.  7 C . 
         FIG.  10    is a schematic block diagram of a packaged module that includes a filter with an acoustic wave device according to an embodiment. 
         FIG.  11    is a schematic block diagram of a packaged module that includes a filter with an acoustic wave device according to another embodiment. 
         FIG.  12 A  is a schematic block diagram of a wireless communication device that includes a filter with an acoustic wave device according to an embodiment. 
         FIG.  12 B  is a schematic block diagram of a wireless communication device that includes a filter with an acoustic wave device according to another embodiment. 
     
    
    
     DETAILED DESCRIPTION 
     The following description of certain embodiments presents various descriptions of specific embodiments. However, the innovations described herein can be embodied in a multitude of different ways, for example, as defined and covered by the claims. In this description, reference is made to the drawings where like reference numerals can indicate identical or functionally similar elements. It will be understood that elements illustrated in the figures are not necessarily drawn to scale. Moreover, it will be understood that certain embodiments can include more elements than illustrated in a drawing and/or a subset of the elements illustrated in a drawing. Further, some embodiments can incorporate any suitable combination of features from two or more drawings. 
       FIGS.  1 A- 1 C  show a packaged circuit device or package  50  in different stages during the manufacturing process of the package  50 . The package  50  has a first component (e.g., a shielded package)  10 . In one implementation, the package  50  optionally has a second component  20  attached to or mounted to the first component  10 , for example by electrical connectors such as interconnect members  25  (e.g., solder balls, solder joints, metallic connection posts), so that the package  50  is a dual-sided package. In other implementations, the second component  20  is excluded. The first component  10  and/or second component  20  can include one or more circuit components, such as dies (e.g., semiconductor dies), filters, amplifiers (e.g., low noise, power), switches, memory, processors, transceivers and control circuits. In one implementation, the package  50  can include circuit components that facilitate transmission and/or reception of radio frequency (RF) signals. The first component  10  can include an overmold structure (e.g., surrounding, enveloping the one or more circuit components) to facilitate radio frequency shielding of at least a portion of the one or more circuits of the first component  10 . 
     A plurality of electrically conductive interconnect members  30  (e.g., solder balls, solder joints, metallic connection posts) can be connected to the first component  10 , for example in an array, such as a ball grid array (BGA), as further described below. As shown in  FIGS.  1 A- 1 C , at least a portion of the second component  20  and the interconnect members  30  can be covered by an overmold (e.g., a bottom overmold structure)  27 . The bottom overmold  27  can facilitate radio frequency shielding of at least a portion of the second component  20  (e.g., of at least a portion of the one or more circuit components of the second component  20 ). Though the figures show the interconnect members  30  as ball shaped, one of skill in the art will recognize the interconnect members can have other suitable shapes, such as cylindrical posts. 
       FIG.  1 A  shows the bottom overmold  27  completely covering the interconnect members  30  (e.g., of solder material, such as solder balls having a generally circular shape) and second component  20 .  FIG.  1 B  shows at least a portion of the bottom overmold  27  and interconnect members  30  removed (e.g., via ablation, via grinding) to expose at least a portion of the interconnect members  30  or through-mold connections through the bottom overmold  27 . As shown in  FIG.  1 B , interconnect members  30 , following the removal of said portion of the bottom overmold  27  and material of the interconnect members  30 , where the interconnect members  30  are ball shaped, attain a non-spherical shape  30 ′ (e.g., a generally hemispherical shape, a spheric section).  FIG.  1 C  shows the interconnect members  30 ″ or through-mold connections after a reflow process in which the interconnect members  30 ′ change in shape from the non-spherical shape to a generally spherical shape. The interconnect members  30 ″ protrude past a bottom surface  28  of the bottom overmold  27  and have a shape (e.g., volume) that is smaller than a shape (e.g., volume) of the interconnect members  30 , so that a gap  29  exists between the bottom overmold  27  and the interconnect member  30 ″ (e.g. a gap about the circumference of the interconnect member  30 ″). 
       FIG.  2    is an enlarged view of a portion of the package  50  in  FIG.  1 C , which shows that the bottom of the first component (e.g., a shielded package)  10  includes a substrate  12  (e.g., a packaging substrate). One or more pads  14  are disposed on (e.g., attached to, formed on) the bottom of the first component  10  (e.g., attached to the substrate  12 ). The number of pads  14  corresponds to the number of interconnect members  30 ″. In the illustrated embodiment, the interconnect members  30 ″ are solder balls. The pads  14  can be made of metal or a metal or another suitable material that provides electrical and/or thermal conductivity between the solder balls  30 ″ and the first component  10  (e.g., the one or more circuit components of the first component  10 ) and/or the second component  20 . A solder mask  16  is disposed over at least a portion of the pad  14  to define an area where the interconnect member (e.g., solder ball)  30 ,  30 ′,  30 ″ may be applied (e.g., attached, dropped, deposited, formed) over the pad  14  and solder mask  16 . In some implementations, the pad  14  can be non-solder mask defined or metal defined. 
       FIG.  3    shows the enlarged partial view of the package  50  in  FIG.  2    opposite a circuit board  40  (e.g., phone board, mother board) on which the package  50  is mounted. The circuit board  40  can have one or more pads  42  disposed on (e.g., attached to, formed on) the circuit board  40 . The number of pads  42  can correspond to the number of pads  14 , which correspond to the number of interconnect members  30 ″ (e.g., solder balls). The pads  42  can be made of metal or a metal or another suitable material that provides electrical and/or thermal conductivity between the interconnect members  30 ″ and the circuit board  40 . 
     The package  50  mounts to the circuit board  40  via a connection between the interconnect members  30 ″ and the pads  42 . For example, at least a portion of the interconnect members  30 ″ can be deposited/melted onto the pads  42  (e.g., by applying heat to the interconnect members  30 ″ causing them to reflow). The package  50  can mount to the circuit board  40  so that the bottom surface  28  of the bottom overmold  27  is spaced apart (e.g., by a gap) from the top surface  43  of the circuit board  40 , which can inhibit (e.g., prevent) damage to the second component  20  due to displacement of the package  50  relative to the circuit board  40  (e.g., due to flexing or dropping of the circuit board  40  with the package  50  mounted on it, or dropping of an electronic device, such as a smartphone incorporating the circuit board  40  and package  50 ). In one implementation, the pads  42  of the circuit board  40  have a uniform size (e.g., width) W 1  that is substantially equal to (e.g., coincides with) a size (e.g., width at the centerline, diameter at widest portion) of the interconnect members  30 ″ (e.g., the solder balls  30 ″ have a uniform size), which match the size (e.g., width) of the pads  14  (e.g., the pads  14  have a uniform size). 
       FIG.  4    shows a bottom view of the package  50  in  FIG.  1 C . As discussed above, the interconnect members  30 ″ can have a uniform size (e.g., substantially the same width at the centerline, diameter at widest portion) W 1 . When the package  50  is subjected to a drop test, the stress applied to the connections (e.g., through-mold connections, solder balls  30 ″) of package  50  increases with distance from the center O of the package  50 . Therefore, the interconnect members  30 ″ at the corners C of the package  50  experience a higher level of stress from a drop test, and are therefore more likely to fail (e.g., exhibit cracks in the connection between the solder balls  30 ″ and the pads  42  or pads  14 ), as compared to interconnect members  30 ″ closer to the center of the package  50 . With reference to  FIG.  4   , the interconnect members  30 ″ (e.g., solder balls) at the corner C would experience greater stress during a drop test than the interconnect members  30 ″ proximate the corner C (e.g., than the solder balls  30 ″ at a position C 1  next to the corner along the edge of the package  50 , or at position C 2  along a diagonal between the corner C and the center O of the package  50 ). 
     In accordance with one aspect of the disclosure, the inventor has recognized that failure rates of packages, such as the package  50 , from drop tests can be significantly decreased by increasing the solder joint reliability of at least some (e.g., some, but not all) of the connections between interconnect members (such as solder balls  30 ″) and pads (such as pads  14 ,  42 ) without increasing the size of the interconnect members (such as solder balls  30 ″) relative to pads (e.g., pads  42 ) of the circuit board (e.g., circuit board  40 ). As described further below, in one implementation, the size of one or more pads (e.g., pads  14 ) of the package (e.g., package  50 ) can be increased relative to the size of one or more other pads (e.g., pads  14 ) of the package, while the size (e.g., exposed solderable area) of the interconnect members (e.g., solder balls  30 ″) attached to the pads (e.g., pads  14 ) is uniform and coincides with the size of the pads (e.g., pads  42 ) of the circuit board (e.g., circuit board  40 ) on which the package (e.g., package  50 ) is mounted. 
       FIGS.  5 A- 5 C  are schematic partial enlarged views of interconnect members (e.g., solder balls) connected to different sized pads of a package  50 A in different stages during the manufacturing process of the package  50 A. Some of the features of the package  50 A are similar to features of the package  50  in  FIGS.  1 A- 4   . Thus, reference numerals used to designate the various components of the package  50 A are identical to those used for identifying the corresponding components of the package in  FIGS.  1 A- 4   , except that an “A” has been added to the numerical identifier. Therefore, the structure and description for the various features of the package  50  in  FIGS.  1 A- 4    are understood to also apply to the corresponding features of the package  50 A in  FIGS.  5 A- 5 C , except as described below. 
     The package  50 A differs from the package  50  in that it has one or more first pads  14 A having a first size (e.g., width) W 1  and one or more second pads  14 A′ having a second size (e.g., width) W 2  that is greater than the first size W 1 . In one implementation, the pads  14 A,  14 A′ have a circular shape, as shown in  FIG.  5 D . In another implementation the pads  14 A and/or pads  14 A′ have a square shape or other suitable shape, as shown in  FIG.  5 E .  FIG.  5 A  shows the bottom overmold  27 A completely covering one or more first interconnect members  30 A (e.g., solder balls) and one or more second interconnect members  32 A (e.g., solder balls) that are greater in size than the one or more first interconnect members  30 A. In one implementation, the interconnect members  30 A can be spherical and the interconnect members  32 A can be larger spheres. In another implementation, the interconnect members  32 A can be ovoid in shape in the Z direction (e.g., away from the pads  14 A,  14 A′). Though not shown, the package  50 A can have a second component (similar to the second component  20 ).  FIG.  5 B  shows at least a portion of the bottom overmold  27 A and the interconnect members  30 A,  32 A removed (e.g., via ablation, via grinding) to expose at least a portion of the interconnect members  30 A,  32 A or through-mold connections through the bottom overmold  27 A. In one implementation, the bottom overmold  27 A and material of the interconnect members  30 A,  32 A is removed R to a location that coincides with a midline (e.g., meridian) of the interconnect members  30 A, and a location that is past the midline or meridian of the interconnect members  32 A. However, in other implementations, the bottom overmold  27 A and material of the interconnect members  30 A,  32 A is removed R to a different location (e.g., below or above a midline or meridian of the interconnect members  30 A, and a location that is below or above the midline or meridian of the interconnect members  32 A. As shown in  FIG.  5 B , the interconnect members  30 A,  32 A, following the removal of said portion of the bottom overmold  27 A and material of the interconnect members  30 A,  32 A, attain a non-spherical shape  30 A′,  32 A′ (e.g., a generally hemispherical shape, a spheric section). Advantageously, the interconnect members  30 A′,  32 A′ (e.g., following the removal step) have substantially the same volume of solder material. 
       FIG.  5 C  shows the interconnect members  30 A″,  32 A″ or through-mold connections after a reflow process in which the interconnect members  30 A′,  32 A′ change in shape from the non-spherical shape to a generally spherical shape. The interconnect members  30 A″,  32 A″ protrude past a bottom surface  28 A of the bottom overmold  27 A and have a shape (e.g., volume) that is smaller than a shape (e.g., volume) of the interconnect members  30 A,  32 A, respectively, so that a gap  29 A,  29 A′ exists between the bottom overmold  27 A and the interconnect members  30 A″,  32 A″ (e.g. a gap about the circumference of the solder ball  30 A″,  32 A″), where the gap  29 A′ is greater than the gap  29 A. The interconnect members  30 A″,  32 A″ have substantially the same size (e.g., width W 1 , width at the centerline, diameter at widest portion) or exposed solderable area and coincide with the size W 1  of the pads  42  of the circuit board  40 . 
     Advantageously, because the one or more pads  14 A′ have a greater size than the one or more pads  14 A, the connection between the interconnect members  32 A″ (e.g., solder balls) and the pads  14 A′ have a higher strength and therefore a higher solder joint reliability, while the interconnect members  30 A″,  32 A″ (e.g., solder balls) have substantially the same size. Moreover, as the size W 1  or exposed solderable area of the interconnect members  30 A″,  32 A″ is the same and coincides with the size W 1  of the pads  42  of the circuit board  40 , no changes are needed in the size of the pads  42  of the circuit board  40  (e.g., the pads  42  can have a uniform size that coincides with the size W 1  or exposed solderable area of the solder balls  30 A″,  32 A″). In one example, interconnect members  30 A″,  32 A″ can have an exposed solderable area or size (e.g., width at the centerline, diameter at widest portion) W 1  of 250 microns, and the pads  42  of the circuity board  40  can have a size (e.g., width) W 1  of 250 microns. The pads  14 A can also have a size (e.g., width, area) of 250 microns. The pads  14 A′ can have a size (e.g., width) of between about 300 microns and 350 microns (e.g., about 44% to 96% larger area than that of the pads  14 A). In one implementation, the pads  14 A′ are located at one or more (e.g., all) corners C (see  FIG.  4   ) of the package  50 A. In another implementation, the pads  14 A′ are additionally or alternatively located at positions C 1  next to the corner C (e.g., along the edge of the package  50 A). In another implementation, the pads  14 A′ are additionally or alternatively located at positions C 2  along a diagonal between the corner C and the center O of the package  50 A. In another implementation, the larger pads  14 A′ can additionally or alternatively be located on the substrate  12 A of the package  50 A at locations that require increased thermal dissipation (e.g., from a circuit component attached to the substrate  12 A at that location). In another implementation, the larger pads  14 A′ can additionally or alternatively be located on the substrate  12 A of the package  50 A at locations that require increased current carrying capacity or capability (e.g., from a circuit component attached to the substrate  12 A at that location). 
       FIG.  6    shows a flowchart of a method or process  60  for forming a package, such as the package  50 A of  FIGS.  5 A- 5 C . The method  60  includes the step  62  of forming or providing or forming a substrate with a plurality of first pads (e.g., pads  14 A) and a plurality of second pads (e.g., pads  14 A′), the second pads having a larger size than the first pads. The method  60  also includes the step  64  of depositing a plurality of interconnect members (e.g., solder balls, solder joints, metallic connection posts) on the plurality of pads, including depositing a first plurality of interconnect members (e.g., solder balls  30 A) of a first size on the first pads and depositing a second plurality of interconnect members (e.g., solder balls  32 A) of a second size larger than the first size onto the second pads. In one implementation, depositing the first plurality of interconnect members (e.g., solder balls  30 A) and depositing the second plurality of interconnect members (e.g., solder balls  32 A) occurs simultaneously. In another implementation, depositing the first plurality of interconnect members (e.g., solder balls  30 A) and depositing the second plurality of interconnect members (e.g., solder balls  32 A) occurs sequentially (e.g., the first solder balls deposited first, followed by the depositing of the second solder balls). 
     The method  60  includes the step  66  of removing a portion of a bottom overmold and a portion of the first interconnect members (e.g., solder balls  30 A) and second interconnect members (e.g., solder balls  32 A). In one implementation, the bottom overmold and interconnect members are removed via grinding. In another implementation, the bottom overmold and interconnect members are removed via ablation. In one implementation, the bottom overmold and interconnect members are removed so that the first interconnect members is (e.g., solder balls  30 A) are reduced to the midline or meridian thereof, while the second interconnect members (e.g., solder balls  32 A) are reduced to a location past the midline or meridian thereof (e.g., so that the remaining material, such as volume, of the solder balls  30 A′ and solder balls  32 A′ is substantially equal). The method  60  also includes the step  68  of reflowing a remaining portion of the first interconnect members (e.g., solder balls  30 A′) to form first final interconnect members (e.g., solder balls  30 A″) having a first size or exposed solderable area and reflowing a remaining portion of the second interconnect members (e.g., solder balls  32 A′) to form second final interconnect members (e.g., solder balls  32 A″) having a second size or exposed solderable area, the second size being smaller than the size of the second pads (e.g., pads  14 A′) and the first size for the first final interconnect members (e.g., solder balls  30 A″) being substantially equal to the size of the first pads (e.g., pads  14 A). In one implementation, the first size and second size of the first final interconnect members (e.g., solder balls  30 A″) and second final interconnect members (e.g., solder balls  32 A″) is substantially equal. The method  60  can include other steps. For example, the method can include forming or attaching a shielded package (e.g., first component  10 ,  10 A) on the first side of a substrate (e.g., substrate  12 ,  12 A), and/or forming or providing a second package (e.g., second component  20 ,  20 A) on the second side of the substrate (e.g., substrate  12 ,  12 A) and between two or more of the plurality of interconnect members (e.g., solder balls  30 A,  32 A). In some implementations, the step  68  of reflowing the remaining portion of the first solder balls can be excluded. 
     In accordance with one aspect of the disclosure, the inventor has recognized that failure rates of packages, such as the package  50 , from drop tests can be significantly decreased by increasing the solder joint reliability of at least some (e.g., some, but not all) of the connections between interconnect members (such as solder balls  30 ″) and pads (such as pads  14 ,  42 ) by increasing the size of at least some (e.g., some but not all) of the interconnect members (such as solder balls  30 ″) and their associated pads (e.g., pads  42 ) of the circuit board (e.g., circuit board  40 ), as well as associated pads (e.g., pads  14 ) of the package. As described further below, in one implementation, the size of one or more pads (e.g., pads  14 ) of the package (e.g., package  50 ) can be increased relative to the size of one or more other pads (e.g., pads  14 ) of the package, and the size (e.g., exposed solderable area) of their corresponding interconnect members (e.g., solder balls  30 ″) attached to the pads (e.g., pads  14 ) is also increased relative to other interconnect members, and where the increased size of the pads of the package and interconnect members attached thereto coincide with a larger size of the pads (e.g., pads  42 ) of the circuit board (e.g., circuit board  40 ) on which the package (e.g., package  50 ) is mounted (e.g., as compared with other pads of the circuit board). 
       FIGS.  7 A- 7 C  are schematic partial enlarged views of interconnect members (e.g., solder balls) connected to different sized pads of a package  50 B in different stages during the manufacturing process of the package  50 B. Some of the features of the package  50 B are similar to features of the package  50  in  FIGS.  1 A- 4   . Thus, reference numerals used to designate the various components of the package  50 B are identical to those used for identifying the corresponding components of the package in  FIGS.  1 A- 4   , except that an “B” has been added to the numerical identifier. Therefore, the structure and description for the various features of the package  50  in  FIGS.  1 A- 4    are understood to also apply to the corresponding features of the package  50 B in  FIGS.  7 A- 7 C , except as described below. 
     The package  50 B differs from the package  50  in that it has one or more first pads  14 B having a first size (e.g., width) W 1  and one or more second pads  14 B′ having a second size (e.g., width) W 2  that is greater than the first size W 1 . In one implementation, the pads  14 B,  14 B′ have a circular shape (e.g., similar to pads  14 A,  14 A′ shown in  FIG.  5 D ). In another implementation the pads  14 B and/or pads  14 B′ have a square or rectangular shape or other suitable shape (e.g., similar to pads  14 A,  14 A′ shown in  FIG.  5 E  in plan view).  FIG.  7 A  shows the bottom overmold  27 B completely covering one or more first interconnect members  30 B (e.g., solder balls) and one or more second interconnect members  32 B (e.g., solder balls) that are greater in size than the one or more first interconnect members  30 B. In one implementation, the interconnect members  30 B can be spherical and the interconnect members  32 B can be larger spheres. In another implementation, the interconnect members  32 B can be ovoid in shape. Though not shown, the package  50 B can have a second component (similar to the second component  20 ).  FIG.  7 B  shows at least a portion of the bottom overmold  27 B and the interconnect members  30 B,  32 B removed (e.g., via ablation, via grinding) to expose at least a portion of the interconnect members  30 B,  32 B or through-mold connections through the bottom overmold  27 B. In one implementation, the bottom overmold  27 B and material of the interconnect members  30 B,  32 B is removed R to a location that, for example, coincides with a midline (e.g., meridian) of the interconnect members  30 B, and a location that, for example, is past the midline or meridian of the interconnect members  32 B. As shown in  FIG.  7 B , the interconnect members  30 B,  32 B, following the removal of said portion of the bottom overmold  27 B and material of the interconnect members  30 B,  32 B, attain a non-spherical shape  30 B′,  32 B′ (e.g., a generally hemispherical shape, a spheric section). Advantageously, the interconnect members  32 B′ (e.g., following the removal step) have a larger volume of solder material than the interconnect members  30 B′. 
       FIG.  7 C  shows the interconnect members  30 B″,  32 B″ or through-mold connections after a reflow process in which the interconnect members  30 B′,  32 B′ change in shape from the non-spherical shape to a generally spherical shape (e.g., solder balls). The interconnect members  30 B″,  32 B″ protrude past a bottom surface  28 B of the bottom overmold  27 B and have a shape (e.g., volume) that is smaller than a shape (e.g., volume) of the interconnect members  30 B,  32 B, respectively, so that a gap  29 B,  29 B′ exists between the bottom overmold  27 B and the interconnect members  30 B″,  32 B″ (e.g. a gap about the circumference of the solder ball  30 B″,  32 B″). In one implementation, the gap  29 B′ is greater than the gap  29 B. The interconnect members  32 A″ have a larger size (e.g., width W 2 , width at the centerline, diameter at widest portion) or exposed solderable area than the size (e.g., width W 2 , width at the centerline, diameter at widest portion) of the interconnect members  30 A″. The size W 2  of the interconnect members  32 B″ coincides with the size W 2  of the pads  44 ′ of the circuit board  40 ′ to which the package  50 B couples, and the size W 1  of the interconnect members  30 B″ coincides with the size W 1  of the pads  42 ′ of the circuit board  40 ′. 
     Advantageously, because the one or more pads  14 B′ have a greater size than the one or more pads  14 B, and the interconnect members  32 B″ (e.g., solder balls) have a larger size than the interconnect members  30 B″ (e.g., solder balls), the connection between the interconnect members  32 B″ and the pads  14 B′ have a higher strength and therefore a higher solder joint reliability. In one example, interconnect members  32 B″ can have an exposed solderable area or size (e.g., width at the centerline, diameter at widest portion) W 2  of 230 microns and coincide with the size W 2  of the pads  44 ′ of the circuit board  40 ′, and the interconnect members  30 B″ can have an exposed solderable area or size (e.g., width at the centerline, diameter at widest portion) W 1  of 210 microns and coincide with the size W 1  of the pads  42 ′ of the circuit board  40 ′. 
     In one implementation, the pads  14 B′ and interconnect members  32 B″ (e.g., solder balls) are located at one or more (e.g., all) corners C (see  FIG.  9   ) of the package  50 B. In another implementation, the pads  14 B′ are additionally or alternatively located at positions C 1  next to the corner C (e.g., along the edge of the package  50 B). In another implementation, the pads  14 B′ are additionally or alternatively located at positions C 2  along a diagonal between the corner C and the center O of the package  50 B. In another implementation, the larger pads  14 B′ can additionally or alternatively be located on the substrate  12 B of the package  50 B at locations that require increased thermal dissipation (e.g., from a circuit component attached to the substrate  12 B at that location). In another implementation, the larger pads  14 B′ can additionally or alternatively be located on the substrate  12 B of the package  50 B at locations that require increased current carrying capacity or capability (e.g., from a circuit component attached to the substrate  1 BA at that location). 
       FIG.  8    shows a flowchart of a method or process  70  for forming a package, such as the package  50 B of  FIGS.  7 A- 7 C . The method  70  includes the step  72  of forming or providing or forming a substrate with a plurality of first pads (e.g., pads  14 B) and a plurality of second pads (e.g., pads  14 B′), the second pads having a larger size than the first pads. The method  70  also includes the step  74  of depositing a plurality of interconnect members (e.g., solder balls) on the plurality of pads, including depositing a first plurality of interconnect members (e.g., solder balls  30 B) of a first size on the first pads and depositing a second plurality of interconnect members (e.g., solder balls  32 B) of a second size larger than the first size onto the second pads. In one implementation, depositing the first plurality of interconnect members (e.g., solder balls  30 B) and depositing the second plurality of interconnect members (e.g., solder balls  32 B) occurs simultaneously. In another implementation, depositing the first plurality of interconnect members (e.g., solder balls  30 B) and depositing the second plurality of interconnect members (e.g., solder balls  32 B) occurs sequentially (e.g., the first solder balls deposited first, followed by the depositing of the second solder balls). 
     The method  70  includes the step  76  of removing a portion of a bottom overmold and a portion of the first interconnect members (e.g., solder balls  30 B) and second interconnect members (e.g., solder balls  32 B). In one implementation, the bottom overmold and interconnect members are removed via grinding. In another implementation, the bottom overmold and interconnect members are removed via ablation. In one implementation, the bottom overmold and interconnect members are removed so that the first interconnect members (e.g., solder balls  30 A) are reduced by a first amount, for example to the midline or meridian thereof, while the second interconnect members (e.g., solder balls  32 A) are reduced by a second amount, for example to a location past the midline or meridian thereof (e.g., so that the remaining material, such as volume, of the solder balls  32 B′ is greater than the volume of the solder balls  30 B′). The method  70  also includes the step  78  of reflowing a remaining portion of the first interconnect members (e.g., solder balls  30 B′) to form first final interconnect members (e.g., solder balls  30 B″) having a first size or exposed solderable area and reflowing a remaining portion of the second interconnect members (e.g., solder balls  32 B′) to form second final interconnect members (e.g., solder balls  32 B″) having a second size or exposed solderable area, the second size being substantially equal to the size of the second pads (e.g., pads  14 B′) and the first size for the first final interconnect members (e.g., solder balls  30 B″) being substantially equal to the size of the first pads (e.g., pads  14 B). In one implementation, the first size of the first final interconnect members (e.g., solder balls  30 B″) is smaller than the second size of the second final interconnect members (e.g., solder balls  32 B″). The method  70  can include other steps. For example, the method can include forming or attaching a shielded package (e.g., first component  10 ,  10 A) on the first side of a substrate (e.g., substrate  12 ,  12 A), and/or forming or providing a second package (e.g., second component  20 ,  20 A) on the second side of the substrate (e.g., substrate  12 ,  12 A) and between two or more of the plurality of interconnect members (e.g., solder balls  30 B,  32 B). 
       FIG.  10    is a schematic block diagram of a module  90  that includes a filter  92  with an acoustic wave device in accordance with any suitable principles and advantage disclosed herein. The module  90  includes the filter  92  that includes an acoustic wave device, a switch  94 , a power amplifier  95 , and a radio frequency (RF) coupler  96 . The power amplifier  95  can amplify a radio frequency signal. The switch  94  can selectively electrically couple an output of the power amplifier  95  to the filter  92 . The filter  92  can be a band pass filter. The filter  92  can be included in a duplexer or other multiplexer. The RF coupler  96  can be a directional coupler or any other suitable RF coupler. The RF coupler  96  can sample a portion of RF power in a transmit signal path and provide an indication of the RF power. The RF coupler  96  can be coupled to the transmit signal path in any suitable point, such as between an output of the power amplifier  95  and an input to the switch  94 . The module  90  can include a package that encloses the illustrated elements. The filter  92  with the acoustic wave resonator can be disposed on a common packaging substrate  97  with the other illustrated elements of the module  90 . The packaging substrate  97  can be a laminate substrate, for example. 
       FIG.  11    is a schematic block diagram of a module  100  that includes filters  102  that include one or more acoustic wave devices in accordance with any suitable principles and advantage disclosed herein. As illustrated, the module  100  includes a power amplifier  95 , a switch  94 , filters  102 , an antenna switch  104 , a switch  105 , a low noise amplifier  106 , and a control circuit  107 . 
     The power amplifier  95  can receive a radio frequency signal from a transmit port TX. In some instances, a switch can electrically connect a selected one of a plurality of transmit ports to an input of the power amplifier  95 . The power amplifier  95  can operate in an envelope tracking mode and/or an average power tracking mode. The switch  94  can be a multi-throw radio frequency switch configured to electrically connect an output of the power amplifier  95  to one or more selected transmit filters of the filters  102 . The switch  94  can be a band select switch arranged to electrically connect the output of the power amplifier  95  to a transmit filter for a particular frequency band. 
     The filters  102  can be acoustic wave filters. One or more resonators in any of the filters  102  can include a multi-layer IDT electrode in accordance with any suitable principles and advantages disclosed herein. In certain applications, all acoustic resonators of one or more filters of the filters  102  include a multi-layer IDT electrode in accordance with any suitable principles and advantages disclosed herein. The filters  102  can include a plurality of duplexers and/or other multiplexers. Alternatively or additionally, the filters  102  can include one or more standalone transmit filters and/or one or more standalone receive filters. The filters  102  can include at least four duplexers in some applications. According to some other applications, the filters  102  can include at least eight duplexers. 
     As illustrated, the filters  102  are electrically connected to the antenna switch  104 . The antenna switch  104  can be a multi-throw radio frequency switch arranged to electrically connect one or more filters of the filters  102  to an antenna port ANT of the module  100 . The antenna switch  104  can include at least eight throws in some applications. In certain applications, the antenna switch  104  can include at least ten throws. 
     A switch  105  can electrically connect a selected receive filter of the filters to a low noise amplifier  106 . The low noise amplifier  106  is arranged to amplify the received radio frequency signal and provide an output to a receive port RX. In some instances, another switch can be electrically coupled between the low noise amplifier  106  and the receive port RX. 
     The illustrated module  100  also includes a control circuit  107 . The control circuit  107  can perform any suitable control functions for the module  100 . 
       FIG.  12 A  is a schematic block diagram of a wireless communication device  110  that includes a filter  113  with an acoustic wave device. The wireless communication device  110  can be any suitable wireless communication device. For instance, a wireless communication device  110  can be a mobile phone, such as a smart phone. As illustrated, the wireless communication device  110  includes an antenna  111 , an RF front end  112 , an RF transceiver  114 , a processor  115 , a memory  116 , and a user interface  117 . The antenna  111  can transmit RF signals provided by the RF front end  112 . The antenna  111  can provide received RF signals to the RF front end  112  for processing. 
     The RF front end  112  can include one or more power amplifiers, one or more low noise amplifiers, one or more RF switches, one or more receive filters, one or more transmit filters, one or more duplex filters, one or more filters of a multiplexer, one or more filters of a diplexer or other frequency multiplexing circuit, or any suitable combination thereof. The RF front end  112  can transmit and receive RF signals associated with any suitable communication standard. Any of the acoustic resonators disclosed herein can be implemented in filter  113  of the RF front end  112 . 
     The RF transceiver  114  can provide RF signals to the RF front end  112  for amplification and/or other processing. The RF transceiver  114  can also process an RF signal provided by a low noise amplifier of the RF front end  112 . The RF transceiver  114  is in communication with the processor  115 . The processor  115  can be a baseband processor. The processor  115  can provide any suitable base band processing functions for the wireless communication device  110 . The memory  116  can be accessed by the processor  115 . The memory  116  can store any suitable data for the wireless communication device  110 . The processor  115  is also in communication with the user interface  117 . The user interface  117  can be any suitable user interface, such as a display. 
       FIG.  12 B  is a schematic block diagram of a wireless communication device  120  that includes a radio frequency front end  112  with a filter  113  and a diversity receive module  122  with a filter  123  according to an embodiment. The wireless communication device  120  is like the wireless communication device  110  of  FIG.  12 A , except that the wireless communication device  120  also includes diversity receive features. As illustrated in  FIG.  12 B , the wireless communication device  120  includes a diversity antenna  121 , a diversity receive module  122  configured to process signals received by the diversity antenna  121  and including filters  123 , and a transceiver  124  in communication with both the radio frequency front end  112  and the diversity receive module  122 . The filter  123  can include one or more acoustic wave resonators having any suitable interdigital transducer (IDT) electrode. The filter  123  can include one or more acoustic wave resonators having any suitable IDT electrode. 
     Any of the embodiments described above can be implemented in association with mobile devices such as cellular handsets. The principles and advantages of the embodiments can be used for any systems or apparatus, such as any uplink wireless communication device, that could benefit from any of the embodiments described herein. The teachings herein are applicable to a variety of systems. Although this disclosure includes some example embodiments, the teachings described herein can be applied to a variety of structures. Any of the principles and advantages discussed herein can be implemented in association with RF circuits configured to process signals in a frequency range from about 30 kilohertz (kHz) to 300 gigahertz (GHz), such as in a frequency range from about 450 MHz to 8.5 GHz. An acoustic wave resonator including any suitable combination of features disclosed herein be included in a filter arranged to filter a radio frequency signal in a fifth generation (5G) New Radio (NR) operating band within Frequency Range 1 (FR1). A filter arranged to filter a radio frequency signal in a 5G NR operating band can include one or more acoustic wave resonators disclosed herein. FR1 can be from 410 MHz to 7.125 GHz, for example, as specified in a current 5G NR specification. One or more acoustic wave resonators in accordance with any suitable principles and advantages disclosed herein can be included in a filter arranged to filter a radio frequency signal in a fourth generation (4G) Long Term Evolution (LTE) operating band. 
     Aspects of this disclosure can be implemented in various electronic devices. Examples of the electronic devices can include, but are not limited to, consumer electronic products, parts of the consumer electronic products such as packaged radio frequency modules, uplink wireless communication devices, wireless communication infrastructure, electronic test equipment, etc. Examples of the electronic devices can include, but are not limited to, a mobile phone such as a smart phone, a wearable computing device such as a smart watch or an ear piece, a telephone, a television, a computer monitor, a computer, a modem, a hand-held computer, a laptop computer, a tablet computer, a microwave, a refrigerator, a vehicular electronics system such as an automotive electronics system, a stereo system, a digital music player, a radio, a camera such as a digital camera, a portable memory chip, a washer, a dryer, a washer/dryer, a copier, a facsimile machine, a scanner, a multi-functional peripheral device, a wrist watch, a clock, etc. Further, the electronic devices can include unfinished products. 
     Unless the context clearly requires otherwise, throughout the description and the claims, the words “comprise,” “comprising,” “include,” “including” and the like are to be construed in an inclusive sense, as opposed to an exclusive or exhaustive sense; that is to say, in the sense of “including, but not limited to.” The word “coupled”, as generally used herein, refers to two or more elements that may be either directly connected, or connected by way of one or more intermediate elements. Likewise, the word “connected”, as generally used herein, refers to two or more elements that may be either directly connected, or connected by way of one or more intermediate elements. Additionally, the words “herein,” “above,” “below,” and words of similar import, when used in this application, shall refer to this application as a whole and not to any particular portions of this application. Where the context permits, words in the above Detailed Description using the singular or plural number may also include the plural or singular number respectively. The word “or” in reference to a list of two or more items, that word covers all of the following interpretations of the word: any of the items in the list, all of the items in the list, and any combination of the items in the list. 
     Moreover, conditional language used herein, such as, among others, “can,” “could,” “might,” “may,” “e.g.,” “for example,” “such as” and the like, unless specifically stated otherwise, or otherwise understood within the context as used, is generally intended to convey that certain embodiments include, while other embodiments do not include, certain features, elements and/or states. Thus, such conditional language is not generally intended to imply that features, elements and/or states are in any way required for one or more embodiments. 
     While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the disclosure. Indeed, the novel apparatus, methods, and systems described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein may be made without departing from the spirit of the disclosure. Any suitable combination of the elements and acts of the various embodiments described above can be combined to provide further embodiments. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the disclosure.