Patent Publication Number: US-2023139378-A1

Title: Semiconductor package including stacked semiconductor chips

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2021-0149671 filed on Nov. 3, 2021, which is incorporated herein by reference in its entirety. 
     BACKGROUND 
     1. Technical Field 
     This patent document relates to a semiconductor technology, and more particularly, to a semiconductor package in which a plurality of semiconductor chips are stacked in a vertical direction. 
     2. Related Art 
     Electronic products require multifunctional and high-volume data processing while their sizes are getting smaller. Accordingly, a semiconductor package used for such an electronic product is required to include a plurality of semiconductor chips and to be made to a specified size or smaller. 
     Recently, a system in package (SIP) in which a memory and a memory controller are integrated together in one package has been proposed. 
     SUMMARY 
     In an embodiment, a semiconductor package may include: a substrate having a first side and a second side, the first and second sides being on opposite sides of the substrate in a first direction; a first semiconductor chip disposed over the substrate; a first one-side third semiconductor chip stack disposed over the substrate and spaced apart from the first semiconductor chip, the first one-side third semiconductor chip stack being closer to the first side than the first semiconductor chip; a second semiconductor chip stack disposed over the first semiconductor chip and the first one-side third semiconductor chip stack, the second semiconductor chip stack including one or more second semiconductor chips; and a second one-side third semiconductor chip stack disposed over the second semiconductor chip stack, wherein each of the first one-side third semiconductor chip stack and the second one-side third semiconductor chip stack includes a plurality of third semiconductor chips that are offset-stacked, offset towards the first side as the third semiconductor chips are farther from the substrate, so that chip pads that are disposed on other-side edge regions of the plurality of the third semiconductor chips are exposed, and wherein each of the first one-side third semiconductor chip stack and the second one-side third semiconductor chip stack is electrically connected to the substrate through a bonding wire extending to the substrate while connecting the chip pads of the plurality of third semiconductor chips to each other. 
     In another embodiment, a semiconductor package may include: a substrate having a first side and a second side, the first and second sides being on opposite sides of the substrate in a first direction; a first semiconductor chip disposed over the substrate; a first one-side third semiconductor chip stack disposed over the substrate and spaced apart from the first semiconductor chip, the first one-side third semiconductor chip stack being closer to the first side than the first semiconductor chip; a second semiconductor chip stack disposed over the first one-side third semiconductor chip stack, the second semiconductor chip stack including one or more second semiconductor chips; and a second one-side third semiconductor chip stack disposed over the first semiconductor chip, wherein each of the first one-side third semiconductor chip stack and the second one-side third semiconductor chip stack includes a plurality of third semiconductor chips that are offset-stacked, offset towards the first side as the third semiconductor chips are farther from the substrate, so that chip pads that are disposed on other-side edge regions of the plurality of the third semiconductor chips are exposed, and wherein each of the first one-side third semiconductor chip stack and the second one-side third semiconductor chip stack is electrically connected to the substrate through a bonding ire that extends to the substrate while connecting the chip pads of the plurality of third semiconductor chips to each other. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG.  1    is a view schematically illustrating an example of a data processing system including a memory system according to an embodiment of the present disclosure. 
         FIG.  2 A  is a cross-sectional view illustrating a semiconductor package according to an embodiment of the present disclosure. 
         FIG.  2 B  is a plan view of  FIG.  2 A  viewed from above. 
         FIG.  2 C  is a view illustrating an arrangement of external connection electrodes of  FIG.  2 A  in a plan view. 
         FIG.  3 A  is a cross-sectional view illustrating a semiconductor package according to another embodiment of the present disclosure. 
         FIG.  3 B  is a plan view of  FIG.  3 A  viewed from above. 
         FIG.  3 C  is another plan view of  FIG.  3 A  viewed from above. 
         FIG.  4 A  is a cross-sectional view illustrating a semiconductor package according to another embodiment of the present disclosure. 
         FIG.  4 B  is a plan view of  FIG.  4 A  viewed from above. 
         FIG.  5 A  is a cross-sectional view illustrating a semiconductor package according to another embodiment of the present disclosure. 
         FIG.  5 B  is a plan view of  FIG.  5 A  viewed from above. 
         FIG.  6    is a cross-sectional view illustrating a semiconductor package according to another embodiment of the present disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     Hereinafter, various embodiments of the disclosure will be described in detail with reference to the accompanying drawings. 
     The drawings are not necessarily drawn to scale. In some instances, proportions of at least some structures in the drawings may have been exaggerated in order to clearly illustrate certain features of the described embodiments. In presenting a specific example in a drawing or description having two or more layers in a multi-layer structure, the relative positioning relationship of such layers or the sequence of arranging the layers as shown reflects a particular implementation for the described or illustrated example and a different relative positioning relationship or sequence of arranging the layers may be possible. In addition, a described or illustrated example of a multi-layer structure might not reflect all layers present in that particular multilayer structure (e.g., one or more additional layers may be present between two illustrated layers). As a specific example, when a first layer in a described or illustrated multi-layer structure is referred to as being “on” or “over” a second layer or “on” or “over” a substrate, the first layer may be directly formed on the second layer or the substrate but may also represent a structure where one or more other intermediate layers may exist between the first layer and the second layer or the substrate. 
       FIG.  1    is a view schematically illustrating an example of a data processing system including a memory system according to an embodiment of the present disclosure. 
     Referring to  FIG.  1   , a data processing system  100  may include a host  110  and a memory system  120 . 
     The host  110  may include various wired and/or wireless electronic devices, such as a mobile phone, an MP3 player, a laptop computer, a desktop computer, a game console, a TV, and a projector. In addition, the host  110  may include at least one operating system (OS). This operating system may manage and control the functions and operations of the host  110  generally and may be executed in response to a request of a user by using the data processing system  100  or the memory system  120 . 
     The memory system  120  may execute various operations in response to a request from the host  110 . In particular, the memory system  120  may store data that is accessed by the host  110 . That is, the memory system  120  may be used as a main memory device or an auxiliary memory device of the host  110 . 
     The memory system  120  may include one or more memory devices, for example, first and second memory devices  140  and  150 , and a memory controller  130 . In the present embodiment, the operation of the first memory device  140  may be directly controlled by the host  110 , and the operation of the second memory device  150  may be controlled by the memory controller  130 . 
     The first memory device  140  may include volatile memory, such as dynamic random access memory (DRAM) and static random access memory (SRAM). The second memory device  150  may include nonvolatile memory, such as NAND flash, resistive random access memory (RRAM), phase-change random access memory (PRAM), magneto-resistive random access memory (MRAM), and ferroelectric random access memory (FRAM). In particular, in the present embodiment, the first memory device  140  may include DRAM and the second memory device  150  may include NAND flash. The non-volatile memory may be a memory having a relatively slow speed and a relatively large capacity and may perform a function of storing data or conserving the stored data for a long period of time. The volatile memory may be a memory having a relatively high speed and a relatively small capacity and may perform a function of temporarily storing data. 
     The memory controller  130  may control the second memory device  150  in response to a request from the host  110 . As an example, the memory controller  130  may provide data that is read from the second memory device  150  to the host  110  or may store data that is provided from the host  110  in the second memory device  150 . The memory controller  130  may include a central processing unit (CPU), a controller, an application specific integrated circuit (ASIC), an application processor (AP), or the like. 
     In order for the memory controller  130  to perform an operation, such as receiving a command from the host  110  or transferring data to the host  110 , a signal may be transmitted between the memory controller  130  and the host  110 . In addition, in order for the memory controller  130  to access the second memory device  150  to perform read/write/erase operations under the control of the processor, a signal may be transmitted between the memory controller  130  and the second memory device  150 . In addition, in order for the host  110  to access the first memory device  140  to perform the operations, a signal may be transmitted between the host  110  and the first memory device  140 . These signal transmission paths are indicated by an arrow between memory controller  130  and the host  110 , an arrow between the memory controller  130  and the second memory device  150 , and an arrow between the host  110  and the first memory device  140 . 
     Also, in order for the first and second memory devices  140  and  150  to operate, power may be supplied to them. This power may include various levels of power voltage or ground voltage that required for each of the first and second memory devices  140  and  150 . Accordingly, power may be supplied to each of the first memory device  140  and the second memory device  150  from an external device (not shown) that supplies power. These power supply paths are indicated by an arrow between the first memory device  140  and the external device and an arrow between the second memory device  150  and the external device. 
     In the data processing system  100  described above, the first memory device  140  may be implemented as one or more first memory chips, the second memory device  150  may be implemented as one or more second memory chips, different from the first memory chips, and the memory controller  130  may be implemented as one or more controller chips. Furthermore, the memory system  120  including the first memory device  140 , the second memory device  150 , and the memory controller  130  may be implemented as a single package. This will be described in more detail with reference to the following drawings. 
       FIG.  2 A  is a cross-sectional view illustrating a semiconductor package according to an embodiment of the present disclosure, and  FIG.  2 B  is a plan view of  FIG.  2 A  viewed from above.  FIG.  2 A  may correspond to a cross-sectional view of  FIG.  2 B  in a first direction.  FIG.  2 C  is a view illustrating an arrangement of external connection electrodes of  FIG.  2 A  in a plan view. For convenience of description, in  FIG.  2 B , not only a substrate  200  and a third semiconductor chip stack  230 , but also a second semiconductor chip stack  220 , that is positioned below the third semiconductor chip stack  230  and partially covered by the third semiconductor chip stack  230 , is shown. In addition,  FIG.  2 B  also shows a power connection electrode  240 P, among the external connection electrodes  240  of  FIG.  2 C , serving to supply power to the third semiconductor chip stack  230 . For reference, because the external connection electrodes  240  are schematically illustrated in  FIG.  2 A  and the exact arrangement of the external connection electrodes  240  is not shown in  FIG.  2 A , the arrangement of the external connection electrodes  240  of  FIG.  2 A  might not match that of  FIGS.  2 B and  2 C . The arrangement of the external connection electrodes  240  in a plan view will be described with reference to  FIGS.  2 B and  2 C . 
     First, referring to  FIGS.  2 A and  2 B , the semiconductor package of the present embodiment may include a substrate  200 , a first semiconductor chip  210 , a second semiconductor chip stack  220 , a third semiconductor chip stack  230 , and an external connection electrode  240 . The first semiconductor chip  210 , the second semiconductor chip stack  220 , and the third semiconductor chip stack  230  may be disposed over one surface, for example, an upper surface of the substrate  200  and may be stacked in a vertical direction. The external connection electrode  240  may be disposed over the other surface, for example, a lower surface of the substrate  200 . 
     The substrate  200  may include a circuit and/or wiring structure for electrically connecting the first semiconductor chip  210 , the second semiconductor chip stack  220 , and the third semiconductor chip stack  230  to the external connection electrode  240 . For example, the substrate  200  may include a printed circuit board (PCB), an interposer, a redistribution layer, or the like. Various upper substrate pads for connection with the first semiconductor chip  210 , the second semiconductor chip stack  220 , and the third semiconductor chip stack  230  may be disposed on the upper surface of the substrate  200 , and various lower substrate pads for connection with the external connection electrode  240  may be disposed on the lower surface of the substrate  200 . These upper substrate pads and lower substrate pads may be parts of the circuit and/or wiring structure of the substrate  200  or may be electrically connected to the circuit and/or wiring structure of the substrate  200 . In the cross-sectional view of  FIG.  2 A , for convenience of description, only upper substrate pads  202 A and  202 B for supplying power by connecting with the third semiconductor chip stack  230  are illustrated. As will be described later, the third semiconductor chip stack  230  may include a first one-side third semiconductor chip stack  230 A and a second one-side third semiconductor chip stack  230 B that are disposed on a first side and a second side of the substrate  200 , respectively, in the first direction. The upper substrate pads  202 A and  202 B may include a first one-side upper substrate pad  202 A for supplying power to the first one-side third semiconductor chip stack  230 A and a second one-side upper substrate pad  202 B for supplying power to the second one-side third semiconductor chip stack  230 B. In addition, in the cross-sectional view of  FIG.  2 A , for convenience of description, only a first one-side wiring structure  204 A and a second one-side wiring structure  204 B, respectively connected to the first one-side upper substrate pad  202 A and the second one-side upper substrate pad  202 B, are illustrated in the substrate  200 . Each of the first one-side and the second one-side wiring structures  204 A and  204 B may be formed based on a combination of various conductive patterns that extend in the vertical and/or horizontal directions so as to be connected from each of the first one-side and the second one-side upper substrate pads  202 A and  2023  to the corresponding power connection electrode  240 P. The conductive pattern that extends in the vertical direction may be, for example, a conductive via, and the conductive pattern that extends in the horizontal direction may be, for example, a conductive trace or a conductive plate. 
     The first semiconductor chip  210  may be disposed over the upper surface of the substrate  200  and may be connected to the substrate  200  based on a flip chip bonding method in which a connection electrode  212  that is formed over the lower surface of the first semiconductor chip  210  directly contacts the upper surface of the substrate  200 . The connection electrode  212  may have various shapes, such as a column shape, a ball shape, or a combination thereof, and may include various conductive materials, such as a solder material, a metal material, or a combination thereof. However, the present disclosure is not limited thereto, and the first semiconductor chip  210  may be electrically connected to the substrate  200  through various interconnectors, such as bonding wires. 
     The first semiconductor chip  210  may correspond to a controller chip for controlling the second semiconductor chip stack  220  and/or the third semiconductor chip stack  230 . As an example, when the second semiconductor chip stack  220  and the third semiconductor chip stack  230  include memory chips, the first semiconductor chip  210  may correspond to the memory controller  130  of  FIG.  1   , described above. 
     The second semiconductor chip stack  220  may be disposed over the first semiconductor chip  210 . The second semiconductor chip stack  220  may include one or more second semiconductor chips  220 - 1  and  220 - 2 , stacked in the vertical direction. In the present embodiment, a case in which two second semiconductor chips  220 - 1  and  220 - 2  are stacked is illustrated, but the present disclosure is not limited thereto, and the number of second semiconductor chips stacked in the vertical direction may be variously modified on the assumption that one or more second semiconductor chips are included in the second semiconductor chip stack  220 . That is, the second semiconductor chip stack  220  may include only a single second semiconductor chip. 
     The second semiconductor chips  220 - 1  and  220 - 2  may be the same chips, in particular, the same memory chips. As an example, each of the second semiconductor chips  220 - 1  and  220 - 2  may be a volatile memory chip, such as DRAM. That is, each of the second semiconductor chips  220 - 1  and  220 - 2  may correspond to the first memory device  140  of  FIG.  1   , described above. When the second semiconductor chips  2204  and  220 - 2  are the same chips, they may have the same size in the horizontal direction and the same thickness in the vertical direction. 
     In the present embodiment, the second semiconductor chips  220 - 1  and  220 - 2  may be stacked in a state in which an active surface on which a chip pad  222  is disposed faces upward and an inactive surface faces downward, that is, in a face-up state. Also, the second semiconductor chips  220 - 1  and  220 - 2  may be arranged so that side surfaces thereof are aligned with each other. The chip pad  222  may be disposed on a first one-side edge region, for example, on a left edge region, of each of the second semiconductor chips  220 - 1  and  220 - 2 , in the first direction, and may be electrically connected to the substrate  200  through a bonding wire  224 . However, the present disclosure is not limited thereto, and the stacked form of the second semiconductor chips  220 - 1  and  220 - 2 , the arrangement of the chip pads  222 , an interconnect that connects the substrate  200  to the second semiconductor chips  220 - 1  and  220 - 2 , or the like may be variously modified. 
     Each of the second semiconductor chips  220 - 1  and  220 - 2  may be attached to the upper surface of the second semiconductor chip  220 - 1  or the first semiconductor chip  210  that is positioned directly thereunder through an adhesive layer  226  that is formed over the inactive surface thereof. The adhesive layer  226  may include an insulating adhesive material, such as a die attach film (DAF). The adhesive layer  226  that is under the upper second semiconductor chip  220 - 2  may be thick enough to cover the peak of the bonding wire  224  that is connected to the chip pad  222  of the lower second semiconductor chip  220 - 1 . For example, the adhesive layer  226  that is under the upper second semiconductor chip  220 - 2  may have a greater thickness than the adhesive layer  226  that is under the lower second semiconductor chip  220 - 1 . 
     One or more second semiconductor chip stacks  220  may be arranged to be spaced apart from each other in the horizontal direction. As an example, as shown in the plan view of  FIG.  2 B  the two second semiconductor chip stacks  220  may be arranged in a second direction that is substantially perpendicular to the first direction. The first of the two second semiconductor chip stacks  220  that is disposed on a first side in the second direction, for example, on a lower side in the plan view of  FIG.  2 B , may be referred to as a first one-side second semiconductor chip stack  220 A, and the second of the two second semiconductor chip stacks  220  that is disposed on a second side in the second direction, for example, on an upper side in the plan view of  FIG.  2 B , may be referred to as a second one-side second semiconductor chip stack  220 B. However, the present disclosure is not limited thereto, and the number and arrangement of the second semiconductor chip stack  220  may be variously modified. 
     The first one-side second semiconductor chip stack  220 A and the second one-side second semiconductor chip stack  220 B may be connected to different channels. Here, the channel may mean an independent path for transmitting a signal, such as a command or data to a corresponding semiconductor chip or semiconductor chip stack. In addition, the plurality of second semiconductor chips  220 - 1  and  220 - 2  that are included in the first one-side second semiconductor chip stack  220 A may be connected to different channels or may be connected to the same channel. Similarly, the plurality of second semiconductor chips  220 - 1  and  220 - 2  that are included in the second one-side second semiconductor chip stack  220 B may be connected to different channels or may be connected to the same channel. 
     The second semiconductor chip stack  220  may have a width that corresponds to W 2  in the first direction and a width that corresponds to W 2 ′ in the second direction. As in the present embodiment, when the second semiconductor chips  220 - 1  and  220 - 2  have side surfaces that are aligned with each other, each of the second semiconductor chips  220 - 1  and  220 - 2  may have a width that corresponds to W 2  in the first direction and a width that corresponds to W 2 ′ in the second direction. If the second semiconductor chips  220 - 1  and  220 - 2  do not have side surfaces that are aligned with each other, each of the second semiconductor chips  220 - 1  and  220 - 2  may have a width that is less than W 2  in the first direction and/or a width that is less than W 2 ′ in the second direction. In any case, the area that is occupied by the second semiconductor chip stack  220  in the horizontal direction may be greater than the area of the first semiconductor chip  210 . As an example, as shown in the cross-sectional view of  FIG.  2 A , in the first direction, the width W 1  of the first semiconductor chip  210  may be less than the width W 2  of the second semiconductor chip stack  220 . For this reason, a leaning phenomenon in which the second semiconductor chip stack  220  is inclined over the first semiconductor chip  210  may occur. To prevent this phenomenon, a dummy semiconductor chip  215  may be further disposed in a space between the substrate  200  and the second semiconductor chip stack  220  and may be adjacent to the first semiconductor chip  210 . The dummy semiconductor chip  215  might not electrically perform any function and might not be electrically connected to other components. The dummy semiconductor chip  215  may simply support the second semiconductor chip stack  220  that is under the second semiconductor chip stack  220 . Although this figure illustrates a case in which two dummy semiconductor chips  215  are disposed on both sides of the first semiconductor chip  210  in the first direction, the present disclosure is not limited thereto, and the number and position of dummy semiconductor chips  215  may be variously modified. The dummy semiconductor chip  215  may be attached to the upper surface of the substrate  200  by an adhesive layer  217  that is formed over the lower surface thereof. The total thickness of the dummy semiconductor chip  215  and the adhesive layer  217  may be substantially the same as the total thickness of the first semiconductor chip  210  and the connection electrode  212 . Accordingly, in the vertical direction, the upper surface of the dummy semiconductor chip  215  and the upper surface of the first semiconductor chip  210  may be positioned at substantially the same level. The adhesive layer  226  that is under the lower second semiconductor chip  220 - 1  may be attached to the upper surface of the dummy semiconductor chip  215  and the upper surface of the first semiconductor chip  210  that are positioned at the same level. 
     The third semiconductor chip stack  230  may be disposed over the second semiconductor chip stack  220 . The third semiconductor chip stack  230  may include a plurality of third semiconductor chips  230 - 1  to  230 - 4  that are stacked in the vertical direction. In the present embodiment, a case in which four third semiconductor chips  2304  to  230 - 4  are stacked is illustrated, but the present disclosure is not limited thereto, and the number of third semiconductor chips stacked in the vertical direction may be variously modified. 
     The third semiconductor chips  230 - 1  to  230 - 4  may be the same chips, in particular, the same memory chips. As an example, each of the third semiconductor chips  230 - 1  to  230 - 4  may be a nonvolatile memory chip, such as NAND flash. That is, each of the third semiconductor chips  230 - 1  to  230 - 4  may correspond to the second memory device  150  of  FIG.  1   , described above. When the third semiconductor chips  230 - 1  to  230 - 4  are the same chips, they may have the same size in the horizontal direction and the same thickness in the vertical direction. However, the present disclosure is not limited thereto, and the thicknesses of the third semiconductor chips  230 - 1  to  230 - 4  may be different from each other in the vertical direction. For example, the thickness of the lowermost third semiconductor chip  230 - 1  may be greater than the thickness of each of the remaining third semiconductor chips  230 - 2  to  230 - 4 . 
     Here, at least two third semiconductor chip stacks  230  may be arranged to be spaced apart from each other in a horizontal direction. As an example, the two third semiconductor chip stacks  230  may be arranged in the first direction. One of the two third semiconductor chip stacks  230  that is disposed on a first side, for example, on a left side in the first direction, may be referred to as a first one-side third semiconductor chip stack  230 A, and the other of the two third semiconductor chip stacks  230  that is disposed on a second side, for example, on a right side in the first direction, may be referred to as a second one-side third semiconductor chip stack  230 B. The first one-side third semiconductor chip stack  230 A and the second one-side third semiconductor chip stack  230 B may be connected to different channels. 
     In each of the first and second third semiconductor chip stacks  230 A and  230 B, the third semiconductor chips  230 - 1  to  230 - 4  may be stacked in a state in which an active surface on which a chip pad  232  is disposed faces upward and an inactive surface faces downward, that is, in a face-up state. 
     Here, the chip pad  232  of the first one-side third semiconductor chip stack  230 A may be disposed on a first one-side edge region, for example, on a left edge region of each of the third semiconductor chips  230 - 1  to  230 - 4  in the first direction. Although not shown, a plurality of chip pads  232  may be arranged along the second direction in the first one-side edge region. The third semiconductor chips  230 - 1  to  230 - 4  of the first one-side third semiconductor chip stack  230 A may be stacked so that all of the chip pads  232  are exposed. For example, the third semiconductor chips  230 - 1  to  230 - 4  of the first one-side third semiconductor chip stack  230 A may be stacked to have a predetermined offset from a first side, for example, from a left side, on which the chip pad  232  is disposed toward a second side, for example, toward a right side, as the third semiconductor chips, among the first one-side third semiconductor chip stack  230 A, are farther from the substrate  200 . The first one-side third semiconductor chip stack  230 A may be electrically connected to the substrate  200  through a bonding wire  234  that connects the exposed chip pads  232  of the third semiconductor chips  230 - 1  to  230 - 4  with each other and connects the chip pad  232  of the lowermost third semiconductor chip  230 - 1  to the first one-side upper substrate pad  202 A. 
     On the other hand, the chip pad  232  of the second one-side third semiconductor chip stack  230 B may be disposed on a second one-side edge region, for example, on a right edge region of each of the third semiconductor chips  230 - 1  to  230 - 4  in the first direction. Although not shown, a plurality of chip pads  232  may be arranged along the second direction in the second one-side edge region. The third semiconductor chips  230 - 1  to  230 - 4  of the second one-side third semiconductor chip stack  230 B may be stacked so that all of the chip pads  232  are exposed. For example, the third semiconductor chips  230 - 1  to  230 - 4  of the second one-side third semiconductor chip stack  230 B may be stacked to have a predetermined offset from the second side, for example, from a right side, on which the chip pad  232  is disposed toward a first side, for example, toward a left side, as the third semiconductor chips, among the first one-side third semiconductor chip stack  230 A, are farther from the substrate  200 . The second one-side third semiconductor chip stack  230 B may be substantially mirror the first one-side third semiconductor chip stack  230 A along a vertical axis between the two third semiconductor chip stacks  230 . The second one-side third semiconductor chip stack  230 B may be electrically connected to the substrate  200  through the bonding wire  234  that connects the exposed chip pads  232  of the third semiconductor chips  230 - 1  to  230 - 4  with each other and connects the chip pad  232  of the lowermost third semiconductor chip  230 - 1  to the second one-side upper substrate pad  202 B. 
     Each of the third semiconductor chips  230 - 1  to  230 - 4  may be attached to the upper surface of the second semiconductor chip stack  220  or one of the third semiconductor chips  230 - 1  to  230 - 3 , positioned directly thereunder through an adhesive layer  236 , formed over the inactive surface thereof. The adhesive layer  236  may include an insulating adhesive material, such as DAF. The adhesive layer  236  that is under the lowermost third semiconductor chip  230 - 1  may be thick enough to cover the peak of the bonding wire  224  that is connected to the chip pad  222  of the upper second semiconductor chip  220 - 2 . For example, the adhesive layer  236  that is under the lowermost third semiconductor chip  230 - 1  may have a greater thickness than the adhesive layer  236  that is under each of the remaining third semiconductor chips  230 - 2  to  230 - 4 . 
     The third semiconductor chip stack  230  may have a width that corresponds to W 4  in the first direction and a width that corresponds to W 3 ′ in the second direction. In the present embodiment, the third semiconductor chips  230 - 1  to  230 - 4  may be offset-stacked in the first direction to have side surfaces that are not aligned with each other, while, in the second direction, having side surfaces aligned with each other. In this case, each of the third semiconductor chips  230 - 1  to  230 - 4  may have a width that corresponds to W 3  that is less than W 4  in the first direction and a width that corresponds to W 3 ′ in the second direction. If the third semiconductor chips  230 - 1  to  230 - 4  have side surfaces that are not aligned with each other even in the second direction, each of the third semiconductor chips  2304  to  230 - 4  may have a width that is less than W 3 ′ in the second direction. In any case, the width W 4  of the third semiconductor chip stack  230  may be less than the width W 2  of the second semiconductor chip stack  220  in the first direction. Furthermore, the width W 3 ′ of the third semiconductor chip stack  230  may be greater than the width W 2 ′ of the second semiconductor chip stack  220  in the second direction. As an example, as shown in the cross-sectional view of  FIG.  2 A  and the plan view of  FIG.  2 B , twice the width W 4  of the third semiconductor chip stack  230  may be equal to or less than the width W 2  of the second semiconductor chip stack  220  in the first direction, and the width W 3 ′ of the third semiconductor chip stack  230  may be equal to or greater than twice the width W 2 ′ of the second semiconductor chip stack  220  in the second direction. 
     A plurality of external connection electrodes  240  may be disposed over the lower surface of the substrate  200 . The external connection electrode  240  may have various shapes, such as a column shape, a ball shape, or a combination thereof, and may include various conductive materials, such as a solder material, a metal material, or a combination thereof. 
     According to the semiconductor package described above, it may be possible to reduce the area and thickness of the package as much as possible while integrating different types of memories and controllers into one package. 
     Meanwhile, in a plan view, the arrangement of the external connection electrodes  240  in the semiconductor package is exemplarily shown in  FIG.  2 C . 
     Referring to  FIG.  2 C , the external connection electrodes  240  may be arranged in the first direction and the second direction. Each of the external connection electrodes  240  may function as a terminal for exchanging a signal with an external device or supplying power from the external device. In particular, some of the external connection electrodes  240 , which supply power to the third semiconductor chips  230 - 1  to  230 - 4 , may be hatched with diagonal lines and are referred to as power connection electrodes  240 P. 
     In this case, the arrangement of the external connection electrodes  240  or the function of each external connection electrode  240  may be in a fixed state according to a predetermined ball map. According to this ball map, the power connection electrodes  240 P for supplying power to the NAND flash that can be used as the third semiconductor chips  230 - 1  to  230 - 4  may be disposed relatively biased to the second side, for example, to the right side, in the first direction. In other words, the power connection electrodes  240 P may be disposed closer to the second side, for example, the right side, than the first side, for example, the left side, of the substrate  200  in the first direction. 
     Referring to  FIGS.  2 A and  2 B  again, because the power connection electrodes  240 P are relatively disposed on the second side, for example, on the right side, in the first direction, the length of the first one-side wiring structure  204 A may be greater than the length of the second one-side wiring structure  204 B. The length of the first one-side wiring structure  204 A may be a distance from the first one-side upper substrate pad  202 A that is connected to the first one-side third semiconductor chip stack  230 A through the bonding wire  234  to a first corresponding power connection electrode, among the power connection electrodes  240 P, and the length of the second one-side wiring structure  204 B may be a distance from the second one-side upper substrate pad  202 B that is connected to the second one-side third semiconductor chip stack  230 B through the bonding wire  234  to a second corresponding power connection electrode, among the power connection electrodes  240 P. 
     As a result, because it is relatively difficult to supply power to the first one-side third semiconductor chip stack  230 A that is located relatively far from the power connection electrode  240 P, power integrity may deteriorate. 
     In addition, because the one-side wiring structure  204 A having a relatively long length in the substrate  200  must avoid other wiring structures, it may be difficult to design a circuit/wiring structure in the substrate  200 . 
     Hereinafter, embodiments that can further improve the performance of the semiconductor memory of  FIGS.  2 A and  2 B  and facilitate the design of the substrate  200  will be proposed. 
       FIG.  3 A  is a cross-sectional view illustrating a semiconductor package according to another embodiment of the present disclosure, and  FIG.  3 B  is a plan view of  FIG.  3 A  viewed from above. For convenience of description,  FIG.  3 B  shows not only a substrate  300  and a second one-side third semiconductor chip stack  330 B, but also a second semiconductor chip stack  320  and a first one-side third semiconductor chip stack  330 A of which at least a portion is covered. Differences from the aforementioned embodiment of  FIGS.  2 A and  2 B  will be mainly described. 
     Referring to  FIGS.  3 A and  3 B , the semiconductor package of the present embodiment may include a substrate  300 , a first semiconductor chip  310 , a second semiconductor chip stack  320 , a third semiconductor chip stack  300  including a first one-side third semiconductor chip stack  330 A and a second one-side third semiconductor chip stack  330 B, and external connection electrodes  340  including power connection electrodes  340 P. 
     The substrate  300  may include a first one-side upper substrate pad  302 A for supplying power to the first one-side third semiconductor chip stack  330 A and a second one-side upper substrate pad  302 B for supplying power to the second one-side third semiconductor chip stack  330 B. Also, the substrate  300  may include a first one-side wiring structure  304 A that is connected from the first one-side upper substrate pad  302 A to a first corresponding power connection electrode, among the power connection electrodes  340 P, and a second one-side wiring structure  304 B connected from the second one-side upper substrate pad  302 B to a second corresponding power connection electrode, among the power connection electrodes  340 P. 
     The first semiconductor chip  310  may be disposed over the upper surface of the substrate  300  and may be connected to the substrate  300  by a connection electrode  312  that is formed on the lower surface of the first semiconductor chip  310 . The first semiconductor chip  310  may be disposed to be relatively biased toward the second side, for example, to the right side in the first direction. In other words, the first semiconductor chip  310  may be disposed closer to the second side, for example, the right side, rather than the first side, for example, the left side, of the substrate  300  in the first direction. This may be to provide a space in which the first one-side third semiconductor chip stack  330 A is disposed on the first side, for example, on the left side of the first semiconductor chip  310 . The structure and location of the first one-side third semiconductor chip stack  330 A will be described later. 
     The second semiconductor chip stack  320  may be disposed over the first semiconductor chip  310  and the first one-side third semiconductor chip stack  330 A. The second semiconductor chip stack  320  may include one or more second semiconductor chips  320 - 1  and  320 - 2 , stacked in the vertical direction. Each of the second semiconductor chips  320 - 1  and  320 - 2  may be attached to the upper surface of the second semiconductor chip  320 - 1  or the first semiconductor chip  310 , positioned directly thereunder through an adhesive layer  326 , formed over the inactive surface thereof. The second semiconductor chips  320 - 1  and  320 - 2  may be electrically connected to the substrate  300  through a bonding wire  324  that is connected to the chip pad  322 . The second semiconductor chip stack  320  may include a first one-side second semiconductor chip stack  320 A and a second one-side second semiconductor chip stack  320 B, which are arranged to be spaced apart from each other in the second direction. 
     The first one-side third semiconductor chip stack  330 A of the third semiconductor chip stack  330  may be disposed between the substrate  300  and the second semiconductor chip stack  320  in the vertical direction. That is, the first one-side third semiconductor chip stack  330 A may be positioned at the same level as the first semiconductor chip  310  in the vertical direction. The first one-side third semiconductor chip stack  330 A may have a thickness that is substantially equal to the sum of the thicknesses of the first semiconductor chip  310  and the connection electrode  312 , and thus, the upper surface of the first one-side third semiconductor chip stack  330 A and the upper surface of the first semiconductor chip  310  may be positioned at substantially the same level in the vertical direction. The first one-side third semiconductor chip stack  330 A may be disposed to be spaced apart from the first semiconductor chip  310  on a first side, for example, on the left side of the first semiconductor chip  310  in the first direction. 
     On the other hand, the second one-side third semiconductor chip stack  330 B of the third semiconductor chip stack  330  may be disposed over the second semiconductor chip stack  320 . In the first direction, the second one-side third semiconductor chip stack  330 B may be disposed to be closer to the second side of the substrate  300  than the first one-side third semiconductor chip stack  330 A. As an example, the second one-side third semiconductor chip stack  330 B may be disposed to overlap with the first semiconductor chip  310 . 
     Each of the first one-side and the second one-side third semiconductor chip stacks  330 A and  330 B may include one or more third semiconductor chips  330 - 1  to  330 - 4 , stacked in the vertical direction. The third semiconductor chips  330 - 1  to  330 - 4  may be stacked in a state in which an active surface on which a chip pad  332  is disposed faces upward and an inactive surface faces downward, that is, in a face-up state. In addition, the chip pad  332  of the first one-side and the second one-side third semiconductor chip stacks  330 A and  330 B may be disposed on a second one-side edge region, for example, a right edge region of each of the third semiconductor chips  330 - 1  to  330 - 4  in the first direction. The third semiconductor chips  330 - 1  to  330 - 4  of the first one-side and the second one-side third semiconductor chip stacks  330 A and  330 B may be stacked so that all of the chip pads  332  are exposed. For example, in each of the first one-side and the second one-side third semiconductor chip stacks  330 A and  330 B, the third semiconductor chips  330 - 1  to  330 - 4  may be stacked to have a predetermined offset from the second side, for example, from the right side on which the chip pad  332  is disposed toward the first side, positioned on the opposite side of the second side, for example, toward the left side in the first direction. That is, the offset stacking direction of the third semiconductor chips  330 - 1  to  330 - 4  in the first one-side third semiconductor chip stack  330 A may be identical to the offset stacking direction of the third semiconductor chips  330 - 1  to  330 - 4  in the second one-side third semiconductor chip stack  330 B. The first one-side third semiconductor chip stack  330 A may be electrically connected to the substrate  300  through a bonding wire  334  that connects the exposed chip pads  332  of the third semiconductor chips  330 - 1  to  330 - 4  with each other and connects the chip pad  332  of the lowermost third semiconductor chip  330 - 1  to the first one-side upper substrate pad  302 A. The second one-side third semiconductor chip stack  330 B may be electrically connected to the substrate  300  through the bonding wire  334  that connects the exposed chip pads  332  of the third semiconductor chips  330 - 1  to  330 - 4  with each other and connects the chip pad  332  of the lowermost third semiconductor chip  330 - 1  to the second one-side upper substrate pad  302 B. Each of the third semiconductor chips  330 - 1  to  330 - 4  may be attached to a component that is positioned directly thereunder through an adhesive layer  336  that is formed over the inactive surface thereof. 
     According to the semiconductor package described above, because the first one-side third semiconductor chip stack  330 A is positioned below the second semiconductor chip stack  320 , and the chip pad  332  of the first one-side third semiconductor chip stack  330 A and the bonding wire  334  that is connected thereto are disposed relatively close to the second side, for example, to the right side, the length of the first one-side wiring structure  304 A may be reduced. The length of the first one-side wiring structure  304 A may be a distance from the first one-side upper substrate pad  302 A connected to the first one-side third semiconductor chip stack  330 A through the bonding wire  334  to a corresponding power connection electrode  340 P. 
     As a result, power supply to the first one-side third semiconductor chip stack  330 A may be facilitated, and the power integrity may be improved. 
     In addition, because the area that is occupied by the first one-side wiring structure  304 A in the substrate  300  is reduced, the degree of freedom in designing the circuit/wiring structure in the substrate  300  may be increased. 
     In addition, because the distance between the first one-side third semiconductor chip stack  330 A and the first semiconductor chip  310  is also reduced, the integrity of signals that are exchanged therebetween through the substrate  300  may be improved. 
     Furthermore, because the first one-side third semiconductor chip stack  330 A supports the second semiconductor chip stack  320  together with the first semiconductor chip  310 , the number of required dummy semiconductor chips may be reduced or the dummy semiconductor chips might not be needed. 
     Meanwhile, the first semiconductor chip  310 , the second semiconductor chip stack  320 , and the third semiconductor chip stack  330  may be arranged in various shapes depending on the area and/or size in a plan view, and as necessary, one or more dummy semiconductor chips for supporting may be further used. This will be exemplarily described with further reference to  FIG.  3 C . 
       FIG.  3 C  is another plan view of  FIG.  3 A  viewed from above. For convenience of description,  FIG.  3 C  shows a planar shape and arrangement of the substrate  300 , the first semiconductor chip  310 , the second semiconductor chip stack  320  including the first one-side second semiconductor chip stack  320 A and the second one-side second semiconductor chip stack  320 B, the third semiconductor chip stack  330  including the first one-side third semiconductor chip stack  330 A and the second one-side third semiconductor chip stack  330 B, and first and second dummy semiconductor chips  350 A and  350 B. 
     Referring to  FIGS.  3 A and  3 C , the first semiconductor chip  310  may have a width that corresponds to W 1  in the first direction and a width that corresponds to W 1 ′ in the second direction. The second semiconductor chip stack  320  may have a width that corresponds to W 2  in the first direction and a width that corresponds to W 2 ′ in the second direction. The third semiconductor chip stack  330  may have a width that corresponds to W 4  in the first direction and a width that corresponds to W 3 ′ in the second direction. 
     The width W 4  of the third semiconductor chip stack  330  may be less than the width W 2  of the second semiconductor chip stack  320  in the first direction, while the width W 3 ′ of the third semiconductor chip stack  330  may be greater than the width W 2 ′ of the second semiconductor chip stack  320  in the second direction. The first semiconductor chip  310  may be a chip having a smaller planar area than the second semiconductor chip stack  320  and the third semiconductor chip stack  330 , and thus, the width W 1  of the first semiconductor chip  310  may be less than the width W 2  of the second semiconductor chip stack  320  in the first direction, and the width W 1 ′ of the first semiconductor chip  310  may be greater than the width W 3 ′ of the third semiconductor chip stack  330  in the second direction. 
     In the present embodiment, in the first direction, the second semiconductor chip stack  320  may overlap with the entire upper surface of the first one-side third semiconductor chip stack  330 A and the entire upper surface of the first semiconductor chip  310 . Accordingly, the second semiconductor chip stack  320  may be sufficiently supported by the first one-side third semiconductor chip stack  330 A and the first semiconductor chip  310  in the first direction. In addition, because the first one-side third semiconductor chip stack  330 A has a relatively large width W 3 ′ in the second direction, the second semiconductor chip stack  320 , in particular, the first one-side and the second one-side second semiconductor chip stacks  320 A and  320 B arranged in the second direction may be supported by the first one-side third semiconductor chip stack  330 A. However, because the first semiconductor chip  310  has a relatively small width W 1 ′ in the second direction, it may be difficult to support the second semiconductor chip stack  320 , in particular, the first one-side and the second one-side second semiconductor chip stacks  320 A and  320 B that are arranged in the second direction. In order to solve this difficulty, the dummy semiconductor chips  350 A and  350 B may be disposed in an empty space between the substrate  300  and the second semiconductor chip stack  320  and may be disposed to be adjacent to the first one-side third semiconductor chip stack  330 A and the first semiconductor chip  310 . In the present embodiment, a case in which the first and second dummy semiconductor chips  350 A and  350 B are disposed on both sides of the first semiconductor chip  310 , respectively, in the second direction is illustrated. However, the present disclosure is not limited thereto, and the planar size, position, and number of the dummy semiconductor chip may be variously modified. 
     Although not shown in the cross-sectional view of FIG.  3 A, the dummy semiconductor chips  350 A and  350 B may be disposed between the substrate  300  and the second semiconductor chip stack  320  and may have a thickness that is substantially the same as the thickness of the first one-side third semiconductor chip stack  330 A or the total thickness of the first semiconductor chip  310  and the connection electrode  312 . When the dummy semiconductor chips  350 A and  350 B are attached to the substrate  300  by an adhesive layer (not shown), the sum of the thickness of each of the dummy semiconductor chips  350 A and  350 B and the thickness of the adhesive layer may be the same as the thickness of the first one-side third semiconductor chip stack  330 A or the total thickness of the first semiconductor chip  310  and the connection electrode  312 . 
       FIG.  4 A  is a cross-sectional view illustrating a semiconductor package according to another embodiment of the present disclosure, and  FIG.  4 B  is a plan view of  FIG.  4 A  viewed from above, in a manner similar to that of  FIG.  3 C . Differences from the above-described embodiment of  FIGS.  3 A to  3 C  will be mainly described. 
     Referring to  FIGS.  4 A and  4 B , the semiconductor package of the present embodiment may include a substrate  400 , a first semiconductor chip  410 , a second semiconductor chip stack  420 , a third semiconductor chip stack  430  including a first one-side third semiconductor chip stack  430 A and a second one-side third semiconductor chip stack  430 B, and external connection electrodes  440  including power connection electrodes  440 P. 
     The substrate  400  may include a first one-side upper substrate pad  402 A for supplying power to the first one-side third semiconductor chip stack  430 A and a second one-side upper substrate pad  402 B for supplying power to the second one-side third semiconductor chip stack  430 B. Also, the substrate  400  may include a first one-side wiring structure  404 A that is connected from the first one-side upper substrate pad  402 A to a first corresponding power connection electrode, among the power connection electrodes  440 P, and a second one-side wiring structure  404 B connected from the second one-side upper substrate pad  402 B to a second corresponding power connection electrode, among the power connection electrodes  440 P. 
     The first semiconductor chip  410  may be disposed over the upper surface of the substrate  400  and may be connected to the substrate  400  by a connection electrode  412  that is formed on the lower surface of the first semiconductor chip  410 . The first semiconductor chip  410  may be disposed to be relatively biased toward the second side, for example, to the right side in the first direction. 
     The second semiconductor chip stack  420  may be disposed over the first semiconductor chip  410  and the first one-side third semiconductor chip stack  430 A. The second semiconductor chip stack  420  may include one or more second semiconductor chips  420 - 1  and  420 - 2  that are stacked in the vertical direction. Each of the second semiconductor chips  420 - 1  and  420 - 2  may be attached to the upper surface of a component that is positioned directly thereunder through an adhesive layer  426  that is formed over the inactive surface thereof. The second semiconductor chips  420 - 1  and  420 - 2  may be electrically connected to the substrate  400  through a bonding wire  424  that is connected to the chip pad  422 . The second semiconductor chip stack  420  may include a first one-side second semiconductor chip stack  420 A and a second one-side second semiconductor chip stack  420 B, which are arranged to be spaced apart from each other in the second direction. 
     The first one-side third semiconductor chip stack  430 A of the third semiconductor chip stack  430  may be disposed between the substrate  400  and the second semiconductor chip stack  420  in the vertical direction. The first one-side third semiconductor chip stack  430 A may be disposed to be spaced apart from the first semiconductor chip  410  on a first side, for example, on the left side of the first semiconductor chip  410  in the first direction. 
     On the other hand, the second one-side third semiconductor chip stack  430 B of the third semiconductor chip stack  430  may be disposed over the second semiconductor chip stack  420 . In the first direction, the second one-side third semiconductor chip stack  430 B may be disposed to be closer to the second side of the substrate  400  than the first one-side third semiconductor chip stack  430 A. As an example, the second one-side third semiconductor chip stack  430 B may be disposed to overlap with the first semiconductor chip  410 . 
     Each of the first one-side and the second one-side third semiconductor chip stacks  430 A and  430 B may include one or more third semiconductor chips  430 - 1  to  430 - 4 , stacked in the vertical direction. The third semiconductor chips  430 - 1  to  430 - 4  may be stacked in a state in which an active surface on which a chip pad  432  is disposed faces upward and an inactive surface faces downward, that is, in a face-up state. In addition, the chip pad  432  of the first one-side and the second one-side third semiconductor chip stacks  430 A and  430 B may be disposed on a second one-side edge region, for example, a right edge region of each of the third semiconductor chips  430 - 1  to  430 - 4  in the first direction. The third semiconductor chips  430 - 1  to  430 - 4  of the first one-side and the second one-side third semiconductor chip stacks  430 A and  430 B may be offset-stacked in a direction from the second side toward the first side so that all of the chip pads  432  are exposed. The first one-side and the second one-side third semiconductor chip stacks  430 A and  430 B may be electrically connected to the first one-side and the second one-side upper substrate pads  402 A and  402 B of the substrate  400 , respectively, through a bonding wire  434 . Each of the third semiconductor chips  430 - 1  to  430 - 4  may be attached to a component that is positioned directly thereunder through an adhesive layer  436  formed over the inactive surface thereof. 
     In the present embodiment, the width W 2  of the second semiconductor chip stack  420  in the first direction may be reduced compared to the above-described embodiment. Accordingly, in the first direction, the second semiconductor chip stack  420  may partially overlap with the upper surface of the first semiconductor chip  410  while overlapping with the entire upper surface of the first one-side third semiconductor chip stack  430 A. 
     In this case, if the second one-side third semiconductor chip stack  430 B exists at the same position as in the above-described embodiment, it may be difficult that the second semiconductor chip stack  420  supports the second one-side third semiconductor chip stack  430 B in the first direction. Accordingly, first to third dummy semiconductor chips  450 A,  450 B, and  450 C for sufficient support of the second one-side third semiconductor chip stack  430 B may be disposed. 
     The second dummy semiconductor chip  450 B, among the first to third dummy semiconductor chips  450 A,  450 B, and  450 C, may be disposed between the first semiconductor chip  410  and the second one-side third semiconductor chip stack  430 B in the vertical direction. That is, the second dummy semiconductor chip  450 B may be positioned at the same level as the second semiconductor chip stack  420  in the vertical direction. When the second dummy semiconductor chip  450 B is attached to the upper surface of the first semiconductor chip  410  by an adhesive layer  456  that is formed on its lower surface, the sum of the thickness of the second dummy semiconductor chip  450 B and the thickness of the adhesive layer  456  may be substantially the same as the thickness of the second semiconductor chip stack  420 . If the adhesive layer  456  is omitted, the thickness of the second dummy semiconductor chip  450 B may be substantially the same as the thickness of the second semiconductor chip stack  420 . 
     The first and third dummy semiconductor chips  450 A and  450 C may be disposed between the substrate  400  and the second one-side third semiconductor chip stack  430 B. As described above, because the width W 1 ′ of the first semiconductor chip  410  in the second direction is relatively small, the support of the second one-side third semiconductor chip stack  430 B in the second direction might not be sufficient with the first semiconductor chip  410  and the second dummy semiconductor chip  450 B. Accordingly, the first and third dummy semiconductor chips  450 A and  450 C may be further disposed in an empty space that is under the second one-side third semiconductor chip stack  430 B. In the present embodiment, a case has been described in which the first and third dummy semiconductor chips  450 A and  450 C are disposed on both sides of the second dummy semiconductor chip  450 B, respectively, in the second direction, but the present disclosure is not limited thereto. The size, position, and number of dummy semiconductor chips having thicknesses that correspond to that of each of the first and third dummy semiconductor chips  450 A and  450 C may be variously modified. 
     Each of the first and third dummy semiconductor chips  450 A and  450 C may have a thickness substantially the same as the sum of the thickness of the first one-side third semiconductor chip stack  430 A and the thickness of the second semiconductor chip stack  420 . When each of the first and third dummy semiconductor chips  450 A and  450 C is attached to the upper surface of the substrate  400  by an adhesive layer (not shown), the sum of the thicknesses of the adhesive layer and the thickness of each of the first and third dummy semiconductor chips  450 A and  450 C may be substantially the same as the sum of the thickness of the first one-side third semiconductor chip stack  430 A and the thickness of the second semiconductor chip stack  420 . 
       FIG.  5 A  is a cross-sectional view illustrating a semiconductor package according to another embodiment of the present disclosure, and  FIG.  5 B  is a plan view of  FIG.  5 A  viewed from above, in a manner similar to those of  FIGS.  3 C and  4 B . Differences from the above-described embodiments of  FIGS.  3 A to  3 C , and  FIGS.  4 A and  4 B  will be mainly described. 
     Referring to  FIGS.  5 A and  5 B , the semiconductor package of the present embodiment may include a substrate  500 , a first semiconductor chip  510 , a second semiconductor chip stack  520 , a third semiconductor chip stack  530  including a first one-side third semiconductor chip stack  530 A and a second one-side third semiconductor chip stack  530 B, and external connection electrodes  540  including power connection electrodes  540 P. 
     The substrate  500  may include a first one-side upper substrate pad  502 A for supplying power to the first one-side third semiconductor chip stack  530 A and a second one-side upper substrate pad  502 B for supplying power to the second one-side third semiconductor chip stack  530 B. Also, the substrate  500  may include a first one-side wiring structure  504 A that is connected from the first one-side upper substrate pad  502 A to a first corresponding power connection electrode, among the power connection electrodes  540 P, and a second one-side wiring structure  504 B connected from the second one-side upper substrate pad  502 B to a second corresponding power connection electrode, among the power connection electrodes  540 P. 
     The first semiconductor chip  510  may be disposed over the upper surface of the substrate  500  and may be connected to the substrate  500  by a connection electrode  512  that is formed on the lower surface of the first semiconductor chip  510 . The first semiconductor chip  510  may be disposed to be relatively biased toward the second side, for example, to the right side in the first direction. 
     The second semiconductor chip stack  520  may be disposed over the first one-side third semiconductor chip stack  530 A. The second semiconductor chip stack  520  may include one or more second semiconductor chips  5204  and  520 - 2 , stacked in the vertical direction. Each of the second semiconductor chips  520 - 1  and  520 - 2  may be attached to a component that is positioned directly thereunder through an adhesive layer  526  that is formed over the inactive surface thereof. The second semiconductor chips  520 - 1  and  520 - 2  may be electrically connected to the substrate  500  through a bonding wire  524  that is connected to the chip pad  522 . The second semiconductor chip stack  520  may include a first one-side second semiconductor chip stack  520 A and a second one-side second semiconductor chip stack  520 B, which are arranged to be spaced apart from each other in the second direction. 
     The first one-side third semiconductor chip stack  530 A of the third semiconductor chip stack  530  may be disposed between the substrate  500  and the second semiconductor chip stack  520  in the vertical direction. The first one-side third semiconductor chip stack  530 A may be disposed to be spaced apart from the first semiconductor chip  510  on a first side, for example, on the left side of the first semiconductor chip  510  in the first direction. 
     The second one-side third semiconductor chip stack  530 B of the third semiconductor chip stack  530  may be disposed over the first semiconductor chip  510 . The second one-side third semiconductor chip stack  530 B may directly contact the first semiconductor chip  510 . That is, unlike the above-described embodiments, the second semiconductor chip stack  520  might not be interposed between the second one-side third semiconductor chip stack  530 B and the first semiconductor chip  510 . 
     Each of the first one-side and the second one-side third semiconductor chip stacks  530 A and  530 B may include one or more third semiconductor chips  530 - 1  to  530 - 4 , stacked in the vertical direction. The third semiconductor chips  530 - 1  to  530 - 4  may be stacked in a state in which an active surface on which a chip pad  532  is disposed faces upward and an inactive surface faces downward, that is, in a face-up state. In addition, the chip pad  532  of the first one-side and the second one-side third semiconductor chip stacks  530 A and  530 B may be disposed on a second one-side edge region, for example, a right edge region of each of the third semiconductor chips  530 - 1  to  530 - 4  in the first direction. The third semiconductor chips  530 - 1  to  530 - 4  of the first one-side and the second one-side third semiconductor chip stacks  530 A and  530 B may be offset-stacked in a direction from the second side toward the first side so that all of the chip pads  532  are exposed. The first one-side and the second one-side third semiconductor chip stacks  530 A and  530 B may be electrically connected to the first one-side and the second one-side upper substrate pads  502 A and  502 B of the substrate  500 , respectively, through a bonding wire  534 . Each of the third semiconductor chips  530 - 1  to  530 - 4  may be attached to a component that is positioned directly thereunder through an adhesive layer  536  that is formed over the inactive surface thereof. 
     In the present embodiment, the width W 2  of the second semiconductor chip stack  520  in the first direction may be further reduced compared to the above-described embodiments. Accordingly, in the first direction, the second semiconductor chip stack  520  might not overlap with the upper surface of the first semiconductor chip  510  and may be spaced apart from the first semiconductor chip  510  while overlapping with the entire upper surface of the first one-side third semiconductor chip stack  530 A. 
     In this case, because the second one-side third semiconductor chip stack  530 B also does not overlap with the second semiconductor chip stack  520 , it may be formed over the first semiconductor chip  510  to directly contact the first semiconductor chip  510 . However, because the width W 3 ′ of the second one-side third semiconductor chip stack  530 B in the second direction is greater than the width W 1 ′ of the first semiconductor chip  510 , first and second dummy semiconductor chips  550 A and  550 B may be disposed for sufficiently supporting the second one-side third semiconductor chip stack  530 B. 
     The first and second dummy semiconductor chips  550 A and  550 B may be disposed between the substrate  500  and the second one-side third semiconductor chip stack  530 B. Although not shown in the cross-sectional view of  FIG.  5 A , when each of the first and second dummy semiconductor chips  550 A and  550 B is attached to the upper surface of the substrate  500  by an adhesive layer (not shown) formed on the lower surface thereof, the sum of the thickness of the adhesive layer and the thickness of each of the first and second dummy semiconductor chips  550 A and  550 B may be substantially the same as the sum of the thickness of the first semiconductor chip  510  and the thickness of the connection electrode  512 . If the adhesive layer is omitted, the thickness of each of the first and second dummy semiconductor chips  550 A and  550 B may be substantially the same as the sum of the thickness of the first semiconductor chip  510  and the thickness of the connection electrode  512 . 
       FIG.  6    is a cross-sectional view illustrating a semiconductor package according to another embodiment of the present disclosure. A plan view of  FIG.  6    is omitted because it is substantially the same as  FIG.  3 C  described above. Differences from the above-described embodiment of  FIGS.  3 A to  3 C  will be mainly described. 
     Referring to  FIG.  6   , the semiconductor package of the present embodiment may include a substrate  600 , a first semiconductor chip  610 , a second semiconductor chip stack  620 , a third semiconductor chip stack  630  including a first one-side third semiconductor chip stack  630 A and a second one-side third semiconductor chip stack  630 B, and external connection electrodes  640  including power connection electrodes  640 P. 
     The substrate  600  may include a first one-side upper substrate pad  602 A for supplying power to the first one-side third semiconductor chip stack  630 A and a second one-side upper substrate pad  602 B for supplying power to the second one-side third semiconductor chip stack  630 B. Also, the substrate  600  may include a first one-side wiring structure  604 A that is connected from the first one-side upper substrate pad  602 A to a first corresponding power connection electrode, among the power connection electrodes  640 P, and a second one-side wiring structure  604 B that is connected from the second one-side upper substrate pad  602 B to a second corresponding power connection electrode, among the power connection electrodes  640 P. 
     The first semiconductor chip  610  may be disposed over the upper surface of the substrate  600  and may be connected to the substrate  600  by a connection electrode  612  that is formed on the lower surface of the first semiconductor chip  610 . The first semiconductor chip  610  may be disposed to be relatively biased toward the second side, for example, to the right side in the first direction. 
     The second semiconductor chip stack  620  may be disposed over the first semiconductor chip  610  and the first one-side third semiconductor chip stack  630 A. The second semiconductor chip stack  620  may include one or more second semiconductor chips  620 - 1  and  620 - 2 , stacked in the vertical direction. Each of the second semiconductor chips  6204  and  620 - 2  may be attached to a component that is positioned directly thereunder through an adhesive layer  626  that is formed over the inactive surface thereof. The second semiconductor chips  620 - 1  and  620 - 2  may be electrically connected to the substrate  600  through a bonding wire  624  that is connected to the chip pad  622 . 
     The first one-side third semiconductor chip stack  630 A of the third semiconductor chip stack  630  may be disposed between the substrate  600  and the second semiconductor chip stack  620  in the vertical direction. The first one-side third semiconductor chip stack  630 A may be disposed to be spaced apart from the first semiconductor chip  610  on a first side, for example, on the left side of the first semiconductor chip  610  in the first direction. In this case, the thickness of the first one-side third semiconductor chip stack  630 A may be less than the total thickness of the first semiconductor chip  610  and the connection electrode  612 . Accordingly, in the vertical direction, the upper surface of the first one-side third semiconductor chip stack  630 A may be located below the upper surface of the first semiconductor chip  610 . In this case, because it is difficult to form the second semiconductor chip stack  620 , a dummy semiconductor chip  650  may be disposed between the first one-side third semiconductor chip stack  630 A and the second semiconductor chip stack  620 . The dummy semiconductor chip  650  may be attached to the upper surface of the first one-side third semiconductor chip stack  630 A by an adhesive layer  656 . 
     The second one-side third semiconductor chip stack  630 B of the third semiconductor chip stack  630  may be disposed over the second semiconductor chip stack  620 . 
     Each of the first one-side and the second one-side third semiconductor chip stacks  630 A and  630 B may include one or more third semiconductor chips  630 - 1  and  630 - 2 , stacked in the vertical direction. In the present embodiment, because each of the first one-side and the second one-side third semiconductor chip stacks  630 A and  630 B includes two third semiconductor chips  630 - 1  and  630 - 2 , the thickness thereof may be less than that of the above-described embodiment. The third semiconductor chips  630 - 1  and  630 - 2  may be stacked in a state in which an active surface on which a chip pad  632  is disposed faces upward and an inactive surface faces downward, that is, in a face-up state. In addition, the chip pad  632  of the first one-side and the second one-side third semiconductor chip stacks  630 A and  630 B may be disposed on a second one-side edge region, for example, a right edge region of each of the third semiconductor chips  630 - 1  and  630 - 2  in the first direction. The third semiconductor chips  630 - 1  and  630 - 2  of the first one-side and the second one-side third semiconductor chip stacks  630 A and  630 B may be offset-stacked in a direction from the second side toward the first side so that all of the chip pads  632  are exposed. The first one-side and the second one-side third semiconductor chip stacks  630 A and  630 B may be electrically connected to the first one-side and the second one-side upper substrate pads  602 A and  602 B of the substrate  600 , respectively, through a bonding wire  634 . Each of the third semiconductor chips  630 - 1  and  630 - 2  may be attached to a component positioned directly thereunder through an adhesive layer  636  that is formed over the inactive surface thereof. 
     According to the above embodiments of the present disclosure, it may be possible to provide a semiconductor package capable of reducing the area and thickness of the semiconductor package as much as possible while integrating different types of memories and controllers into one package and securing excellent operating characteristics. 
     Although various embodiments have been described for illustrative purposes, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the present teachings as defined in the following claims.