Patent Publication Number: US-2023146652-A1

Title: Method of manufacturing semiconductor device

Description:
PRIORITY DATA 
     This patent is a divisional application of U.S. patent application Ser. No. 16/739,913 filed on Jan. 10, 2020, entitled of “SEMICONDUCTOR DEVICE HAVING PASSIVATION LAYER AND METHOD OF MANUFACTURING THE SAME”, which is a divisional application of U.S. patent application Ser. No. 15/674,104 filed on Aug. 10, 2017, entitled of “SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME”, the entire disclosure of which is hereby incorporated by reference. 
    
    
     BACKGROUND 
     In the packaging of integrated circuits, semiconductor dies may be stacked through bonding, and may be bonded to other package components such as interposers and package substrates. The resulting packages are known as Three-Dimensional Integrated Circuits (3DICs). Wafer cracking and stress issues, however, are challenges in the 3DICs. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Aspects of the embodiments of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various structures are not drawn to scale. In fact, the dimensions of the various structures may be arbitrarily increased or reduced for clarity of discussion. 
         FIG.  1    is a flow chart illustrating a method of manufacturing a semiconductor device according to various aspects of one or more embodiments of the present disclosure. 
         FIG.  2 A ,  FIG.  2 B ,  FIG.  2 C ,  FIG.  2 D ,  FIG.  2 E ,  FIG.  2 F  and  FIG.  2 G  are schematic views at one of various operations of manufacturing a semiconductor device according to one or more embodiments of the present disclosure. 
         FIG.  3 A  and  FIG.  3 B  are schematic views of a semiconductor device according to one or more embodiments of the present disclosure. 
         FIG.  4 A  and  FIG.  4 B  are schematic views of a semiconductor device according to one or more embodiments of the present disclosure. 
         FIG.  5 A ,  FIG.  5 B ,  FIG.  5 C  and  FIG.  5 D  are schematic views at one of various operations of manufacturing a semiconductor device according to one or more embodiments of the present disclosure. 
         FIG.  6 A ,  FIG.  6 B  and  FIG.  6 C  are schematic views at one of various operations of manufacturing a semiconductor device according to one or more embodiments of the present disclosure. 
         FIG.  7 A  and  FIG.  7 B  are schematic views of a semiconductor device according to one or more embodiments of the present disclosure. 
         FIG.  8 A  and  FIG.  8 B  are schematic views of a semiconductor device according to one or more embodiments of the present disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of elements and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. 
     Further, spatially relative terms, such as “beneath”, “below”, “lower”, “above”, “upper”, “on” and the like, may be used herein for ease of description to describe one element or feature&#39;s relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. 
     As used herein, the terms such as “first”, “second” and “third” describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms may be only used to distinguish one element, component, region, layer or section from another. The terms such as “first”, “second” and “third” when used herein do not imply a sequence or order unless clearly indicated by the context. 
     As used herein, the terms “approximately,” “substantially,” “substantial” and “about” are used to describe and account for small variations. When used in conjunction with an event or circumstance, the terms can refer to instances in which the event or circumstance occurs precisely as well as instances in which the event or circumstance occurs to a close approximation. For example, when used in conjunction with a numerical value, the terms can refer to a range of variation of less than or equal to ±10% of that numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, two numerical values can be deemed to be “substantially” the same or equal if a difference between the values is less than or equal to ±10% of an average of the values, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, “substantially” parallel can refer to a range of angular variation relative to 0° that is less than or equal to ±10°, such as less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°. For example, “substantially” perpendicular can refer to a range of angular variation relative to 90° that is less than or equal to ±10°, such as less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°. 
     Other features and processes may also be included. For example, testing structures may be included to aid in the verification testing of the 3D packaging or 3DIC devices. The testing structures may include, for example, test pads formed in a redistribution layer or on a substrate that allows the testing of the 3D packaging or 3DIC, the use of probes and/or probe cards, and the like. The verification testing may be performed on intermediate structures as well as the final structure. Additionally, the structures and methods disclosed herein may be used in conjunction with testing methodologies that incorporate intermediate verification of known good dies to increase the yield and decrease costs. 
     In some embodiments of the present disclosure, a semiconductor device including a passivation layer covering a surface of the substrate and enclosing an edge of an electrical conductor is provided. The passivation layer helps to enhance robustness of the electrical conductor, and alleviate stress between the substrate and the electrical conductor so as to reduce the risk of cracking. 
       FIG.  1    is a flow chart illustrating a method of manufacturing a semiconductor device according to various aspects of one or more embodiments of the present disclosure. The method  100  begins with operation  110  in which a substrate is received. The method proceeds with operation  120  in which an electrical conductor is formed over a surface of the substrate. The method proceeds with operation  130  in which a photo-curable material is selectively dispensed over the surface of the substrate. The method continues with operation  140  in which the photo-curable material is irradiated to form a passivation layer over the surface of the substrate, wherein the passivation layer partially covers an edge of the electrical conductor. 
     The method  100  is merely an example, and is not intended to limit the present disclosure beyond what is explicitly recited in the claims. Additional operations can be provided before, during, and after the method  100 , and some operations described can be replaced, eliminated, or moved around for additional embodiments of the method. 
       FIG.  2 A ,  FIG.  2 B ,  FIG.  2 C ,  FIG.  2 D ,  FIG.  2 E ,  FIG.  2 F  and  FIG.  2 G  are schematic views at one of various operations of manufacturing a semiconductor device according to one or more embodiments of the present disclosure, where  FIG.  2 A ,  FIG.  2 B ,  FIG.  2 C ,  FIG.  2 D ,  FIG.  2 E  and  FIG.  2 F  are schematic partial enlarged cross-sectional views, and  FIG.  2 G  is a schematic cross-sectional view. It is noted that the method of some embodiments may be a wafer level method. As depicted in  FIG.  2 A , a substrate  10  is received. In some embodiments, the substrate  10  may include a wafer, a semiconductor substrate, an interposer, a package substrate or the like. The substrate  10  includes a surface e.g., a first surface  10 A, and another surface e.g., a second surface  10 B opposite to the first surface  10 A. In some embodiments, the substrate  10  includes one or more through holes  10 H penetrating through the substrate  10 . In some embodiments, the through holes  10 H may be formed from the first surface  10 A of the substrate  10 . In some embodiments, the through holes  10 H may be formed from the second surface  10 B of the substrate  10 . In some embodiments, the through holes  10 H may be formed by recessing one of the first surface  10 A or the second surface  10 B of the substrate  10  without penetrating the substrate  10 , and then thinning the substrate  10  from the other one of the first surface  10 A or the second surface  10 B. In some embodiments, the substrate  10  is a thin substrate having a thickness in micrometer scale. In some embodiments, the thickness of the substrate  10  is substantially ranging from about 5 micrometers to about 15 micrometers such as about 10 micrometers, but is not limited thereto. In some embodiments, the through holes  10 H may be formed by isotropic etching, anisotropic etching, a combination thereof, or other suitable operation. In some embodiments, an sidewall of the through hole  10 H may be substantially perpendicular to the first surface  10 A or the second surface  10 B. In some embodiments, the sidewall of the through hole  10 H may be inclined with respect to the first surface  10 A or the second surface  10 B. In some embodiments, the dimension of the through hole  10 H proximal to the second surface  10 B is larger than the dimension of the through hole  10 H proximal to the first surface  10 A. In some embodiments, the dimension of the through hole  10 H proximal to the first surface  10 A is larger than the dimension of the through hole  10 H proximal to the second surface  10 B. 
     As depicted in  FIG.  2 B , one or more electrical conductors e.g., first electrical conductors  20  are formed over the first surface  10 A of the substrate  10 . In some embodiments, the first electrical conductors  20  may include, but are not limited to, conductive bumps such as controlled collapse chip connection bumps (C4 bumps) or the like. In some embodiments, the first electrical conductor  20  may include a first portion  21 , and a second portion  22  connected to the first portion  21 . In some embodiments, the first portion  21  is substantially formed in the through hole  10 H, and the second portion  22  is formed over the first surface  10 A of the substrate  10  and outside the through hole  10 H. The first electrical conductor  20  may include conductive material such as metal or alloy, but not limited thereof. In some embodiments, the material of the first electrical conductor  20  may include, but is not limited to, copper, an alloy thereof or the like. The first electrical conductor  20  may be formed by electroplating, deposition or other suitable operation. In some embodiments, the first portion  21  and the second portion  22  of the first electrical conductor  20  may be formed of the same material, but is not limited thereto. In some embodiments, the first portion  21  and the second portion  22  of the first electrical conductor  20  may be formed separately. In some embodiments, the first portion  21  may be formed in the through hole  10 H from the second surface  10 B of the substrate  10 , while the second portion  22  may be formed over the first surface  10 A of the substrate  10  after the first portion  21  is formed. In some embodiments, the first portion  21  and the second portion  22  of the first electrical conductor  20  may be formed from the first surface  10 A of the substrate  10 . In some embodiments, the first portion  21  of the first electrical conductor  20  includes a first width W 1 , and the second portion  22  of the first electrical conductor  20  includes a second width W 2  wider than the first width W 1 . In some embodiments, a height Ha of the second portion  22  is greater than a height of the first portion  21 , but not limited thereto. By way of example, the height Ha of the second portion  22  is substantially ranging from about 10 micrometers to about 50 micrometers, and the height Hb of the first portion  21  is substantially ranging from about 5 micrometers to about 20 micrometers such as about 10 micrometers, but not limited thereto. 
     In some embodiments, a conductive bump  26  may be formed over the second portion  22  of the first electrical conductor  20 . The conductive bump  26  may be configured to be electrically connected to a package substrate or other electronic device. In some embodiments, the conductive bump  26  is formed from a conductive material having a melting point lower than that of the first electrical conductor  20 . In some embodiments, the material of the conductive bump  26  may include, but is not limited to, tin (Sn), an alloy thereof or the like. 
     In some embodiments, a passivation layer is formed over the first surface  10 A of the substrate  10 . In some embodiments, the passivation layer may be formed by the operations illustrated in  FIG.  2 C  and  FIG.  2 D , but not limited thereto. As depicted in  FIG.  2 C , a photo-curable material  27  is selectively dispensed over the first surface  10 A of the substrate  10 . In some embodiments, the photo-curable material  27  includes a polymeric material with photo sensitive characteristic. In some embodiments, the polymeric material for the photo-curable material  27  may include, but is not limited to, epoxy, acrylic resin, polyimide (PI), polybenzoxazole (PBO) or the like. In some embodiments, the photo-curable material  27  may be selectively dispensed by printing or the like through a nozzle  28 . In some embodiments, the photo-curable material  27  is irradiated by light beams  29  such as UV beams or other magnetic wave simultaneously when it is dispensed. In some embodiments, the irradiation helps to reduce fluidity of the photo-curable material  27  and solidify the photo-curable material  27 . 
     As depicted in  FIG.  2 D , the passivation layer  30  may be formed over the first surface  10 A of the substrate  10 , partially covering an edge of the first electrical conductor  20  after the photo-curable material  27  is cured and solidified. In some embodiments, the passivation layer  30  partially covers an edge  22 E of the second portion  22  of the first electrical conductor  20 . In some embodiments, the passivation layer  30  is not disposed between an edge  21 E of the first portion  21  of the first electrical conductor  20  and the sidewall of the through hole  10 H. In some embodiments, the passivation layer  30  includes a first part  31  in contact with the edge  22 E of the second portion  22  of the first electrical conductor  20 , and a second part  32  apart from the edge  22 E of the second portion  22 , covering the first surface  10 A of the substrate  10 , and connected to the first part  31 . In some embodiments, the first part  31  of the passivation layer  30  at least partially covers the edge  22 E and partially exposes the edge  22 E of the second portion  22  of the first electrical conductor  20 . In some embodiments, the first part  31  of the passivation layer  30  may include a doughnut-shaped (i.e., ring-shaped) structure surrounding the edge  22 E of the second portion  22 , and the second part  32  is connected to the first part  31  and covers the first surface  10 A of the substrate  10 . In some embodiments, a first height H 1  of the first part  31  of the passivation layer  30  is lower than the height Ha of the second portion  22  of the first electrical conductor  20  as shown in  FIG.  2 D . In some alternative embodiments, the first height H 1  of the first part  31  of the passivation layer  30  may be substantially equal to the height Ha of the second portion  22  of the first electrical conductor  20  as shown in  FIG.  2 E . In some embodiments, the first height H 1  of the first part  31  is about half the height Ha of the second portion  22  or less than half the height Ha of the second portion  22 , but is not limited thereto. In some embodiments, a first height H 1  of the first part  31  of the passivation layer  30  is larger than a second height H 2  of the second part  32  of the passivation layer  30 . In some embodiments, a ratio of the first height H 1  to the second height H 2  is greater than 1 and substantially less than about 15, substantially greater than about 1.5 and substantially less than about 15, or substantially greater than about 1.5 and substantially less than about 8, but is not limited thereto. In some embodiments, the first height H 1  of the first part  31  is substantially ranging from about 5 micrometers to about 50 micrometers, substantially ranging from about 5 micrometers to about 40 micrometers, or substantially ranging from about 5 micrometers to about 30 micrometers, but is not limited thereto. In some embodiments, the second height H 2  of the second part  32  is substantially ranging from about 2 micrometers to about 15 micrometers, but is not limited thereto. 
     In some embodiments, the second part  32  of the passivation layer  30  helps to protect the substrate  10  from cracking, for example when the substrate  10  is thin. In some embodiments, the first part  31  of the passivation layer  30  with higher height H 1  helps to enhance the robustness of the first electrical conductor  20 , and helps to alleviate stress between the substrate  10  and the first electrical conductor  20 . 
     In some embodiments, the material of the photo-curable material  27  is hydrophilic, which helps the photo-curable material  27  to cover the edge  22 E of the second portion  22  of the first electrical conductor  20  due to capillary phenomenon. In such a case, the passivation layer  30  with different profiles can be formed without additional photolithography operation. In some embodiments, the photo-curable material  27  can be selectively dispensed to avoid residues on the first electrical conductor  20 , and additional descum treatment such as plasma treatment may be omitted. In some embodiments, the first part  31  of the passivation layer  30  formed by a hydrophilic material may have a curved surface  31 S. By way of example, the curved surface  31 S may include a concaved surface as depicted in  FIG.  2 F . 
     As depicted in  FIG.  2 G , other components or layers may be formed over the second surface  10 B of the substrate prior to or subsequent to formation of the first electrical conductors  20  and the passivation layer  30 . In some embodiments, a circuit layer  40  is formed over the second surface  10 B of the substrate  10  and electrically connected to the first electrical conductors  20 . In some embodiments, the circuit layer  40  may include, but is not limited to, a redistribution layer (RDL), a conductive post, a conductive pillar, a combination thereof or the like. In some embodiments, at least one semiconductor die  50  is formed over the circuit layer  40 . In some embodiments, the at least one semiconductor die  50  may include an active semiconductor die, a passive semiconductor die, or a combination thereof. By way of example, the at least one semiconductor die  50  may include a system on chip (SOC) die, a memory die or the like. In some embodiments, second electrical conductors  42  may be formed between the at least one semiconductor die  50  and the circuit layer  40 , and electrically connected to the at least one semiconductor die  50  and the circuit layer  40 . In some embodiments, the second electrical conductors  42  may include conductive bumps, conductive balls, conductive pastes or the like. In some embodiments, an underfill layer  44  may be formed over the second surface  10 B of the substrate  10 , between the at least one semiconductor die  50  and the circuit layer  40 , and around the second electrical conductors  42 . In some embodiments, the underfill layer  44  is configured to protect and fix the at least one semiconductor die  50  and the second electrical conductors  42 . In some embodiments, an encapsulant  46  may be formed over the second surface  10 B of the substrate  10 . In some embodiments, the encapsulant  46  may laterally enclose the at least one semiconductor die  50  and the underfill layer  44 . In some embodiments, the encapsulant  46  may further cover an upper surface of the at least one semiconductor die  50 . In some embodiments, the material of the encapsulant  46  may include, but is not limited to, a molding compound such as epoxy or the like. In some embodiments, the semiconductor device  1  may be a chip-on-wafer (CoW) device, but is not limited thereto. In some embodiments, a singulation operation such as dicing operation may be performed to form a semiconductor device  1 . In some embodiments, the semiconductor device  1  may be electrically connected to a package substrate through the first electrical conductors  20  to form a chip-on-wafer-on-substrate (CoWoS) package. 
     In some embodiments of the present disclosure, the passivation layer  30  with a thicken first part  31  seals the edge  22 E of the second portion  22  of the first electrical conductor  20 , and thus helps to enhance the robustness of the first electrical conductor  20 . The passivation layer  30  with the first part  31  covering the edge  22 E of the second portion  22  and the second part  32  covering the first surface  10 A of the substrate  10  may also help to compensate or alleviate stress between the substrate  10  and the first electrical conductor  20 , and thus may help to alleviate warpage of the substrate  10 . In some embodiments, the passivation layer  30  may be formed from the photo-curable material  27  by selectively dispensing. The photo-curable material  27  may be a hydrophilic material, which can climb up to the edge  22 E of the second portion  22  of the first electrical conductor  20  due to capillary phenomenon. In such a case, the passivation layer  30  with different profiles can be formed without additional photolithography operation. In some embodiments, the photo-curable material  27  can be selectively dispensed to avoid residues on the first electrical conductor  20 , and additional descum treatment may be omitted. 
     The semiconductor device and its manufacturing method of the present disclosure are not limited to the above-mentioned embodiments, and may have other different embodiments. To simplify the description and for the convenience of comparison between each of the embodiments of the present disclosure, the identical components in each of the following embodiments are marked with identical numerals. For making it easier to compare the difference between the embodiments, the following description will detail the dissimilarities among different embodiments and the identical features will not be redundantly described. 
       FIG.  3 A  and  FIG.  3 B  are schematic views of a semiconductor device according to one or more embodiments of the present disclosure, where  FIG.  3 A  is a schematic cross-sectional view, and  FIG.  3 B  is a schematic partial enlarged cross-sectional view. As depicted in  FIG.  3 A  and  FIG.  3 B , different from the semiconductor device  1  of  FIG.  2 E , the semiconductor device  2  may further include an insulative layer  24  formed over the first surface  10 A of the substrate  10  before formation of the second portion  22  of the first electrical conductor  20 . In some embodiments, the insulative layer  24  may include a polymeric material formed by low temperature operation. In some embodiments, the material of the insulative layer  24  may include, but is not limited to, polyimide. In some embodiments, the thickness of the insulative layer  24  is substantially ranging from about 0.5 micrometers to about 15 micrometers such as about 4 micrometers, but is not limited thereto. In some embodiments, the second portion  22  of the first electrical conductor  20  is formed over the insulative layer  24 , and electrically connected to the first portion  21 . In some embodiments, the passivation layer  30  is formed over the insulative layer  24 , partially covering an edge of the first electrical conductor  20 . In some embodiments, the passivation layer  30  may be formed in a similar way as disclosed in  FIG.  2 C , but is not limited thereto. In some embodiments, the passivation layer  30  includes the first part  31  with the first height H 1  and in contact with the edge  22 E of the second portion  22  of the first electrical conductor  20 , and the second part  32  with the second height H 2  and apart from the edge  22 E of the second portion  22  of the first electrical conductor  20  and connected to the first part  31 . 
       FIG.  4 A  and  FIG.  4 B  are schematic views of a semiconductor device according to one or more embodiments of the present disclosure, where  FIG.  4 A  is a schematic cross-sectional view, and  FIG.  4 B  is a schematic partial enlarged cross-sectional view. As depicted in  FIG.  4 A  and  FIG.  4 B , different from the semiconductor device  2  of  FIG.  3 A  and  FIG.  3 B , the insulative layer  24  of the semiconductor device  3  may be formed over the first surface  10 A of the substrate  10  before formation of the first portion  21  and the second portion  22  of the first electrical conductor  20 . In some embodiments, the first portion  21  of the first electrical conductor  20  is formed in the substrate  10 , and the insulative  24  is extended between the substrate  10  and the edge  21 E of the first portion  21  of the first electrical conductor  20 . In some embodiments, the second portion  22  of the first electrical conductor  20  is formed over the insulative layer  24 , and electrically connected to the first portion  21 . In some embodiments, the passivation layer  30  is formed over the insulative layer  24 , partially covering an edge of the first electrical conductor  20 . In some embodiments, the passivation layer  30  includes the first part  31  with the first height H 1  and in contact with the edge  22 E of the second portion  22  of the first electrical conductor  20 , and the second part  32  with the second height H 2  and apart from the edge  22 E of the second portion  22  of the first electrical conductor  20  and connected to the first part  31 . 
       FIG.  5 A ,  FIG.  5 B ,  FIG.  5 C  and  FIG.  5 D  are schematic views at one of various operations of manufacturing a semiconductor device according to one or more embodiments of the present disclosure, where  FIG.  5 A ,  FIG.  5 B  and  FIG.  5 C  are schematic cross-sectional views, and  FIG.  5 D  is a schematic partial enlarged cross-sectional view. As depicted in  FIG.  5 A , a substrate  10  is received. In some embodiments, a circuit layer  40  is formed over the second surface  10 B of the substrate  10 . In some embodiments, a dielectric layer  41  (shown in  FIG.  5 D ) may be formed between second surface  10 B of the substrate  10  and the circuit layer  40 . In some embodiments, at least one semiconductor die  50  is formed over the circuit layer  40 . In some embodiments, second electrical conductors  42  may be formed between the at least one semiconductor die  50  and the circuit layer  40 , and electrically connected to the at least one semiconductor die  50  and the circuit layer  40 . In some embodiments, an underfill layer  44  may be formed over the second surface  10 B of the substrate  10 , between the at least one semiconductor die  50  and the circuit layer  40 , and around the second electrical conductors  42 . In some embodiments, an encapsulant  46  may be formed over the second surface  10 B of the substrate  10 . 
     In some embodiments, first electrical conductors  20  may be formed over the first surface  10 A of the substrate  10 . In some embodiments, the first electrical conductor  20  may include a first portion  21 , and a second portion  22  connected to the first portion  21 . In some embodiments, the first portion  21  is substantially formed in a through hole  10 H, and the second portion  22  is formed over the first surface  10 A of the substrate  10  and outside the through hole  10 H. In some embodiments, the first portion  21  and the second portion  22  may be formed from the same conductive material. In some embodiments, the material of the first electrical conductor  20  may include, but is not limited to, tin, an alloy thereof or the like. In some embodiments, the width of the second portion  22  is wider than the width of the first portion  21 . 
     As depicted in  FIG.  5 B , a passivation layer  30  is formed over the first surface  10 A of the substrate  10 , partially covering an edge of the first electrical conductor  20 . In some embodiments, the passivation layer  30  may be formed in a similar way as disclosed in  FIG.  2 C , but is not limited thereto. In some embodiments, the passivation layer  30  includes the first part  31  with the first height H 1  (shown in  FIG.  5 D ) and in contact with the edge  22 E of the second portion  22  of the first electrical conductor  20 , and the second part  32  with the second height H 2  (shown in  FIG.  5 D ) and apart from the edge  22 E of the second portion  22  of the first electrical conductor  20  and connected to the first part  31 . In some embodiments, the passivation layer  30  may surround the edge  22 E of the second portion  22  of the first electrical conductor  20 . In some embodiments, an insulative layer  24  (shown in  FIG.  5 D ) may be formed prior to formation of the passivation layer  30 . In some embodiments, the second part  32  of the passivation layer  30  helps to protect the substrate  10  from cracking. In some embodiments, the first part  31  of the passivation layer  30  with higher height H 1  helps to enhance the robustness of the first electrical conductor  20 , and helps to alleviate stress between the substrate  10  and the first electrical conductor  20 . In some embodiments, the second portion  22  of the first electrical conductor  20  may include a first sub portion  221  laterally covered by the passivation layer  30 , and a second sub portion  222  laterally exposed from the passivation layer  30 . 
     As shown in  FIG.  5 C  and  FIG.  5 D , a reflow operation is performed on the first electrical conductor  20  after the passivation layer  30  is formed to form a semiconductor device  4 . In some embodiments, the first portion  21  of the first electrical conductor  20  is constrained by the substrate  10  during the reflow operation, and thus has a first width W 1  substantially the same as the width before the reflow operation. In some embodiments, the first sub portion  221  of the second portion  22  of the first electrical conductor  20  is constrained by the first part  31  of the passivation layer  30  during the reflow operation, and thus has a second width W 2  substantially the same as the width before the reflow operation. In some embodiments, the second sub portion  222  of the second portion  22  of the first electrical conductor  20  is exposed from the first part  31  of the passivation layer  30 , thereby extending laterally after the reflow operation, and thus has a third width W 3 . After the reflow operation, the second width W 2  is wider than the first width W 1 , the third width W 3  is wider than the second width W 2 , and the second sub portion  222  is protruded laterally to partially overlap the passivation layer  30 . 
       FIG.  6 A ,  FIG.  6 B  and  FIG.  6 C  are schematic views at one of various operations of manufacturing a semiconductor device according to one or more embodiments of the present disclosure, where  FIG.  6 A  and  FIG.  6 B  are schematic cross-sectional views, and  FIG.  6 C  is a schematic partial enlarged cross-sectional view. As depicted in  FIG.  6 A , different from the semiconductor device  4  of  FIG.  5 C  and  FIG.  5 D , the reflow operation is performed on the first electrical conductor  20  before the passivation layer  30  is formed. Since the second portion  22  of the first electrical conductor  20  is reflowed without being constrained, the second portion  22  of the first electrical conductor  20  is extended to have a substantially ball shape. 
     As depicted in  FIG.  6 B  and  FIG.  6 C , the passivation layer  30  is formed over the first surface  10 A of the substrate  10 , partially covering an edge of the first electrical conductor  20  to form a semiconductor device  5 . In some embodiments, the passivation layer  30  may be formed in a similar way as disclosed in  FIG.  2 C , but is not limited thereto. In some embodiments, the passivation layer  30  includes the first part  31  with the first height H 1  and in contact with a portion of the edge  22 E of the second portion  22  of the first electrical conductor  20 , and the second part  32  with the second height H 2  and apart from the edge  22 E of the second portion  22  of the first electrical conductor  20  and connected to the first part  31 . In some embodiments, the second width W 2  of the second portion  22  of the first electrical conductor  20  is wider than the first width W 1  of the first portion  21  of the first electrical conductor  20 . 
       FIG.  7 A  and  FIG.  7 B  are schematic views of a semiconductor device according to one or more embodiments of the present disclosure, wherein  FIG.  7 A  is a schematic cross-sectional view, and  FIG.  7 B  is a schematic partial enlarged cross-sectional view. As depicted in  FIG.  7 A  and  FIG.  7 B , different from the semiconductor device  1  of  FIG.  2 E , the passivation layer  30  of the semiconductor device  6  at least partially covers the edge  22 E of the second portion  22 , but exposes the first surface  10 A of the substrate  10 . In some embodiments, the passivation layer  30  may include a doughnut-shaped structure surrounding the edge  22 E of the second portion  22 . The passivation layer  30  may has a height H lower than or equal to the height Ha of the second portion  22  of the first electrical conductor  20 . In some embodiments, the passivation layer  30  with doughnut-shaped structure may be applied to other embodiments of the present disclosure. 
       FIG.  8 A  and  FIG.  8 B  are schematic views of a semiconductor device according to one or more embodiments of the present disclosure, wherein  FIG.  8 A  is a schematic cross-sectional view, and  FIG.  8 B  is a schematic partial enlarged cross-sectional view. As depicted in  FIG.  8 A  and  FIG.  8 B , the semiconductor device  7  includes a substrate  10 , first electrical conductors  20  adjacent to a first surface  10 A of the substrate  10 , and a passivation layer  30  over the first surface  10 A of the substrate  10 . In some embodiments, each of the first electrical conductors  20  includes a first portion  21  through the substrate  10 , and a second portion  22  over the first surface  10 A of the substrate  10  and connected to the first portion  21 . In some embodiments, the first portion  21  of the first electrical conductor  20  includes a first width W 1 , and the second portion  22  of the first electrical conductor  20  includes a second width W 2  wider than the first width W 1 . In some embodiments, the passivation layer  30  includes a first part  33  covering an edge  21 E of the first portion  21 , and a second part  34  between a surface  22 B of the second portion  22  and the first surface  10 A of the substrate  10 . In some embodiments, the semiconductor device  7  may further include a circuit layer  40 , at least one semiconductor die  50 , second electrical conductors  42 , an underfill layer  44  and an encapsulant  46  disposed over a second surface  10 B of the substrate  10 . 
     In some embodiments, the second part  34  of the passivation layer  30  has a height H substantially greater than about 10 micrometers. In some embodiments, the height H of the second part  34  is substantially ranging from about 10 micrometers to about 40 micrometers, or substantially ranging from about 10 micrometers to about 15 micrometers, but is not limited thereto. In some embodiments, the passivation layer  30  may include a polymeric passivation layer, and may be formed in a similar way as disclosed in  FIG.  2 C , but is not limited thereto. The second part  34  with a thicker thickness may help to provide a buffer and alleviate stress between the substrate  10  and the first electrical conductor  20 , so as to reduce the risk of cracking of the substrate  10  and delamination of the first electrical conductors  20 . 
     In some embodiments of the present disclosure, the passivation layer with a thicker part covering the edge of the electrical conductor helps to enhance the robustness of the electrical conductor, and helps to compensate or alleviate stress between the substrate and the electrical conductor. In some embodiments of the present disclosure, the passivation layer between the electrical conductor and the substrate helps to provide a buffer and alleviate stress between the substrate and the electrical conductor. In some embodiments of the present disclosure, the passivation layer may be formed from a hydrophilic photo-curable material by selectively dispensing, and can climb up to the edge of the electrical conductor. 
     In one exemplary aspect, a method of manufacturing a semiconductor device is provided. The method includes following operations. A substrate is received. An electrical conductor is formed over a surface of the substrate. A photo-curable material is selectively dispensed over the surface of the substrate. The photo-curable material is irradiated to form a passivation layer is formed over the surface of the substrate. The passivation layer partially covers an edge of the electrical conductor. 
     In another aspect, a method of manufacturing a semiconductor device is provided. The method includes following operations. A substrate is received. The substrate has at least a through hole penetrating the substrate. An electrical conductor is formed in the through hole and over a surface of the substrate. A conductive bump is formed over the electrical conductor. A photo-curable material is selectively dispensed over the surface of the substrate. The photo-curable material is irradiated to form a passivation layer over the surface of the substrate. The passivation layer partially covers an edge of the electrical conductor. 
     In yet another aspect, a method of manufacturing a semiconductor device is provided. The method includes following operations. A substrate is received. The substrate has a first surface and a second surface opposite to the first surface. At least a through hole penetrating the substrate is formed. A first electrical conductor is formed in the through hole and over the first surface of the substrate. A photo-curable material is selectively dispensed over the first surface of the substrate. The photo-curable material is irradiated to form a passivation layer over the first surface of the substrate. The passivation layer partially covers an edge of the first electrical conductor. 
     The foregoing outlines structures of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.