Patent Publication Number: US-7902912-B2

Title: Bias current generator

Description:
FIELD OF INVENTION 
     The present invention relates to a bias current generator. The invention more particularly relates to a bias current generator which provides bias current without requiring a resistor. 
     BACKGROUND OF INVENTION 
     Bias current generator circuits are well known in the art. Such circuits supply current for different sub-circuits of an integrated circuit. 
     An example of a prior art proportional to absolute temperature (PTAT) bias current generator  100  implemented using bandgap techniques is illustrated in  FIG. 1   a . The bias current generator  100  includes a first bipolar transistor Q 1  operating at a first collector current density and a second bipolar transistor Q 2  operating at a second collector current density which is less than that of the first collector current density. The emitter of the first bipolar transistor Q 1  is coupled to the inverting input of an operational amplifier A and the emitter of the second bipolar transistor Q 2  is coupled via a resistor r 1  to the non-inverting input of the amplifier A. The output of the amplifier A drives a current mirror arrangement comprising two PMOS transistors of similar aspect ratios, namely, MP 1  and MP 2  which are biased so that their gate-source voltage Vgs are the same. MP 1  and MP 2  force equal currents to the emitters of the two bipolar transistors, Q 1  and Q 2 . The collector current density difference between Q 1  and Q 2  may be established by having the emitter area of the second bipolar transistor Q 2  larger than the emitter area of the first bipolar transistor Q 1 . Alternatively multiple transistors may be provided in each leg, with the sum of the collector currents of each of the transistors in a first leg being greater than that in a second leg. As a consequence of the differences in collector current densities between the bipolar transistors Q 1  and Q 2  a base-emitter voltage difference (ΔV be ) is developed across the resistor r 1 . 
                     Δ   ⁢           ⁢     V   be       =       kT   q     ⁢     ln   ⁡     (   n   )                 (   1   )               
Where:
         k is the Boltzmann constant,   q is the charge on the electron,   T is the operating temperature in Kelvin,   n is the collector current density ratio of the two bipolar transistors.       

     This base emitter voltage difference (ΔV be ) is inherently PTAT. Assuming that the amplifier A is an ideal amplifier, the emitter currents of Q 1  and Q 2  are given by equation 2. 
     
       
         
           
             
               
                 
                   
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     The bias current generated may then be used to bias the sub-circuits of an integrated circuit by typically mirroring the current which flows through r 1 . 
     
       
         
           
             
               
                 
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     Referring now to  FIG. 1   b , another prior art current generator, in this case, a complimentary to absolute temperature (CTAT) current generator  110  is illustrated. The bias current generator  110  is substantially similar to the bias current generator  100 , and like components are identified by the same reference labels. The main difference between the bias current generator  100  and the current generator  110  is that a single bipolar transistor is coupled to the inputs of the amplifier A. The amplifier A forces the voltages at the non-inverting and inverting inputs of the amplifier A to be the same. The voltage at the non-inverting input is equal the base emitter voltage of Q 1 . Thus, the voltage at the inverting input is also equal to the base emitter voltage of Q 1 , which is inherently CTAT. Therefore, a CTAT voltage is developed across r 1 : 
     
       
         
           
             
               
                 
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     The temperature coefficients (TC) of the PTAT and CTAT bias currents according to  FIGS. 1   a  and  1   b  are influenced by the temperature dependence of resistors. Thus, the bias current is dependent on the value of the resistor r 1 . It will be appreciated by those skilled in the art that the resistance of resistors may vary from lot to lot of the order of +/−20%. As a consequence, the value of the bias current generated will also vary. A further disadvantage of the prior art current bias generators  100  and  110  is they occupy a large silicon area in an integrated chip. The resistor r 1  is one of the primary reasons why the current bias generators  100 ,  110  occupy a large silicon area. A circuit which occupies a large silicon area is undesirable for low current applications. 
     Another drawback of resistor based PTAT or CTAT current generators is related to the trimming methods. In order to reduce output current variation due to process variation different methods are used such that the resistor value of r 1  is trimmed for the desired output current. Laser trimming methods are used such that a small part of a resistor r 1  is “polished” until the desired output current is achieved. Laser trimming is also used to blow a short metal link across a resistor, part of r 1 , such that the total resistance increases and the bias current decreases. The trimming part of the circuits adopted for laser trimming usually requires large die area. MOS transistors configured as switches are typically coupled in series or parallel with the resistor r 1  such that the value of r 1  can be digitally controlled. MOS transistors used as switches add errors and nonlinearity on the resulting bias current generated due to the finite value of their drain-source resistance and corresponding nonlinearity. 
     There is therefore a need to provide a bias current generator which provides a bias current without incorporating a resistor. 
     SUMMARY OF INVENTION 
     These and other problems are addressed by providing a bias current generator incorporating a MOS device operating the triode region with a corresponding drain-source resistance r on  which behaves like a resistor. 
     These and other features will be better understood with reference to the followings Figures which are provided to assist in an understanding of the teaching of the invention. 
    
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
       The present application will now be described with reference to the accompanying drawings in which: 
         FIG. 1   a  is a schematic circuit diagram of prior art bias current generator. 
         FIG. 1   b  is a schematic circuit diagram of prior art bias current generator. 
         FIG. 2  is a schematic circuit diagram of a circuit provided in accordance with the teaching of the present invention. 
         FIG. 3  is a schematic circuit diagram of a circuit provided in accordance with the teaching of the present invention. 
         FIG. 4  is a schematic circuit diagram of a circuit provided in accordance with the teaching of the present invention. 
         FIG. 5  is a schematic circuit diagram of a circuit provided in accordance with the teaching of the present invention. 
         FIG. 6  is a schematic circuit diagram of a detail of the circuit of  FIG. 5 . 
         FIG. 7  is a schematic circuit diagram of a circuit provided in accordance with the teaching of the present invention. 
         FIG. 8  is a schematic circuit diagram of a circuit provided in accordance with the teaching of the present invention. 
     
    
    
     DETAILED DESCRIPTION 
     The invention will now be described with reference to some exemplary bias current generators which are provided to assist in an understanding of the teaching of the invention. It will be understood that these circuits are provided to assist in an understanding and are not to be construed as limiting in any fashion. Furthermore, circuit elements or components that are described with reference to any one Figure may be interchanged with those of other Figures or other equivalent circuit elements without departing from the spirit of the present invention. 
     Referring to the drawings and initially to  FIG. 2  there is illustrated a bias current generator circuit  200  which generates a bias current using a load MOS device as opposed to a resistor in accordance with the teaching of the present invention. The circuit  200  comprises a first PNP bipolar transistor Q 1 , and a second PNP bipolar transistor Q 2  operating at different collector current densities. The first bipolar transistor Q 1  operates at a higher collector current density than that of the second bipolar transistor Q 2 . In this exemplary arrangement Q 1  is a unity emitter area bipolar transistor and Q 2  consists of a plurality of parallel unity emitter area bipolar transistors. In this way it will be understood that the collector current density difference from Q 1  to Q 2  is related to the emitter area difference between Q 1  and Q 2 . An example of an alternative way to establish the collector current density difference from Q 1  to Q 2  is to provide the emitter area of the second bipolar transistor Q 2  a constant “n” times larger than the emitter area of the first bipolar transistor Q 1 . It will be appreciated by those skilled in the art that such differences in collector current density may be achieved in any one of a number of different ways and it is not intended to limit the teaching of the present invention to any one specific arrangement. 
     The first bipolar transistor Q 1  has its emitter coupled to the inverting terminal of an operational amplifier (op-amp) A, and the second bipolar transistor, Q 2  has its emitter coupled to the non-inverting terminal of the op-amp A. The collector and base of the first bipolar transistor Q 1 , and the collector of the second bipolar transistor Q 2  are coupled to a ground node gnd. The emitters of the bipolar transistors Q 1  and Q 2  are biased with current from a current mirror comprising four PMOS transistor MP 1 , MP 2 , MP 3 , and MP 4  each of which have their source coupled to a power supply Vdd and their gates coupled together. The aspect ratios of the PMOS transistors MP 1 , MP 2 , MP 3  and MP 4  are similar so that MP 1 , MP 2  and MP 3  mirror the drain current of MP 4 . The drain of the PMOS transistor MP 1  is coupled to the emitter of the first bipolar transistor Q 1 , and the drain of the PMOS transistor MP 2  is coupled to the emitter of the second bipolar transistor Q 2 . It will be appreciated by those skilled in the art that the collector current density difference between Q 1  and Q 2  can also be achieved by having the aspect ratio (Width/Length (W/L) of the MOS device) of MP 1  greater than the aspect ratio (W/L) of MP 2  so that the drain current of MP 1  is greater than the drain current of MP 1 . 
     The output of the op-amp A drives the gates of two NMOS transistors, a load NMOS device MN 1  and a biasing NMOS device MN 2 , which have different aspect ratios. The sources of both MN 1  and MN 2  are coupled to ground. The drain of MN 1  is coupled to the base of the second bipolar transistor Q 2  which is also coupled to the drain of the PMOS transistor MP 3 . The drain of MN 2  is coupled to the drain of the PMOS transistor MP 4  which is in a diode configuration. In this example, MN 1  consists of a plurality “n1” unity stripe NMOS transistor coupled together in parallel, and MN 2  consists of a plurality “n2” unity stripe NMOS transistor coupled together in parallel so that MN 1  and MN 2  have different aspect ratios. Alternatively, and as was mentioned above, the difference in aspect ratios between MN 1  and MN 2  may be achieved by appropriately varying the “Lengths” and “Widths” of the transistors. It will be appreciated by those skilled in the art that varying the aspect ratios may be achieved in any one of a number of different ways and it is not intended to limit the teaching of the present invention to any one specific arrangement. 
     In operation, the amplifier A forces its inverting and non-inverting inputs to the same voltage level, via MN 2 , MP 4 , MP 3 , MP 2 , MP 1 , such that the base-emitter voltage difference from Q 1  to Q 2  is reflected across MN 1  from drain to source. For n1&gt;n2 MN 2  operates in the saturation region and MN 1  operates in the triode region. The load NMOS transistor MN 1  is driven by the amplifier A so that it operates in the triode region with a corresponding drain-source resistance r on . As the drain of the load NMOS transistor MN 1  is coupled to the base of the second bipolar transistor Q 2  a base-emitter voltage difference (ΔV be ) resulting from the collector current density differences between the first and second bipolar transistors Q 1 , Q 2  is developed across the drain-source resistance r on  of MN 1 . The base-emitter voltage difference (ΔV be ) from Q 1  to Q 2  is reflected across r on  of MN 1  which results in generation of a bias current I bias . 
     
       
         
           
             
               
                 
                   
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     Referring now to  FIG. 3 , there is illustrated another bias current generator  300  which generates a bias current using a load MOS device in accordance with the teaching of the present invention. The bias current generator  300  is substantially similar to the bias current generator  200 , and like components are identified by the same reference labels. The main difference is that the amplifier A as well as having differential inputs also has differential outputs, namely, non-inverting output, o+, and inverting output, o−. The non-inverting output of the amplifier A, o+, is coupled to the gate of the biasing NMOS transistor MN 2 , and the inverting output of the amplifier A, o−, is coupled to the gate of the load NMOS transistor MN 1 . The load NMOS transistor MN 1  is driven by the amplifier A so that it operates in the triode region with a corresponding drain-source resistance r on . As the drain of the load NMOS transistor MN 1  is coupled to the base of the second bipolar transistor Q 2  a base-emitter voltage difference (ΔV be ) resulting from the collector current density differences between the first and second bipolar transistors is developed across the drain-source resistance r on  of MN 1 . The biasing NMOS transistor MN 2  is driven by the amplifier A to generate feedback currents for biasing the first and second bipolar transistors Q 1 , and Q 2 , and the load NMOS transistor MN 1  via MP 4 , MP 1 , MP 2  and MP 3 . There are two negative feedback loops around the amplifier A. The first negative feedback loop with dominant gain is from the non-inverting output, o+, via MN 2 , MP 4 , and MP 2  to the non-inverting input. The second negative feedback loop with less gain than the first feedback loop is from the inverting output, o−, via MN 1 , Q 2  to the non-inverting input of the amplifier A. Due to this double negative feedback the amplifier is more stable compared to the amplifier of circuit  200 . 
     Referring now to  FIG. 4 , there is illustrated another bias current generator  400  which, in accordance with the teaching of the present invention, generates a bias current without using a resistor. The bias current generator  400  is substantially similar to the bias current generator  200 , and like components are identified by the same reference labels. The main difference is that the amplifier A is illustrated at transistor level rather than at block level. The components that define the amplifier A are enclosed by the broken lines in  FIG. 4 . The amplifier A is a single stage amplifier with two input PMOS transistors, MP 6  and MP 7 , two load NMOS transistors, MN 3  and MN 4  and a self biased PMOS transistor MP 5 . MN 2  and MP 4  correspond to a second stage amplifier. The start-up circuit of the amplifier A is omitted for clarity. It will be appreciated that different architectures may be implemented for the first stage of the amplifier, for example, NMOS input pair, folded cascade, etc. 
     Referring now to  FIG. 5 , there is illustrated another bias current generator  500  which generates a PTAT bias current without using a resistor in accordance with the teaching of the present invention. The bias current generator  500  includes a first PNP bipolar transistor Q 1  operating at a first collector current density and a second PNP bipolar transistor Q 2  operating at a second collector current density which is less than that of the first collector current density. The emitter of the first bipolar transistor Q 1  is coupled to the non-inverting input of an operational amplifier A and the emitter of the second bipolar transistor Q 2  is coupled via a load device, namely, NMOS transistor MN 1  to the inverting input of the amplifier A. Thus, Q 1  is associated with one of the inputs to the amplifier A and Q 2  is associated with the other one of the inputs to the amplifier A. The bases and the collectors of both bipolar transistors Q 1  and Q 2  are coupled to ground. The output of the amplifier A drives a current mirror arrangement comprising two PMOS transistors of similar aspect ratios, namely, MP 1  and MP 2  which are biased so that their gate-source voltage Vgs are the same so that their drain currents are equal. The sources of the PMOS transistors MP 1 , MP 2  are coupled to Vdd. 
     A biasing device, in this case, a diode connected NMOS transistor MN 2  is connected in a cascoded manner intermediate the NMOS transistor MN 1  and the PMOS transistor MP 2 . The load NMOS transistor MN 1  is biased to operate in the triode region such that the NMOS transistor MN 1  has a corresponding drain-source resistance r on . In this arrangement MN 1  operates as a linear resistor. The NMOS transistor MN 2  is biased to operate in the saturation region. MN 1  and MN 2  are biased with the drain current from MP 2 . 
     The biasing of MN 1  and MN 2  is achieved by operably coupling MN 1  to MN 2  such that MN 2  is forced to operate in saturation, and MN 1  in the triode region (linear) region. In this embodiment, the gate and drain of MN 2  are coupled to the drain of the PMOS transistor MP 2 , while the source of MN 2  is coupled to the inverting input of the amplifier A. The drain of MN 1  is also coupled to the inverting input of the amplifier A, and the source of MN 1  is coupled to the emitter of the bipolar transistor Q 2 . The gate of MN 1  is tied to the gate and drain of MN 2 . 
     The collector current density difference between Q 1  and Q 2  may be established by having the emitter area of the second bipolar transistor Q 2  larger than the emitter area of the first bipolar transistor Q 1 . Alternatively multiple transistors may be provided in each leg, with the sum of the collector currents of each of the transistors in a first leg being greater than that in a second leg. As a consequence of the differences in collector current densities between the bipolar transistors Q 1  and Q 2  a base-emitter voltage difference (ΔV be ) is developed across the drain-source resistance r on  of MN 1  resulting in a PTAT bias current: 
     
       
         
           
             
               
                 
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     The bias current I bias  generated may be used to bias sub-circuits of an integrated circuit by mirroring the current which flows through MN 1 . 
     A trimming circuit Tr is coupled in parallel to the NMOS transistor MN 2 . This circuit provides for a varying of the gate source voltage of MN 2  which in turn varies the gate source voltage of MN 1 . The resistance r on  of MN 1  changes as the gate source voltage of MN 1  changes which allows the bias current to be tuned to a desired value. In this exemplary arrangement of a suitable trimming circuit, the trimming circuit Tr comprises a plurality of binary weighted NMOS transistors MNs selectively coupled in parallel with the biasing device MN 2 . For convenience only one NMOS transistor MNs is shown in  FIG. 5 , but it will be understood that it is not intended to limit the teaching of the present invention to any one specific arrangement. The trimming circuit Tr also comprises a switch S for selectively coupling the gate of transistor MNs to one of the drain and source of transistor MN 2 . It will be appreciated by those skilled in the art that the drain of transistor MN 2  is at a higher voltage than the source of transistor MN 2 . When the switch S couples the gate of MNs to the drain of MN 2  the transistor MNs is switched on resulting in MNs being coupled in parallel with MN 2 . As a consequence, the aspect ratio of the biasing device increases. This in turn results in the gate source voltage of MN 2  being reduced which reduces the gate source voltage of MN 1 . A reduction in the gate source voltage of MN 1  results in the resistance r on  of MN 1  increasing which in turn causes the bias current I bias  to reduce. When the switch S couples the gate of MNs to the source of MN 2  the transistor MNs is switched off thus MNs has no effect on the gate source voltage of MN 2  and the generated bias current remains unchanged. 
     Referring now to  FIG. 6  an exemplary implementation of the trimming circuit Tr of  FIG. 5  which is used for varying the r on  resistance of MN 1  is illustrated. The trimming circuit of  FIG. 6  comprises a plurality of trimming cells T 1  to Tn each comprising a corresponding NMOS transistor MN 2 _t 1  to MN 2 _tn. The NMOS transistors MN 2 _t 1  to MN 2 _tn have aspect ratios which are binary weighted. For example, the aspect ratio (W/L) of MN 2 _t 2  of cell T 2  is twice that of the aspect ratio (W/L) of MN 2 _t 1  of cell T 1 . The aspect ratio of the largest transistor MN 2 _tn is less than the aspect ratio of the biasing transistor MN 2 . The number/magnitude of the cells is related to the desired level of fine tuning required and the semiconductor process used to fabricate the current generator. In this schematic, only three cells T 1  to Tn are shown; however, it will be appreciated, that any desired number of cells may be provided. Typically, the trimming circuit Tr comprises either eight cells, sixteen cells, thirty-two cells, sixty-four cells, etc. For convenience only one trimming cell Tn will be described, however, it will be understood that the other two trimming cells T 1  and T 2  operate in the same manner as trimming cell Tn. The trimming cell Tn comprises an NMOS transistor MN 2 _tn and an CMOS inverter. The transistor MN 2 _tn and the CMOS inverter are coupled between the drain-source nodes MN 2 _d and MN 2 _s of MN 2 . The CMOS inverter comprises a PMOS transistor MP 1 _tn and an NMOS transistor MN 1 _tn with their gates coupled together. The CMOS inverter is driven by a logic signal B n  from a digital control block, and the output the CMOS inverter drives the gate of MN 1 _tn. If the logic signal B n  is ‘1’ the PMOS transistor MP 1 _tn is turned on and the NMOS transistor MN 1 _tn is turned off. Thus, when B n  is ‘1’ the gate of MN 2 _tn is coupled to the drain of MN 2  causing MN 2 _tn to be coupled in parallel with the biasing device MN 2 . As a consequence, the aspect ratio of the biasing device increases which results in the gate source voltage of MN 2  being reduced which in turn reduces the gate source voltage of MN 1 . A reduction in the gate source voltage of MN 1  results in the resistance r on  of MN 1  increasing which in turn causes the bias current I bias  to reduce. If the logic signal B n  is ‘0’ the PMOS transistor MP 1 _tn is turned off and the NMOS transistor MN 1 _tn is turned on. Thus, when B n  is ‘0’ the gate of MN 2 _tn is coupled to the source of MN 2  resulting in the generated bias current remaining unchanged as MN 2 _tn is switched off. 
     Referring now to  FIG. 7 , there is illustrated another bias current generator  600  which generates a CTAT bias current without using a resistor in accordance with the teaching of the present invention. The bias current generator  600  is substantially similar to the bias current generator  500 , and like components are identified by the same reference labels. The load NMOS transistor MN 1  operates in the triode region and the biasing device MN 2  operates in the saturation region. The main difference between the bias current generator  600  and the current generator  500  is that a single bipolar transistor is coupled to the inputs of the amplifier A. The amplifier A forces the voltages at its non-inverting and inverting input to be the same. The voltage at the non-inverting input is equal the base emitter voltage of Q 1 . Thus, the voltage at the inverting input is also equal to the base emitter voltage of Q 1 . Therefore, a CTAT voltage is developed across the drain-source resistance r on  of MN 1  resulting in a CTAT bias current: 
     
       
         
           
             
               
                 
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                   ( 
                   7 
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     Referring now to  FIG. 8 , there is illustrated another bias current generator  700  which generates a PTAT bias current without using a resistor in accordance with the teaching of the present invention. The bias current generator  700  includes a first PNP bipolar transistor Q 1  operating at a first collector current density and a second PNP bipolar transistor Q 2  operating at a second collector current density which is less than that of the first collector current density. The emitter of the first bipolar transistor Q 1  is coupled to the inverting input of the first amplifier A 1 . The emitter of the second bipolar transistor Q 2  is coupled to the non-inverting input of a first operational amplifier A 1  via a load NMOS transistor MN 1  operating in the triode region. The bases and collectors of both bipolar transistors Q 1  and Q 2  are coupled to ground. The load NMOS transistor MN 1  is operably coupled to a biasing device, in this case, a diode configured NMOS transistor MN 2  such that MN 1  operates in the triode region and MN 2  operates in saturation. The gate of MN 1  is coupled to the gate and drain of MN 2 , and the source of MN 1  is coupled to the non-inverting input of the amplifier A 1 . The output of the first amplifier A 1  drives the gates of two NMOS transistors MN 3  and MN 4  of substantially similar aspect ratios (W/L). The transistors MN 3  and MN 4  form part of a current mirror arrangement. 
     A trimming circuit Tr is operably coupled to the diode configured NMOS transistor MN 2  for varying the resistance r on  of the load MOS device MN 1 . It will be appreciated by those skilled in the art that by varying the resistance of MN 1  that the bias current can be tuned to a desired value. The trimming circuit Tr is substantially similar to the trimming circuit of  FIG. 5  and  FIG. 6  and operates in a similar manner. 
     A second amplifier A 2  which has an inverting input, non-inverting input and an output drives three PMOS transistors, namely, MP 1 , MP 2  and MP 3 . The three PMOS transistors are also part of the current mirror arrangement. The output of the second amplifier A 2  is coupled to the gates of MP 1 , MP 2  and MP 3 . The drain of MN 3  is coupled to the inverting input of the amplifier A 2 , and the drain of MN 4  is coupled to the non-inverting input of the amplifier A 2 . The sources of both MN 3  and MN 4  are coupled to ground. The drain of MP 1  is coupled to the gate-drain of MN 2 . The drain of MP 2  is coupled to the emitter of Q 1 . The drain of MP 3  is coupled to the drain of MN 4 . The non-inverting input of amplifier A 1  is coupled to the inverting input of the amplifier A 2 . 
     As a consequence of the differences in collector current densities between the bipolar transistors Q 1  and Q 2  a base-emitter voltage difference (ΔV be ) is developed across the drain-source resistance r on  of MN 1  resulting in a PTAT bias current: 
     
       
         
           
             
               
                 
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     The bias current flows from MN 1  to the drain of MN 3 . The second amplifier A 2  forces the voltages at its inverting and non-inverting inputs of A 2  to be the same. As MN 3  and MN 4  have the same aspect ratios and their drain source voltages as well as their gate source voltages are the same, their drain current will also be the same. In other words, the drain current of MN 4  will track the drain current of MN 3 . The drain current of MN 4  is mirrored by each of the PMOS transistors MP 1 , MP 2  and MP 3 . The aspect ratios of MP 3  and MP 2  are substantially similar, and therefore they provide substantially the same bias current. However, MP 1  supplies bias current to the emitter of Q 1  as well as the drain of MN 1 . Therefore, if Q 1  and Q 2  are to be biased with same amount of current the aspect ratio of MP 1  must be greater than the aspect ratio of MP 2  to account for some of the current which flows through MN 1 . 
     The bias current generator  700  has a high power supply rejection ratio due to the logarithmic relationship of base-emitter voltage of Q 1  and Q 2  versus their emitter currents. Thus, the bias current I bias  is less dependent in variations in the power supply. Furthermore, as the drain current of MN 4  tracks the drain current of MN 3  even slight variations in the supply voltage is inherently compensated. 
     It will be understood that what has been described herein are exemplary embodiments of circuits which have many advantages over the bias current generators known heretofore. By providing a transistor operating in the triode region circuits provided in accordance with the teaching of the invention are less sensitive to process variations compared to circuits using resistors. A further advantage is that the generator occupies less silicon area as the MOS devices used within the context of the present invention may be implemented in smaller silicon area than resistors. 
     While the present invention has been described with reference to exemplary arrangements and circuits it will be understood that it is not intended to limit the teaching of the present invention to such arrangements as modifications can be made without departing from the spirit and scope of the present invention. In this way it will be understood that the invention is to be limited only insofar as is deemed necessary in the light of the appended claims. 
     It will be understood that the use of the term “coupled” is intended to mean that the two transistor s are configured to be in electric communication with one another. This may be achieved by a direct link between the two transistors or may be via one or more intermediary electrical transistors or other electrical elements. 
     Similarly the words “comprises” and “comprising” when used in the specification are used in an open-ended sense to specify the presence of stated features, integers, steps or components but do not preclude the presence or addition of one or more additional features, integers, steps, components or groups thereof.