Patent Publication Number: US-7219238-B2

Title: Data transfer control device, electronic instrument, and data transfer control method

Description:
Japanese Patent Application No. 2002-77974, filed on Mar. 20, 2002, is hereby incorporated by reference in its entirety. 
   BACKGROUND OF THE INVENTION 
   The present invention relates to a data transfer control device, an electronic instrument, and a data transfer control method. 
   It has recently become popular to distribute digital audio-visual (AV) data by digital broadcasting or over the Internet. Together with the spread of this digital distribution of AV data, there have been increasing demands for digital recording/reproduction devices (electronic instruments) that are capable of recording the thus-distributed data efficiently. 
   A high-speed serial bus such as one in accordance with IEEE 1394 or the universal serial bus (USB) 2.0 is used for the transfer of AV data. A digital recording/reproduction device (electronic instrument) that records AV data is preferably provided with a storage medium such as a hard disk drive (HDD) that is capable of storing large volumes of data at high speed. 
   For that reason, the demand is increasing for a data transfer control device that can transfer data at high speed between a high-speed bus in accordance with IEEE 1394 or USB 2.0 and a storage medium such as an HDD. 
   The AV data might require copyright protection, depending on the contents thereof. It is therefore preferable that a data transfer control device that transmits AV data is also capable of protection with respect to the confidentiality of such AV data. 
   BRIEF SUMMARY OF THE INVENTION 
   According to a first aspect of the present invention, there is provided a data transfer control device for data transfer through a bus, comprising: 
   a second memory access control circuit which encrypts data transferred from a first bus side in accordance with a second encryption process, and writes the thus-encrypted data to a second memory; and 
   a third memory access control circuit which reads the encrypted data that has been written to the second memory, and transfers the thus-read encrypted data to a second bus side where a storage medium is connected. 
   According to a second aspect of the present invention, there is provided a data transfer control device for data transfer through a bus, comprising: 
   a third memory access control circuit which writes data to a second memory, the data having been encrypted by a second encryption process and transferred from a second bus side to which is connected a storage medium; and 
   a second memory access control circuit which reads the encrypted data that has been written to the second memory, decrypts the thus-read data by a second decryption process, and transfers the decrypted data to a first bus side. 

   
     BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING 
       FIGS. 1A and 1B  show examples of the configuration of an electronic instrument in accordance with one embodiment of the present invention. 
       FIGS. 2A ,  2 B,  2 C, and  2 D are illustrative of isochronous transfer and asynchronous transfer. 
       FIG. 3  shows the configuration of the data transfer control device in accordance with one embodiment of the present invention. 
       FIG. 4  shows the configuration of the data transfer control device of a comparative example. 
       FIGS. 5A ,  5 B, and  5 C are illustrative of the data transfer control method of one embodiment of the present invention. 
       FIGS. 6A ,  6 B, and  6 C are further illustrative of the data transfer control method of one embodiment of the present invention. 
       FIG. 7  is illustrative of the data transfer control method for the transfer of asynchronous data. 
       FIGS. 8A and 8B  show examples of the memory maps of the SRAM and SDRAM. 
       FIGS. 9A and 9B  are illustrative of a case in which SDRAM is provided outside the data transfer control device. 
       FIGS. 10A and 10B  are also illustrative of a case in which SDRAM is provided outside the data transfer control device. 
       FIG. 11  shows a detailed configurational example of the data transfer control device. 
       FIG. 12  shows a detailed configurational example of the data transfer control device. 
       FIGS. 13A ,  13 B, and  13 C are illustrative of the signals used by the data transfer control device. 
       FIGS. 14A and 14B  show the timing waveforms of the signals. 
       FIG. 15  is a flowchart illustrative of the operation of one embodiment of the present invention. 
       FIG. 16  is another flowchart illustrative of the operation one embodiment of the present invention. 
       FIG. 17  is a further flowchart illustrative of the operation one embodiment of the present invention. 
       FIG. 18  shows the configuration of the data transfer control device when one embodiment of the present invention is applied to USB. 
       FIG. 19  is a block diagram of an encryption circuit. 
       FIG. 20  is a flowchart illustrative of the encryption process. 
       FIG. 21  is a block diagram of a decryption circuit. 
   

   DETAILED DESCRIPTION OF THE EMBODIMENTS 
   Embodiments of the present invention will be described below. 
   Note that the embodiments described below do not in any way limit the scope of the invention laid out in the claims herein. In addition, all the elements of the embodiments described below should not be taken as essential requirements of the present invention. 
   According to one embodiment of the present invention, there is provided a data transfer control device for data transfer through a bus, comprising: 
   a second memory access control circuit which encrypts data transferred from a first bus side in accordance with a second encryption process, and writes the thus-encrypted data to a second memory; and 
   a third memory access control circuit which reads the encrypted data that has been written to the second memory, and transfers the thus-read encrypted data to a second bus side where a storage medium is connected. 
   In this embodiment, data transferred from the first bus side is encrypted by the second encryption process and is written to the second memory. The thus-written data is read from the second memory and is transferred to the second bus side to which is connected a storage medium or the like. 
   This configuration enables the second memory to function as cache memory for the data. If the second memory is provided outside the data transfer control device and connected to the data transfer control device through an external terminal and an external bus, encrypted data is input or output through the external terminal and the encrypted data is stored in the second memory or storage memory. This makes it possible to protect the confidentiality of data. 
   In this data transfer control device, the second memory access control circuit may encrypt isochronous data among data transferred from the first bus side, in accordance with the second encryption process, and write the thus-encrypted isochronous data to the second memory. 
   This configuration makes it possible to transfer data efficiently from the first bus side to the second bus side, while maintaining the confidentiality of isochronous data that is required to be transferred at a fixed transfer rate without break. 
   The data transfer control device may further comprise a first memory access control circuit which decrypts data by a first decryption process, and writes the decrypted data to a first memory provided within the data transfer control device, the data having been encrypted by a first encryption process and then transferred from the first bus side. The second memory access control circuit may read the data that has been written to the first memory, encrypt the thus-read data by the second encryption process, and write the encrypted data to the second memory. 
   This configuration makes it possible to decrypt encrypted data transferred from the first bus side, by the first encryption process, encrypt the decrypted data by the second encryption process, and write that data to the second memory through the first memory. This enables to utilize the first memory to implement data classification, and utilize the second memory to implement buffering of the data. 
   In this data transfer control device, a storage area of the first memory may include an isochronous data area in which isochronous data is stored and another area; the first memory access control circuit may decrypt isochronous data which has been encrypted by a first encryption process and then transferred from the first bus side, by the first decryption process, and write the decrypted isochronous data to the isochronous data area in the first memory; and the second memory access control circuit may read the thus-written isochronous data in the isochronous data area of the first memory, encrypt the thus-read isochronous data by the second encryption process, and write the encrypted isochronous data to the second memory. 
   This configuration makes it possible for the first memory to function as memory for classifying isochronous data. This makes it possible to simplify the process of writing isochronous data from the first memory to the second memory. 
   In this data transfer control device, the second memory access control circuit may bypass the second encryption process for data that does not require encryption, and write the data into the second memory. 
   This configuration makes it possible to implement the optimal transfer processing in accordance with the contents of the data. 
   According to one embodiment of the present invention, there is provided a data transfer control device for data transfer through a bus, comprising: 
   a third memory access control circuit which writes data to a second memory, the data having been encrypted by a second encryption process and transferred from a second bus side to which is connected a storage medium; and 
   a second memory access control circuit which reads the encrypted data that has been written to the second memory, decrypts the thus-read data by a second decryption process, and transfers the decrypted data to a first bus side. 
   In this configuration, encrypted data which is transferred from the second bus side to which a storage medium or the like is connected is written to the second memory. The thus-written encrypted data is then read from the second memory, is decrypted by the second decryption process, and is transferred to the first bus side. 
   This configuration enables the second memory to function as cache memory for the data. If the second memory is provided outside the data transfer control device and connected to the data transfer control device through an external terminal and an external bus, encrypted data is input or output through the external terminal and the encrypted data is stored in the second memory. This makes it possible to protect the confidentiality of data. 
   In this data transfer control device, the third memory access control circuit may write isochronous data from among data which has been transferred from the second bus side to which is connected a storage medium, to the second memory. 
   This configuration makes it possible to transfer data efficiently from the second bus side to the first bus side, while maintaining the confidentiality of isochronous data that is required to be transferred at a fixed transfer rate without break. 
   The data transfer control device may further comprise a first memory access control circuit, wherein: 
   the second memory access control circuit may read encrypted data that has been written to the second memory, decrypt the thus-read data by the second decryption process, and write the decrypted data to a first memory; and 
   the first memory access control circuit may read data that has been written to the first memory, encrypt the thus-read data by a first encryption process, and transfer the encrypted data to the first bus side. 
   This configuration makes it possible to decrypt encrypted data from the second memory, by the second decryption process, and write it to the first memory, read the decrypted data from the first memory and encrypt it by the first encryption method, and transfer the encrypted data to the first bus side. This makes it possible to utilize the second memory to implement data buffering and utilize the first memory to implement packet processing. 
   In this data transfer control device, a storage area of the first memory may include an isochronous data area in which isochronous data is stored and another area; 
   the second memory access control circuit may read encrypted isochronous data that has been written to the second memory, decrypt the thus-read isochronous data by the second decryption process, and write the decrypted isochronous data to the isochronous data area in the first memory; and 
   the first memory access control circuit may read the isochronous data that has been written to the isochronous data area of the first memory, encrypt the thus-read isochronous data by the first encryption process, and transfer the encrypted isochronous data to the first bus side. 
   This configuration makes it possible for the first memory to function as memory for classifying isochronous data. This simplifies the processing for writing isochronous data from the second memory to the second memory. 
   In this data transfer control device, the second memory access control circuit may bypass the second decryption process for data that does not require decryption, and transfer the data to the first bus side. 
   This configuration makes it possible to implement the optimal transfer processing in accordance with the contents of the data. 
   In this data transfer control device, the second memory may be a synchronized type of memory that is capable of inputting and outputting data having sequential addresses in synchronization with a clock. 
   If a synchronized type of memory is used for the second memory, it is possible to efficiently transfer isochronous data or the like that is to be transferred as burst data. 
   According to one embodiment of the present invention, there is provided an electronic instrument comprising the above described data transfer control device; and a storage medium connected to the second bus, for storing data transferred through the second bus. 
   According to one embodiment of the present invention, there is provided a data transfer control method for data transfer through a bus, comprising: 
   encrypting data transferred from a first bus side, by a second encryption process, and writing the encrypted data to a second memory provided outside a data transfer control device, through an external terminal of the data transfer control device; and 
   reading the encrypted data that has been written to the second memory, through the external terminal of the data transfer control device, and transferring the thus-read data to a second bus side to which is connected a storage medium. 
   According to one embodiment of the present invention, there is provided a data transfer control method for data transfer through a bus, comprising: 
   writing data to a second memory provided outside a data transfer control device, through an external terminal of the data transfer control device, the data having been encrypted by a second encryption process and transferred from a second bus side to which is connected a storage medium; and 
   reading the encrypted data that has been written to the second memory, through the external terminal of the data transfer control device, decrypting the thus-read data by a second decryption process, and transferring the decrypted data to a first bus side. 
   These embodiments will be described in detail below, with reference to the accompanying figures. 
   1. Electronic Instrument 
   A typical block diagram of an electronic instrument (digital recording/reproduction device) that comprises a data transfer control device  30  according to one embodiment of the present invention is shown in  FIG. 1A , and a typical external view thereof is shown in  FIG. 1B . 
   This electronic instrument  16  comprises a hard disk drive (HDD)  10  and the data transfer control device  30 . It also comprises an operating section  12  that enables the user to operate the electronic instrument. It further comprises a display section  14  (LCD) that displays various items of information to the user. 
   The user can specify details such as the reproduction mode (normal reproduction or special reproduction), by operating the operating section  12 . Details such as the current reproduction mode can be confirmed by viewing information that is displayed on the display section  14 . 
   This electronic instrument  16  is connected to a digital tuner  20  (or digital video camera) by a first bus BUS 1  such as an IEEE 1394 bus or a USB 2.0 bus. The digital tuner  20  also comprises a moving picture experts group (MPEG) decoder  21  (generally speaking: a decoder), where this MPEG decoder  21  decrypts an MPEG stream that has been received by components such as an antenna  26 . A television  24  (display section) displays images and outputs sounds, based on the decrypted data. The user uses an operating section  22  (such as a remote control) to perform operations such as select a channel (broadcast station) or specify a reproduction mode (normal reproduction or special reproduction). 
   During the recording of an MPEG stream to the HDD  10  (generally speaking: a storage medium) for audio-visual (AV) use, the MPEG stream (TS packets) that has been received by the antenna  26  is written to the HDD  10  via the BUS 1  (IEEE 1394 or USB 2.0) and the data transfer control device  30 . 
   During the reproduction of an MPEG stream from the HDD  10 , on the other hand, the MPEG stream (TS packets or isochronous data) is read from the HDD  10  through a second bus BUS 2  such as an integrated device electronics (IDE) bus. The thus-read MPEG stream is transferred to the digital tuner  20  through the BUS 1  and is decrypted by the MPEG decoder  21  of the digital tuner  20 . This causes the display of images on the television  24 . 
   Note that the electronic instrument to which the present invention is applied is not limited to the electronic instrument shown in  FIGS. 1A and 1B . The present invention could also be applied to various other electronic instruments such as a video tape recorder (with internal HDD), an optical disk (DVD) recorder, a digital video camera, a personal computer, or a portable type of information terminal. 
   2. Isochronous Transfer 
   The packet transfer methods provided by IEEE 1394 are asynchronous transfer (ideal for data transfer where reliability is required) and isochronous transfer (ideal for the transfer of data such as moving images and sounds, real-time capabilities are required). Asynchronous transfer is a transfer method that does not guarantee the transfer rate of the data but does guarantee the reliability of the data. Isochronous transfer, on the other hand, is a transfer method that does not guarantee the reliability of the data but does guarantee the immediacy of the transfer. This isochronous transfer is supported by the universal serial bus (USB) standard. 
   The bus states during data transfer under IEEE 1394 are shown schematically in  FIG. 2A . 
   An isochronous transfer starts with the cycle master generating a cycle-start packet every fixed period. This enables the transfer of at least one isochronous (ISO) packet every 125 μs (every isochronous transfer cycle), per channel. As a result, it is possible to transfer requested data such as moving images and sounds, in a real-time manner. 
   Asynchronous transfer occurs in the intervals between isochronous transfers. In other words, with IEEE 1394, isochronous transfer has a higher priority than asynchronous transfer, and the remaining periods after isochronous transfer has ended are utilized for the transfer of asynchronous (ASY) packets. 
   An example of the format of an isochronous transfer packet during the transfer of an MPEG stream over an IEEE 1394 bus is shown in  FIG. 2B . 
   In  FIG. 2B , the ISO header corresponds to the header of a packet in IEEE 1394 format and the common isochronous packet (CIP) header, source packet (SP) header, and transport stream (TS) packet correspond to the data (payload) of a packet in IEEE 1394 format. 
   Examples of the formats of these SP and CIP headers are shown in  FIGS. 2C and 2D . These SP and CIP headers are defined by the IEC 61883 standard that laid down the protocol for the transfer of an MPEG stream over an IEEE 1394 bus. The SP header comprises data such as time stamp information (number of cycles for the isochronous transfer and an offset within the isochronous transfer cycles). The CIP header declares that the data to be transferred is MPEG data, it specifies the division method of the MPEG TS packets, and it also comprises data such as source node ID, data block size, and format ID. 
   Note that the SP header is not necessary if the electronic instrument connected to the IEEE 1394 bus is a digital video camera or the like, instead of a digital tuner. In such a case, time stamp information is comprised within the CIP header. 
   3. Data Transfer Control Device 
   An example of the configuration of the data transfer control device of this embodiment (denoted by  30  in  FIG. 1 ) is shown in  FIG. 3 . Note that the data transfer control device does not necessarily comprise all of the circuits and units (components) shown in  FIG. 3 ; it is also possible to have a configuration in which some of them are omitted. 
   The data transfer control device of  FIG. 3  comprises a 1394 interface  31  (generally speaking: a first bus interface). This 1394 interface  31  implements an interface between the data transfer control device and other electronic instruments (such as a digital tuner) connected to an IEEE 1394 bus (the first bus BUS 1 ). It also comprises a physical layer (PHY) circuit  32  and link layer circuit  33  that implement a physical layer and a link layer under the IEEE 1394 protocol. 
   The data transfer control device comprises an IDE interface  34  (generally speaking: a second bus interface or an interface for storage media). The IDE interface  34  is circuitry that implements an interface between the data transfer control device and the hard disk drive HDD  10  (generally speaking: a storage medium). 
   If the HDD  10  is for AV use, an inexpensive HDD having an IDE (ATA) interface, which is widely used for personal computers, is used therefor. For an electronic instrument such as a digital tuner (BS tuner or CS tuner), on the other hand, IEEE 1394 is widely used as the interface for digital data (digital video data or digital audio data). 
   If the 1394 interface  31  and the IDE interface  34  are provided, as shown in  FIG. 3 , a conversion bridge function between IEEE 1394 (generally speaking: a first bus standard) and IDE (generally speaking: a second bus standard) could be implemented in the data transfer control device. 
   The data transfer control device comprises an SRAM interface  42  that implements an interface with static random access memory (SRAM)  40 . It also comprises an SDRAM interface  52  that implements an interface with synchronous dynamic random access memory (SDRAM)  50 . 
   In this case, the SRAM  40  (generally speaking: a first memory, packet memory or packet buffer) is smaller in capacity than the SDRAM  50  (second memory). Random access memory can be operated at high speeds. 
   This SRAM  40  has the function of temporarily storing packets (ISO packets or TS packets) that have been received through the first bus BUS 1  (IEEE 1394 or the like). The HDD  10  storage medium has the function of temporarily storing packets that have been read from the second bus BUS 2 , for transfer over BUS 1 . 
   The SRAM  40  is memory that can be accessed at random by components such as a first direct memory access controller (DMAC 1 ), a DMAC 2 , and a processing section  60  (such as a CPU, MPU, or system controller). In this case, the SRAM interface  42  functions as a mediation circuit. In other words, the SRAM interface  42  mediates accesses from the DMAC 1  (accesses from the BUS 1  side), accesses from the processing section  60 , and accesses from the DMAC 2  (accesses from the BUS 2  side). A data path is established between the SRAM  40  and one of the DMAC 1 , the DMAC 2 , and the processing section  60 , based on the mediation result. 
   Note that the SRAM  40  is preferably provided within the data transfer control device but it could also be provided outside of the data transfer control device. 
   The storage area of the SRAM  40  could be divided into a header area (control information area) and a data area, or into a transmission area and a reception area. It could also be divided into an asynchronous area and an isochronous area. 
   The SDRAM  50  (generally speaking: a second memory, cache memory or synchronized type of memory), on the other hand, has a larger capacity than the SRAM  40 . It is a memory that can be accessed sequentially (in which access to sequential addresses can be done) at a higher speed than random access (or the SRAM  40 ). It is also a memory that enables the input and output of data (burst data) with sequential addresses, in synchronization with a clock. This SDRAM  50  functions as a cache memory for isochronous data. 
   Note that the SDRAM  50  is preferably provided outside of the data transfer control device but it could also be provided within the data transfer control device. Instead of ordinary SDRAM, other high-speed synchronized types of memory such as DDR SDRAM or RDRAM made by the Rambus company could be used therefor. 
   The storage area of the SDRAM  50  could be divided into a transmission area and a reception area, or into an asynchronous area and an isochronous area. 
   The data transfer control device comprises the DMAC 1  (generally speaking: a first memory access control circuit) This DMAC 1  performs processing for writing packets (data and headers) from the first bus BUS 1  side (the 1394 interface  31 ) to the SRAM  40 . It also performs processing for reading data (isochronous data) that has been written to the SRAM  40  and transferring packets (isochronous packets) assembled from this data and headers to the BUS 1  side. 
   More specifically, the DMAC 1  generates write request and write addresses during a write to the SRAM  40 . Similarly, it generates read requests and read addresses during a read from the SRAM  40 . This implements DMA transfer between the SRAM  40  and the 1394 interface  31  (BUS 1 ), without involving the processing section  60 . 
   The data transfer control device comprises the DMAC 2  (generally speaking: a second memory access control circuit). This DMAC 2  performs processing to read isochronous data that has been written to the SRAM  40  and write the thus-read data to the SDRAM  50  that has a larger capacity than the SDRAM  50 . It also performs processing to read isochronous data that has been written to the SDRAM  50  and write the thus-read isochronous data to the SRAM  40 . 
   More specifically, the DMAC 2  generates read requests and read addresses during a read from the SRAM  40  or the SDRAM  50 . Similarly, it generates write requests and write addresses during a write to the SRAM  40  or the SDRAM  50 . This implements DMA transfer between the SRAM  40  and the SDRAM  50 , without involving the processing section  60 . 
   The data transfer control device comprises a DMAC 3  (generally speaking: a third memory access control circuit). This DMAC 3  performs processing for reading isochronous data that has been written to the SDRAM  50  and transferring the thus-read isochronous data to the BUS 2  side (the IDE interface  34 ). It also performs processing for writing the isochronous data that has been transferred from the BUS 2  side to the SDRAM  50 . 
   More specifically, the DMAC 3  generates read requests and read addresses during a read from the SDRAM  50 . Similarly, it generates write requests and write addresses during a write to the SDRAM  50 . This implements DMA transfer between the SDRAM  50  and the BUS 2  (the IDE interface  34 ), without involving the processing section  60 . 
   The DMAC 1  comprises a first encryption/decryption circuit ENC/DEC 1  (on the 1394 side). This ENC/DEC 1  performs processing for encrypting data (isochronous data) that has been read from the SRAM  40  in accordance with a first encryption process, for transfer to the BUS 1  side. It also performs processing for decrypting encrypted data (encrypted isochronous data) that has been transferred from the BUS 1  side in accordance with a first decryption process, for writing to the SRAM  40 . 
   In such a case, processing such as that in accordance with Digital Transmission Content Protection (DTCP), which is an encryption standard under IEEE 1394, could be utilized as the first encryption process (decryption process). 
   In this case, DTCP (5C DTCP) is a standard for the transmission of encrypted data between electronic instruments (devices) connected by IEEE 1394. Before encrypted data that ought to be protected is transmitted between electronic instruments, this DTCP enables certification to verify whether or not the electronic instrument on the reception side is provided with a data protection mechanism. If it is verified by the certification processing that a protection mechanism is provided, a key for unlocking the encryption is exchanged between the electronic instruments. The electronic instrument on the transmission side transmits the encrypted data and the electronic instrument on the reception side decrypts the thus-received encrypted data. 
   This configuration makes it possible to transmit protected data between electronic instruments conforming to DTCP. This enables protection of data contents from an electronic instrument that does not have a protection mechanism or an electronic instrument that attempts to modify the data. 
   This DTCP also provides for the exchange between electronic instruments of copy control information that has been set by a contents provider. This enables copy controls such as “copy prohibited”, “single copy enabled”, and “freely copyable”. revision information (system renewability messages) can be distributed together with the contents. This makes it possible to prohibit and suppress data transfer to illegal electronic instruments and inhibit illegal copying in the future. In addition, this DTCP is expected to be utilized not only with IEEE 1394, but also as the USB encryption standard. 
   Note that the DTCP encryption and decryption processes are described in detail on the homepage of the Digital Transmission Licensing Administrator (DTLA). 
   The DMAC 2  comprises a second (IDE side) the encryption/decryption circuit ENC/DEC 2 . This ENC/DEC 2  performs processing to encrypt data (isochronous data, or data transferred from the BUS 1  side) that has been read from the SRAM  40  in accordance with a second encryption process, for writing to the SDRAM  50 . It also performs processing to decrypt encrypted data (encrypted isochronous data) in accordance with a second decryption process, for transfer to the SRAM  40  (processing for transfer to the BUS 1  side). 
   In such a case, processing such as that in accordance with the Data Encryption Standard (DES), which is a common-key encryption method, could be utilized as the second encryption process (decryption process). 
   Common-key encryption methods are encryption methods that are widely used in fields such as the financial world. These common-key encryption methods use the same key for encryption and decryption. Among the common-key encryption methods, DES is the most widely used. 
   This DES uses 16-stage iterations of non-linear conversion (sbox) and transverse processing for blocks of 64 bits of data. A 48-bit sub-key is used in the processing at each stage, where these sub-keys are created from a 64-bit common key. 
   Within DES are single DES (SDES) and triple DES (TDES) TDES is an encryption method that repeats the SDES algorithm three times. This TDES enables the use of the SDES algorithm and, since it achieves an effect similar to increasing the length of the encryption key, it enables an increase in the strength of the encryption in a comparatively simple manner. 
   Note that the data transfer control device of this embodiment can also be applied to the Advanced Encryption Standard (AES), which is a common-key encryption method that supersedes DES, in addition to DES (single DES or triple DES). 
   The data transfer control device comprises the processing section  60 . This processing section  60  controls the various circuits and units (components) within the device and also provides overall control of the device. The functions of the processing section  60  could be implemented by hardware such as a CPU or system controller (ASIC) or by firmware (a program). Note that processing section  60  could be provided outside of the data transfer control device. 
   The data transfer control device comprises a memory pointer management circuit  70 . This memory pointer management circuit  70  is a circuit for managing read and write pointers (pointers indicating addresses in memory) of the SRAM  40  (or the SDRAM  50 ). The DMAC 1  and DMAC 2  use the pointers managed (controlled) by the memory pointer management circuit  70  to generate memory addresses and implement DMA transfers. 
   An automatic DMA determination circuit  72  (generally speaking: a automatic memory access determination circuit) comprised by the memory pointer management circuit  70  is a circuit that determines whether or not the amount of received data in the SRAM  40  has exceeded a given transfer unit (transfer data quantity. If the quantity of reception data has exceeded a given transfer unit (for example, N bytes), this automatic DMA determination circuit  72  makes an automatic DMA (memory access) start signal go active. This ensures that the DMAC 2  reads the above described transfer unit of data (isochronous data) from the reception data area of the SRAM  40 , and transfers it to the SDRAM  50  (BUS 2 ) side. The ENC/DEC 2  encrypts the data in the above described transfer units. 
   The data transfer control device comprises a transfer number reservation register TNREG. This transfer number reservation register TNREG is a register that the processing section  60  uses for reserving the number of transfers for an isochronous packet (generally speaking: a packet) comprising isochronous data. 
   In other words, the DMAC 1  reads isochronous packet (isochronous data and isochronous header) from the SRAM  40 . It then performs processing for transferring the thus-read isochronous packet automatically at each isochronous transfer cycle (125 μs) to the BUS 1  side (transfer without involving the processing section  60 ), until the number of transfers reserved in TNREG reaches zero. 
   Note that if the number of transfers reserved in TNREG reaches zero, the automatic transfer is suspended at the next isochronous transfer cycle and an interrupt is generated with respect to the processing section  60 . 
   The TNREG comprises a transfer number reservation register TNREGK for the page area of the Kth (where K=0, byway of example) header area of the SRAM  40  and a transfer number reservation register TNREGL for the page area of the Lth (where L=1, by way of example) header area. 
   When the processing section  60  is preparing the isochronous header to be written to the Kth page area, the DMAC 1  reads the isochronous header written to the Lth page area and the isochronous data written to the data area, from the SRAM  40 . Isochronous packets configured of the thus-read isochronous header and isochronous data are then transferred automatically to the BUS 1  side, until the reserved number of transfers in TNREGL reaches zero. 
   When the processing section  60  is preparing the isochronous header to be written to the Lth page area, the DMAC 1  reads the isochronous that is written to the Kth page area and the isochronous that is written to the data area, from the SRAM  40 . Isochronous packets configured of the thus-read isochronous header and isochronous data are then transferred automatically to the BUS 1  side, until the reserved number of transfers in TNREGK reaches zero. 
   A data transfer control device in accordance with a comparative example is shown in  FIG. 4 . 
   The main difference between  FIGS. 3 and 4  is the lack of components such as the DMAC 2  that implements DMA transfer between SRAM and SDRAM, the SDRAM interface  52 , the transfer number reservation register TNREG, and the automatic DMA determination circuit  72 . 
   The configuration of the comparative example of  FIG. 4  is suitable for the transfer of file data of a personal computer. For high-speed transfer of AV data, however, the configuration of this embodiment shown in  FIG. 3  is more appropriate. 
   In other words, IEEE 1394 enables the transfer of AV data by an isochronous method. In such a case, the isochronous transfer transfers isochronous packets without breaks, at a fixed transfer rate or higher. With the reading or writing of data with respect to an HDD  510 , on the other hand, it is necessary to have an access time (head seek time) of a fixed length. Thus, with a configuration in which only a small-capacity SRAM  540  is provided, as in  FIG. 4 , it is not possible to provide slack-absorbing buffering of isochronous packets to be transferred without breaks. In other words, if there is any delay in the processing of writing to the HDD  510 , due to the head seek time, it will not be possible to receive isochronous packets. If there is any delay in reading from the HDD  510 , it will be impossible to transmit isochronous packets. 
   In contrast thereto, the configuration of this embodiment shown in  FIG. 3  uses the SDRAM  50  that functions as a cache memory, to buffer the isochronous data. This therefore enables slack-absorbing buffering of the isochronous data to be transferred without breaks, even if there is some delay in the write processing or read processing with respect to the HDD  510 , making it possible to guarantee data continuity. In other words, it is possible to increase the reproduction capabilities of AV data, by using the inexpensive SDRAM  50 , which can be obtained easily, to cache the isochronous data, thus guaranteeing the data transfer rate. 
   In particular, a fixed quantity of data is transferred sequentially by isochronous transfer. In other words, a certain quantity of continuous image data or sound data is transferred as a batch. With  FIG. 3 , therefore, the use of the SDRAM  50  that can perform rapid sequential access (access to sequential addresses) as cache memory for isochronous data makes it possible to implement efficient buffering of the isochronous data. 
   On the other hand, data classification or the like is performed in the SRAM  40 . The processing section  60  randomly accesses a desired address of the SRAM  40  and performs packet processing such as writing a header of a packet to be transferred or analyzing a packet. Therefore, if the SRAM  40  which can perform random access at higher speed than the SDRAM  50  is used as a memory for classification and packet processing, classification and packet processing can be efficiently implemented. 
   In this embodiment as shown in  FIG. 3 , the SRAM  40  is used as memory for data classification processing and packet processing and the SDRAM  50  is used as cache memory for isochronous data, enabling memory usage that has not been possible up to now. This enables the implementation of efficient data transfer processing that is not possible with the configuration of  FIG. 4 . 
   4. Data Transfer Control Method 
   The data transfer control method according to one embodiment of the present invention will now be described with reference to  FIGS. 5A ,  5 B,  6 A, and  6 B. 
   In the embodiment shown in  FIG. 5A , the storage area of the SRAM (first memory) is separated into an area for storing isochronous data and another area. 
   During reception, as shown in  FIG. 5A , the DMAC 1  selects an isochronous packet from the packets transferred to the BUS 1  side, and writes the isochronous data comprised within the isochronous packet to the isochronous data area of the SRAM  40 . During this time, the first encryption/decryption circuit ENC/DEC 1  decrypts the encrypted data in accordance with DTCP or the like. It then writes the decrypted data to the isochronous data area of the SRAM  40 . 
   Next, the DMAC 2  reads the isochronous data from the isochronous data area of the SRAM  40  and writes it to the SDRAM  50  (the second memory). During this time, the second encryption/decryption circuit ENC/DEC 2  encrypts the isochronous data that has been read from the SRAM  40 , in accordance with DES or the like. It then writes the encrypted data to the SDRAM  50 . 
   The performance of this encryption process makes it possible to maintain the confidentiality of the isochronous data (digital contents) that has been written to the SDRAM  50  in this manner, thus enabling the implementation of copyright protection. 
   The DMAC 3  then reads the encrypted isochronous data from the SDRAM  50  and transfers it to the BUS 2  side. The configuration is such that the isochronous data (TS packets) encrypted by DES in this manner are stored on the HDD  10 . 
   Note that the storage area of the SRAM  40  is preferably divided into an isochronous data area and an asynchronous data area, as shown in  FIG. 5B . 
   In such a case, the DMAC 1  selects a packet to be transferred from the BUS 1  side, writes the isochronous data to the isochronous data area, and writes the asynchronous data to the asynchronous data area. The DMAC 2  reads only the isochronous data that has been written to the isochronous data area, and writes it to the SDRAM  50 . 
   The storage area of the SRAM  40  could also be divided into an isochronous transmission data area, and isochronous reception data area, an asynchronous transmission data area, and an asynchronous reception data area, as shown in  FIG. 5C . Similarly, the storage area of the SDRAM  50  could be divided into an isochronous transmission data area and an isochronous reception data area. 
   In such a case, the DMAC 1  writes isochronous data to the isochronous data area and asynchronous data to the asynchronous data area. The DMAC 2  then reads the isochronous data from the SRAM  40  and writes it to the isochronous reception data area of the SDRAM  50 . The DMAC 3  reads the isochronous data from the isochronous reception data area of the SDRAM  50  and transfers it to the BUS 2  side. 
   During transmission, as shown in  FIG. 6A , the DMAC 3  writes isochronous data (TS packets) from the BUS 2  side (the HDD  10 ) to the SDRAM  50 . 
   The DMAC 2  then reads the isochronous data from the SDRAM  50  and writes it to the isochronous data area of the SRAM  40 . During this time, the second encryption/decryption circuit ENC/DEC 2  decrypts the encrypted data by DES. It then writes the decrypted data to the isochronous data area of the SRAM  40 . 
   The DMAC 1  then reads the isochronous data from the isochronous data area of the SRAM  40  and transfers it to the BUS 1  side. During this time, the first encryption/decryption circuit ENC/DEC 1  encrypts the isochronous data read from the SRAM  40  in accordance with DTCP or the like. It then transfers the encrypted data over BUS 1 . 
   The performance of this DTCP encryption process makes it possible to maintain the confidentiality of the isochronous data (digital contents) by IEEE 1394, thus enabling the implementation of copyright protection. 
   Note that if the storage area of the SRAM  40  is divided into an isochronous data area and an asynchronous data area, the data transfer could be done as shown in  FIG. 6B . If the storage areas of the SRAM  40  and the SDRAM  50  are divided into a transmission data area and a reception data area, the data transfer could be done as shown in  FIG. 6C . 
   If the isochronous data area and asynchronous data area are not separated for the transfer of AV data, it would be difficult to classify the AV data (AV stream) and AV commands (AV/C protocol commands). 
   Since the storage area of the SRAM  40  of this embodiment is divided into an isochronous data area and an asynchronous data area, as shown in  FIGS. 5B and 6B , it is simple to classify AV data and AV commands. This makes it possible to transfer only the AV data that has been received from the BUS 1  (IEEE 1394) side automatically to the BUS 2  (IDE) side, enabling the implementation of efficient AV data transfer that does not place any load on the processing section  60 . 
   With this embodiment, the storage areas of the SRAM  40  and the SDRAM  50  are divided into a transmission data area and a reception data area, as shown in  FIGS. 5C and 6C . This makes it possible to transmit and receive isochronous data independently. It is therefore possible to simultaneously guarantee the transfer rates for the transmission and reception of isochronous data. As a result, it is simple to implement time-shifted reproduction in which image data is read from the HDD  10  while other image data is being stored on the HDD  10 . 
   Note that if asynchronous data is stored on the HDD  10 , the data transfer could be as shown in  FIG. 7 . In other words, the data transfer path of the SDRAM  50  is bypassed so that asynchronous data is transferred directly between the DMAC 2  and DMAC 3 . 
   In such a case, the isochronous data can accumulate unchanged in the SDRAM  50 , waiting until the transfer of asynchronous data has ended. When the transfer of asynchronous data ends, the data transfer control device is reconnected to the SDRAM  50  on the outside. The isochronous data collected in the SDRAM  50  is transferred by the method described with reference to  FIGS. 5A to 6C , and the transfer could be restarted. 
   In general, asynchronous transfer is used when the HDD  10  is to be used as a personal computer (PC) file system. If AV data is to be stored in the HDD  10 , on the other hand, isochronous transfer is used. 
   As shown by this embodiment, the storage area of the SRAM  40  is divided into an isochronous data area and an asynchronous data area, and also the SDRAM  50  separates from the DMA transfer path during asynchronous transfer, so that both AV data and PC file data can be stored on the HDD  10 . In other words, when AV data that is isochronous data is being transferred, the data transfer could be done through the isochronous data area using the method shown in  FIGS. 5A to 6C . When PC file data that is asynchronous data is being transferred, on the other hand, the SDRAM  50  could separate from the DMA transfer path to transfer data through the asynchronous data area. 
   In this manner the user can be provided with a usage state in which it seems that both an HDD for AV data and an HDD for PC use are connected. 
   Detailed examples of the memory maps of the SRAM  40  and the SDRAM  50  as shown in  FIGS. 8A and 8B . 
     FIG. 8A  shows how the storage area of the SRAM  40  is divided into a header area, an asynchronous transmission data area, an asynchronous reception data area, an isochronous transmission data area, and an isochronous reception data area. Similarly,  FIG. 8B  shows how the storage area of the SDRAM  50  is divided into an isochronous transmission data area and an isochronous reception data area. Note that areas other than those shown in  FIGS. 8A and 8B  could be provided as the storage areas of the SRAM  40  and SDRAM  50 . 
   In  FIG. 8A , ATP 1  (BUS 1 -side asynchronous Tx pointer) is provided as a read pointer for the asynchronous transmission data area and ATP 2  (BUS 2 -side asynchronous Tx pointer) is provided as a write pointer therefor. 
   Similarly, ARP 1  (BUS 1 -side asynchronous Rx pointer) is provided as a write pointer for the asynchronous reception data area and ARP 2  (BUS 2 -side asynchronous Rx pointer) is provided as a read pointer therefor. 
   Furthermore, ITP 1  (BUS 1 -side isochronous Tx pointer) is provided as a read pointer for the isochronous transmission data area and ITP 2  (BUS 2 -side isochronous Tx pointer) is provided as a write pointer therefor. 
   In addition, IRP 1  (BUS 1 -side isochronous Rx pointer) is provided as a write pointer for the isochronous reception data area and IRP 2  (BUS 2 -side isochronous Rx pointer) is provided as a read pointer therefor. 
   These pointers are managed (set and updated) by the memory pointer management circuit  70  of  FIG. 3 . The use of these pointers makes it possible to implement efficient reading and writing of data. 
   Note that AV/C protocol commands are written to the asynchronous transmission data area of  FIG. 8A  during transmission, or written to the asynchronous reception data area during reception. These AV/C protocol commands are commands for controlling the AV device (reproduction and stop, etc.) and for enquiring about status. 
   The areas shown in  FIGS. 8A and 8B  are in a configuration called a ring buffer. In other words, information (data and headers) is stored from one boundary (start address) of each area to the other boundary (end address) thereof, and once that other boundary has been reached, information is stored again from that first boundary. 
   5. External Connection of SDRAM 
   With this embodiment, the SRAM  40  (first memory) is provided within the data transfer control device  30  (integrated circuit) and the SDRAM  50  (second memory) is provided outside of the data transfer control device  30  (IC), as shown in  FIGS. 9A and 9B . The SDRAM  50  is connected to external terminals of the data transfer control device  30 . 
   The configuration shown in  FIGS. 9A and 9B  makes it unnecessary to provide the SDRAM  50  within the IC of the data transfer control device  30 , thus enabling a reduction in the chip area of the IC. This makes it possible to use an inexpensive general-purpose SDRAM  50 , enabling reductions in the cost of the electronic instrument. 
   However, if the SDRAM  50  is provided on the outside, there is a danger of leaking of the confidentiality of the isochronous data. 
   With this embodiment of the present invention, the configuration is such that only data that has been encrypted by DES or the like (a second encryption process) is input or output through the external terminals of the data transfer control device  30 . 
   Specifically, during reception, as shown by way of example in  FIG. 9A , the DMAC 2  reads data from the SRAM  40  (the BUS 1  side) and the ENC/DEC 2  encrypts the thus-read data by DES (generally speaking: a second encryption process). The DMAC 2  writes the encrypted data to the SDRAM  50  through the external terminals (data terminals) of the data transfer control device  30 . 
   The DMAC 3  then reads the encrypted data that has been written to the SDRAM  50  through the external terminals of the data transfer control device  30 , and transfers the thus-read encrypted data to the BUS 2  side to which the HDD  10  (storage medium) or the like is connected. 
   During transmission, on the other hand, the DMAC 3  reads data that has been encrypt by DES from the HDD  10  through the BUS 2 , as shown in  FIG. 9B . The data is written to the SDRAM  50  through the external terminals of the data transfer control device  30 . 
   The DMAC 2  reads the encrypted data that has been written to the SDRAM  50  through the external terminals of the data transfer control device  30 , and the ENC/DEC 2  uses the DES decryption process to decrypt the thus-read encrypted data. The DMAC 2  writes the decrypted data to the SRAM  40  (transfer to the BUS 1  side) The DMAC 2  writes the decrypted data to the SRAM  40  (transfer to the BUS 1  side). 
   Note that the ENC/DEC 1  decrypts the data that has been encrypted by IEEE 1394 DTCP (generally speaking: a first encryption process) during reception, as shown in  FIG. 9A . The DMAC 1  writes the decrypted data to the DMAC 1 . 
   During the transmission of  FIG. 9B , on the other hand, the DMAC 1  reads data from the SRAM  40  and the ENC/DEC 1  encrypts the thus-read data. The DMAC 1  then transfers the encrypted data to the DMAC 1 . 
   In the above described manner, only encrypted data is input or output through the external terminals (data terminals) of the data transfer control device  30 . This maintains the confidentiality of the data and enables the implementation of copyright protection for the data contents. 
   Data confidentiality can be further increased by storing only encrypted data in the SDRAM  50 . 
   The provision of the ENC/DEC 1  and ENC/DEC 2  as shown in  FIGS. 9A and 9B  ensures that the SRAM  40  always stores only decrypted data. This makes it possible for the processing section  60  to use the SRAM  40  for packet processing (packet analysis and packet preparation). 
   Note that encryption might not be necessary, depending on the data contents. For example, if the contents are distributed as analog data, in some cases copyright protection will not be required, so encryption is not necessary. 
   There is a danger that the execution of encryption/decryption processing will reduce the transfer speed by an equivalent amount. 
   With this embodiment, paths are provided for bypassing encryption/decryption processing. 
   More specifically, during the reception shown in  FIG. 9A , the DMAC 2  (second memory access control circuit) uses a bypass path  62  to bypass the DES encryption process (second encryption process) for data for which encryption is not necessary. Data that has been read from the SRAM  40  (data on the BUS 1  side) is written directly to the SDRAM  50  without passing through the ENC/DEC 2 , by way of example. 
   During the transmission shown in  FIG. 9B , on the other hand, the DMAC 2  uses the bypass path  62  to bypass the DES decryption process (second decryption process) when decryption is not necessary. Data read from the SDRAM  50  is written directly to the SRAM  40  without passing through the ENC/DEC 2  (transfer to the BUS 1  side). 
   This makes it possible to do without unnecessary encryption and decryption processing for data (contents) that do not require copyright protection. As a result, the effective transfer rate of the data transfer can be increased. 
   Note that a configuration in which the SRAM  40  (internal memory) is not provided as shown in  FIGS. 10A and 10B  could be used when encrypted data is input or output with respect to the SDRAM  50  (external memory) through the external terminals of the data transfer control device  30 . 
   For example, during reception as shown in  FIG. 10A , the ENC/DEC 2  comprised within the DMAC 2  encrypts data transferred from the BUS 1  side (the 1394 interface  31 ) by DES (second encryption process). The DMAC 2  writes the thus-encrypted data to the SDRAM  50 . The DMAC 3  reads the encrypted data from the SDRAM  50  and transfers it to the BUS 2  side (the IDE interface  34 ). 
   During transmission as shown in  FIG. 10B , the DMAC 3  writes encrypted data transferred from the BUS 2  side (the IDE interface  34 ) to the SDRAM  50 . The DMAC 2  reads the encrypted data from the SDRAM  50  and the ENC/DEC 2  decrypts the thus-read data. The DMAC 2  transfers the decrypted data to the BUS 1  side (the 1394 interface  31 ). 
   Note that DTCP encryption/decryption processing could be done by the ENC/DEC 2  or by the 1394 interface  31 . 
   6. Detailed Configurational Example 
   An example of details of the configuration and connections of the DMAC 2 , the SDRAM interface  52 , and the DMAC 3  is shown in  FIGS. 11 and 12 . 
   The meanings of the various signals used in  FIGS. 11 and 12  are shown in  FIGS. 13A ,  13 B, and  13 C. Note that IdeReq 2  in  FIG. 11  is an access (read or write) signal from the DMAC 2  to the SRAM  40  and IdeAck 2  is an access acknowledgement signal. Similarly, HostReq 3  is an access request signal from the DMAC 3  to the IDE side and HostAck 3  is an access acknowledgement signal. DMAGO is an automatic DMA start signal. 
   As shown in  FIG. 11 , the DMAC 2  comprises a FIFO 1 , the ENC/DEC 2 , and a FIFO 2 . During reception, data that has been read from the SRAM  40  through the SRAM interface  42  accumulates temporarily in the FIFO 1 . The FIFO 1  outputs that data to the ENC/DEC 2 . The ENC/DEC 2  encrypts the data and the encrypted data accumulates in the FIFO 2 . The FIFO 2  sends the accumulated data to the SDRAM  50 . 
   During transmission, on the other hand, data that has been read from the SDRAM  50  through the SDRAM interface  52  is accumulates temporarily in the FIFO 2 . The FIFO 2  outputs that data to the ENC/DEC 2 . The ENC/DEC 2  decrypts the data and the decrypted data accumulates in the FIFO 1 . The FIFO 1  sends the accumulated data to the SRAM  40 . 
   Note that if encryption is not performed on the data, the data read from the SRAM  40  is sent directly to the SDRAM  50  through the bypass path  62 . Similarly, if decryption is not performed on the data, the data read from the SDRAM  50  is sent directly to the SRAM  40  through the bypass path  62 . 
   The DMAC 2  starts DMA when the automatic DMA start signal from the memory pointer management circuit  70  (the automatic DMA determination circuit  72 ) becomes active. 
   The DMAC 3  comprises a FIFO 3 , as shown in  FIG. 11 . During reception, the data read from the SDRAM  50  accumulates temporarily in the FIFO 3  before being sent to the IDE side. During transmission, on the other hand, the data from the IDE side accumulates temporarily in the FIFO 3  before being sent to the SDRAM  50 . 
   Note that a bypass path  64  is a bypass path for when the ENC/DEC 2  and SDRAM  50  are not used. If the encryption process of the SDRAM  50  is not necessary, this bypass path  64  is selected for the data transfer. A bypass path  66  is a bypass path for when the SDRAM  50  is not used. If the SDRAM  50  is not required (during asynchronous data transfer, for example) this bypass path  66  is selected for the data transfer. 
   The data transfer control device  30  and the SDRAM  50  use a synchronization clock signal RAMCLK, control signals CKE, XCS, XRAS, XCAS, XWE, UDQM, and LDQM, and an address signal Address to transfer data Data, as shown in  FIG. 12 . Note that the meanings of these signals are shown in  FIG. 13A . 
   Specifically, the data transfer control device  30  uses the control signals (on the memory bus) to set various operating modes (commands) in the SDRAM  50  and start addresses. When that happens, the SDRAM  50  inputs or outputs data (burst data) sequentially from the start address, in synchronization with RAMCLK. In other words, the SDRAM  50  generates addresses automatically within itself, and accesses internal memory blocks based on the thus-generated addresses. Note that in this case the RAMCLK could also be a high-speed clock signal that is generated internally, for accessing internal memory blocks. 
   Timing waveforms in  FIGS. 14A and 14B  are examples of the write data WrData, write acknowledgement signal WrAck, write request signal WrReq, read data RdData, read acknowledgement signal RdAck, and read request signal RdReq of  FIGS. 13B and 13C . 
   7. Operation of Data Transfer Control Device 
   The description now turns to the operation of the data transfer control device of this embodiment, with reference to the flowcharts of  FIGS. 15 ,  16 , and  17 . 
     FIG. 15  is a flowchart of the operation during reception. 
   First of all, the transfer processing starts unconditionally at the reception of an isochronous packet (step S 1 ). The data of the received isochronous packet is written to the isochronous reception-data area of the SRAM (step S 2 ). 
   The system then determines whether or not the quantity of reception data that has been written to SRAM exceed an automatic DMA transfer unit ATU (step S 3 ). If it does exceed it, the automatic DMA transfer unit ATU is set in the number of remaining transfers RTN and the DMAC 2  is activated (step S 4 ). More specifically, the automatic DMA start signal DMAGO of  FIG. 11  goes active. 
   The system then determines whether or not the SDRAM storage area is full (step S 5 ). If it is full, the transfer waits (step S 6 ) until there is space in the SDRAM. 
   If it is not full (if there is space therein), on the other hand, one word of data is read from the SRAM (step S 7 ). The thus-read data is encrypted and written to the SDRAM (steps S 8  and S 9 ). 
   The number of remaining transfers RTN is decremented by one (step S 10 ). The system then determines whether or not RTN is zero (step S 11 ) and the flow returns to step S 5  if RTN is not zero or to step S 2  if RTN is zero. 
   The above described procedure ensures that data that has been received over BUS 1  (IEEE 1394) is written to the SDRAM through the SRAM. 
     FIGS. 16 and 17  are flowcharts of the operation during transmission. 
   First of all, the total number of transfers ATN is set in the number of remaining transfers RTN and the DMAC 3  is activated (step S 21 ). 
   The system then determines whether or not the SDRAM storage area is full (step S 22 ) and, if it is full, the transfer waits (step S 23 ) until there is space. If it is not full (if there is space therein), one word of data is transferred (step S 24 ). 
   The number of remaining transfers RTN is then decremented by one (step S 25 ). The system then determines whether or not RTN is zero (step S 26 ) and, if RTN is not zero, the flow returns to step S 22  and processing ends when RTN does reach zero. 
   The above described procedure ensures that data from the BUS 2  (IDE) side is written to SDRAM. 
   The total number of transfers ATN (for M isochronous packets) is then set in the number of remaining transfers RTN and the DMAC 2  is activated (step S 31 ), as shown in  FIG. 17 . 
   The system then determines whether or not the SDRAM storage area is empty (step S 32 ) and, if it is empty, the transfer waits (step S 33 ) until data has filled the SDRAM. If the SDRAM is not empty (if it is full of data), on the other hand, the system determines whether or not the SRAM storage area is full (step S 34 ). If it is full, the transfer waits (step S 35 ) until the there is space in the SRAM. 
   If the SRAM storage area is not full (if there is space therein), one word of data is read from the SDRAM (step S 36 ). If it is copyright-protected data, the thus-read data is decrypted (step S 37 ), and the decrypted data is written to the SRAM (step S 38 ). 
   The number of remaining transfers RTN is then decremented by one (step S 39 ). The system then determines whether or not RTN is zero (step S 40 ) and, if RTN is not zero, the flow returns to step S 32  and processing ends when RTN does reach zero. 
   In the above-described manner, data that has been written to SDRAM is written to SRAM. 
   8. Application to USB 
   An example of the configuration of the data transfer control device that is shown in  FIG. 18  concerns the application of the method of this embodiment to USB (such as USB 2.0). 
   The configuration of  FIG. 18  differs from that of  FIG. 3  in the points described below. 
   That is to say,  FIG. 18  is provided with a USB interface  131  instead of the 1394 interface  31  of  FIG. 3 . In addition, the DMAC 1  also has the function of an end point management circuit in  FIG. 18 . Furthermore, a bulk transfer management circuit  174  is provided in  FIG. 18 . In all other points, this configuration is substantially the same as that of  FIG. 3 . 
   In  FIG. 18 , a transceiver macro  132  comprised by the USB interface  131  is a circuit for implementing data transfer in USB FS mode or HS mode. A transceiver macrocell that conforms to the USB 2.0 Transceiver Macrocell Interface (UTMI), which defines physical-layer circuitry and some logical-layer circuitry for USB 2.0, could be used as the transceiver macro  132 . This transceiver macro  132  comprises an analog front-end circuit for transmitting data over USB by using a difference signal, and it could also comprise circuitry for processing such as bit stuffing, bit unstuffing, serial-to-parallel conversion, parallel-to-serial conversion, NRZI decoding, NRZI encoding, and sampling clock generation. 
   A serial interface engine (SIE) comprised by the USB interface  131  is circuitry for performing various processes such as USB packet transfer processing. This SIE can comprise circuitry for managing transactions, circuitry for assembling (creating) and disassembling packets, and circuitry for creating or reading CRCs. 
   Circuits such as the DMAC 1 , DMAC 2 , and DMAC 3  of  FIG. 18  implement processing that is similar to that of the circuits described with reference to  FIG. 3 , etc. 
   Note that the DMAC 1  also has the function of managing the end points that form entrances to the storage areas of an SDRAM  140 . Specifically, the DMAC 1  comprises a register for storing end point attribute information. 
   The bulk transfer management circuit  174  is a circuit for managing bulk transfers by USB. 
   9. Encryption/Decryption Circuits 
   The description now turns to the encryption and decryption circuits using the ENC/DEC 2  of  FIG. 3  for DES (generally speaking: a common-key encryption method). 
   A functional block diagram of the encryption circuit that performs DES (SDES) encryption is shown in  FIG. 19 . This encrypt circuit comprises an encryption section  200  and a key generation processing section  202 . 
   In this case, the encryption section  200  repeats 16 stages of non-linear conversion and permutation processing on 64 bits of input data (plain text) that correspond to one data block, and outputs converted data (encrypted text). The key generation processing section  202  creates 48-bit (sub-) keys K 1  to K 16  that are used by the processing at each stage by the encryption section  200 , based on a 64-bit common secret key. 
   A flowchart illustrative of the processing of the encryption section  200  is shown in  FIG. 20 . 
   If 64 bits of input data M is input as one data block unit to the encryption section  200 , an initial permutation (IP) is performed on that input data M to randomize it (step S 41 ). The initial permutation is processing that converts the bits positions to be output, corresponding to the input bit positions, and outputs them. For example, the 58th input bit is transposed to the first bit of the output, and the first bit of the input is transposed to the 40th bit of the output. 
   Initial permutation data obtained by the initial permutation is divided into bits, the high-order 32 bits are set in input data L 0  of the first stage and the low-order 32 bits are set in input data R 0  of the first stage (steps S 42  and S 43 ). 
   The first-stage input data R 0  is then converted into non-linear conversion data f (R 0 , K 1 ) by a non-linear conversion f using the first-stage key K 1  (step S 50 - 1 ). An exclusive OR is taken between the thus-obtained non-linear conversion data f (R 0 , K 1 ) and the first-stage input data L 0  (step S 51 - 1 ). This computational result is set into second-stage input data R 1  (step S 52 - 1 ). 
   The first-stage input data R 0  is set into second-stage input data L 1  (step S 53 - 1 ). 
   If the processing up to the above-described creation of the second-stage input data L 1  and R 1  from the first-stage input data L 0  and R 0  is assumed to be first-stage processing of the DES encryption process (a given computation), similar processing is performed for up until the sixteenth stage. The key applied at each stage is changed for the non-linear conversion at each stage. 
   As a result, the sixteenth stage of input data L 16  and R 16  created by the sixteenth stage are as follows (steps S 53 - 16  and S 52 - 16 ):
 
L16=R15  (1)
 
 R 16 =L 15 (+)  f ( R 15,  K 16)  (2)
 
In this case, (+) represents an exclusive OR.
 
   Finally, the high-order 32 bits and low-order 32 bits are switched. In other words, substitution data L 16 ′ is set in the sixteenth stage of input data R 16  (step S 54 ), substitution data R 16 ′ is set in the sixteenth stage of input data L 16  (step S 55 ), and a final permutation (IP- 1 ) is performed as 64-bit data (step S 56 ). 
   The final permutation (IP- 1 ) is data substituted into the bit position by the initial permutation, and the flow returns to the start. For example, the first bit of the input is transposed to the 58th bit of the output and the 40th bit of the input is transposed to the first bit of the output. 
   Converted data P is created by the above process. 
   A functional block diagram of the decryption circuit that performs DES (SDES) decryption is shown in  FIG. 20 . This decryption circuit comprises a decryption section  210  and a key generation processing section  212 . 
   In this case, the decryption section  210  repeats 16 stages of non-linear conversion and permutation processing on 64 bits of input data (encrypted text) that correspond to one data block, and outputs converted data (plain text). The key generation processing section  212  creates 48-bit (sub-) keys K 1  to K 16  that are used by the processing at each stage by the decryption section  210 , based on a 64-bit common secret key. 
   The processing of the decryption section  210  can be implemented by reversing the sequence of the processing of the encryption section  200  described with reference to  FIGS. 19 and 20 . In this case, the key at each stage of the decryption section  210  is applied in the reverse order of the keys for the encryption process: K 16 , K 15 , . . . , K 1 . 
   The key generation processing of the key generation processing section  212  is implemented by converting the left-shift of the key generation processing section  202  of  FIG. 19  into a right-shift. The key generation processing section  212  generates the keys K 16 , K 15 , . . . , K 1  for each stage. 
   In this way, the processing details at each stage of the decryption process are in common with the processing details at each stage of the encryption process. In the second encryption/decryption circuit ENC/DEC 2  of this embodiment as shown in  FIG. 3 , the same circuitry is used for the encryption and decryption processes in common. 
   Note that the plain text or encrypted text that is the input data for DES (SDES) is divided into a plurality of blocks and the encryption or decryption processing is performed in block data units. There is therefore a possibility that the converted data will be the same if the block data is the same, and it will become easy to specify the key. For that reason, embodiments of the present invention utilize various encryption modes such as a cipher block chaining (CBC) mode or a cipher feedback (CFB) mode. 
   The second encryption/decryption circuit ENC/DEC 2  of embodiments of the present invention can implement pipelining of the processing for 16 stages of DES, by employing two DES computation circuits of the same configuration. Embodiments of the present invention can also implement encryption or decryption by TDES, by forming a plurality of loops of DES (SDES) processing, using the above described pipelining. Such a configuration makes it possible to implement encryption and decryption by TDES, without causing any increase in the circuit scale. 
   Note that the present invention is not limited to these embodiments described above, and thus various modifications thereto are possible within the scope of the present invention laid out herein. 
   For example, terminology (such as: SRAM, SDRAM, SRAM interface, SDRAM interface, IEEE 1394 or USB bus, IDE bus, 1394 interface, IDE interface, DMAC 1 , DMAC 2 , DMAC 3 , HDD, DTCP, and DES) that is derived from generic terminology defined within this document (such as: first memory, second memory, first memory interface, second memory interface, first bus, second bus, first bus interface, second bus interface, first memory access control circuit, second memory access control circuit, third memory access control circuit, storage medium, first encryption/decryption processing, and second encryption/decryption processing) could be replaced by other terminology used within this document. 
   Some of the requirements of the dependent claims of the present invention may be omitted. Some of requirements of any one of the independent claims of the present invention can be made to depend on any other independent claims of the present invention. 
   The configuration of the data transfer control device of the present invention is not limited to those shown in  FIGS. 3 ,  9 A to  12 , and  18 , and thus various modifications thereto are possible. For example, some of the various blocks and units in these figures can be omitted, and the connective relationships therebetween can be modified. 
   The present invention can also be applied to data transfer in accordance with bus standards that are based on a similar concept to that of IEEE 1394 or USB, or standards that are developed from IEEE 1394 or USB. Alternatively, the present invention can be applied to transfer over a bus (high-speed serial bus) conforming to a standard other than IEEE 1394 or USB.