Patent Publication Number: US-2023154896-A1

Title: 3D Package Structure and Methods of Forming Same

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is a continuation of U.S. patent application Ser. No. 17/113,676, filed Dec. 7, 2020, and entitled “3D Package Structure and Methods of Forming Same,” which is a continuation of U.S. patent application Ser. No. 16/397,479, filed Apr. 29, 2019, and entitled “3D Package Structure and Methods of Forming Same,” now U.S. Pat. No. 10,861,827, issued on Dec. 8, 2020, which is a divisional of U.S. patent application Ser. No. 14/755,798, filed Jun. 30, 2015, and entitled “3D Package Structure and Methods of Forming Same,” now U.S. Pat. No. 10,276,541 issued on Apr. 30, 2019, which applications are incorporated herein by reference. 
    
    
     BACKGROUND 
     Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic equipment, as examples. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductive layers of material over a semiconductor substrate, and patterning the various material layers using lithography to form circuit components and elements thereon. Dozens or hundreds of integrated circuits are typically manufactured on a single semiconductor wafer. The individual dies are singulated by sawing the integrated circuits along a scribe line. The individual dies are then packaged separately, in multi-chip modules, or in other types of packaging, for example. 
     The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continual reductions in minimum feature size, which allow more components to be integrated into a given area. These smaller electronic components such as integrated circuit dies may also require smaller packages that utilize less area than packages of the past, in some applications. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. 
         FIGS.  1  through  18    are various intermediate structures in forming a package structure in accordance with some embodiments. 
         FIGS.  19  through  22    are various intermediate structures in forming a package structure in accordance with some embodiments. 
         FIGS.  23  through  33    are various intermediate structures in forming a package structure in accordance with some embodiments. 
         FIG.  34    is a package structure in accordance with some embodiments. 
     
    
    
     DETAILED DESCRIPTION 
     The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. 
     Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature&#39;s relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. 
     Embodiments will be described with respect to embodiments in a specific context, namely a three dimensional (3D) integrated fan-out (InFO) package device. Other embodiments may also be applied, however, to other electrically connected components, including, but not limited to, package-on-package assemblies, die-to-die assemblies, wafer-to-wafer assemblies, die-to-substrate assemblies, in assembling packaging, in processing substrates, interposers, substrates, or the like, or mounting input components, boards, dies or other components, or for connection packaging or mounting combinations of any type of integrated circuit or electrical component. 
       FIGS.  1  through  18    are various intermediate structures in forming a package structure in accordance with some embodiments.  FIG.  1    illustrates an intermediate step in the formation of a package structure including a carrier substrate  30 , an adhesive layer  32  over a carrier substrate  30 , and an adhesive layer  34  over the adhesive layer  32 . The carrier substrate  30  may be any suitable substrate that provides (during intermediary operations of the fabrication process) mechanical support for the layers over the carrier substrate  30 . The carrier substrate  30  may be a wafer including glass, silicon (e.g., a silicon wafer), silicon oxide, metal plate, a ceramic material, or the like. 
     The adhesive layer  32  may be disposed, for example laminated, on the carrier substrate  30 . The adhesive layer  32  may be formed of a glue, such as an ultra-violet (UV) glue which loses its adhesive property when exposed to UV lights, a light-to-heat conversion (LTHC) material which loses its adhesive property when heated, or the like. The adhesive layer  32  may be dispensed as a liquid and cured, may be a laminate film laminated onto the carrier substrate  30 , or may be the like. The top surface of the adhesive layer  32  may be leveled and may have a high degree of coplanarity. 
     The adhesive layer  34  may be disposed, for example laminated, on the adhesive layer  32 . The adhesive layer  34  may be any suitable adhesive, such as a die attach film, such as any suitable adhesive, epoxy, UV glue, or the like. 
       FIG.  2    illustrates the adhering of dies  36  ( 36 A and  36 B) to the carrier substrate  30  and the adhesive layer  32  by the adhesive layer  34 . The dies  36  include, pads  38  (such as an electrical connector pad), and a passivation layer  40  on an active side of the dies  36 . The dies  36  may be, for example, logic integrated circuits, memory dies, analog dies, any other dies, or a combination thereof. The dies  36  may include a semiconductor substrate, such as a bulk semiconductor substrate, semiconductor-on-insulator substrate, or the like, on which active devices, such as transistors, and/or passive devices, such as capacitors, inductors, or the like, are formed according to semiconductor processes. Metallization layers, including a top metallization layer (not shown), may be on the semiconductor substrate and may include interconnect structures to electrically couple devices together and/or to pads  38 . The pads  38  are exposed through respective openings in the passivation layer  40 . 
     In an example, the dies  36  may be formed as part of a wafer. The wafer is singulated, such as by dicing or sawing, to form individual dies  36 . The dies  36  are placed on the carrier substrate  30  using, for example, a pick-and-place tool. The pads  38  and passivation layer  40  are placed opposite from the carrier substrate  30 . 
       FIG.  3    illustrates the encapsulation of the dies  36 . In some embodiments, the dies  36  are encapsulated by a molding material  42 . In some embodiments, the molding material includes filler material  44  throughout the molding material. The molding material  42  may be molded on the dies  36 , for example, using compression molding. In some embodiments, the molding material  42  is made of a molding compound, a polymer, an epoxy, the like, or a combination thereof. The filler material  44  in the molding material  42  may be silicon oxide filler material or the like. A curing step may be performed to cure the molding material  42 , wherein the curing may be a thermal curing, a UV curing, the like, or a combination thereof. 
     In some embodiments, the dies  36  are buried in the molding material  42 , and after the curing of the molding material  42 , a planarization step, such as a grinding, is performed on the molding material  42  as illustrated in  FIG.  3   . The planarization step is used to remove excess portions of the molding material  42 , which excess portions are over top surfaces of the passivation layers  40  of the dies  36 . In some embodiments, surfaces of the passivation layers  40  and the pads  38  are exposed, and the surfaces of the passivation layers  40  are level with a surface of the molding material  42 . The molding material  42  may be described as laterally encapsulating the dies  36 . 
       FIG.  4    illustrates the formation of a dielectric material  46  over the active sides of the dies  36 , such as on the passivation layers  40 . The dielectric material  46  may continuously cover the dies  36  and the molding material  42  and may cover the pads  38 . The dielectric material  46  may be a polymer, such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), or the like. In other embodiments, the dielectric material  46  is formed of a nitride such as silicon nitride; an oxide such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), or the like; or the like. In some embodiments, the dielectric material  46  is a partially cured polymer that is applied as a dry film with a laminating process. In an embodiment, the dielectric material  46  is less than 50 percent cured when applied and may be subsequently cured. In some embodiments, the degree of curing of the dielectric material  46  is directly related to the amount of cross-linking in the dielectric material  46 . The dielectric material  46  may be formed by any acceptable deposition process, such as spin coating, chemical vapor deposition (CVD), laminating, the like, or a combination thereof. 
     In some embodiments, the dielectric material  46  has an uneven top surface, and a planarization step, such as a grinding, is performed on the dielectric material  46 . The planarization step is used to provide a planar top surface for the dielectric material  46 . 
       FIG.  5    illustrates the formation of openings  47  through the dielectric material  46  and the passivation layers  40  (if openings not already formed through the passivation layers  40 ) to expose portions of the pads  38 . The openings  47  may be referred to as via openings. The openings  47  may be formed by, for example, etching, milling, laser techniques, the like, or a combination thereof. 
       FIG.  6    illustrates the formation of conductive patterns  48  ( 48 A,  48 B, and  48 C) over the dielectric material  46  and in the openings  47  to the pads  38 . The conductive patterns  48  include various traces and/or vias, such as vias in the openings  47 . The conductive patterns  48  may be referred to as a redistribution layer  48 . The conductive patterns  48 , in an example, include a metal such as copper, titanium, the like, or a combination thereof, formed by a plating process, such as electroless plating, electroplating, or the like. For example, a seed layer (not shown) is deposited over the dielectric material  46  and in the openings  47 . The seed layer can be copper, titanium, the like, or a combination thereof deposited by atomic layer deposition (ALD), sputtering, another physical vapor deposition (PVD) process, or the like. A photoresist is deposited and patterned exposing the pattern for the conductive patterns  48  that is desired, such as by an acceptable photolithography technique. A conductive material, such as copper, aluminum, the like, or a combination thereof, is deposited on the seed layer by electroless plating, electroplating, or the like. The photoresist is removed, such as an appropriate photoresist stripping process. Remaining exposed seed layer portions are removed, such as by a wet or dry etch. 
     Although only one layer of vias, one dielectric material  46 , and one layer of conductive patterns  48  are illustrated in the embodiment, there may be more than the one layer of vias, dielectric material  46 , and layer of conductive patterns  48  to form the redistribution layer  48  in some other embodiments. For example, in one embodiment, the process for forming the dielectric material  46 , vias, and conductive patterns  48  may be repeated two more times to form a redistribution layer with three layers of conductive material and three dielectric material layers. 
       FIG.  7    illustrates the adhering of die  52  to the dielectric material  46  (and possibly one or more of the conductive patterns  48 ) by an adhesive layer  50 . The die  52  include, pads  54  (such as an electrical connector pad), and a passivation layer  56  on an active side of the die  52 . The die  52  may be, for example, logic integrated circuits, memory dies, analog dies, any other dies, or a combination thereof. The die  52  may include a semiconductor substrate, such as a bulk semiconductor substrate, semiconductor-on-insulator substrate, or the like, on which active devices, such as transistors, and/or passive devices, such as capacitors, inductors, or the like, are formed according to semiconductor processes. Metallization layers, including a top metallization layer (not shown), may be on the semiconductor substrate and may include interconnect structures to electrically couple devices together and/or to pads  54 . The pads  54  may be exposed through respective openings in the passivation layer  56 . 
     In an example, the die  52  may be formed as part of a wafer. The wafer is singulated, such as by dicing or sawing, to form individual dies  52 . The die  52  is placed on the dielectric material  46  (and possibly one or more of the conductive patterns  48 ) using, for example, a pick-and-place tool. The pads  54  and passivation layer  56  are placed opposite from the dielectric material  46 . 
       FIG.  8    illustrates the formation of a dielectric material  58  over the conductive patterns  48 , the dielectric material  46 , and the die  52 . The dielectric material  58  laterally encapsulates the die  52 . As shown, the dielectric material  58  continuously extends from a region disposed laterally from the die  52  to a region disposed directly above the die  52 . For example, there is no vertical interface (where vertical, as shown, is in a direction perpendicular to a top surface of the die  52 ) with a different dielectric material near a lateral edge of the die  52 , e.g., not directly over pad  54  of the die  52 . The dielectric material  58  may be a polymer, such as PBO, polyimide, BCB, or the like. In other embodiments, the dielectric material  58  is formed of a nitride such as silicon nitride; an oxide such as silicon oxide, PSG, BSG, BPSG, or the like; or the like. In some embodiments, the dielectric material  58  is a partially cured polymer that is applied as a dry film with a laminating process. In an embodiment, the dielectric material  58  is less than 50 percent cured when applied and may be subsequently cured. In some embodiments, the degree of curing of the dielectric material  58  is directly related to the amount of cross-linking in the dielectric material  58 . The dielectric material  58  may be formed by any acceptable deposition process, such as spin coating, CVD, laminating, the like, or a combination thereof. 
     In some embodiments, the dielectric material  58  has an uneven top surface, and a planarization step, such as a grinding, is performed on the dielectric material  58 . The planarization step is used to provide a planar top surface for the dielectric material  58 . 
     The dies  36  and the molding material  42  may be referred to as a first layer of the structure and the die  52  and the dielectric material  58  may be referred to as an Nth layer, or in this case the second layer. Although only two layers are illustrated in the embodiment, there may be more or less than two layers in the structure. For example, in one embodiment, the  2 ′ layer (illustrated as N th ) may be repeated two more times to give a total of four layers (i.e. N=4). In another example, only one layer may be in the structure and it may be a structure similar to the Nth layer structure. 
       FIG.  9    illustrates the formation of openings  60  through the dielectric material  58  and the passivation layer  56  (if openings not already formed through passivation layer  56 ) to expose portions of the pads  54 . The openings  60  may be referred to as via openings  60 . The openings  60  may be formed by, for example, etching, milling, laser techniques, the like, or a combination thereof. 
       FIG.  10    illustrates the formation through openings  62  through the dielectric material  58  to expose portions of the conductive patterns  48 . The openings  62  may be formed by, for example, etching, milling, laser techniques, the like, or a combination thereof. 
       FIG.  11    illustrates the formation of seed layer  64  and conductive material  66  over the dielectric material  58  and in the openings  60  and  62  to the pads  54  and conductive patterns  48 , respectively. The conductive material  66  includes via portions  66 A and  66 B in the openings  62  and  60 , respectively. The seed layer  64  may be deposited over the dielectric material  58  and in the openings  60  and  62 . The seed layer  64  can be copper, titanium, the like, or a combination thereof deposited by ALD, sputtering, another PVD process, or the like. The conductive material  66 , in an example, includes a metal such as copper, titanium, the like, or a combination thereof, formed by a plating process, such as electroless plating, electroplating, or the like. The via portions  66 A may be referred to as through package vias (TPVs) and/or through InFO vias (TIVs) and will be referred to as TIVs  66 A hereinafter. 
     In some embodiments, the conductive material  66  has an uneven top surface, and a planarization step, such as a grinding, is performed on the conductive material  66  as illustrated in  FIG.  12   . The planarization step is used to provide a planar top surface for the conductive material  66 . 
       FIG.  13    illustrates the patterning of the conductive material  66  to form conductive patterns  68  ( 68 A,  68 B, and  68 C), the formation of a dielectric layer  70 , and the formation of openings  72  through the dielectric layer  70 . The conductive material  66  can be patterned with any acceptable photolithography technique. In one example, a photoresist is deposited and patterned exposing the pattern for the conductive patterns  68  that is desired, such as by an acceptable photolithography technique. The exposed conductive material  66  is then removed with an acceptable etch process to form the separate conductive patterns  68 . The conductive patterns  68  may be referred to as a redistribution layer  68 . The photoresist is removed, such as an appropriate photoresist stripping process. Remaining exposed seed layer portions are removed, such as by a wet or dry etch. The conductive patterns  68 A and  68 C each include at least one TIV  66 A. 
     The dielectric layer  70  covers the conductive patterns  68 . The dielectric layer  70  may be a polymer, such as PBO, polyimide, BCB, or the like. In other embodiments, the dielectric layer  70  is formed of a nitride such as silicon nitride; an oxide such as silicon oxide, PSG, BSG, BPSG, or the like; or the like. The dielectric layer  70  may be formed by any acceptable deposition process, such as spin coating, CVD, laminating, the like, or a combination thereof. The openings  72  may be formed through the dielectric layer  70  to expose portions of the conductive patterns  68  by, for example, etching, milling, laser techniques, the like, or a combination thereof. 
     Although only one layer of vias  66 B, one dielectric layer  70 , and one layer of conductive patterns  68  are illustrated in the embodiment, there may be more than the one layer of vias  66 B, dielectric layer  70 , and layer of conductive patterns  69  to form the redistribution layer  68  in some other embodiments. For example, in one embodiment, the process for forming the dielectric layer  70 , vias  66 B, and conductive patterns  68  may be repeated two more times to form a redistribution layer  68  with three layers of conductive material and three dielectric layers. 
       FIG.  14    further illustrates the formation of a set of conductive connectors  74  over and electrically coupled to the conductive patterns  68  through the openings  72 . The conductive connectors  74  may be solder bumps, metal pillars, controlled collapse chip connection (C4) bumps, micro bumps, electroless nickel-electroless palladium-immersion gold technique (ENEPIG) formed bumps, or the like. The conductive connectors  74  may include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or a combination thereof. In an embodiment in which the conductive connectors  74  are solder bumps, the conductive connectors  74  are formed by initially forming a layer of solder through such commonly used methods such as evaporation, electroplating, printing, solder transfer, ball placement, or the like. Once a layer of solder has been formed on the structure, a reflow may be performed in order to shape the material into the desired bump shapes. In another embodiment, the conductive connectors  74  are metal pillars (such as a copper pillar) formed by a sputtering, printing, electro plating, electroless plating, CVD, or the like. The metal pillars may be solder free and have substantially vertical sidewalls. In some embodiments, a metal cap layer (not shown) is formed on the top of the metal pillar connectors  74 . The metal cap layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, the like, or a combination thereof and may be formed by a plating process. 
     Although not shown, there may be underbump mettalizations (UBMs) coupled to the redistribution layer  68  with the conductive connectors  74  coupled to the UBMs (not shown). The UBMs may extend through the openings  72  in the dielectric layer  70  and also extend along a surface of dielectric layer  70 . The UBMs may include three layers of conductive materials, such as a layer of titanium, a layer of copper, and a layer of nickel. However, one of ordinary skill in the art will recognize that there are many suitable arrangements of materials and layers, such as an arrangement of chrome/chrome-copper alloy/copper/gold, an arrangement of titanium/titanium tungsten/copper, or an arrangement of copper/nickel/gold, that are suitable for the formation of the UBMs. Any suitable materials or layers of material that may be used for the UBMs are fully intended to be included within the scope of the current application. 
       FIG.  15    illustrates that there may be several regions  100  that include the structure that has been previously described in  FIGS.  1  through  14    laterally adjoining each other. These regions  100  including their respective structures may be formed on the carrier substrate  30 . 
       FIG.  16    illustrates a singulation process for singulating the regions  100  into separate structures. Before the singulation process, the carrier substrate  30  and the adhesive layer  32  are removed to expose the adhesive layer  34  according to an embodiment. In this embodiment, the structures are placed on a frame  80  with the conductive connectors  74  adjoining the frame  80  while the carrier substrate  30  and the adhesive layer  32  are removed. 
     The singulation process is performed by sawing  82  along a scribe line region between the regions  100 . The sawing  82  singulates the regions  100  into separate packages  110 .  FIG.  17    illustrates a resulting, singulated package structure. The singulation results in package  110 , which may be from one of the regions  100  in  FIG.  16   , being singulated. 
     In  FIG.  18   , the package  110  is attached to a substrate  120 . The external conductive connectors  74  are electrically and mechanically coupled to pads  122  on the substrate  120 . The substrate  120  can be, for example, a printed circuit board (PCB) or the like. 
     By encapsulating the die  52  in the laminated dielectric material  58  rather than a molding material with a filler material, the top surface of the dielectric material  58  is free from pits and other imperfections that may be caused by the filler material. For example, if a molding material with a filler material was used, then pits and other imperfections may be formed during a subsequent grinding process of the molding material. However, the laminated dielectric material  58  may not require a grinding process, and even if one is used, will not cause pits or other imperfections. In addition, the formation of the TIVs  66 A is combination with the formation of the vias  66 B and the conductive patterns  68  to reduce the number of steps and increase the throughput of the process. 
       FIGS.  19  through  22    are various intermediate structures in forming a package structure in accordance with embodiments that are similar to the previously described embodiment in  FIGS.  1  through  18    except in  FIGS.  19  through  22   , the molding material  42  in the first layer of the structure is replaced with a dielectric material  130 . Details regarding this embodiment that are similar to those for the previously described embodiment will not be repeated herein. 
     Processing first proceeds as discussed above with respect to  FIGS.  1  and  2    to achieve the structure illustrated in  FIG.  19   .  FIG.  20    illustrates the encapsulation of the dies  36  in a dielectric material  130 . The dielectric material  130  may be a polymer, such as PBO, polyimide, BCB, or the like. In other embodiments, the dielectric material  58  is formed of a nitride such as silicon nitride; an oxide such as silicon oxide, PSG, BSG, BPSG, or the like; or the like. In some embodiments, the dielectric material  130  is a partially cured polymer that is applied as a dry film with a laminating process. In an embodiment, the dielectric material  130  is less than 50 percent cured when applied and may be subsequently cured. In some embodiments, the degree of curing of the dielectric material  130  is directly related to the amount of cross-linking in the dielectric material  130 . The dielectric material  130  may be formed by any acceptable deposition process, such as spin coating, CVD, laminating, the like, or a combination thereof. 
     In some embodiments, the dies  36  are buried in the dielectric material  130 , and after the curing of the dielectric material  130 , a planarization step, such as a grinding, is performed on the dielectric material  130  as illustrated in  FIG.  20   . The planarization step is used to remove excess portions of the dielectric material  130 , which excess portions are over top surfaces of the passivation layers  40  of the dies  36 . In some embodiments, surfaces of the passivation layers  40  and the pads  38  are exposed, and the surfaces of the passivation layers  40  are level with a surface of the dielectric material  130 . The dielectric material  130  may be described as laterally encapsulating the dies  36 . In some embodiments, the dielectric material  130  is formed to have a height H 1  that is less than or equal to 200 μm, such as about 150 μm. 
       FIG.  21    illustrates the formation of a dielectric material  46  over the active sides of the dies  36 , such as on the passivation layers  40 . The dielectric material  46  may continuously cover the dies  36  and the dielectric material  130  and may cover the pads  38 . 
     Processing will continue similar to  FIGS.  5  through  17    as discussed above to achieve the package  140  illustrated in  FIG.  22    which is similar to the package  110  in  FIG.  18   . In  FIG.  22   , the package  140  is attached to the substrate  120 . The external conductive connectors  74  are electrically and mechanically coupled to pads  122  on the substrate  120 . The substrate  120  can be, for example, a PCB or the like. 
     By encapsulating both the dies  36  and the die  52  in the laminated dielectric material  130  and laminated dielectric material  58 , respectively rather than molding materials with filler materials, the top surfaces of the dielectric material are free from pits and other imperfections that may be caused by the filler. For example, if molding materials with filler materials were used, then pits and other imperfections may be formed during a subsequent grinding process of the molding materials. However, the laminated dielectric materials may not require a grinding process, and even if one is used, will not cause pits or other imperfections. 
       FIGS.  23  through  33    are various intermediate structures in forming a package structure in accordance with embodiments that are similar to the previously described embodiment in  FIGS.  1  through  18    except in  FIGS.  23  through  33   , the TIVs and the vias are formed in separate processes with the TIVs being formed first. Details regarding this embodiment that are similar to those for the previously described embodiment will not be repeated herein. 
     Processing first proceeds as discussed above with respect to  FIGS.  1  through  6   . In  FIG.  23    a mask  150 , such as photoresist, is deposited and patterned forming openings  152 , such as by an acceptable photolithography technique. The openings  152  will be used to form the TIVs through the Nth layer of the structure. 
       FIG.  24    illustrates the formation of the TIVs  154  in the openings  152  and coupled to at least one of the conductive patterns  48 . In the illustrated embodiment, one of the TIVs  154  is coupled to the conductive pattern  48 A and one is coupled to the conductive pattern  48 C. The TIVs  154 , in an example, include a metal such as copper, titanium, the like, or a combination thereof, formed by a plating process, such as electroless plating, electroplating, or the like. For example, a seed layer (not shown) may be in at least the bottoms of the openings  152  and may be formed before or after the mask  150 . The seed layer can be copper, titanium, the like, or a combination thereof deposited by ALD, sputtering, another PVD process, or the like. A conductive material, such as copper, aluminum, the like, or a combination thereof, is deposited on the seed layer (if present) by electroless plating, electroplating, or the like. The mask  150  is removed, such as an appropriate process, such as a photoresist stripping process. Remaining exposed seed layer portions are removed, such as by a wet or dry etch to leave the TIVs  154 . 
       FIG.  25    illustrates the adhering of die  52  to the dielectric material  46  (and possibly one or more of the conductive patterns  48 ) by an adhesive layer  50 . In the illustrated embodiment, the die  52  is adhered between two of the TIVs  154 . 
       FIG.  26    illustrates the formation of a dielectric material  58  over the conductive patterns  48 , the TIVs  154 , the dielectric material  46 , and the die  52 . The dielectric material  58  laterally encapsulates the die  52  and the TIVs  154 . As shown, the dielectric material  58  continuously extends from a region disposed laterally from the die  52  and the TIVs  154  to a region disposed directly above the die  52  and the TIVs  154 , respectively. For example, there is no vertical interface (where vertical, as shown, is in a direction perpendicular to a top surface of the die  52  and the TIVs  154 ) with a different dielectric material near a lateral edge of the die  52  and the TIVs  154 , e.g., not directly over pad  54  of the die  52  or the top surface of the TIVs  154 . 
     In some embodiments, the TIVs  154  are buried in the dielectric material  58 , and after the curing of the dielectric material  58 , a planarization step, such as a grinding, is performed on the dielectric material  58  as illustrated in  FIG.  27   . The planarization step is used to remove excess portions of the dielectric material  58 , which excess portions are over top surfaces of the TIVs  154 . In some embodiments, surfaces of the TIVs  154  are exposed, and the surfaces of the TIVs  154  are level with a surface of the dielectric material  58 . The dielectric material  58  may be described as laterally encapsulating the TIVs  154 . 
       FIG.  28    illustrates the formation of openings  60  through the dielectric material  58  and the passivation layer  56  (if openings not already formed through passivation layer  56 ) to expose portions of the pads  54 . The openings  60  may be referred to as via openings  60 . The openings  60  may be formed by, for example, etching, milling, laser techniques, the like, or a combination thereof. 
       FIG.  29    illustrates the formation of seed layer  64  and conductive material  66  over the dielectric material  58  and the TIVs  154  and in the openings  60  to the pads  54 . The seed layer  64  may be deposited over the dielectric material  58  and in the openings  60 . 
     In some embodiments, the conductive material  66  has an uneven top surface, and a planarization step, such as a grinding, is performed on the conductive material  66  as illustrated in  FIG.  30   . The planarization step is used to provide a planar top surface for the conductive material  66 . 
       FIG.  40    further illustrates the patterning of the conductive material  66  to form conductive patterns  156  ( 156 A,  156 B, and  156 C). The conductive material  66  can be patterned with any acceptable photolithography technique. In one example, a photoresist is deposited and patterned exposing the pattern for the conductive patterns  68  that is desired, such as by an acceptable photolithography technique. The exposed conductive material  66  is then removed with an acceptable etch process to form the separate conductive patterns  156  which are similar to the conductive patterns  68  described above except that the conductive patterns  156 A and  156 C do not include via or TIV portions as the TIVs  154  were formed in a separate process. The conductive patterns  156  may be referred to as a redistribution layer  156 . The photoresist is removed, such as an appropriate photoresist stripping process. Remaining exposed seed layer portions are removed, such as by a wet or dry etch. 
       FIG.  32    illustrates the formation of the dielectric layer  70  and the formation of openings  72  through the dielectric layer  70 . The dielectric layer  70  covers the conductive patterns  156  with the openings  72  exposing portions of the conductive patterns  156  by, for example, etching, milling, laser techniques, the like, or a combination thereof. 
     Processing will continue similar to  FIGS.  14  through  17    as discussed above to achieve the package  160  illustrated in  FIG.  33    which is similar to the package  110  in  FIG.  17   . In  FIG.  33   , the package  160  is attached to the substrate  120 . The external conductive connectors  74  are electrically and mechanically coupled to pads  122  on the substrate  120 . The substrate  120  can be, for example, a PCB or the like. 
       FIG.  34    is a package structure in accordance with embodiments that are similar to the previously described embodiment in  FIGS.  23  through  33    except in  FIGS.  34   , the molding material  42  is replaced with dielectric material  170  which is similar to the dielectric material  130  described above in the embodiment in  FIGS.  19  through  22   . Details regarding this embodiment that are similar to those for the previously described embodiment will not be repeated herein. 
     By encapsulating one or more of the dies  52  and  36  in the laminated dielectric material rather than a molding material with a filler material, the top surface of the dielectric material is free from pits and other imperfections that may be caused by the filler. For example, if a molding material with a filler material was used, then pits and other imperfections may be formed during a subsequent grinding process of the molding material. However, the laminated dielectric material may not require a grinding process, and even if one is used, will not cause pits or other imperfections. In addition, the formation of the TIVs can be in combination with the formation of other vias and the conductive patterns to reduce the number of steps and increase the throughput of the process. 
     An embodiment is method including forming a first die package over a carrier substrate, the first die package comprising a first die, forming a first redistribution layer over and coupled to the first die, the first redistribution layer including one or more metal layers disposed in one or more dielectric layers, adhering a second die over the redistribution layer, laminating a first dielectric material over the second die and the first redistribution layer, forming first vias through the first dielectric material to the second die and forming second vias through the first dielectric material to the first redistribution layer, and forming a second redistribution layer over the first dielectric material and over and coupled to the first vias and the second vias. 
     Another embodiment is a method including adhering backside surfaces of a first die and a second die to a carrier substrate, the first die and the second die having active surfaces opposite of the backside surfaces, the active surfaces including conductive pads, encapsulating at least lateral edges of the first die and the second die with an encapsulant, laminating a first dielectric layer over the active surfaces of the first die and the second die and the encapsulant, forming a first redistribution layer over the first dielectric layer and coupled to the conductive pads of first die and the second die, adhering a backside surfaces of a third die to the first dielectric layer, the third die having an active surface opposite of a backside surface, the active surface including conductive pads, laminating a second dielectric layer over the second die and the first redistribution layer, and forming a second redistribution layer over the second dielectric layer and coupled to the conductive pads of third die and the first redistribution layer. 
     A further embodiment is a structure including a first die layer including a first die and a second die laterally encapsulated with an encapsulant, the first die and the second die having backside surfaces and active surfaces opposite of the backside surfaces, the active surfaces including conductive pads, a first dielectric layer over the active surfaces of the first die and the second die and over the encapsulant, a first redistribution layer extending along a top surface of the first dielectric layer and extending through the first dielectric layer to contact the conductive pads of the first die and the second die, a second die layer including a third die over the first dielectric layer and the first redistribution layer, the third die being laterally encapsulated with a second dielectric layer, the third die having a backside surface and an active surface opposite of the backside surface, the active surface including conductive pads, and a second redistribution layer extending along a top surface of the second dielectric layer and extending through the second dielectric layer to contact the conductive pads of the third die and the first redistribution layer. 
     The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.