Patent Publication Number: US-10776690-B2

Title: Neural network unit with plurality of selectable output functions

Description:
CROSS REFERENCE TO RELATED APPLICATION(S) 
     This application claims priority based on the following U.S. Provisional Applications, each of which is hereby incorporated by reference in its entirety. 
                                     Ser. No.   Filing Date   Title                  62/239,254   Oct. 8, 2015   PROCESSOR WITH NEURAL NETWORK UNIT       62/262,104   Dec. 2, 2015   PROCESSOR WITH VARIABLE RATE EXECUTION               UNIT       62/299,191   Feb. 4, 2016   MECHANISM FOR COMMUNICATION BETWEEN               ARCHITECTURAL PROGRAM RUNNING ON               PROCESSOR AND NON-ARCHITECTURAL               PROGRAM RUNNING ON EXECUTION UNIT OF THE               PROCESSOR REGARDING SHARED RESOURCE;               NEURAL NETWORK UNIT WITH OUTPUT BUFFER               FEEDBACK AND MASKING CAPABILITY, AND               THAT PERFORMS CONCURRENT LSTM CELL               CALCULATIONS, AND WITH OUTPUT BUFFER               FEEDBACK FOR PERFORMING RECURRENT               NEURAL NETWORK COMPUTATIONS                    
This application is related to the following concurrently-filed U.S. Non-Provisional Applications, each of which is hereby incorporated by reference in its entirety.
 
     
       
         
           
               
               
             
               
                   
               
               
                 Ser. No. 
                 Title 
               
               
                   
               
             
            
               
                 VAS.3039 
                 NEURAL NETWORK UNIT WITH NEURAL MEMORY AND 
               
               
                   
                 ARRAY OF NEURAL PROCESSING UNITS THAT 
               
               
                   
                 COLLECTIVELY SHIFT ROW OF DATA RECEIVED FROM 
               
               
                   
                 NEURAL MEMORY 
               
               
                 VAS.3040 
                 TRI-CONFIGURATION NEURAL NETWORK UNIT 
               
               
                 VAS.3049 
                 PROCESSOR WITH ARCHITECTURAL NEURAL NETWORK 
               
               
                   
                 EXECUTION UNIT 
               
               
                 VAS.3050 
                 NEURAL NETWORK UNIT WITH NEURAL PROCESSING 
               
               
                   
                 UNITS DYNAMICALLY CONFIGURABLE TO PROCESS 
               
               
                   
                 MULTIPLE DATA SIZES 
               
               
                 VAS.3051 
                 NEURAL PROCESSING UNIT THAT SELECTIVELY WRITES 
               
               
                   
                 BACK TO NEURAL MEMORY EITHER ACTIVATION 
               
               
                   
                 FUNCTION OUTPUT OR ACCUMULATOR VALUE 
               
               
                 VAS.3052 
                 NEURAL NETWORK UNIT WITH SHARED ACTIVATION 
               
               
                   
                 FUNCTION UNITS 
               
               
                 VAS.3053 
                 NEURAL NETWORK UNIT EMPLOYING USER-SUPPLIED 
               
               
                   
                 RECIPROCAL FOR NORMALIZING AN ACCUMULATED VALUE 
               
               
                 VAS.3059 
                 PROCESSOR WITH VARIABLE RATE EXECUTION UNIT 
               
               
                 VAS.3060 
                 MECHANISM FOR COMMUNICATION BETWEEN 
               
               
                   
                 ARCHITECTURAL PROGRAM RUNNING ON PROCESSOR 
               
               
                   
                 AND NON-ARCHITECTURAL PROGRAM RUNNING ON 
               
               
                   
                 EXECUTION UNIT OF THE PROCESSOR REGARDING 
               
               
                   
                 SHARED RESOURCE 
               
               
                 VAS.3062 
                 DIRECT EXECUTION BY AN EXECUTION UNIT OF A MICRO- 
               
               
                   
                 OPERATION LOADED INTO AN ARCHITECTURAL REGISTER 
               
               
                   
                 FILE BY AN ARCHITECTURAL INSTRUCTION OF A PROCESSOR 
               
               
                 VAS.3063 
                 MULTI-OPERATION NEURAL NETWORK UNIT 
               
               
                 VAS.3064 
                 NEURAL NETWORK UNIT THAT PERFORMS 
               
               
                   
                 CONVOLUTIONS USING COLLECTIVE SHIFT REGISTER 
               
               
                   
                 AMONG ARRAY OF NEURAL PROCESSING UNITS 
               
               
                 VAS.3065 
                 NEURAL NETWORK UNIT WITH PLURALITY OF 
               
               
                   
                 SELECTABLE OUTPUT FUNCTIONS 
               
               
                 VAS.3066 
                 NEURAL NETWORK UNIT THAT PERFORMS STOCHASTIC ROUNDING 
               
               
                 VAS.3067 
                 APPARATUS EMPLOYING USER-SPECIFIED BINARY POINT 
               
               
                   
                 FIXED POINT ARITHMETIC 
               
               
                 VAS.3068 
                 PROCESSOR WITH HYBRID COPROCESSOR/EXECUTION 
               
               
                   
                 UNIT NEURAL NETWORK UNIT 
               
               
                 VAS.3069 
                 NEURAL NETWORK UNIT WITH OUTPUT BUFFER 
               
               
                   
                 FEEDBACK AND MASKING CAPABILITY 
               
               
                 VAS.3075 
                 NEURAL NETWORK UNIT THAT PERFORMS CONCURRENT 
               
               
                   
                 LSTM CELL CALCULATIONS 
               
               
                 VAS.3076 
                 NEURAL NETWORK UNIT WITH OUTPUT BUFFER 
               
               
                   
                 FEEDBACK FOR PERFORMING RECURRENT NEURAL 
               
               
                   
                 NETWORK COMPUTATIONS 
               
               
                 VAS.3078 
                 NEURAL NETWORK UNIT WITH NEURAL MEMORY AND 
               
               
                   
                 ARRAY OF NEURAL PROCESSING UNITS AND SEQUENCER 
               
               
                   
                 THAT COLLECTIVELY SHIFT ROW OF DATA RECEIVED 
               
               
                   
                 FROM NEURAL MEMORY 
               
               
                 VAS.3079 
                 NEURAL NETWORK UNIT WITH OUTPUT BUFFER 
               
               
                   
                 FEEDBACK AND MASKING CAPABILITY WITH PROCESSING 
               
               
                   
                 UNIT GROUPS THAT OPERATE AS RECURRENT NEURAL 
               
               
                   
                 NETWORK LSTM CELLS 
               
               
                   
               
            
           
         
       
     
     BACKGROUND 
     Recently, there has been a resurgence of interest in artificial neural networks (ANN), and such research has commonly been termed deep learning, computer learning and similar terms. The increase in general-purpose processor computation power has given rise to the renewed interest that waned a couple of decades ago. Recent applications of ANNs have included speech and image recognition, along with others. There appears to be an increasing demand for improved performance and efficiency of computations associated with ANNs. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a block diagram illustrating a processor that includes a neural network unit (NNU). 
         FIG. 2  is a block diagram illustrating a NPU of  FIG. 1 . 
         FIG. 3  is a block diagram illustrating an embodiment of the arrangement of the N mux-regs of the N NPUs of the NNU of  FIG. 1  to illustrate their operation as an N-word rotater, or circular shifter, for a row of data words received from the data RAM of  FIG. 1 . 
         FIG. 4  is a table illustrating a program for storage in the program memory of and execution by the NNU of  FIG. 1 . 
         FIG. 5  is a timing diagram illustrating the execution of the program of  FIG. 4  by the NNU. 
         FIG. 6A  is a block diagram illustrating the NNU of  FIG. 1  to execute the program of  FIG. 4 . 
         FIG. 6B  is a flowchart illustrating operation of the processor of  FIG. 1  to perform an architectural program that uses the NNU to perform multiply-accumulate-activation function computations classically associated with neurons of hidden layers of an artificial neural network such as performed by the program of  FIG. 4 . 
         FIG. 7  is a block diagram illustrating a NPU of  FIG. 1  according to an alternate embodiment. 
         FIG. 8  is a block diagram illustrating a NPU of  FIG. 1  according to an alternate embodiment. 
         FIG. 9  is a table illustrating a program for storage in the program memory of and execution by the NNU of  FIG. 1 . 
         FIG. 10  is a timing diagram illustrating the execution of the program of  FIG. 9  by the NNU. 
         FIG. 11  is a block diagram illustrating an embodiment of the NNU of  FIG. 1  is shown. In the embodiment of  FIG. 11 , a neuron is split into two portions, the activation function unit portion and the ALU portion (which also includes the shift register portion), and each activation function unit portion is shared by multiple ALU portions. 
         FIG. 12  is a timing diagram illustrating the execution of the program of  FIG. 4  by the NNU of  FIG. 11 . 
         FIG. 13  is a timing diagram illustrating the execution of the program of  FIG. 4  by the NNU of  FIG. 11 . 
         FIG. 14  is a block diagram illustrating a move to neural network (MTNN) architectural instruction and its operation with respect to portions of the NNU of  FIG. 1 . 
         FIG. 15  is a block diagram illustrating a move from neural network (MFNN) architectural instruction and its operation with respect to portions of the NNU of  FIG. 1 . 
         FIG. 16  is a block diagram illustrating an embodiment of the data RAM of  FIG. 1 . 
         FIG. 17  is a block diagram illustrating an embodiment of the weight RAM of  FIG. 1  and a buffer. 
         FIG. 18  is a block diagram illustrating a dynamically configurable NPU of  FIG. 1 . 
         FIG. 19  is a block diagram illustrating an embodiment of the arrangement of the 2N mux-regs of the N NPUs of the NNU of  FIG. 1  according to the embodiment of  FIG. 18  to illustrate their operation as a rotater for a row of data words received from the data RAM of  FIG. 1 . 
         FIG. 20  is a table illustrating a program for storage in the program memory of and execution by the NNU of  FIG. 1  having NPUs according to the embodiment of  FIG. 18 . 
         FIG. 21  is a timing diagram illustrating the execution of the program of  FIG. 20  by the NNU that includes NPUs of  FIG. 18  operating in a narrow configuration. 
         FIG. 22  is a block diagram illustrating the NNU of  FIG. 1  including the NPUs of  FIG. 18  to execute the program of  FIG. 20 . 
         FIG. 23  is a block diagram illustrating a dynamically configurable NPU of  FIG. 1  according to an alternate embodiment. 
         FIG. 24  is a block diagram illustrating an example of data structures used by the NNU of  FIG. 1  to perform a convolution operation. 
         FIG. 25  is a flowchart illustrating operation of the processor of  FIG. 1  to perform an architectural program that uses the NNU to perform a convolution of the convolution kernel with the data array of  FIG. 24 . 
         FIG. 26A  is a program listing of an NNU program that performs a convolution of a data matrix with the convolution kernel of  FIG. 24  and writes it back to the weight RAM. 
         FIG. 26B  is a block diagram illustrating certain fields of the control register of the NNU of  FIG. 1  according to one embodiment. 
         FIG. 27  is a block diagram illustrating an example of the weight RAM of  FIG. 1  populated with input data upon which a pooling operation is performed by the NNU of  FIG. 1 . 
         FIG. 28  is a program listing of an NNU program that performs a pooling operation of the input data matrix of  FIG. 27  and writes it back to the weight RAM. 
         FIG. 29A  is a block diagram illustrating an embodiment of the control register of  FIG. 1 . 
         FIG. 29B  is a block diagram illustrating an embodiment of the control register of  FIG. 1  according to an alternate embodiment. 
         FIG. 29C  is a block diagram illustrating an embodiment of the reciprocal of  FIG. 29A  stored as two parts according to one embodiment. 
         FIG. 30  is a block diagram illustrating in more detail an embodiment of an AFU of  FIG. 2 . 
         FIG. 31  is an example of operation of the AFU of  FIG. 30 . 
         FIG. 32  is a second example of operation of the AFU of  FIG. 30 . 
         FIG. 33  is a third example of operation of the AFU of  FIG. 30 . 
         FIG. 34  is a block diagram illustrating the processor of  FIG. 1  and in more detail portions of the NNU of  FIG. 1 . 
     
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
     Processor with Architectural Neural Network Unit 
     Referring now to  FIG. 1 , a block diagram illustrating a processor  100  that includes a neural network unit (NNU)  121  is shown. The processor  100  includes an instruction fetch unit  101 , an instruction cache  102 , and instruction translator  104 , a rename unit  106 , reservation stations  108 , media registers  118 , general purpose registers (GPR)  116 , execution units  112  other than the NNU  121 , and a memory subsystem  114 . 
     The processor  100  is an electronic device that functions as a central processing unit (CPU) on an integrated circuit. The processor  100  receives digital data as input, processes the data according to instructions fetched from a memory, and generates results of operations prescribed by the instructions as output. The processor  100  may be employed in a desktop, mobile, or tablet computer, and is employed for uses such as computation, text editing, multimedia display, and Internet browsing. The processor  100  may also be disposed in an embedded system to control a wide variety of devices including appliances, mobile telephones, smart phones, automobiles and industrial control devices. A CPU is the electronic circuits (i.e., “hardware”) that execute the instructions of a computer program (also known as a “computer application” or “application”) by performing operations on data that include arithmetic operations, logical operations, and input/output operations. An integrated circuit (IC) is a set of electronic circuits fabricated on a small piece of semiconductor material, typically silicon. An IC is also referred to as a chip, a microchip, or a die. 
     The instruction fetch unit  101  controls the fetching of architectural instructions  103  from system memory (not shown) into the instruction cache  102 . The instruction fetch unit  101  provides a fetch address to the instruction cache  102  that specifies a memory address at which the processor  100  fetches a cache line of architectural instruction bytes into the instruction cache  102 . The fetch address is based on the current value of the instruction pointer (not shown), or program counter, of the processor  100 . Normally, the program counter is incremented sequentially by the size of an instruction unless a control instruction is encountered in the instruction stream, such as a branch, call or return instruction, or an exception condition occurs, such as an interrupt, trap, exception or fault, in which case the program counter is updated with a non-sequential address, such as a branch target address, return address or exception vector. Generally speaking, the program counter is updated in response to the execution of instructions by the execution units  112 / 121 . The program counter may also be updated in response to detection of an exception condition such as the instruction translator  104  encountering an instruction  103  that is not defined by the instruction set architecture of the processor  100 . 
     The instruction cache  102  caches the architectural instructions  103  fetched from a system memory that is coupled to the processor  100 . The architectural instructions  103  include a move to neural network (MTNN) instruction and a move from neural network (MFNN) instruction, which are described in more detail below. In one embodiment, the architectural instructions  103  are instructions of the x86 instruction set architecture (ISA), with the addition of the MTNN and MFNN instructions. In the context of the present disclosure, an x86 ISA processor as a processor that generates the same results at the instruction set architecture level that an Intel® 80386® processor generates when it executes the same machine language instructions. However, other embodiments contemplate other instruction set architectures, such as Advanced RISC Machines (ARM)®, Sun SPARC®, or PowerPC®. The instruction cache  102  provides the architectural instructions  103  to the instruction translator  104 , which translates the architectural instructions  103  into microinstructions  105 . 
     The microinstructions  105  are provided to the rename unit  106  and eventually executed by the execution units  112 / 121 . The microinstructions  105  implement the architectural instructions. Preferably, the instruction translator  104  includes a first portion that translates frequently executed and/or relatively less complex architectural instructions  103  into microinstructions  105 . The instruction translator  104  also includes a second portion that includes a microcode unit (not shown). The microcode unit includes a microcode memory that holds microcode instructions that implement complex and/or infrequently used instructions of the architectural instruction set. The microcode unit also includes a microsequencer that provides a non-architectural micro-program counter (micro-PC) to the microcode memory. Preferably, the microcode instructions are translated by a microtranslator (not shown) into the microinstructions  105 . A selector selects the microinstructions  105  from either the first portion or the second portion for provision to the rename unit  106 , depending upon whether or not the microcode unit currently has control. 
     The rename unit  106  renames architectural registers specified in the architectural instructions  103  to physical registers of the processor  100 . Preferably, the processor  100  includes a reorder buffer (not shown). The rename unit  106  allocates, in program order, an entry in the reorder buffer for each microinstruction  105 . This enables the processor  100  to retire the microinstructions  105 , and their corresponding architectural instructions  103 , in program order. In one embodiment, the media registers  118  are 256 bits wide and the GPR  116  are 64 bits wide. In one embodiment, the media registers  118  are x86 media registers, such as Advanced Vector Extensions (AVX) registers. 
     In one embodiment, each entry in the reorder buffer includes storage for the result of the microinstruction  105 ; additionally, the processor  100  includes an architectural register file that includes a physical register for each of the architectural registers, e.g., the media registers  118  and the GPR  116  and other architectural registers. (Preferably, there are separate register files for the media registers  118  and GPR  116 , for example, since they are different sizes.) For each source operand of a microinstruction  105  that specifies an architectural register, the rename unit populates the source operand field in the microinstruction  105  with the reorder buffer index of the newest older microinstruction  105  that writes to the architectural register. When the execution unit  112 / 121  completes execution of the microinstruction  105 , it writes the result to the microinstruction&#39;s  105  reorder buffer entry. When the microinstruction  105  retires, a retire unit (not shown) writes the result from the microinstruction&#39;s reorder buffer entry to the register of the physical register file associated with the architectural destination register specified by the retiring microinstruction  105 . 
     In another embodiment, the processor  100  includes a physical register file that includes more physical registers than the number of architectural registers, but does not include an architectural register file, and the reorder buffer entries do not include result storage. (Preferably, there are separate physical register files for the media registers  118  and GPR  116 , for example, since they are different sizes.) The processor  100  also includes a pointer table with an associated pointer for each architectural register. For the operand of a microinstruction  105  that specifies an architectural register, the rename unit populates the destination operand field in the microinstruction  105  with a pointer to a free register in the physical register file. If no registers are free in the physical register file, the rename unit  106  stalls the pipeline. For each source operand of a microinstruction  105  that specifies an architectural register, the rename unit populates the source operand field in the microinstruction  105  with a pointer to the register in the physical register file assigned to the newest older microinstruction  105  that writes to the architectural register. When the execution unit  112 / 121  completes execution of the microinstruction  105 , it writes the result to a register of the physical register file pointed to by the microinstruction&#39;s  105  destination operand field. When the microinstruction  105  retires, the retire unit copies the microinstruction&#39;s  105  destination operand field value to the pointer in the pointer table associated with the architectural destination register specified by the retiring microinstruction  105 . 
     The reservation stations  108  hold microinstructions  105  until they are ready to be issued to an execution unit  112 / 121  for execution. A microinstruction  105  is ready to be issued when all of its source operands are available and an execution unit  112 / 121  is available to execute it. The execution units  112 / 121  receive register source operands from the reorder buffer or the architectural register file in the first embodiment or from the physical register file in the second embodiment described above. Additionally, the execution units  112 / 121  may receive register source operands directly from the execution units  112 / 121  via result forwarding buses (not shown). Additionally, the execution units  112 / 121  may receive from the reservation stations  108  immediate operands specified by the microinstructions  105 . As discussed in more detail below, the MTNN and MFNN architectural instructions  103  include an immediate operand that specifies a function to be performed by the NNU  121  that is provided in one of the one or more microinstructions  105  into which the MTNN and MFNN architectural instructions  103  are translated. 
     The execution units  112  include one or more load/store units (not shown) that load data from the memory subsystem  114  and store data to the memory subsystem  114 . Preferably, the memory subsystem  114  includes a memory management unit (not shown), which may include, e.g., translation lookaside buffers and a tablewalk unit, a level-1 data cache (and the instruction cache  102 ), a level-2 unified cache, and a bus interface unit that interfaces the processor  100  to system memory. In one embodiment, the processor  100  of  FIG. 1  is representative of a processing core that is one of multiple processing cores in a multi-core processor that share a last-level cache memory. The execution units  112  may also include integer units, media units, floating-point units and a branch unit. 
     The NNU  121  includes a weight random access memory (RAM)  124 , a data RAM  122 , N neural processing units (NPUs)  126 , a program memory  129 , a sequencer  128  and control and status registers  127 . The NPUs  126  function conceptually as neurons in a neural network. The weight RAM  124 , data RAM  122  and program memory  129  are all writable and readable via the MTNN and MFNN architectural instructions  103 , respectively. The weight RAM  124  is arranged as W rows of N weight words, and the data RAM  122  is arranged as D rows of N data words. Each data word and each weight word is a plurality of bits, preferably 8 bits, 9 bits, 12 bits or 16 bits. Each data word functions as the output value (also sometimes referred to as an activation) of a neuron of the previous layer in the network, and each weight word functions as a weight associated with a connection coming into a neuron of the instant layer of the network. Although in many uses of the NNU  121  the words, or operands, held in the weight RAM  124  are in fact weights associated with a connection coming into a neuron, it should be understood that in other uses of the NNU  121  the words held in the weight RAM  124  are not weights, but are nevertheless referred to as “weight words” because they are stored in the weight RAM  124 . For example, in some uses of the NNU  121 , e.g., the convolution example of  FIGS. 24 through 26A  or the pooling example of  FIGS. 27 through 28 , the weight RAM  124  may hold non-weights, such as elements of a data matrix, e.g., image pixel data. Similarly, although in many uses of the NNU  121  the words, or operands, held in the data RAM  122  are in fact the output value, or activation, of a neuron, it should be understood that in other uses of the NNU  121  the words held in the data RAM  122  are not such, but are nevertheless referred to as “data words” because they are stored in the data RAM  122 . For example, in some uses of the NNU  121 , e.g., the convolution example of  FIGS. 24 through 26A , the data RAM  122  may hold non-neuron outputs, such as elements of a convolution kernel. 
     In one embodiment, the NPUs  126  and sequencer  128  comprise combinatorial logic, sequential logic, state machines, or a combination thereof. An architectural instruction (e.g., MFNN instruction  1500 ) loads the contents of the status register  127  into one of the GPR  116  to determine the status of the NNU  121 , e.g., that the NNU  121  has completed a command or completed a program the NNU  121  was running from the program memory  129 , or that the NNU  121  is free to receive a new command or start a new NNU program. 
     Advantageously, the number of NPUs  126  may be increased as needed, and the size of the weight RAM  124  and data RAM  122  may be extended in both width and depth accordingly. Preferably, the weight RAM  124  is larger since in a classic neural network layer there are many connections, and therefore weights, associated with each neuron. Various embodiments are described herein regarding the size of the data and weight words and the sizes of the weight RAM  124  and data RAM  122  and the number of NPUs  126 . In one embodiment, a NNU  121  with a 64 KB (8192 bits×64 rows) data RAM  122 , a 2 MB (8192 bits×2048 rows) weight RAM  124 , and 512 NPUs  126  is implemented in a Taiwan Semiconductor Manufacturing Company, Limited (TSMC) 16 nm process and occupies approximately a 3.3 mm 2  area. 
     The sequencer  128  fetches instructions from the program memory  129  and executes them, which includes, among other things, generating address and control signals for provision to the data RAM  122 , weight RAM  124  and NPUs  126 . The sequencer  128  generates a memory address  123  and a read command for provision to the data RAM  122  to select one of the D rows of N data words for provision to the N NPUs  126 . The sequencer  128  also generates a memory address  125  and a read command for provision to the weight RAM  124  to select one of the W rows of N weight words for provision to the N NPUs  126 . The sequence of the addresses  123  and  125  generated by the sequencer  128  for provision to the NPUs  126  determines the “connections” between neurons. The sequencer  128  also generates a memory address  123  and a write command for provision to the data RAM  122  to select one of the D rows of N data words for writing from the N NPUs  126 . The sequencer  128  also generates a memory address  125  and a write command for provision to the weight RAM  124  to select one of the W rows of N weight words for writing from the N NPUs  126 . The sequencer  128  also generates a memory address  131  to the program memory  129  to select a NNU instruction that is provided to the sequencer  128 , such as described below. The memory address  131  corresponds to a program counter (not shown) that the sequencer  128  generally increments through sequential locations of the program memory  129  unless the sequencer  128  encounters a control instruction, such as a loop instruction (see, for example,  FIG. 26A ), in which case the sequencer  128  updates the program counter to the target address of the control instruction. The sequencer  128  also generates control signals to the NPUs  126  to instruct them to perform various operations or functions, such as initialization, arithmetic/logical operations, rotate and shift operations, activation functions and write back operations, examples of which are described in more detail below (see, for example, micro-operations  3418  of  FIG. 34 ). 
     The N NPUs  126  generate N result words  133  that may be written back to a row of the weight RAM  124  or to the data RAM  122 . Preferably, the weight RAM  124  and the data RAM  122  are directly coupled to the N NPUs  126 . More specifically, the weight RAM  124  and data RAM  122  are dedicated to the NPUs  126  and are not shared by the other execution units  112  of the processor  100 , and the NPUs  126  are capable of consuming a row from one or both of the weight RAM  124  and data RAM  122  each clock cycle in a sustained manner, preferably in a pipelined fashion. In one embodiment, each of the data RAM  122  and the weight RAM  124  is capable of providing 8192 bits to the NPUs  126  each clock cycle. The 8192 bits may be consumed as 512 16-bit words or as 1024 8-bit words, as described in more detail below. 
     Advantageously, the size of the data set that may be processed by the NNU  121  is not limited to the size of the weight RAM  124  and data RAM  122 , but is rather only limited by the size of system memory since data and weights may be moved between system memory and the weight RAM  124  and data RAM  122  using the MTNN and MFNN instructions (e.g., through the media registers  118 ). In one embodiment, the data RAM  122  is dual-ported to enable data words to be written to the data RAM  122  while data words are concurrently read from or written to the data RAM  122 . Furthermore, the large memory hierarchy of the memory subsystem  114 , including the cache memories, provides very high data bandwidth for the transfers between the system memory and the NNU  121 . Still further, preferably, the memory subsystem  114  includes hardware data prefetchers that track memory access patterns, such as loads of neural data and weights from system memory, and perform data prefetches into the cache hierarchy to facilitate high bandwidth and low latency transfers to the weight RAM  124  and data RAM  122 . 
     Although embodiments are described in which one of the operands provided to each NPU  126  is provided from a weight memory and is denoted a weight, which are commonly used in neural networks, it should be understood that the operands may be other types of data associated with calculations whose speed may be improved by the apparatuses described. 
     Referring now to  FIG. 2 , a block diagram illustrating a NPU  126  of  FIG. 1  is shown. The NPU  126  operates to perform many functions, or operations. In particular, advantageously the NPU  126  is configured to operate as a neuron, or node, in an artificial neural network to perform a classic multiply-accumulate function, or operation. That is, generally speaking, the NPU  126  (neuron) is configured to: (1) receive an input value from each neuron having a connection to it, typically but not necessarily from the immediately previous layer of the artificial neural network; (2) multiply each input value by a corresponding weight value associated with the connection to generate a product; (3) add all the products to generate a sum; and (4) perform an activation function on the sum to generate the output of the neuron. However, rather than performing all the multiplies associated with all the connection inputs and then adding all the products together as in a conventional manner, advantageously each neuron is configured to perform, in a given clock cycle, the weight multiply operation associated with one of the connection inputs and then add (accumulate) the product with the accumulated value of the products associated with connection inputs processed in previous clock cycles up to that point. Assuming there are M connections to the neuron, after all M products have been accumulated (which takes approximately M clock cycles), the neuron performs the activation function on the accumulated value to generate the output, or result. This has the advantage of requiring fewer multipliers and a smaller, simpler and faster adder circuit (e.g., a 2-input adder) in the neuron than an adder that would be required to add all, or even a subset of, the products associated with all the connection inputs. This, in turn, has the advantage of facilitating a very large number (N) of neurons (NPUs  126 ) in the NNU  121  so that after approximately M clock cycles, the NNU  121  has generated the output for all of the large number (N) of neurons. Finally, the NNU  121  constructed of such neurons has the advantage of efficiently performing as an artificial neural network layer for a large number of different connection inputs. That is, as M increases or decreases for different layers, the number of clock cycles required to generate the neuron outputs correspondingly increases or decreases, and the resources (e.g., multipliers and accumulators) are fully utilized; whereas, in a more conventional design, some of the multipliers and a portion of the adder may not be utilized for smaller values of M. Thus, the embodiments described herein have the benefit of flexibility and efficiency with respect to the number of connection inputs to the neurons of the NNU  121 , and provide extremely high performance. 
     The NPU  126  includes a register  205 , a 2-input multiplexed register (mux-reg)  208 , an arithmetic logic unit (ALU)  204 , an accumulator  202 , and an activation function unit (AFU)  212 . The register  205  receives a weight word  206  from the weight RAM  124  and provides its output  203  on a subsequent clock cycle. The mux-reg  208  selects one of its inputs  207  or  211  to store in its register and then to provide on its output  209  on a subsequent clock cycle. One input  207  receives a data word from the data RAM  122 . The other input  211  receives the output  209  of the adjacent NPU  126 . The NPU  126  shown in  FIG. 2  is denoted NPU J from among the N NPUs  126  of  FIG. 1 . That is, NPU J is a representative instance of the N NPUs  126 . Preferably, the mux-reg  208  input  211  of NPU J receives the mux-reg  208  output  209  of NPU  126  instance J−1, and the mux-reg  208  output  209  of NPU J is provided to the mux-reg  208  input  211  of NPU  126  instance J+1. In this manner, the mux-regs  208  of the N NPUs  126  collectively operate as an N-word rotater, or circular shifter, as described in more detail below with respect to  FIG. 3 . A control input  213  controls which of the two inputs the mux-reg  208  selects to store in its register and that is subsequently provided on the output  209 . 
     The ALU  204  has three inputs. One input receives the weight word  203  from the register  205 . Another input receives the output  209  of the mux-reg  208 . The other input receives the output  217  of the accumulator  202 . The ALU  204  performs arithmetic and/or logical operations on its inputs to generate a result provided on its output. Preferably, the arithmetic and/or logical operations to be performed by the ALU  204  are specified by instructions stored in the program memory  129 . For example, the multiply-accumulate instruction of  FIG. 4  specifies a multiply-accumulate operation, i.e., the result  215  is the sum of the accumulator  202  value  217  and the product of the weight word  203  and the data word of the mux-reg  208  output  209 . Other operations that may be specified include, but are not limited to: the result  215  is the passed-through value of the mux-reg output  209 ; the result  215  is the passed-through value of the weight word  203 ; the result  215  is zero; the result  215  is the passed-through value of the weight word  203 ; the result  215  is the sum of the accumulator  202  value  217  and the weight word  203 ; the result  215  is the sum of the accumulator  202  value  217  and the mux-reg output  209 ; the result  215  is the maximum of the accumulator  202  value  217  and the weight word  203 ; the result  215  is the maximum of the accumulator  202  value  217  and the mux-reg output  209 . 
     The ALU  204  provides its output  215  to the accumulator  202  for storage therein. The ALU  204  includes a multiplier  242  that multiplies the weight word  203  and the data word of the mux-reg  208  output  209  to generate a product  246 . In one embodiment, the multiplier  242  multiplies two 16-bit operands to generate a 32-bit result. The ALU  204  also includes an adder  244  that adds the product  246  to the accumulator  202  output  217  to generate a sum, which is the result  215  accumulated in the accumulator  202  for storage in the accumulator  202 . In one embodiment, the adder  244  adds the 32-bit result of the multiplier  242  to a 41-bit value  217  of the accumulator  202  to generate a 41-bit result. In this manner, using the rotater aspect of the mux-reg  208  over the course of multiple clock cycles, the NPU  126  accomplishes a sum of products for a neuron as required by neural networks. The ALU  204  may also include other circuit elements to perform other arithmetic/logical operations such as those above. In one embodiment, a second adder subtracts the weight word  203  from the data word of the mux-reg  208  output  209  to generate a difference, which the adder  244  then adds to the accumulator  202  output  217  to generate a sum  215 , which is the result accumulated in the accumulator  202 . In this manner, over the course of multiple clock cycles, the NPU  126  may accomplish a sum of differences. Preferably, although the weight word  203  and the data word  209  are the same size (in bits), they may have different binary point locations, as described in more detail below. Preferably, the multiplier  242  and adder  244  are integer multipliers and adders, as described in more detail below, to advantageously accomplish less complex, smaller, faster and lower power consuming ALUs  204  than floating-point counterparts. However, it should be understood that in other embodiments the ALU  204  performs floating-point operations. 
     Although  FIG. 2  shows only a multiplier  242  and adder  244  in the ALU  204 , preferably the ALU  204  includes other elements to perform the other operations described above. For example, preferably the ALU  204  includes a comparator (not shown) for comparing the accumulator  202  with a data/weight word and a mux (not shown) that selects the larger (maximum) of the two values indicated by the comparator for storage in the accumulator  202 . For another example, preferably the ALU  204  includes selection logic (not shown) that bypasses the multiplier  242  with a data/weight word to enable the adder  244  to add the data/weight word to the accumulator  202  value  217  to generate a sum for storage in the accumulator  202 . These additional operations are described in more detail below, for example, with respect to  FIGS. 18 through 29A , and may be useful for performing convolution and pooling operations, for example. 
     The AFU  212  receives the output  217  of the accumulator  202 . The AFU  212  performs an activation function on the accumulator  202  output  217  to generate a result  133  of  FIG. 1 . Generally speaking, the activation function in a neuron of an intermediate layer of an artificial neural network may serve to normalize the accumulated sum of products, preferably in a non-linear fashion. To “normalize” the accumulated sum, the activation function of an instant neuron produces a resulting value within a range of values that neurons connected to the instant neuron expect to receive as input. (The normalized result is sometimes referred to as an “activation” that, as described herein, is the output of an instant node that a receiving node multiplies by a weight associated with the connection between the outputting node and the receiving node to generate a product that is accumulated with other products associated with the other input connections to the receiving node.) For example, the receiving/connected neurons may expect to receive as input a value between 0 and 1, in which case the outputting neuron may need to non-linearly squash and/or adjust (e.g., upward shift to transform negative to positive values) the accumulated sum that is outside the 0 to 1 range to a value within the expected range. Thus, the AFU  212  performs an operation on the accumulator  202  value  217  to bring the result  133  within a known range. The results  133  of all of the N NPUs  126  may be written back concurrently to either the data RAM  122  or to the weight RAM  124 . Preferably, the AFU  212  is configured to perform multiple activation functions, and an input, e.g., from the control register  127 , selects one of the activation functions to perform on the accumulator  202  output  217 . The activation functions may include, but are not limited to, a step function, a rectify function, a sigmoid function, a hyperbolic tangent (tanh) function and a softplus function (also referred to as smooth rectify). The softplus function is the analytic function f(x)=ln(1+e x ), that is, the natural logarithm of the sum of one and e x , where “e” is Euler&#39;s number and x is the input  217  to the function. Preferably, the activation functions may also include a pass-through function that passes through the accumulator  202  value  217 , or a portion thereof, as described in more detail below. In one embodiment, circuitry of the AFU  212  performs the activation function in a single clock cycle. In one embodiment, the AFU  212  comprises tables that receive the accumulated value and output a value that closely approximates the value that the true activation function would provide for some of the activation functions, e.g., sigmoid, hyperbolic tangent, softplus. 
     Preferably, the width (in bits) of the accumulator  202  is greater than the width of the AFU  212  output  133 . For example, in one embodiment, the accumulator is 41 bits wide, to avoid loss of precision in the accumulation of up to 512 32-bit products (as described in more detail below, e.g., with respect to  FIG. 30 ), and the result  133  is 16 bits wide. In one embodiment, an example of which is described in more detail below with respect to  FIG. 8 , during successive clock cycles different portions of the “raw” accumulator  202  output  217  value are passed through the AFU  212  and written back to the data RAM  122  or weight RAM  124 . This enables the raw accumulator  202  values to be loaded back to the media registers  118  via the MFNN instruction so that instructions executing on other execution units  112  of the processor  100  may perform complex activation functions that the AFU  212  is not capable of performing, such as the well-known softmax activation function, also referred to as the normalized exponential function. In one embodiment, the processor  100  instruction set architecture includes an instruction that performs the exponential function, commonly referred to as e x  or exp(x), which may be used to speed up the performance of the softmax activation function by the other execution units  112  of the processor  100 . 
     In one embodiment, the NPU  126  is pipelined. For example, the NPU  126  may include registers of the ALU  204 , such as a register between the multiplier and the adder and/or other circuits of the ALU  204 , and a register that holds the output of the AFU  212 . Other embodiments of the NPU  126  are described below. 
     Referring now to  FIG. 3 , a block diagram illustrating an embodiment of the arrangement of the N mux-regs  208  of the N NPUs  126  of the NNU  121  of  FIG. 1  to illustrate their operation as an N-word rotater, or circular shifter, for a row of data words  207  received from the data RAM  122  of  FIG. 1  is shown. In the embodiment of  FIG. 3 , N is 512 such that the NNU  121  has 512 mux-regs  208 , denoted  0  through  511 , corresponding to 512 NPUs  126 , as shown. Each mux-reg  208  receives its corresponding data word  207  of one row of the D rows of the data RAM  122 . That is, mux-reg  0  receives data word  0  of the data RAM  122  row, mux-reg  1  receives data word  1  of the data RAM  122  row, mux-reg  2  receives data word  2  of the data RAM  122  row, and so forth to mux-reg  511  receives data word  511  of the data RAM  122  row. Additionally, mux-reg  1  receives on its other input  211  the output  209  of mux-reg  0 , mux-reg  2  receives on its other input  211  the output  209  of mux-reg  1 , mux-reg  3  receives on its other input  211  the output  209  of mux-reg  2 , and so forth to mux-reg  511  that receives on its other input  211  the output  209  of mux-reg  510 , and mux-reg  0  receives on its other input  211  the output  209  of mux-reg  511 . Each of the mux-regs  208  receives the control input  213  that controls whether to select the data word  207  or the rotated input  211 . As described in more detail below, in one mode of operation, on a first clock cycle, the control input  213  controls each of the mux-regs  208  to select the data word  207  for storage in the register and for subsequent provision to the ALU  204 ; and during subsequent clock cycles (e.g., M−1 clock cycles as described above), the control input  213  controls each of the mux-regs  208  to select the rotated input  211  for storage in the register and for subsequent provision to the ALU  204 . 
     Although  FIG. 3  (and  FIGS. 7 and 19  below) describe an embodiment in which the NPUs  126  are configured to rotate the values of the mux-regs  208 / 705  to the right, i.e., from NPU J to NPU J+1, embodiments are contemplated (such as with respect to the embodiment of  FIGS. 24 through 26 ) in which the NPUs  126  are configured to rotate the values of the mux-regs  208 / 705  to the left, i.e., from NPU J to NPU J−1. Furthermore, embodiments are contemplated in which the NPUs  126  are configured to rotate the values of the mux-regs  208 / 705  selectively to the left or to the right, e.g., as specified by the NNU instructions. 
     Referring now to  FIG. 4 , a table illustrating a program for storage in the program memory  129  of and execution by the NNU  121  of  FIG. 1  is shown. The example program performs the calculations associated with a layer of an artificial neural network as described above. In the table of  FIG. 4 , four rows and three columns are shown. Each row corresponds to an address of the program memory  129  denoted in the first column. The second column specifies the instruction, and the third column indicates the number of clock cycles associated with the instruction. Preferably, the number of clock cycles indicates the effective number of clocks in a clocks-per-instruction type value in a pipelined embodiment, rather than the latency of the instruction. As shown, each of the instructions has an associated one clock cycle due to the pipelined nature of the NNU  121 , with the exception of the instruction at address  2  which requires 511 clocks because it effectively repeats itself 511 times, as described in more detail below. 
     For each instruction of the program, all of the NPUs  126  perform the instruction in parallel. That is, all N NPUs  126  performs the instruction in the first row in the same clock cycle(s), all N NPUs  126  performs the instruction in the second row in the same clock cycle(s), and so forth. However, other embodiments are described below in which some of the instructions are performed in a partially parallel and partially sequential fashion, e.g., the activation function and output instructions at addresses  3  and  4  in an embodiment in which NPUs  126  share an activation function unit, e.g., with respect to the embodiment of  FIG. 11 . The example of  FIG. 4  assumes 512 neurons (NPUs  126 ) of a layer, each having 512 connection inputs from a previous layer of 512 neurons, for a total of 256K connections. Each neuron receives a 16-bit data value from each connection input and multiplies the 16-bit data value by an appropriate 16-bit weight value. 
     The first row, at address  0  (although other addresses may be specified), specifies an initialize NPU instruction. The initialize instruction clears the accumulator  202  value to zero. In one embodiment, the initialize instruction can also specify to load the accumulator  202  with the corresponding word of a row of the data RAM  122  or weight RAM  124  whose address is specified by the instruction. The initialize instruction also loads configuration values into the control register  127 , as described in more detail below with respect to  FIGS. 29A and 29B . For example, the width of the data word  207  and weight word  209  may be loaded, which may be used by the ALU  204  to determine the sizes of the operations performed by the circuits and may affect the result  215  stored in the accumulator  202 . In one embodiment, the NPU  126  includes a circuit that saturates the ALU  204  output  215  before being stored in the accumulator  202 , and the initialize instruction loads a configuration value into the circuit to affect the saturation. In one embodiment, the accumulator  202  may also be cleared to a zero value by so specifying in an ALU function instruction (e.g., multiply-accumulate instruction at address  1 ) or an output instruction, such as the write AFU output instruction at address  4 . 
     The second row, at address  1 , specifies a multiply-accumulate instruction that instructs the 512 NPUs  126  to load a respective data word from a row of the data RAM  122  and to load a respective weight word from a row of the weight RAM  124 , and to perform a first multiply-accumulate operation on the data word input  207  and weight word input  206 , which is accumulated with the initialized accumulator  202  zero value. More specifically, the instruction instructs the sequencer  128  to generate a value on the control input  213  to select the data word input  207 . In the example of  FIG. 4 , the specified data RAM  122  row is row  17 , and the specified weight RAM  124  row is row  0 , which instructs the sequencer  128  to output a data RAM address  123  value of 17 and to output a weight RAM address  125  value of 0. Consequently, the 512 data words from row  17  of the data RAM  122  are provided to the corresponding data input  207  of the 512 NPUs  126  and the 512 weight words from row  0  of the weight RAM  124  are provided to the corresponding weight input  206  of the 512 NPUs  126 . 
     The third row, at address  2 , specifies a multiply-accumulate rotate instruction with a count of 511, which instructs each of the 512 NPUs  126  to perform 511 multiply-accumulate operations. The instruction instructs the 512 NPUs  126  that the data word  209  input to the ALU  204  for each of the 511 multiply-accumulate operations is to be the rotated value  211  from the adjacent NPU  126 . That is, the instruction instructs the sequencer  128  to generate a value on the control input  213  to select the rotated value  211 . Additionally, the instruction instructs the 512 NPUs  126  to load a respective weight word for each of the 511 multiply-accumulate operations from the “next” row of the weight RAM  124 . That is, the instruction instructs the sequencer  128  to increment the weight RAM address  125  by one relative to its value in the previous clock cycle, which in the example would be row  1  on the first clock cycle of the instruction, row  2  on the next clock cycle, row  3  on the next clock cycle, and so forth to row  511  on the 511 th  clock cycle. For each of the 511 multiply-accumulate operations, the product of the rotated input  211  and weight word input  206  is accumulated with the previous value in the accumulator  202 . The 512 NPUs  126  perform the 511 multiply-accumulate operations in 511 clock cycles, in which each NPU  126  performs a multiply-accumulate operation on a different data word from row  17  of the data RAM  122 —namely, the data word operated on by the adjacent NPU  126  in the previous cycle—and a different weight word associated with the data word, which is conceptually a different connection input to the neuron. In the example, it is assumed that the number of connection inputs to each NPU  126  (neuron) is 512, thus involving 512 data words and 512 weight words. Once the last iteration of the multiply-accumulate rotate instruction of row  2  is performed, the accumulator  202  contains the sum of products for all 512 of the connection inputs. In one embodiment, rather than having a separate instruction for each type of ALU operation (e.g., multiply-accumulate, maximum of accumulator and weight word, etc. as described above), the NPU  126  instruction set includes an “execute” instruction that instructs the ALU  204  to perform an ALU operation specified by the initialize NPU instruction, such as specified in the ALU function  2926  of  FIG. 29A . 
     The fourth row, at address  3 , specifies an activation function instruction. The activation function instruction instructs the AFU  212  to perform the specified activation function on the accumulator  202  value  217  to generate the result  133 . The activation functions according to one embodiment are described in more detail below. 
     The fifth row, at address  4 , specifies a write AFU output instruction that instructs the 512 NPUs  126  to write back their AFU  212  output as results  133  to a row of the data RAM  122 , which is row  16  in the example. That is, the instruction instructs the sequencer  128  to output a data RAM address  123  value of 16 and a write command (in contrast to a read command in the case of the multiply-accumulate instruction at address  1 ). Preferably the execution of the write AFU output instruction may be overlapped with the execution of other instructions in a pipelined nature such that the write AFU output instruction effectively executes in a single clock cycle. 
     Preferably, each NPU  126  is configured as a pipeline that includes the various functional elements, e.g., the mux-reg  208  (and mux-reg  705  of  FIG. 7 ), ALU  204 , accumulator  202 , AFU  212 , mux  802  (of  FIG. 8 ), row buffer  1104  and AFUs  1112  (of  FIG. 11 ), etc., some of which may themselves be pipelined. In addition to the data words  207  and weight words  206 , the pipeline receives the instructions from the program memory  129 . The instructions flow down the pipeline and control the various functional units. In an alternate embodiment, the activation function instruction is not included in the program. Rather, the initialize NPU instruction specifies the activation function to be performed on the accumulator  202  value  217 , and a value indicating the specified activation function is saved in a configuration register for later use by the AFU  212  portion of the pipeline once the final accumulator  202  value  217  has been generated, i.e., once the last iteration of the multiply-accumulate rotate instruction at address  2  has completed. Preferably, for power savings purposes, the AFU  212  portion of the pipeline is inactive until the write AFU output instruction reaches it, at which time the AFU  212  is powered up and performs the activation function on the accumulator  202  output  217  specified by the initialize instruction. 
     Referring now to  FIG. 5 , a timing diagram illustrating the execution of the program of  FIG. 4  by the NNU  121  is shown. Each row of the timing diagram corresponds to a successive clock cycle indicated in the first column. Each of the other columns corresponds to a different one of the 512 NPUs  126  and indicates its operation. For simplicity and clarity of illustration, the operations only for NPUs  0 ,  1  and  511  are shown. 
     At clock  0 , each of the 512 NPUs  126  performs the initialization instruction of  FIG. 4 , which is illustrated in  FIG. 5  by the assignment of a zero value to the accumulator  202 . 
     At clock  1 , each of the 512 NPUs  126  performs the multiply-accumulate instruction at address  1  of  FIG. 4 . NPU  0  accumulates the accumulator  202  value (which is zero) with the product of data RAM  122  row  17  word  0  and weight RAM  124  row  0  word  0 ; NPU  1  accumulates the accumulator  202  value (which is zero) with the product of data RAM  122  row  17  word  1  and weight RAM  124  row  0  word  1 ; and so forth to NPU  511  accumulates the accumulator  202  value (which is zero) with the product of data RAM  122  row  17  word  511  and weight RAM  124  row  0  word  511 , as shown. 
     At clock  2 , each of the 512 NPUs  126  performs a first iteration of the multiply-accumulate rotate instruction at address  2  of  FIG. 4 . NPU  0  accumulates the accumulator  202  value with the product of the rotated data word  211  received from the mux-reg  208  output  209  of NPU  511  (which was data word  511  received from the data RAM  122 ) and weight RAM  124  row  1  word  0 ; NPU  1  accumulates the accumulator  202  value with the product of the rotated data word  211  received from the mux-reg  208  output  209  of NPU  0  (which was data word  0  received from the data RAM  122 ) and weight RAM  124  row  1  word  1 ; and so forth to NPU  511  accumulates the accumulator  202  value with the product of the rotated data word  211  received from the mux-reg  208  output  209  of NPU  510  (which was data word  510  received from the data RAM  122 ) and weight RAM  124  row  1  word  511 , as shown. 
     At clock  3 , each of the 512 NPUs  126  performs a second iteration of the multiply-accumulate rotate instruction at address  2  of  FIG. 4 . NPU  0  accumulates the accumulator  202  value with the product of the rotated data word  211  received from the mux-reg  208  output  209  of NPU  511  (which was data word  510  received from the data RAM  122 ) and weight RAM  124  row  2  word  0 ; NPU  1  accumulates the accumulator  202  value with the product of the rotated data word  211  received from the mux-reg  208  output  209  of NPU  0  (which was data word  511  received from the data RAM  122 ) and weight RAM  124  row  2  word  1 ; and so forth to NPU  511  accumulates the accumulator  202  value with the product of the rotated data word  211  received from the mux-reg  208  output  209  of NPU  510  (which was data word  509  received from the data RAM  122 ) and weight RAM  124  row  2  word  511 , as shown. As indicated by the ellipsis of  FIG. 5 , this continues for each of the following  509  clock cycles until . . . . 
     At clock  512 , each of the 512 NPUs  126  performs a 511 th  iteration of the multiply-accumulate rotate instruction at address  2  of  FIG. 4 . NPU  0  accumulates the accumulator  202  value with the product of the rotated data word  211  received from the mux-reg  208  output  209  of NPU  511  (which was data word  1  received from the data RAM  122 ) and weight RAM  124  row  511  word  0 ; NPU  1  accumulates the accumulator  202  value with the product of the rotated data word  211  received from the mux-reg  208  output  209  of NPU  0  (which was data word  2  received from the data RAM  122 ) and weight RAM  124  row  511  word  1 ; and so forth to NPU  511  accumulates the accumulator  202  value with the product of the rotated data word  211  received from the mux-reg  208  output  209  of NPU  510  (which was data word  0  received from the data RAM  122 ) and weight RAM  124  row  511  word  511 , as shown. In one embodiment, multiple clock cycles are required to read the data words and weight words from the data RAM  122  and weight RAM  124  to perform the multiply-accumulate instruction at address  1  of  FIG. 4 ; however, the data RAM  122  and weight RAM  124  and NPUs  126  are pipelined such that once the first multiply-accumulate operation is begun (e.g., as shown during clock  1  of  FIG. 5 ), the subsequent multiply accumulate operations (e.g., as shown during clocks  2 - 512 ) are begun in successive clock cycles. Preferably, the NPUs  126  may briefly stall in response to an access of the data RAM  122  and/or weight RAM  124  by an architectural instruction, e.g., MTNN or MFNN instruction (described below with respect to  FIGS. 14 and 15 ) or a microinstruction into which the architectural instructions are translated. 
     At clock  513 , the AFU  212  of each of the 512 NPUs  126  performs the activation function instruction at address  3  of  FIG. 4 . Finally, at clock  514 , each of the 512 NPUs  126  performs the write AFU output instruction at address  4  of  FIG. 4  by writing back its result  133  to its corresponding word of row  16  of the data RAM  122 , i.e., the result  133  of NPU  0  is written to word  0  of the data RAM  122 , the result  133  of NPU  1  is written to word  1  of the data RAM  122 , and so forth to the result  133  of NPU  511  is written to word  511  of the data RAM  122 . The operation described above with respect to  FIG. 5  is also shown in block diagram form in  FIG. 6A . 
     Referring now to  FIG. 6A , a block diagram illustrating the NNU  121  of  FIG. 1  to execute the program of  FIG. 4  is shown. The NNU  121  includes the 512 NPUs  126 , the data RAM  122  that receives its address input  123 , and the weight RAM  124  that receives its address input  125 . Although not shown, on clock  0  the 512 NPUs  126  perform the initialization instruction. As shown, on clock  1 , the 512 16-bit data words of row  17  are read out of the data RAM  122  and provided to the 512 NPUs  126 . On clocks  1  through  512 , the 512 16-bit weight words of rows  0  through  511 , respectively, are read out of the weight RAM  124  and provided to the 512 NPUs  126 . Although not shown, on clock  1 , the 512 NPUs  126  perform their respective multiply-accumulate operations on the loaded data words and weight words. On clocks  2  through  512 , the mux-regs  208  of the 512 NPUs  126  operate as a 512 16-bit word rotater to rotate the previously loaded data words of row  17  of the data RAM  122  to the adjacent NPU  126 , and the NPUs  126  perform the multiply-accumulate operation on the respective rotated data word and the respective weight word loaded from the weight RAM  124 . Although not shown, on clock  513 , the 512 AFUs  212  perform the activation instruction. On clock  514 , the 512 NPUs  126  write back their respective 512 16-bit results  133  to row  16  of the data RAM  122 . 
     As may be observed, the number clocks required to generate the result words (neuron outputs) produced and written back to the data RAM  122  or weight RAM  124  is approximately the square root of the number of data inputs (connections) received by the current layer of the neural network. For example, if the currently layer has 512 neurons that each has 512 connections from the previous layer, the total number of connections is 256K and the number of clocks required to generate the results for the current layer is slightly over 512. Thus, the NNU  121  provides extremely high performance for neural network computations. 
     Referring now to  FIG. 6B , a flowchart illustrating operation of the processor  100  of  FIG. 1  to perform an architectural program that uses the NNU  121  to perform multiply-accumulate-activation function computations classically associated with neurons of hidden layers of an artificial neural network such as performed by the program of  FIG. 4 , for example. The example of  FIG. 6B  assumes computations for 4 hidden layers (signified by the initialization of the NUM_LAYERS variable at block  602 ), each having 512 neurons each fully connected to 512 neurons of the previous layer (by use of the program of  FIG. 4 ). However, it should be understood that these numbers of layers and neurons are selected for illustration purposes, and the NNU  121  may be employed to perform similar computations for different numbers of hidden layers and different numbers of neurons per layer and for non-fully connected neurons. In one embodiment, the weight values may be set to zero for non-existent neurons in a layer or for non-existent connections to a neuron. Preferably, the architectural program writes a first set of weights to the weight RAM  124  and starts the NNU  121 , and while the NNU  121  is performing the computations associated with the first layer, the architectural program writes a second set of weights to the weight RAM  124  so that as soon as the NNU  121  completes the computations for the first hidden layer, the NNU  121  can start the computations for the second layer. In this manner, the architectural program ping-pongs back and forth between the two regions of the weight RAM  124  in order to keep the NNU  121  fully utilized. Flow begins at block  602 . 
     At block  602 , the processor  100 , i.e., the architectural program running on the processor  100 , writes the input values to the current hidden layer of neurons to the data RAM  122 , e.g., into row  17  of the data RAM  122 , as shown and described with respect to  FIG. 6A . Alternatively, the values may already be in row  17  of the data RAM  122  as results  133  of the operation of the NNU  121  for a previous layer (e.g., convolution, pooling or input layer). Additionally, the architectural program initializes a variable N to a value of 1. The variable N denotes the current layer of the hidden layers being processed by the NNU  121 . Additionally, the architectural program initializes a variable NUM_LAYERS to a value of 4 since there are 4 hidden layers in the example. Flow proceeds to block  604 . 
     At block  604 , the processor  100  writes the weight words for layer  1  to the weight RAM  124 , e.g., to rows  0  through  511 , as shown in  FIG. 6A . Flow proceeds to block  606 . 
     At block  606 , the processor  100  writes a multiply-accumulate-activation function program (e.g., of  FIG. 4 ) to the NNU  121  program memory  129 , using MTNN  1400  instructions that specify a function  1432  to write the program memory  129 . The processor  100  then starts the NNU program using a MTNN  1400  instruction that specifies a function  1432  to start execution of the program. Flow proceeds to decision block  608 . 
     At decision block  608 , the architectural program determines whether the value of variable N is less than NUM_LAYERS. If so, flow proceeds to block  612 ; otherwise, flow proceeds to block  614 . 
     At block  612 , the processor  100  writes the weight words for layer N+1 to the weight RAM  124 , e.g., to rows  512  through  1023 . Thus, advantageously, the architectural program writes the weight words for the next layer to the weight RAM  124  while the NNU  121  is performing the hidden layer computations for the current layer so that the NNU  121  can immediately start performing the hidden layer computations for the next layer once the computations for the current layer are complete, i.e., written to the data RAM  122 . Flow proceeds to block  614 . 
     At block  614 , the processor  100  determines that the currently running NNU program (started at block  606  in the case of layer  1 , and started at block  618  in the case of layers  2  through  4 ) has completed. Preferably, the processor  100  determines this by executing a MFNN  1500  instruction to read the NNU  121  status register  127 . In an alternate embodiment, the NNU  121  generates an interrupt to indicate it has completed the multiply-accumulate-activation function layer program. Flow proceeds to decision block  616 . 
     At decision block  616 , the architectural program determines whether the value of variable N is less than NUM_LAYERS. If so, flow proceeds to block  618 ; otherwise, flow proceeds to block  622 . 
     At block  618 , the processor  100  updates the multiply-accumulate-activation function program so that it can perform the hidden layer computations for layer N+1. More specifically, the processor  100  updates the data RAM  122  row value of the multiply-accumulate instruction at address  1  of  FIG. 4  to the row of the data RAM  122  to which the previous layer wrote its results (e.g., to row  16 ) and also updates the output row (e.g., to row  15 ). The processor  100  then starts the updated NNU program. Alternatively, the program of  FIG. 4  specifies the same row in the output instruction of address  4  as the row specified in the multiply-accumulate instruction at address  1  (i.e., the row read from the data RAM  122 ). In this embodiment, the current row of input data words is overwritten (which is acceptable as long as the row of data words is not needed for some other purpose, because the row of data words has already been read into the mux-regs  208  and is being rotated among the NPUs  126  via the N-word rotater). In this case, no update of the NNU program is needed at block  618 , but only a re-start of it. Flow proceeds to block  622 . 
     At block  622 , the processor  100  reads the results of the NNU program from the data RAM  122  for layer N. However, if the results are simply to be used by the next layer, then the architectural program may not need to read the results from the data RAM  122 , but instead leave them in the data RAM  122  for the next hidden layer computations. Flow proceeds to decision block  624 . 
     At decision block  624 , the architectural program determines whether the value of variable N is less than NUM_LAYERS. If so, flow proceeds to block  626 ; otherwise, flow ends. 
     At block  626 , the architectural program increments N by one. Flow returns to decision block  608 . 
     As may be determined from the example of  FIG. 6B , approximately every 512 clock cycles, the NPUs  126  read once from and write once to the data RAM  122  (by virtue of the operation of the NNU program of  FIG. 4 ). Additionally, the NPUs  126  read the weight RAM  124  approximately every clock cycle to read a row of the weight words. Thus, the entire bandwidth of the weight RAM  124  is consumed by the hybrid manner in which the NNU  121  performs the hidden layer operation. Additionally, assuming an embodiment that includes a write and read buffer such as the buffer  1704  of  FIG. 17 , concurrently with the NPU  126  reads, the processor  100  writes the weight RAM  124  such that the buffer  1704  performs one write to the weight RAM  124  approximately every 16 clock cycles to write the weight words. Thus, in a single-ported embodiment of the weight RAM  124  (such as described with respect to  FIG. 17 ), approximately every 16 clock cycles, the NPUs  126  must be stalled from reading the weight RAM  124  to enable the buffer  1704  to write the weight RAM  124 . However, in an embodiment in which the weight RAM  124  is dual-ported, the NPUs  126  need not be stalled. 
     Referring now to  FIG. 7 , a block diagram illustrating a NPU  126  of  FIG. 1  according to an alternate embodiment is shown. The NPU  126  of  FIG. 7  is similar in many respects to the NPU  126  of  FIG. 2 . However, the NPU  126  of  FIG. 7  additionally includes a second 2-input mux-reg  705 . The mux-reg  705  selects one of its inputs  206  or  711  to store in its register and then to provide on its output  203  on a subsequent clock cycle. Input  206  receives the weight word from the weight RAM  124 . The other input  711  receives the output  203  of the second mux-reg  705  of the adjacent NPU  126 . Preferably, the mux-reg  705  input  711  of NPU J receives the mux-reg  705  output  203  of NPU  126  instance J−1, and the output of NPU J is provided to the mux-reg  705  input  711  of NPU  126  instance J+1. In this manner, the mux-regs  705  of the N NPUs  126  collectively operate as an N-word rotater, similar to the manner described above with respect to  FIG. 3 , but for the weight words rather than for the data words. A control input  713  controls which of the two inputs the mux-reg  705  selects to store in its register and that is subsequently provided on the output  203 . 
     Including the mux-regs  208  and/or mux-regs  705  (as well as the mux-regs of other embodiments, such as of  FIGS. 18 and 23 ) to effectively form a large rotater that rotates the data/weights of a row received from the data RAM  122  and/or weight RAM  124  has an advantage that the NNU  121  does not require an extremely large mux that would otherwise be required between the data RAM  122  and/or weight RAM  124  in order to provide the necessary data/weight words to the appropriate NNU  121 . 
     Writing Back Accumulator Values in Addition to Activation Function Result 
     In some applications, it is useful for the processor  100  to receive back (e.g., to the media registers  118  via the MFNN instruction of  FIG. 15 ) the raw accumulator  202  value  217  upon which instructions executing on other execution units  112  can perform computations. For example, in one embodiment, in order to reduce the complexity of the AFU  212 , it is not configured to perform the softmax activation function. Consequently, the NNU  121  may output the raw accumulator  202  value  217 , or a subset thereof, to the data RAM  122  or weight RAM  124 , which the architectural program subsequently reads from the data RAM  122  or weight RAM  124  and performs computations on the raw values. However, use of the raw accumulator  202  value  217  is not limited to performance of softmax, and other uses are contemplated. 
     Referring now to  FIG. 8 , a block diagram illustrating a NPU  126  of  FIG. 1  according to an alternate embodiment is shown. The NPU  126  of  FIG. 8  is similar in many respects to the NPU  126  of  FIG. 2 . However, the NPU  126  of  FIG. 8  includes a multiplexer (mux)  802  in the AFU  212  that has a control input  803 . The width (in bits) of the accumulator  202  is greater than the width of a data word. The mux  802  has multiple inputs that receive data word-width portions of the accumulator  202  output  217 . In one embodiment, the width of the accumulator  202  is 41 bits and the NPU  126  is configured to output a result word  133  that is 16 bits; thus, for example, the mux  802  (or mux  3032  and/or mux  3037  of  FIG. 30 ) includes three inputs that receive bits [15:0], bits [31:16], and bits [47:32] of the accumulator  202  output  217 , respectively. Preferably, output bits not provided by the accumulator  202  (e.g., bits [47:41]) are forced to zero value bits. 
     The sequencer  128  generates a value on the control input  803  to control the mux  802  to select one of the words (e.g., 16 bits) of the accumulator  202  in response to a write ACC instruction such as the write ACC instructions at addresses  3  through  5  of  FIG. 9  described below. Preferably, the mux  802  also has one or more inputs that receive the output of activation function circuits (e.g., elements  3022 ,  3024 ,  3026 ,  3018 ,  3014 , and  3016  of  FIG. 30 ) that generate outputs that are the width of a data word. The sequencer  128  generates a value on the control input  803  to control the mux  802  to select one of the activation function circuit outputs, rather than one of the words of the accumulator  202 , in response to an instruction such as the write AFU output instruction at address  4  of  FIG. 4 . 
     Referring now to  FIG. 9 , a table illustrating a program for storage in the program memory  129  of and execution by the NNU  121  of  FIG. 1  is shown. The example program of  FIG. 9  is similar in many respects to the program of  FIG. 4 . Specifically, the instructions at addresses  0  through  2  are identical. However, the instructions at addresses  3  and  4  of  FIG. 4  are replaced in  FIG. 9  by write ACC instructions that instruct the 512 NPUs  126  to write back their accumulator  202  output  217  as results  133  to three rows of the data RAM  122 , which is rows  16  through  18  in the example. That is, the write ACC instruction instructs the sequencer  128  to output a data RAM address  123  value of 16 and a write command in a first clock cycle, to output a data RAM address  123  value of 17 and a write command in a second clock cycle, and to output a data RAM address  123  value of 18 and a write command in a third clock cycle. Preferably the execution of the write ACC instruction may be overlapped with the execution of other instructions such that the write ACC instruction effectively executes in three clock cycles, one for each row written to in the data RAM  122 . In one embodiment, the user specifies values of the activation function  2934  and output command  2956  fields in the control register  127  (of  FIG. 29A ) to accomplish the writing of the desired portions of the accumulator  202  to the data RAM  122  or weight RAM  124 . Alternatively, rather than writing back the entire contents of the accumulator  202 , the write ACC instruction may optionally write back a subset of the accumulator  202 . In one embodiment, a canonical form of the accumulator  202  may written back, as described in more detail below with respect to  FIGS. 29 through 31 . 
     Referring now to  FIG. 10 , a timing diagram illustrating the execution of the program of  FIG. 9  by the NNU  121  is shown. The timing diagram of  FIG. 10  is similar to the timing diagram of  FIG. 5 , and clocks  0  through  512  are the same. However, at clocks  513 - 515 , the AFU  212  of each of the 512 NPUs  126  performs one of the write ACC instructions at addresses  3  through  5  of  FIG. 9 . Specifically, at clock  513 , each of the 512 NPUs  126  writes back as its result  133  to its corresponding word of row  16  of the data RAM  122  bits [15:0] of the accumulator  202  output  217 ; at clock  514 , each of the 512 NPUs  126  writes back as its result  133  to its corresponding word of row  17  of the data RAM  122  bits [31:16] of the accumulator  202  output  217 ; and at clock  515 , each of the 512 NPUs  126  writes back as its result  133  to its corresponding word of row  18  of the data RAM  122  bits [40:32] of the accumulator  202  output  217 . Preferably, bits [47:41] are forced to zero values. 
     Shared AFUs 
     Referring now to  FIG. 11 , a block diagram illustrating an embodiment of the NNU  121  of  FIG. 1  is shown. In the embodiment of  FIG. 11 , a neuron is split into two portions, the activation function unit portion and the ALU portion (which also includes the shift register portion), and each activation function unit portion is shared by multiple ALU portions. In  FIG. 11 , the ALU portions are referred to as NPUs  126  and the shared activation function unit portions are referred to as AFUs  1112 . This is in contrast to the embodiment of  FIG. 2 , for example, in which each neuron includes its own AFU  212 . Hence, for example, in one embodiment the NPUs  126  (ALU portions) of the embodiment of  FIG. 11  include the accumulator  202 , ALU  204 , mux-reg  208  and register  205  of  FIG. 2 , but not the AFU  212 . In the embodiment of  FIG. 11 , the NNU  121  includes 512 NPUs  126  as an example; however, other embodiments with other numbers of NPUs  126  are contemplated. In the example of  FIG. 11 , the 512 NPUs  126  are grouped into 64 groups of eight NPUs  126  each, referred to as groups  0  through  63  in  FIG. 11 . 
     The NNU  121  also includes a row buffer  1104  and a plurality of shared AFUs  1112  coupled between the NPUs  126  and the row buffer  1104 . The row buffer  1104  is the same width (in bits) as a row of the data RAM  122  or weight RAM  124 , e.g., 512 words. There is one AFU  1112  per NPU  126  group, i.e., each AFU  1112  has a corresponding NPU  126  group; thus, in the embodiment of  FIG. 11  there are 64 AFUs  1112  that correspond to the 64 NPU  126  groups. Each of the eight NPUs  126  in a group shares the corresponding AFU  1112 . Other embodiments with different numbers of AFUs  1112  and NPUs  126  per group are contemplated. For example, other embodiments are contemplated in which two or four or sixteen NPUs  126  in a group share an AFU  1112 . 
     A motivation for sharing AFUs  1112  is to reduce the size of the NNU  121 . The size reduction is obtained at the cost of a performance reduction. That is, it may take several clocks longer, depending upon the sharing ratio, to generate the results  133  for the entire array of NPUs  126 , as demonstrated in  FIG. 12  below, for example, in which seven additional clock cycles are required because of the 8:1 sharing ratio. However, generally speaking, the additional number of clocks (e.g., 7) is relatively small compared to the number of clocks required to generated the accumulated sum (e.g., 512 clocks for a layer that has 512 connections per neuron). Hence, the relatively small performance impact (e.g., one percent increase in computation time) may be a worthwhile tradeoff for the reduced size of the NNU  121 . 
     In one embodiment, each of the NPUs  126  includes an AFU  212  that performs relatively simple activation functions, thus enabling the simple AFUs  212  to be relatively small and therefore included in each NPU  126 ; whereas, the shared, or complex, AFUs  1112  perform relatively complex activation functions and are thus relatively significantly larger than the simple AFUs  212 . In such an embodiment, the additional clock cycles are only required when a complex activation function is specified that requires sharing of a complex AFU  1112 , but not when an activation function is specified that the simple AFU  212  is configured to perform. 
     Referring now to  FIGS. 12 and 13 , two timing diagrams illustrating the execution of the program of  FIG. 4  by the NNU  121  of  FIG. 11  is shown. The timing diagram of  FIG. 12  is similar to the timing diagram of  FIG. 5 , and clocks  0  through  512  are the same. However, at clock  513 , operation is different than described in the timing diagram of  FIG. 5  because the NPUs  126  of  FIG. 11  share the AFUs  1112 ; that is, the NPUs  126  of a group share the AFU  1112  associated with the group, and  FIG. 11  illustrates the sharing. 
     Each row of the timing diagram of  FIG. 13  corresponds to a successive clock cycle indicated in the first column. Each of the other columns corresponds to a different one of the 64 AFUs  1112  and indicates its operation. For simplicity and clarity of illustration, the operations only for AFUs  0 ,  1  and  63  are shown. The clock cycles of  FIG. 13  correspond to the clock cycles of  FIG. 12  but illustrate the sharing of the AFUs  1112  by the NPUs  126  in a different manner. At clocks  0 - 512 , each of the 64 AFUs  1112  is inactive, as shown in  FIG. 13 , while the NPUs  126  perform the initialize NPU and multiply-accumulate and multiply-accumulate rotate instructions. 
     As shown in both  FIGS. 12 and 13 , at clock  513 , AFU  0  (the AFU  1112  associated with group  0 ) begins to perform the specified activation function on the accumulator  202  value  217  of NPU  0 , which is the first NPU  126  in group  0 , and the output of AFU  0  will be stored to row buffer  1104  word  0 . Also at clock  513 , each of the AFUs  1112  begins to perform the specified activation function on the accumulator  202  of the first NPU  126  in its corresponding group of NPUs  126 . Thus, in clock  513 , as shown in  FIG. 13 , AFU  0  begins to perform the specified activation function on the accumulator  202  of NPU  0  to generate a result that will be stored to row buffer  1104  word  0 ; AFU  1  begins to perform the specified activation function on the accumulator  202  of NPU  8  to generate a result that will be stored to row buffer  1104  word  8 ; and so forth to AFU  63  begins to perform the specified activation function on the accumulator  202  of NPU  504  to generate a result that will be stored to row buffer  1104  word  504 . 
     At clock  514 , AFU  0  (the AFU  1112  associated with group  0 ) begins to perform the specified activation function on the accumulator  202  value  217  of NPU  1 , which is the second NPU  126  in group  0 , and the output of AFU  0  will be stored to row buffer  1104  word  1 , as shown. Also at clock  514 , each of the AFUs  1112  begins to perform the specified activation function on the accumulator  202  of the second NPU  126  in its corresponding group of NPUs  126 . Thus, in clock  514 , as shown in  FIG. 13 , AFU  0  begins to perform the specified activation function on the accumulator  202  of NPU  1  to generate a result that will be stored to row buffer  1104  word  1 ; AFU  1  begins to perform the specified activation function on the accumulator  202  of NPU  9  to generate a result that will be stored to row buffer  1104  word  9 ; and so forth to AFU  63  begins to perform the specified activation function on the accumulator  202  of NPU  505  to generate a result that will be stored to row buffer  1104  word  505 . This pattern continues until at clock cycle  520 , AFU  0  (the AFU  1112  associated with group  0 ) begins to perform the specified activation function on the accumulator  202  value  217  of NPU  7 , which is the eighth (last) NPU  126  in group  0 , and the output of AFU  0  will be stored to row buffer  1104  word  7 , as shown. Also at clock  520 , each of the AFUs  1112  begins to perform the specified activation function on the accumulator  202  of the eighth NPU  126  in its corresponding group of NPUs  126 . Thus, in clock  520 , as shown in  FIG. 13 , AFU  0  begins to perform the specified activation function on the accumulator  202  of NPU  7  to generate a result that will be stored to row buffer  1104  word  7 ; AFU  1  begins to perform the specified activation function on the accumulator  202  of NPU  15  to generate a result that will be stored to row buffer  1104  word  15 ; and so forth to AFU  63  begins to perform the specified activation function on the accumulator  202  of NPU  511  to generate a result that will be stored to row buffer  1104  word  511 . 
     At clock  521 , once all 512 results associated with the 512 NPUs  126  have been generated and written to the row buffer  1104 , the row buffer  1104  begins to write its contents to the data RAM  122  or weight RAM  124 . In this fashion, the AFU  1112  of each of the 64 groups of NPUs  126  performs a portion of the activation function instruction at address  3  of  FIG. 4 . 
     Embodiments such as that of  FIG. 11  that share AFUs  1112  among groups of ALUs  204  may be particularly advantageous in conjunction with integer ALUs  204 , as described more below, e.g., with respect to  FIGS. 29A through 33 . 
     MTNN and MFNN Architectural Instructions 
     Referring now to  FIG. 14 , a block diagram illustrating a move to neural network (MTNN) architectural instruction  1400  and its operation with respect to portions of the NNU  121  of  FIG. 1  is shown. The MTNN instruction  1400  includes an opcode field  1402 , a src 1  field  1404 , a src 2  field  1406 , a gpr field  1408 , and an immediate field  1412 . The MTNN instruction  1400  is an architectural instruction, i.e., it is included in the instruction set architecture of the processor  100 . Preferably, the instruction set architecture associates a predetermined value of the opcode field  1402  with the MTNN instruction  1400  to distinguish it from other instructions in the instruction set architecture. The MTNN instruction  1400  opcode  1402  may or may not include prefixes, such as are common, for example, in the x86 architecture. 
     The immediate field  1412  provides a value that specifies a function  1432  to control logic  1434  of the NNU  121 . Preferably, the function  1432  is provided as an immediate operand of a microinstruction  105  of  FIG. 1 . The functions  1432  that may be performed by the NNU  121  include, but are not limited to, writing to the data RAM  122 , writing to the weight RAM  124 , writing to the program memory  129 , writing to the control register  127 , starting execution of a program in the program memory  129 , pausing the execution of a program in the program memory  129 , request notification (e.g., interrupt) of completion of the execution of a program in the program memory  129 , and resetting the NNU  121 . Preferably, the NNU instruction set includes an instruction whose result indicates the NNU program is complete. Alternatively, the NNU instruction set includes an explicit generate interrupt instruction. Preferably, resetting the NNU  121  includes effectively forcing the NNU  121  back to a reset state (e.g., internal state machines are cleared and set to an idle state), except the contents of the data RAM  122 , weight RAM  124 , program memory  129  are left intact. Additionally, internal registers such as the accumulator  202  are not affected by the reset function and must be explicitly cleared, e.g., by an initialize NPU instruction at address  0  of  FIG. 4 . In one embodiment, the function  1432  may include a direct execution function in which the first source register contains a micro-operation (see for example micro-operation  3418  of  FIG. 34 ). The direct execution function instructs the NNU  121  to directly execute the specified micro-operation. In this manner, an architectural program may directly control the NNU  121  to perform operations, rather than writing instructions to the program memory  129  and then instructing the NNU  121  to execute the instructions in the program memory or by executing an MTNN instruction  1400  (or an MFNN instruction  1500  of  FIG. 15 ).  FIG. 14  illustrates an example of the function  1432  of writing to the data RAM  122 . 
     The gpr field  1408  specifies one of the GPR in the general purpose register file  116 . In one embodiment, each GPR is 64 bits. The general purpose register file  116  provides the value from the selected GPR to the NNU  121 , as shown, which uses the value as an address  1422 . The address  1422  selects a row of the memory specified in the function  1432 . In the case of the data RAM  122  or weight RAM  124 , the address  1422  additionally selects a chunk that is twice the size of a media register (e.g., 512 bits) location within the selected row. Preferably, the location is on a 512-bit boundary. In one embodiment, a multiplexer selects either the address  1422  (or address  1422  in the case of a MFNN instruction  1400  described below) or the address  123 / 125 / 131  from the sequencer  128  for provision to the data RAM  122 /weight RAM  124 /program memory  129 . In one embodiment, as described in more detail below, the data RAM  122  is dual-ported to allow the NPUs  126  to read/write the data RAM  122  concurrently with the media registers  118  reading/writing the data RAM  122 . In one embodiment, the weight RAM  124  is also dual-ported for a similar purpose. 
     The src 1  field  1404  and src 2  field  1406  each specify a media register in the media register file  118 . In one embodiment, each media register  118  is 256 bits. The media register file  118  provides the concatenated data (e.g., 512 bits) from the selected media registers to the data RAM  122  (or weight RAM  124  or program memory  129 ) for writing into the selected row  1428  specified by the address  1422  and into the location specified by the address  1422  within the selected row  1428 , as shown. Advantageously, by executing a series of MTNN instructions  1400  (and MFNN instructions  1400  described below), an architectural program executing on the processor  100  can populate rows of the data RAM  122  and rows of the weight RAM  124  and write a program to the program memory  129 , such as the programs described herein (e.g., of  FIGS. 4 and 9 ) to cause the NNU  121  to perform operations on the data and weights at extremely high speeds to accomplish an artificial neural network. In one embodiment, the architectural program directly controls the NNU  121  rather than writing a program into the program memory  129 . 
     In one embodiment, rather than specifying two source registers (e.g.,  1404  and  1406 ), the MTNN instruction  1400  specifies a start source register and a number of source registers, Q. This form of the MTNN instruction  1400  instructs the processor  100  to write the media register  118  specified as the start source register as well as the next Q−1 sequential media registers  118  to the NNU  121 , i.e., to the data RAM  122  or weight RAM  124  specified. Preferably, the instruction translator  104  translates the MTNN instruction  1400  into as many microinstructions as needed to write all the Q specified media registers  118 . For example, in one embodiment, when the MTNN instruction  1400  specifies a start source register as MR 4  and Q is 8, then the instruction translator  104  translates the MTNN instruction  1400  into four microinstructions, the first of which writes MR 4  and MR 5 , the second of which writes MR 6  and MR 7 , the third of which writes MR 8  and MR 9 , and the fourth of which writes MR 10  and MR 11 . In an alternate embodiment in which the data path from the media registers  118  to the NNU  121  is 1024 bits rather than 512, the instruction translator  104  translates the MTNN instruction  1400  into two microinstructions, the first of which writes MR 4  through MR 7 , and the second of which writes MR 8  through MR 11 . A similar embodiment is contemplated in which the MFNN instruction  1500  specifies a start destination register and a number of destination registers, to enable reading larger chunks of a row of the data RAM  122  or weight RAM  124  per MFNN instruction  1500  than a single media register  118 . 
     Referring now to  FIG. 15 , a block diagram illustrating a move from neural network (MFNN) architectural instruction  1500  and its operation with respect to portions of the NNU  121  of  FIG. 1  is shown. The MFNN instruction  1500  includes an opcode field  1502 , a dst field  1504 , a gpr field  1508 , and an immediate field  1512 . The MFNN instruction  1500  is an architectural instruction, i.e., it is included in the instruction set architecture of the processor  100 . Preferably, the instruction set architecture associates a predetermined value of the opcode field  1502  with the MFNN instruction  1500  to distinguish it from other instructions in the instruction set architecture. The MFNN instruction  1500  opcode  1502  may or may not include prefixes, such as are common, for example, in the x86 architecture. 
     The immediate field  1512  provides a value that specifies a function  1532  to the control logic  1434  of the NNU  121 . Preferably, the function  1532  is provided as an immediate operand of a microinstruction  105  of  FIG. 1 . The functions  1532  that may be performed by the NNU  121  include, but are not limited to, reading from the data RAM  122 , reading from the weight RAM  124 , reading from the program memory  129 , and reading from the status register  127 .  FIG. 15  illustrates an example of the function  1532  of reading from the data RAM  122 . 
     The gpr field  1508  specifies one of the GPR in the general purpose register file  116 . The general purpose register file  116  provides the value from the selected GPR to the NNU  121 , as shown, which uses the value as an address  1522  that operates in a manner similar to the address  1422  of  FIG. 14  to select a row of the memory specified in the function  1532  and, in the case of the data RAM  122  or weight RAM  124 , the address  1522  additionally selects a chunk that is the size of a media register (e.g., 256 bits) location within the selected row. Preferably, the location is on a 256-bit boundary. 
     The dst field  1504  specifies a media register in the media register file  118 . The media register file  118  receives the data (e.g., 256 bits) into the selected media register from the data RAM  122  (or weight RAM  124  or program memory  129 ) read from the selected row  1528  specified by the address  1522  and from the location specified by the address  1522  within the selected row  1528 , as shown. 
     NNU Internal RAM Port Configurations 
     Referring now to  FIG. 16 , a block diagram illustrating an embodiment of the data RAM  122  of  FIG. 1  is shown. The data RAM  122  includes a memory array  1606 , a read port  1602  and a write port  1604 . The memory array  1606  holds the data words and is preferably arranged as D rows of N words, as described above. In one embodiment, the memory array  1606  comprises an array of 64 horizontally arranged static RAM cells in which each cell is 128 bits wide and 64 tall to provide a 64 KB data RAM  122  that is 8192 bits wide and has 64 rows, and the data RAM  122  occupies approximately 0.2 square millimeters of die area. However, other embodiments are contemplated. 
     The read port  1602  is coupled, preferably in a multiplexed fashion, to the NPUs  126  and to the media registers  118 . (More precisely, the media registers  118  may be coupled to the read port  1602  via result busses that may also provide data to a reorder buffer and/or result forwarding busses to the other execution units  112 ). The NPUs  126  and media registers  118  share the read port  1602  to read the data RAM  122 . The write port  1604  is also coupled, preferably in a multiplexed fashion, to the NPUs  126  and to the media registers  118 . The NPUs  126  and media registers  118  shared the write port  1604  to write the data RAM  122 . Thus, advantageously, the media registers  118  can concurrently write to the data RAM  122  while the NPUs  126  are also reading from the data RAM  122 , or the NPUs  126  can concurrently write to the data RAM  122  while the media registers  118  are reading from the data RAM  122 . This may advantageously provide improved performance. For example, the NPUs  126  can read the data RAM  122  (e.g., to continue to perform calculations) while the media registers  118  write more data words to the data RAM  122 . For another example, the NPUs  126  can write calculation results to the data RAM  122  while the media registers  118  read calculation results from the data RAM  122 . In one embodiment, the NPUs  126  can write a row of calculation results to the data RAM  122  while the NPUs  126  also read a row of data words from the data RAM  122 . In one embodiment, the memory array  1606  is configured in banks. When the NPUs  126  access the data RAM  122 , all of the banks are activated to access an entire row of the memory array  1606 ; whereas, when the media registers  118  access the data RAM  122 , only the specified banks are activated. In one embodiment, each bank is 128 bits wide and the media registers  118  are 256 bits wide, hence two banks are activated per media register  118  access, for example. In one embodiment, one of the ports  1602 / 1604  is a read/write port. In one embodiment, both the ports  1602  and  1604  are read/write ports. 
     An advantage of the rotater capability of the NPUs  126  as described herein is that it facilitates the ability for the memory array  1606  of the data RAM  122  to have significantly fewer rows, and therefore be relatively much smaller, than might otherwise be needed in order to insure that the NPUs  126  are highly utilized, which requires the architectural program (via the media registers  118 ) to be able to continue to provide data to the data RAM  122  and to retrieve results from it while the NPUs  126  are performing computations. 
     Internal RAM Buffer 
     Referring now to  FIG. 17 , a block diagram illustrating an embodiment of the weight RAM  124  of  FIG. 1  and a buffer  1704  is shown. The weight RAM  124  includes a memory array  1706  and a port  1702 . The memory array  1706  holds the weight words and is preferably arranged as W rows of N words, as described above. In one embodiment, the memory array  1706  comprises an array of 128 horizontally arranged static RAM cells in which each cell is 64 bits wide and 2048 tall to provide a 2 MB weight RAM  124  that is 8192 bits wide and has 2048 rows, and the weight RAM  124  occupies approximately 2.4 square millimeters of die area. However, other embodiments are contemplated. 
     The port  1702  is coupled, preferably in a multiplexed fashion, to the NPUs  126  and to the buffer  1704 . The NPUs  126  and buffer  1704  read and write the weight RAM  124  via the port  1702 . The buffer  1704  is also coupled to the media registers  118  of  FIG. 1  such that the media registers  118  read and write the weight RAM  124  through the buffer  1704 . Thus, advantageously, the media registers  118  can concurrently write to or read from the buffer  1704  while the NPUs  126  are also reading from or writing to the weight RAM  124  (although preferably the NPUs  126  stall, if they are currently executing, to avoid accessing the weight RAM  124  while the buffer  1704  is accessing the weight RAM  124 ). This may advantageously provide improved performance, particularly since the reads/writes by the media registers  118  to the weight RAM  124  are relatively much smaller than the reads/writes by the NPUs  126  to the weight RAM  124 . For example, in one embodiment, the NPUs  126  read/write 8192 bits (one row) at a time, whereas the media registers  118  are 256 bits wide, and each MTNN instructions  1400  writes two media registers  118 , i.e., 512 bits. Thus, in the case where the architectural program executes sixteen MTNN instructions  1400  to populate the buffer  1704 , a conflict occurs between the NPUs  126  and the architectural program for access to the weight RAM  124  only less than approximately six percent of the time. In an alternate embodiment, the instruction translator  104  translates a MTNN instruction  1400  into two microinstructions  105 , each of which writes a single media register  118  to the buffer  1704 , in which case a conflict occurs between the NPUs  126  and the architectural program for access to the weight RAM  124  even less frequently. 
     In one embodiment that includes the buffer  1704 , writing to the weight RAM  124  by an architectural program requires multiple MTNN instructions  1400 . One or more MTNN instructions  1400  specify a function  1432  to write to specified chunks of the buffer  1704  followed by an MTNN instruction  1400  that specifies a function  1432  that instructs the NNU  121  to write the contents of the buffer  1704  to a specified row of the weight RAM  124 , where the size of a chunk is twice the number of bits of a media register  118  and chunks are naturally aligned within the buffer  1704 . In one embodiment, in each of the MTNN instructions  1400  that specify a function  1432  to write to specified chunks of the buffer  1704 , a bitmask is included that has a bit corresponding to each chunk of the buffer  1704 . The data from the two specified source registers  118  is written to each chunk of the buffer  1704  whose corresponding bit in the bitmask is set. This may be useful for repeated data values within a row of the weight RAM  124 . For example, in order to zero out the buffer  1704  (and subsequently a row of the weight RAM  124 ), the programmer may load the source registers with zero and set all bits of the bitmask. Additionally, the bitmask enables the programmer to only write to selected chunks of the buffer  1704  and thereby retain the previous data in the other chunks. 
     In one embodiment that includes the buffer  1704 , reading from the weight RAM  124  by an architectural program requires multiple MFNN instructions  1500 . An initial MFNN instruction  1500  specifies a function  1532  to load the buffer  1704  from a specified row of the weight RAM  124  followed by one or more MFNN instructions  1500  that specify a function  1532  to read a specified chunk of the buffer  1704  into the destination register, where the size of a chunk is the number of bits of a media register  118  and chunks are naturally aligned within the buffer  1704 . Other embodiments are contemplated in which the weight RAM  124  includes multiple buffers  1704  to further reduce contention between the NPUs  126  and the architectural program for access to the weight RAM  124  by increasing the number of accesses that can be made by the architectural program while the NPUs  126  are executing, which may increase the likelihood that the accesses by the buffers  1704  can be performed during clock cycles in which the NPUs  126  do not need to access the weight RAM  124 . 
     Although  FIG. 16  describes a dual-ported data RAM  122 , other embodiments are contemplated in which the weight RAM  124  is also dual-ported. Furthermore, although  FIG. 17  describes a buffer for use with the weight RAM  124 , other embodiments are contemplated in which the data RAM  122  also has an associated buffer similar to buffer  1704 . 
     Dynamically Configurable NPUs 
     Referring now to  FIG. 18 , a block diagram illustrating a dynamically configurable NPU  126  of  FIG. 1  is shown. The NPU  126  of  FIG. 18  is similar in many respects to the NPU  126  of  FIG. 2 . However, the NPU  126  of  FIG. 18  is dynamically configurable to operate in one of two different configurations. In a first configuration, the NPU  126  of  FIG. 18  operates similar to the NPU  126  of  FIG. 2 . That is, in the first configuration, referred to herein as “wide” configuration or “single” configuration, the ALU  204  of the NPU  126  performs operations on a single wide data word and a single wide weight word (e.g., 16 bits) to generate a single wide result. In contrast, in the second configuration, referred to herein as “narrow” configuration or “dual” configuration, the NPU  126  performs operations on two narrow data words and two respective narrow weight words (e.g., 8 bits) to generate two respective narrow results. In one embodiment, the configuration (wide or narrow) of the NPU  126  is made by the initialize NPU instruction (e.g., at address  0  of  FIG. 20 , described below). Alternatively, the configuration is made by an MTNN instruction whose function  1432  specifies to configure the NPU  126  to the configuration (wide or narrow). Preferably, configuration registers are populated by the program memory  129  instruction or the MTNN instruction that determine the configuration (wide or narrow). For example, the configuration register outputs are provided to the ALU  204 , AFU  212  and logic that generates the mux-reg control signal  213 . Generally speaking, the elements of the NPUs  126  of  FIG. 18  perform similar functions to their like-numbered elements of  FIG. 2  and reference should be made thereto for an understanding of  FIG. 18 . However, the embodiment of  FIG. 18  will now be described, including differences from  FIG. 2 . 
     The NPU  126  of  FIG. 18  includes two registers  205 A and  205 B, two 3-input mux-regs  208 A and  208 B, an ALU  204 , two accumulators  202 A and  202 B, and two AFUs  212 A and  212 B. Each of the registers  205 A/ 205 B is separately half the width (e.g., 8 bits) of register  205  of  FIG. 2 . Each of the registers  205 A/ 205 B receives a respective narrow weight word  206 A/ 206 B (e.g., 8 bits) from the weight RAM  124  and provides its output  203 A/ 203 B on a subsequent clock cycle to operand selection logic  1898  of the ALU  204 . When the NPU  126  is in a wide configuration, the registers  205 A/ 205 B effectively function together to receive a wide weight word  206 A/ 206 B (e.g., 16 bits) from the weight RAM  124 , similar to the manner of the register  205  of the embodiment of  FIG. 2 ; and when the NPU  126  is in a narrow configuration, the registers  205 A/ 205 B effectively function individually to each receive a narrow weight word  206 A/ 206 B (e.g., 8 bits) from the weight RAM  124  such that the NPU  126  is effectively two separate narrow NPUs. Nevertheless, the same output bits of the weight RAM  124  are coupled to and provided to the registers  205 A/ 205 B, regardless of the configuration of the NPU  126 . For example, the register  205 A of NPU  0  receives byte  0 , the register  205 B of NPU  0  receives byte  1 , the register  205 A of NPU  1  receives byte  2 , the register  205 A of NPU  1  receives byte  3 , and so forth to the register  205 B of NPU  511  receives byte  1023 . 
     Each of the mux-regs  208 A/ 208 B is separately half the width (e.g., 8 bits) of register  208  of  FIG. 2 . The mux-reg  208 A selects one of its inputs  207 A or  211 A or  1811 A to store in its register and then to provide on its output  209 A on a subsequent clock cycle, and the mux-reg  208 B selects one of its inputs  207 B or  211 B or  1811 B to store in its register and then to provide on its output  209 B on a subsequent clock cycle to the operand selection logic  1898 . The input  207 A receives a narrow data word (e.g., 8 bits) from the data RAM  122 , and the input  207 B receives a narrow data word from the data RAM  122 . When the NPU  126  is in a wide configuration, the mux-regs  208 A/ 208 B effectively function together to receive a wide data word  207 A/ 207 B (e.g., 16 bits) from the data RAM  122 , similar to the manner of the mux-reg  208  of the embodiment of  FIG. 2 ; and when the NPU  126  is in a narrow configuration, the mux-regs  208 A/ 208 B effectively function individually to each receive a narrow data word  207 A/ 207 B (e.g., 8 bits) from the data RAM  122  such that the NPU  126  is effectively two separate narrow NPUs. Nevertheless, the same output bits of the data RAM  122  are coupled to and provided to the mux-regs  208 A/ 208 B, regardless of the configuration of the NPU  126 . For example, the mux-reg  208 A of NPU  0  receives byte  0 , the mux-reg  208 B of NPU  0  receives byte  1 , the mux-reg  208 A of NPU  1  receives byte  2 , the mux-reg  208 A of NPU  1  receives byte  3 , and so forth to the mux-reg  208 B of NPU  511  receives byte  1023 . 
     The input  211 A receives the output  209 A of mux-reg  208 A of the adjacent NPU  126 , and the input  211 B receives the output  209 B of mux-reg  208 B of the adjacent NPU  126 . The input  1811 A receives the output  209 B of mux-reg  208 B of the adjacent NPU  126 , and the input  1811 B receives the output  209 A of mux-reg  208 A of the instant NPU  126 , as shown. The NPU  126  shown in  FIG. 18  is denoted NPU J from among the N NPUs  126  of  FIG. 1 . That is, NPU J is a representative instance of the N NPUs  126 . Preferably, the mux-reg  208 A input  211 A of NPU J receives the mux-reg  208 A output  209 A of NPU  126  instance J−1, the mux-reg  208 A input  1811 A of NPU J receives the mux-reg  208 B output  209 B of NPU  126  instance J−1, and the mux-reg  208 A output  209 A of NPU J is provided both to the mux-reg  208 A input  211 A of NPU  126  instance J+1 and to the mux-reg  208 B input  211 B of NPU  126  instance J; and the mux-reg  208 B input  211 B of NPU J receives the mux-reg  208 B output  209 B of NPU  126  instance J−1, the mux-reg  208 B input  1811 B of NPU J receives the mux-reg  208 A output  209 A of NPU  126  instance J, and the mux-reg  208 B output  209 B of NPU J is provided to both the mux-reg  208 A input  1811 A of NPU  126  instance J+1 and to the mux-reg  208 B input  211 B of NPU  126  instance J+1. 
     The control input  213  controls which of the three inputs each of the mux-regs  208 A/ 208 B selects to store in its respective register and that is subsequently provided on the respective outputs  209 A/ 209 B. When the NPU  126  is instructed to load a row from the data RAM  122  (e.g., as by the multiply-accumulate instruction at address  1  of  FIG. 20 , described below), regardless of whether the NPU  126  is in a wide or narrow configuration, the control input  213  controls each of the mux-regs  208 A/ 208 B to select a respective narrow data word  207 A/ 207 B (e.g., 8 bits) from the corresponding narrow word of the selected row of the data RAM  122 . 
     When the NPU  126  is instructed to rotate the previously received data row values (e.g., as by the multiply-accumulate rotate instruction at address  2  of  FIG. 20 , described below), if the NPU  126  is in a narrow configuration, the control input  213  controls each of the mux-regs  208 A/ 208 B to select the respective input  1811 A/ 1811 B. In this case, the mux-regs  208 A/ 208 B function individually effectively such that the NPU  126  is effectively two separate narrow NPUs. In this manner, the mux-regs  208 A and  208 B of the N NPUs  126  collectively operate as a 2N-narrow-word rotater, as described in more detail below with respect to  FIG. 19 . 
     When the NPU  126  is instructed to rotate the previously received data row values, if the NPU  126  is in a wide configuration, the control input  213  controls each of the mux-regs  208 A/ 208 B to select the respective input  211 A/ 211 B. In this case, the mux-regs  208 A/ 208 B function together effectively as if the NPU  126  is a single wide NPU  126 . In this manner, the mux-regs  208 A and  208 B of the N NPUs  126  collectively operate as an N-wide-word rotater, similar to the manner described with respect to  FIG. 3 . 
     The ALU  204  includes the operand selection logic  1898 , a wide multiplier  242 A, a narrow multiplier  242 B, a wide two-input mux  1896 A, a narrow two-input mux  1896 B, a wide adder  244 A and a narrow adder  244 B. Effectively, the ALU  204  comprises the operand selection logic  1898 , a wide ALU  204 A (comprising the wide multiplier  242 A, the wide mux  1896 A and the wide adder  244 A) and a narrow ALU  204 B (comprising the narrow multiplier  242 B, the narrow mux  1896 B and the narrow adder  244 B). Preferably, the wide multiplier  242 A multiplies two wide words and is similar to the multiplier  242  of  FIG. 2 , e.g., a 16-bit by 16-bit multiplier. The narrow multiplier  242 B multiplies two narrow words, e.g., an 8-bit by 8-bit multiplier that generates a 16-bit result. When the NPU  126  is in a narrow configuration, the wide multiplier  242 A is effectively used, with the help of the operand selection logic  1898 , as a narrow multiplier to multiply two narrow words so that the NPU  126  effectively functions as two narrow NPUs. Preferably, the wide adder  244 A adds the output of the wide mux  1896 A and the wide accumulator  202 A output  217 A to generate a sum  215 A for provision to the wide accumulator  202 A and is similar to the adder  244  of  FIG. 2 . The narrow adder  244 B adds the output of the narrow mux  1896 B and the narrow accumulator  202 B output  217 B to generate a sum  215 B for provision to the narrow accumulator  202 B. In one embodiment, the narrow accumulator  202 B is 28 bits wide to avoid loss of precision in the accumulation of up to 1024 16-bit products. When the NPU  126  is in a wide configuration, the narrow multiplier  242 B, narrow mux  1896 B, narrow adder  244 B, narrow accumulator  202 B and narrow AFU  212 B are preferably inactive to reduce power consumption. 
     The operand selection logic  1898  selects operands from  209 A,  209 B,  203 A and  203 B to provide to the other elements of the ALU  204 , as described in more detail below. Preferably, the operand selection logic  1898  also performs other functions, such as performing sign extension of signed-valued data words and weight words. For example, if the NPU  126  is in a narrow configuration, the operand selection logic  1898  sign extends the narrow data word and weight word to the width of a wide word before providing them to the wide multiplier  242 A. Similarly, if the ALU  204  is instructed to pass through a narrow data/weight word (bypass the wide multiplier  242 A via wide mux  1896 A), the operand selection logic  1898  sign extends the narrow data/weight word to the width of a wide word before providing it to the wide adder  244 A. Preferably, logic is also present in the ALU  204  of the NPU  126  of  FIG. 2  to perform the sign-extension function. 
     The wide mux  1896 A receives the output of the wide multiplier  242 A and an operand from the operand selection logic  1898  and selects one of the inputs for provision to the wide adder  244 A, and the narrow mux  1896 B receives the output of the narrow multiplier  242 B and an operand from the operand selection logic  1898  and selects one of the inputs for provision to the narrow adder  244 B. 
     The operands provided by the operand selection logic  1898  depend upon the configuration of the NPU  126  and upon the arithmetic and/or logical operations to be performed by the ALU  204  based on the function specified by the instruction being executed by the NPU  126 . For example, if the instruction instructs the ALU  204  to perform a multiply-accumulate and the NPU  126  is in a wide configuration, the operand selection logic  1898  provides to the wide multiplier  242 A on one input a wide word that is the concatenation of outputs  209 A and  209 B and on the other input a wide word that is the concatenation of outputs  203 A and  203 B, and the narrow multiplier  242 B is inactive, so that the NPU  126  functions as a single wide NPU  126  similar to the NPU  126  of  FIG. 2 . Whereas, if the instruction instructs the ALU  204  to perform a multiply-accumulate and the NPU  126  is in a narrow configuration, the operand selection logic  1898  provides to the wide multiplier  242 A on one input an extended, or widened, version of the narrow data word  209 A and on the other input an extended version of the narrow weight word  203 A; additionally, the operand selection logic  1898  provides to the narrow multiplier  242 B on one input the narrow data words  209 B and on the other input the narrow weight word  203 B. To extend, or widen, a narrow word, if the narrow word is signed, then the operand selection logic  1898  sign-extends the narrow word, whereas if the narrow word is unsigned, the operand selection logic  1898  pads the narrow word with zero-valued upper bits. 
     For another example, if the NPU  126  is in a wide configuration and the instruction instructs the ALU  204  to perform an accumulate of the weight word, the wide multiplier  242 A is bypassed and the operand selection logic  1898  provides the concatenation of outputs  203 A and  203 B to the wide mux  1896 A for provision to the wide adder  244 A. Whereas, if the NPU  126  is in a narrow configuration and the instruction instructs the ALU  204  to perform an accumulate of the weight word, the wide multiplier  242 A is bypassed and the operand selection logic  1898  provides an extended version of the output  203 A to the wide mux  1896 A for provision to the wide adder  244 A; and the narrow multiplier  242 B is bypassed and the operand selection logic  1898  provides an extended version of the output  203 B to the narrow mux  1896 B for provision to the narrow adder  244 B. 
     For another example, if the NPU  126  is in a wide configuration and the instruction instructs the ALU  204  to perform an accumulate of the data word, the wide multiplier  242 A is bypassed and the operand selection logic  1898  provides the concatenation of outputs  209 A and  209 B to the wide mux  1896 A for provision to the wide adder  244 A. Whereas, if the NPU  126  is in a narrow configuration and the instruction instructs the ALU  204  to perform an accumulate of the data word, the wide multiplier  242 A is bypassed and the operand selection logic  1898  provides an extended version of the output  209 A to the wide mux  1896 A for provision to the wide adder  244 A; and the narrow multiplier  242 B is bypassed and the operand selection logic  1898  provides an extended version of the output  209 B to the narrow mux  1896 B for provision to the narrow adder  244 B. The accumulation of weight/data words may be useful for performing averaging operations that are used in pooling layers of some artificial neural network applications, such as image processing. 
     Preferably, the NPU  126  also includes a second wide mux (not shown) for bypassing the wide adder  244 A to facilitate loading the wide accumulator  202 A with a wide data/weight word in wide configuration or an extended narrow data/weight word in narrow configuration, and a second narrow mux (not shown) for bypassing the narrow adder  244 B to facilitate loading the narrow accumulator  202 B with a narrow data/weight word in narrow configuration. Preferably, the ALU  204  also includes wide and narrow comparator/mux combinations (not shown) that receive the respective accumulator value  217 A/ 217 B and respective mux  1896 A/ 1896 B output to select the maximum value between the accumulator value  217 A/ 217 B and a data/weight word  209 A/B/ 203 A/B, an operation that is used in pooling layers of some artificial neural network applications, as described in more detail below, e.g., with respect to  FIGS. 27 and 28 . Additionally, the operand selection logic  1898  is configured to provide zero-valued operands (for addition with zero or for clearing the accumulators) and to provide one-valued operands (for multiplication by one). 
     The narrow AFU  212 B receives the output  217 B of the narrow accumulator  202 B and performs an activation function on it to generate a narrow result  133 B, and the wide AFU  212 A receives the output  217 A of the wide accumulator  202 A and performs an activation function on it to generate a wide result  133 A. When the NPU  126  is in a narrow configuration, the wide AFU  212 A considers the output  217 A of the wide accumulator  202 A accordingly and performs an activation function on it to generate a narrow result, e.g., 8 bits, as described in more detail below with respect to  FIGS. 29A through 30 , for example. 
     As may observed from the above description, advantageously the single NPU  126  operates effectively as two narrow NPUs when in a narrow configuration, thus providing, for smaller words, approximately up to twice the throughput as when in the wide configuration. For example, assume a neural network layer having 1024 neurons each receiving 1024 narrow inputs from the previous layer (and having narrow weight words), resulting in 1 Mega-connections. An NNU  121  having 512 NPUs  126  in a narrow configuration (1024 narrow NPU) compared to an NNU  121  having 512 NPUs  126  in a wide configuration is capable of processing four times the number of connections (1 Mega-connections vs. 256K connections) in approximately half the time (approx. 1026 clocks vs. 514 clocks), albeit for narrow words rather than wide words. 
     In one embodiment, the dynamically configurable NPU  126  of  FIG. 18  includes 3-input multiplexed-registers similar to mux-regs  208 A and  208 B in place of the registers  205 A and  205 B to accomplish a rotater for a row of weight words received from the weight RAM  124  somewhat similar to the manner described with respect to the embodiment of  FIG. 7  but in a dynamically configurable fashion as described with respect to  FIG. 18 . 
     Referring now to  FIG. 19 , a block diagram illustrating an embodiment of the arrangement of the 2N mux-regs  208 A/ 208 B of the N NPUs  126  of the NNU  121  of  FIG. 1  according to the embodiment of  FIG. 18  to illustrate their operation as a rotater for a row of data words  207  received from the data RAM  122  of  FIG. 1  is shown. In the embodiment of  FIG. 19 , N is 512 such that the NNU  121  has 1024 mux-regs  208 A/ 208 B, denoted  0  through  511 , corresponding to 512 NPUs  126  and effectively 1024 narrow NPUs, as shown. The two narrow NPUs within a NPU  126  are denoted A and B, and within each of the mux-regs  208 , the designation of the corresponding narrow NPU is shown. More specifically, mux-reg  208 A of NPU  126   0  is designated  0 -A, mux-reg  208 B of NPU  126   0  is designated  0 -B, mux-reg  208 A of NPU  126   1  is designated  1 -A, mux-reg  208 B of NPU  126   1  is designated  1 -B, mux-reg  208 A of NPU  126   511  is designated  511 -A, and mux-reg  208 B of NPU  126   511  is designated  0 -B, which values also correspond to the narrow NPUs of  FIG. 21  described below. 
     Each mux-reg  208 A receives its corresponding narrow data word  207 A of one row of the D rows of the data RAM  122 , and each mux-reg  208 B receives its corresponding narrow data word  207 B of one row of the D rows of the data RAM  122 . That is, mux-reg  0 A receives narrow data word  0  of the data RAM  122  row, mux-reg  0 B receives narrow data word  1  of the data RAM  122  row, mux-reg  1 A receives narrow data word  2  of the data RAM  122  row, mux-reg  1 B receives narrow data word  3  of the data RAM  122  row, and so forth to mux-reg  511 A receives narrow data word  1022  of the data RAM  122  row, and mux-reg  511 B receives narrow data word  1023  of the data RAM  122  row. Additionally, mux-reg  1 A receives on its input  211 A the output  209 A of mux-reg  0 A, mux-reg  1 B receives on its input  211 B the output  209 B of mux-reg  0 B, and so forth to mux-reg  511 A that receives on its input  211 A the output  209 A of mux-reg  510 A and mux-reg  511 B that receives on its input  211 B the output  209 B of mux-reg  510 B, and mux-reg  0 A receives on its input  211 A the output  209 A of mux-reg  511 A and mux-reg  0 B receives on its input  211 B the output  209 B of mux-reg  511 B. Each of the mux-regs  208 A/ 208 B receives the control input  213  that controls whether to select the data word  207 A/ 207 B or the rotated input  211 A/ 211 B or the rotated input  1811 A/ 1811 B. Finally, mux-reg  1 A receives on its input  1811 A the output  209 B of mux-reg  0 B, mux-reg  1 B receives on its input  1811 B the output  209 A of mux-reg  1 A, and so forth to mux-reg  511 A that receives on its input  1811 A the output  209 B of mux-reg  510 B and mux-reg  511 B that receives on its input  1811 B the output  209 A of mux-reg  511 A, and mux-reg  0 A receives on its input  1811 A the output  209 B of mux-reg  511 B and mux-reg  0 B receives on its input  1811 B the output  209 A of mux-reg  0 A. Each of the mux-regs  208 A/ 208 B receives the control input  213  that controls whether to select the data word  207 A/ 207 B or the rotated input  211 A/ 211 B or the rotated input  1811 A/ 1811 B. As described in more detail below, in one mode of operation, on a first clock cycle, the control input  213  controls each of the mux-regs  208 A/ 208 B to select the data word  207 A/ 207 B for storage in the register and for subsequent provision to the ALU  204 ; and during subsequent clock cycles (e.g., M−1 clock cycles as described above), the control input  213  controls each of the mux-regs  208 A/ 208 B to select the rotated input  1811 A/ 1811 B for storage in the register and for subsequent provision to the ALU  204 . 
     Referring now to  FIG. 20 , a table illustrating a program for storage in the program memory  129  of and execution by the NNU  121  of  FIG. 1  having NPUs  126  according to the embodiment of  FIG. 18  is shown. The example program of  FIG. 20  is similar in many ways to the program of  FIG. 4 . However, differences will now be described. The initialize NPU instruction at address  0  specifies that the NPU  126  is to be in a narrow configuration. Additionally, the multiply-accumulate rotate instruction at address  2  specifies a count of 1023 and requires 1023 clock cycles, as shown. This is because the example of  FIG. 20  assumes effectively 1024 narrow (e.g., 8-bit) neurons (NPUs) of a layer, each having 1024 connection inputs from a previous layer of 1024 neurons, for a total of 1024K connections. Each neuron receives an 8-bit data value from each connection input and multiplies the 8-bit data value by an appropriate 8-bit weight value. 
     Referring now to  FIG. 21 , a timing diagram illustrating the execution of the program of  FIG. 20  by the NNU  121  that includes NPUs  126  of  FIG. 18  operating in a narrow configuration is shown. The timing diagram of  FIG. 21  is similar in many ways to the timing diagram of  FIG. 5 ; however, differences will now be described. 
     In the timing diagram of  FIG. 21 , the NPUs  126  are in a narrow configuration because the initialize NPU instruction at address  0  initializes them to a narrow configuration. Consequently, the 512 NPUs  126  effectively operate as 1024 narrow NPUs (or neurons), which are designated in the columns as NPU  0 -A and NPU  0 -B (the two narrow NPUs of NPU  126   0 ), NPU  1 -A and NPU  1 -B (the two narrow NPUs of NPU  126   1 ) and so forth through NPU  511 -A and NPU  511 -B (the two narrow NPUs of NPU  126   511 ). For simplicity and clarity of illustration, the operations only for narrow NPUs  0 -A,  0 -B and  511 -B are shown. Due to the fact that the multiply-accumulate rotate at address  2  specifies a count of 1023, which requires 1023 clocks, the rows of the timing diagram of  FIG. 21  include up to clock cycle  1026 . 
     At clock  0 , each of the 1024 NPUs performs the initialization instruction of  FIG. 4 , which is illustrated in  FIG. 5  by the assignment of a zero value to the accumulator  202 . 
     At clock  1 , each of the 1024 narrow NPUs performs the multiply-accumulate instruction at address  1  of  FIG. 20 . Narrow NPU  0 -A accumulates the accumulator  202 A value (which is zero) with the product of data RAM  122  row  17  narrow word  0  and weight RAM  124  row  0  narrow word  0 ; narrow NPU  0 -B accumulates the accumulator  202 B value (which is zero) with the product of data RAM  122  row  17  narrow word  1  and weight RAM  124  row  0  narrow word  1 ; and so forth to narrow NPU  511 -B accumulates the accumulator  202 B value (which is zero) with the product of data RAM  122  row  17  narrow word  1023  and weight RAM  124  row  0  narrow word  1023 , as shown. 
     At clock  2 , each of the 1024 narrow NPUs performs a first iteration of the multiply-accumulate rotate instruction at address  2  of  FIG. 20 . Narrow NPU  0 -A accumulates the accumulator  202 A value  217 A with the product of the rotated narrow data word  1811 A received from the mux-reg  208 B output  209 B of narrow NPU  511 -B (which was narrow data word  1023  received from the data RAM  122 ) and weight RAM  124  row  1  narrow word  0 ; narrow NPU  0 -B accumulates the accumulator  202 B value  217 B with the product of the rotated narrow data word  1811 B received from the mux-reg  208 A output  209 A of narrow NPU  0 -A (which was narrow data word  0  received from the data RAM  122 ) and weight RAM  124  row  1  narrow word  1 ; and so forth to narrow NPU  511 -B accumulates the accumulator  202 B value  217 B with the product of the rotated narrow data word  1811 B received from the mux-reg  208 A output  209 A of narrow NPU  511 -A (which was narrow data word  1022  received from the data RAM  122 ) and weight RAM  124  row  1  narrow word  1023 , as shown. 
     At clock  3 , each of the 1024 narrow NPUs performs a second iteration of the multiply-accumulate rotate instruction at address  2  of  FIG. 20 . Narrow NPU  0 -A accumulates the accumulator  202 A value  217 A with the product of the rotated narrow data word  1811 A received from the mux-reg  208 B output  209 B of narrow NPU  511 -B (which was narrow data word  1022  received from the data RAM  122 ) and weight RAM  124  row  2  narrow word  0 ; narrow NPU  0 -B accumulates the accumulator  202 B value  217 B with the product of the rotated narrow data word  1811 B received from the mux-reg  208 A output  209 A of narrow NPU  0 -A (which was narrow data word  1023  received from the data RAM  122 ) and weight RAM  124  row  2  narrow word  1 ; and so forth to narrow NPU  511 -B accumulates the accumulator  202 B value  217 B with the product of the rotated narrow data word  1811 B received from the mux-reg  208 A output  209 A of narrow NPU  511 -A (which was narrow data word  1021  received from the data RAM  122 ) and weight RAM  124  row  2  narrow word  1023 , as shown. As indicated by the ellipsis of  FIG. 21 , this continues for each of the following 1021 clock cycles until . . . . 
     At clock  1024 , each of the 1024 narrow NPUs performs a 1023 rd  iteration of the multiply-accumulate rotate instruction at address  2  of  FIG. 20 . Narrow NPU  0 -A accumulates the accumulator  202 A value  217 A with the product of the rotated narrow data word  1811 A received from the mux-reg  208 B output  209 B of narrow NPU  511 -B (which was narrow data word  1  received from the data RAM  122 ) and weight RAM  124  row  1023  narrow word  0 ; NPU  0 -B accumulates the accumulator  202 B value  217 B with the product of the rotated narrow data word  1811 B received from the mux-reg  208 A output  209 A of NPU  0 -A (which was narrow data word  2  received from the data RAM  122 ) and weight RAM  124  row  1023  narrow word  1 ; and so forth to NPU  511 -B accumulates the accumulator  202 B value with the product of the rotated narrow data word  1811 B received from the mux-reg  208 A output  209 A of NPU  511 -A (which was narrow data word  0  received from the data RAM  122 ) and weight RAM  124  row  1023  narrow word  1023 , as shown. 
     At clock  1025 , the AFU  212 A/ 212 B of each of the 1024 narrow NPUs performs the activation function instruction at address  3  of  FIG. 20 . Finally, at clock  1026 , each of the 1024 narrow NPUs performs the write AFU output instruction at address  4  of  FIG. 20  by writing back its narrow result  133 A/ 133 B to its corresponding narrow word of row  16  of the data RAM  122 , i.e., the narrow result  133 A of NPU  0 -A is written to narrow word  0  of the data RAM  122 , the narrow result  133 B of NPU  0 -B is written to narrow word  1  of the data RAM  122 , and so forth to the narrow result  133  of NPU  511 -B is written to narrow word  1023  of the data RAM  122 . The operation described above with respect to  FIG. 21  is also shown in block diagram form in  FIG. 22 . 
     Referring now to  FIG. 22 , a block diagram illustrating the NNU  121  of  FIG. 1  including the NPUs  126  of  FIG. 18  to execute the program of  FIG. 20  is shown. The NNU  121  includes the 512 NPUs  126 , i.e., 1024 narrow NPUs, the data RAM  122  that receives its address input  123 , and the weight RAM  124  that receives its address input  125 . Although not shown, on clock  0  the 1024 narrow NPUs perform the initialization instruction of  FIG. 20 . As shown, on clock  1 , the 1024 8-bit data words of row  17  are read out of the data RAM  122  and provided to the 1024 narrow NPUs. On clocks  1  through  1024 , the 1024 8-bit weight words of rows  0  through  1023 , respectively, are read out of the weight RAM  124  and provided to the 1024 narrow NPUs. Although not shown, on clock  1 , the 1024 narrow NPUs perform their respective multiply-accumulate operations on the loaded data words and weight words. On clocks  2  through  1024 , the mux-regs  208 A/ 208 B of the 1024 narrow NPUs operate as a 1024 8-bit word rotater to rotate the previously loaded data words of row  17  of the data RAM  122  to the adjacent narrow NPU, and the narrow NPUs perform the multiply-accumulate operation on the respective rotated data narrow word and the respective narrow weight word loaded from the weight RAM  124 . Although not shown, on clock  1025 , the 1024 narrow AFUs  212 A/ 212 B perform the activation instruction. On clock  1026 , the 1024 narrow NPUs write back their respective 1024 8-bit results  133 A/ 133 B to row  16  of the data RAM  122 . 
     As may be observed, the embodiment of  FIG. 18  may be advantageous over the embodiment of  FIG. 2 , for example, because it provides the flexibility for the programmer to perform computations using wide data and weight words (e.g., 16-bits) when that amount of precision is needed by the particular application being modeled and narrow data and weight words (e.g., 8-bits) when that amount of precision is needed by the application. From one perspective, the embodiment of  FIG. 18  provides double the throughput over the embodiment of  FIG. 2  for narrow data applications at the cost of the additional narrow elements (e.g., mux-reg  208 B, reg  205 B, narrow ALU  204 B, narrow accumulator  202 B, narrow AFU  212 B), which is approximately a 50% increase in area of the NPU  126 . 
     Tri-Mode NPUs 
     Referring now to  FIG. 23 , a block diagram illustrating a dynamically configurable NPU  126  of  FIG. 1  according to an alternate embodiment is shown. The NPU  126  of  FIG. 23  is configurable not only in wide and narrow configurations, but also in a third configuration referred to herein as a “funnel” configuration. The NPU  126  of  FIG. 23  is similar in many respects to the NPU  126  of  FIG. 18 . However, the wide adder  244 A of  FIG. 18  is replaced in the NPU  126  of  FIG. 23  with a 3-input wide adder  2344 A that receives a third addend  2399  that is an extended version of the output of the narrow mux  1896 B. A program for operating an NNU  121  having the NPUs  126  of  FIG. 23  is similar in most respects to the program of  FIG. 20 . However, the initialize NPU instruction at address  0  initializes the NPUs  126  to a funnel configuration, rather than a narrow configuration. Additionally, the count of the multiply-accumulate rotate instruction at address  2  is 511 rather than 1023. 
     When in the funnel configuration, the NPU  126  operates similarly to when in the narrow configuration when executing a multiply-accumulate instruction such as at address  1  of  FIG. 20  in that it receives two narrow data words  207 A/ 207 B and two narrow weight words  206 A/ 206 B; the wide multiplier  242 A multiplies data word  209 A and weight word  203 A to generate product  246 A which the wide mux  1896 A selects; and the narrow multiplier  242 B multiplies data word  209 B and weight word  203 B to generate product  246 B which the narrow mux  1896 B selects. However, the wide adder  2344 A adds both the product  246 A (selected by wide mux  1896 A) and the product  246 B/ 2399  (selected by wide mux  1896 B) to the wide accumulator  202 A value  217 A, and narrow adder  244 B and narrow accumulator  202 B are inactive. Furthermore, when in the funnel configuration, when executing a multiply-accumulate rotate instruction such as at address  2  of  FIG. 20 , the control input  213  causes the mux-regs  208 A/ 208 B to rotate by two narrow words (e.g., 16-bits), i.e., the mux-regs  208 A/ 208 B select their respective  211 A/ 211 B inputs as if they were in a wide configuration. However, the wide multiplier  242 A multiplies data word  209 A and weight word  203 A to generate product  246 A which the wide mux  1896 A selects; and the narrow multiplier  242 B multiplies data word  209 B and weight word  203 B to generate product  246 B which the narrow mux  1896 B selects; and the wide adder  2344 A adds both the product  246 A (selected by wide mux  1896 A) and the product  246 B/ 2399  (selected by wide mux  1896 B) to the wide accumulator  202 A value  217 A, and the narrow adder  244 B and narrow accumulator  202 B are inactive as described above. Finally, when in the funnel configuration, when executing an activation function instruction such as at address  3  of  FIG. 20 , the wide AFU  212 A performs the activation function on the resulting sum  215 A to generate a narrow result  133 A and the narrow AFU  212 B is inactive. Hence, only the A narrow NPUs generate a narrow result  133 A, and the narrow results  133 B generated by the B narrow NPUs are invalid. Consequently, the row of results written back (e.g., to row  16  as at the instruction at address  4  of  FIG. 20 ) includes holes since only the narrow results  133 A are valid and the narrow results  133 B are invalid. Thus, conceptually, each clock cycle each neuron (NPU  126  of  FIG. 23 ) processes two connection data inputs, i.e., multiplies two narrow data words by their respective weights and accumulates the two products, in contrast to the embodiments of  FIGS. 2 and 18  which each process a single connection data input per clock cycle. 
     As may be observed with respect to the embodiment of  FIG. 23 , the number of result words (neuron outputs) produced and written back to the data RAM  122  or weight RAM  124  is half the square root of the number of data inputs (connections) received and the written back row of results has holes, i.e., every other narrow word result is invalid, more specifically, the B narrow NPU results are not meaningful. Thus, the embodiment of  FIG. 23  may be particularly efficient in neural networks having two successive layers in which, for example, the first layer has twice as many neurons as the second layer (e.g., the first layer has 1024 neurons fully connected to a second layer of 512 neurons). Furthermore, the other execution units  112  (e.g., media units, such as x86 AVX units) may perform pack operations on a disperse row of results (i.e., having holes) to make compact it (i.e., without holes), if necessary, for use in subsequent computations while the NNU  121  is performing other computations associated with other rows of the data RAM  122  and/or weight RAM  124 . 
     Hybrid NNU Operation; Convolution and Pooling Capabilities 
     An advantage of the NNU  121  according to embodiments described herein is that the NNU  121  is capable of concurrently operating in a fashion that resembles a coprocessor in that it executes its own internal program and operating in a fashion that resembles an execution unit of a processor in that it executes architectural instructions (or microinstructions translated therefrom) issued to it. The architectural instructions are of an architectural program being performed by the processor that includes the NNU  121 . In this manner, the NNU  121  operates in a hybrid fashion, which is advantageous because it provides the ability to sustain high utilization of the NNU  121 . For example, the  FIGS. 24 through 26  illustrate the operation of the NNU  121  to perform a convolution operation in which the NNU  121  is highly utilized, and  FIGS. 27 through 28  illustrate the operation of the NNU  121  to perform a pooling operation, which are required for convolution layers and pooling layers and other digital data computing applications, such as image processing (e.g., edge detection, sharpening, blurring, recognition/classification). However, the hybrid operation of the NNU  121  is not limited to performing a convolution or pooling operation, rather the hybrid feature may be used to perform other operations, such as classic neural network multiply-accumulate and activation function operations as described above with respect to  FIGS. 4 through 13 . That is, the processor  100  (more specifically, the reservation stations  108 ) issue MTNN  1400  and MFNN  1500  instructions to the NNU  121  in response to which the NNU  121  writes data to the memories  122 / 124 / 129  and reads results from the memories  122 / 124  written there by the NNU  121 , while concurrently the NNU  121  reads and writes the memories  122 / 124 / 129  in response to executing programs written to the program memory  129  by the processor  100  (via MTNN  1400  instructions). 
     Referring now to  FIG. 24 , a block diagram illustrating an example of data structures used by the NNU  121  of  FIG. 1  to perform a convolution operation are shown. The block diagram includes a convolution kernel  2402 , a data array  2404 , and the data RAM  122  and weight RAM  124  of  FIG. 1 . Preferably, the data array  2404  (e.g., of image pixels) is held in system memory (not shown) attached to the processor  100  and loaded into the weight RAM  124  of the NNU  121  by the processor  100  executing MTNN instructions  1400 . A convolution operation is an operation that convolves a first matrix with a second matrix, the second matrix referred to as a convolution kernel herein. As understood in the context of the present disclosure, a convolution kernel is a matrix of coefficients, which may also be referred to as weights, parameters, elements or values. Preferably, the convolution kernel  2042  is static data of the architectural program being executed by the processor  100 . 
     The data array  2404  is a two-dimensional array of data values, and each data value (e.g., an image pixel value) is the size of a word of the data RAM  122  or weight RAM  124  (e.g., 16 bits or 8 bits). In the example, the data values are 16-bit words and the NNU  121  is configured as 512 wide configuration NPUs  126 . Additionally, in the embodiment, the NPUs  126  include mux-regs for receiving the weight words  206  from the weight RAM  124 , such as mux-reg  705  of  FIG. 7 , in order to perform the collective rotater operation of a row of data values received from the weight RAM  124 , as described in more detail below. In the example, the data array  2404  is a 2560 column×1600 row pixel array. When the architectural program convolves the data array  2404  with the convolution kernel  2402 , it breaks the data array  2404  into 20 chunks, each chunk being a 512×400 data matrix  2406 , as shown. 
     The convolution kernel  2042 , in the example, is a 3×3 matrix of coefficients, or weights, or parameters, or elements. The first row of coefficients are denoted C 0 , 0 ; C 0 , 1 ; and C 0 , 2 ; the second row of coefficients are denoted C 1 , 0 ; C 1 , 1 ; and C 1 , 2 ; and the third row of coefficients are denoted C 2 , 0 ; C 2 , 1 ; and C 2 , 2 . For example, a convolution kernel that may be used for performing edge detection has the following coefficients: 0, 1, 0, 1, −4, 1, 0, 1, 0. For another example, a convolution kernel that may be used to Gaussian blur an image has the following coefficients: 1, 2, 1, 2, 4, 2, 1, 2, 1. In this case, a divide is typically performed on the final accumulated value, where the divisor is the sum of the absolute values of the elements of the convolution kernel  2042 , which is 16 in this example. For another example, the divisor is the number of elements of the convolution kernel  2042 . For another example, the divisor is a value that compresses the convolutions back within a desired range of values, and the divisor is determined from the values of the elements of the convolution kernel  2042  and the desired range and the range of the input values of the matrix being convolved. 
     As shown in  FIG. 24  and described in more detail with respect to  FIG. 25 , the architectural program writes the data RAM  122  with the coefficients of the convolution kernel  2042 . Preferably, all the words of each of nine (the number of elements in the convolution kernel  2402 ) consecutive rows of the data RAM  122  are written with a different element of the convolution kernel  2402  in row-major order. That is, each word of one row is written with the first coefficient C 0 , 0 ; the next row is written with the second coefficient C 0 , 1 ; the next row is written with the third coefficient C 0 , 2 ; the next row is written with the fourth coefficient C 1 , 0 ; and so forth until each word of the ninth row is written with the ninth coefficient C 2 , 2 , as shown. To convolve a data matrix  2406  of a chunk of the data array  2404 , the NPUs  126  repeatedly read, in order, the nine rows of the data RAM  122  that hold the convolution kernel  2042  coefficients, as described in more detail below, particularly with respect to  FIG. 26A . 
     As shown in  FIG. 24  and described in more detail with respect to  FIG. 25 , the architectural program writes the weight RAM  124  with the values of a data matrix  2406 . As the NNU program performs the convolution, it writes back the resulting matrix to the weight RAM  124 . Preferably, the architectural program writes a first data matrix  2406  to the weight RAM  124  and starts the NNU  121 , and while the NNU  121  is convolving the first data matrix  2406  with the convolution kernel  2042 , the architectural program writes a second data matrix  2406  to the weight RAM  124  so that as soon as the NNU  121  completes the convolution of the first data matrix  2406 , the NNU  121  can start convolving the second data matrix  2406 , as described in more detail with respect to  FIG. 25 . In this manner, the architectural program ping-pongs back and forth between the two regions of the weight RAM  124  in order to keep the NNU  121  fully utilized. Thus, the example of  FIG. 24  shows a first data matrix  2406 A corresponding to a first chunk occupying rows  0  through  399  of the weight RAM  124 , and a second data matrix  2406 B corresponding to a second chunk occupying rows  500  through  899  of the weight RAM  124 . Furthermore, as shown, the NNU  121  writes back the results of the convolutions to rows  900 - 1299  and  1300 - 1699  of the weight RAM  124 , which the architectural program subsequently reads out of the weight RAM  124 . The data values of the data matrix  2406  held in the weight RAM  124  are denoted “Dx,y” where “x” is the weight RAM  124  row number and “y” is the word, or column, number of the weight RAM  124 . Thus, for example, data word  511  in row  399  is denoted D 399 ,  511  in  FIG. 24 , which is received by the mux-reg  705  of NPU  511 . 
     Referring now to  FIG. 25 , a flowchart illustrating operation of the processor  100  of  FIG. 1  to perform an architectural program that uses the NNU  121  to perform a convolution of the convolution kernel  2042  with the data array  2404  of  FIG. 24 . Flow begins at block  2502 . 
     At block  2502 , the processor  100 , i.e., the architectural program running on the processor  100 , writes the convolution kernel  2042  of  FIG. 24  to the data RAM  122  in the manner shown and described with respect to  FIG. 24 . Additionally, the architectural program initializes a variable N to a value of 1. The variable N denotes the current chunk of the data array  2404  being processed by the NNU  121 . Additionally, the architectural program initializes a variable NUM_CHUNKS to a value of 20. Flow proceeds to block  2504 . 
     At block  2504 , the processor  100  writes the data matrix  2406  for chunk  1  to the weight RAM  124 , as shown in  FIG. 24  (e.g., data matrix  2406 A of chunk  1 ). Flow proceeds to block  2506 . 
     At block  2506 , the processor  100  writes a convolution program to the NNU  121  program memory  129 , using MTNN  1400  instructions that specify a function  1432  to write the program memory  129 . The processor  100  then starts the NNU convolution program using a MTNN  1400  instruction that specifies a function  1432  to start execution of the program. An example of the NNU convolution program is described in more detail with respect to  FIG. 26A . Flow proceeds to decision block  2508 . 
     At decision block  2508 , the architectural program determines whether the value of variable N is less than NUM_CHUNKS. If so, flow proceeds to block  2512 ; otherwise, flow proceeds to block  2514 . 
     At block  2512 , the processor  100  writes the data matrix  2406  for chunk N+1 to the weight RAM  124 , as shown in  FIG. 24  (e.g., data matrix  2406 B of chunk  2 ). Thus, advantageously, the architectural program writes the data matrix  2406  for the next chunk to the weight RAM  124  while the NNU  121  is performing the convolution on the current chunk so that the NNU  121  can immediately start performing the convolution on the next chunk once the convolution of the current chunk is complete, i.e., written to the weight RAM  124 . Flow proceeds to block  2514 . 
     At block  2514 , the processor  100  determines that the currently running NNU program (started at block  2506  in the case of chunk  1 , and started at block  2518  in the case of chunks  2 - 20 ) has completed. Preferably, the processor  100  determines this by executing a MFNN  1500  instruction to read the NNU  121  status register  127 . In an alternate embodiment, the NNU  121  generates an interrupt to indicate it has completed the convolution program. Flow proceeds to decision block  2516 . 
     At decision block  2516 , the architectural program determines whether the value of variable N is less than NUM_CHUNKS. If so, flow proceeds to block  2518 ; otherwise, flow proceeds to block  2522 . 
     At block  2518 , the processor  100  updates the convolution program so that it can convolve chunk N+1. More specifically, the processor  100  updates the weight RAM  124  row value of the initialize NPU instruction at address  0  to the first row of the data matrix  2406  (e.g., to row  0  for data matrix  2406 A or to row  500  for data matrix  2406 B) and updates the output row (e.g., to  900  or  1300 ). The processor  100  then starts the updated NNU convolution program. Flow proceeds to block  2522 . 
     At block  2522 , the processor  100  reads the results of the NNU convolution program from the weight RAM  124  for chunk N. Flow proceeds to decision block  2524 . 
     At decision block  2524 , the architectural program determines whether the value of variable N is less than NUM_CHUNKS. If so, flow proceeds to block  2526 ; otherwise, flow ends. 
     At block  2526 , the architectural program increments N by one. Flow returns to decision block  2508 . 
     Referring now to  FIG. 26A , a program listing of an NNU program that performs a convolution of a data matrix  2406  with the convolution kernel  2042  of  FIG. 24  and writes it back to the weight RAM  124  is shown. The program loops a number of times through a loop body of instructions at addresses  1  through  9 . An initialize NPU instruction at address  0  specifies the number of times each NPU  126  executes the loop body, which in the example of  FIG. 26A  has a loop count value of 400, corresponding to the number of rows in a data matrix  2406  of  FIG. 24 , and a loop instruction at the end of the loop (at address  10 ) decrements the current loop count value and if the result is non-zero causes control to return to the top of the loop body (i.e., to the instruction at address  1 ). The initialize NPU instruction also clears the accumulator  202  to zero. Preferably, the loop instruction at address  10  also clears the accumulator  202  to zero. Alternatively, as described above, the multiply-accumulate instruction at address  1  may specify to clear the accumulator  202  to zero. 
     For each execution of the loop body of the program, the 512 NPUs  126  concurrently perform 512 convolutions of the 3×3 convolution kernel  2402  and  512  respective 3×3 sub-matrices of a data matrix  2406 . The convolution is the sum of the nine products of an element of the convolution kernel  2042  and its corresponding element of the respective sub-matrix. In the embodiment of  FIG. 26A , the origin (center element) of each of the 512 respective 3×3 sub-matrices is the data word Dx+1,y+1 of  FIG. 24 , where y (column number) is the NPU  126  number, and x (row number) is the current weight RAM  124  row number that is read by the multiply-accumulate instruction at address  1  of the program of  FIG. 26A  (also, the row number is initialized by the initialize NPU instruction at address  0 , incremented at each of the multiply-accumulate instructions at addresses  3  and  5 , and updated by the decrement instruction at address  9 ). Thus, for each loop of the program, the 512 NPUs  126  compute the 512 convolutions and write the 512 convolution results back to a specified row of the weight RAM  124 . In the present description, edge handling is ignored for simplicity, although it should be noted that the use of the collective rotating feature of the NPUs  126  will cause wrapping for two of the columns from one vertical edge of the data matrix  2406  (e.g., of the image in the case of image processing) to the other vertical edge (e.g., from the left edge to the right edge or vice versa). The loop body will now be described. 
     At address  1  is a multiply-accumulate instruction that specifies row  0  of the data RAM  122  and implicitly uses the current weight RAM  124  row, which is preferably held in the sequencer  128  (and which is initialized to zero by the instruction at address  0  for the first pass through the loop body). That is, the instruction at address  1  causes each of the NPUs  126  to read its corresponding word from row  0  of the data RAM  122  and read its corresponding word from the current weight RAM  124  row and perform a multiply-accumulate operation on the two words. Thus, for example, NPU  5  multiplies C 0 , 0  and Dx, 5  (where “x” is the current weight RAM  124  row), adds the result to the accumulator  202  value  217  and writes the sum back to the accumulator  202 . 
     At address  2  is a multiply-accumulate instruction that specifies to increment the data RAM  122  row (i.e., to row  1 ) and then read the row from the data RAM  122  at the incremented address. The instruction also specifies to rotate the values in the mux-reg  705  of each NPU  126  to the adjacent NPU  126 , which in this case is the row of data matrix  2406  values just read from the weight RAM  124  in response to the instruction at address  1 . In the embodiment of  FIGS. 24 through 26 , the NPUs  126  are configured to rotate the values of the mux-regs  705  to the left, i.e., from NPU J to NPU J−1, rather than from NPU J to NPU J+1 as described above with respect to  FIGS. 3, 7 and 19 . It should be understood that in an embodiment in which the NPUs  126  are configured to rotate right, the architectural program may write the convolution kernel  2042  coefficient values to the data RAM  122  in a different order (e.g., rotated around its central column) in order to accomplish a similar convolution result. Furthermore, the architectural program may perform additional pre-processing (e.g., transposition) of the convolution kernel  2042  as needed. Additionally, the instruction specifies a count value of 2. Thus, the instruction at address  2  causes each of the NPUs  126  to read its corresponding word from row  1  of the data RAM  122  and receive the rotated word into the mux-reg  705  and perform a multiply-accumulate operation on the two words. Due to the count value of 2, the instruction also causes each of the NPUs  126  to repeat the operation just described. That is, the sequencer  128  increments the data RAM  122  row address  123  (i.e., to row  2 ) and each NPU  126  reads its corresponding word from row  2  of the data RAM  122  and receives the rotated word into the mux-reg  705  and performs a multiply-accumulate operation on the two words. Thus, for example, assuming the current weight RAM  124  row is 27, after executing the instruction at address  2 , NPU  5  will have accumulated into its accumulator  202  the product of C 0 , 1  and D 27 , 6  and the product of C 0 , 2  and D 27 , 7 . Thus, after the completion of the instructions at addresses  1  and  2 , the product of C 0 , 0  and D 27 , 5 , the product of C 0 , 1  and D 27 , 6 , and the product of C 0 , 2  and D 27 , 7  will have been accumulated into the accumulator  202 , along with all the other accumulated values from previous passes through the loop body. 
     The instructions at addresses  3  and  4  perform a similar operation as the instructions at addresses  1  and  2 , however for the next row of the weight RAM  124 , by virtue of the weight RAM  124  row increment indicator, and for the next three rows of the data RAM  122 , i.e., rows  3  through  5 . That is, with respect to NPU  5 , for example, after the completion of the instructions at addresses  1  through  4 , the product of C 0 , 0  and D 27 , 5 , the product of C 0 , 1  and D 27 , 6 , the product of C 0 , 2  and D 27 , 7 , the product of C 1 , 0  and D 28 , 5 , the product of C 1 , 1  and D 28 , 6 , and the product of C 1 , 2  and D 28 , 7  will have been accumulated into the accumulator  202 , along with all the other accumulated values from previous passes through the loop body. 
     The instructions at addresses  5  and  6  perform a similar operation as the instructions at addresses  3  and  4 , however for the next row of the weight RAM  124 , and for the next three rows of the data RAM  122 , i.e., rows  6  through  8 . That is, with respect to NPU  5 , for example, after the completion of the instructions at addresses  1  through  6 , the product of C 0 , 0  and D 27 , 5 , the product of C 0 , 1  and D 27 , 6 , the product of C 0 , 2  and D 27 , 7 , the product of C 1 , 0  and D 28 , 5 , the product of C 1 , 1  and D 28 , 6 , the product of C 1 , 2  and D 28 , 7 , the product of C 2 , 0  and D 29 , 5 , the product of C 2 , 1  and D 29 , 6 , and the product of C 2 , 2  and D 29 , 7  will have been accumulated into the accumulator  202 , along with all the other accumulated values from previous passes through the loop body. That is, after the completion of the instructions at addresses  1  through  6 , and assuming the weight RAM  124  row at the beginning of the loop body was  27 , NPU  5 , for example, will have used the convolution kernel  2042  to convolve the following 3×3 sub-matrix: 
                                                D27, 5   D27, 6   D27, 7           D28, 5   D28, 6   D28, 7           D29, 5   D29, 6   D29, 7                    
More generally, after the completion of the instructions at addresses  1  through  6 , each of the 512 NPUs  126  will have used the convolution kernel  2042  to convolve the following 3×3 sub-matrix:
 
                                                Dr, n   Dr, n + 1   Dr, n + 2           Dr + 1, n   Dr + 1, n + 1   Dr + 1, n + 2           Dr + 2, n   Dr + 2, n + 1   Dr + 2, n + 2                    
where r is the weight RAM  124  row address value at the beginning of the loop body, and n is the NPU  126  number.
 
     The instruction at address  7  passes through the accumulator  202  value  217  through the AFU  212 . The pass through function passes through a word that is the size (in bits) of the words read from the data RAM  122  and weight RAM  124  (i.e., in the example, 16 bits). Preferably, the user may specify the format of the output, e.g., how many of the output bits are fractional bits, as described in more detail below. Alternatively, rather than specifying a pass through activation function, a divide activation function is specified that divides the accumulator  202  value  217  by a divisor, such as described herein, e.g., with respect to  FIGS. 29A and 30 , e.g., using one of the “dividers”  3014 / 3016  of  FIG. 30 . For example, in the case of a convolution kernel  2042  with a coefficient, such as the one-sixteenth coefficient of the Gaussian blur kernel described above, rather than a pass through function, the activation function instruction at address  7  may specify a divide (e.g., by 16) activation function. Alternatively, the architectural program may perform the divide by 16 on the convolution kernel  2042  coefficients before writing them to the data RAM  122  and adjust the location of the binary point accordingly for the convolution kernel  2402  values, e.g., using the data binary point  2922  of  FIG. 29 , described below. 
     The instruction at address  8  writes the output of the AFU  212  to the row of the weight RAM  124  specified by the current value of the output row register, which was initialized by the instruction at address  0  and which is incremented each pass through the loop by virtue of the increment indicator in the instruction. 
     As may be determined from the example of  FIGS. 24 through 26  having a 3×3 convolution kernel  2402 , the NPUs  126  read the weight RAM  124  approximately every third clock cycle to read a row of the data matrix  2406  and write the weight RAM  124  approximately every 12 clock cycles to write the convolution result matrix. Additionally, assuming an embodiment that includes a write and read buffer such as the buffer  1704  of  FIG. 17 , concurrently with the NPU  126  reads and writes, the processor  100  reads and writes the weight RAM  124  such that the buffer  1704  performs one write and one read of the weight RAM  124  approximately every 16 clock cycles to write the data matrices  2406  and to read the convolution result matrices, respectively. Thus, approximately half the bandwidth of the weight RAM  124  is consumed by the hybrid manner in which the NNU  121  performs the convolution operation. Although the example includes a 3×3 convolution kernel  2042 , other size convolution kernels may be employed, such as 2×2, 4×4, 5×5, 6×6, 7×7, 8×8, etc. matrices, in which case the NNU program will vary. In the case of a larger convolution kernel, a smaller percentage of the weight RAM  124  bandwidth is consumed since the NPUs  126  read the weight RAM  124  a smaller percentage of the time because the count in the rotating versions of the multiply-accumulate instructions is larger (e.g., at addresses  2 ,  4  and  6  of the program of  FIG. 26A  and additional such instructions that would be needed for a larger convolution kernel). 
     Alternatively, rather than writing back the results of the convolutions to different rows of the weight RAM  124  (e.g.,  900 - 1299  and  1300 - 1699 ), the architectural program configures the NNU program to overwrite rows of the input data matrix  2406  after the rows are no longer needed. For example, in the case of a 3×3 convolution kernel, rather than writing the data matrix  2406  into rows  0 - 399  of the weight RAM  124 , the architectural program writes the data matrix  2406  into rows  2 - 401 , and the NNU program is configured to write the convolution results to the weight RAM  124  beginning at row  0  and incrementing each pass through the loop body. In this fashion, the NNU program is overwriting only rows that are no longer needed. For example, after the first pass through the loop body (or more specifically after the execution of the instruction at address  1  which loads in row  0  of the weight RAM  124 ), the data in row  0  can now be overwritten, although the data in rows  1 - 3  will be needed in the second pass through the loop body and are therefore not overwritten by the first pass through the loop body; similarly, after the second pass through the loop body, the data in row  1  can now be overwritten, although the data in rows  2 - 4  will be needed in the second pass through the loop body and are therefore not overwritten by the second pass through the loop body; and so forth. In such an embodiment, the height of each data matrix  2406  (chunk) may be larger (e.g., 800 rows), resulting in fewer chunks. 
     Alternatively, rather than writing back the results of the convolutions to the weight RAM  124 , the architectural program configures the NNU program to write back the results of the convolutions to rows of the data RAM  122  above the convolution kernel  2402  (e.g., above row  8 ), and the architectural program reads the results from the data RAM  122  as the NNU  121  writes them (e.g., using the address of the most recently written data RAM  122  row  2606  of  FIG. 26B , described below). This alternative may be advantageous in an embodiment in which the weight RAM  124  is single-ported and the data RAM  122  is dual-ported. 
     As may be observed from the operation of the NNU  121  according to the embodiment of  FIGS. 24 through 26A , each execution of the program of  FIG. 26A  takes approximately 5000 clock cycles and, consequently, the convolving of the entire 2560×1600 data array  2404  of  FIG. 24  takes approximately 100,000 clock cycles, which may be considerably less than the number of clock cycles required to perform a similar task by conventional methods. 
     Referring now to  FIG. 26B , a block diagram illustrating certain fields of the control register  127  of the NNU  121  of  FIG. 1  according to one embodiment is shown. The status register  127  includes a field  2602  that indicates the address of the most recent row of the weight RAM  124  written by the NPUs  126 ; a field  2606  that indicates the address of the most recent row of the data RAM  122  written by the NPUs  126 ; a field  2604  that indicates the addresses of the most recent row of the weight RAM  124  read by the NPUs  126 ; and a field  2608  that indicates the addresses of the most recent row of the data RAM  122  read by the NPUs  126 . This enables the architectural program executing on the processor  100  to determine the progress of the NNU  121  as it marches through reading and/or writing the data RAM  122  and/or weight RAM  124 . Employing this capability, along with the choice to overwrite the input data matrix as described above (or to write the results to the data RAM  122 , as mentioned above), the data array  2404  of  FIG. 24  may be processed as 5 chunks of 512×1600 rather than 20 chunks of 512×400, for example, as follows. The processor  100  writes a first 512×1600 chunk into the weight RAM  124  starting at row  2  and starts the NNU program (which has a loop count of 1600 and an initialized weight RAM  124  output row of  0 ). As the NNU  121  executes the NNU program, the processor  100  monitors the location/address of the weight RAM  124  output in order to (1) read (using MFNN  1500  instructions) the rows of the weight RAM  124  that have valid convolution results written by the NNU  121  (beginning at row  0 ), and (2) to write the second 512×1600 data matrix  2406  (beginning at row  2 ) over the valid convolution results once they have already been read, so that when the NNU  121  completes the NNU program on the first 512×1600 chunk, the processor  100  can immediately update the NNU program as needed and start it again to process the second 512×1600 chunk. This process is repeated three more times for the remaining three 512×1600 chunks to accomplish high utilization of the NNU  121 . 
     Advantageously, in one embodiment, the AFU  212  includes the ability to efficiently perform an effective division of the accumulator  202  value  217 , as described in more detail below, particularly with respect to  FIGS. 29A and 29B and 30 . For example, an activation function NNU instruction that divides the accumulator  202  value  217  by 16 may be used for the Gaussian blurring matrix described above. 
     Although the convolution kernel  2402  used in the example of  FIG. 24  is a small static convolution kernel applied to the entire data array  2404 , in other embodiments the convolution kernel may be a large matrix that has unique weights associated with the different data values of the data array  2404 , such as is commonly found in convolutional neural networks. When the NNU  121  is used in such a manner, the architectural program may swap the locations of the data matrix and the convolution kernel, i.e., place the data matrix in the data RAM  122  and the convolution kernel in the weight RAM  124 , and the number of rows that may be processed by a given execution of the NNU program may be relatively smaller. 
     Referring now to  FIG. 27 , a block diagram illustrating an example of the weight RAM  124  of  FIG. 1  populated with input data upon which a pooling operation is performed by the NNU  121  of  FIG. 1 . A pooling operation, performed by a pooling layer of an artificial neural network, reduces the dimensions of a matrix of input data (e.g., an image or convolved image) by taking sub-regions, or sub-matrices, of the input matrix and computing either the maximum or average value of the sub-matrices, and the maximum or average values become a resulting matrix, or pooled matrix. In the example of  FIGS. 27 and 28 , the pooling operation computes the maximum value of each sub-matrix. Pooling operations are particularly useful in artificial neural networks that perform object classification or detection, for example. Generally, a pooling operation effectively reduces the size of its input matrix by a factor of the number of elements in the sub-matrix examined, and in particular, reduces the input matrix in each dimension by the number of elements in the corresponding dimension of the sub-matrix. In the example of  FIG. 27 , the input data is a 512×1600 matrix of wide words (e.g., 16 bits) stored in rows  0  through  1599  of the weight RAM  124 . In  FIG. 27 , the words are denoted by their row, column location, e.g., the word in row  0  and column  0  is denoted D 0 , 0 ; the word in row  0  and column  1  is denoted D 0 , 1 ; the word in row  0  and column  2  is denoted D 0 , 2 ; and so forth to the word in row  0  and column  511  is denoted D 0 , 511 . Similarly, the word in row  1  and column  0  is denoted D 1 , 0 ; the word in row  1  and column  1  is denoted D 1 , 1 ; the word in row  1  and column  2  is denoted D 1 , 2 ; and so forth to the word in row  1  and column  511  is denoted D 1 , 511 ; and so forth to the word in row  1599  and column  0  is denoted D 1599 , 0 ; the word in row  1599  and column  1  is denoted D 1599 , 1 ; the word in row  1599  and column  2  is denoted D 1599 , 2 ; and so forth to the word in row  1599  and column  511  is denoted D 1599 , 511 . 
     Referring now to  FIG. 28 , a program listing of an NNU program that performs a pooling operation of the input data matrix of  FIG. 27  and writes it back to the weight RAM  124  is shown. In the example of  FIG. 28 , the pooling operation computes the maximum value of respective 4×4 sub-matrices of the input data matrix. The program loops a number of times through a loop body of instructions at addresses  1  through  10 . An initialize NPU instruction at address  0  specifies the number of times each NPU  126  executes the loop body, which in the example of  FIG. 28  has a loop count value of 400, and a loop instruction at the end of the loop (at address  11 ) decrements the current loop count value and if the result is non-zero causes control to return to the top of the loop body (i.e., to the instruction at address  1 ). The input data matrix in the weight RAM  124  is effectively treated by the NNU program as 400 mutually exclusive groups of four adjacent rows, namely rows  0 - 3 , rows  4 - 7 , rows  8 - 11  and so forth to rows  1596 - 1599 . Each group of four adjacent rows includes 128 4×4 sub-matrices, namely the 4×4 sub-matrices of elements formed by the intersection of the four rows of a group and four adjacent columns, namely columns  0 - 3 ,  4 - 7 ,  8 - 11  and so forth to columns  508 - 511 . Of the 512 NPUs  126 , every fourth NPU  126  of the 512 NPUs  126  (i.e.,  128 ) performs a pooling operation on a respective 4×4 sub-matrix, and the other three-fourths of the NPUs  126  are unused. More specifically, NPUs  0 ,  4 ,  8 , and so forth to NPU  508  each perform a pooling operation on their respective 4×4 sub-matrix whose left-most column number corresponds to the NPU number and whose lower row corresponds to the current weight RAM  124  row value, which is initialized to zero by the initialize instruction at address  0  and is incremented by four upon each iteration of the loop body, as described in more detail below. The 400 iterations of the loop body correspond to the number of groups of 4×4 sub-matrices of the input data matrix of  FIG. 27  (the 1600 rows of the input data matrix divided by 4). The initialize NPU instruction also clears the accumulator  202  to zero. Preferably, the loop instruction at address  11  also clears the accumulator  202  to zero. Alternatively, the maxwacc instruction at address  1  specifies to clear the accumulator  202  to zero. 
     For each iteration of the loop body of the program, the 128 used NPUs  126  concurrently perform 128 pooling operations of the 128 respective 4×4 sub-matrices of the current 4-row group of the input data matrix. More specifically, the pooling operation determines the maximum-valued element of the sixteen elements of the 4×4 sub-matrix. In the embodiment of  FIG. 28 , for each NPU y of the used 128 NPUs  126 , the lower left element of the 4×4 sub-matrix is element Dx,y of  FIG. 27 , where x is the current weight RAM  124  row number at the beginning of the loop body, which is read by the maxwacc instruction at address  1  of the program of  FIG. 28  (also, the row number is initialized by the initialize NPU instruction at address  0 , and incremented at each of the maxwacc instructions at addresses  3 ,  5  and  7 ). Thus, for each loop of the program, the used 128 NPUs  126  write back to a specified row of the weight RAM  124  the corresponding maximum-valued element of the respective 128 4×4 sub-matrices of the current group of rows. The loop body will now be described. 
     At address  1  is a maxwacc instruction that implicitly uses the current weight RAM  124  row, which is preferably held in the sequencer  128  (and which is initialized to zero by the instruction at address  0  for the first pass through the loop body). The instruction at address  1  causes each of the NPUs  126  to read its corresponding word from the current row of the weight RAM  124 , compare the word to the accumulator  202  value  217 , and store in the accumulator  202  the maximum of the two values. Thus, for example, NPU  8  determines the maximum value of the accumulator  202  value  217  and data word Dx, 8  (where “x” is the current weight RAM  124  row) and writes the maximum value back to the accumulator  202 . 
     At address  2  is a maxwacc instruction that specifies to rotate the values in the mux-reg  705  of each NPU  126  to the adjacent NPU  126 , which in this case is the row of input data matrix values just read from the weight RAM  124  in response to the instruction at address  1 . In the embodiment of  FIGS. 27 through 28 , the NPUs  126  are configured to rotate the values of the mux-regs  705  to the left, i.e., from NPU J to NPU J−1, as described above with respect to  FIGS. 24 through 26 . Additionally, the instruction specifies a count value of 3. Thus, the instruction at address  2  causes each of the NPUs  126  to receive the rotated word into the mux-reg  705  and determine the maximum value of the rotated word and the accumulator  202  value  217 , and then to repeat this operation two more times. That is, each NPU  126  receives the rotated word into the mux-reg  705  and determines the maximum value of the rotated word and the accumulator  202  value  217  three times. Thus, for example, assuming the current weight RAM  124  row at the beginning of the loop body is 36, after executing the instruction at addresses  1  and  2 , NPU  8 , for example, will have stored in its accumulator  202  the maximum value of the accumulator  202  at the beginning of the loop body and the four weight RAM  124  words D 36 ,  8  and D 36 , 9  and D 36 , 10  and D 36 , 11 . 
     The maxwacc instructions at addresses  3  and  4  perform a similar operation as the instructions at addresses  1  and  2 , however for the next row of the weight RAM  124 , by virtue of the weight RAM  124  row increment indicator. That is, assuming the current weight RAM  124  row at the beginning of the loop body is 36, after the completion of the instructions at addresses  1  through  4 , NPU  8 , for example, will have stored in its accumulator  202  the maximum value of the accumulator  202  at the beginning of the loop body and the eight weight RAM  124  words D 36 , 8  and D 36 , 9  and D 36 , 10  and D 36 , 11  and D 37 , 8  and D 37 , 9  and D 37 , 10  and D 37 , 11 . 
     The maxwacc instructions at addresses  5  through  8  perform a similar operation as the instructions at addresses  3  and  4 , however for the next two rows of the weight RAM  124 . That is, assuming the current weight RAM  124  row at the beginning of the loop body is 36, after the completion of the instructions at addresses  1  through  8 , NPU  8 , for example, will have stored in its accumulator  202  the maximum value of the accumulator  202  at the beginning of the loop body and the sixteen weight RAM  124  words D 36 , 8  and D 36 , 9  and D 36 , 10  and D 36 , 11  and D 37 , 8  and D 37 , 9  and D 37 , 10  and D 37 , 11  and D 38 , 8  and D 38 , 9  and D 38 , 10  and D 38 , 11  and D 39 , 8  and D 39 , 9  and D 39 , 10  and D 39 , 11 . That is, after the completion of the instructions at addresses  1  through  8 , and assuming the weight RAM  124  row at the beginning of the loop body was  36 , NPU  8 , for example, will have determined the maximum value of the following 4×4 sub-matrix: 
                                                    D36, 8   D36, 9   D36, 10   D36, 11           D37, 8   D37, 9   D37, 10   D37, 11           D38, 8   D38, 9   D38, 10   D38, 11           D39, 8   D39, 9   D39, 10   D39, 11                    
More generally, after the completion of the instructions at addresses  1  through  8 , each of the used 128 NPUs  126  will have determined the maximum value of the following 4×4 sub-matrix:
 
                                                    Dr, n   Dr, n + 1   Dr, n + 2   Dr, n + 3           Dr + 1, n   Dr + 1, n + 1   Dr + 1, n + 2   Dr + 1, n + 3           Dr + 2, n   Dr + 2, n + 1   Dr + 2, n + 2   Dr + 2, n + 3           Dr + 3, n   Dr + 3, n + 1   Dr + 3, n + 2   Dr + 3, n + 3                    
where r is the weight RAM  124  row address value at the beginning of the loop body, and n is the NPU  126  number.
 
     The instruction at address  9  passes through the accumulator  202  value  217  through the AFU  212 . The pass through function passes through a word that is the size (in bits) of the words read from the weight RAM  124  (i.e., in the example, 16 bits). Preferably, the user may specify the format of the output, e.g., how many of the output bits are fractional bits, as described in more detail below. 
     The instruction at address  10  writes the accumulator  202  value  217  to the row of the weight RAM  124  specified by the current value of the output row register, which was initialized by the instruction at address  0  and which is incremented each pass through the loop by virtue of the increment indicator in the instruction. More specifically, the instruction at address  10  writes a wide word (e.g., 16 bits) of the accumulator  202  to the weight RAM  124 . Preferably, the instruction writes the 16 bits as specified by the output binary point  2916 , as describe in more detail below with respect to  FIGS. 29A and 29B  below. 
     As may be observed, each row written to the weight RAM  124  by an iteration of the loop body includes holes that have invalid data. That is, the resulting  133  wide words  1  through  3 ,  5  through  7 ,  9  through  11  and so forth to wide words  509  through  511  are invalid, or unused. In one embodiment, the AFU  212  includes a mux that enables packing of the results into adjacent words of a row buffer, such as the row buffer  1104  of  FIG. 11 , for writing back to the output weight RAM  124  row. Preferably, the activation function instruction specifies the number of words in each hole, and the number of words in the hole is used to control the mux to pack the results. In one embodiment, the number of holes may be specified as values from 2 to 6 in order to pack the output of pooling 3×3, 4×4, 5×5, 6×6 or 7×7 sub-matrices. Alternatively, the architectural program executing on the processor  100  reads the resulting sparse (i.e., including holes) result rows from the weight RAM  124  and performs the packing function using other execution units  112 , such as a media unit using architectural pack instructions, e.g., x86 SSE instructions. Advantageously, in a concurrent manner similar to those described above and exploiting the hybrid nature of the NNU  121 , the architectural program executing on the processor  100  may read the status register  127  to monitor the most recently written row of the weight RAM  124  (e.g., field  2602  of  FIG. 26B ) to read a resulting sparse row, pack it, and write it back to the same row of the weight RAM  124  so that it is ready to be used as an input data matrix for a next layer of the neural network, such as a convolution layer or a classic neural network layer (i.e., multiply-accumulate layer). Furthermore, although an embodiment is described that performs pooling operations on 4×4 sub-matrices, the NNU program of  FIG. 28  may be modified to perform pooling operations on other size sub-matrices such as 3×3, 5×5, 6×6 or 7×7 sub-matrices. 
     As may also be observed, the number of result rows written to the weight RAM  124  is one-fourth the number of rows of the input data matrix. Finally, in the example, the data RAM  122  is not used. However, alternatively, the data RAM  122  may be used rather than the weight RAM  124  to perform a pooling operation. 
     In the example of  FIGS. 27 and 28 , the pooling operation computes the maximum value of the sub-region. However, the program of  FIG. 28  may be modified to compute the average value of the sub-region by, for example, replacing the maxwacc instructions with sumwacc instructions (sum the weight word with the accumulator  202  value  217 ) and changing the activation function instruction at address  9  to divide (preferably via reciprocal multiply, as described below) the accumulated results by the number of elements of each sub-region, which is sixteen in the example. 
     As may be observed from the operation of the NNU  121  according to the embodiment of  FIGS. 27 and 28 , each execution of the program of  FIG. 28  takes approximately 6000 clock cycles to perform a pooling operation of the entire 512×1600 data matrix of  FIG. 27 , which may be considerably less than the number of clock cycles required to perform a similar task by conventional methods. 
     Alternatively, rather than writing back the results of the pooling operation to the weight RAM  124 , the architectural program configures the NNU program to write back the results to rows of the data RAM  122 , and the architectural program reads the results from the data RAM  122  as the NNU  121  writes them (e.g., using the address of the most recently written data RAM  122  row  2606  of  FIG. 26B ). This alternative may be advantageous in an embodiment in which the weight RAM  124  is single-ported and the data RAM  122  is dual-ported. 
     Fixed-Point Arithmetic with User-Supplied Binary Points, Full Precision Fixed-Point Accumulation, User-Specified Reciprocal Value, Stochastic Rounding of Accumulator Value, and Selectable Activation/Output Functions 
     Generally speaking, hardware units that perform arithmetic in digital computing devices may be divided into what are commonly termed “integer” units and “floating-point” units, because they perform arithmetic operations on integer and floating-point numbers, respectively. A floating-point number has a magnitude (or mantissa) and an exponent, and typically a sign. The exponent is an indication of the location of the radix point (typically binary point) with respect to the magnitude. In contrast, an integer number has no exponent, but only a magnitude, and frequently a sign. An advantage of a floating-point unit is that it enables a programmer to work with numbers that can take on different values within on an enormously large range, and the hardware takes care of adjusting the exponent values of the numbers as needed without the programmer having to do so. For example, assume the two floating-point numbers 0.111×10 29  and 0.81×10 31  are multiplied. (A decimal, or base 10, example is used here, although floating-point units most commonly work with base 2 floating-point numbers.) The floating-point unit automatically takes care of multiplying the mantissa, adding the exponents, and then normalizing the result back to a value of 0.8991×10 59 . For another example, assume the same two floating-point numbers are added. The floating-point unit automatically takes care of aligning the binary points of the mantissas before adding them to generate a resulting sum with a value of 0.81111×10 31 . 
     However, the complexity and consequent increase in size, power consumption and clocks per instruction and/or lengthened cycle times associated with floating-point units is well known. Indeed, for this reason many devices (e.g., embedded processors, microcontrollers and relatively low cost and/or low power microprocessors) do not include a floating-point unit. As may be observed from the example above, some of the complexities of floating-point units include logic that performs exponent calculations associated with floating-point addition and multiplication/division (adders to add/subtract exponents of operands to produce resulting exponent value for floating-point multiplication/division, subtracters to determine subtract exponents of operands to determine binary point alignment shift amounts for floating-point addition), shifters that accomplish binary point alignment of the mantissas for floating-point addition, shifters that normalize floating-point results. Additionally, flow proceeds to block units typically require logic to perform rounding of floating-point results, logic to convert between integer and floating-point formats or between different floating-point precision formats (e.g., extended precision, double precision, single precision, half precision), leading zero and leading one detectors, and logic to deal with special floating-point numbers, such as denormal numbers, NANs and infinity. 
     Furthermore, there is the disadvantage of the significant complexity in verification of the correctness of a floating-point unit largely due to the increased number space over which the design must be verified, which may lengthen the product development cycle and time to market. Still further, as described above, floating-point arithmetic implies the storage and use of separate mantissa and exponent fields for each floating-point number involved in the computation, which may increase the amount of storage required and/or reduce precision given an equal amount of storage to store integer numbers. Many of these disadvantages are avoided by the use of integer units that perform arithmetic operations on integer numbers. 
     Frequently, programmers write programs that process fractional numbers, i.e., numbers that are not whole numbers. The programs may run on processors that do not have a floating-point unit or, if they do, the integer instructions executed by the integer units of the processor may be faster. To take advantage of potential performance advantages associated with integer units, the programmer employs what is commonly known as fixed-point arithmetic on fixed-point numbers. Such programs include instructions that execute on integer units to process integer numbers, or integer data. The software is aware that the data is fractional and includes instructions that perform operations on the integer data to deal with the fact that the data is actually fractional, e.g., alignment shifts. Essentially, the fixed-point software manually performs some or all of the functionality that a floating-point unit performs. 
     As used in the present disclosure, a “fixed-point” number (or value or operand or input or output) is a number whose bits of storage are understood to include bits that represent a fractional portion of the fixed-point number, referred to herein as “fractional bits.” The bits of storage of the fixed-point number are comprised in a memory or register, e.g., an 8-bit or 16-bit word in a memory or register. Furthermore, the bits of storage of the fixed-point number are all used to represent a magnitude, and in some cases a bit is used to represent a sign, but none of the storage bits of the fixed-point number are used to represent an exponent of the number. Furthermore, the number of fractional bits, or binary point location, of the fixed-point number is specified in storage that is distinct from the storage bits of the fixed-point number and that in a shared, or global, fashion indicates the number of fractional bits, or binary point location, for a set of fixed-point numbers to which the fixed-point number belongs, such as the set of input operands, accumulated values or output results of an array of processing units, for example. 
     Advantageously, embodiments are described herein in which the ALUs are integer units, but the activation function units include fixed-point arithmetic hardware assist, or acceleration. This enables the ALU portions to be smaller and faster, which facilitates having more ALUs within a given space on the die. This implies more neurons per die space, which is particularly advantageous in a neural network unit. 
     Furthermore advantageously, in contrast to floating-point numbers that require exponent storage bits for each floating-point number, embodiments are described in which fixed-point numbers are represented with an indication of the number of bits of storage that are fractional bits for an entire set of numbers, however, the indication is located in a single, shared storage that globally indicates the number of fractional bits for all the numbers of the entire set, e.g., a set of inputs to a series of operations, a set of accumulated values of the series, a set of outputs. Preferably, the user of the NNU is enabled to specify the number of fractional storage bits for the set of numbers. Thus, it should be understood that although in many contexts (e.g., common mathematics) the term “integer” refers to a signed whole number, i.e., a number not having a fractional portion, the term “integer” in the present context may refer to numbers having a fractional portion. Furthermore, the term “integer” in the present context is intended to distinguish from floating-point numbers for whom a portion of the bits of their individual storage are used to represent an exponent of the floating-point number. Similarly, an integer arithmetic operation, such as an integer multiply or add or compare performed by an integer unit, assumes the operands do not have an exponent and therefore the integer elements of the integer unit, e.g., integer multiplier, integer adder, integer comparator, do not include logic to deal with exponents, e.g., do not shift mantissas to align binary points for addition or compare operations, do not add exponents for multiply operations. 
     Additionally, embodiments are described herein that include a large hardware integer accumulator to accumulate a large series of integer operations (e.g., on the order of 1000 multiply-accumulates) without loss of precision. This enables the NNU to avoid dealing with floating-point numbers while at the same time retaining full precision in the accumulated values without having to saturate them or incur inaccurate results due to overflows. Once the series of integer operations has accumulated a result into the full precision accumulator, the fixed-point hardware assist performs the necessary scaling and saturating to convert the full-precision accumulated value to an output value using the user-specified indications of the number of fractional bits of the accumulated value and the desired number of fractional bits in the output value, as described in more detail below. 
     As described in more detail below, preferably the activation function units may selectively perform stochastic rounding on the accumulator value when compressing it from its full precision form for use as an input to an activation function or for being passed through. Finally, the NPUs may be selectively instructed to apply different activation functions and/or output a variety of different forms of the accumulator value as dictated by the different needs of a given layer of a neural network. 
     Referring now to  FIG. 29A , a block diagram illustrating an embodiment of the control register  127  of  FIG. 1  is shown. The control register  127  may include a plurality of control registers  127 . The control register  127  includes the following fields, as shown: configuration  2902 , signed data  2912 , signed weight  2914 , data binary point  2922 , weight binary point  2924 , ALU function  2926 , round control  2932 , activation function  2934 , reciprocal  2942 , shift amount  2944 , output RAM  2952 , output binary point  2954 , and output command  2956 . The control register  127  values may be written by both an MTNN instruction  1400  and an instruction of an NNU program, such as an initiate instruction. 
     The configuration  2902  value specifies whether the NNU  121  is in a narrow configuration, a wide configuration or a funnel configuration, as described above. The configuration  2902  implies the size of the input words received from the data RAM  122  and the weight RAM  124 . In the narrow and funnel configurations, the size of the input words is narrow (e.g., 8 bits or 9 bits), whereas in the wide configuration, the size of the input words is wide (e.g., 12 bits or 16 bits). Furthermore, the configuration  2902  implies the size of the output result  133 , which is the same as the input word size. 
     The signed data value  2912 , if true, indicates the data words received from the data RAM  122  are signed values, and if false, indicates they are unsigned values. The signed weight value  2914 , if true, indicates the weight words received from the weight RAM  124  are signed values, and if false, indicates they are unsigned values. 
     The data binary point  2922  value indicates the location of the binary point for the data words received from the data RAM  122 . Preferably, the data binary point  2922  value indicates the number of bit positions from the right for the location of the binary point. Stated alternatively, the data binary point  2922  indicates how many of the least significant bits of the data word are fractional bits, i.e., to the right of the binary point. Similarly, the weight binary point  2924  value indicates the location of the binary point for the weight words received from the weight RAM  124 . Preferably, when the ALU function  2926  is a multiply and accumulate or output accumulator, then the NPU  126  determines the number of bits to the right of the binary point for the value held in the accumulator  202  as the sum of the data binary point  2922  and the weight binary point  2924 . Thus, for example, if the value of the data binary point  2922  is 5 and the value of the weight binary point  2924  is 3, then the value in the accumulator  202  has 8 bits to the right of the binary point. When the ALU function  2926  is a sum/maximum accumulator and data/weight word or pass through data/weight word, the NPU  126  determines the number of bits to the right of the binary point for the value held in the accumulator  202  as the data/weight binary point  2922 / 2924 , respectively. In an alternate embodiment, described below with respect to  FIG. 29B , rather than specifying an individual data binary point  2922  and weight binary point  2924 , a single accumulator binary point  2923  is specified. 
     The ALU function  2926  specifies the function performed by the ALU  204  of the NPU  126 . As described above, the ALU functions  2926  may include, but are not limited to: multiply data word  209  and weight word  203  and accumulate product with accumulator  202 ; sum accumulator  202  and weight word  203 ; sum accumulator  202  and the data word  209 ; maximum of accumulator  202  and data word  209 ; maximum of accumulator  202  and weight word  203 ; output accumulator  202 ; pass through data word  209 ; pass through weight word  203 ; output zero. In one embodiment, the ALU function  2926  is specified by an NNU initiate instruction and used by the ALU  204  in response to an execute instruction (not shown). In one embodiment, the ALU function  2926  is specified by individual NNU instructions, such as the multiply-accumulate and maxwacc instructions described above. 
     The round control  2932  specifies which form of rounding is to be used by the rounder  3004  (of  FIG. 30 ). In one embodiment, the rounding modes that may be specified include, but are not limited to: no rounding, round to nearest, and stochastic rounding. Preferably, the processor  100  includes a random bit source  3003  (of  FIG. 30 ) that generates random bits  3005  that are sampled and used to perform the stochastic rounding to reduce the likelihood of a rounding bias. In one embodiment, when the round bit  3005  is one and the sticky bit is zero, the NPU  126  rounds up if the sampled random bit  3005  is true and does not round up if the random bit  3005  is false. In one embodiment, the random bit source  3003  generates the random bits  3005  based on a sampling of random electrical characteristics of the processor  100 , such as thermal noise across a semiconductor diode or resistor, although other embodiments are contemplated. 
     The activation function  2934  specifies the function applied to the accumulator  202  value  217  to generate the output  133  of the NPU  126 . As described above and below in more detail, the activation functions  2934  include, but are not limited to: sigmoid; hyperbolic tangent; softplus; rectify; divide by specified power of two; multiply by a user-specified reciprocal value to accomplish an effective division; pass-through full accumulator; and pass-through the accumulator as a canonical size, which is described in more detail below. In one embodiment, the activation function is specified by an NNU activation function instruction. Alternatively, the activation function is specified by the initiate instruction and applied in response to an output instruction, e.g., write AFU output instruction at address  4  of  FIG. 4 , in which embodiment the activation function instruction at address  3  of  FIG. 4  is subsumed by the output instruction. 
     The reciprocal  2942  value specifies a value that is multiplied by the accumulator  202  value  217  to accomplish a divide of the accumulator  202  value  217 . That is, the user specifies the reciprocal  2942  value as the reciprocal of the actual desired divisor. This is useful, for example, in conjunction with convolution and pooling operations, as described herein. Preferably, the user specifies the reciprocal  2942  value in two parts, as described in more detail with respect to  FIG. 29C  below. In one embodiment, the control register  127  includes a field (not shown) that enables the user to specify division by one of a plurality of built-in divisor values that are the size of commonly used convolution kernels, e.g., 9, 25, 36 or 49. In such an embodiment, the AFU  212  may store reciprocals of the built-in divisors for multiplication by the accumulator  202  value  217 . 
     The shift amount  2944  specifies a number of bits that a shifter of the AFU  212  shifts the accumulator  202  value  217  right to accomplish a divide by a power of two. This may also be useful in conjunction with convolution kernels whose size is a power of two. 
     The output RAM  2952  value specifies which of the data RAM  122  and the weight RAM  124  is to receive the output result  133 . 
     The output binary point  2954  value indicates the location of the binary point for the output result  133 . Preferably, the output binary point  2954  indicates the number of bit positions from the right for the location of the binary point for the output result  133 . Stated alternatively, the output binary point  2954  indicates how many of the least significant bits of the output result  133  are fractional bits, i.e., to the right of the binary point. The AFU  212  performs rounding, compression, saturation and size conversion based on the value of the output binary point  2954  (as well as, in most cases, based on the value of the data binary point  2922 , the weight binary point  2924 , the activation function  2934 , and/or the configuration  2902 ). 
     The output command  2956  controls various aspects of the output result  133 . In one embodiment, the AFU  212  employs the notion of a canonical size, which is twice the size (in bits) of the width specified by the configuration  2902 . Thus, for example, if the configuration  2902  implies the size of the input words received from the data RAM  122  and the weight RAM  124  are 8 bits, then the canonical size is 16 bits; for another example, if the configuration  2902  implies the size of the input words received from the data RAM  122  and the weight RAM  124  are 16 bits, then the canonical size is 32 bits. As described herein, the size of the accumulator  202  is large (e.g., the narrow accumulator  202 B is 28 bits and the wide accumulator  202 A is 41 bits) in order to preserve full precision of the intermediate computations, e.g., 1024 and 512 NNU multiply-accumulate instructions, respectively. Consequently, the accumulator  202  value  217  is larger (in bits) than the canonical size, and the AFU  212  (e.g., CCS  3008  described below with respect to  FIG. 30 ), for most values of the activation function  2934  (except for pass-through full accumulator), compresses the accumulator  202  value  217  down to a value that is the canonical size. A first predetermined value of the output command  2956  instructs the AFU  212  to perform the specified activation function  2934  to generate an internal result that is the same size as the original input words, i.e., half the canonical size, and to output the internal result as the output result  133 . A second predetermined value of the output command  2956  instructs the AFU  212  to perform the specified activation function  2934  to generate an internal result that is twice the size as the original input words, i.e., the canonical size, and to output the lower half of the internal result as the output result  133 ; and a third predetermined value of the output command  2956  instructs the AFU  212  to output the upper half of the canonical size internal result as the output result  133 . A fourth predetermined value of the output command  2956  instructs the AFU  212  to output the raw least-significant word (whose width specified by the configuration  2902 ) of the accumulator  202  as the output result  133 ; a fifth predetermined value instructs the AFU  212  to output the raw middle-significant word of the accumulator  202  as the output result  133 ; and a sixth predetermined value instructs the AFU  212  to output the raw most-significant word of the accumulator  202  as the output result  133 , as described above with respect to  FIGS. 8 through 10 . As described above, outputting the full accumulator  202  size or the canonical size internal result may be advantageous, for example, for enabling other execution units  112  of the processor  100  to perform activation functions, such as the softmax activation function. 
     Although the fields of  FIG. 29A  (and  FIGS. 29B and 29C ) are described as residing in the control register  127 , in other embodiments one or more of the fields may reside in other parts of the NNU  121 . Preferably, many of the fields are included in the NNU instructions themselves and decoded by the sequencer  128  to generate to a micro-operation  3416  (of  FIG. 34 ) that controls the ALUs  204  and/or AFUs  212 . Additionally, the fields may be included in a micro-operation  3414  (of  FIG. 34 ) stored in a media register  118  that controls the ALUs  204  and/or AFUs  212 . In such embodiments, the use of the initialize NNU instruction is minimized, and in other embodiments the initialize NNU instruction is eliminated. 
     As described above, an NNU instruction is capable of specifying to perform ALU operations on memory operands (e.g., word from data RAM  122  and/or weight RAM  124 ) or a rotated operand (e.g., from the mux-regs  208 / 705 ). In one embodiment, an NNU instruction may also specify an operand as a registered output of an activation function (e.g., the output of register  3038  of  FIG. 30 ). Additionally, as described above, an NNU instruction is capable of specifying to increment a current row address of the data RAM  122  or weight RAM  124 . In one embodiment, the NNU instruction may specify an immediate signed integer delta value that is added to the current row to accomplish incrementing or decrementing by a value other than one. 
     Referring now to  FIG. 29B , a block diagram illustrating an embodiment of the control register  127  of  FIG. 1  according to an alternate embodiment is shown. The control register  127  of  FIG. 29B  is similar to the control register  127  of  FIG. 29A ; however, the control register  127  of  FIG. 29B  includes an accumulator binary point  2923 . The accumulator binary point  2923  indicates the location of the binary point for the accumulator  202 . Preferably, the accumulator binary point  2923  value indicates the number of bit positions from the right for the location of the binary point. Stated alternatively, the accumulator binary point  2923  indicates how many of the least significant bits of the accumulator  202  are fractional bits, i.e., to the right of the binary point. In this embodiment, the accumulator binary point  2923  is specified explicitly, rather than being determined implicitly, as described above with respect to the embodiment of  FIG. 29A . 
     Referring now to  FIG. 29C , a block diagram illustrating an embodiment of the reciprocal  2942  of  FIG. 29A  stored as two parts according to one embodiment is shown. A first part  2962  is a shift value that indicates the number of suppressed leading zeroes  2962  in the true reciprocal value that the user desires to be multiplied by the accumulator  202  value  217 . The number of leading zeroes is the number of consecutive zeroes immediately to the right of the binary point. The second part  2694  is the leading zero-suppressed reciprocal  2964  value, i.e., the true reciprocal value with all leading zeroes removed. In one embodiment, the number of suppressed leading zeroes  2962  is stored as four bits and the leading zero-suppressed reciprocal  2964  value is stored as 8-bit unsigned value. 
     To illustrate by example, assume the user desires the accumulator  202  value  217  to be multiplied by the reciprocal of 49. The binary representation of the reciprocal of 49 represented with 13 fractional bits is 0.0000010100111, which has five leading zeroes. In this case, the user populates the number of suppressed leading zeroes  2962  with a value of five, and populates the leading zero-suppressed reciprocal  2964  with a value of 10100111. After the reciprocal multiplier “divider A”  3014  (of  FIG. 30 ) multiplies the accumulator  202  value  217  and the leading zero-suppressed reciprocal  2964  value, it right-shifts the resulting product by the number of suppressed leading zeroes  2962 . Such an embodiment may advantageously accomplish high precision with a relatively small number of bits used to represent the reciprocal  2942  value. 
     Referring now to  FIG. 30 , a block diagram illustrating in more detail an embodiment of an AFU  212  of  FIG. 2  is shown. The AFU  212  includes the control register  127  of  FIG. 1 ; a positive form converter (PFC) and output binary point aligner (OBPA)  3002  that receives the accumulator  202  value  217 ; a rounder  3004  that receives the accumulator  202  value  217  and indication of the number of bits shifted out by the OBPA  3002 ; a random bit source  3003  that generates random bits  3005 , as described above; a first mux  3006  that receives the output of the PFC and OBPA  3002  and the output of the rounder  3004 ; a compressor to canonical size (CC S) and saturator  3008  that receives the output of the first mux  3006 ; a bit selector and saturator  3012  that receives the output of the CCS and saturator  3008 ; a rectifier  3018  that receives the output of the CCS and saturator  3008 ; a reciprocal multiplier  3014  that receives the output of the CCS and saturator  3008 ; a right shifter  3016  that receives the output of the CCS and saturator  3008 ; a hyperbolic tangent (tanh) module  3022  that receives the output of the bit selector and saturator  3012 ; a sigmoid module  3024  that receives the output of the bit selector and saturator  3012 ; a softplus module  3026  that receives the output of the bit selector and saturator  3012 ; a second mux  3032  that receives the outputs of the tanh module  3022 , the sigmoid module  3024 , the softplus module  3026 , the rectifier  3108 , the reciprocal multiplier  3014 , the right shifter  3016  and the passed-through canonical size output  3028  of the CCS and saturator  3008 ; a sign restorer  3034  that receives the output of the second mux  3032 ; a size converter and saturator  3036  that receives the output of the sign restorer  3034 ; a third mux  3037  that receives the output of the size converter and saturator  3036  and the accumulator output  217 ; and an output register  3038  that receives the output of the mux  3037  and whose output is the result  133  of  FIG. 1 . 
     The PFC and OBPA  3002  receive the accumulator  202  value  217 . Preferably, the accumulator  202  value  217  is a full precision value, as described above. That is, the accumulator  202  has a sufficient number of bits of storage to hold an accumulated value that is the sum, generated by the integer adder  244 , of a series of products generated by the integer multiplier  242  without discarding any of the bits of the individual products of the multiplier  242  or sums of the adder  244  so that there is no loss of precision. Preferably, the accumulator  202  has at least a sufficient number of bits to hold the maximum number of accumulations of the products that an NNU  121  is programmable to perform. For example, referring to the program of  FIG. 4  to illustrate, the maximum number of product accumulations the NNU  121  is programmable to perform when in a wide configuration is 512, and the accumulator  202  bit width is 41. For another example, referring to the program of  FIG. 20  to illustrate, the maximum number of product accumulations the NNU  121  is programmable to perform when in a narrow configuration is 1024, and the accumulator  202  bit width is 28. To generalize, the full precision accumulator  202  includes at least Q bits, where Q is the sum of M and log 2 P, where M is the bit width of the integer product of the multiplier  242  (e.g., 16 bits for a narrow multiplier  242 , or 32 bits for a wide multiplier  242 ) and P is the maximum permissible number of the integer products that may be accumulated into the accumulator  202 . Preferably, the maximum number of product accumulations is specified via a programming specification to the programmer of the NNU  121 . In one embodiment, the sequencer  128  enforces a maximum value of the count of a multiply-accumulate NNU instruction (e.g., the instruction at address  2  of  FIG. 4 ), for example, of 511, with the assumption of one previous multiply-accumulate instruction that loads the row of data/weight words  206 / 207  from the data/weight RAM  122 / 124  (e.g., the instruction at address  1  of  FIG. 4 ). 
     Advantageously, by including an accumulator  202  that has a large enough bit width to accumulate a full precision value for the maximum number of allowable accumulations, this simplifies the design of the ALU  204  portion of the NPU  126 . In particular, it alleviates the need for logic to saturate sums generated by the integer adder  244  that would overflow a smaller accumulator and that would need to keep track of the binary point location of the accumulator to determine whether an overflow has occurred to know whether a saturation was needed. To illustrate by example a problem with a design that included a non-full precision accumulator and instead includes saturating logic to handle overflows of the non-full precision accumulator, assume the following.
         (1) The range of the data word values is between 0 and 1 and all the bits of storage are used to store fractional bits. The range of the weight words is between −8 and +8 and all but three of the bits of storage are used to store fractional bits. And, the range of the accumulated values for input to a hyperbolic tangent activation function is between −8 and +8 and all but three of the bits of storage are used to store fractional bits.   (2) The bit width of the accumulator is non-full precision (e.g., only the bit width of the products).   (3) The final accumulated value would be somewhere between −8 and +8 (e.g., +4.2), assuming the accumulator were full precision; however, the products before a “point A” in the series tend to be positive much more frequently, whereas the products after point A tend to be negative much more frequently.
 
In such a situation, an inaccurate result (i.e., a result other than +4.2) might be obtained. This is because at some point before point A the accumulator may be saturated to the maximum +8 value when it should have been a larger value, e.g., +8.2, causing loss of the remaining +0.2. The accumulator could even remain at the saturated value for more product accumulations resulting in loss of even more positive value. Thus, the final value of the accumulator could be a smaller number than it would have been (i.e., less then +4.2) if the accumulator had a full precision bit width.
       

     The PFC  3002  converts the accumulator  202  value  217  to a positive form, if the value is negative, and generates an additional bit that indicates whether the original value was positive or negative, which is passed down the AFU  212  pipeline along with the value. Converting to a positive form simplifies subsequent operations by the AFU  212 . For example, it enables only positive values to be inputted to the tanh  3022  and sigmoid  3024  modules, thus simplifying them. Additionally, it simplifies the rounder  3004  and the saturator  3008 . 
     The OBPA  3002  shifts, or scales, the positive-form value right to align it with the output binary point  2954  specified in the control register  127 . Preferably, the OBPA  3002  calculates the shift amount as a difference that is the number of fractional bits of the output (e.g., specified by the output binary point  2954 ) subtracted from the number of fractional bits of the accumulator  202  value  217  (e.g., specified by the accumulator binary point  2923  or the sum of the data binary point  2922  and the weight binary point  2924 ). Thus, for example, if the accumulator  202  binary point  2923  is 8 (as in the example above) and the output binary point  2954  is 3, then the OBPA  3002  shifts the positive-form value right 5 bits to generate a result provided to the mux  3006  and to the rounder  3004 . 
     The rounder  3004  rounds the accumulator  202  value  217 . Preferably, the rounder  3004  generates a rounded version of the positive-form value generated by the PFC and OBPA  3002  and provides the rounded version to the mux  3006 . The rounder  3004  rounds according to the round control  2932  described above, which may include stochastic rounding using the random bit  3005 , as described above and below. The mux  3006  selects one of its inputs, i.e., either the positive-form value from the PFC and OBPA  3002  or the rounded version thereof from the rounder  3004 , based on the round control  2932  (which may include stochastic rounding, as described herein) and provides the selected value to the CCS and saturator  3008 . Preferably, if the round control  2932  specifies no rounding, then the mux  3006  selects the output of the PFC and OBPA  3002 , and otherwise selects the output of the rounder  3004 . Other embodiments are contemplated in which the AFU  212  performs additional rounding. For example, in one embodiment, the bit selector  3012  rounds based on lost low-order bits when it compresses the bits of the CCS and saturator  3008  output (described below). For another example, in one embodiment, the product of the reciprocal multiplier  3014  (described below) is rounded. For yet another example, in one embodiment, the size converter  3036  rounds when it converts to the proper output size (described below), which may involve losing low-order bits used in the rounding determination. 
     The CCS  3008  compresses the mux  3006  output value to the canonical size. Thus, for example, if the NPU  126  is in a narrow or funnel configuration  2902 , then the CCS  3008  compresses the 28-bit mux  3006  output value to 16 bits; and if the NPU  126  is in a wide configuration  2902 , then the CCS  3008  compresses the 41-bit mux  3006  output value to 32 bits. However, before compressing to the canonical size, if the pre-compressed value is greater than the maximum value expressible in the canonical form, the saturator  3008  saturates the pre-compressed value to the maximum value expressible in the canonical form. For example, if any of the bits of the pre-compressed value left of the most-significant canonical form bit has a 1 value, then the saturator  3008  saturates to the maximum value (e.g., to all 1&#39;s). 
     Preferably, the tanh  3022 , sigmoid  3024  and softplus  3026  modules comprise lookup tables, e.g., programmable logic arrays (PLA), read-only memories (ROM), combinational logic gates, and so forth. In one embodiment, in order to simplify and reduce the size of the modules  3022 / 3024 / 3026 , they are provided an input value that has 3.4 form, i.e., three whole bits and four fractional bits, i.e., the input value has four bits to the right of the binary point and three bits to the left of the binary point. These values are chosen because at the extremes of the input value range (−8, +8) of the 3.4 form, the output values asymptotically approach their minimum/maximum values. However, other embodiments are contemplated that place the binary point at a different location, e.g., in a 4.3 form or a 2.5 form. The bit selector  3012  selects the bits of the CCS and saturator  3008  output that satisfy the 3.4 form criteria, which involves compression, i.e., some bits are lost, since the canonical form has a larger number of bits. However, prior to selecting/compressing the CCS and saturator  3008  output value, if the pre-compressed value is greater than the maximum value expressible in the 3.4 form, the saturator  3012  saturates the pre-compressed value to the maximum value expressible in the 3.4 form. For example, if any of the bits of the pre-compressed value left of the most-significant 3.4 form bit has a 1 value, then the saturator  3012  saturates to the maximum value (e.g., to all 1&#39;s). 
     The tanh  3022 , sigmoid  3024  and softplus  3026  modules perform their respective activation functions (described above) on the 3.4 form value output by the CCS and saturator  3008  to generate a result. Preferably, the result of the tanh  3022  and sigmoid  3024  modules is a 7-bit result in a 0.7 form, i.e., zero whole bits and seven fractional bits, i.e., the input value has seven bits to the right of the binary point. Preferably, the result of the softplus module  3026  is a 7-bit result in a 3.4 form, e.g., in the same form as the input to the module  3026 . Preferably, the outputs of the tanh  3022 , sigmoid  3024  and softplus  3026  modules are extended to canonical form (e.g., leading zeroes added as necessary) and aligned to have the binary point specified by the output binary point  2954  value. 
     The rectifier  3018  generates a rectified version of the output value of the CCS and saturator  3008 . That is, if the output value of the CCS and saturator  3008  (its sign is piped down as describe above) is negative, the rectifier  3018  outputs a value of zero; otherwise, the rectifier  3018  outputs its input value. Preferably, the output of the rectifier  3018  is in canonical form and has the binary point specified by the output binary point  2954  value. 
     The reciprocal multiplier  3014  multiplies the output of the CCS and saturator  3008  by the user-specified reciprocal value specified in the reciprocal value  2942  to generate its canonical size product, which is effectively the quotient of the output of the CCS and saturator  3008  and the divisor that is the reciprocal of the reciprocal  2942  value. Preferably, the output of the reciprocal multiplier  3014  is in canonical form and has the binary point specified by the output binary point  2954  value. 
     The right shifter  3016  shifts the output of the CCS and saturator  3008  by the user-specified number of bits specified in the shift amount value  2944  to generate its canonical size quotient. Preferably, the output of the right shifter  3016  is in canonical form and has the binary point specified by the output binary point  2954  value. 
     The mux  3032  selects the appropriate input specified by the activation function  2934  value and provides the selection to the sign restorer  3034 , which converts the positive form output of the mux  3032  to a negative form if the original accumulator  202  value  217  was a negative value, e.g., to two&#39;s-complement form. 
     The size converter  3036  converts the output of the sign restorer  3034  to the proper size based on the value of the output command  2956 , which values are described above with respect to  FIG. 29A . Preferably, the output of the sign restorer  3034  has a binary point specified by the output binary point  2954  value. Preferably, for the first predetermined value of the output command  2956 , the size converter  3036  discards the bits of the upper half of the sign restorer  3034  output. Furthermore, if the output of the sign restorer  3034  is positive and exceeds the maximum value expressible in the word size specified by the configuration  2902  or is negative and is less than the minimum value expressible in the word size, the saturator  3036  saturates its output to the respective maximum/minimum value expressible in the word size. For the second and third predetermined values, the size converter  3036  passes through the sign restorer  3034  output. 
     The mux  3037  selects either the size converter and saturator  3036  output or the accumulator  202  output  217 , based on the output command  2956 , for provision to the output register  3038 . More specifically, for the first and second predetermined values of the output command  2956 , the mux  3037  selects the lower word (whose size is specified by the configuration  2902 ) of the output of the size converter and saturator  3036 . For the third predetermined value, the mux  3037  selects the upper word of the output of the size converter and saturator  3036 . For the fourth predetermined value, the mux  3037  selects the lower word of the raw accumulator  202  value  217 ; for the fifth predetermined value, the mux  3037  selects the middle word of the raw accumulator  202  value  217 ; and for the sixth predetermined value, the mux  3037  selects the upper word of the raw accumulator  202  value  217 . As describe above, preferably the AFU  212  pads the upper bits of the upper word of the raw accumulator  202  value  217  to zero. 
     Referring now to  FIG. 31 , an example of operation of the AFU  212  of  FIG. 30  is shown. As shown, the configuration  2902  is set to a narrow configuration of the NPUs  126 . Additionally, the signed data  2912  and signed weight  2914  values are true. Additionally, the data binary point  2922  value indicates the binary point for the data RAM  122  words is located such that there are 7 bits to the right of the binary point, and an example value of the first data word received by one of the NPUs  126  is shown as 0.1001110. Still further, the weight binary point  2924  value indicates the binary point for the weight RAM  124  words is located such that there are 3 bits to the right of the binary point, and an example value of the first data word received by the one of the NPUs  126  is shown as 00001.010. 
     The 16-bit product (which is accumulated with the initial zero value of the accumulator  202 ) of the first data and weight words is shown as 000000.1100001100. Because the data binary point  2912  is 7 and the weight binary point  2914  is 3, the implied accumulator  202  binary point is located such that there are 10 bits to the right of the binary point. In the case of a narrow configuration, the accumulator  202  is 28 bits wide, in the example embodiment. In the example, a value  217  of 000000000000000001.1101010100 of the accumulator  202  after all the ALU operations (e.g., all 1024 multiply-accumulates of  FIG. 20 ) are performed is shown. 
     The output binary point  2954  value indicates the binary point for the output is located such that there are 7 bits to the right of the binary point. Therefore, after passing through the OBPA  3002  and CCS  3008 , the accumulator  202  value  217  is scaled, rounded and compressed to the canonical form value of 000000001.1101011. In the example, the output binary point location indicates 7 fractional bits, and the accumulator  202  binary point location indicates 10 fractional bits. Therefore, the OBPA  3002  calculates a difference of 3 and scales the accumulator  202  value  217  by shifting it right 3 bits. This is indicated in  FIG. 31  by the loss of the 3 least significant bits (binary  100 ) of the accumulator  202  value  217 . Further in the example, the round control  2932  value indicates to use stochastic rounding, and in the example it is assumed that the sampled random bit  3005  is true. Consequently, the least significant bit was rounded up because the round bit of the accumulator  202  value  217  (most significant bit of the 3 bits shifted out by the scaling of the accumulator  202  value  217 ) was one and the sticky bit (Boolean OR of the 2 least significant bits of the 3 bits shifted out by the scaling of the accumulator  202  value  217 ) was zero, according to the description above. 
     The activation function  2934  indicates to use a sigmoid function, in the example. Consequently, the bit selector  3012  selects the bits of the canonical form value such that the input to the sigmoid module  3024  has three whole bits and four fractional bits, as described above, i.e., a value of 001.1101, as shown. The sigmoid module  3024  outputs a value that is put in canonical form as shown of 000000000.1101110. 
     The output command  2956  in the example specifies the first predetermined value, i.e., to output the word size indicated by the configuration  2902 , which in this case is a narrow word (8 bits). Consequently, the size converter  3036  converts the canonical sigmoid output value to an 8 bit quantity having an implied binary point located such that 7 bits are to the right of the binary point, yielding an output value of 01101110, as shown. 
     Referring now to  FIG. 32 , a second example of operation of the AFU  212  of  FIG. 30  is shown. The example of  FIG. 32  illustrates operation of the AFU  212  when the activation function  2934  indicates to pass-through the accumulator  202  value  217  in the canonical size. As shown, the configuration  2902  is set to a narrow configuration of the NPUs  126 . 
     In the example, the accumulator  202  is 28 bits wide, and the accumulator  202  binary point is located such that there are 10 bits to the right of the binary point (either because the sum of the data binary point  2912  and the weight binary point  2914  is 10 according to one embodiment, or the accumulator binary point  2923  is explicitly specified as having a value of 10 according to an alternate embodiment, as described above). In the example,  FIG. 32  shows a value  217  of 000001100000011011.1101111010 of the accumulator  202  after all the ALU operations are performed. 
     In the example, the output binary point  2954  value indicates the binary point for the output is located such that there are 4 bits to the right of the binary point. Therefore, after passing through the OBPA  3002  and CCS  3008 , the accumulator  202  value  217  is saturated and compressed to the canonical form value of 111111111111.1111, as shown, that is received by the mux  3032  as the canonical size pass-through value  3028 . 
     In the example, two output commands  2956  are shown. The first output command  2956  specifies the second predetermined value, i.e., to output the lower word of the canonical form size. Since the size indicated by the configuration  2902  is a narrow word (8 bits), which implies a canonical size of 16 bits, the size converter  3036  selects the lower 8 bits of the canonical size pass-through value  3028  to yield an 8 bit value of 11111111, as shown. The second output command  2956  specifies the third predetermined value, i.e., to output the upper word of the canonical form size. Consequently, the size converter  3036  selects the upper 8 bits of the canonical size pass-through value  3028  to yield an 8 bit value of 11111111, as shown. 
     Referring now to  FIG. 33 , a third example of operation of the AFU  212  of  FIG. 30  is shown. The example of  FIG. 33  illustrates operation of the AFU  212  when the activation function  2934  indicates to pass-through the full raw accumulator  202  value  217 . As shown, the configuration  2902  is set to a wide configuration of the NPUs  126  (e.g., 16-bit input words). 
     In the example, the accumulator  202  is 41 bits wide, and the accumulator  202  binary point is located such that there are 8 bits to the right of the binary point (either because the sum of the data binary point  2912  and the weight binary point  2914  is 8 according to one embodiment, or the accumulator binary point  2923  is explicitly specified as having a value of 8 according to an alternate embodiment, as described above). In the example,  FIG. 33  shows a value  217  of 001000000000000000001100000011011.11011110 of the accumulator  202  after all the ALU operations are performed. 
     In the example, three output commands  2956  are shown. The first output command  2956  specifies the fourth predetermined value, i.e., to output the lower word of the raw accumulator  202  value; the second output command  2956  specifies the fifth predetermined value, i.e., to output the middle word of the raw accumulator  202  value; and the third output command  2956  specifies the sixth predetermined value, i.e., to output the upper word of the raw accumulator  202  value. Since the size indicated by the configuration  2902  is a wide word (16 bits),  FIG. 33  shows that in response to the first output command  2956 , the mux  3037  selects the 16-bit value of 0001101111011110; in response to the second output command  2956 , the mux  3037  selects the 16-bit value of 0000000000011000; and in response to the third output command  2956 , the mux  3037  selects the 16-bit value of 0000000001000000. 
     As discussed above, advantageously the NNU  121  operates on integer data rather than floating-point data. This has the advantage of simplifying each NPU  126 , or at least the ALU  204  portion. For example, the ALU  204  need not include adders that would be needed in a floating-point implementation to add the exponents of the multiplicands for the multiplier  242 . Similarly, the ALU  204  need not include shifters that would be needed in a floating-point implementation to align binary points of the addends for the adder  234 . As one skilled in the art will appreciate, floating point units are generally very complex; thus, these are only examples of simplifications to the ALU  204 , and other simplifications are enjoyed by the instant integer embodiments with hardware fixed-point assist that enable the user to specify the relevant binary points. The fact that the ALUs  204  are integer units may advantageously result in a smaller (and faster) NPU  126  than a floating-point embodiment, which further advantageously facilitates the incorporation of a large array of NPUs  126  into the NNU  121 . The AFU  212  portion deals with scaling and saturating the accumulator  202  value  217  based on the, preferably user-specified, number of fractional bits desired in the accumulated value and number of fractional bits desired in the output value. Advantageously, any additional complexity and accompanying increase in size, power consumption and/or time in the fixed-point hardware assist of the AFUs  212  may be amortized by sharing the AFUs  212  among the ALU  204  portions, as described with respect to the embodiment of  FIG. 11 , for example, since the number of AFUs  1112  may be reduced in a shared embodiment. 
     Advantageously, embodiments described herein enjoy many of the benefits associated with reduced complexity of hardware integer arithmetic units over floating-point arithmetic units, while still providing arithmetic operations on fractional numbers, i.e., numbers with a binary point. An advantage of floating-point arithmetic is that it accommodates arithmetic operations on data whose individual values may be anywhere within a very wide range of values (which is effectively limited only by the size of the exponent range, which may be very large). That is, each floating-point number has its own potentially unique exponent value. However, embodiments are described here that recognize and take advantage of the fact that there are certain applications in which the input data is highly parallelized and whose values are within a relatively narrow range such that the “exponent” for all the parallelized values can be the same. Therefore, the embodiments enable the user to specify the binary point location once for all the input values and/or accumulated values. Similarly, the embodiments enable the user to specify the binary point location once for all the output values, recognizing and taking advantage of similar range characteristics of the parallelized outputs. An artificial neural network is an example of such an application, although the embodiments may be employed to perform computations for other applications. By specifying the binary point location for the inputs once, rather than for each individual input number, the embodiments provide more efficient use of memory space (e.g., require less memory) over a floating-point implementation and/or provide an increase in precision for a similar amount of memory since the bits that would be used for an exponent in a floating-point implementation can be used to specify more precision in the magnitude. 
     Further advantageously, the embodiments recognize the potential loss of precision that could be experienced during the accumulation of a large series of integer operations (e.g., overflow or loss of fractional bits of lesser significance) and provide a solution, primarily in the form of a sufficiently large accumulator to avoid loss of precision. 
     Direct Execution of NNU Micro-Operation 
     Referring now to  FIG. 34 , a block diagram illustrating the processor  100  of  FIG. 1  and in more detail portions of the NNU  121  of  FIG. 1  is shown. The NNU  121  includes pipeline stages  3401  of the NPUs  126 . The pipeline stages  3401 , separated by staging registers, include combinatorial logic that accomplish the operation of the NPUs  126  as described herein, such as Boolean logic gates, multiplexers, adders, multipliers, comparators, and so forth. The pipeline stages  3401  receive a micro-operation  3418  from a mux  3402 . The micro-operation  3418  flows down the pipeline stages  3401  and controls their combinatorial logic. The micro-operation  3418  is a collection of bits. Preferably the micro-operation  3418  includes the bits of the data RAM  122  memory address  123 , the weight RAM  124  memory address  125 , the program memory  129  memory address  131 , the mux-reg  208 / 705  control signals  213 / 713 , the mux  802  control signals  803 , and many of the fields of the control register  127  (e.g., of  FIGS. 29A through 29C , for example, among others. In one embodiment, the micro-operation  3418  comprises approximately 120 bits. The mux  3402  receives a micro-operation from three different sources and selects one of them as the micro-operation  3418  for provision to the pipeline stages  3401 . 
     One micro-operation source to the mux  3402  is the sequencer  128  of  FIG. 1 . The sequencer  128  decodes the NNU instructions received from the program memory  129  and in response generates a micro-operation  3416  provided to a first input of the mux  3402 . 
     A second micro-operation source to the mux  3402  is a decoder  3404  that receives microinstructions  105  from a reservation station  108  of  FIG. 1 , along with operands from the GPR  116  and media registers  118 . Preferably, the microinstructions  105  are generated by the instruction translator  104  in response to translating MTNN instructions  1400  and MFNN instructions  1500 , as described above. The microinstructions  105  may include an immediate field that specifies a particular function (which was specified by an MTNN instruction  1400  or an MFNN instruction  1500 ), such as starting and stopping execution of a program in the program memory  129 , directly executing a micro-operation from the media registers  118 , or reading/writing a memory of the NNU  121 , as described above. The decoder  3404  decodes the microinstructions  105  and in response generates a micro-operation  3412  provided to a second input of the mux  3402 . Preferably, in response to some functions  1432 / 1532  of an MTNN/MFNN  1400 / 1500  instruction, it is not necessary for the decoder  3404  to generate a micro-operation  3412  to send down the pipeline  3401 , for example, writing to the control register  127 , starting execution of a program in the program memory  129 , pausing the execution of a program in the program memory  129 , waiting for completion of the execution of a program in the program memory  129 , reading from the status register  127  and resetting the NNU  121 . 
     A third micro-operation source to the mux  3402  is the media registers  118  themselves. Preferably, as described above with respect to  FIG. 14 , a MTNN instruction  1400  may specify a function that instructs the NNU  121  to directly execute a micro-operation  3414  provided from the media registers  118  to a third input of the mux  3402 . The direct execution of a micro-operation  3414  provided by the architectural media registers  118  may be particularly useful for test, e.g., built-in self test (BIST), and debug of the NNU  121 . 
     Preferably, the decoder  3404  generates a mode indicator  3422  that controls the mux  3402  selection. When an MTNN instruction  1400  specifies a function to start running a program from the program memory  129 , the decoder  3404  generates a mode indicator  3422  value that causes the mux  3402  to select the micro-operation  3416  from the sequencer  128  until either an error occurs or until the decoder  3404  encounters an MTNN instruction  1400  that specifies a function to stop running a program from the program memory  129 . When an MTNN instruction  1400  specifies a function that instructs the NNU  121  to directly execute a micro-operation  3414  provided from a media register  118 , the decoder  3404  generates a mode indicator  3422  value that causes the mux  3402  to select the micro-operation  3414  from the specified media register  118 . Otherwise, the decoder  3404  generates a mode indicator  3422  value that causes the mux  3402  to select the micro-operation  3412  from the decoder  3404 . 
     While various embodiments of the present invention have been described herein, it should be understood that they have been presented by way of example, and not limitation. It will be apparent to persons skilled in the relevant computer arts that various changes in form and detail can be made therein without departing from the scope of the invention. For example, software can enable, for example, the function, fabrication, modeling, simulation, description and/or testing of the apparatus and methods described herein. This can be accomplished through the use of general programming languages (e.g., C, C++), hardware description languages (HDL) including Verilog HDL, VHDL, and so on, or other available programs. Such software can be disposed in any known computer usable medium such as magnetic tape, semiconductor, magnetic disk, or optical disc (e.g., CD-ROM, DVD-ROM, etc.), a network, wire line, wireless or other communications medium. Embodiments of the apparatus and method described herein may be included in a semiconductor intellectual property core, such as a processor core (e.g., embodied, or specified, in a HDL) and transformed to hardware in the production of integrated circuits. Additionally, the apparatus and methods described herein may be embodied as a combination of hardware and software. Thus, the present invention should not be limited by any of the exemplary embodiments described herein, but should be defined only in accordance with the following claims and their equivalents. Specifically, the present invention may be implemented within a processor device that may be used in a general-purpose computer. Finally, those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiments as a basis for designing or modifying other structures for carrying out the same purposes of the present invention without departing from the scope of the invention as defined by the appended claims.