Patent Publication Number: US-2018052204-A1

Title: FPGA Clock Signal Self-detection Method

Description:
FIELD OF THE INVENTION 
     The invention relates to a control module technology, in particular to a technology of FPGA clock signal self-detection method. 
     DESCRIPTION OF THE RELATED ART 
     Since FPGA technology has high reliability and is easy to be verified, FPGA technology has a good prospect in nuclear power protection systems. At present, many companies are vigorously developing FPGA-based nuclear power protection systems. 
     Clock signal is an important input signal of an FPGA chip, and all synchronous logic operations in the FPGA chip are based on such signal. At present, stability and reliability of the clock signal depend on the signal generating source. Once failure occurs to the signal generating source, an operation error of the FPGA chip will occur, resulting in safety accident. 
     SUMMARY OF THE INVENTION 
     With regard to the deficiencies in the prior art, the technical problem to be solved by the invention is to provide an FPGA clock signal self-detection method capable of avoiding an operation error caused by clock signal failure and improving operational reliability and safety of the FPGA chip. 
     To solve the above technical problem, the invention provides an FPGA clock signal self-detection method. The method is characterized by comprising introducing two clock signals to an FPGA chip, wherein one clock signal is a first clock signal, and the other clock signal is a second clock signal; 
     using the first clock signal to control all synchronous logic operations in the FPGA chip, and using the second clock signal to detect the first clock signal, comprising the following steps: 
     detecting the first clock signal once when the second clock signal goes through every N cycles; if the number of cycles that the first clock signal goes through within such period of time is less than A or more than B, judging that the first clock signal has an error; 
     wherein N is a preset threshold of cycle number, A is a preset lower limit of cycle number, and B is a preset upper limit of cycle number. 
     Further, frequency of the first clock signal is different from that of the second clock signal. 
     Further, the frequency of the first clock signal is higher than that of the second clock signal. 
     Further, the frequency of the first clock signal is 50 MHZ, and the frequency of the second clock signal is 19.6608 MHZ (N=65536, A=166654, B=166680). 
     The FPGA clock signal self-detection method of the invention is to use the first clock signal to control all synchronous logic operations in the FPGA chip, and use the second clock signal to detect the first clock signal for correctness, thus being capable of improving operational reliability and safety the FPGA chip and avoiding the operation error caused by clock signal failure. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     The technical solution of the invention is described in detail in combination with the embodiment which is not used to limit the invention. Any structures and changes similar to the invention should be incorporated in the protection scope of the invention. 
     An FPGA clock signal self-detection method provided by the embodiment of the invention is characterized by comprising introducing two clock signals to an FPGA chip, wherein one clock signal is a first clock signal, and the other clock signal is a second clock signal; 
     using the first clock signal to control all synchronous logic operations in the FPGA chip, and using the second clock signal to detect the first clock signal, comprising the following steps: 
     detecting the first clock signal once when the second clock signal goes through every N cycles; if the number of cycles that the first clock signal goes through within such period of time is less than A or more than B, judging that the first clock signal has an error; 
     wherein N is a preset threshold of cycle number, A is a preset lower limit of cycle number, and B is a preset upper limit of cycle number. 
     In the embodiment of the invention, frequency of the first clock signal is different from that of the second clock signal, wherein the frequency of the first clock signal is 50 MHZ, and the frequency of the second clock signal is 19.6608 MHZ (N=65536, A=166654, B=166680). 
     The embodiment of the invention is particularly applicable to a system with the FPGA chip as a main controller or important control unit.