Patent Publication Number: US-2016233228-A1

Title: L-shaped capacitor in thin film storage technology

Description:
REFERENCE TO RELATED APPLICATION 
     This application claims priority to U.S. Provisional Application No. 62/112,701 filed on Feb. 6, 2015. 
    
    
     BACKGROUND 
     Flash memory is an electronic non-volatile computer storage medium that can be electrically erased and reprogrammed. It is used in a wide variety of electronic devices and equipment (e.g., consumer electronics, automotive, etc.). Common types of flash memory cells include stacked gate memory cells and split-gate memory cells. Split-gate memory cells have several advantages over stacked gate memory cells, such as lower power consumption, higher injection efficiency, less susceptibility to short channel effects, and over erase immunity. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. 
         FIG. 1  illustrates a cross-sectional view of some embodiments of a non-planar FEOL (front-end-of-the-line) capacitor having a charge trapping dielectric layer. 
         FIG. 2  illustrates a cross-sectional view of some additional embodiments of a non-planar FEOL capacitor having a charge trapping dielectric layer. 
         FIGS. 3A-3B  illustrates cross-sectional views of some additional embodiments of non-planar FEOL capacitors having a charge trapping dielectric layer. 
         FIG. 4  illustrates a cross-sectional view of some embodiments of a non-planar FEOL capacitor located in a periphery region of an integrated chip having an embedded memory cell. 
         FIGS. 5A-5B  some embodiments of BEOL connections of integrated chips having an embedded flash memory and a non-planar FEOL capacitor. 
         FIG. 6  illustrates a flow diagram of some embodiments of a method of forming a non-planar FEOL capacitor having a charge trapping dielectric layer. 
         FIG. 7  illustrates a flow diagram of some additional embodiments of a method of forming a non-planar FEOL capacitor having a charge trapping dielectric layer. 
         FIGS. 8-17  illustrate some embodiments of cross-sectional views showing a method of forming an integrated chip having a non-planar FEOL capacitor having a charge trapping dielectric layer. 
     
    
    
     DETAILED DESCRIPTION 
     The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. 
     Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature&#39;s relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. 
     Embedded memory has become common in modern day integrated chips. Embedded memory is electronic memory that is located on a same integrated chip die as logic functions (e.g., a processor or ASIC). One common type of embedded memory is embedded flash memory. Embedded flash memory cells include a select gate arranged between first and second source/drain regions of a flash memory cell. The flash memory cell also includes a control gate arranged alongside the select gate. The control gate is separated from the select gate by a charge trapping dielectric layer. 
     Data can be written to such a flash memory cell by applying voltages to the select gate and to the control gate. Modern day flash memory typically require high voltages (e.g., voltages greater than or equal to approximately 14 V) to implement erase and program operations. To achieve such high voltages, an integrated charge pump may be used. Integrated charge pumps use capacitors to store charge and then to release the charge to achieve a high voltage. Typically, planar PIP (poly-interpoly-poly) capacitors are used in integrated charge pump circuits. However, such PIP capacitors have a smaller height than select and control gates of flash memory cells. It has been appreciated that during fabrication, the smaller height causes masking layers used during fabrication to be thinner in the area of the capacitor. The thinner masking layers fail to provide for sufficient protection of a substrate underlying the PIP capacitors, resulting in damage to the substrate that degrades device performance. 
     Accordingly, the present disclosure relates to a non-planar FEOL capacitor comprising a charge trapping dielectric layer disposed between electrodes, and an associated method of fabrication. The non-planar FEOL capacitor is formed according to a process that causes the electrodes to have heights that are substantially equal to that of select and control gates of a split-gate memory cell, thereby mitigating damage to an underlying substrate. In some embodiments, the non-planar FEOL capacitor comprises a first electrode disposed over a substrate. A charge trapping dielectric layer is disposed onto the substrate at a position adjacent to the first electrode. The charge trapping dielectric layer comprises an “L” shape, with a lateral component extending in a first direction and a vertical component extending in a second direction. A second electrode is arranged onto the lateral component and is separated from the first electrode by the first component. The non-planar FEOL capacitor provides for a capacitance that is relatively large in comparison to its footprint (due to its lateral and vertical components). Furthermore, the non-planar FEOL capacitor has a relatively low cost since it eliminates the need for patterning of a capacitor top plate. 
       FIG. 1  illustrates a cross-sectional view of some embodiments of a non-planar front-end-of-the-line (FEOL) capacitor  100  having a charge trapping dielectric layer. It will be appreciated that the term FEOL line refers to pre-metal interconnect layers of an integrated chip, such that the FEOL capacitor is formed prior to the formation of a back-end-of-the-line (BEOL) metal interconnect (e.g., device contacts, metal interconnect wires, and via interconnects). 
     The non-planar FEOL capacitor  100  comprises a gate dielectric layer  104  disposed onto a semiconductor substrate  102 . A first electrode  106 , comprising a conductive material, is disposed over the semiconductor substrate  102  at a position overlying the gate dielectric layer  104 . In some embodiments, the first electrode  106  may comprise doped polysilicon or a metal (e.g., aluminum), for example. In some embodiments, the first electrode  106  may abut a top surface of the gate dielectric layer  104 . 
     A charge trapping dielectric layer  108  is disposed over the semiconductor substrate  102  at a position overlying the gate dielectric layer  104  and abutting a sidewall of the first electrode  106 . The charge trapping dielectric layer  108  comprises an “L” shape. The “L” shape has a lateral component extending in a first direction  118  and a vertical component extending in a second direction  120 . In some embodiments, the first direction  118  may be substantially perpendicular to the second direction  120 . The vertical component may abut the sidewall of the first electrode  106 , while the lateral component may abut the top surface of the gate dielectric layer  104 . In some such embodiments, the first electrode  106  and the charge trapping dielectric layer  108  may have bottom surfaces that are substantially aligned along a planar surface. 
     The charge trapping dielectric layer  108  may comprise a tri-layer structure. In some embodiments, the tri-layer structure may comprise an oxide-nitride-oxide (ONO) structure, having a dielectric layer, a nitride layer disposed over the first oxide layer, and a second oxide layer disposed over the nitride layer. In other embodiments, the tri-layer structure may comprises oxide-nano-crystal-oxide (ONCO) structure having first dielectric layer  110 , a plurality of quantum dots  112  disposed over the first dielectric layer  110 , and a second dielectric layer  114  disposed over the first dielectric layer  110  and the plurality of quantum dots  112 . In some embodiments, the first dielectric layer  110  and the second dielectric layer  114  may comprise oxides. In some embodiments, the plurality of quantum dots  112  may comprise silicon quantum dots. In other embodiments, the plurality of quantum dots  112  may comprise other materials such as gallium, gallium arsenide, graphene, etc. 
     A second electrode  116  is arranged over the lateral component of the charge trapping dielectric layer  108 . The second electrode  116  is laterally separated from the first electrode  106  by the vertical component of the charge trapping dielectric layer  108 . In some embodiments, the second electrode  116  may abut the lateral component and the vertical component of the charge trapping dielectric layer  108 . In some embodiments, the second electrode  116  may comprise doped polysilicon or metal, for example. 
     During operation, different voltages are applied to the first electrode  106  and the second electrode  116 . The different voltages will generate a potential difference between the first electrode  106  and the second electrode  116 . The potential difference generates an electric field that extends across the charge trapping dielectric layer  108 . The electric field will cause charges having a first sign (e.g., positive charges) to collect on the first electrode  106  and charges having an opposite, second sign (e.g., negative charges) to collect on the second electrode  116 . The potential of the charges stores energy in the non-planar FEOL capacitor  100 . 
       FIG. 2  illustrates a cross-sectional view of some additional embodiments of a non-planar FEOL capacitor  200  having a charge trapping dielectric layer. 
     The non-planar FEOL capacitor  200  comprises a plurality of electrodes disposed over a gate dielectric layer  104 . The plurality of electrodes comprise a first electrode  106   a  and a second electrode  106   b  arranged onto a top surface of a gate dielectric layer  104 . The plurality of electrodes further comprise a third electrode  116   a , a fourth electrode  116   b , and a fifth electrode  116   c  that are vertically separated from the gate dielectric layer  104  by a charge trapping dielectric layer  202  (e.g., an ONO layer or a ONCO layer). The first electrode  106   a  is arranged laterally between a third electrode  116   a  and a fourth electrode  116   b , and the second electrode  106   b  is arranged laterally between the fourth electrode  116   b  and a fifth electrode  116   c . In various embodiments, the plurality of electrodes may comprise doped polysilicon or metal. 
     The charge trapping dielectric layer  202  comprises a first component  202   a , a second component  202   b , and a third component  202   c  that are laterally separated by the first and second electrodes,  106   a  and  106   b . In some embodiments, the non-planar FEOL capacitor  200  may comprise a symmetric structure. For example, the first component  202   a  and the third component  202   c  may be symmetric with respect to an axis of symmetry extending through the second component  202   b.    
     The first component  202   a  of the charge trapping dielectric layer  202  has an ‘L’ shape comprising a first lateral component that extends vertically below the third electrode  116   a  and a first vertical component that extends between the first electrode  106   a  and the third electrode  116   a . In some embodiments, the first lateral component abuts the gate dielectric layer  104  and the first vertical component abuts sidewalls of the first electrode  106   a  and the third electrode  116   a . The second component  202   b  of the charge trapping dielectric layer  202  is disposed onto an opposite side of the first electrode  106   a  as the first component  202   a . The second component  202   b  has an ‘U’ shape comprising a second lateral component that extends vertically below the fourth electrode  116   b , a second vertical component that extends between the first electrode  106   a  and the fourth electrode  116   b , and a third vertical component that extends between the second electrode  106   b  and the fourth electrode  116   b . The third component  202   c  of the charge trapping dielectric layer  202  is disposed onto an opposite side of the second electrode  106   b  as the second component  202   b . The third component  202   c  has an ‘L’ shape comprising a third lateral component that extends vertically below the fifth electrode  116   c  and a fourth vertical component that extends between the second electrode  106   b  and the fifth electrode  116   c.    
     Each of the components  202   a - 202   c  of the charge trapping dielectric layer  202  have a lateral capacitance and a vertical capacitance. For example, the first component  202   a  of the charge trapping dielectric layer  202  has a vertical capacitance C v  between electrode  116   a  and the semiconductor substrate  102 . The first component  202   a  of the charge trapping dielectric layer  202  also has a lateral capacitance C L  between electrode  116   a  and the electrode  106   a . Therefore, the capacitance of the non-planar FEOL capacitor  200  is equal to a sum of lateral components (between electrodes  106   a  and  116   a , between electrodes  106   a  and  116   b , between electrodes  116   b  and  106   b , and between electrodes  106   b  and  116   c ) and vertical components (between electrode  116   a  and semiconductor substrate  102 , between electrode  116   b  and semiconductor substrate  102  and between electrode  116   c  and semiconductor substrate  102 ) of each of the components  202   a - 202   c  of the charge trapping dielectric layer  202 . 
       FIG. 3A  illustrates a cross-sectional view of some additional embodiments of a non-planar FEOL capacitor  300   a  having a charge trapping dielectric layer. 
     The non-planar FEOL capacitor  300   a  comprises a dielectric material  302  arranged over a semiconductor substrate  102 . In some embodiments, a control gate hard mask layer  304  is located at positions laterally abutting the third electrode  116   a  and the fifth electrode  116   c . In some such embodiments, the control gate hard mask layer  304  may have sidewalls that are substantially aligned with sidewalls of the charge trapping dielectric layer  108 . In some embodiments, the control gate hard mask layer  304  may also overlie the third electrode  116   a , the fourth electrode  116   b  and the fifth electrode  116   c . In such embodiments, the control gate hard mask layer  304  may abut sidewalls of the first component  202   a , the second component  202   b  and the third component  202   c  of the charge trapping dielectric layer  202 . The control gate hard mask layer  304  may comprise silicon nitride (SiN), for example. 
     In some embodiments, a select gate hard mask layer  308  may be arranged over the first electrode  106   a  and the second electrode  106   b . In some embodiments, the select gate hard mask layer  308  may have sidewalls that are substantially aligned with sidewalls of the first electrode  106   a  and the second electrode  106   b . A spacer layer  306  may also be arranged over the outer edges of the third electrode  116   a  and the fifth electrode  116   c . The spacer layer  306  may comprise silicon nitride (SiN), for example. In some embodiments, the spacer layer  306  may have sidewalls that are substantially aligned with sidewalls of the third electrode  116   a  and the fifth electrode  116   c.    
     An inter-layer dielectric (ILD) layer  310  is located over the dielectric material  302 . In some embodiments, the ILD layer  310  may comprise a low-k dielectric layer, an ultra low-k dielectric layer, an extreme low-k dielectric layer, and/or a silicon dioxide layer. A plurality of contacts  312  comprising a conductive material extend vertically through the ILD layer  310  to abut the plurality of electrodes. In some embodiments, the plurality of contacts  312  may connect electrodes  116   a - 116   c  to a first voltage potential and electrodes  106   a - 106   b  and the substrate  102  to a ground terminal. In some embodiments, the plurality of contacts  312  may comprise tungsten, copper, and/or aluminum. Although the plurality of contacts  312  are illustrated as contacting the third electrode  116   a , the fourth electrode  116   b , and the fifth electrode  116   c , it will be appreciated that additional contacts (not shown) may also extend through the ILD layer to abut the first electrode  106   a  and the second electrode  106   b.    
     In some embodiments, shown in  FIG. 3A , a non-planar FEOL capacitor  300   a  may comprise a “cell like” layout with electrodes  116   a - 116   c  having different widths. Such a layout is “cell like” since it is similar to the widths of electrodes in a split-gate flash memory cell, which has a smaller drain electrode with to improve hot electron injection. In such embodiments, electrodes on opposing sides of electrodes  106   a  and  106   b  will have different widths. For example, electrode  116   a  has a first width w 1  while electrode  116   b  has a larger second width w 1 ′ larger than the first width w 1 . 
     In some alternative embodiments, shown in  FIG. 3B , a non-planar FEOL capacitor  300   b  may comprise a “source like” layout with electrodes  116   a ′,  116   b , and  116   c ′ having substantially equal widths. In such embodiments, electrodes on opposing sides of electrodes  106   a  and  106   b  will substantially equal widths. For example, electrode  116   a ′, electrode  116   b  and electrode  116   c ′ have a second width w 1 ′. 
       FIG. 4  illustrates a cross-sectional view of some embodiments of a non-planar FEOL capacitor located in a periphery region of an integrated chip  400  having an embedded memory cell. 
     The integrated chip  400  comprises an embedded memory region  402  and a periphery region  414 . The embedded memory region  402  is separated from the periphery region  414  by a boundary region  410 . The boundary region  410  configured to provide electrical isolation between the embedded memory region  402  and the periphery region  414 . 
     The embedded memory region  402  comprises a plurality of memory cells. In some embodiments, the embedded memory region  402  comprises a pair of split-gate flash cells  403  comprising a first memory cell  403   a  and a second memory cell  403   b . In some embodiments, the pair of split-gate flash cells  403  are disposed over a first well region  404  having a first doping type (e.g., a p-type doping). In some embodiments, the first memory cell  403   a  and the second memory cell  403   b  are mirror images of one another about an axis of symmetry. 
     The pair of split-gate flash cells  403  includes two individual source/drain regions  406   a ,  406   c , and a common source/drain region  406   b  that is shared between the memory cells  403   a ,  403   b . The first and second memory cells,  403   a , and  403   b , respectively include select gates, SG 1  and SG 2 , and control gates, CG 1  and CG 2 , arranged over the cells&#39; respective channel regions. The select gates, SG 1  and SG 2 , comprise a conductive select gate material (e.g., doped polysilicon) and the control gate CG 1  and CG 2  comprise a conductive control gate material (e.g., doped polysilicon). A charge trapping dielectric layer  202  is disposed between the control gates, CG 1  and CG 2 , and the select gates, SG 1  and SG 2 , in the respective memory cells,  403   a  and  403   b . The select gates, SG 1  and SG 2 , are separated by a distance d 1 . In some embodiments, a dielectric material  408  is disposed between the select gates, SG 1  and SG 2 . In such embodiments, a contact  312  comprising a conductive material (e.g., tungsten, titanium nitride, etc.) vertically extends through the dielectric material  408  to the underlying shared drain region  406   b.    
     The boundary region  410  comprises one or more isolation structures  412 . In some embodiments, the one or more isolation structures  412  may comprise shallow trench isolation (STI) structures extending into the semiconductor substrate  102 . In some embodiments, the boundary region  410  further comprises an electrically inactive dummy structure  411 . In some embodiments, the dummy structure  411  comprises a dummy select gate SG d  disposed over the gate dielectric layer  104 . The dummy select gate SG d  abuts a charge trapping dielectric layer  202  on opposing sides. The charge trapping dielectric layer  202  separates the dummy select gate SG d  from dummy control gates CG d . The dummy control gates CG d  and the dummy select gates SG d  are electrically inactive (i.e., are not connected to BEOL metal interconnect layers). 
     The periphery region  414  comprises a capacitor section  416   a  having a non-planar FEOL capacitor  415  and a logic section  416   b  comprising a plurality of logic elements. The non-planar FEOL capacitor  415  comprises a plurality of electrodes E 1 -E 5 . Electrodes E 1  and E 2  comprise a same select gate material as select gates SG 1  and SG 2 . Electrodes E 3 -E 5  comprise a same control gate material as control gates CG 1  and CG 2 . In some embodiments, electrodes E 1 -E 2  are separated by a distance d 2  that is greater than distance d 1 . The plurality of electrodes E 1 -E 5  have top surfaces that are substantially aligned with the top surface of the control gates, CG 1  and CG 2 , and the select gates, SG 1  and SG 2 , of the split-gate flash memory cell  403 . In some embodiments, the non-planar FEOL capacitor  415  is disposed over a second well region  418  having a second doping type (e.g., an n-type doping) that is different than the first doping type of the first well region  404 . 
     The plurality of logic elements may comprise a high-k metal gate transistor  417 . The high-k metal gate transistor  417  comprises a high-k dielectric layer  420  and an overlying replacement metal gate electrode  422 . In some embodiments, the high-k dielectric layer  420  may comprise a bottom high temperature oxide layer and an overlying high-k dielectric layer comprising hafnium oxide (HfO), hafnium silicon oxide (HfSiO), hafnium aluminum oxide (HfAlO), or hafnium tantalum oxide (HfTaO), for example. In some embodiments, an etch-stop layer (not shown) is arranged between the high-k dielectric layer  420  and an overlying replacement metal gate electrode  422 . 
       FIGS. 5A-5B  illustrate some embodiments of metal interconnect schemes for an integrated chip  500  having an embedded flash memory and a non-planar FEOL capacitor. 
     As shown in  FIG. 5A , in some embodiments, electrodes E 1  and E 2  of the non-planar FEOL capacitor  415  are electrically connected to a ground terminal. Electrodes E 3 -E 5  of the non-planar FEOL capacitor  415  are electrically connected to a shared metal interconnect wire at a variable voltage value. The semiconductor substrate  102  is also connected to a ground terminal. By connecting electrodes E 1  and E 2  and the semiconductor substrate  102  to the ground terminal and electrodes E 3 -E 5  to the variable voltage value, a capacitance is formed between electrodes E 1  and E 2  and electrodes E 3 -E 5  and between electrodes E 1  and E 2  and the semiconductor substrate  102 . 
     It will be appreciated that the connections of the non-planar FEOL capacitor  415  will remain the same irrespective of a type of split-gate memory cell within the embedded memory region  402 . For example,  FIG. 5A  illustrates a split-gate memory cell  502  without a drain control gate. In such a split-gate memory cell  502  the select gates SG 1  and SG 2  are connected together.  FIG. 5B  illustrates a split-gate memory cell  504  having a drain control gate CG 3  located between select gates SG 1  and SG 2 . In such a split-gate memory cell  504  the select gates SG 1  and SG 2  are connected to a ground terminal. 
       FIG. 6  illustrates a flow diagram of some embodiments of a method  600  of forming an integrated chip having a non-planar FEOL capacitor with a charge trapping dielectric layer. 
     While the disclosed methods (e.g., methods  600  and  700 ) are illustrated and described herein as a series of acts or events, it will be appreciated that the illustrated ordering of such acts or events are not to be interpreted in a limiting sense. For example, some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein. In addition, not all illustrated acts may be required to implement one or more aspects or embodiments of the description herein. Further, one or more of the acts depicted herein may be carried out in one or more separate acts and/or phases. 
     At  602 , an embedded flash memory cell is formed. The embedded flash memory cell has a select gate separated from control gate by charge trapping dielectric layer. 
     At  604 , a non-planar FEOL capacitor is concurrently formed along with the embedded flash memory cell. The non-planar FEOL capacitor comprises a plurality of electrodes with top surface substantially planar with control gate and select gate of embedded flash memory cell. It will be appreciated that the term concurrently does not mean that all fabrication steps used to form the non-planar FEOL capacitor and the embedded flash memory cell are performed at the same time, but rather that at least one step fabrication steps used to form the non-planar FEOL capacitor and the embedded flash memory cell are performed at the same time 
     At  606 , a dielectric material is formed over the embedded flash memory cell and the non-planar FEOL capacitor. 
     At  608 , contacts are formed within the dielectric material. 
       FIG. 7  illustrates a flow diagram of some additional embodiments of a method  700  of forming an integrated chip having a non-planar FEOL capacitor with a charge trapping dielectric layer. 
     At  702 , a select gate layer is formed over a substrate. 
     At  704 , the select gate material is patterned to form select gates within a split-gate flash memory cell and a first plurality of capacitor electrodes within a non-planar FEOL capacitor. 
     At  706 , a charge trapping dielectric layer is formed over the select gates and the first plurality of capacitor electrodes. 
     At  708 , a control gate layer is formed over the charge trapping dielectric layer. 
     At  710 , the control gate layer is patterned to form control gates within the split-gate flash memory cell and a second plurality of capacitor electrodes within the non-planar FEOL capacitor. 
     At  712 , perform etch back process to recess control gates and second plurality of capacitor electrodes. 
     At  714 , a control gate disposed between select gates of the split-gate flash memory cell (i.e., a drain side control gate) may be removed. 
     At  716 , the charge trapping dielectric layer is selectively removed. 
     At  718 , a dielectric material is formed over the substrate. 
     At  720 , a planarization process is performed to make upper surfaces of select gates, control gates, and capacitor electrodes co-planar. 
     At  722 , contacts are formed within an inter-level dielectric layer formed over the dielectric material. 
       FIGS. 8-17  illustrate some embodiments of cross-sectional views showing a method of forming an integrated chip having a non-planar FEOL capacitor with a charge trapping dielectric layer. Although  FIGS. 8-17  are described in relation to method  700 , it will be appreciated that the structures disclosed in  FIGS. 8-17  are not limited to such a method, but instead may stand alone as structures independent of the method. 
       FIG. 8  illustrates some embodiments of a cross-sectional view  800  of an integrated chip corresponding to acts  702 - 704 . 
     As shown in cross-sectional view  800 , the integrated chip comprises a semiconductor substrate  102  having an embedded memory region  402  and a periphery region  414 , which are separated by a boundary region  410 . The embedded memory region  402  comprises a first well region  404  having a first doping type (e.g., a p-type doping). The periphery region  414  comprises a second well region  418  having a second doping type different than the first doping type (e.g., an n-type doping). 
     A gate dielectric layer  802  (e.g., SiO 2 ) is formed over a semiconductor substrate  102 . In some embodiments, the gate dielectric layer  802  comprises an oxide (e.g., SiO 2 ) formed by way of a thermal process or by a deposition process (e.g., chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), etc.). A select gate layer  804  is formed over the gate dielectric layer  802 . In some embodiments, the select gate layer  804  may comprise doped polysilicon or metal formed by a deposition process (e.g., CVD, PVD, ALD, etc.) 
     After being deposited, the select gate layer  804  is patterned according to a select gate hard mask layer  806  configured to define select gate material stacks  808 . In some embodiments, the select gate hard mask layer  806  may comprise a first hard mask layer  806   a  and a second overlying hard mask layer  806   b . The select gate hard mask layer  806  may be patterned according to a photolithography process. The select gate layer  804  is then selectively exposed to an etchant in areas not masked by the select gate hard mask layer  806  to form select gates SG 1  and SG 2  within the embedded memory region  402 , a dummy select gate SG d  within the boundary region  410 , and a first plurality of capacitor electrodes E 1 -E 2  within the periphery region  414 . In some embodiments, the select gate hard mask layer  806  may comprise one or more of an oxide (e.g., SiO 2 ) or a nitride (e.g., SiN). 
       FIG. 9  illustrates some embodiments of a cross-sectional view  900  of an integrated chip corresponding to acts  706 - 708 . 
     As shown in cross-sectional view  900 , a charge trapping dielectric layer  902  is formed over the semiconductor substrate  102  and the select gate material stacks  808 . The charge trapping dielectric layer  902  abuts the gate dielectric layer  802  between the select gate material stacks  808 , the sidewalls of the patterned select gate layer  804 , and top surfaces of the select gate hard mask layer  806 . In some embodiments, the charge trapping dielectric layer  902  may comprise a tri-layer structure. In some embodiments, the tri-layer structure may have a first dielectric layer  110 , a plurality of quantum dots  112  disposed over the first dielectric layer  110 , and a second dielectric layer  114  disposed over the first dielectric layer  110  and the plurality of quantum dots  112 . 
     A control gate layer  904  is conformally formed onto the charge trapping dielectric layer  902 . In some embodiments, the control gate layer  904  may comprise doped polysilicon. In some embodiments, the control gate layer  904  may comprise doped polysilicon or metal formed by a deposition process (e.g., CVD, PVD, ALD, etc.). A spacer layer  906  is conformally formed onto the control gate layer  904 . In some embodiments, spacer layer  906  may comprise an oxide (e.g., SiO 2 ) or a nitride (e.g., SiN) formed by a deposition process. 
       FIG. 10  illustrates some embodiments of a cross-sectional view  1000  of an integrated chip corresponding to act  710 . 
     As shown in cross-sectional view  1000 , the control gate layer  904  is patterned. In some embodiments, the control gate layer  1002  is patterned by performing a first etching process, which exposes the substrate to a first etchant  1004  configured to remove portions of the control gate layer  1002  and the spacer layer  306 . The first etching process leaves a vertical portion of the control gate layer  1002  and the spacer layer  306  disposed along sidewalls of the charge trapping dielectric layer  902 . In some embodiments, the first etchant  1004  comprises a dry etch (e.g., a plasma etch with tetrafluoromethane (CF 4 ), sulfur hexafluoride (SF 6 ), nitrogen trifluoride (NF 3 ), etc.). 
       FIG. 11  illustrates some embodiments of a cross-sectional view  1100  of an integrated chip corresponding to act  712 . 
     As shown in cross-sectional view  1100 , an etch back process is performed to recess the control gate layer  1002  to form control gates CG 1 -CG 3  within the embedded memory region  402  and a second plurality of capacitor electrodes E 3 -E 5  within the periphery region  414 . The etch back process selectively exposes the control gate layer  1002  to a second etchant  1104 . The second etchant  1104  has a large etching selectivity, which etches the control gate layer  1002  (e.g., polysilicon) without substantially etching the spacer layer  306  (e.g., oxide and/or nitride material). This etch back process reduces the height of the control gate layer  1002  so that the control gates CG 1 -CG 3  and the second plurality of capacitor electrodes E 3 -E 5  have upper surfaces are substantially aligned with upper surfaces of the select gates SG 1 , SG 2  and the first plurality of capacitor electrodes E 1 -E 2 . In some embodiments, a masking layer  1102  may be disposed over the substrate the charge trapping dielectric layer  902 . In some embodiments, the masking layer  1102  may comprise a bottom antireflective coating (BARC) formed on the substrate through a spin-coating or other appropriate technique. The BARC has a substantially uniform thickness between the embedded memory region  402  and the periphery region  414   
       FIG. 12  illustrates some embodiments of a cross-sectional view  1200  of an integrated chip corresponding to act  714 . 
     As shown in cross-sectional view  1200 , a control gate hard mask layer  304  is formed onto the control gates CG 1 -CG 3  and the second plurality of capacitor electrodes E 3 -E 5 . The control gate hard mask layer  304  may be formed by a deposition process and a subsequent etching process. In some embodiments, the control gate hard mask layer  304  may comprise an oxide or a nitride, for example. 
       FIGS. 13-14  illustrate some embodiments of cross-sectional views,  1300  and  1400 , of an integrated chip corresponding to act  714 . 
     As shown in cross-sectional view  1300 , a masking structure  1302  is formed over the substrate. In some embodiments, the masking structure  1302  may comprise a BARC  1304  formed on the substrate through a spin-coating or other appropriate technique. The BARC  1304  has a substantially uniform thickness between the embedded memory region  402  and the periphery region  414 . The BARC  1304  is configured to protect the substrate during a subsequently-performed etch. The masking structure  1302  may further comprise a photoresist layer  1306  overlying the BARC  1304 . The masking structure  1302  comprises an opening  1308  overlying the control gate CG 3  of the split-gate flash memory cell (i.e., between select gates SG 1  and SG 2 ). 
     As shown in cross-sectional view  1400 , a second etching process is carried out to remove control gate CG 3  (i.e., drain side control gate). The second etching process selectively exposes the control gate CG 3  to a third etchant  1402  according to the masking structure  1302 . The third etchant  1402  is configured to remove the control gate CG 3 . In some embodiments, the third etchant  1402  comprises a dry etchant. 
       FIG. 15  illustrates some embodiments of a cross-sectional view  1500  of an integrated chip corresponding to act  716 . 
     As shown in cross-sectional view  1500 , the charge trapping dielectric layer  202  is selectively removed. The charge trapping dielectric layer  202  may be removed by exposing the substrate to a fourth etchant  1502 . 
     Source/drain extension regions (not shown) may be subsequently formed within the first well region  404  according to openings in the above layers. The source and drain regions may be formed by implanting the substrate with a dopant species, such as boron (B) or phosphorous (P), for example. The dopant species may be subsequently driven into the semiconductor substrate  102  by an anneal process. 
       FIG. 16  illustrates some embodiments of a cross-sectional view  1600  of an integrated chip corresponding to acts  718 - 720 . 
     As shown in cross-sectional view  1600 . A dielectric material  302  is formed onto the semiconductor substrate  102  and a planarization process is subsequently performed. The planarization process remove materials overlying line  1602  so as to make upper surfaces of select gates SG 1  and SG 2 , control gates CG 1  and CG 2 , and capacitor electrodes E 1 -E 5  co-planar. In some embodiments the dielectric material  302  may comprise silicon oxide, formed by way of a deposition process (e.g., CVD, PVD, etc.). In some embodiments, the planarization process may comprise a chemical mechanical polishing (CMP) process, for example. 
       FIG. 17  illustrates some embodiments of a cross-sectional view  1700  of an integrated chip corresponding to act  722 . 
     As shown in cross-sectional view  1700 , contacts  312  are formed within an inter-layer dielectric (ILD) layer  310  overlying the dielectric material  302 . The contacts  312  may be formed by selectively etching the ILD layer  310  to form openings, and by subsequently depositing a conductive material within the openings. In some embodiments, the conductive material may comprise tungsten (W) or titanium nitride (TiN), for example. 
     Therefore, the present disclosure relates to a non-planar FEOL (front-end-of-the-line) capacitor comprising a charge trapping dielectric layer disposed between electrodes, and an associated method of fabrication. 
     In some embodiments, the present disclosure relates to an integrated capacitor. The integrated capacitor comprises a first electrode disposed over a substrate. A charge trapping dielectric layer is disposed onto the substrate at a position adjacent to the first electrode. The charge trapping dielectric layer comprises an “L” shape, with a lateral component extending in a first direction and a vertical component extending in a second direction different than the first direction. A second electrode is arranged onto the lateral component and separated from the first electrode by the vertical component 
     In other embodiments, the present disclosure relates to an integrated chip. The integrated chip comprises a gate dielectric layer disposed over a semiconductor substrate, and a first electrode abutting a top surface of the gate dielectric layer. A charge trapping dielectric layer abuts the top surface of the gate dielectric layer at a position adjacent to the first electrode. The charge trapping dielectric layer comprises a lateral component extending in a first direction and a vertical component extending in a second direction different than the first direction. A second electrode is arranged onto the lateral component and separated from the first electrode by the vertical component. A split-gate flash memory cell is disposed over the substrate at a position that is laterally separated from the first electrode by a boundary region. 
     In yet other embodiments, the present disclosure relates to a method of forming an integrated chip. The method comprises forming a select gate layer over a semiconductor substrate having an embedded memory region laterally separated from a periphery region, and patterning the select gate layer to form select gates within the embedded memory region and a first plurality of capacitor electrodes within the periphery region. The method further comprises forming a charge trapping dielectric layer over the select gates and the first plurality of capacitor electrodes. The method further comprises forming a control gate layer over the charge trapping dielectric layer, and patterning the control gate layer to form control gates within the embedded memory region and a second plurality of capacitor electrodes within the periphery region. 
     The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.