Patent Publication Number: US-11639054-B2

Title: Wafer structure

Description:
FIELD OF THE INVENTION 
     The present disclosure relates to a wafer structure, and more particularly to a wafer structure fabricated by a semiconductor process and applied to an inkjet chip for inkjet printing. 
     BACKGROUND OF THE INVENTION 
     In view of the common printers currently on the market, in addition to a laser printer, an inkjet printer is another model widely used. The inkjet printer has the advantages of low price, easy operation and low noise. Moreover, the inkjet printer is capable of printing on various printing media, such as paper and photo paper. The printing quality of an inkjet printer mainly depends on the design factors of an ink cartridge. In particular, the design factor of an inkjet chip releasing ink droplets to the printing medium is regarded as an important consideration in the design factors of the ink cartridge. 
     In addition, as the inkjet chip is pursuing the printing quality requirements of higher resolution and higher printing speed, the price of the inkjet printer has dropped very fast in the highly competitive inkjet printing market. Therefore, the manufacturing cost of the inkjet chip combined with the ink cartridge and the design cost of higher resolution and higher printing speed are key factors that determine market competitiveness. 
     However, the inkjet chip produced in the current inkjet printing market is made from a wafer structure by a semiconductor process. The conventional inkjet chip is all fabricated with the wafer structure of less than 6 inches. Moreover, in the pursuit of higher resolution and higher printing speed at the same time, the design of the printing swath of the inkjet chip needs to be changed to be larger and longer, so that the printing speed can be greatly increased. In this way, the overall area required for the inkjet chip is larger. Therefore, the number of inkjet chips required to be manufactured on a wafer structure with a limited area of less than 6 inches is quite limited, and the manufacturing cost cannot be effectively reduced. 
     For example, the printing swath of an inkjet chip produced from a wafer structure of less than 6 inches is 0.56 inches, and can be diced to generate 334 inkjet chips at most. Furthermore, the wafer structure of less than 6 inches is utilized to produce the inkjet chip having the printing swath more than 1 inch or meeting the printing swath of one A4 page width (8.3 inches), so that the printing quality requirements of higher resolution and higher printing speed is achieved. Under the printing quality requirements, the number of inkjet chips required to be produced on the wafer structure with the limited area less than 6 inches is quite limited, and the number is even smaller. If the inkjet chips are produced on the wafer structure with the limited area of less than 6 inches, there is a waste of remaining blank area. These empty areas occupy more than 20% of the entire area of the wafer structure, and it is quite wasteful. Furthermore, the manufacturing cost cannot be effectively reduced. 
     Therefore, how to meet the pursuit of lower manufacturing cost of the inkjet chip in the inkjet printing market and the printing quality pursuit of higher resolution and higher printing speed is a main subject developed in the present disclosure. 
     SUMMARY OF THE INVENTION 
     An object of the present disclosure provides a wafer structure including a chip substrate and a plurality of inkjet chips. The chip substrate is fabricated by a semiconductor process on a wafer of at least 12 inches or more, so that more inkjet chips required are arranged on the chip substrate. Furthermore, a first inkjet chip and a second inkjet chip having different sizes of printing swath are directly generated in the same inkjet chip semiconductor process, and arranged in a printing inkjet design for higher resolution and higher performance. The wafer structure is diced into the first inkjet chip and the second inkjet chip used in inkjet printing to achieve the lower manufacturing cost of the inkjet chips and the printing quality pursuit of higher resolution and higher printing speed. 
     In accordance with an aspect of the present disclosure, a wafer structure is provided and includes a chip substrate and a plurality of inkjet chips. The chip substrate is a silicon substrate and fabricated by a semiconductor process on a wafer of at least 12 inches. The plurality of inkjet chips include at least one first inkjet chip and at least one second inkjet chip directly formed on the chip substrate by the semiconductor process, respectively, whereby the inkjet chips are diced into the at least one first inkjet chip and the at least one second inkjet chip, to be implemented for inkjet printing. Each of the first inkjet chip and the second inkjet chip includes a plurality of ink-drop generators produced by the semiconductor process and formed on the chip substrate. In the first inkjet chip and the second inkjet chip, the plurality of ink-drop generators are arranged in a longitudinal direction to form a plurality of longitudinal axis array groups having a pitch maintained between two adjacent ink-drop generators in the longitudinal direction, and arranged in a horizontal direction to form a plurality of horizontal axis array groups having a central stepped pitch maintained between two adjacent ink-drop generators in the horizontal direction. The central stepped pitch is at least equal to 1/600 inches or less. 
     The above contents of the present disclosure will become more readily apparent to those ordinarily skilled in the art after reviewing the following detailed description and accompanying drawings, in which: 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG.  1    is a schematic view illustrating a wafer structure according to an embodiment of the present disclosure; 
         FIG.  2    is a schematic cross-sectional view illustrating the ink-drop generators on the wafer structure according to the embodiment of the present disclosure; 
         FIG.  3 A  is a schematic view illustrating the ink-supply channels, the manifolds and the ink-supply chamber arranged on the inkjet chip of the wafer structure according to the embodiment of the present disclosure, 
         FIG.  3 B  is a partial enlarged view illustrating the region C of  FIG.  3 A ; 
         FIG.  3 C  is a schematic view illustrating the ink-supply channels and the inkjet control circuit zone arranged on the inkjet chip of the wafer structure according to another embodiment of the present disclosure; 
         FIG.  3 D  is a schematic view illustrating the nozzles formed and arranged on the inkjet chip of  FIG.  3 A ; 
         FIG.  4    is a schematic circuit diagram illustrating the resistance heating layer controlled and excited by the conductive layer for heating according to the embodiment of the present disclosure; 
         FIG.  5    is an enlarged view illustrating the ink-drop generators formed and arranged on the wafer structure according to the embodiment of the present disclosure; and 
         FIG.  6    is a schematic view illustrating an internal carrying system applied to an inkjet printer. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     The present disclosure will now be described more specifically with reference to the following embodiments. It is to be noted that the following descriptions of preferred embodiments of this invention are presented herein for purpose of illustration and description only. It is not intended to be exhaustive or to be limited to the precise form disclosed. 
     Please refer to  FIG.  1   . The present disclosure provides a wafer structure  2 . The wafer structure  2  includes a chip substrate  20  and a plurality of inkjet chips  21 . Preferably but not exclusively, the chip substrate  20  is a silicon substrate and fabricated by a semiconductor process on a wafer of at least 12 inches. In an embodiment, the chip substrate  20  is fabricated by the semiconductor process on a 12-inch wafer. In another embodiment, the chip substrate  20  is fabricated by the semiconductor process on a 16-inch wafer. 
     In the embodiment, the plurality of inkjet chips  21  include at least one first inkjet chip  21 A and at least one second inkjet chip  21 B directly formed on the chip substrate  20  by the semiconductor process, whereby the inkjet chips  21  are diced into the at least one first inkjet chip  21 A and at least one second inkjet chip  21 B, to be implemented for inkjet printing of a printhead  111  (referred to  FIG.  6   ). In the embodiment, each of the first inkjet chip  21 A and the second inkjet chip  21 B includes a plurality of ink-drop generators  22 . The plurality of ink-drop generators  22  are produced by the semiconductor process and formed on the chip substrate  20 . As shown in  FIG.  2   , each of the ink-drop generators  22  includes a thermal-barrier layer  221 , a resistance heating layer  222 , a conductive layer  223 , a protective layer  224 , a barrier layer  225 , an ink-supply chamber  226  and a nozzle  227 . In the embodiment, the thermal-barrier layer  221  is formed on the chip substrate  20 . The resistance heating layer  222  is formed on the thermal-barrier layer  221 . The conductive layer  223  and a part of the protective layer  224  are formed on the resistance heating layer  222 . A rest part of the protective layer  224  is formed on the conductive layer  223 . The barrier layer  225  is formed on the protective layer  224 . Moreover, the ink-supply chamber  226  and the nozzle  227  are integrally formed in the barrier layer  225 . In the embodiment, a bottom of the ink-supply chamber  226  is in communication with the protective layer  224 . A top of the ink-supply chamber  226  is in communication with the nozzle  227 . In other words, the ink-drop generator  22  of the inkjet chip  21  is fabricated by implementing the semiconductor process on the chip substrate  20 , and it is described as the followings. Firstly, a thin film of the thermal-barrier layer  221  is formed on the chip substrate  20 . Secondly, the heating resistance layer  222  and the conductive layer  223  are successively disposed thereon by sputtering, and the required size is determined by the process of photolithography. Afterwards, the protective layer  224  is coated thereon through a sputtering device or a chemical vapor deposition (CVD) device. Then, the ink-supply chamber  226  is formed on the protective layer  224  by dry film lamination, and a dry film is coated to form the nozzle  227  by dry film lamination, so that the barrier layer  225  is integrally formed on the protective layer  224 . In this way, the ink-supply chamber  226  and the nozzle  227  are integrally formed in the barrier layer  225 . Alternatively, in another embodiment, a polymer film is formed on the protective layer  224  to directly define the ink-supply chamber  226  and the nozzle  227  by a photolithography process. In this way, the ink-supply chamber  226  and the nozzle  227  are integrally formed in the barrier layer  225 . The bottom of the ink-supply chamber  226  is in communication with the protective layer  224 , and the top of the ink-supply chamber  226  is in communication with the nozzle  227 . In the embodiment, the chip substrate  20  is a silicon substrate. The thermal-barrier layer  221  is made of a silicon dioxide (SiO 2 ) material. The resistance heating layer  222  is made of a tantalum aluminide (TaAl) material. The conductive layer  223  is made of an aluminum (Al) material. The protective layer  224  is formed by stacking a second protective layer  224 B disposed above on a first protective layer  224 A disposed below. The first protective layer  224 A is made of a silicon nitride (Si 3 N 4 ) material. The second protective layer  224 B is made of a silicon carbide (SiC) material. The barrier layer  225  is made of a polymer material. 
     Certainly, in the embodiment, the ink-drop generator  22  of the inkjet chip  21  is fabricated by implementing the semiconductor process on the wafer substrate  20 . Further in the process of determining the required size by the lithographic etching process, as shown in  FIGS.  3 A to  3 B , at least one ink-supply channel  23  and a plurality of manifolds  24  are defined. Then, the ink-supply chamber  226  is formed on the protective layer  224  by dry film lamination, and a dry film is coated to form the nozzle  227  by dry film lamination, so that the barrier layer  225  is integrally formed on the protective layer  224  as shown in  FIG.  2   . Moreover, the ink-supply chamber  226  and the nozzle  227  are integrally formed in the barrier layer  225 . In the embodiment, the bottom of the ink-supply chamber  226  is in communication with the protective layer  224 , and the top of the ink-supply chamber  226  is in communication with the nozzle  227 . The plurality of nozzles  227  are directly exposed on the surface of the inkjet chip  21  and disposed in the required arrangement, as shown in  FIG.  3 D . Therefore, the ink-supply channels  23  and the plurality of manifolds  24  are also fabricated by the semiconductor process at the same time. Each of the plurality of ink-supply channels  23  provides ink, and the ink-supply channel  23  is in communication with the plurality of manifolds  24 . Moreover, the plurality of manifolds  24  are in communication with each of the ink-supply chambers  226  of the ink-drop generators  22 . As shown in  FIG.  3 B , the resistance heating layer  222  is formed and exposed in the ink-supply chamber  226 . The heating resistor layer  222  has a rectangular area formed by a length HL and a width HW. 
     Please refer to  FIGS.  3 A and  3 C . The number of the at least one ink-supply channel  23  is one to six. As shown in  FIG.  3 A , the number of the at least one ink-supply channel  23  arranged on a single inkjet chip  21  is one, thereby providing monochrome ink. Preferably but not exclusively, the monochrome ink is one selected from the group consisting of cyan, magenta, yellow and black ink. As shown in  FIG.  3 C , the number of the at least one ink-supply channel  23  arranged on a single inkjet chip  21  is six, thereby providing six-color ink of black, cyan, magenta, yellow, light cyan and light magenta, respectively. Certainly, in other embodiments, the number of the at least one ink-supply channel  23  arranged on a single inkjet chip  21  is four, thereby providing four-color ink of cyan, magenta, yellow and black, respectively. The number of the ink-supply channels  23  is adjustable and designed according to the practical requirements. 
     Please refer to  FIG.  3 A ,  FIG.  3 C  and  FIG.  4   . In the embodiment, the conductive layer  223  is fabricated by implementing the semiconductor process on the wafer structure  2 . Preferably but not exclusively, the conductive layer  223  is connected to a conductor fabricated by the semiconductor process of less than 90 nanometers to form an inkjet control circuit. In that, more metal oxide semiconductor field-effect transistors (MOSFETs) are arranged in the inkjet control circuit zone  25  to control the resistance heating layer  222 . Thereby, a loop is formed on the resistance heating layer  222  to activate heating. Alternatively, the loop is not formed on the resistance heating layer  222 , and the resistance heating layer  222  is not activated for heating. That is, as shown in  FIG.  4   , when a voltage Vp is applied to the resistance heating layer  222 , the transistor switch Q controls the circuit state of the resistance heating layer  222  grounded. When one end of the resistance heating layer  222  is grounded, a loop is formed to activate heating. Alternatively, if the loop is not formed, the resistance heating layer  22  is not grounded and not activated for heating. Preferably but not exclusively, the transistor switch Q is a metal oxide semiconductor field effect transistor (MOSFET), and the conductor connected to the conductive layer  223  is a gate G of the metal oxide semiconductor field effect transistor (MOSFET). In an embodiment, the conductive layer  223  is connected to a conductor, and the conductor is a gate G of a complementary metal oxide semiconductor (CMOS). In another embodiment, the conductive layer  223  is connected to a conductor, and the conductor is a gate G of an N-type metal oxide semiconductor (NMOS). The conductor connected to the conductive layer  223  is adjustable and selected according to the practical requirements for the inkjet control circuit. Certainly, in an embodiment, the conductor connected to the conductive layer  223  is fabricated by the semiconductor process of 65 nanometers to 90 nanometers, to form the inkjet control circuit. In an embodiment, the conductor connected to the conductive layer  223  is fabricated by the semiconductor process of 45 nanometers to 65 nanometers, to form the inkjet control circuit. In an embodiment, the conductor connected to the conductive layer  223  is fabricated by the semiconductor process of 28 nanometers to 45 nanometers, to form the inkjet control circuit. In an embodiment, the conductor connected to the conductive layer  223  is fabricated by the semiconductor process of 20 nanometers to 28 nanometers, to form the inkjet control circuit. In an embodiment, the conductor connected to the conductive layer  223  is fabricated by the semiconductor process of 12 nanometers to 20 nanometers, to form the inkjet control circuit. In an embodiment, the conductor connected to the conductive layer  223  is fabricated by the semiconductor process of 7 nanometers to 12 nanometers, to form the inkjet control circuit. In an embodiment, the conductor connected to the conductive layer  223  is fabricated by the semiconductor process of 2 nanometers to 7 nanometers, to form the inkjet control circuit. It is understandable that the more sophisticated the semiconductor process technology, the more groups of inkjet control circuits can be fabricated with the same unit volume. 
     As described above, the present disclosure provides the wafer structure  2  including the chip substrate  20  and the plurality of inkjet chips  21 . The chip substrate  20  is fabricated by the semiconductor process on a wafer of at least 12 inches or more, so that a larger number of inkjet chips  21  required are arranged on the chip substrate  20 . The plurality of inkjet chips  21  include at least one first inkjet chip  21 A and at least one second inkjet chip  21 B directly formed on the chip substrate  20  by the semiconductor process. The chip substrate  20  is diced, and the at least one first inkjet chip  21 A and the at least one second inkjet chip  21 B are produced, to be implemented for inkjet printing. Thus, the first inkjet chip  21 A and the second inkjet chip  21 B having different sizes of printing swath are directly generated in the same inkjet chip semiconductor process, as shown in  FIG.  1   . When the wafer structure  2  is used to produce the chip substrate  20  by the semiconductor process on the wafer of at least 12 inches, after arranging the number of second inkjet chips  21 B required, the remaining blank area is used to arrange the first inkjet chip  21 A with a smaller size of printing swath. In that, the remaining blank area won&#39;t be wasted. Furthermore, the manufacturing cost of directly generating the first inkjet chip  21 A and the second inkjet chip  21 B having different sizes of printing swath on the same wafer structure  2  by the same inkjet chip semiconductor process is effectively reduced. In addition, the first inkjet chip  21 A and the second inkjet chip  21 B are used to arrange in a printing inkjet design for higher resolution and higher performance. 
     The resolution and the sizes of printing swath of the first inkjet chip  21 A and the second inkjet chip  21 B are described below. 
     As shown in  FIGS.  3 D and  5   , each of the first inkjet chip  21 A and the second inkjet chip  21 B of the inkjet chips  21  includes a rectangular area having a length L and a width W, and a printing swath Lp. In the embodiment, each of the first inkjet chip  21 A and the second inkjet chip  21 B of the inkjet chips  21  includes a plurality of ink-drop generators  22  produced by the semiconductor process and formed on the chip substrate  20 . In the first inkjet chip  21 A and the second inkjet chip  21 B of the inkjet chips  21 , the plurality of ink-drop generators  22  are arranged in the longitudinal direction to form a plurality of longitudinal axis array groups (Ar 1  . . . Arn) having a pitch M maintained between two adjacent ink-drop generators  22  in the longitudinal direction, and arranged in the horizontal direction to form a plurality of horizontal axis array groups (Ac 1  . . . Acn) having a central stepped pitch P maintained between two adjacent ink-drop generators  22  in the horizontal direction. That is, as shown in  FIG.  5   , the pitch M is maintained between the ink-drop generator  22  with the coordinate (Ar 1 , Ac 1 ) and the ink-drop generator  22  with the coordinate (Ar 1 , Ac 2 ). Moreover, the central stepped pitch P is maintained between the ink-drop generator  22  with the coordinate (Ar 1 , Ac 1 ) and the ink-drop generator  22  with the coordinate (Ar 2 , Ac 1 ). The resolution number of dots per inch (DPI) for the inkjet chip  21  is equal to 1/(the central stepped pitch P). Therefore, in order to achieve the higher resolution required, a layout design with a resolution of at least 600 DPI is utilized in the present disclosure. Namely, the central stepped pitch P is at least equal to 1/600 inches or less. Certainly, the resolution DPI of the inkjet chip  21  in the present disclosure can also be designed with at least 600 DPI to 1200 DPI. That is the central stepped pitch P is equal to at least 1/600 inches to 1/1200 inches. Preferably but not exclusively, the resolution DPI of the inkjet chip  21  is designed with 720 DPI, and the central stepped pitch P is at least equal to 1/720 inches or less. Preferably but not exclusively, the resolution DPI of the inkjet chip  21  in the present disclosure is designed with at least 1200 DPI to 2400 DPI. That is, the central stepped pitch P is equal to at least 1/1200 inches to 1/2400 inches. Preferably but not exclusively, the resolution DPI of the inkjet chip  21  in the present disclosure is designed with at least 2400 DPI to 24000 DPI. That is, the central stepped pitch P is equal to at least 1/2400 inches to 1/24000 inches. Preferably but not exclusively, the resolution DPI of the inkjet chip  21  in the present disclosure is designed with at least 24000 DPI to 48000 DPI. That is, the central stepped pitch P is equal to at least 1/24000 inches to 1/48000 inches. 
     In the embodiment, the first inkjet chip  21 A disposed on the wafer structure  2  has a printing swath Lp, which ranges from at least 0.25 inches to 1.5 inches. Preferably but not exclusively, the printing swath Lp of the first inkjet chip  21 A ranges from at least 0.25 inches to 0.5 inches. Preferably but not exclusively, the printing swath Lp of the first inkjet chip  21 A ranges from at least 0.5 inches to 0.75 inches. Preferably but not exclusively, the printing swath Lp of the first inkjet chip  21 A ranges from at least 0.75 inches to 1 inch. Preferably but not exclusively, the printing swath Lp of the first inkjet chip  21 A ranges from at least 1 inch to 1.25 inches. Preferably but not exclusively, the printing swath Lp of the first inkjet chip  21 A ranges from at least 1.25 inches to 1.5 inches. In the embodiment, the first inkjet chip  21 A disposed on the wafer structure  2  has a width W ranging from at least 0.5 mm to 10 mm. Preferably but not exclusively, the width W of the first inkjet chip  21 A ranges from at least 0.5 mm to 4 mm. Preferably but not exclusively, the width W of the first inkjet chip  21 A ranges from at least 4 mm to 10 mm. 
     In the embodiment, a length of the second inkjet chip  21 B disposed on the wafer structure  2  is equal to or greater than a width of a printing medium thereby constituting a page-width printing, and the second inkjet chip  21 B has a printing swath Lp greater than at least 1.5 inches. Preferably but not exclusively, the printing swath Lp of the second inkjet chip  21 B is 8.3 inches, and the extent of the page-width printing is 8.3 inches corresponding to the width of the printing medium (A4 size) when the second inkjet chip  21 B prints thereon. Preferably but not exclusively, the printing swath Lp of the second inkjet chip  21 B is 11.7 inches, and the extent of the page-width printing is 11.7 inches corresponding to the width of the printing medium (A3 size) when the second inkjet chip  21 B prints thereon. Preferably but not exclusively, the printing swath Lp of the second inkjet chip  21 B ranges from at least 1.5 inches to 2 inches, and the extent of the page-width printing ranges from at least 1.5 inches to 2 inches corresponding to the width of the printing medium when the second inkjet chip  21 B prints thereon. Preferably but not exclusively, the printing swath Lp of the second inkjet chip  21 B ranges from at least 2 inches to 4 inches, and the extent of the page-width printing ranges from at least 2 inches to 4 inches corresponding to the width of the printing medium when the second inkjet chip  21 B prints thereon. Preferably but not exclusively, the printing swath Lp of the second inkjet chip  21 B ranges from at least 4 inches to 6 inches, and the extent of the page-width printing ranges from at least 4 inches to 6 inches corresponding to the width of the printing medium when the second inkjet chip  21 B prints thereon. Preferably but not exclusively, the printing swath Lp of the second inkjet chip  21 B ranges from at least 6 inches to 8 inches, and the extent of the page-width printing ranges from at least 6 inches to 8 inches corresponding to the width of the printing medium when the second inkjet chip  21 B prints thereon. Preferably but not exclusively, the printing swath Lp of the second inkjet chip  21 B ranges from at least 8 inches to 12 inches, and the extent of the page-width printing ranges from at least 8 inches to 12 inches corresponding to the width of the printing medium when the second inkjet chip  21 B prints thereon. Preferably but not exclusively, the printing swath Lp of the second inkjet chip  21 B is greater than at least 12 inches, and the extent of the page-width printing is greater than at least 12 inches corresponding to the width of the printing medium when the second inkjet chip  21 B prints thereon. 
     In the embodiment, the second inkjet chip  21 B disposed on the wafer structure  2  has a width W, which ranges from at least 0.5 mm to 10 mm. Preferably but not exclusively, the width W of the second inkjet chip  21 B ranges from at least 0.5 mm to 4 mm. Preferably but not exclusively, the width W of the second inkjet chip  21 B ranges from at least 4 mm to 10 mm. 
     In the present disclosure, the wafer structure  2  is provided and includes the chip substrate  20  and the plurality of inkjet chips  21 . The chip substrate  20  is fabricated by the semiconductor process on a wafer of at least 12 inches or more, so that a larger number of inkjet chips  21  required are arranged on the chip substrate  20 . The plurality of inkjet chips  21  include at least one first inkjet chip  21 A and at least one second inkjet chip  21 B directly formed on the chip substrate  20  by the semiconductor process. The chip substrate  20  is diced, and the at least one first inkjet chip  21 A and the at least one second inkjet chip  21 B are produced, to be implemented for inkjet printing. Therefore, the plurality of inkjet chips  21  diced from the wafer structure  2  of the present disclosure, regardless of the first inkjet chip  21 A and the second inkjet chip  21 B of the inkjet chips  21 , can be implemented for inkjet printing of a printhead  111 . The following is an explanation. Please refer to  FIG.  6   . In the embodiment, the carrying system  1  is mainly used to support the structure of the printhead  111  in the present disclosure. The carrying system  1  includes a carrying frame  112 , a controller  113 , a first driving motor  116 , a position controller  117 , a second driving motor  119 , a paper feeding structure  120  and a power source  121 . The power source  121  provides electric energy for operation of the entire carrying system  1 . In the embodiment, carrying frame  112  is mainly used to accommodate the print head  111  and includes one end connected with the first driving motor  116 , so as to drive the printhead  111  to move along a linear track in the direction of a scanning axis  115 . Preferably but not exclusively, the printhead  111  is detachably or permanently installed on the carrying frame  112 . The controller  113  is connected to the carrying frame  112  to transmit a control signal to the printhead  111 . Preferably but not exclusively, in the embodiment, the first driving motor  116  is a stepping motor. The first driving motor  116  is configured to move the carrying frame  112  along the scanning axis  115  according to a control signal sent by the position controller  117 , and the position controller  117  determines the position of the carrying frame  112  on the scanning axis  115  through a storage device  118 . In addition, the position controller  117  is also configured to control the operation of the second driving motor  119  to drive the printing medium  122 , such as paper, and the paper feeding structure  120 . In that, the printing medium  122  is moved along the direction of a feeding axis  114 . After the printing medium  122  is positioned in the printing area (not shown), the first drive motor  116  is driven by the position controller  117  to move the carrying frame  112  and the printhead  111  along the scanning axis  115  for printing on the printing medium  122 . After one or more scanning is performed along the scanning axis  115 , the position controller  117  controls the second driving motor  119  to operate and drive the printing medium  122  and the paper feeding structure  120 . In that, the printing medium  122  is moved along the feeding axis  114  to place another area of the printing medium  122  into the printing area. Then, the first drive motor  116  drives the carrying frame  112  and the printhead  111  to move along the scanning axis  115  for performing another line of printing on the printing medium  112 . When all the printing data is printed on the printing medium  122 , the printing medium  122  is pushed out to an output tray (not shown) of the inkjet printer. Thus, the printing action is completed. 
     From the above descriptions, the present disclosure provides a wafer structure including a chip substrate and a plurality of inkjet chips. The chip substrate is fabricated by a semiconductor process on a wafer of at least 12 inches or more, so that more inkjet chips required are arranged on the chip substrate. Furthermore, a first inkjet chip and a second inkjet chip having different sizes of printing swath are directly generated in the same inkjet chip semiconductor process, and arranged in a printing inkjet design for higher resolution and higher performance. The wafer structure is diced into the first inkjet chip and the second inkjet chip used in inkjet printing to achieve the lower manufacturing cost of the inkjet chips and the printing quality pursuit of higher resolution and higher printing speed. The present disclosure includes the industrial applicability and the inventive steps. 
     While the invention has been described in terms of what is presently considered to be the most practical and preferred embodiments, it is to be understood that the invention needs not be limited to the disclosed embodiment. On the contrary, it is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims which are to be accorded with the broadest interpretation so as to encompass all such modifications and similar structures.