Patent Publication Number: US-2022216051-A1

Title: Semiconductor wafer, manufacturing method for semiconductor wafer, and manufacturing method for semiconductor device

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is a divisional of U.S. application Ser. No. 16/792,944, filed Feb. 18, 2020, the entire contents of which is incorporated herein by reference. U.S. application Ser. No. 16/792,944 is based upon and claims the benefit of priority from Japanese Patent Application No, 2019-161278, filed on Sep. 4, 2019; the entire contents of which are incorporated herein by reference. 
    
    
     FIELD 
     Embodiments of the present invention relate to a semiconductor wafer, a manufacturing method for a semiconductor wafer, and a manufacturing method for a semiconductor device. 
     BACKGROUND 
     Processes such as exposure, film formation, and etching are performed to a semiconductor wafer when a semiconductor device is manufactured. At this time, the semiconductor wafer is adsorbed in a state of being supported by a support member to keep a horizontal attitude. 
     When a semiconductor wafer is adsorbed in a state of being supported by a support member, an outside region of the semiconductor wafer positioned on an outer side of the support region bends in some cases. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a plan view of a semiconductor wafer according to a first embodiment; 
         FIG. 2  is a sectional view along a section line A-A illustrated in  FIG. 1 ; 
         FIG. 3  is a plan view illustrating a modification of a support member; 
         FIG. 4A  is an explanatory diagram of a manufacturing method for a semiconductor wafer; 
         FIG. 4B  is an explanatory diagram of the manufacturing method for a semiconductor wafer; 
         FIG. 5  is a schematic diagram of a substrate processing apparatus that exposes a semiconductor wafer to light; 
         FIG. 6  is a plan a view illustrating an exposure pattern region on the semiconductor wafer; 
         FIG. 7  is a sectional view of a semiconductor wafer according to a modification of the first embodiment; 
         FIG. 8  is a sectional view of a semiconductor wafer according to another modification of the first embodiment; 
         FIG. 9  is a schematic diagram of a substrate processing apparatus that performs film formation or etching of the semiconductor wafer; 
         FIG. 10  is a plan view of a semiconductor wafer according to a second embodiment; 
         FIG. 11  is a sectional view along a section line B-B illustrated in  FIG. 10 ; 
         FIG. 12  is a sectional view of a semiconductor wafer according to a modification of the second embodiment; and 
         FIG. 13  is a sectional view of a semiconductor wafer according to another modification of the second embodiment. 
     
    
    
     DETAILED DESCRIPTION 
     Embodiments will now be explained with reference to the accompanying drawings. The present invention is not limited to the embodiments. 
     A semiconductor wafer according to an embodiment includes a support region facing a support member, an outer circumferential region positioned on an outer side of the support region, and an inner circumferential region positioned on an inner side of the support region. The outer circumferential region has a convex portion with a thickness protruded upward with respect to the inner circumferential region or a concave portion with a thickness recessed downward with respect to the inner circumferential region. 
     First Embodiment 
       FIG. 1  is a plan view of a semiconductor wafer according to a first embodiment.  FIG. 2  is a sectional view along a section line A-A illustrated in  FIG. 1 .  FIG. 3  is a plan view illustrating a modification of a support member. 
     A semiconductor wafer  1  according to the present embodiment includes a first surface  10  and a second surface  20 . Processes such as exposure, film formation, and etching are performed to the first surface  10 , The second surface  20  is in contact with a support member  2  as illustrated in  FIG. 2 . The first surface  10  and the second surface  20  include a support region R 1 , an outer circumferential region R 2 , and an inner circumferential region R 3 . 
     The support member  2  has a shape of a ring continuously surrounding the inner circumferential region R 3  along the circumferential direction of the semiconductor wafer  1 . The support member  2  may have a shape of pins dotted to intermittently surround the inner circumferential region R 3  along the circumferential direction as illustrated in  FIG. 3 . 
     The support region R 1  is a region facing the support member  2  in the vertical direction. The outer circumferential region R 2  is a region positioned on the outer side of the support region R 1 . The inner circumferential region R 3  is a region positioned on the inner side of the support region R 1  and including a center C of the semiconductor wafer  1 . 
     In the present embodiment, the outer circumferential region R 2  of the semiconductor wafer  1  has a convex portion with a thickness protruded upward with respect to the inner circumferential region R 3  as illustrated in  FIG. 2 . The outer circumferential region R 2  is, for example, a region on an outer side than 0.9R where the radius of the semiconductor wafer  1  is R, in other words, a region where the distance from the outer circumferential end of the semiconductor wafer  1  is 0.1R. 
     A manufacturing method for the semiconductor wafer  1  described above is explained below with reference to  FIGS. 4A and 43 . 
     First, a semiconductor wafer  1   a  is formed as illustrated in  FIG. 4A . A thickness t 1  of the semiconductor wafer  1   a  is constant in the entire region. Next, a region corresponding to the support region R 1  and the inner circumferential region R 3  described above of the semiconductor wafer  1   a  is ground by, for example, chemical mechanical polishing (CMP) or etching until the region has a thickness t 2  (&lt;t 1 ) as illustrated in  FIG. 4B . As a result, the outer circumferential region R 2  becomes a convex portion with the thickness protruded upward with respect to the inner circumferential region R 3 , whereby the semiconductor wafer  1  according to the present embodiment is completed. A semiconductor device can be manufactured by performing exposure and film formation to this semiconductor wafer  1 . The semiconductor device includes, for example, a three-dimensional semiconductor memory where electrode layers (word lines) are stacked. 
     An exposure step for the semiconductor wafer  1  according to the present embodiment is explained below with reference to  FIG. 5 .  FIG. 5  is a schematic diagram of a substrate processing apparatus that exposes the semiconductor wafer  1  according to the present embodiment to light. 
     A substrate processing apparatus  100  illustrated in  FIG. 5  includes a substrate stage  101 , a projector  102 , a mask stage  103 , a light source  104 , and a controller  105 , The substrate processing apparatus  100  is, for example, a scanning exposure apparatus that performs projection exposure of a pattern drawn on a mask MK onto the semiconductor wafer  1  being an exposure target while synchronously moving the mask MK and the semiconductor wafer  1  with respect to each other in a scanning direction. 
     The substrate stage  101  holds the semiconductor wafer  1  via the support member  2 . A chuck part  111  is provided on the substrate stage  101 . The chuck part  111  causes the semiconductor wafer  1  to be adsorbed to the substrate stage  101  with, for example, static electricity or vacuum. The substrate stage  101  is capable of horizontally moving or rotationally moving on the basis of control of the controller  105 . 
     The projector  102  is provided above the substrate stage  101 . The mask stage  103  holding the mask MK is provided above the projector  102 . The light source  104  is provided above the mask stage  103 . 
     In the substrate processing apparatus  100 , exposure light emitted from the light source  104  is diffracted by the pattern drawn on the mask MK and enters the projector  102 . The projector  102  performs projection exposure of the first surface  10  of the semiconductor wafer  1  to the incident light. Accordingly, the pattern on the mask MK is transferred to the first surface  10 . 
       FIG. 6  is a plan a view illustrating an exposure pattern region on the semiconductor wafer. The substrate processing apparatus  100  performs the exposure processing with the semiconductor wafer  1  being divided into a plurality of exposure pattern regions. The exposure pattern regions of the substrate processing apparatus  100  include an exposure pattern region E 1  that entirely falls within the semiconductor wafer  1  while including an exposure pattern region E 2  that partially spreads out of the semiconductor wafer  1  as illustrated in  FIG. 6 . 
     A large part of the exposure pattern region E 2  is occupied by the outer circumferential region R 2  of the semiconductor wafer  1 . At the time of exposure processing, the semiconductor wafer  1  is adsorbed to the substrate stage  101  by the chuck part  111  in a state of being supported by the support member  2  as described above. At this time, if the thicknesses of the support region R 1 , the outer circumferential region R 2 , and the inner circumferential region R 3  are all equal, the outer circumferential region R 2  sometimes bends downward (hangs down) from a boundary portion with the support region R 1  to be a curved surface while the inner circumferential region R 3  is generally a flat surface. In this case, a desired focus accuracy is not obtained on the exposure pattern region E 2  and an exposure failure is likely to occur. 
     In the present embodiment, the outer circumferential region R 2  is processed into a convex portion with the thickness protruded upward with respect to the inner circumferential region R 3 . Accordingly, the outer circumferential region R 2  is thicker than the inner circumferential region R 3  and is therefore less likely to bend. The thickness t 1  of the convex portion is set based on a largest bending amount of the outer circumferential region R 2 , which is supposed in a case where the respective thicknesses of the regions are equal. For example, when a radius R of the semiconductor wafer  1  is 150 millimeters (the diameter is 300 millimeters), the largest bending amount is generally not smaller than 10 nm and not larger than 10 μm. In this case, to suppress bending of the outer circumferential region R 2 , the thickness t 1  of the convex portion is desirably larger than the thickness t 2  by a thickness not smaller than 10 nm and not larger than 10 μm. 
     Due to formation of the convex portion on the outer circumferential region R 2  as described above, the semiconductor wafer  1  has a generally horizontal attitude when adsorbed in the state of being supported by the support member  2 . Therefore, the focus accuracy of the exposure pattern region R 2  is ensured. Accordingly, an exposure failure in the outer circumferential region R 2  can be reduced, 
       FIG. 7  is a sectional view of a semiconductor wafer according to a modification of the first embodiment.  FIG. 8  is a sectional view of a semiconductor wafer according to another modification of the first embodiment. 
     In the embodiment described above, the first surface  10  of the outer circumferential region R 2  is protruded assuming a situation in which the outer circumferential region R 2  bends downward from the boundary portion with the support region R 1  at the time of adsorption of the semiconductor wafer  1 . However, a situation in which the outer circumferential region R 2  bends upward (warps upward) at the time of adsorption of the semiconductor wafer  1  is also supposed. In this case, when the second surface  20  of the outer circumferential region R 2  is protruded as illustrated in  FIG. 7 , deformation of the outer circumferential region R 2  is suppressed and an exposure failure can be consequently reduced. 
     A concave portion having a thickness recessed downward with respect to the inner circumferential region R 3  may be formed on the outer circumferential region R 2  as illustrated in  FIG. 8  in anticipation of deformation of the outer circumferential region R 2 , which is expected at the time of adsorption of the semiconductor wafer  1  in a case where the thicknesses of the respective regions are uniform. 
     A film formation step and an etching step for the semiconductor wafer  1  according to the present embodiment are explained next with reference to  FIG. 9 .  FIG. 9  is a schematic diagram of a substrate processing apparatus that performs film formation or etching of the semiconductor wafer  1  according to the present embodiment. 
     A substrate processing apparatus  200  illustrated in  FIG. 9  includes an electrostatic chuck part  201 , a focus ring  202 , a lower electrode  203 , and a head  204 . The substrate processing apparatus  200  is, for example, a plasma CVD (Chemical Vapor Deposition) apparatus that forms a film on the semiconductor wafer  1  by CVD in a state where plasma is generated, or an etching apparatus that etches a film formed on the semiconductor wafer  1  by dry etching using plasma. 
     The electrostatic chuck part  201  holds the semiconductor wafer  1  via the support member  2 . The focus ring  202  is placed on the top surface of the electrostatic chuck part  201 . The electrostatic chuck part  201  causes the semiconductor wafer  1  and the focus ring  202  to be adsorbed thereto with static electricity. 
     The focus ring  202  is formed in an annular shape surrounding the semiconductor wafer  1 . The focus ring  202  is placed to uniformly generate plasma between the center of the semiconductor wafer  1  and the outer circumference thereof. 
     The lower electrode  203  is provided on the bottom part of the electrostatic chuck part  201 . The head  204  is provided above the electrostatic chuck part  201 . Plasma is generated when a high-frequency electric field is generated between the lower electrode  203  and the head  204  by supply of power from a high-frequency power source (not illustrated). When plasma is generated, the head  204  ejects a film forming gas or an etching gas toward the first surface  10  of the semiconductor wafer  1 . 
     In the substrate processing apparatus  200 , plasma generation on the outer circumferential region R 2  of the semiconductor wafer  1  is particularly adjusted by installation of the focus ring  202 . However, if the outer circumferential region R 2  bends at the time of adsorption by the electrostatic chuck part  201 , the horizontal attitude cannot be maintained and thus the controllability of film formation or etching is degraded. As a result, a film formation failure or an etching failure is likely to occur. 
     However, in the semiconductor wafer  1  according to the present embodiment, the shape of the outer circumferential region R 2  is optimized to enable the outer circumferential region R 2  to keep the horizontal attitude at the time of adsorption by the electrostatic chuck part  201 . Accordingly, the controllability of film formation or etching is improved and a film formation failure or an etching failure can be reduced. 
     Second Embodiment 
       FIG. 10  is a plan view of a semiconductor wafer according to a second embodiment.  FIG. 11  is a sectional view along a section line B-B illustrated in  FIG. 10 . In  FIG. 10  and  FIG. 11 , constituent elements identical to those in the first embodiment described above are denoted by like reference signs, and detailed explanations thereof are omitted. 
     As illustrated in  FIGS. 10 and 11 , a semiconductor wafer  11  according to the present embodiment is supported by the support member  2  having a ring shape continuously doubly surrounding the inner circumferential region R 3  along the circumferential direction. In a case of this support mode, the semiconductor wafer  11  has an intermediate region R 4  sandwiched by the support region R 1  in addition to the support region R 1 , the outer circumferential region R 2 , and the inner circumferential region R 3 . The intermediate region R 4  has a possibility of bending downward when adsorbed by the substrate processing apparatus  100  and the substrate processing apparatus  200  explained in the first embodiment. In this case, process failures such as an exposure failure, a film formation failure, and an etching failure are likely to occur on the intermediate region R 4 . 
     In the present embodiment, in order to solve this problem, a portion of the intermediate region R 4  on the side of the first surface  10  is processed into a convex portion with the thickness protruded upward with respect to the outer circumferential region R 2  and the inner circumferential region R 3 . Accordingly, the intermediate region R 4  is thicker than the outer circumferential region R 2  and the inner circumferential region R 3  and is thus less likely to bend. As a result, the semiconductor wafer  11  has a generally horizontal attitude when adsorbed by the substrate processing apparatus  100  or the substrate processing apparatus  200  and process failures on the intermediate region R 4  can be reduced. 
       FIG. 12  is a sectional view of a semiconductor wafer according to a modification of the second embodiment.  FIG. 13  is a sectional view of a semiconductor wafer according to another modification of the second embodiment. 
     For example, in a case in which a situation where the outer circumferential region R 2  bends upward (warps upward) at the time of adsorption of the semiconductor wafer  11  is supposed, deformation of the intermediate region R 4  can be suppressed when a portion of the intermediate region R 4  on the side of the second surface  20  is protruded as illustrated in  FIG. 12 . Consequently, process failures can be reduced. Further, a concave portion recessed downward with respect to the outer circumferential region R 2  and the inner circumferential region R 3  may be formed by grinding the intermediate region R 4  as illustrated in  FIG. 13  in anticipation of deformation of the intermediate region R 4 , which is expected at the time of adsorption of the semiconductor wafer  1  in a case where the thicknesses of the respective regions are uniform. 
     While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions, Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.