Patent Publication Number: US-2021182051-A1

Title: Chip having memory

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This non-provisional application claims priority under 35 U.S.C. § 119(a) to Patent Application No. 201911269473.0 filed in China, P.R.C. on Dec. 11, 2019, the entire contents of which are hereby incorporated by reference. 
     BACKGROUND 
     Technical Field 
     The disclosure describes a chip, especially a chip having a memory. 
     Related Art 
     A chip is an integrated circuit that performs a specific or general function. The chip includes a control circuit and a memory. The memory is accessed during operations of the chip, and may further store firmware. The firmware is a software for driving the chip, and the chip performs functions according to the firmware. In addition, a device connected to the chip can recognize the type and the functions of the chip through communication with the firmware of the chip. 
     Depending on customization or different applications, the firmware of the chip needs to be updated. The firmware is updated through a communication interface of the chip. However, different chips have different communication interfaces, such as I 2 C, a system management bus (SMBus), a universal serial bus (USB), and a serial port. Therefore, for updating the firmware of the chip, in addition to being limited to the communication interface supported by the chip, the transmission speed during the update is also limited to the transmission speed supported by the communication interface. 
     SUMMARY 
     In view of the above, the disclosure provides a chip adapted to update firmware in the memory. 
     According to some embodiments, the chip includes a power pin, a ground pin, a plurality of input/output (I/O) pins, a readable/writable memory, a switching circuit, a control circuit, and a processing circuit. The I/O pins include a control pin. The readable/writable memory includes a plurality of ports. The control circuit selectively activates or does not activate the switching circuit according to the control pin. When the switching circuit is activated, the switching circuit electrically couples the ports to the mapping pins, respectively. 
     Therefore, according to some embodiments, when the switching circuit of the chip is activated, the clock port, the I/O ports, and the enable port of the ports of the readable/writable memory are electrically coupled to the mapping pins of the I/O pins. In this way, a programming device can directly control the readable/writable memory, and program a firmware in the readable/writable memory through the mapping pins. This programming operation is not limited to a communication interface of the chip, and a transmission speed of the programming is not limited to a transmission speed of the communication interface either. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  illustrates a schematic block diagram of a chip according to some embodiments; 
         FIG. 2  illustrates a schematic block diagram of a switching circuit according to some embodiments; 
         FIG. 3  illustrates a schematic block diagram of a chip according to some embodiments; 
         FIG. 4  illustrates a schematic block diagram of a control circuit according to some embodiments; and 
         FIG. 5  illustrates a schematic block diagram of a chip according to some embodiments. 
     
    
    
     DETAILED DESCRIPTION 
     Referring to  FIG. 1 ,  FIG. 1  illustrates a schematic block diagram of a chip  10  according to some embodiments. The chip  10  includes a power pin  12 , a ground pin  14 , a plurality of I/O pins  20 , a readable/writable memory  30 , a switching circuit  40 , and a control circuit  50 . The I/O pins  20  include a plurality of mapping pins  22 A to  22 D and a control pin  24 . The readable/writable memory  30  includes a plurality of ports. The plurality of ports include a clock port  32 , a plurality of I/O ports  34 A and  34 B, and an enable port  36 . The control circuit  50  selectively activates or does not activate the switching circuit  40  according to the control pin  24 . When the switching circuit  40  is activated, the switching circuit  40  electrically connects the clock port  32 , the I/O ports  34 A and  34 B, and the enable port  36  to the mapping pins  22 A to  22 D respectively. 
     Therefore, a programming device  80  causes the control circuit  50  to activate the switching circuit  40  through the control pin  24 . When the switching circuit  40  is activated, the clock port  32 , the I/O ports  34 A and  34 B, and the enable port  36  of the readable/writable memory  30  are electrically connected to the mapping pins  22 A to  22 D respectively. In this way, the programming device  80  can directly control the readable/writable memory  30  through the mapping pins  22 A to  22 D, and program firmware in the readable/writable memory  30 . This programming operation is not limited to a communication interface of the chip  10 , and a transmission speed of the programming is not limited to a transmission speed of the communication interface either. 
     The chip  10  is the chip  10  including the readable/writable memory  30  that can store the firmware. According to some embodiments, the chip  10  is a general-purpose integrated circuit or a functional integrated circuit. The chip  10  is, for example, but not limited to, a central processing unit (CPU), a microprocessor, an application-specific integrated circuit (ASIC), or a system on a chip (SOC). 
     The chip  10  has a plurality of pins for electrically connecting to and communicating with a peripheral device. The pins of the chip  10  include the power pin  12 , the ground pin  14 , and the I/O pins  20 . The power pin  12  is, for example, but not limited to, a pin for supplying power for operating of the chip  10 . The power of the power pin  12  may be from the programming device  80  or other external devices. According to some embodiments, the chip  10  includes a plurality of power pins  12 . 
     The ground pin  14  is, for example, but not limited to, a pin for grounding the chip  10  and the programming device  80 . In some embodiments, the ground of the programming device  80  is electrically connected to the ground pin  14 . According to some embodiments, the chip  10  includes a plurality of ground pins  14 . 
     The programming device  80  is configured to program the readable/writable memory  30  of the chip  10  and update the data in the readable/writable memory  30 . The programming device  80  may be, for example, but not limited to, a universal programmer, a mass programmer, or a dedicated programmer. 
     The readable/writable memory  30  is, for example, but not limited to, an electrically-erasable programmable read-only memory (EEPROM), a flash memory, and other non-volatile memories (NVM). The clock port  32  of the readable/writable memory  30  is configured to receive a clock signal provided by the outside, and the readable/writable memory  30  operates according to the clock signal. The I/O ports  34 A and  34 B of the readable/writable memory  30  are configured to receive or send data of the readable/writable memory  30 . The enable port  36  of the readable/writable memory  30  is used by an external device to control the readable/writable memory  30 . Specifically, the external device is, for example, but not limited to, a microprocessor. The microprocessor generates an enable signal to enable the readable/writable memory  30 . In some embodiments, the enable signal is a level signal. For example, when the level signal is at a high level, it indicates that the readable/writable memory  30  is enabled. When the level signal is at a low level, it indicates that the readable/writable memory  30  is not enabled. However, this is not limited thereto. When the level signal is at a low level, it indicates that the readable/writable memory  30  is enabled. When the level signal is at a high level, it indicates that the readable/writable memory  30  is not enabled. In some embodiments, the enable signal is a sequence signal. For example, when the microprocessor sends a sequence signal to the enable port  36 , the readable/writable memory  30  is enabled when the content of the sequence signal conforms to an enable sequence; otherwise, the readable/writable memory  30  is not enabled. 
     In some embodiments, the chip  10  includes a processing circuit  60 . The processing circuit  60  is configured to access the data of the readable/writable memory  30  and perform the function of the chip  10 . In addition, the processing circuit  60  is configured to access data of the I/O pins  20  as well (for example, the processing circuit  60  access data of the mapping pins  22 A to  22 D). According to some embodiments, the chip  10  has two modes: a programming mode and a normal mode. When the switching circuit  40  is not activated by the control circuit  50 , that is, the chip  10  is in the normal mode, the mapping pins  22 A to  22 D, the clock port  32 , the I/O ports  34 A and  34 B, and the enable port  36  are electrically connected to the processing circuit  60  through the switching circuit  40 , and the chip  10  performs the existing function. 
     In some embodiments, the processing circuit (the processing circuit  60 A) includes a master controller  62  (as shown in  FIG. 3 ). The master controller  62  is configured to access the data of the readable/writable memory  30 . When the switching circuit  40  is not activated by the control circuit  50 , that is, the chip  10  is in the normal mode, the clock port  32 , the I/O ports  34 A and  34 B, and the enable port  36  are electrically connected to the master controller  62  through the switching circuit  40 . Therefore, the master controller  62  can access and control the readable/writable memory  30 . In addition, the mapping pins  22 A to  22 D are electrically coupled to another circuit of the processing circuit  60 A (for example, another circuit that does not include the master controller  62  in processing circuit  60 A) when the switching circuit is not activated. 
     Referring to  FIG. 2 ,  FIG. 2  illustrates a schematic block diagram of a switching circuit  40  according to some embodiments. The switching circuit  40  of the chip  10  includes a plurality of switches  42 A to  42 H. The switches  42 E to  42 H respectively correspond to the clock port  32 , the I/O ports  34 A and  34 B, and the enable port  36  of the readable/writable memory  30 , and the switches  42 A to  42 D respectively correspond to the mapping pins  22 A to  22 D of the chip  10 . When the switching circuit  40  of the chip  10  is not activated, the mapping pins  22 A to  22 D are electrically connected to the processing circuit  60  through the switches  42 A to  42 D, and the clock port  32 , the I/O ports  34 A and  34 B, and the enable port  36  are electrically connected to the processing circuit  60  through the switches  42 E to  42 H. Therefore, the processing circuit  60  can perform the function of the chip  10 . When the switching circuit  40  of the chip  10  is activated, the clock port  32 , the I/O ports  34 A and  34 B, and the enable port  36  of the readable/writable memory  30  are electrically connected to the mapping pins  22 A to  22 D respectively. Taking the switch  42 A and the switch  42 E as an example, the switch  42 A corresponds to a contact  61 A of the processing circuit and the mapping pin  22 D, and the switch  42 E corresponds to the enable port  36  and a contact  61 E of the processing circuit. The switch  42 A corresponds to the switch  42 E. When the switch  42 A and the switch  42 E are not activated, the switch  42 A electrically connects the mapping pin  22 D to the contact  61 A, and the switch  42 E electrically connects the enable port  36  to the contact  61 E. When the switch  42 A and the switch  42 E are activated, the switch  42 A electrically connects the mapping pin  22 D to the enable port  36  through switching. 
     Referring to  FIG. 1 . The control circuit  50  selectively activates or does not activate the switching circuit  40  according to the control pin  24 . In some embodiments, the control pin  24  receives a level signal or a sequence signal, and the control circuit  50  selectively activates or does not activate the switching circuit  40  according to the signal received by the control pin  24 . For example, when the level signal is at a high level, it indicates that the switching circuit  40  is enabled. When the level signal is at a low level, it indicates that the switching circuit  40  is not enabled. However, this is not limited thereto. When the level signal is at a low level, it indicates that the switching circuit  40  is enabled. When the level signal is at a high level, it indicates that the switching circuit  40  is not enabled. For example, when the microprocessor sends a sequence signal to the control pin  24 , the control circuit  50  activates the switching circuit  40  when the content of the sequence signal conforms to an activating sequence; otherwise, the switching circuit  40  is not activated. In some embodiments, the control circuit  50  includes a master controller. The master controller is electrically connected to the control pin  24  and receives a level signal or a digital sequence provided by the outside. 
     Referring to  FIG. 3 ,  FIG. 3  illustrates a schematic block diagram of a chip  10  according to some embodiments. In some embodiments, the control circuit (the control circuit  50 A) is a logic circuit. The I/O pins  20  include a plurality of control pins  24 A to  24 C. When a combination of the control pins  24 A to  24 C is a preset value, the logic circuit activates the switching circuit  40  to make the chip  10  enter the programming mode. According to some embodiments, the logic circuit has one or more input terminals that can be electrically connected to the control pins  24 A to  24 C respectively and output at least one logic result. The logic circuit may be, but is not limited to, a logic gate, or a combination of a plurality of logic gates. The logic gate is, for example, but not limited to, an inverter, an AND gate, an OR gate, an exclusive OR gate, a buffer gate, or other logic gates. The preset value may be a combination of logic 0 and logic 1. 
     Referring to  FIG. 4 ,  FIG. 4  illustrates a schematic block diagram of a control circuit  50 B according to some embodiments. In some embodiments, the control circuit (the control circuit  50 B) includes a driving circuit  52  and a communication circuit  54 . The communication circuit  54  is electrically connected to the control pin  24  and actives the driving circuit  52  according to a signal received by the control pin  24 . When the driving circuit  52  is activated, the switching circuit  40  is activated, so that the chip  10  enters the programming mode. According to some embodiments, the communication circuit  54  may be, for example, but not limited to, an RS232 communication interface. According to some embodiments, the driving circuit  52  may be, for example, but not limited to, a circuit for amplifying a control signal. 
     Referring to  FIG. 5 ,  FIG. 5  illustrates a schematic block diagram of a chip  10  according to some embodiments. In some embodiments, the control (the control circuit  50 C) is a master controller. The master controller activates the switching circuit  40  according to the signal received by the control pin  24 , that is, the chips 10  enters the programming mode, and the master controller electrically connects the clock port  32 , the I/O ports  34 A and  34 B, and the enable port  36  to the mapping pins  22 A to  22 D. In this embodiment, the control circuit  50 C (the master controller) and the programming device  80  may receive and send signals through, but not limited to, I 2 C, RS232, USB, SMBus, and other types of protocols. When the switching circuit  40  is not activated as the chip  10  is in the normal mode, the clock port  32 , the I/O ports  34 A and  34 B, and the enable port  36  are electrically connected to the master controller respectively. Therefore, the master controller can access and control the readable/writable memory  30 . Taking a contact  61 E″ of the control circuit  50 C (the master controller) as an example, in the normal mode, the enable port  36  is electrically connected to the contact  61 E″ of the control circuit  50 C (the master controller) through the switch  42 E of the switching circuit  40  (as shown in  FIG. 2 ). According to some embodiments, the chip  10  further includes a processing circuit  60 B, wherein the processing circuit  60 B is another circuit that does not include the master controller in processing circuit  60 A of  FIG. 3 . According to some embodiments, when the switching circuit  40  is not activated, that is, the chip  10  is in the normal mode, the mapping pins  22 A to  22 D are electrically connected to the processing circuit  60 B through the switching circuit  40 . Therefore, the processing circuit  60  can perform the original functions of the chip  10 . Taking a contact  61 A″ of the processing circuit  60 B as an example, in the normal mode, the mapping pin  22 D is electrically connected to the contact  61 A″ of the processing circuit  60 B through the switch  42 A of the switching circuit  40  (as shown in  FIG. 2 ). 
     In view of the above, according to some embodiments, when the switching circuit  40  of the chip  10  is activated, the clock port  32 , the I/O ports  34 A and  34 B, and the enable port  36  of the ports of the readable/writable memory  30  are electrically coupled to the mapping pins to the mapping pins  22 A to  22 D of the I/O pins respectively. In this way, the programming device  80  can directly control the readable/writable memory  30  through the mapping pins  22 A to  22 D, and program the firmware in the readable/writable memory  30 . This programming operation is not limited to a communication interface of the chip, and a transmission speed of the programming is not limited to a transmission speed of the communication interface either.