Patent Publication Number: US-4097807-A

Title: Automatic equalizing method and system

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a transversal-type equalizing apparatus and method for use in a suppressed carrier data transmission system, and more specifically to apparatus and method that automatically compensates for phase pertubations in the reinserted carrier signal at the receiving terminal of such system as well as for variations in phase and amplitude of the received signal due to the transmission channel. 
     2. Description of the Prior Art 
     The demands for data transmission have greatly increased in recent years, resulting in development of techniques for transmission of high-rate pulse-type data signals over bandlimited transmission channels such as telephone lines and the like. Additionally, demands are also placed on greater accuracies in detection of such data signals at the receiving terminal. 
     Two significant factors influencing the capability of a data communication system to correctly receive the transmitted signals are: (1) the noise characteristics of the transmission channel, and (2) the intersymbol interference caused by the time dispersion in the channel. For low-noise environments, as typified by telephone channels, the most important consideration is minimization of the latter factor. 
     For a given telephone channel, the transfer function of the channel is characterized by its attenuation and delay as a function of frequency. The envelope delay, defined as the derivative of the phase characteristic, represents the relative time of arrival of the various frequency components of the input signal; thus, a sequence of pulses, or symbols, in passing through the channel are distorted and overlap in time between successive symbols. This distortion is referred to above as intersymbol interference. 
     While the above-mentioned channel characteristics may be relatively constant for a specific telephone line, in switched telephone networks a channel is generally chosen at random for a given transmission; therefore a wide variation of channel characteristics may be expected with respect to a given receiving terminal. To solve this problem, it is well-known to provide at the receiving terminal an automatic equalizer having the capability to compensate for the expected range of attenuation and phase variations of the incoming channels, thus minimizing intersymbol interference in the received data. 
     The most effective prior art equalizer is the transversal filter wherein a delay line tapped at intervals equal to the symbol period has each tap connected through a variable gain element to a summing bus. The gain elements are automatically controlled by means of an error signal to introduce echoes of the signal of such amplitudes as to compensate for the overall channel delay characteristics. 
     The requirements for higher data rates have led to development of multi-level modulation methods (e.g., multiphase and quadrature amplitude modulation methods) to increase the data rate in a given channel bandwidth. As is well known, it is common to translate the baseband data signal to a higher carrier frequency, and to frequency multiplex a number of such frequency-translated signals over a single wide-band channel. Generally, the carrier frequency is suppressed and only the upper and lower sidebands are transmitted, this method being known as double sideband, suppressed carrier (DSBSC) transmission. Therefore, the pilot signal is not required. This makes unnecessary the use of complicated carrier regeneration circuit which inevitably was required for regenerating the pilot signal. Moreover, since there is no need to allocate within the bandwidth available for transmission the pilot signal adjacent to the data signal, a comparatively simplified filter circuit can be used. This is a large merit of such a transmission system. 
     At the receiving terminal, however, it is necessary to regenerate the carrier frequency and to insert the carrier at the correct phase in order to demodulate the data signal and thereby recover the baseband signal. The requirement for locally generating the carrier for demodulating the DSBSC signal gives rise to an additional source of signal distortion. Unavoidable variations in generation of the carrier may result in frequency offset and phase jitter. Prior art automatic equalizers of the transversal type have attempted to solve this second distortion problem by two basic compensating, or correcting, techniques. The first is to use a local carrier generator or of fixed frequency, and to rely on the normal automatic adjustment of tap gains of the equalizer to correct for carrier frequency deviation and phase jitter. The second is to use a voltage controlled local carrier-generating oscillator and to control same as a function of the error signal of the automatic equilizer. 
     Such compensating methods have the disadvantage that high channel equalizing accuracy requires a relatively large number of delay line taps, and the response time of the filter increases with the number of taps; yet, the response time must be short if the system is to be able to follow the rapid carrier phase jitter. Therefore, a satisfactory compromise between equalizing accuracy and phase jitter compensation is difficult or not possible -- i.e., increasing equalizer accuracy increases jitter, and decreasing jitter results in decreased accuracy. 
     SUMMARY OF THE INVENTION 
     The present invention overcomes the disadvantages of the prior art by providing means, used in combination with an automatic equalizer, for automatically compensating for variations in phase of the locally-generated carrier in a DSBSC data transmission receiving terminal without affecting the equalizing accuracy of the automatic equalizer with respect to the data channel amplitude and phase characteristics. Hence, the present invention provides an automatic equalizing method and system which can effectively compensate, or correct the phase of the carrier without deterioration of the equalizing accuracy of the automatic equalizing circuit. 
     One embodiment of the invention involves modifying the signal appearing on the transversal filter summing bus in accordance with a characterization of the error signal caused only by the carrier phase pertubations. The modified sum signal is then applied to the decision circuitry and a composite error signal derived conventionally. The composite error signal is next processed to remove the carrier phase pertubation error signal and thus to provide a gain control signal that is relatively free from the effects of the phase variations. The resultant gain control signal is used to control the tap gain circuits of the transversal filter. 
     It is therefore a primary object of the present invention to provide apparatus and method for automatically compensating for distortion in received data symbols caused by phase pertubations in the re-inserted carrier of a DSBSC data transmisison receiving terminal. 
     It is a further object of the present invention to provide apparatus for and a method of compensating for carrier phase pertubations without affecting the accuracy of the automatic compensation for variations in the data transmission channel amplitude and phase characteristics. 
     It is another object of the present invention to provide an automatic equalizing apparatus and method that will closely track phase variations of the locally generated carrier signal. 
     It is yet another object of the present invention to provide an automatic equalizing apparatus in which variations in phase of the locally-generated carrier signal are compensated through the use of digital circuitry. 
     These and other objects and advantages of the present invention will become apparent to one skilled in the art to which the invention pertains from a perusal of the appended claims and the detailed description when read in conjunction with the attached drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram of a conventional prior art automatic equalizing circuit of the transversal-filter type presented to delineate the operating principles thereof; 
     FIG. 2 is a block diagram of one embodiment of an automatic equalizing circuit in accordance with the present invention; 
     FIG. 3 is a block diagram of another embodiment of the present invention, showing an automatic equalizing circuit realized with digital circuit elements; 
     FIG. 4 is a diagram of the coding technique used for transmission of information in a quadrature amplitude modulation (QAM) system that may utilize the present invention; and 
     FIG. 5 is a detailed block diagram of the decision circuit shown in FIG. 3 suitable for use in the QAM system referred to by FIG. 4. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Before describing embodiments of the present invention, it is helpful to analyze the prior art automatic equalizer of the transversal-filter type as applied to a DSBSC data communication system. Accordingly, in FIG. 1, a typical prior art automatic equalizer is shown. Input terminal 1 of demodulation circuit 2 receives the DSBSC signal. Demodulator 2 includes a local oscillator 2a which generates the demodulation signal θc of the required carrier frequency, applied to multiplier 2b.  The DSBSC signal is then multiplied by multiplier 2b with signal θc producing a baseband signal at the output of the demodulator 2. A low-pass filter, although not shown, is assumed to be (and typically is) included in demodulator 2 to pass only the fundamental baseband frequencies to the output. 
     As will be recognized, the baseband signal can include distortion from the following sources: 
     1. the amplitude vs. frequency characteristic of the transmission channel is not a constant; 
     2. the phase vs. frequency characteristic of the transmission channel is not linear with frequency; 
     3. pertubations in the phase of carrier θc. 
     The baseband signal is passed through a series of delay circuits 3 in the delay interval of each of which is selected to be equal to the data symbol duration. A tap at each delay circuit 3 supplies the signal from each delay 3 through a corresponding variable tap gain circuit 4, the outputs of all circuits 4 being supplied to summing circuit 5. The summed signal at the output of summer 5 is thus the baseband signal modified by weighted and delayed versions, or sample portions of the signal. By properly adjusting each tap gain circuit 4, the distortions of the baseband signal can be minimized, within the inherent capabilities of the equalizer. 
     The summed signal is accordingly analyzed by decision circuit 6 which judges and regenerates the data signal, based on a prior knowledge of the total ensemble of possible signals, as to the correct signal (typically by a thresholding operation) which then appears as the digital output at output terminal 10. Difference circuit 7 substracts the output signal of summer 5 from the digital output signal of the decision circuit 6, with the difference thus representing the residual distortion, or error, signal. The error signal is utilized in a negative feedback fashion to modify the transfer characteristics of the transversal filter to cause the summed signal from summer 5 to more nearly approximate the digital output signal of decision circuit 6, thereby reducing the error signal. Accordingly, the error signal is multiplied by multipliers 8 respectively associated with the taps, the products therefrom being smoothed or averaged by associated integrators 9, and the outputs of the latter then are utilized as gain control signals for the corresponding tap gain circuits 4. It is to be noted that the signals present at each multiplication and summing point are considered to be complex, varying in both amplitude and phase. 
     Having briefly summarized the operation of the prior art circuit of FIG. 1, an analysis will be described to illustrate the operation of the circuit and the problems of such a circuit to which the present invention is directed. 
     Case (1) Static channel characteristics: 
     The baseband input signal to the delay circuit is expressed as x(t) and is assumed to have the form ##EQU1## where: a(K) is the code transmitted over the channel; 
     h 1  (t) is the impulse response of the equalizer input; and 
     T is the symbol or pulse duration of the code. 
     The automatic equalizer output, y(t), can be expressed as: ##EQU2## where: h 2  (t) is the impulse response of the equalizer, and is given by: ##EQU3## where: M is the number of taps before the center tap, 
     N is the number of taps after the center tap, and 
     C n  is the tap gain coefficient. 
     The relation between x(t) and y(t) can be expressed as: ##EQU4## and the equalizing output after sampling becomes: ##EQU5## 
     Referring to the output of the decision circuit 6 as a(τ), the error ε(τ), comprising the difference between the equalizer output and the decision circuit output and hereinafter referred to as the &#34;equalizing error,&#34; is seen to be 
     
         ε(τ) = y(τ,T) - a(τ).                  (6) 
    
     The automatic equalizing circuit is adjusted by an algorithm that determines the correlation of the input signal x(t) and the equalizing error ε(τ) to compensate the tap coefficient C K , as expressed by the following equation: 
     
         C.sub.K.sup.(n+1) = C.sub.K.sup.(n) - α.sub.c ·ε(τ)·x {(τ-K)T}        (7) 
    
     where α c  is the control coefficient, and C K .sup.(n) is the gain value of the Kth tap adjusted by n times. 
     Assume that the optimum C K  has been obtained by minimization of the mean-square (MS) distortion and is C OK  ; then, the root mean-square error defined by the following equation becomes a minimum when C K  = C OK  : ##EQU6## 
     Case (2) Dynamic channel characteristics: 
     The general case for which the channel amplitude and phase characteristics vary with time, as will occur due to jitter in the locally-generated carrier, will be considered with the input signal to the automatic equalizer being designated as x&#39;(t). x&#39;(t) may be expressed as: 
     
         x&#39;(t) = x(t)e.sup.γ(t)                               (9) 
    
     where: 
     γ(t) = α(t)+i β(t) and 
     α(t) = time variation of amplitude and 
     β(t) = time variation of phase (including phase jitter and any frequency offset). 
     The output y&#39;(t) of the transversal filter may be expressed as ##EQU7## 
     If the total delay time, (M+N)T, through the automatic equalizing circuit is much smaller than the dynamic channel variation rate, the value of e.sup.(t-nT) will appear to be a constant for n = -M through N, which may be expressed as e.sup.γ(t). 
     In this case, the expression for channel variation reduces to ##EQU8## 
     The sampled equalizing error ε&#39;(τ) now may be expressed as: 
     
         ε&#39;(τ) = y&#39;(τ,T) - a(τ) 
    
     
         = y (τ,T)e.sup.γ(τ,T) -a(τ).             (12) 
    
     In order to minimize the inter symbol interference, the following expression must be optimized: ##EQU9## 
     For this expression to become a minimum in accordance with equation (8), the following relation must obtain: 
     
         C.sub.n &#39; = C.sub.on ·e.sup.-γ(t)           (14) 
    
     In other words, C n  &#39; must follow or track the channel fluctuation e - γ(t). 
     Thus, the fundamental problem in the prior art transversal-filter type automatic equalizer can be now seen. Increasing the speed of response of the filter by reducing the number of delay line taps to allow C n  &#39; to track the channel fluctuation e - γ(t) results in decreased accuracy of equalization of the static channel characteristics; and in general, the equalizer cannot be optimized for both types of compensation. Furthermore, when the carrier includes a frequency offset, e - γ(t) exhibits a linear increase of phase, and prior art circuits do not have sufficient control to track such error. 
     Turning now to FIG. 2, the block diagram of a preferred embodiment of the present invention is shown. Elements in FIG. 2 that correspond to the identical elements in FIG. 1 are identified by the same numbers. As may be noted, the identical prior art transversal-filter type automatic equalizer section of FIG. 1 is included in the instant invention in combination with a phase compensating network 11 and an equalizing error compensation multiplier 12. 
     Compensating network 11 is connected at the output of the transversal-filter and serves to compensate for phase jitter of the channel characteristic independently of the static characteristic as will be explained in detail hereinbelow. The equalizing error compensation multiplier 12 is connected in the tap-gain control feedback line and is utilized to prevent the phase jitter error component in the equalizing error signal from affecting the static compensation of the equalizer. 
     The Signal y&#34;(t) at the output of summer 5 may be conveniently expressed in terms of the sampled output of decision circuit 6 and the equalizing error signal as follows: 
     
         y&#34;(t) = {a(τ,T) + ε(τ)} e.sup.γ(t)   (15) 
    
     ε(t) as defined in equation (6) represents the equalizing error for the static channel characteristics and will hereinafter be referred to as the steady state error. 
     At point C in network 11, signal C APC  appears as will be shown hereinbelow and approaches e - γ(t) with an error of Δ(t). This residual error, Δ(t) will hereinafter be referred to as the dynamic error. With this notation, the value of C APC  may be expressed as 
     
         C.sub.APC = e.sup.-γ(t) + Δ(t)                 (16) 
    
     The value C APC  is applied to multiplication circuit 13 with the product of y&#34;(t) and C APC  designated as z(t), which has the form 
     
         z(t) = y&#34;(t)·C.sub.APC 
    
     
         = {a(τ,T) + ε(τ)} e.sup.Δ(t) 
    
     
         ≈ a(τ,T) + ε(τ) + a(τ,T)Δ(t) + ε(-τ)Δ(t).                              (17) 
    
     As may now be seen from equation (17), z(t) is the decision circuit output term a(τ,T) plus a residual error involving the steady state error ε(t) and the dynamic error Δ(t) and represents the input to decision circuit 6. As is well known, a digital decision circuit generates a discrete output for all input levels lying within a set of limits, effectively determining within which set of limits the analog signal lies. Therefore, the residual error of Equation (17) need be only sufficiently small so that the vector y&#34;(t) lies within the limits which define its correct digital value. Since Δ(t), the dynamic error, can be made to approach zero as shown hereinbelow, the circuit can thus be compensated for the source of this error. 
     The manner in which the instant invention extracts or compensates for the dynamic channel variations at the output of summer 5 will now be explained. Assuming that the sampled output of decision circuit 6 is a(τ,T), the overall equalized error signal E(t) at the output of difference circuit 7 may be expressed as follows: 
     
         E(t) = z(t) - a(τ,T) 
    
     
         = ε(τ) + a(τ,T)Δ(t) + ε(τ)Δ(t) 
    
     
         ≈ ε(t) + a(τ,T)Δ(t), where ε(t)&lt;&lt;1. (18) 
    
     Multiplication circuit 18 receives the output a(τ,T) from decision circuit 6 and the output E(t) of difference circuit 7, with the output at point G then expressed as 
     
         Ea(t) = E(t)a*(τ,T) 
    
     
         = ε(t)a* (τ,T) +  a(τ,T)!.sup.2 Δ(t) (19) 
    
     where a*(τ,T) is the complex conjugate of a(τ,T). 
     The first term in equation (19) corresponds to the steady state error, and the second term corresponds to the dynamic error. Thus, the first term will become zero when averaged, leaving only a contribution from the second term. E a  (t) is integrated by integrator 17 and added in summer 16 with the output of integrator 17 to produce the sum, E b  (t): 
     
         E.sub.b (t) = a E.sub.y (t) + b∫E.sub.a (t) dt        (20) 
    
     where a and b are coefficients determined by the parameters of circuits 17 and 16. 
     Next, E b  (t) is multiplied in multiplier 15 by the signal at point C, namely, C APC , with the product representing an input to integrator 14. Thus, the output of integrator 14 is signal C APC  as a function of time and may be expressed as 
     
         C.sub.APC (t) = ∫C.sub.APC E.sub.b (t) dt.            (21) 
    
     Assume the period between times t 1  and t 2  is short, with the value of C APC  (t) during this interval expressed as C&#39; APC , wherein ##EQU10## 
     As expressed in equation (16) above, C APC  is e - γ(t) + Δt, and the following relation can be obtained: ##EQU11## 
     Assuming that in the short period t 1  through t 2 , Δ(t)&lt;&lt;1 and the variation of -γ(t) is small, C&#39; APC  then becomes ##EQU12## Thus, at t 2  the value of C APC  (t) becomes ##EQU13## and compensation for the error (t 1 ) can be provided by selecting the proper value for the signal expressed by the term ##EQU14## In other words, the signal at point G in network 11, E a  (t) is operated on by the second order averaging circuit formed by integrators 14 and 17, with the characteristics of such circuit expressed in operational form by a Laplace conversion as ##EQU15## Thus, when E a  (t) is averaged as mentioned above with reference to equation (19), the first term in E a  (t), which is steady state error as shown in Equation (19) becomes zero, leaving E a  (t) equivalent to Δ(t), thereby effectively adjusting Δ(t) which then approaches zero. 
     It now remains to be shown that the compensation of the steady state error remains effective independently of the dynamic compensation in accordance with the present invention. As may be noted, the steady state compensation is controlled by the output signal of multiplier 12, considered to be H(t), which is, of course, the product of E(t) and C APC . Considering γ(t) and C APC  as complex members, H(t) can be expressed as 
     
         H(t) = E(t)·C.sub.APC (t) 
    
     
         = ε(t) + a(τ,T)Δ(t)!e.sup.γ(t) - Δ(t) 
    
     
         =ε(t)·e.sup.γ(t) +a(τ,T)·Δ(t)e.sup.γ(t) -Δ(t)·ε(t)-a(τ,T)·Δ.sup.2 (t) 
    
     
         =ε(t)·e.sup.γ(t) +a(τ,T)·Δ(t)·e.sup.γ(t) (26) 
    
     Signal H(t) represents the residual equalized error signal, made input to multipliers 8. Assuming that I K  (t) is the output of the Kth multiplier, this term can be expressed as 
     
         I.sub.K (t) = H(t)·X*{(τ-K)T} 
    
     
         = h(t)·X*}(τ-K)T}e.sup.-γ(t) 
    
     
         = ε(t)·X*{(τ-K)T}+a(τ,T)·Δt.multidot.X*{(τ-K)T}                                            (27) 
    
     averaging I K  (t) by an integrator 9, the required compensation of C K  can be determined: 
     
         C.sub.K.sup.(n+1) =C.sub.K.sup.(n) -α.sub.1  ε(τ)·X*{(τ-K)T}+a(τ,T)Δ(t)·X* {(τ-K)T}!                                             (28) 
    
     comparing equation (28) for the tap gain coefficient in accordance with the present invention, with equation (7) for the prior art automatic equalizer shows that the first term in the brackets  ! of equation (28) is the same as that of equation (7). 
     Therefore, assuming proper adjustment of C APC  the second term becomes very small, and C K  is optimized with respect to the steady state error. 
     Accordingly, it is demonstrated that the automatic equalizer implementation of the present invention compensates for the steady state characteristics of the channel in the presence of phase jitter with essentially no effect from such jitter. 
     The features and advantages of the present invention can be summarized as follows: 
     1. There is no necessity for the tap gain coefficient C K  to follow the dynamic channel variations as in prior art equalizers. As indicated by equation (15) the dynamic channel variations e.sup.γ(t) may be superimposed on the transversal filter output. Since it is only necessary for C K  to track such dynamic variations, it is sufficient for the transversal filter to compensate only for the steady state distortion, and the accuracy of the equalizer can be maintained or raised without regard to maintaining high response speed for adjustment of C K . 
     2. Optimum adjustment of C K  can be made with respect to static channel characteristics without being essentially affected by the dynamic characteristics e.sup.γ(t) as shown by equation (28) for C K , since e.sup.γ(t) does not appear therein. A small term involving the residual dynamic error does appear but its effect is negligible when C APC  is properly adjusted. 
     3. Adjustment of C APC  can be accomplished essentially independently of the adjustment of C K . Therefore, the speed of response of the phase correction network 11 can be made as high as necessary to track the dynamic variation of the channel characteristics without affecting the static compensation as is desired. 
     The embodiment of the present invention presented hereinabove has utilized an automatic equalizing circuit using the minimum mean square criteria in which the tap gain is controlled by the equalized residual signal and the tap output. However, the present invention can also be adapted to other types of automatic equalizing circuits. For example, it is applicable to the automatic equalizing circuit of the ZF (zero forcing) type in which tap gain is controlled by both the magnitude of the equalizing error signal and the polarity of the tap output. In this case, the equalizing error signal is quantized to a two-level signal with a positive or negative polarity. 
     The present invention as exemplified by FIG. 2 may be implemented with conventional analog-type circuit elements in accordance with the block diagram shown therein. Other implementations of the invention are also practical and may have certain advantages. In particular, the use of digital circuit elements with the various mathematical operations being performed by logic circuits is a useful and effective approach. Such an implementation lends itself to large-scale integration with resultant savings in cost, size, weight and power consumption. Accordingly, an alternative embodiment of the digital type will be described hereinbelow. The instant invention has been described as applied to a data communication system using DSBSC modulation. However, as will be evident to those skilled in the art, it is equally applicable to multi-level modulation methods having suppressed carriers. In particular, the digital circuit implementation to be described is directed to a system using quadrature amplitude modulation (QAM). 
     Before presenting this alternative embodiment of the instant invention, the QAM system will be briefly described with reference to FIG. 4. The diagram illustrates the identification of 8 data points with specific X,Y coordinates. Each of the 8 data points represents a 3-bit (000 to 111) code, and the points are arranged on the circumference of a circle of constant radius such that the projections of each point on the X and Y axes are integers of either &#34;1&#34; or &#34;2.&#34; For example, at the point A, the data point represents the code 000 and has a value of &#34;2&#34; on the X axis and a value of &#34;1&#34; on the Y axis. 
     For transmission of these codes, two independent DSBSC signals in quadrature are used. Each of the suppressed carriers is related to one of the axes. For example, the X axis can correspond to the cos ω c  t carrier, and the Y axis to the sin ω c  t carrier. To transmit point A, the cos ω c  t carrier is subjected to amplitude modulation with the value of &#34;2&#34; and the sin ω c  t carrier subjected to amplitude modulation with value &#34;1.&#34; The two signals are combined, the carriers suppressed and the composite signal transmitted. At the receiving terminal, the received composite signal is synchronously detected with locally-generated cos ω c  t and sin ω c  t carriers. Two baseband signals can thus be obtained and the amplitude of each determined to define point A and code 000. As may be understood, the value on the X axis may be considered as the real number, the value on the Y axis as the imaginary number, and the data point, a complex number. 
     Also shown in FIG. 4 are X&#39; and Y&#39; axes which can be obtained by rotation of the X and Y axes for 45° in the counterclockwise direction, as is useful for certain purposes described hereinafter. 
     FIG. 3 is the block diagram of the instant invention implemented through use of a digital operational processing circuit. The program for operation of the automatic equalizer is stored in the program memory 71 and is controlled by instruction counter 70. Basically, analog-to-digital converter 30 converts the baseband data signals into digital signals which are distributed by data bus 103. The program via command read circuit 72 causes the digital signals to be stored in appropriate registers, drawn out, transferred, and processed (by multiplier 50, adder 51 and decision circuit 40) as required by the equalizer algorithm. 
     As will be recognized, all of the algorithms and calculations previously described for the analog implementation of the present invention can be performed or approximated by the processing capabilities indicated in the block diagram as will be described in detail hereinbelow. It is assumed that a source of timing, or clock, signals synchronous with the data signal bit rate is available for the program control, sampling, and readout control. 
     The registers utilized in accordance with the present embodiment are as follows: tap output register 40 which stores the tap output values; tap gain register 41 which stores the gain value for each tap; equalizing error signal register 42 which stores the value of the equalizing error signal; accumulator 43 for storing of intermediate processing signals; constant register 48 for storage of constants required during processing; and a set of intermediate registers designated as CA register 44, CI register 45, A register 46 and B register 47. 
     Before describing the operation of the invention in performing the automatic equalizer algorithms and calculations, a brief explanation of the processing functions will be given. 
     Assume that operation of the system is initiated by application of a start signal to instruction counter 70 via input line 70b; the counter output on line 70a then causes program memory 71 to read out the first command of the program stored therein. 
     The read out program command is received by the command read circuit 72 through line 71a and decoded therein. In accordance with the content of the command, it is given to one of the four command transmission lines 110, 120, 130 and 140. Each time a command is read out from program memory 71, instruction counter 70 is stepped one time via line 71b. As is now evident, programs will be sequentially read out from program memory 71 under the direction of instruction counter 70. 
     Assume now that data A is present on the first data bus 101, and data B is present on second data bus 102; multiplication circuit 50 receives the data A from line 50a and the data B from line 50b. The multiplication of A × B is performed on command from the command read circuit upon receipt by multiplier 50 of the appropriate command over the dashed line 130. The multiplication result D is sent to adder 51 via line 50c. 
     Now assume that Data E appears on third data bus 103 and is sent to adder 51 through line 51a; adder 51 then performs either the addition D+E or the subtraction E-D dependent on the command received via dashed line 120 from command read circuit 72. The resultant output is fed to the fourth output data bus 104 by line 51b. 
     To control the storage and readout of data from the registers, commands from command read circuit 72 are sent over dashed line 110 to the following registers: tap output register 40; tap gain register 41; error register 42; accumulator 43; CA register 44; compensation signal register 45; A register 46; B register 47; and constant register 48. In accordance with the particular command, data will be stored in the designated address or the stored data in the designated address will be output to the desired data bus. 
     Having described the general operation of the control program and the method of commanding and controlling each element in the present embodiment of the invention, the specific operation in performing the automatic equalization function will be explained by the sequence in which the steps are accomplished. 
     Step 1: To initially reset the accumulator 43 a constant value &#34;0&#34; is placed on lines 48a, 48b, and 48c by constant register 48 and this &#34;0&#34; is input to multiplier 50 and adder 51 via the data buses 101, 102, 103 and lines 50a, 50b, and 51a. The output line 51b of adder 51 goes to &#34;0&#34; resetting accumulator 43 to &#34;0&#34; by output data bus 104 and line 43b. 
     Step 2: The analog-to-digital converter 30 receives the two baseband signals from the cos ω c  t demodulator and the sin ω c  t demodulator and converts the analog values to the digital values X x  and Y y  respectively. The digital values are sent to the third data bus 103 via line 30a. As above and hereinafter, the signal from the cos ω c  t demodulator will be identified by the subscript x and the signal from the sin ω c  t demodulator by the subscript y. 
     The digital values X x  and Y y  appearing on bus 103 are sent to adder 51 by line 51a. At this time a constant value of &#34;0&#34; from constant register 48 is sent to both data buses 101 and 102 via lines 48a and 48b. Therefore, the inputs to multiplier 50 via lines 50a and 50b are both &#34;0&#34; and output of multiplier 50 is &#34;0.&#34; Adder 51 thus receives this &#34;0&#34; value via line 50c with the result that the digital values X x  and Y y  are unchanged. These values are supplied via data bus 104 and line 40b to tap output register 40 and are stored, or accumulated, therein. Assuming that the desired number, n, of taps is nine (n=9), the program will cause nine of such digital values X K .sbsb.x and Y K .sbsb.y to accumulate in tap output register 40. 
     Step 3: The digital values X K .sbsb.x and Y K .sbsb.y stored in tap output register 40 are sequentially read out and sent to data bus 101 via line 40a. Simultaneously with the storing of X K .sbsb.x and Y K .sbsb.y, the tap gain values (C K .sbsb.x and C K .sbsb.y) are calculated (described in a later step) and stored in tap gain register 41. At this point, previously stored tap gain values are read out and sent to data bus 102 via line 41b. Additionally, the contents of accumulator 43 are sent to data bus 103 via line 43a. The arithmetic operation X K  ·C K  now is carried out in multiplier 50 and adder 51. It is to be noted that the arithmetic operation must be performed for complex numbers. For example, in the case of the quadrature amplitude modulation system, cos ωt is considered a real number and sin ωt is considered an imaginary number. The above-mentioned operation is carried out under the condition that: 
     
         X.sub.K = X.sub.Kx + iX.sub.Ky and C.sub.K = C.sub.Kx + iC.sub.Ky. 
    
     Therefore the operations to be performed are 
     
         X.sub.K C.sub.K = (X.sub.Kx + iX.sub.Ky) (C.sub.Kx + iC.sub.Ky) 
    
     
         = X.sub.Kx C.sub.Kx - X.sub.Ky C.sub.Ky + i(X.sub.Kx C.sub.Ky + X.sub.Ky C.sub.Kx)                                                 (30) 
    
     The above described operation is repeated as many times as there are taps and the results added sequentially. As will now be recognized, this step has produced the combined tap output as shown by equation (4). 
     The role of accumulator 43 in the above calculations is to store certain intermediate real and imaginary products and sums designated as (A cc ) x  and (A cc ) y , respectively. The specific procedures will be followed for calculation of equation (30) and the source of these values thereby identified. 
     The operation X Kx  ·C Ky  is carried out in multiplier 50 and the contents (A cc ) x  of accumulator 43 are added to the output of multiplier 50 at adder 51. The sum is stored in accumulator 43 via output data bus 104 as a new value for (A cc ) x . The operation X Ky  ·C Ky  is similarly performed by multiplier 50 and the product subtracted from the stored (A c ) x  in adder 51 thereby producing the real term of equation (30). The result of this operation is then stored in accumulator 43 as a new (A cc ) x  via output data bus 104. 
     The calculation of the imaginary term of equation (30) involving the sum of X Kx  C Ky  and X Ky  C Kx  is similarly performed by multiplier 50 and adder 51 utilizing the imaginary content of accumulator 43, (A cc ) y . The final imaginary term of equation (30) is stored via bus 104 in accumulator 43 as (A cc ) y . 
     The sequence of operations for calculation of equation (30) is repeated as many times as the number of taps (for example, when the number of taps K is 9, the sequence is repeated 9 times), and the real part and imaginary part of the combined tap output is available from accumulator 43 as (A cc ) x  and (A cc ) y , respectively. These stored values correspond, of course, to the real and imaginary parts of y&#34;(t) of equation (15). 
     Step 4: Next, Z (t) is calculated using equation (17), involving operation with complex numbers. Again, accumulator 43 is utilized to separate and store the various real and imaginary parts as the calculation proceeds as (Acc)x and (Acc)y respectively. The operation for Z (t) proceeds accordingly: 
     
         Z(t) = y&#34;(t) C.sub.APC 
    
     
         = {(a.sub.cc).sub.x + i(A.sub.cc).sub.y } {C.sub.APCx + i C.sub.APCy } 
    
     
         = (A.sub.cc).sub.x C.sub.APCx - (A.sub.cc).sub.y C.sub.APCy + i {(A.sub.cc).sub.y C.sub.APCx + (A.sub.cc).sub.x C.sub.APCy } 
    
     To start the above calculation, an initial value for the real part of C APCx  is set as &#34;1&#34; and stored in CA register 44 and the imaginary part C CAPCy  is set as &#34;0&#34; and stored in CA register 44. The operation (Acc) x  C APCx  is performed by multiplier 50; adder 51 receives the value &#34;0&#34; from the constant register 48 via data bus 103 and generates output (A cc ) x  C APCx , storing this term in the real part storage of A register 46 as A x  via data bus 104. 
     Next, the operation (A cc ) y  C APCy  is performed by multiplier 50; the subtraction between A x  in A register 46 and the output from multiplier 50 is performed by adder 51 and the result stored as a new value A x  in A register 46. 
     The operation of (A cc ) y  C APCx  is performed in a similar manner with its result stored in the imaginary part storage of A register 46 as A y . Next, (A cc ) x  C APCy  is similarly calculated by multiplication circuit 50, added to A y  by adder 51 and the result stored in the A register 46 as A y . Thus, A x  and A y  represent the real and imaginary parts, respectively, of Z (t). 
     Step 5: Having obtained Z (t), the procedure for generating the code output from Z (t) will be explained. As previously described with reference to FIG. 4, eight possible data codes may be transmitted with the codes corresponding to eight data points arranged on the circumference of a circle so that the projections of each point onto the X and Y axes have values of either &#34;1&#34; or &#34;2. &#34; 
     Also, it was indicated that the X and Y axes could be rotated 45° counterclockwise to produce axes X&#39; and Y&#39;. Assuming such axis rotation, it will be understood that each of the data points lies between adjacent axes. For example, point A (000) in FIG. 4 lies between positive axis X and positive axis X&#39;. 
     To determine the code point corresponding to a received signal Z (t), the adjacent axes between which the vector Z (t) (indicated by real part A x  and imaginary part A y ) lies can be found. This operation can be performed by determining if A x  is positive or negative about the X axis; if A y  is positive or negative about the Y axis; and if the vector Z (t) is positive or negative about the X&#39; axis and Y&#39; axis. Accordingly, A x  and A y  stored in A register 46 can be checked for polarity, and the coordinates of vector Z(t) rotated and the converted value checked for its polarity -- i.e., whether positive or negative. 
     The rotation and polarity determination is performed by obtaining the value A x  cos 45° + A y  sin 45°, and the value (A x  cos 135° + A y  sin 135°). These terms will be referred to hereinafter as (A x  + A y ) and (A x  - A y ), respectively, to simplify the notation. 
     The required calculations are performed by decision circuit 60, and FIG. 5 shows a block diagram of this element of the present embodiment. In this figure, 61 represents the D x  register; 62, D Y  register; 63, D X  &#39; register; 64, D Y  &#39; register; 65, LATCH circuit; 66, code output generator; and 67, 68, D OX  output generator and D OY  output generator, respectively. 
     First, to store the positive or negative code bit A x  from A register 46 in D x  register 61 of decision circuit 60, a constant &#34;0&#34; is sent to the data bus 101 and to the data bus 102 from constant register 48. Multiplier 50 performs the operation of &#34;0 × 0&#34;; adder 51, receiving the results of the operation via line 50c, performs the addition between this operation result and A x  of A register 46, supplied via bus 103, and stores the new A x  in register 46 via output data bus 104. 
     The positive or negative code bit A x  is next stored in D x  register 61 of decision circuit 60, via line 60a. Similarly, the positive or negative code bit A y  of A register 46 is stored in the D y  register 62 of decision circuit 60. 
     To obtain the positive or negative code bits for the D x  &#39; and D y  &#39; values, constant register 48 sends a &#34;1&#34; to data bus 101 and A register 46 sends the A y  value to data bus 102. Multiplier 50 carries out the multiplication of &#34;1 × A y  &#34;, while adder 51 performs the addition of this multiplication result and A x  from A register 46, sending the output &#34;A x  + A y  &#34; to output data bus 104, and this sum stored in D x  &#39; register 63. In a similar fashion, adder 51 carries out the subtraction between A x  and A y , sends the &#34;A x  - A y  &#34; to the output data bus 104 and stores the positive/negative code of &#34;A x  - A y  &#34; in the D y  &#39; register 64 of decision circuit 60. After the positive and negative code bits are stored in D-registers 61, 62, 63, 64, each bit output is sent to code output generator 66 sequentially by means of latch circuit 65. The code output generator 66 includes a ROM (read-only memory) and will output any one of the eight codes shown in FIG. 4 according to the polarity sequence of the four output bits from latch circuit 65. Thus, the decision circuit 60 outputs the code group as required for that data symbol duration. This output code also inputs to D ox  output generator 67 and D oy  output generator 68 which generate the values D ox  on the X axis and D oy  on the Y axis, respectively. 
     For example, if the output code group is &#34;000,&#34; the digital output of D ox  will represent a &#34;2&#34; and of D oy  will represent a &#34;1.&#34; The D ox  and D oy  values are sent to data bus 102 of FIG. 3. 
     Step 6: It is now required to generate the error signal E(t) as expressed by equation (18). Consequently, the difference (A x  - D ox ) is calculated and stored as E x  in E register 42, and the difference (A y  - D oy ) calculated and stored as E y  in E register 42, using the subtraction algorithm previously described. In other words, the multiplication circuit 50 performs the multiplication of a constant &#34;1&#34; of the constant value register 48 given via the first data bus 101 and the value D OX  on the above-mentioned second data bus 102 and the adder 51 carries out the subtraction between A x  of the A register 46 given via the third data bus 103 and the multiplication result D OX . Thus, the output (A x  - D OX ) is stored as the E x  in the error signal register 42. In the same way, (A y  - D OY ) is stored as the E y  in the error signal register 42. 
     Step 7: Next, H(t) of equation (26) is obtained utilizing the following relation: 
     
         H(t) = E(t) C*.sub.APC (t) 
    
     
         = (E.sub.x + E.sub.y) (C.sub.APCx - C.sub.APCy) 
    
     H(t) can be transformed as follows: 
     
         H(t) = E.sub.x C.sub.APCx + E.sub.y C.sub.APCy + i(E.sub.y C.sub.APCx - E.sub.x C.sub.APCy) 
    
     The calculation is performed using the same technique for obtaining Z(t) as described in step 4 above. Namely, the multiplication circuit 50 performs the multiplication of E x  and C APCx , while the adder 51 carries out the addition of multiplication result and a constant &#34;0.&#34; Thereby, the result is stored in the A register as the A x  of the A register 46. Then the multiplication circuit 50 performs the multiplication of E y  and C APCy , while the adder 51 carries out the addition of A x  stored and the multiplication result. Thereby, the result is stored in the A register as A x  and, specifically, the real part of H(t) is stored in A register 46 as A x . In a similar way, the operation is performed for the imaginary part A y  and the imaginary part is stored in A register 46 as A y . Thereby A y  = E y  &#39;C APCx  - E x  &#39;C APCy  can be obtained. 
     Step 8: Compensation of the tap gain values is carried out using the value of H(t) computed in step 7 above. For purposes of the computation, C K  is expressed as: 
     
         C.sub.K.sup.(n+1) = C.sub.K.sup.(n) + X.sub.K H*(t) 
    
     
         = C.sub.Kx + iC.sub.Ky + (X.sub.Kx + iX.sub.Ky)(A.sub.x - iA.sub.y) 
    
     
         = C.sub.Kx +X.sub.Kx A.sub.x +X.sub.Ky A.sub.y +i(C.sub.Ky +X.sub.Ky A.sub.x -X.sub.Kx A.sub.y) 
    
     This operation can be performed using the same technique as described in step 3 above. That is, the multiplier 50 performs the multiplication of X kx  of tap output register 40 and A x  of A register 46. Next, adder 51 performs the addition of C kx  of the tap gain register 41 and the result of the multiplication. The result is stored in the tap gain register 41 as C Kx . The calculation of C Ky  is made in the same manner as C Kx . The above operations are repeated as many times as the number of taps K and thus the gain values C Kx  and C Ky  for each tap can be optimized. 
     Step 9: Next E a  (t) is computed in accordance with equation (19) which can be expressed by 
     
         E.sub.a (t) = E(t)a*(τ,T) 
    
     
         = (e.sub.x + iE.sub.y) (D.sub.ox - iD.sub.oy) 
    
     
         = (E.sub.x D.sub.ox + E.sub.y D.sub.oy) + i(E.sub.y D.sub.ox - E.sub.x D.sub.oy). 
    
     This operation is performed using the same technique as described in step 4 above. Decision circuit 60 sends D ox  and D oy  to the data bus 102, error signal register 42 sends E x  and E y  to the data bus 101, and the A register 46 sends A x  and A y  to the data bus 103, and the operation is carried out by the multiplier 50 and adder 51. 
     In other words, multiplier circuit 50 performs the operation of E x  ·D ox , and stores the results in the A register 46 as A x . Next, the multiplier circuit 50 carries out the operation of E y  ·D oy , while the adder 51 performs the addition of stored A x  and the multiplication result and stores the result in the A register as a new value of A x . The operation is similarly performed for the imaginary part and the result is store in the A register 46 as A y . 
     Step 10: Following equation (20), E b  (t) is next calculated. For the computation of b∫E a  (t)dt, (the second term of Equation 20), an approximation of the integration is made by multiplication of the integral coefficient b and E a  (t) (from A x  and A y ) using coefficient b from constant value register 48 and A x  from A register 46. The adder 51 adds C ix  of the CI register 45 to the result of the above multiplication. The result of this addition is then stored in the CI register 45 as a new value for C ix . Initially, the value &#34;1&#34; is stored in CI register 45 as C ix  and C iy  -- i.e., C ix  = C iy  = &#34;1&#34; is input as the initial value into the CI register 45. 
     The same operations are carried out for the imaginary part and C iy  + bA y  is stored as C iy . Next, the constant a is multiplied with A x  and the product added to C ix  and the result stored in A register 46 as a new A x , and the result of multiplication of constant a and A y  is added to C iy  and stored in A register 46 as A y . Thus, the real and imaginary parts of E b  (t) are available as A x  and A y , respectively. 
     Step 11: C APC  is now obtained using equation (21). Accordingly, C APC  ·E b  (t) is obtained first. Denoting C APC  E b  (t) as E c  (t), it can be expressed as 
     
         E.sub.c (t) = (C.sub.APCx + iC.sub.APCy) (A.sub.x + iA.sub.y) 
    
     
         = A.sub.x C.sub.APCx - A.sub.y C.sub.APCy + i(A.sub.x C.sub.APCy + A.sub.y C.sub.APCx) 
    
     This computation can be performed using the same technique as described in step 4 above, and the result stored in B register 47 as B x  and B y . 
     Namely, C APCx , C APCy  of the CA register are sent to the first data bus 101, A x , A y  of the A register 46 of the second data bus. Then, the operation result of the multiplication circuit 50 and the adder 51 is stored in the B register 47. 
     For example, the multiplication circuit performs the operation of C APXx  ·A x  and stores the operation result in the B register as B x  via the adder 51. Then, the multiplication circuit carries out the multiplication of C APCy  ·A y  and the adder 51 carries out the subtraction between B x  and this multiplication result. The result is stored as B x . The operation for B y  (that is, the imaginary part) can be made in the same manner. Then, C APC  is obtained by using B x  and B y . The integration, C APC  ∫E c  (t) dt can now be performed using an approximate calculation with the integral coefficient of &#34;1.&#34; In other words, the computations 
     C APCx  = C APCx  + B x  (i.e., in each successive cycle) 
     C APCy  = C APCy  + B y  (i.e., in each successive cycle) 
     are performed with C APC  obtained. This operation is, of course, accomplished by multiplier 50 performing multiplication of C APCx  from CA register 44 and a constant &#34;1&#34; from constant register 48 with adder 51 adding B x  from B register 47 to the multiplication result. The result is then stored in CA register 44 as a new value of C APCx . C APCy  is also obtained in the same manner, generating a new C APCy  in CA register 44. The values of C APCx  and C APCy  are then used for compensation of X x  and X y  for the next cycle of step 4. 
     As has now been shown, the digital processing implementation of the present invention can compensate for the effect of phase jitter present on the locally-generated carrier without decreasing or significantly affecting the compensating accuracy of the equalizer with respect to the steady state channel characteristics. 
     An analog circuit implementation and a digital implementation of the automatic equalizer have been described hereinabove. However, it will be apparent to those skilled in the art that various other implementations and configurations can be made, following these teachings, and such implementations are to be considered within the scope of the present invention.