Patent Publication Number: US-2023163183-A1

Title: Method of Implanting Dopants into a Group III-Nitride Structure and Device Formed

Description:
PRIORITY CLAIM AND CROSS-REFERENCE 
     This application is a continuation of U.S. application Ser. No. 17/166,775, filed on Feb. 3, 2021, which is a divisional of U.S. application Ser. No. 16/231,793, filed Dec. 24, 2018, now U.S. Pat. No. 10,937,878, issued on Mar. 2, 2021, which is a continuation of U.S. application Ser. No. 13/753,867, filed Jan. 30, 2013, now U.S. Pat. No. 10,164,038, issued Dec. 25, 2018, which applications are hereby incorporated herein by reference. 
    
    
     BACKGROUND 
     Semiconductor devices which include a group III-nitride compound, such as gallium nitride, are used in a device which operates at high frequencies or using high operating voltages. Group III-nitride compounds are also used in optoelectronic devices such as light emitting diodes (LEDs). In order to increase conductivity of the group III-nitride compounds, silicon or magnesium is implanted into source and drain regions of the group III-nitride compound and dopant activation using an annealing process. The implantation process and annealing process increase a number of charge carriers in the group III-nitride compound. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       One or more embodiments are illustrated by way of example, and not by limitation, in the figures of the accompanying drawings, wherein elements having the same reference numeral designations represent like elements throughout. It is emphasized that, in accordance with standard practice in the industry various features may not be drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various features in the drawings may be arbitrarily increased or reduced for clarity of discussion. 
         FIG.  1    is a flow chart of a method of forming a semiconductor device in accordance with one or more embodiments; and 
         FIGS.  2 A- 2 G  are cross sectional views of the semiconductor device formed using the method of  FIG.  1    in accordance with one or more embodiments. 
     
    
    
     DETAILED DESCRIPTION 
     The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are examples and are not intended to be limiting. 
       FIG.  1    is a flow chart of a method  100  of forming a semiconductor device in accordance with one or more embodiments. In operation  102 , a III-V layer is formed over a substrate. In some embodiments, the III-V layer comprises a group III-nitride compound layer. In some embodiments, the group III-nitride compound layer is grown by an epitaxial process. In some embodiments, the epitaxial process is a molecular beam epitaxial process. In some embodiments, the group III-nitride compound layer is formed by metal-organic chemical vapor deposition (MOCVD). In some embodiments, the group III-nitride compound layer is formed by forming at least one buffer layer between a main group III-nitride compound layer and the substrate. In some embodiments, the nitride layer is formed to have a top group III-nitride compound layer over the main group III-nitride compound layer. 
       FIG.  2 A  is a cross sectional view of a semiconductor device  200  following operation  102  in accordance with one or more embodiments. A III-V layer  204  is formed over a substrate  202 . III-V layer  204  is also called group III-nitride compound layer  204 . The group III-nitride compound layer  204  comprises a multi-layer structure. The group III-nitride compound layer  204  comprises a first buffer layer  206  over substrate  202 , a second buffer layer  208  over the first buffer layer, a main group III-nitride compound layer  210  over the second buffer layer and a top group III-nitride compound layer  212  over the main group III-nitride compound layer. In some embodiments, the group III-nitride compound layer  204  includes only one buffer layer. In some embodiment, top group III-nitride compound layer  212  is omitted. 
     In some embodiments, substrate  202  comprises an elementary semiconductor including silicon or germanium in crystal, or polycrystalline structure; a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide; an alloy semiconductor including SiGe, GaAsP, AllnAs, AlGaAs, GainAs, GainP, and GainAsP; any other suitable material; or combinations thereof. In some embodiments, the alloy semiconductor substrate has a gradient SiGe feature in which the Si and Ge composition change from one ratio at one location to another ratio at another location of the gradient SiGe feature. In some embodiments, the alloy SiGe is formed over a silicon substrate. In some embodiments, substrate  202  is a strained SiGe substrate. In some embodiments, the semiconductor substrate has a semiconductor on insulator structure, such as a silicon on insulator (SOI) structure. In some embodiments, the semiconductor substrate includes a doped epi layer or a buried layer. In some embodiments, the compound semiconductor substrate has a multilayer structure, or the substrate includes a multilayer compound semiconductor structure. 
     A crystal structure of first buffer layer  206  is more similar to main group III-nitride compound layer  210  than a crystal structure of substrate  202  is to the main group III-nitride compound layer. The increased similarity in crystal structure facilitates formation of main group III-nitride compound layer  210  on substrate  202 . In some embodiments, first buffer layer  206  comprises aluminum nitride (AlN). In some embodiments, first buffer layer  206  has a thickness ranging from about 20 Angstrom (Å) to about 500 Å. If the thickness of first buffer layer  206  is less than about 20 Å, the first buffer layer does not provide sufficient electrical resistance between main group III-nitride compound layer  210  and substrate  202  and provides insufficient wetting enhancement, in some embodiments. Further, if the thickness of first buffer layer  206  is out of the indicated range, stresses between the crystal lattice structure of second buffer layer  208  and substrate  202  remain high and result in cracks or de-lamination of the second buffer layer, in some instances. 
     Second buffer layer  208  has a crystal structure more similar to main group III-nitride compound layer  210  than first buffer layer  206 . The similar crystal structure aids in the formation of main group III-nitride compound layer  210 . The combination of first buffer layer  206  and second buffer layer  208  changes a crystal structure at a surface of substrate  202  to a crystal structure more similar to main group III-nitride compound layer  210 , thereby enhancing an ability to form the main group III-nitride compound layer. In some embodiments, second buffer layer  208  comprises aluminum gallium nitride (AlGaN). In some embodiments, second buffer layer  208  has a thickness ranging from about 20 Å to about 500 Å. Further, if the thickness of second buffer layer  208  is out of the indicated range, stresses between the crystal lattice structure of second buffer layer  208  and main group III-nitride compound layer  210  remain high and result in cracks, de-lamination of main group III-nitride compound layer  210 , or crystal quality degradation of main group III-nitride compound layer  210 , in some instances. Note that the definition of crystal quality here means the amounts of point defect or dislocation density in crystal layers; while good crystal quality have lower point defect or dislocation density (&lt;10 8  cm −1  for GaN crystal). 
     Main group III-nitride compound layer  210  provides a charge carrying layer for the semiconductor device. In some embodiments, the main group III-nitride compound layer  210  comprises gallium nitride (GaN). In some embodiments, main group III-nitride compound layer may be replaced by other suitable III-V layer comprises gallium arsenide (GaAs), indium phosphate (InP), indium gallium arsenide (InGaAs), indium aluminum arsenide, (InAlAs), gallium antimonide (GaSb), aluminum antimonide (AlSb), aluminum arsenide (AlAs), aluminum phosphate (AlP) or gallium phosphate (GaP). Main nitride layer  210  has a crystal structure similar to second buffer layer  208 . In some embodiments, main group III-nitride compound layer  210  has a thickness ranging from about 1 micrometer (μm) to about 10 μm. 
     Top group III-nitride compound layer  212  is formed on the main group III-nitride compound layer  210  as the strain layer during subsequent processing. A band gap discontinuity exists between the top group III-nitride compound layer  212  and the main group III-nitride compound layer  210 . The top group III-nitride compound layer  212  has a band gap higher than of the main group III-nitride compound layer  210 . Electrons are formed on the top of main group III-nitride compound layer  210 , due to a piezoelectric effect, creating a thin layer of highly mobile conducting electrons. This thin layer is referred to as a two-dimensional electron gas (2-DEG), forming a carrier channel. The carrier channel of 2-DEG is located at main group III-nitride compound layer  210  near an interface of top group III-nitride compound layer  212  and the main group III-nitride compound layer  210 . The carrier channel has high electron mobility, in comparison with doped layers, because main group III-nitride compound layer  210  is undoped or unintentionally doped, and the electrons move freely without collision or with substantially reduced collisions with impurities. In some embodiments, top group III-nitride compound layer  212  comprises an aluminum gallium nitride (Al x Ga 1-x N). In some embodiments, a thickness of top group III-nitride compound layer  212  ranges from about 20 Å to about 300 Å. In this range of thickness, the top group III-nitride compound layer  212  can provide a sufficient piezoelectric effect to form the 2-DEG on the top of the group III-nitride compound layer  210 . 
     Returning to  FIG.  1   , in operation  104 , a passivation layer is formed over the group III-nitride compound layer. In some embodiments, the passivation layer is formed by chemical vapor deposition (CVD), atomic-layer-deposition, physical vapor deposition (PVD), sputtering, combinations thereof or other suitable processes. 
     In operation  106 , main dopants of source and drain regions are implanted into the III-V layer. In some embodiments, the source and drain regions are formed by ion implantation through the passivation layer into the III-V layer. In some embodiments, the source and drain regions comprise p-type dopants. In some embodiments, the source and drain regions comprise n-type dopants. 
       FIG.  2 B  is a cross sectional view of semiconductor device  200  after operation  104  and operation  106  in accordance with one or more embodiments. A passivation layer  214  is over the group III-nitride compound layer  204 . Passivation layer  214  acts as an etch stop layer over the group III-nitride compound layer  204 , in some embodiments. Passivation layer  214  acts as an etch stop layer, for example, during formation of a gate structure on top group III-nitride compound layer  212 . In some embodiments, passivation layer  214  comprises silicon nitride (SiN), silicon oxide (SiO), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ) or other suitable material. In some embodiments, passivation layer  214  has a thickness ranging from about 10 nanometers (nm) to about 800 nm. If the thickness of passivation layer  214  is less than about 10 nm, the passivation layer does not effectively prevent etching of group III-nitride compound layer  204 , in some embodiments. If the thickness of passivation layer  214  is greater than about 800 nm, a size of the passivation layer increases without significant benefit decreasing production cost efficiency, in some embodiments. 
     Main dopants are implanted in the group III-nitride compound layer  204  to form source and drain regions  216  by an implantation process. In some embodiments, the main dopants include silicon, magnesium, beryllium, calcium, zinc, germanium, sulfur, selenium or combinations thereof. A particular main dopant is selected based on whether the source and drain regions are p-type doped or n-type doped regions. In some embodiments, the dopants comprise silicon or other suitable n-type dopants. In some embodiments, the dopants comprise magnesium or other suitable p-type dopants. In some embodiments, a concentration of dopants in source and drain regions  216  ranges from about 1×10 18  atoms/cm 3  to about 1×10 21  atoms/cm 3 . If the dopant concentration is less than about 1×10 18  atoms/cm 3 , source and drain regions  216  do not provide sufficient charge carriers for semiconductor device  200  to function proper, in some embodiments. If the dopant concentration exceeds about 1×10 21  atoms/cm 3 , source and drain regions  216  become saturated, in some embodiments. If semiconductor device  200  becomes saturated, the semiconductor device behaves similar to a constant-current source because charge carriers are not blocked from flowing through the semiconductor device. In some embodiments, source and drain regions  216  extend into group III-nitride compound layer  204  to a depth ranging from about 5 nm to about 100 nm. In some embodiments, the depth of source and drain regions  216  extends through top group III-nitride compound layer  212  into main group III-nitride compound layer  210 . If the depth is less than about 5 nm, source and drain regions  216  form a channel layer having a high resistance which negative impacts performance of semiconductor device  200 , in some embodiments. If the depth exceeds about 100 nm, source and drain regions  216  increase leakage through the group III-nitride compound layer  204  into substrate  202 , in some embodiments. 
     Returning to  FIG.  1   , in operation  108 , group V species are implanted into the source and drain regions. In some embodiments, operation  108  is performed simultaneously with operation  106  or before operation  106 . In some embodiments, the group V species are implanted using an ion implantation process. Group V species include vanadium, niobium, tantalum, protactinium, nitrogen, phosphorous, arsenic, antimony and bismuth or combinations thereof. By combining the group V species with the main dopants, a dopant activation efficiency is increased in comparison with semiconductor devices which do not include group V species. Dopant activation efficiency is a ratio of dopants capable of acting as charge carriers in the semiconductor device to a total number of dopants present. In some embodiments, dopant activation efficiency is increased by about 10% in comparison to a dopant activation efficiency for semiconductor devices without group V species. In some embodiments, the dopant activation efficiency is greater than about 60%. 
       FIG.  2 C  is a cross sectional view of semiconductor device  200  after operation  108  in accordance with some embodiments. Group V species are implanted into source and drain regions  216  by implantation process  220  to form source and drain regions  216 ′. As the concentration of dopants source and drain regions  216 ′ increases, a resistivity of semiconductor device  200  decreases. For example, if a dopant concentration is approximately 9×10 20  atoms/cm 3 , the resistivity of semiconductor device  200  is approximately 1.8×10 −3  Ωcm. If a dopant concentration is approximately 1.5×10 19  atoms/cm 3 , the resistivity of semiconductor device  200  is approximately 1.8×10 −2  Ωcm. If a dopant concentration is approximately 1×10 18  atoms/cm 3 , the resistivity of semiconductor device  200  is approximately 1.5×10 −1  Ωcm. 
     In some embodiments, a ratio of the main dopants to the group V species ranges from about 1,000:1 to about 10:1. If the ratio is less than about 1,000:1, an amount of group V species is insufficient to impact the dopant activation efficiency and a dopant activation temperature, in some embodiments. If the ratio is greater than about 10:1, a number of p-type or n-type dopants in source and drain regions  216 ′ is insufficient for semiconductor device  200  to function properly, in some embodiments. 
     Returning to  FIG.  1   , in operation  110 , dopants in the source and drain regions are activated (also referred to as a dopant activation process). In some embodiments, the dopants are activated by an annealing process. In some embodiments, the annealing process is a rapid thermal annealing process, a flash annealing process, a laser annealing process, a furnace annealing process or another suitable annealing process. In some embodiments, the annealing process is performed using front-side heating, back-side heating or a combination thereof. In some embodiments, a temperature of the dopant activation process ranges from about 800° C. to about 1200° C. If the temperature is less than about 800° C., a number of activated dopants is insufficient for the semiconductor device to function properly, in some embodiments. If the temperature is greater than about 1200° C., damage occurs to portions of the semiconductor device or expensive high temperature materials are used to form the semiconductor device to avoid damage, in some embodiments. In some embodiments, a duration of the anneal process ranges from about 10 μs to about 20 minutes. In semiconductor devices which do not include the group V species, the temperature of the activation process is greater than approximately 1350° C. The higher temperature used in semiconductor devices which do not include group V species increases production costs because energy costs are increased, and expensive high temperature materials are used to form the semiconductor device. In contrast, semiconductor devices which include the group V species are processed at a lower temperature and are able to be formed using less expensive materials. The lower processing temperature also reduces the risk of damage to components of the semiconductor device during the annealing process. 
       FIG.  2 D  is a cross sectional view of semiconductor device  200  after operation  110  in accordance with one or more embodiments. Dopant activation process  230  is used to activate dopants in source and drain regions  216 ′ to form source and drain regions  216 ″. 
     Returning to  FIG.  1   , in operation  112 , source and drain contacts are formed. In some embodiments, the source and drain contacts are formed by etching an opening in the passivation layer and forming a conductive layer in the opening in contact with the source and drain regions. 
       FIG.  2 E  is a cross sectional view of semiconductor device  200  after operation  112  in accordance with one or more embodiments. Source and drain contacts  240  are formed in contact with source and drain regions  216 ″. In some embodiments, source and drain contacts  240  are copper, aluminum, tungsten, combinations thereof or other metallic compounds. In some embodiments, source and drain contacts  240  form an ohmic contact with source and drain regions  216 ″. The ohmic contact between source and drain contacts  240  and source and drain regions  216 ″ which is higher quality than semiconductor devices which do not include group V species in the source and drain regions. The higher quality ohmic contact is a product of the lower resistance in source and drain regions  216 ″ resulting from the inclusion of the group V species. In some embodiments, source and drain contacts  240  comprise polysilicon or other conductive material. 
     Returning to  FIG.  1   , in operation  114 , a capping layer is formed over the source and drain contacts and over the passivation layer. In some embodiments, the capping layer is formed by CVD, PVD, sputtering or other suitable formation process. In some embodiments, an opening is formed in the capping layer and the passivation layer to expose a portion of the nitride layer between the source and drain regions. In some embodiments, the passivation layer acts as an etch stop layer during formation of the opening in the capping layer. 
       FIG.  2 F  is a cross sectional view of semiconductor device  200  after operation  114  in accordance with one or more embodiments. A capping layer  250  is over source and drain contacts  240  and passivation layer  214 . An opening  252  is formed in capping layer  250  and passivation layer  214  to expose a portion of top group III-nitride compound layer  212  between source and drain regions  216 ″. In some embodiments, opening  252  is formed during a multi-step process in which a first opening is formed in capping layer  250  and then a second opening is formed in passivation layer  214 . In some embodiments, passivation layer  214  acts as an etch stop layer during formation of the first opening. Capping layer  250  limits diffusion of atoms from source and drain regions  216 ″ to other parts of semiconductor device  200 . In some embodiments, capping layer  250  comprises SiO, SiN, SiON, silicon carbide (SiC), a low-k dielectric material or other suitable dielectric material. In some embodiments, the low-k dielectric material has a dielectric constant less than a dielectric constant of silicon dioxide. In some embodiments, a thickness of capping layer  250  ranges from about 20 nm to about 1000 nm. If the thickness is less than about 20 nm, capping layer  250  does not effectively prevent atoms from diffusing from source and drain regions  216 ″, in some embodiments. If the thickness is greater than about 1000 nm, a size of capping layer  250  increases without providing significant benefit thereby unnecessarily increasing production costs. 
     Returning to  FIG.  1   , in operation  116 , a gate structure is formed. In some embodiments, the gate structure comprises a gate dielectric and a gate electrode. In some embodiments, the gate structure does not include the gate dielectric. In some embodiments, the gate structure is formed by etching an opening in the capping layer and the passivation layer between the source and drain regions. The gate dielectric and gate electrode are formed in the opening. In some embodiments, the gate dielectric and the gate electrode are formed by CVD, PVD, sputtering or other suitable method. 
       FIG.  2 G  is a cross sectional view of semiconductor device  200  after operation  116  in accordance with one or more embodiments. In some embodiments, gate structure  260  is over capping layer  250 . Gate structure  260  contacts group III-nitride compound layer  204  between source and drain regions  216 ″. In some embodiments where semiconductor device  200  is a high electron mobility transistor (HEMT), gate structure  260  comprises a gate electrode  262 . In some embodiments, gate electrode  262  comprises polysilicon, copper, aluminum or other suitable conductive material. In some embodiments where semiconductor device  200  is a metal insulator semiconductor HEMT (MIS-HEMT), gate structure  260  comprises gate electrode  262  and a gate dielectric  264 . Gate dielectric  264  is between gate electrode  262  and group III-nitride compound layer  204 . In some embodiments, gate dielectric  264  comprises a high-k dielectric material. A high-k dielectric material has a dielectric constant (k) higher than the dielectric constant of silicon dioxide. In some embodiments, the high-k dielectric material has a k value greater than 3.9. In some embodiments, the high-k dielectric material has a k value greater than 8.0. In some embodiments, the gate dielectric comprises silicon dioxide (SiO 2 ), silicon oxynitride (SiON), hafnium dioxide (HfO 2 ), zirconium dioxide (ZrO 2 ) or other suitable materials. 
     One aspect of this description relates to a method of forming a semiconductor device. The method includes forming a III-V compound layer on a substrate and implanting a main dopant into the III-V compound layer to form source and drain regions. The method further includes implanting a group V species into the source and drain regions. 
     Another aspect of this description relates to a semiconductor device including a substrate and a III-V compound layer over the substrate. The semiconductor device further includes source and drain regions in the III-V compound layer, wherein the source and drain regions comprises a first dopants and a second dopant, and the second dopant include a group V material. 
     Still another aspect of this description relates to a method of forming a semiconductor device. The method includes forming a group III-nitride compound layer over a substrate and forming a passivation layer over the group III-nitride compound layer. The method further includes implanting a main dopant into the group III-nitride compound layer to form source and drain regions and implanting a group V species in the source and drain regions. The method further includes activating the source and drain regions. The method further includes forming a capping layer over the source and drain regions and forming a gate structure over the group III-nitride compound layer. 
     It will be readily seen by one of ordinary skill in the art that the disclosed embodiments fulfill one or more of the advantages set forth above. After reading the foregoing specification, one of ordinary skill will be able to affect various changes, substitutions of equivalents and various other embodiments as broadly disclosed herein. It is therefore intended that the protection granted hereon be limited only by the definition contained in the appended claims and equivalents thereof.