Patent Publication Number: US-6709939-B2

Title: Method for fabricating semiconductor device

Description:
This is a continuation of application Ser. No. 10/125,271, filed Apr. 18, 2002, now U.S. Pat. No. 6,586,306. 
    
    
     BACKGROUND 
     1. Technical Field 
     A method for fabricating a semiconductor device is disclosed. In particular, an improved method for fabricating a semiconductor device is disclosed which provides a difference in junction depth by performing at least one implant process for forming an LDD region in a MOSFET having a thin gate oxide in a high speed device having a silicide (self-aligned silicide). 
     2. Description of the Related Art 
     In general, the most important function of a transistor of a semiconductor circuit is a current driving function. A channel width of a metal-oxide-semiconductor field effect transistor (MOSFET) is adjusted in consideration of the current driving function. In the most widely-used MOSFET, an impurity-doped polysilicon layer is used as a gate electrode, and a diffusion region formed by doping an impurity on a semiconductor substrate is used as a source/drain region. 
     A buried channel is formed in a positive metal-oxide-semiconductor field effect transistor (PMOSFET) which uses an N+ doped polysilicon gate electrode in a complementary metal-oxide-semiconductor field effect transistor (CMOSFET). Here, because a negative metal-oxide-semiconductor field effect transistor (NMOSFET) with a channel on its surface and the PMOSFET have different threshold voltages, there are various restrictions in design and fabrication of the device. 
     That is, in the CMOSFET using a dual gate electrode, the dual gate electrodes are formed by ion-implanting N-type and P-type impurities twice. Therefore, a photolithography process should be performed twice, and this complicates the fabrication process. Accordingly, the device is easily contaminated due to a wet process, and thus the process yield and reliability of the devices are reduced. 
     FIGS. 1A through 1C are cross-sectional views illustrating sequential steps of a conventional method for fabricating such a semiconductor device which is an example of a MOSFeT having a thin gate oxide film. 
     First, referring to FIG. 1A, a field oxide  11  defining an active region is formed on a semiconductor substrate  10 . A thin gate oxide  12  and a polysilicon layer (not shown) are formed on the semiconductor substrate  10 . Thereafter, the polysilicon layer is etched using a gate electrode mask as an etching mask, to form a gate electrode  13 . An LDD (lightly doped drain) region  14  is formed by ion-implanting a low concentration impurity to the semiconductor substrate  10  at both sides of or around the gate electrode  13 . An insulating film spacer  15  is formed at side walls of the gate electrode  13 . 
     As shown in FIG. 1B, a first source/drain region  16  is formed by ion-implanting a high concentration impurity to the semiconductor substrate  10  at both sides of or around the insulating film spacer  15 . Thereafter, a second source/drain region  17  is formed by implanting a dopant having a high diffusion ratio at a low dose. 
     As shown in FIG. 1C, a silicide layer  18  is then formed on the surfaces of the gate electrode  13 , and the semiconductor substrate. 
     However, the conventional method for fabricating the semiconductor device has a limit due to a shallow junction region resulting from miniaturization of the device. Specifically, the depth of the junction region is increased by the ion implant process for forming the silicide layer  18 , which influences the LDD region  14  due to the close proximity of the silicide layer  18  to the LDD region  14  as shown in FIG.  1 C. Further, when the silicide layer  18  is formed deeply along the rim of the field oxide, a leakage current is considerably increased in the junction region adjacent to the field oxide  11 . Still further, as the height of the field oxide is decreased during subsequent processes, the leakage current increases. 
     SUMMARY OF THE INVENTION 
     Accordingly, a method for fabricating a semiconductor device is disclosed which can prevent an increase of the junction leakage current and which can improve the process yield and reliability, by forming a deep junction near the field oxide which does not influence the channel region of a MOSFET where a gate oxide is thin (hereinafter referred to as “a core device”), by partially exposing a source/drain region adjacent to the field oxide to a photolithography process for forming an LDD region of an input/output device between the core device and a MOSFET where the gate oxide film (hereinafter referred to as “a input/output device) is thick in a CMOS fabrication process, and by ion-implanting an impurity thereto at the same time an ion implant process is carried out for forming the LDD region of the input/output device region. 
     A disclosed method for fabricating a semiconductor device comprises: forming a field oxide defining an active region on a semiconductor substrate having a central core device region and a peripheral input/output device region; forming a gate oxide on the core device region; forming a gate electrode on the gate oxide; forming a first LDD region by ion-implanting a low concentration of impurity ions to the input/output device region of the active region; forming a photoresist film pattern over the gate electrode and on the sides of the gate electrode, the photoresist film pattern reaching from an end of the gate oxide to a part of input/output device region spaced a determined distance from the gate electrode or gate oxide; forming a second LDD region deeper than the first LDD region by implanting a low concentration of impurity ions by using the photoresist film pattern as an ion implant mask; removing the photoresist film pattern; forming an insulating film spacer on side walls of the gate electrode; forming a deep source/drain region and a shallow source/drain region by implanting a high concentration impurity ions to the input/output device region of the active region of the semiconductor substrate at least once, by using the insulating film spacer as an ion implant mask; and forming a silicide film on the gate electrode and the source/drain regions. 
     A novel semiconductor device made in accordance with the methods disclosed herein is also disclosed. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The disclosed methods and devices will become better understood with reference to the accompanying drawings which are given only by way of illustration and thus are not limitative of the disclosure, wherein: 
     FIGS. 1A through 1C are cross-sectional views illustrating sequential steps of a conventional method for fabricating a semiconductor device; 
     FIGS. 2A through 2D are cross-sectional views illustrating sequential steps of a method for fabricating a semiconductor device in accordance with a first embodiment; and 
     FIGS. 3A through 3D are cross-sectional views illustrating sequential steps of a method for fabricating a semiconductor device in accordance with a second embodiment. 
    
    
     DETAILED DESCRIPTION OF THE PRESENTLY PREFERRED EMBODIMENTS 
     A method for fabricating a semiconductor device in accordance with preferred embodiments will now be described in detail with reference to the accompanying drawings. 
     FIGS. 2A through 2D are cross-sectional views illustrating sequential steps of a method for fabricating a semiconductor device in accordance with a first embodiment. A core device region is shown in an NMOS region or PMOS region of a CMOS. 
     First, referring to FIG. 2A, a field oxide  21  defining an active region is formed on a semiconductor substrate  20 . The active region defined by the field oxide can be further characterized as including a central core device region and a peripheral input/output device region. A gate oxide  22  is formed on the active region of the semiconductor substrate  20 . A polysilicon layer (not shown) is formed on the gate oxide  22 . Here, the gate oxides  22  in the core device region and the input/output device region are formed to be different thickness. 
     Thereafter, the polysilicon layer is etched using a gate electrode mask as an etching mask, to form a gate electrode  23  on the gate oxide  22  in the core device region and the input/output device region, respectively. A first LDD region  24  is formed by ion-implanting a low concentration impurity ions to the semiconductor substrate  20  at both sides of or around the gate electrode  23  in the core device region. At this time, the ion implant process is performed at a dose ranging from about 1×10 13  to about 2×10 15  ions/cm 2  with an ion implant energy ranging from about 10 to about 50 keV. 
     When the core device region is a PMOS region, the ion implant process is performed using BF 2 , B 11  or In as a dopant. In the case that core device region is a NMOS region, the ion implant process is performed using As or P as the dopant. 
     Referring to FIG. 2B, a photoresist film pattern  25  is formed to partially expose the first LDD region  24  at the inner rim of the field oxide  21  in the core device region. The photoresist pattern  25  is used as an LDD ion implant mask in the input/output device region. 
     Then, an impurity is ion-implanted to the exposed portion of the input/output device region and the first LDD region  24  by using the photoresist film pattern  25  as an ion implant mask, thus forming a second LDD region  26 . Here, the ion implant process is performed at a dose ranging from about 1×10 13  to about 2×10 15  ions/cm 2  with an ion implant energy ranging from about 10 to about 50 keV. The second LDD region  26  has a deeper profile than the first LDD region  24  (see FIG.  2 B). 
     Referring to FIG. 2C, the photoresist film pattern  25  is then removed and an insulating film spacer  27  is formed at sides walls of the gate electrode  23 . A first source/drain region  28  is formed by ion-implanting a high concentration impurity to the semiconductor substrate  20  at both sides of or around the insulating film spacer  27 . 
     Still referring to FIG. 2C, a second source/drain region  29  is formed by ion-implanting a high concentration impurity to the semiconductor substrate  20  at both sides of or around the insulating film spacer  27 . Here, the ion implant processes for forming the first source/drain region  28  and the second source/drain region  29  are performed at a dose ranging from about 1×10 13  to about 1×10 16  ions/cm 2  with an ion implant energy ranging from about 5 to about 60 keV. In the case of the PMOS, the ion implant process is carried out by using BF 2 , B 11 , or In. In the case of the NMOS, the ion implant process is performed by using As or P. In addition, heavy ions are used among the identical conductive type doses when forming a shallow region such as the first source/drain region  28 , and light ions are used when forming a deep region such as the second source/drain region  29 . 
     As shown in FIG. 2D, a silicide layer  30  is formed on the gate electrode  23  and the first and second source/drain regions  28 ,  29 . 
     FIGS. 3A through 3D are cross-sectional diagrams illustrating sequential steps of a method for fabricating a semiconductor device in accordance with a second embodiment. As compared with the first embodiment, the processes of FIGS. 2A and 2B are performed in a different order. 
     Turning first to FIG. 3A, a substrate  31  is provided with a field oxide  32  that defines an active region that can be characterized as including a central core region and a peripheral input/output device region. A gate oxide  33  and gate electrode  34  are disposed in the active region. A photoresist film pattern  35  is then formed to partially expose the core device region at the inner rim of the field oxide. Then, an impurity is ion-implanted to the exposed portion of the core device region of the substrate  31  using the photoresist film pattern  35  as an ion implant mask, thus forming a first LDD region  36 . 
     Turning to FIG. 3B, the photoresist film pattern  35  is removed and a second ion implantation step is carried out at a low concentration of impurity ions to form a second LDD region  37 . 
     Turning to FIG. 3C, an insulation film spacer  38  is then formed on the sidewall or sidewalls of the gate electrode  34 /gate oxide  33  structure. Then, a first source/drain region  39  is formed by ion-implanting a high concentration of impurity ions to the semiconductor substrate  31  around the insulating film spacer  38 . Subsequently, a second source/drain region  40  is formed by ion/implanting another high concentration of impurity ions to the semiconductor substrate  31  around the insulating film spacer  27 . The first source/drain region  39  is formed using heavy ions while the second source/drain region  40  is formed using lighter ions. Then, as shown in FIG. 3D, a silicide layer  41  is formed on top of the gate electrode  34  and the first and second source/drain regions  39 ,  40 . 
     As described earlier, in the high speed device structure consisting of a self-aligned silicide, in order to fabricate a device having at least two gate oxide structures in the identical chip, the LDD region of the core device is formed, and the ion implant process for forming the LDD region of the input/output device having a thick gate oxide and the process for forming the source/drain region at the rim of the field oxide of the core device having a thin oxide film are performed at the same time, thereby increasing the depth of the junction region. Thus, a junction leakage current is decreased in the junction region of the peripheral circuit region, and the whole process is simplified without requiring additional processes. As a result, a process yield and reliability of the device are improved. 
     As the present invention may be embodied in several forms without departing from the spirit or essential characteristics thereof, it should also be understood that the above-described embodiments are not limited by any of the details of the foregoing description, unless otherwise specified, but rather should be construed broadly within its spirit and scope as defined in the appended claims, and therefore all changes and modifications that fall within the meets and bounds of the claims, or equivalences of such meets and bounds are therefore intended to be embraced by the appended claims.