Patent Publication Number: US-6711043-B2

Title: Three-dimensional memory cache system

Description:
RELATED APPLICATIONS 
     This application claims the benefit of U.S. Provisional Application No. 60/308,330 filed Jul. 26, 2001, which is incorporated by reference herein. Additionally, this application is a continuation-in-part of U.S. patent application Ser. No. 09/638,334, filed Aug. 14, 2000 now U.S. Pat. No. 6,545,891, which is also incorporated by reference herein. 
    
    
     BACKGROUND 
     A three-dimensional solid-state memory array is a relatively slow memory, but it is a far more economical means of storing data than other semiconductor memory types. The relatively slow read access time of three-dimensional memory arrays is not a drawback when the data read from the memory array is digital audio or digital images. However, when the data read from the memory array is code executed by a host device, a user can notice the delay because the clock speed of the host device is faster than what can typically be supported by a three-dimensional memory array. There is a need, therefore, for adapting three-dimensional memory arrays for use in faster environments. 
     Additionally, several caching topologies are known for use with two-dimensional memory arrays. In one caching topology, separate cache memory and two-dimensional primary memory chips are used. One disadvantage to this multi-chip arrangement is that chip-to-chip busses add cost and power to the system. In another caching topology, the cache memory and the two-dimensional primary memory are integrated in a single silicon chip in the same two-dimensional plane. Although this arrangement eliminates the inter-chip data transmission delay encountered with the multi-chip arrangement, area on the silicon chip is need for busses between the cache memory and the primary memory, thereby increasing die size and cost. Accordingly, there is also a need for a new caching topology that will overcome these disadvantages. 
     SUMMARY 
     The present invention is defined by the following claims, and nothing in this section should be taken as a limitation on those claims. 
     By way of introduction, the preferred embodiments described below provide a three-dimensional memory cache system. In one preferred embodiment, a modular memory device removably connectable to a host device is provided. The modular memory device comprises a substrate, a cache memory array, a three-dimensional primary memory array, and a modular housing. The cache memory array and the three-dimensional primary memory array can be on the same or separate substrates in the modular housing. In another preferred embodiment, an integrated circuit is provided comprising a substrate, a cache memory array in the substrate, and a three-dimensional primary memory array above the substrate. Other preferred embodiments are provided, and each of the preferred embodiments can be used alone or in combination with one another. 
     The preferred embodiments will now be described with reference to the attached drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram of a memory device and host device of a preferred embodiment in which control logic in the memory device is responsible for flow control. 
     FIG. 2 is a block diagram of a memory device and host device of a preferred embodiment in which software in the host device is responsible for flow control. 
     FIG. 3 is an illustration of a preferred embodiment in which a three-dimensional cache system is part of a device that comprises a CPU and software. 
     FIG. 4 is a block diagram of a preferred embodiment in which RAM memory and caching control circuitry are part of a single-chip solution. 
     FIG. 5A is a block diagram of a prior art multi-chip caching topology. 
     FIG. 5B is a block diagram of a prior art systems-on-chips (SoC) caching topology. 
     FIG. 6 is a block diagram of an integrated circuit of a preferred embodiment. 
     FIG. 7 is a block diagram of an integrated circuit of another preferred embodiment. 
     FIG. 8 is a block diagram of a prior art disk drive controller. 
     FIG. 9 is a block diagram of a disk drive controller of a preferred embodiment. 
    
    
     DETAILED DESCRIPTION OF THE PRESENTLY PREFERRED EMBODIMENTS 
     Turning now to the drawings, FIG. 1 is an illustration of one preferred embodiment. In this embodiment, a memory device with a three-dimensional cache system  100  is coupled with a host device  200 . As used herein, the terms “connected to” and “coupled with” are intended broadly to cover elements that are connected to or coupled with one another either directly or indirectly through one or more intervening components. The three-dimensional cache system  100  comprises a solid-state three-dimensional memory array  110  (the “primary memory array”) coupled with control logic  120  and a cache memory array  130  (here, RAM). It is important to note that control logic is not required to be in the memory device in every preferred embodiment and that control logic should not be read into the claims unless explicitly recited therein. 
     The three-dimensional primary memory array  110  preferably comprises a plurality of layers of memory cells stacked vertically above one another and above a substrate of an integrated circuit. Examples of such three-dimensional memory arrays can be found in U.S. Pat. No. 6,034,882 to Johnson et al. and U.S. patent application Ser. No. 09/560,626, both of which are assigned to the assignee of the present invention and are hereby incorporated by reference. It should be noted that some prior memory arrays have cells that protrude either upwardly or downwardly. While these cells have, in the past, been referred to as a “three dimensional memory cell,” these memory cells are arrayed in a conventional two-dimensional array and are not stacked vertically above one another and above a single substrate of an integrated circuit. Accordingly, an array of such cells is not a “three-dimensional memory array,” as that term is used herein. Further, individual integrated circuits each containing a separate two-dimensional memory array can be stacked and secured together. However, the overall three-dimensional structure is not a monolithic “three-dimensional memory array” because the memory cells of the stack are not stacked above a single substrate and the memory cells are not stacked vertically above one another (because there is an interposing substrate between each layer). 
     In the embodiment shown in FIG. 1, the cache memory array  130  takes the form of RAM. In addition to RAM (e.g., SRAM or DRAM), other suitable memory devices can be used, such as but not limited to NOR Flash or EPROM/EEPROM. Accordingly, the cache memory can be either a non-volatile or volatile memory. However, the cache memory array  130  preferably comprises volatile memory cells, and the three-dimensional primary memory array preferably comprises non-volatile memory cells. Also, it is preferred that the three-dimensional primary memory array have a greater storage capacity than the cache memory array and that the memory cells of the three-dimensional primary memory array have a slower access time than memory cells of the cache memory array. As will be clear from the following discussion, a cache memory array is used to temporarily store (1) data that is later to be stored in the three-dimensional primary memory array and/or (2) data that was previously stored in the three-dimensional primary memory array. 
     The host device  200  comprises a processor (here, a CPU  210 ) running software  220 . Any suitable host device can be used. For example, the host device  200  can be a cell phone, and the memory array  110  can store a speech recognition program or a program used to play audio on the cell phone. As another example, the host device  200  can be a set-top box, and the memory array  100  can store an application that allows the set-top box to record television shows featuring designated actors. The data stored in the memory array  110  can be pre-authored data that is delivered with the host device to the end-user, can be data downloaded to the host device, can be data created and stored with the host device  200 , or can be any combination of the foregoing. Additionally, the “code” stored in these devices can be the software upon which the entire system relies, like the operating system of a PC. 
     A three-dimensional solid-state memory has several advantages over disk drives. It has no moving parts, consumes less power, is more compact, and can allow lower-cost system designs. Such memories are particularly well suited for use in cost- and size-sensitive consumer electronic devices but need to be adapted to meet the speed demands of the code and applications resident therein. The preferred embodiments described herein can be used to address these demands. Specifically, fast RAM memory  130  is used in conjunction with the control logic circuitry  120  to increase the performance of the slower, non-volatile three-dimensional memory  110  by regulating the flow of data between the RAM  130  and the host device  200 . The result is an extremely economical way of storing code/applications in a semiconductor device while still meeting performance requirements of the host device. As described below, the control logic  120  manages the caching of data stored in the relatively-slow three-dimensional memory  110  to the relatively-faster RAM  130 . 
     As shown in FIG. 1, the control logic  120  is coupled to the CPU  210  of the host device  200  via a bus. While two lines are shown connecting the control logic  120  and the CPU  210  (the data bus  10  and the flow control bus  20 ), these two lines are preferably part of a single physical bus (i.e., the flow control bus is a copper wire on the bus that contains the data bus). Alternatively, multiple physical busses can be used. In operation, the CPU  210  of the host device  200  requests data from the memory device  100 , and the control logic  120  determines if the requested data is stored in RAM  130 . If the requested data is stored in RAM  130 , the control logic  120  sends the data from RAM  130  to the CPU  210  via the data bus  10 . If the requested data is not stored in RAM  130 , the control logic  120  sends a “wait” signal to the CPU  210  on the flow control bus  20 . The control logic  120  then transfers the requested data from the three-dimensional memory  10  to the RAM  130 . During the time the “wait” signal is asserted, the CPU  210  does not perform any operations, and no data is transferred over the data bus  10  to the CPU  210 . When the data is transferred from the three-dimensional memory array  110  to the RAM  130 , the control logic  120  removes the “wait” signal from the flow control bus and sends the requested data from the RAM  130  to the CPU  210  via the data bus  10 . 
     In the embodiment discussed above, the control logic  120  was responsible for flow control by using the flow control bus to cause the CPU  210  to “wait” while data stored in the three-dimensional memory  110  was cached in RAM  130 . In an alternate embodiment, software in the host device can be responsible for flow control. This alternate embodiment may be preferred when the host device does not accept a flow control bus as input and, accordingly, the control logic cannot send a “wait” signal to the CPU. This alternate embodiment will now be illustrated in conjunction with FIG.  2 . As shown in FIG. 2, a memory device with a three-dimensional cache system  400  is coupled with a host device  500 . While two lines are shown connecting the memory device  400  and the host device  500  (the data bus  300  and side band  310 ), these two lines are preferably part of a single physical bus. The three-dimensional cache system  400  comprises a solid-state three-dimensional memory array  410  coupled with control logic  420  and a cache memory  430  (here, RAM). Preferably, the control logic  420  in this embodiment comprises a DMA controller. The host device  500  comprises a processor (here, a CPU  510 ) and software  520 . In this embodiment, the software  520  knows what data is stored in the RAM  430 . 
     In operation, if the software  520  knows that the data it needs is stored in RAM  430 , it sends a request for that data to the control logic  420 , which retrieves the data from the RAM  430  and sends it to the CPU  510  via the data bus  300 . However, if the software  520  knows that the data it needs is not stored in the RAM  430 , it instructs the control logic  420  to transfer the needed data from the three-dimensional memory  410  to the RAM  430 . While this transfer is taking place, the software  520  performs some other function, such as requesting additional data that is stored in the RAM  430 . The control logic  420  sends the additional data from the RAM  430  to the CPU  510  via the data bus  300 . Accordingly, additional data is transferred on the data bus  300  while the caching takes place, unlike the embodiment described above in which no data is transferred on the data bus while the “wait” signal is provided to the CPU. When the data is cached in the RAM  430 , the control logic  420  sends an interrupt signal in the sideband  310  of the data bus  300 . Data can be flowing on the data bus  300  when the interrupt signal is sent in the sideband  310 . The CPU  510  processes the interrupt command and then the software  530  sends a request for the newly-cached data to the control logic  420 , which retrieves the data from the RAM  430  and sends it to the CPU  510  via the data bus  300 . 
     In another preferred embodiment, instead of using bus based flow control, the control logic interrupts software access to the cache memory by presenting an alternate set of instructions to the host software in lieu of the data residing in the cache memory. In this manner, accesses to the cache memory, which needs to be reloaded from the three-dimensional memory array (the backing store), would be diverted. This diversion allows the control logic sole access to the cache memory for transferring the next block of data from the backing store to the appropriate area in the cache memory. Once the control logic has completed its transfer, it redirects the host software back to the proper area for continuation in the now updated cache memory. 
     There are several alternatives that can be used with these preferred embodiments. For example, in the embodiments discussed above, the three-dimensional cache system was part of a modular memory device comprising a modular housing enclosing a substrate, cache memory array, and three-dimensional primary memory array, which was coupled with a host device comprising a CPU and software. For example, the host device can be a cell phone, and the memory device can be a handheld, modular memory device (such as a memory card or stick) that is removably connectable to the cell phone. In an alternate embodiment, shown in FIG. 3, the three-dimensional cache system is part of a device  320  that comprises the CPU and software. For example, the three-dimensional cache system, CPU, and software can be part of a set-top box. Additionally, while the RAM memory and caching control circuitry was shown as part of a multiple-chip solution in FIGS. 1-3, the RAM memory and caching control circuitry can be part of a single-chip solution  350 , as shown in FIG.  4 . In this way, all parts can exist on one single die. In other words, instead of being on two different substrates, the cache memory array and the three-dimensional non-volatile memory array can be integrated in the same substrate. In another alternate embodiment, instead of being in the memory device  100 , the control logic  120  can be located external to the memory device  100 , such as in the host device  200 . 
     Suitable types of three-dimensional memory arrays are described in the following patent documents, each of which is hereby incorporated by reference: U.S. Pat. Nos. 6,034,882 and 5,835,396 and U.S. patent applications Ser. Nos. 09/638,428; 09/638,334; 09/727,229; 09/638,439; 09/638,427; 09/638,334; 09/560,626; and 09/662,953. While write-many memory cells can be used in the three-dimensional memory array  110 , it is preferred that the memory cells of the three-dimensional memory array be write-once memory cells. In a write-once memory cell, an original, un-programmed digital state of the memory cell (e.g., the Logic 1 state) cannot be restored once switched to a programmed digital state (e.g., the Logic 0 state). The memory cells can be made from any suitable material. The memory cells are preferably made from a semiconductor material; however, other materials such as phase-change materials and amorphous solids as well as those used with MRAM and organic passive element arrays can be used. 
     As mentioned above, the cache memory array and the three-dimensional non-volatile memory array can be two different chips or part of a single-chip solution. The advantages of integrating the cache memory array and the three-dimensional non-volatile memory array in a single chip can be appreciated when viewed against the prior approaches to caching using a two-dimensional memory array. In one prior approach, a cache memory chip  600  (e.g., an SRAM or DRAM memory chip) is placed between a processing unit  610  and a two-dimensional non-volatile memory chip  620  (e.g., a Flash memory chip) (see FIG.  5 A). One disadvantage to this multi-chip arrangement is that the chip-to-chip busses between the processing unit  610 , cache memory chip  600 , and two-dimensional non-volatile memory chip  620  add cost and power to the system. As an alternative to the multi-chip arrangement, a systems-on-chips (SoC) arrangement has been used in which the processing unit  630 , cache memory  640 , and two-dimensional non-volatile memory  650  are integrated in a single silicon chip (see FIG.  5 B). While the SoC approach eliminates the inter-chip data transmission delay encountered with the multi-chip arrangement, there are other disadvantages associated with the SoC approach. First, because area on the silicon chip is used for busses between the cache memory  640  and the non-volatile memory  650 , a larger die must be used, thereby increasing die cost. Additionally, the relatively long busses involved result in relatively large chip power due to driver size. Further, the limited available silicon space requires trading off one memory type for another, limiting the size and complexity of the circuits that can be put on the chip. Also, because the same silicon processing is usually applied to both the cache memory  640  and the non-volatile memory  650 , the individual performance and manufacturability of each type of memory can be compromised. 
     FIG. 6 is a diagram of a caching topology of a preferred embodiment that overcomes the disadvantages described above. In this preferred embodiment, an integrated circuit  700  is provided in which a volatile memory array (the “cache memory array”)  710  is built in a silicon substrate surface  720  and a non-volatile memory array (the “primary memory array”)  730  is built in one or more layers above the silicon substrate surface  720  and the volatile memory array  710 . The non-volatile memory array  730  is a three-dimensional memory array (i.e., its memory cells are arranged in a plurality of layers stacked vertically above one another and above the substrate  720 ). While the volatile memory array  710  can be located in any suitable location in the substrate  720 , the volatile memory array  710  is preferably distributed below the three-dimensional non-volatile memory array  730  in the open area in the substrate  720  defined by support circuitry in the substrate  720  for the three-dimensional primary memory array  730 , as described in U.S. patent application Ser. No. 10/185,588; filed on the same day as the present application), which is assigned to the assignee of the present invention and is hereby incorporated by reference. That application also describes different memories and control logic that can be distributed in the open area in the substrate  720 . 
     It is preferred that the memory cells in the cache memory array  710  have a relatively faster access time (i.e., write and/or read time) than the memory cells in the primary memory array  730  and that the primary memory array  730  have a greater storage capacity than the cache memory array  710 . It should be noted that the non-volatile memory array  730  is called the “primary” memory array because of its larger size with respect to the cache memory array  710 . The primary memory array  730  is not necessarily the largest memory storage unit in the system. For example, as will be described in more detail below, a disk drive with a much larger storage capacity than the primary memory array  730  can be used in conjunction with the integrated circuit  700 . 
     There are several advantages associated with a caching topology using the integrated circuit of this preferred embodiment as compared to prior approaches using a two-dimensional memory array. Like the SoC approach described above, this preferred embodiment eliminates the problems associated with using two different chips to perform caching of data. Integrating multiple functional blocks onto one chip saves system power by eliminating the need for drivers and busses to pass signals between individual chips. Further, integrating the high bandwidth connection between the two memories in a single piece of silicon saves cost and power. There are also several advantages to this preferred embodiment as compared to the SoC approach. First, die cost is reduced because the non-volatile memory array sits above the cache memory array and, hence, saves area. Also, because most of the three-dimensional non-volatile memory process is in separate layers, the cost impact is minimized because the chip size is about half that of a two-dimensional memory array. Second, the bus structure between the cache memory array and the primary memory array can be wide and short because of the relative proximity of the memory arrays. This saves cost (because of the area savings) and power (because of the small drivers needed for short distances). In contrast, the SoC two-dimensional integrated systems requires longer busses and larger die sizes. Further, chip power is reduced with this preferred embodiment because of the higher degree of integration. Finally, with this preferred embodiment, the cells of both memory arrays can be pitch-matched and stacked directly above one another, allowing common sensing and decoding circuitry to be used for both types of cells. This saves cost (because of the area savings) and power (because half as many driver circuits are used). 
     Any suitable form of caching can be implemented with the control logic  740  of the system. The control logic  740  can be formed in the substrate  710  of the integrated circuit  700  (see FIG. 7) or can be separate from the integrated circuit  700  (see FIG.  8 ). Any of the flow control embodiments described above can be used. For example, the control logic  740  can transfer subsets of data stored in the primary memory array  730  to the cache memory array  720  to allow faster access to the data. This emulates a fast memory array with a relatively slow three-dimensional memory array. In operation, the control logic  740  transfers into the cache memory array  720  a subset of data stored in the primary memory array  730  before the data is requested by a processing unit  750 . By reading from the relatively faster cache memory array  720  instead of from the primary memory array  730 , the processing unit  750  spends less time reading stored data. Additionally, this preferred embodiment can be used to provide a higher “virtual density” SRAM array in applications such as 3G cellular phones. 
     The control logic  740  can also be used to control the transfer of data from the cache memory array  720  to the primary memory array  730 . To allow faster writes of data, the control logic  740  temporarily stores data sent by the processing unit  750  in the cache memory array  720  and later transfers the data from the cache memory array  720  to the primary memory array  730 . Because the cache memory array  720  has a faster write time than the primary memory array  730 , the processing unit  750  does not need to wait as long to store data as it would if the data were stored directly in the primary memory array  730 . 
     In another application of this preferred embodiment, the integrated circuit is part of a disk drive controller. The advantages associated with this application can be appreciated when viewed against conventional disk drive controllers. FIG. 8 is a diagram of a prior art disk drive controller  800  coupled between a processing unit  810  and a disk drive  820 . Because of the very slow speed of the mechanical disk drive  820 , a cache memory array (here, a DRAM buffer)  830  is used to increase the speed of the write operation. That is, instead of waiting for the control logic  840  to store data sent from the processing unit  810  in the relatively slower disk drive  820 , the control logic  840  stores the data in the relatively faster DRAM buffer  830 . The control logic  840  later transfers the data from the DRAM buffer  830  to the disk drive  820 . The time between committing the data from the DRAM buffer  830  to disk drive  820  is long enough that a power outage or other form of unanticipated malady can cause data to become invalid in the RAM buffer  820  before transfer of the data to the disk drive  820  is complete. To maintain data integrity, the processing unit  810  waits for positive feedback from the disk drive  820  before it continues processing. Therefore, even with the use of the DRAM buffer  830 , there is a write delay because the processing unit  810  does not complete its transaction until there has been a confirmed write to the disk drive  830 . Additionally, because DRAM needs refreshing, a large amount of data to be stored in the disk drive  830  requires a relatively large amount of power to refresh the DRAM buffer  830 . 
     To avoid the large time penalty in waiting for the drive interface to be ready to receive data, a disk drive controller  900  can be used having an integrated circuit  905  with a cache memory array (e.g., a DRAM buffer)  910  built on the silicon substrate surface and a three-dimensional non-volatile memory array  920  built above the silicon substrate (see FIG.  9 ). While DRAM is used in this example, it should be noted that any high speed volatile memory, such as SRAM, can be used in the cache memory array  910 . In this embodiment, the monolithic DRAM buffer  910  and non-volatile memory array  920  create a two level cache to improve host-write-to-disk performance. The first level of cache is the high speed volatile DRAM buffer  910 , and the second level is the lower speed but non-volatile backing store  920 . The third level of memory is the ultra slow mechanical disk drive  930 . With this preferred embodiment, system write speed is gated by the speed of the level two (non-volatile  920 ) memory and not the very slow level three (disk drive  930 ) memory. In operation, instead of transferring data from the DRAM buffer  910  to the disk drive  930  as in the prior art, the control logic  940  transfers the data from the DRAM buffer  910  to the non-volatile memory array  920  above the substrate. Since writes to the non-volatile memory array  920  are faster than to the disk drive  930 , the processing unit  950  receives a faster write confirmation as compared to the prior approach. The increased capacity of the combined DRAM/non-volatile memory allows for larger and less frequent transfers to the disk drive  930 , thereby improving system performance. 
     The volatile memory cells in the cache memory array can take any suitable form, including, but not limited to, SRAM cells (for a very fast memory) and DRAM cells (for a dense and relatively fast memory). Additionally, any suitable write-once or re-writable non-volatile memory cell that can be formed in vertically-stacked transistor structures above the silicon substrate can be used in the primary memory array. Suitable non-volatile memory cells include, but are not limited to, the Flash cells, junction anti-fuse memory cells, and pillar anti-fuse memory cells described in the patent documents incorporated by reference earlier in this detailed description, as well as EEPROM three-dimensional memory cells using SONOS or floating-gate cells, as described in U.S. patent application Ser. No. 09/927,648, filed Aug. 13, 2001, which is assigned to the assignee of the present invention and is hereby incorporated by reference. 
     In the preferred embodiments described above, a single type of memory cell was used in the cache memory and a different single type of memory cell was used in the three-dimensional memory array. It is important to note that there is no limit to the number of memory types that can be used in each memory array, and that a plurality of memory types can be used per die to resolve different memory requirements. For example, both field-programmable write-once and field-programmable re-writable memory cells can be used in the three-dimensional memory array, as described in U.S. patent application Ser. No. 10/184578, filed on the same day as the present application), which is assigned to the assignee of the present invention and is hereby incorporated by reference. As another example, one die can contain two completely separate 3-D write-once cells, one cell programmed during manufacturing for register settings used by a controller and another updateable in the field to store data, such as a digital media file (e.g., pictures, songs). Additionally, the same die can contain multiple re-writeable memory cells (e.g., Flash, 3-D memory, DRAM, SRAM) to store file system structures (such as a FAT table, root directory, or sub-directory) or data with different speed or access time requirements (e.g., the write and/or read times can vary). As data can be allocated for different performance requirements, a plurality of re-writeable cells can be used for different data types. Moreover, memory cells can be assigned for different levels of cache hierarchies (e.g., L1, L2, L3 cache), as described above. 
     It is intended that the foregoing detailed description be understood as an illustration of selected forms that the invention can take and not as a definition of the invention. It is only the following claims, including all equivalents, that are intended to define the scope of this invention. Finally, it should be noted that any aspect of any of the preferred embodiments described herein can be used alone or in combination with one another.