Patent Publication Number: US-2015061734-A1

Title: Interface circuit

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2013-175925, filed on Aug. 27, 2013; the entire contents of which are incorporated herein by reference. 
     FIELD 
     Embodiments described herein relate generally to an interface circuit. 
     BACKGROUND 
     In an interface circuit, a plurality of circuit blocks operated by a mutually different power supply voltage is connected to each other in some cases. In such cases, a tolerant function is provided for these circuit blocks in order to set a signal voltage irrespective of the power supply voltage. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a block diagram illustrating a schematic configuration of a communication apparatus to which an interface circuit according to a first embodiment is applied; 
         FIG. 2  is a circuit diagram illustrating a schematic configuration of the interface circuit according to the first embodiment; 
         FIG. 3  is a circuit diagram illustrating a schematic configuration of an interface circuit according to a second embodiment; and 
         FIG. 4  is a circuit diagram illustrating a schematic configuration of an interface circuit according to a third embodiment. 
     
    
    
     DETAILED DESCRIPTION 
     In general, according to one embodiment, an interface circuit includes a first pull-down transistor, a mode switching circuit, and a leak-cut circuit. The first pull-down transistor pulls down an input/output terminal. The mode switching circuit controls on and off of the first pull-down transistor based on an enable signal. The leak-cut circuit turns off the first pull-down transistor when a power supply of the mode switching circuit is shut down. 
     Exemplary embodiments of an interface circuit will be explained below in detail with reference to the accompanying drawings. The present invention is not limited to these embodiments. 
     First Embodiment 
       FIG. 1  is a block diagram illustrating a schematic configuration of a communication apparatus to which an interface circuit according to a first embodiment is applied. 
     In  FIG. 1 , in this communication apparatus, communication can be performed by an I2C (Inter-Integrated Circuit) system. In the I2C system, serial communication with a rate of 100 kbps or 400 kbps can be performed between the communication apparatus and peripheral devices such as a NAND flash memory that are directly connected within a short distance, such as within a same substrate. 
     In the I2C system, a signal line B 1  that transmits a serial clock SCL and a signal line B 2  that transmits serial data SDA are provided. The I2C system is divided into a master  1  that takes control of the system and slaves  2  and  3  that are operated according to the control of the master  1 . The master  1  and the slaves  2  and  3  are connected to each other via the signal lines B 1  and B 2 , respectively. The master  1  can communicate with a plurality of slaves  2  and slaves  3 . The signal lines B 1  and B 2  are connected to an external power supply potential VD 1  via a resistor R 1  and a resistor R 2 , respectively. For example, the external power supply potential VD 1  can be set to approximately 5 V (volts). 
     Interface circuits  1 A and  1 B that can set a power supply potential of the master  1  irrespective of the external power supply potential VD 1  of the signal lines B 1  and B 2  are provided in the master  1 . The interface circuits  1 A and  1 B are provided with a tolerant function that prevents a current from flowing to a power supply from an input of the master  1  even when the power supply potential of the master  1  is smaller than the external power supply potential VD 1 . Interface circuits  2 A and  2 B that can set a power supply potential of the slave  2  irrespective of the external power supply potential VD 1  of the signal lines B 1  and B 2  are provided in the slave  2 . The interface circuits  2 A and  2 B are provided with a tolerant function that prevents a current from flowing to a power supply from an input of the slave  2  even when the power supply potential of the slave  2  is smaller than the external power supply potential VD 1 . Interface circuits  3 A and  3 B that can set a power supply potential of the slave  3  irrespective of the external power supply potential VD 1  of the signal lines B 1  and B 2  are provided in the slave  3 . The interface circuits  3 A and  3 B are provided with a tolerant function that prevents a current from flowing to a power supply from an input of the slave  3  even when the power supply potential of the slave  3  is smaller than the external power supply potential VD 1 . 
       FIG. 2  is a circuit diagram illustrating a schematic configuration of the interface circuit  1 A according to the first embodiment. 
     In  FIG. 2 , an input/output terminal P is provided in the interface circuit  1 A. The input/output terminal P can serve as a pad electrode provided on a semiconductor chip. The input/output terminal P is connected to the signal line B 1 . 
     Pull-down transistors N 2  and N 3  that pull down the input/output terminal P, a self-bias circuit  4 , inverters V 1  and V 2 , a buffer F 1 , control transistors P 1  and P 2 , a mode switching circuit  5 , and a leak-cut circuit  6  are provided in the interface circuit  1 A. The self-bias circuit  4  is provided with a transfer transistor N 1  and resistors R 3  and R 4 . The inverter V 1  is provided with a P-type transistor P 4  and an N-type transistor N 4 . The inverter V 2  is provided with a P-type transistor P 5  and an N-type transistor N 5 . The mode switching circuit  5  is provided with an inverter V 3  and a buffer F 2 . The leak-cut circuit  6  is provided with control transistors P 3  and N 6  and a leak-cut transistor N 7 . 
     A P-type transistor can be used for the control transistors P 1  to P 3 . An N-type transistor can be used for the transfer transistor N 1 , the pull-down transistors N 2  and N 3 , the control transistor N 6 , and the leak-cut transistor N 7 . 
     The pull-down transistors N 2  and N 3  pull down the input/output terminal P. In this example, the pull-down transistors N 2  and N 3  are connected to each other in series, a drain of the pull-down transistor N 2  is connected to the input/output terminal P, and a source of the pull-down transistor N 3  is connected to a ground potential VSS. 
     The self-bias circuit  4  generates an input voltage Vin based on a divided voltage that is generated by dividing an external voltage applied to the input/output terminal P. The external voltage applied to the input/output terminal P can be set equal to or lower than the external power supply potential VD 1 . In this example, the resistors R 3  and R 4  are connected to each other in series, and a series circuit of the resistors R 3  and R 4  is connected between the input/output terminal P and the ground potential VSS. A gate of the transfer transistor N 1  is connected to a connection point of the resistors R 3  and R 4 , and a source of the transfer transistor N 1  is connected to the input/output terminal P. 
     The inverters V 1  and V 2  are connected to each other in series, and power feeding is made from the input voltage Vin to the inverters V 1  and V 2 . An internal power supply potential VD 2  is then input to the inverter V 1  and an output of the inverter V 1  is input to the inverter V 2 . The internal power supply potential VD 2  can be set lower than the external power supply potential VD 1  and can be set to approximately 3.3 V, for example. 
     Power feeding is made from an internal power supply potential VD 3  to the buffer F 1 . The input voltage Vin is then input to the buffer F 1  and an output voltage ZI is output from the buffer F 1 . The internal power supply potential VD 3  can be set lower than the internal power supply potential VD 2  and can be set to approximately 1.1 V, for example. In this example, the buffer F 1  can cause the output voltage ZI to be lower-amplified than the external power supply potential VD 1 . Therefore, it is possible to realize a higher speed of subsequent circuits of the buffer F 1  as well as lower power consumption. 
     Power feeding is made from the input voltage Vin to the control transistor P 1  and the control transistor P 1  can turn on the pull-down transistor N 2  when the internal power supply potential VD 2  is shut down. In this case, a gate of the control transistor P 1  is connected to an output of the inverter V 2 , the input voltage Vin is input to a source of the control transistor P 1 , and a drain of the control transistor P 1  is connected to a gate of the pull-down transistor N 2 . 
     Power feeding is made from the internal power supply potential VD 2  to the control transistor P 2  and the control transistor P 2  can turn on the pull-down transistor N 2  when the internal power supply potential VD 2  is supplied. In this case, a gate of the control transistor P 2  is connected to the output of the inverter V 1 , the internal power supply potential VD 2  is input to a source of the control transistor P 2 , and a drain of the control transistor P 2  is connected to the gate of the pull-down transistor N 2 . 
     Power feeding is made from the internal power supply potentials VD 2  and VD 3  to the mode switching circuit  5  and the mode switching circuit  5  controls on and off of the pull-down transistor N 3  based on an enable signal EN. The enable signal EN can switch an input mode and an output mode of the interface circuit  1 A. In the input mode, the input/output terminal P can be pulled up to the external power supply potential VD 1 . In the output mode, the input/output terminal P can be pulled down to the ground potential VSS. In this example, power feeding is made from the internal power supply potential VD 2  to the inverter V 3  and an output of the inverter V 3  is connected to a gate of the pull-down transistor N 3 . Power feeding is made from the internal power supply potential VD 3  to the buffer F 2 , an output of the buffer F 2  is connected to an input of the inverter V 3 , and the enable signal EN is input to the buffer F 2 . 
     Power feeding is made from the input voltage Vin to the leak-cut circuit  6  and the leak-cut circuit  6  can turn off the pull-down transistor N 3  when the internal power supply potential VD 2  is shut down. In this case, the control transistors P 3  and N 6  are connected to each other in series. The input voltage Vin is input to a source of the control transistor P 3  and a gate of the control transistor P 3  is connected to the output of the inverter V 2 . The internal power supply potential VD 2  is input to a gate of the control transistor N 6 . A gate of the leak-cut transistor N 7  is connected to a connection point of the control transistors P 3  and P 6  and a drain of the leak-cut transistor N 7  is connected to a gate of the pull-down transistor N 3 . 
     Thereafter, an external voltage applied to the input/output terminal P is input to the source of the transfer transistor N 1 , is divided at the resistors R 3  and R 4 , and the divided voltage is applied to the gate of the transfer transistor N 1 . Accordingly, a voltage having a threshold voltage of the transfer transistor N 1  subtracted from the divided voltage is output from the source of the transfer transistor N 1  as the input voltage Vin. Subsequently, the input voltage Vin is output via the buffer F 1  as the output voltage ZI. 
     In this case, because the self-bias circuit  4  generates a bias voltage of the transfer transistor N 1  from an external voltage that is applied to the input/output terminal P, even when the internal power supply potential VD 2  is shut down, the input voltage Vin can be generated. Furthermore, the self-bias circuit  4  can generate the input voltage Vin by dropping the external voltage that is applied to the input/output terminal P, and it becomes possible to prevent a high voltage corresponding to the external power supply potential VD 1  from being applied to the buffer F 1 . Therefore, the buffer F 1  can be protected. 
     Further, the input voltage Vin is input to sources of the P-type transistors P 4  and P 5  of the inverters V 1  and V 2 , and is also input to the sources of the control transistors P 1  and P 3 . At this time, when the internal power supply potential VD 2  is supplied, the output of the inverter V 1  becomes a low level, thereby turning on the control transistor P 2 . As a result, the internal power supply potential VD 2  is applied to the pull-down transistor N 2  and a gate potential of the pull-down transistor N 2  becomes a high level, thereby turning on the pull-down transistor N 2 . 
     Meanwhile, when the internal power supply potential VD 2  is shut down, the output of the inverter V 1  becomes a high level, and as the output of the inverter V 1  is inverted by the inverter V 2 , the output of the inverter V 2  becomes a low level, thereby turning on the control transistor P 1 . As a result, the input voltage Vin is applied to the pull-down transistor N 2  and the gate potential of the pull-down transistor N 2  becomes a high level, thereby turning on the pull-down transistor N 2 . 
     In the output mode, the enable signal EN is set to be a low level. The enable signal EN then becomes a high level as it is inverted by the inverter V 3  and a gate potential of the pull-down transistor N 3  becomes a high level, thereby turning on the pull-down transistor N 3 . Accordingly, the input/output terminal P is pulled down to the ground potential VSS via the pull-down transistors N 2  and N 3 . At this time, when the internal power supply potential VD 2  is supplied, the output of the inverter V 1  becomes a low level and the output of the inverter V 2  becomes a high level as the output of the inverter V 1  is inverted by the inverter V 2 . Accordingly, a gate potential of the control transistor P 3  becomes a high level, thereby turning off the control transistor P 3 . Furthermore, a gate potential of the control transistor N 6  becomes a high level, thereby turning on the control transistor N 6 . Accordingly, the ground potential VSS is applied on a gate of the leak-cut transistor N 7  and the leak-cut transistor N 7  is turned off, and thus the gate potential of the pull-down transistor N 3  can be maintained at a high level. 
     Meanwhile, in the input mode, the enable signal EN is set to be a high level. When the internal power supply potential VD 2  is supplied, the enable signal EN becomes a low level as it is inverted by the inverter V 3 , thereby turning off the pull-down transistor N 3 . Accordingly, the input/output terminal P is pulled up to the external power supply potential VD 1 . In the input mode, when the internal power supply potential VD 2  is shut down, the output of the inverter V 1  becomes a high level and the output of the inverter V 2  becomes a low level as the output of the inverter V 1  is inverted by the inverter V 2 . Accordingly, the gate potential of the control transistor P 3  becomes a low level, thereby turning on the control transistor P 3 . As a result, the input voltage Vin is applied to the gate of the leak-cut transistor N 7 , thereby turning on the leak-cut transistor N 7 . Accordingly, the ground potential VSS is applied to the gate of the pull-down transistor N 3  and then the pull-down transistor N 3  is turned off, so that it is possible to prevent a leak current LA from flowing from the input/output terminal P to the ground potential VSS. 
     The configuration shown in  FIG. 2  can be also used for the interface circuits  1 B,  2 A,  2 B,  3 A, and  3 B shown in  FIG. 1 . 
     Second Embodiment 
       FIG. 3  is a circuit diagram illustrating a schematic configuration of an interface circuit  1 A′ according to a second embodiment. 
     In  FIG. 3 , a leak-cut circuit  7  is provided in the interface circuit  1 A′ instead of the leak-cut circuit  6  shown in  FIG. 2 . The leak-cut transistor N 7  is provided in the leak-cut circuit  7 . The input voltage Vin is input to the gate of the leak-cut transistor N 7 . The gate of the leak-cut transistor N 7  can be connected to, for example, a drain of the transfer transistor N 1 . 
     Thereafter, as the input voltage Vin is input to the gate of the leak-cut transistor N 7 , the leak-cut transistor N 7  is turned on. Furthermore, when the internal power supply potential VD 2  is shut down, the output of the inverter V 3  is in a high impedance state. Accordingly, the ground potential VSS is applied to the gate of the pull-down transistor N 3  and then the pull-down transistor N 3  is turned off, so that it is possible to prevent the leak current LA from flowing from the input/output terminal P to the ground potential VSS. 
     Third Embodiment 
       FIG. 4  is a circuit diagram illustrating a schematic configuration of an interface circuit  1 A″ according to a third embodiment. 
     In  FIG. 4 , a mode switching circuit  8  is provided in the interface circuit  1 A″ instead of the mode switching circuit  5  and the leak-cut circuit  6  shown in  FIG. 2 . A NAND circuit A 1  is provided in the mode switching circuit  8 . The enable signal EN is input to a first input terminal of the NAND circuit A 1  and the internal power supply potential VD 2  is input to a second input terminal of the NAND circuit A 1 . An output terminal of the NAND circuit A 1  is connected to the gate of the pull-down transistor N 3 . Power feeding is made from the input voltage Vin to the NAND circuit A 1 . 
     In the output mode, the enable signal EN is set to a low level. When the internal power supply potential VD 2  is supplied, an output of the NAND circuit A 1  becomes a high level and the gate potential of the pull-down transistor N 3  becomes a high level, thereby turning on the pull-down transistor N 3 . Accordingly, the input/output terminal P is pulled down to the ground potential VSS via the pull-down transistors N 2  and N 3 . 
     Meanwhile, in the input mode, the enable signal EN is set to be a high level. When the internal power supply potential VD 2  is supplied, the output of the NAND circuit A 1  becomes a low level and then the pull-down transistor N 3  is turned off. Accordingly, the input/output terminal P is pulled up to the external power supply potential VD 1 . In the input mode, when the internal power supply potential VD 2  is shut down, the output of the NAND circuit A 1  becomes a low level, and then the pull-down transistor N 3  is turned off. Accordingly, it is possible to prevent the leak current LA from flowing from the input/output terminal P to the ground potential VSS. 
     While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.