Patent Publication Number: US-2023138898-A1

Title: Method of fabricating a semiconductor layout and a semiconductor structure

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present disclosure relates to a technical field of fabricating semiconductor, and more particularly, to a method of fabricating a semiconductor layout and a semiconductor structure. 
     2. Description of the Prior Art 
     In the fabrication of integrated circuits (ICs), photolithography has been an essential technique. At present, the resolution required by photolithography at 32 nm node and below has exceeded the limit capability of the present mask aligner. Therefore, the double patterning technique (DPT), which can enlarge the minimum pattern distance on the present mask aligner, has become the solution for the line width between 32 nm to 22 nm. DPT technology includes decomposing a set of high-density circuit patterns into two or more sets of low-density circuit patterns; then fabricating photomasks having the sets of low-density circuit patterns respectively which can be used in the corresponding exposure and etching processes; and finally forming a merged pattern corresponding to the high-density patterns as originally required. 
     However, because DPT must go through multiple exposure processes, overlay control and alignment have always been a concern of DPT, and the problem of overlay control and alignment is more prominent when the high-density circuit pattern is decomposed into two or more sets of circuit patterns with lower density. When DPT occurs overlay errors or inaccurate alignment occur in DPT, it will lead to disconnection or connection of circuit patterns, resulting in serious open circuit or short circuit. Therefore, there is still a need in the industry for a method of fabricating semiconductor layout and semiconductor structure that can overcome the above problems. 
     SUMMARY OF THE INVENTION 
     One of the objectives of the present disclosure provides a method of fabricating a semiconductor layout, in which, an optical proximity correction technique is used to modify an original layout, so as to prevent the connection patterns with dimensions and/or pitches that violates the predetermined rule of photolithography, from causing significant light diffraction during fabricating corresponding patterns of photomask. Accordingly, the present disclosure may improve the quality of the photomask. 
     Another one of the objectives of the present disclosure provides a method of fabricating a semiconductor structure, in which, an optical proximity correction technique is used to modify an original layout, so that, the photomask formed by outputting the original layout may therefor include more accurate patterns and contours. With these arrangements, the semiconductor structure formed through the photomask may significantly improve the reliability of the electrically connection between the metal lines and the conductive pads through a simplified process flow without additionally photolithography step, even when the dimensions and the pitches of the connection patterns which are adjacent with each other, or the dimensions and the pitches of the connection patterns and the to-be split pattern which are adjacent with each other, violate the predetermined rule of photolithography. 
     To achieve the purpose described above, one embodiment of the present disclosure provides a method of forming a semiconductor layout including the following steps. A layout is provided, and the layout includes a plurality of connection patterns separately arranged with each other. The connection patterns are decomposed to a plurality of first connection patterns and a plurality of second connection patterns alternatively arranged with each other. An optical proximity correction process is performed on the first connection patterns and the second connection patterns to form a plurality of third connection patterns and a plurality of fourth connection patterns, wherein at least a portion of the third connection patterns is overlapped with the fourth connection patterns. The third connection patterns and the fourth connection patterns are outputted to form photomasks. 
     To achieve the purpose described above, one embodiment of the present disclosure provides a method of forming a semiconductor structure including the following steps. A layout is provided, and the layout includes a plurality of connection patterns separately arranged with each other. The connection patterns are decomposed to a plurality of first connection patterns and a plurality of second connection patterns alternatively arranged with each other. An optical proximity correction process is performed on the first connection patterns and the second connection patterns to form a plurality of third connection patterns and a plurality of fourth connection patterns, wherein at least a portion of the third connection patterns is overlapped with the fourth connection patterns. The third connection patterns and the fourth connection patterns are outputted to form photomasks, and the photomask is transferred into a target layer to form a plurality of first patterns and a plurality of second patterns, wherein the first patterns are not overlapped with the second patterns. 
     These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG.  1    to  FIG.  6    are schematic diagrams illustrating a method of fabricating a semiconductor layout according to one embodiment in the present disclosure, wherein: 
         FIG.  1    shows a plan view of a semiconductor layout according to one embodiment in the present disclosure; 
         FIG.  2    shows a plan view of a discomposed layout according to one embodiment in the present disclosure; 
         FIG.  3    shows a plan view of another discomposed layout according to one embodiment in the present disclosure; 
         FIG.  4    shows a plan view of a discomposed modification layout according to one embodiment in the present disclosure; 
         FIG.  5    shows a plan view of another discomposed modification layout according to one embodiment in the present disclosure; and 
         FIG.  6    shows a plan view of a modification layout according to one embodiment in the present disclosure. 
         FIG.  7    to  FIG.  9    are schematic diagrams illustrating a method of fabricating a semiconductor structure according to one embodiment in the present disclosure, wherein: 
         FIG.  7    shows a cross-sectional view of a semiconductor structure after forming a photoresist structure according to one embodiment in the present disclosure; 
         FIG.  8    shows a cross-sectional view of a semiconductor structure after forming a photoresist structure after forming another photoresist structure according to one embodiment in the present disclosure; and 
         FIG.  9    shows a cross-sectional view of a semiconductor structure after forming a photoresist structure after patterning a target layer according to one embodiment in the present disclosure. 
         FIG.  10    to  FIG.  14    are schematic diagrams illustrating a method of fabricating a semiconductor layout according to another embodiment in the present disclosure, wherein: 
         FIG.  10    shows a plan view of a discomposed layout according to another embodiment in the present disclosure; 
         FIG.  11    shows a plan view of another discomposed layout according to another embodiment in the present disclosure; 
         FIG.  12    shows a plan view of a discomposed modification layout according to another embodiment in the present disclosure; 
         FIG.  13    shows a plan view of another discomposed modification layout according to another embodiment in the present disclosure; and 
         FIG.  14    shows a plan view of a modification layout according to another embodiment in the present disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     To provide a better understanding of the presented disclosure, preferred embodiments will be described in detail. The preferred embodiments of the present disclosure are illustrated in the accompanying drawings with numbered elements. In addition, the technical features in different embodiments described in the following may be replaced, recombined, or mixed with one another to constitute another embodiment without departing from the spirit of the present disclosure. 
     Please refer to  FIGS.  1 - 6   , which are plan schematic diagrams illustrating a method of fabricating the semiconductor layout according to one embodiment of the present disclosure. Firstly, as shown in  FIG.  1   , a layout  100  is provided, the layout  100  may be a layout of metal connection layers for fabricating semiconductor devices (for example, memory devices such as dynamic random access memory or static random access memory), such as the layout of a 0-th metal layer (M0) and a first metal layer (M1), but is not limited thereto. The layout  100  includes a plurality of patterns arranged with each other, and the dimension (not shown in the drawings) of the patterns or the pitches (not shown in the drawings) between the patterns are preferably smaller than the critical dimension for photolithography, so that, the semiconductor devices may enable to achieve a relative higher integration. The patterns for example include a plurality of connection patterns  110  which are separately arranged with each other and at least one to-be-split pattern  120 , and the to-be-split pattern  213  is arranged between two adjacent ones of the connection patterns  110 . Precisely speaking, the connection patterns  110  are respectively extended along a direction (for example the y-direction as shown in  FIG.  1   ), and which are sequentially arranged in another direction (for example the x-direction as shown in  FIG.  1   ) being perpendicular to the direction (y-direction). It is noted that, at least a part of each connection pattern  110  is not extended along the direction (y-direction), but on the whole, each of the connection patterns  110  may be regarded as extending along the direction (y-direction), as shown in  FIG.  1   . On the other hand, the to-be-split pattern  120  is also extended along the direction (y-direction), and arranged between any two adjacent ones of the connections patterns  110 . In one embodiment, a maximum width W 2  of the to-be-split pattern  120  is larger than a maximum width W 1  of the connection patterns  110 , for example being about 2 to 3 times larger than the maximum width W 1  of the connection patterns  110 , but is not limited thereto. People in the art should fully realize that although six to-be-split patterns  120  are exemplified in the layout  100  of the present embodiment, with each two of them being arranged in the direction (y-direction) for example, and with each to-be-split pattern in alignment with each other in the another direction (x-direction), as shown in  FIG.  1   , the detailed number and arrangement of the to-be-split patterns  120  are not limited to those shown in  FIG.  1    and may be further adjusted according to practical product requirements. 
     Next, the layout  100  is inputted into a computer set (not shown in the drawings), and the layout  100  is decomposed by using the computer set, in which the connections patterns  110  of the layout  100  are decomposed to a plurality of first connection patterns  111  and a plurality of second connection patterns  113 , and each of the to-be-split patterns  120  of the layout  100  are split into a cutting portion  121  and a counterpart cutting portion  123 . It is noted that, the first connection patterns  111  and the second connection patterns  113  are alternatively arranged with each other, with each of the first connection patterns  111  being arranged between two adjacent ones of the second connection patterns  113 , and with each of the second connection patterns  113  being arranged between two adjacent ones of the first connection patterns  111 , as shown in  FIG.  1   . Furthermore, the to-be-split patterns  120  is split into the cutting portion  121  and the counterpart cutting portion  123  through a boundary line  120 L, wherein the cutting portion  121  is arranged adjacent to the second connection patterns  113 , and the counterpart cutting portion  123  is arranged adjacent to the first connection patterns  111 , but is not limited thereto. It is also noted that, the boundary line  120 L of the present embodiment is preferably closed to the counterpart cutting portion  123 , so that the area of the cutting portion  121  may be relative greater than the area of the counterpart cutting portion  123 , as shown in  FIG.  1   , but is not limited thereto. Accordingly, after the layout  100  is decomposed, a decomposed layout  101  as shown in  FIG.  2    and another decomposed layout  103  as shown in  FIG.  3    may be therefore formed, the decomposed layout  101  includes the first connection patterns  111  and the cutting portion  121  arranged with each other, and the another decomposed layout  103  includes the second connection patterns  113  and the counterpart cutting portion  123 . 
     Next, an optical proximity correction process is performed respectively on the decomposed layout  101  and the another decomposed layout  103 , to form a modification layout  101   a  as shown in  FIG.  4    and another modification layout  103   a  as shown in  FIG.  5   . The optical proximity correction process is performed through the computer set to process the first connection patterns  111  and the cutting portion  121  in the decomposed layout  101 , which includes laterally expanding the first connection patterns  111  and the cutting portion  121  along the another direction (the x-direction) to form a plurality of third connection patterns  111   a  and at least one cutting modification portion  121   a , thereby forming the modification layout  101   a . preferably, the first connection patterns  111  and the cutting portion  121  are proportionally enlarged to both sides in the another direction (x-direction), so that each of the third connection patterns  111   a  may therefore obtain an enlarged width W 3 , as shown in  FIG.  4   . On the other hand, the optical proximity correction process is performed through the computer set to process the second connection patterns  113  and the counterpart cutting portion  123  in the decomposed layout  103 , and which also includes laterally expanding the second connection patterns  113  and the counterpart cutting portion  123  along the another direction (the x-direction) to form a plurality of fourth connection patterns  113   a  and at least one counterpart cutting modification portion  123   a , thereby forming the modification layout  103   a . The second connection patterns  113  and the counterpart cutting portion  123  are also proportionally enlarged to both sides in the another direction (x-direction), so that each of the fourth connection patterns  113   a  may also obtain the enlarged width W 3 , as shown in  FIG.  5   . In one embodiment, the width W 3  of each third connection pattern  111   a  or each fourth connection pattern  113   a  may be 1.5 to 3 times larger than the width W 1  of each first connection pattern  111  or each second connection pattern  113 , but is not limited thereto. 
     Then, the third connection patterns  111   a  and the cutting modification portion  121   a  in the modification layout  101   a  and the fourth connection patterns  113   a  and the counterpart cutting modification portion  123   a  are outputted through the computer set to format least one photomask (not shown in the drawings). Preferably, the third connection patterns  111   a  and the cutting modification portion  121   a  are outputted simultaneously to form a first photomask, with the first photomask including patterns corresponding to the third connection patterns  111   a  and the cutting modification portion  121   a  respectively, and the fourth connection patterns  113   a  and the counterpart cutting modification portion  123   a  are outputted simultaneously to form a second photomask, with the second photomask including patterns corresponding to the fourth connection patterns  113   a  and the counterpart cutting modification portion  123   a . After that, photolithography processes are respectively performed through the first photomask and the second photomask, but is not limited thereto. Through these performances, the method of fabricating the semiconductor layout according to one embodiment of the present disclosure is accomplished. 
     It is noteworthy that, after performing the optical proximity correction process through the computer set, if the modification layout  101   a  and the modification layout  103   a  are further integrated into a modification layout  105  as shown in  FIG.  6   , the third connection patterns  111   a  and the fourth connection patterns  113   a  are alternately arranged with each other substantially, and at least a portion of the third connection patterns  111   a  are partially overlapped with the fourth connection patterns  113   a , with the overlapping portion therebetween being about 10% to 50% of the area of the third connection patterns  111   a  or the area of the fourth connection patterns  113   a . Meanwhile, at least a portion of the third connection patterns  111   a  are partially overlapped with the counterpart cutting modification portion  123   a , with the overlapping portion therebetween being about 10% to 50% of the area of the counterpart cutting modification portion  123   a  or the area of the third connection patterns  111   a , and at least a portion of the fourth connection patterns  113   a  are partially overlapped with the cutting modification portion  121   a , with the overlapping portion therebetween being about 10% to 50% of the area of the cutting modification portion  121   a  or the area of the fourth connection patterns  113   a . On the other hand, the cutting modification portion  121   a  and the counterpart cutting modification portion  123   a  are still arranged between adjacent ones of the third connection patterns  111   a  and the fourth connection patterns  113   a , and the cutting modification portion  121   a  is still partially overlapped with the counterpart cutting modification portion  123   a , with the overlapping portion therebetween being about 10% to 50% of the area of the counterpart cutting modification portion  123   a  or the area of the cutting modification portion  121   a , as shown in  FIG.  6   . However, while the third connection patterns  111   a  and the cutting modification portion  121   a  in the modification layout  101   a , and the fourth connection patterns  113   a  and the counterpart cutting modification portion  123   a  in the modification layout  103   a  are respectively outputted to form the first photomask and the second photomask, followed by being transferred to a photoresist layer (not shown in the drawings) through the subsequent exposure and development processes, the width of the corresponding patterns (not shown in the drawings) formed on the photoresist layer based on the third connection patterns  111   a  and the fourth connection patterns  113   a  may be proportionally shrunk, and the corresponding patterns based on the third connection patterns  111   a  and the fourth connection patterns  113   a  may not overlap with each other. Likewise, the width of corresponding patterns (not shown in the drawings) formed on the photoresist layer based on the cutting modification portion  121   a  and the counterpart cutting modification portion  123   a  may also be proportionally shrunk, and the corresponding patterns based on the cutting modification portion  121   a  and the counterpart cutting modification portion  123   a  compose to a pattern corresponding to the to-be-split pattern  120  in the layout  100 . Accordingly, using the overlapped relationship between the third connection patterns  111   a  and the fourth connection patterns  113   a  may improve the possible issues such as light diffraction or poor photolithography caused by the connection patterns  110  in the layout  100  with dimensions and/or pitches that violates the predetermined rule of photolithography, and also, improve the patterns and contours of the first photomask and the second photomask formed by outputting the modification layout  101   a  and the modification layout  103   a . Thus, the quality of the photomask may be significantly improved. 
     According to the method of the present embodiment, the layout  100  is firstly decomposed to enlarge the pitches between the patterns in the layout, thereby forming the decomposed layouts  101 ,  103 . As following, the optical proximity correction technique is performed on the first connection patterns  111 , second connection patterns  113 , cutting portion  121  and the counterpart cutting portion  123  in the decomposed layouts  101 ,  103 , to laterally expand the width of the aforementioned patterns, so that, the connection patterns  110  in the layout  100  with dimensions and/or pitches that violates the predetermined rule of photolithography may at least partially overlapped with each other, to form the third connection patterns  111   a  with at least a portion thereof being partially overlapped with the fourth connection patterns  113   a . With these arrangements, through the third connection patterns  111   a  with at least a portion thereof being partially overlapped with the fourth connection patterns  113   a  may effectively improve the technical problems such as process defects or inaccurate pattern contours caused by the connections patterns  110  in the layout  100  with dimensions and/or pitches that violates the predetermined rule of photolithography, and the photomasks with more accurate patterns and contours may be successfully formed based on the layout  100  under the method of the present embodiment. Thus, the method of the present embodiment enables to optimize the quality of the photomask. 
     Please refer to  FIGS.  7 - 9   , which are schematic diagrams illustrating a method of fabricating a semiconductor structure according to one embodiment in the present disclosure. Firstly, as shown in  FIG.  7   , a substrate  200  is provided, the substrate  200  may be a silicon substrate, a silicon-containing substrate (such as SiC, SiGe), or a silicon-on-insulator (SOI) substrate. Then, a target layer  210 , a protection layer  220 , a first mask layer  230 , a second mask layer  240  and a photoresist structure  250  are sequentially formed on the substrate  200 . In one embodiment, the target layer  210  may include a conductive layer for example including a low resistant metal like aluminum (Al), titanium (Ti), copper (Cu), or tungsten (w), or a dielectric layer, and the target layer  210  may be patterned into required patterns in the subsequent photolithography process. Furthermore, the protection layer  220  for example includes a dielectric material like silicon nitride (SiN), silicon oxide (SiO x ), or silicon oxynitride, and which is covered on the target layer  210  to protect the target layer  210  underneath. The first mask layer  230  and the second mask layer  240  may respectively include mask materials with different etching selectivity, such as silicon oxide or amorphous silicon, so that, the third connection patterns  111   a  and the cutting modification portion  121   a  of the modification layout  101   a  in the aforementioned embodiment may be transferred into the first mask layer  230 , and then the fourth connection patterns  113   a  and the counterpart cutting modification portion  123   a  of the modification layer  103   a  in the aforementioned embodiment may be transferred into the second mask layer  240  in the subsequent processes, but is not limited to be the aforementioned order. 
     Please referring to  FIG.  7   , the photoresist structure  250  further includes a photoresist bottom layer  251 , a photoresist intermediate layer  253 , a bottom anti-reflective coating (BARC) layer  255 , and a patterned photoresist layer  257 . In one embodiment, the photoresist bottom layer  251  may be a spin-on carbon (SOC) layer, which provides a relatively flat surface for the photoresist deposited or coated thereon, so as to facilitate subsequent exposure and development processes. The material of the photoresist intermediate layer  253  may be silicon oxynitride, and the bottom anti-reflective coating layer  255  is used to reduce the reflected light between the photoresist and the substrate  200  during the exposure process. In the present embodiment, a second photomask  201  based on the modification layout  103   a  in the aforementioned embodiment is transferred to a photoresist layer (not shown in the drawings) through exposure and development processes, to form the patterned photoresist layer  257  which includes patterns corresponding to the second photomask. It is noted that, the second photomask includes a substrate  202  for light transmission, such as a transparent quartz substrate, and light shielding patterns  204  formed on the substrate  202 , wherein each of the light shielding patterns  204  is corresponding to the fourth connection patterns  113   a  and the counterpart cutting modification portion  123   a  in the modification layout  103   a  respectively, and the light shielding patterns  204  corresponding to the fourth connection patterns  113   a  includes the corresponding width W 3 . It is also noted that, while each light shielding pattern  204  is transferred to the photoresist layer through the subsequent exposure and development processes to form the patterned photoresist layer  257 , the width of the patterned photoresist layer  257  may be proportionally reduced, for example, being the width W 1  based on the connection patterns  110  in the layout  100 , but is not limited thereto. 
     Then, an etching process is performed to transfer patterns of the patterned photoresist layer  257  to the second mask layer  240  underneath, to form a plurality of first mask patterns  241  and at least one second mask pattern  243 , as shown in  FIG.  8   . Patterns of the first mask patterns  241  may be the same as the patterns of the fourth connection patterns  113   a  in the modification layout  103   a , and patterns of the second mask patterns  243  maybe the same as the pattern of the counterpart cutting modification portion  123   a  in the modification layout  103   a , but not limited thereto. Next, a photoresist structure  260  is formed, to cover on the first mask patterns  241  and the second mask pattern  243 . Precisely speaking, the photoresist structure  260  includes a photoresist bottom layer  261 , a photoresist intermediate layer  263 , and a patterned photoresist layer  265 , wherein the photoresist bottom layer  261  may be an organic dielectric layer (ODL) to fill in the gaps between the first mask patterns  241  and the second mask pattern  243  to provide a flat surface on which photoresist is deposited or coated, and the photoresist intermediate layer  263  may include a silicon-containing hard-mask bottom anti-reflection coating (SHB) layer, but is not limited thereto. Also, in the present embodiment, the first photomask  203  based on the modification layout  101   a  in the aforementioned embodiment is transferred to another photoresist layer (not shown in the drawings) through exposure and development processes, to form the patterned photoresist layer  265  which includes patterns corresponding to the first photomask  203 . It is noted that, the first photomask  203  also includes the a substrate  202  for light transmission, such as a transparent quartz substrate, and light shielding patterns  206  formed on the substrate  202 , wherein each of the light shielding patterns  206  is corresponding to the third connection patterns  111   a  and the cutting modification portion  121   a  in the modification layout  101   a  respectively, and the light shielding patterns  206  corresponding to the third connection patterns  111   a  also includes the corresponding width W 3 . It is also noted that, while each light shielding pattern  206  is transferred to the another photoresist layer through the subsequent exposure and development processes to form the patterned photoresist layer  265 , the width of the patterned photoresist layer  265  may be proportionally reduced, for example, being the width W 1  based on the connection patterns  110  in the layout  100 , but is not limited thereto. 
     As shown in  FIG.  9   , another etching process is performed to simultaneously transfer the patterns of the patterned photoresist layer  265 , the first mask patterns  241  and the second mask pattern  243  to the first mask layer  230  underneath to form a plurality of third mask patterns  231 , a plurality of fourth mask patterns  233 , and at least one fifth mask pattern  235 . Patterns of the third mask patterns  231  and the fourth mask patterns  233  may be respectively the same as the patterns of the fourth connection patterns  113   a  in the modification layout  103   a  and the third connection patterns  111   a  in the modification layout  101   a . The third mask patterns  231  and the fourth mask patterns  233  are alternately arranged with each other, and a pattern of the fifth mask pattern  235  may be the same as the pattern of the to-be-split pattern  120  in the layout  100 . Following these, another etching process may be further performed by using the third mask patterns  231 , the fourth mask patterns  233 , and the fifth mask pattern  235  as a mask to sequentially pattern the protection layer  220  and the target layer  210  underneath, so as to from a plurality of first patterns  211 , a plurality of second patterns  213 , and a third pattern  215  in the target layer  210 . The first patterns  211  and the second patterns  213  are separately and alternately arranged with each other, and the first patterns  211  are not overlapped with the second patterns  213 . The third pattern  215  is arranged at aside of the first patterns  211  and the second patterns  213 , as shown in  FIG.  9   . Through these performances, the method of fabricating the semiconductor structure in the present embodiment is accomplished. 
     According to the method of the present embodiment, the first photomask  203  and the second photomask  201  based on the modification layout  101   a ,  103   a  respectively are transferred to different photoresist layers through different photolithography processes, to form the patterned photoresist layers  265 ,  257 , followed by patterning the target layer  210  through the patterned photoresist layer  265 ,  257 , to form the first patterns  211 , the second patterns  213 , and the third pattern  215 . In this way, patterns of the first patterns  211 , the second patterns  213  and the third pattern  215  in the target layer  210  may be corresponding to the connection patterns  110  and the to-be-split pattern  120 , obtaining corresponding dimensions and pattern contours. Therefore, the method of the present embodiment enables to effectively and faithfully transfer the connection patterns  110  of the layout  100  to a semiconductor wafer through the photolithography process, so as to prevent the patterns from being break or having vague pattern contours. 
     People well known in the arts should easily realize the method of fabricating the semiconductor layout in the present disclosure is not limited to the aforementioned embodiment, and may further include other examples or variety. For example, in order to further modify the connection patterns  110  in the layout  100  with dimensions and/or pitches that violates the predetermined rule of photolithography, additional processes may be further performed either before or after performing the optical proximity correction process. The following description will detail the different embodiments of the method of fabricating the semiconductor layout in the present disclosure. To simplify the description, the following description will detail the dissimilarities among the different embodiments and the identical features will not be redundantly described. In order to compare the differences between the embodiments easily, the identical components in each of the following embodiments are marked with identical symbols. 
     Please refer to  FIGS.  10 - 14   , which are plan schematic diagrams illustrating a method of fabricating the semiconductor layout according to another embodiment of the present disclosure. The method of fabricating the semiconductor layout in the present embodiment is substantially the same as the method of fabricating the semiconductor layout in the aforementioned embodiment as shown in  FIGS.  1 - 3   , and all similarities will not be redundantly described thereinafter. The differences between the present embodiment and the aforementioned embodiment is mainly in that a plurality of dummy connection patterns is previously formed in the decomposed layout  101  and in the decomposed layout  103 , before performing the optical proximity correction process, with each pattern (including the first connection patterns  111 , the second connection patterns  113 , the cutting portion  121 , the counterpart cutting portion  123  and the said dummy connection patterns) in the decomposed layout  101  and the decomposed layout  103  may obtaining the same pitch substantially. Accordingly, the decomposed layout  101  and the decomposed layout  103  may therefore maintain a certain degree of integration as a whole, so as to facilitate the subsequent exposure manufacturing process. 
     Precisely speaking, a plurality of first dummy connection patterns  331  separately arranged with each other is formed in the decomposed layout  101 , to arrange either between any two adjacent ones of the first connection patterns  111 , or between the adjacent ones of the first connecting patterns  111  and the cutting portion  121 , and then, a decomposed layout  301  as shown in  FIG.  10    is formed thereby. Also, a plurality of second dummy connection patterns  333  separately arranged with each other is formed in the decomposed layout  103 , to arrange either between any two adjacent ones of the second connection patterns  113 , or between adjacent ones of the second connecting patterns  113  and the counterpart cutting portion  123 , and then, a decomposed layout  303  as shown in  FIG.  11    is formed thereby. It is noted that, according to the decomposed layout  301 , the first dummy connection patterns  331  are completely not overlapped with the first connection patterns  111  or the cutting portion  121 . Preferably, the arranged locations of the first dummy connection patterns  331  may partially overlap the arranged locations of the second connection patterns  113  in the layout  100 , and each of the first dummy connection patterns  331  may have the same maximum width W 1  as each first connection pattern  111 . According to the decomposed layout  303 , the second dummy connection patterns  333  are completely not overlapped with the second connection patterns  113  or the counterpart cutting portion  123 . Preferably, the arranged locations of the second dummy connection patterns  333  may partially overlap the arranged locations of the first connection patterns  111  in the layout  100 , and has the same maximum width W 1  as each second connection pattern  113 . It is also noted that, if the decomposed layout  301  and the decomposed layout  303  are further integrated into a modification layout (not shown in the drawings), the arranged locations of the first dummy connection patterns  331  maybe optionally not overlapped with the second dummy connection patterns  333 , or partially overlapped with the second dummy connection patterns  333 . The relative relationship between the first dummy connection patterns  331  and the second dummy connection patterns  333  may be further adjusted based on the practical requirements of the actual semiconductor layout. 
     Then, an optical proximity correction process is performed respectively on the decomposed layout  301  and the another decomposed layout  303 , to form a modification layout  301   a  as shown in  FIG.  12    and another modification layout  303   a  as shown in  FIG.  13   . The optical proximity correction process is performed through the computer set to process the first connection patterns  111 , the first dummy connection patterns  331 , and the cutting portion  121  in the decomposed layout  301 , which includes laterally expanding the first connection patterns  111 , the first dummy connection patterns  331 , and the cutting portion  121  along the another direction (the x-direction) to form a plurality of third connection patterns  111   a , a plurality of third dummy connection patterns  331   a , and at least one cutting modification portion  121   a , thereby forming the modification layout  301   a . preferably, the first connection patterns  111 , the first dummy connection patterns  331 , and the cutting portion  121  are proportionally enlarged to both sides in the another direction (x-direction), so that each of the third connection patterns  111   a  and each of the third dummy connection patterns  331   a  may therefore obtain an enlarged width W 3 , as shown in  FIG.  12   . On the other hand, the optical proximity correction process is performed through the computer set to process the second connection patterns  113 , the second dummy connection patterns  333 , and the counterpart cutting portion  123  in the decomposed layout  303 , and which also includes laterally expanding the second connection patterns  113 , the second dummy connection patterns  333 , and the counterpart cutting portion  123  along the another direction (the x-direction) to form a plurality of fourth connection patterns  113   a , a plurality of fourth dummy connection patterns  333   a , and at least one counterpart cutting modification portion  123   a , thereby forming the modification layout  303   a . The second connection patterns  113 , the second dummy connection patterns  333  and the counterpart cutting portion  123  are also proportionally enlarged to both sides in the another direction (x-direction), so that each of the fourth connection patterns  113   a  and each of the fourth dummy connection patterns  333   a  may obtain the enlarged width W 3 , as shown in  FIG.  13   . In one embodiment, the width W 3  of each third connection pattern  111   a  or each fourth connection pattern  113   a  may be 1.5 to 3 times larger than the width W 1  of each first connection pattern  111  or each second connection pattern  113 , and the width of each third dummy connection pattern  331   a  or each fourth dummy connection pattern  333   a  may be 1.5 to 3 times larger than the width W 1  of each first dummy connection pattern  331  or each second dummy connection pattern  333 , but are not limited thereto. 
     Following these, the third connection patterns  111   a , the third dummy connection patterns  331   a , and the cutting modification portion  121   a  in the modification layout  301   a , and the fourth connection patterns  113   a , the fourth dummy connection patterns  333   a , and the counterpart cutting modification portion  123   a  are outputted by the computer set to format least one photomask (not shown in the drawings). Preferably, the third connection patterns  111   a , the third dummy connection patterns  331   a  and the cutting modification portion  121   a  are outputted simultaneously to form a first photomask (not shown in the drawings), with the first photomask including patterns corresponding to the third connection patterns  111   a , the third dummy connection patterns  331   a , and the cutting modification portion  121   a  respectively, and the fourth connection patterns  113   a , the fourth dummy connection patterns  333   a , and the counterpart cutting modification portion  123   a  are outputted simultaneously to form a second photomask (not shown in the drawings), with the second photomask including patterns corresponding to the fourth connection patterns  113   a , the fourth dummy connection patterns  333   a  and the counterpart cutting modification portion  123   a . After that, photolithography processes are respectively performed through the first photomask and the second photomask, but is not limited thereto. Through these performances, the method of fabricating the semiconductor layout according to the another embodiment of the present disclosure is accomplished. It is noteworthy that, after performing the optical proximity correction process through the computer set, if the modification layout  301   a  and the modification layout  303   a  are further integrated into a modification layout  305  as shown in  FIG.  14   , the third connection patterns  111   a  and the fourth connection patterns  113   a  are still alternately arranged with each other, at least a portion of the third connection patterns  111   a  are partially overlapped with the fourth connection patterns  113   a  and/or the fourth dummy connection patterns  333   a  with the overlapping portion therebetween being about 10% to 50% of the area of the third connection patterns  111   a , the fourth connection patterns  113   a , or the fourth dummy connection patterns  333   a , and at least a portion of the fourth connection patterns  113   a  are partially overlapped with the third dummy connection patterns  331   a , with the overlapping portion therebetween being about 10% to 50% of the area of the fourth connection patterns  113   a  or the area of the third dummy connection patterns  331   a . Furthermore, at least a portion of the third dummy connection patterns  331  may be partially overlapped with the fourth dummy connection patterns  333   a , as shown in  FIG.  14   . On the other hand, the cutting modification portion  121   a  and the counterpart cutting modification portion  123   a  are still arranged between adjacent ones of the third connection patterns  111   a  and the fourth connection patterns  113   a , and the cutting modification portion  121   a  is still partially overlapped with the counterpart cutting modification portion  123   a . Meanwhile, at least a portion of the third connection patterns  111   a  is still partially overlapped with the counterpart cutting modification portion  123   a , with the overlapping portion therebetween being about 10% to 50% of the area of the counterpart cutting modification portion  123   a  or the area of the third connection patterns  111   a , at least a portion of the fourth connection patterns  113   a  is still partially overlapped with the cutting modification portion  121   a , with the overlapping portion therebetween being about 10% to 50% of the area of the cutting modification portion  121   a  or the area of the fourth connection patterns  113   a , as shown in  FIG.  14   . Accordingly, through the overlapped relationship between the third connection patterns  111   a  and the fourth connection patterns  113   a , and between the third dummy connection patterns  331   a  and the fourth dummy connection patterns  333   a , the method of the present embodiment may improve the possible issues such as light diffraction or poor photolithography caused by the connection patterns  110  in the layout  100  with dimensions and/or pitches that violates the predetermined rule of photolithography. Particularly, through the partial overlapped relationship between the fourth connection patterns  113   a  and the third dummy connection patterns  331 , and between the third connection patterns  111   a  and the fourth dummy connection patterns  333   a , the method of the present embodiment may compensate the patterns and contours of the fourth connection patterns  113   a  and the third connection patterns  111   a , so as to improve the patterns and contours of the first photomask and the second photomask formed by outputting the modification layout  301   a  and the modification layout  303   a . Thus, the quality of the photomasks may be significantly improved. 
     According to the method of the present embodiment, the layout  100  is firstly decomposed to enlarge the pitches between the connection patterns of the layout  100 , thereby forming the decomposed layouts  101 ,  103 . Next, dummy connection patterns are disposed in the decomposed layout  101 ,  103 , to form the decomposed layouts  301 ,  303 . Then, the optical proximity correction technique is performed on the first connection patterns  111 , the first dummy connection patterns  331 , the second connection patterns  113 , the second dummy connection patterns  333 , the cutting portion  121  and the counterpart cutting portion  123  in the decomposed layouts  301 ,  303 , to laterally expand the width of the aforementioned patterns, so that, the connection patterns  110  in the layout  100  with dimensions and/or pitches that violates the predetermined rule of photolithography may at least partially overlapped with each other, to form the third connection patterns  111   a  and the fourth connection patterns  113   a  at least partially overlapped with each other and/or the third dummy connection patterns  331   a  and the fourth dummy connection patterns  333   a  at least partially overlapped with each other. With these arrangements, through the third connection patterns  111   a  with at least a portion thereof being partially overlapped with the fourth connection patterns  113   a  and/or the third dummy connection patterns  331   a  with at least a portion thereof being partially overlapped with the fourth dummy connection patterns  333   a  may effectively improve the technical problems such as process defects or inaccurate pattern contours caused by the connections patterns  110  in the layout  100  with dimensions and/or pitches that violates the predetermined rule of photolithography, and the photomask with more accurate patterns and contours may be successfully formed based on the layout  100  under the method of the present embodiment. Thus, the method of the present embodiment enables to optimize the quality of the photomask, and then, the connection patterns  110  of the layout  100  may be effectively and faithfully transferred to a semiconductor wafer through the photolithography process in the present embodiment. 
     Overall speaking, the method of fabricating the semiconductor layout and the method of fabricating the semiconductor structure in the present disclosure use the optical proximity correction process to modify the connection patterns, and, the photomask formed by outputting the layout may therefore obtain more accurate patterns and contours. With these arrangements, the semiconductor structure formed through the photomask may significantly improve the reliability of the electrically connection between the metal lines and the conductive pads through a simplified process flow without additionally photolithography step, even when the dimensions and the pitches of the connection patterns which are adjacent with each other, or the dimensions and the pitches of the connection patterns and the to-be split pattern which are adjacent with each other, violate the predetermined rule of photolithography. 
     Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.