Patent Publication Number: US-9420653-B2

Title: LED driver circuit and method

Description:
BACKGROUND 
     The present invention relates, in general, to electronics and, more particularly, to methods of forming semiconductor devices and structure. 
     In the past, the electronics industry used Light Emitting Diodes (LEDs) for a variety of applications. Improvements in the quality and efficiency of LEDs facilitated the use of LEDs in automotive lighting applications such as for brake lights and taillights. Further advances in LEDs facilitated the use for more traditional AC lighting applications such as traffic lights, fluorescent lights, street lights and other lighting applications. Typical control systems for LED applications converted an AC waveform into a DC voltage and used this DC voltage to power the LEDs. Systems to control LEDs are disclosed in U.S. Pat. No. 6,285,139 issued to Mohamed Ghanem on Sep. 4, 2001 and U.S. Pat. No. 6,989,807 issued to Johnson Chiang on Jan. 24, 2006. Most such LED control systems had a high cost. Other systems to control LEDs are disclosed in U.S. Pat. Nos. 6,038,016, 6,150,774, and 6,806,659 issued to Mueller et al. on Jan. 18, 2000, Nov. 21, 2000, and Oct. 19, 2004, respectively. 
     Accordingly, it would be advantageous to have a method and circuit for driving one or more LEDs. In addition, it is desirable for the method and circuit to be cost and time efficient to implement. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The present invention will be better understood from a reading of the following detailed description, taken in conjunction with the accompanying drawing figures, in which like reference characters designate like elements and in which: 
         FIG. 1  is a schematic diagram of a portion of an LED driver circuit in accordance with an embodiment of the present invention; 
         FIG. 1A  is a schematic diagram of a portion of an LED driver circuit in accordance with another embodiment of the present invention; 
         FIG. 2  is a schematic diagram of a portion of an LED driver circuit in accordance with another embodiment of the present invention; 
         FIG. 2A  is a schematic diagram of a portion of an LED driver circuit in accordance with another embodiment of the present invention; 
         FIG. 2B  is a schematic diagram of a portion of an LED driver circuit in accordance with another embodiment of the present invention; 
         FIG. 3  is a schematic diagram of a portion of an LED driver circuit in accordance with another embodiment of the present invention; 
         FIG. 3A  is a schematic diagram of a portion of an LED driver circuit in accordance with another embodiment of the present invention; 
         FIG. 4  is a schematic diagram of a portion of an LED driver circuit in accordance with another embodiment of the present invention; 
         FIG. 4A  is a schematic diagram of a portion of an LED driver circuit in accordance with another embodiment of the present invention; 
         FIG. 5  is a schematic diagram of a portion of an LED driver circuit in accordance with another embodiment of the present invention; and 
         FIG. 5A  is a schematic diagram of a portion of an LED driver circuit in accordance with another embodiment of the present invention; 
         FIG. 6  is a block diagram of an LED lighting system in accordance with another embodiment of the present invention. 
     
    
    
     For simplicity and clarity of the illustration, elements in the figures are not necessarily to scale, and the same reference characters in different figures denote the same elements. Additionally, descriptions and details of well-known steps and elements are omitted for simplicity of the description. As used herein current carrying electrode means an element of a device that carries current through the device such as a source or a drain of an MOS transistor or an emitter or a collector of a bipolar transistor or a cathode or anode of a diode, and a control electrode means an element of the device that controls current flow through the device such as a gate of an MOS transistor or a base of a bipolar transistor. Although the devices are explained herein as certain N-channel or P-channel devices, or certain N-type of P-type doped regions, a person of ordinary skill in the art will appreciate that complementary devices are also possible in accordance with embodiments of the present invention. It will be appreciated by those skilled in the art that the words during, while, and when as used herein are not exact terms that mean an action takes place instantly upon an initiating action but that there may be some small but reasonable delay, such as a propagation delay, between the reaction that is initiated by the initial action. The use of the word approximately or substantially means that a value of an element has a parameter that is expected to be very close to a stated value or position. However, as is well known in the art there are always minor variances that prevent the values or positions from being exactly as stated. It is well established in the art that variances of up to about ten percent (10%) (and up to twenty percent (20%) for semiconductor doping concentrations) are regarded as reasonable variances from the ideal goal of exactly as described. 
     DETAILED DESCRIPTION 
     Generally the present invention provides a Light Emitting Diode (LED) driver circuit and a method for driving an LED. In accordance with embodiments of the present invention, the LED driver is configured to operate in a high light emission state or a low light emission state. In an aspect, current flows through one or more LEDS in the high and low light emission states. However, the intensity of the light emitted in the high light emission state is much greater than the intensity of the light emitted in the low light emission state. Thus, in the low light emission state the intensity of the light emitted by the one or more diodes may be sufficiently low as to appear off. 
     In accordance with other embodiments, current may flow through the one or more LEDs in the high light emission state and may not flow through the one or more LEDs during the low light emission state. 
       FIG. 1  is a circuit schematic of a Light Emitting Diode (LED) driver circuit  10  in accordance with an embodiment of the present invention. LED driver circuit  10  includes a level shift circuit  12  and a current source  14  connected to a voltage follower circuit  16  and a plurality of input/output (I/O) nodes  18 ,  20 , and  22 . It should be noted that level shift circuit  12 , current source  14 , and voltage follower circuit  16  may be monolithically integrated into a single semiconductor substrate or a single semiconductor material. In embodiments in which I/O nodes  18 ,  20 , and  22  are connected to or serve as input/output pins of driver circuit  10 , I/O nodes  18 ,  20 , and  22  may be referred to as input/output (I/O) pins. I/O nodes  18 ,  20 , and  22  may also be referred to as I/O terminals. By way of example, voltage follower circuit  16  may be comprised of an operational amplifier  24  coupled to a field effect transistor  26 . More particularly, operational amplifier  24  has a noninverting input  28 , an inverting input  30 , and an output  32  and transistor  26  may be a field effect transistor having a gate, a source, and a drain, where output  32  of operational amplifier  24  is connected to the gate of transistor  26  and inverting input  30  is connected to the source of transistor  26 . Input  28  may serve as the input of voltage follower circuit  16  and the commonly connected inverting input  30  and the source of transistor  26  may serve as the output of voltage follower circuit  16 . Current source  14  has a terminal that may serve as or alternatively may be connected to I/O node  18  and a terminal connected to the drain of field effect transistor  26  to form a node that may serve as or alternatively may be connected to I/O node  20 . 
     In accordance with an embodiment of the present invention, level shift circuit  12  may include a field effect transistor  34  and a plurality of resistors  36 ,  38 , and  40 . Resistor  36  is coupled between the drain and source of field effect transistor  34  where the source and a terminal of resistor  36  are commonly coupled for receiving a source of operating potential V SS . By way of example, source of operating potential V SS  is ground potential. Resistor  38  is coupled between the drain of field effect transistor  34  and noninverting input  28  of operational amplifier  24  and resistor  40  has a terminal commonly connected to resistor  38  and input  28 , and a terminal coupled for receiving a source of operating potential V DD . Alternatively, resistor  40  may be coupled for receiving a reference potential V REF . The gate of field effect transistor  34  serves as an input  13  of level shift circuit  12  and may be coupled for receiving pulse width modulation signals (V PWM ). 
     In operation, a circuit element  42  is coupled between I/O node  18  and I/O node  20  and a set resistor  44  may be connected between I/O node  22  and a source of operating potential such as, for example, V SS . By way of example, circuit element  42  is a light emitting diode in which its anode is connected to I/O node  18  and its cathode is connected to I/O node  20 . Current source  14  injects a bypass current I BYPASS  into I/O node  20  and a set current I SET  is sunk from I/O node  22 . Set current I SET  is generated in accordance with Ohm&#39;s Law by developing a voltage across set resistor  44 . More particularly, set current I SET  is generated in accordance with a pulse width modulation signal V PWM  appearing at input  13  such that level shift circuit  12  transmits a bias voltage V BIAS  to noninverting input  28  of voltage follower circuit  16 . It should be noted that voltage follower circuit  16  and set resistor  44  cooperate to form a current generation circuit. In response to a logic low voltage level appearing at input  13 , transistor  34  is off and bias voltage V BIAS  is determined as a voltage divider relationship between resistors  36 - 40  and voltage sources V SS  and V DD  or voltage sources V SS  and V REF  and has a voltage level V BIAS1 . In response to a logic high voltage level appearing at input  13 , transistor  34  is on and bias voltage V BIAS  is determined from a voltage divider relationship between resistors  38  and  40 , the parallel combination of the on-resistance of transistor  34  and resistor  36  and voltage sources V SS  and V DD  or voltage sources V SS  and V REF  and has a voltage level V BIAS2 , where voltage V BIAS1  is greater than voltage V BIAS2 . 
     Because operational amplifier  24  is configured as a voltage follower, the voltage appearing at noninverting input  28  appears at inverting input  30  and therefore at I/O node  22 . In accordance with embodiments in which voltage V SS  is at ground potential, voltage V BIAS  appears across resistor  44  and a current I SET  flows through resistor  44 . Thus, in response to voltage V BIAS  appearing at noninverting input  28  being at voltage level V BIAS1 , a set current I SET  having a value or current level of I SET1  flows through set resistor  44  and in response to voltage V BIAS  appearing at noninverting input  28  being at voltage level V BIAS2 , set current I SET  flows through set resistor  44 , where current I SET  has a value or current level of I SET2 . It should be noted that currents I SET1  and I SET2  are greater than bypass current I BYPASS . Kirchoff&#39;s Current Law provides that the sum of the currents entering a node equals the sum of the currents leaving that node. To comply with Kirchoff&#39;s Current Law, the sum the currents at I/O node  20  is substantially equal to zero. Bypass current, I BYPASS , and the current flowing through LED  42 , i.e., current I LED , flows into I/O node  20 . The current flowing out of I/O node  20  is substantially equal to the source-to-drain current of field effect transistor  26 . Because the source-to-drain current flows into node  22 , the current flowing out of I/O node  20  is equal to set current I SET . Thus, set current I SET  substantially equals the sum of bypass current I BYPASS  and LED current I LED . 
     As discussed above, set current I SET  may have a value or current level I SET1  or a value or current level I SET2  where both current levels I SET1  and I SET2  are greater than the current level of bypass current I BYPASS . In accordance with embodiments in which set current I SET  is at a current level I SET1 , the current I SET  is much larger than current I BYPASS , thus LED current I LED  is sufficiently large, as set forth by Kirchoff&#39;s Current Law, to cause LED  42  to emit light having a high intensity. In accordance with embodiments in which set current I SET  is at a current level I SET2 , current I SET  is minimally larger than current I BYPASS , and, in accordance with Kirchoff&#39;s Current Law, LED current I LED  flows through LED  42  and is injected into I/O node  20 . Although current I LED  flows and causes LED  42  to emit light, the intensity of the light emitted by LED  42  is much less than that emitted when operating in the high light emission state. Accordingly, LED  42  is in a low light emission state. 
     Thus, LED driver circuit  10  is configured to receive a drive signal having a phase in which a non-zero voltage is asserted across the light emitting diode and another phase in which a fixed non-zero current is asserted in the light emitting diode. In response to the assertion of the non-zero current in the light emitting diode set current I SET2  is sunk from I/O node  20  and bypass current I BYPASS  is injected into I/O node  20 . As discussed above, current I SET2  is minimally greater than bypass current I BYPASS  and the difference between currents I SET2  and I BYPASS  substantially equals the non-zero current, i.e., LED current I LED . In response to set current ISET having current level ISET 1 , a large current flows through LED  42  and a non-zero voltage is asserted across LED  42 . 
     Thus, LED driver circuit  10  operates in a constant current conduction mode in which LED current I LED  continuously flows through LED  42 . 
       FIG. 1A  is a circuit schematic of an LED driver circuit  10  that drives a plurality of LEDs  42 A 1 - 42 A n , where n is an integer. 
       FIG. 2  is a circuit schematic of an LED driver circuit  100  in accordance with another embodiment of the present invention. LED driver circuit  100  includes a j-bit Digital-to-Analog (DAC) circuit  102 , a controlled current source  106 , and a calibration stage  108  connected to a voltage follower circuit  16  and a plurality of I/O nodes  18 ,  20 , and  22 . It should be noted that DAC  102  is a j-bit DAC where j is an integer indicating the number of inputs of DAC  102 . By way of example, when j is 4, DAC  102  is a 4-bit DAC having four inputs for receiving a four bit signal. DAC  102 , current source  106 , voltage follower circuit  16 , and calibration stage  108  may be monolithically integrated into a single semiconductor substrate or a single semiconductor material. The current provided to I/O node  20  by current source  116  is identified by reference character I 116 . Calibration stage  108  may be referred to as a compensation stage. In embodiments in which I/O nodes  18 ,  20 , and  22  are connected to or serve as I/O pins of driver circuit  100 , I/O nodes  18 ,  20 , and  22  are referred to as I/O pins. I/O nodes  18 ,  20 , and  22  may also be referred to as I/O terminals. By way of example, voltage follower circuit  16  may be comprised of an operational amplifier  24  coupled to a field effect transistor  26 . More particularly, operational amplifier  24  has a noninverting input  28 , an inverting input  30 , and an output  32  and transistor  26  may be a field effect transistor having a gate, a source, and a drain, where output  32  of operational amplifier  24  is connected to the gate of transistor  26  and inverting input  30  is connected to the source of transistor  26 . Current source  106  has a terminal that may serve as or alternatively may be connected to I/O node  18  and a terminal connected to the drain of field effect transistor  110  to form a node that may serve as or alternatively may be connected to I/O node  20 . The current provided to I/O node  20  by current source  106  is identified by reference character I 106 . Current source  106  is configured such that current I 106  compensates for the difference between current I 116  and current I SET . Field effect transistor  110  has a gate coupled for receiving a source of operating potential V DD , a source connected to the drain of transistor  26 , and a drain connected to I/O node  20 . It should be noted that field effect transistor  110  is an optional element that may be absent from LED driver circuit  100 . Transistor  26  may be configured to have a large drain-to-source voltage in embodiments in which transistor  110  is absent. 
     An output of j-bit DAC  102  is connected to noninverting input  28  of operational amplifier  24  and an input of j-bit DAC  102  is coupled for receiving PWM signals V PWM  at terminal  103 . 
     In accordance with another embodiment of the present invention, calibration circuit  108  may include a controller  113  comprising a digital control circuit  114  having an n-bit output coupled to a control terminal of a controlled current source  116  through an n-bit current DAC  118 , where n is an integer. Thus, digital control circuit  114  converts an input signal into an n-bit output signal. It should be noted that DAC  118  is an n-bit DAC where n is an integer indicating the number of inputs of DAC  118 . By way of example, when n is 6, DAC  118  is a 6-bit DAC having six inputs for receiving a six bit signal. Controlled current source  116  has a terminal commonly connected to controlled current source  106  and to I/O node  20  and a terminal commonly connected to controlled current source  106  and to I/O node  18 . Calibration circuit  108  further includes an operational amplifier  120  and a comparator  130 . Operational amplifier  120  has an inverting input  122 , a non-inverting input  124 , and an output  126 , where inverting input  122  is commonly connected to controlled current source  106 , controlled current source  116 , and to the drain of transistor  110  at I/O node  20 . Comparator  130  has a noninverting input  134 , an inverting input  132 , and an output  136 . Noninverting input  134  is commonly connected to noninverting input  124  of operational amplifier  120  and to voltage source  138 . Inverting input  132  is commonly connected to inverting input  122  of operational amplifier  124 , controlled current source  106 , controlled current source  116 , the drain of transistor  110 , and I/O node  20 . Output  136  of comparator  130  is connected to an input of digital control circuit  114 . Voltage source  138  is connected between non-inverting input  124  of operational amplifier  120  and I/O node  18 . It should be noted that voltage source  138  is also connected between inverting input  134  of comparator  130  and I/O node  18 . 
     In operation, a circuit element  42  is connected between I/O node  18  and I/O node  20 , a set resistor  44  is connected between I/O node  22  and a source of operating potential such as, for example, V SS , and I/O node  18  is coupled for receiving a source of potential V DD . By way of example, circuit element  42  is a light emitting diode having an anode connected to I/O node  18  and a cathode connected to I/O node  20 . As discussed with reference to LED driver circuit  10 , a set current I SET  is sunk from I/O node  20 , which is generated in accordance with Ohm&#39;s Lawby developing a voltage across set resistor  44 . 
     LED driver circuit  100  operates in a calibration phase or in an active phase in accordance with signals V PWM  that appear at input  103 . The calibration phase may be referred to as a compensation phase, a compensation mode, or a calibration mode. The calibration and active phases may be referred to as operating phases. In the calibration phase, input signals V PWM  appearing at input  103  are converted by j-bit DAC  102  into an analog signal having a level indicative of operation in the low light emission state. Similarly, in the active phase input signals Vp PWM  appearing at input  103  are converted by j-bit DAC  102  into an analog signal having a level indicative of operation in the high light emission state. For example, with DAC  102  being a 4-bit DAC, the output of 4-bit DAC  102  for the low light emission state may be 20 millivolts and the output of 4-bit DAC  102  for the high light emission state may be 320 millivolts. It should be noted that in response to the signals at input  103  being in the calibration phase, current I SET  having a current level I SET2  flows through set resistor  44  and in response to the signals at input  103  being in the active phase, current I SET  having a current level I SET1  flows through set resistor  44 . 
     In response to the PWM signals V PWM  indicating operation in the low light emission state, LED driver circuit  100  operates in the calibration phase and in response to the PWM signals indicating operation in the high light emission state LED driver circuit  100  operates in the active phase. LED driver circuit  100  uses calibration circuit  108  to calibrate the voltage appearing at I/O node  20  to compensate for current changes caused by resistor  44 , errors introduced by temperature variation, offset errors associated with operational amplifier  120  or comparator  130 , variations caused by the age of one or more circuit elements, or the like. During the calibration phase, LED driver circuit  100  calibrates current source  116  such that the combination of current source  116  and current source  106  sources currents that maintain the voltage at I/O node  20  (and thus the voltage at inverting input  122  of operational amplifier  120  and at inverting input  132  of comparator  130 ) at a level that is substantially equal to one volt less than voltage V DD , i.e., (V DD −1) volts. 
     More particularly, in response to signal V PWM  at input  103  corresponding to the calibration phase, current source  116  is adjusted to compensate for the current I sErz  that flows through set resistor  44  such that the voltage at I/O node  22  is (V DD −1) volts. The value of current I SET2  is substantially equal to the voltage at input  28  of voltage follower circuit  16  (plus or minus any offset voltage) minus voltage V SS  divided by the resistance value of set resistor  44 . For example, the voltage at input  28  may be 20 millivolts, the offset voltage may be zero, the resistance value of set resistor  44  may be 10 Ohms, and voltage V SS  may be zero. In this example, current I SET  has a value of I SET2  which is substantially equal to 2 milliamps. Comparator  130  is used to determine if the voltage at I/O node  20  is below or above the voltage equal to the difference between voltage V DD  and 1 volt, i.e., (V D1 −1) volts. If the voltage at I/O node  20  is greater than (V DD −1) volts, then the sum of current I 116  and current I 106  has a value that is greater than current level I SET2 . Thus, the voltage signal at the output of comparator  130  is at a logic low voltage. Control circuit  113  generates an “n” bit signal that decrements the signal of n-bit current DAC  118  by one LSB current unit, i.e., the level of current I 116  is decremented by the amount of current associated with the least significant bit. If the voltage at I/O node  20  is less than (V DD −1) volts, then the sum of current I 116  and current I 106  has a value that is less than current level I SET2 . Thus, the voltage signal at the output of comparator  130  is at a logic high voltage level. Control circuit  113  generates an “n” bit signal that increments the signal of n-bit current DAC  118  by one LSB current unit, i.e., the level of current I 116  is incremented by the amount of current associated with the least significant bit. Because current DAC  118  is an n-bit current DAC, there is granularity in its output current signal which inhibits setting current I 116  to be exactly equal to current I SET . By way of example, a current equal to one least significant bit may be 60 microamperes. Thus, decreasing current I 116  by one least significant bit decreases current I 116  by 60 microamperes and increasing current I 116  by one least significant bit increases current I 116  by 60 microamperes. Preferably, this determination is made in response to each calibration phase. Thus, during each calibration phase the code for n-bit current DAC  118  will increase or decrease successively until the sum of currents I 116  and I 106  approximately equals the current I SET2  and the voltage imposed on LED  42  is one volt. As discussed above, this calibration compensates for offset of the amplifier, mismatches of circuit elements, and current variations over temperature. 
     In response to signal V PWM  at input  103  corresponding to the active phase, current I SET  has a value of I SET1  and the current I LED  that flows through LED  42  is substantially equal to current I SET1  minus current I 116  minus the current equal to one least significant bit, i.e., I LED =I SET1 −I 116 −I 106 . If current I 116  is approximately equal to current level I SET2 , i.e., the current level of current I SET  corresponding to the calibration phase, then current I LED  is approximately equal to current level I SET1 −I 116  with a maximum error equivalent to twice the amount corresponding to the least significant bit. It should be noted that current source  116  provides a coarse current adjustment and operational amplifier  120  and current source  106  cooperate to provide a fine current adjustment so that the voltage at noninverting inputs  124  and  134  is one volt below the voltage at I/O node  18 . This pulls the voltage at inverting inputs  122  and  132 , hence the voltage at I/O node  20  and the cathode of LED  42 , closer to one volt lower than the voltage at I/O node  18 . It should be further understood that up to one least significant bit (ILSB) of current can be derived from operational amplifier  120  and current source  106  and the rest of the current is derived from current source  116 , where current source  116  provides a discrete value and operational amplifier  120  and current source  106  cooperate to provide a continuum of current values. Thus, operational amplifier  120  and current source  106  cooperate to compensate for a difference between current level I SET1  and current I 116  within a window of plus or minus one least significant bit. In the active phase, current I 106  from current source  106  may change by one LSB because the voltage at inverting input  122  is changing. For example, the voltage at input  28  may be 320 millivolts, the offset voltage may be zero, the resistance value of set resistor  44  may be 10 Ohms, and voltage V SS  may be zero. The maximum change in current introduced by the combination of operational amplifier  120  and current source  106  is plus or minus the current value of one least significant bit. In this example, current I SET  has a value of I SET1  which is substantially equal to 32 milliamps and the current value of one least significant bit is 60 μA. Thus, current I LED  is substantially equal to 32 mA-2 mA-120 μA which is approximately equal to 30 mA, which causes LED  42  to emit light at a high intensity. It should be appreciated that the current change introduced by operational amplifier  120  and current source  106  may be less than the current associated with plus or minus one least significant bit, i.e., it can 0 μA, 60 μA, or −60 μA. 
     As discussed with reference to LED driver circuit  10 , set current I SET  may have a value or current level I SET1  or a value or current level I SET2  where both levels I SET1  and I SET2  are greater than the level of the sum of current I 106  from current source  106  and current I 116  from current source  116 . In accordance with embodiments in which set current I SET  is at a current level I SET1 , the current I SET  is much larger than the sum of current I 106  and current I 116 , thus, from Kirchofrs Current Law, an LED current I LED  flows through LED  42  causing it to emit light. LED  42  operating under this condition is said to be operating in a high light emission state. In accordance with embodiments in which set current I SET  is at a current level I SET2 , current I SET  is minimally larger than the sum of currents I 106  and I 116 , and in accordance with Kirchoff&#39;s Current Law, LED current I LED  flows through LED  42  into I/O node  20  such that LED  42  emits light. Thus, LED  42  emits light during the high light emission state and during the low light emission state. The highest intensity of the light emission by LED  42  occurs during the on portion of the current period of LED  42 , i.e., when current I SET  is at current level I SET1 . Because the intensity of the light emitted by LED  42  is much smaller during the off portion of the current period, i.e., when current I SET  is at current level I SET2 , or during the low light emission state, the contribution of light during the off portion to the average value of the light emission during a period of the LED is small and substantially unaffected by the current level during the low light emission state. 
     Because the voltage drop across LED  42  is clamped to no less than one volt, LED driver circuit  100  operates in a constant current conduction mode in which LED current I LED  continuously flows through LED  42 . 
       FIG. 2A  is a circuit schematic of an LED driver circuit  100  that drives a plurality of LEDs  42 A 1 - 42 A n , where n is an integer. 
       FIG. 2B  is a circuit schematic of an LED driver circuit that drives an LED  42 A wherein current source  116  shown in  FIG. 2  has been replaced by a transistor  116 A having a control electrode connected to current D/A converter  118 , a current carrying electrode connected to input/output node  18 , and a current carrying electrode connected to input/output node  20 . 
       FIG. 3  is a circuit schematic of an LED driver circuit  100 A in accordance with another embodiment of the present invention. Like LED driver circuit  100 , LED driver circuit  100 A includes j-bit DAC  102 , voltage follower circuit  16 , field effect transistor  110 , controller  113 , comparator  130 , voltage source  138 , and current source  116 . Operational amplifier  120  and controlled current source  106  are replaced by an operational transconductance amplifier  120 A, which has an inverting input  122 A, a noninverting input  124 A, and an output  126 A. Thus, the reference character “A” has been appended to reference character “ 108 ” to identify the calibration stage. It should be understood that j-bit DAC  102 , voltage follower circuit  16 , transistor  110 , and calibration stage  108 A may be monolithically integrated into a single semiconductor substrate or a single semiconductor material. Noninverting input  134  of comparator  130  and noninverting input  124 A of operational transconductance amplifier  120 A are commonly connected together and to voltage source  138 , inverting input  132  of comparator  130  and inverting input  122 A of operational transconductance amplifier  120 A are commonly connected together and to output  126 A, I/O node  20 , the drain terminal of field effect transistor  110 , and to a terminal of current source  116 . 
     In response to the signal at input  103  being in the calibration phase, current I SET  having a current level I SET2  flows through set resistor  44  and in response to the signal at input  103  being in the active phase, current I SET  having a current level I SET1  flows through set resistor  44 . The current provided to I/O node  20  by operational transconductance amplifier  120 A is identified by reference character I 120 A. 
     In operation, a circuit element  42  is connected between I/O node  18  and I/O node  20 , a set resistor  44  is connected between I/O node  22  and a source of operating potential such as, for example, V SS , and I/O node  18  is coupled for receiving a source of potential V DD . By way of example, circuit element  42  is a light emitting diode having an anode connected to I/O node  18  and a cathode connected to I/O node  20 . As discussed with reference to LED driver circuit  10 , a set current I SET  is sunk from I/O node  20 , which is generated in accordance with Ohm&#39;s Law by developing a voltage across set resistor  44 . 
     Like LED driver circuit  100 , LED driver circuit  100 A operates in a calibration phase or in an active phase in accordance with signals V PWM  that appear at input  103 . The calibration phase may be referred to as a compensation phase, a compensation mode, or a calibration mode. In the calibration phase, input signals V PWM  appearing at input  103  are converted by j-bit DAC  102  into an analog signal having a level indicative of operation in the low light emission state. Similarly, in the active phase input signals V PWM  appearing at input  103  are converted by j-bit DAC  102  into an analog signal having a level indicative of operation in the high tight emission state. For example, with DAC  102  being a 4-bit DAC, the output of 4-bit DAC  102  for the low light emission state may be 20 millivolts and the output of 4-bit DAC  102  for the high light emission state may be 320 millivolts. It should be noted that in response to the signals at input  103  being in the calibration phase, current I SET  having a current level I SET2  flows through set resistor  44  and in response to the signals at input  103  being in the active phase, current I SET  having a current level I SET1  flows through set resistor  44 . 
     In response to the PWM signals V PWM  indicating operation in the low light emission state, LED driver circuit  100 A operates in the calibration phase and in response to the PWM signals indicating operation in the high light emission state LED driver circuit  100 A operates in the active phase. LED driver circuit  100 A uses calibration circuit  108 A to calibrate the voltage appearing at I/O node  20  to compensate for current changes caused by resistor  44 , errors introduced by temperature variation, offset errors associated with operational amplifier  120  or comparator  130 , variations caused by the age of one or more circuit elements, or the like. During the calibration phase, LED driver circuit  100 A calibrates current source  116  such that the combination of current source  116  and operational transconductance amplifier  120 A sources currents that maintain the voltage at I/O node  20  (and thus the voltage at inverting input  122  of operational transconductance amplifier  120 A and at inventing input  132  of comparator  130 ) at a level that is substantially equal to one volt less than voltage V DD , i.e., (V DD −1) volts. 
     More particularly, in response to signal V PWM  at input  103  corresponding to the calibration phase, current source  116  is adjusted to compensate for the current I SET2  that flows through set resistor  44  such that the voltage at I/O node  22  is (V DD −1) volts. The value of current I SET2  is substantially equal to the voltage at input  28  of voltage follower circuit  16  (plus or minus any offset voltage) minus voltage V SS  divided by the resistance value of set resistor  44 . For example, the voltage at input  28  may be 20 millivolts, the offset voltage may be zero, the resistance value of set resistor  44  may be 10 Ohms, and voltage V SS  may be zero. In this example, current I SET  has a value of I SET2  which is substantially equal to 2 milliamps. Comparator  130  is used to determine if the voltage at I/O node  20  is below or above the voltage equal to the difference between voltage V DD  and 1 volt, i.e., (V DD −1) volts. If the voltage at I/O node  20  is greater than (V DD −1) volts, then the sum of current I 116  and current I 120 A has a value that is greater than current level I SET2 . Thus, the voltage signal at the output of comparator  130  is at a logic low voltage. Control circuit  113  generates an “n” bit signal that decrements the signal of n-bit current DAC  118  by one LSB current unit, i.e., the level of current I 116  is decremented by the amount of current associated with the least significant bit. If the voltage at I/O node  20  is less than (V DD −1) volts, then the sum of current I 116  and current I 120 A has a value that is less than current level I SET2 . Thus, the voltage signal at the output of comparator  130  is at a logic high voltage level. Control circuit  113  generates an “n” bit signal that increments the signal of n-bit current DAC  118  by one LSB current unit, i.e., the level of current I 116  is incremented by the amount of current associated with the least significant bit. Because current DAC  118  is an n-bit current DAC, there is granularity in its output current signal which inhibits setting current I 116  to be exactly equal to current I SET . By way of example, a current equal to one least significant bit may be 60 microamperes. Thus, decreasing current I 116  by one least significant bit decreases the current by 60 microamperes and increasing current I 116  by one least significant bit increases current I 116  by 60 microamperes. Preferably, this determination is made in response to each calibration phase. Thus, during each calibration phase the code for n-bit current DAC  118  will increase or decrease successively until the sum of currents I 116  and I 120A  approximately equals the current I SET2  and the voltage imposed on LED  42  is one volt. As discussed above, this calibration compensates for offset of the amplifier, mismatches of circuit elements, and current variations over temperature. 
     In response to PWM signals V PWM  at input  103  corresponding to the active phase, current I SET  has a value of I SET1  and the current I LED  that flows through LED  42  is substantially equal to current I SET1  minus current I 116  minus the current equal to one least significant bit, i.e., I LED =I SET1 −I 116 −I 120A . If current I 116  is approximately equal to current level I SET2 , i.e., the current level of current I SET  corresponding to the calibration phase, then current I LED  is approximately equal to current level I SET1 −I 116  with a maximum error equivalent to twice the amount corresponding to the least significant bit. It should be noted that current source  116  provides a coarse current adjustment and operational transconductance amplifier  120 A provides a fine current adjustment so that the voltage at noninverting inputs  124 A and  134  is one volt below the voltage at I/O node  18 . This pulls the voltage at inverting inputs  122 A and  132 , hence the voltage at I/O node  20  and the cathode of LED  42 , closer to one volt lower than the voltage at I/O node  18 . It should be further understood that up to one least significant bit (1LSB) of current can be derived from operational transconductance amplifier  120 A and the rest of the current is derived from current source  116 , where current source  116  provides a discrete value and operational transconductance amplifier  120 A provides a continuum of current values. Thus, operational transconductance amplifier  120 A compensates for a difference between current level I SET1  and current I 116  within a window of plus or minus one least significant bit. In the active phase, current I 120A  from operational transconductance amplifier  120 A may change by one LSB because the voltage at inverting input  122 A is changing. For example, the voltage at input  28  may be 320 millivolts, the offset voltage may be zero, the resistance value of set resistor  44  may be 10 Ohms, and voltage V SS  may be zero. The maximum change in current introduced by operational transconductance amplifier  120 A is plus or minus the current value of one least significant bit. In this example, current I SET  has a value of I SET1  which is substantially equal to 32 milliamps and the current value of one least significant bit is 60 μA. Thus, current I LED  is substantially equal to 32 mA−2 mA−120 μA which is approximately equal to 30 mA, which causes LED  42  to emit light at a high intensity. It should be appreciated that the current change introduced by operational transconductance amplifier  120 A may be less than the current associated with plus or minus one least significant bit, i.e., it can 0 μA, 60 μA, or −60 μA. 
     As discussed with reference to LED driver circuit  10 , set current I SET  may have a value or current level I SET1  or a value or current level I SET2  where both levels I SET1  and I SET2  are greater than the level of the sum of current I 120 A from operational transconductance amplifier  120 A and current I 116  from current source  116 . In accordance with embodiments in which set current I SET  is at a current level I SET1 , current I SET  is much larger than the sum of current I 120 A and current I 116 , thus, from Kirchoff&#39;s Current Law, an LED current I LED  flows through LED  42  causing it to emit light. LED  42  operating under this condition is said to be operating in a high light emission state. In accordance with embodiments in which set current I SET  is at a current level I SET2 , current I SET  is minimally larger than the sum of currents I 120 A and I 116 , and in accordance with Kirchoff&#39;s Current Law, LED current I LED  flows through LED  42  into I/O node  20  such that LED  42  emits light. Thus, LED  42  emits light during the high light emission state and during the low light emission state. The highest intensity of the light emission by LED  42  occurs during the on portion of the current period of LED  42 , i.e., when current I SET  is at current level I SET1 . Because the intensity of the light emitted by LED  42  is much smaller during the off portion of the current period, i.e., when current I SET  is at current level I SET2 , or during the low light emission state, the contribution of light during the off portion to the average value of the light emission during a period of the LED is small and substantially unaffected by the current level during the low light emission state. 
     Because the voltage drop across LED  42  is clamped to no less than one volt, LED driver circuit  100 A operates in a constant current conduction mode in which LED current I LED  continuously flows through LED  42 . 
       FIG. 3A  is a circuit schematic of an LED driver circuit  100  that drives a plurality of LEDs  42 A 1 - 42 A n , where n is an integer. 
       FIG. 4  is a circuit schematic of an LED driver circuit  150  in accordance with another embodiment of the present invention. It should be noted that LED driver circuit  150  may be monolithically integrated into a single semiconductor substrate or a single semiconductor material. LED driver circuit  150  includes a variable voltage source  152  and a field effect transistor  154  connected to a voltage follower circuit  16  and a plurality of I/O nodes  18 ,  20 , and  22 . In embodiments in which I/O nodes  18 ,  20 , and  22  are connected to or serve as I/O pins of driver circuit  150 , I/O nodes  18 ,  20 , and  22  are referred to as I/O pins. By way of example, voltage follower circuit  16  may be comprised of an operational amplifier  24  coupled to a field effect transistor  26 . More particularly, operational amplifier  24  has a noninverting input  28 , an inverting input  30 , and an output  32  and transistor  26  may be a field effect transistor having a gate, a source, and a drain, where output  32  of operational amplifier  24  is connected to the gate of transistor  26  and inverting input  30  is connected to the source of transistor  26 . Transistor  154  has a gate coupled for receiving a gate drive signal V G154 , a drain that may serve as or alternatively may be connected to I/O node  18  and a source connected to the drain of field effect transistor  26  to form a node that may serve as or alternatively may be connected to I/O node  20 . 
     In operation, a circuit element  42  is coupled between I/O node  18  and I/O node  20  and a set resistor  44  may be connected between I/O node  22  and a source of operating potential such as, for example, V SS . By way of example, circuit element  42  is a light emitting diode having its anode connected to I/O node  18  and its cathode connected to I/O node  20 . A current equal to the sum of currents I 154  and I LED  flows into I/O node  20  and a current substantially equal to the drain-to-source current of field effect transistor  26  flows from node  20  into node  22 . Thus, the current flowing out of or sunk from I/O node  20 , i.e., the drain-to-source current of field effect transistor  26 , is substantially equal to a set current I SET . Set current I SET  is generated in accordance with Ohm&#39;s Law by developing a voltage&#39;across set resistor  44 . More particularly, set current I SET  is generated in accordance with a voltage signal V BIAS  appearing at noninverting input  28  of operational amplifier  24 . Variable voltage source  152  places voltage V BIAS  having a voltage level V BIAS1  or V BIAS2  at inverting input  28  of operational amplifier  24 , where voltage V BIAS1  is greater than voltage V BIAS2 . 
     In a high light emission state, a gate drive voltage V G154  that turns off transistor  154  is applied to the gate of transistor  154  and a bias voltage V BIAS1  is applied to noninverting input terminal  28 . By way of example voltage V BIAS1  is 320 millivolts. Because operational amplifier  24  is configured as a voltage follower, the voltage appearing at noninverting input  28  appears at inverting input  30  and therefore at I/O node  22 . In accordance with embodiments in which voltage V SS  is at ground potential, voltage V BIAS1  appears across resistor  44  and a current I SET1  flows through resistor  44 . For example, in response to bias voltage V BIAS1  being 320 millivolts, voltage V SS  being ground, and the resistance value of resistor  44  being 10Ω, current I SET1 , the drain-to-source current of transistor  26  is 32 milliamps. As discussed above, Kirchoff&#39;s Current Law provides that the sum of the currents entering a node equals the sum of the currents leaving that node. To comply with Kirchoff&#39;s Current Law, the sum of the currents at I/O node  20  is substantially equal to zero. A current equal to the sum of currents I 154  and I LED  flows into I/O node  20  and a current substantially equal to the drain-to-source current of field effect transistor  26  flows from node  20  into node  22 . Because the drain-to-source current of transistor  26  is substantially equal to set current I SET , and current I 154  is substantially equal to zero, the LED current I LED  equals current I SET , which is 32 milliamps for the example above. It should be noted that current I 154  is the drain-to-source current of transistor  154 . Thus, LED  42  emits light in a high light emission state. 
     In a low light emission state, a gate drive voltage V G154  that turns on transistor  154  is applied to the gate of transistor  154  and a bias voltage V BIAS2  is applied to noninverting input terminal  28 . By way of example voltage V BIAS2  is 20 millivolts. Because operational amplifier  24  is configured as a voltage follower, the voltage appearing at noninverting input  28  appears at inverting input  30  and therefore at I/O node  22 . In accordance with embodiments in which voltage V SS  is at ground potential, voltage V BIAS2  appears across resistor  44  and a current I SET2  flows through resistor  44 . For example, in response to bias voltage V BIAS2  being 20 millivolts, voltage V SS  being ground, and the resistance value of resistor  44  being 10Ω, current I SET2 , hence the drain-to-source current of transistor  26 , is 2 milliamps. As discussed above, Kirchoff&#39;s Current Law provides that the sum of the currents entering a node equals the sum of the currents leaving that node. To comply with Kirchoff&#39;s Current Law, the sum of the currents at I/O node  20  is substantially equal to zero. A current equal to the sum of currents I 154  and I LED  flows into I/O node  20  and a current substantially equal to the drain-to-source current of field effect transistor  26  flows from node  20  into node  22 . Because the drain-to-source current of transistor  26  is substantially equal to set current I SET , and current I 154  is substantially equal to the drain-to-source current of transistor  26 , the LED current I LED  is substantially equal to zero for the example above. Thus, LED  42  is in a nonconductive state and does not emit light. 
       FIG. 4A  is a circuit schematic of an LED driver circuit  150  that drives a plurality of LEDs  42 A 1 - 42 A n , where n is an integer. 
       FIG. 5  is a circuit schematic of an LED driver circuit  200  in accordance with another embodiment of the present invention. It should be noted that LED driver circuit  200  may be monolithically integrated into a single semiconductor substrate or a single semiconductor material. LED driver circuit  200  includes a variable voltage source  152  and a field effect transistor  154  connected to a voltage follower circuit  202  and a plurality of I/O nodes  18 ,  20 , and  22 . In accordance with embodiments in which I/O nodes  18 ,  20 , and  22  are connected to or serve as I/O pins of driver circuit  200 , I/O nodes  18 ,  20 , and  22  are referred to as I/O pins. By way of example, voltage follower circuit  202  may be comprised of an operational amplifier  24  coupled to a field effect transistor  26  through a Single Pole Double Throw (SPDT) switch  204 . As described with reference to  FIG. 1 , operational amplifier  24  has a noninverting input  28 , an inverting input  30 , and an output  32  and transistor  26  may be a field effect transistor having a gate, a source, and a drain. Switch  204  has conduction terminals  206 ,  208 , and  210  and a control terminal  212 . Output  32  of operational amplifier  24  is connected to terminal  206 , terminal  208  is connected to the gate of transistor  26 , terminal  210  is coupled for receiving a source of operating potential such as, for example, V SS , and control terminal  212  is coupled for receiving a switching or control signal V CTRL . 
     Transistor  154  has a gate coupled for receiving a gate signal V G154 , a drain that may serve as or alternatively may be connected to I/O node  18  and a source connected to the drain of field effect transistor  26  to form a node that may serve as or alternatively may be connected to I/O node  20 . 
     LED driver  200  further includes an SPDT switch  214  and a current source  216  coupled between I/O node  20  and source of operating potential V SS . Switch  214  has conduction terminals  218 ,  220 , and  222  and a control terminal  224 . Terminal  218  is connected to I/O node  20 , terminal  220  is connected to a conduction terminal of current source  216 , terminal  222  is coupled for receiving source of operating potential V SS , and control terminal  224  is coupled for receiving control signal V CTRL . 
     In operation, a circuit element  42  is coupled between I/O node  18  and I/OS node  20  and a set resistor  44  may be connected between I/O node  22  and a source of operating potential such as, for example, V SS . By way of example, circuit element  42  is a light emitting diode having its anode connected to I/O node  18  and its cathode connected to I/O node  20 . SPDT switches  204  and  214  are configured so that LED driver circuit  200  operates in the high light emission state or the low light emission state. 
     In the high light emission state, voltage V G154  at the gate of transistor  154  is set so that switching transistor  154  is off and not conducting current and switching signal V CTRL  configures switch  204  so that output  32  of operational amplifier  24  is connected to the gate of field effect transistor  26 . In addition, switching signal V CTRL  configures switch  214  so that both terminals of current source  216  are coupled to the same potential, V SS , and substantially no current flows along a current path from I/O node  20  through switch  214  and current source  216 . Switch  214  is shown in this position in  FIG. 5 . Connecting output terminal  32  to the gate of field effect transistor  26  configures operational amplifier  24  as a voltage follower. Because operational amplifier  24  is configured as a voltage follower, the voltage appearing at noninverting input  28  appears at inverting input  30  and therefore at I/O node  22 . In accordance with embodiments in which voltage V SS  is at ground potential, voltage V 152  from voltage source  152  appears across resistor  44  and a current I SET  flows through resistor  44 . Thus, in response to voltage V BIAS  appearing at noninverting input  28 , a set current I SET  flows through set resistor  44 . As discussed above, Kirchoff&#39;s Current Law provides that the sum of the currents entering a node equals the sum of the currents leaving that node. To comply with Kirchoff&#39;s Current Law, the sum of the currents at I/O node  20  is substantially equal to zero. Because switching transistor  154  is off, LED current I LED  is equal to set current I SET , which is sufficiently high to cause LED  42  to emit light at a high intensity. 
     In the low light emission state, voltage V G154  at the gate of transistor  154  is set so that switching transistor  154  is on and conducting current I 154  and switching signal V CTRL  configures switches  204  and  214  so that the gate of transistor  26  is grounded and I/O node  20  is coupled to source of operating potential V SS  through current source  216 . Because the gate of field effect transistor  26  is grounded, transistor  26  is nonconductive. As discussed above, Kirchoff&#39;s Current Law provides that the sum of the currents entering a node equals the sum of the currents leaving that node. To comply with Kirchoff&#39;s Current Law, the sum of the currents at I/O node  20  is substantially equal to zero. Transistor  154  conducts a current I 154  substantially equal to the current of current source  216 . Thus, current I LED  of LED  42  is substantially equal to zero and LED  42  does not emit light. 
       FIG. 5A  is a circuit schematic of an LED driver circuit  200  that drives a plurality of LEDs  42 A 1 - 42 A n , where n is an integer. 
       FIG. 6  is a circuit schematic of a lighting system  300  in accordance with another embodiment of the present invention. What is shown in  FIG. 6  is light intensity control network  302  having a plurality of outputs that send Pulse Width Modulation (PWM) signals to corresponding LED driver circuits. It should be noted that the LED driver circuit may be LED driver circuit  10 , LED driver circuit  100 , LED driver circuit  100 A, LED driver circuit  150 , or LED driver circuit  200 . By way of example, the LED driver circuit is LED driver circuit  100 A and light intensity control network  302  is configured to provide control signals for a plurality of LED driver circuits  100 A. To distinguish between the LED driver circuits a subscripted reference character  1 , . . . , q has been appended to reference character  100 A. Accordingly, LED driver circuits  100 A are identified as LED driver circuits  100 A 1 ,  100 A 2 , . . . ,  100 A q , where q is an integer greater than or equal to 1. It should be noted that when q is one, there is a single LED driver circuit  100 A 1 , when q is two there are two LED driver circuits  100 A, and  100 A 2 , etc. Similarly, reference characters  1 , . . . , q have been appended to the I/O terminals of LED driver circuit  100 A to distinguish them from the other LED driver circuits. Thus, LED driver circuit  100 A, has I/O nodes  18   1 ,  20   1 , and  22   1 , LED driver circuit  100 A 2  has I/O nodes  18   2 ,  20   2 , and  22   2 , and LED driver circuit  100 A q  has I/O nodes  18   q ,  20   q , and  22   q . 
     Each LED driver circuit  100 A 1 , . . . ,  100 A q  is connected to intensity control network  302  by one or more signal lines. Reference character m indicates that intensity control network  302  is coupled to LED driver circuit  100 A 1  by m signal lines, where m is an integer greater than or equal. To one, intensity control network  302  is coupled to LED driver circuit  100 A 2  by k signal lines, where k is an integer greater than or equal to one, intensity control network  302  is coupled to LED driver circuit  100 A q  by p signal lines, where p is an integer greater than or equal to one. It should be noted that m, k, and p may be equal to each other or they may be different from each other. 
     An LED  42   1  is coupled between I/O nodes  18   1  and  20   1 , an LED  42   2  is coupled between I/O nodes  18   2  and  20   2 , an LED  42   q  is coupled between I/O nodes  18   q  and  20   q , a resistor  44   1  is connected between I/O node  22 , and source of operating potential V SS , a resistor  44   2  is connected between I/O node  22   2  and source of operating potential V SS , and a resistor  44   q  is connected between I/O node  22   q  and source of operating potential V SS . 
     In operation, light intensity control network  302  transmits control signals to LED driver circuits  100 A 1 ,  100 A 2 , . . . ,  100 A q . In response to the control signals from light intensity control circuit  302 , LED driver circuits  100 A 1 ,  100 A 2 , . . . ,  100 A q  stimulate corresponding LEDs  42   1 ,  42   2 , . . . ,  42   9  to emit light. In accordance with an embodiment in which q equals three (q=3), LED  42  may be a red LED, LED  42   2  may be a green LED, and LED  42   3  may be a blue LED. The operation of eachLED driver circuit  100 A 1 ,  100 A 2 , . . .  100 A q  has been described with reference to  FIG. 3 . As noted above, lighting system  300  may be comprised of LED driver circuits  10 ,  150 , or  200  rather than LED driver circuit  100 A. Thus, lighting system  300  may be comprised of intensity control network  302  coupled to  10   1 ,  10   2 , . . . ,  10   q ; lighting system  300  may be comprised of intensity control network  302  coupled to  150   1 ,  150   2 , . . . ,  150   q ; and lighting system  300  may be comprised of intensity control network  302  coupled to LED driver circuits  200   1 ,  200   2 , . . . ,  200   q . 
     Although certain preferred embodiments and methods have been disclosed herein, it will be apparent from the foregoing disclosure to those skilled in the art that variations and modifications of such embodiments and methods may be made without departing from the scope of the invention. It is intended that the invention shall be limited only to the extent required by the appended claims and the rules and principles of applicable law.