Patent Publication Number: US-9842860-B2

Title: Semiconductor device

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is a continuation of U.S. application Ser. No. 14/190,200, filed Feb. 26, 2014, now allowed, which claims the benefit of a foreign priority application filed in Japan as Serial No. 2013-038087 on Feb. 28, 2013, both of which are incorporated by reference. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to an object, a method, or a manufacturing method. In addition, the present invention relates to a process, a machine, manufacture, or a composition of matter. In particular, the present invention relates to, for example, a semiconductor device, a display device, a light-emitting device, a power storage device, a driving method thereof, or a manufacturing method thereof. The present invention particularly relates to a semiconductor device, a display device, or a light-emitting device each including an oxide semiconductor, for example. 
     2. Description of the Related Art 
     Patent Document 1 discloses a logic circuit that maintains data even during instantaneous power reduction or interruption. 
     REFERENCE 
     Patent Document 1: Japanese Published Patent Application No. 2006-050208 
     SUMMARY OF THE INVENTION 
     An object of one embodiment of the present invention is to provide a semiconductor device including a circuit different from that in Patent Document 1. Another object of one embodiment of the present invention is to provide a high-quality semiconductor device or the like. 
     An object of one embodiment of the present invention is to provide a semiconductor device or the like with low off-state current. Another object of one embodiment of the present invention is to provide a semiconductor device or the like with low power consumption. Another object of one embodiment of the present invention is to provide an eye-friendly display device or the like. Another object of one embodiment of the present invention is to provide a semiconductor device or the like including a transparent semiconductor layer. Another object of one embodiment of the present invention is to provide a semiconductor device or the like including a semiconductor layer with high reliability. 
     Note that the description of these objects does not disturb the existence of other objects. In one embodiment of the present invention, there is no need to achieve all the objects. Other objects will be apparent from and can be derived from the description of the specification, the drawings, the claims, and the like. 
     One embodiment of the present invention is a semiconductor device including a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor. The first transistor and the fourth transistor are p-channel transistors. The second transistor and the fifth transistor are n-channel transistors. The third transistor includes an oxide semiconductor layer including a region where a channel is formed (hereinafter referred to as channel formation region). The sixth transistor includes an oxide semiconductor layer including a channel formation region. A gate of the first transistor is electrically connected to one of a source and a drain of the third transistor. A high voltage is applied to one of a source and a drain of the first transistor. A low voltage is applied to one of a source and a drain of the second transistor. The other of the source and the drain of the first transistor is electrically connected to the other of the source and the drain of the second transistor, a gate of the fourth transistor, and one of a source and a drain of the sixth transistor. A gate of the second transistor is electrically connected to the other of the source and the drain of the third transistor. The high voltage is applied to one of a source and a drain of the fourth transistor. The low voltage is applied to one of a source and a drain of the fifth transistor. The other of the source and the drain of the fourth transistor is electrically connected to the other of the source and the drain of the fifth transistor, the gate of the first transistor, and one of the source and the drain of the third transistor. A gate of the fifth transistor is electrically connected to the other of the source and the drain of the sixth transistor. 
     In the semiconductor device of one embodiment of the present invention, the channel formation region of each of the third and sixth transistors is included in the oxide semiconductor layer. Thus, even if the high voltage and the low voltage are temporarily interrupted, a voltage of a node electrically connected to the other of the source and the drain of the first transistor and the other of the source and the drain of the second transistor can be recovered when the high voltage and the low voltage are recovered. Moreover, a voltage of a node electrically connected to the other of the source and the drain of the fourth transistor and the other of the source and the drain of the fifth transistor can be recovered. 
     One embodiment of the present invention is a semiconductor device including a first resistor, a second resistor, a first transistor, a second transistor, a third resistor, and a fourth transistor. The first transistor and the third transistor are n-channel transistors. The second transistor includes an oxide semiconductor layer including a channel formation region. The fourth transistor includes an oxide semiconductor layer including a channel formation region. A high voltage is applied to one terminal of the first resistor. A low voltage is applied to one of a source and a drain of the first transistor. The other terminal of the first resistor is electrically connected to the other of the source and the drain of the first transistor and one of a source and a drain of the fourth transistor. The high voltage is applied to one terminal of the second resistor. The low voltage is applied to one of a source and a drain of the third transistor. The other terminal of the second resistor is electrically connected to the other of the source and the drain of the third transistor and one of a source and a drain of the second transistor. A gate of the first transistor is electrically connected to the other of the source and the drain of the second transistor. A gate of the third transistor is electrically connected to the other of the source and the drain of the fourth transistor. 
     In the semiconductor device of one embodiment of the present invention, the channel formation region of each of the second and fourth transistors is included in the oxide semiconductor layer. Thus, even if the high voltage and the low voltage are temporarily interrupted, a voltage of a node electrically connected to the other terminal of the first resistor and the other of the source and the drain of the first transistor can be recovered when the high voltage and the low voltage are recovered. Moreover, a voltage of a node electrically connected to the other terminal of the second resistor and the other of the source and the drain of the third transistor can be recovered. 
     One embodiment of the present invention is a semiconductor device including a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor. The first transistor and the fourth transistor are p-channel transistors. The second transistor and the fifth transistor are n-channel transistors. The third transistor includes an oxide semiconductor layer including a channel formation region. The sixth transistor includes an oxide semiconductor layer including a channel formation region. A high voltage is applied to one of a source and a drain of the first transistor. A low voltage is applied to one of a source and a drain of the second transistor. The other of the source and the drain of the first transistor is electrically connected to the other of the source and the drain of the second transistor, one of a source and a drain of the sixth transistor, and a gate of the fifth transistor. The high voltage is applied to one of a source and a drain of the fourth transistor. The low voltage is applied to one of a source and a drain of the fifth transistor. The other of the source and the drain of the fourth transistor is electrically connected to the other of the source and the drain of the fifth transistor, a gate of the second transistor, and one of a source and a drain of the third transistor. A gate of the first transistor is electrically connected to the other of the source and the drain of the third transistor. A gate of the fourth transistor is electrically connected to the other of the source and the drain of the sixth transistor. 
     In the semiconductor device of one embodiment of the present invention, the channel formation region of each of the third and sixth transistors is included in the oxide semiconductor layer. Thus, even if the high voltage and the low voltage are temporarily interrupted, a voltage of a node electrically connected to the other of the source and the drain of the first transistor and the other of the source and the drain of the second transistor can be recovered when the high voltage and the low voltage are recovered. Moreover, a voltage of a node electrically connected to the other of the source and the drain of the fourth transistor and the other of the source and the drain of the fifth transistor can be recovered. 
     One embodiment of the present invention is a semiconductor device including a first resistor, a second resistor, a first transistor, a second transistor, a third transistor, and a fourth transistor. The first transistor and the third transistor are p-channel transistors. The second transistor includes an oxide semiconductor layer including a channel formation region. The fourth transistor includes an oxide semiconductor layer including a channel formation region. A high voltage is applied to one of a source and a drain of the first transistor. A low voltage is applied to one terminal of the first resistor. The other of the source and the drain of the first transistor is electrically connected to the other terminal of the first resistor and one of a source and a drain of the fourth transistor. The high voltage is applied to one of a source and a drain of the third transistor. The low voltage is applied to one terminal of the second resistor. The other of the source and the drain of the third transistor is electrically connected to the other terminal of the second resistor and one of a source and a drain of the second transistor. A gate of the first transistor is electrically connected to the other of the source and the drain of the second transistor. A gate of the third transistor is electrically connected to the other of the source and the drain of the fourth transistor. 
     In the semiconductor device of one embodiment of the present invention, the channel formation region of each of the second and fourth transistors is included in the oxide semiconductor layer. Thus, even if the high voltage and the low voltage are temporarily interrupted, a voltage of a node electrically connected to the other terminal of the first resistor and the other of the source and the drain of the first transistor can be recovered when the high voltage and the low voltage are recovered. Moreover, a voltage of a node electrically connected to the other terminal of the second resistor and the other of the source and the drain of the third transistor can be recovered. 
     One embodiment of the present invention is a semiconductor device including a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor. The first transistor and the fifth transistor are p-channel transistors. The second transistor and the sixth transistor are n-channel transistors. The third transistor includes an oxide semiconductor layer including a channel formation region. The fourth transistor includes an oxide semiconductor layer including a channel formation region. The seventh transistor includes an oxide semiconductor layer including a channel formation region. The eighth transistor includes an oxide semiconductor layer including a channel formation region. A high voltage is applied to one of a source and a drain of the first transistor. A low voltage is applied to one of a source and a drain of the second transistor. The other of the source and the drain of the first transistor is electrically connected to the other of the source and the drain of the second transistor, one of a source and a drain of the seventh transistor, and one of a source and a drain of the eighth transistor. The high voltage is applied to one of a source and a drain of the fifth transistor. The low voltage is applied to one of a source and a drain of the sixth transistor. The other of the source and the drain of the fifth transistor is electrically connected to the other of the source and the drain of the sixth transistor, one of a source and a drain of the third transistor, and one of a source and a drain of the fourth transistor. A gate of the first transistor is electrically connected to the other of the source and the drain of the fourth transistor. A gate of the second transistor is electrically connected to the other of the source and the drain of the third transistor. A gate of the fifth transistor is electrically connected to the other of the source and the drain of the eighth transistor. A gate of the sixth transistor is electrically connected to the other of the source and the drain of the seventh transistor. 
     In the semiconductor device of one embodiment of the present invention, the channel formation region of each of the third, fourth, seventh, and eighth transistors is included in the oxide semiconductor layer. Thus, even if the high voltage and the low voltage are temporarily interrupted, a voltage of a node electrically connected to the other of the source and the drain of the first transistor and the other of the source and the drain of the second transistor can be recovered when the high voltage and the low voltage are recovered. Moreover, a voltage of a node electrically connected to the other of the source and the drain of the fifth transistor and the other of the source and the drain of the sixth transistor can be recovered. 
     In the semiconductor device of one embodiment of the present invention, since the channel formation region of some of the transistors is included in the oxide semiconductor layer, even if the high voltage and the low voltage are temporarily interrupted, the original state can be recovered when the high voltage and the low voltage are recovered. In other words, data can be maintained during instantaneous power reduction or interruption. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       In the accompanying drawings, 
         FIG. 1  is a circuit diagram of a semiconductor device; 
         FIG. 2  is a timing chart; 
         FIG. 3  is a circuit diagram of a semiconductor device; 
         FIG. 4  is a circuit diagram of a semiconductor device; 
         FIG. 5  is a circuit diagram of a semiconductor device; 
         FIG. 6  is a circuit diagram of a semiconductor device; 
         FIG. 7  is a timing chart; 
         FIG. 8  is a circuit diagram of a semiconductor device; 
         FIG. 9  is a timing chart; 
         FIG. 10  is a circuit diagram of a semiconductor device; 
         FIG. 11  is a circuit diagram of a semiconductor device; 
         FIG. 12  is a circuit diagram of a semiconductor device; 
         FIG. 13  is a circuit diagram of a semiconductor device; 
         FIG. 14  is a circuit diagram of a semiconductor device; 
         FIG. 15  is a circuit diagram of a semiconductor device; 
         FIG. 16  is a circuit diagram of a semiconductor device; 
         FIG. 17  is a circuit diagram of a semiconductor device; 
         FIG. 18  is a circuit diagram of a semiconductor device; 
         FIG. 19  is a timing chart; 
         FIG. 20  is a circuit diagram of a semiconductor device; 
         FIG. 21  is a circuit diagram of a semiconductor device; 
         FIG. 22  is a circuit diagram of a semiconductor device; 
         FIG. 23  is a circuit diagram of a semiconductor device; 
         FIG. 24  is a block diagram of a semiconductor device; 
         FIG. 25  is a circuit diagram of a semiconductor device; 
         FIG. 26  is a circuit diagram of a semiconductor device; 
         FIG. 27  is a timing chart; 
         FIG. 28  is a cross-sectional view of a semiconductor device; 
         FIGS. 29A and 29B  are cross-sectional views of transistors; 
         FIG. 30  is a block diagram of a CPU; and 
         FIGS. 31A to 31F  each illustrate an electronic device. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Embodiments of the present invention will be described below with reference to the drawings. Note that the present invention is not limited to the following description. It will be readily appreciated by those skilled in the art that various changes and modifications are possible without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the following description of the embodiments. Note that in describing structures of the present invention with reference to the drawings, reference numerals denoting the same portions are used in common in different drawings. 
     In this specification, the term “connection” means electrical connection and corresponds to the state in which current, voltage, or a potential can be supplied or transmitted. Therefore, a connection state means not only a state of direct connection but also a state of indirect connection through a circuit element such as a wiring, a resistor, a diode, or a transistor in which current, voltage, or a potential can be supplied or transmitted. 
     In a block diagram attached to this specification, components are classified according to their functions and shown as independent blocks; however, it is practically difficult to completely separate the components according to their functions, and one component may have a plurality of functions. 
     Note that a “source” of a transistor means a source region that is part of a semiconductor film functioning as an active layer or a source electrode electrically connected to the semiconductor film. Similarly, a “drain” of a transistor means a drain region that is part of a semiconductor film functioning as an active layer or a drain electrode electrically connected to the semiconductor film. A “gate” means a gate electrode. 
     The terms “source” and “drain” of a transistor interchange with each other depending on the type of the channel of the transistor or the levels of potentials applied to the terminals. In general, in an n-channel transistor, a terminal to which a lower potential is applied is called a source, and a terminal to which a higher potential is applied is called a drain. Further, in a p-channel transistor, a terminal to which a lower potential is applied is called a drain, and a terminal to which a higher potential is applied is called a source. In this specification, although connection relation of the transistor is described assuming that the source and the drain are fixed in some cases for convenience, actually, the names of the source and the drain interchange with each other depending on the relation of the potentials. 
     In this specification, the term “parallel” indicates that the angle formed between two straight lines ranges from −10° to 10°, and accordingly also includes the case where the angle ranges from −5° to 5°. In addition, the term “perpendicular” indicates that the angle formed between two straight lines ranges from 80° to 100°, and accordingly includes the case where the angle ranges from 85° to 95°. 
     In this specification, trigonal and rhombohedral crystal systems are included in a hexagonal crystal system. 
     Embodiment 1 
       FIG. 1  illustrates a semiconductor device  100 . The semiconductor device  100  includes a transistor  101 , a transistor  102 , a transistor  103 , a transistor  104 , a capacitor  105 , a transistor  106 , a transistor  107 , a transistor  108 , a transistor  109 , and a capacitor  110 . In the transistors  104  and  109 , an oxide semiconductor layer includes a channel formation region. Thus, even if power supply is interrupted in the semiconductor device  100 , data can be restored. Note that the transistors  101  and  106  are switches for controlling input or output of signals and are provided as needed. The capacitors  105  and  110  are provided as needed. 
     A signal Sig 1  is input to a gate of the transistor  101  from a wiring  111 . 
     A signal Sig 3  is input to one of a source and a drain of the transistor  101  from a wiring  113 . 
     The other of the source and the drain of the transistor  101  is electrically connected to a drain of the transistor  102 , a drain of the transistor  103 , a gate of the transistor  107 , and one of a source and a drain of the transistor  109 . 
     The transistor  102  is a p-channel transistor. 
     A gate of the transistor  102  is electrically connected to one of a source and a drain of the transistor  104 , one of a source and a drain of the transistor  106 , a drain of the transistor  107 , and a drain of the transistor  108 . 
     A voltage VDD is applied to a source of the transistor  102 . Note that the voltage VDD is a high voltage and is higher than a voltage VSS 1  and a voltage VSS 2 . The voltage VDD may be a high power supply voltage. 
     The drain of the transistor  102  is electrically connected to the other of the source and the drain of the transistor  101 , the drain of the transistor  103 , the gate of the transistor  107 , and one of the source and the drain of the transistor  109 . 
     The transistor  103  is an n-channel transistor. 
     A gate of the transistor  103  is electrically connected to the other of the source and the drain of the transistor  104  and one electrode of the capacitor  105 . 
     The voltage VSS 1  is applied to a source of the transistor  103 . The voltage VSS 1  is a low voltage and is lower than the voltage VDD. The voltage VSS 1  may be a reference potential. 
     The drain of the transistor  103  is electrically connected to the other of the source and the drain of the transistor  101 , the drain of the transistor  102 , the gate of the transistor  107 , and one of the source and the drain of the transistor  109 . 
     The channel formation region of the transistor  104  is included in an oxide semiconductor layer; thus, the off-state current of the transistor  104 , that is, the leakage current of the transistor  104  in an off state is extremely low. 
     A signal Sig 2  is input to a gate of the transistor  104  from a wiring  112 . 
     One of the source and the drain of the transistor  104  is electrically connected to the gate of the transistor  102 , the drain of the transistor  107 , the drain of the transistor  108 , and one of the source and the drain of the transistor  106 . 
     The other of the source and the drain of the transistor  104  is electrically connected to the gate of the transistor  103  and the one electrode of the capacitor  105 . 
     The one electrode of the capacitor  105  is electrically connected to the gate of the transistor  103  and the other of the source and the drain of the transistor  104 . 
     The voltage VSS 2  is applied to the other electrode of the capacitor  105 . The voltage VSS 2  is a low voltage and is lower than the voltage VDD. The voltage VSS 2  may be a reference potential. Here, the voltages of the wirings and the terminals are relative to each other, and whether each voltage is higher or lower than a given reference voltage is an important factor. Thus, the term “GND” is not limited to 0 V. The same applies to the drawings, and a portion indicated by GND does not necessarily have 0 V. Although one electrode of a capacitor is grounded in some drawings, it may be electrically connected to a power supply line of VSS, VDD, or the like as long as the capacitor can hold a voltage. 
     Note that the other electrode of the capacitor  105  may be electrically connected to a wiring different from VSS 2 , for example, a wiring to which the voltage VDD, the voltage VSS 1 , or the voltage GND can be supplied. The same applies to the other electrode of the capacitor  110 . It is preferable that the other electrode of the capacitor  105  and the other electrode of the capacitor  110  be electrically connected to the same wiring because the number of wirings can be reduced. However, one embodiment of the present invention is not limited to this, and these electrodes can be electrically connected to different wirings. For example, the other electrode of the capacitor  105  can be electrically connected to a wiring supplied with VSS 2 , and the other electrode of the capacitor  110  can be electrically connected to a wiring supplied with VDD. 
     The signal Sig 1  is input to a gate of the transistor  106  from the wiring  111 . Note that the gate of the transistor  101  is also electrically connected to the wiring  111 . Electrically connecting the two gates to the same wiring in such a manner can reduce the number of wirings. However, one embodiment of the present invention is not limited to this, and the wiring  111  can be divided into two separate wirings so that the two wirings can be electrically connected to the respective gates of the transistors  101  and  106 . Electrically connecting the two gates to different wirings enables different signals to be supplied to the gates, thereby offering greater flexibility in controlling timing. 
     A signal Sig 4  is input to the other of the source and the drain of the transistor  106  from a wiring  114 . The signal Sig 4  is a low voltage signal when the signal Sig 3  is a high voltage signal, whereas the signal Sig 4  is a high voltage signal when the signal Sig 3  is a low voltage signal. 
     When the semiconductor device  100  is used for a memory cell, the wiring  113  serves as a bit line and the wiring  114  serves as an inverted bit line. Accordingly, the states of a node  130  and a node  131  illustrated in  FIG. 1  can be output to the bit line and the inverted bit line. 
     One of the source and the drain of the transistor  106  is electrically connected to the gate of the transistor  102 , one of the source and the drain of the transistor  104 , the drain of the transistor  107 , and the drain of the transistor  108 . 
     The transistor  107  is a p-channel transistor. 
     The gate of the transistor  107  is electrically connected to the other of the source and the drain of the transistor  101 , the drain of the transistor  102 , the drain of the transistor  103 , and one of the source and the drain of the transistor  109 . 
     The voltage VDD is applied to the source of the transistor  107 . 
     The drain of the transistor  107  is electrically connected to the gate of the transistor  102 , one of the source and the drain of the transistor  104 , one of the source and the drain of the transistor  106 , and the drain of the transistor  108 . 
     The transistor  108  is an n-channel transistor. Although the transistors except the transistors  102 ,  103 ,  107 , and  108  can be either an n-channel transistor or a p-channel transistor, the case of using n-channel transistors will be described below. 
     A gate of the transistor  108  is electrically connected to the other of the source and the drain of the transistor  109  and one electrode of the capacitor  110 . 
     The voltage VSS 1  is applied to the source of the transistor  108 . 
     The drain of the transistor  108  is electrically connected to the gate of the transistor  102 , one of the source and the drain of the transistor  104 , one of the source and the drain of the transistor  106 , and the drain of the transistor  107 . 
     The channel of the transistor  109  is included in an oxide semiconductor layer as in the transistor  104 . Thus, the off-state current of the transistor  109 , that is, the leakage current of the transistor  109  in an off state is extremely low. 
     The signal Sig 2  is input to a gate of the transistor  109  from the wiring  112 . Note that the gate of the transistor  104  is also electrically connected to the wiring  112 . Electrically connecting the two gates to the same wiring in such a manner can reduce the number of wirings. However, one embodiment of the present invention is not limited to this, and the wiring  112  can be divided into two separate wirings so that the two wirings can be electrically connected to the respective gates of the transistors  104  and  109 . Electrically connecting the two gates to different wirings enables different signals to be supplied to the gates, thereby offering greater flexibility in controlling timing. 
     One of the source and the drain of the transistor  109  is electrically connected to the other of the source and the drain of the transistor  101 , the drain of the transistor  102 , the drain of the transistor  103 , and the gate of the transistor  107 . 
     The other of the source and the drain of the transistor  109  is electrically connected to the gate of the transistor  108  and the one electrode of the capacitor  110 . 
     The voltage VSS 2  is applied to the other electrode of the capacitor  110 . 
     An example of the operation of the semiconductor device  100  will be described.  FIG. 2  is a timing chart. Although the voltage VSS 1  and the voltage VSS 2  are the same voltage in  FIG. 2 , they are not necessarily the same voltage. 
     The signal Sig 1  (high signal) is input to the gate of the transistor  101  and the gate of the transistor  106 . The transistors  101  and  106  are turned on. 
     The signal Sig 2  (high signal) is input to the gate of the transistor  104  and the gate of the transistor  109 . The transistors  104  and  109  are turned on. 
     The signal Sig 3  (high signal) is input to one of the source and the drain of the transistor  101 . The node  130  is set to high level. The high signal is input to the gate of the transistor  107 , so that the transistor  107  is turned off because the transistor  107  is a p-channel transistor. Moreover, the high signal is input to one of the source and the drain of the transistor  109 . Since the transistor  109  is on, the high signal is input to the gate of the transistor  108  and the one electrode of the capacitor  110 . As a result, the transistor  108  is turned on, and a node  133  is set to high level. 
     The transistor  106  is on, and the signal Sig 4  (low signal) is input to one of the source and the drain of the transistor  106 . The node  131  is set to low level. The low signal is input to the gate of the transistor  102 , and the transistor  102  is turned on. Moreover, the low signal is input to one of the source and the drain of the transistor  104 . Since the transistor  104  is on, the low signal is input to the gate of the transistor  103  and the one electrode of the capacitor  105 . Since the transistor  103  is an n-channel transistor, the transistor  103  is turned off. The node  132  is set to low level. 
     Accordingly, the node  130  is set to high level and the node  131  is set to low level; thus, a write operation is completed. 
     Next, the transistors  101  and  106  are turned off by the signal Sig 1 . Since the transistor  102  is on and the transistor  103  is off at this time, the node  130  is supplied with the voltage VDD and remains at high level. On the other hand, since the transistor  108  is on and the transistor  107  is off, the node  131  is supplied with the voltage VSS 1  and remains at low level. 
     Then, the transistors  104  and  109  are turned off by the signal Sig 2 . The transistor  103  remains off because the low signal of the node  132  is supplied to the gate of the transistor  103 . The transistor  108  remains on because the high signal of the node  133  is supplied to the gate of the transistor  108 . 
     Assuming that the voltage VDD, the voltage VSS 1 , and the voltage VSS 2  are temporarily lowered or interrupted at time t 1 , the states held at the nodes  130  and  131  are lost. At this time, at least the transistors  104  and  109  are off owing to the signal Sig 2 . Since the off-state current of the transistors  104  and  109  is extremely low, the states held at the nodes  132  and  133  are not lost. Thus, the transistor  103  is off and the transistor  108  is on. 
     Then, assuming that the voltage VDD, the voltage VSS 1 , and the voltage VSS 2  are recovered at time t 2 , since the transistor  108  is on, the node  131  is supplied with the voltage VSS 1  and set to low level. 
     The low signal is input to the gate of the transistor  102 , so that the transistor  102  is turned on. 
     The voltage VDD is applied to the node  130 , so that the node  130  is set to high level. 
     Accordingly, the states of the nodes  130  and  131  are recovered. After that, the transistors  104  and  109  are turned on by the signal Sig 2 , the node  133  remains at high level, and the node  132  remains at low level. 
     In the semiconductor device  100 , even if the voltage VDD, the voltage VSS 1 , and the voltage VSS 2  are interrupted, data can be restored when these voltages are subsequently recovered. 
     Note that the transistors  102  and  107  may be resistors. The semiconductor device  100  illustrated in  FIG. 3  includes a resistor  120  and a resistor  121  instead of the transistor  102  and the transistor  107 , respectively. 
     The voltage VDD is applied to one terminal of the resistor  120 . The other terminal of the resistor  120  is electrically connected to the other of the source and the drain of the transistor  101 , the drain of the transistor  103 , and one of the source and the drain of the transistor  109 . 
     The voltage VDD is applied to one terminal of the resistor  121 . The other terminal of the resistor  121  is electrically connected to one of the source and the drain of the transistor  106 , the drain of the transistor  108 , and one of the source and the drain of the transistor  104 . 
     The operation of the semiconductor device  100  in  FIG. 3  is similar to that of the semiconductor device  100  in  FIG. 1 ; therefore, the detailed description is omitted here. 
     This embodiment can be combined with any other embodiment as appropriate. 
     Embodiment 2 
       FIG. 4  illustrates a semiconductor device  200 . The semiconductor device  200  includes the transistor  101 , the transistor  102 , the transistor  103 , a transistor  115 , a capacitor  116 , the transistor  106 , the transistor  107 , the transistor  108 , a transistor  117 , and a capacitor  118 . In the transistors  115  and  117 , an oxide semiconductor layer includes a channel formation region. Thus, even if power supply is interrupted in the semiconductor device  200 , data can be restored. Note that the transistors  101  and  106  are switches for controlling input or output of signals and are provided as needed. The capacitors  116  and  118  are provided as needed. 
     The semiconductor device  200  differs from the semiconductor device  100  ( FIG. 1 ) in that the transistor  104 , the capacitor  105 , the transistor  109 , and the capacitor  110  are not provided and that the transistor  115 , the capacitor  116 , the transistor  117 , and the capacitor  118  are provided. 
     The channel of the transistor  115  is included in an oxide semiconductor layer; thus, the off-state current of the transistor  115 , that is, the leakage current of the transistor  115  in an off state is extremely low. 
     The signal Sig 2  is input to a gate of the transistor  115  from the wiring  112 . 
     One of a source and a drain of the transistor  115  is electrically connected to the gate of the transistor  103 , the drain of the transistor  107 , the drain of the transistor  108 , and one of the source and the drain of the transistor  106 . 
     The other of the source and the drain of the transistor  115  is electrically connected to the gate of the transistor  102  and one electrode of the capacitor  116 . 
     The one electrode of the capacitor  116  is electrically connected to the gate of the transistor  102  and the other of the source and the drain of the transistor  115 . 
     The voltage VSS 2  is applied to the other electrode of the capacitor  116 . The voltage VSS 2  is a low voltage and is lower than the voltage VDD. The voltage VSS 2  may be a reference potential. Note that the other electrode of the capacitor  116  may be electrically connected to a wiring different from a wiring to which VSS 2  can be supplied, for example, a wiring to which the voltage VDD, the voltage VSS 1 , or the voltage GND can be supplied. 
     The channel of the transistor  117  is included in an oxide semiconductor layer as in the transistor  115 . Thus, the off-state current of the transistor  117 , that is, the leakage current of the transistor  117  in an off state is extremely low. 
     The signal Sig 2  is input to a gate of the transistor  117  from the wiring  112 . Note that the gate of the transistor  115  is also electrically connected to the wiring  112 . Electrically connecting the two gates to the same wiring in such a manner can reduce the number of wirings. However, one embodiment of the present invention is not limited to this, and the wiring  112  can be divided into two separate wirings so that the two wirings can be electrically connected to the respective gates of the transistors  115  and  117 . Electrically connecting the two gates to different wirings enables different signals to be supplied to the gates, thereby offering greater flexibility in controlling timing. 
     One of a source and a drain of the transistor  117  is electrically connected to the other of the source and the drain of the transistor  101 , the drain of the transistor  102 , the drain of the transistor  103 , and the gate of the transistor  108 . 
     The other of the source and the drain of the transistor  117  is electrically connected to the gate of the transistor  107  and one electrode of the capacitor  118 . Although the transistors  115  and  117  can be either an n-channel transistor or a p-channel transistor, the case of using n-channel transistors will be described below. 
     The voltage VSS 2  is applied to the other electrode of the capacitor  118 . The other electrode of the capacitor  118  is electrically connected to the other electrode of the capacitor  116 . Note that the other electrode of the capacitor  118  may be electrically connected to a wiring different from a wiring to which VSS 2  can be supplied, for example, a wiring to which the voltage VDD, the voltage VSS 1 , or the voltage GND can be supplied. It is preferable that the other electrode of the capacitor  116  and the other electrode of the capacitor  118  be electrically connected to the same wiring because the number of wirings can be reduced. However, one embodiment of the present invention is not limited to this, and these electrodes can be electrically connected to different wirings. For example, the other electrode of the capacitor  116  can be electrically connected to a wiring supplied with VSS 2 , and the other electrode of the capacitor  118  can be electrically connected to a wiring supplied with VDD. 
     An example of the operation of the semiconductor device  200  will be described.  FIG. 2  shows the timing chart. Although the voltage VSS 1  and the voltage VSS 2  are the same voltage in  FIG. 2 , they are not necessarily the same voltage. 
     The signal Sig 1  (high signal) is input to the gate of the transistor  101  and the gate of the transistor  106 . The transistors  101  and  106  are turned on. 
     The signal Sig 2  (high signal) is input to the gate of the transistor  115  and the gate of the transistor  117 . The transistors  115  and  117  are turned on. 
     The signal Sig 3  (high signal) is input to one of the source and the drain of the transistor  101 . The node  130  is set to high level. The high signal is input to the gate of the transistor  108 , so that the transistor  108  is turned on. Moreover, the high signal is input to one of the source and the drain of the transistor  117 . Since the transistor  117  is on, the high signal is input to the gate of the transistor  107  and the one electrode of the capacitor  118 . The transistor  108  is turned off because the transistor  108  is a p-channel transistor. A node  136  is set to high level. 
     The transistor  106  is on, and the signal Sig 4  (low signal) is input to one of the source and the drain of the transistor  106 . The node  131  is set to low level. The low signal is input to the gate of the transistor  103 , and the transistor  103  is turned off. Moreover, the low signal is input to one of the source and the drain of the transistor  115 . Since the transistor  115  is on, the low signal is input to the gate of the transistor  102  and the one electrode of the capacitor  116 . Since the transistor  102  is a p-channel transistor, the transistor  102  is turned on. A node  135  is set to low level. 
     Accordingly, the node  130  is set to high level and the node  131  is set to low level; thus, a write operation is completed. 
     Next, the transistors  101  and  106  are turned off by the signal Sig 1 . Since the transistor  102  is on and the transistor  103  is off at this time, the node  130  is supplied with the voltage VDD and remains at high level. On the other hand, since the transistor  108  is on and the transistor  107  is off, the node  131  is supplied with the voltage VSS 1  and remains at low level. 
     Then, the transistors  115  and  117  are turned off by the signal Sig 2 . The transistor  102  remains on because the low signal of the node  135  is supplied to the gate of the transistor  102 . The transistor  107  remains off because the high signal of the node  136  is supplied to the gate of the transistor  107 . 
     Assuming that the voltage VDD, the voltage VSS 1 , and the voltage VSS 2  are temporarily lowered or interrupted at time t 1 , the states held at the nodes  130  and  131  are lost. At this time, at least the transistors  115  and  117  are off owing to the signal Sig 2 . Since the off-state current of the transistors  115  and  117  is extremely low, the states held at the nodes  135  and  136  are not lost. Thus, the transistor  102  is on and the transistor  107  is off. 
     Then, assuming that the voltage VDD, the voltage VSS 1 , and the voltage VSS 2  are recovered at time t 2 , since the transistor  102  is on, the node  130  is supplied with the voltage VDD and set to high level. 
     The high signal is input to the gate of the transistor  108 , so that the transistor  108  is turned on. 
     The voltage VSS 1  is applied to the node  131 , so that the node  131  is set to low level. 
     Accordingly, the states of the nodes  130  and  131  are recovered. After that, the transistors  115  and  117  are turned on by the signal Sig 2 , the node  135  remains at low level, and the node  136  remains at high level. 
     In the semiconductor device  200 , even if the voltage VDD, the voltage VSS 1 , and the voltage VSS 2  are interrupted, data can be restored when these voltages are subsequently recovered. 
     Note that the transistors  103  and  108  may be resistors. The semiconductor device  200  illustrated in  FIG. 5  includes a resistor  122  and a resistor  123  instead of the transistor  103  and the transistor  108 , respectively. 
     One terminal of the resistor  122  is electrically connected to the other of the source and the drain of the transistor  101 , the drain of the transistor  102 , and one of the source and the drain of the transistor  117 . The voltage VSS 1  is applied to the other terminal of the resistor  122 . 
     One terminal of the resistor  123  is electrically connected to one of the source and the drain of the transistor  106 , the drain of the transistor  107 , and one of the source and the drain of the transistor  115 . The voltage VSS 1  is applied to the other terminal of the resistor  123 . 
     The operation of the semiconductor device  200  in  FIG. 5  is similar to that of the semiconductor device  200  in  FIG. 4 ; therefore, the detailed description is omitted here. 
     This embodiment can be combined with any other embodiment as appropriate. 
     Embodiment 3 
       FIG. 6  illustrates a semiconductor device  250 . The semiconductor device  250  includes the transistor  101 , the transistor  102 , the transistor  103 , the transistor  104 , the capacitor  105 , the transistor  106 , the transistor  107 , the transistor  108 , the transistor  109 , the capacitor  110 , the transistor  115 , the transistor  117 , the capacitor  116 , and the capacitor  118 . In the transistors  104 ,  109 ,  115 , and  117 , an oxide semiconductor layer includes a channel formation region. Thus, even if power supply is interrupted in the semiconductor device  250 , data can be restored. Note that the transistors  101  and  106  are switches for controlling input or output of signals and are provided as needed. The capacitors  105 ,  110 ,  116 , and  118  are provided as needed. 
     The semiconductor device  250  has a structure in which the semiconductor device  100  ( FIG. 1 ) and the semiconductor device  200  ( FIG. 4 ) are combined. 
     The channel of the transistor  104  is included in an oxide semiconductor layer; thus, the off-state current of the transistor  104 , that is, the leakage current of the transistor  104  in an off state is extremely low. 
     A signal Sig 5  is input to the gate of the transistor  104  from a wiring  125 . Note that the gate of the transistor  109  is also electrically connected to the wiring  125 . Electrically connecting the two gates to the same wiring in such a manner can reduce the number of wirings. However, one embodiment of the present invention is not limited to this, and the wiring  125  can be divided into two separate wirings so that the two wirings can be electrically connected to the respective gates of the transistors  104  and  109 . Electrically connecting the two gates to different wirings enables different signals to be supplied to the gates, thereby offering greater flexibility in controlling timing. 
     One of the source and the drain of the transistor  104  is electrically connected to one of the source and the drain of the transistor  115 , the drain of the transistor  107 , the drain of the transistor  108 , and one of the source and the drain of the transistor  106 . 
     The other of the source and the drain of the transistor  104  is electrically connected to the gate of the transistor  103  and one electrode of the capacitor  105 . 
     The one electrode of the capacitor  105  is electrically connected to the gate of the transistor  103  and the other of the source and the drain of the transistor  104 . 
     The voltage VSS 2  is applied to the other electrode of the capacitor  105 . The voltage VSS 2  is a low voltage and is lower than the voltage VDD. The voltage VSS 2  may be a reference potential. Note that the other electrode of the capacitor  105  may be electrically connected to a wiring different from a wiring to which VSS 2  can be supplied, for example, a wiring to which the voltage VDD, the voltage VSS 1 , or the voltage GND can be supplied. The same applies to the other electrode of the capacitor  110 , the other electrode of the capacitor  116 , and the other electrode of the capacitor  118 . It is preferable that the other electrode of the capacitor  105 , the other electrode of the capacitor  110 , the other electrode of the capacitor  116 , and the other electrode of the capacitor  118  be electrically connected to the same wiring because the number of wirings can be reduced. However, one embodiment of the present invention is not limited to this, and these electrodes can be electrically connected to different wirings. For example, the other electrode of the capacitor  105  can be electrically connected to a wiring supplied with VSS 2 , and the other electrode of the capacitor  110 , the other electrode of the capacitor  116 , and the other electrode of the capacitor  118  can be electrically connected to a wiring supplied with VDD. 
     The channel of the transistor  115  is included in an oxide semiconductor layer; thus, the off-state current of the transistor  115 , that is, the leakage current of the transistor  115  in an off state is extremely low. 
     The signal Sig 2  is input to the gate of the transistor  115  from the wiring  112 . Note that the gate of the transistor  117  is also electrically connected to the wiring  112 . Electrically connecting the two gates to the same wiring in such a manner can reduce the number of wirings. However, one embodiment of the present invention is not limited to this, and the wiring  112  can be divided into two separate wirings so that the two wirings can be electrically connected to the respective gates of the transistors  115  and  117 . Electrically connecting the two gates to different wirings enables different signals to be supplied to the gates, thereby offering greater flexibility in controlling timing. 
     One of the source and the drain of the transistor  115  is electrically connected to one of the source and the drain of the transistor  104 , the drain of the transistor  107 , the drain of the transistor  108 , and one of the source and the drain of the transistor  106 . 
     The other of the source and the drain of the transistor  115  is electrically connected to the gate of the transistor  102  and one electrode of the capacitor  116 . 
     The one electrode of the capacitor  116  is electrically connected to the gate of the transistor  102  and the other of the source and the drain of the transistor  115 . 
     The voltage VSS 2  is applied to the other electrode of the capacitor  116 . The voltage VSS 2  is a low voltage and is lower than the voltage VDD. 
     The channel of the transistor  109  is included in an oxide semiconductor layer; thus, the off-state current of the transistor  109 , that is, the leakage current of the transistor  109  in an off state is extremely low. 
     The signal Sig 5  is input to the gate of the transistor  109  from the wiring  125 . 
     One of the source and the drain of the transistor  109  is electrically connected to the other of the source and the drain of the transistor  101 , the drain of the transistor  102 , the drain of the transistor  103 , and one of the source and the drain of the transistor  117 . 
     The other of the source and the drain of the transistor  109  is electrically connected to the gate of the transistor  108  and the one electrode of the capacitor  110 . 
     The one electrode of the capacitor  110  is electrically connected to the gate of the transistor  108  and the other of the source and the drain of the transistor  109 . 
     The voltage VSS 2  is applied to the other electrode of the capacitor  110 . 
     The channel of the transistor  117  is included in an oxide semiconductor layer; thus, the off-state current of the transistor  117 , that is, the leakage current of the transistor  117  in an off state is extremely low. 
     The signal Sig 2  is input to the gate of the transistor  117  from the wiring  112 . 
     One of the source and the drain of the transistor  117  is electrically connected to one of the source and the drain of the transistor  109 , the drain of the transistor  102 , the drain of the transistor  103 , and the other of the source and the drain of the transistor  101 . 
     The other of the source and the drain of the transistor  117  is electrically connected to the gate of the transistor  107  and the one electrode of the capacitor  118 . 
     The one electrode of the capacitor  118  is electrically connected to the gate of the transistor  107  and the other of the source and the drain of the transistor  117 . 
     The voltage VSS 2  is applied to the other electrode of the capacitor  118 . The voltage VSS 2  is a low voltage and is lower than the voltage VDD. The voltage VSS 2  may be a reference potential. 
     An example of the operation of the semiconductor device  250  will be described.  FIG. 7  is a timing chart. Although the signal Sig 2  and the signal Sig 5  are the same signal in  FIG. 7 , they are not necessarily the same signal. Although the voltage VSS 1  and the voltage VSS 2  are the same voltage in  FIG. 7 , they are not necessarily the same voltage. 
     The signal Sig 1  (high signal) is input to the gate of the transistor  101  and the gate of the transistor  106 . The transistors  101  and  106  are turned on. 
     The signal Sig 2  (high signal) is input to the gate of the transistor  115  and the gate of the transistor  117 . The transistors  115  and  117  are turned on. 
     The signal Sig 5  (high signal) is input to the gate of the transistor  104  and the gate of the transistor  109 . The transistors  104  and  109  are turned on. 
     The signal Sig 3  (high signal) is input to one of the source and the drain of the transistor  101 . The node  130  is set to high level. Since the transistor  117  is on, the high signal is input to the gate of the transistor  107  and the one electrode of the capacitor  118 . The transistor  107  is turned off because the transistor  107  is a p-channel transistor. The node  136  is set to high level. 
     Since the transistor  109  is on, the high signal is input to the gate of the transistor  108  and the one electrode of the capacitor  110 . As a result, the transistor  108  is turned on, and the node  133  is set to high level. 
     The transistor  106  is on, and the signal Sig 4  (low signal) is input to one of the source and the drain of the transistor  106 . The node  131  is set to low level. Since the transistor  115  is on, the low signal is input to the gate of the transistor  102  and the one electrode of the capacitor  116 . Since the transistor  102  is a p-channel transistor, the transistor  102  is turned on. 
     Since the transistor  104  is on, the low signal is input to the gate of the transistor  103  and the one electrode of the capacitor  105 . Since the transistor  103  is an n-channel transistor, the transistor  103  is turned off. The node  132  is set to low level. 
     Accordingly, the node  130  is set to high level and the node  131  is set to low level; thus, a write operation is completed. 
     Next, the transistors  101  and  106  are turned off by the signal Sig 1 . Since the transistor  102  is on and the transistor  103  is off at this time, the node  130  is supplied with the voltage VDD and remains at high level. On the other hand, since the transistor  108  is on and the transistor  107  is off, the node  131  is supplied with the voltage VSS 1  and remains at low level. 
     Then, the transistors  104  and  109  are turned off by the signal Sig 5 . The transistor  103  remains off because the low signal of the node  132  is supplied to the gate of the transistor  103 . The transistor  108  remains on because the high signal of the node  133  is supplied to the gate of the transistor  108 . 
     The transistors  115  and  117  are turned off by the signal Sig 2 . The transistor  102  remains on because the low signal of the node  135  is supplied to the gate of the transistor  102 . The transistor  107  remains off because the high signal of the node  136  is supplied to the gate of the transistor  107 . 
     Assuming that the voltage VDD, the voltage VSS 1 , and the voltage VSS 2  are temporarily lowered or interrupted at time t 1 , the states held at the nodes  130  and  131  are lost. At this time, the transistors  104  and  109  are off owing to the signal Sig 5 . Since the off-state current of the transistors  104  and  109  is extremely low, the states held at the nodes  132  and  133  are not lost. Thus, the transistor  103  is off and the transistor  108  is on. 
     Further, at this time, the transistors  115  and  117  are off owing to the signal Sig 2 . Since the off-state current of the transistors  115  and  117  is extremely low, the states held at the nodes  135  and  136  are not lost. Thus, the transistor  102  is on and the transistor  107  is off. 
     Then, if the voltage VDD, the voltage VSS 1 , and the voltage VSS 2  are recovered at time t 2 , since the transistor  102  is on and the transistor  103  is off, the node  130  is supplied with the voltage VDD and set to high level. Moreover, since the transistor  108  is on and the transistor  107  is off, the node  131  is supplied with the voltage VSS 1  and set to low level. 
     Accordingly, the states of the nodes  130  and  131  are recovered. After that, the transistors  104  and  109  are turned on by the signal Sig 5 , the node  133  remains at high level, and the node  132  remains at low level. The transistors  115  and  117  are turned on by the signal Sig 2 , the node  135  remains at low level, and the node  136  remains at high level. 
     In the semiconductor device  250 , data can be restored even if the voltage VDD, the voltage VSS 1 , and the voltage VSS 2  are interrupted. 
     This embodiment can be combined with any other embodiment as appropriate. 
     Embodiment 4 
       FIG. 8  illustrates a semiconductor device  150 . The semiconductor device  150  includes the transistor  101 , the transistor  102 , the transistor  103 , the transistor  104 , the capacitor  105 , the transistor  107 , the transistor  108 , the transistor  109 , the capacitor  110 , a liquid crystal element  140 , and a capacitor  141 . The semiconductor device  150  is a liquid crystal display device. A channel formation region of each of the transistors  104  and  109  is included in an oxide semiconductor layer. Thus, even if power supply is interrupted in the semiconductor device  150 , the state of the liquid crystal element  140  can be recovered. Note that the capacitors  105  and  110  are provided as needed. 
     The semiconductor device  150  differs from the semiconductor device  100  ( FIG. 1 ) in not including the transistor  106  and in including the liquid crystal element  140  and the capacitor  141 . Moreover, in the semiconductor device  150 , a voltage VSS is applied to the other electrode the capacitor  105 , the other electrode the capacitor  110 , the source of the transistor  103 , and the source of the transistor  108 . The voltage VSS is a low voltage and is lower than the voltage VDD. The voltage VSS may be a reference potential. 
     One electrode of the liquid crystal element  140  is electrically connected to the gate of the transistor  102 , one of the source and the drain of the transistor  104 , the drain of the transistor  107 , the drain of the transistor  108 , and one electrode of the capacitor  141 . 
     The other electrode of the liquid crystal element  140  is electrically connected to a wiring supplied with a reference potential (GND). When GND is an intermediate or nearly intermediate voltage between the voltage VDD and the voltage VSS, a positive signal and a negative signal can be supplied to the liquid crystal element  140 , whereby the liquid crystal element  140  can be driven by an inversion scheme. 
     The one electrode of the capacitor  141  is electrically connected to the gate of the transistor  102 , one of the source and the drain of the transistor  104 , the drain of the transistor  107 , the drain of the transistor  108 , and the one electrode of the liquid crystal element  140 . 
     The other electrode of the capacitor  141  is electrically connected to a wiring supplied with the reference potential (GND). 
     An example of the operation of the semiconductor device  150  will be described.  FIG. 9  is a timing chart. 
     The signal Sig 1  (high signal) is input to the gate of the transistor  101 . The transistor  101  is turned on. 
     The signal Sig 2  (high signal) is input to the gate of the transistor  104  and the gate of the transistor  109 . The transistors  104  and  109  are turned on. 
     The signal Sig 3  (low signal) is input to one of the source and the drain of the transistor  101 . The node  130  is set to low level. The low signal is input to the gate of the transistor  107 , and the transistor  107  is turned on. Since the transistor  109  is on, the low signal is input to the gate of the transistor  108  and the one electrode of the capacitor  110 . As a result, the transistor  108  is turned off, and the node  131  is set to high level. 
     The high signal is input to the one electrode of the liquid crystal element  140 , so that a voltage is applied to the liquid crystal element  140 . The high signal is also input to the one electrode of the capacitor  141 , so that charge is stored in the capacitor  141 . 
     The high signal is input to the gate of the transistor  102 , and the transistor  102  is turned off. Since the transistor  104  is on, the high signal is input to the gate of the transistor  103  and the one electrode of the capacitor  105 ; thus, the transistor  103  is turned on. The node  130  is set to low level. 
     Next, the transistor  101  is turned off by the signal Sig 1 . Since the transistor  102  is off and the transistor  103  is on at this time, the node  130  is supplied with the voltage VSS and remains at low level. On the other hand, since the transistor  107  is on and the transistor  108  is off, the node  131  is supplied with the voltage VDD and remains at high level. 
     Then, the transistors  104  and  109  are turned off by the signal Sig 2 . The transistor  103  remains on because the high signal is supplied to the gate of the transistor  103 . The transistor  108  remains off because the low signal is supplied to the gate of the transistor  108 . 
     Assuming that the voltage VDD and the voltage VSS are temporarily lowered or interrupted at time t 1 , the states held at the nodes  130  and  131  are lost. At this time, at least the transistors  104  and  109  are off owing to the signal Sig 2 . Since the off-state current of the transistors  104  and  109  is extremely low, the transistor  103  is kept on and the transistor  108  is kept off. 
     Then, if the voltage VDD and the voltage VSS are recovered at time t 2 , since the transistor  103  is on, the node  130  is supplied with the voltage VSS and set to low level. 
     The low signal is input to the gate of the transistor  107 , and the transistor  107  is turned on. 
     The voltage VDD is applied to the node  131 , so that the node  131  is set to high level. The high signal is input to the one electrode of the liquid crystal element  140 , and a voltage is applied to the liquid crystal element  140 . 
     Accordingly, the state of the liquid crystal element  140  is recovered. 
     In the semiconductor device  150 , data can be restored even if the voltage VDD and the voltage VSS are interrupted. 
     Note that the transistors  102  and  107  may be resistors. The semiconductor device  150  illustrated in  FIG. 10  includes the resistor  120  and the resistor  121  instead of the transistor  102  and the transistor  107 , respectively. 
       FIG. 11  illustrates a semiconductor device  155 . The semiconductor device  155  includes the transistor  101 , the transistor  102 , the transistor  103 , the transistor  104 , the capacitor  105 , the transistor  107 , the transistor  108 , the transistor  109 , the capacitor  110 , a transistor  142 , an EL element  143 , and the capacitor  141 . The semiconductor device  155  is an EL display device. A current is supplied to the EL element  143  from a wiring  144 . Note that the transistor  142  may be electrically connected to a wiring having a function of supplying the voltage VDD, instead of the wiring  144 . Similarly, the EL element  143  may be electrically connected to a wiring having a function of supplying the voltage VSS, instead of a wiring having a function of supplying the voltage GND. 
     The operation of the semiconductor device  155  is similar to that of the semiconductor device  150 . When the node  131  is set to high level, the high signal is input to a gate of the transistor  142  and one electrode of the capacitor  141 . The transistor  142  is turned on and thus a current is supplied to the EL element  143  from the wiring  144 , so that electroluminescence is obtained. 
     In the semiconductor device  155 , when the voltage VDD and the voltage VSS are interrupted and then recovered, the node  131  is set to high level. Accordingly, the state of the EL element  143  is recovered. 
     Note that the transistors  102  and  107  may be resistors. The semiconductor device  155  illustrated in  FIG. 12  includes the resistor  120  and the resistor  121  instead of the transistor  102  and the transistor  107 , respectively. 
     This embodiment can be combined with any other embodiment as appropriate. 
     Embodiment 5 
       FIG. 13  illustrates a semiconductor device  260 . The semiconductor device  260  includes the transistor  101 , the transistor  102 , the transistor  103 , the transistor  115 , the capacitor  116 , the transistor  107 , the transistor  108 , the transistor  117 , the capacitor  118 , the liquid crystal element  140 , and the capacitor  141 . The semiconductor device  260  is a liquid crystal display device. In the transistors  115  and  117 , an oxide semiconductor layer includes a channel formation region. Thus, even if power supply is interrupted in the semiconductor device  260 , the state of the liquid crystal element  140  can be recovered. Note that the capacitors  116  and  118  are provided as needed. 
     The semiconductor device  260  differs from the semiconductor device  150  ( FIG. 8 ) in that the transistor  104 , the capacitor  105 , the transistor  109 , and the capacitor  110  are not provided and that the transistor  115 , the capacitor  116 , the transistor  117 , and the capacitor  118  are provided. 
     An example of the operation of the semiconductor device  260  will be described.  FIG. 9  shows the timing chart. 
     The signal Sig 1  (high signal) is input to the gate of the transistor  101 . The transistor  101  is turned on. 
     The signal Sig 2  (high signal) is input to the gate of the transistor  115  and the gate of the transistor  117 . The transistors  115  and  117  are turned on. 
     The signal Sig 3  (low signal) is input to one of the source and the drain of the transistor  101 . The node  130  is set to low level. Since the transistor  117  is on, the low signal is input to the gate of the transistor  107 , and the transistor  107  is turned on. The low signal is input to the gate of the transistor  108  and the one electrode of the capacitor  110 . As a result, the transistor  108  is turned off, and the node  131  is set to high level. 
     The high signal is input to the one electrode of the liquid crystal element  140 , so that a voltage is applied to the liquid crystal element  140 . The high signal is also input to the one electrode of the capacitor  141 , so that charge is stored in the capacitor  141 . 
     Since the transistor  115  is on, the high signal is input to the gate of the transistor  102 ; thus, the transistor  102  is turned off. The high signal is input to the gate of the transistor  103  and the one electrode of the capacitor  105 , so that the transistor  103  is turned on. The node  130  is set to low level. 
     Next, the transistor  101  is turned off by the signal Sig 1 . Since the transistor  102  is off and the transistor  103  is on at this time, the node  130  is supplied with the voltage VSS and remains at low level. On the other hand, since the transistor  107  is on and the transistor  108  is off, the node  131  is supplied with the voltage VDD and remains at high level. 
     Then, the transistors  115  and  117  are turned off by the signal Sig 2 . The transistor  102  remains off because the high signal is supplied to the gate of the transistor  102 . The transistor  107  remains on because the low signal is supplied to the gate of the transistor  107 . 
     Assuming that the voltage VDD and the voltage VSS are temporarily lowered or interrupted at time t 1 , the states held at the nodes  130  and  131  are lost. At this time, at least the transistors  115  and  117  are off owing to the signal Sig 2 . Since the off-state current of the transistors  115  and  117  is extremely low, the transistor  102  is kept off and the transistor  107  is kept on. 
     Then, if the voltage VDD and the voltage VSS are recovered at time t 2 , since the transistor  107  is on, the node  131  is supplied with the voltage VDD and set to high level. The high signal is input to the one electrode of the liquid crystal element  140 , so that a voltage is applied to the liquid crystal element  140 . 
     Accordingly, the state of the liquid crystal element  140  is recovered. 
     Note that the transistors  103  and  108  may be resistors. A semiconductor device  262  illustrated in  FIG. 14  includes the resistor  122  and the resistor  123  instead of the transistor  103  and the transistor  108 , respectively. 
       FIG. 15  illustrates a semiconductor device  265 . The semiconductor device  265  includes the transistor  101 , the transistor  102 , the transistor  103 , the transistor  115 , the capacitor  116 , the transistor  107 , the transistor  108 , the transistor  117 , the capacitor  118 , the transistor  142 , the EL element  143 , and the capacitor  141 . The semiconductor device  265  is an EL display device. A current is supplied to the EL element  143  from the wiring  144 . Note that the transistor  142  may be electrically connected to a wiring having a function of supplying the voltage VDD, instead of the wiring  144 . Similarly, the EL element  143  may be electrically connected to a wiring having a function of supplying the voltage VSS, instead of a wiring having a function of supplying the voltage GND. 
     The operation of the semiconductor device  265  is similar to those of the semiconductor device  260  and the semiconductor device  155 ; therefore, the detailed description is omitted here. 
     This embodiment can be combined with any other embodiment as appropriate. 
     Embodiment 6 
       FIG. 16  illustrates a semiconductor device  270 . The semiconductor device  270  includes the transistor  101 , the transistor  102 , the transistor  103 , the transistor  104 , the capacitor  105 , the transistor  107 , the transistor  108 , the transistor  109 , the capacitor  110 , the transistor  115 , the capacitor  116 , the transistor  117 , the capacitor  118 , the liquid crystal element  140 , and the capacitor  141 . The semiconductor device  270  is a liquid crystal display device. In the transistors  104 ,  109 ,  115 , and  117 , an oxide semiconductor layer includes a channel formation region. Thus, even if power supply is interrupted in the semiconductor device  270 , the state of the liquid crystal element  140  can be recovered. Note that the capacitors  105 ,  110 ,  116 , and  118  are provided as needed. 
     The semiconductor device  270  has a structure in which the semiconductor device  150  ( FIG. 8 ) and the semiconductor device  260  ( FIG. 13 ) are combined. 
     An example of the operation of the semiconductor device  270  will be described.  FIG. 9  shows the timing chart. 
     The signal Sig 1  (high signal) is input to the gate of the transistor  101 . The transistor  101  is turned on. 
     The signal Sig 2  (high signal) is input to the gate of the transistor  115  and the gate of the transistor  117 . The transistors  115  and  117  are turned on. 
     The signal Sig 2  (high signal) is input to the gate of the transistor  104  and the gate of the transistor  109 . The transistors  104  and  109  are turned on. 
     The signal Sig 3  (low signal) is input to one of the source and the drain of the transistor  101 . The node  130  is set to low level. Since the transistor  117  is on, the low signal is input to the gate of the transistor  107 , so that the transistor  107  is turned on. Since the transistor  109  is on, the low signal is input to the gate of the transistor  108  and the one electrode of the capacitor  110 . As a result, the transistor  108  is turned off, and the node  131  is set to high level. 
     The high signal is input to the one electrode of the liquid crystal element  140 , so that a voltage is applied to the liquid crystal element  140 . The high signal is also input to the one electrode of the capacitor  141 , so that charge is stored in the capacitor  141 . 
     Since the transistor  115  is on, the high signal is input to the gate of the transistor  102 ; thus, the transistor  102  is turned off. Since the transistor  104  is on, the high signal is input to the gate of the transistor  103  and the one electrode of the capacitor  105 ; thus, the transistor  103  is turned on. The node  130  is set to low level. 
     Next, the transistor  101  is turned off by the signal Sig 1 . Since the transistor  102  is off and the transistor  103  is on at this time, the node  130  is supplied with the voltage VSS and remains at low level. On the other hand, since the transistor  107  is on and the transistor  108  is off, the node  131  is supplied with the voltage VDD and remains at high level. 
     Then, the transistors  104 ,  109 ,  115 , and  117  are turned off by the signal Sig 2 . The transistor  102  remains off because the low signal is supplied to the gate of the transistor  102 . The transistor  103  remains on because the high signal is supplied to the gate of the transistor  103 . The transistor  107  remains on because the low signal is supplied to the gate of the transistor  107 . The transistor  108  remains off because the low signal is supplied to the gate of the transistor  108 . 
     Assuming that the voltage VDD and the voltage VSS are temporarily lowered or interrupted at time t 1 , the states held at the nodes  130  and  131  are lost. At this time, the transistors  104 ,  109 ,  115 , and  117  are off owing to the signal Sig 2 . Since the off-state current of the transistors  104 ,  109 ,  115 , and  117  is extremely low, the transistors  102  and  108  are kept off and the transistors  103  and  107  are kept on. 
     Next, if the voltage VDD and the voltage VSS are recovered at time t 2 , since the transistor  107  is on, the node  131  is supplied with the voltage VDD and set to high level. The high signal is input to the one electrode of the liquid crystal element  140 , so that a voltage is applied to the liquid crystal element  140 . 
     Accordingly, the state of the liquid crystal element  140  is recovered. 
       FIG. 17  illustrates a semiconductor device  275 . The semiconductor device  275  includes the transistor  101 , the transistor  102 , the transistor  103 , the transistor  104 , the capacitor  105 , the transistor  115 , the capacitor  116 , the transistor  107 , the transistor  108 , the transistor  109 , the capacitor  110 , the transistor  117 , the capacitor  118 , the transistor  142 , the EL element  143 , and the capacitor  141 . The semiconductor device  275  is an EL display device. A current is supplied to the EL element  143  from the wiring  144 . Note that the transistor  142  may be electrically connected to a wiring having a function of supplying the voltage VDD, instead of the wiring  144 . Similarly, the EL element  143  may be electrically connected to a wiring having a function of supplying the voltage VSS, instead of a wiring having a function of supplying the voltage GND. 
     The operation of the semiconductor device  275  is similar to those of the semiconductor device  270  and the semiconductor device  155 ; therefore, the detailed description is omitted here. 
     This embodiment can be combined with any other embodiment as appropriate. 
     Embodiment 7 
       FIG. 18  illustrates a semiconductor device  370 . The semiconductor device  370  includes the transistor  101 , the transistor  102 , the transistor  103 , the transistor  104 , the capacitor  105 , the transistor  107 , the transistor  108 , the transistor  109 , and the capacitor  110 . The semiconductor device  370  can function as a register. In the transistors  104  and  109 , an oxide semiconductor layer includes a channel formation region. Thus, even if power supply is interrupted in the semiconductor device  370 , the state of an output (OUT) can be recovered. Note that the capacitors  105  and  110  are provided as needed. 
     The semiconductor device  370  differs from the semiconductor device  100  ( FIG. 1 ) in that the transistor  106  is not provided. 
     An example of the operation of the semiconductor device  370  will be described.  FIG. 19  is a timing chart. 
     The signal Sig 1  (high signal) is input to the gate of the transistor  101 . The transistor  101  is turned on. 
     The signal Sig 2  (high signal) is input to the gate of the transistor  104  and the gate of the transistor  109 . The transistors  104  and  109  are turned on. 
     A signal IN (high signal) is input to one of the source and the drain of the transistor  101 . The node  130  is set to high level. The high signal is input to the gate of the transistor  107 , and the transistor  107  is turned off. Since the transistor  109  is on, the high signal is input to the gate of the transistor  108  and one electrode of the capacitor  110 . As a result, the transistor  108  is turned on, and the output (OUT) is set to low level. 
     The low signal is input to the gate of the transistor  102 , and the transistor  102  is turned on. Since the transistor  104  is on, the low signal is input to the gate of the transistor  103  and the one electrode of the capacitor  105 ; thus, the transistor  103  is turned off. The node  130  is set to high level. 
     Next, the transistor  101  is turned off by the signal Sig 1 . Since the transistor  102  is on and the transistor  103  is off at this time, the node  130  is supplied with the voltage VDD and remains at high level. On the other hand, since the transistor  107  is off and the transistor  108  is on, the output (OUT) is supplied with the voltage VSS 1  and remains at low level. 
     Then, the transistors  104  and  109  are turned off by the signal Sig 2 . The transistor  103  remains off because the low signal is supplied to the gate of the transistor  103 . The transistor  108  remains on because the high signal is supplied to the gate of the transistor  108 . 
     Assuming that the voltage VDD, the voltage VSS 1 , and the voltage VSS 2  are temporarily lowered or interrupted at time t 1 , the states held at the node  130  and the output (OUT) are lost. At this time, at least the transistors  104  and  109  are off owing to the signal Sig 2 . Since the off-state current of the transistors  104  and  109  is extremely low, the transistor  103  is kept off and the transistor  108  is kept on. 
     Then, if the voltage VDD, the voltage VSS 1 , and the voltage VSS 2  are recovered at time t 2 , since the transistor  108  is on, the output (OUT) is supplied with the voltage VSS 1  and set to low level. 
     The low signal is input to the gate of the transistor  102 , and the transistor  102  is turned on. 
     The voltage VDD is applied to the node  130 , and the node  130  is set to high level. 
     Accordingly, the state of the semiconductor device  370  is recovered. 
     In the semiconductor device  370 , data can be restored even if the voltage VDD, the voltage VSS 1 , and the voltage VSS 2  are interrupted. 
     Note that the transistors  102  and  107  may be resistors. The semiconductor device  370  illustrated in  FIG. 20  includes the resistor  120  and the resistor  121  instead of the transistor  102  and the transistor  107 , respectively. 
     The operation of the semiconductor device  370  in  FIG. 20  is similar to that of the semiconductor device  370  in  FIG. 18 ; therefore, the detailed description is omitted here. 
     This embodiment can be combined with any other embodiment as appropriate. 
     Embodiment 8 
       FIG. 21  illustrates a semiconductor device  374 . The semiconductor device  374  includes the transistor  101 , the transistor  102 , the transistor  103 , the transistor  115 , the capacitor  116 , the transistor  107 , the transistor  108 , the transistor  117 , and the capacitor  118 . The semiconductor device  374  can function as a register. In the transistors  115  and  117 , an oxide semiconductor layer includes a channel formation region. Thus, even if power supply is interrupted in the semiconductor device  374 , the state of an output (OUT) can be recovered. Note that the capacitors  116  and  118  are provided as needed. 
     The semiconductor device  374  differs from the semiconductor device  200  ( FIG. 4 ) in that the transistor  106  is not provided. 
     An example of the operation of the semiconductor device  374  will be described.  FIG. 19  shows the timing chart. 
     The signal Sig 1  (high signal) is input to the gate of the transistor  101 . The transistor  101  is turned on. 
     The signal Sig 2  (high signal) is input to the gate of the transistor  115  and the gate of the transistor  117 . The transistors  115  and  117  are turned on. 
     The signal IN (high signal) is input to one of the source and the drain of the transistor  101 . The node  130  is set to high level. Since the transistor  117  is on, the high signal is input to the gate of the transistor  107 , and the transistor  107  is turned off. The high signal is also input to the gate of the transistor  108  and one electrode of the capacitor  118 . As a result, the transistor  108  is turned on, and the output (OUT) is set to low level. 
     Since the transistor  115  is on, the low signal is supplied to the gate of the transistor  102 , and the transistor  102  is turned on. The low signal is supplied to the gate of the transistor  103  and the one electrode of the capacitor  116 , and the transistor  103  is turned off. The node  130  is set to high level. 
     Next, the transistor  101  is turned off by the signal Sig 1 . Since the transistor  102  is on and the transistor  103  is off at this time, the node  130  is supplied with the voltage VDD and remains at high level. On the other hand, since the transistor  107  is off and the transistor  108  is on, the output (OUT) is supplied with the voltage VSS 1  and remains at low level. 
     Then, the transistors  115  and  117  are turned off by the signal Sig 2 . The transistor  102  remains on because the low signal is supplied to the gate of the transistor  102 . The transistor  107  remains off because the high signal is supplied to the gate of the transistor  107 . 
     Assuming that the voltage VDD, the voltage VSS 1 , and the voltage VSS 2  are temporarily lowered or interrupted at time t 1 , the states held at the node  130  and the output (OUT) are lost. At this time, at least the transistors  115  and  117  are off owing to the signal Sig 2 . Since the off-state current of the transistors  115  and  117  is extremely low, the transistor  102  is kept on and the transistor  107  is kept off. 
     Then, if the voltage VDD, the voltage VSS 1 , and the voltage VSS 2  are recovered at time t 2 , since the transistor  102  is on, the node  130  is supplied with the voltage VDD and set to high level. The high signal is input to the gate of the transistor  108 , and the output (OUT) is set to low level. 
     Accordingly, the state of the output is recovered. 
     Note that the transistors  103  and  108  may be resistors. A semiconductor device  375  illustrated in  FIG. 22  includes the resistor  122  and the resistor  123  instead of the transistor  103  and the transistor  108 , respectively. 
     The operation of the semiconductor device  375  is similar to that of the semiconductor device  374 ; therefore, the detailed description is omitted here. 
     This embodiment can be combined with any other embodiment as appropriate. 
     Embodiment 9 
       FIG. 23  illustrates a semiconductor device  376 . The semiconductor device  376  includes the transistor  101 , the transistor  102 , the transistor  103 , the transistor  104 , the capacitor  105 , the transistor  107 , the transistor  108 , the transistor  109 , the capacitor  110 , the transistor  115 , the capacitor  116 , the transistor  117 , and the capacitor  118 . The semiconductor device  376  can function as a register. In the transistors  104 ,  109 ,  115 , and  117 , an oxide semiconductor layer includes a channel formation region. Thus, even if power supply is interrupted in the semiconductor device  376 , the state of an output can be recovered. Note that the capacitors  105 ,  110 ,  116 , and  118  are provided as needed. 
     The semiconductor device  376  differs from the semiconductor device  250  ( FIG. 6 ) in that the transistor  106  is not provided and that the signal Sig 2  is input to the gate of the transistor  104  and the gate of the transistor  109 . 
     An example of the operation of the semiconductor device  376  will be described.  FIG. 19  shows the timing chart. 
     The signal Sig 1  (high signal) is input to the gate of the transistor  101 . The transistor  101  is turned on. 
     The signal Sig 2  (high signal) is input to the gate of the transistor  115  and the gate of the transistor  117 . The transistors  115  and  117  are turned on. 
     The signal Sig 2  (high signal) is input to the gate of the transistor  104  and the gate of the transistor  109 . The transistors  104  and  109  are turned on. 
     The signal IN (high signal) is input to one of the source and the drain of the transistor  101 . The node  130  is set to high level. Since the transistor  117  is on, the high signal is input to the gate of the transistor  107 , and the transistor  107  is turned off. Since the transistor  109  is on, the high signal is input to the gate of the transistor  108 . As a result, the transistor  108  is turned on, and the output is set to low level. 
     Since the transistor  115  is on, the low signal is input to the gate of the transistor  102 , and the transistor  102  is turned on. Since the transistor  104  is on, the low signal is input to the gate of the transistor  103 , and the transistor  103  is turned off. The node  130  is set to high level. 
     Next, the transistor  101  is turned off by the signal Sig 1 . Since the transistor  102  is on and the transistor  103  is off at this time, the node  130  is supplied with the voltage VDD and remains at high level. On the other hand, since the transistor  107  is off and the transistor  108  is on, the output is supplied with the voltage VSS 1  and remains at low level. 
     Then, the transistors  104 ,  109 ,  115 , and  117  are turned off by the signal Sig 2 . The transistor  102  remains on because the low signal is supplied to the gate of the transistor  102 . The transistor  103  remains off because the low signal is supplied to the gate of the transistor  103 . The transistor  107  remains off because the high signal is supplied to the gate of the transistor  107 . The transistor  108  remains on because the high signal is supplied to the gate of the transistor  108 . 
     Assuming that the voltage VDD, the voltage VSS 1 , and the voltage VSS 2  are temporarily lowered or interrupted at time t 1 , the states held at the node  130  and the output are lost. At this time, the transistors  104 ,  109 ,  115 , and  117  are off owing to the signal Sig 2 . Since the off-state current of the transistors  104 ,  109 ,  115 , and  117  is extremely low, the transistors  102  and  108  are kept on and the transistors  103  and  107  are kept off. 
     Then, if the voltage VDD, the voltage VSS 1 , and the voltage VSS 2  are recovered at time t 2 , since the transistor  108  is on, the output is supplied with the voltage VSS 1  and set to low level. 
     Accordingly, the state of the output is recovered. 
     This embodiment can be combined with any other embodiment as appropriate. 
     Embodiment 10 
       FIG. 24  illustrates a semiconductor device  380 . The semiconductor device  380  is a shift register. Although  FIG. 24  illustrates the semiconductor device  380  including semiconductor devices  370  to  373 , the semiconductor device  380  includes at least the semiconductor devices  370  and  371 . The semiconductor device  370  is the semiconductor device illustrated in  FIG. 18 . The semiconductor devices  371  to  373  have the same configuration as the semiconductor device  370 . That is, the semiconductor device  380  has a structure in which the semiconductor devices  370  are connected in series. Alternatively, the semiconductor device  380  may have a structure in which the semiconductor devices  374 , the semiconductor devices  375 , or the semiconductor devices  376  are connected in series. 
     The signal IN and the signal Sig 1  are input to the semiconductor device  370 , and a signal OUT 1  is output from the semiconductor device  370 . The signal OUT 1  and the signal Sig 3  are input to the semiconductor device  371 , and a signal OUT 2  is output from the semiconductor device  371 . The signal OUT 2  and the signal Sig 1  are input to the semiconductor device  372 , and a signal OUT 3  is output from the semiconductor device  372 . The signal OUT 3  and the signal Sig 3  are input to the semiconductor device  373 , and a signal OUT 4  is output from the semiconductor device  373 . 
       FIG. 25  illustrates the semiconductor device  370  and the semiconductor device  371 , and  FIG. 26  illustrates the semiconductor device  372  and the semiconductor device  373 . The semiconductor devices  371  to  373  have the same configuration as the semiconductor device  370 . 
     The semiconductor device  371  includes a transistor  201 , a transistor  202 , a transistor  203 , a transistor  204 , a capacitor  205 , a transistor  207 , a transistor  208 , a transistor  209 , and a capacitor  210 . In the transistors  204  and  209 , an oxide semiconductor layer includes a channel formation region. Thus, even if power supply is interrupted in the semiconductor device  371 , the state of an output can be recovered. Note that the capacitors  205  and  210  are provided as needed. 
     A gate of the transistor  204  and a gate of the transistor  209  are electrically connected to the wiring  112 . The signal Sig 2  is input to the gate of the transistor  204  and the gate of the transistor  209 . 
     The semiconductor device  372  includes a transistor  301 , a transistor  302 , a transistor  303 , a transistor  304 , a capacitor  305 , a transistor  307 , a transistor  308 , a transistor  309 , and a capacitor  310 . In the transistors  304  and  309 , an oxide semiconductor layer includes a channel formation region. Thus, even if power supply is interrupted in the semiconductor device  372 , the state of an output can be recovered. Note that the capacitors  305  and  310  are provided as needed. 
     A gate of the transistor  304  and a gate of the transistor  309  are electrically connected to the wiring  112 . The signal Sig 2  is input to the gate of the transistor  304  and the gate of the transistor  309 . 
     The semiconductor device  373  includes a transistor  401 , a transistor  402 , a transistor  403 , a transistor  404 , a capacitor  405 , a transistor  407 , a transistor  408 , a transistor  409 , and a capacitor  410 . In the transistors  404  and  409 , an oxide semiconductor layer includes a channel formation region. Thus, even if power supply is interrupted in the semiconductor device  373 , the state of an output can be recovered. Note that the capacitors  405  and  410  are provided as needed. 
     A gate of the transistor  404  and a gate of the transistor  409  are electrically connected to the wiring  112 . The signal Sig 2  is input to the gate of the transistor  404  and the gate of the transistor  409 . 
     An example of the operation of the semiconductor device  380  will be described.  FIG. 27  is a timing chart. 
     First, the operation of the semiconductor device  370  will be described. At time t 0 , the signal IN makes a low to high transition. 
     At time t 1 , the signal Sig 1  makes a low to high transition. The transistor  101  is turned on. 
     At time t 1 , the signal Sig 2  makes a low to high transition. The transistors  104  and  109  are turned on. 
     The transistor  108  is turned on, and the signal OUT 1  (low) is output. 
     At time t 2 , the signal Sig 1  makes a high to low transition. The transistor  101  is turned off. However, the high state of the node  130  is maintained because the transistor  102  is on. Further, the signal OUT 1  (low) is output because the transistor  108  is on. 
     The signal Sig 2  makes a high to low transition between time t 2  and time t 3 . The transistors  104  and  109  are turned off. However, since the off-state current of the transistor  109  is extremely low, the transistor  108  remains on and the signal OUT 1  (low) is output. Note that like the signal Sig 1 , the signal Sig 2  may make a high to low transition at time t 2 . In this case also, the transistor  108  remains on and the signal OUT 1  (low) is output because the off-state current of the transistor  109  is extremely low. Alternatively, the signal Sig 2  may remain high. 
     As will be described below, the signal Sig 2  becomes low when the voltage VDD, the voltage VSS 1 , and the voltage VSS 2  are temporarily lowered or interrupted. In other cases, the signal Sig 2  may remain high. 
     At time t 3 , the signal IN makes a high to low transition. Since the transistor  101  is off, the signal OUT 1  (low) remains unchanged. 
     At time t 5 , the signal Sig 1  makes a low to high transition. The transistor  101  is turned on. 
     At time t 5 , the signal Sig 2  makes a low to high transition. The transistors  104  and  109  are turned on. Note that the signal Sig 2  may remain high. 
     The transistor  107  is turned on, and the signal OUT 1  (high) is output. 
     At time t 6 , the signal Sig 1  makes a high to low transition. The transistor  101  is turned off. However, the low state of the node  130  is maintained because the transistor  103  is on. Further, the signal OUT 1  (high) is output because the transistor  107  is on. 
     The signal Sig 2  makes a high to low transition between time t 6  and time t 7 . The transistors  104  and  109  are turned off. The transistor  107  remains on and the signal OUT 1  (high) is output. Note that the signal Sig 2  may remain high. 
     Subsequently, from time t 7  to time t 11 , the semiconductor device  370  operates in a similar manner. 
     Next, the operation of the semiconductor device  371  will be described. At time t 3 , the signal Sig 3  makes a low to high transition. The transistor  201  is turned on. 
     At time t 3 , the signal Sig 2  makes a low to high transition. The transistors  204  and  209  are turned on. Note that the signal Sig 2  may remain high. 
     The transistor  207  is turned on, and the signal OUT 2  (high) is output. 
     At time t 4 , the signal Sig 3  makes a high to low transition. The transistor  201  is turned off. However, the low state of a node  230  is maintained because the transistor  203  is on. Further, the signal OUT 2  (high) is output because the transistor  207  is on. 
     The signal Sig 2  makes a high to low transition between time t 4  and time t 5 . The transistors  204  and  209  are turned off. However, since the off-state current of the transistor  204  is extremely low, the transistor  203  remains on and the low state of the node  230  is maintained as a result. Since the transistor  207  is on, the signal OUT 2  (high) is output. Note that the signal Sig 2  may remain high. 
     At time t 5 , the signal OUT 1  makes a low to high transition. Since the transistor  201  is off, the signal OUT 2  (high) remains unchanged. 
     At time t 7 , the signal Sig 3  makes a low to high transition. The transistor  201  is turned on. 
     At time t 7 , the signal Sig 2  makes a low to high transition. The transistors  204  and  209  are turned on. Note that the signal Sig 2  may remain high. 
     The transistor  208  is turned on, and the signal OUT 2  (low) is output. 
     At time t 8 , the signal Sig 3  makes a high to low transition. The transistor  201  is turned off. However, the high state of the node  230  is maintained because the transistor  202  is on. Further, the signal OUT 2  (low) is output because the transistor  208  is on. 
     Subsequently, from time t 9  to time t 11 , the semiconductor device  371  operates in a similar manner. 
     The operation of the semiconductor device  372  will be described. At time t 5 , the signal Sig 1  makes a low to high transition. The transistor  301  is turned on. 
     At time t 5 , the signal Sig 2  makes a low to high transition. The transistors  304  and  309  are turned on. Note that the signal Sig 2  may remain high. 
     The transistor  308  is turned on, and the signal OUT 3  (low) is output. 
     At time t 6 , the signal Sig 1  makes a high to low transition. The transistor  301  is turned off. However, the high state of a node  330  is maintained because the transistor  302  is on. Further, the signal OUT 3  (low) is output because the transistor  308  is on. 
     The signal Sig 2  makes a high to low transition between time t 6  and time t 7 . The transistors  304  and  309  are turned off. However, since the off-state current of the transistor  309  is extremely low, the transistor  308  remains on and the signal OUT 3  (low) is output. Note that the signal Sig 2  may remain high. 
     At time t 7 , the signal OUT 2  makes a high to low transition. Since the transistor  301  is off, the signal OUT 3  (low) remains unchanged. 
     At time t 9 , the signal Sig 1  makes a low to high transition. The transistor  301  is turned on. 
     At time t 9 , the signal Sig 2  makes a low to high transition. The transistors  304  and  309  are turned on. Note that the signal Sig 2  may remain high. 
     The transistor  307  is turned on, and the signal OUT 3  (high) is output. 
     At time t 10 , the signal Sig 1  makes a high to low transition. The transistor  301  is turned off. However, the low state of the node  330  is maintained because the transistor  303  is on. Further, the signal OUT 3  (high) is output because the transistor  307  is on. 
     The signal Sig 2  makes a high to low transition between time t 10  and time t 11 . The transistors  304  and  309  are turned off. The transistor  307  remains on and the signal OUT 3  (high) is output. Note that the signal Sig 2  may remain high. 
     Subsequently, the semiconductor device  372  operates in a similar manner. 
     Finally, the operation of the semiconductor device  373  will be described. At time t 7 , the signal Sig 3  makes a low to high transition. The transistor  401  is turned on. 
     At time t 7 , the signal Sig 2  makes a low to high transition. The transistors  404  and  409  are turned on. Note that the signal Sig 2  may remain high. 
     The transistor  407  is turned on, and the signal OUT 4  (high) is output. 
     At time t 8 , the signal Sig 3  makes a high to low transition. The transistor  401  is turned off. However, the low state of a node  430  is maintained because the transistor  403  is on. Further, the signal OUT 4  (high) is output because the transistor  407  is on. 
     The signal Sig 2  makes a high to low transition between time t 10  and time t 11 . The transistors  404  and  409  are turned off. However, since the off-state current of the transistor  404  is extremely low, the transistor  403  remains on and the low state of the node  430  is maintained as a result. Since the transistor  407  is on, the signal OUT 4  (high) is output. Note that the signal Sig 2  may remain high. 
     Subsequently, the semiconductor device  372  operates in a similar manner. 
     It is clear from  FIG. 27  that the timing of rise or fall is shifted sequentially from the signal IN to the signal OUT 1 , the signal OUT 2 , the signal OUT 3 , and the signal OUT 4 . 
     In the shift register of this embodiment, the signal Sig 2  becomes low when the voltage VDD, the voltage VSS 1 , and the voltage VSS 2  are temporarily lowered or interrupted. The transistors  104 ,  109 ,  204 ,  209 ,  304 ,  309 ,  404 , and  409  are turned off. 
     Since the off-state current of the transistors  104 ,  109 ,  204 ,  209 ,  304 ,  309 ,  404 , and  409  is extremely low, the transistors  103 ,  108 ,  203 ,  208 ,  303 ,  308 ,  403 , and  408  remain on or off. Then, when the voltage VDD, the voltage VSS 1 , and the voltage VSS 2  are recovered, the states of the signals OUT 1  to OUT 4  are recovered. 
     The signal Sig 2  becomes high after the signals OUT 1  to OUT 4  are recovered. 
     This embodiment can be combined with any other embodiment as appropriate. 
     Embodiment 11 
     An oxide semiconductor that can be used for a channel of the transistors in Embodiments 1 to 10 will be described. 
     A highly purified oxide semiconductor (purified OS) obtained by reduction of impurities such as moisture or hydrogen which serves as an electron donor (donor) and by reduction of oxygen defects is an intrinsic (i-type) semiconductor or a substantially i-type semiconductor. Thus, a transistor including a channel in a highly purified oxide semiconductor has extremely low off-state current and high reliability. 
     Specifically, various experiments can prove low off-state current of a transistor including a channel in a highly purified oxide semiconductor. For example, the off-state current of even an element having a channel width of 1×10 6  μm and a channel length of 10 μm can be less than or equal to the measurement limit of a semiconductor parameter analyzer, that is, less than or equal to 1×10 −13  A at a voltage between the source electrode and the drain electrode (a drain voltage) of 1 V to 10 V. In this case, it can be seen that off-state current standardized on the channel width of the transistor is lower than or equal to 100 zA/μm. In addition, the off-state current is measured using a circuit in which a capacitor and a transistor are electrically connected to each other and charge flowing into or from the capacitor is controlled by the transistor. In the measurement, a highly purified oxide semiconductor film is used for a channel formation region of the transistor, and the off-state current of the transistor is measured from a change in the amount of charge of the capacitor per unit time. As a result, it is found that when the voltage between the source electrode and the drain electrode of the transistor is 3 V, a lower off-state current of several tens of yoctoamperes per micrometer (yA/μm) is obtained. Consequently, the off-state current of the transistor in which a highly purified oxide semiconductor film is used for a channel formation region is much lower than that of a transistor including crystalline silicon. 
     Unless otherwise specified, in this specification, the off-state current of an n-channel transistor is a current that flows between a source and a drain when the potential of a gate is lower than or equal to 0 with the potential of the source as a reference potential while the potential of the drain is higher than those of the source and the gate. Moreover, in this specification, the off-state current of a p-channel transistor is a current that flows between a source and a drain when the potential of a gate is higher than or equal to 0 with the potential of the source as a reference potential while the potential of the drain is lower than those of the source and the gate. 
     An oxide semiconductor preferably contains at least indium (In) or zinc (Zn). The oxide semiconductor preferably contains, in addition to In and Zn, gallium (Ga), tin (Sn), hafnium (Hf), aluminum (Al), and/or zirconium (Zr) that serve as a stabilizer for reducing variations in electric characteristics of transistors using the oxide semiconductor. 
     Among the oxide semiconductors, unlike silicon carbide, gallium nitride, or gallium oxide, In—Ga—Zn-based oxide, In—Sn—Zn-based oxide, or the like has an advantage of high mass productivity because a transistor with favorable electrical characteristics can be formed by sputtering or a wet process. Further, unlike silicon carbide, gallium nitride, or gallium oxide, with the use of the In—Ga—Zn-based oxide, a transistor with favorable electrical characteristics can be formed over a glass substrate, and a larger substrate can be used. 
     As another stabilizer, one or more kinds of lanthanoid such as lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), or lutetium (Lu) may be contained. 
     As the oxide semiconductor, any of the following oxides can be used, for example: indium oxide, gallium oxide, tin oxide, zinc oxide, In—Zn-based oxide, Sn—Zn-based oxide, Al—Zn-based oxide, Zn—Mg-based oxide, Sn—Mg-based oxide, In—Mg-based oxide, In—Ga-based oxide, In—Ga—Zn-based oxide (also referred to as IGZO), In—Al—Zn-based oxide, In—Sn—Zn-based oxide, Sn—Ga—Zn-based oxide, Al—Ga—Zn-based oxide, Sn—Al—Zn-based oxide, In—Hf—Zn-based oxide, In—La—Zn-based oxide, In—Pr—Zn-based oxide, In—Nd—Zn-based oxide, In—Sm—Zn-based oxide, In—Eu—Zn-based oxide, In—Gd—Zn-based oxide, In—Tb—Zn-based oxide, In—Dy—Zn-based oxide, In—Ho—Zn-based oxide, In—Er—Zn-based oxide, In—Tm—Zn-based oxide, In—Yb—Zn-based oxide, In—Lu—Zn-based oxide, In—Sn—Ga—Zn-based oxide, In—Hf—Ga—Zn-based oxide, In—Al—Ga—Zn-based oxide, In—Sn—Al—Zn-based oxide, In—Sn—Hf—Zn-based oxide, and In—Hf—Al—Zn-based oxide. 
     Note that, for example, an In—Ga—Zn-based oxide means an oxide containing In, Ga, and Zn and there is no particular limitation on the ratio of In, Ga, and Zn. Further, the In—Ga—Zn-based oxide may contain a metal element other than In, Ga, and Zn. The In—Ga—Zn-based oxide has sufficiently high resistance when no electric field is applied thereto, so that off-state current can be sufficiently reduced. Moreover, the In—Ga—Zn-based oxide has high mobility. 
     For example, an In—Ga—Zn-based oxide with an atomic ratio of In:Ga:Zn=1:1:1 (=1/3:1/3:1/3) or In:Ga:Zn=2:2:1 (=2/5:2/5:1/5), or an oxide with an atomic ratio close to any of the above atomic ratios can be used. Alternatively, an In—Sn—Zn-based oxide with an atomic ratio of In:Sn:Zn=1:1:1 (=1/3:1/3:1/3), In:Sn:Zn=2:1:3 (=1/3:1/6:1/2), In:Sn:Zn=2:1:5 (=1/4:1/8:5/8) or an oxide with an atomic ratio close to any of the above atomic ratios may be used. 
     For example, with an In—Sn—Zn-based oxide, high mobility can be achieved relatively easily. However, even with an In—Ga—Zn-based oxide, mobility can be increased by reducing the defect density in the bulk. 
     A structure of an oxide semiconductor film is described below. 
     The oxide semiconductor film is classified roughly into a single-crystal oxide semiconductor film and a non-single-crystal oxide semiconductor film. The non-single-crystal oxide semiconductor film includes any of an amorphous oxide semiconductor film, a microcrystalline oxide semiconductor film, a polycrystalline oxide semiconductor film, a c-axis aligned crystalline oxide semiconductor (CAAC-OS) film, and the like. 
     The amorphous oxide semiconductor film has disordered atomic arrangement and no crystalline component. A typical example of the amorphous oxide semiconductor film is an oxide semiconductor film in which no crystal part exists even in a microscopic region, and the whole of the film is amorphous. 
     The microcrystalline oxide semiconductor film includes a microcrystal (also referred to as nanocrystal) with a size greater than or equal to 1 nm and less than 10 nm, for example. Thus, the microcrystalline oxide semiconductor film has a higher degree of atomic order than the amorphous oxide semiconductor film. Hence, the density of defect states of the microcrystalline oxide semiconductor film is lower than that of the amorphous oxide semiconductor film. 
     The CAAC-OS film is one of oxide semiconductor films including a plurality of crystal parts, and most of the crystal parts each fit inside a cube whose one side is less than 100 nm. Thus, there is a case where a crystal part included in the CAAC-OS film fits inside a cube whose one side is less than 10 nm, less than 5 nm, or less than 3 nm. The density of defect states of the CAAC-OS film is lower than that of the microcrystalline oxide semiconductor film. The CAAC-OS film is described in detail below. 
     In a transmission electron microscope (TEM) image of the CAAC-OS film, a boundary between crystal parts, that is, a grain boundary is not clearly observed. Thus, in the CAAC-OS film, a reduction in electron mobility due to the grain boundary is less likely to occur. 
     According to the TEM image of the CAAC-OS film observed in a direction substantially parallel to a sample surface (cross-sectional TEM image), metal atoms are arranged in a layered manner in the crystal parts. Each metal atom layer has a morphology reflected by a surface over which the CAAC-OS film is formed (hereinafter, a surface over which the CAAC-OS film is formed is referred to as a formation surface) or a top surface of the CAAC-OS film, and is arranged in parallel to the formation surface or the top surface of the CAAC-OS film. 
     On the other hand, according to the TEM image of the CAAC-OS film observed in a direction substantially perpendicular to the sample surface (plan TEM image), metal atoms are arranged in a triangular or hexagonal configuration in the crystal parts. However, there is no regularity of arrangement of metal atoms between different crystal parts. 
     From the results of the cross-sectional TEM image and the plan TEM image, alignment is found in the crystal parts in the CAAC-OS film. 
     A CAAC-OS film is subjected to structural analysis with an X-ray diffraction (XRD) apparatus. For example, when a CAAC-OS film including an InGaZnO 4  crystal is analyzed by an out-of-plane method, a peak appears frequently when the diffraction angle (2θ) is around 31°. This peak is derived from the (009) plane of the InGaZnO 4  crystal, which indicates that crystals in the CAAC-OS film have c-axis alignment, and that the c-axes are aligned in a direction substantially perpendicular to the formation surface or the top surface of the CAAC-OS film. 
     On the other hand, when the CAAC-OS film is analyzed by an in-plane method in which an X-ray enters a sample in a direction substantially perpendicular to the c-axis, a peak appears frequently when 2θ is around 56°. This peak is derived from the (110) plane of the InGaZnO 4  crystal. Here, analysis (φ scan) is performed under conditions where the sample is rotated around a normal vector of a sample surface as an axis (φ axis) with 2θ fixed at around 56°. In the case where the sample is a single-crystal oxide semiconductor film of InGaZnO 4 , six peaks appear. The six peaks are derived from crystal planes equivalent to the (110) plane. On the other hand, in the case of a CAAC-OS film, a peak is not clearly observed even when φ scan is performed with 2θ fixed at around 56°. 
     According to the above results, in the CAAC-OS film having c-axis alignment, while the directions of a-axes and b-axes are different between crystal parts, the c-axes are aligned in a direction parallel to a normal vector of a formation surface or a normal vector of a top surface. Thus, each metal atom layer arranged in a layered manner observed in the cross-sectional TEM image corresponds to a plane parallel to the a-b plane of the crystal. 
     Note that the crystal part is formed concurrently with deposition of the CAAC-OS film or is formed through crystallization treatment such as heat treatment. As described above, the c-axis of the crystal is aligned in a direction parallel to a normal vector of a formation surface or a normal vector of a top surface. Thus, for example, in the case where the shape of the CAAC-OS film is changed by etching or the like, the c-axis might not be necessarily parallel to a normal vector of a formation surface or a normal vector of a top surface of the CAAC-OS film. 
     The degree of crystallinity in the CAAC-OS film is not necessarily uniform. For example, in the case where crystal growth leading to the CAAC-OS film occurs from the vicinity of the top surface of the film, the degree of the crystallinity in the vicinity of the top surface is higher than that in the vicinity of the formation surface in some cases. Further, when an impurity is added to the CAAC-OS film, the crystallinity in a region to which the impurity is added is changed, and the degree of crystallinity in the CAAC-OS film varies depending on regions. 
     Note that when the CAAC-OS film with an InGaZnO 4  crystal is analyzed by an out-of-plane method, a peak of 2θ may also be observed at around 36°, in addition to the peak of 2θ at around 31°. The peak of 2θ at around 36° indicates that a crystal having no c-axis alignment is included in part of the CAAC-OS film. It is preferable that in the CAAC-OS film, a peak of 2θ appear at around 31° and a peak of 2θ do not appear at around 36°. 
     With the use of the CAAC-OS film in a transistor, change in electric characteristics of the transistor due to irradiation with visible light or ultraviolet light is small. Thus, the transistor has high reliability. 
     Note that an oxide semiconductor film may be a stacked film including two or more films of an amorphous oxide semiconductor film, a microcrystalline oxide semiconductor film, and a CAAC-OS film, for example. 
     For example, the CAAC-OS film is formed by sputtering with a polycrystalline metal oxide sputtering target. By collision of ions with the target, a crystal region included in the target may be separated from the target along an a-b plane; in other words, sputtered particles having a plane parallel to an a-b plane (flat-plate-like sputtered particle or pellet-like sputtered particle) may flake off from the target. In this case, the flat-plate-like sputtered particles reach a substrate while maintaining their crystal state, whereby the CAAC-OS film can be formed. 
     The CAAC-OS film is preferably deposited under the following conditions. 
     Decay of the crystal state due to impurities can be prevented by reducing the amount of impurities entering the CAAC-OS film during the deposition, for example, by reducing the concentration of impurities (e.g., hydrogen, water, carbon dioxide, and nitrogen) that exist in the deposition chamber or by reducing the concentration of impurities in a deposition gas. Specifically, a deposition gas with a dew point of −80° C. or lower, preferably −100° C. or lower is used. 
     By increasing the substrate temperature during the deposition, migration of a sputtered particle is likely to occur after the sputtered particle reaches a substrate surface. Specifically, the substrate temperature during the deposition ranges from 100° C. to 740° C., preferably from 200° C. to 500° C. By increasing the substrate temperature during the deposition, when the flat-plate-like sputtered particle reaches the substrate, migration occurs on the substrate surface; thus, a flat plane of the flat-plate-like sputtered particle is attached to the substrate. 
     It is preferable that the proportion of oxygen in the deposition gas be increased and the electric power be optimized in order to reduce plasma damage in the deposition. The proportion of oxygen in the deposition gas is 30 vol % or higher, preferably 100 vol %. 
     As an example of the target, an In—Ga—Zn-based oxide target is described below. 
     The polycrystalline In—Ga—Zn-based oxide target is made by mixing InO X  powder, GaO Y  powder, and ZnO Z  powder in a predetermined molar ratio, applying pressure, and performing heat treatment at a temperature of 1000° C. to 1500° C. Note that X, Y, and Z are each a given positive number. Here, the predetermined molar ratio of InO X  powder to GaO Y  powder and ZnO Z  powder is, for example, 2:2:1, 8:4:3, 3:1:1, 1:1:1, 4:2:3, or 3:1:2. The kinds of powder and the molar ratio for mixing powder can be determined as appropriate depending on the desired target. 
     Alkali metal is not an element included in an oxide semiconductor and thus is an impurity. Likewise, alkaline earth metal is an impurity when the alkaline earth metal is not a component of the oxide semiconductor. When an insulating film in contact with an oxide semiconductor layer is an oxide, Na, among the alkali metals, diffuses into the insulating film and becomes Na + . Further, in the oxide semiconductor layer, Na cuts or enters a bond between metal and oxygen which are components of the oxide semiconductor. As a result, the characteristics of the transistor deteriorate, for example, the transistor is placed in a normally-on state due to a negative shift of the threshold voltage or the mobility is decreased. In addition, the characteristics of transistors vary. Specifically, the measurement value of a Na concentration by secondary ion mass spectrometry is preferably 5×10 16  atoms/cm 3  or lower, further preferably 1×10 16  atoms/cm 3  or lower, still further preferably 1×10 15  atoms/cm 3  or lower. Similarly, the measurement value of a Li concentration is preferably 5×10 15  atoms/cm 3  or lower, further preferably 1×10 15  atoms/cm 3  or lower. Similarly, the measurement value of a K concentration is preferably 5×10 15  atoms/cm 3  or lower, further preferably 1×10 15  atoms/cm 3  or lower. 
     When metal oxide containing indium is used, silicon or carbon having higher bond energy with oxygen than indium might cut the bond between indium and oxygen, so that an oxygen vacancy may be formed. Accordingly, when silicon or carbon is contained in the oxide semiconductor layer, the electric characteristics of the transistor are likely to deteriorate as in the case of using alkali metal or alkaline earth metal. Thus, the concentrations of silicon and carbon in the oxide semiconductor layer are preferably low. Specifically, the carbon concentration or the silicon concentration measured by secondary ion mass spectrometry is 1×10 18  atoms/cm 3  or lower. In this case, the deterioration of the electric characteristics of the transistor can be prevented, so that the reliability of a semiconductor device can be improved. 
     A metal in the source electrode and the drain electrode might extract oxygen from the oxide semiconductor layer depending on a conductive material used for the source and drain electrodes. In such a case, a region of the oxide semiconductor layer in contact with the source electrode or the drain electrode becomes an n-type region due to the formation of an oxygen vacancy. 
     The n-type region serves as a source region or a drain region, resulting in a decrease in the contract resistance between the oxide semiconductor layer and the source electrode or the drain electrode. Accordingly, the formation of the n-type region increases the mobility and on-state current of the transistor, which achieves high-speed operation of a switch circuit using the transistor. 
     Note that the extraction of oxygen by a metal in the source electrode and the drain electrode is probably caused when the source and drain electrodes are formed by sputtering or when heat treatment is performed after the formation of the source and drain electrodes. 
     The n-type region is more likely to be formed when the source and drain electrodes are formed using a conductive material that is easily bonded to oxygen. Examples of such a conductive material include Al, Cr, Cu, Ta, Ti, Mo, and W. 
     The oxide semiconductor layer is not limited to a single-layer metal oxide film and may have a stacked structure of a plurality of metal oxide films. In a semiconductor film in which first to third metal oxide films are sequentially stacked, for example, the first metal oxide film and the third metal oxide film are each an oxide film which contains at least one of the metal elements contained in the second metal oxide film and whose lowest conduction band energy is closer to the vacuum level than that of the second metal oxide film by 0.05 eV or more, 0.07 eV or more, 0.1 eV or more, or 0.15 eV or more and 2 eV or less, 1 eV or less, 0.5 eV or less, or 0.4 eV or less. Further, the second metal oxide film preferably contains at least indium in order to increase the carrier mobility. 
     In the transistor including the above semiconductor film, when a voltage is applied to the gate electrode so that an electric field is applied to the semiconductor film, a channel region is formed in the second metal oxide film, whose energy at the bottom of the conduction band is the lowest. That is, since the third metal oxide film is provided between the second metal oxide film and a gate insulating film, a channel region can be formed in the second metal oxide film that is insulated from the gate insulating film. 
     Since the third metal oxide film contains at least one of the metal elements contained in the second metal oxide film, interface scattering is unlikely to occur at the interface between the second metal oxide film and the third metal oxide film. Thus, the movement of carriers is unlikely to be inhibited at the interface, which results in an increase in the field-effect mobility of the transistor. 
     If an interface level is formed at the interface between the second metal oxide film and the first metal oxide film, a channel region is formed also in the vicinity of the interface, which causes a change in the threshold voltage of the transistor. However, since the first metal oxide film contains at least one of the metal elements contained in the second metal oxide film, an interface level is unlikely to be formed at the interface between the second metal oxide film and the first metal oxide film. Accordingly, the above structure can reduce variations in the electrical characteristics of the transistor, such as the threshold voltage. 
     Further, it is preferable that a plurality of metal oxide films be stacked so that an interface level due to impurities existing between the metal oxide films, which inhibits carrier flow, is not formed at the interface between the metal oxide films. This is because if impurities exist between the stacked metal oxide films, the continuity of the lowest conduction band energy between the metal oxide films is lost, and carriers are trapped or disappear by recombination in the vicinity of the interface. By reducing impurities existing between the films, a continuous junction (here, particularly a U-shape well structure whose lowest conduction band energy is changed continuously between the films) is formed more easily than the case of merely stacking a plurality of metal oxide films that contain at least one common metal as a main component. 
     In order to form continuous junction, the films need to be stacked successively without being exposed to the air by using a multi-chamber deposition system (sputtering system) provided with a load lock chamber. Each chamber of the sputtering system is preferably evacuated to a high vacuum (to about 5×10 −7  Pa to 1×10 −4  Pa) by an adsorption vacuum pump such as a cryopump so that water and the like acting as impurities for the oxide semiconductor are removed as much as possible. Alternatively, a combination of a turbo molecular pump and a cold trap is preferably used to prevent back-flow of a gas from an exhaust system into a chamber. 
     Not only high vacuum evaporation in a chamber but also high purity of a sputtering gas is necessary to obtain a high-purity intrinsic oxide semiconductor. As an oxygen gas or an argon gas used as the sputtering gas, a gas that is highly purified to have a dew point of −40° C. or lower, preferably −80° C. or lower, more preferably −100° C. or lower is used, so that entry of moisture or the like into the oxide semiconductor film can be prevented as much as possible. 
     For example, the first metal oxide film and/or the third metal oxide film can be an oxide film that contains aluminum, silicon, titanium, gallium, germanium, yttrium, zirconium, tin, lanthanum, cerium, or hafnium at a higher atomic ratio than the second metal oxide film. Specifically, the first metal oxide film and/or the third metal oxide film is preferably an oxide film with a content of any of the above elements 1.5 times or more, preferably 2 times or more, further preferably 3 times or more that of the second metal oxide film in an atomic ratio. The above element is strongly bonded to oxygen and thus has a function of suppressing generation of oxygen vacancies in the oxide film. Accordingly, the first metal oxide film and/or the third metal oxide film can be an oxide layer in which oxygen vacancies are less likely to be generated than in the second metal oxide film. 
     Specifically, when both the second metal oxide film and the first or third metal oxide film are In-M-Zn-based oxide films and the atomic ratio of the first or third metal oxide film is In:M:Zn=x 1 :y 1 :z 1  and that of the second metal oxide film is In:M:Zn=x 2 :y 2 :z 2 , the atomic ratios are set so that y 1 /x 1  is larger than y 2 /x 2 . Note that the element M is a metal element whose bonding strength to oxygen is larger than that of In, and can be Al, Ti, Ga, Y, Zr, Sn, La, Ce, Nd, or Hf, for example. The atomic ratios are preferably set so that y 1 /x 1  is 1.5 times or more, preferably 2 times or more, further preferably 3 times or more y 2 /x 2 . Here, in the second metal oxide film, y 2  is preferably larger than or equal to x 2  because the transistor can have stable electrical characteristics. Note that the field-effect mobility of the transistor is reduced when y 2  is 3 times or more x 2 ; accordingly, y 2  is preferably smaller than 3 times x 2 . 
     The thickness of first metal oxide film and the third metal oxide film ranges from 3 nm to 100 nm, preferably from 3 nm to 50 nm. The thickness of the second metal oxide film ranges from 3 nm to 200 nm, preferably from 3 nm to 100 nm, further preferably from 3 nm to 50 nm. 
     In the three-layer semiconductor film, the first to third metal oxide films can be amorphous or crystalline. Note that the transistor can have stable electrical characteristics when the second metal oxide film where a channel region is formed is crystalline; therefore, the second metal oxide film is preferably crystalline. 
     Note that a channel formation region refers to a region of a semiconductor film of a transistor that overlaps with a gate electrode and is located between a source electrode and a drain electrode. Further, a channel region refers to a region through which current mainly flows in the channel formation region. 
     For example, when an In—Ga—Zn-based oxide film formed by sputtering is used as the first and third metal oxide films, a sputtering target that is In—Ga—Zn-based oxide containing In, Ga, and Zn at an atomic ratio of 1:3:2 can be used to deposit the first and third metal oxide films. The deposition conditions can be as follows, for example: an argon gas (flow rate: 30 sccm) and an oxygen gas (flow rate: 15 sccm) are used as the deposition gas; the pressure is 0.4 Pa; the substrate temperature is 200° C.; and the DC power is 0.5 kW. 
     Further, when the second metal oxide film is a CAAC-OS film, a sputtering target including polycrystalline In—Ga—Zn-based oxide containing In, Ga, and Zn at an atomic ratio of 1:1:1 is preferably used to deposit the second metal oxide film. The deposition conditions can be as follows, for example: an argon gas (flow rate: 30 sccm) and an oxygen gas (flow rate: 15 sccm) are used as the deposition gas; the pressure is 0.4 Pa; the substrate temperature is 300° C.; and the DC power is 0.5 kW. 
     Note that the end portions of the semiconductor film in the transistor may be tapered or rounded. 
     Also in the case where a semiconductor film including stacked metal oxide films is used in the transistor, a region in contact with the source electrode or the drain electrode may be an n-type region. Such a structure increases the mobility and on-state current of the transistor and achieves high-speed operation of a semiconductor device. Further, when the semiconductor film including the stacked metal oxide films is used in the transistor, the n-type region particularly preferably reaches the second metal oxide film part of which is to be a channel region, because the mobility and on-state current of the transistor are further increased and higher-speed operation of the semiconductor device is achieved. 
     Embodiment 12 
     An example of the semiconductor devices shown in Embodiments 1 to 11 will be described.  FIG. 28  illustrates an example of a cross-sectional structure of the transistor  103 , the transistor  104 , and the capacitor  105  included in the semiconductor device  100  illustrated in  FIG. 1 . 
     The channel of the transistor  104  is included in an oxide semiconductor layer.  FIG. 28  shows the case where the transistor  104  and the capacitor  105  are formed over the transistor  103  that has a channel formation region in a single crystal silicon substrate. 
     Note that an active layer in the transistor  103  can be an amorphous, microcrystalline, polycrystalline, or signal crystal semiconductor film of silicon, germanium, or the like. Alternatively, the transistor  103  may include an active layer containing an oxide semiconductor. In the case where all of the transistors include an active layer containing an oxide semiconductor, the transistor  104  is not necessarily stacked over the transistor  103 , and the transistors  103  and  104  may be formed in the same layer. 
     When the transistor  103  is formed using a thin silicon film, any of the following can be used, for example: amorphous silicon formed by sputtering or vapor phase growth such as plasma-enhanced CVD, polycrystalline silicon obtained by crystallization of amorphous silicon by laser irradiation, and single crystal silicon obtained by separation of a surface portion of a single crystal silicon wafer by implantation of hydrogen ions or the like into the silicon wafer. 
     Examples of a semiconductor substrate  1400  where the transistor  103  is formed are an n-type or p-type silicon substrate, germanium substrate, silicon germanium substrate, and compound semiconductor substrate (e.g., GaAs substrate, InP substrate, GaN substrate, SiC substrate, GaP substrate, GaInAsP substrate, and ZnSe substrate). As an example,  FIG. 28  shows the case where an n-type single crystal silicon substrate is used. 
     The transistor  103  is electrically isolated from other transistors by an element isolation insulating film  1401 . The element isolation insulating film  1401  can be formed by local oxidation of silicon (LOCOS), trench isolation, or the like. 
     Specifically, the transistor  103  includes impurity regions  1402  and  1403  that are formed in the semiconductor substrate  1400  and function as source and drain regions, a gate electrode  1404 , and a gate insulating film  1405  between the semiconductor substrate  1400  and the gate electrode  1404 . The gate electrode  1404  overlaps with a channel formation region formed between the impurity regions  1402  and  1403 , with the gate insulating film  1405  placed therebetween. 
     An insulating film  1409  is provided over the transistor  103 . Openings are formed in the insulating film  1409 . A wiring  1410  in contact with the impurity region  1402 , a wiring  1411  in contact with the impurity region  1403 , and a wiring  1412  electrically connected to the gate electrode  1404  are formed in the openings. 
     The wiring  1410  is electrically connected to a wiring  1415  over the insulating film  1409 . The wiring  1411  is electrically connected to a wiring  1416  over the insulating film  1409 . The wiring  1412  is electrically connected to a wiring  1417  over the insulating film  1409 . 
     An insulating film  1420  and an insulating film  1440  are formed to be stacked in this order over the wirings  1415  to  1417 . An opening is formed in the insulating films  1420  and  1440 . A wiring  1421  electrically connected to the wiring  1417  is formed in the opening. 
     In  FIG. 28 , the transistor  104  and the capacitor  105  are formed over the insulating film  1440 . 
     The transistor  104  includes, over the insulating film  1440 , a semiconductor film  1430  containing an oxide semiconductor; conductive films  1432  and  1433  that function as source and drain electrodes and are provided over the semiconductor film  1430 ; a gate insulating film  1431  over the semiconductor film  1430  and the conductive films  1432  and  1433 ; and a gate electrode  1434  that is provided over the gate insulating film  1431  and overlaps with the semiconductor film  1430  in the region between the conductive films  1432  and  1433 . Note that the conductive film  1433  is electrically connected to the wiring  1421 . 
     A conductive film  1435  is provided over the gate insulating film  1431  to overlap with the conductive film  1433 . A portion where the conductive films  1433  and  1435  overlap with each other with the gate insulating film  1431  placed therebetween functions as the capacitor  105 . 
     Although  FIG. 28  illustrates an example where the capacitor  105  is provided over the insulating film  1440  together with the transistor  104 , the capacitor  105  may be provided below the insulating film  1440  together with the transistor  103 . 
     An insulating film  1441  and an insulating film  1442  are formed to be stacked in this order over the transistor  104  and the capacitor  105 . An opening is formed in the insulating films  1441  and  1442 . A conductive film  1443  that is in contact with the gate electrode  1434  in the opening is provided over the insulating film  1441 . 
     In  FIG. 28 , the transistor  104  includes the gate electrode  1434  on at least one side of the semiconductor film  1430 . Alternatively, the transistor  104  may include a pair of gate electrodes with the semiconductor film  1430  placed therebetween. 
     In the case where the transistor  104  has a pair of gate electrodes with the semiconductor film  1430  therebetween, one of the gate electrodes may be supplied with a signal for controlling the on/off state of the transistor  104 , and the other of the gate electrodes may be supplied with a potential from another element. In this case, potentials with the same level may be supplied to the pair of gate electrodes, or a fixed potential such as the ground potential may be supplied only to the other of the gate electrodes. By controlling the level of a potential supplied to the other of the gate electrodes, the threshold voltage of the transistor can be controlled. 
     In  FIG. 28 , the transistor  104  has a single-gate structure in which one channel formation region corresponding to one gate electrode  1434  is provided. Alternatively, the transistor  104  may have a multi-gate structure in which a plurality of gate electrodes electrically connected to each other are provided and thus a plurality of channel formation regions are included in one active layer. 
     The semiconductor film  1430  is not limited to a single film of an oxide semiconductor and may be a stack including a plurality of oxide semiconductor films  FIG. 29A  illustrates a structural example of a transistor  1110 A in which the semiconductor film  1430  has a three-layer structure. 
     The transistor  1110 A illustrated in  FIG. 29A  includes the semiconductor film  1430  over an insulating film  820  or the like, conductive films  832  and  833  electrically connected to the semiconductor film  1430 , a gate insulating film  831 , and a gate electrode  834  provided over the gate insulating film  831  so as to overlap with the semiconductor film  1430 . 
     In the transistor  1110 A, as the semiconductor film  1430 , oxide semiconductor layers  830   a  to  830   c  are stacked in this order from the insulating film  820  side. 
     The oxide semiconductor layers  830   a  and  830   c  are each an oxide film that contains at least one of metal elements contained in the oxide semiconductor layer  830   b . The energy at the bottom of the conduction band of the oxide semiconductor layers  830   a  and  830   c  is closer to a vacuum level than that of the oxide semiconductor layer  830   b  by 0.05 eV or more, 0.07 eV or more, 0.1 eV or more, or 0.15 eV or more and 2 eV or less, 1 eV or less, 0.5 eV or less, or 0.4 eV or less. The oxide semiconductor layer  830   b  preferably contains at least indium in order to increase carrier mobility. 
     As illustrated in  FIG. 29B , part of the oxide semiconductor layer  830   c  may be placed over the conductive films  832  and  833  to overlap with the gate insulating film  831 . 
     In order to fabricate a liquid crystal display device or an EL display device, a liquid crystal element or an EL element is formed over the insulating film  1442 . 
     Embodiment 13 
     In this embodiment, a configuration of a CPU, which is a semiconductor device of one embodiment of the present invention, will be described. 
       FIG. 30  illustrates a configuration of the CPU of this embodiment. The CPU illustrated in  FIG. 30  mainly includes, over a substrate  900 , an arithmetic logic unit (ALU)  901 , an ALU controller  902 , an instruction decoder  903 , an interrupt controller  904 , a timing controller  905 , a register  906 , a register controller  907 , a bus interface (bus I/F)  908 , a rewritable ROM  909 , and a ROM interface (ROM I/F)  920 . The ROM  909  and the ROM I/F  920  may be provided over another chip. The CPU in  FIG. 30  is just an example in which the configuration is simplified, and actual CPUs have various configurations according to their intended purpose. 
     An instruction that is input to the CPU through the bus I/F  908  is input to the instruction decoder  903  and decoded therein, and then, input to the ALU controller  902 , the interrupt controller  904 , the register controller  907 , and the timing controller  905 . 
     The ALU controller  902 , the interrupt controller  904 , the register controller  907 , and the timing controller  905  perform various controls based on the decoded instruction. Specifically, the ALU controller  902  generates signals for controlling the operation of the ALU  901 . While the CPU is executing a program, the interrupt controller  904  judges an interrupt request from an external input/output device or a peripheral circuit on the basis of its priority or a mask state, and processes the request. The register controller  907  generates an address of the register  906 , and reads/writes data from/to the register  906  in accordance with the state of the CPU. 
     The timing controller  905  generates signals for controlling operation timings of the ALU  901 , the ALU controller  902 , the instruction decoder  903 , the interrupt controller  904 , and the register controller  907 . For example, the timing controller  905  is provided with an internal clock generator for generating an internal clock signal CLK 2  based on a reference clock signal CLK 1 , and supplies the clock signal CLK 2  to the above circuits. 
     This embodiment can be combined with any of the above embodiments as appropriate. 
     Embodiment 14 
     The semiconductor device of one embodiment of the present invention can be used for display devices, personal computers, and image reproducing devices provided with recording media (typically, devices that reproduce the content of recording media such as digital versatile discs (DVDs) and have displays for displaying the reproduced images). Other examples of electronic devices that can be equipped with the semiconductor device of one embodiment of the present invention are mobile phones, game machines including portable game consoles, portable information appliances, e-book readers, cameras such as video cameras and digital still cameras, goggle-type displays (head mounted displays), navigation systems, audio reproducing devices (e.g., car audio systems and digital audio players), copiers, facsimiles, printers, multifunction printers, automated teller machines (ATM), and vending machines.  FIGS. 31A to 31F  illustrate specific examples of such electronic devices. 
       FIG. 31A  illustrates a portable game console including a housing  5001 , a housing  5002 , a display portion  5003 , a display portion  5004 , a microphone  5005 , speakers  5006 , a control key  5007 , a stylus  5008 , and the like. Although the portable game console illustrated in  FIG. 31A  has the two display portions  5003  and  5004 , the number of display portions included in the portable game console is not limited to this. 
       FIG. 31B  illustrates a portable information appliance including a first housing  5601 , a second housing  5602 , a first display portion  5603 , a second display portion  5604 , a joint  5605 , an operation key  5606 , and the like. The first display portion  5603  is provided in the first housing  5601 , and the second display portion  5604  is provided in the second housing  5602 . The first housing  5601  and the second housing  5602  are connected to each other with the joint  5605 , and the angle between the first housing  5601  and the second housing  5602  can be changed with the joint  5605 . Images displayed on the first display portion  5603  may be switched in accordance with the angle at the joint  5605  between the first housing  5601  and the second housing  5602 . A display device with a position input function may be used as at least one of the first display portion  5603  and the second display portion  5604 . Note that the position input function can be added by providing a touch panel in a display device. Alternatively, the position input function can be added by providing a photoelectric conversion element called a photosensor in a pixel area of a display device. 
       FIG. 31C  illustrates a laptop including a housing  5401 , a display portion  5402 , a keyboard  5403 , a pointing device  5404 , and the like. 
       FIG. 31D  illustrates an electric refrigerator-freezer including a housing  5301 , a refrigerator door  5302 , a freezer door  5303 , and the like. 
       FIG. 31E  illustrates a video camera including a first housing  5801 , a second housing  5802 , a display portion  5803 , operation keys  5804 , a lens  5805 , a joint  5806 , and the like. The operation keys  5804  and the lens  5805  are provided in the first housing  5801 , and the display portion  5803  is provided in the second housing  5802 . The first housing  5801  and the second housing  5802  are connected to each other with the joint  5806 , and the angle between the first housing  5801  and the second housing  5802  can be changed with the joint  5806 . Images displayed on the display portion  5803  may be switched in accordance with the angle at the joint  5806  between the first housing  5801  and the second housing  5802 . 
       FIG. 31F  illustrates a passenger car including a car body  5101 , wheels  5102 , a dashboard  5103 , lights  5104 , and the like. 
     This application is based on Japanese Patent Application serial no. 2013-038087 filed with Japan Patent Office on Feb. 28, 2013, the entire contents of which are hereby incorporated by reference.