Patent Publication Number: US-2023154810-A1

Title: Semiconductor packages with shortened talking path

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application is a continuation application of and claims the priority benefit of a prior application Ser. No. 17/385,939, filed on Jul. 27, 2021. The prior application Ser. No. 17/385,939 is a continuation application of and claims the priority benefit of a prior application Ser. No. 16/572,612, filed on Sep. 17, 2019. The entirety of each of the above-mentioned patent applications is hereby incorporated by reference herein and made a part of this specification. 
    
    
     BACKGROUND 
     In recent years, the semiconductor industry has experienced rapid growth due to continuous improvement in integration density of various electronic components, e.g., transistors, diodes, resistors, capacitors, etc. For the most part, this improvement in integration density has come from successive reductions in minimum feature size, which allows more components to be integrated into a given area. 
     These smaller electronic components also require smaller packages that occupy less area than previous packages. Examples of the type of packages for semiconductors include quad flat pack (QFP), pin grid array (PGA), ball grid array (BGA), flip chips (FC), three-dimensional integrated circuits (3DICs), wafer level packages (WLPs), and package on package (PoP) devices. Some 3DICs are prepared by placing chips over chips on a semiconductor wafer level. The 3DICs provide improved integration density and other advantages, such as faster speeds and higher bandwidth, because of the decreased length of interconnects between the stacked chips. However, there are many challenges related to 3DICs. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG.  1 A  is a top view of a semiconductor package in accordance with some embodiments. 
         FIG.  1 B  is a cross-sectional view of a semiconductor package along the line I-I of  FIG.  1 A  in accordance with some embodiments. 
         FIG.  2 A  is a top view of a semiconductor package in accordance with some embodiments. 
         FIG.  2 B  is a cross-sectional view of a semiconductor package along the line I-I of  FIG.  2 A  in accordance with some embodiments. 
         FIG.  3 A  is a top view of a semiconductor package in accordance with some embodiments. 
         FIG.  3 B  is a cross-sectional view of a semiconductor package along the line I-I of  FIG.  3 A  in accordance with some embodiments. 
     
    
    
     DETAILED DESCRIPTION 
     The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below for the purposes of conveying the present disclosure in a simplified manner. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a second feature over or on a first feature in the description that follows may include embodiments in which the second and first features are formed in direct contact, and may also include embodiments in which additional features may be formed between the second and first features, such that the second and first features may not be in direct contact. In addition, the same reference numerals and/or letters may be used to refer to the same or similar parts in the various examples the present disclosure. The repeated use of the reference numerals is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. 
     Further, spatially relative terms, such as “beneath”, “below”, “lower”, “on”, “over”, “overlying”, “above”, “upper” and the like, may be used herein to facilitate the description of one element or feature&#39;s relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated  90  degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. 
       FIG.  1 A  is a top view of a semiconductor package in accordance with some embodiments, and  FIG.  1 B  is a cross-sectional view of a semiconductor package along the line I-I of  FIG.  1 A  in accordance with some embodiments. For simplicity and clarity of illustration, only few elements such as first and second dies, an integrated circuit, seal rings, bonding structures and conductive features are shown in the simplified top view of  FIG.  1 A , and these elements are not necessarily in the same plane. 
     Referring to FIGs. lA and  1 B, a first die  100 A and a second die  100 B are mounted onto the integrated circuit  200 . The first and second dies  100 A,  100 B may be the same type of dies or different types of dies. The first and second dies  100 A,  100 B may be an application-specific integrated circuit (ASIC) chip, an analog chip, a sensor chip, a wireless and radio frequency chip, a voltage regulator chip or a memory chip, for example. In some embodiments, the first and second dies  100 A,  100 B may be an active component or a passive component. In some embodiments, the first and second dies  100 A,  100 B include a semiconductor substrate  104 , an interconnect structure  110  and a plurality of bonding structures  120 ,  120 A,  120 B. 
     In some embodiments, the first and second dies  100 A,  100 B may be rectangular-shaped, and has four sides  102   a ,  102   b ,  102   c ,  102   d , for example. The sides  102   a ,  102   b ,  102   c ,  102   d  are connected to one another. The sides  102   a ,  102   c  are longer sides, and the sides  102   b ,  102   d  are shorter sides. The side  102   a  is opposite to and parallel to the side  102   c , and the side  102   b  is opposite to and parallel to the side  102   d . In some embodiments, a length of the sides  102   a ,  102   c  is 0.5 mm to 55 mm, for example. A length of the sides  102   b ,  102   d  is 0.5 mm to 55 mm, for example. In some embodiments, the side  102   a  of the first die  100 A faces to the side  102   a  of the second die  100 B. In some embodiments, the shortest distance D AB  between the die  100 A and the die  100 B is formed between the side  102   a  of the first die  100 A and the side  102   a  of the second die  100 B, which is also referred to as a die-to-die spacing. In some embodiments, the distance D AB  may be in a range of 10 μm to 100 μm, for example. 
     In some embodiments, the semiconductor substrate  104  includes an elementary semiconductor such as silicon or germanium and/or a compound semiconductor such as silicon germanium, silicon carbide, gallium arsenic, indium arsenide, gallium nitride or indium phosphide. In some embodiments, the semiconductor substrate  104  is a semiconductor-on-insulator (SOI) substrate. In some alternative embodiments, the semiconductor substrate  104  may take the form of a planar substrate, a substrate with multiple fins, nanowires, or other forms known to people having ordinary skill in the art. Depending on the requirements of design, the semiconductor substrate  104  may be a P-type substrate or an N-type substrate and may have doped regions therein. The doped regions may be configured for an N-type device or a P-type device. 
     In some embodiments, the semiconductor substrate  104  includes isolation structures defining at least one active area, and a device layer is disposed on/in the active area. The device layer includes a variety of devices. In some embodiments, the devices include active components, passive components, or a combination thereof. In some embodiments, the devices may include integrated circuits devices. The devices are, for example, transistors, capacitors, resistors, diodes, photodiodes, fuse devices, or other similar devices. In some embodiments, the device layer includes a gate structure, source/drain regions, spacers, and the like. 
     In some embodiments, a through substrate via  106  may be disposed in the semiconductor substrate  104 . In some embodiments, the through substrate via  106  is called “a through silicon via” when the semiconductor substrate  104  is a silicon-containing substrate. The through substrate via  106  is electrically connected to the interconnect structure  110  and the to-be-formed redistribution layer structure  304 . In some embodiments, the through substrate via  106  includes a conductive via. The conductive via includes copper, a copper alloy, aluminum, an aluminum alloy or a combination thereof. In some embodiments, the through substrate via  106  further includes a diffusion barrier layer between the conductive via and the semiconductor substrate  104 . The diffusion barrier layer includes Ta, TaN, Ti, TiN, CoW or a combination thereof. The through substrate via  106  penetrates the semiconductor substrate  104 , in other words, the through substrate via  106  is extended between two opposite surfaces of the semiconductor substrate  104 . In some embodiments, a dielectric layer  108  may be further formed over a surface (i.e., the back surface) of the semiconductor substrate  104 . The through substrate via  106  is extended into the dielectric layer  108  and exposed through the dielectric layer  108 . In some embodiments, a surface of the through substrate via  106  may be substantially coplanar with a surface of the dielectric layer  108 , for example. 
     The interconnect structure  110  is disposed over a surface (e.g., front surface) of the semiconductor substrate  104 . Specifically, the interconnect structure  110  is disposed over and electrically connected to the device layer. In some embodiments, the interconnect structure  110  includes at least one insulating layer  112  and a plurality of conductive features  114 ,  116 . The conductive features  114 ,  116  are disposed in the insulating layer  112  and electrically connected with each other. In some embodiments, the insulating layer  112  includes an inter-layer dielectric (ILD) layer on the semiconductor substrate  104 , and at least one inter-metal dielectric (IMD) layer over the inter-layer dielectric layer. In some embodiments, the insulating layer  112  includes silicon oxide, silicon oxynitride, silicon nitride, a low dielectric constant (low-k) material or a combination thereof. The insulating layer  112  may be a single layer or a multiple-layer structure. In some embodiments, the conductive features  114 ,  116  include plugs and metal lines. The plugs may include contacts formed in the inter-layer dielectric layer, and vias formed in the inter-metal dielectric layer. The contacts are formed between and in contact with a metal line and the device layer. The vias are formed between and in contact with two metal lines. The conductive features  114 ,  116  may include tungsten (W), copper (Cu), a copper alloy, aluminum (Al), an aluminum alloy or a combination thereof. In some embodiments, a barrier layer may be disposed between the conductive features  114 ,  116  and the insulating layer  112  to prevent the material of the conductive features  114 ,  116  from migrating to the underlying device layer. The barrier layer includes Ta, TaN, Ti, TiN, CoW or a combination thereof, for example. In some embodiments, the interconnect structure  110  is formed by a dual damascene process. In alternative embodiments, the interconnect structure  110  is formed by multiple single damascene processes. In yet alternative embodiments, the interconnect structure  110  is formed by an electroplating process. It is noted that although the interconnector structure  110  is shown as  FIG.  1 B , however, the disclosure is not limited thereto, in other words, the interconnector structure  110  may have other suitable configuration. 
     The bonding structures  120 ,  120 A,  120 B are disposed over the surface (e.g., front surface) of the interconnect structure  110  and disposed in at least one bonding dielectric layer  122 . In some embodiments, the bonding structures  120 A,  120 B are disposed along the side  102   a , and the bonding structures  120  may be arranged along the sides  102   b ,  102   c ,  102   d . A distance between the adjacent two bonding structures  120 ,  120 A,  120 B may be the same or different. In some embodiments, the bonding structure  120 ,  120 A,  120 B includes a bonding conductive feature such as a bonding pad  124   a  and/or a bonding via  124   b . The bonding via  124   b  is electrically connected to the interconnect structure  110 , and the bonding pad  124   a  is electrically connected to the bonding via  124   b . In some embodiments, the bonding dielectric layer  122  includes silicon oxide, silicon nitride, a polymer or a combination thereof. The bonding conductive feature may include tungsten (W), copper (Cu), a copper alloy, aluminum (Al), an aluminum alloy or a combination thereof. In some embodiments, a barrier layer may be disposed between the bonding conductive feature and the bonding dielectric layer  122 . The barrier layer includes Ta, TaN, Ti, TiN, CoW or a combination thereof, for example. In some embodiments, the bonding structure  120 ,  120 A,  120 B is formed by a dual damascene process. In some alternative embodiments, the bonding structure  120 ,  120 A,  120 B is formed by multiple single damascene processes. In some alternative embodiments, the bonding structure  120 ,  120 A,  120 B is formed by an electroplating process. 
     In some embodiments, the conductive feature  116  is physically and electrically connected to the bonding structure  120 A,  120 B. Specifically, the conductive feature  116  is in contact with the bonding via  124   b  of the bonding structure  120 A,  120 B, and the bonding via  124   b  is disposed between the bonding pad  124   a  and the conductive feature  116 . In some embodiments, the bonding structure  120 A,  120 B may be extended in a first direction (i.e., a stack direction of the first and second dies  100 A,  100 B onto the integrated circuit  200 ), and the conductive feature  116  may be extended in a second direction (i.e., a arranging direction of the first die  100 A and the second die  100 A) substantially perpendicular to the first direction. In some embodiments, the conductive feature  116  further electrically connects the bonding structures  120 ,  120 A or the bonding structures  120 ,  120 B. In some embodiments, the conductive feature  116  are included in the interconnect structure  110 , however, the invention is not limited thereto. For example, in some alternative embodiments, the conductive feature  116  may be other conductive feature disposed in the semiconductor substrate  104 , the bonding dielectric layer  122  or other suitable sites and in direct contact with the bonding structure  120 A,  120 B. 
     In some embodiments, the first and second dies  100 A,  100 B further include seal rings  130 A,  130 B. The seal ring  130 A,  130 B is disposed over the surface (e.g., front surface) of the semiconductor substrate  104 . Specifically, the seal ring  130 A,  130 B is disposed over and electrically insulated from the device layer, and located aside the interconnect structure  110 . In some embodiments, the seal ring  130 A,  130 B is continuously disposed at the sides  102   a ,  102   b ,  102   c ,  102   d , for example. As shown in  FIG.  1 A , the seal ring  130 A,  130 B has a ring shape or any suitable shape from a top view. In some embodiments, the bonding structures  120 A,  120 B are disposed within and surrounded by the seal ring  130 A,  130 B. 
     In some embodiments, the seal ring  130 A of the first die  100 A has a portion  132 A and a portion  134 A, and the portion  132 A and the portion  134 A are physically connected. Similarly, the seal ring  130 B of the second die  100 B has a portion  132 B and a portion  134 B, and the portion  132 B and the portion  134 B are physically connected. In some embodiments, the portion  132 A,  132 B is disposed at the side  102   a , and the portion  134 A,  134 B is disposed at the sides  102   b ,  102   c ,  102   d . In some embodiments, the portion  132 A,  132 B may be line-shaped and elongated along the side  102   a . The portion  134 A,  134 B may be U-shaped and continuously disposed along the sides  102   b ,  102   c ,  102   d . The first portion  132 A of the first die  100 A is disposed adjacent to the side  102   a.    
     In some embodiments, the shortest distance D 1   A , D 1   B  between the bonding structure  120 A,  120 B and the portion  132 A,  132 B is the distance between the outermost edge of the bonding pad  124   a  and the innermost edge of the portion  132 A,  132 B. In some embodiments, the distance D 1   A , D 1   B  may be in a range of 20 μm to 100 μm, for example. In some embodiments, the shortest distance D 2   A , D 2   B  between the portion  132 A,  132 B and the side  102   a  may be in a range of 5 μm to 100 μm, for example. In some embodiments, the distance D 2   A , D 2   B  is also the width of the remained silicon after silicon singulation. In some embodiments, the shortest distance (not shown) between the seal ring  130 A,  130 B and each side  102   a ,  102   b ,  102   c ,  102   d  may be substantially the same, for example. 
     In some embodiments, the portion  132 A,  132 B has a uniform width W 1   A , W 1   B , and the portion  134 A,  134 B has a uniform width W 2   A , W 2   B . The width W 1   A , W 1   B  of the portion  132 A,  132 B is smaller than the width W 2   A , W 2   B  of the portion  134 A,  134 B. That is, a portion of the seal ring  130 A,  130 B (i.e., the portion  132 A,  132 B) is narrowed at the side  102   a . In some embodiments, the width W 1   A  is smaller than the width W 2   A  by at least 5 μm, and the width W 1   B  is smaller than the width W 2   B  by at least 5 μm, for example. In some embodiments, the width W 1   A , W 1   B  may be in a range of 5 μm to 45 μm, and the width W 2   A , W 2   B  may be in a range of 10 μm to 50 μm. In some embodiments, the portion  132 A,  132 B and the portion  134 A,  134 B may be formed simultaneously. 
     Herein, when elements are described as “at substantially the same level”, the elements are formed at substantially the same height in the same layer, or having the same positions embedded by the same layer. In some embodiments, the elements at substantially the same level are formed from the same material(s) with the same process step(s). In some embodiments, the surfaces of the elements at substantially the same level are substantially coplanar. For example, as shown in  FIG.  1 B , the seal ring  130 A,  130 B is at substantially the same level with the interconnect structure  110 . In detail, the seal ring  130 A,  130 B may include a plurality of conductive features  136  such as conductive lines and plugs between the conductive lines. The conductive features  136  of the seal ring  130 A,  130 B are at substantially the same level with the conductive features  114 ,  116  of the interconnect structure  110 . 
     In some embodiments, a region R A , R B  is defined as being between the side  102   a  and the outermost edge of the interconnect structure  110  (i.e., the outermost edge of the conductive features  114 ,  116 ). When an element (such as the portion  132 A,  132 B of the seal ring  130 A,  130 B) is disposed in the region R A , R B , a space for the element is required, and a distance between the conductive feature  116  and the side  102   a  is increased. Furthermore, since the bonding structure  120 A,  120 B is physically connected to and disposed over the conductive feature  116 , a distance between the bonding structure  120 A,  120 B (i.e., the outermost edge of the bonding pad  124   a ) and the side  102   a  is also increased. 
     Still referring to  FIG.  1 A and  1 B , the integrated circuit  200  may be an application-specific integrated circuit (ASIC) chip, an analog chip, a sensor chip, a wireless and radio frequency chip, a voltage regulator chip or a memory chip, for example. The integrated circuit  200  and the first and second dies  100 A,  100 B may be the same type of dies or different types of dies. In some embodiments, the integrated circuit  200  may be an active component or a passive component. In some embodiments, the integrated circuit  200  is larger than a total area of the first and second dies  100 A,  100 B. In some embodiments, the size of the integrated circuit  200  is larger than the size of the first and second dies  100 A,  100 B. Herein, the term “size” is referred to the length, width and/or area. 
     In some embodiments, the integrated circuit  200  includes a semiconductor substrate  204 , an interconnect structure  210 , a plurality of bonding structures  220  and a plurality of conductive features  216 . 
     The interconnect structure  210  is similar to the interconnect structure  110 . Similarly, the interconnect structure  210  is disposed over a surface (e.g., front surface) of the semiconductor substrate  204 . Specifically, the interconnect structure  210  is disposed over and electrically connected to the device layer. In some embodiments, the interconnect structure  210  includes at least one insulating layer  212  and a plurality of conductive features  214 ,  216 . The conductive features  214 ,  216  are disposed in the insulating layer  212  and electrically connected with each other. A portion of the conductive features, such as the outermost conductive features  216 , are exposed by the insulating layer  212 . 
     The bonding structure  220  is similar to the bonding structure  120 A,  120 B. Similarly, the bonding structure  220  is disposed over the surface (e.g., front surface) of the interconnect structure  210 . In some embodiments, the bonding structure  220  is disposed in at least one bonding dielectric layer  222  and includes a bonding conductive feature such as a bonding pad  224   a  and/or a bonding via  224   b . The bonding via  224   b  is electrically connected to the interconnect structure  210 , and the bonding pad  224   a  is electrically connected to the bonding via  224   b.    
     In some embodiments, the first and second dies  100 A,  100 B and the integrated circuit  200  are face-to-face bonded together with the bonding structures  120 A,  120 B and the bonding structures  220 . In some embodiments, before the first and second dies  100 A,  100 B are bonded to the integrated circuit  200 , the bonding structures  120 A,  120 B and the bonding structures  220  are aligned, such that the bonding pads  124   a  are bonded to the bonding pads  224   a  and the bonding dielectric layer  122  is bonded to the bonding dielectric layer  222 . In some embodiments, the alignment of the bonding structure  120 A,  120 B and the bonding structure  220  may be achieved by using an optical sensing method. After the alignment is achieved, the bonding structure  120 A,  120 B and the bonding structure  220  are bonded together by a hybrid bonding including a metal-to-metal bonding and a dielectric-to-dielectric bonding. 
     After the first and second dies  100 A,  100 B are bonded to the integrated circuit  200 , the first and second dies  100 A,  100 B are electrically connected to the integrated circuit  200 , respectively. In addition, the conductive feature  216  electrically connects the first die  100 A and the second die  100 B directly. Specifically, the conductive feature  216  electrically and physically connects the bonding structure  220  bonded to the bonding structure  120 A of the first die  100 A and the bonding structure  220  bonded to the bonding structure  120 B of the second die  100 B. In some embodiments, the terminals of the conductive feature  216  are physically connected to the bonding vias  224   b  bonded to the bonding structures  120 A,  120 B of the first and second dies  100 A,  100 B. The bonding via  224   b  is disposed between the bonding pads  224   a  and the conductive feature  216 . The conductive feature  216  is elongated between the bonding structure  120 A of the first die  100 A and the bonding structure  120 B of the second die  100 B. In some embodiments, the bonding structure  220  may be extended in a first direction (i.e., a stack direction of the first and second dies  100 A,  100 B onto the integrated circuit  200 ), and the conductive feature  216  may be extended in a second direction (i.e., a arranging direction of the first die  100 A and the second die  100 B) substantially perpendicular to the first direction. In some embodiments, the conductive feature  216  are the outermost conductive feature of the interconnect structure  210 , however, the invention is not limited thereto. For example, in some alternative embodiments, the conductive feature  216  may be other conductive feature disposed in the semiconductor substrate  204 , the bonding dielectric layer  222  or other suitable sites. In addition, the conductive feature  216  may be also referred to as a connecting feature or a bridge structure. 
     In some embodiments, the portion  132 A,  132 B of the seal ring  130 A,  130 B may be extended in a first direction parallel to the side  102   a , and the conductive feature  216  may be extended in a second direction substantially perpendicular to the side  102   a , for example. Accordingly, as shown in  FIG.  1 A , from a top view, the conductive feature  216  may be partially overlapped with the portion  132 A,  132 B of the seal ring  130 A,  130 B, to form an overlapped region OPR A , OPR B . In some embodiments, the conductive features  216  are substantially parallel to one another, for example. In some embodiments, the conductive features  216  may be parallel to the sides  102   a ,  102   c  (such as short sides) of the first and second dies  100 A,  100 B, for example. 
     In some embodiments, the conductive feature  216  may be line-shaped, for example. A pitch of the conductive feature  216  may be in a range of 0.04 μm to 5 μm, for example. In some embodiments, the conductive feature  216  may include tungsten (W), copper (Cu), a copper alloy, aluminum (Al), an aluminum alloy or a combination thereof. In some embodiments, a barrier layer may be disposed between the conductive feature  216  and the insulating layer  212 . The barrier layer includes Ta, TaN, Ti, TiN, CoW or a combination thereof, for example. In some embodiments, the conductive feature  216  is formed by a dual damascene process. In some alternative embodiments, the conductive feature  216  is formed by multiple single damascene processes. In some alternative embodiments, the conductive feature  216  is formed by an electroplating process. 
     In some embodiments, the conductive feature  216  electrically connects the bonding structures  120 A,  120 B which are nearest to each other. Therefore, the conductive feature  216  provides the shortest conductive path between the corresponding bonding structures  120 A,  120 B. Accordingly, the first die  100 A and the second die  100 B may be talked to each other efficiently, that is, the conductive feature  216  provides a die-to-die talking path TP. In some embodiments, the conductive feature  216  is disposed across the portion  132 A of the seal ring  130 A, the spacing between the first die  100 A and the second die  100 B, and the portion  132 B of the seal ring  130 B. Therefore, a length of the die-to-die talking path TP is substantially equal to a total of the distance D 1 A between the portion  132 A and the bonding structure  120 A of the first die  100 A, the width W 1 A of the portion  132 A, the distance D 2 A between the portion  132 A and the side  102   a  of the first die  100 A, the distance DAB between the sides  102   a  of the first and second dies  100 A,  100 B, the distance D 1 B between the portion  132 B and the side  102   a  of the second die  100 B, the width W 1 B of the portion  132 B and the distance D 2 B between the portion  132 B and the bonding structure  120 B of the second die  100 B. In some embodiments, the distance D 1 A, D 2 A may depend on the process window of the photolithography or the requirement of insulation between the conductive elements. The distance DAB may depend on the gap-filling capacity of the encapsulant. In some embodiments, by narrowing the portion  132 A,  132 B of the seal ring  130 A,  130 B, the width W 1 A, W 1 B is reduced. Accordingly, the die-to-die talking path TP may be shortened. In some embodiments, the length of the die-to-die talking path TP may be equal to or less than 70 μm, for example. Furthermore, since the width W 1 A, W 1 B of the portion  132 A,  132 B of the seal ring  130 A,  130 B at the side  102   a  is smaller than the width W 2 A, W 2 B of the portion  134 A,  134 B of the seal ring  130 A,  130 B at other side  102   b ,  102   c ,  102   d , the distance between the bonding structure  120 A and the side  102   a  is smaller than a distance between the bonding structure  120  and other side  102   b ,  102   c ,  102   d . For example, the distance (i.e., a total of the distance D 1 A, the width W 1 A and the distance D 2 A) between the bonding structure  120 A and the side  102   a  is smaller than a distance D 3  between the bonding structure  120  and the side  102   a.    
     In some embodiments, since the outermost edge of the bonding pad  124   a  of the bonding structure  120 A,  120 B is disposed inside the outermost edge of the conductive feature  116 , an additional distance is formed between the outermost edge of the bonding pad  124   a  and the outermost edge of the conductive feature  116 . Therefore, the shortest distance D 1   A , D 1   B  between the bonding structure  120 A,  120 B and the portion  132 A,  132 B is larger than the shortest distance D 4  between the conductive feature  116  and the portion  132 A,  132 B. In some embodiments, the distance D 4  is in a range of 20 μm to 100 μm. However, in some alternative embodiments, the bonding structure  120 A,  120 B may be disposed closer to the portion  132 A,  132 B, for example, the outermost edge of the bonding structure  120 A,  120 B may be substantially flush with the outermost edge of the conductive feature  116 . Thus, the additional distance is not required. Accordingly, the shortest distance D 1   A , D 1   B  may be reduced, and the length of the die-to-die talking path TP is shortened. 
     In some embodiments, an encapsulant  302 , a redistribution layer structure  304 , a plurality of pads  310  and a passivation layer  312  are further included in a semiconductor package  1  of  FIG.  1 B . In some embodiments, the semiconductor package  1  may be a high performance multi-die package which requires extremely short talking path, for example. 
     The encapsulant  302  is disposed over the integrated circuit  200  and aside the first and second dies  100 A,  100 B. Specifically, the encapsulant  302  surrounds sides  102   a ,  102   b ,  102   c ,  102   d  of the first and second dies  100 A,  100 B, exposes tops of the first and second dies  100 A,  100 B and overlays the surface (e.g., front surface) of the integrated circuit  200 . In some embodiments, the surfaces (e.g., back surfaces) of the first and second dies  100 A,  100 B are substantially coplanar with the top surface of the encapsulant  302 . In some embodiments, the encapsulant  302  includes a molding compound. The molding compound may include a resin and a filler. In alternative embodiments, the encapsulant  302  includes silicon oxide, silicon nitride or a combination thereof. The encapsulant  302  may be formed by spin-coating, lamination, deposition or the like. 
     In some alternative embodiments, a plurality of through dielectric vias may be disposed in the encapsulant  302  and electrically connected with the interconnect structure  210  and the to-be-formed redistribution layer structure  304 . In some embodiments, the through dielectric vias include conductive vias. The conductive vias include copper, a copper alloy, aluminum, an aluminum alloy or a combination thereof. In some embodiments, the through dielectric vias further include a diffusion barrier layer between the conductive vias and the encapsulant  302 . The diffusion barrier layer includes Ta, TaN, Ti, TiN, CoW or a combination thereof. 
     The redistribution layer structure  304  is disposed over the surfaces (e.g., back surfaces) of the first and second dies  100 A,  100 B and over the encapsulant  302 . The redistribution layer structure  304  includes at least one dielectric layer  306  and at least one conductive layer  308  stacked alternately. In some embodiments, a portion of the redistribution layer structure  304  is electrically connected to the through silicon vias  106 . In some embodiments, another portion of the redistribution layer structure  304  may be electrically connected to the through dielectric vias, to electrically connect the integrated circuit  200 . In some embodiments, the dielectric layer  306  includes a photo-sensitive material such as polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), a combination thereof or the like. In some embodiments, the conductive layer  308  includes copper, nickel, titanium, a combination thereof or the like. 
     The pads  310  are disposed over the redistribution layer structure  304 . In some embodiments, the pads  310  are under bump metallization (UBM) pads. The pads  310  include a metal or a metal alloy. The pads  310  includes aluminum, copper, nickel, or an alloy thereof. 
     The passivation layer  312  covers the dielectric layer  306  and edge portions of the pads  310 , and exposes the center portions of the pads  310 . In some embodiments, the passivation layer  312  includes silicon oxide, silicon nitride, benzocyclobutene (BCB) polymer, polyimide (PI), polybenzoxazole (PBO) or a combination thereof. 
     The conductive connectors  314  are mounted to the pads  310 . In some embodiments, the conductive connectors  314  may be ball grid array (BGA) connectors, solder balls, metal pillars, and/or the like. The conductive connectors  314  may be formed by a mounting process and a reflow process, for example. 
     In some embodiments, a portion of the seal ring adjacent to another die has a narrower width than other portions of the seal ring. Therefore, the space for the portion of the seal ring may be reduced, and the bonding structure may become closer to another die. Therefore, the talking path between the bonding structures of the adjacent dies may be shortened, and the performance of the semiconductor package may be improved. 
       FIG.  2 A  is a top view of a semiconductor package in accordance with some embodiments, and  FIG.  2 B  is a cross-sectional view of a semiconductor package along the line I-I of  FIG.  2 A  in accordance with some embodiments. For simplicity and clarity of illustration, only few elements such as first and second dies, an integrated circuit, seal rings, bonding structures and conductive features are shown in the simplified top view of  FIG.  2 A , and these elements are not necessarily in the same plane. 
     The semiconductor package  2  of  FIGS.  2 A and  2 B  is similar to the semiconductor package  1  of FIGs. lA and  1 B. Thus, the difference between the semiconductor package  2  and the semiconductor package  1  is illustrated in details below and the similarity between them is not iterated herein. 
     Referring to  FIGS.  2 A and  2 B , the semiconductor package  2  includes a first die  100 A, a second die  100 B and an integrated circuit  200 . The first die  100 A and the second die  100 B are bonded to the integrated circuit  200 . In some embodiments, bonding structures  120 A of the first die  100 A are bonded to bonding structures  220  of the integrated circuit  200 , and bonding structures  120 B of the second die  100 B are bonded to bonding structure  220  of the integrated circuit  200 . In addition, a conductive feature  216  of the integrated circuit  200  electrically connects the bonding structures  220 , so as to electrically connect the first die  100 A and the second die  100 B. 
     In some embodiments, the first and second dies  100 A,  100 B have seal rings  130 A,  130 B. In some embodiments, the seal ring  130 A,  130 B is merely disposed at the sides  102   b ,  102   c ,  102   d , for example. The seal ring  130 A,  130 B may be continuously disposed along the sides  102   b ,  102   c ,  102   d . In other words, no seal ring is disposed at the side  102   a . Specifically, no seal ring is disposed in a region R A , R B  between the side  102   a  and the conductive feature  116  connected to the bonding structure  120 A,  120 B. In other words, the region R A , R B  is a seal ring-free region. Therefore, as shown in  FIG.  2 A , from a top view, the seal ring  130 A,  130 B is not overlapped with the conductive feature  216 . In some embodiments, the seal ring  130 A,  130 B may be U-shaped, for example. 
     In some embodiments, since no seal ring or any other component of the die is disposed in the region RA, RB between the side  102   a  and the conductive feature  116  connected to the bonding structure  120 A,  120 B, the space for the seal ring or any other component is not required. In some embodiments, there is merely dielectric layer (i.e., the insulating layer  112 ) in the region RA, RB, for example. Accordingly, a die-to-die talking path TP is substantially equal to a total of a distance DA between the bonding structure  120 A and the side  102   a  of the first die  100 A, a distance DAB between the first die  100 A and the second die  100 B and a distance DB between the bonding structure  120 B and the side  102   a  of the second die  100 B. The distance DA, DB between the bonding structure  120 A,  120 B and the side  102   a  is smaller than a distance (such as a distance D 3 ) between the bonding structure  120  and other side  102   b ,  102   c ,  102   d . In some embodiments, the distance DA, DB between the bonding structure  120 A,  120 B and the side  102   a  of the first and second dies  100 A,  100 B depends on the process window of the photolithography or singulation or placement process of the first and second dies  100 A,  100 B. In some embodiments, the distance DA, DB may be in a range of 25 μm to 200 μm, for example. In some embodiments, the distance DAB may be in a range of 10 μm to 100 μm, for example. In some embodiments, the length of the die-to-die talking path may be reduced to 60 μm or more, for example. In some embodiments, by removing a portion of the seal ring between the bonding structure and the side adjacent to another die, the talking path between the dies may be shortened. 
     In some alternative embodiments, the bonding structure  120 A,  120 B may be disposed closer to the outermost edge of the conductive feature  116 , for example, the outermost edge of the bonding structure  120 A,  120 B may be substantially flush with the outermost edge of the conductive feature  116 . Accordingly, the distance D A , D B  may be further reduced, and the length of the die-to-die talking path TP may be shorter. 
       FIG.  3 A  is a top view of a semiconductor package in accordance with some embodiments, and  FIG.  3 B  is a cross-sectional view of a semiconductor package along the line I-I of  FIG.  3 A  in accordance with some embodiments. For simplicity and clarity of illustration, only few elements such as first and second dies, an integrated circuit, bonding structures and conductive features are shown in the simplified top view of  FIG.  3 A , and these elements are not necessarily in the same plane. 
     The semiconductor package  3  of  FIGS.  3 A and  3 B  is similar to the semiconductor package  1  of FIGs. lA and  1 B. Thus, the difference between the semiconductor package  3  and the semiconductor package  1  is illustrated in details below and the similarity between them is not iterated herein. 
     Referring to  FIGS.  3 A and  3 B , the semiconductor package  3  includes a first die  100 A, a second die  100 B and an integrated circuit  200 . The first die  100 A and the second die  100 B are bonded to the integrated circuit  200 . In some embodiments, bonding structures  120 A of the first die  100 A are bonded to bonding structures  220  of the integrated circuit  200 , and bonding structures  120 B of the second die  100 B are bonded to bonding structure  220  of the integrated circuit  200 . In addition, a conductive feature  216  of the integrated circuit  200  electrically connects the bonding structures  220 , so as to electrically connect the first die  100 A and the second die  100 B. 
     In some embodiments, there is no seal ring in the first and second dies  100 A,  100 B. In other words, the region R A , R B  is a seal ring-free region, and the first and second dies  100 A,  100 B may be seal ring-free dies. Accordingly, no seal ring is disposed in a region R A , R B  between the side  102   a  and a conductive feature  116  connected to the bonding structure  120 A,  120 B. 
     In some embodiments, since no seal ring or any other component of the die is disposed in the region RA, RB between the side  102   a  and the conductive feature  116 , the space for the seal ring or any other component is not required. In some embodiments, there is merely dielectric layer (i.e., the insulating layer  112 ) in the region RA, RB, for example. Accordingly, a die-to-die talking path TP is substantially equal to a total of a distance DA between the bonding structure  120 A and the side  102   a  of the first die  100 A, a distance DAB between the first die  100 A and the second die  100 B and a distance DB between the bonding structure  120 B and the side  102   a  of the second die  100 B. The distance DA, DB between the bonding structure  120 A,  120 B and the side  102   a  is substantially equal to a distance (such as a distance D 3 ) between the bonding structure  120  and other side  102   b ,  102   c ,  102   d . 
     In some embodiments, the distance D A , D B  between the bonding structure  120 A,  120 B and the side  102   a  of the first and second dies  100 A,  100 B depends on the process window of the photolithography or singulation or placement process of the first and second dies  100 A,  100 B. In some embodiments, the distance D A , D B  may be in a range of 25 μm to 200 μm, for example. In some embodiments, the distance D AB  may be in a range of 10 μm to 100 μm, for example. In some embodiments, the length of the die-to-die talking path may be reduced to 60 μm or more, for example. In some embodiments, by providing the seal ring-free dies, the talking path between the dies may be shortened. 
     In some alternative embodiments, the bonding structure  120 A,  120 B may be disposed closer to the outermost edge of the conductive feature  116 , for example, the outermost edge of the bonding structure  120 A,  120 B may be substantially flush with the outermost edge of the conductive feature  116 . Accordingly, the distance D A , D B  may be further reduced, and the length of the die-to-die talking path TP may be shorter. 
     In above embodiments, the first die  100 A and the second die  100 B adopt the same technique to reduce the distance between the bonding structure  120 A,  120 B and the side  102   a , however, the invention is not limited thereto. In some alternative embodiments, the first die  100 A and the second die  100 B may adopt different technique to reduce the distance between the bonding structure  120 A,  120 B and the side  102   a . For example, in some alternative embodiments, a first die may be selected from the first dies  100 A in  FIGS.  1 A to  3 B  or the like, and a second die may be selected from the second dies  100 B in  FIGS.  1 A to  3 B  or the like. In addition, although there are two adjacent dies (i.e., the first die and the second die) illustrated, more than two dies may be bonded to the integrated circuit. 
     In view of the above, the space for the element may be reduced or eliminated by narrowing the width of the element (such as a seal ring), removing a portion of the element (such as a seal ring) or totally removing the element (such as a seal ring) from the die. Therefore, the bonding structure of one die may become closer to the bonding structure of another die. Accordingly, the talking path between the bonding structures of the adjacent dies may be shortened, and the performance of the semiconductor package may be improved. 
     In accordance with some embodiments of the present disclosure, a semiconductor package includes an integrated circuit, a first die and a second die. The first die includes a first bonding structure and a first seal ring. The first bonding structure is bonded to the integrated circuit and disposed at a first side of the first die. The second die includes a second bonding structure. The second bonding structure is bonded to the integrated circuit and disposed at a first side of the second die. The first side of the first die faces the first side of the second die. A first portion of the first seal ring is disposed between the first side and the first bonding structure, and a width of the first portion is smaller than a width of a second portion of the first seal ring. 
     In accordance with alternative embodiments of the present disclosure, a semiconductor package includes an integrated circuit, a first die and a second die. The integrated circuit includes a conductive feature. The first die includes a first bonding structure and a first seal ring. The first bonding structure is bonded to the integrated circuit and disposed at a first side of the first die. The second die includes a second bonding structure. The second bonding structure is bonded to the integrated circuit and disposed at a first side of the second die. The first side of the first die faces the first side of the second die. The conductive feature is disposed between and electrically connected to the first bonding structure and the second bonding structure, and the first seal ring is not overlapped with the conductive feature from a top view. 
     In accordance with yet alternative embodiments of the present disclosure, a semiconductor package includes an integrated circuit, a first die and a second die. The first die includes a first bonding structure and a first conductive feature at a first side of the first die. The first bonding structure is bonded to the integrated circuit and disposed between the integrated circuit and the first conductive feature. The first conductive feature is physically connected to the first bonding structure. The second die includes a second bonding structure at a first side of the second die. The second bonding structure is bonded to the integrated circuit, and the first side of the first die faces the first side of the second die. A region between the first conductive feature and the first side of the first die is a seal ring-free region. 
     In accordance with yet alternative embodiments of the present disclosure, a forming method of a semiconductor package includes the following steps. A first die is provided. The first die includes a first bonding structure and a first seal ring, the first bonding structure is formed at a first side of the first die, a first portion of the first seal ring is formed between the first side and the first bonding structure, and a width of the first portion is smaller than a width of a second portion of the first seal ring. A second die is provided. The second die includes a second bonding structure. The first die and the second die are bonded onto an integrated circuit through the first bonding structure and the second bonding structure. 
     In accordance with yet alternative embodiments of the present disclosure, a forming method of a semiconductor package includes the following steps. A first die is provided, and the first die includes a first bonding structure at a first side of the first die and a first seal ring. A second die is provided, and the second die includes a second bonding structure at a first side of the second die. The first die and the second die are bonded onto an integrated circuit through the first bonding structure and the second bonding structure. After bonding, the first side of the first die faces the first side of the second die, and the first seal ring is not overlapped with a conductive feature of the integrated circuit from a top view. 
     In accordance with yet alternative embodiments of the present disclosure, a forming method of a semiconductor package includes the following steps. An integrated circuit is provided, and the integrated circuit includes a first bonding structure, a second bonding structure and a conductive bridge connecting and being in direct contact with the first bonding structure and the second bonding structure. A first die is provided, and the first die includes a third bonding structure and a seal ring. A second die is provided, and the second die includes a fourth bonding structure. The first die and the second die are bonded onto the integrated circuit through bonding the first bonding structure and the third bonding structure and bonding the second bonding structure and the fourth bonding structure. After bonding, there is no seal ring overlapped with the conductive bridge from a top view. 
     In accordance with yet alternative embodiments of the present disclosure, a semiconductor package includes a first die. The first die has a first side and a second side different from the first side and includes a first seal ring. The first seal ring includes a first portion at the first side and a second portion at the second side, and a width of the first portion is smaller than a width of the second portion. 
     In accordance with yet alternative embodiments of the present disclosure, a semiconductor package includes a first die and a second die. The first die includes a first seal ring. The first die and the second die are disposed along a horizontal direction and electrically connected to each other, a first side of the first die faces the second die, and the first seal ring is not disposed at the first side of the first die. 
     In accordance with yet alternative embodiments of the present disclosure, a semiconductor package includes a first die, a second die and a conductive bridge. The first die includes a first seal ring. The first die and the second die are disposed along a horizontal direction. The conductive bridge extends between the first die and the second die along the horizontal direction, to electrically connect the first die and the second die, and the first seal ring is not overlapped with the conductive bridge from a top view. 
     Other features and processes may also be included. For example, testing structures may be included to aid in the verification testing of the 3D packaging or 3DIC devices. The testing structures may include, for example, test pads formed in a redistribution layer or on a substrate that allows the testing of the 3D packaging or 3DIC, the use of probes and/or probe cards, and the like. The verification testing may be performed on intermediate structures as well as the final structure. Additionally, the structures and methods disclosed herein may be used in conjunction with testing methodologies that incorporate intermediate verification of known good dies to increase the yield and decrease costs. 
     The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.