Patent Publication Number: US-6665845-B1

Title: System and method for topology based noise estimation of submicron integrated circuit designs

Description:
CROSS REFERENCE TO RELATED PATENT APPLICATIONS 
     The present application is a continuation-in-part of U.S. patent application Ser No. 09/528,667 filed on Mar. 20, 2000. The parent application, U.S. patent application Ser. No. 09/528,667, is itself a continuation-in-part of U.S. patent application Ser. No. 09/513,161, filed on Feb. 25, 2000. Both Ser. Nos. 09/513,161 and 09/528,667 are assigned to Sun Microsystems, Inc., assignee of the present invention. The present invention is related to the subject matter disclosed in U.S. patent application Ser. Nos. 09/513,545 filed on Feb. 25, 2000 and assigned to Sun Microsystems, Inc., assignee of the present invention, the disclosure of which is herein specifically incorporated by this reference. 
    
    
     FIELD OF THE INVENTION 
     The present invention relates, to the field of noise analysis models for use in designing digital integrated circuits (“ICs”). More particularly, the present invention relates to a hierarchical use of a two pole time-gated model of coupling noise of particular utility in analyzing submicron integrated circuit designs to detect or prevent problems due to noise voltages from coupling between various circuit components. 
     BACKGROUND OF THE INVENTION 
     A major factor in the design of high-speed digital circuits is the inevitable parasitic resistances and capacitances that degrade circuit performance. It is known that accurate modeling of digital circuit performance requires that parasitic resistances and capacitances be considered. Software is available from vendors including Cadence Design Systems and Avant!, for extracting the total capacitance, including parasitic capacitances, on nodes of an integrated circuit and for estimating the effect of this capacitance on circuit speed. 
     Parasitic resistances, capacitances, and inductances are also known to couple noise onto individual nodes of an integrated circuit by coupling signals between adjacent circuit elements. The undesired coupling of signals between adjacent elements is known as crosstalk. 
     Although digital circuits are inherently resistant to noise, the scaling of supply voltages and metal oxide semiconductor field effect transistor (“MOSFET”) threshold voltages has resulted in modern submicron designs having lower noise margins than typical of earlier designs. Most complementary metal oxide semiconductor (“CMOS”) circuits continue to have considerable immunity to power supply and substrate noise even at the submicron level. However, the effect of capacitive coupling noise has become a major concern for designers of deep sub-micron circuits. 
     A good noise detection tool must not only pick out the noise problems on chip, but also be useable on large datasets such as those of ten to twenty million or more transistor integrated circuit designs. Since noise on any given digital circuit is either a problem or it is not, the exact amount of noise induced is not as great a concern to the digital designer, as it is to know whether the induced noise crosses a threshold of potential failure for that net. 
     The scaling of transistor sizes in digital integrated circuits has also led to the shrinking of wire dimensions. A proportionate scaling (shrinking) of the wire thickness would result in an increasing of wire resistance. To avoid this increase in resistance, the scale factor for the wire thickness has usually been much smaller than the scale factor for horizontal dimensions including wire-to-wire spacing. Further, the space between wires is also reduced by the scaling factor. Hence, the coupling capacitance per unit length between minimally spaced adjacent nodes is greater on modern submicron processes than it is with earlier CMOS digital integrated circuit processes. 
     Interconnect layers in modern multilayer-metal integrated circuits tend to be designed such that wires on a given layer of metal are generally routed orthogonal to those on an adjacent layer. This orthogonality results in many relatively small parasitic capacitances to circuit elements on the adjacent layers, the noise contribution of these parasitic capacitances is minimal because the contributions of many of these small capacitances tend to cancel each other. 
     All these factors contribute to a relative increase per unit length in capacitance to neighboring wires and a decrease in the capacitance to the relatively quiet planes above and below the wire. This leads to an increase in the coupling coefficient of a given wire to adjacent wires. In addition, the reduction of the vertical wire dimension, albeit smaller than the scaling factor, and the shrinking of the horizontal wire dimension according to the scale factor, result in an increase in wire resistance that also aggravates the noise situation. 
     The increased coupling coefficients and wire resistances contribute to much larger noise voltages being induced in deep sub-micron designs than seen in previous generations. These voltages can push digital gates into the amplifying region of their transfer characteristic, turning traditionally noise-rejecting gates into noise amplifying stages. Induced noise voltages can create several different problems on the chip. Of these, designers are most concerned with the detection of faulty logic transitions triggered by noise, especially irrevocable logic transitions, such as the firing of a precharged dynamic gate or corruption of data in a storage element. 
     Noise voltages and spikes cannot be easily measured on silicon since probing a given net greatly alters its coupling coefficient because of the immense capacitance of the probe. In addition, it is far preferable that parasitic and noise effects be evaluated through pre-tapeout simulation rather than through debugging after wafer fabrication. 
     Noise problems typically are a function of the data set, the testing frequency and process variations. Large test vector sets are needed to increase the probability that the chip reaches a condition where the effect of coupling noise can be seen during simulation. 
     A good noise detection methodology can and must ensure that a large and complex chip, such as a modern microprocessor, can be produced and tested without significant delay or cost being added in the noise detection steps. 
     A. Noise Effects on Chip 
     Noise on any given net in the chip can have one or more of the following effects: 
     Data loss or metastability in latches, flip-flops or other storage elements. This can result from a noise spike on a clock, reset, set, or latch enable input or from a noise spike on a data input coincident with a clock transition; 
     Faulty logic transitions, including transitions in dynamic logic gates. Dynamic logic gates may be viewed as a combination of logic and storage elements; 
     Speed changes leading to setup or hold time violations due to the Miller effect, when the aggressor (the line or lines that induce noise in neighboring lines) and the victim (the line or lines that have noise induced therein) switch in opposite directions; 
     Substrate bounce due to current injection into the substrate, when voltage excursions due to noise are above or below the supply level; and 
     Extra power dissipation due to propagated glitches. 
     It is essential to prevent data loss in latches and flip-flops, and faulty logic transitions in dynamic logic, lest functionality be compromised. The effects on power are typically less significant, while speed changes can be accounted for by guardbanding standard timing tools and by designing the underlying circuits accordingly. The most crucial requirement of a noise detection tool is that it prevents data loss or corruption in storage elements and data corruption due to faulty logic transitions. 
     The problem of incorrect data stored in storage elements can be subdivided into two categories; frequency dependent noise (wherein a change of clock frequency causes the noise pulse to occur outside the sampling period of the storage element and therefore work correctly at a different frequency); and frequency independent noise (wherein a change of frequency does not shift the noise pulse relative to the sampling period and the error occurs at many frequencies). 
     B. Requirements of a Noise Detection Strategy 
     To guarantee function, a noise detection strategy should ensure that all frequency independent noise problems are detected such that they may be eliminated and the chip can be guaranteed to work at some frequency. 
     A tighter criterion is that the strategy should guarantee the chip will work at the target frequency and all lower frequencies. Whatever tool is used, the tool should detect both frequency independent and frequency dependent noise problems that may cause functional failure at the target frequency. 
     A third, stricter, criterion that may be applied in a conservative design, is to prevent all faulty logic transitions induced by coupled noise. 
     To verify large devices, of the order of a million transistors or more, it is necessary that circuit modeling be done with a tool that is faster and less memory intensive than those which construct full-circuit matrix equations, as does the circuit simulator SPICE. SPICE is well known to those of skill in the art. 
     A noise detection tool should also allow for sensitivity analysis on the circuit parameters. This enables designers to run “what if” analysis on suspect wires during design and redesign. For example, analysis may be repeated for a process minimum and a process maximum of metal line-to-line or layer-to-layer spacing, or for a typical, versus a minimum, enhancement device threshold. 
     It is also desirable that errors in a coupling-noise detection tool err on the side of pessimism rather than on the side of optimism, i.e., it is better to use a conservative model. This is because, while pessimistic or conservative analysis may result in some degree of extra labor in design of an integrated circuit, the resulting design can be guaranteed to work. In contrast, an optimistic analysis may result in undetected problems remaining in a design. 
     Most integrated circuit designs are subjected to repeated analysis to detect design rule violations and circuit speed problems during the design process. It is also known that typical large integrated circuit layouts have large numbers of parasitic capacitances. Extraction of all capacitances and resistances, and their reduction for modeling, of a large integrated circuit therefore requires considerable computer time. It is desirable that this computer time be minimized. 
     SUMMARY OF THE INVENTION 
     In accordance with the principles of the invention, a high capacity noise analysis tool is created for analyzing potential noise coupling in submicron integrated circuit designs. One embodiment of the invention uses a two-pole model of coupling. This embodiment is a program product operational on a digital computer permitting it to analyze large numbers of aggressor and victim wires. 
     According to the principles of the invention, the speed of analysis is enhanced by combining multiple aggressors into single aggressors for analysis, and by performing a hierarchical analysis. 
     According to the invention, the speed of analysis is optionally further boosted through topology-based parameter estimation for the two-pole coupling model. In this embodiment, topology-based parameter estimates are used with the two-pole model of coupling to generate a list of wires that have potential for noise problems. This list may be examined by the user, or may be reexamined by the tool of the invention with more precisely calculated circuit parameters. 
    
    
     The aforementioned and other features and objects of the present invention, and the manner of attaining them, will become more apparent, and the invention itself will be best understood, by reference to the following description of the invention in conjunction with the accompanying drawings. 
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 a  is a sectional illustration of the relative dimensions of minimum width metal lines, or wires, on previous generations of CMOS processes; 
     FIG. 1 b  is an illustration of the relative dimensions of minimum width metal lines, or wires, on current generation CMOS processes; 
     FIG. 2 a  is a circuit diagram illustrating how a frequency dependant coupled noise can disrupt data in a data storage element; 
     FIG. 2 b  is a circuit diagram illustrating how a frequency independent coupled noise can disrupt data in a data storage element; 
     FIG. 3 is a circuit diagram of a model that is used to model coupling noise between circuit elements according to the principles of one embodiment of the present invention; 
     FIG. 4 is a comparison of a coupling noise waveform produced by the two-pole model of one embodiment of the present invention and a SPICE simulation of coupling using a more detailed model; 
     FIG. 5 is an illustration of the event timing windows used to account for non-simultaneous coupling-noise sources according to the principles of one embodiment of the present invention; 
     FIG. 6 is a flow chart of the noise analysis process; 
     FIG. 7 is a schematic diagram of the two-pole noise model applied to a hierarchical netlist; 
     FIG. 8 is a schematic diagram of a library model of a gate for use with a hierarchical gate-level netlist; 
     FIG. 9 is a schematic diagram of the resistances and capacitances of a signal line as represented in an extracted netlist; 
     FIG. 10 is a schematic diagram of the resistances and capacitances of a signal line as reduced according to the principles of one embodiment of the present invention prior to computing coupled noise; and 
     FIG. 11 is a portion of an integrated circuit layout showing the traversal window scanned for a particular wire according to the principles of one embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION 
     Reduction of typical feature dimensions to the submicron range has resulted in the aspect ratio of the wires being changed as shown from that of FIG. 1 a  to that of FIG. 1 b  after scaling. Typically, the width  100  of a metal line  101  (FIG. 1 a ) at the micron level of process is shrunk by a scale factor to a narrower width  102  for a metal line  103  (FIG. 1 b ) when fabricated on a deep submicron process. Similarly, the line spacing  105  (FIG. 1 a ) is shrunk by the scale factor to a narrower line spacing  106  (FIG. 1 b ), while the line thickness or height  110  (FIG. 1 a ) stays substantially constant  111  (FIG. 1 b ). The dielectric thickness  112  and  113  also remains substantially constant between micron (FIG. 1 a ) and submicron (FIG. 1 b ) processes. 
     Consider the flip-flop in FIG. 2 a , where coupling noise is injected from a neighboring line to the flip-flop input. Assuming the aggressor signal  203  on line  200  (FIG. 2 a ) changes just before the rising edge of the clock signal on line  201 , the noise pulse  205  on the victim line  202  then occurs during the setup period of flip-flop  204 . This results in an incorrect value being stored in  204 . However, if the frequency is lowered, the signal  203  on line  200  arrives early relative to the clock signal on line  201 , and the noise pulse  205  on the victim line  202  then occurs earlier than, and ends before, the setup or sampling period of the flip-flop  204 . This is frequency dependent noise, since any failure vanishes at lower frequency. 
     If we consider the flip-flop  210  in FIG. 2 b , the noise pulse  225  is now caused by coupling with the output of another flip-flop  211  which we assume gets an early (skewed) clock signal on line  212  relative to the clock at flip-flop  210 . At least some degree of clock skew is inevitable on modern submicron digital integrated circuits. It is now possible that the noise pulse  225  caused by aggressor signal  223  on line  221  occurs on victim line  215  during the sampling or setup period of flip-flop  210 . Since the aggressor signal  223  on line  221  moves with the rising clock edge, no matter how much the frequency is reduced, the noise pulse  225  most likely remains during the sampling period of flip-flop  210  and so results in an incorrect value being stored in flip-flop  210 . This is frequency independent noise-induced data corruption, since it does not change with the frequency. 
     Noise on dynamic gates that results in the firing of the victim gate (loss of precharged voltage on the gate) is most often frequency independent noise, since dynamic gates cannot recover from a wrong transition regardless of the operating frequency. Dynamic logic is commonly used even at the submicron level in design of on-chip memory circuits, among other places. 
     To simplify analysis, it has been found possible to guarantee that noise does not propagate through amplifying stages by setting a low threshold for tolerable noise on a net. This makes noise on each net a function of its neighbors and itself, independent of noise from earlier logic stages. While pessimistic, this approach guarantees function. 
     Circuit Model 
     In the interest of high analysis speed, a simplified circuit model as shown in FIG. 3, is used to model the crosstalk. Referring to FIG. 3, we model the victim line as a single pi segment resistance/capacitance (“RC”) circuit. Capacitances to effective ground  300  and  301 , and coupling capacitances  302  and  303 , are lumped at the beginning and end of the victim line resistance  305 . An inherent assumption of this model is that the coupling capacitance and ground capacitance are uniformly distributed throughout the wire. The victim line is assumed to hold its value by way of a transistor or group of transistors in the linear region of operation, modeled as a single equivalent resistor  320 ; representing the ON resistance of the transistors, the value of which may be determined from the device geometries and circuit configuration. 
     For the Nth aggressor, A N , the model assumes a ramp with a fixed slope, Vdd/Tr, that is rising or falling from time O to time Tr. The rise time, Tr, is estimated from the circuit parameters, including the equivalent resistance of the transistors and ground capacitances  310 , on the aggressor side  312  of the coupling capacitances. Since this is a simple 2-pole circuit, it can be solved to give the voltage at X by the following relationship,                        Relationship                 1     _                     
              Vx        (   t   )       =       P                        k     1   t           +     Q                        2   t     k       +       Cc   ·     (     Rd   +     Rw   2       )       Tr         ,       0   ≤   t   ≤     Tr                 and        
          Vx        (   t   )           =       (       P                        1   Tr     k       +     Q                        k     2   Tr           +       Cc   ·     (     Rd   +     Rw   2       )       Tr       )     ·            -     (     t   -   Tr     )           (     Rd   +     Rw   2       )     ·   Ct             ,     t   &gt;   Tr                                                           
     Where k 1 , and k 2  are the natural frequencies of the circuit and P and Q are given by:          P   =       Cc   ·     (     1   +       k   2        RCt       )         Tr   ·   Ct   ·     (       k   1     -     k   2       )           ,                Q   =     -     (       Cc   ·     (     1   +       k   1        RCt       )         Tr   ·   Ct   ·     (       k   1     -     k   2       )         )                         
     With R=Rd+Rw/2 and Ct=Cg+Cc. The natural frequencies K 1  and K 2  can be found as:        k1   =       (       -   1       C   1       )          [       2     R   w       +     1     R   d       +       (       4     R   w   2       +     1     R   d   2         )         ]               k2   =       (       -   1       C   1       )          [       2     R   w       +     1     R   d       -       (       4     R   w   2       +     1     R   d   2         )         ]                       
     With R=Rd+Rw/2 and Ct=Cg+Cc. 
     All numbers are normalized to the supply voltage, Vdd. A simplified single-pole model represents decay of the pulse, for time greater than Tr, without much loss of accuracy. 
     Rise time of the aggressor lines A 1  and A 2  is estimated from the switching ON resistance of the devices  325  driving those lines, the total capacitive load (sum of the coupling capacitors  302  and  303 , and all other capacitances  310  on the line) and a portion of the wire resistance  316  of those lines. The risetime is taken as the geometric mean of the risetime at the source and destination ends of the wire.                  Relationship                 2     _                     
          Tr   =     2     (       1     Trise        (   SourceEnd   )         +     2     Trise        (   DestinationEnd   )           )                                           
     Typical circuits have multiple aggressor lines per victim line. By superposition the stimulus for N aggressors is:          ∑     i   +   1     N                       Cc        (   i   )         Tr                   (   i   )                         
     This is equivalent to a lumped aggressor with all capacitance connected to it and risetime Tr(equiv):              ∑     i   =   1     N                     Cc        (   i   )           Tr        (   eqv   )         =         ∑     i   +   1     N                         Cc        (   i   )         Tr        (   i   )                       which                 gives                 Tr                   (   eqv   )         =         (       ∑     i   +   1     N                       Cc        (   i   )         Tr        (   i   )           )       -   1       ×       ∑     i   -   1     N                       Cc        (   i   )       .                           
     Multiple aggressors are lumped together in the model, with an effective rise time for the lumped line. This effective rise time, Tr(eff), is the weighted harmonic mean of the individual rise times of all the aggressors, attacking the victim line and is given by:                  Relationship                 3     _                     
            Tr        (   eff   )       =         (       ∑     i   =   1     N                       Cc        (   i   )         Tr        (   i   )           )       -   1       ×       ∑     i   =   1     N                     Cc        (   i   )                                               
     Where the weighting factor Cc(i) is the capacitive coupling from the ith aggressor to the victim and N is the total number of aggressors. 
     FIG. 4 shows a plot of a noise waveform  401  produced by SPICE for a realistic circuit model and the approximation of this noise pulse  403  as given by the above Relationship. 
     Failure Criteria of Noise Pulses 
     The criterion for failure depends not only on the noise pulse but also on the gate that receives this pulse as an input. The criterion ensures that the amount of noise propagated through the receiving gate is below a given level, with margin for ground bounce and other effects. For any given gate, there exist two values, the maximum noise energy E NMAX , and maximum peak noise voltage V NMAX , which the gate can tolerate without propagating noise through it. It has been found that an acceptable pass criteria is: 
     Relationship 4 
     
       
         Max{ Vx ( t )}&lt; V   NMAX   
       
     
     and                  Relationship                 5     _                     
              ∫   Tn            Vx        (   t   )                 )     2                        t         &lt;     E     N                 MAX                                           
     Where Tn is the duration of the noise pulse. 
     The “Propagating noise through a gate” may be defined in two ways. Amplified propagation corresponds to noise propagating through a gate being greater than the input noise to the gate. Restricting the input noise pulse to be small enough that the receiving gate is not pushed into the greater than unity gain region of operation eliminates amplified propagation. For most symmetric static gates, this corresponds to setting V NMAX  equal to, or less than, the unity gain voltage in the dynamic transfer characteristic of the receiving gate. 
     For dynamic gates, where the gain in one direction is much higher than in the other direction, discharge current is a function of the square of the gate voltage. The amount of charge discharged by a MOSFET in the evaluate stack due to a noise pulse is proportional to the energy of the pulse to first order. Bounding this energy to a low value, E NMAX , ensures a lack of amplified propagation. Bounding the peak voltage to a particularly low value also ensures absence of propagation through the dynamic gate. Alternatively, a reduced V NMAX  is defined for dynamic gates that prevents propagation of noise and avoids need for Relationship 5, but this induces some pessimism. 
     Pulse propagation, or propagation of noise through a gate, for one embodiment of the invention, is assumed to occur where the input noise to a gate causes a pulse at the output having a height greater than 5% of the rail. By limiting E NMAX  and V NMAX  to limits that are determined by circuit simulation for each gate type, pulse propagation is eliminated. 
     Eliminating pulse propagation prevents amplified propagation for all practical gates. As an alternative to simulation, E NMAX  and V NMAX  can be calculated from the transistor models, gate structure and loading information. These limits are uniform across families of gates, therefore typical values for E NMAX  and V NMAX  are determined for classes of gates. Then finding the V NMAX  or E NMAX  failure threshold requires identifying the class of gates for a wire destination and looking up and applying the correct predetermined pass criteria. One embodiment of the invention utilizes a gate-name based classifier that classifies gates into six gate types: static gates; dynamic gates; flip-flop logic inputs; flip-flop clock inputs; pass gate structures; and unclassifiable gates. 
     For wires having multiple loads of different types, the smallest V NMAX  value of the relevant gate types is selected as the failure threshold. 
     Exclusivity 
     The assumption that all aggressors of a given line fire at the same time, and in the same direction, is inherent in the lumping of all aggressors into a single aggressor. This leads to undue pessimism in the analysis in several cases. In a given set of aggressors, there may be some logically exclusive signals that cannot switch in the same direction at the same time. There may be several signals that switch at different points of the cycle and it is pessimistic to assume they switch simultaneously. 
     The logical exclusivity of signals may be provided by the user, as with some available timing tools. This is used to find the worst aggressor in any given mutually exclusive set. The worst of these aggressors is then lumped with other non-exclusive aggressors, to produce an effective lumped aggressor. Other signals in the mutually exclusive set are assumed quiet, and not contributing to the coupling. 
     Temporal exclusivity is accounted for by defining timing windows in which signals can switch. As shown in FIG. 5, the cycle time is divided into N timing windows, labeled W 0  through W N−1 . Based on an “a priori” timing analysis, a signal is placed in the one or more windows in which it switches. Once all signals have been placed, we define a switching interval S, comprising three windows [W (r−I)modN  Wr W (r+,)modN ] as shown in FIG.  5 . This creates a set of overlapped switching intervals, S 0  through S N−1 . Noise analysis is then done in each switching interval individually. The switching interval has the effect of spreading the signal switching time to the two neighboring windows. Any noise caused by a signal that switches in W r  adds on to the effect of another signal that may switch W r , W r−1  or W r+1 . Spreading of the signal switching time accounts for the fact that signals are ‘switching’ not only when they are at the 50% of Vdd point, but from 0% to 100%. Spreading also allows for uncertainties in timing and clock skew. Consequently an ideal size for the switching intervals S 0  through S N−1  is 
     Relationship 6 
       T   interval   =T   rise   +T   skew   +T   uncertainity   
     Where T rise =expected rise/fall time on the aggressors, T skew =clock skew and T uncertainity =uncertainty in signal arrival time. 
     The switching intervals wrap around, i.e., a signal in W N−1  spreads to W 0  and vice versa. Signals for which no timing information is available are placed in all the switching intervals while a few mostly-inactive signals (such as reset, and scan-enable) are placed in none. Once all signals are placed, noise analysis is done for each switching interval, using only those signals that may switch in that interval as aggressors. The noise in the worst-case interval is reported as the noise on the line. 
     The number of windows used, N, is determined by T interval  defined in Relationship 6. Since the skew and rise/fall times do not vary much, the uncertainty term usually determines the size of the interval used. A large N leads to less pessimism in the noise analysis while a smaller N is more tolerant of uncertainties in the timing analysis. N must be at least 4 for this scheme to be meaningful since a value of N=3 means the entire cycle is the switching interval. In practice N=6 to N=8 are achieved easily, whereas a tighter partition on the switching times may not be possible. With N=6, noise levels reported on a test datapath were about 30% less than without any timing information being taken into account. 
     Noisetool 
     An analysis tool (Noisetool) was developed according to the invention, to detect large coupling noise voltages induced in a microprocessor or other logic integrated circuit. It ensures that noise pulses do not propagate through an amplifying stage. Pulse propagation is eliminated, so that the noise induced on any net is induced only by its aggressive neighbors and not by the previous logic stages. This simplifies analysis by making noise on any net independent of nets in previous logic stages. 
     As shown in FIG. 6, Noisetool uses a layout at  601  to create a parasitic extracted netlist at  603 , as would be extracted with an extractor at  602 , such as the STAR extractor available from Avant!. Extractors are well known in the art and other extractors known in the art could be used. Interconnect parasitic capacitances are read from netlist at  603 , while multiple capacitances to the same node or to equivalent quiet nodes are summed at  604 . These parasitic capacitances include the capacitances of capacitors  300 ,  301 ,  302 ,  303  and  310  of FIG.  3 . One embodiment of the invention performs flat and hierarchical analyses as described. In flat analysis, gate and diffusion capacitance of the transistors are calculated at  605  (FIG. 6) based on the transistor models and the transistor sizing information in the netlist from  603 . Since a bias independent linear resistance is assumed for the transistor holding the victim line ( 320  in FIG.  3 ), this resistance is computed based on the device parameters. During hierarchical analysis, capacitive loading and/or drive resistance of the sub-circuit ports are obtained from characterized data files. 
     Destination gates  330  described in the netlist of  603  (FIG. 6) are analyzed to determine their type, and pre-characterized values of V NMAX  and E NMAX  are found at  607  that prevent pulse propagation for each possible victim wire. 
     Next, the circuit model shown in FIG. 3 is built at  610  (FIG. 6) and solved through application of Relationships (1) and (2) above. The V NMAX  and E NMAX  failure criteria are applied at  611  for each net. Failing nets are flagged and reported at  612  in a result file at  613  as violations with the calculated maximum noise voltage and other information about the net. Detailed circuit simulation in SPICE showed that the failure criterion of Relationship 4 tracks with failures observed in simulations. 
     In one embodiment of the invention, a layout-versus-schematic analysis program is run prior to extraction of the netlist at  603  so that the netlist will have meaningful names, these names are placed in the result file at  613  to assist review by design engineers. 
     Hierarchical Analysis 
     The analysis may be conducted on a flat, parameterized, transistor level netlist of the circuit. Such analysis is often unwieldy for large designs due to the size of the netlists involved and run times for generating and analyzing them. It has been found that in the circuit model of FIG. 3, the driver element  320  need not be a transistor. It may be a gate or other block. FIG. 8 schematically illustrates this gate level block model with driving element resistance  800  connected to an output pin  806 . Since characteristic switching resistances are generally found during timing characterization for all gates used in the design, Rd can be derived for any gate from available characterization data. Similarly, for the receiving gate inputs, such as input pins  805 , capacitive loading information, modeled as capacitors  801 ,  802 , and  803 , can be obtained from characterized libraries. 
     As shown in FIG. 7, when a hierarchical layout is extracted to a parameterized netlist, aggressor wire interconnect resistance is modeled as a resistor  700  in series with the appropriate output resistance from the gate block model effectively inserted into the netlist as the aggressor gate  701 . The aggressor node parasitic capacitances are modeled as a capacitor  705  in parallel with the input capacitance of any load gates  706 , such as library model input capacitance  801  (FIG. 8) on the aggressor wire. These resistances and capacitances are used to determine an aggressor wire  710  (FIG. 7) rise time. 
     Similarly, the output resistance from the appropriate gate model, such as library model output resistance  800  in FIG. 8, is used as the driving resistance  320  (FIG. 3) holding the victim line in the model. The victim line interconnect resistance  720  (FIG. 7) becomes the second pole resistance  305  (FIG. 3) of the model, and half of the interconnect capacitance of the victim line, illustrated by capacitors  725  and  726  of FIG. 7, become the victim line capacitances  300  and  301  (FIG. 3) of the model. The library gate model also incorporates tolerable input noise thresholds for use as V NMAX  or E NMAX . 
     Resistance/Capacitance Network Reduction 
     According to one embodiment of the invention, the wire resistance used for non-reconvergent paths is computed by dropping all branch paths other than a shortest actual interconnect path between the driving gate or module and the destination gate or module. This may be pessimistic in the event that there are multiple paths from the driving gate  320  to the destination gate  330 . 
     The resistance and capacitance network reduction of one embodiment of the invention can be better understood through reference to FIG.  9 . Assuming that the signal path being analyzed is that from driving gate or module  900  to recipient gate or module  901 , it is seen that resistors  902  and  903  are a reconvergent path. All but the least resistance of these reconvergent resistors are dropped from the circuit. In this example, resistor  903  has a greater resistance value than resistor  902 , and therefore resistor  903  is dropped. In the integrated circuit being analyzed, multiple parallel resistors such as  902  and  903  may occur in the netlist if multiple vias are used in the layout where two metal lines cross on different layers, or where a metal line has multiple contacts to a silicided diffusion layer; both are common in integrated circuit layouts. 
     The resistive value of resistor  902 , the survivor of the first reduction, is then added to that of resistor  905 , then this total resistance is compared with that of resistor  906 , representing a higher-level reconvergent path. Again, the greater value resistance is dropped, and the lesser retained. In this example,  906  is dropped and the lesser sum of the values of resistors  902  and  905  is retained. Next, the values of resistors  902  and  905  is added to the remaining series resistor  907 , the sum becoming the value of resistor  1000  in the simplified or reduced circuit of FIG.  10 . 
     Capacitances, including capacitances  915  and  916  found in the network between the driving gate  900  and the recipient gate  901  are summed, then divided into two equal capacitances that are added to the terminal capacitances  917  and  918  of the interconnect line. 
     In reducing the resistance and capacitance network for use with the two-pole model of the present invention, driven gates and hierarchical modules, including the recipient gate  901  and off-path recipient gates or modules, such as  925  and  926 , are replaced with their equivalent load capacitance as determined from their library models or from their device sizes. 
     Circuit resistances off the path between the driving gate  900  (FIG. 9) and recipient gate  901 , such as resistances  910  and  911 , are removed from the circuit. Load capacitances connected by these off-path resistances, such as capacitances  920  and  921 , and the equivalent capacitances of off-path gates and modules such as gates  925  and  926 , are summed and added to the appropriate, nearest, terminal capacitances  917  and  918 . As shown in FIG. 10, the resulting total terminal capacitances become capacitances  1001  and  1002  of the simplified, reduced, network. 
     This reduction technique can be summarized as: 
     (1) For on-path network resistances in parallel: 
     replace resistances with the lower-value resistance; 
     (2) For on-path network resistances in series: 
     replace resistances with a resistance having a resistance equal to the sum of the resistances; 
     (3) Repeat the reduction of parallel and series resistances until only one resistance is left on the path from driving gate to receiving gate; 
     (4) Add all capacitances found on-path, divide these equally between the driving gate or module and the receiving gate or module, and add these to any terminal capacitances of the network; 
     (5) Remove all off-path network resistances, adding all off-path network capacitances to the appropriate terminal capacitances of the network; 
     (6) Finally, the output resistance of the driving gate  900 , as determined from the transistor models or from a library value, is placed in the network as the driving resistance  1004 . 
     Parameters other than those in the resistance-capacitance network of the netlist that are needed for the analysis are obtained from a hierarchical layout extracted netlist, such as is obtained by extracting an integrated circuit layout with commercially available tools, with gates treated as a “black box” with a characteristic output resistance and input capacitance as described. A hierarchical noise analysis may be conducted at an inter-gate level instead of a flat inter-transistor level. Abstracting the circuits even further, we can “black box” entire blocks (such as datapaths, memories and control blocks) and run the extraction and noise analysis on a top level chip or high level block, using a default capacitance, output resistance, and thresholds for each pin of the block. Since the internal nodes of the black boxes are not visible to the hierarchical analysis, they are dealt with by a transistor or gate level analysis on the block itself. Such a hierarchical approach allows noise analysis to be done on arbitrarily large blocks by splitting them into manageable levels of hierarchy. 
     A hierarchical analysis at a very coarse level results in some inaccuracy because noise injected into a higher level of hierarchy from a lower level may be ignored. Smart extraction tools that do a “gray box” extraction, where wiring from inside the hierarchy boxes is also extracted, can help reduce this inaccuracy. A lower level affected by routing in a higher level can be accounted for by a “cookie cutter” extraction, where the top level routing is captured on top of a lower level block when the lower level block is extracted. If such tools are not available, keeping the level of the hierarchy box as low as possible reduces inaccuracy, while making the boxes bigger reduces complexity and run time. Table 3 (below) compares the noise levels as measured by a gate level hierarchical analysis and flat analysis. It shows that the loss of accuracy in going from fully flat to gate level is small. 
     A hierarchical analysis may also be done prior to fully completing chip design. A top level extraction may be performed with black boxes at lower levels to locate at least some of the problems that may exist in top-level interconnect. Lower level blocks may also be run independently to locate at least some of the noise coupling problems that may exist in their interconnect. 
     SPICE Comparisons 
     The normalized noise levels (peak induced noise voltage as a fraction of Vdd) reported by the simulator of the present invention are compared to SPICE results on two types of circuits. Type  1  circuits are comparisons on “test circuits” where some assumptions made by the Noisetool of the present invention were constrained to be true. These comparisons are made on wires with coupling uniformly distributed, no branches, and two major, uniform, aggressors switching at the same time. These circuits give a value of peak noise voltage between 20% and 40% of Vdd, since this is a range where failures are likely to occur. Results for a 0.25u technology are shown in Table 1. 
     
       
         
           
               
               
               
             
               
                   
                 TABLE 1 
               
             
            
               
                   
                   
               
               
                   
                 Peak Noise/Vdd 
                   
               
            
           
           
               
               
               
               
            
               
                   
                 Noise- 
                   
                   
               
               
                 Signal Description 
                 tool 
                 SPICE 
                 Error 
               
               
                   
               
            
           
           
               
               
               
               
            
               
                 1 mm long; 
                 0.30 
                 0.29 
                 4% 
               
               
                 minimum width and space to aggressors 
               
               
                 1 mm long; min width and space; 
                 0.28 
                 0.27 
                 4% 
               
               
                 very strongly held 
               
               
                 2 mm long; min width and space 
                 0.42 
                 0.38 
                 10% 
               
               
                 2 mm long; twice min width and space 
                 0.29 
                 0.28 
                 4% 
               
               
                 3 mm long; twice min width and space 
                 0.35 
                 0.32 
                 9% 
               
               
                 2 mm long; twice min width; 
                 0.36 
                 0.33 
                 9% 
               
               
                 1.5 × min space; strongly held 
               
               
                 3 mm long wire; partial shield; 
                 0.29 
                 0.27 
                 7% 
               
               
                 twice min width; min space 
               
               
                 2.5 mm long; twice min width; 
                 0.27 
                 0.24 
                 −12% 
               
               
                 thrice min space 
               
               
                 3 mm low resistive metal; min width and space 
                 0.26 
                 0.28 
                 −7% 
               
               
                 4 mm low resistive metal; min width and space 
                 0.27 
                 0.29 
                 −7% 
               
               
                   
               
            
           
         
       
     
     Type  2  comparisons are run on actual blocks taken from a large microprocessor design. The results for a regular datapath structure, a synthesized control block, and for the core of the chip are presented. Peak noise calculated on nets was found pessimistic by an average of 20%. In the floating point datapath, where wiring is regular and non-branching, the average error is lower than in a more random control block. The aggressor rise time, [Tr as defined previously], was found pessimistic by about 30% on average and 66% in the worst case, and is the largest contributor to inaccuracy in the peak noise. Improved calculations of the aggressor slew rate, especially for aggressors with non-uniform loading and multiple branches, will enhance the accuracy of Noisetool. 
     
       
         
           
               
               
               
               
             
               
                 TABLE 2 
               
               
                   
               
               
                   
                 Floating 
                   
                 Instruc- 
               
               
                   
                 Point 
                 Top 
                 tion 
               
               
                   
                 Data- 
                 Level 
                 Issue 
               
               
                 Measure\Circuit 
                 path 
                 Chip 
                 Control 
               
               
                   
               
             
            
               
                   
               
            
           
           
               
               
               
               
            
               
                 Worst case peak noise a   
                 155% 
                 155% 
                 140% 
               
               
                 Number of violations a   
                 200% 
                 250% 
                 220% 
               
               
                 Overlap in reported violations b   
                 100% 
                  99% 
                 100% 
               
               
                 R.M.S. error in peak noise compared to SPICE 
                 12% 
                  24% 
                 20% 
               
               
                   
               
               
                   a Number reported by Noisetool/Number reported by SPICE  
               
               
                   b Percentage of nets reported by SPICE that were also reported by Noisetool  
               
            
           
         
       
     
     
       
         
           
               
               
             
               
                 TABLE 3 
               
               
                   
               
               
                   
                 Floating 
               
               
                   
                 Point 
               
               
                 Measure\Circuit 
                 Datapath 
               
               
                   
               
             
            
               
                   
               
            
           
           
               
               
            
               
                 Worst case peak noise a   
                 95% 
               
               
                 Number of violations a   
                 99% 
               
               
                 Overlap in reported violations b   
                 100% 
               
               
                 R.M.S. error in peak noise of analysis 
                 2% 
               
               
                 of hierarchical gate-level netlist as compared to a flat netlist 
               
               
                   
               
               
                   a Number reported by hierarchical analysis/Number reported by flat analysis  
               
               
                   b Percentage of nets reported by flat analysis that were also reported in hierarchical analysis  
               
            
           
         
       
     
     Parameter Estimating Embodiment 
     The foregoing full-chip and hierarchical analyses may consume considerable processor time because of the many parasitic capacitances that may need extraction and consideration in a large design. In another embodiment, a topology-based data structure is extracted from the layout for each wire of the circuit. The topology-based data structure includes the following characteristics of each net: 
     
       
         
           
               
             
               
                 TABLE 4 
               
             
            
               
                   
               
               
                 Topology-Based Data Structure 
               
            
           
           
               
               
            
               
                 Parameter 
                 Definition 
               
               
                   
               
               
                 length 
                 length of net from source to destination 
               
               
                 average width 
                 weighted arithmetic mean line width, 
               
               
                   
                 weighted by the lengths 
               
               
                 average space 
                 weighted harmonic mean of the spaces between lines, 
               
               
                   
                 weighted by the lengths 
               
               
                 coupling length 
                 length for which a metal line has neighbors running 
               
               
                   
                 close enough to it to potentially cause capacitive 
               
               
                   
                 coupling 
               
               
                 full_coverage 
                 portion of metal line which is covered above and below 
               
               
                   
                 by orthogonal metal layers 
               
               
                 half_coverage 
                 portion of metal line which is covered above or below 
               
               
                   
                 but not both, by orthogonal metal layers 
               
               
                   
               
            
           
         
       
     
     Referring to FIG. 11, each possible victim metal line  1100  of the layout is traversed using a traversal window  1101  of a predetermined size. In one embodiment of the invention, the window  1101  extends about five times the minimum dimension of the process beyond the traversed victim lines to identify adjacent lines that can significantly affect the possible victim line, while ignoring adjacent lines that can&#39;t significantly affect the possible victim line. The window  1101  therefore sweeps an area  1105  near the victim line  1100  as it traverses the line. Since neighbor lines crossing on another layer at forty-five degree angles to the possible victim line are rare under the rules of the process, they are ignored. 
     As the window traverses along the possible victim line under control of a computer program executing on a computer, the program seeks changes in neighbors  1110 , or distance to neighbors, to victim line  1100  in the same or adjacent layers as well as changes in the width of victim line  1100 . The spacing  1112  to these neighbors  1110  and the width  1114  of victim line  1100  is measured, as is the length of the portion of victim line  1100  between each change. 
     If there are no parallel neighbors within the window for a portion of victim line  1100  length, then that portion of the length is not considered part of the coupling length, but is considered part of the total length of the line. If there are parallel neighbors  1110  on only one side of victim line  1100 , that portion  1116  of the length is considered part of the coupling length, and part of the total length. If there are parallel neighbors on both sides of the wire, that portion of the length is doubly counted as part of the coupling length, but is singly considered part of the total length of the line. 
     During the traversal, a harmonic mean of the spacing between the victim line and the neighbor lines is computed by maintaining a running total of squares of the inverse of the spacing times the length, and a running total of the length. Similarly, an arithmetic mean of the width of victim line  1100  is maintained by maintaining a running average of the victim line  1100  width throughout the traversal process. 
     The program product captures perpendicular neighbors  1118  in the layers above and below the wire that fall within the height of the window. If these layers exist above and below, that portion  1120  of the length is considered to have full coverage; if they exist only above or below but not both, that portion  1122  has half coverage. If there are no layers above and below the wire within the window height, the wire is considered to have no coverage for that length. 
     The topology information is then used to calculate estimated resistance, capacitance and coupling capacitance parameters for the possible victim line. The total capacitance of the victim line is calculated as: 
     
       
           C   tot   =K   1 *(averagewidth)*(totallength)+ K   2 *(totallength)+ K   3 *(half coveragelength)+ k   4 *(full coveragelength) 
       
     
     The coupling capacitance of the line is estimated as: 
       C   couple   =K   5 *(couplinglength)/(harmonicmeanspacing) 
     and the resistance of the line is estimated as: 
     
       
           R   line   =K   6 *(totallength)/(averagewidth) 
       
     
     Where K 1 -K 6  are positive or negative real constants predetermined for the process used for the integrated circuit. 
     These resistance and capacitance parameters are input to the two-pole model for noise estimation as previously described. 
     A computer program product is any machine-readable media, including any disk or tape, having recorded on it a computer program, whether for distribution, execution, or storage. 
     Conclusion 
     While there have been described above the principles of the present invention with specific embodiments thereof, it is to be understood that the foregoing description is made by way of example and not as limitation to the scope of the invention. The foregoing disclosure may suggest other modifications to those persons skilled in the relevant art. Such modifications may involve other features which are already known per se and which may be used instead of or in addition to features already described herein. 
     For instance, in one embodiment of the invention, when the topology information is used to calculate estimated resistance, capacitance and coupling capacitance parameters for the possible victim line as discussed above, an additional half coverage length and full coverage length parameter is computed for those lengths having neighbors so as to take into account the fringe-field trapping (shielding) effect of the adjacent layers. 
     Although claims have been made in this application to particular combinations of features, it is understood that the scope of the disclosure herein also includes novel features or any novel combination of features disclosed explicitly or implicitly or any modification or generalization thereof which is apparent to persons skilled in the art, whether or not such relates to the invention as presently claimed in any claim and whether or not it mitigates any or all technical problems as confronted by the present invention. The applicants reserve the right to formulate new claims to such features and combinations of such features during the prosecution of the present application or of any further application derived therefrom.