Patent Publication Number: US-9852940-B2

Title: Method for forming a reliable solderable contact

Description:
RELATED APPLICATIONS 
     This is a divsional of application Ser. No. 10/982,965 filed 11/5/2004. 
     This application claims the benefit of U.S. Provisional Application No. 60/552,139, filed Mar. 11, 2004. 
    
    
     FIELD OF THE INVENTION 
     This invention relates to semiconductor devices and processes for their manufacture and more specifically relates to a novel solderable contact structure for semiconductor die. 
     BACKGROUND OF THE INVENTION 
     Solderable contacts for semiconductor devices are well known. Such contact structures are commonly silver-containing alloys deposited on aluminum die electrodes, which are insulated from other surfaces by an insulation passivation coating which overlaps the edges of the contact area. 
     It has been found that the silver ions from the top metal layer will migrate under the passivation layer and form dendrites under prolonged exposure to electric fields and moisture. Thus, over time, the dendrites will form conductive bridges between device electrodes and device terminations, thus reducing device reliability. 
     It would be desireable to provide a passivated top silver-containing solderable contact in which the migration of silver from device electrodes and under the passivation is prevented. 
     BRIEF DESCRIPTION OF THE INVENTION 
     In accordance with the invention the silver-containing solderable metal layer is terminated around its periphery and is spaced from the edge an epoxy passivation layer, forming a gap between the edge of the epoxy passivation and the confronting edge of the solderable metal layer. During solder attach of the device to a circuit board or the like, the attach-solder will dissolve the exposed silver, forming a solder alloy. This prevents the migration of silver ions from the solderable electrodes to the termination during applied electric fields to the device during its operation. Thus, dendrite formation is reduced and device reliability is improved. 
     The novel invention has application to any semiconductor device in which a solderable contact is desired, such as the Direct FET® device of International Rectifier as shown, for example, in U.S. Pat. No. 6,624,522, issued Sep. 23, 2003, entitled CHIP SCALE SURFACE MOUNTED DEVICE AND PROCESS OF MANUFACTURE (IR-1830), as well as to flip chips; humped/wafer level packages and the like. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a bottom view of a Direct FET® type package of the type shown in aforementioned U.S. Pat. No. 6,624,522. 
         FIG. 2  is a cross-section of the circled portion of  FIG. 1 , showing the area of overlap of a passivation layer and solderable metal of the prior art. 
         FIG. 3  is a cross-section like that of  2 , but illustrating the novel invention in which the edge of the solderable metal is spaced from the confronting edge of the epoxy passivation. 
     
    
    
     DETAILED DESCRIPTION OF THE DRAWINGS 
     Referring first to  FIGS. 1 and 2  there is shown a bottom view of a Direct FET® type package  10  in which a MOSFET semiconductor die  11  is contained within a metal can  12  which has an open bottom, shown in Figure, and a top web  13 , shown in  FIGS. 2 and 3 . The web  13  is connected to flanges  14  and  15  which form a contact for drain electrode  16  on the bottom surface of die  11 . 
     The top surface of die  11  is exposed by the open bottom of conductive can  12  and contains a source electrode having solderable contacts  20  and  21  and a solderable gate contact  22 . The top surfaces of contacts  20 ,  21  and  22  are generally coplanar with drain contacts  14 ,  15  although there could be an upset of up to about 50 μm an due to tolerance variations. Thus, the device is solderable at its contacts  14 ,  15 ,  20 ,  21  and  22  to respective corresponding contact areas on a flat circuit board (not shown). The contacts  20 ,  21  and  22  are insulated from one another and from the conventional termination enclosing the upper surface of die  11  by an insulation passivation layer  30 . 
     It is to be noted that the invention is illustrated as applied to a Direct FET® type device. However, the die  11  may be any semiconductor die which has a solderable contact which is insulated by a surrounding passivation coating. 
     In the device illustrated, the die  10  (shown as silicon, but which may be of other materials, for example, SiC, GaN, and the like) has the contact structure shown in cross-section in  FIG. 2 , which is a section through the surface area shown in the circle  35  in  FIG. 1 . Thus solderable contact  21  is the exposed area of a silver-containing solderable metal such as a conventional titanium/nickel/silver stack having thicknesses of 1,000 Å, 2000 Å and 6000 Å respectively, which is deposited atop the aluminum source contact  40  of MOSFET die  11 . The solderable contact  21  is surrounded by insulation passivation layer  30  which consists of a nitride layer  42  and an epoxy layer  41 . Note that the edge of contact  21  overlaps nitride layer  42  and is encapsulated under the epoxy layer  41 . Thus, the outer rim area  43  of contact  21 , is captured under epoxy  41  and is not exposed to solder during a soldering operation. The epoxy layer  41  may also be formed of BCB, polyamide or polysiloxane passivation materials. 
     In the structure of  FIG. 2 , and after soldering to the exposed area of contact  21 , free silver ions can migrate from top metal  21 , under the insulation epoxy layer and form dendrites under prolonged exposure to electric fields and moisture during operation. These dendrites can form conductive bridges to and toward the die terminations, thus impacting device reliability. 
     In accordance with the invention, and as shown in  FIG. 3 , the edge of metallizing  21  is foreshortened to overlie nitride layer  42 , but spaced from the confronting edge of epoxy layer  41 , creating the gap  50  there between. The gap  50  will preferably surround the periphery of contact  21  in  FIG. 1 . Significantly, the outer rim of contact  21  is fully exposed for solder connection. 
     When the device of  FIG. 3  is to be attached by soldering to a circuit board, the attach solder dissolves the exposed silver containing contact  21 , forming a solder alloy in the conventional manner. This takes place when using any conventional solder. The silver is now fully captured within the alloy and cannot migrate from the device electrodes to create dendrites and reduce device reliability. Note that in the prior art device that the silver-containing solderable contact  21  captured under the epoxy layer  42  is not reached during soldering and the remaining silver is a source of the migrating ions which will form the disadvantageous dendrites. 
     To form gap  50 , the nitride layer  42  was extended by about 35 microns, as compared to  FIG. 2 ; and the gap  50  is about 10 microns and can be from about 5 microns to about 20 microns wide. More generally, the gap should be at least as wide as needed to insure that no silver is encapsulated under epoxy  41 , and all of the silver contact  21  is exposed to alloying during soldering. 
     Although the present invention has been described in relation to particular embodiments thereof, many other variations and modifications and other uses will become apparent to those skilled in the art. It is preferred, therefore, that the present invention be limited not by the specific disclosure herein.