Patent Publication Number: US-7215162-B2

Title: Start signal outputting circuit

Description:
TECHNICAL FIELD 
   This invention relates to a novel start signal outputting circuit. Here a start signal outputting circuit is defined as a circuit for outputting a direct current potential (DC) when inputting a high frequency power (RF) of a certain frequency band. This definition naturally includes circuits which, when inputting a high frequency power (RF) in the respective band intermittently at short intervals, output a direct current potential (DC) intermittently in correspondence with this. An example of a related field of the invention is technology relating to diode wave detection and rectenna. 
   BACKGROUND ART 
   As technology relating to diode wave detection and rectenna, technologies disclosed in Japanese Patent No.2561023 (Document 1), Japanese Patent No. 2605827 (Document 2), JP-A-4-291167 (Document 3), JP-A-9-162644 (Document 4), Japanese Patent No. 2533800 (Document 5), and JP-B-6-48895 (Document 6) are known. Of these, Documents 1 through 4 disclose technology relating to high frequency wave detection using a diode, and Documents 5 and 6 disclose technology relating to rectenna. 
   First, high frequency wave detection technology using an ordinary diode disclosed in Documents 1 through 3 will be described.  FIG. 11A  shows a known diode detection circuit for performing high frequency wave detection. In the diode detection circuit shown in  FIG. 11A , a bias voltage source B is connected to the anode side of a diode D via an inductance L 0 , and a resistance R 01  and a capacitance C 2  connected to ground are connected in parallel with each other to the cathode side of the diode D. However, the diode detection circuit shown in  FIG. 11A  is sometimes operated without a bias voltage being applied. 
   For example, when a low-level high frequency power is to be detected, generally, down to about −40 dBm a zero bias Schottky diode or the like can be used. When the high frequency power is of a lower level than that, normally, a slight bias voltage is applied. However, even when a bias voltage is applied, as will be further discussed later about −50 dBm constitutes a lower limit of high frequency wave detection. 
   To convert high frequency power into direct current, half-wave rectification is used; but when the circuit shown in  FIG. 11A  is used for that purpose, to convert a low-level high frequency power into a direct current it is necessary for the d.c. bias current to be made very small. For example to realize a bias current of 1 μA with a voltage of 3V, a resistance of 3 MΩ is necessary. In this case, the inductance L 0  on the anode side of the diode D of  FIG. 11A  can be replaced with a resistance R 02  ( FIG. 11B ) 
   However, in the cases of both  FIGS. 11A and 11B , the resistances R 01  and R 02  used must be of several MΩ. When a resistance having a large resistance value like this is realized on an IC chip, the resistance element becomes long, and a large space becomes necessary. As a result, the facing area of the resistance element facing ground becomes large, a parasitic capacitance and a parasitic resistance arise between the resistance on the chip and the ground in the substrate, and the high frequency power leaks to the substrate. Consequently, to convert a low-level high frequency power of for example 5.8 GHz, −60 dBm into a direct current with a diode circuit formed on an IC chip is difficult. 
   Although it is possible to convert a low-level high frequency wave of −60 dBm into a direct current by using heterodyne detection technology, a transmitter or LAN and mixer must be operated continually, and the power consumed during high frequency signal standby time becomes large. 
   Also, with a high frequency detection circuit using a diode, it is notable that when the load resistance is large, the voltage applied across the anode/cathode of the diode becomes small and the high frequency wave cannot be converted, and that post-conversion output resulting from bias fluctuation is not distinguishable from d.c. potential obtained by converting high frequency power. 
   In Document 4, technology for producing a d.c. potential corresponding to an inputted high frequency power level is disclosed. That is, in Document 4, technology for converting a high frequency power of essentially any frequency into a d.c. current is disclosed. The technology of Documents 5 and 6 relates to rectenna, and discloses the use of received microwaves as a power source. 
   The present invention relates to a start signal outputting circuit capable of receiving a high frequency wave, generating a d.c. potential from that high frequency wave, and using this d.c. potential as a starting signal of a designated circuit, and particularly it is an object of the invention to provide a start signal outputting circuit having a construction suitable for integration. It is another object of the invention to provide a start signal outputting circuit capable of generating a low-noise d.c. potential when converting a high frequency signal into a d.c. potential. 
   DISCLOSURE OF THE INVENTION 
   A start signal outputting circuit provided by the invention has an RF/DC convertor circuit for converting a high frequency power of a specified frequency into a d.c. component and outputting this. This RF/DC convertor circuit is made up of a device working as a diode; a matching circuit provided on the anode side of that diode for obtaining matching with respect to the inputted high frequency power; a first transistor, connected to the anode side of the diode, working as a high resistance to which a positive potential is applied; and a second transistor, inserted between the cathode side of the diode and ground, working as a high resistance to which a positive potential is applied. Thus, by utilizing the high resistance across the base/emitter of a transistor and the current source arising across the collector/emitter, it becomes possible to realize a high resistance having low high frequency leakage. And because first and second transistors are used as high resistances, a construction suited to integration can be obtained. 
   The RF/DC convertor circuit also has a resonance circuit connected between the cathode side of the diode and ground for shorting at a specified frequency. By a circuit for shorting at the specified frequency being provided on the cathode side of the diode, the high frequency power can be applied to the diode efficiently. 
   And, in the RF/DC convert or circuit, a two-stage transistor circuit may be connected to the cathode side of the diode. That is, a first npn transistor having its collector connected to the cathode side of the diode and its emitter connected to ground via a resistance, and a second npn transistor having its emitter connected to the base of the first npn transistor and a predetermined positive voltage applied to its base and collector may be provided. When the transistor on the cathode side of the diode is made two-stage like this and a resistance is provided between it and ground, cathode potential adjustment of the diode becomes easy and further stabilization of the circuit can be achieved. 
   Using a start signal outputting circuit according to the invention described above, when a specified high frequency wave is received, it is possible to start for example a communication device as a designated device, and to cause a primary battery for the communication device to be consumed when the specified high frequency wave is received. By this means it is possible to realize mobile communication appliances in which a primary battery for a communication device can be used for several years. 
   Other characteristics and excellent effects of the invention will become clear from the following description of embodiments using drawings. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a circuit diagram showing an RF/DC convertor circuit constituting a main part of a start signal outputting circuit according to a first embodiment of the invention.  FIG. 2  is a circuit diagram showing an RF/DC convertor circuit constituting a main part of a start signal outputting circuit according to a second embodiment of the invention.  FIG. 3A  is a graph showing operation simulation results of the start signal outputting circuit of the second embodiment,  FIG. 3B  is a graph showing a potential increase part arising from conversion of a high frequency power in the simulation, and  FIG. 3C  is a graph showing operation simulation results of a start signal outputting circuit of  FIG. 12  as a comparison example.  FIG. 4  is a circuit diagram showing an RF/DC convertor circuit constituting a main part of a start signal outputting circuit according to a third embodiment of the invention.  FIG. 5  is a view illustrating a filter operation of the invention.  FIG. 6  is a circuit diagram showing the construction of a three-stage differential amplifier.  FIG. 7  is a circuit diagram showing a with-filter amplifier part constituting a main part of a start signal outputting circuit according to a fourth embodiment of the invention.  FIG. 8A  is chart of the amplifying characteristic of the differential amplifier of  FIG. 6  with respect to frequency, and  FIG. 8B  is a chart of the amplifying characteristic of the with-filter amplifier part of  FIG. 7  with respect to frequency.  FIG. 9  is a circuit diagram showing a start signal outputting circuit according to a fifth embodiment of the invention.  FIG. 10  is characteristic charts of the start signal outputting circuit of the fifth embodiment,  FIG. 10A  being the output characteristic of a first-stage filter part and  FIG. 10B  the output characteristic of a second-stage filter part.  FIG. 11  is circuit diagrams of diode RF/DC convertor circuits of related art,  FIG. 11A  showing one example and  FIG. 11B  another example.  FIG. 12  is a circuit diagram of an RF/DC convertor circuit of a comparison example for comparison with the second embodiment. 
   

   BEST MODES FOR CARRYING OUT THE INVENTION  
   First, characteristics of a start signal outputting circuit according to the invention will be explained directly. Firstly, in an ordinary diode detecting circuit (for example  FIG. 11 ), when currents are to be made low, the resistance values become extremely high, and it becomes unsuitable for integration. The start signal outputting circuit of the present invention uses transistors to realize integration (reduced size) and low currents (low power consumption). Secondly, in connecting an amplifier part for amplifying the d.c. potential (DC), by the amplifier being made low-current a band-limiting effect is provided, and by filtering circuits being provided before and after the amplifier part the band-limiting effect is strengthened. By means of this band-limiting, high sensitivity in the vicinity of the outputted d.c. potential (DC) can be achieved. In this way, both low power consumption and high sensitivity of the amplifier part are obtained. 
   The ‘RF/DC convertor circuit for converting high frequency power of a specified frequency into a d.c. component and outputting it’ in the start signal outputting circuit naturally includes ‘circuits which, when inputting a high frequency power (RF) in the respective band intermittently at short intervals, output a d.c. current (DC) intermittently in correspondence with this’. And also included are ‘circuits which when inputting a high frequency power (RF) in the respective frequency band output a corresponding d.c. potential (DC) (High Level) and when not inputting a high frequency power (RF) in the respective frequency band do not output a d.c. potential (DC) (Low Level)’. 
   (First Embondiment) 
     FIG. 1  is a circuit diagram showing an RF/DC-conversion circuit  11  constituting a main part of a start signal outputting circuit according to a first embodiment of the invention. The RF/DC-conversion circuit  11  is made up of a matching circuit MC; an npn transistor Q D  used as a diode; an npn transistor Q 1  having its emitter connected to the base (anode side) of the npn transistor Q D ; a resistance R 1  connected to the base of the npn transistor Q 1 ; an npn transistor Q 2  having its collector connected to the emitter (cathode side) of the npn transistor Q D ; a resistance R 2  connected to the base of the npn transistor Q 2 ; a capacitance C 1  and an inductance L 1  connected in series with the emitter (cathode side) of the npn transistor Q D ; and a capacitance C 2  also connected to the emitter (cathode side) of the npn transistor Q D . 
   A potential B 0  is applied to the collector of the npn transistor Q 1  and a potential B 1  to the base via the resistance R 1 . The npn transistor Q 2  has its emitter grounded and a potential B 2  applied to its base via the resistance R 2 . 
   One end of the series circuit of the capacitance C 1  and the inductance L 1  is connected to the emitter of the npn transistor Q D , and the other end is grounded. As a result, this series circuit shorts at a specified signal (carrier). The other end of the capacitance C 2  having its first end connected to the emitter of the npn transistor Q D  is also grounded. 
   The matching circuit MC performs impedance matching of a high frequency signal with respect to the anode end of the npn transistor Q D  using a stub, transmission line, or chip capacitance. 
   The operation of the RF/DC-conversion circuit  11  of  FIG. 1  is as follows. A high frequency wave passes through the matching circuit MC and is applied to the base (anode side) of the npn transistor Q D , which works as a diode. Because impedance matching has been carried out by the matching circuit MC, the high frequency power is applied to the npn transistor Q D  with good efficiency. 
   The npn transistor Q 1  has a high resistance between its base and emitter, and its collector and emitter work as a constant current source. Consequently, the transistor Q 1  works as a high resistance on the anode side (base) of the npn transistor Q D . The collector and emitter of the npn transistor Q 2  work as a constant current source, and it works as a high resistance on the cathode side (emitter) of the npn transistor Q D . The collector and base of the npn transistor Q 2  are joined by a capacitance, but this capacitance is small. Furthermore, high frequency leakage is prevented by the resistance R 2 . 
   Because the capacitance C 1  and inductance L 1  on the cathode side (emitter) of the npn transistor Q D  are grounded and short at a specified carrier, the high frequency power is applied to the npn transistor Q D  efficiently. In this way, a d.c. potential DC of the cathode side (emitter) of the npn transistor Q D  is outputted. This d.c. potential DC maybe put through an amplifier in a later stage or may be used as it is as a signal for starting a communication device or the like constituting a designated output destination. When there is no amplifier in a later stage, the RF/DC-conversion circuit  11  it self constitutes a start signal outputting circuit. 
   (Second Embodiment) 
     FIG. 2  is a circuit diagram showing an RF/DC-conversion circuit  12  constituting a main part of a start signal outputting circuit according to a second embodiment of the invention. From the construction of the RF/DC-conversion circuit  11  of  FIG. 1 , the RF/DC-conversion circuit  12  has the resistance R 2  connected to the base of the npn transistor Q 2  removed along with the bias potential B 2 . In their place, a resistance R′ 2  is provided between the emitter of the npn transistor Q 2  and ground and the emitter of an npn transistor Q 3  is connected to the base of the npn transistor Q 2 . A bias potential B 3  is applied to the base of the npn transistor Q 3  via a resistance R 3 , and the bias potential B 0  is applied to the collector of the npn transistor Q 3 . 
   The RF/DC-conversion circuit  12  of  FIG. 2  was made in view of the fact that it is difficult to freely adjust the potential of the cathode side (emitter) of the npn transistor Q D  which works as the diode of the RF/DC-conversion circuit  11  of FIG.  1 . With the RF/DC-conversion circuit  12  shown in  FIG. 2 , first the potential of the cathode side (emitter) of the npn transistor Q 3  working as a diode rises by the voltage drop of the resistance R′ 2 . The resistance R′ 2  also acts as a feedback resistance preventing fluctuation of the bias potential due to temperature variation. By the npn transistor Q 3  being added, the high resistance (the resistance R 2 ) of the RF/DC-conversion circuit  11  of  FIG. 1  is formed with the npn transistor Q 3 . By this means it is possible to increase the controllability of the base potential of the npn transistor Q 2  and control its collector current and the bias potential of the cathode side (emitter) of the npn transistor Q D . 
   A simulation of the operation of the RF/DC-conversion circuit  12  of  FIG. 2  is shown in  FIGS. 3A ,  3 B and  3 C. V out0  in  FIG. 3A  is the output potential of the RF/DC-conversion circuit  12  of  FIG. 2  when a high frequency wave is not inputted, and is 1.55554V. V out  in  FIG. 3A  is the output potential when a high frequency wave of 5.8 GHz, −50 dBm is inputted to the RF/DC-conversion circuit  12  of  FIG. 2 , and is 1.55566V. The difference between these is shown in  FIG. 3B . From  FIG. 3B  it can be seen that a d.c. potential of 118 μV and a small a.c. potential component from the high frequency wave appear. The small a.c. potential component from the high frequency wave arises because the shorting effected by the capacitance C 1  and the inductance L 1  is incomplete. The d.c. potential of 118 μV is the result of the RF/DC-conversion circuit  12  of  FIG. 2  converting the 5.8 GHz, −50 dBm high frequency wave into a d.c. potential. For comparison, a simulation of the operation of an RF/DC-conversion circuit of the kind shown in  FIG. 12  simply having resistances R 01  and R 02  in place of the two biases provided by resistances and transistors in the RF/DC-conversion circuit  11  of  FIG. 1  is shown in  FIG. 3C . It can be seen that the RF/DC-conversion circuit of  FIG. 12  only converts the 5.8 GHz, −50 dBm high frequency power to a small d.c. potential of 14 μV, whereas the RF/DC-conversion circuit  12  of  FIG. 2  of the second embodiment of the present invention converts high frequency power into a d.c. potential efficiently. 
   When an amplifier or the like is not provided in a later stage, the RF/DC-conversion circuit  12  itself constitutes a start signal outputting circuit. 
   (Third Embodiment) 
   As a third embodiment of the invention, an RF/DC-conversion circuit  150  obtained by making the RF/DC-conversion circuit  12  of  FIG. 2  a differential type is shown in  FIG. 4 . The RF/DC-conversion circuit  150  is made up of a matching circuit  110 , a differential RF/DC convertor part  100 , and a filter part  120 . A high frequency signal is inputted to the differential RF/DC convertor part  100  through the matching circuit  110 . The differential RF/DC convertor part  100  has substantially the same construction as the four transistors of the RF/DC-conversion circuit  12  of  FIG. 2  in duplicate, and has two d.c. outputs. The filter part  120  performs low-pass filtering on each of the two d.c. outputs of the differential RF/DC convertor part  100 . Of the differential RF/DC convertor part  100  of the RF/DC-conversion circuit  150  of  FIG. 4 , the construction which converts a high frequency wave to a d.c. potential is made up of npn transistors Q RD , Q R1 , Q R2 , Q R3  and resistances R R1 , R R2 , R R3 , which correspond to the npn transistors Q D , Q 1 , Q 2 , Q 3  and the resistances R 1 , R′ 2 , R 3  of the RF/DC-conversion circuit  12  of  FIG. 2  and are connected in substantially the same way. What is different is that whereas in the RF/DC-conversion circuit  12  of  FIG. 2  three bias potentials B 0 , B 1 , and B 3  were used, in the differential RF/DC convertor part  100  of the RF/DC-conversion circuit  150  of  FIG. 4  only two bias potentials V B0  and V B1  are needed. The bias potential V B0  supplies a collector bias potential of the npn transistors Q R1  and Q R3  and via the resistance R R1  a base bias potential to the npn transistor Q R1 . The bias potential V B1  supplies a base bias potential of the npn transistor Q R3  via the resistance R R3 . In this way, a high frequency wave is inputted to the anode side of the npn transistor Q RD , and a d.c. potential is outputted from the cathode side. 
   The differential RF/DC convertor part  100  of the RF/DC-conversion circuit  150  of  FIG. 4  has a construction which does not input the high frequency wave directly, and this construction is made-up of npn transistors Q DD , Q D1 , Q D2 , Q D3  and resistances R D1 , R D2  and R D3 . To the anode side of the npn transistor Q DD  on this high frequency non-converting side, only the bias V B0  is applied via the resistance R D1  and the npn transistor Q D1 . As a result, fluctuation of the bias potential is removed by the difference between the cathode side output of the npn transistor Q RD  on the high frequency converting side and the cathode side output of the npn transistor Q DD  on the high frequency non-converting side being taken, and only the d.c. potential derived from the conversion of the high frequency power is outputted. 
   In the filter part  120 , with respect to the two outputs of the differential RF/DC convertor part  100 , shorts with respect to the carrier frequency are formed using respective pairs of capacitances C R1 , C R2 , C D1 , C D2  and pairs of inductances L R1 , L R2 , L D1 , L D2 . Also, the a.c. component is smoothed with respective pairs of smoothing capacitances C R3 , C R4 , C D3 , C D4 . When an amplifier or the like is not provided in a later stage, the RF/DC-conversion circuit  150  itself constitutes a start signal outputting circuit. 
   Next, characteristics of a filter part and an amplifier which constitute a second main part of the invention will be explained, using the spectrum charts of  FIG. 5A  through  FIG. 5F . When a high frequency signal of center frequency ω 0 , band Δω and amplitude A as shown in  FIG. 5A  is detected by double wave detection, it assumes the state shown in  FIG. 5B . At this time, the noise is proportional to the three triangular areas. Of these, to take out the signal around the d.c. component (ω=0), with an ordinary detection circuit a low-pass filter having the kind of characteristic shown in  FIG. 5C  is used and the signal shown in  FIG. 5D  is obtained. 
   Now, in the present invention only a d.c. potential is needed, and the purpose is not the wave detection of a high frequency signal. So, a low-pass filter of the kind shown in  FIG. 5E , which is extremely narrow with respect to the original band Δω, is used, and the signal shown in  FIG. 5F  is obtained. By this means noise also can be almost completely removed. For example, with respect to an original band Δω of 4.4 MHz, by filtering to only the low region of 2 kHz, it is possible to reduce noise to 1/1100. This is an improvement of 30 dB. 
   And, according to T. Vlasits et al, ‘A 5.8 GHz Microwave Link Automatic Debiting Applications’, Microwave Journal, July 1995, in a construction for detecting an ASK signal directly by means of a diode, the reception power which will bring the bit error rate of the received signal to 10 −6  can be expressed by means of the following Exp. 1. 
   
     
       
         
           
             
               
                 
                   P 
                   res 
                 
                 = 
                 
                   9.5 
                   ⁢ 
                   
                     
                       P 
                       TSS 
                     
                     
                       2 
                       ⁢ 
                       
                         2 
                       
                     
                   
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   
                     ( 
                     
                       unit 
                       : 
                       dBm 
                     
                     ) 
                   
                 
               
             
             
               
                 ( 
                 1 
                 ) 
               
             
           
         
       
     
   
   And according to Hewlett Packard Application note  923 , the following Exp. 2 holds. 
   
     
       
         
           
             
               
                 
                   P 
                   TSS 
                 
                 = 
                 
                   
                     - 
                     107 
                   
                   + 
                   
                     5 
                     ⁢ 
                     log 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     
                       B 
                       V 
                     
                   
                   + 
                   
                     10 
                     ⁢ 
                     log 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     
                       I 
                       d 
                     
                   
                   + 
                   
                     5 
                     ⁢ 
                     log 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     
                       { 
                       
                         
                           R 
                           A 
                         
                         + 
                         
                           
                             28 
                             
                               I 
                               d 
                             
                           
                           ⁢ 
                           
                             ( 
                             
                               1 
                               + 
                               
                                 
                                   
                                     f 
                                     N 
                                   
                                   
                                     B 
                                     V 
                                   
                                 
                                 ⁢ 
                                 ln 
                                 ⁢ 
                                 
                                   
                                     B 
                                     V 
                                   
                                   
                                     f 
                                     1 
                                   
                                 
                               
                             
                             ) 
                           
                         
                       
                       } 
                     
                   
                   + 
                   
                     10 
                     ⁢ 
                     log 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     
                       ( 
                       
                         1 
                         + 
                         
                           
                             
                               R 
                               S 
                             
                             ⁢ 
                             
                               C 
                               J 
                             
                             ⁢ 
                             
                               f 
                               2 
                             
                           
                           
                             I 
                             d 
                           
                         
                       
                       ) 
                     
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     
                       ( 
                       
                         unit 
                         ⁢ 
                         
                           : 
                         
                         ⁢ 
                         dBm 
                       
                       ) 
                     
                   
                 
               
             
             
               
                 ( 
                 2 
                 ) 
               
             
           
         
       
     
   
   Here, I d  is the diode current, and R A , R S , C j  are parameters of when an equivalent circuit is substituted for the diode. If I d =2 μA, R A =0.909 kΩ, R S =43.7Ω, C j =0.4278 pF, B v =4.4 MHz, and f=5.8 GHz, then P TSS =−52.7 dBm and P res =−47.4 dBm. Because as mentioned above in d.c. level detection an improvement of about 30 dB can be achieved, it can be seen that the sensing limit is −77 dBm. 
     FIG. 6  is a circuit diagram showing the construction of an amplifier  200  having three operational amplifier stages. The construction of the operational amplifier of the n-th stage (n=1,2,3) is mainly made up of two npn transistors Q nR , Q nD , resistances R nR , R nD  connected to the collectors of the transistors Q nR , Q nD , and a constant current circuit connected to the emitters of the transistors Q nR , Q nD . A bias potential is supplied to the collectors of the two transistors Q nR , Q nD  from a constant voltage supply V B0  via the resistances R nR , R nD , and the emitters of the two transistors Q nR , Q nD  are connected and grounded via the constant current circuit. 
   The constant current circuit is made up of an npn transistor Q in  and two resistances R inB , R inE . The collector of the npn transistor Q in  is connected to the emitters of the two transistors Q nR , Q nD . A bias potential V B2  is supplied to the base of the transistor Q in  via the resistance R inB . The emitter of the transistor Q in  is grounded via the resistance R inE . The constant voltage supply V B0  is grounded via a separate capacitance C VB02 . 
   A high frequency converting side input terminal is connected to the base of the npn transistor Q 1R  via a resistance R 0R . The collector of the npn transistor Q 1R  is connected to the base of the npn transistor Q 2R , the collector of the npn transistor Q 2R  is connected to the base of the npn transistor Q 3R , and the collector of the npn transistor Q 3R  is an output terminal. Similarly, a high frequency non-converting side input terminal is connected to the base of the npn transistor Q 1D  via a resistance R 0D ; the collector of the npn transistor Q 1D  is connected to the base of the npn transistor Q 2D ; the collector of the npn transistor Q 2D  is connected to the base of the npn transistor Q 3D ; and the collector of the npn transistor Q3 D  is an output terminal. 
   Constant current circuits are also connected to the connections between the operational amplifiers of the different stages. That is, a constant current circuit made up of an npn transistor Q i12R  and two resistances R i12RB , R i12RE  is connected to the collector of the npn transistor Q 1R  and the base of the npn transistor Q 2R . A bias potential V B3  is applied to the base of the npn transistor Q i12R . 
   The constant current circuit made up of the npn transistor Q i12R  and the two resistances R i12RB , R i12RE  is constructed in the same way as the constant current circuit made up of the npn transistor Q i1  and the two resistances R i1B , R i1E . Constant current circuits of the same construction, i.e. constant current circuits made up of an npn transistor Q i23R  and two resistances R i23RB , R i23RE , an npn transistor Q i12D  and two resistances R i12DB , R i12DE , and an npn transistor Q i23D  and two resistances R i23DB , R i23DE , are connected to the other three connections between the operational amplifiers of the different stages. 
   Differential amplifiers like this have a low-pass filtering effect when operated at a low current. Accordingly, by using low-pass filters in combination or, as described above, connecting differential amplifiers in a plurality of stages, it is possible to transmit and amplify a band of below 1/1000 compared to the band of the high frequency signal. That is, because with respect to the high frequency band only the band around d.c. is passed through low-pass filtering and amplified, sensitivity can be increased to much more than that of diode detection of related art. 
   (Fourth Embodiment) 
     FIG. 7  is a circuit diagram showing the construction of a with-filter amplifier part  250  constituting a main part of a start signal outputting circuit according to a fourth embodiment of the invention. The with-filter amplifier part  250  constitutes a start signal outputting circuit together with an RF/DC-conversion circuit of a previous stage (not shown). The with-filter amplifier part  250  has a first-stage filter part  120 , an amplifier  200 , and a second-stage filter part  210 . The construction of the first-stage filter part  120  of the with-filter amplifier part  250  of  FIG. 7  is the same as the construction of the filter part  120  of the RF/DC-conversion circuit  150  of  FIG. 4 . And, the construction of the amplifier  200  of the with-filter amplifier part  250  of  FIG. 7  is the same as the construction of the amplifier  200  of  FIG. 6 . The second-stage filter part  210  has with respect to the high frequency converting side output and the high frequency non-converting side output of the amplifier  200  filter circuits made up of inductances L R  and L D  and grounded capacitances C R0  and C D0 . That is, the high frequency converting side output and the high frequency non-converting side output of the amplifier  200  are outputted from a high frequency converting side output terminal and a high frequency non-converting side output terminal through these filter circuits. 
   The amplifying characteristic of the amplifier  200  of  FIG. 6  is shown in  FIG. 8A  and the amplifying characteristic of the with-filter amplifier part  250  of  FIG. 7  is shown in  FIG. 8B . The amplifier  200 , with no filter, of  FIG. 6  shows a gain of 88 dB in the d.c. vicinity, and with increasing frequency the gain decreases monotonously to 35 dB at 5 MHz ( FIG. 8A ). This is a result of the differential amplifier having the effect of a low-pass filter. The with-filter amplifier part  250  of  FIG. 7  has about the same gain in the d.c. vicinity as the amplifier  200  of  FIG. 6  without a filter, but the gain at 2 kHz is greatly reduced to 22 dB and at 40 kHz and over it is no greater than 0 dB ( FIG. 8B ). This shows that in the with-filter amplifier part  250  of  FIG. 7  the first-stage filter part  120  and the second-stage filter part  210  are fulfilling the role of an extremely narrow low-pass filter. To remove the unwanted high frequency component like this, it is desirable that the amplifying characteristic of the amplifier part decrease monotonously with frequency, and the steeper the slope of that decrease the more efficiently the high frequency component can be removed. 
   (Fifth Embodiment) 
     FIG. 9  is a circuit diagram showing the construction of a start signal outputting circuit  1000  according to a fifth embodiment of the invention. The start signal outputting circuit  1000  is made up of a matching circuit  110 , a differential RF/DC convertor part  100 , a first-stage filter part  120 , an amplifier  200 , a second-stage filter part  210 , a constant voltage source  300 , and bias potential generating circuits  301 ,  302 , and  303 . The start signal outputting circuit  1000  of  FIG. 9  consists of the construction of the with-filter amplifier part  250  apart from the first-stage filter part  120  added to the RF/DC-conversion circuit  150  of  FIG. 4 . 
   In  FIG. 9 , to avoid complexity, many of the reference numerals of the constituent devices of the seven constant current circuits of the amplifier  200  have been omitted. However, its construction is exactly the same as the amplifier  200  of  FIG. 6  and  FIG. 7 , and the same reference numerals as those of the corresponding devices should of course be assigned. And, in  FIG. 9 , the wiring between the constant voltage source  300  and the supply destination of the potential V B0  from the constant voltage source  300 , and between the bias potential generating circuits  301 ,  302 , and  303  and the supply destinations of their bias potentials V B1 , V B2 , V B3  is not shown. 
   The matching circuit  110  is made up of a capacitance C 00  for removing an inputted d.c. component (this may be outside the matching circuit, i.e. as a previous stage), an open half stub S H , a grounded capacitance C 0  and a stub S. The differential RF/DC convertor part  100  is the same construction as the differential RF/DC convertor part  100  of  FIG. 4  and is supplied with the potential V B0  from the constant voltage source  300  and the bias potential V B1  from the bias potential generating circuit  301 . The constructions of the first-stage filter part  120 , the amplifier  200  and the second-stage filter part  210  are exactly the same as in  FIG. 7 , and the amplifier  200  is supplied with the potential V B0  from the constant voltage source  300  and the bias potentials V B2 , V B3  from the bias potential generating circuits  302 ,  303 . 
   The bias potential generating circuit  301  is constructed using an npn transistor Q B1 . A resistance R B11  is connected to the collector of the transistor Q B1 , a resistance R B12  to the emitter, and resistances R B11 , R B14  to the base. The other ends of the resistance R B12  and the resistance R B14  are grounded, and the potential V B0  from the constant voltage source  300  is supplied to the other ends of the resistances R B11  and R B13 . The bias potential V B1  is made the collector potential of the transistor Q B1 . 
   The bias potential generating circuit  302  is constructed using an npn transistor Q B2 . A resistance R B21  is connected to the collector of the transistor Q B2  and a resistance R B22  to the emitter. One end of a resistance R B25  is connected to the base of the npn transistor Q B2 , and resistances R B23 , R B24  are connected to the other end of the resistance R B25 . The other ends of the resistances R B22 , R B24  are grounded, and the potential V B0  from the constant voltage source  300  is supplied to the other ends of the resistances R B21  and R B23 . The bias voltage V B2  is made the base potential of the transistor Q B2 . 
   The bias potential generating circuit  303  is constructed using an npn transistor Q B3 . A resistance R B31  is connected to the collector of the transistor Q B3 , a resistance R B32  to the emitter and a resistance R B35  and a resistance R B36  to the base. Resistances R B33  and R B34  are each connected to the other end of the resistance R B35 . The other ends of the resistances R B32  and R B34  are grounded, and the potential V B0  from the constant voltage source  300  is supplied to the other ends of the resistances R B31  and R B33 . The bias potential V B3  is made the potential of the other end of the resistance R B36  connected to the base of the transistor Q B3 . 
     FIGS. 10A and 10B  are characteristic charts showing characteristics of the start signal outputting circuit  1000  of  FIG. 9 . Of these,  FIG. 10A  is the differential output of the first-stage filter part  120  (the difference between the potential of the two terminals) when an inputted high frequency power is varied, and  FIG. 10B  is the differential output of the second-stage filter part  210  (the difference between the potential of the two terminals) when an inputted high frequency power is varied. As shown in  FIG. 10A , even when the inputted high frequency power is weak, at −70 dBm, with the differential RF/DC convertor part  100  a conversion output (d.c. potential) of about 1 μV can be obtained. When the inputted high frequency power is −60 dBm, a conversion output of about 10 μV is obtained with the differential RF/DC convertor part  100 , and after three-stage amplification a d.c. output of 0.3V can be obtained. When the high frequency power is −40 dBm or above, a conversion output (d.c. potential) of 10 mV or above is obtained with the differential RF/DC convertor part  100 , and after three-stage amplification a d.c. output of 2.4V can be obtained. 
   Thus, with this invention, it is possible to construct a start signal outputting circuit for outputting a start signal for starting a communication device when it receives a designated high frequency wave. Any of the circuits set forth in the above embodiments can be integrated extremely easily, and because only a current of 2 to 3 μA flows, the power consumed in high frequency wave ‘standby time’ is also extremely low. And, when an amplifier is used, because the current flowing through this amplifier is also extremely small, the threshold frequency of the low-pass filter action is lowered, the low-pass filtering is more sure, and low power consumption can also be achieved. 
   INDUSTRIAL APPLICABILITY  
   The start signal outputting circuit of this invention generates a d.c. potential by converting a high frequency signal and uses this d.c. potential as a starting signal of a designated device. Accordingly, the start signal outputting circuit of this invention is suitable for use in receivers for receiving command signals wirelessly. Therefore, fields of application of the invention include for example ITS, LAN and monitoring systems including ETC. For example in the field of ITS, it is possible to realize an electronic number plate which communicates a vehicle number only when a gate is to be passed through, and at other times does not perform such communication. And for example in a monitoring system, it is possible to realize an ID card which transmits an ID only when a user is entering or leaving a room. In this way, by using a start signal outputting circuit according to the invention, it is possible to cause a primary battery of a communication device to be consumed only when necessary, whereby the invention is extremely useful and has an extremely wide range of applications.