Patent Publication Number: US-9431550-B2

Title: Trench polysilicon diode

Description:
RELATED APPLICATIONS 
     This is a Divisional Application of commonly owned U.S. patent application Ser. No. 12/611,865, now U.S. Pat. No. 8,072,013, filed Nov. 3, 2009, entitled “Trench Polysilicon Diode” to Chen et al., which in turn was a Continuation Application of commonly owned U.S. patent application Ser. No. 12/009,379, now U.S. Pat. No. 7,612,431, filed Jan. 17, 2008, entitled “Trench Polysilicon Diode” to Chen et al., which in turn was a Divisional application of U.S. patent application Ser. No. 11/322,040, now U.S. Pat. No. 7,544,545, filed Dec. 28, 2005. All applications are hereby incorporated by reference herein in their entirety. 
    
    
     FIELD OF INVENTION 
     Metal oxide semiconductor (MOS) integrated circuits (ICs) receive input signals through the gate of a MOS transistor. If a high voltage input signal is applied to the gate terminal, the gate oxide layer may be unable to withstand the high voltage and break down. When semiconductor devices are transported by humans or machines, higher than normal input voltages may be produced resulting in damage to the device. 
     However, the causes of abnormally high voltages are many. For example, electric charges can be produced by friction between surfaces or when an IC is unpacked from plastic packaging. Static electricity can range from several hundreds volts to several thousand volts. If such high voltages are applied to the pins of an IC package, voltage breakdown of the gate oxide layer of a transistor within the package can occur which would result in the transistor being inoperative. As a result, the entire IC could be rendered inoperative. 
     To prevent such damages to the MOS transistors, protective circuits are connected to pins of an IC package. Such protective circuits are typically connected between each input/output (I/O) pad and the integrated circuit. The protective circuits are designed to conduct when a high voltage is applied to the I/O pad. Hence, these protective circuits provide an electrical path to, e.g., ground, to safely discharge the high voltage. 
     A surface-formed Zener diode is preferred for ESD (electro-static discharge) protection in MOSFET devices. However, as feature sizes of semiconductor IC devices are reduced, it is important to have flat surfaces for lithography processes to print small features and therefore achieve higher circuit density. A conventional surface-formed polysilicon Zener diode increases surface topology, which reduces the ability to print small features during lithography. 
     SUMMARY OF THE INVENTION 
     Embodiments of the present invention include a method of manufacturing a trench polysilicon diode. The method includes forming a substrate of a first conductivity type and implanting a dopant of a second conductivity type, forming a body region of the substrate. The method further includes forming a trench in the body region and depositing an insulating layer in the trench and over the body region wherein the insulating layer lines the trench. The method further includes filling the trench with polysilicon forming a top surface of the trench and forming a diode in the body region wherein a portion of the diode is lower than the top surface of the trench. 
     Embodiments of the present invention further include a trench transistor comprising electrostatic discharge protection. The trench transistor comprising a substrate of a first conductivity type and a body region over the substrate, wherein the body region comprises a second conductivity type. A trench is formed in the body region, wherein the trench comprises a top surface. An insulating layer lines the trench and is formed over the body region. The trench transistor further comprises a diode formed in the body layer such that a portion of the diode is formed below the top surface of the trench. 
     The trench polysilicon diode of the present invention significantly reduces the topology of the silicon surface by locating the ESD structure in the silicon. Conventional diode ESD structures are located on the surface of the silicon and increase the topology of the silicon, reducing feature density. In one embodiment of the invention, modifying the stripe source block can specify different breakdown voltages of the ESD structure. In one embodiment of the invention, the trench diode can be also used for clamping and temperature sensing. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments of the present invention and, together with the description, serve to explain the principles of the invention: 
         FIGS. 1A, 1B, 1C, 1D, 1E, 1F, 1G, 1H, 1I, 1J, 1K, and 1L  are illustrations of various steps performed during exemplary method of manufacturing a trench transistor comprising a trench polysilicon diode in accordance with embodiments of the present invention. 
         FIG. 2A  is an illustration of an exemplary single stripe trench polysilicon diode in accordance with embodiments of the present invention. 
         FIG. 2B  is an illustration of a first cross section view of a single stripe trench polysilicon diode in accordance with embodiments of the present invention. 
         FIG. 2C  is an illustration of a second cross section view of a single stripe trench polysilicon diode in accordance with embodiments of the present invention. 
         FIG. 3A  is an illustration of a double stripe trench polysilicon diode in accordance with embodiments of the present invention. 
         FIG. 3B  is an illustration of a cross section view of a double stripe trench polysilicon diode in accordance with embodiments of the present invention. 
         FIG. 3C  is a schematic of an exemplary single stage trench polysilicon Zener diode for ESD protection in accordance with embodiments of the present invention. 
         FIG. 3D  is a schematic of an exemplary dual stage polysilicon Zener diode for ESD protection in accordance with embodiments of the present invention. 
         FIG. 4  is a process flow chart of an exemplary method for manufacturing a trench polysilicon diode in accordance with embodiments of the present invention. 
         FIG. 5A  is an illustration of a temperature sensing circuit comprising vertical trench polysilicon diodes in accordance with embodiments of the present invention. 
         FIG. 5B  is a schematic of an exemplary system for sensing temperature comprising vertical trench diodes in accordance with embodiments of the present invention. 
     
    
    
     DETAILED DESCRIPTION 
     Reference will now be made in detail to the various embodiments of the present invention, examples of which are illustrated in the accompanying drawings. While the invention will be described in conjunction with these embodiments, it will be understood that they are not intended to limit the invention to these embodiments. On the contrary, the invention is intended to cover alternatives, modifications and equivalents, which may be included within the spirit and scope of the invention as defined by the appended claims. 
     Furthermore, in the following detailed description of present invention, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be understood that the present invention may be practiced without these specific details. In other instances, well-known methods, procedures, components, and circuits have not been described in detail so as not to unnecessarily obscure aspects of the present invention. 
     Embodiments of the present invention include a method and structure of a trench polysilicon diode. The trench polysilicon diode of the present invention significantly reduces the topology of the silicon surface by locating the diode structure in the silicon. Conventional diode ESD structures are located on the surface of the silicon and increase the topology of the silicon, reducing feature density. In one embodiment of the invention, modifying the diode implantations can specify different breakdown voltages of the ESD structure. In one embodiment of the invention, the trench diode can be used for clamping and temperature sensing. In one embodiment of the invention, a Zener diode is formed for SD protection and clamping and a trench diode is formed for temperature sensing. 
       FIGS. 1A, 1B, 1C, 1D, 1E, 1F, 1G, 1   h ,  1 I,  1 J,  1 K, and  1 L are illustrations of various steps performed during exemplary method of manufacturing a vertical trench polysilicon diode in accordance with embodiments of the present invention. 
     In  FIG. 1A , an N− doped epitaxial layer  102  is formed over a conventionally N+ doped substrate  101 . An oxide pad  103  is formed over the N− doped epitaxial layer  102 . In one embodiment of the invention, the oxide pad is approximately 300 angstroms in thickness. In one embodiment of the invention, the oxide pad comprises SiO2. A polysilicon layer  104  is formed over the oxide pad  103 . In one embodiment of the invention, polysilicon layer  104  is approximately two thousand angstroms in thickness. 
     A photoresist layer  105  is used to mask the location of a trench  120 .  FIG. 1A  is an illustration of the semiconductor device after the trench formation. In one embodiment of the invention, the trench  120  is an electrostatic discharge (ESD) trench. In another embodiment of the invention, the trench  120  is part of a trench diode used for a clamping function or for a temperature sensing function. 
     In  FIG. 1B , the photoresist layer  105  (of  FIG. 1A ) is removed and an insulating layer  122  is formed on the inside of the trench  120 . In one embodiment of the invention, the insulating layer comprises an oxide. In one embodiment of the invention, the insulating layer is three thousand angstroms in thickness. In one embodiment of the invention, the thickness of the insulating layer  122  depends on the desired protection rating of the diode ESD protection device. For example, a thicker insulating layer  122  will provide a higher protection rating than a thinner insulating layer  122 . In one embodiment of the invention, an insulating layer  122  of three thousand angstroms comprises a breakdown voltage (By) greater than 40 volts. In one embodiment of the invention, the insulating layer  122  is deposited on the top surface of the polysilicon layer  104 . 
     In  FIG. 1C , a polysilicon layer  140  is deposited to fill the trench  120 . In one embodiment of the invention, the polysilicon layer  140  is 1.5 micrometers thick. The polysilicon layer  140  is deposited over the insulating layer  122 . In one embodiment of the invention, the polysilicon layer is deposited over the surface of polysilicon layer  104 . In this embodiment of the invention, the oxide layer  122  (when deposited over the polysilicon layer  104 ) serves as an etch stop.  FIG. 1C  is an illustration after etchback of the polysilicon layer  140 . The remaining polysilicon  140  fills the trench  120 . In one embodiment of the invention the trench is filled such that the top of the trench is level with the top layer of the substrate. 
     In  FIG. 1D , the oxide pad layer  103  and the polysilicon layer  104  are removed. In one embodiment of the invention, the oxide pad layer  103  and the polysilicon layer  104  are removed simultaneously. In one embodiment of the invention, a buffer oxide etch or an HF etch are used to remove the oxide pad layer  103  and the polysilicon layer  104 . 
     In  FIG. 1E , one or more MOSFET transistor trenches  155  are formed adjacent to the diode (ESD) trenches  120 . A trench mask (photoresist)  150  masks the location for the MOSFET transistor trenches  155 . In one embodiment of the invention, conventional manufacture process is used to form the MOSFET trenches  155 . 
     In  FIG. 1F , the photoresist  150  is removed and a gate oxide layer  160  is deposited and lines the MOSFET trenches  155 . The gate oxide layer  160  is also deposited on the top of the polysilicon  140  that fills the diode (ESD) trenches  120 . A gate polysilicon layer  161  is deposited over the gate oxide layer  160 . In one embodiment of the invention, the gate polysilicon  161  is approximately one micrometer in thickness. 
     In  FIG. 1G , the gate polysilicon  161  is etched back and a remaining portion of the gate polysilicon  161  fills the MOSFET trench  155 . In one embodiment of the invention, gate doping can be performed at this step. In one embodiment of the invention, a POCL3 doping is used for the gate doping. 
     In  FIG. 1H , mask  170  is used to protect the MOSFET trenches  155  from an ESD implant  171  to form a P+ type of trench polysilicon diode  175  (of  FIG. 1I ). The ESD implant can be modified to tune the characteristics of the trench polysilicon diode of the present invention. For example, different implant chemicals can be used for different breakdown voltages of the diode. 
     In  FIG. 1I , a body implant is performed. In one embodiment of the invention, a body block mask is used to form the body implant area. In one embodiment of the invention, the body implant is driven in after implantation. 
     In  FIG. 1J , a source block mask is used to form the source implant area and N+ conductivity type regions  180  are formed. The undoped polysilicon region  140  of  FIG. 1G  is now an N+ doped region  180 . 
     In  FIGS. 1K and 1L , the trench transistors  155  are completed in a conventional manner. In  FIG. 1K , BPSG (BoroPhosphoSilicate Glass) regions  181  associated with the source and gate electrodes are patterned and formed and LTO (low temperature oxide) regions  179  are formed. In one embodiment of the invention, a contact mask is used during a contact implant to form a contact. After contact formation, in one embodiment of the invention, a clamping implant can be performed when a clamping function is desired. 
     In  FIG. 1L , metallization  199  is performed to complete the source/drain side  189  of the MOSFET transistor and the ESD side  190 . 
       FIG. 2A  is an illustration of a single stripe vertical trench polysilicon Zener diode cell layout in accordance with embodiments of the present invention. The gate side  200  comprises an N+ conductivity region  203  and a gate contact  204 . The ground side  206  also comprises an N+ conductivity region  203  and a ground contact  214 . A P type conductivity region  201  is between the N+ conductivity regions  203 . 
     The NPN (e.g., N+  203 , P  201 , N+  203 ) region forms the trench polysilicon Zener diode of the present invention. In one embodiment of the trench polysilicon Zener diode of the present invention is used for ESD protection. In one embodiment of the invention, multiple polysilicon trench Zener diodes can be coupled (e.g., in parallel) to achieve different ESD protection ratings. 
     In another embodiment of the invention, the trench polysilicon Zener diode of the present invention is used for a clamping function. In another embodiment of the invention, a trench polysilicon diode of the present invention can be used for temperature sensing. A cross section of the trench polysilicon Zener diode of  FIG. 2A  can be viewed by bisecting the Zener diode along an axis from A  210  to A′  216  (as illustrated in  FIG. 2B . 
       FIG. 2B  is a cross section of the vertical trench polysilicon diode of  FIG. 2A  from A  210  to A′  216  (of  FIG. 2A ). The NPN formation corresponds to the trench polysilicon Zener diode  280  of  FIG. 2B . 
       FIG. 3A  is an illustration of a double stripe vertical trench polysilicon Zener diode cell layout in accordance with embodiments of the present invention. The gate side  300  comprises an N+ conductivity region  303  and a gate contact  304 . The ground side  306  comprises an N+ conductivity region  303  and a ground contact  314 . Two P type conductivity regions  301  are between the N+ conductivity regions  203 . Between the two P type conductivity regions  301  is another N+ type conductivity region  303 . The NPNPN region forms a plurality of trench polysilicon diodes of the present invention. In one embodiment of the plurality of trench polysilicon diodes of the present invention are coupled and used for ESD protection. A cross section of the trench polysilicon Zener diode of  FIG. 3A  can be viewed by bisecting the Zener diode along an axis from C  310  to C′  316  (as illustrated in  FIG. 3B . 
       FIG. 3B  is a cross section of the vertical trench polysilicon Zener diode of  FIG. 3A  from C  310  to C′  316  (of  FIG. 3A ). The NPNPN formation corresponds to a plurality of trench polysilicon Zener diodes  380  of  FIG. 3B  coupled together. 
       FIG. 3C  is a schematic of a single stage ESD protection circuit  380  comprising a vertical trench polysilicon Zener diode  381  in accordance with embodiments of the present invention. 
       FIG. 4  is a flow diagram of an exemplary method for manufacturing a vertical trench polysilicon diode in accordance with embodiments of the present invention. In one embodiment of the invention, the resulting trench polysilicon Zener diode of process  400  is used for ESD protection. In another embodiment of the invention, the resulting trench polysilicon diode of process  400  is used for temperature sensing and/or a clamping function. It is appreciated that method  400  can also be used for manufacturing a trench polysilicon diode that can be used for temperature sensing. 
     At step  402 , process  400  includes forming a substrate of a first conductivity type. 
     At step  404 , process  400  includes implanting a dopant of a second conductivity type, which forms a body region of the substrate formed in step  402 . 
     At step  406 , process  400  includes forming a trench in the body region formed in step  404 . In one embodiment of the invention, the trench formed in step  406  is an ESD trench. 
     At step  408 , process  400  includes depositing an insulating layer in the trench formed in step  406  and over the body region wherein the insulating layer lines the trench. In one embodiment of the invention, the thickness of the insulating layer and the material used for the insulating layer can be modified to achieve a desired breakdown voltage and ESD rating for the finished diode. 
     At step  410 , process  400  includes filling the trench with polysilicon forming a top surface of the trench. 
     At step  412 , process  400  includes forming a diode in the body region wherein a portion of the diode is lower than the top surface of the trench. In one embodiment of the invention, performing a sequence of implants forms the diode. A first implant is performed to dope the polysilicon deposited in the trench (forming an N+ conductivity region) and a second implant is performed in the body region (forming a P+ type conductivity region). 
       FIG. 5A  is an illustration of an exemplary circuit  500   a  for sensing temperature in accordance with embodiments of the present invention. The temperature sensor  500   a  comprises vertical trench polysilicon diodes  510  and  520 . The trench polysilicon diodes  510  and  520  are electrically coupled in anti-parallel and are electrically coupled to pins one  501  and two  504 . 
     Trench diode  510  comprises a region of n type conductivity  512  and a region of p type conductivity  511 . Diode  510  is electrically coupled to pin one  502  via contact  513  and is electrically coupled to pin two  504  via contact  514 . 
     Trench diode  520  comprises a region of n type conductivity  521  and a region of p type conductivity  522 . Diode  520  is electrically coupled to pin one  502  via contact  523  and is electrically coupled to pin two  504  via contact  524 . 
     A temperature can be determined by measuring a voltage between pin one  502  and pin two  504 . A look-up table can be used to determine corresponding temperatures for a plurality of voltages. 
       FIG. 5B  is a schematic view of the temperature sensor  500   a  of  FIG. 5A . Trench polysilicon diodes  510  and  520  are electrically coupled to pins one  502  and two  504 . A voltage can be measured between pin one  502  and pin two  504  and a corresponding temperature can be determined by a look-up table, for example. It is appreciated that any number of methods of retrieving a corresponding temperature for a given voltage can be used in accordance with embodiments of the invention. 
     Embodiments of the present invention, a vertical trench polysilicon diode have been described. While the present invention has been described in particular embodiments, it should be appreciated that the present invention should not be construed as limited by such embodiments, but rather construed according to the following Claims.