Patent Publication Number: US-8121119-B2

Title: Point-to multipoint (P2MP) network resource management

Description:
BACKGROUND 
     Point to multipoint (P2MP) topology is one of the most commonly used topologies in an access network. In general, P2MP may include a root station (RS) and a number of leaf stations (LSs). In P2MP, any media having a RS that broadcasts packets through a single trunk (such as a frequency, wavelength, or wireless channel) to LSs typically may be referred to as downstream. Similarly, LSs unicasting packets through branches and the trunk to the RS may be referred to as upstream. In addition, the LSs may not communicate with each other in a peer-to-peer manner. 
     Many wired broadband access networks such as the Time Division Multiplex (TDM) Passive Optical Network (PON) (which includes Ethernet passive optical networks (EPONs), Gigabit passive optical networks (GPONs), and Broadband passive optical networks (BPONs)), can be generalized into a P2MP architecture. The P2MP architecture of PONs may reduce the dominant deployment and maintenance cost, and facilitates the central management by utilizing the RS as the central office. 
     In the recent past, there have been attempts to address upstream resource management and allocation mechanism issues in P2MP networks, especially in P2MP EPON networks. These schemes may be categorized into three categories: fixed resource allocation (FRA), request-based resource allocation (RRA), and prediction-based resource allocation (PRA). Although most of the schemes address the resource management in EPONs, they can be generalized to other P2MP networks by employing appropriate MAC control cells and fields in the frames. 
     Although attempts have been made to address the upstream resource management issue in P2MP networks, few attempts have addressed the above different resource management schemes such that these schemes can be evaluated, compared and further improved. Furthermore, few current upstream resource allocation schemes in a P2MP system address queue management, which may have a significant impact in achieving high network resource utilization. 
    
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
       The foregoing and other features of the present disclosure will become more fully apparent from the following description and appended claims, taken in conjunction with the accompanying drawings. Understanding that these drawings depict only several embodiments in accordance with the disclosure and are, therefore, not to be considered limiting of its scope, the disclosure will be described with additional specificity and detail through use of the accompanying drawings. 
         FIG. 1  is a diagram of a general P2MP architecture; 
         FIG. 2  is a flowchart showing the operation of an example embodiment; 
         FIG. 3  is a flowchart showing the operation of another example embodiment; 
         FIG. 4  is a flowchart showing the operation of yet another example embodiment; 
         FIG. 5  is a diagram depicting service cycles over time in an example embodiment of a P2MP architecture; 
         FIG. 6  is a schematic diagram of an example embodiment of a control system; 
         FIG. 7  is a schematic diagram of another example embodiment of a control system; and 
         FIG. 8  is a block diagram of an example computing device that is arranged for point-to-multipoint (P2MP) network resource management, all arranged in accordance with the present disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     In the following detailed description, reference is made to the accompanying drawings, which form a part hereof. In the drawings, similar symbols typically identify similar components, unless context dictates otherwise. The illustrative embodiments described in the detailed description, drawings, and claims are not meant to be limiting. Other embodiments may be utilized, and other changes may be made, without departing from the spirit or scope of the subject matter presented here. It will be readily understood that the aspects of the present disclosure, as generally described herein, and illustrated in the Figures, can be arranged, substituted, combined, and designed in a wide variety of different configurations, all of which are explicitly contemplated and make part of this disclosure. 
     This disclosure is drawn, inter alia, to methods and systems related to systems and methods for efficient resource management in P2MP networks. 
       FIG. 1  is a diagram of a general point-to-multipoint (P2MP) architecture arranged in accordance with the present disclosure. As show in  FIG. 1 , a control system for use with a point-to-multipoint (P2MP) network resource management system may include at least one root station  10  (identified in  FIG. 1  as RS- 1 , RS- 2  and RS-n, where n may be any numeral) adapted to transmit and receive network packets, and at least one leaf station  12  (identified in  FIG. 1  as LS- 1 , LS- 2  and LS-n, where n may be any numeral) may be adapted to transmit and receive network packets from the at least one root station  10 . Each leaf station  12  may be in communication with the root station(s)  10 . The control system may include a resource management component  14  adapted to manage network packet transmission that may include a reference input signal  16 , a compensator  18 , a comparator  20 , a controller  22 , and a feedback loop  24 . 
     The compensator  18  may be operably connected to the reference input signal  16 . The compensator  18  may be adapted to offset a control error (which may be the difference between the reference input signal  16  and an output signal  26 , for example). The compensator  18  may be further adapted to drive the control error toward a zero value. The comparator  20  may be adapted to calculate the control error and may be operably connected to the compensator  18 . The controller  22  may be adapted to output the output signal  26 . Further, the controller  22  may be adapted to manipulate the output signal  26  if the control error is determined to be a non-zero value. The feedback loop  24  may be operably connected to the controller  22  and the comparator  20 . Further, the feedback loop  24  may include a controller gain (which may be multiplied by or otherwise combined with the output signal  26 ). 
     In some example embodiments, the controller  22  may be configured to adjust the controller gain to manipulate the output signal  26  such that specific characteristics of the output signal  26  may be attained. Design objectives for resource allocation in a P2MP system may include system robustness, accuracy, and target transient performance. These objectives (and others) may be achieved through proper design of the compensator  20 , as discussed below. 
     Some additional example embodiments may include a method for an electrical control system to manage resources in a point-to-multipoint (P2MP) network, which may operate as depicted by the flowchart in  FIG. 2 . The illustrated embodiment may include one or more of processing operations  28 ,  30  and  32 . Operation  28  may include controlling the at least one root station based, at least in part, on output of the electrical control system, wherein the electrical control system is configured to reduce an amount of time for the electrical control system to produce an output comprising a steady state and also configured to define a maximum boundary for the output, the electrical control system comprising a feedback control loop and a compensator, wherein the compensator is adapted to adjust a control error toward a zero value and to adjust the output toward the steady state. Operation  30  may include transmitting the one or more network packets to the at least one leaf station, wherein the at least one root station is capable of transmitting and receiving the one or more network packets from the at least one root station, and wherein the at least one leaf station is capable of communication with the at least one root station. Operation  32  may include repeating the controlling and transmitting for at least one of the one or more network packets. 
     In some example embodiments, a point-to-multipoint (P2MP) network architecture may be configured to implement the method of  FIG. 2 . 
     Additional example embodiments may include a method for an electrical control system to manage resources in a point-to-multipoint (P2MP) network, which may operate as depicted by the flowchart in  FIG. 3 . The example embodiment may include one or more of processing operations  34 ,  36 ,  38 ,  40  and  42 . Operation  34  may include adapting a compensator for the electrical control system based, at least in part, on the equation 
                 F   i     =           [       K   i     ⁢           ⁢   1     ]     ⁡     [             A   i     -   I           B   i               C   i         0         ]         -   1       ⁡     [         0           1         ]         ,     
     ⁢     where   ⁢     
     [             A   i     -   I           B   i               C   i         0         ]           
is a non-singular matrix, where A i  is a state matrix, where B i  is an input matrix, where C i  is an output matrix, and where K i  is a controller gain for adjusting the output, wherein the electrical control system includes a controller gain for an output, a compensator for adjusting a control error toward a zero value and adjusting the output toward a steady state. Operation  36  may include repeatedly analyzing the output of the electrical control system to determine if the output is equal to a desired output. Operation  38  may include dynamically adjusting the output of the electrical control system to provide a new output by changing the controller gain until the new output achieves the desired output. Operation  40  may include transmitting one or more network packets to one or more of the at least one leaf station and at least one root station based at least in part on the output of the electrical control system. At operation  42 , the controller gain is K i , a constant matrix and may be defined by the equation
 
             {               f   1     ⁡     (       k   11     ,     k   12     ,     k   21     ,     k   22     ,     α   i       )       =       -   2     ⁢     ⅇ       -   4     /     T   i         ⁢     cos   (     π   ⁢       log   ⁢           ⁢   r       log   ⁢           ⁢     M   i           )                         f   2     ⁡     (       k   11     ,     k   12     ,     k   21     ,     k   22     ,     α   i       )       =     ⅇ       -   2     /     T   i           ,                 
where k 11 , k 12 , k 21  and k 22  are vectors of K i , α i  is an estimate index, r is a reference input, T i  is the amount of time for the electrical control system to produce an output having a steady state, and M i  is the maximum boundary for the output.
 
     In some example embodiments, a point-to-multipoint (P2MP) network architecture may be configured to implement the method of  FIG. 3 . In one example, such a point-to-multipoint network architecture may implement the PRA scheme. 
     Additional example embodiments may include a method for an electrical control system to manage resources in a point-to-multipoint (P2MP) network, which may operate as depicted by the flowchart in  FIG. 4 . The example embodiment may include one or more of processing operations  44 ,  46 ,  48 ,  50  and  52 . Operation  44  may include adapting a compensator for the electrical control system based, at least in part, on the equation 
                 F   i     =           [       K   i     ⁢           ⁢   1     ]     ⁡     [             A   i     -   I           B   i               C   i         0         ]         -   1       ⁡     [         0           1         ]         ,     
     ⁢     where   ⁢     
     [             A   i     -   I           B   i               C   i         0         ]           
is a non-singular matrix, where A i  is a state matrix, where B i  is an input matrix, where C i  is an output matrix, and where K i  is a controller gain for adjusting the output, wherein the electrical control system includes a controller gain for an output, a compensator for adjusting a control error toward a zero value and adjusting the output toward a steady state. Operation  46  may include repeatedly analyzing the output of the electrical control system to determine if the output is equal to a desired output. Operation  48  may include dynamically adjusting the output of the electrical control system to provide a new output by changing the controller gain until the new output achieves the desired output. Operation  50  may include transmitting one or more network packets to one or more of the at least one leaf station and at least one root station based at least in part on the output of the electrical control system. At operation  52 , the controller gain is K i , a constant matrix and may be defined by the equation
 
             {               f   1     ⁡     (       k   1     ,     k   2       )       =       -   2     ⁢     ⅇ       -   4     /     T   i         ⁢     cos   (     π   ⁢       log   ⁢           ⁢   r       log   ⁢           ⁢     M   i           )                         f   2     ⁡     (       k   1     ,     k   2       )       =     ⅇ       -   2     /     T   i           ,                 
where k 1  and k 2  are vectors of K i , r is a reference input, T i  is the amount of time for the electrical control system to produce an output comprising a steady state, and M i  is the maximum boundary for the output.
 
     In some example embodiments, a point-to-multipoint (P2MP) network architecture may be configured to implement the method of  FIG. 4 . In one example, such a point-to-multipoint network architecture may implement the RRA scheme. 
     The present disclosure now considers a P2MP system with one RS and y LSs, as depicted by the diagram in  FIG. 5 . The RS serves each LS once in a service cycle  66 ,  68 ,  70 . As previously discussed, the present disclosure contemplates that an issue with P2MP networks may include queue management for upstream resource management. A purpose of queue management may be to ensure a desired queue length Q i   d  in the LSs. The desired queue length Q i   d  may be defined as the efficient queue length to maintain high network resource utilization. Theoretically, each LS may need to maintain a desired queue length Q i   d  to avoid overflow or emptiness. If the queue length is too large, data loss and retransmission may occur due to a limited amount of available buffers. On the other hand, if the queued length becomes empty, it may indicate that the allocated resource for this LS may be more than it actually needs. The network resource may thus be wasted with low utilization. It may be desirable to avoid both extremes by maintaining a desired queue length Q i   d . 
     The upstream resource could be bandwidth (TDM-PON), wavelength (wavelength-division multiplexing or WDM-PON), or frequency (orthogonal frequency-division multiplexing or OFDM). Under the P2MP architecture, multiple LSs may share an upstream trunk, and each LS may have no knowledge of the transmission condition of the other LSs. To avoid data collision, a request/grant arbitrary mechanism, such as the multipoint control protocol (MPCP) in an EPON, may be deployed for upstream resource sharing. The request/grant mechanism may be implemented in continuous service cycles  66 ,  68 ,  70 . In each service cycle  66 ,  68 ,  70 , LSs send requests  72  to RS for a resource grant  74  before any transmission may occur. Thereafter, RS may determine an appropriate transmission window in the next service cycle  68 ,  70  to each LS, by considering the requests  72  as well as the available resources, and may send out grants  74  to LSs. Finally, after receiving the grants  74 , LSs may begin to transmit their packets until their granted window has passed. In this manner, a dynamic resource allocation may be achieved. 
     As used herein, the following notations shall be adopted.
     Q i (n): the reported residual queued length from LS i (1≦l≦y) at the end of service cycle n  66 ;   R i (n): the resource request  72  of LS i  for service cycle n  66  (R i (n) may or may not be the same as Q i (n), depending on the particular resource allocation scheme as described below);   λ i (n): the actual arrived data of LS i  at service cycle n+1  68 ;   {circumflex over (λ)} i (n): the predicted arrival data at LS i  in service cycle n+1  68 ;   d i (n): the departed data from LS i  at service cycle n  66 ;   G i (n): the allocated timeslot to LS i  at service cycle n  66 ;   G i   max : the maximum timeslot length prescribed by the service level agreement (SLA).   

     Since no queue status report may be conducted in the FRA scheme, and the reported queue length may equal zero, e.g.,
 
 Q   i ( n+ 1)=0  (Eq. 1a)
 
for FRA.
 
     In some RRA schemes, the reported queue length of transmission cycle (n+1)  68  may be determined by the difference of the injected data, which may include the transmission residual of cycle n  66  (e.g., Q i (n)) as well as the incoming data arrived in the waiting time at ONU i  in transmission cycle n  66  (e.g., λ i (n)), and the delivered data (e.g., d i (n)), e.g.,
 
 Q   i ( n+ 1)= Q   i ( n )+λ i ( n )− d   i ( n+ 1)  (Eq. 1b)
 
     In some PRA schemes, “over-grant” may occur. This “over-grant” may be adjusted by reporting the difference between the injected data (e.g., Q i (n)+λ i (n)) and the grant G i (n)  74 , e.g.,
 
 Q   i ( n+ 1)= Q   i ( n )+λ i ( n )− G   i ( n+ 1)  (Eq. 1c)
 
Eqs. 1a-1c may be summarized as
 
     
       
         
           
             
               
                 
                   
                     
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     On the other hand, the resource request R i (n)  72  of LS i  for service cycle n  66  may be determined by perspective resource allocation schemes. For FRA, the resource request of LSi in service cycle (n+1)  68  (e.g., R i (n+1)) is the fixed value R fix , e.g.,
 
 R   i ( n+ 1)= R   fix   (Eq. 2a)
 
In RRA, R i (n+1) may be determined by the reported queue length, e.g.,
 
 R   i ( n+ 1)= Q   i ( n ),  (Eq. 2b)
 
When a traffic predictor is employed, as in PRA, R i (n+1) may be determined by the sum of the reported queue length and the predicted arrival data, e.g.,
 
 R   i ( n+ 1)= Q   i ( n )+{circumflex over (λ)} i ( n )  (Eq. 2c)
 
where {circumflex over (λ)} i (n) is the predicted arrival data at LS i  in service cycle (n+1)  68 . Eq. 2a-2c may be summarized as
 
     
       
         
           
             
               
                 
                   
                     
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     After processing the request  72 , the RS allocates time windows G i (n+1) to LS i . In FRA, the assigned resource to LSi in transmission cycle n+1  68  (e.g., G i (n+1)) may be the fixed value R fix . In both RRA and PRA, G i (n+1) may be the smaller value of the bandwidth request (e.g., R i (n+1)) and the SLA parameter (e.g., G i   max ), e.g., 
     
       
         
           
             
               
                 
                   
                     
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     After receiving the bandwidth allocation decision, LS i  may schedule its upstream transmission indicated by G i (n+1), and the delivered data d i (n+1) may be described as
 
 d   i ( n+ 1)=min{ G   i ( n+ 1), Q   i ( n )+λ i ( n )}  (Eq. 4).
 
     The present disclosure considers that a unified state space model may be constructed for FRA, RRA, and PRA based, at least in part, on Eqs. 1 and 2, as follows
 
 X   i ( n+ 1)= AX   i ( n )+ BU   i ( n ),  (Eq. 5)
 
where X i (n)=[R i (n) Q i (n)] T  may be the state vector, indicating the bandwidth requirement and the queue length of LS i , and U i (n) may be the input vector, representing the arrived data during the waiting time and the SLA parameter. A and B may be the matrices for the state vector and input vector, respectively, that may determine intrinsic characteristics of each scheme at the system level.
 
     Therefore, a unified model for upstream resource allocation over a P2MP system may be established through the state space equation (Eq. 5), with Eqs. 3 and 4 being performance constraints. The model essentially exhibits the relationship between the input (e.g., on-line network traffic load), output (e.g., bandwidth allocation decision), and state variables (e.g., queue length and resource requirement). The state space representation may provide a convenient and compact way to model and analyze various resource allocation schemes for the P2MP system from the control theory point of view. In this way, a specific resource allocation scheme may essentially define its particular coefficient matrices A and B to assign the upstream resource in a different way. 
     The present disclosure contemplates that the above control objectives may have been difficult to solve in P2MP systems because of the complexity of mapping the objectives into the corresponding scheduling algorithm and resource management schemes. However, the example state space model described herein may give a simple and straightforward framework to achieve such objectives by using state space feedback control techniques. 
     In some example embodiments, the settling time T i  and the maximum overshoot M i  may be two central parameters for the transient performance. The settling time T i  may be defined as the time for the P2MP system to reach the steady state. Short settling times may be utilized to achieve the performance objective, especially when the incoming traffics of LSs have large volatility. In such case, short settling time may ensure that the system converges to the stable state before the traffic load changes. On the other side, the maximum overshoot M i  may be defined as the difference between the maximum system output y max  and steady-state system output y ss  divided by the steady-state system output y ss , e.g., 
                     M   i     =         y   max     -     y   ss         y   ss               (     Eq   .           ⁢   6     )               
The maximum overshoot may give the upper bound for the output oscillations of a P2MP system. For example, the specifications of a P2MP system may call for the system to reach a stable state within 10 seconds, and the overshoot should be less than 5%.
 
     In some embodiments, for resource allocation schemes that may be based, at least in part, on the state space model (e.g., Eq. (5)), there may exist a controller, u i (n)  76 , such that
 
 u   i ( n )=− K   i   x   i ( n ),  (Eq. 7)
 
to drive the system into a close-loop form, as long as the system is controllable; this is known as pole placement. Substituting Eq. 7 into Eq. 5 yields,
 
 x   i ( n+ 1)=( A   i   −B   i   K   i ) x   i ( n ).  (Eq. 8)
 
which is the close-loop form for Eq. 5, where K i    78  may be a constant matrix. The controller design in this embodiment is illustrated in  FIG. 6 .
 
     The present disclosure contemplates that, from the control point of view, the settling time and maximum overshoot may be determined by the closed loop poles. Further, the controller gain K i    78  in Eq. 8 may essentially determine the poles in the closed loop characteristic polynomial det[zI−(A i −B i K i )]. Thus, the target transient performance T i  and M i  may be achieved by properly tuning the controller gain K i    78 . 
     Now, the present disclosure considers that the poles of a second order P2MP system are a pair of complex conjugates re ±jθ . According to control theory, the relationship between the pole parameters r and θ, and the settling time T i  and the maximum overshoot M i  may be stated as 
                   r   ≈     ⅇ       -   4     /     T   i                 (       Eq   .           ⁢   9     ⁢   a     )               θ   ≈     π   ⁢       log   ⁢           ⁢   r       log   ⁢           ⁢     M   i                   (       Eq   .           ⁢   9     ⁢   b     )               
The eigenvalues of the closed-form characteristic polynomial det[zI−(A i −B i K i )] may be re ±jθ , or simply, det[zI−(A i −B i K i )]=(z−re jθ )(z−re −jθ ), e.g.,
 
det[ zI −( A   i   −B   i   K   i )]= z   2 −2 r  cos θ z+r   2   (Eq. 10)
 
     On the other hand, the present disclosure considers that the second order closed-form characteristic polynomial for the PRA scheme may be based, at least in part, on,
 
det[ zI −( A   i   −B   i   K   i )]= z   2   +f   1 ( k   11   ,k   12   ,k   21   ,k   22 , α i ) z+f   2 ( k   11   ,k   12   ,k   21   ,k   22 ,α i )  (Eq. 11)
 
where k 11 , k 12 , k 21  and k 22  are vectors of K i , and α i  is the estimate index.
 
     As Eqs. 10 and 11 represent the same closed-form characteristic polynomial for PRA, they have the same coefficients for each order of z. Thus, 
                   {               f   1     ⁡     (       k   11     ,     k   12     ,     k   21     ,     k   22     ,     α   i       )       =       -   2     ⁢   r   ⁢           ⁢   cos   ⁢           ⁢   θ                     f   2     ⁡     (       k   11     ,     k   12     ,     k   21     ,     k   22     ,     α   i       )       =       r   2     .                     (     Eq   .           ⁢   12     )               
By substituting Eqs. 9a and 9b into Eq. 12, the result is
 
     
       
         
           
             
               
                 
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                             ⁡ 
                             
                               ( 
                               
                                 
                                   k 
                                   11 
                                 
                                 , 
                                 
                                   k 
                                   12 
                                 
                                 , 
                                 
                                   k 
                                   21 
                                 
                                 , 
                                 
                                   k 
                                   22 
                                 
                                 , 
                                 
                                   α 
                                   i 
                                 
                               
                               ) 
                             
                           
                           = 
                           
                             
                               - 
                               2 
                             
                             ⁢ 
                             
                               ⅇ 
                               
                                 
                                   - 
                                   4 
                                 
                                 / 
                                 
                                   T 
                                   i 
                                 
                               
                             
                             ⁢ 
                             
                               cos 
                               ( 
                               
                                 π 
                                 ⁢ 
                                 
                                   
                                     log 
                                     ⁢ 
                                     
                                         
                                     
                                     ⁢ 
                                     r 
                                   
                                   
                                     log 
                                     ⁢ 
                                     
                                         
                                     
                                     ⁢ 
                                     
                                       M 
                                       i 
                                     
                                   
                                 
                               
                               ) 
                             
                           
                         
                       
                     
                     
                       
                         
                           
                             
                               f 
                               2 
                             
                             ⁡ 
                             
                               ( 
                               
                                 
                                   k 
                                   11 
                                 
                                 , 
                                 
                                   k 
                                   12 
                                 
                                 , 
                                 
                                   k 
                                   21 
                                 
                                 , 
                                 
                                   k 
                                   22 
                                 
                                 , 
                                 
                                   α 
                                   i 
                                 
                               
                               ) 
                             
                           
                           = 
                           
                             ⅇ 
                             
                               
                                 - 
                                 2 
                               
                               / 
                               
                                 T 
                                 i 
                               
                             
                           
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   
                     Eq 
                     . 
                     
                         
                     
                     ⁢ 
                     13 
                   
                   ) 
                 
               
             
           
         
       
     
     Eq. 13 provides the range of each vector of the controller gain K i    78  to reach the target settling time and maximum overshoot. The solutions of Eq. 13 also show relationships between each vector of the control gain matrix  78  and the estimate index. Although the exact value of each vector and estimate index is not given, Eq. 13 may essentially provide a guideline to design a suitable controller gain K i    78  such that the target settling time T i  and maximum overshoot M i  in the PRA scheme may be met. It is also noted that the estimate index α i  may have an impact on achieving the called for transient performance. 
     Similarly, the characteristic polynomial for the RRA scheme may be
 
det[ zI −( A   i   −B   i   K   i )]= z   2   +f   1 ( k   1   ,k   2 ) z+f   2 ( k   1   ,k   2 )  (Eq. 14)
 
where k 1  and k 2  are vectors of K i    78 .
 
     Since Eqs. 10 and 14 represent the same or similar closed-form characteristic polynomial for RRA, they may have the same or similar coefficients for each order of z. Comparing the coefficients of Eqs. 10 and 14 yields 
     
       
         
           
             
               
                 
                   { 
                   
                     
                       
                         
                           
                             
                               f 
                               1 
                             
                             ⁡ 
                             
                               ( 
                               
                                 
                                   k 
                                   1 
                                 
                                 , 
                                 
                                   k 
                                   2 
                                 
                               
                               ) 
                             
                           
                           = 
                           
                             
                               - 
                               2 
                             
                             ⁢ 
                             r 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             cos 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             θ 
                           
                         
                       
                     
                     
                       
                         
                           
                             
                               f 
                               2 
                             
                             ⁡ 
                             
                               ( 
                               
                                 
                                   k 
                                   1 
                                 
                                 , 
                                 
                                   k 
                                   2 
                                 
                               
                               ) 
                             
                           
                           = 
                           
                             r 
                             2 
                           
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   
                     Eq 
                     . 
                     
                         
                     
                     ⁢ 
                     15 
                   
                   ) 
                 
               
             
           
         
       
     
     Substituting Eqs. 9a and 9b into Eq. 15 yields 
                   {               f   1     ⁡     (       k   1     ,     k   2       )       =       -   2     ⁢     ⅇ       -   4     /     T   i         ⁢     cos   (     π   ⁢       log   ⁢           ⁢   r       log   ⁢           ⁢     M   i           )                       f   2     ⁡     (       k   1     ,     k   2       )       =     ⅇ       -   2     /     T   i                         (     Eq   .           ⁢   16     )               
Therefore, the solutions of Eq. 16 may essentially provide guidelines to design a suitable controller gain K i    78  such that the target settling time T i  and maximum overshoot M i  in RRA scheme may be met.
 
       FIG. 6  is a schematic diagram of an example embodiment of a control system arranged in accordance with the present disclosure. As shown in  FIG. 6 , the target system  80  may be achieved by feeding back proportional state variables  84  to the control input  82 . The state variables  84  may represent the on-line traffic dynamics, which may imply changes of the queue length and bandwidth requirement of an LS. The controller  76  may essentially feedback the traffic dynamics information, after multiplying by the controller gain  78 , to the input  82  of the system. By doing so, the eigenvalues of an open plant system, which is usually outside of the unit circle, may be driven back into the inside of the unit circle after implementing proper controller gains. In this manner, the system is driven into the stable state. An example controller  76  may be facilitated through the proper buffering and intra-LS scheduling schemes at the RS, or the appropriate inter-LS scheduling scheme among LSs. Thus, the RS may work as a central controller to tune LSs accordingly, which may ensure that the upstream resource of a P2MP system is fairly shared among multiple LSs. The controller gains K i | i=1,2,3,4,5,6    78  describe the controller  76  characteristics in different scenarios. 
     For PRA, the RS may manipulate the upstream transmission from multiple LSs by using a controller U i (n)=−KX i (n)  76 , where K=K i | i=1˜4    78 . The estimation index α i  may affect the system stability when designing a controller  76  for a P2MP system with PRA. In both RRA and PRA, the above equations may provide guidelines for the controller  76  design to achieve a P2MP system&#39;s stability. 
     Based, at least in part, on the models discussed above, example control system designs may now be determined. An example of one such control system design is depicted in  FIG. 7 . The present disclosure considers that design objectives typically may be an initial step in control system design. In this case, the design objectives for resource allocation in a P2MP system may be system robustness, accuracy, and target transient performance. 
     In designing a control system in one embodiment, consider the measured system output Y i (n)=CX i (n)  86 , and define matrix c=[0 1]. The system output essentially may be the measurement to the report queue length Q i (n). The state space system may then be described as
 
 X   i ( n+ 1)= AX   i ( n )+ BU   i ( n ) 90   (Eq. 17)
 
 Y   i ( n )= CX   i ( n )
 
It may be useful to design a compensator  88  to achieve the design objectives of desired queue length Q i   d .  FIG. 7  is a schematic diagram illustrating another example embodiment of a control system arranged in accordance with the present disclosure. As illustrated, an example compensator  88  may be realized by implementing the controller
 
 U   i ( n )=− K   i   X   i ( n )+ F   i   r 92  (Eq. 18)
 
to achieve the prescribed objectives. The reference input r  82  is the desired queue length, and thus e(n)=Y i (n)−r is the control error. The matrix F i    88  is a compensator to offset the control error, so that the system output  86  can eventually converge to the input reference  82  (e.g., e(n)=0). Therefore, a suitable compensator F i    88  may be determined.
 
     As discussed above, the objective of queue management for achieving the desired queue length Q i   d    82  may be mapped to how to design the compensator F i    88 , such that the queue length measurement Y i (n)  86  may converge to the system input r  82 , which may be the desired queue length. To reach this objective, in some embodiments, a compensator F i    88  may be implemented immediately after the reference  82 , and added up to the feedback from the state variable  84 , to form the controller U i (n)  92 , which is illustrated in  FIG. 7 . Therefore, a compensator F i    88  may be designed in such way to offset the control error, e.g., e(n)=0. 
     For a particular P2MP system i, the compensator F i    88  may be determined by the state matrix A i , the input matrix B i , the output matrix C i , and the controller gain K i    94 . The present disclosure contemplates that the compensator F i    88  that drives the control error e(n)=Y i (n)−r to zero may be given by 
                       F   i     =           [       K   i     ⁢           ⁢   1     ]     ⁡     [             A   i     -   I           B   i               C   i         0         ]         -   1       ⁡     [         0           1         ]         ⁢     
     ⁢     where   ⁢     
     [             A   i     -   I           B   i               C   i         0         ]             (     Eq   .           ⁢   19     )               
is a non-singular matrix.
 
     Eq. 19 may be derived by the following process. When a system output converges to the input reference  82  (e.g., e(n)=Y i (n)−r=0), the state variable X i (n)  84  may reach its steady state X i   ss . Assume the associated steady state input is U i   ss  the controller represented by Eq. 18 may be re-written as
 
 U   i ( n )=− K   i ( X   i ( n )− X   i   ss )+ U   i   ss   (Eq. 20)
 
From Eq. 20, it is shown that the system input U i (n)  92  may reach its steady state U i   ss  when the state variables X i (n)  84  reach X i   ss . Eq. 20 may be further re-written as U i (n)=−K i X i (n)+K i X i   ss +U i   ss , e.g.,
 
     
       
         
           
             
               
                 
                   
                     
                       U 
                       i 
                     
                     ⁡ 
                     
                       ( 
                       n 
                       ) 
                     
                   
                   = 
                   
                     
                       
                         - 
                         
                           K 
                           i 
                         
                       
                       ⁢ 
                       
                         
                           X 
                           i 
                         
                         ⁡ 
                         
                           ( 
                           n 
                           ) 
                         
                       
                     
                     + 
                     
                       
                         [ 
                         
                           
                             K 
                             i 
                           
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           1 
                         
                         ] 
                       
                       ⁡ 
                       
                         [ 
                         
                           
                             
                               
                                 X 
                                 i 
                                 ss 
                               
                             
                           
                           
                             
                               
                                 U 
                                 i 
                                 ss 
                               
                             
                           
                         
                         ] 
                       
                     
                   
                 
               
               
                 
                   ( 
                   
                     Eq 
                     . 
                     
                         
                     
                     ⁢ 
                     20 
                   
                   ) 
                 
               
             
           
         
       
     
     When the system reaches the steady state, the following equations may hold true,
 
 X   i   ss   =AX   i   ss   +BU   i   ss  
 
Y i   ss =CX i   ss   (Eq. 21)
 
Y i   ss =r
 
Eq. 21 further yields, (A−I)X i   ss +BU i   ss =0 e.g.,
 
CX i   ss =r
 
                       [           A   -   I         B           C       0         ]     ⁡     [           X   i   ss               U   i   ss           ]       =     [         0           r         ]             (     Eq   .           ⁢   22     )               
Therefore, from Eq. 22, the following equation may hold true,
 
                     [           X   i   ss               U   i   ss           ]     =         [           A   -   I         B           C       0         ]       -   1       ⁡     [         0           r         ]               (     Eq   .           ⁢   23     )               
provided that
 
                   [           A   -   I         B           C       0         ]           
is a non-singular matrix. From Eqs. 20 and 23, the controller may be expressed as follows,
 
     
       
         
           
             
               
                 
                   
                     
                       U 
                       i 
                     
                     ⁡ 
                     
                       ( 
                       n 
                       ) 
                     
                   
                   = 
                   
                     
                       
                         - 
                         
                           K 
                           i 
                         
                       
                       ⁢ 
                       
                         
                           X 
                           i 
                         
                         ⁡ 
                         
                           ( 
                           n 
                           ) 
                         
                       
                     
                     + 
                     
                       
                         
                           
                             
                               [ 
                               
                                 
                                   
                                     
                                       K 
                                       i 
                                     
                                   
                                   
                                     1 
                                   
                                 
                               
                               ] 
                             
                             ⁡ 
                             
                               [ 
                               
                                 
                                   
                                     
                                       A 
                                       - 
                                       I 
                                     
                                   
                                   
                                     B 
                                   
                                 
                                 
                                   
                                     C 
                                   
                                   
                                     0 
                                   
                                 
                               
                               ] 
                             
                           
                           
                             - 
                             1 
                           
                         
                         ⁡ 
                         
                           [ 
                           
                             
                               
                                 0 
                               
                             
                             
                               
                                 1 
                               
                             
                           
                           ] 
                         
                       
                       ⁢ 
                       r 
                     
                   
                 
               
               
                 
                   ( 
                   
                     Eq 
                     . 
                     
                         
                     
                     ⁢ 
                     24 
                   
                   ) 
                 
               
             
           
         
       
     
     By comparing Eqs. 18 and 24, a compensator F i    88  that may offset the control error is Eq. 19 discussed above and as follows 
     
       
         
           
             
               F 
               i 
             
             = 
             
               
                 
                   
                     
                       [ 
                       
                         
                           
                             
                               K 
                               i 
                             
                           
                           
                             1 
                           
                         
                       
                       ] 
                     
                     ⁡ 
                     
                       [ 
                       
                         
                           
                             
                               A 
                               - 
                               I 
                             
                           
                           
                             B 
                           
                         
                         
                           
                             C 
                           
                           
                             0 
                           
                         
                       
                       ] 
                     
                   
                   
                     - 
                     1 
                   
                 
                 ⁡ 
                 
                   [ 
                   
                     
                       
                         0 
                       
                     
                     
                       
                         1 
                       
                     
                   
                   ] 
                 
               
               . 
             
           
         
       
     
     Consequently, by implementing the compensator F i    88  of Eq. 19, the controller  92  of Eq. 18 may be able to force the system output Y i (n)  86  to track the reference input r  82 , implying that the queue length may be eventually driven into the desired queue length Q i   d . The compensator F i    88  may be facilitated through the proper buffering and intra-LS scheduling schemes at the LS, or the appropriate inter-LS scheduling scheme among LSs. 
     With reference to  FIG. 8 , depicted is a block diagram illustrating an example computing device  800  that is arranged for point-to-multipoint (P2MP) network resource management in accordance with the present disclosure. In a very basic configuration  801 , computing device  800  typically includes one or more processors  810  and system memory  820 . A memory bus  830  can be used for communicating between the processor  810  and the system memory  820 . 
     Depending on the desired configuration, processor  810  can be of any type including but not limited to a microprocessor (μP), a microcontroller (μC), a digital signal processor (DSP), or any combination thereof. Processor  810  can include one more levels of caching, such as a level one cache  811  and a level two cache  812 , a processor core  813 , and registers  814 . The processor core  813  can include an arithmetic logic unit (ALU), a floating point unit (FPU), a digital signal processing core (DSP Core), or any combination thereof. A memory controller  815  can also be used with the processor  810 , or in some implementations the memory controller  815  can be an internal part of the processor  810 . 
     Depending on the desired configuration, the system memory  820  can be of any type including but not limited to volatile memory (such as RAM), non-volatile memory (such as ROM, flash memory, etc.) or any combination thereof. System memory  820  typically includes an operating system  821 , one or more applications  822 , and program data  824 . Application  822  includes a point-to-multipoint (P2MP) network resource management algorithm  823  that is arranged to efficiently manage network resources in a point-to-multipoint network. Program Data  824  includes point-to-multipoint (P2MP) network resource management data  825 . In some embodiments, application  822  can be arranged to operate with program data  824  on an operating system  821  to effectuate the efficient management of network resources. This described basic configuration is illustrated in  FIG. 8  by those components within dashed line  801 . 
     Computing device  800  can have additional features or functionality, and additional interfaces to facilitate communications between the basic configuration  801  and any required devices and interfaces. For example, a bus/interface controller  840  can be used to facilitate communications between the basic configuration  801  and one or more data storage devices  850  via a storage interface bus  841 . The data storage devices  850  can be removable storage devices  851 , non-removable storage devices  852 , or a combination thereof. Examples of removable storage and non-removable storage devices include magnetic disk devices such as flexible disk drives and hard-disk drives (HDD), optical disk drives such as compact disk (CD) drives or digital versatile disk (DVD) drives, solid state drives (SSD), and tape drives to name a few. Example computer storage media can include volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information, such as computer readable instructions, data structures, program modules, or other data. 
     System memory  820 , removable storage  851  and non-removable storage  852  are all examples of computer storage media. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by computing device  800 . Any such computer storage media can be part of device  800 . 
     Computing device  800  can also include an interface bus  842  for facilitating communication from various interface devices (e.g., output interfaces, peripheral interfaces, and communication interfaces) to the basic configuration  801  via the bus/interface controller  840 . Example output devices  860  include a graphics processing unit  861  and an audio processing unit  862 , which can be configured to communicate to various external devices such as a display or speakers via one or more A/V ports  863 . Example peripheral interfaces  870  include a serial interface controller  871  or a parallel interface controller  872 , which can be configured to communicate with external devices such as input devices (e.g., keyboard, mouse, pen, voice input device, touch input device, etc.) or other peripheral devices (e.g., printer, scanner, etc.) via one or more I/O ports  873 . An example communication device  880  includes a network controller  881 , which can be arranged to facilitate communications with one or more other computing devices  890  over a network communication via one or more communication ports  882 . The communication connection is one example of a communication media. Communication media may typically be embodied by computer readable instructions, data structures, program modules, or other data in a modulated data signal, such as a carrier wave or other transport mechanism, and includes any information delivery media. A “modulated data signal” can be a signal that has one or more of its characteristics set or changed in such a manner as to encode information in the signal. By way of example, and not limitation, communication media can include wired media such as a wired network or direct-wired connection, and wireless media such as acoustic, radio frequency (RF), infrared (IR) and other wireless media. The term computer readable media as used herein can include both storage media and communication media. 
     Computing device  800  can be implemented as a portion of a small-form factor portable (or mobile) electronic device such as a cell phone, a personal data assistant (PDA), a personal media player device, a wireless web-watch device, a personal headset device, an application specific device, or a hybrid device that include any of the above functions. Computing device  800  can also be implemented as a personal computer including both laptop computer and non-laptop computer configurations. 
     According to one embodiment, computing device  800  is coupled to a networking environment such that the processor  810 , application  822  and/or program data  824  can perform with or as a point-to-multipoint (P2MP) network resource management system in accordance with embodiments herein. 
     It should also be understood that, while a stated objective of various example embodiments disclosed herein may be to “minimize” the settling time or other parameters or characteristics, it is not necessary to literally minimize any parameters or other characteristic to fall within the scope of any claim unless such specific objective is expressly claimed. Likewise, it should be understood that it is not necessary to literally “optimize” the settling time or other parameters or characteristics to fall within the scope of any claim unless such specific objective is expressly claimed. 
     The herein described subject matter sometimes illustrates different components contained within, or coupled with, different other components. It is to be understood that such depicted architectures are merely examples, and that in fact many other architectures can be implemented which achieve the same functionality. In a conceptual sense, any arrangement of components to achieve the same functionality is effectively “associated” such that the desired functionality is achieved. Hence, any two components herein combined to achieve a particular functionality can be seen as “associated with” each other such that the desired functionality is achieved, irrespective of architectures or intermedial components. Likewise, any two components so associated can also be viewed as being “operably connected”, or “operably coupled”, to each other to achieve the desired functionality, and any two components capable of being so associated can also be viewed as being “operably couplable”, to each other to achieve the desired functionality. Specific examples of operably couplable include but are not limited to physically mateable and/or physically interacting components and/or wirelessly interactable and/or wirelessly interacting components and/or logically interacting and/or logically interactable components. 
     With respect to the use of substantially any plural and/or singular terms herein, those having skill in the art can translate from the plural to the singular and/or from the singular to the plural as is appropriate to the context and/or application. The various singular/plural permutations may be expressly set forth herein for sake of clarity. 
     It will be understood by those within the art that, in general, terms used herein, and especially in the appended claims (e.g., bodies of the appended claims) are generally intended as “open” terms (e.g., the term “including” should be interpreted as “including but not limited to,” the term “having” should be interpreted as “having at least,” the term “includes” should be interpreted as “includes but is not limited to,” etc.). It will be further understood by those within the art that if a specific number of an introduced claim recitation is intended, such an intent will be explicitly recited in the claim, and in the absence of such recitation no such intent is present. For example, as an aid to understanding, the following appended claims may contain usage of the introductory phrases “at least one” and “one or more” to introduce claim recitations. However, the use of such phrases should not be construed to imply that the introduction of a claim recitation by the indefinite articles “a” or “an” limits any particular claim containing such introduced claim recitation to inventions containing only one such recitation, even when the same claim includes the introductory phrases “one or more” or “at least one” and indefinite articles such as “a” or “an” (e.g., “a” and/or “an” should typically be interpreted to mean “at least one” or “one or more”); the same holds true for the use of definite articles used to introduce claim recitations. In addition, even if a specific number of an introduced claim recitation is explicitly recited, those skilled in the art will recognize that such recitation should typically be interpreted to mean at least the recited number (e.g., the bare recitation of “two recitations,” without other modifiers, typically means at least two recitations, or two or more recitations). Furthermore, in those instances where a convention analogous to “at least one of A, B, and C, etc.” is used, in general such a construction is intended in the sense one having skill in the art would understand the convention (e.g., “a system having at least one of A, B, and C” would include but not be limited to systems that have A alone, B alone, C alone, A and B together, A and C together, B and C together, and/or A, B, and C together, etc.). In those instances where a convention analogous to “at least one of A, B, or C, etc.” is used, in general such a construction is intended in the sense one having skill in the art would understand the convention (e.g., “a system having at least one of A, B, or C” would include but not be limited to systems that have A alone, B alone, C alone, A and B together, A and C together, B and C together, and/or A, B, and C together, etc.). It will be further understood by those within the art that virtually any disjunctive word and/or phrase presenting two or more alternative terms, whether in the description, claims, or drawings, should be understood to contemplate the possibilities of including one of the terms, either of the terms, or both terms. For example, the phrase “A or B” will be understood to include the possibilities of “A” or “B” or “A and B.” 
     While various aspects and embodiments have been disclosed herein, other aspects and embodiments will be apparent to those skilled in the art. The various aspects and embodiments disclosed herein are for purposes of illustration and are not intended to be limiting, with the true scope and spirit being indicated by the following claims.