Patent Publication Number: US-2023138732-A1

Title: Transistor level interconnection methodologies utilizing 3d interconnects

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     The present application is a continuation of U.S. patent application Ser. No. 17/217,104, filed Mar. 30, 2021, which is a divisional of U.S. patent application Ser. No. 16/265,456, filed Feb. 1, 2019, which claims the benefit of the filing date of U.S. Provisional Patent Application No. 62/650,220, filed Mar. 29, 2018. The disclosures of the above applications are hereby incorporated by reference in their entireties. 
    
    
     BACKGROUND OF THE INVENTION 
     Microelectronic devices generally comprise a thin slab of a semiconductor material, such as silicon or gallium arsenide, commonly called a die or a semiconductor chip. In some unit designs, the semiconductor chip is mounted to a substrate or chip carrier, which is in turn mounted on a circuit panel, such as a printed circuit board. 
     In one face of the semiconductor chip is active circuitry. To facilitate electrical connection to the active circuitry, the chip is provided with bond pads on the same face. The bond pads are typically placed in a regular array either around the edges of the die or, for many memory devices, in the die center. 
     The sources and drains of fully-depleted silicon-on-insulator (“FD-SOI”) transistors are typically electrically accessed via conductive interconnects extending above the front surface of the top layer of silicon, in which the transistors are formed. For example,  FIG.  1 A  illustrates a first microelectronic unit  100  having a source  112  and a drain  110 , wherein the drain  110  is electrically connected to a bond pad  120  exposed through an opening at a top surface  130  of a front dielectric layer assembly  140 . The electrical connections include traces  150  that extend through numerous dielectric layers  160  of the front dielectric layer assembly  140  that overlie the buried oxide layer  180  on a silicon body layer  185 .  FIG.  1 B  illustrates a similar assembly wherein the buried oxide layer  181  is patterned to form isolation trenches on either side of the source  112  and drain  110 . Despite the advances that have been made in access to the source and drain of FD-SOI transistors, there is still a need for further improvements. 
     BRIEF SUMMARY OF THE INVENTION 
     A microelectronic unit according to an aspect of the invention may include an epitaxial silicon layer having a front silicon surface and a back silicon surface opposite the front silicon surface, a buried oxide layer having a top oxide surface and a bottom oxide surface opposite the top oxide surface, such that the top oxide surface faces the back silicon surface, an ohmic contact extending through the buried oxide layer between the top and bottom oxide surfaces, one or more dielectric layers collectively having a first dielectric surface and a second dielectric surface opposite the first dielectric surface, such that the first dielectric surface faces the bottom oxide surface, and one or more conductive elements extending through the one or more dielectric layers between the first and second dielectric surfaces. 
     The epitaxial silicon layer may be epitaxially grown over the buried oxide layer, and may have a source and a drain each extending from the front silicon surface to the back silicon surface. The source and the drain may be doped portions of the epitaxial silicon layer. The top surface of the buried oxide layer may be coupled to the back surface of the epitaxial silicon layer. For example, the epitaxy may be grown over the buried oxide layer. The ohmic contact may be coupled to a lower surface of one of the source or the drain. 
     The one or more dielectric layers may be deposited onto the bottom surface of the buried oxide layer. The conductive element may include metallization in the one or more dielectric layers that is deposited to contact a lower surface of the ohmic contact. A portion of the conductive element may be exposed at the second dielectric surface and may be configured to be coupled to an external component. 
     A microelectronic unit according to another aspect of the invention may include an epitaxial silicon layer having a front silicon surface and a back silicon surface opposite the front silicon surface, a bulk silicon layer having a top bulk surface and a bottom bulk surface opposite the top bulk surface, an ohmic contact extending through the bulk silicon layer between the top and bottom bulk surfaces, one or more dielectric layers collectively having a first dielectric surface and a second dielectric surface opposite the first dielectric surface, the first dielectric surface in contact with the bottom bulk surface and one or more conductive elements extending through the one or more dielectric layers between the first and second dielectric surfaces. 
     The epitaxial silicon layer may have a source and a drain each extending between the front and back silicon surfaces. The source and the drain may be doped portions of the epitaxial silicon layer. The top bulk surface of the bulk silicon layer may be directly in contact with the back silicon surface of the epitaxial silicon layer. The ohmic contact may be coupled to a lower surface of one of the source or the drain. The first dielectric surface of the one or more dielectric layers may be deposited to contact the bottom bulk surface of the bulk silicon layer. The conductive element may be, for example, metallization that is deposited to contact a lower surface of the ohmic contact. A portion of the conductive element may be exposed at the second dielectric surface of the one or more dielectric layers and may be configured to be coupled to an external component. 
     A method of fabricating a microelectronic unit according to yet another aspect of the invention may include providing a bulk silicon wafer, growing or depositing a buried oxide layer at an exposed surface of the bulk silicon wafer, epitaxially growing a silicon layer at a top surface of the buried oxide layer, forming a source and a drain by doping portions of the epitaxial silicon layer, removing a portion of the bulk silicon wafer from a bottom surface of the buried oxide layer, forming an ohmic contact extending through the buried oxide layer between the top and bottom surfaces, forming one or more dielectric layers having a first dielectric surface and a second dielectric surface opposite the first dielectric surface, and forming one or more conductive elements extending through the one or more dielectric layer between the first and second dielectric surfaces. 
     The bottom surface of the buried oxide layer may be adjacent the exposed surface of the bulk silicon wafer. The top surface of the buried oxide layer may be opposite the bottom surface thereof. The back surface of the epitaxial silicon layer may be adjacent the top surface of the buried oxide layer. The front silicon surface of the epitaxial silicon layer may be opposite the back silicon surface thereof. The source and the drain may each extend through the epitaxial silicon layer between the front and back silicon surfaces. The ohmic contact may be in contact with a lower surface of one of the source or the drain. The one or more dielectric layers may be deposited such that the first dielectric surface of the one or more dielectric layers contacts the bottom surface of the buried oxide layer. The conductive element may be, for example, metallization in the one or more dielectric layers that is deposited to contact a lower surface of the ohmic contact. A portion of the conductive element may be exposed at the second dielectric surface of the one or more dielectric layers and may be configured to be coupled to an external component. 
     A microelectronic assembly according to still another aspect of the invention may include a microelectronic unit and an external component having electrically conductive features at an exposed surface thereof. The microelectronic unit may include an epitaxial silicon layer having a front silicon surface and a back silicon surface opposite the front silicon surface, a buried oxide layer having a top oxide surface and a bottom oxide surface opposite the top oxide surface, an ohmic contact extending through the buried oxide layer between the top and bottom oxide surfaces, one or more dielectric layers having a first dielectric surface and a second dielectric surface opposite the first dielectric surface, and one or more conductive elements extending through the one or more dielectric layers between the first and second dielectric surfaces. 
     The epitaxial silicon layer may have a source and a drain each extending between the front and back silicon surfaces. The source and the drain may be doped portions of the epitaxial silicon layer. The top oxide surface of the buried oxide layer may be in direct contact with the back silicon surface of the epitaxial silicon layer. The ohmic contact may be coupled to a lower surface of one of the source or the drain. The one or more dielectric layers may be deposited onto the bottom surface of the buried oxide layer. The one or more conductive elements may be, for example, metallizations deposited in the one or more dielectric layers, such that the one or more conductive elements contact a lower surface of the ohmic contact. A portion of the one or more conductive elements may be exposed at the second dielectric surface of the one or more dielectric layers. At least one of the electrically conductive features of the external component may be electrically connected with the one or more conductive elements of the microelectronic unit. The exposed surface of the external component may be directly bonded to the second dielectric surface of the one or more dielectric layers. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIGS.  1 A-B  illustrate examples of conventional FD-SOI transistors, in which the drain of each is accessed via conductive interconnects extending through numerous dielectric layers. 
         FIG.  2    is a cross-section of a microelectronic element including an FD-SOI transistor according to one embodiment, in which the drain is accessed via a conductive interconnect connected to the backside of the drain. 
         FIGS.  2 A- 2 C  illustrate stages of forming the microelectronic element of  FIG.  2   , wherein  FIGS.  2 B- 2 C  focus on backside details of forming the microelectronic element. 
         FIG.  3    is a cross-section of a variation of the microelectronic element of  FIG.  2   , including a bulk silicon layer, in which the source is accessed via a conductive interconnect connected to the backside of the source. 
         FIGS.  3 A and  3 B  are cross-sections of in-process stages of forming the microelectronic element of  FIG.  3   . 
         FIG.  4    illustrates an example system according to aspects of the disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     As illustrated in  FIG.  2   , a microelectronic unit  200  may comprise one or more fully-depleted silicon-on-insulator transistors. The microelectronic unit  200  may include an epitaxial silicon layer  210  having a front silicon surface  212  and a back silicon surface  214  opposite the front silicon surface. The epitaxial silicon layer  210  may be a layer of silicon that is epitaxially grown. 
     In  FIG.  2   , the first and second directions parallel to the front silicon surface  212  of the epitaxial silicon layer  210  are referred to herein as “horizontal” or “lateral” directions, whereas the directions perpendicular to the front silicon surface are referred to herein as upward or downward directions and are also referred to herein as the “vertical” directions. The directions referred to herein are in the frame of reference of the structures referred to. Thus, these directions may lie at any orientation to the normal or gravitational frame of reference. A statement that one feature is disposed at a greater height “above a surface” than another feature means that the one feature is at a greater distance in the same orthogonal direction away from the surface than the other feature. Conversely, a statement that one feature is disposed at a lesser height “above a surface” than another feature means that the one feature is at a smaller distance in the same orthogonal direction away from the surface than the other feature. 
     The epitaxial silicon layer  210  may have a source  220  and a drain  222  each extending between the front and back silicon surfaces  212 ,  214 . The source  220  and the drain  222  may each be doped portions of the epitaxial silicon layer  210 . A gate terminal  224  may be above the front silicon surface  212  and over an epitaxial silicon region between the source  220  and drain  222 . Activating the gate terminal  224  by applying a voltage to the terminal may couple the source  220  and drain  222  together. The gate terminal  224  may comprise one or more electrically conductive materials, such as a conductor, highly doped silicon, a refractory metal, or a silicide. The gate terminal  224  may be separated from the epitaxial silicon layer and the source  220  and the drain  222  by a dielectric layer (not shown) made, for example, of silicon dioxide. 
     The microelectronic unit  200  may have an isolation trench  230  extending through the epitaxial silicon layer  210  between the front and back silicon surfaces  212 ,  214 . The isolation trench  230  may be configured to electrically insulate the source  220  and the drain  222  from adjacent portions of the epitaxial silicon layer  210  that may contain adjacent transistors. The isolation trench  230  may comprise one or more dielectric materials (e.g., silicon dioxide) deposited into an opening extending through the epitaxial silicon layer  210 . In some examples, the isolation trench  230  may comprise a dielectric coating extending along inner surfaces of the opening, and the remainder of the volume of the opening may be filled with a metal. In some examples, the isolation trench  230  may extend completely around the source  220  and the drain  222  in the first and second directions, for example, in a rectangular or ring shape. 
     The microelectronic unit  200  may have a buried oxide layer  240  having a top oxide surface  242  and a bottom oxide surface  244  opposite the top surface. The top oxide surface  242  may directly contact the back surface  214  of the epitaxial silicon layer  210 . The epitaxial silicon layer  210  may be epitaxially grown on the top oxide surface  242  of the buried oxide layer. The buried oxide layer  240  may comprise silicon dioxide or another dielectric material. 
     The microelectronic unit  200  may have an ohmic contact  250  extending through the buried oxide layer  240  between the top and bottom oxide surfaces  242 ,  244 . The ohmic contact  250  may be coupled to a lower surface of one of the source  220  and the drain  222 . As shown in  FIG.  2   , the ohmic contact  250  is coupled to a lower surface  226  of the drain  222 , but in other examples, the ohmic contact may be coupled to a lower surface of the source  220 . The ohmic contact  250  may comprise an electrically conductive metal, such as copper or tungsten. The ohmic contact  250  may be deposited into an opening extending through the buried oxide layer  240 . In some examples, the ohmic contact  250  may be coupled to the lower surface of the source or the drain by a layer of silicide (not shown) extending between an upper surface  252  of the ohmic contact and the lower surface of the source or the drain. 
     The microelectronic unit  200  may have one or more dielectric layers  260  deposited onto the bottom oxide surface  244 . The one or more dielectric layers  260  may include a first surface  262  and a second surface  264  opposite the first surface. In the example shown in  FIG.  2   , the one or more dielectric layers  260  comprises two dielectric layers  266  and  267 , although in other examples, the dielectric layers may comprise any number of dielectric layers, such as one, three, four, five, eight, ten, or more than ten. 
     The one or more dielectric layers may further include a conductive element  270 , such as metallization. The conductive element  270  may extend through the one or more dielectric layers  260 , such as between the first and second surfaces  262 ,  264 . An interconnection portion  272  of the conductive element  270  may be coupled to a lower surface  254  of the ohmic contact  250  opposite the upper surface  252  as shown in  FIG.  2 C . A terminal portion  274  of the conductive element  270  may be exposed at the second surface  264  of the one or more dielectric layers  260  and may be configured to be bonded to and electrically connected to an electrically conductive feature of an external component (not shown). The conductive element  270  may include one or more conductive traces  276  extending within at least one of the dielectric layers  266 , and the conductive trace may be electrically connected to the terminal portion  274 . In some examples, the terminal portion  274  of the conductive element  270  may be a conductive bond pad. 
     As used in this disclosure with reference to a structure (e.g., the one or more dielectric layers  260 ), a statement that an electrically conductive element (e.g., the conductive element  270 ) is “at” a surface or “exposed at” a surface (e.g., the second surface  264 ) indicates that, when the structure containing the surface is not assembled with any other element, the electrically conductive element is available for contact with a theoretical point moving in a direction perpendicular to the surface of the structure toward the surface of the structure from outside the structure. Thus, a terminal or other conductive element that is at a surface of a structure may project from such surface; may be flush with such surface; or may be recessed relative to such surface in a hole or depression in the structure. In some embodiments, a conductive element at a surface may be attached to the surface or may be disposed in one or more layers of dielectric coating on the said surface. 
     The microelectronic unit  200  may be bonded to and electrically connected with an external component (not shown), thereby forming a microelectronic assembly. In some examples, the terminal portion  274  of the conductive element  270  may be bonded to an electrically conductive feature of an external component using solder, conductive posts, or other electrically conductive elements. In some examples, the second surface  264  of the one or more dielectric layers  260  may be directly bonded to the external component, for example, using direct dielectric bonding, non-adhesive techniques, such as a ZiBond® direct bonding technique or a DBI® hybrid bonding technique, both available from Invensas Bonding Technologies, Inc. (formerly Ziptronix, Inc.), a subsidiary of Xperi Corp. (see for example, U.S. Pat. Nos. 6,864,585 and 7,485,968, which are incorporated herein in their entirety). Such a direct bonding of the microelectronic unit  200  and an external component may be accomplished without using solder, conductive posts, or other electrically conductive elements that may extend below the second surface  264 . In such a direct bonding example, the second surface  264  may be laminated onto a confronting exposed surface of an external component, and heat and pressure may be used to bond the second surface with the confronting exposed surface of the external component. 
     The microelectronic unit  200  may have a front dielectric layer assembly  280  over the epitaxial silicon layer  210 . The front dielectric layer assembly may include a dielectric material such as silicon dioxide, and it may be a passivation layer. The front dielectric layer assembly may be configured to electrically insulate and protect the source  220 , the drain  222 , and the gate terminal  224 . The front dielectric layer assembly may be devoid of electrically conductive elements extending therethrough to the source  220  or the drain  222 , since one of the source or the drain is already electrically connected with the terminal portion  274  of the conductive element  270  at the second surface  264  of the rear dielectric layer assembly  260 . In other possible embodiments, electrical connection to the top surface of the source  220  or the drain  222  may exist in order to share the source or drain connections with other circuit elements. For example, the source may be driven externally, and the drain may be coupled to the gate of a different transistor. 
     A method of fabricating the microelectronic unit  200  will now be discussed, with reference to  FIGS.  2 A- 2 C . A bulk silicon wafer  202  may be provided. The buried oxide layer  240  may be grown or deposited at an exposed surface  204  of the bulk silicon wafer  202 . The bottom surface  244  of the buried oxide layer  240  may be adjacent the exposed surface  204  of the bulk silicon wafer  202 . The epitaxial silicon layer  210  may be epitaxially grown at the top oxide surface  242  of the buried oxide layer  240 , with the back silicon surface  214  being formed adjacent the top oxide surface of the buried oxide layer. 
     The source  220  and the drain  222  may be formed by doping portions of the epitaxial silicon layer  210 , and the gate terminal  224  may be formed and electrically coupled to the epitaxial silicon to form a transistor with the source  220  and the drain  222 . The isolation trench  230  may be formed extending through the epitaxial silicon layer  210  between the front and back silicon surfaces  212 ,  214 . The isolation trench  230  may be formed by depositing one or more dielectric materials into an opening extending through the epitaxial silicon layer  210 . The isolation trench  230  may extend completely around the source, drain, and gate terminal in the first and second directions, for example, in a rectangular or ring shape. The isolation trench  230  may completely isolate adjacent transistor structures. In some examples, the isolation trench  230  may be formed by depositing a dielectric coating extending along inner surfaces  234  of the opening, and the remainder of the volume of the opening may be filled with a metal. 
     As shown in  FIG.  2 A , a plurality of dielectric layers  280  may be added. The unit  200  including the layers  280  may then be bonded to a second unit  290  that includes a second bulk silicon layer  292 . The second unit  290  may provide support to the unit  200  during a process of chemical and/or mechanical etching of the bulk silicon wafer  202 . The unit  200  including the dielectric layers  280  may be bonded to the second unit  290  using, for example, direct dielectric bonding, non-adhesive techniques, such as a ZiBond® direct bonding technique, or a DBI® hybrid bonding technique, both available from Invensas Bonding Technologies, Inc. (formerly Ziptronix, Inc.), a subsidiary of Xperi Corp. (see for example, U.S. Pat. Nos. 6,864,585 and 7,485,968, which are incorporated herein in their entirety). 
     In some embodiments, all or a portion of the bulk silicon wafer  202  may be removed from the bottom surface  244  of the buried oxide layer  240 , using one or more chemical and/or mechanical processes, such as etching, chemical mechanical planarization (“CMP”), etc. According to some examples, the removal may automatically stop upon reaching the buried oxide layer  240 . 
     As shown in  FIG.  2 B , the ohmic contact  250  may be formed extending through the buried oxide layer  240  between the top and bottom oxide surfaces  242 ,  244 , the ohmic contact being coupled to a lower surface of one of the source or the drain. While the second unit  290  and the dielectric layers  280  are not shown in  FIGS.  2 B- 2 C , it should be understood that they may nevertheless be present. 
     In some examples, the ohmic contact  250  may be deposited into an opening extending through the buried oxide layer  240 . The opening may be formed by pattern etching the bottom oxide surface  244  of the buried oxide layer  240 , for example, using a photoresist to protect the remaining portions of bottom surface. The ohmic contact  250  may be formed by depositing a seed layer along inner surfaces  248  of the opening, and then by depositing the remainder of the electrically conductive material onto the seed layer. In some examples, the ohmic contact  250  may be coupled to the lower surface of the source or the drain by first forming a layer of silicide (not shown) on the lower surface of the source or the drain, and then depositing the metal of the ohmic contact into the opening overlying the layer of silicide. 
     As shown in  FIG.  2 C , the one or more dielectric layers  260  may deposited onto the bottom oxide surface  244  of the buried oxide layer  240 . The conductive element  270  may be formed extending through the one or more dielectric layers  260  between the first and second dielectric surfaces  262 ,  264 , the conductive element being deposited onto the lower surface  254  of the ohmic contact  250 . A terminal portion  274  of the conductive element  270  may be exposed at the second dielectric surface  264 . 
     In the example shown in  FIG.  2 C , a first one of the dielectric layers  266  may be deposited onto the bottom surface  244  of the buried oxide layer  240 . The first dielectric layer may be patterned and etched to create openings, and electrically conductive traces  276  or other portions of the conductive element  270  may be deposited into the openings. A second one of the dielectric layers  266  may be deposited onto an exposed surface of the first dielectric layer. The second dielectric layer may be patterned and etched to create openings, and electrically conductive traces  276  and the terminal portion  274  of the conductive element  270  may be deposited into the openings. Before or after forming of the one or more dielectric layers  260 , a front dielectric layer assembly  280  may be formed at the front surface  212  of the epitaxial silicon layer  210 . 
     The microelectronic unit  200  may be bonded to and electrically connected with an external component (not shown), thereby forming a microelectronic assembly. The coupling of the microelectronic unit  200  with an external component may be performed using any of a variety of processes. For example, the microelectronic unit  200  may be bonded in a stacked arrangement with an external component using various bonding techniques, including using direct dielectric bonding, non-adhesive techniques, such as ZiBond® direct bonding technique, or DBI® hybrid bonding technique. 
     As illustrated in  FIG.  3   , a microelectronic unit  300  according to a variation of the microelectronic unit  200  may comprise one or more transistors formed in a bulk silicon wafer without a buried oxide layer. The microelectronic unit  300  may include an epitaxial silicon layer  310  having a front surface  312  and a back surface  314  opposite the front surface. The epitaxial silicon layer  310  may be a layer of silicon that is epitaxially grown. 
     The epitaxial silicon layer  310  may have a source  320  and a drain  322  each extending between the front and back surfaces  312 ,  314 . The source  320  and the drain  322  may each be doped portions of the epitaxial silicon layer  310 . A gate terminal  324  may be electrically coupled to epitaxial silicon thus forming a transistor with the source  320  and the drain  322 . The gate terminal  324  may comprise one or more electrically conductive materials, such as a conductor, highly doped silicon, a refractory metal, or a silicide. The gate terminal  324  may be separated from the source  320  and the drain  322  by a dielectric layer (not shown) made, for example, of silicon dioxide. According to other examples, the gate terminal may have contacts to a doped region that forms other devices, such as a diode, or forms a part of a routing scheme where a connection through a doped region is desired. 
     The microelectronic unit  300  may have an isolation trench  330  extending through the epitaxial silicon layer  310 , between the front and back surfaces  312 ,  314 . In some examples, where the microelectronic unit does not include an epitaxial layer, the isolation trench may extend lower than the source and drain and be at a depth that would be exposed after backgrind. The isolation trench  330  may comprise one or more dielectric materials (e.g., silicon dioxide) deposited into an opening extending through the epitaxial silicon layer  310 . In some examples, the isolation trench  330  may comprise a dielectric coating extending along inner surfaces of the opening, and the remainder of the volume of the opening may be filled with a metal. In some examples, the isolation trench  330  may extend completely around the source  320  and the drain  322  in the first and second directions, for example, in a rectangular or ring shape. 
     The microelectronic unit  300  may have a thinned bulk silicon layer  340  having a top surface  342  and a bottom surface  344  opposite the top surface. In the illustration of  FIG.  3   , the thinned bulk silicon layer  340  has been thinned, as discussed further below in connection with  FIGS.  3 A- 3 B . The top surface  342  may meet the back surface  314  of the epitaxial silicon layer  310 . For example, the epitaxial silicon layer  310  may be epitaxially grown on the top surface  342  of the bulk silicon layer. The isolation trench  330  may extend through the bulk silicon layer  340  as well as the epitaxial silicon layer  310 , so that the isolation trench extends between the front surface  312  of the epitaxial silicon layer and the bottom surface  344  of the bulk silicon layer. 
     The microelectronic unit  300  may have an ohmic contact  350  extending through the thinned bulk silicon layer  340  between the top and bottom surfaces  342 ,  344 . The ohmic contact  350  may be coupled to a lower surface of one of the source  320  and the drain  322 . As shown in  FIG.  3   , the ohmic contact  350  is coupled to a lower surface  326  of the source  320 , but in other examples, the ohmic contact may be coupled to a lower surface of the drain  322 . The ohmic contact  350  may be deposited into an opening extending through the thinned bulk silicon layer  340 . In some examples, the ohmic contact  350  may be coupled to the lower surface of the source or the drain by a layer of silicide (not shown) extending between an upper surface  352  of the ohmic contact and the lower surface of the source or the drain. 
     The microelectronic unit  300  may have a one or more dielectric layers  360  having a first dielectric surface  362  and a second dielectric surface  364  opposite the first dielectric surface. The first dielectric surface may directly contact the bottom bulk surface  344  of the thinned bulk silicon layer  340 . In the example shown in  FIG.  3   , the one or more dielectric layers  360  comprises three dielectric layers  366 , including two upper dielectric layers  366   a  and  366   b  comprising silicon dioxide, and one lower dielectric layer  366   c  comprising silicon nitride at the second surface  364 . However, it should be understood that any number of dielectric layers may be used, and the composition of each dielectric layer may vary. 
     The microelectronic unit  300  may have a conductive element  370  extending through the one or more dielectric layers  360  between the first and second dielectric surfaces  362 ,  364 . An interconnection portion  372  of the conductive element  370  may contact a lower surface  354  of the ohmic contact  350  opposite the upper surface  352 . A terminal portion  374  of the conductive element  370  may be exposed at the second dielectric surface  364  of the one or more dielectric layers  360 . The terminal portion  374  of the conductive element  370  may include a rigid conductive post  375  extending below the second surface  364  of the one or more dielectric layers  360 . The conductive post  375  may be configured to be electrically connected to an electrically conductive feature of an external component (not shown). The conductive element  370  may connect to one or more conductive traces  376  extending within at least one of the dielectric layers  366 , and the one or more conductive traces may be electrically connected to the conductive post  375 . 
     The microelectronic unit  300  may also have a conductive interconnect  380  extending from the front silicon surface  312  of the epitaxial silicon layer  310  to the second surface  364  of the one or more dielectric layers  360 . The conductive interconnect  380  may be electrically connected with the epitaxial silicon layer  310 , but not with the source  320  or the drain  322 . A contact portion  382  of the conductive interconnect  380  may be exposed at the front surface  312  of the epitaxial silicon layer  310 . A terminal portion  384  of the conductive interconnect  380  may be exposed at the second surface  364  of the rear dielectric layer assembly  360 . The terminal portion  384  of the conductive interconnect  380  may include a rigid conductive post  385  extending above the second surface  364  of the rear dielectric layer assembly  360 . The conductive post  385  may be configured to be bonded to and electrically connected to an electrically conductive feature of an external component (not shown). The conductive interconnect  380  may include one or more conductive traces  386  extending within at least one of the dielectric layers  366 , and the conductive trace may be electrically connected to the conductive post  385 . 
     The microelectronic unit  300  may be electrically connected with an external component (not shown), thereby forming a microelectronic assembly. In some examples, the conductive posts  375  and  385  may be bonded to electrically conductive features of an external component using electrically conductive masses  390 , such as masses of a bond metal, e.g., tin, indium, solder or a eutectic material, or a conductive matrix material of metal particles embedded in a polymeric material. 
     In a variation of the microelectronic unit  300 , the conductive posts  375  and  385  may be omitted, and the second dielectric surface  364  of the one or more dielectric layers  360  may directly contact the second surface of the one or more dielectric layers. Such direct contact may be achieved using, by way of example, a direct bonding of the microelectronic unit  300  and an external component. Such direct bonding may be accomplished without using solder, conductive posts, or other electrically conductive elements that may extend above the second surface  364 . In such a direct bonding example, the second surf ace  364  may be laminated onto a confronting exposed surface of an external component, and heat and pressure may be used to bond the second surface with the confronting exposed surface of the external component. 
     The microelectronic unit  300  may have a front dielectric layer assembly  395  at the front surface  312  of the epitaxial silicon layer  310 . The front dielectric layer assembly  395  may include a dielectric material such as silicon dioxide, and it may be a passivation layer. The front dielectric layer assembly  395  may be configured to electrically insulate and protect the source  320 , the drain  322 , and the gate terminal  324 . The front dielectric layer assembly may be devoid of electrically conductive elements extending therethrough to the source  320  or the drain  322 , since one of the source or the drain is already electrically connected with the terminal portion  374  of the conductive element  370  at the second surface  364  of the one or more dielectric layers  360 . 
     A method of fabricating the microelectronic unit  300  will now be discussed, with reference to  FIGS.  3 A and  3 B . A bulk silicon wafer  302  may be provided. The epitaxial silicon layer  310  may be epitaxially grown at an exposed surface  304  of the bulk silicon wafer  302 , with the back surface  314  of the epitaxial silicon layer being formed adjacent the exposed surface of the bulk silicon wafer. 
     The source  320  and the drain  322  may be formed by doping portions of the epitaxial silicon layer  310 , and the gate terminal  324  may be formed and electrically coupled to the source  320  and the drain  322 . The isolation trench  330  may be formed extending through the epitaxial silicon layer  310  between the front and back silicon surfaces  312 ,  314  and extending into the bulk silicon wafer  302  below the exposed surface  304 . The isolation trench  330  may be formed by depositing one or more dielectric materials into an opening extending through the epitaxial silicon layer  310 . In some examples, the isolation trench  330  may be formed by depositing a dielectric coating extending along inner surfaces of the opening, and the remainder of the volume of the opening may be filled with a metal. 
     The resulting in-process structure at this point is shown in  FIG.  3 A . Though not shown in  FIG.  3 A , the dielectric layers  395  may be added. Moreover, similar to  FIG.  2 A , the unit  200  may be bonded to a second unit having another bulk silicon portion to provide stability for a process of removing portions of the bulk silicon wafer  302 , as discussed below. 
     As shown in  FIG.  3 B , a portion of the bulk silicon wafer  302  may be removed from a second surface  306  of the bulk silicon wafer opposite the exposed surface  304 . For example, the bulk silicon wafer  302  may be thinned, such as by using chemical and/or mechanical processes, such as etching, CMP, etc. The remaining portion of the bulk silicon wafer  302  can be seen in  FIG.  3 B  as the thinned bulk silicon layer  340 . The ohmic contact  350  may be formed extending through the thinned bulk silicon layer  340  between the top and bottom surfaces  342 ,  344 , the ohmic contact being bonded to a lower surface of one of the source or the drain. 
     In some examples, the ohmic contact  350  may be deposited into an opening extending through the bulk silicon layer  340 . The opening may be formed by pattern etching the bottom surface  344  of the thinned bulk silicon layer  340 , using a photoresist to protect the remaining portions of bottom surface. The ohmic contact  350  may be formed by depositing an insulating layer along inner surfaces of the opening, while leaving an end portion of the opening exposed to complete an electrical connection, depositing a seed layer along inner surfaces of the insulating layer, and then by depositing the remainder of the electrically conductive material onto the seed layer. In some examples, the ohmic contact  350  may be coupled to the lower surface of the source or the drain by first forming a layer of silicide (not shown) on the lower surface of the source or the drain, and then depositing the metal of the ohmic contact into the opening overlying the layer of silicide. 
     The one or more dielectric layers  360  may be formed, for example, by depositing dielectric onto the bottom bulk silicon surface  344  of the bulk silicon layer  340 . The conductive element  370  may be formed extending through the one or more dielectric layers  360  between the first and second dielectric surfaces  362 ,  364 , the conductive element being deposited onto the lower surface  354  of the ohmic contact  350 . The conductive interconnect  380  may be formed extending from the front silicon surface  312  of the epitaxial silicon layer  310  to the second dielectric surface  364  of the one or more dielectric layers  360 . 
     In the example shown in  FIG.  3 B , a first one of the upper dielectric layers  366   a  may be deposited onto the bottom surface  344  of the thinned bulk silicon layer  340 . The first dielectric layer may be patterned and etched to create openings, and electrically conductive traces  376 ,  386  may be deposited into the openings. A second one of the upper dielectric layers  366   b  may be deposited onto an exposed surface of the first dielectric layer. The second dielectric layer may be patterned and etched to create openings, and electrically conductive traces  376 ,  386  may be deposited into the openings. Next, the lower dielectric layer  366   c  may be patterned and etched to create openings, and the conductive posts  375  and  385  may be formed extending above the second surface  364  of the one or more dielectric layers  360 . Before or after forming of the one or more dielectric layers  360 , a front dielectric layer assembly  380  may be formed at the front surface  312  of the epitaxial silicon layer  310 . 
     The microelectronic unit  300  may be electrically connected with an external component (not shown), thereby forming a microelectronic assembly. In some examples, the conductive posts  375  and  385  may be coupled to electrically conductive features of an external component using electrically conductive masses  390 , such as masses of a bond metal, e.g., tin, indium, solder or a eutectic material, or a conductive matrix material of metal particles embedded in a polymeric material. 
     The assemblies described above with reference to  FIGS.  2  and  3    above can be utilized in construction of diverse electronic systems, such as the system  400  shown in  FIG.  4   . For example, the system  400  in accordance with a further embodiment of the invention includes a plurality of modules or components  406  such as the microelectronic elements described above, in conjunction with other electronic components  408 ,  410  and  411 . 
     In the exemplary system  400  shown, the system can include a circuit panel, motherboard, or riser panel  402  such as a flexible printed circuit board, and the circuit panel can include numerous conductors  404 , of which only one is depicted in  FIG.  4   , interconnecting the modules or components  406 ,  408 ,  410  with one another. Such a circuit panel  402  can transport signals to and from each of the microelectronic packages and/or microelectronic assemblies included in the system  400 . However, this is merely exemplary; any suitable structure for making electrical connections between the modules or components  406  can be used. 
     In a particular embodiment, the system  400  can also include a processor such as the semiconductor chip  408 , such that each module or component  406  can be configured to transfer a number N of data bits in parallel in a clock cycle, and the processor can be configured to transfer a number M of data bits in parallel in a clock cycle, M being greater than or equal to N. 
     In the example depicted in  FIG.  4   , the component  408  is a semiconductor chip and component  410  is a display screen, but any other components can be used in the system  400 . Of course, although only two additional components  408  and  411  are depicted in  FIG.  4    for clarity of illustration, the system  400  can include any number of such components. 
     Modules or components  406  and components  408  and  411  can be mounted in a common housing  401 , schematically depicted in broken lines, and can be electrically interconnected with one another as necessary to form the desired circuit. The housing  401  is depicted as a portable housing of the type usable, for example, in a cellular telephone or personal digital assistant, and screen  410  can be exposed at the surface of the housing. In embodiments where a structure  406  includes a light-sensitive element such as an imaging chip, a lens  411  or other optical device also can be provided for routing light to the structure. Again, the simplified system shown in  FIG.  4    is merely exemplary; other systems, including systems commonly regarded as fixed structures, such as desktop computers, routers and the like can be made using the structures discussed above. 
     It will be appreciated that the various dependent claims and the features set forth therein can be combined in different ways than presented in the initial claims. It will also be appreciated that the features described in connection with individual embodiments may be shared with others of the described embodiments. For example, the microelectronic unit  200  ( FIG.  2   ) may have its conductive element  270  electrically connected with the source  220 , rather than the drain  222 . As another example, the microelectronic unit  200  may have rigid posts, similar to the rigid conductive posts  375  and  385  of  FIG.  3   , extending from the second dielectric surface  264  and configured to join the microelectronic unit with an external component. As a further example, the microelectronic element  200  may have a conductive interconnect extending between the front silicon surface  212  and the second dielectric surface  264 , similar to the conductive interconnect  380  ( FIG.  3   ). 
     In other examples, the microelectronic unit  300  of  FIG.  3    may have its conductive element  370  electrically connected with the drain  322 , rather than the source  320 . Further, the microelectronic unit  300  may be formed without the rigid conductive posts  375  and  385 , so that the second dielectric surface  364  can be directly bonded with an exposed surface of an external component, including using direct dielectric bonding, non-adhesive techniques, such as a ZiBond® direct bonding technique, or a DBI® hybrid bonding technique. In some examples, the microelectronic unit  300  may be formed without the conductive interconnect  380 , similar to the microelectronic unit  200 . 
     Although the invention herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the present invention. It is therefore to be understood that numerous modifications may be made to the illustrative embodiments and that other arrangements may be devised without departing from the spirit and scope of the present invention as defined by the appended claims.