Patent Publication Number: US-2023136978-A1

Title: Semiconductor structure

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application claims the priority benefit of China application serial no. 202111262076.8, filed on Oct. 28, 2021. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification. 
     BACKGROUND 
     Technical Field 
     The disclosure relates to a semiconductor structure, and in particular, to a semiconductor structure with a passivation layer. 
     Description of Related Art 
     In some semiconductor structures, a passivation layer is formed on a conductive layer. However, in the further high-temperature fabrication process, the conductive layer may expand due to the heat, and stress is generated on the passivation layer. As a result, a crack is generated at a corner of the passivation layer. Therefore, how to reduce the stress applied to the passivation layer is a field that is currently worked on. 
     SUMMARY 
     The disclosure is directed to a semiconductor structure capable of effectively reducing stress applied to a passivation layer. 
     The disclosure provides a semiconductor structure including a substrate, a dielectric layer, a first conductive layer, and a passivation layer. The dielectric layer is disposed on the substrate. The first conductive layer is disposed on the dielectric layer. The passivation layer is disposed on the first conductive layer and the dielectric layer. The passivation layer includes a first upper surface and a second upper surface. The first upper surface is located above a top surface of the first conductive layer. The second upper surface is located on one side of the first conductive layer. A height of the first upper surface is higher than a height of the second upper surface. The height of the second upper surface is lower than or equal to a height of a lower surface of the first conductive layer located between a top surface of the dielectric layer and the first conductive layer. 
     According to an embodiment of the disclosure, in the semiconductor structure, the passivation layer may include multiple insulating layers. An uppermost insulating layer of the insulating layers may be a nitride layer. The uppermost insulating layer of the insulating layers may have the first upper surface and the second upper surface. 
     According to an embodiment of the disclosure, in the semiconductor structure, one side of the first conductive layer may have an opening. The passivation layer may be located on a sidewall of the opening and a bottom surface of the opening. 
     According to an embodiment of the disclosure, in the semiconductor structure, the opening may extend into the dielectric layer. 
     According to an embodiment of the disclosure, in the semiconductor structure, an included angle between the sidewall of the opening and the bottom surface of the opening may be greater than 95 degrees and less than or equal to 120 degrees. 
     According to an embodiment of the disclosure, in the semiconductor structure, the included angle between the sidewall of the opening and the bottom surface of the opening may be greater than or equal to 95.5 degrees and less than or equal to 110 degrees. 
     According to an embodiment of the disclosure, in the semiconductor structure, the passivation layer may include a first insulating layer and a second insulating layer. The second insulating layer is disposed on the first insulating layer. The second insulating layer may have the first upper surface and the second upper surface. 
     According to an embodiment of the disclosure, in the semiconductor structure, an included angle between a sidewall of the second insulating layer and a bottom surface of the second insulating layer may be greater than 95 degrees and less than or equal to 120 degrees. 
     According to an embodiment of the disclosure, in the semiconductor structure, the included angle between the sidewall of the second insulating layer and the bottom surface of the second insulating layer may be greater than or equal to 95.5 degrees and less than or equal to 110 degrees. 
     According to an embodiment of the disclosure, in the semiconductor structure, the dielectric layer may have a rounded corner at a position that is adjacent to a bottom of the opening. 
     According to an embodiment of the disclosure, in the semiconductor structure, the passivation layer may further include a connection surface. The connection surface is located between the first upper surface and the second upper surface and is connected to the first upper surface and the second upper surface. 
     According to an embodiment of the disclosure, in the semiconductor structure, a portion of the passivation layer may be located in the dielectric layer. 
     According to an embodiment of the disclosure, in the semiconductor structure, the first conductive layer may be a single-layer structure. 
     According to an embodiment of the disclosure, in the semiconductor structure, the first conductive layer may be a multilayer structure. 
     According to an embodiment of the disclosure, in the semiconductor structure, the first conductive layer may include a barrier layer and a conductor layer. The conductor layer is disposed on the barrier layer. 
     According to an embodiment of the disclosure, in the semiconductor structure, the semiconductor structure may further include a second conductive layer. The second conductive layer is located between the dielectric layer and the substrate. 
     According to an embodiment of the disclosure, in the semiconductor structure, the first conductive layer and the second conductive layer may be separated from each other through the dielectric layer. 
     According to an embodiment of the disclosure, in the semiconductor structure, the first conductive layer may be electrically connected to the second conductive layer. 
     According to an embodiment of the disclosure, in the semiconductor structure, the passivation layer may expose a portion of the first conductive layer. 
     According to an embodiment of the disclosure, in the semiconductor structure, the semiconductor structure may further include a cap layer. The cap layer is located between the dielectric layer and the second conductive layer. 
     Based on the above, in the semiconductor structure provided in the disclosure, since the height of the second upper surface of the passivation layer is lower than or equal to the height of the lower surface of the first conductive layer located between the top surface of the dielectric layer and the first conductive layer, the stress applied to the passivation layer may be effectively reduced. Therefore, a crack generated on the passivation layer may be prevented so that an electrical performance of a semiconductor device is enhanced. 
     In order to make the aforementioned features and advantages of the disclosure comprehensible, embodiments accompanied with drawings are described in detail below. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG.  1    is a cross-sectional diagram of a semiconductor structure according to some embodiments of the disclosure. 
         FIG.  2    is a cross-sectional diagram of a semiconductor structure according to other embodiments of the disclosure. 
         FIG.  3    is a cross-sectional diagram of a semiconductor structure according to other embodiments of the disclosure. 
     
    
    
     DESCRIPTION OF THE EMBODIMENTS 
     Reference will now be made in detail to the embodiments of the disclosure, examples of which are illustrated in the accompanying drawings, but the provided examples are not used to limit the scope of the invention. In addition, the drawings are for illustrative purposes only, and are not drawn according to the original dimensions. In order to facilitate understanding, the same elements will be described with the same symbols in the following description. 
       FIG.  1    is a cross-sectional diagram of a semiconductor structure according to some embodiments of the disclosure.  FIG.  2    is a cross-sectional diagram of a semiconductor structure according to other embodiments of the disclosure.  FIG.  3    is a cross-sectional diagram of a semiconductor structure according to other embodiments of the disclosure. 
     Referring to  FIG.  1   , a semiconductor structure  10  includes a substrate  100 , a dielectric layer  102 , a conductive layer  104 , and a passivation layer  106 . The substrate  100  may be a semiconductor substrate, such as a silicon substrate. In addition, although it is not shown in  FIG.  1   , an element required for a doped region and/or an isolation structure may be included in the substrate  100 , and an element required for a semiconductor device (e.g. an active device and/or a passive device), a dielectric layer, and an interconnect structure may be included in the substrate  100 . The description thereof is omitted. 
     The dielectric layer  102  is disposed on the substrate  100 . The dielectric layer  102  may be an inter-metal dielectric (IMD) layer. A material of the dielectric layer  102  may be, for example, an oxide, such as silicon oxide. 
     The conductive layer  104  is disposed on the dielectric layer  102 . The conductive layer  104  may be a single-layer structure or a multilayer structure. In some embodiments, the conductive layer  104  may be a top metal layer in the semiconductor structure  10 . In the embodiment, the conductive layer  104  is, for example, a multilayer structure. For example, the conductive layer  104  may include a barrier layer  108  and a conductor layer  110 . A material of the barrier layer  108  is, for example, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or a combination thereof. The conductor layer  110  is disposed on the barrier layer  108 . The conductor layer  110  is, for example, a metal layer. In the embodiment, the conductor layer  110  may be the top metal layer in the semiconductor structure  10 . A material of the conductor layer  110  is, for example, aluminum. 
     In some embodiments, the semiconductor structure  10  may include multiple conductive layers  104 ; however, the disclosure is not limited thereto. The semiconductor structure  10  including one or more than one conductive layer  104  belongs to the scope of the disclosure. In the embodiment, the semiconductor structure  10  may include a conductive layer  104   a  and a conductive layer  104   b  adjacent to each other. The conductive layer  104   a  may be a conductive line, and the conductive layer  104   b  may be a pad. 
     The passivation layer  106  is disposed on the conductive layer  104  and the dielectric layer  102 . In addition, a portion of the passivation layer  106  may be located in the dielectric layer  102 . The passivation layer  106  includes an upper surface S 1  and an upper surface S 2 . The upper surface S 1  is located above a top surface TS 1  of the conductive layer  104 . The upper surface S 2  is located on one side of the conductive layer  104 . A height H 1  of the upper surface S 1  is higher than a height H 2  of the upper surface S 2 . The height H 2  of the upper surface S 2  is lower than or equal to a height H 3  of a lower surface LS of the conductive layer  104  located between a top surface TS 2  of the dielectric layer  102  and the conductive layer  104  so that stress applied to the passivation layer  106  may be effectively reduced. In addition, the passivation layer  106  may further include a connection surface S 3 . The connection surface S 3  is located between the upper surface S 1  and the upper surface S 2  and is connected to the upper surface S 1  and the upper surface S 2 . 
     Furthermore, the passivation layer  106  may include multiple insulating layers  112 ; however, the disclosure is not limited thereto. The passivation layer  106  including one or more than one insulating layer  112  belongs to the scope of the disclosure. For example, the passivation layer  106  may include an insulating layer  112   a  and an insulating layer  112   b.  The insulating layer  112   a  may be an oxide layer. A material of the insulating layer  102   a  is, for example, a silicon oxide. The insulating layer  112   b  is disposed on the insulating layer  112   a . The uppermost insulating layer  112  (e.g. the insulating layer  112   b ) of the insulating layers  112  may have the upper surface S 1  and the upper surface S 2 . The uppermost insulating layer  112  (e.g. the insulating layer  112   b ) of the insulating layers  112  may be a nitride layer. A material of the insulating layer  112  may be, for example, silicon nitride or silicon oxynitride. 
     In addition, one side of the conductive layer  104  may have an opening OP. The opening OP may be located between the two conductive layers  104  (e.g. the conductive layer  104   a  and the conductive layer  104   b ) adjacent to each other. The passivation layer  106  may be located on a sidewall of the opening OP and a bottom surface of the opening OP. The opening OP may extend into the dielectric layer  102 . In some embodiments, an included angle θ 1  between the sidewall of the opening OP and the bottom surface of the opening OP may be greater than 95 degrees and less than or equal to 120 degrees. In some embodiments, the included angle θ 1  between the sidewall of the opening OP and the bottom surface of the opening OP may be greater than or equal to 95.5 degrees and less than or equal to 110 degrees. By setting the included angle θ 1  between the sidewall of the opening OP and the bottom surface of the opening OP in the range above, the dielectric layer  102  may have a rounded corner R at a position adjacent to a bottom of the opening OP, and the stress applied to the passivation layer  106  may be further reduced. In some embodiments, an included angle θ 2  between a sidewall of the insulating layer  112   b  and a bottom surface of the insulating layer  112   b  may be greater than 95 degrees and less than or equal to 120 degrees. In some embodiments, the included angle θ 2  between the sidewall of the insulating layer  112   b  and the bottom surface of the insulating layer  112   b  may be greater than or equal to 95.5 degrees and less than or equal to 110 degrees. 
     The semiconductor structure  10  may further include a conductive layer  114 . The conductive layer  114  is located between the dielectric layer  102  and the substrate  100 . A material of the conductive layer  114  is, for example, copper. In addition, the semiconductor structure  10  may include multiple conductive layers  114 ; however, the disclosure is not limited thereto. The semiconductor structure  10  including one or more than one conductive layer  114  belongs to the scope of the disclosure. For example, the semiconductor structure  10  may include a conductive layer  114   a  and a conductive layer  114   b.  The conductive layer  104  may be overlapped with the corresponding conductive layer  114  in a direction D perpendicular to the substrate  100 . For example, the conductive layer  104   a  may be overlapped with the conductive layer  114   a  in the direction D perpendicular to the substrate  100 . The conductive layer  104   a  (e.g. the conductive line) and the conductive layer  114   a  may be separated from each other through the dielectric layer  102 . The passivation layer  106  may cover the conductive layer  104   a  (e.g. the conductive line). The conductive layer  104   b  may be overlapped with the conductive layer  114   b  in the direction D perpendicular to the substrate  100 . The conductive layer  104   b  (e.g. the pad) may be electrically connected to the conductive layer  114   b.  The passivation layer  106  may expose a portion of the conductive layer  104   b  (e.g. the pad). 
     The semiconductor structure  10  may further include a dielectric layer  116 . The dielectric layer  116  is located between the dielectric layer  102  and the substrate  100 . The conductive layer  114  may be located in the dielectric layer  116 . In addition, the dielectric layer  116  may be located between the conductive layer  114   a  and the conductive layer  114   b.  The dielectric layer  116  may be an inter-metal dielectric layer. The dielectric layer  116  may be a single-layer structure or a multilayer structure. A material of the dielectric layer  116  may be an oxide (e.g. silicon oxide), a nitride (e.g. silicon oxynitride, silicon carbon-nitride, or silicon nitride), or a combination thereof. 
     The semiconductor structure  10  may further include a cap layer  118 . In the embodiment, the cap layer  118  may be located between the dielectric layer  102  and the conductive layer  114  and between the dielectric layer  102  and the dielectric layer  116 . A material of the cap layer  118  is, for example, a nitride (e.g. silicon nitride). 
     In the embodiment, the semiconductor structure  10  includes, for example, the conductive layer  104   a  (e.g. the conductive line) and the conductive layer  104   b  (e.g. the pad) located at the two sides of the opening OP; however, the disclosure is not limited thereto. In other embodiments, as shown in  FIG.  2   , the semiconductor structure  10  may include the two conductive layers  104   a  (e.g. the conductive lines) located at the two sides of the opening OP. In other embodiments, as shown in  FIG.  3   , the semiconductor structure  10  may include the two conductive layers  104   b  (e.g. the pads) located at the two sides of the opening OP. 
     Based on the embodiments above, in the semiconductor structure  10 , since the height H 2  of the upper surface S 2  of the passivation layer  106  is lower than or equal to the height H 3  of the lower surface LS of the conductive layer  104  located between the top surface TS 2  of the dielectric layer  102  and the conductive layer  104 , the stress applied to the passivation layer  106  may be effectively reduced. Therefore, a crack generated on the passivation layer  106  may be prevented so that an electrical performance of a semiconductor device is enhanced. 
     In summary of the above, the semiconductor structure of the embodiments may effectively reduce the stress applied to the passivation layer so that the crack generated on the passivation layer may be prevented and the electrical performance of the semiconductor device is thus enhanced. 
     Although the disclosure has been described with reference to the above embodiments, they are not intended to limit the disclosure. It will be apparent to one of ordinary skill in the art that modifications to the described embodiments may be made without departing from the spirit and the scope of the disclosure. Accordingly, the scope of the disclosure will be defined by the attached claims and their equivalents and not by the above detailed descriptions.