Patent Publication Number: US-2023146017-A1

Title: Comparator circuit

Description:
TECHNICAL FIELD 
     The present invention relates to a comparator circuit. 
     BACKGROUND ART 
     One example of conventional temperature sensing devices is disclosed in Patent Document 1 identified below. In the temperature sensing device of Patent Document 1, a diode is used as a temperature sensor. This temperature sensing device senses temperature by utilizing the characteristic that when a constant current is fed to a diode, the value of the forward voltage of the diode changes with temperature. 
     CITATION LIST 
     Patent Literature 
     
         
         Patent Document 1: Japanese unexamined patent application publication No. 2012-227517 
       
    
     SUMMARY OF INVENTION 
     Technical Problem 
     Conventional temperature sensing devices that use a diode as a temperature sensor as described above include a comparator circuit that uses a forward voltage generated in the diode as a temperature sensing voltage and compares the temperature sensing voltage with a triangular wave signal. This comparator circuit outputs a pulse signal with a duty ratio commensurate with temperature. 
     Here, in the above-described comparator circuit, there is a demand for adapting to a wider range of levels of an input signal as a target of comparison with the triangular wave signal. This problem, however, is not confined to comparator circuits for use in temperature sensing devices. 
     In light of the foregoing, an object of the present invention is to provide a comparator circuit capable of adapting to a wider range of an input signal. 
     Solution to Problem 
     According to one aspect of the present invention, a comparator circuit includes a first comparator configured to receive input of an input signal and a comparison target signal to be compared with the input signal, a first output stage including an N-channel transistor having a control terminal to which a first control terminal voltage output from the first comparator is applied, and a first clamp unit configured to limit the first control terminal voltage to be not higher than a first predetermined voltage that is higher than a first threshold voltage of the N-channel transistor but is lower than a first high side voltage output as high level from the first comparator when the first control terminal voltage is not limited (a first configuration). 
     In the first configuration described above, preferably, the first predetermined voltage has a value twice the first threshold voltage (a second configuration). 
     In the first or second configuration described above, preferably, the comparison target signal is a triangular wave signal (a third configuration). 
     In any one of the first to third configurations described above, preferably, the first output stage includes a first constant current source connected to the N-channel transistor on a higher potential side than the N-channel transistor (a fourth configuration). 
     In any one of the first to fourth configurations described above, preferably, the first clamp unit includes a diode-connected NMOS transistor (a fifth configuration). 
     Preferably, any one of the first to fifth configurations described above further includes a second comparator configured to receive input of the input signal and the comparison target signal, a second output stage including a P-channel transistor having a control terminal to which a second control terminal voltage output from the second comparator is applied, a second clamp unit configured to limit the second control terminal voltage to be not lower than a second predetermined voltage that is lower than a third threshold voltage lower, by a second threshold voltage of the P-channel transistor, than a second high side voltage output as high level from the second comparator but is higher than a low level voltage output as low level from the second comparator when the second control terminal voltage is not limited, and an output unit configured to generate a third output signal on detecting whichever of rising timing/falling timing of each of a first output signal of the first output stage and a second output signal of the second output stage is earlier (a sixth configuration). 
     According to another aspect of the present invention, a comparator circuit includes a second comparator configured to receive input of an input signal and a comparison target signal to be compared with the input signal, a second output stage including a P-channel transistor having a control terminal to which a second control terminal voltage output from the second comparator is applied, and a second clamp unit configured to limit the second control terminal voltage to be not lower than a second predetermined voltage that is lower than a third threshold voltage lower, by a second threshold voltage of the P-channel transistor, than a second high side voltage output as high level from the second comparator but is higher than a low level voltage output as low level from the second comparator when the second control terminal voltage is not limited (a seventh configuration). 
     In the seventh configuration described above, preferably, the second predetermined voltage is lower than the second high side voltage by a voltage twice the second threshold voltage (an eighth configuration). 
     In the seventh or eighth configuration described above, preferably, the comparison target signal is a triangular wave signal (a ninth configuration). 
     In any one of the seventh to ninth configurations described above, preferably, the second output stage includes a second constant current source connected to the P-channel transistor on a lower potential side than the P-channel transistor (a tenth configuration). 
     In any one of the seventh to tenth configurations described above, preferably, the second clamp unit includes a diode-connected PMOS transistor (an eleventh configuration). 
     According to still another aspect of the present invention, a temperature monitor circuit includes the comparator circuit having any one of the above-described configurations, and a constant current circuit configured to feed a constant current to a diode. Here, the input signal is a signal based on a forward voltage of the diode (a twelfth configuration). 
     According to yet another aspect of the present invention, an IC package includes the temperature monitor circuit having the configuration described above, a pulse generator configured to generate a pulse based on a temperature sensing signal output from the temperature monitor circuit, an isolation transformer configured to transmit the pulse, and a logic unit configured to operate such that a temperature output signal is externally output from an external terminal based on the pulse transmitted by the isolation transformer (a thirteenth configuration). 
     Advantageous Effects of Invention 
     According to the present invention, a comparator circuit can adapt to a wider range of the input signal. 
    
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         FIG.  1    is a diagram showing a configuration of a gate driver according to an exemplary embodiment of the present invention. 
         FIG.  2    is a diagram showing an internal configuration example of a temperature monitor circuit. 
         FIG.  3 A  is a circuit diagram showing a configuration of a comparator circuit according to a first comparative example. 
         FIG.  3 B  is a circuit diagram showing a configuration of a comparator circuit according to a first embodiment. 
         FIG.  3 C  is a diagram showing a specific example of a clamp unit in  FIG.  3 B . 
         FIG.  4 A  is a timing chart showing an operation example in the comparator circuit according to the first comparative example (a case with a comparatively low input signal). 
         FIG.  4 B  is a timing chart showing an operation example in the comparator circuit according to the first comparative example (a case with a comparatively high input signal). 
         FIG.  5 A  is a timing chart showing an operation example in the comparator circuit according to the first embodiment (a case with a comparatively low input signal). 
         FIG.  5 B  is a timing chart showing an operation example in the comparator circuit according to the first embodiment (a case with a comparatively high input signal). 
         FIG.  6 A  is a circuit diagram showing a configuration of a comparator circuit according to a second comparative example. 
         FIG.  6 B  is a circuit diagram showing a configuration of a comparator circuit according to a second embodiment. 
         FIG.  6 C  is a diagram showing a specific example of a clamp unit in  FIG.  6 B . 
         FIG.  7 A  is a timing chart showing an operation example in the comparator circuit according to the second comparative example (a case with a comparatively low input signal). 
         FIG.  7 B  is a timing chart showing an operation example in the comparator circuit according to the second comparative example (a case with a comparatively high input signal). 
         FIG.  8 A  is a timing chart showing an operation example in the comparator circuit according to the second embodiment (a case with a comparatively low input signal). 
         FIG.  8 B  is a timing chart showing an operation example in the comparator circuit according to the second embodiment (a case with a comparatively high input signal). 
         FIG.  9    is a circuit diagram showing a configuration of a comparator circuit according to a third embodiment. 
     
    
    
     DESCRIPTION OF EMBODIMENTS 
     Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. 
     &lt;Configuration of Gate Driver&gt; 
       FIG.  1    is a diagram showing a configuration of a gate driver  10  according to an exemplary embodiment of the present invention. As shown in  FIG.  1   , the gate driver  10  is a device that drives the gate of an NMOS transistor M 1 . 
     The gate driver  10  includes a primary side circuit  1 , a secondary side circuit  2 , and an isolation transformer  3 . The gate driver  10  is an IC package that includes, as external terminals (lead terminals) for establishing external electric connection, a VCC 1  terminal, an INA terminal, an INB terminal, a SENS terminal, a GND 1  terminal, a VCC 2  terminal, an OUT terminal, a TO terminal, a TC terminal, and a GND 2  terminal. 
     The primary side circuit  1  includes a first Schmitt trigger  11 , a second Schmitt trigger  12 , an AND circuit  13 , a pulse generator  14 , a first under voltage lock out (UVLO) unit  15 , a PMOS transistor  16 , an NMOS transistor  17 , and a logic unit  18 . 
     The secondary side circuit  2  includes a logic unit  21 , a PMOS transistor  22 , an NMOS transistor  23 , a second UVLO unit  24 , an overvoltage protection (OVP) unit  25 , a pulse generator  26 , and a temperature monitor circuit  27 . 
     The isolation transformer  3  is disposed so as to connect the primary side circuit  1  and the secondary side circuit  2 . The isolation transformer  3 , while isolating the primary side circuit  1  and the secondary side circuit  2  from each other, transmits a signal coming from one of the primary side circuit  1  and the secondary side circuit  2  to the other. 
     The first UVLO unit  15  monitors a power supply voltage Vcc 1  applied to the VCC 1  terminal, and shuts down the primary side circuit  1  when the power supply voltage Vcc 1  falls to be lower than a predetermined voltage. 
     The first Schmitt trigger  11  transmits a first input signal In 1 , which is externally fed to the INA terminal, to a first input terminal of the AND circuit  13 . The second Schmitt trigger  12  transmits a second input signal In 2 , which is externally fed to the INB terminal, to a second input terminal of the AND circuit  13 . 
     The AND circuit  13  takes the logical product of the level of a signal fed to the first input terminal and a level obtained by inverting the level of a signal fed to the second input terminal. Accordingly, in cases where the first input signal In 1  is at low level and the second input signal In 2  is at low level, where the first input signal In 1  is at low level and the second input signal In 2  is at high level, and where the first input signal In 1  is at high level and the second input signal In 2  is at high level, the output of the AND circuit  13  is at low level, while, in a case where the first input signal In 1  is at high level and the second input signal In 2  is at low level, the output of the AND circuit  13  is at high level. 
     The pulse generator  14 , with a fall of the output of the AND circuit  13  from high level to low level as a trigger, generates a pulse with a width narrower than that of the output of the AND circuit  13 , and outputs the generated pulse to the primary side of the isolation transformer  3 . The pulse fed to the primary side of the isolation transformer  3  causes a change in current, whereby, on the secondary side of the isolation transformer  3 , a current is generated, and this current is fed to the logic unit  21 . In this case, a high-level signal is output from the logic unit  21  to be fed to the gate of the PMOS transistor  22  and to the gate of the NMOS transistor  23 . 
     Here, the PMOS transistor  22  (a switch element) and the NMOS transistor  23  (a switch element) are connected in series between a power supply voltage Vcc 2 , which is applied to the VCC 2  terminal, and a second ground GND 2 , which is applied to the GND 2  terminal, and thereby form a switching arm. Specifically, the source of the PMOS transistor  22  is connected to the application terminal for the power supply voltage Vcc 2 . The drain of the PMOS transistor  22  is connected to the drain of the NMOS transistor  23  at node N 2 . The source of the NMOS transistor  23  is connected to the application terminal for the second ground GND 2 . 
     Node N 1 , at which the gate of the PMOS transistor  22  and the gate of the NMOS transistor  23  are connected, is connected to the output terminal of the logic unit  21 . 
     Node N 2  is connected to the OUT terminal. To the OUT terminal, one end of a resistor R 1  is externally connected. The other end of the resistor R 1  is connected to the gate of the NMOS transistor M 1 . The source of the NMOS transistor M 1  is externally connected to the GND 2  terminal. Note that the second ground GND 2 , serving as a reference voltage for the secondary side circuit  2 , is different from a first ground GND 1 , which is applied to the GND 1  terminal to serve as a reference voltage for the primary side circuit  1 . 
     Here, in a case where, as described previously, a high-level signal from the logic unit  21  is applied to node N 1 , the PMOS transistor  22  is turned off, the NMOS transistor  23  is turned on, and an output voltage Out, which is a voltage of the OUT terminal, becomes the second ground GND 2  (low level). Accordingly, the NMOS transistor M 1  is turned off. 
     By contrast, the pulse generator  14 , with a rise of the output of the AND circuit  13  from low level to high level as a trigger, generates a pulse with a width narrower than that of the output of the AND circuit  13 , and outputs the generated pulse to the primary side of the isolation transformer  3 . The pulse fed to the primary side of the isolation transformer  3  causes a change in current, whereby, on the secondary side of the isolation transformer  3 , a current is generated, and this current is fed to the logic unit  21 . In this case, a low-level signal is output from the logic unit  21  to be applied to node N 1 . 
     In this case, the PMOS transistor  22  is turned on, the NMOS transistor  23  is turned off, and the output voltage Out becomes the power supply voltage Vcc 2  (high level). Accordingly, the NMOS transistor M 1  is turned on. 
     Here, the target transistor to be driven by the gate driver  10  may be constituted by an IGBT instead of the NMOS transistor M 1 . In that case, the other end of the resistor R 1  is connected to the gate of the IGBT, and the GND 2  terminal is connected to the emitter of the IGBT. 
     The second UVLO unit  24  monitors the power supply voltage Vcc 2 , which is applied to the VCC 2  terminal, and when the power supply voltage Vcc 2  falls to be lower than a predetermined voltage, the second UVLO unit  24  shuts down the secondary side circuit  2 . The OVP unit  25  is a circuit that senses an overvoltage of the power supply voltage Vcc 2 . 
     To the TO terminal, the anode of a diode D 1  is externally connected. Here, the diode D 1  may be constituted by a plurality of elements as shown in  FIG.  1   , or may instead be constituted by a single element. The cathode of the diode D 1  is externally connected to the GND 2  terminal. 
     To the TC terminal, one end of a resistor RTC is connected. The other end of the resistor RTC is externally connected to the GND 2  terminal. 
     The temperature monitor circuit  27  is a circuit that senses temperature by using the diode D 1  as a temperature sensor. The resistor RTC is an element that sets the current value of a constant current generated in the temperature monitor circuit  27 . 
     The temperature monitor circuit  27  outputs, to the pulse generator  26 , a sensed temperature as a temperature sensing signal Ts, which is a pulse signal. The pulse generator  26 , similarly to the pulse generator  14  described previously, generates a pulse with a width shorter than that of the pulse signal (the temperature sensing signal Ts) fed from the temperature monitor circuit  27 , and outputs the generated pulse to the secondary side of the isolation transformer  3 . The pulse fed to the secondary side of the insulation transformer  3  causes a change in current, whereby, on the primary side of the insulation transformer  3 , a current is generated, and this current is fed to the logic unit  18 . In this case, a high-level or low-level signal is output from the logic unit  18  to be fed to the gate of the PMOS transistor  16  and to the gate of the NMOS transistor  17 . 
     Here, the PMOS transistor  16  (a switch element) and the NMOS transistor  17  (a switch element) are connected in series between a power supply voltage Vcc 1 , which is applied to the VCC 1  terminal, and a first ground GND 1 , which is applied to the GND 1  terminal, and thereby form a switching arm. Specifically, the source of the PMOS transistor  16  is connected to the application terminal for the power supply voltage Vcc 1 . The drain of the PMOS transistor  16  is connected to the drain of the NMOS transistor  17  at node N 4 . The source of the NMOS transistor  17  is connected to the application terminal for the first ground GND 1 . 
     Node N 3 , at which the gate of the PMOS transistor  16  and the gate of the NMOS transistor  17  are connected, is connected to the output terminal of the logic unit  18 . Node N 4  is connected to the SENS terminal. 
     Based on a pulse output from the logic unit  18 , by the switching arm constituted by the PMOS transistor  16  and the NMOS transistor  17 , a temperature output signal Tsout, which is a pulse signal, is externally output from the SENS terminal. In this manner, temperature information sensed by the diode D 1  serving as a temperature sensor can be output outside the IC. Note that the first input signal In 1 , the second input signal In 2 , and the temperature output signal Tsout are communicated, for example, between an electronic control unit (ECU) (not shown) outside the IC (the gate driver  10 ) and the IC. 
     &lt;Configuration of Temperature Monitor Circuit&gt; 
       FIG.  2    is a diagram showing an internal configuration example of the temperature monitor circuit  27 . The temperature monitor circuit  27  shown in  FIG.  2    includes a constant current circuit  271 , an oscillator  272 , and a comparator circuit  273 . 
     The constant current circuit  271  includes an error amplifier  271 A, an NMOS transistor  271 B, and POS transistors  271 C and  271 D. 
     To the non-inverting input terminal (+) of the error amplifier  271 A, a reference voltage Vtc is applied. To the inverting input terminal (−) of the error amplifier  271 A, via the TC terminal, the one end of the resistor RTC is connected. The output terminal of the error amplifier  271 A is connected to the gate of the NMOS transistor  271 B. The source of the NMOS transistor  271 B is connected to the TC terminal. 
     The PMOS transistors  271 C and  271 D constitute a current mirror. Specifically, the gate and the drain of the PMOS transistor  271 C are short-circuited. The drain of the PMOS transistor  271 C is connected to the drain of the NMOS transistor  271 B. The gate of the PMOS transistor  271 C is connected to the gate of the PMOS transistor  271 D. The sources of the PMOS transistors  271 C and  271 D are connected to the VCC 2  terminal. The drain of the PMOS transistor  271 D is connected to the TO terminal. 
     With this configuration, control is performed such that the voltage of the TC terminal agrees with the reference voltage Vtc, and through the NMOS transistor  271 B passes a constant current Iin with a current value determined by the reference voltage Vtc and a resistance value Rtc of the resistor RTC. Then, by the current mirror constituted by the PMOS transistors  271 C and  271 D, the constant current Iin has its current value increased by 10 times, for example, to become a constant current Tout to be fed from the TO terminal to the diode D 1 . That is, the constant current circuit  271  generates the constant current Tout to be fed to the diode D 1 . 
     The diode D 1  has a characteristic that, under a constant current, its forward voltage decreases as temperature rises. Accordingly, the temperature can be sensed by feeding the constant current Tout to the diode D 1  serving as a temperature sensor and measuring the forward voltage generated in the diode D 1 . 
     The comparator circuit  273  compares a voltage Vto of the TO terminal generated as the forward voltage of the diode D 1  with a triangular wave signal Str generated by the oscillator  272 , and outputs, as a comparison result, the temperature sensing signal Ts, which is a pulse signal. The temperature sensing signal Ts is a pulse signal with a duty ratio corresponding to the sensed temperature. 
     &lt;First Embodiment of Comparator Circuit&gt; 
     Next, descriptions will be given of various embodiments of the comparator circuit  273  in the temperature monitor circuit  27 . 
     First, a first embodiment of the comparator circuit  273  will be described.  FIG.  3 A  is a circuit diagram showing a configuration of a comparator circuit  2731 X according to a first comparative example presented for better understanding of the characteristics of the first embodiment of the comparator circuit  273 . 
     As shown in  FIG.  3 A , the comparator circuit  2731 X according to the first comparative example includes a comparator  273 E, an NMOS transistor  273 F (an N-channel transistor), and a constant current source  273 G. The NMOS transistor  273 F and the constant current source  273 G constitute an output stage NOUT.  FIG.  3 A  also shows a line to which the second ground GND 2  is applied and a line to which a predetermined high side voltage Vh, which is a voltage higher than the second ground GND 2 , is applied. Here, the high side voltage Vh is, for example, a predetermined internal voltage Vreg, which is generated based on the power supply voltage Vcc 2 . 
     To the non-inverting input terminal (+) of the comparator  273 E, the voltage Vto (see  FIG.  2   ) of the TO terminal is fed as an input signal Sin. To the inverting input terminal (—) of the comparator  273 E, the triangular wave signal Str is fed. The comparator  273 E compares the input signal Sin with the triangular wave signal Str, and outputs a gate signal (a control terminal voltage) Gt as a comparison result to the gate (a control terminal) of the NMOS transistor  273 F. That is, the triangular wave signal Str is an example of a comparison target signal to be compared with the input signal Sin. 
     The source of the NMOS transistor  273 F is connected to an application terminal for a second ground GND 2 . The constant current source  273 G is disposed between an application terminal for the high side voltage Vh and the drain of the NMOS transistor  273 F. The NMOS transistor  273 F is turned on/off in accordance with the gate signal Gt, and thereby, at node N 13 , at which the constant current source  273 G and the drain of the NMOS transistor  273 F are connected, the temperature sensing signal Ts is generated. That is, from the output stage NOUT, the temperature sensing signal Ts is output. 
     Now, a description will be given of an operation of the thus-configured comparator circuit  2731 X according to the first comparative example, with reference to timing charts shown in  FIG.  4 A  and  FIG.  4 B . 
     In both  FIG.  4 A  and  FIG.  4 B , in the order from the top stage, waveforms of the input signal Sin, the triangular wave signal Str, the gate signal Gt, and the temperature sensing signal Ts are shown. This also applies to other timing charts to be described later. 
     In both  FIG.  4 A  and  FIG.  4 B , together with the gate signal Gt, a threshold voltage VthN of the NMOS transistor  273 F is also shown. There is a larger voltage difference between the threshold voltage VthN and the high side voltage Vh than between the threshold voltage VthN and the second ground GND 2 . 
       FIG.  4 A  is a timing chart showing an example of a case where the input signal Sin is comparatively low. In this case, at timing t 1 , at which the triangular wave signal Str rises to cross the input signal Sin from below to above the input signal Sin, the gate signal Gt starts to fall from high level (the high side voltage Vh) toward low level (the second ground GND 2 ). Then, when the gate signal Gt reaches the threshold voltage VthN at timing t 2 , the NMOS transistor  273 F is turned off, and the temperature sensing signal Ts rises to high level. Thereafter, the gate signal Gt continues to fall and reaches low level. 
     Thereafter, at timing t 3 , at which the triangular wave signal Str falls to cross the input signal Sin from above to below the input signal Sin, the gate signal Gt starts to rise toward high level. Then, when the gate signal Gt reaches the threshold voltage VthN at timing t 4 , the NMOS transistor  273 F is turned on, and the temperature sensing signal Ts falls to low level. 
     Thereafter, at timing t 5 , at which the triangular wave signal Str rises to cross the input signal Sin from below to above the input signal Sin, the gate signal Gt starts to fall toward low level. Then, when the gate signal Gt reaches the threshold voltage VthN at timing t 6 , the NMOS transistor  273 F is turned off, and the temperature sensing signal Ts rises to high level. Thereafter, the gate signal Gt continues to fall and reaches low level. 
     In this manner, in the example shown in  FIG.  4 A , by comparison between the input signal Sin and the triangular wave signal Str, the temperature sensing signal Ts is generated which is a pulse signal including high level and low level. However, since the voltage difference between the threshold voltage VthN and the high side voltage Vh is larger than the voltage difference between the threshold voltage VthN and the second ground GND 2 , delay time T 1  (timing t 1  to timing t 2 ) until the temperature sensing signal Ts rises when the triangular wave signal Str crosses the input signal Sin to above becomes longer than delay time T 2  (timing t 3  to timing t 4 ) until the temperature sensing signal Ts falls when the triangular wave signal Str crosses the input signal Sin to below, and thus there is a large delay time difference. 
       FIG.  4 B  is a timing chart showing an example of a case where the input signal Sin is comparatively high. In this case, at timing t 11 , at which the triangular wave signal Str rises to cross the input signal Sin from below to above the input signal Sin, the gate signal Gt starts to fall toward low level. 
     Thereafter, at timing t 12 , the triangular wave signal Str falls to cross the input signal Sin from above to below the input signal Sin, but the comparatively high input signal Sin causes the time period from timing t 11  to timing t 12  to be short, so that the gate signal Gt starts to rise before reaching the threshold voltage VthN. Accordingly, the NMOS transistor  273 F remains on, and thus the temperature sensing signal Ts remains at low level. Thereafter, the gate signal Gt reaches high level. 
     In this manner, the example shown in  FIG.  4 B  suffers a disadvantage that although the triangular wave signal Str has crossed the input signal Sin to above the input signal Sin, the temperature sensing signal Ts does not rise to high level. 
     Thus, a comparator circuit  2731  according to the first embodiment of the present invention has a configuration as shown in  FIG.  3 B . The comparator circuit  2731  shown in  FIG.  3 B  is different in configuration from the comparator circuit  2731   x  according to the first comparative example in that the comparator circuit  2731  includes a clamp unit  273 H. 
     The clamp unit  273 H has a function of limiting the gate signal Gt to be not higher than a first predetermined voltage V 1  that is lower than the high side voltage Vh but is higher than the threshold voltage VthN.  FIG.  3 C  shows an example of a specific configuration of the clamp unit  273 H. In  FIG.  3 C , the clamp unit  273 H is constituted by a diode-connected NMOS transistor NM. The clamp unit  273 H may be constituted otherwise, for example, by a Zener diode, etc. 
     Now, a description will be given of an operation of the thus-configured comparator circuit  2731  according to the first embodiment, with reference to the timing charts shown in  FIG.  5 A  and  FIG.  5 B . In  FIG.  5 A  and  FIG.  5 B , together with the gate signal Gt, the first predetermined voltage V 1  is also shown. Here, the first predetermined voltage V 1  has, as a preferable value, a value (2·VthN) twice the threshold voltage VthN. 
       FIG.  5 A  shows a case where the input signal Sin is comparatively low, and corresponds to  FIG.  4 A  according to the first comparative example described previously. In this case, at timing t 21 , at which the triangular wave signal Str rises to cross the input signal Sin from below to above the input signal Sin, the gate signal Gt starts to fall toward low level from the first predetermined voltage V 1  which is a limit of the gate signal Gt set by the clamp unit  273 H. Then, when the gate signal Gt reaches the threshold voltage VthN at timing t 22 , the NMOS transistor  273 F is turned off, and the temperature sensing signal Ts rises to high level. Thereafter, the gate signal Gt continues to fall and reaches low level. 
     Thereafter, at timing t 23 , at which the triangular wave signal Str falls to cross the input signal Sin from above to below the input signal Sin, the gate signal Gt starts to rise toward high level. Then, when the gate signal Gt reaches the threshold voltage VthN at timing t 24 , the NMOS transistor  273 F is turned on, and the temperature sensing signal Ts falls to low level. 
     In this manner, by having the gate signal Gt limited, by the clamp unit  273 H, to be not higher than the first predetermined voltage V 1 , it is possible to reduce the difference between the voltage difference between the first predetermined voltage V 1  and the threshold voltage VthN and the voltage difference between the threshold voltage VthN and the second ground GND 2 , and thus it is possible to reduce the delay time difference between delay time T 11  (timing t 21  to timing t 22 ) until the temperature sensing signal Ts rises when the triangular wave signal Str crosses the input signal Sin to above the input signal Sin and delay time T 12  (timing t 23  to timing t 24 ) until the temperature sensing signal Ts falls when the triangular wave signal Str crosses the input signal Sin to below the input signal Sin. In particular, in  FIG.  5 A , the first predetermined voltage V 1  is set equal to 2 VthN, this delay time difference can be reduced to approximately zero. 
       FIG.  5 B  shows a case where the input signal Sin is comparatively high, and corresponds to  FIG.  4 B  according to the first comparative example described previously. In this case, at timing t 31 , at which the triangular wave signal Str rises to cross the input signal Sin from below to above the input signal Sin, the gate signal Gt starts to fall toward low level from the first predetermined voltage V 1  which is a limit of the gate signal Gt set by the clamp unit  273 H. Then, when the gate signal Gt reaches the threshold voltage VthN at timing t 32 , the NMOS transistor  273 F is turned off, and the temperature sensing signal Ts rises to high level. Thereafter, the gate signal Gt continues to fall and reaches low level. 
     Thereafter, at timing t 33 , at which the triangular wave signal Str falls to cross the input signal Sin from above to below the input signal Sin, the gate signal Gt starts to rise toward high level. Then, when the gate signal Gt reaches the threshold voltage VthN at timing t 34 , the NMOS transistor  273 F is turned on, and the temperature sensing signal Ts falls to low level. 
     In this manner, in  FIG.  5 B , unlike in  FIG.  4 B , at timing t 31 , the gate signal Gt starts to fall from the first predetermined voltage V 1 , and thus, although the time period from timing t 31  to timing t 33  is short, the gate signal Gt can reach the threshold voltage VthN at timing t 32 . Accordingly, the temperature sensing signal Ts can rise to high level. Further, similarly to in  FIG.  5 A , it is possible to reduce the delay time difference between delay time T 11  and delay time T 12 . 
     In this manner, with the comparator circuit  2731  according to this embodiment, regardless of whether the input signal Sin is high or low, the temperature sensing signal Ts can be generated properly, and thus it is possible to adapt to a wider range of the input signal Sin. 
     &lt;Second Embodiment of Comparator Circuit&gt; 
     Next, a second embodiment of the comparator circuit will be described.  FIG.  6 A  is a circuit diagram showing a configuration of a comparator circuit  2732 X according to a second comparative example, which is provided for better understanding of the characteristics of the second embodiment of the comparator circuit  273 . 
     The comparator circuit  2732 X according to the second comparative example is different in configuration from the first comparative example ( FIG.  3 A ) in that the comparator circuit  2732 X includes a PMOS transistor  273 I (a P-channel transistor) and a constant current source  273 J that constitute an output stage POUT. Specifically, to the gate (a control terminal) of the PMOS transistor  273 I, the gate signal (the control terminal voltage) Gt, which is output from the comparator  273 E, is applied. The source of the PMOS transistor  273 I is connected to the application terminal for the high side voltage Vh. The constant current source  273 J is disposed between the drain of the PMOS transistor  273 I and the application terminal for the second ground GND 2 . At node N 14 , at which the drain of the PMOS transistor  273 I and the constant current source  273 J are connected, the temperature sensing signal Ts is generated. That is, from the output stage POUT, the temperature sensing signal Ts is output. 
     Now, a description will be given of an operation of the thus-configured comparator circuit  2732 X according to the second comparative example, with reference to timing charts shown in  FIG.  7 A  and  FIG.  7 B . 
     In  FIG.  7 A  and  FIG.  7 B , together with the gate signal Gt, a threshold voltage (Vh−VthP) is also shown which is a voltage lower than the high side voltage Vh by a threshold voltage VthP of the PMOS transistor  273 I. The voltage difference between the threshold voltage (Vh−VthP) and the high side voltage Vh is smaller than the voltage difference between the threshold voltage (Vh−VthP) and the second ground GND 2 . 
       FIG.  7 A  is a timing chart showing an example of a case where the input signal Sin is comparatively low. In this case, at timing t 41  at which the triangular wave signal Str rises to cross the input signal Sin from below to above the input signal Sin, the gate signal Gt starts to fall from high level (the high side voltage Vh) toward low level (the second ground GND 2 ). Then, when the gate signal Gt reaches the threshold voltage (Vh−VthP) at timing t 42 , the PMOS transistor  273 I is turned on and the temperature sensing signal Ts rises to high level. Thereafter, the gate signal Gt continues to fall and reaches low level. 
     Thereafter, at timing t 43  at which the triangular wave signal Str falls to cross the input signal Sin from above to below the input signal Sin, the gate signal Gt starts to rise toward high level. Thereafter, at timing t 44 , the triangular wave signal Str crosses the input signal Sin from below to above the input signal Sin. The comparatively low input signal Sin causes the time period between timing t 43  and timing t 44  to be short, so that the gate signal Gt starts to fall before reaching the threshold voltage (Vh−VthP). Accordingly, the PMOS transistor  273 I remains on, and thus the temperature sensing signal Ts remains at high level. Thereafter, the gate signal Gt reaches low level. 
     In this manner, the example shown in  FIG.  7 A  suffers a disadvantage that although the triangular wave signal Str has crossed the input signal Sin to below the input signal Sin, the temperature sensing signal Ts does not fall to low level. 
       FIG.  7 B  is a timing chart showing an example of a case where the input signal Sin is comparatively high. In this case, at timing t 51 , at which the triangular wave signal Str rises to cross the input signal Sin from below to above the input signal Sin, the gate signal Gt starts to fall from high level toward low level. Then, when the gate signal Gt reaches the threshold voltage (Vh−VthP) at timing t 52 , the PMOS transistor  273 I is turned on, and the temperature sensing signal Ts rises to high level. Thereafter, the gate signal Gt continues to fall. 
     Thereafter, at timing t 53 , at which the triangular wave signal Str falls to cross the input signal Sin from above to below the input signal Sin, the gate signal Gt starts to rise toward high level. Then, when the gate signal Gt reaches the threshold voltage (Vh−VthP) at timing t 54 , the PMOS transistor  273 I is turned off, and the temperature sensing signal Ts falls to low level. Thereafter, the gate signal Gt continues to rise and reaches high level. 
     In this manner, in the example shown in  FIG.  7 B , the voltage difference between the threshold voltage (Vh−VthP) and the high side voltage Vh is smaller than the voltage difference between the threshold voltage (Vh−VthP) and the second ground GND 2 , and thus delay time T 21  (timing t 51  to timing t 52 ) until the temperature sensing signal Ts rises when the triangular wave signal Str crosses the input signal Sin to above the input signal Sin is shorter than delay time T 22  (timing t 53  to timing t 54 ) until the temperature sensing signal Ts falls when the triangular wave signal Str crosses the input signal Sin to below the input signal Sin, and thus there is a large delay time difference. 
     Thus, a comparator circuit  2732  according to the second embodiment of the present invention has a configuration as shown in  FIG.  6 B . The comparator circuit  2732  shown in  FIG.  6 B  is different in configuration from the comparator circuit  2732 X according to the second comparative example in that the comparator circuit  2732  includes a clamp unit  273 K. 
     The clamp unit  273 K has a function of limiting the gate signal Gt to be not lower than a second predetermined voltage V 2  that is lower than the threshold voltage (Vh−VthP) but higher than the second ground GND 2  (a low level voltage).  FIG.  6 C  shows an example of a specific configuration of the clamp unit  273 K. In  FIG.  6 C , the clamp unit  273 K is constituted by the diode-connected PMOS transistor PM. The clamp unit  273 K can be constituted otherwise, and for example, it may be constituted by a Zener diode, etc. 
     Now, a description will be given of an operation of the thus-configured comparator circuit  2732  according to the second embodiment, with reference to the timing charts shown in  FIG.  8 A  and  FIG.  8 B . In  FIG.  8 A  and  FIG.  8 B , together with the gate signal Gt, the second predetermined voltage V 2  is also shown. Here, the second predetermined voltage V 2  has, as a preferable value, a voltage that is lower than the high side voltage Vh by a value twice the threshold voltage VthP (2·VthP). 
       FIG.  8 A  shows a case where the input signal Sin is comparatively low, and corresponds to  FIG.  7 A  according to the second comparative example described previously. In this case, at timing t 61 , at which the triangular wave signal Str rises to cross the input signal Sin from below to above the input signal Sin, the gate signal Gt starts to fall from high level toward low level. Then, when the gate signal Gt reaches the threshold voltage (Vh−VthP) at timing t 62 , the PMOS transistor  273 I is turned on, and the temperature sensing signal Ts rises to high level. Thereafter, the gate signal Gt continues to fall to be limited to be equal to the second predetermined voltage V 2 . 
     Thereafter, at timing t 63 , at which the triangular wave signal Str falls to cross the input signal Sin from above to below the input signal Sin, the gate signal Gt starts to rise toward high level. Then, when the gate signal Gt reaches the threshold voltage (Vh−VthP) at timing t 64 , the PMOS transistor  273 I is turned off, and the temperature sensing signal Ts falls to low level. 
     Thereafter, at timing t 65 , the triangular wave signal Str rises to cross the input signal Sin from below to above the input signal Sin, and thus the gate signal Gt starts to fall toward low level. 
     In this manner, in  FIG.  8 A , unlike in  FIG.  7 A , at timing t 63 , the gate signal Gt starts to rise from the second predetermined voltage V 2 , and thus, although the time period from timing t 63  to timing t 65  is short, the gate signal Gt can reach the threshold voltage (Vh−VthP) at timing t 64 . Accordingly, the temperature sensing signal Ts can fall to low level. 
     Further, by having the gate signal Gt limited, by the clamp unit  273 K, to be not lower than the second predetermined voltage V 2 , it is possible to reduce the difference between the voltage difference between the threshold voltage (Vh−VthP) and the high side voltage Vh and the voltage difference between the threshold voltage (Vh−VthP) and the second predetermined voltage V 2 , and thus it is possible to reduce the delay time difference between delay time T 31  (timing t 61  to timing t 62 ) until the temperature sensing signal Ts rises when the triangular wave signal Str crosses the input signal Sin to above the input signal Sin and delay time T 32  (timing t 63  to timing t 64 ) until the temperature sensing signal Ts falls when the triangular wave signal Str crosses the input signal Sin to below the input signal Sin. In particular, in  FIG.  8 A , the second predetermined voltage V 2  is set equal to V 2 −2·VthP, this delay time difference can be reduced to approximately zero. 
       FIG.  8 B  shows a case where the input signal Sin is comparatively high, and corresponds to  FIG.  7 B  according to the second comparative example described previously. In this case, at timing t 71 , at which the triangular wave signal Str rises to cross the input signal Sin from below to above the input signal Sin, the gate signal Gt starts to fall from high level toward low level. Then, when the gate signal Gt reaches the threshold voltage (Vh−VthP) at timing t 72 , the PMOS transistor  273 I is turned on, and the temperature sensing signal Ts rises to high level. Thereafter, the gate signal Gt continues to fall to be limited to be equal to the second predetermined voltage V 2 . 
     Thereafter, at timing t 73  at which the triangular wave signal Str falls to cross the input signal Sin from above to below the input signal Sin, the gate signal Gt starts to rise toward high level. Then, when the gate signal Gt reaches the threshold voltage (Vh−VthP) at timing t 74 , the PMOS transistor  273 I is turned off, and the temperature sensing signal Ts falls to low level. 
     In the case of  FIG.  8 B , similarly to the case of  FIG.  8 A , it is possible to reduce the delay time difference between delay time T 31  and delay time T 32 . 
     In this manner, the comparator circuit  2732  according to this embodiment can also generate proper temperature sensing signal Ts regardless of whether the input signal Sin is high or low, and thus can adapt to a wider range of the input signal Sin. 
     &lt;Third Embodiment of Comparator Circuit&gt; 
     Next, a third embodiment of the comparator circuit  273  will be described.  FIG.  9    is a circuit diagram showing a configuration of a comparator circuit  2733  according to the third embodiment. 
     In this embodiment, to the configuration of the first embodiment described previously, the configuration of the second embodiment is added. That is, as shown in  FIG.  9   , the comparator circuit  2733  includes, in addition to the configuration of the first embodiment, the configuration of the second embodiment (a comparator  273 E′, the PMOS transistor  273 I, the constant current source  273 J, and the clamp unit  273 K). 
     The input signal Sin and the triangular wave signal Str are both fed to the comparator  273 E′ as well as to the comparator  273 E. 
     The comparator circuit  2733  further includes an output unit  273 L. The output unit  273 L receives a first output signal Out 1  generated at node N 13  and a second output signal Out 2  generated at node  14 , and the output unit  273 L outputs the temperature sensing signal Ts (a third output signal). The output unit  273 L raises the temperature sensing signal Ts at whichever of rising timing of the first output signal Out 1  and rising timing of the second output signal Out 2  is earlier, and lowers the temperature sensing signal Ts at whichever of falling timing of the first output signal Out 1  and falling timing of the second output signal Out 2  is earlier. 
     For example, in a case where the input signal Sin is comparatively low, the comparator circuit  2733  operates as shown in  FIG.  5 A  and  FIG.  8 A  described previously, and the temperature sensing signal Ts shown in  FIG.  5 A  corresponds to the first output signal Out 1 , and the temperature sensing signal Ts shown in  FIG.  8 A  corresponds to the second output signal Out 2 . 
     Regarding the rising of the output signals, the output stage POUT constituted by the PMOS transistor  273 I and the constant current source  273 J is faster in operation speed than the output stage NOUT constituted by the NMOS transistor  273 F and the constant current source  273 G. Regarding the falling of the output signals, the output stage NOUT is faster in operation speed than the output stage POUT. 
     Accordingly, the timing (t 62  in  FIG.  8 A ) of rising of the second output signal Out 2  is a little earlier than the timing (t 22  in  FIG.  5 A ) of rising of the first output signal Out 1 , and thus at the timing of rising of the second output signal Out 2 , the temperature sensing signal Ts is raised. Further, the timing (t 24  in  FIG.  5 A ) of falling of the first output signal Out 1  is a little earlier than the timing (t 64  in  FIG.  8 A ) of falling of the second output signal Out 2 , and thus at the timing of falling of the first output signal Out 1 , the temperature sensing signal Ts is lowered. 
     OTHERS 
     It should be understood that the above embodiments are examples in all respects and are not limiting; the technological scope of the present invention is not indicated by the above description of the embodiments but by the claims; and all modifications within the scope of the claims and the meaning equivalent to the claims are covered. 
     INDUSTRIAL APPLICABILITY 
     The present invention is usable in temperature monitor circuits, for example. 
     REFERENCE SIGNS LIST 
     
         
         
           
               10  gate driver 
               1  primary side circuit 
               11  first Schmitt trigger 
               12  second Schmitt trigger 
               13  AND circuit 
               14  pulse generator 
               15  first UVLO unit 
               16  PMOS transistor 
               17  NMOS transistor 
               18  logic unit 
               2  secondary side circuit 
               21  logic unit 
               22  PMOS transistor 
               23  NMOS transistor 
               24  second UVLO unit 
               25  OVP unit 
               26  pulse generator 
               27  temperature monitor circuit 
               271  constant current circuit 
               271 A error amplifier 
               271 B NMOS transistor 
               271 C,  271 D PMOS transistor 
               272  oscillator 
               273 ,  2731 ,  2731 X,  2732 ,  2732 X,  2733  comparator circuit 
               273 E comparator 
               273 F NMOS transistor 
               273 G constant current source 
               273 H clamp unit 
               273 I PMOS transistor 
               273 J constant current source 
               273 K clamp unit 
               273 L output unit 
             NOUT, POUT output stage 
             R 1 , RTC resistor 
             M 1  NMOS transistor 
             D 1  diode