Patent Publication Number: US-8122317-B1

Title: Two-dimensional parity technique to facilitate error detection and correction in memory arrays

Description:
This application claims the benefit of U.S. provisional application Ser. No. 60/946,696 filed Jun. 27, 2007, the disclosure of which is incorporated herein by reference in its entirety. 
    
    
     GOVERNMENT FUNDING 
     This invention was made with government support under grant number F29601-02-2-299, awarded by the Air Force Research Laboratory. The United States Government may have certain rights in this invention. 
    
    
     FIELD OF THE INVENTION 
     The present invention relates to a two-dimensional parity technique to facilitate error detection and correction in memory arrays. 
     BACKGROUND OF THE INVENTION 
     Microprocessors rely on instructions and data, which are stored in various types of memory, for operation. The integrity of the instructions and data is imperative for proper operation. An error in a single bit of the instructions or data may lead to operation errors ranging from an errant function to a complete malfunction. Accordingly, efforts are often taken to ensure the integrity of the data by checking for errors before the data is used. A common error detection technique employs a parity bit for every x number of bits. For example, each byte of data may be associated with a parity bit. The value of the parity bit is calculated based on the values of each bit in the byte and is stored in association with the byte. Assuming single bytes may be written at any given time, each time the byte is written, a new parity bit value is calculated and stored in the parity bit. Each time the byte is read, the values in each bit of the byte are used to generate a new parity value, which is then compared to the parity value stored in the parity bit. If the new parity value and the parity value stored in the parity bit do not match, at least one of the values of the bits in the byte is in error. 
     Such parity schemes are relatively easy and efficient to implement, as the extra memory and processing resources required to implement parity checking is relatively low. Unfortunately, basic parity schemes only allow for the detection of errors and do not allow for the correction of errors. As such, parity schemes are generally used for data that is normally stored in multiple locations, such that when an error is detected for data in one location, an error free version of the data can be obtained from the other location. 
     When errors in data must be corrected, error detection and correction (EDAC) techniques may be employed. EDAC techniques generally employ error correction codes (ECC), such as the Hamming or Hsiao codes described in M. Hsiao, “A Class of Optimal Minimum Odd-weight-column SEC-DEC Codes”, IBM J. Res. Dev., 14, pp. 395-401, July 1970, and C. Chen et al., “Error-Correcting Codes for Semiconductor Memory Applications: A State-of-the-Art Review”, IBM J. Res. &amp; Dev., 28, 2, pp. 124-134, March 1984, which are incorporated herein by reference in their entireties. In an ECC scheme, r values for the check bits are calculated and stored in association with every bundle of z data bits during write operations. For read operations, the check bits generally allow the detection of single- or double-bit errors and the correction of single-bit errors. An exemplary read operation may flow as follows. Initially, the values of data bits are read and used to calculate new check bit values, which are logically exclusive-ORed with the corresponding values stored in the check bits to generate an r bit syndrome. If the values of the syndrome are all logic 0s, the data is valid. If any value of the syndrome is a logic 1, the data is corrupted. The nature of ECCs allows single-bit errors to be corrected and multiple-bit errors to be detected. 
     An example of data and check bit storage is provided in  FIG. 1 . An N×32 bit array  12  is illustrated where each bundle of 32 bits represents a row of data, which is associated with the required seven check bits. As illustrated, the number of check bits required for each bundle is inefficient and creates a significant penalty in the memory required to implement this EDAC scheme. A processing penalty is also imposed, as the large number of check bits for a bundle must be calculated each time a bundle is written. Partial, or narrow, writes require essentially the same amount of processing as a complete write. A partial write is one in which only a portion of the bundle is rewritten, such as when only an eight-bit byte is written within the 32-bit bundle. For a partial write, the entire 32-bit bundle is read. The eight-bit byte to be written is inserted into the bundle, and updated check bit values are calculated based on the entire bundle. The updated check bit values are then stored in the associated check bits. 
     Although conventional EDAC schemes are very effective, the processing and area penalties associated with their use limit their application. As such, usually only larger memories and second level (Layer 2) cache in high performance processor applications employ EDAC schemes. These performance penalties generally preclude the use of EDAC schemes in register files, and limit the application of EDAC schemes in first level (Layer 1) caches. As such, many processor applications are forced to rely on parity schemes, and if EDAC schemes are employed, they are only used for memories where processor overhead, access speeds, and overall size are of limited importance. 
     Bit errors in memory may be attributed to any number of causes. One of the more difficult causes to guard against is radiation. Electronic circuits, and in particular memory circuits, are vulnerable to high-energy sub-atomic particles and other types of electromagnetic radiation. Many high-altitude flight, outer space, military, nuclear, and various commercial applications require that such vulnerability be reduced to an acceptable level. Employing techniques to reduce the vulnerability of these circuits to the effects of radiation is generally referred to as radiation hardening. For the most part, radiation hardening involves employing special circuit designs, circuit layouts, the use of select materials, or any combination thereof to increase the robustness of the circuit. Long-term radiation effects that may impact the long-term functionality of the circuit are referred to as total ionizing dose (TID) effects and are often mitigated using special semiconductor material and layer organization techniques. 
     Another type of radiation effect that is becoming more of an issue is referred to as a single event effect (SEE). When a high-energy particle passes through a semiconductor providing the electronic circuit, excess charge may be left in the semiconductor along the path through which the particle passes. If excess charge is left on or near a node that is charged to a level representing a desired logic state, the excess charge may change the level of charge at the node. The change in charge level may result in the node changing from the desired logic state to another logic state. 
     For example, if a particle of ionizing radiation passes through a circuit node that is charged for a logic 1, excess electrons from the ionizing particle track may collect at the storage node and discharge the storage node to a charge level corresponding to a logic 0. The effect of the change in charge level of the storage node may result in a temporary transient, where the storage node returns to the charge level for a logic 1 and does not upset the overall output of the of the electronic circuit. This type of SEE is referred to as a single event transient (SET). If the effect of the change in charge level of the circuit node changes the logical state of the circuit by affecting a storage node, where the storage node does not return to the proper state, a single event upset (SEU) is said to occur. Generally, SETs and SEUs are temporary, unlike TID effects, which are long-term radiation effects. 
     EDAC schemes may be employed to detect and correct certain bit errors caused from radiation effects. However, such schemes are limited in the number of bit errors that can be corrected for a given word or portion of a word. Without adequate radiation hardening, a radiation event may result in more bit errors than the EDAC scheme is capable of detecting, let alone correcting. Accordingly, there is a need for an EDAC scheme that is significantly more efficient than conventional EDAC schemes. For environments subjected to radiation, there is also a need for an efficient and effective EDAC scheme that is conducive to radiation hardening. There is a further need for an EDAC scheme that can be efficiently applied in first level caches, register files, and other memories used in high performance applications, especially memories that must support finer granularity, e.g., byte width writes. 
     SUMMARY OF THE INVENTION 
     The present invention is directed to a two-dimensional parity technique for data to be stored in one or more memory arrays, each of which has various rows and columns of cells. In normal use, words of any size are written into the array. Each word is broken into to a k bit bundle. Bundles of different words are associated with each other in a super bundle. Each bundle represents a row in a super bundle and is referred to as a row bundle. Accordingly, a super bundle includes numerous rows of row bundles, and corresponding bits in each of the row bundles in the super bundle are aligned in k columns. 
     A row check bit is provided for each row bundle in each super bundle. Each row check bit provides a parity bit that is derived from the k bits of the corresponding row bundle. In one embodiment, the row check bit is derived from taking the logical exclusive-OR (XOR) of each of the bits in the corresponding row bundle. A column check bit is provided for each column in each super bundle. Each column check bit C provides a parity bit that is derived from each of the bits in the corresponding column in the super bundle. As such, each column check bit is based on a corresponding bit from the different row bundles in the super bundle. In one embodiment, the column check bit CR is derived from taking the exclusive-OR of each of the bits in the corresponding column. The various bits in the super bundles are mapped to the cells of the memory array. The row check bits and the column check bits are mapped to cells in the same or different memory array. 
     Those skilled in the art will appreciate the scope of the present invention and realize additional aspects thereof after reading the following detailed description of the preferred embodiments in association with the accompanying drawing figures. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWING FIGURES 
       The accompanying drawing figures incorporated in and forming a part of this specification illustrate several aspects of the invention, and together with the description serve to explain the principles of the invention. 
         FIG. 1  illustrates a memory array employing conventional error detection and correction techniques according to the prior art. 
         FIG. 2  is a block representation of a processing system according to one embodiment of the present invention. 
         FIGS. 3A and 3B  illustrate a memory array employing error detection and correction techniques according to one embodiment of the present invention. 
         FIG. 4  is a flow diagram illustrating a write operation according to one embodiment of the present invention. 
         FIG. 5  is a flow diagram illustrating a read operation according to one embodiment of the present invention. 
         FIG. 6  is a flow diagram illustrating a basic error correction process according to one embodiment of the present invention. 
         FIGS. 7A-7C  contain a flow diagram illustrating a detailed error correction process according to one embodiment of the present invention. 
         FIG. 8  illustrates a simple super bundle according to one embodiment of the present invention. 
         FIGS. 9A and 9B  illustrate a memory array employing error detection and correction techniques according to another embodiment of the present invention. 
         FIG. 10  is a block representation of column check bit update circuitry according to one embodiment of the present invention. 
         FIG. 11  is a timing diagram associated with the circuitry illustrated in  FIG. 10 . 
         FIGS. 12A and 12B  contain a block representation of a radiation-hardened memory array in association with column check bit update circuitry according to one embodiment of the present invention. 
         FIG. 13  is a block representation of the partitioning of data and associated row and column check bits according to one embodiment of the present invention. 
         FIG. 14  illustrates a register file cell array in association with column check bit and update circuitry according to one embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the invention and illustrate the best mode of practicing the invention. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the invention and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims. 
     Prior to delving into the details of various embodiments of the present invention, attention is drawn to  FIG. 2 , which illustrates a basic processing architecture  10  in which the concepts of the present invention may be employed. In general, a memory array  12  of any type may comprise an array of individual cells  14 , which are substantially aligned on various rows and columns. The individual cells  14  are each configured to store a binary value that is associated with a logical bit. The memory array  12  is associated with a central processing unit (CPU)  16 , which may represent a microprocessor or a system including one or more microprocessors. The CPU  16  is configured to read data from and write data to the memory array  12 . Notably, the term “data” is defined to encompass traditional data as well as operating instructions, which control operation of the CPU  16 . Memory control circuitry  18  is provided to enable the CPU  16  to access the memory array  12  as well as implement certain aspects of the present invention, as will be described below. Notably, the functionality of the memory control circuitry  18  may be provided in separate circuitry or integrated with and distributed among the CPU  16  and the memory array  12 . 
     The present invention is directed to a two-dimensional parity technique for data to be stored in one or more memory arrays  12 , each of which has various rows and columns of cells. In normal use, words that are d bits long are written into the array. Each word is broken into to a k bit bundle, wherein for example a 32-bit word (d=32) may have four eight-bit bundles (k=8). Although 32-bit words and byte-sized bundles are used for the examples herein, the words and bundles may be sized in virtually any manner. Bundles of different words are associated with each other in a super bundle. Each bundle represents a row in a super bundle and is referred to as a row bundle. Accordingly, a super bundle includes numerous rows of row bundles, and corresponding bits in each of the row bundles in the super bundle are aligned in k columns. 
     A row check bit CR is provided for each row bundle in each super bundle. Each row check bit CR provides a parity bit that is derived from the k bits of the corresponding row bundle. In one embodiment, the row check bit CR is derived from taking the logical exclusive-OR (XOR) of each of the bits in the corresponding row bundle. As such, each row check bit CR ROW,SB  for a given row, ROW, in a given super bundle, SB, can be calculated as follows:
 
 CR   ROW,SB   =b 0 ROW,SB   XOR b 1 ROW,SB   XOR b 2 ROW,SB   XOR . . . bi   ROW,SB  for  i=k− 1,
 
wherein k is the number of bits in the row bundle.
 
     A column check bit CC is provided for each column in each super bundle. Each column check bit CC provides a parity bit that is derived from each of the bits in the corresponding column in the super bundle. As such, each column check bit is based on a corresponding bit from the different row bundles in the super bundle. In one embodiment, the column check bit CR is derived from taking the exclusive-OR of each of the bits in the corresponding column. As such, the column check bits CC COL,SB  for a given column, COL, in a given super bundle SB can be calculated as follows:
 
 CC   COL,SB   =bi   0,SB   XOR bi   1,SB   XOR bi   2,SB   XOR . . . bi   ROW,SB , for ROW= N− 1
 
wherein N is the number of rows in the super bundle SB, i identifies a corresponding bit in each of the row bundles in the super bundle, and bit bi corresponds to a column, COL. The various bits in the super bundles are mapped to the cells of the memory array. The row check bits CR and the column check bits CC are mapped to cells in the same or different memory array.
 
     With reference to  FIG. 3A , an N×32 cell memory array is shown to illustrate a two-dimensional parity scheme according to one embodiment of the present invention. Assume the row check bits CR and the column check bits CC are stored in a separate memory array, but are interwoven about the different super bundles in a logical fashion to show their relationship with the corresponding row bundles and columns of the super bundles. Further assume that a 32-bit word (d=32) is written across each row of the memory array. Each 32-bit word is broken into four eight-bit row bundles (k=8). As such, each word is represented by a first row bundle for bits  0  through  7 , a second row bundle for bits  8  through  15 , a third row bundle for bits  16  through  23 , and a fourth row bundle for bits  24  through  31 . The first row bundles for each of the N words form a first super bundle; the second row bundles for each of the words form a second super bundle; the third row bundles for each of the words form a third super bundle; and the fourth row bundles for each of the words form a fourth super bundle. 
     Each row bundle in each of the super bundles is associated with a row check bit CR ROW,SB , wherein ROW identifies the row in the super bundle in which the corresponding row bundle resides and SB identifies the super bundle. Each column in each of the super bundles is associated with a column check bit CC COL,SB , wherein COL identifies the column in the super bundle and SB identifies the super bundle. Notably, column check bits CC COL,SB  may be provided for the row check bits CR ROW,SB , in each of the super bundles, SB, as illustrated. 
     Turning now to  FIG. 3B , assume that bit  10  of the overall word in row  1  is corrupted and that bit  10  resides in a row bundle on row  1  of the second super bundle. For clarity, even though bit  10  is the third bit in the row bundle, it will be referred to as bit  10  when discussing its relative position in the row bundle or actual position in the word. Further, the corresponding column in the super bundle will be referenced with respect to bit  10 . As such, the second super bundle (SB=2) that is associated with bits  8  through  15  will have column check bits CC 8,2  through CC 15,2 , and perhaps another column check bit CC COL,SB  for the row check bits CR ROW,SB  of the super bundle. 
     Since bit  10  is corrupted in this example, both the corresponding row check bit CR 1,2  and the corresponding column check bit CC 10,2  are mismatched. The integrity of the row bundle can be checked by calculating a temporary row check bit value based on the value for the bits of the row bundle, and comparing the temporary row check bit value with the actual value stored in the row check bit CR 1,2 . If there is a mismatch, the row bundle has an error; however, the comparison of the temporary row check bit value and the actual row check bit value will not identify the specific bit (bit  10 ) in the row bundle that is corrupted. The corrupted bit can be identified by analyzing the column check bits CR of the second super bundle. For instance, temporary column check bit values may be calculated for each column in the super bundle. Each temporary column check bit value is calculated based on taking the value for the bits in the corresponding column and comparing the temporary column check bit value with the actual value stored in the column check bit CC for that column. The column where the temporary check bit value does not match the actual value of the column check bit CC will identify the specific bit that is corrupted in the row bundle. 
     The following Figures,  FIGS. 4 ,  5 , and  6 , provide flow diagrams illustrating exemplary write, read, and error correction processes, respectively, according to exemplary embodiments of the present invention. With particular reference to  FIG. 4 , an exemplary write process is described. Prior to writing particular data to the memory array  12 , each cell  14  in the memory array  12  is preferably initialized to a known state. Accordingly, all data bits in corresponding row and column check bits, CR and CC, respectively, may be set to a logic 0 or a logic 1. In this initialized state, each of the row check bits CR for the various row bundles and each of the column check bits CC for the columns of the super bundles are proper for the initialized state of the data bits. 
     Notably, the present invention supports narrow writes, wherein a byte, or like smaller group of bits, in an overall word may be written without having to write the entire word. The following example assumes that each row bundle corresponds to an 8-bit byte, and illustrates the writing of data to a particular row bundle. The data bits of the row bundle are associated with an overall word, wherein each row bundle is provided in a different super bundle. For the write operation, the process begins by reading the old values to be overwritten from the data bits of the row bundle (step  100 ). The new values to be written into the data bits for the row bundle are received (step  102 ). Next, the old column check bit values for each bit of the row bundle are read from the corresponding column check bits CC (step  104 ). For each bit in the row bundle, a new column check bit value is calculated for the super bundle in which the row bundle resides (step  106 ). As noted above, the new column check bit value may be calculated based on the old values of the data bits to be overwritten, the new values for the data bits to be overwritten, and the old column check bit value. In a preferred embodiment, the new column check bit value is calculated by taking the exclusive-OR of these three values, wherein:
 
 CC   NEW   =b   OLD   XOR b   NEW   XOR CC   OLD ,
 
wherein b OLD  represents the old value of the data bit to be overwritten by b NEW  and CC OLD  represents the old column check bit value to be overwritten by new column check bit value CC NEW .
 
     Next, a new row check bit value is calculated based on the new values to be written in the data bits of the row bundle (step  108 ). The new row check bit value may be calculated, as described above, by taking the exclusive-OR of the new values to be written in the data bits of the row bundle. The new values are written in the data bits of the row bundle (step  110 ) and the new row check bit value for the row bundle is written into the corresponding row check bit CR ROW,SS  (step  112 ). Finally, the new column check bit values for each column check bit of the super bundle in which the row bundle resides are written into the corresponding column check bits CC COL,SB  (step  114 ). It should be noted that variations from this order may result in correct functionality and that many of the steps may be performed concurrently, depending upon the circuitry employed. 
     With reference to  FIG. 5 , an exemplary read process is described according to one embodiment of the present invention. For the row bundle to be read, the values from the data bits of the row bundle are initially accessed (step  200 ). A temporary row check bit value is calculated based on the values accessed from the data bits of the row bundle (step  202 ). Next, the old row check bit value for the row bundle is retrieved from the corresponding row check bit CR ROW,SB  (step  204 ) and compared with the temporary row check bit value (step  206 ). If the old and temporary row check bit values match (step  208 ), the read operation proceeds in normal fashion (step  210 ), because the values from the data bits of the row bundle are assumed to be uncorrupted. 
     If the old and temporary row check bit values do not match (step  208 ), the errors in the values of the data bits of the row bundle are identified and corrected (step  212 ). Notably, this process may allow the identification and correction of errors that occur in the value of the check bit CR ROW,SB , assuming the values of the data bits of the corresponding row bundle are accurate. Continuing with the flow, the row check bit values for the row bundles are recalculated (step  214 ) and are written to the corresponding row check bits CR ROW,SB  (step  216 ). Once the values of the data bits of the row bundle are corrected, the read operation can proceed in traditional fashion (step  210 ). 
     With reference to  FIG. 6 , a high-level error correction process is provided according to one embodiment of the present invention. After the high-level overview of the error correction process, a more detailed error correction process is provided according to one embodiment of the present invention. With particular reference to  FIG. 6 , an error correction process proceeds as follows. Initially, a row bundle with a data bit having an errant value is identified based on the row check bit value for the errant row bundle (step  300 ). The column check bit values for the super bundle having the errant row bundle are then accessed (step  302 ). The errant bit in the row bundle is identified based on the column check-bit values and the corresponding data values of the super bundle (step  304 ). In one embodiment, the column check bit values are recalculated for the super bundle and compared with the original column check bit values. A mismatch in the recalculated and original column check bit values points to the column, and thus the errant bit in the row bundle. The errant bit is corrected in the row bundle, assuming there is no more than one errant bit (step  306 ), and the row check bit value for the row bundle is recalculated (step  308 ). Finally, the row check bit value is written to the corresponding row check bit (step  310 ). 
     With reference to  FIGS. 7A-7C , a more detailed correction process is provided according to a preferred embodiment of the present invention. The process is described in association with a representative super bundle, such as that illustrated in  FIG. 8 . Initially, the row bundle with a data bit having an errant value is identified based on the row check bit value for the errant row bundle (step  400 ). In this example, the row bundle corresponds to row  1  of the super bundle illustrated in  FIG. 8 . In the row bundle, bit  1  is the errant bit, and has a value of 1. The corresponding value of the row check bit CR ROW  is a logic 0. The column check bit values for the super bundle are accessed (step  402 ) and stored in a temporary memory location (step  404 ). The column check bit values stored in a temporary memory location are referred to as temporary check bit values. 
     Next, an iterative process is provided wherein the temporary check bit values are exclusive-ORed with the data bit values of the first row bundle of the super bundle. The result is stored as the temporary check bit values in the temporary memory location. This process is repeated for each row bundle of the super bundle as follows. Initially, the data bit values for the first row bundle of the super bundle are set as the current data bit values (step  406 ), and exclusive-ORed with the temporary check bit values (step  408 ). For this first exclusive-OR operation, the temporary check bit values correspond to the column check bit values. The result of the exclusive-OR of the current data bit values and the temporary check bit values is stored as the temporary check bit values in the temporary memory location (step  410 ). If there are more row bundles of the super bundle to process (step  412 ), the next row bundle of the super bundle is selected (step  414 ). The data bit values for the next row bundle of the super bundle are set as the current data bit values (step  416 ), and the process repeats until each of the row bundles of the super bundle have been processed, and effectively exclusive-ORed with each other and the column check bit values for the super bundle. These steps are represented as follows: 
     Step 1: TEMP=CC=0000 
     Step 2: TEMP=TEMP XOR ROW 0=0000 
     Step 3: TEMP=TEMP XOR ROW 1=0100 
     Step 4: TEMP=TEMP XOR ROW 2=0100 
     Step 5: TEMP=TEMP XOR ROW 3=0100 
     Once all of the row bundles in the super bundle have been processed (step  412 ), the resultant temporary check bit values are set as syndrome values (step  418 ). 
     Step 6: SYNDROME=TEMP=0100 
     The syndrome values are then analyzed to detect the errant bit in the errant super bundle (step  420 ). In this example, the bit that is a logic 1 in the syndrome corresponds to the errant bit in the errant row bundle. At this point, the errant bit in the errant row bundle has been identified. To correct the errant bit value in the errant row bundle, the errant bit value is exclusive-ORed with the value of the corresponding bit in the syndrome (step  422 ). The result of the exclusive-OR is the corrected bit value for the errant bit in the errant row bundle. 
     The corrected bit value for the errant bit is written into its appropriate location (step  424 ). At this point, the values of the data bits in the row bundle are correct, and a new row check bit value is calculated for the row bundle (step  426 ) and written into the corresponding row check bit CR ROW,SB  (step  428 ). The recalculation of the row check bit CR ROW,SB  is provided in case the error was actually in the row check bit CR ROW,SB  itself. If desired, the row check bit values for each of the row bundles may be calculated. In the above examples, the rows and columns of a super bundle basically aligned with actual rows and columns of the memory array  12 . As such, there was a substantially direct mapping of data bits in a super bundle to corresponding cells  14  in the memory array  12 . In such a configuration, the memory array  12  is not substantially radiation hardened. In other words, when an ionizing radiation particle strikes an affected cell  14 , the adjacent cells  14  may also be affected. If the strike causes two adjacent cells in a row bundle to change states, the error correction scheme described above may not be able to correct the errors. This condition may be detected by multiple row or column check bits for a single super bundle being found to be inconsistent with the stored data during the correction procedure outlined above. Consequently, bits in a super bundle should not be stored in physically adjacent memory cells. 
     To provide significant radiation hardening, the bits in different super bundles are interleaved with one another in the actual memory array  12 . In one embodiment, adjacent bits in each row bundle of a given super bundle are mapped to cells  14  in the memory array  12  such that the adjacent bits in each row bundle are separated by a bit from another super bundle. Preferably, adjacent bits in each column of the given super bundle are also mapped to cells  14  in the memory array  12  such that the adjacent bits in each column are separated by a bit from another super bundle. 
     An exemplary mapping scheme is illustrated in  FIG. 9A . In particular, the memory array  12  has N rows and 64 columns, where one-half of the memory array  12  is not illustrated. The leftmost section, like the other sections, has N rows and 16 columns, wherein each pair of columns is designated as an SB column k, and each pair of rows is designed as an SB row. The leftmost section of the illustrated memory array supports four super bundles, wherein bits for the respective super bundles are referenced as a, b, c, and d. Each of the other sections of the array may also support four super bundles, wherein the row bundles for a word may be written in different super bundles in the different sections. As illustrated for the leftmost section, no bits for a given super bundle are adjacent to one another along a row or column. As such, a radiation strike that affects adjacent cells  14  in the memory array  12  will not affect adjacent bits in the same super bundle. 
     In particular, the first row bundle of the first super bundle (a) is mapped to cells  0 ,  2 ,  4 ,  6 ,  8 ,  10 ,  12 , and  14  of row  0  of the memory array  12 . The first row bundle of the second super bundle (b) is mapped to cells  1 ,  3 ,  5 ,  7 ,  9 ,  11 , and  15  of row  0  of the memory array  12 . The first row bundle of the third super bundle (c) is mapped to cells  0 ,  2 ,  4 ,  6 ,  8 ,  10 ,  12 , and  14  of row  1  of the memory array  12 . The first row bundle of the fourth super bundle (d) is mapped to cells  1 ,  3 ,  5 ,  7 ,  9 ,  11 , and  15  of row  1  of the memory array  12 . Moving down the section, the remaining row bundles of the first and second super bundles (a, b) are mapped to rows  2 ,  4 ,  6  . . . N−2, while the remaining row bundles of the third and fourth super bundles are mapped to rows  3 ,  5 ,  7 , . . . N−1. In this example, the corresponding row and column check bits CR, CC for the row bundles and columns of the different super bundles are logically illustrated and stored in another memory array in a similar interleaved fashion. Although each section is illustrated to provide four interleaved super bundles, any number of super bundles may be interleaved in a variety of ways, as will be appreciated by those skilled in the art. 
     As will be described below in further detail, column check bit update circuitry (CCUC)  20  may be associated with an SB column, which represents a logic column that is shared by a group of interleaved super bundles. In other words, corresponding columns in each of the interleaved super bundles are associated with a given SB column. For example, column  0  for each of the four interleaved super bundles in  FIG. 9A  will correspond to each other and are associated with SB column  0 , and so on and so forth. The CCUC  20  may be configured to update the value of the corresponding column check bit CC COL,SB  when data is written to one of the row bundles in the super bundle. The inclusion of the CCUCs  20  in  FIGS. 9A and 9B  is provide to show the relationship of the CCUCs  20  with the corresponding columns in the interleaved super bundles. 
     With reference to  FIG. 9B , a corrupted bit is illustrated. The corrupted bit is bit  0  of the first row bundle in the fourth super bundle (d). Bit  0  is in column  0  of the fourth super bundle and column  1  of the memory array  12 . The corresponding row check bit CR 1,d  and column check bit CC 1,d  are highlighted. As described above, these check bits are used to first identify the row bundle that has the error and then identify the errant bit in the errant row bundle. If a radiation strike caused this bit error, there is little likelihood of the strike causing further damage to bits in the fourth super bundle (d), because there is at least one bit from the other super bundles that separates the errant bit from other bits in the fourth super bundle (d). 
     Turning now to  FIG. 10 , an exemplary CCUC  20  is illustrated according to one embodiment of the present invention. Notably, the CCUC  20  is illustrated as being logically connected to a single static random access memory (SRAM) cell  14  of the memory array  12 . The circuitry used to selectively couple the CCUC circuitry to the various bits in the column of the super bit supported by the CCUC  20  is not shown for clarity. Those skilled in the art should recognize that various configurations are available for dynamically coupling the CCUC  20  to an appropriate SRAM cell  14 . In traditional SRAM fashion, the output of the SRAM cell  14  is a differential output, which is represented by bit line (BL) and bit line not (BLN). 
     In this embodiment, a key function of the CCUC  20  is to provide a memory location for storing the corresponding column check bit CC COL,SB  for the corresponding column. In this embodiment, the column check bit value is stored in a D-type flip-flop  22 , which is driven by a clock signal (CLK). When a write line WL[X] corresponding to the SRAM cell  14  is active, a signal representative of the logic state stored by the SRAM cell  14  is provided in differential form on lines BL and BLN. Lines BL and BLN are coupled to isolation and hold circuitry  24 , which will read lines BL and BLN and present the signal to the input of a differential sense amplifier  26 . When enabled, the output of the sense amplifier  26  (SA OUT ) represents the value stored in the SRAM cell  14 . The output of the sense amplifier  26  is presented to a first input of an exclusive-OR gate  28 . 
     When data is being written to the SRAM cell  14 , the value to be written (WRITE DATA) is presented to a first input of an exclusive-OR gate  30  at the same time as the flip-flop  22  is providing the value for the old column check bit CC OLD  to the second input of the exclusive-OR gate  30 . As such, the exclusive-OR gate  30  provides an exclusive-OR of the value of the bit to be written in the SRAM cell  14  and the value of the old column check bit CC OLD . The output of the exclusive-OR gate  30  is provided to the second input of the exclusive-OR gate  28 . As such, the value that was read from the SRAM cell  14  is exclusive-ORed with the output of the exclusive-OR gate  30 . The output of the exclusive-OR gate  28  represents the value for the new column check bit CC NEW , which is provided to the input of the flip-flop  22 . The new value for the column check bit CC NEW  is stored in the flip-flop  22  when the clock signal CLK becomes active. In essence, this portion of the CCUC  20  calculates a new value for the column check bit CC NEW  for a write operation. As described above, the new value for the column check bit CC NEW  is provided by exclusive-ORing the values for each bit in the column of the super bundle. Thus, at any given time, the current value of the column check bit CC OLD  represents the result of exclusive-ORing each of the bits in the column of the super bundle. As such, when a single bit in a column changes, such as when data is written to a row bundle, the exclusive-OR of each of the bits in the column does not need to be recalculated. It is sufficient to take the exclusive-OR of the old value of the column check bit, the value of the bit to be overwritten, and the value of the bit to be written to determine the new column check bit value. 
     With continued reference to  FIG. 10 , as the new column check bit value is being calculated, the CCUC  20  facilitates the writing of the write data to the SRAM cell  14 . As indicated, the old value that was stored in the SRAM cell  14  is read and used to calculate the new column check bit value. While the new column check bit value is being calculated, the hold circuitry  24  will isolate the lines BL and BLN from the sense amplifier  26 , while continuing to present the value that was read from the SRAM cell  14  to the differential inputs of the sense amplifier  26 . Accordingly, lines BL and BLN are available to be presented a differential version of the write data. 
     A sense amplifier enable signal (SAE), which is used to activate the sense amplifier  26 , is delayed through a delay circuit  32 , which instructs the isolation and hold circuitry  24  to isolate lines BL and BLN from the sense amplifier  26  as well as enable inverters  34  and  36 . Together with inverter  38 , inverters  34  and  36  present a differential signal representing the write data to the respective lines BL and BLN to effectively write data to the SRAM cell  14 . 
     A timing diagram illustrating operation of the CCUC  20  is provided in  FIG. 11 . In essence, when the write line WL[X] is active, the value stored in the SRAM cell  14  is presented on lines BL and BLN. The sense amplifier enable signal SAE becomes active and activates the sense amplifier  26 , which is receiving the value being read from the SRAM cell  14 . The output of the sense amplifier  26  SA OUT  is provided to the first input of the exclusive-OR gate  28  to enable calculation of the new column check bit value CC NEW . 
     After the delay provided by the delay circuitry  32 , a write enable signal (WE) provided by the output of the delay circuitry  32  triggers the isolation and hold circuitry  24  to isolate the lines BL and BLN as well as enable the inverters  34  and  36 . At this point, the differential version of the write data is presented on lines BL and BLN, which will effectively set the SRAM cell  14  to the corresponding value of the write data. On the next clock cycle, the new column check bit value is clocked into the flip-flop  22  and will become the old column check bit value for the next write cycle. 
     With reference to  FIGS. 12A and 12B , another embodiment of the present invention is illustrated. In particular, a radiation-hardened memory array  12  is depicted, wherein four super bundles are interleaved in much the same fashion as that illustrated in  FIGS. 9A and 9B . Accordingly, first, second, third, and fourth super bundles (a, b, c, and d) have corresponding bits that are interleaved such that adjacent bits in any given super bundle are separated from each other by at least one bit from another super bundle. As described above, the corresponding columns of the different super bundles may be associated with a single CCUC  20 . Accordingly, the CCUC  20  that is illustrated in  FIG. 10  has been modified to provide four memory locations. Each memory location is for storing a column check bit value for each of the corresponding columns of the different super bundles. As illustrated, the CCUC  20  is associated with SB column  0 . Accordingly, a first flip-flop  22  is used to store a column check bit value for column  0  of the first super bundle (a); a second flip-flop  22  is used to store a column check bit value for column  0  of the second super bundle (b); a third flip-flop  22  is used to store a column check bit value for column  0  of the third super bundle (c); and a fourth flip-flop  22  is used to store a column check bit value for column  0  of the fourth super bundle (d). A similar CCUC  20  is provided for each SB column in the memory array. 
     Multiplexer circuitry (MUX)  40  and de-multiplexer circuitry (DEMUX)  42  or the like may be used to select the appropriate flip-flop  22 , based on the super bundle being processed. As illustrated, a super bundle select signal (SB BEL ) or the like may be used to control the multiplexer and de-multiplexer circuitries  40 ,  42 . Further, column routing circuitry  18 A may be used to route the appropriate columns of the memory array  12  to the appropriate CCUCs  20  based on a column select signal COL SEL  or the like. Assuming the memory array  12  is an SRAM array, row selection circuitry  18 B may be responsive to a row selection signal ROW SEL  or the like to effectively map write lines to the appropriate rows in the memory array  12  for memory reads and writes. The row selection circuitry  18 B and the column routing circuitry  18 A may be part of the memory control circuitry  18 , the memory array  12 , the CPU  16 , or other circuitry associated therewith. A notable feature of this embodiment is the ability for a single CCUC  20  to store and support the updating of multiple column check bits CC COL,SB  for different super bundles. For SRAM embodiments, a single sense amplifier  26  may be used in each CCUC  20 . 
     With reference to  FIG. 13 , different memory arrays  12 A and  12 B are illustrated. To facilitate radiation hardening, as well as being able to read or write data with its associated row and column check bits CR ROW,SB  and CC COL,SB , the row and column check bits CR ROW,SB  and CC COL,SB  may be stored in a different memory array  12  than the associated data. As illustrated, data  0  is stored in memory array  12 A, while the associated row and column check bits CR DATA0  and CC DATA0  are stored in memory array  12 B. Similarly, data  1  is stored in memory array  12 B, while the associated row and column check bits CR DATA1  and CC DATA1  are stored in memory array  12 A. By separating the data and corresponding row and column check bits CR ROW,SB  and CC COL,SB , the data values and the check bit values may be read or written at substantially the same time. Without separating the data bits from the row and column check bits CR ROW,SB  and CC COL,SB , it may not be possible to read or write the respective information, or it may not be possible read or write the information at the same time. 
     Although the above examples have been focused on SRAM configurations for the memory array  12 , the memory array  12  may take any form and may be created using any type of memory technology. An exemplary alternative is a register file array  12 ′ comprised of register file (RF) cells  14 ′, such as that illustrated in  FIG. 14 . In essence, a typical register file configuration is provided and associated with a modified CCUC  20 ′. In this example, each register file cell  14 ′ includes one write port and three read ports, which are associated with a pair of cross-coupled inverters  46 ,  48 . The write port is provided by PMOS transistors  50 ,  52 , and  54 . The two conventional read ports are provided by PMOS transistors  56  and  58 , each of which drives a separate data port, port  0  and port  1 , through read buffers  60  and  62 , respectively. Unique to the present invention is the addition of the third read port, which is provided by PMOS transistor  64 , which along with PMOS transistors  56 ,  58  is coupled to the cross-coupled inverters  46 ,  48  via transistor  65 . Notably, the third read port provides a direct input to a corresponding CCUC  20 ′ through a read buffer  66 . The output of the read buffer  66  represents the third read port (port  2 ). The output of the read buffer  66  may be provided substantially directly to the first input of the exclusive-OR gate  28 , instead of being run through the isolation and hold circuitry  24  and the sense amplifier  26 . Further, the write data signal may be provided to a write buffer  68 , which drives the write port provided by PMOS transistors  50 ,  52 , and  54 . 
     The exemplary register file  12 ′ allows access to a row of cells, e.g., to row N by asserting the read word line (RWLNx[N]) low, where x indicates the read port. The register file cell is written by asserting the write word line (WWLN[N]) low to place the value on the WBL[y] onto the associated cell via transistors  50 ,  52 , and  54 . For example, to read the present value of the bit stored in the bottom row of the register file, RWLN2[0] is driven low by the RWL decoder (not shown) to place the bit value onto the predischarged RBL2[x] read bit lines, which is in turn buffered to read port  2 . These read bit lines are either left in their predischarged state or charged via PMOS transistors  64  and  65  depending on the stored bit value. To read the present value, the RWLN2[x] for the desired row x is asserted, the bit value to be replaced is read out on RBL2[n] and the values appear on port  2 . Read ports  0  and  1  allow concurrent reads of the same or other rows as needed by the processor, independent of the super-bundle check bit update circuitry. The RWLN2[x] of the row x to be written should be de-asserted before the WWLN[x] is asserted to avoid a race-through condition, as should be evident to those skilled in the art. It should be noted that the access transistors may be NMOS, using precharged read bit lines or other access schemes such as CMOS pass gate logic may also be employed, as well as other single-ended or differential write circuits. 
     With the addition of the extra port, the value stored in the register file cell  14 ′ may be provided at all three ports, port  0 , port  1 , and port  2 , simultaneously. Accordingly, the value stored in a register file may be provided to other circuitry at the same time it is provided to the corresponding CCUC  20 ′. As the other circuitry is processing, the CCUC  20 ′ may facilitate a write to the register file cell  14 ′ and calculate a new column check bit value CC NEW  as described above. Radiation hardening may be provided as described above, wherein corresponding bits of interleaved super bundles are mapped to the register file cells  14 ′ such that adjacent bits in the super bundle are isolated from one another by bits from other super bundles. Further, the CCUC  20 ′ of  FIG. 14  may provide multiple memory locations for storing corresponding column check bit values for the different interleaved super bundles. 
     Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present invention. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.