Patent Publication Number: US-8121015-B2

Title: Optical disk drive device and method

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 2008-327273, filed on Dec. 24, 2008, the entire contents of which are incorporated herein by reference. 
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to an optical disc drive device and a method that reads out an RF (Radio Frequency) signal from an optical disk using an RF amplifier. 
     2. Related Art 
     Generally, a pickup or the like of an optical disk drive device has mechanical fluctuation. A recent optical disc drive device has a function to adjust a radial tilt (the shift of the point on an optical disk to which a laser beam is irradiated in the radial direction) when performing record and/or playback (reproduction) of the optical disk. However, a tangential tilt (the angle shift in the rotational direction of a position on the optical disk on which a laser beam is irradiated) is not adjusted physically and mechanically. 
     The tangential tilt may be a cause to distort playback data. Therefore, in order to avoid the influence of the tangential tilt, the waveform distortion of an RF signal must be corrected. If not corrected, it is necessary to design a pickup so as not to have the tangential tilt. Therefore, there is a problem that the margin of the pickup and/or pickup mechanism is small and the process yield gets worse. 
     JP-A No. 2006-351063 (Kokai) discloses a technique to detect the tangential tilt of the optical disk drive device. However, a technique to adjust the detected tangential tilt has never been described at all in the above publication. 
     In recent year, there has been increasing number of proposals of systems to secondarily adjust the tangential tilt by electric signal process. For example, one way is to introduce a PRML (Partial Response Maximum Likelihood) technique, which is generally used for HDD (Hard Disk Drive), to the optical disk drive device. However, for the PRML technique, large scale operation processing circuits such as a high speed A/D (Analog to Digital) converting circuit and a Viterbi decoding circuit are used. Therefore, a chip cost increases and consumption power also increases because the chip must operate with a high speed clock corresponding to a channel rate of input signals. 
     SUMMARY 
     According to one aspect of the present invention, an optical disk drive device comprising: an RF equalizer configured to generate an equalized RF signal by controlling a frequency characteristic of a delay time of an RF signal read out from an optical disk based on a control input signal; a playback clock extractor configured to extract a playback clock for reproducing data recorded on the optical disk from the equalized RF signal; and an RF rate controller configured to generate the control input signal inputted to the RF equalizer, wherein the control input signal is a signal for correcting waveform distortion of the RF signal by controlling the delay time of the RF signal dependent on a frequency of the playback clock. 
     According to the other aspect of the present invention, an optical disk drive method comprising: generating an equalized RF signal by controlling a frequency characteristic of a delay time of an RF signal read out from an optical disk based on a control input signal; extracting a playback clock for reproducing data recorded on the optical disk from the equalized RF signal; and generating the control input signal, wherein the control input signal is a signal for reducing waveform distortion included in the RF signal by controlling the delay time of the RF signal dependent on a frequency of the playback clock. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a block diagram showing a schematic configuration of an optical disk drive device according to a first embodiment of the present invention. 
         FIG. 2  is a block diagram showing an example of an internal configuration of an RF equalizer  15   a , a multi slicing circuit  30   a , a waveform distortion measuring circuit  30   b , and an RF rate measuring and controlling circuit  28   b.    
         FIG. 3  is a circuit diagram showing an example of an internal configuration of a filter  151 - 1  in the RF equalizer  15   a.    
         FIG. 4  is a graph showing an example of a frequency characteristic of a delay time τ of the filter  151 - 1  in the case of gm 1 *gm 2 =α (α=1/1.2, 1.0, and 1.2). 
         FIG. 5  is a graph showing a transfer function of the RF equalizer  15   a  of  FIG. 2  having the filters  151 - 1  to  151 - 3  with the internal configuration of  FIG. 3 . 
         FIG. 6  is a graph showing an example of a frequency characteristic of the delay time τ of the RF equalizer  15   a  of  FIG. 5 . 
         FIG. 7A  and  FIG. 7B  are examples of operation waveforms of the multi slicing circuit  30   a  and the waveform distortion measuring circuit  30   b.    
         FIG. 8  is a block diagram showing an example of an internal configuration of the RF rate measuring and controlling circuit  28   b.    
         FIG. 9  is an example showing an operation of the RF rate measuring and controlling circuit  28   b.    
         FIG. 10  is a characteristic showing an example of signals Vf 1  to Vf 3  versus a frequency of a playback clock. 
         FIG. 11  is a block diagram showing a schematic configuration of an optical disk drive device according to a second embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Hereinafter, the present embodiments will be explained with reference to accompanying drawings. 
     First Embodiment 
       FIG. 1  is a block diagram showing a schematic configuration of an optical disk drive device according to a first embodiment of the present invention. The optical disk drive device of  FIG. 1  has a pickup  12 , an RF amplifier  15  having an RF equalizer  15   a  (RF EQ), an A/D-converting circuit  16   a  for TE (Tracking Error), a tracking servo controlling circuit  16 , a lens driving signal generating circuit  22   a  for tracking, an adder  39   a , a D/A (Digital to Analog) converting circuit  20   a  for tracking servo, a tracking actuator driver  20 , a feed motor controlling circuit  17 , a D/A-converting circuit for feed motor  18   a , a feed motor driver  18 , a feed motor  14 , an A/D-converting circuit  19   a  for FE (Focus Error), a focus servo controlling circuit  19 , a lens driving signal generating circuit  22  for focus, an adder  39   b , a D/A-converting circuit  21   a  for focus servo, and a focus actuator driver  21 . 
     The pickup  12  irradiates an optical disk  11  with a beam and detects a beam signal reflected on the optical disk  11  to provide its reflected beam signal to the RF amplifier  15 . The RF amplifier  15  generates a tracking servo error signal for controlling the direction of the track, a focus servo signal for controlling the beam to focus on the recording surface of the optical disk  11 , an RF signal functioning as an information signal and a Wobble signal, based on the reflected beam signal. 
     The A/D-converting circuit  16   a  for TE converts the tracking error signal to a digital signal to provide its digital signal to the tracking servo controlling circuit  16 . The lens driving signal generating circuit  22   a  for tracking generates a lens driving signal for jumping in direction of the track on address seeking. This lens driving signal is added by the adder  39   a  to tracking servo data generated by the tracking servo controlling circuit  16  and is converted to an analog signal by the D/A-converting circuit  20   a  for tracking. The tracking actuator driver  20  drives a tracking actuator (not shown) of the pickup  12  based on the analog signal. 
     The feed motor controlling circuit  17  amplifies a low frequency component of the tracking servo data necessary to move the pickup  12  in the radial direction of the optical disk  11 . The amplified data is converted to an analog signal by the D/A-converting circuit  18   a  for feed motor. The feed motor driver  18  drives the feed motor  14  based on the analog signal. 
     The D/A-converting circuit  19   a  for FE converts the focus error signal to a digital signal to provide its digital signal to the focus servo controlling circuit  19 . The lens driving signal generating circuit  22  for focus generates a lens driving signal which is necessary to activate the focus servo. The lens driving signal is added by the adder  39   b  to focus servo data generated by the focus servo controlling circuit  19  and is converted to an analog signal by the D/A-converting circuit  21   a  for focus. The focus actuator driver  21  drives a focus actuator (not shown) of the pickup  12  based on the analog signal. 
     Furthermore, the optical disk driving device according to the present embodiment also has a Wobble PLL (Phase Locked Loop) decoder  26 , a disk motor controlling circuit  40 , a disk motor driver  41 , a disk motor  13 , a recording clock PLL  27 , a modulating circuit  32 , a laser power modulating circuit  29 , a multi slicing circuit  30   a , a waveform distortion measuring circuit  30   b , an RF rate measuring and controlling circuit  28   b  (RF rate controller), a playback clock PLL  28  (playback clock extractor), a demodulating circuit  31 , a data correcting and parity generating circuit  33  (error corrector), a correcting RAM  34 , a buffer controller  35 , a data buffer RAM  36 , an ATAPI (Advanced Technology Attachment Packet Interface) interface  37 , and a system controller  38  (coefficient controller). 
     Hereinafter, the reproducing operation will be explained. The playback clock PLL  28  extracts a bit clock (playback clock) from the RF signal. The disk motor controlling circuit  40  generates a control signal for controlling the disk motor  13  in synchronization with the playback clock. The disk motor driver  41  rotate the disk motor  13  based on the control signal. The multi slicing circuit  30   a  binarizes the RF signal. Furthermore, the multi slicing circuit  30   a , the waveform distortion measuring circuit  30   b  and the RF rate measuring and controlling circuit  28   b  control the RF equalizer  15   a  to correct a waveform distortion of the RF signal, as is described below. The playback clock and the binarized RF signal are provided to the demodulating circuit  31 . The demodulating circuit  31  generates demodulated data by separating a sync signal and conducting demodulation to provide its demodulated data to the data correcting and parity generating circuit  33 . The data correcting and parity generating circuit  33  performs correcting process of the demodulated data using the correcting RAM  34  and provides the buffer controller  35  with the corrected data. The buffer controller  35  buffers the corrected data on the data buffer RAM  36  temporarily and transfers the data according to request from a host PC (not shown) to the host PC through the ATAPI interface  37 . The system controller  38  acquires an error flag which the data correcting and parity generating circuit  33  generates when performing the correcting process and determines the quality of the data read out from the optical disk  11 . 
     Hereinafter, the recording operation will be explained. The Wobble PLL decoder  26  generates a Wobble clock based on the Wobble signal. The disk motor controlling circuit  40  generates a control signal for controlling the disk motor  13  based on the Wobble clock. The disk motor driver  41  rotates the disk motor  13  based on the control signal. Furthermore, the Wobble PLL decoder  26  obtains address information indicative of the recording position from the Wobble signal. The system controller  38  determines the recording position based on the address information. The recording data sent from the host PC is stored in the data buffer RAM  36  from the buffer controller  35  through the ATAPI interface  37 . The data correcting and parity generating circuit  33  adds parity data to the recording data. The modulating circuit  32  converts the recording data with the parity data to a stream signal using a modulating clock obtained by generating a multiple of the frequency of the Wobble clock by the recording clock PLL  27 . The laser power modulating circuit  29  modulates the stream signal to a pulse signal and controls the pickup  12  to record the data. 
     Hereinafter, the correction of the waveform distortion of the RF signal, which is one of the characteristic features of the present embodiments, will be explained. In general, the RF signal contains signal components including not a single frequency but a plurality of channel frequencies. For example, the RF signal of CD (Compact Disk) contains signal components composed of a plurality of channel frequencies of 3T to 11T as fundamental frequencies, while the RF signal of DVD (Digital Versatile Disk) contains that of 3T to 14T, where T is a cycle of 1 channel bit. It is known that delay time of the RF signal varies dependent on the frequency on the transfer path if the tangential tilt occurs. In the present embodiments, the RF equalizer  15   a  is controlled so as to have a transfer characteristic opposite to that of the transfer path. Because of this, the RF equalizer  15   a  corrects the distorted waveform of the RF signal, thereby improving the quality of the RF signal. 
       FIG. 2  is a block diagram showing an example of an internal configuration of the RF equalizer  15   a , the multi slicing circuit  30   a , the waveform distortion measuring circuit  30   b , and the RF rate measuring and controlling circuit  28   b . At least a part of these may be integrated in a semiconductor chip. The chip may have other circuits such as the demodulating circuit  31 . 
     The RF equalizer  15   a  has a plurality of filters  151 - 1 ,  151 - 2 ,  151 - 3  connected in series. The multi slicing circuit  30   a  has first to third comparators  301  to  303 . Each of the comparators binarizes the RF signal with different slicing level. The waveform distortion measuring circuit  30   b  detects the waveform distortion of the RF signal based on the slicing result of the multi slicing circuit  30   a . The RF rate measuring and controlling circuit  28   b  measures a frequency of the playback clock generated by the playback clock PLL  28  and controls a frequency characteristic of gain and phase (delay time) of the filters  151 - 1  to  151 - 3  in the RF equalizer  15   a  based on the frequency of the playback clock and the waveform distortion of the RF signal. As described above, the RF equalizer  15   a  corrects the waveform distortion of the RF signal dependent on the frequency of the playback clock. 
     The internal configuration and operation of the RF equalizer  15   a  of  FIG. 2  will be explained firstly. The RF equalizer  15   a  of  FIG. 2  is a sixth-order filter having second-order filters  151 - 1  to  151 - 3  connected in serial. Two kinds of time constants (ω and Q, as will be described below) of the filters  151 - 1  to  151 - 3  can be controlled by control input signals Vf 1  and Vf 3 . In  FIG. 2 , the transfer functions of the filters  151 - 1  to  151 - 3  are H (ω 1 , Q 1 ), H (ω 2 , Q 2 ) and H (ω 3 , Q 3 ), respectively. 
     One of the purpose of the RF equalize  15   a  is to delay the RF signal dependent on the frequency on the transfer characteristic opposite to that of the transmission path of the RF signal to correct the waveform distortion of the RF signal, which is described above. Other purpose is to amplify the amplitude of the high frequency component of the RF signal. This is because higher frequency components have smaller amplitudes. In the case of CAV (Constant Angular Velocity) rotation, as the pickup  12  moves outside of the optical disk  11 , the frequency of the playback clock gets higher. Therefore, the frequency characteristic of the gain of the filters  151 - 1  to  151 - 3  must be shifted dependent on the frequency of the playback clock. Because the control of the characteristic of the gain of the filters  151 - 1  to  151 - 3  dependent on the frequency of the playback clock is conventionally performed, the detailed explanation is omitted. Hereinafter, the control of the frequency characteristic of the delay, time of the filters  151 - 1  to  151 - 3  will be explained in detail. 
       FIG. 3  is a circuit diagram showing an example of an internal configuration of the filter  151 - 1  in the RF equalizer  15   a . Here, because the internal configurations of the filters  151 - 1  to  151 - 3  are the same, the internal configuration of the filter  151 - 1  is shown in  FIG. 3  as a representative. The filter  151 - 1  has a first operation amplifier  152  (first differential amplifier), a second operation amplifier  153  (second differential amplifier), a third operation amplifier  154  (third differential amplifier), a capacitor C 1  (first capacitor) a capacitor C 2  (second capacitor), and a buffer  155 . 
     An input signal vi of the filter  151 - 1  is inputted to the positive terminal of the first operation amplifier  152 , an output signal vo is inputted to the negative terminal thereof, and the gain gm 1  (first gain) thereof is controlled by the signal Vf 1  (first control signal). An output signal of the first operation amplifier  152  (first signal) is inputted to the positive terminal of the second operation amplifier  153 , the output signal vo is inputted to the negative terminal thereof, and the gain gm 2  (second gain) thereof is controlled by the signal Vf 3  (second control signal). The output signal vo is inputted to the positive terminal of the third operation amplifier  154 , the input signal vi is inputted to the negative terminal thereof, the gain gm 3  (third gain) thereof is controlled by the signal Vf 3 . The capacitor C 1  is connected between the output terminal of the operation amplifier  152  and the ground terminal (reference voltage terminal). The capacitor C 2  is connected between the input signal vi and the output terminal of the second operation amplifier  153  (here, the output signals terminals of the second and the third operation amplifiers  153  and  154  (second and third signal) are short-circuited). The output signal of the second operation amplifier  153  is inputted to the buffer  155 , and the buffer  155  generates the output signal vo. 
     The signals Vf 1  and Vf 3  are provided by the RF rate measuring and controlling circuit  28   b  of  FIG. 2 . Furthermore, the operation amplifiers  152  to  154  are supplied with supply voltage (e.g. 2.5V), which is not shown in  FIG. 3 . 
     The transfer function H (ω 1 , Q 1 )=vo/vi of the filter  151 - 1  is expressed by following equation (1). Here, s=j2nf (f is the frequency). 
     
       
         
           
             
               
                 
                   
                     vo 
                     vi 
                   
                   = 
                   
                     
                       1 
                       - 
                       
                         s 
                         ⁢ 
                         
                           
                             gm 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             
                               3 
                               · 
                               C 
                             
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             1 
                           
                           
                             gm 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             
                               1 
                               · 
                               gm 
                             
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             2 
                           
                         
                       
                       + 
                       
                         
                           s 
                           2 
                         
                         ⁡ 
                         
                           ( 
                           
                             
                               C 
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               
                                 1 
                                 · 
                                 C 
                               
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               2 
                             
                             
                               gm 
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               
                                 1 
                                 · 
                                 gm 
                               
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               2 
                             
                           
                           ) 
                         
                       
                     
                     
                       1 
                       + 
                       
                         s 
                         ⁢ 
                         
                           
                             
                               
                                 ( 
                                 
                                   
                                     gm 
                                     ⁢ 
                                     
                                         
                                     
                                     ⁢ 
                                     2 
                                   
                                   - 
                                   
                                     gm 
                                     ⁢ 
                                     
                                         
                                     
                                     ⁢ 
                                     3 
                                   
                                 
                                 ) 
                               
                               · 
                               C 
                             
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             1 
                           
                           
                             gm 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             
                               1 
                               · 
                               gm 
                             
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             2 
                           
                         
                       
                       + 
                       
                         
                           s 
                           2 
                         
                         ⁡ 
                         
                           ( 
                           
                             
                               C 
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               
                                 1 
                                 · 
                                 C 
                               
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               2 
                             
                             
                               gm 
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               
                                 1 
                                 · 
                                 gm 
                               
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               2 
                             
                           
                           ) 
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   1 
                   ) 
                 
               
             
           
         
       
     
     Both of gm 2  and gm 3  are cooperatively controlled by signal Vf 3 . When the second and the third operation amplifiers  153  and  154  are designed so as to satisfy the relationship of gm 2 =2*gm 3 , the following equation (2) is satisfied. 
     
       
         
           
             
               
                 
                   
                     vo 
                     vi 
                   
                   = 
                   
                     
                       
                         1 
                         - 
                         
                           s 
                           ⁢ 
                           
                             
                               C 
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               1 
                             
                             
                               
                                 2 
                                 · 
                                 gm 
                               
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               1 
                             
                           
                         
                         + 
                         
                           
                             s 
                             2 
                           
                           ⁡ 
                           
                             ( 
                             
                               
                                 C 
                                 ⁢ 
                                 
                                     
                                 
                                 ⁢ 
                                 
                                   1 
                                   · 
                                   C 
                                 
                                 ⁢ 
                                 
                                     
                                 
                                 ⁢ 
                                 2 
                               
                               
                                 gm 
                                 ⁢ 
                                 
                                     
                                 
                                 ⁢ 
                                 
                                   1 
                                   · 
                                   gm 
                                 
                                 ⁢ 
                                 
                                     
                                 
                                 ⁢ 
                                 2 
                               
                             
                             ) 
                           
                         
                       
                       
                         1 
                         + 
                         
                           s 
                           ⁢ 
                           
                             
                               C 
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               1 
                             
                             
                               
                                 2 
                                 · 
                                 gm 
                               
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               1 
                             
                           
                         
                         + 
                         
                           
                             s 
                             2 
                           
                           ⁡ 
                           
                             ( 
                             
                               
                                 C 
                                 ⁢ 
                                 
                                     
                                 
                                 ⁢ 
                                 
                                   1 
                                   · 
                                   C 
                                 
                                 ⁢ 
                                 
                                     
                                 
                                 ⁢ 
                                 2 
                               
                               
                                 gm 
                                 ⁢ 
                                 
                                     
                                 
                                 ⁢ 
                                 
                                   1 
                                   · 
                                   gm 
                                 
                                 ⁢ 
                                 
                                     
                                 
                                 ⁢ 
                                 2 
                               
                             
                             ) 
                           
                         
                       
                     
                     = 
                     
                       
                         
                           ω 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           
                             1 
                             2 
                           
                         
                         - 
                         
                           
                             
                               ω 
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               1 
                             
                             
                               Q 
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               1 
                             
                           
                           ⁢ 
                           s 
                         
                         + 
                         
                           s 
                           2 
                         
                       
                       
                         
                           ω 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           
                             1 
                             2 
                           
                         
                         + 
                         
                           
                             
                               ω 
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               1 
                             
                             
                               Q 
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               1 
                             
                           
                           ⁢ 
                           s 
                         
                         + 
                         
                           s 
                           2 
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   2 
                   ) 
                 
               
             
           
         
       
     
     Here, ω 1  is a parameter indicative of a characteristic angular frequency, and Q 1  is a parameter indicative of steepness of the filter  151 - 1  at the characteristic angular frequency ω 1 . They are expressed by following equations (3) and (4). 
     
       
         
           
             
               
                 
                   
                     ω 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     
                       1 
                       2 
                     
                   
                   = 
                   
                     
                       gm 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       
                         1 
                         · 
                         gm 
                       
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       2 
                     
                     
                       C 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       
                         1 
                         · 
                         C 
                       
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       2 
                     
                   
                 
               
               
                 
                   ( 
                   3 
                   ) 
                 
               
             
             
               
                 
                   
                     Q 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     1 
                   
                   = 
                   
                     
                       
                         
                           2 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           C 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           2 
                         
                         
                           gm 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           2 
                         
                       
                       · 
                       ω 
                     
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     1 
                   
                 
               
               
                 
                   ( 
                   4 
                   ) 
                 
               
             
           
         
       
     
       FIG. 4  is a graph showing an example of a frequency characteristic of a delay time τ of the filter  151 - 1  in the case of gm 1 *gm 2 =α (α=1/1.2, 1.0, and 1.2). The horizontal axis is the frequency, and the vertical axis is the delay time τ. Thus α is varied by controlling gm 1  to gm 3  by the signal Vf 1  and Vf 3  generated by the RF rate measuring and controlling circuit  28   b , thereby controlling the characteristic angular frequency ω 1  and the steepness Q 1  expressed by the equations (3) and (4) dependent on the value of α. As a result, the delay time of the RF signal can be controlled dependent on the frequency. As described above, the delay time of the RF signal can be controlled dependent on the frequency by controlling the time constants of the filters  151 - 1  to  151 - 3  by the signal Vf 1  to Vf 3 . 
       FIG. 5  is a graph showing a transfer function of the RF equalizer  15   a  of  FIG. 2  having the filters  151 - 1  to  151 - 3  with the internal configuration of  FIG. 3 . Parameters a 1  to a 3 , b 1  to b 3 , and k are constants determined by gains of the operation amplifiers in the filters  151 - 1  to  151 - 3  and the capacitances of the capacitors.  FIG. 6  is a graph showing an example of a frequency characteristic of the delay time τ of the RF equalizer  15   a  of  FIG. 5 . The horizontal and vertical axes are the same as  FIG. 4 . In  FIG. 6 , each curve of the frequency characteristic controlled by the control input signals Vf 1  to Vf 3  is expressed as g 1  to g 3 , respectively. 
     Here, as described above, the RF signal for the CD contains a signal component including plurality of channel frequencies of 3T to 11T as fundamental frequencies, while the RF signal of DVD contains that of 3T to 14T. Therefore, it is preferable that the filters  151 - 1  to  151 - 3  are designed so that the delay time can be controlled dependent on the frequency within these frequency bands. 
     More specifically, when the higher frequency component of the RF signal has longer delay time, the characteristic of the RF equalizer  15   a  is set so that the delay time of the RF signal becomes shorter as the frequency is higher, as the curve g 1  of  FIG. 6 . When the delay time of the RF signal is substantially constant regardless of the frequency, the characteristic of the RF equalizer  15   a  is set so that the delay time does not vary at the wide frequency range, as the curve g 2  of  FIG. 6 . When the higher frequency component of the RF signal has shorter delay time, the characteristic of the RF equalizer  15   a  is set so that the delay time of the RF signal becomes longer as the frequency is higher, as the curve g 3  of  FIG. 6 . By such a manner, the waveform distortion of the RF signal due to the tangential tilt can be adjusted. 
     By performing above described processing, the waveform distortion of the RF signal which has passed the RF equalizer  15   a  is corrected. Therefore, an output signal of the RF equalizer  15   a  will be hereinafter called as an equalized RF signal. 
     Here, the configuration of the filter of  FIGS. 2 ,  3  and  5  is only an example. The configuration of the RF equalizer  15   a  is not limited to these, and the internal configurations of the filters  151 - 1  to  151 - 3  can be modified variously. For example, when the order of the RF equalizer  15   a  is designed higher, the controllable range of the delay time can be widened. When the order of the RF equalizer  15   a  is designed lower, the circuit volume can be reduced. Furthermore, the internal configurations of the filters  151 - 1  to  151 - 3  are not necessarily the same. For example, the value of the capacitor C 1  or the like can be varied for each of the filters  151 - 1  to  151 - 3 . 
     Next, the internal configurations and operations of the multi slicing circuit  30   a  and the waveform distortion measuring circuit  30   b  will be explained. The multi slicing circuit  30   a  and the waveform distortion measuring circuit  30   b  has a waveform distortion detector. A slicing level Vsc (center level) of the second comparator  302  is generated by the integrating circuit  42  by integrating binarized data (reference binarized data) outputted from the second comparator  302 . That is, the slicing level Vsc is generated by a feedback loop composed of the second comparator  302  and the integrating circuit  42 . This feedback loop is composed based on a rule called DSV (Digital Sum Value) slice that the binarized data is modulated so that a time period of high level gets equal to that of low level averagely for a long time. The first slicing level Vsu is a level added by Vo (predetermined voltage) from the center level Vsc, and the third slicing level Vsd is a level subtracted by Vo from the center level Vsc. 
     Here, although the integrating circuit  42  is omitted in  FIG. 1  for convenience, a practical configuration is shown in  FIG. 2 . 
       FIG. 7  is an example of an operation waveform of the multi slicing circuit  30   a  and the waveform distortion measuring circuit  30   b . For simplification,  FIG. 7  shows an example of a case where the RF signal contains a single frequency component.  FIG. 7A  shows an example of a case where the waveform is distorted backward of the time axis direction, while  FIG. 7B  shows an example of a case where the waveform is distorted forward of the time axis direction. In general, when the tangential tilt occurs, the waveform is distorted as  FIG. 7A  or  FIG. 7B  dependent on whether the beam irradiated by the pickup  12  shifts forward or backward of the rotation direction of the disk surface. 
     The first comparator  301  (high threshold comparator) and the third comparator  303  (low threshold comparator) compare the equalized RF signal that has passed the RF equalizer  15   a  with the slicing level Vsu and Vsd to generate binarized data SU (second binarized data) and SD (first binarized data), respectively. The first and the third comparator  301  and  303  also provide the waveform distortion measuring circuit  30   b  with these binarized data SU and SD. The second comparator  302  (reference comparator) compares the equalized RF signal with the slicing level Vsc to generate binarized data as well. The second comparator  302  also provides the demodulating circuit  31  with the binarized data as an information signal. The slicing level Vsc is an intermediate level between the slicing levels Vsu and Vsd. 
     As shown in  FIG. 2 , the waveform distortion measuring circuit  30   b  has a detecting circuit  304 , an integrating circuit  305 , and an A/D-converting circuit  306 . The waveform distortion measuring circuit  30   b  detects the waveform distortion based on the binarized data SU and SD and provides the RF rate measuring and controlling circuit  28   b  with the detection result as described below. That is, as shown in  FIG. 7 , the detecting circuit  304  sets an output signal DET as “1” (first value) when the binarized data SD rises and sets the output signal DET as “0” (second value) when the binarized data SU rises. Furthermore, the detecting circuit  304  sets the output signal DET as “−1” (third value) when the binarized data SD falls and sets the output signal DET as “0” when the binarized data SU falls. Here, “1” corresponds to a supply voltage, “−1” to a ground voltage, and “0” to the intermediate voltage of these voltages, for example. Thus, the output signal DET of the detecting circuit  304  can be three values, comprising “1”, “0”, and “−1”. 
     The integrating circuit  305  integrates the output signal DET of the detecting circuit  304 . The A/D-converting circuit  306  converts the integrated voltage to a digital signal to generate a signal DISORTION (distortion detection signal) indicative of the distortion. For example, in the case of  FIG. 7A , because a time period Tu when the output signal DET is “1” is longer than a time period Td when the output signal DET is “−1”, the voltage obtained by integrating the signal DET (dashed line in  FIG. 7A ) is higher than the intermediate voltage. Therefore, the waveform distortion measuring circuit  30   b  can detect that the waveform with a frequency shown in the signal of  FIG. 7A  is distorted backward. 
     As described above, the integrating circuit  305  detects a positive and negative pulse width of the output signal DET of the detecting circuit  304 , and the waveform distortion measuring circuit  30   b  detects the waveform distortion. 
     Although only, a single frequency is shown in  FIG. 7 , the RF signal practically contains a plurality of channel frequency components. Therefore, the waveform distortion measuring circuit  30   b  detects a delay time of average frequency of the equalized RF signal (e.g. about 5T for CD). Furthermore, when the delay time is longer, the difference between the voltage obtained by integrating the signal DET and the intermediate voltage, gets larger. Additionally, in the case where the waveform is distorted backward of the time axis direction (in this case, the voltage obtained by integrating the signal DET is higher than the intermediate voltage) as shown in  FIG. 7A , as the frequency is higher, the delay time of the RF signal on the transmission path becomes longer. Contrarily, in the case where the waveform is distorted forward of the time axis direction (in this case, the voltage obtained by integrating the signal DET is lower than the intermediate voltage) as shown in  FIG. 7B , as the frequency is higher, the delay time of the RF signal on the transmission path becomes shorter. 
     That is, the signal DISTORTION, which is obtained by A/D-converting the voltage obtained by integrating the signal DET, is a signal indicative of the delay time of the average frequency of the RF signal and the tendency of the delay characteristic for the frequency. 
     The above described operation of the waveform distortion measuring circuit  30   b  is only an example, and various modifications can be conceivable. For example, without A/D-converting the voltage outputted from the integrating circuit  305  obtained by integrating the output signal DET, the voltage as an analog signal can be used by the RF rate measuring and controlling circuit  28   b . Furthermore, without using the integrating circuit  305 , by measuring the time periods Tu and Td as digital signals using high frequency clock, and the waveform distortion can be detected from the difference between the measured Tu and Td. 
     Hereinafter, an internal configuration and operation of the RF rate measuring and controlling circuit  28   b  will be explained.  FIG. 8  is a block diagram showing an example of the internal configuration of the RF rate measuring and controlling circuit  28   b . The RF rate measuring and controlling circuit  28   b  controls the transfer characteristic of the RF equalizer  15   a  by variably controlling the time constants of the filters  151 - 1  to  151 - 3  in the RF equalizer  15   a . The RF rate measuring and controlling circuit  28   b  is provided with the distortion detection signal DISTORTION, which is a digital signal from the waveform distortion measuring circuit  30   b . The RF rate measuring and controlling circuit  28   b  has a 1/N dividing circuit  281  (divider), a clock frequency measuring circuit  282 , a filtering circuit  283 , multiplying circuits  284   a  to  284   d , adding circuits  285   a  to  285   c , and D/A-converting circuits  286   a  to  286   c.    
       FIG. 9  is an example showing the operation of the RF rate measuring and controlling circuit  28   b . The 1/N dividing circuit  281  generates a divided clock by frequency-dividing the playback clock generated by the playback clock PLL  28  by 1/N. The clock frequency measuring circuit  282  samples the frequency of the divided playback clock using a measuring reference clock with much higher frequency than that of the divided clock. This measuring reference clock may be generated in the optical disk driving device, or may be provided from the outside of the device. 
     In the example of  FIG. 9 , the 1/N dividing circuit  281  generates the divided clock as N=14. The clock frequency measuring circuit  282  detects that the frequency of the divided clock is 1/7 times that of the measuring reference clock by sampling the divided clock using the measuring reference clock. Because the value of N is known, the clock frequency measuring circuit  282  can measure that the frequency of the playback clock is 14/7=2 times that of the measuring reference clock. Practically, when the value of N is set large, the clock frequency measuring circuit  282  can measure the frequency of the playback signal even if the frequency of the measuring reference clock is not so high. 
     Here, the frequency of the playback clock corresponds to 1/T (T is a cycle of 1 channel bit) and varies dependent on the rotation speed of the optical disk  11 . It is inevitable to measure the frequency of the playback clock in order to control the delay time dependent on the frequency of the RF signal as shown in  FIG. 6 . 
     The frequency data measured by the clock frequency measuring circuit  282  is inputted to the filtering circuit  283 . The filtering circuit  283  eliminates the high frequency noise so that the measurement result does not vary too much. The frequency data f 0  of the playback clock, which is a measurement result of the frequency, which has passed the filtering circuit  283  is multiplied by a control coefficient K 0  (first coefficient) by the multiplying circuit  284   a  (first multiplying circuit). 
     Here, the 1/N dividing circuit  281 , the clock frequency measuring circuit  282 , the filtering circuit  283  and the multiplying circuit  284   a , which are described above, perform digital signal processing. Each of the playback signal provided by the playback clock PLL  28 , the measuring reference clock and the frequency data f 0  of the playback clock is a digital signal. 
     On the other hand, the distortion detection signal DISTORTION outputted by the waveform distortion measuring circuit  30   b  is multiplied by a control coefficients K 1  to K 3  (second coefficient) by the multiplying circuits  284   b  to  284   d  (second multiplying circuit). The multiplied results are added to the output signal of the multiplying circuit  284   a  by the adding circuits  285   a  to  285   c . And the added signals are converted to analog signals Vf 1  to Vf 3  by the D/A-converting circuits  286   a  to  286   c . More specifically, the output signals DA 1  to DA 3  of the adding circuits  285   a  to  285   c  are expressed by the following equations (5) to (7).
 
 DA 1= K 0* f 0+ K 1*DISTORTION  (5)
 
 DA 2= K 0* f 0+ K 2*DISTORTION  (6)
 
 DA 3= K 0* f 0+ K 3*DISTORTION  (7)
 
     The output signals DA 1  to DA 3  of the adding circuit  285   a  to  285   c  expressed by equations (5) to (7) are converted to the analog signals Vf 1  to Vf 3  by the D/A-converting circuits  286   a  to  286   c , respectively. 
     The signals Vf 1  to Vf 3  are provided to the filters  151 - 1  to  151 - 3  in the RF equalizer  15   a  of  FIG. 3  as control input signals to control the frequency characteristics of the filters  151 - 1  to  151 - 3 . 
     The control coefficients K 0  to K 3  used by the multiplying circuits  284   a  to  284   d  are predetermined to a value suitable for a type of the pickup  12  so as to correct the frequency of the delay time of the RF signal caused by the tangential tilt. More specifically, when there is no waveform distortion of the equalized signal, the control coefficients K 0  to K 3  are set so that the transfer function of the RF equalizer  15   a  becomes the curve g 2  of  FIG. 6 . When the waveform of the equalized RF signal is distorted backward of the time axis direction as shown in  FIG. 7A , the control coefficients K 0  to K 3  are set so that the transfer function of the RF equalizer  15   a  becomes the curve g 1  of  FIG. 6  because the delay time of the RF signal on the transmission path becomes longer as the frequency is higher. The most suitable value of the coefficients K 0  to K 3  may be set depending on the result of experiment or simulation by varying the waveform of the RF signal. 
       FIG. 10  is a characteristic showing an example of the signals Vf 1  to Vf 3  versus the frequency of the playback clock. The horizontal axis is frequency data f 0  of the playback clock, and the horizontal axis is analog values of the signal Vf 1  to Vf 3 .  FIG. 10  shows an example of K 1 &gt;K 2 &gt;K 3  and the relationship between the signal DISTORTION and the waveform distortion of the RF signal is assumed below. That is, the value of the signal DISTORTION is set to be 0 when there is no waveform distortion in the equalized RF signal, and the sign of the signal DISTORTION is set to be negative when the waveform is distorted forward of the time axis direction of  FIG. 7A . 
       FIG. 10A  shows a case where there is no waveform distortion in the equalized RF signal. Because DISTORTION=0 in the above equations (5) to (7), Vf 1 =Vf 2 =Vf 3 . The values of the signals Vf 1  to Vf 3  vary dependent on the frequency data f 0  lineally, and the frequency characteristic of the gain of the RF equalizer  15   a  is controlled dependent on the signals Vf 1  to Vf 3 . 
     On the other hand,  FIG. 10B  shows a case where the waveform distortion is present in the equalized RF signal. The signals Vf 1  to Vf 3 , each of which has different values, are generated dependent on the value of the signal DISTORTION. As a result, the frequency characteristic of not only the gain but the delay time of the RF equalizer  15   a  is controlled, thereby obtaining the transfer characteristic that the delay time is different dependent on the frequency as shown in  FIG. 6 . Because this characteristic is opposite to that of the frequency characteristic of the delay time on the transmission path of the RF signal, the frequency characteristic of the delay time of the RF signal, in other words, the waveform distortion, can be corrected. 
     Here,  FIG. 10  is an example to simply explain the operation of the RF rate measuring and controlling circuit  28   b . The relationship between the signal DISTORTION and the waveform distortion of the RF signal and/or the control coefficients K 0  to K 3  are determined dependent on the configurations of the filters  151 - 1  to  151 - 3  etc. 
     An example has been explained where only the signals Vf 1  and Vf 3  are used in order to control the frequency characteristic of the RF equalizer  15   a  which has the second-order filters  151 - 1  to  151 - 3  in  FIG. 2  or the like. The signal Vf 2  can be used as well according to the configurations of the filters  151 - 1  to  151 - 3 , for example, in the case where they are odd-order. An example has been explained in  FIG. 8  where conversion to the analog signal is performed after digital processing is performed. However, the RF rate measuring and controlling circuit  28   b  can also output analog signals. In this case, the RF rate measuring and controlling circuit  28   b  performs only analog operation, thereby simplifying the circuit configuration. 
     As described above, according to the first embodiment, the multi slicing circuit  30   a  and the RF rate measuring and controlling circuit  28   b  detect the waveform distortion of the equalized RF signal. In order to correct the waveform distortion of the RF signal, the RF rate measuring and controlling circuit  28   b  generates the control input signals Vf 1  to Vf 3 , and the frequency characteristic of the delay time of the filters  151 - 1  to  151 - 3  in the RF equalizer  15   a  is controlled by the control input signals Vf 1  to Vf 3 . Therefore, even if the waveform distortion in the RF signal is caused by the tangential tilt, the waveform distortion can be corrected accurately. As a result, the margin of the pickup is not necessarily set to be extremely small so as the tangential tilt does not occur, thereby increasing the manufacturing yield of the pickup. 
     Second Embodiment 
     In the first embodiment, the multi slicing circuit  30   a  and the RF rate measuring and controlling circuit  28   b  detect the waveform distortion of the equalized RF signal, and the RF rate measuring and controlling circuit  28   b  controls the filters  151 - 1  to  151 - 3  in the RF equalizer  15   a  dependent on the detected distortion. In a second embodiment, which will be described below, the system controller  38  controls the filter  151 - 1  to  151 - 3  without detecting the waveform distortion of the RF signal. 
       FIG. 11  is a block diagram showing a schematic configuration of an optical disk drive device according to the second embodiment of the present invention. In  FIG. 11 , parts common to those of  FIG. 1  have common reference numerals, respectively. Hereinafter, different parts from  FIG. 1  will be mainly described. The optical disk drive device has a data slicing circuit  30   c  instead of the multi slicing circuit  30   a . The data slicing circuit  30   c  binarizes the equalized RF signal and provides its binarized data to the demodulating circuit  31  as an information signal. The data slicing circuit  30   c  can be composed of a comparator (not shown) because the data slicing circuit  30   c  does not detect the waveform distortion of the equalized RF signal different from the multi slicing circuit  30   a . Furthermore, the waveform distortion measuring circuit is unnecessary in  FIG. 11 . 
     The internal configuration of the RF rate measuring and controlling circuit  28   b  is the same as that of  FIG. 8 . However, the RF rate measuring and controlling circuit  28   b  is provided with a digital distortion control signal from the system controller  38 , instead of the signal DISTORTION. 
     The RF rate measuring and controlling circuit  28   b  measures the frequency of the playback clock like the first embodiment. The system controller  38  has a plurality of predetermined coefficients for controlling the filters  151 - 1  to  151 - 3  and provides the RF rate measuring and controlling circuit  28   b  with one of them as the distortion control signal. The RF rate measuring and controlling circuit  28   b  of  FIG. 8  generates the control input signals Vf 1  to Vf 3  inputted to the filters  151 - 1  to  151 - 3  based on the measurement result of the frequency of the playback clock and the distortion control signal provided by the system controller  38 . Therefore, the transfer characteristic of the RF equalizer  15   a  can be controlled so that the delay time is adjusted dependent on the frequency as shown in  FIG. 6 . 
     On the other hand, the system controller  38  constantly acquires an error flag generated by the data correcting and parity generating circuit  33 . When errors are present in the playback data, the data correcting and parity generating circuit  33  generates the error flag when performing the correcting process. As there are more errors, the error flags are generated more frequently. The system controller  38  monitors the error flag and changes the coefficients by turns to update the distortion control signal provided to the RF rate measuring and controlling circuit  28   b . The system controller  38  finally selects the best coefficient which reduces the frequency of the error. 
     As described above, according to the second embodiment, the system controller  38  controls the filters  151 - 1  to  151 - 3  without detecting the waveform distortion of the RF signal. Therefore, the multi slicing circuit  30   a  and the waveform distortion measuring circuit  30   b  are unnecessary, and the circuit volume can be reduced. Furthermore, the waveform of the RF signal can be corrected even if the waveform distortion of the RF signal can not be detected. In addition, because the system controller  38  monitors the error flag, the best coefficient which reduces the frequency of the error can be selected to control the transfer characteristic of the filters  151 - 1  to  151 - 3 . 
     As a modification example of the present embodiment, the optical disk drive device of  FIG. 11  can have the multi slicing circuit  30   a  and the waveform distortion measuring circuit  30   b  like that of  FIG. 1 . In this example, when the waveform distortion measuring circuit  30   b  can detect the waveform distortion of the RF signal, the filters  151 - 1  to  151 - 3  are controlled dependent on the detected waveform distortion as well as the first embodiment. When the waveform distortion measuring circuit  30   b  cannot detect the waveform distortion of the RF signal, for example, when there are a lot of jitters, the system controller  38  controls the filters  151 - 1  to  151 - 3  in a manner of the present embodiment. 
     Although in the above described embodiments, examples of driving CD and DVD have been explained, the present invention can be applied to other optical disks such as HD (High Definition) DVD and BD (Blu-ray Disk). 
     The configurations capable of performing both record and playback are explained in  FIG. 1  and  FIG. 11 . However, the present invention is applicable to an optical disk drive device for only playback because there are cases where only the playback of the optical disk is required. 
     Although based on above description, those skilled in the art can figure out additional effects and variations of the present invention, the aspect of the present invention is not limited to the stated each embodiments. Various additions, alterations and partial deletions can be done to the present invention within the conceptualistic thought and purpose of the present invention drawn on the claims and the equivalents.