Patent Publication Number: US-2022216205-A1

Title: Method of forming a single metal that performs n work function and p work function in a high-k/metal gate process

Description:
PRIORITY 
     This is a continuation of U.S. application Ser. No. 15/961,935, filed on Apr. 25, 2018, which is a continuation of U.S. application Ser. No. 14/013,960, filed on Aug. 29, 2013, now issued U.S. Pat. No. 9,960,160, which is a divisional of U.S. application Ser. No. 12/492,889, filed on Jun. 26, 2009, now issued U.S. Pat. No. 8,524,588, which claims priority to U.S. Provisional Application Ser. No. 61/089,674 filed on Aug. 18, 2008. The entire disclosure of each of the applications above is incorporated herein by reference. 
    
    
     BACKGROUND 
     The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed. 
     In the course of integrated circuit evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling-down also produces a relatively high power dissipation value, which may be addressed by using low power dissipation devices such as complementary metal-oxide-semiconductor (CMOS) devices. 
     During the scaling trend, various materials have been implemented for the gate electrode and gate dielectric for CMOS devices. There has been a desire to fabricate these devices with a metal material for the gate electrode and a high-k dielectric for the gate dielectric. However, an n-type MOS device (NMOS) and a p-type MOS device (PMOS) require different work functions for their respective gate electrode. Several approaches have been implemented to achieve N and P work functions, simultaneously, for the metal gates. One approach uses additional metal and/or cap layers for the gate stack to achieve both N and P work functions. Although this approach has been satisfactory for its intended purpose, it has not been satisfactory in all respects. For example, the approach increases the complexity of the gate stack in NMOS and PMOS devices, and thus increases the difficulty of patterning the gate stack. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. 
         FIG. 1  is a flow chart illustrating a method for fabricating a semiconductor device in a high-k/metal gate process according to various aspects of the present disclosure; and 
         FIGS. 2A to 2F  are cross-sectional views of a semiconductor device at various stages of fabrication according to the method of  FIG. 1 . 
     
    
    
     DETAILED DESCRIPTION 
     It is to be understood that the following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. Moreover, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed interposing the first and second features, such that the first and second features may not be in direct contact. Various features may be arbitrarily drawn in different scales for simplicity and clarity. 
     Illustrated in  FIG. 1  is a flowchart of a method  100  for fabricating a semiconductor device in a high-k/metal gate process.  FIGS. 2A to 2F  illustrate cross-sectional views of one embodiment of a semiconductor device  200  at various stages of fabrication according to the method  100  of  FIG. 1 . It is understood that  FIGS. 2A to 2F  have been simplified to better understand the inventive concepts of the present disclosure. 
     Referring to  FIG. 1 , the method  100  begins with block  110  in which a high-k dielectric material may be formed over a semiconductor substrate. Referring also to  FIG. 2A , the semiconductor device  200  includes the semiconductor substrate  202  such as a silicon substrate. The substrate  202  may include various doping configurations depending on design requirements as is known in the art. The substrate  202  may also include other elementary semiconductors such as germanium and diamond. Alternatively, the substrate  202  may include a compound semiconductor and/or an alloy semiconductor. Further, the substrate  202  may optionally include an epitaxial layer (epi layer), may be strained for performance enhancement, and may include a silicon-on-insulator (SOI) structure. 
     The semiconductor device  200  may further include an isolation structure  204  such as a shallow trench isolation (STI) feature formed in the substrate  202  for isolating active regions  206  and  208  in the substrate. The isolation structure  204  may be formed of silicon oxide, silicon nitride, silicon oxynitride, fluoride-doped silicate (FSG), and/or a low k dielectric material known in the art. The active region  206  may be configured for an N-type metal-oxide-semiconductor transistor device (referred to as NMOS) and the active region  208  may be configured for a P-type MOS transistor device (referred to as PMOS). It is understood the semiconductor device  200  may be formed by complementary MOS (referred to as CMOS) technology processing, and thus some processes are not described in detail herein. The semiconductor device  200  may further include an interfacial layer  210  formed over the substrate  202 . The interfacial layer  210  may include a grown silicon oxide layer having a thickness ranging from about 5 to 10 angstrom (A). The semiconductor device  200  may further include a high-k dielectric layer  212  formed on the interfacial layer  210 . The high-k dielectric layer  212  may include hafnium oxide (HfO 2 ). Alternatively, the high-k dielectric layer  212  may optionally include other high k dielectric materials such as hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), and combinations thereof. 
     The high-k dielectric layer  212  may be formed by atomic layer deposition (ALD) or other suitable technique. Additionally, a capping layer may be formed on the high-k dielectric layer  212 , or may be formed between the high-k dielectric layer  212  and interfacial layer  210 , or may be formed on and underneath the high-k dielectric layer  212 . The capping layer may include lanthanum oxide (LaO), aluminum oxide (Al 2 O3), or other suitable material. In some embodiments, the capping layer may be used to tune a work function of a metal layer (for the gate electrode) for properly performing as an NMOS transistor device and a PMOS transistor device, respectively. 
     The method  100  continues with block  120  in which a metal layer may be formed over the high-k dielectric layer. The metal layer  214  may have a first work function such as an N-metal work function. For example, the metal layer  214  may include various metals, such as TiN, TaC, or TaN, having the N-metal work function. The metal layer  214  may be formed by various deposition techniques such as chemical vapor deposition (CVD), physical vapor deposition (PVD or sputtering), plating, or other suitable technique. The method  100  continues with block  130  in which a hard mask layer  216  may be formed over the metal layer  214 . The hard mask layer  216  may include silicon oxide, silicon oxynitride, silicon nitride, or other suitable material. 
     The method  100  continues with block  140  in which the hard mask layer  216  may be patterned to protect a portion of the metal layer  214  in the NMOS region  206 . The hard mask  216  may be patterned by first forming a patterned photoresist layer  218  over the hard mask layer  216 , and then dry or wet etching to remove a portion of the hard mask layer  216  in the PMOS region  208 . The patterned photoresist layer  218  may be formed by photolithography, immersion lithography, or other suitable process known in the art. For example, the photolithography process may include spin coating, soft-baking, exposure, post-baking, developing, rinsing, drying, and other suitable process. Referring also to  FIG. 2B , the portion of the hard mask that is not protected by the patterned photoresist  218  may be removed by the etching process, and thus a portion  220  of the hard mask remains overlying the NMOS region  206 . The patterned photoresist  218  may be removed by a stripping process or other suitable process. 
     Referring also to  FIG. 2C , the method  100  continues with block  150  in which the unprotected portion of the metal layer may be treated such that the unprotected portion changes from the first work function to a second work function. In the present example, the unprotected portion  230  may be treated  225  with a plasma such that the work function changes (or adjusts) from an N-metal work function to a P-metal work function. Accordingly, the protected portion  228  of the metal layer remains unchanged with an N-metal work function. For example, the plasma treatment may include an O 2  plasma with the following process conditions: source power ranging from about 300 to 600 W, bias power ranging from about 0 to 20 W, pressure at about 7.5 mtorr, gas flow including 30 sccm O 2 /0 to 130 sccm Ar, and process time ranging from about 30 to 100 seconds. In another example, the plasma treatment may include N 2  plasma. 
     In another embodiment, the treatment  225  may include an implantation process. For example, the implantation process may include O implantation with the following process conditions: implant energy ranging from 1 to 5 KeV, implant concentration ranging from about 1E15 to 1E16 atoms/cm 3 , and implant tilt angle of about 7 degrees. In another example, the implantation process may include Al implantation with the following process conditions: implant energy ranging from about 1 to 5 KeV, implant concentration ranging from about 1E15 to 1E16 atoms/cm 3 , and implant tilt angle of about 7 degrees. In some embodiments, the Al concentration in TiN for N-metal work function may be n-TiAlN having 30% [N] and 17.5% [Al], and for P-metal work function may be p-TiAlN having 50% [N] and 12.5% [Al]. Also, a combination of a plasma process and an implantation process may be used. It is understood that the various parameters and concentrations disclosed above are examples, and that these parameters and concentrations may be tuned for optimization depending on the process tools and the operating environment without departing from the spirit and scope of the present disclosure. 
     Referring also to  FIG. 2D , the method  100  continues with block  160  in which the hard mask  220  may be removed. The hard mask  220  may be removed by a wet or dry etch process known in the art. Referring also to  FIG. 2E , the method  100  continues with block  170  in which a metal gate having the first work function may be formed from the untreated portion of the metal layer, and a metal gate having the second work function may be formed from the treated portion of the metal layer. Following the removal of the hard mask  220 , a polysilicon (or poly) layer  240  may be formed over the N-metal  228  and the P-metal  230  by a suitable deposition process. A hardmask layer  250  may be formed over the poly layer  240 . The hard mask layer  250  may include SiN, SiON, SiC, SiOC/PEOX, TEOS, or other suitable material. Additionally, an anti-reflective coating or bottom anti-reflective coating (BARC) may be formed on the hard mask layer  250  as is known in the art. A patterned photoresist layer may be formed with a gate pattern  261  for the NMOS region  206  and a gate pattern  262  for the PMOS region  208 . The gate patterns  261 ,  262  may be formed by photolithography, immersion lithography, or other suitable process as was discussed above. 
     Referring also to  FIG. 2F , the hard mask layer  250  may be patterned by a dry or wet etching process using the gate patterns  261 ,  262 , and the patterned hard mask layer may be used to pattern a gate stack  281  in the NMOS region  206  and a gate stack  282  in the PMOS region  208 . The gate stacks  281 ,  282  may be formed by a dry or wet etching process (e.g., gate patterning). The gate stack  281  in the NMOS region  206  may include a poly layer  240   a , an N-metal  228   a , a high-k dielectric  212   a  (with or without a capping layer), and an interfacial layer  210   a . The gate stack  282  in the PMOS region  208  may include a poly layer  240   b , a P-metal  230   b , a high-k dielectric  212   b  (with or without a capping layer), and an interfacial layer  210   b . It should be noted that prior to the gate patterning, the N-metal layer  228  and the P-metal layer  230  may have a similar composition and thickness, and thus gate patterning in the NMOS region  206  and the PMOS region  208  becomes less difficult as compared to pattering gate stacks with varying thicknesses. 
     It is understood that the semiconductor device  200  may undergo further CMOS or MOS technology processing to form various features known in the art. For example, gate sidewall spacers may be formed on both sides of the gate stacks  281 ,  282  by a deposition and etching process. The gate spacers may include a suitable dielectric material such as silicon nitride, silicon oxide, silicon carbide, silicon oxynitride, or combinations thereof. In another example, source and drain regions (referred to as S/D regions) may be formed in the substrate  202  using ion implantation or diffusion with suitable dopants (depending on the configuration of the device such as NMOS and PMOS) and located proximate to each end of the gate stacks  281 ,  282  (the high-k gate dielectric and metal gate electrode), respectively. In still another example, various contacts/vias and multilayer interconnect features (e.g., metal layers and interlayer dielectric) may be formed on the substrate  202  and configured to connect the various features or structures of the semiconductor device  200 . 
     The present invention achieves different advantages in various embodiments. For example, the present disclosed method provides a simple and cost-effective single metal layer that performs both N-metal work function and P-metal work function for NMOS and PMOS devices, respectively. Accordingly, patterning the gate structures for NMOS and PMOS devices becomes easier since the corresponding gate stacks have a similar composition and thickness. Accordingly, performance of the NMOS and PMOS transistor devices may become more reliable and predictable. Also, the methods disclosed herein are compatible with current CMOS technology process flow, and thus can easily be integrated with current processing equipment and device technologies. It is understood that different embodiments disclosed herein offer several different advantages, and that no particular advantage is necessarily required for all embodiments. 
     Thus, the present disclosure provide a method of fabricating a semiconductor device that includes forming a gate dielectric over a semiconductor substrate, forming a capping layer over or under the gate dielectric, forming a metal layer over the capping layer, the metal layer having a first work function, treating a portion of the metal layer such that a work function of the portion of the metal layer changes from the first work function to a second work function, and forming a first metal gate from the untreated portion of the metal layer having the first work function and forming a second metal gate from the treated portion of the metal layer having the second work function. 
     Also provided is a semiconductor device that includes a semiconductor substrate, an isolation structure formed in the substrate for isolating a first active region and a second active region, a first transistor formed in the first active region, the first transistor having a high-k gate dielectric, a first capping layer formed over or under the high-k gate dielectric, and a metal gate with a first work function formed over the first capping layer, and a second transistor formed in the second active region, the second transistor having the high-k gate dielectric, a second capping layer formed over or under the high-k gate dielectric, and a metal gate with a second work function formed over the second capping layer. The metal gates of the first transistor and the second transistor are formed from at least a single metal layer having the first work function and the second work function. 
     The foregoing has outlined features of several embodiments so that those skilled in the art may better understand the detailed description that follows. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure. For example, although the embodiments have been described in a gate first process, the methods disclosed herein are also applicable in a gate last process or a hybrid process that includes both gate first and gate last processes. Further, it is understood that the semiconductor devices disclosed herein are not limited to a specific transistor and may include other active and passive devices such as a finFET transistor, a high voltage transistor, a bipolar junction transistor (BJT), a capacitor, a resistor, a diode, a fuse, or combinations thereof