Patent Publication Number: US-8970255-B2

Title: Frequency detection apparatus with internal output voltage which changes along with input signal frequency

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The disclosed embodiments of the present invention relate to frequency detection, and more particularly, to a frequency detection apparatus with an internal output voltage which changes along with an input signal frequency of an input signal. 
     2. Description of the Prior Art 
     Power consumption in the normal operation mode and the standby mode of electronic devices needs to be taken care since the low power requirement is highly demanded in today&#39;s communication systems. Particularly, power management designs of portable devices now face new challenges regarding aspects of core and I/O voltages, power management, battery life, etc. A buck converter with synchronous rectification, which is widely applied in portable devices, provides a power saving mode to maintain high efficiency over the entire load range. The converter operates in a pulse frequency modulation (PFM) mode in a light load case, and switches to a pulse width modulation (PWM) mode automatically in a medium or heavy load case. The conventional architecture may need to detect voltage loads of components other than core components, for instance, I/O components; therefore, it consumes more power and has a larger die size. Hence, how to switch between PFM and PWM more efficiently has become an important issue in this field. 
     SUMMARY OF THE INVENTION 
     Therefore, one of the objectives of the present invention is to provide a frequency detection apparatus with an internal output voltage which changes along with an input signal frequency of an input signal, so as to allow the mode switching between PFM and PWM to be more efficient. 
     According to a first embodiment of the present invention, a frequency detection apparatus is disclosed. The frequency detection apparatus comprises a constant current generator, a first capacitor, a first transistor, a second capacitor, and a second transistor. The constant current generator is arranged for providing a constant current to a voltage output terminal; the first capacitor is coupled between the voltage output terminal and a first reference voltage; the first transistor has a first connection terminal, a control terminal, and a second connection terminal, wherein the first connection terminal is coupled to the voltage output terminal, and the control terminal is coupled to an input signal; the second capacitor is coupled between the second connection terminal of the first transistor and the first reference voltage; the second transistor has a first connection terminal, a control terminal, and a second connection terminal, wherein the first connection terminal of the second transistor is coupled to the second connection terminal of the first transistor, the second connection terminal of the second transistor is coupled to the first reference voltage, and the control terminal of the second transistor is coupled to an inverted input signal; wherein a voltage output of the voltage output terminal changes in pace with an input signal frequency of the input signal. 
     According to a second embodiment of the present invention, a frequency detection apparatus is disclosed. The frequency detection apparatus comprises a constant current generator and a frequency-voltage conversion unit. The constant current generator is arranged for providing a constant current to a voltage output terminal; and the frequency-voltage conversion unit is arranged for receiving an input signal, an inverted input signal and the constant current, and generating a voltage output at a voltage output terminal in accordance with the input signal, the inverted input signal and the constant current; wherein there is a predetermined proportion relationship between the voltage output and an input signal frequency of the input signal. 
     These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a diagram illustrating a frequency detection apparatus according to an embodiment of the present invention. 
         FIG. 2  is a diagram illustrating a frequency detection apparatus according to an embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION 
     Certain terms are used throughout the description and following claims to refer to particular components. As one skilled in the art will appreciate, manufacturers may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not function. In the following description and in the claims, the terms “include” and “comprise” are used in an open-ended fashion, and thus should be interpreted to mean “include, but not limited to . . . ”. Also, the term “couple” is intended to mean either an indirect or direct electrical connection. Accordingly, if one device is electrically connected to another device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections. 
     Please refer to  FIG. 1 , which is a diagram illustrating a frequency detection apparatus  100  according to an embodiment of the present invention. The frequency detection apparatus  100  includes a constant current generator  102 , a frequency-voltage conversion unit  104  and a comparator  106 . The constant current generator  102  is utilized to provide a constant current I total  to a voltage output terminal N out  of the frequency-voltage conversion unit  104 . The frequency-voltage conversion unit  104  is utilized to receive an input signal S PFM , an inverted input signal  S   PFM  and the constant current I total , wherein the inverted input signal  S   PFM  is an inverted version of the input signal S PFM . The frequency-voltage conversion unit  104  generates a voltage output V out  at a voltage output terminal N out  according to the input signal S PFM , the inverted input signal  S   PFM  and the constant current I total . The voltage output V out  changes along with an input signal frequency f of the input signal S PFM . The comparator  106  has a first input terminal (+) and a second input terminal (−), wherein the first input terminal (+) is coupled to the voltage output terminal N out , and the second input terminal (−) is coupled to a predetermined voltage V pd  corresponding to a predetermined frequency f pd . The comparator  106  is utilized to determine whether the input signal frequency f of the input signal S PFM  exceeds the predetermined frequency f pd . 
     More specifically, the constant current generator  102  includes a first resistor  1022 , a first transistor  1024 , a second transistor  1026 , a third transistor  1028 , an amplifier  1030  and a second resistor  1032 . The first resistor  1022  has a resistance value R and is coupled between a second reference voltage V 2  and the voltage output terminal N out . The first transistor  1024  has a first connection terminal, a control terminal and a second connection terminal, wherein the first connection terminal is coupled to the voltage output terminal N out , and the second connection terminal is coupled to the second reference voltage V 2 . The second transistor  1026  has a first connection terminal, a control terminal and a second connection terminal, wherein the first connection terminal of the second transistor  1026  is coupled to the control terminal of the first transistor  1024  and the control terminal of the second transistor  1026 , and the second connection terminal of the second transistor  1026  is coupled to the second reference voltage V 2 . The third transistor  1028  has a first connection, a control terminal and a second connection terminal, wherein the first connection terminal of the third transistor  1028  is coupled to the first connection terminal of the second transistor  1026 . The amplifier  1030  has a positive input terminal (+), a negative input terminal (−) and an output terminal, wherein the positive terminal (+) is coupled to the voltage output terminal, the negative input terminal (−) is coupled to the second connection terminal of the third transistor  1028 , and the output terminal is coupled to the control terminal of the third transistor  1028 . The second resistor  1032  may have a resistance value R the same as that of the first resistor  1022 , and the second resistor  1032  is coupled between the second connection terminal of the third transistor  1028  and the first reference voltage V 1  (the first reference voltage V 1  may be a ground voltage in this embodiment). It should be noted that, in practice, the transistors in this embodiment may be replaced with any other designs which are able to achieve functions similar to switches, and these alternative designs all fall within the scope of the present invention. For instance, the transistors in this embodiment may be Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs), and the first connection terminal, the control terminal and the second connection terminal of each transistor may be a drain terminal, a gate terminal, and a source terminal, respectively. 
     The output terminal of the amplifier  1030  is coupled to the control terminal of the third transistor  1028 . The positive input terminal (+) of the amplifier  1030  receives the voltage output V out  generated by the voltage output terminal N out . The negative input terminal (−) of the amplifier  1030  outputs an output voltage V out  and is coupled to the register  1032 , such that the voltage output V out  is converted into a control current I through the register  1032   
               (       i   .   e   .           ⁢   I     =       V   out     R       )     .         
In addition, the transistor  1024  and the transistor  1026  in this embodiment may have the same aspect ratio; therefore, the transistor  1024  will obtain a current the same as the control current I flowing through the transistor  1026  due to a current mirror. The constant current generator  102  provides the constant current I total  to the voltage output terminal of the frequency-voltage conversion unit  104 . Hence, the overall constant current I total  may be expressed as:
 
     
       
         
           
             
               
                 
                   
                     I 
                     total 
                   
                   = 
                   
                     
                       
                         
                           V 
                           out 
                         
                         R 
                       
                       + 
                       
                         
                           
                             V 
                             2 
                           
                           - 
                           
                             V 
                             out 
                           
                         
                         R 
                       
                     
                     = 
                     
                       
                         V 
                         2 
                       
                       R 
                     
                   
                 
               
               
                 
                   ( 
                   1 
                   ) 
                 
               
             
           
         
       
     
     That is to say, the constant current I total  has a fixed current value, and is not affected by the voltage output V out  of the voltage output terminal N out  of the frequency-voltage conversion unit  104 . It should be noted that the operations of the constant current generator  102  are not detailed in the present invention due to the fact that those skilled in this field should readily understand the principles of the constant current generator  102  after referring to the descriptions set forth and the equation (1). Therefore, the details of the constant current generator  102  are omitted here for brevity. In addition, the design of the constant current generator  102  (e.g. the aspect ratios of the transistors  1024  and  1026 ) is for illustrative purpose only. In practice, any alternative designs that achieve the same objective all fall within the scope of the present invention. 
     The frequency-voltage conversion unit  104  includes a first capacitor  1042 , a first transistor  1044 , a second capacitor  1046  and a second transistor  1048 . The first capacitor  1042  has a capacitance C 1 , and is coupled between the voltage output terminal N out  and the first reference voltage V 1 . The first transistor  1044  has a first connection terminal, a control terminal and a second connection terminal, wherein the first connection terminal is coupled to the voltage output terminal N out , and the control terminal is coupled to the input signal S PFM . The second capacitor  1046  has a capacitance C 2 , and is coupled between the second connection terminal of the first transistor and the first reference voltage V 1 . The second transistor  1048  has a first connection terminal, a control terminal and a second connection terminal, wherein the first connection terminal of the second transistor  1048  is coupled to the second connection terminal of the first transistor  1044 , the second connection terminal of the second transistor  1048  is coupled to the first reference voltage V 1 , and the control terminal of the second transistor  1048  is coupled to the inverted input signal  S   PFM . In this embodiment, the input signal S PFM  is an output signal generated via PFM and having a frequency equal to the input signal frequency f. 
     The operation principle of the frequency detection device  100  of the present invention will be described as follows. Please refer to  FIG. 1 . The conduction status of the first transistor  1044  in the frequency-voltage conversion unit  104  is determined pursuant to the input signal S PFM ; and the conduction status of the second transistor  1048  in the frequency-voltage conversion unit  104  is determined pursuant to the inverted input signal  S   PFM . Therefore, the operation of the frequency-voltage conversion unit  104  may be separated into two phases. In the first phase, the input signal S PFM  is logic low ‘0’, the inverted input signal  S   PFM  is logic high ‘1’, the first transistor  1044  is turned off, and the second transistor  1048  is turned on; meanwhile, the charging operation performed upon the capacitor  1042  by the constant current I total  may be expressed as follows: 
                     I   total     =           C   1     ⁢       ⅆ   v       ⅆ   t         ⇒       ∫   0     V   1       ⁢     ⅆ   v         =             I   total       C   1       ⁢       ∫   0     1     2   ⁢   f         ⁢     ⅆ   t         ⇒     V   1       =         I   total       C   1       ⁢     1     2   ⁢   f                     (   2   )               
where V 1  is the increased voltage across the capacitor  1042 , and f is the frequency of the input signal S PFM  and the inverted input signal  S   PFM .
 
     In the second phase, the input signal S PFM  is logic high ‘1’, the inverted input signal  S   PFM  is logic low ‘0’, the first transistor  1044  is turned on, and the second transistor  1048  is turned off. Since the first transistor  1044  is turned on, the charge sharing effect is induced around the first and the second capacitors  1042  and  1046 . The derivations concerned may be expressed as follows: 
                       V   1     ⁢     C   1       =           V   x     ⁡     (       C   1     +     C   2       )       ⇒     V   X       =         C   1         C   1     +     C   2         ⁢     V   1                 (   3   )               
where V x  is the decreased voltage across the capacitor  1046 , which is a result of the charge sharing effect.
 
     Therefore, in the second phase, the charging operation performed upon the capacitor  1042  by the constant current I total  may be expressed as follows: 
                     I   total     =       ⁢           (       C   1     +     C   2       )     ⁢       ⅆ   v       ⅆ   t         ⇒       ∫     v   x       v   2       ⁢     ⅆ   v         =             I   total         C   1     +     C   2         ⁢       ∫     1     2   ⁢   f         1   f       ⁢     ⅆ   t         ⇒       V   2     -     V   x         =         I   total         C   1     +     C   2         ⁢     1     2   ⁢   f                     (   4   )                 V   2     =       ⁢         V   x     +         I   total         C   1     +     C   2         ⁢     1     2   ⁢   f           =           C   1         C   1     +     C   2         ⁢     V   1       +         I   total         C   1     +     C   2         ⁢     1     2   ⁢   f                     (   5   )               
where V 2  is the increased voltage across the capacitor  1042  during the period of the second phase.
 
     Since the first phase and the second phase will continue to repeat, it can be assumed that: 
     
       
         
           
             β 
             = 
             
               
                 C 
                 1 
               
               
                 
                   C 
                   1 
                 
                 + 
                 
                   C 
                   2 
                 
               
             
           
         
       
       
         
           
             
               V 
               C 
             
             = 
             
               
                 
                   I 
                   total 
                 
                 
                   
                     C 
                     1 
                   
                   + 
                   
                     C 
                     2 
                   
                 
               
               ⁢ 
               
                 1 
                 
                   2 
                   ⁢ 
                   f 
                 
               
             
           
         
       
     
     Thus, the voltage output V out  of the voltage output terminal N out  of the frequency-voltage conversion unit  104  can be obtained through the following deductions: 
     
       
         
           
             
               
                 
                   
                     V 
                     
                       2 
                       ⁢ 
                       n 
                     
                   
                   = 
                   
                     
                       
                         ( 
                         
                           
                             β 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             
                               V 
                               1 
                             
                           
                           + 
                           
                             V 
                             out 
                           
                         
                         ) 
                       
                       ⁢ 
                       
                         ( 
                         
                           
                             β 
                             
                               n 
                               - 
                               1 
                             
                           
                           + 
                           
                             β 
                             
                               n 
                               - 
                               2 
                             
                           
                           + 
                           … 
                           + 
                           1 
                         
                         ) 
                       
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       
                         =&gt; 
                       
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       
                         V 
                         out 
                       
                     
                     = 
                     
                       
                         I 
                         total 
                       
                       
                         fC 
                         2 
                       
                     
                   
                 
               
               
                 
                   ( 
                   6 
                   ) 
                 
               
             
           
         
       
     
     Further, the relation of the control current I and the voltage output V out  can be expressed as: 
     
       
         
           
             
               
                 
                   I 
                   = 
                   
                     
                       
                         
                           V 
                           out 
                         
                         R 
                       
                       -&gt; 
                       
                         I 
                         total 
                       
                     
                     = 
                     
                       
                         V 
                         2 
                       
                       R 
                     
                   
                 
               
               
                 
                   ( 
                   7 
                   ) 
                 
               
             
           
         
       
     
     The signal frequency f of the input signal S PFM  and the inverted input signal  S   PFM  can be derived by combining the equations (6) and (7), and is expressed as: 
     
       
         
           
             
               
                 
                   
                     f 
                     = 
                     
                       
                         V 
                         2 
                       
                       
                         
                           RC 
                           2 
                         
                         ⁢ 
                         
                           V 
                           out 
                         
                       
                     
                   
                   , 
                   
                     
 
                   
                   ⁢ 
                   or 
                 
               
               
                 
                   ( 
                   8 
                   ) 
                 
               
             
             
               
                 
                   
                     V 
                     out 
                   
                   = 
                   
                     
                       V 
                       2 
                     
                     
                       fRC 
                       2 
                     
                   
                 
               
               
                 
                   ( 
                   9 
                   ) 
                 
               
             
           
         
       
     
     Wherein if the voltage output V out  and the increased voltage V 2  across the capacitor  1042  are both fixed, and the signal frequency f relates to RC 2 , thus the signal frequency f of the input signal S PFM  and the inverted input signal  S   PFM  can be derived precisely when RC 2  is processed, for example, by a calibration process. In other words, the voltage output V out  of the voltage output terminal N out  of the frequency-voltage conversion unit  104  is inversely proportional to the input signal frequency f of the input signal S PFM , that is to say, the higher is the signal frequency f of the input signal S PFM , the lower the voltage output V out  of the voltage output terminal N out  is. And the voltage output V out  of the voltage output terminal N out  of the frequency-voltage conversion unit  104  is inversely proportional to the value of R or C 2 . 
     When the signal frequency f of the input signal S PFM  becomes higher and higher, switching the modulation mode from PFM to PWM would reduce the overall power consumption and improves the overall modulation efficiency. In this embodiment, the voltage output V out  of the voltage output terminal N out  of the frequency-voltage conversion unit  104  may be utilized to judge how fast the input signal frequency f is. For instance, a predetermined frequency f pd  may be defined in advance, and then the modulation mode could be switched from PFM to PWM once the input signal frequency f of the input signal S PFM  exceeds the predetermined frequency f pd . Therefore, a corresponding predetermined voltage V pd  can be derived by equation (9). The comparator  106  is used to compare the voltage output V out  with the predetermined voltage V pd . When the voltage output V out  decreases to a level lower than the predetermined voltage V pd , an output of the comparator  106  has a transition from logic high ‘1’ to logic low ‘0’, thereby instructing associated control and modulation circuits to switch from PFM to PWM. 
     Please note that the above descriptions regarding an embodiment of the present invention are for illustrative purposes only. In practice, any alternative designs and modifications capable of achieving the same objective fall within the scope of the present invention. Please refer to  FIG. 2 , which is a diagram illustrating a frequency detection apparatus  200  according to an embodiment of the present invention. The frequency detection apparatus  200  includes a constant current generator  202 , a frequency-voltage conversion unit  204  and a comparator  106 . The constant current generator  202  is arranged for providing a constant current I total  to a voltage output terminal of the frequency-voltage conversion unit  204 . The frequency-voltage conversion unit  204  generates a voltage output V out  at a voltage output terminal in accordance with the input signal, the inverted input signal and the constant current I total , wherein the inverted input signal is an inverted version of the input signal. The comparator  106  has a first input terminal (+) and a second input terminal (−), wherein the first input terminal (+) is coupled to the voltage output terminal, and the second input terminal (−) is coupled to a predetermined voltage V pd  corresponding to a predetermined frequency f pd . The comparator  106  is utilized to determine whether the input signal frequency f of the input signal exceeds the predetermined frequency f pd . In this embodiment, the circuit architecture of the frequency-voltage conversion unit  204  in the frequency detection apparatus  200  may be different from that of the frequency-voltage conversion unit  104 . More specifically speaking, the spirit of the present invention is obeyed as long as there is a predetermined proportion relationship between the voltage at the output terminal of the frequency-voltage conversion unit  204  and the frequency of the output signal of the frequency-voltage conversion unit  204 . 
     In summary, the disclosed frequency detection apparatus may be used to control the signal processing modules by detecting the frequency variation. For instance, the frequency detection apparatus  100 / 200  can detect the frequency of the input signal to automatically control the switching between PFM and PWM without detecting the voltage load of components other than core components, which is efficient and power saving. To put it another way, the frequency detection apparatus of the present invention prolongs the battery life in portable devices, and has less power consumption and heat dissipation. 
     Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.