Patent Publication Number: US-11641769-B2

Title: Display device having component area

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     The present application claims priority to and the benefit of Korean Patent Application No. 10-2020-0057828, filed on May 14, 2020, in the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. 
     BACKGROUND 
     1. Field 
     Aspects of one or more example embodiments relate to a display device. 
     2. Description of Related Art 
     With the advancement of technology, the various uses and applications for display devices has become more and more diverse. In addition, as display devices have become thinner and lighter, their range of uses has gradually expanded. 
     As display devices are variously utilized, there may be various methods in designing the shape of display devices, and functions that may be combined or associated with display devices have increased. 
     The above information disclosed in this Background section is only for enhancement of understanding of the background and therefore the information discussed in this Background section does not necessarily constitute prior art. 
     SUMMARY 
     Aspects of one or more example embodiments relate to a display device, and for example, to a display panel in which a display area extends to display an image even in a region in which a component is arranged, and a display device including the display panel, the component being an electronic element. 
     Aspects of one or more example embodiments include a display panel in which a display area extends to display an image even in a region in which a component is arranged, and a display device including the display panel, the component being an electronic element. However, it should be understood that example embodiments described herein should be considered in a descriptive sense only and not for limitation of the disclosure. 
     Additional aspects will be set forth in part in the description which follows and, in part, will be more apparent from the description, or may be learned by practice of the presented example embodiments of the disclosure. 
     According to one or more example embodiments, a display device including a main display area, a component area, and a peripheral area, main display elements being arranged in the main display area, auxiliary display elements and a transmission area being arranged in the component area, and the peripheral area being outside the main display area, the display apparatus includes a first pixel circuit arranged in the component area and connected to a first auxiliary display element among the auxiliary display elements, a second pixel circuit arranged in the component area and connected to a second auxiliary display element among the auxiliary display elements, the second pixel circuit neighboring the first pixel circuit in a column direction, and a first initialization voltage line arranged in the component area, extending in a row direction, arranged between the first pixel circuit and the second pixel circuit, and connected to the first pixel circuit and the second pixel circuit, wherein the first pixel circuit and the second pixel circuit are symmetric with respect to the first initialization voltage line. 
     According to some example embodiments, each of the first pixel circuit and the second pixel circuit may include a first thin film transistor including a first semiconductor layer and a first gate electrode, and a second thin film transistor including a second semiconductor layer and a second gate electrode and connected to the first gate electrode and the first initialization voltage line. 
     According to some example embodiments, the first semiconductor layer of the first thin film transistor may include a silicon semiconductor, and the second semiconductor layer of the second thin film transistor may include an oxide semiconductor. 
     According to some example embodiments, the display device may further include a driving voltage line extending in the column direction. 
     According to some example embodiments, the display device may further include an initialization voltage supply line arranged in the peripheral area and connected to the first initialization voltage line. 
     According to some example embodiments, the display device may further include a first vertical voltage line extending in the column direction and connected to the first initialization voltage line. 
     According to some example embodiments, the display device may further include an initialization voltage supply line arranged in the peripheral area and connected to the first vertical voltage line. 
     According to some example embodiments, the display device may further include a second initialization voltage line connected to the first pixel circuit, and a third initialization voltage line connected to the second pixel circuit, wherein the second initialization voltage line and the third initialization voltage line may be symmetric with respect to the first initialization voltage line. 
     According to some example embodiments, a first initialization voltage applied to the first initialization voltage line may be different from a second initialization voltage applied to the second initialization voltage line. 
     According to some example embodiments, the display device may further include a second vertical voltage line extending in the column direction and connected to the second initialization voltage line and the third initialization voltage line. 
     According to one or more example embodiments, a display device includes a substrate including a main display area and a component area, main display elements being arranged in the main display area, and auxiliary display elements and a transmission area being arranged in the component area, a first initialization voltage line arranged in the component area, extending in a first direction, and arranged between a first row and a second row, a second initialization voltage line arranged in the component area, extending in the first direction, and arranged on the first row, and a third initialization voltage line arranged in the component area, extending in the first direction, and arranged on the second row, wherein a first pixel circuit and a second pixel circuit are symmetric with respect to the first initialization voltage line, the first pixel circuit being arranged on the first row, and the second pixel circuit being arranged on the second row and neighboring a second direction intersecting with the first direction. 
     According to some example embodiments, the first pixel circuit may be connected to the first initialization voltage line and the second initialization voltage line, and the second pixel circuit may be connected to the first initialization voltage line and the third initialization voltage line. 
     According to some example embodiments, the display device may further include a driving voltage line connected to the first pixel circuit and the second pixel circuit and extending in the second direction. 
     According to some example embodiments, the driving voltage line may be arranged with an interval of a column in the first direction. 
     According to some example embodiments, the display device may further include a first initialization voltage supply line connected to the first initialization voltage line, and a second initialization voltage supply line connected to the second initialization voltage line and the third initialization voltage line, the first initialization voltage supply line and the second initialization voltage supply line being arranged in the peripheral area. 
     According to some example embodiments, the display device may further include a first vertical voltage line extending in the second direction and connected to the first initialization voltage line. 
     According to some example embodiments, the display device may further include a driving voltage line extending in the second direction, and a second vertical voltage line extending in the second direction and connected to the second initialization voltage line and the third initialization voltage line, wherein the driving voltage line, the first vertical voltage line, and the second vertical voltage line may be alternately arranged with an interval of a column in the first direction. 
     According to some example embodiments, the display device may further include a first initialization voltage supply line connected to the first vertical voltage line, and a second initialization voltage supply line connected to the second vertical voltage line, the first initialization voltage supply line and the second initialization voltage supply line being arranged in the peripheral area outside the main display area. 
     According to some example embodiments, each of the first pixel circuit and the second pixel circuit may include a first thin film transistor including a first semiconductor layer and a first gate electrode, and a second thin film transistor including a second semiconductor layer and a second gate electrode and connected to the first gate electrode and the first initialization voltage line. 
     According to some example embodiments, the first semiconductor layer of the first thin film transistor may include a silicon semiconductor, and the second semiconductor layer of the second thin film transistor may include an oxide semiconductor. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The above and other aspects, features, and characteristics of certain example embodiments according to the present disclosure will be more apparent from the following description taken in conjunction with the accompanying drawings, in which: 
         FIG.  1    is a perspective view of a display device according to some example embodiments; 
         FIG.  2    is a cross-sectional view of a portion of a cross-section of the display device according to some example embodiments; 
         FIG.  3    is a plan view of a display panel according to some example embodiments; 
         FIG.  4    is an arrangement view of a pixel arrangement structure in a main display area according to some example embodiments; 
         FIGS.  5 A and  5 B  are arrangement views of a sub-pixel arrangement structure in a component area according to some example embodiments; 
         FIG.  6    is a cross-sectional view of a portion of the display panel according to some example embodiments and shows a main display area and a component area; 
         FIG.  7    is an equivalent circuit diagram of a pixel circuit driving a sub-pixel according to some example embodiments; 
         FIG.  8    is a view of the arrangement of wirings in the main display area according to some example embodiments; 
         FIG.  9    is a view of the arrangement of wirings in the component area according to some example embodiments; 
         FIG.  10    is a plan view of a pixel circuit of an auxiliary sub-pixel according to some example embodiments; 
         FIG.  11    is a cross-sectional view of the pixel circuit taken along the lines I-I′ and II-II′ of  FIG.  10   ; 
         FIG.  12    is a plan view of a pixel circuit of a main sub-pixel according to some example embodiments; 
         FIG.  13    is a view of the arrangement of wirings in the main display area according to some example embodiments; 
         FIG.  14    is a view of the arrangement of wirings in the component area according to some example embodiments; 
         FIG.  15    is a plan view of the arrangement of pixel circuits of auxiliary sub-pixels according to some example embodiments; and 
         FIG.  16    is a plan view of a display panel according to some example embodiments. 
     
    
    
     DETAILED DESCRIPTION 
     Reference will now be made in more detail to aspects of some example embodiments, which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout. In this regard, the embodiments according to the present disclosure may have different forms and should not be construed as being limited to the descriptions set forth herein. Accordingly, aspects of some example embodiments are merely described below, by referring to the figures, to explain aspects of embodiments according to the present description. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. Throughout the disclosure, the expression “at least one of a, b or c” indicates only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof. 
     As the present disclosure allows for various changes and numerous embodiments, example embodiments will be illustrated in the drawings and described in detail in the written description. Effects and characteristics of the present disclosure, and a method of accomplishing the same will become apparent and more readily appreciated from the following description of the embodiments and the accompanying drawings. However, embodiments according to the present disclosure are not limited to embodiments below and may be implemented in various forms. 
     Hereinafter, aspects of some example embodiments are described in more detail below with reference to the accompany drawings. When description is made with reference to the drawings, like reference numerals are given to like or corresponding elements, and some repeated descriptions thereof may be omitted for brevity. 
     It will be understood that when a layer, region, or element is referred to as being “formed on,” another layer, region, or element, it can be directly or indirectly formed on the other layer, region, or element. That is, for example, intervening layers, regions, or elements may be present. Sizes of elements in the drawings may be exaggerated or reduced for convenience of explanation. In other words, since sizes and thicknesses of elements in the drawings are arbitrarily illustrated for convenience of explanation, the following embodiments are not limited thereto. 
     As used herein, “on a plan view” means that an objective portion is viewed from above, and “on a cross-sectional view” means that a cross-section of an objective portion taken vertically is viewed from a lateral side. As used herein, when it is referred that a first element “overlaps” a second element, the first element is arranged above or below the second element. 
     In the following examples, the x-axis, the y-axis and the z-axis are not limited to three axes of the rectangular coordinate system, and may be interpreted in a broader sense. For example, the x-axis, the y-axis, and the z-axis may be perpendicular to one another, or may represent different directions that are not perpendicular to one another. 
       FIG.  1    is a perspective view of a display device  1  according to some example embodiments. 
     Referring to  FIG.  1   , the display device  1  includes a display area DA and a peripheral area DPA outside the display area DA. The display area DA includes a component area CA and a main display area MDA, the main display area MDA at least partially surrounding the component area CA. That is, the component area CA and the main display area MDA may display an image individually or in cooperation with each other. The peripheral area DPA may include a non-display area in which display elements are not arranged. The display area DA may be entirely surrounded by the peripheral area DPA. 
     It is shown in  FIG.  1    that one component area CA is arranged inside the main display area MDA. According to some example embodiments, the display device  1  may include two or more component areas CA. The shapes, sizes, and locations of the plurality of component areas CA may be different from each other, and may be any suitable shape size, or location according to the design of the display device  1 . When viewed in a plan view (e.g., a view in a direction perpendicular (or approximately perpendicular) or normal with respect to the top surface (e.g., a plane of the display surface)) of the display device  1 , the component area CA may have various shapes such as a circle, an ellipse, a polygon including a quadrangle, a hexagon, and an octagon, a star shape, or a diamond shape. Though it is shown in  FIG.  1    that, in a plan view (e.g., when viewed in a direction perpendicular (approximately perpendicular) or normal with respect to the top surface (e.g., a plane of the display surface)) of the display device  1 , the component area CA is arranged at the top center (a+y direction) of the main display area MDA having an approximately quadrangular shape, the component area CA may be arranged in any suitable location according to the design of the display device  1 , for example, at one side of the main display area MDA, which has a quadrangular shape, for example, on the top right side or the top left side. 
     The display device  1  may display an image by using a plurality of main sub-pixels Pm and a plurality of auxiliary sub-pixels Pa, the plurality of main sub-pixels Pm being arranged in the main display area MDA, and the plurality of auxiliary sub-pixels Pa being arranged in the component area CA. 
     In the component area CA, as described below with reference to  FIG.  2   , a component  40 , which is an electronic element, may be arranged below a display panel  10  to correspond to the component area CA. The component  40  may include a camera that uses infrared or visible light, etc. and include an imaging element. Alternatively, the component  40  may include a solar battery, a flash, an illuminance sensor, a proximity sensor, and an iris sensor. Alternatively, the component  40  may have a function of receiving sound. To minimize or reduce limitations on the function of the component  40 , the component area CA may include a transmission area TA through which light and/or sound output from the component  40  to the outside or progressing toward the component  40  from the outside may pass. In the display panel and the display device including the display panel according to some example embodiments, when light is allowed to pass through the component area CA, a light transmittance may be 10% or more, more preferably, 40% or more, 25% or more, 50% or more, 85% or more, or 90% or more. 
     The plurality of auxiliary sub-pixels Pa may be arranged in the component area CA. The plurality of auxiliary sub-pixels Pa may display an image by emitting light. An image displayed in the component area CA includes an auxiliary image and may have a resolution less than an image displayed in the main display area MDA. That is, the component area CA includes the transmission area TA through which light and sound may pass. In the case where sub-pixels are not arranged in the transmission area TA, the number of auxiliary sub-pixels Pa that may be arranged per unit area of the component area CA may be less than the number of main sub-pixels Pm arranged per unit area of the main display area MDA. 
       FIG.  2    is a cross-sectional view of a portion of a cross-section of the display device  1  according to some example embodiments. 
     Referring to  FIG.  2   , the display device  1  may include the display panel  10  and the component  40  overlapping the display panel  10 . According to some example embodiments, a cover window may be further arranged on the display panel  10 , the cover window protecting the display panel  10 . 
     The display panel  10  includes the component area CA and the main display area MDA, the component area CA including a region overlapping the component  40 , and a main image being displayed in the main display area MDA. The display panel  10  may include a substrate  100 , a display layer DISL, a touchscreen layer TSL, an optical functional layer OFL on the substrate  100 , and a panel protection member PB, the panel protection member PB being under the substrate  100 . 
     The display layer DISL may include a circuit layer PCL, a display element layer EDL, and a sealing member ENCM such as a thin-film encapsulation layer TFEL or a sealing substrate. The circuit layer PCL includes a plurality of thin film transistors TFT and TFT′, and the display element layer EDL includes a plurality of light-emitting diodes ED and ED′, which are display elements. Insulating layers IL and IL′ may be between the substrate  100  and the display layer DISL, and inside the display layer DISL. 
     The substrate  100  may include an insulating material such as glass, quartz, and/or a polymer resin. The substrate  100  may include a rigid substrate or may be a flexible substrate that is bendable, foldable, and/or rollable. 
     A main sub-pixel Pm including a main light-emitting diode ED and a main thin film transistor TFT being connected to the main sub-pixel Pm may be arranged in the main display area MDA of the display panel  10 . An auxiliary sub-pixel Pa including an auxiliary light-emitting diode ED′ and an auxiliary thin film transistor TFT′ being connected to the auxiliary sub-pixel Pa may be arranged in the component area CA. A region in which auxiliary sub-pixels Pa are arranged of the component area CA may be referred to as a sub-pixel area ADA. 
     In addition, the transmission area TA may be arranged in the component area CA, display elements not being arranged in the transmission area TA to enable light or signals to pass through the transmission area TA without being blocked by non-transmissive elements or components. That is, the transmission area TA may include a region through which light and/or a signal emitted from the component  40  or light and/or a signal incident to the component  40  may pass through to the component or from the component, the component  40  being arranged to correspond to the component area CA. The sub-pixel area ADA and the transmission area TA may be alternately arranged in the component area CA. Thus, as illustrated in  FIG.  2   , the density of thin film transistors, light-emitting diodes, and/or other electrical components that may be non-transmissive of signals or light, may be lower in the component area CA than the main display area MDA, in order to accommodate the transmission area TA. 
     A bottom metal layer BML may be arranged in the component area CA. The bottom metal layer BML may be arranged to correspond to below the auxiliary thin film transistor TFT′. For example, the bottom metal layer BML may be between the auxiliary thin film transistor TFT′ and the substrate  100 . The bottom metal layer BML may block external light from reaching the auxiliary thin film transistor TFT′. According to some example embodiments, a constant voltage or signal may be applied to the bottom metal layer BML. 
     The display element layer EDL may be covered by the thin-film encapsulation layer TFEL or a sealing substrate. According to some example embodiments, the thin-film encapsulation layer TFEL may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. According to some example embodiments, the thin-film encapsulation layer TFEL may include first and second inorganic encapsulation layers  131  and  133  and an organic encapsulation layer  132  therebetween. 
     The first and second inorganic encapsulation layers  131  and  133  may include at least one inorganic insulating material among aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, or silicon oxynitride. The organic encapsulation layer  132  may include a polymer-based material. The polymer-based material may include an acryl-based resin, an epoxy-based resin, polyimide, and polyethylene. 
     In the case where the display element layer EDL is sealed by the sealing substrate, the sealing substrate may face the substrate  100  with the display element layer EDL therebetween. There may be a gap between the sealing substrate and the display element layer EDL. The sealing substrate may include glass. Sealant may be between the substrate  100  and the sealing substrate, the sealant including frit and being arranged in the peripheral area DPA. The sealant arranged in the peripheral area DPA may surround the display area DA and prevent or reduce instances of moisture or other contaminants penetrating into the display area DA through a lateral surface of the display area DA. 
     The touchscreen layer TSL may obtain coordinate information corresponding to an external input, for example, a touch event. The touchscreen layer TSL may include a touch electrode and touch wirings, the touch wirings being connected to the touch electrode. The touchscreen layer TSL may detect an external input (e.g., from a user&#39;s finger, a stylus, and the like) by using a self-capacitive method or a mutual capacitive method. 
     The touchscreen layer TSL may be formed on the thin-film encapsulation layer TFEL. Alternatively, the touchscreen layer TSL may be separately formed on the touchscreen and then coupled to the thin-film encapsulation layer TFEL through an adhesive layer such as an optically clear adhesive (OCA). According to some example embodiments, the touchscreen layer TSL may be directly formed right on the thin-film encapsulation layer TFEL. In this case, the adhesive layer may not be arranged between the touchscreen layer TSL and the thin-film encapsulation layer TFEL. 
     The optical functional layer OFL may include a reflection prevention layer. The reflection prevention layer may reduce reflectivity of light (external light) incident toward the display apparatus  1  from the outside. 
     According to some example embodiments, the optical functional layer OFL may include a polarizing film. The optical functional layer OFL may include an opening OFL_OP corresponding to the transmission area TA. Accordingly, a light transmittance of the transmission area TA may be remarkably improved. A transparent material such as an optically clear resin (OCR) may fill the opening OFL_OP. 
     According to some example embodiments, the optical functional layer OFL may include a filter plate including a black matrix and color filters. 
     According to some example embodiments, a cover window may be arranged on the display panel  10  to protect the display panel  10 . The optical functional layer OFL may be attached on the cover window by using an optically clear adhesive or attached on the touchscreen layer TSL by using an optically clear adhesive. 
     The panel protection member PB may be attached to the bottom of the substrate  100  to support and protect the substrate  100 . The panel protection member PB may include an opening PB_OP corresponding to the component area CA. Because the opening PB_OP is formed in the panel protection member PB at a region corresponding to the component area CA, according to some example embodiments, (such that a portion of the panel protection member PB is removed or not present at the component area CA), a light transmittance of the component area CA may be relatively improved (compared to embodiments in which the panel protection member PB is present at the component area CA). The panel protection member PB may include, for example, polyethylene terephthalate (PET) or polyimide (PI). 
     The area of the component area CA may be greater than an area in which the component  40  is arranged. Accordingly, the area of the opening PB_OP formed in the panel protection member PB may not coincide with the area of the component area CA. 
     In addition, a plurality of components  40  may be arranged in the component area CA (or in multiple component areas CA). The functions of the plurality of components  40  may be different from each other. For example, in embodiments in which a plurality of components  40  are arranged in the component area CA (or in multiple component areas CA) the plurality of components  40  may include at least two of a camera (an imaging element), a solar battery, a flash, a proximity sensor, an illuminance sensor, and/or an iris sensor, or any other suitable component configured to emit or receive external signals. 
       FIG.  3    is a plan view of the display panel  10  according to some example embodiments. 
     Referring to  FIG.  3   , various elements constituting the display panel  10  are arranged on the substrate  100 . The substrate  100  includes the display area DA and the peripheral area DPA surrounding (e.g., outside a footprint of) the display area DA. The display area DA includes the main display area MDA and the component area CA, a main image being displayed in the main display area MDA, an auxiliary image being displayed in the component area CA, and the component area CA including the transmission area TA. An auxiliary image may constitute one entire image in cooperation with a main image (e.g., an image that corresponds to a portion of the main image, for example, having a relatively lower resolution at the location of the component area CA) or include an image independent of the main image. 
     A plurality of main sub-pixels Pm are arranged in the main display area MDA. Each of the main sub-pixels Pm may include a display element such as an organic light-emitting diode OLED. Each of the main sub-pixels Pm may emit, for example, red, green, blue, or white light. The main display area MDA may be covered by the sealing member and protected from external air or moisture, etc. 
     The component area CA may be arranged on one side of the main display area MDA as described above, or arranged inside the display area DA and surrounded by the main display area MDA. The plurality of auxiliary sub-pixels Pa are arranged in the component area CA. Each of the plurality of auxiliary sub-pixels Pa may include a display element such as an organic light-emitting diode OLED. Each of the auxiliary sub-pixels Pa may emit, for example, red, green, blue, or white light. The component area CA may be covered by the sealing member and protected from external air or moisture, etc. 
     The component area CA may include the transmission area TA. The transmission area TA may surround the plurality of auxiliary sub-pixels Pa. Alternatively, the transmission area TA may be arranged in a lattice configuration with the plurality of auxiliary sub-pixels Pa. 
     Because the component area CA includes the transmission area TA, the resolution of the component area CA may be less than the resolution of the main display area MDA. For example, the resolution of the component area CA may be about ½, ⅜, ⅓, ¼, 2/9, ⅛, 1/9, 1/16, etc. of the resolution of the main display area MDA. For example, the resolution of the main display area MDA may be about 400 ppi and the resolution of the component area CA may be about 200 ppi or about 100 ppi. 
     Each of pixel circuits configured to drive the main and auxiliary sub-pixels Pm and Pa may be electrically connected to outer circuits arranged in the peripheral area DPA. A first scan driving circuit SDRV 1 , a second scan driving circuit SDRV 2 , a terminal portion PAD, a driving voltage supply line  11 , a common voltage supply line  13 , and an initialization voltage supply line  15  may be arranged in the peripheral area DPA. 
     The first scan driving circuit SDRV 1  may apply a scan signal to each of the pixel circuits configured to drive the main and auxiliary sub-pixels Pm and Pa through a scan line SL. The first scan driving circuit SDRV 1  may apply an emission control signal to each pixel circuit through an emission control line EL. The second scan driving circuit SDRV 2  may be arranged on an opposite side of the first scan driving circuit SDRV 1  with the main display area MDA therebetween and may be approximately parallel to the first scan driving circuit SDRV 1 . 
     Some of the pixel circuits of the main sub-pixels Pm in the main display area MDA may be electrically connected to the first scan driving circuit SDRV 1 , and the rest of the pixel circuits may be electrically connected to the second scan driving circuit SDRV 2 . Some of the pixel circuits of the auxiliary sub-pixels Pa in the component area CA may be electrically connected to the first scan driving circuit SDRV 1 , and the rest of the pixel circuits may be electrically connected to the second scan driving circuit SDRV 2 . According to some example embodiments, the second scan driving circuit SDRV 2  may be omitted. 
     The terminal portion PAD may be arranged on one side of the substrate  100 . The terminal portion PAD may be exposed by not being covered by an insulating layer and may be connected to a display circuit board  30 . A display driver  32  may be arranged on the display circuit board  30 . 
     The display driver  32  may generate a control signal transferred to the first scan driving circuit SDRV 1  and the second scan driving circuit SDRV 2 . The display driver  32  generates a data signal. The generated data signal may be transferred to the pixel circuits of the main and auxiliary sub-pixels Pm and Pa through a fan-out line FW and the data line DL connected to the fan-out line FW. 
     The display driver  32  may supply a driving voltage ELVDD to the driving voltage supply line  11  and supply a common voltage ELVSS to the common voltage supply line  13 . The driving voltage ELVDD may be applied to the pixel circuits of the main and auxiliary sub-pixels Pm and Pa through the driving voltage line PL connected to the driving voltage supply line  11 , and the common voltage ELVSS may be applied to an opposite electrode of the display elements through the common voltage supply line  13 . The display driver  32  may supply an initialization voltage to the initialization voltage supply line  15 . The initialization voltage may be applied to the pixel circuits of the main and auxiliary sub-pixels Pm and Pa through an initialization voltage line VL. 
     The driving voltage supply line  11  may be connected to the terminal portion PAD and may extend in an x-direction from below the main display area MDA. The common voltage supply line  13  may be connected to the terminal portion PAD and have a loop shape having one open side to partially surround the main display area MDA. 
     The initialization voltage supply line  15  may include a first initialization voltage supply line  15   a  and a second initialization voltage supply line  15   b . The first initialization voltage supply line  15   a  and the second initialization voltage supply line  15   b  may be connected to the terminal portion PAD and may extend in a y-direction in a shape at least surrounding the left and right of the main display area MDA. The first initialization voltage supply line  15   a  and the second initialization voltage supply line  15   b  may be apart from each other with the display area DA therebetween. 
     As described below with reference to  FIGS.  8  to  10   , the initialization voltage line VL may include a first initialization voltage line VL 1  and a second initialization voltage line VL 2 . In this case, an initialization voltage supply line connected to the first initialization voltage line VL 1 , and an initialization voltage supply line connected to the second initialization voltage line VL 2  may be provided separately. The initialization voltage supply line connected to the first initialization voltage line VL 1 , and the initialization voltage supply line connected to the second initialization voltage line VL 2  may respectively include the first initialization voltage supply line  15   a  and the second initialization voltage supply line  15   b.    
       FIG.  4    is an arrangement view of a pixel arrangement structure in the main display area MDA according to some example embodiments. 
     Referring to  FIG.  4   , a plurality of main sub-pixels Pm may be arranged in the main display area MDA. In the present specification, a sub-pixel is a minimum unit configured to display an image and denotes an emission area. In the case where an organic light-emitting diode is employed as a display element, an emission area of a sub-pixel may be defined by an emission layer or an opening of a pixel-defining layer. This is described in more detail below. 
     The main display area MDA of  FIG.  4    may be divided into circuit areas PCA in which a pixel circuit connected to a main sub-pixel Pm is arranged. 
     The main sub-pixels Pm may include a red sub-pixel Pr, a green sub-pixel Pg, and a blue sub-pixel Pb. A red sub-pixel Pr, a green sub-pixel Pg, and a blue sub-pixel Pb may respectively implement red color, green color, and blue color. 
     Red sub-pixels Pr and blue sub-pixels Pb are alternately arranged on a first sub-row  1 SN of each of rows  1 N,  2 N, . . . , N. Green sub-pixels Pg are apart from each other on a second sub-row  2 SN that neighbors the first sub-row  1 SN. Such a pixel arrangement may be repeated up to an N-th row. In this case, the blue sub-pixel Pb and the red sub-pixel Pr may be greater than the green sub-pixel Pg. The red sub-pixels Pr and the blue sub-pixels Pb on the first sub-row  1 SN and the green sub-pixels Pg on the second sub-row  2 SN may be alternately arranged with each other. Therefore, red sub-pixels Pr and blue sub-pixels Pb are alternately arranged on a first column  1 M, and green sub-pixels Pg are apart from each other on a neighboring second column  2 M. Blue sub-pixels Pb and red sub-pixels Pr are alternately arranged on a neighboring third column  3 M, and green sub-pixels Pg are apart from each other on a neighboring fourth column  4 M. Such a pixel arrangement may be repeated up to an M-th column. 
     Such a pixel arrangement structure may be expressed differently, in which: red sub-pixels Pr are respectively arranged on first and third vertexes among the vertexes of a virtual quadrangle VS with a green sub-pixel Pg centered at the center of the quadrangle, and blue sub-pixels Pb are respectively arranged on second and fourth vertexes, which are the rest of the vertexes. In this case, the virtual quadrangle VS may be variously modified to a rectangle, a rhombus, a square, etc. 
     Such a pixel arrangement structure is referred to as a pentile matrix structure or a pentile structure. The pentile matrix structure may implement a relatively high resolution image with a relatively small number of pixels by applying rendering that expresses colors by sharing neighboring pixels. 
     Though it is shown in  FIG.  4    that a plurality of main sub-pixels Pm are arranged in a pentile structure, the embodiments according to the present disclosure are not limited thereto. For example, a plurality of main sub-pixels Pm may be arranged in various configurations such as a stripe structure, a mosaic arrangement structure, a delta arrangement structure, etc., or any other suitable pixel arrangement or structure according to the design of the display device  1 . 
       FIGS.  5 A and  5 B  are arrangement views of a sub-pixel arrangement structure in the component area CA according to some example embodiments. 
     Referring to  FIG.  5 A , a plurality of auxiliary sub-pixels Pa may be arranged in the component area CA. Each of the plurality of auxiliary sub-pixels Pa may emit red, green, blue, or white light. 
     The component area CA may include the sub-pixel area ADA and the transmission area TA, a pixel group PG being arranged in the sub-pixel area ADA, and the pixel group PG including at least one auxiliary sub-pixel Pa. The sub-pixel areas ADA and the transmission areas TA are alternately arranged in the x-direction and the y-direction and arranged, for example, in a lattice configuration. In this case, the component area CA may include a plurality of sub-pixel areas ADA and a plurality of transmission areas TA. The sub-pixel area ADA may be divided into circuit areas PCA in which a pixel circuit connected to an auxiliary sub-pixel Pa is arranged. 
     The pixel group PG may be defined as a sub-pixel aggregation in which a plurality of auxiliary sub-pixels Pa are bound on a preset basis. For example, as shown in  FIG.  5 A , a pixel group PG may include eight auxiliary sub-pixels Pa arranged in a pentile structure. That is, a pixel group PG may include two red sub-pixels Pr, four green sub-pixels Pg, and two blue sub-pixels Pb. 
     A basic unit U may be repeatedly arranged in the component area CA in the x-direction and the y-direction, a preset number of pixel groups PG and a preset number of transmission areas TA being bound in the basic unit U. In  FIG.  5 A , the basic unit U may have a shape in which two pixel groups PG and two transmission areas TA are bound in a quadrangle, the two areas TA surrounding the two pixel groups PG. The basic unit U includes divided shapes that are repeated and does not mean disconnection of the configuration. 
     As shown in  FIG.  4   , a corresponding unit U′ may be set in the main display area MDA, the corresponding unit U′ having the same area as the basic unit U. In this case, the number of main sub-pixels Pm included in the corresponding unit U′ may be greater than the number of auxiliary sub-pixels Pa included in the basic unit U. 
     Similar to the arrangement of the main sub-pixels Pm in the main display area MDA, four auxiliary sub-pixels Pa may be respectively arranged at the vertexes of a virtual quadrangle VS′. The resolution of the component area CA is about ½ of the resolution of the main display area MDA. The pixel arrangement structure of the component area CA is referred to as a ½ pentile structure. The number of auxiliary sub-pixels Pa or the arrangement structure of the auxiliary sub-pixels Pa included in the pixel group PG may be modified depending on the resolution of the component area CA. 
     Referring to  FIG.  5 B , the pixel arrangement structure of the component area CA may include a ¼ pentile structure. According to some example embodiments, the pixel group PG includes eight auxiliary sub-pixels Pa arranged in a pentile structure, but the basic unit U may include only one pixel group PG. The rest of the regions of the basic unit U may include the transmission area TA. Therefore, the number of auxiliary sub-pixels Pa and the number of main sub-pixels Pm per same area may be provided at a ratio of 1:4. In this case, one pixel group PG may be surrounded by the transmission area TA. 
     Though it is shown in  FIGS.  5 A and  5 B  that a plurality of auxiliary sub-pixels Pa are arranged in a pentile structure, the embodiments according to the present disclosure are not limited thereto. For example, a plurality of auxiliary sub-pixels Pa may be arranged in various configurations such as a stripe structure, a mosaic arrangement structure, a delta arrangement structure, etc. 
     In addition, though it is shown in  FIGS.  5 A and  5 B  that the size of the auxiliary sub-pixel Pa is the same as the size of the main sub-pixel Pm of  FIG.  4   , the embodiments according to the present disclosure are not limited thereto. The size of the auxiliary sub-pixel Pa may be greater than the size of the main sub-pixel Pm representing the same color. For example, the size of a blue sub-pixel Pb of an auxiliary sub-pixel Pa, may be greater than the size of a blue sub-pixel Pb of a main sub-pixel Pm. A difference in the size may be designed by taking into account a difference in brightness and/or resolution of the component area CA and the main display area MDA. 
       FIG.  6    is a cross-sectional view of a portion of the display panel  10  according to some example embodiments and shows the main display area MDA and the component area CA. 
     Referring to  FIG.  6   , the display panel  10  includes the main display area MDA and the component area CA. Main sub-pixels Pm are arranged in the main display area MDA, and auxiliary sub-pixels Pa and the transmission areas TA are arranged in the component area CA. A main pixel circuit PC and a main organic light-emitting diode OLED, which is a display element, may be arranged in the main display area MDA, the main pixel circuit PC including a main thin film transistor TFT and a main capacitor Cst, and the main light-emitting diode OLED being connected to the main pixel circuit PC. An auxiliary pixel circuit PC′ and an auxiliary organic light-emitting diode OLED′, which is a display element, may be arranged in the component area CA, the auxiliary pixel circuit PC′ including an auxiliary thin film transistor TFT′ and an auxiliary capacitor Cst′, and the auxiliary organic light-emitting diode OLED′ being connected to the auxiliary pixel circuit PC′. 
     Though an organic light-emitting diode is employed as a display element as an example in the example embodiments, an inorganic light-emitting diode or a quantum-dot light-emitting diode may be employed as a display element according to some example embodiments. 
     A structure in which elements of the display panel  10  are stacked is described below. The display panel  10  may include the substrate  100 , a buffer layer  111 , the circuit layer PCL, and the display element layer EDL. As shown in  FIG.  2   , the sealing member ENCM and the optical functional layer OFL may be further stacked on the display element layer EDL. 
     The substrate  100  may include an insulating material such as glass, quartz, and a polymer resin. The substrate  100  may include a rigid substrate or a flexible substrate that is bendable, foldable, and rollable. 
     The buffer layer  111  may be arranged on the substrate  100  to reduce or block the penetration of foreign substances or external air from below the substrate  100  and may provide a flat surface on the substrate  100 . The buffer layer  111  may include an inorganic material such as oxide or nitride, an organic material, or an organic/inorganic composite material and include a single layer or a multi-layer including an inorganic material and an organic material. A barrier layer may be further arranged between the substrate  100  and the buffer layer  111 , the barrier layer blocking the penetration of external air. According to some example embodiments, the buffer layer  111  may include silicon oxide (SiO x ) or silicon nitride (SiN x ). The buffer layer  111  may have a structure in which a first buffer layer  111   a  and a second buffer layer  111   b  are stacked. 
     A bottom metal layer BML may be between the first buffer layer  111   a  and the second buffer layer  111   b  in the component area CA. According to some example embodiments, the bottom metal layer BML may be between the substrate  100  and the first buffer layer  111   a . The bottom metal layer BML may be arranged below the auxiliary pixel circuit PC′ to prevent or reduce the characteristic of the auxiliary thin film transistor TFT′ being deteriorated by light emitted from a component, etc. In addition, the bottom metal layer BML may prevent or reduce light emitted from a component or received by the component being diffracted through a narrow gap between wirings connected to the auxiliary pixel circuit PC′. According to some example embodiments, there is no bottom metal layer BML in the transmission area TA. 
     In addition, the bottom metal layer BML may be connected to a bias line BW on a different layer through a contact hole. The bottom metal layer BML may receive a constant voltage or signal from the bias line BW. For example, the bottom metal layer BML may receive a bias voltage. A difference in the brightness of the component area CA and the main display area MDA depending on a process distribution may be adjusted by adjusting a bias voltage. In addition, as the bias voltage is applied to the bottom metal layer BML, the auxiliary thin film transistor TFT′ may be embodied as a double-gate transistor including two gate electrodes facing each other with a semiconductor layer therebetween and thus the characteristic of the auxiliary thin film transistor TFT′ may be adjusted. 
     The bottom metal layer BML may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chrome (Cr), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and/or copper (Cu). The bottom metal layer BML may include a single layer or a multi-layer including the above materials. 
     The pixel circuit layer PCL may be arranged on the buffer layer  111  and may include the pixel circuits, that is, the main and auxiliary pixel circuits PC and PC′, a first gate insulating layer  112 , a second gate insulating layer  113 , an interlayer insulating layer  115 , and a planarization layer  117 . 
     The main thin film transistor TFT and the auxiliary thin film transistor TFT′ may be arranged over the buffer layer  111 . The main thin film transistor TFT includes a first semiconductor layer A 1 , a first gate electrode G 1 , a first source electrode S 1 , and a first drain electrode D 1 . The auxiliary thin film transistor TFT′ may include a second semiconductor layer A 2 , a second gate electrode G 2 , a second source electrode S 2 , and a second drain electrode D 2 . The main thin film transistor TFT may be connected to the main organic light-emitting diode OLED to drive the organic light-emitting diode OLED. The auxiliary thin film transistor TFT′ may be connected to the auxiliary organic light-emitting diode OLED′ to drive the auxiliary organic light-emitting diode OLED′. 
     The first semiconductor layer A 1  and the second semiconductor layer A 2  may be arranged on the buffer layer  111  and may include polycrystalline silicon. According to some example embodiments, the first semiconductor layer A 1  and the second semiconductor layer A 2  may include amorphous silicon. According to some example embodiments, the first semiconductor layer A 1  and the second semiconductor layer A 2  may include an oxide of at least one of indium (In), gallium (Ga), stannum (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), or zinc (Zn). Each of the first semiconductor layer A 1  and the second semiconductor layer A 2  may include a channel region, a source region, and a drain region, the source region and the drain region being doped with impurities. 
     The second semiconductor layer A 2  may overlap the bottom metal layer BML with the second buffer layer  111   b  therebetween. According to some example embodiments, the width of the second semiconductor layer A 2  may be less than the width of the bottom metal layer BML and accordingly, in a direction perpendicular to the substrate  100 , the second semiconductor layer A 2  may entirely overlap the bottom metal layer BML. 
     The first gate insulating layer  112  may cover the first semiconductor layer A 1  and the second semiconductor layer A 2 . The first gate insulating layer  112  may include an inorganic insulating material such as silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), tantalum oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ), or zinc oxide (ZnO 2 ). The first gate insulating layer  112  may include a single layer or a multi-layer including the above inorganic insulating material. 
     The first gate electrode G 1  and the second gate electrode G 2  are arranged on the first gate insulating layer  112  to respectively overlap the first semiconductor layer A 1  and the second semiconductor layer A 2 . The first gate electrode G 1  and the second gate electrode G 2  may include at least one of molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti) and include a single layer or a multi-layer. For example, the first gate electrode G 1  and the second gate electrode G 2  may include a single Mo layer. 
     The second gate insulating layer  113  may cover the first gate electrode G 1  and the second gate electrode G 2 . The second gate insulating layer  113  may include an inorganic insulating material such as silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), tantalum oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ), or zinc oxide (ZnO 2 ). The second gate insulating layer  113  may include a single layer or a multi-layer including the above inorganic insulating material. 
     A first top electrode CE 2  of the main capacitor Cst and a second top electrode CE 2 ′ of an auxiliary capacitor Cst′ may be arranged on the second gate insulating layer  113 . 
     The first top electrode CE 2  may overlap the first gate electrode G 1  therebelow in the main display area MDA. The first gate electrode G 1  and the first top electrode CE 2  overlapping each other with the second gate insulating layer  113  therebetween may constitute the main capacitor Cst. The first gate electrode G 1  may serve as a first bottom electrode CE 1  of the main capacitor Cst. 
     The second top electrode CE 2 ′ may overlap the second gate electrode G 2  therebelow in the component area CA. The second gate electrode G 2  and the second top electrode CE 2 ′ overlapping each other with the second gate insulating layer  113  therebetween may constitute the auxiliary capacitor Cst′. The second gate electrode G 2  may serve as a second bottom electrode CE 1 ′ of the auxiliary capacitor Cst′. 
     The first top electrode CE 2  and the second top electrode CE 2 ′ may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chrome (Cr), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and/or copper (Cu) and include a single layer or a multi-layer including the above materials. 
     An interlayer insulating layer  114  may cover the first top electrode CE 2  and the second top electrode CE 2 ′. The interlayer insulating layer  114  may include silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), tantalum oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ), or zinc oxide (ZnO 2 ). The interlayer insulating layer  114  may include a single layer or a multi-layer including the above inorganic insulating material. 
     Assuming that the first gate insulating layer  112 , the second gate insulating layer  113 , and the interlayer insulating layer  114  are collectively referred to as an inorganic insulating layer IL, the inorganic insulating layer IL may include a first hole H 1  corresponding to the transmission area TA. The first hole H 1  may expose a portion of the top surface of the buffer layer  111  or the substrate  100 . The first hole H 1  may include an opening of the first gate insulating layer  112 , an opening of the second gate insulating layer  113 , and an opening of the interlayer insulating layer  114  each corresponding to the transmission area TA and overlapping one another. These openings may be respectively formed through separate processes or simultaneously formed through the same process. In the case where these openings are formed through separate processes, the inner surface of the first hole H 1  may not be smooth and may have a stair-like step difference. 
     According to some example embodiments, the inorganic insulating layer IL may include a groove, not the first hole H 1  exposing the buffer layer  111 . Alternatively, the inorganic insulating layer IL may not have the first hole H 1  or the groove corresponding to the transmission area TA. Because the inorganic insulating layer IL includes an inorganic insulating material having an excellent light transmittance, even though the inorganic insulating layer IL does not include a hole or groove corresponding to the transmission area TA, the component  40  (see  FIG.  2   ) may transmit/receive a sufficient amount of light. 
     The first and second source electrodes S 1  and S 2  and the first and second drain electrodes D 1  and D 2  may be arranged on the interlayer insulating layer  114 . The first and second source electrodes S 1  and S 2  and the first and second drain electrodes D 1  and D 2  may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti) and include a single layer or a multi-layer including the above materials. According to some example embodiments, the first and second source electrodes S 1  and S 2  and the first and second drain electrodes D 1  and D 2  may have a multi-layered structure of Ti/Al/Ti. 
     The planarization layer  117  may be arranged to cover the first and second source electrodes S 1  and S 2  and the first and second drain electrodes D 1  and D 2 . The planarization layer  117  may have a flat top surface such that a first pixel electrode  121  and a second pixel electrode  121 ′ arranged on the planarization layer  117  are formed flat. 
     The planarization layer  117  may include an organic material or an inorganic material and include a single-layered structure or a multi-layered structure. The planarization layer  117  may include a first planarization layer  117   a  and a second planarization layer  117   b . Accordingly, because a conductive pattern such as wirings may be formed between the first planarization layer  117   a  and the second planarization layer  117   b , such a structure is advantageous in high integration. 
     The planarization layer  117  may include a general-purpose polymer such asbenzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), polymethylmethacrylate (PMMA) or polystyrene (PS), polymer derivatives having a phenol-based group, an acryl-based polymer, an imide-based polymer, an aryl ether-based polymer, an amide-based polymer, a fluorine-based polymer, a p-xylene-based polymer, or a vinyl alcohol-based polymer. The planarization layer  117  may include an inorganic insulating material such as silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), tantalum oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ), or zinc oxide (ZnO 2 ). To provide a flat top surface while the planarization layer  117  is formed, after the planarization layer  117  is formed, chemical mechanical polishing may be performed on a surface of the planarization layer  117 . 
     As shown in  FIG.  6   , the bias line BW may be arranged on the inorganic insulating layer IL. According to some example embodiments, the bias line BW may be between the first planarization layer  117   a  and the second planarization layer  117   b . The bias line BW may be electrically connected to the bottom metal layer BML through a contact hole, the bottom metal layer BML being arranged in the component area CA. 
     The first planarization layer  117   a  may be arranged to cover the pixel circuits, that is, the main and auxiliary pixel circuits PC and PC′. The second planarization layer  117   b  may be arranged on the first planarization layer  117   a  and may have a flat top surface such that the first and second pixel electrodes  121  and  121 ′ are formed flat. 
     The main and auxiliary organic light-emitting diodes OLED and OLED′ are arranged on the second planarization layer  117   b . The first and second pixel electrodes  121  and  121 ′ of the main and auxiliary organic light-emitting diodes OLED and OLED′ may be respectively connected to the pixel circuits, that is, the main and auxiliary pixel circuits PC and PC′ through connection metals CM and CM′ on the first planarization layer  117   a.    
     The connection metals CM and CM′ may be between the first planarization layer  117   a  and the second planarization layer  117   b . The connection metals CM and CM′ may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti) and include a single layer or a multi-layer including the above materials. For example, the connection metals CM and CM′ may have a multi-layered structure of Ti/Al/Ti. 
     The planarization layer  117  may include a second hole H 2  corresponding to the transmission area TA. The second hole H 2  may overlap the first hole H 1 . It is shown in  FIG.  6    that the second hole H 2  is larger than the first hole H 1 . According to some example embodiments, the planarization layer  117  may cover the edges of the first hole H 1  of the inorganic insulating layer IL and accordingly, the area of the second hole H 2  may be less than the area of the first hole H 1 . 
     The planarization layer  117  includes a via hole exposing one of the first source electrode S 1  and the first drain electrode D 1  of the main thin film transistor TFT. And the first pixel electrode  121  may be electrically connected to the main thin film transistor TFT by contacting the first source electrode S 1  or the first drain electrode D 1  through the contact hole. In addition, the planarization layer  117  includes a via hole exposing one of the second source electrode S 2  and the second drain electrode D 2  of the auxiliary thin film transistor TFT′. And the second pixel electrode  121 ′ may be electrically connected to the auxiliary thin film transistor TFT′ by contacting the second source electrode S 2  or the second drain electrode D 2  through the contact hole. 
     The first pixel electrode  121  and the second pixel electrode  121 ′ may include a conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In 2 O 3 ), indium gallium oxide (IGO), or aluminum zinc oxide (AZO). The first pixel electrode  121  and the second pixel electrode  121 ′ may include a reflective layer including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chrome (Cr), or compound thereof. For example, the first pixel electrode  121  and the second pixel electrode  121 ′ may include a structure including ITO, IZO, ZnO, or In 2 O 3  on/under the reflective layer. In this case, the first pixel electrode  121  and the second pixel electrode  121 ′ may have a stacked structure of ITO/Ag/ITO. 
     A pixel-defining layer  119  covers the edges of the first pixel electrode  121  and the second pixel electrode  121 ′ on the planarization layer  117  and may include a first opening OP 1  and a second opening OP 2  respectively exposing the portions of the first pixel electrode  121  and the second pixel electrode  121 ′. Emission areas of the main and auxiliary organic light-emitting diodes OLED and OLED′, that is, the sizes and shapes of the main and auxiliary sub-pixels Pm and Pa, are defined by the first opening OP 1  and the second opening OP 2 . 
     The pixel-defining layer  119  may prevent or reduce instances of an arc, etc. from occurring at the edges of the first pixel electrode  121  and the second pixel electrode  121 ′ by increasing a distance between the edges of the first pixel electrode  121  and the second pixel electrode  121 ′ and an opposite electrode  123  over the first pixel electrode  121  and the second pixel electrode  121 ′. The pixel-defining layer  119  may include an organic insulating material such as polyimide, polyamide, an acrylic resin, HMDSO, and a phenolic resin and be formed by using spin coating, etc. 
     The pixel-defining layer  119  may include a third hole H 3  arranged in the transmission area TA. The third hole H 3  may overlap the first hole H 1  and the second hole H 2 . A light transmittance of the transmission area TA may be improved by the first to third holes H 1 , H 2 , and H 3 . Though it is shown in  FIG.  6    that the buffer layer  111  is continuously arranged to correspond to the transmission area TA, the buffer layer  111  may include a hole located in the transmission area TA. A portion of the opposite electrode  123  described below may be arranged on the inner surfaces of the first to third holes H 1 , H 2 , and H 3 . 
     A first emission layer  122   b  and a second emission layer  122   b ′ are arranged inside the first opening OP 1  and the second opening OP 2  of the pixel-defining layer  119 , the first emission layer  122   b  and the second emission layer  122   b ′ respectively corresponding to the first pixel electrode  121  and the second pixel electrode  121 ′. The first emission layer  122   b  and the second emission layer  122   b ′ may include a polymer material or a low molecular weight material and emit red, green, blue, or white light. 
     An organic functional layer  122   e  may be arranged on and/or under the first emission layer  122   b  and the second emission layer  122   b ′. The organic functional layer  122   e  may include a first functional layer  122   a  and/or a second functional layer  122   c . According to some example embodiments, the first functional layer  122   a  or the second functional layer  122   c  may be omitted. 
     The first functional layer  122   a  may be arranged under the first emission layer  122   b  and the second emission layer  122   b ′. The first functional layer  122   a  may include a single layer or a multi-layer including an organic material. The first functional layer  122   a  may include a hole transport layer (HTL), which has a single-layered structure. Alternatively, the first functional layer  122   a  may include a hole injection layer (HIL) and an HTL. The first functional layer  122   a  may be formed as one body to correspond to the main and auxiliary organic light-emitting diodes OLED and OLED′ in the main display area MDA and the component area CA. 
     The second functional layer  122   c  may be arranged on the first emission layer  122   b  and the second emission layer  122   b ′. The second functional layer  122   c  may include a single layer or a multi-layer including an organic material. The second functional layer  122   c  may include an electron transport layer (ETL) and/or an electron injection layer (EIL). The second functional layer  122   c  may be formed as one body to correspond to the main and auxiliary organic light-emitting diodes OLED and OLED′ in the main display area MDA and the component area CA. 
     The opposite electrode  123  is arranged on the second functional layer  122   c . The opposite electrode  123  may include a conductive material having a small work function. For example, the opposite electrode  123  may include a (semi) transparent layer including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chrome (Cr), lithium (Li), calcium (Ca), or an alloy thereof. Alternatively, the opposite electrode  123  may include a layer including ITO, IZO, ZnO, or In 2 O 3  on the (semi) transparent layer including the above material. The opposite electrode  123  may be formed as one body to correspond to the main and auxiliary organic light-emitting diodes OLED and OLED′ in the main display area MDA and the component area CA. 
     The layers from the first pixel electrode  121  to the opposite electrode  123  formed in the main display area MDA may constitute the main organic light-emitting diode OLED. The layers from the first pixel electrode  121 ′ to the opposite electrode  123  formed in the component area CA may constitute the auxiliary organic light-emitting diode OLED′. 
     A top layer  150  may be formed on the opposite electrode  123 , the top layer  150  including an organic material. The top layer  150  may include a layer configured to protect the opposite electrode  123  and simultaneously increase a light-extraction efficiency. The top layer  150  may include an organic material having a higher refractive index than the opposite electrode  123 . Alternatively, the top layer  150  may include a stack of layers having different refractive indexes. For example, the top layer  150  may include a stack of a high refractive index layer/a low refractive index layer/a high refractive index layer. In this case, the refractive index of the high refractive index layer may be 1.7 or more and the refractive index of the low refractive index layer may be 1.3 or less. 
     The top layer  150  may additionally include lithium fluoride (LiF). Alternatively, the top layer  150  may additionally include an inorganic insulating material such as silicon oxide (SiO x ) and silicon nitride (SiN x ). 
     The first functional layer  122   a , the second functional layer  122   c , the opposite electrode  123 , and the top layer  150  may each include a transmission hole TAH corresponding to the transmission area TA. That is, Each of the first functional layer  122   a , the second functional layer  122   c , the opposite electrode  123 , and the top layer  150  may include an opening corresponding to the transmission area TA. The areas of the openings may be substantially the same. For example, the area of the opening of the opposite electrode  123  may be substantially the same as the area of the transmission hole TAH. 
     When the transmission hole TAH corresponds to the transmission area TA, it may be understood that the transmission hole TAH overlaps the transmission area TA. In this case, the area of the transmission hole TAH may be less than the area of the first hole H 1  formed in the inorganic insulating layer IL. For this, it is shown in  FIG.  6    that a width Wt of the transmission hole TAH is less than the width of the first hole H 1 . Here, the area of the transmission hole TAH may be defined as the area of an opening having a smallest area among the openings constituting the transmission hole TAH. The area of the first hole H 1  may be defined as the area of an opening having a smallest area among the openings constituting the first hole H 1 . 
     A portion of the opposite electrode  123  is removed from the transmission area TA due to the transmission hole TAH. Through this configuration, a light transmittance of the transmission area TA may be remarkably improved. 
     The bottom metal layer BML in the component area CA may be provided to correspond to the entire component area CA. In this case, the bottom metal layer BML may include a bottom hole BMLH overlapping the transmission area TA. According to some example embodiments, the shape and size of the transmission area TA may be defined by the shape and size of the bottom hole BMLH. The bottom metal layer BML may not be arranged in the main display area MDA. 
       FIG.  7    is an equivalent circuit diagram of a pixel circuit PC driving a sub-pixel according to some example embodiments. 
       FIG.  7    shows the pixel circuit PC of the main sub-pixel Pm, and the pixel circuit PC′ of the auxiliary sub-pixel Pa may be the same as or different from the pixel circuit PC of the main sub-pixel Pm. An embodiment below is described using an example in which the pixel circuit PC′ of the auxiliary sub-pixel Pa is the same as the pixel circuit PC of the main sub-pixel Pm. 
     The pixel circuit PC may include first to seventh transistors T 1 , T 2 , T 3 , T 4 , T 5 , T 6 , and T 7  and a first capacitor Cst and a second capacitor Cbt. The pixel circuit PC may be connected to a data line DL, a first scan line SL 1 , a second scan line SL 2 , a third scan line SL 3 , a fourth scan line SL 4 , and an emission control line EL. In addition, the pixel circuit PC may be connected to first and second initialization voltage lines VL 1  and VL 2  and a driving voltage line PL. The pixel circuit PC may be connected to an organic light-emitting diode OLED as a display element. 
     The driving voltage line PL may transfer a driving voltage ELVDD to the first transistor T 1 . The first initialization voltage line VL 1  may transfer a first initialization voltage Vint 1  to a second node N 2 , the first initialization voltage Vint 1  initializing the first transistor T 1 . The second initialization voltage line VL 2  may transfer a second initialization voltage Vint 2  to the organic light-emitting diode OLED, the second initialization voltage Vint 2  initializing the organic light-emitting diode OLED. 
     It is shown in  FIG.  7    that the third transistor T 3  and the fourth transistor T 4  among the first to seventh transistors T 1 , T 2 , T 3 , T 4 , T 5 , T 6 , and T 7  include n-channel metal oxide semiconductor field effect transistors (NMOS) and the rest of the transistors include p-channel metal oxide semiconductor field effect transistors (PMOS). 
     The first transistor T 1  is connected to a first node N 1  and a third node N 3 . The first transistor T 1  is connected to the driving voltage line PL through the fifth transistor T 5  and electrically connected to the organic light-emitting diode OLED through the sixth transistor T 6 . A gate electrode of the first transistor T 1  is connected to the second node N 2 . The first transistor T 1  serves as a driving transistor, receives a data signal DATA according to a switching operation of the second transistor T 2 , and supplies a driving current IDLED to the organic light-emitting diode OLED. 
     The second transistor T 2  (a switching transistor) is connected to the data line DL and the first node N 1 . The second transistor T 2  is connected to the driving voltage line PL through the fifth transistor T 5 . A gate electrode of the second transistor T 2  is connected to the first scan line SL 1 . The second transistor T 2  is turned on in response to a first scan signal SS 1  transferred through the first scan line SL 1  and performs a switching operation of transferring a data signal DATA transferred through the data line DL to the first node N 1 . 
     The third transistor T 3  (a compensation transistor) is connected to the first node N 1  and the third node N 3 . The third transistor T 3  is connected to the organic light-emitting diode OLED through the sixth transistor T 6 . A gate electrode of the third transistor T 3  is connected to a second scan line SL 2 . The third transistor T 3  is turned on in response to a second scan signal SS 2  transferred through the second scan line SL 2  and diode-connects the first transistor T 1 . The second scan signal SS 2  may include an inverted signal of a first scan signal SS 1 . The second scan signal SS 2  may be applied at the same timing as the first scan signal SS 1 . 
     The fourth transistor T 4  (a first initialization transistor) is connected to the second node N 2  and the first initialization voltage line VL 1 . A gate electrode of the fourth transistor T 4  is connected to a third scan line SL 3 . The fourth transistor T 4  is turned on in response to a third scan signal SS 3  transferred through the third scan line SL 3  and initializes the voltage of the gate electrode of the first transistor T 1  by transferring the first initialization voltage Vint 1  from the first initialization voltage line VL 1  to the gate electrode of the first transistor T 1 . A third scan signal SS 3  may be applied at a timing prior to a first scan signal SS 1 . 
     The fifth transistor T 5  (a first emission control transistor) is connected to the driving voltage line PL and the first node N 1 . The sixth transistor T 6  (a second emission control transistor) is connected to the third node N 3  and the organic light-emitting diode OLED. A gate electrode of each of the fifth transistor T 5  and the sixth transistor T 6  is connected to an emission control line EL, and the fifth transistor T 5  and the sixth transistor T 6  are simultaneously turned on in response to an emission control signal EM and form a current path such that the driving current IDLED flows from the driving voltage line PL to the organic light-emitting diode OLED. 
     A seventh transistor T 7  (a second initialization transistor) is connected to the organic light-emitting diode OLED and the second initialization voltage line VL 2 . A gate electrode of the seventh transistor T 7  is connected to the fourth scan line SL 4 . The seventh transistor T 7  is turned on in response to a fourth scan signal SS 4  transferred through the fourth scan line SL 4  and initializes the organic light-emitting diode OLED by transferring a second initialization voltage Vint 2  from the second initialization voltage line VL 2  to the organic light-emitting diode OLED. A fourth scan signal SS 4  may be applied at a timing prior to a first scan signal SS 1  or applied at a timing later than a first scan signal SS 1 . According to some example embodiments, the seventh transistor T 7  may be omitted. 
     The first capacitor Cst includes the first electrode CE 1  and the second electrode CE 2 . The first electrode CE 1  is connected to the first transistor T 1 , and the second electrode CE 2  is connected to the driving voltage line PL. The first capacitor Cst serves as a storage capacitor and may maintain a voltage applied to the gate electrode of the first transistor T 1  by storing and maintaining a voltage corresponding to a voltage difference between two opposite ends of the driving voltage line PL and the gate electrode of the first transistor T 1 . 
     The second capacitor Cbt includes a third electrode CE 3  and a fourth electrode CE 4 . The third electrode CE 3  is connected to the first scan line SL 1  and the gate electrode of the second transistor T 2 . The fourth electrode CE 4  is connected to the gate electrode of the first transistor T 1  and the first electrode CE 1  of the first capacitor Cst. The second capacitor Cbt serves as a boosting capacitor. In the case where a first scan signal SS 1  of the first scan line SL 1  is a voltage that turns off the second transistor T 2 , the second capacitor Cbt may reduce a voltage (a black voltage) that displays black by raising the voltage of the second node N 2 . 
     The organic light-emitting diode OLED includes a pixel electrode and an opposite electrode. The opposite electrode may receive a common voltage ELVSS. The organic light-emitting diode OLED displays an image by receiving the driving current IDLED from the first transistor T 1  and emitting light. 
     The pixel circuit PC is not limited to the number of transistors, the number of capacitors, and the circuit design described with reference to  FIG.  7    and may be variously modified. 
       FIG.  8    is a view of the arrangement of wirings in the main display area MDA according to some example embodiments. 
     The main sub-pixels Pm may be respectively connected to corresponding pixel circuits. Each pixel circuit may be connected to the first initialization voltage line VL 1 , the second initialization voltage line VL 2 , the first to fourth scan lines SL 1 , SL 2 , SL 3 , and SL 4 , the data line DL. The driving voltage line PL, the first initialization voltage line VL 1  and the second initialization voltage line VL 2 , and the first to fourth scan lines SL 1 , SL 2 , SL 3 , and SL 4  may extend in an x-direction (a first direction, a row direction), and the data line DL and the driving voltage line PL may extend in a y-direction (a second direction, a column direction). That is, each main sub-pixel Pm may be connected to the first initialization voltage line VL 1 , the second initialization voltage line VL 2 , the first to fourth scan lines SL 1 , SL 2 , SL 3 , and SL 4 , the data line DL, and the driving voltage line PL. The driving voltage line PL may be repeatedly arranged in the x-direction with a column interval in the main display area MDA.  FIG.  8    shows only the first scan line SL 1  and the fourth scan line SL 4 , for convenience of description. 
     The first scan line SL 1  and the fourth scan line SL 4  may be shared by two main sub-pixels Pm neighboring each other in the y-direction, that is, the two main sub-pixels Pm on neighboring rows and on the same column. For example, the first scan line SL 1  ( i ) to which a main sub-pixel  21  on a (i)-th row ((i) N) is connected may be connected to a main sub-pixel  22  on a (i+1)-th row ((i+1) N). The first scan line SL 1  ( i ) connected to the main sub-pixel  21  may serve as a fourth scan line SL 4  (i+1) connected to the main sub-pixel  22 , and the first scan line SL 1  (i+1) connected to the main sub-pixel  22  may serve as a fourth scan line SL 4  (i+2) connected to the main sub-pixel Pm arranged on the next row of the same column in the y-direction. 
       FIG.  9    is a view of the arrangement of wirings in the component area CA according to some example embodiments. 
     The auxiliary sub-pixels Pa may be respectively connected to corresponding pixel circuits. Each pixel circuit may be connected to the first to fourth scan lines SL 1 , SL 2 , SL 3 , and SL 4 , the first initialization voltage line VL 1 , the second initialization voltage line VL 2 , the data line DL, and the driving voltage line PL. The first to fourth scan lines SL 1 , SL 2 , SL 3 , and SL 4 , and the first initialization voltage line VL 1  and the second initialization voltage line VL 2  may extend in the x-direction, and the data line DL and the driving voltage line PL may extend in the y-direction. That is, each auxiliary sub-pixel may be connected to the first to fourth scan lines SL 1 , SL 2 , SL 3 , and SL 4 , the first initialization voltage line VL 1 , the second initialization voltage line VL 2 , the data line DL, and the driving voltage line PL. The driving voltage line PL may be repeatedly arranged with a row interval in the x-direction in the component area CA.  FIG.  9    shows only the first scan line SL 1  and the fourth scan line SL 4 , for convenience of description. 
     The first initialization voltage line VL 1  may be between pixel circuits of two auxiliary sub-pixels Pa neighboring each other in the y-direction, that is, the two auxiliary sub-pixels Pa on the same column and on neighboring rows and accordingly be shared by the pixel circuits. For example, the first initialization voltage line VL 1  may be between a k-th row (k)N and a (k+1)-th row (k+1)N, and a pixel circuit of the auxiliary sub-pixel  31  on the k-th row (k)N and a pixel circuit of the auxiliary sub-pixel  33  on the (k+1)-th row (k+1)N may be connected to the first initialization voltage line VL 1 . Pixel circuits of two auxiliary sub-pixels Pa may be symmetric with respect to the first initialization voltage line VL 1 . For example, a pixel circuit connected to the auxiliary sub-pixel  31  and a pixel circuit connected to the auxiliary sub-pixel  33  may be symmetric with respect to the first initialization voltage line VL 1 . 
     Because the first initialization voltage line VL 1  is shared by pixel circuits connected to a pair of auxiliary sub-pixels Pa neighboring each other on the same column through a vertical symmetrical structure, the area in which the pixel circuits are arranged in the component area CA may be reduced. Accordingly, a light transmittance of the transmission area TA and a light transmittance of the entire component area CA may be improved. 
     The data line DL and the driving voltage line PL are arranged on the left of the main sub-pixel Pm in  FIG.  8   , and the data line DL and the driving voltage line PL are arranged on the right of the main sub-pixel Pm in  FIG.  9   . The embodiments according to the present disclosure are not limited thereto and the positions of the data line DL and the driving voltage line PL may be changed depending on the arrangement of elements constituting the pixel circuit. 
       FIG.  10    is a plan view of a pixel circuit of an auxiliary sub-pixel according to some example embodiments.  FIG.  11    is a cross-sectional view of the pixel circuit taken along the lines I-I′ and II-II′ of  FIG.  10   . Hereinafter, some detailed descriptions of the same elements as those of  FIG.  6    may be omitted. 
       FIG.  10    shows a pair of pixel circuits arranged on the same column of neighboring rows in the component area CA shown in  FIG.  9   . A top pixel circuit PCa and a bottom pixel circuit PCb shown in  FIG.  10    have a symmetric structure with respect to the first initialization voltage line VL 1 . For example, the arrangements of the first to seventh transistors T 1 , T 2 , T 3 , T 4 , T 5 , T 6 , and T 7  and the first capacitors Cst and the second capacitors Cbt of the top pixel circuit PCa and the bottom pixel circuit PCb are symmetric with respect to the first initialization voltage line VL 1 . A distance between the first initialization voltage line VL 1  and the second initialization voltage line VL 2  connected to the top pixel circuit PCa may be the same as a distance between the first initialization voltage line VL 1  and the second initialization voltage line VL 2  connected to the bottom pixel circuit PCb. 
     The pixel circuit may be connected to the first scan line SL 1 , the second scan line SL 2 , the third scan line SL 3 , the fourth scan line SL 4 , the emission control line EL, the first initialization voltage line VL 1 , and the second initialization voltage line VL 2  each extending in the x-direction. In addition, the pixel circuit may be connected to the data line DL and the driving voltage line PL each extending in the y-direction. 
     The pixel circuit may include the first transistor T 1 , the second transistor T 2 , the third transistor T 3 , the fourth transistor T 4 , the fifth transistor T 5 , the sixth transistor T 6 , the seventh transistor T 7 , the first capacitor Cst, and the second capacitor Cbt. 
     According to some example embodiments, the first transistor T 1 , the second transistor T 2 , the third transistor T 3 , the fourth transistor T 4 , the fifth transistor T 5 , the sixth transistor T 6 , and the seventh transistor T 7  may each include a thin film transistor including a silicon semiconductor. The third transistor T 3  and the fourth transistor T 4  may include a thin film transistor including an oxide semiconductor. Hereinafter, the first to seventh transistors T 1 , T 2 , T 3 , T 4 , T 5 , T 6 , and T 7  are respectively denoted by first to seventh thin film transistors T 1 , T 2 , T 3 , T 4 , T 5 , T 6 , and T 7 . 
     A first semiconductor layer may be arranged over the substrate  100 , the first semiconductor layer including a silicon semiconductor. As another example, the buffer layer  111  may be formed on the substrate  100 , and the first semiconductor layer may be formed on the buffer layer  111 . As shown in  FIG.  6   , the buffer layer  111  may have a structure in which the first buffer layer  111   a  and the second buffer layer  111   b  are stacked. The first semiconductor layer may include polycrystalline silicon. 
     The substrate  100  may include glass, a ceramic material, a metal material, or a flexible or bendable material. In the case where the substrate  100  is flexible or bendable, the substrate  100  may include a polymer resin such as polyethersulfone (PES), polyacrylate, polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyarylate, polyimide (PI), polycarbonate (PC), and cellulose acetate propionate (CAP). 
     The substrate  100  may have a multi-layered structure. For example, the substrate  100  may have a structure in which a first base layer  101 , a first barrier layer  103 , a second base layer  105 , and a second barrier layer  107  are sequentially stacked. The first base layer  101  and the second base layer  103  may include the polymer resin. The first barrier layer  101  and the second barrier layer  103  prevent or reduce instances of external foreign substances or contaminants causing damage and may include a single layer or a multi-layer including an inorganic material such as silicon nitride (SiN x ) and silicon oxide (SiO x ). 
     Some regions of the first semiconductor layer may constitute the semiconductor layer of each of the first transistor T 1 , the second transistor T 2 , the fifth transistor T 5 , the sixth transistor T 6 , and the seventh transistor T 7 . 
     Semiconductor layers of the first transistor T 1 , the second transistor T 2 , the fifth transistor T 5 , the sixth transistor T 6 , and the seventh transistor T 7  may respectively include channel regions, source regions S 1 , S 2 , S 5 , S 6 , and S 7 , and drain regions D 1 , D 2 , D 5 , D 6 , and D 7 , the source regions S 1 , S 2 , S 5 , S 6 , and S 7  and the drain regions D 1 , D 2 , D 5 , D 6 , and D 7  respectively being on two opposite sides of the channel regions. For example, the source region and the drain region may be doped with impurities and may include p-type impurities. The source region and the drain region may respectively correspond to a source electrode and a drain electrode. The source region and the drain region may be exchanged with each other depending on the characteristic of the transistor. Hereinafter, terms a ‘source region’ and a ‘drain region’ are used instead of a source electrode and a drain electrode.  FIG.  11    shows a channel region C 1  of the first thin film transistor T 1  as an example. 
     The first gate insulating layer  112  is arranged on the first semiconductor layer. The first gate electrode G 1  of the first thin film transistor T 1 , the first scan line SL 1 , the fourth scan line SL 4 , and the emission control line EL may be arranged on the first gate insulating layer  112 . The first scan line SL 1 , the fourth scan line SL 4 , and the emission control line EL may extend in the x-direction and be apart from each other in the y-direction. 
     The gate electrode G 1  of the first thin film transistor T 1  includes an isolated pattern and overlaps the channel region C 1  with the first gate insulating layer  112  therebetween. 
     A region of the first scan line SL 1  overlapping the channel region of the second thin film transistor T 2  may include the gate electrode G 2  of the second thin film transistor T 2 . A region of the fourth scan line SL 4  overlapping the channel region of the seventh thin film transistor T 7  may include a gate electrode G 7  of the seventh thin film transistor T 7 . Regions of the emission control line EL overlapping the channel regions of the fifth and sixth thin film transistors T 5  and T 6  may respectively include gate electrodes G 5  and G 6  of the fifth and sixth thin film transistors T 5  and T 6 . 
     The second gate insulating layer  113  may be arranged on the gate electrode G 1  of the first thin film transistor T 1 , the first scan line SL 1 , the fourth scan line SL 4 , and the emission control line EL. 
     An electrode voltage line HL, the first initialization voltage line VL 1 , a bottom scan line SL 2   a  of the second scan line SL 2 , and a bottom scan line SL 3   a  of the third scan line SL 3  may extend in the x-direction and be apart from each other in the y-direction on the second gate insulating layer  113 . 
     The electrode voltage line HL may cover at least a portion of the gate electrode G 1  of the first thin film transistor T 1  and serve as the second electrode CE 2  of the first capacitor Cst. The electrode voltage line HL may include an opening. The first capacitor Cst includes the first electrode CE 1  and the second electrode CE 2  and may overlap the first thin film transistor T 1 . The gate electrode G 1  of the first thin film transistor T 1  may also serve as the first electrode CE 1  of the first capacitor Cst. That is, the gate electrode G 1  of the first thin film transistor T 1  and the first electrode CE 1  may be formed as one body. 
     The interlayer insulating layer  114  may be arranged on the second gate insulating layer  113 . A second semiconductor layer may be arranged on the interlayer insulating layer  114 , the second semiconductor layer including the semiconductor layer of each of the third thin film transistor T 3  and the fourth thin film transistor T 4 . The second semiconductor layer may include zinc (Zn) oxide-based material and include zinc (Zn) oxide, indium (In)-zinc (Zn) oxide, and gallium (Ga)-indium (In)-zinc (Zn) oxide. According to some example embodiments, the second semiconductor layer may include In—Ga—Zn—O (IGZO), In—Sn—Zn—O (ITZO), or In—Ga—Sn—Zn—O (IGTZO) semiconductor containing metal such as indium (In), gallium (Ga), and stannum (Sn) in ZnO. 
     The second semiconductor layer of the top pixel circuit PCa may be connected to the second semiconductor layer of the bottom pixel circuit PCb. The second semiconductor layer of the top pixel circuit PCa and the second semiconductor layer of the bottom pixel circuit PCb may be formed as one body. 
     Some regions of the second semiconductor layer may respectively constitute the semiconductor layers of the third thin film transistor T 3  and the fourth thin film transistor T 4 . The semiconductor layers of the third thin film transistor T 3  and the fourth thin film transistor T 4  may each include a channel region, a source region, and a drain region, the source region and a drain region respectively being on two opposite sides of the channel region. The source regions S 3  and S 4  and the drain regions D 3  and D 4  of the third thin film transistor T 3  and the fourth thin film transistor T 4  may be formed by adjusting carrier concentration of an oxide semiconductor and making the source region and the drain region conductive. The source regions S 3  and S 4  and the drain regions D 3  and D 4  of the third thin film transistor T 3  and the fourth thin film transistor T 4  may be formed by increasing carrier concentration through plasma treatment that uses a hydrogen (H)-based gas, a fluorine (F)-based gas, or a combination thereof performed on the oxide semiconductor.  FIG.  11    shows the channel region C 4  of the fourth thin film transistor T 4  as an example. 
     The second semiconductor layer may include the fourth electrode CE 4  of the second capacitor Cbt. In a plan view, the fourth electrode CE 4  of the second capacitor Cbt may be between the semiconductor layer of the third thin film transistor T 3  and the semiconductor layer of the fourth thin film transistor T 4 . The fourth electrode CE 4  may extend from the semiconductor layer of the third thin film transistor T 3  or the semiconductor layer of the fourth thin film transistor T 4 . A portion of the first scan line SL 1  overlapping the fourth electrode CE 4  of the second capacitor Cbt may include the third electrode CE 3  of the second capacitor Cbt. 
     The third gate insulating layer  115  may be arranged on the second semiconductor layer. The top scan line SL 2   b  of the second scan line SL 2  and a top scan line SL 3   b  of the third scan line SL 3  may extend in the x-direction on the third gate insulating layer  115 . That is, the second scan line SL 2  and the third scan line SL 3  may include two conductive layers arranged on different layers. 
     The top scan line SL 2   b  of the second scan line SL 2  may overlap at least a portion of the bottom scan line SL 2   a . The top scan line SL 3   b  of the third scan line SL 3  may overlap at least a portion of a bottom scan line SL 3   a.    
     A portion of the bottom scan line SL 2   a  of the second scan line SL 2  overlapping the second semiconductor layer may include a bottom gate electrode G 3   a  of the third thin film transistor T 3 , and a portion of the top scan line SL 2   b  of the second scan line SL 2  overlapping the second semiconductor layer may include a top gate electrode G 3   b  of the third thin film transistor T 3 . 
     A portion of the bottom scan line SL 3   a  of the third scan line SL 3  overlapping the second semiconductor layer may include a bottom gate electrode G 4   a  of the fourth thin film transistor T 4 , and a portion of the top scan line SL 3   b  overlapping the second semiconductor layer may include a top gate electrode G 4   b  of the fourth thin film transistor T 4 . 
     That is, the third thin film transistor T 3  and the fourth thin film transistor T 4  may each have a double-gate structure in which control electrodes are respectively provided on and under the semiconductor layer. The width of the bottom gate electrode G 3   a  of the third thin film transistor T 3  may be greater than the width of the top gate electrode G 3   b . The width of the bottom gate electrode G 4   a  of the fourth thin film transistor T 4  may be greater than the width of the top gate electrode G 4   b.    
     According to some example embodiments, the third gate insulating layer  115  may be patterned in a shape corresponding to the top scan line SL 2   b  of the second scan line SL 2  and the top scan line SL 3   b  of the third scan line SL 3 . 
     A second interlayer insulating layer  116  may cover the third thin film transistor T 3  and the fourth thin film transistor T 4  on the third gate insulating layer  115 . The driving voltage line PL, a node electrode  171 , and connection electrodes  172 ,  173 ,  174 ,  175 , and  176  may be arranged on the second interlayer insulating layer  116 . 
     The driving voltage line PL, the node electrode  171 , and the connection electrodes  172 ,  173 ,  174 ,  175 , and  176  may include a material having high conductivity such as a conductive oxide. For example, the driving voltage line PL, the node electrode  171 , and the connection electrodes  172 ,  173 ,  174 ,  175 , and  176  may each include a single layer or a multi-layer including at least one of aluminum (Al), copper (Cu), or titanium (T 1 ). According to some example embodiments, the driving voltage line PL, the node electrode  171 , and the connection electrodes  172 ,  173 ,  174 ,  175 , and  176  may each include a triple layer of Ti/Al/Ti that are sequentially arranged. 
     The second interlayer insulating layer  116  may include an inorganic material including oxide or nitride. For example, the second interlayer insulating layer  116  may include silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), tantalum oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ), or zinc oxide (ZnO 2 ). 
     The third gate insulating layer  115  and the second interlayer insulating layer  116  may constitute the inorganic insulating layer IL shown in  FIG.  6    in cooperation with the first gate insulating layer  112 , the second gate insulating layer  113 , and the interlayer insulating layer  114 . 
     Branches protruding from the driving voltage line PL may be electrically and respectively connected to the source region S 5  of the fifth thin film transistor T 5  and the electrode voltage line HL through contact holes. Accordingly, wirings configured to apply the driving voltage ELVDD may have a mesh structure. 
     The node electrode  171  may contact and be electrically connected to the first gate electrode G 1  of the first thin film transistor T 1  and the second semiconductor layer through contact holes. One end of the node electrode  171  may be connected to the gate electrode G 1  of the first thin film transistor T 1  through an opening of the second electrode CE 2  of the first capacitor Cst. The other end of the node electrode  171  may be connected to the fourth electrode CE 4  of the second capacitor Cbt. 
     One end of the connection electrode  172  may be electrically connected to the drain region D 1  of the first thin film transistor T 1  and the source region S 6  of the sixth thin film transistor T 6  through contact holes. The other end of the connection electrode  172  may be electrically connected to the drain region D 3  of the third thin film transistor T 3  through a contact hole. 
     The connection electrode  173  may be electrically connected to the source region S 2  of the second thin film transistor T 2  through a contact hole. 
     The connection electrode  174  may be electrically connected to the drain region D 6  of the sixth thin film transistor T 6  through a contact hole. 
     One end of the connection electrode  175  may be electrically connected to the drain region D 7  of the seventh thin film transistor T 7  through a contact hole. The other end of the connection electrode  175  may be electrically connected to the second initialization voltage line VL 2  through a contact hole. 
     The connection electrode  176  may be electrically connected to the source region S 4  of the fourth thin film transistor T 4  and the first initialization voltage line VL 1  through contact holes. 
     The first planarization layer  117   a  and the second planarization layer  117   b  may be stacked on the second interlayer insulating layer  116 . The data line DL and the connection metal CM may be between the first planarization layer  117   a  and the second planarization layer  117   b.    
     The data line DL and the connection metal CM may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (T 1 ) and include a single layer or a multi-layer. For example, the data line DL and the connection metal CM may include a multi-layered structure of Ti/Al/Ti. 
     The data line DL may be electrically connected to the source region S 2  of the second thin film transistor T 2  by being connected to the connection electrode  173  through a contact hole. 
     The connection metal CM is connected to the connection electrode  174  through a contact hole, and the pixel electrode  121  is connected to the connection metal CM through a via hole of the second planarization layer  117   b . Therefore, the pixel electrode  121  may be electrically connected to the pixel circuit. 
     The pixel electrode  121  may be arranged on the second planarization layer  117   b . The pixel-defining layer  119  may be arranged on the second planarization layer  117   b  and covering the edges of the pixel electrodes  121 .  FIG.  11    shows only the emission layer  122   b . As described in  FIG.  6   , various functional layers may be further arranged on and/or under the emission layer  122   b.    
       FIG.  12    is a plan view of a pixel circuit PC of a main sub-pixel Pm according to some example embodiments. Hereinafter, elements different from those of  FIG.  10    are mainly described. Some repetitive detailed descriptions of some the same elements as those of  FIG.  10    may be omitted. 
       FIG.  12    is a plan view of a pixel circuit PC of a main sub-pixel Pm according to some example embodiments.  FIG.  12    shows the pixel circuit PC in the main display area MDA shown in  FIG.  8   . 
     The pixel circuit PC may be connected to the first scan line SL 1 , the second scan line SL 2 , the third scan line SL 3 , the fourth scan line SL 4 , the emission control line EL, the first initialization voltage line VL 1 , and the second initialization voltage line VL 2  each extending in the x-direction. In addition, the pixel circuit PC may be connected to the data line DL and the driving voltage line PL extending in the y-direction. The first initialization voltage line VL 1  and the second initialization voltage line VL 2  may be arranged on each row. 
     In the pixel circuit PC of the auxiliary sub-pixel Pa shown in  FIG.  10   , the driving voltage line PL is electrically connected to the source region S 5  of the fifth thin film transistor T 5  and the electrode voltage line HL. In contrast, in the pixel circuit of the main sub-pixel Pm shown in  FIG.  12   , the connection electrode  177  may be arranged on the second interlayer insulating layer  116 , and the connection electrode  177  may be electrically connected to the source region S 5  of the fifth thin film transistor T 5  and the electrode voltage line HL through contact holes. 
     In the pixel circuit shown in  FIG.  12   , the driving voltage line PL may be arranged on the first planarization layer  117   a , that is, on the same layer as the data line DL and may include the same material as the data line DL. The driving voltage line PL may be electrically connected to the electrode voltage line HL through a contact hole. 
     The semiconductor layer of the seventh thin film transistor T 7  in the pixel circuit shown in  FIG.  12    has a greater length in the y-direction than the semiconductor layer of the seventh thin film transistor T 7  in the pixel circuit shown in  FIG.  10   . 
     The first scan line SL 1  and the fourth scan line SL 4  may be shared by two pixel circuits neighboring each other in the y-direction. That is, the fourth scan line SL 4  may be electrically connected to the second thin film transistor of another pixel circuit adjacent above the pixel circuit shown in  FIG.  12    in the (+) y-direction in the drawing. Therefore, a fourth scan signal SS 4  applied to the fourth scan line SL 4  may be transferred as a second scan signal to the second thin film transistor of the other pixel circuit. Likewise, the first scan line SL 1  may be electrically connected to the seventh thin film transistor of another pixel circuit adjacent below the pixel circuit shown in  FIG.  12    in the (−) y-direction in the drawing. Therefore, a first scan signal SS 1  applied to the first scan line SL 1  may be transferred as a fourth scan signal to the seventh thin film transistor of the other pixel circuit. 
     According to some example embodiments, the pixel circuit of the main sub-pixel Pm shown in  FIG.  12    may be repeatedly arranged in the x-direction and the y-direction. According to some example embodiments, the pixel circuits of the main sub-pixel Pm may have a horizontally symmetric structure. That is, a pair of pixel circuits symmetric with respect to a dashed line RL of  FIG.  12    may be repeatedly arranged in the main display area MDA in the x-direction and the y-direction. 
       FIG.  13    is a view of the arrangement of wirings in the main display area MDA according to some example embodiments. Hereinafter, configurations different from those of  FIG.  8    are mainly described. 
     Referring to  FIG.  13   , a first vertical voltage line VL 1 ′ and a second vertical voltage line VL 2 ′ may be further arranged in the main display area MDA shown in  FIG.  8   . The first vertical voltage line VL 1 ′ and the second vertical voltage line VL 2 ′ may extend in the y-direction. The first vertical voltage line VL 1 ′ may be connected to the first initialization voltage line VL 1  extending in the x-direction, and the second vertical voltage line VL 2 ′ may be connected to the second initialization voltage line VL 2  extending in the x-direction. Accordingly, a wiring configured to supply the first initialization voltage Vint 1  and a wiring configured to supply the second initialization voltage Vint 2  may have a mesh structure. 
     The first vertical voltage line VL 1 ′ may be arranged on a layer different from the first initialization voltage line VL 1  and electrically connected to the first initialization voltage line VL 1  by contacting the first initialization voltage line VL 1  through a contact hole. The second vertical voltage line VL 2 ′ may be arranged on a layer different from the second initialization voltage line VL 2  and electrically connected to the second initialization voltage line VL 2  by contacting the second initialization voltage line VL 2  through a contact hole. 
     The first vertical voltage line VL 1 ′ and the second vertical voltage line VL 2 ′ may be arranged on the same layer. The first vertical voltage line VL 1 ′ and the second vertical voltage line VL 2 ′ may be arranged on the same layer as the data line DL or the driving voltage line PL. The first vertical voltage line VL 1 ′ and the second vertical voltage line VL 2 ′ may include the same material as the data line DL or the driving voltage line PL. 
     In the main display area MDA, the driving voltage line PL, the first vertical voltage line VL 1 ′, and the second vertical voltage line VL 2 ′ may be alternately arranged with a constant interval (e.g. with a column interval) in the x-direction. That is, in the main display area MDA, one of the driving voltage line PL, the first vertical voltage line VL 1 ′, and the second vertical voltage line VL 2 ′ may extend in the y-direction. 
       FIG.  14    is a view of the arrangement of wirings in the component area CA according to some example embodiments. Hereinafter, configurations different from those of  FIG.  9    are mainly described. 
     Referring to  FIG.  14   , the first vertical voltage line VL 1 ′ and the second vertical voltage line VL 2 ′ extending in the y-direction may be further arranged in the component area CA shown in  FIG.  9   . The first vertical voltage line VL 1 ′ and the second vertical voltage line VL 2 ′ may extend in the y-direction. The first vertical voltage line VL 1 ′ may be connected to the first initialization voltage line VL 1  extending in the x-direction, and the second vertical voltage line VL 2 ′ may be connected to the second initialization voltage line VL 2  extending in the x-direction. Accordingly, a wiring configured to supply the first initialization voltage Vint 1  and a wiring configured to supply the second initialization voltage Vint 2  may have a mesh structure. 
     The first initialization voltage line VL 1  may be between pixel circuits of two auxiliary sub-pixels Pa on the same column and neighboring rows and be connected to the two auxiliary sub-pixels Pa. The pixel circuits of the two auxiliary sub-pixels Pa may be symmetric with respect to the first initialization voltage line VL 1 . For example, the pixel circuit connected to the auxiliary sub-pixel  31  and the pixel circuit connected to the auxiliary sub-pixel  33  may be symmetric with respect to the first initialization voltage line VL 1 . 
     The first vertical voltage line VL 1 ′ may be arranged on a layer different from the first initialization voltage line VL 1  and be electrically connected to the first initialization voltage line VL 1  by contacting the first initialization voltage line VL 1  through a contact hole. The second vertical voltage line VL 2 ′ may be arranged on a layer different from the second initialization voltage line VL 2  and be electrically connected to the second initialization voltage line VL 2  by contacting the second initialization voltage line VL 2  through a contact hole. 
     The first vertical voltage line VL 1 ′ and the second vertical voltage line VL 2 ′ may be arranged on the same layer. The first vertical voltage line VL 1 ′ and the second vertical voltage line VL 2 ′ may be arranged on the same layer as the data line DL or the driving voltage line PL. The first vertical voltage line VL 1 ′ and the second vertical voltage line VL 2 ′ may include the same material as the data line DL or the driving voltage line PL. 
     In the component area CA, the driving voltage line PL, the first vertical voltage line VL 1 ′, and the second vertical voltage line VL 2 ′ may be alternately arranged with a constant interval (e.g. with a column interval) in the x-direction. That is, in the component area CA, one of the driving voltage line PL, the first vertical voltage line VL 1 ′, and the second vertical voltage line VL 2 ′ may extend in the y-direction on each column. 
     In the embodiments of  FIGS.  13  and  14   , the driving voltage line PL may not be arranged on a column on which the first vertical voltage line VL 1 ′ and the second vertical voltage line VL 2 ′ are arranged. In this case, since the driving voltage lines PL on neighboring columns are connected to the electrode voltage line HL, the driving voltage ELVDD may be supplied to auxiliary sub-pixels Pa of a column on which the first vertical voltage line VL 1 ′ and the second vertical voltage line VL 2 ′ are arranged. 
       FIG.  15    is a plan view of the arrangement of pixel circuits PC of auxiliary sub-pixels Pa according to some example embodiments.  FIG.  15    shows pixel circuits PC arranged in a portion of the component area CA shown in  FIG.  14   . 
     In the component area CA, the driving voltage line PL, the first vertical voltage line VL 1 ′, and the second vertical voltage line VL 2 ′ may be alternately arranged with a column interval in the x-direction and accordingly one of the driving voltage line PL, the first vertical voltage line VL 1 ′, and the second vertical voltage line VL 2 ′ may extend in the y-direction on each column. 
     In the pixel circuits of a column on which the driving voltage line PL is arranged, branches PLb protruding from the driving voltage line PL may be electrically connected to the source region S 5  of the fifth thin film transistor T 5  and the electrode voltage line HL through contact holes. The pixel circuits of a column on which the first vertical voltage line VL 1 ′ and the second vertical voltage line VL 2 ′ are arranged may be electrically connected to each of the source region S 5  of the fifth thin film transistor T 5  and the electrode voltage line HL through contact holes by a connection electrode  178   
     In the pixel circuits of a column on which the driving voltage line PL is arranged and the pixel circuits of a column on which the second vertical voltage line VL 2 ′ is arranged, the source region D 4  of the fourth thin film transistor T 4  may be electrically connect to the first initialization voltage line VL 1  by the connection electrode  176 . In the pixel circuits of a column on which the first vertical voltage line VL 1 ′ is arranged, a branch VL 1   b  protruding from the first vertical voltage line VL 1 ′ may be electrically connected to each of the source region D 4  of the fourth thin film transistor T 4  and the first initialization voltage line VL 1 . 
     In the pixel circuits of a column on which the driving voltage line PL is arranged and the pixel circuit of a column on which the first vertical voltage line VL 1 ′ is arranged, the drain electrode D 7  of the seventh thin film transistor T 7  may be electrically connected to the second initialization voltage line VL 2  by the connection electrode  175 . In the pixel circuits of a column on which the second vertical voltage line VL 2 ′ is arranged, a branch VL 2   b  protruding from the second vertical voltage line VL 2 ′ may be electrically connected to each of the source region S 7  of the seventh thin film transistor T 7  and the second initialization voltage line VL 2 . 
       FIG.  16    is a plan view of a display panel  10 ′ according to some example embodiments. 
     The display panel  10 ′ shown in  FIG.  16    is different from the embodiment of  FIG.  3    in that the initialization voltage supply line  15  is arranged below the main display area MDA. According to some example embodiments, the initialization voltage supply line  15  may be arranged over the main display area MDA or arranged both above and below the main display area MDA. According to some example embodiments, the initialization voltage supply line  15  may be arranged on the left and right of the main display area MDA as shown in  FIG.  3    and arranged above and/or below the main display area MDA as shown in  FIG.  16   . 
     The initialization voltage supply line  15  may be configured to apply an initialization voltage to the pixel circuits of sub-pixels, that is, the main and auxiliary sub-pixels Pm and Pa through the vertical voltage line VL′ extending in the y-direction. The vertical voltage VL′ may include the first vertical voltage line VL 1 ′ and the second vertical voltage line VL 2 ′ shown in  FIGS.  13  to  15   . Though  FIG.  16    shows one initialization voltage supply line  15 , an initialization voltage supply line connected to the first vertical voltage line VL 1 ′ and an initialization voltage supply line connected to the second vertical voltage line VL 2 ′ may be provided in the peripheral area DPA. 
     As shown in  FIGS.  13  to  15   , the first vertical voltage line VL 1 ′ may be electrically connected to the first initialization voltage line VL 1 , and the second vertical voltage line VL 2 ′ may be electrically connected to the second initialization voltage line VL 2 . In this case, the first initialization voltage line VL 1  and the second initialization voltage line VL 2  may receive an initialization voltage through the first vertical voltage line VL 1 ′ and the second vertical voltage line VL 2 ′. 
     Though the above embodiments describe the pixel circuit including the first thin film transistor that includes a silicon semiconductor and the second thin film transistor that includes an oxide semiconductor, the embodiments according to the present disclosure are not limited thereto. For example, the embodiment is applicable to a pixel circuit connected to the first initialization voltage line and the second initialization voltage line, the pixel circuit including only thin film transistors that include a silicon semiconductor and only thin film transistors that include an oxide semiconductor. 
     As described above, in the display panel and the display apparatus according to the present embodiments, because the pixel circuits that are vertically arranged share the initialization voltage line, a transmittance of the component area may be secured. However, the scope of embodiments according to the present disclosure are not limited by this effect. 
     It should be understood that embodiments described herein should be considered in a descriptive sense only and not for purposes of limitation. Descriptions of features or aspects within each embodiment should typically be considered as available for other similar features or aspects in other embodiments. While one or more embodiments have been described with reference to the figures, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope as defined by the following claims and their equivalents.