Patent Publication Number: US-2023145751-A1

Title: Voltage dividing capacitor circuits, supply modulators and wireless communication devices

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This U.S. non-provisional application is a continuation of and claims the benefit of priority under 35 U.S.C. §§ 120/121 to U.S. patent application Ser. No. 17/334,053, filed on May 28, 2021, which claims the benefit of priority under 35 USC § 119 to Korean Patent Application No. 10-2020-0114323, filed on Sep. 8, 2020 and to Korean Patent Application No. 10-2021-0005733, filed on Jan. 15, 2021, in the Korean Intellectual Property Office, the disclosures of each of which are incorporated by reference in their entirety herein. 
    
    
     BACKGROUND 
     Various example embodiments generally relate to voltage converters in integrated circuits, and more particularly to voltage dividing capacitor circuits, supply modulators, and/or wireless communication devices including the same, and/or methods of operating the same. 
     Wireless communication devices, such as smartphones, tablets, and Internet of Things (IoT) devices, etc., use WCDMA (3G), LTE, LTE Advanced (4G), 5G New Radio (NR), etc., technology for high speed communication. As communication technology has been increasingly advancing, transmission and/or reception signals having a higher peak-to-average power ratio (PAPR) and a greater bandwidth are desired and/or required. Thus, if a power supply of a power amplifier of a transmission end is connected to a battery, the efficiency of the power amplifier decreases. In order to increase the efficiency of a power amplifier having a high PAPR and a large bandwidth, average power tracking (APT) and/or envelope tracking (ET) is used. When using the ET technique, the efficiency and linearity of a power amplifier may be enhanced. A chip that supports the APT technique and/or ET technique is referred to as a supply modulator. 
     SUMMARY 
     Some example embodiments may provide a voltage dividing capacitor circuit capable of enhancing efficiency of a circuit. 
     Some example embodiments may provide a supply modulator capable of performing discrete ET and providing enhanced electrical efficiency. 
     Some example embodiments may provide a wireless communication device including a supply modulator capable of performing discrete ET and enhancing the electrical efficiency of the wireless communication device. 
     According to some example embodiments, a voltage dividing capacitor circuit includes a first capacitor voltage divider and a second capacitor voltage divider. The first capacitor voltage divider includes connected to a second voltage node, the first capacitor voltage divider including a first flying capacitor and a plurality of first switches, the second voltage node coupled to a second load capacitor, the plurality of first switches connected in series between a first voltage node and a ground node, the first voltage node coupled to a first load capacitor, and the ground node coupled to a ground voltage. The second capacitor voltage divider is connected between the first voltage node and the second voltage node, the second capacitor voltage divider including a second flying capacitor and a plurality of second switches, and the plurality of second switches connected in series between the first voltage node and the second voltage node. 
     According to some example embodiments, a voltage dividing capacitor circuit includes a first capacitor voltage divider including a first flying capacitor and a plurality of first switches, the plurality of first switches connected in series between a first voltage node and a third voltage node, the first voltage node coupled to a first load capacitor, the third voltage node coupled to a third load capacitor, and the first capacitor voltage divider connected to a second voltage node coupled to a second load capacitor, a second capacitor voltage divider connected between the first voltage node and the second voltage node, a third capacitor voltage divider connected between the second voltage node and the third voltage node, a fourth capacitor voltage divider connected between the third voltage node and a ground node coupled to a ground voltage, and a fifth capacitor voltage divider connected between the second voltage node and the ground node. 
     According to some example embodiments, a voltage dividing capacitor circuit includes a first capacitor voltage divider including a first flying capacitor and a plurality of first switches, the plurality of first switches connected in series between a first node and a second node, and the first capacitor voltage divider connected to a third node, and a second capacitor voltage divider including a second first flying capacitor and a plurality of second switches, the plurality of second switches connected in series between the third node and the second node. 
     According to some example embodiments, a supply modulator includes a DC-DC converter including an inductor connected to a battery voltage, first through third power switches connected between the inductor and one of a first voltage node, a second voltage node and a ground node, respectively, the ground node coupled to a ground voltage, a first load capacitor, the first load capacitor connected between the first voltage node and the ground node, a second load capacitor, the second load capacitor connected between the second voltage node and the ground node, and a voltage dividing capacitor circuit including at least two capacitor voltage dividers, the at least two capacitor voltage dividers connected to the first voltage node, the second voltage node and the ground node, wherein the DC-DC converter is configured to generate a current based on an energy stored in the inductor, and output the current to at least one of the first voltage node and the second voltage node based on a first set of switch control signals, and the voltage dividing capacitor circuit is configured to generate a plurality of voltages having different levels based on the current, and output the plurality of voltages to the first voltage node, the second voltage node and a first and second intermediate voltage nodes, the first intermediate voltage node connected between the first voltage node and the second voltage node, and the second intermediate voltage node connected between the second voltage node and the ground node. 
     According to at least one example embodiment, a wireless communication device includes a power amplifier configured to generate a radio frequency (RF) output signal based on a RF input signal, a supply modulator configured to generate a plurality of voltages in response to an envelope signal of the RF output signal, each of the plurality of voltages having different voltage levels, a switch array configured to select a selected supply voltage from a plurality of voltages based on a received plurality of switch control signals corresponding to the envelope signal, and connect the selected supply voltage to the power amplifier, and a modem configured to extract an envelope of a baseband signal, and generate the envelope signal based on the extracted envelope, wherein the supply modulator includes, a DC-DC converter including an inductor connected to a battery voltage, first through third power switches connected between the inductor and one of a first voltage node, a second voltage node, and a ground node, respectively, the ground node coupled to a ground voltage, a first load capacitor, the first load capacitor connected between the first voltage node and the ground node, a second load capacitor, the second load capacitor connected between the second voltage node and the ground node, and a voltage dividing capacitor circuit including at least two capacitor voltage dividers, the at least two capacitor voltage dividers connected to the first voltage node, the second voltage node, and the ground node, wherein the DC-DC converter is configured to, generate a current based on an energy stored in the inductor, and output the current to at least one of the first voltage node and the second voltage node based on power switch control signals, and wherein the voltage dividing capacitor circuit is configured to generate the plurality of voltages having different voltage levels based on the current, and output the plurality of voltages to the first voltage node, the second voltage node, and at least a first and second intermediate voltage nodes, the first intermediate voltage node connected between the first voltage node and the second voltage node, and the second intermediate voltage node connected between the second voltage node and the ground node. 
     According to at least one example embodiment, a wireless communication device includes a first power amplifier configured to generate a first radio frequency (RF) output signal based on a first RF input signal, a second power amplifier configured to generate a second RF output signal based on a second RF input signal, a supply modulator configured to output a plurality of voltages having different voltage levels in response to receiving a first envelope signal of the first RF output signal and a second envelope signal of the second RF output signal, and the supply modulator is configured to output a first average power voltage and a second average power voltage based on an average power signal, a first switch array configured to select a first selected supply voltage from the plurality of voltages in response to a plurality of first switch control signals corresponding to the first envelope signal, and output the first selected supply voltage to the first power amplifier, a second switch array configured to select a second selected supply voltage from the plurality of voltages in response to a plurality of second switch control signals corresponding to the second envelope signal, and output the second selected supply voltage to the second power amplifier, a third switch configured to selectively provide the first average power voltage to the first power amplifier based on a third switch control signal, and a fourth switch configured to selectively provide the second average power voltage to the second power amplifier based on a fourth switch control signal, and wherein the supply modulator includes, a DC-DC converter including an inductor connected to a battery voltage, first through third power switches connected between the inductor and one of a first voltage node, a second voltage node, and a ground node coupled to a ground voltage, respectively, a first load capacitor, the first load capacitor connected between the first voltage node and the ground node, and a second load capacitor, the second load capacitor connected between the second voltage node and the ground node, and a voltage dividing capacitor circuit including at least two capacitor voltage dividers connected to the first voltage node, the second voltage node, and the ground node, the DC-DC converter is configured to generate a current based on an energy stored in the inductor, and provide the current to at least one of the first voltage node and the second voltage node based on power switch control signals, and the voltage dividing capacitor circuit is configured to generate the plurality of voltages having different voltage levels based on the current, and output the plurality of voltages to the first voltage node, the second voltage node, and at least a first and second intermediate voltage nodes, the first intermediate voltage node connected between the first voltage node and the second voltage node, and the second intermediate voltage node connected between the second voltage node and the ground node. 
     Accordingly, the voltage dividing capacitor circuit includes a plurality of capacitor voltage dividers connected to a first voltage node, a second voltage node and a ground node, and each of the capacitor voltage dividers performs voltage conversion in response to phase control signal set. The DC-DC converter provides current at least one of the first and second voltage nodes based on battery voltage and the capacitor voltage dividers provide output voltages to load capacitors using voltage based on the current. Therefore, the SIMO converter may rapidly provide a current to a target voltage node to obtain quick response characteristic and since each of the voltage nodes is coupled to the ground voltage via a corresponding load capacitor, the SIMO converter may reduce output ripple. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Illustrative, non-limiting example embodiments will be more clearly understood from the following detailed description in conjunction with the accompanying drawings. 
         FIG.  1    is a block diagram illustrating a wireless communication device according to some example embodiments. 
         FIG.  2 A  illustrates an example of the digital transmission signal processing circuit (DTSPC) in  FIG.  1    according to at least one example embodiment. 
         FIG.  2 B  is a graph for explaining an operation of a supply modulator in  FIG.  1    according to at least one example embodiment. 
         FIG.  3 A  is a block diagram illustrating an example of a supply modulator according to some example embodiments. 
         FIG.  3 B  illustrates an ET reference signal and an average power signal provided to the main controller in  FIG.  3 A  according to at least one example embodiment. 
         FIG.  4    is a block diagram illustrating an example of the SIMO converter in the supply modulator in  FIG.  3 A  according to some example embodiments. 
         FIG.  5    is a block diagram illustrating an example of the SIMO converter of  FIG.  4    according to some example embodiments. 
         FIG.  6 A  illustrates a configuration of the first capacitor divider in the voltage dividing capacitor circuit in  FIG.  5    according to some example embodiments. 
         FIGS.  6 B and  6 C  illustrate operation of the first capacitor divider in  FIG.  6 A , respectively according to some example embodiments. 
         FIG.  7 A  is a circuit diagram illustrating an example of the voltage dividing capacitor circuit in the SIMO converter of  FIG.  5    according to some example embodiments. 
         FIG.  7 B  is a timing diagram illustrating operation of the SIMO converter of  FIG.  7 A  according to at least one example embodiment. 
         FIG.  7 C  illustrates operating frequencies of the first through third capacitor dividers based on currents provided to loads from the voltages nodes in the SIMO converter in  FIG.  7 A  according to at least one example embodiment. 
         FIG.  8 A  is a circuit diagram illustrating an example of the voltage dividing capacitor circuit in the SIMO converter of  FIG.  5    according to some example embodiments. 
         FIGS.  8 B and  8 C  illustrate operations of the second capacitor divider and the fourth capacitor divider in the voltage dividing circuit in  FIG.  8 A , respectively according to some example embodiments. 
         FIG.  9    is a block diagram illustrating an example of the SIMO converter of  FIG.  4    according to some example embodiments. 
         FIG.  10    is a block diagram illustrating an example of the SIMO converter of  FIG.  4    according to some example embodiments. 
         FIG.  11    is a circuit diagram illustrating an example of the voltage dividing capacitor circuit in the SIMO converter of  FIG.  10    according to some example embodiments. 
         FIG.  12    is a circuit diagram illustrating an example of the voltage dividing capacitor circuit in the SIMO converter of  FIG.  10    according to some example embodiments. 
         FIG.  13    is a block diagram illustrating an example of a supply modulator according to some example embodiments. 
         FIG.  14    is a block diagram illustrating an example of the SIMO converter in the supply modulator in  FIG.  13    according to some example embodiments. 
         FIG.  15    illustrates that the SIMO converter in  FIG.  14    drives two power amplifiers in ET-ET mode according to at least one example embodiment. 
         FIG.  16    illustrates that the SIMO converter in  FIG.  14    drives two power amplifiers in APT-APT mode according to at least one example embodiment. 
         FIG.  17 A  illustrates that the SIMO converter in  FIG.  14    drives two power amplifiers in ET-APT mode according to at least one example embodiment. 
         FIG.  17 B  illustrates waveforms of the output voltage according to a tracking mode in the SIMO converter in  FIG.  14    according to at least one example embodiment. 
         FIG.  18    is a circuit diagram illustrating a converter that employs two DC-DC converters according to some example embodiments. 
         FIG.  19    is a circuit diagram illustrating a converter that employs two DC-DC converters according to some example embodiments. 
         FIG.  20    is a circuit diagram illustrating an example of a voltage dividing capacitor circuit according to some example embodiments. 
         FIG.  21    is a circuit diagram illustrating an example of a voltage dividing capacitor circuit according to some example embodiments. 
         FIG.  22    is a circuit diagram illustrating an example of a voltage dividing capacitor circuit according to some example embodiments. 
         FIG.  23    is a circuit diagram illustrating an example of a voltage dividing capacitor circuit according to some example embodiments. 
     
    
    
     DETAILED DESCRIPTION 
     Various example embodiments will be described more fully hereinafter with reference to the accompanying drawings, in which some example embodiments are shown. 
       FIG.  1    is a block diagram illustrating a wireless communication device according to some example embodiments. 
     Referring to  FIG.  1   , a wireless communication device  10  may include a modem  40 , a supply modulator (SM)  100 , a radio frequency integrated circuit (RFIC)  60 , a power amplifier (PA)  90 , and/or an antenna ANT, but the example embodiments are not limited thereto, and for example, the wireless communication device  10  may include a greater or lesser number of constituent components. 
     The modem  40  may include a digital transmission signal processing circuit (DTSPC)  50 , a digital reception signal processing circuit (DRSPC)  40 , a digital-to-analog converter (DAC)  44 , an analog-to-digital converter (ADC)  45 , and/or a mobile industry processor interface (MIPI)  43 , but is not limited thereto. 
     The modem  40  may process a baseband signal BB_T including information to be transmitted, the information including an in-phase (I) signal and/or a quadrature phase (Q) signal, etc., based on a desired and/or predetermined communication protocol using the DTSPC  50 , but is not limited thereto. The modem  40  may process a received baseband signal BB_R based on a desired and/or predetermined communication protocol using the DRSPC  41 , but is not limited thereto. For example, the modem  40  may process a signal to be transmitted according to a communication scheme, such as orthogonal frequency division multiplexing (OFDM), orthogonal frequency division multiple access (OFDMA), wideband code multiple access (WCDMA), and/or high speed packet access+ (HSPA+), etc., but is not limited thereto. In addition, the modem  400  may process the baseband signal BB_T and/or BB_R according to and/or based on various types of communication schemes, e.g., radio access technologies (RATs), to which a technique of modulating the amplitude and frequency of a transmission signal is applied. 
     The modem  40  may extract at least one envelope of the baseband signal BB_T using the DTSPC  50 , and may generate at least one envelope signal ENV based on the extracted envelope. The modem  40  may generate an average power tracking (APT) signal APT_REF based on APT table stored in a memory (not illustrated), may generate an envelope tracking (ET) reference signal ET_REF based on the envelope signal ENV, and/or may provide the APT signal APT_REF and the ET reference signal ET_REF to the supply modulator  100  through the MIPI  43 , etc. The extracted envelope may correspond to an amplitude (e.g., the magnitude of the I signal and Q signal) of the baseband signal BB_T, but the example embodiments are not limited thereto. The modem  40  may generate a tracking mode signal TMS, etc. 
     The APT table may store information on desired and/or required power supply voltage of the power amplifier  90  based on expected (e.g., anticipated, configured, designed, desired, etc.) power of the antenna ANT and may store information on average power signal corresponding to the desired and/or required power supply voltage. When the expected power of the antenna ANT is determined, the modem  40  may generate the average power signal based on the APT table and may provide the APT signal APT_REF to the supply modulator  100 , etc. 
       FIG.  2 A  illustrates an example of the digital transmission signal processing circuit (DTSPC) in  FIG.  1    according to at least one example embodiment. 
     Referring to  FIG.  2 A , the DTSPC  50  may perform various operations through crest factor reduction (CFR)  51 , shaping function (SF)  52 , digital pre-distortion (DPD)  53 , a first delay (DELAY 1 )  54 , and/or a second delay (DELAY 2 )  55  in addition to processing the baseband signal, envelope extraction, and/or generation of digital envelope signal, etc., but the example embodiments are not limited thereto. The DTSPC  50  may further include a plurality of switches  56  and  57 , etc., but is not limited thereto. 
     The CFR  51  may reduce a PAPR of at least one transmission signal, for example, the baseband signal BB_T, etc., but not limited thereto. The SF  52  may shape the envelope signal ENV such that the efficiency and/or linearity of the power amplifier  90  is enhanced. The DPD  53  may compensate for distortion of the power amplifier  90  in a digital region (e.g., a digital domain, etc.). The first delay  54  may adjust a delay of the envelope signal ENV and the second delay  56  may adjust a delay of the baseband signal BB_T, but the example embodiments are not limited thereto. 
     The DTSPC  50  may output the envelope signal ENV and/or the baseband signal BB_T, etc. 
     The envelope signal ENV may be directly provided to the supply modulator  100  and/or may be provided to the supply modulator  100  via the MIPI  43 . The DVC  44  may convert the baseband signal BB_T to a transmission signal TX to be provided to a transmission circuit (TXC)  70 , but is not limited thereto. 
     Referring back to  FIG.  1   , the modem  40  may receive an analog reception signal RX from the RFIC  60 . The ADC  45  in the modem  40  may convert the reception signal RX to the baseband signal BB_R. The reception signal RX may be a differential signal, but is not limited thereto. 
     The RFIC  60  may generate a radio frequency (RF) input signal RF_IN by performing a frequency up-conversion on the transmission signal TX, and/or may generate a RF output signal RF_OUT by performing a frequency down-conversion on the reception signal RX. The RFIC  60  may include a transmission circuit  70  to perform the frequency up-conversion, a reception circuit  80  to perform the frequency down-conversion, and a local oscillator LO, etc., but the example embodiments are not limited thereto. Moreover, one or more of the transmission circuit  70 , reception circuit, and/or the local oscillator LO may be combined into a single circuit, etc. 
     The transmission circuit  70  may include a first analog baseband filter ABF 1   71 , a first mixer  73  and/or an amplifier (AMP)  75 , etc., but is not limited thereto. The ABF 1   71  may include a low pass filter, but is not limited thereto. The ABF 1   71  filters the transmission signal TX and provides the filtered transmission signal to the first mixer  73 . The first mixer  73  may mix a frequency from the local oscillator LO with the filtered transmission signal and may perform the frequency up-conversion on the transmission signal TX. The transmission signal TX may be provided to the AMP  75 , and the AMP  75  amplifies an output of the first mixer  73  and provide the RF input signal RF_IN to the power amplifier  90 , etc. 
     The power amplifier  90  may receive a supply voltage VCC from the supply modulator  100 , and amplifies the RF input signal RF_IN based on the supply voltage VCC to generate the RF output signal RF_OUT. The power amplifier  90  may provide the RF output signal RF_OUT to the duplexer  95 , but is not limited thereto. 
     The reception circuit  80  may include a second analog baseband filter ABF 2   85 , a second mixer  83 , and/or a low noise amplifier (LNA)  81 , etc., but the example embodiments are not limited thereto. The ABF 2   85  may include a low pass filter, but is not limited thereto. 
     The LNA  81  may amplify a RF reception signal RF_R received from the duplexer  95  to provide the amplified signal to the second mixer  83 , but is not limited thereto. The second mixer  83  may mix a frequency from the local oscillator LO with the amplified signal and may perform the frequency down-conversion on the mixed signal to generate the reception signal RX. The ABF 2  filters the reception signal RX and provides the filtered signal to the modem  40 . 
     In some example embodiments, the wireless communication device  10  may transmit at least one transmission signal through a plurality of frequency bands by using carrier aggregation (CA), but the example embodiments are not limited thereto. To this end, the wireless communication device  10  may include a plurality of power amplifiers for power-amplifying a plurality of RF input signals corresponding to a plurality of carriers, but is not limited thereto. However, one power amplifier  90  is illustrated in the wireless communication device  10  of the Figures for the convenience of explanation, and in one or more example embodiments, the wireless communication device  10  may include a plurality of power amplifiers, etc., to support carrier aggregation, etc. 
     The supply modulator  100  may generate the supply voltage VCC whose level is dynamically varied (e.g., changed, modified, etc.) based on the envelope signal ENV and the ET reference signal ET_REF in an ET mode, and may provide the supply voltage VCC to the power amplifier  90 . The supply modulator  100  may adjust the supply voltage VCC based on the average power signal APT_REF in an APT mode and may provide the supply voltage VCC to the power amplifier  90 . 
     The supply modulator  100  may generate a plurality of voltages having different levels, voltage levels, voltage values, etc., based on a battery voltage VBAT (e.g., the battery voltage VBAT may also be referred to as a power supply voltage, etc.), and may provide one of the plurality of voltages to the power amplifier  90  as the supply voltage VCC based on the envelope signal ENV when in the ET mode (e.g., the wireless communication device  10  and/or the DTSPC  50  is in the ET mode, etc.). The supply modulator  100  may select a voltage corresponding to a level (e.g., voltage level, voltage value, etc.) of the envelope signal ENV and may provide the selected voltage to the power amplifier  90  as the supply voltage VCC. 
     When a level (e.g., voltage level, etc.) of the envelope signal ENV is small (e.g., less than a desired voltage ENV threshold, etc.), the supply modulator  100  may provide a voltage having a small level (e.g., a first voltage level, a corresponding voltage level, etc.) to the power amplifier  90  as the supply voltage VCC. When a level of the envelope signal ENV is great (e.g., greater than the desired voltage ENV threshold, etc.), the supply modulator  100  may provide a voltage having a great level (e.g., a second voltage level, a corresponding voltage level, etc.) to the power amplifier  90  as the supply voltage VCC. Therefore, the supply modulator  100  may enhance the efficiency of power consumption of the wireless communication device  10  and/or the DTSPC  50  and may increase the length of battery use and/or increase the battery capacity of the wireless communication device  10 , etc. 
     The technique to adjust the level (e.g., voltage level) of the supply voltage adaptively based on the envelope signal ENV is referred to as ET. The ET according to some example embodiments may be referred to as a discrete ET because a voltage having a level which is most similar with a level of the envelope signal ENV is selected, but the example embodiments are not limited thereto. 
     The supply modulator  100  may select ET and/or APT based on a selected transmission power set in a communication device including the supply modulator  100 , but the example embodiments are not limited thereto. Hereinafter, the example embodiments will be described assuming the supply modulator  100  performs ET operation for the sake of brevity and clarity, but the example embodiments are not limited thereto, and the operation of the supply modulator  100  may apply equally to APT operation as well. 
     The duplexer  95  is coupled to the antenna ANT and may separate a transmission frequency and/or a reception frequency, but the example embodiments are not limited thereto. The duplexer  95  may divide the RF output signal RF_OUT according to frequency bands and may provide the RF output signal RF_OUT to a corresponding antenna ANT. The duplexer  95  may provide the LNA  81  in the reception circuit  80  of the RFIC  60  with a signal received from the antenna ANT. 
     According to some example embodiments, the wireless communication device may include at least one switch to separate a transmission frequency and/or a reception frequency instead of the duplexer  65 , but is not limited thereto. According to other example embodiments, the wireless communication device may include both a switch and a duplexer, etc. 
     The antenna ANT may transmit the RF output signal RF_OUT whose frequency is separated to an outside (e.g., may transmit the RF output signal RF_OUT to an external device) and/or may provide the RF reception signal RF_R from the outside (e.g., external source, etc.) to the duplexer  95 . The antenna ANT may include an array antenna, etc., but is not limited thereto. 
       FIG.  2 B  is a graph for explaining an operation of a supply modulator in  FIG.  1    according to at least one example embodiment. 
     Referring to  FIG.  2 B , the supply modulator  100  may modulate the supply voltage VCC to be provided to the power amplifier  90 , based on the envelope signal ENV by using DC voltages having different voltage levels. In other words, the supply modulator  100  may generate the supply voltage VCC to have different voltage levels based on the envelope signal ENV. The supply voltage VCC provided to the power amplifier  90  may be referred to as a bias voltage. 
       FIG.  3 A  is a block diagram illustrating an example of a supply modulator according to some example embodiments. 
     Referring to  FIG.  3 A , a supply modulator  100   a  may include a main controller  110 , a discrete level (DL) controller  120 , a switch controller  130 , a switch array  140   a , and/or a single inductor multiple output (SIMO) converter  200 , etc., but the example embodiments are not limited thereto. According to some example embodiments, the supply modulator  100   a  may be implemented as processing circuitry, or in other words, processing circuitry included in the supply modulator  100   a  may be capable of performing the functionality of one or more of the supply modulator  100   a , main controller  110 , DL controller  120 , switch controller  130 , switch array  140   a , and/or SIMO converter  200 , etc. The processing circuitry may include hardware, such as processors, processor cores, logic circuits, storage devices, etc.; a hardware/software combination such as at least one processor core executing software and/or executing any instruction set, etc.; or a combination thereof. For example, the processing circuitry more specifically may include, but is not limited to, a field programmable gate array (FPGA), a programmable logic unit, an application-specific integrated circuit (ASIC), a System-on-Chip (SoC), etc. 
     The main controller  110  may receive the tracking mode signal TMS, the average power signal ART_REF, and/or the ET reference signal ET_REF from the modem  40  in  FIG.  1   , and may determine a tracking mode of the supply modulator  100   a  based on the tracking mode signal TMS, etc., but is not limited thereto. Additionally, the main controller  110  may generate a plurality of reference voltages VREF 1 ˜VREFn (where n is an integer greater than one) based on the ET reference signal ET_REF in the ET mode, and may provide the plurality of reference voltages VREF 1 ˜VREFn to the SIMO converter  200 , but is not limited thereto. The main controller  110  may control the discrete level controller  120 , the switch controller  130  and/or the SIMO converter  200 , etc. 
     The SIMO converter  200  may generate a plurality of voltages V 1 ˜Vn based on the battery voltage VBAT under control of and/or based on instructions from the main controller  110 , and may provide the plurality of voltages V 1 ˜Vn to the switch array  140   a . The SIMO converter  200  may generate the plurality of voltages V 1 ˜Vn having different levels (e.g., voltage levels, voltage values, etc.) based on the plurality of reference voltages VREF 1 ˜VREFn and the battery voltage VBAT and may output the plurality of voltages V 1 ˜Vn to the switch array  140   a.    
     The switch array  140   a  may include a plurality of switches S 1 ˜Sn corresponding to the plurality of voltages V 1 ˜Vn having different levels (e.g., voltage levels, etc.). The opening and/or closing operation of the plurality of switches S 1 ˜Sn may be controlled by and/or based on a switch control signal SWC provided from the switch controller  130 . The switch array  140   a  may select one or more voltages among the plurality of voltages V 1 ˜Vn having different levels based on the switch control signal SWC, and may provide the selected voltage(s) to the power amplifier  90 , but is not limited thereto. 
     The discrete level controller  120  may generate a level control signal ENV_LV including envelope level information based on the envelope signal ENV from the modem  40 . The discrete level controller  120  may provide the level control signal ENV_LV to the switch controller  130 , but is not limited thereto. 
     The switch controller  130  may receive the level control signal ENV_LV from the discrete level controller  120 , and may control on/off (e.g., the opening and/or closing) of one or more of the plurality of switches S 1 ˜Sn based on the level control signal ENV_LV. The switch controller  130  may generate the switch control signal SWC for controlling on/off of one or more of the plurality of switches S 1 ˜Sn and may provide the switch control signal SWC to the switch array  140   a.    
     In the ET mode, the switch controller  130  may select a voltage corresponding to a level (e.g. voltage level, etc.) of the envelope signal ENV among the plurality of voltages V 1 ˜Vn having different levels and may control the on/off (e.g., control the operation) of the plurality of switches S 1 ˜Sn such that the selected voltage is provided to the power amplifier  90 . In addition, in the APT mode, the switch controller  130  may control at least one of the plurality of switches S 1 ˜Sn such that a voltage having a nearest level (e.g., closest voltage level) with a desired and/or required level and/or a greater level than the desired and/or required level among the plurality of voltages V 1 ˜Vn is selected, but the example embodiments are not limited thereto. 
     In some example embodiments, the supply modulator  100   a  may further include at least one switch Sa, and the switch Sa may provide the power amplifier  90  with an APT voltage APT_V provided from the SIMO converter  200  based on the average power signal APT_REF in the APT mode. The switch controller  130  may turn on the switch Sa in the APT mode, and may turn off the switch Sa in the ET mode, by applying a switch control signal SWCa to the switch Sa, but the example embodiments are not limited thereto. In the APT mode, the switch controller  130  may turn off the plurality of switches S 1 ˜Sn. 
     Although not illustrated, either in the ET mode or in the APT mode, the switch array  140   a  may connect a load capacitor corresponding to the controlled switch among load capacitors coupled to a plurality of voltage nodes in the SIMO converter  200  to the power amplifier  90 . The load capacitor corresponding to the controlled switch may serve as a decoupling capacitor connected to the supply voltage VCC, but the example embodiments are not limited thereto. 
       FIG.  3 B  illustrates an ET reference signal and an average power signal provided to the main controller in  FIG.  3 A  according to at least one example embodiment. 
     Referring to  FIG.  3 B , the ET reference signal ET_REF may include a plurality of reference signals, e.g., ET_VO 1 , ET_VO 2 , ET_VO 3 , and/or ET_VO 4 , etc., corresponding to levels (e.g., voltage levels, etc.) of the envelope signal ENV, and the average power signal APT_REF may include average power voltages, e.g., APT_VO 1  and/or APT_VO 2 , etc. 
       FIG.  4    is a block diagram illustrating an example of the SIMO converter in the supply modulator in  FIG.  3 A  according to some example embodiments. 
     Referring to  FIG.  4   , the SIMO converter  200  may include a DC-DC converter  210  and/or a voltage dividing capacitor circuit  300 , etc., but is not limited thereto. The SIMO converter  200  may further include a comparator block  220 , a power switch control signal generator (PSCSG)  230 , and/or a phase control signal generator (PCSG)  235 , etc., but is not limited thereto. 
     The comparator block  220  may include a plurality of comparators, e.g., comparators  221 ,  22 , . . . ,  22   n  that compare each of a plurality of voltages, e.g., voltages V 1 , Va, V 2 , Vb and Vn, etc., output from the voltage dividing capacitor circuit  300  with respect to one of the plurality of reference voltages VREF 1 ˜VREFn. The comparator block  220  may generate and/or output a plurality of comparison signals, e.g., CS 1 , CS 2 , . . . , CSn, etc., based on the results of the comparisons. 
     The PSCSG  230  may generate a first set of switch control signals SCS based on a first comparison signal CS 1  associated with the first voltage V 1  and a second comparison signal CS 2  associated with the second voltage V 2  among the plurality of comparison signals CS 1 , CS 2 , . . . , CSn. The PSCSG  230  may provide the first set of switch control signal SCS to the DC-DC converter  210 . 
     The PCSG  235  may generate a phase control signal PCS based on the plurality of comparison signals CS 1 , CS 2 , . . . , CSn and may provide the phase control signal PCS to the voltage dividing capacitor circuit  300 . 
     The DC-DC converter  210  may include an inductor (L)  211  connected to the battery voltage VBAT to store energy, and the DC-DC converter  210  may transfer a current based on the battery voltage VBAT to at least one of a first voltage node VN 1  and/or a second voltage node VN 2  between the first voltage node VN 1  and/or a ground node VN connected to a ground voltage, in response to the first set of power switch control signal SCS. 
     The voltage dividing circuit  300  may include a plurality of capacitor dividers (each of the capacitor dividers may be referred to as a capacitor voltage divider that divides a voltage with a ratio greater than one or smaller than one using at least one capacitor), such as, CD 1 , CD 2 , CD 3 , . . . , etc., which are connected between the first voltage node VN 1 , the second voltage node VN 2  and the ground node GN. Each of the plurality of capacitor dividers CD 1 , CD 2 , CD 3 , . . . , etc., may perform one of a voltage boosting operation and a voltage drop operation, individually, in response to receiving a phase control signal set. The voltage dividing circuit  300  may output the plurality of voltages V 1 , Va, V 2 , Vb, and Vn, etc., at the first voltage node VN 1 , the second voltage node VN 2  and intermediate voltage nodes IVNa, and IVNb between the first voltage node VN 1  and the second voltage node VN 2 , and between the second voltage node VN 2  and the ground node GN, but are not limited thereto. 
     The DC-DC converter  210  may include the inductor  211 , first through third power switches SW 1 , SW 2  and SW 3 , a first load capacitor CL 1  and/or a second load capacitor CL 2 , but the example embodiments are not limited thereto. 
     The inductor  211  is connected between the battery voltage VBAT and a first switching node SN 1 , and stores energy when a current based on the battery voltage VBAT flows through the inductor  211 . 
     The first power switch SW 1  may be connected between the first switching node SN 1  and the first voltage node VN 1 , and may transfer the energy stored in the inductor  211  to the first voltage node VN 1  in the form of current in response to a first switch control signal SCS 1 . The second power switch SW 2  may be connected between the first switching node SN 1  and the second voltage node VN 2 , and may transfer the energy stored in the inductor  211  to the second voltage node VN 2  in the form of current in response to a second switch control signal SCS 2 . 
     The third power switch SW 3  may be connected between the first switching node SN 1  and the ground node GN, and may couple the first switching node SN 1  to the ground node GN in response to a third switch control signal SCS 3 . When a level of the battery voltage VBAT is smaller than or equal to a voltage level of the second voltage node VN 2 , the third power switch SW 3  may perform a current build-up operation by coupling the first switching node SN 1  to the ground voltage. 
     In some example embodiments, the first power switch SW 1  may include a p-channel metal-oxide semiconductor (PMOS) transistor, the second power switch SW 2  may include an n-channel metal-oxide semiconductor (NMOS) transistor and the third power switch SW 3  may include an NMOS transistor, however the example embodiments are not limited thereto. 
       FIG.  5    is a block diagram illustrating an example of the SIMO converter of  FIG.  4    according to some example embodiments. 
       FIG.  5    illustrates an example in which a SIMO converter  200   a  generates four output voltages, but is not limited thereto, and may generate a greater or lesser number of output voltages. 
     Referring to  FIG.  5   , the SIMO converter  200   a  may include the DC-DC converter  210 , a voltage dividing capacitor circuit  300   a , a comparator block  220   a , PSCSG  230   a  and/or a PCSG  235   a , etc. 
     The DC-DC converter  210  may be the same as the DC-DC converter  210  in  FIG.  4   , and duplicate description with  FIG.  4    will be omitted. 
     The comparator block  220   a  may include a plurality of comparators  221 ,  222 ,  223  and  224 , etc., that compare each of a plurality of voltages V 1 , V 2 , V 3  and V 4 , etc., with respective one of a plurality of reference voltages VREF 1 , VREF 2 , VREF 3  and VREF 4 , etc., and the comparator block  220   a  may generate and/or output a plurality of comparison signals CS 11 , CS 12 , CS 13  and CS 14 , etc., based on the results of the comparisons. 
     The PSCSG  230   a  may generate a first set of switch control signals SCSa based on a first comparison signal CS 11  and a second comparison signal CS 12 , and may provide the first set of switch control signals SCSa to the DC-DC converter  210 . The first set of switch control signals SCSa may include switch control signals SCS 1 , SCS 2  and SCS 3 , but is not limited thereto. 
     The PCSG  235   a  may generate a phase control signal PCSa based on the plurality of comparison signals CS 1 , CS 2 , CS 3  and CS 4 , etc., and may provide the phase control signal PCSa to the voltage dividing capacitor circuit  300   a.    
     The voltage dividing circuit  300   a  may include first through third capacitor dividers  310 ,  320  and  330 , but is not limited thereto. 
     The first capacitor divider  310  may be connected between a first voltage node VN 1  coupled to a first load capacitor CL 1 , a second voltage node VN 2  coupled to a second load capacitor CL 2 , and the ground node GN, but is not limited thereto. The second capacitor divider  320  may be connected between the first voltage node VN 1 , a first intermediate voltage node IVN 1 , and the second voltage node VN 2 , but is not limited thereto. The third capacitor divider  330  may be connected between the second voltage node VN 2 , a second intermediate voltage node IVN 2  and the ground node GN, but is not limited thereto. The first intermediate voltage node IVN 1  may be coupled to a third load capacitor CL 3  connected to the ground voltage and the second intermediate voltage node IVN 2  may be coupled to a fourth load capacitor CL 4  connected to the ground voltage, but the example embodiments are not limited thereto. 
     When the DC-DC converter  210  generates (and/or, provides) a first voltage V 1  to the first voltage node VN 1  coupled to the first load capacitor CL 1  through the first power switch SW 1 , the first capacitor divider  310  may provide a second voltage V 2  based on the first voltage V 1  at the second voltage node VN 2 . The second voltage V 2  may correspond to a desired percentage of the first voltage V 1 , for example, a half (e.g., one half, 50%, etc.) of the first voltage V 1 , but is not limited thereto. When the level of the battery voltage VBAT is smaller than or equal to the second voltage V 2 , the DC-DC converter  210  may supply the first voltage V 1  to the first voltage node VN 1  through the first power switch SW 1 . The PSCSG  230   a  may determine a level (e.g., voltage level) of the battery voltage VBAT based on the first comparison signal CS 11  and the second comparison signal CS 12 , etc. 
     The second voltage divider  320  may provide (and/or output) a third voltage at the first intermediate voltage node IVN 1  based on the first voltage V 1  and the second voltage V 2 , but is not limited thereto. The third voltage V 3  may correspond to a desired percentage of a sum of the first voltage V 1  and second voltage V 2 , for example, a half of a sum of the first voltage V 1  and the second voltage V 2 , but the example embodiments are not limited thereto. The third capacitor divider  330  may provide (and/or, output) a fourth voltage V 4  based on the second voltage V 2  to the second intermediate voltage node IVN 2 . The fourth voltage V 4  may correspond to a desired percentage of the second voltage V 2 , for example, a half of the second voltage V 2 , but is not limited thereto. 
     Therefore, the voltage dividing capacitor circuit  300   a  may output voltages corresponding to, e.g., V 1 , (3/4)*V 1 , (2/4)*V 1  and (1/4)*V 1  at the first voltage node VN 1 , the intermediate voltage node IVN 1 , the second node VN 2  and the second intermediate voltage node IVN 2 , respectively, but is not limited thereto. The voltages corresponding to V 1 , (3/4)*V 1 , (2/4)*V 1  and (1/4)*V 1  have different levels (e.g., voltage levels). 
     When the DC-DC converter  210  generates (and/or, provides) the second voltage V 2  to the second voltage node VN 2 , the first capacitor divider  310  may provide the first voltage V 1  to the first voltage node VN 1  based on the second voltage V 2 , etc. 
     The DC-DC converter  210  may provide a voltage to one or more of the first voltage node VN 1  and the second voltage node VN 2 , and the voltage dividing capacitor circuit  300   a  may generate a voltage at another node based on the voltage which is generated by the DC-DC converter  210  and is provided to at one node. 
       FIG.  6 A  illustrates a configuration of the first capacitor divider in the voltage dividing capacitor circuit in  FIG.  5    according to some example embodiments. 
       FIGS.  6 B and  6 C  illustrate operation of the first capacitor divider in  FIG.  6 A , respectively according to some example embodiments. 
     Referring to  FIG.  6 A , the first capacitor divider  310  may include a plurality of transistors, e.g., transistors  311 ,  312 ,  313  and  314 , etc., connected in series between the first voltage node VN 1  and the ground node GN, and a flying capacitor CF connected between a node N 11  and a node N 12 , etc. According to at least one example embodiment, the flying capacitor CF may be connected in parallel to one or more transistors, such as the transistors  312  and/or  313 , etc., but the example embodiments are not limited thereto. Each of the transistors  311 ,  312 ,  313  and  314  may be referred to as a switch. 
     The transistor  311  is connected between the first voltage node VN 1  and the node N 11 , the transistor  312  is connected between the node N 11  and the second voltage node VN 2 , the transistor  313  is connected between the second voltage node VN 2  and the node N 12  and the transistor  314  is connected between the second voltage node VN 2  and the ground node GN, etc. 
     As illustrated in  FIG.  6 B , when the transistors  311  and  313  are turned on and the transistors  312  and  314  are turned off in response to first state of phase control signals Φ 1  and Φ 1 B, the first capacitor divider  310  stores, in the flying capacitor CF, a voltage corresponding to a difference between the first voltage V 1  and the second voltage V 2 , but is not limited thereto. In this case, a relationship of a voltage VCF stored in the flying capacitor CF, the first voltage V 1  and the second voltage V 2  may be represented as VCF=V 1 −V 2 , but the example embodiments are not limited thereto. 
     As illustrated in  FIG.  6 C , when the transistors  311  and  313  are turned off and the transistors  312  and  314  are turned on in response to second state of the phase control signals Φ 1  and Φ 1 B, the voltage stored in the flying capacitor CF is provided to the second voltage node VN 2  and is stored in the second load capacitor CL 2  coupled to the second voltage node VN 2 . 
     In this case, a relationship between the voltage VCF and the second voltage V 2  is represented as VCF=V 2 . Therefore, a representation of V 1 −V 2 =V 2  then V 2 =(1/2)*V 1 , but the example embodiments are not limited thereto. 
     When the DC-DC converter  210  provides the first voltage V 1  to the first voltage node VN 1  through the first power switch SW 1 , the first capacitor divider  310  performs a voltage drop operation based on the first voltage V 1  in response to the phase control signals. The DC-DC converter  210  then outputs the second voltage V 2  to the second voltage node VN 2 . In addition, when the DC-DC converter  210  provides the second voltage V 2  to the second voltage node VN 2  through the second power switch SW 2 , the first capacitor divider  310  performs a voltage boosting operation based on the second voltage V 2  in response to the phase control signals and outputs the first voltage V 1  at the first voltage node VN 1 . 
     Therefore, the SIMO converter  200   a  may rapidly generate and/or provide a current to a target voltage node that desires and/or needs to supply a load current through the plurality of capacitor dividers, e.g., capacitor dividers  310 ,  320  and  330 , etc., and thus a response characteristic of the SIMO converter  200   a  is fast. In addition, the SIMO converter  200   a  may increase, maintain and/or prevent efficiency from being reduced, because a number of capacitors from the DC-Dc converter  200  to the target node is smaller than a number of capacitors in a SIMO converter in which capacitor dividers are sequentially connected. In addition, since each of the plurality of capacitor dividers  310 ,  320  and  330  may be controlled based on individual phase control signals, the switching loss may be reduced. In addition, since each of the voltage nodes is coupled to the ground voltage via a corresponding load capacitor, effective capacitance increases and the ripple characteristic of the SIMO converter  200   a  may be enhanced. 
       FIG.  7 A  is a circuit diagram illustrating an example of the voltage dividing capacitor circuit in the SIMO converter of  FIG.  5    according to some example embodiments. 
     In  FIG.  7 A , the DC-DC converter  210  is illustrated together for the convenience of explanation, but the example embodiments are not limited thereto. 
     Referring to  FIG.  7 A , the voltage dividing circuit  300   a  may include the first through third capacitor dividers  310 ,  320  and  330 , but is not limited thereto. 
     The first capacitor divider  310  may include a plurality of transistors  311 ,  312 ,  313  and  314 , etc., connected in series between the first voltage node VN 1  and the ground node GN, and a flying capacitor CF connected between a node N 11  and a node N 12 . According to some example embodiments, the flying capacitor CF may be in parallel to one or more transistors, e.g., transistors  312  and/or  313 , etc., but the example embodiments are not limited thereto. 
     The transistor  311  is connected between the first voltage node VN 1  and the node N 11 , the transistor  312  is connected between the node N 11  and the second voltage node VN 2 , the transistor  313  is connected between the second voltage node VN 2  and the node N 12 , and the transistor  314  is connected between the second voltage node VN 2  and the ground node GN, but the example embodiments are not limited thereto. 
     Each gate of the transistors  311  and  313  receives a first phase control signal Φ 1 , and each gate of the transistors  312  and  314  receives a first inversion phase control signal Φ 1 B which has a phase difference of 180 degrees with respect to the first phase control signal Φ 1 , but is not limited thereto. When the transistors  311  and  313  are turned on, and the transistors a 312  and  314  are turned off, the first capacitor divider  310  stores, in the flying capacitor CF, a voltage corresponding to a difference between the first voltage V 1  and the second voltage V 2 . When the transistors  311  and  313  are turned off, and the transistors  312  and  314  are turned, the voltage stored in the flying capacitor CF is provided to the second voltage node VN 2  and is stored in the second load capacitor CL 2 , but is not limited thereto. 
     The second capacitor divider  320  may include a plurality of transistors, e.g.,  321 ,  322 ,  323  and  324 , etc., connected in series between the first voltage node VN 1  and the second voltage node VN 2 , and a flying capacitor CF connected between a node N 21  and a node N 22 . According to some example embodiments, the flying capacitor CF may be connected in parallel to one or more transistors, e.g., transistors  322  and/or  323 , etc., but the example embodiments are not limited thereto. Each gate of the transistors  321  and  323  receives a second phase control signal Φ 2 , and each gate of the transistors  322  and  324  receives a second inversion phase control signal Φ 2 B which has a phase difference of 180 degrees with respect to the second phase control signal Φ 2 , but the example embodiments are not limited thereto. 
     As described with reference to  FIGS.  6 B and  6 C , the second capacitor divider  320  may provide the third voltage V 3  based on the first voltage V 1  and the second voltage V 2 , in response to the second phase control signal Φ 2  and the second inversion phase control signal Φ 2 B, etc. 
     The third capacitor divider  330  may include a plurality of transistors, e.g.,  331 ,  332 ,  333  and  334 , etc., connected in series between the second voltage node VN 2  and the ground node GN, and a flying capacitor CF connected between a node N 31  and a node N 32 , etc. According to some example embodiments, the flying capacitor CF may be connected in parallel to one or more transistors, e.g., transistors  332  and/or  333 , etc., but the example embodiments are not limited thereto. Each gate of the transistors  331  and  333  receives a third phase control signal Φ 3 , and each gate of the transistors  332  and  334  receives a third inversion phase control signal Φ 3 B which has a phase difference of 180 degrees with respect to the third phase control signal Φ 3 , but the example embodiments are not limited thereto. 
     As described with reference to  FIGS.  6 B and  6 C , the third capacitor divider  330  may provide the fourth voltage V 4  based on the second voltage V 2 , in response to the third phase control signal Φ 3  and the third inversion phase control signal Φ 3 B, but is not limited thereto. 
     When the DC-DC converter  210  provides current to the first voltage node VN 1  and the second voltage node VN 2 , the second capacitor divider  320  generates the third voltage V 3  based on the first voltage V 1  and the second voltage V 2 , and the second capacitor divider  320  provides the third voltage V 3  to the first intermediate voltage node IVN 1 . In addition, while the second capacitor divider  320  generates the third voltage V 3 , the third capacitor divider  330  generates the fourth voltage V 4  based on the second voltage V 2 , and provides the fourth voltage V 4  to the second intermediate voltage node IVN 2 . In this case, the current provided to the first voltage node VN 1  and the second voltage node VN 2  via the first power switch SW 1  and the second power switch SW 2  has a magnitude corresponding to, for example, a half of a magnitude of current provided to either the first voltage node VN 1  or the second voltage node VN 2  through one current path and efficiency of the SIMO converter  300   a  may increase by four times, but the example embodiments are not limited thereto. 
     When the DC-DC converter  210  performs a converting operation (e.g., conversion operation) using the first power switch SW 1  and the third power switch SW 3 , the DC-DC converter  210  may increase a magnitude of current provided to the first voltage node VN 1  by performing a current build-up operation using the inductor  211 . In this case, the first capacitor divider  310  generates the second voltage V 2  based on the first voltage V 1 . In addition, the second capacitor divider  320  generates the third voltage V 3  based on the first voltage V 1  and the second voltage V 2 , and provides the third voltage V 3  to the first intermediate voltage node IVN 1 . In addition, while the second capacitor divider  320  generates the third voltage V 3 , the third capacitor divider  330  generates the fourth voltage V 4  based on the second voltage V 2 , and provides the fourth voltage V 4  to the second intermediate voltage node IVN 2 . 
     When the second power switch SW 2  and the third power switch SW 3  are turned on in the DC-DC converter  210 , the DC-DC converter  210  performs a current build-up operation using the inductor  211 . Additionally, the first capacitor divider  310  and the third capacitor divider  330  generate the first voltage V 1  and the third voltage V 3  based on the second voltage V 2 , respectively. In this case, the SIMO converter  300   a  may increase efficiency of the entire circuit by reducing the amount of current from the battery voltage VBAT. 
     When the level of the battery voltage VBAT is smaller than the level of the second voltage V 2  and/or when the battery voltage VBAT is not enough (e.g., the battery voltage VBAT does not meet a desired threshold voltage and/or the power demands of the electronic device, etc.), the first power switch SW 1 , the second power switch SW 2  and the third power switch SW 3  may be turned on in the DC-DC converter  210 . In this case, the second capacitor divider  320  generates the third voltage V 3  based on the first voltage V 1  and the second voltage V 2 , and provides the third voltage V 3  to the first intermediate voltage node IVN 1 . In addition, while the second capacitor divider  320  generates the third voltage V 3 , the third capacitor divider  330  generates the fourth voltage V 4  based on the second voltage V 2 , and provides the fourth voltage V 4  to the second intermediate voltage node IVN 2 , but the example embodiments are not limited thereto. 
       FIG.  7 B  is a timing diagram illustrating operation of the SIMO converter of  FIG.  7 A  according to at least one example embodiment. 
     Referring to  FIG.  7 B , the battery voltage VBAT and the plurality of reference voltages VREF 1 , VREF 2 , VREF 3  and VREF 4  are illustrated, but the example embodiments are not limited thereto.  FIG.  7 B  illustrates a case when the DC-DC converter  210  provides current to the first voltage node VN 1  and the second voltage node VN 2 , and the second capacitor divider  320  and the third capacitor divider  330  generates the third voltage V 3  and the fourth voltage V 4 , respectively, but the example embodiments are not limited thereto. 
     When the reference voltage VREF 1  begins to increase at time t 1  and reaches a constant level at time t 2 , each of the first through fourth voltages V 1 , V 2 , V 3  and V 4  reaches a constant level at time t 2  and the constant level is maintained until time t 3 . Therefore, the operating frequencies of the phase control signals Φ 1 , Φ 2  and Φ 3  are constant from times t 1  to t 3 , but the example embodiments are not limited thereto. When the level of the third voltage V 3  decreases at time t 3  due to a load current provided to a load from the first intermediate voltage node IVN 1  increasing at time t 3 , the operating frequencies of the phase control signals Φ 1 , Φ 1 B, Φ 2  and Φ 2 B applied to the capacitor divider  310  and the second capacitor divider  320  associated with the third voltage V 3  increase. 
     Accordingly, the level of the third voltage V 3  increase from time t 3  to time t 5 . The operating frequencies of the phase control signals Φ 1 , Φ 1 B, Φ 2  and Φ 2 B applied to the capacitor divider  310  and the second capacitor divider  320  decrease from time t 4  to time t 5 , at which the level of the third voltage V 3  becomes greater than a level of the reference voltage VREF 3 . Therefore, the level of the third voltage V 2  stops increasing at time t 6  and converges to the reference voltage VREF 3 . When a voltage at the load capacitor varies based on a magnitude of the load current, the SIMO converter  200   a  may cope with the change of the voltage by increasing or decreasing a frequency of a phase control signal applied to the corresponding capacitor divider. The interval from time t 6  to time t 7  is similar with the interval from time t 4  to time t 5 , etc. 
       FIG.  7 C  illustrates operating frequencies of the first through third capacitor dividers based on currents provided to loads from the voltages nodes in the SIMO converter in  FIG.  7 A  according to at least one example embodiment. 
     In  FIG.  7 C , a reference numeral  411  illustrates a magnitude of a current Io provided to a load from the first voltage node VN 1 , and associated operating frequencies of the phase control signal Φ 1  applied to the first capacitor divider  310 , and the phase control signal Φ 2  applied to the second capacitor divider  320 . A reference numeral  412  illustrates a magnitude of a current Io provided to a load from the second voltage node VN 2  and associated operating frequency of the phase control signal Φ 1  applied to the first capacitor divider  310 . A reference numeral  413  illustrates a magnitude of a current Io provided to a load from the first intermediate voltage node IVN 1  and associated operating frequencies of the phase control signal Φ 1  applied to the first capacitor divider  310  and the phase control signal Φ 2  applied to the second capacitor divider  320 . A reference numeral  414  illustrates a magnitude of a current Io provided to a load from the second intermediate voltage node IVN 2  and associated operating frequencies of the phase control signal Φ 1  applied to the first capacitor divider  310  and the phase control signal Φ 3  applied to the third capacitor divider  330 . 
     Referring to  FIG.  7 C , it is noted that the operating frequency of a corresponding capacitor divider increases when a load current increases, the load current consumed by a load connected to each of the first voltage node VN 1 , the second voltage node VN 2 , the first intermediate voltage node IVN 1  and the second intermediate voltage node IVN 2  at which one of the first through fourth voltages V 1 , V 2 , V 3  and V 4 , respectively, is provided. 
       FIG.  8 A  is a circuit diagram illustrating an example of the voltage dividing capacitor circuit in the SIMO converter of  FIG.  5    according to some example embodiments. 
     In  FIG.  8 A , the DC-DC converter  210  is illustrated together with the voltage dividing circuit  300   b  for the sake of brevity and convenience of explanation, but the example embodiments are not limited thereto and other DC-DC converter designs may be implemented. 
     A voltage dividing circuit  300   b  in  FIG.  8 A  differs from the voltage dividing circuit  300   a  in  FIG.  7 A  in that the voltage dividing circuit  300   b  further includes at least a fourth capacitor divider  320   b , but is not limited thereto. 
     The fourth capacitor divider  320   b  may be connected between the first voltage node VN 1  and the second voltage node VN 2  in parallel with the second capacitor divider  320 , and may include a plurality of transistors  321   b ,  322   b ,  323   b  and  324   b , etc., connected in series between the first voltage node VN 1  and the second voltage node VN 2 , and a flying capacitor CF connected between a node N 21   b  and a node N 22   b . According to some example embodiments, the flying capacitor CF may be connected in parallel to one or more transistors, e.g., transistors  322   b  and/or  323   b , etc., but the example embodiments are not limited thereto. Each gate of the transistors  321   b  and  323   b  receives the second inversion phase control signal Φ 2 B, and each gate of the transistors  322  and  324  receives the second phase control signal Φ 2 . 
       FIGS.  8 B and  8 C  illustrate operations of the second capacitor divider and the fourth capacitor divider in the voltage dividing circuit in  FIG.  8 A , respectively, according to some example embodiments. 
     Referring to  FIGS.  8 B and  8 C , the second capacitor divider  320  and the fourth capacitor divider  320   b  may operate complementarily in response to the second phase control signal Φ 2  and the second inversion phase control signal Φ 2 B, and may provide additional current to the first intermediate voltage node IVN 1  when a current provided to the load from the first intermediate voltage node IVN 1  increases. When a current provided to the load from the first intermediate voltage node IVN 1  increases, additional current is desired and/or needs to be provided to the first intermediate voltage node IVN 1 . When the fourth capacitor divider  320   b  supplies the additional current to the first intermediate voltage node IVN 1 , each of the second capacitor divider  320  and the fourth capacitor divider  320   b  provide a desired percentage, such as half of current, to be provided to the intermediate voltage node IVN 1  and thus transient response becomes fast and power consumption may be reduced. 
       FIG.  9    is a block diagram illustrating an example of the SIMO converter of  FIG.  4    according to some example embodiments. 
     Referring to  FIG.  9   , a SIMO converter  200   b  may include a DC-DC converter  210   b , a voltage dividing capacitor circuit  300   b , a comparator block  220   a , a PSCSG  230   c , and/or a PCSG  235   a , etc., but the example embodiments are not limited thereto. 
     The SIMO converter  200   b  of  FIG.  9    differs from the SIMO converter  200   b  of  FIG.  9    in the DC-DC converter  210   b  and the PSCSG  230   c.    
     The PSCSG  230   c  may generate a first set of switch control signal SCSb based on a first control signal CTL 1  received from the modem  40 , the first comparison signal CS 11 , and the second comparison signal CS 12  received from the comparator block  220   a . The PSCSG  230   c  may provide the first set of switch control signal SCSb to the DC-DC converter  210   b . The first set of switch control signal SCSb may include switch control signals SCS 1 , SCS 2 , SCS 3 , SCS 4  and SCS 5 , etc., but is not limited thereto. The first control signal CTL 1  may designate an operation mode of the DC-DC converter  210   b , e.g., the operation mode may be one of a buck mode or a boost mode, etc. 
     The DC-DC converter  210   b  may include an inductor  211 , first through fifth power switches SW 1 , SW 2 , SW 3 , SW 4  and SW 5 , a first load capacitor CL 1  and a second load capacitor CL 2 , but is not limited thereto. 
     The inductor  211  may be connected between a first switching node SN 1  and a second switching node SN 2 , but is not limited thereto. The first power switch SW 1  may be connected between the first switching node SN 1  and the first voltage node VN 1 . The second power switch SW 2  may be connected between the first switching node SN 1  and the second voltage node VN 2 . The third power switch SW 3  may be connected between the first switching node SN 1  and the ground node GN. The fourth power switch SW 4  may be connected between the second switching node SN 2  and the battery voltage VBAT, and may have a gate to receive a fourth switch control signal SCS 4 . The fifth power switch SW 5  may be connected between the second switching node SN 2  and the ground node GN, and may have a gate to receive a fifth switch control signal SCS 5 . 
     In the SIMO converter  200   b  of  FIG.  9   , the DC-DC converter  210   b  further includes the fourth power switch SW 4  and the power switch SW 5 , and the DC-DC converter  210   b  may operate either in a buck mode in which the DC-DC converter  210   b  generates a voltage whose level is smaller than a level of the battery voltage VBAT, or in a boost mode in which the DC-DC converter  210   b  generates a voltage whose level is greater than a level of the battery voltage VBAT. 
     When a voltage equal to or smaller than the second voltage V 2  is to be used, the DC-DC converter  210   b  operates in the buck mode by turning on the second power switch SW 2 , and a battery current provided to the first voltage node VN 1  may be reduced because the first capacitor divider  310  generates the second voltage V 2  based on the first voltage V 1 . In this case, when the first voltage V 1  is generated, the second voltage V 2  is generated based on the first voltage V 1 , and the second voltage V 2  is transferred causing an increase in power loss. However, when the DC-DC converter  210   b  directly generates the second voltage V 2  based on the battery voltage VBAT, the first voltage V 1  may be maintained by the first capacitor divider  310 , and thus the power loss may be reduced. 
       FIG.  10    is a block diagram illustrating an example of the SIMO converter of  FIG.  4    according to some example embodiments. 
     Referring to  FIG.  10   , a SIMO converter  200   c  may include a DC-DC converter  210 , a voltage dividing capacitor circuit  300   c , a comparator block  220   c , a PSCSG  230   b , and/or a PCSG  235   c , etc., but is not limited thereto. 
     The configuration and operation of the DC-DC converter  210  and the PSCSG  230   b  of  FIG.  10    may be the same as the configuration and operation of the DC-DC converter  210  and the PSCSG  230   b  in  FIG.  5   , respectively, but the example embodiments are not limited thereto. 
     The comparator block  220   c  may include a plurality of comparators  221 ˜ 228  that compare each of a plurality of voltages V 1 ˜V 4  with a respective reference voltage from a plurality of reference voltages VREF 1 ˜VREF 8 , and the comparator block  220   c  may generate and/or output a plurality of comparison signals CS 21 ˜CS 28 . The PCSG  235   c  may generate a phase control signal PCSb based on the plurality of comparison signals CS 21 ˜CS 28 , and may provide the phase control signal PCSb to the voltage dividing capacitor circuit  300   c.    
     The voltage dividing circuit  300   c  may include first through seventh capacitor dividers  310 ˜ 370 , but is not limited thereto. 
     The first through third capacitor dividers  310 ,  320  and  330  of  FIG.  10    may be the same as the first through third capacitor dividers  310 ,  320  and  330  in  FIG.  5   , but the example embodiments are not limited thereto. 
     The fourth capacitor divider  340  may be connected to the first voltage node VN 1 , the first intermediate voltage node IVN 1 , and a third intermediate voltage node IVN 3 , and the fourth capacitor divider  340  may generate and output a fifth voltage V 5  to the third intermediate voltage node IVN 3 . The fifth capacitor divider  350  may be connected to the first intermediate voltage node IVN 1 , the second voltage node VN 2 , and a fourth intermediate voltage node IVN 4 , and the fifth capacitor divider  340  may generate and output a sixth voltage V 6  to the fourth intermediate voltage node IVN 4 . 
     The sixth capacitor divider  360  may be connected to the second voltage node VN 2 , the second intermediate voltage node IVN 2 , and a fifth intermediate voltage node IVN 5 , and the sixth capacitor divider  360  may generate and output a seventh voltage V 7  to the fifth intermediate voltage node IVN 5 . The seventh capacitor divider  370  may be connected to the second intermediate voltage node IVN 2 , the ground node GN, and a sixth intermediate voltage node IVN 6 , and seventh capacitor divider  370  may output an eighth voltage V 8  at the sixth intermediate voltage node IVN 6 . Each of the first voltage node VN 1 , the third voltage node VN 3 , the first intermediate voltage node IVN 3 , the fourth intermediate voltage node IVN 4 , the second voltage node VN 2 , the fifth intermediate voltage node IVN 5 , the second intermediate voltage node IVN 2 , and the sixth intermediate voltage node IVN 6  may be connected to respective one of a plurality of load capacitors CL 1 , CL 5 , CL 3 , CL 6 , CL 2 , CL 7 , CL 4  and CL 8  coupled to the ground voltage, etc. 
     Each of the first through seventh capacitor dividers  310 ˜ 370  may perform and/or operate one of a voltage drop operation and a voltage booting operation. 
     Therefore, when the DC-DC converter  210  provides a current to the first voltage node VN 1  through the first power switch SW 1 , and the first voltage V 1  is present at the first voltage node VN 1 , the first capacitor divider  310  provides the second voltage V 2  to the second voltage node VN 2  based on the first voltage VN 1  as described with reference to  FIGS.  6 B and  6 C , the second capacitor divider  320 , but the example embodiments are not limited thereto. The second capacitor divider  320  provides the third voltage V 3  to the first intermediate voltage node IVN 1  based on the first voltage V 1  and the second voltage V 2 , and the third capacitor divider  330  provides the fourth voltage V 4  to the second intermediate voltage node IVN 2  based on the second voltage V 2 . 
     In addition, the fourth capacitor divider  340  provides the fifth voltage V 5  to the third intermediate voltage node IVN 3  based on the first voltage V 1  and the third voltage V 3 , and the fifth capacitor divider  350  provides the sixth voltage V 6  to the fourth intermediate voltage node IVN 4  based on the third voltage V 3  and the second voltage V 2 . The sixth capacitor divider  360  provides the seventh voltage V 7  to the fifth intermediate voltage node IVN 5  based on the second voltage V 2  and the fourth voltage V 4 , and the seventh capacitor divider  370  provides the eighth voltage V 8  to the sixth intermediate voltage node IVN 6  based on the fourth voltage V 4 . 
     Therefore, the voltage dividing capacitor circuit  300   c  may generate and output a plurality of voltages corresponding to V 1 , (7/8)*V 4 , (6/8)*V 1 , (5/8)*V 1 , (4/8)*V 1 , (3/8)*V 1 , (2/8)*V 1  and (1/8)*V 1  to the first voltage node VN 1 , the third voltage node VN 3 , the first intermediate voltage node IVN 3 , the fourth intermediate voltage node IVN 4 , the second voltage node VN 2 , the fifth intermediate voltage node IVN 5 , the second intermediate voltage node IVN 2  and the sixth intermediate voltage node IVN 6 , respectively, but the example embodiments are not limited thereto. The plurality of voltages corresponding to V 1 , (7/8)*V 4 , (6/8)*V 1 , (5/8)*V 1 , (4/8)*V 1 , (3/8)*V 1 , (2/8)*V 1  and (1/8)*V 1  have different voltage levels. 
       FIG.  11    is a circuit diagram illustrating an example of the voltage dividing capacitor circuit in the SIMO converter of  FIG.  10    according to some example embodiments. 
     Referring to  FIG.  11   , the voltage dividing circuit  300   c  may include the first through seventh capacitor dividers  310 ˜ 370 , but is not limited thereto. 
     The first capacitor divider  310  may include a plurality of transistors  311 ,  312 ,  313  and  314 , etc., connected in series between the first voltage node VN 1  and the ground node GN, and a flying capacitor CF connected between a node N 11  and a node N 12 . According to some example embodiments, the flying capacitor CF may be connected in parallel to one or more transistors, e.g., transistors  312  and/or  313 , etc., but the example embodiments are not limited thereto. 
     The transistor  311  is connected between the first voltage node VN 1  and the node N 11 , the transistor  312  is connected between the node N 11  and the second voltage node VN 2 , the transistor  313  is connected between the second voltage node VN 2  and the node N 12 , and the transistor  314  is connected between the second voltage node VN 2  and the ground node GN, but the example embodiments are not limited thereto. 
     Each gate of the plurality of transistors  311  and  313  receives a first phase control signal Φ 1 , and each gate of the plurality of transistors  312  and  314  receives a first inversion phase control signal Φ 1 B which has a phase difference of 180 degrees with respect to the first phase control signal Φ 1 , but the example embodiments are not limited thereto. When the transistors  311  and  313  are turned on, and the transistors a 312  and  314  are turned off, the first capacitor divider  310  stores, in the flying capacitor CF, a voltage corresponding to a difference between the first voltage V 1  and the second voltage V 2 . When the transistors  311  and  313  are turned off, and the transistors  312  and  314  are turned, the voltage stored in the flying capacitor CF is provided to the second voltage node VN 2  and stored in the second load capacitor CL 2 . 
     The second capacitor divider  320  may include a plurality of transistors  321 ,  322 ,  323  and  324 , etc., connected in series between the first voltage node VN 1  and the second voltage node VN 2 , and a flying capacitor CF connected between a node N 21  and a node N 22 , but the example embodiments are not limited thereto. Each gate of the transistors  321  and  323  receives a second phase control signal Φ 2 , and each gate of the transistors  322  and  324  receives a second inversion phase control signal Φ 2 B which has a phase difference of 180 degrees with respect to the second phase control signal Φ 2 , but is not limited thereto. 
     The third capacitor divider  330  may include a plurality of transistors  331 ,  332 ,  333  and  334  connected in series between the second voltage node VN 2  and the ground node GN, and a flying capacitor CF connected between a node N 31  and a node N 32 . Each gate of the transistors  331  and  333  receives a third phase control signal Φ 3 , and each gate of the transistors  332  and  334  receives a third inversion phase control signal Φ 3 B which has a phase difference of 180 degrees with respect to the third phase control signal Φ 3 , but is not limited thereto. 
     The fourth capacitor divider  340  may include a plurality of transistors  341 ,  342 ,  343  and  344  connected in series between the first voltage node VN 1  and the first intermediate voltage node IVN 1 , and a flying capacitor CF connected between a node N 41  and a node N 42 . Each gate of the transistors  341  and  343  receives a fourth phase control signal Φ 4 , and each gate of the transistors  342  and  344  receives a fourth inversion phase control signal Φ 4 B which has a phase difference of 180 degrees with respect to the fourth phase control signal Φ 4 , but is not limited thereto. A node between the transistors  342  and  343  may be the third intermediate voltage node IVN 3 . 
     The fifth capacitor divider  350  may include a plurality of transistors  351 ,  352 ,  353  and  354  connected in series between the first intermediate voltage node IVN 1  and the second voltage node VN 2 , and a flying capacitor CF connected between a node N 51  and a node N 52 . Each gate of the transistors  351  and  353  receives a fifth phase control signal Φ 5 , and each gate of the transistors  352  and  354  receives a fifth inversion phase control signal Φ 5 B which has a phase difference of 180 degrees with respect to the fifth phase control signal Φ 5 , but is not limited thereto. A node between the transistors  352  and  353  may be the fourth intermediate voltage node IVN 4 . 
     The sixth capacitor divider  360  may include a plurality of transistors  361 ,  362 ,  363  and  364  connected in series between the second voltage node VN 2  and the second intermediate voltage node IVN 2 , and a flying capacitor CF connected between a node N 61  and a node N 62 . Each gate of the transistors  361  and  363  receives a sixth phase control signal Φ 6 , and each gate of the transistors  362  and  364  receives a sixth inversion phase control signal Φ 6 B which has a phase difference of 180 degrees with respect to the sixth phase control signal Φ 6 , but is not limited thereto. A node between the transistors  362  and  363  may be the fifth intermediate voltage node IVN 5 . 
     The seventh capacitor divider  370  may include a plurality of transistors  371 ,  372 ,  373  and  374  connected in series between the second intermediate voltage node IVN 2  and the ground node GN, and a flying capacitor CF connected between a node N 71  and a node N 72 . Each gate of the transistors  371  and  373  receives a seventh phase control signal Φ 7 , and each gate of the transistors  372  and  374  receives a seventh inversion phase control signal Φ 7 B which has a phase difference of 180 degrees with respect to the seventh phase control signal Φ 7 , but is not limited thereto. A node between the transistors  372  and  373  may be the sixth intermediate voltage node IVN 6 . 
     Operation of each of the second through fourth capacitor dividers  320 ˜ 370  in a first state and a second state of a corresponding phase control signal may be similar to the operations discussed in connection with  FIGS.  6 B and  6 C , but the example embodiments are not limited thereto. 
       FIG.  12    is a circuit diagram illustrating an example of the voltage dividing capacitor circuit in the SIMO converter of  FIG.  10    according to some example embodiments. 
     A voltage dividing circuit  300   cc  in  FIG.  12    differs from the voltage dividing circuit  300   c  in  FIG.  11    in that the voltage dividing circuit  300   cc  further include an eighth capacitor divider  380 , but the example embodiments are not limited thereto. 
     Referring to  FIG.  12   , the eighth capacitor divider  380  may be connected between the first voltage node VN 1  and the first intermediate voltage node IVN 1  in parallel with the fourth capacitor divider  340 , but is not limited thereto. 
     The eighth capacitor divider  380  may include a plurality of transistors  381 ,  382 ,  383  and  384  connected in series between the first voltage node VN 1  and the first intermediate voltage node IVN 1 , and a flying capacitor CF connected between a node N 81  and a node N 82 . Each gate of the transistors  381  and  383  receives the fourth inversion phase control signal Φ 4 B, and each gate of the transistors  382  and  384  receives the fourth phase control signal Φ 4 . 
     As described with reference to  FIGS.  8 B and  8 C , the fourth capacitor divider  340  and the eighth capacitor divider  380  may operate complementarily in response to the fourth phase control signal Φ 4  and the fourth inversion phase control signal Φ 4 B, and may provide additional current to the third intermediate voltage node IVN 3  when a current provided to the load from the third intermediate voltage node IVN 3  increases. At least one additional capacitor divider operating complementarily may be connected to a load which consumes too much current and/or more current than desired, and the additional capacitor divider may supply additional current to the desired node rapidly. 
       FIG.  13    is a block diagram illustrating an example of a supply modulator according to some example embodiments. 
     In  FIG.  13   , a first power amplifier  90   a  and a second power amplifier  90   b  are illustrated together for the sake of brevity and convenience of explanation, but the example embodiments are not limited thereto. 
     Referring to  FIG.  13   , a supply modulator  100   b  may include a main controller  110 , a discrete level (DL) controller  120   a , a switch controller  130   a , a first switch array  140   a , a second switch array  140   b , a third switch S 31 , a fourth switch S 32  and/or a SIMO converter  200   d , etc., but is not limited thereto. 
     The main controller  110  may receive the tracking mode signal TMS, the average power signal ART_REF, and the ET reference signal ET_REF from a modem, such as the modem  40  in  FIG.  1   , and the main controller  110  may determine a tracking mode of the supply modulator  100   d  based on the tracking mode signal TMS, but is not limited thereto. Additionally, the main controller  110  may generate a plurality of reference voltages VREF 1 ˜VREFn based on the ET reference signal ET_REF while in the ET mode, and may provide the plurality of reference voltages VREF 1 ˜VREFn to the SIMO converter  200   b . The main controller  110  may control the discrete level controller  120   a , the switch controller  130   a  and/or the SIMO converter  200   d , etc., but the example embodiments are not limited thereto. 
     The SIMO converter  200   d  may generate a plurality of voltages V 1 ˜Vn based on the battery voltage VBAT under the control of (and/or based on signals received from) the main controller  110 , and may provide the plurality of voltages V 1 ˜Vn to the first switch array  140   a  and/or the second switch array  140   b , etc. The SIMO converter  200   d  may generate a plurality of APT voltages, such as first APT voltage APT_V 1  and a second APT voltage APT_V 2 , based on the average power signal ART_REF while in the APT mode, and the SIMO converter  200   d  may provide the first APT voltage APT_V 1  to the first power amplifier  90   a  through the third switch S 32  or may provide the second APT voltage APT_V 2  to the second power amplifier  90   b  through the fourth switch S 33 . 
     The SIMO converter  200   d  may generate the plurality of voltages V 1 ˜Vn having different voltage levels based on the plurality of reference voltages VREF 1 ˜VREFn and the battery voltage VBAT in the ET mode, and the SIMO converter  200   d  may output the plurality of voltages V 1 ˜Vn to the first switch array  140   a  and the second switch array  140   b.    
     The first switch array  140   a  may include a plurality of switches S 1   a ˜Sna corresponding to the plurality of voltages V 1 ˜Vn having different voltage levels. The second switch array  140   b  may include a plurality of switches S 2   a ˜Snb corresponding to the plurality of voltages V 1 ˜Vn having different voltage levels. The opening and closing operations of the plurality of switches S 1   a ˜Sna may be controlled by a switch control signal SWC 1  provided from the switch controller  130   a . The opening and closing operations of the plurality of switches S 2   a ˜Snb may be controlled by a switch control signal SWC 2  provided from the switch controller  130   a.    
     The switch controller  130   a  may control on/off of the third switch S 31  and the fourth switch S 32  using switch control signals SWC 3  and SWC 4  under the control of (and/or based on signals received from) the main controller  110  while in the APT mode. 
     When the SIMO converter  200   d  operates in an APT-APT mode, the switch controller  130   a  may turn off the switches S 1   a ˜Sna and the switches S 2   a ˜Snb, and may turn on the third switch S 31  and the fourth switch S 32 . When the SIMO converter  200   d  operates in an ET-ET mode, the switch controller  130   a  may turn on one of the switches S 1   a ˜Sna and one of the switches S 2   a ˜Snb, and may turn off the third switch S 31  and the fourth switch S 32 . 
     The discrete level controller  120   a  may generate a first level control signal ENV_LV 1  including envelope level information based on a first envelope signal ENV 1  from the modem  40 , and the discrete level controller  120   a  may generate a second level control signal ENV_LV 2  including envelope level information based on a second envelope signal ENV 2  from the modem  40 . The discrete level controller  120  may provide the first level control signal ENV_LV 1  and/or the second level control signal ENV_LV 2  to the switch controller  130   a , but is not limited thereto. 
     In the ET mode, the first switch array  140   a  may select a first voltage among the plurality of voltages V 1 ˜Vn, and may provide the selected first voltage to the first power amplifier  90   a  as a first supply voltage VCC 1 . In the ET mode, the second switch array  140   b  may select a second voltage among the plurality of voltages V 1 ˜Vn and may provide the selected second voltage to the second power amplifier  90   b  as a second supply voltage VCC 2 . In addition, in the APT mode, the switch controller  130  may control at least one of the plurality of switches S 1 ˜Sn such that a voltage having a nearest level (e.g., closest voltage level, etc.) with a desired and/or required level and/or a greater level than the desired and/or required level among the plurality of voltages V 1 ˜Vn is selected. 
     The first power amplifier  90   a  may amplify a first RF input signal RF_IN 1  based on the first supply voltage VCC 1  or the first APT voltage APT_V 1  to generate a first RF output signal RF_OUT 1 . The second power amplifier  90   b  may amplify a second RF input signal RF_IN 2  based on the second supply voltage VCC 2  or the second APT voltage APT_V 2  to generate a second RF output signal RF_OUT 2 . 
     The SIMO converter  200   d  may operate in one of APT-APT mode, ET-APT mode and ET-ET mode, and may provide the plurality of voltages V 1 ˜Vn to the first switch array  140   a  and the second switch array  140   b , but the example embodiments are not limited thereto. 
       FIG.  14    is a block diagram illustrating an example of the SIMO converter in the supply modulator in  FIG.  13    according to some example embodiments. 
     In  FIG.  14   , the first switch array  140   a , the second switch array  140   b , the first power amplifier  90   a  and the second power amplifier  90   b  are illustrated together for the sake of brevity and convenience of explanation, but the example embodiments are not limited thereto. 
     Referring to  FIG.  14   , a SIMO converter  200   d  may include a DC-DC converter  210 , a voltage dividing capacitor circuit  300   d , a comparator block  220   d , PSCSG  230   d , and/or a PCSG  235   d , etc., but the example embodiments are not limited thereto. 
     The comparator block  220   d  may include a plurality of comparators  221 ,  222 ,  223  and  224  that compare each of a plurality of voltages V 1 , V 2 , V 3  and V 4  with one of a plurality of reference voltages VREF 1 , VREF 2 , VREF 3  and VREF 4 , respectively, to generate and output a plurality of comparison signals CS 21 , CS 22 , CS 23  and CS 24  based on the results of the comparisons. 
     The PSCSG  230   d  may generate a first set of switch control signal SCSc based on a first comparison signal CS 21 , a second comparison signal CS 22 , and/or the tracking mode signal TYMS, and the PSCSG  230   d  may provide the first set of switch control signal SCSc to the DC-DC converter  210   d.    
     The PCSG  235   d  may generate a phase control signal PCSa based on the plurality of comparison signals CS 21 , CS 22 , CS 23  and CS 24 , and may provide the phase control signal PCSa to the voltage dividing capacitor circuit  300   d . According to some example embodiments, the configuration of the voltage dividing capacitor circuit  300   d  of  FIG.  14    may be the same as the configuration of the voltage dividing capacitor circuit  300   a  in  FIG.  4   , but the example embodiments are not limited thereto. 
     The DC-DC converter  210   d  may include the inductor  211 , first through eighth power switches SW 1 , SW 2 , SW 3 , SW 4 , SW 5 , SW 6 , SW 7  and SW 8 , and/or load capacitors CL 1 , CL 12 , CL 2  and CL 22 , etc., but is not limited thereto. 
     The inductor  211  may be connected between a first switching node SN 1  and a second switching node SN 2 . The first power switch SW 1  may be connected between the first switching node SN 1  and the first voltage node VN 1 , and the first power switch SW 1  may have a gate to receive a first switch control signal SCS 31 . The second power switch SW 2  may be connected between the first switching node SN 1  and the second voltage node VN 2 , and the second power switch SW 2  may have a gate to receive a second switch control signal SCS 32 . The third power switch SW 3  may be connected between the first switching node SN 1  and the ground node GN, and the third power switch SW 3  may have a gate to receive a third switch control signal SCS 33 . The fourth power switch SW 4  may be connected between the second switching node SN 2  and the battery voltage VBAT, and the fourth power switch SW 4  may have a gate to receive a fourth switch control signal SCS 34 . 
     The fifth power switch SW 5  may be connected between the second switching node SN 2  and the ground node GN, and the fifth power switch SW 5  may have a gate to receive a fifth switch control signal SCS 35 . The sixth power switch SW 6  may be connected between the first switching node SN 1  and the load capacitor CL 12 , and the sixth power switch SW 6  may have a gate to receive a sixth switch control signal SCS 36 . The seventh power switch SW 7  may be connected between the first switching node SN 1  and the load capacitor CL 22 , and the seventh power switch SW 7  may have a gate to receive a seventh switch control signal SCS 37 . The eighth power switch SW 8  may be connected between the battery voltage VBAT and the second voltage node VN 2 , and the eighth power switch SW 8  may have a gate to receive an eighth switch control signal SCS 38 . 
     The SIMO converter  200   d  as shown in  FIG.  14    may provide the first power amplifier  140   a  and the second power amplifier  140   b  with a first supply voltage and a second supply voltage having different voltage levels through the first switch array  140   a  and the second switch array  140 , and the SIMO converter  200   d  may support APT mode and the ET mode, but is not limited thereto. 
     The SIMO converter  200   d  may support at least one of an APT-APT mode, APT-ET mode, ET-APT mode, and/or ET-ET mode according to and/or based on a driving mode (e.g., operating mode, etc.) of the supply modulator including the SIMO converter  200   d , but is not limited thereto. 
     When the SIMO converter  200   d  operates in the ET-ET mode, the SIMO converter  200   d  may provide at least one of the voltages V 1 , V 2 , V 3  and V 4  generated in the voltage dividing capacitor circuit  300   d  to the first power amplifier  140   a  and the second power amplifier  140   b  through the first switch array  140   a  and the second switch array  140 , but is not limited thereto. 
     When the SIMO converter  200   d  operates in the APT-ET mode, the DC-DC converter  210   d  provides a current to the voltage dividing capacitor circuit  300   d  via the first power switch SW 1 , and the voltage dividing capacitor circuit  300   d  generates the voltages V 2 , V 3  and V 4  based on the voltage V 1  to support the ET mode. In addition, the DC-DC converter  210   d  may generate an APT voltage using the sixth power switch SW 6  coupled to the load capacitor CL 12  and the seventh power switch SW 7  coupled to the load capacitor CL 22 , and the DC-DC converter  210   d  may provide the APT voltage to the second power amplifier  90   b  using the second voltage node VN 2  and the switch S 32  as shown in  FIG.  13    to support the APT mode, but is not limited thereto. 
     When the SIMO converter  200   d  operates in the APT-APT mode, the DC-DC converter  210   d  maintains the voltages V 1 , V 2 , V 3  and V 4  in the voltage dividing capacitor circuit  300   d  by using the eighth power switch SW 8  coupled to the battery voltage VBAT as a low-voltage drop out regulator, and the DC-DC converter  210   d  may provide an APT voltage using the sixth power switch SW 6  coupled to the load capacitor CL 12  and the seventh power switch SW 7  coupled to the load capacitor CL 22 , but is not limited thereto. 
       FIG.  15    illustrates that the SIMO converter in  FIG.  14    drives two power amplifiers in ET-ET mode according to at least one example embodiment. 
     Referring to  FIG.  15   , each of the plurality of power switches SW 1 , SW 2 , SW 4  and SW 5 , etc., in the DC-DC converter  210   d  is switched in response to one of the switch control signals SCS 31 , SCS 32 , SCS 34  and SCS 35 , respectively, and each of the power switches SW 3 , SW 6 , SW 7  and SW 8  in the DC-DC converter  210   d  is turned off in response to one of the switch control signals SCS 33 , SCS 36 , SCS 37  and SCS 38 , respectively. Accordingly, the DC-DC converter  210   d  supplies current to the first voltage node VN 1  and the second voltage node VN 2 , the voltage dividing capacitor circuit  300   d  generates the third voltage V 3  and the fourth voltage V 4  based on the first voltage V 1  and the second voltage V 2 , and the voltage dividing capacitor circuit  300   d  provides the first through fourth voltages V 1 , V 2 , V 3  and V 4  to the first switch array  140   a  and the second switch array  140   b , but the example embodiments are not limited thereto. 
     The first switch array  140   a  may select one of the first through fourth voltages V 1 , V 2 , V 3  and V 4  based on the first switch control signal SWC 1 . The first switch control signal SWC 1  may be generated based on a voltage level of the first envelope signal ENV 1 . The first switch array  140   a  may provide the selected voltage to the first power amplifier  90   a , and the second switch array  140   b  may select one of the first through fourth voltages V 1 , V 2 , V 3  and V 4  based on the second switch control signal SWC 2  generated based on a voltage level of the second envelope signal ENV 2 , and the second switch array  140   b  may provide the selected voltage to the second power amplifier  90   b.    
       FIG.  16    illustrates that the SIMO converter in  FIG.  14    drives two power amplifiers in APT-APT mode according to at least one example embodiment. 
     Referring to  FIG.  16   , each of the plurality of power switches SW 3 , SW 4 , SW 5 , SW 6 , SW 7  and SW 8 , etc., in the DC-DC converter  210   d  is switched in response to one of the switch control signals SCS 33 , SCS 34 , SCS 35 , SWC 36 , SWC 37  and SCS 38 , respectively, and each of the power switches SW 1  and SW 8  in the DC-DC converter  210   d  is turned off in response to one of the switch control signals SCS 31  and SCS 32 , respectively. Accordingly, the DC-DC converter  210   d  provides the second voltage V 2  to the voltage dividing capacitor circuit  300   d  by using the eighth power switch SW 8  coupled to the battery voltage VBAT as a low-voltage drop out regulator, and the voltage dividing capacitor circuit  300   d  generates a plurality of voltages V 1 , V 2 , V 3 , and V 4 . The plurality of voltages V 1 , V 2 , V 3 , and V 4  are prepared for a next ET mode. The DC-DC converter  210   d  may provide an APT voltage using the sixth power switch SW 6  coupled to the load capacitor CL 12  and the seventh power switch SW 7  coupled to the load capacitor CL 22  as described with reference to  FIG.  14   , but the example embodiments are not limited thereto. 
       FIG.  17 A  illustrates that the SIMO converter in  FIG.  14    drives two power amplifiers in ET-APT mode according to at least one example embodiment. 
     Referring to  FIG.  17 A , each of the plurality of power switches SW 1 , SW 3 , SW 4 , SW 5 , SW 7  and SW 8  in the DC-DC converter  210   d  is switched in response to one of the plurality of switch control signals SCS 31 , SCS 33 , SCS 34 , SWC 35 , SWC 37  and SCS 38 , respectively, and each of the power switches SW 2  and SW 6  in the DC-DC converter  210   d  is turned off in response to one of the switch control signals SCS 32  and SCS 36 , respectively. Accordingly, the DC-DC converter  210   d  supplies current to the first voltage node VN 1  through the power switch SW 1 , and supplies current to the second voltage node VN 2  through the power switch SW 8 . The voltage dividing capacitor circuit  300   d  generates the third voltage V 3  and the fourth voltage V 4  based on the first voltage V 1  and the second voltage V 2 . In addition, the DC-DC converter  210   d  generates the APT voltage using the power switch SW 7  coupled to the load capacitor CL 22  and may provide the APT voltage through the first voltage node VN 1 . 
       FIG.  17 B  illustrates waveforms of the output voltage according to a tracking mode in the SIMO converter in  FIG.  14    according to at least one example embodiment. 
       FIG.  17 B  illustrates an output voltage waveform APT_V in the APT mode and an output voltage waveform ET_V in the ET mode, but is not limited thereto. 
     Here, the APT is a technique for applying a modulation voltage to a power amplifier (e.g., the power amplifier  90  in  FIG.  1   , etc.), the modulation voltage varying based on a peak level of an envelope RF_OUT_ENV of a RF output signal RF_OUT for each desired and/or predetermined transmission time interval (TTI). The ET is a technique for applying a modulation voltage to a power amplifier (e.g., the power amplifier  90  in  FIG.  1   , etc.), which instantaneously follows (and/or corresponds to, etc.) a voltage level of the envelope RF_OUT_ENV of the RF output signal RF_OUT, but the example embodiments are not limited thereto. The modulation voltage is limited to a plurality voltages (for example, V 11 , V 12 , V 13  and V 14 , etc.) having different voltage levels which the voltage dividing capacitor circuit  300   d  is capable of generating. In  FIG.  17 B , it is assumed that the output voltage waveform APT_V has a level V′, but the example embodiments are not limited thereto. 
     The envelope RF_OUT_ENV of the RF output signal RF_OUT may be generated based on amplitude of the RF output signal RF_OUT, but is not limited thereto. 
       FIG.  18    is a circuit diagram illustrating a converter that employs two DC-DC converters according to some example embodiments. 
     Referring to  FIG.  18   , a converter  200   e  may include a DC-DC converter  210   d , a voltage dividing capacitor circuit  300   d , a comparator block  220   d , a PSCSG  230   d , a PCSG  235   d , and/or a second DC-DC converter  210   e , etc., but is not limited thereto. 
     The converter  200   e  of  FIG.  18    differs from the SIMO converter  200   b  of  FIG.  9    in that the converter  200   e  further includes the second DC-DC converter  210   e , but the example embodiments are not limited thereto. 
     The second DC-DC converter  210   e  may include an inductor  211   a  and a first through fifth power switches SW 11 , SW 12 , SW 13 , SW 14  and SW 15 , etc. The inductor  211   a  may be connected between a first switching node SN 11  and a second switching node SN 12 . 
     The first power switch SW 11  may be connected between the first switching node SN 11  and the first voltage node VN 1 , and the first power switch SW 11  may have a gate to receive the first switch control signal SW 31 . The second power switch SW 12  may be connected between the first switching node SN 11  and the second voltage node VN 2 , and the second power switch SW 12  may have a gate to receive the second switch control signal SW 32 . The third power switch SW 13  may be connected between the first switching node SN 11  and the ground node GN, and the third power switch SW 13  may have a gate to receive the third switch control signal SW 33 . The fourth power switch SW 14  may be connected between the second switching node SN 12  and the battery voltage VBAT, and the fourth power switch SW 14  may have a gate to receive the fourth switch control signal SCS 34 . The fifth power switch SW 15  may be connected between the second switching node SN 12  and the ground node GN, and the fifth power switch SW 15  may have a gate to receive the fifth switch control signal SCS 35 . 
     The DC-DC converter  210   d  and the second DC-DC converter  210   e  may be connected to the same nodes, and the DC-DC converter  210   d  and the second DC-DC converter  210   e  may share the voltage dividing capacitor circuit  300   d  and increase the processing capacity and/or efficiency of the circuit. 
       FIG.  19    is a circuit diagram illustrating a converter that employs two DC-DC converters according to some example embodiments. 
     Referring to  FIG.  19   , a converter  200   f  may include a DC-DC converter  210   d , a voltage dividing capacitor circuit  300   d , a comparator block  220   d , a PSCSG  230   d , a PCSG  235   d , and/or a second DC-DC converter  210   f , etc., but the example embodiments are not limited thereto. 
     The converter  200   f  of  FIG.  19    differs from the SIMO converter  200   b  of  FIG.  9    in that the converter  200   e  further includes the second DC-DC converter  210   f , but the example embodiments are not limited thereto. 
     The second DC-DC converter  210   fe  may include an inductor  211   a  and first through fifth power switches SW 21 , SW 22 , SW 23 , SW 24  and SW 25 , but is not limited thereto. The inductor  211   a  may be connected between a first switching node SN 21  and a second switching node SN 22 . 
     The first power switch SW 21  may be connected between the first switching node SN 21  and the first intermediate voltage node IVN 1 , and the first power switch SW 21  may have a gate to receive the first switch control signal SW 31 . The second power switch SW 22  may be connected between the first switching node SN 21  and the second intermediate voltage node IVN 2 , and the second power switch SW 22  may have a gate to receive the second switch control signal SW 32 . 
     The third power switch SW 23  may be connected between the first switching node SN 21  and the ground node GN, and the third power switch SW 23  may have a gate to receive the third switch control signal SW 33 . The fourth power switch SW 24  may be connected between the second switching node SN 22  and the battery voltage VBAT, and the fourth power switch SW 24  may have a gate to receive the fourth switch control signal SCS 34 . The fifth power switch SW 15  may be connected between the second switching node SN 22  and the ground node GN, and the fifth power switch SW 15  may have a gate to receive the fifth switch control signal SCS 35 . 
     The DC-DC converter  210   d  may supply current to the first voltage node VN 1  and the second voltage node VN 2  based on the battery voltage VBAT, and the second DC-DC  210   f  may supply current to the first intermediate voltage node IVN 1  and the second intermediate voltage node IVN 2  based on the battery voltage VBAT. Therefore, the converter  200   f  may provide current to the first voltage node VN 1 , the second voltage node VN 2 , the first intermediate voltage node IVN 1 , and/or the second intermediate voltage node IVN 2  without passing through the capacitor divider, and thereby may increase the efficiency of the circuit. 
     According to some example embodiments, the DC-DC converter  210   d  and the second DC-DC converter  210   f  may employ DC-DC converters with different configurations, and are not limited thereto. 
       FIG.  20    is a circuit diagram illustrating an example of a voltage dividing capacitor circuit according to some example embodiments. 
     Referring to  FIG.  20   , a voltage dividing capacitor circuit  300   e  may include first through fourth capacitor dividers  310   a ,  320 ,  330  and  340   a , but the example embodiments are not limited thereto. 
     The first capacitor divider  310   a  may include a plurality of transistors  311 ,  312 ,  313 ,  314 ,  315  and  316 , etc., connected in series between the first voltage node VN 1  and the ground node GN, and two flying capacitor CF may be connected between a node N 11  and a node N 13 . A first load capacitor CL 1  may be connected between the first voltage node VN 1  and the ground voltage. 
     The transistor  311  is connected between the first voltage node VN 1  and the node N 11 , the transistor  312  is connected between the node N 11  and the second voltage node VN 2 , the transistor  313  is connected between the second voltage node VN 2  and the node N 12 , the transistor  314  is connected between the node N 12  and a third voltage node VN 3 , the transistor  315  is connected between the third voltage node VN 3  and a node N 13 , and the transistor  315  is connected between the node N 13  and the ground node GN. 
     Each gate of the transistors  311 ,  313  and  315  receives a first phase control signal Φ 1 , and each gate of the transistors  312 ,  314  and  316  receives a first inversion phase control signal Φ 1 B which has a phase difference of 180 degrees with respect to the first phase control signal Φ 1 , but is not limited thereto. The first capacitor divider  310   a  may generate the second voltage V 2  and the third voltage V 3  based on the first voltage V 1  at the first voltage node VN 1 , and may provide the second voltage V 2  and the third voltage V 3  to the second voltage node VN 2  and the third voltage node Vn 3 , respectively. 
     The configuration and operation of each of the second capacitor divider  320  and the third capacitor divider  330  may be similar to the second capacitor divider  320  and the third capacitor divider  330  described in  FIG.  7 A , but are not limited thereto. A second load capacitor CL 2  may be connected between the second voltage node VN 2  and the ground voltage. A third load capacitor CL 3  may be connected between the third voltage node VN 3  and the ground voltage. A fourth load capacitor CL 4  may be connected between a first intermediate voltage node IVN 1  and the ground voltage. A fifth load capacitor CL 5  may be connected between a first intermediate voltage node IVN 1  and the ground voltage. 
     The fourth capacitor divider  340   a  may include a plurality of transistors  341   a ,  342   a ,  343   a  and  344   a  connected in series between the third voltage node VN 3  and the ground node GN, and a flying capacitor CF may be connected between a node N 41   a  and a node N 42   a . The transistor  341   a  is connected between the third voltage node VN 3  and the node N 41   a , the transistor  342   a  is connected between the node N 41   a  and the third intermediate voltage node IVN 3 , the transistor  343   a  is connected between the third intermediate voltage node IVN 3  and the node N 42   a , and the transistor  344   a  is connected between the node N 42   a  and the ground node GN. 
     Each gate of the transistors  341   a  and  343   a  receives a fourth phase control signal Φ 4 , and each gate of the transistors  342   a  and  344   a  receives a fourth inversion phase control signal Φ 4 B which has a phase difference of 180 degrees with respect to the fourth phase control signal Φ 4 , but is not limited thereto. The fourth capacitor divider  340   a  may generate a sixth voltage V 6  based on the third voltage V 3  and may provide the sixth voltage V 6  to the third intermediate voltage node IVN 3 . 
       FIG.  21    is a circuit diagram illustrating an example of a voltage dividing capacitor circuit according to some example embodiments. 
     Referring to  FIG.  21   , a voltage dividing capacitor circuit  300   f  may include first through fifth capacitor dividers  310 ,  320 ,  330 ,  340   a  and  350   a , but is not limited thereto. 
     Configuration of each of the first through third capacitor dividers  310 ,  320  and  330  of  FIG.  21    may be substantially the same as configuration of each of the first through third capacitor dividers  310 ,  320  and  330  in  FIG.  7 A , and configuration of the fourth capacitor divider  340   a  of  FIG.  21    may be substantially the same as configuration of the fourth capacitor divider  340   a  in  FIG.  20   , but the example embodiments are not limited thereto. 
     The fifth capacitor divider  350   a  may include a plurality of transistors  351   a ,  352   a ,  353   a  and  354   a  connected in series between the second voltage node VN 2  and the ground node GN, and a flying capacitor CF may be connected between a node N 51   a  and a node N 52   a.    
     The transistor  351   a  is connected between the second voltage node VN 3  and the node N 51   a , the transistor  352   a  is connected between the node N 51   a  and the third voltage node VN 3 , the transistor  353   a  is connected between the third voltage node VN 3  and the node N 52   a , and the transistor  354   a  is connected between the node N 52   a  and the ground node GN. 
     Each gate of the transistors  351   a  and  353   a  receives a fifth phase control signal Φ 5 , and each gate of the transistors  352   a  and  354   a  receives a fifth inversion phase control signal Φ 5 B which has a phase difference of 180 degrees with respect to the fifth phase control signal Φ 5 , but is not limited thereto. The fifth capacitor divider  350   a  may generate a third voltage V 3  based on the second voltage V 2 , and may provide the third voltage V 3  to the third voltage node VN 3 . 
       FIG.  22    is a circuit diagram illustrating an example of a voltage dividing capacitor circuit according to some example embodiments. 
     A voltage dividing capacitor circuit  300   g  of  FIG.  22    has a configuration in which the second capacitor divider  320  is omitted from the voltage dividing capacitor circuit  300   a  in  FIG.  7 A . The voltage dividing capacitor circuit  300   g  may include the first capacitor divider  310  and the third capacitor divider  330  in  FIG.  7 A . Therefore, the voltage dividing capacitor circuit  300   g  may have a reduced number of load capacitors and/or switches. 
     In  FIG.  22   , the first voltage node VN 1  may be referred to as a first node, the ground node may be referred to as a second node and the second voltage node may be referred to as a third node. 
       FIG.  23    is a circuit diagram illustrating an example of a voltage dividing capacitor circuit according to some example embodiments. 
     A voltage dividing capacitor circuit  300   h  of  FIG.  23    has a configuration in which the third capacitor divider  330  is omitted from the voltage dividing capacitor circuit  300   a  in  FIG.  7 A . The voltage dividing capacitor circuit  300   h  may include the first capacitor divider  310  and the second capacitor divider  320  in  FIG.  7 A , but is not limited thereto. Therefore, the voltage dividing capacitor circuit  300   h  may have a reduced number of load capacitors and/or switches. 
     In  FIG.  23   , the first voltage node VN 1  may be referred to as a second node, the ground node may be referred to as a first node, and the second voltage node may be referred to as a third node. 
     Referring to  FIGS.  22  and  23   , at least one capacitor divider associated with a voltage that is not used, may be omitted from a plurality of capacitor dividers included in the voltage dividing capacitor circuit, and the number of load capacitors and/or switches included in the voltage dividing capacitor circuit may be reduced. 
     The voltage dividing capacitor circuit, the SIMO converter and the supply modulator according to some example embodiments may be employed in various communication devices, may reduce power consumption of the communication device, and may enhance performance of the communication device. 
     The foregoing is illustrative of some example embodiments and is not to be construed as limiting thereof. Although a few some example embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible in the some example embodiments without materially departing from the novel teachings and advantages of the inventive concept. Accordingly, all such modifications are intended to be included within the scope of the inventive concept as defined in the claims.