Patent Publication Number: US-11639958-B2

Title: Voltage tracking circuit and method of operating the same

Description:
PRIORITY CLAIM AND CROSS-REFERENCE 
     The present application is a continuation of U.S. application Ser. No. 17/030,062, filed Sep. 23, 2020, now U.S. Pat. No. 11,454,668, issued Sep. 27, 2022, which claims the benefit of U.S. Provisional Application No. 62/954,924, filed Dec. 30, 2019, which are herein incorporated by reference in their entireties. 
    
    
     BACKGROUND 
     The recent trend in miniaturizing integrated circuits (ICs) has resulted in smaller devices which consume less power, yet provide more functionally at higher speeds than before. The miniaturization process has also increased the devices&#39; susceptibility to electrostatic discharge (ESD) events due to various factors, such as thinner dielectric thicknesses and associated lowered dielectric breakdown voltages. ESD is one of the causes of electronic circuit damage and is also one of the considerations in semiconductor advanced technology. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. 
         FIG.  1 A  is a schematic diagram of an integrated circuit, in accordance with some embodiments. 
         FIG.  1 B  is a cross-sectional view of integrated circuit, in accordance with some embodiments. 
         FIG.  2 A  is a schematic diagram of an integrated circuit, in accordance with some embodiments. 
         FIG.  2 B  is a cross-sectional view of integrated circuit, in accordance with some embodiments. 
         FIG.  3 A  is a circuit diagram of an integrated circuit, in accordance with some embodiments. 
         FIG.  3 B  is a circuit diagram of an equivalent circuit of integrated circuit, in accordance with some embodiments. 
         FIG.  3 C  is a cross-sectional view of integrated circuit, in accordance with some embodiments. 
         FIG.  4 A  is a circuit diagram of an integrated circuit, in accordance with some embodiments. 
         FIG.  4 B  is a circuit diagram of an equivalent circuit of integrated circuit, in accordance with some embodiments. 
         FIG.  4 C  is a cross-sectional view of integrated circuit, in accordance with some embodiments. 
         FIG.  5 A  is a circuit diagram of an integrated circuit, in accordance with some embodiments. 
         FIG.  5 B  is a circuit diagram of an equivalent circuit of integrated circuit, in accordance with some embodiments. 
         FIG.  5 C  is a cross-sectional view of integrated circuit, in accordance with some embodiments. 
         FIG.  6 A  is a circuit diagram of an integrated circuit, in accordance with some embodiments. 
         FIG.  6 B  is a circuit diagram of an equivalent circuit of integrated circuit, in accordance with some embodiments. 
         FIG.  6 C  is a cross-sectional view of integrated circuit, in accordance with some embodiments. 
         FIG.  7 A  is a circuit diagram of an integrated circuit, in accordance with some embodiments. 
         FIG.  7 B  is a circuit diagram of an integrated circuit, in accordance with some embodiments. 
         FIG.  7 C  is a circuit diagram of an integrated circuit, in accordance with some embodiments. 
         FIG.  7 D  is a circuit diagram of an integrated circuit, in accordance with some embodiments. 
         FIG.  8    is a circuit diagram of a control logic circuit, in accordance with some embodiments. 
         FIG.  9    is a flowchart of a method of operating a circuit, such as the integrated circuit of  FIG.  1 A- 1 B,  2 A- 2 B,  3 A- 3 C,  4 A- 4 C,  5 A- 5 C,  6 A- 6 C,  7 A- 7 D or  8   , in accordance with some embodiments. 
     
    
    
     DETAILED DESCRIPTION 
     The following disclosure provides different embodiments, or examples, for implementing features of the provided subject matter. Specific examples of components, materials, values, steps, arrangements, or the like, are described below to simplify the present disclosure. These are, of course, merely examples and are not limiting. Other components, materials, values, steps, arrangements, or the like, are contemplated. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. 
     Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature&#39;s relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. 
     In accordance with some embodiments, a voltage tracking circuit includes a first transistor, a second transistor, a third transistor and a fourth transistor. In some embodiments, the first transistor and second transistor are coupled to each other in a stacked structure, and the third transistor and the fourth transistor are coupled to each other in another stacked structure. 
     In some embodiments, each of a first gate terminal of the first transistor, a third gate terminal of the third transistor and a pad voltage terminal are coupled to each other, and configured to receive a pad voltage. In some embodiments, each of a second gate terminal of the second transistor, a fourth gate terminal of the fourth transistor and a first voltage supply are coupled to each other, and configured to receive a supply voltage. 
     In some embodiments, the first transistor is in a first well, and at least the third transistor is in a second well different from the first well. In some embodiments, the second well is separated from the first well in a first direction. 
     In some embodiments, by positioning at least the first transistor and the third transistor in corresponding separate wells, the voltage tracking circuit has better ESD immunity and occupies less area than other approaches. 
     Integrated Circuit 
       FIG.  1 A  is a schematic diagram of an integrated circuit  100 A, in accordance with some embodiments. 
     Integrated circuit  100 A comprises P-type Metal Oxide Semiconductor (PMOS) transistors M 1 , M 2 , M 3  and M 4  coupled to a voltage supply VDD and a pad terminal PAD. In some embodiments, integrated circuit  100 A corresponds to a pad voltage tracking circuit configured to track a voltage from the pad terminal PAD. In some embodiments, the pad terminal PAD corresponds to an input/output (IO) pad, a voltage supply pad (e.g., VDD), a reference voltage supply (e.g., VSS), or the like. 
     Each PMOS transistor M 1 , M 2 , M 3  and M 4  is positioned in a corresponding well NW 4 , NW 1 , NW 3  and NW 2 . For example, PMOS transistor M 1  is positioned in a well NW 4 , PMOS transistor M 2  is positioned in a well NW 1 , PMOS transistor M 3  is positioned in a well NW 3 , and PMOS transistor M 4  is positioned in a well NW 2 . At least well NW 4 , NW 1 , NW 3  or NW 2  includes an n-type dopant impurity, and is referred to as an N-Well. In some embodiments, at least well NW 4 , NW 1 , NW 3  or NW 2  includes a p-type dopant impurity, and is referred to as a P-Well. 
     PMOS transistor M 1  is positioned in the well NW 4 . PMOS transistor M 1  includes a gate terminal, a drain terminal, a source terminal, and a body terminal. The source terminal of PMOS transistor M 1  is coupled to at least the first voltage supply VDD. The gate terminal of PMOS transistor M 1  is coupled to at least the pad terminal PAD and is configured to receive a pad voltage (not labelled). The body terminal of PMOS transistor M 1  is coupled to the well NW 4 . 
     PMOS transistor M 2  is positioned in the well NW 1 . PMOS transistor M 2  includes a gate terminal, a drain terminal, a source terminal, and a body terminal. The source terminal of PMOS transistor M 2  is coupled to at least the pad terminal PAD and is configured to receive a pad voltage (not labelled). The gate terminal of PMOS transistor M 2  is coupled to at least the voltage supply VDD, and is configured to receive the supply voltage (not labelled). The body terminal of PMOS transistor M 2  is coupled to the well NW 1 . 
     PMOS transistor M 3  is positioned in the well NW 4 . PMOS transistor M 1  includes a gate terminal, a drain terminal, a source terminal, and a body terminal. The source terminal of PMOS transistor M 3  is coupled to the drain terminal of PMOS transistor M 1 . Each of the gate terminal of PMOS transistor M 3 , the gate terminal of PMOS transistor M 1  and the source terminal of PMOS transistor M 2  are coupled together, and are also coupled to the pad terminal PAD. The gate terminal of PMOS transistor M 3  and the gate terminal of PMOS transistor M 1  are configured to receive the pad voltage (not labelled) from the pad terminal PAD. The body terminal of PMOS transistor M 3  is coupled to the well NW 3 . 
     PMOS transistor M 4  is positioned in the well NW 2 . PMOS transistor M 4  includes a gate terminal, a drain terminal, a source terminal, and a body terminal. The source terminal of PMOS transistor M 4  is coupled to the drain terminal of PMOS transistor M 2 . The drain terminal of PMOS transistor M 4  and the drain terminal of PMOS transistor M 3  are coupled together, and are electrically floating. Each of the gate terminal of PMOS transistor M 2 , the gate terminal of PMOS transistor M 4  and the source terminal of PMOS transistor M 1  are coupled together, and are also coupled to the voltage supply VDD. The gate terminal of PMOS transistor M 4  and the gate terminal of PMOS transistor M 2  are configured to receive the supply voltage (not labelled) from the voltage supply VDD. The body terminal of PMOS transistor M 4  is coupled to the well NW 2 . 
     Other transistor types or other numbers of transistors in at least integrated circuit  100 A- 100 B ( FIG.  1 B ),  200 A- 200 B ( FIGS.  2 A- 2 B ),  300 A- 300 C ( FIGS.  3 A- 3 C ),  400 A- 400 C ( FIGS.  4 A- 4 C ),  500 A- 500 C ( FIGS.  5 A- 5 C ),  600 A- 600 C ( FIGS.  6 A- 6 C ) or  700 A- 700 D ( FIGS.  7 A- 7 D ) are within the scope of the present disclosure. 
     In some embodiments, by positioning PMOS transistors M 1 , M 2 , M 3  and M 4  in corresponding separate wells NW 4 , NW 1 , NW 3  and NW 2 , integrated circuit  100 A- 100 B has better ESD immunity and occupies less area than other approaches. 
       FIG.  1 B  is a cross-sectional view of integrated circuit  100 B, in accordance with some embodiments. Integrated circuit  100 B is an embodiment of integrated circuit  100 A. 
     Components that are the same or similar to those in one or more of  FIGS.  1 A- 1 B and  2 A- 8    (shown below) are given the same reference numbers, and detailed description thereof is thus omitted. 
     Integrated circuit  100 B comprises a substrate  102 . In some embodiments, substrate  102  is a p-type substrate. In some embodiments, substrate  102  is an n-type substrate. In some embodiments, substrate  102  includes an elemental semiconductor including silicon or germanium in crystal, polycrystalline, or an amorphous structure; a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and GaInAsP; another suitable material; or combinations thereof. In some embodiments, the alloy semiconductor substrate has a gradient SiGe feature in which the Si and Ge composition change from one ratio at one location to another ratio at another location of the gradient SiGe feature. In some embodiments, the alloy SiGe is formed over a silicon substrate. In some embodiments, first substrate  102  is a strained SiGe substrate. In some embodiments, the semiconductor substrate has a semiconductor on insulator structure, such as a silicon on insulator (SOI) structure. In some embodiments, the semiconductor substrate includes a doped epi layer or a buried layer. In some embodiments, the compound semiconductor substrate has a multilayer structure, or the substrate includes a multilayer compound semiconductor structure. 
     Integrated circuit  100 B further comprises wells NW 1 , NW 2 , NW 3  and NW 4  in substrate  102 . In some embodiments, at least well NW 1 , NW 2 , NW 3  or NW 4  includes a dopant impurity type opposite of the substrate type. In some embodiments, at least well NW 1 , NW 2 , NW 3  or NW 4  includes an n-type dopant impurity, and substrate is a p-type substrate. In some embodiments, at least well NW 1 , NW 2 , NW 3  or NW 4  includes a p-type dopant impurity, and substrate is an n-type substrate. 
     At least well NW 1 , NW 2 , NW 3  or NW 4  extends in a first direction X. Each of wells NW 1 , NW 2 , NW 3  or NW 4  is separated from another of wells NW 1 , NW 2 , NW 3  or NW 4  in the first direction X. In some embodiments, at least well NW 4 , NW 3 , NW 2  or NW 1  is referred to as a body of corresponding PMOS transistor M 1 , M 3 , M 4  or M 2 . 
     Integrated circuit  100 B further comprises regions  104   a ,  104   b ,  104   c  and  104   d . Region  104   a ,  104   b ,  104   c  or  104   d  is within corresponding well NW 4 , NW 3 , NW 2  or NW 1 . In some embodiments, at least region  104   a ,  104   b ,  104   c  or  104   d  includes an n-type dopant impurity. In some embodiments, at least region  104   a ,  104   b ,  104   c  or  104   d  includes a p-type dopant impurity. In some embodiments, region  104   a ,  104   b ,  104   c  or  104   d  is connected to a corresponding body terminal of corresponding PMOS transistor M 1 , M 3 , M 4  or M 2 . 
     Integrated circuit  100 B further comprises gates  106   a ,  106   b ,  106   c  and  106   d . Gate  106   a ,  106   b ,  106   c  or  106   d  is above corresponding well NW 4 , NW 3 , NW 2  or NW 1 . In some embodiments, gate  106   a ,  106   b ,  106   c  or  106   d  is a corresponding gate of corresponding PMOS transistor M 1 , M 3 , M 4  or M 2 . For ease of illustration, gates  106   a  and  106   b  are not shown as being coupled to each other or other elements, and gates  106   c  and  106   d  are not shown as being coupled to each other or other elements. 
     Integrated circuit  100 B further comprises implant regions  108   a ,  108   b ,  108   c  and  108   d . Implant region  108   a ,  108   b ,  108   c  or  108   d  is within corresponding well NW 4 , NW 3 , NW 2  or NW 1 . In some embodiments, at least implant region  108   a ,  108   b ,  108   c  or  108   d  includes a dopant impurity type opposite of the dopant impurity type in the corresponding well NW 4 , NW 3 , NW 2  or NW 1 . In some embodiments, at least implant region  108   a ,  108   b ,  108   c  or  108   d  includes a p-type dopant impurity. In some embodiments, at least implant region  108   a ,  108   b ,  108   c  or  108   d  includes an n-type dopant impurity. In some embodiments, implant region  108   a  or  108   b  is the corresponding source terminal of corresponding PMOS transistor M 1  or M 3 . In some embodiments, implant region  108   c  or  108   d  is the corresponding drain terminal of corresponding PMOS transistor M 4  or M 2 . 
     Integrated circuit  100 B further comprises implant regions  110   a ,  110   b ,  110   c  and  110   d . Implant region  110   a ,  110   b ,  110   c  or  110   d  is within corresponding well NW 4 , NW 3 , NW 2  or NW 1 . In some embodiments, at least implant region  110   a ,  110   b ,  110   c  or  110   d  includes a dopant impurity type opposite of the dopant impurity type in the corresponding well NW 4 , NW 3 , NW 2  or NW 1 . In some embodiments, at least implant region  110   a ,  110   b ,  110   c  or  110   d  includes a p-type dopant impurity. In some embodiments, at least implant region  110   a ,  110   b ,  110   c  or  110   d  includes an n-type dopant impurity. In some embodiments, implant region  110   a  or  110   b  is the corresponding drain terminal of corresponding PMOS transistor M 1  or M 3 . In some embodiments, implant region  110   c  or  110   d  is the corresponding source terminal of corresponding PMOS transistor M 4  or M 2 . 
     Implant region  110   a  is electrically coupled to implant region  108   b  and corresponds to the connection between the drain terminal of PMOS transistor M 1  and the source terminal of PMOS transistor M 3  of  FIG.  1 A . Implant region  110   b  is electrically coupled to implant region  108   c  and corresponds to the connection between the drain terminal of PMOS transistor M 3  and the drain terminal of PMOS transistor M 4  of  FIG.  1 A . Implant region  110   c  is electrically coupled to implant region  108   d  and corresponds to the connection between the drain terminal of PMOS transistor M 2  and the source terminal of PMOS transistor M 4  of  FIG.  1 A . 
     A parasitic pnp transistor  112   a ,  112   b ,  112   c  or  112   d  is formed by corresponding well NW 4 , NW 3 , NW 2  or NW 1 , corresponding implant region  108   a ,  108   b ,  108   c  or  108   d  and corresponding implant region  110   a ,  110   b ,  110   c  or  110   d . For example, the well NW 4  forms a base of parasitic pnp transistor  112   a , the implant region  108   a  forms an emitter of parasitic pnp transistor  112   a  and region  110   a  forms a collector of parasitic pnp transistor  112   a . Similarly, the well NW 3  forms a base of parasitic pnp transistor  112   b , the implant region  108   b  forms an emitter of parasitic pnp transistor  112   b  and region  110   b  forms a collector of parasitic pnp transistor  112   a . Similarly, the well NW 2  forms a base of parasitic pnp transistor  112   c , the implant region  108   c  forms a collector of parasitic pnp transistor  112   c  and region  110   c  forms an emitter of parasitic pnp transistor  112   a . Similarly, the well NW 1  forms a base of parasitic pnp transistor  112   d , the implant region  108   d  forms a collector of parasitic pnp transistor  112   d  and region  110   d  forms an emitter of parasitic pnp transistor  112   d . In some embodiments, at least parasitic pnp transistor  112   a ,  112   b ,  112   c  or  112   d  is a parasitic bipolar junction transistor (BJT). 
     In some embodiments, at least parasitic pnp transistor  112   a ,  112   b ,  112   c  or  112   d  is configured to provide a current path for an ESD event. In some embodiments, the ESD event corresponds to a voltage of the pad terminal PAD being greater than a voltage of the supply voltage VDD. In some embodiments, at least parasitic pnp transistor  112   a ,  112   b ,  112   c  or  112   d  is configured to block a current path for the ESD event. 
     In some embodiments, by positioning PMOS transistors M 1 , M 2 , M 3  and M 4  in corresponding separate wells NW 4 , NW 1 , NW 3  and NW 2 , integrated circuit  100 B has better ESD immunity and occupies less area than other approaches. 
       FIG.  2 A  is a schematic diagram of an integrated circuit  200 A, in accordance with some embodiments. Integrated circuit  200 A is a variation of integrated circuit  100 A, and similar detailed description is therefore omitted. For example, integrated circuit  200 A illustrates an example of where additional PMOS transistors M 5  and M 6  are utilized in the stacked PMOS configuration of the PAD voltage tracking circuit. 
     In comparison with integrated circuit  100 A of  FIG.  1 A , integrated circuit  200 A further includes PMOS transistors M 5  and M 6  and corresponding wells NW 5  and NW 6 . 
     PMOS transistor M 5  or M 6  is positioned in corresponding well NW 5  or NW 6 . For example, PMOS transistor M 5  is positioned in a well NW 5 , and PMOS transistor M 6  is positioned in a well NW 6 . At least well NW 5  or NW 6  includes an n-type dopant impurity. In some embodiments, at least well NW 5  or NW 6  includes a p-type dopant impurity. 
     PMOS transistor M 5  includes a gate terminal, a drain terminal, a source terminal, and a body terminal. The source terminal of PMOS transistor M 5  is coupled to the drain terminal of PMOS transistor M 3  in  FIG.  2 A . Each of the gate terminal of PMOS transistor M 5 , the gate terminal of PMOS transistor M 1 , the gate terminal of PMOS transistor M 3  and the source terminal of PMOS transistor M 2  are coupled together in  FIG.  2 A , and are also coupled to the pad terminal PAD. The gate terminal of PMOS transistor M 5  is configured to receive the pad voltage (not labelled) from the pad terminal PAD. The body terminal of PMOS transistor M 5  is coupled to the well NW 5 . 
     PMOS transistor M 6  includes a gate terminal, a drain terminal, a source terminal, and a body terminal. The source terminal of PMOS transistor M 6  is coupled to the drain terminal of PMOS transistor M 4  in  FIG.  2 A . The drain terminal of PMOS transistor M 6  and the drain terminal of PMOS transistor M 5  are coupled together, and are electrically floating. Each of the gate terminal of PMOS transistor M 6 , the gate terminal of PMOS transistor M 2 , the gate terminal of PMOS transistor M 4  and the source terminal of PMOS transistor M 1  are coupled together in  FIG.  2 A , and are also coupled to the voltage supply VDD. The gate terminal of PMOS transistor M 6  is configured to receive the supply voltage (not labelled) from the voltage supply VDD. The body terminal of PMOS transistor M 6  is coupled to the well NW 6 . 
     In some embodiments, by positioning PMOS transistors M 1 , M 2 , M 3 , M 4 , M 5  and M 6  in corresponding separate wells NW 4 , NW 1 , NW 3 , NW 2 , NW 5  and NW 6 , integrated circuit  200 A- 200 B has better ESD immunity and occupies less area than other approaches. 
       FIG.  2 B  is a cross-sectional view of integrated circuit  200 B, in accordance with some embodiments. Integrated circuit  200 B is an embodiment of integrated circuit  200 A. 
     Integrated circuit  200 B is a variation of integrated circuit  100 B, and similar detailed description is therefore omitted. For example, integrated circuit  100 B illustrates an example of where additional PMOS transistors M 5  and M 6  are utilized in the stacked PMOS configuration of the PAD voltage tracking circuit (e.g., integrated circuit  100 A of  FIG.  1 A ). 
     In comparison with integrated circuit  100 B of  FIG.  1 B , integrated circuit  200 B further includes PMOS transistors M 5  and M 6  in corresponding wells NW 5  and NW 6 . 
     In comparison with integrated circuit  100 B of  FIG.  1 B , integrated circuit  200 B further includes wells NW 5  and NW 6 , regions  204   e  and  204   f , gates  206   e  and  206   f , implant regions  208   e  and  208   f , and implant regions  210   e  and  210   f.    
     Wells NW 5  and NW 6  are in substrate  102 . In some embodiments, at least well NW 5  or NW 6  includes a dopant impurity type opposite of the substrate type. In some embodiments, at least well NW 5  or NW 6  includes an n-type dopant impurity, and substrate is a p-type substrate. In some embodiments, at least well NW 5  or NW 6  includes a p-type dopant impurity, and substrate is an n-type substrate. 
     At least well NW 5  or NW 6  extends in a first direction X. Each of wells NW 1 , NW 2 , NW 3 , NW 4 , NW 5  or NW 6  is separated from another of wells NW 1 , NW 2 , NW 3 , NW 4 , NW 5  or NW 6  in the first direction X. In some embodiments, at least well NW 5  or NW 6  is referred to as a body of corresponding PMOS transistor M 5  or M 6 . 
     Region  204   e  or  204   f  is within corresponding well NW 5  or NW 6 . In some embodiments, at least region  204   e  or  204   f  includes an n-type dopant impurity. In some embodiments, at least region  204   e  or  204   f  includes a p-type dopant impurity. In some embodiments, region  204   e  or  204   f  is connected to a corresponding body terminal of corresponding PMOS transistor M 5  or M 6 . 
     Gate  206   e  or  206   f  is above corresponding well NW 5  or NW 6 . In some embodiments, gate  206   e  or  206   f  is a corresponding gate of corresponding PMOS transistor M 5  or M 6 . For ease of illustration, gates  106   a ,  106   b  and  206   e  are not shown as being coupled to each other or other elements, and gates  106   c ,  106   d  and  206   f  are not shown as being coupled to each other or other elements. 
     Implant region  208   e  or  208   f  is within corresponding well NW 5  or NW 6 . In some embodiments, at least implant region  208   e  or  208   f  includes a dopant impurity type opposite of the dopant impurity type in the corresponding well NW 5  or NW 6 . In some embodiments, at least implant region  208   e  or  208   f  includes a p-type dopant impurity. In some embodiments, at least implant region  208   e  or  208   f  includes an n-type dopant impurity. In some embodiments, implant region  208   e  is the source terminal of PMOS transistor M 5 . In some embodiments, implant region  208   f  is the drain terminal of PMOS transistor M 6 . 
     Implant region  210   e  or  210   f  is within corresponding NW 5  or NW 6 . In some embodiments, at least implant region  210   e  or  210   f  includes a dopant impurity type opposite of the dopant impurity type in the corresponding well NW 5  or NW 6 . In some embodiments, at least implant region  210   e  or  210   f  includes a p-type dopant impurity. In some embodiments, at least implant region  210   e  or  210   f  includes an n-type dopant impurity. In some embodiments, implant region  210   e  is the drain terminal of PMOS transistor M 5 . In some embodiments, implant region  210   f  is the source terminal of PMOS transistor M 6 . 
     In comparison with integrated circuit  100 B of  FIG.  1 B , implant region  110   b  of  FIG.  2 B  is not electrically coupled to implant region  108   c.    
     Implant region  110   b  of  FIG.  2 B  is electrically coupled to implant region  208   e , and corresponds to the connection between the drain terminal of PMOS transistor M 3  and the source terminal of PMOS transistor M 5  of  FIG.  2 A . Implant region  108   c  of  FIG.  2 B  is electrically coupled to implant region  210   f , and corresponds to the connection between the drain terminal of PMOS transistor M 4  and the source terminal of PMOS transistor M 6  of  FIG.  2 A . Implant region  210   e  is electrically coupled to implant region  208   f  and corresponds to the connection between the drain terminal of PMOS transistor M 5  and the drain terminal of PMOS transistor M 6  of  FIG.  2 A . 
     A parasitic pnp transistor  212   e  or  212   f  is formed by corresponding well NW 5  or NW 6 , corresponding implant region  208   e  or  208   f  and corresponding implant region  210   e  or  210   f . For example, the well NW 5  forms a base of parasitic pnp transistor  212   e , the implant region  208   e  forms an emitter of parasitic pnp transistor  212   e  and region  210   e  forms a collector of parasitic pnp transistor  212   e . Similarly, the well NW 6  forms a base of parasitic pnp transistor  212   f , the implant region  208   f  forms a collector of parasitic pnp transistor  212   f  and region  210   f  forms an emitter of parasitic pnp transistor  212   f . In some embodiments, at least parasitic pnp transistor  112   a ,  112   b ,  112   c ,  112   d ,  212   e  or  212   f  is a parasitic BJT. 
     In some embodiments, at least parasitic pnp transistor  112   a ,  112   b ,  112   c ,  112   d ,  212   e  or  212   f  is configured to provide a current path for an ESD event. In some embodiments, at least parasitic pnp transistor  112   a ,  112   b ,  112   c ,  112   d ,  212   e  or  212   f  is configured to block a current path for the ESD event. 
     In some embodiments, by positioning PMOS transistors M 1 , M 2 , M 3 , M 4 , M 5  or M 6  in corresponding separate wells NW 4 , NW 1 , NW 3 , NW 2 , NW 5  or NW 6 , integrated circuit  200 B has better ESD immunity and occupies less area than other approaches. In some embodiments, by having additional PMOS transistors M 1 , M 2 , M 3 , M 4 , M 5  or M 6  positioned in corresponding additional separate wells NW 4 , NW 1 , NW 3 , NW 2 , NW 5  or NW 6 , integrated circuit  200 B has better ESD immunity than other approaches with less transistors positioned in corresponding wells. 
       FIG.  3 A  is a circuit diagram of an integrated circuit  300 A, in accordance with some embodiments.  FIG.  3 B  is a circuit diagram of an equivalent circuit  300 B of integrated circuit  300 A, in accordance with some embodiments.  FIG.  3 C  is a cross-sectional view of integrated circuit  300 A, in accordance with some embodiments. 
     Integrated circuit  300 A is an embodiment of integrated circuit  100 A of  FIG.  1 A . 
     Integrated circuit  300 A comprises PMOS transistors M 1 , M 2 , M 3  and M 4  coupled to the voltage supply VDD and the pad terminal PAD. 
     In comparison with integrated circuit  100 A of  FIG.  1 A , PMOS transistor M 1  is positioned in a well  320   a  ( FIG.  3 C ), and PMOS transistors M 2 , M 3  and M 4  are positioned in a well  320   b  ( FIG.  3 C ) different from well  320   a.    
     The body terminal of PMOS transistor M 1  and the source terminal of PMOS transistor M 1  are coupled together, and are further coupled to the first voltage supply VDD. By coupling the body terminal of PMOS transistor M 1 , the source terminal of PMOS transistor M 1  and the voltage supply VDD, the parasitic PNP transistor  112   a  of  FIG.  1 A  is changed to a parasitic diode D 1  ( FIG.  3 B ). 
     PMOS transistors M 2 , M 3  and M 4  are positioned in a same well, (e.g., N-well  320   b ), and therefore the body terminal of PMOS transistor M 2 , the body terminal of PMOS transistor M 3 , and the body terminal of PMOS transistor M 4  are coupled together. 
     Each of the body terminal of PMOS transistor M 2 , the body terminal of PMOS transistor M 3 , the body terminal of PMOS transistor M 4 , the drain terminal of PMOS transistor M 3  and the drain terminal of PMOS transistor M 4  are coupled together at a node F 1 . In some embodiments, node F 1  is electrically floating. In some embodiments, node F 1  is electrically coupled to supply voltage VDD by PMOS transistors M 1  and M 3 . In some embodiments, node F 1  is electrically coupled to pad terminal PAD by PMOS transistors M 2  and M 4 . 
       FIG.  3 B  is a circuit diagram of an equivalent circuit  300 B of integrated circuit  300 A, in accordance with some embodiments. 
     Equivalent circuit  300 B is a variation of integrated circuit  300 A showing parasitic elements  330  of integrated circuit  300 A, and similar detailed description is therefore omitted. For example, equivalent circuit  300 B corresponds to integrated circuit  300 A of  FIG.  3 A  with parasitic elements  330  (e.g., diode D 1 , parasitic transistors Q 2  and Q 3 ), in accordance with some embodiments. 
     Equivalent circuit  300 B includes integrated circuit  300 A and parasitic elements  330 . Parasitic elements  330  include a diode D 1 , a parasitic transistor Q 2  and a parasitic transistor Q 3 . 
     Each of an anode of the diode D 1 , the source terminal of PMOS transistor M 3 , the drain terminal of PMOS transistor M 1 , and an emitter of parasitic transistor Q 3  are coupled together. Each of a cathode of the diode D 1 , the body terminal of PMOS transistor M 1 , the source terminal of PMOS transistor M 1 , the gate of PMOS transistor M 2 , the gate of PMOS transistor M 4  and the first voltage supply VDD are coupled together. In some embodiments, diode D 1  is forward biased, and is configured to allow a current flow through diode D 1  and a parasitic current path. In some embodiments, diode D 1  is reverse biased, and is configured to block a current from flowing through diode D 1  and the parasitic current path. 
     Each of a base of parasitic transistor Q 3 , a collector of parasitic transistor Q 3 , a base of parasitic transistor Q 2 , a collector of parasitic transistor Q 2 , the drain terminal of PMOS transistor M 3 , the drain terminal of PMOS transistor M 4 , the body terminal of PMOS transistor M 2 , the body terminal of PMOS transistor M 3 , and the body terminal of PMOS transistor M 4  are coupled together at node F 1 . 
     Each of an emitter of parasitic transistor Q 2 , the source terminal of PMOS transistor M 2 , the gate of PMOS transistor M 1 , the gate of PMOS transistor M 3  and the pad terminal PAD are coupled together. 
     In some embodiments, during an ESD event with positive stress from the pad terminal PAD to the voltage supply VDD, the voltage of the pad terminal PAD is greater than the voltage of the voltage supply VDD, and therefore PMOS transistors M 2  and M 4  are turned on, and PMOS transistors M 1  and M 3  are turned off, and the voltage of the pad terminal PAD will be placed at node F 1 . In these embodiments, when the voltage of node F 1  is equal to the voltage of the pad terminal PAD, the whole voltage stress of the ESD event will be placed across PMOS transistors M 3  and M 1 , thereby turning on parasitic transistor Q 3  and diode Q 3  to conduct the discharged ESD current to the voltage supply VDD. Thus, since the ESD current path includes two parasitic elements (e.g., parasitic diode D 1  and parasitic transistor Q 3 ) positioned in different wells ( 320   a  and  320   b ), the ESD immunity is boosted compared to other approaches. 
     In some embodiments, during an ESD event with negative stress from the voltage supply VDD to the pad terminal PAD, the voltage of the voltage supply VDD is greater than the voltage of the pad terminal PAD, and therefore PMOS transistors M 1  and M 3  are turned on, and PMOS transistors M 2  and M 4  are turned off, and the voltage of the voltage supply VDD will be placed at node F 1 . In these embodiments, when the voltage of node F 1  is equal to the voltage of the voltage supply VDD, the whole voltage stress of the ESD event will be placed across PMOS transistors M 2  and M 4 , thereby turning on parasitic transistor Q 2  to conduct the discharged ESD current to the pad terminal PAD. Thus, the ESD current path includes one parasitic element (e.g., parasitic transistor Q 2 ). 
     In some embodiments, the 2-stacked PMOS structure utilizing PMOS transistors M 2  and M 4  can be reduced to a single PMOS transistor (either M 2  or M 4 ), if negative stress ESD events are not an issue. 
       FIG.  3 C  is a cross-sectional view of integrated circuit  300 A, in accordance with some embodiments. 
     Integrated circuit  300 C is an embodiment of integrated circuit  100 B of  FIG.  1 B , and similar detailed description is therefore omitted. 
     Integrated circuit  300 C illustrates an example of where PMOS transistor M 1  is positioned in well  320   a , and PMOS transistors M 2 , M 3  and M 4  are positioned in well  320   b . In other words, wells NW 2 , NW 3  and NW 4  of  FIG.  1 B  are merged into well  320   b.    
     Integrated circuit  300 C comprises substrate  102 , wells  320   a  and  320   b , regions  304   a  and  304   b , gates  106   a ,  106   b ,  106   c  and  106   d , implant regions  308   a ,  308   b ,  308   c  and  308   d , and implant regions  310   a ,  310   b ,  310   c  and  310   d.    
     In comparison with integrated circuit  100 B of  FIG.  1 B , well  320   a  replaces well NW 1 , and well  320   b  replaces wells NW 2 , NW 3  and NW 4  of  FIG.  1 B , and similar detailed description is therefore omitted. In other words, wells NW 2 , NW 3  and NW 4  of  FIG.  1 B  are merged into well  320   b , and similar detailed description is therefore omitted. Well  320   b  is different from well  320   a . Well  320   b  is separated from well  320   a  in the first direction X. 
     Gate  106   a  is above well  320   a , and gates  106   b ,  106   c  and  106   d  are above well  320   b . For ease of illustration, gates  106   a  and  106   b  are not shown as being coupled to each other or other elements, and gates  106   c  and  106   d  are not shown as being coupled to each other or other elements. 
     In comparison with integrated circuit  100 B of  FIG.  1 B , region  304   a  replaces region  104   a , and region  304   b  replaces regions  104   b ,  104   c  and  104   d  of  FIG.  1 B , and similar detailed description is therefore omitted. In other words, regions  104   b ,  104   c ,  104   d  of  FIG.  1 B  are merged into region  304   a , and similar detailed description is therefore omitted. Region  304   a  is within well  320   a , and region  304   b  is within well  320   b.    
     In comparison with integrated circuit  100 B of  FIG.  1 B , implant regions  308   a ,  308   b ,  308   c  and  308   d  replace corresponding implant regions  108   a ,  108   b ,  108   c  and  108   d , and implant regions  310   a ,  310   b ,  310   c  and  310   d  replace corresponding implant regions  110   a ,  110   b ,  110   c  and  110   d , and similar detailed description is therefore omitted. 
     Implant regions  308   a  and  310   a  are within well  320   a . Implant regions  308   b ,  308   c  and  308   d  and implant regions  310   b ,  310   c  and  310   d  are within well  320   b.    
     Each of region  304   a , implant region  308   a  and voltage supply VDD are electrically coupled together and corresponds to the connection between the body terminal of PMOS transistor M 1 , the source terminal of PMOS transistor M 1  and the voltage supply VDD of  FIG.  3 A . 
     Implant region  310   a  is electrically coupled to implant region  308   b  and corresponds to the connection between the drain terminal of PMOS transistor M 1  and the source terminal of PMOS transistor M 3  of  FIG.  3 A . 
     Each of implant region  310   b , implant region  308   c  and region  304   b  are electrically coupled together at node F 1 , and corresponds to the connection between the drain terminal of PMOS transistor M 3 , the drain terminal of PMOS transistor M 4  of  FIG.  3 A , the body terminal of PMOS transistor M 2 , the body terminal of PMOS transistor M 3  and the body terminal of PMOS transistor M 4  of  FIG.  3 A . 
     Implant region  310   c  is electrically coupled to implant region  308   d  and corresponds to the connection between the drain terminal of PMOS transistor M 2  and the source terminal of PMOS transistor M 4  of  FIG.  3 A . 
     Implant region  310   d  is electrically coupled to the pad terminal PAD and corresponds to the connection between the source terminal of PMOS transistor M 2  and the pad terminal PAD of  FIG.  3 A . 
     In comparison with integrated circuit  100 B of  FIG.  1 B , parasitic diode D 1  replaces parasitic pnp transistor  112   a  of  FIG.  1 B , parasitic transistor Q 3  replaces parasitic pnp transistor  112   b  of  FIG.  1 B , and parasitic transistor Q 2  replaces parasitic pnp transistors  112   c  and  112   d  of  FIG.  1 B , and similar detailed description is therefore omitted. 
     Parasitic diode D 1  is formed by well  320   a  and implant region  310   a . For example, implant region  310   a  corresponds to the anode of diode D 1 , and well  320   a  corresponds to the cathode of diode D 1 . 
     Parasitic transistor Q 3  is formed by well  320   b , implant region  308   b  and implant region  310   b . For example, the well  320   b  forms a base of parasitic transistor Q 3 , the implant region  308   b  forms an emitter of parasitic transistor Q 3  and region  310   b  forms a collector of parasitic transistor Q 3 . 
     Parasitic transistor Q 2  is formed by well  320   b , implant region  308   c  and implant region  310   d . For example, the well  320   b  forms a base of parasitic transistor Q 2 , the implant region  310   d  forms an emitter of parasitic transistor Q 2  and region  308   c  forms a collector of parasitic transistor Q 2 . 
     In some embodiments, by positioning PMOS transistor M 1  in well  320   a , and by positioning PMOS transistors M 2 , M 3  and M 4  in a separate well (well  320   b ), the parasitic current path of integrated circuit  300 C includes parasitic elements (e.g., parasitic diode D 1  and parasitic transistors Q 2  and Q 3 ) positioned in different wells ( 320   a  and  320   b ), thereby improving the ESD immunity of integrated circuit  300 A- 300 C compared to other approaches, and integrated circuit  300 A- 300 C occupies less area than other approaches with similar performance. 
       FIG.  4 A  is a circuit diagram of an integrated circuit  400 A, in accordance with some embodiments.  FIG.  4 B  is a circuit diagram of an equivalent circuit  400 B of integrated circuit  400 A, in accordance with some embodiments.  FIG.  4 C  is a cross-sectional view of integrated circuit  400 A, in accordance with some embodiments. 
     Integrated circuit  400 A is an embodiment of integrated circuit  100 A of  FIG.  1 A . 
     Integrated circuit  400 A comprises PMOS transistors M 1 , M 2 , M 3  and M 4  coupled to the voltage supply VDD and the pad terminal PAD. 
     Integrated circuit  400 A is a variation of integrated circuit  300 A of  FIG.  3 A . In comparison with integrated circuit  300 A of  FIG.  3 A , PMOS transistor M 1  of integrated circuit  400 A is positioned in well  320   a  ( FIG.  4 C ), PMOS transistors M 3  and M 4  of integrated circuit  400 A are positioned in well  420   a  ( FIG.  4 C ), and PMOS transistor M 2  of integrated circuit  400 A is positioned in a well  420   b  ( FIG.  4 C ), and similar detailed description is therefore omitted. In some embodiments, each of wells  320   a ,  420   a  and  420   b  are different from each other. 
     In comparison with integrated circuit  300 A of  FIG.  3 A , PMOS transistor M 2  of  FIGS.  4 A- 4 C  is in well  420   b , and therefore the body terminal of PMOS transistor M 2  is no longer coupled to the body terminal of PMOS transistor M 3  and the body terminal of PMOS transistor M 4 . The body terminal of PMOS transistor M 2  in  FIGS.  4 A- 4 C  is coupled to node F 2 . In some embodiments, node F 2  is charged from the pad terminal PAD by a parasitic body diode of PMOS transistor M 4 . In some embodiments, the parasitic body diode is formed between the gate and drain of PMOS transistor M 4 . 
     For example, in some embodiments, during an ESD event, the voltage of the pad terminal PAD is sufficient to cause the parasitic body diode to turn on and conduct resulting in node F 2  charging to the voltage of the pad terminal PAD. Thus, in these embodiments, node F 2  is able to track the voltage of the pad terminal PAD without being directly coupled to the body terminal of PMOS transistor M 3  and the body terminal of PMOS transistor M 4  nwell controller that means no PMOS/NMOS connected to F 2 . However, node F 2  voltage could track to PAD by parasitic BJT. In some embodiments, a parasitic body diode is formed by implant  410   d  and well  420   b . In some embodiments, a parasitic body diode is formed by implant  408   d  and well  420   b.    
     PMOS transistors M 3  and M 4  are positioned in a same well, (e.g., well  420   a ), and therefore the body terminal of PMOS transistor M 3  and the body terminal of PMOS transistor M 4  are coupled together. Each of the body terminal of PMOS transistor M 3 , the body terminal of PMOS transistor M 4 , the drain terminal of PMOS transistor M 3  and the drain terminal of PMOS transistor M 4  are coupled together at node F 1 . In some embodiments, node F 1  is electrically floating. In some embodiments, node F 1  is electrically coupled to supply voltage VDD by PMOS transistors M 1  and M 3 . In some embodiments, node F 1  is electrically coupled to pad terminal PAD by PMOS transistors M 2  and M 4 . 
       FIG.  4 B  is a circuit diagram of an equivalent circuit  400 B of integrated circuit  400 A, in accordance with some embodiments. 
     Equivalent circuit  400 B is a variation of integrated circuit  400 A showing parasitic elements  430  of integrated circuit  400 A, and similar detailed description is therefore omitted. For example, equivalent circuit  400 B corresponds to integrated circuit  400 A of  FIG.  4 A  with parasitic elements  430  (e.g., diode D 1 , parasitic transistors Q 2 ′, Q 3  and Q 4 ), in accordance with some embodiments. 
     Equivalent circuit  400 B includes integrated circuit  400 A and parasitic elements  430 . Parasitic elements  430  are a variation of parasitic elements  330  of  FIG.  3 B , and similar detailed description is therefore omitted. Parasitic elements  430  include diode D 1  of  FIG.  3 B , a parasitic transistor Q 2 ′, parasitic transistor Q 3  of  FIG.  3 B  and a parasitic transistor Q 4 . 
     In comparison with parasitic elements  330  of  FIGS.  3 B- 3 C , parasitic transistor Q 2 ′ and parasitic transistor Q 4  replace parasitic transistor Q 2  of  FIG.  3 B , and similar detailed description is therefore omitted. 
     In comparison with parasitic elements  330  of  FIGS.  3 B- 3 C , for  FIG.  4 B , each of the base of parasitic transistor Q 3 , the collector of parasitic transistor Q 3 , a base of parasitic transistor Q 2 ′, a collector of parasitic transistor Q 2 ′, the drain terminal of PMOS transistor M 3 , the drain terminal of PMOS transistor M 4 , the body terminal of PMOS transistor M 3 , and the body terminal of PMOS transistor M 4  are coupled together at node F 1 . 
     In  FIG.  4 B , each of an emitter of parasitic transistor Q 4 , the source terminal of PMOS transistor M 2 , the gate of PMOS transistor M 1 , the gate of PMOS transistor M 3  and the pad terminal PAD are coupled together. In  FIG.  4 B , a base of parasitic transistor Q 4  is coupled to the body terminal of PMOS transistor M 2 . 
     In  FIG.  4 B , each of an emitter of parasitic transistor Q 2 ′, a collector of parasitic transistor Q 4 , the drain terminal of PMOS transistor M 2  and the source of PMOS transistor M 4  are coupled together. 
     In some embodiments, during an ESD event with positive stress from the pad terminal PAD to the voltage supply VDD, the voltage of the pad terminal PAD is greater than the voltage of the voltage supply VDD, and therefore PMOS transistors M 2  and M 4  are turned on, and PMOS transistors M 1  and M 3  are turned off, and the voltage of the pad terminal PAD will be placed at node F 1 . In these embodiments, when the voltage of node F 1  is equal to the voltage of the pad terminal PAD, the whole voltage stress of the ESD event will be placed across PMOS transistors M 3  and M 1 , thereby turning on parasitic transistor Q 3  and diode D 1  to conduct the discharged ESD current to the voltage supply VDD. Thus, since the parasitic current path includes two parasitic elements (e.g., parasitic diode D 1  and parasitic transistor Q 3 ) positioned in different wells ( 320   a  and  420   a ), the ESD immunity is boosted compared to other approaches. 
     In some embodiments, during an ESD event with negative stress from the voltage supply VDD to the pad terminal PAD, the voltage of the voltage supply VDD is greater than the voltage of the pad terminal PAD, and therefore PMOS transistors M 1  and M 3  are turned on, and PMOS transistors M 2  and M 4  are turned off, and the voltage of the voltage supply VDD will be placed at node F 1 . In these embodiments, when the voltage of node F 1  is equal to the voltage of the voltage supply VDD, the whole voltage stress of the ESD event will be placed across PMOS transistors M 2  and M 4 , thereby turning on parasitic transistors Q 2 ′ and Q 4  to conduct the discharged ESD current to the pad terminal PAD. Thus, since the ESD current path includes two parasitic elements (e.g., parasitic transistor Q 4  and parasitic transistor Q 2 ′) positioned in different wells ( 420   a  and  420   b ), the ESD immunity is boosted compared to other approaches. 
       FIG.  4 C  is a cross-sectional view of integrated circuit  400 A, in accordance with some embodiments. 
     Integrated circuit  400 C is an embodiment of integrated circuit  100 B of  FIG.  1 B  or integrated circuit  300 B of  FIG.  3 B , and similar detailed description is therefore omitted. 
     Integrated circuit  400 C illustrates an example of where PMOS transistor M 1  is positioned in well  320   a , PMOS transistors M 3  and M 4  are positioned in well  420   a , and PMOS transistor M 2  is positioned in well  420   b . In comparison with integrated circuit  100 B of  FIG.  1 B , wells NW 3  and NW 4  of  FIG.  1 B  are merged into well  420   a.    
     Integrated circuit  400 C comprises substrate  102 , wells  320   a ,  420   a  and  420   b , regions  304   a ,  404   b  and  404   d , gates  106   a ,  106   b ,  106   c  and  106   d , implant regions  308   a ,  408   b ,  408   c  and  408   d , and implant regions  310   a ,  410   b ,  410   c  and  410   d.    
     In comparison with integrated circuit  100 B of  FIG.  1 B , well  320   a  replaces well NW 1 , and well  420   a  replaces wells NW 3  and NW 2  of  FIG.  1 B , and well  420   b  replaces wells NW 1  of  FIG.  1 B , and similar detailed description is therefore omitted. In other words, wells NW 2  and NW 3  of  FIG.  1 B  are merged into well  420   a , and similar detailed description is therefore omitted. Each of wells  320   a ,  420   a  and  420   b  are separated from each other in the first direction X. In some embodiments, each of wells  320   a ,  420   a  and  420   b  are different from each other. 
     Gate  106   a  is above well  320   a , gates  106   b  and  106   c  are above well  420   a  and gate  106   d  is above well  420   b . For ease of illustration, gates  106   a  and  106   b  are not shown as being coupled to each other or other elements, and gates  106   c  and  106   d  are not shown as being coupled to each other or other elements. 
     In comparison with integrated circuit  100 B of  FIG.  1 B , region  404   b  replaces regions  104   b  and  104   c  of  FIG.  1 B , and region  404   d  replaces regions  104   d  of  FIG.  1 B , and similar detailed description is therefore omitted. Stated differently, regions  104   b  and  104   c  of  FIG.  1 B  are merged into region  404   b , and similar detailed description is therefore omitted. Region  304   a  is within well  320   a , region  404   b  is within well  420   a  and region  404   d  is within well  420   b.    
     Integrated circuit  400 C is a variation of integrated circuit  300 C of  FIG.  3 C , and similar detailed description is therefore omitted. In comparison with integrated circuit  300 C of  FIG.  3 C , implant regions  408   b ,  408   c  and  408   d  replace corresponding implant regions  308   b ,  308   c  and  308   d , and implant regions  410   b ,  410   c  and  410   d  replace corresponding implant regions  310   b ,  310   c  and  310   d , and similar detailed description is therefore omitted. 
     Implant regions  408   b  and  408   c  and implant regions  410   b  and  410   c  are within well  420   a . Implant region  408   d  and implant region  410   d  are within well  420   b.    
     Implant region  310   a  is electrically coupled to implant region  408   b  and corresponds to the connection between the drain terminal of PMOS transistor M 1  and the source terminal of PMOS transistor M 3  of  FIG.  4 A . 
     Each of implant region  410   b , implant region  408   c  and region  404   b  are electrically coupled together at node F 1 , and corresponds to the connection between the drain terminal of PMOS transistor M 3 , the drain terminal of PMOS transistor M 4  of  FIG.  4 A , the body terminal of PMOS transistor M 3  and the body terminal of PMOS transistor M 4 . 
     Region  404   d  is electrically coupled to node F 2 , and corresponds to the connection between the body terminal of PMOS transistor M 2  and node F 2  in  FIG.  4 A . 
     Implant region  410   c  is electrically coupled to implant region  408   d  and corresponds to the connection between the drain terminal of PMOS transistor M 2  and the source terminal of PMOS transistor M 4  of  FIG.  4 A . 
     Implant region  410   d  is electrically coupled to the pad terminal PAD and corresponds to the connection between the source terminal of PMOS transistor M 2  and the pad terminal PAD of  FIG.  4 A . 
     Integrated circuit  400 C includes parasitic diode D 1  of  FIG.  3 C , a parasitic transistor Q 2 ′, parasitic transistor Q 3  of  FIG.  3 C  and a parasitic transistor Q 4 . In comparison with integrated circuit  300 C of  FIG.  3 C , parasitic transistor Q 2 ′ and parasitic transistor Q 4  replace parasitic Q 2  of  FIG.  3 C , and similar detailed description is therefore omitted. 
     In comparison with integrated circuit  100 B of  FIG.  1 B , parasitic transistor Q 2 ′ replaces parasitic pnp transistor  112   c  of  FIG.  1 B , and parasitic transistor Q 4  replaces parasitic pnp transistor  112   d  of  FIG.  1 B , and similar detailed description is therefore omitted. 
     Parasitic transistor Q 2 ′ is formed by well  420   a , implant region  408   c  and implant region  410   c . For example, the well  420   a  forms a base of parasitic transistor Q 2 ′, the implant region  410   c  forms an emitter of parasitic transistor Q 2 ′ and region  408   c  forms a collector of parasitic transistor Q 2 ′. 
     Parasitic transistor Q 4  is formed by well  420   b , implant region  408   d  and implant region  410   d . For example, the well  420   b  forms a base of parasitic transistor Q 4 , the implant region  410   d  forms an emitter of parasitic transistor Q 4  and region  408   d  forms a collector of parasitic transistor Q 4 . 
     In some embodiments, by positioning PMOS transistor M 1  in well  320   a , by positioning PMOS transistors M 3  and M 4  in a separate well (well  420   a ), and by positioning PMOS transistor M 2  in another separate well (well  420   b ), a parasitic current path of integrated circuit  400 C includes parasitic elements (e.g., parasitic diode D 1  and parasitic transistor Q 3 ) positioned in different wells ( 320   a  and  420   a ), and another parasitic current path of integrated circuit  400 C includes parasitic elements (e.g., parasitic transistors Q 2 ′ and Q 4 ) positioned in different wells ( 420   a  and  420   b ), thereby improving the ESD immunity of integrated circuit  400 A- 400 C compared to other approaches, and integrated circuit  400 A- 400 C occupies less area than other approaches with similar performance. 
       FIG.  5 A  is a circuit diagram of an integrated circuit  500 A, in accordance with some embodiments.  FIG.  5 B  is a circuit diagram of an equivalent circuit  500 B of integrated circuit  500 A, in accordance with some embodiments.  FIG.  5 C  is a cross-sectional view of integrated circuit  500 A, in accordance with some embodiments. 
     Integrated circuit  500 A is an embodiment of integrated circuit  200 A of  FIG.  2 A , and similar detailed description is therefore omitted. In comparison with integrated circuit  200 A of  FIG.  2 A , PMOS transistor M 1  is positioned in well  320   a  ( FIG.  5 C ), PMOS transistor M 3  is positioned in a well  520   a  ( FIG.  5 C ), and PMOS transistors M 2 , M 4 , M 5  and M 6  are positioned in a well  520   b  ( FIG.  5 C ). In some embodiments, each of wells  320   a ,  520   a  and  520   b  are separated from each other and are thus different. 
     Integrated circuit  500 A comprises PMOS transistors M 1 , M 2 , M 3 , M 4 , M 5  and M 6  coupled to the voltage supply VDD and the pad terminal PAD. 
     Integrated circuit  500 A is a variation of integrated circuit  400 A of  FIG.  4 A , and similar detailed description is therefore omitted. 
     PMOS transistors M 2 , M 4 , M 5  and M 6  are positioned in a same well, (e.g., well  520   b ). Each of the body terminal of PMOS transistor M 2 , the body terminal of PMOS transistor M 4 , the body terminal of PMOS transistor M 5 , the body terminal of PMOS transistor M 6 , the drain terminal of PMOS transistor M 5  and the drain terminal of PMOS transistor M 6  are coupled together at node F 1 . In some embodiments, node F 1  is electrically floating. In some embodiments, node F 1  is electrically coupled to supply voltage VDD by PMOS transistors M 1 , M 3  and M 5 . In some embodiments, node F 1  is electrically coupled to pad terminal PAD by PMOS transistors M 2  M 4  and M 6 . 
     PMOS transistor M 3  is positioned in well  520   a . In  FIGS.  5 A- 5 C and  6 A- 6 C , a body terminal of PMOS transistor M 3 , the drain terminal of PMOS transistor M 3 , and the source terminal of PMOS transistor M 5  are coupled together at a node F 2 ′. In some embodiments, by coupling the body terminal of PMOS transistor M 3  to the drain terminal of PMOS transistor M 3 , PMOS transistor M 3  is self-biased and node F 2 ′ is not provided a bias voltage from a circuit external of integrated circuit  500 A. 
       FIG.  5 B  is a circuit diagram of an equivalent circuit  500 B of integrated circuit  500 A, in accordance with some embodiments. 
     Equivalent circuit  500 B is a variation of integrated circuit  500 A showing parasitic elements  530  of integrated circuit  500 A, and similar detailed description is therefore omitted. For example, equivalent circuit  500 B corresponds to integrated circuit  500 A of  FIG.  5 A  with parasitic elements  530  (e.g., diode D 1 , parasitic transistors Q 2 ″, Q 3  and Q 5 ), in accordance with some embodiments. 
     Equivalent circuit  500 B is a variation of equivalent circuit  300 B of  FIG.  3 B or  400 B  of  FIG.  4 B , and similar detailed description is therefore omitted. 
     Equivalent circuit  500 B includes integrated circuit  500 A and parasitic elements  530 . Parasitic elements  530  include diode D 1 , a parasitic transistor Q 2 ″, parasitic transistor Q 3  and a parasitic transistor Q 5 . 
     Each of the gate of PMOS transistor M 6 , the cathode of the diode D 1 , the body terminal of PMOS transistor M 1 , the source terminal of PMOS transistor M 1 , the gate of PMOS transistor M 2 , the gate of PMOS transistor M 4 , and the first voltage supply VDD are coupled together. 
     For  FIGS.  5 A- 5 C &amp;  6 A- 6 C , each of an emitter of parasitic transistor Q 5 , the base of parasitic transistor Q 3 , the collector of parasitic transistor Q 3 , the drain terminal of PMOS transistor M 3  and the source terminal of PMOS transistor M 5  are coupled together. 
     For  FIGS.  5 A- 5 C , each of a collector of parasitic transistor Q 5 , a base of parasitic transistor Q 5 , the body terminal of PMOS transistor M 5 , the drain terminal of PMOS transistor M 5 , the drain terminal of PMOS transistor M 6 , the body terminal of PMOS transistor M 6 , the body terminal of PMOS transistor M 4 , the body terminal of PMOS transistor M 2 , a collector of parasitic transistor Q 2 ″ and a base of parasitic transistor Q 2 ″ are coupled together at node F 1 . 
     Each of an emitter of parasitic transistor Q 2 ″, the gate of PMOS transistor M 5 , the source terminal of PMOS transistor M 2 , the gate of PMOS transistor M 1 , the gate of PMOS transistor M 3  and the pad terminal PAD are coupled together. 
     In some embodiments, during an ESD event with positive stress from the pad terminal PAD to the voltage supply VDD, the voltage of the pad terminal PAD is greater than the voltage of the voltage supply VDD, and therefore PMOS transistors M 2 , M 4  and M 6  are turned on, and PMOS transistors M 1 , M 3  and M 5  are turned off, and the voltage of the pad terminal PAD will be placed at node F 1 . In these embodiments, when the voltage of node F 1  is equal to the voltage of the pad terminal PAD, the whole voltage stress of the ESD event will be placed across PMOS transistors M 5 , M 3  and M 1 , thereby turning on parasitic transistors Q 5  and Q 3  and diode D 1  to conduct the discharged ESD current to the voltage supply VDD. Thus, since the ESD current path includes three parasitic elements (e.g., parasitic diode D 1 , parasitic transistor Q 3  and parasitic transistor Q 5 ) positioned in different wells ( 320   a ,  520   a  and  520   b ), the ESD immunity is boosted compared to other approaches. 
     In some embodiments, during an ESD event with negative stress from the voltage supply VDD to the pad terminal PAD, the voltage of the voltage supply VDD is greater than the voltage of the pad terminal PAD, and therefore PMOS transistors M 1  M 3 , and M 5  are turned on, and PMOS transistors M 2 , M 4  and M 6  are turned off, and the voltage of the voltage supply VDD will be placed at node F 1 . In these embodiments, when the voltage of node F 1  is equal to the voltage of the voltage supply VDD, the whole voltage stress of the ESD event will be placed across PMOS transistors M 2 , M 4  and M 6 , thereby turning on parasitic transistor Q 2 ″ to conduct the discharged ESD current to the pad terminal PAD. Thus, the ESD current path includes one parasitic element (e.g., parasitic transistor Q 2 ″). 
     In some embodiments, the 3-stacked PMOS structure utilizing PMOS transistors M 2 , M 4  and M 6  can be reduced to a single PMOS transistor (one of M 2 , M 4  or M 6 ) or a 2-stacked PMOS structure utilizing two PMOS transistors (two of M 2 , M 4  or M 6 ), if negative stress ESD events are not an issue. 
       FIG.  5 C  is a cross-sectional view of integrated circuit  500 A, in accordance with some embodiments. 
     Integrated circuit  500 C is an embodiment of integrated circuit  200 B of  FIG.  2 B , and similar detailed description is therefore omitted. 
     Integrated circuit  500 C illustrates an example of PMOS transistor M 1  positioned in well  320   a , PMOS transistor M 3  is positioned in well  520   a , and PMOS transistors M 2 , M 4 , M 5  and M 6  are positioned in well  520   b . In some embodiments, each of wells  320   a ,  520   a  and  520   b  are separated from each other and are thus different. 
     Integrated circuit  500 C comprises substrate  102 , wells  320   a ,  520   a  and  520   b , regions  304   a ,  504   b  and  504   c , gates  106   a ,  106   b ,  106   c ,  106   d ,  206   e  and  206   f , implant regions  308   a ,  508   b ,  508   c ,  508   d ,  508   e  and  508   f , and implant regions  310   a ,  510   b ,  510   c ,  510   d ,  510   e  and  510   f.    
     In comparison with integrated circuit  200 B of  FIG.  2 B , well  320   a  replaces well NW 4 , well  520   a  replaces well NW 3 , and well  520   b  replaces wells NW 5 , NW 6 , NW 2  and NW 1  of  FIG.  2 B , and similar detailed description is therefore omitted. 
     In other words, wells NW 5 , NW 6 , NW 2  and NW 1  of  FIG.  2 B  are merged into well  520   b , and similar detailed description is therefore omitted. Each of well  320   a ,  520   a  and  520   b  are separated from each other in the first direction X. In some embodiments, at least well  320   a ,  520   a  or  520   b  is different from another of at least well  320   a ,  520   a  or  520   b.    
     Gate  106   a  is above well  320   a , gate  106   b  is above well  520   a , and gates  106   b ,  106   c ,  106   d ,  206   e  and  206   f  are above well  520   b . For ease of illustration, gates  106   a ,  106   b  and  206   e  are not shown as being coupled to each other or other elements, and gates  106   c ,  106   d  and  206   f  are not shown as being coupled to each other or other elements. 
     In comparison with integrated circuit  200 B of  FIG.  2 B , region  304   a  replaces region  104   a , region  504   b  replaces region  104   b  of  FIG.  2 B , and region  504   c  replaces regions  104   c ,  104   d ,  204   e  and  204   f  of  FIG.  2 B , and similar detailed description is therefore omitted. Stated differently, regions  104   c ,  104   d ,  204   e  and  204   f  of  FIG.  2 B  are merged into region  504   b , and similar detailed description is therefore omitted. Region  304   a  is within well  320   a , region  504   b  is within well  520   a  and region  504   c  is within well  520   b.    
     Integrated circuit  500 C is a variation of integrated circuit  300 C of  FIG.  3 C , and similar detailed description is therefore omitted. In comparison with integrated circuit  300 C of  FIG.  3 C , implant regions  508   b ,  508   c  and  508   d  replace corresponding implant regions  308   b ,  308   c  and  308   d , and implant regions  510   b ,  510   c  and  510   d  replace corresponding implant regions  310   b ,  310   c  and  310   d , and similar detailed description is therefore omitted. Implant regions  308   a  and  310   a  are described in  FIG.  3 C , and similar detailed description is therefore omitted. 
     In comparison with integrated circuit  200 B of  FIG.  2 B , implant regions  508   b ,  508   c ,  508   d ,  508   e  and  508   f  replace corresponding implant regions  108   b ,  108   c ,  108   d ,  208   e  and  208   f , and implant regions  510   b ,  510   c ,  510   d ,  510   e  and  510   f  replace corresponding implant regions  110   b ,  110   c ,  110   d ,  210   e  and  210   f , and similar detailed description is therefore omitted. 
     Implant regions  308   a  and  310   a  are within well  320   a . Implant regions  508   b  and  510   b  are within well  520   a . Implant regions  508   c ,  508   d ,  508   e  and  508   f  and implant regions  510   c ,  510   d ,  510   e  and  510   f  are within well  520   b.    
     Implant region  310   a  is electrically coupled to implant region  508   b  and corresponds to the connection between the drain terminal of PMOS transistor M 1  and the source terminal of PMOS transistor M 3  of  FIG.  5 A . 
     Each of region  504   c , implant region  510   e  and implant region  508   f  are electrically coupled together at node F 1 , and corresponds to the connection between the body terminal of PMOS transistor M 5 , the drain terminal of PMOS transistor M 5 , the drain terminal of PMOS transistor M 6 , the body terminal of PMOS transistor M 6 , the body terminal of PMOS transistor M 4 , and the body terminal of PMOS transistor M 2  at node F 1 . 
     Each of region  504   b , implant region  510   b  and implant region  508   e  are electrically coupled together at node F 2 ′, and corresponds to the connection between the body terminal of PMOS transistor M 3 , the drain terminal of PMOS transistor M 3  and the source terminal of PMOS transistor M 5  of  FIG.  5 A . 
     Implant region  510   f  is electrically coupled to implant region  508   c  and corresponds to the connection between the source terminal of PMOS transistor M 6  and the drain terminal of PMOS transistor M 4  of  FIG.  5 A . 
     Implant region  510   c  is electrically coupled to implant region  508   d  and corresponds to the connection between the source terminal of PMOS transistor M 4  and the drain terminal of PMOS transistor M 2  of  FIG.  5 A . 
     Implant region  510   d  is electrically coupled to the pad terminal PAD and corresponds to the connection between the source terminal of PMOS transistor M 2  and the pad terminal PAD of  FIG.  5 A . 
     Integrated circuit  500 C includes parasitic diode D 1  of  FIG.  3 C , a parasitic transistor Q 2 ″, parasitic transistor Q 3  of  FIG.  3 C  and a parasitic transistor Q 5 . Parasitic diode D 1  is described in  FIG.  3 C , and parasitic transistor Q 3  is described in  FIG.  3 C , and similar detailed description is therefore omitted. 
     In comparison with integrated circuit  200 B of  FIG.  2   +B, parasitic transistor Q 2 ″ replaces parasitic pnp transistors  212   f ,  112   c  and  112   d  of  FIG.  2 B , and parasitic transistor Q 5  replaces parasitic pnp transistor  212   e  of  FIG.  2 B , and similar detailed description is therefore omitted. 
     Parasitic transistor Q 3  in  FIG.  5 C  is formed by well  520   a , implant region  508   b  and implant region  510   b . For example, the well  520   a  forms the base of parasitic transistor Q 3  in  FIG.  5 C , the implant region  508   b  forms the emitter of parasitic transistor Q 3  in  FIG.  5 C  and region  510   b  forms the collector of parasitic transistor Q 3  in  FIG.  5 C . 
     Parasitic transistor Q 2 ″ is formed by well  520   b , implant region  508   f  and implant region  510   d . For example, the well  520   b  forms a base of parasitic transistor Q 2 ″, the implant region  510   d  forms an emitter of parasitic transistor Q 2 ″ and region  508   f  forms a collector of parasitic transistor Q 2 ″. 
     Parasitic transistor Q 5  is formed by well  520   b , implant region  508   e  and implant region  510   e . For example, the well  520   b  forms a base of parasitic transistor Q 5 , the implant region  508   e  forms an emitter of parasitic transistor Q 5  and region  510   e  forms a collector of parasitic transistor Q 5 . 
     In some embodiments, by positioning PMOS transistor M 1  in well  320   a , by positioning PMOS transistor M 3  in a separate well (well  520   a ), and by positioning PMOS transistors M 5 , M 6 , M 4  and M 2  in another separate well (well  520   b ), a parasitic current path of integrated circuit  500 C includes parasitic elements (e.g., parasitic diode D 1 , parasitic transistor Q 3  and parasitic transistor Q 5 ) positioned in different wells ( 320   a ,  520   a  and  520   b ), and another parasitic current path of integrated circuit  500 C includes parasitic elements (e.g., parasitic transistor Q 2 ″) positioned in the another well ( 520   b ), thereby improving the ESD immunity of integrated circuit  500 A- 500 C compared to other approaches, and integrated circuit  500 A- 500 C occupies less area than other approaches with similar performance. 
       FIG.  6 A  is a circuit diagram of an integrated circuit  600 A, in accordance with some embodiments.  FIG.  6 B  is a circuit diagram of an equivalent circuit  600 B of integrated circuit  600 A, in accordance with some embodiments.  FIG.  6 C  is a cross-sectional view of integrated circuit  600 A, in accordance with some embodiments. 
     Integrated circuit  600 A is an embodiment of integrated circuit  200 A of  FIG.  2 A . 
     Integrated circuit  600 A comprises PMOS transistors M 1 , M 2 , M 3 , M 4 , M 5  and M 6  coupled to the voltage supply VDD and the pad terminal PAD. 
     Integrated circuit  600 A is a variation of integrated circuit  500 A of  FIG.  5 A  and integrated circuit  400 A of  FIG.  4 A . In comparison with integrated circuit  500 A of  FIG.  5 A  or integrated circuit  400 A of  FIG.  4 A , PMOS transistor M 1  of integrated circuit  600 A is positioned in well  320   a  ( FIG.  6 C ), PMOS transistor M 3  of integrated circuit  600 A is positioned in well  520   a  ( FIG.  6 C ), PMOS transistor M 2  of integrated circuit  600 A is positioned in well  420   b  ( FIG.  6 C ), and PMOS transistors M 4 , M 5  and M 6  of integrated circuit  600 A are positioned in a well  620   a  ( FIG.  6 C ), and similar detailed description is therefore omitted. 
     In some embodiments, each of wells  320   a ,  420   b ,  520   a  and  620   a  are different from each other. 
     In comparison with integrated circuit  500 A of  FIG.  5 A , PMOS transistor M 2  of  FIGS.  6 A- 6 C  is in well  420   b  and the body terminal of PMOS transistor M 2  is coupled to node F 2 . In some embodiments, node F 2  is charged from the pad terminal PAD by the parasitic body diode of PMOS transistor M 4 . 
     The configuration of PMOS transistor M 1  in  FIGS.  6 A- 6 C  is similar to the configurations of PMOS transistor M 1  in at least  FIGS.  3 A- 3 C , and similar detailed description is therefore omitted. The configuration of PMOS transistor M 3  in  FIGS.  6 A- 6 C  is similar to the configurations of PMOS transistor M 3  in at least  FIGS.  5 A- 5 C , and similar detailed description is therefore omitted. 
     PMOS transistors M 4 , M 5  and M 6  are positioned in a same well (e.g., well  620   a ). Each of the body terminal of PMOS transistor M 4 , the body terminal of PMOS transistor M 5 , the body terminal of PMOS transistor M 6 , the drain terminal of PMOS transistor M 5  and the drain terminal of PMOS transistor M 6  are coupled together at node F 1  in  FIGS.  6 A- 6 C . In some embodiments, node F 1  is electrically floating. In some embodiments, node F 1  is electrically coupled to supply voltage VDD by PMOS transistors M 1 , M 3  and M 5 . In some embodiments, node F 1  is electrically coupled to pad terminal PAD by PMOS transistors M 2 , M 4  and M 6 . 
       FIG.  6 B  is a circuit diagram of an equivalent circuit  600 B of integrated circuit  600 A, in accordance with some embodiments. 
     Equivalent circuit  600 B is a variation of integrated circuit  600 A showing parasitic elements  630  of integrated circuit  600 A, and similar detailed description is therefore omitted. For example, equivalent circuit  600 B corresponds to integrated circuit  600 A of  FIG.  6 A  with parasitic elements  630  (e.g., diode D 1 , parasitic transistors Q 2 ′″, Q 3 , Q 4  and Q 5 ), in accordance with some embodiments. 
     Equivalent circuit  600 B is a variation of equivalent circuit  500 B of  FIG.  5 B or  400 B  of  FIG.  4 B , and similar detailed description is therefore omitted. 
     Equivalent circuit  600 B includes integrated circuit  600 A and parasitic elements  630 . Parasitic elements  630  include diode D 1 , parasitic transistor Q 2 ′″, parasitic transistor Q 3 , parasitic transistor Q 4  and parasitic transistor Q 5 . 
     The configuration of diode D 1 , parasitic transistor Q 3 , and parasitic transistor Q 5  in  FIGS.  6 A- 6 C  is similar to the configurations of diode D 1 , parasitic transistor Q 3 , and parasitic transistor Q 5  in at least  FIGS.  5 A- 5 C , and similar detailed description is therefore omitted. 
     For  FIGS.  6 A- 6 C , each of the collector of parasitic transistor Q 5 , the base of parasitic transistor Q 5 , the body terminal of PMOS transistor M 5 , the drain terminal of PMOS transistor M 5 , the drain terminal of PMOS transistor M 6 , the body terminal of PMOS transistor M 6 , the body terminal of PMOS transistor M 4 , the collector of parasitic transistor Q 2 ′″ and the base of parasitic transistor Q 2 ′″ are coupled together at node F 1 . 
     For  FIGS.  6 A- 6 C , each of an emitter of parasitic transistor Q 4 , the gate of PMOS transistor M 5 , the source terminal of PMOS transistor M 2 , the gate of PMOS transistor M 1 , the gate of PMOS transistor M 3  and the pad terminal PAD are coupled together. 
     For  FIGS.  6 A- 6 C , the body terminal of PMOS transistor M 2  is coupled to base of parasitic transistor Q 4 . 
     For  FIGS.  6 A- 6 C , each of the drain terminal of PMOS transistor M 2 , the source terminal of PMOS transistor M 4 , the collector of parasitic transistor Q 4  and the emitter of parasitic transistor Q 2 ′″ are coupled together. 
     In some embodiments, during an ESD event with positive stress from the pad terminal PAD to the voltage supply VDD, the voltage of the pad terminal PAD is greater than the voltage of the voltage supply VDD, and therefore PMOS transistors M 2 , M 4  and M 6  are turned on, and PMOS transistors M 1 , M 3  and M 5  are turned off, and the voltage of the pad terminal PAD will be placed at node F 1 . In these embodiments, when the voltage of node F 1  is equal to the voltage of the pad terminal PAD, the whole voltage stress of the ESD event will be placed across PMOS transistors M 5 , M 3  and M 1 , thereby turning on parasitic transistors Q 5 ′ and Q 3  and diode D 1  to conduct the discharged ESD current to the voltage supply VDD. Thus, since the ESD current path includes three parasitic elements (e.g., parasitic diode D 1 , parasitic transistor Q 3  and parasitic transistor Q 5 ′) positioned in different wells ( 320   a ,  520   a  and  620   a ), the ESD immunity is boosted compared to other approaches. 
     In some embodiments, during an ESD event with negative stress from the voltage supply VDD to the pad terminal PAD, the voltage of the voltage supply VDD is greater than the voltage of the pad terminal PAD, and therefore PMOS transistors M 1  M 3 , and M 5  are turned on, and PMOS transistors M 2 , M 4  and M 6  are turned off, and the voltage of the voltage supply VDD will be placed at node F 1 . In these embodiments, when the voltage of node F 1  is equal to the voltage of the voltage supply VDD, the whole voltage stress of the ESD event will be placed across PMOS transistors M 2 , M 4  and M 6 , thereby turning on parasitic transistors Q 2 ′″ and Q 4  to conduct the discharged ESD current to the pad terminal PAD. Thus, since the parasitic current path includes two parasitic elements (e.g., parasitic transistor Q 4  and parasitic transistor Q 2 ′″) positioned in different wells ( 420   b  and  620   a ), the ESD immunity is boosted compared to other approaches. 
     In some embodiments, the 2-stacked PMOS structure in a same well (well  620   a ) utilizing PMOS transistors M 4  and M 6  can be reduced to a single PMOS transistor (one of M 4  or M 6 ), if negative stress ESD events are not an issue. 
       FIG.  6 C  is a cross-sectional view of integrated circuit  600 A, in accordance with some embodiments. 
     Integrated circuit  600 C is an embodiment of integrated circuit  200 B of  FIG.  2 B , and similar detailed description is therefore omitted. 
     Integrated circuit  600 C illustrates an example of PMOS transistor M 1  positioned in well  320   a , PMOS transistor M 3  is positioned in well  520   a , PMOS transistor M 2  is positioned in well  420   b , and PMOS transistors M 4 , M 5  and M 6  are positioned in a well  620   a , and similar detailed description is therefore omitted. In some embodiments, each of wells  320   a ,  420   b ,  520   a  and  620   a  are separated from each other in the first direction X and are thus different. 
     Integrated circuit  600 C comprises substrate  102 , wells  320   a ,  420   b ,  520   a  and  620   a , regions  304   a ,  404   d ,  504   b  and  604   c , gates  106   a ,  106   b ,  106   c ,  106   d ,  206   e  and  206   f , implant regions  308   a ,  408   d ,  508   b ,  608   c ,  608   e  and  608   f , and implant regions  310   a ,  410   d ,  510   b ,  610   c ,  610   e  and  610   f.    
     In comparison with integrated circuit  200 B of  FIG.  2 B , well  320   a  replaces well NW 4 , well  420   b  replaces well NW 1 , well  520   a  replaces well NW 3 , and well  620   a  replaces wells NW 5 , NW 6  and NW 2  of  FIG.  2 B , and similar detailed description is therefore omitted. 
     In other words, wells NW 5 , NW 6  and NW 2  of  FIG.  2 B  are merged into well  620   a , and similar detailed description is therefore omitted. Each of well  320   a ,  420   b ,  520   a  and  620   a  are separated from each other in the first direction X. In some embodiments, at least well  320   a ,  420   b ,  520   a  or  620   a  is different from another of at least well  320   a ,  420   b ,  520   a  or  620   a.    
     Gate  106   a  is above well  320   a , gate  106   b  is above well  520   a , gates  106   c ,  206   e  and  206   f  are above well  620   a , and gate  106   d  is above well  420   b . For ease of illustration, gates  106   a ,  106   b  and  206   e  are not shown as being coupled to each other or other elements, and gates  106   c ,  106   d  and  206   f  are not shown as being coupled to each other or other elements. 
     In comparison with integrated circuit  200 B of  FIG.  2 B , region  304   a  replaces region  104   a , region  504   b  replaces region  104   b  of  FIG.  2 B , region  604   c  replaces regions  104   c ,  204   e  and  204   f  of  FIG.  2 B , and region  404   d  replaces region  104   d  of  FIG.  2 B , and similar detailed description is therefore omitted. 
     Stated differently, regions  104   c ,  204   e  and  204   f  of  FIG.  2 B  are merged into region  604   c , and similar detailed description is therefore omitted. Region  304   a  is within well  320   a , region  504   b  is within well  520   a , region  404   d  is within well  420   b , and region  604   c  is within well  620   a.    
     Integrated circuit  600 C is a variation of integrated circuit  500 C of  FIG.  5 C  and integrated circuit  400 C of  FIG.  4 C , and similar detailed description is therefore omitted. In comparison with integrated circuit  500 C of  FIG.  5 C , implant regions  608   e ,  608   f  and  608   c  replace corresponding implant regions  508   e ,  508   f  and  508   c , and implant regions  610   e ,  610   f  and  610   c  replace corresponding implant regions  510   e ,  510   f  and  510   c , and similar detailed description is therefore omitted. 
     Implant regions  308   a  and  310   a  are described in  FIG.  3 C , and similar detailed description is therefore omitted. Implant regions  508   b  and  510   b  are described in  FIG.  5 C , and similar detailed description is therefore omitted. 
     Integrated circuit  600 C is a variation of integrated circuit  400 C of  FIG.  4 C , and similar detailed description is therefore omitted. For example, implant regions  408   d  and  410   d  described in  FIG.  4 C , and similar detailed description is therefore omitted. 
     In comparison with integrated circuit  200 B of  FIG.  2 B , implant regions  608   e ,  608   f  and  608   c  replace corresponding implant regions  108   e ,  108   f  and  108   c , and implant regions  610   e ,  610   f  and  610   c  replace corresponding implant regions  110   e ,  110   f  and  110   c , and similar detailed description is therefore omitted. 
     Implant regions  308   a  and  310   a  are within well  320   a . Implant regions  508   b  and  510   b  are within well  520   a . Implant region  408   d  and implant region  410   d  are within well  420   b . Implant regions  608   c ,  608   e  and  608   f  and implant regions  610   c ,  610   e  and  610   f  are within well  520   b.    
     Each of region  604   c , implant region  610   e  and implant region  608   f  are electrically coupled together at node F 1 , and corresponds to the connection between the body terminal of PMOS transistor M 5 , the drain terminal of PMOS transistor M 5 , the drain terminal of PMOS transistor M 6 , the body terminal of PMOS transistor M 6 , and the body terminal of PMOS transistor M 4  at node F 1 . 
     Each of region  504   b , implant region  510   b  and implant region  608   e  are electrically coupled together at node F 2 ′, and corresponds to the connection between the body terminal of PMOS transistor M 3 , the drain terminal of PMOS transistor M 3  and the source terminal of PMOS transistor M 5  of  FIG.  6 A . 
     Implant region  404   d  is electrically coupled to node F 2  and corresponds to the connection between the body terminal of PMOS transistor M 2  and node F 2  of  FIG.  6 A . 
     Implant region  610   f  is electrically coupled to implant region  608   c  and corresponds to the connection between the source terminal of PMOS transistor M 6  and the drain terminal of PMOS transistor M 4  of  FIG.  6 A . 
     Implant region  610   c  is electrically coupled to implant region  408   d  and corresponds to the connection between the source terminal of PMOS transistor M 4  and the drain terminal of PMOS transistor M 2  of  FIG.  6 A . 
     Implant region  410   d  is electrically coupled to the pad terminal PAD and corresponds to the connection between the source terminal of PMOS transistor M 2  and the pad terminal PAD of  FIG.  5 A . 
     Integrated circuit  600 C includes parasitic diode D 1  of  FIG.  3 C , a parasitic transistor Q 2 ′″, parasitic transistor Q 3  of  FIG.  3 C , parasitic transistor Q 4  of  FIG.  4 C , and a parasitic transistor Q 5 ′. 
     Parasitic diode D 1  is described in  FIG.  3 C , and parasitic transistor Q 3  is described in  FIGS.  3 C and  5 C , parasitic transistor Q 4  is described in  FIG.  4 C , and similar detailed description is therefore omitted. 
     In comparison with integrated circuit  200 B of  FIG.  2 B , parasitic transistor Q 2 ′″ replaces parasitic pnp transistors  212   f  and  112   c  of  FIG.  2 B , and similar detailed description is therefore omitted. 
     In comparison with integrated circuit  500 C of  FIG.  5 C , parasitic transistor Q 5 ′ replaces parasitic transistor Q 5  of  FIG.  5 C , and similar detailed description is therefore omitted. 
     Parasitic transistor Q 5 ′ is formed by well  620   a , implant region  608   e  and implant region  610   e . For example, the well  620   a  forms a base of parasitic transistor Q 5 ′, the implant region  608   e  forms an emitter of parasitic transistor Q 5 ′ and region  610   e  forms a collector of parasitic transistor Q 5 ′. 
     Parasitic transistor Q 2 ′″ is formed by well  620   a , implant region  608   f  and implant region  610   c . For example, the well  620   a  forms a base of parasitic transistor Q 2 ′″, the implant region  610   c  forms an emitter of parasitic transistor Q 2 ′″ and region  608   f  forms a collector of parasitic transistor Q 2 ′″. 
     In some embodiments, by positioning PMOS transistor M 1  in well  320   a , by positioning PMOS transistor M 3  in a separate well (well  520   a ), by positioning PMOS transistors M 5 , M 6  and M 4  in another separate well (well  620   a ), and by positioning PMOS transistor M 2  in yet another separate well (well  420   b ), a parasitic current path of integrated circuit  600 C includes parasitic elements (e.g., parasitic diode D 1 , parasitic transistor Q 3  and parasitic transistor Q 5 ′) positioned in different wells ( 320   a ,  520   a  and  620   a ), and another parasitic current path of integrated circuit  600 C includes parasitic elements (e.g., parasitic transistor Q 2 ′″ and parasitic transistor Q 4 ) positioned in different wells ( 620   a  and  420   b ), thereby improving the ESD immunity of integrated circuit  600 A- 600 C compared to other approaches, and integrated circuit  600 A- 600 C occupies less area than other approaches with similar performance. 
       FIG.  7 A  is a circuit diagram of an integrated circuit  700 A, in accordance with some embodiments. 
     Integrated circuit  700 A is an embodiment of integrated circuit  100 A of  FIG.  1 A . Integrated circuit  700 A is a variation of integrated circuit  300 A of  FIG.  3 A , and similar detailed description is therefore omitted. In comparison with integrated circuit  300 A of  FIG.  3 A , integrated circuit  700 A further comprises a control logic circuit  702   a.    
     Control logic circuit  702   a  is configured to generate a control logic signal CLS. In some embodiments, the control logic signal CLS is similar to the voltage of the pad terminal PAD, and similar detailed description is therefore omitted. 
     In comparison with integrated circuit  300 A of  FIG.  3 A , each of the gate terminal of PMOS transistor M 3  and the gate terminal of PMOS transistor M 1  are not coupled to the source terminal of PMOS transistor M 2  and the pad terminal PAD. 
     In  FIGS.  7 A- 7 B , the gate terminal of PMOS transistor M 3  and the gate terminal of PMOS transistor M 1  are coupled to the control logic circuit  702   a , and are configured to receive a control logic signal CLS from the control logic circuit  702   a.    
     In some embodiments, the control logic signal CLS is equal to a logic 0 corresponding to a reference supply voltage VSS. In some embodiments, the control logic signal CLS is equal to a logic 1 corresponding to the voltage of the pad terminal PAD (e.g., the PAD voltage). 
       FIG.  7 B  is a circuit diagram of an integrated circuit  700 B, in accordance with some embodiments. 
     Integrated circuit  700 B is an embodiment of integrated circuit  100 A of  FIG.  1 A . Integrated circuit  700 B is a variation of integrated circuit  400 A of  FIG.  4 A , and similar detailed description is therefore omitted. In comparison with integrated circuit  400 A of  FIG.  4 A , integrated circuit  700 B further comprises control logic circuit  702   a . The control logic circuit  702   a  of  FIG.  7 B  was described in  FIG.  7 A , and similar detailed description is therefore omitted. 
     In comparison with integrated circuit  400 A of  FIG.  4 A , each of the gate terminal of PMOS transistor M 3  and the gate terminal of PMOS transistor M 1  are not coupled to the source terminal of PMOS transistor M 2  and the pad terminal PAD. 
     In  FIG.  7 B , the gate terminal of PMOS transistor M 3  and the gate terminal of PMOS transistor M 1  are coupled to the control logic circuit  702   a , and are configured to receive a control logic signal CLS from the control logic circuit  702   a.    
       FIG.  7 C  is a circuit diagram of an integrated circuit  700 C, in accordance with some embodiments. 
     Integrated circuit  700 C is an embodiment of integrated circuit  200 A of  FIG.  2 A . Integrated circuit  700 C is a variation of integrated circuit  500 A of  FIG.  5 A , and similar detailed description is therefore omitted. In comparison with integrated circuit  500 A of  FIG.  5 A , integrated circuit  700 C further comprises a control logic circuit  702   b.    
     Control logic circuit  702   b  of  FIGS.  7 C- 7 D  is similar to control logic circuit  702   a  described in  FIGS.  7 A- 7 B , and similar detailed description is therefore omitted. 
     In comparison with integrated circuit  500 A of  FIG.  5 A , each of the gate terminal of PMOS transistor M 3 , the gate terminal of PMOS transistor M 1  and the gate terminal of PMOS transistor M 5  are not coupled to the source terminal of PMOS transistor M 2  and the pad terminal PAD. 
     In  FIGS.  7 C- 7 D , the gate terminal of PMOS transistor M 3 , the gate terminal of PMOS transistor M 1  and the gate terminal of PMOS transistor M 5  are coupled to the control logic circuit  702   b , and are configured to receive control logic signal CLS from the control logic circuit  702   b.    
       FIG.  7 D  is a circuit diagram of an integrated circuit  700 D, in accordance with some embodiments. 
     Integrated circuit  700 D is an embodiment of integrated circuit  200 A of  FIG.  2 A . Integrated circuit  700 D is a variation of integrated circuit  600 A of  FIG.  6 A , and similar detailed description is therefore omitted. In comparison with integrated circuit  600 A of  FIG.  6 A , integrated circuit  700 D further comprises control logic circuit  702   b.    
     Control logic circuit  702   b  of  FIG.  7 D  is similar to control logic circuit  702   a  described in  FIGS.  7 A- 7 B , and similar detailed description is therefore omitted. 
     In comparison with integrated circuit  600 A of  FIG.  6 A , each of the gate terminal of PMOS transistor M 3 , the gate terminal of PMOS transistor M 1  and the gate terminal of PMOS transistor M 5  are not coupled to the source terminal of PMOS transistor M 2  and the pad terminal PAD. 
     In  FIG.  7 D , the gate terminal of PMOS transistor M 3 , the gate terminal of PMOS transistor M 1  and the gate terminal of PMOS transistor M 5  are coupled to the control logic circuit  702   b , and are configured to receive control logic signal CLS from the control logic circuit  702   b.    
       FIG.  8    is a circuit diagram of a control logic circuit  800 , in accordance with some embodiments. 
     Control logic circuit  800  is an embodiment of at least control logic circuit  700 A of  FIG.  7 A , control logic circuit  700 B of  FIG.  7 B , control logic circuit  700 C of  FIG.  7 C  or control logic circuit  700 D of  FIG.  7 D . 
     Control logic circuit  800  includes a PMOS transistor M 7  and a NMOS transistor M 8  coupled to voltage supply VDD, pad terminal PAD, reference voltage supply VSS and a node NA. In some embodiments, control logic circuit  800  is an inverter. Other circuits are within the scope of the present disclosure. 
     A source terminal of PMOS transistor M 7  is coupled to at least the pad terminal PAD and is configured to receive a pad voltage (not labelled). Each of a gate terminal of PMOS transistor M 7  and a gate terminal of NMOS transistor M 8  is coupled together. The gate terminal of PMOS transistor M 7  and NMOS transistor M 8  are further coupled to at least the voltage supply VDD, and are configured to receive the supply voltage (not labelled). A drain terminal of PMOS transistor M 7  is coupled to a drain terminal of NMOS transistor M 8  at node NA. A source terminal of PMOS transistor M 8  is coupled to reference voltage supply VSS. 
     In some embodiments, when the voltage of the pad terminal PAD is greater than a voltage of the supply voltage VDD, then PMOS transistor M 7  is turned on and pulls node NA to the voltage of the pad terminal PAD thereby causing the voltage of node NA to be equal to the voltage of the pad terminal PAD, and the control logic signal CLS is equal to a logic 1. In some embodiments, when the voltage of the pad terminal PAD is less than a voltage of the supply voltage VDD, then NMOS transistor M 8  is turned on and pulls node NA to the voltage of the reference supply voltage VSS thereby causing the voltage of node NA to be equal to the voltage of the reference supply voltage VSS, and the control logic signal CLS is equal to a logic 0. 
     Method 
       FIG.  9    is a flowchart of a method of operating a circuit, such as the integrated circuit of  FIG.  1 A- 1 B,  2 A- 2 B,  3 A- 3 C,  4 A- 4 C,  5 A- 5 C,  6 A- 6 C,  7 A- 7 D or  8   , in accordance with some embodiments. It is understood that additional operations may be performed before, during, and/or after the method  900  depicted in  FIG.  9   , and that some other processes may only be briefly described herein. It is understood that method  900  utilizes features of one or more of integrated circuits  100 A- 100 B of  FIGS.  1 A- 1 B,  200 A- 200 B  of  FIGS.  2 A- 2 B,  300 A- 300 C  of  FIGS.  3 A- 3 C,  400 A- 400 C  of  FIGS.  4 A- 4 C,  500 A- 500 C  of  FIGS.  5 A- 5 C,  600 A- 600 C  of  FIGS.  6 A- 6 C,  700 A- 700 C  of  FIGS.  7 A- 7 D or  800    of  FIG.  8   . 
     In operation  902  of method  900 , a pad voltage is received on a pad voltage terminal PAD. In some embodiments, the pad voltage is greater than a supply voltage of a voltage supply VDD. In some embodiments, if the pad voltage is greater than the supply voltage of the voltage supply VDD, then method  900  proceeds to operation  904 . 
     In some embodiments, the pad voltage is less than the supply voltage of a voltage supply VDD. In some embodiments, if the pad voltage is less than the supply voltage of the voltage supply VDD, then method  900  proceeds to operation  912 . 
     In operation  904  of method  900 , at least a first set of transistors M 2  coupled to the pad voltage terminal are turned on in response to the pad voltage being greater than the supply voltage of the voltage supply VDD, and at least a second set of transistors coupled to the first voltage supply are turned off in response to the pad voltage being greater than the supply voltage of the voltage supply VDD. In some embodiments, the first set of transistors includes at least PMOS transistor M 1 , M 3  or M 5 . In some embodiments, the second set of transistors includes at least PMOS transistor M 2 , M 4  or M 6 . In some embodiments, a first transistor of the first set of transistors is in a first well, and a second transistor of the second set of transistors is in a second well different from the first well. In some embodiments, the first well includes at least a well described in  FIGS.  1 A- 8   , the second well includes at least another well described in  FIGS.  1 A- 8   . 
     In some embodiments, operation  904  comprises one or more of operations  906 ,  908  or  910 . 
     In operation  906  of method  900 , a first node F 1  is electrically coupled with the pad voltage terminal by the first set of transistors. 
     In operation  908  of method  900 , the first node F 1  is electrically decoupled from the first voltage supply by the second set of transistors. 
     In operation  910  of method  900 , the pad voltage is placed across the second set of transistors. 
     In operation  912  of method  900 , at least the first set of transistors M 2  coupled to the pad voltage terminal are turned off in response to the pad voltage being less than the supply voltage of the voltage supply VDD, and at least the second set of transistors coupled to the first voltage supply are turned on in response to the pad voltage being less than the supply voltage of the voltage supply VDD. 
     In some embodiments, operation  912  comprises one or more of operations  914 ,  916  or  918 . 
     In operation  914  of method  900 , the first node F 1  is electrically decoupled from the pad voltage terminal by the first set of transistors. 
     In operation  916  of method  900 , the first node F 1  is electrically coupled with the first voltage supply by the second set of transistors. 
     In operation  918  of method  900 , the pad voltage is placed across the first set of transistors. 
     In some embodiments, one or more of the operations of method  900  is not performed. While method  900  was described above with reference to  FIGS.  3 A- 3 C , it is understood that method  900  utilizes the features of one or more of  FIGS.  1 A- 2 B &amp;  4 A- 8   . In these embodiments, other operations of method  900  would be performed consistent with the description and operation of integrated circuits  100 A- 200 B &amp;  400 A- 800  of  FIGS.  1 A- 2 B &amp;  4 A- 8   . 
     Furthermore, various PMOS transistors shown in  FIGS.  1 A- 8    are of a particular dopant type (e.g., N-type or P-type) and are for illustration purposes. Embodiments of the disclosure are not limited to a particular transistor type, and one or more of the PMOS or NMOS transistors shown in  FIGS.  1 A- 8    can be substituted with a corresponding transistor of a different transistor/dopant type. Similarly, the low or high logical value of various signals used in the above description is also used for illustration. Embodiments of the disclosure are not limited to a particular logical value when a signal is activated and/or deactivated. Selecting different logical values is within the scope of various embodiments. Selecting different numbers of PMOS transistors in  1 A- 8  is within the scope of various embodiments. 
     One aspect of this description relates to a voltage tracking circuit. The voltage tracking circuit includes a first transistor in a first well, the first transistor including a first gate terminal, a first drain terminal and a first source terminal, the first source terminal being coupled to a first voltage supply, the first gate terminal being coupled to a pad voltage terminal and configured to receive a pad voltage. In some embodiments, the voltage tracking circuit further includes a second transistor including a second gate terminal, a second drain terminal and a second source terminal, the second source terminal being coupled to the first drain terminal, the second gate terminal being coupled to the first gate terminal and the pad voltage terminal. In some embodiments, the voltage tracking circuit further includes a third transistor including a third gate terminal, a third drain terminal and a third source terminal, the third gate terminal being coupled to the first voltage supply. In some embodiments, the voltage tracking circuit further includes a fourth transistor in a second well different from the first well, and being separated from the first well in a first direction, the fourth transistor including a fourth gate terminal, a fourth drain terminal and a fourth source terminal, the fourth drain terminal being coupled to the third source terminal, the fourth gate terminal being coupled to the third gate terminal and the first voltage supply, and the fourth source terminal being coupled to the pad voltage terminal. In some embodiments, at least the second transistor or the third transistor is in a third well different from the first well and the second well, and being separated from the first well in the first direction. 
     Another aspect of this description relates to a voltage tracking circuit. The voltage tracking circuit includes a control logic circuit, and a first transistor in a first well, the first transistor including a first gate terminal, a first drain terminal and a first source terminal, the first source terminal being coupled to a first voltage supply, the first gate terminal being coupled to the control logic circuit and configured to receive a control logic signal. In some embodiments, the voltage tracking circuit further includes a second transistor including a second gate terminal, a second drain terminal and a second source terminal, the second source terminal being coupled to the first drain terminal, the second gate terminal being coupled to the first gate terminal and the control logic circuit, and configured to receive the control logic signal. In some embodiments, the voltage tracking circuit further includes a third transistor including a third gate terminal, a third drain terminal and a third source terminal, the third gate terminal being coupled to the first voltage supply. In some embodiments, the voltage tracking circuit further includes a fourth transistor in a second well different from the first well, and being separated from the first well in a first direction, the fourth transistor including a fourth gate terminal, a fourth drain terminal and a fourth source terminal, the fourth drain terminal being coupled to the third source terminal, the fourth gate terminal being coupled to the third gate terminal and the first voltage supply, and the fourth source terminal being coupled to a pad voltage terminal. In some embodiments, at least the second transistor or the third transistor is in a third well different from the first well and the second well, and being separated from the first well in the first direction. 
     Yet another aspect of this description relates to a method of operating a pad voltage tracking circuit. The method includes receiving a pad voltage on a pad voltage terminal, the pad voltage being less than a supply voltage of a first voltage supply. In some embodiments, the method further includes turning off at least a first set of transistors coupled to the pad voltage terminal, and turning on a second set of transistors coupled to the first voltage supply, a first transistor of the first set of transistors being in a first well, and a second transistor of the second set of transistors being in a second well different from the first well. In some embodiments, the method further includes electrically decoupling a first node from the pad voltage terminal by the first set of transistors. In some embodiments, the method further includes electrically coupling the first node with the first voltage supply by the second set of transistors. In some embodiments, the method further includes placing the pad voltage across the first set of transistors. 
     A number of embodiments have been described. It will nevertheless be understood that various modifications may be made without departing from the spirit and scope of the disclosure. For example, various transistors being shown as a particular dopant type (e.g., N-type or P-type Metal Oxide Semiconductor (NMOS or PMOS)) are for illustration purposes. Embodiments of the disclosure are not limited to a particular type. Selecting different dopant types for a particular transistor is within the scope of various embodiments. The low or high logical value of various signals used in the above description is also for illustration. Various embodiments are not limited to a particular logical value when a signal is activated and/or deactivated. Selecting different logical values is within the scope of various embodiments. In various embodiments, a transistor functions as a switch. A switching circuit used in place of a transistor is within the scope of various embodiments. In various embodiments, a source of a transistor can be configured as a drain, and a drain can be configured as a source. As such, the term source and drain are used interchangeably. Various signals are generated by corresponding circuits, but, for simplicity, the circuits are not shown. 
     Various figures show capacitive circuits using discrete capacitors for illustration. Equivalent circuitry may be used. For example, a capacitive device, circuitry or network (e.g., a combination of capacitors, capacitive elements, devices, circuitry, or the like) can be used in place of the discrete capacitor. The above illustrations include exemplary steps, but the steps are not necessarily performed in the order shown. Steps may be added, replaced, changed order, and/or eliminated as appropriate, in accordance with the spirit and scope of disclosed embodiments. 
     The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.