Patent Publication Number: US-2023154520-A1

Title: Semiconductor device performing refresh operation

Description:
BACKGROUND 
     A DRAM is a volatile semiconductor memory device in which data in a memory cell is retained by periodically performing a refresh operation. Reduction of current consumption caused by the refresh operation is desired in order to reduce current consumption in the DRAM. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG.  1    is a block diagram showing a configuration of a semiconductor device according to an embodiment of the present disclosure; 
         FIG.  2    is a block diagram showing a configuration of a refresh controller; 
         FIG.  3    is a table for explaining a relationship among commands and addresses and memory banks subjected to a refresh operation; 
         FIG.  4    is a circuit diagram showing a configuration of a refresh bank counter, 
         FIGS.  5 A and  5 B  are timing charts for explaining an operation of the refresh bank counter; 
         FIG.  6    is a circuit diagram showing a configuration of a refresh bank selector; and 
         FIG.  7    is a timing chart for explaining an operation of the semiconductor device according to an embodiment of the present disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     Various embodiments of the present disclosure will be explained below in detail with reference to the accompanying drawings. The following detailed description refers to the accompanying drawings that show, by way of illustration, specific aspects, and various embodiments of the present disclosure. The detailed description provides sufficient detail to enable those skilled in the art to practice these embodiments of the present disclosure. Other embodiments may be utilized, and structural, logical, and electrical changes may be made without departing from the scope of the present disclosure. The various embodiments disclosed herein are not necessary mutually exclusive, as some disclosed embodiments can be combined with one or more other disclosed embodiments to form new embodiments. 
       FIG.  1    is a block diagram showing a configuration of a semiconductor device  10  according to the present disclosure. The semiconductor device  10  shown in  FIG.  1    is, for example, a DRAM and includes a memory cell array  11 , an access control circuit  12  that makes access to the memory cell array  11 , and an I/O circuit  13  that performs input and output of data to/from the memory cell army  11 . The memory cell array  11  includes 16 memory banks MB #0 to MB #15. The access control circuit  12  makes access to the memory cell array  11  based on a command address signal CA input from an external controller via a command address terminal  14 . In a read operation, data DQ read out from any of the memory banks MB #0 to MB #15 is output to a data I/O terminal  15  via the L/C) circuit  13 . In a write operation, data DQ input from the external controller to the data I/O terminal  15  is written to any of the memory banks MB #0 to MB #15 via the I/O circuit  13 . The access control circuit  12  includes a command decoder  16  and a refresh controller  17 . 
       FIG.  2    is a block diagram showing a configuration of the refresh controller  17 . As shown in  FIG.  2   , the refresh controller  17  includes a refresh bank counter  18  and eight refresh bank selectors  20  to  27 . Refresh signals REFAB and REFPB&lt;0&gt; to REFPB&lt;7&gt; output from the command decoder  16  are supplied to the refresh bank counter  18 . When a command CMD included in the command address signal CA indicates an all-bank-refresh command, the command decoder  16  activates the all-bank-refresh signal REFAB. When the command CMD included in the command address signal CA indicates a per-bank-refresh command, the command decoder  16  activates any of the per-bank-refresh signals REFPB&lt;0&gt; to REFPB&lt;7&gt; based on a bank group address BG and a bank address BA. As shown in  FIG.  3   , the bank group address BG has a 2-bit configuration including BG0 and BG1, and the bank address BA has a 2-bit configuration including BA0 and BA1. In a normal read-write operation, any one of the 16 memory banks MB #0 to MB #15 is selected based on the bank group address BG and the bank address BA. In a per-bank-refresh operation, the bank group address BG1 is disabled, and two memory banks to be refreshed are selected based on three bits including the bank group address BG0 and the bank addresses BA0 and BA1. For example, when values of the addresses BG0, BA1, and BA0 are &lt;000&gt; as shown in an access number #1, the per-bank-refresh signal REFPB&lt;0&gt; is activated and, in response to this activation, a refresh operation is performed on the memory banks MB #0 and MB #8. When the values of the addresses BG0, BA1, and BA0 are &lt;001&gt; as shown in an access number #2, the per-bank-refresh signal REFPB&lt;1&gt; is activated and, in response to this activation, a refresh operation is performed on the memory banks MB #1 and MB #9. Meanwhile, in an all-bank-refresh operation as shown in an access number #17, all the bank group address BG and the bank address BA are disabled and the all-bank-refresh signal REFAB is activated. When the all-bank-refresh signal REFAB is activated, a refresh operation is performed on all the memory banks MB #0 to MB #15 in principle. In some cases, as details thereof are described later, a refresh operation on one or more memory banks is skipped also in the all-bank-refresh operation as shown in an access number #21. In the example shown in  FIG.  3   , a refresh operation on the memory banks MB #0 to MB ##2 and MB #8 to MB #10 is skipped in an all-bank-refresh operation that is performed immediately after a refresh operation on the memory banks MB #0 to MB #2 and MB #8 to MB #10 as shown in access numbers #18 to #20. 
       FIG.  4    is a circuit diagram showing a configuration of the refresh bank counter  18 . As shown in  FIG.  4   , the refresh bank counter  18  includes a counter  30  that counts the per-bank-refresh signals REFPB&lt;0&gt; to REFPB&lt;7&gt; and an OR gate circuit  31  that receives a selection signal SELa output from the counter  30  and the all-bank-refresh signal REFAB and generates a selection signal SELb. The counter  30  counts the per-bank-refresh signals REFPB&lt;0&gt; to REFPB&lt;7&gt; and, when detecting all the per-bank-refresh signals REFPB&lt;0≥ to REFPB&lt;7&gt;, activates the selection signal SELa to a high level. Therefore, when all the per-bank-refresh signals REFPB&lt;0&gt; to REFPB&lt;7&gt; are activated or when the all-bank-refresh signal REFAB is activated, the selection signal SELb is activated to a high level. The selection signal SELb is fed back to the counter  30  to reset a value of the counter  30 . The selection signal SELb is also supplied to a refresh counter  40 . The refresh counter  40  updates a refresh address REFADD in response to the selection signal SELb. The selection signal SELb is supplied to one input node of a NOR gate circuit  32  and one input node of an AND gate circuit  33 . An inverted signal of a state signal ST is supplied to the other input node of the NOR gate circuit  32 . The state signal ST is supplied to the other input node of the AND gate circuit  33 . The state signal ST is activated to a high level in a refresh operation. 
     Therefore, when the per-bank-refresh signals REFPB&lt;0&gt; to REFPB&lt;7&gt; are sequentially activated as shown in the access numbers #1 to #8 in  FIG.  3   , the selection signals SELa and SELb are activated in response to the eighth per-bank-refresh signal REFPB&lt;7&gt;. Consequently, as shown in  FIG.  5 A , while the first to seventh per-bank-refresh signals REFPB&lt;0&gt; to REFPB&lt;6&gt; are input, a set signal SET output flout the NOR gate circuit  32  is high and a reset signal RST output from the AND gate circuit  33  is low. Thereafter, when the per-bank-refresh signals REFPB&lt;0&gt; to REFPB&lt;7&gt; are sequentially activated again as shown in access numbers #9 to #16 in  FIG.  3   , the selection signals SELa and SELb are activated in response to the eighth per-bank-refresh signal REFPB&lt;7&gt;, as shown in  FIG.  5 A . In this manner, every time the eighth per-bank-refresh signal REFPB&lt;7&gt; is activated, the set signal SET becomes low and the reset signal RST becomes high. Although the per-bank-refresh signals REFPB&lt;0&gt; to REFPB&lt;T&gt; are activated in this order in the example shown in  FIGS.  3  and  5 A , the order of activation of the per-bank-refresh signals REFPB&lt;0&gt; to REFPB&lt;7&gt; is determined by the bank group address BG and the bank address BA input from an external controller. Meanwhile, as shown in  FIG.  5 B , when the all-bank-refresh signal REFAB is activated, the set signal SET immediately becomes low and the reset signal RST immediately becomes high. As described above, when the first to seventh per-bank-refresh signals are activated, the set signal SET is activated. When the all-bank-refresh signal REFAB is activated or when the eighth per-bank-refresh signal is activated, the reset signal RST is activated. 
     The set signal SET and the reset signal RST are supplied to the refresh bank selectors  20  to  27  in common as shown in  FIG.  2   . In addition, the all-bank-refresh signal REFAB is supplied to the refresh bank selectors  20  to  27  in common, and the per-bank-refresh signals REFPB&lt;0&gt; to REFPB&lt;7&gt; corresponding to the refresh bank selectors  20  to  27  are supplied to the refresh bank selectors  20  to  27 , respectively. 
       FIG.  6    is a circuit diagram showing a configuration of the refresh bank selector  20 . As shown in  FIG.  6   , the refresh bank selector  20  includes an OR gate circuit  47  that receives the per-bank-refresh signal REFPB&lt;0&gt; and the all-bank-refresh signal REFAB and a latch circuit  41  that latches an output signal of the OR gate circuit  47 . An enable signal EN output from the latch circuit  41  is supplied to one input nodes of NAND gate circuits  42  to  44 . In an initial state, an SR latch circuit  45  is reset, and a block signal BLK output from the SR latch circuit  45  is low. Therefore, when the enable signal EN is activated to a high level, an output signal of the NAND gate circuit  43  becomes low, and a refresh bank signal RFACTBK&lt;0&gt; output from a NAND gate circuit  46  is activated to a high level. Accordingly, the memory banks MB #0 and MB #8 perform a refresh operation on a refresh address REFADD indicated by the refresh counter  40  shown in  FIG.  4   . 
     The set signal SET is supplied to the other input node of the NAND gate circuit  42 . Therefore, when the per-bank-refresh signal REFPB&lt;0&gt; or the all-bank-refresh signal REFAB is activated while the set signal SET is high, an output signal of the NAND gate circuit  42  becomes low, and the SR latch circuit  45  is set. Accordingly, the block signal BLK output from the SR latch circuit  45  becomes high, and a subsequent enable signal EN is disabled. However, when a special refresh command indicating refresh management is issued from an external controller, a refresh management signal RFM is activated, and an output signal of the NAND gate circuit  44  becomes low in response to the enable signal EN. Therefore, even if the block signal BLK is at a high level, the refresh bank signal RFACTBK&lt;0&gt; output from the NAND gate circuit  46  is activated to a high level, so that a refresh operation on the memory banks MB #0 and MB #8 is performed. In the refresh operation using the refresh management signal RFM, the refresh address REFADD output from the refresh counter  40  is not used. Instead, a special refresh address prepared for refresh management is used. 
     When the reset signal RST is activated, the SR latch circuit  45  is reset, and the block signal BLK is cleared. The other refresh bank selectors  21  to  27  also have the same circuit configuration as that in  FIG.  6    except that the per-bank-refresh signals REFPB&lt;1&gt; to REFPB&lt;7&gt; are used, respectively, in place of the per-bank-refresh signal REFPB&lt;0&gt;. 
       FIG.  7    is a timing chart for explaining an operation of the semiconductor device  10  according to the present disclosure. In the example shown in  FIG.  7   , the all-bank-refresh signal REFAB is activated at a time t1. In response to this activation, the refresh bank signals RFACTBK&lt;0&gt; to RFACTBK&lt;7&gt; are activated to a high level, and a refresh operation is performed on a refresh address n in the memory banks MB #0 to MB #15. Further, in response to activation of the all-bank-refresh signal REFAB, a value of the refresh address REFADD is updated from n to n+1. Although block signals BLK&lt;0&gt; to BLK&lt;7&gt; in the refresh bank selectors  20  to  27  become high for a short time in response to activation of the all-bank-refresh signal REFAB, they are immediately changed to a low level by activation of the reset signal RST. 
     Next, when the per-bank-refresh signal REFPB&lt;0&gt; is activated at a time t2, the refresh bank signal RFACTBK&lt;0&gt; is activated to a high level in response to this activation, so that a refresh operation is performed on the refresh address n+1 in the memory banks MB #0 and MB #8. Further, the block signal BLK&lt;0&gt; in the refresh bank selector  20  becomes high. Next, when the per-bank-refresh signal REFPB&lt;1&gt; is activated at a time t3, the refresh bank signal RFACTBK&lt;1&gt; is activated to a high level in response to this activation, so that a refresh operation is performed on the refresh address n+1 in the memory banks MB #1 and MB #9. In addition, the block signal BLK&lt;1&gt; in the refresh bank selector  21  becomes high. 
     Next, when the all-bank-refresh signal REFAB is activated at a time t4, the refresh bank signals RFACTBK&lt;2&gt; to RFACTBK&lt;7&gt; are activated to a high level in response to this activation, so that a refresh operation is performed on the refresh address n+1 in the memory banks MB #2 to MB #7 and MB #10 to MB #15. Meanwhile, the per-bank-refresh signals REFPB&lt;0&gt; and REFPB&lt;1&gt; are blocked because the block signals BLK&lt;0&gt; and BLK&lt;1&gt; have become high in the refresh bank selectors  20  and  21  for which a per-bank-refresh operation has been performed at the times t2 and t3. Accordingly, a duplicate refresh operation on the refresh address n+1 in the memory banks MB #0, MB #1, MB #8, and MB #9 is avoided, resulting in reduction of current consumption. Thereafter, the value of the refresh address REFADD is updated from n+1 to n+2, and the block signals BLK&lt;0&gt; to BLK&lt;7&gt; in all the refresh bank selectors  20  to  27  are cleared by activation of the reset signal RST. 
     At times t5 to t12, the per-bank-refresh signals REFPB&lt;7&gt;, REFPB&lt;5&gt;, REFPB&lt;3&gt;, REFPB&lt;1&gt;, REFPB&lt;6&gt;, REFPB&lt;4&gt;, REFPB&lt;2&gt;, and REFPB&lt;0&gt; are activated in this order. In response to such activation, the refresh bank signals RFACTBK&lt;7&gt;, RFACTBK&lt;5&gt;, RFACTBK&lt;3&gt;, RFACTBK&lt;1&gt;, RFACTBK&lt;6&gt;, RFACTBK&lt;4&gt;, RFACTBK&lt;2≥, and RFACTBK&lt;0&gt; are activated to a high level in this order, so that a refresh operation is performed on the refresh address n+2 in the memory banks MB #0 to MB #15. When a per-bank-refresh operation has been performed on the refresh address n+2 in all the memory banks MB #0 to MB #15 in this manner, the value of the refresh address REFADD is updated from n+2 to n+3, and the block signals BLK&lt;0&gt; to BLK&lt;7=&gt; in all the refresh bank selectors  20  to  27  are cleared by activation of the reset signal RST. 
     Subsequently, when the per-bank-refresh signal REFPB&lt;7&gt; is activated at a time t13, the refresh bank signal RFACTBK&lt;7&gt; is activated to a high level in response to this activation, so that a refresh operation is performed on the refresh address n+3 in the memory banks MB #7 and MB #15. Further, the block signal BLK&lt;7&gt; in the refresh bank selector  27  becomes high. Next, when the refresh management signal RFM is activated at a time t14, the refresh bank signals RFACTBK&lt;0&gt; to RFACTBK&lt;7&gt; are activated to a high level in response to this activation, so that a refresh operation is performed on any refresh address REFADD in the memory banks MB #0 to MB #15. At this time, although the block signal BLK&lt;7&gt; in the refresh bank selector  27  is at a high level, the refresh bank signal RFACTBK&lt;T&gt; is activated without being blocked. It is therefore possible to perform a refresh operation on a special refresh address prepared for refresh management. Further, even after completion of the refresh operation in response to the refresh management signal RFM, the refresh counter  40  is not updated, and its value is maintained to be n+3. Therefore, when the per-bank-refresh signal REFPB&lt;1&gt; is activated at a time t15, the refresh bank signal RFACTBK&lt;1&gt; is activated to a high level in response to this activation, so that a refresh operation is performed on the refresh address n+3 in the memory banks MB #1 and MB #9. In addition, the block signal BLK&lt;1&gt; in the refresh bank selector  21  becomes high. 
     Next, when a self refresh signal SR is activated at a time t16, the refresh bank signals RFACTBK&lt;0&gt; and RFACTBK&lt;2&gt; to RFACTBK&lt;6&gt; are activated to a high level in response to this activation, so that a self refresh operation is performed on the refresh address n+3 in the memory banks MB #0, MB #2 to MB #6, MB #8, and MB #10 to MB #14. Meanwhile, the per-bank-refresh signals REFPB&lt;1&gt; and REFPB&lt;7&gt; are blocked because the block signals BLK&lt;1&gt; and BLK&lt;7&gt; have become high in the refresh bank selectors  21  and  27  for which a per-bank-refresh operation has been performed at the times t13 and t15. Accordingly, a duplicate refresh operation on the refresh address n+3 in the memory banks MB #1, MB #7, MB #9, and MB #15 is avoided, resulting in reduction of current consumption. Thereafter, the value of the refresh address REFADD is updated from n+3 to n+4, and the block signals BLK&lt;0&gt; to BLK&lt;7&gt; in all the refresh bank selectors  20  to  27  are cleared by activation of the reset signal RST. Thereafter, a normal self refresh operation is performed. 
     As described above, in each of an all-bank-refresh operation and a self refresh operation, the semiconductor device  10  according to the present disclosure does not perform a duplicate refresh operation on a memory bank on which a per-bank-refresh operation has been completed for the same refresh address immediately before that refresh operation. Accordingly, current consumption required for a refresh operation is reduced. 
     Although various embodiments have been disclosed in the context of certain preferred embodiments and examples, it will be understood by those skilled in the art that the scope of the present disclosure extends beyond the specifically disclosed embodiments to other alternative embodiments and/or uses of the embodiments and obvious modifications and equivalents thereof. In addition, other modifications which are within the scope of this disclosure will be readily apparent to those of skill in the art based on this disclosure. It is also contemplated that various combination or sub-combination of the specific features and aspects of the embodiments may be made and still fall within the scope of the disclosure. It should be understood that various features and aspects of the disclosed embodiments can be combined with or substituted for one another in order to form varying modes of the disclosed embodiments. Thus, it is intended that the scope of at least some of the present disclosure should not be limited by the particular disclosed embodiments described above.