Patent Publication Number: US-8537150-B2

Title: Method and control board for eliminating power-off residual images in display and display using the same

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application claims the priority benefit of Taiwan application serial no. 97128692, filed on Jul. 29, 2008. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification. 
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a flat-panel display technology, more particularly, the present invention relates to a liquid crystal display without power-off residual images. 
     2. Description of the Related Art 
     In recent years, with great advance in the fabricating techniques of opto-electronics and semiconductor devices, flat panel displays (FPDs) have been vigorously developed. Among the FPDs, a liquid crystal display (hereinafter “LCD”) has become the mainstream display product due to its advantages of outstanding space utilization efficiency, low power consumption, free radiation, and low electrical field interference. 
     In conventional, the power-off residual images in the liquid crystal display (LCD) are always caused by electric charges still remaining in pixels of the LCD panel when the LCD is in power-off. Accordingly, a low voltage detection IC is embedded into the conventional control board for outputting a low voltage signal to an XAO pin of the gate driver when the LCD is in power-off, so that the gate driver would turn on all scan lines in the LCD panel to neutralize electric charges remaining in pixels of the LCD panel so as to achieve the purpose of eliminating power-off residual images in the LCD. 
     However, in actually, since the velocity of discharge of a gate driver turn-on voltage (i.e. V GH ) supplied to the gate driver and generated from a power supply unit of the control board is too fast when the LCD is in power-off, so that the gate driver is incapable of successfully turning on all scan lines of the LCD panel to neutralize electric charges remaining in pixels of the LCD panel. Therefore, the power-off residual images eventually produce when the LCD is in power-off. 
     SUMMARY OF THE INVENTION 
     The present invention is directed to a method and a control board for eliminating power-off residual images produced when the LCD is in power-off. 
     The present invention provides a method for eliminating power-off residual images in a display. The method includes the following steps of providing a first voltage to compensate a second voltage which is used for sequentially turning on all of scan lines within a display panel when the display is in power-off, and then forming a third voltage to turn on the scan lines according to the compensated second voltage. 
     According to an embodiment of the present invention, the method is adapted for eliminating residual images produced when a liquid crystal display (LCD) is in power-off. 
     The present invention also provides a control board including a compensation unit and a low voltage detection unit. The compensation unit is used for compensating a second voltage which is used for sequentially turning on all of scan lines within a display panel according to a first voltage when a display is in power-off. The low voltage detection unit is used for detecting whether a logic operating voltage is lower than a predetermined value or not when the display is in power-off. When the logic operating voltage is lower than the predetermined value, the low voltage detection unit outputs a low voltage signal to a gate driver, such that the gate driver turns on the scan lines according to a third voltage, wherein the third voltage is formed by the compensated second voltage. 
     According to an embodiment of the present invention, the control board further includes a power supply unit for at lest providing the first, the second and the logic operating voltages. 
     According to an embodiment of the present invention, the compensation unit includes a diode having an anode receiving the first voltage and a cathode receiving the second voltage. 
     According to an embodiment of the present invention, the cathode of the diode receives the second voltage through a current limiting resistor. 
     According to an embodiment of the present invention, the gate driver is directly disposed on the display panel. 
     According to an embodiment of the present invention, the display at least includes an LCD. 
     The present invention also provides a display including a display panel and a control board provided by the present invention. 
     According to an embodiment of the present invention, a velocity of discharge of the first voltage is slower than a velocity of discharge of the second voltage. 
     According to an embodiment of the present invention, the second voltage is incapable of turning on the scan lines within the display panel when the display is in power-off. 
     According to an embodiment of the present invention, the second voltage is a gate driver turn-on voltage (V GH ). 
     According to an embodiment of the present invention, the first voltage at least includes a common voltage (V COM ). 
     The method and the control board provided by the present invention firstly employ the common voltage (V COM ) to compensate the gate driver turn-on voltage (V GH ) when the LCD is in power-off, and then turning on all scan lines within the display panel to rapidly neutralize electric charges remaining in pixels of the display panel according to the compensated gate diver turn-on voltage. Therefore, the power-off residual images produced when the LCD is in power-off would be eliminated. 
     It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. 
         FIG. 1  is a system diagram of an LCD according to an embodiment of the present invention. 
         FIG. 2  is a circuit diagram of a compensation unit according to an embodiment of the present invention. 
         FIG. 3  is a waveform diagram of a gate driver turn-on voltage (V GH ), a common voltage (V COM ) and a gate driver turn-on current (I GH ) in conventional. 
         FIG. 4  is a waveform diagram of a gate driver turn-on voltage (V GH ), a common voltage (V COM ) and a gate driver turn-on current (I GH ) according to an embodiment of the present invention. 
         FIG. 5  is a flow chart of a method for eliminating power-off residual images in a display according to an embodiment of the present invention. 
     
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts. 
     The present invention is directed to effectively eliminate power-off residual images produced when the LCD is in power-off. Below, the characteristics and advantages of the technique in the present invention will be described in detail. 
       FIG. 1  is a system diagram of an LCD according to an embodiment of the present invention. Referring to  FIG. 1 , the LCD  100  includes an LCD panel  101 , a control board  103 , a flexible printed circuit board (FPC)  105  and a backlight module  107  for providing backlight source to the display panel  101 . 
     In the present embodiment, the LCD panel  101  includes a gate driver  101   a  and display unit  101   b . The gate driver  101   a  is directly disposed on one side of the glass substrate of the LCD  101  through a chip-on-glass (COG) process. The display unit  101   b  includes a plurality of scan lines (not shown in  FIG. 1 ), and each scan line includes a plurality of pixels. 
     The control board  103  includes a power supply unit  103   a , a compensation unit  103   b , a low voltage detection unit  103   c  and a timing controller (T-con)  103   d . In the present embodiment, the control board  103  connects with the LCD panel  101  through the FPC  105  manufactured by chip-on-film (COF) process, wherein a source driver  105   a  is disposed on the FPC  105 . 
     In general, the operations of the gate and the source drivers are controlled by the timing controller  103   d  through the FPC  105 , so as to further collocate with the backlight module  107  for making the display unit  101   b  display images to user watch. However, such display technical is not the focal point for the present invention, and one person having ordinary skilled in the art should be known such display technical, so that the detail about such display technical would be omitted herein. Below, the focal point of the technique in the present invention will be described in detail. 
     The power supply unit  103   a  is used for providing a plurality of system voltages, such as a compensation voltage (for example, a common voltage V com  in the present invention), a enabling voltage (for example, a gate driver turn-on voltage V LH  in the present invention), a disabling voltage (for example, a gate driver turn-off voltage V GL  in the present invention), and a logic operating voltage V cc , which all are needed by the LCD panel  101 . 
     Referring to Description of the Related Art, it can be known that, in conventional, since the velocity of discharge of a gate driver turn-on voltage (i.e. V GH ) supplied to the gate driver and generated from a power supply unit of the control board is too fast when the LCD is in power-off, so that the gate driver is incapable of successfully turning on all scan lines of the LCD panel to neutralize electric charges remaining in pixels of the LCD panel. In other words, the gate driver turn-on voltage (i.e. V GH ) supplied to the gate driver and generated from the power supply unit of the control board is incapable of turning on all scan lines of the LCD panel when the conventional LCD is in power-off. Therefore, the power-off residual images eventually produce when the conventional LCD is in power-off. 
     Accordingly, the compensation unit  103  of the present embodiment would compensate the enabling voltage (i.e. V GH ) according to the compensation voltage (i.e. V COM ) when the LCD  100  is in power-off, so that the gate driver  101   a  is still capable of turning on all scan lines within the LCD panel  101   b  when the LCD  100  is in power-off. 
     It should be noted that the reason why the present embodiment employs the common voltage V COM  to compensate the gate diver turn-on voltage V GH . This is because of the velocity of discharge of the common voltage V COM  is slower than the velocity of discharge of the gate driver turn-on voltage V GH  when the LCD  100  is in power-off. However, the present invention is not limited to employ the common voltage V COM  to compensate the gate diver turn-on voltage V GH . In other words, any system voltage, which is different from the common voltage V COM  and which velocity of discharge is slower than the gate diver turn-on voltage V GH  when the LCD  100  is in power-off, can be replaced with the common voltage V COM  and employed to compensate the gate diver turn-on voltage V GH . 
     For clearly explaining why the compensation unit  103  can be compensated the enabling voltage (i.e. the gate diver turn-on voltage V GH ) according to the compensation voltage (i.e. the common voltage V COM ) when the LCD  100  is in power-off.  FIG. 2  is a circuit diagram of the compensation unit according to an embodiment of the present invention. Referring to  FIGS. 1 and 2  both, the compensation unit  103   b  includes a diode D and a current limiting resistor R. An anode of the diode D is used for receiving the compensation voltage (i.e. the common voltage V COM ), and a cathode of the diode D is used for receiving the enabling voltage (i.e. the gate diver turn-on voltage V GH ) through the current limiting resistor R. The resistance value of the current limiting resistor R can be determined by any design requirements. 
     In the present embodiment, since the velocity of discharge of the common voltage V COM  is slower than the velocity of discharge of the gate diver turn-on voltage V GH  when the LCD  100  is in power-off, so that when the voltage level of the common voltage V COM  is higher than the gate diver turn-on voltage V GH  to a forward bias of the diode D, the diode D then will conduct for making the common voltage V COM  to compensate the gate diver turn-on voltage V GH . 
     From the above, referring to  FIGS. 1 and 2  both again, the low voltage detection unit  103   c , such as a low voltage detection IC, is used for detecting whether the logic operating voltage V CC  is lower than a predetermined value when the LCD  100  is in power-off, wherein the predetermined value can be determined by any design requirements. In the present embodiment, when the logic operating value V CC  is lower than the predetermined value, the low voltage detection unit  103   c  would output a low voltage signal LS to the XAO pin of the gate driver  101   a  through the FPC  105 , and then the gate driver  101   a  would turn on all scan lines within the display unit  101   b  to rapidly neutralize electric charges remaining in the pixels of each scan line according to the compensated enabling voltage (i.e. the compensated gate driver turn-on voltage V GH ). Therefore, the power-off residual images produced when the LCD  100  is in power-off would be eliminated effectively. 
     For one person having ordinary skilled in the art to know what the technical efficiency of the compensation unit  103   b  in the present embodiment. Below, several experimental waveform diagrams will show for one person having ordinary skilled in the art to reference. 
       FIG. 3  is a waveform diagram of a gate driver turn-on voltage (V GH ), a common voltage (V COM ) and a gate driver turn-on current (I GH ) in conventional.  FIG. 4  is a waveform diagram of a gate driver turn-on voltage (V GH ), a common voltage (V COM ) and a gate driver turn-on current (I GH ) according to an embodiment of the present invention. Referring to  FIGS. 3 and 4  both, the symbol Toff in  FIGS. 3 and 4  represents the power-off timing of the LCD. Accordingly, in  FIG. 3 , the gate driver turn-on voltage (V GH ) rapidly discharges to 0V when the conventional LCD is in power-off, so that the gate driver turn-on current (I GH ) is incapable of turning on anyone of scan lines within the LCD panel when the LCD is in power-off. 
     On the contrary, in  FIG. 4 , since the gate driver turn-on voltage (V GH ) would be compensated by the common voltage (V COM ) when the LCD  100  is in power-off, so that the gate driver turn-on voltage (V GH ) would not rapidly pull down to 0V. Accordingly, the gate driver turn-on current (I GH ) of the present invention is capable of turning on all scan lines within the LCD panel  101  to neutralize electric charges remaining the pixels of the LCD panel  101  when the LCD  100  is in power-off. Therefore, the power-off residual images produced when the LCD  100  is in power-off would be eliminated effectively. 
     According to the content disclosed in the above embodiment, a method for eliminating power-off residual images in a display is summarized below for those skilled in the art.  FIG. 5  is a flow chart of a method for eliminating power-off residual images in a display according to an embodiment of the present invention. Referring to  FIG. 5 , the method of the present embodiment includes the following steps. Firstly, as shown in step S 501 , provide a compensation voltage to compensate an enabling voltage which is used for sequentially turning on all of scan lines within a display panel when a display is in power-off. Next, as shown in step S 503 , turn on the scan lines to neutralize electric charges remaining in pixels of each scan line according to the compensated enabling voltage. 
     The method of the present embodiment is at least adapted for eliminating residual images produced when an LCD is in power-off. Moreover, the velocity of discharge of the compensation voltage (for example, the common voltage V COM  in the present embodiment) is slower than the velocity of discharge of the enabling voltage (for example, the gate drive turn-on voltage V GH  in the present embodiment), and the enabling voltage is incapable of turning on anyone of scan lines within the display panel when the LCD is in power-off. Furthermore, in accordance with the above embodiment, it can be known that when the LCD is in power-off, all of compensation mechanizes/methods and circuits to compensate the gate driver turn-on voltage (V GH ) should fall into the scope of the present invention. 
     In summary, the method and the control board provided by the present invention firstly employ the common voltage (V COM ) to compensate the gate driver turn-on voltage (V GH ) when the LCD is in power-off, and then turning on all scan lines within the display panel to rapidly neutralize electric charges remaining in pixels of the display panel according to the compensated gate diver turn-on voltage. Therefore, the power-off residual images produced when the LCD is in power-off would be eliminated. 
     It will be apparent to those skills in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.