Patent Publication Number: US-7911037-B1

Title: Method and structure for creating embedded metal features

Description:
RELATED APPLICATIONS 
     This application is a continuation of Huemoeller et al., U.S. patent application Ser. No. 11/543,540, filed on Oct. 4, 2006, now U.S. Pat. No. 7,589,398, issued on Sep. 15, 2009, which is herein incorporated by reference in its entirety. 
    
    
     BACKGROUND 
     1. Field 
     The present invention relates to the field of integrated circuits and packaging and, in particular, to metal trace and feature formation processes and structures. 
     2. Description of Related Art 
     As the electronic arts have moved to smaller and lighter weight devices, it has become increasingly important that integrated circuits and integrated circuit packages process greater numbers of signals and provide for greater density of signal routing features such as signal traces and bias traces associated with substrates used in both integrated circuits and integrated circuit packages. As a result, it is desirable to minimize the width of signal and bias traces and place as many signal traces as possible on a given substrate. However, this means electrical properties, such as impedance and shielding provided by the bias traces must be more accurately controlled. 
     Currently used substrates typically include a substrate first surface and a substrate second surface, opposite the substrate first surface with a substrate body, or thickness, between the two surfaces. Currently used substrates also typically include bias traces, such as ground and/or power and/or voltage potential traces, and signal traces, such as input/output (I/O), or data, signal traces formed on one of the substrate surfaces, such as the substrate first surface, as well as a bias plane, such as a ground and/or power and/or voltage potential plane, attached to the opposite substrate surface, such as the substrate second surface. As a result, an electric field between the bias traces, the signal traces, and the bias plane has a generally vertical orientation and the electrical properties provided by the bias traces, such as impedance control and shielding, are provided in vertically offset planes of bias traces and signal traces, typically offset by the thickness of the substrate. 
     What is needed is a method and apparatus that allows for greater accuracy and control of the electrical properties provided by bias traces. 
     SUMMARY 
     According to one embodiment, a method and structure for creating embedded metal features includes a dielectric layer wherein bias and signal traces are embedded in a first surface of the dielectric layer and extend into the dielectric layer. 
     According to one embodiment, bias trace and signal trace trenches are formed into the dielectric layer using LASER ablation, or other ablation, techniques. Using ablation techniques to form the bias and signal trace trenches, as disclosed herein, allows for extremely accurate control of the depth, width, shape, and horizontal displacement of the bias and signal trace trenches, often on the order of a single micron. As a result, the distance between the bias traces and the signal traces eventually formed in the trenches, and therefore the electrical properties, such as impedance and noise shielding, provided by the bias traces, can also be very accurately controlled. In addition, the depth of the bias and signal traces can also be very accurately controlled for better, and more accurate, signal shielding. Consequently, using the embedded trace substrates disclosed herein, the ability to accurately control the electrical properties provided by the bias traces is greatly improved over current structures; in one embodiment on the order of a ten-fold increase in accuracy is achieved. 
     In addition, using the method and structure for creating embedded metal features disclosed herein, significant improvements in substrate miniaturization can be achieved. This is because, using the method and structure for creating embedded metal features disclosed herein, the bias trace and signal trace structures are co-planar and this helps to reduce typical differential line widths by 20% to 50% compared with currently used structures. This reduction leads to reduced substrate layer counts and/or reduced overall integrated circuit package size. 
     In addition, as discussed above, the impedance for currently used substrates is controlled by a ground/bias layer, in contrast, using the method and structure for creating embedded metal features disclosed herein, the impedance is controlled by the surrounding, and co-planar, bias traces. As a result, any cut or discontinuity of the surface under the signal traces will not effect the impedance of the signal traces. 
     In addition, using the method and structure for creating embedded metal features disclosed herein, strong coupling between bias traces and signal traces is provided. This is because, in one embodiment, the signals are routed in a coplanar structure with a given signal trace “sandwiched” between two bias traces, so the signal trace is guarded by two surrounding bias traces, in one embodiment by a spacing on the order of 10 micrometers. This shortened distance between signal and bias traces provided by the method and structure for creating embedded metal features disclosed herein creates a strong coupling, especially when compared with the typical 35 micrometer spacing for current substrates. 
     In addition, since the bias and signal traces of the embedded trace substrates disclosed herein are embedded in the dielectric layer, the horizontal width of the bias traces at the dielectric layer surface can be accurately controlled and/or minimized. Therefore, more bias and signal traces can be formed in a given dielectric layer while, at the same time, providing improved electrical performance. 
     In addition, using the method and structure for creating embedded metal features disclosed herein, improved, i.e., decreased, crosstalk among signal traces results because, using the method and structure for creating embedded metal features disclosed herein, in one embodiment, a bias trace is positioned between signal traces. As a result, crosstalk between signal traces is minimized as the bias trace absorbs the electromagnetic waves between the trace signals. 
     In one embodiment, an embedded trace substrate includes one or more bias traces embedded in the dielectric layer such that a first surface of the one or more bias traces is substantially level with, or slightly above or below, a first surface of the dielectric layer and the one or more bias traces extend into the dielectric layer. 
     In one embodiment, an embedded trace substrate includes one or more signal traces embedded in the dielectric layer such that a first surface of the one or more signal traces is substantially level with, or slightly above or below, a first surface of the dielectric layer. 
     As noted above, according to one embodiment, the bias and signal traces are embedded into the dielectric layer itself using ablation techniques that provide accuracy tolerances on the order of a single micron. As a result, the electrical properties of bias traces can be accurately controlled by the precise placement of the bias trace with respect to the corresponding signal trace, and by accurately controlling the depths of the bias traces within the dielectric layer. Consequently, the embedded trace substrates disclosed herein provide a mechanism for controlling impedance levels and shielding provided by the bias traces with much tighter tolerances than are provided by current structures. 
     In addition, the embedded trace substrates disclosed herein allow shielding and impedance control of signal traces in the same horizontal plane. In addition, the embedded trace substrates disclosed herein reduce the need for additional metal layers to provide horizontal displacement of signal and bias traces, connect bias signals, or to manage electric signal performance. Therefore, the embedded trace substrates disclosed herein improve electrical performance in a simpler structure, with fewer elements to potentially fail. 
     In addition, as discussed in more detail below, using the below embodiments, with little or no modification, there is considerable flexibility, adaptability, and opportunity for customization to meet the specific needs of various users of the invention under numerous circumstances. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1A  shows a representation of a cutaway side view of an embedded trace substrate in accordance with the principles of one embodiment; 
         FIG. 1B  shows a representation of a cutaway side view of an embedded trace substrate in accordance with the principles of one embodiment; 
         FIG. 2A  shows a representation of a cutaway side view of a substrate prior to processing in accordance with the principles of one embodiment; 
         FIG. 2B  shows a representation of a cutaway side view of a partially processed substrate structure after a first bias trace trench has been formed into the first surface of the substrate of  FIG. 2A  in accordance with the principles of one embodiment; 
         FIG. 2C  shows a representation of a cutaway side view of a partially processed substrate structure after first and second signal trace trenches have been formed into the first surface of the structure of  FIG. 2B  in accordance with the principles of one embodiment; 
         FIG. 2D  shows a representation of a cutaway side view of a partially processed substrate structure after a second bias trace trench has been formed into the first surface of the structure of  FIG. 2C  in accordance with the principles of one embodiment; 
         FIG. 2E  shows a representation of a cutaway side view of a partially processed substrate structure after a seed layer has been applied to a first surface of the substrate structure of  FIG. 2D , including the surfaces of the first bias trace trench, first and second signal trenches, and second bias trace trench in accordance with the principles of one embodiment; 
         FIG. 2F  shows a representation of a cutaway side view of a partially processed substrate structure after a layer of conductive material has been applied to a first surface of the substrate structure of  FIG. 2E , and filled the first bias trace trench, the first and second signal trenches, and the second bias trace trench with conductive material, thereby forming a first bias trace, first and second signal traces, and a second bias trace, in accordance with the principles of one embodiment; 
         FIG. 2G  shows a representation of a cutaway side view of the structure of  FIG. 2F  after excess conductive material has been removed to yield an embedded trace substrate in accordance with one embodiment; 
         FIG. 3  shows a representation of a cutaway side view of a multi-depth embedded trace substrate in accordance with the principles of one embodiment; 
         FIG. 4  shows a representation of a cutaway side view of an embedded trace substrate with bias plane in accordance with the principles of one embodiment; 
         FIG. 5A  shows a representation of a cutaway side view of an in-plane and out-of-plane embedded trace substrate in accordance with the principles of one embodiment; 
         FIG. 5B  shows a representation of a cutaway side view of an in-plane and out-of-plane embedded trace substrate in accordance with the principles of one embodiment; 
         FIG. 5C  shows a representation of a cutaway side view of an in-plane and out-of-plane embedded trace substrate in accordance with the principles of one embodiment; 
         FIG. 5D  shows a representation of a cutaway side view of an in-plane and out-of-plane embedded trace substrate in accordance with the principles of one embodiment; 
         FIG. 6A  shows a representation of a cutaway side view of a substrate prior to processing in accordance with the principles of one embodiment; 
         FIG. 6B  shows a representation of a cutaway side view of a partially processed substrate structure in accordance with the principles of one embodiment; 
         FIG. 6C  shows a representation of a cutaway side view of a partially processed substrate structure in accordance with the principles of one embodiment; 
         FIG. 6D  shows a representation of a cutaway side view of a partially processed substrate structure in accordance with the principles of one embodiment; 
         FIG. 6E  shows a representation of a cutaway side view of a partially processed substrate structure in accordance with the principles of one embodiment; 
         FIG. 6F  shows a representation of a cutaway side view of a partially processed substrate structure in accordance with one embodiment; 
         FIG. 6G  shows a representation of a cutaway side view of a partially processed substrate structure in accordance with one embodiment; 
         FIG. 6H  shows a representation of a cutaway side view of a partially processed substrate structure in accordance with one embodiment; 
         FIG. 6I  shows a representation of a cutaway side view of a partially processed substrate structure in accordance with one embodiment; 
         FIG. 6J  shows a representation of a cutaway side view of a partially processed substrate structure in accordance with the principles of one embodiment; 
         FIG. 6K  shows a representation of a cutaway side view of a partially processed substrate structure in accordance with one embodiment; 
         FIG. 6L  shows a representation of a cutaway side view of the structure of  FIG. 6J  after excess conductive material has been removed to yield an in-plane and out-of-plane embedded trace substrate in accordance with the principles of one embodiment; 
         FIG. 7  shows a representation of a cutaway side view of an embedded trace substrate in accordance with the principles of one embodiment; and 
         FIG. 8  shows a representation of a cutaway side view of an embedded trace substrate in accordance with the principles of one embodiment. 
     
    
    
     Common reference numerals are used throughout the FIGS. and the detailed description to indicate like elements. One skilled in the art will readily recognize that the above FIGS. are examples and that other structures, orders of fabrication and elements/functions can be provided and implemented without departing from the characteristics and features of the invention, as set forth in the claims. 
     DETAILED DESCRIPTION 
     According to one embodiment, a method and structure for creating embedded metal features includes embedded trace substrates ( 100 A in  FIG. 1A ,  100 B in  FIG. 1B ,  200  in  FIG. 2G ,  300  in  FIG. 3 ,  400  in  FIG. 4 ,  500  in  FIG. 5A ,  600  in  FIG. 6L ,  700  in  FIGS. 7 and 800  in  FIG. 8 ) wherein bias and signal traces are embedded in a first surface of a dielectric layer of the embedded trace substrate and extend into the dielectric layer. 
     As used herein, the term “bias” refers to any electrical potential such as ground or power, and the term “bias trace” includes any bias traces, such as ground and/or power and/or voltage potential traces. In addition, as used herein, “bias plane” includes any bias plane structure, such as ground and/or power and/or voltage potential plane. In addition, the term “signal trace” includes any trace capable of conducting, transmitting, propagating, or otherwise carrying or transferring an electrical signal or data. 
     According to one embodiment, bias trace and signal trace trenches are formed into the dielectric layer of the substrate body using LASER ablation, or other ablation, techniques. Using ablation techniques to form the bias and signal trace trenches, as disclosed herein, allows for extremely accurate control of the depth, width, shape, and horizontal displacement of the bias and signal trace trenches, often on the order of a single micron. As a result, the distance between the bias traces and the signal traces eventually formed in the trenches, and therefore the electrical properties, such as impedance and noise shielding, provided by the bias traces, can also be very accurately controlled. In addition, the depth of the bias and signal traces can also be very accurately controlled for better, and more accurate, signal shielding. Consequently, using the embedded trace substrates disclosed herein, the ability to accurately control the electrical properties provided by the bias traces is greatly improved over current structures; in one embodiment on the order of a ten-fold increase in accuracy is achieved. 
     In addition, since the bias and signal traces of the embedded trace substrates disclosed herein are embedded in the embedded trace substrate, the horizontal width of the bias traces at the embedded trace substrate surface can be accurately controlled and/or minimized. Therefore, more bias and signal traces can be formed in a given embedded trace substrate while, at the same time, providing improved electrical performance. 
     In addition, using the method and structure for creating embedded metal features disclosed herein, significant improvements in substrate miniaturization can be achieved. This is because, using the method and structure for creating embedded metal features disclosed herein, the bias trace and signal trace structures are co-planar and this helps to reduce typical differential line widths by 20% to 50% compared with currently used structures. This reduction leads to reduced substrate layer counts and/or reduced overall integrated circuit package size. 
     In addition, as discussed above, the impedance for currently used substrates is controlled by a ground/bias layer, in contrast, using the method and structure for creating embedded metal features disclosed herein, the impedance is controlled by the surrounding and co-planar bias traces. As a result, any cut or discontinuity of the surface under the signal traces will not effect the impedance of the signal traces. 
     In addition, using the method and structure for creating embedded metal features disclosed herein, strong coupling between bias traces and signal traces is provided. This is because, in one embodiment, the signals are routed in a coplanar structure with a given signal trace “sandwiched” between two bias traces, so the signal trace is guarded by two surrounding bias traces, in one embodiment at a spacing on the order of 10 micrometers. This shortened distance between signal and bias traces provided by the method and structure for creating embedded metal features disclosed herein creates a strong coupling, especially when compared with the typical 35 micrometer spacing for current substrates. 
     In addition, since the bias and signal traces of the embedded trace substrates disclosed herein are embedded in the dielectric layer, the horizontal width of the bias traces at the dielectric layer surface can be accurately controlled and/or minimized. Therefore, more bias and signal traces can be formed in a given dielectric layer while, at the same time, providing improved electrical performance. 
     In addition, using the method and structure for creating embedded metal features disclosed herein, improved, i.e., decreased, crosstalk among signal traces results because, using the method and structure for creating embedded metal features disclosed herein, in one embodiment, a bias trace is positioned between signal traces. As a result, crosstalk between signal traces is minimized as the bias trace absorbs the electromagnetic waves between the trace signals. 
     In one embodiment, an embedded trace substrate includes at least one bias trace embedded in the dielectric layer of the embedded trace substrate body such that a first surface of the at least one bias trace is substantially level with, or slightly above or below, a first surface of the embedded trace substrate and the at least one bias trace extends into the dielectric layer. 
     In one embodiment, an embedded trace substrate includes at least one signal trace embedded in the dielectric layer of the embedded trace substrate such that a first surface of the at least one signal trace is substantially level with, or slightly above or below, a first surface of the embedded trace substrate. 
     As noted above, according to one embodiment, the bias and signal traces are embedded into the dielectric layer of the embedded trace substrate body itself using ablation techniques that provide accuracy tolerances on the order of a single micron. As a result, the electrical properties of bias traces can be accurately controlled by the precise placement of the bias trace with respect to the corresponding signal trace, and by accurately controlling the depths of the bias traces within the embedded trace substrate body. Consequently, the embedded trace substrates disclosed herein provide a mechanism for controlling impedance levels and shielding provided by the bias traces with much tighter tolerances than are provided by current structures. 
     In addition, the embedded trace substrates disclosed herein allow shielding and impedance control of signal traces in the same horizontal plane. In addition, the embedded trace substrates disclosed herein reduce the need for additional metal layers to provide horizontal displacement of signal and bias traces, connect bias signals, or to manage electric signal performance. Therefore, the embedded trace substrates disclosed herein improve electrical performance in a simpler structure, with fewer elements to potentially fail. 
     In particular,  FIG. 1A  shows a representation of a cutaway side view of an embedded trace substrate  100 A in accordance with the principles of one embodiment. As shown in  FIG. 1A , embedded trace substrate  100 A includes: dielectric layer first surface  103 A; dielectric layer second surface  105 A, opposite dielectric layer first surface  103 A; dielectric layer  101 A, positioned between dielectric layer first surface  103 A and dielectric layer second surface  105 A; first bias trace  107 A; second bias trace  111 A; first signal trace  109 A; and portions of seed layer  161 A. 
     In one embodiment, dielectric layer  101 A is made of any of the numerous substrate materials known to those of skill in the art such as Prepreg, or any other primarily dielectric material, whether known at the time of filing or developed later. As discussed in more detail below, in one embodiment, seed layer  161 A is applied to prepare dielectric layer  101 A to receive a conductive layer. In one embodiment, seed layer  161 A is a layer of metal, such as copper. In other embodiments, seed layer  161 A can be any metal or other material desired, whether known at the time of filing or as developed later. In one embodiment, first bias trace  107 A, first signal trace  109 A, and second bias trace  111 A are made of conductive material, such as a metal, filling trenches formed by LASER ablation, as discussed in more detail below. 
     As shown in  FIG. 1A , in one embodiment, first bias trace  107 A includes a first bias trace first surface  123 A that is substantially level with, or slightly above or below, dielectric layer first surface  103 A. In one embodiment, first bias trace  107 A is embedded within dielectric layer  101 A of embedded trace substrate  100 A a first bias trace depth  141 A below dielectric layer first surface  103 A. First bias trace  107 A also includes a horizontal width  115 A. 
     As also shown in  FIG. 1A , in one embodiment, second bias trace  111 A includes a second bias trace first surface  129 A that is substantially level with, or slightly above or below, dielectric layer first surface  103 A. In one embodiment, second bias trace  111 A is embedded within embedded trace substrate body  101 A a second bias trace depth  143 A below dielectric layer first surface  103 A. Second bias trace  111 A also includes a horizontal width  116 A 
     As also shown in  FIG. 1A , in one embodiment, first signal trace  109 A includes a first signal trace first surface  128 A that is substantially level with, or slightly above or below, dielectric layer first surface  103 A. In one embodiment, first signal trace  109 A is embedded within dielectric layer  101 A of embedded trace substrate  100 A a first signal trace depth  125 A below dielectric layer first surface  103 A. First signal trace  109 A also includes a horizontal width  117 A. As also shown in  FIG. 1A , in one embodiment, first signal trace  109 A is positioned horizontally between first bias trace  107 A and second bias trace  111 A such that an electric field between first bias trace  107 A, first signal trace  109 A and second bias trace  111 A is oriented horizontally as shown by arrow  113 A. 
     Also show in  FIG. 1A  are first horizontal spacing  131 A between first bias trace  107 A and first signal trace  109 A; and second horizontal spacing  133 A between first signal trace  109 A and second bias trace  111 A. As noted above, according to one embodiment, first bias trace  107 A, first signal trace  109 A, and second bias trace  111 A are formed into substrate body  101 A using LASER ablation, or other ablation, techniques. Using ablation techniques to form first bias trace  107 A, first signal trace  109 A, and second bias trace  111 A, as disclosed herein, allows for very accurate control, on the order of a single micron, of first horizontal spacing  131 A and second horizontal spacing  133 A, as well as first bias trace horizontal width  115 A, first signal trace horizontal width  117 A, and second bias trace horizontal width  116 A. Consequently, the control impedance provided by first bias trace  107 A and second bias trace  111 A can also be very accurately controlled; in some embodiments, to the order of a single ohm. 
     In addition, using ablation techniques to form first bias trace  107 A, first signal trace  109 A, and second bias trace  111 A, as disclosed herein, allows for very accurate control, on the order of a single micron, of: first bias trace depth  141 A; second bias trace depth  143 A; and first signal trace depth  125 A. Consequently, the shielding provided by first bias trace  107 A and second bias trace  111 A can also be very accurately controlled. In addition, using ablation techniques to form first bias trace  107 A, first signal trace  109 A, and second bias trace  111 A, as disclosed herein, allows for very accurate control, on the order of a single micron, of: first bias trace horizontal width  115 A; first signal trace horizontal width  117 A; and second bias trace horizontal width  116 A. This fact also provides for tighter impedance tolerances. 
     In other embodiments, it is desirable to include more than one signal trace, such as first signal trace  109 A of embedded trace substrate  100 A, in an embedded trace substrate. In particular,  FIG. 1B  shows a representation of a cutaway side view of an embedded trace substrate  100 B in accordance with the principles of one embodiment. As shown in  FIG. 1B , embedded trace substrate  100 B includes: dielectric layer first surface  103 B; dielectric layer second surface  105 B, opposite dielectric layer first surface  103 B; dielectric layer  101 B, positioned between dielectric layer first surface  103 B and dielectric layer second surface  105 B; first bias trace  107 B; second bias trace  111 B; first signal trace  109 B; second signal trace  110 B; and portions of seed layer  161 B. 
     In one embodiment, dielectric layer  101 B is made of any of the numerous substrate materials known to those of skill in the art such as Prepreg, or any other primarily dielectric substrate material, whether known at the time of filing or developed later. As discussed in more detail below, in one embodiment, seed layer  161 B is applied to prepare dielectric layer  101 B to receive a conductive layer. In one embodiment, seed layer  161 B is a layer of metal, such as copper. In other embodiments, seed layer  161 B can be any metal or other material desired, whether known at the time of filing or as developed later. In one embodiment, first bias trace  107 B, first signal trace  109 B, second signal trace  110 B, and second bias trace  111 B are made of conductive material, such as a metal, filling trenches formed by LASER ablation, as discussed in more detail below. 
     As shown in  FIG. 1B , in one embodiment, first bias trace  107 B includes a first bias trace first surface  123 B that is substantially level with, or slightly above or below, dielectric layer first surface  103 B. In one embodiment, first bias trace  107 B is embedded within dielectric layer  101 B of embedded trace substrate  100 B a first bias trace depth  141 B below dielectric layer first surface  103 B. First bias trace  107 B also includes a first bias trace horizontal width  115 B. 
     As also shown in  FIG. 1B , in one embodiment, second bias trace  111 B includes a second bias trace first surface  129 B that is substantially level with, or slightly above or below, dielectric layer first surface  103 B. In one embodiment, second bias trace  111 B is embedded within dielectric layer  101 B a second bias trace depth  143 B below dielectric layer first surface  103 B. Second bias trace  111 B also includes a second bias trace horizontal width  116 B 
     As also shown in  FIG. 1B , in one embodiment, first signal trace  109 B includes a first signal trace first surface  128 B that is substantially level with, or slightly above or below, dielectric layer first surface  103 B. In one embodiment, first signal trace  109 B is embedded within dielectric layer  101 B of embedded trace substrate  100 B a first signal trace depth  125 B below dielectric layer first surface  103 B. First signal trace  109 B also includes a first signal trace horizontal width  117 B. 
     As also shown in  FIG. 1B , in one embodiment, second signal trace  110 B includes a second signal trace first surface  147 B that is substantially level with, or slightly above or below, dielectric layer first surface  103 B. In one embodiment, second signal trace  110 B is embedded within dielectric layer  101 B of embedded trace substrate  100 B a second signal trace depth  145 B below dielectric layer first surface  103 B. Second signal trace  110 B also includes a second signal trace horizontal width  118 B. 
     As also shown in  FIG. 1B , in one embodiment, first signal trace  109 B is positioned horizontally between first bias trace  107 B and second signal trace  110 B. In addition, second signal trace  110 B is positioned horizontally between first signal trace  109 B and second bias trace  111 B. Consequently, an electric field between first bias trace  107 B and first signal trace  109 B and second signal trace  110 B and second bias trace  111 B is oriented horizontally as shown by arrows  113 B and  149 B. 
     Also show in  FIG. 1B  are first horizontal spacing  131 B between first bias trace  107 B and first signal trace  109 B; second horizontal spacing  133 B between first signal trace  109 B and second signal trace  110 B; and third horizontal spacing  135 B between second signal trace  110 B and second bias trace  111 B. As noted above, according to one embodiment, first bias trace  107 B, first signal trace  109 B, second signal trace  110 B, and second bias trace  111 B are formed into dielectric layer  101 B using LASER ablation, or other ablation, techniques. Using ablation techniques to form first bias trace  107 B, first signal trace  109 B, second signal trace  110 B, and second bias trace  111 B, as disclosed herein, allows for very accurate control, on the order of a single micron, of first horizontal spacing  131 B, second horizontal spacing  133 B, and third horizontal spacing  135 B. Consequently, the impedance provided by first bias trace  107 B and second bias trace  111 B can also be very accurately controlled; in some embodiments, to the order of a single ohm. 
     In addition, using ablation techniques to form first bias trace  107 B, first signal trace  109 B, second signal trace  110 B, and second bias trace  111 B, as disclosed herein, allows for very accurate control, on the order of a single micron, of: first bias trace depth  141 B; second bias trace depth  143 B; first signal trace depth  125 B; and second signal trace depth  145 B. Consequently, the shielding provided by first bias trace  107 B and second bias trace  111 B can also be very accurately controlled. In addition, using ablation techniques to form first bias trace  107 B, first signal trace  109 B, second signal trace  110 B, and second bias trace  111 B, as disclosed herein, allows for very accurate control, on the order of a single micron, of: first bias trace horizontal width  115 B; first signal trace horizontal width  117 B; second signal trace horizontal width  118 B, and second bias trace horizontal width  116 B. This fact also provides for tighter impedance tolerances. 
     As discussed above, using ablation techniques to form the bias and signal trace trenches, as disclosed herein, the depth, width, shape, and horizontal displacement of the bias and signal trace trenches can be controlled extremely accurately, on the order of a single micron. Therefore, the horizontal distance, such as horizontal distances  131 A,  133 A,  131 B,  133 B, and  135 B, between the bias traces and the signal traces, such as bias traces  107 A,  111 A,  107 B and  111 B and signal traces  109 A,  109 B and  110 B of  FIGS. 1A and 1B , eventually formed in the trenches, and therefore the signal control impedance provided by the bias traces, can be very accurately controlled. In addition, the depth of the bias traces can also be very accurately controlled for better, and more accurate, signal shielding. Consequently, using embedded trace substrates  100 A and  100 B, the ability to accurately control the electrical properties provided by the bias traces is greatly improved over current bias traces. In one embodiment on the order of a ten-fold increase in accuracy is achieved. 
     In addition, since the bias and signal traces disclosed herein are embedded in the embedded trace substrate, the horizontal width of the bias traces, such as widths  115 A,  115 B,  117 A,  117 B,  116 A,  116 B and  118 B of  FIGS. 1A and 1B , at the embedded trace substrate surface, such as dielectric layer first surfaces  103 A and  103 B of embedded trace substrates  100 A and  100 B, can be minimized. Therefore, more bias and signal traces can be formed in a given embedded trace substrate while, at the same time, providing improved electrical performance. 
     In addition, embedded trace substrates  100 A and  100 B provide for in-horizontal plane electrical management versus the alternate horizontal plane, vertically displaced, electrical management of currently used substrates. That is to say, since first bias traces  107 A and  107 B are horizontally displaced from signal traces  109 A,  109 B, and  110 B, and second bias traces  111 A and  111 B, the electric control field between the traces is horizontally oriented. 
     In addition, the structure of embedded trace substrates  100 A and  100 B allows shielding of signal traces, such as first signal trace  109 A, first signal trace  109 B, and second signal trace  110 B, to bias traces, such as first bias traces  107 A and  107 B and second bias traces  111 A and  111 B, in the same horizontal plane. In addition, the structure of embedded trace substrates  100 A and  100 B reduces the need for additional metal layers to connect bias signals or to manage electric signal performance and therefore the structure of embedded trace substrates  100 A and  100 B improve electrical performance without added structural complexity. 
     In addition, the structure of embedded trace substrates  100 A and  100 B allows for significant improvements in substrate and package miniaturization. This is because, with the structure of embedded trace substrates  100 A and  100 B, the bias traces  107 A,  111 A,  107 B,  111 B and signal traces  109 A,  109 B,  110 B are co-planar and this fact helps to reduce trace widths  115 A,  117 A,  116 A,  115 B,  117 B,  118 B,  116 B, as well as spacings  131 A,  133 A,  131 B,  133 B,  135 B, by 20% to 50% compared with currently used structures. This reduction leads to reduced dielectric layer counts and/or reduced overall integrated circuit package size. 
     In addition, as discussed above, the impedance for currently used substrates is controlled by a ground/bias layer, in contrast, the structure of embedded trace substrates  100 A and  100 B allows the impedance to be controlled by the surrounding and co-planar bias traces  107 A,  111 A,  107 B,  111 B. As a result, any cut or discontinuity of the surface under the signal traces  109 A,  109 B,  110 B will not effect the impedance of signal traces  109 A,  109 B,  110 B. 
     In addition, the structure of embedded trace substrate  100 A allows strong coupling between bias traces  107 A,  111 A and signal trace  109 A. This is because, in one embodiment, the signals are routed in a coplanar structure with a given signal trace  109 A, “sandwiched” between two bias traces  107 A,  111 A, so the signal trace  109 A is guarded by two surrounding bias traces  107 A,  111 A, in one embodiment by a spacing  131 A,  133 A on the order of 10 micrometers. This shortened distance between signal and bias traces provided by the method and structure for creating embedded metal features disclosed herein creates a strong coupling, especially when compared to the typical 35 micrometer spacing for current substrates. 
     In addition, since the bias and signal traces  107 A,  111 A,  107 B,  111 B and  109 A,  109 B,  110 B of embedded trace substrates  100 A and  100 B are embedded in dielectric layer  101 A,  101 B, the horizontal width  115 A,  117 A,  116 A,  115 B,  117 B,  118 B,  116 B of the bias and signal traces  107 A,  111 A,  107 B,  111 B and  109 A,  109 B,  110 B at dielectric layer first surface  103 A,  103 B can be accurately controlled and/or minimized. Therefore, more bias and signal traces  107 A,  111 A,  107 B,  111 B and  109 A,  109 B,  110 B can be formed in a given dielectric layer  101 A,  101 B while, at the same time, providing improved electrical performance. 
     In addition, the structure of embedded trace substrates  100 A and  100 B provides improved, i.e., decreased, crosstalk among signal traces  109 A,  109 B,  110 B because, in one embodiment, a bias trace  107 A,  111 A,  107 B,  111 B is positioned between signal traces  109 A,  109 B,  110 B. As a result, crosstalk between signal traces is minimized as the bias trace absorbs the electromagnetic waves between the trace signals. 
       FIGS. 2A ,  2 B,  2 C,  2 D,  2 E,  2 F, and  2 G together are a representation of some of the fabrication stages making up one embodiment of a method for creating an embedded trace substrate, such as embedded trace substrates  100 A and/or  100 B of  FIG. 1A  and  FIG. 1B , respectively. 
       FIG. 2A  shows a representation of a cutaway side view of a substrate prior to processing in accordance with the principles of one embodiment of a method for creating an embedded trace substrate. 
     As shown in  FIG. 2A , and as discussed above, substrate includes dielectric layer first surface  203  and dielectric layer second surface  205 , opposite dielectric layer first surface  203 , and separated from dielectric layer first surface  203  by dielectric layer  201 . As discussed above, dielectric layer  201  is made of any of the numerous substrate materials known to those of skill in the art such as Prepreg, or any other primarily dielectric substrate material, whether known at the time of filing or as later developed. 
       FIG. 2B  shows a representation of a cutaway side view of a partially processed substrate structure after a first bias trace trench  231  has been ablated into dielectric layer first surface  203  of the substrate of  FIG. 2A  in accordance with the principles of one embodiment. 
     Returning to  FIG. 2B , in one embodiment, first bias trace trench  231  is formed with a first bias trace trench depth  233  into dielectric layer  201  and with a first bias trace trench horizontal width  235  at dielectric layer first surface  203 . In one embodiment, first bias trace trench  231  is created using LASER ablation or any other method for ablating, etching, scratching, digging, or otherwise forming a trench into a substrate, whether known at the time of filing or as developed later. 
       FIG. 2C  shows a representation of a cutaway side view of a partially processed substrate structure after a first signal trace trench  241  and a second signal trace trench  242  have been ablated into dielectric layer first surface  203  of the structure of  FIG. 2B  in accordance with the principles of one embodiment. 
     Returning to  FIG. 2C , in one embodiment, first signal trace trench  241  is formed with a first signal trace trench depth  243  into dielectric layer  201  and with a first signal trace trench horizontal width  245  at dielectric layer first surface  203 . In one embodiment, first signal trace trench  241  is created using LASER ablation or any other method for ablating, etching, scratching, digging, or otherwise forming a trench into a substrate, whether known at the time of filing or as developed later. 
     Likewise, in one embodiment, second signal trace trench  242  is formed with a second signal trace trench depth  244  into dielectric layer  201  and with a second signal trace trench horizontal width  246  at dielectric layer first surface  203 . In one embodiment, second signal trace trench  242  is created using LASER ablation or any other method for ablating, etching, scratching, digging, or otherwise forming a trench into a substrate, whether known at the time of filing or as developed later. 
       FIG. 2D  shows a representation of a cutaway side view of a partially processed substrate structure after a second bias trace trench  251  has been ablated into dielectric layer first surface  203  of the structure of  FIG. 2C  in accordance with the principles of one embodiment. 
     Returning to  FIG. 2D , in one embodiment, second bias trace trench  251  is formed with a second bias trace trench depth  253  into dielectric layer  201  and with a second bias trace trench horizontal width  255  at dielectric layer first surface  203 . In one embodiment, second bias trace trench  251  is created using LASER ablation or any other method for ablating, etching, scratching, digging, or otherwise forming a trench into a substrate, whether known at the time of filing or as developed later. 
       FIG. 2E  shows a representation of a cutaway side view of a partially processed substrate structure after a seed layer  261  has been applied to dielectric layer first surface  203  of structure of  FIG. 2D , including the surfaces of first bias trace trench  231 , first signal trench  241 , second signal trench  242 , and second bias trace trench  251 , in accordance with the principles of one embodiment. 
     Returning to  FIG. 2E , seed layer  261  is applied to prepare dielectric layer first surface  203  to receive a conductive layer. In one embodiment, seed layer  261  is a layer of metal, such as copper. In other embodiments, seed layer  261  can be any metal or other conductive material desired, whether known at the time of filing or as developed later. Methods, apparatuses, and structures associated with applying a seed layer, such as seed layer  261 , to a substrate are well known to those of skill in the art. Consequently, a more detailed discussion of the application of seed layers to a substrate is omitted here to avoid detracting from the invention. 
       FIG. 2F  shows a representation of a cutaway side view of a partially processed substrate structure after a layer of conductive material  271  has been applied to dielectric layer first surface  203 , and seed layer  261  ( FIG. 2E ), of the substrate structure of  FIG. 2E , and filled first bias trace trench  231  ( FIG. 2E ), first signal trench  241  ( FIG. 2E ), second signal trench  242  ( FIG. 2E ) and second bias trace trench  251  ( FIG. 2E ) with conductive material, thereby forming first bias trace  207  ( FIG. 2F ), first signal trace  209  ( FIG. 2F ), second signal trace  210  ( FIG. 2F ) and second bias trace  211  ( FIG. 2F ), in accordance with the principles of one embodiment. 
     In one embodiment, layer of conductive material  271  is a layer of metal, such as copper. In other embodiments, layer of conductive material  271  can be any metal or other conductive material desired, whether known at the time of filing or as developed later. Methods, apparatuses, and structures associated with applying a layer of conductive material, such as layer of conductive material  271 , to a substrate, are well known to those of skill in the art. Consequently, a more detailed discussion of the application of layers of conductive material to a substrate is omitted here to avoid detracting from the invention. 
       FIG. 2G  shows a representation of a cutaway side view of the structure of  FIG. 2F  after excess conductive material of layer of conductive material  271  has been removed to yield embedded trace substrate  200  in accordance with one embodiment. In one embodiment, the excess conductive material of layer of conductive material  271  of  FIG. 2F  is removed using any process for removing conductive material, such as grinding, etching, scraping or any other mechanical or chemical process, whether known at the time of filing or as developed thereafter. 
     Embedded trace substrates  100 A,  100 B discussed above with respect to  FIG. 1A ,  FIG. 1B , respectively, include first bias traces  107 A,  107 B having first bias trace depths  141 A,  141 B that are shown, in the particular examples of  FIG. 1A  and  FIG. 1B , as being substantially similar to second bias trace depths  143 A,  143 B of second bias traces  111 A,  111 B. However, those of skill in the art will readily recognize that the depths of bias traces need not be the same, or even similar, and that in some cases it may be desirable to have significantly different depths for the various bias traces to form a multi-depth embedded trace substrate to provide a multiple electrical properties feature. Since according to one embodiment, the bias and signal traces are embedded in the substrate, and the bias and signal trenches are formed using ablation methods, such as LASER ablation, the depth of the bias and signal traces can be very accurately controlled. Consequently, a variety of depths of bias and signal traces can be created in a single substrate to meet the various needs of the user. 
     For example,  FIG. 3  shows a representation of a cutaway side view of a multi-depth embedded trace substrate  300  in accordance with the principles of one embodiment. As shown in  FIG. 3 , multi-depth embedded trace substrate  300  includes: dielectric layer first surface  303 ; dielectric layer second surface  305 , opposite dielectric layer first surface  303 ; dielectric layer  301 , positioned between dielectric layer first surface  303  and dielectric layer second surface  305 ; first bias trace  307 ; second bias trace  311 ; first signal trace  309 ; third bias trace  327 ; fourth bias trace  331 ; second signal trace  329 ; and portions of seed layer  361 . 
     In one embodiment, dielectric layer  301  is made of any of the numerous substrate materials known to those of skill in the art such as Prepreg, or any other primarily dielectric substrate material, whether known at the time of filing or developed later. As discussed in more detail above, in one embodiment, seed layer  361  is applied to prepare dielectric layer  301  to receive a conductive layer. In one embodiment, seed layer  361  is a layer of metal, such as copper. In other embodiments, seed layer  361  can be any metal or other material desired, whether known at the time of filing or as developed later. In one embodiment, first bias trace  307 , first signal trace  309 , second bias trace  311 , third bias trace  327 , fourth bias trace  331 , and second signal trace  329  are made of conductive material, such as a metal, filling trenches formed by LASER ablation, as discussed in more detail above. 
     As shown in  FIG. 3 , in one embodiment, first bias trace  307  is embedded within dielectric layer  301  of multi-depth embedded trace substrate  300  a first bias trace depth  341  below dielectric layer first surface  303 . First bias trace  307  also has a first bias trace horizontal width  351 . 
     As also shown in  FIG. 3 , in one embodiment, second bias trace  311  is embedded within dielectric layer  301  of multi-depth embedded trace substrate  300  a second bias trace depth  343  below dielectric layer first surface  303 . In addition, in this particular exemplary embodiment, second bias trace depth  343  is less than first bias trace depth  341 . Second bias trace  311  also has a second bias trace horizontal width  353 . 
     As also shown in  FIG. 3 , in one embodiment, first signal trace  309  is embedded within dielectric layer  301  of multi-depth embedded trace substrate  300  a first signal trace depth  342  below dielectric layer first surface  303 . As also shown in  FIG. 3 , in one embodiment, first signal trace  309  is positioned horizontally between first bias trace  307  and second bias trace  311  and has a first signal trace horizontal width  352 . 
     As also shown in  FIG. 3 , in one embodiment, third bias trace  327  is embedded within dielectric layer  301  of multi-depth embedded trace substrate  300  a third bias trace depth  345  below dielectric layer first surface  303 . Third bias trace  327  also has a third bias trace horizontal width  355 . 
     As also shown in  FIG. 3 , in one embodiment, fourth bias trace  331  is embedded within dielectric layer  301  of multi-depth embedded trace substrate  300  a fourth bias trace depth  347  below dielectric layer first surface  303 . In addition, in this particular exemplary embodiment, fourth bias trace depth  347  is substantially the same as third bias trace depth  345 . Fourth bias trace  331  also has a fourth bias trace horizontal width  357 . 
     As also shown in  FIG. 3 , in one embodiment, second signal trace  329  is embedded in dielectric layer  301  of multi-depth embedded trace substrate  300  a second signal trace depth  346  below dielectric layer first surface  303 . In one embodiment, second signal trace depth  346  is different from first signal trace depth  342 . In one embodiment, second signal trace depth  346  is substantially the same as fourth bias trace depth  347  and third bias trace depth  345 . As also shown in  FIG. 3 , in one embodiment, second signal trace  329  is positioned horizontally between third bias trace  327  and fourth bias trace  331 . 
     In some instances it may be desirable to induce both an electric field having a horizontal orientation and an electric field having a vertical orientation. In one embodiment, this is accomplished by adding a bias plane to a second surface of an embedded trace substrate. 
       FIG. 4  shows a representation of a cutaway side view of an embedded trace substrate  400  with bias plane  431  in accordance with the principles of one embodiment. As shown in  FIG. 4 , embedded trace substrate  400  with bias plane  431  includes: dielectric layer first surface  403 ; dielectric layer second surface  405 , opposite dielectric layer first surface  403 ; dielectric layer  401 , positioned between dielectric layer first surface  403  and dielectric layer second surface  405 ; first bias trace  407 ; second bias trace  411 ; first signal trace  409 ; third bias trace  408 ; fourth bias trace  412 ; second signal trace  410 ; bias plane  431 ; and portions of seed layer  461 . 
     In one embodiment, embedded trace substrate with dielectric layer  401  is made of any of the numerous substrate materials known to those of skill in the art such as Prepreg, or any other primarily dielectric substrate material, whether known at the time of filing or developed later. As discussed in more detail above, in one embodiment, seed layer  461  is applied to prepare dielectric layer  401  to receive a conductive layer. In one embodiment, seed layer  461  is a layer of metal, such as copper. In other embodiments, seed layer  461  can be any metal or other material desired, whether known at the time of filing or as developed later. In one embodiment, first bias trace  407 , first signal trace  409 , second bias trace  411 , third bias trace  408 , fourth bias trace  412 , second signal trace  410 , and bias plane  431  are made of conductive material, such as a metal, filling trenches or forming an applied layer and/or formed by LASER ablation, as discussed in more detail above. 
     As shown in  FIG. 4 , in one embodiment, first bias trace  407  is embedded within dielectric layer  401  of embedded trace substrate  400  with bias plane  431  a first bias trace depth  421 A below dielectric layer first surface  403 . First bias trace  407  also has a first bias trace horizontal width  415 A. 
     As also shown in  FIG. 4 , in one embodiment, second bias trace  411  is embedded within dielectric layer  401  of embedded trace substrate  400  with bias plane  431  a second bias trace depth  421 B below dielectric layer first surface  403 . In addition, in this particular exemplary embodiment, second bias trace depth  421 B is substantially similar to first bias trace depth  421 A. Second bias trace  411  also has a second bias trace horizontal width  415 B. 
     As also shown in  FIG. 4 , in one embodiment, first signal trace  409  is embedded within dielectric layer  401  of embedded trace substrate  400  with bias plane  431  a first signal trace depth  423  below dielectric layer first surface  403 . First signal trace  409  also has a first signal trace horizontal width  417 . As also shown in  FIG. 4 , in one embodiment, first signal trace  409  is positioned horizontally between first bias trace  407  and second bias trace  411 . 
     As also shown in  FIG. 4 , in one embodiment, bias plane  431  is attached, or formed, or applied, on embedded trace substrate with bias plane second surface  405  by methods well known to those of skill in the art. The location of bias plane  431  on dielectric layer second surface  405  creates a vertically orientated electric field between first bias trace  407 , second bias trace  411 , and first signal trace  409  and bias plane  431  as indicated by arrow  414 . This vertically orientated electric field is in addition to the horizontally oriented electric field between first bias trace  407 , first signal trace  409  and second bias trace  411  as indicated by arrow  413 . 
     As shown in  FIG. 4 , in one embodiment, third bias trace  408  is embedded within dielectric layer  401  of embedded trace substrate  400  with bias plane  431  a third bias trace depth  422 A below dielectric layer first surface  403  such that third bias trace  408  is in electrical contact with bias plane  431 . Third bias trace  408  also has a third bias trace horizontal width  416 A. 
     As also shown in  FIG. 4 , in one embodiment, fourth bias trace  412  is embedded within dielectric layer  401  of embedded trace substrate  400  with bias plane  431  a fourth bias trace depth  422 B below dielectric layer first surface  403  such that fourth bias trace  412  is also in electrical contact with bias plane  431 . Fourth bias trace  412  also has a fourth bias trace horizontal width  416 B. 
     As also shown in  FIG. 4 , in one embodiment, second signal trace  410  is embedded within dielectric layer  401  of embedded trace substrate  400  with bias plane  431  a second signal trace depth  424  below dielectric layer first surface  403 . Second signal trace  410  also has a second signal trace horizontal width  418 . As also shown in  FIG. 4 , in one embodiment, second signal trace  410  is positioned horizontally between third bias trace  408  and fourth bias trace  412 . 
     In some instances, it is desirable to create a substrate structure wherein bias traces and signal traces are formed in and out of a given horizontal plane.  FIG. 5A  shows a representation of a cutaway side view of an in-plane and out-of-plane embedded trace substrate  500  in accordance with the principles of one embodiment. As shown in  FIG. 5A , in-plane and out-of-plane embedded trace substrate  500  includes: dielectric layer first surface  503 ; dielectric layer second surface  505 , opposite dielectric layer first surface  503 ; dielectric layer  501 , positioned between dielectric layer first surface  503  and dielectric layer second surface  505 ; in-plane first bias trace  507 ; in-plane first signal trace  509 ; in-plane second bias trace  511 ; out-of-plane first bias trace  508 ; out-of-plane first signal trace  510 ; out-of-plane second bias trace  512 ; and portions of seed layer  561 . 
     In one embodiment, dielectric layer  501  is made of any of the numerous substrate materials known to those of skill in the art such as Prepreg, or any other primarily dielectric substrate material, whether known at the time of filing or developed later. As discussed in more detail above, in one embodiment, seed layer  561  is applied to prepare dielectric layer  501  to receive a conductive layer. In one embodiment, seed layer  561  is a layer of metal, such as copper. In other embodiments, seed layer  561  can be any metal or other material desired, whether known at the time of filing or as developed later. In one embodiment, in-plane first bias trace  507 , in-plane first signal trace  509 , in-plane second bias trace  511 , out-of-plane first bias trace  508 , out-of-plane first signal trace  510 , and out-of-plane second bias trace  512  are made of conductive material, such as a metal. 
     As shown in  FIG. 5A , in one embodiment, in-plane first bias trace  507  includes an in-plane first bias trace first surface  523  that is substantially level with, or slightly above or below, dielectric layer first surface  503 . In one embodiment, in-plane first bias trace  507  is embedded within dielectric layer  501  of in-plane and out-of-plane embedded trace substrate  500  an in-plane first bias trace depth  541  below dielectric layer first surface  503 . In-plane first bias trace  507  includes in-plane bias trace horizontal width  515 . 
     As also shown in  FIG. 5A , in one embodiment, in-plane first signal trace  509  includes an in-plane first signal trace first surface  528  that is substantially level with, or slightly above or below, dielectric layer first surface  503 . In one embodiment, in-plane first signal trace  509  is embedded within dielectric layer  501  of in-plane and out-of-plane embedded trace substrate  500  an in-plane first signal trace depth  525  below dielectric layer first surface  503 . In-plane first signal trace  509  includes in-plane first signal trace  509  horizontal width  517   
     As shown in  FIG. 5A , in one embodiment, in-plane second bias trace  511  includes an in-plane second bias trace first surface  529  that is substantially level with, or slightly above or below, dielectric layer first surface  503 . In one embodiment, in-plane second bias trace  511  is embedded within dielectric layer  501  of in-plane and out-of-plane embedded trace substrate  500  an in-plane second bias trace depth  543  below dielectric layer first surface  503 . In-plane second bias trace  511  includes in-plane bias trace horizontal width  516 . 
     As also shown in  FIG. 5A , in one embodiment, in-plane first signal trace  509  is positioned horizontally between in-plane first bias trace  507  and in-plane second bias trace  511 . 
     Also show in  FIG. 5A  are first horizontal spacing  531  between in-plane first bias trace  507  and in-plane first signal trace  509 ; and second horizontal spacing  533  between in-plane first signal trace  509  and in-plane second bias trace  511 . As noted above, according to one embodiment, in-plane first bias trace  507 , in-plane first signal trace  509  and in-plane second bias trace  511  are formed using LASER ablation, or other ablation, techniques. Using ablation techniques to form in-plane first bias trace  507 , in-plane first signal trace  509  and in-plane second bias trace  511 , as disclosed herein, allows for very accurate control, on the order of a single micron, of first horizontal spacing  531  and second horizontal spacing  533 . Consequently, the control impedance provided by in-plane first bias trace  507  and in-plane second bias trace  511  can also be very accurately controlled; in some embodiments, to the order of a single ohm. 
     In-plane first bias trace  507 , in-plane first signal trace  509  and in-plane second bias trace  511  are similar to first bias trace  107 A, first signal trace  109 A and second bias trace  111 A of  FIG. 1A  discussed above. Consequently the discussion of the characteristics, features, advantages and formation of first bias trace  107 A, first signal trace  109 A and second bias trace  111 A of  FIG. 1A  are applicable to, and incorporated here for, in-plane first bias trace  507 , in-plane first signal trace  509  and in-plane second bias trace  511  of  FIG. 5A . 
     As also shown in  FIG. 5A , in one embodiment, out-of-plane first bias trace  508  includes an out-of-plane first bias trace first surface  524  that is an out-of-plane first bias trace height  542  above dielectric layer first surface  503 . In one embodiment, out-of-plane first bias trace  508  is in electrical contact with dielectric layer first surface  503 . Out-of-plane first bias trace  508  includes an out-of-plane first bias trace horizontal width  518 . 
     As also shown in  FIG. 5A , in one embodiment, out-of-plane first signal trace  510  includes an out-of-plane first signal trace first surface  538  that is an out-of-plane first signal trace height  526  above dielectric layer first surface  503 . In one embodiment, out-of-plane first signal trace  510  is in electrical contact with dielectric layer first surface  503 . Out-of-plane first signal trace  510  includes out-of-plane first signal trace horizontal width  520 . 
     As also shown in  FIG. 5A , in one embodiment, out-of-plane second bias trace  512  includes an out-of-plane second bias trace first surface  530  that is an out-of-plane second bias trace height  544  above dielectric layer first surface  503 . In one embodiment, out-of-plane second bias trace  512  is in electrical contact with dielectric layer first surface  503 . Out-of-plane second bias trace  512  includes an out-of-plane second bias trace horizontal width  522 . 
     As also shown in  FIG. 5A , in one embodiment, out-of-plane first signal trace  510  is positioned horizontally between out-of-plane first bias trace  508  and out-of-plane second bias trace  512 . 
     Also show in  FIG. 5A  are third horizontal spacing  532  between out-of-plane first bias trace  508  and out-of-plane first signal trace  510 ; and fourth horizontal spacing  534  between out-of-plane first signal trace  510  and out-of-plane second bias trace  512 . 
     In some instances, it is desirable to create a substrate structure wherein bias traces and signal traces are formed in and out of a given horizontal plane and two or more of the bias traces are electrically coupled.  FIG. 5B  shows a representation of a cutaway side view of an in-plane and out-of-plane embedded trace substrate  550  in accordance with the principles of one embodiment. As shown in  FIG. 5B , in-plane and out-of-plane embedded trace substrate  550  includes: dielectric layer first surface  503 B; dielectric layer second surface  505 B, opposite dielectric layer first surface  503 B; dielectric layer  501 B, positioned between dielectric layer first surface  503 B and dielectric layer second surface  505 B; in-plane first bias trace  507 B; in-plane first signal trace  509 B; in-plane second bias trace  511 B; out-of-plane first bias trace  508 B; out-of-plane first signal trace  510 B; out-of-plane second bias trace  512 B; portions of seed layer  561 B; and electrically conductive connector trace  551 . 
     In one embodiment: dielectric layer first surface  503 B; dielectric layer second surface  505 B; dielectric layer  501 B; in-plane first bias trace  507 B; in-plane first signal trace  509 B; in-plane second bias trace  511 B; out-of-plane first bias trace  508 B; out-of-plane first signal trace  510 B; portions of seed layer  561 B; and out-of-plane second bias trace  512 B of in-plane and out-of-plane embedded trace substrate  550  of  FIG. 5B  are substantially similar to: dielectric layer first surface  503 ; dielectric layer second surface  505 ; dielectric layer  501 ; in-plane first bias trace  507 ; in-plane first signal trace  509 ; in-plane second bias trace  511 ; out-of-plane first bias trace  508 ; out-of-plane first signal trace  510 ; portions of seed layer  561 ; and out-of-plane second bias trace  512  of in-plane and out-of-plane embedded trace substrate  500  of  FIG. 5A . Consequently, the discussion above with respect to: dielectric layer first surface  503 ; dielectric layer second surface  505 ; dielectric layer  501 ; in-plane first bias trace  507 ; in-plane first signal trace  509 ; in-plane second bias trace  511 ; out-of-plane first bias trace  508 ; out-of-plane first signal trace  510 ; portions of seed layer  561 ; and out-of-plane second bias trace  512  of in-plane and out-of-plane embedded trace substrate  500  of  FIG. 5A  is applicable to, and incorporated here for, similarly named and labeled elements: dielectric layer first surface  503 B; dielectric layer second surface  505 B; dielectric layer  501 B; in-plane first bias trace  507 B; in-plane first signal trace  509 B; in-plane second bias trace  511 B; out-of-plane first bias trace  508 B; out-of-plane first signal trace  510 B; portions of seed layer  561 B; and out-of-plane second bias trace  512 B of in-plane and out-of-plane embedded trace substrate  550  of  FIG. 5B . 
     In one embodiment, dielectric layer  501 B is made of any of the numerous substrate materials known to those of skill in the art such as Prepreg, or any other primarily dielectric substrate material, whether known at the time of filing or developed later. As discussed in more detail below, in one embodiment, seed layer  561 B is applied to prepare dielectric layer  50133  to receive a conductive layer. In one embodiment, seed layer  561 B is a layer of metal, such as copper. In other embodiments, seed layer  561 B can be any metal or other material desired, whether known at the time of filing or as developed later. In one embodiment, in-plane first bias trace  507 B, in-plane first signal trace  509 B, in-plane second bias trace  511 B, out-of-plane first bias trace  508 B, out-of-plane first signal trace  510 B, and out-of-plane second bias trace  512 B and electrically conductive connector trace  551  are made of conductive material, such as a metal. In one embodiment, connector trace  551  is a portion of seed layer  561 B. 
     In some instances, it is desirable to create a substrate structure wherein bias traces and signal traces are formed in and out of a given horizontal plane and one or more out-of-plane bias traces are formed directly above one or more in-plane bias traces.  FIG. 5C  shows a representation of a cutaway side view of an in-plane and out-of-plane embedded trace substrate  560  in accordance with the principles of one embodiment. As shown in  FIG. 5C , in-plane and out-of-plane embedded trace substrate  560  includes: dielectric layer first surface  503 C; dielectric layer second surface  505 C, opposite dielectric layer first surface  503 C; dielectric layer  501 C, positioned between dielectric layer first surface  503 C and dielectric layer second surface  505 C; in-plane first bias trace  507 C; in-plane first signal trace  509 C; in-plane second bias trace  511 C; out-of-plane first bias trace  508 C; out-of-plane first signal trace  510 C; out-of-plane second bias trace  512 C; out-of-plane third bias trace  563 C; out-of-plane fourth bias trace  565 C; and portions of seed layer  561 C. 
     In one embodiment: dielectric layer first surface  503 C; dielectric layer second surface  505 C; dielectric layer  501 C; in-plane first bias trace  507 C; in-plane first signal trace  509 C; in-plane second bias trace  511 C; out-of-plane first bias trace  508 C; out-of-plane first signal trace  510 C; out-of-plane second bias trace  512 C; and portions of seed layer  561 C of in-plane and out-of-plane embedded trace substrate  560  of  FIG. 5C  are substantially similar to: dielectric layer first surface  503 ; dielectric layer second surface  505 ; dielectric layer  501 ; in-plane first bias trace  507 ; in-plane first signal trace  509 ; in-plane second bias trace  511 ; out-of-plane first bias trace  508 ; out-of-plane first signal trace  510 ; out-of-plane second bias trace  512 ; and portions of seed layer  561  of in-plane and out-of-plane embedded trace substrate  500  of  FIG. 5A . Consequently, the discussion above with respect to: dielectric layer first surface  503 ; dielectric layer second surface  505 ; dielectric layer  501 ; in-plane first bias trace  507 ; in-plane first signal trace  509 ; in-plane second bias trace  511 ; out-of-plane first bias trace  508 ; out-of-plane first signal trace  510 ; out-of-plane second bias trace  512 ; and portions of seed layer  561  of in-plane and out-of-plane embedded trace substrate  500  of  FIG. 5A  is applicable to, and incorporated here for, similarly named and labeled elements: dielectric layer first surface  503 C; dielectric layer second surface  505 C; dielectric layer  501 C; in-plane first bias trace  507 C; in-plane first signal trace  509 C; in-plane second bias trace  511 C; out-of-plane first bias trace  508 C; out-of-plane first signal trace  510 C; out-of-plane second bias trace  512 C; and portions of seed layer  561 C of in-plane and out-of-plane embedded trace substrate  560  of  FIG. 5C . 
     In one embodiment, dielectric layer  501 C is made of any of the numerous substrate materials known to those of skill in the art such as Prepreg, or any other primarily dielectric substrate material, whether known at the time of filing or developed later. In one embodiment, seed layer  561 C is applied to prepare dielectric layer first surface  503 C to receive a conductive layer. In one embodiment, seed layer  561 C is a layer of metal, such as copper. In other embodiments, seed layer  561 C can be any metal or other conductive material desired, whether known at the time of filing or as developed later. In one embodiment, in-plane first bias trace  507 C, in-plane first signal trace  509 C, in-plane second bias trace  511 C, out-of-plane first bias trace  508 C, out-of-plane first signal trace  510 C, out-of-plane second bias trace  512 C, out-of-plane third bias trace  563 C, and out-of-plane fourth bias trace  565 C, are made of a conductive material, such as a metal. 
     As shown in  FIG. 5C , in-plane and out-of-plane embedded trace substrate  560  includes out-of-plane third bias trace  563 C and out-of-plane fourth bias trace  565 C. In one embodiment, out-of-plane third bias trace  563 C and out-of-plane fourth bias trace  565 C are similar to out-of-plane first bias trace  508 C and out-of-plane second bias trace  512 C. However, in one embodiment, out-of-plane third bias trace  563 C and out-of-plane fourth bias trace  565 C are formed directly over in-plane first bias trace  507 C and in-plane second bias trace  511 C, respectively, to provide further shielding for in-plane first signal trace  509 C, and, in particular, to shield out-of-plane electromagnetic field components produced by a signal on in-plane first signal trace  509 C. Consequently, out-of-plane third bias trace  563 C and out-of-plane fourth bias trace  565 C provide more complete shielding of first signal trace  509 C. 
     In one embodiment, one or more of the physical dimensions, such as width and height, of out-of-plane third bias trace  563 C and out-of-plane fourth bias trace  565 C are substantially similar to the physical dimensions of in-plane first bias trace  507 C and in-plane second bias trace  511 C and/or out-of-plane first bias trace  508 C and out-of-plane second bias trace  512 C. In other embodiments, the physical dimensions, such as width and height, of out-of-plane third bias trace  563 C and out-of-plane fourth bias trace  565 C are different, depending on the needs and desires of the user of the invention. 
     In some instances, it is desirable to create a substrate structure wherein bias traces and signal traces are formed in and out of a given horizontal plane with one or more out-of-plane bias traces formed directly above one or more in-plane bias traces and two or more of the bias traces are electrically coupled.  FIG. 5D  shows a representation of a cutaway side view of an in-plane and out-of-plane embedded trace substrate  570  in accordance with the principles of one embodiment. As shown in  FIG. 5D , in-plane and out-of-plane embedded trace substrate  570  includes: dielectric layer first surface  503 D; dielectric layer second surface  505 D, opposite dielectric layer first surface  503 D; dielectric layer  501 D, positioned between dielectric layer first surface  503 D and dielectric layer second surface  505 D; in-plane first bias trace  507 D; in-plane first signal trace  509 D; in-plane second bias trace  511 D; out-of-plane first bias trace  508 D; out-of-plane first signal trace  510 D; out-of-plane second bias trace  512 D; out-of-plane third bias trace  563 D; out-of-plane fourth bias trace  565 D; portions of seed layer  561 D; and electrically conductive connector trace  571 . 
     In one embodiment: dielectric layer first surface  503 D; dielectric layer second surface  505 D; dielectric layer  501 D; in-plane first bias trace  507 D; in-plane first signal trace  509 D; in-plane second bias trace  511 D; out-of-plane first bias trace  508 D; out-of-plane first signal trace  510 D; and out-of-plane second bias trace  512 D; and portions of seed layer  561 D of in-plane and out-of-plane embedded trace substrate  570  of  FIG. 5D  are substantially similar to: dielectric layer first surface  503 ; dielectric layer second surface  505 ; dielectric layer  501 ; in-plane first bias trace  507 ; in-plane first signal trace  509 ; in-plane second bias trace  511 ; out-of-plane first bias trace  508 ; out-of-plane first signal trace  510 ; out-of-plane second bias trace  512 ; and portions of seed layer  561  of in-plane and out-of-plane embedded trace substrate  500  of  FIG. 5A . Consequently, the discussion above with respect to: dielectric layer first surface  503 ; dielectric layer second surface  505 ; dielectric layer  501 ; in-plane first bias trace  507 ; in-plane first signal trace  509 ; in-plane second bias trace  511 ; out-of-plane first bias trace  508 ; out-of-plane first signal trace  510 ; out-of-plane second bias trace  512 ; and portions of seed layer  561  of in-plane and out-of-plane embedded trace substrate  500  of  FIG. 5A  is applicable to, and incorporated here for, similarly named and labeled elements: dielectric layer first surface  503 D; dielectric layer second surface  505 D; dielectric layer  501 D; in-plane first bias trace  507 D; in-plane first signal trace  509 D; in-plane second bias trace  511 D; out-of-plane first bias trace  508 D; out-of-plane first signal trace  510 D; out-of-plane second bias trace  512 D; and portions of seed layer  561 D of in-plane and out-of-plane embedded trace substrate  570  of  FIG. 5D . 
     In one embodiment, dielectric layer  501 D is made of any of the numerous substrate materials known to those of skill in the art such as Prepreg, or any other primarily dielectric substrate material, whether known at the time of filing or developed later. In one embodiment, seed layer  561 D is applied to prepare dielectric layer first surface  503 D to receive a conductive layer. In one embodiment, seed layer  561 D is a layer of metal, such as copper. In other embodiments, seed layer  561 D can be any metal or other conductive material desired, whether known at the time of filing or as developed later. In one embodiment, in-plane first bias trace  507 D, in-plane first signal trace  509 D, in-plane second bias trace  511 D, out-of-plane first bias trace  508 D, out-of-plane first signal trace  510 D; out-of-plane second bias trace  512 D; out-of-plane third bias trace  563 D; out-of-plane fourth bias trace  565 D; and electrically conductive connector trace  571 , are made of a conductive material, such as a metal. 
     As shown in  FIG. 5D , in-plane and out-of-plane embedded trace substrate  570  includes out-of-plane third bias trace  563 D and out-of-plane fourth bias trace  565 D. In one embodiment, out-of-plane third bias trace  563 D and out-of-plane fourth bias trace  565 D are similar to out-of-plane first bias trace  508 D and out-of-plane second bias trace  512 D. However, in one embodiment, out-of-plane third bias trace  563 D and out-of-plane fourth bias trace  565 D are formed directly over in-plane first bias trace  507 D and in-plane second bias trace  511 D, respectively, to provide further shielding for in-plane first signal trace  509 D, and, in particular, to shield out-of-plane electromagnetic field components produced by signal on in-plane first signal trace  509 D. Consequently, out-of-plane third bias trace  563 D and out-of-plane fourth bias trace  565 D provide more complete shielding of first signal trace  509 D. 
     In one embodiment, one or more of the physical dimensions, such as width and height, of out-of-plane third bias trace  563 D and out-of-plane fourth bias trace  565 D are substantially similar to the physical dimensions of in-plane first bias trace  507 D and in-plane second bias trace  511 D and/or out-of-plane first bias trace  508 D and out-of-plane second bias trace  512 D. In other embodiments, the physical dimensions, such as width and height, of out-of-plane third bias trace  563 D and out-of-plane fourth bias trace  565 D are different, depending on the needs and desires of the user of the invention. 
     As shown in  FIG. 5D , in one embodiment, in-plane and out-of-plane embedded trace substrate  570  includes conductive connector trace  571 . As shown in  FIG. 5D , in one embodiment, conductive connector trace  571  rises a height  577  above dielectric layer first surface  503 D. In some embodiments, conductive connector trace  571  is formed such that height  577  is approximately the same as the height of out-of-plane third bias trace  563 D and out-of-plane fourth bias trace  565 D. In other embodiments, height  577  of conductive connector trace  571  is formed to any specified value based on the desired electrical characteristics for, and/or provided by, conductive connector trace  571 . 
       FIGS. 6A ,  6 B,  6 C,  6 D,  6 E,  6 F,  6 G,  6 H,  6 I,  6 J,  6 K and  6 L together are a representation of some of the fabrication stages making up one embodiment of a method for creating an in-plane and out-of-plane embedded trace substrate, such as in-plane and out-of-plane embedded trace substrate  500  of  FIG. 5A . 
       FIG. 6A  shows a representation of a cutaway side view of a substrate prior to processing in accordance with the principles of one embodiment. As shown in  FIG. 6A , and as discussed above, the substrate includes dielectric layer first surface  603  and dielectric layer second surface  605 , opposite dielectric layer first surface  603 , and separated from dielectric layer first surface  603  by dielectric layer  601 . As discussed above, dielectric layer  601  is made of any of the numerous substrate materials known to those of skill in the art such as Prepreg, or any other primarily dielectric substrate material, whether known at the time of filing or as later developed. 
       FIG. 6B  shows a representation of a cutaway side view of a partially processed substrate structure after an in-plane first bias trace trench  687 , an in-plane first signal trace trench  689 , and an in-plane second bias trace trench  691  have been formed into dielectric layer  601  in accordance with the principles of one embodiment. 
     Returning to  FIG. 6B , in one embodiment, in-plane first bias trace trench  687  is formed with an in-plane first bias trace trench depth  641  into dielectric layer  601  and with an in-plane first bias trace trench horizontal width  615  at dielectric layer first surface  603 . In one embodiment, in-plane first bias trace trench  687  is created using LASER ablation or any other method for ablating, etching, scratching, digging, or otherwise forming a trench into a substrate, whether known at the time of filing or as developed later. 
     As also shown in  FIG. 6B , in one embodiment, in-plane second bias trace trench  691  is formed with an in-plane second bias trace trench depth  643  into dielectric layer  601  and with an in-plane second bias trace trench horizontal width  616  at dielectric layer first surface  603 . In one embodiment, in-plane second bias trace trench  691  is created using LASER ablation or any other method for ablating, etching, scratching, digging, or otherwise forming a trench into a substrate, whether known at the time of filing or as developed later. 
     As also shown in  FIG. 6B , in one embodiment, in-plane first signal trace trench  689  is formed with an in-plane first signal trace trench depth  625  into dielectric layer  601  and with an in-plane first signal trace trench horizontal width  617  at dielectric layer first surface  603 . In one embodiment, in-plane first signal trace trench  689  is created using LASER ablation or any other method for ablating, etching, scratching, digging, or otherwise forming a trench into a substrate, whether known at the time of filing or as developed later. 
       FIG. 6C  shows a representation of a cutaway side view of a partially processed substrate structure after a seed layer  621  has been applied to dielectric layer first surface  603  of the substrate structure of  FIG. 6B , including the surfaces of in-plane first bias trace trench  687 , in-plane first signal trench  689 , and in-plane second bias trace trench  691  in accordance with the principles of one embodiment. 
     Returning to  FIG. 6C , seed layer  621  is applied to prepare dielectric layer first surface  603  to receive a conductive layer. In one embodiment, seed layer  621  is a layer of metal, such as copper. In other embodiments, seed layer  621  can be any metal or other conductive material desired, whether known at the time of filing or as developed later. Methods, apparatuses, and structures associated with applying a seed layer, such as seed layer  621 , to a substrate are well known to those of skill in the art. Consequently, a more detailed discussion of the application of seed layers to a substrate is omitted here to avoid detracting from the invention. 
       FIG. 6D  shows a representation of a cutaway side view of a partially processed substrate structure after a layer of conductive material  623  has been applied to dielectric layer first surface  603  and seed layer  621  ( FIG. 6C ) of substrate structure of  FIG. 6C , and filled in-plane first bias trace trench  687  ( FIG. 6C ), in-plane first signal trench  689  ( FIG. 6C ), and in-plane second bias trace trench  691  ( FIG. 6C ) thereby forming an in-plane first bias trace  607  ( FIG. 6D ), an in-plane first signal trace  609  ( FIG. 6D ), and an in-plane second bias trace  611  ( FIG. 6D ) in accordance with the principles of one embodiment. 
     In one embodiment, layer of conductive material  623  is a layer of metal, such as copper. In other embodiments, layer of conductive material  623  can be any metal or other conductive material desired, whether known at the time of filing or as developed later. Methods, apparatuses, and structures associated with applying a layer of conductive material, such as layer of conductive material  623 , to a substrate, are well known to those of skill in the art. Consequently, a more detailed discussion of the application of layers of conductive material to a substrate is omitted here to avoid detracting from the invention. 
       FIG. 6E  shows a representation of a cutaway side view of a partially processed substrate structure after excess conductive material has been removed from layer of conductive material  623  of  FIG. 6D  to yield in-plane first bias trace  607 , in-plane first signal trace  609 , and in-plane second bias trace  611  in accordance with the principles of one embodiment. In one embodiment, the excess conductive material of layer of conductive material  623  of  FIG. 6D  is removed using any process for removing conductive material, such as grinding, etching, scraping or any other mechanical or chemical process, whether known at the time of filing or as developed thereafter. 
       FIG. 6F  shows a representation of a cutaway side view of a partially processed substrate structure after a layer of photo resist  627  has been applied to seed layer  621  in accordance with one embodiment. In one embodiment, layer of photo resist  627  is attached to seed layer  621  using one of various methods known to those of skill in the art such as adhesives, tapes, and static surface placement, whether known at the time of filing or as developed thereafter. In one embodiment, layer of photo resist  627  is any photo resist material and/or masking material capable of being selectively etched and/or ablated and or chemically removed. Methods, apparatuses, and structures associated with applying a layer of photo resist, such as layer of photo resist  627 , are well known to those of skill in the art. Consequently, a more detailed discussion of the application of layers of photo resist is omitted here to avoid detracting from the invention. 
       FIG. 6G  shows a representation of a cutaway side view of a partially processed substrate structure after an out-of-plane first bias trace trench  688  has been formed in photo resist layer  627  in accordance with one embodiment. As shown in  FIG. 6G , out-of-plane first bias trace trench  688  is formed in photo resist layer first surface  651  to a first bias trace trench depth  642  such that a portion of seed layer  621  forms a bottom surface  653  of out-of-plane first bias trace trench  688 . As also shown in  FIG. 6G , out-of-plane first bias trace trench  688  includes horizontal width  618  at photo resist layer first surface  651 . In one embodiment, out-of-plane first bias trace trench  688  is created as a pattern resist using methods well known to those of skill in the art. In one embodiment, out-of-plane first bias trace trench  688  is created using LASER ablation or any other method for ablating, etching, scratching, digging, or otherwise forming a trench into a photo resist layer, whether known at the time of filing or as developed later. 
     As shown in  FIG. 6G , out-of-plane second bias trace trench  692  is also formed in photo resist layer first surface  651  to an out-of-plane second bias trace trench depth  644  such that a portion of seed layer  621  forms a bottom surface  655  of out-of-plane second bias trace trench  692 . As also shown in  FIG. 6G , out-of-plane second bias trace trench  692  includes horizontal width  622  at photo resist layer first surface  651 . In one embodiment, out-of-plane second bias trace trench  692  is created as a pattern resist using methods well known to those of skill in the art. In one embodiment, out-of-plane first bias trace trench  692  is created using LASER ablation or any other method for ablating, etching, scratching, digging, or otherwise forming a trench into a photo resist layer, whether known at the time of filing or as developed later. 
       FIG. 6H  shows a representation of a cutaway side view of a partially processed substrate structure after a conductive material  657  has been plated into out-of-plane first bias trace trench  688  and out-of-plane second bias trace trench  692  of  FIG. 6G , partially filling out-of plane first bias trace trench  688  and out-of-plane second bias trace trench  692  in accordance with one embodiment. In one embodiment, conductive material  657  is copper or any other metal or conductive material, whether known at the time of filing or as developed later. In one embodiment, conductive material  657  is the same conductive material making up seed layer  621 . Methods, apparatuses, and structures associated with conductive material plating are well known to those of skill in the art. Consequently, a more detailed discussion of conductive material plating is omitted here to avoid detracting from the invention. 
       FIG. 6I  shows a representation of a cutaway side view of a partially processed substrate structure after an out-of-plane first signal trace trench  690  has been formed in photo resist layer  627  in accordance with one embodiment. As shown in  FIG. 6I , out-of-plane first signal trace trench  690  is formed in photo resist layer first surface  651  to a depth  661  such that a portion of seed layer  621  forms a second, or bottom, surface  659  of out-of-plane first signal trace trench  690 . As also shown in  FIG. 6I , out-of-plane first signal trace trench  690  includes horizontal width  620  at photo resist layer first surface  651 . In one embodiment, out-of-plane first signal trace trench  690  is created as a pattern resist using methods well known to those of skill in the art. In one embodiment, out-of-plane first signal trace trench  690  is created using LASER ablation or any other method for ablating, etching, scratching, digging, or otherwise forming a trench into a photo resist layer, whether known at the time of filing or as developed later. 
       FIG. 6J  shows a representation of a cutaway side view of a partially processed substrate structure after a layer of conductive material  665  of height  663  has been plated into out-of-plane first bias trace trench  688  ( FIG. 6I ), out-of-plane first signal trace trench  690  ( FIG. 6I ), and out-of-plane second bias trace trench  692  ( FIG. 6I ) to form an out-of-plane first bias trace  608  ( FIG. 6J ), an out-of-plane first signal trace  610  ( FIG. 6J ), and an out-of-plane second bias trace  612  ( FIG. 6J ) in accordance with the principles of one embodiment. In one embodiment, conductive material  665  is copper or any other metal or conductive material, whether known at the time of filing or is developed later. In one embodiment conductive material  665  is the same conductive material making up seed layer  621  and conductive material  657  of  FIG. 6I . Methods, apparatuses, and structures associated with conductive material plating are well known to those of skill in the art. Consequently, a more detailed discussion of conductive material plating is omitted here to avoid detracting from the invention. 
       FIG. 6K  shows a representation of a cutaway side view of a partially processed substrate structure after photo resist layer  627  of  FIG. 6J  has been removed in accordance with one embodiment by methods well know to those of skill in the art such as chemical and/or electro-magnetic energy etching, or any other methods and/or processes for removing photo resist material, whether known at the time of filing or developed thereafter. 
       FIG. 6L  shows a representation of a cutaway side view of the structure of  FIG. 6J  after excess conductive material has been removed to yield an in-plane and out-of-plane embedded trace substrate in accordance with the principles of one embodiment. 
     In other embodiments, the process discussed above with respect to  FIGS. 6A to 6L  is continued and repeated as a second dielectric layer is applied to the first dielectric layer first surface, such as dielectric layer first surface  603 , and then in-plane bias and signal traces, such as traces  607 ,  609  and  611  are then embedded in the second dielectric layer, by a process such as described above, and electrical connections are made between the first dielectric layer and the second dielectric layer using methods well known to those of skill in the art, such as blind vias or through hole vias, between the two dielectric layers. In other embodiments, out-of-plane bias and signal traces, such as traces  608 ,  610  and  612 , are then formed on the second dielectric layer, by a process such as described above. This layering of dielectric layers can be continued through as many iterations as needed to create a multilayer structure to accommodate almost any signal density desired. 
     In some embodiments, it is desirable to shape the embedded bias and/or signal traces. Since, according to one embodiment of the invention, LASER ablation is used to form the traces, there is sufficient control and accuracy to form virtually any shaped trace desired. In some instances, shaping bias and/or signal traces can help deliver optimal electrical performance and significantly reduce noise. 
       FIG. 7  shows a representation of a cutaway side view of an embedded trace substrate  700  in accordance with the principles of one embodiment. As shown in  FIG. 7 , embedded trace substrate  700  includes: dielectric layer first surface  703 ; dielectric layer second surface  705 , opposite dielectric layer first surface  703 ; dielectric layer  701 , positioned between dielectric layer first surface  703  and dielectric layer second surface  705 ; first triangular bias trace  707 ; second triangular bias trace  711 ; first signal trace  709 ; second signal trace  710 ; and portions of seed layer  761 . 
     As seen in  FIG. 7 , first triangular bias trace  707  and second triangular bias trace  711  are, as their names implies, substantially triangular in shape and are embedded in dielectric layer  701 , in one embodiment, by LASER ablation techniques. 
     In other embodiments, both the bias traces and the signal traces are shaped traces.  FIG. 8  shows a representation of a cutaway side view of an embedded trace substrate  800  in accordance with the principles of one embodiment. As shown in  FIG. 8 , embedded trace substrate  800  includes: dielectric layer first surface  803 ; dielectric layer second surface  805 , opposite dielectric layer first surface  803 ; dielectric layer  801 , positioned between dielectric layer first surface  803  and dielectric layer second surface  805 ; first trapezoidal bias trace  807 ; second trapezoidal bias trace  811 ; first rounded signal trace  809 ; and portions of seed layer  861 . 
     As seen in  FIG. 8 , first trapezoidal bias trace  807  and second trapezoidal bias trace  811  are, as their names implies, substantially trapezoidal in shape and embedded in dielectric layer  801 , in one embodiment, by LASER ablation techniques. In addition, first rounded signal trace  809  is also embedded in dielectric layer  801  and has a rounded lower surface. 
     Using LASER ablation, or other ablation techniques, virtually any shaped traces can be formed. Consequently, the specific shapes shown are for illustrative purposes only and other traces could be other shapes such as, but not limited to: square; rectangular; triangular; trapezoidal; hexagonal; semi-circular; rounded; pointed; or any other shape desired 
     This disclosure provides exemplary embodiments of the present invention. The scope of the present invention is not limited by these exemplary embodiments. Consequently, numerous variations, whether explicitly provided for by the specification or implied by the specification or not, may be implemented by one of skill in the art in view of this disclosure.