Patent Publication Number: US-2021183693-A1

Title: Rf devices with enhanced performance and methods of forming the same

Description:
RELATED APPLICATIONS 
     This application claims the benefit of provisional patent application Ser. No. 62/947,444, filed Dec. 12, 2019, the disclosure of which is hereby incorporated herein by reference in its entirety. 
    
    
     FIELD OF THE DISCLOSURE 
     The present disclosure relates to a radio frequency (RF) device and a process for making the same, and more particularly to an RF device with enhanced thermal and electrical performance, and a wafer-level fabricating and packaging process to provide the RF device with enhanced performance. 
     BACKGROUND 
     The wide utilization of cellular and wireless devices drives the rapid development of radio frequency (RF) technologies. The substrates on which RF devices are fabricated play an important role in achieving high-level performance in the RF technologies. Fabrications of the RF devices on conventional silicon substrates may benefit from the low cost of silicon materials, a large-scale capacity of wafer production, well-established semiconductor design tools, and well-established semiconductor manufacturing techniques. Despite the benefits of using conventional silicon substrates for the RF device fabrications, it is well known in the industry that the conventional silicon substrates may have two undesirable properties for the RF devices: harmonic distortion and low resistivity values. The harmonic distortion is a critical impediment to achieve high-level linearity in the RF devices built over silicon substrates. 
     In addition, high-speed and high-performance transistors are more densely integrated in RF devices. Consequently, the amount of heat generated by the RF devices increases significantly due to the large number of transistors integrated in the RF devices, the large amount of power passing through the transistors, and/or the high operation speed of the transistors. Accordingly, it is desirable to package the RF devices in a configuration for better heat dissipation. 
     Wafer-level fan-out (WLFO) technology and embedded wafer-level ball grid array (eWLB) technology currently attract substantial attention in portable RF applications. WLFO and eWLB technologies are designed to provide high-density input/output ports without increasing the size of a package. This capability allows for densely packaging the RF devices within a single wafer. 
     To enhance the operation speed and performance of the RF devices, to accommodate the increased heat generation of the RF devices, to reduce deleterious harmonic distortion of the RF devices, and to utilize advantages of WLFO/eWLB technologies, it is therefore an object of the present disclosure to provide an improved wafer-level fabricating and packaging process for the RF devices with enhanced performance. Further, there is also a need to enhance the performance of the RF devices without increasing the device size. 
     SUMMARY 
     The present disclosure relates to a radio frequency (RF) device with enhanced performance and a process for making the same. According to an exemplary process, a precursor wafer, which includes a number of device regions, a number of individual interfacial layers, and a silicon handle substrate, is first provided. Each device region includes a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion. The FEOL portion has isolation sections and an active layer, which is surrounded by the isolation sections and does not extend vertically beyond the isolation sections. Herein, each individual interfacial layer is over one active layer of a corresponding device region, and the silicon handle substrate is over each individual interfacial layer. Each individual interfacial layer is formed of silicon germanium (SiGe). Next, a first bonding layer is formed underneath the precursor wafer. After a support carrier with a second bonding layer is provided, the precursor wafer is attached to the support carrier by bonding the first bonding layer directly to the second bonding layer. Herein, the first bonding layer and the second bonding layer merge to form a bonding structure between the support carrier and the precursor wafer. The silicon handle substrate is then removed from the precursor wafer to provide an etched wafer after attaching the precursor wafer to the support carrier. A first mold compound is applied to the etched wafer to provide a mold device wafer. The first mold compound is applied at least over the active layer of each device region from where the silicon handle substrate is removed. 
     According to another embodiment, the exemplary process further includes forming a barrier layer covering an entire bottom surface of the precursor wafer before forming the first bonding layer underneath the precursor wafer. Herein, the barrier layer covers a bottom surface of the BEOL portion of each device region, and the barrier layer separates the bonding structure from the device regions. 
     In one embodiment of the exemplary process, the support carrier is formed of silicon, the bonding structure is formed of silicon oxide, and the barrier layer is formed of a nitride material. 
     According to another embodiment, the exemplary process further includes removing the support carrier from the mold device wafer after applying the first mold compound, removing the bonding structure after removing the support carrier, and removing the barrier layer after removing the bonding structure. After the removal of the support carrier, the bonding structure, and the barrier layer, the bottom surface of the BEOL portion of each device region is exposed. 
     In one embodiment of the exemplary process, the support carrier, the bonding structure, and the barrier layer have different reactions to a same etching technique. 
     In one embodiment of the exemplary process, the support carrier, the bonding structure, and the barrier layer have different etching speeds with a same etchant. 
     In one embodiment of the exemplary process, the support carrier, the bonding structure, and the barrier layer are removed by different etching processes. 
     In one embodiment of the exemplary process, the support carrier is removed by a mechanical grinding process followed by an etching process. Herein, the etching process is provided by a wet etching system with an etchant chemistry, which is at least one of tetramethylammonium hydroxide (TMAH), potassium hydroxide (KOH), sodium hydroxide (NaOH), acetylcholine (ACH), and xenon difluoride (XeF 2 ). 
     In one embodiment of the exemplary process, the support carrier is removed by a mechanical grinding process followed by an etching process. Herein, the etching process is provided by a reactive ion etching system with a chlorine-based gas chemistry or a fluorine-based gas chemistry. 
     In one embodiment of the exemplary process, the bonding structure is removed by a etch system capable of identifying the presence of the nitride material in the barrier layer. 
     In one embodiment of the exemplary process, the barrier layer is removed by a etch system capable of identifying the presence of the BEOL portion of each of the plurality of device regions. 
     According to another embodiment, the exemplary process further includes forming a multilayer redistribution structure underneath the mold device wafer after removing the support carrier, the bonding structure, and the barrier layer. Herein, the multilayer redistribution structure comprises a number of bump structures on a bottom surface of the multilayer redistribution structure and redistribution interconnections within the multilayer redistribution structure. Each bump structure is electrically coupled to one active layer of a corresponding device region via the redistribution interconnections and connecting layers within the BEOL portion of the corresponding device region. 
     In one embodiment of the exemplary process, the first bonding layer and the second bonding layer are formed of a same material. Herein, the hardness of the bonding structure does not change in a temperature range from a room temperature to 350° C. 
     According to another embodiment, the exemplary process further includes removing each individual interfacial layer from the etched wafer after removing the silicon handle substrate and before applying the first mold compound. 
     According to another embodiment, the exemplary process further includes applying a passivation layer over an entire backside of the etched wafer after removing each individual interfacial layer and before applying the first mold compound. Herein, the passivation layer is formed of silicon dioxide. The passivation layer covers at least the top surface of each active layer and the top surface of each isolation section, and the first mold compound is over the passivation layer. 
     According to another embodiment, the exemplary process further includes applying a thermally conductive film over the passivation layer before applying the first mold compound. Herein, the thermally conductive film has a thermal conductivity greater than 10 w/m·k and an electrical resistivity greater than 1E5 Ohm-cm. The thermally conductive film is formed between the passivation layer and the first mold compound. 
     In one embodiment of the exemplary process, the thermally conductive film is formed of one of silicon nitride, aluminum nitride, alumina, boron-nitride, and a diamond-based material. The thermally conductive film has a thickness between 100 Å and 50 μm. 
     In one embodiment of the exemplary process, the thermally conductive film is formed from carbon nanotube-rich layers. 
     In one embodiment of the exemplary process, silicon crystal, which has no germanium, nitrogen, or oxygen content, does not exist between the active layer of each device region and the first mold compound. The mold device wafer includes a number of mold device dies, each of which includes a corresponding device region, a portion of the passivation layer over the corresponding device region, a portion of the thermally conductive film over the portion of the passivation layer, and a portion of the first mold compound over the portion of the thermally conductive film. 
     According to another embodiment, the exemplary process further includes singulating the mold device wafer into a plurality of individual mold device dies, and applying a second mold compound around and over each individual mold device die to provide a double mold device wafer. The second mold compound encapsulates a top surface and side surfaces of each individual mold device die, while a bottom surface of each individual mold device die is exposed. A bottom surface of the double mold device wafer is a combination of the bottom surface of each individual mold device die and a bottom surface of the second mold compound. Also the exemplary process includes forming a multilayer redistribution structure underneath the double mold device wafer. Herein, the multilayer redistribution structure includes a number of bump structures on a bottom surface of the multilayer redistribution structure and redistribution interconnections within the multilayer redistribution structure. Each bump structure is electrically coupled to one active layer of a corresponding individual mold device die via the redistribution interconnections within the multilayer redistribution structure and connecting layers within the BEOL portion of the corresponding individual mold device die. 
     In one embodiment of the exemplary process, the first mold compound and the second mold compound are formed of different materials. 
     In one embodiment of the exemplary process, providing the precursor wafer starts with providing a starting wafer that includes a common silicon epitaxial layer, a common interfacial layer over the common silicon epitaxial layer, and the silicon handle substrate over the common interfacial layer. The common interfacial layer is formed of SiGe. Next, a complementary metal-oxide-semiconductor (CMOS) process is performed to the starting wafer to provide the precursor wafer. Herein, the isolation sections extend through the common silicon epitaxial layer, the common interfacial layer, and extend into the silicon handle substrate, such that the common interfacial layer is separated into a number of individual interfacial layers, and the common silicon epitaxial layer is separated into a number of individual silicon epitaxial layers. Each active layer of the device regions is formed from a corresponding individual silicon epitaxial layer. Each individual interfacial layer resides over a top surface of a corresponding active layer, and the silicon handle substrate resides over each individual interfacial layer. 
     In another aspect, any of the foregoing aspects individually or together, and/or various separate aspects and features as described herein, may be combined for additional advantage. Any of the various features and elements as disclosed herein may be combined with one or more other disclosed features and elements unless indicated to the contrary herein. 
     Those skilled in the art will appreciate the scope of the present disclosure and realize additional aspects thereof after reading the following detailed description of the preferred embodiments in association with the accompanying drawing figures. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWING FIGURES 
       The accompanying drawing figures incorporated in and forming a part of this specification illustrate several aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure. 
         FIG. 1  shows an exemplary radio frequency (RF) device with enhanced performance according to one embodiment of the present disclosure. 
         FIG. 2  shows an alternative RF device with enhanced thermal and electrical performance according to one embodiment of the present disclosure. 
         FIGS. 3-20  show an exemplary wafer-level fabricating and packaging process that illustrates steps to provide the exemplary RF device shown in  FIG. 1 . 
         FIGS. 21-26  show an alternative wafer-level fabricating and packaging process that illustrates steps to provide the alternative RF device shown in  FIG. 2 . 
     
    
    
     It will be understood that for clear illustrations,  FIGS. 1-26  may not be drawn to scale. 
     DETAILED DESCRIPTION 
     The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims. 
     It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. 
     It will be understood that when an element such as a layer, region, or substrate is referred to as being “on” or extending “onto” another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being “over” or extending “over” another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly over” or extending “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. 
     Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures. 
     The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and/or “including” when used herein specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. 
     Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. 
     Embodiments are described herein with reference to schematic illustrations of embodiments of the disclosure. As such, the actual dimensions of the layers and elements can be different, and variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are expected. For example, a region illustrated or described as square or rectangular can have rounded or curved features, and regions shown as straight lines may have some irregularity. Thus, the regions illustrated in the figures are schematic and their shapes are not intended to illustrate the precise shape of a region of a device and are not intended to limit the scope of the disclosure. Additionally, sizes of structures or regions may be exaggerated relative to other structures or regions for illustrative purposes and, thus, are provided to illustrate the general structures of the present subject matter and may or may not be drawn to scale. Common elements between figures may be shown herein with common element numbers and may not be subsequently re-described. 
     With the looming shortage of conventional radio frequency silicon-on-insulator (RFSOI) wafers expected in the coming years, alternative technologies are being devised to get around the need for high resistivity using silicon wafers, the trap-rich layer formation, and Smart-Cut SOI wafer process. One alternative technology is based on the use of a silicon germanium (SiGe) interfacial layer instead of a buried oxide layer between a silicon substrate and a silicon epitaxial layer. However, this technology still suffers from the deleterious distortion effects due to the silicon substrate, similar to what is observed in an RFSOI technology. The present disclosure, which relates to a radio frequency (RF) device with enhanced performance, and a wafer-level fabricating and packaging process for making the same, utilizes the SiGe interfacial layer without deleterious distortion effects from the silicon substrate. 
       FIG. 1  shows an exemplary RF device  10  with enhanced performance according to one embodiment of the present disclosure. For the purpose of this illustration, the exemplary RF device  10  includes a mold device die  12  that has a device region  14 , a thermally conductive film  15 , a first mold compound  16 , and a multilayer redistribution structure  18  formed under the device region  14  of the mold device die  12 . 
     In detail, the device region  14  includes a front-end-of-line (FEOL) portion  20  and a back-end-of-line (BEOL) portion  22  underneath the FEOL portion  20 . In one embodiment, the FEOL portion  20  may be configured to provide a switch field-effect transistor (FET) and includes an active layer  24  and a contact layer  26 . The active layer  24  has a source  28 , a drain  30 , and a channel  32  between the source  28  and the drain  30 . The source  28 , the drain  30 , and the channel  32  are formed from a same silicon epitaxial layer. The contact layer  26  is formed underneath the active layer  24  and includes a gate structure  34 , a source contact  36 , a drain contact  38 , and a gate contact  40 . The gate structure  34  may be formed of silicon oxide and extends horizontally underneath the channel  32  (i.e., from underneath the source  28  to underneath the drain  30 ). The source contact  36  is connected to and under the source  28 , the drain contact  38  is connected to and under the drain  30 , and the gate contact  40  is connected to and under the gate structure  34 . An insulating material  42  may be formed around the source contact  36 , the drain contact  38 , the gate structure  34 , and the gate contact  40  to electrically separate the source  28 , the drain  30 , and the gate structure  34 . In different applications, the FEOL portion  20  may have different FET configurations or provide different device components, such as a diode, a capacitor, a resistor, and/or an inductor. 
     In addition, the FEOL portion  20  also includes isolation sections  44 , which reside over the insulating material  42  of the contact layer  26  and surround the active layer  24 . The isolation sections  44  are configured to electrically separate the RF device  10 , especially the active layer  24 , from other devices formed in a common wafer (not shown). Herein, the isolation sections  44  may extend from a top surface of the contact layer  26  and vertically beyond a top surface of the active layer  24  to define an opening  46  that is within the isolation sections  44  and over the active layer  24 . The isolation sections  44  may be formed of silicon dioxide, which may be resistant to etching chemistries such as tetramethylammonium hydroxide (TMAH), xenon difluoride (XeF 2 ), potassium hydroxide (KOH), sodium hydroxide (NaOH), or acetylcholine (ACH) and may be resistant to a dry etching system, such as a reactive ion etching (RIE) system with a chlorine-based gas chemistry. 
     In some applications, the active layer  24  may be passivated to achieve proper low levels of current leakage in the device. The passivation may be accomplished with deposition of a passivation layer  48 . The passivation layer  48  extends over an entire backside of the device region  14 , such that the passivation layer  48  continuously covers exposed surfaces within the opening  46  and top surfaces of the isolation sections  44 . In one embodiment, the passivation layer  48  may only be deposited over the top surface of the active layer  24  and within the opening  46  and the isolation sections  44  not covered by the thermally conductive film  15  (not shown). The passivation layer  48  may be formed of silicon dioxide with a thickness between 10 Å and 5000 Å. 
     In some applications, the RF device  10  may further include an interfacial layer, which is formed of SiGe, over the top surface of the active layer  24  and within the opening  46  (described in the following paragraphs and not shown herein). If the passivation layer  48  and the interfacial layer exist, the interfacial layer is vertically between the active layer  24  and the passivation layer  48 . 
     The thermally conductive film  15  extends over an entire backside of the device region  14 , such that the thermally conductive film  15  continuously covers exposed surfaces within the opening  46  and top surfaces of the isolation sections  44 . If the passivation layer  48  exists, the thermally conductive film  15  resides over the passivation layer  48 . If the passivation layer  48  is omitted, the thermally conductive film  15  may be in contact with the active layer  24  of the FEOL portion  20  (not shown). Note that the thermally conductive film  15  is always adjacent to the active layer  24 . 
     The thermally conductive film  15  has a high thermal conductivity between 10 W/m·K and 3000 W/m·K, and a high electrical resistivity between 1E5 Ohm-cm and 1E12 Ohm-cm. The thermally conductive film  15  may include nitrides and or ceramics, such as silicon nitride, aluminum nitride, alumina, boron nitride, diamond-based materials, and the like. In addition, the thermally conductive film  15  may be formed from carbon nanotube-rich layers. Heat generated in the device region  14  may travel upward to an area above the active layer  24 , pass laterally in the area above the active layer  24 , and then pass downward through the device region  14  and toward the multilayer redistribution structure  18 , which dissipates the heat. It is therefore highly desirable to have a high thermal conductivity region adjacent to the active layer  24  to conduct most of the heat generated by the device region  14 . Consequently, the higher the thermal conductivity in the adjacent region above the active layer  24 , the better the heat dissipation performance of the device region  14 . Depending on different deposition stresses and different deposited materials, the thermally conductive film  15  may have different thicknesses varying from 100 Å to 50 μm. For a diamond-based material, such as chemical vapor deposition diamond, which may have an extremely high thermal conductivity between 1000 W/m·K and 3000 W/m·K, a very thin thickness of the thermally conductive film  15 , such as between 100 Å and 1000 Å, is extremely effective for the heat dissipation management of the device region  14 . In the case of aluminum nitride, the thermal conductivity is the order of 180 W/m·K and the thermally conductive film  15  may need to be relatively thick for thermal behavior enhancement, such as between 1 μm and 20 μm. In the case of silicon nitride, the thermal conductivity is between 10 W/m·K and 40 W/m·K, and the thermally conductive film  15  may have a thickness between 30 μm and 40 μm. 
     In addition, the thermally conductive film  15  may also be engineered so as to provide additional tensile strain to the active layer  24 . Such strain may be beneficial in providing additional improvement of electron mobility in n-channel devices. In some applications, the thermally conductive film  15  formed of silicon nitride may further passivate the active layer  24 . In such case, there may be no need for the passivation layer  48  described above. 
     The first mold compound  16  is directly over the thermally conductive film  15  and fills the opening  46 . Although the first mold compound  16  is not immediately above the active layer  24 , the first mold compound  16  is still close to the active layer  24 . Consequently, it is also desirable for the first mold compound  16  to have a relatively high thermal conductivity and a relatively high electrical resistivity. In this embodiment, the first mold compound  16  may have a lower thermal conductivity than the thermally conductive film  15 . The first mold compound  16  has a thermal conductivity between 1 W/m·K and 100 W/m·K, or between 7 W/m·K and 20 W/m·K. In addition, the first mold compound  16  may have a low dielectric constant less than 8, or between 3 and 5, to yield low RF coupling. 
     The first mold compound  16  may be formed of thermoplastics or thermoset polymer materials, such as polyphenylene sulfide (PPS), overmold epoxies doped with boron nitride, alumina, carbon nanotubes, or diamond-like thermal additives, or the like. A thickness of the first mold compound  16  is based on the required thermal performance of the RF device  10 , the device layout, the distance from the multilayer redistribution structure  18 , as well as the specifics of the package and assembly. The first mold compound  16  may have a thickness between 200 μm and 500 μm. Notice that, regardless of the presence of the thermally conductive film  15 , the passivation layer  48 , and/or the interfacial layer, silicon crystal, which has no germanium, nitrogen, or oxygen content, may not exist between the first mold compound  16  and the top surface of the active layer  24 . Each of the thermally conductive film  15 , the passivation layer  48 , and the interfacial layer is formed of silicon composite. 
     Further, in some applications, the top surface of each isolation section  44  and the top surface of the active layer  24  may be coplanar (not shown), and the opening  46  is omitted. The thermally conductive film  15  resides over both the active layer  24  and the isolation sections  44  of the FEOL portion  20 , and the first mold compound  16  resides over the thermally conductive film  15 . Note that the active layer  24  never extends vertically beyond the isolation sections  44 ; otherwise the isolation sections  44  may not fully separate the active layer  24  from other devices formed from the same wafer. 
     The BEOL portion  22  is underneath the FEOL portion  20  and includes multiple connecting layers  50  formed within dielectric layers  52 . Some of the connecting layers  50  (for internal connection) are encapsulated by the dielectric layers  52  (not shown), while some of the connecting layers  50  have a bottom portion not covered by the dielectric layers  52 . Certain connecting layers  50  are electrically connected to the FEOL portion  20 . For the purpose of this illustration, one of the connecting layers  50  is connected to the source contact  36 , and another connecting layer  50  is connected to the drain contact  38 . 
     The multilayer redistribution structure  18 , which is formed underneath the BEOL portion  22  of the mold device die  12 , includes a number of redistribution interconnections  54 , a dielectric pattern  56 , and a number of bump structures  58 . Herein, each redistribution interconnection  54  is connected to a corresponding connecting layer  50  within the BEOL portion  22  and extends over a bottom surface of the BEOL portion  22 . The connections between the redistribution interconnections  54  and the connecting layers  50  are solder-free. The dielectric pattern  56  is formed around and underneath each redistribution interconnection  54 . Some of the redistribution interconnections  54 , which connect the mold device die  12  to other device components formed from the same wafer, may be encapsulated by the dielectric pattern  56  (not shown), while some of the redistribution interconnections  54  have a bottom portion exposed through the dielectric pattern  56 . Each bump structure  58  is formed at a bottom surface of the multilayer redistribution structure  18  and electrically coupled to a corresponding redistribution interconnection  54  through the dielectric pattern  56 . As such, the redistribution interconnections  54  are configured to connect the bump structures  58  to certain ones of the connecting layers  50  in the BEOL portion  22 , which are electrically connected to the FEOL portion  20 . Consequently, the bump structures  58  are electrically connected to the FEOL portion  20  via corresponding redistribution interconnections  54  and corresponding connecting layers  50 . In addition, the bump structures  58  are separate from each other and protrude from the dielectric pattern  56 . 
     In some applications, there may be extra redistribution interconnections (not shown) electrically coupled to the redistribution interconnections  54  through the dielectric pattern  56 , and extra dielectric patterns (not shown) formed underneath the dielectric pattern  56 , such that a bottom portion of some extra redistribution interconnections may be exposed. Consequently, each bump structure  58  is coupled to a corresponding extra redistribution interconnection through the extra dielectric pattern (not shown). Regardless of the level numbers of the redistribution interconnections and/or the dielectric pattern, the multilayer redistribution structure  18  may be free of glass fiber or glass-free. Herein, the glass fiber refers to individual glass strands twisted to become a larger grouping. These glass strands may then be woven into a fabric. The redistribution interconnections  54  may be formed of copper or other suitable metals. The dielectric pattern  56  may be formed of benzocyclobutene (BCB), polyimide, or other dielectric materials. The bump structures  58  may be solder balls or copper pillars. The multilayer redistribution structure  18  has a thickness between 2 μm and 300 μm. 
       FIG. 2  shows an alternative RF device  10 A, which further includes a second mold compound  60  compared with the RF device  10  shown in  FIG. 1 . Herein, the multilayer redistribution structure  18  may extend horizontally beyond the mold device die  12 , and the second mold compound  60  resides over the multilayer redistribution structure  18  to encapsulate the mold device die  12 . In this embodiment, the redistribution interconnections  54  of the multilayer redistribution structure  18  may extend horizontally beyond the mold device die  12 , and the bump structures  58  of the multilayer redistribution structure  18  may not be confined within a periphery of the mold device die  12 . The second mold compound  60  may be formed of a same or a different material as the first mold compound  16 . Unlike the first mold compound  16 , the second mold compound  60  may not have thermal conductivity or dielectric constant requirements. 
       FIGS. 3-20  provide an exemplary wafer-level fabricating and packaging process that illustrates steps to fabricate the exemplary RF device  10  shown in  FIG. 1 . Although the exemplary steps are illustrated in a series, the exemplary steps are not necessarily order dependent. Some steps may be done in a different order than that presented. Further, processes within the scope of this disclosure may include fewer or more steps than those illustrated in  FIGS. 3-20 . 
     Initially, a starting wafer  62  with a Si—SiGe—Si structure is provided as illustrated in  FIG. 3 . The starting wafer  62  includes a common silicon epitaxial layer  64 , a common interfacial layer  66  over the common silicon epitaxial layer  64 , and a silicon handle substrate  68  over the common interfacial layer  66 . Herein, the common silicon epitaxial layer  64  is formed from a device-grade silicon material, which has desired silicon epitaxy characteristics to form electronic devices. The silicon handle substrate  68  may consist of conventional low-cost silicon. The common interfacial layer  66  is formed of SiGe and separates the common silicon epitaxial layer  64  from the silicon handle substrate  68 . Typically, the higher the Ge concentration, the better the etch selectivity (details are described in the following paragraphs) between the silicon handle substrate  68  and the common interfacial layer  66 , but also the more difficult the epitaxial growth of the common silicon epitaxial layer  64  becomes. In one embodiment, the common interfacial layer  66  may have a Ge concentration greater than 15% or greater than 25%. The Ge concentration may be uniform throughout the common interfacial layer  66 . In some applications, the Ge concentration may be vertically graded between 1% and 50%, for example, from the silicon handle substrate  68  to the common interfacial layer  66  with a lower concentration (0%) of Ge to a higher concentration (30%) of Ge, so as to yield the necessary strain relief for the growth of the common silicon epitaxial layer  64 . A thickness of the common silicon epitaxial layer  64  may be between 700 nm and 2000 nm, a thickness of the common interfacial layer  66  may be between 100 nm and 1000 nm, and a thickness of the silicon handle substrate  68  may be between 200 μm and 700 μm. 
     Next, a complementary metal-oxide-semiconductor (CMOS) process is performed on the starting wafer  62  to provide a precursor wafer  70  with a number of device regions  14 , as illustrated in  FIG. 4 . For the purpose of this illustration, the FEOL portion  20  of each device region  14  is configured to provide a switch FET. In different applications, the FEOL portion  20  may have different FET configurations or provide different device components, such as a diode, a capacitor, a resistor, and/or an inductor. 
     In this embodiment, the isolation sections  44  of each device region  14  extend through the common silicon epitaxial layer  64  and the common interfacial layer  66 , and extend into the silicon handle substrate  68 . As such, the common interfacial layer  66  separates into a number of individual interfacial layers  66 I, and the common silicon epitaxial layer  64  separates into a number of individual silicon epitaxial layers  64 I. Each individual silicon epitaxial layer  64 I is used to form a corresponding active layer  24  in one device region  14 . The isolation sections  44  may be formed by shallow trench isolation. 
     The top surface of the active layer  24  is in contact with a corresponding interfacial layer  66 I. The silicon handle substrate  68  resides over each individual interfacial layer  66 I, and portions of the silicon handle substrate  68  may reside over the isolation sections  44 . The BEOL portion  22  of the device region  14 , which includes at least the multiple connecting layers  50  and the dielectric layers  52 , is formed under the contact layer  26  of the FEOL portion  20 . Bottom portions of certain connecting layers  50  are exposed through the dielectric layers  52  at the bottom surface of the BEOL portion  22 . 
     In another embodiment, the isolation sections  44  do not extend into the silicon handle substrate  68 . Instead, the isolation sections  44  only extend through the common silicon epitaxial layer  64  and extend into the common interfacial layer  66  (not shown). Herein, the common interfacial layer  66  remains continuous, and the individual interfacial layers  66 I are connected with each other. The common interfacial layer  66  directly resides over the top surface of each active layer  24 , and directly resides over a top surface of each isolation section  44 . The silicon handle substrate  68  remains over the common interfacial layer  66 . Further, the isolation sections  44  may extend through the common silicon epitaxial layer  64  but do not extend into the common interfacial layer  66  (not shown). The top surface of each isolation section  44  and the top surface of each active layer  24  may be coplanar (not shown). The common interfacial layer  66  and the silicon handle substrate  68  remain intact. The common interfacial layer  66  is over each isolation section  44  and each active layer  24 , and the silicon handle substrate  68  is over the common interfacial layer  66 . 
     After the precursor wafer  70  is completed, a thin barrier layer  71  is formed to cover an entire bottom surface of the precursor wafer  70 , so as to cover the bottom surface of the BEOL portion  22  of each device region  14 , as illustrated in  FIG. 5 . Herein, the barrier layer  71  may be a nitride layer, for example, formed of silicon nitride with a thickness between 100 Å and 10000 Å,or other suitable barrier layer(s), which may have different etching reactions compared to the connecting layers  50 , the dielectric layers  52 , and oxide materials (more details are described in the following paragraphs). The barrier layer  71  may be formed by low temperature chemical vapor deposition. 
     A first bonding layer  72 A is then formed at the bottom of the precursor wafer  70  and underneath the barrier layer  71 , as illustrated in  FIG. 6 . The first bonding layer  72 A may be formed of silicon oxide and is engineered to have a proper thickness for subsequent planarization and bonding steps. For defect-free and void-free wafer slice bonding, a bottom surface of the first bonding layer  72 A at the bottom of the precursor wafer  70  may be planarized with a nanometer range flatness (not shown). Chemical mechanical polishing technology may be utilized in the planarization process. 
       FIG. 7  provides a support carrier  74  with a second bonding layer  72 B. The second bonding layer  72 B is formed over the support carrier  74  for bonding to the first bonding layer  72 A, so as to bond to the precursor wafer  70 . The second bonding layer  72 B may have a planarized top surface with a nanometer range flatness and is formed of a same material as the first bonding layer  72 A, such as silicon oxide. The support carrier  74  may be a thick silicon wafer from a cost and thermal expansion point of view but may also be constructed of glass, sapphire, or any other suitable carrier material, which is configured to provide mechanical support to the precursor wafer  70 . 
     A bonding step is then applied to attach the precursor wafer  70  to the support carrier  74  by bonding the first bonding layer  72 A directly to the second bonding layer  72 B, as illustrated in  FIG. 8 . The precursor wafer  70  is placed over the support carrier  74 , where the planarized bottom surface of the first bonding layer  72 A directly connects the planarized top surface of the second bonding layer  72 B. The first bonding layer  72 A and the second bonding layer  72 B merge to form a bonding structure  72 . Notice that, the bonding structure  72  used between the precursor wafer  70  and the support carrier  74  does not contain any polymer components such as a polymer adhesive, which may become less rigid during some of the processing temperatures required in the following fabricating and packaging steps. The bonding structure  72  and the support carrier  74  form a superior rigid structure, which does not soften in the temperature ranges between room temperature and 350° C. and provides a solid mechanical support during the following etching/molding steps. Different methods may be utilized to implement the bonding step, such as a low-temperature oxide-oxide plasma bonding technology. 
     Next, the silicon handle substrate  68  is selectively removed to provide an etched wafer  76 , as illustrated in  FIG. 9 . The selective removal may be stopped at or into each interfacial layer  66 I. Removing the silicon handle substrate  68  may be provided by chemical mechanical grinding and an etching process or may be provided by the etching process itself. As an example, the silicon handle substrate  68  may be ground to a thinner thickness to reduce the subsequent etching time. An etching process is then performed to remove the remaining silicon handle substrate  68 . Since the silicon handle substrate  68  and the individual interfacial layers  66 I have different characteristics, they may have different reactions to a same etching technique, for instance, different etching speeds with a same etchant. Consequently, the etching system is capable of identifying the presence of the individual interfacial layers  66 I (presence of Ge) and is capable of indicating when to stop the etching process. 
     Typically, the higher the germanium concentration, the better the etching selectivity between the silicon handle substrate  68  and the individual interfacial layers  66 I. The etching process may be provided by a wet etching system with an etchant chemistry, which is at least one of TMAH, KOH, NaOH, ACH, and XeF2, or a dry etching system, such as a reactive ion etching system with a chlorine-based gas chemistry or a fluorine-based gas chemistry. 
     During the removal process, the isolation sections  44  are not removed and protect sides of each active layer  24 . If the isolation sections  44  extend vertically beyond the individual interfacial layers  66 I, the removal of the silicon handle substrate  68  provides the opening  46  over each individual interfacial layer  66 I (over each active layer  24 ) and within the isolation sections  44 . Herein, the top surface of each isolation section  44  and a top surface of each individual interfacial layer  66 I are exposed after the removal step of the silicon handle substrate  68 . If the isolation sections  44  only extend into the common interfacial layer  66  but not through the common interfacial layer  66  (as shown in  FIG. 4B ), or the top surface of each isolation section  44  and the top surface of each active layer  24  are coplanar (not shown), only the top surface of the common interfacial layer  66  is exposed (not shown) after the removal of the silicon handle substrate  68 . The support carrier  74  and the bonding structure  72  protect the bottom surface of each BEOL portion  22 . 
     Due to the narrow gap nature of the SiGe material, it is possible that the individual interfacial layers  66 I (or the common interfacial layer  66 ) may be conducting. The individual interfacial layers  66 I may cause appreciable leakage between the source  28  and the drain  30  of the active layer  24 . Therefore, in some applications, such as FET applications, it is desired to also remove the individual interfacial layers  66 I (or the common interfacial layer  66 ), as illustrated in  FIG. 10 . Each active layer  24  is exposed, at a bottom of a corresponding opening  46  if there is one opening  46  over each active layer  24 . If the individual interfacial layer  66 I is thin enough, it may be completely depleted and may not cause any appreciable leakage between the source  28  and the drain  30  of the FEOL portion  20 . In that case, the individual interfacial layers  66 I may be left intact. Herein, the individual interfacial layers  66 I may be removed by the same etching process used to remove the silicon handle substrate  68  or may be removed by another etching process, such as hydrogen chloride (HCl) dry etch systems. 
     In some applications, after the removal of the silicon handle substrate  68  and the individual interfacial layers  66 I, the active layer  24  may be passivated to achieve proper low levels of current leakage in the device. The passivation layer  48  may be formed directly over the FEOL portion  20  of each device region  14 , as illustrated in  FIG. 11 . Herein, the passivation layer  48  may extend over an entire backside of the etched wafer  76 , such that the passivation layer  48  continuously covers exposed surfaces within each opening  46  and top surfaces of the isolation sections  44 . In some applications, the passivation layer  48  may only cover the top surface of each active layer  24  within the corresponding opening  46  (not shown). The passivation layer  48  may be formed of silicon dioxide by a plasma enhanced deposition process, an anodic oxidation process, an ozone-based oxidation process, and a number of other proper techniques. 
     The thermally conductive film  15  is then applied over the passivation layer  48 , as illustrated in  FIG. 12 . If the passivation layer  48  does not exist, the thermally conductive film  15  is formed directly over the FEOL portion  20  of each device region  14 , such that the thermally conductive film  15  continuously covers exposed surfaces within each opening  46  and top surfaces of the isolation sections  44  (not shown). Notice that, regardless of the presence of the passivation layer  48  or the individual interfacial layer  66 I, the thermally conductive film  15  always resides over the top surface of each active layer  24 . 
     Herein, the thermally conductive film  15  has a high thermal conductivity between 10 W/m·K and 3000 W/m·K and a high electrical resistivity between 1E5 Ohm-cm and 1E12 Ohm-cm. The thermally conductive film  15  may include nitrides and or ceramics, such as silicon nitride, aluminum nitride, alumina, boron nitride, diamond-based materials, and the like. In addition, the thermally conductive film  15  may be formed from carbon nanotube-rich layers. 
     Heat generated in the device regions  14  may travel upward to an area above each active layer  24 , pass laterally in the area above each active layer  24 , and then pass downward through the device regions  14  (toward the multilayer redistribution structure  18  formed later). It is therefore highly desirable to have a high thermal conductivity region adjacent to each active layer  24  to conduct most of the heat generated by the device regions  14 . Consequently, the higher the thermal conductivity in the adjacent region above each active layer  24 , the better the heat dissipation performance of the device regions  14 . Depending on different deposition stresses and different deposited materials, the thermally conductive film  15  may have different thicknesses varying from 100 Å to 50 μm. For a diamond-based material, which has an extremely high thermal conductivity between 1000 W/m·K and 3000 W/m·K, a very thin thickness of the thermally conductive film  15 , such as between 100 Å and 1000 Å, is extremely effective for the heat dissipation management of the device regions  14 . In the case of aluminum nitride, the thermal conductivity is on the order of 180 W/m·K and the thermally conductive film  15  may need to be relatively thick for thermal behavior enhancement, such as between 1 μm and 20 μm. In the case of silicon nitride, the thermal conductivity is between 10 W/m·K and 40 W/m·K, and the thermally conductive film  15  may have a thickness between 30 μm and 40 μm. The thermally conductive film  15  may be formed by a chemical vapor deposition process, such as plasma enhanced chemical vapor deposition (PECVD) or atomic layer deposition (ALD), such as a PEALD system. 
     Next, the first mold compound  16  is applied over thermally conductive film  15  to provide a mold device wafer  78 , as illustrated in  FIG. 13 . The mold device wafer  78  includes a number of the mold device dies  12 , each of which includes the device region  14 , a portion of the passivation layer  48 , a portion of the thermally conductive film  15 , and a portion of the first mold compound  16 . Herein, the first mold compound  16  fills each opening  46  and fully covers the thermally conductive film  15 . In addition, portions of the first mold compound  16  may extend over the isolation sections  44 . Notice that, regardless of the presence of the thermally conductive film  15 , the passivation layer  48 , or the individual interfacial layer  66 I, silicon crystal, which has no germanium, nitrogen, or oxygen content, may not exist between the first mold compound  16  and the top surface of each active layer  24 . The thermally conductive film  15 , the passivation layer  48 , and the individual interfacial layer  66 I are silicon composite. 
     The first mold compound  16  may be applied by various procedures, such as compression molding, sheet molding, overmolding, transfer molding, dam fill encapsulation, and screen print encapsulation. Although the first mold compound  16  is not immediately above the active layer  24 , the first mold compound  16  is still close to the active layer  24 . Consequently, it is also desirable for the first mold compound  16  to have a relatively high thermal conductivity and a relatively high electrical resistivity. In one embodiment, the first mold compound  16  may have a lower thermal conductivity than the thermally conductive film  15 . The first mold compound  16  has a thermal conductivity between 1 W/m·K and 100 W/m·K, or between 7 W/m·K and 20 W/m·K. In addition, the first mold compound  16  may have a low dielectric constant less than 8, or between 3 and 5, to yield low RF coupling. 
     During the molding process of the first mold compound  16 , the bonding structure  72  and the support carrier  74  provide mechanical strength and rigidity to the etched wafer  76 . Unlike the polymer adhesive used for carrier attaching, the bonding structure  72  does not soften with temperature variation (between the room temperature and 350° C.), such that the bonding structure  72  and the support carrier  74  provide mechanical strength and rigidity to the etched wafer  76 . A curing process (not shown) is followed to harden the first mold compound  16 . The curing temperature is between 100° C. and 320° C. depending on which material is used as the first mold compound  16 . After the curing process, the first mold compound  16  may be thinned and/or planarized (not shown). 
     After the mold device wafer  78  is formed, the support carrier  74 , the bonding structure  72 , and the barrier layer  71  are removed in sequence, as illustrated in  FIGS. 14-16 . As shown in  FIG. 14 , the support carrier  74  is selectively removed first. Removing the support carrier  74  may be provided by a mechanical grinding process and an etching process or provided by the etching system itself. As an example, the support carrier  74  may be ground to a thinner thickness to reduce the subsequent etching time. An etching process is then performed to completely remove the support carrier  74 . Herein, the bonding structure  72  and the support carrier  74  are formed of different materials (the bonding structure  72  formed of silicon oxide, and the support carrier  74  formed of silicon), such that the support carrier  74  and the bonding structure  72  have different reactions to a same etching technique, for instance, different etching speeds with a same etchant. During the etching process for the support carrier  74 , the etching system may be capable of identifying the presence of the bonding structure  72  and and may be capable of indicating when to stop the etching process for the support carrier  74 . Consequently, the selective removal of the support carrier  74  can be stopped on or into the bonding structure  72 . The bonding structure  72  is configured to be an etching stop for the removal of the support carrier  74 . The etching process may be provided by a wet etching system with an etchant chemistry, which is at least one of TMAH, KOH, NaOH, ACH, and XeF2, or a dry etching system, such as a reactive ion etching system with a chlorine-based gas chemistry or a fluorine-based gas chemistry. 
     The bonding structure  72  is then selectively removed, as illustrated in 
       FIG. 15 . Herein, the bonding structure  72  and the barrier layer  71  are formed of different materials (the bonding structure  72  formed of silicon oxide, and the barrier layer  71  formed of a nitride material), such that the barrier layer  71  and the bonding structure  72  have different reactions to a same etching technique, for instance, different etching speeds with a same etchant. During the etching process for the bonding structure  72 , the etching system may be capable of identifying the presence of the barrier layer  71  and may be capable of indicating when to stop the etching process for the bonding structure  72 . Consequently, the selective removal of the bonding structure  72  can be stopped on the barrier layer  71 . The barrier layer  71  is configured to be an etching stop for the removal of the bonding structure  72 . The etching process may be provided by a wet etching system with an etchant chemistry, which is at least one of TMAH, KOH, NaOH, ACH, and XeF2, or a dry etching system, such as a reactive ion etching system with a chlorine-based gas chemistry or a fluorine-based gas chemistry. 
     Next, the barrier layer  71  is selectively removed, as illustrated in  FIG. 16 . Herein, the barrier layer  71 , the dielectric layers  52  of each BEOL portion  22 , and the connecting layers  50  of each BEOL portion  22  are formed of different materials, such that the barrier layer  71 , the dielectric layers  52 , and the connecting layers  50  may have different reactions to a same etching technique, for instance, different etching speeds and selectivity with a same etchant. During the etching process for the barrier layer  71 , the etching system may be capable of identifying the presence of the dielectric layers  52  and/or the connecting layers  50  and may be capable of indicating when to stop the etching process for the barrier layer  71  without damaging the dielectric layers  52  and the connecting layers  50 . Consequently, the selective removal of the barrier layer  71  can be at least stopped on the dielectric layers  52  and on the bottom portions of certain ones of the connecting layers  50  that are not covered by the dielectric layers  52 . After the removal of the barrier layer  71 , the bottom portions of certain ones of the connecting layers  50 , which may function as input/output (I/O) ports of each mold device die  12 , are exposed through the dielectric layers  52  at the bottom surface of each BEOL portion  22 . As such, each mold device die  12  in the mold device wafer  78  may be electrically verified to be working properly at this point. 
     With reference to  FIGS. 17 through 19 , the multilayer redistribution structure  18  is formed underneath the mold device wafer  78  according to one embodiment of the present disclosure. Although the redistribution steps are illustrated in a series, the redistribution steps are not necessarily order dependent. Some steps may be done in a different order than that presented. Further, redistribution steps within the scope of this disclosure may include fewer or more steps than those illustrated in  FIGS. 17-19 . 
     A number of the redistribution interconnections  54  are first formed underneath each BEOL portion  22 , as illustrated in  FIG. 17 . Each redistribution interconnection  54  is electrically coupled to the exposed bottom portion of the corresponding connecting layer  50  within the BEOL portion  22  and may extend over the bottom surface of the BEOL portion  22 . The connections between the redistribution interconnections  54  and the connecting layers  50  are solder-free. The dielectric pattern  56  is then formed underneath each BEOL portion  22  to partially encapsulate each redistribution interconnection  54 , as illustrated in  FIG. 18 . As such, the bottom portion of each redistribution interconnection  54  is exposed through the dielectric pattern  56 . In different applications, there may be extra redistribution interconnections (not shown) electrically coupled to the redistribution interconnection  54  through the dielectric pattern  56 , and extra dielectric patterns (not shown) formed underneath the dielectric pattern  56 , such that a bottom portion of each extra redistribution interconnection is exposed. 
     Next, a number of the bump structures  58  are formed to complete the multilayer redistribution structure  18  and provide a wafer-level fan-out (WLFO) package  80 , as illustrated in  FIG. 19 . Each bump structure  58  is formed at the bottom of the multilayer redistribution structure  18  and electrically coupled to an exposed bottom portion of the corresponding redistribution interconnection  54  through the dielectric pattern  56 . Consequently, the redistribution interconnections  54  are configured to connect the bump structures  58  to certain ones of the connecting layer  50  in the BEOL portion  22 , which are electrically connected to the FEOL portion  20 . As such, the bump structures  58  are electrically connected to the FEOL portion  20  via corresponding redistribution interconnections  54  and corresponding connecting layers  50 . In addition, the bump structures  58  are separate from each other and extend underneath the dielectric pattern  56 . 
     The multilayer redistribution structure  18  may be free of glass fiber or glass-free. Herein, the glass fiber refers to individual glass strands twisted to become a larger grouping. These glass strands may then be woven into a fabric. The redistribution interconnections  54  may be formed of copper or other suitable metals, the dielectric pattern  56  may be formed of BCB, polyimide, or other dielectric materials, and the bump structures  58  may be solder balls or copper pillars. The multilayer redistribution structure  18  has a thickness between 2 μm and 300 μm.  FIG. 20  shows a final step to singulate the WLFO package  80  into individual RF devices  10 . The singulating step may be provided by a probing and dicing process at certain isolation sections  44 . 
     In another embodiment,  FIGS. 21-26  provide an alternative process that illustrates steps to fabricate the alternative RF device  10 A shown in  FIG. 2 . Although the exemplary steps are illustrated in a series, the exemplary steps are not necessarily order dependent. Some steps may be done in a different order than that presented. Further, processes within the scope of this disclosure may include fewer or more steps than those illustrated in  FIGS. 21-26 . 
     After the removal of the support carrier  74 , the bonding structure  72 , and the thin barrier layer  71  to provide the clean mold device wafer  78  as shown in  FIG. 16 , a singulating step is followed to singulate the mold device wafer  78  into individual mold device dies  12 , as illustrated in  FIG. 21 . This singulating step may be provided by a probing and dicing process at certain isolation sections  44 . Herein, each mold device die  12  may have a same height and includes the device region  14  with the FEOL portion  20  and the BEOL portion  22 , the passivation layer  48 , the thermally conductive film  15 , and the first mold compound  16 . 
     Next, the second mold compound  60  is applied around and over the mold device dies  12  to provide a double mold device wafer  82 , as illustrated in  FIG. 22 . The second mold compound  60  encapsulates a top surface and side surfaces of each mold device die  12 , while a bottom surface of each mold device die  12 , which is the bottom surface of the BEOL portion  22 , is exposed. A bottom surface of the double mold device wafer  82  is a combination of the bottom surface of each mold device die  12  and a bottom surface of the second mold compound  60 . Herein, the bottom portions of certain ones of the connecting layers  50  remain exposed at the bottom surface of each mold device die  12 . The second mold compound  60  may be applied by various procedures, such as sheet molding, overmolding, compression molding, transfer molding, dam fill encapsulation, or screen print encapsulation. The second mold compound  60  may be formed of the same or different material as the first mold compound  16 . However, unlike the first mold compound  16 , the second mold compound  60  does not have thermal conductivity or electrical resistivity requirements. The second mold compound  60  may be an organic epoxy resin system or the like. A curing process (not shown) is then used to harden the second mold compound  60 . The curing temperature is between 100° C. and 320° C. depending on which material is used as the second mold compound  60 . A grinding process (not shown) may be followed to provide a planarized top surface of the second mold compound  60 . 
     With reference to  FIGS. 23 through 25 , the multilayer redistribution structure  18  is formed according to one embodiment of the present disclosure. Although the redistribution steps are illustrated in a series, the redistribution steps are not necessarily order dependent. Some steps may be done in a different order than that presented. Further, redistribution steps within the scope of this disclosure may include fewer or more steps than those illustrated in  FIGS. 23-25 . 
     A number of the redistribution interconnections  54  are first formed underneath the double mold device wafer  82 , as illustrated in  FIG. 23 . Each redistribution interconnection  54  is electrically coupled to the corresponding connecting layer  50  within the BEOL portion  22  and may extend horizontally beyond the corresponding mold device die  12  and underneath the second mold compound  60 . The connections between the redistribution interconnections  54  and the connecting layers  50  are solder-free. The dielectric pattern  56  is then formed underneath the double mold device wafer  82  to partially encapsulate each redistribution interconnection  54 , as illustrated in  FIG. 24 . As such, the bottom portion of each redistribution interconnection  54  is exposed through the dielectric pattern  56 . In different applications, there may be extra redistribution interconnections (not shown) electrically coupled to the redistribution interconnection  54  through the dielectric pattern  56 , and extra dielectric patterns (not shown) formed underneath the dielectric pattern  56 , such that a bottom portion of each extra redistribution interconnection is exposed. 
     Next, a number of the bump structures  58  are formed to complete the multilayer redistribution structure  18  and provide an alternative WLFO package  80 A, as illustrated in  FIG. 25 . Each bump structure  58  is formed at the bottom of the multilayer redistribution structure  18  and electrically coupled to an exposed bottom portion of the corresponding redistribution interconnection  54  through the dielectric pattern  56 . Consequently, the redistribution interconnections  54  are configured to connect the bump structures  58  to certain ones of the connecting layer  50  in the BEOL portion  22 , which are electrically connected to the FEOL portion  20 . As such, the bump structures  58  are electrically connected to the FEOL portion  20  via corresponding redistribution interconnections  54  and corresponding connecting layers  50 . Herein, the bump structures  58  may not be confined within a periphery of a corresponding mold device die  12 . In addition, the bump structures  58  are separate from each other and extend underneath the dielectric pattern  56 . 
       FIG. 26  shows a final step to singulate the alternative WLFO package  80 A into individual alternative RF devices  10 A. The singulating step may be provided by a probing and dicing process at portions of the second mold compound  60 , which are horizontally between adjacent mold device dies  12 . 
     It is contemplated that any of the foregoing aspects, and/or various separate aspects and features as described herein, may be combined for additional advantage. Any of the various embodiments as disclosed herein may be combined with one or more other disclosed embodiments unless indicated to the contrary herein. 
     Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.