Patent Publication Number: US-8112613-B2

Title: Selecting broadcast SIMD instruction or cached MIMD instruction stored in local memory of one of plurality of processing elements for all elements in each unit

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     The present application is a divisional application of U.S. Ser. No. 12/917,918 filed Nov. 2, 2010, which is a divisional of Ser. No. 12/162,551 filed on Jul. 29, 2008, now U.S. Pat. No. 7,853,775 granted Dec. 14, 2010, which is a &#39;371 filing of PCT/JP2007/065620 filed on Aug. 9, 2007 and is based on Convention rights pertaining to JP Patent Application No. 2006-225963 filed on Aug. 23, 2006. The entire disclosures of each of which are incorporated herein by reference thereto. 
    
    
     TECHNICAL FIELD 
     The present invention relates to processing elements, a mixed mode parallel processor system, a processing method by processing elements, a mixed mode parallel processor method, a processor program by processing elements and a mixed mode parallel processor program. More particularly, it relates to processing elements, a mixed mode parallel processor system, a processing method by processing elements, a mixed mode parallel processor method, a processor program by processing elements and a mixed mode parallel processor program of higher efficiency. 
     BACKGROUND ART 
     There has so far been proposed a parallel processor of the so-called SIMD (Single Instruction Multiple Data) system, in which larger numbers of processors or processing elements (PEs) or arithmetic/logic units are operated in parallel in accordance with a common instruction stream. There has also been proposed a parallel processor of the so-called MIMD (Multiple Instruction Multiple Data) system, in which a plurality of instruction streams are used to operate a plurality of processors or processing units (PUs) or a plurality of arithmetic/logic units with a plurality of instruction streams. 
     With the parallel processor of the SIMD system, it is sufficient to generate the same single instruction stream for a larger number of PEs, and hence it is sufficient to provide a single instruction cache for generating the instruction stream and a single sequence control circuit for implementing conditional branching. Thus, the parallel processor of the SIMD system has a merit that it has higher performance for a smaller number of control circuits and for a smaller circuit scale, and another merit that, since the operations of the PEs are synchronized with one another at all times, data may be exchanged highly efficiently between the arithmetic/logic units. However, the parallel processor of the SIMD system has a disadvantage that, since there is only one instruction stream, the range of problems that may be tackled with is necessarily restricted. 
     Conversely, the parallel processor of the MIMD system has a merit that, since a larger number of instruction streams may be maintained simultaneously, an effective range of problems to which the system can be applied is broad. There is however a deficiency proper to the parallel processor of the MIMD system that it is in need of the same number of control circuits as the number of the PEs and hence is increased in circuit scale. 
     There is also proposed an arrangement of a so-called ‘mixed mode’ parallel processor aimed to achieve the merits of both the SIMD and MIMD systems in such a manner as to enable dynamic switching between SIMD and MIMD systems within the same processor. 
     For example, there is also disclosed a system in which each processing element (PE) is configured to have a pair of a control circuit and PE so as to enable operation in MIMD mode from the outset and in which all PEs select and execute instruction stream, broadcast over an external instruction bus, in a SIMD mode, while selecting and executing a local instruction stream in a SIMD mode, thereby enabling dynamic switching between a SIMD mode and a MIMD mode (Patent Documents 1 to 4).
     [Patent Document  1 ] JP Patent Kokai Publication No. JP-A59-16071   [Patent Document 2] JP Patent Kokai Publication No. JP-A5-20283   [Patent Document 3] JP Patent No. 2647315   [Patent Document 4] JP Patent No. 3199205   

     DISCLOSURE OF THE INVENTION 
     Problems to be Solved by the Invention 
     It is assumed that the disclosures of the Patent Documents 1 to 4 are incorporated herein by reference. The following analysis has been given by the present invention. 
     The principal object of the above-described conventional MIMD system based mixed mode parallel processor is to enable highly efficient data exchange between PEs to advantage by switching to a SIMD mode. 
     However, from the comparison of the conventional mixed mode parallel processor and a parallel processor, which is based solely on a simple SIMD system, and which has a number of PEs equal to that of the conventional mixed mode parallel processor, the numbers of the instruction cache memories or related control circuits, indispensable to deliver an instruction stream to each processing element, especially, an instruction cache memory and register resources for tag storage of an instruction cache, needed in the former processor, are each equal to the number of processing elements. Thus, the number of the processing elements that can be integrated in a circuit chip in the former processor is about one half or less of that in the latter, generally, if the two processors have the same circuit scale. That is, the processing performance of the former processor is decreased to one half or less of that of the latter. 
     In light of the above, whether or not the conventional mixed mode parallel processor is really more effective than a simple SIMD processor depends appreciably on the proportions of SIMD processing and MIMD processing in an application where SIMD processing and MIMD processing are present together. That is, the conventional mixed mode parallel processor suffers a problem that the higher the proportion of SIMD processing, the lower becomes the efficacy of the mixed mode parallel processor. 
     It is an object of the present invention to provide a processing element, a mixed mode parallel processor system, a processing method, a mixed mode parallel processor method, a processor program and a mixed mode parallel processor program in which the circuit scale is not increased appreciably and the performance in SIMD processing is not lowered, as compared with that of a simple SIMD processor having the same number of processing elements. 
     Means to Solve the Problems 
     A processing element according to the present invention includes means for performing parallel operations with other N−1 number of processing elements in SIMD operation and for performing parallel operations with other S (=N÷M)−1 number (where S and M are natural numbers not smaller than 2) of processing elements in MIMD operation. 
     A first mixed mode parallel processor system according to the present invention comprises: N number of processing elements that perform parallel operations in SIMD operation. The N number of processing elements are grouped into M (=N÷S) sets (where S and M are natural numbers not smaller than 2) of processing units, in MIMD operation, each of the M sets including S number of processing elements. In MIMD operation, the M sets of processing units perform parallel operations, each other, while S number of the processing elements also perform parallel operations, each other. 
     The second mixed mode parallel processor system according to the present invention is configured, based on the above first mixed mode parallel processor system in such a manner that in MIMD operation, part of memory resources of the processing unit operates as an instruction cache memory, and general-purpose register resources of the processing units operate as a tag storage area of the instruction cache. 
     The third mixed mode parallel processor system according to the present invention is configured based on the above second mixed mode parallel processor system in such a manner that the processing unit includes a control circuit that performs instruction cache control and instruction sequence control. 
     The fourth mixed mode parallel processor system according to the present invention is configured based on the above second or third mixed mode parallel processor system in such a manner that in MIMD operation, P (P&lt;S) out of S number of the memory resources belonging to S number of the processing elements in each of the M sets of processing units operate as instruction cache memories, with the remaining S−P memory resources operating as data memories or as data cache memories. One set of S sets of the general-purpose register resources, belonging to S number of the processing elements, directly operates as the general-purpose register resources of the sole processing unit. T set (T&lt;S−1) or a predetermined constant number out of the remaining S−1 sets, operate as tag storage resources of an instruction cache, with the remaining sets operating as tag storage resources for a data cache in case of using the data cache. 
     The fifth mixed mode parallel processor system according the present invention is configured based on the above second, third or fourth mixed mode parallel processor system in which there is included a control processing element for performing system control. One of the processing elements in each processing unit, including the instruction cache memory, includes the control circuit and an instruction stream selector that selects an instruction from the control processing element or an instruction from the instruction cache memory. In MIMD operation, the remaining processing elements not including the instruction cache memory receive and execute the instruction from the instruction stream selector. 
     The sixth mixed mode parallel processor system according to the present invention is configured based on the above second mixed mode parallel processor system in such a manner that there is included a control processing element for performing a system control. Each of S number of the processing elements in each of the processing units includes the control circuit and an instruction stream selector. In MIMD operation, the instruction stream selector of one of the processing elements, including the instruction cache memory, out of the processing elements, selects an instruction from the control processing element or an instruction from the instruction cache memory. The remaining processing elements, not including the instruction cache memory, receive and execute the instruction from the instruction stream selector of the sole processing element including the instruction cache memory. 
     A processing method by processing elements according to the present invention includes a step of allowing one of N number of processing elements to perform parallel operations with other (N−1) processing elements in SIMD operation, and a step of allowing one of S of the processing elements to perform parallel operations with other S (=N÷M)−1 processing elements, where S and M are natural numbers not smaller than 2. 
     A first mixed mode parallel processor method according to the present invention is a mixed mode parallel processor method for a mixed mode parallel processor system including N number of processing elements, which N number of processing elements are grouped in MIMD operation into M (=N÷S) sets of processing units, each set including S number of processing elements, where S and M are natural numbers not smaller than 2. The first mixed mode parallel processor method comprises a step of allowing N number of the processing elements to perform parallel operations, in SIMD operation, a step of allowing the M sets of the processing units to perform parallel operations and a step of allowing S number of the processing elements to perform parallel operations in MIMD operation. 
     The second mixed mode parallel processor method according to the present invention comprises a step of allowing part of memory resources of the processing units to operate as an instruction cache memory, in MIMD operation, and a step of allowing general-purpose register resources of the processing units to operate as a tag storage area of the instruction cache. 
     The third mixed mode parallel processor method according to the present invention is the above second mixed mode parallel processor method in which a sole control circuit in the processing unit manages a step of performing instruction cache control and instruction sequence control. 
     The fourth mixed mode parallel processor method according to the present invention is the above second or third mixed mode parallel processor method in which, during the MIMD operation, each of the M sets of the processing units manages a step of allowing P out of S memory resources belonging to S number of the processing elements, where P&lt;S, to operate as instruction cache memories, and allowing the remaining S−P memory resources to operate as data memories or as data cache memories, a step of allowing one of S sets of the general-purpose register resources, belonging to S number of the processing elements, to directly operate as the general-purpose register resources of the processing unit, and a step of allowing T or a predetermined constant number of sets out of the remaining S−1 sets, where T&lt;S−1, to operate as tag storage resources for instruction cache, and allowing the remaining sets to operate as data cache tag storage resources in case of using a data cache. 
     The fifth mixed mode parallel processor method according to the present invention is the above second, third or fourth mixed mode parallel processor method for the mixed mode parallel processing including the control processing element for global control. The present mixed mode parallel processor method comprises a step of the instruction stream selector of the sole processing element in the processing unit, including the instruction cache memory, selecting an instruction from the control processing element for global control or an instruction from the instruction cache memory, and a step of the remaining processing elements, not including the instruction cache memory, receiving and executing the instruction from the instruction stream selector during the MIMD operation. 
     The sixth mixed mode parallel processor method according to the present invention is the above second mixed mode parallel processor method for the mixed mode parallel processing including the control processing element for global control. The present mixed mode parallel processor method comprises a step of the instruction stream selector of the sole processing element in the processing unit, including the instruction cache memory, selecting an instruction from the control processing element for global control or an instruction from the instruction cache memory, during the MIMD operation, and a step of the remaining processing elements, not including the instruction cache memory, receiving and executing the instruction from the instruction stream selector of the sole processing element including the instruction cache memory. 
     A program for processing according to the present invention comprises a step of allowing one of the processing elements to perform parallel operations, in SIMD operation, with other (N−1) processing elements, and a step of allowing one of S of the processing elements to perform parallel operations, in MIMD operation, with other S (=N÷M)−1 processing elements, where S and M are natural numbers not smaller than 2. 
     A first mixed mode parallel processor program for a mixed mode parallel processor system, which system includes N number of processing elements grouped into M (=N÷S) sets of processing units in MIMD operation, where S and M are natural numbers not smaller than 2. Each of the M sets includes S number of processing elements. The program allows the mixed mode parallel processor system to execute a step of allowing N number of the processing elements in the mixed mode parallel processor system to perform parallel operations in SIMD operation, and a step of allowing the M sets of the processing units to perform parallel operations and allowing S number of the processing elements to perform parallel operations in MIMD operation. 
     The second mixed mode parallel processor program according to the present invention is the above first mixed mode parallel processor program further comprising a step of allowing part of memory resources of the processing units to operate as an instruction cache memory, in MIMD operation, and a step of allowing general-purpose register resources of the processing units to operate as a tag storage area for the instruction cache. 
     The third mixed mode parallel processor program according to the present invention is the above second mixed mode parallel processor program further comprising a step of allowing a sole control circuit in the processing unit to perform instruction cache control and instruction sequence control. 
     The fourth mixed mode parallel processor program according to the present invention is the above second or third mixed mode parallel processor program further comprising a step of allowing P of the S memory resources belonging to S number of the processing elements, in each of the processing units, where P&lt;S, to operate as instruction cache memories, and allowing the remaining S−P memory resources to operate as data memories or as data cache memories, in MIMD operation, a step of allowing one of S sets of the general-purpose register resources, belonging to S number of the processing elements, to directly operate as the general-purpose register resources of the processing units, and a step of allowing T or a predetermined constant number of sets out of the remaining S−1 sets, where T&lt;S−1, to operate as tag storage resources for instruction cache, and allowing the remaining sets to operate as data cache tag storage resources in case of using a data cache. 
     Meritorious Effects of the Invention 
     The present invention has a merit that a mixed mode parallel processor may be implemented in which, as compared to the simple SIMD processor having the same number of PEs, the processing performance at the time of SIMD processing may be prevented from being lowered even though the circuit scale is not appreciably increased. 
     The reason is that N number of processing elements perform parallel operations with other (N−1) processing elements in SIMD operation and S out of N number of the processing elements perform parallel operations with other (=N÷S)−1 processing elements, in MIMD operation, where S is a natural numbers not smaller than 2. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a block diagram showing the configuration of a first exemplary embodiment of the present invention. 
         FIG. 2  is a block diagram showing a detailed structure of the first exemplary embodiment of the present invention. 
         FIG. 3  is a flowchart for illustrating the operation of the first exemplary embodiment of the present invention. 
         FIG. 4  is a diagrammatic view for illustrating the contents of the access information for an instruction cache of the first exemplary embodiment of the present invention. 
         FIG. 5  is a block diagram showing the configuration of an example of the first exemplary embodiment of the present invention. 
         FIG. 6  is a block diagram showing the configuration of a second exemplary embodiment of the present invention. 
     
    
    
     EXPLANATION OF REFERENCE SIGNS 
     
         
         PS mixed mode parallel processor system 
         CP control processing element 
         PE 1 ˜PEn processing elements 
         MEM main memory 
         BUS common bus 
         PU 1  processing unit 
         PU 1 ˜PUm processing units 
         RAM 1 ˜RAMn memories 
         GPR 1 ˜GPRn register resources 
         ALU 1 ˜ALUn arithmetic/logic units 
         ISEL 1 ˜ISELm instruction stream selectors 
         PC program counters 
         MODE mode designation register 
         CTR 1 ˜CTRm control circuits 
         CTR 1  control circuit 
         RAM 0  memory 
         GRP 0  register resource 
         CTR 0  control circuit 
         ALU 0  arithmetic/logic unit 
         ARBT arbitration circuit 
         FF 1 ˜FFr general-purpose registers 
         ID 1 , I D 2  instruction decoder circuits 
         SELG 1 ˜SELGr data selectors 
         RSEL 1 ˜RSEL 2  operand readout selectors 
         CSEL 1  control selector 
         SELAD 1  address selector 
         CMP 1  comparator circuit 
       
    
     PREFERRED MODES FOR CARRYING OUT THE INVENTION 
     A mixed mode parallel processor system according to the present invention includes N number of processing elements PEs capable of performing SIMD operations. Each PE includes a memory (resource) and general-purpose registers (resources) for storing the temporary results of partial operation in the course of the arithmetic/logic operation. The mixed mode parallel processor system also includes M (=N÷S) instruction cache control circuits, not containing an instruction cache tag storage area, and M number of instruction sequence control circuits. It is noted that M, N and S are natural numbers. 
     A group consisting of S number of processing elements PEs, neighboring to each other, a sole instruction cache control circuit and a sole instruction sequence control circuit makes up a processing unit PU that performs MIMD operations. The instruction cache control circuit and the instruction sequence control circuit may also be included in the sole processing element PE. 
     In MIMD operation, P number (P&lt;S) of memories out of S number of memories (resources) in each processing unit PU operate as instruction cache memories, with the remaining memories (resources) operating as data memories or as data cache memories. One set out of S sets of general-purpose registers (resources) directly operates as the general-purpose registers (resources) of the processing unit PU. 
     T set (T&lt;S−1) out of the remaining S−1 sets operate as tag storage registers for instruction cache (directory resources). The remaining S−1−T sets may be arranged as data cache memories operating as tag storage registers for data cache (resources). 
     The mixed mode parallel processor system also includes selectors for switching write data to the memories (resources) or general-purpose registers (resources) for use in SIMD operation or for use in MIMD operation. 
     With the above configuration, only the sole instruction sequence control circuit, several selectors and a sole instruction cache control circuit for generating control signals for the instruction sequence control circuit or the selectors per each PE are sufficient as additional circuits needed to implement the mixed mode parallel processor. It is noted that the instruction cache control circuit does not include the tag storage area for instruction cache per se, and is responsible. 
     Thus, it is unnecessary to add the instruction cache memory as well as the tag storage registers (resources) for the instruction cache most liable to increase the circuit scale in implementing the MIMD operations. The mixed mode parallel processor system PS of the present invention thus provides for parallel operations by N number of processing elements in SIMD mode and parallel operations by M (=N÷S) processing units in MIMD mode. Further, the mixed mode parallel processor system PS of the present invention may be implemented with only minor increase in circuit scale as compared with the simple SIMD processor made up of N number of processing elements. 
     Referring to the drawings, a first exemplary embodiment of the present invention is now described in detail.  FIG. 1  is a block diagram showing the configuration of a mixed mode parallel processor system PS according to the first exemplary embodiment of the present invention. Referring to  FIG. 1 , the mixed mode parallel processor system PS according to the first exemplary embodiment of the present invention includes a control processing element CP for performing global control, n number of processing elements PE 1 , PE 2 , PE 3 , PE 4 , . . . , PEn−1, PEn, and a main memory MEM. The processing elements PE 1 , PE 2 , PE 3 , PE 4 , . . . , PEn−1, PEn are connected over a common bus BUS to the control processing element CP. 
     The mixed mode parallel processor system PS is for a case where S=2, and hence M=N/2, that is, for a case where processing units PU 1 , PU 2 , . . . , PUm, each performing a sole MIMD operation, are each made up of two processing elements PEi and PEi+1 each performing a SIMD operation. 
     The processing elements PE 1  to PEn include memories RAM 1  to RAMn (resources), register resources GPR 1  to GPRn, and arithmetic/logic units ALU 1  to ALUn, respectively. The processing units PU 1  to PUm include instruction stream selectors ISEL 1  to ISELm, and control circuits CTR 1  to CTRm, each of which includes a program counter PC and a mode designation register MODE and performs instruction sequence control and instruction cache control, respectively. It is noted that the instruction stream selectors ISEL 1  to ISELm and the control circuits CTR 1  to CTRm can be provided in odd-numbered processing elements PE 1 , PE 3 , . . . , PEn−1. 
     The control processing element CP, providing an instruction stream to the entire PE array in SIMD mode operation, includes a data memory RAM 0  (resource), a register resource GRP 0 , a control circuit CTR 0 , an arithmetic/logic circuit ALU 0  and an arbitration circuit ARBT. 
       FIG. 2  is a block diagram showing a detailed configuration of the processing unit PU 1 . Referring to  FIG. 2 , the processing unit PU 1  includes processing elements PE 1  and PE 2 . The instruction stream selector ISEL 1  of the processing element PE 1  selects an instruction from the control processing element CP or an instruction word from the memory RAM 1  to output the so selected instruction or instruction word to the inside of the processing element PE 1  and to the processing element PE 2 . 
     Instruction decoder circuits ID 1  and ID 2  decode the instruction word to generate control signals. It is noted that two sets each of r number of general-purpose registers FF 1  to FFr are register resources of the processing elements PE 1  and PE 2 . 
     Data selectors SELG 1  to SELGr each select one of ‘write-back data from the arithmetic/logic unit ALU 1 ’, ‘write-back data from the memory RAM 1 ’, and ‘tag update data generated by the control circuit CTR 1 ’, as inputs to the general-purpose registers FF 1  to FFr of the processing element PE 1 . 
     An address selector SELAD 1  selects which of an address value from the control circuit CTR 1  and an address value from the register resource GPR 1  is to be used for accessing the memory RAM 1 . Selectors for operand readout RSEL 1  and RSEL 2  select a source operand, to be supplied to the arithmetic/logic unit ALU 1  (arithmetic/logic unit ALU 2 ), out of output data of the register resource GPR 1  (register resource GPR 2 ). 
     With the above-described configuration, the mixed mode parallel processor operates in N parallel in SIMD mode and in M (=N/2) parallel in MIMD mode substantially as follows. It is noted that, in the following description, reference is sometimes made only to reference numerals or symbols for particular components, without stating the names of the components. 
     Referring to  FIG. 1 , CTR 1  to CTRn control the instruction stream selectors ISEL 1  to ISELm, in SIMD mode operation, in order to select the instruction broadcast from CP. By so doing, the same instruction is broadcast to PE 1  to PEn, as a result of which the SIMD operation by these N number of PE 1  to PEn is carried out. 
     Referring to  FIG. 2 , CTR 1  in PU 1  controls SELG 1  to SELGr, in MIMD mode operation, in order to provide write data (an instruction cache tag) to FF 1  to FFr of PE 1 . Hence, FF 1  to FFr of PE 1  may now be usable for storing tag of the instruction cache. CTR 1  controls SELAD 1  to select an access address value to RAM 1  from CTR 1 , instead of from GPR 1 . Accordingly, RAM 1  may thus be usable as an instruction cache memory. 
     With PE 2 , the circuit from GPR 2  to ALU 2  functions, in MIMD mode operation, as a data path for performing the arithmetic/logic processing operation specified by an instruction, in the same way as in SIMD mode operation. However, these arithmetic/logic processing operations are specified by the result of decoding by the instruction decoder circuit ID 2  of the instruction as read out by the memory RAM 1 . Thus, in the MIMD mode, the major portions of the hardware resources in each of PE 1 , PE 3 , PE 5  and so forth in each of the processing units PU 1  to PUm are used as hardware elements necessary for issuing the instructions in MIMD mode, thus enabling the instructions to be issued efficiently. The so issued instructions are used in the other processing elements PE 4 , PE 6  and so forth. 
     The operation of the first exemplary embodiment of the present invention is now described with reference to the drawings.  FIG. 3  is a flowchart for illustrating the operation of PU 1  of the present exemplary embodiment. For simplicity of explanation, it is assumed that PE 1  and PE 2  in the present exemplary embodiment include the arithmetic/logic units (ALU 1 , ALU 2 ), respectively, and execute one instruction for each cycle at the maximum. It is however possible for each PE 1  and PE 2  to include a plurality of arithmetic/logic units to execute a plurality of instructions simultaneously for each cycle. 
     Moreover, it is assumed that, in the present exemplary embodiment, in PU 1 , PE 1  and PE 2  which perform two SIMD operations, perform a sole MIMD operation, again for simplicity of explanation. In the present exemplary embodiment, the number of bits D of data read out per cycle from RAM 1  and RAM 2  (memory resources) of PE 1  and PE 2  coincides with the instruction word length L. It is however possible that D≧L, in which case it is sufficient to use only L out of the D bits. 
     Alternatively, when D&lt;L, such a configuration is possible in which design parameters of RAM 1  and RAM 2  (memory resources) in PE 1  and PE 2  are adjusted so that D≧L. Still alternatively, such a configuration is also possible in which the number of the processing elements in the processing unit performing a sole MIMD operation is increased to, for example, three to four, in which case the memory resources of two or three of the processing elements may be combined together for use as an instruction cache memory. 
     Referring to  FIG. 3 , PU 1  operates in the following manner to implement the MIMD operation through the use of hardware resources of the two processing elements PE 1  and PE 2  which inherently perform the SIMD operations. The value of MODE in CTR 1 , which can be read out or written by CP, indicate SIMD operation (the value of MODe is “0”) or MIMD operation (the value of MODe is “1”). 
     CP writes “0” in MODE in CTR 1  of PU 1  to set the operation of PU 1  to the SIMD mode or writes “0” to set the operation of PU 1  to the MIMD mode. 
     The cycle-based operation of PU 1  is now described with reference to the flowchart shown in  FIG. 3 . Initially, when MODE=“0” (when the result of step S 1  of  FIG. 3  is YES), ISEL 1  selects the instruction broadcast from CP (step S 2 ) and, when MODE=“1” (when the result of step S 1  is NO), ISEL 1  selects the instruction as read out from RAM 1 . 
     The CTR 1  decides whether or not the instruction as selected is for commanding halt operation (HALT). If the instruction is for HALT (if the result of step S 4  is YES), CTR 1  halts the operations of PE 1 , PE 2  (step S 5 ). 
     Next, ID 1 , ID 2  receive the so selected instruction from ISEL 1  (step S 6 ) and decodes the instruction to generate a variety of control signals needed for executing the instruction (step S 7 ). PE 2  controls GPR 2 , ALU 2  and RAM 2 , by the control signal, generated by ID, to execute the instruction (step S 8 ). 
     On the other hand, PE 1 , if MODE=“0” (if the result of step S 9  is YES), SELG 1  to SELGr of GPR 1  select data from RAM 1  or data from ALU 1  to deliver the so selected data to FF 1  to FFr (step S 10 ). RAM 1  is then controlled to execute the instruction in accordance with the control signal from ID 1  (step S 11 ), based on the instruction from CP (step S 11 ). 
     On the other hand, if MODE=“1” (if the result of the step S 9  is NO), the instruction word, executed during the next cycle, is read out as follows. CTR 1  updates PC to a value equal to the current PC value plus 1, and sets the so updated PC value as the access information for the instruction cache (RAM 1 ) to access the instruction cache (step S 12 ). 
     The access information A for the instruction cache is now described. The contents of the access information A for the instruction cache are schematically shown in  FIG. 4 . In this figure, the access information A is made up of an upper order side bit string X, an intermediate bit string Y and a lower order bit string Z. 
     CTR 1  of PE 1  compares a cache tag stored in one FFy of the registers FF 1  to FFr, and which is specified by Y, with X, to decide whether or not the contents of Y and the bit string X coincide with each other, to make a hit-or-miss decision of the instruction cache (step S 13 ). If the contents of Y coincide with X, that is, in case of an instruction cache hit (result of step S 14  is YES), CTR 1  accesses RAM 1  with an address, which is a bit string made up of a concatenation of Y and Z, in order to read out the instruction. 
     If conversely the contents of the register FFy are not coincident with X, that is, in case of an instruction cache miss (the result of step S 14  is NO), CTR 1  outputs an instruction fetch request to CP, with an access address made up of a concatenation of X and Y as an upper order address part, and a number of zeros corresponding to the number of bits of Z as a lower address part. 
     CTR 1  then performs control to read out a number of instruction words corresponding to the size of cache entries from MEM (step S 17 ). CTR 1  then writes the instruction words from BUS in the matched entries of RAM 1  as the instruction cache (step S 18 ). CTR 1  then causes the value X to be stored in FFy via SELGy (step S 19 ). 
     CTR 1  again formulates the access information A for accessing the instruction cache and accesses the instruction cache (step S 20 ) to decide as to hit or miss of the instruction cache (step S 13 ). Since the value X is now stored in FFy, instruction cache ‘hit’ occurs (the result of the step S 14  is YES). CTR 1  performs an instruction read access to RAM 1  with an address made up of a bit string formed by concatenation of Y and Z (step S 15 ). 
     By the above operation, the instruction word, used for the next cycle, can be read out from RAM 1  which is the instruction cache. It also becomes possible to cause PE 1  and PE 2  to operate in the SIMD mode of executing the same instruction, or to cause PE 1  and P 2  to form a sole PU and to operate in the MIMD mode, depending on the MODE value. In addition, with the present exemplary embodiment, a part of PEs may form a processing unit PU that operates in the MIMD mode, at the same time as another part of PEs operates in the SIMD mode. 
     The above shows an operational example in which RAM 1  is used as a cache memory of a one-way configuration. However, RAM 1  may also operate as a cache memory of a multi-way configuration, if such operation of RAM 1  is allowed by an excess number of the general-purpose registers provided in GPR 1 . 
     PE 1  according to the first exemplary embodiment of the present invention is now described with reference to the drawings.  FIG. 5  is a block diagram showing the configuration of PE 1  of the present first exemplary embodiment. In this figure, PE 1  includes a control selector CSEL 1  (hereinafter referred to simply as CSEL 1 ), not shown in  FIG. 2 , and a comparator circuit CMP 1  (hereinafter referred to simply as CMP 1 ), also not shown in  FIG. 2 . Although neither CSEL 1  nor CMP 1  is shown in  FIG. 2 , this does not mean that PE 1  of  FIG. 2  lacks in CSEL 1  and CMP 1 . These components are included in PE 1  as shown in  FIG. 5 , which is a detailed example of PE of  FIG. 2 . 
     CSEL 1  selects a control signal (selection signal) from ID 1  in the SIMD mode, while selecting a control signal from CTR 1 . This control signal from CTR 1  is a selection signal corresponding to the value Y. The selection signal for CSEL 1  is used as a selection signal for RSEL 1 . 
     In the SIMD mode, the output of RSEL 1  is data for ALU 1  or RAM 1 . In the MIMD mode, the output of RSEL 1  is a tag for the instruction cache, and is delivered to CMP 1 . This CMP 1  compares the tag from RSEL 1  with the value of X from CTR 1  and delivers the result of comparison to CTR 1 . The result of comparison for coincidence indicates an instruction cache ‘hit’, while the result of comparison for non-coincidence indicates an instruction cache ‘miss’. 
     The actual operation and its effect are now described with reference to a more specified example. PE 1  to PEn are each a SIMD parallel processor including 16-bit general-purpose registers FF 1  to FF 16  and RAM 1  to RAMn which are each a 4K word memory with each word being a 32-bit. 
     The processing element PE 1  includes SELG 1  to SELG 16 , associated with FF 1  to FF 16 , SELAD 1  associated with RAM 1 , ISEL 1  for selecting an instruction from CP or a readout instruction word from RAM 1 , CTR 1  provided with PC and with a mode register MODE, CSEL 1  for controlling the selection by RSEL 1 , and CMP 1  for deciding hit or miss of the instruction cache, in addition to the components that make up PE 2 . 
     The following is an example of the configuration for combining PE 1  and PE 2  to enable dynamic switching to a sole PU capable of performing MIMD operation. 
     The 4K word memory RAM 1  of PE 1  is used as an instruction cache. The 16 registers FF 1  to FF 16  are directly used as registers for tag storage registers of the instruction cache. With 28-bit PC in CTR 1 , the upper 16 bits (=X) of the 28-bit instruction cache access information A are reserved, in meeting with the number of bits 16 of each of the registers FF 1  to FF 16 , as a tag for cache entry, and the instruction cache is of the 16-entry 256 words/entry configuration. Out of the remaining 12 (28−16) bits, the upper 4 bits (=Y) specify the GS entry numbers, while the lower 8 bits (=Z) specify the word positions in each entry (see  FIG. 4 ). 
     The 16 general-purpose registers may simultaneously be usable as storage registers for a tag associated with each entry of the instruction cache. Based on this allocation, the operation in case of execution of the steps S 12  to S 20  in the flowchart of  FIG. 3  is as follows: 
     In case the mode value is “1”, ISLE 1  selects the result of readout from RAM 1  as being an instruction. In order for an instruction word to be read out efficiently from a program area on MEM without undue stagnation per each cycle, it is necessary to implement instruction cache control. In the present exemplary embodiment, such instruction cache control is implemented by diverting the pre-existing hardware resources of PE 1  as now described. 
     Initially, the 16-bit value of the contents of the register FFy, as one of the 16 general-purpose registers, specified by the 4-bit value of Y, is compared to the 16-bit value of X, to verify the hit-or-miss of the instruction cache. As a selector for reading out the register FFy, RSEL 1 , present on a data path of PE 1 , may directly be used. 
     If the result of comparison of the contents of FFy to X indicates coincidence, it indicates ‘hit’ of the instruction cache. In this case, a 12-bit string corresponding to a concatenation of Y and Z becomes an access address for RAM 1 . This access address is output via SELAD 1  to RAM 1  that operates as the instruction cache memory. An instruction for the next cycle is read out from RAM 1 . 
     If the result of comparison indicates non-coincidence, an access address of 28 bits, of which the upper order 20 bits are a concatenation of 16 bits of X and 4 bits of Y, and the lower 8 bits are all zero, is used. CP 1  delivers the access address to CP. From MEM, connected to CP, 256 instruction words, corresponding to the number of words of the cache entries, are output via ARBT and BUS to RAM 1 . It is noted that, in these instruction words, the bit strings Z are each made up of 8 bits. 
     The instruction word from MEM is written in an address location of a corresponding cache entry. This address location is an area in RAM 1  headed by an address location formed by 12 bits, the upper four bits of which are Y and the lower 8 bits of which are all zero. It is noted that the number 8 of the lower bits is the same as the number of bits of Z. Also, the contents of FFy are changed to the value of X via RSELGy. 
     The access address of 12 bits, obtained on concatenation of Y and Z, is delivered via SEALD 1  to RAM 1 , so that an instruction of the next cycle is read out from RAM 1  that operates as an instruction cache memory. 
     In this manner, an instruction indispensable for performing the MIMD operations may be read out each cycle from the 28-bit memory space by the sole processing unit PU that is made up of two processing elements in the SIMD parallel processor, herein PE 1  and PE 2 . 
     Also, RAM 1 , used by PE 1  in SIMD operation as a data memory, is now used as an instruction cache, while FF 1  to FF 16 , used by PE 1  in SIMD operation as general-purpose registers, are now used as registers for tag storage of instruction cache. The hardware components added for this purpose, namely ISEL 1 , CTR 1 , SELAD 1 , CSEL 1  and CMP 1 , are only small in quantity. 
     In the above exemplary embodiment, no validity bit is appended to a tag of each instruction cache implemented on each general-purpose register. In this case, a tag of interest may be deemed to be invalid if the tag is of a zero value. If, in this case, the SIMD mode is to be switched to the MIMD mode, it is necessary to first clear the tag value of the instruction cache entry to zero and then to prevent the PC value from becoming zero by using a software technique. 
     In another method, it is also possible to extend the tag storage register by one bit and to use the bit as a validity bit, that is, as the information for indicating whether or not the tag of interest is valid. In this case, if the validity bit is “1”, the tag of interest is retained to be valid and, in switching from the SIMD mode to the MIMD mode, the validity bits of the totality of the tags are set to zero in unison. In this case, it is unnecessary to prevent the PC value from becoming zero by using a software technique. 
     The operation and the meritorious effect of the present invention are now described in comparison with the technique of constructing a mixed mode parallel processor based on using the processing elements capable of performing the MIMD operation of the related technique. 
     If, with the related art technique, an instruction word is to be readable from memory space of 28-bit, and a 4K word instruction cache is to be usable, as in the present exemplary embodiment, it is necessary to provide one more 4K word memory for storage of instruction words, in addition to the 4K word memory inherently present in each PE. Moreover, if instruction cache control is to be exercised as in the present exemplary embodiment, it is necessary to add 16-by-16=256 bit flip-flops as registers for tag storage of instruction cache. 
     Considering that the general-purpose registers (resources) and the memories (resources) take up the major portion of the area of the processing element PE that performs the SIMD operation, each PE of the related-art-based mixed mode parallel processor would be of a circuit scale twice that in accordance with the present invention. 
     Thus, the circuit scale of the mixed mode parallel processor of the related art, having the same number of the processing elements in SIMD mode as that of the present invention, is twice that of the present invention. Nevertheless, the peak performance of the mixed mode parallel processor of the related art in SIMD mode operation is about equal to that of the present invention. Although the peak performance of the related art processor in MIMD mode operation is twice that of the processor of the present invention, the circuit scale of the related art processor is twice that of the processor of the present invention. Hence, the related art processor may not be said to be superior to the processor of the present invention from the perspective of the cost performance ratio. 
     The first effect of the present exemplary embodiment of the invention is that the pre-existing simple SIMD parallel processor, supporting only the SIMD mode, may dynamically be re-constructed to a MIMD parallel processor, capable of processing a broader range of application, even though the increase in circuit scale is only small. 
     The reason is that, by grouping a plural number of pre-existing processing elements, performing the SIMD operations, into a plurality of sets, and by re-utilizing pre-existing memory or register resources in each set as an instruction cache memory or as an instruction cache entry based tag storage space, it is unnecessary to add new components of the larger circuit scale which might be necessary to implement the MIMD operations. 
     The second effect of the present exemplary embodiment of the invention is that an application including both the task processed by SIMD and the task processed by MIMD may be processed more effectively than is possible with the conventional mixed mode parallel processor. 
     The reason is that, in the case of an application including both the task processed by SIMD and the task processed by the MIMD, the former task is more amenable to the parallel processing than the latter task, and that, taking this into consideration, the mixed mode parallel processor according to the present invention is more amenable to SIMD parallel processing than the pre-existing MIMD parallel processor based mixed mode parallel processor, if the two processors are similar in circuit scale. 
     It is seen from above that, if the design parameters of the processor of the example of the present invention and those of the related art processor remain the same, the cost performance ratio of the processor of the present invention at the time of the SIMD operation is higher by a factor of approximately two than that of the related art processor, with the cost performance ratio at the time of the MIMD operation remaining unchanged. 
     In case a sole processing unit PU, performing the MIMD operations, is to be constructed by S number of processing units, each performing the SIMD operation, part of the arithmetic/logic units, inherently belonging to the individual processing units, are present unused in the so constructed processing unit PU. These arithmetic/logic units may be interconnected to form a more complex operating unit, such as a division unit or a transcendental function operating unit, which may be utilized from the processing unit PU. It is possible in this case to further improve the operating performance of the processing unit PU than that of the individual processing elements. 
     A second exemplary embodiment of the present invention is now described in more detail with reference to the drawings. The configuration of the mixed mode parallel processor system PS of the present second exemplary embodiment is shown in a block diagram of  FIG. 6 . In this figure, the mixed mode parallel processor system PS of the present second exemplary embodiment includes processing elements PE 1  and PE 2  of the same hardware configuration. The processing element PE 1  operates similarly to the processing element PE 1  of the first exemplary embodiment. An output of the instruction stream selector ISEL 1  of PE 1  is delivered as an input to the instruction stream selector ISEL 1  of PE 2 . The instruction stream selector ISEL 1  of PE 2  selects an output of the instruction stream selector ISEL 1  of PE 1  at all times. 
     In PE 2 , CTR 1  exercises control so that the operation takes place using the instruction word output from ISEL 1  of PEI. For example, a clamp terminal may be provided on the control circuit CTR 1  of PE 1  and PE 2 , so that, when CTR 1  is clamped at ‘1’, the operation is that of PE 1  and, when CTR 2  is clamped at ‘0’, the operation is that of PE 2 . 
     With the above-described configuration of the second exemplary embodiment of the present invention, it is sufficient to fabricate PE 1  and PE 2  of the same configuration and hence the prime cost may be decreased. 
     The above-described first and second exemplary embodiments of the present invention may be firmware-controlled with the use of a micro-program. 
     The present invention may be applied to an application of implementing the mixed mode parallel processor, capable of dynamically switching between the SIMD and MIMD operations, at a reduced cost. 
     Although the present invention has so far been described with reference to preferred exemplary embodiments, the present invention is not to be restricted to the exemplary embodiments. It is to be appreciated that those skilled in the art can change or modify the exemplary embodiments without departing from the spirit and the scope of the present invention.