Patent Publication Number: US-9412509-B2

Title: Multilayer electronic component having conductive patterns and board having the same

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application claims the benefit of Korean Patent Application No. 10-2014-0077158 filed on Jun. 24, 2014, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference. 
     BACKGROUND 
     The present disclosure relates to a multilayer electronic component and a board having the same. 
     An inductor, an electronic component, is a representative passive element configuring an electronic circuit together with a resistor and a capacitor to remove noise. 
     Among multilayer electronic components, a multilayer inductor may have a structure in which conductive patterns are formed on insulating layers using a magnetic material or a dielectric material as a main material, the insulating layers having the conductive patterns formed thereon are stacked to form an internal coil part within a multilayer body, and external electrodes for electrically connecting the internal coil part to an external circuit are formed on outer surfaces of the multilayer body. 
     The internal coil part is formed within the multilayer body to generate inductance. A vertical multilayer inductor in which the internal coil part is disposed in a direction perpendicular to a mounting surface of a board in order to generate relatively high inductance has been known. 
     The vertical multilayer inductor may obtain higher inductance than a multilayer inductor in which the internal coil part is disposed in a horizontal direction, and may increase a magnetic resonance frequency. 
     RELATED ART DOCUMENT 
     (Patent Document 1) Japanese Patent Laid-Open Publication No. 2003-077728 
     SUMMARY 
     An exemplary embodiment in the present disclosure may provide a multilayer electronic component having reduced parasitic capacitance, and a board having the same. 
     According to an exemplary embodiment in the present disclosure, the perimeter of at least one conductive pattern disposed in peripheral regions of a multilayer body may be smaller than the perimeters of conductive patterns disposed in a central region of the multilayer body. 
    
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
       The above and other aspects, features and advantages in the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which: 
         FIG. 1  is a schematic perspective view of a multilayer electronic component having an internal coil part according to an exemplary embodiment in the present disclosure; 
         FIG. 2  is an exploded perspective view of a multilayer body according to an exemplary embodiment in the present disclosure; 
         FIG. 3  is a cross-sectional view taken along line I-I′ of  FIG. 1 ; 
         FIG. 4  is a cross-sectional view of a multilayer electronic component according to another exemplary embodiment in the present disclosure; 
         FIG. 5  is a cross-sectional view for describing a distance between a conductive pattern and an upper surface of a multilayer body in a multilayer electronic component according to an exemplary embodiment in the present disclosure; and 
         FIG. 6  is a perspective view of the multilayer electronic component of  FIG. 1  mounted on a printed circuit board. 
     
    
    
     DETAILED DESCRIPTION 
     Exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. 
     The disclosure may, however, be exemplified in many different forms and should not be construed as being limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. 
     In the drawings, the shapes and dimensions of elements may be exaggerated for clarity, and the same reference numerals will be used throughout to designate the same or like elements. 
     Multilayer Electronic Component 
     Hereinafter, a multilayer electronic component according to an exemplary embodiment in the present disclosure. In particular, a multilayer inductor will be described as an example, and the present disclosure is not limited thereto. 
       FIG. 1  is a schematic perspective view of a multilayer electronic component having an internal coil part according to an exemplary embodiment in the present disclosure. 
     Referring to  FIG. 1 , a multilayer electronic component according to this exemplary embodiment in the present disclosure may include a multilayer body  110 , an internal coil part  120 , and first and second external electrodes  131  and  132 . 
     The perimeter of at least one conductive pattern disposed in peripheral regions of the multilayer body  110  among conductive patterns forming the internal coil part  120  may be smaller than the perimeters of conductive patterns disposed in a central region of the multilayer body  110  among the conductive patterns. 
     The perimeters of conductive patterns  121  disposed in regions of the multilayer body  110  adjacent to the first and second external electrodes  131  and  132  may be reduced, such that distances between the first and second external electrodes  131  and  132  and the conductive patterns  121  are increased, whereby parasitic capacitance may be decreased. 
     In the multilayer electronic component  100  according to the exemplary embodiment in the present disclosure, a length direction′ refers to an ‘L’ direction of  FIG. 1 , a ‘width direction’ refers to a ‘W’ direction of  FIG. 1 , and a ‘thickness direction’ refers to a ‘T’ direction of  FIG. 1 . 
     The multilayer body  100  may have lower and upper surfaces S 1  and S 2  opposing each other in the thickness T direction, both side surfaces S 5  and S 6  opposing each other in the width W direction, and both end surfaces S 3  and S 4  opposing each other in the length L direction. 
     The multilayer electronic component  100  according to the exemplary embodiment in the present disclosure may have a form in which a thickness T of the multilayer body  110  is larger than a width W of the multilayer body  110  in order to generate a high inductance. 
     A general multilayer electronic component has been manufactured so that a width and a thickness thereof are substantially the same as each other. 
     However, in the multilayer electronic component  100  according to the exemplary embodiment in the present disclosure, since the thickness T of the multilayer body  110  is larger than the width W of the multilayer body  110 , even in the case that a mounting area occupied by the multilayer electronic component is not increased at the time of mounting the multilayer electronic component on a board, a magnetic path area may be increased, whereby relatively high inductance may be obtained. 
     In the case in which the thickness T of the multilayer body  110  is larger than the width W of the multilayer body  110  as in the exemplary embodiment in the present disclosure, a high inductance may be secured. However, an area of the internal coil part  120  may be increased as compared with a general multilayer electronic component, whereby parasitic capacitance may also be increased. 
     However, according to the exemplary embodiment in the present disclosure, the perimeters of the conductive patterns disposed in the regions adjacent to the first and second external electrodes  131  and  132  are reduced and the distances between the first and second external electrodes  131  and  132  and the conductive patterns  121  are increased, whereby the above-mentioned problem may be solved. 
       FIG. 2  is an exploded perspective view of a multilayer body according to an exemplary embodiment in the present disclosure. 
     Referring to  FIG. 2 , the multilayer body  110  may include a plurality of insulating layers  111  and conductive patterns  121  and  122  formed on the insulating layers  111 . 
     A raw material forming the insulating layer  111  may be known ferrite such as Mn—Zn-based ferrite, Ni—Zn-based ferrite, Ni—Zn—Cu-based ferrite, Mn—Mg-based ferrite, Ba-based ferrite, Li-based ferrite, or the like, but is not limited thereto. 
     The multilayer body  110  may be formed by stacking the plurality of insulating layers  111 , and the plurality of insulating layers  111  forming the multilayer body  110  may be in a sintered state. In addition, adjacent insulating layers  111  may be integrated with each other so that boundaries therebetween are not readily apparent without a scanning electron microscope (SEM). 
     The internal coil part  120  may be formed by electrically connecting the conductive patterns  121  and  122  formed at a predetermined thickness on the plurality of insulating layers  111  to each other. 
     The perimeters of the conductive patterns  121  disposed in the peripheral regions may be smaller than the perimeters of the conductive patterns  122  disposed in the central region. 
     The conductive patterns  121  and  122  may be formed by applying a conductive paste containing a conductive metal on the insulating layers  111  using a printing method, or the like. As a method of printing the conductive paste, a screen printing method, a gravure printing method, or the like, may be used. However, the present disclosure is not limited thereto. 
     Vias may be formed at predetermined positions in the respective insulating layers  111  on which the conductive patterns  121  and  122  are printed, and the conductive patterns  121  and  122  formed on the respective insulating layers  111  may be electrically connected to each other through the vias to form a single internal coil part  120 . 
     Here, the conductive patterns  121  and  122  may be disposed to be perpendicular to the lower surface S 1  or the upper surface S 2  of the multilayer body  110 . That is, the conductive patterns  121  and  122  may be disposed to be perpendicular to the lower surface (mounting surface), which is a surface of the multilayer body facing the board at the time of mounting the multilayer electronic component  100  on the board. Therefore, an axis of the internal coil part  120  may be parallel with respect to the mounting surface of the multilayer body  110 . 
     The conductive metal forming the conductive patterns  121  and  122  is not particularly limited as long as it has excellent electrical conductivity. For example, the conductive metal may be at least one selected from the group consisting of silver (Ag), palladium (Pd), aluminum (Al), nickel (Ni), titanium (Ti), gold (Au), copper (Cu), platinum (Pt), and mixtures thereof. 
     The first and second external electrodes  131  and  132  may be disposed on both end surfaces S 3  and S 4  of the multilayer body  110 , respectively. 
     The first and second external electrodes  131  and  132  may be connected to lead portions formed at both ends of the internal coil part  120  and exposed to both end surfaces S 3  and S 4  of the multilayer body  110 , respectively. 
     The first and second external electrodes  131  and  132  may include band surfaces extended to portions of the lower and upper surfaces S 1  and S 2  and the side surfaces S 5  and S 6 , adjacent to the end surfaces S 3  and S 4 . 
     The first and second external electrodes  131  and  132  may be formed of a conductive material, for example, copper (Cu), silver (Ag), nickel (Ni), or the like, but is not limited thereto. 
     The first and second external electrodes  131  and  132  may be formed by applying a conductive paste prepared by adding a glass frit to a metal powder to the surfaces of the multilayer body and sintering the same. 
       FIG. 3  is a cross-sectional view taken along line I-I′ of  FIG. 1 . 
     Referring to  FIG. 3 , when the widths of band surfaces  131   a  and  132   a  of the first and second external electrodes  131  and  132  are defined as W 1 , the sum of regions of the multilayer body enclosed by the band surfaces  131   a  and  132   a  and regions of the multilayer body extending inwardly from edges of the band surfaces  131   a  and  132   a  by distances 0.5W 1  may be defined as D 1 . 
     Here, the perimeter of at least one conductive pattern  121  of the conductive patterns disposed inside the regions D 1  may be smaller than the perimeters of the conductive patterns  122  disposed outside the regions D 1 . 
     The conductive patterns  121  disposed inside the regions D 1 , the regions adjacent to the first and second external electrodes  131  and  132 , have reduced perimeters, such that the distances between the first and second external electrodes  131  and  132  and the conductive patterns  121  are increased, whereby the parasitic capacitance may be decreased. 
     Here, when a line width of the conductive pattern  121  disposed inside the regions D 1  is P 1  and a line width of the conductive pattern  122  disposed outside the regions D 1  is P 2 , P 1  and P 2  may be the same as each other, but are not limited thereto. 
       FIG. 4  is a cross-sectional view of a multilayer electronic component according to another exemplary embodiment in the present disclosure. 
     Referring to  FIG. 4 , the perimeter of at least one conductive pattern  121  of the conductive patterns disposed in the regions of the multilayer body enclosed by the band surfaces  131   a  and  132   a  of the first and second external electrodes  131  and  132  may be smaller than the perimeters of the conductive patterns  122  disposed in the region of the multilayer body not enclosed by the band surfaces  131   a  and  132   a.    
       FIG. 5  is a cross-sectional view for describing a distance between a conductive pattern and an upper surface of a multilayer body in a multilayer electronic component according to an exemplary embodiment in the present disclosure. 
     Referring to  FIG. 5 , among the conductive patterns in the multilayer electronic component according to this exemplary embodiment in the present disclosure, a distance from the lower surface S 1  or the upper surface S 2  of the multilayer body  110  in the thickness T direction to at least one conductive pattern  121  of the conductive patterns disposed in the peripheral regions of the multilayer body may be greater than a distance from the lower surface S 1  or the upper surface S 2  of the multilayer body  110  in the thickness T direction to the conductive pattern  122  disposed in the central region of the multilayer body among the conductive patterns. 
     That is, when a distance between the conductive pattern  121  disposed in the peripheral regions and the upper surface S 2  of the multilayer body  110  is q 1  and a distance between the conductive pattern  122  disposed in the central region and the upper surface S 2  of the multilayer body  110  is q 2 , q 1  may be greater than q 2 . 
     The distances from the lower surface S 1  or the upper surface S 2  of the multilayer body  110  to the conductive patterns  121  disposed in the regions of the multilayer body adjacent to the first and second external electrodes  131  and  132  are increased, such that the distances between the first and second external electrodes  131  and  132  and the conductive patterns  121  are increased, whereby parasitic capacitance may be decreased. 
     Here, when the widths of the band surfaces  131   a  and  132   a  of the first and second external electrodes  131  and  132  are W 1 , the conductive patterns disposed in the sum of the regions of the multilayer body enclosed by the band surfaces  131   a  and  132   a  and the regions of the multilayer body extending inwardly from edges of the band surfaces  131   a  and  132   a  by distances 0.5W 1  may indicate the conductive patterns  121  disposed in the peripheral regions of the multilayer body. 
     In order to allow the distance from the lower surface S 1  or the upper surface S 2  of the multilayer body  110  in the thickness T direction to at least one conductive pattern  121  of the conductive patterns disposed in the peripheral regions to be greater than the distance from the lower surface S 1  or the upper surface S 2  of the multilayer body  110  in the thickness T direction to the conductive pattern  122  disposed in the central region, the perimeter of the conductive pattern  121  disposed in the peripheral region may be smaller than that of the conductive pattern  122  disposed in the central region while the line widths of the conductive patterns  121  and  122  may be the same as each other. 
     Board Having Multilayer Electronic Component 
       FIG. 6  is a perspective view of the multilayer electronic component of  FIG. 1  mounted on a printed circuit board. 
     Referring to  FIG. 6 , a board  200  having a multilayer electronic component  100  according an exemplary embodiment in the present disclosure may include a printed circuit board  210  on which the multilayer electronic component  100  is mounted, and first and second electrode pads  211  and  212  formed on an upper surface of the printed circuit board  210  to be spaced apart from each other. 
     Here, the multilayer electronic component  100  may be electrically connected to the printed circuit board  210  by solders  230  in a state in which the first and second external electrodes  131  and  132  thereof are positioned to contact the first and second electrode pads  211  and  212 , respectively. 
     The multilayer electronic component  100  may be mounted on the printed circuit board  210  so that the lower surface S 1  thereof in the thickness T direction is disposed to face the upper surface of the printed circuit board  210 , and thus, the conductive patterns  121  and  122  of the multilayer electronic component  100  may be disposed to be perpendicular to the printed circuit board  210 . 
     A description of features of the board having a multilayer electronic component, the same as those of the multilayer electronic component described above, will be omitted in order to avoid redundancy. 
     As set forth above, according to exemplary embodiments of the present disclosure, the perimeters of the conductive patterns disposed in the regions of the multilayer body adjacent to the external electrodes may be reduced, such that the distances between the external electrodes and the conductive patterns are increased, whereby the parasitic capacitance may be decreased. 
     While exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations could be made without departing from the scope of the present invention as defined by the appended claims.