Patent Publication Number: US-2022232185-A1

Title: Image sensing device and method for operating the same

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     The present application claims priority of Korean Patent Application No. 10-2021-0007819, filed on Jan. 20, 2021, which is incorporated herein by reference in its entirety. 
     BACKGROUND 
     1. Field 
     Exemplary embodiments of the present invention relate to semiconductor designing technology, and more particularly, to an image sensing device and a method for operating the image sensing device. 
     2. Description of the Related Art 
     An image sensing device is a device that captures an image by using the property of a semiconductor that responds to light. Image sensing devices are generally divided into an image sensing device adopting a charge coupled device (CCD) and an image sensing device adopting a Complementary Metal Oxide Semiconductor (CMOS) device. Recently, Image sensing devices using CMOS devices are widely used due to its advantage that analog and digital control circuits can be directly realized over an integrated circuit (IC). 
     SUMMARY 
     Embodiments of the present invention are directed to an image sensing device capable of reducing noise by setting an offset voltage for analog-to-digital (A/D) conversion based on a read-out pixel signal, and a method for operating the image sensing device. 
     In accordance with an embodiment of the present invention, an image sensing device may include a pixel array including a unit pixel suitable to transfer and store charges in response to a transfer signal and read out a pixel signal corresponding to the stored charges in response to a selection signal provided to the unit pixel; a signal converter suitable for comparing the pixel signal with a ramp signal based on a switch signal to generate a distance information signal; and a signal controller suitable for generating the switch signal for initializing the signal converter in a temporal section where the pixel signal is read out. 
     In accordance with another embodiment of the present invention, a method for operating an image sensing device may include reading out, in response to a selection signal, a first pixel signal and a second pixel signal respectively corresponding to a first charges and a second charges that are stored in a unit pixel; setting an offset voltage between the read-out first and second pixel signals and a ramp signal in response to a switch signal; resetting the first and second pixel signals in response to a transfer signal; and generating a distance information signal corresponding to a voltage change difference between the reset first pixel signal and the reset second pixel signal in response to the ramp signal. 
     In accordance with another embodiment of the present invention, a method for operating an image sensing device having a pixel array including a unit pixel comprising a first pixel and a second pixel, the method may include storing a first charges in the first pixel based on a first photodiode output, the first charges a) based on a reflected signal returning to the image sensing device from a subject and b) produced in response to a first phase signal that is in phase with an optical signal output from the image sensing device; storing a second charges in the second pixel based on a second photodiode output, the second charges a) based on the reflected signal and b) produced in response to a second phase signal that has a phase difference with the optical signal output from the image sensing device; reading out a first pixel signal from the first pixel corresponding to the first charges; reading out a second pixel signal from the second pixel corresponding to the second charges; and comparing the first pixel signal and the second pixel signal to a ramped reference signal to generate a distance information signal corresponding to a voltage change difference. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a block diagram illustrating an image sensing device in accordance with an embodiment of the present invention, 
         FIG. 2  is a circuit diagram illustrating a unit pixel included in a pixel array shown in  FIG. 1 , 
         FIG. 3  is a block diagram illustrating a signal converter shown in  FIG. 1 , 
         FIG. 4  is a timing diagram illustrating an operation of the image sensing device shown in  FIG. 1 , 
         FIG. 5  is a flowchart describing an operation of an image sensing device in accordance with an embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION 
     Exemplary embodiments of the present invention will be described below in more detail with reference to the accompanying drawings. The present invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. Throughout the disclosure, like reference numerals refer to like parts throughout the various figures and embodiments of the present invention. 
     It will be understood that when an dement is referred to as being “coupled” or “connected” to another element, it can be directly coupled or connected to the other element or intervening elements may be present therebetween. In contrast, it should be understood that when an element is referred to as being “directly coupled” or “directly connected” to another element, there are no intervening elements present. Other expressions that explain the relationship between elements, such as “between”, “directly between”, “adjacent to” or “directly adjacent to” should be construed in the same way. 
     The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. In the present disclosure, the singular forms are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprise”, “include”, “have”, etc. when used in this specification, specify the presence of stated features, numbers, steps, operations, elements, components, and/or combinations of them but do not preclude the presence or addition of one or more other features, numbers, steps, operations, elements, components, and/or combinations thereof. 
       FIG. 1  is a block diagram illustrating an image sensing device  100  in accordance with an embodiment of the present invention. 
     Referring to  FIG. 1 , the image sensing apparatus  100  may generate a distance information signal DOUT indicating a depth from a subject  200  by using a time of flight (TOF) method. For example, the image sensing device  100  may detect a phase difference between a first optical signal MS output to the subject  200  and a second optical signal RS reflected from the subject  200  to generate the distance information signal DOUT. The image sensing apparatus  100  may include an optical transmitter  110 , an optical receiver  120 , a signal controller  130 , a pixel array  140 , and a signal converter  150 . 
     The optical transmitter  110  may output the first optical signal MS to the subject  200 . Herein, the first optical signal MS may be a periodic signal that periodically toggles. 
     The optical receiver  120  may receive the second optical signal RS that is reflected from the subject  200 . The optical receiver  120  may remove noise originating from ambient light from the second optical signal RS and provide the pixel array  140  with a third optical signal RS′ corresponding to the first optical signal MS. 
     The signal controller  130  may generate control signals MIXA, MIXB, ROWs, SW, and VRAMP for controlling the pixel array  140  and the signal converter  150 . Referring to  FIG. 1 , the signal controller  130  may include a phase signal generator  132 , a control signal generator  134 , and a ramp signal generator  136 . 
     The phase signal generator  132  may generate a first phase signal MIXA and a second phase signal MIXB having different phases. For example, the first and second phase signals MIXA and MIXB may have a phase difference for example of approximately 180 degrees, but other phase differences may be used. The first and second phase signals MIXA and MIXB may have the same period as the first optical signal MS, and one of the first phase signal MIXA and the second phase signal MIXB may have the same phase as that of the first optical signal MS with the other one having a phase difference of approximately 180 degrees (see  FIG. 4 ). 
     The control signal generator  134  may generate a plurality of row signals ROWs for controlling the pixel array  140  on a row basis. For example, the control signal generator  134  may generate first row signals for controlling the pixels that are arranged in a first row of the pixel array  140  and generate n th  row signals for controlling the pixels that are arranged in an n th  row of the pixel array  140  (where ‘n’ is a natural number greater than 2). Also, the control signal generator  134  may generate a switch signal SW for initializing the signal converter  150 . 
     The ramp signal generator  136  may generate a ramp signal VRAMP and transfer the ramp signal VRAMP to the signal converter  150 , The ramp signal VRAMP may include a signal having a voltage level which rises at a predetermined slope between a low voltage level and a high voltage level. 
     The pixel array  140  may generate a plurality of pixel signals VPXs based on the third optical signal RS′, the first and second phase signals MIXA and MIXB, and the row signals ROWs. The pixel array  140  may include at least one unit pixel  142  (shown for example in  FIG. 2 ) for measuring a distance to the subject  200 . In one embodiment, the unit pixel  142  may be selected based on the row signals ROWs, and the unit pixel  142  may generate pixel signals VPXs such as the first pixel signal VPX_A and the second pixel signal VPX_B based on the first and second phase signals MIXA and MIXB (one having the same phase as the first optical signal MS and the other having a predetermined phase difference such 180 degrees from the first optical signal MS) and the third optical signal RS′ (having a different phase from the first optical signal MS). The structure of the unit pixel  142  will be described in more detail with reference to  FIG. 2 . 
     The signal converter  150  may generate a distance information signal DOUT indicating a distance to the subject  200  based on the pixel signals VPXs. For example, the signal converter  150  may perform an analog-to-digital (A/D) conversion to the first pixel signal VPX_A and the second pixel signal VPX_B so as to produce digital signals and generate the distance information signal DOUT by processing the obtained digital signals, 
       FIG. 2  is a circuit diagram illustrating unit pixel  142  included in the pixel array  140  shown in  FIG. 1 , Referring to  FIG. 2 , unit pixel  142  may include a first pixel TAPA and a second pixel TAPB. 
     The first pixel TAPA may generate the first pixel signal VPX_A based on a reset signal RX, a transfer signal TX, a selection signal SX, and the first phase signal MIXA, The reset signal RX, the transfer signal TX, and the selection signal SX may be signals included in the row signals ROWs described earlier. Referring to  FIG. 2 , a first pixel TAPA may include a first sensing circuit P 1 , a first reset circuit RT 1 , a first transfer circuit TT 1 , a first charge storage circuit C 1 , and a first driving circuit DT 1 , and a first selection circuit ST 1 . 
     The first sensing circuit P 1  may be coupled between a first node N 1  and a low voltage terminal. The first sensing circuit P 1  may generate first charges corresponding to the third optical signal RS′ in response to the first phase signal MIXA. In one embodiment, the first sensing circuit P 1  may include a photodiode which receives the third optical signal RS′ and converts the third optical signal RS′ into a first digital signal related to the first charges and provides (in response to the first phase signal MIXA) the first digital signal to the first node N 1 . 
     The first reset circuit RT 1  may be coupled between a high voltage terminal and the first node N 1 . The first reset circuit RT 1  may reset the first sensing circuit P 1  and the first charge storage circuit C 1  in response to the reset signal RX. In one embodiment, the first reset circuit RT 1  may include an NMOS transistor. 
     The first transfer circuit TT 1  may be coupled between the first node N 1  and a first floating diffusion node FD 1 , The first transfer circuit TT 1  may reset the first charge storage circuit C 1  in response to the transfer signal TX and transfer the first charges generated from the first sensing circuit P 1  to the first charge storage circuit C 1 . According to one embodiment of the present invention, in a read-out section of the first pixel TAPA, the first transfer circuit TT 1  may reset the first charge storage circuit C 1  in response to the transfer signal TX. In one embodiment, the first transfer circuit TT 1  may include an NMOS transistor. 
     The first charge storage circuit C 1  may be coupled between the first floating diffusion node FD 1  and a low voltage terminal. As described above, in a read-out section of the first pixel TAPA, the first charge storage circuit C 1  may be reset by the first transfer circuit TT 1 . In one embodiment, the first charge storage circuit C 1  may include a parasitic capacitor and/or a capacitor added between the first floating diffusion node FD 1  and the low voltage terminal. 
     The first driving circuit DT 1  may be coupled between a high voltage terminal and the first selection circuit ST 1 . The first driving circuit DT 1  may drive a first column line COL 1  with a high voltage that is supplied through the high voltage terminal based on the voltage applied to the first floating diffusion node FD 1 . In one embodiment, the first driving circuit DT 1  may include an NMOS transistor. 
     The first selection circuit ST 1  may be coupled between the first driving circuit DT 1  and the first column line COL 1 . The first selection circuit ST 1  may selectively couple the first driving circuit DT 1  to the first column line COL 1  in response to the selection signal SX. In one embodiment, the first selection circuit ST 1  may include an NMOS transistor. 
     The second pixel TAPB may generate the second pixel signal VPX_B based on the reset signal RX, the transfer signal TX, the selection signal SX, and the second phase signal MIXB, Referring to  FIG. 2 , the second pixel TAPB may include a second sensing circuit P 2 , a second reset circuit RT 2 , a second transfer circuit TT 2 , a second charge storage circuit C 2 , and a second driving circuit DT 2 , and a second selection circuit ST 2 . 
     The second sensing circuit P 2  may be coupled between the second node N 2  and a low voltage terminal that can be but is not necessarily the low voltage terminal of TAPA. The second sensing circuit P 2  may generate second charges corresponding to the third optical signal RS′ in response to the second phase signal MIXB. In one embodiment, the second sensing circuit P 2  may include a photodiode which receives the third optical signal RS′ and converts the third optical signal RS′ into a second digital signal related to the second charges and provides (in response to the second phase signal MIXB) the second digital signal to the second node N 2 . 
     The second reset circuit RT 2  may be coupled between a high voltage terminal (that can be but is not necessarily the high voltage terminal of TAPA) and the second node N 2 . The second reset circuit RT 2  may reset the second sensing circuit P 2  and the second charge storage circuit C 2  in response to the reset signal RX. In one embodiment, the second reset circuit RT 2  may include an NMOS transistor. 
     The second transfer circuit TT 2  may be coupled between the second node N 2  and the second floating diffusion node FD 2 . The second transfer circuit TT 2  may reset the second charge storage circuit C 2  in response to the transfer signal TX and transfer the second charges generated from the second sensing circuit P 2  to the second charge storage circuit C 2 . According to one embodiment of the present invention, in a read-out section of the second pixel TAPB, the second transfer circuit TT 1  may reset the second charge storage circuit C 2  in response to the transfer signal TX, In one embodiment, the second transfer circuit TT 2  may include an NMOS transistor. 
     The second charge storage circuit C 2  may be coupled between the second floating diffusion node FD 2  and the low voltage terminal. As described above, in a read-out section of the second pixel TAPB, the second charge storage circuit C 2  may be reset by the second transfer circuit TT 2 . In one embodiment, the second charge storage circuit C 2  may include a parasitic capacitor and/or a capacitor added between the second floating diffusion node FD 2  and the low voltage terminal. 
     The second driving circuit DT 2  may be coupled between the high voltage terminal and the second selection circuit ST 2 . The second driving circuit DT 2  may drive the second column line COL 2  with a high voltage that is supplied through the high voltage terminal based on the voltage that is applied to the second floating diffusion node FD 2 . In one embodiment, the second driving circuit DT 2  may include an NMOS transistor. 
     The second selection circuit ST 2  may be coupled between the second driving circuit DT 2  and the second column line COL 2 , The second selection circuit ST 2  may selectively couple the first driving circuit DT 2  to the second column line COL 2  in response to the selection signal SX. In one embodiment, the second selection circuit ST 2  may include an NMOS transistor. 
       FIG. 3  is a block diagram illustrating an example of the signal converter  150  shown in  FIG. 1 . 
     The signal converter  150  may generate a first count signal CNT 1  and a second count signal CNT 2  corresponding to the voltage level difference between the first pixel signal VPX_A and the second pixel signal VPX_B and the ramp signal VRAMP. Since the signal converter  150  may have the same structure to process the first pixel signal VPX_A and the second pixel signal VPX_B,  FIG. 3  shows only the structure that processes one of the first pixel signal VPX_A and the second pixel signal VPX_B. 
     Referring to  FIG. 3 , the signal converter  150  may include first and second input units (first and second input circuits) C 3  and C 4  (e.g., a capacitive circuit which may include capacitors), first and second switching units (first and second switching circuits) SW 1  and SW 2  (e.g., switching circuits which may include transistor-controlled switches), a comparison unit  310  (e.g., a comparator), and a counting unit  320  (e.g., a counter). The signal converter  150  may in one embodiment include a structure that calculates the first count signal CNT 1  and the second count signal CNT 2  and outputs the difference between the count values CNT 1  and CNT 2  as a distance information signal DOUT, such as a logic operation unit (e.g., a logic circuit). 
     The first input unit C 3  may generate an input signal VIN_A or VIN_B by receiving the first pixel signal VPX_A or the second pixel signal VPX_B. For example, the first input unit C 3  may include a capacitor that samples the first pixel signal VPX_A or VPX_B to generate the input signal VIN_A or VIN_B. 
     The second input unit C 4  may generate a reference signal VREF by receiving the ramp signal VRAMP. For example, the second input unit C 4  may include a capacitor that samples the ramp signal VRAMP to generate the reference signal VREF. 
     The comparison unit  310  may compare the input signal VIN_A (or VIN_B) with the reference signal VREF to output a comparison signal VOUTP_A (or VOUTP_B). The comparison unit  310  may maintain the comparison signal VOUTP_A (or VOUTP_B) at a logic high level (or a logic low level) until the voltage level of the reference signal VREF becomes the same as the input signal VIN_A (or VIN_B). 
     The first and second switching units SW 1  and SW 2  may be coupled between the input node and the output node of the comparison unit  310 . In response to a switch signal SW, the first and second switching units SW 1  and SW 2  may selectively couple the input node and the output node of the comparison unit  310 . When the switch signal SW transitions between a logic low level and a logic high level, the first and second switching units SW 1  and SW 2  may be turned on to couple the input node to the output node of the comparison unit  310 . 
     The counting unit  320  may count a clock signal CLK in response to the comparison signal VOUTP_A (or VOUTP_B) and output the count signal CNT 1  (or CNT 2 ). The counting unit  320  may output the count signal CNT 1  (or CNT 2 ) having a count value corresponding to a section in which the logic level of the comparison signal VOUTP_A or VOUTP_B is maintained. 
       FIG. 4  is a timing diagram illustrating an operation of the image sensing device  100  shown in  FIG. 1 . 
     Referring to  FIG. 4 , the first and second pixels TAPA and TAPB may perform a reset operation during a reset section RESET in response to a reset signal RX and a transfer signal TX. In one embodiment, when the reset signal RX is activated, the first sensing circuit P 1  of the first pixel TAPA and the second sensing circuit P 2  of the second pixel TAPB may be reset. Also, in response to activation of the reset signal RX and the transfer signal TX, the first charge storage circuit C 1  of the first pixel TAPA and the second charge storage circuit C 2  of the second pixel TAPB may be reset. 
     Subsequently, during an exposure section EXPOSURE, the first and second pixels TAPA and TAPB may generate, transfer, and store respectively first and second charges based on the third optical signal RS′, the transfer signal TX, and the first and second phase signals MIXA and MIXB. In one embodiment, the first sensing circuit P 1  may generate the first charges based on the third optical signal RS′ and the first phase signal MIXA. When the first transfer circuit TT 1  of the first pixel TAPA transfers the first charges in response to the transfer signal TX, the first charge storage circuit C 1  may store the first charges. Likewise, the second sensing circuit P 2  may generate the second charges based on the third optical signal RS′ and the second phase signal MIXB. When the second transfer circuit TT 2  of the second pixel TAPB transfers the second charges in response to the transfer signal TX, the second charge storage circuit C 2  may store the second charges. In this case, the first phase signal MIXA and the second phase signal MIXB may have a phase difference of for example approximately 180 degrees. 
     During a temporal read-out section READOUT (shown in  FIG. 4 ) of the first and second pixels TAPA and TATS, the reset signal RX and the selection signal SX may be activated to a logic high level. The first and second pixels TAPA and TATB may read out the first and second pixel signals VPX_A and VPX_B corresponding to the first and second charges stored in the first and second charge storage circuits C 1  and C 2  in response to the selection signal SX. 
     In one embodiment, in the first pixel TAPA, the first selection circuit ST 1  may electrically couple the first driving circuit DT 1  and the first column line COL 1  in response to activation of the selection signal SX. The first driving circuit DT 1  may read out the first pixel signal VPX_A by driving the first column line COL 1  with a high voltage according to the voltage applied to the first floating diffusion node FD 1 . 
     Similarly in one embodiment, in the second pixel TAPB, the second selection circuit ST 2  may electrically couple the second driving circuit DT 2  and the second column line COL 2  in response to activation of the selection signal SX. The second driving circuit DT 2  may read out the second pixel signal VPX_B by driving the second column line COL 2  with a high voltage according to the voltage applied to the second floating diffusion node FD 2 . 
     According to one embodiment of the present invention, the switch signal SW may transition between a logic low level and a logic high level at the beginning of the temporal read-out section READOUT. The control signal generator  134  of the signal controller  130  may activate the selection signal SX for the temporal read-out section READOUT shown in  FIG. 4 , and when the selection signal SX is activated, the switch signal SW may transition between a logic low level and a logic high level. 
     In response to the transition of the switch signal SW changing from a logic low level to a logic high level, the signal converter  150  may be initialized. In one embodiment, in response to the transition of the switch signal SW to a logic high level, the first and second switching units SW 1  and SW 2  may be turned on to couple the input node and the output node of the comparison unit  310 . The offset voltage between the read-out first and second pixel signals VPX_A and VPX_B and the ramp signal VRAMP may be stored in the first and second input units C 3  and C 4 . The initialization operation of the signal converter  150  may in one embodiment include an auto-zeroing operation of offsetting the input offset voltage of the comparison unit  310 . 
     In one embodiment, after the switch signal SW transitions to a logic high level, the control signal generator  134  of the signal controller  130  may activate the transfer signal TX. When the transfer signal TX is activated while the reset signal RX is in a logic high level in a temporal read-out section READOUT (such as shown in  FIG. 4 ), the first and second pixel signals VPX_A and VPX_B are reset. In one embodiment, the first and second reset circuits RT 1  and RT 2  and the first and second transfer circuits TT 1  and TT 2  may initialize the first and second charge storage circuits C 1  and C 2  in response to the activated reset signal RX and the transfer signal TX. Accordingly, as illustrated in the lower half of  FIG. 4 , the first and second pixel signals VPX_A and VPX_B, that is, the input signals VIN_A and VIN_B may increase by as much as the reset voltage changes (that is by as much as ΔVPX_A and ΔVPX_B). 
     After the transfer signal TX is activated, the ramp signal generator  136  of the signal controller  130  may generate a ramp signal VRAMP that rises (e.g., gradually rises) from a low voltage to a high voltage. The voltage level of the reference signal VREF may also increase in proportion to the ramp signal VRAMP, The comparison unit  310  in one embodiment may compare the input signals VIN_A and VIN_B with the reference signal VREF and continue to produce the comparison signals VOUTP_A and VOUTP_B at a logic high level or a logic low level until the voltage level of the reference signal VREF becomes the same as the input signals VIN_A and VIN_B. 
     In one embodiment, the counting unit  320  may count the dock signal CLK (shown in the lower half of  FIG. 4 ) from a first moment when the reference signal VREF begins to ramp to respective second moments when the logic levels of the comparison signals VOUTP_A and VOUTP_B change, and generate the first and second count signals CNT 1  and CNT 2  that respectively correspond to the voltage changes ΔVPX_A and ΔVPX_B. The signal converter  150  may process the first and second count signals CNT 1  and CNT 2  (corresponding to the voltage changes ΔVPX_A and ΔVPX_B) to output a distance information signal DOUT corresponding to the difference between the first charges and the second charges generated in the first pixels TAPA and the second pixels TAPS. 
       FIG. 5  is a flowchart describing an operation of an image sensing device in accordance with one embodiment of the present invention. 
     In step S 510 , the unit pixel of the pixel array  140  may read out the first and second pixel signals VPX_A and VPX_B in response to the selection signal SX. In a read-out section READOUT, the control signal generator  134  of the signal controller  130  may activate the selection signal SX to a logic high level. When the selection signal SX is activated, the first and second pixels TAPA and TATB may read-out the first and second pixel signals VPX_A and VPX_B corresponding to the first and second charges that are stored in the first and second charge storage circuits C 1  and C 2 . 
     In step S 520 , the signal converter  150  may set an offset voltage between the read-out first and second pixel signals VPX_A and VPX_B and the ramp signal VRAMP. After the selection signal SX is activated to a logic high level in a read-out section READOUT, the control signal generator  134  may transition the switch signal SW between a logic low level and a logic high level. In response to the transition of the switch signal SW, the switching units SW 1  and SW 2  of the signal converter  150  may be turned on, and the offset voltage between the read-out first and second pixel signals VPX_A and VPX_B and the ramp signal VRAMP) may be stored in the first and second input units C 3  and C 4  of the signal converter  150 . 
     In step S 530 , the unit pixel  142  of the pixel array  140  may reset the first and second pixel signals VPX_A and VPX_B in response to the transfer signal TX. After transitioning the switch signal SW, the control signal generator  134  may activate the transfer signal TX to a logic high level. When the transfer signal TX is activated, the first and second pixels TAPA and TATB may initialize the first and second charge storage circuits C 1  and C 2  and reset the first and second pixel signals VPX_A and VPX_B to initial values. 
     In step S 540 , the signal converter  150  may generate a distance information signal DOUT which corresponds to the difference between the voltage changes ΔVPX_A and ΔVPX_B of the first and second pixel signals VPX_A and VPX_B that are reset to the initial values in response to the ramp signal VRAMP. When the transfer signal TX is activated, the ramp signal generator  136  of the signal controller  130  may increase (e.g., gradually increase) the ramp signal VRAMP from a low voltage to a high voltage. 
     The signal converter  150  may generate a first count signal CNT 1  corresponding to the voltage change ΔVPX_A by comparing the rising ramp signal VRAMP with the reset first pixel signal VPX_A. Also, the signal converter  150  may generate a second count signal CNT 2  corresponding to the voltage change ΔVPX_B by comparing the rising ramp signal VRAMP with the reset second pixel signal VPX_B. The signal converter  150  may generate a distance information signal BOUT corresponding to the difference between the voltage changes ΔVPX_A and ΔVPX_B by processing the first count signal CNT 1  and the second count signal CNT 2 . 
     According to one embodiment of the present invention, the image sensing device may set an offset voltage for analog-to-digital (A/D) conversion based on a read-out pixel signal and perform an analog-to-digital (A/D) conversion operation in a state that a pixel signal is reset. While the offset voltage is set and analog-to-digital conversion is performed, the transistor included in a unit pixel, that is, a driving transistor, may maintain the same state. Therefore, noise caused by a change in the threshold voltage of the transistor of the unit pixel, for example, fixed pattern noise, may be removed, and a signal-to-noise ratio of the distance information signal generated from the image sensing device may be improved. 
     While the present invention has been described with respect to the specific embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.