Patent Publication Number: US-2021193624-A1

Title: Apparatus For Non-Volatile Random Access Memory Stacks

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application claims the benefit of the filing date of U.S. Provisional Patent Application No. 62/951,668 filed Dec. 20, 2019, the disclosure of which is hereby incorporated herein by reference. 
    
    
     BACKGROUND 
     Various types of existing memory each have significant limitations. For example, Dynamic Random Access Memory (DRAM) is fast, but low density and volatile. NAND is dense and inexpensive, but slow. Magnetic RAM (MRAM) is neither dense nor fast, and is also relatively expensive. 
     SUMMARY 
     One aspect of the disclosure provides a memory structure, including a NAND block comprising a plurality of oxide layers, the plurality of layers forming a staircase structure at a first edge of the NAND block, a plurality of vias disposed on the staircase structure of NAND block, two or more of plurality of vias terminating along a same plane, a plurality of first bonding interconnects disposed on the plurality of vias, a plurality of bitlines extending across the NAND block, and a plurality of second bonding interconnects disposed along the bitlines. 
     According to some examples, the plurality of first bonding interconnects may be substantially aligned in the same plane with the plurality of second bonding interconnects. Further, the plurality of first bonding interconnects and the plurality of second bonding interconnects may be embedded in a dielectric. According to some examples, the plurality of second bonding interconnects are spaced at wordline contact pitch or greater. 
     In some examples, the memory structure may further include a logic wafer, wherein the logic wafer is face-to-face bonded with the plurality of vias and the bitlines through the first and second bonding interconnects. The logic wafer may include a plurality of bonding interconnects on a bonding surface of the logic wafer. The plurality of bonding interconnects of the wafer may be bonded to the plurality of vias and bitlines using a non-adhesive direct bonding technique or a non-adhesive hybrid bonding technique. 
     According to some examples, the memory structure may further include at least one slit formed in the plurality of oxide layers, the at least one slit separating a first wordline structure from a second wordline structure. The plurality of bitlines may extend across the at least one slit. 
     Another aspect of the disclosure provides a stacked memory device, including at least one first stack layer and at least one second stack layer, wherein each of the first stack layer and the second stack layer include a NAND block comprising a plurality of oxide layers, the plurality of oxide layers forming a staircase structure at a first edge of the NAND block, a first plurality of vias disposed on the staircase structure of NAND block, a second plurality of vias disposed at the first edge of the NAND block, a plurality of first bonding interconnects disposed on and connected to the second plurality of vias, a plurality of bitlines extending across the NAND block, and a plurality of second bonding interconnects disposed along the bitlines. 
     According to some examples, the plurality of first bonding interconnects may be in the same plane with the plurality of second bonding interconnects and/or embedded in dielectric. The first plurality of bonding interconnects and the second plurality of bonding interconnects may all be in one plane embedded in a dielectric. 
     According to some examples, the stacked memory device further includes at least one slit formed in the plurality of oxide layers, the at least one slit separating a first wordline structure from a second wordline structure. The plurality of bitlines may extend across the at least one slit. Further, the stacked memory device may include a plurality of third vias disposed within the at least one slit, and a plurality of fourth vias disposed outside the stack layers. The plurality of second bonding interconnects disposed along the bitlines may be substantially aligned with the third plurality of vias. 
     According to some examples, the plurality of second bonding interconnects may be spaced at wordline contact pitch. Further, each of the first and second stack layers may further include a bitline redistribution layer disposed on an opposing side of the NAND block from the bitlines. 
     According to some examples, each of the first and second stack layers further comprises a silicon layer. The silicon layer may include logic for one or more operations within the stack layer. Such operations may include, for example, switching operations. Moreover, the memory structure may further include a shift register. 
     According to some examples, each stack layer may include an amount of remaining silicon. The amount of remaining silicon may be between 0.1 um to 6 um thick in some examples, or between 6 um to 20 um thick in other examples. 
     Each NAND block may further comprise logic for addressing at least one of data, wordline selection, serialization of data, or deserialization of data. The memory structure ma further include a third layer, the third layer comprising a logic layer, wherein silicon substrate has been completely removed from the first stack layer and the second stack layer. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a perspective view of an example 3D-NAND structure (e.g. structure of 3D-NAND flash) according to aspects of the disclosure. 
         FIGS. 2A-B  are perspective views of example interconnects on bitlines of the 3D-NAND structure of  FIG. 1 . 
         FIG. 3  is a perspective view of the 3D-NAND structure of  FIG. 1  adapted to be face-to-face bonded with a logic wafer according to aspects of the disclosure. 
         FIG. 4  is a perspective view of another example 3D-NAND structure configured to be stacked according to aspects of the disclosure. 
         FIG. 5  is a perspective view of another example 3D-NAND structure configured to be stacked according to aspects of the disclosure. 
         FIG. 6A  is a side view of an example 3D-NAND stack according to aspects of the disclosure. 
         FIG. 6B  is a perspective view of the example 3D-NAND stack of  FIG. 6A . 
         FIG. 7  is a 3D schematic diagram of an example stacked memory according to aspects of the disclosure. 
         FIG. 8  is a side view of another example 3D-NAND stack according to aspects of the disclosure. 
         FIG. 9  is a 3D schematic diagram of another example stacked memory according to aspects of the disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     F2F Bonded Structure 
       FIG. 1  illustrates an example nonvolatile memory (NVM), e.g. 3D-NAND structure  100 , adapted for face-to-face bonding with another structure, such as a logic array. The 3D-NAND structure  100  includes a plurality of stacked oxide layers  110 . For example, the stacked layers  100  include alternating and uniform layers of silicon oxide and silicon nitride stacked on top of a substrate. In other designs, alternating layers of silicon oxide and polysilicon (or some other conductive material) may also be used. The silicon nitride layers may be further processed, such as removed and replaced by tungsten or some other conductive material to form word lines or word planes. Stacks formed using alternating layers of silicon oxide and polysilicon do not need to replace the polysilicon layers with tungsten and instead use polysilicon as the word lines. 
     At a first edge of the structure  100 , the oxide layers  110  are processed to form a staircase arrangement  115 . The staircase arrangement is formed such that the conductive layers including word line planes are exposed. Any other arrangement, alternative to the staircase, may also be implemented to expose the conductive planes or layer. 
     The different layers, each separated by silicon oxide (or any other dielectric) layer, may have different functions. For example, majority of the conductive layers in the middle form word lines or word planes. The bottom of the stack  112  may be a source select layer, or a gate select layer, ground select layer, etc. A top of the stack  118  may be a drain select layer or a string select layer. According to some examples, the oxide layers  110  may be sized differently from one another. For example, some layers may be thicker than others, such as by making the top layer  118  and the bottom layer thicker as compared to the wordline layers in the center of the layer stack  110 . 
     Before the staircase formation, strings or channels  125  are formed in the stack. The strings or channels formation include etching the holes through the whole stack and filling them with one or more conformal layers of various dielectrics, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, and polysilicon. Memory cells may be formed at the location of each intersection of a string or channel with tungsten layer (or other conductive material) which replaced the silicon nitride layers. 
     According to some examples, a slit  105 , such as a trench, extends between and isolates different sections of the stack. 
     The exposed layers may each have one or more wordline contacts  120  extending therefrom. The wordline contacts  120  may be made of tungsten or any of a variety of other conductive materials. Where the word line layers form a staircase arrangement  115 , and the wordline contacts  120  extend from varying levels of the staircase, the wordline vias  120  may vary in size to terminate along a same plane. For example, wordline vias  120  extending from the bottom select layer  112  may be longer as compared to vias extending from the top select layer  118 , such that all wordline contacts or vias  120  terminate along a plane parallel to any of the oxide layers  110  and to bitlines  140 . According to other examples, the wordline vias  120  may terminate along more than one plane. 
     Bitlines  140  extend across the oxide layers  110  above the strings  125 , and the strings  125  extend through the whole stack and connected to the bitlines  140  via bitline contacts (not shown here). While the bitlines  140  are shown in  FIG. 1  as extending across only two sections of the stack separated by a slit  105 , it should be understood that this is only a representative example and that the bitlines  140  may extend across many additional sections of the stack. Moreover, only a few bitlines  140  are shown. It should be understood that the wordline structure and the bitlines  140  may actually extend a significant distance in a direction opposite the staircase  115 . 
     The wordline vias  120  are substantially aligned with bonding interconnects  130  along a longitudinal axis of each wordline via. In other examples, bonding interconnects  130  may be offset from the wordline contact vias  120  using a redistribution layer. The bonding interconnects  130  may be adapted for various bonding techniques, including direct dielectric bonding, non-adhesive techniques, such as a ZiBond® direct bonding technique, or a DBI® hybrid bonding technique, both available from Invensas Bonding Technologies, Inc. (formerly Ziptronix, Inc.), a subsidiary of Xperi Corp. (see for example, U.S. Pat. Nos. 6,864,585 and 7,485,968, which are incorporated herein in their entirety). The bonding interconnects  130  may be used for bonding the 3D-NAND structure  100  to another structure. For example, the wordline vias  120  and bonding interconnects  130  may provide a connection between the wordlines of the 3D-NAND structure  100  and the other structure bonded thereto. In one example, the bonding interconnects  130  are embedded in a dielectric material (e.g. silicon oxide). Then structure  100  is direct bonded to another structure, a dielectric to dielectric bond between the 2 structures first occurs (at room temperature, without any adhesive or external pressure); as the structures are annealed at higher temperature, the interconnects  130  from  100  are bonded to the interconnects on the other structure 
     The bitlines  140  may also include a plurality of bonding interconnects  130  on the opposite side of bitline contacts (not shown here). The bonding interconnects  130  on the bitlines  140  may be spaced apart. For example, each bitline  140  may include an interconnect  130  at one point of intersection with a wordline. 
     The bonding interconnects  130  may be coupled to the bitlines  140  through an interconnect structure.  FIGS. 2A-2B  illustrate examples of such interconnect structures. 
     As shown in  FIG. 2A , bonding interconnect  230  is coupled to bitline  240  through structure  234 . The structure  234  is a narrow, substantially cylindrical structure, such as a circular via. The structure  234  may be made of tungsten or any other conductive material. The structure  234  separates the bonding interconnect  230  from the bitline  240  by a predetermined distance, typically under lmicron, though the predetermined distance may vary. In this regard, the bonding interconnect  230  may be wider than a width of a single bitline. Even in such circumstance, the bonding interconnect  230  may couple to a single bitline  240  without unintentionally coupling to a neighboring bitline. 
       FIG. 2B  shows another example, where structure  236  is elongated as compared to the structure  234  of  FIG. 2A . In this regard, the structure  236  may contact a greater surface area of the bonding interconnect  230  and the bitline  240 , thereby providing for a more stable coupling. Although only one contact structure is shown connecting the bonding interconnect  230  and the bitline  240 , two or more such contact structures may also be used. Although only one the bonding interconnect  230  is shown to connect to each bitline  240 , two or more interconnects  230  may also be used to contact a single bitline, spread along the length of that single bitline  120   
     The bonding interconnects  130  of  FIG. 1  allow for the 3D-NAND structure  100  to be coupled to another structure, such as a logic block or another 3D-NAND structure. For example, the 3D-NAND structure  100  may be face-to-face bonded with the other structure. 
       FIG. 3  illustrates the 3D-NAND structure  100  being coupled with logic wafer  170 . The source select layer  112 , drain select layer  118 , ground, and other elements may be directly interconnected with the logic wafer  170  through the bonding interconnects  130  on the vias  120  and the bitlines  140 . 
     Stack without Remaining Silicon on 3D-NAND Layer 
     According to some examples, the 3D-NAND structure  100  of  FIG. 1  may be stacked vertically with one or more other 3D-NAND structures. In such a stack, silicon may be removed from the 3D-NAND structures or it may remain, each discussed in further detail below. 
       FIG. 4  illustrates a 3D-NAND structure  400  for stacking. In this example, bitlines  440  are coupled to a plurality of bitline vias  424 . The bitline vias  424  may reside in slits  405 . The bitline vias  424  may further reside along edges of the 3D-NAND structure  400  for coupling to edge portions of the bitline  440 . The bitline vias  424  may be built in a same process as used to build wordline vias  420 . 
     Wordlines may be redistributed beyond the oxide layers  410  to enable further stacking, since the wordlines may not go through the oxide layers  410 . As an example of such redistribution, edge vias  422  may be positioned at an edge of the staircase. The edge vias  422  may be copies of wordline vias  420 . Each of the edge vias  422  may be linked to the wordline via  420  of which it is a copy. For example, the edge vias  422  and wordline vias  420  may be linked by a plurality of links  426 , such as wires, traces, or other connections. As the wordlines are redistributed, bonding interconnects  430  may also be moved from wordline vias  420  to the edge vias  422 . 
     Bonding interconnects  430  on the bitlines, as shown in  FIG. 4 , may be spaced at wordline pitch. For example, similar to  FIG. 1 , one bonding interconnect  430  may be positioned on each bitline  440 . In other example, bonding interconnect  430  may be spaced at different pitches at different locations 
       FIG. 5  illustrates another example embodiment  500 . Similar to  FIG. 4 , the embodiment of  FIG. 5  includes wordline vias  420  redistributed beyond the staircase as edge vias  422 , and bitline vias  424 . In this example, however, the bonding interconnects  430  on the bitlines  440  are aligned with the bitline vias  424 . 
       FIGS. 6A-B  illustrate a stacked arrangement of the 3D-NAND structures  400  described above in connection with  FIG. 4 .  FIG. 6A  provides a side view of the stack while  FIG. 6B  provides a perspective view of the same stack. While only three layers of the stack are shown, it should be understood that additional or fewer layers may be included. Moreover, in addition to layers of 3D-NAND structures, the stack may further include other structures, such as a logic layer. Such logic layer may be positioned at a bottom layer of the stack, such that the bond interconnects  430  on the bitlines  440  couple to the logic layer. In other examples, such logic layer may be positioned at a top layer of the stack, where the bond interconnects  430  on the bitlines  440  are redistributed through the bitline vias  424 . 
     In some examples, the stack layers may be direct bonded. According to other examples, the layers may be sequentially built. 
     When stacked, the edge vias  422  of a first layer of the stack align with the edge vias of a second layer of the stack and a third layer of the stack, etc. Moreover, the bitline vias  424  of the first layer of the stack align with the bitline vias of the second and third layers, etc. Accordingly, the edge vias  422  and bitline vias  424  connect the first level of the stack to the second level to the third level, etc. 
     As shown, all silicon has been removed from a widest portion  602  of the oxide layers  410 . In other examples, described below, the silicon or other dielectric may remain in the stack. 
     The stack may further include a vertical switch or transistor (not shown). When data is received for storage in the stack, the vertical switch or transistor may be used to determine which stack layer  682 ,  684 ,  686  the data should be sent to. For example, a particular line may be charged to activate a corresponding stack layer  682 ,  684   686 . 
     As shown in  FIGS. 6A-B , bitlines from a bottom side of each layer are repeated on the opposite (top) side. In other examples, repetition of the bitlines may be omitted. For example, if the layers of the stack are 3D-NAND structures  500  as in  FIG. 5 , wherein the bonding interconnects on the bitlines align with the bitline vias, such repetition may not be needed. 
       FIG. 7  is a schematic diagram illustrating interconnection of components in the 3D-NAND stack  700 . It should be understood that the elements of the stack as shown in  FIG. 7  are not to scale, or otherwise sized or shaped as they may be in an actual stack, but rather are intended to show the relationship and interconnection of components. Moreover, as shown the stack includes four layers  782 - 788  of 3D-NAND. However, similar to the other examples described above, additional or fewer layers may be included. Each of the layers  782 - 788  includes substantially the same elements. 
     As shown, each layer  782 - 788  includes a 3D-NAND array  710 . For example, while the 3D-NAND array  710  is shown as a block, it may actually include a plurality of oxide layers arranged in a staircase arrangement as described above in connection with  FIG. 1 . Each 3D-NAND array  710  may include one or more source select layers and one or more drain select layers. There may be relatively few source select layers, such as 1-8 source select layers, and relatively few drain select layers. As such, the source select layers and drain select layers may be individually routed from the logic layer  770 . 
     A plurality of wordlines  760  are shown for the 3D-NAND array  710 . A wordline redistribution  765  may also be included. According to some examples, the wordlines  760  of a first layer  782  may not be the same as the wordlines of a second layer  784 . For example, the wordlines of different layers may have different switching capabilities. 
     Each stack layer may include a plurality of bitlines  740  extending along a first side of the 3D-NAND array  710  and a bitline redistribution  745  on an opposing side of the 3D-NAND array  710 . The bitlines  740  and bitline redistribution  745  may extend in an opposing direction as compared to the wordlines  760  and wordline redistribution  765 . In some examples, the bitline redistribution  745  may be omitted. For example, referring back to the example of  FIG. 5 , where the bitline vias  424  align with the bonding interconnects  430  on the bitlines  440 , bitlines may be coupled to a next layer of a stack through the bitline vias  424 , and therefore bitline redistribution may not be needed. 
     Bonding interconnects  730  may be used to couple each layer  782 - 788  of the stack. For example, bonding interconnects  730  extend between the bitline redistribution  745  of a first layer  782  and the bitlines  740  of a second layer  784 . The connectivity between each of the layers  782 - 788  may be common, for example, if the bitlines  740  of each layer are common. 
     Stack with Remaining Silicon on 3D-NAND Layer 
     According to some examples, rather than removing silicon from the stack, silicon may be retained in the stack. In this regard, rather than all logic operations occurring in a separate logic layer in the stack, logic operations may be performed at each individual layer of the stack. For example, switching between bitlines in each layer may be performed to enable which layer is accessed. As another example, switching between wordline addresses in each layer may be performed to enable which layer is accessed. 
       FIG. 8  illustrates a stacked arrangement of 3D-NAND structures wherein a silicon or other dielectric layer has been retained in each 3D-NAND layer of the stack. Similar to  FIG. 6A ,  FIG. 8  provides a side view of the stack. While only three layers of the stack are shown, it should be understood that additional or fewer layers may be included. 
     In contrast to  FIG. 6A , the stack of  FIG. 8  includes a silicon layer  880  at a widest portion  602  of the oxide layers  410 . The silicon layer  880  may be used to store logic functions, such as registers used for switching or other operations. Vias  823 ,  835 , such as through-silicon vias (TSVs may extend through the silicon layer  880  and couple to edge vias  422  and bitline vias  424 , respectively. Accordingly, when stacked, the edge vias  422  of a first layer of the stack align with the edge vias of a second layer of the stack and a third layer of the stack, etc., and couple to one another through the silicon  880  by way of the TSVs  823 . The bitline vias  424  of the first layer of the stack align with the bitline vias of the second and third layers, etc., and couple to one another through the silicon  880  by way of the TSVs  825 . Accordingly, the edge vias  422  and bitline vias  424  connect the first level of the stack to the second level to the third level, etc. 
     While the silicon layer  880  is shown as having a particular thickness in proportion to the oxide layers, it should be understood that the thickness of the silicon layer  880  may be varied. For example, a portion of the silicon layer  880  may be selectively removed. 
       FIG. 9  illustrates an example  3 D schematic of a stack  900  including a plurality of 3D-NAND layers where silicon has been retained. Similar to the stack  700  of  FIG. 7 , the elements of the stack as shown in  FIG. 9  are not to scale, or otherwise sized or shaped as they may be in an actual stack, but rather are intended to show the relationship and interconnection of components. Moreover, as shown the stack includes four layers  982 - 988  of 3D-NAND. However, similar to the other examples described above, additional or fewer layers may be included. 
     As shown, each layer  982 - 988  includes a 3D-NAND array  910 , which may include one or more source select layers and one or more drain select layers. Source select layers and drain select layers may be individually routed from the logic layer  970 . 
     A plurality of wordlines  960  are shown in  FIG. 9  for the 3D-NAND array  910 , and a wordline redistribution  965  is further shown. Each stack layer may include a plurality of bitlines  940  and a bitline redistribution  945 . In some examples, the bitline redistribution  945  may be omitted. For example, referring back to the example of  FIG. 5 , where the bitline vias  424  align with the bonding interconnects  430  on the bitlines  440 , bitlines may be coupled to a next layer of a stack through the bitline vias  424 , and therefore bitline redistribution may not be needed. 
     Bonding interconnects  930  may be used to couple each layer  982 - 988  of the stack. For example, bonding interconnects  930  extend between the bitline redistribution  945  of a first layer  982  and the bitlines  940  of a second layer  984 . The connectivity between each of the layers  982 - 988  may be common, for example, if the bitlines  940  of each layer are common. 
     In contrast to the stack  700  of  FIG. 7 , however, the stack  900  of  FIG. 9  may include a shift register [R] in each 3D-NAND array  910 . The shift register [R] may provide for serializing and deserializing data. For example, the shift register [R] can be used as a Serial In Parallel Out (SIPO) register and/or as a Parallel In Serial Out (PISO) register. As such, simultaneous read/write access may be achieved, and a fast clocking rate may be achieved as compared to the stack  700  of  FIG. 7 . 
     The source select layers and drain select layers of each 3D-NAND array  910  may include a switch [S] to select between physical die layers. The logic may also switch for the source select, drain select, and other select layers, as well as the bitlines. 
     Although the invention herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the present invention. It is therefore to be understood that numerous modifications may be made to the illustrative embodiments and that other arrangements may be devised without departing from the spirit and scope of the present invention as defined by the appended claims.