Patent Publication Number: US-2023154919-A1

Title: Protection of a domain of an integrated circuit against overvoltages

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application claims priority to French Application No. 2112211, filed on Nov. 18, 2021, which application is hereby incorporated by reference herein in its entirety. 
     TECHNICAL FIELD 
     The present disclosure generally relates to integrated circuits, and in particular embodiments, to the protection of a domain of the integrated circuit against overvoltages. 
     BACKGROUND 
     Integrated circuits such as microcontrollers generally provide input/output cells allowing the routing of signals between the exterior of the integrated circuit and one or more domains internal to the integrated circuit. A domain of the integrated circuit can be designed to operate under a first voltage but withstand a second maximum voltage greater than the first. However, it is possible that the input/output cell connected to this domain is subjected at least temporarily to a third voltage greater than the second voltage. There is, therefore, a need to protect the domain as effectively as possible against these overvoltages. 
     Moreover, some integrated circuits may provide a high-speed input/output (“High speed I/O”) cell to allow high-speed communication between the outside and the domain. More particularly, this type of input/output cell must, for example, be capable of routing high-frequency signals, of the order of 12 MHz, for example, from a domain of the integrated circuit or towards this domain. There is, therefore, also a need to propose a solution allowing to protect this domain against overvoltages without, however, restricting the transmission of high-frequency signals to or from this domain in operation. 
     SUMMARY 
     According to one aspect, provision is made in this regard of an integrated circuit including at least one input/output cell having a first signal terminal for receiving/transmitting a signal and having a second signal terminal connected to a domain configured to operate under a power supply voltage V 0 , for example, 1.8 volts, and capable of withstanding a maximum voltage V 1 , for example, 3.6 volts, greater than V 0 . 
     The input/output cell includes an array of N diodes, for example, four diodes, connected in series between the second signal terminal and a cold power supply point, typically ground, the array having an overall threshold voltage greater than V 1 . 
     This overall threshold voltage is equal to N times the effective threshold voltage of a diode, this effective threshold voltage taking into account that the diode includes an access resistor. For example, the effective threshold voltage of a “real” diode can be, for example, of the order of 1.1 volts, while the theoretical threshold voltage of an “ideal” diode (without access resistance) is typically of the order of 0.7 volts. 
     The input/output cell also includes a control circuit connected between the first signal terminal and the array of diodes, and configured, in the presence of a voltage V 2 , for example, 5 volts or more, on the first signal terminal greater than the voltage V 1 , to automatically and autonomously short-circuit at least one of the diodes to limit the voltage on the second signal terminal to a value V 3  less than V 1 . 
     “Control circuit configured to automatically and autonomously short-circuit at least one of the diodes” means that the short-circuit of at least one of the diodes of the diode array is performed without the intervention of an activation signal of these control circuit from a circuit external to these control circuit even if the input/output cell is not power supplied, which also allows to ensure protection against electrostatic discharges (ESD: Electro Static Discharge). The activation of the short-circuit mechanism is advantageously only conditioned by the presence of the voltage V 2  on the first signal terminal. Consequently, the value of the voltage V 3  can be determined from the sum of the effective threshold voltages of the diodes not short-circuited by the control circuit. 
     According to one embodiment, the number N is chosen to limit current leaks between the second signal terminal and the cold power supply point below a threshold, for example, 10 nA, during the operation of the domain. 
     Thus, for example, the number of diodes must not be too low to sufficiently limit the leakage current of the domain of the integrated circuit during its operation. 
     The person skilled in the art will know how to choose the number N according to the features of the considered domain of the integrated circuit. 
     According to one embodiment, the control circuit includes a first resistor connected between the first signal terminal and the second signal terminal, a first PMOS transistor, the source and the gate of which are respectively connected to the two terminals of the first resistor and a second NMOS transistor, the gate of which is connected to the drain of the first transistor, the source of which is connected to the cold power supply point by a second resistor, and the drain of which is connected to a node of the diode array located between two consecutive diodes. 
     The first resistor allows having, in the presence of the voltage V 2  on the first signal terminal, a potential difference at these terminals leading to a negative source gate voltage of the first PMOS transistor to turn on this first transistor and have a positive source gate voltage for the second NMOS transistor to turn it on and short-circuit the desired number of diodes. 
     The person skilled in the art will be able to choose the value of the first resistor to obtain, in the presence of the voltage V 2 , a source gate voltage of the first PMOS transistor greater in absolute value than the threshold voltage of the first transistor. 
     Furthermore, using MOS transistors and resistors allows simply achieving the control circuit. 
     According to one embodiment, the control circuit further includes a third resistor connected between the first resistor and the first signal terminal, the source of the first transistor being connected to the node common to the first resistor and the second resistor. 
     Adding a third resistor in the control circuit reduces the voltage between the gate and the source of the first transistor thanks to a “divider bridge” type assembly, which protects the first transistor, in particular for high voltage values V 2 . 
     According to one embodiment, the control circuit includes a fourth resistor connected between the drain of the first transistor and the third resistor, the gate of the second transistor being connected to the node common to the third resistor and the fourth resistor. 
     The addition of a fourth resistor in the control circuit reduces the voltage between the gate and the source of the second transistor thanks to a “divider bridge” type assembly which also allows protection of the second transistor, in particular for high voltage values V 2 . 
     According to one embodiment, the input/output cell further includes a capacitor connected between the first signal terminal and the gate of the second NMOS transistor. 
     It is possible to observe sudden variations in voltage V 2  on the first signal terminal and an exceeding of the maximum voltage value V 1 , which is fast enough not to trigger the short-circuit mechanism quickly enough. The capacitor then allows a voltage to be applied to the gate of the second transistor from the voltage V 2  present on the first signal terminal to activate the short-circuit mechanism very quickly. 
     However, this capacitor forms with the first resistor and, optionally, the third resistor, an RC filter. The person skilled in the art will know how to choose the capacitive value of the capacitor so as not to disturb the transmission of high-speed and high-frequency signals. 
     According to another aspect, provision is made of a method for protecting at least one domain of an integrated circuit against overvoltages, wherein the domain operates under a power supply voltage V 0 , and can withstand a maximum voltage V 1  greater than V 0 , and receives/transmits a signal via a first signal terminal of an input/output cell. 
     An array of N diodes is connected in series inside the cell, between a second signal terminal connected to the domain and a cold power supply point, the array having an overall threshold voltage greater than V 1 , and in the presence of a voltage V 2  on the first signal terminal greater than the voltage V 1 , the cell itself automatically and autonomously short-circuits at least one of the diodes to limit the voltage on the second signal terminal to a value V 3  less than V 1 . 
     According to one embodiment, the number N is chosen to limit the current leaks between the second signal terminal and the cold power supply point below a threshold during the operation of the domain. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       For a more complete understanding of the present disclosure and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which: 
         FIGS.  1 - 4    are diagrams of an embodiment integrated circuit. 
     
    
    
     DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS 
       FIG.  1    illustrates an integrated circuit IC, for example, a microcontroller that includes several input/output cells of which only one referenced CEL is shown for the brevity of discussion. This cell CEL is connected to a domain DV of the integrated circuit IC. The input/output cell CEL includes a first signal terminal E 1 , a second signal terminal ND 3 , and a diode array. 
     The first signal terminal E 1  is used to receive a signal from outside the circuit IC or to transmit a signal from the input/output cell CEL. This signal may be a square signal or a sinusoidal signal, for example, having a defined frequency, for example, 12 MHz. The voltage V 2  of this signal is therefore applied between the first signal terminal E 1  and a cold power supply point GND. The second signal terminal ND 3  is connected to the domain DV configured here to operate at a power supply voltage V 0 , for example, 1.8 volts. 
     However, the domain DV is here capable of withstanding a maximum voltage V 1 , for example, 3.6 volts, greater than V 0 . 
     The diode array may include N diodes, for example, four diodes D 1 , D 2 , D 3 , and D 4  connected in series between the second signal terminal ND 3  and a cold power supply point GND, typically ground, of the cell CEL. 
     The choice of the number N of diodes may depend on the parameters of the circuit during the operation of the domain DV and will therefore be detailed subsequently during the description of  FIG.  2   . 
     The diode array has an overall threshold voltage VTH 0  greater than V 1 , which is here equal to 4 (N=4) times the effective threshold voltage of a diode. The effective threshold voltage takes into account the fact that a diode includes an access resistor (not shown in the figure) and therefore corresponds to the “real” threshold voltage of the diode. The “real” threshold voltage may, for example, be of the order of 1.1 volts, while the theoretical threshold voltage of a diode, that is to say, without access resistance, is typically around 0.7 volts. The overall threshold voltage VTH 0  of the diode array can then be worth, in practice, 4.4 volts instead of 2.8 volts in theory. 
     The input/output cell CEL further includes a control circuit MC connected between the first signal terminal E 1  and the diode array. The control circuit MC includes, in this embodiment, a first resistor R 2  and a first PMOS transistor M 2 . The first resistor R 2  is indirectly connected between the first signal terminal E 1  and the second signal terminal ND 3 . 
     In embodiments, the first resistor R 2  has a terminal VR 21  and a terminal VR 22  connected to the second signal terminal ND 3 . The source S 2  and the gate G 2  of the first transistor M 2  are respectively connected to the terminals VR 21  and VR 22  of the first resistor R 2 . 
     The voltage Vgs 2  between the gate G 2  and the source S 2  of the first transistor M 2  is equal to the potential difference at the terminals of the first resistor R 2 . Depending on the voltage present at the first signal terminal E 1  and the value of the resistor R 2 , the source gate voltage Vgs 2  of the first PMOS transistor M 2  will be less or greater in absolute value than the threshold voltage of the first transistor M 2 . For example, the resistor R 2  is here equal to 113 Ohms. 
     The control circuit also includes a second NMOS transistor M 0  the gate G 0  of which is connected to the drain D 2  of the first transistor M 2  and the source of which is connected to the cold power supply point GND by a second resistor R 4 . The drain D 0  of the second transistor M 0  is connected to a node of the diode array located between two consecutive diodes, for example, the node ND 4  located between the diodes D 2  and D 3 . 
     Thus, the voltage Vgs 0  between the gate G 0  and the source S 0  of the second transistor M 0  is equal to the potential difference at the terminals of the second resistor R 4 . Depending on whether the transistor M 2  is turned on or off and depending on the value of the resistor R 4 , a source gate voltage Vgs 0  of the second NMOS transistor M 0  will be less or greater in absolute value than the threshold voltage of the second transistor M 0 . For example, a resistor R 4  is equal to 86000 Ohms. 
     Furthermore, the control circuit MC can optionally include third and fourth resistors R 1  and R 3 . 
     The third resistor R 1  is connected between the first resistor R 2  and the first signal terminal E 1 . 
     In embodiments, the third resistor R 1  has a terminal VR 11  connected to the first signal terminal E 1  and a terminal VR 12  connected to the terminal VR 21  of the first resistor R 2 . Moreover, the source S 2  of the first transistor M 2  is connected to the common node ND 1  to the first resistor R 2  and to the third resistor R 1 . The fourth resistor R 3  is connected between the drain D 2  of the first transistor M 2  and the second resistor R 4 . 
     In embodiments, the fourth resistor R 3  has a terminal VR 31  connected to the drain D 2  of the first transistor M 2  and a terminal VR 32  connected to the terminal VR 41  of the second resistor R 4 . Moreover, the gate G 0  of the second transistor M 0  is connected to the common node ND 2  to the second resistor R 4  and to the fourth resistor R 3 . 
     The resistors R 1  and R 3 , respectively, lower the voltage at the terminals of the resistor R 2  and the voltage at the terminals of the resistor R 4  thanks to a “divider bridge” type assembly. The values of the resistors R 1  and R 3  are chosen to maintain voltages Vgs 0  and Vgs 2  sufficiently low to protect the transistors M 0  and M 2 , in particular for high voltage values V 2  at the first signal terminal E 1 . 
     In embodiments, the resistor R 1  i 48 Ohms and resistor R 3  is 86000 Ohms. 
     The control circuit MC further includes a capacitor Cbs connected between the first signal terminal E 1  and the gate G 0  of the second transistor M 0 . The operation of the capacitor Cbs will be detailed later in the description in  FIG.  4   . 
       FIGS.  2  to  4    illustrate the integrated circuit IC described previously in relation to  FIG.  1    for different voltage values present at the first signal terminal E 1 . 
       FIG.  2    illustrates the operation of the circuit IC when a voltage V 5  less than the maximum voltage V 1  that the domain DV can withstand is present at the first terminal E 1 . 
     In the presence of a voltage V 5  on the first signal terminal E 1 , the resistors R 1  and R 2  cause a drop in potential, respectively, between the first signal terminal E 1  and the common node ND 1  and between the common node ND 1  and the second signal terminal ND 3 . The voltage Vgs 2  between the gate G 2  and the source S 2  of the first PMOS transistor M 2  is less in absolute value than the threshold voltage of the first PMOS transistor M 2 . Consequently, the first transistor M 2  remains in the off state and does not allow any current to flow between the source S 2  and the drain D 2 . 
     The transistor M 2  prevents current from flowing through the second and fourth resistors R 4  and R 3 , and the potential difference at the terminals of the resistor R 4  is, therefore, zero. The source gate voltage Vgs 0  of the second transistor M 0  is then less in absolute value than the threshold voltage of the second transistor M 0 . Consequently, the transistor M 0  is in the off state and does not allow any current to flow between the drain D 0  and the source S 0 . 
     In other words, the second transistor M 0  does not allow any current to flow between the node ND 4  of the array of diodes located between the diodes D 2  and D 3  and the cold power supply point GND, and the diodes D 3  and D 4  are therefore not short-circuited by the second transistor M 0 . 
     The domain DV has a voltage V 3  at the node ND 3  lower than V 1 . More specifically, the voltage V 3  is less than VTH 0  and the diodes D 1 , D 2 , D 3 , and D 4  of the diode array are therefore in the off state. However, it is known that a diode, even in the off state, is susceptible to leakage current due to its non-ideal features. The number N of diodes is chosen to limit the current leaks between the second signal terminal ND 3  and the cold power supply point GND below a threshold, for example, 10 nA, during the operation of the domain DV. 
     For example, a too low number N of diodes will perhaps allow the normal operation of the domain DV but will not be able to sufficiently limit the leakage current and will then lead to an increase in the power consumption of the circuit IC. Thus, it is advantageous to use in this embodiment four diodes D 1 , D 2 , D 3 , and D 4  to limit the current leaks between the second signal terminal ND 3  and the cold power supply point GND below 10 nA. 
       FIG.  3    illustrates the circuit IC when a voltage V 2  greater than the maximum voltage V 1  that the domain DV can withstand is present at the first signal terminal E 1 . 
     In the presence of such a voltage V 2 , of 5.5 volts, for example, on the first signal terminal E 1 , the resistors R 1  and R 2  cause a drop in potential respectively between the first signal terminal E 1  and the common node ND 1  and between the common node ND 1  and the second signal terminal ND 3 . It is possible to obtain a potential of 4.44 volts on the common node ND 1  and a potential difference between the terminals of the resistor R 2  of 2.36 volts. 
     The voltage Vgs 2  between the gate and the source of the first PMOS transistor M 2 , of the same value as the potential difference at the terminals of the resistor R 2 , then becomes greater in absolute value than the threshold voltage of the first PMOS transistor M 2 . The transistor M 2  then switches from the off state to the on state and a current can flow between the source S 2  and the drain D 2 . A voltage of 4.44 volts is then present at the node ND 5 . 
     The current flowing between the first signal terminal E 1  and the second signal terminal ND 3  flows through the second and fourth resistors R 4  and R 3  by means of the first transistor M 2 , which has the effect of increasing the potential difference between the terminals of the resistors R 3  and R 4 . A potential difference can be obtained between the terminals of the resistor R 4  of 2.22 volts, corresponding to the potential on the common node ND 2 . 
     The voltage Vgs 0  between the gate G 0  and the source S 0  of the second NMOS transistor M 0 , of the same value as the potential difference at the terminals of the resistor R 4 , becomes greater in absolute value than the threshold voltage of the second transistor M 0 . 
     The transistor M 0  switches to the on state and the current at the node ND 4  of the diode array located between the diodes D 2  and D 3  can flow between the drain D 0  and the source S 0  of the transistor M 0 , thus short-circuiting the diodes D 3  and D 4 . 
     Consequently, the diodes D 1  and D 2  turn on and the domain DV has a voltage V 3  between the second signal terminal ND 3  and the cold power supply point GND equal to the sum of the effective threshold voltages VTH 1  of the diodes D 1  and D 2  not short-circuited by the control circuit. It is thus possible to obtain a potential of 2.08 volts on the second signal terminal ND 3 , corresponding to the real value of the threshold voltage VTH 1 . 
     This voltage VTH 1  is less than V 1  (3.6 volts) and the domain DV is consequently protected. 
     The switching of the transistor M 0  occurs only because of the presence of the voltage V 2 , which is located beyond a threshold defined according to the features of the control circuit such as the threshold voltages of the transistors M 2  and M 0  and the values of the resistors R 1  to R 4  previously determined by the person skilled in the art. 
     Therefore, the control circuit is configured to automatically and autonomously short-circuit the diodes D 3  and D 4  to limit the voltage on the second signal terminal ND 3  to a value V 3  less than the voltage V 1 , even in the absence of a power supply. 
     However, in some cases, it is possible to observe sudden variations in the voltage V 2 , in particular for high-frequency signals. 
     The voltage V 2  can then exceed the voltage value V 1  without the switching of the first transistor M 2  having time to occur. The short-circuit mechanism is, therefore, no longer able to be triggered quickly enough to limit the voltage on the second signal terminal ND 3  to a value V 3  less than the voltage V 1 . The capacitor Cbs will overcome this, as illustrated in  FIG.  4   . 
     In the presence of a voltage V 2 , of 5.5 volts, for example, on the first signal terminal E 1 , the capacitor Cbs allows to apply the voltage V 2  directly to the gate G 0  of the second transistor M 0 , (regardless of the state of the first transistor M 2 ) when the control circuit MC only include a resistor R 4 . 
     When the control circuit MC includes the fourth resistor R 3 , the capacitor Cbs allows the application of the voltage V 2  on the common node ND 5  to the transistor M 2  and the resistor R 3 . 
     Taking into account the values of the resistors R 3  and R 4 , in the presence of the voltage V 2  on the common node ND 5 , a source gate voltage Vgs 0  of the second NMOS transistor M 0  is obtained, which is greater in absolute value than the threshold voltage of the second transistor M 0 . Therefore, this results in a switching of the transistor M 0  to the on state and a short-circuit of the diodes D 3  and D 4 . 
     However, the capacitor Cbs forms a low pass filter RC with the equivalent resistance of the resistors R 1  and R 2 . 
     The values of the resistors R 1  and R 2 , as well as the capacitance of the capacitor Cbs are therefore determined according to the frequency of the signal to be routed through the cell CEL so as not to restrict the transmission of high-frequency signals in operation. For a signal frequency of 12 MHz, it is possible to choose, for example, a capacitance of 2 pF and the values of the resistors R 1  and R 2  mentioned above. 
     The input/output cell CEL, therefore, protects the domain DV against overvoltages, even in the absence of a power supply, since it is the only overvoltage present at the first signal terminal E 1  that will trigger the protection mechanism by short-circuiting a chosen number of diodes. 
     In the example which has been described, effective protection is obtained against overvoltages ranging from V 1  (3.6 volts) to a voltage of 5.5 volts, even in the presence of a rapid voltage variation on the terminal E 1 , while maintaining correct operation for high-frequency signals. 
     The values of the various resistors, of the capacitor Cbs and the number of diodes to be short-circuited will be determined by the person skilled in the art when designing the cell CEL according to the voltage V 1  and the overvoltage range for which protection is required. 
     Although the description has been described in detail, it should be understood that various changes, substitutions, and alterations may be made without departing from the spirit and scope of this disclosure as defined by the appended claims. The same elements are designated with the same reference numbers in the various figures. Moreover, the scope of the disclosure is not intended to be limited to the particular embodiments described herein, as one of ordinary skill in the art will readily appreciate from this disclosure that processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, may perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps. 
     The specification and drawings are, accordingly, to be regarded simply as an illustration of the disclosure as defined by the appended claims, and are contemplated to cover any and all modifications, variations, combinations, or equivalents that fall within the scope of the present disclosure.