Patent Publication Number: US-2023145327-A1

Title: Semiconductor device and fabrication method thereof

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a metal resistor used in a semiconductor integrated circuit, and more particularly to a semiconductor device embedded with a metal nitride resistor and a method of manufacturing the same. 
     2. Description of the Prior Art 
     In semiconductor integrated circuits (ICs), a resistor may be used to control the resistance of other electronic components of the IC. 
     Prior art resistors are typically composed of doped polysilicon. As the integration of semiconductor devices increases, each component within a semiconductor IC has to provide equivalent or better electrical properties. A downscaled resistor thus has to provide a constant resistance value that does not fluctuate much during use. However, due to the properties of polysilicon, a prior art resistor comprised of doped polysilicon can only provide a limited resistance within a limited space. Employing a polysilicon resistor to provide relatively tighter resistance tolerances then becomes a problem in designing and fabricating a highly integrated semiconductor device. 
     An embedded titanium nitride (TiN) resistor process has been developed in the 28 nm high-dielectric-constant mid-end process (middle-end-of-line, MEOL), which presents better wafer acceptance test resistance (WAT RS) and uniformity control than traditional doped polysilicon resistors. However, the drawback is that the difference in contact stop depth affects the process window, resulting in a decline in yield. 
     SUMMARY OF THE INVENTION 
     One aspect of the invention provides a semiconductor device including a substrate having a transistor forming region and a resistor forming region thereon; a transistor disposed on the substrate within the transistor forming region; a first inter-layer dielectric (ILD) layer covering the transistor forming region and the resistor forming region and around the transistor; a first etch stop layer disposed on the first ILD layer; a second inter-layer dielectric (ILD) layer disposed on the first etch stop layer; a contact plug in the second ILD layer, the first etch stop layer, and the first ILD layer to electrically connect with a terminal of the transistor; a third inter-layer dielectric (ILD) layer disposed on the second ILD layer; a first metal interconnect layer disposed in the third ILD layer and being electrically connected to the contact plug; a second etch stop layer disposed on the third ILD layer; a resistor disposed on the second etch stop layer within the resistor forming region; a fourth inter-layer dielectric (ILD) layer covering the resistor and the second etch stop layer; and a first via disposed in the fourth ILD layer and being electrically connect with a terminal of the resistor. 
     According to some embodiments, the semiconductor device further includes a second via penetrating through the fourth ILD layer. The second via is disposed within the transistor forming region to electrically connect with the first metal interconnect layer. 
     According to some embodiments, the first via and the second via are damascened copper vias. 
     According to some embodiments, the resistor comprises a patterned titanium nitride layer. 
     According to some embodiments, the semiconductor device further includes a patterned hard mask layer on the patterned titanium nitride layer. 
     According to some embodiments, the fourth ILD layer covers the patterned hard mask layer. 
     According to some embodiments, the patterned hard mask layer is a patterned silicon nitride layer. 
     According to some embodiments, the first via penetrates through the fourth ILD layer and the patterned hard mask layer. 
     According to some embodiments, the contact plug is a tungsten contact plug. 
     According to some embodiments, the first etch stop layer and the second etch stop layer are silicon nitride layers. 
     Another aspect of the invention provides a method for forming a semiconductor device. A substrate having a transistor forming region and a resistor forming region thereon is provided. A transistor is formed on the substrate within the transistor forming region. A first inter-layer dielectric (ILD) layer is formed to cover the transistor forming region and a resistor forming region and is disposed around the transistor. A first etch stop layer is formed on the first ILD layer. A second inter-layer dielectric (ILD) layer is formed on the first etch stop layer. A contact plug is formed in the second ILD layer, the first etch stop layer, and the first ILD layer to electrically connect with a terminal of the transistor. A third inter-layer dielectric (ILD) layer is formed on the second ILD layer. A first metal interconnect layer is formed in the third ILD layer and electrically connected to the contact plug. A second etch stop layer is formed on the third ILD layer. A resistor is formed on the second etch stop layer within the resistor forming region. A fourth inter-layer dielectric (ILD) layer is formed to cover the resistor and the second etch stop layer. A first via is formed in the fourth ILD layer to electrically connect with a terminal of the resistor. 
     According to some embodiments, a second via that penetrates through the fourth ILD layer within the transistor forming region is formed to electrically connect with the first metal interconnect layer. 
     According to some embodiments, the first via and the second via are damascened copper vias. 
     According to some embodiments, the resistor comprises a patterned titanium nitride layer. 
     According to some embodiments, a patterned hard mask layer is formed on the patterned titanium nitride layer. 
     According to some embodiments, the fourth ILD layer covers the patterned hard mask layer. 
     According to some embodiments, the patterned hard mask layer is a patterned silicon nitride layer. 
     According to some embodiments, the first via penetrates through the fourth ILD layer and the patterned hard mask layer. 
     According to some embodiments, the contact plug is a tungsten contact plug. 
     According to some embodiments, the first etch stop layer and the second etch stop layer are silicon nitride layers. 
     These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG.  1    is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention. 
         FIG.  2    and  FIG.  3    are schematic diagrams showing an exemplary method for fabricating a semiconductor device according to an embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION 
     In the following detailed description of the disclosure, reference is made to the accompanying drawings, which form a part hereof, and in which is shown, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. 
     Other embodiments may be utilized, and structural, logical, and electrical changes may be made without departing from the scope of the present invention. Therefore, the following detailed description is not to be considered as limiting, but the embodiments included herein are defined by the scope of the accompanying claims. 
     One feature of the present invention is that the fabrication process of the embedded titanium nitride resistor is changed from the middle-end process (MEOL) to the back-end-of-line (BEOL), and the via connection structure of the embedded titanium nitride resistor and the tungsten plug connection structure of the transistor are in different layers, so when etching the via hole of the embedded titanium nitride resistor, there is a relatively larger tolerance for process differences, thereby increasing the etching process window of the contact plug and improved yield. 
     Please refer to  FIG.  1   , which is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention. As shown in  FIG.  1   , the semiconductor device  1  includes a substrate  100  having a transistor forming region TR and a resistor forming region HIR. According to an embodiment of the present invention, the substrate  100  may be a silicon substrate, but is not limited thereto. A transistor T is formed on the substrate  100  in the transistor forming region TR. According to an embodiment of the present invention, the transistor T may include a gate TG, a source doped region TS, and a drain doped region TD. According to an embodiment of the present invention, for example, the gate TG may be a metal gate. According to an embodiment of the present invention, the gate TG may be surrounded by the contact etch stop layer  110  and the interlayer dielectric layer  120 . 
     According to an embodiment of the present invention, for example, the contact etch stop layer  110  may be a silicon nitride layer, and the interlayer dielectric layer  120  may be a silicon oxide layer or a low dielectric constant material layer, but is not limited thereto. According to an embodiment of the present invention, the top surface of the gate TG is flush with the top surface of the interlayer dielectric layer  120 . 
     According to an embodiment of the present invention, the resistor forming region HIR is directly located on the trench isolation structure  102  of the substrate  100 . According to an embodiment of the present invention, a semiconductor structure TP may be formed on the trench isolation structure  102 , for example, a passing gate. 
     According to an embodiment of the present invention, the interlayer dielectric layer  120  covers the transistor forming region TR and the resistor forming region HIR and surrounds the transistor T. An etch stop layer  130  is formed on the interlayer dielectric layer  120 . According to an embodiment of the present invention, for example, the etch stop layer  130  may be a silicon nitride layer. An interlayer dielectric layer  140  is formed on the etch stop layer  130 . According to an embodiment of the present invention, for example, the interlayer dielectric layer  140  may be a silicon oxide layer or a low dielectric constant material layer, but is not limited thereto. 
     According to an embodiment of the present invention, contact plugs CP 1  to CP 3  are formed in the interlayer dielectric layer  140 , the etch stop layer  130 , and the interlayer dielectric layer  120 , which are respectively electrically connected to the terminals of the transistor T: the gate TG, the source doped region TS and the drain doped region TD. According to an embodiment of the present invention, the contact plugs CP 1  to CP 3  are tungsten metal contact plugs. The contact plug CP 1  penetrates through the interlayer dielectric layer  140  and the etch stop layer  130  and is electrically connected to the gate TG of the transistor T. The contact plug CP 2  penetrates through the interlayer dielectric layer  140 , the etch stop layer  130 , the interlayer dielectric layer  120  and the contact etch stop layer  110  and is electrically connected to the source doped region TS of the transistor T. The contact plug CP 3  penetrates through the interlayer dielectric layer  140 , the etch stop layer  130 , the interlayer dielectric layer  120  and the contact etch stop layer  110 , and is electrically connected to the drain doped region TD of the transistor T. 
     According to an embodiment of the present invention, an interlayer dielectric layer  160  is formed on the interlayer dielectric layer  140 . According to an embodiment of the present invention, metal interconnection layers IM 1 ˜IM 3  are formed in the interlayer dielectric layer  160 . The metal interconnection layers IM 1 ˜IM 3  are disposed in the first metal layer and are electrically connected to the contact plugs CP 1 ˜CP 3 , respectively. According to an embodiment of the present invention, an etch stop layer  170  is formed on the interlayer dielectric layer  160 . According to an embodiment of the present invention, the etch stop layer  130  and the etch stop layer  170  are silicon nitride layers. 
     According to an embodiment of the present invention, a resistor  200  is formed on the etch stop layer  170  in the resistor forming region HIR. According to an embodiment of the present invention, the resistor  200  includes a patterned titanium nitride layer  201 . According to some embodiments of the present invention, the resistor  200  may include other high-resistance materials. According to an embodiment of the present invention, the patterned titanium nitride layer  201  directly contacts the etch stop layer  170 . According to an embodiment of the present invention, the semiconductor device  1  further includes a patterned hard mask layer  202  on the patterned titanium nitride layer  201 . According to an embodiment of the present invention, the patterned hard mask layer  202  is a patterned silicon nitride layer. According to some embodiments of the present invention, after the patterned titanium nitride layer  201  is formed, the patterned hard mask layer  202  may be removed. 
     According to an embodiment of the present invention, an interlayer dielectric layer  180  is further formed on the substrate  100  to cover the resistor  200  and the etch stop layer  170 . According to an embodiment of the present invention, the interlayer dielectric layer  180  covers the patterned hard mask layer  202 . According to an embodiment of the present invention, for example, the interlayer dielectric layer  180  may be a silicon oxide layer or a low dielectric constant material layer, but is not limited thereto. According to an embodiment of the present invention, vias V 1  are formed in the interlayer dielectric layer  180  and are electrically connected to terminals  200   a  of the resistor  200 . According to an embodiment of the present invention, the vias V 1  penetrate through the interlayer dielectric layer  180  and the patterned hard mask layer  202 . 
     According to an embodiment of the present invention, the semiconductor device  1  further includes metal interconnection layers ML and vias V 2 , which penetrate through the interlayer dielectric layer  180 . The metal interconnection layers ML are disposed in the second metal layer. The metal interconnection layers ML and the vias V 2  are located in the transistor forming region TR and are electrically connected to the metal interconnection layers IM 1 -IM 3 , respectively. According to an embodiment of the present invention, the vias V 1  and the vias V 2  are damascened copper vias. 
     Those skilled in the art should understand that the position of the resistor  200  in  FIG.  1    is for illustration purpose only.  FIG.  1    illustrates that the vias V 1  of the resistor  200  and the vias V 2  of the second metal layer (M 2 ) are made at the same time. However, in some embodiments, the resistor  200  may be disposed in a higher interlayer dielectric layer. For example, the vias V 1  of the resistor  200  and the vias (not shown) of the third metal layer (M 3 ) are made at the same time. The vias of the resistor and the tungsten plug of the transistor are in different layers, so when forming the vias of the embedded titanium nitride resistor, there is a relatively larger tolerance for process differences. 
     Please refer to  FIG.  2    and  FIG.  3   , which are schematic diagrams of the manufacturing method of the semiconductor device according to an embodiment of the present invention. As shown in  FIG.  2   , first, a substrate  100  having a transistor forming region TR and a resistor forming region HIR is provided. A transistor T is formed on the substrate  100  in the transistor forming region TR. After the replacement metal gate (RMG) process and the chemical mechanical polishing (CMP) process, the interlayer dielectric layer  120  covers the transistor forming region TR and the resistor forming region HIR and surrounds the gate TG of the transistor T. 
     Next, an etch stop layer  130  is formed on the interlayer dielectric layer  120 . Then, an interlayer dielectric layer  140  is formed on the etch stop layer  130 . Contact plugs CP 1 -CP 3  are formed in the interlayer dielectric layer  140 , the etch stop layer  130 , and the interlayer dielectric layer  120 , which are respectively electrically connected to the terminals of the transistor T: the gate TG, the source doped region TS, and the drain doped region TD. According to an embodiment of the present invention, the contact plugs CP 1 ˜CP 3  are tungsten metal contact plugs. An interlayer dielectric layer  160  is then formed on the interlayer dielectric layer  140 . Metal interconnection layers IM 1 ˜IM 3  are formed in the interlayer dielectric layer  160  to electrically connect the contact plugs CP 1 ˜CP 3 , respectively. An etch stop layer  170  is formed on the interlayer dielectric layer  160 . According to an embodiment of the present invention, the etch stop layer  130  and the etch stop layer  170  are silicon nitride layers. 
     As shown in  FIG.  3   , a resistor  200  is formed on the etch stop layer  170  in the resistor forming region HIR. For example, the method of forming the resistor  200  includes depositing a titanium nitride layer in a blanket manner, and then patterning the titanium nitride layer by using a lithographic process and an etching process. According to an embodiment of the present invention, the resistor  200  includes a patterned titanium nitride layer  201 . According to an embodiment of the present invention, the resistor  20  further includes a patterned hard mask layer  202  on the patterned titanium nitride layer  201 . According to an embodiment of the present invention, the patterned hard mask layer  202  is a patterned silicon nitride layer. 
     After the resistor  200  is formed, an interlayer dielectric layer  180  is deposited to cover the resistor  200  and the etch stop layer  170 . Then, vias V 1  are formed in the interlayer dielectric layer  180  and the vias V 1  are electrically connected to the terminals  200   a  of the resistor  200 . According to an embodiment of the present invention, the vias V 1  penetrates through the interlayer dielectric layer  180  and the patterned hard mask layer  202 . According to an embodiment of the present invention, the interlayer dielectric layer  180  covers the patterned hard mask layer  202 . 
     According to an embodiment of the present invention, vias V 2  penetrating the interlayer dielectric layer  180  are formed in the transistor forming region TR and are electrically connected to the metal interconnection layers IM 1 ˜IM 3 . The vias V 1 , the vias V 2 , and the metal interconnection layer ML can be formed in the interlayer dielectric layer  180  through a dual damascene copper process. According to an embodiment of the present invention, the vias V 1  and the vias V 2  are damascened copper vias. Since the vias V 1  of the resistor  200  and the contact plugs CP 1 ˜CP 3  of the transistor are in different layers, when the vias of the resistor  200  is etched, there can be a relatively larger tolerance for process differences. 
     Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.