Patent Publication Number: US-9886934-B2

Title: Ordering mechanism for offload graphics scheduling

Description:
BACKGROUND 
     In a computing device, graphics data are typically provided by a central processing unit (CPU). The CPU may be part of a general computing architecture. The CPU may be involved in “processor-to-processor” multi-tasking techniques to process/render graphics. In particular, the CPU communicates and hands graphics data to a graphics processing unit (GPU), and the GPU renders (processes) the graphics data. The hand off between CPU and GPU may make use of semaphores, where semaphores are a variable or abstract type used for controlling access for multiple processes (i.e., multi-tasking). 
     The CPU may offload or send the graphics data for processing to memory, like dynamic random access memory (DRAM) for example. The hand off between CPU and GPU using semaphores, may rely on the graphics data being produced and consumed from the same memory (i.e., DRAM). The GPU accesses memory (i.e. DRAM) to receive the graphics data. This type of offload graphics command scheduling may involve sending command lists into a non-coherent memory (fabric) through memory mapped (MMIO) access. The non-coherent memory may then use a graphics translation table to translate the MMIO address to a DRAM address. The resulting translated access will be redirected to DRAM using the translated address. The non-coherent memory (fabric) may be considered as a “first space.” Coherent memory (fabric) is then used to notify the GPU, or a command scheduling graphics microcontroller of the GPU, that there is new work/graphics data to schedule. The coherent memory (fabric) may be considered as a “second space.” Because the new work notification occurs through coherent memory (fabric), and not non-coherent memory (fabric), a method is needed to ensure that the command list has been pushed from non-coherent memory MMIO memory back to DRAM before scheduling the work. 
     The command list is produced or sent to one space (i.e., non-coherent memory or fabric), but graphics data is consumed by the GPU in another space (coherent memory). Because two different spaces are involved for the command list, when the control is passed from CPU to GPU, the command list is not guaranteed to be visible via the coherent memory (i.e., coherent DRAM). 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  illustrates an example block diagram of a system or computing device used in accordance with implementations described herein. 
         FIG. 2  illustrates an example block diagram of a graphics processing unit (GPU) used in accordance with implementations described herein. 
         FIG. 3  illustrates block diagram of graphics steering component or unit used in accordance with implementations described herein. 
         FIG. 4  illustrates example flowchart illustrating an example method for token comparison for context/graphics scheduling as described herein. 
         FIG. 5  illustrates an example flowchart illustrating an example method for a coherent communication interrupt/doorbell ring scheduling as described herein. 
         FIG. 6  is a block diagram of a data processing system according to an embodiment. 
         FIG. 7  is a block diagram of an embodiment of a processor having one or more processor cores, an integrated memory controller, and an integrated graphics processor. 
         FIG. 8  is a block diagram of one embodiment of a graphics processor which may be a discrete graphics processing unit, or may be graphics processor integrated with a plurality of processing cores. 
         FIG. 9  is a block diagram of an embodiment of a graphics processing engine for a graphics processor. 
         FIG. 10  is a block diagram of another embodiment of a graphics processor. 
         FIG. 11  illustrates thread execution logic including an array of processing elements employed in one embodiment of a graphics processing engine. 
         FIG. 12  is a block diagram illustrating a graphics processor execution unit instruction format according to an embodiment. 
         FIG. 13  is a block diagram of another embodiment of a graphics processor which includes a graphics pipeline, a media pipeline, a display engine, thread execution logic, and a render output pipeline. 
         FIG. 14A  is a block diagram illustrating a graphics processor command format according to an embodiment and  FIG. 14B  is a block diagram illustrating a graphics processor command sequence according to an embodiment. 
         FIG. 15  illustrates exemplary graphics software architecture for a data processing system according to an embodiment. 
     
    
    
     DETAILED DESCRIPTION 
     Described herein are technologies to assure that command lists, such as used in memory mapped (MMIO) access, are pushed to non-coherent memory (fabric). A token based handshake may be implemented to assure the command list is pushed through the non-coherent memory (fabric) back to DRAM. A graphics scheduling engine or microcontroller, may issue a token based on a send or push command. A graphics steering component (unit) residing in non-coherent memory (fabric) sends a token based on a response to sending or pushing a command, back to the scheduling engine or microcontroller. Once the response to sending or pushing a command is received by the scheduling engine or microcontroller, graphics data from the DRAM residing in coherent memory (fabric) may be processed. 
       FIG. 1  is an example block diagram of a system or computing device  100  that may be used in accordance with implementations described herein. The computing device  100  may include a central processing unit (CPU)  102 . CPU  102  may be part of a central processing architecture of computing device  100 . CPU  102  may be tasked to perform tasks, other than graphics processing; however, CPU  102  may receive and pass on graphics data, and perform graphics scheduling by passing graphics commands (i.e., command lists). 
     The computing device  100  may further include a graphics processing unit (GPU)  104 . GPU  104  may be configured to receive and process graphics commands/lists and graphics data. Computing device  100  may include coherent memory (fabric)  106 , which may include cache memory  108 . Computing device  100  may include non-coherent memory (fabric)  110 , which may include a non-coherent graphics steering component or unit (graphics steering unit)  112 . The computing device  100  may include a dynamic access random memory (DRAM) or other type of main memory  114 . Communication connections  116  show example data channels between the elements of computer device  100 . The communications connections  116  show flow of data such as commands, tokens, and graphics data. It is to be understood that the described one or more components of  FIG. 1  may be integrated with one another as part of a system on a chip or SOC. For example, as part of a graphics SOC. 
       FIG. 2  shows an example block diagram of a graphics processing unit (GPU)  104 . The GPU  104  includes a graphics renderer  200  to process received graphics data. A graphics media component  202  represents graphics data for processing. GPU  104  includes coherent cache memory  204 . A scheduling microcontroller  206  that includes a “PushAp” response register  208 . “PushAp” is a command to push or send graphics data. “PushAp” may be triggered by CPU  102  (of  FIG. 1 ) after work has been sent by CPU  102 . GPU  104 . The “PushAp” response register  208  may be used to keep track of such work. 
       FIG. 3  shows an example block diagram of a non-coherent graphics steering component or unit (graphics steering unit)  112 . The graphics steering unit  112  includes a “PushAp” register  300 . The “PushAp” register  300  receives “PushAp” commands from CPU  102  and then sends a “PushAp” response command to GPU  104 . 
     Graphics steering unit  112  further includes a register access component  302  used for non-coherent memory access, such as used for non-coherent memory mapped (MMIO) access or accessing other types of registers. A graphics aperture translation component  304  used to translate non-coherent memory mapped (MMIO) addresses to DRAM (e.g., DRAM  114 ) addresses. 
     Referring back now to  FIG. 1 . The CPU  102  performs a write, which combines write(s) targeting non-coherent graphics commands (i.e., aperture). An instruction from CPU  102  is performed to ensure that non-coherent graphics commands (i.e., aperture) are flushed from CPU  102  and forwarded to the non-coherent memory (fabric)  110 . 
     The CPU  102  initiates a write back (WB) “doorbell ring” through the coherent memory (fabric)  106 . The WB doorbell ring, through coherent memory (fabric)  106  notifies GPU  104  that new work is to be scheduled/consumed. 
     The GPU  104  issues a non-coherent write token that is targeted for the “PushAp” register  300 . The write token may have an incrementing value that provides that non-coherent graphics apertures/command writes are globally observed in the DRAM  114 . Access to the “PushAp” register  300 , and particularly the write token may first appear on a coherent communication interface (e.g., IDI) then pass through the non-coherent memory (fabric)  110 . Non-coherent memory (fabric)  110  ordering rules ensure the graphics aperture writes are pushed by the “PushAp” register access to the graphics steering unit  112  which resides on non-coherent memory (fabric)  110 . 
     Once the “PushAp” register write is issued, the GPU  104  is free to do other work, while waiting for any response feedback. The same token value is available (in memory) as part of the workload. 
     Write tokens to the “PushAp” register  300  may be allowed to continuously update; however, implementations may provide that the latest value is always returned. For example, the GPU  104  may issue two writes (tokens), the first write (token) with a value of “1” and the second with a value of “2.” If collapsing occurs, the response (response token) “PushAp Response” register write will have the value of “2.” 
     The graphics steering unit  112  receives a “PushAp” token update, and the will trigger a “PushAp Response” message. This allows the graphics steering unit  112  to return a response token value and notify the GPU  104  that aperture (command) writes are available in DRAM  114 . The standard ordering rules implemented by the graphics steering unit  112  ensures that the non-coherent “PushAp” write token pushes the non-coherent aperture (command) writes. 
     In an implementation, a graphics command will compare a “context token” against the “PushAp Response” token in the “PushAp” response register  208  of GPU  104 . For example, if a context token value is less than or equal to a token value in the “PushAp” response register  208  of GPU  104 , then the context is may be executed. If the context token value is greater than a token value in the “PushAp” response register  208  of GPU  104 , then a loop can take place allowing the token value to be updated. 
     In certain implementations, rollover handling may take place. For example, a token value may be derived from a  32  bit incrementing counter at the GPU  104 . The GPU  104  may prevent boundary cases, around rollover when the token value reaches the maximum value. 
       FIG. 4  shows an example process flowchart  400  illustrating an example method for context/graphics token comparison for context/graphics scheduling as described herein. The order in which the method is described is not intended to be construed as a limitation, and any number of the described method blocks may be combined in any order to implement the method, or alternate method. Additionally, individual blocks may be deleted from the method without departing from the spirit and scope of the subject matter described herein. Furthermore, the method may be implemented in any suitable hardware, software, firmware, or a combination thereof, without departing from the scope of the invention. 
     At block  402 , inserting a graphics command is performed. The graphics command may be provided by a graphics driver running on a CPU of a device, (e.g., CPU  102 ) 
     The graphics command will wait for a context or graphics token to have a value less than the value of a context or graphics token in register in a graphics processing unit (e.g., GPU  104 ). For example, the register is the “PushAp” response register  208  of GPU  104 . 
     If the context or graphics token has a value less than or equal to the value of a context or graphics token in the register, then following the YES branch of block  404 , at block  406 , the context or graphics is executed. 
     If the context or graphics token does not have a value less than or equal to the value of a context or graphics token in the register, then following the NO branch of block  404 , at block  408 , a coherent transaction is performed. The GPU receives the coherent transaction that results in a doorbell from the CPU indicating context/graphics are available. 
     At block  410 , writing a new token value (i.e. an incremented token value) is performed and the context token (value) is updated (which is to be compared again at block  404 ). The GPU (e.g., GPU  104 ) may perform the writing and updating. 
     At block  412 , scheduling context/graphics is performed. The GPU (e.g., GPU  104 ) may perform the scheduling. 
     At block  414 , flushing/sending graphics apertures (commands) from memory is performed. The graphics steering unit (e.g., graphics steering unit  112 ) may perform the sending. 
     At block  416 , returning the updated context token (value) to the register in a graphics processing unit (e.g., GPU  104 ) is performed. For example, the register is the “PushAp” response register  208  of GPU  104 . 
       FIG. 5  shows an example process flowchart  500  illustrating an example method for a coherent communication interrupt or doorbell ring scheduling as described herein. The order in which the method is described is not intended to be construed as a limitation, and any number of the described method blocks may be combined in any order to implement the method, or alternate method. Additionally, individual blocks may be deleted from the method without departing from the spirit and scope of the subject matter described herein. Furthermore, the method may be implemented in any suitable hardware, software, firmware, or a combination thereof, without departing from the scope of the invention. 
     At block  502 , providing an instruction for a non-coherent write to target graphics aperture (command) is performed. The providing may be performed by the CPU (e.g., CPU  102 ). 
     At block  504 , sending a command that flushes/sends non-coherent graphics aperture writes to non-coherent memory is performed. The sending may be performed by the CPU (e.g., CPU  102 ). 
     At block  506 , providing a coherent “write-back” transaction in the form of a doorbell ring is performed. The providing may be performed by the CPU (e.g., CPU  102 ). 
     At block  508 , writing a non-coherent Push Graphics Aperture or “PushAp” token is performed. The writing may be performed by a scheduling microcontroller of the GPU (e.g., scheduling microcontroller  206  of GPU  104 ). 
     At block  510 , writing a non-coherent “PushAp Response” token is performed. The graphics steering unit  112  may perform the writing. The non-coherent “PushAp” response token may be sent to the scheduling microcontroller of the GPU (e.g., scheduling microcontroller  206  of GPU  104 ). 
     At block  512 , comparing the context/graphics non-coherent Push Graphics Aperture or “PushAp” token with the non-coherent “PushAp” response token is performed. The comparison result determines whether the context/graphics may execute or whether to wait for an updated “PushAp Response” token. 
     Overview— FIGS. 6-9   
       FIG. 6  is a block diagram of a data processing system  600 , according to an embodiment. The data processing system  600  includes one or more processors  602  and one or more graphics processors  608 , and may be a single processor desktop system, a multiprocessor workstation system, or a server system having a large number of processors  602  or processor cores  607 . In on embodiment, the data processing system  600  is a system on a chip integrated circuit (SOC) for use in mobile, handheld, or embedded devices. 
     An embodiment of the data processing system  600  can include, or be incorporated within a server-based gaming platform, a game console, including a game and media console, a mobile gaming console, a handheld game console, or an online game console. In one embodiment, the data processing system  600  is a mobile phone, smart phone, tablet computing device or mobile Internet device. The data processing system  600  can also include, couple with, or be integrated within a wearable device, such as a smart watch wearable device, smart eyewear device, augmented reality device, or virtual reality device. In one embodiment, the data processing system  600  is a television or set top box device having one or more processors  602  and a graphical interface generated by one or more graphics processors  608 . 
     The one or more processors  602  each include one or more processor cores  607  to process instructions which, when executed, perform operations for system and user software. In one embodiment, each of the one or more processor cores  607  is configured to process a specific instruction set  609 . The instruction set  609  may facilitate complex instruction set computing (CISC), reduced instruction set computing (RISC), or computing via a very long instruction word (VLIW). Multiple processor cores  607  may each process a different instruction set  609  which may include instructions to facilitate the emulation of other instruction sets. A processor core  607  may also include other processing devices, such a digital signal processor (DSP). 
     In one embodiment, the processor  602  includes cache memory  604 . Depending on the architecture, the processor  602  can have a single internal cache or multiple levels of internal cache. In one embodiment, the cache memory is shared among various components of the processor  602 . In one embodiment, the processor  602  also uses an external cache (e.g., a Level 3 (L3) cache or last level cache (LLC)) (not shown) which may be shared among the processor cores  607  using known cache coherency techniques. A register file  606  is additionally included in the processor  602  which may include different types of registers for storing different types of data (e.g., integer registers, floating point registers, status registers, and an instruction pointer register). Some registers may be general-purpose registers, while other registers may be specific to the design of the processor  602 . 
     The processor  602  is coupled to a processor bus  610  to transmit data signals between the processor  602  and other components in the system  600 . The system  600  uses an exemplary ‘hub’ system architecture, including a memory controller hub  616  and an input output (I/O) controller hub  630 . The memory controller hub  616  facilitates communication between a memory device and other components of the system  600 , while the I/O controller hub (ICH)  630  provides connections to I/O devices via a local I/O bus. 
     The memory device  620 , can be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, flash memory device, or some other memory device having suitable performance to serve as process memory. The memory  620  can store data  622  and instructions  621  for use when the processor  602  executes a process. The memory controller hub  616  also couples with an optional external graphics processor  612 , which may communicate with the one or more graphics processors  608  in the processors  602  to perform graphics and media operations. 
     The ICH  630  enables peripherals to connect to the memory  620  and processor  602  via a high-speed I/O bus. The I/O peripherals include an audio controller  646 , a firmware interface  628 , a wireless transceiver  626  (e.g., Wi-Fi, Bluetooth), a data storage device  624  (e.g., hard disk drive, flash memory, etc.), and a legacy I/O controller for coupling legacy (e.g., Personal System 2 (PS/2)) devices to the system. One or more Universal Serial Bus (USB) controllers  642  connect input devices, such as keyboard and mouse  644  combinations. A network controller  634  may also couple to the ICH  630 . In one embodiment, a high-performance network controller (not shown) couples to the processor bus  610 . 
       FIG. 7  is a block diagram of an embodiment of a processor  700  having one or more processor cores  702 A-N, an integrated memory controller  714 , and an integrated graphics processor  708 . The processor  700  can include additional cores up to and including additional core  702 N represented by the dashed lined boxes. Each of the cores  702 A-N includes one or more internal cache units  704 A-N. In one embodiment each core also has access to one or more shared cached units  706 . 
     The internal cache units  704 A-N and shared cache units  706  represent a cache memory hierarchy within the processor  700 . The cache memory hierarchy may include at least one level of instruction and data cache within each core and one or more levels of shared mid-level cache, such as a level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache, where the highest level of cache before external memory is classified as the last level cache (LLC). In one embodiment, cache coherency logic maintains coherency between the various cache units  706  and  704 A-N. 
     The processor  700  may also include a set of one or more bus controller units  716  and a system agent  710 . The one or more bus controller units manage a set of peripheral buses, such as one or more Peripheral Component Interconnect buses (e.g., PCI, PCI Express). The system agent  710  provides management functionality for the various processor components. In one embodiment, the system agent  710  includes one or more integrated memory controllers  714  to manage access to various external memory devices (not shown). 
     In one embodiment, one or more of the cores  702 A-N include support for simultaneous multi-threading. In such embodiment, the system agent  710  includes components for coordinating and operating cores  702 A-N during multi-threaded processing. The system agent  710  may additionally include a power control unit (PCU), which includes logic and components to regulate the power state of the cores  702 A-N and the graphics processor  708 . 
     The processor  700  additionally includes a graphics processor  708  to execute graphics processing operations. In one embodiment, the graphics processor  708  couples with the set of shared cache units  706 , and the system agent unit  710 , including the one or more integrated memory controllers  714 . In one embodiment, a display controller  711  is coupled with the graphics processor  708  to drive graphics processor output to one or more coupled displays. The display controller  711  may be separate module coupled with the graphics processor via at least one interconnect, or may be integrated within the graphics processor  708  or system agent  710 . 
     In one embodiment a ring based interconnect unit  712  is used to couple the internal components of the processor  700 , however an alternative interconnect unit may be used, such as a point to point interconnect, a switched interconnect, or other techniques, including techniques well known in the art. In one embodiment, the graphics processor  708  couples with the ring interconnect  712  via an I/O link  713 . 
     The exemplary I/O link  713  represents at least one of multiple varieties of I/O interconnects, including an on package I/O interconnect which facilitates communication between various processor components and a high-performance embedded memory module  718 , such as an eDRAM module. In one embodiment each of the cores  702 -N and the graphics processor  708  use the embedded memory modules  718  as shared last level cache. 
     In one embodiment cores  702 A-N are homogenous cores executing the same instruction set architecture. In another embodiment, the cores  702 A-N are heterogeneous in terms of instruction set architecture (ISA), where one or more of the cores  702 A-N execute a first instruction set, while at least one of the other cores executes a subset of the first instruction set or a different instruction set. 
     The processor  700  can be a part of or implemented on one or more substrates using any of a number of process technologies, for example, Complementary metal-oxide-semiconductor (CMOS), Bipolar Junction/Complementary metal-oxide-semiconductor (BiCMOS) or N-type metal-oxide-semiconductor logic (NMOS). Additionally, the processor  700  can be implemented on one or more chips or as a system on a chip (SOC) integrated circuit having the illustrated components, in addition to other components. 
       FIG. 8  is a block diagram of one embodiment of a graphics processor  800  which may be a discreet graphics processing unit, or may be graphics processor integrated with a plurality of processing cores. In one embodiment, the graphics processor is communicated with via a memory mapped I/O interface to registers on the graphics processor and via commands placed into the processor memory. The graphics processor  800  includes a memory interface  814  to access memory. The memory interface  814  can be an interface to local memory, one or more internal caches, one or more shared external caches, and/or to system memory. 
     The graphics processor  800  also includes a display controller  802  to drive display output data to a display device  820 . The display controller  802  includes hardware for one or more overlay planes for the display and composition of multiple layers of video or user interface elements. In one embodiment the graphics processor  800  includes a video codec engine  806  to encode, decode, or transcode media to, from, or between one or more media encoding formats, including, but not limited to Moving Picture Experts Group (MPEG) formats such as MPEG-, Advanced Video Coding (AVC) formats such as H.264/MPEG-4 AVC, as well as the Society of Motion Picture &amp; Television Engineers (SMPTE) 421M/VC-1, and Joint Photographic Experts Group (JPEG) formats such as JPEG, and Motion JPEG (MJPEG) formats. 
     In one embodiment, the graphics processor  800  includes a block image transfer (BLIT) engine  804  to perform two-dimensional (2D) rasterizer operations including, for example, bit-boundary block transfers. However, in one embodiment, 2D graphics operations are performed using one or more components of the graphics-processing engine (GPE)  810 . The graphics-processing engine  810  is a compute engine for performing graphics operations, including three-dimensional (8D) graphics operations and media operations. 
     The GPE  810  includes a 8D pipeline  812  for performing 8D operations, such as rendering three-dimensional images and scenes using processing functions that act upon 3D primitive shapes (e.g., rectangle, triangle, etc.). The 3D pipeline  812  includes programmable and fixed function elements that perform various tasks within the element and/or spawn execution threads to a 3D/Media sub-system  815 . While the 3D pipeline  812  can be used to perform media operations, an embodiment of the GPE  810  also includes a media pipeline  816  that is specifically used to perform media operations, such as video post processing and image enhancement. 
     In one embodiment, the media pipeline  816  includes fixed function or programmable logic units to perform one or more specialized media operations, such as video decode acceleration, video de-interlacing, and video encode acceleration in place of, or on behalf of the video codec engine  806 . In on embodiment, the media pipeline  816  additionally includes a thread spawning unit to spawn threads for execution on the 3D/Media sub-system  815 . The spawned threads perform computations for the media operations on one or more graphics execution units included in the 3D/Media sub-system. 
     The 3D/Media subsystem  815  includes logic for executing threads spawned by the 3D pipeline  812  and media pipeline  816 . In one embodiment, the pipelines send thread execution requests to the 3D/Media subsystem  815 , which includes thread dispatch logic for arbitrating and dispatching the various requests to available thread execution resources. The execution resources include an array of graphics execution units to process the 3D and media threads. In one embodiment, the 3D/Media subsystem  815  includes one or more internal caches for thread instructions and data. In one embodiment, the subsystem also includes shared memory, including registers and addressable memory, to share data between threads and to store output data. 
     3D/Media Processing— FIG. 9   
       FIG. 9  is a block diagram of an embodiment of a graphics processing engine  910  for a graphics processor. In one embodiment, the graphics processing engine (GPE)  910  is a version of the GPE  310  shown in  FIG. 3 . The GPE  910  includes a 3D pipeline  912  and a media pipeline  916 , each of which can be either different from or similar to the implementations of the 3D pipeline  312  and the media pipeline  316  of  FIG. 3 . 
     In one embodiment, the GPE  910  couples with a command streamer  903 , which provides a command stream to the GPE 3D and media pipelines  912 ,  916 . The command streamer  903  is coupled to memory, which can be system memory, or one or more of internal cache memory and shared cache memory. The command streamer  903  receives commands from the memory and sends the commands to the 3D pipeline  912  and/or media pipeline  916 . The 3D and media pipelines process the commands by performing operations via logic within the respective pipelines or by dispatching one or more execution threads to the execution unit array  914 . In one embodiment, the execution unit array  914  is scalable, such that the array includes a variable number of execution units based on the target power and performance level of the GPE  910 . 
     A sampling engine  930  couples with memory (e.g., cache memory or system memory) and the execution unit array  914 . In one embodiment, the sampling engine  930  provides a memory access mechanism for the scalable execution unit array  914  that allows the execution array  914  to read graphics and media data from memory. In one embodiment, the sampling engine  930  includes logic to perform specialized image sampling operations for media. 
     The specialized media sampling logic in the sampling engine  930  includes a de-noise/de-interlace module  932 , a motion estimation module  934 , and an image scaling and filtering module  936 . The de-noise/de-interlace module  932  includes logic to perform one or more of a de-noise or a de-interlace algorithm on decoded video data. The de-interlace logic combines alternating fields of interlaced video content into a single fame of video. The de-noise logic reduces or remove data noise from video and image data. In one embodiment, the de-noise logic and de-interlace logic are motion adaptive and use spatial or temporal filtering based on the amount of motion detected in the video data. In one embodiment, the de-noise/de-interlace module  932  includes dedicated motion detection logic (e.g., within the motion estimation engine  934 ). 
     The motion estimation engine  934  provides hardware acceleration for video operations by performing video acceleration functions such as motion vector estimation and prediction on video data. The motion estimation engine determines motion vectors that describe the transformation of image data between successive video frames. In one embodiment, a graphics processor media codec uses the video motion estimation engine  934  to perform operations on video at the macro-block level that may otherwise be computationally intensive to perform using a general-purpose processor. In one embodiment, the motion estimation engine  934  is generally available to graphics processor components to assist with video decode and processing functions that are sensitive or adaptive to the direction or magnitude of the motion within video data. 
     The image scaling and filtering module  936  performs image-processing operations to enhance the visual quality of generated images and video. In one embodiment, the scaling and filtering module  936  processes image and video data during the sampling operation before providing the data to the execution unit array  914 . 
     In one embodiment, the graphics processing engine  910  includes a data port  944 , which provides an additional mechanism for graphics subsystems to access memory. The data port  944  facilitates memory access for operations including render target writes, constant buffer reads, scratch memory space reads/writes, and media surface accesses. In one embodiment, the data port  944  includes cache memory space to cache accesses to memory. The cache memory can be a single data cache or separated into multiple caches for the multiple subsystems that access memory via the data port (e.g., a render buffer cache, a constant buffer cache, etc.). In one embodiment, threads executing on an execution unit in the execution unit array  914  communicate with the data port by exchanging messages via a data distribution interconnect that couples each of the sub-systems of the graphics processing engine  910 . 
     Execution Units— FIGS. 10-12   
       FIG. 10  is a block diagram of another embodiment of a graphics processor. In one embodiment, the graphics processor includes a ring interconnect  1002 , a pipeline front-end  1004 , a media engine  1037 , and graphics cores  1080 A-N. The ring interconnect  1002  couples the graphics processor to other processing units, including other graphics processors or one or more general-purpose processor cores. In one embodiment, the graphics processor is one of many processors integrated within a multi-core processing system. 
     The graphics processor receives batches of commands via the ring interconnect  1002 . The incoming commands are interpreted by a command streamer  1003  in the pipeline front-end  1004 . The graphics processor includes scalable execution logic to perform 3D geometry processing and media processing via the graphics core(s)  1080 A-N. For 3D geometry processing commands, the command streamer  1003  supplies the commands to the geometry pipeline  1036 . For at least some media processing commands, the command streamer  1003  supplies the commands to a video front end  1034 , which couples with a media engine  1037 . The media engine  1037  includes a video quality engine (VQE)  1030  for video and image post processing and a multi-format encode/decode (MFX)  1033  engine to provide hardware-accelerated media data encode and decode. The geometry pipeline  1036  and media engine  1037  each generate execution threads for the thread execution resources provided by at least one graphics core  1080 A. 
     The graphics processor includes scalable thread execution resources featuring modular cores  1080 A-N (sometime referred to as core slices), each having multiple sub-cores  1050 A-N,  1060 A-N (sometimes referred to as core sub-slices). The graphics processor can have any number of graphics cores  1080 A through  1080 N. In one embodiment, the graphics processor includes a graphics core  1080 A having at least a first sub-core  1050 A and a second core sub-core  1060 A. In another embodiment, the graphics processor is a low power processor with a single sub-core (e.g.,  1050 A). In one embodiment, the graphics processor includes multiple graphics cores  1080 A-N, each including a set of first sub-cores  1050 A-N and a set of second sub-cores  1060 A-N. Each sub-core in the set of first sub-cores  1050 A-N includes at least a first set of execution units  1052 A-N and media/texture samplers  1054 A-N. Each sub-core in the set of second sub-cores  1060 A-N includes at least a second set of execution units  1062 A-N and samplers  1064 A-N. In one embodiment, each sub-core  1050 A-N,  1060 A-N shares a set of shared resources  1070 A-N. In one embodiment, the shared resources include shared cache memory and pixel operation logic. Other shared resources may also be included in the various embodiments of the graphics processor. 
       FIG. 11  illustrates thread execution logic  1100  including an array of processing elements employed in one embodiment of a graphics processing engine. In one embodiment, the thread execution logic  1100  includes a pixel shader  1102 , a thread dispatcher  1104 , instruction cache  1106 , a scalable execution unit array including a plurality of execution units  1108 A-N, a sampler  1110 , a data cache  1112 , and a data port  1114 . In one embodiment the included components are interconnected via an interconnect fabric that links to each of the components. The thread execution logic  1100  includes one or more connections to memory, such as system memory or cache memory, through one or more of the instruction cache  1106 , the data port  1114 , the sampler  1110 , and the execution unit array  1108 A-N. In one embodiment, each execution unit (e.g.  1108 A) is an individual vector processor capable of executing multiple simultaneous threads and processing multiple data elements in parallel for each thread. The execution unit array  1108 A-N includes any number individual execution units. 
     In one embodiment, the execution unit array  1108 A-N is primarily used to execute “shader” programs. In one embodiment, the execution units in the array  1108 A-N execute an instruction set that includes native support for many standard 3D graphics shader instructions, such that shader programs from graphics libraries (e.g., Direct 3D and OpenGL) are executed with a minimal translation. The execution units support vertex and geometry processing (e.g., vertex programs, geometry programs, vertex shaders), pixel processing (e.g., pixel shaders, fragment shaders) and general-purpose processing (e.g., compute and media shaders). 
     Each execution unit in the execution unit array  1108 A-N operates on arrays of data elements. The number of data elements is the “execution size,” or the number of channels for the instruction. An execution channel is a logical unit of execution for data element access, masking, and flow control within instructions. The number of channels may be independent of the number of physical ALUs or FPUs for a particular graphics processor. The execution units  1108 A-N support integer and floating-point data types. 
     The execution unit instruction set includes single instruction multiple data (SIMD) instructions. The various data elements can be stored as a packed data type in a register and the execution unit will process the various elements based on the data size of the elements. For example, when operating on a 256-bit wide vector, the 256 bits of the vector are stored in a register and the execution unit operates on the vector as four separate 64-bit packed data elements (quad-word (QW) size data elements), eight separate 32-bit packed data elements (double word (DW) size data elements), sixteen separate 16-bit packed data elements (word (W) size data elements), or thirty-two separate 8-bit data elements (byte (B) size data elements). However, different vector widths and register sizes are possible. 
     One or more internal instruction caches (e.g.,  1106 ) are included in the thread execution logic  1100  to cache thread instructions for the execution units. In one embodiment, one or more data caches (e.g.,  1112 ) are included to cache thread data during thread execution. A sampler  1110  is included to provide texture sampling for 3D operations and media sampling for media operations. In one embodiment, the sampler  1110  includes specialized texture or media sampling functionality to process texture or media data during the sampling process before providing the sampled data to an execution unit. 
     During execution, the graphics and media pipelines send thread initiation requests to the thread execution logic  1100  via thread spawning and dispatch logic. The thread execution logic  1100  includes a local thread dispatcher  1104  that arbitrates thread initiation requests from the graphics and media pipelines and instantiates the requested threads on one or more execution units  1108 A-N. For example, the geometry pipeline dispatches vertex processing, tessellation, or geometry processing threads to the thread execution logic  1100 . The thread dispatcher  1104  can also process runtime thread spawning requests from the executing shader programs. 
     Once a group of geometric objects have been processed and rasterized into pixel data, the pixel shader  1102  is invoked to further compute output information and cause results to be written to output surfaces (e.g., color buffers, depth buffers, stencil buffers, etc.). In one embodiment, the pixel shader  1102  calculates the values of the various vertex attributes that are to be interpolated across the rasterized object. The pixel shader  1102  then executes an API-supplied pixel shader program. To execute the pixel shader program, the pixel shader  1102  dispatches threads to an execution unit (e.g.,  1108 A) via the thread dispatcher  1104 . The pixel shader  1102  uses texture sampling logic in the sampler  1110  to access texture data in texture maps stored in memory. Arithmetic operations on the texture data and the input geometry data compute pixel color data for each geometric fragment, or discards one or more pixels from further processing. 
     In one embodiment, the data port  1114  provides a memory access mechanism for the thread execution logic  1100  output processed data to memory for processing on a graphics processor output pipeline. In one embodiment, the data port  1114  includes or couples to one or more cache memories (e.g., data cache  1112 ) to cache data for memory access via the data port. 
       FIG. 12  is a block diagram illustrating a graphics processor execution unit instruction format according to an embodiment. In one embodiment, the graphics processor execution units support an instruction set having instructions in multiple formats. The solid lined boxes illustrate the components that are generally included in an execution unit instruction, while the dashed lines include components that are optional or that are only included in a sub-set of the instructions. The instruction format described an illustrated are macro-instructions, in that they are instructions supplied to the execution unit, as opposed to micro-operations resulting from instruction decode once the instruction is processed. 
     In one embodiment, the graphics processor execution units natively support instructions in a 128-bit format  1210 . A 64-bit compacted instruction format  1230  is available for some instructions based on the selected instruction, instruction options, and number of operands. The native 128-bit format  1210  provides access to all instruction options, while some options and operations are restricted in the 64-bit format  1230 . The native instructions available in the 64-bit format  1230  varies by embodiment. In one embodiment, the instruction is compacted in part using a set of index values in an index field  1213 . The execution unit hardware references a set of compaction tables based on the index values and uses the compaction table outputs to reconstruct a native instruction in the 128-bit format  1210 . 
     For each format, an instruction opcode  1212  defines the operation that the execution unit is to perform. The execution units execute each instruction in parallel across the multiple data elements of each operand. For example, in response to an add instruction the execution unit performs a simultaneous add operation across each color channel representing a texture element or picture element. By default, the execution unit performs each instruction across all data channels of the operands. An instruction control field  1212  enables control over certain execution options, such as channels selection (e.g., predication) and data channel order (e.g., swizzle). For 128-bit instructions  1210  an exec-size field  1216  limits the number of data channels that will be executed in parallel. The exec-size field  1216  is not available for use in the 64-bit compact instruction format  1230 . 
     Some execution unit instructions have up to three operands including two source operands, src 0   1222 , src 1   1222 , and one destination  1218 . In one embodiment, the execution units support dual destination instructions, where one of the destinations is implied. Data manipulation instructions can have a third source operand (e.g., SRC 2   1224 ), where the instruction opcode JJ 12  determines the number of source operands. An instruction&#39;s last source operand can be an immediate (e.g., hard-coded) value passed with the instruction. 
     In one embodiment instructions are grouped based on opcode bit-fields to simplify Opcode decode  1240 . For an 8-bit opcode, bits  4 ,  5 , and  6  allow the execution unit to determine the type of opcode. The precise opcode grouping shown is exemplary. In one embodiment, a move and logic opcode group  1242  includes data movement and logic instructions (e.g., mov, cmp). The move and logic group  1242  shares the five most significant bits (MSB), where move instructions are in the form of 0000xxxxb (e.g., 0x0x) and logic instructions are in the form of 0001xxxxb (e.g., 0x01). A flow control instruction group  1244  (e.g., call, jmp) includes instructions in the form of 0010xxxxb (e.g., 0x20). A miscellaneous instruction group  1246  includes a mix of instructions, including synchronization instructions (e.g., wait, send) in the form of 0011xxxxb (e.g., 0x30). A parallel math instruction group 1248 includes component-wise arithmetic instructions (e.g., add, mul) in the form of 0100xxxxb (e.g., 0x40). The parallel math group  1248  performs the arithmetic operations in parallel across data channels. The vector math group  1250  includes arithmetic instructions (e.g., dp4) in the form of 0101xxxxb (e.g., 0x50). The vector math group performs arithmetic such as dot product calculations on vector operands. 
     Graphics Pipeline— FIG. 8   
       FIG. 13  is a block diagram of another embodiment of a graphics processor which includes a graphics pipeline  1320 , a media pipeline  1330 , a display engine  1340 , thread execution logic  1350 , and a render output pipeline  1370 . In one embodiment, the graphics processor is a graphics processor within a multi-core processing system that includes one or more general purpose processing cores. The graphics processor is controlled by register writes to one or more control registers (not shown) or via commands issued to the graphics processor via a ring interconnect  1302 . The ring interconnect  1302  couples the graphics processor to other processing components, such as other graphics processors or general-purpose processors. Commands from the ring interconnect are interpreted by a command streamer  1303  which supplies instructions to individual components of the graphics pipeline  1320  or media pipeline  1330 . 
     The command streamer  1303  directs the operation of a vertex fetcher  1305  component that reads vertex data from memory and executes vertex-processing commands provided by the command streamer  1303 . The vertex fetcher  1305  provides vertex data to a vertex shader  1307 , which performs coordinate space transformation and lighting operations to each vertex. The vertex fetcher  1305  and vertex shader  1307  execute vertex-processing instructions by dispatching execution threads to the execution units  1352 A,  1352 B via a thread dispatcher  1331 . 
     In one embodiment, the execution units  1352 A,  1352 B are an array of vector processors having an instruction set for performing graphics and media operations. The execution units  1352 A,  1352 B have an attached L1 cache  1351  that is specific for each array or shared between the arrays. The cache can be configured as a data cache, an instruction cache, or a single cache that is partitioned to contain data and instructions in different partitions. 
     In one embodiment, the graphics pipeline  1320  includes tessellation components to perform hardware-accelerated tessellation of 3D objects. A programmable hull shader  1311  configures the tessellation operations. A programmable domain shader  1317  provides back-end evaluation of tessellation output. A tessellator  1313  operates at the direction of the hull shader  1311  and contains special purpose logic to generate a set of detailed geometric objects based on a coarse geometric model that is provided as input to the graphics pipeline  1320 . If tessellation is not used, the tessellation components  1311 ,  1313 ,  1317  can be bypassed. 
     The complete geometric objects can be processed by a geometry shader  1319  via one or more threads dispatched to the execution units  1352 A,  1352 B, or can proceed directly to the clipper  1329 . The geometry shader operates on entire geometric objects, rather than vertices or patches of vertices as in previous stages of the graphics pipeline. If the tessellation is disabled the geometry shader  1319  receives input from the vertex shader  1307 . The geometry shader  1319  is programmable by a geometry shader program to perform geometry tessellation if the tessellation units are disabled. 
     Prior to rasterization, vertex data is processed by a clipper  1329 , which is either a fixed function clipper or a programmable clipper having clipping and geometry shader functions. In one embodiment, a rasterizer  1373  in the render output pipeline  1370  dispatches pixel shaders to convert the geometric objects into their per pixel representations. In one embodiment, pixel shader logic is included in the thread execution logic  1350 . 
     The graphics engine has an interconnect bus, interconnect fabric, or some other interconnect mechanism that allows data and message passing amongst the major components of the graphics engine. In one embodiment the execution units  1352 A,  1352 B and associated cache(s)  1351 , texture and media sampler  1354 , and texture/sampler cache  1358  interconnect via a data port  1356  to perform memory access and communicate with render output pipeline components of the graphics engine. In one embodiment, the sampler  1354 , caches  1351 ,  1358  and execution units  1352 A,  1352 B each have separate memory access paths. 
     In one embodiment, the render output pipeline  1370  contains a rasterizer and depth test component  1373  that converts vertex-based objects into their associated pixel-based representation. In one embodiment, the rasterizer logic includes a windower/masker unit to perform fixed function triangle and line rasterization. An associated render and depth buffer caches  1378 ,  1379  are also available in one embodiment. A pixel operations component  1377  performs pixel-based operations on the data, though in some instances, pixel operations associated with 2D operations (e.g. bit block image transfers with blending) are performed by the 2D engine  1341 , or substituted at display time by the display controller  1343  using overlay display planes. In one embodiment a shared L3 cache  1375  is available to all graphics components, allowing the sharing of data without the use of main system memory. 
     The graphics processor media pipeline  1330  includes a media engine  337  and a video front end  1334 . In one embodiment, the video front end  1334  receives pipeline commands from the command streamer  1303 . However, in one embodiment the media pipeline  1330  includes a separate command streamer. The video front-end  1334  processes media commands before sending the command to the media engine  1337 . In one embodiment, the media engine includes thread spawning functionality to spawn threads for dispatch to the thread execution logic  1350  via the thread dispatcher  1331 . 
     In one embodiment, the graphics engine includes a display engine  1340 . In one embodiment, the display engine  1340  is external to the graphics processor and couples with the graphics processor via the ring interconnect  1302 , or some other interconnect bus or fabric. The display engine  1340  includes a 2D engine  1341  and a display controller  1343 . The display engine  1340  contains special purpose logic capable of operating independently of the 3D pipeline. The display controller  1343  couples with a display device (not shown), which may be a system integrated display device, as in a laptop computer, or an external display device attached via an display device connector. 
     The graphics pipeline  1320  and media pipeline  1330  are configurable to perform operations based on multiple graphics and media programming interfaces and are not specific to any one application programming interface (API). In one embodiment, driver software for the graphics processor translates API calls that are specific to a particular graphics or media library into commands that can be processed by the graphics processor. In various embodiments, support is provided for the Open Graphics Library (OpenGL) and Open Computing Language (OpenCL) supported by the Khronos Group, the Direct3D library from the Microsoft Corporation, or, in one embodiment, both OpenGL and D3D. Support may also be provided for the Open Source Computer Vision Library (OpenCV). A future API with a compatible 3D pipeline would also be supported if a mapping can be made from the pipeline of the future API to the pipeline of the graphics processor. 
     Graphics Pipeline Programming— FIG. 14A-B   
       FIG. 14A  is a block diagram illustrating a graphics processor command format according to an embodiment and  FIG. 14B  is a block diagram illustrating a graphics processor command sequence according to an embodiment. The solid lined boxes in  FIG. 14A  illustrate the components that are generally included in a graphics command while the dashed lines include components that are optional or that are only included in a sub-set of the graphics commands. The exemplary graphics processor command format  1400  of  FIG. 14A  includes data fields to identify a target client  1402  of the command, a command operation code (opcode)  1404 , and the relevant data  1406  for the command. A sub-opcode  1405  and a command size  1408  are also included in some commands. 
     The client  1402  specifies the client unit of the graphics device that processes the command data. In one embodiment, a graphics processor command parser examines the client field of each command to condition the further processing of the command and route the command data to the appropriate client unit. In one embodiment, the graphics processor client units include a memory interface unit, a render unit, a 2D unit, a 3D unit, and a media unit. Each client unit has a corresponding processing pipeline that processes the commands. Once the command is received by the client unit, the client unit reads the opcode  1404  and, if present, sub-opcode  1405  to determine the operation to perform. The client unit performs the command using information in the data  1406  field of the command. For some commands an explicit command size  1408  is expected to specify the size of the command. In one embodiment, the command parser automatically determines the size of at least some of the commands based on the command opcode. In one embodiment commands are aligned via multiples of a double word. 
     The flow chart in  FIG. 14B  shows a sample command sequence  1410 . In one embodiment, software or firmware of a data processing system that features an embodiment of the graphics processor uses a version of the command sequence shown to set up, execute, and terminate a set of graphics operations. A sample command sequence is shown and described for exemplary purposes, however embodiments are not limited to these commands or to this command sequence. Moreover, the commands may be issued as batch of commands in a command sequence, such that the graphics processor will process the sequence of commands in an at least partially concurrent manner. 
     The sample command sequence  1410  may begin with a pipeline flush command  1412  to cause any active graphics pipeline to complete the currently pending commands for the pipeline. In one embodiment, the 3D pipeline  1422  and the media pipeline  1424  do not operate concurrently. The pipeline flush is performed to cause the active graphics pipeline to complete any pending commands. In response to a pipeline flush, the command parser for the graphics processor will pause command processing until the active drawing engines complete pending operations and the relevant read caches are invalidated. Optionally, any data in the render cache that is marked ‘dirty’ can be flushed to memory. A pipeline flush command  1412  can be used for pipeline synchronization or before placing the graphics processor into a low power state. 
     A pipeline select command  1413  is used when a command sequence requires the graphics processor to explicitly switch between pipelines. A pipeline select command  1413  is required only once within an execution context before issuing pipeline commands unless the context is to issue commands for both pipelines. In one embodiment, a pipeline flush command is  1412  is required immediately before a pipeline switch via the pipeline select command  1413 . 
     A pipeline control command  1414  configures a graphics pipeline for operation and is used to program the 3D pipeline  1422  and the media pipeline  1424 . The pipeline control command  1414  configures the pipeline state for the active pipeline. In one embodiment, the pipeline control command  1414  is used for pipeline synchronization and to clear data from one or more cache memories within the active pipeline before processing a batch of commands. 
     Return buffer state commands  1416  are used to configure a set of return buffers for the respective pipelines to write data. Some pipeline operations require the allocation, selection, or configuration of one or more return buffers into which the operations write intermediate data during processing. The graphics processor also uses one or more return buffers to store output data and to perform cross thread communication. The return buffer state  1416  includes selecting the size and number of return buffers to use for a set of pipeline operations. 
     The remaining commands in the command sequence differ based on the active pipeline for operations. Based on a pipeline determination  1420 , the command sequence is tailored to the 3D pipeline  1422  beginning with the 3D pipeline state  1430 , or the media pipeline  1424  beginning at the media pipeline state  1440 . 
     The commands for the 3D pipeline state  1430  include 3D state setting commands for vertex buffer state, vertex element state, constant color state, depth buffer state, and other state variables that are to be configured before 3D primitive commands are processed. The values of these commands are determined at least in part based the particular 3D API in use. 3D pipeline state  1430  commands are also able to selectively disable or bypass certain pipeline elements if those elements will not be used. 
     The 3D primitive  1432  command is used to submit 3D primitives to be processed by the 3D pipeline. Commands and associated parameters that are passed to the graphics processor via the 3D primitive  1432  command are forwarded to the vertex fetch function in the graphics pipeline. The vertex fetch function uses the 3D primitive  1432  command data to generate vertex data structures. The vertex data structures are stored in one or more return buffers. The 3D primitive  1432  command is used to perform vertex operations on 3D primitives via vertex shaders. To process vertex shaders, the 3D pipeline  1422  dispatches shader execution threads to graphics processor execution units. 
     The 3D pipeline  1422  is triggered via an execute  1434  command or event. In one embodiment a register write triggers command execution. In one embodiment execution is triggered via a ‘go’ or ‘kick’ command in the command sequence. In one embodiment command execution is triggered using a pipeline synchronization command to flush the command sequence through the graphics pipeline. The 3D pipeline will perform geometry processing for the 3D primitives. Once operations are complete, the resulting geometric objects are rasterized and the pixel engine colors the resulting pixels. Additional commands to control pixel shading and pixel back end operations may also be included for those operations. 
     The sample command sequence  1410  follows the media pipeline  1424  path when performing media operations. In general, the specific use and manner of programming for the media pipeline  1424  depends on the media or compute operations to be performed. Specific media decode operations may be offloaded to the media pipeline during media decode. The media pipeline can also be bypassed and media decode can be performed in whole or in part using resources provided by one or more general purpose processing cores. In one embodiment, the media pipeline also includes elements for general-purpose graphics processor unit (GPGPU) operations, where the graphics processor is used to perform SIMD vector operations using computational shader programs that are not explicitly related to the rendering of graphics primitives. 
     The media pipeline  1424  is configured in a similar manner as the 3D pipeline  1422 . A set of media pipeline state commands  1440  are dispatched or placed into in a command queue before the media object commands  1442 . The media pipeline state commands  1440  include data to configure the media pipeline elements that will be used to process the media objects. This includes data to configure the video decode and video encode logic within the media pipeline, such as encode or decode format. The media pipeline state commands  1440  also support the use one or more pointers to “indirect” state elements that contain a batch of state settings. 
     Media object commands  1442  supply pointers to media objects for processing by the media pipeline. The media objects include memory buffers containing video data to be processed. In one embodiment, all media pipeline state must be valid before issuing a media object command  1442 . Once the pipeline state is configured and media object commands  1442  are queued, the media pipeline  1424  is triggered via an execute  1434  command or an equivalent execute event (e.g., register write). Output from the media pipeline  1424  may then be post processed by operations provided by the 3D pipeline  1422  or the media pipeline  1424 . In one embodiment, GPGPU operations are configured and executed in a similar manner as media operations. 
     Graphics Software Architecture— FIG. 15   
       FIG. 15  illustrates exemplary graphics software architecture for a data processing system according to an embodiment. The software architecture includes a 3D graphics application  1510 , an operating system  1520 , and at least one processor  1530 . The processor  1530  includes a graphics processor  1532  and one or more general-purpose processor core(s)  1534 . The graphics application  1510  and operating system  1520  each execute in the system memory  1550  of the data processing system. 
     In one embodiment, the 3D graphics application  1510  contains one or more shader programs including shader instructions  1512 . The shader language instructions may be in a high-level shader language, such as the High Level Shader Language (HLSL) or the OpenGL Shader Language (GLSL). The application also includes executable instructions  1514  in a machine language suitable for execution by the general-purpose processor core  1534 . The application also includes graphics objects  1516  defined by vertex data. 
     The operating system  1520  may be a Microsoft® Windows® operating system from the Microsoft Corporation, a proprietary UNIX-like operating system, or an open source UNIX-like operating system using a variant of the Linux kernel. When the Direct3D API is in use, the operating system  1520  uses a front-end shader compiler  1524  to compile any shader instructions  1512  in HLSL into a lower-level shader language. The compilation may be a just-in-time compilation or the application can perform share pre-compilation. In one embodiment, high-level shaders are compiled into low-level shaders during the compilation of the 3D graphics application  1510 . 
     The user mode graphics driver  1526  may contain a back-end shader compiler  1527  to convert the shader instructions  1512  into a hardware specific representation. When the OpenGL API is in use, shader instructions  1512  in the GLSL high-level language are passed to a user mode graphics driver  1526  for compilation. The user mode graphics driver uses operating system kernel mode functions  1528  to communicate with a kernel mode graphics driver  1529 . The kernel mode graphics driver  1529  communicates with the graphics processor  1532  to dispatch commands and instructions. 
     To the extent various operations or functions are described herein, they can be described or defined as hardware circuitry, software code, instructions, configuration, and/or data. The content can be embodied in hardware logic, or as directly executable software (“object” or “executable” form), source code, high level shader code designed for execution on a graphics engine, or low level assembly language code in an instruction set for a specific processor or graphics core. The software content of the embodiments described herein can be provided via an article of manufacture with the content stored thereon, or via a method of operating a communication interface to send data via the communication interface. 
     A non-transitory machine readable storage medium can cause a machine to perform the functions or operations described, and includes any mechanism that stores information in a form accessible by a machine (e.g., computing device, electronic system, etc.), such as recordable/non-recordable media (e.g., read only memory (ROM), random access memory (RAM), magnetic disk storage media, optical storage media, flash memory devices, etc.). A communication interface includes any mechanism that interfaces to any of a hardwired, wireless, optical, etc., medium to communicate to another device, such as a memory bus interface, a processor bus interface, an Internet connection, a disk controller, etc. The communication interface is configured by providing configuration parameters or sending signals to prepare the communication interface to provide a data signal describing the software content. The communication interface can be accessed via one or more commands or signals sent to the communication interface. 
     Various components described can be a means for performing the operations or functions described. Each component described herein includes software, hardware, or a combination of these. The components can be implemented as software modules, hardware modules, special-purpose hardware (e.g., application specific hardware, application specific integrated circuits (ASICs), digital signal processors (DSPs), etc.), embedded controllers, hardwired circuitry, etc. Besides what is described herein, various modifications can be made to the disclosed embodiments and implementations of the invention without departing from their scope. Therefore, the illustrations and examples herein should be construed in an illustrative, and not a restrictive sense. The scope of the invention should be measured solely by reference to the claims that follow. 
     The following examples pertain to further embodiments: 
     Example 1 is a method of scheduling graphics commands in a processor to processor transaction comprising: providing through non-coherent memory an instruction for a write token to target a graphics command; sending the write token to target the graphics command to the non-coherent memory; providing a write back transaction token through coherent memory when the graphics command is sent; sending the write token for the graphics command through the non-coherent memory; comparing the write back transaction token provided through coherent memory against the write token for the graphics command; and executing graphics context when the write back token comparison with the write token for the graphics command is satisfied. 
     In Example 2, the method of Example 1, wherein the graphics command is provided by a graphics driver of a central processing unit. 
     In Example 3, the method of Example 1, wherein the graphics command is provided by a graphics processing unit. 
     In Example 4, the method of Example 1, wherein the graphics context are consumed by a graphics processing unit. 
     In Example 5, the method of Example 1, wherein the tokens are sent to registers in a graphics steering unit connected to the non-coherent fabric and graphics processing unit with a coherent fabric connection. 
     In Example 6, the method of Example 1 further comprising a coherent transaction in the form of a doorbell ring or a snoop request to a pre-determined address from one processor to another processor indicating that the graphics commands is available. 
     In Example 7, the method of Example 1 further comprising updating the write token by an incremental value. 
     In Example 8, the method of Example 1, wherein the incremental value is set up to a maximum counter value. 
     Example 9 is a device to process graphics context comprising: a central processor unit; a graphics processing unit configured with the central processor unit, the graphics processing unit comprising register to store tokens associated with graphics commands associated with the graphics context; memory residing on coherent memory configured to the central processor unit and graphics processing unit to receive the graphics context; and a graphics steering component residing in non-coherent memory comprising a register configured to receive tokens from the graphics processing unit, wherein the tokens are sent through non-coherent memory and used to determine whether to execute the graphics context. 
     In Example 10, the device of Example 9, wherein the central processor unit provides a doorbell ring to the graphics processing unit to indicate that the graphics context are available. 
     In Example 11, the device of Example 10, wherein the central processor unit is configured to perform a write instruction to perform to push commands to non-coherent memory prior to the doorbell ring. 
     In Example 12, the device of Example 9, wherein the graphics processing unit comprises a scheduling engine implemented by a microcontroller or programmable engine, to create the tokens. 
     In Example 13, the device of Example 9, wherein the graphics processing unit comprises an incrementing counter configured to increment the value of the tokens as new graphics contexts are received. 
     In Example 14, the device of Example 9, wherein the graphics steering unit graphics comprises a register configured to receive graphics scheduling commands from the central processor unit, wherein the graphics scheduling commands are passed to the graphics processing unit. 
     In Example 15, the device of Example 9, wherein the graphics steering unit comprises a graphics aperture translation component used to translate non-coherent memory mapped addresses to memory addresses. 
     Example 16 is one or more computer-readable media storing processor-executable instructions that when executed cause processors to implement a method comprising: initiating graphics command; providing a token associated with the graphics command; comparing the token to a stored token in a non-coherent memory, to determine if the stored token comparison with the provided token is satisfied; and executing the graphics command if the provided token comparison with the stored token is satisfied, otherwise performing the following: performing a transaction by a first processor to a second processor through coherent memory to indicate that graphics context is available; writing an updated token by the second processor to be sent to the non-coherent memory; comparing the token to the stored token in the non-coherent memory; andupdating the token associated with the graphics command. 
     In Example 17, the one or more computer-readable media as recited in Example 16, wherein the initiating is from a graphics driver of the first processor. 
     In Example 18, the one or more computer-readable media as recited in Example 16, wherein the first processor is a central processing unit and the second processor is a graphics processing unit. 
     In Example 19, the one or more computer-readable media as recited in Example 16 further comprising sending graphics context associated with the graphics command to a coherent memory for consumption by the second processing unit. 
     In Example 20, the one or more computer-readable media as recited in Example 16 further comprising incrementing a counter as to token values. 
     Example 21 is a device to process graphics context comprising: a central processor unit; a first graphics processing unit configured to a second graphics processing unit, the first graphics processing unit comprising register to store tokens associated with graphics commands; memory residing on coherent memory configured to the central processor unit and first graphics processing unit to receive the graphics context; anda graphics steering component residing in non-coherent memory comprising a register to receive tokens from the first graphics processing unit, wherein the tokens are sent through the non-coherent memory and are used to determine whether to execute the graphics context. 
     In Example 22, the device of Example 21, wherein the second graphics processing unit provides a doorbell ring to the first graphics processing unit to indicate the graphics context are available. 
     In Example 23, the device of Example 22, wherein the second graphics processing unit is configured to perform a write instruction to push the graphics commands to non-coherent memory prior to the doorbell ring. 
     In Example 24, the device of Example 21, wherein the first graphics processing unit comprises a scheduling engine implemented through a microcontroller or programmable engine, to create the tokens. 
     In Example 25, the device of Example 21, wherein the first graphics processing unit comprises an incrementing counter configured to increment the value of the tokens as new graphics contexts are received. 
     In Example 26, the device of Example 21, wherein the graphics steering unit graphics comprises a register configured to receive graphics scheduling commands from the second graphics processing unit, wherein the graphics scheduling commands are passed to the first graphics processing unit. 
     In Example 27, the device of Example 21, wherein the graphics steering unit comprises a graphics aperture translation component configured to translate non-coherent memory mapped addresses to memory addresses.