Patent Publication Number: US-10784200-B2

Title: Ionizing radiation blocking in IC chip to reduce soft errors

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is a divisional of U.S. patent application Ser. No. 11/836,819, filed on Aug. 10, 2007, currently pending and hereby incorporated by reference in its entirety. 
    
    
     BACKGROUND 
     1. Technical Field 
     The disclosure relates generally to integrated circuit (IC) chip fabrication, and more particularly, to ionizing radiation blocking in an IC chip to reduce soft errors. 
     2. Background Art 
     Soft errors caused by ionizing radiation including, for example, alpha particles, beta radiation, cosmic rays, high-frequency electromagnetic radiation, or other types of radiation capable of producing a change in electrical state, are an increasingly large problem for integrated circuit (IC) chip fabricators. In particular, the continual miniaturization of IC chip circuitry and increased performance requirements has caused fabricators to focus more attentively to soft error rates (SER) caused by ionizing radiation, which drain performance. One approach to address this issue is to use external radiation shields about an IC chip. Ionizing radiation, however, can enter an IC chip from a number of sources such as the package to which an IC chip is attached, e.g., through the interconnecting solder. As a result, external shields are not always effective. Another approach is to use special circuitry within an IC chip to prevent the ionizing radiation from altering electrical states. However, special circuitry spends resources, e.g., space, power, etc., that may be better used for the overall IC chip function. 
     SUMMARY 
     Methods of blocking ionizing radiation to reduce soft errors and resulting IC chips are disclosed. One embodiment includes forming a front end of line (FEOL) for an integrated circuit (IC) chip; and forming at least one back end of line (BEOL) dielectric layer including ionizing radiation blocking material therein. Another embodiment includes forming a front end of line (FEOL) for an integrated circuit (IC) chip; and forming an ionizing radiation blocking layer positioned in a back end of line (BEOL) of the IC chip. The ionizing radiation blocking material or layer absorbs ionizing radiation and reduces soft errors within the IC chip. 
     A first aspect of the disclosure provides a method comprising: forming a front end of line (FEOL) for an integrated circuit (IC) chip; and forming at least one back end of line (BEOL) dielectric layer including ionizing radiation blocking material therein. 
     A second aspect of the disclosure provides an integrated circuit (IC) chip comprising: at least one back end of line (BEOL) dielectric layer including ionizing radiation blocking material therein. 
     A third aspect of the disclosure provides a method comprising: forming a front end of line (FEOL) for an integrated circuit (IC) chip; and forming an ionizing radiation blocking layer positioned in a back end of line (BEOL) of the IC chip. 
     A fourth aspect of the disclosure provides an integrated circuit (IC) chip comprising: an ionizing radiation blocking layer positioned in a back end of line (BEOL) of the IC chip. 
     A fifth aspect of the disclosure provides an integrated circuit (IC) chip having: a first layer of the integrated circuit chip; a first metallization layer over the first layer; and at least one dielectric layer over the first metallization layer, the at least one dielectric layer including ionizing radiation blocking material therein, wherein the ionizing radiation blocking material is configured to block or absorb ionizing radiation. 
     A sixth aspect of the disclosure provides an integrated circuit (IC) chip having: a first metallization layer; and a dielectric layer over the first metallization layer, the dielectric layer including an ionizing radiation blocking layer configured to block or absorb ionizing radiation. 
     A seventh aspect of the disclosure provides an integrated circuit (IC) chip having: a first back end of the line (BEOL) dielectric layer; a conductor located within the BEOL dielectric layer; a second BEOL dielectric layer over the first BEOL dielectric layer; and an ionizing radiation blocking material layer over the second BEOL, wherein the ionizing radiation blocking material layer is configured to block or absorb ionizing radiation, wherein the ionizing radiation blocking material layer is distanced from the conductor. 
     The illustrative aspects of the present disclosure are designed to solve the problems herein described and/or other problems not discussed. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       These and other features of this disclosure will be more readily understood from the following detailed description of the various aspects of the disclosure taken in conjunction with the accompanying drawings that depict various embodiments of the disclosure, in which: 
         FIG. 1  shows a cross-sectional view of a first embodiment of an IC chip including a dielectric having ionizing radiation blocking material therein according to one embodiment of the disclosure. 
         FIG. 2  shows a cross-sectional view of a second embodiment of an IC chip including a dielectric having ionizing radiation blocking material therein according to one embodiment of the disclosure. 
         FIGS. 3-6  show cross-sectional views of one embodiment of a method of reducing soft errors including forming an ionizing radiation blocking layer according to the disclosure, with  FIG. 6  showing one embodiment of the resulting IC chip. 
         FIG. 7  shows a cross-sectional view of an alternative embodiment of the method of  FIGS. 3-6  and another embodiment of the resulting IC chip. 
         FIG. 8  shows a graph illustrating the effectiveness of the ionizing radiation blocking material embodiment of  FIGS. 1-2 . 
     
    
    
     It is noted that the drawings of the disclosure are not to scale. The drawings are intended to depict only typical aspects of the disclosure, and therefore should not be considered as limiting the scope of the disclosure. In the drawings, like numbering represents like elements between the drawings. 
     DETAILED DESCRIPTION 
     The disclosure includes a number of methods and IC chips including ionizing radiation blocking material in a dielectric thereof or an ionizing radiation blocking layer to reduce soft errors. As used herein, “ionizing radiation” may include, for example, alpha particles, beta radiation, cosmic rays, high-frequency electromagnetic radiation, and/or other types of radiation capable of producing a change in electrical state. Various dielectrics may be used in forming the IC chips according to the disclosure. Unless otherwise specified, the dielectrics may be any dielectric material appropriate for the stated use. Such dielectrics may include but are not limited to: silicon nitride (Si 3 N 4 ), silicon oxide (SiO 2 ), fluorinated SiO 2  (FSG), hydrogenated silicon oxycarbide (SiCOH), porous SiCOH, boro-phosho-silicate glass (BPSG), silsesquioxanes, carbon (C) doped oxides (i.e., organosilicates) that include atoms of silicon (Si), carbon (C), oxygen (O), and/or hydrogen (H), thermosetting polyarylene ethers, a polyarylene ether (e.g., SiLK available from Dow Chemical Corporation), a spin-on silicon-carbon contained polymer material (available form JSR Corporation), other low dielectric constant (&lt;3.9) material, or layers thereof. 
       FIGS. 1-2  show embodiments of a method according to the disclosure for blocking ionizing radiation to reduce soft errors in an IC chip  100 . IC chip  100  includes at least one BEOL dielectric layer  104  including ionizing radiation blocking material  108  therein. A method according to one embodiment includes forming a front end of line (FEOL) layer  102  for IC chip  100 . FEOL means operations performed on a semiconductor wafer in the course of device manufacturing up to first metallization (M 1 ), while back end of line (BEOL) refers to operations performed on the semiconductor wafer in the course of device manufacturing following first metallization (M 1 ). FEOL  102  may be formed using any now known or later developed techniques such as material deposition, ion implantation, photolithography, etching, etc. FEOL  102  may include any conventional IC chip structures, e.g., transistors, resistors, capacitors, interconnecting wiring, etc. 
       FIGS. 1-2  also show forming BEOL  106  including a plurality of BEOL dielectric layers M 1  to MX/VX. As understood, each BEOL dielectric layer includes one or more dielectric layers, each of which may have a contact and/or wire interconnects positioned therein or therethrough. At least one BEOL dielectric layer  104  includes ionizing radiation blocking material  108  therein. Ionizing radiation blocking material  108  may be any material that absorbs ionizing radiation such as alpha particles. In one embodiment, ionizing radiation blocking material  108  may include: hafnium (Hf), zirconium (Zr), graphite (C), cadmium (Cd), cobalt (Co) or copper (Cu). In the embodiment shown in  FIG. 1 , BEOL dielectric layer  104  is positioned as a penultimate BEOL dielectric layer  110  and may include an oxide such as silicon oxide (SiO 2 ). In the embodiment shown in  FIG. 2 , BEOL dielectric layer  104  is positioned as a last BEOL dielectric layer  112  and may include a polymer such as a polyimide (e.g., a photosensitive polyimide (PSPI)). In one particular embodiment, BEOL dielectric layer  104  ( FIG. 2 ) includes dielectric  106  including a polyimide and ionizing radiation blocking material  108  includes copper (Cu). It is understood that BEOL dielectric layer  104  may also be positioned at different levels of BEOL  106 . 
     The mechanism for forming BEOL dielectric layer  104  including ionizing radiation blocking material  108  varies depending on the dielectric material used. In some instances, it may be difficult to form BEOL dielectric layer  104  and combine in ionizing radiation blocking material  108  during formation of the dielectric, e.g., where the dielectric includes an oxide. In this case, BEOL dielectric layer(s)  104  forming includes forming the dielectric (on the wafer) with ionizing radiation blocking material  108  previously combined therein. That is, the dielectric material is manufactured with ionizing radiation blocking material  108  therein and BEOL dielectric layer  104  is formed using that material, e.g., by any conventional deposition technique. In other cases, it may be possible to simultaneously form BEOL dielectric layer  104  and combine ionizing radiation blocking material  108  therein. For example, where the dielectric includes a polymer, it may be possible to deposit the polymer while introducing ionizing radiation blocking material  108  thereto, e.g., by any conventional deposition technique for the dielectric and by introducing particles of ionizing radiation blocking material  108 . 
     While  FIGS. 1 and 2  show BEOL dielectric layer  104  as a single layer, it is understood that it may include multiple adjacent layers. Furthermore, while only one BEOL dielectric layer  104  is shown for each IC chip  100 , it may be possible to provide more than one BEOL dielectric layer  104  with ionizing radiation blocking material  108  therein. 
     Referring to  FIGS. 3-7 , other embodiments of methods for blocking ionizing radiation to reduce soft errors in an IC chip  200  ( FIGS. 6 and 7 ) are shown. In these embodiments, as shown in  FIGS. 6 and 7 , IC chip  200  may include an ionizing radiation blocking layer  220  positioned in BEOL  222 . By “in BEOL”  222  is meant that ionizing radiation blocking layer  220  may be within any BEOL dielectric layer, between any BEOL dielectric layers or located across a plurality of BEOL dielectric layers.  FIG. 3  shows forming a FEOL  230  (only shown in  FIG. 3  for clarity). FEOL  230  may be formed using any now known or later developed technique, such as material deposition, photolithography, etching, etc., and may include any conventional IC chip structures, e.g., transistors, resistors, capacitors, interconnecting wiring, etc. 
     Forming ionizing radiation blocking layer  220  ( FIG. 6 ) positioned in BEOL  222  follows FEOL  230  formation. Ionizing radiation blocking layer  220  includes an ionizing radiation blocking film  250  and a conductor  252  that overlaps an opening or discontinuity  260  ( FIG. 6 ) in film  250  through which a contact  254  may extend.  FIGS. 4-6  show forming ionizing radiation blocking layer  220  with ionizing radiation blocking film  250  thereof between two different BEOL dielectric layers  272 ,  274  of different material and distanced from conductor  252 . In contrast,  FIG. 7  shows an alternative embodiment in which film  250  is positioned between a BEOL dielectric layer  272  and another BEOL dielectric layer  276  that are the same material. Also, in  FIG. 7 , film  250  is above conductor  252 , i.e., not distanced greatly from conductor  252 , typically in the range of 150 to 1000 Å. BEOL dielectric layer(s)  272 ,  274 ,  276  may be at any position within BEOL  222  from M 1  up to a last BEOL dielectric layer. As seen in  FIGS. 6 and 7 , ionizing radiation blocking layer  220  is positioned across a plurality of BEOL dielectric layers and is laterally discontinuous in any one BEOL dielectric layer but forms a complete plane in a vertical sense because of an overlap of conductor  252  and opening or discontinuity  260  in film  250 , i.e., when viewed in a plan view. As such, layer  220  substantially blocks ionizing radiation. 
     Returning to  FIG. 3 , in one embodiment ionizing radiation blocking layer  220  forming may include the following process. As shown in  FIG. 3 , conductor  252 , e.g., an operational conductor of IC  200  ( FIG. 6 ), is formed in a first BEOL dielectric layer  270 . Conductor  252  may be formed using any conventional or later developed damascene or dual damascene processing. A second BEOL dielectric layer  272  is formed over conductor  252 , e.g., by any conventional or later developed deposition techniques. As indicated, second BEOL dielectric layer  272  may include any number of dielectric layers. In  FIG. 3 , three layers are shown and in  FIG. 7  only one layer is shown. Ionizing radiation blocking film  250  is formed over second BEOL dielectric layer  272 . Ionizing radiation blocking film  250  may include any material capable of absorbing ionizing radiation such as: hafnium (Hf), zirconium (Zr), graphite (C), cadmium (Cd), cobalt (Co) and copper (Cu). If necessary, a liner material (not shown) may be employed to prevent diffusion. If ionizing radiation blocking film  250  is in a last BEOL dielectric layer, there may be some concern for aluminum (Al) shorting from package interconnects (not shown) to film  250 . In this case, a BEOL dielectric layer  274 , e.g., a silicon nitride (Si 3 N 4 ) cap, may be deposited over film  250 . Otherwise, layer  274  may represent the start of another BEOL layer. 
       FIG. 4  shows forming an opening or discontinuity  260  through ionizing radiation blocking film  250 , e.g., by depositing and patterning a photoresist  280  and etching. Opening  260  extends through film  250  to an underlying layer, i.e., first BEOL dielectric layer  272  in  FIG. 4  or conductor  252  in  FIG. 7 .  FIGS. 5-6  show filling opening  260  with a third BEOL dielectric layer  278 , and forming a contact  254  through third BEOL dielectric layer  278  (and first BEOL dielectric layer  272 ) to conductor  252 , e.g., by depositing and patterning a photoresist  284 , etching to form an opening  286 , depositing a liner and conductor, and planarizing. Contact  254  is not as wide as opening  260  for purposes described herein. 
       FIG. 6  shows ionizing radiation blocking layer  220  in which ionizing radiation blocking film  250  is distanced from conductor  252  by second BEOL dielectric layer  272 , which forms a part of layer  220 .  FIG. 7  shows ionizing radiation blocking film  250  above conductor  252  to allow a more complete block of ionizing radiation. In either scenario, an inner edge (i.e., outer edge of opening  260 ) of ionizing radiation blocking film  250  is distanced from an edge of contact  254  to prevent a short. In addition, conductor  252  laterally overlaps opening  260  of film  250  so as to form a continuous ionizing radiation blocking layer  220 . As such, even though ionizing radiation blocking layer  220  is positioned in a plurality of BEOL dielectric layers and is laterally discontinuous in any one BEOL dielectric layer, it forms a complete plane in a vertical sense because of the overlap of conductor  252  and opening  260  in film  250 , i.e., when viewed in a plan view. 
       FIG. 8  shows a graph illustrating how a dielectric including an ionizing radiation blocking material (as in  FIGS. 1-2 ) reduces soft errors.  FIG. 8  shows stopping thickness required for BEOL dielectric layer  104  and ionizing radiation blocking material  108  including copper and silicon oxide Cu x (SiO 2 ) y  versus percent of copper (Cu) for two different types of alpha particles. For example, for a controlled collapse chip connect (C4) caused alpha particle having 5.3 MeV energy, with 40% copper (weight average), BEOL dielectric layer  104  having just less than 20 μm is required to absorb the alpha particle. Similarly, for package caused alpha particle having 8.8 MeV energy, with 40% copper (weight average), BEOL dielectric layer  104  having just less than 40 μm is required to absorb the alpha particle. Similar results can be expected for the embodiments of  FIGS. 3-7 . 
     The methods as described above are used in the fabrication of integrated circuit chips. The resulting IC chips  100 ,  200  can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor. 
     The foregoing description of various aspects of the disclosure has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the disclosure to the precise form disclosed, and obviously, many modifications and variations are possible. Such modifications and variations that may be apparent to a person skilled in the art are intended to be included within the scope of the disclosure as defined by the accompanying claims.