Patent Publication Number: US-11044429-B2

Title: Charge collection gate with central collection photodiode in time of flight pixel

Description:
BACKGROUND INFORMATION 
     Field of the Disclosure 
     This disclosure relates generally to semiconductor devices, and in particular but not exclusively, relates to time of flight image sensors. 
     Background 
     Interest in three dimensional (3D) cameras is increasing as the popularity of 3D applications continues to grow in areas such as imaging, movies, games, computers, user interfaces, facial recognition, object recognition, augmented reality, and the like. A typical passive way to create 3D images is to use multiple cameras to capture stereo or multiple images. Using the stereo images, objects in the images can be triangulated to create the 3D image. One disadvantage with this triangulation technique is that it is difficult to create 3D images using small devices because there must be a minimum separation distance between each camera in order to create the 3D images. In addition, this technique is complex and therefore requires significant computer processing power in order to create the 3D images in real time. 
     For applications that require the acquisition of 3D images in real time, active depth imaging systems based on time of flight measurements are sometimes utilized. Time of flight cameras typically employ a light source that directs light at an object, a sensor that detects the light that is reflected from the object, and a processing unit that calculates the distance to the object based on the round-trip time it takes for the light to travel to and from the object. 
     A continuing challenge with the acquisition of 3D images is balancing the desired performance parameters of the time of flight camera with the physical size and power constraints of the system. For example, the power requirements of high-performance time of flight systems are considerably high as time of flight cameras typically operate at very high frequencies and require very fast charge transfer times. These challenges are further complicated by both extrinsic parameters (e.g., desired frame rate of the camera, depth resolution, and lateral resolution) as well as intrinsic parameters (e.g., quantum efficiency of the sensor, fill factor, jitter, and noise). 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Non-limiting and non-exhaustive embodiments of the present invention are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified. 
         FIG. 1  is a block diagram that shows one example of a time of flight light sensing system including an example charge collection gate with a central collection photodiode in time of flight pixels in accordance with the teachings of the present disclosure. 
         FIG. 2  is a schematic that shows one example of a time of flight light pixel circuit including example an example charge collection gate with a central collection photodiode in accordance with the teachings of the present disclosure. 
         FIG. 3  is a top down view of one example a time of flight light pixel circuit in semiconductor material including an example charge collection gate with a central collection photodiode in accordance with the teachings of the present disclosure. 
         FIG. 4  is a cross section view of one example a time of flight light pixel circuit including an example charge collection gate with a central collection photodiode in semiconductor material in accordance with the teachings of the present disclosure. 
         FIGS. 5A-5F  are example timing diagrams that illustrate operation of example of a time of flight light sensing systems including an example charge collection gate with a central collection photodiode in time of flight pixels in accordance with the teachings of the present disclosure. 
     
    
    
     Corresponding reference characters indicate corresponding components throughout the several views of the drawings. Skilled artisans will appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help to improve understanding of various embodiments of the present invention. Also, common but well-understood elements that are useful or necessary in a commercially feasible embodiment are often not depicted in order to facilitate a less obstructed view of these various embodiments of the present invention. 
     DETAILED DESCRIPTION 
     Examples directed to an example charge collection gate with central collection photodiodes in time of flight pixel structures and corresponding circuitry are described herein. In the following description, numerous specific details are set forth to provide a thorough understanding of the examples. One skilled in the relevant art will recognize, however, that the techniques described herein can be practiced without one or more of the specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail in order to avoid obscuring certain aspects. 
     Reference throughout this specification to “one example” or “one embodiment” means that a particular feature, structure, or characteristic described in connection with the example is included in at least one example of the present invention. Thus, the appearances of the phrases “in one example” or “in one embodiment” in various places throughout this specification are not necessarily all referring to the same example. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more examples. 
     Throughout this specification, several terms of art are used. These terms are to take on their ordinary meaning in the art from which they come, unless specifically defined herein or the context of their use would clearly suggest otherwise. It should be noted that element names and symbols may be used interchangeably through this document (e.g., Si vs. silicon); however, both have identical meaning. 
     As will be discussed, in the various embodiments of this disclosure, a time of flight light sensing system or image sensor having reduced power consumption and improved charge transfer speeds for each individual pixel without increased pixel sizes compared to known photogate indirect time of flight (iTOF) pixel structures are disclosed. For example, one known type of photogate iTOF pixel structure uses large long finger photogates, and toggles between activating the photogates to perform potential modulation to generate a potential gradient to fully deplete the low doped silicon substrate during integration. Generally, for higher accuracy the known iTOF pixel structure is operated at a high modulated frequency (e.g., 30 MHz-100 MHz). This type of large long photogate generates high capacitance during operation, thereby suffers from a high power consumption requirement (e.g., ˜1.2 W), especially at high frequency. 
     Another known photogate iTOF pixel structure uses high alternating current toggling through two photogates that are located at a large distance from each other. Since the high alternating current is required to flow through a silicon substrate of high resistivity, which consequently causes a large IR drop, this iTOF pixel structure also suffers from high power consumption. Furthermore, the power consumed increases significantly at higher operating frequencies. Moreover, the image charge transfer paths in these types of known iTOF pixel structures also are long, which increase the response time of the iTOF pixel structure. 
     In addition, photogates of known iTOF pixel structures require large pixel areas, thus having a negative impact on fill factor and pixel miniaturization. Furthermore, photogates of known iTOF pixel structures occupy certain space per unit pixel, which reduces the size of photodiodes and limits the full well capacity (FWC) of photodiode the pixel. 
       FIG. 1  is a block diagram that shows one example of a time of flight light sensing system  100 , in accordance with the teachings of the present disclosure. Time of flight light sensing system  100  includes light source  102 , lens  116 , image sensor  120  (including a plurality of pixels such as first pixel  122 ), and control circuitry  124 . As will be discussed in greater detail below, the plurality of pixels included in image sensor  120  include example charge collection gates with central collection photodiodes in time of flight pixels to perform indirect time of flight (iTOF) measurements in accordance with the teachings of the present invention. Control circuitry  124  is coupled to light source  102  and image sensor  120 . Image sensor  120  is positioned at a focal length f lens  from lens  116 . 
     As shown in the example, light source  102  and lens  116  are positioned at a distance L from object  130 . It is appreciated that  FIG. 1  is not illustrated to scale and that in one example the focal length f lens  is substantially less than the distance L between lens  116  and object  130 . Therefore, it is appreciated that for the purposes of this disclosure, the distance L and the distance L+focal length f lens  are substantially equal for the purposes of time of flight measurements in accordance with the teachings of the present invention. As illustrated, image sensor  120  and control circuitry  124  are represented as separate components. However, in one example, it is appreciated that image sensor  120  and control circuitry  124  may all be integrated onto a same stacked chip sensor. In other examples, image sensor  120  and control circuitry  124  may be integrated onto a non-stacked standard planar sensor. Furthermore, it is appreciated that control circuitry  124  may include one or more of time-to-digital converters. In some examples, each pixel may include one or more avalanche photodiodes (e.g., single-photon avalanche diode) that may be associated with a corresponding one of one or more time-to-digital converters. It is also appreciated, that in some examples, individual time-to-digital converters may be associated with any pre-determined number of pixels. Furthermore, it is appreciated that each pixel may have a corresponding memory for storing digital bits or signals for counting detected photons from the avalanche photodiode. 
     In the depicted example, time of flight light sensing system  100  is a 3D camera that calculates image depth information of a scene to be imaged (e.g., object  130 ) based on indirect time of flight (iTOF) measurements with image sensor  120 . In some examples, it is appreciated that although time of flight light sensing system  100  is capable of sensing 3D images, time of flight light sensing system may also be utilized to capture 2D images. In various examples, time of flight light sensing system may also be utilized to capture high dynamic range (HDR) images. 
     Continuing with the depicted example, each pixel of the plurality of pixels in the image sensor  120  determines depth information for a corresponding portion of object  130  such that a 3D image of object  130  can be generated. In the depicted example depth information is determined by measuring the delay/phase difference  106  between emitted light  104  and the received reflected light  110  to indirectly determine a round-trip time for light to propagate from light source  102  to object  130  and back to time of flight light sensing system  100 . The depth information may be based on an electric signal generated by the image sensor  120  (e.g., the first pixel  122 ) that is subsequently transferred to a storage node. 
     As illustrated, light source  102  (e.g., a light emitting diode, a vertical-cavity surface-emitting laser, or the like) is configured to emit light  104  (e.g., emitted light waves) to the object  130  over a distance L. The emitted light  104  is then reflected from the object  130  as reflected light  110  (e.g., reflected light waves), some of which propagates towards the time of flight light sensing system  100  over the distance L and is incident upon the image sensor  120  as image light. Each pixel (e.g., the first pixel  122 ) of the plurality of pixels included in the image sensor  120  includes a photodetector (e.g., one or more photodiodes, avalanche photodiodes, or single-photon avalanche diodes) to detect the image light and convert the image light into an electric signal (e.g., signal electrons, image charge, etc.). 
     As shown in the depicted example, the round-trip time for the light waves of the emitted light  104  to propagate from light source  102  to object  130  and then be reflected back to image sensor  120  can be used to determine the distance L using the following relationships in Equations (1) and (2) below: 
                     T     T   ⁢   O   ⁢   F       =       2   ⁢   L     c             (   1   )               L   =         T     T   ⁢   O   ⁢   F       ×   c     2             (   2   )               
where c is the speed of light, which is approximately equal to 3×10 8  m/s, and T TOF  corresponds to the round-trip time which is the amount of time that it takes for the light to travel to and from the object as shown in  FIG. 1 . Accordingly, once the round-trip time is known, the distance L may be calculated and subsequently used to determine depth information of object  130 .
 
     Control circuitry  124  is coupled to image sensor  120  (including first pixel  122 ) and light source  102 , and includes logics and memory that when executed causes time of flight light sensing system  100  to perform operations for determining the round-trip time. Determining the round-trip time may be based on, at least in part, timing signals generated by control circuitry  124 . For indirect time of flight (iTOF) measurements, the timing signals are representative of the delay/phase difference  106  between the light waves of when the light source  102  emits light  104  and when the photodetector detects the reflected light  110 . 
     In some examples, time of flight light sensing system  100  is included in a handheld device (e.g., a mobile phone, a tablet, a camera, etc.) that has size and power constraints determined, at least in part, based on the size of the device. Alternatively, or in addition, time of flight light sensing system  100  may have specific desired device parameters such as frame rate, depth resolution, lateral resolution, etc. 
       FIG. 2  is a schematic that shows one example of a time of flight light pixel circuit  222  including an example charge collection gate with a central collection photodiode in accordance with the teachings of the present disclosure. It is appreciated pixel circuit  222  of  FIG. 2  may be an example of a pixel  122  of the image sensor  120  as shown in  FIG. 1 , and that similarly named and numbered elements described above are coupled and function similarly below. As shown in  FIG. 2 , pixel circuit  222  includes a photodiode  232 , which is configured to accumulate image charge in response to light that is incident upon the photodiode  232 . As will discussed in greater detail below, in one example, photodiode  232  is a central collecting photodiode disposed in semiconductor material layer with a doping profile that creates a potential profile that pushes photo-generated image charge carriers to the surface of the semiconductor material towards the center of the photodiode  232  beneath a charge collection gate  262  that is coupled to the photodiode  232 . As will be discussed in greater detail below, the charge collection gate  262  is coupled and constantly biased (by a charge collection signal CCG) to generate an inversion layer in the semiconductor material layer under the charge collection gate  262  with image charge collected from the photodiode. 
     In the illustrated example, a tri-gate charge transfer block  234 A and a tri-gate charge transfer block  234 B are coupled to the charge collection gate  262  to transfer the collected photo-generated image charge carriers from the inversion layer of charge collection gate  262  with low power consumption and at improved charge transfer speeds in accordance with the teachings of the present invention. As shown in the depicted example, tri-gate charge transfer block  234 A is also coupled to a floating diffusion  246 A and a charge storage structure  244 A. Similarly, tri-gate charge transfer block  234 B is also coupled to a floating diffusion  246 B and a charge storage structure  244 B. In the depicted example, charge storage structures  244 A and  244 B are capacitors coupled to receive a strobe signal. As will be discussed, in one example, the strobe signals can be configured to pulsed between first and second values to spill over charges stored in the charge storage structures  244 A and  244 B through the tri-gate charge transfer blocks  234 A and/or  234 B to floating diffusions  246 A and  246 B as an alternate way to transfer the charges for readout in accordance with the teachings of the present invention 
     Tri-gate charge transfer block  234 A includes a transfer gate  236 A coupled to charge collection gate  262 , a shutter gate  240 A coupled to floating diffusion  246 A, and a switch gate  238 A coupled to charge storage structure  244 A.  FIG. 2  shows transfer gate  236 A having a source coupled to charge collection gate  262 , shutter gate  240 A having a drain coupled to floating diffusion  246 A, and switch gate  238 A having a drain coupled to charge storage structure  244 A. Transfer gate  236 A, shutter gate  240 A, and switch gate  238 A are electrically coupled. Transfer gate  236 A, shutter gate  240 A, and switch gate  238 A are all disposed proximate to and share a single shared channel region  250 A in the semiconductor material (as indicated with the dashed circle labeled  250 A in  FIG. 2 .) Thus, the single shared channel region  250 A of tri-gate charge transfer block  234 A is a common extended channel region of transistor gate  236 A, shutter gate  240 A, and switch gate  238 A. Restated, transfer gate  236 A, shutter gate  240 A, and switch gate  238 A share a single region. It can be appreciated that there may be no junction or source/drain doping between transfer gate  236 A, shutter gate  240 A and switch gate  238 A. In one embodiment, single share channel region  250 A shared among transfer gate  236 A, shutter gate  240 A and switch gate  238 A may be an un-doped region. In another embodiment, the single shared region shared among transfer gate  236 A, shutter gate  240 A and switch gate  238 A may be a doped region. The conduction of single shared channel region  250 A can be modulated or determined by the coupling combined biasing potential of transfer gate  236 A, shutter gate  240 A, and switch gate  238 A. 
     As such, image charge that is in the single shared channel region  250 A is simultaneously in the drain of transistor gate  236 A, in the source of shutter gate  240 A, and in the source of switch gate  238 A. As a result, transfer speeds of image charge through tri-gate charge transfer block  234 A are improved because the distances of the image charge paths through tri-gate charge transfer block  234 A are very short in accordance with the teachings of the present invention. 
     In operation, the transfer gate  236 A is configured to transfer the image charge collected by charge collection gate  262  to the single shared channel region  250 A in response to a transfer signal TX 1 , the shutter gate  240 A is configured to transfer the image charge in the single shared channel region  250 A to a floating diffusion  246 A in response to a shutter signal SHUTTER, and the switch gate  238 A is configured to couple the single shared channel region  250 A to the charge storage structure  244 A in response to a switch signal SW 1 . 
     In one example, during an exemplary integration operation, where transfer gate  236 A and shutter gate  240 A are biased to be on while the switch gate  238 A is off, the potential barrier for the conduction channel formed in between the transfer gate  236 A and the shutter gate  240 A is lowered for the electrons to transfer or tunnel through. At the same time, the potential barrier for the conduction channel formed between transfer gate  236 A and switch gate  238 A and between shutter gate  240 A and switch gate  238 A is high, such that charges are only transferred from transfer gate  236 A to floating diffusion  246 A through the conducting channel formed between the transfer gate  236 A and shutter gate  240 A and no charge is flowing to switch gate  238 A. It is appreciated by those skilled in the arts that the transfer operation of the single shared channel region can be controlled by modulating the biasing potential applied to transfer gate  236 A, switch gate  238 A, and shutter gate  240 A. 
     Tri-gate charge transfer block  234 B shares many similarities with tri-gate charge transfer block  234 A. As shown, tri-gate charge transfer block  234 B includes a transfer gate  236 B coupled to charge collection gate  262 , a shutter gate  240 B coupled to floating diffusion  246 B, and a switch gate  238 B coupled to charge storage structure  244 B. Transfer gate  236 B includes a source coupled to charge collection gate  262 , shutter gate  240 B includes a drain coupled to floating diffusion  246 B, and switch gate  238 B includes a drain coupled to charge storage structure  244 B. Transfer gate  236 B, shutter gate  240 B, and switch gate  238 B are electrically coupled and are all disposed proximate to and share a single doped region  250 B in the semiconductor material layer (as indicated with the dashed circle labeled  250 B in  FIG. 2 .) Thus, the single shared channel region  250 B of tri-gate charge transfer block  234 B is a single shared channel region  250 B shared among transistor gate  236 B, shutter gate  240 B, and switch gate  238 B. Similarly, the conduction of single shared channel region  250 B is modulated or determined by the coupling combined biasing potential of transfer gate  236 B, shutter gate  240 B, and switch gate  238 B. As such, image charge that is in the single shared channel region  250 B is simultaneously in the drain of transistor gate  236 B, in the source of shutter gate  240 B, and in the source switch gate  238 B. 
     In operation, the transfer gate  236 B is configured to transfer the image charge collected by charge collection gate  262  to the single shared channel region  250 B in response to a transfer signal TX 2 , the shutter gate  240 B is configured to transfer the image charge in the single shared channel region  250 B to a floating diffusion  246 B in response to a shutter signal SHUTTER, and the switch gate  238 B is configured to couple the single shared channel region  250 B to the charge storage structure  244 A in response to a switch signal SW 2 . 
     The example illustrated in  FIG. 2  shows that pixel circuit  222  also includes a reset transistor  252 A coupled between a voltage supply AVDD (e.g., 2.8V˜3.3V) and floating diffusion  246 A. Reset transistor  252 A is coupled to reset the floating diffusion  246 A in response to a reset signal RST 1 . A source follower transistor  254 A is coupled to the floating diffusion  246 A, and is coupled to generate a pixel output signal PIXOUT 1  in response to the image charge in the floating diffusion  246 A. A row select transistor  256 A is coupled to the source follower transistor  254 A and current source  258 A as shown. In operation, row select transistor  256 A is coupled to output the pixel output signal PIXOUT 1  from the source follower transistor  254 A in response to a row select signal RS 1 . 
     Similarly, the example illustrated in  FIG. 2  shows that pixel circuit  222  also includes a reset transistor  252 B coupled between voltage supply AVDD and floating diffusion  246 B. Reset transistor  252 B is coupled to reset the floating diffusion  246 B in response to a reset signal RST 2 . A source follower transistor  254 B is coupled to the floating diffusion  246 B, and is coupled to generate a pixel output signal PIXOUT 2  in response to the image charge in the floating diffusion  246 B. A row select transistor  256 B is coupled to the source follower transistor  254 B and current source  258 B as shown. In operation, row select transistor  256 B is coupled to output the pixel output signal PIXOUT 2  from the source follower transistor  254 B in response to a row select signal RS 2 . 
     In one example, pixel circuit  222  also includes an overflow transistor  242  coupled between a voltage supply AVDD and the photodiode  232 . In operation, the overflow transistor  242  is configured to drain excess image charge from the photodiode  232  in response to an overflow signal OFG. As such, it is appreciated that overflow transistor  242  can help improve performance of the pixel circuit  222  in bright sunny outdoor conditions because image charge generated by background ambient light can be drained through the overflow transistor  242  during readout operations. For example, after an integration period, the pixel circuit  222  begins a readout period to read out the charges from storage. However, during the readout period, light is still incident on photodiode  232 , which can interfere with image charge readings. As such, the overflow transistor  242  can be turned on during the readout period to drain these charges into the overflow transistor  242  drain node. 
     In one example, pixel circuit  222  also includes a common mode transistor  248  coupled between floating diffusion  246 A and floating diffusion  246 B. In operation, the common mode transistor  248  is configured to reset a common mode level between floating diffusion  246 A and floating diffusion  246 B in response to a common mode reset signal COM to help to reduce noise in pixel circuit  222 . In particular, it is appreciated that there can be many factors that can cause a potential difference between floating diffusion  246 A and floating diffusion  246 B, such as for example process variations, transistor mismatches, offset variations, etc. In order to help cancel the noise that can result from a potential difference or offset between floating diffusion  246 A and floating diffusion  246 B, a common mode level can be provided by enabling and disabling (e.g., turning on and turning off) common mode transistor  248  shortly after sampling signals from floating diffusion  246 A and floating diffusion  246 B. 
     In operation, pixel circuit  222  may be reset to pre-charge the elements of pixel circuit  222  to initialized values before the integration period begins. In one example, during the initial pre-charge or reset period, the overflow gate  242 , transfer gates  236 A and  236 B, reset transistors  252 A and  252 B, switch gates  238 A and  238 B, and shutter gates  240 A and  240 B are all enabled to pre-charge or reset the charge in photodiode  232 , charge storage structures  244 A and  244 B, and floating diffusions  246 A and  246 B to initialized values. It is appreciated by those skilled in the arts that initial reset values may be configured based on the supplied voltage (e.g., voltage supply AVDD) and the power consumption requirements for pixel circuit  222 . 
     Afterwards, the integration period may begin so that image charge is photo-generated in photodiode  232  in response to light (e.g., reflected light  110  from object  130  of  FIG. 1 ) that illuminates photodiode  232 . The accumulated image charge photo-generated in photodiode  232  is collected by charge collection gate  262  in an inversion layer in the semiconductor material. The image charge collected by the charge collection gate  262  is transferred from the inversion layer to single shared channel region  250 A of tri-gate charge transfer block  234 A by transfer gate  236 A in response to transfer signal TX 1 . In addition, the image charge collected by the charge collection gate  262  may also be transferred to single shared channel region  250 B of tri-gate charge transfer block  234 B by transfer gate  236 B in response to transfer signal TX 2 . The image charge in single shared channel region  250 A and in single shared channel region  250 B may then be transferred to floating diffusion  246 A and floating diffusion  246 B by shutter gate  240 A and shutter gate  240 B, respectively, in response to respective SHUTTER signals. 
     Transfer gates  236 A and  236 B are toggled to switch on and off to collect the image charge collected by the charge collection gate  262  from photodiode  232 . In one example, the transfer signal TX 1  and the transfer signal TX 2  are pulse signals configured to have different phases driving the transfer gate  236 A and the transfer gate  236 B with different delays during the integration period to measure the phase shift information of incident light (e.g., reflected light  110  in  FIG. 1 ) so as to determine the distance between an object (e.g., the object  130 ) and the pixel  222  circuit of the image sensor. In one example, the driving voltage (e.g., the signal level of transfer signal TX 1  and TX 2 ) for the transfer gate  236 A and the transfer gate  236 B may be ranged between 1.0V-2.0V. 
     In various examples, the full well capacity (FWC) of pixel circuit  222  may also be adjusted in by switch gates  238 A and  238 B in response to respective switch signals SW 1  and SW 2  to adjust the conversion gain of pixel circuit  222  to accommodate lighting conditions. For instance, by enabling switch gates  238 A and  238 B during the integration period, image charge may be stored in charge storage structures  244 A and  244 B as well as floating diffusions  246 A and  246 B, which increases the FWC to reduce the conversion gain of pixel circuit  222  for bright outdoor conditions. In the alternative, by disabling switch gates  238 A and  238 B, image charge is not stored in charge storage structures  244 A and  244 B, which decreases the FWC to increase the conversion gain of pixel circuit  222  for dimmer indoor conditions. Therefore, it is appreciated that pixel circuit  222  may be suitable for both indoor or outdoor conditions to sense high dynamic range (HDR) image data in response to switch signals SW 1  and SW 2  in accordance with the teachings of the present invention. 
     The image charge in floating diffusion  246 A is converted to a pixel output signal PIXOUT 1  by source follower transistor  254 A and the image charge in floating diffusion  246 B is converted to a pixel output signal PIXOUT 2  by source follower transistor  254 B. During the readout period of pixel circuit  222 , the pixel output signal PIXOUT 1  may be read out by enabling the row select transistor  256 A in response to a row select signal RS 1 , and/or the pixel output signal PIXOUT 2  may be read out by enabling the row select transistor  256 B in response to a row select signal RS 2 . 
     In exemplary operation, normalized output pixel values may also be provided with pixel  222  by generating correlated double sampling (CDS) pixel outputs for PIXOUT 1  and PIXOUT 2  with a sampled reset signal. To this end, the CDS pixel output values for PIXOUT 1  and PIXOUT 2  may be determined by measuring the charge in the floating diffusions  246 A and  246 B twice and then determining the difference between each of the two image charge measurements and the sampled reset signal to cancel out noise, such as for example kTC noise, or the like. One of the measurements is sampled after a reset of the floating diffusions  246 A and  246 B in response to enabling the reset transistors  252 A and  252 B in response to reset signals RST 1  and RST 2 , respectively. The other measurement is sampled after transferring the image charge accumulated in photodiode  232  to floating diffusions  246   a  and  246 B through transfer gates  236 A and  236 B in response to transfer signals TX 1  and TX 2 , and through shutter gates  240 A and  240 B in response to respective SHUTTER signals. In various example, the reset readings from floating diffusions  246 A and  246 B may be sampled before or after the sampling of the signal values from floating diffusions  246 A and  246 B in accordance with the teachings of the present invention. 
       FIG. 3  is a top down view or plan view of one example a time of flight light pixel circuit  322  in semiconductor material including an example charge collection gate with an example central collection photodiode in accordance with the teachings of the present disclosure. It is appreciated pixel circuit  322  of  FIG. 3  may be an example of pixel circuit  222  of  FIG. 2 , and/or of a pixel  122  of the image sensor  120  as shown in  FIG. 1 , and that similarly named and numbered elements described above are coupled and function similarly below. As shown in  FIG. 3 , pixel circuit  322  includes a photodiode  332  disposed in a semiconductor material layer  370  to accumulate image charge in response to light incident upon the photodiode  332 . A charge collection gate  362  is disposed over the photodiode  332  in semiconductor material layer  370 . In the example, the charge collection gate  362  is coupled to the photodiode  332  to generate an inversion layer  376  in the semiconductor material layer  370  under the charge collection gate  362  to collect the image charge from the photodiode  332  in accordance with the teachings of the present invention. 
     As shown in the depicted example, a tri-gate charge transfer block  334 A is coupled to the charge collection gate  362  to transfer the image charge collected in the inversion layer  376  of the charge collection gate  362 . The tri-gate charge transfer block  334 A includes a single shared channel region  350 A disposed in the semiconductor material layer  370 . In the example, the single shared channel region  350 A is a single shared channel region that is shared by transfer gate  336 A, shutter gate  340 A, and switch gate  338 A. As such, the transfer gate  336 A is disposed proximate to the single shared channel region  350 A, and the transfer gate  336 A is configured to transfer the image charge from the inversion layer  376  of the charge collection gate  362  to the single shared channel region  350 A in response to a transfer signal TX 1 . The shutter gate  340 A is disposed proximate to the single shared channel region  350 A, and the shutter gate  340 A is configured to transfer the image charge in the single shared channel region  350 A to a floating diffusion  346 A disposed in the semiconductor material layer  370  in response to a shutter signal SHUTTER. The switch gate  338 A is disposed proximate to the single shared channel region  350 A, and the switch gate  338 A is configured to couple the single shared channel region  350 A to a charge storage structure  344 A disposed in the semiconductor material layer  370  in response to a switch signal SW 1 . 
     As shown in the illustrated example, pixel circuit  322  also includes tri-gate charge transfer block  334 B, which is coupled to the charge transfer gate  362 . It is appreciated that tri-gate charge transfer block  334 B is similar to tri-gate charge transfer block  334 A as tri-gate charge transfer block  334 B includes a single shared channel region  350 B disposed in the semiconductor material layer  370 . Transfer gate  336 B, shutter gate  340 B, and switch gate  338 B are disposed proximate to single shared channel region  350 B. Transfer gate  336 B is configured to transfer the image charge collected in the inversion layer  376  of the charge collection gate  362  to the single shared channel region  350 B in response to a transfer signal TX 2 . Shutter gate  340 B is configured to transfer the image charge in the single shared channel region  350 B to a floating diffusion  346 B disposed in the semiconductor material layer  370  in response to shutter signal SHUTTER. The switch gate  338 B is configured to couple the single shared channel region  350 B to a charge storage structure  344 B disposed in the semiconductor material layer  370  in response to a switch signal SW 2 . 
     The example illustrated in  FIG. 3  also illustrates the row select gates  356 A and  356 B, the source follower gates  354 A and  354 B, reset gates  352 A and  352 B, and common mode gate  348  of pixel circuit  322  arranged over semiconductor material layer  370  around the photodiode  332 . In addition, the overflow gate  342  is also disposed over the semiconductor material layer  370  and is coupled to the photodiode  332  to drain the excess image charges from the photodiode  332  in response to an overflow signal OFG. In the depicted example, it is appreciated that the overflow gate  342  is disposed a sufficient distance from the charge collecting point of inversion layer  376  so as to prevent unwanted image charge loss. 
     In one exemplary operation, the charge storage structures are used to enhance the full well capacity, for example, for an outdoor image application. During the integration, switch gates  338 A,  338 B are turned on with switch signals SW 1 , SW 2 , respectively while transfer gates  336 A and  336 B are pulsed to turn on alternatively with transfer signals TX 1 , TX 2 . When transfer gate  336 A is pulsed on while transfer gate  336 B is pulsed off, the photo-generated image charges collected in the inversion layer  376  of the charge collection gate  362  are transferred to the charge storage structure  344 A through the single shared channel region  350 A formed between transfer gate  336 A and switch gate  338 A. When transfer gate  336 B is pulsed on while transfer gate  336 A is pulsed off, the photo-generated image charges collected in the inversion layer  376  of the charge collection gate  362  are transfer to charge storage structure  344 B through the single shared channel region  350 B formed between transfer gate  336 B and switch gate  338 B. At the end of integration, overflow gate  342  turns on in response to overflow signal OFG to drain excess image charges from photodiode  332 . During read out, transfer gates  336 A and  336 B are turned off while switch gates  338 A,  338 B and shutter gates  340 A,  340 B are turned on to facilitate image charge transfer to floating diffusions  346 A,  346 B. Image charges stored in the charge storage structure  344 A are transferred to floating diffusion  346 A through the single shared channel region  350 A between the switch gate  338 A and shutter gate  340 A. Image charges stored in charge storage structure  344 B are transferred to floating diffusion  346 B through single shared channel region  350 B between switch gate  338 B and shutter gate  340 B. 
     In one exemplary application for small full well capacity with high conversion gain, for example, for an indoor imaging application, only floating diffusions are used for storing charges. During the integration, switch gates  338 A,  338 B are turned off while shutter gates  340 A,  340 B are turned on with the shutter signal SHUTTER while transfer gates  336 A,  336 B are pulsed to turn on alternatively with transfer signals TX 1 , TX 2 . When the transfer gate  336 A is pulsed on while transfer gate  336 B is pulsed off, the photo-generated images charges collected are transferred from the inversion layer  376  of the charge collection gate  362  to floating diffusion  346 A through single shared channel region  350 A formed between transfer gate  336 A and shutter gate  340 A. When transfer gate  336 B is pulsed on while transfer gate  336 A is pulsed off, the photo-generated image charges collected are transferred from the inversion layer  376  of the charge collection gate  362  to floating diffusion  346 B through the single shared channel region  350 B formed between transfer gate  336 B and the shutter gate  340 B. At the end of integration, overflow gate  342  turns on in response to the overflow signal OFG to drain excess image charges from photodiode  332 . During read out, image charges stored in floating diffusions  346 A and  346 B are read out, respectively. 
     As shown in the depicted example and as will be described in further detail below, it is appreciated that photodiode  332  is a central collecting photodiode disposed in semiconductor material layer  370  with a doping profile that creates a potential profile that pushes photo-generated image charge carriers to the surface of the semiconductor material layer  370  towards the center of the photodiode  332 . For instance, in the depicted example and as will be described in further detail below, photodiode  332  is illuminated through a backside surface of semiconductor material layer  370 . Image charge is photo-generated in photodiode  332 , and the doping profile and structure of photodiode  332  pushes the image charge accumulated in photodiode  332  towards a front side surface of semiconductor material layer  370  and towards the center of photodiode  332  near the front side surface of semiconductor material layer  370 , which is below the charge collection gate  362 . In one example, the cross sectional area of the doped region of photodiode  332  closest to the backside surface of semiconductor material layer  370  is a wider cross sectional area, which is illustrated with dashed line  332 - 2  in  FIG. 3 . In the example, the cross sectional area of the doped region of photodiode  332  closest to the front side surface of semiconductor material layer  370  is a narrower cross sectional area, which is illustrated with dashed line  332 - 1  in  FIG. 3 . The charge collection gate  362  is charge collection gate is coupled to be biased with a constant bias voltage (e.g., charge collection signal CCG) to collect the image charge from the photodiode  332  into the inversion layer  376 , which is coupled to the transfer gates  336 A and  336 B of tri-gate charge transfer block  234 A,  234 B, respectively. 
     To illustrate,  FIG. 4  is a cross section view of one example a pixel circuit  422  including an example charge collection gate  462  with a central collection photodiode  432  in semiconductor material layer  470  in accordance with the teachings of the present disclosure. It is appreciated pixel circuit  422  of  FIG. 4  may be a cross section view example of pixel circuit  322  along dashed line A′-A of  FIG. 3 , and/or pixel  222  of  FIG. 2 , and/or of a pixel  122  of the image sensor  120  as shown in  FIG. 1 , and that similarly named and numbered elements described above are coupled and function similarly below. As shown in  FIG. 4 , pixel circuit  422  includes a photodiode  432  disposed in a semiconductor material layer  470 . Charge collection gate  462 , transfer gates  436 A and  436 B, and switch gates  438 A and  438 B are arranged along the front side surface  474  surface of semiconductor material layer  470  as shown. In one example, charge collection gate  462 , transfer gates  436 A and  436 B, and switch gates  438 A and  438 B are formed with polysilicon, and the semiconductor material layer  470  is formed from a p-type epitaxial silicon wafer. In one example, the semiconductor material  470  includes a p-type epitaxial silicon layer (or a p-type semiconductor substrate layer), and photodiode  432  includes n-type dopants that are implanted into the p-type epitaxial silicon layer of semiconductor material layer  470 . In other examples, it appreciated of course the polarities of the dopants may be switched such that photodiode  432  may be formed from p-type dopants that are implanted into an n-type epitaxial silicon layer of the semiconductor material  470 . 
     In the illustrated example, the cross sectional area of the portion  432 - 2  of photodiode  432  that is closer to the backside surface  472  of semiconductor material layer  470  is a wider cross sectional area, and the cross sectional area of the portion  432 - 1  of photodiode  432  that is closer to the front side surface  474  of semiconductor material layer  470  is a narrower cross sectional area. In one example, during fabrication, the photodiode  432  is implanted in the semiconductor material layer  470  with a deep n-type photodiode implant with a wider open n-type photodiode mask, and a middle/shallow n-type photodiode implant is performed with a smaller or narrower open n-type photodiode mask. 
     The example depicted in  FIG. 4  also shows that photodiode  432  has a gradient doping profile. For instance, in one example, the doping profile of the doped region of photodiode  432  has a doping concentration of approximately  1 E 12  atoms per cubic centimeter (atoms/cm 3 ) at the portion  432 - 2  of photodiode  432  that is closest to the backside surface  472  of semiconductor material layer  470 , which increases gradually to approximately  1 E 15  atoms/cm 3  at a middle portion of photodiode  432  between the backside surface  472  and front side surface  474  of semiconductor material layer  470 . In the example, the doping concentration continues to increase gradually to 1E16 atoms/cm 3  at the front side surface  474  surface of semiconductor material layer  470  beneath the charge collection gate  476  as shown. As shown in the depicted example, the potential in the photodiode  432  therefore increases gradually from the backside surface  472  to the front side surface  474  of semiconductor material layer  470 . It is appreciated that the specific doping concentrations provided herewith are for explanation purposes, and that in other examples, different specific doping concentrations may also be contemplated in accordance with the teachings of the present invention. 
     During operation, light  410  (e.g., light that is reflected from object  130  in  FIG. 1 ) is directed through the backside surface  472  of semiconductor material layer  470  and into photodiode  432 . Image charge carriers, which are illustrated as electrons “e-” in  FIG. 4 , are photo-generated in photodiode  432  in response to the incident reflected light  410 . In the depicted example, it is appreciated that the shape and concentration of the gradual doping profile in photodiode  432  create a potential profile that increases gradually from the backside surface  472  to the front side surface  474  of semiconductor material layer  470  as shown, which pushes the image charge carriers e- up to the front side surface  474  and towards the center of photodiode  432  at the front side surface  474  beneath the charge collection gate  462 . 
     As shown in the depicted example, the charge collection gate  462  is coupled to be biased with a static constant bias voltage (e.g., charge collection signal CCG), which generates the inversion layer  476  that collects the image charge e- from the photodiode  432  into the inversion layer  476  at the front side surface  474  of semiconductor material layer  470  under the charge collection gate  462 . In one example, the collected image charge carriers e- are transferred from the inversion layer  476  of charge collection gate  462  by applying corresponding transfer signals TX 1  and TX 2  to the transfer gates  436 A and  436 B, respectively, and switch signals SW 1  and SW 2  to switch gates  438 A and  438 B, respectively. In one example, the first transfer signal TX 1  and the second transfer signal TX 1  are oscillating pulse trains that are out of phase with one another to alternatingly transfer the image charge e- from the inversion layer  476 . As such, transfer gates  436 A and  436 B are switch on/off constantly to move the image charge e- from the inversion layer  476  of the charge collection gate  462  to switch gates SW 1   438 A and SW 2   438 B as shown. 
     It is appreciated that with the static biased charge collection gate  462  collecting the image charge in the inversion layer  476 , the required voltage levels for the first and second transfer signals TX 1  and TX 2  to transfer the image charge from the inversion layer  476  are reduced, which can reduce power consumption of pixel circuit  422  in accordance with the teachings of the present invention. Stated in another way, the required voltage swings of first and second transfer signals TX 1  and TX 2  are reduced when compared to having to transfer the image charge from photodiode  432  without the inversion layer  476  of charge collection gate  462 . For instance, in one example, voltage swings of less than 1.5 volts are needed for transfer signals TX 1  and TX 2  and the constant bias voltage. With the smaller required voltages for the constant bias and the first and second transfer signals TX 1  and TX 2 , it is further appreciated therefore that smaller gate areas of transfer gates  436 A and  436 B are needed, and that switching speeds may be further increased in accordance with the teachings of the present invention. 
       FIGS. 5A-5F  are various example timing diagrams  564  that illustrate operation of example of a time of flight light sensing systems including example charge collection gates with central collection photodiodes in time of flight pixels in accordance with the teachings of the present disclosure. It is appreciated that the timing diagrams may reference elements discussed above with respect to  FIGS. 1-4 , and as such similarly named and numbered elements described above are coupled and function similarly below. 
     As shown in  FIG. 5A , an example of operations for the pixel operating in a 3D depth mode begin with a pre-charge reset period, during which time the elements in the pixel are pre-charged or reset to initial values. As such, during the initial pre-charge or reset period, the overflow signal OFG  542 , the transfer signals TX 1   536 A and TX 2   536 B, the reset signals RST 1  and RST 2   552 , the switch signals SW 1  and SW 2   538 , and shutter signal  240  are all pulsed high, while the strobe signal  544 , row select signals RS 1   546 A and RS 2   546 B, and common mode reset signal COM  548  remain low. As shown in the example, the charge collection gate bias voltage  562  remains regulated at the constant voltage during the pre-charge reset period, the integration period, the readout period, and the idle period. 
     During the integration period, image charge carriers are photo-generated in the photodiode in response to incident light. The regulated charge collection gate bias voltage  562  applied to the charge collection gate generates an inversion layer with the photo-generated image charge carriers that are collected from the photodiode. The transfer signals TX 1   536 A and TX 2   536 B are alternatingly pulsed, which alternatingly transfers or pumps the photo-generated charge from the inversion layer to either to the first single shared channel region or the second single shared channel region in repeated individual succession during the integration period of the pixel. In addition, the switch signals SW 1  and SW 2   538  as well as the shutter signal  540  are enabled (e.g., set at a high logic signal level) during the integration period, which enables the charge transferred from the inversion layer to be stored in both floating diffusions as well as in the charge storage structures during the integration period. As such, the pixel is set for high FWC and low conversion gain in the depicted example in accordance with the teachings of the present invention. 
     During the readout period, the overflow signal OFG  542  is enabled, which enables the overflow transistor to drain excess image charge from the photodiode. As such, performance of the pixel can be improved in bright sunny outdoor conditions so that image charge generated by background ambient light can be drained through the overflow transistor during the readout period. The row select signals RS 1   546 A and RS 2   546 B are enabled, which enables the pixel output signals PIXOUT 1  and PIXOUT 2  to be read out from the pixel. The pixel output signals are sampled and held to sample the signal output values of the pixel, as indicated with the SHS  568  pulse. In the example, the floating diffusions are then reset, as indicated with the pulse of the reset signals RST 1  and RST 2   552 . In one example, the common mode reset signal COM  548  may also be optionally pulsed as the reset signals RST 1  and RST 2   552  are pulsed to reset the floating diffusions to a common reset level, e.g., supply voltage of the voltage supply. In the example, the pixel output signals are then sampled and held again to sample the reset output values of the pixel, as indicated with the SHR  566  pulse. 
     As such, it is appreciated that the difference between the sampled signal output values and the sampled reset signal values can be computed to determine the pixel output values, for example by a differential amplification circuitry included in the control circuit  124  of  FIG. 1 , in accordance with the teachings of the present invention. 
     It is appreciated by skilled artisans that in the operation illustrated by  FIG. 5A , the pixel output signal associated with photo-generated image charges is sampled prior to the sampling of the reset signal, and as such the image signal level and reset signal level are not correlated. Thus, no correlated double sampling (CDS) operation may be performed. But because the image charge storages are shared with charge storage structures during the image signal read out period as switch signals SW 1  and SW 2   538  are enabled after the reset of the floating diffusions, the full well capacity for the photodiode can be maximized and therefore suitable for outdoor imaging applications. 
     As shown in  FIG. 5B , another example of operations for the pixel operating in a 3D depth mode begin with the pre-charge reset period, during which time the elements in the pixel are pre-charged or reset to initial values. As such, during the initial pre-charge or reset period, the overflow signal OFG  542 , the transfer signals TX 1   536 A and TX 2   536 B, the reset signals RST 1  and RST 2   552 , the switch signals SW 1  and SW 2   538 , and shutter signal  540  are all pulsed high, while the strobe signal  544 , row select signals RS 1   546 A and RS 2   546 B, and common mode reset signal COM  548  remain low. As shown in the example, the charge collection gate bias voltage  562  remains regulated at the constant voltage during the pre-charge reset period, the integration period, the readout period, and the idle period. 
     During the integration period, image charge carriers are photo-generated in the photodiode in response to incident light. The regulated charge collection gate bias voltage  562  applied to the charge collection gate generates an inversion layer with the photo-generated image charge carriers that are collected from the photodiode. The transfer signals TX 1   536 A and TX 2   536 B are alternatingly pulsed, which alternatingly transfers or pumps the photo-generated charge from the inversion layer to either to the first single shared channel region or the second single shared channel region in repeated individual succession during the integration period of the pixel. In addition, the switch signals SW 1  and SW 2   538  remain disabled while the shutter signal  540  is enabled during the integration period. As such, the charge transferred from the inversion layer is stored in both floating diffusions, but not in the charge storage structures during the integration period. As such, the pixel is set for low FWC and high conversion gain in the depicted example in accordance with the teachings of the present invention. 
     During the readout period, the overflow signal OFG  542  is enabled, which enables the overflow transistor to drain excess image charge from the photodiode. As such, performance of the pixel can be improved in bright sunny outdoor conditions so that image charge generated by background ambient light can be drained through the overflow transistor during the readout period. The shutter signal  540  and row select signals RS 1   546 A and RS 2   546 B are enabled during the readout period, which enables the pixel output signals PIXOUT 1  and PIXOUT 2  to be read out from the pixel. The pixel output signals are sampled and held during the readout period to sample the signal output values of the pixel, as indicated with the SHS  568  pulse. In the example, the floating diffusions are then reset, as indicated with the pulse of the reset signals RST 1  and RST 2   552 . In one example, the common mode reset signal COM  548  may also be optionally pulsed as the reset signals RST 1  and RST 2   552  are pulsed to reset the floating diffusions to a common reset level, e.g., supply voltage of the voltage supply. In the example, the pixel output signals are then sampled and held again to sample the reset output values of the pixel, as indicated with the SHR  566  pulse. 
     It is appreciated by skilled artisans that in the operation illustrated by  FIG. 5B , the pixel output signal associated with photo-generated image charges is also sampled prior to the sampling of the reset signal, thus no correlated double sampling (CDS) operation may be performed. It is appreciated that the difference between the sampled signal output values and the sampled reset signal values may be computed, for example by a differential amplification circuitry included in the control circuit  124  of  FIG. 1 , to determine the pixel output values in accordance with the teachings of the present invention. 
     It is appreciated that the pixel may be controlled, for example, by the control circuit  124  of  FIG. 1  to selectively operate as illustrated in  FIG. 5A  for outdoor applications with the environment having a brighter light setting, or as illustrated in  FIG. 5B  for indoor applications with the environment having a darker light setting. 
     As shown in  FIG. 5C , yet another example of operations for the pixel operating in a 3D depth mode begin with the pre-charge reset period, during which time the elements in the pixel are precharged or reset to initial values. As such, during the initial pre-charge or reset period, the overflow signal OFG  542 , the transfer signals TX 1   536 A and TX 2   536 B, the reset signals RST 1  and RST 2   552 , the switch signals SW 1  and SW 2   538 , and shutter signal  540  are all pulsed high, while the strobe signal  544 , row select signals RS 1   546 A and RS 2   546 B, and common mode reset signal COM  548  remain low. As shown in the example, the charge collection gate bias voltage  562  remains regulated at the constant voltage during the pre-charge reset period, the integration period, the readout period, and the idle period. 
     During the integration period, image charge carriers are photo-generated in the photodiode in response to incident light. The regulated charge collection gate bias voltage  562  applied to the charge collection gate generates an inversion layer with the photo-generated image charge carriers that are collected from the photodiode. The transfer signals TX 1   536 A and TX 2   536 B are alternatingly pulsed, which alternatingly transfers or pumps the photo-generated charge from the inversion layer to either to the first single shared channel region or the second single shared channel region in repeated individual succession during the integration period of the pixel. In addition, the shutter signal  540  remains disabled while the switch signals SW 1  and SW 2   538  are enabled during the integration period. As such, the charge transferred from the inversion layer is stored in the charge storage structures, but not in the floating diffusions during the integration period in the depicted example. 
     During the readout period, the overflow signal OFG  542  is enabled, which enables the overflow transistor to drain excess image charge from the photodiode. As such, performance of the pixel can be improved in bright sunny outdoor conditions so that image charge generated by background ambient light can be drained through the overflow transistor during the readout period. In the example, the switch signals SW 1  and SW 2   538  are initially disabled during the readout period, which isolates the charged stored in the charge storage structures from the floating diffusions. The shutter signal  540  and the row select signals RS 1   546 A and RS 2   546 B are enabled, which enables the pixel output signals PIXOUT 1  and PIXOUT 2  to be read out from the pixel. The floating diffusions are then reset, as indicated with the pulse of the reset signals RST 1  and RST 2   552 . In one example, the common mode reset signal COM  548  is also pulsed as the reset signals RST 1  and RST 2   552  are pulsed to reset the floating diffusions to a common reset level, e.g., supply voltage of the voltage supply. After the reset, the switch signals SW 1  and SW 2   538  are then enabled in the example so that the charge stored in the charge storage structures during integration can now be transferred to the floating diffusions. The pixel output signals are then sampled and held to sample the signal output values of the pixel, as indicated with the SHS  568  pulse. In the example, the common mode reset signal COM  548  is pulsed again after the signal output values are sampled to reset the common mode level between the first and second floating diffusions. In the example, the pixel output signals are then sampled and held again to sample the reset output value of the pixel, as indicated with the SHR  566  pulse. It is appreciated by skilled artisans that in the operation illustrated by  FIG. 5C , the pixel output signal associated with photo-generated image charges is also sampled prior to the sampling of the reset signal, thus no correlated double process operation may be performed. It is further appreciated that the difference between the sampled reset signal values and the sampled signal output values can be determined, for example by a differential amplification circuitry included in the control circuit  124  of  FIG. 1 , to determine the pixel output values in accordance with the teachings of the present invention. The operation illustrated by  FIG. 5C  may be selected to maximize full well capacity, i.e., the combination capacity of the charge storage structures and the floating diffusions, but with lower conversion gain, and hence is applicable for outdoor imaging applications. 
     As shown in  FIG. 5D , still another example of operations for the pixel operating in a 3D depth mode begin with the pre-charge reset period, during which time the elements in the pixel are pre-charged or reset to initial values. As such, during the initial pre-charge or reset period, the overflow signal OFG  542 , the transfer signals TX 1   536 A and TX 2   536 B, the reset signals RST 1  and RST 2   552 , the switch signals SW 1  and SW 2   538 , and shutter signal  540  are all pulsed high, while row select signals RS 1   546 A and RS 2   546 B, and common mode reset signal COM  548  remain low. In the example, the strobe signal  544  is set to a first voltage level. As shown in the example, the charge collection gate bias voltage  562  remains regulated at the constant voltage during the pre-charge reset period, the integration period, the readout period, and the idle period. 
     During the integration period, image charge carriers are photo-generated in the photodiode in response to incident light. The regulated charge collection gate bias voltage  562  applied to the charge collection gate generates an inversion layer with the photo-generated image charge carriers that are collected from the photodiode. The transfer signals TX 1   536 A and TX 2   536 B are alternatingly pulsed, which alternatingly transfers or pumps the photo-generated charge from the inversion layer to either to the first single shared channel region or the second single shared channel region in repeated individual succession during the integration period of the pixel. In addition, the shutter signal  540  remains disabled while the switch signals SW 1  and SW 2   538  are enabled during the integration period. As such, the charge transferred from the photodiode is stored in the charge storage structures, but not in the floating diffusions during the integration period in the depicted example. In the example, the strobe signal  544  coupled to the charge storage structures remains set to the first voltage level during integration. 
     During the readout period, the overflow signal OFG  542  is enabled, which enables the overflow transistor to drain excess image charge from the photodiode. As such, performance of the pixel can be improved in bright sunny outdoor conditions so that image charge generated by background ambient light can be drained through the overflow transistor during the readout period. In the example, the switch signals SW 1  and SW 2   538  are disabled during the readout period, which turns off the switch gates to isolate the charged stored in the charge storage structures from the floating diffusions. The shutter signal  540  and the row select signals RS 1   546 A and RS 2   546 B are enabled, which enables the pixel output signals PIXOUT 1  and PIXOUT 2  to be read out from the pixel. The floating diffusions are then reset, as indicated with the pulse of the reset signals RST 1  and RST 2   552 . In one example, the common mode reset signal COM  548  is also pulsed as the reset signals RST 1  and RST 2   552  are pulsed to reset the floating diffusions to a common reset level, e.g., supply voltage of the voltage supply. In the example, the pixel output signals are then sampled and held to sample the reset output value of the pixel, as indicated with the SHR  566  pulse. After the reset output value of the pixel has been sampled, the strobe signal  544  is pulsed or toggled from the first level to a second level as shown so that the charges stored in the first and second charge storage structures spill over to the first and second floating diffusions through the first and second switch gates, which remain disabled by the switch signals SW 1  and SW 2   538  during the readout period of the pixel. In the example, the second level of the strobe signal  544  is less than the first level. The pixel output signals are then sampled and held again to sample the signal output values of the pixel, as indicated with the SHS  568  pulse. As such, It is appreciated by skilled artisans that in the operation illustrated by  FIG. 5D , the pixel output signal associated with photo-generated image charges is sampled after the sampling of the reset signal, thus a correlated double sampling (CDS) operation may be performed to determine the difference between the sampled reset signal values and the sampled signal output values, so as to determine the CDS pixel output values in accordance with the teachings of the present invention. 
     In one embodiment, a wider dynamical range of the pixel may be further achieved by sampling the signal read out multiple times with different conversion gains. The conversion gain may be varied with selectively turned on switch gates and shutter gates. For instance, during a first time interval of read out, the switch gates and shutter gates can be turned on to provide low conversion gain for signal output read out as the conversion gain for the pixel will be determined by the capacitance of charge storage structure and the floating diffusions. During a second time interval of read out, the switch gates may be turned off while shutter gates are turned on to provide mid-level conversion gain for signal output read out as the conversion gain for the pixel will be determined by the capacitance of the shutter gates and the floating diffusion. During a third time interval of read out, the switch gates and shutter gates may be turned off to provide high conversion gain for signal output as the conversion gain for the pixel in the third time interval will be determined by the effective capacitance of the floating diffusion. 
     As shown in  FIG. 5E , an example of operations for the pixel operating in an a 2D intensity mode begin with a pre-charge reset period, during which time the elements in the pixel are pre-charged or reset to initial values. As such, during the initial pre-charge or reset period, the overflow signal OFG  542 , the transfer signals TX 1   536 A and TX 2   536 B, the reset signals RST 1  and RST 2   552 , the switch signals SW 1  and SW 2   538 , and shutter signal  540  are all pulsed high, while the strobe signal  544 , row select signals RS 1   546 A and RS 2   546 B, and common mode reset signal COM  548  remain low. As shown in the example, the charge collection gate bias voltage  562  remains regulated at the constant voltage during the pre-charge reset period, the integration period, the readout period, and the idle period. 
     During the integration period, image charge carriers are photo-generated in the photodiode in response to incident light. The regulated charge collection gate bias voltage  562  applied to the charge collection gate generates an inversion layer with the photo-generated image charge carriers that are collected from the photodiode. The transfer signal TX 1   536 A is enabled while the transfer signal TX 2   536 B is disabled. Thus, it is appreciated that in the depicted example, first transfer transistor, and first floating diffusion are utilized to generate the first output pixel value PIXOUT 1 . With the transfer signal TX 1   536 A enabled, the photo-generated charge collected in the inversion layer is transferred to the first single shared channel region during the integration period of the pixel. In addition, the switch signals SW 1  and SW 2   538  remain disabled while the shutter signal  540  is enabled during the integration period. As such, the charge transferred from the inversion layer is stored in the first floating diffusion, but not in the charge storage structures during the integration period. As such, the pixel is set for low FWC and high conversion gain in the depicted example in accordance with the teachings of the present invention. 
     During the readout period, the overflow signal OFG  542  is enabled, which enables the overflow transistor to drain excess image charge from the photodiode. As such, performance of the pixel can be improved in bright sunny outdoor conditions so that image charge generated by background ambient light can be drained through the overflow transistor during the readout period. The shutter signal  540  and row select signals RS 1   546 A and RS 2   546 B are enabled during the readout period, which enables the pixel output signal PIXOUT 1  to be read out from the pixel. The pixel output signals are sampled and held during the readout period to sample the signal output value of the pixel, as indicated with the SHS  568  pulse. In the example, the floating diffusions are then reset, as indicated with the pulse of the reset signals RST 1  and RST 2   552 . In one example, the common mode reset signal COM  548  may also be optionally pulsed as the reset signals RST 1  and RST 2   552  are pulsed to reset the floating diffusions to a common reset level, e.g., supply voltage of the voltage supply. In the example, the pixel output signals are then sampled and held again to sample the reset output values of the pixel, as indicated with the SHR  566  pulse. It is appreciated by skilled artisans that in the operation illustrated by  FIG. 5E , the pixel output signal associated with photo-generated image charges is also sampled prior to the sampling of the reset signal, and thus no correlated double sampling operation may be performed. It is further appreciated that the difference between the sampled signal output values and the sampled reset signal values can be computed, for example by a differential amplification circuitry included in the control circuit  124  of  FIG. 1 , to determine the pixel output value in accordance with the teachings of the present invention. 
     As shown in  FIG. 5F , another example of operations for the pixel operating in an a 2D intensity mode begin with a pre-charge reset period, during which time the elements in the pixel are pre-charged or reset to initial values. As such, during the initial pre-charge or reset period, the overflow signal OFG  542 , the transfer signals TX 1   536 A and TX 2   536 B, the reset signals RST 1  and RST 2   552 , the switch signals SW 1  and SW 2   538 , and shutter signal  540  are all pulsed high, while the strobe signal  544 , row select signals RS 1   546 A and RS 2   546 B, and common mode reset signal COM  548  remain low. As shown in the example, the charge collection gate bias voltage  562  remains regulated at the constant voltage during the pre-charge reset period, the integration period, the readout period, and the idle period. 
     During the integration period, image charge carriers are photo-generated in the photodiode in response to incident light. The regulated charge collection gate bias voltage  562  applied to the charge collection gate generates an inversion layer with the photo-generated image charge carriers that are collected from the photodiode. The transfer signal TX 1   536 A is enabled while the transfer signal TX 2   536 B is disabled. Thus, it is appreciated that in the depicted example, first transfer transistor, and first floating diffusion are utilized to generate the first output pixel value PIXOUT 1 . With the transfer signal TX 1   536 A enabled, the photo-generated image charge collected in the inversion layer is transferred to the first single shared channel region during the integration period of the pixel. In addition, the switch signals SW 1  and SW 2   538  as well as shutter signal  540  remain disabled during the integration period. As such, the charge transferred from the inversion layer is stored in the transfer gate capacitance, but not in the charge storage structures or in the floating diffusions during the integration period. As such, the pixel is set for low FWC and high conversion gain in the depicted example in accordance with the teachings of the present invention. 
     During the readout period, the overflow signal OFG  542  is enabled, which enables the overflow transistor to drain excess image charge from the photodiode. As such, performance of the pixel can be improved in bright sunny outdoor conditions so that image charge generated by background ambient light can be drained through the overflow transistor during the readout period. In the example, the transfer gate signal  536 A remains high during the readout period so that the charge transferred from the inversion layer during the integration period remains stored in the transfer gate capacitance. The switch signals SW 1  and SW 2   538  are also disabled during the readout period, which turns off the switch gates to isolate the charged stored in the transfer gate capacitance from the charge storage structures. The shutter signal  540  and the row select signals RS 1   546 A and RS 2   546 B are enabled, which enables the pixel output signals PIXOUT 1  to be read out from the pixel. The floating diffusions are then reset, as indicated with the pulse of the reset signals RST 1  and RST 2   552 . In the example, the pixel output signals are then sampled and held to sample the reset output values of the pixel, as indicated with the SHR  566  pulse. After the reset output value of the pixel has been sampled, the shutter signal  540  is pulsed as shown so that the charges stored in the first transfer gate capacitance are transferred to the first floating diffusion. The pixel output signals are then sampled and held again to sample the signal output values of the pixel, as indicated with the SHS  568  pulse. As such, it is appreciated that the difference between the sampled reset signal values and the sampled signal output values can be determined by a correlated double sampling operation to determine the CDS pixel output values in accordance with the teachings of the present invention. 
     It is appreciated by those skilled in the art that the operation illustrated by  FIGS. 5A-5F  may be implemented by a control circuitry (e.g., the control circuitry  124  of  FIG. 1 ) of a time of flight light sensing system. The control circuitry (may include logics for controlling the operations of a light source (e.g., the light source  102  of  FIG. 1 ) and an image sensor having a plurality of pixels (e.g., the image sensor  120  of  FIG. 1 ) of the time of flight light sensing system. The control circuitry may further include a build-in memory (e.g., random access memory, erasable read only memory, or the like), and the memory may be programmed in such way that it causes the control circuitry to control the light source to emit light and the image sensor to detect the reflective light from an object (e.g., the object  130  of  FIG. 1 ) and selectively perform the operations described in  FIGS. 5A-5F . As stated above, the control circuitry may be an application specific integrated circuit (ASIC—custom designed for the time of flight light sensing system), a general purpose processor that can be programed in many different ways, or a combination of the two. 
     The above description of illustrated examples of the invention, including what is described in the Abstract, is not intended to be exhaustive or to limit the invention to the precise forms disclosed. While specific examples of the invention are described herein for illustrative purposes, various modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize. 
     These modifications can be made to the invention in light of the above detailed description. The terms used in the following claims should not be construed to limit the invention to the specific examples disclosed in the specification. Rather, the scope of the invention is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.