Patent Publication Number: US-11385831-B2

Title: Memory controller and storage device including the same

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application claims the benefit under 35 USC § 119 of U.S. Provisional Application No. 62/913,951 filed on Oct. 11, 2019, in the US Patent Office the entire disclosure of which are incorporated herein by reference for all purposes. 
    
    
     BACKGROUND 
     1. Field 
     The disclosure relates to a memory controller and a storage device including the same, and more particularly, to a memory control technique for dynamically changing and controlling an allowed number of erase/program suspend operations. 
     2. Description of Related Art 
     Semiconductor memories are categorized into volatile memory and non-volatile memory according to the storage mechanisms of information. Volatile memories include dynamic random access memory (DRAM) and static random access memory (SRAM). Although the volatile memory provides fast read and write speeds, the volatile memory loses stored information when it is powered off. In contrast, the non-volatile memory maintains its stored information even after it is powered off and thus is used as a storage medium for persistent storage devices such as solid-state drives (SSDs). Non-volatile memories include erasable programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM), ferroelectric RAM (FRAM), phase change RAM (PRAM), magnetoresistive RAM (MRAM), and flash memory. Particularly, the flash memory is widely used as an audio and video data storage medium for information devices such as a computer, a smartphone, a digital camera, a voice recorder, and a camcorder. 
     There are multiple outstanding host read/write commands in a flash memory based storage device due to multiple concurrent tasks inside the storage device such as host command processing, buffer flush, garbage collection (GC), etc. Due to the queuing effect caused by multiple commands, the host command processing latencies are not constant and have a specific distribution. It is preferable that the width of the latency distribution is narrow because latencies are easily predictable on the part of a host. That is, as latencies are more consistent (i.e., the distribution width is narrower), quality of service (QoS) of the storage device is more excellent. Conventionally, write buffering is used to improve write QoS, and erase/program suspend is used to improve read QoS. However, when an allowed number of erase/program suspend operations is set to be too small, read QoS is decreased, whereas when the allowed number of erase/program suspend operations is set to be too large, write QoS is decreased. Particularly, when too many suspend operations are allowed, erase or program throughput is lowered, thereby degrading buffer flush or GC performance. In this case, the resulting late buffer flush causes a full buffer, or the resulting late GC leads to exhaustion of free blocks and hence delayed write command processing. 
     There is thus a pressing need for a method of improving the QoS of a flash storage device to overcome the conventional problem. 
     SUMMARY 
     The present disclosure has been made in an effort to solve the above-mentioned problems of the prior art and an aspect of the present disclosure is to provide a memory controller for dynamically changing an allowed number of erase/program suspend operations. 
     According to an embodiment of the disclosure, a memory controller includes memory channel controllers configured to perform erase, program, read, and erase suspend and program suspend operations for flash memories, a flash translation layer configured to control the memory channel controllers to process write/read commands, allocate a buffer space in a buffer memory in response to a write command in the write/read commands, temporarily store data in the allocated buffer space, and deallocate the buffer space after the data is programmed to the flash memory, a host interface configured to receive the write/read commands from a host and transmit the received write/read commands to the flash translation layer, and a suspend-limit changer configured to dynamically change an erase/program suspend-limit based on the size of the allocable buffer space, the erase/program suspend-limit being a maximum allowed number of erase/program suspend operations. 
     In the memory controller according to an embodiment of the disclosure, the suspend-limit changer may be configured to change the erase/program suspend-limit by referring to a reference table in which erase/program suspend-limits are recorded for preset sizes of buffer spaces. 
     The memory controller according to an embodiment of the disclosure may further include a memory configured to store the reference table. 
     In the memory controller according to an embodiment of the disclosure, the flash translation layer may be configured to calculate the size of the allocable buffer space and the suspend-limit changer may be configured to change the erase/program suspend-limit so as to correspond to the calculated size of the buffer space by referring to the reference table. 
     In the memory controller according to an embodiment of the disclosure, the suspend-limit changer may be configured to calculate the size of the allocable buffer space and change the erase/program suspend-limit so as to correspond to the calculated size of the buffer space by referring to the reference table. 
     In the memory controller according to an embodiment of the disclosure, the memory channel controllers may be configured to count the number of erase/program suspend operations, and upon input of a read command during the erase/program operation to process a write command in the read/write commands from the host, suspend the erase/program operation and perform the read operation, when the number of erase/program suspend operations is less than the erase/program suspend-limit. The memory channel controllers may resume the suspended erase/program operation after the read operation completes. 
     According to an embodiment of the disclosure, a storage device includes a flash memory, and a memory controller controlling the flash memory. 
     The features and advantages of the disclosure will become more apparent from the following description based on the attached drawings. 
     The terms or words used in the specification and claims should not be interpreted in a conventional and lexical sense. Rather, they should be interpreted as meanings and concepts consistent with the technical idea of the disclosure based on the principle that the inventor can appropriately define the concept of terms in order to explain his or her invention in the best way. 
     According to the present disclosure, write QoS and read QoS can be maintained consistent despite a change in host workload characteristics, by dynamically changing allowed numbers of erase suspend and program suspend operations. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The above and other aspects, features, and advantages of certain embodiments of the disclosure will be more apparent from the following description taken in conjunction with the accompanying drawings, in which: 
         FIG. 1  is a block diagram illustrating a memory controller according to an embodiment of the disclosure; 
         FIG. 2  is a block diagram illustrating an operation of the memory controller illustrated in  FIG. 1 ; 
         FIG. 3  is a flowchart illustrating a method of operating the memory controller according to the disclosure; 
         FIG. 4  is a block diagram illustrating a storage device according to an embodiment of the disclosure; and 
         FIG. 5  is a block diagram illustrating a solid-state drive (SSD) to which the storage device according to the embodiment of the disclosure is applied. 
     
    
    
     DETAILED DESCRIPTION 
     The objects, specific advantages, and novel features of the disclosure will become more apparent from the following detailed description and preferred embodiments, examples of which are illustrated in the accompanying drawings. The same reference numerals and signs denote the same or like components even when they are shown in different accompanying drawings from one another. The term as used in the disclosure, “1 st ”, “2 nd ”, “first” or “second’ may be used for the names of various components, not limiting the components. These expressions are used only to distinguish one component from another component. Lest it should obscure the subject matter of the disclosure, a detailed description of well-known technologies is avoided. 
     Preferred embodiments of the disclosure will be described below in detail with reference to the attached drawings. 
       FIG. 1  is a block diagram illustrating a memory controller according to an embodiment of the disclosure. 
     Referring to  FIG. 1 , a memory controller  100  according to an embodiment of the disclosure includes memory channel controllers  10  that perform erase, program, read, erase suspend and program suspend operations for flash memories  200 , a flash translation layer (FTL)  20  that controls an operation of a memory channel controller  10  to process a write/read commands, allocates a buffer space in a buffer memory in response to a write command in the write/read commands, temporarily stores data in the allocated buffer space, and deallocates the buffer space after the data is programmed to the flash memory, a host interface (I/F)  30  that receives the write/read commands from a host  300  and transmits the received write/read commands to the flash translation layer  20 , and a suspend-limit changer  40  that dynamically changes an erase/program suspend-limit based on the size of the allocable buffer space, the erase/program suspend-limit being a maximum allowed number of erase/program suspend operations. 
     The disclosure relates to a memory controller that controls a flash memory in a storage device. Although erase/program suspend is used to improve quality of service (QoS) of the storage device, when an allowed number of erase/program suspend operations is set to be too small, read QoS is decreased, whereas when the allowed number of erase/program suspend operations is set to be too large, write QoS is decreased. The disclosure is devised to overcome this problem. 
     Specifically, the memory controller  100  according to the disclosure includes the memory channel controllers  10 , the FTL  20 , the host I/F  30 , and the suspend-limit changer  40 . 
     Each of the memory channel controllers  10  performs erase, program, read, erase suspend, and program suspend operations for a flash memory  200  connected to the memory channel controller  10  via a channel. These operations are performed in response to a flash erase command, a flash program command, and a flash read command from the FTL  20 . 
     The memory channel controller  10  fetches a command from a queue into which flash commands are placed by the FTL  20 . When a target flash memory  200  to which the command has been issued is idle, the memory channel controller  10  executes the command and transmits completion information attached with an execution result to the FTL  20 . On the contrary, when the target flash memory  200  is busy, that is, when the target flash memory  200  is executing a previous command, the memory channel controller  10  waits until the flash memory  200  is idle and then executes the new command, or suspends the ongoing command which is being executed, preferentially executes the new command, and then resumes the execution of the suspended command. It is determined whether to suspend the ongoing command according to the priority of the command. A higher priority may be assigned to the flash read command than the flash erase or program command. A suspended and then resumed flash erase or program operation may be suspended again. However, a maximum allowed number of erase/program suspend operations may be limited. When the maximum allowed number of erase/program suspend operations is exceeded, a corresponding erase or program operation is executed without being suspended, even though a higher-priority command is input. Hereinafter, the maximum allowed number of erase/program suspend operations is defined as an erase/program suspend-limit. The erase/program suspend-limit may be divided into an erase suspend-limit and a program suspend-limit. 
     The FTL  20  receives a write/read command and controls an operation of the memory channel controller  10 . The write/read command, which is received from the host  300  through the host I/F  30 , may be divided into a host write command and a host read command. 
     The FTL  20  may perform write buffering and buffer flush in response to the host write command. Upon receipt of the host write command, the FTL  20  allocates a buffer space in a buffer memory, temporarily stores host data in the allocated buffer space, and then transmits a write completion to the host  300  through the host I/F  30 . This process is referred to as write buffering. Subsequently, to store the buffered data to the flash memory  200 , the FTL  20  transmits a flash program command to the memory channel controller  10 . Upon receipt of a flash program completion, the FTL  20  records the physical address of the flash memory  200  at which the data has been stored in a mapping table and deallocates the buffer space. This process is referred to as buffer flush. Because fast transmission of a completion to the host is possible by the write buffering, a write latency is improved. The buffer flush is performed in the background. Therefore, although the buffer flush does not affect performance that the host  300  experiences, too late buffer flush results in exhaustion of an available buffer space that may be allocated to the buffer memory, thereby lengthening the latency of a subsequent host write command. 
     Upon receipt of the host read command, the FTL  20  first determines whether requested data exists in a buffer space. In the presence of the data in the buffer, the FTL  20  transmits the data and then a completion to the host  300 . On the contrary, in the absence of the buffered data, the FTL  20  obtains a physical address of the flash memory  200 , at which the data is located, referring to the mapping table, transmits a flash read command to the memory channel controller  10 , and thus transmits the data of the flash memory  200  and a completion to the host  300 . 
     In addition, the FTL  20  performs garbage collection (GC). Only when a page of the flash memory  200  is free, writing on the page is possible, with no overwrite allowed. Accordingly, to program new data, a block of the flash memory  200  composed of multiple pages should first be erased. A block which has been erased and thus is programmable is called a free block. To program write-buffered data to the flash memory  200 , a free block should exist. An operation of generating free blocks is called GC. 
     The host I/F  30  interfaces with the host  300 . The host I/F  30  may be connected to the host  300  via at least one channel or port. For example, the host I/F  30  may be connected to the host  300  via one or all of a parallel AT attachment (PATA) bus, a serial AT attachment (SATA) bus, and a peripheral component interconnect express (PCIe) bus. Alternatively, the host I/F  30  may be connected to the outside via a small computer system interface (SCSI), a universal serial bus (USB), or the like. 
     The host I/F  30  receives a write/read command from the host  300 , transmits the write/read command to the FTL  20 , receives a completion corresponding to the transmitted write/read command from the FTL  20 , and transmits the completion to the host  300 . 
     The suspend-limit changer  40  dynamically changes the erase/program suspend-limit based on the size of the allocable buffer space. The size of the allocable buffer space is defined as a free write buffer size and is initially set to a maximum value of the available buffer memory. The size of the allocable buffer space decreases upon write buffering and again increases upon completion of buffer flush. 
     The suspend-limit changer  40  may be implemented in hardware or software. That is, the suspend-limit changer  40  may be implemented in the form of a digital or analog circuit inside the memory controller  100 , or may be implemented as a separate chip or module and connected to the memory controller  100 . Further, the suspend-limit changer  40  may be implemented by storing and executing software in an internal memory such as an SRM or an external memory such as a floppy disk, a compact disk, or a USB flash drive. Further, the suspend-limit changer  40  may be implemented in a form programmable by a user. Further, the suspend-limit changer  40  may be incorporated with the FTL  20  or the host I/F  30 . That is, in addition to the afore-described original functions of the FTL  20  or the host I/F  30 , the FTL  20  or the host I/F  30  may execute all or some of the functions of the suspend-limit changer  40 . 
     The suspend-limit changer sends the erase/program suspend-limit to the memory channel controller  10  after changing the erase suspend-limit and/or the program suspend-limit. Upon input of a command with a higher priority than an ongoing command, the memory channel controller  10  performs a suspend operation only when the number of suspend operations performed so far is less than the suspend-limit, without unconditionally suspending an erase or program operation. Because the suspend-limit is changed based on the size of the allocable buffer space which directly affects write QoS and thus indirectly affects read QoS, the write QoS and the read QoS may be maintained consistent even though host workload characteristics are changed. 
     An embodiment of determining an erase/program suspend-limit will be described below. 
       FIG. 2  is a block diagram illustrating an operation of the memory controller illustrated in  FIG. 1 , and  FIG. 3  is a flowchart illustrating a method of operating the memory controller according to the disclosure. 
     Referring to  FIGS. 2 and 3 , the suspend-limit changer  40  can determine an erase/program suspend-limit by referring to a reference table. The reference table is a table in which erase/program suspend-limits are recorded for sizes of allocable buffer spaces and provides preset erase suspend-limits and program suspend-limits optimized for sizes of allocable buffer spaces. Table  1  is an example of the reference table. 
     
       
         
           
               
               
               
             
               
                   
                 TABLE 1 
               
             
            
               
                   
                   
               
               
                   
                 Suspend-limit 
                   
               
            
           
           
               
               
               
            
               
                 Free write buffer size (MB) 
                 p-limit 
                 e-limit 
               
               
                   
               
            
           
           
               
               
               
            
               
                 Less than 10 
                 0 
                 0 
               
               
                 10~20 
                 4 
                 10 
               
               
                 20~30 
                 8 
                 20 
               
               
                   
                 . . . 
               
               
                 180~190 
                 72 
                 110 
               
               
                 190~200 
                 ∞ 
                 ∞ 
               
               
                   
               
            
           
         
       
     
     In Table 1, p-limit and e-limit represent the program suspend-limit and the erase suspend-limit, respectively. 
     The reference table is merely illustrative and the specific sizes of buffer spaces and the corresponding suspend-limits can be determined, for example, empirically through experimentation. This reference table may be stored in a memory  50 . The memory  50  may be provided as a separate memory such as an SRAM or an existing buffer memory may be used as the memory  50 . When the size of the allocable buffer space is calculated during execution of the write/read command, the suspend-limit changer  40  can change the erase/program suspend-limit so as to correspond to the calculated size of the buffer space by referring to the reference table. Here, the size of the allocable buffer space can be calculated in the FTL  20  or the suspend-limit changer  40 . 
     The erase/program suspend-limit determined by the suspend-limit changer  40  in this manner may be stored separately, for example, in the memory channel controller  10 . 
     The memory channel controller  10  performs an operation for the flash memory  200 , using the erase/program suspend-limit. The memory channel controller  10  counts the number of times a specific erase or program command has been suspended, that is, the number of erase suspend operations and the number of program suspend operations. Upon receipt of a read command with a higher priority during an erase or program operation corresponding to a write command, the memory channel controller  10  compares the count of suspend operations with the suspend-limit. Then, only when the count is less than the suspend-limit, the memory channel controller  10  performs a suspend operation and then a read operation. 
     The memory controller according to the disclosure is applicable to a storage device, which will be described below. 
       FIG. 4  is a block diagram illustrating a storage device according to an embodiment of the disclosure, and  FIG. 5  is a block diagram illustrating a solid-state drive (SSD) to which the storage device according to the embodiment of the disclosure is applied. 
     Referring to  FIG. 4 , a storage device  1000  according to an embodiment of the disclosure may include a flash memory  1100  and a memory controller  1200  controlling the flash memory  1100 . 
     The storage device  1000  may include a memory card or a detachable mobile storage device. The storage device  1000  is used in connection to a host  2000  and exchanges data with the host  200  via an interface (I/F) of the host  2000 . The storage device  1000  may perform an internal operation by receiving power from the host  2000 . 
     As described before, read and erase/program suspend operations of the flash memory  1100  are controlled based on an erase/program suspend-limit changed dynamically by the memory controller  1200 . A related operation control has been described before and thus its detailed description is avoided herein. 
     Referring to  FIG. 5 , the storage device  1000  according to the disclosure may be an SSD. 
     Because the SSD is connected to the host  2000 , the host  2000  may write data to or read stored data from the SSD. The SSD may exchange signals with the host  2000  via the host I/F and receive power from the host  2000  via a power connector. The SSD may include a plurality of flash memories  1100  and an SSD controller. The plurality of flash memories  1100  may be connected to the SSD controller via a plurality of channels. One channel may be connected to one or more flash memories  1100  and the flash memories  1100  connected to one channel may be connected to the same data bus. 
     The memory controller  1200  according to the disclosure is provided as the SSD controller and exchanges signals with the host  2000  via the host I/F. The signals may carry commands, addresses, and data, and data is written to or read from a corresponding flash memory  1100  according to a command from the host  2000 . 
     While the disclosure has been described in detail with reference to specific embodiments, the embodiments are intended only for describing the disclosure, not limiting the disclosure. It is apparent to those skilled in the art that many variations or modifications can be made without departing the scope and spirit of the disclosure. 
     Simple modifications and changes of the disclosure fall within the scope of the disclosure and the specific protection scope of the disclosure will become apparent from the appended claims.