Patent Publication Number: US-11024396-B2

Title: Reduction or elimination of a latency penalty associated with adjusting read thresholds for non-volatile memory

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This non-provisional utility patent application is a continuation and claims the benefit of the filing date of U.S. patent application Ser. No. 15/440,225, filed Feb. 23, 2017 which application claimed the benefit of the filing date of U.S. patent application Ser. No. 14/087,520, filed Nov. 22, 2014, and of U.S. Provisional Application Ser. No. 61/898,947, filed on Nov. 1, 2013, with this same title, which applications are incorporated by reference herein in their entirety. 
    
    
     TECHNICAL FIELD 
     The invention relates generally to flash memory, and more particularly, to adapting a read reference voltage to be used in reading flash memory based on one or more channel conditions. 
     BACKGROUND 
     Related Art: Unless expressly identified as being publicly or well known, mention herein of techniques and concepts, including for context, definitions, or comparison purposes, should not be construed as an admission that such techniques and concepts are previously publicly known or otherwise part of the prior art. All references cited herein (if any), including patents, patent applications, and publications, are hereby incorporated by reference in their entireties, whether specifically incorporated or not, for all purposes. 
     Various aspects of flash memory as used by Solid State Disk (SSD) controllers will now be described in part to establish a technology background and in part to establish antecedents for nomenclature used in the balance of the specification. The minimal size of data readable by the SSD controller from Non-Volatile Memory (NVM) is a “read unit” that is protected by included error correction, such as a Low-Density Parity-Check (LDPC) code. In some contexts, a read unit is referred to as a “codeword”. In some embodiments, each read unit contains approximately 4K to approximately 32K bits of user data, plus error correction overhead. Under command of the SSD controller, those bits are read from NVM memory cells (e.g., via an array access of one or more portions of the NVM memory cells), which depending on the technology as discussed below, may hold one or more bits per cell. In some embodiments, for security reasons an SSD controller encrypts the data prior to writing the data to NVM. In some embodiments, in view of circuit design limitations with respect to long strings of identically programmed cells, an SSD controller scrambles the data prior to writing the data to NVM. 
     Considered individually, each cell has a particular stored (programmed) charge that corresponds to a device threshold voltage for that cell, and further corresponds to the logical bit values being stored in the cell. While ideally all of the cells in the NVM would have identical device threshold voltages for the logical bit values stored, in practice for a variety of reasons the device threshold voltages differ across the cells in probability distributions along the device threshold voltage axis (e.g., “device threshold voltage distributions”) that are similar to a Gaussian in shape. 
     Thus, considered in aggregate across a large number of cells, such as of a read unit, there are as many device threshold voltage distributions (e.g., Gaussian probability curves) as there are states per cell (two states per bit of storage per cell). That is, for N-bits per cell of storage, there are 2 N  states and the same number of device threshold voltage distributions. Generally, (2 N )−1 different read thresholds (read reference voltages V READ1  through V READN-1 ) are required by read circuits in the NVM to distinguish between the 2 N  states. 
     Continuing from above, for Single-Level Cell (SLC) flash memories, N=1. SLC memories thus store one-bit per cell of storage, have two device threshold voltage distributions (one for zeroes and another for ones), and require a single read threshold, read reference voltage V READ1 . From lower to higher device threshold voltages, the two device threshold voltage distributions are known as the E (Erased) state and D1 (first Data) state. While arbitrary, a common mapping (coding) is to assign logical one to the E state and logical zero to the D1 state. Thus, references to zeroes and ones are proxy references for respective decodings of the D1 state and the E state. 
     Continuing further from above, for Multi-Level Cell (MLC) flash memories, N&gt;1. MLC memories thus store more than one bit per cell, have more than two device threshold voltage distributions, and require multiple different read thresholds to distinguish the distributions. For example, a 4LC memory (e.g., flash memory) stores two bits per cell, has four device threshold voltage distributions, and generally requires three read thresholds (read reference voltages V READ1 , V READ2 , and V READ3 ). From lower to higher device threshold voltages, the four device threshold voltage distributions are known as the E (Erased), D1 (Data1), D2 (Data2), and D3 (Data3) states. While arbitrary, each of the four device threshold voltage distributions is also mapped (addressed) in accordance with a particular binary sequence, such as a Gray code sequence. Thus, references to one or more of the 11, 10, 00, and 01 states, are proxy references for respective decodings of the E, D1, D2, and D3 states. 
     With respect to address mapping used for the states of an MLC, each can be said to have a Most Significant Bit (MSB) and a Least Significant Bit (LSB) (and for more than two bits per cell, bits of significance in between). While there are various ways that MLC NVMs program their cells, the following approach is common. An initial programming round (a manipulation of the charge distributions) establishes the LSB, e.g., writes the “lower pages”. This is done loosely in the same manner as for writing an SLC, e.g., a charge manipulation that establishes the E state device threshold voltage distribution and a second state device threshold voltage distribution. Depending on the binary sequence used, the second state device threshold voltage distribution is similar to the D1 state device threshold voltage distribution, similar to the D2 state device threshold voltage distribution, or between the D1 and D2 state device threshold voltage distributions. For MLC, one or more additional programming rounds further manipulate the device threshold voltage distributions (in number, location along the device threshold voltage axis, and in shape), as required per the number of levels of the MLC. More particularly, one or more subsequent programming operations write the “middle pages” (if any, for more than two bits per cell), and a last programming operation establishes the MSB, e.g., writes the “upper pages”. For example in a 4LC (2-bit per cell MLC), the E distribution and the second distribution of the first program round are respectively bifurcated by a second program round into E and D1 distributions and D2 and D3 distributions. 
     The device threshold voltage distributions are modified away from their initial/nominal distributions by one or more factors, such as read disturb, write disturb, and retention loss. More particularly, over time, temperature, and other factors related to use, the location of each of the device threshold voltage distribution can move around with respect to the device threshold voltage axis. Such changes increase the likelihood of read errors that are performed using a read reference voltage value for the read threshold that was previously established based on the nominal device threshold voltage distribution. In some SLC embodiments, when a hard-decision uncorrectable error is encountered in a read unit read from NVM, a series of retry operations is performed to recover the read unit. The retry operations include the controller re-reading the read unit at different read reference voltage values for V READ1 , such as determined by a register setting written via an I/O command from the SSD controller. By reading at different settings of the read reference voltage values, the read unit is sampled at different points on the device threshold voltage axis in an attempt to locate a sample of the read unit that is (hard-decision) correctable. 
     One algorithm suggested by NVM vendors involves sweeping the SLC read threshold slowly upwards (increasing the read reference voltage V READ1  from its nominal value) in an attempt to find a sample of the read unit that is correctable. If this procedure fails, then the read threshold is swept in another direction (decreasing the read reference voltage V READ1  from its nominal value). If both sweeps fail, then the read unit is uncorrectable (by hard-decision decoding). Linearly sweeping the read threshold, which might have 16 to 64 steps at different respective read reference voltage settings, requires many time-consuming samples of the read unit (each with an attendant recovery time latency). Even when such a search is infrequently required, and thus not a major impact on average latencies, for applications with strict maximum latency requirements, including some database applications, such a time-consuming search is unacceptable. 
     Also, the adjustments that are made to the read reference voltage during the retry operations cannot be made on the fly at read time due to the latency that is involved with the process of sweeping the read reference voltage values. The sweeping process can only be performed when the extra time needed to perform it is not a major concern. Furthermore, while flash memory vendors provide the capability of adjusting the read reference voltages on a die level or chip enable (CE) level, there is no provision for separately setting the read reference voltages of different blocks within the same die. Often times it is necessary or desirable to be able to set the read reference voltages to different values for different blocks within the same die. 
       FIG. 1  is a block diagram of a portion of a flash memory configured as a Redundant Array of Independent Silicon Elements (RAISE™). In RAISE™ technology, data is duplicated across blocks of multiple dies, commonly referred to as R-blocks, to provide data redundancy that enables data to be recovered in the event of a die failure similar to the way in which Redundant Arrays of Independent Disks (RAID) technology duplicates data over multiple disks of a disk drive array to allow data to be recovered in the event of a disk failure. For example, as shown in  FIG. 1 , R-block  0  of R-blocks  0 -M−1 includes blocks in Dies  0 -N−1, wherein M and N are integers that are equal to or greater than one. In such a configuration, if a read in a block belonging to one R-block of one of the dies is being followed by a read in a block of a different R-block of the same die, the read that occurred earlier in time can necessitate an adjustment to the read reference voltages of the R-block that will be read later in time. For example, if a read in Block  0  of R-block  0  of Die  0  is followed by a read of Block  0  of R-block  2  of Die  0 , the read of Block  0  of R-block  0  can affect the device threshold voltage distributions of cells of Block  0  of R-block  2  in a way that necessitates an adjustment to the read reference voltages of R-block  2  before the subsequent read of R-block  2  occurs. 
     However, adjusting the read reference voltage values this frequently may result in a significant read performance penalty due to the latency associated with making these adjustments. For example, for an upper page read in MLC flash, up to two reference voltage values may need to be adjusted. For an upper page read in TLC flash, the read performance penalty may be even worse because up to four read reference voltage values may need to be adjusted. Accordingly, a need exists for a way to reduce or eliminate the read performance penalty associated with adjusting the read reference voltages. 
     SUMMARY 
     The invention is directed to systems and methods for reducing or eliminating a read performance penalty associated with updating read reference voltages used for reading flash memory. The storage system comprises an NVM comprising at least a first flash memory die having a plurality of memory cells, and a SSD controller in communication with the NVM via a first interface (I/F) that interfaces the NVM with the SSD controller. The SSD controller being configured to execute read commands in order to read the memory cells and uses a read reference voltage, V READ , to read the memory cells. 
     In accordance with one embodiment, the SSD controller is configured to determine a difference between a value of a current read reference voltage, V READ_CURRENT , to be used during a current read operation for reading a group of memory cells, V READ_LAST , that was used during a previous read operation to read a group of memory cells. The SSD controller is configured to determine whether or not the difference value indicates that an adjustment of the read reference voltage value from the V READ_LAST  to the V READ_CURRENT  value should be made before performing the current read operation. 
     In accordance with another embodiment, the SSD controller is configured to determine whether or not the V READ_CURRENT  value are equal. If the SSD controller determines that the V READ_CURRENT  value and the V READ_LAST  value are equal, the SSD controller performs the current read operation using the V READ_LAST  value. 
     In accordance with one embodiment, the method performed by the SSD controller comprises: determining a difference between a value of a current read reference voltage, V READ_CURRENT , to be used during a current read operation for reading a group of memory cells of at least a first flash memory die and a value of a last read reference voltage, V READ_LAST , that was used during a previous read operation to read a group of memory cells of the first flash memory die; and determining whether or not the difference value indicates that an adjustment of the read reference voltage value from the V READ_LAST  value to the V READ_CURRENT  value should be made before performing the current read operation. 
     In accordance with another embodiment, the method performed by the SSD controller comprises: determining in the SSD controller whether or not a value of a current read reference voltage, V READ_CURRENT , to be used during a current read operation for reading a group of memory cells of at least a first flash memory die is equal to a value of a last read reference voltage, V READ_LAST , that was used during a previous read operation to read a group of memory cells of said at least a first flash memory die; and, if a determination is made that the V READ_CURRENT  value and the V READ_LAST  value are equal, performing the current read operation in the SSD controller using the V READ_LAST  value. 
     Embodiments of the invention also include non-transitory computer-readable mediums (CRMs) for storing computer code that is used by the SSD controller to perform the methods. 
     These and other features and advantages of the invention will become apparent from the following description, drawings and claims. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a block diagram of a portion of a flash memory configured as a Redundant Array of Independent Silicon Elements (RAISE™). 
         FIG. 2A  illustrates selected details of an embodiment of a Solid-State Disk (SSD) including an SSD controller that implements optimization of read thresholds for managing Non-Volatile Memory (NVM) elements (e.g., flash memories). 
         FIG. 2B  illustrates selected details of various embodiments of systems including one or more instances of the SSD of  FIG. 2A . 
         FIGS. 3A through 3D  illustrate example device threshold voltage distributions relevant to zero/one balance restoration.  FIGS. 3A and 3B  are SLC specific, respectively illustrating device threshold voltage distributions at a first and a later second time.  FIGS. 3C and 3D  are MLC specific, respectively illustrating device threshold voltage distributions at a first and a later second time. 
         FIG. 4  illustrates selected details of a system embodiment of an instance of the SSD of  FIG. 2A , providing particular details regarding zero/one balance management and offline tracking. 
         FIG. 5  illustrates selected control flow details for an embodiment of the SSD of  FIGS. 2A, 2B, and 4 , providing particular details regarding write related operations (actions  410  through  430 ) and read related operations (actions  440  through  480 ). 
         FIG. 6A  illustrates a flow diagram of selected details of an embodiment of optimizing of read thresholds for an NVM (e.g. of an SSD). 
         FIG. 6B  illustrates a flow diagram of selected details of an embodiment of Offline Tracking of device threshold voltages in a managed group of blocks of an NVM. 
         FIGS. 7A, 7B, 7C and 7D  conceptually illustrate device threshold voltage distributions in a 4LC memory. 
         FIG. 8  illustrates a flow diagram that represents a method for determining whether or not an adjustment to the read reference voltage can be avoided altogether. 
         FIG. 9  illustrates a flow diagram that represents a method for adaptively varying the D value used in the method represented by the flow diagram of  FIG. 8 . 
         FIG. 10  illustrates four device threshold voltage distributions for four states of a MLC and distances between the means of adjacent distributions. 
         FIG. 11  illustrates a flow diagram that represents an embodiment of a method performed by the SSD controller shown in  FIGS. 2A, 2B and 4  for choosing a rounding precision to be used for rounding off the read threshold voltage values. 
         FIG. 12  illustrates a lookup table (LUT) that may be used to select the rounding precision value to be used in adjusting the read reference voltages. 
         FIG. 13  illustrates a flow diagram that represents the method performed by the SSD controller shown in  FIG. 2A  in accordance with another illustrative embodiment for determining whether or not an adjustment to the read reference voltage can be avoided altogether. 
     
    
    
     LIST OF REFERENCE SYMBOLS IN DRAWINGS 
     At least some of the various shorthand abbreviations (e.g. acronyms) defined here refer to certain elements used herein. 
     
       
         
           
               
               
             
               
                   
               
               
                 Acronym 
                 Description 
               
               
                   
               
             
            
               
                 AES 
                 Advanced Encryption Standard 
               
               
                 AHCI 
                 Advanced Host Controller Interface 
               
               
                 API 
                 Application Program Interface 
               
               
                 ASCII 
                 American Standard Code for Information Interchange 
               
               
                 ATA 
                 Advanced Technology Attachment (AT Attachment) 
               
               
                 BCH 
                 Bose Chaudhuri Hocquenghem 
               
               
                 BER 
                 Bit Error Rate 
               
               
                 CD 
                 Compact Disk 
               
               
                 CF 
                 Compact Flash 
               
               
                 CMOS 
                 Complementary Metal Oxide Semiconductor 
               
               
                 CPU 
                 Central Processing Unit 
               
               
                 CRC 
                 Cyclic Redundancy Check 
               
               
                 DAS 
                 Direct Attached Storage 
               
               
                 DDR 
                 Double-Data-Rate 
               
               
                 DES 
                 Data Encryption Standard 
               
               
                 DMA 
                 Direct Memory Access 
               
               
                 DNA 
                 Direct NAND Access 
               
               
                 DRAM 
                 Dynamic Random Access Memory 
               
               
                 DVD 
                 Digital Versatile/Video Disk 
               
               
                 DVR 
                 Digital Video Recorder 
               
               
                 ECC 
                 Error-Correcting Code 
               
               
                 eMMC 
                 Embedded MultiMediaCard 
               
               
                 eSATA 
                 external Serial Advanced Technology Attachment 
               
               
                 GPS 
                 Global Positioning System 
               
               
                 HDD 
                 Hard Disk Drive 
               
               
                 I/O 
                 Input/Output 
               
               
                 IC 
                 Integrated Circuit 
               
               
                 IDE 
                 Integrated Drive Electronics 
               
               
                 JPEG 
                 Joint Photographic Experts Group 
               
               
                 LAN 
                 Local Area Network 
               
               
                 LB 
                 Logical Block 
               
               
                 LBA 
                 Logical Block Address 
               
               
                 LDPC 
                 Low-Density Parity-Check 
               
               
                 LFSR 
                 Linear Feedback Shift Register 
               
               
                 LPN 
                 Logical Page Number 
               
               
                 LSB 
                 Least Significant Bit 
               
               
                 LZ 
                 Lempel-Ziv 
               
               
                 MLC 
                 Multi-Level Cell 
               
               
                 MMC 
                 MultiMediaCard 
               
               
                 MPEG 
                 Moving Picture Experts Group 
               
               
                 MSB 
                 Most Significant Bit 
               
               
                 NAS 
                 Network Attached Storage 
               
               
                 NCQ 
                 Native Command Queuing 
               
               
                 NVM 
                 Non-Volatile Memory 
               
               
                 ONA 
                 Optimized NAND Access 
               
               
                 ONFI 
                 Open NAND Flash Interface 
               
               
                 OS 
                 Operating System 
               
               
                 PC 
                 Personal Computer 
               
               
                 PCIe 
                 Peripheral Component Interconnect express (PCI express) 
               
               
                 PDA 
                 Personal Digital Assistant 
               
               
                 PHY 
                 PHYsical interface 
               
               
                 POS 
                 Point Of Sale 
               
               
                 RAID 
                 Redundant Array of Inexpensive/Independent Disks 
               
               
                 RASIE 
                 Redundant Array of Silicon Independent Elements 
               
               
                 ReRAM 
                 Resistive Random Access Memory 
               
               
                 RS 
                 Reed-Solomon 
               
               
                 RSA 
                 Rivest, Shamir &amp; Adleman 
               
               
                 SAN 
                 Storage Attached Network 
               
               
                 SAS 
                 Serial Attached Small Computer System Interface (Serial 
               
               
                   
                 SCSI) 
               
               
                 SATA 
                 Serial Advanced Technology Attachment (Serial ATA) 
               
               
                 SCSI 
                 Small Computer System Interface 
               
               
                 SD 
                 Secure Digital 
               
               
                 SDR 
                 Single-Data-Rate 
               
               
                 SLC 
                 Single-Level Cell 
               
               
                 SMART 
                 Self-Monitoring Analysis and Reporting Technology 
               
               
                 SSD 
                 Solid-State Disk/Drive 
               
               
                 TCG 
                 Trusted Computing Group 
               
               
                 UFS 
                 Unified Flash Storage 
               
               
                 USB 
                 Universal Serial Bus 
               
               
                 VF 
                 Virtual Function 
               
               
                 WAN 
                 Wide Area Network 
               
               
                   
               
            
           
         
       
     
     DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS 
     In a related application having Ser. No. 13/533,130, which is assigned to the assignee of the present application, devices and methods are disclosed for performing an Offline Tracking process that monitors/tracks the read channel offline, or in the background, while other algorithms or processes are being performed by the SSD controller. The Offline Tracking process gathers various types of channel information and determines various types of channel conditions, which are then used to make adjustments to the read reference voltages, also referred to herein as read thresholds. 
     In accordance with illustrative embodiments disclosed in the present application, channel information and channel conditions that are determined by the Offline Tracking process are used to determine whether or not an adjustment to the read reference voltage can be avoided altogether without detrimentally affecting performance (due to a higher bit error rate caused by non-optimal read reference voltages), or, alternatively, to determine a precision with which a read reference voltage adjustment should be made. If it is determined based on the channel conditions that a read reference voltage adjustment can be avoided altogether, read performance is actually improved by avoiding the read reference voltage adjustment altogether. If it is determined based on the channel conditions that a read reference voltage adjustment needs to be made with a particular precision, the read reference voltage is adjusted with that precision. This latter approach is advantageous in that a determination that the precision with which the adjustments can be made is relatively low leads to fewer adjustments having to be made overall, which reduces processing overhead and frees up processing resource to perform other tasks. These new approaches, which may be used separately or in combination, further reduce latency and the performance penalty associated with making adjustments to the read reference voltages. 
     Prior to discussing these new approaches, a storage system, devices and methods for performing the aforementioned Offline Tracking algorithm and for adjusting the read reference voltages will be described with reference to  FIGS. 2A-7D , which subject matter is also disclosed in the parent application. The methods in accordance with illustrative embodiments of the present invention will then be described with reference to  FIGS. 8-13 . 
     Tracking and Restoring Zero/One Balances 
     The initial discussion that follows, of tracking and managing counts for zeroes and ones and the shifting of the read threshold, referred to interchangeably herein as the read reference voltage, used to distinguish the zero and one states, is directly applicable to SLC memories and (with minor variation, as noted) to the lower pages of MLC memories. More generally with respect to MLC memories, extension to tracking and managing counts for upper pages and the shifting of multiple read thresholds (e.g., read reference voltages V READ1 , V READ2 , and V READ3 ) is detailed in separate paragraphs below. 
     In accordance with some illustrative embodiments, a zero count and a one count are obtained for each read unit (or each group of read units transferred at one time from one NVM die) read from an SLC NVM. In an event that the read unit is uncorrectable (e.g. in a context of hard-decision decoding) in part due to the shift in the device threshold voltage distributions away from their (initial) nominal distributions, the zero count and/or the one count enable a determination of a direction and/or a magnitude to move (set) a read threshold to track the shift in the device threshold voltage distributions and restore the zero/one balance. The read threshold being adjusted is read voltage reference V READ1  for SLC memories and read voltage reference V READ2  for the lower pages of MLC memories. For example, in an SLC having a logical one assigned to the erase state, and written with a known statistically equal (50-50 percent, a.k.a. 50/50 percent, or simply 50/50) distribution of zeroes and ones, if a current zero/one counts indicates a predominance of ones, V READ1  is shifted lower; and if the current zero/one counts indicates a predominance of zeroes, V READ1  is shifted higher. (Substitute V READ2  for V READ1  in the foregoing example, for the lower pages of MLC memories.) A magnitude of how much to change (shift) the read threshold is optionally determined by a percentage of a number of zeroes (or ones). The magnitude is based on one or more of: the number of zeroes and/or ones observed in one or more samples; a read threshold increment of the one or more samples; a knowledge of predicted device threshold voltage distributions corresponding to a midpoint between the peaks of the two distributions; program/erase count (wear); read disturb counts; retention time; and other similar factors. 
     Finding the Read-Equilibrium Point 
     In further embodiments, a binary-search-like operation (iteratively sampling the same read unit at respective values of the appropriate read voltage reference) is used to find a read threshold “read-equilibrium point”. This is a point on the device threshold voltage axis between adjacent device threshold voltage distributions resulting in raw data (pre error correction) statistical state distributions that upon reading, match within a statistical margin of error to the statistical state distributions written, or idealized models of same. 
     For SLC memory and random scrambling, such as resulting from encryption, the read-equilibrium point is the read threshold (read voltage reference V READ1 ) where a zero/one balance (of the raw data read from the NVM) is most even (near identical). Under such conditions, the two state distributions have a 50-50 balance. I.e., 50% of the states read are zeroes and 50% of the states read are ones. (Substitute V READ2  for V READ1  in the foregoing for the lower pages of MLC memories.) 
     In some embodiments, the read-equilibrium point corresponds to one or more of: a center point between two voltage distributions, a minima between two voltage distributions, a point at which the zero/one balance in read data is closest to 50-50, and a point determined according to interpolation of the zero/one balance found at two other points. The read equilibrium point corresponds to a center-point between the adjacent device threshold voltage distributions in embodiments having symmetric adjacent device threshold voltage distributions. 
     Finding and setting the read threshold to the desired read-equilibrium point reduces the number of reads required to find an optimal point at which to attempt hard-decision decoding. In still further embodiments, hard-decision decoding is attempted at each read threshold sampling point (each value of V READ1  for SLC memories, or each value of V READ2  for the lower pages of MLC memories) in the binary search in the event a “good enough” read threshold is found before the read threshold read-equilibrium point is found. The search is generally truncated upon finding the good enough read threshold, except as discussed below regarding possibly taking additional sampling around the determined read-equilibrium point for soft-decision decoding purposes. In various embodiments, the “good enough” read threshold results in successful hard decision decoding of the raw read data. In some embodiments, a magnitude of the search steps (the read threshold increment) in the binary search is determined (based), at least in part, on various factors as detailed above regarding the magnitude of the read threshold change. 
     MLC Considerations 
     In MLC memories, multiple read thresholds are managed. In some embodiments, this is performed by assuming uniform displacements of the multiple device-threshold-voltage distributions and changing all other read thresholds based on decisions made for the first read threshold (V READ1 ) based on a read data zero/one balance of the lower pages. 
     For a 4LC NVM, theoretically there is an 11/10/00/01 balance of 25-25-25-25 (in contrast to a zero/one balance of 50-50). However, there is no single operation that directly provides this balance, given that 4LCs are generally read via separate array accesses using the three read voltage references: V READ2  for lower pages and V READ1  and V READ3  for upper pages. One could thus evaluate two respective zero/one balances: between the D1 and D2 states for lower pages, and between the E and D1 states combined with between the D2 and D3 states for upper pages. Alternatively, one could carry out three separate lower-page-like array accesses setting the single lower-page read threshold to values near each of V READ1 , V READ2 , and V READ3 . 
     By way of example, in some 4LC NVM embodiments, read reference voltages V READ1 , V READ2 , V READ3  may need shifting, at least for one of the two bits stored in the cell. Working similarly to the SLC case, one of the two bits stored in the cell requires a single array access at a first read threshold (V READ2 , in this MLC case). Ascertaining the other bit requires two additional read thresholds (V READ1 , and V READ3 , and effectively two associated respective additional array accesses that are performed internally by the NVM). 
     According to various embodiments, either: the two read thresholds (V READ1  and V READ3 ) for the other bit are moved in unison by a same and/or a differing amount (under a presumption that drift is similar for both states); or the two read thresholds for the other bit are moved independently (at a cost in additional read operations). The latter option requires knowing the state of the SLC-like bit in the cell (the LSB), as the state of the SLC-like bit determines which of the two read thresholds (V READ1  and V READ3 ) are used for ascertaining the corresponding other bit (the MSB). 
     In some 4LC embodiments, a combined “upper page” read data zero/one balance is evaluated for a simultaneous blend of the E and D1 distributions and the D2 and D3 distributions. Based on disparities in the combined zero/one balance read vs. that written, and in view of the bit sense reversal (1 to 0 for moving from E to D1, and 0 to 1 for moving from D2 to D3), the corresponding two read thresholds (V READ1  and V READ3 ) are moved in unison in opposite directions. This is done such that the zero/one balance of each component of the blend moves “in the same direction” (e.g., the movements do not conflict). 
     In some 4LC embodiments, the movement of the two upper page read thresholds (V READ1  and V READ3 ) are separately determined by respective evaluations of zero/one balance for the upper page while using a respective LSB for each bit of the read unit. When the LSB=1, the direction of movement is the opposite of that of the LSB=0 case. For example, instead of computing a disparity between a zero count and a one count in upper page read data, an upper page disparity is computed by selectively modifying each bit of upper page read data based on a corresponding bit of lower page read data, converting a sense of the bits of the upper page read data from a numeric value to a directional value where, for example, 0 represents a higher device threshold voltage and 1 represents a lower device threshold voltage. In some embodiments, an XNOR of the bits of the upper page read data and the corresponding bits of the lower page read data performs the converting. 
     Removing Bias from Soft-Decision Samples 
     In some embodiments, soft decision information is obtained from NVM to perform soft-decision based decoding. The soft decision information is obtained by reading a read unit (or each group of read units transferred at one time from one NVM die) at a variety of read threshold sampling points (for an SLC, values of V READ1 ) about the nominal (unadjusted) read threshold to obtain multiple samples of data of the read unit, thus building up a soft-decision likelihood of a value of each bit of the read unit. A spacing of the samples depends, at least in part, on particular properties of the NVM used, such as its nominal separation of charge states. 
     The soft-decision information is biased, however, unless the nominal read threshold about which the samples are taken is a read threshold read-equilibrium point (as described above). If the current read threshold is not the threshold read-equilibrium point, then all the soft-decision information is biased in one direction or the other. Following are two example techniques to adjust for this and obtain unbiased (or at least less-biased) soft-decision information:
         1. Since a zero/one balance of the read unit as sampled at each of the read threshold sampling points is readily identified, the read threshold read-equilibrium point is readily determined (according to embodiment, such as by using linear interpolation). An offset is calculated corresponding to the difference between the determined read threshold read-equilibrium point and the (old, unadjusted) nominal read threshold. Previously determined soft-decision information is enabled to be properly “re-centered” and still used by applying the offset with respect to the voltages at which the soft-decision information was previously sampled (with values larger than 1.0 or less than 0.0 being truncated). This approach requires no additional reads, but produces a differing amount of precision/accuracy for some of the data.   2. Since a zero/one balance of the read unit as sampled at each of the read threshold sampling points is readily identified, after collecting all required samples, the read threshold sampling point closest to the read threshold read-equilibrium point is readily determined. The closest is the read threshold sampling point with the zero/one balance most proximate to the zero/one balance written. For the SLC encryption (or scrambling) case, it is the read threshold sampling point closest to having a 50-50 balance. As all of the samples nominally have equivalent spacing from each other, the closest sample is chosen as a new nominal read threshold, and additional soft-decision information samples are optionally gathered (assuming the new nominal read threshold differs from the old). Alternatively, a binary search to find the threshold read-equilibrium point is done first, with precision of the binary search limited to a finest granularity of sampling required for the desired precision of the soft-decision information. The desired precision of the soft-decision information has an associated sample window around the new nominal read threshold. Doing a binary search as a part of multiple reads needed to obtain soft-decision information requires no additional reads, unless the old nominal read threshold falls outside the desired precision sample window.       

     In the SLC encryption embodiments described so far, the above techniques have focused on finding a preferred read threshold that yields a read data zero/one balance that is closest to 50-50. For cases where the device threshold voltage distributions are of generally the same symmetric shape and do not substantively overlap, this preferred read threshold would also correspond to the minima of the combined device threshold voltage distributions. 
     READ THRESHOLD INTERPOLATED FROM KNOWN POINTS ON THE DEVICE THRESHOLD VOLTAGE DISTRIBUTIONS 
     In some embodiments, another approach to finding the preferred read threshold is to instead find two points, one on each adjacent device threshold voltage distribution, and determine the midpoint between these two points by interpolation. For example, sampling at the peak of each device threshold voltage distribution should yield a 75/25 balance of read data zeroes/ones (or ones/zeroes, depending on which peak). Once the two peaks are identified, the calculated midpoint between the two on the device threshold voltage axis is used to set a new read threshold. 
     If it is known a priori that the device threshold voltage distributions are not uniform (e.g., asymmetrically biased on one side or the other, such as by having a long tail), then in some embodiments that information is used to interpret the position of the peak and to locate the center by a slightly more complex interpolation (e.g., not just the midpoint). Factors such as retention time and/or wear may influence the symmetry of the device threshold voltage distributions and are accounted for in some embodiments. Multiple sampling points are also used in some embodiments to reveal the shape of the device threshold voltage distributions. 
     In some embodiments where the range of device threshold voltage adjustment is limited, it may not be possible to find the true peak. In particular, the device threshold voltage cannot be moved less than 0V with some flash devices even though the voltage distribution of the E state extends into negative device threshold voltages. Knowledge of the device threshold voltage distribution still permits the midpoint to be determined via interpolation. For example, if at 0V the read data zero/one balance is 60/40, then approximately 10% excess zeroes are being observed and an area of the E distribution to the right of 0V is approximately 10%. In a first approach of some embodiments, the peak of the D1 distribution is found, and the midpoint is interpolated based on knowledge of the approximate shape of the E distribution. In a second approach of some embodiments, the point of the D1 distribution at which the read data zero/one balance is 40/60 (the opposite point from the 0V measurement) is found. The calculated midpoint between the 60/40 and the 40/60 observations is then used to set the new preferred read threshold. The calculated midpoint could be determined with greater precision with additional knowledge and/or measurement of the two device threshold voltage distributions. 
     In some embodiments, the points being interpolated are both on a same side as the read equilibrium point. For example, knowing that a first read threshold sampling point X yields 75/25 read data zero/one balance and a second read threshold sampling point Y yields 62.5/37.5, the read equilibrium point would be close to Y+/− (Y) where ‘+’ vs. ‘−’ depends on whether Y is less than X. The direction of the read equilibrium point is the direction corresponding to moving the read data zero/one balance closer to 50/50. In the example given, that is in the direction from X and toward Y. Knowledge of the device threshold voltage distributions would yield a more accurate interpolation rather than the simple linear interpolation indicated. 
     Offline Tracking 
     In various embodiments and/or usage scenarios, the device threshold voltage distributions in an NVM shift over time and cause a read error (e.g. when hard-decision decoding). As the device threshold voltage distributions shift, values that were previously below (or above) a certain read threshold, fall above (or below) the certain read threshold and cause a bit error. For example, a value previously stored as (and considered to be in) the D1 distribution, is determined to be in the D2 distribution, thus resulting in a bit error. A small number of bit errors are correctable; however a sufficient number of bit errors causes an uncorrectable (e.g. hard-decision decode) error. In some embodiments and/or usage scenarios, an uncorrectable (e.g. hard-decision decode) error that would otherwise occur is avoidable via proactive adjustment of read thresholds, such as via offline tracking that adjusts the read thresholds independently of uncorrectable error detection. 
     In some embodiments, an I/O device, such as an SSD, includes an SSD controller. The SSD controller acts as a bridge between the host interface and NVM of the SSD, and executes commands of a host protocol sent from a computing host via a host interface of the SSD. At least some of the commands direct the SSD to write and read the NVM with data sent from and to the computing host, respectively. In further embodiments, the SSD controller is enabled to use a map to translate between LBAs of the host protocol and physical storage addresses in the NVM. In further embodiments, at least a portion of the map is used for private storage (not visible to the computing host) of the I/O device. For example, a portion of the LBAs not accessible by the computing host is used by the I/O device to manage access to logs, statistics, or other private data. 
     In some embodiments, accessing compressed data of varying-sized quanta in NVM provides improved storage efficiency in some usage scenarios. For example, an SSD controller receives (uncompressed) data from a computing host (e.g., relating to a disk write command), compresses the data, and stores the compressed data into flash memory. In response to a subsequent request from the computing host (e.g., relating to a disk read command), the SSD controller reads the compressed data from the flash memory, uncompresses the compressed data, and provides the uncompressed data to the computing host. The compressed data is stored in the flash memory according to varying-sized quanta, the quanta size varying due to, e.g., compression algorithm, operating mode, and compression effectiveness on various data. The SSD controller uncompresses the data in part by consulting an included map table to determine where header(s) are stored in the flash memory. The SSD controller parses the header(s) obtained from the flash memory to determine where appropriate (compressed) data is stored in the flash memory. The SSD controller uncompresses the appropriate data from the flash memory to produce the uncompressed data to provide to the computing host. In the instant application, uncompress (and variants thereof) is synonymous with decompress (and variants thereof). 
     In various embodiments, an SSD controller includes a host interface for interfacing with a computing host, an interface for interfacing with NVM such as flash memory, and circuitry for controlling the interfaces and performing (and/or controlling various aspects of the performing) compressing and uncompressing, as well as lower-level error correction, higher-level error correction, and dynamic higher-level redundancy mode management with independent silicon elements. 
     According to various embodiments, some host interfaces are compatible with one or more of a USB interface standard, a CF interface standard, an MMC interface standard, an eMMC interface standard, a Thunderbolt interface standard, a UFS interface standard, an SD interface standard, a Memory Stick interface standard, an xD-picture card interface standard, an IDE interface standard, a SATA interface standard, a SCSI interface standard, a SAS interface standard, and a PCIe interface standard. According to various embodiments, the computing host is all or any portions of a computer, a workstation computer, a server computer, a storage server, a SAN, a NAS device, a DAS device, a storage appliance, a PC, a laptop computer, a notebook computer, a netbook computer, a tablet device or computer, an ultrabook computer, an electronic reading device (such as an e-reader), a PDA, a navigation system, a (handheld) GPS device, an automotive control system, an automotive media control system or computer, a printer, copier or fax machine or all-in-one device, a POS device, a cash-register, a media player, a television, a media recorder, a DVR, a digital camera, a cellular handset, a cordless telephone handset, and an electronic game. In some embodiments, an interfacing host (such as an SAS/SATA bridge) operates as a computing host and/or as a bridge to a computing host. 
     In various embodiments, the SSD controller includes one or more processors. The processors execute firmware to control and/or perform operation of the SSD controller. The SSD controller communicates with the computing host to send and receive commands and/or status as well as data. The computing host executes one or more of an operating system, a driver, and an application. Communication by the computing host with the SSD controller is optionally and/or selectively via the driver and/or via the application. In a first example, all communication to the SSD controller is via the driver, and the application provides higher-level commands to the driver that the driver translates into specific commands for the SSD controller. In a second example, the driver implements a bypass mode and the application is enabled to send specific commands to the SSD controller via the driver. In a third example, a PCIe SSD controller supports one or more Virtual Functions (VFs), enabling an application, once configured, to communicate directly with the SSD controller, bypassing the driver. 
     According to various embodiments, some SSDs are compatible with form-factors, electrical interfaces, and/or protocols used by magnetic and/or optical non-volatile storage, such as HDDs, CD drives, and DVD drives. In various embodiments, SSDs use various combinations of zero or more parity codes, zero or more RS codes, zero or more BCH codes, zero or more Viterbi or other trellis codes, and zero or more LDPC codes. 
       FIG. 2A  illustrates selected details of SSD  101  including SSD Controller  100  that implements optimization of read reference voltages (e.g., via zero/one balance management and/or offline tracking techniques) for managing Non-Volatile Memory (NVM) elements (e.g., flash memories). SSD Controller  100  is communicatively coupled via one or more External Interfaces  110  to a host (such as host  102  of  FIG. 1B ). According to various embodiments, External Interfaces  110  are one or more of: a SATA interface; a SAS interface; a PCIe interface; a Fibre Channel interface; an Ethernet Interface (such as 10 Gigabit Ethernet); a non-standard version of any of the preceding interfaces; a custom interface; or any other type of interface used to interconnect storage and/or communications and/or computing devices. For example, in some embodiments, SSD Controller  100  includes a SATA interface and a PCIe interface. 
     SSD Controller  100  is further communicatively coupled via one or more Device Interfaces  190  to NVM  199  including one or more storage devices, such as one or more of Flash Device  192 . According to various embodiments, Device Interfaces  190  are one or more of: an asynchronous interface; a synchronous interface; a single-data-rate (SDR) interface; a double-data-rate (DDR) interface; a DRAM-compatible DDR or DDR2 synchronous interface; an ONFI compatible interface, such as an ONFI 2.2 or ONFI 3.0 compatible interface; a Toggle-mode compatible flash interface; a non-standard version of any of the preceding interfaces; a custom interface; or any other type of interface used to connect to storage devices. 
     Each Flash Device  192  has, in some embodiments, one or more individual Flash Die  194 . According to type of a particular one of Flash Device  192 , a plurality of Flash Die  194  in the particular Flash Device  192  is optionally and/or selectively accessible in parallel. Flash Device  192  is merely representative of one type of storage device enabled to communicatively couple to SSD Controller  100 . In various embodiments, any type of storage device is usable, such as an SLC NAND flash memory, MLC NAND flash memory, NOR flash memory, flash memory using polysilicon or silicon nitride technology-based charge storage cells, two- or three-dimensional technology-based flash memory, read-only memory, static random access memory, dynamic random access memory, ferromagnetic memory, phase-change memory, racetrack memory, ReRAM, or any other type of memory device or storage medium. 
     According to various embodiments, Device Interfaces  190  are organized as: one or more busses with one or more of Flash Device  192  per bus; one or more groups of busses with one or more of Flash Device  192  per bus, where busses in a group are generally accessed in parallel; or any other organization of one or more of Flash Device  192  onto Device Interfaces  190 . 
     Continuing with reference to  FIG. 2A , SSD Controller  100  has one or more modules, such as Host Interfaces  111 , Data Processing  121 , Buffer  131 , Map  141 , Recycler  151 , ECC  161 , Device Interface Logic  191 , and CPU  171 . The specific modules and interconnections illustrated in  FIG. 1A  are merely representative of one embodiment, and many arrangements and interconnections of some or all of the modules, as well as additional modules not illustrated, are conceived. In a first example, in some embodiments, there are two or more Host Interfaces  111  to provide dual-porting. In a second example, in some embodiments, Data Processing  121  and/or ECC  161  are combined with Buffer  131 . In a third example, in some embodiments, Host Interfaces  111  is directly coupled to Buffer  131 , and Data Processing  121  optionally and/or selectively operates on data stored in Buffer  131 . In a fourth example, in some embodiments, Device Interface Logic  191  is directly coupled to Buffer  131 , and ECC  161  optionally and/or selectively operates on data stored in Buffer  131 . 
     Host Interfaces  111  sends and receives commands and/or data via External Interfaces  110 , and, in some embodiments, tracks progress of individual commands via Tag Tracking  113 . For example, the commands include a read command specifying an address (such as an LBA) and an amount of data (such as a number of LBA quanta, e.g., sectors) to read; in response the SSD provides read status and/or read data. For another example, the commands include a write command specifying an address (such as an LBA) and an amount of data (such as a number of LBA quanta, e.g., sectors) to write; in response the SSD provides write status and/or requests write data and optionally subsequently provides write status. For yet another example, the commands include a de-allocation command (e.g., a trim command) specifying one or more addresses (such as one or more LBAs) that no longer need be allocated; in response the SSD modifies the Map accordingly and optionally provides de-allocation status. In some contexts an ATA compatible TRIM command is an exemplary de-allocation command. For yet another example, the commands include a super capacitor test command or a data hardening success query; in response, the SSD provides appropriate status. In some embodiments, Host Interfaces  111  is compatible with a SATA protocol and, using NCQ commands, is enabled to have up to 32 pending commands, each with a unique tag represented as a number from 0 to 31. In some embodiments, Tag Tracking  113  is enabled to associate an external tag for a command received via External Interfaces  110  with an internal tag used to track the command during processing by SSD Controller  100 . 
     According to various embodiments, one or more of: Data Processing  121  optionally and/or selectively processes some or all data sent between Buffer  131  and External Interfaces  110 ; and Data Processing  121  optionally and/or selectively processes data stored in Buffer  131 . In some embodiments, Data Processing  121  uses one or more Engines  123  to perform one or more of: formatting; reformatting; transcoding; and any other data processing and/or manipulation task. 
     Buffer  131  stores data sent to/from External Interfaces  110  from/to Device Interfaces  190 . In some embodiments, Buffer  131  additionally stores system data, such as some or all map tables, used by SSD Controller  100  to manage one or more of Flash Device  192 . In various embodiments, Buffer  131  has one or more of: Memory  137  used for temporary storage of data; DMA  133  used to control movement of data to and/or from Buffer  131 ; and ECC-X  135  used to provide higher-level error correction and/or redundancy functions; and other data movement and/or manipulation functions. An example of a higher-level redundancy function is a RAISE capability, where redundancy is at a flash device (e.g., multiple ones of Flash Device  192 ) level and/or a flash die (e.g., Flash Die  194 ) level instead of at a disk level. 
     According to various embodiments, one or more of: ECC  161  optionally and/or selectively processes some or all data sent between Buffer  131  and Device Interfaces  190 ; and ECC  161  optionally and/or selectively processes data stored in Buffer  131 . In some embodiments, ECC  161  is used to provide lower-level error correction and/or redundancy functions, such as in accordance with one or more ECC techniques. In some embodiments, ECC  161  implements one or more of: a CRC code; a Hamming code; an RS code; a BCH code; an LDPC code; a Viterbi code; a trellis code; a hard-decision code; a soft-decision code; an erasure-based code; any error detecting and/or correcting code; and any combination of the preceding. In some embodiments, ECC  161  includes one or more decoders (such as LDPC decoders). 
     Device Interface Logic  191  controls instances of Flash Device  192  via Device Interfaces  190 . Device Interface Logic  191  is enabled to send data to/from the instances of Flash Device  192  according to a protocol of Flash Device  192 . Device Interface Logic  191  includes Scheduling logic  193  to selectively sequence control of the instances of Flash Device  192  via Device Interfaces  190 . For example, in some embodiments, Scheduling logic  193  is enabled to queue operations to the instances of Flash Device  192 , and to selectively send the operations to individual ones of the instances of Flash Device  192  (or Flash Die  194 ) as individual ones of the instances of Flash Device  192  (or Flash Die  194 ) are available. 
     Map  141  converts between data addressing used on External Interfaces  110  and data addressing used on Device Interfaces  190 , using Table  143  to map external data addresses to locations in NVM  199 . For example, in some embodiments, Map  141  converts LBAs used on External Interfaces  110  to block and/or page addresses targeting one or more Flash Die  194 , via mapping provided by Table  143 . For LBAs that have never been written since drive manufacture or de-allocation, the Map points to a default value to return if the LBAs are read. For example, when processing a de-allocation command, the Map is modified so that entries corresponding to the de-allocated LBAs point to one of the default values. In various embodiments, there are various default values, each having a corresponding pointer. The plurality of default values enables reading some de-allocated LBAs (such as in a first range) as one default value, while reading other de-allocated LBAs (such as in a second range) as another default value. The default values, in various embodiments, are defined by flash memory, hardware, firmware, command and/or primitive arguments and/or parameters, programmable registers, or various combinations thereof. 
     In some embodiments, Map  141  uses Table  143  to perform and/or to look up translations between addresses used on External Interfaces  110  and data addressing used on Device Interfaces  190 . According to various embodiments, Table  143  is one or more of: a one-level map; a two-level map; a multi-level map; a map cache; a compressed map; any type of mapping from one address space to another; and any combination of the foregoing. According to various embodiments, Table  143  includes one or more of: static random access memory; dynamic random access memory; NVM (such as flash memory); cache memory; on-chip memory; off-chip memory; and any combination of the foregoing. 
     In some embodiments, Recycler  151  performs garbage collection. For example, in some embodiments, instances of Flash Device  192  contain blocks that must be erased before the blocks are re-writeable. Recycler  151  is enabled to determine which portions of the instances of Flash Device  192  are actively in use (e.g., allocated instead of de-allocated), such as by scanning a map maintained by Map  141 , and to make unused (e.g., de-allocated) portions of the instances of Flash Device  192  available for writing by erasing them. In further embodiments, Recycler  151  is enabled to move data stored within instances of Flash Device  192  to make larger contiguous portions of the instances of Flash Device  192  available for writing. 
     In some embodiments, instances of Flash Device  192  are selectively and/or dynamically configured, managed, and/or used to have one or more bands for storing data of different types and/or properties. A number, arrangement, size, and type of the bands are dynamically changeable. For example, data from a computing host is written into a hot (active) band, while data from Recycler  151  is written into a cold (less active) band. In some usage scenarios, if the computing host writes a long, sequential stream, then a size of the hot band grows, whereas if the computing host does random writes or few writes, then a size of the cold band grows. 
     CPU  171  controls various portions of SSD Controller  100 . CPU  171  includes CPU Core  172 . CPU Core  172  is, according to various embodiments, one or more single-core or multi-core processors. The individual processors cores in CPU Core  172  are, in some embodiments, multi-threaded. CPU Core  172  includes instruction and/or data caches and/or memories. For example, the instruction memory contains instructions to enable CPU Core  172  to execute programs (e.g. software sometimes called firmware) to control SSD Controller  100 . In some embodiments, some or all of the firmware executed by CPU Core  172  is stored on instances of Flash Device  192  (as illustrated, e.g., as Firmware  106  of NVM  199  in  FIG. 1B ). 
     In various embodiments, CPU  171  further includes: Command Management  173  to track and control commands received via External Interfaces  110  while the commands are in progress; Buffer Management  175  to control allocation and use of Buffer  131 ; Translation Management  177  to control Map  141 ; Coherency Management  179  to control consistency of data addressing and to avoid conflicts such as between external data accesses and recycle data accesses; Device Management  181  to control Device Interface Logic  191 ; Identity Management  182  to control modification and communication of identify information, and optionally other management units. None, any, or all of the management functions performed by CPU  171  are, according to various embodiments, controlled and/or managed by hardware, by software (such as firmware executing on CPU Core  172  or on a host connected via External Interfaces  110 ), or any combination thereof. 
     In some embodiments, CPU  171  is enabled to perform other management tasks, such as one or more of: gathering and/or reporting performance statistics; implementing SMART; controlling power sequencing, controlling and/or monitoring and/or adjusting power consumption; responding to power failures; controlling and/or monitoring and/or adjusting clock rates; and other management tasks. 
     Various embodiments include a computing-host flash memory controller that is similar to SSD Controller  100  and is compatible with operation with various computing hosts, such as via adaptation of Host Interfaces  111  and/or External Interfaces  110 . The various computing hosts include one or any combination of a computer, a workstation computer, a server computer, a storage server, a SAN, a NAS device, a DAS device, a storage appliance, a PC, a laptop computer, a notebook computer, a netbook computer, a tablet device or computer, an ultrabook computer, an electronic reading device (such as an e-reader), a PDA, a navigation system, a (handheld) GPS device, an automotive control system, an automotive media control system or computer, a printer, copier or fax machine or all-in-one device, a POS device, a cash-register, a media player, a television, a media recorder, a DVR, a digital camera, a cellular handset, a cordless telephone handset, and an electronic game. 
     In various embodiments, all or any portions of an SSD controller (or a computing-host flash memory controller) are implemented on a single IC, a single die of a multi-die IC, a plurality of dice of a multi-die IC, or a plurality of ICs. For example, Buffer  131  is implemented on a same die as other elements of SSD Controller  100 . For another example, Buffer  131  is implemented on a different die than other elements of SSD Controller  100 . 
       FIG. 2B  illustrates selected details of various embodiments of systems including one or more instances of the SSD  101  of  FIG. 2A . SSD  101  includes SSD Controller  100  coupled to NVM  199  via Device Interfaces  190 . This figure illustrates various classes of embodiments: a single SSD coupled directly to a host, a plurality of SSDs each respectively coupled directly to a host via respective external interfaces, and one or more SSDs coupled indirectly to a host via various interconnection elements. 
     As an example embodiment of a single SSD coupled directly to a host, one instance of SSD  101  is coupled directly to Host  102  via External Interfaces  110  (e.g. Switch/Fabric/Intermediate Controller  103  is omitted, bypassed, or passed-through). As an example embodiment of a plurality of SSDs each coupled directly to a host via respective external interfaces, each of a plurality of instances of SSD  101  is respectively coupled directly to Host  102  via a respective instance of External Interfaces  110  (e.g. Switch/Fabric/Intermediate Controller  103  is omitted, bypassed, or passed-through). As an example embodiment of one or more SSDs coupled indirectly to a host via various interconnection elements, each of one or more instances of SSD  101  is respectively coupled indirectly to Host  102 . Each indirect coupling is via a respective instance of External Interfaces  110  coupled to Switch/Fabric/Intermediate Controller  103 , and Intermediate Interfaces  104  coupling to Host  102 . 
     Some of the embodiments including Switch/Fabric/Intermediate Controller  103  also include Card Memory  112 C coupled via Memory Interface  180  and accessible by the SSDs. In various embodiments, one or more of the SSDs, the Switch/Fabric/Intermediate Controller, and/or the Card Memory are included on a physically identifiable module, card, or pluggable element (e.g. I/O Card  116 ). In some embodiments, SSD  101  (or variations thereof) corresponds to a SAS drive or a SATA drive that is coupled to an initiator operating as Host  102 . 
     Host  102  is enabled to execute various elements of Host Software  115 , such as various combinations of OS  105 , Driver  107 , Application  109 , and Multi-Device Management Software  114 . Dotted-arrow  107 D is representative of Host Software ↔ I/O Device Communication, e.g. data sent/received to/from one or more of the instances of SSD  101  and from/to any one or more of OS  105  via Driver  107 , Driver  107 , and Application  109 , either via Driver  107 , or directly as a VF. 
     OS  105  includes and/or is enabled to operate with drivers (illustrated conceptually by Driver  107 ) for interfacing with the SSD. Various versions of Windows (e.g. 95, 98, ME, NT, XP, 2000, Server, Vista, and 7), various versions of Linux (e.g. Red Hat, Debian, and Ubuntu), and various versions of MacOS (e.g. 8, 9 and X) are examples of OS  105 . In various embodiments, the drivers are standard and/or generic drivers (sometimes termed “shrink-wrapped” or “pre-installed”) operable with a standard interface and/or protocol such as SATA, AHCI, or NVM Express, or are optionally customized and/or vendor specific to enable use of commands specific to SSD  101 . Some drives and/or drivers have pass-through modes to enable application-level programs, such as Application  109  via Optimized NAND Access (sometimes termed ONA) or Direct NAND Access (sometimes termed DNA) techniques, to communicate commands directly to SSD  101 , enabling a customized application to use commands specific to SSD  101  even with a generic driver. ONA techniques include one or more of: use of non-standard modifiers (hints); use of vendor-specific commands; communication of non-standard statistics, such as actual NVM usage according to compressibility; and other techniques. DNA techniques include one or more of: use of non-standard commands or vendor-specific providing unmapped read, write, and/or erase access to the NVM; use of non-standard or vendor-specific commands providing more direct access to the NVM, such as by bypassing formatting of data that the I/O device would otherwise do; and other techniques. Examples of the driver are a driver without ONA or DNA support, an ONA-enabled driver, a DNA-enabled driver, and an ONA/DNA-enabled driver. Further examples of the driver are a vendor-provided, vendor-developed, and/or vendor-enhanced driver, and a client-provided, client-developed, and/or client-enhanced driver. 
     Examples of the application-level programs are an application without ONA or DNA support, an ONA-enabled application, a DNA-enabled application, and an ONA/DNA-enabled application. Dotted-arrow  109 D is representative of Application ↔ I/O Device Communication (e.g. bypass via a driver or bypass via a VF for an application), e.g. an ONA-enabled application and an ONA-enabled driver communicating with an SSD, such as without the application using the OS as an intermediary. Dotted-arrow  109 V is representative of Application ↔ Device Communication (e.g. bypass via a VF for an application), e.g. a DNA-enabled application and a DNA-enabled driver communicating with an SSD, such as without the application using the OS or the driver as intermediaries. 
     One or more portions of NVM  199  are used, in some embodiments, for firmware storage, e.g. Firmware  106 . The firmware storage includes one or more firmware images (or portions thereof). A firmware image has, for example, one or more images of firmware, executed, e.g., by CPU Core  172  of SSD Controller  100 . A firmware image has, for another example, one or more images of constants, parameter values, and NVM device information, referenced, e.g. by the CPU core during the firmware execution. The images of firmware correspond, e.g., to a current firmware image and zero or more previous (with respect to firmware updates) firmware images. In various embodiments, the firmware provides for generic, standard, ONA, and/or DNA operating modes. In some embodiments, one or more of the firmware operating modes are enabled (e.g. one or more APIs are “unlocked”) via keys or various software techniques, optionally communicated and/or provided by a driver. 
     In some embodiments lacking the Switch/Fabric/Intermediate Controller, the SSD is coupled to the Host directly via External Interfaces  110 . In various embodiments, SSD Controller  100  is coupled to the Host via one or more intermediate levels of other controllers, such as a RAID controller. In some embodiments, SSD  101  (or variations thereof) corresponds to a SAS drive or a SATA drive and Switch/Fabric/Intermediate Controller  103  corresponds to an expander that is in turn coupled to an initiator, or alternatively Switch/Fabric/Intermediate Controller  103  corresponds to a bridge that is indirectly coupled to an initiator via an expander. In some embodiments, Switch/Fabric/Intermediate Controller  103  includes one or more PCIe switches and/or fabrics. 
     In various embodiments, such as some of the embodiments where Host  102  is a computing host (e.g. a computer, a workstation computer, a server computer, a storage server, a SAN, a NAS device, a DAS device, a storage appliance, a PC, a laptop computer, a notebook computer, and/or a netbook computer), the computing host is optionally enabled to communicate (e.g. via optional I/O &amp; Storage Devices/Resources  117  and optional LAN/WAN  119 ) with one or more local and/or remote servers (e.g. optional Servers  118 ). The communication enables, for example, local and/or remote access, management, and/or usage of any one or more of SSD  101  elements. In some embodiments, the communication is wholly or partially via Ethernet. In some embodiments, the communication is wholly or partially via Fibre Channel. LAN/WAN  119  is representative, in various embodiments, of one or more Local and/or Wide Area Networks, such as any one or more of a network in a server farm, a network coupling server farms, a metro-area network, and the Internet. 
     In various embodiments, an SSD controller and/or a computing-host flash memory controller in combination with one or more NVMs are implemented as a non-volatile storage component, such as a USB storage component, a CF storage component, an MMC storage component, an eMMC storage component, a Thunderbolt storage component, a UFS storage component, an SD storage component, a Memory Stick storage component, and an xD-picture card storage component. 
     In various embodiments, all or any portions of an SSD controller (or a computing-host flash memory controller), or functions thereof, are implemented in a host that the controller is to be coupled with (e.g., Host  102  of  FIG. 1B ). In various embodiments, all or any portions of an SSD controller (or a computing-host flash memory controller), or functions thereof, are implemented via hardware (e.g., logic circuitry), software and/or firmware (e.g., driver software or SSD control firmware), or any combination thereof. For example, functionality of or associated with an ECC unit (such as similar to ECC  161  and/or ECC-X  135  of  FIG. 1A ) is implemented partially via software on a host and partially via a combination of firmware and hardware in an SSD controller. For another example, functionality of or associated with a recycler unit (such as similar to Recycler  151  of  FIG. 1A ) is implemented partially via software on a host and partially via hardware in a computing-host flash memory controller. 
     Zero/One Balance Restoration 
       FIGS. 3A through 3D  illustrate device threshold voltage distributions relevant to “zero/one” balance restoration. For the purposes of this discussion, each hill-like bump is an abstraction for an independent Gaussian-like curve representing a device threshold voltage probability distribution for a respective state of a read unit sized portion of an NVM. The device threshold voltage axis is drawn with increasing positive voltage to the right. An absolute scale is purposefully not provided, and no reference points are identified, such that the plots apply more generally to a larger population of NVMs.  FIGS. 3A and 3B  are SLC specific, while  FIGS. 3C and 3D  are MLC specific. 
     In  FIG. 3A , representing an initial time (e.g., when the corresponding data is written), leftmost distribution  220  represents a logical one and the rightmost distribution  230  represents a logical zero. Depending on the technology, the leftmost distribution may reside (at least predominantly) at negative voltages. Read reference voltage  210  is ideally situated between the two distributions. 
     Except as linked by the embodiments herein, independent of these device threshold voltage distributions, in some embodiments, the NVM is written with specific knowledge of the statistical distribution of zeroes and ones being stored. More particularly, in some embodiments various encryption and/or scrambling techniques are used such that the statistical distribution of zeroes and ones is 50-50 percent (50 percent zeroes and 50 percent ones). When the SLC is read using the nominal read threshold or read reference voltage, which is ideally situated for the case of  FIG. 3A , the observed read data statistical distribution of zeroes and ones is likewise 50-50 percent. The statistical distribution being 50-50 percent does not mean that any one sample of data would have an exactly even balance of zero bits and one bits, but rather that an average over many samples produces a ratio of zero bits and one bits that converges on 50-50 percent with an increasingly tight probabilistic bound as a number of the samples increases. An analogy is a distribution of heads and tails when a coin is flipped many times, generating a Gaussian distribution with a variance that is approximated by n/4 where n is a number of the coin flips. For example, if there are 18,432 bits in a read unit with a 50-50 percent statistical distribution of zero bits and one bits, the variance in the number of zero bits (or one bits) is approximately 4,608 and the standard deviation is approximately 68. With a standard deviation of 68, less than one in one million samples of read units would be expected to have a number of zero bits more than 340 (5 standard deviations) away from the average of 9,216. 
     In  FIG. 3B , representing a later time, nominal read reference voltage  210  is as in  FIG. 3A , and the two device threshold voltage distributions  225  and  235  are shifted with respect to their earlier respective distributions  220  and  230  in  FIG. 3A . For the purposes of example, the two distributions are shown as having both uniformly shifted to the left (toward more negative voltages). It should be understood that more generally the two distributions are enabled to move independently of each other and in either a positive or negative direction. 
     In view of  FIG. 3B , when the SLC is again read using the nominal read reference voltage  210 , it is predictable that the observed statistical distribution of zeroes and ones read directly from the NVM (e.g., prior to any error correction) will not be 50-50 percent. More particularly, for the conceptual example given, an erroneous excess of ones is to be expected, as the read threshold is such that some of the zeroes will be falsely read as ones. 
     In practice, the direction of inference is reversed. That is, in practice, generally such shifts in the device threshold voltage distributions are not known or directly knowable. In some embodiments, instead the observation of a disparity in the zeroes and ones read from the NVM (with respect to the known stored distribution of zeroes and ones) is used to infer the existence of shifts in the device threshold voltage distributions. Furthermore, in these embodiments, the read threshold is adjusted based at least in part on the disparity observed (as detailed elsewhere herein) to read threshold  215 , as required until the zero/one balance is restored. 
     Similarly,  FIG. 3C  represents an initial time (such as when the corresponding data is written) with initial device threshold voltage distributions, while  FIG. 3D  represents a later time with corresponding later device threshold voltage distributions. More specifically, for a selected Gray code mapping, respectively representing the 11, 10, 00, and 10 states, device threshold voltage distributions  251 ,  261 ,  271 , and  281  (of  FIG. 3D ) are shifted with respect to their earlier respective device threshold voltage distributions  250 ,  260 ,  270 , and  280  (of  FIG. 3C ). Three nominal (initial) read reference voltages are also shown: V READ1    240 , V READ2    242 , and V READ3    244 . Again for the purposes of example, in  FIG. 3D  the four distributions are shown as having all uniformly shifted to the left (toward more negative voltages). It should be understood that more generally the four distributions are enabled to move independently of each other and in either a positive or negative direction. 
     In some embodiments, various scrambling techniques are used such that the statistical distribution of the four states is 25-25-25-25 percent (25 percent in each state). When the MLC is read using the nominal read reference voltages that are ideally situated for the case of  FIG. 3C , in some embodiments the statistical distribution of the four states is configurable to likewise be 25-25-25-25 percent. (As discussed elsewhere, zeroes and ones are directly observable by the controller, but all four states are inferable as required.) In some embodiments, the observation of a disparity (a deviation from the expected 25-25-25-25 percent) read from the NVM (with respect to the known stored distribution of states) is used to infer the existence of shifts in the device threshold voltage distributions. The read reference voltages are then adjusted (as detailed elsewhere herein) as shown in FIG.  3 D to become V READ1    265 , V READ2    275 , and V READ3    285 . In some embodiments, the read threshold adjustments are performed separately for lower page reads (adjusting V READ2    275 ) and upper page reads (adjusting V READ1    265  and/or V READ3    285 ). 
     Functions for Zero/One Balance Restoration 
       FIG. 4  provides alternate views of SSD  101 , SSD Controller  100 , and NVM  199  of  FIGS. 2A and 2B , redrawing selected logic block boundaries to emphasize particular functions. SSD  101  at the top level features External Interface  110 , SSD Controller  100 , NVM  199 , and Device Interface  190 . 
     External Interface  110  is coupled to a host, such as Host  102  of  FIG. 2B , and supports a high-level storage protocol such as SATA, comprising host-sourced storage-related commands and write-data and controller-sourced read-data, and as detailed in the above discussion of  FIG. 2A . Device Interface  190  supports low-level NVM I/O transactions, as detailed in the discussion of  FIG. 2A . NVM  199  features NVM Array  332 , Programmable Read Voltage Circuitry  334 , Control/Status Registers  336 , and I/O  338 . SSD Controller  100  features Host Interfaces  111 , Scrambler  310 , ECC Encoder  320 , Device Interface Logic  191 , Imbalance Detector  340 , Buffer  131 , ECC Decoder  360 , Descrambler  370 , and Balance Restoration Logic  380 . Host Interfaces  111  couples with the Host via External Interface  110  as discussed previously, provides Write Data  306  to Scrambler  310 , and receives Read Data  351  from Buffer  131 . 
     The write path and functionality are as follows. Scrambler  310  operates on Write Data  306  to generate Scrambled Write Data  311  to ECC Encoder  320 . Scrambler  310  scrambles Write Data  306  in a reversible manner and such that the Scrambled Write Data  311  has a known statistical distribution of states stored. An example of a block comprising scrambled data is a block containing Scrambled Write Data  311 . For example, an SLC block comprising scrambled data contains an equal number of ‘0’ and ‘1’ values and a 4LC block comprising scrambled data contains an equal number of ‘00’, ‘01’, ‘10’, and ‘11’ states. In some embodiments, Scrambler  310  performs encryption, such as via an AES encoder that randomizes the data as a by-product of encryption. In some embodiments, Scrambler  310  uses a Linear Feedback Shift Register (LFSR) to randomize the data (but without any data security intent). ECC Encoder  320  processes the Scrambled Write Data  311  to add additional ECC bits, resulting in ECC Encoded Write Data  321  that is provided to Device Interface  191  for storing into NVM  199  via Device Interface  190 . 
     The basic read path and functionality are as follows. NVM pages, comprising Uncorrected and Scrambled (Raw) Read Data  359 , are received from NVM  199  via Device Interface  190 . Continuing with respect to  FIG. 4 , each read unit nominally comprises the data scrambled by Scrambler  301  as well as the additional ECC bits generated by ECC Encoder  320 , but as generally unintentionally altered as a result of NVM storage and retrieval operations. The read units are provided to ECC Decoder  360  via Buffer  131 . ECC Decoder  360  processes the read units, exploiting the included additional ECC bits to generally correct any errors that may have arisen at any point and time since the data was first ECC encoded, resulting in Corrected Read Data  361 , which is provided to Descrambler  370 . The Descrambler  370  operates on the Corrected Read Data  361 , reversing the scrambling performed by Scrambler  310 , resulting in Unscrambled Read Data  371  that is provided as Read Data  351  to Host Interfaces  111  via Buffer  131 . 
     The read path and functionality further includes Imbalance Detector  340  and Balance Restoration Logic  360 . Imbalance Detector  340  monitors Raw Read Data  359  received from the NVM, and at least temporarily maintains data on the statistical distributions of state. Balance Restoration Logic  380  interacts with NVM Control/Status Registers  336 , via Device Interface Logic  191  and NVM I/O  338 , to selectively adjust NVM read thresholds (used to read the NVM Array  332 ) via NVM Programmable Read Voltage Circuitry  334 . An example of NVM read thresholds are current read thresholds referred to in  FIGS. 6A and 6B . In some embodiments, NVM read thresholds are written to Control/Status Register  336  and configure Programmable Read Voltage Circuitry  334 . The read thresholds are adjusted based upon a) Uncorrectable Read  362  detected by ECC Decoder  360 , and b) Imbalance  341  (in the statistical of state) detected by Imbalance Detector  340 . The read unit is binary data in both SLC and MLC embodiments. Disparities in the zeroes and ones are directly measurable in the SLC case (or when an MLC is operated as though it were an SLC). In some embodiments, disparities in the more than two states of an MLC are inferred based on knowledge of how the data was stored in the NVM. 
       FIG. 4  illustrates functions for zero/one balance restoration in a context where a host operates as a source and a sink for data written to and read from NVM  199 . In various embodiments (such as illustrated by  FIG. 2A  and  FIG. 2B ), one or more other agents operate as sources and sinks for data written to and read from NVM  199 . An example of the other agents is Recycler  151  of  FIG. 2A , that moves data from one location to another in NVM  199 , as described elsewhere herein. 
     In various embodiments, any or all portions of functionality associated with any one or more of Scrambler  310 , ECC Encoder  320 , ECC Decoder  360 , and Descrambler  370  are implemented at least in part using one or more of Data Processing  121  and ECC  161  (both of  FIG. 2A ). 
     Control Flows for Zero/One Balance Restoration 
       FIG. 5  illustrates selected control flow details for an embodiment of the SSD of  FIGS. 2A, 2B, and 4 , providing particular details regarding write related operations and read related operations. Write operations start with action  410  and continue through  430 . While a return path is not explicitly drawn, subsequent write operations start anew with action  410 . Similarly, read operations start with action  440 , continue through  460 , and conditionally continue through  480 . While a return path is not explicitly drawn, subsequent read operations start anew with action  440 . It is assumed that at least an initial write precedes a read to the same location. Otherwise, except for contrived cases, such as in testing, the read operations and write operations are generally invoked independently as application needs dictate, for the same or generally different locations. Nevertheless, in a heuristic example, the first read operation  440  conceptually continues immediately after the last write operation  430  for a same location. 
     Considering in more detail the write related operations, original data to be written to the NVM is generally first scrambled in action  410 , such as via encryption or use of an LFSR. Except where more specificity is employed, the term “scrambling” as used herein refers to the manipulation of the original data to be written via any manipulation or selection that results in a known statistical distribution among the various states stored in the NVM. Scrambling methods include encryption and LFSR techniques. (See also Scrambler  310  of  FIG. 4 ). In some encryption embodiments, the scrambling is in accordance with at least one version of the AES encryptions specification. In some LFSR embodiments, the scrambling is in accordance with at least one choice of LFSR. In some embodiments, the scrambling is more directly determined via the selection of one or more test patterns, providing a chosen statistical distribution of states when written to the NVM (without necessarily using encryption or LFSR processing). 
     The LFSR is a hardware shift register having a combinational logic feedback network generating an input bit from a linear function of selected taps of the shift register, or a software model thereof. The LFSR generates a deterministic pseudorandom sequence. At least conceptually, the LFSR-generated pseudorandom sequence is modulo 2 added to the original data to provide the scrambled data. 
     Subsequently, the scrambled data is next optionally ECC encoded, as illustrated in action  420 . (See also ECC Encoder  320  of  FIG. 4 .) ECC encoding provides redundant information that facilitates data recovery (via error correction) in the face of errors that arise for a variety of reasons when using NVM. Such errors are more prevalent, and thus ECC encoding more advisable, with one or more of smaller geometries, greater use, greater age, greater temperature excursions, and use of MLC memories. 
     The scrambled and optionally ECC encoded data is then written to the NVM, as shown in action  430 , the last of the write related operations. The distribution of states being written is known as a result of the scrambling. In the case of the use of SLC memories and AES encryption, the zero-one distribution is known to be 50-50 (i.e., 50 percent zeroes and 50 percent ones). In the case of the use of a 4LC (4-level MLC) memories and AES encryption, the distribution after writing both lower and upper pages is known to be 25-25-25-25 (i.e., 25 percent in each of the four states). 
     In some embodiments, at least one reference region is dedicated for the use of one or more test patterns as discussed above. In some embodiments, the location of the reference region is selected to minimize (or conversely, to maximize) the impact on the test patterns of various NVM write/read artifacts. In some embodiments, the reference region is a reference page, and its location is chosen to be a last page written in a block, so as to minimize the impact of write disturbs on the data written. As some of the phenomena affecting the voltage distributions are time and/or temperature variant, the reference region serves as a known measure of these effects on zero/one disparity. 
     Considering in more detail the read related operations, starting in action  440 , one or more read units are read from the NVM and the distribution of states is captured. In some embodiments, each of a zeroes count and a ones count are directly determined. Next, in action  450 , an attempt is made to recover the original data. This performs the inverse of whatever data manipulation operations were performed prior to writing. ECC encoding was optionally added prior to writing, and thus the read units next optionally undergo ECC decoding. (See also ECC Decoder  360  of  FIG. 4 ). On a per read unit basis, if ECC decoding is successful, then descrambling is performed next, as appropriate. E.g., where AES encryption was used prior to writing, AES-decryption is performed. Or, where an LFSR-generated pseudorandom sequence was used, the same sequence is modulo 2 added to the ECC decoded data from the read unit. 
     The read related operations conclude early when the original data is recoverable, either without error or for errors that are correctable via ECC decoding. See the “no” path from decision  460 . However, on uncorrectable errors of any of the read units, actions  470  and  480  are also performed. See the “yes” path from decision  460 . In action  470 , a disparity in the distribution of states is evaluated. (See also Imbalance Detector  340  of  FIG. 4 ). In some embodiments, the determined disparity is a determined difference between the zeroes count and the ones count. In various embodiments, the determined disparity is computed over all of the read units, even if less than all of the read units had uncorrectable (e.g. hard-decision decode) errors. 
     Next, in action  480  an adjusted value (a.k.a. a threshold shift) for at least one read threshold is determined at least in part based on the magnitude of the determined disparity. In some embodiments, if the magnitude of the determined disparity is below a predetermined tolerance, the read threshold is not adjusted. In some embodiments, a multi-factor “correction algorithm” is employed for determining the adjusted read threshold, for which the magnitude of the determined disparity is but one factor. 
     In some embodiments, the correction algorithm takes the form of a lookup table used to select a replacement value for the read threshold. The magnitude of the determined disparity is the basis for at least part of the index in the lookup table. In some embodiments, the lookup table is pre-characterized (weighted) based on the particular vendor of the NVM being used. In some embodiments, the index has additional components, comprising one or more of: program/erase cycles, age, retention time (time since the last write), temperature, and any other factors that may pertain to drift of, or disturbances to, the device threshold voltages distributions of the NVM. (See also Balance Restoration Logic  380  of  FIG. 4 ). 
     Here and throughout the detailed description, it should be remembered that in commonly used flash memory microarchitectures, granularity of operations is different; e.g. a read unit is a minimum size for reading, a page is a minimum size for writing (e.g. programming), and a block is a minimum size for erasing. Each block includes a corresponding plurality of pages, and each page includes a corresponding plurality of read units. In various embodiments, an SSD controller reads from and/or writes to one or more flash memories in quanta corresponding to any one or more of: one or more read units, one or more pages, and one or more blocks. 
     In some embodiments, disparities are evaluated on an entire page basis. In some embodiments, disparities are evaluated on a read unit basis. The disparity evaluation performed in conjunction with an uncorrectable (e.g. hard-decision decode) error on a read is performed with respect to the same (page, or read unit) location as written in the most recent write that included that same location. 
     Optimization of Read Thresholds 
     Embodiments represented by  FIG. 5  adjust at least one read threshold, or read reference voltage, in response to an uncorrectable (e.g., a hard-decision decode) error. Embodiments represented by  FIGS. 6A, 6B and 7A-7D  adjust at least one read threshold in response to any one or more of manufacturing characterization, initial use, a timer (e.g. periodic, irregular, or random), a bit error rate that is above a threshold, and an uncorrectable (e.g., hard-decision decode) error. Various embodiments represented by  FIGS. 6A, 6B, and 7A-7D  are operated in contexts where blocks of NVM are managed in groups, and adjustment of at least one read threshold for all of the blocks of a particular group is based on partial reads of a sampling of the blocks of the particular group. For example, if at least some of the partial reads meet a condition, then the read threshold is adjusted for all of the blocks of the particular managed group. In various embodiments, the adjusting is via estimating device threshold voltage distributions using techniques applicable to Gaussian distributions. In some embodiments, techniques represented by  FIG. 5  are used in conjunction with techniques represented by  FIGS. 6A and 6B . 
       FIG. 6A  illustrates a flow diagram of selected details of an embodiment of optimizing of read thresholds for an NVM (e.g., of an SSD). In various embodiments, the NVM is provided with default operating read thresholds specified by a manufacturer of the NVM and guaranteed by the manufacturer to function correctly. Reading a read unit of the NVM is performed in accordance with current read thresholds. Initially, the current read thresholds are set to the default operating read thresholds, in action  510 . In some embodiments, the default operating read thresholds are written to Control/Status Register  336  and configure Programmable Read Voltage Circuitry  334  of  FIG. 4 . 
     Reads of the NVM are performed in accordance with the current read thresholds, in action  520 . Conceptually in parallel with the reads of action  520 , the controller also performs Offline Tracking  540  on one or more managed groups of blocks that contain at least some data retrieved by the reads of action  520 , as described elsewhere herein. The Offline Tracking is enabled to update the current read thresholds with new operating read thresholds, in action  530 , that are optimized to improve one or more of performance, power consumption, and reliability. In some embodiments, the new operating read thresholds are written to the Control/Status Register  336  and configure Programmable Read Voltage Circuitry  334  of  FIG. 4 . In various embodiments, subsequent reads are performed in accordance with current read thresholds that have been updated to the new operating read thresholds update by the Offline Tracking. The Offline Tracking is described as operating conceptually in parallel with the reads, in that at least in some embodiments, reads of the NVM in action  520  are performed such that reads of the NVM in action  540  are prevented from being performed simultaneously with the reads of the NVM in action  520 . For example, the reads of the NVM in action  520  are performed at a higher priority than the reads of the NVM inaction  540 . For another example, the reads of the NVM in action  540  are performed in a background manner, such as when the NVM is otherwise idle. 
     In various embodiments, the SSD periodically re-evaluates the current read thresholds. A timer tracks time elapsed since the last Offline Tracking was performed, in action  550 . When the timer expires, the Offline Tracking is performed again. In some embodiments, the timer is configurable through any one or more of software, firmware, and hardware. In some embodiments, the timer is configured to one or more weeks. 
       FIG. 6B  illustrates a flow diagram of selected details of an embodiment of Offline Tracking  540  of device threshold voltages in a managed group of blocks of an NVM. Offline Tracking reduces the number of read errors in a managed group of blocks by adjusting the current read thresholds as the device threshold voltage distributions shift (e.g. due to aging). Reducing the number of errors improves performance, reduces power consumption and/or improves the lifetime of an NVM. In some embodiments, offline tracking is performed in whole and/or incrementally when an SSD, any portions of NVM used in an SSD, or any portions of NVM used in any context, are idle, to reduce the impact on operations other than the offline tracking (e.g. accesses from a host, recycling, and/or map management). In various embodiments, an advantage of offline tracking is that it estimates the device threshold voltage distribution shift without maintaining reference information (e.g., a reference block or a reference read unit), or storing device threshold voltage distribution information, thus reducing overhead. 
     In various embodiments, a managed group of blocks are managed to share at least one determined characteristic. Examples of a determined characteristic include any one or more of a number of program cycles, a number of erase cycles, and a programming window. In some usage scenarios, blocks with similar program/erase counts and/or retention behave similarly. For example, any one of the R-blocks shown in  FIG. 1  may be considered a managed group of blocks. Because the managed group of blocks is managed to share determined characteristics, randomly selected blocks are representative of the group of managed blocks. In some embodiments, the managed group of blocks is a managed group of blocks comprising scrambled data (e.g., an R-block). An example of a managed group of blocks is an R-block. 
     One or more representative blocks are randomly selected from the managed group of blocks. All data within the representative blocks is read in accordance with the current read thresholds, in action  541 . For example, this may be performed by reading all read units within the representative block(s). 
     If action  542  determines that a read unit in the representative blocks meets a condition, then in response the current read thresholds of the read unit are adjusted by writing new operating read thresholds to Control/Status Register  336  and configuring Programmable Read Voltage Circuitry  334  of  FIG. 4 . If the read unit does not meet the condition, then in response the current read thresholds are left unchanged and the Offline Tracking ends. In some embodiments, the condition is one or more of exceeding a target BER at the current read thresholds and/or exceeding a target disparity of the zero/one balance at the current read thresholds. 
     In some embodiments, exceeding a target BER and/or target disparity of the zero/one balance at the current read threshold indicates that the device threshold voltage distributions have shifted to new device threshold voltage distributions. The target BER and/or target disparity of zero/one balance is configurable through any one or more of hardware, firmware, and software. In some embodiments, the target BER is set to one half the correctable BER (e.g. if up to 80 bits per read are correctable, then the target BER is set to 40 bits per read). In various embodiments, ECC Decoder  360  of  FIG. 4  detects the BER during a read of a read unit. 
     In action  543 , the read unit is read in accordance with sample read thresholds to sample and characterize the new device threshold voltage distributions. In some embodiments, the sample read thresholds comprise two sets of sample read thresholds. A first set of sample read thresholds is computed, based on the old read thresholds. The read unit is read in accordance with the first set of sample read thresholds, and based on the results, a second set of sample read thresholds is computed and the read unit is read in accordance with the second set of sample read thresholds. 
     In some embodiments, six LSB sample read thresholds (used, e.g., by six respective array accesses) are sufficient to characterize the new device threshold voltage distributions for a 4LC memory. The new device threshold voltage distributions are Gaussian, thus two LSB samples are sufficient to determine respective mean and standard deviation of each of the new device threshold voltage distributions. The first set of sample read thresholds is computed, as described elsewhere herein, e.g. Equations 1.10, 1.11, and 1.12 (Equations 1.1-1.15 are described in Appendix “Selected Details of Particular Embodiments of Optimization of Read Thresholds” attached, and incorporated by reference for all purposes). The read unit is read in accordance with the first set of sample read thresholds to generate a second set of sample read thresholds, as described elsewhere herein, e.g. Equations 1.13, 1.14, and 1.15, that are statistically valid for blocks comprising scrambled data. In other embodiments, two LSB sample read thresholds and two MSB sample read thresholds are sufficient to estimate the new device threshold voltage distributions. 
     Based on at least some of the results of reading the read unit in accordance with the sample read thresholds, the new device threshold voltage distributions are estimated  544 . As illustrated in  FIGS. 7A-7D , the means and the standard deviations of D1′  621 , D2′ 622 , and D3′  623  are estimated. In some embodiments, some results of reads performed in accordance with the sample read thresholds are used to look-up intermediate values in a Q-table with a binary tree search. The intermediate values and some of the results are used to compute the estimated means and standard deviations of the new device threshold voltage distributions. 
     The new operating read thresholds are calculated  545 , based upon the estimated means and standard deviations of the new device threshold voltage distributions. In some embodiments, E′  620  cannot be estimated, because the erasure level is not measurable. In some embodiments, the three new operating read thresholds (V NEW1    650 , V NEW2    651 , and V NEW3    652 ) are calculated using Equations 1.7 and 1.8. 
     Once the new operating read thresholds have been calculated, the current read thresholds are updated to the new operating read thresholds for the read unit in the representative blocks, in action  546 . In some embodiments, the current read thresholds for other (e.g. other than the representative) blocks within the managed group of blocks are also updated to the calculated new operating read thresholds. In various embodiments, multiple representative blocks are selected for processing via offline tracking as a set, and the new operating read thresholds are averaged for the set to reduce block-to-block variation within a managed group of blocks (e.g., an R-block). 
     In various embodiments, one or more operations (or portions thereof) illustrated in  FIGS. 6A and 6B  are performed by and/or managed by an SSD controller (such as SSD Controller  100  of  FIG. 2A ) or elements thereof. For example, in some embodiments, one or more operations illustrated in  FIGS. 6A and 6B  are implemented by and/or managed by firmware executed by CPU Core  172  of  FIG. 2A . In various embodiments, one or more operations (or portions thereof) illustrated in  FIGS. 6A and 6B  are performed by and/or managed by any one or more elements illustrated in  FIG. 4 . For example, in some embodiments, detection of exceeding a target disparity of zero/one balance (e.g., as performed by some embodiments of Meets Condition?  542 ) is performed at least in part by Imbalance Detector  340  of  FIG. 4 . 
       FIGS. 7A through 7D  conceptually illustrate device threshold voltage distributions in a 4LC memory. For the purposes of this discussion, as in  FIGS. 3A through 3D , each hill-like bump is an abstraction for an independent Gaussian-like curve representing a device threshold voltage probability distribution for a respective state of a read unit sized portion of an NVM. The device threshold voltage axis is drawn with increasing positive voltage to the right. An absolute scale is purposefully not provided, and no reference points are identified, such that the plots apply more generally to a larger population of NVMs.  FIG. 7A  conceptually illustrates a 4LC memory that stores two bits per cell. There are four device threshold voltage distributions (E  600 , D1  601 , D2  602 , and D3  603 ), with three current read thresholds (V OLD1    610 , V OLD2    611 , and V OLD3    612 ) that delineate the device threshold voltage distributions corresponding to the different states. 
       FIG. 7B  conceptually illustrates a 4LC with shifted device threshold voltage distributions. There are four new device threshold voltage distributions (E′  620 , D1′  621 , D2′  622 , and D3′  623 ). Note that the three current read thresholds no longer cleanly separate the new device threshold voltage distributions. For example, some parts of D2′  622  lie to the right of V OLD3    612  and would be incorrectly identified. 
       FIG. 7C  conceptually illustrates sample read thresholds in a 4LC with shifted device threshold voltage distributions. In various embodiments,  FIG. 7C  conceptually illustrates the sample read thresholds used in action  543 . There are six sample LSB read thresholds used to estimate the new device threshold voltage distributions. The first set of sample read thresholds (V SAMPLE1,1    630 , V SAMPLE2,1    631 , and V SAMPLE3,1    632 ) are chosen to fall close to the centers of D1  601 , D2  602 , and D3  603 . In some usage scenarios, the first set of sample read thresholds are relatively close to the centers of D1′  621 , D2′  622 , and D3′  623 . The first set of sample read thresholds is computed, as described elsewhere herein, e.g. Equations 1.10, 1.11, and 1.12. 
     The second set of sample read thresholds (V SAMPLE1,2    640 , V SAMPLE2,2    641 , and V SAMPLE3,2    642 ) are chosen to fall within D1′  621 , D2′  622 , and D3′  623 , but offset from the first set and lying on different sides of the centers of D1′  621 , D2′  622 , and D3′  623 . The read unit is read in accordance with the first set of sample read thresholds to generate a second set of sample read thresholds, as described elsewhere herein, e.g. Equations 1.13, 1.14, and 1.15. 
       FIG. 7D  conceptually illustrates new operating read thresholds in a 4LC with shifted device threshold voltage distributions. The new operating read thresholds V NEW1    650 , V NEW2    651 , and V NEW3    652  are calculated by the Offline Tracking. Note that in contrast to the current read thresholds (V OLD1 , V OLD2 , and V OLD3 ), the new operating read thresholds (V NEW1 , V NEW2 , and V NEW3 ) cleanly separate the new device threshold voltage distributions, thus reducing the likelihood of a bit error and/or an uncorrectable (e.g. hard-decision decode) error. In various embodiments,  FIG. 6D  conceptually illustrates the new operating read thresholds from Calculate New Operating Read Thresholds  545 . 
     Adjusting the Read Reference Voltages 
     In accordance with some illustrative embodiments, a portion  140  of the buffer module  131  ( FIGS. 2A and 4 ) is used for storing one or more channel parameters. In accordance with one illustrative embodiment, a channel parameter is used to determine whether or not an adjustment to the read reference voltage, V READ , can be avoided altogether based on how close the current V READ  for the memory cell or block of memory cells is to the most recently used V READ  for the same memory cell or block of memory cells. When the scheduling logic  193  receives a read command from the CPU  171 , the read command includes read reference voltage values to be used when performing the read operation. In order to adjust the reference voltages, the scheduling logic  193  uses a set feature or other command supported by the NVM  199  to adjust the read reference voltage values. Performing the set feature or other command adds extra latency for each page read operation. This additional latency results in the incurrence of a read performance penalty. 
     In accordance with an illustrative embodiment, the additional latency is avoided in some cases by not performing the set feature or other command if a determination is made that the last read reference voltage value that was used is sufficiently close to the current read reference voltage value included with the read command. In accordance with this illustrative embodiment, a channel parameter, D, to be used for this purpose is stored by the SSD controller  100  in the portion  140  of the buffer module  131 . The value of D is either preselected or determined periodically based on channel conditions detected by the above-described Offline Tracking process. Typically, a separate D value or group of D values will be stored in portion  140  for each managed group of blocks (e.g., each R-block), due to the fact that all of the memory cells of a given R-block are typically read during the same read cycle using the same read reference voltage(s) (e.g., V READ1  for SLC and V READ1 , V READ2  and V READ3  for MLC). For example, in the case where each block is made up of MLCs, each R-block may have three D values associated with it, D1, D2 and D3, which, in turn, are associated with the V READ1 , V READ2  and V READ3  values, respectively. The respective D values are stored at respective addresses in the channel parameter buffer portion  140  and used by scheduling logic  193  of the device I/F logic  191  to determine, on the fly at read time, whether adjustments to the respective read reference voltages need to be made. 
     In particular, the scheduling logic  193  ( FIG. 2A ) takes the difference between the current read reference voltage for the memory cell that is about to be read (V READ_CURRENT ) and the most recent read reference voltage that was last used for reading the same memory cell (V READ_LAST ) and compares the absolute value of the difference (Diff_Abs) to the corresponding D value stored in the channel parameter portion  140 . If the scheduling logic  193  determines that the Diff_Abs value is less than the respective D value, then the scheduling logic  193  decides that no adjustment needs to be made to the read reference voltage and therefore reads the memory cell using the V READ_LAST  value. Thus, in this case, the latency associated with executing the set feature or other command to adjust the read reference voltage value is avoided. 
     On the other hand, if the scheduling logic  193  determines that the Diff_Abs value is greater than or equal to the D value, then the SSD controller  100  adjusts the read reference voltage to a new value, V READ_CURRENT , and reads the memory cell using V READ_CURRENT . The process of adjusting the read reference voltages is described above with reference to  FIGS. 5-7D . 
     Performing the difference and comparison operations takes very little time, and takes much less time than typically required to adjust the read reference voltages. Consequently, in cases where it is determined that the read reference voltage needs to be adjusted, virtually no additional latency is added by the difference and comparison operations because these operations take a negligible amount of time to perform and are performed at read time by the scheduling logic  193 . 
     In general, the scheduling logic  193  is used to perform certain optimizations with respect to the order in which reads and writes are committed to the flash dies  194 . These optimizations ensure that reads and writes are performed on memory cells that are physically near one another to avoid disk seek latency. Consequently, the scheduling logic  193  already possesses the value of V READ_LAST . For this reason, the scheduling logic  193  is well suited to perform the difference and comparison operations. However, it will be understood by those of skill in the art, in view of the description being provided herein, that these operations may be performed at other suitable locations by other suitable logic within the SSD controller  100 . 
       FIG. 8  illustrates a flow diagram that represents the method described above for determining whether or not an adjustment to the read reference voltage can be avoided altogether. At read time, the D value associated with a memory cell or block of memory cells to be read is obtained from a channel parameter storage location inside of the SSD controller  100 , as indicated by block  701 . As described above, the storage location is typically inside of the buffer module  131 , and the D value is typically obtained by the scheduling logic  193 . An absolute value of a difference V READ_CURRENT  and V READ_LAST  for the memory cell or block of memory cells to be read is then determined by the SSD controller  100 , as indicated by block  703 . As indicated above, this operation is typically performed by the scheduling logic  193 . 
     This value, Diff_Abs, is then compared to the D value to determine whether or not Diff_Abs is less than the D value, as indicated by block  704 . If so, then V READ_LAST  will be used as the read reference voltage to read the memory cell or block of memory cells, as indicated by block  706 . The steps that would otherwise be involved in adjusting the read reference voltage to a new read reference voltage are skipped. 
     If it is determined at the step represented by block  704  that Diff_Abs is not less than D, then the aforementioned set feature or other command is executed to adjust the read reference voltage(s) of the target die to V READ_CURRENT , as indicated by block  707 , which is then used as the read reference voltage to read the memory cell or block of memory cells, as indicated by block  708 . As described above, the Offline Tracking process determines optimal read reference voltage values to be used in the future, stores them in NVM  199  and loads them into the buffer  131  so that they may be retrieved later by CPU  171  for all read requests. These values are the V READ_CURRENT  values that are used at the step represented by block  708 . These values also become the V READ_LAST  values for the next time that a read operation is performed on the respective flash die  194 . Because the Offline Tracking process is performed offline, i.e., in the background, it does not contribute to read latency. However, the adjustments could instead be made on the fly in real time if doing so would not result in too much add latency. 
     The method represented by the flow diagram shown in  FIG. 8  may be performed simultaneously for all dies in a drive. Assuming the tracking granularity is R-block level granularity, there may be different respective D values for each respective R-block, or some of the D values for some of the R-blocks may be the same whereas some of the D values for some of the other R-blocks may be different. It should be noted, however, that the invention is not limited with respect to the memory cell granularity with which the method is performed. For example, there is no reason why the method could not be performed on a block level or even a sub-block level. Also, if the method is performed on a multi-block level, it need not be performed on an R-block level, but may be performed on any multi-block level, i.e., on any grouping of blocks. 
     In accordance with another illustrative embodiment, the Offline Tracking process gathers channel information, such as signal-to-noise (SNR) ratio, BER, raw bit error rate (RBER), and the means and variances of the device threshold voltage distributions. Part or all of this channel information is stored as channel parameters in the channel parameter storage portion  140  of the buffer module  131 . In accordance with one illustrative embodiment, the channel parameters are used to adaptively vary the respective D values. When the SNR is relatively high, the RBER is relatively low. In accordance with embodiments described herein, it has been determined that this type of channel information can be used as a basis for adaptively varying the D value. For example, when the channel conditions indicate that the SNR is relatively high (RBER is relatively low), the value of D can be increased, which makes it more likely that the decision that is made at block  704  of  FIG. 8  will be answered in the affirmative. Consequently, there will be fewer times that the read reference voltage will need to be adjusted (block  707 ). In this way, the aforementioned read performance penalty incurred due to the latency associated with adjusting the read reference voltage is reduced or minimized. 
     Conversely, when the SNR is relatively low (the RBER is relatively high), the value of D is decreased, which makes it more likely that the decision that is made at block  704  of  FIG. 8  will be answered in the negative. Consequently, when the channel conditions are relatively poor, there will be more times that the read reference voltages will need to be adjusted. Adaptively varying D in this manner ensures that the performance penalty will be incurred less often and only when the channel conditions are determined to be relatively poor. 
       FIG. 9  illustrates a flow diagram that represents the method described above for adaptively varying D. The SSD controller  100  determines the channel conditions and stores one or more corresponding channel parameters at a storage location within the SSD controller  100 , as indicated by block  801 . In accordance with an illustrative embodiment, the SSD controller  100  calculates the SNR and/or the RBER and stores corresponding channel parameters in the channel parameter portion  140  of the buffer module  131 . The value of D is also stored in the channel parameter portion  140 . The initial value of D is typically preselected. The invention is not limited with respect to the types of channel parameters that are used for this purpose. The channel parameters may be based on any information that the SSD controller  100  may gather and process to determine the sensitivity of the BER or RBER to shifts in the read reference voltage. The manner in which the Offline Tracking process obtains these channel parameters has been described above with reference to  FIG. 4 . 
     A determination is made at block  802  as to whether or not the channel conditions are favorable, which is typically based on the SNR and/or the RBER, but could be based on any information that indicates a sensitivity of the RBER or BER to shifts in the read reference voltage. If it is determined at block  802  that the channel conditions are favorable, the value of D is increased, the channel parameter storage location is updated with the new value of D, and the process returns to the step represented by block  701  in  FIG. 8 , as indicated by block  803 . If it is determined at block  802  that the channel conditions are unfavorable, the value of D is decreased, the channel parameter storage location is updated with the new value of D, and the process returns to the step represented by block  701  in  FIG. 8 , as indicated by block  804 . The process represented by the flow diagram of  FIG. 8  is then performed in the manner described above, with the main difference being that the adapted D values are used. Another difference is that when adapted D values are used, the D values for each R-block are stored at locations in the NVM  199 , retrieved from the NVM  199  by the CPU  171 , and sent together with optimal read reference voltage values and the read requests to the scheduling logic  193 . This is somewhat different from what is shown in block  701  of  FIG. 8 . 
     An example of the manner in which the channel conditions can be determined by the Offline Tracking process will now be described with reference to  FIG. 10 .  FIG. 10  illustrates four device threshold voltage distributions  821 ,  822 ,  823 , and  824  for four states of a MLC. Each of the distributions has a mean, μ (mu), and a standard deviation, σ (sigma), which are known or can easily be obtained through well-known mathematical calculations. The SNR for the MLC can be calculated as:
 
SNR=20*log10( d /sigma),
 
where d is the distance between means of two neighboring distributions and sigma is the average of the sigmas of the two neighboring states. As shown in  FIG. 10 , distances d 1 , d 2  and d 3  correspond to the distances between the means of the distributions  821  and  822 ,  822  and  823 , and  823  and  824 , respectively. Thus, the SNRs are calculated as:
 
SNR( Va )=10*log10(2*(μ01−μ11)/(σ11+σ01));
 
SNR( Vb )=10*log10(2*(μ00−μ01)/(σ00+σ01));
 
SNR( Vc )=10*log10(2*(μ10−μ00)/(σ11+σ10));
 
     The SNR calculated in this manner may be used by itself or in conjunction with other factors in the step represented by block  801  ( FIG. 9 ) to determine whether the channel conditions are favorable or unfavorable. If the channel is noisy, this will typically lead to a higher RBER. The RBER is typically determined in the background by the Offline Tracking process. The RBER and/or the SNR may be used by the SSD controller  100  to ascertain the current channel conditions and to adapt the D values accordingly. 
     In accordance with another illustrative embodiment, the Offline Tracking process evaluates the channel conditions and uses them to set and to adapt a precision value for adjusting the read reference voltage values to their optimal values. The adapting of the precision value may be a rounding operation that rounds the read reference voltage value up, a truncating operation that truncates the read reference voltage value, a ceiling operation that rounds the read reference voltage up, or a flooring operation that rounds the read reference voltage down. In accordance with this embodiment, the D values described above with reference to  FIGS. 8 and 9  are not needed. An example of a channel condition that is evaluated and used for this purpose is the SNR. For example, the SNR may be determined using the above equations and then the precision may be set based on whether the SNR is high or low. If the SNR is relatively high indicating that the RBER is less sensitive to shifts in Vref, the precision may be set to a relatively low precision (e.g., 8), whereas if the SNR is relatively low indicating that the RBER is more sensitive to shifts in Vref, the precision may be set to a relatively high precision (e.g., 2). If the precision is 8, for example, and a rounding-up operation is being used to adjust the read reference voltage values, the read reference voltage value would be rounded up to the nearest multiple of 8 (e.g., 0, 8, 16, 24, 32, . . . and 248) when adjusting it to its optimal value. If the precision is 2, for example, and a rounding-up operation is being used to adjust the read reference voltage values, the read reference voltage would be rounded up to the nearest multiple of 2 (e.g., 0, 2, 4, 6, 8, . . . and 248) when adjusting it to its optimal value. Subsequently during a read operation, it is less likely that back-to-back read reference voltage values used for different blocks within the same die will be different. 
     Consequently, when the scheduling logic  193  compares the V READ_CURRENT  with V READ_LAST , there is a higher likelihood that there will be a match, thereby eliminating the need to adjust the read reference voltage. The overall result is that the Offline Tracking process makes fewer adjustments to the read reference voltages values. Compared to the embodiments of  FIGS. 8 and 9 , this embodiment requires no additional storage for storing the D values for every R-block, and the scheduling logic  193  can be less complex because it only needs to perform one comparison operation rather than one subtraction operation and one comparison operation. 
     Typically, when a flash memory device is shipped, it is configured with some default read reference voltage values, and typically each die has a default set of read reference voltage values, Va, Vb and Vc. Typically, when a read command is issued to any page in that die, the flash memory device applies the default values (Vb if for the lower page, Va and Vc if for the upper page) to the word line that contains the page to be read. 
     In accordance with the embodiments described above with reference to  FIGS. 5-7D , the default values, Va, Vb and Vc are adjusted to the optimal values by the Offline Tracking process. The term “optimal value,” as that term is used herein, is a value that the SSD controller  100  determines to be better than the default value in achieving a lower BER when performing the processes described above with reference to  FIGS. 5-7D . These optimal values are stored in flash NVM  199  and loaded into buffer  131  during boot-up. When the SSD controller  100  is about to execute a host command to read a page in a flash die  195 , it sets the optimal values, i.e., the V READ_CURRENT  values (one value for the lower page, two values for the MLC upper page, and four values for TLC upper page), for the target die  194 . The actual setting/adjusting is typically achieved by setting corresponding registers on the target die based on the values that are contained in the Control/Status Register  336 . After the register values are set, the next read command on the same die issued by the SSD controller  100  will use the newly set optimal values as the V READ_CURRENT  values and that flash die will apply the corresponding newly set values to the target word line. 
     As described above with reference to  FIG. 1 , if a read in a block belonging to one R-block of one of the dies is followed by a read in a block of a different R-block of the same die, the read that occurred earlier in time can necessitate an adjustment to the read reference voltages of the R-block that is going to be read later in time. By controlling the precision with which the Offline Tracking process adjusts the read reference voltage values to the optimal values, fewer adjustments will be necessitated by the above scenario and no additional storage is needed for D values. The following example demonstrates the way in which a lower precision setting reduces the number of adjustments that need to be made to the read reference voltages. 
     With reference again to  FIG. 1 , it will be assumed for this example that R-block  1  has an optimal read reference voltage Vb that was optimally set by the Offline Tracking process to Vb=28 and that R-block  2  has a read reference voltage Vb that was optimally set by the Offline Tracking algorithm to Vb=31. If the precision is set to 8, both values are rounded by the Offline Tracking process to 32. If two back-to-back read operations on the same die, e.g., die  0 , are targeted first at R-block  1  and then at R-block  2 , the V READ_CURRENT  value for R-block  2  and the V READ_LAST  value for R-block  1  are now both equal to 32. When the scheduling logic  193  compares V READ_CURRENT  with V READ_LAST , there will be a match, and therefore no adjustment to the read reference voltage will need to be made. In this way, adjustments to the read reference voltages will occur less frequently. On the other hand, if the precision had been set to 2, there would have been a mismatch that could have necessitated an adjustment to V READ_CURRENT  before the second read could occur. 
       FIG. 11  illustrates a flow diagram that represents the method performed by the SSD controller  100  to choose the rounding or truncating precision to be used for rounding off the read reference voltages. Block  901  represents the process of estimating the sensitivity of RBER to shifts in the read reference voltage. This process may be performed by using the above SNR equations to estimate the SNRs of the neighboring states. However, other information about the channel, such as a histogram of the tail region, for example, may be calculated and used to determine the sensitivity of RBER to shifts in the read reference voltage. Based on the estimation, the adjustment precision to be used is selected, as indicated by block  902 . As described above, each SNR provides an indication of the sensitivity of the RBER to shifts in the value of read reference voltage that is used to read the memory cell. This observation allows a lower precision to be used when the channel is less noisy and a higher precision to be used when the channel is more noisy. After the precision has been selected, the read reference voltage values are adjusted to the selected precision, as indicated by block  903 . 
     The process represented by the flow diagram of  FIG. 11  may be part of the process represented by the flow diagram of  FIG. 6A . For example, during the Offline Tracking process represented by block  540 , the channel conditions could be assessed and the rounding or truncating precision selected (blocks  901  and  902 ). Then, as part of the updating process represented by block  530 , the new current read thresholds would be adjusted within the selected precision and updated in the Control/Status Registers  336 . 
       FIG. 12  illustrates a lookup table (LUT)  910  that may be used to select the rounding precision value to be used in adjusting the read reference voltages. The LUT  910  is located at a suitable location in the SSD controller  100 , such as in the buffer module  131 . In accordance with this illustrative embodiment, the SNR is used as an index to the LTU  910 . The LUT  910  includes logic (not shown) that converts the SNR into an address pointer in the LUT  910  and outputs the corresponding precision rounding value to be used when rounding off the read reference voltages. For this example, an SNR that is equal to or greater than 16.1 causes a rounding value of 8 to be output from the LUT  910 , an SNR that is less than 16.1 and equal to or greater than 15.8 causes a rounding value of 4 to be output from the LUT  910 , and an SNR that is less than 15.8 causes a rounding increment value of 2 to be output from the LUT  910 . Of course, other ranges and precision values may be used for this purpose, as will be understood by those of skill in the art in view of the description being provided herein. 
       FIG. 13  illustrates a flow diagram that represents the method performed by the SSD controller  100  in accordance with another illustrative embodiment for determining whether or not an adjustment to the read reference voltage can be avoided altogether. When a read request is issued by the SSD controller  100 , the SSD controller  100  obtains the optimal read reference voltage values, i.e., the V READ_CURRENT  values, for the group of storage cells to be read (e.g., the R-block to be read). As indicated above, the optimal read reference voltages are channel parameters contained in the buffer  131  of the SSD controller  100 . This step is represented by block  921 . The SSD controller  100  then sends the read command along with the V READ_CURRENT  values to the scheduling logic  193 , as indicated by block  922 . The scheduling logic  193  then determines whether the current optimal read reference voltage value, V READ_CURRENT , is equal to the last optimal read reference voltage value used, V READ_CURRENT , as indicated by block  923 . If so, then the SSD controller  100  issues an NVM read command to the NVM  199  to read the page in the target die, as indicated by block  926 . The NVM  199  will then use the last optimal read reference voltage value that was used, V READ_LAST , to read the corresponding R-block page. 
     The algorithm represent by the flow diagram of  FIG. 13  has benefits that are similar to those of the algorithm represent by the flow diagram of  FIG. 8  in that both algorithms obviate the need to adjust the read reference voltage values of the current value is the same as the last value used. An advantage of the algorithm represented by the flow diagram of  FIG. 13  over that of  FIG. 8  is that no storage capacity is needed for storing the D values. Another advantage is that the scheduling logic  193  only has to perform one comparison operation rather than a difference operation and a comparison operation, which allows the scheduling logic  193  to have reduced complexity. 
     It should be noted that the invention has been described with reference to illustrative embodiments for the purposes of demonstrating the principles and concepts of the invention. The invention, however, is not limited to these embodiments. For example, although the above-described embodiment relates to MLC NAND flash memory, other embodiments can relate to SLC, TLC or any other suitable type of flash memory. Also, although the storage system and the SSD shown in  FIGS. 2A, 2B and 4  are depicted as having particular configurations and features, they are not limited to having these configurations or features, as will be understood by persons skilled in the art. As will be understood by persons skilled in the art, in view of the description provided herein, many variations may be made to the embodiments described herein and all such variations are within the scope of the invention.