Patent Publication Number: US-9837469-B1

Title: Resistive memory array using P-I-N diode select device and methods of fabrication thereof

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is a Continuation of U.S. patent application Ser. No. 13/165,652, filed Jun. 21, 2011, which is a Division of U.S. patent application Ser. No. 11/641,646, filed on Dec. 19, 2006, now U.S. Pat. No. 7,989,328, issued on Aug. 2, 2011, all of which are incorporated by reference herein in their entirety. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Technical Field 
     This invention relates generally to resistive memory arrays, and more particularly, to fabrication and use of P-I-N diodes as part of the array. 
     2. Background Art 
       FIG. 1  illustrates a resistive memory array  60 . The array  60  includes a first plurality of parallel conductors  62  (bit lines) BL 0 , BL 1 , . . . BLn, and a second plurality of parallel conductors  64  (word lines) WL 0 , WL 1 , . . . WLn overlying and spaced from, orthogonal to, and crossing the first plurality of conductors  62 . A plurality of memory structures  66  are included in the array. Each memory structure  66  includes a resistive memory cell  68  and a diode  70  in series therewith connecting a conductor WL of the plurality thereof with a conductor BL of the plurality thereof at the intersection of those conductors, with the diode  70  in a forward direction from the conductor WL to the conductor BL. For example, as shown in  FIG. 1 , in the memory structure  66   00 , resistive memory cell  68   00  and diode  70   00  connect in series WL 0  with BL 0 ; in the memory structure  66   01 , resistive memory cell  68   01  and diode  70   01  connect in series connect WL 1  with BL 0 , etc. 
     The diodes  70  have the conventional PN configuration shown in  FIGS. 2 and 3 , including a P+ region in contact with an N+ region. As is well known, a diode of this type, having a relatively low forward threshold voltage, readily conducts current in the forward direction upon application of forward potential thereto ( FIG. 2 ), but having a relatively high reverse breakdown voltage, does not conduct substantial current upon application of reverse potential thereto ( FIG. 3 ). 
     Because of this characteristic, these diodes  70  (oriented as shown in  FIGS. 1, 4 and 5 ) are used as select devices in the array  60  of  FIG. 1 .  FIGS. 1, 4 and 5  illustrate this utility. 
       FIG. 1  illustrates the programming of a selected resistive memory cell  68   00  of the array  60 . In such programming, V pg  is applied to word line WL 0 , and 0V is applied to bit line BL 0  and word lines WL 1  . . . WLn. Meanwhile, V pg  is applied to bit lines BL 1  . . . BLn. This causes a voltage V pg  to be applied across the memory structure  66   00 , in the forward direction from the word line WL 0  to the bit line BL 0 , sufficient to program the resistive memory cell  68   00 . All other resistive memory cells connected to the word line WL 0  and bit line BL 0  have 0V potential thereacross. Meanwhile, all the other resistive memory cells of the array  60  have V pg  applied thereacross in the reverse direction of the diode  70 , with V pg  applied thereto being less than the reverse breakdown voltage of the diode  70 . In this way, the diodes throughout the array  60  act as select devices to ensure that only the selected resistive memory cell is programmed and that the other resistive memory cells of the array are undisturbed. 
       FIG. 4  illustrates the erasing of the selected resistive memory cell  68   00  of the array  60 . In such erasing, V er  (lower voltage than V pg ) is applied to word line WL 0 , and 0V is applied to bit line BL 0  and word lines WL 1  . . . WLn. Meanwhile, V er  is applied to bit lines BL 1  . . . BLn. This causes a voltage V er  to be applied across the memory structure  66   00 , in the forward direction from the word line WL 0  to the bit line BL 0 , which (along with increased current applied through the resistive memory cell  68   00  as compared to programming current) is sufficient to erase the resistive memory cell  68   00 . All other resistive memory cells connected to the word line WL 0  and bit line BL 0  have 0V potential thereacross. Meanwhile, all the other resistive memory cells of the array  60  have V er  applied thereacross in the reverse direction of the diode  70 , with V er  applied thereto being less than the reverse breakdown voltage of the diode. In this way, the diodes throughout the array  60  act as select devices to ensure that only the selected resistive memory cell is erased and that the other resistive memory cells of the array are undisturbed. 
       FIG. 5  illustrates the reading of the selected resistive memory cell  68   00  of the array  60 . In such reading, V r  (lower voltage than V er ) is applied to word line WL 0 , and 0V is applied to bit line BL 0  and word lines WL 1  . . . WLn. Meanwhile, V t  is applied to bit lines BL 1  . . . BLn. This causes a voltage V r  to be applied across the memory structure  66   00 , in the forward direction from the word line WL 0  to the bit line BL 0 , sufficient to read the state of the resistive memory cell  68   00 . All other resistive memory cells connected to the word line WL 0  and bit line BL 0  have 0V potential thereacross. Meanwhile, all the other resistive memory cells of the array  60  have V r  applied thereacross in the reverse direction of the diode  70 , with V r  applied thereto being less than the reverse breakdown voltage of the diode. In this way, the diodes throughout the array  60  act as select devices to ensure that only the selected resistive memory cell is read and that the other resistive memory cells of the array are undisturbed. 
     While such an approach is useful, it will be understood that diodes of this type may exhibit an undesirable degree of current leakage, potentially resulting in undesired disturbing of other cells, along with a high level of power consumption. Meanwhile, it will be understood diodes used as select devices should provide high driving capability. What is needed is an approach wherein select devices in a resistive memory array exhibit very low current leakage along with high driving capability. What is further needed are methods for fabricating structures which are capable of providing these features, which methods are simple and efficient. 
     DISCLOSURE OF THE INVENTION 
     Broadly stated, the present method of forming a region of a P-I-N diode comprises providing a semiconductor body, providing a doped body adjacent the semiconductor body, the doped body containing a dopant of a selected conductivity type, and diffusing dopant of the selected conductivity type from the doped body into the semiconductor body to form a region of the selected conductivity type in the semiconductor body, the region of the selected conductivity type in the semiconductor body making up part of a P-I-N diode. 
     The present invention is better understood upon consideration of the detailed description below, in conjunction with the accompanying drawings. As will become readily apparent to those skilled in the art from the following description, there are shown and described embodiments of this invention simply by way of the illustration of the best mode to carry out the invention. As will be realized, the invention is capable of other embodiments and its several details are capable of modifications and various obvious aspects, all without departing from the scope of the invention. Accordingly, the drawings and detailed description will be regarded as illustrative in nature and not as restrictive. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The novel features believed characteristic of the invention are set forth in the appended claims. The invention itself, however, as well as said preferred mode of use, and further objects and advantages thereof, will best be understood by reference to the following detailed description of illustrative embodiments when read in conjunction with the accompanying drawings, wherein: 
         FIG. 1  illustrates programming of a resistive memory cell of a prior art resistive memory array; 
         FIGS. 2 and 3  illustrate a prior art diode as used in the array of  FIG. 1 ; 
         FIG. 4  illustrates erasing of a resistive memory cell of the resistive memory array of  FIG. 1 ; 
         FIG. 5  illustrates reading of a resistive memory cell of the resistive memory array of  FIG. 1 ; 
         FIGS. 6-23  illustrate method steps in fabricating a first embodiment of diode and resistive memory device in accordance with the present invention; 
         FIGS. 24-41  illustrate method steps in fabricating a second embodiment of diode and resistive memory device in accordance with the present invention; 
         FIGS. 42-54  illustrate method steps in fabricating a third embodiment of diode and resistive memory device in accordance with the present invention; 
         FIGS. 55 and 56  illustrate the present P-I-N diode and its operating characteristics; 
         FIG. 57  illustrates programming, erasing and reading of a resistive memory cell of the present memory array incorporating the present P-I-N diodes; 
         FIGS. 58 and 59  illustrate devices in relation to feature size; and 
         FIGS. 60-62  illustrate systems using devices of the previous embodiments. 
     
    
    
     BEST MODE(S) FOR CARRYING OUT THE INVENTION 
     Reference is now made in detail to specific embodiments of the present invention which illustrate the best mode presently contemplated by the inventors for practicing the invention. 
     Referring to  FIG. 6 , a monocrystalline P-silicon semiconductor substrate  100  is provided. A silicon nitride (Si 3 N 4 ) layer  102  is deposited thereon, and using standard photolithographic techniques, silicon nitride strips  102 A,  102 B (running perpendicular to the plane of the drawing of  FIG. 6 ) are formed. Using the silicon nitride strips  102 A,  102 B as a mask, the semiconductor substrate  100  is etched to form openings  104 A,  104 B,  104 C therein and to define elongated silicon semiconductor strips  106 A,  106 B ( FIG. 7 ). Next ( FIG. 8 ), a High Density Plasma (HDP) undoped oxide  108 A,  108 B,  108 C is deposited in the openings  104 A,  104 B,  104 C, and a chemical mechanical polish (CMP) is undertaken to planarize the top surface of the resulting structure. Referring to  FIG. 9 , a substantial portion of the HDP oxide  108 A,  108 B,  108 C is removed by etching from each of the openings  104 A,  104 B,  104 C, leaving a smaller portion of HDP oxide  108 D,  108 E,  108 F at the bottom thereof. Then, an N+, for example phosphorus doped oxide  110 A,  110 B,  110 C is deposited in each of the remaining openings  104 A,  104 B,  104 C, and a chemical mechanical polish is undertaken to planarize the top surface of the resulting structure. 
     Referring to  FIG. 10 , a portion of the phosphorus doped oxide  110 A,  110 B,  110 C is removed from each of the openings  104 A,  104 B,  104 C, leaving smaller portions  110 D,  110 E,  110 F thereof in each of the openings  104 A,  104 B,  104 C on the remaining HDP oxide portions  108 D,  108 E,  108 F respectively. HDP (undoped) oxide  112 A,  112 B,  112 C is then deposited in the openings  104 A,  104 B,  104 C, and a chemical mechanical polish is undertaken to planarize the top surface of the resulting structure. 
     Then, high temperature is applied to the resulting structure, causing phosphorus dopant to simultaneously diffuse from each of the phosphorus doped oxide portions  110 D,  110 E,  110 F into the adjacent silicon strips  106 A,  106 B on opposite sides thereof. That is, as will be seen in  FIG. 11 , dopant simultaneously flows and diffuses from the portion  110 E between the silicon strips  106 A,  106 B into both of those silicon strips  106 A,  106 B. Likewise, dopant simultaneously flows and diffuses from the portion  110 D into the silicon strip  106 A and into the silicon strip on the opposite side thereof (not shown), and simultaneously dopant flows and diffuses from the portion  110 F into the silicon strip  106 B and into the silicon strip on the opposite side thereof (not shown). In this way, N+ regions  114 A,  114 B are formed in the silicon strips  106 A,  106 B, extending across the strips, with intrinsic regions  116 A,  116 B respectively thereover. 
     Next, all material is removed from between the silicon strips ( FIG. 12 ), HDP (undoped) oxide  118 A,  118 B,  118 C is deposited in the openings  104 A,  104 B,  104 C ( FIG. 13 ), and a chemical-mechanical polish is undertaken.  FIG. 14  shows the resulting structure as viewed along the line  14 - 14  of  FIG. 13 . 
     Using standard photolithographic masking and etching techniques, the silicon nitride layer  102 A is patterned as shown in  FIG. 15 , forming rectangular silicon nitride bodies  102 A 1 ,  102 A 2 , and an etching step is undertaken to etch away the unmasked portions of silicon down to the N+ region  114 A to form pillars  116 A 1 ,  116 A 2  of silicon material. Openings are filled with undoped HDP oxide  119  ( FIG. 16 ), and a chemical-mechanical polish is undertaken. Next, the silicon nitride  102 A 1 ,  102 A 2  (and portions of the exposed HDP oxide  119 ) are removed, and an ion implant is undertaken, implanting for example boron into the exposed portions of the silicon pillars  116 A 1 ,  116 A 2 , to simultaneously form P+ regions  120 A,  120 B therein, to a depth so that in each pillar, there is defined an intrinsic region between the P+ region thereof and the N+ region (intrinsic region  121 A between P+ region  120 A and N+ region  114 A; intrinsic region  121 B between P+ region  120 B and N+ region  114 A,  FIG. 17 ). An activation step is than undertaken. 
     As an alternative, instead of implanting dopant into the pillars to form the P+ regions, a layer of P+ (for example boron) doped oxide  122  may be deposited over the structure of  FIG. 17  prior to implant, with a high temperature step being undertaken to simultaneously diffuse dopant from the oxide layer  122  into the pillars  116 A 1 ,  116 A 2  to form the P+ regions ( FIG. 19 ). The layer  122  is then removed and an activation step is undertaken. 
     Next, a metal layer  124 , for example cobalt, tantalum, nickel, titanium, platinum, palladium, tungsten, or hafnium is deposited over the resulting structure ( FIG. 20 ) and ( FIG. 21 ) a silicidation step is undertaken to form metal silicide regions  126 A,  126 B on the exposed silicon. The metal on the oxide does not react therewith and is removed after the silicidation step. Next, an insulating layer  128  is deposited over the resulting structure, and a metal layer  130  is deposited over the insulating layer  128  ( FIG. 22 ). Using conventional masking and etching techniques, the metal layer  130  is formed into strips  132 A.  1328  running perpendicular to the plane of the drawing of  FIG. 22  (see  FIG. 23 ). 
     In this embodiment, the elongated N+ regions  114 A,  114 B form bit lines of the array  460  of  FIG. 57 . As will be seen, a plurality of P-I-N diodes are formed, each connected in series with a resistive memory device. Each P-I-N diode includes an N+ region, an intrinsic (I) region, and a P+ region, in stacked relation. In contact with each P+ region is a silicide. On and in contact with this silicide is an insulating layer, and on and in contact with this insulating layer are metal strips. As an example, the silicide  126 A, insulating layer  128 , and metal strip  132 A together form the respective first electrode, insulating layer, and second electrode of a metal-insulator-metal (MIM) resistive memory device  140  connected in series with the respective P-I-N diode  142  (including P+ region  120 A, intrinsic region  121 A, and N+ region  114 A) associated therewith. The metal strips  132 A,  132 B form the word lines of the array  460  of  FIG. 57 . 
     In a second embodiment of the invention, referring to  FIG. 24 , a monocrystalline P-silicon semiconductor substrate  200  is provided. Using appropriate masking techniques, an N+ ion blanket implant, for example phosphorous, is undertaken, at for example 5E15 keV, to form N+ region  202 . A silicon nitride (Si 3 N 4 ) layer is then deposited over the resulting structure and, using appropriate masking techniques, the silicon nitride layer is patterned into strips  204 A,  204 B,  204 C running perpendicular to the plane of the drawing of  FIG. 25 . Using the silicon nitride strips  204 A,  204 B,  204 C as a mask, the N+ region  202  is etched to form openings  206 A,  206 B,  206 C therein ( FIG. 26 ) and to define elongated N+ regions  202 A,  202 B in the form of strips running perpendicular to the plane of the drawing of  FIG. 26 . Next ( FIG. 27 ), HDP undoped oxide  208 A,  208 B,  208 C is deposited in the openings  206 A,  206 B,  206 C, and a chemical mechanical polish (CMP) is undertaken to planarize the top surface of the resulting structure. Referring to  FIG. 28 , a substantial portion of the HDP oxide  208 A,  208 B,  208 C is removed by etching, leaving a smaller portion of HDP oxide  208 D,  208 E,  208 F. A metal layer  210 , for example cobalt, tantalum, nickel, titanium, platinum, palladium, tungsten, or hafnium is deposited over the resulting structure ( FIG. 28 ), and ( FIG. 29 ) a silicidation step is undertaken to form metal silicide regions  212 A,  212 B,  212 C,  212 D,  212 E on the sides of the exposed silicon. The metal on the oxide and nitride does not react therewith and the unreacted metal is removed after the silicidation step. 
     Next ( FIG. 30 ), HDP undoped oxide  214 A,  214 B,  214 C is deposited in the openings  206 A,  206 B,  206 C, and a chemical mechanical polish (CMP) is undertaken to planarize the top surface of the resulting structure. The silicon nitride  204 A;  204 B,  204 C is then removed ( FIG. 31 ), and the openings over the exposed silicon (including N+ strips  202 A,  202 B) are filled with HDP oxide  216 A,  216 B,  216 C ( FIG. 32 ). 
       FIG. 33  as a view taken along the line  33 - 33  of  FIG. 32 . The oxide strip on each of the N+ regions is patterned as shown in  FIG. 34  (oxide strip  216 A patterned as  216 A 1 ,  216 A 2 ,  216 A 3  and N+ region  202 A shown in  FIG. 34 ), using appropriate masking technology. This patterning of the oxide  216 A provides rectangular openings therethrough on and over the associated N+ strip  202 A, the openings being configured as shown in  FIG. 35  along the length of the associated N+ strip  202 A and substantially equal in width to the associated N+ strip  202 A. Monocrystalline epitaxial silicon layers  218 A,  218 B are then grown on the exposed silicon, rectangular in configuration, and filling the openings in the oxide layer  216 A ( FIG. 35 ). Similar to the previous embodiment, an ion implant and activation is undertaken, implanting for example boron into the exposed portions of the epitaxial silicon  218 A,  218 B, to simultaneously form P+ region  221 A,  221 B respectively therein, to a depth so that in each epitaxial layer, there is defined an intrinsic region  220 A,  220 B respectively between the P+ region thereof and the N+ region ( FIG. 35 ). 
       FIG. 36  is a view of the structure of  FIG. 35 , taken from the position in viewing  FIGS. 24-32 . Referring to  FIG. 37 , using appropriately patterned photoresist  224 A,  224 B,  224 C as masking to block off opposite edges of each P+ region and to leave exposed a central portion thereof, an implant of O 2  is undertaken into the exposed P+ regions  221 A,  223 A to form O 2 -implanted regions  225 ,  226 . After removal of the photoresist  224 A,  224 B,  224 C, a metal layer  227 , for example, cobalt, tantalum, nickel, titanium, platinum, palladium, tungsten, or hafnium is deposited over the resulting structure ( FIG. 38 ) and ( FIG. 39 , and  FIG. 40 , a view taken along the line  40 - 40  of  FIG. 39 ) a silicidation step is undertaken to form metal silicide regions  228 A,  228 B,  228 C,  228 D on the exposed silicon. The metal on the oxide and on the Oz-implanted silicon  225 ,  226  does not react therewith and the unreacted metal is removed after the silicidation step. 
     Next, an insulating layer  230  is deposited over the resulting structure, and a metal layer  232  is deposited over the insulating layer  230  ( FIG. 41 ). Using conventional etching techniques, the metal layer  232  is formed into strips running parallel to the plane of the drawing of  FIG. 41 . 
     In this embodiment, the elongated N+ regions  202 A,  202 B form bit lines of the array  460  of  FIG. 57 . As will be seen, a plurality of P-I-N diodes are formed, each connected in series with a resistive memory device. Each P-I-N diode includes an N+ region, an intrinsic (I) region, and a P+ region. In contact with each P+ region is a silicide. On and in contact with this silicide is an insulating layer, and on and in contact with this insulating layer are metal strips. As an example, the silicide  228 A, insulating layer  230 , and metal strip  232  together form the respective first electrode, insulating layer, and second electrode of a metal-insulator-metal (MIM) resistive memory device connected in series with the respective P-I-N diode ( 221 A,  220 A,  202 A) associated therewith. The metal strips  232  form the word lines in the array  460  of  FIG. 57 . 
     The silicide regions  212 A,  212 B,  212 C,  212 D,  212 E on each N+ strip act as low resistance conductors connecting that N+ region with its associated intrinsic region. 
     In a third embodiment of the invention, referring to  FIG. 42 , the structure formed is similar to that of  FIG. 9 , including monocrystalline substrate  300 , oxide regions  308 A,  308 B, N+ (for example phosphorus) doped oxide regions  310 A,  310 B, silicon strips  306 A,  306 B, and silicon nitride strips  302 A,  302 B,  302 C. At this point in the process, high temperature is applied to the resulting structure, causing phosphorus dopant to simultaneously diffuse from each of the phosphorus doped oxide portions into the adjacent silicon strips on opposite sides thereof. In this way, N+ regions  314 A,  314 B,  314 C,  314 D,  314 E are formed, the diffusion being controlled and limited so that an intrinsic portion remains between the N+ regions formed in each silicon strip ( 316 A,  316 B shown). An N+ activation step is then undertaken. 
     Next, portions of the phosphorus doped oxide  310 A,  310 B are removed, leaving smaller portions  310 C,  310 D on the HDP oxide  308 A,  308 B, and a metal layer  318 , for example cobalt, tantalum, nickel, titanium, platinum, palladium, tungsten, or hafnium is deposited over the resulting structure ( FIG. 43 ). A silicidation step is undertaken to form metal silicide regions  320 A,  320 B,  320 C,  320 D,  320 E on the exposed silicon. The metal on the oxide and nitride does not react therewith and the unreacted metal is removed after the silicidation step. The N+ oxide and oxide regions  308 A,  308 B are then removed, and the remaining openings are filled with (undoped) HDP oxide  322 A,  322 B ( FIG. 44 ). 
     Then ( FIG. 45 ), successive layers of N+ (for example phosphorous) doped oxide  330 , undoped oxide  332 , and P+ (for example boron) doped oxide  334  are applied and etched to form strips  335 A,  335 B running on and along the oxide  322 A,  322 B therebeneath ( FIG. 46 ), the strips  335 A,  335 B running perpendicular to the plane of the drawing of  FIG. 46 . Referring to  FIG. 47 , monocrystalline silicon epitaxial layers  336 A,  336 B,  336 C in the form of strips are then grown on the exposed silicon. Next, high temperature is applied to the resulting structure, causing dopant to simultaneously flow and diffuse from portions between the epitaxial strips into both of those epitaxial strips, to simultaneously form a pair of P+ regions in each of the silicon strips and a pair of N+ regions in each of the epitaxial strips. The P+ regions in each strip are separated by an intrinsic region, and the N+ regions in each strip are separated by an intrinsic region. The P+ and N+ regions adjacent the N+ doped oxide, undoped oxide, and P+ doped oxide are separated by an intrinsic region. For example, dopant flows from doped oxide region  334 A into the adjacent epitaxial layer  336 A and the adjacent epitaxial layer  336 B to form P+ regions  340  and  342  respectively therein. At the same time, dopant flows from doped oxide region  330 A into the adjacent epitaxial layer  336 A and the adjacent epitaxial layer  336 B to form N+ regions  344  and  346  respectively therein. Likewise, dopant flows from doped oxide region  334 B into the adjacent epitaxial layer  336 B and the adjacent epitaxial layer  336 C to form P+ regions  348  and  350  respectively therein. At the same time, dopant flows from doped oxide region  330 B into the adjacent epitaxial layer  336 B and the adjacent epitaxial layer  336 C to form N+ regions  352  and  354  respectively therein. Intrinsic regions  11 ,  12  remain as shown. All of these P+ and N+ regions are formed simultaneously. Then, an activation step is then undertaken. 
     Next ( FIG. 48 ), the strips  335 A,  335 B and oxide  322 A,  322 B are removed and the resulting openings are filled with undoped HDP oxide  338 A,  338 B.  FIG. 49  shows the resulting structure of  FIG. 48  taken along the line  49 - 49  of  FIG. 48 . 
     As shown in  FIG. 50 , photoresist is applied to the resulting structure and is patterned as shown in that Figure ( 360 A,  360 B,  360 C). An etching step is undertaken, using the photoresist as a mask, to form pillars  362 ,  364 ,  366 , respectively including N+ regions  346 A,  346 B,  346 C, intrinsic regions I 2 A, I 2 B, I 2 C, and P+ regions  342 A,  342 B,  342 C ( FIG. 51 ). The photoresist is removed, and the resulting openings are filled with undoped HDP oxide  363 A,  363 B ( FIG. 52 ).  FIG. 53  is a view of the structure of  FIG. 52  as viewed in a manner similar to the previous  FIGS. 42-48 . Similar to the previous embodiments, a metal layer  370  is deposited and patterned, and a silicidation step is undertaken to form silicide regions  372 A,  372 B,  372 C,  372 D,  372 E in contact with the respective P+ regions. An insulating layer  374  is deposited thereover, and a metal layer  376  is deposited on the insulating layer  374  and is patterned to provide strips running parallel to the plane of the drawing of  FIG. 54 . 
     In this embodiment, the elongated N+ regions  314 A,  314 B,  314 C,  314 D,  314 E form the bit lines of the array  460  of  FIG. 57 . As will be seen, a plurality of P-I-N diodes are formed. Each includes an N+ region, an intrinsic (I) region, and a P+ region. In contact with each P+ region is a silicide. On and in contact with this silicide region is an insulating layer, and on and in contact with this insulating are the metal strips. As an example, the silicide  372 B, insulating layer  374 , and metal strip  376  together form the respective first electrode, insulating layer, and second electrode of a metal-insulator-metal (MIM) resistive memory device connected in series with the respective P-I-N diode ( 340 , II,  344 ) associated therewith. The metal strips  376  form the word lines in the array  460  of  FIG. 57 . 
     The silicide regions  320 A,  320 B,  320 C,  320 D,  320 E on each N+ region act as low resistance conductors connecting that N+ region with its associated P-I-N diode. 
       FIGS. 55 and 56  illustrate the structure and operating characteristics of a P-I-N diode formed in accordance with the above methods. As shown in  FIG. 55 , the P-I-N diode includes N+ region and P+ region separated by an intrinsic region I. As illustrated in  FIG. 56 , with the diode forward biased (higher potential applied to P+ region than to N+ region, +V), current flows in the forward direction through the diode, with the diode exhibiting decreasing resistance with increasing current, as is typical with the P-I-N diode configuration. Meanwhile, such a diode exhibits a high reverse breakdown voltage (higher potential applied to N+ region than to P+ region, −V). 
       FIG. 57  illustrates a resistive memory array  460  incorporating the present invention. The array  460  includes a first plurality of parallel conductors  462  (bit lines) BL 0 , BL 1 , . . . BLn, and a second plurality of parallel conductors  464  (word lines) WL 0 , WL 1 , . . . WLn overlying and spaced from, orthogonal to, and crossing the first plurality of conductors  462 . A plurality of memory structures  466  are included in the array  460 . Each memory structure  466  includes a resistive memory cell  468  (including as shown for resistive memory cell  468   00  a first electrode  490 , insulating layer  492  on and in contact with first electrode  490 , and second electrode  494  on and in contact with the insulating layer  492 ), and a diode  470  in series therewith connecting a conductor WL of the plurality thereof with a conductor BL of the plurality thereof at the intersection of those conductors, with the diode thereof oriented in a forward direction from the conductor WL to the conductor BL. These memory structures  466  take the various forms shown and described above, including any of the various forms of P-I-N diode. The P-I-N diode characteristics insure that the diodes allow for proper programming, erasing and reading of a selected memory device (application of V pg  V er  and V r  as previously shown and described), meanwhile acting as select devices for other memory devices in the array  460  so as to avoid disturbing the state thereof. The diodes exhibit very low current leakage and high drivability. In addition, it will be noted that in each embodiment only two masking steps are required to fabricate the P-I-N diodes, resulting in high efficiency in the manufacturing process. 
     In the interest of forming an overall structure of very high density, the pillars in all embodiments are with advantage formed using minimum feature size F. This minimum feature size F also determines the space between adjacent pillars in the horizontal and vertical directions ( FIGS. 58 and 59 ). The unit block A of  FIGS. 58 and 59 , dimensions 2F×2F (dark lined box), including a pillar (dark hatching) and three adjacent spaces, repeats itself across the overall structure. Each block (including the indicated unit block A) has an area 2F×2F=4F 2 . Thus, where each pillar includes a single P-I-N diode and a single memory device associated therewith (i.e., the embodiments of  FIGS. 6-23  and also  FIG. 58 , pillar  116 A 2  illustrated in unit block A), one P-I-N diode and one memory device are provided for each area 4F 2 . 
     Device density is improved where each pillar includes two P-I-N diodes, with two memory device associated therewith (i.e., the embodiments of  FIGS. 24-54  and also  FIG. 59 , illustrating pillar  364  in unit block A). As such, two P-I-N diodes and two memory device are provided for each area 4F 2 , i.e., one P-I-N diode and one associated memory device for each area 2F 2  (4F 2 /2). This approach, it will be seen, provides improved scaling through increased devices density.  FIG. 60  illustrates a system  500  utilizing devices as described above. As shown therein, the system  500  includes hand-held devices in the form of cell phones  502 , which communicate through an intermediate apparatus such as a tower  504  (shown) and/or a satellite. Signals are provided from one cell phone to the other through the tower  504 . Such a cell phone  502  with advantage uses devices of the type described above. One skilled in the art will readily understand the advantage of using such devices in other hand-held devices. 
       FIG. 61  illustrates another system  600  utilizing devices as described above. The system  600  includes a vehicle  602  having an engine  604  controlled by an electronic control unit  606 . The electronic control unit  606  with advantage uses devices of the type described above. 
       FIG. 62  illustrates yet another system  700  utilizing devices as described above. This system  700  is a computer  702  which includes an input in the form of a keyboard, and a microprocessor for receiving signals from the keyboard through an interface. The microprocessor also communicates with a CDROM drive, a hard drive, and a floppy drive through interfaces. Output from the microprocessor is provided to a monitor through an interface. Also connected to and communicating with the microprocessor is memory which may take the form of ROM, RAM, flash and/or other forms of memory. The memory and other parts of the computer  702  with advantage use devices of the type described above. 
     The foregoing description of the embodiments of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Other modifications or variations are possible in light of the above teachings. 
     The embodiments were chosen and described to provide the best illustration of the principles of the invention and its practical application to thereby enable one of ordinary skill of the art to utilize the invention in various embodiments and with various modifications as are suited to the particular use contemplated. All such modifications and variations are within the scope of the invention as determined by the appended claims when interpreted in accordance with the breadth to which they are fairly, legally and equitably entitled.