Patent Publication Number: US-8125277-B1

Title: Dual loop frequency synthesizer

Description:
BACKGROUND OF THE INVENTION 
     The present specification relates generally to the field of signal generation for electronic devices. More particularly, the present specification relates to a frequency synthesizer. 
     U.S. Pat. No. 7,508,275, assigned to assignee of the present application, discusses frequency synthesizers as well as other electronic components. In general, fractional-N synthesizers can be utilized to provide one or more signals at a number of different frequencies. Generally, such systems utilize a phase locked loop (PLL) that includes a voltage controlled oscillator (VCO), a filter, a crystal oscillator, a fractional divider and a phase frequency detector. However, fractional-N synthesizers can be prone to providing spurious side band signals. An integer boundary spur or fractional spur can be caused by the carrier frequency of the PLL crossing over harmonics of the phase frequency detector sampling frequency. Spurious side band signals can degrade the performance of the device within which the frequency synthesizer is utilized. This performance degradation can be particularly problematic in wide bandwidth synthesizer applications. 
     Accordingly, there is a need for a frequency synthesizer that provides adaptable tuning and yet has reduced problems associated with spurious sidebands. Yet further, there is a need for a frequency synthesizer architecture that provides a high resolution, wide band frequency signals and avoids spurious signals. Yet further still, there is a need for a frequency synthesizer architecture that yields a highly integrated synthesizer that reduces size, weight, power, and complexity. 
     SUMMARY OF THE INVENTION 
     An exemplary embodiment relates to a frequency synthesizer. The frequency synthesizer provides a first output signal in the 2-8 GHz range. The frequency synthesizer includes a fractional loop and an integer loop. The fractional loop has a first output for providing a second output signal. The fractional loop includes a fractional divider. The fractional divider has a fractional divider input coupled to the first output and a fractional divider output coupled to a first input of a first phase frequency detector. A second input of the phase frequency detector is coupled to a reference signal. The reference signal has a frequency of less than 40 MHz. The integer loop has a first input coupled to receive the second output signal and a second output for providing the first output signal. The integer loop includes a first integer divider. The first integer divider has a first integer divider input coupled to receive the second output signal and a first integer divider output coupled to a first input of a second phase frequency detector. A second input of the second phase frequency detector is coupled to receive a second integer divider output from a second integer divider. A first input of a second integer divider is coupled to receive the first output signal. 
     Another exemplary embodiment relates to an electronic device. The electronic device includes a frequency synthesizer having a fractional loop and an integer loop. The output frequency of the signal of the fractional loop is constrained to a range of values between adjacent harmonics of a reference frequency used in the fractional loop. The signal of the fractional loop is received by the integer loop. 
     Another exemplary embodiment relates to a method of providing an output signal. The method comprises providing a first signal from a first oscillator at a first frequency to a fractional divider and providing a first divided signal from the fractional divider to a phase or frequency detector. The method also includes providing a reference frequency signal to the detector, and providing a control signal from the detector to the first oscillator. A frequency of the first signal is chosen to be in a range between adjacent harmonics of the referenced frequency signal. The method also concludes providing the first signal to an integer divider phase locked loop. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Exemplary embodiments will become more fully understood from the following detail description taken in conjunction with the accompanying drawings, wherein like numerals refer to like parts, and wherein: 
         FIG. 1  is a general block diagram of an electronic device including a frequency synthesizer in accordance with an exemplary embodiment. 
         FIG. 2  is a more detailed block diagram of the frequency synthesizer illustrated in  FIG. 1 , in accordance with another exemplary embodiment. 
         FIG. 3  is a drawing of the transfer function for a fractional N 1  loop in the frequency synthesizer illustrated in  FIG. 2  in accordance with a further exemplary embodiment. 
         FIG. 4  is a drawing of a transfer function for an integer N 2  loop in the frequency synthesizer illustrated in  FIG. 2  in accordance with yet another an exemplary embodiment. 
         FIG. 5  is a drawing of a transfer function for the frequency synthesizer illustrated in  FIG. 2  in accordance with still another exemplary embodiment. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Before describing in detail the particular improved system and method, it should be observed that the invention includes, but is not limited to a novel structural combination of conventional data/signal processing components and circuits, and not in the particular detailed configurations thereof. Accordingly, the structure, methods, functions, control and arrangement of conventional components and circuits have, for the most part, been illustrated in the drawings by readily understandable block representations and schematic diagrams, in order not to obscure the disclosure with structural details which will be readily apparent to those skilled in the art, having the benefit of the description herein. Further, the invention is not limited to the particular embodiments depicted in the exemplary diagrams, but should be construed in accordance with the language in the claims. 
     With reference to  FIG. 1 , an electronic device  2  includes a frequency synthesizer system  5 . Frequency synthesizer system  5  is preferably a dual loop frequency synthesizer configured to reduce spurious side bands associated with a high frequency signal capable of being provided at variable frequencies. In one embodiment, system  5  can be configured as a fractional-N 1 , integer-N 2  frequency synthesizer (e.g., a Dual-FIN Synthesizer). Preferably, electronic device  2  can be any electronic device that utilizes a signal generated by a frequency synthesizer. For example, system  5  can be a radio, a radar system, a computer system, a communication system, an optical system, etc. In addition, electronic device  2  can be part of a larger electronic device such as part of a component in a radio system such as a modulator, demodulator, decoder, clock circuit, synchronizer or any circuit that requires a variable frequency signal, etc. 
     Synthesizer system  5  preferably provides an output signal at an output  8 . The output signal at output  8  is preferably a high frequency signal such as a 2-8 gigahertz (GHz) signal capable of being provided at a number of different frequencies. Preferably, system  5  is configured so that the signal at output  8  can be advantageously provided across a wide band and yet is not susceptible to spurious side bands. Synthesizer system  5  is preferably configured so that spurious side bands associated with integer boundary spurs are reduced. Spurs can be caused by the carrier frequency of phase locked loops (PLLs) crossing over harmonics of the phase detector sampling frequency. 
     With reference to  FIG. 2 , fractional-N 1 , integer-N 2  frequency synthesizer system  5  preferably includes a fractional N 1  loop  10  and an integer N 2  loop  100 . Loops  10  and  100  can be provided on a common integrated circuit such as integrated circuit  15 . In a preferred embodiment, integrated circuit  15  is an ASIC device configured to provide the circuitry as shown in  FIG. 2 . In a preferred embodiment, loop filter  26 , VCO  28 , loop filter  126 , VCO  112 , loop filter power splitter  32  and reference oscillator  12  can be provided as off-chip devices. Alternative implementations can be utilized without departing from the invention. 
     Loop  10  includes a reference oscillator  12 , a differential amplifier  14 , an integer divider  16 , a phase frequency detector  18 , a charge pump  20 , a loop filter  26 , a voltage controlled oscillator (VCO)  28 , a power splitter  32 , a differential amplifier  34 , a fractional divider  36 , and a circuit  50  for providing a fractional plus integer input to divider  36 . Circuit  50  can include an integer register  56 , fractional modulator  52 , a fractional register  54 , and an adder  58 . 
     Charge pump  20  can be coupled to a reference current circuit  22  and a current setting circuit  24 . Current setting circuit  24  can be controlled by register settings. Filter  26  is embodied as an active or passive RC filter to provide stability to the control loop and attenuate reference spurious signals. Phase frequency detector  18  is preferably embodied as a BiCMOS logic function providing an up/down control signal to charge pump  20 . 
     Voltage controlled oscillator  28  is preferably an LC type oscillator having a control input coupled to loop filter  26  and an output coupled to power splitter  32 . Power splitter  32  can be embodied as a Wilkenson power splitter. Voltage controlled oscillator  28  provides an output signal at output  29  at a first frequency f 1  to amplifier  34  which operates as a buffer. Amplifier  34  can be configured to receive a differential signal. Although only shown as receiving a single signal in  FIG. 2 , the components of  FIG. 2  are preferably configured to receive and provide differential signals. The output signal from voltage controlled oscillator  28  at frequency f 1  is provided through amplifier  34  to fractional N 1  divider  36 . 
     Fractional N 1  divider  36  is preferably embodied as a BiCMOS logic function configured as a frequency divider. Fractional N 1  divider  36  preferably provides an output signal to an input of phase frequency detector  18  at a frequency of f 1  divided by N 1  where (N 0 +(2i+1)/2−Δ)&lt;N 1 &lt;(N 0 +(2i+1)/2+Δ), i=[0, 1, 2 . . . ] and 0&lt;Δ&lt;1/2. The value of the fractional portion of number N 1  is provided via fractional register  54  through fractional modulator  52 . Fractional modulator  52  can be a 25 bit third order fractional modulator and can provided its value through summer  58 . Summer  58  also receives an integer value from integer register  56 . Integer register  56  can provide the value for N 0 +i. Accordingly, summer  58  of circuit  50  provides value N 1  to divider  36 . 
     An input of phase frequency detector  18  also receives a signal from integer divider  16 . Reference oscillator  12  provides a reference oscillator signal at a frequency f 0  to integer divider  16  through amplifier  14  which operates as a buffer amplifier. Integer divider  16  divides the output signal from reference oscillator  12  at frequency f 0  by an integer R 1  provided by 32 bit data register  60 , to provide a signal at a frequency fr 1  to phase frequency detector  18 . 
     Phase frequency detector  18  compares the phase and frequency associated with the signal from divider  16  and the signal from divider  36  and provides a control signal to charge pump  20 . Detector  18  can be embodied as a phase frequency detector. The output signal from charge pump  20  controls the oscillator  28 , through loop filter  26  to adjust the frequency f 1  of output signal at output  29  from oscillator  28 . The frequency f 1  of the output signal at output  29  is controlled so that the frequency of the signal from divider  36  is equal to the frequency of the signal from divider  16  in accordance with phase locked loop (PLL) operation. Preferably, frequency f 1  is in the 2-8 GHZ range. 
     According to one embodiment, the output signal from voltage controlled oscillator  28  can have a variety of frequencies, preferably across a relatively continuous range. A preferred range of frequencies for the output signal from voltage controlled oscillator  28  is approximately 8 gigahertz (GHz). Preferably, a 32-bit data register provides values for the various components so that frequency f 1  is constrained to value between adjacent harmonics of frequency fr 1 . 
     Loop  100  can be configured as a PLL and includes a differential amplifier  114 , an integer divider  116 , a phase frequency detector  118 , a charge pump  120 , a loop filter  126 , a voltage controlled oscillator (VCO)  112 , a current settings circuit  122 , a reference setting circuit  124 , and a CSR circuit  125 . CSR circuit  125  performs cycle slip reduction to aid the control loop during frequency settling. 
     Charge pump  120  can be coupled to a reference current circuit  124  and a current setting circuit  122 . Current setting circuit  122  can be controlled by register settings. Filter  126  can be embodied as an active or passive RC filter to provide stability to the control loop and attenuate reference spurious signals. Voltage control oscillator  112  is preferably an oscillator having a control input coupled to loop filter  126  and an output coupled to output  8  and amplifier  114 , preferably configured as a buffer amplifier. 
     The output signal at output  8  is provided at a frequency f 2  from oscillator  112  through amplifier  114  to integer divider  116 . Integer divider  116  preferably receives an integer value from  32  data register  60  for dividing the frequency f 2  of the signal at output  8  by an integer value N 2 . Divider  116  provides a signal at the frequency of f 2 /N 2  to phase frequency detector  118 . 
     Phase frequency detector  118  also receives a signal at a frequency of f 1 /R 2  from integer divider  136 . Integer divider  36  receives the signal at output  29  from splitter  32  through amplifier  134 . Amplifier  134  is configured as a buffer amplifier. The signal at output  29  is provided at frequency f 1 . The integer value R 2  is preferably provided by data register  60 . Phase frequency detector  118  compares the phase and frequency associated with the signal from divider  116  and the signal from divider  136  and provides a control signal to charge pump  120  via filter  126 . 
     Detector  118  is preferably embodied as a BiCMOS logic function providing an up/down control signal to charge pump  120 . Divider  118  and  136  are preferably embodied as BiCMOS logic function configured as a frequency divider. 
     The output signal from charge pump  120  controls oscillator  112  to adjust the frequency f 2  of the output signal at output  8 . Preferably, a computing device, processor, or other circuitry provides values to data register  60  so that the frequency f 2  is appropriately chosen in accordance with values for R 1 , R 2 , N 1 , and N 2 . Preferably, the values are chosen so that the output frequency f 1  is constrained to a range of values between adjacent harmonics of the signal at frequency fr 1  to reduce spurious sideband signals. 
     The frequency fr 1  is 32 MHz in one preferred embodiment. Other values are possible, including, but not limited to, 16 MHz, 24 MHz, 64 MHz, etc. 
     With reference to  FIGS. 2 and 3 , the frequency f 0  provided by oscillator  12  is preferably a fixed frequency signal from a stable frequency source such as a crystal oscillator. The signal fr 1  from divider  16  is a divided version frequency signal f 0 . (fr 1 =f 0 /R 1 ). In  FIGS. 3 and 5 , 
               β   1     =       1     N   1       .           
The frequency fr 1  is a function of value of R 1  which is a function of the maximum operating frequency of the phase detector used in loop  10 . In accordance with phase locked loop (PLL) operation, f 1 =N 1 ×fr 1 , where f 1  is the frequency of the output signal of loop  10 . Preferably, frequency f 1  is constrained to a small range of frequencies located between adjacent harmonics of the reference frequency, fr 1 . In being constrained, f 1  min=(N 0 +(2i+1)/2−Δ) fr 1 , and f 1  max=(N 0 +(2i+1)/2+Δ)fr 1 .
 
     With reference to  FIGS. 2 and 4 , f 2 =N 2  fr 2  in accordance with one exemplary embodiment. In  FIGS. 4 and 5 , 
               β   2     =       1     N   2       .           
According to one embodiment, f 2  min=f 1 min/R 2 max and fr 2 max=f 1 max/R 2  min where R 2  min and R 2  max=a range of suitable values. R 2  is chosen to realize a frequency suitable for detector  118 . ΔR 2 =R 2  max−R 2  min. According to one embodiment, ΔR 2 =0 thereby providing a simplified synthesizer architecture.
 
     According to another embodiment, f 2  min=f 1  min/R 2  and fr 2  max=f 1  max/R 2  wherein f 1  min=(N 0 +(2i+1)/2−Δ)fr 1  and f 1  max=(N 0 +(2i+1)/2+Δ)fr 1 . Other mathematical expressions for exemplary embodiments of system  15  are given below: 
     
       
         
           
             
               
                 
                   
                     f 
                     
                       r 
                       ⁢ 
                       2 
                       ⁢ 
                       mi 
                       ⁢ 
                       n 
                     
                   
                   = 
                   
                     
                       f 
                       
                         1 
                         ⁢ 
                         min 
                       
                     
                     
                       R 
                       2 
                     
                   
                 
               
             
             
               
                 
                   
                     f 
                     
                       r 
                       ⁢ 
                       2 
                       ⁢ 
                       max 
                     
                   
                   = 
                   
                     
                       f 
                       
                         1 
                         ⁢ 
                         max 
                       
                     
                     
                       R 
                       2 
                     
                   
                 
               
             
             
               
                 
                   
                     f 
                     
                       1 
                       ⁢ 
                       min 
                     
                   
                   = 
                   
                     
                       ( 
                       
                         
                           N 
                           0 
                         
                         + 
                         
                           
                             
                               2 
                               ⁢ 
                               i 
                             
                             + 
                             1 
                           
                           2 
                         
                         - 
                         Δ 
                       
                       ) 
                     
                     ⁢ 
                     
                       f 
                       
                         r 
                         ⁢ 
                         1 
                       
                     
                   
                 
               
             
             
               
                 
                   
                     f 
                     
                       1 
                       ⁢ 
                       max 
                     
                   
                   = 
                   
                     
                       ( 
                       
                         
                           N 
                           0 
                         
                         + 
                         
                           
                             
                               2 
                               ⁢ 
                               i 
                             
                             + 
                             1 
                           
                           2 
                         
                         + 
                         Δ 
                       
                       ) 
                     
                     ⁢ 
                     
                       f 
                       
                         r 
                         ⁢ 
                         1 
                       
                     
                   
                 
               
             
             
               
                 
                   
                     f 
                     
                       r 
                       ⁢ 
                       2 
                       ⁢ 
                       min 
                     
                   
                   = 
                   
                     
                       
                         
                           N 
                           0 
                         
                         + 
                         
                           
                             
                               2 
                               ⁢ 
                               i 
                             
                             + 
                             1 
                           
                           2 
                         
                         - 
                         Δ 
                       
                       
                         R 
                         2 
                       
                     
                     ⁢ 
                     
                       f 
                       
                         r 
                         ⁢ 
                         1 
                       
                     
                   
                 
               
             
             
               
                 
                   
                     f 
                     
                       r 
                       ⁢ 
                       2 
                       ⁢ 
                       max 
                     
                   
                   = 
                   
                     
                       
                         
                           N 
                           0 
                         
                         + 
                         
                           
                             
                               2 
                               ⁢ 
                               i 
                             
                             + 
                             1 
                           
                           2 
                         
                         + 
                         Δ 
                       
                       
                         R 
                         2 
                       
                     
                     ⁢ 
                     
                       f 
                       
                         r 
                         ⁢ 
                         1 
                       
                     
                   
                 
               
             
           
         
       
     
     Preferably, frequency characteristics for the output signal at frequency f 2  is a range of frequencies between 2 and 8 gigahertz (GHz). R 2  is chosen in loop  100  via N 2  to realize the loop output frequency f 2 =N 2 ×fr 2 . Since N 2  is constrained to integer values, the output frequency signal at f 2  (for loop  100 ) can be represented as shown in Table I below. N 2  can be incremented as fr 2  is varied from f r2 min  to f r2 max . 
     
       
         
           
               
               
               
               
             
               
                   
                 TABLE I 
               
               
                   
                   
               
               
                   
                 k 
                 f r2min   
                 f r2max   
               
               
                   
                   
               
             
            
               
                   
                 k 
                 (N 2min  + k)f r2min   
                 (N 2min  + k)f r2max   
               
               
                   
                 0 
                 (N 2min  + 0)f r2min   
                 (N 2min  + 0)f r2max   
               
               
                   
                 1 
                 (N 2min  + 1)f r2min    
                 (N 2min  + 1)f r2max   
               
               
                   
                 2 
                 (N 2min  + 2)f r2min   
                 (N 2min  + 2)f r2min   
               
               
                   
                   
               
            
           
         
       
     
     For continuous frequency coverage 
     
       
         
           
             
               
                 ( 
                 
                   
                     N 
                     
                       2 
                       ⁢ 
                       min 
                     
                   
                   + 
                   0 
                 
                 ) 
               
               ⁢ 
               
                 f 
                 
                   r 
                   ⁢ 
                   2 
                   ⁢ 
                   max 
                 
               
             
             ≥ 
             
               
                 ( 
                 
                   
                     N 
                     
                       2 
                       ⁢ 
                       min 
                     
                   
                   + 
                   1 
                 
                 ) 
               
               ⁢ 
               
                 f 
                 
                   
                     r 
                     ⁢ 
                     2 
                   
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   min 
                 
               
             
           
         
       
       
         
           
             
               
                 
                   N 
                   
                     2 
                     ⁢ 
                     
                       mi 
                       ⁢ 
                       n 
                     
                   
                 
                 ⁢ 
                 
                   f 
                   
                     r 
                     ⁢ 
                     2 
                     ⁢ 
                     max 
                   
                 
               
               - 
               
                 
                   N 
                   
                     2 
                     ⁢ 
                     m 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     i 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     n 
                   
                 
                 ⁢ 
                 
                   f 
                   
                     r 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     2 
                     ⁢ 
                     m 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     i 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     n 
                   
                 
               
             
             ≥ 
             
               f 
               
                 r 
                 ⁢ 
                 2 
                 ⁢ 
                 min 
               
             
           
         
       
       
         
           
             
               
                 N 
                 
                   2 
                   ⁢ 
                   min 
                 
               
               ⁡ 
               
                 ( 
                 
                   
                     f 
                     
                       r 
                       ⁢ 
                       2 
                       ⁢ 
                       max 
                     
                   
                   - 
                   
                     f 
                     
                       r 
                       ⁢ 
                       2 
                       ⁢ 
                       min 
                     
                   
                 
                 ) 
               
             
             ≥ 
             
               f 
               
                 r 
                 ⁢ 
                 2 
                 ⁢ 
                 min 
               
             
           
         
       
       
         
           
             
               N 
               
                 2 
                 ⁢ 
                 min 
               
             
             ≥ 
             
               
                 f 
                 
                   r 
                   ⁢ 
                   2 
                   ⁢ 
                   min 
                 
               
               
                 
                   f 
                   
                     r 
                     ⁢ 
                     2 
                     ⁢ 
                     max 
                   
                 
                 - 
                 
                   f 
                   
                     r 
                     ⁢ 
                     2 
                     ⁢ 
                     min 
                   
                 
               
             
           
         
       
     
     Since N 2  must be an integer, N 2 min  is the smallest integer value that is larger than the value given by: 
     
       
         
           
             
               N 
               
                 2 
                 ⁢ 
                 min 
               
             
             = 
             
               
                 f 
                 
                   r 
                   ⁢ 
                   2 
                   ⁢ 
                   min 
                 
               
               
                 
                   f 
                   
                     r 
                     ⁢ 
                     2 
                     ⁢ 
                     max 
                   
                 
                 - 
                 
                   f 
                   
                     r 
                     ⁢ 
                     2 
                     ⁢ 
                     min 
                   
                 
               
             
           
         
       
     
     The minimum output frequency (f 2 min ) of loop  100  can be expressed as:
 
f 2 min =N 2 min f r2 min  
 
     where: 
     
       
         
           
             
               
                 
                   
                     f 
                     
                       r 
                       ⁢ 
                       2 
                       ⁢ 
                       min 
                     
                   
                   = 
                   
                     
                       
                         
                           N 
                           0 
                         
                         + 
                         
                           
                             
                               2 
                               ⁢ 
                               i 
                             
                             + 
                             1 
                           
                           2 
                         
                         - 
                         Δ 
                       
                       
                         R 
                         2 
                       
                     
                     ⁢ 
                     
                       f 
                       
                         r 
                         ⁢ 
                         1 
                       
                     
                   
                 
               
             
             
               
                 
                   
                     f 
                     
                       r 
                       ⁢ 
                       2 
                       ⁢ 
                       max 
                     
                   
                   = 
                   
                     
                       
                         
                           N 
                           0 
                         
                         + 
                         
                           
                             
                               2 
                               ⁢ 
                               i 
                             
                             + 
                             1 
                           
                           2 
                         
                         + 
                         Δ 
                       
                       
                         R 
                         2 
                       
                     
                     ⁢ 
                     
                       f 
                       
                         r 
                         ⁢ 
                         1 
                       
                     
                   
                 
               
             
           
         
       
     
     While the detailed drawings, specific examples and particular formulations given describe preferred and exemplary embodiments, they serve the purpose of illustration only. The inventions disclosed are not limited to the specific forms shown. For example, the methods may be performed in any of a variety of sequence of steps. The hardware and software configurations shown and described may differ depending on the chosen performance characteristics and physical characteristics. The mathematical formulas can be altered according to application criteria. For example, the type of device, communications bus, or processor used may differ. The term coupled to refers to direct and indirect coupling so that signals or forms of signals can be communicated between devices. The systems and methods depicted and described are not limited to the precise details, values and conditions disclosed. Furthermore, other substitutions, modifications, changes, and omissions may be made in the design, operating conditions, and arrangement of the exemplary embodiments without departing from the scope of the invention as expressed in the appended claims.