Patent Publication Number: US-2010109613-A1

Title: Switch control circuit with voltage sensing function and camera flash capacitor charger thereof

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to flash capacitor chargers, and more particularly to a flash capacitor charger with a voltage sensing function. 
     2. Description of the Prior Art 
     Please refer to  FIG. 1 , which is a diagram of a camera flash capacitor charger  1   00  according to the prior art. As shown in  FIG. 1 , the camera flash capacitor charger  100  comprises a transformer  110 , a switch control circuit  120 , a comparator CMP 1 , two feedback resistors R FB1 , R FB2 , a diode D 1 , a transistor M 1 , and an output capacitor C OUT . The camera flash capacitor charger  100  is utilized for increasing an input voltage source V DD  (outputs the voltage V DD ) to generate an output voltage source V OUT  (outputs the voltage V OUT ), which is utilized for providing voltage needed for a camera flash unit to flash. 
     Generally speaking, the output voltage V OUT  should be approximately 300V in order to make the camera flash unit flash. However, as the input voltage source V DD  is typically provided by a battery, the voltage V DD  is around 5V. Thus, the camera flash capacitor charger  100  increases the 5 Volts of the voltage source V DD  to 300V to allow the camera flash unit to flash. Besides, the voltage source V SS  may be seen as ground. 
     The transformer  110  includes a primary winding  111  and a secondary winding  112 . The primary winding  111  is coupled to the voltage source V DD  and the transistor M 1 . The secondary winding  112  is coupled to the output voltage source V OUT  and the voltage source V SS . More particularly, the secondary winding  112  is connected to the output voltage source V OUT  through the diode D 1 . 
     The transistor M 1  is an N-channel Metal Oxide Semiconductor (NMOS) transistor, and is coupled to the primary winding  111  and the voltage source V SS . When the transistor M 1  is turned on, the primary winding  111  is connected to the voltage source V SS  through the transistor M 1 , such that a current I is generated by the voltage source V DD  for charging the primary winding  111 ; when the transistor M 1  is turned off, the current I built up in the primary winding  111  begins to discharge through the secondary winding  112  to charge the output capacitor C OUT  through the diode D 1 . Through this charge/discharge mechanism, the output voltage V OUT  is steadily increased to the required voltage, e.g. 300V. 
     The feedback resistors R FB1 , R FB2  are coupled to the diode D 1  and the voltage source V SS  for providing a feedback voltage V FB , which is divided from the output voltage V OUT . 
     The comparator CMP 1  compares a reference voltage V REF  and the feedback voltage V FB  for generating a switch enabling signal S EN  accordingly. The switch enabling signal S EN  has two levels, “enabled” and “disabled,” for controlling on/off status of the transistor M 1 . More particularly, when the feedback voltage V FB  is lower than the reference voltage V REF , the comparator CMP 1  outputs the switch enabling signal S EN  as enabled; when the feedback voltage V FB  is higher than the reference voltage V REF , the comparator CMP 1  outputs the switch enabling signal S EN  as disabled. 
     The switch control circuit  120  is coupled to a source of the transistor M 1 , a gate of the transistor M 1 , and an output end of the comparator CMP 1 . The switch control circuit  120  receives switch voltage V SW  through the source of the transistor M 1 , and receives switch enabling signal S EN  through the comparator CMP 1 . The switch control circuit  120  generates switch control signal S SW  according to the switch voltage V SW  and the switch enabling signal S EN . More particularly, when the switch enabling signal S EN  indicates “enabled,” the switch control circuit  120  generates the switch control signal S SW  according to the switch voltage V SW ; when the switch enabling signal S EN  indicates “disabled,” the switch control circuit  120  does not generate the switch control signal S SW , keeping the transistor M 1  in the off state, such that the primary winding  111  cannot be charged further. 
     Because the switch voltage V SW  is rapidly increased to a very high voltage level when the primary winding  111  begins to be discharged right after being charged, circuit elements of the switch control circuit  120  must be able to withstand high voltages. The switch control circuit  120  therefore requires components resistant to high voltages, increasing cost and reducing convenience. 
     SUMMARY OF THE INVENTION 
     According to an embodiment of the present invention, a switch control circuit has a voltage sensing function. The switch control circuit is coupled to a control end of a first transistor. The first transistor comprises a first end, a second end, and the control end. The first end of the first transistor is coupled to a first end of a primary winding of a transformer, and the second end of the first transistor is coupled to a first source voltage. A second end of the primary winding of the transformer is coupled to a second source voltage. The switch control circuit comprises a voltage-clamping buffer, a set driver, a reset driver, and an R-dominant SR latch. The voltage-clamping buffer is coupled to the first end of the first transistor for receiving a switch voltage and shifting the switch voltage to generate a down-shifted switch voltage. The set driver is coupled to the voltage-clamping buffer for receiving the down-shifted switch voltage and generating a set signal according to the down-shifted switch voltage. The reset driver is coupled to the voltage-clamping buffer for receiving the down-shifted switch voltage and generating a reset signal according to the down-shifted switch voltage. The R-dominant SR latch comprises a set end coupled to the set driver for receiving the set signal, a reset end coupled to the reset driver for receiving the reset signal, an output end coupled to the control end of the first transistor for outputting a switch control signal to the control end for controlling conductance of the first transistor, and an output bar end for outputting an inverted switch control signal. The inverted switch control signal has logic level inverse the switch control signal. When the set signal is at a first logic level, the switch control signal is at the first logic level. When the reset signal is at the first logic level, the switch control signal is at a second logic level. When the set signal and the reset signal are simultaneously at the first logic level the switch control signal is at the second logic level. When the switch control signal is at the first logic level, the first transistor conducts to couple the primary winding to the first source voltage. When the switch control signal is at the second logic level, the first transistor does not conduct. 
     According to another embodiment, a flash capacitor charger has a voltage sensing function. The flash capacitor charger comprises a transformer, a diode, a first transistor, and a switch control circuit. The transformer comprises a primary winding and a secondary winding. The primary winding comprises a first end, and a second end coupled to a second source voltage. The secondary winding comprises a first end, and a second end coupled to a first source voltage. The diode is coupled to the first end of the secondary winding for outputting an output voltage. The first transistor comprises a first end coupled to the first end of the primary winding, a second end coupled to the first source voltage, and a control end for receiving a switch control signal. The switch control circuit comprises a voltage-clamping buffer, a set driver, a reset driver, and an R-dominant SR latch. The voltage-clamping buffer is coupled to the first end of the first transistor for receiving a switch voltage and shifting the switch voltage to generate a down-shifted switch voltage. The set driver is coupled to the voltage-clamping buffer for receiving the down-shifted switch voltage and generating a set signal according to the down-shifted switch voltage. The reset driver is coupled to the voltage-clamping buffer for receiving the down-shifted switch voltage and generating a reset signal according to the down-shifted switch voltage. The R-dominant SR latch comprises a set end coupled to the set driver for receiving the set signal, a reset end coupled to the reset driver for receiving the reset signal, an output end coupled to the control end of the first transistor for outputting a switch control signal to the control end for controlling conductance of the first transistor, and an output bar end for outputting an inverted switch control signal. The inverted switch control signal has logic level inverse the switch control signal. When the set signal is at a first logic level, the switch control signal is at the first logic level. When the reset signal is at the first logic level, the switch control signal is at a second logic level. When the set signal and the reset signal are simultaneously at the first logic level the switch control signal is at the second logic level. When the switch control signal is at the first logic level, the first transistor conducts to couple the primary winding to the first source voltage. When the switch control signal is at the second logic level, the first transistor does not conduct. 
     These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a diagram of a camera flash capacitor charger according to the prior art. 
         FIG. 2  is a diagram of a flash capacitor charger with a voltage sensing function according to an embodiment of the present invention. 
         FIG. 3  is a timing diagram of internal signals of the switch control circuit of the flash capacitor charger. 
     
    
    
     DETAILED DESCRIPTION 
     Please refer to  FIG. 2 , which is a diagram of a flash capacitor charger  200  with a voltage sensing function according to one embodiment. As shown in  FIG. 2 , the flash capacitor charger  200  has structure similar to the flash capacitor charger  100  of the prior art. However, the flash capacitor charger  200  comprises a switch control circuit  250  having structure different from the switch control circuit  120  of the prior art. 
     The switch control circuit  250  comprises a voltage-clamping buffer  210 , a set driver  220 , a reset driver  230 , and an R-dominant SR latch  240 . 
     Likewise, the switch control circuit  250  generates the switch control signal S SW  according to the switch voltage V SW  and the switch enabling signal S EN . More particularly, when the switch enabling signal S EN  indicates “enabled,” the switch control circuit  250  generates the switch control signal S SW  according to the switch voltage V SW ; when the switch enable signal S EN  indicates “disabled,” the switch control circuit  250  does not generate the switch control signal S SW , keeping the transistor M 1  in the off state, such that the primary winding  111  cannot be charged. Further, the switch control signal S SW  is a periodic signal. 
     The voltage-clamping buffer  210  comprises an NMOS transistor M 2  and a resistor R 1 . The transistor M 2  may be a high-voltage-withstanding component. 
     A gate of the transistor M 2  is coupled to the voltage source V DD  for receiving the voltage V DD ; a drain of the transistor M 2  is coupled to the drain of the transistor M 1  (primary winding  111 ) for receiving the switch voltage V SW ; a source of the transistor M 2  is coupled to the resistor R 1  for outputting the down-shifted switch voltage V SWK . 
     Because the gate of the transistor M 2  receives the voltage V DD , the voltage level of the down-shifted switch voltage V SWK  has an upper limit clamped lower than the source voltage V DD  by the gate-source voltage V GS2  of the transistor M 2 , i.e. V DD -V GS2 . Thus, the down-shifted switch voltage V SWK  is not increased to the relatively high voltage level of the switch voltage V SW . Thus, components performing later operations according to the voltage level of the down-shifted switch voltage V SWK  do not need to be high-voltage-withstanding components, which saves cost. 
     The set driver  220  comprises a waveform-shaping circuit  221  and a level-detecting circuit  222 . 
     The level-detecting circuit  222  may be utilized for detecting voltage level of the down-shifted switch voltage V SWK . When the down-shifted switch voltage V SWK  is lower than a predetermined voltage V P , the level-detecting circuit  222  generates a logic high voltage (logic “1” voltage) acting as a set signal S S . On the other hand, when the down-shifted switch voltage V SWK  is higher than the predetermined voltage V P , the level-detecting circuit  222  generates a logic low voltage (logic “0” voltage) acting as the set signal S S . The logic high voltage may be any voltage level above a logic high threshold, and the logic low voltage may be any voltage level below a logic low threshold. In one embodiment, for example, in a range of 0V-5V, the logic high threshold may be 4V, and the logic low threshold may be 1 V. 
     The level-detecting circuit  222  comprises a resistor R 2  and two NMOS transistors M 3  and M 4 . The predetermined voltage V P  may be equal to the threshold voltage V TH  of NMOS transistors M 3  and M 4 , namely V P =V TH . In addition, the level-detecting circuit  222  may also be realized with one resistor and one NMOS transistor. In this embodiment, the NMOS transistors M 3  and M 4  are in cascode for the purpose of reducing bulk effect and effectively increasing the equivalent threshold voltage V TH . 
     When the down-shifted switch voltage V SWK  is lower than the predetermined voltage V P , both of the transistors M 3  and M 4  are not turned on. Thus, the level-detecting circuit  222  utilizes the voltage V DD  to output the set signal S S  with the logic high voltage through the resistor R 2 . 
     On the other hand, when the down-shifted switch voltage V SWK  is higher than the predetermined voltage V P , the transistors M 3  and M 4  are turned on. Thus, the level-detecting circuit  222  utilizes the turned-on transistors M 3  and M 4  to couple to the voltage V SS  for outputting the set signal S S  with the logic low voltage. 
     However, the purpose of installing NMOS transistors in the level-detecting circuit  222  is only for utilizing the threshold voltage of the installed NMOS transistors to determine the voltage level of the down-shifted switch voltage V SWK . Although two NMOS transistors are utilized in the level-detecting circuit  222  in the present embodiment, in another embodiment one NMOS transistor may be utilized. In another embodiment, a plurality of NMOS transistors may be utilized in the level-detecting circuit  222 . In other words, number of NMOS transistors utilized in the level-detecting circuit  222  is not limited. 
     The waveform-shaping circuit  221  may be utilized for shaping the set signal S S  outputted from the level-detecting circuit  222  to have a waveform approaching a square waveform, so as to prevent the set signal S S  from having a level between the logic high threshold and the logic low threshold, i.e. a level that is neither logic high nor logic low. In other words, the waveform-shaping circuit  221  shaping the set signal S S  into a square waveform helps to prevent operation errors in the SR latch  240  based on the set signal S S . As shown in  FIG. 2 , the waveform-shaping circuit  221  may be realized as two inverters connected in series. 
     In one embodiment, the R-dominant SR latch  240  comprises a set end S, a reset end R, an output end Q, and an output bar end Qb. 
     The set end S of the R-dominant SR latch  240  is coupled to the set driver  220  for receiving the set signal S S ; the reset end R of the R-dominant SR latch  240  is coupled to the reset driver  230  for receiving the reset signal S R ; the output end Q of the R-dominant SR latch  240  is coupled to the gate of the transistor M 1  for generating the switch control signal S SW  according to the set signal S S  and the reset signal S R  to control on/off state of the transistor M 1 ; the output bar end Qb of the R-dominant SR latch  240  outputs an inverted switch control signal S SWI , which has logic level inverse of the switch control signal S SW . 
     When the R-dominant SR latch  240  receives the set signal S S  with logic level “1,” the R-dominant SR latch  240  outputs the switch control signal S SW  with the logic high voltage (logic “1”) from the output end Q, and inverted switch control signal S SWI  with the logic low voltage (logic “0”) from the output bar end Qb. 
     When the R-dominant SR latch  240  receives the reset signal S R  with logic level “0,” the R-dominant SR latch  240  outputs the switch control signal S SW  with the logic low voltage (logic “0”) from the output end Q, and the inverted switch control signal S SWI  with the logic high voltage (logic “1”) from the output bar end Qb. 
     When the R-dominant SR latch  240  receives both the set signal S S  and the reset signal S R  with logic level “1,” the R-dominant SR latch  240  outputs the switch control signal S SW  with the logic low voltage (logic “0”) from the output end Q, and the inverted switch control signal S SWI  with the logic high voltage (logic “1”) from the output bar end Qb. 
     The reset driver  230  comprises a comparator CMP 2  and two switches SW 1  and SW 2 . 
     The first end  1  of the switch SW 1  is coupled to the voltage-clamping buffer  210  for receiving the down-shifted switch voltage V SWK ; the second end  2  of the switch SW 1  is coupled to the positive input end of the comparator CMP 2 ; the control end C of the switch SW 1  is coupled to the output end Q of the R-dominant SR latch  240  for receiving the switch control signal S SW . 
     When the switch control signal S SW  is at logic “1,” the first end  1  of the switch SW 1  is coupled to the second end  2  of the switch SW 1 , so that the down-shifted switch voltage V SWK  is sent to the positive input end of the comparator CMP 2 ; when the switch control signal S SW  is at logic “0,” the first end  1  of the switch SW 1  is not coupled to the second end  2  of the switch SW 1 , so that the down-shifted switch voltage V SWK  is not sent to the positive input end of the comparator CMP 2 . 
     The first end  1  of the switch SW 2  is coupled to the voltage source V SS  (ground) for receiving the voltage V SS  (low voltage level); the second end  2  of the switch SW 2  is coupled to the positive input end of the comparator CMP 2 ; the control end C of the switch SW 2  is coupled to the output bar end Qb of the R-dominant SR latch  240  for receiving the inverted switch control signal S SWI . 
     When the inverted switch control signal S SWI  is at logic “1,” the first end  1  of the switch SW 2  is coupled to the second end  2  of the switch SW 2 , so that the voltage V SS  (low voltage level) is sent to the positive input end of the comparator CMP 2 ; when the inverted switch control signal S SWI  is at logic “0,” the first end  1  of the switch SW 2  is not coupled to the second end  2  of the switch SW 2 , so that the voltage V SS  is not sent to the positive input end of the comparator CMP 2 . 
     The negative input end of the comparator CMP 2  is utilized for receiving an upper threshold voltage V LIMIT . The comparator CMP 2  compares voltage amplitudes on the positive input end and the negative input end, and outputs a comparison signal as the reset signal S R . More specifically, when voltage on the positive input end of the comparator CMP 2  is greater than the upper threshold voltage V LIMIT , the comparator CMP 2  outputs the reset signal S R  with logic “1.” 
     In summary, operation of the reset driver  230  may be understood as follows. When the switch control signal S SW  is at logic “1,” the transistor M 1  is turned on, and the voltage source V DD  begins to charge the primary winding  111  to generate the current I with steadily increasing amplitude. Because the transistor M 1  acts as an equivalent resistor R M1 , having a limit of drain-source resistance R DS     —     ON  of the transistor M 1 , when the transistor M 1  is turned on, the switch voltage V SW  increases with the increasing current I, as V SW =R M1 ×1. In other words, the down-shifted switch voltage V SWK  also increases with the increasing current I. 
     On the other hand, because the primary winding  111  of the transformer  110  has a current amplitude limit, if the current I increases without limit, the transformer  110  may be damaged. Thus, the reset driver  230  limits the current I. 
     Based on the above, amplitude of the current I is directly proportional to the down-shifted switch voltage V SWK . Thus, when the transistor M 1  is turned on (the switch control signal S SW  is at logic “1”), the first end  1  of the switch SW 1  is coupled to the second end  2  of the switch SW 1  for sending the down-shifted switch voltage V SWK  to the positive input end of the comparator CMP 2 . At this time, the comparator CMP 2  compares the down-shifted switch voltage V SWK  with the upper limit voltage V LIMIT . When the down-shifted switch voltage V SWK  is greater than the upper limit voltage V LIMIT , the current I flowing through the primary winding  111  has reached the upper limit. Thus, the transistor M 1  is turned off, and the comparator CMP 2  outputs the reset signal S R  at logic “1” to the R-dominant SR latch  240  for resetting the SR latch  240 , namely resetting the switch control signal S SW  from logic “1” to logic “0.” By turning off the transistor M 1  at an appropriate time, the primary winding  111  is prevented from being damaged by the over-magnitude current I. 
     On the other hand, when the transistor M 1  is turned off (the inverted switch control signal S SWI  is at logic “1”), the first end  1  of the switch SW 2  is coupled to the second end  2  of the switch SW 2  for sending the voltage V SS  to the positive input end of the comparator CMP 2 . Because the voltage V SS  is lower than the upper limit voltage V LIMIT , at this time, the reset signal S R  outputted from the comparator CMP 2  is held at logic “0,” and does not reset the R-dominant SR latch  240 . 
     Please refer to  FIG. 3 , which is a timing diagram of internal signals of the switch control circuit  250  of the flash capacitor charger  200  having a voltage sensing function according to an embodiment of the present invention. As shown in  FIG. 3 , the voltage V 1  represents the upper limit voltage V LIMIT , the voltage V 2  represents the threshold voltage V TH  of the transistors M 3  and M 4 , and the voltage V 3  represents (V DD -V GS2 ). As can be seen from  FIG. 3 , when the down-shifted switch voltage V SWK  reaches the upper limit voltage V LIMIT , the reset signal S R  goes to logic “1” to reset the R-dominant SR latch  240 , such that the switch control signal S SW  transitions to logic “0” to turn off the transistor M 1 , thereby increasing the switch voltage V SW  abruptly. Likewise, the down-shifted switch voltage V SWK  also increases abruptly. However, due to the voltage-clamping buffer  210 , the down-shifted switch voltage V SWK  only increases to (V DD -V GS2 ), and is not increased to the amplitude as high as the switch voltage V SW . After the transistor M 1  is turned off, the primary winding  111  begins discharging, and the current I drops steadily. In other words, the switch voltage V SW  and the down-shifted switch voltage V SWK  also drop steadily. When the down-shifted switch voltage V SWK  drops lower than the voltage V 2 , the transistors M 3  and M 4  of the level-detecting circuit  222  are turned off, the set signal S S  is increased to logic “1” and sent to the R-dominant SR latch  240  to transition the switch control signal S SW  from logic “0” to logic “1,” so as to turn on the transistor M 1  again, and reinitiate charging of the primary winding  111 . This cycle allows the output voltage V OUT  to increase steadily to the required voltage level, e.g. 300V. When the output voltage V OUT  reaches the required voltage level, the comparator CMP 1  outputs the switch enabling signal S EN  as “disabled” to the switch control circuit  250  to disable operation of the switch control circuit  250 . 
     The switch control circuit and the flash capacitor charger described in the above embodiments effectively sense voltage to prevent damage to the winding of the transformer, and effectively remove the need for components resistant to high voltages, increasing convenience to the user. 
     Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention.