Patent Publication Number: US-2022216395-A1

Title: Semiconductor device

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The invention relates to a semiconductor device, and more particularly to a magnetoresistive random access memory (MRAM). 
     2. Description of the Prior Art 
     Magnetoresistance (MR) effect has been known as a kind of effect caused by altering the resistance of a material through variation of outside magnetic field. The physical definition of such effect is defined as a variation in resistance obtained by dividing a difference in resistance under no magnetic interference by the original resistance. Currently, MR effect has been successfully utilized in production of hard disks thereby having important commercial values. Moreover, the characterization of utilizing GMR materials to generate different resistance under different magnetized states could also be used to fabricate MRAM devices, which typically has the advantage of keeping stored data even when the device is not connected to an electrical source. 
     The aforementioned MR effect has also been used in magnetic field sensor areas including but not limited to for example electronic compass components used in global positioning system (GPS) of cellular phones for providing information regarding moving location to users. Currently, various magnetic field sensor technologies such as anisotropic magnetoresistance (AMR) sensors, GMR sensors, magnetic tunneling junction (MTJ) sensors have been widely developed in the market. Nevertheless, most of these products still pose numerous shortcomings such as high chip area, high cost, high power consumption, limited sensibility, and easily affected by temperature variation and how to come up with an improved device to resolve these issues has become an important task in this field. 
     SUMMARY OF THE INVENTION 
     According to an embodiment of the present invention, a semiconductor device includes an array region defined on a substrate, a ring of dummy pattern surrounding the array region, and a gap between the array region and the ring of dummy pattern. Preferably, the ring of dummy pattern further includes a ring of magnetic tunneling junction (MTJ) pattern surrounding the array region and a ring of metal interconnect pattern overlapping the ring of MTJ and surrounding the array region. 
     These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  illustrates a top view of a semiconductor device according to an embodiment of the present invention. 
         FIG. 2  illustrates a cross-section of the semiconductor device taken along the sectional line AA′ of  FIG. 1 . 
         FIG. 3  illustrates a cross-section of the semiconductor device taken along the sectional line BB′ of  FIG. 1 . 
     
    
    
     DETAILED DESCRIPTION 
     Referring to  FIGS. 1-3 ,  FIG. 1  illustrates a top view of a semiconductor device, or more specifically a MRAM device according to an embodiment of the present invention,  FIG. 2  illustrates a cross-section of the MRAM device taken along the sectional line AA′ of  FIG. 1 , and  FIG. 3  illustrates a cross-section of the MRAM device taken along the sectional line BB′ of  FIG. 1 . As shown in  FIGS. 1-3 , a substrate  12  made of semiconductor material is first provided, in which the semiconductor material could be selected from the group consisting of silicon (Si), germanium (Ge), Si—Ge compounds, silicon carbide (SiC), and gallium arsenide (GaAs). An array region  14  and a ring of dummy pattern  16  surrounding the array region  14  are defined on the substrate  12 , in which the array region  14  in this embodiment could also be referred to as a MRAM macro region and the array region  14  could further include a MRAM region  18  and a logic region  20 . 
     In this embodiment, the dummy pattern  16  further includes a ring of MTJ pattern  24  and a ring of metal interconnect pattern  22  overlapping the ring of MTJ pattern  24  to surround the array region  14 , the MRAM region  18  includes a plurality of MTJ patterns  24  arranged according to an array, and the MRAM device also includes a gap  26  disposed between the array region  14  and the ring of dummy pattern  16  so that the dummy pattern  16  does not contact the array region  14  directly. Specifically, the ring of MTJ pattern  24  further includes a first MTJ pattern  128  and a second MTJ pattern  130  extending along a first direction such as X-direction and a third MTJ pattern  132  and a fourth MTJ pattern  134  extending along a second direction such as Y-direction. Preferably, the first MTJ pattern  128  overlaps the third MTJ pattern  132  at a first corner  36 , the first MTJ pattern  128  overlaps the fourth MTJ pattern  134  at a second corner  38 , the second MTJ pattern  130  overlaps the third MTJ pattern  132  at a third corner  40 , and the second MTJ pattern  130  overlaps the fourth MTJ pattern  134  at a fourth corner  42 . 
     Similarly, the ring of metal interconnect pattern  22  directly above the ring of MTJ pattern  24  further includes a first metal interconnect pattern  28  and a second metal interconnect pattern  30  extending along a first direction such as X-direction and a third metal interconnect pattern  32  and a fourth metal interconnect pattern  34  extending along a second direction such as Y-direction. Preferably, the first metal interconnect pattern  28  overlaps the third metal interconnect pattern  32  at the first corner  36 , the first metal interconnect pattern  28  overlaps the fourth metal interconnect pattern  34  at the second corner  38 , the second metal interconnect pattern  30  overlaps the third metal interconnect pattern  32  at the third corner  40 , and the second metal interconnect pattern  30  overlaps the fourth metal interconnect pattern  34  at the fourth corner  42 . 
     In other words, the first MTJ pattern  128 , the second MTJ pattern  130 , the third MTJ pattern  132 , and the fourth MTJ pattern  134  together constitute a ring or ring-shaped pattern such as a square-shaped rectangular shaped ring surrounding the array region  14 , and the first metal interconnect pattern  28 , the second metal interconnect pattern  30 , the third metal interconnect pattern  32 , and the fourth metal interconnect pattern  34  also constitute a square-shaped or rectangular-shaped ring surrounding the array region  14  while the ring formed by the first MTJ pattern  128 , the second MTJ pattern  130 , the third MTJ pattern  132 , and the fourth MTJ pattern  134  preferably overlaps the ring formed by the first metal interconnect pattern  28 , the second metal interconnect pattern  30 , the third metal interconnect pattern  32 , and the fourth metal interconnect pattern  34  entirely. It should be noted that even though only a single ring of dummy pattern  16  made of a ring of MTJ pattern  24  and a ring of metal interconnect pattern  22  is disposed around the array region  14 , according to other embodiment of the present invention it would also be desirable to adjust the number of dummy pattern  16  by forming more than one ring such as two rings or even three rings of dummy pattern  16  surrounding the array region  14 , which are all within the scope of the present invention. Moreover, even though the MTJ pattern  24  of the dummy pattern  16  forms a ring surrounding the array region  14  according to a top view perspective, the MTJ patterns  24  within the MRAM region  18  are disposed according to an array as each of the MTJ patterns  24  include a square or rectangular shape if viewed from the top. 
     As shown in the cross-section views in  FIGS. 2-3 , active devices such as metal-oxide semiconductor (MOS) transistors, passive devices, conductive layers, and interlayer dielectric (ILD) layer  52  could also be formed on top of the substrate  12 . More specifically, planar MOS transistors or non-planar (such as FinFETs) MOS transistors could be formed on the substrate  12 , in which the MOS transistors could include transistor elements such as gate structures (for example metal gates), source/drain regions, spacers, epitaxial layers, and contact etch stop layer (CESL). The ILD layer  52  could be formed on the substrate  12  to cover the MOS transistors, and a plurality of contact plugs (not shown) could be formed in the ILD layer  52  to electrically connect to the gate structure and/or source/drain region of MOS transistors. Since the fabrication of planar or non-planar transistors and ILD layer is well known to those skilled in the art, the details of which are not explained herein for the sake of brevity. 
     The semiconductor device also includes metal interconnect structures  54 ,  56  disposed on the ILD layer  52 , MTJ patterns  24  disposed on metal interconnect structure  56  in the dummy pattern  16  and the MRAM region  18 , metal interconnection  60  disposed on the metal interconnect structure  54  on the logic region  20 , spacers  62  disposed on sidewalls of each of the MTJ patterns  24 , inter-metal dielectric (IMD) layer  64  disposed around the spacers  62 , and another metal interconnect structure  66  disposed on the MTJ patterns  24  and the metal interconnection  60 . 
     In this embodiment, the metal interconnect structure  54  includes a stop layer  68 , an IMD layer  70 , and a plurality of metal interconnections  72  embedded within the stop layer  68  and the IMD layer  70 , the metal interconnect structure  56  includes a stop layer  74 , an IMD layer  76 , and a plurality of metal interconnections  78  embedded in the stop layer  74  and the IMD layer  76 , and the metal interconnect structure  66  includes a stop layer  80 , an IMD layer  82 , and metal interconnections  84  embedded in the stop layer  80  and the IMD layer  82 . 
     In this embodiment, each of the metal interconnections  72 ,  78 ,  84  within the metal interconnect structures  54 ,  56 ,  66  and the metal interconnection  60  could be fabricated according to a single damascene or dual damascene process. For instance, each of the metal interconnections  72  preferably include a trench conductor, each of the metal interconnections  78  preferably include a via conductor, each of the metal interconnections  84  preferably include a via conductor, and the metal interconnection  60  preferably includes a trench conductor. 
     Moreover, each of the metal interconnections  72 ,  78 ,  84  could further include a barrier layer  86  and a metal layer  88 , in which the barrier layer  86  could be selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN) and the metal layer  88  could be selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), titanium aluminide (TiAl), and cobalt tungsten phosphide (CoWP). Since single damascene process and dual damascene process are well known to those skilled in the art, the details of which are not explained herein for the sake of brevity. In this embodiment, the metal layers  88  directly under the MTJ patterns  24  are preferably made of tungsten while the rest of the metal layers  88  are preferably made of copper, the IMD layers  70 ,  76 ,  82  are preferably made of silicon oxide, and the stop layers  68 ,  74 ,  80  are preferably made of nitrogen doped carbide (NDC), silicon nitride, silicon carbon nitride (SiCN), or combination thereof. 
     In this embodiment, the formation of the MTJ patterns  24  could be accomplished by sequentially forming a bottom electrode  90 , a MTJ stack, a top electrode  98 , and a patterned mask (not shown) on the metal interconnect structure  56 , in which the MTJ stack preferably includes a pinned layer  92 , a barrier layer  94 , and a free layer  96  on the bottom electrode  90 . In this embodiment, the bottom electrode  90  and the top electrode  98  are preferably made of conductive material including but not limited to for example Ta, Pt, Cu, Au, Al, or combination thereof. The pinned layer  92  could be made of ferromagnetic material including but not limited to for example iron, cobalt, nickel, or alloys thereof such as cobalt-iron-boron (CoFeB) or cobalt-iron (CoFe). Moreover, the pinned layer  92  could also be made of antiferromagnetic (AFM) material including but not limited to for example ferromanganese (FeMn), platinum manganese (PtMn), iridium manganese (IrMn), nickel oxide (NiO), or combination thereof, in which the pinned layer  92  is formed to fix or limit the direction of magnetic moment of adjacent layers. The barrier layer  94  could be made of insulating material including but not limited to for example oxides such as aluminum oxide (AlO x ) or magnesium oxide (MgO). The free layer  96  could be made of ferromagnetic material including but not limited to for example iron, cobalt, nickel, or alloys thereof such as cobalt-iron-boron (CoFeB), in which the magnetized direction of the free layer  96  could be altered freely depending on the influence of outside magnetic field. 
     Next, a pattern transfer process or a photo-etching process is conducted by using a patterned mask such as patterned resist to remove part of the top electrode  98 , part of the MTJ stack, and part of the bottom electrode  90  to form the entire ring of MTJ pattern  24  in the dummy pattern  16 , in which the MTJ pattern  24  preferably directly contacting and electrically connecting the metal interconnections  78  underneath. 
     It should be noted that even though the bottom electrode  90  or the bottom of MTJ pattern  24  are electrically connecting or directly contacting the metal interconnections  78  of the metal interconnect structure  56 , only the MTJ pattern  24  on the MRAM region  18  would connect to the MOS transistors disposed on the surface of the substrate  12  through the metal interconnection  78  underneath. The MTJ pattern  24  of the dummy pattern  16  on the other hand is a dummy MTJ pattern while the metal interconnections  78 ,  84  directly under or on top of the MTJ pattern  24  of the dummy pattern  16  are also dummy metal interconnections not electrically connecting any other device or conductive wires. Accordingly, the MTJ pattern  24  and the metal interconnections  78 ,  84  in the dummy pattern  16  would together form a dummy barrier around the array region  14 . 
     It should be further noted that the metal interconnections  84  directly above the MTJ pattern  24  as shown in  FIGS. 2-3  are in fact the ring of metal interconnect pattern  22  around the array region  14  shown in  FIG. 1 . Since the MTJ pattern  24  and the metal interconnect pattern  84  are both disposed around the array region  14  like a ring, the bottom surface of the single metal interconnect pattern  84  as shown in the cross-section view of  FIG. 3  taken along the sectional line BB′ of  FIG. 1  would electrically or directly contacting the single top electrode  98  on top of the single MTJ pattern  24 . 
     Overall, the present invention preferably forms at least a ring of dummy pattern made of a ring of MTJ pattern and a ring of multi-layered metal interconnection pattern surrounding an array region or logic region of a semiconductor device for shielding electromagnetic waves. According to a preferred embodiment of the present invention, the dummy pattern surrounding the array region or logic region could be used as a barrier for blocking electromagnetic waves, in which the dummy pattern includes a ring of MTJ pattern disposed around the array region and a ring of metal interconnect pattern disposed on top of the MTJ pattern. Preferably, the MTJ pattern and the metal interconnect pattern are both disposed in the manner of a ring or ring-like pattern in a top view perspective instead of a plurality of rectangular patterns arranged in an array as typically found in conventional art. 
     Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.