Patent Publication Number: US-6989698-B2

Title: Charge pump circuit for compensating mismatch of output currents

Description:
TECHNICAL FIELD 
   The present invention relates to a charge pump circuit of a phase-locked loop, more particularly, a correcting circuit for improving speed of switching and a correcting mismatch between source current and sink current which are generated on switching time in charge pump circuit, and a charge pump circuit using thereof. 
   BACKGROUND OF THE INVENTION 
     FIG. 1  shows a block diagram of a conventional phase-locked loop. 
   As shown in  FIG. 1 , the phase-locked loop has a phase detector  101 , a charge pump  103 , a loop filter  105 , and a voltage controlled oscillator  107 . The voltage controlled oscillator  107  controls frequency of an outputted oscillation signal CLK, according to an inputted voltage signal. The phase detector  101  outputs UP and DOWN signals when the frequency of the oscillation signal CLK outputted from the voltage controlled oscillator  107  is not matched with that of a reference oscillation signal REFCLK. More specifically, the phase detector outputs the UP signal if the frequency of the oscillation signal CLK is less than that of the reference oscillation signal REFCLK, and outputs the DN signal if the frequency of the oscillation signal CLK is greater than that of the reference oscillation signal REFCLK. The charge pump  203  outputs positive current pulse in case that an applied voltage pulse is the UP signal, and outputs negative current pulse in case that the applied voltage pulse is the DN signal. Generally, the loop filter  105  comprises a large capacitor, and controls an output voltage V CLT  by adding charge to the capasitor or removing charge from the capacitor in accordance with the inputted current pulse. The voltage controlled oscillator  107  controls the frequency of the oscillation signal CLK by the voltage Vclt outputted from the loop filter  105 . That is, the frequency of the oscillation signal CLK is increased when the output voltage Vclt of the loop filter  105  is raised, and the frequency of the oscillation signal CLK is decreased when the output voltage V CLT  of the loop filter  105  is gone down. 
   Accordingly, when the frequency of the oscillation signal CLK which is outputted from the voltage controlled oscillator  107  is less than the reference oscillation signal REFCLK, the phase detector  101  generates the UP signal, and the charge pump  103  charges the capacitor of the loop filter  105  by outputting the positive current pulse. Moreover, the voltage Vclt applied to the voltage controlled oscillator  107  is raised, and the frequency of the oscillation signal CLK is increased. On the other hands, when the frequency of the oscillation signal CLK which is outputted from the voltage controlled oscillator  107  is greater than the reference oscillation signal REFCLK, the phase detector  101  generates the DN signal, and the voltage V CLT  applied to the voltage controlled oscillator  107  is gone down, and the frequency of the oscillation signal CLK is decreased. 
     FIG. 2  shows a circuit diagram of conventional charge pump used in the phase locked loop shown in  FIG. 1 . 
   As shown in  FIG. 2 , the conventional charge pump  103  comprises the first and second PMOS transistors MP 21 , MP 22 , and the first and second NMOS transistors MN 21 , MN 22 . The first PMOS and NMOS transistors MP 21 , MN 21  are implemented by common-source transistors, and activated or inactivated by voltage pulses UPB, DN which are applied to gates thereof, respectively. The second PMOS and NMOS transistors MP 22 , MN 22  are implemented by common-gate transistors, and constant bias voltages BIASP, BIASN are applied to gates, respectively. 
   Below, operation and problems of the conventional charge pump  103  are illustrated, with referring to  FIG. 2 . 
   When the UP pulse of the phase detector  101  is pulsed high, the UPB pulse of the charge pump  103  is pulsed low. Accordingly, the first PMOS transistor MP 21  is activated. Tthe source of the second PMOS transistor MP 22  is charged, and source voltage is raised until the gate-to-source voltage exceeds the threshold voltage. Accordingly, a source current I source  flows from voltage source to the first and second PMOS transistors MP 21 , MP 22 , and the capacitor C 21  connected to the output terminal V LFO  is charged. 
   When the DN pulses is pulses high, the first NMOS transistor MN 21  is activated. The source of the second NMOS transistor MN 21  is discharged, and source voltage is gone down until the gate-to-source voltage exceeds the threshold voltage. Accordingly, a sink current I sink  flows from the output terminal a charge pump circuit to the ground through the first and second NMOS transistors MN 21 , MN 22 , and the capacitor C 21  is discharged. 
   In the conventional charge pump circuit  103 , amounts of the source and sink currents I source , I sink  flowing to the output terminal V LFO  is controlled by the bias voltages BIASP, BIASN which is applied to the gates of the second PMOS and NMOS transistors MP 22 , MN 22 . Generally, the bias voltages BIASP, BIASN is setted to predetermined voltages so that amounts of the source and the sink currents I source , I sink  are same. 
   However, a parasitic capacitance generated between gate and source of the second NMOS transistor MN 22  drops quickly gate voltage of the second NMOS transistor MN 22  which controls the sink current I sink  when the DN signal is applied. Accordingly, the sink current I sink  flowing the output terminal V LFO  is not desired current. Although, voltage drop by parasitic capacitance is corrected by the biasing unit  2100 , in the conventional charge pump circuit, correction time is needed. Moreover, parasitic capacitance generated from the source of the second NMOS transistor MN 22  delays voltage drop of the source terminal to the ground and prevents a desired sink current Isink from flowing to the output terminal V LFO . 
   On the other hand, the gate voltage of the second PMOS transistor MP 22  is raised quickly by parasitic capacitance generated between gate and source of the second PMOS transistor MP 22  when the UP signal is applied. Moreover, parasitic capacitance generated from the source of the second PMOS transistor MP 22  delays voltage rise of source terminal to value of the voltage source, and prevents a desired source current Isource from flowing to the output terminal V LFO . 
   Accordingly, the conventional charge pump circuit has problems that switching speed is low, and current mismatch generated between source and sink currents during current switching owing to parasitic capacitance. This current mismatch generates spurious tone, and deteriorates the phase noise figure of the phase-locked loop. 
   In order to resolve above problems, in conventional charge pump circuit  103 , there are the method that increases impedance by being long the length of the first and second NMOS transistor MN 21 , MN 22  used to CMOS charge pump, and the method that has greater impedance than general circuit by the second NMOS and PMOS transistor MN 22 , MP 22  consisted of cascode. But, in case being long the length of element, swiching speed is slow, and in case that element is consisted of cascode, operating range of a charge pump is small. Moreover, because a output impedance can not substantially become in infinity, they have a limit in that source and sink currents is harmonized. 
   SUMMARY OF THE INVENTION 
   An object of the present invention is to provide a charge pump circuit for improving switching speed and compensating a mismatch between a source and sink currents flowing to output terminal charge. 
   Another object of the present invention is to provide a control circuit for controlling a compensating charge of a compensating circuit, in charge pump circuit. 
   Still another object of the present invention is to provide a charge pump circuit for compensating mismatch between a source and sink currents flowing to output terminal. 
   The other object of the present invention is to provide a chage pump circuit for getting to be indentical the source and sink currents without deteriorating the switching speed and operating range. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  shows a block diagram of a conventional phase-looked loop. 
       FIG. 2  shows a conventional charge pump circuit diagram in the phase-looked loop shown in  FIG. 1 . 
       FIG. 3  shows a charge pump circuit diagram according to an embodiment of the present invention. 
       FIG. 4  shows a charge pump circuit diagram according to another embodiment of the present invention. 
       FIG. 5  shows a charge pump circuit diagram according to another embodiment of the present invention. 
       FIG. 6  shows a circuit diagram of a control circuit for contolling a quantity of compensating charge of the first and second compensating units according to an embodiment of the present invention in the charge pump circuit shown in  FIG. 3 . 
       FIG. 5  shows a circuit diagram of the variable gain amplifier shown in  FIG. 2  according to another embodiment of the present invention. 
       FIG. 6  shows a circuit diagram of the variable gain amplifier shown in  FIG. 2  according to another embodiment of the present invention. 
       FIG. 7  shows a charge pump circuit diagram according to another embodiment of the present invention. 
       FIG. 8  shows a charge pump circuit diagram shown in  FIG. 7  used practical emements according to an embodiment of the present invention. 
       FIG. 9  shows a charge pump circuit diagram shown in  FIG. 7  used practical emements according to another embodiment of the present invention. 
   

   DETAILED DESCRIPTION 
   Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings. 
   The First Embodiment 
     FIG. 3  shows a charge pump circuit diagram according to an embodiment of the present invention. 
   As shown in  FIG. 3 , the charge pump circuit diagram according to an embodiment of the present invention comprises a first and second switching elements MN 31 , MP 31 , a charging element MP 32 , a discharging element MN 32 , a biasing unit  3100 , and a first and second compensating units  3300 , 3500 . 
   The first and second compensating units  3300 ,  3500  compensates the effect according to parasitic capacitances generated between gates-sources of the discharging and charging elements MN 32 , MP 32 . In this way, the charge pump circuit shown in  FIG. 3  compensates a switching speed of the charge pump circuit and a mismatch of output terminal V LFO  current. 
   The first and second switching elements MN 31 , MP 31  are activated by down and up signals DN, UPB applied to a respective gate. The charging and discharging elements MP 32 , Mn 32  control the current which flows to the output terminal V LFO  of the charge pump circuit by bias voltage applied to a respective gate. 
   The biasing unit  3100  comprises a first and second terminal  301 ,  302 , and applies a respective bias voltage to the gate of the discharging and charging elements MN 32 , MP 32 . 
   The first and second compensating units  3300 , 3500  comprise input terminals  305 , 311 , output terminals  307 ,  313 , and control terminals  309 ,  315 , and discharge and charge to the output terminals  307 ,  313  when down and up signals DN, UPB are applied to the input terminals  305 ,  311 , respectively. More, The first and second compensating units  3300 ,  3500  control the quantity of charge of the output terminals  307 ,  313  by a first and second control signals VccCAL, VssCAL applied to the control terminals  309 ,  315 , respectively. 
   Hereinafter, the connection of component will be described with reference to the attached  FIG. 3 . 
   The down and up signals DN, UPB are applied to the first and second switching elements MN 31 , MP 31 , respectively, and the drains are connected to the sources of the discharging and charging elements MN 32 , MP 32 , respectively, and the sources are connected to ground and power source, respectively. The gates the discharging and charging elements MN 32 , MP 32  are connected to the first and second terminals  301 ,  303 , respectively, the drains are connected to each other and form an output terminal V LFO  of the charge pump circuit. 
   The down and up signals DN, UPB are applied to the first and second compensating units  3300 ,  3500 , respectively, and the output terminals  307 ,  313  are connected to the gates of the discharging and charging elements MN 32 , MP 32 , respectively. 
   The composition of the charge pump circuit will be described in detail according to an embodiment of the present invention. 
   The biasing unit  3100  comprises a first, second, third, and fourth NMOS transistors BN 31 , BN 32 , BN 33 , BN 34 , and a first and second PMOS transistors BP 31 , BP 32 , and a bias current Ibias. The composition and operation of the biasing unit  3100  is apparent for those skilled in the art, and because the essence of the present invention is not confined to specific implementations of the biasing unit  3100 , the description of the biasing unit  3100  is omitted. 
   The first and second compensating units  3300 ,  3500  comprise buffers BF 31 , BF 32  and capasitors C 31 , C 32 , respectively. The input terminals of the buffers BF 31 , BF 32  form the input terminals  305 ,  311  of the first and second compensating units  3300 , 3500 , respectively, and the output terminals are connected to one terminal of the capacitors C 31 , C 32 , respectively. The other terminal of of the capacitors C 31 , C 32  MN 32  form the output terminals  307 ,  313  of the first and second compensating units  3300 , 3500 , respectively. A high level control terminal of the buffer BF 31  forms the control terminal  309  of the first compensating unit  3300 , and a low level control terminal of the buffer BF 32  forms the control terminal  315  of the second compensating unit  3500 . 
   Hereinafter, the operation of the charge pump circuit according to an embodiment of the present invention will be described with reference to  FIG. 3 . 
   The first switching element MN 31  is activated when the down signal DN is applied to the charge pump circuit, and the capacitor C 31  connected to the output terminal V LFO  of the charge pump circuit is discharged. That is, a sink current Isink is passed to ground through the discharging element MN 32  and the first switching element MN 31  from the output terminal V LFO , the capacitor C 31  is discharged. In a similar, the second switching element MN 32  is activated when the up signal UPB is applied to the charge pump circuit, and the capacitor C 31  connected to the output terminal V LFO  of the charge pump circuit is charged. That is, a source current Isource is passed to the output terminal V LFO  through the charging element MP 32  and the second switching element MP 31  from the power source, the capacitor C 31  is charged. 
   In this case, as above description, the gate voltage of the discharging and charging elements MN 32 , MP 32  is raised and dropped instantaneously by the parasitic capacitances generated between gates-sources of discharging and charging elements MN 32 , MP 32 . That is, when the up signal UPB is applied to the charge pump circuit and the source terminal voltage of the charging elements MP 32  raises to a source voltage, the gate voltage of the charging elements MP 32  is raised instantaneously by the parasitic capacitance generated between gate-source of the charging element MP 32 . On the contrary, when the down signal DN is applied to the charge pump circuit and the source terminal voltage of the discharging elements MN 32  drop to ground volage, the gate voltage of the discharging elements MN 32  is dropped instantaneously by the parasitic capacitance generated between gate-source of the discharging element MP 32 . Therefore, the rapid switching operation of the charge pump circuit is interrupted, and the mismatch of between the source current Isource and the sink current Isink is occurred. 
   When the down signal DN is applied to the charge pump circuit, the buffer BF 31  of the first compensating unit  3300  regulates the high level voltage of the down signal DN by the first control signal VccCAL applied to the control terminal  309 , and applies the regulated voltage to the capacitor C 31 . When a positive voltage is applied to one terminal of the capacitor C 31 , the capacitor C 31  is discharged, and the other terminal voltage of the capacitor C 31 , namely, the gate voltage of the discharging element MN 32  is raised. 
   The total charges of the parasitic capacitance and the capacitor C 31  after appling of the down signal, are equal to the total charges of the parasitic capacitance and the capacitor C 31  at the initial time by the law of conservation of charge. Therefore, if the first control signal VccCAL is regulated and the quantity of discharge is controlled, the voltage drop according to the parasitic capacitance and the voltage raise according to the capacitor C 31  of the first compensating is offsetted each other. Consequently, the gate voltage of the discharging element MN 32  is maintained uniformly. 
   When the up signal UPB is applied to the charge pump circuit, the buffer BF 32  of the second compensating unit  3300  regulates the low level voltage of the up signal UPB by the second control signal VssCAL applied to the control terminal  315 , and applies the regulated voltage to the capacitor C 32 . When a negative voltage is applied to one terminal of the capacitor C 32 , the capacitor C 32  is charged, and the other terminal voltage of the capacitor C 32 , namely, the gate voltage of the charging element MP 32  is dropped. 
   The total charges of the parasitic capacitance and the capacitor C 32  after appling of the up signal, are equal to the total charges of the parasitic capacitance and the capacitor C 32  at the initial time by the law of conservation of charge. Therefore, if the second control signal VssCAL is regulated and the quantity of charge is controlled, the voltage raise according to the parasitic capacitance and the voltage drop according to the capacitor C 32  of the second compensating is offsetted each other. Consequently, the gate voltage of the charging element MP 32  is maintained uniformly. 
   As described above, since the charge pump cuircuit according to an embodiment of the present invention have the first and second compensating units  3300 ,  3500 , the bias voltage applied to the gates of the discharging and charging elements MN 32 , MP 32  may be prevented the change in response to switching operation. Accordingly, the switching speed of the charge pump circuit is improved, and as the desired source and sink currents Isource, Isink passes to the output terminal V LFO , the mismatch between currents according to the up and down signals UPB, DN may be compensated. 
     FIG. 4  shows a charge pump circuit according to the other embodiment of the present invention. 
   As shown in  FIG. 4 , the charge pump circuit comprises a first and second switching elements MN 41 , MP 41 , a charging element MP 42 , a discharging element MN 42 , a biasing unit  4100 , and a first and second compensating units  4300 ,  4500 . 
   The first and second compensating units  4300 ,  4500  compensates the effect according to parasitic capacitances generated between gates-sources of the discharging and charging elements MN 42 , MP 42 . In this way, the charge pump circuit shown in  FIG. 4  compensates a switching speed of the charge pump circuit and a mismatch of output terminal V LFO  current. 
   Below, a composition and operation of the charge pump circuit according to the other embodiment of the present invention is illustrated with referring to  FIG. 4 . But, the first and second switching elements MN 41 , MP 41 , the charging element MP 42 , the discharging element MN 42 , and the biasing unit  4100  are the same as the composition and operation of the charge pump circuit according to an embodiment of the present invention shown in  FIG. 3 , accordingly, the illustration about the composition and the operation above is omitted. 
   The first and second compensating units  4300 ,  4500  comprise input terminals  405 ,  409  and output terminals  407 ,  411 , and charge or discharge to the output terminals  407 ,  411  by the down and up signals DN, UPB applied to the input terminals  405 ,  409 , respectively. The down and up signals DN, UPB are applied to the input terminals  405 ,  409  of the first and second compensating units  4300 ,  4500 , respectively, and the output terminals  407 ,  411  are connected to sources of the discharging and charging elements MN 42 , MP 42 , respectively. 
   The first and second compensating units  4300 ,  4500  comprise invertors IN 41 , IN 42  and capacitors C 41 , C 42 , respectively. Input terminals of invertors IN 41 , IN 42  form the input terminals  405 ,  409  of the first and second compensating units  4300 ,  4500 , respectively, and output terminals are connected to one terminal of the capacitor C 41 , C 42 , respectively. The other terminal of the capacitor C 41 , C 42  form the output terminals  407 ,  411  of the first and second compensating units  4300 ,  4500 , respectively. 
   Hereinafter, the operation of the charge pump circuit according to the other embodiments of the present invention will be described in detail. 
   When the down signal DN is applied to the charge pump circuit, the first switching element MN 41  is activated, a source terminal of the discharging element MN 42  is dropped to grounding voltage. However, the voltage drop is delayed by the parasitic capacitance existed in the source terminal of the discharging element MN 42 . 
   When the down signal DN of a high level is applied to the input terminal  405 , the invertor IN 41  of the first compensating unit  4300  reverses the down signal DN, and applies a low level signal to the capacitor C 41 . When a negative voltage is applied to one terminal of the capacitor C 41 , the capacitor C 41  inflows forcibly the charge from the parasitic capacitance of the source terminal of the discharging element MN 42 . Therefore, the source terminal of the discharging element MN 42  is grounded instantaneously, and the desired a sink current Isink passes to a drain of the discharging element MN 42 . 
   When the up signal UPB is applied to the charge pump circuit, the second switching element MP 41  is activated, a source terminal of the charging element MP 42  is raised to source voltage. However, the voltage raise is delayed by the parasitic capacitance existed in the source terminal of the charging element MP 42 . 
   When the up signal DN of a low level is applied to the input terminal  409 , the invertor IN 42  of the second compensating unit  4500  reverses the up signal UPB, and applies a high level signal to the capacitor C 42 . When a positive voltage is applied to one terminal of the capacitor C 42 , the capacitor C 42  emits forcibly the charge to the parasitic capacitance of the source terminal of the charging element MP 42 . Therefore, the source terminal of the discharging element MN 42  is raised to source voltage instantaneously, and the desired a source current Isource passes to a source of the charging element MP 42 . 
   As described above, since the charge pump cuircuit according to the other embodiment of the present invention have the first and second compensating units  4300 ,  4500 , the switching speed of the charge pump circuit can be improved, and the mismatch between source current and sink current flowing to the output terminal V LFO  can be compensated, by removing the influence according to the parasitic capacitance existed in the source terminal of the discharging and charging elements MN 42 , MP 42 . 
     FIG. 5  shows a charge pump circuit according to another embodiment of the present invention. 
   As shown in  FIG. 5 , it is different from the embodiments shown  FIG. 3  and  FIG. 4  in that the charge pump circuit comprises the first and second compensating  3300 ,  3500  shown in  FIG. 3  and the first and second compensating  4300 ,  4500  shown in  FIG. 4 . 
   As the charge pump circuit according to another embodiment of the present invention has four compensating circuits, the switching speed of the charge pump circuit can be more improved, and the mismatch between currents flowing to the output terminal V LFO  can be more compensated, by removing the influence according to the parasitic capacitance existed in the source terminals and the gate-source terminals of the discharging and charging elements MN 42 , MP 42  at the same time. 
   In the charge pump circuit shown  FIG. 3  and  FIG. 5 , the first and second compensating units  3500 ,  3700  emit and flow the charge to the discharging and charging elements MN 32 , MP 32 , and remove the influence according to the parasitic capacitance exsited in the gate-source terminals of the discharging and charging elements MN 32 , MP 32 . However, in case that the compensating charge emitted or flowed from the first and second compensating units  3500 ,  3700  is not equal to the theoretically necessary compensating charge in order to maintain the constant gate voltage of the discharging and charging elements MN 32 , MP 32 , the mismatch between currents of the output terminal V LFO  exists as usual. In the charge pump circuit shown  FIG. 3  and  FIG. 5 , the voltage drop and raise by the parasitic capacitance varies according to the output voltage V LFO , and the compensating charge varies according to the source voltage, temperature, etc. Therefore, it is necessary that controlls the compensating charge. 
   But, the first and second compensating units  4300 ,  4500  of the charge pump circuit shown in  FIG. 4  are the circuits so that the source terminals of the discharging and charging elements MN 42 , MP 42  turn into the grounding and source voltages rapidly. Consequencely, the benefit by controlling the compensating charge is not much. 
     FIG. 6  shows a control circuit diagram according to an embodiment of the present invention in order to control the compensating charge of the first and second compensating units  3300 ,  3500 , in the charge pump circuit shown in  FIG. 3 . 
   As shown  FIG. 6 , the control circuit uses the equivalent circuit of the charge pump circuit according to an embodiment of the present invention shown in  FIG. 3 . 
   As shown  FIG. 6 , the control circuit comprises a first and second switching elements MN 61 , MP 61 , charging and discharging elements MP 62 , MN 62 , a biasing unit  6100 , a first and second compensating units  6300 ,  6500 , a first and second switch means SW 1 , SW 2 , and a first and second controlling units  6700 ,  6900 . Also, it is preferable that a buffer (not shown) is connected to the output terminal V LFO  of the control circuit. 
   Hereinafter, the relation of connection between compositions is illustrated with referring to  FIG. 6   
   But, the first and second switching elements MN 61 , MP 61 , the charging element MP 62 , the discharging element MN 62 , the biasing unit  6100 , and the first and second compensating units  6300 ,  6500  are the same as the composition and operation of the charge pump circuit according to an embodiment of the present invention shown in  FIG. 3 , accordingly, the illustration about the composition and the operation above is omitted. 
   The first switch means SW 1  is connected to between a first terminal  601  of the biasing unit  6100  and the gate of the discharging element MN 62 , the second switch means SW 2  is connected to between a second terminal  603  of the biasing unit  6100  and the gate of the charging element MP 62 . 
   The first controlling unit  6700  comprises a first and second input terminals  617 ,  619 , and an output terminal  621 , outputs the value which is integrated the difference between voltages applied to the first and second input terminals  617 ,  619 . The second controlling unit  6900  comprises a first and second input terminals  623 ,  625 , and an output terminal  627 , outputs the value which is integrated the difference between voltages applied to the first and second input terminals  623 ,  625 . 
   The first input terminal  617  of the first controlling unit  6700  is connected to the first terminal of the biasing unit  6100 , the second input terminal  619  is connected to the gate of the discharging element MN 62 . Also, a output signal VccCAL of the first controlling unit  6700  is applied to control terminals  309 ,  609  of the first compensating units  3300 ,  6300  comprised in the charge pump circuit and the charge compensating control circuit. 
   Hereinafter, the inside composition of the first and second controlling units is illustrated in detail. 
   The first controlling unit  6700  comprises a comparator CMP 1 , a switch means SW 3 , an integrator INT 1 . +input terminal of the comparator CMP 1  forms the first input terminal  617  of the first controlling unit  6700 , −input terminal of the comparator CMP 1  forms the second input terminal  619  of the first controlling unit  6700 . The output terminal of comparator CMP 1  is connected to one terminal of the switch means SW 3 , and the other terminal of the switch means SW 3  is connected to the input terminal of the integrator INT 1 , and the output terminal of the integrator INT 1  is connected to the output terminal  621  of the first controlling unit  6700 . 
   The second controlling unit  6900  comprises a comparator CMP 2 , a switch means SW 4 , an integrator INT 2 . +input terminal of the comparator CMP 2  forms the first input terminal  623  of the first controlling unit  6900 , −input terminal of the comparator CMP 2  forms the second input terminal  625  of the second controlling unit  6900 . The output terminal of comparator CMP 2  is connected to one terminal of the switch means SW 4 , and the other terminal of the switch means SW 4  is connected to the input terminal of the integrator INT 2 , and the output terminal of the integrator INT 2  is connected to the output terminal  627  of the first controlling unit  6900 . 
   Hereinafter, the operation of the control circuit according to an embodiment of the present invention shown in  FIG. 6  is illustrated in detail. 
   In the control circuit, the operation of a sink terminal is illustrated first of all. In the initial state, the switch first means SW 1  is shorted and the target bias voltage is applied to a gate of the discharging element MN 62 . In the second place, the first switch means is opened, and a first signal PHDR is applied to the charge pump circuit. As described above, if the first signal PHDR is applied, the gate voltage of the discharging element MN 62  is dropped instantaneously by the parasitic capacitance between gate-source of the discharging element MN 62 , and the capacitor C 61  of the first compensating unit  6300  emits the charge in order to compensate that. However, in case that the charge quantity emitted from the first compensating unit  6300  is not equal to the theoretically necessary compensating charge, consequently, the gate voltage of the discharging element MN 62  is not in keeping with the voltage outputted to the first terminal  601  of the biasing unit  6100 . 
   The comparator CMP 1  of the first controlling unit  6700  compares the voltage of the first terminal  601  of the biasing unit  6100  applied to +input terminal and the voltage of gate of the discharging element MN 62  applied to +input terminal, and the difference of both voltages is outputted. The integrator INT 1  integrates the output valve outputted from the comparator CMP 1 , and outputs integrated value to the first control signal VccCAL. The first control signal VccCAL is applied to the control terminal  309 ,  609  of the first compensating units  3300 ,  6300  of the control circuit and the charge pump circuit, and regulates a high level voltage Vcc of buffer BF 31 , BF 61 . Therefore, the compensating charge quantity emitted from the capacitor C 31 , C 61  are regulated by controlling the voltage applied to the capacitor C 31 , C 61 . That is, in case that the compensating charge is not enough and the gate voltage of the discharging element MN 62  is lower than a target voltage, the emitted compensating charge is increased by raising the voltage of the first control signal VccCAL. The other way, in case that the compensating charge is ever so much and the gate voltage of the discharging element MN 62  is higher than a target voltage, the emitted compensating charge is decreased by dropping the voltage of the first control signal VccCAL. 
   In the control circuit, the operation of a source terminal is as well as the sink terminal. In the initial state, the second switch means SW 2  is shorted and the target voltage is applied to a gate of the charging element MP 62 . In the second place, the second switch means is opened, and a second signal PHDRB is applied to the charge pump circuit. As described above, if the second signal PHDRB is applied, the gate voltage of the charging element MP 62  is raised instantaneously by the parasitic capacitance between gate-source of the charging element MP 62 , and the capacitor C 62  of the second compensating unit  6500  flows the charge in order to compensate that. However, in case that the charge quantity flowed into the second compensating unit  6500  is not equal to the theoretically necessary compensating charge, consequently, the gate voltage of the charging element MP 62  is not in keeping with the voltage outputted to the second terminal  603  of the biasing unit  6100 . 
   The comparator CMP 2  of the second controlling unit  6900  compares the voltage of the second terminal  603  of the biasing unit  6100  applied to +input terminal and the voltage of gate of the charging element MP 62  applied to +input terminal, and the difference of both voltages is outputted. The integrator INT 2  integrates the output valve outputted from the comparator CMP 2 , and outputs integrated value to the second control signal VssCAL. The second control signal VssCAL is applied to the control terminal  315 ,  615  of the second compensating units  3500 ,  6500  of the control circuit and the charge pump circuit, and regulates a low level voltage Vss of buffer BF 32 , BF 62 . Therefore, the compensating charge quantity emitted from the capacitor C 32 , C 62  are regulated by controlling the voltage applied to the capacitor C 32 , C 62 . That is, in case that the compensating charge is not enough and the gate voltage of the charging element MP 62  is higher than a target voltage, the flowed compensating charge is increased by dropping the voltage of the second control signal VssCAL. The other way, in case that the compensating charge is ever so much and the gate voltage of the charging element MP 62  is lower than a target voltage, the flowed compensating charge is decreased by raising the voltage of the second control signal VssCAL. 
   The control circuit shown in  FIG. 6  is implemented by using the equivalent circuit of the control circuit shown in  FIG. 3 . Moreover, the charge pump circuit can be implemented by using the equivalent circuit of the control circuit shown in  FIG. 5  or by using the equivalent circuit of the changed control circuit of that. The idea of the present invention is not confined to the specific control circuit, and this is apparent for those skilled in the art. 
   The Second Embodiment 
     FIG. 7  shows a charge pump circuit diagram according to an embodiment of the present invention summarily. 
   As shown  FIG. 7 , the charge pump circuit comprises a charge pumping unit  7100 , a current mirror unit  7300 , a control unit  7500 , and a biasing unit  7700 . 
   The charge pumping unit  7100  has a first and second input terminals  701 ,  703 , a bias terminal  705 , and an output terminal  707 , charges and discharges a capacitor C 71  connected to the output terminal  707  by up and down signals applied to the first and second input terminals  701 ,  703 , respectively. Moreover, the current quantity flowed to the output terminal  707  of the charge pumping unit  7100  control by the voltage applied to the bias terminal  705 . The current mirror unit  7300  has a bias terminal  709  and an output terminal  711 , takes the current flowed to the output terminal  707 . In addition to, the current mirror unit  7300  controls the voltage of the output terminal  707  by the voltage applied to the bias terminal  709 . The control unit  7500  has a first and second input terminals  713 ,  715  and an output terminal  717 , and controls the quantity of a control current Icomp flowed to the output terminal  717  by the differential voltage between the first and second input terminals  713 ,  715 . The biasing unit comprises a control terminal  719  and an output terminal  721 , controls the output voltage by the control current Icomp applied to the control terminal  719 . 
   Hereinafter, the relation of connection between compositions is illustrated with referring to  FIG. 7   
   The up and down signals UPB, DN are applied to the first and second input terminals  701 ,  703  of the charge pumping unit  7100 , the bias terminal  705  is connected to the output terminal  721  of the biasing unit  7700 . The output terminal  707  is connected to the capacitor C 71  and is more connected to the first input terminal  713  of the controlling unit  7500 . 
   The bias terminal  709  of the current mirror unit  7300  is connected to the output terminal  721  of the biasing unit  7700 , the output terminal  711  is connected to the second input terminal  715  of the controlling unit  7500 . 
   The output terminal  717  of the controlling unit  7500  is connected to the control terminal  719  of the biasing unit  7700 . 
     FIG. 8  shows the charge pump circuit diagram which is used actual elements according to an embodiment of the present invention in  FIG. 7 . 
   The charge pump circuit is implemented by MOSFET transistor amplifying element. The amplifying element has a gate, a source, and a drain. The MOSFET transistor has a characteristic which determines the quantity and direction of current (flows from a drain to a source or that inversely) according to the level and polarity of voltage applied to the gate. This sort of amplifying element is Bipolar Junction Transistor (BJT), Junction Field Effect Transistor (JFET), Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET), Metal-Semiconductor Field Effect Transistor (MESFET). 
   Hereinafter, the charge pump circuit will be illustrated in priority MOSFET. However, the idea of the present invention can be applied not only MOSFET but also all sort of complementary elements. Therefore, the conception and range of the present invention is not confined to MOSFET. In addition to, hereinafter, the charge pump circuit will be illustrated in priority N type MOSFET, but P type MOSFET can be applied to the circuit as apparent for those skilled in the art. 
   As shown in  FIG. 8 , the charge pump circuit compensates the mismatch between currents of the output terminal  807  of the charge pumping unit  8100  by compensating the mismatch between an output voltage V LFO  of the charge pumping unit  8100  and an output voltage V LFO ′ of the current mirror unit  8300  at the source terminal. 
   The charge pumping  8100  comprises a first and second PMOS transistor MP 81 , MP 82 , and a first and second NMOS transistor MN 81 , MN 82 . The gates of the first PMOS and NMOS transistors MP 81 , MN 81  form a first and second input terminals  801 ,  803  of the charge pumping unit  8100 , respectively, the drains of the first PMOS and NMOS transistors MP 81 , MN 81  are connected to the sources of the second PMOS and NMOS transistors MP 82 , MN 82 , respectively. The sources of the first PMOS and NMOS transistors MP 81 , MN 81  are connected to power source and ground, respectively. A gate of the second PMOS transistor MP 82  forms the bias terminal  805  of the charge pumping unit  8100 , and a drain of the second PMOS transistor MP 82  is connected to a gate of the second NMOS transistor MN 82  and forms the output terminal  807  of the charge pumping unit  8100 . The gate of the second NMOS transistor MN 82  is applied to the predetermined constant N type bias voltage BIASN so that a sink current is identical to a source current flowing to the second PMOS transistor MP 82 . 
   The current mirror unit  8300  comprises a first and second PMOS transistors CP 81 , CP 82 , and a first and second NMOS transistors CN 81 , CN 82 , and a capacitor C 82 . The gates of the first PMOS and NMOS transistors CP 81 , CN 81  are connected to ground and power source, respectively, and the drains of the first PMOS and NMOS transistors CP 81 , CN 81  are connected to the sources of the second PMOS and NMOS transistors CP 82 , CN 82 , respectively, and the sources of the first PMOS and NMOS transistors CP 81 , CN 81  are connected to power source and ground, respectively. A gate of the second PMOS transistor CP 82  forms the bias terminal  809  of the current mirror unit  8300 , and a drain of the second PMOS transistor CP 82  is connected to a drain of the second NMOS transistor CN 82  and forms the output terminal  811  of the current mirror unit  8300 . The gate of the second NMOS transistor CN 82  is applied to the predetermined constant N type bias voltage BIASN, and the capacitor C 82  is connected to between the connecting point of the second PMOS and NMOS transistors CP 82 , CN 82  and the ground. The current mirror unit  8300  can be implemented by current mirror circuit the so-called, the idea of the present invention is not confined to specific implementations of the current mirror unit  8300 , as apparent for those skilled in the art. 
   The control unit  8500  comprises a comparator CMP 81  and a PMOS transistor CTR 81 . ±input terminals of the comparator CMP 81  form the first and second input terminals  813 ,  815  of the control unit  8500 , respectively, and an output terminal of the comparator CMP 81  is connected to a gate of the PMOS transistor CTR 81 . A source of the PMOS transistor CTR 81  is connected to power source, and a drain of the PMOS transistor CTR 81  forms the output terminal of the control unit  8500 . 
   The biasing unit  8700  comprises a first and second PMOS transistors BP 81 , BP 82 , and a first and second NMOS transistors BN 81 , BN 82 . The gates of the first PMOS and NMOS transistors BP 81 , BN 81  are connected to ground and power source, respectively, and the drains of the first PMOS and NMOS transistors BP 81 , BN 81  are connected to the sources of the second PMOS and NMOS transistors BP 82 , BN 82 , respectively, and the sources of the first PMOS and NMOS transistors BP 81 , BN 81  are connected to power source and ground, respectively. A gate of the second PMOS transistor BP 82  forms the output terminal  821  of the biasing unit  8700 , and a drain of the second PMOS transistor BP 82  is connected to a drain of the second NMOS transistor BN 82  and forms the control terminal  819  of the biasing unit  8700 . The gate and drain of the second PMOS transistor BP 82  is connected to each other, and the constant N type bias voltage BIASN is applied to the gate of the second NMOS transistor BN 82 . 
   Hereinafter, the operation of the charge pump circuit according to an embodiment of the present invention will be illustrated with referring to  FIG. 8 . 
   The charge pump circuit has the current mirror unit  8300  which takes a source current Isource and a sink current Isink of the charge pumping unit  8100 . The charge pump circuit detects the difference in voltage between the output terminal voltage V LFO  of the charge pumping unit  8100  and the output terminal voltage V LFO ′ of the current mirror unit  8300 , and then feeds the dectected voltage by negative feedback circuit. And the charge pump circuit controls the difference in voltage between the output terminal  807  of the charge pumping unit  8100  and the output terminal  811  of the current mirror unit  8300  by varying the current flowed to the control terminal  819  of the biasing unit  8700  in accordance with the negative feedback signal. 
   The charge pumping unit  8100  charges and discharges the capacitor C 81  connected to the output terminal  807  by the up and down signals UPB, DN applied to the first and second input terminals, respectively. That is, when the up signal UPB is applied, the first PMOS transistor MP 81  is activated and the source current Isource flows from power source to the output terminal  807  via the first and second PMOS transistors MP 81 , MP 82 . Consequently, the capacitor C 81  connected to the output terminal  807  of the charge pumping unit  8100  is charged. When the down signal DN is applied, the first NMOS transistor MN 81  is activated and the sink current Isink flows from the output terminal  807  to the ground via the first and second NMOS transistors MN 81 , MN 82 . Consequently, the capacitor C 81  connected to the output terminal  807  of the charge pumping unit  8100  is discharged. In addition to, the quantity of the source current Isource and the sink current Isink are determined by the bias voltage applied to the gate of the second PMOS and NMOS transistors MP 82 , MN 82 , and the bias voltage is setted up so that the source current Isource is identical to the sink current Isink at the initial state. However, as above described, there is the problem that the source current Isource is not identical to the sink current Isink on account of the non-ideal output impedance of output drive element. 
   The current mirror unit  8300  takes the current flowed to the output terminal  807  of the charge pumping unit  8100 , and controls the voltage V LFO ′ by the voltage applied to the bias terminal  809 . That is, the gate of the second PMOS transistor CP 82  of the current mirror unit  8300  is connected to the output terminal  821  of the biasing unit  8700 , and is applied to the voltage that is substantially identical to the bias voltage applied to the gate of the second PMOS transistor MP 82  of the charge pumping unit  8100 , and the gate of the second NMOS transistor MN 82  of the current mirror unit  8300  is applied to the voltage that is substantially identical to the bias voltage BIASN applied to the gate of the second NMOS transistor MN 82  of the charge pumping unit  8100 . Therefore, in case that the output voltage of the charge pumping unit  8100  is substantially identical to the output voltage V LFO ′ of the current mirror unit  8300 , when the up signal UPB is applied, the first current Isource′ which is identical to the source current Isource flowing to the second PMOS transistor CP 82  of the charge pumping unit  8100  flows to the second PMOS transistor CP 82  of the current mirror unit  8300 , when the down signal DN is applied, the second current Isink′ which is identical to the sink current Isink flowing to the second NMOS transistor CN 82  of the charge pumping unit  8100  flows to the second NMOS transistor CN 82  of the current mirror unit  8300 . Moreover, if the bias voltage applied to the bias terminal  809  of the current mirror unit  8300  is increased, the first current Isource′ flowing to the second PMOS transistor CP 82  is decreased, and the output voltage V LFO ′ is decreased, on the contrary, if the bias voltage applied to the bias terminal  809  of the current mirror unit  8300  is decreased, and the output voltage V LFO ′ is increased. 
   The control unit  8500  compares the voltage applied to the first and second input terminals  813 ,  815 , and controls the current Icomp flowing to the output terminal  817  by above the differential voltage. The comparator CMP 81  of the control unit  8500  compares the output voltage V LFO  of the charge pumping unit  8100  applied to +input terminal and the output voltage V LFO  of the current mirror unit  8300  applied to −input terminal, and then controls the output voltage Vc. That is, in case that the output voltage V LFO  of the charge pumping unit  8100  is lower than the output voltage V LFO ′ of the current mirror unit  8300 , the voltage Vc is decreased, in case the contrary, the voltage Vc is increased. The PMOS transistor CRT 81  of the control unit  8500  controls the current Icomp flowing to the output terminal  817  of the control unit  8500  by the voltage Vc applied to the gate. That is, when the control voltage Vc applied to the gate of the PMOS transistor CRT 81  is decreased, the current Icomp is increased, when the control voltage Vc is increased, the current Icomp is decreased. 
   The biasing unit  8700  provides the gates of the second PMOS transistors MP 82 , CP 82  of the charge pumping unit  8100  and the current mirror unit  8300  with the bias voltage, and controls the voltage of the output terminal  821  in proportion to the current control signal Icomp flowed to the control terminal  819 . That is, when the current Icomp is decreased, the current Icomp′ flowing to the first and second PMOS transistors BP 81 , BP 82  is increased. On the contrary, when the current Icomp is increased, the the current Icomp′ flowing to the first and second PMOS transistors BP 81 , BP 82  is decreased, and the output voltage of the biasing unit  8700  is increased. 
   In the charge pump circuit according to an embodiment of the present invention, the source current Isource and sink current Isink of the charge pumping unit  8100  is not identical according to the output voltage V LFO , the mismatch of this sort gives rise to the mismatch between the first current Isource′ and second current Isink′ of the current mirror unit  8300 . Therefore, the mismatch between the output voltage V LFO  of the charge pumping unit  8100  and the output voltage V LFO ′ of the current mirror unit  8300  is occurred. The control unit  8500  detects the mismatch of this sort, and compensates the mismatch between the output voltage V LFO  of the charge pumping unit  8100  and the output voltage V LFO ′ of the current mirror unit  8300  by regulating the control current Icomp flowed to the control terminal  819  of the biasing unit  8700 . 
   Hereinafter, the operation of the charge pump circuit according to an embodiment of the present invention is illustrated in detail. 
   When the output voltage V LFO  of the charge pumping unit  8100  is lower than the output voltage V LFO ′ of the current mirror unit  8300 , the current Icomp is increased by the control unit  8500 . When the current Icomp is increased, the output voltage is increased by the biasing unit  8700 . Therefore, the bias voltage applied to the bias terminal of the current mirror unit  8300  is increased, and the output voltage V LFO ′ of the current mirror unit  8300  is decreased. At this time, the bias voltage applied to the bias terminal  805  of the charge pumping unit  8100  is increased, but the source terminal of the charge pumping unit  8100  is operated only in case that the up signal UPB is applied and the capacitor C 71  of large capacity is connected to the output terminal  807 , and so the output voltage V LFO  is not substantially affected. After all, the output voltage V LFO ′ of the current mirror unit  8300  is substantially identical to the output voltage V LFO  of the charge pumping unit  8100 , and the mismatch between the source current Isource and the sink current Isink is compensated. 
   On the contrary, when the output voltage V LFO  of the charge pumping unit  8100  is higher than the output voltage V LFO ′ of the current mirror unit  8300 , the current Icomp is decreased by the control unit  8500 . When the current Icomp is decreased, the output voltage is decreased by the biasing unit  8700 . Therefore, the bias voltage applied to the bias terminal of the current mirror unit  8300  is decreased, and the output voltage V LFO ′ of the current mirror unit  8300  is increased. After all, the output voltage V LFO ′ of the current mirror unit  8300  is substantially identical to the output voltage V LFO  of the charge pumping unit  8100 , and the mismatch between the source current Isource and the sink current Isink is compensated. 
   In the charge pump circuit according to an embodiment of the present invention, when the mismatch between the source current Isource and the sink current Isink is occurred, the difference between the output voltage V LFO  of the charge pumping unit  8100  and the output voltage V LFO  of the current mirror unit  8300  is occurred. Because the difference of this sort is detected and compensated by the control unit  8500 , the mismatch between the source current Isource and the sink current Isink is compensated. 
     FIG. 9  shows the charge pump circuit diagram which is used actual elements according to an embodiment of the present invention in  FIG. 7 . 
   As shown  FIG. 9 , the charge pump circuit compensates the mismatch of an output terminal  907  current of a charge pumping unit  9100  by compensating the mismatch between the output voltage V LFO  of the charge pumping unit  9100  and the output voltage V LFO ′ of the current mirror unit  9300 . 
   Hereinafter, the composition of the charge pump circuit according to the other embodiment of the present invention will be illustrated with referring to  FIG. 9 . But, the parts that are identical with the charge pump circuit according to an embodiment of the present invention are emitted, and the points of difference are illustrated. 
   In a charge pumping unit  9100 , the gates of a first PMOS and NMOS transistors MP 91 , MN 91  form a first and second input terminals  901 ,  903 , and the gates of a second NMOS transistor MN 92  forms a bias terminal of the charge pumping unit  9100 . Gates of a second PMOS transistor is applied to the predetermined constant P type bias voltage BIASP so that a source current Isource is identical to a sink current Isink flowing to the second NMOS transistor MN 92 . Drains of a second PMOS and NMOS transistors MP 92 , MN 92  are connected to each other, and form the output terminal  907 . 
   In a current mirror unit  9300 , the constant P type bias voltage BIASP is applied to a gate of a second PMOS transistor CP 92 , and a gate of a second NMOS transistor CN 92  forms a bias terminal  909 , and drains of a second PMOS and NMOS transistors CP 92 , CN 92  are connected to each other, and form the output terminal  911 . A capacitor C 92  is connected to between the connection point of the drains of the second PMOS and NMOS transistors C 092 , CN 92  and power source. 
   A control unit  9500  comprises a comparator CMP 91  and a NMOS transistor CTR 91 . +input terminal of the comparator CMP 91  forms a first input terminal of the control unit  9500 , −input terminal of the comparator CMP 91  forms a second input terminal of the control unit  9500 , An output terminal of the comparator CMP 91  is connected to a gate of the NMOS transistor CTR 91 . A drain of the NMOS transistor CTR 91  forms a output terminal  917  of the control unit  9500 , a drain of the NMOS transistor CTR 91  is grounded. 
   In a biasing unit  9700 , the constant P type bias voltage BIASP is applied to a gate of a second PMOS transistor BP 92 , and a gate of a second NMOS transistor BN 92  forms an output terminal  921 . A drain and gate of the second NMOS transistor BN 92  are connected to each other, and drains of the second PMOS and NMOS transistors BP 92 , BN 92  are connected to each other and form the control terminal  919 . 
   Hereinafter, the operation of the charge pump circuit according to the other embodiment of the present invention will be illustrated in detail with referring to  FIG. 9 . 
   When the output voltage V LFO  of the charge pumping unit  9100  is lower than the output voltage V LFO ′ of the current mirror unit  9300 , the control voltage Vc is decreased as well as the difference of both voltages by the comparator CMP 91  of the control unit  9500 . When the control voltage Vc is decreased, and the output current Icomp of the control unit  9500  is decreased by the NMOS transistor CTR 91 , and a current Icomp′ flowing to the second NMOS transistor BN 92  of the biasing unit  9700  is increased. And then, when the current Icomp′ is increased, the gate voltage of the second NMOS transistor BN 92  is increased. As a result of this, the bias voltage applied to the bias terminal  909  of the current mirror  9300  is increased. Therefore, the second current Isink′ of the current mirror  9300  is increased, and the output voltage V LFO ′ is decreased. Finally, the output voltage V LFO ′ of the current mirror unit  9300  get to be substantially identical to the output voltage V LFO  of the charge pumping unit  9100 . 
   When the output voltage V LFO  of the charge pumping unit  9100  is higher than the output voltage V LFO ′ of the current mirror unit  9300 , on the same principle as above, the bias voltage applied to the bias terminal  909  of the current mirror unit  9300  is decreased. Finally, the output voltage V LFO ′ of the current mirror unit  9300  get to be substantially identical to the output voltage V LFO  of the charge pumping unit  9100 . 
   INDUSTRIAL APPLICABILITY 
   According to a first embodiment of the present invention, the switching speed of a charge pump circuit can be improved and a mismatch between currents of an output terminals can be compensated, by adding a first and second compensating circuits and removing a deterioration owing to a parasitic capacitance. 
   Moreover, a compensating charge of the first and second compensating circuits can be exactly controlled by adding the first and second compensating circuits. 
   According to a second embodiment of the present invention, a mismatch between currents of the output terminals can be compensated by adding a current mirror circuit and a control circuit, and feeding an output voltage of the charge pump circuit in negative feedback. 
   Moreover, a source and sink currents get to be identical without deteriorating a switching speed and operating range.