Patent Publication Number: US-7224210-B2

Title: Voltage reference generator circuit subtracting CTAT current from PTAT current

Description:
CROSS-REFERENCE TO RELATED APPLICATION(S) 
   BACKGROUND 
   1. Field of the Invention 
   The present invention relates to generating a reference voltage in integrated circuits, and more particularly to reference voltage circuits for low-power applications. 
   2. Description of the Related Art 
   A bangap reference circuit has improved temperature stability and is less dependent on power supply voltage than other known voltage reference circuits. Bandgap reference circuits typically generate a reference voltage approximately equal to the bandgap voltage of silicon extrapolated to zero degrees Kelvin, i.e., V G0 =1.205V. Typical voltage reference circuits include a current mirror coupled to the power supply and the voltage reference node to provide a current proportional to the absolute temperature to the voltage reference node. 
   Integrated circuits having 3V power supplies can easily meet the demands of operating devices included in a cascoded current mirror and generate the reference voltage without compromising stability of the reference voltage. For example, a voltage reference generator with a power supply of 3V provides a reference voltage of 1.2V. The V DS  of a MOSFET included in the current mirror has a magnitude of 3V−1.2V=1.8V, which is sufficient to operate the device under typical conditions with an acceptable power supply rejection ratio (PSRR) (i.e., the ability of the voltage reference generator to reject noise on the power supply). However, as the power supply voltage drops, e.g., for low-power applications, available voltage headroom required to operate the devices included in the current mirror is reduced, the PSRR becomes more critical, and the voltage reference generator is less likely to provide a sufficiently stable reference voltage with respect to variations on the power supply. 
   Accordingly, improved techniques for generating stable reference voltages for low-power applications are desired. 
   SUMMARY 
   A voltage reference generator generates a stable reference voltage that is less than the bandgap voltage of silicon for power supply voltages less than 2V, yet provides sufficient voltage headroom to operate a current mirror. In one embodiment, the voltage reference generator has a power supply rejection ratio of at least 60 dB and has a noise performance comparable to traditional bandgap circuits. These advantages are achieved by subtracting a current proportional to a complement of an absolute temperature from a current proportional to the absolute temperature to generate a voltage having a positive temperature coefficient, which is then added to a voltage that is a complement of the absolute temperature to achieve a voltage that has a low temperature coefficient. 
   In some embodiments of the present invention, an integrated circuit includes a first circuit and a second circuit that generate first and second currents, respectively. The first current is proportional to the absolute temperature. The second current is proportional to a complement of the absolute temperature. The integrated circuit further includes a node at which the second current is subtracted from the first current to generate a third current. The third current is proportional to an absolute temperature. The integrated circuit includes a third circuit that compensates for a temperature coefficient of the third current with a first voltage proportional to a complement of the absolute temperature. A reference voltage at the node is based at least in part on the third current and the first voltage. The temperature coefficient of the reference voltage is low. 
   In some embodiments of the present invention, a method for generating a reference voltage on a node of a circuit includes subtracting a current proportional to a complement of absolute temperature from a first current proportional to absolute temperature at a reference node. The subtracting generates a second current proportional to absolute temperature. The second current has a temperature coefficient more positive than the temperature coefficient of the first current. The method includes generating a first voltage proportional to absolute temperature across a resistor using the second current. The method further includes combining a second voltage proportional to a complement of absolute temperature with the first voltage to provide, at the reference node, a voltage having a low temperature coefficient. 
   In some embodiments of the present invention, a method of manufacturing an integrated circuit product includes forming a first circuit that generates a first current. The first current is proportional to an absolute temperature. The method includes forming a second circuit that generates a second current. The second current is proportional to a complement of the absolute temperature. The method includes forming a node at which the second current is subtracted from the first current to generate a third current. The third current is proportional to an absolute temperature. The method further includes forming a third circuit that compensates for a temperature coefficient of the third current with a first voltage proportional to a complement of the absolute temperature. A temperature coefficient of a reference voltage at the node is low. The reference voltage is based at least in part on the third current and the first voltage. 
   In some embodiments of the present invention, a voltage reference generator includes a resistor coupled to receive a first current. The first current is formed by subtracting a current proportional to a complement of an absolute temperature from a current proportional to the absolute temperature at a reference node, thereby generating a voltage proportional to absolute temperature across the resistor. The voltage reference generator includes a bipolar transistor coupled to the resistor and provides a voltage proportional to a complement of the absolute temperature to be combined with the voltage proportional to absolute temperature. The combination provides a reference voltage at the reference node. The reference voltage has a low temperature coefficient. 
   In some embodiments of the present invention, a method includes generating a first and second currents proportional to absolute temperature. The first current has a first temperature coefficient and the second current has a second temperature coefficient. The second temperature coefficient is greater than the first temperature coefficient. The method includes generating a reference voltage based on the first and second currents. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention may be better understood, and its numerous objects, features, and advantages made apparent to those skilled in the art by referencing the accompanying drawings. 
       FIG. 1  illustrates a voltage reference generator circuit. 
       FIG. 2  illustrates a voltage reference generator circuit in accordance with some embodiments of the present invention. 
   

   The use of the same reference symbols in different drawings indicates similar or identical items. 
   DESCRIPTION OF THE PREFERRED EMBODIMENT(S) 
   A typical voltage reference circuit (e.g., voltage reference generator  100  of  FIG. 1 ) is designed to provide a temperature stable reference voltage (i.e., V REF ). In general, voltage reference circuits take advantage of two electrical characteristics to achieve the desired V REF : the V BE  of a bipolar transistor is nearly complementary to absolute temperature, e.g., V BE =(−1.5 mV/°K*T+1.22)V, and V T  is proportional to absolute temperature, i.e, V T =kT/q. 
   A voltage proportional to absolute temperature (i.e., a ‘ptat’ voltage) may be obtained by taking the difference between two V BE s biased at different current densities: 
               Δ   ⁢           ⁢     V   BE       =       V   T     ⁢           ⁢     ln   ⁡     (       J   1       J   2       )           ,         
where J 1  and J 2  are saturation currents of corresponding bipolar transistors. Accordingly, voltage reference circuit  100  includes a pair of pnp bipolar transistors (i.e., transistors  106  and  108 ) that are connected in a diode configuration (i.e., the collectors and bases of these transistors are coupled together) and coupled to ground. Transistor  108  has an emitter area that is M times larger than the area of transistor  106 . Thus, the saturation currents of transistor  108  and transistor  106  vary by a factor of M. The emitter of transistor  106  is coupled to an inverting input of operational amplifier  116 . The emitter of transistor  108  is coupled, via resistor R 1 , to the non-inverting input of operational amplifier  116 . Operational amplifier  116  maintains equivalent voltages at nodes  118  and  120 , i.e., V 118 =V 120 =V BE106 . Hence, the difference between V BE106  and V BE108  (i.e., ΔV BE106,108 ) forms across resistor R 1 . Operational amplifier  116  and transistors  102  and  104  convert this voltage difference into a current (i.e., current I 1 ) proportional to the voltage difference:
 
             I   1     =         Δ   ⁢           ⁢     V     BE106   ,   108           NR   1       =         V   T     ⁢           ⁢     ln   ⁡     (     M   N     )           NR   1               
Since the thermal voltage V T  has a positive temperature coefficient of k/q, k=1.38*10 −23 J/K and q=1.6*10 −19 C, the current proportional to the voltage difference is proportional to an absolute temperature, i.e., I 1  is a ‘ptat’ current.
 
   Transistor  114  provides a voltage nearly complementary to absolute temperature (i.e., a ‘ctat’ voltage) because the V BE  of a bipolar transistor is nearly complementary to absolute temperature. By compensating the ptat current with a ctat voltage, transistors  102 ,  104 ,  106 ,  108 ,  112 , and  114 , and resistors R 1  and R 2 , may be appropriately sized to generate a particular reference voltage output having a zero temperature coefficient: 
                   V   REF     -     V   BE114         R   2       =     PI   1       ;                   V   REF     =       V   BE114     +       PI   1     ⁢     R   2           ;                   V   REF     =       V   BE114     +         PR   2     ⁢     V   T     ⁢           ⁢     ln   ⁡     (     M   N     )           NR   1           ;                   ⅆ     V   REF         ⅆ   T       =         ⅆ     V   BE114         ⅆ   T       +           PR   2     ⁢   k   ⁢           ⁢     ln   ⁡     (     M   N     )             NR   1     ⁢   q       .             
Setting
 
                 ⅆ     V   REF         ⅆ   T       =   0     ,         
for V REF  to have a zero temperature coefficient,
 
                 PR   2     ⁢   k   ⁢           ⁢     ln   ⁡     (     M   N     )             NR   1     ⁢   q       =       -       ⅆ     V   BE114         ⅆ   T         =         1.5   ⁢           ⁢   mV       °   ⁢           ⁢   K       .             
V BE114 =V BE106 =0.74 at 300° K for an exemplary process and choosing M=8, N=¼, P/N˜4, and R 2 /R 1 ˜1.2:
 
               V   REF     =       V   BE114     +         PR   2     ⁢     V   T     ⁢           ⁢     ln   ⁡     (     M   N     )           NR   1           ;                   V   REF     =       0.74   ⁢           ⁢   V     +         1.5   ⁢           ⁢   mV       °   ⁢           ⁢   K       ⁢   T         ;         
at 300° K, V REF =0.74V+0.45V=1.19V≈1.2V.
 
V REF  is approximately equal to, V G0 =1.205V, i.e., the bandgap voltage of silicon extrapolated to zero degrees Kelvin.
 
   When the power supply is 3V, the V DS  of transistor  112  has a magnitude of 3V−1.2V=1.8V, which is sufficient to operate the device to provide a current independent of fluctuations in V DS . Thus power supply noise will have a minimal effect on I 1 . However, for an exemplary low-power application, the power supply voltage is 1.62V. Voltage reference generator  100  provides only a V DS  of 0.42V for device  112 . Transistor  112  may be operating in a linear/quasi-saturation current region and noise on the power supply will cause significant noise in PI 1 , thereby generating a noisy V REF  and degrading the accuracy of V REF . The PSRR is typically determined empirically by presenting a varying signal on the power supply and measuring variations exhibited at the V REF  node. At a 1.62V power supply, voltage reference generator  100  is unable to provide a desired 60 dB PSRR. The poor power supply rejection of voltage reference generator  100  makes voltage reference generator  100  inoperable for the purpose of providing a stable voltage reference. A desired voltage reference generator PSRR for a low-power application is at least 60 dB over process and temperature variations. In addition, noise from operational amplifier  116 , which dominates the circuit noise of voltage reference generator  100 , is amplified by a factor of √{square root over (P)} by the current mirror thus amplifying noise on V REF . 
   Referring to  FIG. 2 , voltage reference generator  200  improves the power supply rejection ratio as compared to voltage reference generator  100 , without increasing the noise performance, by subtracting a current complementary to absolute temperature from a current proportional to absolute temperature and by maintaining V DS  of corresponding current mirror transistors to operate the current mirror transistors in a saturation region. Voltage reference circuit  200  includes a pair of pnp bipolar transistors (i.e., transistors  202  and  204 ) that are coupled in a diode configuration and coupled to ground. Transistor  204  has an emitter area that is M times larger than the area of transistor  202 . Thus, transistor  204  has a current density that varies from the current density of transistor  202  by a factor of M. The emitter of transistor  202  is coupled to an inverting input of operational amplifier  212 . The emitter of transistor  204  is coupled, via resistor R 3 , to the non-inverting input of operational amplifier  212 . Operational amplifier  212  maintains equivalent voltages at nodes  208  and  210 , i.e., V 208 =V 210 =V BE202 . Hence, the difference between V BE202  and V BE204  (i.e., ΔV BE202,204 ) forms across resistor R 3 . Operational amplifier  212  and transistors  214  and  216  convert this voltage difference into a current (i.e., current I 4 ) proportional to the voltage difference: 
             I   4     =         Δ   ⁢           ⁢     V     BE202   ,   204           NR   3       =         V   T     ⁢           ⁢     ln   ⁡     (     M   N     )           NR   3               
Since the thermal voltage V T  has a positive temperature coefficient of k/q, k=1.38*10 −23 J/K and q=1.6*10 −19 C, I 4 , is a ptat current. Transistor  228  provides node  REF  with a mirrored I 4  current, amplified by B.
 
   Transistor  206  provides a ctat voltage because the V BE  of a pnp bipolar transistor is nearly complementary to absolute temperature. The emitter of transistor  206  is coupled to an inverting input of operational amplifier  222 . The resistor R 4  is coupled to the non-inverting input of operational amplifier  222 . Operational amplifier  222  maintains equivalent voltages at nodes  223  and  224 , i.e., V 223 =V 224 =V BE206 . Hence, a ctat current proportional to V BE206  flows through resistor R 4 : 
             I   5     =         V   BE206       R   4       .           
Transistors  226 ,  230 , and  232  form mirror current I 5  with a gain of A, thus, providing a ctat current AI 5  that is subtracted from BI 4  at node V REF .
 
   Transistor  234  provides a ctat voltage because the V BE  of bipolar transistor is nearly complementary to absolute temperature. By subtracting a ctat current from a ptat current and compensating for a remaining ptat current with a ctat voltage, transistors  214 ,  216 ,  202 ,  204 ,  218 ,  206 ,  220 ,  226 ,  228 ,  230 , and  234 , and resistors R 3 , R 4 , and R 5 , may be appropriately sized to generate a particular reference voltage output, V REF , having a low (e.g., substantially zero) temperature coefficient (e.g., less than 1 μV/° K over a given temperature range): 
   
     
       
         
           
             
               BI 
               4 
             
             = 
             
               
                 
                   
                     V 
                     REF 
                   
                   - 
                   
                     V 
                     BE234 
                   
                 
                 
                   R 
                   5 
                 
               
               + 
               
                 
                   AV 
                   BE206 
                 
                 
                   R 
                   4 
                 
               
             
           
           ; 
         
       
     
     
       
         
           
             
               V 
               REF 
             
             = 
             
               
                 
                   BI 
                   4 
                 
                 ⁢ 
                 
                   R 
                   5 
                 
               
               + 
               
                 V 
                 BE234 
               
               - 
               
                 
                   
                     AR 
                     5 
                   
                   ⁢ 
                   
                     V 
                     BE206 
                   
                 
                 
                   R 
                   4 
                 
               
             
           
           ; 
         
       
     
   
             I   4     =           V   T     ⁢           ⁢     ln   ⁡     (     M   N     )           NR   3       .           
Choosing M=8 and N=1/4,
 
               I   4     =           4   ⁢     V   T     ⁢     ln   ⁡     (   32   )           R   3       .     
     ⁢   at     ⁢           ⁢   300   ⁢   °   ⁢           ⁢   K       ,         V   234     ≈     V   206     ≈     0.74   ⁢           ⁢   V       ;                     ⅆ     V   BE3         ⅆ   T       ≈       ⅆ     V   BE4         ⅆ   T       ≈       -   1.5     ⁢           ⁢       mV     °   ⁢           ⁢   K       .             
Choosing A=1/4, B=3/2;
 
             V   REF     =       6   ⁢     V   T     ⁢       R   5       R   3       ⁢     ln   ⁡     (   32   )         -       (     1   4     )     ⁢       R   5       R   4       ⁢     V   BE206       +       V   BE234     .             
Setting
 
                 ⅆ     V   REF         ⅆ   T       =   0     ,         
for V REF  to have a zero temperature coefficient,
 
                 ⅆ     V   REF         ⅆ   T       =       6   ⁢     k   q     ⁢       R   5       R   3       ⁢     ln   ⁡     (   32   )         +       (     1   4     )     ⁢       R   5       R   4       ⁢   1.5   *     10     -   3         -     1.5   *     10     -   3             ;                   4.8   ⁢       R   5       R   3         +       R   5       R   4         =   4.         
For currents AI 5  and I 6  to be positive,
 
               BI   4     &gt;     A   ⁢       V   BE206       R   4           ;                   6   ⁢     V   T     ⁢   ln   ⁢           ⁢   32   ⁢       R   5       R   3         &gt;       (     1   4     )     ⁢     V   BE206     ⁢       R   5       R   4           ;                   R   4       R   3       &gt;         1.22   -     1.5   *     10     -   3       ⁢   T         7.17   *     10     -   3       ⁢   T       .           
Evaluating over a temperature range (e.g., −55° C.&lt;T&lt;125° C.), at −55° C. (i.e., T=218° K),
 
                 R   4       R   3       &gt;   0.5713     ,   and                 at   ⁢           ⁢   125   ⁢   °   ⁢           ⁢     C   .     (       i   .   e   .     ,     T   =     398   ⁢   °   ⁢           ⁢   K         )         ,     
     ⁢         R   4       R   3       &gt;     0.2183   .     
     ⁢   Therefore       ,           ⁢         R   4       R   3       &gt;     0.5713   .             
Also,
 
               R   5       R   4       =       4   -     4.8   ⁢       R   5       R   3           &gt;   0           
for the ratio of the two resistors to be positive;
 
                 R   5       R   3       &lt;     4   4.8       =       0.833   .     
     ⁢     V   REF       =       6   ⁢     V   T     ⁢       R   5       R   3       ⁢     ln   ⁡     (   32   )         -       (     1   4     )     ⁢       R   5       R   4       ⁢     V   BE206       +       V   BE234     .               
Assuming V BE206 =V BE234 =V BE ,
 
             V   REF     =       6   ⁢     V   T     ⁢       R   5       R   3       ⁢   ln   ⁢           ⁢   32     +       (     1   -       (     1   4     )     ⁢       R   5       R   4           )     ⁢     V   BE                       V   REF     =       6   ⁢     V   T     ⁢       R   5       R   3       ⁢   ln   ⁢           ⁢   32     +       (     1   -       (     1   4     )     ⁢       R   5       R   4           )     ⁢     (     1.22   -     1.5   *     10     -   3       ⁢   T       )               
Substituting
 
   
     
       
         
           
             
               
                 R 
                 5 
               
               
                 R 
                 4 
               
             
             = 
             
               4 
               - 
               
                 4.8 
                 ⁢ 
                 
                   
                     R 
                     5 
                   
                   
                     R 
                     3 
                   
                 
               
             
           
           , 
         
       
     
   
               V   REF     =       6   ⁢     V   T     ⁢       R   5       R   3       ⁢   ln   ⁢           ⁢   32     +       (     1   -   1   +     1.2   ⁢           ⁢       R   5       R   3           )     ⁢     (     1.22   -     1.5   *     10     -   3       ⁢   T       )           ;                   V   REF     =       1.8   *     10     -   3       ⁢       R   5       R   3       ⁢   T     +     (     1.464   ⁢           ⁢       R   5       R   3         )     -     1.8   *     10     -   3       ⁢       R   5       R   3       ⁢   T         ;                   V   REF     =         1.464   ⁢           ⁢         R   5       R   3       .     
     ⁢   Since     ⁢           ⁢       R   5       R   3         &lt;     4   4.8       =   0.833       ,     
     ⁢       V   REF     &lt;     1.22   ⁢     V   .     
     ⁢   However         ,         R   4       R   3       &gt;     0.5713   ⁢           ⁢   and                         R   5       R   4       &lt;       R   5       0.5713   ⁢           ⁢     R   3           ;                     R   5       R   4       +     4.8   ⁢           ⁢       R   5       R   3           &lt;         R   5       0.5713   ⁢           ⁢     R   3         +     4.8   ⁢           ⁢         R   5       R   3       .               
From above,
 
   
     
       
         
           
             
               
                 
                   R 
                   5 
                 
                 
                   R 
                   4 
                 
               
               + 
               
                 4.8 
                 ⁢ 
                 
                     
                 
                 ⁢ 
                 
                   
                     R 
                     5 
                   
                   
                     R 
                     3 
                   
                 
               
             
             = 
             4 
           
           ; 
         
       
     
   
                   R   5       0.5713   ⁢           ⁢     R   3         +     4.8   ⁢           ⁢       R   5       R   3           &gt;   4     ;                   R   5       R   3       &gt;     0.61   .             V   REF &gt;(1.464)0.61=0.893V. Hence, 0.893V&lt; V   REF &lt;1.22V. 
Choosing V REF =0.96V, in one embodiment of the present invention, R 3 =7.5 kΩ, R 4 =5.28 kΩ, R 5 =4.82 kΩ. The values given above are exemplary. Other values (e.g., resistances and transistor sizes) may be selected to obtain an appropriate voltage reference in a given environment.
 
   Voltage reference generator  200  provides reference voltages less than 1.0V (e.g., 0.96V) by subtracting a ctat current AI 5  from ptat current BI 4  to generate a current proportional to absolute temperature having a temperature coefficient more positive than the temperature coefficient of BI 4 . A current having a temperature coefficient greater than the temperature coefficient of BI 4  may also be achieved by adding a ptat current to B I 4  to form I 6 . As described above, the reference voltage of voltage reference generator  100  is 
               V   REF     =       V   BE114     +         PR   2     ⁢     V   T     ⁢     ln   ⁡     (     M   N     )           NR   1           ,         
which may be modeled as
   V   REF   =V   BE   +C   1   R   2   T.   
The reference voltage of voltage reference generator  200  is
 
                   V   REF     =       V   BE234     +       R   5     ⁡     (       BI   4     -     AI   5       )           ⁢     
     ⁢       V   REF     =       V   BE234     +       R   5     (           BV   T     ⁢     ln   ⁡     (     M   N     )           NR   3       -       AV   BE206       R   4         )         ⁢     
     ⁢       V   REF     =       V   BE234     +       R   5     ⁡     (         B4V   T     ⁢   ln   ⁢           ⁢   32       R   3       )       +       R   5     ⁢       A   ⁡     (     1.5   ⁢     mV   /           °     ⁢   KT         )         R   4         -       R   5     ⁢       1.22   ⁢   V       R   4               )     ,         
which may be modeled as
   V   REF   =V   BE   +C   2   R   5   T+C   3   R   5 . 
Since C 2  (i.e., the slope of current I 6  with respect to temperature) is greater than C 1  (i.e., the slope of current I 1  with respect to temperature), to maintain a constant voltage with respect to temperature, resistor R 5  is smaller than R 2 . However, C 3 , i.e., the offset of ptat current I 6 , is negative, thus reducing the reference voltage produced by voltage reference generator  200  from that produced by voltage reference generator  100  (e.g., below 1.2V). The increase in the temperature coefficient of I 6  and the offset of current I 6  allows reducing V REF  below 1.2V while maintaining a substantially zero temperature coefficient of V REF . The increase in the temperature coefficient of I 6  also allows reducing B, which reduces noise contributions from operational amplifier  212  at V REF . A smaller B also results in transistor  228  operating farther from its linear/quasi-saturation region.
 
   The reduction in V REF  from 1.2V improves the PSRR because the voltage headroom for the current mirror is at least 1.62V−0.96V=0.66V. Noise performance of voltage reference generator  200  is similar to that for voltage reference generator  100  because the noise from operational amplifier  222  is attenuated by A, thus the dominant noise component is from operational amplifier  212 . Ptat current I 6  has a greater slope as a function of temperature than ptat current BI 4 . The exemplary embodiment of circuit  200  was designed for a supply voltage of 1.62V and a reference voltage of 0.96V, however, this circuit is not limited thereto. Voltage reference generator  200  may be operated at other supply voltages and reference voltages, and remains operable so long as V DD −V REF &gt;400 mV (i.e., the current mirror remains operable) and 1.22V&gt;V REF &gt;0.893V. 
   While circuits and physical structures are generally presumed, it is well recognized that in modern semiconductor design and fabrication, physical structures and circuits may be embodied in computer readable descriptive form suitable for use in subsequent design, test, or fabrication stages. Structures and functionality presented as discrete components in the exemplary configurations may be implemented as a combined structure or component. The invention is contemplated to include circuits, systems of circuits, related methods, and computer-readable medium encodings of such circuits, systems, and methods, all as described herein, and as defined in the appended claims. As used herein, a computer readable medium includes at least disk, tape, or other magnetic, optical, semiconductor (e.g., flash memory cards, ROM), or electronic medium and a network, wireline, wireless or other communications medium.