Patent Publication Number: US-6337578-B2

Title: Redundancy circuitry for programmable logic devices with interleaved input circuits

Description:
This application is a continuation of U.S. patent application Ser. No. 09/527,903, filed Mar. 17, 2000, hereby incorporated by reference in its entirety, which is a continuation of U.S. patent application Ser. No. 09/082,081, filed May 20, 1998, now U.S. Pat. No. 6,107,820, hereby incorporated by reference herein in its entirety, which claims the benefit of U.S. provisional application No. 60/047,610, filed May 23, 1997. 
    
    
     BACKGROUND OF THE INVENTION 
     This invention relates to programmable logic devices, and more particularly, to redundancy circuitry for repairing programmable logic devices containing defects. 
     Programmable logic devices are integrated circuits that may be programmed to perform custom logic functions. Integrated circuit fabrication techniques are not perfect, so occasionally a programmable logic device may be fabricated with a defect. Unless the defect can be repaired before the logic device is put into use, the logic device must be discarded. Discarding such a device is wasteful, particularly when a defect is relatively minor. As a result, various redundancy schemes have been developed that allow spare circuitry to be switched into place to repair a defective portion of a circuit. 
     The difficulty of implementing a suitable redundancy scheme for a given logic device architecture depends on the attributes of the architecture. For example, there are difficulties associated with providing redundancy for programmable logic devices that use interleaved multiplexer circuitry to distribute signals to logic array blocks. Because adjacent logic array blocks share signal routing resources in such arrangements, the occurrence of a defect in one logic array block can affect an adjacent and otherwise defect-free logic array block. Although it might be possible to use a redundancy scheme in which both of these affected logic array blocks are replaced upon detection of a defect, such a scheme would necessarily involve bypassing at least one defect-free logic array block. A redundancy scheme that uses logic resources more efficiently would be desirable. 
     It is therefore an object of the present invention to provide a redundancy arrangement for programmable logic devices with interleaved input circuits. 
     SUMMARY OF THE INVENTION 
     This and other objects of the invention are accomplished in accordance with the principles of the present invention by providing redundant circuitry for a programmable logic device that uses interleaved input multiplexer circuits to distribute signals to adjacent logic regions. The programmable logic device has at least one row of logic regions and has multiple columns, each of which contains one of the interleaved input multiplexers and one of the logic regions. A set of conductors associated with the row of logic regions is used to convey signals between logic regions. 
     Each interleaved input multiplexer circuit distributes logic signals from the conductors in the row to two adjacent logic regions. One of the logic regions to which the signals are distributed is in the same column as the interleaved input multiplexer circuit. The other logic region to which the signals are distributed is in an adjacent column. 
     Bypass circuitry is provided in each column for bypassing the interleaved input multiplexer and logic region in that column. During manufacturing of the device, the device is tested to determine if any of the columns contain defective circuitry. If a defect is detected in a column, the manufacturer can repair the device by configuring the bypass circuitry to bypass that column during use of the device. 
     During programming of the programmable logic device, a user supplies programming data to the device that directs the various logic components on the device to perform desired logical functions. If a column of circuitry contains a defect, circuitry previously configured by the manufacturer shifts the programming data originally intended for that column into an adjacent column. The programming data originally intended for the adjacent column and each successive column of logic in the row is also shifted. 
     A spare column of logic is provided at the end of the row to receive the shifted programming data from the last column of regular logic when the programming data for the various columns of logic is being shifted to accommodate the bypassing of a defective column. The spare logic makes up for the logic that is lost when the defective column is bypassed. As a result, the same number of logic regions are used regardless of whether the device is repaired following detection of a defect or was defect free initially. 
     Outputs from the logic regions are applied to the conductors using programmable drivers. The drivers associated with each column typically form a unique pattern of connections to the conductors. When programming data is shifted to a successive column during repair of a defect, the programming data associated with the drivers is also shifted to the successive column. In one arrangement, the programmable logic device uses programming data redirecting circuitry to redirect the shifted programming data for the drivers back to the drivers in the original column. In another arrangement, auxiliary drivers are provided in each column. The auxiliary drivers in each column form the same pattern of connections to the conductors that are formed by the normal drivers in the previous column. When a column containing a defect is repaired, the auxiliary drivers in successive columns are used in place of the normal drivers to ensure that the outputs of the logic regions in the successive columns are directed to the same destinations that they would have been directed to had the programming data not been shifted. 
     The logic regions are preferably programmable logic array blocks, each of which contains a plurality of programmable logic elements based on a four-input look-up table or based on product term logic. 
     Two sets of logic array blocks may be provided in a row. In this type of arrangement, a single spare logic array block may be provided in the center of the row. This reduces the overhead associated with redundancy, because the two sets of logic array blocks in the row can share the spare logic array block. 
     Further features of the invention, its nature and various advantages will be more apparent from the accompanying drawings and the following detailed description of the preferred embodiments. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING 
     FIG. 1 is a circuit diagram of a portion of an illustrative programmable logic device with a redundancy arrangement in accordance with the present invention. 
     FIG. 2 is a more detailed circuit diagram of a portion of a programmable logic device of the type shown in FIG.  1 . 
     FIG. 3 is a circuit diagram of a portion of the programmable logic device of FIG. 2 showing the interleaved input multiplexer circuits in more detail. 
     FIG. 4 is a circuit diagram showing the circuitry used to route programming data to various portions of the programmable logic device of the present invention. 
     FIG. 5 is a circuit diagram showing the output driver connections that are made between logic array blocks and horizontal conductors in a programmable logic device in accordance with the present invention. 
     FIG. 6 is a circuit diagram showing an arrangement for reducing the overhead associated with providing redundancy in accordance with the present invention. 
     FIG. 7 is a diagram of a data processing system in which a programmable logic device having the redundancy circuitry of the present invention may be used. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Programmable logic devices are integrated circuits that contain logic that may be reconfigured or “programmed” by a user to perform custom logic functions. At their most basic level, programmable logic devices are based on programmable switches or connectors. Such programmable components may use random-access memory, read-only memory, erasable programmable read-only memory, electrically-erasable programmable read-only memory, fuses, antifuses, ferro-electric elements, or other suitable programmable component technology. 
     Programmable logic devices that contain redundant or spare circuitry may be configured by a manufacturer during the manufacturing process to repair portions of the circuit that are determined to be defective. 
     A programmable logic device integrated circuit having a redundancy arrangement in accordance with the present invention is shown in FIG.  1 . Programmable logic device  10  preferably has one or more rows of logic array blocks  12 , although the principles of the invention are applicable to programmable logic devices containing any suitable type of programmable logic region. The logic array blocks  12  in a row are interconnected by horizontal conductors  14 . If more than one row of logic array blocks  12  is desired, suitable vertical conductors and associated programmable routing circuitry (not shown) may be used to convey logic signals between rows. To avoid over-complicating the drawings, only a single row of logic array blocks  12  is shown in FIG.  1 . In addition, not all of the components of logic device  10  are shown in FIG.  1 . For example, details of the input/output circuitry for device  10  are not shown in FIG.  1 . 
     Each logic array block  12  preferably contains a number of programmable logic elements  16 . Logic elements  16  and other programmable logic circuitry in programmable logic device  10  may be programmed by a user to perform various logic functions. Logic elements  16  may be based on look-up table logic, product term logic, or any other suitable type of programmable logic. If desired, logic elements  16  may contain register logic for registering various logic signals. 
     Programmable logic device  10  has multiple columns each of which contains a logic array block  12  and an interleaved input multiplexer circuit  18 . Interleaved multiplexer circuits  18  are used to distribute logic signals from horizontal conductors  14  to logic array blocks  12 . Each interleaved input multiplexer circuit  18  distributes signals to two adjacent logic array blocks  12  via conductors  20 . One of the array blocks  12  to which the signals are distributed is in the same column as the interleaved input multiplexer circuit  18 . The other logic array block  12  to which the signals are distributed is in an adjacent column. Although conductors like conductors  14  and conductors  20  are depicted as single lines in FIG. 1, each such line typically represents multiple parallel signal conductors. 
     In each row of device  10  there is preferably at least one spare logic array block  12  and at least one spare interleaved input multiplexer circuit  18 . The location of such spare circuitry within a row of logic array blocks  12  is not critical. For example, spare circuitry may be located at either end of a row or may be located in the center of a row if desired. 
     During the manufacturing process, device  10  is tested by the manufacturer. If a defect is located in one of logic array blocks  12  or one of interleaved input multiplexer circuits  18 , device  10  may be repaired by replacing the logic array block  12  and interleaved input multiplexer circuit  18  in the defective column using the spare circuitry. 
     Replacing the defective circuitry typically involves configuring the device so that logic signals that were originally provided to the inputs of the defective circuitry are redirected to unaffected circuitry that is adjacent to the defective circuitry. For example, if it is determined that there is a defect located in the column containing logic array block  12   a  and interleaved input multiplexer circuit  18   a  (column N−1), bypass circuit  22   a  associated with that column may be used to redirect signals that would normally have been provided to inputs  20   a  of logic array block  12   a  to inputs  20   b  of logic array block  12   b  in column N. Bypass circuit  22   b  in column N, bypass circuit  22   c  in column N+1, and the bypass circuits in other columns are not used. 
     Each logic array block  12  in a row typically makes output connections to the horizontal conductors  14  in the row using a different pattern of drivers. As a result, replacing the defective circuitry also involves redirecting the outputs of some of the logic array blocks so that the outputs of the repaired row of logic array blocks are connected to horizontal conductors  14  in the same way that the outputs would have been connected to horizontal conductors  14  if the circuit had been defect free. This ensures that the output signals from each logic array block are directed to the same destinations that they would have been directed to had the circuit not contained a defect. A repaired circuit therefore works identically to a defect-free circuit. 
     For example, if it is determined that there is a defect located in logic array block  12   a  or interleaved input multiplexer circuit  18   a  in column N−1, output redirecting circuitry  24   a  may be used to redirect the signals at outputs  26   b  back to driver paths  28   a.  Because this allows the same pattern of driver connections to be used to connect outputs  26   b  to conductors  14  that would have been used to connect outputs  26   a  to conductors  14  had there been no defect, this arrangements ensures that the output signals from logic array block  12   b  are directed to the same destinations that the output signals from logic array block  12   a  would have been directed had logic array block  12   a  or interleaved input multiplexer circuit  18   a  not been defective. 
     Because outputs  26   b  of logic array block  12   b  are redirected to driver paths  28   a,  outputs  26   c  must be redirected to driver paths  28   b  by output redirecting circuit  24   b.  The outputs of the logic array blocks  12  in successive columns to the left of logic array block  12   c  use similar output redirecting circuits  24  to shift output signals to the output drivers in previous columns immediately to their right. 
     If desired, the original output driver patterns of a circuit can be preserved during replacement of defective circuitry using other output redirecting circuitry arrangements. For example, the output redirecting circuitry arrangement may have auxiliary driver paths  28 ′ that can be used in place of the circuitry of normal driver paths  28 . Each auxiliary driver path  28 ′ uses same pattern of drivers to connect its associated logic array block outputs to conductors  14  that are used by the normal driver path  28  in the previous column. 
     If no defective circuitry is found, each logic array block is connected to conductors  14  using its associated normal driver path  28 . If it is determined that a column contains a defect, the logic array blocks  12  to the right of the defective column are connected to conductors  14  using normal driver paths  28  and the logic array blocks  12  to the left of the defective column are connected to conductors  14  using auxiliary driver paths  28 ′. For example, if logic array block  12   a  is defective, the outputs of each logic array block  12  to the right of logic array block  12   a  are connected to conductors  14  using a respective one of normal driver paths  28 . However, the outputs of logic array block  12   b  and each logic array block  12  to the left of logic array block  12   b  are connected to conductors  14  using auxiliary driver paths  28 ′. 
     FIG. 2 is a more detailed circuit diagram of a portion of a programmable logic device of the type shown in FIG.  1 . The portion of the programmable logic device  30  shown in FIG. 2 has a single row and multiple columns of logic elements  32  that are interconnected by horizontal conductors  34 . A number of such logic elements  32  in each column are preferably grouped together to form a logic array block in each column, as shown in FIG.  1 . This level of detail is not shown in FIG. 2 to avoid over-complicating the drawings. Programmable logic device  30  also preferably contains multiple rows of such logic array blocks each of which contains the same type of logic element arrangement. The logic array blocks in other rows may be interconnected with the row of logic array blocks containing the row of logic elements  32  depicted in FIG. 2 using vertical conductors (not shown) to route signals between various rows of horizontal conductors  34 . Although there are only four logic elements  32  in the row of logic elements  32  shown in FIG. 2, logic device  30  may have any suitable number of logic elements  32 . 
     Logic elements  32  may be based on any suitable type of logic such as product term logic or look-up table logic and may contain register logic if desired. Logic elements  32  may have any suitable number of inputs and outputs. In the illustrative arrangement of FIG. 2, logic elements  32  have inputs A, B, C, and D, which may be, for example, the inputs to a standard four-input look-up table circuit. Logic elements  32  of FIG. 2 each have an L output and a G output which may be the outputs from a standard look-up table circuit. 
     Signals from horizontal conductors  34  are provided to input multiplexer circuits  36  by programmable multiplexers  38  and local vertical conductors  40 . Input multiplexer circuits  36  preferably extend past all of the logic elements  32  in a given logic array block. Programmable multiplexers  38  may be programmed by a user of device  30  to connect selected horizontal conductors  34  to local vertical conductors  40 . Local horizontal conductors  42  are used to direct signals from the input multiplexer circuits  36  to the logic elements  32 . 
     An illustrative set of input multiplexer circuits  36  and logic elements  32  is shown in more detail in FIG.  3 . As shown in FIG. 3, signals on the four local vertical conductors  40  associated with each input multiplexer circuit  36  may be selectively routed to the intersecting local horizontal conductors  42  by programmable connectors  43 . The operation of programmable connectors  43  is controlled by data in storage cells  45 . 
     Each multiplexer  47  directs one of the four horizontal conductors  42  connected to its input to an input of a logic element  32 . Each programmable multiplexer  38  is preferably formed from a number of individual programmable connectors  49 . 
     In the depicted embodiment of FIG. 2, there are four columns of logic elements  32 . Logic elements  32   b,    32   c,  and  32   d  are regular logic elements. Logic element  32   a  is a spare or redundant logic element  32 . During the manufacturing process, device  30  is tested for defects. If it is determined that device  30  is defect free, spare logic element  32   a  need not be used. If a defect is located in a column, the defect can be bypassed by bypassing the logic in that column. In addition, the circuitry of spare logic element  32   a  can be shifted into place to replace circuitry lost in the bypassed column (i.e., the bypassed logic element). 
     Each logic element  32  can receive signals from four associated input multiplexer circuits  36 . For example, logic element  32   c  may receive signals from input multiplexer circuits  36   e  and  36   f  (via the local horizontal conductors  42   a  connected to the A and C inputs of logic element  32   c ) and input multiplexer circuits  36   g  and  36   h  (via the local horizontal conductors  42   b ′ connected to the B and D inputs of logic element  32   c  with multiplexers  44 ). 
     Adjacent input multiplexer circuits  36  are interleaved with one another because they share a common set of local horizontal conductors  42 . For example, input multiplexer circuit  36   e  is interleaved with input multiplexer circuit  36   f  because the local horizontal conductors  42  that pass through input multiplexer  36   e  also pass through input multiplexer  36   f.    
     Local horizontal conductors  42   a  supply signals from input multiplexer circuits  36  directly to logic element inputs A and C. Local horizontal conductors  42   b  supply signals from input multiplexer circuits  36  to logic element inputs B and D via bypass multiplexers  44 . 
     During the manufacturing process, device  30  is tested to determine whether or not device  30  contains defective circuitry. If testing indicates that device  30  is defect free, no bypassing is needed. Bypass multiplexers  44  are therefore configured to pass signals from the local horizontal conductors  42   b  that are directly connected to their inputs to logic element inputs B and D via multiplexer outputs  46 . If testing indicates that device  30  contains a defect in one of the logic elements  32  or input multiplexer circuits  36  in a column, the manufacturer configures the appropriate bypass multiplexers  44  so that the defective logic in that column is bypassed. 
     For example, if a defect is detected in logic element  32   c  or in interleaved input multiplexer circuits  36   e  or  36   f  of column  2 , bypass multiplexers  44 ′ may be configured to route the signals from local horizontal conductors  42   b ′ to the B and D inputs of logic element  32   b  in column  3  via bypass conductors  48 , rather than to the B and D inputs of logic element  32   c  of column  2  via outputs  46 ′. 
     The pathways that supply programming data to the logic of device  30  are preferably configured by the manufacturer so that the programming data with which the user programs device  30  is routed to the appropriate logic during device programming. For example, the programming data that would have been used for the programmable multiplexers  38 ′ associated with interleaved input multiplexer circuits  36   e  and  36   f  had circuits  36   e  and  36   f  been used is directed to programmable multiplexers  38 ″. The programming data that would have been used to configure logic element  32   c  is provided to logic element  32   b.  The programming data that would have been used to establish the pattern of programmable connections between local vertical conductors  40 ′ and local horizontal conductors  42   a  and  42   b ″ in interleaved input multiplexers  36   e  and  36   f  of column  2  is provided to interleaved input multiplexer circuits  36   c  and  36   d  of column  3 . 
     Another change that is made when defective logic circuitry is bypassed relates to the paths of the logic element output signals provided to conductors  34 . When there is no defective circuitry, the output multiplexers  50  that are associated with each logic element  32  direct the L and G outputs of that logic element  32  directly to horizontal conductors  34 . For example, multiplexers  50 ′ direct the L and G outputs of logic element  32   c  to horizontal conductors  34  via drivers  52 ′ and paths  54 ′ and multiplexers  50 ″ direct the L and G outputs of logic element  32   b  to horizontal conductors  34  via drivers  52 ″ and paths  54 ″. When it is determined that device  30  contains defective circuitry, multiplexers  50  are configured so that the output signals are directed to the horizontal conductors  34  using the same driver patterns that were used when there was no defective circuitry. 
     For example, if a defect is detected in logic element  32   c  or in interleaved input multiplexer circuits  36   e  or  36   f  of column  2 , multiplexers  50 ′ and paths  58 ′ are used to redirect the output signals from logic element  32   b  in column  3  to the drivers  52 ′ associated with bypassed logic element  32   c  in column  2 . Similarly, multiplexers  50 ″ direct the outputs from spare logic element  32   a  in the redundant or spare column back to the drivers  52 ″ that were originally associated with logic element  32   b  in column  3 . This arrangement allows the pattern of connections  56  between paths  54  and horizontal conductors  34  that are associated with each set of drivers  52  to be preserved even if some of the circuitry on device  30  is rearranged during the replacement of defective circuitry by spare circuitry. 
     Each set of driver connections  56  typically drives a different pattern of horizontal conductors  34 . As a result, preserving the pattern of driver connections  56  that are used ensures that the logic element output signals for a given logic element  32  reach their intended destinations. 
     Drivers  54  are preferably programmable to either an on state or an off state. If desired, each driver  54  can drive more than one conductor  34 . Unlike the programming data for the logic element  32  and input multiplexer  36  in a defective column, which is shifted to a non-defective logic element  32  and a non-defective input multiplexer in an adjacent column, the programming data for the drivers in the defective column is ultimately not shifted. This is shown in FIG.  4 . 
     The programming arrangement of FIG. 4 has multiple vertical chains of programming storage cells  60 . The programming data loaded into storage cells  60  configures the programmable logic with which the cells  60  are associated. Each column of cells  60  is associated with a different column of logic elements  32 , input multiplexer circuits  36 , and programmable multiplexers  38  in device  30  in FIG.  2 . For example, the redundant column of cells  60  of FIG. 4 may be associated with redundant logic element  32   a  of FIG. 2, column  3  of cells  60  may be associated with logic element  32   b,  column  2  of cells  60  may be associated with logic element  32   c,  and column  1  of cells  60  may be associated with logic element  32   d.    
     To program the device, programming data supplied to input line  62  is serially clocked into the data registers  64 . If no defective circuitry is detected, multiplexers  68  are configured to shift the programming data for columns  1 ,  2 , and  3  into data registers  66   b,    66   c,  and  66   d.  The programming data in registers  66   b,    66   c,  and  66   d  is clocked into the vertical chains of cells  60  in columns  3 ,  2 , and  1  respectively. 
     If defective circuitry is detected (e.g., in column  2 ), multiplexers  68  are configured to shift the programming data that would normally have traveled down the vertical chain of cells  60  in column  2  to column  3  and the programming data that would normally have traveled down the vertical chain of cells  60  in column  3  to the redundant or spare column. The programming data for column  1  is unaffected. 
     Shifting the programming data for logic elements  32 , input multiplexer circuits  36 , and programmable multiplexers  38  allows the logic functions originally to be performed by the circuitry that was found to be defective to be performed by defect-free circuitry. The multiplexer arrangement of FIG. 2 redirects the output signals of each shifted logic element back to the original column during use of the device so that the original drivers are used. This requires that the programming data for these drivers be shifted back to the original column containing the defective circuitry during device programming rather than remain in the column to which it was shifted. 
     As shown in FIG. 4, programming data for the various components of the device are loaded serially. For example, all of the programming data for the drivers in a row of logic array blocks may be loaded before loading the programming data for the logic elements, the input multiplexer circuits, and the programmable multiplexers  38  for that row. Shifting multiplexers  70  are used to selectively redirect the driver programming data back to the row in which that data was originally to be used before detection of the defect. For example, if column  2  contains a defective circuit, the programming data originally intended for the drivers in column  2  is shifted into column  3  with the rest of the shifted column  2  programming data by multiplexers  68 ′, but is redirected back into column  2  and into the appropriate cells  60 ′ via path  72  and multiplexer  70 ′. 
     Because programming data is loaded serially from the top of each columns of cells  60 , configuring multiplexer  70 ′ to redirect the programming data for the column  2  drivers back to column  2  from column  3  causes all the other programming data that passes through multiplexer  70 ′ to be directed to column  2  even if that data is for column  3  circuitry. Multiplexer  74 ′ is therefore used to ensure that the programming data that is directed back to column  2  by multiplexer  70  is directed back to column  3 , so that the programmable logic associated with column  3  is programmed correctly. The other multiplexers  70  and  74  are also configured to direct the programming data for the drivers and other circuit components to the appropriate cells to program device  30 . 
     The programming data for drivers  52  does not need to be rerouted back to its original column if each column of logic is provided with an auxiliary set of drivers that may be used whenever logic is shifted during repair of a defective logic region. One suitable arrangement of this type is shown in FIG.  5 . As shown in FIG. 5, the L and G outputs of logic elements  76  may be connected to horizontal conductors  78  through either normal drivers  80  or auxiliary drivers  82 . If a column has no defects, then the outputs of the logic elements  76  in that column are provided to horizontal conductors  78  through the normal drivers  80 . 
     For example, if there are no defects in the logic of column  2 , the L and G outputs of logic element  76   a  are applied to horizontal conductors  78  via normal drivers  80  and connections  84  and  86 . If there is a defect in column  2 , the logic functions that are normally performed by the logic of logic element  76   a  are performed by logic element  76   b.  This is accomplished by configuring the device so that the programming data originally intended for the logic of column  2  is shifted into column  3  during device programming. In order to retain the same pattern of output driver connections in column  3  that would have been used in column  2 , the L and G outputs of logic element  76   b  are applied to horizontal conductors  78  via auxiliary drivers  82  and connections  88  and  90 . 
     The auxiliary drivers  82  associated with each column make the same connections to the horizontal conductors  78  as the normal drivers  80  associated with the previous column (i.e., the next column to the right). For example, connections  88  and  90 , which are connections associated with the auxiliary drivers  82  for the L and G outputs in column  3 , are connected to the same horizontal conductors as connections  84  and  86 , which are connections associated with the regular drivers  80  for the L and G outputs in column  2 . If column  2  contains a defect, the logic element  76  in column  1  uses normal drivers  80  and the logic element in column  2  is not used. The logic elements in column  3  and the redundant column use auxiliary drivers  82 . 
     As shown in FIG. 2, input multiplexer circuits  36   a  and  36   j  are “end caps.” End caps are active input multiplexer circuits that provide symmetry to the layout of device  30  and facilitate the programming of device  30  by reducing potential software fitting problems. Input multiplexer circuit  36 a provides symmetry by balancing input multiplexer circuit  36   d,  which is located on the opposite side of logic element  32   a  and input multiplexer circuit  36   j  provides symmetry by balancing input multiplexer circuitry  36   g,  which is located on the opposite side of logic element  32   d.    
     If a defect is detected in an input multiplexer adjacent to an end cap, programming data is shifted somewhat differently than when a defect is detected in the middle of a row of logic elements. In particular, the programming data for four logic components (one logic element and three input multiplexer circuits) is shifted rather than the programming data for three components (one logic element and two input multiplexer circuits). For example, if a defect is detected in input multiplexer circuit  36   i  of device  30  in FIG. 2, the programming data for the following regions of logic is shifted: input multiplexer circuit  36   i  (shifted to input multiplexer circuit  36   g ), logic element  32   d  (shifted to logic element  32   c ), input multiplexer circuit  36   h  (shifted to input multiplexer  36   f ), and input multiplexer circuit  36   g  (shifted to input multiplexer circuit  36   e ). This switching arrangement is equivalent to shifting only the programming data associated with input multiplexer circuit  36   i.    
     In certain situations it may be desirable to reduce the overhead costs associated with providing spare circuitry. As shown in FIG. 6, programmable logic array device  92  may be contain an array of logic regions  94 , each of which has two groups of logic array blocks (GOLs)  96 . Each GOL  96  contains two sets of logic array blocks  98 . Spare logic array blocks  100  may be provided in the center of the two sets of logic array blocks  98  per row in each logic region  94 . A redundancy scheme such as the one shown in FIG. 2 may be used to repair logic regions  94  using spare logic array blocks  100 . Because spare logic array blocks  100  are centrally located, it is only necessary to provide a single spare logic array block  100  for each row containing two sets of logic array blocks  98 , rather than providing two such spare logic array blocks  100 , thereby reducing overhead. 
     The foregoing arrangements are typically used in programmable logic devices that are made part of larger systems. FIG. 7 shows a programmable logic device  102  containing the redundancy circuitry of this invention in use in a digital data processing system  104 . Data processing system  104  may include one or more of the following components: a processor  106 , memory  108 , I/O circuitry  110 , and peripheral drivers  112 . These components are coupled together by a system bus  114  and populate a circuit board  116  that is contained in system  104 . 
     System  104  may be used in a wide variety of applications, such as computer networking, data networking, instrumentation, video processing, digital signal processing, or any other application where the advantage of using programmable logic is desirable. Programmable logic device  102  may be used to perform a variety of different logic functions. For example, programmable logic device  102  may be configured as a processor or controller that works in cooperation with processor  106 . Programmable logic device  102  may also be used as an arbiter for arbitrating access to a shared resource in system  104 . In yet another example, programmable logic device  102  may be configured as an interface between processor  106  and one of the other components in system  104 . 
     The programmable connections made between various components in the programmable logic devices of the present invention can be implemented in any of a wide variety of ways. For example, each programmable connection can be a relatively simple programmable connector such as a switch or a plurality of switches for connecting any one of several inputs to an output. Each such connection may be configured using a memory cell such as a random-access memory cell. Alternatively, programmable connectors can be somewhat more complex elements which are capable of performing logic (e.g., by logically combining several of their inputs) as well as making connections. For example, each programmable connection can use product term logic, implementing functions such as AND, NAND, OR, or NOR. Examples of components suitable for implementing programmable connections are erasable programmable read-only memories (EPROMs), electrically-erasable programmable read-only memories (EEPROMs), pass transistors, transmission gates, antifuses, laser fuses, metal optional links, etc. These programmable components may be controlled by various programmable function control elements or memory cells, which store the configuration data used to control the programmable components and various programmable logic circuits. Examples of suitable function control elements include static random-access memory (SRAM) cells, dynamic random-access memory (DRAM) cells, first-in first-out cells, EPROMs, EEPROMs, function control registers (e.g., as in Wahlstrom U.S. Pat. No. 3,473,160), ferro-electric memories, fuses, antifuses, or the like. From the various examples mentioned above it will be seen that this invention is applicable both to one-time-only programmable and reprogrammable devices. 
     The foregoing is merely illustrative of the principles of this invention and various modifications can be made by those skilled in the art without departing from the scope and spirit of the invention.