Patent Publication Number: US-10770444-B2

Title: Electronics package having a multi-thickness conductor layer and method of manufacturing thereof

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     The present application is a continuation of, and claims priority to, U.S. patent application Ser. No. 15/343,252, filed Nov. 4, 2016, the disclosure of which is incorporated herein by reference in its entirety. 
    
    
     BACKGROUND OF THE INVENTION 
     Embodiments of the invention relate generally to semiconductor device packages or electronics packages and, more particularly, to an electronics package that includes a conductor with locally varied thicknesses. This multi-thickness conductor includes a combination of regions having high current carrying capabilities and high density routing capabilities and facilitates the integration of different types of electronics devices in a miniaturized package topology. 
     As semiconductor device packages have become increasingly smaller and yield better operating performance, packaging technology has correspondingly evolved from leaded packaging, to laminated-based ball grid array (BGA) packaging, to chip scale packaging (CSP), then flipchip packages, and now buried die/embedded chip build-up packaging. Advancements in semiconductor chip packaging technology are driven by ever-increasing needs for achieving better performance, greater miniaturization, and higher reliability. 
     A challenge to existing manufacturing techniques is the miniaturization of electronics packages that incorporate different types of individually packaged semiconductor dies that have different current carrying and routing density requirements, such as a mixture digital semiconductor devices and power semiconductor devices. The general structure of a prior art electronics package  10  incorporating a number of individually packaged components  12 ,  14 ,  16 ,  18  is shown in  FIG. 1 . The individually packaged components  12 ,  14 ,  16 ,  18  are mounted on a multi-layer printed circuit board (PCB)  20  that has a thickness  22  of approximately 31 to 93 mils. The individually packaged components  12 ,  14 ,  16 ,  18  may be power semiconductor packages, packaged controllers, or other discrete electrical components such as inductors or passive components that are coupled to electrical contacts  24  of PCB  20  using metalized connections  26  such as, for example, solder balls in the form of a ball grid array (BGA). 
     In the illustrated example, individually packaged devices  14 ,  16  each include a respective semiconductor device or die  28 ,  30  having contact pads  32  formed on an active surface thereof. Die  28 ,  30  are provided on a mounting platform  34 ,  36  and encased within an insulating material  38 ,  40 . Wirebonds  42 ,  44  form direct metal connections between active surfaces of respective die  28 ,  30  and a metalized input/output (I/O) provided on or coupled to the lower surface of die  28 ,  30 . In the case of discrete component  14 , wirebonds  42  form an electrical connection between contact pads  32  of die  28  to I/O pads  46  provided on a bottom surface of discrete component  14 . Wirebond  42  electrically couples contact pads  32  to I/O leads  48 . Where die  30  is a diode, for example, wirebond  42  may connect to the anode on a first surface of the die  30  and a second surface of the die  30  may be soldered to the leadframe. I/O pads  46  and I/O leads  48  are coupled to electrical contacts  24  of PCB  20  by way of metalized connections  26 . The overall thickness  50  of such prior art IC packages may be in the range of 500 μm-2000 μm or larger. 
     Alternatively, electrical connections between components may be realized using a combination of thick and thin conductor layers that are electrically connected to the appropriate semiconductor dies or power devices using through hole or via technology. However, inclusion of multiple routing layers adds considerable thickness to the overall electronics package, a factor that in combination with the complex conductor structure, limits product level miniaturization, design flexibility, and cost efficiency. Additionally, both of the aforementioned techniques include multiple routing layers, which results in a long and complex conductor structure between electrical components and weakens the electrical performance of the overall package, which is increasingly unfavorable in high performance packaging (e.g., high frequency, RF, intelligent power, and other advanced electronics packaging). 
     Accordingly, it would be desirable to provide a new electronics packaging technology that permits electrical components of different types to be integrated into a highly miniaturized electronics package with locally enhanced electrical and thermal conductivity for certain electronics components and increased routing density in regions proximate other electronics components. It would further be desirable for such a packaging technology to permit a shorter conductor length between electrical components and improve signal fidelity. 
     BRIEF DESCRIPTION OF THE INVENTION 
     In accordance with one aspect of the invention, an electronics package includes an insulating substrate, a first electrical component coupled to a first surface of the insulating substrate, and a first conductor layer formed on the first surface of the insulating substrate. A second conductor layer is formed on a second surface of the insulating substrate, opposite the first surface, the second conductor layer extending through vias in the insulating substrate to contact at least one contact pad of the first electrical component and couple with the first conductor layer. The electronics package also includes a second electrical component having at least one contact pad coupled to the first conductor layer. The first conductor layer has a thickness greater than a thickness of the second conductor layer. 
     In accordance with another aspect of the invention, a method of manufacturing an electronics package includes providing an insulating substrate, forming a first conductor layer on a first surface of the insulating substrate, and coupling a first electrical component to the first surface of the insulating substrate. The method also includes coupling a second electrical component to the first conductor layer and forming a second conductor layer on a second surface of the insulating substrate, opposite the first surface. The second conductor layer extends through vias formed in the insulating substrate to electrically couple with the first conductor layer and contact at least one contact pad on the first electrical component. The first conductor layer is formed having a thickness greater than a thickness of the second conductor layer. 
     In accordance with yet another aspect of the invention, an electronics package includes an insulating substrate having a top surface and a bottom surface and a multi-thickness conductor extending through vias in the insulating substrate. The multi-thickness conductor includes a first conductor layer formed on the bottom surface of the insulating substrate and a second conductor layer formed on the top surface of the insulating substrate and electrically coupled with the first patterned conductor layer through a portion of the vias, the second patterned conductor layer having a thickness less than a thickness of the first patterned conductor layer. A first electrical component is affixed to the bottom surface of the insulating substrate, the first electrical component having a plurality of contact pads electrically coupled to the second conductor layer through another portion of the vias. A second electrical component having at least one contact pad is coupled to the first conductor layer. 
     These and other advantages and features will be more readily understood from the following detailed description of preferred embodiments of the invention that is provided in connection with the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The drawings illustrate embodiments presently contemplated for carrying out the invention. 
       In the drawings: 
         FIG. 1  is a schematic cross-sectional side view of a prior art electronics package incorporating a power die and a digital die. 
         FIGS. 2-7A  are schematic cross-sectional side views of an electronics package during various stages of a manufacturing/build-up process according embodiments of the invention. 
         FIG. 8  is a schematic cross-sectional side view of the electronics package of  FIG. 7  further including an insulating material surrounding the electrical components, according to another embodiment of the invention. 
         FIG. 9  is a schematic cross-sectional side view of the electronics package of  FIG. 7  further including a direct bond copper (DBC) substrate, according to another embodiment of the invention. 
         FIGS. 10-15  are schematic cross-sectional side views of an electronics package of during various stages of a manufacturing/build-up process according to another embodiment of the invention. 
     
    
    
     DETAILED DESCRIPTION 
     Embodiments of the present invention provide for an electronics package that includes multiple semiconductor devices, dies, or chips coupled to a patterned conductor layer with locally varied thicknesses. This multi-thickness conductor layer is formed on opposing surfaces of an insulating substrate, extends through the insulating substrate, and includes regions having different routing density and current carrying capabilities. As described in more detail below, portions of the multi-thickness conductor layer include a low density routing pattern that provides the requisite current carrying capabilities for one type of electrical component, such as a power semiconductor die, while other, thinner portions of the conductor layer have a high density routing pattern that enables routing capability below 100/100 μm L/S for another type of electrical component, such as a digital semiconductor die. 
     As used herein, the phrase “power semiconductor device” refers to a semiconductor component, device, die or chip designed to carry a large amount of current and/or support a large voltage. Power semiconductor devices are typically used as electrically controllable switches or rectifiers in power electronic circuits, such as switched mode power supplies, for example. Non-limiting examples of power semiconductor devices include insulated gate bipolar transistors (IGBTs), metal oxide semiconductor field effect transistors (MOSFETs), bipolar junction transistors (BJTs), integrated gate-commutated thyristors (IGCTs), gate turn-off (GTO) thyristors, Silicon Controlled Rectifiers (SCRs), diodes or other devices or combinations of devices including materials such as Silicon (Si), Silicon Carbide (SiC), Gallium Nitride (GaN), and Gallium Arsenide (GaAs). In use, power semiconductor devices are typically mounted to an external circuit by way of a packaging structure, with the packaging structure providing an electrical connection to the external circuit and also providing a way to remove the heat generated by the devices and protect the devices from the external environment. Typical power semiconductor devices include two (2) to four (4) input/output (I/O) interconnections to electrically connect both sides of a respective power semiconductor device to an external circuit. 
     As used herein, the phrase “digital semiconductor device” refers to a semiconductor component, device, die, or chip provided in the form of a digital logic device, such as a microprocessor, microcontroller, memory device, video processor, or an Application Specific Integrated Circuit (ASIC), as non limiting examples. As is understood in the art, digital semiconductor devices have reduced current carrying requirements and require increased routing density as compared to power semiconductor devices due to the differences in interconnection pitch and number of I/Os between the device types. A digital semiconductor device may include anywhere between ten and thousands of I/Os depending on the device configuration. 
     While the electrical components embedded in the electronics package are referenced below in the embodiments of  FIGS. 2-15  specifically as one or more power semiconductor devices in combination with one or more digital semiconductor devices, it is understood that other combinations of differently configured electrical components could be substituted in the electronics package, and thus embodiments of the invention are not limited only to the embedding of power devices and digital devices in a common electronics package. That is, the technique of using locally varied planar conductor thicknesses may be extended to electronics packages with any combination of electrical components having differing current carrying capabilities and routing density structures. Thus, the electronics package embodiments described below should also be understood to encompass electronics packages including resistors, capacitors, inductors, filters, or other similar devices, provided either alone or in combination with one or more power or digital devices. Additionally, while the embodiments of  FIGS. 2-15  are described as including one power device and one digital device, it is contemplated that the concepts described herein may be extended to electronics packages that include any combination of three or more electrical components. 
     Referring now to  FIGS. 2-7 , cross-sectional views showing the various build up steps of a technique for manufacturing an electronics package  100  are illustrated according to an embodiment of the invention. A cross-section of the build-up process for a singular electronics package  100  is shown in  FIGS. 2-7  for ease of visualization of the build-up process. However, one skilled in the art will recognize that multiple electronics packages could be manufactured in a similar manner at the panel level and then singulated into individual electronics packages as desired. As described in detail below, electronics package  100  includes a combination of different semiconductor devices or die  102 ,  104 . In the illustrated embodiment described herein, die  102  is a power semiconductor device and die  104  is a digital semiconductor device. However, electronics package  100  may include any combination of electrical components requiring different current carrying and routing density capabilities in alternative embodiments. 
     Referring first to  FIG. 2 , the manufacturing technique begins by plating an insulating substrate  106  with a first conductor layer  108 . According to various embodiments, insulating substrate  106  may be provided in the form of an insulating film or dielectric substrate, such as for example a Kapton® laminate flex, although other suitable materials may also be employed, such as Ultem®, polytetrafluoroethylene (PTFE), or another polymer film, such as a liquid crystal polymer (LCP) or a polyimide substrate, as non-limiting examples. First conductor layer  108  is an electrically conductive metal such as, for example, copper. However, other electrically conducting materials or a combination of metal and a filling agent may be used in other embodiments. First conductor layer  108  may be applied directly to the bottom surface  110  of insulating substrate  106  using a sputtering and electroplating technique or other electroless method of metal deposition. Alternatively, a titanium adhesion layer and copper seed layer  111  ( FIG. 7A ) may first be applied to the bottom surface  110  of insulating substrate  106  using a sputtering process, followed by an electroplating process that increases a thickness  114  of the first conductor layer  108  to a desired level. In the embodiments described herein, thickness  114  may be in the range of 25 μm-250 μm. However, it is contemplated that first conductor layer  108  may be formed having a thickness outside this range of values in alternative embodiments. In yet another embodiment, the manufacturing technique may begin by providing a metal-clad insulating film. 
     Next a first layer photoresist mask  116 , shown in  FIG. 3 , is formed on first conductor layer  108  and is patterned with openings for a high current, I/O routing layer. With the first layer photoresist mask  116  in place, first conductor layer  108  is subsequently patterned using an etching process. After the first layer photoresist mask  116  is removed, one or multiple organic or inorganic coating layers (not shown), such as organic solderability preservative (OSP) or Ni/Au, may be applied to the surface of first conductor layer  108 . 
     A layer of insulating material  118  is used to affix a digital semiconductor device  104  to insulating substrate  106 , as shown in  FIG. 4 . As used herein the phrase “insulating material” refers to an electrically insulating material that adheres to surrounding components of the electronics package such as a polymeric material (e.g., epoxy, liquid crystal polymer, ceramic or metal filled polymers) or other organic material as non-limiting examples. In some embodiments, insulating material  118  may be provided in either an uncured or partial cured (i.e., B-stage) form. In the illustrated embodiment, insulating material  118  is limited to a select portion of bottom surface  110  of insulating substrate  106 , however, insulating material  118  may be applied to coat the entirety of bottom surface  110  and all or portions of exposed surfaces of patterned first conductor layer  108  in alternative embodiments. Insulating material  118  may be applied using a coating technique such as spin coating or slot die coating, using a lamination or spray process, or may be applied by a programmable dispensing tool in the form of an inkjet printing-type device technique, as non-limiting examples. Alternatively, insulating material  118  may be applied to digital semiconductor device  104  prior to placement on insulating substrate  106 . In alternative embodiments, digital semiconductor device  104  may be affixed to insulating substrate  106  by way of an adhesive property of the insulating substrate  106  itself. 
     Digital semiconductor device  104  is positioned into insulating material  118  using conventional pick and place equipment and methods. As shown, digital semiconductor device  104  is positioned with respect to insulating substrate  106  such that a top surface or active surface  120  comprising electrical contact pads  122  or connection pads is positioned into insulating material  118 . Contact pads  122  provide conductive routes (I/O connections) to internal contacts within digital semiconductor device  104  and may have a composition that includes a variety of electrically conductive materials such as aluminum, copper, gold, silver, nickel, or combinations thereof as non-limiting examples. As understood in the art, the number of contact pads  122  on digital semiconductor device  104  is dependent upon the complexity and intended functionality of device  104 . The pad pitch (i.e., the center-to-center distance between adjacent contact pads) is inversely proportional to the number of contact pads  122  provided on digital semiconductor device  104 . While not shown in the illustrated embodiment, it is contemplated that other discrete or passive devices, such as, for example, a resistor, a capacitor, or an inductor, may be affixed to insulating substrate  106  by way of insulating material  118 . 
     After semiconductor device  104  is positioned, insulating material  118  is fully cured, thermally or by way of a combination of heat or radiation. Suitable radiation may include UV light and/or microwaves. In one embodiment, a partial vacuum and/or above atmospheric pressure may be used to promote the removal of volatiles from the insulating material  118  during cure if any are present. 
     Referring now to  FIG. 5 , a plurality of vias  124 ,  126  are formed through insulating substrate  106  and insulating material  118 . As shown, vias  124  are aligned with remaining portions of first conductor layer  108  and vias  126  are formed to expose contact pads  122  of semiconductor device  104 . Vias  124 ,  126  may be formed by a UV laser drilling or dry etching, photo-definition, or mechanical drilling process as non-limiting examples. Alternately, vias  124 ,  126  may be formed by way of other methods including: plasma etching, dry and wet etching, or other laser techniques like CO2 and excimer. In one embodiment, vias  124 ,  126  are formed having angled side surfaces, as shown in  FIG. 5 , to facilitate later filling and metal deposition. Vias  124 ,  126  are subsequently cleaned such as through a reactive ion etching (RIE) desoot process or laser process. 
     While the formation of vias  124 ,  126  through insulating substrate  106  and insulating material  118  is shown in  FIG. 5  as being performed after placement of digital semiconductor device  104  into insulating material  118 , it is recognized that the placement of semiconductor device  104  could occur after via formation. Furthermore, a combination of pre- and post-drilled vias could be employed. 
     A second conductor layer  128  or metallization layer is then plated on the top surface  130  of insulating substrate  106 . Similar to first conductor layer  108 , second conductor layer  128  is an electrically conducting material and may be applied using any of the techniques described above with respect to first conductor layer  108 . Optionally, a titanium adhesion layer and copper seed layer  129  ( FIG. 7A ) may first be applied via a sputtering process to the top surface  130  of insulating substrate  106  prior to applying second conductor layer  128 . 
     As shown, second conductor layer  128  extends through vias  126  and electrically couples with contact pads  122  of digital semiconductor device  104 . Second conductor layer  128  has a thickness  132  less than the thickness  114  of conductor layer  108 . The reduced thickness  132  of second conductor layer  128  permits the portion  134  of second conductor layer  128  electrically coupled to digital semiconductor device  104  to be formed having a routing pattern with a high density routing capability. As used herein, the phrase “high density routing capability” or “high density L/S pattern” refers to a routing capability below 100/100 μm L/S (line/space). In an exemplary embodiment, thickness  132  is in the range of approximately 4 μm-30 μm. However, one skilled in the art will recognize that the thickness  132  of second conductor layer  128  may be varied to correspond to the interconnection pitch of a particular digital semiconductor die  104 . 
     A second layer photoresist mask  136 , shown in  FIG. 6 , is formed on second conductor layer  128  and patterned with openings that define a routing layer electrically connected to contact pads  122  of digital semiconductor device  104  and conductor layer  108 . With the second layer photoresist mask  136  in place, second conductor layer  128  is patterned using an etching process. As shown in  FIG. 7 , the process yields a patterned second conductor layer  128  with openings for a high density L/S pattern that extends out from contact pads  122  of digital semiconductor device  104 , through vias  126 , and out across the top surface  130  of insulating substrate  106 . Together, the first conductor layer  108  and second conductor layer  128  create a multi-thickness conductor layer  138  that extends through insulating substrate  106  and has high density routing capabilities for digital semiconductor device  104  and high current carrying capabilities for power semiconductor device  102 . Multi-thickness conductor layer  138  has an overall thickness  139  equal to the combined thicknesses  114 ,  132  of the first conductor layer  108  and second conductor layer  128  plus the thickness  141  of the insulating substrate  106 . 
     After any remaining portions of second layer photoresist mask  136  are removed, a joining material  140  is used to mechanically and electrically couple power semiconductor device  102  to conductor layer  108 . According to various embodiments, joining material  140  may be solder, sintered silver, a conductive adhesive such as a polymer filled with an electrically conductive filler such as silver, or another electrically conductive material able to withstand high temperatures. In one embodiment, a liquid phase bonding joining technique is used to couple power semiconductor device  102  to conductor layer  108 . 
     As shown, joining material  140  is electrically coupled to contact pads  142  or connection pads located on a top surface or active surface  144  of power semiconductor device  102 . Similar to contact pads  122  of digital semiconductor device  104 , contact pads  142  provide conductive routes (I/O connections) to internal contacts within power semiconductor device  102  and are formed of an electrically conductive material. In the case where power semiconductor device  102  is an IGBT, for example, contact pads  142  are coupled to corresponding emitter and/or gate or anode regions of the power semiconductor device  102 . Depending on the device configuration, power semiconductor device  102  may also include at least one lower collector pad or contact pad  146  (shown in phantom) that is disposed on its backside or lower surface  148 . 
     In the fabrication technique described above, power semiconductor device  102  is affixed to conductor layer  108  as a final step of the fabrication technique. Doing so beneficially permits multi-thickness conductor layer  138  to be tested prior to attaching the costly power semiconductor device  102 . In alternative embodiments, power semiconductor device  102  may be affixed at any time after forming first conductor layer  108 . 
     Referring to  FIGS. 8 and 9 , a solder mask layer  150  may be applied over the second conductor layer  128  of electronics package  100  to provide a protective coating and define interconnect pads. Interconnect pads may have a metal finish, such as Ni or Ni/Au, to aid solderability. A series of input/output (I/O) connections  152  are then made to provide a route for electrical connections between the power semiconductor device  102 , digital semiconductor device  104 , and external components (not shown) such as, for example a busbar or printed circuit board (PCB). Such I/O connections  152  may be provided in the form of plated bumps or pillar bumps, as non-limiting examples. 
     In some embodiments, power semiconductor device  102  and digital semiconductor device  104  are overcoated with a layer of electrically insulating material  154  to provide rigidity and ease of handling and to prevent arcing between semiconductor devices and other metal components in high voltage applications. Such a configuration is shown in  FIG. 8  and is applicable in embodiments where the power semiconductor device  102  is a lateral device that does not include a connection to the backside of the device  102 . As shown in  FIG. 9 , electrically insulating material  154  may also be applied to fill the region between power semiconductor device  102  and conductor layer  108 . 
     In embodiments where power semiconductor device  102  includes one or more lower contact pad  146 , a conductive substrate  156  may be provided to create an electrical connection to lower contact pad  146  as shown in  FIG. 9 . Conductive substrate  156  may be an encapsulated metal lead frame or a multi-layer substrate such as, for example, a printed circuit board (PCB) or DBC substrate as shown in the illustrated embodiment that includes a non-organic ceramic substrate with upper and lower sheets of copper bonded to both sides thereof with a direct bond copper interface or braze layer. The electrical connection between conductive substrate  156  and power semiconductor die  104  is made through a conductive joining layer  158 , such as solder, silver paste, or a conductive adhesive as examples, which is formed on lower contact pad  146 . In such an embodiment, the connection between conductive substrate  156  and the lower contact pad  146  of power semiconductor device  102  is made prior to filling the volume between the conductive substrate  156  and the insulating substrate  106  with electrically insulating material  154 . 
     An alternative technique for manufacturing an electronics package  160  is illustrated in  FIGS. 10-15 . Electronics package  160  includes a number of similar components as electronics package  100 , and thus numbers used to indicate components in  FIGS. 2-9  will also be used to indicate similar components in  FIGS. 10-15 . 
     Similar to the manufacturing technique described with respect to  FIG. 2 , manufacture of electronics package  160  begins by applying a first conductor layer  108  to the bottom surface  110  of insulating substrate  106 , as shown in  FIG. 10 . Alternatively, fabrication of electronics package  160  may begin with a metal-clad dielectric substrate. A first layer photoresist mask  162  ( FIG. 11 ) is then applied to mask the portion of conductor layer  108  corresponding to a low density L/S pattern. An etching technique is used to remove portions of the conductor layer  108  exposed by the first layer photoresist mask  162 . 
     Insulating material  118  ( FIG. 12 ) is next applied and used to affix digital semiconductor device  104  and power semiconductor device  102  to insulating substrate  106 . After insulating material  118  is cured, a series of vias  124 ,  126  are formed through insulating substrate  106 , conductor layer  108  and cured insulating material  118 , as shown in  FIG. 13 . Second conductor layer  128  is then formed on the top surface  130  of insulating substrate  106  and extends through vias  124 ,  126  to electrically connect to contact pads  122 ,  142 . 
     Referring to  FIG. 14 , a second layer photoresist mask  136  is applied to the top surface  164  of the second conductor layer  128 . Select portions of second photoresist mask  136  are removed to define a high density L/S pattern. The exposed portions of second conductor layer  128  are then removed using an etching technique resulting in the formation of the high density L/S pattern, as shown in  FIG. 15 . After etching process is complete, the remaining portions of second layer photoresist mask  136  are removed using a stripping technique to yield the electronics package  160  shown in  FIG. 15 . The multi-thickness conductor layer  138  formed by the combination of first conductor layer  108  and second conductor layer  128  thus includes a high density routing pattern for electrical connections to digital semiconductor device  104  and a low density routing pattern with high current carrying capabilities for power semiconductor device  102 . 
     Similar to the embodiments illustrated in  FIGS. 8 and 9 , fabrication of electronics package  160  may also include the addition of an electrically insulating material and I/O connections. Where one or more of the embedded electrical components includes a backside contact pad, similar to contact pad  146  of  FIG. 7 , a conductive substrate may be included to provide an electrical connection thereto in a similar manner as illustrated in  FIG. 9 . 
     Beneficially, use of the multi-thickness conductor layer enables locating disparate electrical components much closer in proximity to each other than prior art techniques such as that shown in  FIG. 1 , while providing the requisite high density routing capabilities and high current carrying capabilities for the different types of electrical components. The multi-thickness conductor layer also provides a shorter and less complex conductor structure between electrical components as compared to the prior art techniques, thus improving the reliability of electrical connections within the packaging structure. 
     Therefore, according to one embodiment of the invention, an electronics package includes an insulating substrate, a first electrical component coupled to a first surface of the insulating substrate, and a first conductor layer formed on the first surface of the insulating substrate. A second conductor layer is formed on a second surface of the insulating substrate, opposite the first surface, the second conductor layer extending through vias in the insulating substrate to contact at least one contact pad of the first electrical component and couple with the first conductor layer. The electronics package also includes a second electrical component having at least one contact pad coupled to the first conductor layer. The first conductor layer has a thickness greater than a thickness of the second conductor layer. 
     According to another embodiment of the invention, a method of manufacturing an electronics package includes providing an insulating substrate, forming a first conductor layer on a first surface of the insulating substrate, and coupling a first electrical component to the first surface of the insulating substrate. The method also includes coupling a second electrical component to the first conductor layer and forming a second conductor layer on a second surface of the insulating substrate, opposite the first surface. The second conductor layer extends through vias formed in the insulating substrate to electrically couple with the first conductor layer and contact at least one contact pad on the first electrical component. The first conductor layer is formed having a thickness greater than a thickness of the second conductor layer. 
     According to yet another embodiment of the invention, an electronics package includes an insulating substrate having a top surface and a bottom surface and a multi-thickness conductor extending through vias in the insulating substrate. The multi-thickness conductor includes a first conductor layer formed on the bottom surface of the insulating substrate and a second conductor layer formed on the top surface of the insulating substrate and electrically coupled with the first patterned conductor layer through a portion of the vias, the second patterned conductor layer having a thickness less than a thickness of the first patterned conductor layer. A first electrical component is affixed to the bottom surface of the insulating substrate, the first electrical component having a plurality of contact pads electrically coupled to the second conductor layer through another portion of the vias. A second electrical component having at least one contact pad is coupled to the first conductor layer. 
     While the invention has been described in detail in connection with only a limited number of embodiments, it should be readily understood that the invention is not limited to such disclosed embodiments. Rather, the invention can be modified to incorporate any number of variations, alterations, substitutions or equivalent arrangements not heretofore described, but which are commensurate with the spirit and scope of the invention. Additionally, while various embodiments of the invention have been described, it is to be understood that aspects of the invention may include only some of the described embodiments. Accordingly, the invention is not to be seen as limited by the foregoing description, but is only limited by the scope of the appended claims.