Patent Publication Number: US-10790781-B2

Title: Semiconductor integrated circuit

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2018-093309, filed on May 14, 2018; the entire contents of which are incorporated herein by reference. 
     FIELD 
     Embodiments described herein relate generally to a semiconductor integrated circuit. 
     BACKGROUND 
     In a semiconductor integrated circuit having a charge pump circuit and a negative feedback circuit, a voltage output from the charge pump circuit can be controlled by a negative feedback operation of the negative feedback circuit by using power received at a power supply input terminal. At this time, in order to use the semiconductor integrated circuit as a constant voltage power supply circuit, it is desirable to stabilize the negative feedback operation of the negative feedback circuit. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a circuit diagram illustrating a configuration of a semiconductor device including a semiconductor integrated circuit according to an embodiment; 
         FIG. 2  is a circuit diagram illustrating a configuration of the semiconductor integrated circuit according to the embodiment; 
         FIG. 3  is a circuit diagram illustrating a configuration example of the charge pump circuit in the embodiment; 
         FIG. 4  is a circuit diagram illustrating another configuration example of the charge pump circuit in the embodiment; 
         FIGS. 5A and 5B  are diagrams illustrating open loop frequency characteristics of the semiconductor integrated circuit according to the embodiment; 
         FIG. 6  is a diagram illustrating the stability of operations of the semiconductor integrated circuit according to the embodiment; 
         FIG. 7  is a circuit diagram illustrating a configuration of a semiconductor integrated circuit according to Modified Example of the embodiment; 
         FIGS. 8A and 8B  are diagrams illustrating open loop frequency characteristics of the semiconductor integrated circuit according to Modified Example of the embodiment; 
         FIG. 9  is a circuit diagram illustrating a configuration of a semiconductor integrated circuit according to another Modified Example of the embodiment; and 
         FIGS. 10A and 10B  are diagrams illustrating open loop frequency characteristics of the semiconductor integrated circuit according to another Modified Example of the embodiment. 
     
    
    
     DETAILED DESCRIPTION 
     In general, according to one embodiment, there is provided a semiconductor integrated circuit including an oscillation circuit, a charge pump circuit, a smoothing circuit, and a negative feedback circuit. The charge pump circuit is arranged between each of a power supply input terminal and the oscillation circuit and a power supply output terminal. The smoothing circuit is arranged between the charge pump circuit and the power supply output terminal. The negative feedback circuit is arranged on a path returning from the smoothing circuit to the oscillation circuit. The smoothing circuit includes a first zero point generation circuit. 
     Exemplary embodiments of a semiconductor integrated circuit will be explained below in detail with reference to the accompanying drawings. The present invention is not limited to the following embodiments. 
     Embodiment 
     A semiconductor integrated circuit according to an embodiment is a circuit including a power supply circuit that adjusts (steps up or steps down) the power supply voltage. For example, a semiconductor integrated circuit is a circuit having a power supply circuit such as a step-up circuit or a step-down circuit and a feedback loop and can be used as a constant voltage power supply circuit that steps up or steps down an external power to generate a predetermined internal power. 
     The semiconductor device  1  including the semiconductor integrated circuit  100  can be configured, for example, as illustrated in  FIG. 1 .  FIG. 1  is a circuit diagram illustrating a configuration of the semiconductor device  1  including the semiconductor integrated circuit  100  The semiconductor device  1  includes the semiconductor integrated circuit  100  and a load circuit  2 . The semiconductor integrated circuit  100  has a power supply input terminal TMin, a monitor terminal TMm, and a power supply output terminal TMout. A power supply voltage Vdd is directly applied to the power supply input terminal TMin otherwise a power supply voltage Vdd generated in the semiconductor device  1  is applied to the TMin. The monitor terminal TMm is a terminal provided for monitoring operations of the semiconductor integrated circuit  100  and may be omitted. The power supply output terminal TMout is electrically connected to the load circuit  2  and supplies the power supply voltage Vout adjusted (stepped up or stepped down) by the semiconductor integrated circuit  100  to the load circuit  2 . As a result, the load circuit  2  can operate by using the power supply voltage Vout. 
     The semiconductor integrated circuit  100  can be configured, for example, as illustrated in  FIG. 2 .  FIG. 2  is a circuit diagram illustrating a configuration of the semiconductor integrated circuit  100 . The semiconductor integrated circuit  100  includes a power supply circuit  110  and a control circuit  120 . The power supply circuit  110  is arranged on a path extending from the power supply input terminal TMin to the power supply output terminal TMout. The control circuit  120  is arranged on a path (feedback loop) that returns from the power supply output terminal TMout to the power supply input terminal TMin. 
     The power supply circuit  110  receives the power supply voltage Vdd via the power supply input terminal TMin, adjusts (steps up or steps down) the power supply voltage, and outputs the adjusted power supply voltage Vout to the load circuit  2  via the power supply output terminal TMout. The control circuit  120  controls the power supply circuit  110  so that the power supply circuit  110  adjusts the level of the power supply voltage Vout to a predetermined target, level Vtg (refer to  FIG. 6 ). 
     The power supply circuit  110  has a charge pump circuit Ill and a filter circuit (smoothing circuit)  112 . The control circuit  120  has a negative feedback circuit  121  and an oscillation circuit  122 . 
     The negative feedback circuit  121  is arranged on a path (feedback loop) returning from the filter circuit  112  to the oscillation circuit  122 . The negative feedback circuit  121  has an input node  121   i  and an output node  121   o . The input node  121   i  is electrically connected to the power supply output terminal TMout via the output node  112   o  of the filter circuit  112 . The output node  121   o  is electrically connected to the control node  122   c  of the oscillation circuit  122 . 
     The negative feedback circuit  121  can be configured with, for example, a comparator having an inverting input terminal to which a feedback voltage is supplied and a non-inverting input terminal to which a target level Vtg is supplied. 
     The negative feedback circuit  121  inverts the phase of the feedback voltage by about 180 degrees and outputs a signal (comparison result) indicating whether or not the level of the feedback voltage is higher than the target level Vtg. For example, the negative feedback circuit  121  compares the level of the feedback voltage with the target level Vtg. When the level of the feedback voltage is higher than the target level Vtg, the negative feedback circuit can output the comparison result of the logical low level, and when the level of the feedback voltage is lower than the target level Vtg, the negative feedback circuit can output the comparison result of the logical high level. 
     The oscillation circuit  122  is arranged on a path (feedback loop) returning from the negative feedback circuit  121  to the charge pump circuit  111 . The oscillation circuit  122  has a control node  122   c  and an output node  122   o . In the oscillation circuit  122 , the control node  122   c  is electrically connected to the negative feedback circuit  121 , and the output node  122   o  is electrically connected to the charge pump circuit  111 . 
     The oscillation circuit  122  can be configured with a ring oscillator, which odd numbered inverters are cascaded like a ring shape, which have variable current sources or variable impedance elements which are connected to the control node  122   c . In the case of receiving the comparison result of the logical high level, the oscillation circuit  122  can increase the frequency and/or the amplitude of the oscillation operation by increasing the operating current. In the case of receiving the comparison result of the logical low level, the oscillation circuit  122  can decrease the frequency and/or the amplitude of the oscillation operation. 
     The oscillation circuit  122  receives a signal (comparison result) from the negative feedback circuit  121  at the control node  122   c , performs an oscillation operation at a frequency and/or amplitude according to the comparison result, and supplies a clock ϕCK obtained by the oscillation operation and an inverted clock ϕCKB to the charge pump circuit  111  via the output node  122   o . In the case of receiving the comparison result of the logical high level, the oscillation circuit  122  increases the frequency and/or the amplitude of the oscillation operation and supplies the obtained clock ϕCK and the inverted clock ϕCKB to the charge pump circuit  111 . In the case of receiving the comparison result of the logical low level, the oscillation circuit  122  decreases the frequency and/or the amplitude of the oscillation operation and supplies the obtained clock ϕCK and the inverted clock ϕCKB to the charge pump circuit  111 . 
     The charge pump circuit  111  is arranged between each of the power supply input terminal TMin and the oscillation circuit  122  and each of the filter circuit  112  and the power supply output terminal TMout. The charge pump circuit  111  adjusts (steps up or steps down) the power supply voltage Vdd received from the power supply input terminal TMin according to the signal received from the oscillation circuit  122  and supplies the adjusted power supply voltage Vp to the filter circuit  112 . 
     The charge pump circuit  111  has an input node  111   i , a control node group  111   c , and an output node  111   o . In the charge pump circuit  111 , the input node  111   i  is electrically connected to the power supply input terminal TMin, the control node group  111   c  is electrically connected to the oscillation circuit  122 , and the output node  111   o  is electrically connected to the filter circuit  112 . 
     Specifically, the charge pump circuit  111  can be configured as illustrated in  FIG. 3 .  FIG. 3  is a circuit diagram illustrating a configuration example of the charge pump circuit  111 . The charge pump circuit  111  illustrated in  FIG. 3  is a circuit called a Dickson type and has a plurality of diodes D 11  and D 12  and a plurality of capacitive elements C 11  and C 12 . 
     The plurality of diodes D 11  and D 12  is arranged in series on a power supply line PL extending from the input node  111   i  to the output node  111   o . The anode of the diode D 11  is electrically connected to the input node  111   i , and the cathode of the diode D 11  electrically connected to the node N 11  on the power supply line PL. The anode of the diode D 12  is electrically connected to the node N 11  on the power supply line PL, and the cathode is electrically connected to the output node  111   o  via the node N 12  on the power supply line PL. 
     The plurality of capacitive elements C 11  and C 12  is arranged in parallel between the power supply line PL and the control node group  111   c . The control node group  111   c  includes a plurality of control nodes  111   c   1  and  111   c   2 . One end of the capacitive element C 11  is electrically connected to the node N 11  on the power supply line PL, and the other end of the capacitive element C 11  is electrically connected to the oscillation circuit  122  via the control node  111   c   1 . One end of the capacitive element C 12  is electrically connected to the node N 12  on the power supply line PL, and the other end of the capacitive element C 12  is electrically connected to the oscillation circuit  122  via the control node  111   c   2 . The clock ϕCK is supplied from the oscillation circuit  122  to the control node  111   c   1 , and the inverted clock ϕCKB is supplied from the oscillation circuit  122  to the control node  111   c   2 . Since the clock ϕCK is a pulse-shaped signal, the clock can be transmitted from the control node  111   c   1  to the node N 11  on the power supply line PL via the capacitive element C 11 . Since the inverted clock ϕCKB is a pulse-shaped signal, the inverted clock can be transmitted from the control node  111   c   2  to the node N 12  on the power supply line PL via the capacitive element C 12 . 
     In the charge pump circuit  111  illustrated in  FIG. 3 , in a state where no charge is accumulated in the node N 11 , the diode D 11  is biased with a voltage equal to or higher than the forward on voltage in the forward direction and turned on, and electric charges corresponding to the voltage according to the power supply voltage Vdd are accumulated in the node N 11 . In addition, the diode D 12  is biased with a voltage lower than the forward on voltage in the forward direction or in the reverse direction and turned off. 
     When the logical high level of the clock ϕCK is supplied to the node N 11  and the logical low level of the inverted clock ϕCKB is supplied to the node N 12 , the diode D 11  is biased with a voltage lower than the forward on voltage in the forward direction or in the reverse direction and turned off, electric charges are further accumulated in the node N 11  by the logical high level of the clock ϕCK, and the voltage of the node N 11  is stepped up from the voltage according to the power supply voltage Vdd (for example, up to Vdd+ΔV 11 ). In addition, the diode D 12  is biased with a voltage equal to or higher than the forward on voltage in the forward direction and turned on, and electric charges corresponding to the stepped-up voltage (Vdd+ΔV 11 ) are accumulated in the node N 12 . 
     When the logical low level of the clock ϕCK is supplied to the node N 11  and the logical high level of the inverted clock ϕCKB is supplied to the node N 12 , the diode D 11  is biased with a voltage equal to or higher than the forward on voltage in the forward direction and turned on, and electric charges corresponding to the voltage according to the power supply voltage Vdd are accumulated in the node N 11 . In addition, the diode D 12  is biased with a voltage lower than the forward on voltage in the forward direction or in the reverse direction and turned off, electric charges are further accumulated in the node N 12  by the logical high level of the inverted clock ϕCKB, and the voltage of the node N 12  is stepped up from the voltage according to the power supply voltage Vdd (for example, up to Vdd+□ΔV 11 +ΔV 12 ). As a result, the charge pump circuit  111  supplies the stepped-up power supply voltage Vp (for example, a voltage of “Vdd+ΔV 11 ” to “Vdd+ΔV 11 +ΔV 12 ”) to the filter circuit  112  via the output node  111   o.    
     Alternatively, the charge pump circuit  111  can be configured as illustrated in  FIG. 4 .  FIG. 4  is a circuit diagram illustrating another configuration example of the charge pump circuit  111 . The charge pump circuit  111  illustrated in  FIG. 4  is a circuit called a synchronous rectification type and has a plurality of transistors NM 21 , NM 22 , PM 21 , and PM 22 . 
     On a path extending from the input node  111   i  to the output node  111   o , a power supply line PL 20  is branched to two power supply lines PL 21  and PL 22  which are parallel to each other, and then, the two power supply lines are merged into a power supply line PL 23 . The plurality of transistors NM 21  and PM 21  is arranged in series on the power supply line PL 21  extending from the input node  111   i  to the output node  111   o . The plurality of transistors NM 22  and PM 22  is arranged in series on the power supply line PL 22  extending from the input node  111   i  to the output node  111   o . The plurality of transistors NM 22  and PM 22  is arranged in parallel to the plurality of transistors NM 21  and PM 21  between the input node  111   i  and the output node  111   o.    
     The transistor NM 21  can be configured with an NMOS transistor. The gate of the transistor NM 21  is electrically connected to the gate of the transistor PM 21  and a node N 22  on the power supply line PL 22 , the source of the transistor NM 21  is electrically connected to the input node  111   i , and the drain of the transistor NM 21  is electrically connected to the node N 21  on the power supply line PL 21 . The transistor PM 21  can be configured with a PMOS transistor. The gate of the transistor PM 21  is electrically connected to the gate of the transistor NM 21  and the node N 22  on the power supply line PL 22 , the source of the transistor PM 21  is electrically connected to the node N 21  on the power supply line PL 21 , and the drain of the transistor PM 21  is electrically connected to the output node  111   o  via a node N 23 . 
     The transistor NM 22  can be configured with an NMOS transistor. The gate of the transistor NM 22  is electrically connected to the gate of the transistor PM 22  and the node N 21  on the power supply line PL 21  on the power supply line PL 21 , the source of the transistor NM 22  is electrically connected to the input node  111   i , and the drain of the transistor NM 22  is electrically connected to the node N 22  on the power supply line PL 22 . The transistor PM 22  can be configured with a PMOS transistor. The gate of the transistor PM 22  is electrically connected to the gate of the transistor NM 22  and the node N 21  on the power supply line PL 21 , the source of the transistor PM 22  is electrically connected to the node N 22  on the power supply line PL 22 , and the drain of the transistor PM 22  is electrically connected to the output node  111   o  via the node N 23 . 
     The control node group  111   c  includes the plurality of control nodes  111   c   1  and  111   c   2 . The control node  111   c   1  is electrically connected to the node N 22  on the power supply line PL 22 . The control node  111   c   2  is electrically connected to the node N 21  on the power supply line PL 21 . The clock ϕCK is supplied from the oscillation circuit  122  to the control node  111   c   1 , and the inverted clock ϕCKB is supplied from the oscillation circuit  122  to the control node  111   c   2 . 
     In the charge pump circuit  111  illustrated in  FIG. 4 , when the logical high level of the clock ϕCK is supplied to the node N 22  and the logical low level of the inverted clock ϕCKB is supplied to the node N 21 , the transistor NM 21  is turned on and the transistor PM 21  is turned off in the power supply line PL 21 , and electric charges corresponding to the voltage according to the power supply voltage Vdd are accumulated in the node N 21 . At this time, the transistor NM 22  in the power supply line PL 22  is turned off. 
     When the logical low level of the clock ϕCK is supplied to the node N 22  and the logical high level of the inverted clock ϕCKB is supplied to the node N 21 , the transistor NM 22  is turned on and the transistor PM 22  is turned off in the power supply line PL 22 , and electric charges corresponding to the voltage according to the power supply voltage Vdd are accumulated in the node N 22 . At this time, the transistor NM 21  in the power supply line PL 21  is turned off, the electric charges are further accumulated in the node N 21  by the logical high level of the inverted clock ϕCKB, the voltage of the node N 21  is stepped up from the voltage according to the power supply voltage Vdd (for example, up to Vdd+ΔV 21 ), the transistor PM 21  is turned on, and electric charges corresponding to the stepped-up voltage (Vdd+ΔV 21 ) are accumulated in the node N 23 . 
     When the logical high level of the clock ϕCK is supplied to the node N 22  and the logical low level of the inverted clock ϕCKB is supplied to the node N 21 , the transistor NM 21  is turned on and the transistor PM 21  is turned off in the power supply line PL 21 , and electric charges corresponding to the voltage according to the power supply voltage Vdd are accumulated in the node N 21  again. At this time, the transistor NM 22  in the power supply line PL 22  is turned off, electric charges are further accumulated in the node N 22  by the logical high level of the clock ϕCK, the voltage of the node N 22  is stepped up from the voltage according to the power supply voltage Vdd (for example, up to Vdd+ΔV 22 ), the transistor PM 22  is turned on, and electric charges corresponding to the stepped-up voltage (Vdd+ΔV 22 ) are accumulated in the node N 23 . 
     Returning to  FIG. 2 , since the charge pump circuit  111  is controlled by pulses (clock ϕCK and inverted clock ϕCKB) from the oscillation circuit  122 , the amplitude of the output power supply voltage Vp can vary with time (refer to  FIG. 6 ). However, in consideration of ease of use in the load circuit  2  (refer to  FIG. 1 ), it is desirable that time variation of the power supply voltage Vp is suppressed. 
     In order to suppress time variation of the power supply voltage Vp, the filter circuit (smoothing circuit)  112  is arranged between the charge pump circuit  111  and the power supply output terminal TMout. The filter circuit  112  smoothes the power supply voltage Vp supplied from the charge pump circuit  111  and supplies the smoothed power supply voltage Vout to the power supply output terminal TMout. 
     The filter circuit  112  has an input node  112   i  and an output node  112   o . The input node  112   i  is electrically connected to the charge pump circuit  111 . The output node  112   o  is electrically connected to each of the power supply output terminal TMout and the negative feedback circuit  121 . 
     Specifically, the filter circuit  112  has a low-pass filter  113 . The low-pass filter  113  has a resistive element R 1  and a capacitive element C 1 . 
     The resistive element R 1  is arranged between the charge pump circuit  111  and the power supply output terminal TMout. One end of the resistive element R 1  is electrically connected to the charge pump circuit  111  via the input node  112   i , and the other end of the resistive element R 1  is electrically connected to one end of the capacitive element C 1  and is electrically connected to the power supply output terminal TMout via the output node  112   o.    
     The capacitive element C 1  is arranged between the resistive element R 1  and the power supply output terminal TMout. The capacitive element C 1  is shunt-connected to the path extending from the input node  112   i  through the resistive element R 1  to the output node  112   o . One end of the capacitive element C 1  is electrically connected to the other end of the resistive element R 1  and the output node  112   o , and the other end of the capacitive element C 1  is electrically connected to the ground potential. 
     In the semiconductor integrated circuit  100 , the power supply voltage Vp adjusted (stepped up or stepped down) by the charge pump circuit  111  is smoothed by the filter circuit  112  and is output as the power supply voltage Vout from the power supply output terminal TMout to the load circuit  2  and is fed back to the negative feedback circuit  121 . The power supply voltage Vout fed back to the negative feedback circuit  121  is referred to as a feedback voltage. 
     In a case where the level of the feedback voltage Vout is lower than the target level Vtg, the negative feedback circuit  121  outputs an logical high level signal to the oscillation circuit  122 . In response to this, the oscillation circuit  122  increases the frequency and/or the amplitude of the oscillation operation and supplies the obtained clock ϕCK and the inverted clock ϕCKB to the charge pump circuit  111 . Since the charge pump circuit  111  receives the clock ϕCK and the inverted clock ϕCKB having the increased frequency and/or amplitude, the charge pump circuit can increase the output voltage Vp. 
     In a case where the level of the feedback voltage Vout is higher than the target level Vtg, the negative feedback circuit  121  outputs an logical low level signal to the oscillation circuit  122 . In response to this, the oscillation circuit  122  decreases the frequency and/or the amplitude of the oscillation operation and supplies the obtained clock ϕCK and the inverted clock ϕCKB to the charge pump circuit  111 . Since the charge pump circuit  111  receives the clock ϕCK and the inverted clock ΔCKB having the decreased frequency and/or amplitude, the charge pump circuit can reduce the output voltage Vp. 
     According to these operations, the level of the output voltage Vp of the charge pump circuit  111  can be controlled so as to be close to the target level Vtg. Therefore, it can be considered that, by smoothing the output voltage Vp by the filter circuit  112 , the level of the power supply voltage Vout output from the power supply output terminal TMout can be stabilized so as to be within a predetermined required range. 
     However, with respect to the negative feedback loop in the semiconductor integrated circuit  100 , when an open-loop transfer function is considered, this open-loop transfer function is the complex number quantity of the gain and the phase. Considering the frequency characteristic, with respect to the phase margin (PM), which is defined at unity gain frequency (i.e., the frequency when the gain becomes 1, that is, 0 dB) f UG , when the phase margin (PM)=180°−(the deviation from the phase at the low frequency)&lt;0, this system is likely to be unstable. 
     That is, when the parasitic capacitance of the load circuit  2  connected to the power supply output terminal TMout of the semiconductor integrated circuit  100  increases, poles in the frequency characteristic are likely to be formed at the frequency lower than the unity gain frequency f UG  by the parasitic capacitance in the load circuit  2 , the parasitic resistance and the parasitic capacitance in the negative feedback circuit  121 , and the resistive element R 1  and the capacitive element C 1  in the filter circuit  112 . As a result, the phase of open loop characteristic of the semiconductor integrated circuit  100  rotates in the minus direction on the frequency lower than the unity gain frequency f UG , and the phase margin at the unity gain frequency f UG  is likely to become negative (likely to be PM&lt;0). That is, the negative feedback operation in the semiconductor integrated circuit  100  is likely to be unstable. 
     On the other hand, when the resistance value of the resistive element R 1  and the capacitance value of the capacitive element C 1  in the filter circuit  112  are decreased, the pole frequency can be shifted to the higher frequency side than the unity gain frequency f UG . However, in this case, since the cutoff frequency of the low-pass filter  113  is increased, the smoothing performance of the power supply voltage Vp is likely to deteriorate, and it becomes difficult to stabilize the level of the power supply voltage Vout output from the power supply output terminal TMout so as to be within a predetermined required range. When the level of the power supply voltage Vout deviates from a predetermined required range and hunting is large, there is a possibility that the load circuit  2  which is the supply destination of the power supply voltage Vout malfunctions. 
     Therefore, in the embodiment, in the semiconductor integrated circuit  100 , a circuit for forming the zero point in the frequency characteristic on the lower frequency side than the unity gain frequency f UG  is provided in the filter circuit  112 , so that the improvement of the smoothing performance of the power supply voltage and the improvement of the stability of the negative feedback operation can be simultaneously achieved. 
     Specifically, as illustrated in  FIG. 2 , the filter circuit  112  has a zero point generation circuit  114  and a pole generation circuit  115 . The zero point generation circuit  114  is arranged between the charge pump circuit  111  and the power supply output terminal TMout. 
     The zero point generation circuit  114  has the resistive element (first resistive element) R 1  and a capacitive element (first capacitive element) C 3 . The pole generation circuit  115  has the resistive element R 1 , the capacitive element C 3 , and the capacitive element C 1 . The zero point generation circuit  114  and the pole generation circuit  115  share the resistive element R 1  and the capacitive element C 3  with each other. The zero point generation circuit  114  shares the resistive element R 1  with the low-pass filter  113 . The pole generation circuit  115  includes the low-pass filter  113 . 
     The capacitive element C 3  is arranged in parallel to the resistive element R 1  between the charge pump circuit  111  and the power supply output terminal TMout. The resistive element R 1  and the capacitive element C 3  are connected in parallel to each other between the input node  112   i  and the intermediate node  112   m . One end of the capacitive element C 3  is electrically connected to the charge pump circuit  111  via the input node  112   i , and the other end of the capacitive element C 3  is electrically connected to the power supply output terminal TMout via the intermediate node  112   m  and the output node  112   o.    
     More specifically, in a case where the parasitic capacitance in the load circuit  2  (refer to  FIG. 1 ) and the parasitic resistance and the parasitic capacitance in the negative feedback circuit  121  can be neglected, the open-loop transfer function of the negative feedback loop of the charge pump circuit  111 →the filter circuit  112 →the negative feedback circuit  121 →the oscillation circuit  122 →the charge pump circuit  111  can be expressed approximately by the following Mathematical Formula 1. 
     
       
         
           
             
               
                 
                   
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     From Mathematical Formula 1, the frequency f z1  of the zero point generated by the zero point generation circuit  114  can be expressed by the following Mathematical Formula 2, and the frequency f P1  of the pole generated by the pole generation circuit  115  can be expressed by the following Mathematical Formula 3. 
     
       
         
           
             
               
                 
                   
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     It can be understood from Mathematical Formula 2 that by adjusting the capacitance value of the capacitive element C 3  without decreasing the resistance value of the resistive element R 1 , it is possible to locate the frequency f z1  of the zero point on the lower frequency side than the unity gain frequency f UG . At this time, according to Mathematical Formula 3, the frequency f P1  of the pole is located on the lower frequency side than the frequency f z1  of the zero point. 
     For example, the frequency characteristic of the semiconductor integrated circuit  100  is illustrated in  FIG. 5 .  FIG. 5A  illustrates the frequency characteristic of the gain of the semiconductor integrated circuit  100 , and  FIG. 5B  illustrates the frequency characteristic of the phase of the semiconductor integrated circuit  100 . In  FIG. 5A , the vertical axis represents the magnitude of the gain [dB], and the horizontal axis represents the magnitude of the frequency in log scale. In  FIG. 5B , the vertical axis represents the magnitude of the phase [deg] by arctan Vout/Vin), and the horizontal axis represents the magnitude of the frequency in log scale. 
     The frequency at which the gain=0 [dB] in the frequency characteristic of the gain in  FIG. 5A  can be defined as a unity gain frequency f UG . As illustrated in the frequency characteristic of the phase illustrated in  FIG. 5B , the next relationship can be obtained. 
     The relationship is as follows: Frequency of Pole f P1 &lt;Frequency of Zero Point f z1 &lt;Unity Gain Frequency f UG . 
     The frequency characteristic of the phase rotates to the minus side in the vicinity of the frequency f P1  of the pole (the phase lags), and the frequency characteristic of the phase rotates to the plus side at the frequency f z1  of the zero point (the lagging of the phase is mitigated), so the phase margin PM 1  at the unity gain frequency f UG  can be allowed to a positive value (PM 1 &gt;0). For example, in a case where R 1 =20 [kΩ], C 1 =50 [pF], and C 3 =2 [pF], the frequency of the pole becomes 0.153 [MHz], the frequency of the zero point becomes 3.98 [MHz], and the phase margin PM 1  becomes PM 1 ≈+0.25 [deg]. 
     As illustrated in  FIGS. 5A and 5B , the zero point acts to offset the pole, so the phase margin can be restored to a positive value, and as illustrated in  FIG. 6 , for example, at the time of start up of the semiconductor integrated circuit  100 , the settling operation of the power supply voltage Vout can be stabilized. That is, at the time of start up of the semiconductor integrated circuit  100 , the power supply voltage Vout can be controlled so as to satisfy the Mathematical Formula 4 after the timing t 1  at which the power supply voltage Vout reaches the target level Vtg.
 
 Vtg−ΔV   US   &lt;V out&lt; Vtg+ΔV   C3   (4)
 
     In Mathematical Formula 4, ΔV US  (&gt;0) represents an allowable undershoot amount with respect to the target level Vtg, and ΔV CS  (&gt;0) represents an allowable overshoot amount with respect to the target level Vtg. That is, the level of the power supply voltage Vout can be stabilized so as to be within a predetermined required range, and thus, the negative feedback operation of the negative feedback loop in the semiconductor integrated circuit  100  can be stabilized. 
     As described above, in the embodiment, in the semiconductor integrated circuit  100 , the circuit for forming the zero point in the frequency characteristic on the lower frequency side than the unity gain frequency f UG  is provided in the filter circuit  112 . Therefore, it is possible to simultaneously achieve the improvement of the smoothing performance of the power supply voltage and the improvement of the stability of the negative feedback operation. That is, the stability of the negative feedback loop can be improved while maintaining the smoothing performance for the charge pump output (Vp) at a required level. 
     In addition, in the semiconductor integrated circuit  100 , at least one of the pole frequencies generated by the filter circuit  112  can be allowed to be ⅕ times or less of the fundamental wave frequency of the waveform output by the oscillation circuit  122 . As a result, although the phase characteristic of the semiconductor integrated circuit  100  rotates in the minus direction on the considerably lower frequency side than the unity gain frequency f UG , the phase margin can be restored to a positive value by applying this embodiment. 
     Alternatively, in the semiconductor integrated circuit  100 , the zero point frequency generated by the filter circuit  112  may be 5 times or more and 200 times or less of the pole frequency. In this case, by applying this embodiment, it is possible to locate the frequency f z1  of the zero point on the lower frequency side than the unity gain frequency f UG , and thus, the phase margin can be restored to a positive value. 
     Alternatively, in the embodiment, a case where one zero point is formed in the frequency characteristic of the semiconductor integrated circuit is exemplified. However, it is considered that, if a plurality of zero points is formed in the frequency characteristic of the semiconductor integrated circuit, the phase margin in the frequency characteristic of the semiconductor integrated circuit can be further increased, and the negative feedback operation can be further stabilized. 
     On the basis of the idea, the semiconductor integrated circuit  200  can be configured, for example, as illustrated in  FIG. 7 .  FIG. 7  is a circuit diagram illustrating a configuration of the semiconductor integrated circuit  200  according to Modified Example of the embodiment. 
     The semiconductor integrated circuit  200  illustrated in  FIG. 7  has a filter circuit  212  instead of the filter circuit  112  (refer to  FIG. 2 ). In the filter circuit  212 , the zero point generation circuits are arranged in a two-stage configuration between the charge pump circuit  111  and the power supply output terminal TMout. That is, the filter circuit  212  further includes a low-pass filter  216  and a zero point generation circuit (second zero point generation circuit)  217  and is different in terms of the configuration of the pole generation circuit  215 . 
     The low-pass filter  216  is arranged between the low-pass filter  113  and the power supply output terminal TMout. The low-pass filter  216  has a resistive element R 2  and a capacitive element C 2 . The resistive element R 2  is arranged between the low-pass filter  113  and the power supply output terminal TMout. One end of the resistive element R 2  is electrically connected to the other end of the resistive element R 1  and one end of the capacitive element C 1 , and the other end of the resistive element R 2  is electrically connected to one end of the capacitive element C 2  and is electrically connected to the power supply output terminal TMout via the output node  112   o.    
     The capacitive element C 2  is arranged between the resistive element R 2  and the power supply output terminal TMout. The capacitive element C 2  is shunt-connected to a path extending from the input node  112   i  through the resistive elements R 1  and R 2  to the output node  112   o . One end of the capacitive element C 2  is electrically connected to the other end of the resistive element R 2  and the output node  112   o , and the other end of the capacitive element C 2  is electrically connected to the ground potential. 
     The zero point generation circuit  114  is arranged between the charge pump circuit  111  and the zero point generation circuit  217 . The zero point generation circuit  217  is arranged between the zero point generation circuit  114  and the power supply output terminal TMout. The zero point generation circuit  217  has the resistive element (second resistive element) R 2  and a capacitive element (second capacitive element) C 4 . The pole generation circuit  215  has the resistive element R 1 , the resistive element R 2 , the capacitive element C 3 , the capacitive element C 1 , the capacitive element C 4 , and the capacitive element C 2 . The zero point generation circuit  114  and the pole generation circuit  215  share the resistive element R 1  and the capacitive element C 3  with each other. The zero point generation circuit  217  and the pole generation circuit  215  share the resistive element R 2  and the capacitive element C 4  with each other. The zero point generation circuit  114  shares the resistive element R 1 , with the low-pass filter  113 . The zero point generation circuit  217  shares the resistive element R 2  with the low-pass filter  216 . The pole generation circuit  215  includes low-pass filters  113  and  216 . 
     The capacitive element C 4  is arranged in parallel to the resistive element R 2  between the charge pump circuit  111  and the power supply output terminal TMout. The resistive element R 2  and the capacitive element C 4  are connected in parallel to each other between the intermediate node  112   m  and the output node  112   o . One end of the capacitive element C 4  is electrically connected to the zero point generation circuit  114  via the intermediate node  112   m , and the other end of the capacitive element C 4  is electrically connected to the power supply output terminal TMout via the output node  112   o.    
     More specifically, in a case where the parasitic capacitance in the load circuit  2  (refer to  FIG. 1 ) and the parasitic resistance and the parasitic capacitance in the negative feedback circuit  121  can be neglected, the open-loop transfer function of the negative feedback loop of the charge pump circuit  111 →the filter circuit  212 →the negative feedback circuit  121 →the oscillation circuit  122 →the charge pump circuit  111  can be expressed approximately by the following Mathematical Formula 5. 
     
       
         
           
             
               
                 
                   
                       
                   
                   ⁢ 
                   
                     ( 
                     5 
                     ) 
                   
                 
               
             
             
               
                 
                   
                     G 
                     ⁡ 
                     
                       ( 
                       s 
                       ) 
                     
                   
                   = 
                   
                     
                       
                         
                           C 
                           3 
                         
                         ⁢ 
                         
                           C 
                           4 
                         
                       
                       
                         
                           
                             ( 
                             
                               
                                 C 
                                 1 
                               
                               + 
                               
                                 C 
                                 3 
                               
                             
                             ) 
                           
                           ⁢ 
                           
                             ( 
                             
                               
                                 C 
                                 2 
                               
                               + 
                               
                                 C 
                                 4 
                               
                             
                             ) 
                           
                         
                         + 
                         
                           
                             C 
                             2 
                           
                           ⁢ 
                           
                             C 
                             4 
                           
                         
                       
                     
                     × 
                   
                 
               
             
             
               
                 
                   
                       
                   
                   ⁢ 
                   
                     
                       
                         ( 
                         
                           s 
                           + 
                           
                             1 
                             
                               
                                 C 
                                 3 
                               
                               ⁢ 
                               
                                 R 
                                 1 
                               
                             
                           
                         
                         ) 
                       
                       ⁢ 
                       
                         ( 
                         
                           s 
                           + 
                           
                             1 
                             
                               
                                 C 
                                 4 
                               
                               ⁢ 
                               
                                 R 
                                 2 
                               
                             
                           
                         
                         ) 
                       
                     
                     
                       
                         s 
                         2 
                       
                       + 
                       
                         s 
                         ⁢ 
                         
                           
                             
                               
                                 ( 
                                 
                                   
                                     C 
                                     1 
                                   
                                   + 
                                   
                                     C 
                                     3 
                                   
                                 
                                 ) 
                               
                               ⁢ 
                               
                                 R 
                                 1 
                               
                             
                             + 
                             
                               
                                 ( 
                                 
                                   
                                     C 
                                     2 
                                   
                                   + 
                                   
                                     C 
                                     4 
                                   
                                 
                                 ) 
                               
                               ⁢ 
                               
                                 R 
                                 2 
                               
                             
                             + 
                             
                               
                                 C 
                                 2 
                               
                               ⁢ 
                               
                                 R 
                                 1 
                               
                             
                           
                           
                             
                               { 
                               
                                 
                                   
                                     ( 
                                     
                                       
                                         C 
                                         1 
                                       
                                       + 
                                       
                                         C 
                                         3 
                                       
                                     
                                     ) 
                                   
                                   ⁢ 
                                   
                                     ( 
                                     
                                       
                                         C 
                                         2 
                                       
                                       + 
                                       
                                         C 
                                         4 
                                       
                                     
                                     ) 
                                   
                                 
                                 + 
                                 
                                   
                                     C 
                                     2 
                                   
                                   ⁢ 
                                   
                                     C 
                                     4 
                                   
                                 
                               
                               } 
                             
                             ⁢ 
                             
                               R 
                               1 
                             
                             ⁢ 
                             
                               R 
                               2 
                             
                           
                         
                       
                       + 
                       
                         1 
                         
                           
                             
                               
                                 { 
                                 
                                   
                                     ( 
                                     
                                       
                                         C 
                                         1 
                                       
                                       + 
                                       
                                         C 
                                         3 
                                       
                                     
                                     ) 
                                   
                                   ⁢ 
                                   
                                     ( 
                                     
                                       
                                         C 
                                         2 
                                       
                                       + 
                                     
                                   
                                 
                               
                             
                           
                           
                             
                               
                                 
                                   
                                     
                                       
                                         C 
                                         4 
                                       
                                       ) 
                                     
                                     + 
                                     
                                       
                                         C 
                                         2 
                                       
                                       ⁢ 
                                       
                                         C 
                                         4 
                                       
                                     
                                   
                                   } 
                                 
                                 ⁢ 
                                 
                                   R 
                                   1 
                                 
                                 ⁢ 
                                 
                                   R 
                                   2 
                                 
                               
                             
                           
                         
                       
                     
                   
                 
               
             
           
         
       
     
     From Mathematical Formula 5, the frequency f z11  of the zero point generated by the zero point generation circuit  114  can be expressed by the following Mathematical Formula 6, and the frequency f z12  of the zero point generated by the zero point generation circuit  217  can be expressed by the following Mathematical Formula 7. 
     
       
         
           
             
               
                 
                   
                     f 
                     
                       Z 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       11 
                     
                   
                   = 
                   
                     1 
                     
                       2 
                       ⁢ 
                       π 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       
                         C 
                         3 
                       
                       × 
                       
                         R 
                         1 
                       
                     
                   
                 
               
               
                 
                   ( 
                   6 
                   ) 
                 
               
             
             
               
                 
                   
                     f 
                     
                       Z 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       12 
                     
                   
                   = 
                   
                     1 
                     
                       2 
                       ⁢ 
                       
                         πC 
                         4 
                       
                       × 
                       
                         R 
                         2 
                       
                     
                   
                 
               
               
                 
                   ( 
                   7 
                   ) 
                 
               
             
           
         
       
     
     In addition, by inserting the variables α and β expressed by the following Mathematical Formula 8 into Mathematical Formula 5, the frequencies f P11  and f P12  of the two poles generated by the pole generation circuit  215  can be expressed by the following Mathematical Formulas 9 and 10, respectively. 
     
       
         
           
             
               
                 
                   
                     α 
                     = 
                     
                       
                         
                           
                             ( 
                             
                               
                                 C 
                                 1 
                               
                               + 
                               
                                 C 
                                 3 
                               
                             
                             ) 
                           
                           ⁢ 
                           
                             R 
                             1 
                           
                         
                         + 
                         
                           
                             ( 
                             
                               
                                 C 
                                 2 
                               
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                                 C 
                                 4 
                               
                             
                             ) 
                           
                           ⁢ 
                           
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                             2 
                           
                         
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                             2 
                           
                           ⁢ 
                           
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                             1 
                           
                         
                       
                       
                         
                           { 
                           
                             
                               
                                 ( 
                                 
                                   
                                     C 
                                     1 
                                   
                                   + 
                                   
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                                     3 
                                   
                                 
                                 ) 
                               
                               ⁢ 
                               
                                 ( 
                                 
                                   
                                     C 
                                     2 
                                   
                                   + 
                                   
                                     C 
                                     4 
                                   
                                 
                                 ) 
                               
                             
                             + 
                             
                               
                                 C 
                                 2 
                               
                               ⁢ 
                               
                                 C 
                                 4 
                               
                             
                           
                           } 
                         
                         ⁢ 
                         
                           R 
                           1 
                         
                         ⁢ 
                         
                           R 
                           2 
                         
                       
                     
                   
                   , 
                   
                     
 
                   
                   ⁢ 
                   
                     β 
                     = 
                     
                       1 
                       
                         
                           { 
                           
                             
                               
                                 ( 
                                 
                                   
                                     C 
                                     1 
                                   
                                   + 
                                   
                                     C 
                                     3 
                                   
                                 
                                 ) 
                               
                               ⁢ 
                               
                                 ( 
                                 
                                   
                                     C 
                                     2 
                                   
                                   + 
                                   
                                     C 
                                     4 
                                   
                                 
                                 ) 
                               
                             
                             + 
                             
                               
                                 C 
                                 2 
                               
                               ⁢ 
                               
                                 C 
                                 4 
                               
                             
                           
                           } 
                         
                         ⁢ 
                         
                           R 
                           1 
                         
                         ⁢ 
                         
                           R 
                           2 
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   8 
                   ) 
                 
               
             
             
               
                 
                   
                     f 
                     
                       P 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       11 
                     
                   
                   = 
                   
                     
                       1 
                       
                         4 
                         ⁢ 
                         π 
                       
                     
                     [ 
                     
                       α 
                       + 
                       
                         
                           
                             α 
                             2 
                           
                           - 
                           
                             4 
                             ⁢ 
                             β 
                           
                         
                       
                     
                     ] 
                   
                 
               
               
                 
                   ( 
                   9 
                   ) 
                 
               
             
             
               
                 
                   
                     f 
                     
                       P 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       12 
                     
                   
                   = 
                   
                     
                       1 
                       
                         4 
                         ⁢ 
                         π 
                       
                     
                     [ 
                     
                       α 
                       - 
                       
                         
                           
                             α 
                             2 
                           
                           - 
                           
                             4 
                             ⁢ 
                             β 
                           
                         
                       
                     
                     ] 
                   
                 
               
               
                 
                   ( 
                   10 
                   ) 
                 
               
             
           
         
       
     
     It can be understood from Mathematical Formula 6 that, by adjusting the capacitance value of the capacitive element C 3  without decreasing the resistance value of the resistive element R 1 , the frequency f z11  of the zero point can be located on the lower frequency side than the unity gain frequency f UG . It can be understood from Mathematical Formula 7 that, by adjusting the capacitance value of the capacitive element C 4  without decreasing the resistance value of the resistive element R 2 , the frequency f z12  of the zero point can be located on the lower frequency side than the unity gain frequency f UG . At this time, according to the Mathematical Formulas 8 to 10, the frequencies f P11  and f P12  of the two poles are located on the lower frequency side than the frequencies f z11  and f z12  of the two zero points, respectively. 
     For example, the frequency characteristics of the semiconductor integrated circuit  200  are illustrated in  FIG. 8 .  FIG. 8A  illustrates the frequency characteristic of the gain of the semiconductor integrated circuit  200 , and  FIG. 8B  illustrates the frequency characteristic of the phase of the semiconductor integrated circuit  200 . In  FIG. 8A , the vertical axis represents the magnitude of the gain [dB], and the horizontal axis represents the magnitude of the frequency in log scale. In  FIG. 8B , the vertical axis represents the magnitude of the phase [deg] by arctan (Vout/Vin), and the horizontal axis represents the magnitude of the frequency in log scale. 
     The frequency at which the gain=0 [dB] in the frequency characteristic of the gain in  FIG. 8A  can be defined as a unity gain frequency f UG . As illustrated in the frequency characteristic of the phase illustrated in  FIG. 8B , the following relationship can be obtained.
 
Frequency of Pole f P11 &lt;Frequency of Pole f P12 &lt;Frequency of Zero Point f z11 &lt;Frequency of Zero Point f z12 &lt;Unity Gain Frequency f UG  
 
The frequency characteristic of the phase rotates to the minus side at the frequency f P11  of the pole and further rotates to the minus side at the frequency f P12  of the pole (the phase lags), and the frequency characteristic of the phase rotates to the plus side at the frequency f z11  of the zero point and further rotates to the plus side at the frequency f z12  of the zero point (the lagging of the phase is mitigated), so that the phase margin PM 2  at the unity gain frequency f UG  can be allowed to be easily increased to a positive value (PM 2 &gt;0). For example, in a case where C 1 =5 [pF], C 2 =50 [pF], C 3 =1 [pF], C 4 =2 [pF], R 1 =20 [kΩ], and R 2 =30 [kΩ], the phase margin PM 2  becomes PM 2 ≈+30.6 [deg].
 
     As illustrated in  FIGS. 8A and 8B , by generating a plurality (for example, two) of zero points that act to offset the poles, it is possible to further strengthen the effect of mitigating the leading of the phase. Therefore, the phase margin in the frequency characteristic of the semiconductor integrated circuit  200  can be further increased, and the negative feedback operation can be further stabilized. As a result, the degree of freedom of the load circuit  2  connected to the power supply output terminal TMout of the semiconductor integrated circuit  200  can be increased. 
     Alternatively, in Modified Example, a plurality of zero point generation circuits is provided in the filter circuit so as to form a plurality of zero points. However, it can be considered that a plurality of zero points can also be formed by changing the configuration of the zero point generation circuit itself. 
     On the basis of the idea, the semiconductor integrated circuit  300  can be configured, for example, as illustrated in  FIG. 9 .  FIG. 9  is a circuit diagram illustrating a configuration of the semiconductor integrated circuit  300  according to another Modified Example of the embodiment. 
     The semiconductor integrated circuit  300  illustrated in  FIG. 9  has a filter circuit  312  instead of the filter circuit  112  (refer to  FIG. 2 ). The filter circuit  312  is different in terms of the configuration of the zero point generation circuit. That is, the filter circuit  312  has a zero point generation circuit  314  and a pole generation circuit  315  instead of the zero point generation circuit  114  and the pole generation circuit  115  (refer to  FIG. 2 ) and further has the low-pass filter  216 . 
     The low-pass filter  216  is arranged between the low-pass filter  113  and the power supply output terminal TMout. The low-pass filter  216  has the resistive element R 2  and the capacitive element C 2 . The resistive element R 2  is arranged between the low-pass filter  113  and the power supply output terminal TMout. One end of the resistive element R 2  is electrically connected to the other end of the resistive element R 1  and one end of the capacitive element C 1 , and the other end of the resistive element R 2  is electrically connected to one end of the capacitive element C 2  and is electrically connected to the power supply output terminal TMout via the output node  112   o.    
     The capacitive element C 2  is arranged between the resistive element R 2  and the power supply output terminal TMout. The capacitive element C 2  is shunt-connected to a path extending from, the input node  112   i  through the resistive elements R 1  and R 2  to the output node  112   o . One end of the capacitive element C 2  is electrically connected to the other end of the resistive element R 2  and the output node  112   o , and the other end of the capacitive element C 2  is electrically connected to the ground potential. 
     The zero point generation circuit  314  is arranged between the charge pump circuit  111  and the power supply output terminal TMout. The zero point generation circuit  314  has the resistive element (first resistive element) R 1 , the resistive element (second resistive element) R 2 , and the capacitive element (first capacitive element.) C 3 . The pole generation circuit  315  has the resistive element R 1 , the resistive element R 2 , the capacitive element C 3 , the capacitive element C 1 , and the capacitive element C 2 . The zero point generation circuit  314  and the pole generation circuit  315  share the resistive element R 3 , the resistive element R 2 , and the capacitive element C 3  with each other. The zero point generation circuit  314  shares the resistive element R 1  with the low-pass filter  113  and shares the resistive element R 2  with the low-pass filter  216 . The pole generation circuit  315  includes low-pass filters  113  and  216 . 
     The capacitive element C 3  is arranged in parallel to the series connection of the plurality of resistive elements R 1  and R 2  between the charge pump circuit  111  and the power supply output terminal TMout. The series connection of the plurality of resistive elements R 1  and R 2  and the capacitive element C 3  are connected in parallel to each other between the input node  112   i  and the intermediate node  112   m . One end of the capacitive element C 3  is electrically connected to the charge pump circuit  111  via the input node  112   i , and the other end of the capacitive element C 3  is electrically connected to the power supply output terminal TMout via the output node  112   o.    
     More specifically, in a case where the parasitic capacitance in the load circuit  2  (refer to  FIG. 1 ) and the parasitic resistance and the parasitic capacitance in the negative feedback circuit  121  can be neglected, the open-loop transfer function of the negative feedback loop of the charge pump circuit  111 →the filter circuit  312 →the negative feedback circuit  121 →the oscillation circuit.  122 →the charge pump circuit  111  can be expressed approximately by the following Mathematical Formula 11. 
     
       
         
           
             
               
                 
                   
                       
                   
                   ⁢ 
                   
                     ( 
                     11 
                     ) 
                   
                 
               
             
             
               
                 
                   
                     G 
                     ⁡ 
                     
                       ( 
                       s 
                       ) 
                     
                   
                   = 
                   
                     
                       
                         C 
                         3 
                       
                       
                         
                           C 
                           2 
                         
                         + 
                         
                           C 
                           3 
                         
                       
                     
                     × 
                   
                 
               
             
             
               
                 
                   
                       
                   
                   ⁢ 
                   
                     
                       
                         s 
                         2 
                       
                       + 
                       
                         s 
                         ⁢ 
                         
                           
                             
                               C 
                               3 
                             
                             ⁡ 
                             
                               ( 
                               
                                 
                                   R 
                                   1 
                                 
                                 + 
                                 
                                   R 
                                   2 
                                 
                               
                               ) 
                             
                           
                           
                             
                               C 
                               1 
                             
                             ⁢ 
                             
                               C 
                               3 
                             
                             ⁢ 
                             
                               R 
                               1 
                             
                             ⁢ 
                             
                               R 
                               2 
                             
                           
                         
                       
                       + 
                       
                         1 
                         
                           
                             C 
                             1 
                           
                           ⁢ 
                           
                             C 
                             3 
                           
                           ⁢ 
                           
                             R 
                             1 
                           
                           ⁢ 
                           
                             R 
                             2 
                           
                         
                       
                     
                     
                       
                         s 
                         2 
                       
                       + 
                       
                         s 
                         ⁢ 
                         
                           
                             
                               
                                 ( 
                                 
                                   
                                     C 
                                     2 
                                   
                                   + 
                                   
                                     C 
                                     3 
                                   
                                 
                                 ) 
                               
                               ⁢ 
                               
                                 ( 
                                 
                                   
                                     R 
                                     1 
                                   
                                   + 
                                   
                                     R 
                                     2 
                                   
                                 
                                 ) 
                               
                               ⁢ 
                               
                                 R 
                                 2 
                               
                             
                             + 
                             
                               
                                 C 
                                 1 
                               
                               ⁢ 
                               
                                 R 
                                 1 
                               
                             
                           
                           
                             
                               
                                 C 
                                 1 
                               
                               ⁡ 
                               
                                 ( 
                                 
                                   
                                     C 
                                     2 
                                   
                                   + 
                                   
                                     C 
                                     3 
                                   
                                 
                                 ) 
                               
                             
                             ⁢ 
                             
                               R 
                               1 
                             
                             ⁢ 
                             
                               R 
                               2 
                             
                           
                         
                       
                       + 
                       
                         1 
                         
                           
                             
                               C 
                               1 
                             
                             ⁡ 
                             
                               ( 
                               
                                 
                                   C 
                                   2 
                                 
                                 + 
                                 
                                   C 
                                   3 
                                 
                               
                               ) 
                             
                           
                           ⁢ 
                           
                             R 
                             1 
                           
                           ⁢ 
                           
                             R 
                             2 
                           
                         
                       
                     
                   
                 
               
             
           
         
       
     
     By inserting the variables α 1  and β 1 , expressed by the following Mathematical Formula 12 into Mathematical Formula 11, the frequencies f z21  and f z22  of the two zero points generated by the zero point generation circuit  314  can be expressed by the following Mathematical Formulas 13 and 14. 
     
       
         
           
             
               
                 
                   
                     
                       α 
                       1 
                     
                     = 
                     
                       
                         
                           C 
                           3 
                         
                         ⁡ 
                         
                           ( 
                           
                             
                               R 
                               1 
                             
                             + 
                             
                               R 
                               2 
                             
                           
                           ) 
                         
                       
                       
                         
                           C 
                           1 
                         
                         ⁢ 
                         
                           C 
                           3 
                         
                         ⁢ 
                         
                           R 
                           1 
                         
                         ⁢ 
                         
                           R 
                           2 
                         
                       
                     
                   
                   , 
                   
                     
                       β 
                       1 
                     
                     = 
                     
                       1 
                       
                         
                           C 
                           1 
                         
                         ⁢ 
                         
                           C 
                           3 
                         
                         ⁢ 
                         
                           R 
                           1 
                         
                         ⁢ 
                         
                           R 
                           2 
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   12 
                   ) 
                 
               
             
             
               
                 
                   
                     f 
                     
                       Z 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       21 
                     
                   
                   = 
                   
                     
                       1 
                       
                         4 
                         ⁢ 
                         π 
                       
                     
                     [ 
                     
                       
                         α 
                         1 
                       
                       + 
                       
                         
                           
                             α 
                             1 
                             2 
                           
                           - 
                           
                             4 
                             ⁢ 
                             
                               β 
                               1 
                             
                           
                         
                       
                     
                     ] 
                   
                 
               
               
                 
                   ( 
                   13 
                   ) 
                 
               
             
             
               
                 
                   
                     f 
                     
                       Z 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       22 
                     
                   
                   = 
                   
                     
                       1 
                       
                         4 
                         ⁢ 
                         π 
                       
                     
                     [ 
                     
                       
                         α 
                         1 
                       
                       - 
                       
                         
                           
                             α 
                             1 
                             2 
                           
                           - 
                           
                             4 
                             ⁢ 
                             
                               β 
                               1 
                             
                           
                         
                       
                     
                     ] 
                   
                 
               
               
                 
                   ( 
                   14 
                   ) 
                 
               
             
           
         
       
     
     In addition, by inserting the variables α 2  and β 2  expressed by the following Mathematical Formula 15 into Mathematical Formula 11, the frequencies f P21  and f P22  of the two poles generated by the pole generation circuit  315  can be expressed by the following Mathematical Formulas 16 and 17, respectively. 
     
       
         
           
             
               
                 
                   
                     
                       α 
                       2 
                     
                     = 
                     
                       
                         
                           
                             ( 
                             
                               
                                 C 
                                 2 
                               
                               + 
                               
                                 C 
                                 3 
                               
                             
                             ) 
                           
                           ⁢ 
                           
                             ( 
                             
                               
                                 R 
                                 1 
                               
                               + 
                               
                                 R 
                                 2 
                               
                             
                             ) 
                           
                           ⁢ 
                           
                             R 
                             2 
                           
                         
                         + 
                         
                           
                             C 
                             1 
                           
                           ⁢ 
                           
                             R 
                             1 
                           
                         
                       
                       
                         
                           
                             C 
                             1 
                           
                           ⁡ 
                           
                             ( 
                             
                               
                                 C 
                                 2 
                               
                               + 
                               
                                 C 
                                 3 
                               
                             
                             ) 
                           
                         
                         ⁢ 
                         
                           R 
                           1 
                         
                         ⁢ 
                         
                           R 
                           2 
                         
                       
                     
                   
                   , 
                   
                     
 
                   
                   ⁢ 
                   
                     
                       β 
                       2 
                     
                     = 
                     
                       1 
                       
                         
                           
                             C 
                             1 
                           
                           ⁡ 
                           
                             ( 
                             
                               
                                 C 
                                 2 
                               
                               + 
                               
                                 C 
                                 3 
                               
                             
                             ) 
                           
                         
                         ⁢ 
                         
                           R 
                           1 
                         
                         ⁢ 
                         
                           R 
                           2 
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   15 
                   ) 
                 
               
             
             
               
                 
                   
                     f 
                     
                       P 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       21 
                     
                   
                   = 
                   
                     
                       1 
                       
                         4 
                         ⁢ 
                         π 
                       
                     
                     [ 
                     
                       
                         α 
                         2 
                       
                       + 
                       
                         
                           
                             α 
                             2 
                             2 
                           
                           - 
                           
                             4 
                             ⁢ 
                             
                               β 
                               2 
                             
                           
                         
                       
                     
                     ] 
                   
                 
               
               
                 
                   ( 
                   16 
                   ) 
                 
               
             
             
               
                 
                   
                     f 
                     
                       P 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       22 
                     
                   
                   = 
                   
                     
                       1 
                       
                         4 
                         ⁢ 
                         π 
                       
                     
                     [ 
                     
                       
                         α 
                         2 
                       
                       - 
                       
                         
                           
                             α 
                             2 
                             2 
                           
                           - 
                           
                             4 
                             ⁢ 
                             
                               β 
                               2 
                             
                           
                         
                       
                     
                     ] 
                   
                 
               
               
                 
                   ( 
                   17 
                   ) 
                 
               
             
           
         
       
     
     It can be understood from Mathematical Formula 13 that, by adjusting the capacitance value of the capacitive element C 3  without decreasing the resistance values of the resistive elements R 1  and R 2  or decreasing the capacitance value of the capacitive element C, the frequency f z21  of the zero point can be located on the lower frequency side than the unity gain frequency f UG . It can be understood from Mathematical Formula 14 that, by adjusting the capacitance value of the capacitive element C 3  without decreasing the resistance values of the resistive elements R 1  and R 2  or decreasing the capacitance value of the capacitive element C 1 , the frequency f z22  of the zero point can be located on the lower frequency side than the unity gain frequency f UG . At this time, according to Mathematical Formulas 15 to 17, the frequencies f P21  and f P22  of the two poles are located on the lower frequency side than the frequencies f z21  and f z22  of the two zero points, respectively. 
     For example, the frequency characteristics of the semiconductor integrated circuit  300  are illustrated in  FIG. 10 .  FIG. 10A  illustrates the frequency characteristic of the gain of the semiconductor integrated circuit  300 , and  FIG. 10B  illustrates the frequency characteristic of the phase of the semiconductor integrated circuit  300 . In  FIG. 10A , the vertical axis represents the magnitude of the gain [dB], and the horizontal axis represents the magnitude of the frequency in log scale. In  FIG. 10B , the vertical axis represents the magnitude of the phase [deg] by arctan (Vout/Vin), and the horizontal axis represents the magnitude of the frequency in log scale. 
     The frequency at which the gain=0 [dB] in the frequency characteristic of the gain in  FIG. 10A  can be defined as a unity gain frequency f UG . As illustrated in the frequency characteristic of the phase illustrated in  FIG. 10B , the following relationship can be obtained.
 
Frequency of Pole f P21 &lt;Frequency of Pole f P22 &lt;Frequency of Zero Point f z21 &lt;Frequency of Zero Point f z22 &lt;Unity Gain Frequency f UG  
 
The frequency characteristic of the phase rotates to the minus side at the frequency f P21  of the pole and further rotates to the minus side at the frequency f P22  of the pole (the phase lags), and the frequency characteristic of the phase rotates to the plus side at the frequency f z21  of the zero point and further rotates to the plus side at the frequency f z22  of the zero point (the lagging of the phase is mitigated), so the phase margin PM 3  at the unity gain frequency f UG  can be allowed to be easily increased to a positive value (PM 3 &gt;0). For example, in a case where C 1 =5 [PF], C 2 =50 [pF], C 3 =2 [pF], R 1 =20 [kΩ], and R 2 =30 [kΩ], the phase margin PM 3  becomes PM 3 ≈+62.7 [deg].
 
     As illustrated in  FIGS. 10A and 10B , by generating a plurality (for example, two) of zero points to mitigate phase rotation by the poles, it is possible to further strengthen the effect of mitigating the leading of the phase. Therefore, the phase margin in the frequency characteristic of the semiconductor integrated circuit  300  can be further increased, and the negative feedback operation can be further stabilized. As a result, the design of the load circuit  2  connected to the power supply output terminal TMout of the semiconductor integrated circuit  300  can become more flexible. 
     While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fail within the scope and spirit of the inventions.