Patent Publication Number: US-11664794-B2

Title: Substrate-enhanced comparator and electronic device

Description:
CROSS REFERENCE TO RELATED APPLICATION 
     This is a Sect. 371 National Stage of PCT International Application No. PCT/CN2020/070588, filed on Jan. 7, 2020, which claims the benefit of priority to Chinese Patent Application No. CN 2019103821436, entitled “substrate-enhanced comparator and electronic device”, filed with CNIPA on May 9, 2019, the disclosure of which is incorporated herein by reference in its entirety. 
     FIELD OF TECHNOLOGY 
     The present disclosure generally relates to technical field of mixed analog and digital integrated circuits, and in particular to a substrate-enhanced comparator and electronic device. 
     BACKGROUND 
     A comparator is an important component module of many integrated circuits (IC), such as analog-to-digital converter (ADC), operational transconductance amplifier (OTA), voltage reference source (VR) and clock data recovery circuit (CDR), which generates corresponding output by detecting differential input voltage and displays input voltage information of large amplitude. In modern communication systems, a low-voltage, high-speed comparator architecture is urgently needed due to the constant demand for lighter weight and smaller size in portable devices. 
     However, as the size of advanced CMOS processes has shrunk (to 40 nm and 28 nm, or even smaller), the supply voltage of the core circuit has followed suit, but the threshold voltage of the MOS cannot be reduced in the same proportion, which limits the common-mode input range of the comparator; more importantly, limited by the supply voltage and process characteristic frequency, the lower the supply voltage, the slower the latch in the comparator and it is unlikely to keep the comparator operating at high speed under low-voltage conditions (i.e., a supply voltage below 1.2V can be considered low-voltage). 
     SUMMARY 
     The present disclosure provides a substrate-enhanced comparator and electronic device for solving the problem that the speed of the latch is limited by the restricted supply voltage and the process characteristic frequency, resulting in the comparator not being able to achieve high speed in a low-voltage condition. 
     The present disclosure provides a substrate-enhanced comparator, including 
     a cross-coupled latch, for connecting input signals to the gate of a cross-coupled MOS transistor to form a first input of the latch; 
     output buffers, connected to the cross-coupled latch, for amplifying output signals of the latch; and 
     AC couplers, each connected to one of the output buffers, for receiving and further amplifying the output signals of the latch, and coupling the output signals to substrates of the cross-coupled MOS transistors for forming second inputs of the latch. 
     The cross-coupled latch is further configured for output signal regenerative latching based on input signals sampled at the first input and input signals sampled at the second input. 
     The present disclosure further provides an electronic device including a substrate-enhanced comparator as described above. 
     As described above, the substrate-enhanced comparator and electronic device of the present disclosure have the following beneficial effects: 
     The present disclosure introduces an additional substrate input in the cross-coupled structure of the conventional latch as the second input of the latch, which not only introduce the body transconductance of the cross-coupled MOS transistor into the input node, but also enhances the positive feedback capability and increases speed of the latch. 
     The substrate enhancement latching technology can effectively improve the latch sub-stable latching speed, break through the bottleneck of traditional latches that their latch regeneration speed is limited by the process characteristic frequency and supply voltage, and realize high-speed latches even in an advanced low-voltage process. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG.  1    shows a schematic diagram of a substrate-enhanced comparator provided by the present disclosure. 
         FIG.  2    shows a schematic diagram of an embodiment of a substrate-enhanced comparator provided by the present disclosure. 
         FIG.  3    shows a circuit diagram of a substrate-enhanced comparator provided by the present disclosure. 
         FIG.  4    shows a timing diagram of a substrate-enhanced comparator based on  FIG.  3    provided by the present disclosure. 
     
    
    
     REFERENCE NUMERALS 
     
         
         
           
               1  Cross-coupled latch 
               2  Output buffer 
               3  AC coupler 
               4  Substrate common-mode resettor 
           
         
       
    
     DETAILED DESCRIPTION 
     The following describes the implementation of the present disclosure through specific examples, and those skilled in the art can easily understand other advantages and effects of the present disclosure from the content disclosed in this specification. The present disclosure can also be implemented or applied through other different specific embodiments. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present disclosure. It should be noted that the following embodiments and the features in the embodiments can be combined with each other if no conflict will result. 
     It should be noted that the drawings provided in this disclosure only illustrate the basic concept of the present disclosure in a schematic way, so the drawings only show the components related to the present disclosure. The drawings are not necessarily drawn according to the number, shape and size of the components in actual implementation; during the actual implementation, the type, quantity and proportion of each component can be changed as needed, and the components&#39; layout may also be more complicated. 
     Referring to  FIG.  1   , the present disclosure provides a schematic diagram of a substrate-enhanced comparator including: 
     a cross-coupled latch  1 , for connecting input signals to the gate of a cross-coupled MOS transistor to form a first input of the latch; 
     output buffers  2 , connected to the cross-coupled latch for amplifying output signals of the latch; 
     AC couplers  3 , each connected to one of the output buffers, for receiving and further amplifying the output signals of the latch, and coupling the output signals to substrates of the cross-coupled MOSs forming second inputs of the latch; 
     The cross-coupled latch is further configured for output signal regenerative latching based on input signals sampled at the first input and input signals sampled at the second input; 
     The substrates of the cross-coupled MOS transistors are made by a deep well process, for isolating the substrates of the MOS transistors from the outside to make its substrate coupling noise smaller and prevent crosstalk or mutual influence. The output buffers amplify the output signals in the same or opposite direction to ensure that cross-coupled MOS transistors on the same side have input signals with the same phase on their substrates, and on their gates. For example, the transistor P 2  and transistor N 3  are on the same side, and the transistor P 3  and transistor N 4  are on the other side, i.e., input signals on the substrate and the gate of the transistor P 2  are in the same phase, input signals on the substrate and the gate of the transistor N 3  are in the same phase, and so on. 
     Specifically, corresponding output node and input node of the cross-coupled latch are in the same position during resetting and latching phases. When the cross-coupled latch is in a sampling phase, the input node receives input signals, and when the cross-coupled latch is in the latching phase, the output node performs positive feedback output signal regeneration. 
     In the present disclosure, the latch, as the core unit of the traditional comparator, uses positive feedback for regenerative latching of sub-stable signals, while almost all current latches are designed using cross-coupled inverters, and the latching speed of this kind of structure is limited by the process characteristic frequency. With the development of advanced process technology, the power supply voltage of semiconductor chips is getting lower and lower, severely limiting latching speed of the traditional latch. 
     The present disclosure introduces an additional substrate input in the cross-coupled structure of the conventional latch as the second input of the latch, which not only introduce the body transconductance of the cross-coupled MOS transistor into the input node, but also enhances the positive feedback capability and increases speed of the latch. 
     Please refer to  FIG.  2    for a schematic diagram of an embodiment of a substrate-enhanced comparator provided by the present disclosure, the substrate-enhanced comparator including: 
     substrate common-mode resettors connected to the cross-coupled latch, and AC couplers, respectively, for common-mode resetting of the AC couplers and the substrates of the cross-coupled MOS transistors during a resetting phase. 
     The substrate common-mode resettors reset output nodes of the latch and the substrates of the cross-coupled MOS transistors during a resetting phase, with a corresponding reset voltage connected to different AC couplers for resetting according to respective transconductance of each NMOS transistor and PMOS transistor of the cross-coupled MOS transistors, and as long as the reset voltage does not make PN junctions of corresponding MOS transistor forward-conducting. The lower the reset voltage corresponding to PMOS transistors, the better; the higher the reset voltage corresponding to NMOS transistors, the better. 
     The disclosure introduces additional substrate inputs in the cross-coupled structure of the traditional latch as second inputs of the latch, which not only introduce body transconductance of the cross-coupled MOS transistors into the input nodes, but also enhances the positive feedback capability; and introduces common mode signals in the substrates of the cross-coupled MOS transistors to lower the threshold of the cross-coupled MOS transistors, thus increasing the effective transconductance and accelerating the latch speed. 
     The substrate enhancement latching technology of the present disclosure can effectively improve the latch sub-stable latching speed, break through the bottleneck of traditional latches that their latch regeneration speed is limited by the process characteristic frequency and supply voltage, and realize high-speed latches even in an advanced low-voltage process. 
     As shown in  FIG.  3   , showing an preferred embodiment based on  FIG.  2   , in which transistors P 1 , P 2 , P 3 , N 1 , N 2 , N 3  and N 4  constitute a cross-coupled latch LatchT; transistors P 4  and N 5 , and P 5  and N 6  constitute push-pull amplifiers as output buffers (first output buffer  21  and second output buffer  21 ); transistors N 7  and N 9 , and N 8  and N 10  constitute substrate common-mode resettors SUBR (first substrate common-mode resettor  41  and second substrate common-mode resettor  42 ); capacitors C 1 , C 2 , C 3 , and C 4  constitute AC couplers (ACC) (first AC coupler  31  and second AC coupler  32 ). 
     Specifically, the cross-coupled latch includes transistors P 1 , P 2 , P 3 , N 1 , N 2 , N 3 , and N 4 , a gate of the transistor P 1  is connected to a first clock signal, a source of the transistor P 1  is connected to a supply voltage, a drain of the transistor P 1  is connected to sources of the transistors P 2  and P 3  respectively; a first input signal is connected to a first output node formed by connecting a drain of the transistor P 2 , a gate of the transistor P 3 , the first input signal, drains of the transistors N 2 , N 3 , and a gate of the transistor N 4 ; a second input signal is connected to a second output node formed by connecting a gate of the transistor P 2 , a drain of the transistor P 3 , a source of the transistor N 2 , a gate of the transistor N 3  and a drain of the transistor N 4 ; a gate of the transistor N 1  is connected to a second clock signal, a gate of the transistor N 2  is connected to a third clock signal, a drain of the transistor N 2  is connected to sources of the transistors N 3  and N 4  respectively, a source of transistor N 1  is grounded; substrates of the transistor P 2  and the transistor N 3  are interconnected, which are designated as substrates on a first side of the cross-coupled MOS transistors; substrates of the transistor P 3  and the transistor N 4  are interconnected, which are designated as substrates on a second side of the cross-coupled MOS transistors. 
     The output buffers  2  include a first output buffer  21  including transistors P 4  and N 5 , and a second output buffer  22  including transistors P 5  and N 6 . In the first output buffer  21 , gates of the transistors P 4  and N 5  are connected to an output of the cross-coupled latch, a source of transistor P 4  is connected to a supply voltage, a source of the transistor N 5  is grounded, drains of the transistor P 4  and N 5  are interconnected as an amplifying output of the first output buffer  21 ; in the second output buffer  22 , gates of the transistors P 5  and N 6  are connected to the other output of the cross-coupled latch, a source of the transistor P 5  is connected to a supply voltage, a source of the transistor N 6  is grounded, drains of the transistors P 5  and N 6  are interconnected as an amplifying output of the second output buffer  22 . 
     The substrate common-mode resettors  4  include a first substrate common-mode resettor  41  including transistors N 7  and N 9  and a second substrate common-mode resettor  42  including transistors N 8  and N 10 ; gates of the transistors N 7  and N 9  in the first substrate common-mode resettor  41  are connected to a third clock signal, a drain of the transistor N 7  is connected to an output of the cross-coupled latch, a source of the transistor N 9  is connected to a common mode level, a source of the transistor N 7  and a drain of the transistor N 9  serve as two outputs of the first substrate common mode resettor  41 ; gates of the transistors N 8  and N 10  in the second substrate common mode resettor  42  are connected to the third clock signal, a drain of the transistor N 8  is connected to another output of the cross-coupled latch, a source of transistor N 10  is connected to a common mode level, and a source of the transistor N 8 , and a drain of the transistor N 10  serve as two outputs of the second substrate common-mode resettor  42 . 
     The AC couplers  3  include a first AC coupler  31  including a first capacitor and a third capacitor, a second AC coupler  32  including a second capacitor and a fourth capacitor. When the comparator does not have a substrate common-mode resettor, the AC couplers are connected as follows: 
     upper plates of the first capacitor C 1  and third capacitor C 3  are connected to an output of the first output buffer  21 , and a lower plate of the first capacitor C 1  is connected to a first substrate on the first side of the cross-coupled MOS transistors, and the lower plate of the third capacitor C 3  is connected to a second substrate on the first side of the cross-coupled MOS transistors; upper plates of the second capacitor C 2  and fourth capacitor C 4  are connected to an output of the second output buffer  22 , a lower plate of the second capacitor C 2  is connected to a first substrate on the second side of the cross-coupled MOS transistors, and a lower plate of the fourth capacitor C 4  is connected to a second substrate on the second side of the cross-coupled MOS transistors. When the comparator has a substrate common mode resettor, the AC couplers are connected as follows. 
     upper plates of the first capacitor and third capacitor are connected to an output of the first output buffer and a first output of the first substrate common-mode resettor, and a lower plate of the first capacitor is connected to a first substrate on the first side of the cross-coupled MOS transistors and a second output of the first substrate common-mode resettor, and the lower plate of the third capacitor is connected to a second substrate on the first side of the cross-coupled MOS transistors and the second output of the first substrate common-mode resettor; upper plates of the second and fourth capacitors are connected to an output of the second output buffer and a first output of the second substrate common-mode resettor, a lower plate of the second capacitor is connected to a first substrate on the second side of the cross-coupled MOS transistors and a second output of the second substrate common-mode resettor, and a lower plate of the fourth capacitor is connected to a second substrate on the second side of the cross-coupled MOS transistors and the second output of the second substrate common-mode resettor. 
     The first capacitor C 1  and the second capacitor C 2  have the same capacitance and provide the reset voltage to the transistors P 2  and P 3 , respectively, and the third capacitor C 3  and the fourth capacitor C 4  have the same capacitance and provide the reset voltage to the transistors N 3  and N 4 , respectively. 
     As shown in  FIG.  4   , which is a timing diagram of an embodiment based on  FIG.  3   , when the third clock signal CLKrst is a high level, switches N 2 , N 7 , N 8 , N 9  and N 10  of the substrate common-mode resettor SUBR are on, output nodes VP and VN of the latch are shorted, the upper plates of AC coupling capacitors C 1  and C 2  are reset to the latch output common-mode, and their lower plates are connected to the common-mode level Vbcm. 
     When the first clock signal CLKSP 1  is a high level and the second clock signal CLKSP 2  is a low level, the latch enters the sampling phase and the switches P 1 , N 1 , N 2 , N 7 , N 8 , N 9  and N 10  are disconnected, and the output nodes VP and VN of the latch receive input signals, which first acts on the gates of the cross-coupled transistors P 2 , P 3 , N 3  and N 4  to form the first inputs of the latch; voltage at the output nodes of the latch acts on the upper plates of the AC coupling capacitors C 1 , C 2 , C 3  and C 4  through buffers, and then on the substrates of the cross-coupled transistors P 2 , P 3 , N 3  and N 4 , forming the second inputs of the latch. 
     When the first clock signal CLKSP 1  is a low level and the second clock signal CLKSP 2  is a high level, the transistors P 1  and N 1  are turned on and the latch enters the latching phase and regenerates the output signals based on the input signals sampled from the first inputs, i.e., the output nodes VP and VN, and the input signals sampled from the second inputs formed by the substrates of the cross-coupled transistors P 2 , P 3 , N 3  and N 4 . 
     The first clock signal CLKSP 1  and the second clock signal CLKSP 2  are equal in value and opposite in phase. 
     During the latching process, due to the adoption of the cross-coupled transistors P 2 , P 3 , N 3  and N 4  as the second inputs, the body transconductance is increased from that of the conventional latch, effectively speeding up the latch regeneration; on the other hand, due to the lower plates of the AC coupling capacitors C 1 , C 2 , C 3  and C 4  being connected to the reset level Vbcm during the resetting phase, threshold voltages of the cross-coupled transistors P 2 , P 3 , N 3  and N 4  in the sampling and latching process are reduced to further increase the sub-stable effective transconductance and speed of the latch. 
     The present disclosure also provides an electronic device including a substrate-enhanced comparator described above, which may be a circuit, an analog-to-digital converter, an analog-to-digital conversion system, etc. 
     In this embodiment, the circuit includes the above-mentioned substrate-enhanced comparator. 
     In this embodiment, the analog-to-digital converter includes: a sampling capacitor array, a dynamic comparator, and a successive approximation logic circuits. The sampling capacitor array is used to sample an analog input signal and input the sampled signal to a comparator. The sampled signal, after processing by the comparator, is input to the successive approximation logic circuit in order to output a digital signal. The comparator is the substrate-enhanced comparator described in any of the above embodiments. 
     In this embodiment, the analog-to-digital conversion system includes: an analog-to-digital converter, a digital processing and storage module circuit, and a switching array circuit, the switching array circuit being used to control the analog-to-digital converter by turning on/off to input an analog signal as well as a DC out-of-tune calibration of the analog-to-digital converter, the analog-to-digital converter including a sampling capacitor array, a comparator, and a successive approximation logic circuit, the sampling capacitor array being used to sampling an analog input signal and inputting the sampled signal into a comparator, where the sampled signal, after processing by the comparator, is input to the successive approximation logic circuit in order to output a digital signal, the comparator being a substrate-enhanced comparator described in any of the above embodiments. 
     In summary, the disclosure introduces additional substrate inputs in the cross-coupled structure of the traditional latch as second inputs of the latch, which not only introduce body transconductance of the cross-coupled MOS transistors into the input nodes, but also enhances the positive feedback capability; and introduces common mode signals in the substrates of the cross-coupled MOS transistors to lower the threshold of the cross-coupled MOS transistors, thus increasing the effective transconductance and accelerating the latch speed. The substrate enhancement latching technology can effectively improve the latch sub-stable latching speed, break through the bottleneck of traditional latches that their latch regeneration speed is limited by the process characteristic frequency and supply voltage, and realize high-speed latches even in an advanced low-voltage process. Therefore, the present disclosure effectively overcomes various shortcomings of the prior art and has a high value for industrial application. 
     The above-mentioned embodiments only exemplarily illustrate the principles and effects of the present disclosure, but are not used to limit the present disclosure. Any person skilled in the art may modify or change the above embodiments without violating the spirit and scope of the present disclosure. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical concepts disclosed by the present disclosure should still be covered by the attached claims of the present disclosure.