Patent Publication Number: US-7593270-B2

Title: Integrated circuit device and electronic instrument

Description:
Japanese Patent Application No. 2005-192683, filed on Jun. 30, 2005, is hereby incorporated by reference in its entirety. 
     BACKGROUND OF THE INVENTION 
     The present invention relates to an integrated circuit device and an electronic instrument. 
     In recent years, an increase in resolution of a display panel provided in an electronic instrument has been demanded accompanying a widespread use of electronic instruments. Therefore, a driver circuit which drives a display panel is required to exhibit high performance. However, since many types of circuits are necessary for a high-performance driver circuit, the circuit scale and the circuit complexity tend to be increased in proportion to an increase in resolution of a display panel. Therefore, since it is difficult to reduce the chip area of the driver circuit while maintaining the high performance or providing another function, manufacturing cost cannot be reduced. 
     A high-resolution display panel is also provided in a small electronic instrument, and high performance is demanded for its driver circuit. However, the circuit scale cannot be increased to a large extent since a small electronic instrument is limited in space. Therefore, since it is difficult to reduce the chip area while providing high performance, a reduction in manufacturing cost or provision of another function is difficult. 
     The invention of JP-A-2001-222276 cannot solve the above problems. 
     SUMMARY 
     A first aspect of the invention relates to an integrated circuit device having a display memory which stores data for at least one frame displayed in a display panel which has a plurality of scan lines and a plurality of data lines, 
     wherein the display memory includes a plurality of RAM blocks, each of the RAM blocks including a plurality of wordlines, a plurality of bitlines, a plurality of memory cells, and a data read control circuit, and 
     wherein each of the RAM blocks is disposed along a first direction in which the bitlines extend. 
     A second aspect of the invention relates to an electronic instrument, comprising the above-described integrated circuit device; and a display panel. 
    
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING 
         FIGS. 1A and 1B  are diagrams showing an integrated circuit device according to one embodiment of the invention. 
         FIG. 2A  is a diagram showing a part of a comparative example for the embodiment, and  FIG. 2B  is a diagram showing a part of the integrated circuit device according to the embodiment. 
         FIGS. 3A and 3B  are diagrams showing a configuration example of the integrated circuit device according to the embodiment. 
         FIG. 4  is a configuration example of a display memory according to the embodiment. 
         FIG. 5  is a cross-sectional diagram of the integrated circuit device according to the embodiment. 
         FIGS. 6A and 6B  are diagrams showing a configuration example of a data line driver. 
         FIG. 7  is a configuration example of a data line driver cell according to the embodiment. 
         FIG. 8  is a diagram showing a comparative example according to the embodiment. 
         FIGS. 9A to 9D  are diagrams illustrative of the effect of a RAM block according to the embodiment. 
         FIG. 10  is a diagram showing the relationship of the RAM blocks according to the embodiment. 
         FIGS. 11A and 11B  are diagrams illustrative of reading of data from the RAM block. 
         FIG. 12  is a diagram illustrative of data latching of a divided data line driver according to the embodiment. 
         FIG. 13  is a diagram showing the relationship between the data line driver cells and sense amplifiers according to the embodiment. 
         FIG. 14  is another configuration example of the divided data line drivers according to the embodiment. 
         FIGS. 15A and 15B  are diagrams illustrative of an arrangement of data stored in the RAM block. 
         FIG. 16  is another configuration example of the divided data line drivers according to the embodiment. 
         FIGS. 17A to 17C  are diagrams showing a configuration of a memory cell according to the embodiment. 
         FIG. 18  is a diagram showing the relationship between horizontal cells shown in  FIG. 17B  and the sense amplifiers. 
         FIG. 19  is a diagram showing the relationship between a memory cell array using the horizontal cells shown in  FIG. 17B  and the sense amplifiers. 
         FIG. 20  is a block diagram showing memory cell arrays and peripheral circuits in an example in which two RAMs are adjacent to each other as shown in  FIG. 3A . 
         FIG. 21A  is a diagram showing the relationship between the sense amplifier and a vertical memory cell according to the embodiment, and  FIG. 21B  is a diagram showing a selective sense amplifier SSA according to the embodiment. 
         FIG. 22  is a diagram showing the divided data line drivers and the selective sense amplifiers according to the embodiment. 
         FIG. 23  is an arrangement example of the memory cells according to the embodiment. 
         FIGS. 24A and 24B  are timing charts showing the operation of the integrated circuit device according to the embodiment. 
         FIG. 25  is another arrangement example of data stored in the RAM block according to the embodiment. 
         FIGS. 26A and 26B  are timing charts showing another operation of the integrated circuit device according to the embodiment. 
         FIG. 27  is still another arrangement example of data stored in the RAM block according to the embodiment. 
         FIG. 28  is a diagram showing a modification according to the embodiment. 
         FIG. 29  is a timing chart illustrative of the operation of the modification according to the embodiment. 
         FIG. 30  is an arrangement example of data stored in the RAM block in the modification according to the embodiment. 
     
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENT 
     The invention may provide an integrated circuit device which allows a flexible circuit arrangement to enable an efficient layout, and an electronic instrument including the same. 
     An embodiment of the invention provides an integrated circuit device having a display memory which stores data for at least one frame displayed in a display panel which has a plurality of scan lines and a plurality of data lines, 
     wherein the display memory includes a plurality of RAM blocks, each of the RAM blocks including a plurality of wordlines, a plurality of bitlines, a plurality of memory cells, and a data read control circuit, and 
     wherein each of the RAM blocks is disposed along a first direction in which the bitlines extend. 
     In a related-art integrated circuit device, since the number of memory cells connected with one wordline must be equal to the number of grayscale bits of the pixels corresponding to all the data lines of the display panel, the degrees of freedom of the layout are decreased. In a related-art integrated circuit device, when dividing the display memory into RAM blocks, the display memory is divided into blocks in the direction in which the wordlines extend, and the RAM blocks are disposed along the direction in which the wordlines extend. 
     In the embodiment, the RAM blocks divided in the wordline direction are rotated at 90 degrees and disposed along the first direction in which the bitlines extend. 
     This enables the RAM blocks to be arranged in the integrated circuit device in a way completely differing from the related-art uniform layout. 
     With this integrated circuit device, 
     each of the memory cells may have a short side and a long side, 
     the bitlines may be formed in each of the memory cells along a direction in which the short sides of the memory cells extend, and 
     the wordlines may be formed along a direction in which the long sides of the memory cells extend. 
     This enables the number of memory cells connected in common with the bitline to be increased even when the size of the RAM block is limited in the direction in which the bitline is formed. Specifically, since an efficient layout can be achieved, cost can be reduced. 
     With this integrated circuit device, 
     the data read control circuit may control data reading so that data for pixels corresponding to the data lines is read out from the display memory by N times reading in one horizontal scan period of the display panel (N is an integer larger than one). 
     Since data stored in the RAM block can be read out by N times reading in one horizontal scan period, the degrees of freedom of the layout of the display memory can be increased. Specifically, when reading data from the display memory only once in one horizontal scan period as in a related-art integrated circuit device, since the number of memory cells connected with one wordline must be equal to the number of grayscale bits of the pixels corresponding to all the data lines of the display panel, the degrees of freedom of the layout are decreased. In the embodiment, since data is read N times in one horizontal scan period, the number of memory cells connected with one wordline can be reduced by 1/N. Therefore, the aspect (height/width) ratio of the RAM block can be changed by changing the number of readings N, for example. 
     With this integrated circuit device, 
     the data read control circuit may include a wordline control circuit, and 
     the wordline control circuit may select N different wordlines from the wordlines in the one horizontal scan period, and may not select the identical wordline a plurality of times in one vertical scan period of the display panel. 
     Although data may be read N times in one horizontal scan period in various ways, the number of memory cells connected with one wordline is reduced by 1/N by the above-described control. The data in the number of grayscale bits of the pixels corresponding to all the data lines of the display panel can be read by selecting N wordlines in one horizontal scan period. 
     With this integrated circuit device, 
     each of the RAM blocks may include a sense amplifier circuit which outputs M-bit (M is an integer larger than one) data by one wordline selection, and 
     at least M memory cells may be arranged in each of the RAM blocks along a second direction in which the wordlines extend. 
     This enables at least M×(long side of memory cell) to be secured for the sense amplifier circuit which outputs M-bit data as the length in the direction in which the wordlines extend. 
     With this integrated circuit device, 
     when the number of the scan lines of the display panel is SCN, at least N×SCN memory cells may be arranged in each of the RAM blocks along the first direction. 
     However, since the side of the memory cell in the direction (first direction) in which the bitline extends is the short side, the length of the RAM block in the first direction is not increased to a large extent. 
     With this integrated circuit device, 
     when the number of the data lines is denoted as DLN, the number of grayscale bits of each pixel corresponding to the data lines is denoted as G, and the number of the RAM blocks is denoted as BNK, the value M may be given by the following equation. 
     
       
         
           
             M 
             = 
             
               
                 DLN 
                 × 
                 G 
               
               
                 BNK 
                 × 
                 N 
               
             
           
         
       
     
     This enables the layout of the RAM block to be determined based on the value M. Moreover, when the value M is limited due to the limitations to the space, the number of RAM blocks BNK can be determined by calculating back from the above equation. 
     This integrated circuit device may include a data line driver which drives the data lines of the display panel based on data read from the display memory in one horizontal scan period. 
     This enables the data lines of the display panel to be driven. 
     With this integrated circuit device, the data line driver may include data line driver blocks in a number corresponding to the RAM blocks, and the data line driver blocks may be disposed along the first direction. 
     This enables the data lines of the display panel to be driven based on data stored in the RAM block. Moreover, an efficient layout for the integrated circuit device can be achieved by disposing the data line driver block and the RAM block along the first direction. 
     With this integrated circuit device, the data line driver blocks may be disposed adjacent to one of the RAM blocks in the first direction. 
     This enables the data line driver block to efficiently receive data from the RAM block. 
     With this integrated circuit device, 
     each of the data line driver blocks may include first to N-th divided data line drivers, 
     first to N-th latch signals may respectively be supplied to the first to N-th divided data line drivers, and 
     the first to N-th divided data line drivers may latch data input from the corresponding RAM blocks based on the first to N-th latch signals. 
     This enables the first to N-th latch signals to be controlled in response to the selection of the wordline, whereby the first to N-th divided data line drivers can latch data necessary for driving the data lines. Moreover, the size of the data line driver block in the second direction can be flexibly set by dividing the data line driver block into the divided data line drivers. Specifically, the data line driver block can be efficiently disposed in the integrated circuit device. 
     With this integrated circuit device, a side of the RAM block opposite to a side adjacent to the data line driver block may be a side adjacent to one of the remaining RAM blocks. 
     According to the embodiment, the RAM blocks can be disposed adjacent to each other. In this case, since the integrated circuit device can be designed so that a part of the circuits necessary for the RAM blocks to be used in common, the size of the RAM block in the first direction can be reduced. Specifically, since an efficient layout for the integrated circuit device can be achieved, manufacturing cost can be reduced. 
     With this integrated circuit device, 
     the wordline control circuit may selecte the wordline based on a wordline control signal, and 
     the identical wordline control signal may be supplied to the wordline control circuits of the RAM blocks when driving the data lines. 
     This enables uniform read control of the RAM blocks, whereby image data can be supplied to the data line driver as the display memory. 
     With this integrated circuit device, 
     the data line driver blocks may drive the data lines based on a data line control signal, and 
     when the data line driver drives the data lines, the identical data line control signal may be supplied to the data line driver blocks. 
     This enables uniform control of the data line driver blocks, whereby the data lines of the display panel can be driven based on data supplied from each RAM block. 
     Another embodiment of the invention provides an electronic instrument, comprising any of the above integrated circuit devices; and a display panel. 
     With this electronic instrument, the integrated circuit device may be mounted on a substrate which forms the display panel. 
     With this electronic instrument, the integrated circuit device may be mounted on the substrate which forms the display panel so that the wordlines of the integrated circuit device are parallel to a direction in which the data lines of the display panel extend. 
     This enables the length of the wordline to be reduced in the electronic instrument according to the embodiment without providing a special circuit, in comparison with the case where the wordline is formed perpendicularly to the data line. In the embodiment, a host may select one of the RAM blocks and control the wordline of the selected RAM block. Since the length of the wordline to be controlled can be reduced as described above, the electronic instrument according to the embodiment can reduce power consumption during write control from the host. 
     Note that the embodiments described hereunder do not in any way limit the scope of the invention defined by the claims laid out herein. Note also that not all of the elements of these embodiments should be taken as essential requirements to the means of the present invention. 
     1. Display Driver 
       FIG. 1A  shows a display panel  10  on which a display driver  20  (integrated circuit device in a broad sense) is mounted. In the embodiment, the display driver  20  or the display panel  10  on which the display driver  20  is mounted may be provided in a small electronic instrument (not shown). As examples of the small electronic instrument, a portable telephone, a PDA, a digital music player including a display panel, and the like can be given. In the display panel  10 , a plurality of display pixels are formed on a glass substrate, for example. A plurality of data lines (not shown) extending in a direction Y and a plurality of scan lines (not shown) extending in a direction X are formed in the display panel  10  corresponding to the display pixels. The display pixel formed in the display panel  10  of the embodiment is a liquid crystal element. However, the display pixel is not limited to the liquid crystal element. The display pixel may be a light-emitting element such as an electroluminescence (EL) element. The display pixel may be either an active type including a transistor or the like or a passive type which does not include a transistor or the like. When the active type display pixel is applied to a display region  12 , the liquid crystal pixel may be an amorphous TFT or a low-temperature polysilicon TFT. 
     The display panel  10  includes the display region  12  having PX pixels in the direction X and PY pixels in the direction Y, for example. When the display panel  10  supports a QVGA display, PX=240 and PY=320 so that the display region  12  is displayed in 240×320 pixels. The number of pixels PX of the display panel  10  in the direction X coincides with the number of data lines in the case of a black and white display. In the case of a color display, one pixel is formed by three subpixels including an R subpixel, a G subpixel, and a B subpixel. Therefore, the number of data lines is (3×PX) in the case of a color display. Accordingly, the “number of pixels corresponding to the data lines” means the “number of subpixels in the direction X” in the case of a color display. The number of bits of each subpixel is determined corresponding to the grayscale. When the grayscale values of three subpixels are respectively G bits, the grayscale value of one pixel is 3 G. When each subpixel represents 64 grayscales (six bits), the amount of data for one pixel is 6×3=18 bits. 
     The relationship between the number of pixels PX and the number of pixels PY may be PX&gt;PY, PX&lt;PY, or PX=PY. 
     The display driver  20  has a length CX in the direction X and a length CY in the direction Y. A long side IL of the display driver  20  having the length CX is parallel to a side PL 1  of the display region  12  on the side of the display driver  20 . Specifically, the display driver  20  is mounted on the display panel  10  so that the long side IL is parallel to the side PL 1  of the display region  12 . 
       FIG. 1B  is a diagram showing the size of the display driver  20 . The ratio of a short side IS of the display driver  20  having the length CY to the long side IL of the display driver  20  is set at 1:10, for example. Specifically, the short side IS of the display driver  20  is set to be much shorter than the long side IL. The chip size of the display driver  20  in the direction Y can be minimized by forming such a narrow display driver  20 . 
     The above-mentioned ratio “1:10” is merely an example. The ratio is not limited thereto. For example, the ratio may be 1:11 or 1:9. 
       FIG. 1A  illustrates the length LX in the direction X and the length LY in the direction Y of the display region  12 . The aspect (height/width) ratio of the display region  12  is not limited to that shown in  FIG. 1A . The length LY of the display region  12  may be shorter than the length LX, for example. 
     In  FIG. 1A , the length LX of the display region  12  in the direction X is equal to the length CX of the display driver  20  in the direction X. It is preferable that the length LX and the length CX be equal as shown in  FIG. 1A , although not limited to  FIG. 1A . The reason is shown in  FIG. 2A . 
     In a display driver  22  shown in  FIG. 2A , the length in the direction X is set at CX 2 . Since the length CX 2  is shorter than the length LX of the side PL 1  of the display region  12 , a plurality of interconnects which connect the display driver  22  with the display region  12  cannot be provided parallel to the direction Y, as shown in  FIG. 2A . Therefore, it is necessary to increase a distance DY 2  between the display region  12  and the display driver  22 . As a result, since the size of the glass substrate of the display panel  10  must be increased, a reduction in cost is hindered. Moreover, when providing the display panel  10  in a smaller electronic instrument, the area other than the display region  12  is increased, whereby a reduction in size of the electronic instrument is hindered. 
     On the other hand, since the display driver  20  of the embodiment is formed so that the length CX of the long side IL is equal to the length LX of the side PL 1  of the display region  12  as shown in  FIG. 2B , the interconnects between the display driver  20  and the display region  12  can be provided parallel to the direction Y. This enables a distance DY between the display driver  20  and the display region  12  to be reduced in comparison with  FIG. 2A . Moreover, since the length IS of the display driver  20  in the direction Y is short, the size of the glass substrate of the display panel  10  in the direction Y is reduced, whereby the size of an electronic instrument can be reduced. 
     In the embodiment, the display driver  20  is formed so that the length CX of the long side IL is equal to the length LX of the side PL 1  of the display region  12 . However, the invention is not limited thereto. 
     The distance DY can be reduced while achieving a reduction in the chip size by setting the length of the long side IL of the display driver  20  to be equal to the length LX of the side PL 1  of the display region  12  and reducing the length of the short side IS. Therefore, manufacturing cost of the display driver  20  and manufacturing cost of the display panel  10  can be reduced. 
       FIGS. 3A and 3B  are diagrams showing a layout configuration example of the display driver  20  of the embodiment. As shown in  FIG. 3A , the display driver  20  includes a data line driver  100  (data line driver block in a broad sense), a RAM  200  (integrated circuit device or RAM block in a broad sense), a scan line driver  300 , a G/A circuit  400  (gate array circuit; automatic routing circuit in a broad sense), a grayscale voltage generation circuit  500 , and a power supply circuit  600  disposed along the direction X. These circuits are disposed within a block width ICY of the display driver  20 . An output PAD  700  and an input-output PAD  800  are provided in the display driver  20  with these circuits interposed therebetween. The output PAD  700  and the input-output PAD  800  are formed along the direction X. The output PAD  700  is provided on the side of the display region  12 . A signal line for supplying control information from a host (e.g. MPU, baseband engine (BBE), MGE, or CPU), a power supply line, and the like are connected with the input-output PAD  800 , for example. 
     The data lines of the display panel  10  are divided into a plurality of (e.g. four) blocks, and one data line driver  100  drives the data lines for one block. 
     It is possible to flexibly meet the user&#39;s needs by providing the block width ICY and disposing each circuit within the block width ICY In more detail, since the number of data lines which drive the pixels is changed when the number of pixels PX of the drive target display panel  10  in the direction X is changed, it is necessary to design the data line driver  100  and the RAM  200  corresponding to such a change in the number of data lines. In a display driver for a low-temperature polysilicon (LTPS) TFT panel, since the scan driver  300  can be formed on the glass substrate, the scan line driver  300  may not be provided in the display driver  20 . 
     In the embodiment, the display driver  20  can be designed merely by changing the data line driver  100  and the RAM  200  or removing the scan line driver  300 . Therefore, since it is unnecessary to newly design the display driver  20  by utilizing the original layout, design cost can be reduced. 
     In  FIG. 3A , two RAMs  200  are disposed adjacent to each other. This enables a part of the circuits used for the RAM  200  to be used in common, whereby the area of the RAM  200  can be reduced. The detailed effects are described later. In the embodiment, the display driver is not limited to the display driver  20  shown in  FIG. 3A . For example, the data line driver  100  and the RAM  200  may be adjacent to each other and two RAMs  200  may not be disposed adjacent to each other, as in a display driver  24  shown in  FIG. 3B . 
     In  FIGS. 3A and 3B , four data line drivers  100  and four RAMs  200  are provided as an example. The number of data lines driven in one horizontal scan period (also called “1H period”) can be divided into four by providing four data line drivers  100  and four RAMs  200  (4BANK) in the display driver  20 . When the number of pixels PX is 240, it is necessary to drive 720 data lines in the 1H period taking the R subpixel, G subpixel, and B subpixel into consideration, for example. In the embodiment, it suffices that each data line driver  100  drive  180  data lines which are ¼ of the 720 data lines. The number of data lines driven by each data line driver  100  can be reduced by increasing the number of BANKs. The number of BANKs is defined as the number of RAMs  200  provided in the display driver  20 . The total storage area of the RAMs  200  is defined as the storage area of a display memory. The display memory may store at least data for displaying an image for one frame of the display panel  10 . 
       FIG. 4  is an enlarged diagram of a part of the display panel  10  on which the display driver  20  is mounted. The display region  12  is connected with the output PAD  700  of the display driver  20  through interconnects DQL. The interconnect may be an interconnect provided on the glass substrate, or may be an interconnect formed on a flexible substrate or the like and connects the output PAD  700  with the display region  12 . 
     The length of the RAM  200  in the direction Y is set at RY. In the embodiment, the length RY is set to be equal to the block width ICY shown in  FIG. 3A . However, the invention is not limited thereto. For example, the length RY may be set to be equal to or less than the block width ICY. 
     The RAM  200  having the length RY includes a plurality of wordlines WL and a wordline control circuit  240  which controls the wordlines WL. The RAM  200  includes a plurality of bitlines BL, a plurality of memory cells MC, and a control circuit (not shown) which controls the bitlines BL and the memory cells MC. The bitlines BL of the RAM  200  are provided parallel to the direction X. Specifically, the bitlines BL are provided parallel to the side PL 1  of the display region  12 . The wordlines WL of the RAM  200  are provided parallel to the direction Y. Specifically, the wordlines WL are provided parallel to the interconnects DQL. 
     Data is read from the memory cell MC of the RAM  200  by controlling the wordline WL, and the data read from the memory cell MC is supplied to the data line driver  100 . Specifically, when the wordline WL is selected, data stored in the memory cells MC arranged along the direction Y is supplied to the data line driver  100 . 
       FIG. 5  is a cross-sectional diagram showing the cross section A-A shown in  FIG. 3A . The cross section A-A is the cross section in the region in which the memory cells MC of the RAM  200  are arranged. For example, five metal interconnect layers are provided in the region in which the RAM  200  is formed. A first metal interconnect layer ALA, a second metal interconnect layer ALB, a third metal interconnect layer ALC, a fourth metal interconnect layer ALD, and a fifth metal interconnect layer ALE are illustrated in  FIG. 5 . A grayscale voltage interconnect  292  to which a grayscale voltage is supplied from the grayscale voltage generation circuit  500  is formed in the fifth metal interconnect layer ALE, for example. A power supply interconnect  294  for supplying a voltage supplied from the power supply circuit  600 , a voltage supplied from the outside through the input-output PAD  800 , or the like is also formed in the fifth metal interconnect layer ALE. The RAM  200  of the embodiment may be formed without using the fifth metal interconnect layer ALE, for example. Therefore, various interconnects can be formed in the fifth metal interconnect layer ALE as described above. 
     A shield layer  290  is formed in the fourth metal interconnect layer ALD. This enables effects exerted on the memory cells MC of the RAM  200  to be reduced even if various interconnects are formed in the fifth metal interconnect layer ALE in the upper layer of the memory cells MC of the RAM  200 . A signal interconnect for controlling the control circuit for the RAM  200 , such as the wordline control circuit  240 , may be formed in the fourth metal interconnect layer ALD in the region in which the control circuit is formed. 
     An interconnect  296  formed in the third metal interconnect layer ALC may be used as the bitline BL or a voltage VSS interconnect, for example. An interconnect  298  formed in the second metal interconnect layer ALB may be used as the wordline WL or a voltage VDD interconnect, for example. An interconnect  299  formed in the first metal interconnect layer ALA may be used to connect with each node formed in a semiconductor layer of the RAM  200 . 
     The wordline interconnect may be formed in the third metal interconnect layer ALC, and the bitline interconnect may be formed in the second metal interconnect layer ALB, differing from the above-described configuration. 
     As described above, since various interconnects can be formed in the fifth metal interconnect layer ALE of the RAM  200 , various types of circuit blocks can be arranged along the direction X as shown in  FIGS. 3A and 3B . 
     2. Data Line Driver 
     2.1 Configuration of Data Line Driver 
       FIG. 6A  is a diagram showing the data line driver  100 . The data line driver  100  includes an output circuit  104 , a DAC  120 , and a latch circuit  130 . The DAC  120  supplies the grayscale voltage to the output circuit  104  based on data latched by the latch circuit  130 . The data supplied from the RAM  200  is stored in the latch circuit  130 , for example. When the grayscale is set at G bits, G-bit data is stored in each latch circuit  130 , for example. A plurality of grayscale voltages are generated according to the grayscale, and supplied to the data line driver  100  from the grayscale voltage generation circuit  500 . For example, the grayscale voltages supplied to the data line driver  100  are supplied to the DAC  120 . The DAC  120  selects the corresponding grayscale voltage from the grayscale voltages supplied from the grayscale voltage generation circuit  500  based on the G-bit data latched by the latch circuit  130 , and outputs the selected grayscale voltage to the output circuit  104 . 
     The output circuit  104  is formed by an operational amplifier, for example. However, the invention is not limited thereto. As shown in  FIG. 6B , an output circuit  102  may be provided in the data line driver  100  instead of the output circuit  104 . In this case, a plurality of operational amplifiers are provided in the grayscale voltage generation circuit  500 . 
       FIG. 7  is a diagram showing a plurality of data line driver cells  110  provided in the data line driver  100 . The data line driver  100  drives the data lines, and the data line driver cell  110  drives one of the data lines. For example, the data line driver cell  110  drives one of the R subpixel, the G subpixel, and the B subpixel which make up one pixel. Specifically, when the number of pixels PX in the direction X is 240, 720(=240×3) data line driver cells  110  in total are provided in the display driver  20 . In the 4BANK configuration, 180 data line driver cells  110  are provided in each data line driver  100 . 
     The data line driver cell  110  includes an output circuit  140 , the DAC  120 , and the latch circuit  130 , for example. However, the invention is not limited thereto. For example, the output circuit  140  may be provided outside the data line driver cell  110 . The output circuit  140  may be either the output circuit  104  shown in  FIG. 6A  or the output circuit  102  shown in  FIG. 6B . 
     When the grayscale data indicating the grayscales of the R subpixel, the G subpixel, and the B subpixel is set at G bits, G-bit data is supplied to the data line driver cell  110  from the RAM  200 . The latch circuit  130  latches the G-bit data. The DAC  120  outputs the grayscale voltage through the output circuit  140  based on the output from the latch circuit  130 . This enables the data line provided in the display panel  10  to be driven. 
     2.2 A Plurality of Readings in One Horizontal Scan Period 
       FIG. 8  shows a display driver  24  of a comparative example according to the embodiment. The display driver  24  is mounted so that a side DLL of the display driver  24  faces the side PL 1  of the display panel  10  on the side of the display region  12 . The display driver  24  includes a RAM  205  and a data line driver  105  of which the length in the direction X is greater than the length in the direction Y. The lengths of the RAM  205  and the data line driver  105  in the direction X are increased as the number of pixels PX of the display panels  10  is increased. The RAM  205  includes a plurality of wordlines WL and a plurality of bitlines BL. The wordline WL of the RAM  205  is formed to extend along the direction X, and the bitline BL is formed to extend along the direction Y. Specifically, the wordline WL is formed to be significantly longer than the bitline BL. Since the bitline BL is formed to extend along the direction Y, the bitline BL is parallel to the data line of the display panel  10  and intersects the side PL 1  of the display panel  10  at right angles. 
     The display driver  24  selects the wordline WL once in the 1H period. The data line driver  105  latches data output from the RAM  205  upon selection of the wordline WL, and drives the data lines. In the display driver  24 , since the wordline WL is significantly longer than the bitline BL as shown in  FIG. 8 , the data line driver  100  and the RAM  205  are longer in the direction X, so that it is difficult to secure space for disposing other circuits in the display driver  24 . This hinders a reduction in the chip area of the display driver  24 . Moreover, since the design time for securing the space and the like is necessary, a reduction in design cost is made difficult. 
     The RAM  205  shown in  FIG. 8  is disposed as shown in  FIG. 9A , for example. In  FIG. 9A , the RAM  205  is divided into two blocks. The length of one of the divided blocks in the direction X is “12”, and the length in the direction Y is “2”, for example. Therefore, the area of the RAM  205  may be indicated by “48”. These length values indicate an example of the ratio which indicates the size of the RAM  205 . The actual size is not limited to these length values. In  FIGS. 9A to 9D , reference numerals  241  to  244  indicate wordline control circuits, and reference numerals  206  to  209  indicate sense amplifiers. 
     In the embodiment, the RAM  205  may be divided into a plurality of blocks and disposed in a state in which the divided blocks are rotated at 90 degrees. For example, the RAM  205  may be divided into four blocks and disposed in a state in which the divided blocks are rotated at 90 degrees, as shown in  FIG. 9B . A RAM  205 - 1 , which is one of the four divided blocks, includes a sense amplifier  207  and the wordline control circuit  242 . The length of the RAM  205 - 1  in the direction Y is “6”, and the length in the direction X is “2”. Therefore, the area of the RAM  205 - 1  is “12” so that the total area of the four blocks is “48”. However, since it is desired to reduce the length CY of the display driver  20  in the direction Y, the state shown in  FIG. 9B  is inconvenient. 
     In the embodiment, the length RY of the RAM  200  in the direction Y can be reduced by reading data a plurality of times in the 1H period, as shown in  FIGS. 9C and 9D .  FIG. 9C  shows an example of reading data twice in the 1H period. In this case, since the wordline WL is selected twice in the 1H period, the number of memory cells MC arranged in the direction Y can be halved, for example. This enables the length of the RAM  200  in the direction Y to be reduced to “3”, as shown in  FIG. 9C . The length of the RAM  200  in the direction X is increased to “4”. Specifically, the total area of the RAM  200  becomes “48”, so that the RAM  200  becomes equal to the RAM  205  shown in  FIG. 9A  as to the area of the region in which the memory cells MC are arranged. Since the RAM  200  can be freely disposed as shown in  FIGS. 3A and 3B , a very flexible layout becomes possible, whereby an efficient layout can be achieved. 
       FIG. 9D  shows an example of reading data three times. In this case, the length “6” of the RAM  205 - 1  shown in  FIG. 9B  in the direction Y can be reduced by ⅓. Specifically, the length CY of the display driver  20  in the direction Y can be reduced by adjusting the number of readings in the 1H period. 
     In the embodiment, the RAM  200  divided into blocks can be provided in the display driver  20  as described above. In the embodiment, the 4BANK RAMs  200  can be provided in the display driver  20 , for example. In this case, data line drivers  100 - 1  to  100 - 4  corresponding to each RAM  200  drive the corresponding data lines DL as shown in  FIG. 10 . 
     In more detail, the data line driver  100 - 1  drives a data line group DLS 1 , the data line driver  100 - 2  drives a data line group DLS 2 , the data line driver  100 - 3  drives a data line group DLS 3 , and the data line driver  1004  drives a data line group DLS 4 . Each of the data line groups DLS 1  to DLS 4  is one of four blocks into which the data lines DL provided in the display region  12  of the display panel  10  are divided, for example. The data lines of the display panel  10  can be driven by providing four data line drivers  100 - 1  to  1004  corresponding to the 4BANK RAM  200  and causing the data line drivers  100 - 1  to  100 - 4  to drive the corresponding data lines. 
     2.3 Divided Structure of Data Line Driver 
     The length RY of the RAM  200  shown in  FIG. 4  in the direction Y may depend not only on the number of memory cells MC arranged in the direction Y, but also on the length of the data line driver  100  in the direction Y. 
     In the embodiment, on the premise that data is read a plurality of times (e.g. twice) in one horizontal scan period in order to reduce the length RY of the RAM  200  shown in  FIG. 4 , the data line driver  100  is formed to have a divided structure consisting of a first data line driver  100 A (first divided data line driver in a broad sense) and a second data line driver  100 B (second divided data line driver in a broad sense), as shown in  FIG. 11A . A reference character “M” shown in  FIG. 11A  indicates the number of bits of data read from the RAM  200  by one wordline selection. 
     For example, when the number of pixels PX is 240, the grayscale of the pixel is 18 bits, and the number of BANKs of the RAM  200  is four (4BANK), 1080 (=240×18÷4) bits of data must be output from each RAM  200  when reading data only once in the 1H period. 
     However, it is desired to reduce the length RY of the RAM  200  in order to reduce the chip area of the display driver  100 . Therefore, as shown in  FIG. 1A , the data line driver  100  is divided into the data line drivers  100 A and  100 B in the direction X on the premise that data is read twice in the 1H period, for example. This enables M to be set at 540 (=1080÷2) so that the length RY of the RAM  200  can be approximately halved. 
     The data line driver  100 A drives a part of the data lines of the display panel  10 . The data line driver  100 B drives a part of the data lines of the display panel  10  other than the data lines driven by the data line driver  100 A. As described above, the data line drivers  100 A and  100 B cooperate to drive the data lines of the display panel  10 . 
     In more detail, the wordlines WL 1  and WL 2  are selected in the 1H period as shown in  FIG. 11B , for example. Specifically, the wordlines are selected twice in the 1H period. A latch signal SLA falls at a timing A 1 . The latch signal SLA is supplied to the data line driver  100 A, for example. The data line driver  100 A latches M-bit data supplied from the RAM  200  in response to the falling edge of the latch signal SLA, for example. 
     A latch signal SLB falls at a timing A 2 . The latch signal SLB is supplied to the data line driver  100 B, for example. The data line driver  100 B latches M-bit data supplied from the RAM  200  in response to the falling edge of the latch signal SLB, for example. 
     In more detail, data stored in a memory cell group MCS 1  (M memory cells) is supplied to the data line drivers  100 A and  100 B through a sense amplifier circuit  210  upon selection of the wordline WL 1 , as shown in  FIG. 12 . However, since the latch signal SLA falls in response to the selection of the wordline WL 1 , the data stored in the memory cell group MCS 1  (M memory cells) is latched by the data line driver  100 A. 
     Upon selection of the wordline WL 2 , data stored in a memory cell group MCS 2  (M memory cells) is supplied to the data line drivers  100 A and  100 B through the sense amplifier circuit  210 . The latch signal SLB falls in response to the selection of the wordline WL 2 . Therefore, the data stored in the memory cell group MCS 2  (M memory cells) is latched by the data line driver  100 B. 
     For example, when M is set at 540 bits, M=540 bit data is latched by each of the data line drivers  100 A and  100 B, since the data is read twice in the 1H period. Specifically, 1080-bit data in total is latched by the data line driver  100  so that 1080 bits necessary for the above-described example can be latched in the 1H period. Therefore, the amount of data necessary in the 1H period can be latched, and the length RY of the RAM  200  can be approximately halved. This enables the block width ICY of the display driver  20  to be reduced, whereby manufacturing cost of the display driver  20  can be reduced. 
       FIGS. 11A and 11B  illustrate an example of reading data twice in the 1H period. However, the invention is not limited thereto. For example, data may be read four or more times in the 1H period. When reading data four times, the data line driver  100  may be divided into four blocks so that the length RY of the RAM  200  can be further reduced. In this case, M may be set at 270 in the above-described example, and 270-bit data is latched by each of the four divided data line drivers. Specifically, 1080 bits of data necessary in the 1H period can be supplied while reducing the length RY of the RAM  200  by approximately ¼. 
     The outputs of the data line drivers  100 A and  100 B may be caused to rise based on control by using a data line enable signal (not shown) or the like as indicated by A 3  and A 4  shown in  FIG. 11B , or the data latched by the data line drivers  100 A and  100 B at the timings A 1  and A 2  may be directly output to the data lines. An additional latch circuit may be provided to each of the data line drivers  100 A and  100 B, and voltages based on the data latched at the timings A 1  and A 2  may be output in the next 1H period. This enables the number of readings in the 1H period to be increased without causing the image quality to deteriorate. 
     When the number of pixels PY is 320 (the number of scan lines of the display panel  10  is 320) and 60 frames are displayed within one second, the 1H period is about 52 μs as shown in  FIG. 11B . The 1H period is calculated as indicated by “1 sec÷60 frames÷320≈52 μs”. As shown in  FIG. 11B , the wordlines are selected within about 40 nsec. Specifically, since the wordlines are selected (data is read from the RAM  200 ) a plurality of times within a period sufficiently shorter than the 1H period, deterioration of the image quality of the display panel  10  does not occur. 
     The value M can be obtained by using the following equation, when BNK denotes the number of BANKs, N denotes the number of readings in the 1H period, and “the number of pixels PX×3” means the number of pixels (or the number of subpixels in the embodiment) corresponding to the data lines of the display panel  10  and coincides with the number of data lines DLN: 
     
       
         
           
             M 
             = 
             
               
                 PX 
                 × 
                 3 
                 × 
                 G 
               
               
                 BNK 
                 × 
                 N 
               
             
           
         
       
     
     In the embodiment, the sense amplifier circuit  210  has a latch function. However, the invention is not limited thereto. For example, the sense amplifier circuit  210  need not have a latch function. 
     2.4 Subdivision of Data Line Driver 
       FIG. 13  is a diagram illustrative of the relationship between the RAM  200  and the data line driver  100  for the R subpixel among the subpixels which make up one pixel as an example. 
     When the grayscale G bits of each subpixel are set at six bits (64 grayscales), 6-bit data is supplied from the RAM  200  to data line driver cells  110 A-R and  110 B-R for the R subpixel. In order to supply the 6-bit data, six sense amplifiers  211  among the sense amplifiers  211  included in the sense amplifier circuit  210  of the RAM  200  correspond to each data line driver cell  110 , for example. 
     For example, it is necessary that a length SCY of the data line driver cell  110 A-R in the direction Y be within a length SAY of the six sense amplifiers  211  in the direction Y. Likewise, it is necessary that the length of each data line driver cell in the direction Y be within the length SAY of the six sense amplifiers  211 . When the length SCY cannot be set within the length SAY of the six sense amplifiers  211 , the length of the data line driver  100  in the direction Y becomes greater than the length RY of the RAM  200 , whereby the layout efficiency is decreased. 
     The size of the RAM  200  has been reduced in view of the process, and the sense amplifier  211  is also small. As shown in  FIG. 7 , a plurality of circuits are provided in the data line driver cell  110 . In particular, it is difficult to design the DAC  120  and the latch circuit  130  to have a small circuit size. Moreover, the size of the DAC  120  and the latch circuit  130  is increased as the number of bits input is increased. Specifically, it may be difficult to set the length SCY within the total length SAY of the six sense amplifiers  211 . 
     In the embodiment, the data line drivers  100 A and  100 B divided by the number of readings N in the 1H period may be further divided into k (k is an integer larger than 1) blocks and stacked in the direction X.  FIG. 14  shows a configuration example in which each of the data line drivers  100 A and  100 B is divided into two (k=2) blocks and stacked in the RAM  200  set to read data twice (N=2) in the 1H period.  FIG. 14  shows the configuration example of the RAM  200  set to read data twice. However, the invention is not limited to the configuration example shown in  FIG. 14 . When the RAM  200  is set to read data four times (N=4), the data line driver is divided into eight (N×k=4×2=8) blocks in the direction X, for example. 
     As shown in  FIG. 14 , the data line drivers  100 A and  100 B shown in  FIG. 13  are respectively divided into data line drivers  100 A 1  and  100 A 2  and data line drivers  100 B 1  and  100 B 2 . The length of a data line driver cell  110 A 1 -R or the like in the direction Y is set at SCY 2 . In  FIG. 14 , the length SCY 2  is set within a length SAY 2  in the direction Y when G×2 sense amplifiers  211  are arranged. Specifically, since the acceptable length in the direction Y is increased in comparison with  FIG. 13  when forming each data line driver cell  110 , efficient design in view of layout can be achieved. 
     The operation of the configuration shown in  FIG. 14  is described below. When the wordline WL 1  is selected, M-bit data in total is supplied to at least one of the data line drivers  100 A 1 ,  100 A 2 ,  100 B 1 , and  100 B 2  through the sense amplifier blocks  210 - 1 ,  210 - 2 ,  210 - 3 , and  210 - 4 , for example. G-bit data output from the sense amplifier block  210 - 1  is supplied to the data line driver cells  110 A 1 -R and  110 -B 1 -R, for example. G-bit data output from the sense amplifier block  210 - 2  is supplied to the data line driver cells  110 A 2 -R and  110 -B 2 -R, for example. 
     The latch signal SLA (first latch signal in a broad sense) falls in response to the selection of the wordline WL 1  in the same manner as in the timing chart shown in  FIG. 11B . The latch signal SLA is supplied to the data line driver  100 A 1  including the data line driver cell  110 A 1 -R and the data line driver  100 A 2  including the data line driver cell  110 A 2 -R. Therefore, G-bit data (data stored in the memory cell group MCS 11 ) output from the sense amplifier block  210 - 1  in response to the selection of the wordline WL 1  is latched by the data line driver cell  110 A 1 -R. Likewise, G-bit data (data stored in the memory cell group MCS 12 ) output from the sense amplifier block  210 - 2  in response to the selection of the wordline WL 1  is latched by the data line driver cell  110 A 2 -R. 
     The above description also applies to the sense amplifier blocks  210 - 3  and  210 - 4 . Specifically, data stored in the memory cell group MCS 13  is latched by the data line driver cell  110 A 1 -Q and data stored in the memory cell group MCS 14  is latched by the data line driver cell  110 A 2 -G. 
     When the wordline WL 2  is selected, the latch signal SLB (an N-th latch signal in a broad sense) falls in response to the selection of the wordline WL 2 . The latch signal SLB is supplied to the data line driver  100 B 1  including the data line driver cell  110 B 1 -R and the data line driver  100 B 2  including the data line driver cell  110 B 2 -R. Therefore, G-bit data (data stored in the memory cell group MCS 21 ) output from the sense amplifier block  210 - 1  in response to the selection of the wordline WL 2  is latched by the data line driver cell  110 B 1 -R. Likewise, G-bit data (data stored in the memory cell group MCS 22 ) output from the sense amplifier block  210 - 2  in response to the selection of the wordline WL 2  is latched by the data line driver cell  110 B 2 -R. 
     The above description also applies to the sense amplifier blocks  210 - 3  and  210 - 4  when the wordline WL 2  is selected. Specifically, data stored in the memory cell group MCS 23  is latched by the data line driver cell  110 B 1 -G, and data stored in the memory cell group MCS 24  is latched by the data line driver cell  110 B 2 -G. A data line driver cell  110 A 1 -B is a B data line driver cell which latches B subpixel data. 
       FIG. 15B  shows data stored in the RAM  200  when the data line drivers  100 A and  100 B are divided as described above. As shown in  FIG. 15B , data in the sequence R subpixel data, R subpixel data, G subpixel data, G subpixel data, B subpixel data, B subpixel data, . . . is stored in the RAM  200  along the direction Y. In the configuration as shown in  FIG. 13 , data in the sequence R subpixel data, G subpixel data, B subpixel data, R subpixel data, . . . is stored in the RAM  200  along the direction Y, as shown in  FIG. 15A . 
     In  FIG. 13 , the length SAY is illustrated as the length of the six sense amplifiers  211 . However, the invention is not limited thereto. For example, the length SAY corresponds to the length of eight sense amplifiers  211  when the grayscale is eight bits. 
       FIG. 14  illustrates the configuration in which the data line drivers  100 A and  100 B are divided into two (k=2) blocks as an example. However, the invention is not limited thereto. For example, the data line drivers  100 A and  100 B may be divided into three (k=3) blocks or four (k=4) blocks. When the data line driver  100 A is divided into three (k=3) blocks, the same latch signal SLA may be supplied to the three divided blocks, for example. As a modification of the number of divisions k equal to the number of readings in the 1H period, when the data line driver is divided into three (k=3) blocks, the divided blocks may be respectively used as an R subpixel data driver, G subpixel data driver, and B subpixel data driver. This configuration is shown in  FIG. 16 .  FIG. 16  shows three divided data line drivers  101 A 1 ,  101 A 2 , and  101 A 3 . The data line driver  101 A 1  includes a data line driver cell  111 A 1 , the data line driver  101 A 2  includes a data line driver cell  111 A 2 , and the data line driver  101 A 3  includes a data line driver cell  111 A 3 . 
     The latch signal SLA falls in response to selection of the wordline WL 1 . The latch signal SLA is supplied to the data line drivers  101 A 1 ,  101 A 2 , and  101 A 3  in the same manner as described above. 
     According to this configuration, data stored in the memory cell group MCS 11  is stored in the data line driver cell  111 A 1  as R subpixel data upon selection of the wordline WL 1 , for example. Likewise, data stored in the memory cell group MCS 12  is stored in the data line driver cell  111 A 2  as G subpixel data, and data stored in the memory cell group MCS 13  is stored in the data line driver cell  111 A 3  as B subpixel data, for example. 
     Therefore, the data written into the RAM  200  can be arranged in the order of R subpixel data, G subpixel data, and B subpixel data along the direction Y, as shown in  FIG. 15A . In this case, the data line drivers  101 A 1 ,  101 A 2 , and  101 A 3  may be further divided into k blocks. 
     3. RAM 
     3.1 Configuration of Memory Cell 
     Each memory cell MC may be formed by a static random access memory (SRAM), for example.  FIG. 17A  shows an example of a circuit of the memory cell MC.  FIGS. 17B and 17C  show examples of the layout of the memory cell MC. 
       FIG. 17B  shows a layout example of a horizontal cell, and  FIG. 17C  shows a layout example of a vertical cell. As shown in  FIG. 17B , the horizontal cell is a cell in which a length MCY of the wordline WL is greater than lengths MCX of the bitlines BL and /BL in each memory cell MC. As shown in  FIG. 17C , the vertical cell is a cell in which the lengths MCX of the bitlines BL and /BL are greater than the length MCY of the wordline WL in each memory cell MC.  FIG. 17C  shows a sub-wordline SWL formed by a polysilicon layer and a main-wordline MWL formed by a metal layer. The main-wordline MWL is used as backing. 
       FIG. 18  shows the relationship between the horizontal cell MC and the sense amplifier  211 . In the horizontal cell MC shown in  FIG. 17B , a pair of bitlines BL and/BL is arranged along the direction X as shown in  FIG. 18 . Therefore, the length MCY of the long side of the horizontal cell MC is the length in the direction Y. The sense amplifier  211  requires a predetermined length SAY 3  in the direction Y in view of the circuit layout, as shown in  FIG. 18 . Therefore, the horizontal memory cells MC for one bit (PY memory cells in the direction X) are easily disposed for one sense amplifier  211 , as shown in  FIG. 18 . Therefore, when the total number of bits read from each RAM  200  in the 1H period is set at M as described by using the above equation, M memory cells MC may be arranged in the RAM  200  in the direction Y, as shown in  FIG. 19 . The example in which the RAM  200  includes M memory cells MC and M sense amplifiers  211  in the direction Y in  FIGS. 13 to 16  may be applied when using the horizontal cells. When the horizontal cell as shown in  FIG. 19  is used and data is read by selecting different wordlines WL twice in the 1H period, the number of memory cells MC arranged in the RAM  200  in the direction X is “number of pixels PY×number of readings (2)”. However, since the length MCX of the horizontal memory cell MC in the direction X is relatively small, the size of the RAM  200  in the direction X is not increased even if the number of memory cells MC arranged in the direction X is increased. 
     As an advantage of using the horizontal cell, an increase in the degrees of freedom of the length MCY of the RAM  200  in the direction Y can be given. Since the length of the horizontal cell in the direction Y can be adjusted, a cell layout having a ratio of the length in the direction Y to the length in the direction X of 2:1 or 1.5:1 may be provided. In this case, when the number of horizontal cells arranged in the direction Y is set at  100 , the length MCY of the RAM  200  in the direction Y can be designed in various ways by using the above-mentioned ratio. On the other hand, when using the vertical cell shown in  FIG. 17C , the length MCY of the RAM  200  in the direction Y is determined by the number of sense amplifiers  211  in the direction Y so that the degrees of freedom are small. 
     3.2 Common Use of Sense Amplifier for Vertical Cells 
     As shown in  FIG. 21A , the length SAY 3  of the sense amplifier  211  in the direction Y is sufficiently greater than the length MCY of the vertical memory cell MC. Therefore, the layout in which the memory cell MC for one bit is associated with one sense amplifier  211  when selecting the wordline WL is inefficient. 
     To deal with this problem, the memory cells MC for a plurality of bits (e.g. two bits) are associated with one sense amplifier  211  when selecting the wordline WL, as shown in  FIG. 21B . This enables the memory cells MC to be efficiently arranged in the RAM  200  irrespective of the difference between the length SAY 3  of the sense amplifier  211  and the length MCY of the memory cell MC. 
     In  FIG. 21B , a selective sense amplifier SSA includes the sense amplifier  211 , a switch circuit  220 , and a switch circuit  230 . The selective sense amplifier SSA is connected with two pairs of bitlines BL and /BL, for example. 
     The switch circuit  220  connects one pair of bitlines BL and /BL with the sense amplifier  211  based on a select signal COLA (sense amplifier select signal in a broad sense). The switch circuit  230  connects the other pair of bitlines BL and /BL with the sense amplifier  211  based on a select signal COLB. The signal levels of the select signals COLA and COLB are controlled exclusively, for example. In more detail, when the select signal COLA is set as a signal which sets the switch circuit  220  to active, the select signal COLB is set as a signal which sets the switch circuit  230  to inactive. Specifically, the selective sense amplifier SSA selects 1-bit data from 2-bit (N-bit or L-bit in a broad sense) supplied through the two pairs of bitlines BL and /BL, and outputs the corresponding data, for example. 
       FIG. 22  shows the RAM  200  including the selective sense amplifier SSA.  FIG. 22  shows a configuration in which data is read twice (N times in a broad sense) in the 1H period and the grayscale G bits are six bits as an example. In this case, M selective sense amplifiers SSA are provided in the RAM  200  as shown in  FIG. 23 . Therefore, data supplied to the data line driver  100  by one wordline selection is M bits in total. On the other hand, M×2 memory cells MC are arranged in the RAM  200  shown in  FIG. 23  in the direction Y. The memory cells MC in the same number as the number of pixels PY are arranged in the direction X, differing from  FIG. 19 . In the RAM  200  shown in  FIG. 23 , since the two pairs of bitlines BL and /BL are connected with the selective sense amplifier SSA, it suffices that the number of memory cells MC arranged in the RAM  200  in the direction X be the same as the number of pixels PY. 
     As a result, when using the vertical cell in which the length MCX of the memory cell MC is greater than the length MCY, an increase in the size of the RAM  200  in the direction X can be prevented by reducing the number of memory cells MC arranged in the direction X. 
     3.3 Read Operation From Vertical Memory Cell 
     The operation of the RAM  200  in which the vertical memory cells shown in  FIG. 22  are arranged is described below. As the read control method for the RAM  200 , two methods can be given, for example. One of the two methods is described below using timing charts shown in  FIGS. 24A and 24B . 
     The select signal COLA is set to active at a timing B 1  shown in  FIG. 24A , and the wordline WL 1  is selected at a timing B 2 . In this case, since the select signal COLA is active, the selective sense amplifier SSA detects and outputs data stored in the A-side memory cell MC, that is, the memory cell MC- 1 A. When the latch signal SLA falls at a timing B 3 , the data line driver cell  110 A-R latches the data stored in the memory cell MC- 1 A. 
     The select signal COLB is set to active at a timing B 4 , and the wordline WL 1  is selected at a timing B 5 . In this case, since the select signal COLB is active, the selective sense amplifier SSA detects and outputs data stored in the B-side memory cell MC, that is, the memory cell MC- 1 B. When the latch signal SLB falls at a timing B 6 , the data line driver cell  110 B-R latches the data stored in the memory cell MC- 1 B. In  FIG. 24A , the wordline WL 1  is selected when reading data twice. 
     The data latch operation of the data line driver  100  by reading data twice in the 1H period is completed in this manner. 
       FIG. 24B  shows a timing chart when the wordline WL 2  is selected. The operation is similar to the above-described operation. As a result, when the wordline WL 2  is selected as indicated by B 7  and B 8 , data stored in the memory cell MC- 2 A is latched by the data line driver cell  110 A-R, and data stored in the memory cell MC- 2 B is latched by the data line driver cell  110 B-R. 
     The data latch operation of the data line driver  100  by reading data twice in the 1H period differing from the 1H period shown in  FIG. 24A  is completed in this manner. 
     According to such a read method, data is stored in each memory cell MC of the RAM  200  as shown in  FIG. 25 . For example, data RA- 1  to RA- 6  is 6-bit R pixel data to be supplied to the data line driver cell  110 A-R, and data RB- 1  to RB- 6  is 6-bit R pixel data to be supplied to the data line driver cell  110 B-R. 
     As shown in  FIG. 25 , the data RA- 1  (data latched by the data line driver  100 A), the data RB- 1  (data latched by the data line driver  100 B), the data RA- 2  (data latched by the data line driver  100 A), the data RB- 2  (data latched by the data line driver  100 B), the data RA- 3  (data latched by the data line driver  100 A), the data RB- 3  (data latched by the data line driver  100 B), . . . are sequentially stored in the memory cells MC corresponding to the wordline WL 1  along the direction Y, for example. Specifically, (data latched by the data line driver  100 A) and (data latched by the data line driver  100 B) are alternately stored in the RAM  200  along the direction Y. 
     In the read method shown in  FIGS. 24A and 24B , data is read twice in the 1H period, and the same wordline is selected in the 1H period. 
     The above description discloses that each selective sense amplifier SSA receives data from two of the memory cells MC selected by one wordline selection. However, the invention is not limited thereto. For example, each selective sense amplifier SSA may receive N-bit data from N memory cells MC of the memory cells MC selected by one wordline selection. In this case, the selective sense amplifier SSA selects 1-bit data received from a first memory cell MC of first to N-th memory cells MC (N memory cells MC) upon first selection of a single wordline. The selective sense amplifier SSA selects 1-bit data received from the K-th memory cell MC upon K-th (1≦K≦N) selection of the wordline. 
     As a modification of  FIGS. 24A and 24B , J (J is an integer larger than 1) wordlines WL each selected N times in the 1H period may be selected so that the number of times data is read from the RAM  200  in the 1H period is N×J. Specifically, when N=2 and J=2, the four wordline selections shown in  FIGS. 24A and 24B  are performed in a single horizontal scan period 1H. Specifically, data is read four (N=4) times by selecting the wordline WL 1  twice and selecting the wordline WL 2  twice in the 1H period. 
     The other control method is described below with reference to  FIGS. 26A and 26B . 
     The select signal COLA is set to active at a timing C 1  shown in  FIG. 26A , and the wordline WL 1  is selected at a timing C 2 . This causes the memory cells MC- 1 A and MC- 1 B shown in  FIG. 22  to be selected. In this case, since the select signal COLA is active, the selective sense amplifier SSA detects and outputs data stored in the A-side memory cell MC (first memory cell in a broad sense), that is, the memory cell MC- 1 A. When the latch signal SLA falls at a timing C 3 , the data line driver cell  110 A-R latches the data stored in the memory cell MC- 1 A. 
     The wordline WL 2  is selected at a timing C 4  so that the memory cells MC- 2 A and MC- 2 B are selected. In this case, since the select signal COLA is active, the selective sense amplifier SSA detects and outputs data stored in the A-side memory cell MC, that is, the memory cell MC- 2 A. When the latch signal SLB falls at a timing C 5 , the data line driver cell  110 B-R latches the data stored in the memory cell MC- 2 A. 
     The data latch operation of the data line driver  100  by reading data twice in the 1H period is completed in this manner. 
     The read operation in the 1H period differing from the 1H period shown in  FIG. 26A  is described below with reference to  FIG. 26B . The select signal COLB is set to active at a timing C 6  shown in  FIG. 26B , and the wordline WL 1  is selected at a timing C 7 . This causes the memory cells MC- 1 A and MC- 1 B shown in  FIG. 22  to be selected. In this case, since the select signal COLB is active, the selective sense amplifier SSA detects and outputs data stored in the B-side memory cell MC (one of the first to N-th memory cells differing from the first memory cell in a broad sense), that is, the memory cell MC- 1 B. When the latch signal SLA falls at a timing C 8 , the data line driver cell  110 A-R latches the data stored in the memory cell MC- 1 B. 
     The wordline WL 2  is selected at a timing C 9  so that the memory cells MC- 2 A and MC- 2 B are selected. In this case, since the select signal COLB is active, the selective sense amplifier SSA detects and outputs data stored in the B-side memory cell MC, that is, the memory cell MC- 2 B. When the latch signal SLB falls at a timing C 10 , the data line driver cell  110 B-R latches the data stored in the memory cell MC- 2 B. 
     The data latch operation of the data line driver  100  by reading data twice in the 1H period differing from the 1H period shown in  FIG. 26A  is completed in this manner. 
     According to such a read method, data is stored in each memory cell MC of the RAM  200  as shown in  FIG. 27 . Data RA- 1 A to RA- 6 A and data RA- 1 B to RA- 6 B are 6-bit R subpixel data to be supplied to the data line driver cell  110 A-R, for example. The data RA- 1 A to RA- 6 A is R subpixel data in the 1H period shown in  FIG. 26A , and the data RA- 1 B to RA- 6 B is R subpixel data in the 1H period shown in  FIG. 26B . 
     Data RB- 1 A to RB- 6 A and data RB- 1 B to RB- 6 B are 6-bit R subpixel data to be supplied to the data line driver cell  110 B-R. The data RB- 1 A to RB- 6 A is R subpixel data in the 1H period shown in  FIG. 26A , and the data RB- 1 B to RB- 6 B is R subpixel data in the 1H period shown in  FIG. 26B . 
     As shown in  FIG. 27 , the data RA- 1 A (data latched by the data line driver  100 A) and the data RB- 1 A (data latched by the data line driver  100 B) are stored in the RAM  200  in that order along the direction X. 
     The data RA- 1 A (data latched by the data line driver  100 A in the 1H period shown in  FIG. 26A ), the data RA- 1 B (data latched by the data line driver  100 A in the 1H period shown in  FIG. 26A ), the data RA- 2 A (data latched by the data line driver  100 A in the 1H period shown in  FIG. 26A ), the data RA- 2 B (data latched by the data line driver  100 A in the 1H period shown in  FIG. 26A ), . . . are stored in the RAM  200  in that order along the direction Y. Specifically, the data latched by the data line driver  100 A in one 1H period and the data latched by the data line driver  100 A in another 1H period are alternately stored in the RAM  200  along the direction Y. 
     In the read method shown in  FIGS. 26A and 26B , data is read twice in the 1H period, and different wordlines are selected in the 1H period. A single wordline is selected twice in one vertical period (i.e. one frame period). This is because the two pairs of bitlines BL and /BL are connected with the selective sense amplifier SSA. Therefore, when three or more pairs of bitlines BL and /BL are connected with the selective sense amplifier SSA, a single wordline is selected three or more times in one vertical period. 
     In the embodiment, the wordline WL is controlled by the wordline control circuit  240  shown in  FIG. 4 , for example. 
     3.4 Arrangement of Data Read Control Circuit 
       FIG. 20  shows two memory cell arrays  200 A and  200 B and peripheral circuits provided in two RAMs  200  formed by using the horizontal cells shown in  FIG. 17B . 
       FIG. 20  is a block diagram showing an example in which two RAMs  200  are adjacent to each other as shown in  FIG. 3A . A row decoder (wordline control circuit in a broad sense)  240 , an output circuit  260 , and a CPU write/read circuit  280  are provided for each of the two memory cell arrays  200 A and  200 B as dedicated circuits. A CPU /LCD control circuit  250  and a column decoder  270  are provided as circuits common to the two memory cell arrays  200 A and  200 B. 
     The row decoders  240  control the wordlines WL of the RAMs  200 A and  200 B based on signals from the CPU/LCD control circuit  250 . Since data read control from each of the two memory cell arrays  200 A and  200 B to the LCD is performed by the row decoder  240  and the CPU/LCD control circuit  250 , the row decoder  240  and the CPU/LCD control circuit  250  serve as a data read control circuit in a broad sense. The CPU/LCD control circuit  250  controls the two row decoders  240 , two output circuits  260 , two CPU write/read circuits  280 , and one column decoder  270  based on control by an external host, for example. 
     The two CPU write/read circuits  280  write data from the host into the memory cell arrays  200 A and  220 B, or read data stored in the memory cell arrays  200 A and  220 B and output the data to the host based on signals from the CPU/LCD control circuit  250 . The column decoder  270  controls selection of the bitlines BL and /BL of the memory cell arrays  200 A and  200 B based on signals from the CPU/LCD control circuit  250 . 
     The output circuit  260  includes a plurality of sense amplifiers  211  to which 1-bit data is respectively input as described above, and outputs M-bit data output from each of the memory cell arrays  200 A and  200 B upon selection of two different wordlines WL in the 1H period to the data line driver  100 , for example. When four RAMs  200  are provided as shown in  FIG. 3A , two CPU/LCD control circuits  250  control four column decoders  270  based on a single wordline control signal RAC shown in  FIG. 10 , so that the wordlines WL having the same column address are selected at the same time in the four memory cell arrays. 
     Since the number of bits M read at one reading is reduced by reading data from each of the memory cell arrays  200 A and  200 B twice in the 1H period, the size of the column decoder  270  and the CPU write/read circuit  280  is halved. When two RAMs  200  are adjacent to each other as shown in  FIG. 3A , since the CPU/LCD control circuit  250  and the column decoder  260  can be used in common for the two memory cell arrays  200 A and  200 B, the size of the RAM  200  can be reduced. 
     When using the horizontal cells shown in  FIG. 17B , since the number of memory cells MC connected with each of the wordlines WL 1  and WL 2  is as small as M as shown in  FIG. 19 , the interconnect capacitance of the wordline is relatively small. Therefore, it is unnecessary to hierarchize the wordline by using a main-wordline and a sub-wordline. 
     4. Modification 
       FIG. 28  shows a modification according to the embodiment. In  FIG. 11A , the data line driver  100  is divided into the data line drivers  100 A and  100 B in the direction X, for example. The R subpixel data line driver cell, the G subpixel data line driver cell, and the B subpixel data line driver cell are provided in each of the data line drivers  100 A and  100 B when displaying a color image. 
     In the modification shown in  FIG. 28 , the data line driver is divided into three data line drivers  100 -R,  100 -Q and  100 -B in the direction X. A plurality of R subpixel data line driver cells  110 -R 1 ,  110 -R 2 , . . . are provided in the data line driver  100 -R, and a plurality of G subpixel data line driver cells  110 -G 1 ,  110 -G 2 , . . . are provided in the data line driver  100 -G. Likewise, a plurality of B subpixel data line driver cells  110 -B 1 ,  110 -B 2 , . . . are provided in the data line driver  100 -B. 
     In the modification shown in  FIG. 28 , data is read three times in the 1H period. For example, when the wordline WL 1  is selected, the data line driver  100 -R latches data output from the RAM  200  in response to the selection of the wordline WL 1 . This causes data stored in the memory cell group MCS31 to be latched by the data line driver  100 -R 1 , for example. 
     When the wordline WL 2  is selected, the data line driver  100 -G latches data output from the RAM  200  in response to the selection of the wordline WL 2 . This causes data stored in the memory cell group MCS 32  to be latched by the data line driver  100 -G 1 , for example. 
     When the wordline WL 3  is selected, the data line driver  100 -B latches data output from the RAM  200  in response to the selection of the wordline WL 3 . This causes data stored in the memory cell group MCS 33  to be latched by the data line driver  100 -B 1 , for example. 
     The above description also applies to the memory cell groups MCS 34 , MCS 35 , and MCS 36 . Data stored in the memory cell groups MCS 34 , MCS 35 , and MCS 36  is respectively stored in the data line driver cells  110 -R 2 ,  110 -G 2 , and  110 -B 2 , as shown in  FIG. 28 . 
       FIG. 29  is a diagram showing a timing chart of this three-stage read operation. The wordline WL 1  is selected at a timing D 1  shown in  FIG. 29 , and the data line driver  100 -R latches data from the RAM  200  at a timing D 2 . This causes data output by the selection of the wordline WL 1  to be latched by the data line driver  100 -R. 
     The wordline WL 2  is selected at a timing D 3 , and the data line driver  100 -G latches data from the RAM  200  at a timing D 4 . This causes data output by the selection of the wordline WL 2  to be latched by the data line driver  100 -G. 
     The wordline WL 3  is selected at a timing D 5 , and the data line driver  100 -B latches data from the RAM  200  at a timing D 6 . This causes data output by the selection of the wordline WL 3  to be latched by the data line driver  100 -B. 
     According to the above-described operation, data is stored in the memory cells MC of the RAM  200  as shown in  FIG. 30 . For example, data R 1 - 1  shown in  FIG. 30  indicates 1-bit data when the R subpixel has a 6-bit grayscale, and is stored in one memory cell MC. 
     For example, the data R 1 - 1  to R 1 - 6  is stored in the memory cell group MCS 31  shown in  FIG. 28 , the data G 1 - 1  to G 1 - 6  is stored in the memory cell group MCS 32 , and the data B 1 - 1  to B 1 - 6  is stored in the memory cell group MCS 33 . Likewise, the data R 2 - 1  to R 2 - 6 , G 2 - 1  to G 2 - 6 , and B 2 - 1  to B 2 - 6  is respectively stored in groups MCS 34  to MCS 36 , as shown in  FIG. 30 . 
     For example, the data stored in the memory cell groups MCS 31  to MCS 33  may be considered to be data for one pixel, and is data for driving the data lines differing from the data lines corresponding to the data stored in the memory cell groups MCS 34  to MSC 36 . Therefore, data in pixel units can be sequentially written into the RAM  200  along the direction Y. 
     Among the data lines provided in the display panel  10 , the data line corresponding to the R subpixel is driven, the data line corresponding to the G subpixel is then driven, and the data line corresponding to the B subpixel is then driven. Therefore, since all the data lines corresponding to the R subpixels have been driven even if a delay occurs in each reading when reading data three times in the 1H period, for example, the area of the region in which an image is not displayed due to the delay is reduced. Therefore, deterioration of display such as a flicker can be reduced. 
     5. Effect of Embodiment 
     In a related-art integrated circuit device, since the number of memory cells connected with one wordline WL must be equal to the number of grayscale bits of the pixels corresponding to all the data lines of the display panel as shown in  FIG. 8 , the degrees of freedom of the layout are decreased. In a related-art integrated circuit device, when dividing the display memory into RAM blocks, the display memory is divided into blocks in the direction in which the wordline WL extends, and the RAM blocks are disposed along the direction in which the wordline WL extends, as shown in  FIG. 9A . 
     In the embodiment, as shown in  FIG. 9B , the RAM blocks  205 - 1  divided in the direction X in which the wordline WL extends are rotated at 90 degrees and disposed along the direction X in which the bitline BL extends. This enables the RAM blocks to be disposed in the integrated circuit device in a way completely differing from the related-art uniform layout. 
     As shown in  FIG. 19 , the sense amplifier  210  can be disposed within the range of the long side MCY of the memory cell MC by disposing the wordline WL along the direction Y in which the long side MCY of the memory cell MC extends. Moreover, since the direction X in which the bitline BL (omitted in  FIG. 19 ) extends coincides with the short side MCX of the memory cell MC, the number of memory cells connected in common with the bitline can be increased even when the size of the RAM block in the direction in which the bitline is formed is limited. Specifically, since an efficient layout can be achieved, cost can be reduced. 
     As shown in  FIGS. 9C and 9D , data is read from the RAM  200  a plurality of times in the 1H period. Therefore, the number of memory cells MC connected with one wordline can be reduced, or the data line driver  100  can be divided. For example, since the number of memory cells MC corresponding to one wordline can be adjusted by changing the number of readings in the 1H period, the length RX in the direction X and the length RY in the direction Y of the RAM  200  can be appropriately adjusted. Moreover, the number of divisions of the data line driver  100  can be changed by adjusting the number of readings in the 1H period. 
     Moreover, the number of blocks of the data line driver  100  and the RAM  200  can be easily changed or the layout size of the data line driver  100  and the RAM  200  can be easily changed corresponding to the number of data lines provided in the display region  12  of the drive target display panel  10 . Therefore, the display driver  20  can be designed while taking other circuits provided to the display driver  20  into consideration, whereby design cost of the display driver  20  can be reduced. For example, when only the number of data lines is changed corresponding to the design change in the drive target display panel  10 , the major design change target may be the data line driver  100  and the RAM  200 . In this case, since the layout size of the data line driver  100  and the RAM  200  can be flexibly designed in the embodiment, a known library may be used for other circuits. Therefore, the embodiment enables effective utilization of the limited space, whereby design cost of the display driver  20  can be reduced. 
     In the embodiment, since data is read a plurality of times in the 1H period, M×2 memory cells MC can be provided in the direction Y of the RAM  200  to which M-bit data is output by the sense amplifier SSA as shown in  FIG. 21A . This enables the memory cells MC to be efficiently arranged, whereby the chip area can be reduced. 
     In the display driver  24  of the comparative example shown in  FIG. 8 , since the wordline WL is very long, a certain amount of electric power is required so that a variation due to a data read delay from the RAM  205  does not occur. Moreover, since the wordline WL is very long, the number of memory cells connected with one wordline WL 1  is increased, whereby the parasitic capacitance of the wordline WL is increased. An increase in the parasitic capacitance may be dealt with by dividing the wordlines WL and controlling the divided wordlines. However, it is necessary to provide an additional circuit. 
     In the embodiment, the wordlines WL 1  and WL 2  and the like are formed to extend along the direction Y as shown in  FIG. 11A , and the length of each wordline is sufficiently small in comparison with the wordline WL of the comparative example. Therefore, the amount of electric power required to select the wordline WL 1  is reduced. This prevents an increase in power consumption even when reading data a plurality of times in the 1H period. 
     When the 4BANK RAMs  200  are provided as shown in  FIG. 3A , the wordline select signal and the latch signals SLA and SLB are controlled in the RAM  200  as shown in  FIG. 11B . These signals may be used in common for each of the 4BANK RAMs  200 , for example. 
     In more detail, the same data line control signal SLC (data line driver control signal) is supplied to the data line drivers  100 - 1  to  100 - 4 , and the same wordline control signal RAC (RAM control signal) is supplied to the RAMs  200 - 1  to  200 - 4 , as shown in  FIG. 10 . The data line control signal SLC includes the latch signals SLA and SLB shown in  FIG. 11B , and the RAM control signal RAC includes the wordline select signal shown in  FIG. 11B , for example. 
     Therefore, the wordline of the RAM  200  is selected similarly in each BANK, and the latch signals SLA and SLB supplied to the data line driver  100  fall similarly. Specifically, the wordline of one RAM  200  and the wordline of another RAM  200  are selected at the same time in the 1H period. This enables the data line drivers  100  to drive the data lines normally. 
     Although only some embodiments of the invention have been described in detail above, those skilled in the art will readily appreciate that many modifications are possible in the embodiments without departing from the novel teachings and advantages of this invention. Accordingly, all such modifications are intended to be included within the scope of this invention. 
     For example, the terms mentioned in the specification or the drawings at least once together with different terms in a broader sense or a similar sense may be replaced with the different terms in any part of the specification or the drawings. 
     In the embodiment, image data for one display frame can be stored in the RAMs  200  provided in the display driver  20 , for example. However, the invention is not limited thereto. 
     The display panel  10  may be provided with k (k is an integer larger than 1) display drivers, and 1/k of the image data for one display frame may be stored in each of the k display drivers. In this case, when the total number of data lines DL for one display frame is denoted by DLN, the number of data lines driven by each of the k display drivers is DLN/k.