Patent Publication Number: US-2022238640-A1

Title: Semiconductor Structure and Method of Forming the Same

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     The present application is a continuation application of International Patent Application No. PCT/CN2021/100517, filed on Jun. 17, 2021, which claims the right of priority of the Chinese Patent Application No. 202110110494.9, filed on Jan. 27, 2021 and entitled “Semiconductor Structure and Method of Forming the Same”. The entire contents of International Patent Application No. PCT/CN2021/100517 and Chinese Patent Application No. 202110110494.9 are herein incorporated by reference. 
    
    
     TECHNICAL FIELD 
     The present application relates to the technical field of semiconductor fabrication, and more particularly to a semiconductor structure and its forming method. 
     BACKGROUND 
     The dynamic random access memory (DRAM) is a semiconductor structure frequently used in such electronic devices as computers, it consists of a plurality of storage cells, each of which usually includes transistors and capacitors. The gate electrode of a transistor is electrically connected to wordlines, the source electrode is electrically connected to bitlines, and the drain electrode is electrically connected to the capacitor; wordline voltage on the wordlines controls on/off of the transistor, whereby it is possible to read data information stored in the capacitor through the bitlines, or to write data information in the capacitor. 
     In the current processing technique, over-etching tends to occur at the location where capacitance contacts the connection pad, and to form through holes in the substrate. During the process of forming capacitance column structure, the dielectric layer formed by a material having high dielectric constant has an adhesion property weaker than adhesion properties of upper and lower electrodes formed by electrically conductive materials, so that, once through holes are formed, the dielectric layer cannot be completely adhered onto the upper and lower electrodes of the capacitance column, and this causes the upper and lower electrodes to directly contact each other, whereby is engendered the problem of short circuit between the upper electrode and the lower electrode, performance of the memory is finally affected, and the memory might even be entirely discarded. 
     Accordingly, it is a technical problem to be urgently solved at present as how to avoid the problem of short circuit between the upper electrode and the lower electrode in the memory, to improve electrical property of the memory and to enhance fabrication acceptance rate of the memory. 
     SUMMARY 
     The present application provides a semiconductor structure and its forming method, so as to solve the current problem of short circuit tending to occur between the upper electrode and the lower electrode in the memory, to thereby improve electrical property of the memory and to enhance fabrication acceptance rate of the memory. 
     According to multiple embodiments, the first aspect of the present application provides a method of forming a semiconductor structure, and the method comprises: forming a substrate, wherein a plurality of capacitive contacts are provided in the substrate, a plurality of electrically conductive contact pads are provided at the surface of the substrate to be correspondingly connected to a plurality of capacitive contacts on a one to one basis, and a space is present between every two adjacent electrically conductive contact pads; forming a filling layer that is fully filled in the space; forming a stacked structure at the filling layer and a surface of the electrically conductive contact pads, wherein the stacked structure includes a plurality of supporting layers stacked one on another along a direction perpendicular to the substrate, the filling layer is in contact with the one supporting layer disposed at a bottom of the stacked structure, and an etching selection ratio between the filling layer and the supporting layer in contact therewith is greater than a preset value; and etching the stacked structure to form a capacitance hole that runs through the stacked structure and exposes the electrically conductive contact pads. 
     According to multiple embodiments, the second aspect of the present application provides a semiconductor structure that comprises: a substrate, wherein a plurality of capacitive contacts are provided in the substrate, and a plurality of electrically conductive contact pads are provided at the surface of the substrate to be correspondingly connected to a plurality of capacitive contacts on a one to one basis; a filling layer, sandwiched between adjacent electrically conductive contact pads; a stacked structure, wherein the stacked structure includes a plurality of supporting layers stacked one on another along a direction perpendicular to the substrate, the filling layer is in contact with the one supporting layer disposed at a bottom of the stacked structure, and an etching selection ratio between the filling layer and the supporting layer in contact therewith is greater than a preset value; and a capacitance hole, running through the stacked structure and exposing the electrically conductive contact pads. 
    
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         FIG. 1  is a flowchart illustrating the method of forming a semiconductor substrate in a specific embodiment of the present application; 
         FIGS. 2A-2G  are cross-sectional views illustrating the main processing techniques in the process of forming a semiconductor structure in specific embodiments of the present application; and 
         FIG. 3  is a diagram schematically illustrating the semiconductor structure in a specific embodiment of the present application. 
     
    
    
     DESCRIPTION OF EMBODIMENTS 
     Specific embodiments of the semiconductor structure and its forming method as provided by the present application will be described in detail below with reference to the accompanying drawings. 
     A specific embodiment provides a semiconductor structure,  FIG. 1  is a flowchart illustrating the method of forming a semiconductor substrate in a specific embodiment of the present application,  FIGS. 2A-2G  are cross-sectional views illustrating the main processing techniques in the process of forming a semiconductor structure in specific embodiments of the present application, and the semiconductor structure formed in this specific embodiment can be referred from  FIG. 3 . As shown in  FIGS. 1, 2A-2G and 3 , the method of forming a semiconductor structure provided by this specific embodiment comprises the following steps. 
     Step S 11 : forming a substrate  20 , wherein a plurality of capacitive contacts  21  are provided in the substrate  20 , a plurality of electrically conductive contact pads  22  are provided at a surface of the substrate  20  to be correspondingly connected to a plurality of capacitive contacts  21  on a one to one basis, and a space  23  is present between every two adjacent electrically conductive contact pads  22 , as shown in  FIG. 2A . 
     Specifically, the substrate  20  has therein a plurality of active regions arranged in an array, and the capacitive contacts  21  are located in the active regions. The material of the capacitive contacts  21  can be, but is not restricted to be, tungsten. A plurality of electrically conductive contact pads  22  are formed at the surface of the substrate  20 , and each electrically conductive contact pad  22  is in direct contact with one capacitive contact  21  for electrically connecting the capacitive contact  21  with a capacitance column. The material of the electrically conductive contact pads  22  can be identical with the material of the capacitive contacts  21 , both being tungsten for example. In this specific embodiment, the electrically conductive contact pad  22  is staggered by a certain distance relative to the capacitive contact  21  in contact therewith, so as to reduce the contact resistance between the electrically conductive contact pad  22  and the capacitive contact  21 . 
     Step S 12 : forming a filling layer  24  that is fully filled in the space  23 , as shown in  FIG. 2C . 
     Optionally, the specific step of forming a filling layer  24  that is fully filled in the space  23  includes: forming a filling layer  24  that is fully filled in the space  23  and covers the surface of the electrically conductive contact pads  22 , as shown in  FIG. 2B ; and removing the filling layer  24  that covers the surface of the electrically conductive contact pads  22  to expose the electrically conductive contact pads  22 , as shown in  FIG. 2C . 
     Optionally, the specific step of exposing the electrically conductive contact pads  22  includes: employing a chemical mechanical grinding process to remove the filling layer  24  that covers the surface of the electrically conductive contact pads  22 , with the electrically conductive contact pads  22  serving as grind halting layers, to expose the electrically conductive contact pads  22 . 
     Specifically, after the electrically conductive contact pads  22  are formed, a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process is employed to grow one layer of filling layer  24 , the filling layer  24  is fully filled in the space  23  and covers the electrically conductive contact pads  22 , as shown in  FIG. 2B . Thereafter, such a planarizing process as chemical mechanical grinding is employed to planarize the filling layer  24  with the electrically conductive contact pads  22  serving as grind halting layers, so that the top surface of the planarized filling layer  24  (namely the surface of the filling layer  24  facing away from the substrate  20 ) is flush with the top surface of the electrically conductive contact pads  22 . 
     Step S 13 : forming a stacked structure  25  at the filling layer  24  and a surface of the electrically conductive contact pads  22 , wherein the stacked structure  25  includes a plurality of supporting layers stacked one on another along a direction perpendicular to the substrate  20 , the filling layer  24  is in contact with the one supporting layer disposed at a bottom of the stacked structure  25 , and an etching selection ratio between the filling layer  24  and the supporting layer in contact therewith is greater than a preset value, as shown in  FIG. 2E . 
     To facilitate subsequent selective etching, and to fully avoid over-etching of the filling layer  24 , the preset value is optionally 3. It is further possible for persons skilled in the art to base on actual requirements to set the preset value as 5. 
     Optionally, the specific step of forming a stacked structure  25  at the filling layer  24  and a surface of the electrically conductive contact pads  22  includes: forming a first supporting layer  251  at the filling layer  24  and the surface of the electrically conductive contact pads  22 , an etching selection ratio between the filling layer  24  and the first supporting layer  251  being greater than a preset value, as shown in  FIG. 2D ; forming a sacrificing layer  252  at a surface of the first supporting layer  251 ; and forming a second supporting layer  253  at a surface of the sacrificing layer  252 . 
     Specifically, after the filling layer  24  is planarized, the first supporting layer  251  is deposited, so that the first supporting layer  251  covers the filling layer  24  and the electrically conductive contact pads  22 ; subsequently, the sacrificial layer  252  is deposited onto the surface of the first supporting layer  251 ; thereafter, the second supporting layer  253  is deposited onto the surface of the sacrificial layer  252 . The material of the first supporting layer  251  can be identical with the material of the second supporting layer  253 , both being a nitride material for example (silicon nitride, for instance). The material of the sacrificial layer  252  can be an oxide material (silica, for instance). 
     Description is made to this specific embodiment with the stacked structure  25  including two supporting layers and one sacrificial layer as an example, whereas in other specific embodiments, it is also possible for persons skilled in the art to base on actual requirements to provide a plurality of supporting layers and a plurality of sacrificial layers, both of which are alternatively arranged along a direction perpendicular to the substrate  20 . 
     In order to further increase the etching selection ratio between the first supporting layer  251  and the filling layer  24 , to thereby further avoid short circuit between upper electrode layer and lower electrode layer to be subsequently formed, optionally, the material of the first supporting layer  251  is SiN, and the material of the filling layer  24  is one of SiNCH and SiCN or a combination of the two. 
     Step S 14 : etching the stacked structure  25  to form a capacitance hole  26  that runs through the stacked structure  25  and exposes the electrically conductive contact pads  22 , as shown in  FIG. 2F . 
     Optionally, the specific step of forming a capacitance hole  26  that runs through the stacked structure  25  and exposes the electrically conductive contact pads  22  includes: etching the stacked structure  25 , with the electrically conductive contact pads  22  and the filling layer  24  serving as halting layers, to form the capacitance hole  26  that runs through the stacked structure  25  and exposes the electrically conductive contact pads  22 . 
     Specifically, after the stacked structure  25  is formed, a dry etching process can be employed to etch the stacked structure  25  along a direction perpendicular to the substrate  20  to form the capacitance hole  26  that runs through only the stacked structure  25  along a direction perpendicular to the substrate  20 , on the bottom of the capacitance hole  26  are exposed the electrically conductive contact pads  22 , as shown in  FIG. 2F . 
     Since the filling layer  24  is formed between adjacent electrically conductive contact pads  22  in this specific embodiment, and since the etching selection ratio between the filling layer  24  and the supporting layer (the first supporting layer  251  for example) contacting therewith at the very bottom of the stacked structure  25  is relatively high, over-etching of the filling layer  24  can be avoided during the process of etching the stacked structure  25  and forming the capacitance hole  26 , whereby is avoided forming holes in the filling layer  24 , and the problem of short circuit between the upper electrode layer and the lower electrode layer in the capacitance column is essentially avoided. 
     Optionally, the following step is further included after forming a capacitance hole  26  that runs through the stacked structure  25  and exposes the electrically conductive contact pads  22 : forming a capacitance column in the capacitance hole  26 , wherein the capacitance column includes a lower electrode layer  27 , a dielectric layer  28  and an upper electrode layer  29  stacked along a radial direction of the capacitance hole  26 , and the lower electrode layer  27  is in contact with the electrically conductive contact pads  22 . 
     Specifically, after the capacitance hole  26  is formed, a lower electrode material is deposited at the inner wall of the capacitance hole  26  and the top surface of the stacked structure  25  to form the lower electrode layer  27 , as shown in  FIG. 2G . Subsequently, the lower electrode layer  27  covering the top surface of the stacked structure  25  is removed, and partial third supporting layer  253  and the entire sacrificial layer  252  are removed via an etching process. Thereafter, a material having a high dielectric constant is deposited to form the dielectric layer  28  that covers the surface of the lower electrode layer  27 , the surface of the third supporting layer  253  and the surface of the first supporting layer  251 . Finally, an upper electrode material is deposited to form the upper electrode layer  29  that covers the surface of the dielectric layer  28 , as shown in  FIG. 3 . The material of the lower electrode layer  27  can be identical with the material of the upper electrode layer  29 , both being TiN for example. 
     Besides the above, the specific embodiment further provides a semiconductor structure.  FIG. 3  is a diagram schematically illustrating the semiconductor structure in a specific embodiment of the present application. The semiconductor structure provided by this specific embodiment can be formed by the method shown in  FIGS. 1 and 2A-2G . As shown in  FIGS. 2A-2G and 3 , the semiconductor structure comprises: a substrate  20 , wherein a plurality of capacitive contacts  21  are provided in the substrate  20 , and a plurality of electrically conductive contact pads  22  are provided at a surface of the substrate  20  to be correspondingly connected to a plurality of capacitive contacts  21  on a one to one basis; a filling layer  24 , sandwiched between adjacent electrically conductive contact pads  22 ; a stacked structure  25 , wherein the stacked structure  25  includes a plurality of supporting layers stacked one on another along a direction perpendicular to the substrate  20 , the filling layer  24  is in contact with the one supporting layer disposed at a bottom of the stacked structure  25 , and an etching selection ratio between the filling layer  24  and the supporting layer in contact therewith is greater than a preset value; and a capacitance hole  26 , running through the stacked structure  25  and exposing the electrically conductive contact pads  22 . 
     Optionally, the preset value is 3. 
     Optionally, the stacked structure  25  includes a first supporting layer  251  disposed at a surface of the filling layer  24  and a second supporting layer  253  disposed above the first supporting layer  251 , and an etching selection ratio between the filling layer  24  and the first supporting layer  251  is greater than a preset value. 
     Optionally, the material of the first supporting layer  251  is SiN, and the material of the filling layer  24  is one of SiNCH and SiCN or a combination of the two. 
     Optionally, a top surface of the filling layer  24  is flush with a top surface of the electrically conductive contact pad  22 . 
     Optionally, the electrically conductive contact pads  22  are disposed to be staggered relative to the capacitive contacts  21  correspondingly connected thereto. 
     Optionally, the semiconductor structure further comprises a capacitance column disposed in the capacitance hole  26 , wherein the capacitance column includes a lower electrode layer  27 , a dielectric layer  28  and an upper electrode layer  29  stacked along a radial direction of the capacitance hole  26 , and the lower electrode layer  27  is in contact with the electrically conductive contact pads  22 . 
     The semiconductor structure and its forming method provided by the specific embodiments avoid the problem of over-etching that tends to occur between adjacent capacitance contact pads during the process of etching the stacked structure to form the capacitance hole, hence avoid short circuit between the upper electrode and the lower electrode, realize improvement of electrical property of the memory, and enhance fabrication acceptance rate of the memory by providing a filling layer between adjacent electrically conductive contact pads, and by defining that the etching selection ratio between the filling layer and the supporting layer in contact therewith is greater than a preset value, without changing the dimension of the capacitance column 
     What is described above is merely directed to preferred embodiments of the present application. As should be pointed out, persons ordinarily skilled in the art may make further improvements and modifications without departing from the principles of the present application, and all such improvements and modifications shall be regarded to fall within the protection scope of the present application.