Patent Publication Number: US-RE35951-E

Title: CMOS voltage reference with stacked base-to-emitter voltages

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates to voltage reference circuits of the band-gap type. More particularly, this invention relates to band-gap circuits suited for use with CMOS integrated-circuit (IC) chips. 
     2. Description of the Prior Art 
     Band-gap voltage regulators have been used for a number of years for developing reference voltages which remain substantially constant in the face of temperature variations. Such circuits generally develop a voltage proportional to the difference between base-to-emitter voltages (ΔV BE ) of two transistors operated at different current densities. This voltage will have a positive temperature coefficient (TC), an is combined with a V BE  voltage having a negative TC to provide the output signal which varies only a little with temperature changes. Reissue Pat. RE. No. 30,586 (A. P. Brokaw) shows a particularly advantageous band-gap voltage reference requiring only two transistors. 
     Band-gap reference circuits have primarily been employed in bipolar ICs. Efforts have been made to adapt such references for CMOS ICs, but significant problems have been encountered in those efforts. As a result, the devices proposed for CMOS have suffered important defects, particularly undue complexity. 
     One serious problem results from the fact that the ΔV BE  voltage is quite small (e.g. less than 100 mV), so that it must be amplified quite a bit to reach a value suitable for reference purposes. Such amplification is inherent in a band-gap circuit such as shown in U.S. Pat. No. 30,586 referred to above, because the ΔV BE  signal is taken from the collectors of the two transistors. In a CMOS chip made by the usual processes, however, the bipolar transistors available for voltage reference purposes are parasitic transistors, the collectors of which cannot be independently accessed for voltage sensing purposes. In such devices, therefore, the ΔV BE  voltage will not automatically be amplified by the transistors from which it is developed. 
     Moreover, the MOS amplifiers on a CMOS chip have relatively large offset voltages, so that the offset after substantial amplification will show up as a large error compared to the ΔV BE  signal component. For example, to develop a reference voltage of around 5 volts, a 20 mV offset in an amplifier (or comparator) could show up as a 0.5 volt error referred to output or threshold. 
     U.S. Pat. No. 4,622,512 (Brokaw) shows an arrangement for multiplying the V BE  of each of two transistors having different current densities by connecting resistor-string V BE  multipliers to each of the two transistors. This is an effective approach to the problem, but is not fully satisfactory for all applications. 
     SUMMARY OF THE INVENTION 
     In one preferred embodiment of the invention, to be described hereinafter in detail, the voltage reference comprises four pairs of parasitic bipolar transistors with the individual transistors of each pair operated at different current densities. The four low-current-density transistors of these pairs form one sub-set, and are interconnected in a string-like or &#34;stacked&#34; arrangement so that their V BE  &#39;s add together cumulatively. The four high-current-density transistors are similarly interconnected as a second sub-set. 
     End transistors of each string are connected together in such a way as to develop the total cumulative ΔV BE  voltage for both strings of transistors. By arranging the transistors of each sub-set to have equal current densities, the net ΔV BE  voltage will be four times as large as that obtained with a single pair of transistors operated at such different current densities. Such a large ΔV BE  voltage makes possible the development of a stable and precise reference voltage on a CMOS IC chip. 
     The preferred embodiment to be described further includes MOS transistors interconnected with the parasitic bipolar transistors to provide improved operating characteristics. In a second embodiment of the invention, two (or more) strings of opposite-polarity transistors (e.g., NPN vs. PNP) are added to the original two strings to further build up the magnitude of the total ΔV BE  voltage. 
     Other objects, aspects and advantages of the invention will in part be pointed out in, and in part apparent from, the following description of the preferred embodiments of the invention, considered together with the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a circuit diagram showing, in somewhat simplified form, one preferred embodiment of the invention; 
     FIGS. 2A and 2B are a more detailed circuit diagram of the embodiment of FIG. 1; and 
     FIG. 3 is a circuit diagram, in somewhat simplified form, showing an arrangement for further increasing the magnitude of the ΔV BE  voltage. 
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS OF THE INVENTION 
     Referring now to FIG. 1, the voltage reference forming part of a CMOS IC chip comprises four pairs of parasitic bipolar PNP transistors Q4, Q5; Q3, Q6; Q2, Q7; and Q1, Q8. The left-hand transistors of these pairs form one sub-set 30 of transistors which, in this embodiment, are all identical. Each transistor of this sub-set is supplied with current from a corresponding current source in the form of a PMOS transistor (M6, M7, M8, M9) having its drain connected to the emitter of the associated bipolar transistor (Q1, Q2, Q3, Q4). These four PMOS current sources are identical, and in this embodiment each furnishes the corresponding bipolar transistor with a current I of one μA. 
     The right-hand transistors Q5-Q8 of the four transistor pairs form a second sub-set 32 of identical transistors each of which is supplied with a current of 20 μA by a respective PMOS current source M10-M13. The emitter areas of these transistors are one-eighth the emitter areas of the transistors Q1-Q4. Thus, the current density of the transistors in the second sub-set is 160 times the current density of the first sub-set of transistors. For any different-current-density pair of these transistors, the difference in V BE  voltages will be: ##EQU1## or 0.131 volts. 
     The bipolar transistors of each of the two sub-sets 30, 32 are interconnected in a string arrangement wherein the emitter of one transistor is connected to the base of the next adjacent transistor. The collectors of all of the transistors are connected to the chip substrate, as indicated by the three-pronged symbol; the substrate is maintained at the negative supply voltage (in this case -5V). With the emitter-to-base string interconnection shown, the V BE  voltages of the individual transistors add together cumulatively. By connecting together the bases of the two transistors (Q4, Q5) at a common end of the two strings of transistors, a net cumulative ΔV BE  voltage will be developed between circuit points 3 and 4 at the two transistors (Q1, Q8) at the opposite ends of the strings. This net voltage will be four times the ΔV BE  voltage for any single pair of the transistors, or about 0.525 volts. 
     The potentials at circuit points 3 and 4 are connected respectively to the gates of two PMOS transistors M1, M2, which act as a buffer circuit along with M3 and M4. With this arrangement, the potential at circuit point 4 is effectively transferred to circuit point 2 at the upper end of a resistor R1 in series with the left-hand buffer transistor M1. Thus the voltage across R1 will be the net ΔV BE  voltage of (about) 0.525. 
     The resulting current through R1 is PTAT (proportional to absolute temperature) because it is produced by a ΔV BE  voltage. This current is mirrored through M5 to M15 with a ratio producing an M15 current of 2501 (i.e., about 250 μA). This latter current flows through a resistor R2, and through a PNP transistor Q9 and series resistors R3, R4. The lower end of resistor R4 is connected to ground, which is the reference terminal for the final output voltage (that is, the ground terminal is midway between the +5V and -5V supply voltages). 
     The voltage across resistor R2 is, in the preferred embodiment described herein, given by the following expression: ##EQU2## In one preferred embodiment R2=5.13K, and R1=6.565K. 
     The upper end of resistor R2 is connected to the base of a PNP transistor Q10. This transistor is supplied with current by a PMOS transistor M16, producing a current of 500 I. The emitter of Q10 is connected to the voltage reference output terminal which produces an output voltage V OUT  as follows: ##EQU3## 
     In the preferred embodiment, R4 was one-half the size of R3, so that X=0.5 
     The V BE  and ΔV BE  terms are so set that the variations in output voltage with changes in temperature are quite small. 
     The use of buffer transistors M1 through M4 permits a relatively high current to flow in the resistor R1 (i.e., 80 μA as against 1 μA in the PNP transistor Q1). This makes it possible to use a resistor value (about 6.5K) which is practicable to implement. If the 1 μA current of transistor Q1 were arranged to flow through resistor R1, in accordance with prior art concepts, the resistor would have to be about 525 K. A resistor that large would not be manageable in normal processing of an IC chip. The buffer arrangement also allows transistor Q1 to operate at low currents, minimizing Beta effects as well as obtaining high current ratios between individual transistors of each pair without requiring large supply currents. 
     FIGS. 2A and 2B present further details of a voltage reference circuit of the type shown in FIG. 1. The designations applied to certain common elements of FIGS. 1 and 2A, 2B remain the same, for ready comparison. It will be seen that the PMOS current sources for the PNP transistors Q1, etc., actually comprise two MOS transistors (e.g., MP1, MP11), to provide increased output impedance. It also should be noted that the FIGS. 2A and 2B circuit furnishes two separate output voltage (VREFOUTL and VREFOUTR) to provide for use in two-channel stereo equipment, with minimal cross-talk between channels. 
     With further reference to FIGS. 2A and 2B, each of the output transistors Q9, Q11 is supplied with current through respective pairs of cascode-connected MOS transistors MP8, MP19, M30, MP21, to provide for correspondence with the similarly cascoded pairs for the ΔV BE  transistors Q1, Q2, etc. The output transistors Q9, Q11 will have some base current, which is potentially error-producing, and this is compensated for by a circuit including a MOS transistor MN7 connected to the upper end of R2. This transistor is part of a current mirror including MN6 which receives a base current from a bipolar transistor Q12. This base current controls correspondingly the current through MN7, thereby to produce a compensating current at the top of R2, so as to compensate for the base currents of the output transistors. Current for Q12 is supplied by M28, MN6 and MNS, corresponding to MP26, MN4 and MN3 in the right-hand side of the ΔV BE  summation circuit. MN5, MN6 and M28 also control the current to MP28 which sets the bias for the lower-tier row of current source transistors MP1, MP2, etc. At the left-hand edge of FIG. 2A is a start-up circuit comprising MP27; when power is applied, this circuit starts up the voltage reference circuitry and then shuts off. 
     It has been found that still larger ΔV BE  voltages can be produced by incorporating further strings of bipolar transistors. FIG. 3 shows such an arrangement, wherein two additional strings 40, 42 of NPN transistors are connected respectively to corresponding upper ends of PNP transistor strings 30, 32 as shown in FIG. 1. Because these additional transistors are NPN type, rather than PNP type as in the first two transistor strings, their operating voltages can be cascaded downwardly (starting at the upper ends of the strings) while still increasing cumulatively the net ΔV BE  voltage. Approximate voltages at juncture points are shown on the circuit diagram. 
     As in the FIG. 1 circuit, the PNP transistors 30, 32 receive current from PMOS current sources, with the left-hand string transistors receiving 1 μA each and the right-hand PNP transistors receiving 20 μA. The left-hand string emitter areas are eight times that of the right-hand string emitter areas, just as in FIG. 1. 
     The left-hand string of NPN transistors 40 have emitter areas equal to those of the right-hand string of PNP transistors 32 and are supplied with currents of 20 μA by corresponding NMOS current sources. The right-hand string of NPN transistors 42 have emitter area eight times that of the emitter areas of the left-hand transistor string 40, and are supplied with currents of 1 μA by corresponding NMOS current sources. 
     The first transistor Q9 of the left-hand NPN string 40 has its base connected to the emitter of the upper end transistor Q7 of the left-hand string of PNP transistors 30. The remaining transistors of this NPN string 40 are interconnected as before, with the emitter of one transistor connected to the base of the next adjacent transistor. 
     The base of the first transistor Q10 of the right-hand NPN string 42 is connected to the emitter of the upper end transistor Q8 of the right-hand PNP string 32. The remaining transistors of this NPN string are interconnected as before, with the emitter of one transistor being connected to the base of the next adjacent transistor. 
     With this arrangement, the net ΔV BE  voltage can be enlarged by the additive relationship between the four strings of transistors. In one exemplary circuit, a total ΔV BE  voltage of 1.04 is shown. 
     Although preferred embodiments of the invention have been disclosed herein in detail, it is to be understood that this is for the purpose of illustrating the invention, and should not be construed as necessarily limiting the invention since those of skill in this art can readily make various changes and modifications thereto without departing from the scope of the invention as reflected in the claims hereof.