Patent Publication Number: US-2023164456-A1

Title: Analog-to-digital converting circuit for optimizing dual conversion gain operation and operation method thereof

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This U.S. non-provisional patent application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2021-0164970, filed on Nov. 25, 2021 in the Korean Intellectual Property Office, and to Korean Patent Application No. 10-2022-0059736, filed on May 16, 2022 in the Korean Intellectual Property Office, the disclosures of which are incorporated by reference herein in their entireties. 
     BACKGROUND 
     Embodiments of the present disclosure relate to an analog-to-digital converter, and more particularly, relate to an analog-to-digital converting circuit for optimizing a dual conversion gain operation and an operation method thereof. 
     Types of image sensors include charge coupled device (CCD) image sensors, complementary metal-oxide semiconductor (CMOS) image sensors (CISs), etc. The CMOS image sensor generates pixel values using CMOS transistors to generate electrical signals by converting light energy into the electrical signal with a photoelectric conversion element (or device) included for each pixel. The CMOS image sensor obtains information about a captured/photographed image by using the electrical signal generated for each pixel. 
     An analog-to-digital converter (ADC) receives an analog input voltage generated for a pixel and converts the received analog input voltage into a digital signal. The converted digital signal may be provided to other devices. The ADC may be used in various signal processing devices. As the performance of signal processing devices is improved, nowadays, an improved resolution for an analog signal is required. As such, there is used an ADC capable of processing many signals simultaneously or within the same period or providing an improved resolution for each signal. However, the ADC causes an increase of power consumption. 
     SUMMARY 
     Embodiments of the present disclosure provide an analog-to-digital converting circuit for optimizing current consumption of a dual conversion gain operation and a time taken to perform the dual conversion gain operation, an operation method thereof, and an image sensor including the same. 
     According to some embodiments, a circuit includes a first amplifier configured to generate a first output signal by comparing a first pixel signal corresponding to a first conversion gain and a first ramp signal and to generate a second output signal by comparing a second pixel signal corresponding to a second conversion gain and a second ramp signal, and a second amplifier configured to generate a third output signal based on the first output signal and generate a fourth output signal based on the second output signal, and a counter configured to count pulses of the third output signal and the fourth output signal and to output a counting result as a digital signal. The first conversion gain is higher than the second conversion gain. A first power current of the first amplifier when the first pixel signal and the first ramp signal are compared is different from a second power current of the first amplifier when the second pixel signal and the second ramp signal are compared. 
     According to some embodiments, an image sensor includes a pixel array configured to output a first pixel signal corresponding to a first conversion gain and a second pixel signal corresponding to a second conversion gain from pixels sharing a floating diffusion region, a ramp signal generator configured to generate a first ramp signal and a second ramp signal, and an analog-to-digital converting circuit configured to output a digital signal based on the first pixel signal and the second pixel signal. The analog-to-digital converting circuit includes an amplifier configured to generate a first output signal by comparing the first pixel signal and the first ramp signal and generate a second output signal by comparing the second pixel signal and the second ramp signal. The first conversion gain is higher than the second conversion gain. A first power current of the amplifier when the first pixel signal and the first ramp signal are compared is different from a second power current of the amplifier when the second pixel signal and the second ramp signal are compared. 
     According to some embodiments, an analog-to-digital converting circuit includes an amplifier. An operation method of the analog-to-digital converting circuit includes generating, at the amplifier, a first output signal by comparing a first pixel signal corresponding to a first conversion gain and a first ramp signal based on a first power current, generating, at the amplifier, a second output signal by comparing a second pixel signal corresponding to a second conversion gain and a second ramp signal based on a second power current, and adjusting a power current of the amplifier, and the first conversion gain is higher than the second conversion gain. 
     According to some embodiments, a circuit includes a first transistor configured to receive a first pixel signal corresponding to a first conversion gain and a second pixel signal corresponding to a second conversion gain, a second transistor configured to receive a first ramp signal and a second ramp signal, a first current source that is connected with a first source terminal of the first transistor and a second source terminal of the second transistor at a common node and configured to output a first sub power current, a switch that is connected with the first source terminal and the second source terminal at the common node, and a second current source that is connected with the switch and configured to output a second sub power current. The first conversion gain is higher than the second conversion gain. A first power current of the circuit when the first pixel signal and the first ramp signal are compared is different from a second power current of the circuit when the second pixel signal and the second ramp signal are compared. When the first pixel signal and the first ramp signal are compared, the switch is turned on, and the first power current is equal to a sum of the first sub power current and the second sub power current. When the second pixel signal and the second ramp signal are compared, the switch is turned off, and the second power current is equal to the first sub power current. A first output signal is generated by comparing the first pixel signal and the first ramp signal, and a second output signal is generated by comparing the second pixel signal and the second ramp signal. 
    
    
     
       BRIEF DESCRIPTION OF THE FIGURES 
       The above and other objects and features of the present disclosure will become apparent by describing in detail embodiments thereof with reference to the accompanying drawings. 
         FIG.  1    illustrates an example of a configuration of an image processing block according to an embodiment of the present disclosure. 
         FIG.  2    illustrates an example of a configuration of an image sensor of the image processing block of  FIG.  1   . 
         FIG.  3    is a circuit diagram illustrating an example of one pixel group among pixel groups of a pixel array of the image sensor of  FIG.  2   . 
         FIG.  4 A  is a circuit diagram illustrating a floating diffusion region under a high conversion gain condition in which a dual conversion transistor of the pixel group of  FIG.  3    is turned off. 
         FIG.  4 B  is a circuit diagram illustrating a floating diffusion region under a low conversion gain condition in which a dual conversion transistor of the pixel group of  FIG.  3    is turned on. 
         FIG.  5    illustrates an example of a configuration of an analog-to-digital converting circuit of the image sensor of  FIG.  2   . 
         FIG.  6    is a circuit diagram illustrating an example of a first amplifier of the analog-to-digital converting circuit of  FIG.  5   . 
         FIG.  7 A  is a timing diagram illustrating a process in which an ADC circuit of the analog-to-digital converting circuit of  FIG.  5    processes a pixel signal depending on a reset-sig-sig-reset (RSSR) method. 
         FIG.  7 B  is a timing diagram illustrating a process in which an ADC circuit of the analog-to-digital converting circuit of  FIG.  5    processes a pixel signal depending on a reset-reset-sig-sig (RRSS) method. 
         FIG.  8 A  illustrates an example in which the offset of the ramp signal RAMP is adjusted in the timing diagram of  FIG.  7 A . 
         FIG.  8 B  illustrates an example in which the offset of the ramp signal RAMP is adjusted in the timing diagram of  FIG.  7 B . 
         FIG.  8 C  illustrates another example in which the offset of the ramp RAMP is adjusted in the timing diagram of  FIG.  7 B . 
         FIG.  9    is a flowchart illustrating an operation method of an analog-to-digital converting (ADC) circuit for optimizing a dual conversion gain operation according to an embodiment of the present disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     Below, embodiments of the present disclosure will be described in detail and clearly to such an extent that one skilled in the art easily carries out the teachings of the present disclosure. 
     In the detailed description, components described with reference to the terms “unit”, “module”, “block”, “˜er or ˜or”, etc. and function blocks illustrated in drawings will be implemented with software, hardware, or a combination thereof. For example, the software may be a machine code, firmware, an embedded code, and application software. For example, the hardware may include an electrical circuit, an electronic circuit, a processor, a computer, an integrated circuit, integrated circuit cores, a pressure sensor, an inertial sensor, a microelectromechanical system (MEMS), a passive element, or a combination thereof. 
       FIG.  1    illustrates an example of a configuration of an image processing block  10  according to an embodiment of the present disclosure. The image processing block  10  may be implemented as a part of various electronic devices such as a smartphone, a digital camera, a laptop computer, and a desktop computer. The image processing block  10  may include a lens  12 , an image sensor  14 , an ISP front end block  16  (image signal processor front end block), and an image signal processor  18 . 
     A light may be reflected by an object, a scenery, etc. targeted for photographing, and the lens  12  may receive the reflected light. The image sensor  14  may generate an electrical signal based on the light received through the lens  12 . For example, the image sensor  14  may be implemented with a complementary metal-oxide semiconductor (CMOS) image sensor or the like. For example, the image sensor  14  may be a multi-pixel image sensor having a dual pixel structure or a tetracell structure. 
     The image sensor  14  may include a pixel array. The pixel array may convert a light into electrical signals and may generate pixel values for each pixel. A ratio at which a light is converted into an electrical signal (e.g., a voltage) may be defined as a conversion gain. In particular, the pixel array may generate pixel signals under a low conversion gain condition and a high conversion gain condition, by using a change of the conversion gain, that is, a dual conversion gain. 
     In addition, the image sensor  14  may include an analog-to-digital converting (ADC) circuit for performing a correlated double sampling (CDS) operation on the pixel values. A configuration of the image sensor  14  will be described in detail with reference to  FIG.  2   . 
     The ISP front end block  16  may perform pre-processing on an electrical signal output from the image sensor  14  so that the input to the image signal processor  18  is appropriate for processing by the image signal processor  18 . Also, the ISP front end block  16  of the present disclosure may selectively perform pre-processing for an (e.g., first) electrical signal corresponding to the low conversion gain condition and pre-processing for an (e.g., second) electrical signal corresponding to the high conversion gain condition, based on an output of the image sensor  14 . 
     The image signal processor  18  may generate image data associated with the photographed object or scenery by appropriately processing the electrical signal pre-processed by the ISP front end block  16 . To this end, the image signal processor  18  may perform various processing operations such as color correction, auto white balance, gamma correction, color saturation correction, formatting, bad pixel correction, and hue correction. 
     One lens  12 , one image sensor  14  and one ISP front end block  16  are illustrated in  FIG.  1   . However, in another embodiment, the image processing block  10  may include a plurality of lenses, a plurality of image sensors, and a plurality of ISP front end blocks. In this case, the plurality of lenses may have different fields of view. Also, the plurality of image sensors may have different functions, different performances, and/or different characteristics, and may respectively include pixel arrays of different configurations. 
       FIG.  2    illustrates an example of a configuration of the image sensor  14  of the image processing block of  FIG.  1   . An image sensor  100  may correspond to the image sensor  14  in  FIG.  1    and may include a pixel array  110 , a row driver  120 , a ramp signal generator  130 , a voltage buffer  140 , an ADC circuit  150 , a timing controller  160 , and a buffer  170 . 
     The pixel array  110  may include a plurality of pixels arranged in the form of a matrix, that is, arranged along rows and columns. In the context of a pixel array  110 , references to pixels should be understood as references to a discrete hardware circuit element or a discrete combination of hardware circuit elements for each pixel represented in the pixel array. Each of the plurality of pixels may include a photoelectric conversion element. For example, the photoelectric conversion element may include a photo diode, a photo transistor, a photo gate, a pinned photo diode, or the like. 
     The pixel array  110  may include a plurality of pixel groups PG. Each pixel group PG may include two or more pixels, that is, a plurality of pixels. A plurality of pixels constituting the pixel group PG may share one floating diffusion region or a plurality of floating diffusion regions. An example in which the pixel array  110  includes the pixel groups PG arranged in the form of a matrix with four rows and four columns (i.e., includes 4×4 pixel groups PG) is illustrated in  FIG.  2   . However, the present disclosure is not limited thereto. 
     The pixel group PG may include pixels of the same color. For example, pixels of the pixel group PG may include a red pixel to convert a light of a red spectrum into an electrical signal, a green pixel to convert a light of a green spectrum into an electrical signal, or a blue pixel to convert a light of a blue spectrum into an electrical signal. For example, the pixels constituting the pixel array  110  may be arranged in the form of a tetra-Bayer pattern. 
     The pixels of the pixel array  110  may be configured to output pixel signals through column lines CL 1  to CL 4 , depending on the intensity or the amount of light received from the outside. For example, the pixel array  110  may be configured to output a first pixel signal corresponding to a first conversion gain and a second pixel signal corresponding to a second conversion gain from pixels sharing a floating diffusion region. For example, the pixel signal may be an analog signal corresponding to the intensity or the amount of light received from the outside. 
     As described with reference to  FIG.  1   , the pixel array  110  may generate pixel signals under the low conversion gain condition and the high conversion gain condition depending on ambient luminance of an object. Below, a pixel signal generated under the low conversion gain condition may be referred to as a low conversion gain pixel signal, and a pixel signal generated under the high conversion gain condition may be referred to as a high conversion gain pixel signal. The pixel signals may pass through voltage buffers (e.g., source followers) and may then be provided to the ADC circuit  150  through the column lines CL 1  to CL 4 . The ADC circuit  150  may be configured to output a digital signal based on the pixel signals, such as based on the first pixel signal corresponding to a first conversion gain or based on the second pixel signal corresponding to a second conversion gain. The pixel array  110  may change the conversion gain by turning on or turning off a dual conversion transistor, which will be described in detail with reference to  FIG.  3   ,  FIG.  4 A , and  FIG.  4 B . 
     The row driver  120  may select and drive a row of the pixel array  110 . The row driver  120  may decode an address and/or a control signal generated by the timing controller  160  and may generate control signals for selecting and driving a row of the pixel array  110 . For example, the control signals may include a signal for selecting a pixel, a signal for resetting a floating diffusion region, etc. 
     The ramp signal generator  130  may generate a ramp signal RAMP under control of the timing controller  160 . For example, the ramp signal generator  130  may operate in response to a control signal such as a ramp enable signal. When the ramp enable signal is activated, the ramp signal generator  130  may generate the ramp signal RAMP depending on preset values (e.g., a start level, an end level, and a slope). In other words, the ramp signal RAMP may be a signal that increases or decreases along a preset slope during a specific time. The ramp signal RAMP may be provided to the ADC circuit  150  through the voltage buffer  140 . 
     The ADC circuit  150  may receive pixel signals from a plurality of pixels through the column lines CL 1  to CL 4 . The ADC circuit  150  may receive the ramp signal RAMP from the ramp signal generator  130  through the voltage buffer  140 . The ADC circuit  150  may operate based on a correlated double sampling (CDS) technique for obtaining a reset signal and an image signal from the received pixel signal and extracting a difference between the reset signal and the image signal as an effective signal component. The ADC circuit  150  may include a plurality of comparators COMP and a plurality of counters CNT. 
     In detail, each of the comparators COMP may compare the reset signal of the pixel signal and the ramp signal RAMP, may compare the image signal of the pixel signal and the ramp signal RAMP, and may perform correlated double sampling (CDS) on comparison results. Each of the counters CNT may count pulses of the signal experiencing the correlated double sampling and may output a counting result as a digital signal. An example in which the ADC circuit  150  includes four comparators COMP and four counters CNT is illustrated in  FIG.  2   , but the present disclosure is not limited thereto. 
     Also, the ADC circuit  150  of the present disclosure may make the current consumption in the comparison operation for the low conversion gain pixel signal and the current consumption in the comparison operation for the high conversion gain pixel signal different. In addition, the ramp signal generator  130  may generate the ramp signal RAMP in the comparison operation for the low conversion gain pixel signal and the ramp signal RAMP in the comparison operation for the high conversion gain pixel signal, so as to be different from each other. Also, even though pixel signals have the same conversion gain, the ramp signal RAMP may be differently generated in the comparison operation for the reset signal and the comparison operation for the image signal. 
     The timing controller  160  may generate a control signal and/or a clock for controlling an operation and/or a timing of each of the row driver  120 , the ramp signal generator  130 , and the ADC circuit  150 . 
     The buffer  170  may include memories MEMs and a sense amplifier SA. The memories MEM may store digital signals output from the corresponding counters CNT of the ADC circuit  150 . The sense amplifiers SA may sense and amplify the digital signals stored in the memories MEMs. The sense amplifiers SA may output the amplified digital signals as image data IDAT. The image data IDAT may be provided to the ISP front end block  16  of  FIG.  1   . 
       FIG.  3    is a circuit diagram illustrating an example of one of the pixel groups PG of the pixel array  110  of the image sensor of  FIG.  2   .  FIG.  4 A  is a circuit diagram illustrating a floating diffusion region FD 1  under a high conversion gain condition in which a dual conversion transistor DC of the pixel group of  FIG.  3    is turned off.  FIG.  4 B  is a circuit diagram illustrating floating diffusion regions FD 1  and FD 2  under a low conversion gain condition in which the dual conversion transistor DC of the pixel group of  FIG.  3    is turned on. 
     For example, the pixel group PG may include pixels PX 1  to PX 4 , photoelectric conversion elements PD 1  to PD 4 , transfer transistors Tx 1  to Tx 4 , a reset transistor RST, the dual conversion transistor DC, a drive transistor Dx, and a select transistor SEL. An example in which the pixel group PG has a tetracell structure in which four pixels PX 1  to PX 4  respectively include photoelectric conversion elements PD 1  to PD 4  is illustrated in  FIG.  3   , but the present disclosure is not limited thereto. For example, the pixel group PG may be implemented to have various different structures. 
     The first pixel PX 1  may include the first photoelectric conversion element PD 1  and the first transfer transistor Tx 1 , and each of the remaining pixels PX 2 , PX 3 , and PX 4  may also include similar components/elements. The pixels PX 1  to PX 4  may share the reset transistor RST, the dual conversion transistor DC, the drive transistor Dx, and the select transistor SEL. Also, the pixels PX 1  to PX 4  may share the first floating diffusion region FD 1 . 
     The first floating diffusion region FD 1  or the second floating diffusion region FD 2  may accumulate (or integrate) charges corresponding to the amount of incident light. While the transfer transistors Tx 1  to Tx 4  are respectively turned on by transfer signals VT 1  to VT 4 , the first floating diffusion region FD 1  or the second floating diffusion region FD 2  may accumulate (or integrate) charges supplied from the photoelectric conversion elements PD 1  to PD 4 . Because the first floating diffusion region FD 1  is connected with a gate terminal of the drive transistor Dx operating as a source follower amplifier, a voltage corresponding to the charges accumulated in the first floating diffusion region FD 1  may be formed. For example, a capacitance of the first floating diffusion region FD 1  is depicted as a first capacitance CFD 1 . 
     The dual conversion transistor DC may be driven by a dual conversion signal VDC. When the dual conversion transistor DC is turned off, the capacitance of the first floating diffusion region FD 1  may correspond to the first capacitance CFD 1 . In a normal environment, because the first floating diffusion region FD 1  is not easily saturated, there is no need to increase the capacitance (i.e., CFD 1 ) of the first floating diffusion region FD 1 . In this case, the dual conversion transistor DC may be turned off. 
     However, in a high-luminance environment, the first floating diffusion region FD 1  may be easily saturated. To prevent the saturation, the dual conversion transistor DC may be turned on such that the first floating diffusion region FD 1  and the second floating diffusion region FD 2  are electrically connected. As shown in each of  FIG.  4 A  and  FIG.  4 B , each of the first floating diffusion region FD 1  and the second floating diffusion region FD 2  may be connected to different capacitors representing capacitance values, such that the pixel group PG of the pixel array  110  includes one or more capacitor connected with a floating diffusion region for the purpose of obtaining a first capacitance value CFD 1  in the case of the first floating diffusion region FD 1  and a second capacitance value CFD 2  in the case of the second floating diffusion region FD 2 . In this case, a capacitance of the floating diffusion regions FD 1  and FD 2  may be increased to a sum of the first capacitance CFD 1  and a second capacitance CFD 2 . For example, the pixel array  110  may be configured to output a first pixel signal corresponding to a first conversion gain and a second pixel signal corresponding to a second conversion gain from pixels sharing a floating diffusion region. For example, the first pixel signal may correspond to charges stored in the floating diffusion region FD 1  having a first capacitance value, and the second pixel signal may correspond to a sum of charges stored in the floating diffusion region FD 1  and the second floating diffusion region FD 2  having a second capacitance value. 
     The transfer transistors Tx 1  to Tx 4  may be respectively driven by the transfer signals VT 1  to VT 4 . The transfer transistors Tx 1  to Tx 4  may transfer charges generated (or integrated) by the photoelectric conversion elements PD 1  to PD 4  to the first floating diffusion region FD 1  or the second floating diffusion region FD 2 . For example, first ends of the transfer transistors Tx 1  to Tx 4  may be respectively connected with the photoelectric conversion elements PD 1  to PD 4 , and second ends thereof may be connected in common with the first floating diffusion region FD 1 . 
     The reset transistor RST may be driven by a reset signal VRST and may provide a power supply voltage VDD to the first floating diffusion region FD 1  or the second floating diffusion region FD 2 . As such, the charges accumulated in the first floating diffusion region FD 1  or the second floating diffusion region FD 2  may move to a terminal for the power supply voltage VDD, and a voltage of the first floating diffusion region FD 1  or the second floating diffusion region FD 2  may be reset. 
     The drive transistor Dx may amplify a voltage of the first floating diffusion region FD 1  or the second floating diffusion region FD 2  and may generate a pixel signal PIX corresponding to a result of the amplification. The select transistor SEL may be driven by a selection signal VSEL and may select pixels to be read in units of row. When the select transistor SEL is turned on, the pixel signal PIX may be output to the ADC circuit  150  of  FIG.  2    through a column line CL. 
       FIG.  5    illustrates an example of a configuration of the ADC circuit  150  (analog-to-digital converting circuit) of the image sensor of  FIG.  2   . The ADC circuit  150  may include a comparator  151  and a counter  152 . The ADC circuit  150  may convert and output the analog pixel signal PIX from the pixel array  110  into a digital signal DS. For clearness of description and brevity of drawing, an example in which the pixel array  110  includes only one pixel is illustrated in  FIG.  5   , and the configuration and function of the pixel array  110  are identical to those described with reference to  FIG.  3   ,  FIG.  4 A , and  FIG.  4 B . 
     In detail, as described with reference to  FIG.  2   , the comparator  151  may compare the reset signal of the pixel signal PIX and the ramp signal RAMP in a first operation period and in a fourth operation period, may compare the image signal of the pixel signal PIX and the ramp signal RAMP in a second operation period and a third operation period, and may perform correlated double sampling (CDS) on comparison results. The counter  152  may count pulses of a signal experiencing the correlated double sampling (CDS) and may output a counting result as a digital signal.  FIG.  5    will be described with reference to  FIG.  2   ,  FIG.  3   ,  FIG.  4 A , and  FIG.  4 B . 
     For example, the comparator  151  may have a two-stage structure including two amplifiers (i.e., a first amplifier  151 _ 1  and a second amplifier  151 _ 2 ). Each of the first amplifier  151 _ 1  and the second amplifier  151 _ 2  may be implemented as an operational transconductance amplifier (OTA). However, the present disclosure is not limited thereto. For example, the comparator  151  may have a structure including more amplifiers. Also, the ADC circuit  150  may include a plurality of comparators and a plurality of counters, although one comparator  151  and one counter  152  are illustrated in  FIG.  5    for clearness of description. 
     The first amplifier  151 _ 1  may receive the pixel signal PIX from the pixel array  110  through the column line CL, and may receive the ramp signal RAMP from the ramp signal generator  130  through the voltage buffer  140 . The first amplifier  151 _ 1  may output a first output signal OTA 1 _OUT based on the received signals. For example, in a period where a level of the ramp signal RAMP is higher than a level of the pixel signal PIX, the first amplifier  151 _ 1  may output the first output signal OTA 1 _OUT having a high level. In a period where the level of the ramp signal RAMP is lower than the level of the pixel signal PIX, the first amplifier  151 _ 1  may output the first output signal OTA 1 _OUT having a low level. Also, the comparison operation of the comparator  151  described above may be performed both when the reset signal of the pixel signal PIX and the ramp signal RAMP are compared by the first amplifier  151 _ 1  and when the image signal of the pixel signal PIX and the ramp signal RAMP are compared by the first amplifier  151 _ 1 . 
     As an example operation of the first amplifier  151 _ 1 , the first amplifier  151 _ 1  may be configured to compare a reset signal of the pixel signal and the ramp signal in some operation periods, and may be configured to compare an image signal of the pixel signal and the ramp signal in other operation periods. As one particular example, the first amplifier  151 _ 1  may be configured to: compare a reset signal of a first pixel signal and a first ramp signal in a first operation period; compare an image signal of the first pixel signal and the first ramp signal in a second operation period; compare an image signal of a second pixel signal and a second ramp signal in a third operation period; and compare a reset signal of the second pixel signal and the second ramp signal in a fourth operation period. In another example, the first amplifier  151 _ 1  may be configured to: compare a reset signal of the second pixel signal and the second ramp signal in a first operation period; compare a reset signal of the first pixel signal and the first ramp signal in a second operation period; compare an image signal of the first pixel signal and the first ramp signal in a third operation period; and compare an image signal of the second pixel signal and the second ramp signal in a fourth operation period. 
     The second amplifier  151 _ 2  may amplify the first output signal OTA 1 _OUT and may output a second output signal OTA 2 _OUT as a comparison signal. For example, the second output signal OTA 2 _OUT may be an inverted version of the first output signal OTA 1 _OUT. In other words, the second amplifier  151 _ 2  may output the second output signal OTA 2 _OUT having the low level during the high level of the first output signal OTA 1 _OUT and may output the second output signal OTA 2 _OUT having the high level during the low level of the first output signal OTA 1 _OUT. 
     In the following description, a transition of a voltage level of the first output signal OTA 1 _OUT or the second output signal OTA 2 _OUT from the high level to the low level or from the low level to the high level as the comparator  151  performs the comparison operation may be referred to as a decision of the ADC circuit  150 . In other words, the decision of the ADC circuit  150  may refer to when a voltage level of the first output signal OTA 1 _OUT or the second output signal OTA 2 _OUT changes from the high level to the low level or from the low level to the high level. In an auto-zero period before the comparison operation is performed, the comparator  151  may be initialized in response to an auto-zero signal AZ and may then again perform the comparison operation. 
     The counter  152  may operate under control of the timing controller  160 , may count pulses of the second output signal OTA 2 _OUT, and may output a counting result as the digital signal DS. The counter  152  may receive a counter clock signal CNT_CLK and an inversion signal CONV which is used for inverting an internal bit of the counter  152 . For example, the counter  152  may operate in response to control signals such as the counter clock signal CNT_CLK and the inversion signal CONV. 
     For example, the counter  152  may include an up/down counter, a bit-wise inversion counter, etc. An operation of the bit-wise inversion counter may be similar to an operation of the up/down counter. For example, the bit-wise inversion counter may perform a function of performing up-counting only and a function of converting all internal bits of a counter to obtain the 1&#39;s complement when a specific signal is input thereto. The bit-wise inversion counter may perform a reset count, and may then invert a reset counting result so as to be converted into the 1&#39;s complement, that is, a negative value. 
     Through the above operation of the ADC circuit  150 , a low conversion gain digital signal corresponding to a low conversion gain pixel signal and a high conversion gain digital signal corresponding to a high conversion gain pixel signal may be output. The image data IDAT may be generated based on the low conversion gain digital signal and the high conversion gain digital signal. The image data IDAT thus generated may correspond to a high dynamic range (HDR) image with a high dynamic range. The quality of the HDR image may be determined by a signal-to-noise ratio (SNR) of the image sensor  100 . 
     The SNR may be affected by a magnitude of a signal and a magnitude of a noise; as the signal magnitude becomes greater and the noise magnitude becomes smaller, the SNR may become higher. For example, the signal magnitude may be determined by a level of a power current flowing to the first amplifier  151 _ 1 . For example, a noise that is capable of occurring in the process of generating an image may include a thermal noise, a flicker noise, a dark noise, a shot noise, a quantization error, a settling error, etc. In particular, in the low conversion gain condition, the shot noise due to the light may be the most important factor determining the SNR. Also, in the low conversion gain condition, because the shot noise included in the SNR is great, even though the signal magnitude decreases, the SNR may not decrease significantly to such an extent as to influence the quality of image data. 
     That is, within a range where the quality of image data is uniformly maintained without the great decrease in the SNR, the ADC circuit  150  may be configured such that the current consumption in the comparison operation for the low conversion gain pixel signal is smaller than the current consumption in the comparison operation for the high conversion gain pixel signal. For example, a level of the power current flowing to the first amplifier  151 _ 1  or the second amplifier  151 _ 2  in the comparison operation for the low conversion gain pixel signal may be adjusted to be lower than in the comparison operation for the high conversion gain pixel signal. As such, the current consumption in the dual conversion gain operation may be optimized, and power consumption of the ADC circuit  150  may decrease. The current consumption optimization operation will be described in detail with reference to  FIG.  6   . 
     Also, when the ambient luminance of the object is very light, the shot noise may be sufficiently great; in this case, even though the comparison operation for the low conversion gain pixel signal is not completely performed (i.e., even though the correlated double sampling (CDS) for the low conversion gain pixel signal is not completely performed), the quality of image data may not be significantly affected. In this case, a portion of a counting period may be omitted by increasing or decreasing an offset of the ramp signal RAMP upon comparing the image signal of the low conversion gain pixel signal and the ramp signal RAMP. Accordingly, a period of the comparison operation for the low conversion gain pixel signal may be shortened, and a time (hereinafter referred to as a “required time”) taken to perform the dual conversion gain operation may decrease. The required time optimization operation will be described in detail with reference to  FIG.  7 A ,  FIG.  7 B ,  FIG.  8 A ,  FIG.  8 B , and  FIG.  8 C . 
       FIG.  6    is a circuit diagram illustrating an example of the first amplifier  151 _ 1  of the ADC circuit  150  of  FIG.  5   . A first amplifier  200   a  may include a plurality of transistors including a first transistor TR 11 , a second transistor TR 12 , a third transistor TR 13 , a fourth transistor TR 4 , and a fifth transistor TR 15 , a first current source  210 , a second current source  220 , and a switch SW. For example, the first transistor TR 11 , the second transistor TR 12 , and the fifth transistor TR 15  may be NMOS transistors, and the third transistor TR 13  and the fourth transistor TR 14  may be PMOS transistors. However, the present disclosure is not limited thereto. The first transistor TR 11 , the second transistor TR 12 , the third transistor TR 13 , the fourth transistor TR 14 , and the fifth transistor TR 15  may be implemented with transistors whose types are different from those illustrated in  FIG.  6   . 
     Referring to  FIG.  6   , the ramp signal RAMP may be input to a gate terminal of the first transistor TR 11 , and the pixel signal PIX may be input to a gate terminal of the second transistor TR 12 . Source terminals of the first transistors TR 11  and second transistors TR 12  may be connected in common with the first current source  210  and the switch SW at a common node COMM. For example, the third transistors TR 13  and fourth transistors TR 14  may be connected in the form of a current mirror. A sum of currents flowing to the first transistors TR 11  and second transistors TR 12  may be equal to a power current ISS 1 . 
     A gate terminal and a drain terminal of the third transistor TR 13  and a drain terminal of the first transistor TR 11  may be connected in common with a second output node OUT 12 , and a drain terminal of the fourth transistor TR 14  and a drain terminal of the second transistor TR 12  may be connected in common with a first output node OUT 11 . The fifth transistor TR 15  may be connected between the first output nodes OUT 11  and second output nodes OUT 12 . For example, the fifth transistor TR 15  may limit a voltage level of a signal that is output from the first output node OUT 11 . 
     The first output signal OTA 1 _OUT may be output from the first output node OUT 11 . For example, in a period where a level of the ramp signal RAMP is higher than a level of the pixel signal PIX, the first output signal OTA 1 _OUT may have the high level. In a period where the level of the ramp signal RAMP is lower than the level of the pixel signal PIX, the first output signal OTA 1 _OUT may have the low level. The first output signal OTA 1 _OUT may be provided to the second amplifier  151 _ 2  of  FIG.  5   . 
     The first current source  210  is configured to output and may output a first sub power current ISS 11 . The second current source  220  is configured to output and may output a second sub power current ISS 12  when the switch SW is turned on and may not operate when the switch SW is turned off. That is, when the switch SW is turned on, the power current ISS 1  may be equal to a sum of the first sub power current ISS 11  and the second sub power current ISS 12 . When the switch SW is turned off, the power current ISS 1  may be equal to only the first sub power current ISS 11 . 
     For example, when the first amplifier  200   a  performs the comparison operation for the low conversion gain pixel signal, the switch SW may be turned off such that only the first current source  210  operates. Accordingly, the power current ISS 1  may be equal to the first sub power current ISS 11 . In contrast, when the first amplifier  200   a  performs the comparison operation for the high conversion gain pixel signal, the switch SW may be turned on such that both the first current source  210  and the second current source  220  operate. Accordingly, the power current ISS 1  may be equal to a sum of the first sub power current ISS 11  and the second sub power current ISS 12 . 
     For example, magnitudes of the first sub power current ISS 11  and the second sub power current ISS 12  may be differently determined depending on a magnitude of the shot noise. In addition, a ratio of the first sub power current ISS 11  and the second sub power current ISS 12  may be optimized in the process of designing the first amplifier  200   a.  Also, the switch SW may be turned on or turned off in response to a signal that is deactivated when the comparison operation for the low conversion gain pixel signal is performed and is activated when the comparison operation for the high conversion gain pixel signal is performed. As such, the current consumption in the dual conversion gain operation may be optimized through the operation of the first amplifier  200   a,  and the current consumption in the comparison operation for the low conversion gain pixel signal may decrease. This may mean that the power consumption of the ADC circuit  150  decreases. 
     An embodiment in which the power current of the first amplifier  151 _ 1  of  FIG.  5    is adjusted while the comparison operation for the low conversion gain pixel signal is performed is described with reference to  FIG.  6   , but the present disclosure is not limited thereto. For example, the power current of the first amplifier  151 _ 1  may be adjusted in a method that is different from that described with reference to  FIG.  6   . Also, the power current of the second amplifier  151 _ 2  of  FIG.  5    may be differently adjusted in the comparison operation for the low conversion gain pixel signal and the comparison operation for the high conversion gain pixel signal. 
       FIG.  7 A  is a timing diagram illustrating a process in which the ADC circuit  150  of the analog-to-digital converting circuit of  FIG.  5    processes the pixel signal PIX depending on a reset-sig-sig-reset (RSSR) method.  FIG.  7 B  is a timing diagram illustrating a process in which the ADC circuit  150  of the analog-to-digital converting circuit of  FIG.  5    processes the pixel signal PIX depending on a reset-reset-sig-sig (RRSS) method. Below,  FIG.  7 A  and  FIG.  7 B  will be described together with  FIG.  5   . 
     A  1 H time period is illustrated in  FIG.  6 A  and  FIG.  6 B . The  1 H time period may refer to a time that should be essentially secured to drive a plurality of pixels of the pixel array  110  in units of row. For example, the  1 H time period may include a high conversion gain reset signal period HRST, a high conversion gain image signal period HSIG, a low conversion gain reset signal period LRST, and a low conversion gain image signal period LSIG. 
     Referring to  FIG.  7 A , the high conversion gain reset signal period HRST, the high conversion gain image signal period HSIG, the low conversion gain image signal period LSIG, and the low conversion gain reset signal period LRST may progress sequentially (Reset-Sig-Sig-Reset: RSSR). 
     A high conversion gain reset signal VHRST, a high conversion gain image signal VHSIG, a low conversion gain image signal VLSIG, and a low conversion gain reset signal VLRST may be respectively output in the plurality of periods HRST, HSIG, LSIG, and LRST as components of the pixel signal PIX, so as to be sequentially converted into digital signals. 
     First, the reset signal VRST of a logic high level is applied to the gate of the reset transistor RST, and the reset signal VRST of a logic low level is then applied to the gate of the reset transistor RST. Next, the adjustment between the voltage level of the ramp signal RAMP and the voltage level of the pixel signal PIX may be made in response to the auto-zero signal AZ. Then, the dual conversion signal VDC of the logic low level may be applied to the gate of the dual conversion transistor DC. Accordingly, the high conversion gain reset signal VHRST may be output in the high conversion gain reset signal period HRST. Afterwards, the transfer signal VT of the logic high level may be applied to the gate of the transfer transistor Tx. Accordingly, the high conversion gain image signal VHSIG may be output in the high conversion gain image signal period HSIG. 
     Next, the adjustment between the voltage level of the ramp signal RAMP and the voltage level of the pixel signal PIX may be again made in response to the auto-zero signal AZ. As the reset signal VRST of the logic low level is applied to the gate of the reset transistor RST, the dual conversion signal VDC of the logic high level is applied to the gate of the dual conversion transistor DC, and the transfer signal VT of the logic high level is applied to the gate of the transfer transistor Tx, the low conversion gain image signal VLSIG may be output in the low conversion gain image signal period LSIG. Afterwards, the reset signal VRST of the logic high level may be applied to the gate of the reset transistor RST. Accordingly, the low conversion gain reset signal VLRST may be output in the low conversion gain reset signal period LRST. 
     Referring to  FIG.  7 B , the low conversion gain reset signal period LRST, the high conversion gain reset signal period HRST, the high conversion gain image signal period HSIG, and the low conversion gain image signal period LSIG may progress sequentially (Reset-Reset-Sig-Sig: RRSS). 
     First, the reset signal VRST of the logic high level is applied to the gate of the reset transistor RST, and the reset signal VRST of the logic low level is then applied to the gate of the reset transistor RST. Next, the adjustment between the voltage level of the ramp signal RAMP and the voltage level of the pixel signal PIX may be made in response to the auto-zero signal AZ. Then, the dual conversion signal VDC of the logic high level may be applied to the gate of the dual conversion transistor DC, and thus, the low conversion gain reset signal VLRST may be output in the low conversion gain reset signal period LRST. After the adjustment between the voltage level of the ramp signal RAMP and the voltage level of the pixel signal PIX is again made in response to the auto-zero signal AZ, the dual conversion signal VDC of the logic low level may be applied to the gate of the dual conversion transistor DC. Accordingly, the high conversion gain reset signal VHRST may be output in the high conversion gain reset signal period HRST. 
     Afterwards, the transfer signal VT of the logic high level may be applied to the gate of the transfer transistor Tx. Accordingly, the high conversion gain image signal VHSIG may be output in the high conversion gain image signal period HSIG. As the dual conversion signal VDC of the logic high level is applied to the gate of the dual conversion transistor DC and the transfer signal VT of the logic high level is applied to the gate of the transfer transistor Tx, the low conversion gain image signal VLSIG may be output in the low conversion gain image signal period LSIG. 
       FIG.  8 A  illustrates an example in which the offset of the ramp signal RAMP is adjusted in the timing diagram of  FIG.  7 A , and  FIG.  8 B  illustrates an example in which the offset of the ramp signal RAMP is adjusted in the timing diagram of  FIG.  7 B . As described above, when the shot noise is sufficiently large, the quality of the image data may not be significantly affected even if the comparison operation on the low conversion gain pixel signal is not completely performed. In this case, during the LSIG period, the ramp signal generator (e.g.,  130  of  FIG.  2   ) may omit a part of counting by either increasing the offset of the ramp signal RAMP by “a” as in  FIG.  8 A  or decreasing by “a” as in  FIG.  8 B . For example, the ramp signal generator  130  may determine the amount “a” of the offset to increase or decrease based on the ratio of the low conversion gain and the high conversion gain. 
     Referring to  FIG.  8 A , as the offset of the ramp signal RAMP increases by “a” in the LSIG section compared to  FIG.  7 A , some of the comparison operation and counting between the low conversion gain image signal VLSIG and the ramp signal RAMP may be omitted. Accordingly, the length of the LSIG interval of  FIG.  9 A  may be shorter than the length of the LSIG interval of  FIG.  7 A , and the length of the  1 H time interval of  FIG.  8 A  may also be shorter than the length of the  1 H time interval of  FIG.  7 A . 
     Referring to  FIG.  8 B , as the offset of the ramp signal RAMP is reduced by “a” in the LSIG section compared to  FIG.  7 B , some of the comparison operation and counting between the low conversion gain image signal VLSIG and the ramp signal RAMP may be omitted. Similarly, the length of the LSIG interval of  FIG.  8 B  may be shorter than the length of the LSIG interval of  FIG.  7 B , and the length of the  1 H time interval of  FIG.  8 B  may also be shorter than the length of the  1 H time interval of  FIG.  7 B . 
     Meanwhile,  FIG.  8 C  illustrates another example in which the offset of the ramp signal RAMP is adjusted in the timing diagram of  FIG.  7 B . Referring to  FIG.  8 C , the level of the ramp signal RAMP after the HSIG interval ends may be adjusted to be lower than the level of the ramp signal RAMP after the LRST interval or the HRST interval ends (for example, to be lowered by a). Accordingly, as shown in  FIG.  8 B , the same effect as that the offset of the ramp signal RAMP is decreased by a in the LSIG interval may be obtained, and some of the comparison operation and counting between the low conversion gain image signal VLSIG and the ramp signal RAMP may be omitted. Accordingly, the length of the LSIG interval of  FIG.  8 C  may be shorter than the interval of the LSIG period of  FIG.  7 B , and the length of the  1 H time interval of  FIG.  8 C  may also be shorter than the length of the  1 H time interval of  FIG.  7 B . Through the above-described operations, a time required for the dual conversion gain operation may be reduced. 
       FIG.  9    is a flowchart illustrating an operation method of an analog-to-digital converting (ADC) circuit for optimizing a dual conversion gain operation according to an embodiment of the present disclosure. Below,  FIG.  9    will be described together with  FIG.  5   . 
     In operation S 110 , the first amplifier  151 _ 1  may generate an output signal by comparing a ramp signal and a high conversion gain pixel signal corresponding to a high conversion gain condition based on a first power current. In operation S 120 , the first amplifier  151 _ 1  may generate the output signal by comparing the ramp signal and a low conversion gain pixel signal corresponding to a low conversion gain condition based on a second power current. 
     In operation S 130 , the first amplifier  151 _ 1  may adjust a power current. For example, the second power current of the first amplifier  151 _ 1  corresponding to the low conversion gain condition may be adjusted to be smaller than the first power current of the first amplifier  151 _ 1  corresponding to the high conversion gain condition. To adjust the power current depending on the conversion gain, the first amplifier  151 _ 1  may be implemented as illustrated in  FIG.  6   . 
     According to an embodiment of the present disclosure, the power consumption of an analog-to-digital converting circuit may be optimized by differently setting current consumption in a low conversion gain operation and current consumption in a high conversion gain operation. 
     Also, according to an embodiment of the present disclosure, a time taken to perform a dual conversion gain operation may be optimized by differently setting a ramp signal in the low conversion gain operation and a ramp signal in the high conversion gain operation. 
     While the present disclosure has been described with reference to embodiments thereof, it will be apparent to those of ordinary skill in the art that various changes and modifications may be made thereto without departing from the spirit and scope of the present disclosure as set forth in the following claims.