Patent Publication Number: US-11652113-B2

Title: Image sensor

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This is a continuation application based on pending application Ser. No. 16/451,412, filed Jun. 25, 2019, the entire contents of which is hereby incorporated by reference. 
     Korean Patent Application No. 10-2018-0135331, filed on Nov. 6, 2018, in the Korean Intellectual Property Office, and entitled: “Image Sensors,” is incorporated by reference herein in its entirety. 
    
    
     BACKGROUND 
     1. Field 
     Embodiments relate to an image sensor. 
     2. Description of the Related Art 
     An image sensor is a device that converts an optical image signal into an electric signal. The image sensor may include pixel region including a plurality of photodiode regions in which incident light is received and converted into the electrical signal, and a pixel isolation region for electrically separating pixels from each other. 
     SUMMARY 
     The embodiments may be realized by providing an image sensor including a semiconductor substrate having a first surface and a second surface; and a pixel isolation film extending from the first surface of the semiconductor substrate into the semiconductor substrate and defining active pixels in the semiconductor substrate, wherein the pixel isolation film includes a buried conductive layer including polysilicon containing a fining element at a first concentration; and an insulating liner between the buried conductive layer and the semiconductor substrate, and wherein the fining element includes oxygen, carbon, or fluorine. 
     The embodiments may be realized by providing an image sensor including a semiconductor substrate; and a pixel isolation film in a pixel trench passing through the semiconductor substrate and defining active pixels in the semiconductor substrate, wherein the pixel isolation film includes an insulating liner on a sidewall of the pixel trench; and a buried conductive layer filled in an inside of the pixel trench on the insulating liner, the buried conductive layer including polysilicon containing a fining element at a first concentration, and wherein the fining element includes oxygen, carbon, or fluorine. 
     The embodiments may be realized by providing an image sensor including a semiconductor substrate including a plurality of active pixels; and a pixel isolation film between active pixels of the plurality of active pixels and in a pixel trench passing through the semiconductor substrate, wherein the pixel isolation film includes: an insulating liner on a sidewall of the pixel trench; and a buried conductive layer filled in an inside of the pixel trench on the insulating liner, the buried conductive layer including polysilicon containing a fining element at a first concentration, and wherein the fining element includes oxygen and the first concentration is about 5 at % to about 40 at %. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Features will be apparent to those of skill in the art by describing in detail exemplary embodiments with reference to the attached drawings in which: 
         FIG.  1    illustrates a layout view of an image sensor according to example embodiments; 
         FIG.  2    illustrates a cross-sectional view taken along line II-II′ of  FIG.  1   ; 
         FIG.  3    illustrates an equivalent circuit diagram of an active pixel of an image sensor according to example embodiments; 
         FIG.  4    illustrates a cross-sectional view of an image sensor according to example embodiments; 
         FIG.  5    illustrates a cross-sectional view of an image sensor according to example embodiments; 
         FIG.  6    illustrates a cross-sectional view of an image sensor according to example embodiments; 
         FIGS.  7 A- 7 L  illustrate cross-sectional views of stages in a method of manufacturing an image sensor according to example embodiments 
         FIG.  8    illustrates a flowchart of a method of manufacturing an image sensor according to example embodiments; 
         FIGS.  9 A- 9 C  illustrate cross-sectional views of stages in a method of manufacturing an image sensor according to example embodiments; 
         FIG.  10    illustrates a flow chart of a method of manufacturing an image sensor in accordance with example embodiments; 
         FIG.  11    illustrates a flowchart of a method of manufacturing an image sensor according to example embodiments; 
         FIGS.  12 A- 12 D  illustrate cross-sectional views of stages in a method of manufacturing an image sensor according to example embodiments; 
         FIG.  13    illustrates a flow chart of a method of manufacturing an image sensor in accordance with example embodiments; 
         FIG.  14    illustrates a flowchart of a method of manufacturing an image sensor according to example embodiments; and 
         FIG.  15    illustrates an X-ray diffraction analysis graph of a buried conductive layer included in an image sensor according to an Example and Comparative Examples. 
     
    
    
     DETAILED DESCRIPTION 
       FIG.  1    illustrates a layout diagram of an image sensor  100  according to example embodiments.  FIG.  2    illustrates a cross-sectional view taken along line II-II′ of  FIG.  1   . 
     Referring to  FIGS.  1  and  2   , the image sensor  100  may include an active pixel region APR, a peripheral circuit region PCR, and a pad region PDR in or on a semiconductor substrate  110 . 
     The active pixel region APR may include a plurality of active pixels PX and each of a plurality of photoelectric conversion regions  120  may be arranged in each of the plurality of active pixels PX. In the active pixel region APR, a plurality of active pixels PX may be arranged in a matrix shape in the form of rows and columns along first direction (for example, X direction in  FIG.  1   ) parallel to an upper surface of the semiconductor substrate  110  and second direction (for example, Y direction in  FIG.  1   ) parallel to the upper surface of the semiconductor substrate  110 . 
     In an implementation, as illustrated, the peripheral circuit region PCR may be on one side of the active pixel region APR in a plan view. In an implementation, the peripheral circuit region PCR may surround an entirety of the active pixel region APR. In an implementation, unlike that shown in  FIG.  1   , the peripheral circuit region PCR may be on an additional substrate, and then the additional substrate may be attached to the semiconductor substrate  110 . 
     The peripheral circuit region PCR may be a region where various kinds of circuits for controlling a plurality of active pixels PX in the active pixel region APR are formed. For example, the peripheral circuit region PCR may include a plurality of transistors, and the plurality of transistors may be driven to provide a constant signal in each photoelectric conversion region  120  of the active pixel region APR, or to control an output signal from each of the photoelectric conversion region  120 . In an implementation, the transistor may configure various logic circuits, such as a timing generator, a row decoder, a row driver, a correlated double sampler CDS, an analog to digital converter ADC, a latch, a column decoder, and the like. 
     The pad region PDR may surround the active pixel region APR and the peripheral circuit region PCR. A conductive pad PAD may be on the peripheral region of the semiconductor substrate  110  and may be electrically connected to circuits in the plurality of active pixels PX and the peripheral circuit region PCR. The conductive pad PAD may function as a connection terminal for externally supplying power and signals to a circuit included in the plurality of active pixels PX and the peripheral circuit region PCR. 
     The semiconductor substrate  110  may include a first surface  110 F 1  and a second surface  110 F 2  opposing to each other. Herein, for convenience, the surface of the semiconductor substrate  110  on which a microlens  168  is arranged is referred to as the second surface  110 F 2 , and the surface opposite to the second surface  110 F 2  is referred to as the first surface  110 F 1 . 
     In an implementation, the semiconductor substrate  110  may include a P-type semiconductor substrate. For example, the semiconductor substrate  110  may be a P-type silicon substrate. In an implementation, the semiconductor substrate  110  may include a P-type bulk substrate and a P-type or a N-type epitaxial layer grown thereon. In an implementation ts, the semiconductor substrate  110  may include an N-type bulk substrate and a P-type or an N-type epitaxial layer grown thereon. In an implementation, the semiconductor substrate  110  may be formed of an organic plastic substrate. 
     A plurality of active pixels PX may be arranged in a matrix form in the semiconductor substrate  110  in the active pixel region APR. One of the photoelectric conversion regions  120  may be arranged in each of the plurality of active pixels PX. Each of the plurality of photoelectric conversion regions  120  may include a photodiode region  122  and a well region  124 . 
     A pixel isolation film  130  may be in the semiconductor substrate  110  in the active pixel region APR, and the plurality of active pixels PX may be defined by the pixel isolation film  130 . The pixel isolation film  130  may be between one of the plurality of photoelectric conversion regions  120  and another one of the photoelectric conversion regions  120  adjacent thereto. The one of the photoelectric conversion regions  120  and the other one of the photoelectric conversion regions  120  adjacent thereto may be physically and electrically separated by the pixel isolation film  130 . The pixel isolation film  130  may be between each of the plurality of photoelectric conversion regions  120  arranged in a matrix form and may have a grid or mesh shape in a plan view. 
     The pixel isolation film  130  may be in a pixel trench  130 T passing through the semiconductor substrate  110  from the first surface  110 F 1  to the second surface  110 F 2  of the semiconductor substrate  110 . The pixel isolation film  130  may include an insulating liner  132  conformally formed on a sidewall of the pixel trench  130 T and a buried conductive layer  134  filled in an inside of the pixel trench  130 T on the insulating liner  132 . 
     In an implementation, the insulating liner  132  may include a metal oxide, e.g., hafnium oxide, aluminum oxide, tantalum oxide, or the like. In an implementation, the insulating liner  132  may serve as a negative fixed charge layer. In an implementation, the insulating liner  132  may include an insulating material, e.g., silicon oxide, silicon nitride, silicon oxynitride, or the like. 
     The buried conductive layer  134  may include polysilicon that contains a fining element at a first concentration. The fining element may include, e.g., oxygen, carbon, or fluorine. As used herein, the term “or” is not an exclusive term, e.g., the fining element may include one or more of the enumerated elements. In an implementation, the buried conductive layer  134  may include polysilicon containing oxygen at a concentration of about 5 at % (atomic percent) to about 40 at %. In an implementation, the buried conductive layer  134  may include polysilicon containing oxygen at a concentration of about 20 at % to about 30 at %. In an implementation, the buried conductive layer  134  may include polysilicon containing carbon at a concentration of about 1 at % to about 20 at %. In an implementation, the buried conductive layer  134  may include polysilicon containing fluorine at a concentration of about 1 at % to about 20 at %. In an implementation, the buried conductive layer  134  may include a plurality of grains made of silicon and having a silicon crystal structure, and the fining element may be uniformly dispersed within the grains of silicon. For example, the buried conductive layer  134  may have a diffraction peak at about 28.44° represented by a silicon (111) crystal plane in an X-ray diffraction analysis. 
     The buried conductive layer  134  may include a polysilicon containing the fining element at the first concentration, and the buried conductive layer  134  may have a relatively small grain size. In an implementation, the buried conductive layer  134  may have an average grain size of about 30 nanometers (nm) or less. In an implementation, in the buried conductive layer  134 , a full width at half maximum of an X-ray diffraction peak (the peak being observed at a scattering angle of about 28.44°) by the silicon (111) crystal plane observed in the X-ray diffraction analysis may be about 0.4° to about 1.1° (See  FIG.  15   ). In an implementation, the average grain size of the buried conductive layer  134  calculated from the X-ray diffraction peak may be about 7.5 nm to about 20.5 nm. 
     In an implementation, the pixel trench  130 T may have a first width w 11  at the same level as the first surface  110 F 1  of the semiconductor substrate  110  and a second width w 12  (that is smaller than the first width w 11 ) at the same level as the second surface  110 F 2  of the semiconductor substrate  110 . For example, the first width w 11  of the pixel trench  130 T measured (e.g., in the first or X direction) at the first surface  110 F 1  of the semiconductor substrate  110  may be greater than the second width w 12  of the pixel trench  130 T measured at the second surface  110 F 2  of the semiconductor substrate  110 . In an implementation, the pixel trench  130 T may have a first height h 11  in a direction (e.g., Z direction) perpendicular to the first surface  110 F 1  of the semiconductor substrate  110 , and a ratio of the first height h 11  to the first width w 11  may be about 20 to about 100. 
     In an implementation, voids or seams may not be formed within the buried conductive layer  134 . The pixel trench  130 T may have a relatively high aspect ratio (e.g., an aspect ratio of about 20 to 100), and seams could otherwise be formed in the conductive layer  134  in the process of forming the buried conductive layer  134  using polysilicon inside the pixel trench  130 T, and undesired voids could be formed in the buried conductive layer  134  due to grain growth or grain coalescence in the buried conductive layer  134  in a subsequent heat treatment processes. However, according to the example embodiments, the buried conductive layer  134  may include the polysilicon containing the fining element (e.g., oxygen, carbon, or fluorine), and the buried conductive layer  134  may be formed to have a relatively small grain size in the process of forming the buried conductive layer  134  filling an interior of the pixel trench  130 T. In addition, in a heat treatment process after the formation of the buried conductive layer  134 , the fining element may be able to help restrain grain growth or grain coalescence, which could otherwise occur due to the migration of silicon atoms, thereby voids or seams not being formed in the buried conductive layer  134 . The grain size and microstructure of the buried conductive layer  134  will be described again in detail below with reference to  FIG.  15   . 
     The buried conductive layer  134  may not fill a portion of an interior of the pixel trench  130 T and a bottom surface of the buried conductive layer  134  may be at a level higher than the first surface  110 F 1  of the semiconductor substrate  110  (e.g., the bottom surface of the buried conductive layer  134  may be inwardly spaced apart from the first surface  110 F 1  of the semiconductor substrate  110  by a predetermined distance along the vertical direction (Z direction)). A buried insulating layer  140  may fill a remaining portion of the pixel trench  130 T on the bottom surface of the buried conductive layer  134  and the insulating liner  132  may be between the buried insulating layer  140  and an inner wall of the pixel trench  130 T. In an implementation, an upper, lower, or outer surface of the buried insulating layer  140  may be at the same level as (e.g., coplanar with) the first surface  110 F 1  of the semiconductor substrate  110 . In an implementation, the buried insulating layer  140  may be omitted and the buried conductive layer  134  may be filled in an inside of the pixel trench  130 T through the entire height h 11  of the pixel trench  130 T, such that the bottom or lower surface of the buried conductive layer  134  may be at the same level as (e.g., coplanar with) the first surface  110 F 1  of the semiconductor substrate  110 . 
     In an implementation, as shown in  FIG.  2   , an isolation film STI (which defines an active region) and a floating diffusion region FD may be on the first surface  110 F 1  of the semiconductor substrate  110 . 
     Gate electrodes TG, RG, SG (see  FIG.  3   ) constituting a part of a plurality of transistors may be on the first surface  110 F 1  of the semiconductor substrate  110 . In an implementation, the plurality of transistors may include a transmission transistor TX configured to transmit the charge generated in the photoelectric conversion region  120  to the floating diffusion region FD, a reset transistor RX configured to periodically reset the charge stored in the floating diffusion region FD, a drive transistor DX configured to function as a source follower buffer amplifier and to buffer a signal according to the charge charged in the floating diffusion region, and a selection transistor SX for switching and addressing in relation to selecting the active pixel region APR. 
     In an implementation, as illustrated in  FIG.  2   , the transmission gate TG constituting the transmission transistor TX may be a recess gate type extending from the first surface  110 F 1  of the semiconductor substrate  110  into the semiconductor substrate  110 . In an implementation, a transmission gate insulating layer TGI may be between the semiconductor substrate  110  and the transmission gate TG. For example, as the transmission gate TG is formed in the recess gate type, a portion of the transmission gate insulating layer TGI may extend into the interior of the semiconductor substrate  110 . 
     A first interconnection structure  152  may be on the first surface  110 F 1  of the semiconductor substrate  110 . The first interconnection structure  152  may be electrically connected to the gate electrodes or the active region. The first interconnection structure  152  may be formed as a stacked structure of a plurality of layers. The first interconnection structure  152  may include at least one of impurity-doped or undoped polysilicon, metal, metal silicide, metal nitride, or metal-containing film. For example, the first interconnection structure  152  may include tungsten, aluminum, copper, tungsten silicide, titanium silicide, tungsten nitride, titanium nitride, doped polysilicon, and the like. 
     A first interlayer insulating film  154  may cover the first interconnection structure  152  on the first surface  110 F 1  of the semiconductor substrate  110 . The first interlayer insulating film  154  may include an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, or the like. 
     A rear insulating layer  160  may be arranged on the second surface  110 F 2  of the semiconductor substrate  110 . The rear insulating layer  160  may be arranged on substantially the entire area of the second surface  110 F 2  of the semiconductor substrate  110 , and the rear insulating layer  160  may contact an upper surface of the pixel isolation film  130  at the same level as the second surface  110 F 2  of the semiconductor substrate  110 . In an implementation, the rear insulating layer  160  may include a metal oxide such as hafnium oxide, aluminum oxide, tantalum oxide, or the like. In an implementation, the rear insulating layer  160  may include an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, or a low dielectric constant material, or the like. 
     A guide pattern  162  may be on the rear insulating layer  160 . In a plan view, the guide pattern  162  may have a grid shape or a mesh shape. The guide pattern  162  may help prevent incident light with a tilt angle with respect to one photoelectric conversion region  120 , from entering the photoelectric conversion region  120 . The guide pattern  162  may include at least one metallic material, e.g., tungsten, aluminum, titanium, ruthenium, cobalt, nickel, copper, gold, silver or platinum. 
     A passivation layer  164  may cover the rear insulating layer  160  and the guide pattern  162  on the second surface  110 F 2  of the semiconductor substrate  110 . A color filter  166  and a microlens  168  may be on the passivation layer  164 . 
     In an implementation, a supporting substrate  170  may be on the first surface  110 F 1  of the semiconductor substrate  110 . An adhesive member may be further arranged between the supporting substrate  170  and the first interlayer insulating film  154 . 
     In the process of forming the buried conductive layer  134  using polysilicon inside the pixel trench  130 T having a relatively high aspect ratio, it is possible that a seam could be formed in the buried conductive layer  134 , and in a subsequent heat treatment process grain growth or grain coalescence could occur to form an undesired void in the buried conductive layer  134 . If such a void were to be formed, performance of the image sensor  100  may be lowered, due to an occurrence of a dark current or an increase in noise level, or the like. 
     On the other hand, in the image sensor  100  according to an embodiment, the buried conductive layer  134  may include polysilicon containing the fining element (e.g., oxygen, carbon, or fluorine), and the buried conductive layer  134  may be formed to have a relatively small grain size. In addition, the fining element may help prevent grain growth or grain coalescence in the heat treatment process after the formation of the buried conductive layer  134 , and the formation of undesired voids may be prevented. For example, voids or seams may not be formed in the buried conductive layer  134 , and the image sensor  100  may be prevented from generating a dark current or increasing of noise level to have improved performance. 
       FIG.  15    illustrates an X-ray diffraction analysis graph of the buried conductive layer included in the image sensors according to an Example and Comparative Examples. 
     The following Example and Comparative Examples are provided in order to highlight characteristics of one or more embodiments, but it will be understood that the Example and Comparative Examples are not to be construed as limiting the scope of the embodiments, nor are the Comparative Examples to be construed as being outside the scope of the embodiments. Further, it will be understood that the embodiments are not limited to the particular details described in the Example and Comparative Examples. 
     Referring to  FIG.  15   , a buried conductive layer EX 11  according to an Example was formed using polysilicon containing oxygen as the fining element at a first concentration, as described with reference to  FIGS.  1  and  2   , and then a subsequent heat treatment was performed. Buried conductive layers CO 11  and CO 12  according to Comparative Examples 1 and 2, respectively, were formed using polysilicon without the fining element, and then a subsequent heat treatment was performed. 
     Referring to  FIG.  15    and the following Table 1, in the buried conductive layer EX 11  according to the Example and the buried conductive layers CO 11  and CO 12  according to the Comparative Examples, diffraction peaks by silicon (111) crystal planes are observed at a scattering angle of about 28.44°, and the intensity of the diffraction peak of the buried conductive layer EX 11  according to the Example was lower than the intensity of the diffraction peaks of the buried conductive layers CO 11  and CO 12  according to the Comparative Examples. 
     In addition, a full width at half maximum (FEX 11 ) by the silicon (111) crystal plane of the buried conductive layer EX 11  according to the Example was higher than a full width at half maximum FCO 11  of the buried conductive layer CO 11  according to Comparative Example 1 and a full width at half maximum FCO 12  of the buried conductive layer CO 12  according to Comparative Example 2. From the calculation based on the full widths at half maximum of such X-ray diffraction peaks, the buried conductive layer EX 11  according to the Example may have an average grain size of about 16.8 nm, while the buried conductive layer CO 11  according to the Comparative Example 1 may have an average grain size of about 43.5 nm, and the buried conductive layer CO 12  according to the Comparative Example 2 may have an average grain size of about 45.8 nm. 
     
       
         
           
               
               
               
               
             
               
                   
                 TABLE 1 
               
               
                   
                   
               
               
                   
                   
                 Intensity of (111) plane 
                 Full width at half 
               
               
                   
                   
                 diffraction peak 
                 maximum 
               
               
                   
                   
               
             
            
               
                   
                 Comparative 
                 481 
                 0.19 
               
               
                   
                 Example 1 (CO11) 
                   
                   
               
               
                   
                 Comparative 
                 611 
                 0.18 
               
               
                   
                 Example 2 (CO12) 
                   
                   
               
               
                   
                 Example (EX11) 
                  79 
                 0.49 
               
               
                   
                   
               
            
           
         
       
     
     Voids or seams were observed inside the buried conductive layers CO 11  and CO 12  according to the Comparative Examples, while voids or seams were not observed inside the buried conductive layer EX 11  according to the Example. 
     According to an embodiment, the buried conductive layer  134  (see  FIG.  2   ) may have a relatively small grain size by including the fining element (including at least one of oxygen, carbon, and fluorine), and then the formation of undesired voids in a subsequent heat treatment process may be prevented by the fining element. 
       FIG.  3    illustrates an equivalent circuit diagram of the active pixel PX of the image sensor  100  of  FIGS.  1  and  2    according to example embodiments. 
     Referring to  FIG.  3   , the plurality of active pixels PX may be arranged in a matrix form. Each of the plurality of active pixels PX may include a transmission transistor TX and logic transistors RX, SX, DX. Herein, the logic transistors may include a reset transistor RX, a selection transistor SX, and a drive transistor DX (or a source follower transistor). The reset transistor RX may include a reset gate RG and the selection transistor SX may include a selection gate SG and the transfer transistor TX may include a transmission gate TG. 
     Each of the plurality of active pixels PX may further include a photoelectric conversion device PD and a floating diffusion region FD. The photoelectric conversion device PD may correspond to the photoelectric conversion region  120  described with reference to  FIGS.  1  and  2   . The photoelectric conversion device PD may generate and accumulate photo charges in proportion to the amount of incident light from an outside, and a photodiode, a photo transistor, a photo gate, a pinned photodiode PPD and combinations thereof may be used as the photoelectric conversion device PD. 
     The transmission gate TG may transfer the charges generated in the photoelectric conversion device PD to the floating diffusion region FD. The floating diffusion region FD may receive the charges generated in the photoelectric conversion device PD and accumulate the charges. The drive transistor DX may be controlled according to the amount of the photo charges accumulated in the floating diffusion region FD. 
     The reset transistor RX may periodically reset the charges accumulated in the floating diffusion region FD. A drain electrode of the reset transistor RX is connected to the floating diffusion region FD and a source electrode thereof is connected to a power source voltage VDD. When the reset transistor RX is turned on, the power source voltage VDD connected to the source electrode of the reset transistor RX is transferred to the floating diffusion region FD. When the reset transistor RX is turned on, the charges accumulated in the floating diffusion region FD are discharged to reset the floating diffusion region FD. 
     The drive transistor DX is connected to a current source (not shown) located outside the plurality of active pixels PX and then functions as a source follower buffer amplifier, and it amplifies potential change in the floating diffusion region FD and outputs it to the output line VOUT. 
     The selection transistor SX may select the plurality of active pixels PX row by row and when the selection transistor SX is turned on, the power supply voltage VDD may be transferred to a source electrode of the drive transistor DX. 
       FIG.  4    illustrates a cross-sectional view of an image sensor  100 A according to example embodiments.  FIG.  4    is a cross-sectional view of a portion corresponding to the portion II-II′ of  FIG.  1   . In  FIG.  4   , the same reference numerals as in  FIGS.  1  to  3    denote the same elements. 
     Referring to  FIG.  4   , the pixel isolation layer  130 A may include an insulating liner  132  and a buried conductive layer  134 A. The buried conductive layer  134 A may contain polysilicon containing the fining element at the first concentration and a P-type dopant at a second concentration or an N-type dopant at the second concentration. For example, the fining element may include oxygen, carbon, or fluorine. In an implementation, the P-type dopant may include, e.g., boron, aluminum, or indium. In an implementation, the N-type dopant may include, e.g., phosphorus, arsenic, or antimony. The fining element may function as an additive, with which the buried conductive layer  134 A may be formed to have a fine grain size, and the P type dopant or the N type dopant may help increase the conductivity of the buried conductive layer  134 A. 
     In an implementation, the fining elements may be uniformly dispersed in the buried conductive layer  134 A, and the P-type dopant or the N-type dopant may also be uniformly dispersed in the buried conductive layer  134 A. 
     In the manufacturing process of the image sensor  100 A according to an embodiment, a first conductive layer  134 A 1  (see  FIG.  9 A ) may be formed by using polysilicon containing the P-type dopant or the N-type dopant on an inner wall of the pixel trench  130 T, a second conductive layer  134 B 1  (see  FIG.  9 B ) may be formed on the first conductive layer  134 A 1  by using the polysilicon containing the fining element, and the buried conductive layer  134 A may be formed by performing a heat treatment process and then diffusing the fining element in the first conductive layer  134 A 1  and the P-type or the N-type dopant in the second conductive layer  134 B 1 . 
       FIG.  5    illustrates a cross-sectional view of an image sensor  100 B according to example embodiments.  FIG.  5    is a cross-sectional view taken along line II-II′ of  FIG.  1   . In  FIG.  5   , the same reference numerals as in  FIGS.  1  to  4    denote the same elements. 
     Referring to  FIG.  5   , a pixel isolation film  130 B may include an insulating liner  132 , a buried conductive layer  134 B, and an interface layer  136 B. The buried conductive layer  134 B may include polysilicon containing the fining element at a first concentration, and the fining element may include at least one of oxygen, carbon, and fluorine. 
     The interface layer  136 B may be between the insulating liner  132  and the buried conductive layer  134 B. The interface layer  136 B may include polysilicon containing the P-type dopant or the N-type dopant. 
     In an implementation, the interface layer  136 B may be between the rear insulating layer  160  and the buried conductive layer  134 B at the same level as the second surface  110 F 2  of the semiconductor substrate  110 , so that the buried conductive layer  134 B may not contact the rear insulating layer  160 . In an implementation, the interface layer  136 B may surround the sidewall of the buried conductive layer  134 B on the sidewall of the pixel trench  130 T, so that both the buried conductive layer  134 B and the interface layer  136 B may be in contact with the rear insulating layer  160  at the same level as the second surface  110 F 2  of the semiconductor substrate  110 . 
     In the manufacturing process of the image sensor  100 B according to the example embodiments, the first conductive layer  134 A 1  (see  FIG.  9 A ) may formed on the inner wall of the pixel trench  130 T by using polysilicon containing the P-type dopant or the N-type dopant, and then a second conductive layer  134 B 1  (see  FIG.  9 B ) may be formed on the first conductive layer  134 A 1  by using polysilicon containing the fining element. Herein, a part of the first conductive layer  134 A 1  may correspond to the interface layer  136 B and a part of the second conductive layer  134 B 1  may correspond to the buried conductive layer  134 B, respectively. 
       FIG.  6    illustrates a cross-sectional view of an image sensor  100 C according to example embodiments.  FIG.  6    is a cross-sectional view of a portion corresponding to the portion II-II′ of  FIG.  1   . In  FIG.  6   , the same reference numerals as in  FIGS.  1  to  5    denote the same elements. 
     Referring to  FIG.  6   , a pixel isolation film  130 C may include an insulating liner  132 , a buried conductive layer  134 C, and an interface layer  136 C. The buried conductive layer  134 C may include polysilicon containing the fining element at a first concentration, and the fining element may include at least one of oxygen, carbon, and fluorine. 
     The interface layer  136 C may be between the insulating liner  132  and the buried conductive layer  134 C, and may have a tapered shape in a direction (e.g., Z direction) toward a first surface  110 F 1  of the semiconductor substrate  110 . For example, a width of the interface layer  136 C may become smaller in the Z direction from the second surface  110 F 2  to the first surface  110 F 1  of the semiconductor substrate  110 . The interface layer  136 C may include polysilicon containing a P-type dopant or an N-type dopant. 
     In the manufacturing process of the image sensor  100 C according to the example embodiments, a first conductive layer  134 A 2  (see  FIG.  12 A ) may be formed on an inner wall of the pixel trench  130 T by using polysilicon containing the P-type dopant or the N-type dopant. And then, by performing anisotropic etching to the first conductive layer  134 A 2 , a top portion  134 A 2 T of the first conductive layer  134 A 2  (see  FIG.  12 B ) may have the tapered shape while a top entrance of the pixel trench  130 T may be expanded. Thereafter, a second conductive layer  134 B 2  (see  FIG.  12 C ) may be formed on the first conductive layer  134 A 2  using polysilicon containing the fining element. Herein, a part of the first conductive layer  134 A 2  may correspond to the interface layer  136 C and a part of the second conductive layer  134 B 2  may correspond to the buried conductive layer  134 C, respectively. 
       FIGS.  7 A- 7 L  illustrate cross-sectional views of stages in a method of manufacturing the image sensor  100  in accordance with example embodiments. In  FIGS.  7 A- 7 L , cross-sectional views corresponding to the cross-sectional views taken along line II-II′ of  FIG.  1    are shown in the order of process. In  FIGS.  7 A- 7 L , the same reference numerals as in  FIGS.  1 - 6    denote the same elements. 
     Referring to  FIG.  7 A , the semiconductor substrate  110  having the first surface  110 F 1  and the second surface  110 F 2  opposite to each other is provided. 
     Thereafter, a first mask layer  210  having an opening  210 H may be formed on the first surface  110 F 1  of the semiconductor substrate  110  and using the first mask layer  210 , a part of the semiconductor substrate  110  may be removed from the first surface  110 F 1  to form an isolation trench ST. 
     Referring to  FIG.  7 B , an isolation insulating layer  220  may be formed on the first surface  110 F 1  of the semiconductor substrate  110  and the first mask layer  210  to fill the isolation trench ST. The isolation insulating layer  220  may be formed using silicon oxide, silicon oxynitride, or silicon nitride. 
     Thereafter, a mask pattern may be formed on the isolation insulating layer  220 , and the pixel trench  130 T may be formed in the semiconductor substrate  110  using the mask pattern. 
     The pixel trench  130 T may have a first height h 01  from the first surface  110 F 1  of the semiconductor substrate  110  and may have a first width w 11  along a first direction (an X direction) at the same level as the first surface  110 F 1  of the semiconductor substrate  110 . In an implementation, the pixel trench  130 T may have an aspect ratio of about 20 to about 100. 
     In an implementation, the pixel trench  130 T may have a second width w 13  (that is less than the first width w 11  along the first direction (the X direction)) at a bottom portion  130 TB of the pixel trench  130 T. In this case, a sidewall  130 TS of the pixel trench  130 T may be slightly inclined so that the width of the pixel trench  130 T becomes narrower from the top to the bottom of the pixel trench  130 T. 
     Referring to  FIG.  7 C , a preliminary insulating liner  132 P may be conformally formed on the isolation insulating layer  220  and the inner wall of the pixel trench  130 T by a chemical vapor deposition (CVD) process, or an atomic layer deposition (ALD) process. The preliminary insulating liner  132 P may have substantially the same thickness on the sidewall  130 TS and the bottom portion  130 TB of the pixel trench  130 T. 
     Referring to  FIG.  7 D , a conductive layer  134 P filling the inner of the pixel trench  130 T may be formed on the preliminary insulating liner  132 P. The conductive layer  134 P may include polysilicon containing the fining element at a first concentration. 
     In an implementation, the process of forming the conductive layer  134 P may include the CVD process or the ALD process using a silicon source material and the fining element source material as precursors. In an implementation, when the fining element includes oxygen, the fining element source material may include, e.g., an oxidizing agent such as nitrogen oxide (N 2 O) or nitrogen monoxide (NO). In an implementation, when the fining element includes carbon, the fining element source material may include, e.g., hydrocarbons such as methane (CH 4 ), ethylene (C 2 H 4 ), acetylene (C 2 H 2 ) or propane (C 3 H 8 ). In an implementation, when the fining element includes fluorine, the fining element source material may include, e.g., a fluorine-containing precursor material such as nitrogen trifluororide (NF 3 ), silicon tetrafluoride (SiF 4 ), etc. 
     For example, the conductive layer  134 P may be formed by reaction according to the following Formula 1 using a silicon source material and an oxygen source material.
 
SiH 4 (g)+N 2 O→Si(s)+O+2H 2 (g)+N 2 (g)  Formula 1
 
     In an implementation, the conductive layer  134 P may include polysilicon containing about 5 at % to 40 at % of oxygen. In an implementation, when the fining element includes carbon or fluorine, the conductive layer  134 P may include polysilicon containing about 1 at % to 20 at % of carbon or polysilicon containing about 1 at % to 20 at % of fluorine. 
     The conductive layer  134 P may be formed to include polysilicon containing the fining element at the first concentration, and the conductive layer  134 P may have a relatively small grain size. For example, the conductive layer  134 P may have polycrystalline microstructure having an average grain size of less than about 30 nm. In an implementation, voids or seams may not be formed within the conductive layer  134 P in the pixel trench  134 T having a relatively large aspect ratio. 
     Referring to  FIG.  7 E , a portion of the conductive layer  134 P (see  FIG.  7 D ) on the preliminary insulating liner  132 P outside the pixel trench  134 T may be removed to remain the buried conductive layer  134  in the pixel trench  134 T. In an implementation, as shown in  FIG.  7 E , the top surface of the buried conductive layer  134  may be at a lower level than the first surface  110 F 1  of the semiconductor substrate  110 . 
     Referring to  FIG.  7 F , a preliminary buried insulating layer  140 P may be formed on the buried conductive layer  134  and the preliminary insulating liner  132 P using an insulating material. The preliminary buried insulating layer  140 P may fill the remaining space of the pixel trench  130 T. 
     Referring to  FIG.  7 G , a portion of the preliminary buried insulating layer  140 P (see  FIG.  7 F ), a portion of the preliminary insulating liner  132 P (see  FIG.  7 F ), a portion of the isolation insulating layer  220  and the first mask layer  210  (see  FIG.  7 F ) may be removed to expose the first surface  110 F 1  of the semiconductor substrate  110 . A remaining portion of the preliminary buried insulating layer  140 P may be the buried insulating layer  140 , a remaining portion of the preliminary insulating liner  132 P may be the insulating liner  132  and a remaining portion of the isolation insulating layer  220  may be the isolation film STI. 
     Referring to  FIG.  7 H , a photoelectric conversion region  120  including a photodiode region  122  and a well region  124  may be formed from or at the first surface  110 F 1  of the semiconductor substrate  110  by an ion implantation process. For example, the photodiode region  122  may be formed by doping with N-type impurities, and the well region  124  may be formed by doping with P-type impurities. 
     A gate structure including a transmission gate TG and a transmission gate insulating layer TGI may be formed on the first surface  110 F 1  of the semiconductor substrate  110  and then a floating diffusion region FD and an active region may be formed in a part of the first surface  110 F 1  of the semiconductor substrate  110  by the ion implantation process. 
     Referring to  FIG.  7 I , a first interconnection structure  152  and a first interlayer insulating film  154  covering the first interconnection structure  152  may be formed on the semiconductor substrate  110  by repeatedly performing the operations of forming a conductive layer on the first surface  110 F 1  of the semiconductor substrate  110 , patterning the conductive layer, and forming an insulating layer covering the patterned conductive layer. 
     Thereafter, a supporting substrate  170  may be adhered to the first interlayer insulating film  154 . An adhesive layer may be between the supporting substrate  170  and the first interlayer insulating film  154 . 
     Referring to  FIG.  7 J , the semiconductor substrate  110  may be inverted such that the second surface  110 F 2  of the semiconductor substrate  110  faces upward. Herein, the bottom portion  130 TB of the pixel trench  130 T may not be exposed at the second surface  110 F 2 . 
     Referring to  FIG.  7 K , a portion of the semiconductor substrate  110  may be removed from or at the second surface  110 F 2  of the semiconductor substrate  110  by a planarization process such as a CMP process or an etch-back process until the buried conductive layer  134  is exposed. As the removal process is performed, the level of the second surface  110 F 2  of the semiconductor substrate  110  may be lowered. 
     One active pixel PX surrounded by the pixel isolation film  130  may be physically and electrically separated from the active pixel PX adjacent thereto. The pixel trench  130 T extends from the first surface  110 F 1  to the second surface  110 F 2  of the semiconductor substrate  110  and may have a first height h 11  along the vertical direction, the Z direction. In an implementation, the first height h 11  of the pixel trench  130 T after the planarization process may be smaller than the first height h 01  (see  FIG.  7 B ) of the pixel trench  130 T prior to the planarization process. In an implementation, the first height h 11  of the pixel trench  130 T after the planarization process may be substantially identical to the first height h 01  of the pixel trench  130 T before the planarization process. 
     Thereafter, a rear insulating layer  160  may be formed on the second surface  110 F 2  of the semiconductor substrate  110 , the buried conductive layer  134 , and the insulating liner  132 . The rear insulating layer  160  may be formed using an insulating material such as a metal oxide such as hafnium oxide, aluminum oxide, tantalum oxide, or the like, silicon oxide, silicon nitride, silicon oxynitride, or a low-k material. 
     Referring to  FIG.  7 L , a conductive layer may be formed on the rear insulating layer  160 , and the conductive layer may be patterned to form a guide pattern  162 . The guide pattern  162  may overlap the pixel isolation film  130  in the active pixel region APR. 
     Thereafter, a conductive pad PAD (see  FIG.  1   ) may be formed on the rear insulating layer  160  in the pad region PDR. The conductive pad PAD may be formed by sequentially forming a first metal layer and a second metal layer. For example, the first metal layer may be formed using the metal material such as titanium, titanium nitride, tantalum, tantalum nitride, titanium tungsten, tungsten, aluminum, cobalt, nickel or copper by a CVD process, an ALD process or the like. The second metal layer may be formed using the metal material such as tungsten, aluminum, cobalt, nickel, or copper by a CVD process, an ALD process, a plating process, or the like. 
     Thereafter, a passivation layer  164  may be formed on the rear insulating layer  160  and the guide pattern  162  and a color filter  166  and a microlens  168  may be formed on the passivation layer  164 . 
     The image sensor  100  may be completed by the above-described process. 
     According to the method of manufacturing the image sensor according to the above-described example embodiments, the buried conductive layer  134  may be formed using polysilicon containing the fining element, and voids or seams may not be formed in the buried conductive layer  134 . Further, even though the heat treatment process is further performed, the fining element included in the buried conductive layer  134  may suppress the movement of silicon atoms or inhibit grain growth, and therefore the formation of voids or seams may be prevented inside the buried conductive layer  134 . 
       FIG.  8    illustrates a flowchart of a method of manufacturing the image sensor  100  according to the example embodiments.  FIGS.  9 A to  9 C  illustrate cross-sectional views of stages in a method of manufacturing the image sensor  100  according to the example embodiments.  FIG.  8    and  FIGS.  9 A to  9 C , the same reference numerals as in  FIGS.  1  to  7 L  denote the same elements. 
     First, the process described with reference to  FIGS.  7 A to  7 C  may be performed to form a preliminary insulating liner  132 P inside the pixel trench  130 T. 
     Referring to  FIGS.  8  and  9 A , a first conductive layer  134 A 1  including polysilicon may be formed on an inner wall of the pixel trench  130 T (operation S 210 ). The first conductive layer  134 A 1  may include polysilicon that is free of impurities or fining elements. 
     In an implementation, the first conductive layer  134 A 1  may be formed by a reaction according to the following Formula 2 using a silicon source material.
 
SiH 4 (g)→Si(s)+2H 2 (g)  Formula 2
 
     Referring to  FIGS.  8  and  9 B , a second conductive layer  134 B 1  including polysilicon containing fining elements may be formed on the first conductive layer  134 A 1  to fill an interior of the pixel trench  130 T (operation S 220 ). 
     In an implementation, when the fining element includes oxygen, the second conductive layer  134 B 1  may be formed using a silicon source material and an oxygen source material by the reaction according to Formula 1 below.
 
SiH 4 (g)+N 2 O→Si(s)+O+2H 2 (g)+N 2 (g)  Formula 1
 
     Referring to  FIGS.  8  and  9 C , the semiconductor substrate  110  may be heat-treated, e.g., annealed (operation S 230 ). The fining element contained in the second conductive layer  134 B 1  may be diffused into the first conductive layer  134 A 1  by the heat treatment process, to thereby form a conductive layer  134 P 1 . 
     In an implementation, the process for forming the first conductive layer  134 A 1  and the process for forming the second conductive layer  134 B 1  may be performed in-situ within the same chamber or reactor. In an implementation, the process for forming the first conductive layer  134 A 1  and the process for forming the second conductive layer  134 B 1  may be performed ex-situ in different chambers or reactors. 
     In an implementation, as illustrated in  FIGS.  8  and  9 A to  9 C , the second conductive layer  134 B 1  may be formed to fill the pixel trench  130 T. In an implementation, the first conductive layer  134 A 1  and the second conductive layer  134 B 1  having a relatively thin thickness may be alternately and repeatedly formed on the inner wall of the pixel trench  130 T. For example, the processes of forming the first conductive layer  134 A 1  and the second conductive layer  134 B 1  may be repeated n times to fill the inside of the pixel trench  130 T. 
     Thereafter, the image sensor  100  may be completed by performing the processes described with reference to  FIGS.  7 E to  7 L . 
       FIG.  10    illustrates a flowchart of a method of manufacturing the image sensor  100  according to the example embodiments. 
     Referring to  FIG.  10    together with  FIG.  9 A , a first conductive layer  134 A 1  containing polysilicon containing fining elements may be formed on the inner wall of the pixel trench  130 T (operation S 210 A). 
     Referring to  FIG.  10    together with  FIG.  9 B , a second conductive layer  134 B 1  including polysilicon not containing the fining elements or impurities may be formed on the first conductive layer  134 A 1  to fill the inside of the pixel trench  130 T (operation S 220 A). 
     Referring to  FIG.  10    together with  FIG.  9 C , the semiconductor substrate  110  may be heat-treated (operation S 230 A). The fining elements included in the first conductive layer  134 A 1  may be diffused into the second conductive layer  134 B 1  by the heat treatment process to form the conductive layer  134 P 1 . 
       FIG.  11    illustrates a flowchart of stages in a method of manufacturing the image sensor  100  according to the example embodiments.  FIGS.  12 A to  12 D  illustrate cross-sectional views of stages in a method of manufacturing the image sensor  100  according to example embodiments. 
     First, the process described with reference to  FIGS.  7 A to  7 C  is performed to form a preliminary insulating liner  132 P inside the pixel trench  130 T. 
     Referring to  FIGS.  11  and  12 A , a first conductive layer  134 A 2  including polysilicon may be formed on an inner wall of the pixel trench  130 T (operation S 210 B). The first conductive layer  134 A 2  may include polysilicon that is free of impurities or fining elements. 
     Referring to  FIGS.  11  and  12 B , an anisotropic etching process may be performed on the first conductive layer  134 A 2  (operation S 215 B). A portion of the first conductive layer  134 A 2  on the preliminary insulating liner  132 P on the first surface  110 F 1  of the semiconductor substrate  110  and a portion of the first conductive layer  134 A 2  on the bottom portion  130 TB of the pixel trench  130 T may be removed by the anisotropic etching process. The first conductive layer  134 A 2  may remain on a sidewall  130 TS of the pixel trench  130 T and a top portion  134 A 2 T of the first conductive layer  134 A 2  may remain and may have a tapered shape in a direction (Z direction) toward the first surface  110 F 1  of the semiconductor substrate  110  (e.g., in the direction toward an entrance of the pixel trench  130 T). As the top portion  134 A 2 T of the first conductive layer  134 A 2  has a tapered shape, the entrance of the pixel trench  130 T may expand laterally as compared to the bottom of the pixel trench  130 T. 
     Referring to  FIGS.  11  and  12 C , a second conductive layer  134 B 2  including polysilicon containing the fining elements may be formed on the first conductive layer  134 A 2  to fill the inside of the pixel trench  130 T (operation S 220 B). 
     As the entrance of the pixel trench  130 T expands laterally as compared to the bottom of the pixel trench  130 T, the source material may be smoothly supplied to the inside of the pixel trench  130 T in the process of forming the second conductive layer  134 B 2 . Thus, the second conductive layer  134 B 2  may densely fill the inside of the pixel trench  130 T without voids or seams. 
     Referring to  FIGS.  11  and  12 D , the semiconductor substrate  110  may be heat-treated, e.g., annealed (operation S 230 B). The fining elements included in the second conductive layer  134 B 2  may be diffused into the first conductive layer  134 A 2  by the heat treatment process to form the conductive layer  134 P 2 . 
     In an implementation, the process for forming the first conductive layer  134 A 2 , the process for anisotropically etching the first conductive layer  134 A 2 , and the process for forming the second conductive layer  134 B 2  may be performed in-situ in a same chamber or reactor. In an implementation, the process for forming the first conductive layer  134 A 2 , the process for anisotropically etching the first conductive layer  134 A 2 , and the process for forming the second conductive layer  134 B 2  may be performed ex-situ in different chambers or reactors. 
     In an implementation, as illustrated in  FIGS.  11  and  12 A to  12 D , the second conductive layer  134 B 2  may include polysilicon containing the fining elements. In an implementation, the first conductive layer  134 A 2  may include polysilicon containing the fining elements and the second conductive layer  134 B 2  may include polysilicon that does not contain the fining elements or impurities. 
     In an implementation, as illustrated in  FIGS.  11  and  12 A to  12 D , the second conductive layer  134 B 2  may fill the pixel trench  130 T. In an implementation, on the inner wall of the pixel trench  130 T, the first conductive layer  134 A 2  and the second conductive layer  134 B 2  having a relatively thin thickness may be alternately and repeatedly formed. For example, the process of forming the first conductive layer  134 A 2 , the anisotropic etching process of the first conductive layer  134 A 2 , the process of forming the second conductive layer  134 B 2 , and the anisotropic etching process of the second conductive layer  134 B 2  are repeated n times, and finally, the first conductive layer  134 A 2  may be formed to fill the inside of the pixel trench  130 T. 
     Thereafter, the image sensor  100  may be completed by performing the processes described with reference to  FIGS.  7 E to  7 L . 
       FIG.  13    illustrates a flowchart of a method of manufacturing the image sensor  100 A according to the example embodiments. 
     Referring to  FIG.  13    together with  FIG.  9 A , a first conductive layer  134 A 1  including polysilicon containing dopant at a second concentration may be formed on the inner wall of the pixel trench  130 T (operation S 210 C). The dopant may include the N-type dopant or the P-type dopant. 
     In an implementation, the first conductive layer  134 A 1  may be formed by reactions according to Formula 3 or Formula 4 using the silicon source material and the dopant source material.
 
SiH 4 (g)+PH 3 →Si(s)+P+H 2 (g)  Formula 3
 
SiH 4 (g)+BCl 3 →Si(s)+B+H 2 (g)+Cl 2 (g)  Formula 4
 
     Referring to  FIG.  13    together with  FIG.  9 B , a second conductive layer  134 B 1  including polysilicon containing fining elements at the first concentration may formed on the first conductive layer  134 A 1 , to thereby fill the inside of the pixel trench  130 T (operation S 220 C). 
     Referring to  FIG.  13    together with  FIG.  9 C , the semiconductor substrate  110  may be heat-treated (operation S 230 C). The dopant contained in the first conductive layer  134 A 1  may be diffused into the second conductive layer  134 B 1  by the heat treatment process and the fining elements contained in the second conductive layer  134 B 1  may be diffused into the first conductive layer  134 A 1 , so that the conductive layer  134 P 1  may be formed. 
     Thereafter, the image sensor  100 A including the buried conductive layer  134 A may be completed by performing the processes described with reference to  FIGS.  7 E to  7 L . 
     In an implementation, as illustrated in  FIG.  13   , the dopant and the fining elements may be uniformly dispersed in the entire region of the buried conductive layer  134 A by performing the heat treatment process. In an implementation, the heat treatment process of the semiconductor substrate  110  may be omitted and the first conductive layer  134 A 1  portion may be remained as the interface layer  136 B and the second conductive layer  134 B 1  portion may be remained as the buried conductive layer  134 B. In this case, the image sensor  100 B described with reference to  FIG.  5    may be formed. 
       FIG.  14    illustrates a flowchart of a method of manufacturing the image sensor  100 A according to the example embodiments. 
     Referring to  FIG.  14    together with  FIG.  12 A , a first conductive layer  134 A 2  including polysilicon containing dopants at the second concentration may be formed on the inner wall of the pixel trench  130 T (operation S 210 D). The dopant may include the N-type dopant or the P-type dopant. 
     Referring to  FIG.  14    together with  FIG.  12 B , an anisotropic etching process may be performed on the first conductive layer  134 A 2  (operation S 215 D). The first conductive layer  134 A 2  may remain on the sidewall  130 TS of the pixel trench  130 T by the anisotropic etching process and the entrance of the pixel trench  130 T may be further expanded laterally as compared to the bottom of the pixel trench  130 T. 
     Referring to  FIG.  14    together with  FIG.  12 C , a second conductive layer  134 B 2  including polysilicon containing fining elements at a first concentration may be formed on the first conductive layer  134 A 2  to thereby fill the inside of the pixel trench  130 T (operation S 220 D). 
     Referring to  FIG.  14    together with  FIG.  12 D , the semiconductor substrate  110  may be heat-treated (operation S 230 D). The dopants contained in the first conductive layer  134 A 2  may be diffused into the second conductive layer  134 B 2  by the heat treatment process and the fining elements contained in the second conductive layer  134 B 2  may be diffused into the first conductive layer  134 A 2 , so that the conductive layer  134 P 2  may be formed. 
     Thereafter, the image sensor  100 A including the buried conductive layer  134 A may be completed by performing the processes described with reference to  FIGS.  7 E to  7 L . 
     In an implementation, as illustrated in  FIG.  14   , the dopants and the fining elements may be uniformly dispersed in the entire region of the buried conductive layer  134 A by performing the heat treatment process. In an implementation, the heat treatment process of the semiconductor substrate  110  may be omitted and the portion of the first conductive layer  134 A 2  may be remained as the interface layer  136 C and the portion of the second conductive layer  134 B 2  may remain as the buried conductive layer  134 C. In this case, the image sensor  100 C described with reference to  FIG.  6    may be formed. 
     By way of summation and review, as a degree of integration of the image sensor increases, a size of each of the plurality of photodiode regions may be reduced. A degree of difficulty of a process for forming the pixel isolation region may increase. 
     One or more embodiments may provide an image sensor including a photodiode. 
     One or more embodiments may provide an image sensor that may fill a buried conductive layer without voids or seams in a pixel isolation region having a large aspect ratio. 
     Example embodiments have been disclosed herein, and although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purpose of limitation. In some instances, as would be apparent to one of ordinary skill in the art as of the filing of the present application, features, characteristics, and/or elements described in connection with a particular embodiment may be used singly or in combination with features, characteristics, and/or elements described in connection with other embodiments unless otherwise specifically indicated. Accordingly, it will be understood by those of skill in the art that various changes in form and details may be made without departing from the spirit and scope of the present invention as set forth in the following claims.