Patent Publication Number: US-7724040-B2

Title: Network overclock control circuit

Description:
BACKGROUND 
   1. Field of the Invention 
   The present invention relates to an overclock control circuit. 
   2. Description of Related Art 
   The technique of overclocking is to make a central processing unit (CPU) run at a higher speed by adjusting the working frequency to be above the normal frequency. For example, the working frequency of Pentium IV 2.4 can be adjusted to 2800 MHz, thus improving the speed of the CPU. 
   Conventionally overclocking of the CPU is achieved manually by a user, however the steps involved are complicated and if not done right can lead to problems and instability with the device using the CPU. 
   What is desired, therefore, is to provide an overclock control circuit for automatically adjusting CPU frequency of a computer according to a status of a network. 
   SUMMARY 
   An exemplary network overclock control circuit for a computer includes a resistor/capacitor (RC) circuit, first and second comparator circuits, and first and second switch circuits. An input terminal of the RC circuit is connected to a signal pin of a network indicating lamp to receive a pulse signal. The RC circuit converting the pulse signal to a direct current (DC) voltage. An input terminal of the first comparator circuit is connected to the DC voltage. An input terminal of the second comparator circuit is connected to the DC voltage. An output terminal of the first comparator circuit is connected to an input terminal of the first switch circuit. An output terminal of the second comparator circuit is connected to an input terminal of the second switch circuit. An output terminal of the first switch circuit is connected to a first clock pin of a clock chip. An output terminal of the second switch circuit is connected to a second clock pin of the clock chip. When the network has little traffic, the first and second comparator circuits output control signals to control the first and second switch circuits to output low level signals. When the network has medium to high traffic, the first and second comparator circuits output control signals to control the first and second switch circuits to output a high level signal and a low level signal respectively. When the network is overloaded, the first and second comparator circuits output control signals to control the first and second switch circuits to output high level signals. The clock chip controls overclocking of the CPU according to signal levels of the first and second clock pins. 
   Other advantages and novel features of the present invention will become more apparent from the following detailed description of preferred embodiment when taken in conjunction with the accompanying drawing, in which: 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The drawing is a circuit diagram of an overclock control circuit in accordance with an exemplary embodiment of the present invention. 
   

   DETAILED DESCRIPTION 
   Referring to the drawing, an overclock control circuit for a central processing unit (CPU) in accordance with an exemplary embodiment of the present invention includes an RC circuit  10 , two comparator circuits  20  and  30 , and two switch circuits  40  and  50 . 
   The RC circuit  10  includes a resistor R 1  and a capacitor C 1 . A signal pin LED_LAN_ACTJ of a network indicating lamp of a computer is grounded via the resistor R 1  and the capacitor C 1  in series. The RC circuit converts a pulse signal from signal pin LED_LAN_ACTJ of a network indicating lamp to a direct current (DC) voltage Vdc. The DC voltage Vdc is connected to a node between the resistor R 1  and the capacitor C 1 . 
   The comparator circuit  20  includes a comparator U 1 . Resistors R 2  and R 3  connected in series between a power source Vcc 1  and ground, form a voltage divider. The inverting input terminal of the comparator U 1  is connected to the DC voltage Vdc. The non-inverting input terminal (reference terminal) of the comparator U 1  is connected to a node between the resistor R 2  and the resistor R 3  to receive a reference voltage Vref 1 . The power terminal of the comparator U 1  is connected to a power source Vcc 2 . 
   The comparator circuit  30  includes a comparator U 2 . Resistors R 4  and R 5  connected in series between the power source Vcc 1  and ground, form a voltage divider. The inverting input terminal of the comparator U 2  is connected to the DC voltage Vdc. The non-inverting input terminal (reference terminal) of the comparator U 2  is connected to a node between the resistor R 4  and the resistor R 5  to receive a reference voltage Vref 2 . The power terminal of the comparator U 2  is connected to the power source Vcc 2 . 
   The reference voltage Vref 1  can be selected according to the values chosen for the resistances of the resistors R 2  and R 3 . The reference voltage Vref 2  can be selected according to the values chosen for the resistances of the resistors R 4  and R 5 . The reference voltage Vref 1  is set to be greater than the reference voltage Vref 2 . 
   The switch circuit  40  includes two transistors Q 1  and Q 10 . The gate of the transistor Q 1  is connected to the output terminal of the comparator U 1  via a resistor R 6 . The drain of the transistor Q 1  is connected to a power source Vcc 3  via a resistor R 7 , and connected to the base of the transistor Q 10 . The source of the transistor Q 1  is connected to the emitter of the transistor Q 10 , and ground. The collector of the transistor Q 10  is connected to a power source Vcc 4  via a resistor R 8 , and connected to a clock pin TURBO_CLK 1  of a clock chip (not shown). 
   The switch circuit  50  includes two transistors Q 2  and Q 20 . The gate of the transistor Q 2  is connected to the output terminal of the comparator U 2  via a resistor R 9 . The drain of the transistor Q 2  is connected to the power source Vcc 3  via a resistor R 10 , and connected to the base of the transistor Q 20 . The source of the transistor Q 2  is connected to the emitter of the transistor Q 20 , and ground. The collector of the transistor Q 20  is connected to the power source Vcc 4  via a resistor R 11 , and connected to a clock pin TURBO_CLK 2  of the clock chip. The clock chip provides control signals from the clock pins TURBO_CLK 1  and TURBO_CLK 2  to control frequency of the CPU. 
   In this embodiment, the transistors Q 1  and Q 2  are N-channel field effect transistors (FETs), and the transistors Q 10  and Q 20  are NPN bipolar junction transistors (BJTs). 
   When the network has little traffic, the signal pin LED_LAN_ACTJ of the network indicating lamp outputs a high level signal. The DC voltage Vdc received by the inverting input terminal of the comparator U 1  is greater than the reference voltage Vref 1  of the non-inverting input terminal of the comparator U 1 . The comparator U 1  outputs a low level signal. The FET Q 1  is turned off. The transistor Q 10  is turned on. The collector of the transistor Q 10  outputs a low level signal to the clock pin TURBO_CLK 1  of the clock chip. The DC voltage Vdc received by the inverting input terminal of the comparator U 2  is greater than the reference voltage Vref 2  of the non-inverting input terminal of the comparator U 2 . The comparator U 2  outputs a low level signal. The FET Q 2  is turned off. The transistor Q 20  is turned on. The collector of the transistor Q 20  outputs a low level signal to the clock pin TURBO_CLK 2  of the clock chip. The CPU is not overclocked. 
   When the network has medium to high traffic, the signal pin LED_LAN_ACTJ of the network indicating lamp outputs a pulse signal with a low frequency (making the blink frequency low). The voltage Vdc is reduced to be less than the reference voltage Vref 1  of the non-inverting input terminal of the comparator U 1  but greater than the reference voltage Vref 2  of the non-inverting input terminal of the comparator U 2 . The comparator U 1  outputs a high level signal. The FET Q 1  is turned on. The transistor Q 10  is turned off, the clock pin TURBO_CLK 1  of the clock chip receives a high level signal. The comparator U 2  outputs a low level signal. The FET Q 2  is turned off. The transistor Q 20  is turned on, the collector of the transistor Q 20  outputs a low level signal to the clock pin TURBO_CLK 2  of the clock chip. The CPU is automatically overclocked by a predetermined intermediate amount. 
   When the network is overloaded, the signal pin LED_LAN_ACTJ of the network indicating lamp outputs a pulse signal with a high frequency (making the blink frequency high). The voltage Vdc is reduced to be less than the reference voltage Vref 1  of the non-inverting input terminal of the comparator U 1 , and reduced to be less than the reference voltage Vref 2  of the non-inverting input terminal of the comparator U 2 . The comparator U 1  outputs a high level signal. The FET Q 1  is turned on. The transistor Q 10  is turned off. The clock pin TURBO_CLK 1  of the clock chip receives a high level signal. The comparator U 2  outputs a high level signal. The FET Q 2  is turned on. The transistor Q 20  is turned off. The clock pin TURBO_CLK 2  of the clock chip receives a high level signal. The CPU is automatically overclocked by large predetermined amount. 
   The user may activate or deactivate the network overclock control circuit in the BIOS (base input/output system) of the computer. When the network overclock control circuit is opened, the CPU of the computer can automatically adjust frequency according to a status of the network loading. The network overclock control circuit is simple, and low-cost. 
   It is to be understood, however, that even though numerous characteristics and advantages of the present invention have been set forth in the foregoing description, together with details of the structure and function of the invention, the disclosure is illustrative only, and changes may be made in detail, especially in matters of shape, size, and arrangement of parts within the principles of the invention to the full extent indicated by the broad general meaning of the terms in which the appended claims are expressed.