Patent Publication Number: US-2004041776-A1

Title: Electro-optical device, driver circuit for electro-optical device, drive method for driving electro-optical device, and electronic equipment

Description:
BACKGROUND OF THE INVENTION  
       [0001] 1. Field of Invention  
       [0002] The present invention relates to an electro-optical device of an active matrix scheme, a driver circuit for an electro-optical device, a drive method to drive an electrooptical device, and an electronic equipment.  
       [0003] 2. Description of Related Art  
       [0004] In general, a related art electro-optical device, such as a liquid crystal device which presents a predetermined display by employing a liquid crystal as an electro-optical substance, is so constructed that the liquid crystal is sandwiched in between a pair of substrates. Particularly in an electro-optical device, such as a liquid crystal device of an active-matrix drive scheme based on TFT drive, TFD drive or the like, a TFT array substrate or the like is overlaid with large numbers of scanning lines and data lines which are respectively arrayed vertically and laterally, a large number of pixel electrodes which are disposed in correspondence with the intersection points of the scanning lines and the data lines, and so forth.  
       [0005] The individual scanning lines are sequentially fed with scanning signals from a scanning line driver circuit. On the other hand, the data lines are fed with image signals by a sampling circuit, which is driven by a data line driver circuit. More specifically, the data line driver circuit is constructed so as to feed a sampling circuit, by which image signals on an image signal line are sampled for the respective data lines, with sampling circuit drive signals in parallel with the sequential feed operations of the scanning signals.  
       [0006] The data line driver circuit includes, in general, a plurality of latch circuits (a shift register circuit), which sequentially shift a transfer signal fed at the outset of a horizontal scanning period in accordance with a clock signal, and which output the shifted signals as the sampling signals. Likewise, the scanning line driver circuit includes a plurality of latch circuits, which sequentially shift a transfer signal fed at the outset of a vertical scanning period in accordance with a clock signal, and which output the shifted signals as the scanning signals. The sampling circuit includes sampling switches which are disposed for the respective data lines, and by which the image signals fed from outside are sampled in accordance with the sampling signals based on the data line driver circuit, so as to be fed to the corresponding data lines.  
       [0007] Accordingly, the sampling signals of the respective data lines need to be generated exclusively from one another. Nevertheless, the sampling signals are sometimes outputted in overlapping fashion for any reason. Then, the image signal which needs to be sampled by one of the data lines is also sampled by the data line adjacent to this line. This results in the problem that so-called “ghost”, “cross-talk” or the like occurs to degrade a display quality.  
       [0008] The related art includes a technique to cope with the heightened frequency of dot clocks, such that an image signal of one loop is subjected to serial-to-parallel conversion (phase expansion) into a plurality of m loops, and the resulting image signals of the m loops are simultaneously sampled in accordance with a sampling signal so as to be fed onto m data lines. When the sampling signal is outputted in overlapping fashion in such a technique, the ghost, the cross-talk or the like appears in units of m lines, and hence, degradation in a display quality becomes a more serious problem.  
       [0009] Therefore, a related art enable circuit can be introduced in order to reduce or prevent the sampling signal from overlapping. The enable circuit includes a technique such that, in order to reduce or prevent the sampling switches from sampling image signals in accordance with successive sampling circuit drive signals which overlap on a time axis, the logical products between an enabling clock signal called an “enable signal” and the respective sampling circuit drive signals are taken, thereby to narrow the pulse width of each of the sampling circuit drive signals to the pulse width of the enable signal.  
       [0010] Some time interval is set as a temporal margin between the two successive sampling circuit drive signals by limiting the pulse width in this manner. Therefore, even when adverse effects such as ON resistances, wiring resistances, time constants, capacitances and delay times in active elements and various wiring lines of TFTs or the like, which constitute the sampling circuit, the data line driver circuit, etc., are relatively intensified with high frequency drive, the adverse effect can be partially or completely absorbed by the temporal margin stated above.  
       [0011] As a result, it is possible to reduce or efficiently prevent the so-called “cross-talk” or “ghost” from appearing between the data lines which are adjacent to each other, in a case where the image signals are not phase-expanded, or between the data lines which are connected to the identical image signal and which are successively driven, in a case where the image signals are phase-expanded.  
       [0012] Meanwhile, the above mentioned shift register circuit is constructed so as to generate transfer signals at individual stages on the basis of an X-side clock signal CLX which is inputted from an image signal processor circuit located outside and which serves as the reference of horizontal scanning (and the inverted signal CLX inv  thereof), and an enable signal ENB, and to output the transfer signals as the sampling circuit drive signals to the sampling switches which are connected to the corresponding scanning lines, respectively.  
       [0013] However, when the rises or falls of the clock signal CLX or the inverted signal CLX inv  thereof and the enable signal ENB occurs substantially at the same time, the level of high frequency noise which mixes into the image signal to be fed to the data line becomes conspicuously high. The high frequency noise is displayed as a vertical line blur on a screen, and incurs the problem of degrading a screen quality.  
       SUMMARY OF THE INVENTION  
       [0014] The present invention address the above and/or other problems, and provides an electro-optical device and an electronic equipment in which the logical status of a clock signal CLX or the inverted signal CLX inv  thereof is prevented from changing in an active enable signal period and a period vicinal thereto, whereby the level of noise to be mixed into an image signal can be lowered to suppress a vertical line blur.  
       [0015] An electro-optical device according to the present invention includes a plurality of scanning lines and a plurality of data lines, switching elements which are disposed in correspondence with intersection parts between the scanning lines and the data lines, pixel electrodes which are disposed in correspondence with the switching elements, and video signal lines which transmit image signals. Further, the device includes a data line drive device to sample the image signals transferred by the video signal lines and feeding them to the data lines, by using a clock which serves as reference of horizontal scanning and an enable signal which determines timings to feed the image signals to the data lines, and a timing generation device to set active periods of the enable signal which make the sampling of the image signals possible, in periods which do not include timings of rise or fall of the clock.  
       [0016] According to such a construction, the data line drive device samples the image signals transferred via the video signal lines and feeds them to the individual data lines by using the reference clock of the horizontal scanning and the enable signal. The timing generation device sets active periods of the enable signal which make the sampling of the image signals possible, in the periods which do not include the timings of the rise or fall of the clock. That is, neither the rise nor fall of the clock arises within the active periods of the enable signal which sets sampling periods. Accordingly, high frequency noises ascribable to the rise and fall of the clock can be reduced or prevented from mixing into the image signals in the periods in which the image signals are being fed to the data lines. Since the timing of the rise or fall of the clock and that of the rise or fall of the enable signal do not coincide, it does not occur that the noises of both the clock and the enable signal are superposed to drastically enlarge the noise level of the image signals. Thus, the level of noise to be mixed into the image signals can be reduced to prevent line blurs in a vertical direction from being displayed on a screen and to enhance a screen quality.  
       [0017] The electro-optical device is provided such that the timing generation device sets the active periods of the enable signal, in periods which are other than a period of predetermined width including the timing of the rise or fall of the clock.  
       [0018] According to such a construction, the rise and fall of the enable signal arise at timings, which are distant from the rise and fall of the clock more than the period of the predetermined width. Accordingly, the level of the sum between noise ascribable to the clock and noise ascribable to the enable signal is comparatively small, so that the level of high frequency noise to be mixed into the image signals which are fed to the data lines is sufficiently reduced.  
       [0019] The electro-optical device is provided such that the period of the predetermined width is a period, which is distant from the timing of the rise or fall of the clock more than 15 nanoseconds.  
       [0020] According to such a construction, the influences of noises ascribable to the rises or falls of the enable signal and the clock are sufficiently relieved, so that image signals of high screen quality can be obtained.  
       [0021] The electro-optical device is provided such that the enable signal has a plurality of active periods within one cycle of the clock, which serves as the reference of the horizontal scanning.  
       [0022] According to such a construction, the image signals can be fed to a plurality of data lines based on the enable signals in time division within one cycle of the clock, so that a clock frequency can be lowered.  
       [0023] An electronic equipment according to the present invention includes the above electro-optical device as the image formation device.  
       [0024] According to such a construction, the high frequency noises are reduced or prevented from mixing into the image signals in the above electro-optical device, so that an image of high image quality free from line blurs can be obtained.  
     
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
     [0025]FIG. 1 is a schematic showing an electro-optical device according to a first exemplary embodiment of the present invention;  
     [0026]FIG. 2 is a perspective view showing the construction of a liquid crystal panel  100  in FIG. 1;  
     [0027]FIG. 3 is a sectional view taken along plane A-A′ in FIG. 2;  
     [0028]FIG. 4 is a schematic circuit diagram showing a practicable construction of a data line driver circuit  140  in FIG. 1;  
     [0029]FIG. 5 is a timing chart showing various signals;  
     [0030]FIG. 6 is a timing chart showing a clock CLK and enable signals ENB 1  to ENB 4  in the case when image signals are fed to four data lines in time division within one clock CLK period;  
     [0031]FIG. 7 is a schematic showing an electronic equipment according to the present invention;  
     [0032]FIG. 8 is a schematic showing another electronic equipment according to the present invention; and  
     [0033]FIG. 9 is a schematic showing still another electronic equipment according to the present invention. 
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS  
     [0034] Exemplary embodiments of the present invention are described below with reference to the drawings. FIG. 1 is a schematic showing an electro-optical device according to a first exemplary embodiment of the present invention. This exemplary embodiment is an example in which the invention is applied to a liquid crystal device employing a liquid crystal as an electro-optical substance.  
     [0035] In this exemplary embodiment, the logical status of a clock signal CLX or the inverted signal CLX inv  thereof is prevented from changing at a timing at which image signals are fed to data lines, that is, in the active period of an enable signal and a period vicinal thereto in which the enable signal permits the feed of the image signals to the data lines, whereby the level of noise to be mixed into the image signals is lowered.  
     [0036] As shown in FIG. 1, the liquid crystal device includes a liquid crystal panel  100 , a timing generator  200 , and an image signal processor circuit  300 . Among them, the timing generator  200  outputs timing signals, control signals, etc., which are used in various portions. An S/P conversion circuit  302  in the image signal processor circuit  300  subjects an inputted image signal Video of one loop to serial-to-parallel conversion and outputs the resulting image signals of six loops in order to write them on the basis of phase expansion. The reason why the image signal is subjected to the serial-to-parallel conversion into the six loops is that, in a sampling circuit  150 , a time period to apply the image signal to the source region of a thin film transistor (hereinafter “TFT”) which constructs each sampling switch  151  is lengthened to sufficiently secure a sampling time period and charge/discharge time periods.  
     [0037] An amplifier/inverter circuit  304  inverts image signals resulting from the serial-to-parallel conversion which need to be inverted, and thereafter amplifies the inverted image signals as necessity, so as to feed as image signals VID 1  to VID 6  to the liquid crystal panel  100  in parallel. Whether or not the image signals are inverted is generally determined in accordance with whether a scheme to apply data signals is based on polarity inversion in units of scanning lines  112 , polarity inversion in units of data lines  114  or polarity inversion in pixel units, and the cycle of the inversion is set at one horizontal scanning period or dot clock cycle. This exemplary embodiment is described below by taking the case of the polarity inversion in units of the scanning lines  112  as an example for the sake of convenience, but the present invention shall not be construed to be restricted thereto.  
     [0038] The “polarity inversion” signifies to alternately invert the voltage levels of the image signals to a positive polarity and a negative polarity with a reference potential set at the center potential of the amplitudes of the image signals. Timings at which the image signals VID 1  to VID 6  of the six loops are fed to the liquid crystal panel  100  are simultaneous in the liquid crystal device shown in FIG. 1, but they may well be sequentially shifted in synchronism with dot clocks. In this case, the image signals of the six loops are sequentially sampled by a sampling circuit described below.  
     [0039]FIG. 2 is a perspective view showing the construction of the liquid crystal panel  100  in FIG. 1, while FIG. 3 is a sectional view taken along plane A-A′ in FIG. 2.  
     [0040] The liquid crystal panel  100  is so constructed that an element substrate  101  formed with various elements, pixel electrodes  118 , etc., and a counter substrate  102  provided with a counter electrode  108 , etc., are stuck together, with a predetermined gap held therebetween by a sealing member  104  containing spacers (not shown) and with their electrode formation surfaces opposing each other, and that a liquid crystal  105  of, for example, TN (Twisted Nematic) type is enclosed in the gap as an electro-optical substance.  
     [0041] Glass, a semiconductor, quartz or the like is employed for the element substrate  101 , while glass or the like is employed for the counter substrate  102 . In a case where an opaque substrate is employed as the element substrate  101 , the liquid crystal panel is used as a reflection type, not as a transmission type. The sealing member  104  is formed along the peripheral edge of the counter substrate  102 , and it is partially opened in order to enclose the liquid crystal  105 . Therefore, after the liquid crystal  105  has been enclosed, the open part is sealed by a sealant  106 .  
     [0042] Next, a data line driver circuit described below is formed on the counter surface of the element substrate  101  and in a region  140 , one latus outside of the sealing member  104 , so as to output sampling signals. Further, image signal lines, the sampling circuit, etc., may well be formed in the region  150  of the latus in the vicinity of the sealing member  104  to-be-formed. On the other hand, a plurality of mount terminals  107  are formed at the outer peripheral parts of the latus so as to input various signals from external circuits (not shown).  
     [0043] Scanning line driver circuits are respectively formed in the regions  130  of two latera adjacent to the above latus, so as to drive the scanning lines from both sides. If the delay of scanning signals to be fed to the scanning lines does not pose a problem, a construction in which only one scanning line driver circuit is formed on one side may well be adopted.  
     [0044] The counter electrode  108  provided on the counter substrate  102  is constructed so as electrically connected with the element substrate  101  by a conductive material at, at least, one of the four corners of a sealing portion by which the counter substrate  102  is stuck with the element substrate  101 .  
     [0045] Further, if necessary, colored layers (color filters) are provided in the regions of the counter substrate  102  opposing to the pixel electrodes  118 , though not especially illustrated. However, in a case where the liquid crystal panel is applied for the use of color light modulation as in a multiple-plate type projector described below, the counter substrate  102  need not be formed with the colored layers.  
     [0046] Orientation films (omitted from FIG. 3) subjected to rubbing treatment are respectively provided on the opposing surfaces of the element substrate  101  and the counter substrate  102 . Polarizers (not shown) conforming to the orientation directions of the orientation films are respectively disposed on the rear surface sides of the substrates  101 ,  102 . In FIG. 3, although the counter electrode  108 , pixel electrodes  118 , mount terminals  107 , etc. are made thick as a convenient measure to clarify their formation positions, they are actually thin enough to be neglected relative to the substrates.  
     [0047] The liquid crystal panel  100  is formed on the element substrate with the plurality of scanning lines  112  arrayed in parallel in an X-direction as shown in FIG. 1, and with the plurality of data lines  114  in parallel in a Y-direction orthogonal to the X-direction. At the intersection points between the scanning lines  112  and the data lines  114 , the gate electrodes of TFTs  116 , which are switches to control individual pixels, are connected to the scanning lines  112 , while the source electrodes of the TFTs  116  are connected to the data lines  114 , and the drain electrodes of the TFTs  116  are connected to the pixel electrodes  118 . In addition, the pixels are respectively constituted by the pixel electrodes  118 , the common electrode formed on the counter substrate, and the liquid crystal held between both of these electrodes, with the result that they are arrayed in the shape of a matrix in correspondence with the intersection points between the scanning lines  112  and the data lines  114 . Incidentally, a storage capacitor (not shown) may well be further formed electrically in parallel with the liquid crystal held between the corresponding pixel electrode  118  and the common electrode for every pixel.  
     [0048] A driver circuit  120  includes, at least, the scanning line driver circuit  130 , the data line driver circuit  140  and the sampling circuit  150 . The constituent elements of the driver circuit  120  are constructed by combining P-channel TFTs and N-channel TFTs which are formed by a manufacturing process common to that of the TFTs  116  for driving the pixels, so that the enhancement of a manufacturing efficiency, the lowering of a manufacturing cost, the homogenization of element characteristics, etc., are attained.  
     [0049]FIG. 4 is a schematic circuit diagram showing a practicable construction of the data line driver circuit  140  in FIG. 1.  
     [0050] The data line driver circuit  140  operates so that a transfer start pulse DX-R or DX-L fed at the outset of a horizontal scanning period is sequentially shifted in accordance with the clock signal CLX and the inverted clock signal CLX inv  thereof, thereby to output the sampling signals S 1  to Sn in a predetermined sequence.  
     [0051] The clock signal CLX as well as the inverted clock signal CLX inv  thereof, the transfer start pulse DX-R (DX-L) and enable signals (pulse width limitation signals) ENB 1 , ENB 2  to be fed to the data line driver circuit  140  are all fed in synchronism with the image signals VID 1  to VID 6  by the timing generator  200  in FIG. 1. Actually used as these signals are signals obtained in such a way that low logic amplitude signals fed from the timing generator  200  are converted into high logic amplitude signals by level shifters (not shown). The reason why logic amplitudes are converted in this manner, is that the timing generator  200  for feeding the various signals to the liquid crystal panel  100  is generally constructed of CMOS circuits and therefore produces output voltages of about 3 to 5 V, whereas the constituent elements of the data line driver circuit  140  are TFTs formed by the same process as that of the TFTs  116  to drive the pixels and therefore require comparatively high operating voltages of about 12 V.  
     [0052] The data line driver circuit  140  includes latch circuits  1430  which are connected in (n+1) stages. One latch circuit  1430  latches and outputs the last input level and feeds it as the input signal of the latch circuit  1430  located at the succeeding stage at the time of the level transitions (rise and fall) of the clock signal CLX and the inverted clock signal CLX inv  thereof.  
     [0053] Each latch circuit  1430  is capable of transfers in both the directions of an R-direction and an L-direction in the figure. In case of the R-directional transfer, the transfer start pulse DX-R is inputted from the left side of the latch circuit  1430 , whereas in case of the L-directional transfer, the transfer start pulse DX-L is inputted from the right side of the latch circuit  1430 . Therefore, the “succeeding stage” signifies the right side in the case of the R-directional transfer, and the left side in the case of the L-directional transfer. In driving the data line driver circuit  140  in both the directions, the enable signals ENB 1 , ENB 2  need not be changed-over in accordance with the transfer directions by setting the number n of stages at an odd number, so that the load of the external circuit can be lowered.  
     [0054] Letter i is for generalizing the latch circuits  1430  of the first stage to the (n+1)th stage in the description. The data line driver circuit in FIG. 4 is capable of the transfers in both the directions. A signal Si′ (a signal outputted from the latch circuit  1430  of the ith stage in the case of the R-directional transfer, or a signal outputted from the latch circuit  1430  of the (i+1)th stage in the case of the L-directional transfer) is fed to the first input node of a 3-input NAND circuit  1464 . The second input node of the NAND circuit  1464  is fed with the enable signal ENB 1  for the ordinal number i being odd, or with the enable signal ENB 2  for the ordinal number i being even. Further, the third input node of the NAND circuit  1464  is fed with the output signal of a NAND circuit  1462 , more specifically, the negative logical product signal of the enable signals ENB 1  and ENB 2 .  
     [0055] The enable signals ENB 1 , ENB 2  are signals which are used in order to prevent the adjacent ones of the signals S 1 ′ to Sn′ from simultaneously becoming an H level, each of which has a pulse width shorter than the half cycle of the clock signal CLX (or inverted clock signal CLX inv ), and which ought not to overlap each other.  
     [0056] The output signals of the NAND circuits  1464  corresponding to the individual stages are inverted by inverters  1466 , and the inverted signals are outputted as the sampling signals S 1  to Sn of the data line driver circuit  140 , respectively. Inverters  1466  may well be configured of an inverter of a single stage, or inverters of a plurality of stages, such as three stages or five stages.  
     [0057] In this exemplary embodiment, the enable signals ENB 1 , ENB 2  are set at L level periods disabling the sampling, at the rise or fall timings of the clocks CLK, CLK inv  and in a period vicinal thereto by the timing generator  200 .  
     [0058]FIG. 5 is a timing chart showing various signals.  
     [0059] As shown in FIG. 5, the enable signals ENB 1 , ENB 2  rise after a period “tb” since the rise timing of the clock CLX (the fall timing of the clock CLX inv ), and they fall before a period “tf” since the fall timing of the clock CLX (the rise timing of the clock CLX inv ). In this exemplary embodiment, the periods “tb”, “tf” are set at time periods of, for example, at least 15 nanoseconds. Alternatively, they are set at time periods of 15 to 20 nanoseconds.  
     [0060] As stated below, the image signals are sampled and fed to the data lines in the H periods of the enable signals ENB 1 , ENB 2 . Due to timing settings in FIG. 5, accordingly, neither of the clocks CLX, CLX inv  rises or falls in the periods in which the image signals are sampled and fed to the data lines, so that high frequency noise ascribable to the rise or fall is reduced or prevented from mixing into the image signals.  
     [0061] Assuming that the rise and fall timings of the enable signals ENB 1 , ENB 2  and the rise or fall timings of the clocks CLX, CLX inv  arise in proximity, the high frequency noises of both the signals are combined to greatly affect the image signals. However, Since the rise and fall timings of the enable signals ENB  1 , ENB 2  are set at the timings which are sufficiently distant from the rise or fall timings of the clocks CLX, CLX inv , the levels of the high frequency noises to be mixed into the image signals can be relieved.  
     [0062] Referring back to FIG. 1, the sampling circuit  150  sets every six data lines  114  as one group (block), and it samples the respective image signals VID 1  to VID 6  and feeds them to the data lines  114  belonging to such groups, in accordance with the sampling signals S 1  to Sn. More specifically, the sampling circuit  150  includes the switches  151 , which are disposed for the respective data lines  114 . Each of the switches  151  is interposed between one end of the corresponding data line  114  and a signal line which is fed with any of the image signals VID 1  to VID 6 , and its gate is fed with the sampling signal.  
     [0063] The scanning line driver circuit  130  has basically the same construction as that of the data line driver circuit  140 , except that the direction of leading out the output signals, and signals to be inputted are different. More specifically, the scanning line driver circuit  130  is such that the data line driver circuit  150  is arranged after being turned 90 degrees counterclockwise. As shown in FIG. 1, a pulse DY-D (DY-U) and a transfer control signal D (U) are inputted to this circuit  130  instead of the pulse DX-R (DX-L) and the transfer control signal R (L), and a clock signal CLY and the inverted clock signal CLY inv  thereof are inputted for every horizontal scanning period instead of the clock signal CLX and the inverted clock signal CLX inv  thereof.  
     [0064] In a case where a vertical scanning direction is the down direction, the pulse DY-D is fed at the outset of a vertical scanning period, and the transfer control signal D is activated. In contrast, in a case where the vertical scanning direction is the up direction, the pulse DY-U is fed at the outset of the vertical scanning period, and the transfer control signal U is activated. The clock signal CLY, the inverted clock signal CLY inv  thereof and the pulse DY-U (or DY-D) are fed in synchronism with the image signals VID 1  to VID 6  by the timing generator  200  in FIG. 1. Further, these signals and the transfer control signal R (L) have all been converted into signals of high logic amplitudes by level shifters (not shown).  
     [0065] By setting the frequencies of these clock signals to be low, it is sufficiently possible that the scanning signals which are fed to the adjacent ones of the scanning lines be substantially reduced or prevented from overlapping. Therefore, no problem is posed even when the scanning line driver circuit  130  is endowed with a simple construction which is based on a NAND circuit to narrow a pulse width, and an inverter succeeding it.  
     [0066] The operation of an exemplary embodiment thus constructed is described below. In the ensuing description, it is assumed for the sake of convenience that the vertical scanning direction be the down direction, while the horizontal scanning direction be the rightward (R) direction.  
     [0067] The scanning line driver circuit  130  is fed with the pulse DY-D at the outset of a vertical scanning period, and this pulse DY-D is sequentially shifted by the clock signal CLY and the inverted clock signal CLY inv  thereof so as to be outputted to the respective scanning lines  112 . Thus, the plurality of scanning lines  112  are selected in the down direction in line sequence one by one.  
     [0068] Due to the image signal processor circuit  300 , the image signal Video of one loop is distributed into the image signals VID 1  to VID 6  and is lengthened 6 times with respect to a time axis as shown in FIG. 5. Further, at the outset of a period in which a certain one of the scanning lines is selected, that is, at the outset of a horizontal scanning period, the data line driver circuit  140  is fed with the transfer start pulse DX-R as shown in the figure.  
     [0069] In an ordinary operation, the enable signals ENB 1 , ENB 2  are fed from the timing generator  200  so that, as shown in FIG. 5, the H level (active) periods thereof may not overlap each other. Therefore, the output signal of the NAND circuit  1462  in FIG. 4 continues to be at the H level and does not transits to an L level. For this reason, the output of the NAND circuit  1464  depends upon only the signal Si and the enable signal ENB 1 , for the ordinal number i being odd, and it depends upon only the signal Si and the enable signal ENB 2 , for the ordinal number i being even.  
     [0070] Therefore, the signals S 1 ′ to Sn′, which are obtained in such a way that the transfer start pulse DX-R fed at the outset is sequentially shifted for every half cycle of the clock signal CLX as well as the inverted clock signal CLX inv  thereof by the latch circuits  1430  of the first stage to the nth stage, are limited within the H level periods SMPa of the enable signals ENB 1 , ENB 2 . They are sequentially outputted as the sampling signals S 1  to Sn as shown in FIG. 5.  
     [0071] When the sampling signal S 1  has become the H level, the image signals VID 1  to VID 6  are respectively sampled onto the six data lines  114  belonging to this group, and these image signals VID 1  to VID 6  are respectively written into the six pixels intersecting with the scanning line  112  selected at the current time, by the corresponding TFTs  116 . Subsequently, when the sampling signal S 2  has become the H level, the image signals VID 1  to VID 6  are respectively sampled onto the next six data lines  114  on this occasion, and these image signals VID 1  to VID 6  are respectively written into the six pixels intersecting with the scanning line  112  selected at that time, by the corresponding TFTs  116 .  
     [0072] Similarly to the above, when the sampling signals S 3 , S 4  . . . , and Sn have become the H level in sequence, the image signals VID 1  to VID 6  are respectively sampled onto the six data lines  114  belonging to each of the sampling signals, and these image signals VID 1  to VID 6  are respectively written into the six pixels intersecting with the scanning line  112  selected at that time. Thereafter, the next scanning line  112  is selected, the sampling signals S 1  to Sn are sequentially outputted again, and similar writing is iteratively executed.  
     [0073] In the sampling periods based on the H levels of the enable signals ENB 1 , ENB 2 , noises are superposed on the image signals of the respective data lines. Especially, the influences of high frequency noises ascribable to the clocks CLX, CLX inv  and the enable signals ENB 1 , ENB 2  which rise and fall in units of the plurality of pixels in the horizontal direction appear as line blurs in the vertical direction and incur the drastic degradation of an image quality.  
     [0074] In this exemplary embodiment, however, the start timing and end timing of each sampling period based on the H level of the enable signal ENB 1  or ENB 2  are set to be sufficiently distant from the rise and fall timings of the clocks CLX, CLX inv . Thus, the high frequency noises ascribable to the clocks CLX, CLX inv  and the enable signals ENB  1 , ENB 2  are large in periods other than the sampling periods and are comparatively small in the sampling periods as shown in FIG. 5. The high frequency noise ascribable to the clocks CLX, CLX inv  and the high frequency noise ascribable to the enable signal ENB 1  or ENB 2  have sufficient distant generation timings, and noise of large level resulting from the addition of both the noises does not develop, so that the level of noise to be mixed into the image signal is comparatively small.  
     [0075] In this manner, in the settings of this exemplary embodiment, the rises and falls of the clocks CLX, CLX inv  are not generated in the H level periods of the enable signals ENB 1 , ENB 2  for setting the sampling periods, and the rises and falls of the enable signals ENB 1 , ENB 2  and those of the clocks CLX, CLX inv  are generated at the sufficiently distant timings, whereby the levels of the high frequency noises to be mixed into the image signals which are fed to the data lines are reduced to prevent the vertical direction line blurs from being displayed on a screen and to enhance a screen quality.  
     [0076] The first exemplary embodiment is described above assuming the horizontal scanning direction to be the rightward (R) direction. To the contrary, in a case where the horizontal scanning direction is the leftward (L) direction, the construction of each latch circuit  1430  in the R-direction transfer mode is bilaterally reversed. In this case, therefore, it is only different that the sampling signals are outputted in the sequence of Sn, S(n−1) . . . , S 2  and S 1 , and hence, the operation shall be omitted from description. Also in a case where the vertical scanning period is in the up direction, the operation is similar.  
     [0077] In the above description, the sampling circuit  150  is so constructed that the image signals VID 1  to VID 6  converted into the six loops are simultaneously sampled and fed to the six data lines  114  forming one group, and that the image signals VID 1  to VID 6  are sequentially applied to the respective data line groups. However, the number of converted loops and the number of data lines to which the image signals are simultaneously applied (that is, the number of data lines constituting one group) are not restricted to “6”. By way of example, if the response rate of each switch  151  in the sampling circuit  150  is sufficiently high, a construction may well be adopted in which the image signals are serially transmitted to a single signal line without being deserialized, so as to be sequentially sampled onto the respective data lines  114 . It is also allowed to adopt a construction in which the number of converted loops and the number of data lines to which the image signals are simultaneously applied are set at, for example, “3”, “12” or “24”, and 3-loop conversion, 12-loop conversion or 24-loop conversion, for example, is performed for the data lines numbering, for example, 3, 12 or 24, whereby the image signals fed in parallel are simultaneously fed. As the number of converted loops and the number of data lines to which the image signals are simultaneously applied, any multiple of “3” is favorable to simplify controls, circuits, etc., in relation to the fact that a color image signal is composed of signals based on three primary colors.  
     [0078] In the exemplary embodiment described above, the switching elements of the pixels have been explained as 3-terminal elements represented by the TFTs, but they may well be constructed of 2-terminal elements, such as diodes. However, in case of employing the 2-terminal elements as the switching elements of the pixels, it is necessary to form the scanning lines  112  on one substrate and the data lines  114  on the other substrate, and to form the 2-terminal elements between either the scanning lines  112  or the data lines  114  and the pixel electrodes  118 . In this case, each pixel is constituted by the pixel electrode  118  to which the 2-terminal element is connected, the signal line (either the data line  114  or the scanning line  112 ) which is formed on the counter substrate, and the liquid crystal which is held between the pixel electrode and the signal line.  
     [0079] The above exemplary embodiment is described as to the example in which one enable signal ENB 1  or ENB 2  is generated for one clock CLX or CLX inv . Further, it is possible to adopt a method in which a plurality of enable signals ENB 1 , ENB 2 , . . . are generated for one clock CLX or CLX inv  so as to feed image signals to a plurality of data lines in time division within one clock CLK period. FIG. 6 is a timing chart showing a clock CLK and enable signals ENB 1  to ENB 4  in the case where image signals are fed to four data lines in time division within one clock CLK period.  
     [0080] As shown in FIG. 6, the enable signals ENB 1 , ENB 2  are activated in the H level period of the clock CLK, and the enable signals ENB 3 , ENB 4  are activated in the L level period of the clock CLK. Accordingly, by using the enable signals ENB 1  to ENB 4 , the image signals corresponding to the four data lines can be sampled in time division within one cycle of the clock CLK so as to be fed to the four corresponding data lines.  
     [0081] Also in FIG. 6, neither the rise nor fall of the clock CLK is generated in the H level periods of the enable signals ENB 1  to ENB 4  to set sampling periods. Moreover, the rises and falls of the enable signals ENB 1  to ENB 4  and those of the clock CLK are generated at sufficiently distant timings.  
     [0082] Thus, also in this case, the levels of high frequency noises to be mixed into the image signals which are fed to the data lines can be reduced as shown in FIG. 6, thereby to reduce or prevent vertical direction line blurs from being displayed on a screen and to enhance a screen quality.  
     [0083] Incidentally, although the example adopting the liquid crystal as the electro-optical substance has been described in the above exemplary embodiment, the present invention is also applicable to a display device which employs electro luminescent elements or the likes so as to present a display on the basis of the electro-optical effect thereof. That is, the present invention is applicable to any electro-optical device, which has a construction similar to that of the foregoing liquid crystal device.  
     [0084] Cases are described below where the liquid crystal device described above is applied to each of various exemplary electronic equipment.  
     [0085] &lt;#1: Projector&gt; 
     [0086] A projector is described below which employs the liquid crystal panel as a light valve. FIG. 7 is a plan view showing the construction of the projector. As shown in FIG. 7, a lamp unit  1102  which includes a white light source, such as halogen lamp, is disposed inside the projector  1100 . Projection light emitted from the lamp unit  1102  is decomposed into three primary colors RGB by three mirrors  1106  and two dichroic mirrors  1108  which are arranged inside, and the light components R, G and B are respectively guided to the liquid crystal panels  100 R,  100 G and  100 B which serve as the light valves corresponding to the primary colors.  
     [0087] The light of the color B has an optical path which is longer as compared with those of the lights of the other colors R and G, and hence, in order to reduce or prevent the loss thereof, it is guided through a relay lens system  1121  which includes an entrance lens  1122 , a relay lens  1123 , and an exit lens  1124 .  
     [0088] The liquid crystal panels  100 R,  100 B and  100 G have constructions each of which is equivalent to that of the liquid crystal panel  100  described above, and they are respectively driven by primary color signals R, B, G which are fed from image signal processor circuits (not shown). Subsequently, the lights modulated by these liquid crystal panels are entered into a dichroic prism  1112  from three directions. In the dichroic prism  1112 , the lights of the colors R and B are refracted at 90 degrees, whereas the light of the color G proceeds rectilinearly. Accordingly, the images of the respective colors are composed, with the result that a color image is projected on a screen  1120  through a projection lens assembly  1114 .  
     [0089] When focused on the display images based on the respective liquid crystal panels  100 R,  100 B and  100 G, the display image based on the liquid crystal panel  100 G needs to be bilaterally inverted with respect to the display images based on the liquid crystal panels  100 R and  100 B. Therefore, horizontal scanning directions are in the relationship of reverse directions to each other between in the liquid crystal panel  100 G and in each of the liquid crystal panels  100 R,  100 B. Since the lights corresponding to the respective primary colors R, B and G are entered into the liquid crystal panels  100 R,  100 B and  100 G by the dichroic mirrors  1108 , color filters need not be disposed.  
     [0090] &lt;#2: Mobile Type Computer&gt; 
     [0091] An example is described below in which the liquid crystal panel is applied to a personal computer of a mobile type. FIG. 8 is a perspective view showing the construction of this personal computer. Referring to FIG. 8, the computer  1200  is constructed of the body portion  1204  including a keyboard  1202 , and a liquid-crystal display unit  1206 . This liquid-crystal display unit  1206  is constructed by adding a backlighting unit onto the rear side of the liquid crystal panel  100  discussed above.  
     [0092] &lt;#3: Portable Telephone&gt; 
     [0093] An example is described below in which the liquid crystal panel is applied to a portable telephone. FIG. 9 is a perspective view showing the construction of this portable telephone. Referring to FIG. 9, the portable telephone  1300  includes the liquid crystal panel  100  together with a plurality of operating buttons  1302  and an earpiece  1304  as well as a mouthpiece  1306 . Also the liquid crystal panel  100  is furnished with a backlighting unit on its rear side as may be needed.  
     [0094] Apart from the electronic equipment described with reference to FIGS.  7  to  9 , other types of electronic equipment include: a liquid crystal television set, a video tape recorder of view finder type or monitor direct-view type, a car navigation system, a pager, an electronic notebook, a desktop calculator, a word processor, a workstation, a video telephone, a POS terminal, an equipment including a touch panel, etc., for example.  
     [0095] The liquid crystal devices and further the electro-optical devices in the respective exemplary embodiments are applicable to these and other various electronic equipment.  
     [0096] As described above, according to the present invention, the logical status of a clock signal CLX or the inverted signal CLX inv  thereof is prevented from changing in an active enable signal period and a period vicinal thereto, thereby to bring forth the advantage that the level of noise to be mixed into an image signal can be lowered to reduce or suppress a vertical line blur.