Patent Publication Number: US-10330701-B2

Title: Test probe head for full wafer testing

Description:
CROSS REFERENCE TO RELATED APPLICATION 
     The present invention is a continuation in part (CIP) of: of U.S. Pat. No. 9,070,586, “METHOD OF FORMING SURFACE PROTRUSIONS ON AN ARTICLE AND THE ARTICLE WITH THE PROTRUSIONS ATTACHED” filed Feb. 22, 2014, and issued Jun. 30, 2015; U.S. patent application Ser. No. 14/516,963, “PLANARITY-TOLERANT REWORKABLE INTERCONNECT WITH INTEGRATED TESTING” filed Oct. 17, 2014; and of U.S. patent application Ser. No. 14/708,198, “METHOD OF FORMING SURFACE PROTRUSIONS ON AN ARTICLE AND THE ARTICLE WITH THE PROTRUSIONS ATTACHED” filed May 9, 2015, all to Bing Dang et al., all assigned to the assignee of the present invention and incorporated herein by reference. 
    
    
     BACKGROUND 
     Field of the Invention 
     The present invention is related to semiconductor device manufacturing and testing, and more particularly to a test probe head for full wafer testing multiple integrated circuit (IC) chips on semiconductor wafers. 
     Background Description 
     Typical semiconductor integrated circuit (IC) chips have layers stacked such that layer features overlay one another to form individual devices and connect devices together. ICs are mass produced by forming an array of chips on a thin semiconductor wafer. Each array location is known as a die. A typical, state of the art wafer may be as large as a dinner plate or larger, e.g., 12 inches (300 millimeters or 300 mm), with projections for 18 inch (450 mm) wafers in the near future. Larger wafers allow for more die per wafer for a given die size. At the same time increased logic complexity requires a higher input/output (I/O) count. 
     Each die may harbor a multilayered structure, such as an IC chip or a structure for test or alignment. The surface layer of each completed chip or die is typically populated by probe-able off-chip pads for connecting to chip power and input/output (I/O) signals. Packing more function on each die typically means providing more and more I/O signals for each die, on one (a top) surface, or for a three dimensional (3D) chip structure, both (top and bottom) surfaces. Each die has at least one surface pad for each I/O signal and a number of power (supply and ground) connection pads. Increasing I/O signal and supply pad count for a given die size requires a tighter I/O pad pitch for dense I/O pad arrays, and correspondingly, a tighter test probe pitch. A typical state of the art IC wafer, for example, die may be populated by several thousand connection pads on very tight a pitch less than 50 microns (&lt;50 μm). 
     Testing these tightly packed pads with or without solder balls requires very fine, delicate, tightly-packed test probes. Historically, what are known as cobra probes were used to probe down to 150 μm. Probing tightly-packed pads at 50 μm and below requires very precise probe tip geometry control and scalability. Achieving necessary probe tip precision for probing ultra-fine pitch pads has proven very difficult, and therefore, expensive. Moreover, in addition to increasing test time, repetitively shifting from one die to the next during manufacturing test, tends to degrade probe quality for these very fine, delicate, tightly-packed test probes. 
     Previously, multisite testing was unavailable for wafers populated by logic complex chips. Large probe heads, especially wafer level probe heads, could be used for testing low pin count memory chips, where it may be relatively easy to make contact to multiple memory dies simultaneously. However, these large probe head test cards were very expensive to build and to maintain. Moreover, these large probe heads have been limited to low pin count applications, which made the probes unattractive for high input/output (I/O) count logic chips. The poor precision of these traditional probes has made high pin count probe heads unsuitable, especially when considering the level of probe force that may be required to contact all of chip pads for chips under test. 
     Thus, there is a need for low cost multi-chip test probes for probing those ultra-fine pitch pads and bumps on wafers with state of the art IC chips, and in addition for probing those ultra-fine pitch pads and bumps on state of the art logic chips in a single probing. 
     SUMMARY 
     A feature of the invention is a multi-chip test probe for wafer level probing multi-chip locations in a single probing; 
     Another feature of the invention is an inexpensive multi-chip test probe for wafer level probing all chip locations in at least a quadrant of a wafer in a single probing; 
     Yet another feature of the invention is an inexpensive multi-chip test probe for wafer level probing all chip locations on a wafer in a single probing. 
     The present invention relates to a test probe head for probe testing multiple chips on a wafer in a single probing. A probe head substrate includes an array of probe tip attach pads on one surface. The array includes a subarray for each probe head chip test site. Probe tips attached to each probe tip attach pad have an across the head tip height variation less than one micrometer or micron (1 μm). The subarray probe tips are on a pitch ranging from one micron to one millimeter (1 μm-1 mm), and preferably, at or less than fifty microns (50 μm). The test probe head may be capable of test probing all chips in a quadrant and even up to all chips on a single wafer in a single probing. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The foregoing and other objects, aspects and advantages will be better understood from the following detailed description of a preferred embodiment of the invention with reference to the drawings, in which: 
         FIGS. 1A-G  show a cross-sectional and plan view example of forming surface protrusions or probe head tips in a large body for a wafer level test probe according to a preferred embodiment of the present invention; 
         FIG. 2  shows an example of a suitable semiconductor structure including a probe head layer for mounting an array of inverted probe tips; 
         FIG. 3  shows an example of the probe head layer with solder bumps  50  for joining to an interposer substrate or handle wafer; 
         FIG. 4  shows an example of the probe head layer after removing the carrier substrate and adhesion layer to expose the surface pads; 
         FIG. 5  shows an example of probe tips, still attached to the template substrate, attached to the surface pads on the probe head layer; 
         FIG. 6  shows an example of the template substrate being forced off of the probe head layer with the probe tips remaining firmly attached; 
         FIG. 7  shows a cross sectional example of completed testing structure for multi-site, or even wafer-level, testing; 
         FIG. 8  shows an example of a multi-chip test arrangement using a completed testing structure or probe head. 
     
    
    
     DETAILED DESCRIPTION 
     Turning now to the drawings and, more particularly,  FIGS. 1A-G  show a cross-sectional and plan view example  100  of forming surface protrusions or probe head tips in a large body  10  for a wafer level test probe, according to a preferred embodiment of the present invention. A preferred wafer level test probe may be used for functional testing multiple logic chips or devices under test (DUTs) on a large wafer area, e.g., wafer quadrant or even a whole wafer, at once in parallel in the time frame of a single functional test. 
     While the probe tips may be formed for a preferred test probe using any suitable transferrable tip formation process, as described herein, the tips and test probes are formed substantially as described in U.S. Pat. No. 9,070,586, “METHOD OF FORMING SURFACE PROTRUSIONS ON AN ARTICLE AND THE ARTICLE WITH THE PROTRUSIONS ATTACHED”, filed Feb. 22, 2014, and issued Jun. 30, 2015; in U.S. patent application Ser. No. 14/516,963, “PLANARITY-TOLERANT REWORKABLE INTERCONNECT WITH INTEGRATED TESTING” (herein Reworkable Interconnect), filed Oct. 17, 2014; and in U.S. patent application Ser. No. 14/708,198, “METHOD OF FORMING SURFACE PROTRUSIONS ON AN ARTICLE AND THE ARTICLE WITH THE PROTRUSIONS ATTACHED” (herein Surface Protrusions II), filed May 9, 2015, all to Bing Dang et al., and assigned to the assignee of the present invention. 
     A preferred multi-chip probe head has application to simultaneously testing multiple state of the art electronics chips, such as the Internet of Things (IoT) device and wearable device chips, manufactured on ultra-thin wafers. These thin wafers are characterized by large quantities (hundreds to thousands or more) of dies with small, tightly packed signal and power supply pads. Thus, for such a wafer even a single quadrant may include hundreds, thousands or more chip pads, e.g., 700,000 pads, for functional test. A preferred a test probe assembly has equally tightly packed probes with high co-planarity such that all the probes contact all test points for all of the multiple DUTs even with low probe force. Thus, the preferred multi-chip test probe structure (e.g., probes, probe head and connecting interposer(s)) lends itself to high pin count applications, up to and including, for full wafer level functional testing. 
     So formation begins in  FIG. 1A , by forming a mask  12  on a preferred large body or template wafer  10  that defines pits  14  at protrusion locations in  FIG. 1B . Preferably the etched template wafer  10 , which may be reusable, is a silicon with prismic, conical, cylindrical or pyramidal pits  14 . In this example, the pits  14  have an inverted pyramid shape with a square base and equilateral triangle shaped sides. Preferably also, the pits  14  are 1-25 μm deep, and most preferably 8 μm deep, with a surface diagonal/diameter 1-50 μm, most preferably 14 μm. 
     The pits  14  may be opened using any well-known semiconductor pattern and etch process, e.g., such as is used for trench formation in deep or shallow trench isolation (STI). Although any suitable wet or dry etch may be used, preferably, an anisotropic wet etch using Tetramethylammonium hydroxide (TMAH or TMAOH), etches the pyramidal pits  14  in the surface of silicon wafer  10 . Further, the pits  14  are scalable down to any size and any pitch, depending upon the particular pattern and etch technology selected. 
     In  FIG. 1C , after removing the mask pattern  12 , a low adhesion surface or seed layer  16  covers the pitted wafer  10 , coating each probe pit  18  to provide a non-planar surface. Preferably, the low adhesion seed layer  16  is a multi-layer (not shown) metal layer. In a particular example, the layers may include a base layer, e.g., titanium, formed directly on the template wafer  100  to ensure good adhesion to the silicon substrate  10 . A highly conductive layer, e.g., copper (Cu), silver (Ag) or gold (Au), formed on base layer ensures uniform current distribution, to maintain current stability during electroplating. A surface layer of seed material, e.g., Ti, is formed on highly conductive layer. Native oxide (also not shown) forms on the Ti surface to ensure sufficiently low adhesion to the Ti surface layer and to allow subsequently separating the electroplated material from the low adhesion seed layer  16  with relatively low force. 
     The coated pits  18  provide a non-planar surface that, during plating, causes local current crowding in each pit  18  to facilitate nucleation in the pit  18  without risking current stability. The surface non-linearity or other surface roughness, pits in this example, also facilitates plating nucleation, maintains adherence of subsequently plated metal to the template wafer during plating, and with sufficiently low adhesion to release the plated material with relatively low force. Other suitable seed materials may include, for example, stainless steel and chromium (Cr). Alternately, the low adhesion seed layer  16  may be a single metal layer, that layer sufficiently adheres to the silicon substrate  10  and provides sufficiently uniform plating current distribution. 
     In  FIG. 1D , a sacrificial mask pattern  22  is formed on the low adhesion seed layer  16  around the probe pits  14 , such that only selected pit  18  surface areas remain exposed for electroplating. Electroplating first forms a capping material layer  20  on exposed portions of low adhesion seed layer  16  to form inverted metal protrusions or bumps in the respective capped pits  24 . Preferably, a capping material layer forms a hard tip cap  20  for each probe tip, electroplated to the low adhesion seed layer  16 . The hard caps  20  cover the low adhesion seed layer  16 , and completely line the pits  24 . Preferably, the capping material is nickel (Ni), cobalt (Co), iron (Fe), suitable refractory metal or an alloy thereof, electroplated to a thickness of 1-30 μm, preferably 5 μm. The patterned sacrificial layer  22  also defines protrusion locations or bases that extend above each capped pit  24 . 
     In  FIG. 1E , a conductive plug  30 , e.g., copper, is plated to the hard caps  20 , such that the plated copper plug  30  has a minimum thickness of 1-100 μm, preferably 10 μm. Next, a base layer  32 , preferably nickel, is electroplated to the conductive plug  30 , and attach material  34 , preferably, lead-free solder, such as a tin/silver (Sn/Ag) solder, is electroplated to the base layer  32 . In this example, the base layer  32  is 0.5-3 μm, preferably 2 μm, thick; and the attach material  34  is 1-100 μm, preferably 10 μm, thick. Also in this example, the inverted metal protrusions  42  completely fill each pit. 
     Removing the patterned sacrificial layer  22  in a typical wet strip, rinse, and dry, exposes the inverted probe tips  42  in  FIG. 1F . Even though adhesion is low, the low adhesion seed layer  16  still has sufficient adhesion to hold the features (inverted probe tips  42 ) in place when the sacrificial layer  22  is stripped. 
       FIG. 1G  shows a plan view example of a wafer probe array  44  of inverted probe tips  42  formed on the silicon template wafer  100  as described in FIGS.  1 A-F. The subarray probe tips are on a pitch ranging from one micron to one millimeter (1 μm-1 mm). In this example, the mounted probe tips  42  may be on a pitch at, or less than, fifty microns (&lt;50 μm). It should be noted that although shown here as a uniform array  44  of probe tips  42 , this is for example only. The array may have blank locations, for example, at chip corners and between die locations. Between die, for example, the blanks divide the array  44  into subarrays, one (1) for each chip. Thus, the typical array  44  may be customized for the particular chips/wafer to be tested. Alternately, a common uniform array  44  may be attached to a suitable custom structure that accepts probes for the particular chips/wafer to be tested with the unused tips  42  remaining behind on the template wafer  100  when it is removed. With the probe array  44  attached to a suitable semiconductor structure and the template removed, the assembly provides a probe head for a multi-chip, or even up to a full wafer level, test probe for functionally testing logic chips prior to dice and mounting. In particular, such a wafer level test probe provides for testing wafers with a large number of dies with tightly spaced pads and a high degree of parallelism, testing multiple die simultaneously in parallel. 
       FIG. 2  shows an example of a suitable semiconductor structure  200  for mounting an array of inverted probe tips, e.g.,  42  in wafer probe array  44  of  FIG. 1G . An example of forming a suitable semiconductor structure  200  is described in Reworkable Interconnect. In this example, the semiconductor structure  200  includes a substrate or probe head layer  50  that may include a functional 2.5D or 3D layer. Preferably, the probe head layer  50  includes active test circuitry for testing and monitoring IC chips during multi-chip or multi-site testing. Also, in one embodiment, the probe head layer  50  may include a 3D silicon or glass die containing interconnect structures  52  or pass-through vias. The probe head layer  50  may have a thickness ranging from approximately 10 μm to approximately 1,000 μm. The interconnect structures  52  may include, for example, through-silicon vias (TSVs), through-glass vias (TGVs). The probe head layer  50  may include a surface pad  53  that allows connecting the probe head layer  50  to additional substrates or semiconductor structures with active test circuitry, as also described in Reworkable Interconnect. 
     The probe head layer  50  may be attached to a carrier substrate  54 , e.g., a silicon or glass wafer, by an adhesion layer  56 . The adhesion layer  56  may include, for example, a suitable adhesive material. The carrier substrate  54  may serve to transfer or move the probe head layer  50  for additional semiconductor processes including bonding to another semiconductor structure or substrate. The probe head layer  50  may further include solder bumps  58  formed on one surface of the probe head layer  50  using a typical, Integrated Circuit (IC) chip bumping technique, well known to those skilled in the art. 
     After forming solder bumps  58 , as shown in the example of  FIG. 3 , the probe head layer  50  may be joined to an interposer substrate  60  at the solder bumps  58 , the carrier substrate  54  as a handle wafer. The interposer substrate  60  may be of a material including, for example, ceramic, organic, glass, or silicon with one or more redistribution and/or logic layers. The probe head layer  50  may be bonded or joined to the interposer substrate  60  by reflowing the solder bumps  58 . Optionally, a non-conductive underfill layer  59  may be applied to fill between the probe head layer  50  and the interposer substrate  60 , for improved stack reliability and mechanical properties. 
     Next, the carrier substrate  54  and the adhesion layer  56  are removed from the probe head layer  50  to expose the surface pads  53 , as shown in  FIG. 4 . Again it should be noted that the surface pads  53  are customized for the particular chips/wafer to be tested and located substantially corresponding to the array  44  of probe tips  42  of  FIG. 1G . The surface pad  53  array has blank locations, for example, at chip corners and between die locations. After releasing the carrier substrate  54  and the adhesion layer  56 , the probe head layer  50  remains joined to the interposer substrate  60  with the surface opposite the bumps  58  exposed. 
     As shown in  FIG. 5 , probe tips  62  attached to a template substrate  66 , e.g., array  44  of  FIG. 1G , are fixed to the structure  200 , attached to the surface pads  53  on the probe head layer  50 . Preferably, the probe tips  62  are attached to the surface pads  53 , e.g., using a reflow or thermo-compression to bond the probe tips  62  IC to pads  53  on the patterned wafer  66 . The IC pads  53  also may be layered pads that include a base layer, preferably copper, on the patterned wafer  66 , an interface layer, preferably nickel, on base layer, and anti-oxidation layer, preferably gold, on the interface layer, as described in Surface Protrusions I and II. Finally, heating the wafer  50  assembly reflows the attach material  34  to permanently connect the probe tips  62 . 
     Once the probe tips  62  are attached to the IC pads  53 , as shown in  FIG. 6 , the template substrate  66  is separated from the wafer  50 . Using very little force the template substrate  66  may be pulled or pried from the probe head layer  300 , separating the template substrate  66  from the semiconductor structure, while the probe tips  62  remain attached and in place. 
     Optionally, the template substrate  66  may be refreshed after removal, first by brushing off any residual process monitoring or measuring protrusions that may remain, e.g., in the Kerf regions. A quick etchant-rinse, e.g., a diluted hydrofluoric acid dip and deionized water rinse, strips oxide from the surface of the low adhesion seed layer. Fresh native oxide regrows in air. After refreshing, the template substrate  66  may be reused to repopulate probe tips  62  for another probe head. Because native oxide is a mono layer the template substrate  66  may be refreshed and reused a number of times, depending on the metal (Ti) thickness, etchant chosen, and process control. 
       FIG. 7  shows a cross sectional example of completed testing structure  300 , e.g., for multi-site or even full wafer-level testing. Although shown in this cross sectional example as including  6  probe tips  62  in one direction, this is for example only, Since a typical, larger state of the art logic IC chip, e.g. a CPU, may include a thousand or more I/O pads in a n by m (e.g., 30 by 40 or larger) array. Thus for simultaneously testing several of these chips in a wafer segment, the probe might include hundreds or more probe tips  62  in each direction. Similarly, for simultaneously testing several smaller devices, where the pad array is smaller, the probe might still include hundreds of probe tips  62  in each direction with more chips being tested simultaneously. 
     For full wafer-level testing of a 300 mm wafer with minimum pitch pads on a 50 μm or closer pitch, some rows might include upwards of 6000 such probe tips  62  and include twelve (12) million or more bumps. Further, although the average IoT application might have only a few hundred of bumps in a very small or tiny footprint, many more of these tiny chips are packed on the same size wafer, e.g., numbering in hundreds to thousands. So, even for these tiny IoT chips, hundreds of pads per die for hundreds to thousands of die results in a high pad count. Further, testing each die individually, it very likely would take more time moving the probe from die to die (raising the probe, moving it to the next die, dropping the probe on the die and testing), than the time spent testing. Thus, testing as many of these small IoT devices in parallel, in a single probing saves substantial test time. 
       FIG. 8  shows an example of a multi-chip test arrangement using a completed testing structure  300  or probe head. The probe head  300  is mounted inverted on a test fixture (not shown) for testing multiple devices under test, i.e., sites or chips, on a target substrate or wafer  71  for functional testing of all chips in a single probing. The target substrate  71  may be a full silicon wafer with each DUT including multiple probe-able solder bumps  72  on chip pads  73 . Again, it should be noted that the probe head  300  may include test logic, and further, the probe head layer  50  may be the terminal layer in a 3D probe head such as described in Reworkable Interconnect. 
     Thus advantageously, a preferred probe head exhibits a high level of probe uniformity with across the head tip height variation less than one micrometer (1 μm). Further, probe tips are precisely located with a positional variation also less than one micrometer (1 μm). This tip positional precision and height planarity minimizes the force required to probe multiple chips simultaneously, requiring a probe force of only 100-400 milligrams (100-400 mG) per tip. Moreover, even at this low contact force, each probe tip has a current carrying capability above one amp (1 A) with low contact resistance of forty milliohms (40 mΩ) or less to minimize supply and signal loss (&lt;40 mV). Probe inductance, and corresponding signal distortion, is minimal and minimizes the signal path between test circuitry and the DUT pads, in some cases (e.g., when active test circuitry is integrated into the probe layer) the length of the probe tip. These preferred probes and probe tips may be further scalable, e.g., using micro-bump and micro-pillar technologies. 
     While the invention has been described in terms of preferred embodiments, those skilled in the art will recognize that the invention can be practiced with modification within the spirit and scope of the appended claims. It is intended that all such variations and modifications fall within the scope of the appended claims. Examples and drawings are, accordingly, to be regarded as illustrative rather than restrictive.