Patent Publication Number: US-2022238406-A1

Title: Package structure and method of manufacturing the same

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application is a continuation application of and claims the priority benefit of a prior application Ser. No. 16/714,801, filed on Dec. 16, 2019, now allowed. The prior application Ser. No. 16/714,801 is a continuation application of and claims the priority benefit of U.S. application Ser. No. 15/706,783, filed on Sep. 18, 2017, now allowed. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification. 
    
    
     BACKGROUND 
     The semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of various electronic components (i.e., transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration density has come from continuous reductions in minimum feature size, which allows more of the smaller components to be integrated into a given area. These smaller electronic components also require smaller packages that utilize less area than previous packages. Some smaller types of packages for semiconductor components include quad flat packages (QFPs), pin grid array (PGA) packages, ball grid array (BGA) packages, and so on. 
     Currently, integrated fan-out packages are becoming increasingly popular for their compactness. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1A  to  FIG. 1L  are schematic cross-sectional views illustrating a method of forming a package structure according to a first embodiment of the disclosure. 
         FIG. 2A  to  FIG. 2C  are schematic cross-sectional views illustrating a method of forming a package structure according to a second embodiment of the disclosure. 
         FIG. 3A  to  FIG. 3F  are schematic cross-sectional views illustrating a method of forming a package structure according to some embodiments of the disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a second feature over or on a first feature in the description that follows may include embodiments in which the second and first features are formed in direct contact, and may also include embodiments in which additional features may be formed between the second and first features, such that the second and first features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. 
     Further, spatially relative terms, such as “beneath”, “below”, “lower”, “on”, “above”, “upper” and the like, may be used herein for ease of description to describe one element or feature&#39;s relationship to another element(s) or feature(s) as illustrated in the FIG.s. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the FIG.s. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. 
     Other features and processes may also be included. For example, testing structures may be included to aid in the verification testing of the 3D packaging or 3DIC devices. The testing structures may include, for example, test pads formed in a redistribution layer or on a substrate that allows the testing of the 3D packaging or 3DIC, the use of probes and/or probe cards, and the like. The verification testing may be performed on intermediate structures as well as the final structure. Additionally, the structures and methods disclosed herein may be used in conjunction with testing methodologies that incorporate intermediate verification of known good dies to increase the yield and decrease costs. 
       FIGS. 1A to 1L  are schematic cross-sectional views illustrating a method of forming a package structure according to a first embodiment of the disclosure. 
     Referring to  FIG. 1A , a carrier  10  is provided. The carrier  10  may be a glass carrier, a ceramic carrier, or the like. A release layer  11  is formed on the carrier  10  by, for example, a spin coating method. In some embodiments, the release layer  11  may be formed of a polymer-based material such as an Ultra-Violet (UV) glue, a Light-to-Heat Conversion (LTHC) material, an epoxy-based thermal-release material, or the like. The release layer  11  is decomposable under the heat of light to thereby release the carrier  10  from the overlying structures that will be formed in subsequent steps. 
     A dielectric layer  12  (or referred as a first dielectric layer) is formed on the release layer  11 . The dielectric layer  12  may be a single layer structure or a multi-layer structure. In some embodiments, the material of the dielectric layer  12  includes an inorganic dielectric material, an organic dielectric material, or a combination thereof. The inorganic dielectric material includes a nitride such as silicon nitride, an oxide such as silicon oxide, an oxynitride such as silicon oxynitride, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), or the like, or a combination thereof. The organic dielectric material includes a polymer, which may be a photosensitive material such as polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), ajinomoto buildup gilm (ABF), solder resist film (SR), or the like, or a combination thereof. The dielectric layer  12  is formed by a suitable fabrication technique such as spin-coating, lamination, deposition, or the like. 
     Still referring to  FIG. 1A , a seed layer  13  is formed on the dielectric layer  12 , for example, through physical vapor deposition (PVD). In some embodiments, physical vapor deposition includes sputtering deposition, vapor deposition, or any other suitable method. The seed layer  13  may be a metal seed layer including copper, aluminum, titanium, alloys thereof, or multi-layers thereof. In some embodiments, the seed layer  13  includes a first metal layer such as a titanium layer (not shown) and a second metal layer such as a copper layer (not shown) over the first metal layer. In some embodiments, such the seed layer  13  is a conformal layer. That is, the seed layer  13  has a substantially equal thickness extending along the region on which the seed layer  13  is formed. 
     Thereafter, a patterned mask layer  14  is formed on the seed layer  13 . The patterned mask layer  14  has a plurality of openings  16 , exposing a portion of the seed layer  13 . The patterned mask layer  14  is, for instance, a photoresist. The patterned mask layer  14  is formed by, for instance, forming a photoresist layer on the seed layer  13  at first, and then performing exposure and development processes on the photoresist layer. 
     Still referring to  FIG. 1A , a conductive layer  15  is formed on the seed layer  13  exposed by the openings  16  through, for example, electroplating, or electroless plating. The conductive layer  15  is formed of, for instance, copper or other suitable metals. 
     Referring to  FIG. 1A  and  FIG. 1B , the patterned mask layer  14  is then removed by a dry strip, a wet strip or a combination thereof, for example, such that the seed layer  13  not covered by the conductive layer  15  is exposed. In some embodiments, the seed layer  13  not covered by the conductive layer  15  is then removed with the conductive layer  15  as a mask, so as to form a seed layer  13   a . In some embodiments, the seed layer  13   a  may be used as a barrier layer or a glue layer of the conductive layer  15 . The removal method includes an etching process, such as a dry etching, a wet etching or a combination thereof. 
     Referring to  FIG. 1B , the seed layer  13   a  and the conductive layer  15  form a redistribution line (RDL) layer  17 . In some embodiments, the RDL layer  17  includes a plurality of conductive traces extending on the dielectric layer  12  connected to each other. In some other embodiments, the RDL layer  17  has a multi-layer structure and includes a plurality of vias and a plurality of conductive traces connected to each other. In some embodiments, the RDL layer  17  includes RDLs  17   a  and RDLs  17   b . Specifically, the RDLs  17   a  are located at the two sides of the RDLs  17   b . The number of the RDLs  17   a  and RDLs  17   b  may be adjusted according to the design of products. A plurality of gaps  18  and  18 ′ are existed between the RDLs  17   a  and  17   b . In some embodiments, the gap  18  is existed between the adjacent two RDLs  17   a , and the width W 0  of the gap  18  ranges from 40 μm to 500 μm. The gap  18 ′ is existed between the adjacent two RDLs  17   b  or between the adjacent RDL  17   a  and RDL  17   b . In some embodiments, the width of the gap  18 ′ is larger than the width W 0  of the gap  18 . 
     Still referring to  FIG. 1B , a dielectric layer  19  (or referred as a second dielectric layer) is formed on the dielectric layer  12  and the RDL layer  17 , and fills in the gap  18  and  18 ′, so as to cover the dielectric layer  12 , the sidewalls  47  of the RDL layer  17  and the top surface  24  of the RDL layer  17 . The dielectric layer  19  may be a single layer structure or a multi-layer structure. In some embodiments, the material of the dielectric layer  19  includes an inorganic dielectric material, an organic dielectric material, or a combination thereof. The inorganic dielectric material includes a nitride such as silicon nitride, an oxide such as silicon oxide, an oxynitride such as silicon oxynitride, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), or the like, or a combination thereof. The organic dielectric material includes a polymer, which may be a photosensitive material such as polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), ajinomoto build-up film (ABF), solder resist film (SR), or the like, or a combination thereof. The material of the dielectric layer  19  and the material of the dielectric layer  12  may be the same or different. The dielectric layer  19  is formed by a suitable fabrication technique such as spin-coating, lamination, deposition, or the like. In some embodiments, the RDL layer  17  and the dielectric layer  19  form a RDL structure  21 . 
     Referring to  FIG. 1B  and  FIG. 1C , thereafter, a portion of the second dielectric layer  19  over the gap  18  and the dielectric layer  19  in the gap  18  are removed by, for example, exposure and development processes, laser drilling process, photolithography and etching processes, or a combination thereof, such that a plurality of recesses  20  are formed. The recess  20  penetrates through the RDL structure  21 , and exposes a portion of the top surfaces  24  and sidewalls  47  of the two adjacent RDLs  17   a , and a portion of the top surface of the dielectric layer  12 . 
     In some embodiments, the recess  20  includes a first recess  20   a  and a second recess  20   b  spatially communicated with each other. The first recess  20   a  is located over the second recess  20   b , that is, the first recess  20   a  and the second recess  20   b  are overlapped. The width of the first recess  20   a  is larger than the width of the second recess  20   b . The first recess  20   a  is located over the two adjacent RDLs  17   a  to expose a portion of the top surfaces  24  of the RDLs  17   a . The second recess  20   b  is located between the two adjacent RDLs  17   a  to expose the sidewalls  47  of the RDLs  17   a  and the top surface of the dielectric layer  12 . 
     In some embodiments, the recess  20  has a stepped shape, the cross-section shape of the recess  20  has a T-shape or a funnel-like shape, but the present disclosure is not limited thereto. The sidewall of the first recess  20   a  (that is the sidewall of the dielectric layer  19 ) and the top surface  19   b  of the dielectric layer  19  form a corner a. The angle of the corner a ranges from 100° to 140°. 
     Referring to  FIG. 1C  to  FIG. 1D , a seed layer  22  is then formed on the RDL structure  21  and on the dielectric layer  12 . The material and the forming method of the seed layer  22  is substantially the same as those of the seed layer  13  shown in  FIG. 1A , which will not be described again. The seed layer  22  covers the top surface  19   b  of the dielectric layer  19  and covers the bottom surface and sidewalls of the recesses  20 . In some embodiments, the seed layer  22  is in contact with a portion of the top surfaces  24  and sidewalls  47  of the RDLs  17   a  and a portion of the top surface of the dielectric layer  12 . The bottom surface of the seed layer  22  is substantially level with the bottom surface of the seed layer  13   a  of the RDLs  17   a.    
     Referring to  FIG. 1D , a patterned mask layer  23  is formed on the seed layer  22 . The patterned mask layer  23  has a plurality of openings  25 . The opening  25  exposes the seed layer  22  located in the recesses  20  and the seed layer  22  covering the corner a of the dielectric layer  19 . 
     Still referring to  FIG. 1D , a plurality of conductive posts  26  are formed on the seed layer  22  exposed by the openings  25  of the patterned mask  23 . The conductive post  26  is disposed in the recess  20  and protrudes from the top surface  19   b  of the dielectric layer  19 . The conductive post  26  may be a copper post or any other suitable metal post. The term “copper posts” refers to copper protrusions, copper through vias, thick copper pads, and/or copper-containing protrusions. Throughout the description, the term “copper” is intended to include substantially pure elemental copper, copper containing unavoidable impurities, and copper alloys containing minor amounts of elements such as tantalum, indium, tin, zinc, manganese, chromium, titanium, germanium, strontium, platinum, magnesium, aluminum, or zirconium, etc. The conductive post  26  is formed by electroplating, for example. 
     Referring to  FIG. 1D  and  FIG. 1E , the patterned mask layer  23  is then removed, such that the seed layer  22  not covered by the conductive posts  26  is exposed. The seed layer  22  not covered by the conductive posts  26  is then removed with the conductive posts  26  as a mask, so as to form a seed layer  22   a . In some embodiments, the seed layer  22   a  may be used as a barrier layer or a glue layer of the conductive post  26 . The removal method includes an etching process, such as a day etching, a wet etching, or a combination thereof. 
     Referring to  FIG. 1E , the seed layer  22   a  and the overlying conductive posts  26  form a plurality of through integrated fan-out vias (TIVs)  27 . The number of the TIVs  27  is not limited to that is shown in  FIG. 1E , which may be adjusted according to the requirement. The TIV  27  is disposed in the recess  20 , and protrudes from the top surface  19   b  of the dielectric layer  19 . The TIV  27  penetrates through the RDL structure  21  and contacts with the dielectric layer  12 . In other words, the TIV  27  is engaged with the RDL structure  21 . Further, the TIV  27  is in electrical contact with a portion of the top surfaces  24  and the sidewalls  47  of the two adjacent RDLs  17   a.    
     Still referring to  FIG. 1E , in some embodiments, an end of the TIV  27  (that is, the bottom of the TIV  27 ) has a stepped shape and is engaged with the RDL structure  21 . Specifically, the seed layer  22   a  and an end of the conductive post  26  have stepped shapes. A portion of sidewalls and bottoms of the conductive post  26  is covered by the seed layer  22   a . Another end of the TIV  27 , that is, another end of the conductive post  26  is flat. The TIV  27  includes, from bottom to top, a first embedded part  27   a , a second embedded part  27   b  and a protruding part  27   c  which are in electrical contact with each other. The first embedded part  27   a  and the second embedded part  27   b  are located in the recess  20 . The protruding part  27   c  is located over the RDL structure  21  to protrude from the top surface  19   b  of the dielectric layer  19 . 
     Specifically, the first embedded part  27   a  is located between the two adjacent RDLs  17   a  and in electrical contact with the sidewalls  47  of the RDLs  17   a . The top surface of the first embedded part  27   a  is substantially level with the top surface  24  of the RDLs  17   a , the bottom surface of the first embedded part  27   a  is substantially level with the bottom surface of the RDLs  17   a  and in contact with the dielectric layer  12 . The second embedded part  27   b  is located on the first embedded part  27   a  and on the two adjacent RDLs  17   a  to be in electrical contact with a portion of the top surfaces  24  of the two adjacent RDLs  17   a . In some embodiments, the cross-section shape of the first embedded part  27   a  is square or rectangle. The cross-section shape of the second embedded part  27   b  is inverted trapezoid or rectangle. The overall cross-section shape of the first embedded part  27   a  and the second embedded part  27   b  has a T-shaped or a funnel-like shape. In some embodiments, the bottom width W 2  of the second embedded part  27   b  is equal to or larger than the top width W 1  of the first embedded part  27   a , such that the bottom of the TIV has a stepped shape. In some exemplary embodiments, the bottom width W 2  of the second embedded part  27   b  ranges from 50 μm to 510 μm, the top width W 1  of the first embedded part  37   a  substantially equals to the width W 0  of the gap  18  (shown in  FIG. 1B ) and ranges from 40 μm to 500 μm. 
     The protruding part  27   c  is located on the second embedded part  27   b . In some embodiments, the protruding part  27   c  covers the top surface of the second embedded part  27   b  and a portion of the top surface  19   b  of the dielectric layer  19 , that is to say, the corner a of the dielectric layer  19  is covered by the TIV  27 , but the disclosure is not limited thereto. In some other embodiments, the protruding part  27   c  only covers the top surface of the second embedded part  27   b  and does not cover the top surface  19   b  of the dielectric layer  19  (not shown). In some embodiments, the cross-section shape of the protruding part  27   c  is rectangle or trapezoid, but the disclosure is not limited thereto. 
     Referring to  FIG. 1F , a die  34  is attached to the dielectric layer  19  though an adhesive film  28  such as a die attach film (DAF), and disposed between the TIVs  27 . The die  34  includes a substrate  29 , a plurality of pads  30 , a passivation layer  31 , a plurality of connectors  32  and a passivation layer  33 . The pads  30  may be a part of an interconnection structure (not shown) and electrically connected to the integrated circuit devices (not shown) formed on the substrate  29 . The passivation layer  31  is formed over the substrate  29  and covers a portion of the pads  30 . A portion of the pads  30  is exposed by the passivation layer  31  and serves as an external connection of the die  34 . The connectors  32  is formed on and electrically connected to the pads  30  not covered by the passivation layer  31 . The connectors  32  include solder bumps, gold bumps, copper bumps, copper posts, or the like. The passivation layer  33  is formed over the passivation layer  31  and aside the connectors  32  to cover the sidewalls of the connectors  32 . The passivation layer  31  and  33  respectively includes an insulating material such as silicon oxide, silicon nitride, polymer, or a combination thereof. In some embodiments, the top surface of the passivation layer  33  is substantially level with the top surface of the connectors  32 . 
     In some embodiments, the die  34  is one of a plurality of dies cut apart from a wafer, for example. The die  34  may be an application-specific integrated circuit (ASIC) chip, an analog chip, a sensor chip, a wireless and radio frequency chip, a voltage regulator chip or a memory chips. The number of the die  34  shown in  FIG. 1F  is merely for illustration, and the disclosure is not limited thereto. In some embodiments, two or more dies  34  may be mounted onto the dielectric layer  19 , and the two or more dies  34  may be the same types of dies or the different types of dies. In some other embodiments, a wafer (not shown) comprising a plurality of dies  34  arranged in an array is mounted onto the dielectric layer  19 , and the die  34  is surrounded by the TIVs  27 . 
     An encapsulant  35  is then formed over the carrier  10  to encapsulate the sidewalls of the die  34  and the protruding parts  27   c  of the TIVs  27 . In some embodiments, the encapsulant  35  includes a molding compound, a molding underfill, a resin such as epoxy, a combination thereof, or the like. In some other embodiments, the encapsulant  35  includes a photo-sensitive material such as PBO, polyimide, BCB, a combination thereof, or the like, which may be easily patterned by exposure and development processes. In alternative embodiments, the encapsulant  35  includes nitride such as silicon nitride, oxide such as silicon oxide, PSG, BSG, BPSG, a combination thereof, or the like. The encapsulant  35  is formed by forming an encapsulant material layer over the carrier  10  by a suitable fabrication technique such as spin-coating, lamination, deposition, or similar processes. The encapsulant material layer encapsulates the top surfaces and sidewalls of the die  34  and the protruding part  27   c  of the TIVs  27 . Thereafter, a grinding or polishing process is performed to remove a portion of the encapsulant material layer, such that the top surfaces of the connectors  32  and the TIVs  27  are exposed. In some embodiments, the top surfaces of the connectors  32 , the TIVs  27  and the encapsulant  35  are substantially coplanar. 
     Referring to  FIG. 1G , a first dielectric layer  36  is formed on the die  34  and the TIVs  27  and the encapsulant  35 . The first dielectric layer  36  may be a single layer structure or a multi-layer structure. The first dielectric layer  36  has a plurality of openings  37 , exposing a portion of the TIVs  27  and a portion of the connectors  32  of the die  34 . The material of the first dielectric layer  36  is similar to that of the dielectric layer  12  and the dielectric layer  19 . The first dielectric layer  36  is formed by forming a first dielectric material layer (not shown) at first to cover the die  34 , the encapsulant  35  and the TIVs  27 . Thereafter, a portion of the dielectric material layer on the TIVs  27  and on the connectors  32  is removed by, for example, exposure and development processes, a laser drilling process, photolithography and etching processes, or a combination thereof, such that the first dielectric layer  36  having the openings  37  is formed. 
     Still referring to  FIG. 1G , a seed layer  38  is formed on the first dielectric layer  36 , and fills into the openings  37  to cover the bottom surface and sidewalls of the openings  37 . The seed layer  38  is in electrical contact with the TIVs  27  and the connectors  32  at the bottom of the openings  37 . The material and the forming method of the seed layer  38  are similar to those of the seed layer  13  shown in  FIG. 1A . 
     Referring to  FIG. 1H , a patterned mask layer  39  is formed on the seed layer  38 . The patterned mask layer  39  has a plurality of openings  40 , exposing the seed layer  38  in the openings  37  and a portion of the seed layer  38  on the first dielectric layer  36 . A conductive layer  41  is then formed on the seed layer  38  exposed by the openings  40 . The conductive layer  41  fills into the openings  37  and protrudes from the top surface of the first dielectric layer  36 , and covers a portion of the top surface of the first dielectric layer  36 . 
     Referring to  FIG. 1H  and  FIG. 1I , the patterned mask layer  39  is then removed, such that the seed layer  38  not covered by the conductive layer  41  is exposed. The seed layer  38  not covered by the conductive layer  41  is then removed with the conductive layer  41  as a mask, so as to form a seed layer  38   a . The removal method includes an etching process, such as a dry etching, a wet etching, or a combination thereof. 
     Referring to  FIG. 1I , the seed layer  38   a  and the conductive layer  41  form a RDL layer  42 . In some embodiments, the RDL layer  42  is in contact with and electrically connected to the TIVs  27  and the connectors  32  of the die  34 . In some embodiments, the RDL layer  42  includes a plurality of vias  42   a  and a plurality of conductive traces  42   b . The vias  42   a  penetrate through the first dielectric layer  36  to contact with the TIVs  27  and the connectors  32 . The conductive traces  42   b  extend on the first dielectric layer  36  and are connected to the vias  42   a . Thereafter, a second dielectric layer  43  is formed on the RDL layer  42 , so as to cover the top surface and sidewalls of the RDL layer  42 . The material and the forming method of the second dielectric layer  43  are similar to those of the dielectric layer  12 , which will not be described again. 
     The first dielectric layer  36 , the RDL layer  42  and the second dielectric layer  43  form a RDL structure  44 . The number of the layers of the RDL layer  42  of the RDL structure  44  is not limited to that is shown in  FIG. 1I , and may be adjusted according to the requirements. The RDL structure  44  may have one or more layers of RDL layer  42 . In some embodiment in which the RDL structure  44  has more than one RDL layers  42 , the RDL structure  44  includes a plurality of stacked dielectric layers  36  and  43  and RDL layers  42  (not shown). The method of forming the multilayer structure of the RDL structure  44  is, for instance, after the second dielectric layer  43  is formed, repeating the processes from  FIG. 1G  to  FIG. 1I  described above to form multi-layers of RDL layers  42 . 
     Still referring to  FIG. 1I , the RDL structure  44  is disposed at the front side of the die  34  (the side close to the connectors  32 , that is, close to an active surface of the die  34 ), the RDL structure  21  is disposed at the back side (the opposite side of the front side) of the die  34 . Therefore, in some embodiments, the RDL structure  21  is referred as the back side RDL structure, and the RDL structure  44  is referred as the front side RDL structure. 
     Referring to  FIG. 1I  and  FIG. 1J , the structure formed in  FIG. 1I  is turned over, the release layer  11  is decomposed under the heat of light, and the carrier  10  is then released from the overlying structure thereof. 
     Still referring to  FIG. 1J  and  FIG. 1K , a portion of the dielectric layer  12 , a portion of the seed layer  13   a , and the seed layer  22   a  at the top of the TIVs  27  are removed to form a plurality of openings  45   a . The opening  45   a  penetrates through the dielectric layer  12  of the RDL structure  21  and the seed layer  13   a  of the RDLs  17   a . Further, portions of the dielectric layer  12  on the RDLs  17   b  and the underlying seed layer  13   a  are removed to form a plurality of openings  45   b . The opening  45   b  penetrates through the dielectric layer  12  and the seed layer  13   a  of the RDLs  17   b . The removal method includes a laser drilling process, for example. A seed layer  13   b  of the RDL layer  17  and a seed layer  22   b  of the TIV  27  are remained. A portion of sidewalls of the conductive post  26  is covered by the seed layer  22   b . The conductive post  26  is separated from the dielectric layer  19  by the seed layer  22   b  therebetween. The bottom of the opening  45   a  exposes the seed layer  22   b  and the conductive post  26  of the TIV  27  and a portion of the top surface of the conductive layer  15  of the RDLs  17   a , and the sidewalls of the opening  45   a  expose the seed layer  13   b  of the RDLs  17   a  and the dielectric layer  12 . The width of the opening  45   a  may be adjusted, as long as at least a portion of the conductive post  26  is exposed by the bottom of the opening  45   a . The bottom of the opening  45   b  exposes the conductive layer  15  of the RDL  17   b , and the sidewalls of the opening  45   b  expose the dielectric layer  12  and the seed layer  13   b  of the RDL  17   b . In some embodiments in which the seed layer  13  (shown in  FIG. 1A ) and the seed layer  22  (shown in  FIG. 1D ) are formed with a same thickness, the top surface of the conductive post  26  and the top surface of the seed layer  22   b  are coplanar with the top surface (the surface in contact with the seed layer  13   b ) of the conductive layer  15 , but the disclosure is not limited thereto. 
     Referring to  FIG. 1K  and  FIG. 1L , a plurality of connectors  46   a  and  46   b  are respectively formed on TIVs  27  and on the RDLs  17   b . The connectors  46   a  and  46   b  may be referred as conductive terminals. In some embodiments, the connectors  46   a  and  46   b  may cover a portion of a top surface of the dielectric layer  12 . In some other embodiments, the connectors  46   a  and  46   b  may not cover the top surface of the dielectric layer  12 . The connectors  46   a  and  46   b  may be simultaneously formed or successively formed. The connector  46   a  fills into the opening  45   a  and penetrates through the dielectric layer  12  and the seed layer  13   b  of the RDLs  17   a . The bottom of the connector  46   a  is in electrical contact with the conductive post  26  and the seed layer  22   b  of the TIV  27 , and the conductive layer  15  of the RDLs  17   a . The sidewalls of the connector  46   a  are in contact with the seed layer  13   b  of the RDLs  17   a  and the dielectric layer  12 . The connector  46   b  fills into the opening  45   b  so that the bottom of the connector  46   b  is in electrical contact with the conductive layer  15  of the RDL  17   b , and the sidewalls of the connector  46   b  are in contact with the seed layer  13   b  of the RDL  17   b  and the dielectric layer  12 . The material of the connector  46   a  and  46   b  include copper, aluminum, lead-free alloys (e.g., gold, tin, silver, aluminum, or copper alloys) or lead alloys (e.g., lead-tin alloys). In some embodiments, the connectors  46   a  and  46   b  are respectively formed by a ball mounting process. In some other embodiments, a printing step may be performed to print a solder paste in the openings  45   a  and  45   b , followed by reflowing the solder paste to form the connectors  46   a  and  46   b . Alternatively, connectors  46   a  and  46   b  are formed by dropping solder balls in openings  45   a  and  45   b  and then a reflow process is performed. In some embodiments, an under-ball metallurgy (UBM) layer (not shown) is further formed before the connectors  46   a  and  46   b  are formed. The UBM layer fills into the openings  45   a  and  45   b , and covers the bottom and sidewalls of the openings  45   a  and  45   b  and a portion of the dielectric layer  12 . 
     Still referring to  FIG. 1L , a package structure  50   a  is thus completed. The package structure  50   a  includes the die  34 , the RDL structure  21 , the TIVs  27 , the RDL structure  44  and the connectors  46   a  and  46   b . The TIVs  27  penetrates through the RDL structure  21  and are in electrical contact with the connectors  46   a . Thereafter, the package structure  50   a  may be connected to other package components such as a printed circuit board (PCB), a flex PCB, or the like through the connectors  46   a  and  46   b . In some embodiments in which a wafer comprising a plurality of dies  34  is formed over the carrier  10  in the forgoing process, before connecting to other package components, the package structure (not shown) may be singulated by a die-saw process to form a plurality of identical package structures  50   a  as illustrated in  FIG. 1L . 
       FIGS. 2A to 2C  are schematic cross-sectional views illustrating a method of forming a package structure according to a second embodiment of the disclosure. The second embodiment differs from the first embodiment in that connectors  63  are further formed to connect to a RDL structure  144  over the die  34 , and a package-on-package (POP) device is further formed. The details are described as below. 
     Referring to  FIG. 1I  and  FIG. 2A , in some embodiments, the RDL structure  144  includes a plurality of RDL layers  42 / 61  and dielectric layers  36 / 43 / 60  stacked alternately, and the RDL layer  42  is referred as a first RDL layer  42 . In some embodiments, after the first dielectric layer  36 , the first RDL layer  42 , and the second dielectric layer  43  are formed as shown in  FIG. 1I , processes similar to those of  FIG. 1G  to  FIG. 1I  are performed, so as to form a second RDL layer  61  and a third dielectric layer  60 . The second RDL layer  61  penetrates through the second dielectric layer  43  to connect to the first RDL layer  42 . The material, forming method and structural characteristics of the second RDL layer  61  and the third dielectric layer  60  are similar to those of the first RDL layer  42  and the second dielectric layer  43 , which will not be described again. 
     Thereafter, a conductive layer  62  penetrating though the third dielectric layer  60  is formed to connect to the second RDL layer  61 . In some embodiments, the conductive layer  62  is referred as under-ball metallurgy (UBM). The material of the conductive layer  62  includes a metal or a metal alloy. The conductive layer  62  is, for example, copper, tin, an alloy thereof, or a combination thereof. The conductive layer  62  is formed by, for instance, physical vapor deposition or electroplating. 
     Still referring to  FIG. 2A , a plurality of connectors (also referred to as conductive balls)  63  are placed on the conductive layer  62 . The material of the connector  63  includes copper, aluminum, lead-free alloys (e.g., gold, tin, silver, aluminum, or copper alloys) or lead alloys (e.g., lead-tin alloys). In some embodiments, the connectors  63  are placed on the conductive layer  62  by a ball mounting process. The connectors  63  are electrically connected to the connectors  32  through the conductive layer  62  and the RDL structure  144 . 
     Referring to  FIG. 2A  and  FIG. 2B , processes similar to those of  FIGS. 1J to 1L  are then performed, the structure formed in  FIG. 2A  is turned over, the release layer  11  is decomposed, and the carrier  10  is then released from the overlying structure thereof. 
     Referring to  FIG. 2B , a plurality of openings  45   a  and  45   b  are formed. Thereafter, a plurality of connectors  46   a  penetrating through the dielectric layer  12  and the seed layer  13   b  of the RDLs  17   a  are formed to be in electrical contact with the TIVs  27  and the RDLs  17   a . A plurality of connectors  46   b  penetrating through the dielectric layer  12  is formed to be in electrical contact with the RDLs  17   b . The connectors  46   a  and  46   b  may be simultaneously formed or successively formed. The forming method and the structural characteristics of the openings  45   a  and  45   b  and the connectors  46   a  and  46   b  are substantially the same as those in the first embodiment, which will not be described again. 
     The package structure  50   b  is thus completed. In some embodiments, the package structure  50   b  may further be electrically coupled to a package structure  70  to form a POP device, but the disclosure is not limited thereto. 
     Referring to  FIG. 2C , in some embodiments, the package structure  70  has a substrate  71 , and a die  72  is mounted on one surface (e.g. top surface) of the substrate  71 . Bonding wires  73  are used to provide electrical connections between the die  72  and pads  74  (such as bonding pads) on the same top surface of the substrate  71 . TIVs (not shown) may be used to provide electrical connections between the pads  74  and pads  75  (such as bonding pads) on an opposing surface (e.g. bottom surface) of the substrate  71 . The connectors  46   a  and  46   b  connect the pads  75  and electrically connect to the package structure  50   b . An encapsulant  77  is formed over the components to protect the components from the environment and external contaminants. 
     Thereafter, an under-fill layer  48  is formed to fill the space between the package structure  50   b  and the package structure  70  and to surround the connectors  46   a  and  46   b . In some embodiments, the under-fill layer  48  includes a molding compound such as epoxy, and is formed using dispensing, injecting, and/or spraying techniques. 
       FIG. 3A  to  FIG. 3F  are schematic cross-sectional views illustrating a method of forming a package structure according to some embodiments of the disclosure. 
     In the forgoing embodiments, as shown in  FIG. 1L  and  FIG. 2B , the TIV  27  penetrates through the RDL structure  21  to be in electrical contact with the connector  46   a , and the TIV  27  and the connector  46   a  are also in electric contact with the conductive layer  15  and the seed layer  13   b  of the RDLs  17   a . Referring to  FIG. 3A  to  FIG. 3F , in some embodiments, there may be some TIVs  127  that is not in contact with an RDL  117   a , but separated from the RDLs  117   a  by the dielectric layer  19 , and the connector  46   a  is not in contact with the RDLs  117   a . For the sake of brevity,  FIGS. 3A to 3E  only show the RDLs  117   a , a TIV  127 , the encapusulant  35  and a connector  146   a.    
     Referring to  FIG. 1B ,  FIG. 3A  and  FIG. 3B , the RDL structure  21  further includes RDLs  117   a , and a gap  118  is existed between the adjacent two RDLs  117   a . A portion of the dielectric layer  19  within the gap  118  is removed, so as to form a recess  120  penetrating through the dielectric layer  19 . The recess  120  is located between the adjacent two RDLs  117   a . In some embodiments, the bottom of the recess  120  exposes a portion of the top surface of the dielectric layer  12 . As the dielectric layer  19  in the gap  118  is partially removed, such that the RDLs  117   a  is not exposed in the recess  120 . In some embodiments, the cross-section shape of the recess  120  is inverted trapezoid, square, rectangle, or any other shape, as long as the surfaces of the RDLs  117   a  are covered by the dielectric layer  19 . Thereafter, a seed layer  122  is formed on the dielectric layer  19 . 
     Referring to  FIGS. 3B to 3D , processes similar to those of  FIGS. 1D to 1E  are performed to form a TIV  127 . The TIV  127  including a conductive post  126  and a seed layer  122   a . The material and the forming method are substantially the same as those of the TIV  27 , which will not be described again. The TIV  127  penetrates through the RDL structure  21  and is in contact with the dielectric layer  12 . The TIV  127  differs from the TIV  27  of the foregoing embodiments in that the TIV  127  is not in electrical contact with the RDLs  117   a , but separated from the RDLs  117   a  by the dielectric layer  19 . In some embodiments, the TIV  127  includes an embedded part  127   a  and a protruding part  127   b . The embedded part  127   a  is located in the recess  120 , and the top surface of the embedded part  127   a  is substantially level with the top surface  19   b  of the dielectric layer  19 . In some embodiments, the cross-section shape of the embedded part  127   a  is inverted trapezoid, square or rectangle, but the disclosure is not limited thereto. In some embodiments in which the embedded part  127   a  has an inverted trapezoid cross-section shape, the top width W 12  of the embedded part  127   a  is less than the width W 11  of the gap  118  as shown in  FIG. 3A . The protruding part  127   b  is located on the embedded part  127   a  and protrudes from the top surface  19   b  of the dielectric layer  19 . The other structural characteristics of the protruding part  127   b  are similar to those of the TIV  27  as shown in  FIG. 1E . 
     Referring to  FIG. 1J ,  FIG. 3D  and  FIG. 3E , after the carrier  10  is released, a portion of the dielectric layer  12 , and the seed layer  122   a  covering the top surface of the conductive post  126  are removed, so as to form an opening  145   a  penetrating through the dielectric layer  12 , and a seed layer  122   b  of the TIV  127  is remained. A portion of sidewalls of the embedded part  127   a  is covered by the seed layer  122   b , and the top surface of the embedded part  127   a  is exposed by the opening  145   a . The width of the opening  145   a  may be adjusted, as long as at least a portion of the conductive post  126  is exposed by the bottom of the opening  145   a.    
     The conductive post  126  is separated from the dielectric layer  19  by the seed layer  122   b  therebetween. In some embodiments, the cross-section shape of the seed layer  122   b  is L shaped or line-shaped, but the disclosure is not limited thereto. 
     In some embodiments, the cross-section shape of the opening  145   a  is inverted trapezoid or rectangle, for example, but the disclosure is not limited thereto. The bottom of the opening  145   a  exposes the conductive post  126  and the seed layer  122   b  of the TIV  127 . In some embodiments, the top surface of the conductive post  126  and the top surface of the seed layer  122   b  are substantially coplanar with the conductive layer  15  of the RDLs  117   a . Referring to  FIG. 3F , a connector  146   a  is formed on the TIV  127 . The connector  146   a  may be referred as a conductive terminal. The connector  146   a  penetrates through the dielectric layer  12 , and the bottom of the connector  146   a  is in electrical contact with the conductive post  126  and the seed layer  122   b  of the TIV  127 . The connector  146   a  and the RDLs  117   a  are separated by the dielectric layer  19  therebetween. 
     In some embodiments of the present disclosure, the TIV is provided to penetrate through the RDL structure to be in contact with and electrically connected to the connector, thus the open issue between the TIV and the RDL structure that caused by the seed layer or barrier layer or glue layer is avoided. On the other hand, as the seed layer is partially removed, a portion of the seed layer is still disposed between the conductive post of the TIV and the dielectric layer, thus the delamination problem is also avoided. 
     In accordance with some embodiments of the disclosure, a package structure includes a die, a RDL structure, a TIV and a first connector is provided. The RDL structure is connected to the die and includes a plurality of RDLs. The TIV is aside the die and penetrates through the RDL structure. The first connector is in electrical contact with the TIV and electrically connected to the die. The TIV is in electrical contact with the RDLs of the RDL structure. 
     In accordance with alternative embodiments of the disclosure, a package structure includes a die, a RDL structure, a TIV and a connector is provided. The RDL structure is connected to the die. The TIV is aside the die and penetrates through the RDL structure. The connector is in electrical contact with the TIV and electrically connected to the die. 
     In accordance with some embodiments of the disclosure, a method of manufacturing a package structure is provided. The method is described as below. A RDL structure is formed on a first dielectric layer. A die is attached on the RDL structure. A TIV is formed aside the die and penetrating through the RDL structure. A connector is formed to be in electrical contact with the TIV. 
     The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the disclosure. Those skilled in the art should appreciate that they may readily use the disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the disclosure.