Patent Publication Number: US-6667072-B2

Title: Planarization of ceramic substrates using porous materials

Description:
BACKGROUND OF INVENTION 
     1. Field of Invention 
     This invention mainly provides a concept of using porous materials on ceramic substrate planarization. This planarized substrate can be utilized in the fields of electronic information communication, opto-electronics and display. 
     2. Description of the Prior Art 
     It is an important postulation for having a planar surface for the thin-film processes. The high cost is due to two main aspects. The first aspect is due to the high substrate-polishing cost based on either silicon wafer or glass manufacture factory. The second aspect is the high fabrication cost on the flattening technology as a key technology to produce metallized module IC. 
     At present, some common smoothing techniques include mechanical polishing, chemical mechanical polishing, chemical etching, high temperature reflow through borophosphosilicate, and spin coating. Thin film&#39;s roughness and adherence are often limited after surface treatment at which may additionally complicate the processing and increase the cost. The prior arts are shown as following: 
     
       
         
           
               
               
               
             
               
                   
               
               
                 Prior Art 
                 Focal technique 
                 Defect 
               
               
                   
               
             
            
               
                 US4944836: 
                 A method for VLSI 
                 The chemical reagent 
               
               
                 Chem-mech 
                 and ULSI (Ultra-Large 
                 used in CMP method 
               
               
                 polishing (CMP) 
                 Semiconductor 
                 is expensive and hard 
               
               
                 method for 
                 Integration) offer 
                 to be controlled during 
               
               
                 producing coplanar 
                 “global 
                 the process. 
               
               
                 metal/insulator films 
                 planarization”. 
                 And it is also lack of 
               
               
                 on a substrate 
                 The combination of 
                 terminate detecting 
               
               
                   
                 mechanism polishing 
                 system. 
               
               
                   
                 and chemical reagent 
                 Finally, a trace of 
               
               
                   
                 to flatten silicon 
                 contaminant may be 
               
               
                   
                 wafer. More than 
                 observed in polish 
               
               
                   
                 94% of rough surface 
                 process. 
               
               
                   
                 as consequence 
               
               
                   
                 can be planarized 
               
               
                   
                 by CMP method. 
               
               
                 Silicon Processing 
                 Surface of 
                 The spin on glass 
               
               
                 for the VLS: 
                 silicon wafer 
                 processing can 
               
               
                 Basics of Thin Films 
                 recovered by a liquid 
                 provide only local 
               
               
                   
                 solution via spin 
                 planarization. 
               
               
                   
                 coating method, after 
                 Disadvantage may be 
               
               
                   
                 heat treatment there- 
                 observed for example 
               
               
                   
                 fore a planar dielectric 
                 like the formation of 
               
               
                   
                 layer can be formed. 
                 particles, film crack, 
               
               
                   
                 A deep gap fill capa- 
                 delamination and 
               
               
                   
                 bility on such surface 
                 exhausted 
               
               
                   
                 can be obtained by 
                 out-gassing. 
               
               
                   
                 SOG method. 
               
               
                 Solid State Technology: 
                 A layer of low glass 
                 Both B 2 H 6  and PH 3   
               
               
                 Viscous Behavior of 
                 transition temperature 
                 are chemically toxic 
               
               
                 Phosphosilicate, 
                 materials BPSG 
                 and are employed in 
               
               
                 Borophosphosilicate 
                 deposition on a surface 
                 BPSG processing. 
               
               
                 and Germano- 
                 by CVD method. At 
                 This planarization can 
               
               
                 phosphosilicate 
                 high temperature 
                 be applied to the 
               
               
                 Glasses in VLSI 
                 reflow BPSG on the 
                 planarizing dielectric 
               
               
                 Processing. 
                 substrate and then 
                 barrier layer before 
               
               
                   
                 resulting surface 
                 metallization. After 
               
               
                   
                 planarization. 
                 the coverage of Al 
               
               
                   
                   
                 metal layer however 
               
               
                   
                   
                 BPSG reflowing 
               
               
                   
                   
                 process cannot be 
               
               
                   
                   
                 applied. 
               
               
                 Solid State 
                 Excess thick layer of 
                 Only a partial 
               
               
                 Technology: 
                 SiO 2  deposited. The 
                 planarization can be 
               
               
                 Chemical Etching 
                 application of 
                 obtained by chemical 
               
               
                   
                 anisotropic-etch 
                 etching method. It is 
               
               
                   
                 method can then etch 
                 not applicable. 
               
               
                   
                 back SiO 2  layer to 
               
               
                   
                 desired thickness. 
               
               
                   
               
            
           
         
       
     
     SUMMARY OF THE INVENTION 
     Conclusively, the main purpose of this invention can solve the above-mentioned defects (film crack, delamination, etc.). In order to overcome these problems, this invention provides a concept of using porous materials on ceramic substrate planarization, wherein the nanostructure layer provides the required surface smoothness upon the ceramic substrates and enhances the adhesion between substrate and subsequent thin-film layers. 
     This invention can tremendously reduce the production cost due to its simple production process. 
     In order to achieve the said objectives, the invention provides a method of using porous materials on ceramic substrate planarization. This invention sustains a surface flattening method by employing the participation of porous materials such as zeolites, zeolite-like, mesoporous and mesoporous composites. Meanwhile, this invention results in good affinity for the electrical and dielectric properties, for instance, thermal conductivity, electrical insulation, dielectric and other required properties for integrated components. Due to a good polarization obtained, this invention permits furthermore an intensive binding between thin films and electronic materials. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG.  1 : Schematic drawing of the architecture of the smoothing technology indicated in the invention description. 
     FIG.  2 : X-ray photograph of example 1. 
     FIG.  3 : SEM photograph of example 1. 
     FIG.  4 : Flatten result on the ceramic substrates surface. 
     FIG. 5 a : Adhesive test of example after deposition of an Al film having a thickness of 6.5 μm and patternization by photolithography. 
     FIG. 5 b : Optical picture of the flatten sample on which an Al film having a thickness of 6.5 μm has been deposited. 
     FIG. 6 a : A current-voltage relationship of the diode which made from the flatten sample (first example). 
     FIG. 6 b : RLCD integrated circuit made from the flatten sample(first example). 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     This invention mainly provides a method of using porous materials on ceramic substrate planarization. The concept of this invention includes at least a layer of ceramic substrate  30 , a buffer layer  20 , and nanostructured layer  10 . As shown in FIG. 1, it is a schematic drawing of the architecture of the smoothing technology indicated in the invention description. First this invention provides a ceramic substrate  30 , then a buffer layer  20  forms on the ceramic substrate  30  and a nanostructure layer  10  forms upon the buffer layer  20 . 
     The ceramic substrate  30  provides the structure stress and surface-mount capability. The buffer layer  20  provides the adhesion between the substrate layer  30  and nanostructured layer  10 . The buffer layer  20  can be chosen from one of or some of the following materials: glaze, glass, ceramic, mesoporous and mesoporous composites. The nanostructure layer  10  is formed by the self repetitively assembled mechanism in order to offer the required surface smoothness of the ceramic substrates for performing the thin-film process techniques, adhesion for metallization and electronic materials, thermal conductivity, electrical insulation, dielectric and other electric material required functions. The nanostructure layer  10  is chosen from one of or some of the following materials: zeolites, zeolite-like, mesoporous and mesoporous composites. Moreover, the buffer layer  20  and nanostructure layer  10  can be either the same layer or multilayer. 
     The concept of the this invention utilizes the nanostructure layer  10  to provide required thermal conductivity, electrical insulation, adhesion, dielectric and other electric material required functions for the substrate that comprises LTCC, chip-carrier, passive device, active device, light emitting device, optical passive device and optical active device and their complexes. 
     The properties and the advantages of this invention are shown in the following example, which can be one of applications. 
     FIRST EXAMPLE 
     Flatness Test 
     The formation of sample as represented in FIG. 2, where substrate  30  was aluminum oxide, buffer layer  20  was glaze, and nanostructure layer  10  was zeolite-like material. X-ray analysis of crystal structure is shown in FIG. 3, the peak signal informs the self-assembly zeolite-like structure. The SEM picture given in FIG. 4 shows the profile of Al 2 O 3  substrate of  30 , glaze buffer layer  20  and nanostructure zeolite-like layer  10 . The flatness measurement shown in FIG. 5 shows flatness in angstrom dimension. 
     SECOND EXAMPLE 
     Adhesion Test 
     As shown in FIG. 6 a , it is the adhesive test of example 1 after deposited 6.5 μm thickness layers of Al film and patternized by photolithography. FIG. 5 b  is the optical picture of flatten sample deposited 6.5 μm thickness layers of Al film for adhesion test. A 6.5 μm thickness layer of Al film deposited on flatten sample and patternized by photolithography, this picture indicates an excellent adhesion between substrate and Al layer. It is fully agreement to the α-step profiling measurement shown in FIG. 5 a.    
     THIRD EXAMPLE 
     Practicable Test 
     As shown in FIG. 6 a , it is the current-voltage relationship of the diode made from the flatten sample (first example), and in FIG. 6 b , it is the RLCD integrated circuit made from the flatten sample (first example). Hence, these are evident examples that proof this invention is practicable. 
     It should be apparent to those skilled in the art that the above description is only illustrative of specific embodiments and examples of the invention. The invention should therefore cover various modifications and variations made to the herein-described structure and operations of the invention, provided they fall within the scope of the invention as defined in the following appended claims.