Patent Publication Number: US-6709922-B2

Title: Method of manufacturing semiconductor integrated circuit device including nonvolatile semiconductor memory devices

Description:
Japanese Patent Application No. 2001-21931, filed on Jan. 30, 2001, is hereby incorporated by reference in its entirety. 
     BACKGROUND 
     1. Technical Field 
     The present invention relates to a method of manufacturing a semiconductor integrated circuit device including nonvolatile semiconductor memory devices. 
     2. Related Art 
     As one type of nonvolatile semiconductor memory device, a MONOS (Metal Oxide Nitride oxide Semiconductor) memory device is known. In the MONOS memory device, a gate insulating layer disposed between a channel and a gate is formed of a laminate consisting of two silicon oxide layers and a silicon nitride layer, and charges are trapped in the silicon nitride layer. 
     A device shown in FIG. 16 is known as such a MONOS nonvolatile semiconductor memory device (Y. Hayashi, et al., 2000  Symposium on VLSI Technology Digest of Technical Papers,  122-123). 
     In this MONOS memory cell  100 , a word gate  14  is formed on a semiconductor substrate  10  with a first gate insulating layer  12  interposed. A first control gate  20  and a second control gate  30  are disposed on either side of the word gate  14  in the shape of sidewalls. A second gate insulating layer  22  is present between the bottom of the first control gate  20  and the semiconductor substrate  10 . A side insulating layer  24  is present between the side of the first control gate  20  and the word gate  14 . A second gate insulating layer  32  is present between the bottom of the second control gate  30  and the semiconductor substrate  10 . A side insulating layer  34  is present between the side of the second control gate  30  and the word gate  14 . Impurity diffusion layers  16  and  18  forming a source region or a drain region are formed in the semiconductor substrate  10  in a region between the control gate  20  and the control gate  30  facing each other in adjacent memory cells. 
     As described above, one memory cell  100  includes two MONOS memory elements, one on each side of the word gate  14 . These MONOS memory elements can be controlled separately. Therefore, the memory cell  100  is capable of storing 2 bits of information. 
     This MONOS memory cell operates as follows. One of the control gates of the memory cell  100  is capable of selecting read or write operation separately by biasing the other control gate to an override voltage. 
     A write (program) operation is described below with reference to a case where electrons are injected into the second gate insulating layer (ONO film)  32  at the left in CG [i+1] in FIG.  16 . In this case, the bit line (impurity diffusion layer)  18  (D[i+1]) is biased to a drain voltage of 4 to 5 V. The control gate  30  (CG[i+1]) is biased to 5 to 7 V in order to cause hot electrons to be injected into the second gate insulating layer  32  at the left of the control gate  30  (CG[i+1]). A word line connected to the word gates  14  (Gw[i] and Gw[i+1]) is biased at a voltage slightly higher than the threshold value of the word gate in order to limit the program current to a specific value (10 μA or less). The control gate  20  (CG[i]) is biased to an override voltage. This override voltage enables a channel under the control gate  20  (CG[i]) to conduct irrespective of the memory state. A left side bit line  16  (D[i]) is biased to ground. Control gates and diffusion layers in unselected memory cells are grounded. 
     In an erase operation, stored charges (electrons) are erased by injection of hot holes. Hot holes can be generated by B—B tunneling at the surface of the bit diffusion layer  18 . At this time, the voltage Vcg of the control gate is biased to a negative voltage (−5 to −6 V) and the voltage of the bit diffusion layer is biased to 5 to 6 V. 
     In the above-cited reference, according to the MONOS memory cell, two separately controllable programming sites in a single memory cell can provide bit density of 3F 2 . 
     SUMMARY 
     According to one embodiment of the present invention, there is provided a method of manufacturing a semiconductor integrated circuit device including a memory cell array in which nonvolatile semiconductor memory devices are arranged in a matrix of a plurality of rows and columns, the method comprising the following steps (a) to (k): 
     (a) a step of forming an element isolation region on the surface of a semiconductor layer; 
     (b) a step of forming a first gate insulating layer and a laminate having a first conductive layer for a word gate disposed over the first gate insulating layer on the semiconductor layer, the laminate having a plurality of openings extending in a first direction; 
     (c) a step of forming second gate insulating layers on the semiconductor layer so as to be adjacent to both sides of the first gate insulating layer; 
     (d) a step of forming side insulating layers on both sides of the first conductive layer for the word gate; 
     (e) a step of forming a second conductive layer over the entire surface of a structure formed by the steps (a) to (d) so as to cover the structure; 
     (f) a step of forming a first mask layer on the second conductive layer at least in a region in which a common contact section is formed; 
     (g) a step of forming a control gate and a common contact section which comprises: 
     anisotropically etching the entire surface of the second conductive layer to form first and second control gates in the shape of sidewalls continuous in the first direction on either side of the side insulating layers, and to form a contact conductive layer at least in a region in which the common contact section is formed; and 
     forming the contact conductive layer continuously with a pair of the first and second control gates adjacent in a second direction which intersects the first direction; 
     (h) a step of doping the semiconductor layer located between the first and second control gates with impurities, and forming an impurity diffusion layer which forms a source region or a drain region; 
     (i) a step of forming an insulating layer which covers the first and second control gates; 
     (j) a step of forming a second mask layer in a region in which the common contact section is formed; and 
     (k) a step of patterning the first conductive layer for the word gate. 
     According to this method of manufacturing a semiconductor integrated circuit device, the common contact section can be formed together with the control gate in the shape of sidewall without increasing the number of steps. The size and shape of the common contact section can be specified by the first and second mask layers at the time of patterning, whereby a sufficient contact area can be secured. Therefore, an electrical connection with narrow control gates can be secured reliably through the common contact sections. 
     According to this a manufacturing method, a semiconductor integrated circuit device including a memory cell array, in which nonvolatile semiconductor memory devices are arranged in a matrix of a plurality of rows and columns, having the following structure can be obtained. 
     The nonvolatile semiconductor memory device comprises: 
     a word gate formed on a semiconductor layer with a first gate insulating layer interposed, 
     an impurity diffusion layer which forms either a source region or a drain region formed in the semiconductor layer, and 
     first and second control gates in the shape of sidewalls formed along either side of the word gate, wherein: 
     the first control gate is disposed on the semiconductor layer with a second gate insulating layer interposed and also on the word gate with a side insulating layer interposed, 
     the second control gate is disposed on the semiconductor layer with a second gate insulating layer interposed and also on the word gate with a side insulating layer interposed, 
     each of the first and second control gates is disposed continuously in a first direction, and 
     a pair of the first and second control gates adjacent in a second direction which intersects the first direction is connected to a common contact section. 
     The manufacture method of the present invention may have the following features. 
     (A) The second conductive layer for the control gate and the common contact section may be formed of a doped polysilicon layer. 
     (B) The second gate insulating layer may be formed by depositing a first silicon oxide layer, a silicon nitride layer, and a second silicon oxide layer one after another. The side insulating layer and the insulating layer in the common contact section may be formed during this step. 
     (C) The step (b) may comprise a step of forming a stopper layer for chemical mechanical polishing (CMP) on the first conductive layer for the word gate, and 
     in the step (i), the insulating layer which covers the first and second control gates may be provided by forming an insulating layer on the entire surface of the structure formed by the steps (a) to (h) and then removing the insulating layer by chemical mechanical polishing until the stopper layer is exposed. An insulating layer formed in this manner is hereinafter called a “buried insulating layer”. 
     (D) The stopper layer may be formed so that an upper surface thereof is located at a position higher than an upper end of the control gate. In this case, the side insulating layer may be formed so that an upper end thereof is located at the same level as an upper surface of the stopper layer. Therefore, the upper end of the side insulating layer is located at a position higher than the control gate with respect to the semiconductor layer. This prevents current leakage and short circuits between the control gates and interconnect layers for the word gates formed on the control gates with the buried insulating layers interposed. 
     (E) The common contact sections may be provided adjacent to an end of the impurity diffusion layer. The common contact sections may be provided alternately on one end and the other end of a plurality of the impurity diffusion layers. 
     (F) The memory cell array may be divided into a plurality of blocks. In this case, contact impurity diffusion layer may be formed in the semiconductor layer after the step (a), and the impurity diffusion layer in one of the blocks may be connected to the impurity diffusion layer in another one of the blocks adjacent to the one block in a first direction through the contact impurity diffusion layer. 
     (G) The first mask layer may be formed corresponding to a region in which the common contact section is formed in the step (f). 
     In the step (f), the first mask layer may be formed continuously so as to cover regions in which a plurality of the common contact sections arranged in the second direction are formed. In this case, in the step (g), a conductive layer may be continuously formed so as to include regions in which the common contact sections are formed, by the first mask layer. In the step (k), the contact conductive layer may be formed together with the word gate by patterning the conductive layer together with the first conductive layer. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a plan view schematically showing a layout of a semiconductor integrated circuit device according to an embodiment of the present invention. 
     FIG. 2 is a cross-sectional view schematically showing a section taken along the line A—A in FIG.  1 . 
     FIG. 3 is a cross-sectional view showing one step in a method of fabricating the semiconductor integrated circuit device shown in FIGS. 1 and 2. 
     FIG. 4 is a plan view showing the step in the method of fabricating the semiconductor integrated circuit device shown in FIG.  3 . 
     FIG. 5 is a cross-sectional view showing one step in the method of fabricating the semiconductor integrated circuit device shown in FIGS. 1 and 2. 
     FIG. 6 is a cross-sectional view showing one step in the method of fabricating the semiconductor integrated circuit device shown in FIGS. 1 and 2. 
     FIG. 7 is a plan view showing the step in the method of fabricating the semiconductor integrated circuit device shown in FIG.  6 . 
     FIG. 8 is a cross-sectional view showing one step in the method of fabricating the semiconductor integrated circuit device shown in FIGS. 1 and 2. 
     FIG. 9 is a cross-sectional view showing one step in the method of fabricating the semiconductor integrated circuit device shown in FIGS. 1 and 2. 
     FIG. 10 is a cross-sectional view showing one step in the method of fabricating the semiconductor integrated circuit device shown in FIGS. 1 and 2. 
     FIG. 11 is a cross-sectional view showing one step in the method of fabricating the semiconductor integrated circuit device shown in FIGS. 1 and 2. 
     FIG. 12 is a cross-sectional view showing one step in the method of fabricating the semiconductor integrated circuit device shown in FIGS. 1 and 2. 
     FIG. 13 is a cross-sectional view showing one step in the method of fabricating the semiconductor integrated circuit device shown in FIGS. 1 and 2. 
     FIG. 14 is a cross-sectional view showing one step in the method of fabricating the semiconductor integrated circuit device shown in FIGS. 1 and 2. 
     FIG. 15 is a plan view showing a modification of one step in the method of fabricating the semiconductor integrated circuit device according to the present invention. 
     FIG. 16 is a cross-sectional view showing a conventional MONOS memory cell. 
    
    
     DETAILED DESCRIPTION 
     1. Device Structure 
     FIG. 1 is a plan view schematically showing a layout of a semiconductor integrated circuit device including nonvolatile semiconductor memory devices obtained by the manufacturing method according to an embodiment of the present invention. FIG. 2 is a cross-sectional view schematically showing a section taken along the line A—A in FIG.  1 . 
     In this semiconductor integrated circuit device, the above-described conventional nonvolatile semiconductor memory devices (memory cells)  100  are arranged in a matrix with a plurality of rows and columns, thereby making up a memory cell array. 
     The layout of the semiconductor integrated circuit device is described below with reference to FIG.  1 . 
     FIG. 1 shows a first block B 1  and a second block B 2  adjacent thereto. The first block B 1  and the second block B 2  are isolated by an element isolation region  300  extending in the row direction (x direction). In each of the blocks B 1  and B 2 , a plurality of word lines  50  (WL) extending in the row direction (X direction, second direction) and a plurality of bit lines  60  (BL) extending in the column direction (Y direction, first direction) are provided. The word lines  50  are provided in contact with word gates  14 . Impurity diffusion layers  16  and  18  form the bit lines  60 . 
     Each of first and second control gates  20  and  30  is formed of a conductive layer  40  extending in the column direction, specifically, along the sides of the word gate  14 . In this embodiment, the conductive layer  40  which forms the first and second control gates  20  and  30  is formed so as to enclose each of the impurity diffusion layers  16  and  18 . One end of the first control gate  20  and one end of the second control gate  30  are connected and the other ends are connected to a common contact section  200 . Therefore, as shown in FIG. 1, the common contact sections  200  are staggered relative to each other. Also, the first and second control gates  20  and  30  have a function of a control gate for the memory cells and a function of interconnection which connects the control gates arranged in the column direction. 
     Each memory cell  100  includes the word gate  14 , the first control gate  20 , the second control gate  30 , the impurity diffusion layer  16  and the impurity diffusion layer  18 . The impurity diffusion layers  16  and  18  are formed outside the first and second control gates  20  and  30 . The adjacent memory cells  100  share the impurity diffusion layers  16  and  18 . 
     In the blocks B 1  and B 2  adjacent in the column direction, the impurity diffusion layers  16  are connected at the ends having no common contact section  200 , by a contact impurity diffusion layer  400  formed in the semiconductor substrate. A contact  250  to the bit line  60  is formed on the contact impurity diffusion layer  400 . Also, the impurity diffusion layers  18  which are adjacent in the column direction are connected by a contact impurity diffusion layer (not shown). Therefore, the contacts  250  are staggered relative to each other. 
     The cross-sectional structure of the semiconductor integrated circuit device is described below with reference to FIG.  2 . 
     The word gate  14  is formed on the main surface of a semiconductor substrate  10  with a first gate insulating layer  12  interposed. The impurity diffusion layers  16  and  18  are formed in the semiconductor substrate  10 . Each of impurity diffusion layers  16  and  18  functions as a source region or a drain region. The first and second control gates  20  and  30  are formed on either side of the word gate  14  with a side insulating layer  24  interposed. The control gates are the same shape as sidewall insulating spacers in conventional MOS transistor. In this embodiment of the present invention, the semiconductor substrate  10  has an N-type first well  10   a  and a P-type second well  10   b  formed in the first well  10   a . The first well  10   a  has a function of electrically isolating the second well  10   b  from other regions of the semiconductor substrate  10 . 
     The first control gate  20  is disposed on the second well  10   b  in the semiconductor substrate  10  with a second gate insulating layer  22  interposed, and disposed on one side of the word gate  14  with a side insulating layer  24  interposed. The second control gate  30  is disposed on the second well  10   b  in the semiconductor substrate  10  with the second gate insulating layer  22  interposed, and disposed on the other side of the word gate  14  with the side insulating layer  24  interposed. A first silicon oxide layer  22   a , a silicon nitride layer  22   b , and a second silicon oxide layer  22   c  make up the second gate insulating layer  22  and the side insulating layer  24 . The second gate insulating layer  22  functions as a charge storage region. The first silicon oxide layer  22   a  mainly functions as a tunnel film through which carriers (electrons, for example) pass. The silicon nitride layer  22   b  mainly functions as a charge storage layer in which the carriers are trapped. 
     The side insulating layers  24  formed on both sides of the word gate  14  have a function of electrically isolating the word gate  14  from the control gates  20  and  30 . There are no specific limitations to the structure of the side insulating layer  24  insofar as the side insulating layer  24  has such a function. In this embodiment, the side insulating layer  24  and the second gate insulating layer  22  are formed in the same step and have the same layer structure. The side insulating layers  24  are formed so that the upper end thereof is located at a position higher than the upper ends of control gates  20  and  30  with respect to the semiconductor substrate  10 . In the adjacent memory cells  100 , a buried insulating layer  70  is formed between the first control gate  20  and the second control gate  30  adjacent thereto. The buried insulating layer  70  covers the control gates  20  and  30  so that at least the control gates  20  and  30  are not exposed. 
     The common contact section  200  applies a voltage to the control gates  20  and  30 . The common contact section  200  includes an insulating layer  210 , a conductive layer  220 , and a cap layer  230  which are formed over the element isolation region  300 . The insulating layer  210  is formed in the same step as the second gate insulating layer  22  and the side insulating layer  24 . The insulating layer  210  is formed of a laminate consisting of the first silicon oxide layer  22   a , the silicon nitride layer  22   b , and the second silicon oxide layer  22   c . The conductive layer  220  is formed in the same step as the first and second control gates  20  and  30 . The conductive layer  220  is connected to the control gates  20  and  30  and formed of the same material as the control gates  20  and  30 . The cap layer  230  is formed of an insulating layer such as a silicon nitride layer. The cap layer  230  functions as a mask layer (second mask layer) during patterning of the control gates  20  and  30  and the conductive layer  220 . 
     An interlayer dielectric  72  is provided over the semiconductor substrate  10  on which the memory cells  100 , the common contact sections  200 , and the like are formed. The interlayer dielectric  72  has a contact hole which reaches the conductive layer  220  in the contact section  200 , and this contact hole is filled with a conductive layer  82 . The conductive layer  82  is connected to an interconnect layer  80  formed on the interlayer dielectric  72 . 
     In the semiconductor integrated circuit device according to this embodiment of the present invention, every pair of control gates  20  and  30  in the shape of sidewalls is connected to the common contact section  200  in the shape of a pad, whereby an electrical connection with the control gates can be achieved reliably. Specifically, the control gate of the present invention has a shape of sidewall and generally has a width of 0.1 μm or less. Therefore, it is important to secure an electrical connection with such control gates. In this semiconductor integrated circuit device according to this embodiment, electrical contact with the control gates can be secured by the common contact section in the minimum area. 
     2. Fabrication Method of Semiconductor Integrated Circuit Device 
     A method of fabricating the semiconductor integrated circuit device according to the embodiment of the present invention is described below with reference to FIGS. 3 to  14 . Each cross-sectional view is a section taken along the line A—A shown in FIG.  1 . In FIGS. 3 to  14 , components that are the same as those in FIG. 1 are denoted by the same reference numbers and further description is omitted. 
     (1) The element isolation region  300  is formed on the surface of the semiconductor substrate  10  using a LOCOS process or a trench isolation process, as shown in FIGS. 3 and 4. The deep N-type first well  10   a  and the P-type second well  10   b  which is shallower than the first well  10   a  are then formed. The contact impurity diffusion layers  400  for forming the contacts  250  (see FIG. 1) for the bit line  60  are formed in the semiconductor substrate  10 . 
     The first gate insulating layer  12 , a word gate layer (first conductive layer)  140  consisting of doped polysilicon, and a stopper layer S 100  used in a chemical mechanical polishing (CMP) process described later are formed on the surface of the semiconductor substrate  10 . A silicon nitride layer or the like may be used as the stopper layer S 100 . 
     A laminate consisting of the word gate layer  140  and the stopper layer S 100  is formed on the entire surface of the semiconductor substrate  10  excluding openings  160  and  180 , as shown in FIG.  4 . The openings  160  and  180  correspond to the regions in which the impurity diffusion layers  16  and  18  are formed by ion implantation described later. The line A—A shown in FIG. 4 corresponds to the line A—A shown in FIG.  1 . The side insulating layers and the control gates are formed along the edges of the openings  160  and  180  in a step described later. 
     (2) The first silicon oxide layer  22   a , the silicon nitride layer  22   b , and the second silicon oxide layer  22   c  are formed in that order on the surface of the semiconductor substrate  10  on which the laminate consisting of the word gate layer  140  and the stopper layer S 100  is formed, as shown in FIG.  5 . The first silicon oxide layer  22   a  may be formed by using a thermal oxidation process, for example. The silicon nitride layer  22   b  may be deposited by using a chemical vapor deposition (CVD) process after annealing in an ammonia atmosphere, for example. The second silicon oxide layer  22   c  may be deposited by using a CVD process such as a high temperature oxidation process. It is preferable to anneal these deposited layers, thereby causing each layer to be densified. 
     The first silicon oxide layer  22   a , the silicon nitride layer  22   b , and the second silicon oxide layer  22   c  are patterned in a step described later, thereby forming the second gate insulating layers  22  and the side insulating layers  24  for the control gates  20  and  30  and the insulating layers  210  in the common contact sections  200 , as shown in FIG.  2 . 
     (3) A doped polysilicon layer (second conductive layer)  20   a  ( 30   a ) is formed on the entire surface of the second silicon oxide layer  22   c , as shown in FIG.  6 . The doped polysilicon layer  20   a  ( 30   a ) is patterned in a step described later, thereby making up the conductive layers  40  (see FIG. 1) which form the control gates  20  and  30  and the conductive layers  220  (see FIG. 2) in the common contact sections  200 . 
     Resist layers (first mask layers) R 100  are then formed in regions  200   a  in which the common contact sections  200  are formed (hereinafter called “common contact section formation regions”). The resist layers R 100  are arranged in a staggered pattern. In this embodiment, the resist layers R 100  are provided at locations corresponding to the common contact section formation regions  200   a , as shown in FIG.  7 . 
     (4) The entire surface of the doped polysilicon layer  20   a  is anisotropically etched, thereby forming the first and second control gates  20  and  30  and the conductive layers  220   a  in the common contact sections, as shown in FIG.  8 . Specifically, the control gates  20  and  30  in the shape of sidewalls are formed on the second gate insulating layer  22 , along the sides of the openings  160  and  180  in the word gate layer  140  (see FIG.  4 ), with the side insulating layers  24  interposed therebetween. At the same time, the conductive layers  220   a  in the common contact sections which are connected to the control gates  20  and  30  are formed in the areas masked by the resist layers R 100 . The resist layers R 100  are then removed by a method such as dissolving or ashing. 
     (5) The impurity diffusion layers  16  and  18  which form either the source region or drain region are formed in the second well  10   b  by ion implantation of impurities such as N-type impurities into the entire surface, as shown in FIG.  9 . The second gate insulating layer  22  may optionally be removed in the regions in which the impurity diffusion layers  16  and  18  are formed. A silicide layer such as a titanium silicide layer or cobalt silicide layer may be formed on the exposed areas of the impurity diffusion layers  16  and  18 . 
     (6) An insulating layer  70   a  is formed of silicon oxide, silicon nitride oxide, or the like over the entire surface of the semiconductor substrate  10  on which the first and second control gates  20  and  30 , conductive layers  220   a  and the like are formed, as shown in FIG.  10 . 
     (7) The insulating layer  70   a  is planarized by using a CMP process so that the stopper layer S 100  is exposed, as shown in FIG.  11 . The side insulating layers  24  formed on the sides of the word gate layer  140  and the stopper layer S 100  are allowed to remain so as to project over the control gates  20  and  30 . As a result, buried insulating layers  70  are formed between the side insulating layers  24  with the control gates  20  and  30  interposed. This step causes the first and second control gates  20  and  30  to be completely covered with the buried insulating layers  70  and exposes at least part of the conductive layers  220  in the common contact sections. 
     (8) An insulating layer  230   a  such as a silicon nitride layer is formed over the entire surface of a structure in which the buried insulating layers  70  and the stopper layer S 100  are formed, as shown in FIG.  12 . Then resist layers R 200  are formed in the common contact section formation regions  200   a , as shown in FIG.  13 . The insulating layer  230   a  is patterned by using the resist layers R 200  as a mask, thereby forming cap layers (second mask layers)  230 . The resist layers R 200  are then removed by a conventional method. 
     (9) After forming a conductive layer consisting of a doped polysilicon layer, a metal layer, or an alloy layer such as a silicide layer, resist layers R 300  are formed as shown in FIG.  14 . Word lines  50  are then formed by patterning this conductive layer. If the resist layers R 300  or word lines  50  are formed of a metal, the word gate layer  140  consisting of doped polysilicon is patterned by using the metal layer as a mask, thereby forming the word gates  14  arranged in a matrix. 
     Then the interlayer dielectric  72  is formed by a conventional method, and then the conductive layers  82  and the interconnect layers  80  connected to the common contact sections  200  are formed, as shown in FIG.  2 . 
     The semiconductor integrated circuit device shown in FIG. 1 is fabricated by these steps. 
     According to this fabrication method, the common contact sections  200  can be formed together with the control gates  20  and  30  in the shape of sidewalls without increasing the number of steps. The common contact section  200  has a size close to at least the widths of the impurity diffusion layers  16  and  18 , whereby a sufficiently large contact area can be secured. According to the present invention, therefore, reliable electrical connection with the control gates  20  and  30  can be achieved through the common contact sections  200  even if the control gates  20  and  30  are shaped as sidewalls for which it is difficult to provide a sufficient contact region. 
     3. Modification 
     A modification of this embodiment of the present invention is described below with reference to FIG.  15 . FIG. 15 is a plan view showing the step (3) in the above embodiment and corresponds to FIG.  7 . In FIG. 15, components that are the same as those shown in FIG. 7 are denoted by the same reference numbers, and further description thereof is omitted. 
     In the configuration in FIG. 7, the resist layers R 100  are formed only in the regions corresponding to the common contact section formation regions  200   a . In contrast, the configuration in FIG. 15 has resist layers (first mask layers) R 400  formed continuously so as to cover a plurality of common contact section formation regions  200   a  present in the row direction. In comparison with the separate resist layers R 100  shown in FIG. 7, use of such continuous resist layers R 400  reduces the proximity effect of light during lithography, enabling more accurate patterning. 
     In this modification, the doped polysilicon layer  20   a  ( 30   a ) remains in the area other than the common contact section formation regions  200   a . However, unnecessary portions may be removed by using the cap layers (second mask layers)  230  as a mask when patterning the word gates  14  in the step (9) in the above embodiment. 
     The present invention is not limited to the above-described embodiment, and various modifications can be made within the scope of the invention. For example, a bulk semiconductor substrate is used as a semiconductor layer in the above embodiment. However, a semiconductor layer of an SOI substrate may be used.