Patent Publication Number: US-11653503-B2

Title: Semiconductor structure with data storage structure and method for manufacturing the same

Description:
PRIORITY CLAIM AND CROSS-REFERENCE 
     This Application is a continuation application of U.S. patent application Ser. No. 16/134,063 filed Sep. 18, 2018, which is a Divisional Application of U.S. patent application Ser. No. 14/885,035, filed on Oct. 16, 2015, and issued as U.S. Pat. No. 10,090,360, which claims the benefit of U.S. Provisional Application No. 62/116,059, filed on Feb. 13, 2015, and entitled “A novel memory structure for OTP memory and RRAM application”, the entirety of each of which are incorporated by reference herein. 
    
    
     BACKGROUND 
     Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic equipment. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers of material over a semiconductor substrate, and patterning the various material layers using lithography to form circuit components and elements thereon. 
     However, although existing semiconductor manufacturing processes have generally been adequate for their intended purposes, as device scaling-down continues, they have not been entirely satisfactory in all respects. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It should be noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. 
         FIGS.  1 A to  1 D  are cross-sectional representations of various stages of forming a semiconductor structure in accordance with some embodiments. 
         FIGS.  2 A to  2 C  are cross-sectional representations of various stages of forming a semiconductor structure in accordance with some embodiments. 
         FIGS.  3 A to  3 D  are cross-sectional representations of various stages of forming a semiconductor structure in accordance with some embodiments. 
         FIGS.  4 A to  4 C  are cross-sectional representations of various stages of forming a semiconductor structure in accordance with some embodiments. 
     
    
    
     DETAILED DESCRIPTION 
     The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. 
     Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature&#39;s relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. 
     Embodiments of semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes a gate structure, source/drain structures formed adjacent to the gate structure, and an interlayer dielectric layer covering the source/drain structures. A first conductive structure is formed through the interlayer dielectric layer over a source/drain structure to be connected with the source/drain structure. A second conductive structure is formed in the interlayer dielectric layer but is not in direct contact with any source/drain structure, such that the semiconductor structure can be used as a memory structure for data storage. 
       FIGS.  1 A to  1 D  are cross-sectional representations of various stages of forming a semiconductor structure  100   a  in accordance with some embodiments. As shown in  FIG.  1 A , a substrate  102  is provided in accordance with some embodiments. Substrate  102  may be a semiconductor wafer such as a silicon wafer. Alternatively or additionally, substrate  102  may include elementary semiconductor materials, compound semiconductor materials, and/or alloy semiconductor materials. Examples of the elementary semiconductor materials may be, but are not limited to, crystal silicon, polycrystalline silicon, amorphous silicon, germanium, and/or diamond. Examples of the compound semiconductor materials may be, but are not limited to, silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide. Examples of the alloy semiconductor materials may be, but are not limited to, SiGe, GaAsP, AlInAs, AlGaAs, GalnAs, GaInP, and/or GaInAsP. 
     A gate structure  104  is formed over substrate  102 , as shown in  FIG.  1 A  in accordance with some embodiments. In some embodiments, gate structure  104  includes a gate dielectric layer  106  and a gate electrode layer  108 . 
     In some embodiments, gate dielectric layer  106  is made of high-k dielectric materials, such as metal oxides, metal nitrides, metal silicates, transition metal-oxides, transition metal-nitrides, transition metal-silicates, or oxynitrides of metals. Examples of the high-k dielectric material include, but are not limited to, hafnium oxide (HfO 2 ), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), zirconium oxide, titanium oxide, aluminum oxide, hafnium dioxide-alumina (HfO 2 —Al 2 O 3 ) alloy, or other applicable dielectric materials. 
     In some embodiments, gate electrode layer  108  is made of a conductive material, such as aluminum, copper, tungsten, titanium, tantalum, titanium nitride, tantalum nitride, nickel silicide, cobalt silicide, TaC, TaSiN, TaCN, TiAl, TiAlN, or other applicable conductive materials. In some embodiments, gate electrode layer  108  is made of polysilicon. 
     A hard mask layer  110  is formed over gate structure  104 , as shown in  FIG.  1 A  in accordance with some embodiments. In some embodiments, hard mask layer  110  is made of silicon oxide, silicon nitride, silicon oxynitride, or silicon carbide. 
     In addition, a sealing layer  112  is formed on the sidewalls of gate structure  104  and hard mask layer  110 , as shown in  FIG.  1 A  in accordance with some embodiments. Sealing layer  112  may protect gate structure  104  from damage or loss during subsequent processing and may also prevent oxidation during subsequent processing. In some embodiments, sealing layer  112  is made of silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, or other applicable dielectric materials. Sealing layer  112  may include a single layer or multiple layers. 
     Spacers  114  are further formed on sealing layer  112  in accordance with some embodiments. In some embodiments, spacers  114  are made of silicon nitride, silicon oxide, silicon carbide, silicon oxynitride, or other applicable materials. 
     A first source/drain structure  116  and a second source/drain structure  118  are formed adjacent to gate structure  104  in substrate  102 , as shown in  FIG.  1 A  in accordance with some embodiments. More specifically, first source/drain structure  116  is formed at a first side of gate structure  104 , and second source/drain structure  118  is formed at a second side of gate structure  104 . That is, first source/drain structure  116  and second source/drain structure  118  are formed at opposite sides of gate structure  104 . 
     In some embodiments, first source/drain structure  116  and second source/drain structure  118  are formed by using an implantation process or an epitaxial (epi) process. In some embodiments, first source/drain structure  116  and second source/drain structure  118  include Ge, SiGe, InAs, InGaAs, InSb, GaAs, GaSb, InAlP, InP, or the like. 
     After first source/drain structure  116  and second source/drain structure  118  are formed in substrate  102 , an interlayer dielectric layer  120  is formed over substrate  102 , as shown in  FIG.  1 A  in accordance with some embodiments. In some embodiments, interlayer dielectric layer  120  includes a first layer  119  and a second layer  121 . In some embodiments, first layer  119  is formed by depositing a dielectric material over substrate  102  and polishing the dielectric material to expose the top surface of hard mask layer  110 . Accordingly, the top surface of first layer  119  is substantially level with the top surface of hard mask layer  110  in accordance with some embodiments. In some embodiments, first layer  119  has a thickness T 119  in a range from about 300 Å to about 1000 Å. In addition, the thickness T 119  may also be seen as the distance between the top surface of substrate  102  and the top surface of hard mask layer  110 . 
     In addition, second layer  121  is formed on first layer  119  and gate structure  104  and has a thickness T 121  in a range from about 300 Å to about 1200 Å in accordance with some embodiments. In addition, the sum of thickness T 119  and thickness T 121  is equal to the thickness of interlayer dielectric layer  120  in accordance with some embodiments. 
     First layer  119  and second layer  121  may be made of the same or different dielectric materials, such as silicon oxide, silicon nitride, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), and/or other applicable dielectric materials. Interlayer dielectric layer  120  may be formed by chemical vapor deposition (CVD), physical vapor deposition, (PVD), atomic layer deposition (ALD), spin-on coating, or other applicable processes. 
     After interlayer dielectric layer  120  is formed, a first trench  122  is formed through interlayer dielectric layer  120 , as shown in  FIG.  1 B  in accordance with some embodiments. In addition, first trench  122  is formed over first source/trench structure  116 , and first source/trench structure  116  is exposed by first trench  122 . In some embodiments, first trench  122  is formed by using a first mask and etching interlayer dielectric layer  120  through the first mask. In some embodiments, first trench  122  has a first depth D 1  in a range from about 600 Å to about 2200 Å. As shown in  FIG.  1 B , since first trench  122  completely penetrates through interlayer dielectric layer  120 , the first depth D 1  of first trench  122  may also be defined as the thickness of interlayer dielectric layer  120 . 
     After first trench  122  is formed, a second trench  124  and a third trench  126  are formed in interlayer dielectric layer  120 , as shown in  FIG.  1 C  in accordance with some embodiments. In some embodiments, second trench  124  and third trench  126  are formed by using a mask and etching interlayer dielectric layer  120  and hard mask layer  110  through the mask in the same patterning process. 
     More specifically, second trench  124  is formed over second source/drain structure  118 , and third trench  126  is formed over gate structure  104 . As shown in  FIG.  1 C , unlike first trench  122 , second trench  124  is formed in interlayer dielectric layer  120  but does not penetrate through interlayer dielectric layer  120 . Accordingly, second source/drain structure  118  is not exposed by second trench  124 . In some embodiments, second trench  124  has a second depth D 2 , which is smaller than the first depth D 1  of first trench  122 . In some embodiments, the second depth D 2  is in a range from about 300 Å to about 2185 Å. 
     In addition, third trench  126  is formed over gate structure  104 . As shown in  FIG.  1 C , third trench  126  is formed through interlayer dielectric layer  120  and hard mask layer  110  over gate structure  104 . Accordingly, the top surface of gate structure  104  is exposed by third trench  126 . 
     In some embodiments, third trench  126  has a third depth D 3 , which is smaller than the second depth D 2  of second trench  124  and also smaller than the first depth D 1  of first trench  122 . In some embodiments, the third depth D 3  is in a range from about 300 Å to about 600 Å. 
     After first trench  122 , second trench  124 , and third trench  126  are formed, a first conductive structure  128 , a second conductive structure  130 , and a third conductive structure  132  are formed in first trench  122 , second trench  124 , and third trench  126  respectively. 
     In some embodiments, first conductive structure  128  includes a barrier layer  134  and a conductive layer  136 . Barrier layer  134  may be formed on the sidewalls and bottom of first trench  122 , and conductive layer  136  may be formed over barrier layer  134 . In some embodiments, barrier layer  134  is made of tantalum nitride, although other materials, such as tantalum, titanium, titanium nitride, or the like, may also be used. 
     In some embodiments, conductive layer  136  is made of aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantulum (Ta), titanium nitride (TiN), tantalum nitride (TaN), nickel silicide (NiS), cobalt silicide (CoSi), tantulum carbide (TaC), tantulum silicide nitride (TaSiN), tantalum carbide nitride (TaCN), titanium aluminide (TiAl), titanium aluminide nitride (TiAlN), other applicable conductive materials, or a combination thereof. 
     In some embodiments, second conductive structure  130  also includes a barrier layer  138  and a conductive layer  140 . Barrier layer  138  may be formed on the sidewalls and bottom of second trench  124 , and conductive layer  140  may be formed over barrier layer  138 . In some embodiments, barrier layer  138  is made of tantalum nitride, although other materials, such as tantalum, titanium, titanium nitride, or the like, may also be used. 
     In some embodiments, conductive layer  140  is made of aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantulum (Ta), titanium nitride (TiN), tantalum nitride (TaN), nickel silicide (NiS), cobalt silicide (CoSi), tantulum carbide (TaC), tantulum silicide nitride (TaSiN), tantalum carbide nitride (TaCN), titanium aluminide (TiAl), titanium aluminide nitride (TiAlN), other applicable conductive materials, or a combination thereof. 
     In some embodiments, third conductive structure  132  also includes a barrier layer  142  and a conductive layer  144 . In some embodiments, barrier layer  142  is made of the same material used to make barrier layer  134 . In some embodiments, conductive layer  144  is made of the same material used to make conductive layer  136 . 
     In some embodiments, first conductive structure  128 , second conductive structure  130 , and third conductive structure  132  are formed in the same depositing process and include the same conductive material. In some embodiments, first conductive structure  128 , second conductive structure  130 , and third conductive structure  132  are formed separately and include different conductive materials. For example, the material used to form second conductive structure  130  may be chosen according to its application to function as a memory structure (Details will be described later). 
     As shown in  FIG.  1 D , first conductive structure  128  is formed through interlayer dielectric layer  120 , and therefore has a first depth D 1 , which is the same as the thickness of interlayer dielectric layer  120 . In addition, since first source/drain structure  116  is exposed by first trench  122 , as shown in  FIG.  1 C , first conductive structure  128  formed in first trench  122  is in direct contact with first source/drain structure  116 . 
     On the other hand, second conductive structure  130  is formed in interlayer dielectric layer  120  but does not penetrate through interlayer dielectric layer  120 , and therefore second conductive structure  130  has a second depth D 2 , which is smaller than the first depth D 1  of first conductive structure  128 . In addition, since second source/drain structure  118  is not exposed by second trench  124 , as shown in  FIG.  1 C , second conductive structure  130  formed in second trench  124  is not in direct contact with second source/drain structure  118 . 
     As shown in  FIG.  1 D , semiconductor structure  100   a  includes first conductive structure  128 , second conductive structure  130 , and third conductive structure  132 . The top surface of first conductive structure  128  is substantially level with the top surface of second conductive structure  130  and the top surface of third conductive structure  132 . In addition, the top surfaces of first conductive structure  128 , second conductive structure  130 , and third conductive structure  132  are also substantially level with the top surface of interlayer dielectric layer  120 . 
     Furthermore, the first depth D 1  of first conductive structure  128 , which is substantially equal to the thickness of interlayer dielectric layer  120 , is larger than the second depth D 2  of second conductive structure  130 . Therefore, interlayer dielectric layer  120  is penetrated by first conductive structure  128  but is not penetrated by second conductive structure  130 . Accordingly, second conductive structure  130  and second source/drain structure  118  are separated by a portion  146  of interlayer dielectric layer  120 . In some embodiments, portion  146  of interlayer dielectric layer  120  has a thickness T a  in a range from about 15 Å to about 500 Å. In some embodiment, a ratio of thickness T a  of portion  146  to thickness T 119  of first layer  119  of interlayer dielectric layer  120  is in a range from about 1/20 to about ½. In some embodiments, a ratio of thickness T a  of portion  146  to second depth D 2  is in a range from about 1/20 to about ½. 
     As described previously, although first trench  122  is formed through interlayer dielectric layer  120 , second trench  124  is formed in interlayer dielectric layer  120  but does not penetrate through interlayer dielectric layer  120 . Therefore portion  146  is left between second conductive structure  130  and second source/drain structure  118 . Accordingly, portion  146  can be used for data storage in semiconductor structure  100   a . However, if the thickness T a  of portion  146  is too thick, the operation voltage of semiconductor structure  100   a  may become too large. On the other hand, if the thickness T a  of portion  146  is too small, it may not be able to switch from one stage to another. 
     The thickness Ta of portion  146  may be adjusted by altering the depth D 2  of second conductive structure  130 , and the depth D 2  of second conductive structure  130  can be controlled by changing the condition of the etching process which is used to form second trench  124  and/or by changing the materials used to form interlayer dielectric layer  120 . 
     In some embodiments, the processes described above are applied to a FinFET manufacturing process, although they may also be applied to a planar transistor manufacturing process. As described previously, second trench  124  can be formed in the process used to form third trench  126 . Therefore, no additional masking process is required. Accordingly, the processes described above may be compatible with existing processes for forming logic devices without using additional complicated processes, such as additional masking processes. 
       FIGS.  2 A to  2 C  are cross-sectional representations of various stages of forming a semiconductor structure  100   b  in accordance with some embodiments. Semiconductor structure  100   b  is similar to, or the same as, semiconductor structure  100   a  described in  FIGS.  1 A to  1 D , except a second trench  124   b  and a third trench  126   b  are formed separately. Materials and processes used to form semiconductor structure  100   b  may be the same as, or similar to, those used to form semiconductor structure  100   a  described previously and are not repeated herein. 
     More specifically, processes shown in  FIGS.  1 A and  1 B  and described previously are performed in accordance with some embodiments. After first trench  122  is formed in interlayer dielectric layer  120 , second trench  124   b  is formed, as shown in  FIG.  2 A  in accordance with some embodiments. After second trench  124   b  is formed, third trench  126   b  is formed, as shown in  FIG.  2 B  in accordance with some embodiments. 
     That is, unlike second trench  124  and third trench  126  shown in  FIG.  1 C , second trench  124   b  and third trench  126   b  are formed by different patterning processes. Since second trench  124   b  and third trench  126   b  are formed separately, the second depth D 2  of second trench  124   b  can be better controlled and can be adjusted if required. 
     After first trench  122 , second trench  124   b , and third trench  126   b  are formed, a first conductive structure  128   b , a second conductive structure  130   b , and a third conductive structure  132   b  are respectively formed in first trench  122 , second trench  124   b , and third trench  126   b . As shown in  FIG.  2 C , first conductive structure  128   b  is in direct contact with first source/drain structure  116 , while second conductive structure  130   b  is not in direct contact with second source/drain structure  118 . 
     In addition, first conductive structure  128   b , second conductive structure  130   b , and third conductive structure  132   b  also include barrier layers  134 ,  138 , and  142  and conductive layers  136 ,  140 , and  144  in accordance with some embodiments. Materials used to form first conductive structure  128   b , second conductive structure  130   b , and third conductive structure  132   b  may be similar to, or the same as, those used to form first conductive structure  128 , second conductive structure  130 , and third conductive structure  132  shown in  FIG.  1 D  and have been described previously, and that description is not repeated herein. 
     As shown in  FIGS.  2 A and  2 B , second trench  124   b  and third trench  126   b  are formed separately. That is, an additional masking process is used to form second trench  124   b . Therefore, the second depth D 2  of second conductive structure  130   b  formed in second trench  124   b  can be adjusted without limiting by the formation of third conductive structure  132   b  formed in third trench  126   b . Since second depth D 2  can be adjusted more freely and separately, thickness T b  of portion  146  can also be adjusted according to its application. For example, thickness T b  of portion  146  may be adjusted so the resulting semiconductor structure  100   b  can have the improved resistance and/or operating voltage. In some embodiments, the thickness T b  of portion  146   b  is in a range of 10 Å to about 500 Å. 
       FIGS.  3 A to  3 D  are cross-sectional representations of various stages of forming a semiconductor structure  100   c  in accordance with some embodiments. Semiconductor structure  100   c  is similar to, or the same as, semiconductor structure  100   a  described in  FIGS.  1 A to  1 D , except the formation of second trench  124   c  is different from that in  FIGS.  1 A to  1 D . Materials and processes used to form semiconductor structure  100   c  may be the same as, or similar to, those used to form semiconductor structure  100   a  and are not repeated herein as they have been described previously. 
     More specifically, when a first trench  122   c  is formed over first source/drain structure  116 , a temporary trench  324  is also formed over second source/drain structure  118 , as shown in  FIG.  3 A  in accordance with some embodiments. As shown in  FIG.  3 A , both first trench  122   c  and second trench  124   c  are formed through interlayer dielectric layer  120 . Therefore, first source/drain structure  116  is exposed by first trench  122   c , and second source/drain structure  118  is exposed by temporary trench  324 . In some embodiments, the depth of temporary trench  324  is substantially equal to the depth D 1  of first trench  122   c.    
     After temporary trench  324  is formed, a third trench  126   c  is formed through interlayer dielectric layer  120  and hard mask layer  110 , as shown in FIG.  3 B in accordance with some embodiments. After the formation of first trench  122 , temporary trench  324 , and third trench  126   b  is completed, an additional dielectric layer  325  is formed in the bottom of temporary trench  324 , as shown in  FIG.  3 C  in accordance with some embodiments. 
     More specifically, additional dielectric layer  325  is deposited in the bottom of temporary trench  324  to form a second trench  124   c , such that second trench  124   c  does not expose second source/drain structure  118 . In some embodiments, additional dielectric layer  325  has a thickness T 325  in a range from about 10 Å to about 2000 Å. In some embodiments, additional dielectric layer  325  is made of silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), or the like. It should be noted that additional dielectric layer  325  may include one or multiple layers made of one or multiple dielectric materials. 
     After first trench  122 , second trench  124   b , and third trench  126   b  are formed, a first conductive structure  128   c , a second conductive structure  130   c , and a third conductive structure  132   c  are formed in first trench  122   c , second trench  124   c , and third trench  126   c , respectively. In addition, first conductive structure  128   c , second conductive structure  130   c , and third conductive structure  132   c  also include barrier layers  134 ,  138 , and  142  and conductive layers  136 ,  140 , and  144  in accordance with some embodiments. Materials used to form first conductive structure  128   c , second conductive structure  130   c , and third conductive structure  132   c  may be similar to, or the same as, those used to form first conductive structure  128 , second conductive structure  130 , and third conductive structure  132  shown in  FIG.  1 D  and described previously and are not repeated herein. 
     As shown in  FIG.  3 D , second conductive structure  130   c  is separated from second source/drain structure  118  by additional dielectric layer  325 . That is, although first conductive structure  128   c  is in direct contact with first source/drain structure  116 , second conductive structure  130   c  is not in direct contact with second source/drain structure  118 . 
     In addition, additional dielectric layer  325  is formed in an individual process. Therefore, the thickness and the material of additional dielectric layer  325  can be adjusted according to its applications. In some embodiments, additional dielectric layer  325  and interlayer dielectric layer  120  are made of different materials. 
     As shown in  FIGS.  3 A to  3 C , second trench  124   c  is formed by forming temporary trench  324  and depositing additional dielectric layer  325  in the bottom of temporary trench  324 . Therefore, the second depth D 2  can be adjusted by depositing additional dielectric layer  325  to a designated thickness. Accordingly, the second depth D 2  can be adjusted more freely and separately without limiting by the formation of third trench  126   b.    
     In addition, since second conductive structure  130   c  is formed in second trench  124   c , second conductive structure  130   c  is separated from second source/drain structure  118  by additional dielectric layer  325 . That is, second conductive structure  130   c  and second source/drain structure  118  is separated from each other by distance T c , which is equal to the thickness T 325  of additional dielectric layer  325 , as shown in  FIGS.  3 C and  3 D . In some embodiments, the distance T c  (i.e. the thickness T 325  of additional dielectric layer  325 ) is in a range of 10 Å to about 2000 Å. 
     Furthermore, the thickness and materials of additional dielectric layer  325  may be altered according to its application, so that the resulting semiconductor structure  100   c  can have the designated resistance and/or operating voltage. Therefore, function of semiconductor structure  100   c  may have more variety and may be applied to various applications. 
       FIGS.  4 A to  4 C  are cross-sectional representations of various stages of forming a semiconductor structure  100   d  in accordance with some embodiments. Semiconductor structure  100   d  is similar to, or the same as, semiconductor structure  100   a  described in  FIGS.  1 A to  1 D , except the formation of second trench  124   d  is different from that in  FIGS.  1 A to  1 D . Materials and processes used to form semiconductor structure  100   d  may be the same as, or similar to, those used to form semiconductor structure  100   a  described previously and are not repeated herein. 
     More specifically, a first trench  122   d  is formed through interlayer dielectric layer  120  over first source/drain structure  116 , and third trench  126   d  is formed through interlayer dielectric layer  120  and hard mask layer  110  over gate structure  104 , as shown in  FIG.  4 A  in accordance with some embodiments. In addition, a temporary trench  324   d  is formed over second source/drain structure  118 . 
     Methods and materials used to form first trench  122   d  may be similar to, or the same as those used to form first trench  122  shown in  FIGS.  1 B,  2 A, and  3 A , and methods and materials used to form third trench  126   d  may be similar to, or the same as those used to form third trenches  126 ,  126   b , and  126   c  in  FIGS.  1 C,  2 B, and  3 B . In addition, methods and materials used to form temporary trench  324   d  may be similar to, or the same as those used to form second trenches  124 ,  124   b , and  124   c  in  FIGS.  1 C,  2 B, and  3 C . For example, temporary trench  324   d  and third trench  126   d  are formed in the same patterning process in accordance with some embodiments. As shown in  FIG.  4 A , a portion  426   d  is left between temporary trench  324   d  and second source/drain structure  118 , and portion  426   d  has a thickness T 146d . 
     After temporary trench  324   d  is formed, an additional dielectric layer  325   d  is formed in the bottom of temporary trench  324   d , as shown in  FIG.  4 B  in accordance with some embodiments. More specifically, additional dielectric layer  325   d  is deposited in the bottom of temporary trench  324   d  to form a second trench  124   d.    
     In some embodiments, additional dielectric layer  325   d  has a thickness T 325d  in a range from about 5 Å to about 500 Å. In some embodiments, additional dielectric layer  325   d  is silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), or the like. It should be noted that additional dielectric layer  325   d  may include one or multiple layers made of one or multiple dielectric materials. In some embodiments, additional dielectric layer  325   d  and interlayer dielectric layer  120  are made of different dielectric materials. 
     After first trench  122 , second trench  124   d , and third trench  126  are formed, a first conductive structure  128   d , a second conductive structure  130   d , and a third conductive structure  132   d  are formed in first trench  122 , second trench  124   d , and third trench  126  respectively. In addition, first conductive structure  128   d , second conductive structure  130   d , and third conductive structure  132   d  also include barrier layers  134 ,  138 , and  142  and conductive layers  136 ,  140 , and  144  in accordance with some embodiments. Methods and materials used to form first conductive structure  128   d , second conductive structure  130   d , and third conductive structure  132   d  may be similar to, or the same as, those used to form the previously described first conductive structure  128 , second conductive structure  130 , and third conductive structure  132  shown in  FIG.  1 D , and these descriptions are not repeated herein. 
     As shown in  FIG.  4 C , second conductive structure  130   d  is separated from second source/drain structure  118  by interlayer dielectric layer  120  and additional dielectric layer  325   d . That is, although first conductive structure  128   d  is in direct contact with first source/drain structure  116 , second conductive structure  130   d  is not in direct contact with second source/drain structure  118 . 
     In addition, the thickness and the material of additional dielectric layer  325   d  can be adjusted according to its applications. In some embodiments, additional dielectric layer  325  and interlayer dielectric layer  120  are made of different materials. 
     As shown in  FIG.  4 B , additional dielectric layer  325   d  is formed in temporary trench  324   d , such that second conductive structure  130   d  and second source/drain structure  118  are separated by a portion  146   d  of interlayer dielectric layer  120  and additional dielectric layer  325   d . Accordingly, second conductive structure  130   d  and second source/drain structure  118  are separated by a distance T d , which is equal to the sum of the thickness T 325d  of additional dielectric layer  325   d  and the thickness T 146d  of portion  146   d  of interlayer dielectric layer  120 . In some embodiments, distance T d  is in a range of 15 Å to about 1000 Å. 
     Similarly, since the thickness and materials of additional dielectric layer  325   d  may be altered according to its application, the resulting semiconductor structure  100   d  can have the designated resistance and/or operating voltage. Therefore, function of semiconductor structure  100   d  may have more variety and may be applied to various applications. 
     As described previously, a second conductive structure, such as second conductive structures  130 ,  130   b ,  130   c , and  130   d , are formed without in direct contact with any source/drain structure, such as second source/drain structure  118 . That is, the second conductive structure is separated from the source/drain structure below it by a dielectric material, such as portion  146 ,  146   b , and  146   d  and additional dielectric layers  325  and  325   d . The dielectric material positioned between the second conductive structure and the source/drain structure can be used for data storage. Accordingly, the semiconductor structure, such as semiconductor structures  100   a ,  100   b ,  100   c , and  100   d  described above, can be used as a memory unit, such as a one-time programmable (OTP) memory unit or a resist random access memory (RRAM) unit. 
     Embodiments of semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes a gate structure formed over a substrate and first and second source/drain structures formed at the opposite sides of the gate structure in the substrate. A conductive structure is formed over the first source/drain structure and is in direct contact with the first source/drain structure. In addition, a second conductive structure is formed over the second source/drain structure but is not in direct contact with the second source/drain structure. That is, a dielectric portion is positioned between the second source/drain structure and the second conductive structure to separate them. In addition, the dielectric portion between the second source/drain structure and the second conductive structure can be used for data storage in a memory unit. 
     In some embodiments, a semiconductor structure is provided. The semiconductor structure includes a substrate and a gate structure formed over the substrate. The semiconductor structure further includes a first source/drain structure and a second source/drain structure formed in the substrate adjacent to the gate structure. The semiconductor structure further includes an interlayer dielectric layer formed over the substrate to cover the gate structure, the first source/drain structure, and the second source/drain structure. The semiconductor structure further includes a first conductive structure formed in the interlayer dielectric layer over the first source/drain structure. The semiconductor structure further includes a second conductive structure formed in the interlayer dielectric layer over the second source/drain structure. In addition, the first conductive structure is in direct contact with the first source/drain structure, and the second conductive structure is not in direct contact with the second source/drain structure. 
     In some embodiments, a semiconductor structure is provided. The semiconductor structure includes a substrate and a gate structure formed over the substrate. The semiconductor structure further includes a first source/drain structure formed adjacent to a first side of the gate structure in the substrate. The semiconductor structure further includes a second source/drain structure formed adjacent to a second side of the gate structure in the substrate. The semiconductor structure further includes an interlayer dielectric layer formed over the substrate to cover the gate structure, the first source/drain structure, and the second source/drain structure. The semiconductor structure further includes a first conductive structure formed through the interlayer dielectric layer on the first source/drain structure. The semiconductor structure further includes a second conductive structure formed in the interlayer dielectric layer over the second source/drain structure. In addition, the first conductive structure is in direct contact with the first source/drain structure, and the second conductive structure and the second source/drain structure are separated by a portion of the interlayer dielectric layer. 
     In some embodiments, a method for manufacturing a semiconductor structure is provided. The method for manufacturing a semiconductor structure includes forming a gate structure over a substrate and forming a first source/drain structure and a second source/drain structure in the substrate adjacent to the gate structure. The method for manufacturing a semiconductor structure further includes forming an interlayer dielectric layer over the substrate to cover the gate structure, the first source/drain structure, and the second source/drain structure. The method for manufacturing a semiconductor structure further includes forming a first trench through the interlayer dielectric layer to expose the first source/drain structure. The method for manufacturing a semiconductor structure further includes forming a second trench in the interlayer dielectric layer over the second source/drain structure, and the second source/drain structure is not exposed by the second trench. The method for manufacturing a semiconductor structure further includes forming a first conductive structure in the first trench and forming a second conductive structure in the second trench. 
     The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.