Patent Publication Number: US-2018054216-A1

Title: Flipped bits for error detection and correction for symbol transition clocking transcoding

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application claims priority to and the benefit of Provisional Patent Application No. 62/378,054 filed in the U.S. Patent Office on Aug. 22, 2016, the entire content of which application is incorporated herein by reference below in their entirety and for all applicable purposes. 
    
    
     TECHNICAL FIELD 
     The present disclosure pertains to enabling efficient operations over data communication interfaces and, more particularly, facilitating error detection in data communication interfaces that employ symbol transition clocking transcoding, 
     BACKGROUND 
     Data communication interfaces may employ symbol transition clocking transcoding to embed clock information in sequences of symbols that encode data to be transmitted over an interface that has multiple signal wires, thereby obviating the need for dedicated clock signal wires. 
     In certain examples of multi-signal data transfer, multi-wire differential signaling such as N-factorial (N!) low-voltage differential signaling (LVDS), transcoding (e,g., the digital-to-digital data conversion of one encoding type to another) may be performed to embed symbol clock information by causing symbol transition at every symbol cycle, instead of sending clock information in separate data lanes (differential transmission paths). Embedding clock information by such transcoding can also minimize skew between clock and data signals, as well as to eliminate the need for a phase-locked loop (PLL) to recover the clock information from the data signals. In one example, a two-wire serial bus operated in accordance with conventional Inter-Integrated Circuit (I2C) protocols or camera control interface (CCI) protocols can be adapted to operate in accordance with I3C high-data rate (HDR) standards and protocols defined by the Mobile Industry Processor Interface (MIPI) Alliance, the CCI extension (CCIe) bus, or other protocols that employ transition encoding. 
     Error detection can be problematic in data transfer interfaces that employ transition encoding because there is typically no direct association between a signaling state error and errors in data decoded from the data transfer interface. The disassociation between data bits and signaling state can render conventional error detection techniques ineffective when applied to transition encoding interfaces. 
     It would be desirable to provide reliable error detection in transmissions between devices that use symbol transition clocking transeoding to communicate. 
     SUMMARY 
     Certain aspects of the disclosure relate to systems, apparatus, methods and techniques that provide reliable error detection in transmissions between devices that use symbol transition clocking transcoding to communicate. 
     According to certain aspects disclosed herein, multiple symbol errors can be detected in transmissions over a transition-encoded multi-wire interface. In one example, data to be communicated over the transition-encoded multi-wire interface may be converted into a transition number, and digits of the transition number may be converted into a sequence of symbols for transmission on a plurality of wires or connectors. The transition number may be expressed using a numeral system based on a maximum number of possible symbol transitions. In some instances, the total number of states per symbol available for encoding data transmissions on the plurality of connectors is at least one less than the total number of states per symbol available for encoding data transmissions on the plurality of connectors. 
     Symbols errors may be detected using an error detection constant (EDC), which may be configured as a predetermined number of least significant bits in a plurality of bits that also includes a data word. The predetermined number of least significant bits may be determined or calculated based on a total number of states per symbol available for encoding data transmissions on the plurality of wires or connectors. A symbol error affecting one or more symbols in the sequence of symbols may cause a decoded version of the EDC to have value that is different from a known, fixed value of the EDC that was appended to the data word at the transmitter. 
     According to certain aspects, a transmitting device may include a communications transceiver coupled to a plurality of connectors, error detection logic configured to provide a data word having air EDC appended thereto, an encoder configured to convert the data word into a transition number and to generate a sequence of symbols from the transition number, and a transmitter circuit configured to transmit the sequence of symbols on the plurality of connectors. The EDC may have a known, fixed value and a fixed length. The EDC may be modified when one or more symbols in the sequence of symbols are modified during transmission. 
     In an aspect, each symbol may be generated using a digit of the transition number and a preceding symbol. Clock information may be embedded in transitions between consecutive symbols in the sequence of symbols. 
     In an aspect, the EDC may be appended as a number of least significant bits, the number of least significant bits being determined based on a total number of states per symbol available for encoding data transmissions on the plurality of connectors. The number of least significant bits may be determined based on a total number of symbols used to encode the data word. The plurality of connectors may include a number (N) of single-ended connectors. The plurality of connectors may include N connectors that carry multi-level differential signals, in one example, the total number of states per symbol available for encoding data transmissions is 2 N −x, where x is at least 1. In another example, the total number of states per symbol available for encoding data transmissions is x, where x is at least 1. 
     In an aspect, the total number of states available at each transition may be 3. The EDC may include 8 bits in a first example. The sequence of symbols may include 17 or more symbols, and the EDC may include 9 bits in a second example. In a third example, where the total number of states available at each transition is 5, the EDC may include 10 bits. In a fourth example, where the total number of states available at each transition is 5 and the sequence of symbols includes 8 or more symbols, the EDC may include 11 bits. 
     According to certain aspects a method of transmitting data on a multi-wire interface includes providing a plurality of data bits in a word to be transmitted such that a bit-order of the plurality of data bits is flipped with respect to bit-order of the word to be transmitted, providing an EDC as one or more least significant bits of the word to be transmitted and adjacent to a most significant bit of the plurality of data bits in the word to be transmitted, converting the word to be transmitted into a transition number, and transmitting the transition number as a sequence of symbols on the multi-wire interface. The transition number may be expressed using a numeral system based on a maximum number of possible states per symbol. The length of the EDC may be at least one bit and the EDC may have a known, fixed value and length selected to enable a decoder to detect or correct one or more symbol errors in the sequence of symbols. The length and the known, fixed value of the EDC may be selected such that a transmission error affecting the one or more symbols in the sequence of symbols results in the EDC having a value different from the known, fixed value when decoded. The EDC may be provided as a number of bits, the number being determined based on a number of symbols in the sequence of symbols and a total number of states per symbol available for encoding data transmissions on the multi-wire interface. In one example, the EDC includes 8 bits. 
     In some examples, the transmitting circuit may generate each symbol in the sequence of symbols using a digit of the transition number and a preceding symbol in the sequence of symbols. Clock information is embedded in transitions between consecutive symbols in the sequence of symbols. 
     In some examples, the transmitting circuit may provide control bits in the word to be transmitted in more significant bits than bits assigned to carry the plurality of data bits. 
     In some examples, the transmitting circuit may select a level of error detection or correction for a transaction on the multi-wire interface, configure the length of the EDC in accordance with the level of error detection or correction selected, and define a number of bits in the plurality of data bits in accordance with the length of the EDC. 
     According to certain aspects, an apparatus includes means for providing a plurality of bits to be transmitted over a plurality of connectors, where the plurality of bits includes an EDC that has a known, fixed value and a fixed length, where the EDC is used for error detection. The apparatus may include means for converting the plurality of bits into a transition number, means for converting the transition number into a sequence of symbols, and means for transmitting the sequence of symbols on the plurality of connectors. The transition number may be expressed using a numeral system based on a maximum number of possible states per symbol. The EDC may be modified when one or two symbols in the sequence of symbols are modified during transmission. 
     In an aspect, a clock is embedded in transitions between symbols in the sequence of symbols. 
     In an aspect, a transmission error affecting the one or two symbols in the sequence of symbols may result in the EDC having a value different from the known, fixed value when decoded at a receiver. 
     In an aspect, the EDC is provided as a number of least significant bits, the number of least significant bits being determined based on a total number of states per symbol available for encoding data transmissions on the plurality of connectors. In a first example, a total number of states available at each transition may be 3 and the EDC may include 8 bits. In a second example, a total number of states available at each transition may be 3, the sequence of symbols includes 17 or more symbols, and the EDC may include 9 bits. In a third example, a total number of states available at each transition may be 5 and the EDC may include 10 bits. 
     According to certain aspects, a method of receiving data from a multi-wire interface includes receiving a sequence of symbols from a plurality of connectors, converting the sequence of symbols into a transition number, each digit of the transition number representing a transition between two consecutive symbols transmitted on the plurality of connectors, converting the transition number into a plurality of bits, and determining whether one or two symbol errors have occurred during transmission of the sequence of symbols based on a value of an EDC included in the plurality of bits. The EDC may have been transmitted as a known, fixed value and a fixed length determined based on a total number of states per symbol defined for encoding data transmissions on the plurality of connectors. 
     In an aspect, a clock is embedded in transitions between symbols in the sequence of symbols. 
     In an aspect, the transition number may be expressed using a numeral system based on a maximum number of possible symbol transitions between a pair of consecutive symbols transmitted on the plurality of connectors. 
     In an aspect, the one or two symbol errors may cause a decoded version of the EDC to have a value that is different from the known, fixed value. 
     In an aspect, the EDC may be provided as a number of least significant bits in the plurality of bits. The number of least significant bits may be determined based on a total number of states per symbol available for encoding data transmissions on the plurality of connectors. The number of least significant bits may be determined or calculated based on a total number of symbols used to encode the plurality of bits. The plurality of connectors may include N single-ended connectors. The plurality of connectors may include N connectors that carry multi-level differential signals. In a first example, the total number of states per symbol available for encoding data transmissions is 2 N −x, where x is at least 1. In a second example, the total number of states per symbol available for encoding data transmissions is N!−x, where x is at least 1. 
     In a third example, where the total number of states available at each transition is 3, the EDC may include 8 bits. In a fourth example, where the total number of states available at each transition is 3 and the sequence of symbols includes 17 or more symbols, the EDC may include 9 bits. In a fifth example, where the total number of states available at each transition is 5, the EDC may include 10 bits. In a sixth example, where the total number of states available at each transition is 5 and the sequence of symbols includes 8 or more symbols, the EDC may include 11 bits. 
     According to certain aspects, an apparatus includes means for receiving a sequence of symbols from a plurality of connectors, means for converting the sequence of symbols into a transition number, each digit of the transition number representing a transition between two consecutive symbols transmitted on the plurality of connectors, means for converting the transition number into a plurality of bits, and means for determining whether one or two symbol errors have occurred during transmission of the sequence of symbols based on a value of an EDC included in the plurality of bits. The EDC may have been transmitted as a known, fixed value and a fixed length determined based on a total number of states per symbol defined for encoding data transmissions on the plurality of connectors. 
     In an aspect, a clock is embedded in transitions between symbols in the sequence of symbols. 
     In an aspect, the transition number may be expressed using a numeral system based on a maximum number of possible symbol transitions between a pair of consecutive symbols transmitted on the plurality of connectors. 
     In an aspect, the one or two symbol errors may cause a decoded version of the EDC to have a value that is different from the known, fixed value. 
     In an aspect, the EDC may be provided as a number of least significant bits in the plurality of bits. The number of least significant bits may be determined based on a total number of states per symbol available for encoding data transmissions on the plurality of connectors. The number of least significant bits may be calculated or otherwise determined based on a total number of symbols used to encode the plurality of bits. The plurality of connectors may include N single-ended connectors. The plurality of connectors may include N connectors that carry multi-level differential signals. In a first example, the total number of states per symbol available for encoding data transmissions is 2 N −x, where x is at least 1. In a second example, the total number of states per symbol available for encoding data transmissions is N!−x, where x is at least 1. In a third example, where the total number of states available at each transition is 3, the EDC may include 8 bits. In a fourth example, where the total number of states available at each transition is 3 and the sequence of symbols includes 17 or more symbols, the EDC may include 9 bits. In a fifth example, where the total number of states available at each transition is 5, the EDC may include 10 bits. In a sixth example, where the total number of states available at each transition is 5 and the sequence of symbols includes 8 or more symbols, the EDC may include 11 bits. 
     According to certain aspects, a computer readable storage medium has instructions stored thereon. The storage medium may include transitory or non-transitory storage media. The instructions may be executed by a processor such that the processor is caused to receive a sequence of symbols from a plurality of connectors, convert the sequence of symbols into a transition number, each digit of the transition number representing a transition between two consecutive symbols transmitted on the plurality of connectors, convert the transition number into a plurality of bits, and determine whether one or more symbol errors have occurred during transmission of the sequence of symbols based on a value of an EDC included in the plurality of bits. The EDC may have been transmitted as a known, fixed value and a fixed length determined based on a total number of states per symbol defined for encoding data transmissions on the plurality of connectors. 
     In an aspect, a clock is embedded in transitions between symbols in the sequence of symbols. 
     In an aspect, the transition number may be expressed using a numeral system based on a maximum number of possible symbol transitions between a pair of consecutive symbols transmitted on the plurality of connectors. 
     In an aspect, the one or two symbol errors may cause a decoded version of the EDC to have a value that is different from the known, fixed value. 
     In an aspect, the EDC may be provided as a fixed number of least significant bits in the plurality of bits. The fixed number of least significant bits may be calculated or otherwise determined based on a total number of states per symbol available for encoding data transmissions on the plurality of connectors. The fixed number of least significant bits may be determined based on a total number of symbols used to encode the plurality of bits. The plurality of connectors may include N single-ended connectors. The plurality of connectors may include N connectors that carry multi-level differential signals. In a first example, the total number of states per symbol available for encoding data transmissions is 2 N −x, where x is at least 1. In a second example, the total number of states per symbol available for encoding data transmissions is N!−x, where x is at least 1. in a third example, where the total number of states available at each transition is 3, the EDC may include 8 bits. In a fourth example, where the total number of states available at each transition is 3 and the sequence of symbols includes 17 or more symbols, the EDC may include 9 bits. In a fifth example, where the total number of states available at each transition is 5, the EDC may include 10 bits. In a sixth example, where the total number of states available at each transition is 5 and the sequence of symbols includes is or more symbols, the EDC may include 11 bits. 
     According to certain aspects, a device includes a communications transceiver coupled to a plurality of connectors, a receiver circuit configured to receive a sequence of symbols on the plurality of connectors, and a decoder configured to convert a transition number into a first data word, the transition number being representative of transitions between consecutive symbols in the sequence of symbols. The first data word may include a predetermined number of least significant bits that are provided for detecting one or two symbol transmission errors associated with transmission of the sequence of symbols. 
     In an aspect, a clock may be embedded in transitions between symbols in the sequence of symbols. 
     In an aspect, the transition number may be expressed using a numeral system based on a maximum number of possible symbol transitions between a pair of consecutive symbols transmitted on the plurality of connectors. 
     In an aspect, the one or two symbol errors may cause a decoded version of the EDC, to have a value that is different from the known, fixed value. 
     In an aspect, the EDC may be provided as a fixed number of least significant bits in the plurality of bits. The fixed number of least significant bits may be calculated or determined based on a total number of states per symbol available for encoding data transmissions on the plurality of connectors. The fixed number of least significant bits may be determined based on a total number of symbols used to encode the plurality of bits. The plurality of connectors may include N single-ended connectors. The plurality of connectors may include N connectors that carry multilevel differential signals. In a first example, the total number of states per symbol available for encoding data transmissions is 2 N −x, where x is at least 1. In a second example, the total number of states per symbol available for encoding data transmissions is N!−x, where x is at least 1. 
     In a third example, where the total number of states available at each transition is 3, the EDC may include 8 bits. In a fourth example, where the total number of states available at each transition is 3 and the sequence of symbols includes 17 or more symbols, the EDC may include 9 bits. In a fifth example, where the total number of states available at each transition is 5, the EDC may include 10 bits. In a sixth example, where the total number of states available at each transition is 5 and the sequence of symbols includes 8 or more symbols, the EDC may include 11 bits. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Various features, nature, and advantages may become apparent from the detailed description set forth below when taken in conjunction with the drawings in which like reference characters identify correspondingly throughout. 
         FIG. 1  depicts an apparatus employing a data link between integrated circuit (IC) devices that selectively operates according to one of a plurality of available standards. 
         FIG. 2  illustrates a system architecture for an apparatus employing a data link between IC devices. 
         FIG. 3  illustrates an example of an N! interface provided between two devices. 
         FIG. 4  illustrates a transmitter and a receiver that may be adapted according to certain aspects disclosed herein. 
         FIG. 5  illustrates an encoding scheme that may be used to control conversions between transition numbers and sequential symbols. 
         FIG. 6  illustrates the relationship between symbols and transition numbers in one example of a transition-encoding interface. 
         FIG. 7  illustrates possible transition number-to-symbol encoding at a symbol boundary in a 3! interface. 
         FIG. 8  illustrates a mathematical relationship between transition numbers and symbols in a 3! interface. 
         FIG. 9  illustrates an example in which a sequence of symbols transmitted over a multi-wire communication interface is affected by a single symbol error. 
         FIG. 10  is a diagram that illustrates a mathematical relationship characterizing a single symbol error in a sequence of symbols transmitted over a multi-wire communication interface. 
         FIG. 11  tabulates values of r n , where n lies in the range 0-15, and when r=3 and r=5. 
         FIG. 12  tabulates error coefficients corresponding to a single symbol error in a sequence of symbols. 
         FIG. 13  illustrates the longest non-zero LSB portion in an error coefficient. 
         FIG. 14  illustrates cases in which a single symbol error results in an error in a single transition number. 
         FIG. 15  illustrates a first example of signaling errors affecting two symbols in a sequence of symbols transmuted over a multi-wire communication interface. 
         FIG. 16  illustrates a second example of signaling errors that affect two consecutive symbols transmitted over a multi-wire communication interface. 
         FIG. 17  illustrates the number of bits provided in an EDC for detection of two symbol errors in a sequence of symbols that encodes a word in accordance with certain aspects disclosed herein. 
         FIG. 18  illustrates a transmitter and a receiver adapted to provide error detection in accordance with certain aspects disclosed herein. 
         FIG. 19  illustrates an example of data formats in a write transaction executed over a CCIe interface. 
         FIG. 20  illustrates an example of data formats in a read transaction executed over a CCIe interface. 
         FIG. 21  illustrates an example of word formats used in a write transaction executed over a CCIe interface in accordance with certain aspects disclosed herein. 
         FIG. 22  illustrates an example of word formats used in read transaction executed over a CCIe interface in accordance with certain aspects disclosed herein. 
         FIG. 23  is a block diagram illustrating an example of an apparatus employing a processing system that may be adapted according to certain aspects disclosed herein. 
         FIG. 24  is a flow chart of a data communications method that may be employed at a transmitter in accordance with certain aspects disclosed herein. 
         FIG. 25  is a diagram illustrating a first example of a hardware implementation for an apparatus used in an interface that provides symbol error detection according to certain aspects disclosed herein. 
         FIG. 26  is a flow chart of a data communications method that may be employed at a receiver in accordance with certain aspects disclosed herein. 
         FIG. 27  is a diagram illustrating a second example of a hardware implementation for an apparatus used in an interface that provides symbol error detection according to certain aspects disclosed herein. 
     
    
    
     DETAILED DESCRIPTION 
     In the following description, specific details are given to provide a thorough understanding of the embodiments. However, it will be understood by one of ordinary skill in the art that the embodiments may be practiced without these specific detail. For example, circuits may be shown in block diagrams in order not to obscure the embodiments in unnecessary detail. In other instances, well-known circuits, structures, and techniques may not be shown in detail in order not to obscure the embodiments. 
     Overview 
     Certain data transfer interfaces employ transition encoding, including 3-phase and N! multi-wire LVDS interfaces, and multi-wire single-ended interfaces including the I3C and CCIe interfaces. Transition encoding embeds clock information in signaling states transmuted over the interface. In certain instances, data is transcoded to transition numbers, where each transition number selects a next symbol to be transmitted after a current symbol. Each symbol may represent signaling state of the interface. For example, the transition number may represent an offset used to select between symbols in an ordered set of symbols that can be transmitted on the interface. By ensuring that consecutive symbols are different from one another, a change in signaling state of the interface occurs at each symbol boundary providing information used to generate a receive clock at the receiver. 
     Errors in signaling state that change a transmitted symbol S 1  to a received symbol Se 1  can cause a receiver to produce an incorrect transition number T 1 +e 1  associated with the transition between art immediately preceding symbol S 2  and the changed symbol Se 1 . T 1  represents the difference between S 2  and the correctly transmitted symbol S 1 , and e 1  is the value of an offset introduced by the signaling error. A second incorrect transition number T 0 +e 0  is associated with the changed symbol Se 1 , where T 0  represents the difference between the correctly transmitted symbol S 1  and a next symbol S 0 , with e 0  representing the value of the offset introduced by the signaling error. The values of e 1  and e 0  do not directly correspond to the error in signaling state, and the disassociation between data bit errors and signaling state errors can render conventional error detection techniques ineffective when applied to transition encoding interfaces. 
     According to certain aspects disclosed herein, reliable error detection is enabled in transition-encoded interfaces by providing an error detection constant (EDC). The EDC may include a fixed number of bits having a known, fixed value. The value of the EDC may have a zero value, in one example, and may be provided as the least significant bits (LSBs) of each word to be transmitted on the interface. Certain aspects relate to modification of data word formats to support various EDCs, including EDCs that are capable of detecting multi-symbol errors and correcting one or more symbol errors. 
     Example of a Device Employing Transition Encoding 
     According to certain aspects, a serial data link may be used to interconnect electronic devices that are subcomponents of an apparatus such as a cellular phone, a smart phone, a session initiation protocol (SIP) phone, a laptop, a notebook, a netbook, a smartbook, a personal digital assistant (PDA), a satellite radio, a global positioning system (GPS) device, a smart home device, intelligent lighting, a multimedia device, a video device, a digital audio player (e.g., MP3 player), a camera, a game console, an entertainment device, a vehicle component, a wearable computing device (e,g., a smart watch, a health or fitness tracker, eyewear, etc.), an appliance, a sensor, a security device, a vending machine, a smart meter, a drone, a multicopter, or any other similar functioning device. 
       FIG. 1  illustrates an example of an apparatus  100  that may employ a data communication bus. The apparatus  100  may include a processing circuit  102  having multiple circuits or devices  104 ,  106 ,  108  and/or  110 , which may be implemented in one or more ASICs and/or one or more system-on-chip (SoC) devices. In one example, the apparatus  100  may be a communication device and the processing circuit  102  may have an ASIC  104  that includes a processor  112 . The ASIC  104  may implement or function as a host or application processor. The apparatus  100  may include one or more peripheral devices  106 , one or more modems  110  and a transceiver  108  that enables the apparatus to communicate through an antenna  124  with a radio access network, a core access network, the Internet and/or another network. The configuration and location of the circuits or devices  104 ,  106 ,  108 ,  110  may vary between applications. 
     The circuits or devices  104 ,  106 ,  108 ,  110  may include a combination of sub-components. In one example, the ASIC  104  may include more than one processors  112 , on-board memory  114 , a bus interface circuit  116  and/or other logic circuits or functions. The processing circuit  102  may be controlled by an operating system that may provide an application programming interface (API) layer that enables the one or more processors  112  to execute software modules residing in the on-hoard memory  114  or other processor-readable storage  122  provided on the processing circuit  102 . The software modules may include instructions and data stored in the on-board memory  114  or processor-readable storage  122 . The ASIC  104  may access its on-board memory  114 , the processor-readable storage  122 , and/or storage external to the processing circuit  102 . The on-board memory  114 , the processor-readable storage  122  may include read-only memory (ROM) or random-access memory (RAM), electrically erasable programmable ROM (EEPROM), flash cards, or any memory device that can be used in processing systems and computing platforms. The processing circuit  102  may include, implement, or have access to a local database or other parameter storage that can maintain operational parameters and other information used to configure and operate the apparatus  100  and/or the processing circuit  102 . The local database may be implemented using registers, a database module, flash memory, magnetic media, EEPROM, soft or hard disk, or the like. The processing circuit  102  may also be operably coupled to external devices such as the antenna  124 , a display  126 , operator controls, such as switches or buttons  128 ,  130  and/or an integrated or external keypad  132 , among other components. A user interface module may be configured to operate with the display  126 , keypad  132 , etc. through a dedicated communication link or through one or more serial data interconnects. 
     The processing circuit  102  may provide one or more buses  118   a,    118   b,    118   c,    120  that enable certain devices  104 ,  106 , and/or  108  to communicate. In one example, the ASIC  104  may include a bus interface circuit  116  that includes a combination of circuits, counters, timers, control logic and other configurable circuits or modules. In one example, the bus interface circuit  116  may be configured to operate in accordance with communication specifications or protocols. The processing circuit  102  may include or control a power management function that configures and manages the operation of the apparatus  100 . 
       FIG. 2  illustrates certain aspects of an apparatus  200  connected to a communication link  220 , where the apparatus  200  may be embodied in one or more of a mobile device, a mobile telephone, a mobile computing system, a cellular telephone, a notebook computer, a tablet computing device, a media player, s gaming device, or the like. The apparatus  200  may include a plurality of IC devices  202  and  230  that exchange data and control information through a communication link  220 . The communication link  220  may be used to connect IC devices  202  and  230  that are located in close proximity to one another, or physically located in different parts of the apparatus  200 . In one example, the communication link  220  may be provided on a chip carrier, substrate or circuit board that carries the IC devices  202  and  230 . In another example, a first IC device  202  may be located in a keypad section of a flip-phone while a second IC device  230  may be located in a display section of the flip-phone. In another example, a portion of the communication link  220  may include a cable or optical connection. 
     The communication link  220  may include multiple channels  222 ,  224  and  226 . One or more channels  226  may be bidirectional, and may operate in half-duplex and/or full-duplex modes. One or more channels  222  and  224  may be unidirectional. The communication link  220  may be asymmetrical, providing higher bandwidth in one direction. In one example described herein, a first communication channel  222  may provide or be referred to as a forward link while a second communication channel  224  may provide or be referred to as a reverse link. The first IC device  202  may be designated as a host system or transmitter, while the second IC device  230  may be designated as a client system or receiver, even if both IC devices  202  and  230  are configured to transmit and receive on the communication channel  222 . In one example, a forward link may operate at a higher data rate when communicating data from a first IC device  202  to a second IC device  230 , while a reverse link may operate at a lower data rate when communicating data from the second IC device  230  to the first IC device  202 . 
     The IC devices  202  and  230  may each have a processor  206 ,  236 , and/or a processing and/or computing circuit, or other such device or circuit. In one example, the first IC device  202  may perform core functions of the apparatus  200 , including maintaining communications through an RE transceiver  204  and an antenna  214 , while the second IC device  230  may support a user interface that manages or operates a display controller  232 . The first IC device  202  or second IC device  230  may control operations of a camera or video input device using a camera controller  234 . Other features supported by one or more of the IC devices  202  and  230  may include a keyboard, a voice-recognition component, and other input or output devices. The display controller  232  may include circuits and software drivers that support displays such as a liquid crystal display (LCD) panel, touch-screen display, indicators and so on. The storage media  208  and  238  may include transitory and/or non-transitory storage devices adapted to maintain instructions and data used by respective processors  206  and  236 , and/or other components of the IC devices  202  and  230 . Communication between each processor  206 ,  236  and its corresponding storage media  208  and  238  and other modules and circuits may be facilitated by one or more bus  212  and  242 , respectively. 
     The reverse link (here, the second communication channel  224 ) may be operated in the same manner as the forward link (here, the first communication channel  222 ), and the first communication channel  222  and second communication channel  224  may be capable of transmitting at comparable speeds or at different speeds, where speed may be expressed as data transfer rate and/or clocking rates. The forward and reverse data rates may be substantially the same or differ by orders of magnitude, depending on the application. In some applications, a single bidirectional link (here, the third communication channel  226 ) may support communications between the first IC device  202  and the second IC device  230 . The first communication channel  222  and/or second communication channel  224  may be configurable to operate in a bidirectional mode when, for example, the forward and reverse links share the same physical connections and operate in a half duplex manner. In one example, the communication link  220  may be operated to communicate control, command and other information between the first IC, device  202  and the second IC device  230  in accordance with an industry or other standard. 
     In one example, forward and reverse links may be configured or adapted to support a wide video graphics array (WVGA) 80 frames per second LCD driver IC without a frame buffer, delivering pixel data at 810 Mbps for display refresh. In another example, forward and reverse links may be configured or adapted to enable communications between with dynamic random access memory (DRAM), such as double data rate synchronous dynamic random access memory (SDRAM). Encoding devices  210  and/or  230  can encode multiple bits per clock transition, and multiple sets of wires can be used to transmit and receive data from the SDRAM, control signals, address signals, and so on. 
     Forward and reverse channels may comply or be compatible with application-specific industry standards. In one example, certain MIPI Alliance standards define physical layer interfaces between an IC device  202  that includes an application processor and an IC device  230  that controls and/or supports the camera or display in a mobile device. The MIPI Alliance standards include specifications that govern the operational characteristics of products that comply with MIPI Alliance specifications for mobile devices. The MIPI Alliance standards may define interfaces that employ complimentary metal-oxide-semiconductor (CMOS) parallel busses. 
     In one example, the communication link  220  of  FIG. 2  may be implemented as a wired bus that includes a plurality of signal wires (denoted as N wires). The N wires may be configured to carry data encoded in symbols, where each symbol defines a signaling state of the N wires, and where clock information is embedded in a sequence of the symbols transmitted over the plurality of wires. 
     In one example, a two-wire serial bus may be operated in accordance with an I3C HDR protocol defined by the MIPI Alliance. In this example, binary signals are transmitted on each wire of the serial bus, and a two-bit symbol can represent the four possible signaling states of the serial bus. Each symbol occupies a symbol transmission interval. In transition encoding interfaces, signaling state changes between each pair of consecutive symbol transmission intervals allowing a clock signal to be reliably recovered based on transitions boundaries between symbol transmission intervals (symbol boundaries). Accordingly, three symbols are available at each symbol boundary for transmission in the next symbol transmission interval. The next symbol may be selected using a transition number, which is a numeric code that can have one of the values {0, 1, 2}. The transition number may be obtained by transcoding a portion of a binary word to obtain a ternary number that can be used as a transition number. The mapping scheme or algorithm used to select a next symbol based on the current symbol and the transition number may vary by application. The MIPI Alliance defines an algorithm used in an I3C HDR mode, but other algorithms may be used in different I3C HDR modes and/or in other types of transition-encoded interfaces. 
       FIG. 3  is a diagram illustrating one example of an N-wire transition-encoded interface  300  provided between two devices. At a transmitter  302 , a transeoder  306  may be used to encode data bits  304  and clock information in symbols to he transmitted over a set of AT wires  314  using N-factorial (N!) encoding. The clock information is derived from a transmit clock  312  and may be encoded in a sequence of symbols transmitted in  N C 2  differential signals over the N wires  314  by ensuring that a signaling state transition occurs on at least one of the  N C 2  signals between consecutive symbols. When N! encoding is used to drive the N wires  314 , each bit of a symbol is transmitted as a differential signal by one of a set of differential line drivers  310 , where the differential drivers in the set of differential line drivers  310  are coupled to different pairs of the N wires. The number of available combinations of wire pairs ( N C 2 ) determines the number of signals that can be transmitted over the N wires  314 . The number of data bits  304  that can be encoded in a symbol may be calculated based on the number of available signaling states available for each symbol transmission interval. 
     A termination impedance (typically resistive) couples each of the N wires  314  to a common center point  318  in a termination network  316 . It will be appreciated that the signaling states of the N wires  314  reflects a combination of the currents in the termination network  316  attributed to the differential line drivers  310  coupled to each wire. It will be further appreciated that the center point  318  is a null point, whereby the currents in the termination network  316  cancel each other at the center point. 
     The N! encoding scheme need not use a separate dock channel and/or non-return-to-zero decoding because at least one of the  N C 2  signals in the link transitions between consecutive symbols. Effectively, the transcoder  306  ensures that a transition occurs between each pair of symbols transmitted on the N wires  314  by producing a sequence of symbols in which each symbol is different from its immediate predecessor symbol. In the example depicted in  FIG. 3 , N=4 wires are provided, and the 4 wires can carry  4 C 2 =6 differential signals. The transcoder  306  may employ a mapping scheme to generate raw symbols for transmission on the N wires  314 . The transcoder  306  may map data bits  304  to a set of transition numbers. The transition numbers may then be used to select a raw symbol for transmission based on the value of the preceding symbol such that the selected raw symbol is different from the preceding raw symbol. In one example, a transition number may be used to lookup a data value corresponding to the second of the consecutive raw symbols with reference to the first of the consecutive raw symbols. At the receiver  320 , a transcoder  328  may employ a mapping to determine a transition number that characterizes a difference between a pair of consecutive raw symbols in a lookup table, for example. The transcoders  306 ,  328  operate on the basis that every consecutive pair of raw symbols includes two different symbols. 
     The transcoder  306  at the transmitter  302  may select between the N!−1 symbols that are available at every symbol transition. In one example, a 4! system provides 4!−1=23 signaling states for the next symbol to be transmitted at each symbol transition. The bit rate may be calculated as log 2 (available_states) per transmit clock cycle. In a system using double data rate (DDR) clocking, whereby symbol transitions occur at both the rising edge and falling edge of the transmit clock  312 , two symbols are transmitted per transmit clock cycle. The total available states in the transmit clock cycle for N=4 is (n!−1) 2 =(23) 2 =529 and the number of data bits  304  that can be transmitted per symbol may be calculated as dot log 2 (529)=9,047 bits. 
     The receiver  320  receives the sequence of symbols using a set of line receivers  322  where each receiver in the set of line receivers  322  determines differences in signaling states on one pair of the N wires  314 . Accordingly,  N C 2  receivers are used, where N represents the number of wires. The  N C 2  receivers produce a corresponding number of raw symbols as outputs. In the depicted N=4 wire example, the signals received on the four wires  314  are processed by 6 receivers ( 4 C 2 =6) to produce a state transition signal that is provided to a corresponding clock and data recovery (CDR) circuit  324  and deserializer  326 . The CDR circuit  324  may produce a receive clock signal  334  that can be used by the deserializer  326 . The receive clock signal  334  may be a DDR clock signal that can be used by external circuitry to receive data provided by the transcoder  328 . The transcoder  328  decodes a block of received symbols from the deserializer  326  by comparing each next symbol to its immediate predecessor. The transcoder  328  produces output data  330  corresponding to the data bits  304  provided to the transmitter  302 . 
     Transition Encoding Example 
       FIG. 4  is a block diagram illustrating a transmitter  400  and a receiver  420  configured according to certain aspects disclosed herein. The transmitter  400  and receiver  420  may he adapted for use with a variety of encoding techniques, including transition encoding used in I3C HDR protocols, N! and CCIe interfaces. The transmitter  400  includes a first converter  404  configured to convert data  402  into transition numbers  414 . The transition numbers  414  may be used to select a next symbol for transmission based on the value of a current symbol, where the next symbol is different from a current symbol. A second converter, such as the encoder  406 , receives the transition numbers and produces a sequence of symbols for transmission on the interface using suitably configured line drivers  408 . Since no pair of consecutive symbols includes two identical symbols, a transition of signaling state occurs in at least one of the signal wires  418  of the interface at every symbol transition. At the receiver  420 , a set of line receivers  426  provides raw symbols (SI)  436  to a CDR circuit  428  that extracts a receive clock  438  and provides captured symbols (S)  434  to a circuit that converts the captured symbols  434  to transition numbers  432 . The transition numbers may be decoded by a circuit  422  to provide output data  430 . 
     In the example of a 3! system, the transmitter  400  may be configured or adapted to transcode data  402  into quinary (base-5) transition numbers  414  represented by 3 bits. In the example of a two-wire serial bus, the transmitter  400  may be configured or adapted to transcode data  402  into ternary (base-3) transition numbers  414  represented by 2 bits. The transition numbers  414  may be encoded in a sequence of symbols  416  to be transmitted on the signal wires  418 . The data  402  provided to the transmitter  400  may be one or more words, each word having a fixed number of bits. The first converter  404 , which may be a transcoder, receives the data  402  and produces a sequence of transition numbers  414  for each data element. The sequence of transition numbers  414  may include a sufficient number of ternary numbers to encode a fixed number of bits of data, error detection and other information. The encoder  406  produces a sequence of symbols  416  that are transmitted through line drivers  408 . In one example, the line drivers  408  may include open-drain output transistors. In another example, the line drivers  408  may include push-pull drivers. The output sequence of symbols  416  generated by the encoder has a transition in the state of at least one of the signal wires  418  between each pair of consecutive symbols in the sequence of symbols  416  by ensuring that no pair of consecutive symbols include two identical symbols. The availability of a transition of state in at least one of the signal wires permits a receiver  420  to extract a receive clock  438  from the sequence of symbols  416 . 
       FIG. 5  is a drawing illustrating a simple example of an encoding scheme  500 . Other encoding schemes may be employed. In the illustrated example, the encoding scheme may be used by the encoder  406  configured to produce a sequence of symbols  416  for transmission on a two-wire CCIe interface. The encoding scheme  500  is also used by a transcoder  424  to extract data from symbols received from signals transmitted on the signal wires  418  of the interface. In the illustrated encoding scheme  500 , the use of two signal wires  418  permits definition of 4 basic symbols S: {0, 1, 2, 3}. Any two consecutive symbols in the sequence of symbols  416 ,  434  have different states, and the symbol sequences 0,0, 1,1, 2,2 and 3,3 are invalid combinations of consecutive symbols. Accordingly, only 3 valid symbol transitions are available at each symbol boundary, where the symbol boundary is determined by the transmit clock and represents the point at which a first symbol (Ps) terminates and a second symbol (Cs) begins. The first symbol may be referred to as the preceding or previous symbol  522  terminates and the second symbol may be referred to as the current symbol  524 . 
     According to certain aspects disclosed herein, the three available transitions are assigned a transition number (T)  526  for each previous symbol  522 . The value of T  526  can be represented by a ternary number. In one example, the value of transition number  526  is determined by assigning a symbol-ordering circle  502  for the encoding scheme. The symbol-ordering circle  502  allocates locations  504   a - 504   d  on the symbol-ordering circle  502  for the four possible symbols, and a direction of rotation  506  between the locations  504   a - 504   d.  In the depicted example, the direction of rotation  506  is clockwise. The transition number  526  may represent the separation between the valid current symbols  524  and the immediately preceding previous symbol  522 . Separation may be defined as the number of steps along the direction of rotation  506  on the symbol-ordering circle  502  required to reach the current symbol  524  from the previous symbol  522 . The number of steps can be expressed as a single digit base-3 number. It will he appreciated that a three-step difference between symbols can be represented as a 0 base-3 . The table  520  in  FIG. 5  summarizes an encoding scheme employing this approach. 
     At the transmitter  400 , the table  520  may be used to lookup a current symbol  524  to be transmitted, given knowledge of the previous symbol  522  and an input ternary number, which is used as a transition number  526 . At the receiver  420 , the table  520  may be used as a lookup to determine a transition number  526  that represents the transition between the previous symbol  522  and the current symbol  524 . The transition number  526  may be output as a ternary number. 
     The use of a transcoder that embeds clock information in a sequence of symbols can disassociate data  402  received for transmission by a transmitter  400  from the sequence of symbols  416  transmitted on signal wires  418 . Consequently, a received raw symbol  436  cannot be directly decoded to obtain the data  402  provided to the transmitter  400  without consideration of at least one previously transmitted symbol. This disassociation can render conventional error correction techniques ineffective. For example, a conventional system may append an error correction code (ECC) to data  402 , where the ECC may be a cyclic redundancy code (CRC) calculated from a predefined block size of data  402  or a packet length. The FCC may be used to identify and/or correct occurrences of errors during transmission in a conventional interface, where the errors may include one or more bit errors. 
     In an interface that uses transition encoding, symbol errors manifest in bursts of bit errors at the receiver. That is, multiple bit errors can be caused by a single symbol transmission error. In these circumstances, a CRC often exceeds Hamming distance and is not a practical solution for error detection. 
       FIG. 6  is a timing diagram  600  that illustrates the relationship between symbols  602  and transition numbers  604 , which may also be referred to herein as “transition symbols.” In this example, each data word is encoded in m symbols transmitted on the multi-wire interface. A word transmitted in m symbols may be decoded using the formula: 
     
       
         
           
             
               ∑ 
               
                 k 
                 = 
                 0 
               
               
                 m 
                 - 
                 1 
               
             
              
             
               
                 T 
                 k 
               
                
               
                 r 
                 k 
               
             
           
         
       
     
     where T k  is the transition number at the k th  iteration, and r is number of available symbols at each transition between symbols. For example, in a 3! interface where a self-transition is prohibited (to ensure that a receive clock can be reliably generated), r=5 states of the 6 defined states are available at each symbol transition. In various examples, the 3! interface may encode data in sequences of m=4 symbols or m=7 symbols. In a 4! interface, r=23 states of the 24 defined states are available at each symbol transition, and, the 4! interface may encode data in sequences of m=2 symbols. In a CCIe interface, r=3 states of the 4 defined states are available at each symbol and data words may be encoded in sequences of m=12 symbols. For a 3-wire single-ended interface, values of m=12 and r=7 may be used. For a 4-wire single-ended interface, values of m=10 and r=15 may be used. 
       FIG. 7  is a drawing  700  that illustrates transition number-to-symbol encoding for a 3! interface. In this example, there are 6 possible symbols, S: {0, 1, 2, 3,4, 5}, arranged around the symbol-ordering circle  702 . Clock information is embedded in sequences of symbols by ensuring that the same symbol does not appear in any two consecutive symbol intervals. In this example, r=5, and a transition number (T) may be assigned a different value for each type of transition  704 ,  706 ,  708 ,  710 ,  712 . The value of the transition number may indicate the location of a next symbol on the symbol-ordering circle  702  relative to the position of a current symbol on the symbol-ordering circle  702 . The transition number may take a value in the range 1-5. Since the current symbol cannot be the same as the previous symbol, the number of steps between the current and next symbols cannot be zero. 
     A transition number may be assigned in accordance with the formula: 
         T=Ps+ 1 ≦Cs?Cs −( Ps+ 1): Cs −( Ps+ 1)+6.
 
     Conversely, the current sequential symbol number (Cs) may be assigned according to: 
         Cs=Ps+ 1+ T&lt; 6? Ps+ 1+ T:Ps+ 1+ T− 6 ,    
     where Cs is the current symbol, and Ps is the previously received symbol. 
       FIG. 8  is a diagram that illustrates a generalized example  800  of symbol transition clocking transcoding. In this example  800 , an interface provides six possible signaling states per symbol transmitted on a multi-wire communication interface, with clock information embedded at each transition between consecutive symbols by ensuring that each pair of consecutively transmitted symbols includes two different symbols. Accordingly, 5 states are available at each transition between symbols. A data word is encoded by converting the bits of the data word to a transition number, which selects the next symbol to be transmitted based on the symbol being currently transmitted. In the example  800 , three sequential symbols  812 ,  814 ,  816  are transmitted over the multi-wire communication interface, where each symbol  812 ,  814 ,  816  defines one of the six signaling states of the multi-wire communication interface. Data and clock information are encoded in the transitions between consecutive pairs of the symbols  812 ,  814 ,  816 . The transitions may be represented as digits of transition numbers  808 ,  810 . Each digit of the transition number identifies a transition between a pair of consecutive symbols in the sequence of symbols, and in this context, the digits may also be referred to as transition numbers. As noted herein, for a sequence of m symbols data is encoded as: 
     
       
         
           
             data 
             = 
             
               
                 ∑ 
                 
                   k 
                   = 
                   0 
                 
                 
                   m 
                   - 
                   1 
                 
               
                
               
                 
                   T 
                   k 
                 
                  
                 
                   r 
                   k 
                 
               
             
           
         
       
     
     where it has a value between 0 and m−1. A first transition number (T k )  808  corresponds to the transition between a first symbol  812  (A) and a second symbol  814  (X), and a second transition number (T k−1 )  810  corresponds to the transition between the second symbol  814  (X) and a third symbol  816  (B). Here, the first symbol  812  may encode the most significant bits of a data word. 
     In one example, a multi-bit data word may be converted to a sequence of in transition numbers. Each transition number may be expressed using a ternary number, quaternary number, quinary number, senary number, or using some other numeral system that can represent r transitions. That is, the numeral system may be a base r system providing numbers that can span the range 0 to r−1. Each transition number may select a next symbol for transmission based on the current symbol being transmitted. The next symbol is selected from symbols that are different from the current symbol in order to ensure a signaling state transition occurs in order to embed clock information in the sequence of symbols  802 . That is, the transmission of two different symbols in a consecutive pair of symbols results in a change in signaling state of at least one wire of a multi-wire interface, and a receiver can generate a receive clock based on the changes detected in signaling state between consecutive symbols. 
     The symbol-ordering circle  806  illustrates one method of selecting a next symbol in the example  800 . Here, the transition number may be expressed as a quinary number (base-5), with possible values {0, 1, 2, 3, 4}. For each of six possible symbols  804   a - 804   f,  one of six signaling states is transmitted on the multi-wire communication interface. The six symbols  804   a - 804   f  are arranged in different positions around the symbol-ordering circle  806 . Given a current symbol location on the symbol-ordering circle  806  a transition number T may be encoded by selecting, as a next symbol, the symbol located T clockwise steps on the symbol-ordering circle  806 . In one example, when the current symbol is Symbol- 0   804   a,  a transition number value of T=1 selects Symbol- 1   804   b  as the next symbol, a transition number value of T=2 selects Symbol- 2   804   c  as the next symbol, a transition number value of T=3 selects Symbol- 3   804   c  as the next symbol, and a transition number value of T=4 selects Symbol- 4   804   d  as the next symbol. A transition number value of T=0 may cause a rollover in that the transition number selects the symbol  5  clockwise steps (or 1 counterclockwise steps) from the current symbol (Symbol- 0   804   a ), thereby selecting Symbol- 5   804   f  as the next symbol. 
     In the example of the transmitted sequence of symbols  802 , the first symbol  812  in the sequence of symbols  802  may correspond to Symbol- 1   804   b.  Input data may be processed to produce the first transition number  808  with a value of T k =2, and the second transition number  810  with a value of T k−1 =1. The second symbol  814  may be determined to be Symbol- 3   804   d  based on the value of T k  and the third symbol  816  may be determined to be Symbol- 4   804   e  based on the value of T k−1 . 
     At a receiver, the symbol-ordering circle  806  may be used to determine a transition number for each transition between consecutive symbols  812 ,  814 , and/or  816 . In one example, the receiver extracts a receive clock based on the occurrence of changes in signaling state between consecutive symbols  812 ,  814 , and/or  816 . The receiver may then capture the symbols  812 ,  814 ,  816  from the multi-wire interface and determine a transition number representing the transition between each pair of consecutive symbols  812 ,  814 , and/or  816 . In one example, the transition number may be determined by calculating the number of steps on the symbol-ordering circle  806  between the pair of consecutive symbols  812 ,  814 . 
     Error Detection in a Transition Encoding Interface 
     According to certain aspects disclosed herein, reliable error detection may be implemented in a transition-encoded interface using an EDC added to data to be transmitted over the transition-encoded interface. The EDC may include a predefined number of bits, where the EDC has a known, fixed value. In one example, the EDC has a zero value when transmitted. In some instances, the EDC is provided as the least significant bits (LSBs) of each word to be transmitted on the interface. The form and structure of the EDC word may be selected such that a single signaling state error affecting a word causes the EDC decoded at the receiver to have a value that is different from the fixed value (e.g., a non-zero value). 
       FIG. 9  illustrates an example  900  of the effect of a single error affecting a transition-encoded interface. In the example, a data word  912  is provided for transmission over the interface. EDC  914  is appended to the data word  912  to produce a transmission word  902  that is input to and encoder. The transmission word  902  is transmitted in a sequence of symbols  910 , where the sequence of symbols  910  includes  12  symbols. The sequence of symbols  910  is transmitted over a two-wire interface configured for CCIe operation and received at a receiver in a stream of symbols  904 . In transmission, a signaling error occurs such that an originally-transmitted symbol  916  is modified and received as an erroneous symbol  918 . A stream of transition numbers  906  corresponding to the received stream of symbols  904  includes transition numbers  920 ,  922  that include error offsets. A first transition number  920  represents the difference between the preceding symbol and the erroneous symbol  918 , and a second transition number  922  represents the difference between the erroneous symbol  918  and the next symbol transmitted after the affected symbol. 
     The size, location, and structure of the EDC  914  may be selected such that the occurrence of a single symbol error produces an EDC  926  at the receiver that is different than the transmitted EDC  914 . In one example, the EDC  914  includes multiple bits and may be set to a zero value. In the example of a CCIe interface, the EDC  914  may have three bits. 
       FIG. 10  is a diagram that illustrates an example in which a sequence of symbols  1002  transmitted over a multi-wire communication interface is affected by a single symbol error  1018  resulting in the capture of an erroneous symbol  1014  in the received sequence of symbols  1004 . The transmitted sequence of symbols  1002  includes a first symbol  1008  (the A symbol), a second symbol (the X symbol  1010 ) and a third symbol  1012  (the B symbol). In the received sequence of symbols  1004 , the first symbol  1008  and the third symbol  1012  are correctly received, while the second symbol  1014  is modified by the symbol error  1018  (displacement e) and is received as an erroneous symbol (the X′ symbol  1014 ). 
     The occurrences of a single symbol error  1018  results in two transition number errors. The first incorrect transition number  1020  represents the transition between the correctly received first symbol  1008  and the X′ Symbol  1014 . The second incorrect transition number  1022  represents the transition between the X′ Symbol  1014  and the correctly received third symbol  1012 . The first incorrect transition number  1020  may be expressed as T k +e k , where T k  is the first correct transition number  1016  corresponding to a transition between the first symbol  1008  and the X Symbol  1010 , and e k  is the value of the error created in the first incorrect transition number  1020  relative to the first correct transition number  1016 . The second incorrect transition number  1022  may be expressed as T k−1 +e k−1 , where T k−1  is the second correct transition number  1024  corresponding to the transition between the X Symbol  1010  and the third symbol  1012 , and e k−1  is the value of the error created in the second incorrect transition number  1022  relative to the first correct transition number  1024 . 
     The effect of the single symbol error  1018  is illustrated in the decoding transition circle  1006 . The first symbol  1008 , which corresponds to Symbol- 1 , is initially received from the multi-wire interface. The next symbol is incorrectly captured as the X′ Symbol  1014  due to error. The X′ Symbol  1014  may correspond to Symbol- 0 . The third symbol  1012 , which corresponds to Symbol- 4 , is then received from the multi-wire interface. In this example, the most significant symbol is transmitted first, and: 
         e=T   k =2,  T   k−1 =1. 
         T   k+e= 2+3=5=0 base5 , and  e   k =−2
 
         T   k−1   −e= 1−3=−2=4 base5 , and e k−1 =−3.
 
     Each data word may be represented by a sequence of transition numbers: 
       { T   0 , T 1   , . . . , T   m−1 }. 
     The displacement error e represents the difference between the transmitted X symbol  1010  and the received X′ Symbol  1014 , which may correspond to a number of steps in the decoding transition circle  1006 . The value of e is not necessarily equal in value to e k  due to roll over in the number system used to express transition numbers. For example, a transition number with a value of 3 may represent the difference between the transmitted X symbol  1014  and the received X′ Symbol  1014  the first correct transition number  1016  on the decoding transition circle  1006  caused by the displacement error e, while the value of e k  has a value of −2. 
     For two consecutive symbol transitions: 
       Bits= T   k   r   k   +T   k−1   r   k−1    
     The result of a single error affecting two consecutive symbols may be expressed as: 
     
       
         
           
             
               
                 
                   
                     
                       Bits 
                       &#39; 
                     
                     = 
                     
                       
                         
                           ( 
                           
                             
                               T 
                               k 
                             
                             + 
                             
                               e 
                               k 
                             
                           
                           ) 
                         
                          
                         
                           r 
                           k 
                         
                       
                       + 
                       
                         
                           ( 
                           
                             
                               T 
                               
                                 k 
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                                 1 
                               
                             
                             - 
                             
                               e 
                               
                                 k 
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                                 1 
                               
                             
                           
                           ) 
                         
                          
                         
                           r 
                           
                             k 
                             - 
                             1 
                           
                         
                       
                     
                   
                 
               
               
                 
                   
                     = 
                     
                       
                         ( 
                         
                           
                             
                               T 
                               k 
                             
                              
                             
                               r 
                               k 
                             
                           
                           + 
                           
                             
                               T 
                               
                                 k 
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                              
                             
                               r 
                               
                                 k 
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                                 1 
                               
                             
                           
                         
                         ) 
                       
                       + 
                       
                         
                           ( 
                           
                             
                               
                                 e 
                                 k 
                               
                                
                               r 
                             
                             - 
                             
                               e 
                               
                                 k 
                                 - 
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                          
                         
                           r 
                           
                             k 
                             - 
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     where: 
     (e k r−e k−1 )r k−1  may be referred to as the error effect, 
     (e k r−e k−1 ) may be referred to as the error coefficient, and 
     r k−1  may be referred to as the base power. 
     According to certain aspects, a transition-encoded interface may be configured such that r is an odd number. When r is an odd number, it follows that r k−1  is also an odd number (LSB is non-zero). Accordingly, the value of (e k r−e k−1 ) determines the number of LSBs required for an EDC.  FIG. 11  provides a listing of e (where n lies in the range 0 to 15) when r=3 and 5. The first table  1100  may relate to a CCIe interface, where T=3 transitions are available at each symbol interval. In each instance, the LSB  1104  of the base power is set to ‘1.’ The second example  1102  may relate to a 3-wire 3! interface, where r=5 transitions are available at each symbol interval (6 possible symbols). In each instance, the LSB  1206  of the base power is set to ‘1.’ 
       FIG. 12  is a table  1200  that tabulates error coefficients and illustrates error coefficient when a symbol error does not involve repetition of a symbol in consecutive symbol intervals, which would cause a clock miss. |e k | is always smaller than r. That is: 
       1≦| e   k   |≦r− 1 ,  
 
       1≦| e   k−1   |≦r− 1 .  
 
     Since the least value of |e k | is 1, the least value for |e k r| is r. The largest value of |e k−1  is r−1. The error coefficient (e k r−e k−1 ) is never zero when a single symbol error is present. 
       FIG. 13  illustrates an example  1300  of calculation and tabulation of the longest non-zero LSB portion in an error coefficient. Here, the power of 2 LSBs of (e k r−e k−1 ) is the longest when both |e k | and |e k−1 | are longest power of 2 ( 2   n ), and e k =e k−1 . The Longest power of 2 LSBs of error coefficient determines the size of the “error detection constant LSBs.” 
     Certain aspects disclosed herein may be applied to interfaces which do not use transition encoding to embed clock information in a sequence of symbols. In some instances, data may be transcoded to a numbering system that has an odd base. For example, data may be transcoded to a numbering system such as a ternary numbering system, a quinary numbering system, a septenary numbering system, etc. 
       FIG. 14  illustrates two examples  1400 ,  1420  of cases in which a single symbol error results in an error in a single transition number  1408 ,  1426 . In the first example  1400 , a signaling error affects the last transmitted symbol  1402  in a preceding sequence of symbols. The signaling error causes a receiver to detect a modified symbol  1404  as the last-received symbol in the preceding sequence of symbols. The error may introduce an offset in the transition number  1406  that represents the difference between the last transmuted symbol  1402  in a preceding sequence of symbols and the first symbol of a current sequence of symbols. In the first example  1400 , the effect of the error may be expressed as: e m−1 r m−1 , where the error coefficient is e m−1  and the base power is r m−1 . 
     In the second example  1420 , a signaling error affects the last transmitted symbol  1422  in a current sequence of symbols. The signaling error causes a receiver to detect a modified symbol  1424  as the last-received symbol in the current sequence of symbols. The error may introduce an offset in the transition number  1426  that represents the difference between the last transmitted symbol  1422  in the current sequence of symbols and the first symbol of a next sequence of symbols. In the first example  1400 , the effect of the error may be expressed as e 0 . 
     Table 1 lists the number of LSBs in an EDC that can detect a single symbol error in a multi-wire interface that uses transition encoding. 
     
       
         
           
               
               
               
               
             
               
                   
                 TABLE 1 
               
               
                   
                   
               
               
                   
                 r 
                 EDC length (bits) 
                 Example 
               
               
                   
                   
               
             
            
               
                   
               
            
           
           
               
               
               
               
            
               
                   
                 3 
                 3 
                 2-wire single-ended (e.g. I3C, CCIe) 
               
               
                   
                 5 
                 5 
                 3-wire multi-level differential (3!) 
               
               
                   
                 7 
                 6 
                 3-wire single ended 
               
               
                   
                 9 
                 7 
               
               
                   
                 11 
                 5 
               
               
                   
                 13 
                 6 
               
               
                   
                 15 
                 8 
                 4-wire single-ended 
               
               
                   
                 17 
                 9 
               
               
                   
                 19 
                 8 
               
               
                   
                 21 
                 7 
               
               
                   
                 23 
                 6 
                 4-wire multi-level differential (4!) 
               
               
                   
                   
               
            
           
         
       
     
     The cases illustrated in  FIG. 14  do not affect the maximum number of LSBs required in an EDC to permit detection of a single symbol error. 
     Detection of Multiple Symbol Errors Per Word 
       FIG. 15  is a timing diagram  1500  that illustrates a first example of signaling errors that affect two symbols  1504 ,  1506  in a sequence of symbols  1502  that encodes a single data word.  FIG. 15  relates to an example in which signaling errors affect two non-consecutive symbols. The errors in symbols  1504 ,  1506  result in corresponding pairs of transition errors  1508 ,  1510 . These transition errors result in erroneous transition numbers  1512 ,  1514 ,  1516 ,  1518 . The error effect attributable to the first affected symbol  1504  may be stated as (e k r−e k−1 )r k−1 , while the error effect attributable to the first affected symbol  1504  may be stated as (e j r−e j−1 )r j−1 . Multiple symbol errors can be detected provided if the total effect of the error 
       ( e   k   r−e   k−1 ) r   k−1 +( e   k   r−e   k−1 ) r   k−1    
     always modifies an EDC that has a predetermined length and value. 
       FIG. 16  is a timing diagram  1600  that illustrates a second example of signaling errors that affect two consecutive symbols  1604 ,  1606  in a sequence of symbols  1602  that encodes a single word. The errors in the consecutive symbols  1604 ,  1606  result in transition errors  1608  that cause the generation of three erroneous transition numbers  1610 ,  1612 ,  1614 . The error effect attributable to the affected symbols  1504 ,  1506  may be stated as (e k r 2 −e k−1 +e k−2 )r k−2 . The error effect attributable to errors affecting consecutive symbols  1604 ,  1606  can be detected with a shorter EDC than errors in non-consecutive symbols  1504 ,  1506  in receivers adapted in accordance with certain aspects disclosed herein. 
       FIG. 17  is a table  1700  that illustrates the number of bits of an EDC used for various values of r (available transitions per symbol boundary) and m (number of symbols used to encode a data element). The size of an EDC used for detecting two symbol errors varies with the value of m. The first row (shaded) of the table  1700  corresponds to an EDC used to detect a single symbol error. 
     According to certain aspects disclosed herein, a receiver can be configured to detect two symbol errors in a sequence of symbols representing a data word, when an EDC of sufficient length is transmitted with the data word. The length of the EDC may be determined based on the number of symbols used to encode a data word and the number of transitions available at the boundary between a pair of consecutively transmitted symbols. 
     Symbol slip error caused by clock miss or extra clock may not be detected by an error detection constant. However, the majority of these types of errors can be detected by higher protocol layers, at the next word, and/or using a state machine at the receiver device. 
       FIG. 18  illustrates a transmitter  1800  and a receiver  1840  coupled by an N-wire serial bus  1820 , where each transmission over the serial bus  1820  includes an EDC (error detection constant) provided in accordance with certain aspects disclosed herein. The transmitter  1800  may include an EDC insertion circuit  1804  adapted to append an EDC to a data word  1802 , where the data word  1802  is provided as an input to the transmitter  1800 . The EDC insertion circuit  1804  may provide an enhanced data word  1814  to a first encoder  1806  that is configured to convert the enhanced data word  1814  into a transition number  1816 . The transmitter  1800  may include a second encoder  1808  configured to generate a sequence of symbols  1818  from the transition number  1816 . Each symbol in the sequence of symbols  1818  may be generated using a digit of the transition number  1816  and a preceding symbol in the sequence of symbols  1818 . A communications transceiver  1810  may be configured to transmit the sequence of symbols  1818  on the serial bus  1820 , in some embodiments, clock information may be embedded in transitions between consecutive symbols in the sequence of symbols  1818 . 
     The EDC may have a length and a known, fixed value selected to enable the receiver  1840  to detect a symbol error in the sequence of symbols  1818  corresponding to the data word  1802 . In some instances, the length and the known, fixed value of the EDC may be selected to enable the receiver  1840  to detect transmission errors affecting multiple symbols in the sequence of symbols  1818 . The EDC insertion circuit  1804  may append the EDC as a predefined and/or fixed number of least significant bits. The number of least significant bits may be determined based on a total number of states per symbol available for encoding data transmissions on the serial bus  1820  and/or a total number of symbols used to encode the data word  1802  and the EDC. 
     In one example, the serial bus  1820  has N single-ended connectors, and the total number of states per symbol available for encoding data transmissions is 2N−x, where x is at least 1. In another example, the serial bus  1820  has N multi-level differential connectors, and the total number of states per symbol available for encoding data transmissions is N!−x, where x is at least 1. In another example, the total number of states available at each transition is 3, and the EDC includes 8 bits. In another example, the total number of states available at each transition is 3, the sequence of symbols includes 17 or more symbols, and the EDC includes 9 bits. In another example, the total number of states available at each transition is 5, and the EDC includes 10 bits. In another example, the total number of states available at each transition is 5, the sequence of symbols includes 8 or more symbols, and the EDC includes 11 bits. 
     The receiver  1840  may include a communications transceiver  1846  that can be configured to receive a sequence of raw symbols  1856  from the serial bus  1820 . In some instances, the receiver  1840  may include a CDR circuit  1848  that provides a receive clock signal  1858  and a sequence of captured symbols  1854  to a first decoder  1844 . The first decoder  1844  converts the sequence of captured symbols  1854  to a transition number  1852 . Each digit of the transition number  1852  may represent a transition between two consecutive symbols in the sequence of captured symbols  1854 . The receiver  1840  may include a second decoder  1842  that is adapted to convert the transition number  1852  to one or more words  1850 ,  1862 . In the illustrated example, an EDC word  1862  may be provided to an error detection circuit  1864 , which produces a signal  1860  indicating whether an error occurred during transmission. The error detection circuit  1864  may include combinational logic and/or comparators configured to compare the EDC word  1862  to an expected, fixed value. An error may be identified when the EDC word  1862  does not match the expected, fixed value. In one example, the known, fixed value is zero, and each bit of the EDC word  1862  is expected to be a ‘0’ bit. A portion of the bits decoded by the second decoder  1842  may be provided as the output data word  1850 . In some examples, the receive clock signal  1858  may be derived from clock information embedded in transitions between consecutive symbols in the sequence of raw symbols  1856 . 
     Example of Word, Address and SID Structures in Transition-Encoded Interfaces 
     Data structures may be defined for transition-encoded interfaces without regard to reliable error detection and correction. For example, a structure may be defined that supports different types of transmission, including data, address and device identifiers, including unique slave identifiers (SIDs). A structure may be designed to support transmission of control information, signaling and commands. The structure may take advantage of additional bits provided when binary data is mapped to transition numbers. For example, an interface that provides a symbol transition that encodes a ternary number involves a mapping to binary data that can yield control bits in additional to the desired data field. These additional bits result in an expanded transmission word format. 
     According to certain aspects disclosed herein, versatile error detection and correction capabilities may be provided in a transition-encoded interface using a word structure that can be modified to provide a desired or required level of protection against symbol errors. Reliable error detection and error correction may be obtained in a transition-encoded interface using an EDC added to data to be transmitted over the transition-encoded interface. The EDC is provided at the end of a word to be encoded and transmitted, such that the EDC provides bits to he encoded in the last symbols to be transmitted. The size of the EDC may be determinative of the number of symbol errors that can be detected and the number of symbol errors that can be reversed. In some conventional transition-encoding schemes, the organization of data and control bits within a word to be transmitted may be incompatible with certain types of EDCs. In one example, the EDC has a zero value in the word to be transmitted, and the EDC is provided as the last bits of each word to be transmitted on the interface. The form and structure of the EDC word may be selected such that a single signaling state error affecting a word causes the EDC decoded at the receiver to have a value that is different from the fixed value. 
       FIG. 19  illustrates an example of data formats in a write transaction  1900  executed over a CCIe interface. A master device may transmit a slave identifier (SID  1902 ) on the CCIe interface, where a device configured with the transmitted SID may respond to commands subsequently transmitted by the master device. The master device may then transmit a multi-word address including the A 1  address word  1904 , followed by a write bit or command  1912  and multiple words of data, including the D 1  data word  1906  to be written to the specified address or a sequence of addresses commencing at the specified address. The transaction includes start bits  1908 , bits  1910 ,  194  that indicate that the address or data is continued, and a transaction end indicator  1916 . 
     The SID  1902  commences with a 0 value bit  1928 , and includes 16 bits, provided as a 14-bit field  1920  and 2 most significant bits (MSBs  1924 ), separated by a 2-bit control code  1922 . A one-bit EDC  1926  may be provided. The A 1  address word  1904  commences with a 0 value bit  1938 , and includes 16 bits, provided as a 14-bit field  1930  and 2 most significant bits (MSBs  1934 ), separated by a 2-bit control code  1932 . A one-bit EDC  1936  may be provided. The D 1  data word  1906  commences with a 0 value  1948 , and includes 16 bits, provided as a 14-bit field  1940  and 2 most significant bits (MSBs  1944 ), separated by a 2-bit control code  1942 . A one-bit EDC  1946  may be provided. In each of the SID  1902 , A 1  address word  1904 , and the D 1  data word  1906 , a 3-bit EDC, may be transmitted if the MSBs  1924 ,  1934  and  1944  are repurposed for error detection or correction. 
       FIG. 20  illustrates an example of data formats in a read transaction  2000  executed over a CCIe interface. A master device may transmit a slave identifier on the CCIe interface, where a device configured with the transmitted SID may respond to commands subsequently transmitted by the master device. The master device may then transmit a multi-word address, followed by a read bit or command  2006 . Next transmitted is a read specification word (RS word  2002 ). The slave device responds by transmitting the number of data words specified by the RS word  2002 , which are read from the specified address and/or successive addresses, where the data words include the D 0  data word  2004 . 
     The RS word  2002  commences with a 0 value bit  2028 , and includes 14 bits, provided as a 14-bit field  2020  followed by a 2-bit control code  2022  and a three-bit EDC  2024 . The D 0  data word  2004  commences with a 0 value bit  2038 , and includes 16 bits, provided as a 14-bit field  2030  and 2 most significant bits (MSBs  2034 ), separated by a 2-bit control code  2032 . A one-bit EDC  2036  may be provided. The D 0  data word  2004  may be transmitted as a 14-bit word when a 3-bit EDC is transmitted, and when the MSBs  2034  are repurposed for error detection or correction. 
     In the examples illustrated in  FIGS. 19 and 20 , data fields  1920 ,  1930 ,  1940 ,  2020  and  2030  are arranged such that the most significant bit is transmitted first and the least significant bit is transmitted last. Furthermore, a control code  1922 ,  1932 ,  1942  and  2032  is transmitted between the 14-bit data fields  1920 ,  1930 ,  1940  and  2030  and fields  1924 ,  1934 ,  1944  and  2034  carrying most significant bits. In these example, the presence of the control codes  1922 ,  1932 ,  1942 ,  2032  and bit orientation of the data fields  1920 ,  1930 ,  1940 ,  2030  present difficulties in providing EDCs that have size greater than 3 bits, where the EDC bits are the bits encoded in the last transmitted symbols that encode the word. 
     Improved Data, Address and Control Word Structures 
     According to certain aspects disclosed herein, the structure of certain data, address and control words may be adapted to provide versatile error correction and detection in transition-encoded interfaces. In one example, the 2-bit control codes  1922 ,  1932 ,  1942 ,  2022 ,  2032  may be encoded among the most significant bits of a word that carries a data field. The bit order of an SID, address or data carried in the data field may be reversed with respect to the bit order of the word, such that most significant bits of the SID, address or data can be repurposed for use in an EDC. In one example, the EDC is provided in the word in the lower significant bits adjacent to the most significant bits of the SID, address or data. A one bit EDC may be transmitted with a 16-bit SID, address or data. Other-sized EDCs may be accommodated by reducing the bit-size of the SID, address or data. 
     According to certain aspects, the size of the EDC can be flexibly defined without impacting the least significant bits of the data, address or control words or the 2-bit control code. For basic error detection can be obtained using a 1-bit EDC with 16-bit data. When one symbol error detection is required, a 3-bit EDC may be transmitted with the data, address or control word limited to 14 bits per word. When two symbol error detection or one symbol error correction is required, an 8-bit EDC may be transmitted with data, address or control word that are limited to 9 bits per word. 
       FIG. 21  illustrates an example of data formats in a write transaction  2100  executed over a CCIe interface using word formats according to certain aspects disclosed herein. In the example, each word  2102 ,  2104 ,  2106  includes 20 bits, with EDCs  2124 ,  2134 ,  2144  occupying the least significant bits of the word  2102 ,  2104 ,  2106 . 
     A master device may transmit a slave identifier (SID) on the CCIe interface, where a device configured with the transmitted SID may respond to commands subsequently transmitted by the master device. The master device may then transmit a multi-word address including the A 1  address word, followed by multiple words of data, including the D 1  data word to be written to the specified address or a sequence of addresses commencing at the specified address. 
     In the example, the most significant bit (bit [19]) of the word  2102  carrying the SID has a ‘0’ value bit  2128 , with the control code  2122  provided in the next most significant bits (bit [18:17]). In the example, a  16 -bit SID field  2120  is provided such that the order of bits in the SID field  2120  is flipped with respect to the order of bit assignments in the word  2102  carrying the SID. That is, the least significant bit of the SID is carried at the most significant bit assigned in the word  2102  for the SID field  2120 . In the example, a one-bit EDC  2124  may be provided at the least significant bit position of the word  2102 . 
     In the example, the most significant bit (bit [19]) of the word  2104  carrying the A 1  address has a ‘0’ value bit  2138 , with the control code  2132  provided in the next most significant bits (bit [18:17]). In the example, a 16-bit A 1  address field  2130  is provided such that the order of bits in the A 1  field  2130  is flipped with respect to the order of bit assignments in the word  2104  carrying the A 1  address field  2130 . That is, the least significant bit of the A 1  address is carried at the most significant bit assigned in the word  2104  for the A 1  address field  2130 . In the example, a one-bit EDC  2134  may be provided at the least significant bit position of the word  2104 . 
     In the example, the most significant bit (bit [19]) of the word  2106  carrying the D 1  data has a ‘0’ value bit  2148 , with the control code  2142  provided in the next most significant bits (bit [18:17]). In the example, a 16-bit D 1  field  2140  is provided such that the order of bits in the D 1  field  2140  is flipped with respect to the order of bit assignments in the word  2106  carrying the D 1  field  2140 . That is, the least significant bit of the D 1  data is carried at the most significant bit assigned in the word  2106  for the D 1  field  2140 . In the example, a one-bit EDC  2144  may be provided at the least significant bit position of the word  2106 . 
     In each word  2102 ,  2104  and  2106  the size of the EDC  2124 ,  2134 ,  2144  may be varied by reducing the number of bits commencing with the MSBs of the SID, address or data words. Freeing up the MSBs results in an increase in the number of available LSBs in the corresponding word  2102 ,  2104  or  2106  that can be added to the EDC  2124 ,  2134 ,  2144 . 
       FIG. 22  illustrates an example of data formats in a read transaction  2200  executed over a CCIe interface using word formats according to certain aspects disclosed herein. A master device may transmit a slave identifier on the CCIe interface, where a device configured with the transmitted SID may respond to commands subsequently transmitted by the master device. The master device may then transmit a multi-word address, followed by a read bit or command  2206 . Next transmitted is a word  2202  carrying a read specification value (RS value). The slave device responds by transmitting the number of data words specified by the RS value, which are read from the specified address and/or successive addresses, where the data words include the D 0  data word  2204 . 
     In the example, the most significant bit (bit [19]) of the word  2202  carrying the RS value has a ‘0’ value bit  2228 , with the control code  2222  provided in the next most significant bits (bit [18:17]). In the example, a 14-bit RS field  2220  is provided such that the order of bits in the RS field  2220  is flipped with respect to the order of bit assignments in the word  2202  carrying the RS value. That is, the least significant bit of the RS value is carried at the most significant bit assigned in the word  2202  for the RS field  2220 . In the example, a three-bit EDC  2224  may be provided at the least significant bit position of the word  2202 . 
     In the example, the most significant bit (bit [19]) of the word  2204  carrying the D 0  data has a ‘0’ value bit  2238 , with the control code  2232  provided in the next most significant bits (bit [18:17]). In the example, a 16-bit D 0  field  2230  is provided such that the order of bits in the D 0  field  2230  is flipped with respect to the order of bit assignments in the word  2204  carrying the D 0  field  2230 . That is, the least significant bit of the D 0  data is carried at the most significant bit assigned in the word  2204  for the field  2230 , in the example, a one-bit EDC  2234  may be provided at the least significant bit position of the word  2204 . 
     The size of the EDC  2224 ,  2234  may be varied by reducing the number of bits commencing with the MSBs of the RS value or D 0  data. Freeing up the MSBs results in an increase in the number of available LSBs in the corresponding word  2202  or  2204  that can be added to the EDC  2224 ,  2234 . In one example, 14-bit D 0  data may be transmitted when a 3-bit EDC  2234  is transmitted. 
     Examples of Processing Circuits and Methods 
       FIG. 23  is a conceptual diagram  2300  illustrating a simplified example of a hardware implementation for an apparatus employing a processing circuit  2302  that may be configured to perform one or more functions disclosed herein. In accordance with various aspects of the disclosure, an element, or any portion of an element, or any combination of elements as disclosed herein may be implemented using the processing circuit  2302 . The processing circuit  2302  may include one or more processors  2304  that are controlled by some combination of hardware and software modules. Examples of processors  2304  include microprocessors, microcontrollers, digital signal processors (DSPs), field programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, sequences, gated logic, discrete hardware circuits, and other suitable hardware configured to perform the various functionality described throughout this disclosure. The one or more processors  2304  may include specialized processors that perform specific functions, and that may be configured, augmented or controlled by one of the software modules  2316 . The one or more processors  2304  may be configured through a combination of software modules  2316  loaded during initialization, and further configured by loading or unloading one or more software modules  2316  during operation. 
     In the illustrated example, the processing circuit  2302  may be implemented with a bus architecture, represented generally by the bus  2310 . The bus  2310  may include any number of interconnecting buses and bridges depending on the specific application of the processing circuit  2302  and the overall design constraints. The bus  2310  links together various circuits including the one or more processors  2304 , and storage  2306 . Storage  2306  may include memory devices and mass storage devices, and may be referred to herein as computer-readable media and/or processor-readable media. The bus  2310  may also link various other circuits such as timing sources, timers, peripherals, voltage regulators, and power management circuits. A bus interface  2308  may provide an interface between the bus  2310  and one or more transceivers  2312 . A transceiver  2312  may be provided for each networking technology supported by the processing circuit. In some instances, multiple networking technologies may share some or all of the circuitry or processing modules found in a transceiver  2312 . Each transceiver  2312  provides a means for communicating with various other apparatus over a transmission medium. Depending upon the nature of the apparatus, a user interface  2318  (e.g., keypad, display, touch interface, speaker, microphone, joystick) may also be provided, and may be communicatively coupled to the bus  2310  directly or through the bus interface  2308 . 
     A processor  2304  may be responsible for managing the bus  2310  and for general processing that may include the execution of software stored in a computer-readable medium that may include the storage  2306 . In this respect, the processing circuit  2302 , including the processor  2304 , may be used to implement any of the methods, functions and techniques disclosed herein. The storage  2306  may be used for storing data that is manipulated by the processor  2304  when executing software, and the software may be configured to implement any one of the methods disclosed herein. 
     One or more processors  2304  in the processing circuit  2302  may execute software. Software shall be construed broadly to mean instructions, instruction sets, code, code segments, program code, programs, subprograms, software modules, applications, software applications, software packages, routines, subroutines, objects, executables, threads of execution, procedures, functions, algorithms, etc., whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise. The software may reside in computer-readable form in the storage  2306  or in an external computer readable medium. The external computer-readable medium and/or storage  2306  may include a non-transitory computer-readable medium. A non-transitory computer-readable medium includes, by way of example, a magnetic storage device (e.g., hard disk, floppy disk, magnetic strip), an optical disk (e.g., a compact disc (CD) or a digital versatile disc (DVD)), a smart card, a flash memory device (e.g., a “flash drive,” a card, a stick, or a key drive), a random access memory (RAM), a read only memory (ROM), a programmable ROM (PROM), an erasable PROM (EPROM), an electrically erasable PROM (EEPROM), a register, a removable disk, and any other suitable medium for storing software and/or instructions that may be accessed and read by a computer. The computer-readable medium and/or storage  2306  may also include, by way of example, a carrier wave, a transmission line, and any other suitable medium for transmitting software and/or instructions that may be accessed and read by a computer. Computer-readable medium and/or the storage  2306  may reside in the processing circuit  2302 , in the processor  2304 , external to the processing circuit  2302 , or be distributed across multiple entities including the processing circuit  2302 . The computer-readable medium and/or storage  2306  may be embodied in a computer program product. By way of example, a computer program product may include a computer-readable medium in packaging materials. Those skilled in the art will recognize how best to implement the described functionality presented throughout this disclosure depending on the particular application and the overall design constraints imposed on the overall system. 
     The storage  2306  may maintain software maintained and/or organized in loadable code segments, modules, applications, programs, etc., which may be referred to herein as software modules  2316 . Each of the software modules  2316  may include instructions and data that, when installed or loaded on the processing circuit  2302  and executed by the one or more processors  2304 , contribute to a run-time image  2314  that controls the operation of the one or more processors  2304 . When executed, certain instructions may cause the processing circuit  2302  to perform functions in accordance with certain methods, algorithms and processes described herein. 
     Some of the software modules  2316  may be loaded during initialization of the processing circuit  2302 , and these software modules  2316  may configure the processing circuit  2302  to enable performance of the various functions disclosed herein. For example, some software modules  2316  may configure internal devices and/or logic circuits  2322  of the processor  2304 , and may manage access to external devices such as the transceiver  2312 , the bus interface  2308 , the user interface  2318 , timers, mathematical coprocessors, and so on. The software modules  2316  may include a control program and/or an operating system that interacts with interrupt handlers and device drivers, and that controls access to various resources provided by the processing circuit  2302 . The resources may include memory, processing time, access to the transceiver  2312 , the user interface  2318 , and so on. 
     One or more processors  2304  of the processing circuit  2302  may be multifunctional, whereby some of the software modules  2316  are loaded and configured to perform different functions or different instances of the same function. The one or more processors  2304  may additionally be adapted to manage background tasks initiated in response to inputs from the user interface : 2318 , the transceiver  2312 , and device drivers, for example. To support the performance of multiple functions, the one or more processors  2304  may be configured to provide a multitasking environment, whereby each of a plurality of functions is implemented as a set of tasks serviced by the one or more processors  2304  as needed or desired. In one example, the multitasking environment may be implemented using a timesharing program  2320  that passes control of a processor  2304  between different tasks, whereby each task returns control of the one or more processors  2304  to the timesharing program  2320  upon completion of any outstanding operations and/or in response to an input such as an interrupt. When a task has control of the one or more processors  2304 , the processing circuit is effectively specialized for the purposes addressed by the function associated with the controlling task. The timesharing program  2320  may include an operating system, a main loop that transfers control on a round-robin basis, a function that allocates control of the one or more processors  2304  in accordance with a prioritization of the functions, and/or an interrupt driven main loop that responds to external events by providing control of the one or more processors  2304  to a handling function. 
       FIG. 24  is a flowchart illustrating a method for data communications on a multi-wire communications interface that employs transcoding. The method may be performed using a transmitting circuit. 
     At block  2402 , the transmitting circuit may provide a plurality of data bits in a word to be transmitted such that a bit-order of the plurality of data bits is flipped with respect to bit-order of the word to be transmitted. 
     At block  2404 , the transmitting circuit may provide an EDC as one or more least significant bits of the word to be transmitted and adjacent to a most significant bit of the plurality of data bits in the word to be transmitted. 
     At block  2406 , the transmitting circuit may convert the word to be transmitted into a transition number. 
     At block  2408 , the transmitting circuit may transmit the transition number as a sequence of symbols on the multi-wire interface. The transition number may be expressed using a numeral system based on a maximum number of possible states per symbol. The length of the EDC may be at least one bit and the EDC may have a known, fixed value and length selected to enable a decoder to detect or correct one or more symbol errors in the sequence of symbols. The length and the known, fixed value of the EDC may be selected such that a transmission error affecting the one or more symbols in the sequence of symbols results in the EDC having a value different from the known, fixed value when decoded. The EDC may be provided as a number of bits, the number being determined based on a number of symbols in the sequence of symbols and a total number of states per symbol available for encoding data transmissions on the multi-wire interface. In one example, the EDC includes 8 bits. 
     In some examples, the transmitting circuit may generate each symbol in the sequence of symbols using a digit of the transition number and a preceding symbol in the sequence of symbols. Clock information is embedded in transitions between consecutive symbols in the sequence of symbols. 
     In some examples, the transmitting circuit may provide control bits in the word to be transmitted in more significant bits than bits assigned to carry the plurality of data bits. 
     In some examples, the transmitting circuit may select a level of error detection or correction for a transaction on the multi-wire interface, configure the length of the EDC in accordance with the level of error detection or correction selected, and define a number of bits in the plurality of data bits in accordance with the length of the EDC. 
       FIG. 25  is a conceptual diagram illustrating an example of a hardware implementation for an apparatus  2500  employing a processing circuit  2502 . In this example, the processing circuit  2502  may be implemented with a bus architecture, represented generally by the bus  2516 . The bus  2516  may include any number of interconnecting buses and bridges depending on the specific application of the processing circuit  2502  and the overall design constraints. The bus  2516  links together various circuits including one or more processors, represented generally by the processor  2512 , and computer-readable media, represented generally by the processor-readable storage medium  2514 . The bus  2516  may also link various other circuits such as timing sources, timers, peripherals, voltage regulators, and power management circuits. A transceiver or communications interface  2518  provides a means for communicating with various other apparatus over a multi-wire interface  2520 . Depending upon the nature of the apparatus, a user interface (e.g., keypad, display, speaker, microphone, joystick) may also be provided. One or more clock generation circuits may be provided within the processing circuit  2502  or controlled by the processing circuit  2502  and/or one or more processors  2512 . In one example, the clock generation circuits may include one or more crystal oscillators, one or more phase-locked loop devices, and/or one or more configurable clock trees. 
     The processor  2512  is responsible for managing the bus  2516  and general processing, including the execution of software stored on the processor-readable storage medium  2514 . The software, when executed by the processor  2512 , causes the processing circuit  2502  to perform the various functions described supra for any particular apparatus. The processor-readable storage medium  2514  may be used for storing data that is manipulated by the processor  2512  when executing software. 
     In one configuration, the processing circuit may include one or more modules and/or circuits  2504  for encoding data words with EDCs in transition numbers, one or more modules and/or circuits  2506  for generating sequences of symbols based on the transition numbers to obtain, and one or more modules and/or circuits  2504 ,  2512  for transmitting the sequences of symbols in the signaling state of the multi-wire interface  2520 . 
       FIG. 26  is a flowchart illustrating a method for data communications on a multi-wire communications interface that employs transcoding. The method may be performed using a receiving circuit. 
     At block  2602 , the receiving circuit may receive a sequence of symbols from a plurality of connectors. In some examples, clock information is embedded in transitions between consecutive symbols in the sequence of symbols. 
     At block  2604 , the receiving circuit may convert the sequence of symbols into a transition number. Each digit of the transition number may represent a transition between two consecutive symbols transmitted on the plurality of connectors. The transition number may be expressed using a numeral system based on a maximum number of possible symbol transitions between a pair of consecutive symbols transmitted on the plurality of connectors. 
     At block  2606 , the receiving circuit may convert the transition number into a plurality of bits. 
     At block  2608 , the receiving circuit may determine whether a symbol error has occurred during transmission of the sequence of symbols based on a value of an EDC included in the plurality of bits. The EDC may have a known, fixed value and a length determined based on a total number of states per symbol defined for encoding data transmissions on the plurality of connectors. In some instances, one or more symbol errors may cause a decoded version of the EDC to have a value that is different from the known, fixed value. 
     In some examples, the EDC may be provided as a fixed or predefined number of least significant bits in the plurality of bits. The fixed or predefined number of LSBs may be determined based on a total number of states per symbol available for encoding data transmissions on the plurality of connectors. The fixed or predefined number of LSBs may be determined based on a total number of symbols used to encode the data word. 
     The plurality of connectors may include a number (N) single-ended connectors, the total number of states per symbol available for encoding data transmissions is 2 N −x, where x is at least 1. 
     In one example, the total number of states available at each transition is 3 and the EDC includes 8 bits. When the total number of states available at each transition is 3, and when the sequence of symbols includes 17 or more symbols, the EDC may include 9 bits. 
     In another example, the total number of states available at each transition may be 5 and the EDC may include 10 bits. When the total number of states available at each transition is 5, and when the sequence of symbols includes 8 or more symbols, the EDC may include 11 bits. 
       FIG. 27  is a conceptual diagram illustrating an example of a hardware implementation for an apparatus  2700  employing a processing circuit  2702 . In this example, the processing circuit  2702  may be implemented with a bus architecture, represented generally by the bus  2716 . The bus  2716  may include any number of interconnecting buses and bridges depending on the specific application of the processing circuit  2702  and the overall design constraints. The bus  2716  links together various circuits including one or more processors, represented generally by the processor  2712 , and computer-readable media, represented generally by the processor-readable storage medium  2714 . The bus  2716  may also link various other circuits such as timing sources, timers, peripherals, voltage regulators, and power management circuits. A transceiver or communications interface  2718  provides a means for communicating with various other apparatus over a multi-wire interface  2720 . Depending upon the nature of the apparatus, a user interface (e.g., keypad, display, speaker, microphone, joystick) may also be provided. One or more clock generation circuits may be provided within the processing circuit  2702  or controlled by the processing circuit  2702  and/or one or more processors  2712 . In one example, the clock generation circuits may include one or more crystal oscillators, one or more phase-locked loop devices, and/or one or more configurable clock trees. 
     The processor  2712  is responsible for managing the bus  2716  and general processing, including the execution of software stored on the processor-readable storage medium  2714 . The software, when executed by the processor  2712 , causes the processing circuit  2702  to perform the various functions described supra for any particular apparatus. The processor-readable storage medium  2714  may be used for storing data that is manipulated by the processor  2712  when executing software. 
     In one configuration, the processing circuit may include one or more modules anchor circuits  2704  for receiving sequences of symbols from the multi-wire interface  2720 , one or more modules and/or circuits  2706  for generating transition numbers from the sequences of symbols, one or more modules and/or circuits  2708  for decoding data words from the transition numbers, and one or more modules and/or circuits  2710  for detecting symbol errors using an EDC decoded from the transition numbers. 
     Those of skill in the art would appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. 
     The various features of the invention described herein can be implemented in different systems without departing from the invention. It should be noted that the foregoing embodiments are merely examples and are not to be construed as limiting the invention. The description of the embodiments is intended to be illustrative, and not to limit the scope of the claims. As such, the present teachings can be readily applied to other types of apparatuses and many alternatives, modifications, and variations will he apparent to those skilled in the art.