Patent Publication Number: US-5627461-A

Title: Reference current circuit capable of preventing occurrence of a difference collector current which is caused by early voltage effect

Description:
BACKGROUND OF THE INVENTION 
     This invention relates to a reference current circuit and a reference voltage circuit. 
     A conventional reference current circuit is disclosed in IEEE Journal of Solid-State Circuits, Vol. SC-22, No. 6, pp. 1139-1143, Dec. 1987. 
     In the manner which will later be described more in detail, the conventional reference current circuit comprises a primary pair of first and second transistors and a secondary pair of third and fourth transistors. The first transistor has a first emitter electrode connected to ground through a resistor. The second transistor has a second emitter electrode grounded and a second base electrode connected to a first base electrode of the first transistor. The third transistor has a third emitter electrode connected to a power supply terminal which is supplied with a power supply voltage from a power supply unit. The third transistor has a third collector electrode connected to a first collector electrode of the first transistor. The fourth transistor has a fourth emitter electrode connected to the power supply terminal and a fourth base electrode connected to a third base electrode of the third transistor. The fourth transistor has a fourth collector electrode connected to the fourth base electrode of the fourth transistor and a first collector electrode of the first transistor. 
     A fifth transistor has a fifth emitter electrode connected to the power supply terminal and a fifth electrode connected to the third collector electrode of the third transistor. A sixth transistor has a sixth emitter electrode grounded and a sixth collector electrode connected to a fifth collector electrode of the fifth transistor. The fifth transistor has a fifth base electrode connected to the sixth collector electrode of the sixth transistor and the first base electrode of the first transistor. 
     The first transistor has an emitter area which is Ki times as large as a unit emitter area of a unit transistor. Each of the second through the fourth transistors has an emitter area which is equal to the unit emitter area. Each of the fifth and the sixth transistors has an emitter area which is two times as large as the unit emitter area. Inasmuch as the fifth transistor has the emitter area which is two times as large as the unit emitter area of the unit transistor, a collector current of the first transistor is almost equal to a collector current of the second transistor. 
     However, in this conventional reference current circuit, a difference collector current is caused by Early voltage effect in response to a change of the power supply voltage. As a result, it is hardly possible in the conventional reference current circuit to prevent occurrence of the difference base emitter voltage which is caused by Early voltage effect. 
     It is hardly possible in the conventional reference current circuit to change the reference current circuit into a reference voltage circuit. 
     The conventional reference current circuit has a large amount of consumption current. 
     SUMMARY OF THE INVENTION 
     It is therefore an object of the present invention to provide a reference current circuit or a reference voltage current which is capable of preventing occurrence of a difference collector current which is caused by Early voltage effect in response to a change of a power supply voltage. 
     It is another object of this invention to provide a reference current circuit or a reference voltage circuit which is capable of easily changing the reference current circuit or the reference voltage circuit into the reference voltage circuit or the reference current circuit. 
     It is still another object of this invention to provide a reference current circuit or a reference voltage circuit which has a small amount of consumption current. 
     Other objects of this invention will become clear as the description proceeds. 
     According to a first aspect of this invention, there is provided a reference current circuit which comprises (A) a primary pair of first and second transistors, the first transistor having a first emitter electrode grounded and a first emitter area, the second transistor having a second base electrode connected to a first collector electrode of the first transistor, a second emitter electrode grounded, and a second emitter area which is equal to e times as large as the first emitter area, where e represents the base of natural logarithm; (B) a secondary pair of third and fourth transistors, the third transistor having a third base electrode connected to a second collector electrode of the second transistor, a third emitter electrode connected to a power supply terminal which is supplied with a power supply voltage, and a third emitter area which is equal to the first emitter area, the fourth transistor having a fourth base electrode connected to a third collector electrode of the third transistor, a fourth collector electrode connected to a first base electrode of the first transistor, a fourth emitter electrode connected to the power supply terminal, and a fourth emitter area which is equal to the second emitter area; (C) a first resistor connected between the first collector electrode and the first base electrode; and (D) a second resistor connected between the second collector electrode and the second base electrode. 
     According to a second aspect of this invention, there is provided a reference voltage circuit which comprises (A) a primary pair of first and second transistors, the first transistor having a first emitter electrode grounded and a first emitter area, the second transistor having a second base electrode connected to a first collector electrode of the first transistor, a second emitter electrode grounded, and a second emitter area which is equal to e times as large as the first emitter area, where e represents the base of natural logarithm; (B) a secondary pair of third and fourth transistors, the third transistor having a third base electrode connected to a second collector electrode of the second transistor, a third emitter electrode connected to a power supply terminal which is supplied with a power supply voltage, and a third emitter area which is equal to the first emitter area, the fourth transistor having a fourth base electrode connected to a third collector electrode of the third transistor, a fourth collector electrode connected to a first base electrode of the first transistor, a fourth emitter electrode connected to the power supply terminal, and a fourth emitter area which is equal to the second emitter area; (C) a first resistor connected between the first collector electrode and the first base electrode; (D) a second resistor connected between the second collector electrode and the second base electrode; (E) a third resistor connected between the first base electrode and the fourth collector electrode; and (F) an output voltage terminal connected to a node of the third resistor and the fourth collector electrode. 
     According to a third aspect of this invention, there is provided a reference voltage circuit which comprises (A) a primary pair of first and second transistors, the first transistor having a first emitter electrode grounded and a first emitter area, the second transistor having a second base electrode connected to a first collector electrode of the first transistor, a second emitter electrode grounded, and a second emitter area which is equal to e times as large as the first emitter area, where e represents the base of natural logarithm; (B) a secondary pair of third and fourth transistors, the third transistor having a third base electrode connected to a second collector electrode of the second transistor, a third emitter electrode connected to a power supply terminal which is supplied with a power supply voltage, and a third emitter area which is equal to the first emitter area, the fourth transistor having a fourth base electrode connected to a third collector electrode of the third transistor, a fourth collector electrode connected to a first base electrode of the first transistor, a fourth emitter electrode connected to the power supply terminal, and a fourth emitter area which is equal to the second emitter area; (C) a first resistor connected between the first collector electrode and the first base electrode; (D) a second resistor connected between the second collector electrode and the second base electrode; (E) a third resistor connected between the first base electrode and the fourth collector electrode; (F) a first output voltage terminal connected to a node of the third resistor and the fourth collector electrode; (G) a fourth resistor connected between the second collector electrode and the third base electrode; and (H) a second output voltage terminal connected to a node of the fourth resistor and the second collector electrode. 
     According to a fourth aspect of this invention, there is provided a reference current circuit which comprises (A) a primary pair of first and second transistors, the first transistor having a first emitter electrode grounded and a first emitter area, the second transistor having a second base electrode connected to a first collector electrode of the first transistor, a second emitter electrode grounded, and a second emitter area which is equal to e times as large as the first emitter area, where e represents the base of natural logarithm; (B) a secondary pair of third and fourth transistors, the third transistor having a third collector electrode connected to a second collector electrode of the second transistor, a third emitter electrode connected to a power supply terminal which is supplied with a power supply voltage, and a third emitter area which is equal to the first emitter area, the fourth transistor having a fourth base electrode connected to a third base electrode of the third transistor, a fourth collector electrode connected to a first base electrode of the first transistor, a fourth emitter electrode connected to the power supply terminal, and a fourth emitter area which is equal to the first emitter area; (C) a resistor connected between the first collector electrode and the first base electrode; (D) a fifth transistor having a fifth emitter electrode connected to the power supply terminal, a fifth base electrode connected to the third base electrode, and a fifth collector electrode connected to the fifth base electrode; and (E) a sixth transistor having a sixth emitter electrode grounded, a sixth base electrode connected to the second collector electrode, and a sixth collector electrode connected to the fifth collector electrode. 
     According to a fifth aspect of this invention, there is provided a reference voltage circuit which comprises (A) a primary pair of first and second transistors, the first transistor having a first emitter electrode grounded and a first emitter area, the second transistor having a second base electrode connected to a first collector electrode of the first transistor, a second emitter electrode grounded, and a second emitter area which is equal to e times as large as the first emitter area, where e represents the base of natural logarithm; (B) a secondary pair of third and fourth transistors, the third transistor having a third emitter electrode connected to a power supply terminal which is supplied with a power supply voltage, and a third emitter area which is equal to the first emitter area, the fourth transistor having a fourth base electrode connected to a third base electrode of the third transistor, a fourth emitter electrode connected to the power supply terminal, and a fourth emitter area which is equal to the first emitter area; (C) a first resistor connected between the first collector electrode and the first base electrode; (D) a second resistor connected between the first base electrode and a fourth collector electrode of the fourth transistor, the second resistor having a primary resistance value; (E) a third resistor connected between a second collector electrode of the second transistor and a third collector electrode of the third transistor, the third resistor having a secondary resistance value which is equal to the primary resistance value; (F) a fifth transistor having a fifth emitter electrode connected to the power supply terminal, a fifth base electrode connected to the third base electrode, and a fifth collector electrode connected to the fifth base electrode; and (G) a sixth transistor having a sixth emitter electrode grounded, a sixth base electrode connected to the second collector electrode, and a sixth collector electrode connected to the fifth collector electrode. 
     According to a sixth aspect of this invention, there is provided a reference voltage circuit which comprises (A) a primary pair of first and second transistors, the first transistor having a first emitter electrode grounded and a first emitter area, the second transistor having a second base electrode connected to a first base electrode of the first transistor, and a second emitter area which is equal to e times as large as the first emitter area, where e represents the base of natural logarithm; (B) a secondary pair of third and fourth transistors, the third transistor having a third collector electrode connected to a second collector electrode of the second transistor, a third emitter electrode connected to a power supply terminal which is supplied with a power supply voltage, and a third emitter area which is equal to the first emitter area, the fourth transistor having a fourth base electrode connected to a third base electrode of the third transistor, a fourth collector electrode connected to the third and the fourth base electrodes and a first collector electrode of the first transistor, a fourth emitter electrode connected to the power supply terminal, and a fourth emitter area which is equal to the first emitter area; (C) a first resistor connected between the first emitter electrode and ground; (D) a fifth transistor having a fifth base electrode connected to the third collector electrode, a fifth emitter electrode connected to the power supply terminal, and a fifth emitter area which is equal to two times as large as the first emitter area; (E) a sixth transistor having a sixth base electrode connected to the second base electrode, a sixth collector electrode connected to the sixth base electrode, a sixth emitter electrode grounded, and a sixth emitter area which is equal to the fifth emitter area; (F) a second resistor connected between a fifth collector electrode of the fifth transistor and the sixth collector electrode of the sixth transistor; and (G) an output voltage terminal connected to a node of the fifth collector electrode and the second collector electrode. 
     According to a seventh aspect of this invention, there is provided a reference current circuit which comprises (A) a primary pair of first and second MOS transistors, the first MOS transistor having a first source electrode grounded and a first transconductance, the second MOS transistor having a second gate electrode connected to a first drain electrode of the first MOS transistor, a second source electrode grounded, and a second transconductance which is equal to four times as large as the first transconductance; (B) a secondary pair of third and fourth MOS transistors, the third MOS transistor having a third gate electrode connected to a second drain electrode of the second MOS transistor, a third source electrode connected to a power supply terminal which is supplied with a power supply voltage, and a third transconductance which is equal to the first transconductance, the fourth MOS transistor having a fourth gate electrode connected to a third drain electrode of the third MOS transistor, a fourth electrode connected to a first gate electrode of the first MOS transistor, a fourth source electrode connected to the power supply terminal, and a fourth transconductance which is equal to the second transconductance; (C) a first resistor connected between the first drain electrode and the first gate electrode; and (D) a second resistor connected between the second drain electrode and the second gate electrode. 
     According to an eighth aspect of this invention, there is provided a reference voltage circuit which comprises (A) a primary pair of first and second MOS transistors, the first MOS transistor having a first source electrode grounded and a first transconductance, the second MOS transistor having a second gate electrode connected to a first drain electrode of the first MOS transistor, a second source electrode grounded, and a second transconductance which is equal to four times as large as the first transconductance; (B) a secondary pair of third and fourth MOS transistors, the third MOS transistor having a third gate electrode connected to a second drain electrode of the second MOS transistor, a third source electrode connected to a power supply terminal which is supplied with a power supply voltage, and a third transconductance which is equal to the first transconductance, the fourth MOS transistor having a fourth gate electrode connected to a third drain electrode of the third MOS transistor, a fourth drain electrode connected to a first gate electrode of the first MOS transistor, a fourth source electrode connected to the power supply terminal, and a fourth transconductance which is equal to the second transconductance; (C) a first resistor connected between the first drain electrode and the first gate electrode; (D) a second resistor connected between the second drain electrode and the second gate electrode; (E) a third resistor connected between the first gate electrode and the fourth drain electrode; and (F) an output voltage terminal connected to a node of the third resistor and the fourth drain electrode. 
     According to a ninth aspect of this invention, there is provided a reference voltage circuit which comprises (A) a primary pair of first and second MOS transistors, the first MOS transistor having a first source electrode grounded and a first transconductance, the second MOS transistor having a second gate electrode connected to a first drain electrode of the first MOS transistor, a second source electrode grounded, and a second transconductance which is equal to four times as large as the first transconductance; (B) a secondary pair of third and fourth MOS transistors, the third transistor having a third gate electrode connected to a second drain electrode of the second MOS transistor, a third source electrode connected to a power supply terminal which is supplied with a power supply voltage, and a third transconductance which is equal to the first transconductance, the fourth MOS transistor having a fourth gate electrode connected to a third drain electrode of the third MOS transistor, a fourth drain electrode connected to a first gate electrode of the first MOS transistor, a fourth source electrode connected to the power supply terminal, and a fourth transconductance which is equal to the second transconductance; (C) a first resistor connected between the first drain electrode and the first gate electrode; (D) a second resistor connected between the second drain electrode and the second gate electrode; (E) a third resistor connected between the first gate electrode and the fourth drain electrode; (F) a first output voltage terminal connected to a node of the third resistor and the fourth drain electrode; (G) a fourth resistor connected between the second drain electrode and the third gate electrode; and (H) a second output voltage terminal connected to a node of the fourth resistor and the second drain electrode. 
     According to a tenth aspect of this invention, there is provided a reference current circuit which comprises (A) a primary pair of first and second MOS transistors, the first MOS transistor having a first source electrode grounded and a first transconductance, the second MOS transistor having a second gate electrode connected to a first drain electrode of the first MOS transistor, a second gate electrode grounded, and a second transconductance which is equal to four times as large as the first transconductance; (B) a secondary pair of third and fourth MOS transistors, the third MOS transistor having a third drain electrode connected to a second drain electrode of the second MOS transistor, a third source electrode connected to a power supply terminal which is supplied with a power supply voltage, and a third transconductance which is equal to the first transconductance, the fourth MOS transistor having a fourth gate electrode connected to a third gate electrode of the third MOS transistor, a fourth drain electrode connected to a first gate electrode of the first MOS transistor, a fourth source electrode connected to the power supply terminal, and a fourth transconductance which is equal to the first transconductance; (C) a resistor connected between the first drain electrode and the first gate electrode; (D) a fifth MOS transistor having a fifth source electrode connected to the power supply terminal, a fifth gate electrode connected to the third gate electrode, and a fifth drain electrode connected to the fifth gate electrode; and (E) a sixth MOS transistor having a sixth source electrode grounded, a sixth gate electrode connected to the second drain electrode, and a sixth drain electrode connected to the fifth drain electrode. 
     According to an eleventh aspect of this invention, there is provided a reference voltage circuit which comprises (A) a primary pair of first and second MOS transistors, the first MOS transistor having a first source electrode grounded and a first transconductance, the second MOS transistor having a second gate electrode connected to a first drain electrode of the first MOS transistor, a second source electrode grounded, and a second transconductance which is equal to four times as large as the first transconductance; (B) a secondary pair of third and fourth MOS transistors, the third MOS transistor having a third source electrode connected to a power supply terminal which is supplied with a power supply voltage, and a third transconductance which is equal to the first transconductance, the fourth MOS transistor having a fourth gate electrode connected to a third gate electrode of the third MOS transistor, a fourth source electrode connected to the power supply terminal, and a fourth transconductance which is equal to the first transconductance; (C) a first resistor connected between the first drain electrode and the first base electrode; (D) a second resistor connected between the first gate electrode and a fourth drain electrode of the fourth MOS transistor, the second resistor having a primary resistance value; (E) a third resistor connected between a second drain electrode of the second MOS transistor and a third drain electrode of the third MOS transistor, the third resistor having a secondary resistance value which is equal to the primary resistance value; (F) a fifth MOS transistor having a fifth source electrode connected to the power supply terminal, a fifth gate electrode connected to the third gate electrode, and a fifth drain electrode connected to the fifth gate electrode; and (G) a sixth MOS transistor having a sixth source electrode grounded, a sixth gate electrode connected to the second drain electrode, and a sixth drain electrode connected to the fifth drain electrode. 
     According to a twelfth aspect of this invention, there is provided a reference voltage circuit which comprises (A) a primary pair of first and second MOS transistors, the first MOS transistor having a first source electrode grounded and a first transconductance, the second MOS transistor having a second gate electrode connected to a first gate electrode of the first MOS transistor, and a second transconductance which is equal to four times as large as the first transconductance; (B) a secondary pair of third and fourth MOS transistors, the third MOS transistor having a third drain electrode connected to a second drain electrode of the second MOS transistor, a third source electrode connected to a power supply terminal which is supplied with a power supply voltage, and a third transconductance which is equal to the first transconductance, the fourth MOS transistor having a fourth gate electrode connected to a third gate electrode of the third MOS transistor, a fourth drain electrode connected to the third and the fourth gate electrodes and a first drain electrode of the first MOS transistor, a fourth source electrode connected to the power supply terminal, and a fourth transconductance which is equal to the first transconductance; (C) a first resistor connected between the first source electrode and ground; (D) a fifth MOS transistor having a fifth gate electrode connected to the third drain electrode, a fifth source electrode connected to the power supply terminal, and a fifth transconductance which is equal to two times as large as the first transconductance; (E) a sixth MOS transistor having a sixth gate electrode connected to the second gate electrode, a sixth drain electrode connected to the sixth gate electrode, a sixth source electrode grounded, and a sixth transconductance which is equal to the fifth transconductance; (F) a second resistor connected between a fifth drain electrode of the fifth MOS transistor and the sixth drain electrode of the sixth MOS transistor; and (G) an output voltage terminal connected to a node of the fifth drain electrode and the second drain electrode. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING 
     FIG. 1 is a circuit diagram of a conventional reference current circuit; 
     FIG. 2 is a circuit diagram of a reference current circuit according to a first embodiment of this invention; 
     FIG. 3 is a circuit diagram of a part of the reference current circuit illustrated in FIG. 2; 
     FIG. 4 is a graph for use in describing operation of the reference current circuit illustrated in FIGS. 2 and 3; 
     FIG. 5 is another graph for use in describing operation of the reference current circuit illustrated in FIGS. 2 and 3; 
     FIG. 6 is a circuit diagram of a reference voltage circuit according to a second embodiment of this invention; 
     FIG. 7 is a circuit diagram of a reference voltage circuit according to a third embodiment of this invention; 
     FIG. 8 is a circuit diagram of a reference current circuit according to a fourth embodiment of this invention; 
     FIG. 9 is a circuit diagram of a reference voltage circuit according to a fifth embodiment of this invention; 
     FIG. 10 is a circuit diagram of a reference voltage circuit according to a sixth embodiment of this invention; 
     FIG. 11 is a circuit diagram of a reference current circuit according to a seventh embodiment of this invention; 
     FIG. 12 is a circuit diagram of a part of the reference current circuit illustrated in FIG. 11; 
     FIG. 13 is a graph for use in describing operation of the reference current circuit illustrated in FIGS. 11 and 12; 
     FIG. 14 is a circuit diagram of a reference voltage circuit according to an eighth embodiment of this invention; 
     FIG. 15 is a circuit diagram of a reference voltage circuit according to a ninth embodiment of this invention; 
     FIG. 16 is a circuit diagram of a reference current circuit according to a tenth embodiment of this invention; 
     FIG. 17 is a graph for use in describing operation of the reference current circuit illustrated in FIG. 16; 
     FIG. 18 is a circuit diagram of a reference voltage circuit according to an eleventh embodiment of this invention; and 
     FIG. 19 is a circuit diagram of a reference voltage circuit according to a twelfth embodiment of this invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Referring to FIG. 1, a conventional reference current circuit will be described for a better understanding of this invention. The conventional reference current circuit comprises a primary pair of transistors Q 21  and Q 22  and a secondary pair of transistors Q 23  and Q 24 . The transistor Q 21  has an emitter electrode connected to ground through a resistor R 21 . The transistor Q 22  has an emitter electrode grounded and a base electrode connected to a base electrode of the transistor Q 21 . The transistor Q 23  has an emitter electrode connected to a power supply terminal V CC  which is supplied with a power supply voltage from a power supply unit (not shown). The transistor Q 23  has a collector electrode connected to a collector electrode of the transistor Q 21 . The transistor Q 24  has an emitter electrode connected to the power supply terminal V CC  and a base electrode connected to a base electrode of the transistor Q 23 . The transistor Q 24  has a collector electrode connected to the base electrode of the transistor Q 24  and a collector electrode of the transistor Q 21 . 
     A transistor Q 25  has an emitter electrode connected to the power supply terminal V CC  and a base electrode connected to the collector electrode of the transistor Q 23 . A transistor Q 26  has an emitter electrode grounded and a collector electrode connected to a collector electrode of the transistor Q 25 . The transistor Q 25  has a base electrode connected to the collector electrode of the transistor Q 26  and the base electrode of the transistor Q 21 . 
     The transistor Q 21  has an emitter area which is Ki times as large as a unit emitter area of a unit transistor. Each of the transistors Q 22  to Q 24  has an emitter area which is equal to the unit emitter area. Each of the transistors Q 25  and Q 26  has an emitter area which is two times as large as the unit emitter area. Inasmuch as the transistor Q 25  has the emitter area which is two times as large as the unit emitter area of the unit transistor, a collector current of the transistor Q 21  is almost equal to a collector current of the transistor Q 22 . 
     It will be assumed that Ici represents a collector current of the unit transistor, Vt represents a thermal voltage in an absolute temperature T, Is represents a saturation current in a collector electrode of the unit transistor, Ki represents an emitter area ratio, and V BE  represents a base emitter voltage of the transistor. The collector current Ici is given by: 
     
         Ici=Ki Is exp(V.sub.BE /V.sub.T)                           (1) 
    
     where V T  is given by (kT/q), where k represents Boltzman&#39;s constant, and q, the charge of a unit electron. 
     Inasmuch as the transistor Q 21  has the emitter area which is K 1  times as large as the unit emitter area, a difference base emitter voltage ΔV BE  between the transistors Q 21  and Q 22  is given by: 
     
         ΔV.sub.BE =V.sub.BE2 -V.sub.BE1 =V.sub.T 1n(K.sub.1)=R.sub.1 I.sub.1( 2) 
    
     where V BE1  represents a base emitter voltage of the transistor Q 21 , V BE2  represents a base emitter voltage of the transistor Q 22 , and I 1  represents a collector current of the transistor Q 21 . Herein, each of current amplification factors of the transistors Q 21  and Q 22  is equal to one. 
     The equation (2) is rewritten by a following equation (3). ##EQU1## 
     In this conventional reference current circuit, the difference base emitter voltage ΔV BE  is caused by Early voltage effect in response to a change of the power supply voltage. As a result, it is hardly possible in the conventional reference current circuit to prevent occurrence of the difference base emitter voltage ΔV BE  which is caused by Early voltage effect. 
     It is hardly possible in the conventional reference current circuit to change the reference current circuit into a reference voltage circuit. 
     The conventional reference current circuit has a large amount of consumption current. 
     Referring to FIGS. 2, 3, 4, and 5, the description will proceed to a reference current circuit according to a first embodiment of this invention. 
     In FIG. 2, the reference current circuit comprises a pair of first and second transistors Q 1  and Q 2 , a pair of third and fourth transistors Q 3  and Q 4 , and first and second resistors R 1  and R 2 . 
     The first transistor Q 1  has a first emitter electrode grounded and a first emitter area. The second transistor Q 2  has a second base electrode connected to a first collector electrode of the first transistor Q 1 , a second emitter electrode grounded, and a second emitter area. The second emitter area is equal to e times as large as the first emitter area, where e represents the base of natural logarithm. 
     The third transistor Q 3  has a third base electrode connected to a second collector electrode of the second transistor Q 2  and a third emitter electrode connected to a power supply terminal V CC . The power supply terminal V CC  is supplied with a power supply voltage from a power supply unit (not shown). The third transistor Q 3  has a third emitter area which is equal to the first emitter area. The fourth transistor Q 4  has a fourth base electrode connected to a third collector electrode of the third transistor Q 3  and a fourth collector electrode connected to a first base electrode of the first transistor Q 1 . The fourth transistor Q 4  has a fourth emitter electrode connected to the power supply terminal V CC  and a fourth emitter area which is equal to the second emitter area. 
     The first resistor R 1  is connected between the first collector electrode and the first base electrode and has a first resistance value R 1 . The second resistor R 2  is connected between the second collector electrode and the second base electrode and has a second resistance value R 2  which is equal to the first resistance value. 
     A first voltage drop is caused across the first resistor R 1  when a first collector current flows in the first resistor R 1 . A second voltage drop is caused across the second resistor R 2  when a second collector current flows in the resistor R 2 . Each of the first and the second resistors R 1  and R 2  has a common temperature. Each of the first and the second voltage drops is substantially equal to a thermal voltage in the common temperature. 
     The first transistor Q 1 , the second transistor Q 2 , and the first resistor R 1  are shown in FIG. 2. It will be assumed that I 1  represents the first collector current of the first transistor Q 1 , I 2  represents the second collector current of the second transistor Q 2 , K 1  represents an emitter area ratio of the second transistor R 2  to the first transistor Q 1 , V BE1  represents a first base emitter voltage of the first transistor Q 1 , V BE2  represents a second base emitter voltage of the second transistor Q 2 , and ΔV BE  represents a difference base emitter voltage between the first and the second base emitter voltages V BE1  and V BE2 . The first collector current I 1 , the second collector current I 2 , and the difference base emitter voltage ΔV BE  are given by following equations (4), (5), and (6). 
     
         I.sub.1 =Is exp(V.sub.BE1 /V.sub.T)                        (4) 
    
     
         I.sub.2 =K.sub.1 Is exp(V.sub.BE2 /V.sub.T)                (5) 
    
     
         ΔV.sub.BE =V.sub.BE1 -V.sub.BE2 =R.sub.1 I.sub.1     (6) 
    
     A following equation (7) is given by the equations (4), (5), and (6). 
     
         I.sub.2 =K.sub.1 I.sub.1 exp(-R.sub.1 I.sub.1 /V.sub.T)    (7) 
    
     A curved line A in FIG. 4 shows a relation of I 1  and I 2  in the equation (7). As shown in FIG. 4, I 2  has a peak point P 1 . 
     It will be assumed that K 1  is equal to e, where e represents the base of natural logarithm. A following equation (8) is given by the equation (7). 
     
         I.sub.2 =e I.sub.1 exp(-R.sub.1 I.sub.1 /V.sub.T)          (8) 
    
     A curved line B 1  in FIG. 5 shows a relation of I 1  and I 2  in the equation (8). Each of the first and the second transistors Q 1  and Q 2  is an npn type bipolar transistor. Each of the third and the fourth transistors Q 3  and Q 4  is a pnp type bipolar transistor. A curved line B 2  in FIG. 5 shows a relation of I 1  and I 2  of the third and the fourth transistors Q 3  and Q 4 . A curved line (I 1  =I 2 ) is a line of symmetry of the curved lines B 1  and B 2 . The curved line B 1  crosses the curved line B 2  at a peak point P 1  &#39;. 
     In FIG. 2, it will be assumed that the first resistance value R 1  of the first resistor R 1  is equal to the second resistance value R 2  of the second resistor R 2  and each of the first voltage drop across the first resistor R 1  and the second voltage drop across the second resistor R 2  is substantially equal to the thermal voltage in the absolute temperature T. In this case, each of the first through the fourth transistors Q 1  to Q 4  has a common operating point which is equal to the peak point P 1 . Consequently, when a first change of I 1  and a second change of I 2  are caused by Early voltage effect in response to a change of the power supply voltage, the first change of I 1  and the second change of I 2  counteract each other. As a result, the reference current circuit is capable of preventing occurrence of a difference collector current of I 1  and I 2 . Also, the reference current circuit has a consumption current value which is equal to 0.5 times as large as a consumption current value of the conventional reference current circuit illustrated in FIG. 1. 
     Referring to FIG. 6, the description will proceed to a reference voltage circuit according to a second embodiment of this invention. Similar parts are designated by like reference numerals. 
     The reference voltage circuit further comprises a third resistor R 3  and a first output voltage terminal T 1  in the reference current circuit illustrated in FIG. 2. The third resistor R 3  is connected between the first base electrode of the first transistor Q 1  and the fourth collector electrode of the fourth transistor Q 4 . The first output voltage terminal T 1  is connected to a node of the third resistor R 3  and the fourth collector electrode of the fourth transistor Q 4 . The first output voltage terminal T 1  is supplied with a first output voltage V REF1 . 
     On the assumption that I 1  =I 2 , a following equation (9) is given by the equations (4) and (6). 
     
         ΔV.sub.BE =V.sub.BE1 -V.sub.BE2 =V.sub.T 1.sub.n (K.sub.1)(9) 
    
     In the reference voltage circuit, the difference base emitter voltage ΔV BE  has a positive temperature characteristic. Also, each of the first and the second base emitter voltages V BE1  and V BE2  has a negative temperature characteristic which is almost equal to -2.3 mV/°C. Consequently, the first output voltage V REF1  may have a positive, negative, or zero temperature characteristic. On the assumption that the second resistance value R 2  is approximately equal to twenty-three times as large as the first resistance value R 1 , the first output voltage V REF1  has a zero temperature characteristic. 
     Referring to FIG. 7, the description will proceed to a reference voltage circuit according to a third embodiment of this invention. Similar parts are designated by like reference numerals. 
     The reference voltage circuit further comprises a fourth resistor R 4  and a second output voltage terminal T 2  in the reference voltage illustrated in FIG. 6. The fourth resistor R 4  is connected between the second collector electrode of the second transistor Q 2  and the third base electrode of the third transistor Q 3 . The second output voltage terminal T 2  is connected to a node of the fourth resistor R 4  and the second collector electrode of the second transistor Q 2 . The second output voltage terminal T 2  is supplied with a second output voltage V REF2 . The second output voltage V REF2  may have a positive, negative, or zero temperature characteristic which is independent from the temperature characteristic of the first output voltage V REF1 . The third and the fourth resistors R 3  and R 4  have third and fourth resistance values R 3  and R 4 . On the assumption that the third resistance value R 4  is approximately equal to twenty-three times as large as the third resistance value R 4 , the second output voltage V REF2  has a zero temperature characteristic. 
     Referring to FIG. 8, the description will proceed to a reference current circuit according to a fourth embodiment of this invention. Similar parts are designated by like reference numerals. 
     A fifth transistor Q 5  has a fifth collector electrode connected to the second collector electrode of the second transistor Q 2 , a fifth emitter electrode connected to the power supply terminal V CC , and a fifth emitter area which is equal to the first emitter area. A sixth transistor Q 6  has a sixth base electrode connected to a fifth base electrode of the fifth transistor Q 5 , a sixth collector electrode connected to the first base electrode of the first transistor Q 1 . a sixth emitter electrode connected to the power supply terminal V CC , and a sixth emitter area which is equal to the first emitter area. 
     A seventh transistor Q 7  has a seventh emitter electrode connected to the power supply terminal V CC , a seventh base electrode connected to the fifth base electrode of the fifth transistor Q 5 , and a seventh collector electrode connected to the seventh base electrode. An eighth transistor Q 8  has an eighth emitter electrode grounded, an eighth base electrode connected to the second collector electrode of the second transistor Q 2 , and an eighth collector connected to the seventh collector electrode of the seventh transistor Q 7 . 
     A ninth transistor Q 9  has a ninth emitter electrode connected to the power supply terminal V CC , a ninth base electrode connected to the seventh base electrode of the second terminal Q 7 , and a ninth emitter electrode connected to an output current terminal To which is supplied with an output current Io. The ninth transistor Q 9  has a ninth emitter area which is equal to the first emitter area. A tenth transistor Q 10  has a tenth emitter electrode grounded, a tenth base electrode connected to the eighth base electrode of the eighth transistor Q 8 , and a tenth collector electrode connected to an input current terminal Ti which is supplied with an input current Ii. 
     With this structure, on the assumption that I 1  =I 2 , the first collector current I 1  is given by a following equation (10). ##EQU2## 
     Consequently, the first and the second collector currents I 1  and I 2  are proportional to the absolute temperature T. As a result, the reference current circuit has a positive temperature characteristic. Inasmuch as the first and the second collector currents I 1  and I 2  are controlled by the seventh and the eighth transistors Q 7  and Q 8 , the first and the second collector currents I 1  and I 2  are held at a constant current value even when the power supply voltage is changed. 
     Referring to FIG. 9, the description will proceed to a reference voltage circuit according to a fifth embodiment of this invention. Similar parts are designated by like reference numerals. 
     A fifth resistor R 5  is connected between the first base collector electrode of the first transistor Q 1  and the sixth collector electrode of the sixth transistor Q 6 . The fifth resistor R 5  has a fifth resistance value R 5 . A third output voltage terminal T 3  is connected to a node of the fifth resistor R 5  and the sixth collector electrode of the sixth transistor Q 6 . The third output voltage terminal T 3  is supplied with a third output voltage V REF3 . A sixth resistor R 6  is connected between the second collector electrode of the second transistor Q 2  and the fifth collector electrode of the fifth transistor Q 5 . The sixth resistor R 6  has a sixth resistance value R 6  which is equal to the fifth resistance value R 5  of the fifth resistor R 5 . The third output voltage V REF3  is given by: ##EQU3## 
     Inasmuch as the first and the second collector currents I 1  and I 2  are proportional to the absolute temperature T, the difference base emitter voltage ΔV BE  is proportional to the absolute temperature T. The difference base emitter voltage ΔV BE  has a positive temperature characteristic. On the other hand, the first base emitter voltage V BE1  has a negative temperature characteristic which is, for example, approximately equal to -2 mV/°C. As a result, the third output voltage V REF3  may have a positive, negative, or zero temperature characteristic. 
     Referring to FIG. 10, the description will proceed to a reference voltage circuit according to a sixth embodiment of this invention. Similar parts are designated by like reference numerals. 
     The second transistor Q 2  has the second base electrode connected to the first base electrode of the first transistor Q 1 . The fifth transistor Q 5  has the fifth collector electrode connected to the second collector electrode of the second transistor Q 2 . The sixth transistor Q 6  has the sixth collector electrode connected to the sixth base electrode of the sixth transistor Q 6 . 
     An eleventh transistor Q 11  has an eleventh base electrode connected to the fifth collector electrode, an eleventh emitter electrode connected to the power supply terminal Vcc, and an eleventh emitter area which is equal to two times as large as the first emitter area. A twelfth transistor Q 12  has a twelfth base electrode connected to the second base electrode of the second transistor Q 2 , a twelfth collector electrode connected to the twelfth base electrode, and a twelfth emitter electrode grounded. The twelfth transistor Q 12  has a twelfth emitter area which is equal to the eleventh emitter area. 
     A seventh resistor R 7  is connected between ground and the second emitter electrode of the second transistor Q 2 . The seventh resistor R 7  has a seventh resistance value R 7 . An eighth resistor R 8  is connected between an eleventh collector electrode of the eleventh transistor Q 11  and a twelfth collector electrode of the twelfth transistor Q 12 . The eighth resistor R 8  has an eighth resistance value R 8 . A fourth output voltage terminal T 4  is connected to a node of the eighth resistor R 8  and the eleventh collector electrode of the eleventh transistor Q 11 . The fourth output voltage terminal T 4  is supplied with a fourth output voltage V REF4 . It will be assumed that the twelfth transistor Q 12  has a twelfth base emitter voltage V BE12  and ΔV BE  represents a difference base emitter voltage between the second and the twelfth base emitter voltages V BE2  and V BE12 . The fourth output voltage V REF4  is given by: ##EQU4## 
     The difference base emitter voltage ΔV BE  has a positive temperature characteristic. On the other hand, the twelfth base emitter voltage V BE12  has a negative temperature characteristic. As a result, the fourth output voltage V REF4  may have a positive, negative, or zero temperature characteristic. 
     Referring to FIGS. 11, 12, and 13, the description will proceed to a reference current circuit according to a seventh embodiment of this invention. 
     The reference current circuit comprises a plurality of metal oxide semiconductor (MOS) field effect transistors (FET) which will hereafter be called MOS transistors. 
     In FIG. 11, the reference current circuit comprises a pair of first and second MOS transistors M 1  and M 2 , a pair of third and fourth MOS transistors M 3  and M 4 , and the first and the second resistors R 1  and R 2 . 
     The first MOS transistor M 1  has a first source electrode grounded and a first transconductance. The second MOS transistor M 2  has a second gate electrode connected to a first drain electrode of the first MOS transistor M 1 , a second source electrode grounded, and a second transconductance. The second transconductance is equal to four times as large as the first transconductance. 
     The third MOS transistor M 3  has a third gate electrode connected to a second drain electrode of the second MOS transistor M 2  and a third source electrode connected to a power supply terminal V DD . The power supply terminal V DD  is supplied with a power supply voltage from a power supply unit (not shown). The third MOS transistor M 3  has a third transconductance which is equal to the first transconductance. The fourth MOS transistor M 4  has a fourth gate electrode connected to a third drain electrode of the third MOS transistor M 3  and a fourth drain electrode connected to a first gate electrode of the first MOS transistor M 1 . The fourth MOS transistor M 4  has a fourth source electrode connected to the power supply terminal V DD  and a fourth transconductance which is equal to the second transconductance. 
     The first resistor R 1  is connected between the first drain electrode and the first gate electrode and has a first resistance value R 1 . The second resistor R 2  is connected between the second drain electrode and the second gate electrode and has a second resistance value R 2  which is equal to the first resistance value. The transconductance is approximately equal to a gate (L/W) ratio. 
     A first voltage drop is caused across the first register R 1  when a first drain current flows in the first resistor R 1 . A second voltage drop is caused across the second resistor R 2  when a second drain current flows in the resistor R 2 . Each of the first and the second resistors R 1  and R 2  has a common temperature. Each of the first and the second voltage drops is substantially equal to a thermal voltage in the common temperature. 
     The MOS transistor may be operated in a saturation area. It is assumed that the MOS transistor has n channels and a transconductance β n . In this event, a drain current I Di  is given by a following equation (13) in the saturation area of the MOS transistor. 
     
         I.sub.Di =K.sub.j β.sub.n (V.sub.GSi -V.sub.TH).sup.2 (13) 
    
     where K j  represents an ability ratio or transconductance ratio to a unit MOS transistor, V GSi  represents a gate source voltage, V TH  represents a threshold voltage, β n  is given by [μ n  (C ox  /2)(W/L)], μ n  represents an effective mobility of carrier, C ox  represents a capacity of gate oxide film per unit area, W represents a width of gate electrode, and L represents a length of gate electrode. 
     The first MOS transistor M 1 , the second MOS transistor M 2 , and the first resistor R 1  are shown in FIG. 12. It will be assumed that I D1  represents the first drain current of the first MOS transistor M 1 , I D2  represents the second drain current of the second MOS transistor M 2 , K 2  represents a transconductance ratio of the second MOS transistor M 2  to the first MOS transistor M 1 , V GS1  represents a first gate source voltage of the first MOS transistor M 1 , V GS2  represents a second gate source voltage of the second MOS transistor M 2 , and ΔV GS  represents a difference gate source voltage between the first and the second gate source voltages V GS1  and V GS2 . The first drain current I D1 , the second drain current I D2 , and the difference gate source voltage ΔV GS  are given by following equations (14), (15), and (16). 
     
         I.sub.D1 =β.sub.n (V.sub.GS1 -V.sub.TH).sup.2         (14) 
    
     
         I.sub.D2 =K.sub.2 β.sub.n (V.sub.GS2 -V.sub.TH).sup.2 (15) 
    
     
         ΔV.sub.GS =V.sub.GS1 -V.sub.GS2 =I.sub.D1 R.sub.1    (16) 
    
     A following equation (17) is given by the equations (14) , (15), and (16). ##EQU5## where I D1  is given by [I D1  ≦1/(R 1   2  β n )]. 
     A curved line C in FIG. 4 shows a relation of I D1  and I D2  in the equation (17). As shown in FIG. 13, I D2  has a peak point P 2 . 
     On the assumption that (dI D2  /dI 1 )=0 in the equation (17), I D1  is given by a following equation (18). 
     
         I.sub.D1 =1/(R.sub.1.sup.2 β.sub.n), 1/4R.sub.1.sup.2 β.sub.n(18) 
    
     Consequently, a peak value I D2P  of the drain current I D2  is given by a following equation (19). 
     
         I.sub.D2P =1/(16R.sub.1.sup.2 β.sub.n)=(K.sub.2 /4)I.sub.D1(19) 
    
     In FIG. 11, it will be assumed that K 2  is equal to four, the first resistance value R 1  of the first resistor R 1  is equal to the second resistance value R 2  of the second resistor R 2 , and each of the first voltage drop across the first resistor R 1  and the second voltage drop across the second resistor R 2  is substantially equal to the thermal voltage in the absolute temperature T. In this case, each of the first through the fourth MOS transistors M 1  to M 4  has a common operating point which is equal to the peak point P 2 . Consequently, when a first change of I D1  and a second change of I D2  are caused by Early voltage effect in response to a change of the power supply voltage, the first change of I D1  and the second change of I D2  counteract each other. As a result, the reference current circuit is capable of preventing occurrence of a difference drain current of I D1  and I D2 . 
     The transconductance β n  is given by a following equation (20). 
     
         β.sub.n =β.sub.0 (T/To).sup.-3/2                 (20) 
    
     where β 0  represents a transconductance in a temperature (300° K.). A relation of (1/β n ) and an absolute temperature T is shown in FIG. 14. 
     A differential temperature coefficient [TC F  (β n )] of β n  in the temperature (300° K.) is equal to -5,000 ppm/°C. A differential temperature coefficient [TC F  (V T )] of V T  is positive. The differential temperature coefficient [TC F  (β n )] is negative and an absolute value which is equal to 1.5 times as large as an absolute value of the differential temperature coefficient [T CF (V T )]. As shown in the equations (18) and (19), each of the drain currents I D1  and I D2  is proportional to (1/β n ). Consequently, a differential temperature coefficient [TC F  (1/β n )] is equal to 5,000 ppm/°C. in the temperature (300° K.). 
     Referring to FIG. 15, the description will proceed to a reference voltage circuit according to an eighth embodiment of this invention. Similar parts are designated by like reference numerals. 
     The reference voltage circuit further comprises the third resistor R 3  and the first output voltage terminal T 1  in the reference current circuit illustrated in FIG. 11. The third resistor R 3  is connected between the first gate electrode of the first MOS transistor M 1  and the fourth drain electrode of the fourth MOS transistor M 4 . The first output voltage terminal T 1  is connected to the node of the third resistor R 3  and the fourth drain electrode of the fourth MOS transistor M 4 . The first output voltage terminal T 1  is supplied with a first output voltage V REF1 . 
     On the assumption that I D1  =I D2 , a following equation (21) is given. ##EQU6## 
     On the assumption that V TH  ≈0.7 V, V TH  has a temperature characteristic which is approximately equal to -2.3 mV/°C. Also, a voltage drop (I 1  R 1 ) has a positive temperature characteristic. Consequently, the first output voltage V REF1  may have a positive, negative, or zero temperature characteristic. 
     Referring to FIG. 16, the description will proceed to a reference voltage circuit according to a ninth embodiment of this invention. Similar parts are designated by like reference numerals. 
     The reference voltage circuit further comprises the fourth resistor R 4  and the second output voltage terminal T 2  in the reference voltage illustrated in FIG. 15. The fourth resistor R 4  is connected between the second drain electrode of the second MOS transistor M 2  and the third gate electrode of the third MOS transistor M 3 . The second output voltage terminal T 2  is connected to the node of the fourth resistor R 4  and the second drain electrode of the second MOS transistor M 2 . The second output voltage terminal T 2  is supplied with the second output voltage V REF2 . The second output voltage V REF2  may have a positive, negative, or zero temperature characteristic which is independent relative to the temperature characteristic of the first output voltage V REF1 . The third and the fourth resistors R 3  and R 4  have third and fourth resistance values R 3  and R 4 . 
     Referring to FIG. 17, the description will proceed to a reference current circuit according to a tenth embodiment of this invention. Similar parts are designated by like reference numerals. 
     A fifth MOS transistor MS has a fifth drain electrode connected to the second drain electrode of the second MOS transistor M 2 , a fifth source electrode connected to the power supply terminal V DD , and a fifth transconductance which is equal to the first transconductance. A sixth MOS transistor M 6  has a sixth gate electrode connected to a fifth gate electrode of the fifth MOS transistor MS, a sixth drain electrode connected to the first gate electrode of the first MOS transistor M 1 , a sixth source electrode connected to the power supply terminal V DD , and a sixth transconductance which is equal to the first transconductance. 
     A seventh MOS transistor M 7  has a seventh source electrode connected to the power supply terminal V DD , a seventh gate electrode connected to the fifth gate electrode of the fifth MOS transistor MS, and a seventh drain electrode connected to the seventh gate electrode. An eighth MOS transistor M 8  has an eighth source electrode grounded, an eighth gate electrode connected to the second drain electrode of the second MOS transistor M 2 , and an eighth drain electrode connected to the seventh drain electrode of the seventh MOS transistor M 7 . 
     A ninth MOS transistor M 9  has a ninth source electrode connected to the power supply terminal V DD , a ninth gate electrode connected to the seventh gate electrode of the seventh MOS transistor M 7 , and a ninth source electrode connected to the output current terminal To which is supplied with the output current Io. The ninth MOS transistor M 9  has a ninth transconductance which is equal to the first transconductance. A tenth MOS transistor M 10  has a tenth source electrode grounded, a tenth gate electrode connected to the eighth gate electrode of the eighth MOS transistor M 8 , and a tenth drain electrode connected to the input current terminal Ti which is supplied with the input current Ii. 
     Inasmuch as the first and the second drain currents I D1  and I D2  are controlled by the seventh and the eighth MOS transistors M 7  and M 8 , the first and the second drain currents I D1  and I D2  are held at a constant current value even when the power supply voltage is changed. 
     Referring to FIG. 18, the description will proceed to a reference voltage circuit according to an eleventh embodiment of this invention. Similar parts are designated by like reference numerals. 
     The fifth resistor R 5  is connected between the first gate drain electrode of the first MOS transistor M 1  and the sixth drain electrode of the sixth MOS transistor M 6 . The fifth resistor R 5  has a fifth resistance value R 5 . A third output voltage terminal T 3  is connected to a node of the fifth resistor R 5  and the sixth drain electrode of the sixth MOS transistor M 6 . The third output voltage terminal T 3  is supplied with a third output voltage V REF3 . The sixth resistor R 6  is connected between the second drain electrode of the second MOS transistor M 2  and the fifth drain electrode of the fifth MOS transistor M 5 . The sixth resistor R 6  has a sixth resistance value R 6  which is equal to the fifth resistance value R 5  of the fifth resistor R 5 . The third output voltage V REF3  is given by: ##EQU7## 
     As illustrated in the equation (21), the third output voltage V REF3  may have a positive, negative, or zero temperature characteristic. 
     Inasmuch as the first and the second drain currents I D1  and I D2  are controlled by the seventh and the eighth MOS transistors M 7  and M 8 , the first and the second drain currents I D1  and I D2  are held at the constant value even when the power supply voltage is changed. 
     Referring to FIG. 19, the description will proceed to a reference voltage circuit according to a twelfth embodiment of this invention. Similar parts are designated by like reference numerals. 
     The second MOS transistor M 2  has the second gate electrode connected to the first gate electrode of the first MOS transistor M 1 . The fifth MOS transistor M 5  has the fifth drain electrode connected to the second drain electrode of the second MOS transistor M 2 . The sixth MOS transistor M 6  has the sixth drain electrode connected to the sixth gate electrode of the sixth MOS transistor M 6 . 
     The eleventh MOS transistor M 11  has an eleventh gate electrode connected to the fifth drain electrode, an eleventh source electrode connected to the power supply terminal V DD , and an eleventh transconductance which is equal to the first transconductance. A twelfth MOS transistor M 12  has a twelfth gate electrode connected to the second gate electrode of the second MOS transistor M 2 , a twelfth drain electrode connected to the twelfth gate electrode, and a twelfth source electrode grounded. The twelfth MOS transistor M 12  has a twelfth transconductance which is equal to the eleventh transconductance. 
     The seventh resistor R 7  is connected between ground and the second source electrode of the second MOS transistor M 2 . The seventh resistor R 7  has a seventh resistance value R 7 . The eighth resistor R 8  is connected between an eleventh drain electrode of the eleventh MOS transistor M 11  and a twelfth drain electrode of the twelfth MOS transistor M 12 . The eighth resistor R 8  has an eighth resistance value R 8 . The fourth output voltage terminal T 4  is connected to a node of the eighth resistor R 8  and the eleventh drain electrode of the eleventh MOS transistor M 11 . The fourth output voltage terminal T 4  is supplied with a fourth output voltage V REF4 . It will be assumed that the twelfth MOS transistor M 12  has a twelfth gate source voltage V GS12  and ΔV GS  represents a difference gate source voltage between the second and the twelfth gate source voltages V GS2  and V GS12 . 
     Inasmuch as a twelfth drain current I D12  is the first or the second drain current I D1  or I D2 , the twelfth drain current I D12  is given by a following equation (23). 
     
         I.sub.D12 =β.sub.n (V.sub.GS1 -V.sub.TH).sup.2        (23) 
    
     Also, V GS12  is given by a following equation (24). 
     
         ΔV.sub.GS12 =V.sub.GS1 -V.sub.GS2 =R.sub.1 I.sub.D2  (24) 
    
     A following equation (25) is given by the equations (14), (15), (23), and (24). ##EQU8## 
     Also, the fourth output voltage V REF4  is given by a following equation (26). ##EQU9## 
     As illustrated in the equation (21), the fourth output voltage V REF4  may have a positive, negative, or zero temperature characteristic.