Patent Publication Number: US-10788848-B2

Title: Voltage regulator with controlled current consumption in dropout mode

Description:
TECHNICAL FIELD 
     The present invention generally relates to voltage regulator circuits and, in particular, to a low dropout (LDO) voltage regulator circuit having a controlled current consumption in dropout mode. 
     BACKGROUND 
     Low dropout (LDO) voltage regulators are widely used devices in electronic systems. The main benefit of an LDO-type regulator is the ability to keep the output voltage VOUT regulated even if the difference between the input voltage VIN and the output voltage VOUT is very low (for example, about 100 mV). If the input voltage VIN is sufficiently high, the output voltage VOUT is at nominal level and the regulator operates in a closed loop state. This regulation mode can be considered as the main operating condition of the LDO voltage regulator where the operating points of the circuit are well set with a low overall current consumption. However, if the input voltage VIN drops, the LDO voltage regulator can pass to an open loop operating state (referred to in the art as the dropout condition or dropout mode). This open loop state is characteristic with a significant change of the operating point, especially relating to the gate to source voltage (VGS) of the power MOSFET transistor which can increase up to the input voltage VIN level. In the high performance LDO voltage regulator, the bias (or quiescent) current of power MOSFET transistor usually depends on the VGS. If the VGS increases in the dropout mode, then the bias current increases as well. 
     The increased bias current consumption of the voltage regulator can be a significant concern. As an example, consider a system which includes an LDO voltage regulator that is powered from a battery. As the battery discharges, the input voltage VIN supplied from the battery drops, and the operating state of the LDO voltage regulator passes from the closed loop (regulation mode) state to the open loop (dropout mode) state. The VGS of the power MOSFET transistor increases in the dropout mode causing a corresponding increase in the bias current which can quickly deplete the remaining charge stored in the battery. This behavior is undesired and it can compromise the system operating time or it can even threaten the battery safety. 
     Because the dropout mode condition has to be considered as a standard circuit operating state, it is necessary to keep the current consumption under control in this mode. This can be achieved by a circuit that is able to detect the dropout condition and to limit the quiescent current of important circuit branches of the regulator circuit in this condition. 
     There is a need in the art for a solution for maintaining the LDO voltage regulator current consumption low (controlled) in the dropout condition. 
     SUMMARY 
     To address the problem with controlling current consumption (i.e., quiescent current) of an LDO regulator in the dropout condition, a circuit monitors the operation of the regulator circuit and intervenes when the regulation loop is near or inside the dropout condition. The quiescent current control in the dropout mode is necessary because this mode can occur in the normal course of regulator operation and can remain in place for a long time. Without the intervention of the circuit, the quiescent current of the LDO regulator in the dropout mode can increase, for example by an order of magnitude, even if the load current (ILOAD) is zero. The intervention circuit is useful and applicable inside the differential amplifier (OPAMP) of the LDO regulator. It is especially suited for OPAMP circuits being adaptively biased proportionally to the load current. This is the case with most high performance LDO regulators where the bias current of the output driver stage and other stages of the differential amplifier depends on the load current. The relationship between the load current and the driver bias current is usually realized through the VGS of the power MOSFET. In the closed loop (regulation mode) condition, the VGS of the power MOSFET (being in saturation region) is relatively low. Consequently, the driver bias current is low. In the open loop (dropout mode) condition, however, the VGS of the power MOSFET is maximized by the driver. This results in a significant increase in the driver bias current even if the load current is zero. A voltage regulator with an intervention circuit as provided herein allows for keeping the quiescent current in the dropout mode at a similar value to the closed loop condition. This is accomplished by having the intervention circuit monitor the operational status of the driver stage for the OPAMP by comparing the differential voltage VDIF generated by the OPAMP and the gate drive voltage of the power transistor. If the voltage difference is sufficiently low then the intervention circuit does not influence regulator operation. However, in the case where the voltage difference is too high, the quiescent bias current of the output stage and other stages of the OPAMP is limited by the intervention circuit. 
     In an embodiment, a voltage regulator comprises: an input terminal configured to receive an input voltage; an output terminal configured to supply an output voltage; a power transistor having a first conduction terminal coupled to the input terminal, a second conduction terminal coupled to the output terminal, and a control terminal; a differential amplifier having: a first stage with a first input configured to receive a reference voltage, a second input configured to receive a feedback voltage derived from the output voltage, and an output configured to provide a drive signal based on a first difference in voltage between the reference voltage and the feedback voltage; and a second stage with a driver circuit comprising a variable impedance circuit coupled to the control terminal of said power transistor, and a driver transistor having a first conduction terminal coupled to the control terminal of said power transistor, and a control terminal configured to receive the drive signal; and a dropout detector and quiescent current limiter circuit configured to sense a second difference in voltage between a voltage of the drive signal and a voltage at the control terminal of said power transistor and modify an impedance of the variable impedance circuit in response to the sensed second difference. 
     In an embodiment, a circuit comprises: a low dropout voltage regulator circuit that operates in a closed loop regulation mode and an open loop dropout mode, the low dropout voltage regulator circuit comprising: an amplifier stage configured to generate a drive signal in response to a first difference in voltage between an output voltage of the low dropout voltage regulator circuit and a reference voltage; a drive stage having a quiescent current consumption and configured to generate a control signal in response to the drive signal; and a power transistor having a control terminal configured to receive the control signal; and a dropout detector and quiescent current limiter circuit configured to sense a second difference in voltage between the drive signal and the control signal that is indicative of the low dropout voltage regulator circuit operating in the open loop dropout mode and in response thereto limit the quiescent current consumption of the drive stage. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       For a better understanding of the embodiments, reference will now be made by way of example only to the accompanying figures in which: 
         FIG. 1  is a circuit diagram of a prior art low dropout voltage regulator; 
         FIG. 2  is a circuit diagram of a prior art low dropout voltage regulator with current consumption control; 
         FIG. 3  is a circuit diagram of a low dropout voltage regulator with current consumption control; and 
         FIGS. 4-5  show simulation results for operation of the circuit of  FIG. 3 . 
     
    
    
     DETAILED DESCRIPTION 
     Reference is now made to  FIG. 1  which shows a circuit for a prior art voltage regulator  10  (see, FIG. 1 of U.S. Pat. No. 9,645,594, incorporated herein by reference). The voltage regulator  10  includes an input terminal  12  configured to receive an input voltage VIN (decoupled by an input capacitance CIN), an output terminal  14  configured to supply an output voltage VOUT, and an n-channel MOSFET power transistor MPower having a source conduction terminal coupled to the input terminal  12 , a drain conduction terminal coupled to the output terminal  14  and a control (gate) terminal coupled to node  16 . An input (or first) stage of a differential amplifier  30  has a first input configured to receive a voltage reference VREF and a second input configured to receive a feedback signal VFB which is derived from the output voltage VOUT. An output of the input stage of the differential amplifier  30  generates a drive signal VDIF based on a voltage difference between the voltage reference VREF and the feedback signal VFB. 
     A constant current source ITAIL is coupled to bias the input stage of the differential amplifier  30 . The current source ITAIL is coupled between the input terminal  12  and first pair of n-channel MOSFET differential input transistors M 1 , M 2  for the differential amplifier  30 . The transistors M 1 , M 2  are coupled to a second pair of p-channel MOSFET load transistors M 3 , M 4 , respectively, for the input stage. The gates (control terminals) of the first pair of transistors M 1 , M 2  define the first and second inputs (for the signals VREF and VFB) of the differential amplifier  30  input stage. The second pair of transistors M 3 , M 4  is configured as a current mirror, and the output VDIF is taken at the common drain terminals of transistors M 2  and M 4 . 
     More particularly, the transistor M 1  has a source conduction terminal coupled to the constant current source ITAIL, a control terminal forming the first input that is coupled to a voltage reference (for example, a bandgap voltage generator) providing the reference voltage VREF, and a drain conduction terminal. The transistor M 2  has a source conduction terminal coupled to the constant current source ITAIL, a control terminal forming the second input that receives the feedback signal VFB, and a drain conduction terminal coupled to the output that provides the drive signal VDIF. 
     The transistor M 3  has a drain conduction terminal coupled to the drain conduction terminal of the transistor M 1 , a control terminal, and a source conduction terminal coupled to ground. The transistor M 4  has a drain conduction terminal coupled to the drain conduction terminal of the transistor M 2  (where the signal VDIF is generated), a control terminal coupled to both the drain conduction terminal and the control terminal of the transistor M 3 , and a source conduction terminal coupled to ground. The drive signal VDIF is filtered by a compensation filter circuit formed by series connected resistor Rc and capacitor Cc to ensure stable operation. 
     An output (or second) stage of the differential amplifier  30  includes an inverting driver circuit  50  formed by an impedance circuit device X 2   nd  coupled to the control terminal of the power transistor MPower at node  16  and an n-channel MOSFET driver transistor M 2   nd . The output stage provides several functions—signal amplification, level shifting and power MOSFET driving. The driver transistor M 2   nd  is an n-channel MOSFET having a drain conduction terminal coupled to the control terminal of the power transistor Mpower at node  16 , a source conduction terminal coupled to a ground GND reference voltage, and a control terminal configured to receive the drive signal VDIF from the differential amplifier  30  input stage so as to vary a bias current I 2   nd  applied by the output stage to the control terminal of the power transistor MPower. The driver transistor M 2   nd  is loaded by the impedance circuit device X 2   nd  whose real circuit implementation depends on demanded regulation characteristics and loop stability requirements. The transconductance of driver transistor M 2   nd  together with the impedance of the impedance circuit device X 2   nd  defines the voltage gain of the output stage of the differential amplifier  30 . 
     Since the output of the driver circuit  50  is coupled to the gate terminal of the power transistor MPower at node  16 , a voltage formed across the impedance circuit device X 2   nd  represents the VGS of the power transistor. In other words, the drain current of driver transistor M 2   nd  generates a voltage drop on the impedance circuit device X 2   nd  that is used for driving the power transistor MPower. Because the impedance circuit device X 2   nd  is tied to the input voltage VIN, the voltage drop is level-shifted respect the output voltage VDIF. With changes in the load current of the voltage regulator  10  (where load current ILOAD is the current passing through the power transistor Mpower and applied to the load represented by load capacitance COUT and load impedance RLOAD), the VGS of the power transistor also changes. The relation between the load current and VGS is given by a transfer function of the power transistor MPower, where the transfer function is valid when the power transistor MPower is operating in the saturation region. This corresponds to the voltage regulator  10  operating in the closed loop or regulation mode condition. Since the impedance circuit device X 2   nd  is operating between the node  16  and the source conduction terminal of the power transistor MPower, the bias current I 2   nd  of the driver circuit  50  depends on the load current. 
     The impedance circuit device X 2   nd  may comprise any one of a number of circuit configurations as shown, including: a resistor R 1  coupled between the input voltage VIN and the node  16 ; a diode-connected MOSFET MX 1  coupled between the input voltage VIN and the node  16 ; and a series connection of a diode-connected MOSFET MX 2  and a resistor R 2  coupled between the input voltage VIN and the node  16 . The respective impedances of these three different circuit configurations of the impedance circuit device X 2   nd  are generically referenced as Rx. Consequently, the bias current I 2   nd  is based on the following relationship: I 2   nd =VGS/Rx. 
     The power transistor MPower is a p-channel MOSFET. The VGS of the power transistor MPower is varied by the drain or bias current I 2   nd  of the driver transistor M 2   nd . The VGS is thus defined by the following relationship: VGS=I 2   nd *Rx. 
     The bias current I 2   nd  is controlled by the output voltage VDIF of the differential amplifier  30  input stage. This relationship is given by the transconductance gm of the driver transistor M 2   nd , and is defined as follows: I 2   nd =gm*VDIF. 
     The feedback signal VFB is generated by a voltage divider circuit formed by resistors Rfb 1  and Rfb 2 . The feedback signal VFB is thus a scaled replica of the output voltage VOUT as given by the following: VFB=VOUT*(Rfb 2 /(Rfb 1 +Rfb 2 )). 
     The output voltage VOUT is then a scaled replica of the reference voltage VREF provided by the voltage reference. The relationship between the reference voltage VREF and the output voltage VOUT is given by the following: VOUT=VREF*((Rfb 1 +Rfb 2 )/Rfb 2 ). The feedback with the differential amplifier  30  operation assures that the feedback signal VFB equals the voltage reference VREF 
     Since the impedance circuit device X 2   nd  is operating between the control terminal and the first conduction terminal of the power transistor MPower, the bias current I 2   nd  of the driver transistor M 2   nd  depends on the load current. If the voltage difference (referred to as the drop voltage VDROP) between the input voltage VIN and the output voltage VOUT is sufficiently high, the power transistor MPower stays in the saturation region and the VGS of the power transistor is relatively low (for example, below 1 V). This results in a low bias current I 2   nd  within the driver circuit  50  and the voltage regulator  10  operates in the closed loop (regulation mode) condition. 
     However, if the voltage difference VDROP becomes too low so that the voltage regulator  10  is not able to maintain operation in the closed loop state, then operation of the power transistor MPower passes to a linear (triode) region. This corresponds to the voltage regulator  10  operating in the dropout mode condition. 
     In the dropout mode, the dependence between the load current and the VGS of the power transistor MPower is no longer given by the transfer function of the power transistor, and the VGS can reach a very high level. In fact, the driver circuit  50  can pull the control terminal of the power transistor Mpower at node  16  down to a voltage level near ground GND, and the VGS of the power transistor can approach the input voltage VIN. If the VGS increases in the dropout mode, then the bias current I 2   nd  in the output stage of the amplifier  30  increases as well. This is because the bias current I 2   nd  depends on the VGS of the power transistor. Since the driver circuit  50  operates over the VGS of the power transistor MPower, the bias current I 2   nd  can reach a very high level. In the case of VIN=5 V and a resistive load of the driver transistor M 2   nd , the bias current I 2   nd  can be five times higher than the bias at the maximum load current. This is valid even if the load current is zero when current consumption of the voltage regulator  10  should be minimal. For a battery powered electronic device, this means that when the battery becomes discharged and the voltage regulator  10  passes to the dropout mode, even more quiescent current starts to sink. 
     To address this problem,  FIG. 2  shows a circuit for a prior art voltage regulator  110  (see, FIG. 2 of U.S. Pat. No. 9,645,594, incorporated herein by reference) configured to limit quiescent current consumption when the regulator drops out of regulation in the closed loop state. Like references in  FIGS. 1 and 2  refer to like or similar components whose description will not be repeated. The voltage regulator  110  differs from the voltage regulator  10  due to the inclusion of a dropout detector and quiescent current limiter circuit  160  which operates to limit quiescent current consumption when voltage regulator  110  operation falls into the open loop condition associated with the dropout mode. 
     The dropout detector and quiescent current limiter  160  is coupled to the power transistor MPower and includes a first p-channel MOSFET transistor M 6 , a second n-channel MOSFET transistor M 7  and a bias current generator IB. The first transistor M 6  has a source conduction terminal coupled to the input terminal  12 , a drain conduction terminal coupled to the impedance circuit device X 2   nd , and a control gate terminal. The second transistor M 7  has a source conduction terminal coupled to the output terminal  14 , a drain conduction terminal and a control gate terminal, where the drain and control gate conduction terminals are coupled to each other and to the control terminal of the first transistor M 6 . The bias current generator IB is coupled between the drain/gate conduction terminals of the second transistor M 7  and ground  115  and provides a bias current. 
     The second transistor M 7  is biased by the bias current generator IB so as to define a potential at the control terminals of transistors M 6  and M 7  that is one VGS below the output voltage VOUT. Since the gate conduction terminals of the first and second transistors M 6 , M 7  are shorted together, the VGS of the first transistor M 6  is given by the following. VGS M6 =VGS M7 +VDROP. 
     This means that the higher the difference in voltage between the input voltage VIN and the output voltage VOUT, the higher the VGS overdrive of the first transistor M 6 . The VGS overdrive is an expression and parameter used to specify operation of a transistor in the linear region. If the voltage regulator  110  is operating in a closed loop condition, then the first transistor M 6  is in the linear region. In fact, the first transistor M 6  operates as a switch which does not influence the operation of the regulator circuit. 
     If the load current ILOAD is zero and the input voltage VIN is below the nominal level of the output voltage VOUT, then the voltage regulator  110  is operating in the dropout mode. In this specific case the VDROP will be zero and the following relationship is provided: VGS M6 =VGS M7 . As a result, the first and second transistors M 6 , M 7  form a current mirror and the bias current I 2   nd  of the driver circuit  50  will be given by the bias current generated by the bias current generator IB (i.e., I 2   nd =IB). 
     Operation of transistors M 6 , M 7  as a current mirror for reducing current consumption when the voltage regulator  110  is operating in the dropout mode condition will now be discussed. In the dropout mode, the power transistor MPower is operating in the linear region and may be represented by a resistance RDSON. The first and second transistors M 6 , M 7  are the same (i.e., they are replicas of each other). If the load current ILOAD is zero, then the current through the resistor RDSON is equal to the bias current provided by current source IB. This bias current can, for example, be a range of a few tens of nanoAmps, so the voltage drop across resistance RDSON is practically zero. The resistance RDSON may have a value of 1Ω, for example. With a voltage drop of practically zero across the resistance RDSON, this is equivalent to a short, which in turn provides transistors M 6  and M 7  as a current mirror. Consequently, the bias current I 2   nd  will equal the bias current IB. In other words, the driver circuit  150  is adaptively biased and this sets the maximum current which can flow through the driver circuit  150 . The bias current from the bias current generator IB is a constant current setting the maximum quiescent current. 
     If the voltage regulator  110  is operating in the dropout mode, but the load current ILOAD is not zero, there will be some voltage drop on the resistance RDSON, which is based on the following relationship: VDROP=RDSON*ILOAD, where ILOAD is the load current. Contribution from the bias current source IB is negligible. The VGS of the first transistor M 6  will be higher than the VGS of the second transistor M 7 . This will cause a certain increase in the bias current I 2   nd . The VGS of the first transistor M 6  is given by the following relationship: VGS M6 =VGS M7 +VDROP. Even though the bias current I 2   nd  will be higher than the bias current from the bias current source IB, the current is still limited. 
     By properly sizing of the first and second transistors M 6 , M 7  and the bias current generator IB it is possible to find a good compromise between the dropout mode current consumption and loop stability. Loop stability is an important factor for the sizing of the components. When the dropout detector and quiescent current limiter  160  is starting to limit the bias current I 2   nd  in the driver circuit  150 , the impedance conditions of the driver are changing significantly. 
     The dropout detector and quiescent current limiter  160  addresses the problem with high quiescent current consumption in dropout mode by sensing a voltage difference between VIN and VOUT nodes (i.e., the voltage drop across the power MOSFET) and limiting the amount of current in the driver stage (and other stages) in the dropout mode. It will be noted that this solution has some limitation especially when applied in an LDO regulator with an ultra-low dropout voltage (bellow 100 mV) at maximum load current. The limitation is related to low overdrive voltage for the transistor M 6  (in the case of low dropout voltage) along with consequent issues concerning loop stability near the dropout mode of the LDO regulator. 
     To address the foregoing limitation,  FIG. 3  shows a circuit for a voltage regulator  210  configured to limit quiescent current consumption when the regulator drops out of regulation in the closed loop state like references in  FIGS. 1, 2 and 3  refer to like or similar components whose description will not be repeated. The voltage regulator  210  differs from the voltage regulator  110  due to the inclusion of a different dropout detector and quiescent current limiter circuit  260  which operates to limit quiescent current consumption when voltage regulator  210  operation falls into the open loop condition associated with the dropout mode. Compared to the circuit  160  which operated to detect the dropout mode by monitoring voltage difference between VIN and VOUT levels, the circuit  260  instead monitors the status of the driver circuit  150  to detect the dropout mode and control quiescent current consumption. 
     The dropout detector and quiescent current limiter circuit  260  embedded into the regulator  210  is formed by an n-channel MOSFET transistor MN 1 , a bias current source IB, a CMOS logic inverter  212 , a p-channel MOSFET transistor MP 1  and resistor R 1 . The transistor MN 1  has a first conduction terminal coupled to the node  16 , a second conduction terminal, and a control gate terminal coupled to receive the signal VDIF. Thus, the transistors MN 1  and M 2   nd  share a common gate connection, with the source terminal of transistor MN 1  connected to the drain terminal of transistor M 2   nd . The body terminal of transistor MN 1  is tied to ground. The bias current source IB is coupled between the input terminal  12  and the second conduction terminal of the transistor MN 1  at node  214 . An input terminal of the CMOS logic inverter  212  is coupled at node  214  to the output of the bias current source IB and the second conduction terminal of the transistor MN 1 . The transistor MP 1  has a source conduction terminal coupled to the input terminal  12 , a drain conduction terminal coupled to the impedance circuit device X 2   nd , and a control gate terminal coupled to an output of the CMOS logic inverter  212 . The resistor R 1  is connected in parallel with the transistor MP 1 , with one terminal coupled to the input terminal  12  and another terminal coupled to the impedance circuit device X 2   nd . The resistor R 1  and impedance circuit device X 2   nd  form a variable impedance circuit whose impedance is controlled by a switching action of the transistor MP 1 . The inverter  212  is accommodated for accepting a semi-digital signal generated by transistor MN 1  and current source IB. In particular, the inverter  212  is constructed for minimal crossconductance when its input voltage is between low and high levels. The inverter  212  generates a control signal for driving the gate of transistor MP 1  and thus controlling the on/off state of transistor MP 1  functioning as a transistor switch. Turning on of transistor MP 1  shorts the resistor R 1  which in coupled in series with the impedance circuit device X 2   nd  and thus changes the impedance of the variable impedance circuit. 
     The circuit  260  functions to detect the status of the output stage of the differential amplifier  30 . When in the closed loop state for the regulation mode condition, meaning that the input voltage VIN is sufficiently high for maintaining the output voltage VOUT in regulation, the transistor M 2   nd  is in saturation mode, the transistor MN 1  has a negative VGS due to the difference in voltage between VDI and node  16 , the input of the inverter  212  at node  214  is high, the gate of transistor MP 1  is low to turn on transistor MP 1 , and the resistor R 1  is shorted. In this operational state, the circuit  260  does not influence the normal operation of the driver transistor M 2   nd  working with the impedance circuit device X 2   nd . In principle, transistor MN 1  is used for distinguishing the operation mode of the driver stage. Normally, in the regulation mode, the voltage of the signal VDIF output from the input stage of the differential amplifier  30  node is defined by the VGS of driver transistor M 2   nd  which can be around 0.8V and the voltage at node  16  is defined by the VGS of the power transistor MPower (being around 0.8V) referred to the input voltage VIN. This means that the voltage of the drain terminal of the driver transistor M 2   nd  is high, more precisely given by VIN−VGS (MP2) . As a result, driver transistor M 2   nd  is set in saturation mode. In this condition, the VGS of transistor MN 1  is negative. The drain terminal of transistor MN 1  sinks no current and the input of the inverter  212  is pulled up to the input voltage VIN level by the constant bias current source IB. The output of the inverter  212  is accordingly low to set a maximum VGS for transistor MP 1 , which turns on transistor MP 1  and shorts the resistor R 1 . 
     When the input voltage VIN drops to a level such that the loop is not able keep the output voltage VOUT regulated and the regulator is in the open loop (dropout mode) condition, significant operating point changes occur in the circuit  260 . Because the loop is trying to maintain regulation, the signal VDIF driven by the input stage of the differential amplifier  30  is pulled up and node  16  driven by the transistor M 2   nd  is pulled down. The node at which the signal VDIF is output saturates at some high level (given by construction of the differential stage) and the voltage at node  16  drops to near the GND level. The voltage difference between these two nodes (i.e., the VDIF node and node  16 ) is sensed by transistor MN 1  which turns on when a sufficient VGS (defining a threshold for comparison of the voltages VDIF and Vnode 16 ) is formed between gate and source terminals. When this happens, the drain of transistor MN 1  consumes all the bias current from bias current source IB and the voltage at the input node  214  of the inverter  212  is pulled down. In response, the output of inverter  212  goes up causing the transistor MP 1  to turn off. This will remove the short of resistor R 1 , and now resistor R 1  and impedance X 2   nd  are connected in series between the input voltage VIN and node  16 . Because the resistance value of resistor R 1  is much higher than the resistance of impedance circuit device X 2   nd  (for example, by orders of magnitude, such as R 1 =1 MΩ and X 2   nd= 20 KΩ), the current flowing through the driver circuit  50  is reduced significantly. The change of the impedance in the output stage of the differential amplifier  30  does not cause instability because the regulator is already in dropout mode and no regulation is performed. The exact detection and activation point of the circuit  260  can be tuned by sizing the transistor MN 1 . It is important to activate the current limitation only when the loop is completely open—i.e., no regulation is present. 
     The circuit as shown in  FIG. 3  has been simulated to confirm operation. Results of the simulation are depicted in  FIGS. 4-5 .  FIG. 4  shows a simulation where the load current is set to OA and  FIG. 5  shows a simulation where the load current is set to 100 mA. The nominal output voltage VOUT is 3.0V. The X-axis represents time, the left Y-axis represents voltage and the right Y-axis represents current. In this transient (time domain) simulation, the input voltage VIN is swept from 0V to 5V and the output voltage VOUT and the ground pin quiescent current IQ is monitored. Each graph shows two cases for the monitored quiescent current—one without the use of circuit  260  (IQold) and one with the use of circuit  260  (IQnew). The output voltage VOUT characteristic is plotted just once because the circuit  260  is not influencing the VOUT regulation characteristic. Instead, the circuit  260  functions to alter the quiescent current IQ significantly. Without the use of circuit  260 , in the dropout mode the quiescent current IQold level can reach current consumption over 240 uA, even with zero load current ILOAD as shown in the  FIG. 4  simulation, whereas the normal consumption in regulation mode is just about 15 uA. With use of the circuit  260 , the quiescent current IQ level in the dropout mode is decreased dramatically down to about 50 uA. 
     In the case of the simulation with a 100 mA load current as depicted in  FIG. 6 , the quiescent current IQ level in the dropout mode is even lower compared to the regulation mode. More precisely, the quiescent current IQ level is about 50 uA in the dropout mode versus about 100 uA in the regulation mode. There is some peak visible on the IQ characteristic caused by late activation of the circuit  260 . But this is inevitable because the bias current reduction cannot be activated before the circuit  210  is surely in the dropout mode. Otherwise there is a risk of oscillation. But the peak is occurring in just a small range of the input voltage VIN, and is of little to no concern given the advantage of the presence of the circuit  260  in controlling current consumption. 
     While the invention has been illustrated and described in detail in the drawings and foregoing description, such illustration and description are considered illustrative or exemplary and not restrictive; the invention is not limited to the disclosed embodiments. Other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the drawings, the disclosure, and the appended claims.