Patent Publication Number: US-8994457-B2

Title: Transimpedance amplifier

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This is a continuation-in-part application of application Ser. No. 13/226,650, filed Sep. 7, 2011, incorporated herein by reference in its entirety. 
    
    
     FIELD OF INVENTION 
     The present invention relates generally to transimpedance amplifiers. 
     DESCRIPTION OF RELATED ART 
     Transimpedance amplifiers (TIAs) are often used to convert an input current signal and into a corresponding output voltage signal. Typical TIAs are often used in systems that receive a current signal from a sensor device. The output current signal from the sensor device is received by the TIA and converted into a corresponding voltage signal that may be processed by a processor. For example, optical receivers often include a photodiode device that outputs a current signal in response to being exposed to a source of radiation such as light. The TIA receives the current signal output from the photodiode, converts the current signal into a corresponding voltage signal, and outputs the voltage signal. The voltage signal may be amplified by an amplifier, such as a linear amplifier that outputs the amplified voltage signal to a clock and data recovery block. The clock and data recovery block converts the amplified voltage into a digital data signal and recovers an associated clock signal from the data rate of the digital data. The data signal and the clock signal may be output to a processor device or logic circuit. 
     BRIEF SUMMARY 
     According to one embodiment a method of forming a circuit includes forming a transimpedance amplifier having a first input node and a second input node. The method also includes forming a feedback circuit having a first transistor having a drain terminal connected to the first input node, a source terminal, and a gate terminal, a second transistor having a drain terminal connected to the second input node, a source terminal, and a gate terminal, and a third transistor having a drain terminal connected to the source terminal of the first transistor and the source terminal of the second terminal. 
     According to another embodiment a method of forming a circuit includes forming a transimpedance amplifier having a first input node, a second input node, a first output node, and a second output node. The method includes forming a feedback circuit comprising a first transistor, a second transistor, and a third transistor. The method also includes connecting a drain terminal of the first transistor to the first input node, connecting a drain terminal of the second transistor to the second input node, and connecting a drain terminal of the third transistor to a source terminal of the first transistor and a source terminal of the second transistor. The method further includes forming an amplifier having a first input node connected to the first output node of the transimpedance amplifier, a second input node connected to the second output node of the transimpedance amplifier, and an output node. 
     According to yet another embodiment a method of using a transimpedance amplifier includes receiving an input current signal from a current output device by the transimpedance amplifier. The method also includes drawing a feedback current signal from the current output device by a feedback circuit, outputting a voltage output signal from the transimpedance amplifier based on the input current signal, and filtering the voltage output signal to create a voltage feedback signal which is input into the feedback circuit. The output of the current output device consists of the input current signal and the feedback current signal and the feedback circuit is configured to determine a magnitude of the feedback current signal based on the voltage feedback signal. 
     Additional features and advantages are realized through the techniques of the present invention. Other embodiments and aspects of the invention are described in detail herein and are considered a part of the claimed invention. For a better understanding of the invention with the advantages and the features, refer to the description and to the drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
       The subject matter which is regarded as the invention is particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The forgoing and other features, and advantages of the invention are apparent from the following detailed description taken in conjunction with the accompanying drawings in which: 
         FIG. 1  illustrates a prior art example of a circuit. 
         FIG. 2  illustrates a block diagram of an exemplary embodiment of an optical receiver system. 
         FIG. 3  illustrates a block diagram of an exemplary embodiment of a portion of the system of  FIG. 2 . 
         FIG. 4  illustrates a circuit diagram of an exemplary embodiment of a TIA and differential circuit. 
         FIG. 5  illustrates a graph of the V FB  to I FB  characteristic of the circuit illustrated in  FIG. 4 . 
         FIG. 6  illustrates an exemplary embodiment of a single-ended TIA with a CMOS inverter and a CMOS inverter transconductor circuit. 
         FIG. 7  illustrates a graph of the V FB  to I FB  characteristic of the illustrated embodiment in  FIG. 6 . 
         FIG. 8  illustrates a flowchart diagram of a method for forming a circuit in accordance with an exemplary embodiment. 
         FIG. 9  illustrates a flowchart diagram of a method of using a transimpedance amplifier in accordance with an exemplary embodiment. 
     
    
    
     DETAILED DESCRIPTION 
     To reliably convert an input current into a digital output, the average, or DC input current is determined and used as a threshold to differentiate input currents below the average (digital 0s) from input currents above the average (digital 1s). Removing the DC input current is known as level restoration, as it restores the DC level to zero to provide the threshold. Any DC input offset voltage that exists in a transimpedance amplifier (TIA) or amplifier such as, for example, a limiting amplifier, should also be compensated since the input offset voltage effectively shifts the threshold between 0 and 1. A preferred threshold has the greatest possible distance between the 0 and 1 levels, which allows the greatest space for signal noise or other non-idealities to corrupt the signal without resulting in errors in the received data. The space between the threshold and the 0 and 1 levels is called the noise margin. If the threshold is not optimally set, the noise margin may be degraded and the probability of an error increases (i.e. the bit error rate (BER) increases). 
     A feedback loop is often used to provide level restoration and DC offset compensation in a circuit with a TIA and limiting amplifier (LA). In this regard, the feedback loop measures the DC level at the output of the LA and returns a proportional signal to the input of the TIA, which forces the output DC level to either a reference voltage (for a single ended output) or to a differential zero (for a differential output). The output DC level is forced to an ideal threshold, thereby level restoring the input DC current and compensating for the TIA and LA DC input offsets, maximizing the noise margin, and minimizing the BER. 
       FIG. 1  illustrates a prior art example of a circuit  100  with a TIA  104  and LA  106  circuit with a low pass filter (LPF) arrangement  102 . The feedback loop may be implemented using low pass filter  102  such as, for example, a resistor capacitor (RC). The LPF  102  extracts the DC content of the output and returns the DC content to the TIA  104  to be subtracted from the input DC level and the TIA and LA DC offset. The TIA  104  has two inputs, with one input connected to the input device  108  and the second input connected to the feedback loop. The subtraction of the DC content occurs within the TIA  104 . 
     In prior art examples of complementary metal oxide semiconductor (CMOS) TIA circuits, an additional NMOS transistor (not shown) may be used to subtract the DC input current and any DC offset in the TIA. When such a circuit is used in an analog feedback system, the circuit performs poorly because the feedback loop gain depends on the bias point of the NMOS transistor. The varying feedback loop gain causes the frequency response of the feedback loop to change as the DC input current and the TIA and LA offsets vary, which negatively affects the circuit performance in an analog feedback system. The circuit arrangement may only subtract current from the input node, thus providing level restoration only when the input DC current is positive (flowing into the input node). When the DC current is negative (flowing out of the input node) the circuit cannot provide level restoration. 
       FIG. 2  illustrates a block diagram of an exemplary embodiment of an optical receiver system  200 . The system  200  includes a TIA  202 , an amplifier  204 , that may include an amplifier such as, for example, a limiting amplifier, a clock and data recovery block (CDR)  206 , a current output device  208  that may include any type of device that outputs a current such as, for example, a photo diode, and a feedback circuit  210  that receives a feedback voltage (V FB ) from a low pass filter (LPF)  205 . The LPF  205  may be connected to either the output of the amplifier  204  or the output of the TIA  202 . The features of the system  200  may be arranged as separate components or with any combination of features arranged as integrated components in an integrated circuit chip. In the illustrated embodiment, the system  200  outputs signals to a processor device or logic circuit  212  that may also be included on in integrated circuit or on a separate circuit or device. 
     In operation, the current output device  208  outputs a current signal (I IN ) to the TIA  202  and the feedback circuit  210 . The TIA  202  converts I IN  into corresponding voltage signal (V out )that is output to the amplifier  204 . The amplifier  204  amplifies the V out  signal and outputs an amplified signal V outAMP  to the CDR  206 . The V outAMP  signal (or in alternate embodiments, the V out  signal from the TIA  202 ) DC content is measured by the LPF  205  and the DC content (signal V FB ) is sent to the feedback circuit  210 . The CDR  206  converts the amplified voltage into a digital data signal and recovers an associated clock signal from the data rate of the digital data. The CDR outputs a data signal V data  and a clock signal V clock  to the processor  212 . 
       FIG. 3  illustrates a block diagram of an exemplary embodiment of a portion of the system  200 . In this regard, the system  200  is implemented as a circuit having I IN−  and I IN+  inputs. In the illustrated embodiment, the I IN+  input may be connected to the current output device  208  (of  FIG. 2 ) and the I IN−  input may be floating. The TIA  202  outputs signals V OUT+  and V OUT−  where the V OUT+  signal may be connected to the amplifier  204  (of  FIG. 2 ) and the V OUT−  signal may be floating, alternatively both V OUT+  and V OUT−  may be connected to the amplifier  204  as a differential signal V OUT . The feedback circuit  210  in the illustrated embodiment includes a first transistor (T D1 )  302  that is connected to the I IN−  node  301  and a second transistor (T D2 )  304  that is connected to the I IN+  node  303 . A third transistor (T T )  306  is biased by a bias voltage (V BIAS ) (e.g., a bias voltage source such as a constant or relatively constant voltage) and is connected to the T D1    302  and the T D2    304  at a node  305 . Transistors T D1    302 , T D2    304 , and T T    306  may include any type of transistor, for example, including but not limited to, bipolar transistors and field effect transistors. For the embodiments described herein, though the figures and descriptions include field effect transistors, one of ordinary skill in the art would understand that any of the field effect transistors may be replaced with a variety of other types of transistors, such as, for example, bipolar transistors in alternate embodiments. In this regard, the source, drain, and gate terminals of the field effect transistors described herein correspond to emitter, collector, and base terminals respectively for embodiments that include bipolar transistors and may be used interchangeably when describing the embodiments. The use of the terms source, drain, and gate terminals is thus not limiting to embodiments that include only field effect transistors and may include terminals for any similar corresponding transistor terminals (e.g., emitter, collector, and base terminals respectfully) for other types of transistors understood by one of ordinary skill in the art. In operation, the V BIAS  applied to the T T    306  provides a constant current I TAIL . The I TAIL  is steered by the input voltages V FB+  and V FB−  through the transistors T D1    302  and T D2    304  to produce currents I FB+  and I FB− . The currents I FB+  and I FB−  subtract from the currents I IN+  and I IN−  at the nodes  303  and  301  respectively, to remove the DC input current and to provide level restoration. The arrangement may also be used to compensate for DC offsets in the TIA  202  and the amplifier  204 . 
       FIG. 4  illustrates a circuit diagram of an exemplary embodiment of a TIA  402  and feedback circuit  410  that correspond to the TIA  202  and feedback circuit  210  of the system  200  (of  FIG. 2 ). In this regard, the TIA  402  is a CMOS inverter TIA that include a first single-ended inverter portion  414  and a second single-ended inverter portion  416 . The first single-ended inverter portion  414  includes transistors M P1    418  and M N1    420 , and a resistor R F1    422 . The second single-ended inverter portion  416  includes transistors M P2    424  and M N2    426 , and a resistor R F2    428 . 
     The feedback circuit  410  includes differential pair transistors M D1    430  and M D2    432  and a tail transistor M T    434 . The V OUT−  node  401  is connected to the resistor R F1    422  and the drain terminals of the M P1    418  and M N1    420 . The I IN+  node  403  is connected to the gate terminals of the M P1    418  and M N1    420 , the R F1 , and the drain terminal of the M D1    430 . The V OUT+  node  405  is connected to the resistor R F2    228  and the drain terminals of the M P2    424  and M N2    426 . The I IN−  node  407  is connected to the gate terminals of the M P2   424  and M N2    426 , the R F2    228  and the drain terminal of the M D2    432 . The node  409  is connected to the drain terminal of the M T    434  and the source terminals of the M D1    430  and M D2    432 . The M T    434  receives a bias voltage V BIAS  the gate terminal. The node  401  (V OUT− ) outputs V OUT−  and may be connected to an amplifier, such as, for example, amplifier  202  (of  FIG. 2 ). A low pass filter LPF, such as, for example the LPF  205  (of  FIG. 2 ) may receive V OUT−  prior to, or following amplification (e.g., V outAMP  output by the amplifier  204 ) and is connected to the gate terminal of the MD 1   430 , which provides V FB−  to the M D1    430 . The node  405  (V OUT+ ) outputs V OUT+  and may be connected to an amplifier, such as, for example, amplifier  202  (of  FIG. 2 ). A low pass filter LPF, such as, for example the LPF  205  (of  FIG. 2 ) may receive V OUT+  prior to, or following amplification (e.g., V outAMP ) and is connected to the gate terminal of the M D2    432 , which provides V FB+  to the M D2    432 . The operation of the illustrated embodiment is similar to the operation described above in  FIG. 3 . 
       FIG. 5  illustrates a graph  500  of the V FB  to I FB  characteristic of the circuit illustrated in  FIG. 4 . In this regard, where V FB =(V FB+ −V FB− ) and I FB =(V FB+ −V FB− ) there exists a linear region  501  where the current may be divided between the two sides of the feedback circuit  410  with constant transconductance. The constant transconductance provides a constant gain for the feedback input, which keeps the feedback loop response stable as I FB  and V FB  vary within the linear region  501 . The gain and the linear range of the feedback circuit  410  may be adjusted by changing the V BIAS  voltage, which allows compensation for process and environmental variations. The differential current may be positive or negative allowing the feedback circuit  410  to compensate for a negative single-ended DC input current by subtracting more current from the opposite polarity input, thus balancing the subtracted current from both halves of the TIA  402  to output a balanced differential signal. 
       FIG. 6  illustrates an exemplary embodiment of a single-ended TIA  602  with a CMOS inverter and a feedback circuit  610 . In this regard, the TIA  602  portion includes transistors M P    604  and M N    606  and a resistor R F    608 . The feedback circuit  610  includes transistors M FP    612  and M FN    614 . In the illustrated embodiment, the node  603  is connected to the I IN , the R F    608 ; the gate terminals of the M P    604  and M N    606 ; and the drain terminals of the M FP    612  and M FN    614 . The node  601  is connected to the V OUT ; the drain terminals of the M P    604  and M N    606  and the R F    608 . The node  605  is connected to the gate terminals of the M FP    612  and M FN    614  and a low pass filter LPF, such as, for example the LPF  205  (of  FIG. 2 ), which may receive V OUT  prior to, or following amplification (e.g., V outAMP  output from the amplifier  204 ). The single-ended TIA  602  corresponds to the TIA  202  block (of  FIG. 2 ) while the feedback circuit  610  corresponds to the feedback circuit block  210  and may be incorporated into an alternate embodiment of the system  200  described above. 
     In operation, the feedback circuit  610  provides feedback input for DC offset cancelation and restoration. In this regard, the input V FB  adjusts the current I FB  flowing from the node  603 . The current I FB  subtracts from the current I IN  at the node  603  allowing removal of the DC input current and providing level restoration.  FIG. 7  illustrates a graph  700  of the I FB  to V FB  of the illustrated embodiment in  FIG. 6 . The linear region  701  illustrates the linear region where current I FB  may take on positive or negative values with constant transconductance. The constant transconductance provides a constant gain for the feedback input, which keeps the feedback loop response stable as I FB  and V FB  vary within the linear region  701 . 
     Referring now to  FIG. 8 , a flowchart diagram of a method  800  for forming a circuit in accordance with an exemplary embodiment is shown. As shown at block  802 , the method  800  includes forming a transimpedance amplifier having a first input node and a second input node. Next, as shown at block  804 , the method  800  includes forming a feedback circuit comprising a first transistor, a second transistor, and a third transistor. As shown at block  806 , the method  800  includes connecting a drain terminal of the first transistor to the first input node. Next, as shown at block  808 , the method  800  includes connecting a drain terminal of the second transistor to the second input node. As shown at block  810 , the method  800  includes connecting a drain terminal of the third transistor to a source terminal of the first transistor and to a source terminal of the second transistor. Next, as shown at block  812 , the method  800  includes connecting the first output node of the transimpedance amplifier to a gate terminal of the first transistor via a low pass filter. As shown at block  814 , the method  800  includes connecting the second output node of the transimpedance amplifier to a gate terminal of the second transistor via the low pass filter. 
     Referring now to  FIG. 9 , a flowchart diagram of a method  900  of using a transimpedance amplifier in accordance with an exemplary embodiment is shown. As shown at block  902 , the method  900  includes receiving an input current signal from a current output device by the transimpedance amplifier. Next, as shown at block  904 , the method  900  includes drawing a feedback current signal from the current output device by a feedback circuit. As shown at block  906 , the method  900  includes outputting a voltage output signal from the transimpedance amplifier based on the input current signal. Next, as shown at block  908 , the method  900  includes filtering the voltage output signal to create a voltage feedback signal which is input into the feedback circuit. As shown at block  910 , the method  900  the output of the current output device consists of the input current signal and the feedback current signal and the feedback circuit is configured to determine a magnitude of the feedback current signal based on the voltage feedback signal. 
     The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, element components, and/or groups thereof. 
     The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiment was chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated. 
     The flow diagrams depicted herein are just one example. There may be many variations to this diagram or the steps (or operations) described therein without departing from the spirit of the invention. For instance, the steps may be performed in a differing order or steps may be added, deleted or modified. All of these variations are considered a part of the claimed invention. 
     While the preferred embodiment to the invention had been described, it will be understood that those skilled in the art, both now and in the future, may make various improvements and enhancements which fall within the scope of the claims which follow. These claims should be construed to maintain the proper protection for the invention first described.