Patent Publication Number: US-2009236645-A1

Title: Cmos image sensor and method for manufacturing the same

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is a divisional of U.S. application Ser. No. 11/528,078, filed Sep. 26, 2006, which claims the benefit under 35 U.S.C. §119 of Korean Patent Application Number 10-2005-0090263 filed Sep. 28, 2005, which are hereby incorporated by reference in their entirety 
    
    
     FIELD OF THE INVENTION 
     The present invention relates to a CMOS image sensor and a method for manufacturing the same. 
     BACKGROUND OF THE INVENTION 
     In general, an image sensor is a device for converting an optical image into an electrical signal. Image sensors are generally classified as charge coupled devices (CCDs) or complementary metal oxide silicon (CMOS) image sensors (CISs). 
     The CCD has disadvantages, such as a complex driving method and high power consumption. Also, the CCD is manufactured through a multi-step photolithography process; it needs a very complicated manufacturing process. Therefore, the CIS is currently in the spotlight as a next-generation image sensor to resolve the disadvantages of the CCD. 
     The CIS includes a photodiode and a MOS transistor in a unit pixel to sequentially detect an electric signal in each unit pixel using a switching method for displaying an image. 
       FIG. 1  is a sectional view of a related art CIS. 
     In the related art CIS, a device isolation layer  63  is formed on a substrate  61 , and then a gate  65  is formed on the substrate  61  with a gate insulation layer  64  interposed therebetween. 
     Next, a low-concentration N ion implantation region  69  is formed at one side of the gate  65 . Spacers  70  are formed on both sidewalls of the gate  65 . Then, a high-concentration N +  ion implantation region  72  is formed at the other side of the gate  65 . 
     However, according to the related art CIS, since an N −  diffusion region (i.e., a photodiode region) is included in an interface of the device isolation layer  63 , a portion of the lattice structure collapsed from the trench etching process performed to form the device isolation layer  63  serves as an interface electro trap and a junction leakage. Therefore, the related art CIS has a problem of weak to low illumination. 
     Additionally, according to the related art CIS, the device isolation  63  between pixels may not appropriately function and cause a problem of crosstalk where light of one pixel is transmitted into other pixels. Especially, according to the related art CIS, since the depth of a trench in the device isolation layer  63  is within 0.5 μm, electrons generated from the light of a long wavelength (especially, red) may not be efficiently isolated. 
     SUMMARY OF THE INVENTION 
     Accordingly, the present invention is directed to a CMOS image sensor and a method for manufacturing the same that addresses and/or substantially obviates one or more problems, limitations, and/or disadvantages of the related art. 
     An object of the present invention is to provide a CIS without a junction leakage or an interface electron trap by preventing a lattice defect region from being converted into a photodiode region, the lattice defect region being generated when a lattice structure collapses due to an etching damage in the interface of a device isolation layer, and a method for manufacturing the same. 
     Another object of the present invention is to provide a CIS that can prevent or substantially reduce crosstalk caused by light of one pixel transmitting into other pixels, by effectively performing the separation for device isolation between pixels. 
     Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objectives and other advantages of the invention may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings. 
     To achieve these objects and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, there is provided a CIS including a device isolation layer formed on a device isolation region of a substrate of a first conductive type, the substrate including an active region and the device isolation region, the active region including a photodiode region and a transistor region; a high-concentration diffusion region of the first conductive type formed around the device isolation layer; a gate electrode formed on the active region of the substrate with a gate insulation layer interposed therebetween; a low-concentration diffusion region of a second conductive type formed on the photodiode region and spaced a predetermined distance apart from the device isolation layer; and a high-concentration diffusion region of the second conductive type formed on the transistor region. 
     In another aspect of the present invention, there is provided a method for manufacturing a CIS including forming a device isolation layer on a device isolation region of a substrate of a first conductive type and a high-concentration diffusion region of the first conductive type around the device isolation layer, the substrate including an active region and the device isolation region, the active region including a photodiode region and a transistor region; forming a gate electrode on the active region of the substrate with a gate insulation layer interposed therebetween; forming a low-concentration diffusion region of a second conductive type on the photodiode region spaced a predetermined distance apart from the device isolation layer; and forming a high-concentration diffusion region of the second conductive type on the transistor region. 
     It is to be understood that both the foregoing general description and the following detailed description of the present invention are exemplary and explanatory and are intended to provide further explanation of the invention as claimed. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS  
       The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the principle of the invention. In the drawings: 
         FIG. 1  is a sectional view of a related art CIS; 
         FIG. 2  is a sectional view of a CIS according to an embodiment of the present invention; and 
         FIGS. 3 to 10  are sectional views illustrating a method for manufacturing a CIS according to an embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION  
     Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. 
       FIG. 2  is a sectional view of a complementary metal oxide silicon image sensor (CIS) according to an embodiment of the present invention. 
     Referring to  FIG. 2 , in the CIS, a p −  epi layer  102  can be formed on a p ++  conductive semiconductor substrate  101  having an active region and a device isolation region. The active region includes a photodiode region and a transistor region. 
     The active region on the semiconductor substrate  101  can be defined by a device isolation layer  105  and a high-concentration p +  diffusion region  106  surrounding the device isolation layer  105 . In a specific embodiment, the p +  diffusion region  106  can be formed with a junction depth of 1 to 2 μm. 
     Here, the high-concentration p +  diffusion region  106  surrounds the device isolation layer  105  except for the top surface, and can be formed deeper into the substrate than the device isolation layer  105 . Therefore, an isolation effect for device separation between pixels is maximized and crosstalk can be prevented. 
     Additionally, a lattice defect region in the interface of the device isolation layer  105  prevents the high-concentration p +  diffusion region  106  from being converted into a photodiode region. Therefore, a junction leakage or an interface electron trap can be prevented such that the sensitivity of an image sensor improves. 
     A gate electrode  108  can be formed on the active region of the semiconductor substrate  101  with a gate insulation layer  107  interposed therebetween. 
     A low-concentration n −  diffusion region  112  can be formed on the photodiode region at one side of the gate electrode  108 , and is spaced a predetermined distance apart from the device isolation layer  105 . 
     At this point, the low-concentration n −  diffusion region  112  is spaced apart from the device isolation layer  105  by a thickness of the high-concentration p +  diffusion region  106 . Therefore, an isolation effect for device separation between pixels is maximized and crosstalk can be prevented. 
     A low-concentration n −  diffusion region  110  can be formed on the transistor region at the other side of the gate electrode. Insulation layer sidewalls  113  can be formed on both sides surfaces of the gate electrode  108 . A high-concentration n +  diffusion region  115  can also be formed on the transistor region. In a further embodiment, a P 0  diffusion region  117  can be formed near the surface of the photodiode region having the low-concentration n −  diffusion region  112 . 
       FIGS. 3 to 10  are sectional views illustrating a method for manufacturing a CIS according to an embodiment of the present invention. 
     Hereinafter, the formation order of each component should not be construed as being limited to the embodiments set forth herein. The formation order may be interchangeable between components. 
     Referring to  FIG. 3 , a low-concentration first conductive (P − ) epi layer  102  can be formed on a semiconductor substrate  101  using an epitaxial process. In a specific embodiment, the semiconductor substrate  101  can be a high-concentration first conductive (P ++ ) single crystal silicon. 
     Here, the epi layer  102  can form a depletion region in a photodiode largely and deeply such that the capability for collecting photo charge in a low-voltage photodiode increases and photo sensitivity improves. 
     In another embodiment, the semiconductor substrate  101  may be an n-type substrate having a p-type epi layer thereon. 
     Next, as illustrated in  FIG. 4 , a pad oxide layer  103  can be formed on the semiconductor substrate  101  having the epi layer  102 . A first photosensitive film  104  can be formed on the pad oxide layer  103 . 
     Next, the first photosensitive film  104  can be selectively patterned to define a device isolation region using an exposure and development process. 
     Here, a region where the first photosensitive film  104  is uncovered becomes a device isolation region. A region where the first photosensitive film  104  is covered becomes an active region. 
     Using the patterned first photosensitive film  104  as a mask, oxygen (O 2 ) ions can be implanted into the device isolation region of the semiconductor substrate  101 . Then, p +  impurity ions can be implanted at high concentration into the device isolation region having the oxygen ions. In one embodiment, the p +  impurity ions can be B +  ions. 
     Next, an annealing process can be performed on the semiconductor substrate  101  to diffuse the oxygen ions and the high-concentration p +  impurity ions such that a device isolation layer  105  is formed on the device isolation region of the semiconductor substrate  101  and a high-concentration p +  diffusion region  106  is formed around the device isolation layer  105  simultaneously. 
     Here, the high-concentration p +  impurity ions used in the high-concentration p +  diffusion region  106  have a better diffusivity than the oxygen ions implanted to form the device isolation layer  105 . Thus, the high-concentration p +  impurity ions are more widely diffused and surround the device isolation layer  105 . 
     In a specific embodiment, the high-concentration p +  diffusion region  106  is formed with a junction depth of 1 to 2 μm deeper than the device isolation layer  105 . 
     Accordingly, the high-concentration p +  diffusion region  106  can surround the device isolation layer  105  except for the top surface, and can be formed deeper into the substrate than the device isolation layer  105 . Therefore, an isolation effect for device separation between pixels is maximized and crosstalk can be prevented. 
     Additionally, a lattice defect region in the interface of the device isolation layer  105  prevents the high-concentration p +  diffusion region  106  from being converted into a photodiode region. Therefore, a junction leakage or an interface electron trap can be prevented such that sensitivity of an image sensor improves. 
     Next, as illustrated in  FIG. 5 , the first photosensitive film  104  and the pad oxide layer  103  are removed. A gate insulation layer  107  and a conductive layer (e.g., a high-concentration polycrystal silicon layer) can be sequentially deposited on an entire surface of the epi layer  102  having the device isolation layer  105 . 
     In one embodiment, the gate insulation layer  107  can be formed using a thermal oxide process or a chemical vapor deposition (CVD) method. 
     The conductive layer and the gate insulation layer  107  can then be selectively removed to form a gate electrode  108 . 
     As illustrated in  FIG. 6 , a second photosensitive film  109  can be formed on an entire surface of the semiconductor substrate  101  having the gate electrode  108 . The second photosensitive film  109  can cover each photodiode region and can be patterned to expose source/drain regions for each transistor using an exposure and development process. 
     Using the patterned second photosensitive film  109  as a mask, n −  impurity ions can be implanted at low concentration into the exposed source/drain regions to form an n −  diffusion region  110 . 
     In an embodiment, the n −  diffusion region  110  can be considered as optional and does not need to be formed. 
     As illustrated in  FIG. 7 , after removing the second photosensitive film  109 , a third photosensitive film  111  can be formed on an entire surface of the semiconductor substrate  101 , and can be patterned to expose each photodiode region using an exposure and development process. 
     Using the patterned third photosensitive Film  111  as a mask, n −  impurity ions can be implanted at low concentration into the epi layer  102  to form an n −  diffusion region  112 . 
     In one embodiment, the impurity ion implantation for forming the n −  diffusion region  112  can be performed using higher energy than the n −  diffusion region  110  in the source/drain regions. Thus, the n −  diffusion region  112  can be formed deeper into the substrate than the n −  diffusion region  110 . 
     Then, after removing the patterned third photosensitive film  111  and depositing an insulation layer on an entire surface of the semiconductor substrate  101 , an etch back process can be performed to form sidewall insulation layers  113  on the both sides of the gate electrode  108 . 
     Next, as illustrated in  FIG. 8 , a fourth photosensitive film  114  can be formed on an entire surface of the semiconductor substrate  101  having the sidewall insulation layers  113 . The fourth photosensitive film  114  can cover each photodiode region and can be patterned to expose source/drain regions for each transistor using an exposure and development process. 
     Next, using the fourth photosensitive film  114  as a mask, n +  impurity ions can be implanted at high concentration into the exposed source/drain regions to form the high-concentration n +  diffusion region  115 . 
     Next, as illustrated in  FIG. 9 , after removing the fourth photosensitive film  114  a fifth photosensitive film  116  can be formed on an entire surface of the semiconductor substrate  101 . The fifth photosensitive film  116  can be patterned to expose each photodiode region using an exposure and development process. 
     Using the patterned fifth photosensitive film  116  as a mask, p 0  impurity ions can be implanted into the epi layer  102  having the low-concentration n −  diffusion region  112  to form a p 0  diffusion region  117  in the epi layer  102 . 
     As illustrated in  FIG. 10 , after removing the fifth photosensitive film  116 , a thermal treatment process can be performed on the semiconductor substrate  101  to diffuse each impurity diffusion region. 
     Next, although processes are not shown in the drawings, after forming a plurality of metal lines in an interlayer insulation layer on the result, a color filter layer and a microlens can be formed to complete an image sensor. 
     According to the present invention, the CIS and a method for manufacturing the same have following effects. 
     After implanting oxygen ions, a device isolation layer is formed and then a p +  diffusion region is formed around the device isolation layer. Therefore, an isolation effect for device separation between pixels is maximized and crosstalk can be prevented. 
     Additionally, since the p +  diffusion region is formed around the device isolation layer, a lattice defect region in the interface of the device isolation layer prevents the high-concentration p +  diffusion region  106  from being converted to a photodiode region. Therefore, a junction leakage or an interface electron trap can be prevented such that the sensitivity of an image sensor improves. 
     It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention. Thus, it is intended that the present invention covers the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.