Patent Publication Number: US-6657623-B1

Title: Method and apparatus for transmitting a video signal

Description:
CLAIM OF PRIORITY 
     This application makes reference to, incorporates the same herein, and claims all benefits accruing under 35 U.S.C. §119 from an application entitled METHOD FOR SENDING IMAGE SIGNAL earlier filed in the Korean Industrial Property Office on Jul. 13 th 1999, and there duly assigned Serial No. 99-28202. 
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a method and apparatus for transmitting a video signal, and more particularly, to a method and apparatus for transmitting a video signal by processing a video signal from a computer and inputting the processed signal to a cathode ray tube (CRT) monitor. 
     2. Description of the Related Art 
     In a typical computer, a graphic controlling unit controls a video random access memory (RAM) according to a control signal, an address signal and a data signal from a central processing unit (CPU) to generate a parallel digital video signal. The parallel digital video signal is converted to an analog video signal and then is transmitted to a cathode ray tube (CRT) monitor. 
     Referring to FIG. 1, a video card of a conventional computer  100  includes a graphic controller  11 , a video random access memory (RAM)  12 , a clock pulse generator  13  and a digital-to-analog converter (DAC)  14 . The graphic controller  11  reads or writes data from or to an input address (ADR) area of the video random access memory (RAM)  12  by means of a read/write signal (R/W) according to a control signal (CTR) output from the central processing unit (CPU)  10  of the computer  100 . The graphic controller  11  and the digital-to-analog converter (DAC)  14  operate according to a clock pulse signal (CLK) output from the clock pulse generator  13 . 
     The graphic controller  11  processes data output from the video random access memory (RAM)  12  to generate a parallel digital red video signal R P , a parallel digital green video signal G P , a parallel digital blue video signal B P , a horizontal sync signal H SYNC , a vertical sync signal V SYNC  and a data enable signal DE. 
     The digital-to-analog converter (DAC)  14  processes the parallel digital signals output from the graphic controller  11  to generate an analog red video signal R A , an analog green video signal G A , an analog blue video signal B A , and an analog synthesized sync signal SYNC A . The analog signals output from the digital-to-analog converter (DAC)  14  are transmitted to a monitor  110  via a metal cable  15 . 
     An amplifier  16  of the monitor  110  amplifies the received analog video signals R A , G A , and B A  and inputs the amplified signals R A , G A , and B A  to a cathode ray tube (CRT) driver  18  of monitor  110 . Also, a synchronization controller  17  of monitor  110  controls the received analog synthesized sync signal SYNC A  to input this controlled signal to the cathode ray tube (CRT) driver  18 . 
     According to the conventional transmission method, the parallel digital video signals are transmitted as converted analog signals. Thus, noise externally generated affects the transmission of the analog signals so that the video signals are easily distorted during the transmission period. 
     SUMMARY OF THE INVENTION 
     To solve the above problem, it is an objective of the present invention to provide a method and apparatus for transmitting a video signal from a computer to a cathode ray tube monitor by processing the video signal so that the rate of distortion of the transmitted video signal can be reduced. 
     Accordingly, to achieve the above objective and other objectives of the present invention, there is provided a method of and apparatus for transmitting parallel digital video signals output from a graphic controller of a computer to a driver of a cathode ray tube monitor, transmission being achieved by converting the parallel digital video signals to serial digital video signals, transmitting the converted serial digital video signals to the cathode ray tube monitor via a cable, converting the transmitted serial digital video signals to serial analog video signals, and inputting the converted serial analog video signals to the driver of the cathode ray tube monitor. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     A more complete appreciation of the invention, and many of the attendant advantages thereof, will be readily apparent as the same becomes better understood by reference to the following detailed description when considered in conjunction with the accompanying drawings in which like reference symbols indicated the same or similar components, wherein: 
     FIG. 1 is a block diagram showing a conventional method of transmitting video signals; 
     FIG. 2 is a block diagram showing a method of and apparatus for transmitting video signals according to an embodiment of the present invention; and 
     FIG. 3 is a block diagram showing a method of and apparatus for transmitting video signals according to another embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Referring to FIG. 2, a video card of a computer  200  according to an embodiment of the present invention includes a graphic controller  21 , a video random access memory (RAM)  22 , a clock pulse generator  23  and a parallel-to-serial converter (PSC)  24 . The graphic controller  21  reads or writes data (DATA) from or to an input address (ADR) area of the video random access memory (RAM)  22  by means of a read/write signal (R/W) and according to a control signal (CTR) output from the central processing unit (CPU)  20  of the computer  200 . 
     The graphic controller  21  of computer  200  processes data (DATA) output from the video random access memory (RAM)  22  to generate an n-bit (for example, an 8-bit) parallel digital red video signal R P , an n-bit (for example, an 8-bit) parallel digital green video signal G P , an n-bit (for example, an 8-bit) parallel digital blue video signal B P , a horizontal sync signal H SYNC , a vertical sync signal V SYNC  and a data enable signal DE, as parallel digital video signals. The graphic controller  21  operates according to a first clock pulse signal CLK 1 output from the clock pulse generator  23 . The parallel-to-serial converter (PSC)  24  operates according to a second clock pulse signal CLK 2  output from the clock pulse generator  23 . Preferably, the frequency of the second clock pulse signal CLK 2  is n-times (for example, 8 times) that of the first clock pulse signal CLK 1 . 
     The parallel-to-serial converter (PSC)  24  processes the input parallel digital signals R P , G P , B P , H SYNC  and V SYNC  from graphic controller  21  to generate a serial digital red video signal R S , a serial digital green video signal G S , a serial digital blue video signal B S , a digital synthesized sync signal SYNC S  and a second clock pulse signal CLK 2  as serial digital video signals, for example. The digital synthesized sync signal SYNC S  is generated according to the horizontal sync signal H SYNC , the vertical sync signal V SYNC  and the data enable signal DE from the graphic controller  21 . The serial digital signals output from the parallel-to-serial converter (PSC)  24  are transmitted to a cathode ray tube (CRT) monitor  210  via a metal cable  25 . 
     Continuing with reference to FIG. 2, a level restoration unit  261  in the cathode ray tube (CRT) monitor  210  operates according to the received second clock pulse signal CLK 2  and restores the direct current of the serial digital red video signal R S , the serial digital green video signal G S , and the serial digital blue video signal B S  to the original state before the transmission. A timing controller  27  of monitor  210 , operating according to the received second clock pulse signal CLK 2 , converts the digital synthesized sync signal SYNC S  from the parallel-to-serial converter (PSC)  24  to an analog synthesized sync signal SYNC A , and controls timing of the second clock pulse signal CLK 2  to input the controlled signal CLK 2 ′ to a digital-to-analog converter (DAC)  262  of monitor  210 . 
     A cathode ray tube (CRT) driver  28  of monitor  210  drives the cathode ray tube (CRT)  29  of monitor  210  according to serial analog video signals R A , G A , and B A  output from the digital-to-analog converter (DAC)  262  and an analog synthesized sync signal SYNC A  output from the timing controller  27 , and displays a corresponding image on the cathode ray tube (CRT)  29 . The digital-to-analog converter  262  desirably generates serial analog red video signals (Re) according to the value of the serial digital red video signal of an n-bit packet which is input to the digital-to-analog converter  262  while n pulses of the second clock pulse signal are input to the digital-to-analog converter  262 . The digital-to-analog converter  262  also desirably simultaneously generates serial analog green video signals (G A ) according to the value of the serial digital green video signal of an n-bit packet which is input to the digital-to-analog converter  262  while n pulses of the second clock pulse signal are input to the digital-to-analog converter  262 . Further, the digital-to-analog converter  262  also desirably simultaneously generates serial analog blue video signals (B A ) according to the value of the serial digital blue video signal of an n-bit packet which is input to the digital-to-analog converter  262  while n pulses of the second clock pulse signal are input to the digital-to-analog converter  262 . The digital-to-analog converter  262  repeats the generation of the serial analog red, green and blue video signals (R A ,G A , B A ), as necessary, for displaying a corresponding image on the cathode ray tube (CRT)  29 . 
     Referring to FIG. 3, a video card of a computer  300  according to another embodiment of the present invention includes a graphic controller  31 , a video random access memory (RAM)  32 , a clock pulse generator  33 , a parallel-to-serial converter (PSC)  34 , and an optical transmission unit  391 . In comparison to the structure of FIG. 2, in FIG. 3, the optical transmission unit  391  and an optical receiver  392  are added, and the metal cable  25  is replaced with an optical cable  35 . That is, graphic controller  31  of computer  300  has the same function as the graphic controller  21  of computer  200  of FIG. 2; video random access memory (RAM)  32  of computer  300  has the same function as the video random access memory (RAM)  22  of computer  200  of FIG. 2; clock pulse generator  33  of computer  300  has the same function as the clock pulse generator  23  of computer  200  of FIG. 2; parallel-to-serial converter (PSC)  34  of computer  300  has the same function as the parallel-to-serial converter (PSC)  24  of computer  200  of FIG. 2; level restoration unit  361  of monitor  310  has the same function as the level restoration unit  261  of monitor  210  of FIG. 2; digital-to-analog converter (DAC)  362  of monitor  310  has the same function as the digital-to-analog converter (DAC)  262  of monitor  210  of FIG. 2; timing controller  37  of monitor  310  has the same function as the timing controller  27  of monitor  210  of FIG. 2; and cathode ray tube (CRT) driver  38  of monitor  310  has the same function as the cathode ray tube (CRT) driver  28  of monitor of FIG.  2 . 
     In this regard, referring to FIG. 3, the graphic controller  31  reads or writes data (DATA) from or to an input address (ADR) area of the video random access memory (RAM)  32  by means of a read/write signal (R/W) according to a control signal (CTR) output from the central processing unit (CPU)  30  of the computer  300 . The graphic controller  31  of computer  300  processes data (DATA) output from the video random access memory (RAM)  32  to generate an n-bit (for example, an 8-bit) parallel digital red video signal R P , an n-bit (for example, an 8-bit) parallel digital green video signal G P , an n-bit (for example, an 8-bit) parallel digital blue video signal B P , a horizontal sync signal H SYNC , a vertical sync signal V SYNC , and a data enable signal DE as parallel digital video signals. The graphic controller  31  operates according to a first clock pulse signal CLK 1  output from the clock pulse generator  33 . The parallel-to-serial converter (PSC)  34  operates according to a second clock pulse signal CLK 2  output from the clock pulse generator  33 . The frequency of the second clock pulse signal CLK 2  is n-times (for example, 8 times) that of the first clock pulse signal CLK 1 . 
     The parallel-to-serial converter (PSC)  34  processes the input parallel digital signals R P , G P , and B P , from graphic controller  31  to generate a serial digital red video signal R S , a serial digital green video signal G S , a serial digital blue video signal B S , a digital synthesized sync signal SYNC S  and a second clock pulse signal CLK 2  as serial digital video signals. The digital synthesized sync signal SYNC S  is generated according to the horizontal sync signal H SYNC , the vertical sync signal V SYNC  and the data enable signal DE from the graphic controller  31 . The serial digital signals output from the parallel-to-serial converter (PSC)  34  are transmitted to an optical transmission unit  391 . 
     Continuing with reference to FIG. 3, the optical transmission unit  391  of computer  300  converts the serial digital signals R S , G S , B S , SYNC S  and CLK 2  output from parallel-to-serial converter (PSC)  34  to respective converted optical signals. These converted optical signals are transmitted to an optical receiver  392  of monitor  310  via the optical cable  35 . The optical receiver  392  of monitor  310  converts the received optical signals to electrical serial digital signals R S , G S , B S , SYNC S  and CLK 2  providing the signals R S , G S , and B S  to the level restoration unit  361  and providing the signals SYNC S  and CLK 2  to timing controller  37  of monitor  310 . 
     Continuing with reference to FIG. 3, the level restoration unit  361  in the cathode ray tube (CRT) monitor  310  operates according to the received second clock pulse signal CLK 2  and restores the direct current of the serial digital red video signal R S , the serial digital green video signal G S , and the serial digital blue video signal B S , to the original state before the transmission. The timing controller  37  of monitor  310 , operating according to the received second clock pulse signal CLK 2 , converts the digital synthesized sync signal SYNC S  from the optical receiver  392  to the analog synthesized sync signal SYNC A  and controls timing of the second clock pulse signal CLK 2  to input the controlled signal CLK 2  to a digital-to-analog converter (DAC)  362  of monitor  310 . 
     A cathode ray tube (CRT) driver  38  of monitor  310  drives the cathode ray tube (CRT)  39  of monitor  310  according to serial analog video signals R A , G A , and B A  output from the digital-to-analog converter (DAC)  362  and an analog synthesized sync signal SYNC A  output from the timing controller  37 , and displays a corresponding image on the cathode ray tube (CRT)  39 . The digital-to-analog converter  362  desirably generates serial analog red video signals (R A ) according to the value of the serial digital red video signal of an n-bit packet which is input to the digital-to-analog converter  362  while n pulses of the second clock pulse signal are input to the digital-to-analog converter  362 . The digital-to-analog converter  362  also desirably simultaneously generates serial analog green video signals (G A ) according to the value of the serial digital green video signal of an n-bit packet which is input to the digital-to-analog converter  362  while n pulses of the second clock pulse signal are input to the digital-to-analog converter  362 . Further, the digital-to-analog converter  362  also desirably simultaneously generates serial analog blue video signals (B A ) according to the value of the serial digital blue video signal of an n-bit packet which is input to the digital-to-analog converter  362  while n pulses of the second clock pulse signal are input to the digital-to-analog converter  362 . The digital-to-analog converter  362  repeats the generation of the serial analog red, green and blue video signals (R A , G A , B A ), as necessary, for displaying a corresponding image on the cathode ray tube (CRT)  39 . 
     The above optical transmission method and apparatus of FIG. 3 is desirable and effective in a case in which transmitting the serial digital data causes the rate of distortion of a signal to increase significantly, such as can occur when an analog transmission method is performed. Also, an optical transmission method, such as that illustrated in FIG. 3, typically becomes more efficient when the distance between the computer and the cathode ray tube (CRT) monitor (such as between computer  300  and monitor  310 ) increases. 
     As described above, in the method of and apparatus for transmitting a video signal according to the present invention, as the parallel digital video signals are transmitted by being converted to serial digital video signals, the signals transmitted are not easily affected by noise generated externally during the transmission period. Thus, the rate of distortion of the transmitted video signals can be advantageously reduced. Also, in the present invention, at the stage of inputting the transmitted video signals to the driver of the monitor, analog video signals can be directly generated by the digital-to-analog converter without restoring a serial digital video signal from a parallel digital video signal. Thus, the circuit for input to the driver of the monitor in the present invention can be advantageously simplified. 
     While there have been illustrated and described what are considered to be preferred embodiments of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made, and equivalents may be substituted for elements thereof without departing from the true scope of the present invention. In addition, many modifications may be made to adapt a particular situation to the teaching of the present invention without departing from the scope thereof. Therefore, it is intended that the present invention not be limited to the particular embodiments disclosed as the best mode contemplated for carrying out the present invention, but that the present invention include all embodiments falling within the scope of the appended claims.