Patent Publication Number: US-6665408-B1

Title: Dynamic bass control circuit with variable cut-off frequency

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The subject invention relates to the processing of audio signals, and more particularly, to boosting the bas response of audio signals. 
     2. Description of the Related Art 
     It is common for audio systems to include controls for boosting and/or attenuating the bass response of the audio signal to suit the preferences of a user of the audio system. However, it has been found that while a particular adjustment may be satisfactory for low signal levels, as the signal level increases, the set amount of boost may cause overloading of the amplifier and/or damage to the loudspeakers and/or loudspeaker enclosures attached to the system. 
     European Patent Application EP 0 122 663 to Freadman discloses a method and system for improving speaker performance in which the magnitude level is detected for both low and high frequency portions of an input audio signal. Based on these detected magnitude levels, low and high frequency active voltage control shaper circuits generate control signals for a constant velocity equalizer to dynamically control the high and low frequency response such that at low input signal levels, the high and low frequency portions of the input signal are boosted, while at higher input signal levels, the high and low frequency portions are boosted to a lesser extent. 
     European Patent Application EP 0 554 962 to Laupman discloses tone control circuitry having a frequency characteristic dependent on the input signal level, in which the low frequency boost of the Freadman circuit is enhanced by coupling a fixed filter circuit to the Freadman circuit. 
     SUMMARY OF THE INVENTION 
     It is an object of the invention to provide a dynamic bass control circuit which is considerably simpler than the known systems. 
     This object is achieved in a circuit for providing a variable amount of bass control on an input signal dependent on a signal level of said input signal, said circuit comprising an input for receiving the input signal; high-pass filtering means coupled to said input, said high-pass filtering means having an output forming an output of said circuit; means for coupling the output of said high-pass filtering means to ground, said coupling means having a variable impedance in response to a control signal, wherein said coupling means varies a Q value of said high-pass filtering means; and means coupled to said input for detecting a signal level of said input signal, said detecting means generating said control signal for said coupling means in dependence on said detected signal level. 
     The fundamental operating principle of the subject invention is to vary the Q value of a second order high-pass filter so as to cause an increase in Q under low level input signal conditions, while causing a lowering of the Q of the filter with high level input signals. This is achieved by placing a control element in shunt across the output of the high-pass filter such that at low signal levels, the control element is open effectively removing the shunt allowing the filter to operate in its maximum Q condition. At increased signal levels, the control element is closed and the filter is loaded by the shunting resistance causing a lowering of the Q value and also increasing the cut-off frequency of the high-pass filter. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     With the above and additional objects and advantages in mind as will hereinafter appear, the invention will be described with reference to the accompanying drawings, in which: 
     FIG. 1 is a schematic circuit diagram of a first embodiment of a bass control circuit of the subject invention; 
     FIGS. 2A and 2B show response curves for the circuit of FIG. 1 using various values for the components; 
     FIG. 3 is a schematic circuit diagram of a second embodiment of a bass control circuit of the subject invention; and 
     FIG. 4 shows response curves for the circuit of FIG.  3 . 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 1 shows a first embodiment of the dynamic bass control circuit of the subject invention which includes an input V IN  for receiving an audio signal. The input V IN  is connected through a capacitor C 1  to a non-inverting input of an amplifier A 1 . The non-inverting input is further connected to a voltage source +V CC  through a series combination of resistors R 1  and R 2 . The output of amplifier A 1  is connected to its inverting input and, via a capacitor C 2  and a resistor R 3 , to the junction between resistors R 1  and R 2 , which is connected to ground via the parallel arrangement of a resistor R 4  and a capacitor C 3 . The output of amplifier A 1  is connected through the series arrangement of capacitors C 4  and C 5  to the non-inverting input of amplifier A 2  which is also connected to the junction between resistors R 1  and R 2  by a resistor R 5 . The junction between capacitors C 4  and C 5  is connected to the output of amplifier A 2  via a resistor R 6 . The combination of capacitors C 4  and C 5 , and resistors R 5  and R 6  form high-pass filtering means, while the amplifier A 2  forms an output amplifier of the high-pass filtering means. The output of amplifier A 2  is connected to its inverting input and to ground via the series arrangement of a capacitor C 6  and a resistor R 7 . The junction between capacitor C 6  and resistor R 7  forms the output V OUT  of the dynamic bass control circuit. 
     The non-inverting input of amplifier A 2  is further connected to the series arrangement of a capacitor C 7 , a resistor R 8 , which is, in turn, connected to a drain terminal of a JFET, and, via a series arrangement of a resistor R 9  and a capacitor C 8 , to the gate of the JFET, the source terminal of the JFET being connected to ground. Arranged as such, the JFET forms coupling means for coupling the output of the high-pass filtering means to ground. The gate of the JFET is further connected to the junction between capacitor C 2  and resistor R 3  by the series arrangement of resistor R 10 , diode D 1  and resistor R 11 , the junction between diode D 1  and resistor R 11  being connected to ground via a capacitor C 9 , and the junction between resistor R 10  and diode D 1  being connected to the junction between resistors R 2  and R 3  by a parallel arrangement of a capacitor C 10  and a resistor R 12 . The combination of resistors R 1 -R 4  and R 10 -R 12 , capacitors C 9  and C 10 , and diode D 1  form detecting means for detecting the signal level of the input signal V IN . 
     In operation, when the input signal level is sufficiently low, the JFET, which is placed in shunt across the output of the high-pass filtering means, is turned off thereby removing the shunting effect allowing the high-pass filtering means to operate in its maximum Q condition. As the input signal level increases, the JFET is turned on thereby loading the high-pass filtering means with the shunting resistance causing a lowering of the Q value, and also increasing the cut-off frequency of the high-pass filtering means. 
     Table 1 shows a first and second set of values A and B for the components in FIG.  1 : 
     
       
         
           
               
               
               
               
               
               
             
               
                   
                 TABLE 1 
               
               
                   
                   
               
               
                   
                 COMPONENT 
                 A 
                   
                 B 
               
               
                   
                   
               
             
            
               
                   
               
            
           
           
               
               
               
               
               
               
            
               
                   
                 R1 
                 100 
                 KΩ 
                 100 
                 KΩ 
               
               
                   
                 R2, R4 
                 1 
                 KΩ 
                 1 
                 KΩ 
               
               
                   
                 R3 
                 10 
                 KΩ 
                 10 
                 KΩ 
               
               
                   
                 R5 
                 560 
                 KΩ 
                 120 
                 KΩ 
               
               
                   
                 R6 
                 4.7 
                 KΩ 
                 .20 
                 KΩ 
               
               
                   
                 R7 
                 100 
                 KΩ 
                 10 
                 KΩ 
               
               
                   
                 R8 
                 120 
                 KΩ 
                 33 
                 KΩ 
               
               
                   
                 R9, R10, R12 
                 1 
                 MΩ 
                 1 
                 MΩ 
               
               
                   
                 R11 
                 4.7 
                 KΩ 
                 4.7 
                 KΩ 
               
               
                   
                 C1 
                 5 
                 μf 
                 5 
                 μf 
               
               
                   
                 C2 
                 47 
                 μf 
                 47 
                 μf 
               
               
                   
                 C3 
                 100 
                 μf 
                 100 
                 μf 
               
               
                   
                 C4 
                 0.068 
                 μf 
                 0.1 
                 μf 
               
               
                   
                 C5 
                 0.15 
                 μf 
                 0.1 
                 μf 
               
               
                   
                 C6 
                 5 
                 μf 
                 0.47 
                 μf 
               
               
                   
                 C7 
                 0.1 
                 μf 
                 1 
                 μf 
               
               
                   
                 C8 
                 0.01 
                 μf 
                 0.01 
                 μf 
               
               
                   
                 C9 
                 0.22 
                 μf 
                 0.22 
                 μf 
               
               
                   
                 C10 
                 1 
                 μf 
                 1 
                 μf 
               
               
                   
                   
               
            
           
         
       
     
     FIG. 2A shows response curves for the circuit of FIG. 1 using the first set of values A in Table 1, while FIG. 2B shows the response curves using the second set of values B in Table 1. 
     FIG. 3 shows a second embodiment of the invention. This second embodiment is substantially similar to the first embodiment of FIG. 1 with the following exceptions. Resistor R 3  has been eliminated and the capacitor C 2  is connected only to resistor R 11 . Capacitor C 9  has been eliminated and the conducting direction of diode D 1  has been reversed. The parallel combination of capacitor C 10  and resistor R 12  is now connected directly to ground. Capacitor C 7  is now connected to the inverting input of amplifier A 2 , the output now being connected to the inverting input through a resistor R 13 . 
     In this second embodiment, the JFET shunts the inverting input of the amplifier A 2 . As such, when the input signal level is sufficiently low, the JFET is turned on causing an increase in the gain of amplifier A 2 . This increase in gain increases the Q value of the high-pass filter. When the input signal level increases, the JFET is turned off, the Q value of the filter is lowered and the gain of amplifier A 2  is lowered. 
     Table 2 shows a set of values for the components in the second embodiment of FIG.  3 : 
     
       
         
           
               
               
               
               
             
               
                   
                 TABLE 2 
               
               
                   
                   
               
               
                   
                 COMPONENT 
                 VALUE 
               
               
                   
                   
               
             
            
               
                   
               
            
           
           
               
               
               
               
            
               
                   
                 R1, R7 
                 100 
                 KΩ 
               
               
                   
                 R2, R4 
                 1 
                 KΩ 
               
               
                   
                 R5 
                 36 
                 KΩ 
               
               
                   
                 R6 
                 22 
                 KΩ 
               
               
                   
                 R8, R13 
                 150 
                 KΩ 
               
               
                   
                 R9, R10, R12 
                 1 
                 MΩ 
               
               
                   
                 R11 
                 4.7 
                 KΩ 
               
               
                   
                 C1, C6 
                 5 
                 μf 
               
               
                   
                 C2 
                 47 
                 μf 
               
               
                   
                 C3 
                 100 
                 μf 
               
               
                   
                 C4, C5 
                 0.15 
                 μf 
               
               
                   
                 C7 
                 0.47 
                 μf 
               
               
                   
                 C8 
                 0.01 
                 μf 
               
               
                   
                 C10 
                 1 
                 μf 
               
               
                   
                   
               
            
           
         
       
     
     FIG. 4 is a graph showing the response curve for the second embodiment of FIG. 3 using the values in Table 2. 
     Numerous alterations and modifications of the structure herein disclosed will present themselves to those skilled in the art. However, it is to be understood that the above described embodiment is for purposes of illustration only and not to be construed as a limitation of the invention. All such modifications which do not depart from the spirit of the invention are intended to be included within the scope of the appended claims.