Patent Publication Number: US-11037843-B2

Title: Apparatuses and methods for TSV resistance and short measurement in a stacked device

Description:
CROSS-REFERENCE TO RELATED APPLICATION(S) 
     This application is a divisional of U.S. patent application Ser. No. 15/715,504, filed Sep. 26, 2017 and issued as U.S. Pat. No. 10,468,313 on Nov. 5, 2019. These application and patent are incorporated by reference herein in their entirety and for all purposes. 
    
    
     BACKGROUND 
     Historically, during manufacture of stacked circuit configuration, testing for conduction failures through through-substrate vias (TSVs) between layers of the circuit was limited to physical inspection. Being limited to physical inspection made it impossible to make an assessment to improve screen yield related to the TSV. For example, being limited to physical inspection prevents adoption of an electric non-destructive analysis for a screen test and defect assessment/analysis, which includes identifying defective areas and examining origins of failure modes. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a prior art schematic illustration of an apparatus including a stacked semiconductor device in accordance with embodiments of the disclosure. 
         FIG. 2  is a prior art schematic illustration of an apparatus including a stacked semiconductor device in accordance with embodiments of the disclosure. 
         FIG. 3  is a schematic illustration of an apparatus including a stacked semiconductor device in accordance with embodiments of the disclosure. 
         FIG. 4  is a schematic illustration of an apparatus including a stacked semiconductor device in accordance with embodiments of the disclosure. 
         FIG. 5  is a schematic illustration of an apparatus including a stacked semiconductor device in accordance with embodiments of the disclosure. 
         FIG. 6  is a cross-sectional view showing TSV structures according to embodiments of the disclosure. 
         FIG. 7  is a cross-sectional view showing TSV structures according to embodiments of the disclosure. 
         FIG. 8  is a block diagram of an intermediate buffer according to an embodiment of the disclosure. 
         FIG. 9  is a schematic illustration of an apparatus including a stacked semiconductor device in accordance with embodiments of the disclosure. 
         FIG. 10A  is a schematic diagram of a stacked semiconductor device and logic circuits for providing control signals in accordance with embodiments of the disclosure. 
         FIG. 10B  is a schematic diagram of alternative logic circuits for providing control signals in accordance with embodiments of the disclosure. 
         FIG. 11  is an exemplary table of values of the control signals based on the logic circuits of  FIG. 10  in accordance with embodiments of the disclosure 
     
    
    
     DETAILED DESCRIPTION 
     Certain details are set forth below to provide a sufficient understanding of embodiments of the present disclosure. However, it will be clear to one skilled in the art that embodiments of the present disclosure may be practiced without various of these particular details. In some instances, well-known wireless communication components, circuits, control signals, timing protocols, computing system components, telecommunication components, and software operations have not been shown in detail in order to avoid unnecessarily obscuring the described embodiments of the present disclosure. 
       FIG. 1  is a schematic illustration of an apparatus  100  including a stacked semiconductor device in accordance with embodiments of the disclosure. The apparatus  100  may include an interface chip  110  and a stacked semiconductor device  140 . The interface chip  110  may include a control circuit  111 , a force signal driver  112 , and an output circuit  120 . The control circuit  111  provides control signals to circuitry of the stacked semiconductor device  140 . The output circuit  120  may include amplifier circuits AMP 0 , AMP 1 , AMP 2 , and a CMP circuit to compare voltages of a sense signal and a sense feedback signal and provide an analog output signal OUTA and a digital output signal OUTD that are indications of resistance of the  146  or the  147 . The OUTA signal may provide an indication of actual resistance and the OUTD signal may provide an indication as to whether the resistance of the  146  or the  147  exceeds a threshold (e.g., 100 ohms or some other value). 
     The stacked semiconductor device  140  may include a core chip  142 . While the stacked semiconductor device  140  is depicted with only a single core chip, other core chips may be stacked on the single core chip without departing from the scope of the disclosure. The core chip  142  and the interface chip  110  may include first control circuitry  144 A and  144 B, respectively, to control resistance testing of the  146  and may include second control circuitry  144 C and  144 D, respectively, to control resistance testing of the  147 . Additional sets of control circuitry and TSVs in parallel with the sets control circuitry  144 A/ 144 B/ 146  and control circuitry  144 C/ 144 D/ 147  sets may be included on the core chip  142  and the interface chip  110  without departing from the scope of the disclosure. The control circuitry  144 A may provide a sense signal having a voltage from a first end of the  146  to the output circuit  120  and the control circuitry  144 B may provide the sense feedback signal having a voltage from a second end of the  146  to the output circuit  120 . The control signals for the control circuitry  144 A- 144 D may be provided by the control circuit  111  of the interface chip  110 . The core chip  142  may further include a TSV  132  and TSV  134  to provide a force signal to the control circuitry  144 A and to provide the sense signal from the control circuitry  144 A. 
     In an operation testing resistance of the  146 , the force signal driver  112  may provide a force signal having a constant current through the TSV  132  to the  144 A and to circuitry of the stacked semiconductor device  140 . The constant current is controlled by the force AMP of the force signal driver  112  based on a comparison between the VREF signal and the force feedback signal. The control circuit  111  may provide control signals to the control circuits  144 A and  144 B to enable the respective p-type metal oxide semiconductor (MOS) transistors. With the control circuitry  144 A and  144 B enabled, force signal is provided to the  146  via one enabled p-type MOS transistor of the control circuitry  144 A. Current flows through the  146  to the second end. The force feedback signal is provided at one output of the control circuitry  144 B one enabled p-type MOS transistor of the control circuitry  144 B to the force AMP of the force signal driver  112 . The sense signal is provided via one enabled p-type MOS transistor of the control circuitry  144 A through the TSV  134  to the output circuit  120 . A sense feedback signal is provided through one enabled p-type MOS transistor of the control circuitry  144 B to the output circuit  120 . The AMP 0 , AMP 1 , and AMP 2  circuits may compare the sense and sense feedback signals to determine a voltage difference. The voltage difference between the sense and sense feedback signals provided in the OUTA signal from the output of the AMP 2  circuit may indicate a resistance of the  146 . The OUTA signal may be compared with the force feedback signal to indicate whether the resistance of the  146  exceeds a threshold, such as 100 ohms. Due to sensitivity of the circuitry to small resistance differences, an offset cancellation resistor maybe provided to account for line loss caused by different conductive path lengths for the sense and sense feedback signals. 
       FIG. 2  is a schematic illustration of an apparatus  200  including a stacked semiconductor device in accordance with embodiments of the disclosure. The apparatus  200  may include an interface chip  210  and a stacked semiconductor device  240 . The interface chip  210  may include a control circuit  211 , a force signal driver force signal driver  212 , and an output circuit  220 . The control circuit  211  provides control signals to circuitry of the stacked semiconductor device  240 . The output circuit  220  may include comparator and latch circuits to compare voltages of sense signal with a voltage reference signal VREF and to latch a result of the comparison as an output signal OUT in response to a test clock signal TESTCLK. The output circuit  220  may include a series of serially-coupled transistors separated by resistances that are used to provide the VREF signal. The resistances and transistors may transistors be selected to compensate for line loss as the force and sense signals propagate through the stacked semiconductor device  240  during testing. The interface chip  210  further includes a row of p-type MOS transistors (e.g., the transistor  244 ) that selectively couple a TSV (e.g., the  246 ) to the output circuit  220  during a test. 
     The stacked semiconductor device  240  may include core chips  0 - 3   242 ( 0 - 242 ( 3 ). Each of the core chips  0 - 3   242 ( 0 - 242 ( 3 ) may include rows of TSVs providing connections between the cores, such as the  232 , the  246 , and the  247  of the core chip  0   242 ( 0 ). Each core chip may have a similar layout and structure. While the stacked semiconductor device  140  is depicted with 4 cores, additional core chips may be stacked onto the 4 core chips without departing from the scope of the disclosure. Each of the core chips may also include p-type MOS transistors (e.g., the transistor  243 ) that selectively couple a TSV (e.g., the  247 ) to the force signal from the force signal driver force signal driver  212 . 
     In an operation testing whether there is a short between the  246  and the  247 , the force signal driver force signal driver  212  may provide a force signal through the  232  to the  243  of the core chip  0   242 ( 0 ). The control circuit  211  may provide control signals to enable the respective p-type MOS transistors  243  and  244 . With the respective p-type MOS transistors  243  and  244  enabled, the force signal is provided to the  247  via the enabled p-type MOS transistor  243 . If there is a short between the  246  and the  247 , current will flow from the  247 , through the  246  and the respective p-type MOS transistor  244  to the output circuit  220  via the sense signal. If there is no short between the  246  and the  247 , then no current would flow to the output circuit  220  via the sense signal. The output circuit  220  may compare a voltage of the sense signal with the VREF voltage to determine whether there is a short. The OUT signal is provided from an output of the latch of the output circuit  220  based on the comparison and in response to the TESTCLK signal. 
     As shown in  FIGS. 1 and 2 , the circuitry is able to test for resistance and shorts to detect defects in TSVs of the stacked semiconductor device  140  and the stacked semiconductor device  240 . However, the implementations of the control circuitry  144 A- 144 D and  243 , and  244  in the stacked semiconductor device  140  and the stacked semiconductor device  240 , respectively, require a complete set of additional control circuitry for each additional TSV, and additional circuitry in the output circuit  120  and the output circuit  220  to account for differences in propagation distances of signals. With space constraints become tighter and signal frequencies becoming higher, a better solution may include reusing common circuitry and arranging circuitry to make propagation distances similar or equal. 
       FIG. 3  is a schematic illustration of an apparatus  300  including a stacked semiconductor device in accordance with embodiments of the disclosure. The apparatus  300  may include an interface chip  310  and a stacked semiconductor device  340 . The interface chip  310  may include a control circuit  311 , a force signal driver  312 , interface chip switch circuit  313 , and an output circuit  320 . The control circuit  311  provides control signals to the interface chip switch circuit  313  and to circuitry of the stacked semiconductor device  340 . The output circuit  320  may include amplifier circuits  322 ,  324 ,  326  and resistances R 1 -R 5  to compare voltages of a sense signal and a sense feedback signal and provide an analog output signal OUTA. The OUTA signal may provide an indication of actual resistance of target terminal connections  352 ,  354 ,  356 ,  358 . 
     The stacked semiconductor device  340  may include core chips  0 - 7   342 ( 0 - 242 ( 7 ). Each of the core chips  0 - 7   342 ( 0 - 242 ( 7 ) may include a respective buffer circuit  362 ( 0 )- 362 ( 7 ) and respective control circuitry  344 ( 0 )- 344 ( 7 ). Each of the core chips  0 - 7   342 ( 0 - 242 ( 7 ) may further include rows of terminals providing connections between the cores chips  0 - 7   342 ( 0 - 242 ( 7 ). The TSVs aligned between the core chips  0 - 7   342 ( 0 - 242 ( 7 ) to form columns, such as the TSV columns  332 ,  334 ,  336 ,  338  on a first portion (e.g., left side) of the core chips  0 - 7   342 ( 0 - 242 ( 7 ) and the TSV columns  333 ,  335 ,  337 ,  339  on another portion (e.g., right side) of the core chips  0 - 7   342 ( 0 - 242 ( 7 ). The terminals along the TSV columns  332 ,  334 ,  336 ,  338  may be directly connected in a direct, aligned path through the core chips  0 - 7   342 ( 0 - 242 ( 7 ) to the interface chip  310 . For example, in core chip  7   342 ( 7 ), the terminal  371  is aligned with and connected to the terminal  375 , the terminal  372  is aligned with and connected to the terminal  376 , the terminal  373  is aligned with and connected to the terminal  377 , and the terminal  374  is aligned with and connected to the terminal  378 . 
     The terminals associated with the TSV columns  333 ,  335 ,  337 ,  339  may be connected in a spiral (e.g., staggered) structure such that the terminal connections are offset in one direction from one core chip to an adjacent core chip, with an outer most terminal coupled to an inner most terminal of a lower core chip via a respective buffer circuit  362 ( 0 )- 362 ( 7 ). For example, in core chip  7   342 ( 7 ), the terminal  391  is connected to the terminal  397 , the terminal  392  is and connected to the terminal  398 , the terminal  393  is connected to the terminal  399  via the buffer circuit  362 ( 7 ). The interface chip switch circuit  313  may include sense feedback transistors  314 ( 0 )- 314 ( 3 ) and force feedback transistors  315 ( 0 )- 315 ( 3 ). The sense feedback transistors  314 ( 0 )- 314 ( 3 ) and the force feedback transistors  315 ( 0 )- 315 ( 3 ) are each connected to between the output circuit  320  and a TSV within the interface chip  310  along a respective one of the columns of TSVs  333 ,  335 ,  337 . 
     The buffer circuits  362 ( 0 )- 362 ( 7 ) may control propagation of signals in one direction from a TSV of the TSV column  333  of one core chip to a TSV of the TSV column  339  of an above adjacent core, and may control propagation of signals in an opposite direction from a TSV of the TSV column  339  of one core chip to a TSV of the TSV column  333  of a below adjacent core. Typically, the buffer circuits  362 ( 0 )- 362 ( 7 ) may be enabled during normal operation and may be disabled during test of the TSVs of the TSV columns  333 ,  335 ,  337 ,  339 . The control circuitry  344 ( 0 )- 344 ( 7 ) in each of the core chips may include p-type MOS transistors that are used during testing to perform testing of TSVs within the TSV columns  333 ,  335 ,  337 ,  339  for a total of four TSVs tested during a single test. For example, in core chip  7   342 ( 7 ), the control circuitry  344 ( 7 ) includes a force feedback transistor  382 , a force transistor  384 , a sense feedback transistor  386 , and a sense transistor  388 . The force feedback transistor  382  is coupled to a node between the terminal  373  and the terminal  377  and to a node between the  362 ( 7 ) and the terminal  394 . The force transistor  384  is coupled to a node between the terminal  371  and the terminal  375  and to a node between the  362 ( 7 ) and the terminal  396 . The sense feedback transistor  386  is coupled to a node between the terminal  374  and the terminal  378  and to a node between the  362 ( 7 ) and the terminal  394 . The sense transistor  388  is coupled to a node between the terminal  371  and the terminal  375  and to a node between the  362 ( 7 ) and the terminal  396 . The control circuitry  344 ( 0 )- 344 ( 6 ) of the other core chips  0 - 6   342 ( 0 )- 342 ( 6 ) may include the same corresponding transistors  382 ,  384 ,  386 , and  388  that perform the same function as the transistors  382 ,  384 ,  386 , and  388  of the control circuitry  344 ( 7 ) of core chip  7   342 ( 7 ). The terminal  391  is connected to the terminal  397 , the terminal  392  is and connected to the terminal  398 , the terminal  393  is connected to the terminal  399  via the buffer circuit  362 ( 7 ). 
       FIG. 3  depicts an operation of testing four terminal connections  352 ,  354 ,  356 , and  358  within the TSV columns  333 ,  335 ,  337 , and  339 , respectively, and in core chips  3 - 0   342 ( 3 )- 342 ( 0 ), respectively. During the test, the force signal driver force signal driver  312  may provide a force signal having a constant current through the TSV column  332 . The control circuit  311  may disable the buffer circuits  362 ( 0 )- 362 ( 7 ) and may enable the force transistor  384  and the sense transistor  388  of the control circuitry  344 ( 3 ) (e.g., core chip  3   342 ( 3 ) transistors  384  and  388  are circled in the  FIG. 3 ) of core chip  3   342 ( 3 ) and the sense transistor  314 ( 3 ) and the force transistor  315 ( 3 ) of the interface chip switch circuit  313  (e.g., the sense transistor  314 ( 3 ) and the force transistor  315 ( 3 ) are circled in the  FIG. 3 ). The buffer circuits  362 ( 0 )- 362 ( 7 ) may be disabled to prevent propagation of the force signal through terminals of the core chips  4 - 7   342 ( 4 )- 342 ( 7 ). The force signal may propagate through the TSV column  332 , across core chip  3   342 ( 3 ), through the force transistor  384  of the control circuitry  344 ( 3 ), and through the terminal connections  352 ,  354 ,  356 , and  358  of core chips  3 - 0   342 ( 3 )- 342 ( 0 ), respectively. The force feedback signal may propagate from the terminal  358  through the force transistor  315 ( 3 ) to force signal driver force signal driver  312 . The force feedback signal may be compared with a reference voltage signal VREF by the force signal driver force signal driver  312  to maintain a constant current on the force signal. 
     In response to the force signal, the sense signal may propagate from a node at one end of the terminal  352  through the sense transistor  388  of the control circuitry  344 ( 3 ), across the core chip  3   342 ( 3 ), and through terminals of the TSV column  334  of core chips  3 - 0   342 ( 3 )- 342 ( 0 ) and across the interface chip  310  to the output circuit  320 . The sense feedback signal may flow from the TSV  358  through the sense transistor  314 ( 3 ) to output circuit  320 . Because of the routing of the sense/sense feedback signals and the force/force feedback signals, the propagation distances may be approximately equal, which may mitigate issues caused by different propagation distances. The amplifier  322  may compare the sense voltage with a divided output voltage of the amplifier  322  via the R 1  resistance to provide a sense output voltage. The amplifier  324  may compare the sense voltage with a divided output voltage of the amplifier  324  via the R 3  resistance to provide a sense feedback output voltage. The sense output voltage and the sense feedback voltages may be provided to inputs of the amplifier  326  via resistances R 5  and R 4 , respectively. The amplifier  326  may provide an output signal OUTA based on the comparison. The OUTA signal may indicate a resistance through the terminal connections  352 ,  354 ,  356 , and  358 . 
     As shown in  FIG. 3 , rather than having separate, individual control circuitry for each TSV of the cores, the core chips  342 ( 0 )- 342 ( 7 ) may include a spiral structure in the TSV columns  333 ,  335 ,  337 ,  339 , the control circuitry  344 ( 0 )- 344 ( 7 ), and the buffer circuits  362 ( 0 )- 362 ( 7 ) that allow for testing of a set of TSVs across a subset of the core chips  342 ( 0 )- 342 ( 7 ). 
       FIG. 4  is a schematic illustration of an apparatus  400  including a stacked semiconductor device in accordance with embodiments of the disclosure. The apparatus  400  may include elements that have been previously described with respect to the apparatus  300  of  FIG. 3 . Those elements have been identified in  FIG. 4  using the same reference numbers used in  FIG. 3  and operation of the common elements is as previously described. Consequently, a detailed description of the operation of these particular elements will not be repeated in the interest of brevity. 
       FIG. 4  depicts an operation of testing four terminal connections  451 ,  452 ,  453 , and  454  within the TSV columns  333 ,  335 ,  337 , and  339 , respectively, and in core chips  7 - 4   342 ( 7 )- 342 ( 4 ), respectively. During the test, the force signal driver force signal driver  312  may provide a force signal having a constant current through the TSV column  332 . The control circuit  311  may disable the buffer circuits  362 ( 0 )- 362 ( 3 ) and may enable the force transistor  384  and the sense transistor  388  of the control circuitry  344 ( 7 ) of core chip  7   342 ( 7 ) and the force feedback transistor  382  and sense feedback transistor  386  of the control circuitry  344 ( 3 ) of core chip  3   342 ( 3 ). The buffer circuits  362 ( 0 )- 362 ( 7 ) may be disabled to prevent propagation of the force signal through TSVs of core chips  3 - 0   342 ( 3 )- 342 ( 0 ). The force signal may propagate through the TSV column  332 , across core chip  7   342 ( 7 ), through the force transistor  384  of the control circuitry  344 ( 7 ), and through the terminal connections  451 ,  452 ,  453 , and  454  of core chips  7 - 4   342 ( 7 )- 342 ( 4 ), respectively. The force feedback signal may propagate from the terminal connection  454  through the force feedback transistor  382  of the control circuitry  344 ( 3 ), across the core chip  3   342 ( 3 ), and through terminal connections of the TSV column  336  of core chips  3 - 0   342 ( 3 )- 342 ( 0 ) to the force signal driver force signal driver  312 . The force feedback signal may be compared with a reference voltage signal VREF by the force signal driver force signal driver  312  to maintain a constant current on the force signal. 
     In response to the force signal, the sense signal may propagate from a node at one end of the TSV  451  through the sense transistor  388  of the control circuitry  344 ( 7 ), across the core chip  7   342 ( 7 ) and through terminal connections of the TSV column  334  of core chips  7 - 0   342 ( 7 )- 342 ( 0 ), and across the interface chip  310  to the output circuit  320 . The sense feedback signal may propagate from the TSV  454  through the sense feedback transistor  386  of the control circuitry  344 ( 3 ), across the core chip  3   342 ( 3 ), and through TSVs of the TSV column  338  of core chips  3 - 0   342 ( 3 )- 342 ( 0 ) to the output circuit  320 . Because of the routing of the sense/sense feedback signals and the force/force feedback signals, the propagation distances may be approximately equal, which may mitigate issues caused by different propagation distances. The output circuit  320  may provide an output signal OUTA based on a comparison between the sense and sense feedback signals as described with reference to  FIG. 3 . The OUTA signal may indicate a resistance through the TSVs  352 ,  354 ,  356 , and  358 . 
     While  FIGS. 3 and 4  depict testing specific terminal connections of the TSV columns  333 ,  335 ,  337 ,  339  of the core chips  0 - 7   342 ( 0 )- 342 ( 7 ), other terminal connections of the TSV columns  333 ,  335 ,  337 ,  339  of the core chips  0 - 7   342 ( 0 )- 342 ( 7 ) may be implemented using similar methods to control circuitry  344 ( 0 )- 344 ( 7 ) of other core chips and/or the interface chip switch circuit  313  to perform the testing. 
       FIG. 5  is a schematic illustration of an apparatus  500  including a stacked semiconductor device in accordance with embodiments of the disclosure. The apparatus  500  may include elements that have been previously described with respect to the apparatus  300  of  FIG. 3 . Those elements have been identified in  FIG. 5  using the same reference numbers used in  FIG. 3  and operation of the common elements is as previously described. Consequently, a detailed description of the operation of these particular elements will not be repeated in the interest of brevity. The interface chip  510  may include a control circuit  511 , a force short transistor  518 , a force short feedback transistor  519 , and an output circuit  520 . The force short transistor  518  and the force short feedback transistor  519  may drive a VDD voltage to the non-target terminals during a short test in response to a control signal. The output circuit  520 , in addition to the amplifier  322 , the amplifier  324 , the amplifier  326 , and resistances R 1 -R 7  described with reference to  FIG. 3 , a transistor  522  configured to couple a short signal to ground and a comparator  524  configured to compare the short signal to a voltage reference signal VREF 2  to determine whether any of the terminals of terminal connections  551 - 558  are shorted to adjacent terminals. The control circuit  511  may provide a control signal and the VREF 2  to the transistor  522  and the comparator  524 , respectively. 
       FIG. 5  depicts an operation to test eight terminal connections  551 - 558  within the TSV columns  333 ,  335 ,  337 , and  339  of the core chips  0 - 7   342 ( 0 )-( 7 ) for short circuits between adjacent terminals within the TSV columns  333 ,  335 ,  337 , and  339 . The terminal connections  551 - 558  may also be tested for a short to a ground voltage VSS. During the short to adjacent terminal test, the force short transistor  518  and the force short feedback transistor  519  may provide force and force feedback signals having VDD voltages through the TSV column  332  and the TSV column  336 , respectively, in response to a control signal from the control circuit  311 . The control circuit  311  may disable the buffer circuits  362 ( 0 )- 362 ( 7 ) and may enable the force feedback transistor  382  and the force transistor  384  of the control circuitry  344 ( 0 )- 344 ( 2 ) and  344 ( 4 )- 344 ( 6 ) of core chips  0 - 2  and  4 - 6   342 ( 0 )- 342 ( 2 ) and  342 ( 4 )- 344 ( 6 ), respectively. The control circuit  311  may also enable the sense feedback transistor  386  of the control circuitry  344 ( 3 ) and  344 ( 7 ) of the core chips  3  and  7   342 ( 3 ) and  342 ( 7 ), respectively. The control circuit  311  may also enable the sense transistor  314 ( 3 ). The force signal and force feedback signals may propagate through all terminals of the TSV columns  333 ,  335 ,  337 , and  339  except terminal connections  551 - 558 . 
     The short signal may propagate through the terminal connections  551 - 558  to the output circuit  520  through the sense feedback transistor  386  of the control circuitry  344 ( 3 ) and  344 ( 7 ) and the TSV column  338  and through the sense transistor  314 ( 3 ). The comparator  524  may compare the short signal to a voltage reference signal to determine any of the terminals of the terminal connections  551 - 558  are shorted to an adjacent terminal may cause the short signal to have a voltage higher than the reference voltage. Otherwise, the short signal voltage may be a low voltage signal. 
     In a second test, the control circuit  511  may disable the transistor  522 , and may disable the force feedback transistor  382  and the force transistor  384  of the control circuitry  344 ( 0 )- 344 ( 7 ), enable the sense feedback transistor  386  of the control circuitry  344 ( 3 ) and  344 ( 7 ), enabled the force short transistor  518  and the force short feedback transistor  519  may provide force and force feedback signals having VDD voltages, and enable the sense transistor  314 ( 3 ). This may precharge the terminals of the TSV columns  333 ,  335 ,  337 , and  339  to the VDD voltage. The control circuit  511  may subsequently disable the force feedback transistor  382  and the force transistor  384  of the control circuitry  344 ( 3 ) and  344 ( 7 ), which may leave the terminal connections  551 - 558  in a floating state. The output circuit  520  may sense a voltage of the short signal after a predetermined time period. If the terminal connections  551 - 558  are shorted to a VSS source, the precharged voltage on the short signal will dissipate more quickly than if there is no short to a VSS source. 
       FIG. 6  and  FIG. 7  are cross-sectional views  600  and  700  showing the TSV structures according to embodiments of the disclosure. In some examples, the TSV 1 -TSV 4  structures  610 ( 1 )- 610 ( 4 ) may be implemented in TSVs included in the TSV columns  332 ,  334 ,  336 ,  338  of the core chips  0 - 7   342 ( 0 )-( 7 ) of  FIGS. 3-5 . In some examples, the TSV structures  710 ( 1 )- 710 ( 4 ) may be implemented in TSVs included in the TSV columns  333 ,  335 ,  337 ,  339  of the core chips  0 - 7   342 ( 0 )-( 7 ) of  FIGS. 3-5 . As shown in  FIG. 6 , the each of the TSV  1 -TSV 4  structures  610 ( 1 )- 610 ( 4 ) may penetrate through the silicon substrate  680 , an interlayer insulating film  681 , which is provided on a front surface of the silicon substrate  680 , and a passivation film  683 , which is provided on a back surface of the silicon substrate  680 . The TSV 1 -TSV 4  structures  610 ( 1 )- 610 ( 4 ) are not particularly limited to, but are formed of Cu (copper). The front surface (the upper-side surface in  FIG. 6 ) of the silicon substrate  680  is a device formation surface on which devices such as transistors are formed. Insulating rings  682  are provided around each of the TSV 1 -TSV 4  structures  610 ( 1 )- 610 ( 4 ), thereby ensuring insulation between each of the TSV 1 -TSV 4  structures  610 ( 1 )- 610 ( 4 ) and the transistor region. In the example shown in  FIG. 6 , the insulating rings  682  are doubly provided, thereby reducing the electrostatic capacity between each of the TSV 1 -TSV 4  structures  610 ( 1 )- 610 ( 4 ) and the silicon substrate  680 . The insulating rings  682  may be single instead of being double. Moreover, in place of providing insulating rings  682 , insulating sidewalls may be provided on the surface of TSV 1 -TSV 4  of the TSV 1 -TSV 4  structures  610 ( 1 )- 610 ( 4 ) with no insulating rings. 
     An end part of each of the TSV 1 -TSV 4  structures  610 ( 1 )- 610 ( 4 ) in the back surface side of the silicon substrate  680  is covered with the back-surface bump BB. The BB bump may contact a corresponding front-surface bump FB of an adjacent core chip or interface chip, such as the core chips  0 - 7   342 ( 0 )-( 7 ) or the interface chip  310 /interface chip  510  of  FIGS. 3-5 . The back-surface bumps BB are not particularly limited to, but are formed of SnAg solder covering the surface of the penetrating electrodes TSV 1 . 
     Insulating layers corresponding to five layers including the above described interlayer insulating film  681  are formed on the front surface of the silicon substrate  680 . The uppermost layer thereof is a passivation film  684 . On the front surfaces of the layers excluding the passivation film  684 , wiring layers L 1  to LA are sequentially formed from the side that is closer to the front surface of the silicon substrate  680 . The wiring layers L 1  to L 4  are comprised of pads M 1  to M 4 , respectively. Among them, the pad M 1  is in contact with the end part of the penetrating electrode TSV 1  that is in the front surface side of the silicon substrate  680 . In the layers excluding the interlayer insulating film  81  and the passivation film  684 , a plurality of through-hole electrodes TH 1  to TH 3  are provided sequentially from the side that is close to the front surface of the silicon substrate  680 , thereby mutually connecting the pads M 1  to M 4 . 
     The front-surface bump FB is connected to the pad M 4  via a pillar part  686 , which is penetrating through the passivation film  684 . Therefore, the front-surface bump FB is connected to the end part of each of the TSV 1 -TSV 4  structures  610 ( 1 )- 610 ( 4 ) via the pillar part  686 , the pads M to M 4 , and the through-hole electrodes TH 1  to TH 3 . The front-surface bumps FB are in contact with the back-surface bumps BB of an adjacent core chip or interface chip, such as the core chips  0 - 7   342 ( 0 )-( 7 ) or the interface chip  310 /interface chip  510  of  FIGS. 3-5 . The front-surface bumps FB are in contact with the substrate electrode  691  on the interposer IP. The front-surface bump FB is not particularly limited, but has the pillar part  686  formed of Cu (copper). The surface of the pillar part  686  has a stacked structure of Ni (nickel) and Au (gold). The diameters of the front-surface bumps FB and the back-surface bumps BB are about 20 μm. 
     The front surface of the passivation film  684  is covered with a polyimide film  85  excluding the region in which the front-surface bump FB is formed. The connection with internal circuits not shown is established via internal wiring (not shown) extended from the pads M 1  to M 3  provided in the wiring layers L 1  to L 3 . 
     In this manner, each of the TSV 1 -TSV 4  structures  610 ( 1 )- 610 ( 4 ) are connected to the front-surface bump FB and the back-surface bump BB provided at the same position of the same chip in the planar view. Since each of the TSV 1 -TSV 4  structures  610 ( 1 )- 610 ( 4 ) are commonly connected to the core chips, each of the TSV  1 -TSV 4  structures  610 ( 1 )- 610 ( 4 ) may be used as, for example, power supply paths. 
     Referring to  FIG. 7 , the TSV 1 -TSV 4  structures  710 ( 1 )- 710 ( 4 ) may include elements that have been previously described with respect to the TSV 1 -TSV 4  structures  610 ( 1 )- 610 ( 4 ) of  FIG. 6 . Those elements have been identified in  FIG. 7  using the same reference numbers used in  FIG. 6  and operation of the common elements is as previously described. Consequently, a detailed description of the operation of these particular elements will not be repeated in the interest of brevity. As shown in  FIG. 7 , each of the TSV 1 -TSV 4  structures  710 ( 1 )- 710 ( 4 ) are not provided with the through-hole electrode TH 2 , which connects the pad M 2  and the pad M 3  at the same planar position. Therefore, the front-surface bump FB and the back-surface bump BB at the same planar position are not short-circuited with each other. Rather, the front-surface bump FB of the TSV 1  structure  710 ( 1 ) is connected to the back-surface bump BB of the TSV 2  structure  710 ( 2 ), the front-surface bump FB of the TSV 2  structure  710 ( 2 ) is connected to the back-surface bump BB of the TSV 3  structure  710 ( 3 ), the front-surface bump FB of the TSV 3  structure  710 ( 3 ) is connected to the back-surface bump BB of the TSV 4  structure  710 ( 4 ), and the front-surface bump FB of the TSV 4  structure  710 ( 4 ) loops back to connect to the back-surface bump BB of the TSV 1  structure  710 ( 1 ) via an intermediate buffer  788 . While the intermediate buffer  788  is shown as unidirectional, the intermediate buffer  788  may be bi-directional. The intermediate buffer  788  may be implemented in any of the intermediate buffers  362 ( 0 )- 362 ( 7 ) of  FIGS. 3-5 . Regarding the other points, the TSV 1 -TSV 4  structures  710 ( 1 )- 710 ( 4 ) and the TSV 1 -TSV 4  structures  610 ( 1 )- 610 ( 4 ) have the same structure. 
     Each of the TSV 1 -TSV 4  structures  710 ( 1 )- 710 ( 4 ) are spirally connected so that they are used, for example, in a case in which an interface chip and a core chip are individually connected. 
       FIG. 8  is a block diagram of an intermediate buffer  800  according to an embodiment of the disclosure. The intermediate buffer  800  may include a write first in, first out (WFIFO)  810  configured to propagate data in a first direction and a read first in, first out (RFIFO)  820  configured to propagate data in a second direction. The intermediate buffer  800  may be implemented in any of the intermediate buffers  362 ( 0 )- 362 ( 7 ) of  FIGS. 3-5  and/or the intermediate buffer  788  of  FIG. 7 . 
     A first input buffer  812  is provided at an input of the WFIFO  810  and a first output buffer  814  is provided at an output of the WFIFO  810 . A second input buffer  822  is provided at an input of the RFIFO  820  and a second output buffer  824  is provided at an output of the RFIFO  820 . The first input buffer  812  is activated to pass data to the WFIFO  810  in response to a first input buffer control signal CIB 1  and the first output buffer  814  is activated to pass data from the WFIFO  810  in response to a first output buffer control signal COB 1 . The second input buffer  822  is activated to pass data to the RFIFO  820  in response to a second input buffer control signal CIB 2  and the second output buffer  824  is activated to pass data from the RFIFO  820  in response to a second output buffer control signal COB 2 . Each of the WFIFO  810  and the RFIFO  820  are FIFO circuits having a first-in/first-out function. 
     During normal operation, the CIB 1 / 2  and the COB 1 / 2  may be selectively activated to propagate data or signals through the intermediate buffer  800  from a core chip lower terminal to a core chip upper terminal or from a core chip upper terminal to a core chip lower terminal. During testing, the CIB 1 / 2  and the COB 1 / 2  may remain deactivated to prevent propagation of any data or signals through the intermediate buffer  800 . 
       FIG. 9  is a schematic illustration of an apparatus  900  including a stacked semiconductor device in accordance with embodiments of the disclosure. The apparatus  900  may include elements that have been previously described with respect to the apparatus  300  of  FIG. 3 . Those elements have been identified in  FIG. 9  using the same reference numbers used in  FIG. 3  and operation of the common elements is as previously described. Consequently, a detailed description of the operation of these particular elements will not be repeated in the interest of brevity. 
     The apparatus  900  may include a stacked semiconductor device  940  having the core chips  0 - 6   342 ( 0 )- 342 ( 6 ) and a core chip  7   942 ( 7 ) stacked on top of the core chip  6   342 ( 6 ). In contrast to the core chip  7   362 ( 7 ) of  FIGS. 3-5 , the core chip  7   942 ( 7 ) has a height H 2  that is greater than the height H 1  of others of the core chips  0 - 6   362 ( 0 )- 362 ( 6 ). The core chip  7   942 ( 7 ) is also without the upper terminals  371 - 374  and  391 - 394  and the intermediate buffer  362 ( 7 ). Otherwise, the core chip  7   962 ( 7 ) operates similarly to the core chip 
       FIG. 10A  is a schematic diagram of a stacked semiconductor device  1000  and logic circuits  1001 - 1006  for providing control signals in accordance with embodiments of the disclosure. The stacked semiconductor device  1000  may include elements that have been previously described with respect to the apparatus  300  of  FIG. 3 . Those elements have been identified in  FIG. 10  using the same reference numbers used in  FIG. 3  and operation of the common elements is as previously described. Consequently, a detailed description of the operation of these particular elements will not be repeated in the interest of brevity. The logic circuits  1001 - 1006  may be implemented in a control circuit, such as the control circuit  311  of  FIGS. 3, 4, and 9 , the control circuit  511  of  FIG. 5 , or combinations thereof. 
     The force feedback transistor  382  of the control circuitry  344 ( 3 ) and  344 ( 7 ) may receive a force feedback control signal FFBCS at a gate to control the force feedback transistor  382  to provide the force feedback signal, the force transistor  384  of the control circuitry  344 ( 3 ) and  344 ( 7 ) may receive a force control signal FCS at a gate to control the force transistor  384  to provide the force signal, the sense feedback transistor  386  of the control circuitry  344 ( 3 ) and  344 ( 7 ) may receive a sense feedback control signal SFBCS at a gate to control the sense feedback transistor  386  to provide the sense feedback signal, and the sense transistor  388  of the control circuitry  344 ( 3 ) and  344 ( 7 ) may receive a sense control signal SCS at a gate to control the sense transistor  388  to provide the sense signal. The sense feedback transistor  314 ( 3 ) may receive the interface chip sense feedback control signal IFSFBCS &lt;3&gt; at a gate to control the sense feedback transistor  314 ( 3 ) to provide the sense feedback signal. The force feedback transistor  315 ( 3 ) may receive the interface chip force feedback control signal IFFFBCS&lt;3&gt; at a gate to control the force feedback transistor  314 ( 3 ) to provide the force feedback signal. For the sense feedback transistors  314 ( 0 )- 314 ( 2 ) of  FIGS. 3-5 , IFSFBCS &lt;0:2&gt; signals may be provided to control provision of the sense feedback signal. For the force feedback transistors  315 ( 0 )- 314 ( 2 ) of  FIGS. 3-5 , IFFFBCS &lt;0:2&gt; signals may be provided to control provision of the force feedback signal. 
     The logic circuit  1001  may include components  1010 - 1016  (e.g., inverter  1010 , multiplexer  1011 , inverter  1012 , NAND gate  1013 , inverter  1014 , NOR gate  1015 , and inverter  1016 ) to control a value of the FCS control signal based on a lower core test mode signal TMCL (e.g., whether an upper or lower core chip is being tested, such as core chips  0 - 3   342 ( 0 )- 342 ( 3 ) or core chips  4 - 7   342 ( 4 )- 342 ( 7 )), a core chip identifier signal CID (e.g., testing which of core chips  0 - 7 ), a non-targeted core disable signal TMCD (e.g., disabling non-targeted cores during an operation), and a four port test mode signal TM4P (e.g., indicates testing for resistance through the terminals as described with reference to  FIGS. 3 and 4 ). 
     The logic circuit  1002  may include components  1020 - 1026  (e.g., inverter  1020 , multiplexer  1021 , inverter  1022 , NAND gate  1023 , inverter  1024 , two input NOR gate  1025 , and inverter  1026 ) to control a value of the SCS control signal based on the TMCL signal, the CID signal, the TMCD signal, and the TM4P signal. 
     The logic circuit  1003  may include components  1030 - 1037  (e.g., inverter  1030 , inverter  1031 , multiplexer  1032 , inverter  1033 , NAND gate  1034 , inverter  1035 , NOR gate  1036 , and inverter  1037 ) to control a value of the FFBCS control signal based on the TMCL signal, the CID signal, the TMCD signal, and the TM4P signal. 
     The logic circuit  1004  may include components  1041 - 1047  (e.g., inverter  1040 , inverter  1041 , multiplexer  1042 , inverter  1043 , NAND gate  1044 , inverter  1045 , and NOR gate  1046 , and inverter  1047 ) to control a value of the SFBCS control signal based on the TMCL signal, the CID signal, the TMCD signal, and the TM4P signal. 
     The logic circuit  1005  may include components  1060 - 1063  to control a value of the IFFFBCS&lt;0:3&gt; control signals based on the TMCL signal, a core group selection signal &lt;0:3&gt; signal TMCID&lt;0:3&gt; (e.g., selection of amplifiers associated with an access of a core chip block, such as setting the TMCID signal for core chips  0 - 3   342 ( 0 )- 342 ( 3 ) while set to a first value and setting the TMCID signal for core chips  4 - 7   342 ( 4 )- 342 ( 7 ) while set to a second value), the TMS signal, and the TM4P signal. 
     The logic circuit  1006  may include components  1070 - 1073  to control a value of the IFSFBCS&lt;0:3&gt; control signals based on the TMCL signal, the TMCID&lt;0:3&gt; signal, the TMS signal, and the TM4P signal. 
       FIG. 10B  is a schematic diagram of alternative logic circuits  1001 A- 1006 A for providing control signals in accordance with embodiments of the disclosure. The stacked logic circuits  1001 A- 1004 A may include elements that have been previously described with respect to the logic circuits  1001 - 1004  of  FIG. 10A . Those elements have been identified in  FIG. 10B  using the same reference numbers used in  FIG. 10A  and operation of the common elements is as previously described. Consequently, a detailed description of the operation of these particular elements will not be repeated in the interest of brevity. The logic circuits  1001 A- 1004 A may be implemented in a control circuit, such as the control circuit  311  of  FIGS. 3, 4, and 9 , the control circuit  511  of  FIG. 5 , or combinations thereof. 
     The logic circuit  1001 A may include components  1010 - 1015 ,  1016 A,  1017 , and  1018  (e.g., including NOR gate  1016 A, NAND gate  1017 , and inverter  1018 ) to control a value of the FCS control signal based on the TMCL signal, the CID signal, the TMCD signal, a short test mode signal TMS (e.g., indicates testing for electrical shorts between adjacent terminals as described with reference to  FIG. 5 ), and the TM4P signal. 
     The logic circuit  1002 A may include components  1020 - 1024 ,  1025 A, and  1026  (e.g., including three input NOR gate  1025 A) to control a value of the SCS control signal based on the TMCL signal, the CID signal, the TMCD signal, the TMS signal, and the TM4P signal. 
     The logic circuit  1003 A may include components  1030 - 1036 ,  1037 A,  1038 , and  1039  (e.g., including NOR gate  1037 A, NAND gate  1038 , and inverter  1039 ) to control a value of the FFBCS control signal based on the TMCL signal, the CID signal, the TMCD signal, the TMS signal, and the TM4P signal. 
     The logic circuit  1004 A may include components  1041 - 1047 ,  1048 A, and  1049 - 1051  (e.g., including NOR gate  1048 A, inverter  1049 , NAND gate  1050 , and inverter  1051 ) to control a value of the SFBCS control signal based on the TMCL signal, the CID signal, the TMCD signal, the TMS signal, and the TM4P signal. 
       FIG. 11  is an exemplary table of values of the control signals based on the logic circuits  1001 - 1006  of  FIG. 10  in accordance with embodiments of the disclosure. The column  1110  shows exemplary control signals for a resistance test upper, an example of which is illustrated and described with reference to  FIG. 4 . The column  1112  shows exemplary control signals for a resistance test lower, an example of which is illustrated and described with reference to  FIG. 3 . The column  1114  shows exemplary control signals for a short test, an example of which is illustrated and described with reference to  FIG. 5 . 
     From the foregoing it will be appreciated that, although specific embodiments of the present disclosure have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the present disclosure.