Patent Publication Number: US-10333463-B2

Title: Stress compensated oscillator circuitry and integrated circuit using the same

Description:
RELATED APPLICATION 
     This application claims priority to German Patent Application No. 102015202694.9, filed on Feb. 13, 2015, the content of which is incorporated by reference herein in its entirety. 
     DESCRIPTION 
     Embodiments of the invention relate to the field of integrated circuits, and more specifically, to the field of stress compensated oscillator circuitries and integrated circuits using the same. Moreover, embodiments of the invention relate to an on-chip oscillator with mechanical stress/strain compensation. 
     Integrated circuitries or integrated circuits (ICs) are typically mounted in plastic packages to protect the sensitive integrated circuitries from environmental influences. However, mounting an integrated circuitry in a plastic package can exert considerable mechanical stress on the semiconductor material and thus on the semiconductor substrate of the integrated circuitry. 
     The mechanical stress or the mechanical strain present in the semiconductor material of the semiconductor substrate and acting on the integrated circuitry is generally hard to reproduce because the mechanical stress depends on the combination of the materials used for the semiconductor substrate and for the package and, in addition, on the packaging process of the integrated circuitry itself. 
     Thus, mechanical stress problems are caused by packaging, soldering, humidity changes in plastic packages, bending effects of the die (the semiconductor substrate), trench influences to neighboring devices, etc. The mechanical instabilities lead to current and voltage changes in reference circuits and to changes in passive components like on-chip inductors, capacitors and resistors and active components (e.g. transistors, diodes etc.) in the order of about 3% of the nominal value caused by stress or strain induced piezo-effects in the passive and active components, respectively. 
     To summarize, mechanical stress seems to be a lifetime effect, but actually 90% of the drift effects of the behavior of integrated circuits is caused by packaging, soldering, humidity, and temperature gradients on the die (i.e. the semiconductor substrate), as an expansion of a plastic package leads to the bending of the chip. 
     Thus, up to now only 1% to 3% accuracy and stability over lifetime and temperature range of integrated circuitries could be achieved, even with a trimming approach on a wafer. 
     Therefore, there is a need for improved integrated circuits which work with high precision and high lifetime stability combined with a very low temperature drift and low power or phase noise. Thus, accurate and inexpensive low-power or low-phase noise for on-chip oscillators without external components are required for many integrated circuits (ICs) with digital protocols or RF interfaces. 
     SUMMARY OF THE INVENTION 
     Embodiments of the invention provide a stress compensated oscillator circuitry, comprising a sensor arrangement for providing a sensor output signal S Sensor , wherein the sensor output signal S Sensor  is based on an instantaneous stress or strain component σ in the semiconductor substrate, a processing arrangement for processing the sensor output signal S Sensor  and providing a control signal S Control  depending on the instantaneous stress or strain component σ in the semiconductor substrate, and an oscillator arrangement for providing an oscillator output signal S osc  having an oscillator frequency f osc  based on the control signal S Control , wherein the control signal S Control  controls the oscillator output signal S osc  (e.g. the oscillator frequency S osc  or amplitude A osc  of the oscillator output signal S osc ), and wherein the control signal S Control  reduces the influence of the instantaneous stress or strain component σ in the semiconductor substrate onto the oscillator output signal S osc , so that the oscillator circuitry provides a stress compensated oscillator output signal. 
     Embodiments of the invention also provide an integrated circuit comprising a stress compensated oscillator circuitry having a sensor arrangement for providing a sensor output signal S Sensor , wherein the sensor output signal S Sensor  is based on an instantaneous stress or strain component σ in the semiconductor substrate, a processing arrangement for processing the sensor output signal S Sensor  and providing a control signal S Control  depending on the instantaneous stress or strain component σ in the semiconductor substrate, and an oscillator arrangement for providing an oscillator output signal S osc  having an oscillator frequency f osc  based on the control signal S Control , wherein the control signal S Control  controls the oscillator output signal S osc  (e.g. the oscillator frequency S osc  or amplitude A osc  of the oscillator output signal S osc ), and wherein the control signal S Control  reduces the influence of the instantaneous stress or strain component σ in the semiconductor substrate onto the oscillator output signal S osc , so that the oscillator circuitry provides a stress compensated oscillator output signal, and a processing circuitry for performing a processing operation based on the stress compensated oscillator output signal provided by the stress-compensated oscillator circuitry. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       For a more complete understanding of the invention and the advantages thereof, reference is now made to the following description taken in conjunction with the accompanying drawings, in which: 
         FIG. 1  shows a schematic block diagram of a stress compensated oscillator circuitry in accordance with embodiments of the invention; 
         FIGS. 2 a -2 b    show general definitions of the crystallographic directions in the surface plane of the semiconductor substrate; 
         FIG. 3  shows a schematic block diagram of an integrated circuit in accordance with embodiments of the invention; 
         FIG. 4  shows a graphical illustration of the dependency of the oscillator output frequency of an exemplary (relaxation) oscillator from different stress components in the x- and y-direction in the semiconductor substrate; 
         FIG. 5 a    shows a schematic block diagram of different implementations of the sensor arrangement with different exemplary sensor elements in accordance with embodiments of the present invention; 
         FIG. 5 b    shows a schematic block diagram of different implementations of the sensor arrangement with different exemplary sensor elements in accordance with embodiments of the present invention; 
         FIG. 5 c    shows schematic implementations of exemplary sensor elements of the sensor arrangement in accordance with embodiments of the present invention; 
         FIG. 6 a    shows a schematic top view illustration of exemplary sensor elements of the sensor arrangement and of the influence of a deep trench arranged nearby to the sensor elements onto the different stress components acting on the sensor elements and onto the different piezo coefficients of the sensor elements in accordance with embodiments of the invention; 
         FIG. 6 b    a schematic cross-sectional illustration of exemplary sensor elements of the sensor arrangement and of the influence of a deep trench arranged near the exemplary sensor elements onto the different stress components acting on the sensor elements and onto the different piezo coefficients of the sensor elements in accordance with embodiments of the invention; 
         FIG. 7  shows a schematic illustration of an implementation of the sensor arrangement in the form of a stress sensitive current mirror circuit in accordance with embodiments of the invention; 
         FIG. 8 a    shows a schematic block diagram of a PLL oscillator with stress compensation via digital fractional values in accordance with embodiments of the invention; 
         FIG. 8 b    shows a schematic block diagram of an exemplary fractional PLL for the PLL oscillator with stress compensation via digital fractional values in accordance with embodiments of the invention; 
         FIG. 9  shows a schematic block diagram of a directly stress compensated LC-oscillator in accordance with embodiments of the invention; 
         FIG. 10 a    shows a schematic block diagram of a stress compensated oscillator with correction DAC for the integrator current in accordance with embodiments of the invention; 
         FIG. 10 b    shows a schematic block diagram of a relaxation oscillator with stress compensated integrator current by using a combination of devices with different stress components in accordance with embodiments of the invention; 
         FIG. 11 a    shows a schematic illustration of an LC oscillator with stress sensors and differential temperature sensors in accordance with embodiments of the invention; and 
         FIG. 11 b    shows a schematic illustration of an LC oscillator with stress sensors and differential temperature sensors in accordance with embodiments of the invention. 
     
    
    
     Before discussing the present invention in further detail using the drawings, it is pointed out that in the figures identical elements and elements having the same functionality and/or the same technical or physical effect are provided with the same reference numbers so that the description of these elements and of the functionality thereof illustrated in the different embodiments is mutually exchangeable or may be applied to one another in the different embodiments. 
     To be more specific, embodiments of the invention are discussed in detail below, however, it should be appreciated that the invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contacts. The specific embodiments discussed are merely illustrative of specific ways to make and use the invention, and do not limit the scope of the invention. In the following description of embodiments, the same or similar elements having the same function have associated therewith the same reference signs, and a description of such elements will not be repeated for every embodiment. 
     In the following, the invention will be described with respect to embodiments in the context of integrated oscillator circuits, for example LC or PLL oscillator circuits. However, the invention may also be applied to other integrated circuits, like any integrated circuits, the output signal thereof is not intended to be a signal which is dependent from a physical input signal, e.g. a signal to be measured, such as an external magnetic field or temperature or sensor signal voltage. The inventive concept can also be applied to stabilize voltage or current references or references based on resistor or capacitor values. 
       FIG. 1  is a schematic block diagram of a stress compensated (integrated) oscillator circuitry  10  for providing a stress compensated oscillator output signal s osc . The stress compensated oscillator circuitry  10  comprises a sensor arrangement  100  and is configured to provide a sensor output signal s sensor , wherein the sensor output signal s sensor  is based on instantaneous stress or strain component σ in the semiconductor substrate  20 . 
     The stress compensated oscillator circuitry  10  further comprises a processing (rendering) arrangement  200  which is configured to process or render the sensor output signal s sensor  and to provide a control signal s control  depending on the instantaneous stress or strain component in the semiconductor substrate  20  (as measured by the sensor arrangement  100 ). 
     The stress compensated oscillator circuitry  10  further comprises an oscillator arrangement  300 , which is configured to provide an oscillator output signal s osc  having an oscillator frequency f osc , wherein the oscillator output signal is based on the control signal s control  from the processing arrangement  200 . 
     The control signal s control  (provided by the processing arrangement  200  to a control input not shown in  FIG. 1  of the oscillator arrangement  300 ) controls the oscillator output signal s osc  (e.g. the oscillator frequency f osc  or the oscillator amplitude a osc  of the oscillator output signal s osc ), wherein the control signal s control  reduces the influence of the instantaneous stress or strain component in the semiconductor substrate (as measured by the sensor arrangement  100 ) onto the oscillator output signal s osc  (e.g. onto the oscillator frequency f osc  or the oscillator amplitude a osc  of the oscillator output signal s osc ), so that the oscillator circuitry  10  provides a stress compensated oscillator output signal s osc . 
     The sensor arrangement  100 , the processing arrangement  200  and the oscillator arrangement  300  may be arranged or integrated on the same semiconductor substrate  20 . 
     As indicated above, the control signal s control  provided by the processing arrangement is processed or rendered on the basis of the sensor output signal s sensor  and controls the oscillator arrangement in order to reduce the influence of the instantaneous stress or strain component in the semiconductor substrate (as measured by the sensor arrangement  100 ) onto the oscillator output signal s osc . Thus, the oscillator circuitry  10  provides a stress compensated oscillator output signal s out . Thus, the output signal of the stress compensated oscillator circuitry is within a tolerance range free from the influence of the instantaneous stress or strain component in the semiconductor substrate  20 . 
     Concerning the above indicated “tolerance range”, it is to be noted that in the art there are deviations from the theoretical ideal case in all fields of physics, these deviations from the functionality of the inventive compensation concept needing to be sufficiently small only, i.e. the influence of the instantaneous stress or strain component in the semiconductor substrate onto the oscillator frequency f osc  or the oscillator amplitude a osc  of the oscillator output signal s osc  is reduced by at least 50%, 80%, 90%, 99%, 99.9%, i.e. lie within a tolerance range of 50%, 20%, 10%, 1% or 0.1% form the ideal (stress uninfluenced) oscillator output signal. 
     Moreover, in order to facilitate the understanding of the following detailed description of the inventive stress compensated oscillator circuitry on a semiconductor substrate for providing a stress compensated oscillator output signal, a brief representation with regard to  FIGS. 2 a - b    of the definitions used below regarding the semiconductor material used and the predefined directions on the same with regard to the crystal alignment of the semiconductor material is provided. The semiconductor surface (die or wafer surface) is associated with a crystallographic plane. To determine the respective plane in a cubic crystal, the so-called Miller indices are used, which are indicated in ground (below). For example,  FIG. 2 a    shows a plan view, for example, of a semiconductor wafer cut in the (100) plane. 
     The main crystallographic directions in the wafer plane are marked in  FIG. 2 a - b    with respect to the so-called “primary flat” at the silicon wafer. Usually the edges of the rectangular geometries of the circuit structures on the semiconductor chip extend in parallel with and/or perpendicularly to the primary flats. In  FIG. 2 a   , in particular, the crystallographic directions and/or axes are represented in the plane of the semiconductor wafer, these being represented in square brackets below. The coordinate system is usually employed such that the [110] direction extends perpendicularly to the primary flat, whereas the [110] direction extends in parallel with the primary flat. The directions [010] and [100] here extend at an angle of +/−45° in relation to the [110] direction. 
     In addition, an angle φ is defined in relation to the [110] direction, the angle φ being counted in an anti-clockwise manner, starting from the [110] direction, in a plan view of the topside of the wafer. Usually, the individual chips are positioned at the wafer such that the directions φ=0° and φ=90° correspond to the IC vertical and horizontal directions, respectively. 
     As a packaged integrated circuit chip is generally structured in a layered manner, a limitation to the planar stress condition is possible, i.e. a limitation to two normal stress components, σ XX , σ YY  and one sheer stress component σ XY , as exemplarily illustrated in  FIG. 2 b   . In accordance with the definition, the x- and y-axes are arranged in parallel with the edges of the semiconductor substrate. The remaining stress components are essentially negligibly small and only have a minor influence on the electronic circuit components. At a sufficiently large distance from the edge of the semiconductor chip and in particular in the center of a semiconductor substrate, the sheer stress component σ XY  is usually negligibly small. Thus, essentially only the two normal stress components σ XX  and σ YY  remain to be considered. 
     Moreover, a variety of piezo-effects are present in the semiconductor material of a semiconductor material of a semiconductor substrate, such as the piezo-resistive effect, piezo-MOS effect, piezo-junction effect, piezo-Hall effect and/or piezo-tunnel effect. Each of these piezo-effects alone or in combination may have an effect on relevant electrical and/or electronic parameters of the integrated circuit due to mechanical stress in the semiconductor substrate of the integrated circuit during operation thereof. In connection with the description below, the general term “instantaneous stress or strain component in the semiconductor substrate” (i.e. piezo-effects and also pure strain effects) is to generally refer to the changes of electrical and/or electronic parameters of the circuitry integrated in the semiconductor substrate under the influence of mechanical stress in the semiconductor material. 
     Mechanical stress in the semiconductor material results in a change in the properties of the charge carriers with regard to the charge-carrier transport, such as mobility, collision time, scattering factor, etc. In more general words, the piezo-resistive effect determines how the specific ohmic resistance of the respective semiconductor material will behave under the influence of mechanical stress. The piezo-junction effect results, for example, in changes in the characteristics of diodes and bipolar transistors. The piezo-tunnel effect occurs at a reversely operated, highly doped, shallow lateral pn-junction. This current is dominated by band-to-band tunnel effects and is also dependent on stresses. Thus, the sensor output signal as sensor of the sensor arrangement  100 , e.g. piezo stress sensors, can be used for compensating piezo stress influences. 
     In accordance with embodiments, the sensor output signal s sensor  of the piezo stress sensors of the sensor arrangement  100  can also be used to compensate for strain effects. To be more specific, the expansion of a metal inductance coil of an (LC) oscillator changes, for example, merely by chip (=semiconductor substrate) bending. The piezo-effects in the metal coil, however, can be neglected. Merely due to chip bending, the size of the coil element changes and hence its inductance as well as the width of the conductive trace and accordingly its internal resistance changes. These effects are pure strain effects and describable due to Hooke&#39;s law (elastic deformation case). 
     According to embodiments, the processing arrangement  200  can be configured to consider the plastic deformation case and the viscoelastic deformation case, wherein the history of temperature and stress is detected by the sensor arrangement  100  and is latched in a memory (not shown in  FIG. 1 ) associated to the processing arrangement  200 , wherein based on the information stored in the memory and on the instantaneous stress or strain components, measured by the sensor arrangement  100 , the processing arrangement  200  can generate and provide the control signal (e.g. correction signals), wherein the control signal, which may comprise a plurality of partial control signals or different correction signals, depends on the direction of the measured stress or strain and on the deviation of the temperature (or temperature gradient) in the semiconductor substrate. 
     In accordance with embodiments, the sensor arrangement, the processing arrangement and the oscillator arrangement are integrated on the same semiconductor substrate. 
     In accordance with embodiments, the sensor arrangement comprises a plurality of sensor elements, each sensor element sensing an instantaneous stress or strain component σ in the semiconductor material  20 . 
     In accordance with embodiments, the plurality of sensor elements are configured to sense the instantaneous stress and strain components σ xx , σ yy  which are orthogonal to each other and in plane with respect to the surface of the semiconductor substrate. 
     In accordance with embodiments, the plurality of sensor elements are piezo-sensitive sensor elements. 
     In accordance with embodiments, the piezo-sensitive sensor elements extend lateral and/or vertical in the semiconductor material with respect to the surface of the semiconductor material and have a high temperature coefficient synchronization, e.g. within a tolerance range of 10%, 5% or less (+/−10%, +/−5% or less). 
     In accordance with embodiments, a plurality of the sensor elements comprise L-shaped sensor elements and are spatially distributed across the surface of the semiconductor substrate. 
     In accordance with embodiments, the L-shaped sensor elements are piezo-sensitive diffusion resistors, e.g. having resulting stress coefficients which are independent of the direction of the influencing stress or strain in the semiconductor substrate. 
     In accordance with embodiments, the plurality of piezo-sensitive sensor elements comprises a first number of piezo-sensitive sensor elements having a first stress coefficient and comprises a second number of piezo-sensitive sensor elements having a second stress coefficient, wherein the first and second stress coefficients are different. 
     In accordance with embodiments, the first number of piezo-sensitive sensor elements provides a first stress dependent sensor signal having a first stress component dependency and the second number of piezo-sensitive sensor elements providing a second stress dependent sensor output signal having a second stress component dependency, wherein the first stress dependent signal has a stress component dependency with respect to the sum of the normal stress components (σ xx +σ yy ) in the semiconductor substrate, and wherein the second number of piezo-sensitive sensor elements provide a second stress dependent signal with a stress component dependency with respect to the difference of the normal stress components (σ xx −σ yy ) in the semiconductor substrate. 
     In accordance with embodiments, the stress compensated oscillator circuitry further comprises a temperature sensor element on or in the semiconductor substrate for providing a temperature sensor signal with respect to the instantaneous temperature of the semiconductor substrate. 
     In accordance with embodiments, the temperature sensor arrangement comprises a plurality of temperature sensor elements which are spatially distributed over the surface of the semiconductor substrate. 
     In accordance with embodiments, the plurality of temperature sensor elements form a differential temperature sensor arrangement. 
     In accordance with embodiments, the processing arrangement is configured to perform a feed-forward sensor output signal processing, i.e. without a feedback loop, for providing the control signal as stress compensation signal to the oscillator arrangement. 
     In accordance with embodiments, the processing arrangement is configured to retrieve a look-up table or to calculate a polynomial function based on the sensor output signal in order to determine the control signal. 
     In accordance with embodiments, the processing arrangement is configured to process the sensor output signal in order to provide the control signal which is a combination of a plurality of partial control signals, wherein each partial control signal controls the oscillator frequency of the oscillator output signal and reduces the influence of a different instantaneous component in the semiconductor substrate onto the oscillator frequency of the oscillator output signal. 
     In accordance with embodiments, the processing arrangement processes the first and second stress dependent sensor signal for providing a first and second (partial) control signal (separating X- and Y-stress dependencies of the oscillator) wherein the first control signal is processed to reduce X-stress dependencies of the oscillator arrangement, wherein the second control signal is processed to reduce Y-stress dependencies of the oscillator arrangement. 
     In accordance with embodiments, the processing arrangement is configured to process the sensor output signal in order to provide the control signal, wherein the control signal comprises a first (x-control signal) and a second (y-control signal) partial control signal to provide a first and a second (different) partial correction signal for different stress component dependencies of the oscillator arrangement in the semiconductor substrate. 
     In accordance with embodiments, the processing arrangement is configured to process the sensor output signals from the plurality of temperature sensor elements for determining a temperature dependent stress effect induced to a temperature gradient in the semiconductor substrate, and to provide the control signal which reduces the influence of the instantaneous temperature or temperature gradient in the semiconductor material onto the oscillator frequency of the oscillator output signal so that thermal-gradient-induced stress effects to the oscillator frequency of the oscillator output signal are reduced or compensated. 
     In accordance with embodiments, the oscillator arrangement comprises an oscillator in a fractional PLL loop, wherein the fractional PLL loop has a (e.g. digital) fractional divider, wherein the processing arrangement is configured to process the sensor output signal and to provide the control signal, wherein the control signal controls the fractional divider of the fractional PLL loop of the oscillator arrangement in order to reduce the influence of the instantaneous stress component in the semiconductor substrate on the oscillator frequency of the oscillator output signal. 
     In accordance with embodiments, the oscillator arrangement comprises a directly stress compensated LC oscillator or a stress compensated oscillator with a correction DAC for bias current, switchable capacitances and/or voltage-dependent capacitances. 
     In accordance with embodiments, the oscillator arrangement comprises a relaxation oscillator with a stress-compensated integrator current or stress-compensated reference voltages or stress-compensated integrated capacitances. 
     In accordance with embodiments, the processing arrangement is configured to provide a plurality of partial control signals to adjust a combination of at least two the following electrical characteristics, the electrical characteristics comprise the integrator current, the reference voltages and/or the integrator capacitances, in order to reduce the influence of the instantaneous stress component in the semiconductor substrate onto the oscillator frequency of the oscillator output signal. 
     In accordance with embodiments, an integrated circuit comprises the stress compensated oscillator circuitry, and a processing circuitry for performing a processing operation based on or using the stress compensated oscillator output signal provided by the stress-compensated oscillator circuitry. 
     In accordance with embodiments, the stress compensated oscillator circuitry and the processing circuitry are integrated on the same semiconductor substrate. 
     In accordance with embodiments, the processing arrangement of the stress compensated oscillator circuitry and the processing circuitry commonly share or double use integrated hardware on the semiconductor substrate. 
     In accordance with embodiments, the processing arrangement of the stress compensated oscillator circuitry and the processing circuitry commonly use ADCs temperature sensors, voltage references, voltage supplies and bias current supplies with defined temperature coefficients on the same semiconductor substrate. 
     Embodiments of the invention are advantageous as they provide a stress compensated oscillator circuitry for providing a (stress compensated) oscillator output signal f osc  with high precision and lifetime stability combined with very low temperature drift and low power or phase noise. Thus, according to embodiments of the invention, accurate and inexpensive, low power noise or low phase noise on-chip oscillators without external components are realizable and feasible for a large variety of different integrated circuits with digital protocols or RF interfaces. In accordance with embodiments, a very high accuracy and stability over lifetime and temperature range can be achieved even without trimming on wafer. 
     Based on the inventive concept, it is now possible to replace crystal oscillators so that additional pins and expensive external components can be avoided. 
     Moreover, according to the inventive concept, the trimming on wafer with predetermined frequency shift to compensate package effects can be avoided. According to the inventive concept, not only systematic changes can be compensated, but also a not statistical spread of frequency shift can be considered. Moreover, unpredictable lifetime shifts can be pre-compensated. 
     Further, embodiments are advantageous as they provide a possible synchronization to external clock signals without the requirement of using extra pins or synchronization overhead and without the requirement of an additional PLL circuit. 
     Further, embodiments are advantageous as they provide an automated stress compensated oscillator circuitry concept when compared to MEMS oscillators, which still require a separated die on top of a microprocessor chip with expensive technology and which are not so accurate as crystal oscillators and are difficult to stabilize. 
     In accordance with embodiments, the processing arrangement  200  of the stress compensated oscillator circuitry  10  processes the sensor output signal from the sensor arrangement  100  and determines a control signal or a plurality of partial control signals (components) for stress compensation of the oscillator output signal. The control signal (stress dependent influence signal) does not necessarily need a memory for storing comparison values. 
     In accordance with embodiments, a combination of frequency determining components with different stress components is performed so that the different stress components cancel. For example, a first resistive element (arrangement like L-shape) with positive stress coefficient (i.e. a lateral n diffusion) and a second resistive element (arrangement like L-shape) with negative stress coefficient (e.g. a vertical n diffusion) is used for the sensor elements of the sensor arrangement  100 . 
     In accordance with embodiments, a stress sensor (the stress sensor arrangement  100  with a plurality of sensor elements) is used, wherein the resulting stress signals (sensor output signals as sensor) “correlate” to the undesired influence parameter of the oscillator circuitry and the stress signals are used for stress compensation, i.e. are used by the processing arrangement  200  for determining the control signal s control . For example, the stress sensor provides a (σ xx +σ yy ) stress dependent signal (dependent on an addition of the normal stress components) and a (σ xx −σ yy ) stress dependent signal (dependent on a difference of the normal stress components) to determine different correction signals (different control signals s control ) for the x- and y-direction in the semiconductor substrate (the sensor die). In this connection it is pointed to the fact that, a long resistor parallel to a trench has another stress influence than particular to this trench. 
     In accordance with embodiments, a stress compensated RC relaxation oscillator is used which controls an LC oscillator in a (fractional) PLL loop. 
     In accordance with embodiments, a differential temperature sensor is used to determine stress effects especially in LC oscillators (in addition to stress compensation or alone) in order to compensate thermal-gradient-induced stress effects. 
       FIG. 3  shows a schematic block diagram of an integrated circuit  30  comprising the stress compensated oscillator circuitry  10  of  FIG. 1  and a processing circuitry  40  for performing a processing operation based on or using the stress compensated oscillator signal S osc  provided by the stress compensated oscillator circuitry  10 . 
     In accordance with embodiments, the stress compensated oscillator circuitry  10  and the processing circuitry  40  can be integrated on the same semiconductor substrate  20 . 
     In accordance with embodiments, the processing arrangement  200  of the stress compensated oscillator circuitry  10  and the processing circuitry  40  commonly share or double use integrated hardware elements  40   a  on the semiconductor structure. The commonly shared integrated hardware is indicated in  FIG. 3  by the dashed region  40   a , i.e. the overlapping area of the stress compensated oscillator circuitry  10  and the processing circuitry  40  of the integrated circuit  30 . 
     In accordance with embodiments, the processing arrangement  200  of the stress compensated oscillator circuit  310  and the processing circuitry  40  commonly use, for example, ADCs, temperature sensors, voltage references, voltage supplies and/or bias current supplies with defined temperature coefficients on the same semiconductor substrate  20  as the commonly shared integrated hardware  40   a.    
     The processing circuitry  40  may comprise or may be implemented as a microprocessor or a RF chip (i.e. a circuitry for processing or providing an RF signal). Thus, the processing circuitry  40  may be implemented as a dedicated signal processing circuit. 
     In accordance with embodiments, the integrated circuit  30  comprises the stress compensated oscillator circuitry  10  and a processing circuitry  40  for performing a processing operation based on the stress compensated oscillator output signal provided by the stress compensated oscillator circuitry  10 . 
     Generally, the stress compensated oscillator circuitry can be regarded as a general electronic circuitry for providing a “constant” (e.g. self-generated) output signal, i.e. in contrast to a sensor arrangement for detecting an environmental variable, e.g. an external magnetic field or temperature dependent signal or voltage dependent signal. Thus, the inventive concept can be also applied to any circuitries, such as to voltage, current resistor or capacitor references, which should have no cross sensitivities to other physical or aging effects. 
     In accordance with embodiments, the integrated circuit  30  can be a monolithically integrated overall system with an on-chip oscillator, e.g. with microprocessor, storage elements, sensor ICs with on-chip signal processor, RF signal processing chip (e.g. WLAN), transceiver chip, etc. 
     Embodiments of the invention are advantageous as they provide substantial additional functions or main functions than compared to a pure oscillator chip. Moreover, the integrated circuit  30  allows a double usage of the further integrated hardware, e.g. ADCs, temperature sensors, voltage references, voltage supplies and/or the provision of bias currents with defined temperature coefficients, etc., on the semiconductor chip by means of the stress compensated oscillator circuitry  10 . 
     Embodiments of the invention are advantageous as they provide an integrated circuit  30  which requires less area, less interconnects and less chips in the package than previously known approaches. 
     The integrated circuit  30  allows a common adjustment during chip production so that associated adjustment efforts are reduced. The integrated circuit  30  has a reduced power consumption by omission of otherwise necessitated interconnect drivers. The integrated circuit  30  allows to control the switching on and off of an oscillator  10  by means of a microprocessor or WLAN chip to save energy in idle breaks and to allow fast wakeup behavior which would otherwise require additional pins (interconnects) and hardware. In accordance with embodiments, the integrated circuit  30  provides an extensive temperature measurement on a microprocessor chip, wherein the extensive Flash or EEPROM storage options and the extensive options of the software or existing hardware allow for the provision of very complex and extensive compensation algorithms. 
       FIG. 4  shows a schematic diagram of stress measurements (on an exemplary low-power R-C-relaxation oscillator) showing a typical drift behavior of the oscillator frequency of the oscillator output signal versus the instantaneous stress or strain components in the semiconductor substrate. The drift of the oscillator output signal is indicated with different instantaneous in-plane stress of strain components in the x-direction (resulting in the x-drift) and the y-direction (resulting in the y-drift) in the semiconductor substrate. 
     As shown by the measurement values of  FIG. 4 , the different dependencies of a (relaxation) oscillator exist with respect to the x- and y-direction of the applied stress (e.g. in a bending experiment). Thus, the diagram of  FIG. 4  shows the meaningfulness and relevance of a stress correction or stress compensation which is different in x- and y-directions, for example the relevance of determining different piezo-stress components in the x- and the y-direction in the semiconductor substrate  20 . 
     Such effects as indicated in  FIG. 4 , i.e. different stress dependencies in the x- and y-direction of the circuitry, occur due to the fact that resistors and/or transistors or other electrical or electronic elements have a different position of respect to the edge of the semiconductor substrate (IC) or have a different position with respect to adjacent insulating trenches. These effects will still be thoroughly described in the following, e.g. with respect to  FIGS. 5 a - c , 6 a - b  and 11 a   - b.    
       FIGS. 5 a - c    show a further embodiment of the sensor arrangement  100  of the stress compensated oscillator circuitry  10 . To be more specific,  FIGS. 5 a  and 5 b    each shows a schematic block diagram of different, exemplary sensor elements  110 ,  120  and  130  for different implementations of the sensor arrangement  100  in accordance with embodiments of the present invention. 
     As indicated in  FIGS. 5 a  and 5 b   , the first L-shaped resistor  110  comprises a first and second resistor element  110 - 1 ,  110 - 2  (arranged +/−45° in  FIG. 5 a    and 0°/90° in  FIG. 5 b   ), the second L-shaped resistor  120  comprises a first and a second resistor element  120 - 1 ,  120 - 2 , and the third resistor comprises a first and a second resistor element  130 - 1 ,  130 - 2 . Each of the resistors are preferably connected between a supply signal source  140  and a ground contact. The sensor output signal S sensor  is provided by a read-out circuit  150  in the form of a σ/T-ADC-circuit which is provided by a reference voltage v ref . A σ/T-ADC-circuit can measure stress components (i.e. σ xx +σ yy  and σ xx −σ yy  and temperature T) in a multiplexed sequence. The adjustment of the oscillator frequency and the stress and temperature sensors can be made preferably at only one temperature measurement (single temperature trim point). 
     As indicated in  FIGS. 5 a  and 5 b   , the read-out circuit  150  is, in accordance with different interconnecting options, connectable to the first, second and/or third resistor  110 ,  120  and  130 . The different configurations for reading out the first, second and third L-shaped resistors are indicated in detail below. 
     The first and second resistor  110  and  120  are so-called L-resistors of two resistor elements of equal size which are arranged such that they are perpendicular to one another and lie “directly” adjacently to one another in/on the semiconductor substrate  20 . Moreover, the two orthogonally arranged resistor elements are electrically connected in parallel (elements  110 - 1  and  110 - 2 ) or in series (elements  120 - 1 ,  120 - 2 ) or the resistor elements are connected to a multiplexer, that allows the measurement of resistor elements in a sequential way. 
     As indicated in  FIG. 5 c   , the left resistor element shows a possible realization of the resistor elements  110 - 1 ,  110 - 2 ,  120 - 1 ,  120 - 2  of the L-shaped resistors  110  or  120 . As shown in the left drawing of  FIG. 5 c   , the resistor element is indicated as resistor element R lv,n . The index n (=n diffusion) indicates that the resistor element is a resistive element in a n-doped resistive region (n-epi or n-well) in a semiconductor substrate between two contact structures “n-contacts”. Moreover, the indices “lv” indicate that the current flow between the two contact regions have a lateral portion and a vertical portion. 
     As indicated in  FIG. 5 c   , the right resistor element indicates a possible implementation of the resistor elements  130 - 1 ,  130 - 2  of the third resistor  130 . As shown with respect to the resistor element R v,n , this resistor element also is an n-diffusion resistor element, however, only with vertical current directions from the n-contacts through the n-epi-layer or n-well to the n-buried layer with negligible lateral series resistance. 
     In  FIGS. 5 a  and 5 b   , the dependencies of the resulting resistance from the stress or strain component in the semiconductor substrate are indicated. As shown in  FIG. 5 a   , it is indicated that the first L-resistor  110  is angularly offset by 45° with respect to the second L-resistor  120 . As shown in  FIG. 5 b   , it is indicated that the first L-resistor  110  is angularly offset by 90° with respect to the second L-resistor  120 . 
     As indicated in  FIG. 5 a   , the left 45°-L-resistor  110  (comprising the resistor elements  110 - 1  and  110 - 2 ) provides a stress-dependent output voltage having a (σ XY ) shear stress sensitivity E 1  with E 1 =1+155.6% GPa (σ XY ). As indicated in  FIG. 5 b   , the left 0°/90°-L-resistor  110  (comprising the resistor elements  110 - 1  and  110 - 2 ) provides a stress-dependent output voltage having a (σ XX −σ YY ) sensitivity E 1  with E 1 =1+6.8% GPa (σ XX −σ YY ). Thus, the L-resistor  110  provides a stress dependent output signal which depends on the difference between the normal stress components σ XX , σ YY  in the semiconductor substrate and σ=σ XX −σ YY . 
     Moreover, as indicated as a further option in  FIGS. 5 a  and 5 b   , the signal difference (voltage difference) between the second L-resistor  120  and the vertical resistor  130  provides a stress dependent voltage having a (σ XX +σ YY ) sensitivity E 2 , with E 2 =1+(43.2−22.5)%/GPa. Thus, the combination of the second and third resistors  120 ,  130  is sensitive with respect to the sum of the normal stress components and σ XX +σ YY . 
       FIGS. 6 a - b    show a schematic illustration (as top view and as a cross-sectional view) of the influence of a deep trench arranged near to exemplary circuit elements (which determine the oscillator frequency) onto the different stress components acting to the circuit elements and onto the different piezo coefficients of the circuits elements in accordance with embodiments. Exemplary circuit elements are, for example, stress sensor elements, resistive elements of a RC-relaxation oscillator and/or transistor elements for a current mirror circuit (which provide the bias current for the LC oscillators) etc. 
       FIG. 6 a    provides an exemplary layout arrangement (top view) of resistors (n-MOS or poly), transistors (not shown) and insulating trenches  114 . The insulating trenches (deep or shallow trench)  114  have a very different elastic modulus with respect to the silicon material of the substrate  20 . Thus, the isolating trench  114  generates different stress variations, even with homogenous y-in plane-stress. This is indicated by the different stress components σ YY  and σ XX . As indicated, the locally generated stress σ XX , σ YY  can be different with regards to size and direction. 
     Additionally, there are further circuit elements (resistors, transistors (not shown in  FIG. 6 a   ), etc.), which are laid out in a specific direction and hence also show different reactions to x- and y-stress or strain. Thus, the position of these circuit elements (not shown in  FIG. 6 a   ) with respect to the trenches or to the chip edges is relevant and should be considered when processing and determining the control signal by means of the processing arrangement  200 . In this connection, it is further pointed to out to the explanations with respect to  FIG. 4 . 
       FIG. 6 b    shows a schematic illustration (as a cross-sectional view) of the influence of a deep trench arranged near exemplary circuit elements or sensor elements to the different stress components acting to the circuit elements or sensor elements, and onto the different piezo coefficients of the circuit elements or sensor elements in accordance with the invention. 
       FIG. 6 b    shows exemplary circuit elements in form of n-channel transistors  116  within a n-epi-region  116   a  of semiconductor substrate  116   b . The FETs  116  are separated from neighboring circuit elements (not shown in  FIG. 6 b   ) by means of deep trenches  116   c . The metallization layers  118  (Met 1 , Met 2 ) provide the electrical interconnection to further circuit elements (not shown in  FIG. 6 b   ). 
     As indicated in  FIG. 6 b   , in deep regions of the semiconductor substrate, stress components (deep stress) can occur in the circuit element. The transistors or resistors on the surface are influenced by this local stress effects. I.e. the mobility of a n-channel transistor between the n-diffusion source and drain contacts is influenced by stress. 
     In accordance with embodiments, the following considerations are based on the explanations with respect to  FIGS. 5 a - c  and 6 a - b    and provide further information for providing an improved stress sensor arrangement  100  for the stress compensated oscillator circuitry  10 . 
     In the following, two considerations can be combined in accordance with embodiments.
     1.) Any combinations of the stress components σ XX  and σ YY  can be obtained based on two signals, namely the signal Sp˜σ XX +σ YY  and the signal Sm˜σ XY  ( FIG. 5 a   ) or Sm˜σ XX −σ YY  ( FIG. 5 b   ).   2.) Stress sensors for Sp and Sm can measure the two combinations of stress sensor components Sp˜σ XX +σ YY  and Sm˜σ XX −σ YY  with high sensitivity as well as minor errors due to temperature variations and manufacturing tolerances.   

     Stress sensors for Sp can be taken from examples e.g. described above. For this, either two differently doped resistive elements can be compared (e.g. an n-doped to a p-doped resistor or an NMOS to a PMOS or a low-doped n-resistor to a high-doped n-resistor). Alternatively, lateral and vertical resistive elements with different piezo stress dependencies can be compared to one another, wherein the first have current flow mainly in lateral direction (parallel to the chip surface) and the latter have current flow mainly in the direction vertical to the chip surface). The advantage of the last solution is better temperature difference and lower technology spread. 
     When then the mechanical tension or stress changes, the ratio between the resistors changes, or for example, the conductivity of MOS transistors or the VBE or beta of bipolar transistors (all piezo-effects). 
     By rotating the rectangular arrangement of resistors or MOS transistors by 45° in the layout, σ XY  can be measured instead of σ XX −σ YY , wherein, with p-doped elements, a higher sensitivity results for σ XY  and with n-doped elements a higher sensitivity for σ XX −σ YY . 
     The combination means for Sp and Sm can be a linear combination, e.g. k1*Sp+k2*Sm with any coefficients k1, k2, in particular, k1=1 and k2=1 or k2=−1. Nonlinear combinations are also possible, such as k1*Sp^e1+k2*Sp^e2 or (k1*Sp+k2*Sm) ^e1 with the real valued exponents e1 and e2. 
     Thereby, stress sensitivities can be corrected differently in X-direction than in Y-direction. This is, for example, necessitated for different adjacent layouts, e.g. trenches or different distances to the chip edges. 
       FIG. 7  shows a schematic illustration of a sensor arrangement  100  in the form of stress sensitive current mirror circuit in accordance with embodiments. The stress sensitive current mirror circuit comprises the MOSFETs  119   a ,  119   b  which are arranged in the semiconductor substrate in a +/−45° L-shaped layout so that the resulting current through the first FET  119   a  flows along the [010] direction (see  FIG. 2 a   ) and the resulting current through the second FET  119   b  flows along the [100] direction (see  FIG. 2 a   ). 
     Based on this circuit configuration of the FETs  119   a ,  119   b , the resulting stress components σ XY  can be measured via the ratio of the currents Tout to Tin for n-Mos transistors in  FIG. 7 . 
     If, alternatively, a 0°/90° L-shaped layout of the n-MOS transistors (not shown in  FIG. 7 ) would be used instead of the +/−45° layout (as shown in  FIG. 7 ) the resulting stress component σ XX −σ YY  can be measured via the ratio of the currents Iout to Iin. 
       FIG. 8 a    shows a schematic block diagram of a stress compensated oscillator circuitry  11  according to embodiments, wherein the oscillator arrangement  300  comprises a PLL oscillator  320  with stress compensation via digital fractional values.  FIG. 8 b    shows a schematic block diagram of an exemplary fractional PLL  320  (PLL=Phase Locked Loop) in accordance with embodiments. 
     As shown in  FIG. 8 a   , the sensor arrangement  100  comprises a stress sensor  102  and optionally a temperature sensor  104 . The sensor output signal as sensor is provided to the processing arrangement  200 , wherein the processing arrangement  200  comprises a multiplexer  210 , an LP-ADC  220  (Low Power-Analog/Digital-Converter), and a circuit  230  for querying a table, e.g. a look-up table, or for calculating a polynomial function (i.e. the terms of the polynomial function or a piecewise linear function or any other mathematical function). These function can include temperature dependent coefficients. 
     The processing circuit  200  provides as output signal the control signal s control  to the oscillator arrangement  300 . The oscillator arrangement  300  comprises a precision relaxation oscillator  310 , a fractional PLL oscillator  320  for providing the compensated oscillator output signal s osc  and, optionally, a programmable counter or divider circuit  330 . 
       FIG. 8 b    shows an example for a fractional PLL circuit. As shown in  FIG. 8 b   , the fractional PLL oscillator  320  comprises as reference source s ref , e.g. in form of a precision relaxation oscillator  310 . The fractional PLL oscillator  320  comprises a phase detector PFD  321 , a filter circuit  322 , and voltage control oscillator  323 , and in a feedback loop a fixed  1 /A divider circuit  324  and a fractional  1 /N divider circuit  325 . 
     The phase detector  321  compares its two input signals and produces an error signal which is proportional to their phase difference. The error signal is then low pass filtered in the circuit  322  and is used to drive the voltage controlled oscillator VCO  323 , which creates an output phase. The output signal is fed through a divider (fixed divider circuit  324  and fractional divider circuit  325 ) back to the input of the system, producing a negative feedback loop. The fractional divider circuit  325  is configured to provide a non-integer multiple of the reference frequency in accordance with the following relation of the digital fractional divider:
 
 f   osc   =A *( N+k/M )* f   ref ,
 
wherein the term k/M depends on the control signal s control .
 
     The fractional divider circuit can also be combined with a pseudo-random or sigma delta modulation in order to lower noise at the oscillator output signal s osc . The oscillator output signal has low phase noise and is temperature and stress compensated at the same time. 
     In the following, the functionality of the stress compensated oscillator circuitry  100  as illustrated in  FIGS. 8 a - b    is explained in detail in accordance with embodiments. 
     The stress sensors  102  and (optionally) temperature sensors  104  are queried from time to time via the multiplexer  210  with low-power ADC  220 , e.g. every 0.5 . . . 2 ms for being able to follow thermal transient times, or even several seconds when the IC has been in a sleep mode. The digital result influences the digital divider  325  of the fractional PLL  320  via a lookup table or a calculating unit  23  which calculates a digital dividing ratio (N+k/M), with the help of polynomial calculations (e.g. 1 st  and 2 nd  order). 
     The stress-dependent dividing ratio can be superposed to a different dividing ratio for fine tuning the output frequency (not shown in the figure). 
     The high (but fine-tuned and stress-compensated) output frequency f osc  in the fractional PLL  320  can, for example, be generated by an LC oscillator (e.g. 2.4 GHz), which is initially not very exact. The exact (but still to be stress-compensated) precision relaxation oscillator  310  provides a reference signal S ref  with f ref  (for example 100 kHz), by which the fractionally divided oscillator frequency f osc  of the output is divided down. 
     By fractional division (e.g. dividing ratio varies intermittently from 1/N to 1/(NA/M), e.g. ¼ to ⅕) very fine-tuned output frequencies can be set and hence very fine-tuned temperature and stress compensations and fine-tuned oscillator frequency can be performed. 
     The advantage is that the precision relaxation oscillator shows very good basic accuracy, but provides only a fixed frequency, while the output signal can be very fine-tuned and shows low phase noise. 
     Additionally, the fractional dividing ratio can be distributed in time by sigma-delta methods, such that the same can be easily filtered to provide low-noise output frequency. 
     By dividing down this output frequency, very exact time bases can also be provided for other applications (shown in dashed lines). For example, for specific protocol requirements or for sensors having a time base as a reference. 
     Polynomials can be formed, for example, with:
 
 D out1 =D out1ref+(α 1   ΔT+β   1   ΔT ) with
 
Δ T=T−T ref
 
T measured temperature
 
Tref reference or adjustment temperature
 
Dout1 digital polynomial partial result
 
Dout1ref digital reference value
 
 D out2= D out2ref+(α 2 Δσ xx +β 2 Δσ xx ) with
 
Δσ=σ xx −σ xxref  
 
σ xx  measured piezo effect in X-direction to the crystal direction of the wafer die
 
σ xxref  stress measurement at the reference time
 
Dout2 digital polynomial partial result
 
Dout2ref digital reference value
 
 D out3 =D out3ref+(α 3 Δσ yy +β 3 Δσ yy ) with
 
Δσ=σ yy −σ yyref  
 
σ yy  measured piezo effect in X-direction to the crystal direction of the wafer die
 
σ yyref  stress measurement at the reference time
 
Dout2 digital polynomial partial result
 
Dout2ref digital reference value
 
σ xx  and σ yy  can be calculated from the favored piezo component sensors providing, for example, σ xx +σ yy  or σ xx −σ yy  
 
     As shown in  FIG. 8 b   , the control signal provided by the processing arrangement  200  controls the fractional divider circuit  325  of the fractional PLL oscillator  320 . 
       FIG. 9  shows a schematic block diagram of a stress compensated oscillator circuitry  12  according to another embodiment, wherein the stress compensated oscillator circuitry  12  comprises a directly stress compensated LC oscillator  340 . 
     As shown in  FIG. 9 , the stress compensated oscillator circuitry  10  comprises a sensor arrangement  100  with a stress sensor circuit  102  and an optional temperature sensor circuit  104 . The processing arrangement  200  comprises a multiplexer circuit  210 , an LP-ADC-circuit  220  and a circuit  230  for querying a LUT (look-up table) or for calculating a polynomial function (i.e. the terms of the polynomial function) and a DAC-circuit  240  (DAC=Digital/Analog Converter)  240 . 
     The oscillator arrangement  300  comprises an LC-oscillator  340  for providing the oscillator output signal s osc  having the oscillator output frequency f osc . 
     The oscillator  340  may be an LC oscillator, but the use of a relaxation oscillator or a ring oscillator is also possible, which is provided on the chip  20  and is corrected directly via DAC  240  from the AD-converted stress and/or temperature signal s sensor . For this, the digital stress and temperature signals are read out again via a lookup table or subject to polynomial calculation by means of the circuit  230 . Usually a polynomial calculation requires much less EEPROM memory bits and less reference points. 
     In this connection, it pointed out that an analog compensation of temperature sensors directly on the oscillator would also be possible, but more complex compensations and higher order compensations and cross couplings between the sensors and to the oscillator may impede the adjustment. The piezo stress components themselves, for example, are temperature-dependent. Analog replica circuits translating a stress voltage to an oscillator frequency may have themselves inaccuracies which can also be temperature and stress-dependent (e.g. the offset of an OPV (op-amp) in an analog replica circuit). Above that, fine-tuning of analog elements may be difficult to perform. 
       FIG. 10 a    shows a stress compensated oscillator circuitry  13 , wherein the sensor arrangement  100  comprises a stress sensor for providing the sensor output signal s sensor  to the processing arrangement  200 . The processing arrangement  200  comprises an ADC-circuit  210 , a circuit for querying a look-up table or for calculating a polynomial function (i.e. the terms of the polynomial function)  230  and a digital correction DAC-circuit  250  for providing the control signal s control . 
     The oscillator arrangement  300  may comprise a relaxation oscillator  360  with voltage references VH, VL provided by voltage reference provider  362  for the comparator  364 . Switchable up and down integrator currents  366 - 1 ,  366 - 2 , the two-threshold comparator  364  and the control signal s control , e.g. a stress and optionally temperature-dependent DAC compensation signal. As shown in  FIG. 10 a   , the integrated current  366 - 1 ,  366 - 2  is tuned. 
     As shown in  FIG. 10 a   , the control signal s control  output by the DAC  240  can switch the integrator currents  366 - 1 ,  366 - 2 . Alternatively or additionally the DAC  240  can also change voltage references (e.g. DAC with voltage output) or switch capacitance fields (C-array, C-DAC). Thus,  FIG. 10 a    shows a stress compensated oscillator with correction DAC for the integrator current. 
       FIG. 10 b    shows a further embodiment of the stress compensated oscillator circuitry of the invention, similar to the one of  FIG. 10 a   .  FIG. 10 b    shows a stress compensated oscillator circuitry  14 , wherein the sensor arrangement  100  comprises a stress sensor for providing the sensor output signal s sensor  to the processing arrangement  200 . The processing arrangement  200  processes the sensor output signal s sensor  and provides an “analog” control signal s control . The oscillator arrangement  300  may comprise a relaxation oscillator  360  with voltage references VH, VL provided by voltage reference provider  362  for the comparator  364 , and the integrator currents  366 - 1 ,  366 - 2 . 
     As shown in  FIG. 10 b   , the it is indicated in a relaxation oscillator  360  that the integration currents can also be stress-compensated in an analog manner. As mentioned: the actual implementation may be more difficult and less exact, but more area-efficient. The sub-currents can be generated by mixing currents having different stress dependencies. This is indicated in the formulas below. Thus,  FIG. 10 b    shows a relaxation oscillator with stress compensated integrator current by using combination of devices with different stress components 
     Example for weighted bias current generation to compensate stress effects in circuits (for +/−45° resistor elements, such as shown in  FIG. 5 a   ): 
     
       
         
           
             
               I 
               
                 
                   bias 
                   ⁢ 
                   _ 
                   ⁢ 
                   stresscomp 
                 
                 ⁢ 
                 
                   ( 
                   
                     x 
                     + 
                     y 
                   
                   ) 
                 
               
             
             = 
             
               
                 
                   V 
                   
                     replica 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     1 
                     ⁢ 
                     
                       _ 
                       ⁢ 
                       bandgap 
                     
                   
                 
                 
                   ( 
                   
                     
                       
                         R 
                         
                           lv 
                           , 
                           n 
                         
                       
                       ⁡ 
                       
                         ( 
                         
                           σ 
                           , 
                           T 
                         
                         ) 
                       
                     
                     + 
                     
                       
                         k 
                         1 
                       
                       · 
                       
                         
                           R 
                           
                             v 
                             , 
                             n 
                           
                         
                         ⁡ 
                         
                           ( 
                           
                             σ 
                             , 
                             T 
                           
                           ) 
                         
                       
                     
                   
                 
               
               ~ 
               
                 1 
                 
                   1 
                   + 
                   
                     ( 
                     
                       22.5 
                       ⁢ 
                       
                         % 
                         / 
                         GPa 
                       
                     
                     ) 
                   
                   + 
                   
                     
                       k 
                       1 
                     
                     · 
                     
                       ( 
                       
                         43.2 
                         ⁢ 
                         
                           % 
                           / 
                           GPa 
                         
                       
                       ) 
                     
                   
                 
               
             
           
         
       
       
         
           
             
               I 
               
                 
                   bias 
                   ⁢ 
                   _ 
                   ⁢ 
                   stresscomp 
                 
                 ⁢ 
                 
                   ( 
                   xy 
                   ) 
                 
               
             
             = 
             
               
                 
                   
                     k 
                     2 
                   
                   · 
                   
                     V 
                     
                       replica 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       2 
                       ⁢ 
                       
                         _ 
                         ⁢ 
                         bandgap 
                       
                     
                   
                 
                 
                   ( 
                   
                     
                       
                         R 
                         
                           lv 
                           , 
                           
                             n 
                             
                               
                                 + 
                                 45 
                               
                               ⁢ 
                               ° 
                             
                           
                         
                       
                       ⁡ 
                       
                         ( 
                         
                           σ 
                           , 
                           T 
                         
                         ) 
                       
                     
                     + 
                     
                       
                         R 
                         
                           vl 
                           , 
                           
                             n 
                             - 
                             
                               45 
                               ⁢ 
                               ° 
                             
                           
                         
                       
                       ⁡ 
                       
                         ( 
                         
                           σ 
                           , 
                           T 
                         
                         ) 
                       
                     
                   
                 
               
               ~ 
               
                 
                   k 
                   2 
                 
                 
                   1 
                   + 
                   
                     ( 
                     
                       155.6 
                       ⁢ 
                       
                         % 
                         / 
                         GPa 
                       
                     
                     ) 
                   
                 
               
             
           
         
       
     
     Example for weighted bias current generation to compensate stress effects in circuits (for 0°/90° resistor elements, such as shown in  FIG. 5 b   ): 
     
       
         
           
             
               I 
               
                 
                   bias 
                   ⁢ 
                   _ 
                   ⁢ 
                   stresscomp 
                 
                 ⁢ 
                 
                   ( 
                   
                     x 
                     + 
                     y 
                   
                   ) 
                 
               
             
             = 
             
               
                 
                   V 
                   
                     replica 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     1 
                     ⁢ 
                     
                       _ 
                       ⁢ 
                       bandgap 
                     
                   
                 
                 
                   ( 
                   
                     
                       
                         R 
                         
                           lv 
                           , 
                           n 
                         
                       
                       ⁡ 
                       
                         ( 
                         
                           σ 
                           , 
                           T 
                         
                         ) 
                       
                     
                     + 
                     
                       
                         k 
                         1 
                       
                       · 
                       
                         
                           R 
                           
                             v 
                             , 
                             n 
                           
                         
                         ⁡ 
                         
                           ( 
                           
                             σ 
                             , 
                             T 
                           
                           ) 
                         
                       
                     
                   
                 
               
               ~ 
               
                 1 
                 
                   1 
                   + 
                   
                     ( 
                     
                       22.5 
                       ⁢ 
                       
                         % 
                         / 
                         GPa 
                       
                     
                     ) 
                   
                   + 
                   
                     
                       k 
                       1 
                     
                     · 
                     
                       ( 
                       
                         43.2 
                         ⁢ 
                         
                           % 
                           / 
                           GPa 
                         
                       
                       ) 
                     
                   
                 
               
             
           
         
       
       
         
           
             
               I 
               
                 
                   bias 
                   ⁢ 
                   _ 
                   ⁢ 
                   stresscomp 
                 
                 ⁢ 
                 
                   ( 
                   
                     x 
                     - 
                     y 
                   
                   ) 
                 
               
             
             = 
             
               
                 
                   
                     k 
                     2 
                   
                   · 
                   
                     V 
                     
                       replica 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       2 
                       ⁢ 
                       
                         _ 
                         ⁢ 
                         bandgap 
                       
                     
                   
                 
                 
                   ( 
                   
                     
                       
                         R 
                         
                           lv 
                           , 
                           
                             n 
                             
                               0 
                               ⁢ 
                               ° 
                             
                           
                         
                       
                       ⁡ 
                       
                         ( 
                         
                           σ 
                           , 
                           T 
                         
                         ) 
                       
                     
                     + 
                     
                       
                         R 
                         
                           vl 
                           , 
                           
                             n 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             90 
                             ⁢ 
                             ° 
                           
                         
                       
                       ⁡ 
                       
                         ( 
                         
                           σ 
                           , 
                           T 
                         
                         ) 
                       
                     
                   
                 
               
               ~ 
               
                 
                   k 
                   2 
                 
                 
                   1 
                   + 
                   
                     ( 
                     
                       6.8 
                       ⁢ 
                       
                         % 
                         / 
                         GPa 
                       
                     
                     ) 
                   
                 
               
             
           
         
       
     
     Example 
     A relaxation-type oscillator  360  uses an integrating current lilt, two reference voltages VH=Vref+ and VL=Vref− and an integration capacitor C int . By up- and down-integrating the current I nt  on capacitor C int  until the reference voltages Vref+ or Vref− are reached, an output frequency f osc  is build. 
     
       
         
           
             
               f 
               osc 
             
             = 
             
               
                 I 
                 int 
               
               
                 2 
                 · 
                 
                   ( 
                   
                     
                       v 
                       
                         ref 
                         + 
                       
                     
                     - 
                     
                       V 
                       
                         ref 
                         - 
                       
                     
                   
                   ) 
                 
                 · 
                 
                   C 
                   int 
                 
               
             
           
         
       
       
         
           
             
               I 
               int 
             
             = 
             
               
                 I 
                 
                   int 
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   pstress 
                 
               
               ± 
               
                 I 
                 
                   int 
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   nstress 
                 
               
             
           
         
       
       
         
           
             
               I 
               
                 int 
                 ⁢ 
                 
                     
                 
                 ⁢ 
                 pstress 
               
             
             = 
             
               
                 f 
                 p 
               
               ⁡ 
               
                 ( 
                 σ 
                 ) 
               
             
           
         
       
       
         
           
             
               I 
               
                 int 
                 ⁢ 
                 
                     
                 
                 ⁢ 
                 nstress 
               
             
             = 
             
               
                 f 
                 n 
               
               ⁡ 
               
                 ( 
                 σ 
                 ) 
               
             
           
         
       
     
     The bandgap-based reference voltages Vref+ or Vref− are temperature-compensated and only a little bit stress-dependent (by small piezo-junction effects and small influence of piezo-resistance effect of used resistors, which changes the bias current and thus the Vbe=Vntat only by a logarithmic function from collector current to Vbe). The capacitor C int  is also nearly stress independent. The delay in the comparator  364  decreases a little bit to oscillator frequency f osc  and is a bit stress dependent, because the mobility in the differential input pair is a bit stress dependent by piezo-MOS effect=piezo-resistive effect in transistor channel. The main stress influence comes from the used bias resistors in the bandgap, which have a big piezo-resistive effect, and which are mirrored to the integration current I int . 
     A temperature compensation of integrating current Tint with low technology spread can be done by adding or subtracting currents coming from voltages used in a bandgap circuit with different temperature gradients (Vptat and Vntat). In both voltage branches resistors of the same resistor type are usually used to reject technology influencers to the TC (temperature coefficient) of I int . Finally I int  or C int  is trimmed to a desired f osc , but that can usually be done at only one temperature. 
     The resulting f osc  is mainly stress-dependent to 1/R with R=f(σ). Often used n-doped poly-resistors has a stress coefficient of −11%/GPa, which lead to about 3% frequency shift at 200 MPa in-plane stress in and around the middle of the chip by a normal packaging process and to about +/−0.7% instability by humidity changes and lifetime effects and soldering. 
     But in the near of trenches the stress can change in a different manner (values an X or X dependency), but still correlates with global stress. This can be compensated with a second constant current, which uses also bandgap-inherent voltages Vptat and Vntat to realize temperature compensation. For instance an L-shape p-doped resistor with +4.4%/GPa can be added in the same or a different bandgap circuit with a current ratio of about 4.4/11 compared to the n-poly-based current. The L-shape of diffused resistors is important to make the stress coefficient independent to the direction of stress. 
     The difference of the L-shaped arms can be used to separate X- and Y-stress dependencies of the oscillator. The resulting Tint can now designed to be nearly stress-compensated or the ratio between both resistor types can be now adjusted to compensate remaining stress effects in comparator delay or reference voltages or capacitor. For a first order compensation of stress and temperature it is enough to adjust it with a fixed ratio. 
       FIGS. 11 a  and 11 b    show a stress compensated oscillator circuitry  15  according to a further embodiment, in the form of an LC oscillator with stress sensors and differential temperature sensors, i.e. a stress measurement via a differential voltage measurement. In accordance with embodiments,  FIGS. 11 a  and 11 b    each shows a schematic illustration of a stress compensated oscillator circuitry  15  having, for example an LC oscillator  340 , with stress sensors  102 - 1  to  102 - 4  and differential temperature sensors  104 - 1  to  104 - 4  on the semiconductor substrate  20  in accordance with embodiments of the invention. 
     The L-shaped resistors  102 - 1 ,  102 - 3  (at +/−45° in  FIG. 11 a   ) provide together with vertical resistors  102 - 2 ,  102 - 4  compensation signal V 2  for the X- and Y-stress dependency:
 
 V   2   =f (σ xy )
 
     The L-shaped resistors  102 - 1 ,  102 - 3  (at 0°/90° in  FIG. 11 b   ) provide together with vertical resistors  102 - 2 ,  102 - 4  compensation signals V 1  and V 2  for the X- and Y-stress dependency:
 
 V   1   =f (σ xx +σ yy )
 
 V   2   =f (σ xx −σ yy )
 
 V   1   +V   2   =f (σ xx +σ yy +σ xx −σ yy )= f (σ xx )
 
 V   1   −V   2   =f (σ xx +σ yy −(σ xx −σ yy ))= f (σ yy )
 
     Thus different stress compensation signals for the X and Y direction are available to compensate stress effects in the (LC) oscillator  360 . These stress effects correlates with mechanical bending effects of the chip and are mainly responsible for lifetime shifts or package effects. 
     The layout arrangement of the LC oscillator  340  of  FIGS. 11 a  and 11 b    comprises symmetrically surrounding stress sensors  102 - 1  to  102 - 4  for determining the stress average and temperature average and if possible, showing no reaction to stress gradients. The symmetrically arranged temperature sensors  104 - 1  to  104 - 4  are arranged for determining the temperature without temperature gradients via the average. Moreover, the temperature sensors are radially arranged, wherein a temperature difference measurement can be conducted between symmetrically arranged temperature sensors for determining temperature gradients. Temperature gradients (e.g. caused by power in the coil) which can, for example, slightly change the position or perimeter of coils on the die or the position may be influenced by gradient caused stress effects. 
     In the following, a summary of different aspects of the different embodiments described above with respect to  FIGS. 1-11   b  is provided for facilitating the understanding of the inventive implementation of an on-chip oscillator with stress compensation to reduce package and life-time drift. 
     In accordance with embodiments, the stress compensated oscillator circuitry uses digital values derived from stress sensor to change the digital input of a fractional divider. 
     In accordance with embodiments, the stress compensated oscillator circuitry uses the correlation between global X- and Y-direction stress effects of die to local X- and Y-stress effects. 
     In accordance with embodiments, a combination of frequency determining components with different stress components is performed so that the different stress components cancel. For example, a first resistive element (arrangement like L-shape) with positive stress coefficient (i.e. a lateral n diffusion) and a second resistive element (arrangement like L-shape) with negative stress coefficient (e.g. a vertical n diffusion) is used for the sensor elements of the sensor arrangement  100 . 
     In accordance with embodiments, a stress sensor (the stress sensor arrangement  100  with a plurality of sensor elements) is used, wherein the resulting stress signals (sensor output signals as sensor) “correlate” to the undesired influence parameter of the oscillator circuitry and the stress signals are used for stress compensation, i.e. are used by the processing arrangement  200  for determining the control signal s control . For example, the stress sensor provides a (σ XX +σ YY ) stress dependent signal (dependent on an addition of the normal stress components) and a (σ XX −σ YY ) stress dependent signal (dependent on a difference of the normal stress components) to determine different correction signals (different control signals s control ) for the x- and y-direction in the semiconductor substrate (the sensor die). In this connection it is pointed to the fact that, a long resistor parallel to a trench has another stress influence than particular to this trench. 
     In accordance with embodiments, a stress compensated RC relaxation oscillator is used which controls an LC oscillator in a (fractional) PLL loop. 
     In accordance with embodiments, a differential temperature sensor is used to determine stress effects especially in LC oscillators (in addition to stress compensation or alone) in order to compensate thermal-gradient-induced stress effects. 
     In addition or alternatively, some stress components can be measured on top with differential temperature sensors. 
     A constant current reference or a stress dependent bias current may be built by adding or subtracting two different temperature-constant (or with bandgap-defined temperature coefficient) current sources with different mechanical stress coefficients. This may done by using two different resistor types in the current sources and bandgap-based replica circuits. 
     In accordance with embodiments, a 45° to wafer flat and lateral L-shape n-diffusion or n-well resistors with a positive piezo-resistive effect of σ xx +σ yy =−24%/GPa (sum) and σ xy =+155.6%/GPa are used in combination with vertical n-diffusion or n-well resistors with σ xx +σ yy =+52%/GPa (sum). By that different (X and Y) stress dependent correction signals can be derived. This correction signals can be analog voltages or currents or resistors or digital correction signals derived from a stress sensor via an ADC. 
     In accordance with embodiments, a 0°/90° to wafer flat and lateral L-shape n-diffusion or n-well resistors with a positive piezo-resistive effect of σ xx +σ yy =−24%/GPa (sum) and σ xx −σ yy =+6.8%/GPa are used in combination with vertical n-diffusion or n-well resistors with σ xx +σ yy =+52%/GPa (sum). By that different (X and Y) stress dependent correction signals can be derived. This correction signals can be analog voltages or currents or resistors or digital correction signals derived from a stress sensor via an ADC. 
     The embodiments described above with respect to  FIGS. 1-11   b  are advantageous in that the accordingly implemented stress compensated oscillator circuitry  10  shows 5 to 10 times smaller packaging shifts than comparable oscillator circuitries of the prior art. Moreover, a low cost and low drift on-chip solution with much lower lifetime shifts and higher stability can be provided. Moreover, soldering and process changes in packaging or humidity changes in package do not lead to frequency changes. Only one-point adjustment for the oscillator output signal s osc  with the oscillator output frequency f osc  at any temperature is required. For a higher accuracy, also a two-point adjustment is possible. However, no further two-point adjustments for stress compensation is required. Moreover, fixed stress coefficients can be used for one specific design of the integrated circuit. The inventive oscillator circuitry provides also a much faster settle time after power-on (e.g. 10 times faster). Based on the inventive concept, crystal oscillator circuits or MEMS oscillator circuits can be removed from the integrated circuit for many applications. 
     Although the invention and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims. 
     Moreover, the scope of the present application is not limited to the particular embodiments of the process, machine, manufacturer, composition of matters, means, method and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present application, processes, machines, manufacture, compositions of matter, means, methods, or steps presently existing or later to be developed that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the invention. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, and methods of steps.