Patent Publication Number: US-8116424-B2

Title: Shift register and liquid crystal display using same

Description:
FIELD OF THE INVENTION 
     Embodiments of the present disclosure relate to a shift register, and more particularly to a shift register in a liquid crystal display (LCD). 
     GENERAL BACKGROUND 
     Shift registers are core circuit units of integrated circuits that are used in products such as thin film transistor liquid crystal displays (TFT-LCDs). A shift register provides sequential pulse signals to scanning lines of a TFT-LCD, so as to control on and off states of TFTs connected to the scanning lines. 
     Referring to  FIG. 5 , one such shift register unit  100  includes a first clock inversion circuit  110 , an inverter  120 , and a second clock inversion circuit  130 . All transistors in the first clock inversion circuit  110 , the inverter  120 , and the second clock inversion circuit  130  are PMOS (P-channel metal oxide semiconductor) transistors. The first clock inversion circuit  110  receives an output signal VS from a pre-stage shift register unit (not shown). The output signal VS functions as a start signal. 
     The first clock inversion circuit  110  includes a first transistor P 1 , a second transistor P 2 , a third transistor P 3 , a fourth transistor P 4 , a first output V 1 , and a second output V 2 . The inverter  120  includes a fifth transistor P 5  and a sixth transistor P 6 . The inverter  120  outputs an output signal that serves as a shift register signal V. The second clock inversion circuit  130  and the first clock inversion circuit  120  have similar structures. The second clock inversion circuit  130  includes a seventh transistor P 7 , an eighth transistor P 8 , a ninth transistor P 9 , and a tenth transistor P 10 . 
     Referring to  FIG. 6 , a sequence waveform diagram of pulse signals of the shift register unit  100  is shown. During a period t 1 , the inverter  120  and the second clock inversion circuit  130  perform a latch operation. During the latch operation, the sixth transistor P 6  is switched off such that the shift register signal V of the inverter  120  keeps an original state of the previous stage. During a period t 2 , no latch operation is performed. The start signal VS is applied to the inverter  120 , and the second clock inversion circuit  130  keeps the same state as the start signal VS. Furthermore, the first transistor P 1  is switched on because the start signal VS jumps to a low voltage, such that the fifth transistor P 5  is switched off and the sixth transistor P 6  is switched on. Thus, the inverter  120  outputs the shift register signal V having a low level through the activated sixth transistor P 6 . During a period t 3 , the inverter  120  and the second clock inversion circuit  130  perform latch operation. The inverter  120  maintains output of a low level shift register signal V through the activated sixth transistor P 6 . During a period t 4 , no latch operation is performed. The inverter  120  stops output of the low-level shift register signal V. 
     However, the shift register unit  100  receives the start signal VS during period t 2 , and at the same time, outputs the shirt register signal V. These two signals VS, V may liable to overlap during period t 2 . That is, in the LCD that taking the shift register units  100  as gate or data driving circuits, two rows or columns of the gate/data lines may be scanned at the same time. Therefore, it may cause signal distortions, which may cause color shift while displaying images on the LCD. 
     What is needed, therefore, is a shift register which can overcome the above-described deficiencies. What is also needed is an LCD device including the shift register. 
     SUMMARY 
     A shift register includes a plurality of shift register units, and each two adjacent shift register units receives two inverse clock signals. Each of the shift register unit includes an output circuit, and input circuit, and a logic circuit. The output circuit receives a clock signal from an external circuit, which includes a clock transistor for receiving the clock signal; and a voltage stabilizing transistor for receiving a low level voltage signal. The input circuit receives signals output by a previous shift register unit and outputs signals to turn on the clock transistor. The logic circuit receives a high level voltage signal, a low level voltage signal, and signals output by the input circuit, to control the logic circuit to output a high level voltage signal or a low level voltage signal to the voltage stabilizing transistor. When the input circuit outputs signals to switch on the clock transistor, the logic circuit outputs a low level voltage signal to shut off the voltage stabilizing transistor. Thus, the output circuit outputs signals via the clock circuit. On the other hand, when the input circuit outputs signals to shut off the clock transistor, the logic circuit outputs a high level voltage signal to turn on the voltage stabilizing transistor, so as to maintain the output circuit to output low level voltage signal. 
     A liquid crystal display includes a liquid crystal panel, a gate driving circuit, and a data driving circuit. Each of the gate driving circuit and the data driving circuit includes at least one shift register, and each of the shift registers includes a plurality of shift register units connected in stages. Further, each two adjacent shift register units receives two inverse clock signals. Each of the shift register unit includes an output circuit, and input circuit, and a logic circuit. The output circuit receives a clock signal from an external circuit, which includes a clock transistor for receiving the clock signal; and a voltage stabilizing transistor for receiving a low level voltage signal. The input circuit receives signals output by a previous shift register unit and outputs signals to turn on the clock transistor. The logic circuit receives a high level voltage signal, a low level voltage signal, and signals output by the input circuit, to control the logic circuit to output a high level voltage signal or a low level voltage signal to the voltage stabilizing transistor. When the input circuit outputs signals to switch on the clock transistor, the logic circuit outputs a low level voltage signal to shut off the voltage stabilizing transistor. Thus, the output circuit outputs signals via the clock circuit. On the other hand, when the input circuit outputs signals to shut off the clock transistor, the logic circuit outputs a high level voltage signal to turn on the voltage stabilizing transistor, so as to maintain the output circuit to output low level voltage signal. 
     Other novel features and advantages will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  illustrates a circuit diagram of one embodiment of a shift register of the present disclosure including a plurality of shift register units. 
         FIG. 2  illustrates a low-level schematic diagram of one embodiment of the shift register unit of  FIG. 1 . 
         FIG. 3  illustrates a sequence waveform diagram of exemplary pulse signals of the shift register unit of  FIG. 1 . 
         FIG. 4  illustrates one embodiment of a liquid crystal display employing at least one of the shift registers of  FIG. 1 . 
         FIG. 5  is a circuit diagram of a shift register unit of a conventional shift register. 
         FIG. 6  is a sequence waveform diagram of pulse signals of the shift register of  FIG. 5 . 
     
    
    
     DETAILED DESCRIPTION OF CERTAIN INVENTIVE EMBODIMENTS 
       FIG. 1  illustrates a circuit diagram of one embodiment of a shift register  20  of the present disclosure including a plurality of shift register units  21 ,  22 . The shift register units  21 ,  22  are connected in series, and each of which receives a first clock signal CLK, a second clock signal CLKB inverse to the first clock signal CLK, a high level voltage signal VGH, and a low level voltage signal VGL. Each shift register unit  21  includes a plurality of NMOS (N-channel metal oxide semiconductor) transistors, and each NMOS transistor includes a gate, a source, and a drain. The shift register units  21  includes an input STV, a first output VOUT 1 , and a second VOUT 2 . Further, the shift register unit  22  includes an input VIN, a first output VO 1 , and a second output VO 2 . Signals output by the first output VOUT 1  of the shift register unit  21  are transmitted to the input VIN of the shift register unit  22 , and signals output by the first output VO 1  and the second output VO 2  of the shift register unit  22  may feedback to the shift register unit  21 . The second output VOUT 2  of the shift register unit  21  and the second output VO 2  of the shift register unit  22  serve to output to an external circuit (not shown). 
       FIG. 2  illustrates a low-level schematic diagram of one embodiment of the shift register units  21 ,  22 . The shift register unit  21  includes an input circuit  211 , a logic circuit  213 , a feedback circuit  215 , an output circuit  217 , and a first node X 1 . The input circuit  211 , the logic circuit  213 , and the output circuit  217  are coupled to the first node X 1 . 
     The input circuit  211  includes a first transistor M 1 . A drain of the first transistor M 1  receives the high level voyage signal VGH, and a gate of the first transistor M 1  serves as an input STV of the first shift register unit  21 . Further, a source of the first transistor M 1  is connected to the node X 1 . 
     The logic circuit  213  includes a second transistor M 2 , a third transistor M 3 , a fourth transistor M 4 , and a fifth transistor M 5 . A source of the second transistor M 2  receives the low level voltage signal VGL, and a gate of the second transistor M 2  is connected to a gate of the fourth transistor M 4 . The gates of the second and fourth transistors M 2 , M 4  are connected to the first node X 1 . Further, a drain of the second transistor M 2  is connected to sources of the fifth transistors M 5 . A source of the fourth transistor M 4  receives the low level voltage signal VGL, and a drain of the fourth transistor M 4  is connected to a source of the third transistor M 3 . A gate of the third transistor M 3  is connected to the drain of the second transistor M 2 , and a drain of the third transistor M 3  receives the high level voltage signal VGH. A gate and a drain of the fifth transistor M 5  is connected with each other, for receiving the high level voltage signal VGH. 
     The feedback input  215  includes a sixth transistor M 6 , a seventh transistor M 7 , an eighth transistor M 8 , a ninth transistor M 9 , and a second node X 2 . A gate of the sixth transistor M 6  receives signals output from the second shift register unit  22 , and a drain of the sixth transistor M 6  receives the high level voltage signal VGH. Further, a source of the sixth transistor M 6  is connected to second node X 2 . A gate of the seventh transistor M 7  is connected to the second node X 2 , and a source of the seventh transistor M 7  receives the low level voltage signal VGL. Further, a drain of the seventh transistor M 7  is connected to the node X 1 . Gates of the eighth and ninth transistors M 8 , M 9  are connected to the second node X 2 , and sources of the eighth and ninth transistors M 8 , M 9  receives the low level input VGL. Further, drains of the eighth and ninth transistors M 8 , M 9  are connected to the output circuit  217 . 
     The output circuit  217  includes a tenth transistor M 10 , an eleventh transistor M 11 , and a twelfth transistor M 12 . The tenth and eleventh transistors M 10 , M 11  serve as clock transistors of the output circuit  217 . Gates of the tenth and eleventh transistors M 10 , M 11  are connected to the first node X 1 , and drains of the ninth and tenth transistors M 9 , M 10  are connected to the first clock signal CLK. Further, sources of the tenth and eleventh transistors M 10 , M 11  are respectively connected to the drains of the eighth and ninth transistors M 8 , M 9 , and serve as the first output VOUT 1  and the second output VOUT 2 , respectively. Signals output by the first output VOUT 1  are transmitted to the input VIN of the second shift register unit  22 , and signals output by the second output VOUT 2  are transmitted to an external circuit. The twelfth transistor M 12  serves as a voltage stabilizing transistor, and a gate of the twelfth transistor M 12  is connected to the source of the fifth transistor M 5  of the logic circuit  213 . A source of the twelfth transistor M 12  receives the low level voltage signal VGL, and a drain of the twelfth transistor M 12  is connected to the second output VOUT 2 . 
     The second shift register unit  22  has an arrangement similar to that of the first shift register unit  21 . The second shift register unit  22  includes twelve transistors T 1 ˜T 12 , an input VIN, a first output VO 1 , and a second output VO 2 . The input VIN receives signals output by the first output VOUT 1  of the first shift register unit  21 , and the first output VO 1  is connected to the gate of the sixth transistor M 6  of the first shift register unit  21 . Drains of the tenth transistor T 10  and the twelfth transistor T 12  are connected to the second clock signal CLKB. 
       FIG. 3  illustrates a sequence waveform diagram of exemplary pulse signals of the shift register units  21 ,  22  of  FIG. 1 . During the period t 1 , the first clock signal CLK is set at a low level voltage signal VGL, and the second clock signal CLKB is set at a high level voltage signal VGH. Further, the start input STV turns from a low level voltage signal VGL to a high level voltage signal VGH during the period t 1 . 
     In the first shift register unit  21 , the first transistor M 1  of the input circuit  211  is switched off, so as to maintain the first node X 1  at a low level. Then, the tenth and eleventh transistors M 10 , M 11  of the output circuit  217  are switched off. The first clock signal CLK cannot output to the first output VOUT 1 , and the first output VOUT 1  is kept as a low level. At the same time, the second and fourth transistors M 2 , M 4  of the logic circuit  213  are switched off, and cannot receive the low level voltage signal VGL. The fifth transistor M 5  of the logic circuit  213  is switched on due to that the gate and drain of which receive the high level voltage signal VGH, and cause the twelfth transistor M 12  to be switched on. The second output VOUT 2  of the first shift register  21  outputs low level voltage signal VGL to the external circuit. 
     During the period t 1 , the second shift register unit  22  receives the second clock signal CLKB at a low level voltage signal VGL. The input VIN of the second shift register unit  22  receives the signals output by the first shift register unit  21 , and the signals are maintained at a low level voltage signal VGL. Then, the first, the ninth, and the tenth transistors T 1 , T 9 , T 10  are all switched off. The first and second outputs VO 1 , VO 2  respectively output the low level signal VGL. At the same time, the second and fourth transistors T 2 , T 4  are switched off, and the fifth transistor T 5  is switched on via receiving the high level voltage signal VGH. The second clock signal CLKB at high level VGH are transmitted to twelfth transistor T 12  via the fifth transistor T 5 , so as to make the low level signal VGL to be transmitted to the first and second outputs VO 1 , VO 2 . Therefore, the first and second outputs VO 1 , VO 2  respectively maintain to output the low level voltage signal VGL. The low level voltage signal VGL output by the second output VO 2  is feedback to the gate of the sixth transistor M 6 , so as to switch off the sixth transistor M 6 . Then, the seventh, the eighth, and the ninth transistors M 7 , M 8 , M 9  of the feedback circuit  215  are switched off. 
     After that, when signals input to the input STV turns from a low level voltage signal VGL to a high level voltage signal VGH, the first transistor M 1  is switched on, and the input circuit  211  outputs the high level voltage signal VGH to the first node X 1  via the first transistor M 1 . Then, the tenth and eleventh transistors M 10  and M 11  are switched on, and the first and second outputs VOUT 1 , VOUT 2  respectively outputs the first clock signal CLK. That is, the first output VOUT 1  outputs the low level voltage signal VGL to the second shift register unit  22 , and the second output VOUT 2  outputs the low level voltage signal VGL to the external circuit. At the same time, the second and fourth transistors M 2 , M 4  connected to the first node X 1  are also switched on, so as to pull down a voltage level of the source of the fifth transistor M 5  to a low level voltage signal. Then, the twelfth transistor M 12  is switched off, and the second output VOUT 2  maintains to output the first clock signal CLK. Meanwhile, the first and second outputs VO 1 , VO 2  respectively maintain to output the low level voltage signal VGL. 
     During a period t 2 , the first clock signal CLK turns to a high level voltage signal VGH, and the second clock signal CLKB turns to a low level voltage signal VGL. Further, the start signal STV turns from a high level voltage signal VGH to a low level voltage signal VGL during the period t 2 . 
     In the first shift register unit  21 , the input circuit  211  outputs the high level voltage signal VGH to the first node X 1 . Then, the tenth and eleventh transistors M 10 , M 11  are switched on. Therefore, the first output VOUT 1  of the output circuit  217  outputs the first clock signal CLK (the high level voltage signal VGH) to the second shift register unit  22 , and the second output VOUT 2  of the output circuit  217  outputs the first clock signal CLK (the high level voltage signal VGH) to the external circuit (not shown), so as to pull up the voltage level of the node X 1 . At the same time, the second transistor M 2  is switched on and the source of the fifth transistor M 5  is kept at a low level. Then, the twelfth transistor M 12  is switched off, and the second output VOUT 2  maintains to output the first clock signal CLK (the high level voltage signal VGH) to the external circuit (not shown). 
     During the period t 2 , the second shift register unit  22  receives the second clock signal CLKB at a low level voltage signal VGL. The input VIN of the second shift register unit  22  receives the signals output by the first shift register unit  21 , and the signals are maintained at a high level voltage signal VGH. Then, the first transistor T 1  is switched on to output the high level voltage signal VGH to the tenth and eleventh transistors T 10 , T 11 . The first and second outputs VO 1 , VO 2  respectively output the second clock signal CLKB at a low level voltage signal VGL. Meanwhile, the twelfth transistor T 12  is switched off to maintain the second output VO 2  to output the second clock signal CLKB (the low level voltage signal VGL) to the external circuit and feedback the second clock signal CLKB to the first shift register unit  21  and the gate of the sixth transistor M 6 . The sixth transistor M 6  is switched off so as to shut off the seventh, eighth, and night transistors T 7 , T 8 , T 9 . 
     After that, when signals input to the input STV of the first shift register unit  21  turns from a high level voltage signal VGH to a low level voltage signal VGH, the first transistor M 1  is switched off. That is, the first node X 1  maintains at a high level. The first and second outputs VOUT 1 , VOUT 2  maintains to output the high level voltage signal VGH, and the twelfth transistor M 12  is still shut off. That is, the signals received by the second shift register unit  22  is not varied, and the first and second outputs VO 1 , VO 2  maintain to output the second clock signal CLKB. 
     During the period t 3 , the input STV keeps to receive the low level voltage signal VGL, the first clock signal CLK is at a low level, and the second clock signal CLKB is at a high level. 
     In the first shift register unit  21 , the first transistor M 1  is switched off, and the first node X 1  is maintained at a high level. The tenth and eleventh transistors M 10 , M 11  are switched on. The first and second outputs VOUT 1 , VOUT 2  of the output circuit  217  output the low level voltage signal VGL. 
     At the same time, the second shift register unit  22  receives the second clock signal CLKB at a high level voltage signal VGH. The input VIN of the second shift register unit  22  receives the signals output by the first shift register unit  21 , and the signals are maintained at a low level voltage signal VGL. Then, the first transistor T 1  is switched off, and the tenth and eleventh transistors T 10 , T 11  are all switched on. The first and second outputs VO 1 , VO 2  respectively output the second clock signal CLKB at a high level voltage signal VGH. At the same time, the output VO 2  outputs the high level voltage signal VGH to the external circuit and feedback the high level voltage signal VGH to the sixth transistor M 6  of the first shift register unit  21 . The six transistor M 6  is switched on, which receives the high level signal to switch on the seventh, eighth, and ninth transistors M 7 , M 8 , M 9 . Therefore, the seventh, eighth, and ninth transistors M 7 , M 8 , M 9  receive the low level voltage signal VGL, so as to pull down the voltage level of the first node X 1 , the first and second outputs VOUT 1 , VOUT 2 . Then, the tenth and eleventh transistors M 10 , M 11  are switched off, and the second transistor M 2  is switched off. The fifth transistor M 5  keeps to receive the high level voltage signal VGH, so as to switch on the twelfth transistor M 12 , to keep the second output VOUT 2  to output low level voltage signal VGL. 
     After the period t 3 , the input STV of the first shift register unit  21  keeps to receive the low level voltage signal VGL, and the first node X 1  is kept at a low level. Then, the tenth and eleventh transistors M 10 , M 11  are switched off. The first clock signal CLK cannot output via the tenth and eleventh transistors M 10 , M 11 . Moreover, the first transistor M 5  is switched on, so as to output the high level voltage signal VGH to switch on the twelfth transistor M 12 , for keeping the second output VOUT 2  to output the low level voltage signal VGL. 
     According to the operation sequence, the tenth and eleventh transistors T 10 , T 11  of the second shift register unit  22  are switched on while the tenth and eleventh transistors M 10 , M 11  of the first shift register unit  21  are switched on, and the first clock signal CLK and the second clock signal CLKB are reversed, and periodically varied. Therefore, the signals output by the first and second shift register units  21 ,  22  are not overlapped with each other. Moreover, the second shift register unit  22  may feedback the high level voltage signal VGH to the first shift register unit  21  via the feedback circuit  215 , to reset the first shift register unit  21 , so as to keep the first shift register unit  21  to output a low level voltage signal from the twelfth transistor M 12 . 
     Therefore, the adjacent shift register units may not cause signal distortions between adjacent shift register units due to overlapping adjacent shift register signals. As a result, the shift register unit  21  is liable to be stable. 
     Referring to  FIG. 4 , a liquid crystal display employing the shift registers  20  is shown. The liquid crystal display  30  includes a liquid crystal display panel  31 , a data driving circuit  32 , and a gate driving circuit  33 . Both the gate and data driving circuits  33 ,  32  install shift registers  20  to control output sequence of the gate driving signals and data signals, so as to control the images displayed by the liquid crystal display  30 . 
     Accordingly, the liquid crystal display  30  employing the shift register  20  may not have a distorted display quality because adjacent scanning lines corresponding to adjacent columns or rows of TFTs may be scanned simultaneously by the shift register pulse signals instead of being scanned sequentially. 
     It is to be further understood that even though numerous characteristics and advantages of the present inventive embodiments have been set out in the foregoing description, together with details of the structures and functions of the embodiments, the disclosure is illustrative only, and that changes may be made in detail, especially in matters of shape, size, and arrangement of parts within the principles of the present disclosure to the full extent indicated by the broad general meaning of the terms in which the appended claims are expressed.