Patent Publication Number: US-11035897-B2

Title: Method and device for fault section identification in multi-terminal mixed lines

Description:
FIELD OF THE INVENTION 
     The present invention generally relates to fault section identification in multi-terminal mixed lines. 
     BACKGROUND OF THE INVENTION 
     In power transmission lines, auto-reclosure (or auto-reclose) is referred to as the automatic closing of a switching device (e.g. a circuit breaker) in order to restore service in transmission lines. It is performed following the tripping of the switching device due to a fault on the protected line. Since a significant number of the faults on overhead transmission lines are temporary faults, auto-reclosing can be used to quickly re-energize the line and restore service. 
     Certain considerations are to be taken with respect to the auto-reclosing function, especially in case of lines having underground cables. As faults in underground cables tend to be permanent, it is important that auto-reclosure is not done for underground cables. Auto-reclosing, when the fault is on the cable, can cause damage to the power cable and equipment such as circuit breaker, substation transformer and/or the nearby parts of the power system by subjecting them to additional stress. 
     Special consideration has to be taken for auto-reclosure in mixed lines. A mixed power transmission line (mixed line) is a transmission line with non-uniform line impedance characteristics. In other words, a mixed line has at least two line sections, wherein impedance characteristic (e.g. surge impedance) of one section is different from impedance characteristic of the other section(s). Selective auto-reclosure can be done for such lines only if it can be determined if the fault is on the cable portion or on the overhead line portion. This makes fault section identification (FSI) critical in these systems. 
     FSI becomes even more relevant and critical for multi-terminal mixed lines (e.g. a three-terminal or tapped line). In such lines, faults can happen in an overhead line, an underground cable, or at a junction between overhead line(s) and/or cables. Also, some faults (e.g. faults as a result of lightning) on the overhead line can cause damages to other parts of the line (e.g. insulation breakdown/cable termination damages). 
     Additionally, in multi-terminal mixed lines, the number of overhead line sections is typically more than the number of underground cable sections. Hence, for a reliable power system operation, accurate FSI is a need for selective tripping of the faulted section. 
     Fault location is an important parameter for reducing the maintenance time and increasing the system availability. In multi-terminal lines, the problem of accurate fault location becomes multi-fold due to incorrect FSI. Thus, FSI becomes a mandatory input for getting reliable fault location in multi-terminal mixed lines. 
     SUMMARY OF THE INVENTION 
     Various aspects of the invention relate to fault section identification in a multi-terminal mixed line. The mixed line connects three or more terminals (multi-terminal mixed line). For example, the mixed line can be a three terminal line connecting a first terminal, a second terminal and a third terminal. In such a three terminal line, there can be three sections and a junction (e.g. common junction (or tap) for the three sections), with a first section between the first terminal and the junction, a second section between the second terminal and the junction, and a third section between the third terminal and the junction. 
     The invention provides a method for fault section identification in the multi-terminal mixed line. For example, there may be an electrical fault in the multi-terminal mixed line due to disturbances like as bad weather, wind-borne debris etc. In such a case, a portion of the line or the entire line may be disconnected from the rest of power transmission network to prevent propagation of faults/damage to electrical equipment. The protection is enabled by controlling a switching device connected to the mixed line (e.g. through an Intelligent Electronic Device (IED)). Controlling the switching device includes operating the switching device to connect or disconnect the line. The switching device may be a circuit breaker, and the switching can be controlled with an auto-recloser. 
     The method is performed with one or more processors associated with controlling the switching device. For example, the method can be implemented by an IED having a processor. This may be an IED associated with one of a line section, a junction, a terminal etc. The IED receives one or more signals from one or more measurement equipment connected to the mixed line. For example, the measurement equipment can include a current transformer, a potential transformer, a sensor-based measurement equipment (e.g. Rogowski coils, non-conventional instrument transformers etc.) and/or the like, which provides a signal corresponding to current, voltage or other information as sensed from the mixed line. For example, a current transformer provides single/multiple phase current signal and a potential transformer can provide single/multiple phase voltage signal to the IED. 
     In an embodiment, the IED receives a signal(s) from the measurement equipment, and obtain measurements therefrom. In another embodiment, the measurement equipment publishes the measurements over a bus (e.g. process bus), and the IED (e.g. subscribed to receive data from such bus) receives the measurements over the bus. 
     In an embodiment, the method is implemented with a device for fault section identification in the multi-terminal mixed line, wherein the device has a plurality of modules. The plurality of modules can include, but need not be limited to, an input interface, a phasor calculation module, a fault section identification module and a trip module. Each module carries out one or more steps of the method. Further, the plurality of modules may be implemented using one or more processors. For instance, the one or more processors may be a processor of an IED. 
     The method may also be implemented with communication between a device associated with the multi-terminal mixed line, and a server. Here, some steps of the method may be performed with one or more processors of the server (e.g. calculations or use of models using measurements from various measurement equipment at various terminals of the multi-terminal mixed line), while the others are performed with one or more processors of the device (e.g. generation of re-trip signal for control of the switching device, through one or more processors of the device). 
     The method comprises obtaining positive sequence voltage and current phasors from measurements of voltages and currents at each terminal of the multi-terminal mixed line. It is to be noted that the phasors may be obtained from measurements at the device (e.g. received from a current/potential transformer at an IED of a terminal), or measurements received from other devices (e.g. other IEDs associated with other terminals). Here, a device (e.g. server) may collect current and voltage phasors from all IEDs in the network (e.g. over a communication channel). 
     The method further comprises calculating a voltage phasor for each terminal of the multi-terminal mixed line. The calculation of the voltage phasor for the first terminal is performed using at least the voltage and current phasors obtained for one of the second and third terminals, and the current phasor obtained for the first terminal. 
     The step of calculating the voltage phasor for the each terminal can include calculating two voltage phasors for the terminal. In such a case, a first voltage phasor for the first terminal is calculated using voltage and current phasors obtained for the second terminal, and a second voltage phasor for the second terminal is calculated using voltage and current phasors obtained for the third terminal. Here, one of the two calculated voltage phasors is selected for the terminal based on a comparison of the calculated and obtained voltage phasors. For example, the voltage phasor for which the difference between the calculated and obtained value is the lowest amongst the two is selected. Similarly, the voltage phasors can be calculated for the other terminals. 
     In an embodiment, calculating the voltage phasor for the first terminal comprises calculating a voltage phasor at the junction based on the voltage and current phasors obtained for the second terminal, and impedance characteristics of the section connecting the second terminal with the junction. Thereafter, the voltage phasor for the first terminal is calculated based on the voltage phasor calculated for the junction, the current phasor obtained for the first terminal, and impedance characteristics of the section connecting the first terminal with the junction. Such calculation may also be based on the voltage and current phasors obtained for the third terminal (in place of the second terminal). 
     In addition, the method comprises determining a section of the multi-terminal mixed line having the fault, based on the comparison of the calculated and obtained voltage phasors for each terminal. In an embodiment, determining the section with the fault comprises comparing the difference between the calculated and obtained voltage phasors for each terminal. Consider a case where the difference for each terminal is less than a threshold. In such a case, the fault may be determined to be at the junction. In an embodiment, the terminal for which the difference between the calculated and obtained voltage phasors is the lowest among all, can be identified as healthy or non-faulty sections, and conclude that other section as fault. For example, if the terminal A voltage calculated from terminal B is almost equal to the measured voltage at terminal A (difference is lowest), the fault can be identified on section CJ (that is between terminal C and junction). In another embodiment, the section associated with the terminal for which the difference between the calculated and obtained voltage phasors is the highest among all, can be identified as the section with the fault. 
     In an embodiment, the method comprises determining a location of the fault according to the determined section, wherein the calculated voltage and current phasors for the corresponding terminal are used for determining location of the fault. 
     The method can also comprise controlling the switching device with a re-trip signal (trip signal generated after tripping with a switching device like circuit breaker) for protecting the multi-terminal mixed line, wherein the re-trip signal is generated based on the determination of the section with the fault. The re-trip signal is associated with an auto-reclose function, and the re-trip signal is generated in response to determining that the section with the fault is an overhead line section. In other words, the auto-reclose function is enabled only when it is determined that the fault is in an overhead line section, and not enabled (blocked) when it is determined that the fault is in an underground cable. This re-trip signal may be generated with an IED (e.g. IED at the first terminal) for controlling the associated switching device (e.g. circuit breaker). 
    
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
       The subject matter of the invention will be explained in more detail in the following text with reference to exemplary embodiments which are illustrated in attached drawings in which: 
         FIG. 1  is a simplified representation of a multi-terminal mixed line, in accordance with an embodiment of the invention; 
         FIG. 2  is a simplified representation of a connection of an intelligent electronic device for obtaining measurements from the mixed line, in accordance with an embodiment of the invention; 
         FIG. 3  is a simplified block diagram of a device for fault section identification, in accordance with an embodiment of the invention; and 
         FIG. 4  is a flowchart of a method for fault section identification, in accordance with an embodiment of the invention. 
     
    
    
     DETAILED DESCRIPTION 
     Various aspects of the present invention relate to fault section identification in a mixed line. Here, the mixed line is a multi-terminal line (multi-terminal mixed line), wherein the mixed line has three or more terminals. 
     Referring to  FIG. 1 , which illustrates a multi-terminal mixed line (also referred as tapped line) connecting three terminals in accordance with an embodiment of the invention. The line shown in  FIG. 1  is a three terminal line, having three terminals and one junction. Bus A, Bus B and Bus C are the three terminals and J is the junction. There could also be more than one junction (e.g. two or more) in case of multiple line sections between the terminals (not shown in  FIG. 1 ). For example, there could be an overhead line section, followed by a cable and another overhead line section between two terminals. In such a case, there could be two junctions. 
     The invention provides a method for fault section identification. The identification is performed in response to a fault in the multi-terminal mixed line. The section identification information is used for controlling a switching device connected to the multi-terminal mixed line. Controlling the switching device includes operating the switching device to connect or disconnect the line. The switching device may be a circuit breaker, and the switching can be controlled with an auto-recloser. For example, the switching device may be a circuit breaker such as CB1 or CB2 connected with overhead line sections as shown in  FIG. 1 . 
     The method is performed with one or more processors associated with controlling the switching device. For example, the method can be implemented by an IED with a processor. This may be an IED associated with one of a line section, a junction, a terminal etc. An example is illustrated in  FIG. 2 , wherein the IED ( 202 ) is associated with Bus A. The IED receives one or more signals from one or more measurement equipment connected to the multi-terminal mixed line. In the example of  FIG. 2 , a current transformer (CT) provides single/multiple phase current signal and a potential transformer (PT) provides single/multiple phase voltage signal to the IED. 
     In an embodiment the IED receives a signal(s) from the measurement equipment, and obtain measurements therefrom. In another embodiment, the measurement equipment publishes the measurements over a bus (e.g. process bus), and the IED (e.g. subscribed to receive data from such bus) receives the measurements over the bus. 
     In an embodiment, the method is implemented with a device for fault section identification in the multi-terminal mixed line, wherein the device has a plurality of modules.  FIG. 3  is a simplified block diagram of the device. In accordance with the embodiment illustrated in  FIG. 3 , the plurality of modules include an input interface ( 302 ), a phasor calculation module ( 304 ), a fault section identification module ( 306 ), a trip module ( 308 ) and a memory ( 310 ). 
     In accordance with various embodiments of the invention, each module of the device carries out one or more steps of the method (described herein after in conjunction with description of  FIG. 3 ). Further, the plurality of modules may be implemented using one or more processors. For instance, the one or more processors may be a processor of an IED (e.g. IED  202 ). 
     The method may also be implemented with communication between a device associated with the mixed line, and a server. Here, some steps of the method may be performed with one or more processors of the server (e.g. calculations or use of models using measurements from various measurement equipment at various terminals of the mixed line), while the others are performed with one or more processors of the device (e.g. generation of re-trip signal for control of the switching device, through one or more processors of the device). 
     Referring to  FIG. 4 , which illustrates a flowchart of the method for fault section identification, in accordance with an embodiment. At  402 , the method comprises obtaining impedance parameters associated with each section of the mixed line. As shown in  FIG. 1 , assume:
         Section AJ is an overhead line of length L1 km,   Section BJ is an overhead line of length L2 km, and   Section CJ is an underground cable of length L3 km.       

     Further, assume that:
         ABCD AJ  denotes the positive sequence line impedance parameters (ABCD matrix) of section AJ,   ABCD BJ  denotes positive sequence line impedance parameters of section BJ, and   ABCD CJ  denotes positive sequence line impedance parameters of section CJ.       

     Such impedance parameters are obtained at  302 . Further, the parameters may be known before-hand, and stored in a memory associated with a processor associated with controlling the switching device. For example, this may be with IED  202  (e.g. in a memory thereof), or the device of  FIG. 3  (e.g. in memory  310 ). 
     At  404 , the method comprises obtaining positive sequence voltage and current phasors from measurements of voltages and currents at each terminal of the multi-terminal mixed line. Such phasors may be obtained using a suitable phasor calculation such as, but not limited to, Fourier calculations. For example, from the calculated voltage phasors, positive sequence quantities are computed using following transformation matrix: 
     
       
         
           
             
               [ 
               
                 
                   
                     
                       V 
                       
                         a 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         0 
                       
                     
                   
                 
                 
                   
                     
                       V 
                       
                         a 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         1 
                       
                     
                   
                 
                 
                   
                     
                       V 
                       
                         a 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         2 
                       
                     
                   
                 
               
               ] 
             
             = 
             
               
                 
                   1 
                   3 
                 
                 ⁡ 
                 
                   [ 
                   
                     
                       
                         1 
                       
                       
                         1 
                       
                       
                         1 
                       
                     
                     
                       
                         1 
                       
                       
                         a 
                       
                       
                         
                           a 
                           2 
                         
                       
                     
                     
                       
                         1 
                       
                       
                         
                           a 
                           2 
                         
                       
                       
                         a 
                       
                     
                   
                   ] 
                 
               
               ⁡ 
               
                 [ 
                 
                   
                     
                       
                         V 
                         a 
                       
                     
                   
                   
                     
                       
                         V 
                         b 
                       
                     
                   
                   
                     
                       
                         V 
                         c 
                       
                     
                   
                 
                 ] 
               
             
           
         
       
       
         
           
             where 
             , 
             
               
 
             
             ⁢ 
             
               a 
               = 
               
                 
                   e 
                   
                     j 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     
                       120 
                       0 
                     
                   
                 
                 = 
                 
                   
                     - 
                     
                       1 
                       2 
                     
                   
                   + 
                   
                     j 
                     ⁢ 
                     
                       
                         
                           3 
                         
                         2 
                       
                       . 
                     
                   
                 
               
             
           
         
       
     
     The phasors for each terminal may be obtained using an IED associated with the corresponding terminal (e.g. IED  202  for Bus A). In some embodiments, the phasors obtained for each terminal are communicated and stored (e.g. with IED  202  (e.g. in a memory thereof), or the device of  FIG. 3  (e.g. in memory  310 ). 
     The method further comprises calculating a voltage phasor for each terminal of the mixed line at  406 . The calculation of the voltage phasor for a terminal is performed using voltage and current phasors obtained for another terminal, and the current phasor obtained for the same terminal. For example, in case of three terminal line with a first terminal, a second terminal and a third terminal, the voltage phasor for the first terminal can be calculated using the voltage and current phasors obtained for the second terminal, and the current phasor obtained the first terminal. Here, in place of using the voltage and current phasors obtained for the second terminal, voltage and current phasors obtained for the third terminal may be used. Alternately, two voltage phasors can be calculated using the second and third terminal measurements along with the first terminal measurements, and one of the two selected. 
     In an embodiment, calculating the voltage phasor for the first terminal comprises calculating a voltage phasor at the junction based on the voltage and current phasors obtained for the second terminal, and impedance characteristics of the section connecting the second terminal with the junction. Thereafter, the voltage phasor for the first terminal is calculated based on the voltage phasor calculated for the junction, the current phasor obtained for the first terminal, and impedance characteristics of the section connecting the first terminal with the junction. 
     The following provides an example of calculation of a voltage phasor at each terminal of the three terminal line shown in  FIG. 1 . 
     Assume that:
         V Ameasured   1 , I Ameasured   1  are the positive sequence voltage and current phasors from measurements of voltages and currents at Bus A post the fault,   V Bmeasured   1 , I Bmeasured   1  are the positive sequence voltage and current phasors from measurements of voltages and currents at Bus B post the fault, and   V Cmeasured   1 , I Cmeasured   1  are the voltage and current phasors from measurements of positive sequence voltages and currents at Bus C post the fault.       

     Now, in order to calculate a voltage phasor for a second terminal (Bus B), we first calculate a voltage phasor at the junction J from voltage and current phasors obtained for the first terminal (Bus A); and section AJ impedance parameters, as shown in equations (A.1) and (A.2): 
                     [           V   JA   1               I   JA   1           ]     =         inv   ⁡     [           A   AJ   1           B   AJ   1               C   AJ   1           D   AJ   1           ]       *     [           V   A   1               I   A   1           ]       =       [           -     D   AJ   1             B   AJ   1               C   AJ   1           -     A   AJ   1             ]     *     [           V   A   1               I   A   1           ]                 (     A   ⁢   .1     )                 V     1   ⁢   A     1     =         -     D     A   ⁢   J       1   *         ⁢     V   A   1       +       B     A   ⁢   J       1   *       ⁢     J   A   1     ⁢   A               (     A   ⁢   .2     )               
Where, V JA   1  and I JA   1  are respectively voltage at the junction and current at the junction on section AJ.
 
     Now, using the voltage phasor calculated for the junction, the current phasor measured at the second terminal (Bus B), and impedance parameters of section BJ, lets calculate a voltage phasor, as shown in equation (A.3): 
     
       
         
           
             
               
                 
                   
                     [ 
                     
                       
                         
                           
                             V 
                             JB 
                             1 
                           
                         
                       
                       
                         
                           
                             I 
                             JB 
                             1 
                           
                         
                       
                     
                     ] 
                   
                   = 
                   
                     
                       
                         inv 
                         ⁡ 
                         
                           [ 
                           
                             
                               
                                 
                                   A 
                                   BJ 
                                   1 
                                 
                               
                               
                                 
                                   B 
                                   BJ 
                                   1 
                                 
                               
                             
                             
                               
                                 
                                   C 
                                   BJ 
                                   1 
                                 
                               
                               
                                 
                                   D 
                                   BJ 
                                   1 
                                 
                               
                             
                           
                           ] 
                         
                       
                       * 
                       
                         [ 
                         
                           
                             
                               
                                 V 
                                 Bcalculated 
                                 1 
                               
                             
                           
                           
                             
                               
                                 I 
                                 B 
                                 1 
                               
                             
                           
                         
                         ] 
                       
                     
                     = 
                     
                       
                         [ 
                         
                           
                             
                               
                                 - 
                                 
                                   D 
                                   BJ 
                                   1 
                                 
                               
                             
                             
                               
                                 B 
                                 BJ 
                                 1 
                               
                             
                           
                           
                             
                               
                                 C 
                                 BJ 
                                 1 
                               
                             
                             
                               
                                 - 
                                 
                                   A 
                                   BJ 
                                   1 
                                 
                               
                             
                           
                         
                         ] 
                       
                       * 
                       
                         [ 
                         
                           
                             
                               
                                 V 
                                 Bcalculated 
                                 1 
                               
                             
                           
                           
                             
                               
                                 I 
                                 B 
                                 1 
                               
                             
                           
                         
                         ] 
                       
                     
                   
                 
               
               
                 
                   ( 
                   
                     A 
                     ⁢ 
                     .3 
                   
                   ) 
                 
               
             
           
         
       
     
     Rearranging equation (A.3), we have, 
     
       
         
           
             
               
                 
                   
                     V 
                     Bcalculated 
                     1 
                   
                   = 
                   
                     
                       
                         V 
                         JB 
                         1 
                       
                       - 
                       
                         
                           B 
                           BJ 
                           1 
                         
                         * 
                         
                           I 
                           B 
                           1 
                         
                       
                     
                     
                       - 
                       
                         D 
                         
                           B 
                           ⁢ 
                           1 
                         
                         1 
                       
                     
                   
                 
               
               
                 
                   ( 
                   
                     A 
                     ⁢ 
                     .4 
                   
                   ) 
                 
               
             
           
         
       
     
     Since junction estimated voltage from healthy section are equal, substituting equation (A.2) in equation (A.4), 
     
       
         
           
             
               
                 
                   
                     V 
                     Bcalculated 
                     1 
                   
                   = 
                   
                     
                       
                         
                           D 
                           AJ 
                           1 
                         
                         * 
                         
                           V 
                           A 
                           1 
                         
                       
                       - 
                       
                         
                           B 
                           AJ 
                           1 
                         
                         * 
                         
                           I 
                           A 
                           1 
                         
                       
                       + 
                       
                         
                           B 
                           BJ 
                           1 
                         
                         * 
                         
                           I 
                           B 
                           1 
                         
                       
                     
                     
                       D 
                       BJ 
                       1 
                     
                   
                 
               
               
                 
                   ( 
                   
                     A 
                     ⁢ 
                     .5 
                   
                   ) 
                 
               
             
           
         
       
     
     V Bcalculated   1  provides the voltage phasor at the second terminal. In equation (A.1), 
     D AJ   1  and B AJ   1  are positive sequence impedance parameter of section AJ
 
 D   AJ   1 =cos  h (γ 1   dL   1 )
 
 B   AJ   1   =−Z   c1  sin  h (γ 1   dL   1 )
 
 Z   c1 =√{square root over (( r 1+ jωl 1)/( jωc 1))}
 
γ 1 =√{square root over (( r 1+ jωl 1)( jωc 1))}
         r1, l1 and c1 are resistance, inductance and capacitance per unit length of the section AJ,   V A   1 , I A   1  are the positive sequence voltage and current from measurements at Bus A and,   D BJ   1  and B BJ   1  is the positive sequence impedance parameter of section BJ
 
 D   BJ   1 =cos  h (γ 2   dL   2 )
 
 B   BJ   1   =−Z   c2  sin  h (γ 2   dL   2 )
 
 Z   c2 =√{square root over (( r 2+ jωl 2)/( jωc 2))}
 
γ 2 =√{square root over (( r 2+ jωl 2)( jωc 2))}
   r2, l2 and c2 are resistance, inductance and capacitance per unit length of the section BJ.   I B   1  is the positive sequence current from measurements at Bus B   V Bcalculated   1  is the positive sequence voltage calculated at Bus B.       

     In a similar manner, the voltage phasor for the third terminal (Bus C) can be calculated using the following equation (A.6): 
     
       
         
           
             
               
                 
                   
                     V 
                     Ccalculated 
                     1 
                   
                   = 
                   
                     
                       
                         
                           D 
                           BJ 
                           1 
                         
                         * 
                         
                           V 
                           B 
                           1 
                         
                       
                       - 
                       
                         
                           B 
                           BJ 
                           1 
                         
                         * 
                         
                           I 
                           B 
                           1 
                         
                       
                       + 
                       
                         
                           B 
                           CJ 
                           1 
                         
                         * 
                         
                           I 
                           C 
                           1 
                         
                       
                     
                     
                       D 
                       CJ 
                       1 
                     
                   
                 
               
               
                 
                   ( 
                   
                     A 
                     ⁢ 
                     .6 
                   
                   ) 
                 
               
             
           
         
       
     
     In equation (A.6), 
     D BJ   1  and B BJ   1  is the positive sequence impedance parameter of section BJ
 
 D   BJ   1 =cos  h (γ 2   dL   2 )
 
 B   BJ   1   =−Z   c2  sin  h (γ 2   dL   2 )
 
 Z   c2 =√{square root over (( r 2+ jωl 2)/( jωc 2))}
 
γ 2 =√{square root over (( r 2+ jωl 2)( jωc 2))}
         r2, l2 and c2 are resistance, inductance and capacitance per unit length of the section BJ.   V B   1 , I B   1  are the positive sequence voltage and current from measurements at Bus B   D CJ   1  and B CJ   1  is the positive sequence impedance parameter of section CJ
 
 D   CJ   1 =cos  h (γ 3   dL   3 )
 
 B   CJ   1   =−Z   c3  sin  h (γ 3   dL   3 )
 
 Z   c3 =√{square root over (( r 3+ jωl 3)/( jωc 3))}
 
γ 3 =√{square root over (( r 3+ jωl 3)( jωc 3))}
   r3, l3 and c3 are resistance, inductance and capacitance per unit length of the section CJ.   I C   1  is the positive sequence current from measurements at Bus C   V Ccalculated   1  is the positive sequence voltage calculated at Bus C.       

     In a similar manner, the voltage phasor for the first terminal (Bus A) can be calculated using the following equation (A.7): 
     
       
         
           
             
               
                 
                   
                     V 
                     Acalculated 
                     1 
                   
                   = 
                   
                     
                       
                         
                           D 
                           CJ 
                           1 
                         
                         * 
                         
                           V 
                           C 
                           1 
                         
                       
                       - 
                       
                         
                           B 
                           CJ 
                           1 
                         
                         * 
                         
                           I 
                           C 
                           1 
                         
                       
                       + 
                       
                         
                           B 
                           AJ 
                           1 
                         
                         * 
                         
                           I 
                           A 
                           1 
                         
                       
                     
                     
                       D 
                       AJ 
                       1 
                     
                   
                 
               
               
                 
                   ( 
                   
                     A 
                     ⁢ 
                     .7 
                   
                   ) 
                 
               
             
           
         
       
     
     In equation (A.7),
         D CJ   1  and B CJ   1  is the positive sequence impedance parameter of section CJ
 
 D   CJ   1 =cos  h (γ 3   dL   3 )
 
 B   CJ   1   =−Z   c3  sin  h (γ 3   dL   3 )
 
 Z   c3 =√{square root over (( r 3+ jωl 3)/( jωc 3))}
 
γ 3 =√{square root over (( r 3+ jωl 3)( jωc 3))}
   r3, l3 and c3 are resistance, inductance and capacitance per unit length of the section CJ.
           V C   1 , I C   1  are the positive sequence voltage and current from measurements at Bus C   
               

     And, D AJ   1  and B AJ   1  is the positive sequence impedance parameter of section AJ
 
 D   AJ   1 =cos  h (γ 1   dL   1 )
 
 B   AJ   1   =−Z   c1  sin  h (γ 1   dL   1 )
 
 Z   c1 =√{square root over (( r 1+ jωl 1)/( jωc 1))}
 
γ 1 =√{square root over (( r 1+ jωl 1)( jωc 1))}
         r1, l1 and c1 are resistance, inductance and capacitance per unit length of the section AJ,   I A   1  is the positive sequence current from measurements at Bus A       

     V Acalculated   1  is the positive sequence voltage calculated at Bus A. 
     Referring back to  FIG. 4 , the step  406  of calculating the voltage phasor for each terminal can be performed with the IED associated with the terminal (e.g. with IED  202 ), or with the phasor calculation module ( 304 ) of the device. 
     The method further comprises determining the section with the fault at  408 . The section of the mixed line with the fault is determined based on the comparison of the calculated and obtained voltage phasors for each terminal. 
     In an embodiment, determining the section with the fault comprises comparing the difference between the calculated and obtained voltage phasors for each terminal. For example, the difference between the calculated and obtained voltage phasors is compared with a threshold value (e.g. determined from system parameters such as grounding and fault resistance). 
     Consider a case where the difference for each terminal is less than a threshold (e.g. all three comparisons less than 0.05% of the system voltage). In such a case, the fault may be determined to be at the junction. 
     In an embodiment, the terminal for which the difference between the calculated and obtained voltage phasors is the lowest among all, can be identified as healthy or non-faulty sections, and conclude that other section as fault. For example, if the terminal A voltage calculated from terminal B is almost equal to the measured voltage at terminal A (difference is lowest), the fault is on section CJ (that is between terminal C and junction). 
     In another embodiment, the terminal for which the difference between the calculated and obtained voltage phasors is the highest among all, can be identified as the section with the fault. 
     As an example, the difference between the calculated and the obtained voltage phasors are calculated using the following equations (A.8) to (A.10):
 
[Δ V   B2A ]=| V   B_calculated   1   −V   B   1 |  (A.8)
 
[Δ V   C2B ]=| V   C_calculated   1   −V   C   1 |  (A.9)
 
[Δ V   A2C ]=| V   A_calculated   1   −V   A   1 |  (A.10)
 
     In case of the three terminal line shown in  FIG. 1 , the fault may be at the junction, or in section AJ, section BJ, or section CJ. In accordance with the example, consider the following cases. 
     Case 1: Fault at the Junction: 
     If the fault is at a section, the calculated voltages at all three terminals should be equal to the respective measured voltages. That is ΔV B2A , ΔV A2C  and ΔV C2B  should be equal to (or close to) zero. Hence, if ΔV B2A , ΔV A2C  and ΔV C2B  are less than a small threshold value (c), the fault is identified to be at the junction. 
     Case 2: Fault in Section AJ: 
     If the fault is in section AJ, V C_calculated   1  calculated from Bus B and Bus C measurements is equal to (or substantially equal to) the measured value V C   1 . That is, ΔV C2B  will be zero (or close to zero). 
     Case 3: Fault in Section BJ: 
     Similarly, if fault is in section BJ, V A_calculated   1  calculated from Bus C and Bus A measurements is equal to (or almost equal to) the measured value V A   1 . That is, V A2C  is zero (or close to zero). 
     Case 4: Fault in Section CJ: 
     Likewise, if the fault is in section CJ, V B_calculated   1  calculated from Bus A and B measurements is equal to (or almost equal to) the measured value V Bd   1 . That is, ΔV B2A  is zero (or close to zero). 
     In summary, for the above cases, the following conditions are true,
         If ΔV B2A , ΔV A2C  and ΔV C2B &lt;ϵ, then the fault is at the junction   If ΔV C2B  is minimum of ΔV C2B , ΔV A2C  and ΔV B2A , then section AJ (overhead line) has the fault   If ΔV A2C  is minimum of ΔV C2B , ΔV A2C  and ΔV B2A , then section BJ (overhead line) has the fault   If ΔV B2A  is minimum of ΔV C2B , V A2C  and ΔV B2A , then section CJ (underground cable) has the fault       

     In addition to the three comparisons shown in equations (A.8), (A.9) and (A.10), three more comparisons can be done to improve the robustness of the solution. 
     Equation (A.8) shows comparison of Bus B voltage calculated from Bus A to the measured value. In addition to this, Bus B voltage calculated from Bus C can also be calculated and compared to the measured value. 
     Similarly, Equation (A.9) shows comparison of Bus C voltage calculated from Bus B to the measured value. In addition to this, Bus C voltage calculated from Bus A can also be calculated and compared to the measured value. 
     Likewise, Equation (A.10) shows comparison of Bus A voltage calculated from Bus C to the measured value. In addition to this, Bus A voltage calculated from Bus B can also be calculated and compared to the measured value (Table 1) 
     
       
         
           
               
               
             
               
                 TABLE 1 
               
             
            
               
                   
               
               
                   
                 calculated from measured voltages at terminals 
               
            
           
           
               
               
               
               
            
               
                   
                 A 
                 B 
                 C 
               
               
                   
               
               
                 VA_calculated 
                   
                 ✓ 
                 ✓ 
               
               
                 VB_calculated 
                 ✓ 
                   
                 ✓ 
               
               
                 VC_calculated 
                 ✓ 
                 ✓ 
               
               
                   
               
            
           
         
       
     
     Hence, this would in total give six comparisons between measured and calculated voltages at all buses and the minimum of these can be used to identify the faulted section. 
     This is advantageous in cases where any of the buses have bad measurements. These redundant calculations help in obtaining the correct solution even when any of the buses have bad measurements or data synchronization issues. 
     Thus, by comparing the calculated and obtained voltage phasors for each terminal, the section with the fault can be identified. This step can be performed with the IED associated with the terminal (e.g. with IED  202 ), or with the fault section identification module ( 306 ) of the device. 
     The method further comprises controlling the switching device with a re-trip signal for protecting the mixed line at  410 . The re-trip signal is generated for controlling the associated switching device (e.g. circuit breaker) based on the determination of the section with the fault. The re-trip signal is associated with an auto-reclose function, and the re-trip signal is generated in response to determining that the section with the fault is an overhead line section (for example, section AJ or BJ shown in  FIG. 1 ). 
     In other words, the auto-reclose function is enabled only when it is determined that the fault is in an overhead line section, and not enabled (blocked) when it is determined that the fault is in an underground cable. This re-trip signal may be generated with an IED (e.g. IED at the first terminal) the IED associated with the terminal (e.g. with IED  202 ), or with the trip module ( 308 ) of the device. 
     The method may also be implemented with communication between a device associated with the mixed line, and a server. Here, some steps of the method may be performed with one or more processors of the server (e.g.  404 ,  406 ,  408 ,  410 ), while the others ( 412 ) are performed with one or more processors of the device. 
     Thus, the invention provides for selective auto-reclosing based on FSI for multi-terminal lines.