Patent Publication Number: US-2023140202-A1

Title: Startup protection for standby amplifiers

Description:
BACKGROUND 
     The present disclosure generally relates to computing systems and, more particularly, to reducing a startup voltage of a standby amplifier to reduce a breakdown of an input device of the standby amplifier. 
     Generally, a computing system includes a host sub-system and a memory sub-system. The memory sub-system may store data accessible to processing circuitry of the host sub-system. For example, to perform an operation, the processing circuitry may execute instructions retrieved from a memory device implemented in the memory sub-system. In some instances, input data for the operation may also be retrieved from the memory device. Additionally or alternatively, data output (e.g., resulting) from the operation may be stored in the memory device, for example, to enable subsequent retrieval. However, in some instances, operational efficiency of the computing system may be limited by the architecture of the memory sub-system and, in particular, to circuitry related to the column-select operation for retrieving data stored in the memory device. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Various aspects of the present disclosure may be better understood upon reading the following detailed description and upon reference to the drawings described below. 
         FIG.  1    is a simplified block diagram of an example of a computing system including a processing (e.g., host) sub-system and a memory sub-system, according to an embodiment of the present disclosure. 
         FIG.  2    is a schematic diagram of an example circuit of a standby amplifier of a memory device implemented in the memory sub-system of  FIG.  1   , according to an embodiment of the disclosure. 
         FIG.  3    is a schematic diagram of an example circuit for generating an enable signal for the standby amplifier of  FIG.  2   , according to an embodiment of the disclosure. 
         FIG.  4    is a schematic diagram of an example circuit for generating a reduced enable signal for the standby amplifier of  FIG.  2   , according to an embodiment of the disclosure. 
         FIG.  5    is a graph illustrating signal waveforms of the standby amplifier of  FIG.  2    using the example circuit of  FIG.  3   , according to an embodiment of the disclosure. 
         FIG.  6    is a graph illustrating signal waveforms of the standby amplifier of  FIG.  2    using the example circuits of  FIGS.  3  and  4   , according to an embodiment of the disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     The present disclosure provides apparatus and techniques that facilitate improved operating efficiency and/or operating performance of computing systems, for example, by reducing a voltage of an enable signal for a startup amplifier while minimizing an increase of a physical size of the computing system. 
     A computing system generally includes various computing sub-systems, such as a host (e.g., processing) sub-system and a memory sub-system. The host sub-system may include processing circuitry, for example, implemented in one or more processors and/or one or more processor cores. The memory sub-system may include one or more memory devices (e.g., chips or integrated circuits), for example, implemented on a memory module, such as a dual in-line memory module (DIMM), and/or organized to implement one or more memory arrays (e.g., banks of memory cells). 
     Generally, during operation of the computing system, processing circuitry implemented in the processing sub-system may perform various operations by executing instructions stored in the memory sub-system. For example, the processing sub-system may determine output data by executing a data processing operation based on input data. Additionally, a processing sub-system may generally include one or more registers and/or one or more processor-side caches, which provide storage locations directly accessible to the processing sub-system. However, storage capacity implemented in a processing sub-system is generally limited. 
     As such, the processing sub-system is often communicatively coupled to a memory sub-system via one or more memory buses (e.g., external communication, command, and/or data buses). In some cases, a computing system may include multiple memory buses, for example, each dedicated to different types of communication. For example, the computing system may include a memory command (e.g., control and/or request) bus dedicated to communication of command (e.g., control) signals indicative of memory access command (e.g., a memory read or write command), and a memory data bus dedicated to communication of data signals indicative of a data block to be stored (e.g., written) in a memory device of the memory sub-system (e.g., in response to a memory write command and/or a memory read command). 
     Moreover, in some instances, memory in a memory sub-system may be implemented using multiple different memory types. For example, the memory sub-system may include one or more volatile memory devices, such as a dynamic random-access memory (DRAM) device and/or a static random-access memory (SRAM) device, one or more non-volatile memory devices, such as a flash (e.g., NAND) memory device, a phase-change memory (e.g., 3D XPoint™) device, and/or a ferroelectric random access memory (FeRAIVI) device 
     The memory device(s) in a memory sub-system generally includes various amplifiers (e.g., regulators), including a standby amplifier and an active amplifier. The active amplifier may be a main amplifier of the memory device and may support a relatively large amount of current, for example during a read or write operation. The standby amplifier may be operational when there is no current demand or minimal current demand from the memory device. The standby amplifier may ensure that voltages in the memory device are maintained at a specified level when there is no or minimal current demand. A maximum current provided by the standby amplifier may be about ten to twenty percent of a maximum current of the active amplifier. For example, if a maximum current of the active amplifier is about five milliamps (mA), the standby amplifier may provide up to about 500 microamps (μA). The standby amplifier may be powered on at startup (e.g., power up) and during operation of a respective memory device. 
     Protection of memory devices and associated amplifiers may be critical during startup because voltages of the memory device may be in a meta-stable state. To protect a startup amplifier of the memory device, an input voltage (e.g., enable voltage) of the startup amplifier may be reduced. Embodiments presented herein provide apparatus and techniques to reduce a startup voltage of a standby amplifier to improve an operating performance and prolong a life of one or more components thereof. Further, the reduced startup voltage may be clamped to the standby amplifier only during the startup operation and thus may not affect the standby amplifier or memory device during a normal operation mode (e.g., after startup). 
       FIG.  1    is a simplified block diagram of an example of a computing system  10  (e.g., an apparatus), which includes a processing (e.g., host) sub-system  12  and a memory sub-system  14 , according to an embodiment of the present disclosure. It should be understood that the computing system  10  may include computing sub-systems not shown in  FIG.  1   , such as a networking sub-system, a communication sub-system, a radio frequency sub-system, a user input sub-system, a display sub-system, or a combination thereof. 
     In some embodiments, the computing system  10  may be implemented in a single electronic device, such as a desktop computer, a workstation computer, a laptop computer, a server, a mobile phone, a virtual-reality headset, and/or the like. In other embodiments, the computing system  10  may be distributed between multiple electronic devices. For example, the processing sub-system  12  and the memory sub-system  14  may be implemented in a host device while other computing sub-systems, such as the user input and/or display sub-systems, may be implemented in a client (e.g., remote) device. In some embodiments, a computing sub-system may be distributed between multiple electronic devices. For example, a first portion of the processing sub-system  12  and/or a first portion of the memory sub-system  14  may be implemented in a host device while a second portion of the processing sub-system  12  and/or a second portion of the memory sub-system  14  may be implemented in a client device. 
     As shown, the processing sub-system  12  may include processing circuitry  16 . The processing circuitry  16  may include one or more central processing units (CPUs), one or more graphics processing units (GPUs), one or more processor cores, or any combination thereof. During operation, the processing sub-system  12  may perform various operations such as determining output data by executing, via the processing circuitry  16 , instructions to perform a data processing operations based on input data. The processing sub-system  12  may also include one or more caches  22  which may be integrated with the processing circuitry  16 . The one or more caches  22  may provide storage locations directly accessible to the processing circuitry  16 . The processing sub-system  12  may be coupled to one or more memory controllers  28  via one or more buses  27  to control storage of the one or more caches  22 . 
     The memory sub-system  14  generally stores data accessible by the processing sub-system  12  via one or more memory devices  18 . The memory devices  18  may include integrated circuits or chips with one or more memory cells (e.g., circuitry) organized into one or more memory arrays and thus, may include one or more tangible, non-transitory, computer-readable media. For example, the memory sub-system  14  may include one or more dynamic random-access memory (DRAM) devices, one or more static random-access memory (SRAM) devices, one or more flash (e.g., NAND) memory devices, one or more phase-change memory (e.g., 3D XPoint™) memory devices, one or more ferroelectric random access memory (FeRAM), or any combination thereof. 
     In some embodiments, multiple memory devices  18  may be implemented on a memory module, such as a dual in-line memory module (DIMM) or a single in-line memory module (SIMM). For example, a memory module may include a printed circuit board (PCB) and multiple memory devices  18  each disposed on a flat or planar (e.g., front or back) surface of the printed circuit board. Additionally, the memory devices  18  may be coupled to external pins formed along an (e.g., bottom) edge of the printed circuit board via conductive traces formed on the printed circuit board. 
     It should be understood that one or more of the memory devices  18  may be implemented using other packing techniques. For example, the memory devices  18  may be coupled to a (e.g., silicon) interposer to implement a 2.5D configuration. Additionally or alternatively, the memory devices  18  may be stacked to implement a 3D configuration. Furthermore, in some embodiments, the memory devices  18  may be implemented using organic packaging techniques. In other words, the techniques described in the present disclosure may be implemented as an on-package solution. 
     The memory sub-system  14  also includes one or more memory caches  24 . Although implemented in the memory sub-system  14 , the memory cache  24  may nevertheless provide faster data communication compared to a memory array implemented in the memory devices  18 . For example, the memory cache  24  may be implemented with static random-access memory (SRAM) while the memory devices  18  may be implemented with dynamic random-access memory (DRAM). Additionally or alternatively, a memory cache  24  and a memory array implemented in the one or more memory devices  18  may utilize the same memory type (e.g., DRAM). In fact, in some embodiments, one or more of the memory caches  24  may be implemented in the memory devices  18 . To control storage of the one or more memory caches  24 , the memory sub-system  14  may be coupled to the one or more memory controllers  28  via the one or more buses  27 . 
     As shown, the processing sub-system  12  is communicatively coupled to the memory sub-system  14  via one or more memory buses  20 . The data buses  20  may include one or more cables, one or more wires, one or more conductive traces, one or more communication networks, or any combination thereof. Each of the one or more memory buses  20  may be dedicated to different communication types between the memory sub-system  14  and the processing sub-system  12 . For example, the memory buses  20  may include a memory command bus and a memory data bus. 
       FIG.  2    is a schematic diagram of an example circuit  50  of a standby amplifier  52  of a memory device  18  implemented in the memory sub-system  14  of  FIG.  1   , according to an embodiment of the disclosure. The example circuit  50  includes a protection circuit  54  coupled to the standby amplifier  52 . In some cases, the standby amplifier  52  may be referred to as a operational transconductance amplifier (OTA). In some cases, the standby amplifier may include the OTA  52  and the protection circuit  54 . The standby amplifier  52  includes transistors T 1 , T 2 , T 3 , and T 4 . The transistors T 1  and T 2  may form a first input pair of the standby amplifier  52  and the transistors T 3  and T 4  may form a second input pair of the standby amplifier  52 . The standby amplifier  52  may have a finite bandwidth and thus a gate voltage of the transistors T 1  and T 3  may increase slowly. 
     The protection circuit  54  includes transistors T 9  and T 10 . The transistors T 9  and T 10  may be enabled (e.g., closed) when an enable voltage En  58  is applied to a gate thereof via a node  56 . A larger enable voltage En  58  may close the transistors T 9  and T 10  more quickly and thus increase a voltage across the transistors T 1  and T 3  to a high voltage (e.g., VPP) more quickly. 
     The example circuit  50  also includes transistors T 5 , T 6 , T 7 , and T 8  coupled to the amplifier  52 . As shown, each of the transistors T 1 -T 10  may be n-channel transistors. It should be understood that the transistors T 1 -T 10  may be different types (n-channel or p-channel) and may be disposed in a different configuration than shown. In some cases, the standby amplifier  52  may provide up to about 500 microamps (μA). 
     In some embodiments, a maximum voltage of the transistor T 1  may be, for example, about 1.4 volts from drain-to-source, gate-to-drain, or gate-to-source. If one of those voltage measurements exceeds about 1.4 volts, the transistor T 1  may be damaged beyond repair and the standby amplifier  52  may no longer be operational. To prevent damage to the transistor T 1  (and the transistor T 3 ) and/or the standby amplifier  52 , the protection circuit  54  may ensure that a drain voltage of the transistor T 1  does not exceed a gate voltage of the transistor T 9  minus a threshold voltage V T  of the transistor T 9 . That is, a drain voltage of the transistor T 1  may be less than the enable voltage En  58  at a gate of the transistor T 9  minus the threshold voltage V T  of the transistor T 9 . The transistor T 10  may have a threshold voltage similar to that of the transistor T 9 . A drain voltage of the transistor T 3  may be the same or substantially similar to the drain voltage of the transistor T 9 . In this way, the transistors T 9  and T 10  of the protection circuit  54  may limit a voltage of the transistors T 1  and T 3  of the standby amplifier  52 . 
     At startup of the standby amplifier  52 , a gate voltage of the transistors T 1  and T 2  may be about 1 volt and a gate voltage of the transistors T 3  and T 4  may be zero volts. However, a drain of the transistors T 1  and T 3  may be a high voltage (e.g., about 2.2 volts). In that case, a voltage across the transistors T 1  and T 3  may be larger than the maximum voltage of about 1.4 volts. Thus, the transistors T 1  and/or T 3  may be damaged. 
     Embodiments disclosed herein present apparatus and techniques to reduce and/or limit the enable voltage En  58  supplied to the transistors T 1  and T 3  via the protection circuit  54  during a startup operation. Once the startup operation is complete, the enable voltage En  58  may return to a previous voltage level. Advantageously, the reduced enable voltage En  58  may reduce an occurrence of damage to components (e.g., transistors T 1 -T 4 ) of the standby amplifier  52  during the startup operation without impacting performance or operation thereafter. 
       FIG.  3    is a schematic diagram of an example circuit  80  for generating the enable signal for the standby amplifier  52  of  FIG.  2   , according to an embodiment of the disclosure. As shown, the circuit  80  may receive various inputs  82  and  88 - 94 . Specifically, an input of the circuit  80  may include a power up signal  90 . When the power up signal  90  is high (e.g., between about 1 volt and about 1.5 volts, such as about 1.2 volts), the enable voltage En  58  may be high (e.g., about 2 volts). The circuit  80  includes a number of components including a number of inverters  84 , switches  96 , a logical NOR gate  100 , and a logical NAND gate  102 . 
     The enable voltage En  58  is output from the example circuit  80  via an output node  120 . The enable voltage En  58  may be supplied to the protection circuit  54  via the node  56  as discussed with respect to  FIG.  2   . That is, the node  56  of the standby amplifier  52  may be coupled to the output node  120  of the circuit  80 . 
       FIG.  4    is a schematic diagram of an example circuit  150  for generating a reduced enable voltage EnDy  152  for the standby amplifier  52  of  FIG.  2   , according to an embodiment of the disclosure. The example circuit  150  is a voltage divider that generates a reduced enable voltage EnDy  152  from the enable voltage En  58 . That is, the voltage divider  150  receives the enable voltage En  58  via the node output  120  of the circuit  80  of  FIG.  3   . 
     In some embodiments, the voltage divider  150  may be a resistive divider. As shown, the voltage divider  150  includes a number of resistors R 1 -R 7 . In some embodiments, a resistance of each of the resistors R 1 -R 7  may be the same. For example, a resistance of each of the resistors may be about 30 kilo-ohms (kΩ). In other embodiments, the resistance of each resistor R 1 -R 7  may be different. In some cases, an area of each resistor R 1 -R 7  may be about 1 micrometer. 
     The reduced enable voltage EnDy  152  may be generated by tapping the voltage divider  150  between the resistors R 2  and R 3  via a switch  156 . Thus, the reduced enable voltage EnDy  152  may be about 30% less than the enable voltage En  58 . In some embodiments, the reduced enable voltage EnDy  152  may be about 15% less than the enable voltage En  58  by closing (or opening) the switch  156  such that the switch  156  taps the voltage divider  150  between the resistors R 1  and R 2 . 
     The reduced enable voltage EnDy  152  may be provided to the standby amplifier  52  until an inverse power up signal  154  transitions from a logic high voltage (e.g.,  1 ) to a logic low voltage (e.g.,  0 ). That is, the inverse power up signal  154  may be a logic high before the power up operation and until the power up operation is complete. When the power up operation is complete, the power up signal  90  may transition from a logic low to a logic high. That is, the logic high of the inverse power up signal  154  may close the transistor T 12  such that a current flows through the voltage divider  150  and the reduced enable voltage EnDy  152  is provided to the standby amplifier  52 . Once the power up operation is complete, the inverse power up signal  154  may transition from the logic high to the logic low, causing the transistor T 12  to open and stop current flowing through the resistors R 1 -R 7 . In that case, the enable voltage En  58  may be coupled to the protection circuit  54  after the power up operation is complete. In this way, the transistor T 12  may control a voltage level provided to the protection circuit  54  such that a reduced enable voltage (e.g., EnDy  152 ) may be provided to the protection circuit during the power up operation. 
     In this way, the voltage divider  150  may provide the reduced enable voltage EnDy  152  to the standby amplifier  52  to reduce an occurrence of damage to the standby amplifier  52  and/or components thereof during the startup operation. Upon completion of the startup operation, the voltage divider  150  may provide the enable voltage En  58  (e.g., not reduced) to the standby amplifier  52  to ensure normal operation. It should be understood that the voltage divider  150  is merely an example and that many other configurations including different layouts and/or more or fewer resistors are possible to obtain different values of the reduced enable voltage EnDy  152 . For example, the reduced enable voltage EnDy  152  may be generated by tapping the voltage divider  150  between different resistors than discussed above, such as between the resistors R 3  and R 4 . Advantageously, the reduced enable voltage EnDy  152  may reduce an occurrence of damage to one or more components of the standby amplifier  52  and thus, may prolong a lifespan of the components and/or the standby amplifier. 
       FIG.  5    is a graph  180  illustrating signal waveforms of the standby amplifier  52  of  FIG.  2    using the example circuit  80  of  FIG.  3   , according to an embodiment of the disclosure. As shown, the graph  180  includes the power up signal  90 , the enable voltage En  58 , a gate voltage  184  of the transistor T 1  or the transistor T 3  of  FIG.  2   , a drain voltage  186  of the transistor T 1  or the transistor T 3 , a gate to drain voltage (VGD)  188  across the transistor T 1  or the transistor T 3 , and an output voltage  190  of the standby amplifier  52 . 
     In operation, when the power up signal  90  transitions from low to high (e.g., from about 0 volts to about 1 volt), the gate to drain voltage (VGD)  188  across the transistor T 1  or the transistor T 3  increases to over 1.4 volts. That is, the gate to drain voltage (VGD)  188  across the transistor T 1  or the transistor T 3  exceeds the maximum voltage of the transistor T 1  or the transistor T 3 . Thus, during the power up operation, the transistor T 1  or the transistor T 3  may be damaged by the relatively high voltage. In some cases, the high voltage (e.g., greater than 1.4 volts) may be applied across the transistor T 1  or the transistor T 3  for a relatively long time period (e.g., between about 1 microsecond (μs) and about 4 μs), increasing the damage to the transistor T 1  or the transistor T 3 . 
     If the transistor T 1  or the transistor T 3  is not catastrophically damaged during a particular power up operation, the damage may be cumulative and thus the transistor T 1  or the transistor T 3  may be catastrophically damaged during a subsequent power up operation. As discussed above, embodiments herein present techniques to reduce the voltage supplied to the transistor T 1  or the transistor T 3  (and thus across the transistor T 1  or the transistor T 3 ) to substantially reduce an occurrence of damage caused thereby. 
       FIG.  6    is a graph  200  illustrating signal waveforms of the standby amplifier  52  of  FIG.  2    using the example circuits  80  and  150  of  FIGS.  3  and  4   , according to an embodiment of the disclosure. That is, the graph  200  illustrates signal waveforms using the voltage divider  150  to provide the reduced enable voltage EnDy  152  to the standby amplifier  52 . As shown, the enable voltage En of the standby amplifier  52  of  FIG.  2    is clamped to the reduced enable voltage EnDy  152  for a time period  204  during the power up operation of the standby amplifier  52 . As a result of the reduced enable voltage EnDy  152 , the gate to drain voltage (VGD)  188  across the transistor T 1  or the transistor T 3  may be reduced to about 1 volt. Once the power up operation is complete, the input voltage of the standby amplifier  52  may return to the enable voltage En  58  voltage level (e.g., when the power up signal  90  transitions from low to high and the inverse power up signal  154  transitions from high to low). 
     That is, the reduced enable voltage EnDy  152  maintains the gate to drain voltage (VGD)  188  below the maximum voltage (e.g., 1.4 volts) of the transistor T 1  or the transistor T 3 . In this way, the reduced enable voltage EnDy  152  may reduce an occurrence of damage to one or more components of the standby amplifier  52  and thus, may prolong a lifespan of the components and/or the standby amplifier. 
     One or more specific embodiments of the present disclosure are described herein and depicted in the corresponding figures. The described embodiments are merely examples of the presently disclosed techniques. Additionally, in an effort to provide a concise description of these embodiments, all features of an actual implementation may not be described in the specification. It should be appreciated that in the development of any such actual implementation, as in any engineering or design project, numerous implementation-specific decisions must be made to achieve the developers&#39; specific goals, such as compliance with system-related and business-related constraints, which may vary from one implementation to another. Moreover, it should be appreciated that such a development effort might be complex and time consuming, but may nevertheless be a routine undertaking of design, fabrication, and manufacture for those of ordinary skill having the benefit of this disclosure. 
     When introducing elements of various embodiments of the present disclosure, the articles “a,” “an,” and “the” are intended to mean that there are one or more of the elements. The terms “comprising,” “including,” and “having” are intended to be inclusive and mean that there may be additional elements other than the listed elements. Additionally, it should be understood that references to “one embodiment” or “an embodiment” of the present disclosure are not intended to be interpreted as excluding the existence of additional embodiments that also incorporate the recited features. 
     The specific embodiments described above have been shown by way of example, and it should be understood that these embodiments may be susceptible to various modifications and alternative forms. It should be further understood that the claims are not intended to be limited to the particular forms disclosed, but rather to cover all modifications, equivalents, and alternatives falling within the spirit and scope of this disclosure.