Patent Publication Number: US-8987784-B2

Title: Active area shaping of III-nitride devices utilizing multiple dielectric materials

Description:
The present application is a continuation-in-part of U.S. patent application Ser. No. 13/965,421, filed on Aug. 13, 2013, which itself is a continuation of U.S. patent application Ser. No. 13/721,573, filed on Dec. 20, 2012, which in turn is a continuation of U.S. patent application Ser. No. 12/008,190, filed on Jan. 9, 2008, which claims priority to U.S. provisional application 60/884,272, filed on Jan. 10, 2007. The present application claims the benefit of and priority to all of the above-identified applications; and the disclosures of all of the above-identified applications are hereby fully incorporated by reference into the present application. 
    
    
     BACKGROUND 
     I. Definitions 
     As used herein, the phrase “group III-V” refers to a compound semiconductor including at least one group III element and at least one group V element. By way of example, a group III-V semiconductor may take the form of a III-Nitride semiconductor. “III-Nitride”, or “III-N”, refers to a compound semiconductor that includes nitrogen and at least one group III element such as aluminum (Al), gallium (Ga), indium (In), and boron (B), and including but not limited to any of its alloys, such as aluminum gallium nitride (Al x Ga (1-x) , indium gallium nitride (In y Ga (1-x-y) N), aluminum indium gallium nitride (Al x In y Ga (1-x-y) N), gallium arsenide phosphide nitride (GaAs a P b N (1-a-b) ), aluminum indium gallium arsenide phosphide nitride (Al x In y Ga (1-x-y) As a P b N (1-a-b) , for example. III-Nitride also refers generally to any polarity including but not limited to Ga-polar, N-polar, semi-polar, or non-polar crystal orientations. A III-Nitride material may also include either the Wurtzitic, Zincblende, or mixed polytypes, and may include single-crystal, monocrystalline, polycrystalline, or amorphous structures. Gallium nitride or GaN, as used herein, refers to a III-Nitride compound semiconductor wherein the group III element or elements include some or a substantial amount of gallium, but may also include other group III elements in addition to gallium. 
     II. Background Art 
     A III-nitride heterojunction semiconductor device can include a III-nitride heterojunction having a first III-nitride body of one bandgap and a second III-nitride body of another bandgap formed over the first III-nitride body. The composition of the first and second III-nitride bodies are selected to cause the formation of a carrier rich region referred to as a two-dimensional electron gas (2DEG) at or near the III-nitride heterojunction. The 2DEG can serve as a conduction channel between a first power electrode (e.g. a source electrode) and a second power electrode (e.g. a drain electrode). 
     The III-nitride heterojunction semiconductor device can also include a gate electrode disposed between the first and second power electrodes to selectively interrupt or restore the 2DEG therebetween, whereby the device may be operated as a switch. The gate electrode may be received by a trench that extends through a passivation body. The trench in which the gate electrode is received includes vertical sidewalls that form sharp bottom corners in the gate electrode. This can result in high electric field regions at the bottom corners of the gate electrode, as well as an increase in the overlap between the gate electrode and the 2DEG. 
     SUMMARY 
     Active area shaping of III-nitride devices utilizing multiple dielectric materials, substantially as shown in and/or described in connection with at least one of the figures, and as set forth more completely in the claims. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1A  presents a cross-sectional view of a portion of an exemplary III-nitride semiconductor device, in accordance with one implementation of the present disclosure. 
         FIG. 1B  presents an enhanced cross-sectional view of a portion of an exemplary III-nitride semiconductor device, in accordance with one implementation of the present disclosure. 
         FIG. 2  shows a flowchart illustrating an exemplary method for fabricating a III-nitride semiconductor device, in accordance with one implementation of the present disclosure. 
         FIG. 3A  illustrates a cross-sectional view, which includes a portion of an exemplary wafer processed according to an implementation disclosed in the present application. 
         FIG. 3B  illustrates a cross-sectional view, which includes a portion of an exemplary wafer processed according to an implementation disclosed in the present application. 
         FIG. 3C  illustrates a cross-sectional view, which includes a portion of an exemplary wafer processed according to an implementation disclosed in the present application. 
         FIG. 4  presents a cross-sectional view of a portion of an exemplary III-nitride semiconductor device, in accordance with one implementation of the present disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     The following description contains specific information pertaining to implementations in the present disclosure. The drawings in the present application and their accompanying detailed description are directed to merely exemplary implementations. Unless noted otherwise, like or corresponding elements among the figures may be indicated by like or corresponding reference numerals. Moreover, the drawings and illustrations in the present application are generally not to scale, and are not intended to correspond to actual relative dimensions. 
       FIG. 1A  presents a cross-sectional view of a portion of an exemplary III-nitride semiconductor device, in accordance with one implementation of the present disclosure. In  FIG. 1A , III-nitride semiconductor device  100  is a transistor (e.g. a high-electron-mobility transistor), and may be an enhancement mode or depletion mode transistor. III-nitride semiconductor device  100  includes substrate  102 , buffer layer  104 , III-nitride heterojunction  106 , dielectric body  108 , gate arrangement  110 , and ohmic electrodes  112   a  and  112   b.    
     In the present implementation, buffer layer  104  includes AlN, by way of example, and is formed over substrate  102 . Substrate  102  is a silicon substrate in the present implementation, however other substrate materials can be utilized. III-nitride semiconductor device  100  can include other layers not specifically shown in  FIG. 1A , such as transition layers configured to manage stress between substrate  102  and III-nitride body  114 . Other examples include spacer layers and cap layers. 
     III-nitride heterojunction  106  is formed over buffer layer  104  and includes III-nitride body  116  situated over III-nitride body  114  to form a two-dimensional electron gas (2DEG)  118 . III-nitride body  114  may also be referred to as a channel layer and III-nitride body  116  may also be referred to as a barrier layer, as shown in  FIG. 1A . The composition of III-nitride bodies  114  and  116  are selected to cause formation 2DEG  118 , which is rich in carriers and forms a conduction channel between ohmic electrodes  112   a  and  112   b . III-nitride body  114  includes semiconductor material of one bandgap, and III-nitride body  116  includes semiconductor material of another bandgap. In the present implementation, III-nitride body  114  includes GaN and III-nitride body  116  includes AlGaN. However, other semiconductor materials may be utilized, such as other group III-V semiconductor materials (e.g. III-Nitride materials). 
     Also in  FIG. 1A , ohmic electrodes  112   a  and  112   b  are ohmically coupled to III-nitride body  116  and are thereby electrically coupled to 2DEG  118 . Ohmic electrodes  112   a  and  112   b  extend through dielectric body  108  to contact III-nitride body  116 . As shown, ohmic electrodes  112   a  and  112   b  are optionally situated in respective trenches in dielectric body  108 . In III-nitride semiconductor device  100 , ohmic electrode  112   a  is a source electrode and ohmic electrode  112   b  is a drain electrode. 
     Also in the present implementation, dielectric body  108  is situated over III-nitride heterojunction  106  and includes dielectric layer  108   a  of a first dielectric material and dielectric layer  108   b  of a second dielectric material different than the first dielectric material. Dielectric body  108  is configured to passivate III-nitride body  116 . As such, dielectric body  108  can be referred to as a passivation body in some implementations. In one implementation, dielectric layer  108   a  is an oxide and dielectric layer  108   b  is a nitride. In another implementation, dielectric layer  108   a  is a nitride and dielectric layer  108   b  is an oxide. Silicon Oxide (SiO 2 ) is an example of a material suitable for the oxide and silicon nitride (Si x N y ) is an example of a material suitable for the nitride. Although not shown in  FIG. 1A , dielectric body  108  can include one or more additional dielectric layers. The one or more additional dielectric layers can be of a third dielectric material different than the first or second dielectric materials. However, in one implementation, an additional dielectric layer is situated over dielectric layer  108   b  and is of the first dielectric material. In some implementations, dielectric body  108  alternates between dielectric layers of the first and second dielectric materials. 
     Gate well  120  is defined by dielectric body  108  and extends through dielectric body  108  to contact III-nitride layer  116 . As shown, gate well  120  is formed in dielectric body  108  and is defined by dielectric layers  108   a  and  108   b  of dielectric body  108 . Referring now to  FIG. 1B ,  FIG. 1B  presents an enhanced cross-sectional view of the portion of the exemplary III-nitride semiconductor device shown in  FIG. 1A .  FIG. 1B  shows gate well  120  being of width  130   a  defined by dielectric layer  108   a , and being of width  130   b  defined by dielectric layer  108   b.    
     As shown in  FIG. 1B , width  130   a  is defined by opening  132   a  in dielectric layer  108   a . Furthermore, width  130   b  is defined by opening  132   b  in dielectric layer  108   b . In the present implementation ledges  136   a  and  138   a  of dielectric layer  108   a  define width  130   a  of gate well  120  as well as opening  132   a . Also, sidewalls  136   b  and  138   b  of dielectric layer  108   b  define width  130   b  of gate well  120  as well as opening  132   b . Width  130   b  is greater than width  130   a , such that gate well  120  expands in width away from III-nitride heterojunction  106 . Thus, opening  132   b  in dielectric layer  108   h  is wider than opening  132   a  in dielectric layer  108   a.    
     Gate arrangement  110  has gate electrode  122  situated in gate well  120 . Gate electrode  122  is disposed between ohmic electrodes  112   a  and  112   b  and is configured to selectively modulate 2DEG  118 , whereby III-nitride semiconductor device  100  may be operated as a switch. Gate electrode  122  can make Schottky contact with III-nitride heterojunction  106 . However, in the present implementation, gate arrangement  110  includes gate dielectric  124 , such that gate electrode  122  makes capacitive contact with III-nitride heterojunction  106 . Gate dielectric  124  is situated in and lines gate well  120 . Suitable materials for gate dielectric  124  include silicon nitride (Si x N y ) and/or other suitable gate dielectric material or materials. 
     In gate arrangement  110 , gate electrode  122  is integrated with at least one field plate. For example,  FIG. 1A  shows gate electrode  122  as being integrated with field plates  134   a  and  134   b . Field plates  134   a  and  134   b  are situated over dielectric layer  108   a . Gate dielectric  124  and/or any of field plates  134   a  and  134   b  can optionally extend out from gate well  120 , as shown in  FIGS. 1A and 1B . Thus, as shown, field plates  134   a  and  134   b  are also situated over dielectric layer  108   b . Also, a side of gate well  120  without a corresponding field plate may be substantially parallel to an adjacent side of gate electrode  122 , as no ledge is required. 
     Field plate  134   a  is situated between gate electrode  122  and ohmic electrode  112   a,  which is a source electrode. Thus, field plate  134   a  may be referred to as a source-side field plate. Field plate  134   b  is situated between gate electrode  122  and ohmic electrode  112   b , which is a drain electrode. Thus, field plate  134   b  may be referred to as a drain-side field plate. It is noted that various implementations may include only one of field plates  134   a  and  134   b.    
     Gate electrode  122  is situated in opening  132   a  in dielectric layer  108   a , and field plates  134   a  and  134   b  are situated in opening  132   b  in dielectric layer  108   b . In the implementation shown, gate arrangement  110  fills opening  132   a  in dielectric layer  108   a  and opening  132   b  in dielectric layer  108   b . More particularly, gate electrode  122 , field plates  134   a  and  134   b , and optionally gate dielectric  124  collectively fill gate well  120 . By integrating field plates  134   a  and  134   b  with gate electrode  122 , overlap between gate electrode  122  and 2DEG  118  can be decreased thereby reducing gate-drain charge (Qgd) for III-nitride semiconductor device  100 . Furthermore, field plates  134   a  and  134   b  alleviate high electric fields that would otherwise form from sharp corners of gate electrode  122 , thereby increasing breakdown voltage of III-nitride semiconductor device  100 . 
     In some implementations, one of the ledges, for example, ledge  138   a  that is closer to ohmic electrode  112   b  (e.g. a drain electrode) may be wider than ledge  136   a , which is closer to ohmic electrode  112   a  (e.g. a source electrode). The width of each ledge is in the lateral dimension inside gate well  120 . Doing so can further improve breakdown voltage of III-nitride semiconductor device  100 . Ledge  138   a  can be between approximately 2 to approximately 4 times as wide as ledge  136   a , by way of example. In the implementation shown, ledge  136   a  is approximately 0.025 μm wide and ledge  138   a  is between approximately 0.05 μm to 0.1 μm wide. As a result, field plate  134   b  may be wider than field plate  134   a , as shown. The portion of field plate  134   b  over only dielectric layer  108   a  of dielectric body  108  is wider than the portion of field plate  134   a  over only dielectric layer  108   a  of dielectric body  108 . However, the portion of field plate  134   b  over both dielectric layers  108   a  and  108   b  can also be wider than the portion of field plate  134   a  over both dielectric layers  108   a  and  108   b.    
       FIG. 2  shows a flowchart illustrating an exemplary method for fabricating a III-nitride semiconductor device, in accordance with one implementation of the present disclosure. The approach and technique indicated by flowchart  200  are sufficient to describe at least one implementation of the present disclosure, however, other implementations of the disclosure may utilize approaches and techniques different from those shown in flowchart  200 . Furthermore, while flowchart  200  is described with respect to  FIGS. 3A ,  3 B, and  3 C, disclosed inventive concepts are not intended to be limited by specific features shown and described with respect to  FIGS. 3A ,  3 B, and  3 C. Furthermore, with respect to the method illustrated in  FIG. 2 , it is noted that certain details and features have been left out of flowchart  200  in order not to obscure discussion of inventive features in the present application. Furthermore, implementations illustrated by flowchart  200  are performed on a processed wafer, which, includes, amongst other things, a substrate, a III-nitride heterojunction, and a buffer layer, and or other features, such as transition layers and/or spacer layers. The wafer may also be referred to as a semiconductor die or simply a die in the present application. 
     Referring now to flowchart  200  of  FIG. 2  and  FIG. 3A , flowchart  200  includes forming a dielectric body over a III-nitride heterojunction, the dielectric body including at least a first dielectric layer and a second dielectric layer ( 270  in  FIG. 2 ). As shown in  FIG. 3A , structure  370  includes substrate  302 , buffer layer  304 , III-nitride heterojunction  306 , and dielectric body  308  corresponding respectively to substrate  102 , buffer layer  104 , III-nitride heterojunction  106 , and dielectric body  108  in  FIGS. 1A and 1B  during fabrication of III-nitride semiconductor device  100 . III-nitride heterojunction  306  includes III-nitride bodies  314  and  316  corresponding respectively to III-nitride bodies  114  and  116  in  FIGS. 1A and 1B  during fabrication of III-nitride semiconductor device  100 . 
     In forming structure  370 , buffer layer  304 , such as AlN, can be grown over substrate  302  such as a silicon substrate, a silicon carbide substrate, a sapphire substrate, or the like. Buffer layer  304  may not be necessary if substrate  302  is compatible with III-nitride body  314 . As one example, buffer layer  304  may not be necessary if substrate  302  is a GaN substrate. After buffer layer  304  is formed, III-nitride body  314 , for example, GaN, can be grown over buffer layer  304 , followed by growth of III-nitride body  316 , for example, AlGaN, to obtain 2DEG  318 , corresponding to 2DEG  118  in  FIGS. 1A and 1B . 
     Thereafter, dielectric body  308  is formed over III-nitride heterojunction  306 , buffer layer  304 , and substrate  302 . Dielectric body  308  includes at least dielectric layer  308   a  and dielectric layer  308   b  corresponding respectively to dielectric layer  108   a  and dielectric layer  108   b  in  FIGS. 1A and 1B  during fabrication of III-nitride semiconductor device  100 . Forming dielectric body  308  can include growing or depositing dielectric layer  308   a  of a first dielectric material over III-nitride heterojunction  306  and growing or depositing dielectric layer  308   b  of a second dielectric material over dielectric layer  308   a.    
     The first and second dielectric materials can optionally be different dielectric materials, such as in the present implementation. For example, the first and second dielectric materials can be selected such that an enchant capable of removing portions of dielectric layer  308   b  does not remove portions of dielectric layer  308   a  (i.e. the enchant is selective to dielectric layer  308   b ). Examples of suitable materials for dielectric layer  308   a  include field dielectrics, such as AlN and Si x N y . Dielectric layer  308   a  can be approximately 0.05 μm to approximately 0.1 μm thick, by way of example. 
     Referring now to flowchart  200  of  FIG. 2  and  FIG. 3B , flowchart  200  includes forming a first opening in the first dielectric layer of the dielectric body and a second opening in the second dielectric layer of the dielectric body ( 272  in  FIG. 2 ). As shown in  FIG. 3B , structure  372  includes opening  340   a  in dielectric layer  308   a  and opening  340   b  in dielectric layer  308   b.    
     In forming structure  372 , mask  342  (e.g. a photoresist mask) can be deposited over dielectric body  308  of structure  370 . Mask  342  can be patterned (e.g. utilizing photolithography) to form opening  340   c  over dielectric body  308 . Thereafter, openings  340   a  and  340   b  can be formed in dielectric layers  308   a  and  308   b  by etching through dielectric layers  308   a  and  308   b . The etch is isotropic in some implementations. Thus, openings  340   a  and  340   b  may form substantially vertical sidewalls in dielectric body  308 , as shown. 
     Referring now to flowchart  200  of  FIG. 2  and  FIG. 3C , flowchart  200  includes expanding the second opening in the second dielectric layer of the dielectric body to be wider than the first opening in the first dielectric layer of the dielectric body ( 274  in  FIG. 2 ). As shown in  FIG. 3B , structure  374  opening  332   b  in dielectric layer  308   b  of dielectric body  308  is wider than and opening  332   a  in dielectric layer  308   a  of dielectric body  308 . 
     In forming structure  374 , mask  342  can be removed from structure  372 , and a second mask and a second etch can be utilized to remove portions of dielectric layer  308   b  from the substantially vertical sidewalls formed in dielectric body  308 . In doing so, gate well  320  can be formed corresponding to gate well  120  in  FIGS. 1A and 1B . Thus, openings  332   a  and  332   b  can correspond respectively to openings  132   a  and  132   b  in  FIGS. 1A and 1B . Subsequently, gate dielectric  124 , gate electrode  122 , and ohmic electrodes  112   a  and  112   b  may be formed so as to result in III-nitride semiconductor device  100  in  FIGS. 1A and 1B . The second mask can be offset from the center opening  340   c  in mask  342  so that one of ledges  136   a  and  138   a  is wider than the other of ledges  136   a  and  138   a.    
     As dielectric layer  308   a  includes a first dielectric material that is different than a second dielectric material of dielectric layer  308   b , the second etch can be selective to dielectric layer  308   b . As such, opening  340   a  of  FIG. 3B  can be substantially identical to opening  332   a  of  FIG. 3C . 
     As an alternative, a single etch may be performed on structure  370  of  FIG. 3A  by utilizing an enchant, which etches dielectric layers  308   a  and  308   b  at different rates (i.e. etches dielectric layer  308   b  faster than dielectric layer  308   a ) to obtain structure  374  of  FIG. 3C . As dielectric layer  308   a  includes a first dielectric material that is different than a second dielectric material of dielectric layer  308   b , the single etch can occur at different rates on dielectric layers  308   a  and  308   b . As such, the second mask and etch may be avoided. Thus, it will be appreciated that  272  and  274  in flowchart  200  of  FIG. 2  can be concurrent, in some implementations. Such implementations may still include forming mask  342  of  FIG. 3B  with opening  340   c , as described above. 
     While in implementations described above gate dielectric  124  is formed in gate well  120 , in other implementations, gate well  120  is formed over gate dielectric  124 . Referring now to  FIG. 4 ,  FIG. 4  presents a cross-sectional view of a portion of an exemplary III-nitride semiconductor device, in accordance with one implementation of the present disclosure. 
     In III-nitride semiconductor device  400 , substrate  402 , buffer layer  404 , III-nitride heterojunction  406 , dielectric body  408 , ohmic electrodes  412   a  and  412   b , gate well  420 , and gate electrode  422  correspond respectively to substrate  102 , buffer layer  104 , III-nitride heterojunction  106 , dielectric body  108 , ohmic electrodes  112   a  and  112   b , gate well  120 , and gate electrode  122  in  FIGS. 1A and 1B . Thus, III-nitride semiconductor device  400  can be similar to Ill-nitride semiconductor device  100  in  FIGS. 1A and 1B . However, in gate arrangement  410  of III-nitride semiconductor device  400 , gate dielectric  442  is situated below gate well  420 . As one example, III-nitride semiconductor device  400  can be fabricated similar to III-nitride semiconductor device  100  by forming gate dielectric  442  over III-nitride heterojunction  406  prior to  270  in flowchart  200  of  FIG. 2 . 
     Thus, as described above with respect to  FIGS. 1A ,  1 B,  2 ,  3 A,  3 B,  3 C, and  4 , implementations of the present disclosure utilize multiple dielectric layers to allow for III-nitride semiconductor devices with decreased overlap between a gate electrode and 2DEG, thereby reducing Qgd. Furthermore, high electric fields that would otherwise form from sharp corners of the gate electrode can be alleviated, thereby increasing breakdown voltage of the III-nitride semiconductor device. As such, the active area of the III-nitride semiconductor device can be shaped so as to enhance device performance. 
     From the above description it is manifest that various techniques can be used for implementing the concepts described in the present application without departing from the scope of those concepts. Moreover, while the concepts have been described with specific reference to certain implementations, a person of ordinary skill in the art would recognize that changes can be made in form and detail without departing from the scope of those concepts. As such, the described implementations are to be considered in all respects as illustrative and not restrictive. It should also be understood that the present application is not limited to the particular implementations described above, but many rearrangements, modifications, and substitutions are possible without departing from the scope of the present disclosure.