Patent Publication Number: US-2021164097-A1

Title: Oxidation resistant protective layer in chamber conditioning

Description:
CLAIM OF PRIORITY 
     This patent application claims the benefit of priority to U.S. Provisional Patent Application Ser. No. 62/595,948, filed on Dec. 7, 2017, which is hereby incorporated by reference herein in its entirety. 
    
    
     FIELD 
     The present disclosure relates generally to process and conditioning cycles in wafer processing chambers and in particular to defect reduction and batch size extension by utilizing oxidation resistant protective layers in wafer processing and chamber conditioning operations. 
     BACKGROUND 
     The background description provided here is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure. 
     Over time, repeated wafer processing cycles in a processing chamber can cause films of various types to accumulate on the chamber walls. As film levels increasingly build on components within the reaction chamber, film stresses can increase and adhesion between the accumulated film and the surface of the chamber can deteriorate significantly over time. This loss of adhesion can lead to portions of the accumulated film flaking off the chamber walls. When there is excessive film accumulation inside the chamber, the accumulated film does not adhere well to the chamber walls and it starts to peel off. Flakes and portions of peeled film can fall on to a wafer in the processing chamber and manifest itself as particles or defects. In some instances, oxygen-rich plasma exacerbates film flaking as, firstly, it can cause the accumulated film to shrink, resulting in higher tension, and secondly, it can consume carbon species in the accumulated film and thus cause further deterioration in film adhesion. 
     SUMMARY 
     In some examples, a method for conditioning a wafer processing chamber comprises setting a pressure in the chamber to a predetermined pressure range; setting a temperature of the chamber to a predetermined temperature; supplying a process gas mixture to a gas distribution device within the chamber, wherein the process gas mixture includes a gas including at least an oxygen species, and a helium or argon gas; striking a plasma within the chamber; monitoring a condition in the chamber; based on a detection of the monitored condition meeting or transgressing a threshold value, implementing a chamber conditioning operation, wherein the chamber conditioning operation comprises: depositing a preconditioning film onto an internal surface of the chamber, depositing a silicon oxycarbide (SiCO) film onto the preconditioning film, and depositing a protective layer onto the SiCO film. 
    
    
     
       DESCRIPTION OF THE DRAWINGS 
       Some embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings: 
         FIG. 1  is a schematic diagram of a wafer processing chamber, within which some example methods of the present disclosure may be employed. 
         FIG. 2  illustrates a table of results of film shrinkage and stress, according to some example embodiments. 
         FIGS. 3A-3B  illustrate comparison graphs of measured defect performance, according to some example embodiments. 
         FIG. 4  is a sectional view of a composite protective layer, according to an example embodiment. 
         FIG. 5  is a flow chart depicting operations in a method, according to an example embodiment. 
     
    
    
     DESCRIPTION 
     The description that follows includes systems, methods, techniques, instruction sequences, and computing machine program products that embody illustrative embodiments of the present invention. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of example embodiments. It will be evident, however, to one skilled in the art that the present inventive subject matter may be practiced without these specific details. 
     Portions of the disclosure of this patent document may contain material that is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the Patent and Trademark Office patent files or records, but otherwise reserves all copyright rights whatsoever. The following notice applies to any data as described below and in the drawings that form a part of this document: Copyright Lam Research Corporation, 2018, All Rights Reserved. 
     By way of background, a wafer processing chamber (such as a Striker Carbide™ processing chamber) can permit remote plasma chemical vapor deposition (RPCVD) technology to produce highly conformal silicon carbide films. Some highly conformal silicon carbide films are known as SPARC™ films. At various times during cycles of wafer processing in a chamber, a chamber cleaning or conditioning operation may be required. A chamber clean may be required when on-wafer defect performance is out of specification. As referenced above, if film accumulation within a chamber is too high, the accumulated film may begin to flake off and deposit particles on a processed wafer. This can lead to high levels of defects in the chips and devices made from wafers processed in the chamber. A chamber cleaning operation can remove some or all of the accumulated film to render defect performance back into specification again. 
     After a chamber clean, a thin layer of oxide film (also known as a preconditioning film) is typically deposited on one or more inner surfaces of a processing chamber using atomic layer deposition (ALD) followed by the deposition of another thin layer of silicon oxycarbide (SiCO) film using RPCVD. In some instances, accumulated film thicknesses within a chamber are comprised solely of SiCO. As SiCO films are prone to becoming oxidized, further film deposition on a wafer being processed within the chamber by an oxygen-rich plasma exacerbates the oxidation issue. The application of a SiCO film after cleaning therefore does not necessarily cure the problem of defect performance degradation. In other words, the “defect performance” of a processing chamber, or its ability to prevent defects from occurring in wafers processed within it, can become increasingly compromised over time. 
     In other conventional approaches, prior to deposition of a SPARC™ film on a wafer, a wafer preconditioning operation may be performed to modify surface conditions of the substrate (wafer) when applying the SPARC™ film to a wafer. A wafer preconditioning step may include for example the application to the wafer surface of an initiation layer and a surface treatment thereof. But even during this wafer preconditioning operation, film layers on the chamber surfaces can still be attacked by the oxygen-rich plasma. The plasma can reduce the thickness of the preconditioning film on the chamber surface as well as other accumulated film layers on the chamber surfaces. A reduction in thickness, or shrinkage, can cause the “stress” of an accumulated film on a chamber surface (including for example the chamber walls and showerhead) to become more tensile in nature, while adhesion of the preconditioning film to subsequent layers can itself be compromised for similar reasons. These shrinkage and stress effects can lead to early failure of wafer performance, impaired chamber defect performance, higher on-wafer defect occurrence, and reduced batch sizes through the rejection of defective chips or other devices sourced from compromised wafers. 
     In some examples of the present disclosure, the problems discussed above are addressed by implementing periodic chamber conditioning creating a high-carbon-content and oxidation-resistant protective layer on the chamber surfaces to compensate for film stress and mitigate the effects of an oxygen-rich plasma attack on a preconditioning film. Example triggers for chamber conditioning may include but are not limited to a detected deterioration in defect performance level approaching or meeting a threshold value, or a detected accumulated film stress level approaching or meeting a threshold value. In some examples, a threshold value may be associated with a thickness of an accumulated film within the chamber is within a range from 0.05 to 0.5 μm (microns). 
     In some examples, a protective layer is formed on surfaces of a chamber by chemical vapor deposition (CVD). Example chemicals used in the deposition reaction include silicon-containing species such as silane and disilane, oxygen-containing species such as oxygen and carbon dioxide, and a diluting gas such as argon or helium. The reaction may occur at a pressure ranging from 0.1 to 10 Torr, and at a temperature ranging from 100° C. to 600° C. When a threshold chamber film accumulation (for example, a thickness in a range 0.05 to 0.5 μm) is reached, the chamber stops processing further wafers. In some examples, the stop in processing may occur automatically upon detection of the threshold accumulation thickness. In some examples, a processing chamber is further configured thereafter to commence deposition of a protective layer without a wafer supported inside the processing chamber. A thickness of a protective layer may vary based on a type of wafer process. Example thicknesses may fall within a range of 50 nanometers (nm) and 1 micron (μm). In some examples, after an initial protective layer is deposited on surfaces of the processing chamber, the processing chamber may continue to process wafers until the chamber film accumulation increases to a further threshold thickness, for example a doubling in thickness. Other thresholds are possible. As the further threshold is met or approached, a protective layer may again be deposited onto the initial layer to maintain the defect performance of the chamber within a given specification. In some examples, a cycle of depositing protective layers continues until a composite protective film is formed. In some examples, the creation of a composite protective film continues until an outer layer thereof is unable to adhere to the composite film, or until a breakdown of the outer layer is unable to prevent the initial film previously applied to the inner surface of the chamber from peeling off and causing on-wafer defects and other problems in the manner discussed above. 
     A sectional view of an example protective layer with layers of film elements generally labeled  400  is shown in  FIG. 4 . The protective layer  400 A-N in this example is formed over a preconditioning film  404  formed on a surface  402  of a chamber wall. The illustrated protective layer  400 A-N forms a composite protective layer in this example and will hereinafter be referred to as a composite protective film, for clarity. Other examples of composite protective film and layers within them are possible. The composite protective film  400 A-N may be formed over time for example by performing one or more of the operations described further above. The composite protective film  400 A-N may include repeating or alternating pairs of SiCO and protective layers, as illustrated for example by the successive layers  400 A through  400 N. The formation of paired SiCO and protective layers may be cycled repetitively to extend the composite protective film  400  until a threshold for a monitored chamber condition is reached. An example threshold may be a thickness of the composite protective film, for example as shown by an outer surface of paired layers  400 N. 
     In some examples, in order to improve the defect performance (i.e. minimize wafer defects) of a processing chamber, such as a Striker Carbide™ chamber, a protective layer is created on one or more chamber surfaces to minimize film damage arising from preconditioning operations. Once a certain film accumulation in the reaction chamber is detected based, for example, on one or more of the threshold values discussed above, a protective layer comprising a high carbon content SiCO film is deposited on one or more chamber surfaces. In some examples, the inherent stress of a protective layer is compressive in nature, therefore it may compensate fully or in part any tensile stress induced in a previously-applied preconditioning film by an oxygen-rich plasma, or by a shrinkage in a preconditioning film thickness. Such film stress reduction or shrinkage compensation may be helpful in suppressing film cracking and flaking induced by high tensile stress. 
     In some examples, a protective layer may further serve as a sacrificial layer to protect against the effects of an oxygen-rich plasma attack due to a presence of excess carbon atoms in the protective layer. The excess carbon atoms are consumed sacrificially by the oxygen-rich plasma. As a result, the carbon content of the remaining preconditioning film inside the reaction chamber may be similar, for example, to a SPARC™ film having known excellent adhesion qualities and defect performance. By virtue of the methods and systems of the present disclosure, the defect performance of a processing chamber, such as a Striker Carbide™ processing chamber can be significantly improved and maintained. Further, an improved chamber process as described herein can yield batch sizes 250% larger than conventional examples. Some examples facilitate film deposition at high deposition rates, for example deposition rates in a range from 50 to 500 Angstrom (A)/min for a high-carbon protective layer. Some example high-carbon protective layers include carbon in an amount between 30% and 45% by weight. Some example protective layers are of a relatively low required thickness and the impact on production throughput by creating such a protective layer is therefore minimal. Tests conducted using the methods described herein indicate that batch sizes can be improved in some examples by 250% while maintaining a satisfactory defect performance of the processing chamber that made them. 
     An example chamber in which some example operations of the present disclosure may be employed, with appropriate chamber modifications for film deposition and control testing, is shown in  FIG. 1  of the accompanying drawings. A plasma etching (or deposition) apparatus comprises a reactor in which there is a chamber through which reactive gas or gases flow. Within the chamber, the gases are ionized into a plasma, typically by radio frequency energy. The highly reactive ions of the plasma gas are able to react with material, such as a polymer mask on a surface of a semi-conductor wafer being processed into Integrated Circuits (IC&#39;s). The plasma gas, such as an oxygen-rich plasma gas, may react with other materials in the chamber such as preconditioning or protective films in the manner described above. 
     Prior to etching, the wafer is placed in the chamber and held in proper position by a chuck or holder which exposes a top surface of the wafer to the plasma gas. There are several types of chucks known in the art. The chuck provides an isothermal surface and serves as a heat sink for the wafer. In one type, a semiconductor wafer is held in place for etching by mechanical clamping means. In another type of chuck, a semiconductor wafer is held in place by electrostatic force generated by an electric field between the chuck and wafer. The present methods are applicable to both types of chucks. 
       FIG. 1  illustrates an example capacitively-coupled plasma processing chamber  100 , representing an exemplary plasma processing chamber of the types typically employed to etch or make a film deposition on a substrate. A chuck  102  represents an example workpiece holder on which a substrate, such as a wafer  104 , may positioned during etching or deposition. The chuck  102  may be implemented by any suitable chucking technique, e.g., electrostatic, mechanical, clamping, vacuum, or the like. During etching, the chuck  102  is typically supplied with dual RF frequencies (a low frequency and high frequency), for example 2 MHz and 27 MHz, simultaneously during etching by a dual frequency source  106 . 
     An upper electrode  108  is located above the wafer  104 . The upper electrode  108  is grounded.  FIG. 1  illustrates an etching reactor where the surface of the upper electrode  108  is larger than the surface of the chuck  102  and the wafer  104 . During etching, plasma  110  is formed from etchant source gas supplied via a gas line  112  and pumped out through an exhaust line  114 . An electrical insulator ring  109  insulates the upper electrode  108  from the grounded chamber  100 . Confinement rings  116  may be placed between the upper electrode  108  and a bottom electrode, such as the chuck  102  in  FIG. 1 . In general, confinement rings  116  help confine the etching plasma  110  to the region above the wafer  104  to improve process control and to ensure repeatability. 
     When RF power is supplied to chuck  102  from dual frequency power source  106 , equipotential field lines are set up over the wafer  104 . The equipotential field lines are the electric field lines across the plasma sheath that is between wafer  104  and the plasma  110 . During plasma processing, the positive ions accelerate across the equipotential field lines to impinge on the surface of wafer  104 , thereby providing the desired etch effect, such as improving etch directionality. Due to the geometry of the upper electrode  108  and the chuck  102 , the field lines may not be uniform across the wafer surface and may vary significantly at the edge of the wafer  104 . Accordingly, a focus ring  118  is typically provided to improve process uniformity across the entire wafer surface. With reference to  FIG. 1 , wafer  104  is shown disposed within a focus ring  118 , which may be formed of a suitable dielectric material such as ceramic, quartz, plastic, or the like. Thus, the presence of the focus ring  118  allows the equipotential field lines to be disposed substantially uniformly over the entire surface of the wafer  104 . 
     An electrically conductive shield  120  substantially encircles the focus ring  118 . The electrically conductive shield  120  is configured to be substantially grounded within the plasma processing chamber. The shield  120  prevents the presence of unwanted equipotential field lines outside of focus ring  118 . 
     Reference is now made to  FIG. 2  of the accompanying drawings with illustrates a table  200  of example film stress and thickness shrinkage results. Here, in some examples, a base film was formed on a test wafer without chamber preconditioning steps as a control example. A first comparative hybrid film was created on another test wafer using the same overall deposition time as the base film, but in this case conventional chamber preconditioning steps of the type described further above were performed successively a total of ten times for every tenth of film thickness in the course of creating the first hybrid film. It will be seen from the table  200  in  FIG. 2  that the preconditioning operations resulted in a film stress increase of almost 400% from an initial value of 23.9 MPa for the control base film to a value of 99 MPa for the stressed first hybrid film. Further, the film suffered shrinkage (a reduction in thickness) from 1313.0 (A) for the control base film, to 1152.6 (A) for the first hybrid film. 
     The comparative results depicted in the graphs of  FIGS. 3A-3B  relate to a second hybrid film. The second hybrid film was formed on a test wafer processed in a chamber conditioned by using a protective layer as exemplified herein. A quadrant module including four stations labeled Stn1 through Stn4 in the views was employed to measure particle size (defects) existing at various deposition layers within the respective films placed under test. Results for the stressed first hybrid film (of the type tested in  FIG. 2  above) are shown in  FIG. 3A . Results for the second hybrid film formed in a conditioned (protected) chamber of the present disclosure are shown in  FIG. 3B . In both views of  FIGS. 3A-3B , a particle (defect) size is given on the left vertical axis of the illustrated graph, and a film thickness (or accumulation) is shown along the bottom horizontal axis for each of the four measuring stations. 
     As shown, particle sizes greater than 50 nm (i.e. defects) spiked at film thicknesses of approximately 0.8 μm at each of the four stations for the stressed first hybrid film as shown in  FIG. 3A . On the contrary, notably few, if any, defects were identified in the conditioned second hybrid film results shown in  FIG. 3B , even at film thicknesses depths of approximately 2 μm e.g. 1.904 μm for Stn1. Respective values for an Upper Control Limit (UCL) (for example set at three sigma), Lower Control Limit (LCL) and Average values are shown with demonstrable improvement in the conditioned second hybrid film of  FIG. 3B . 
     In view of the foregoing, a workable batch size (i.e. a level of film deposited on a wafer between chamber cleans) based on the illustrated example film results might be established at 0.8 μm as significant defects can be seen to occur at greater film thicknesses. On the contrary, for film conditioned according to methods of the present disclosure, a workable batch size may be established even at film thicknesses of approximately 2 μm or greater as no significant defects appear to arise below this example value. 
     Some embodiments of the present disclosure include methods. With reference to  FIG. 5 , a method  500  for conditioning a wafer processing chamber comprises, at operation  502 , setting a pressure in the chamber to a predetermined pressure range; at operation  504 , setting a temperature of the chamber to a predetermined temperature; at operation  506 , supplying a process gas mixture to a gas distribution device within the chamber, wherein the process gas mixture includes a gas including at least an oxygen species, and a helium or argon gas; at operation  508 , striking a plasma within the chamber; at  510 , monitoring a condition in the chamber; at operation  512 , based on a detection of the monitored condition meeting or transgressing a threshold value, implementing a chamber conditioning operation, wherein the chamber conditioning operation comprises: at operation  514 , depositing a preconditioning film onto an internal surface of the chamber, at operation  516 , depositing a silicon oxycarbide (SiCO) film onto the preconditioning film and, at operation  518 , depositing a protective layer onto the SiCO film. 
     Some aspects of the method  500  maybe include the following features or operations. In some examples, the monitored condition includes a chamber defect performance. In some examples, the monitored condition includes a film stress value. In some examples, the monitored condition includes a thickness of a film accumulation on the internal surface of the chamber. In some examples, a thickness of the film accumulation is in a range from 0.05 to 0.5 μm (microns). 
     In some examples, the protective layer is formed by chemical vapor deposition (CVD). A chemical used in a CVD reaction may include a silicon-containing species, such as silane or disilane. 
     In some examples, the predetermined pressure range of the chamber during deposition of the protective layer is in a range from 0.1 to 10 Torr. In some examples, the predetermined temperature range of the chamber during deposition of the protective layer is in a range from 100° C. to 600° C. In some examples, a thickness of the protective layer is in a range from 50 nanometers (nm) and 1 micron (μm). 
     In some examples, the operations of depositing a silicon oxycarbide (SiCO) film onto the preconditioning film and depositing a protective layer onto the SiCO film are repeated successively to form paired layers of a SiCO film and a protective layer within a composite protective film. 
     In some examples, the protective layer is a high-carbon, oxidation-resistant protective layer including 30% to 45% by weight carbon. 
     In some examples, the method  500  further comprising depositing the protective layer at a deposition rate in a range from 50 to 500 Angstrom (A)/min. 
     In some examples, striking the plasma comprises supplying HF power to one of an upper electrode and a lower electrode in a range from 500 to 6000 W and LF power to the one of the upper electrode and the lower electrode in a range from 500 to 6000 W. In some examples, striking the plasma comprises supplying HF power to one of an upper electrode and a lower electrode in a range from 2000 to 4000 W and LF power to the one of the upper electrode and the lower electrode in a range from 1000 to 4000 W. 
     Although an embodiment has been described with reference to specific example embodiments, it will be evident that various modifications and changes may be made to these embodiments without departing from the broader scope of the inventive subject matter. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense. The accompanying drawings that form a part hereof, show by way of illustration, and not of limitation, specific embodiments in which the subject matter may be practiced. The embodiments illustrated are described in sufficient detail to enable those skilled in the art to practice the teachings disclosed herein. Other embodiments may be utilized and derived therefrom, such that structural and logical substitutions and changes may be made without departing from the scope of this disclosure. This Detailed Description, therefore, is not to be taken in a limiting sense, and the scope of various embodiments is defined only by the appended claims, along with the full range of equivalents to which such claims are entitled. 
     Such embodiments of the inventive subject matter may be referred to herein, individually and/or collectively, by the term “invention” merely for convenience and without intending to voluntarily limit the scope of this application to any single invention or inventive concept if more than one is in fact disclosed. Thus, although specific embodiments have been illustrated and described herein, it should be appreciated that any arrangement calculated to achieve the same purpose may be substituted for the specific embodiments shown. This disclosure is intended to cover any and all adaptations or variations of various embodiments. Combinations of the above embodiments, and other embodiments not specifically described herein, will be apparent to those of skill in the art upon reviewing the above description.