Patent Publication Number: US-11397202-B2

Title: Comparator and receiver including the same

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     The present application claims priority to and the benefit of Korean patent application No. 10-2018-0121379 filed on Oct. 11, 2018 in the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. 
     BACKGROUND 
     1. Field 
     Aspects of some example embodiments of the present disclosure generally relate to a comparator and a receiver including the same. 
     2. Related Art 
     Major noise that causes degradation of a signal in a transmitting/receiving system in which a transmitter and a receiver are connected to each other through a single channel is inter-symbol interface (ISI). 
     In addition to the ISI, crosstalk further occurs in a high-speed parallel link system in which a transmitter and a receiver are connected to each other through a plurality of channels. The crosstalk includes jitter, in which the phase of a signal received through a victim channel is changed, glitch, in which the magnitude of a signal is changed, and the like. 
     The above information in the Background section is only for enhancement of understanding of the background of the technology and therefore it should not be construed as admission of existence or relevancy of the prior art. 
     SUMMARY 
     Aspects of some example embodiments may include a comparator capable of minimizing or reducing the influence of crosstalk caused by an adjacent channel and a receiver including the comparator. 
     According to some example embodiments of the present disclosure, a comparator includes: a first selector configured to select one of a first reference voltage and a first correction reference voltage, based on a first determination value of data at a past time of a first adjacent channel; a first comparator configured to compare the difference between a voltage selected from the first reference voltage and the first correction reference voltage and a second reference voltage with an input voltage at a current time of a target channel; and a first output unit configured to determine an output voltage at the current time of the target channel, based on the comparison result of the first comparator. 
     According to some example embodiments, the input voltage may be a differential signal and include a first input voltage and a second input voltage. The first comparator may compare the difference between the first input voltage and the second input voltage with the difference between the voltage selected from the first reference voltage and the first correction reference voltage and the second reference voltage. 
     According to some example embodiments, the comparator may further include: a second selector configured to select one of the second reference voltage and a second correction reference voltage, based on the first determination value; a second comparator configured to compare the difference between a voltage selected from the second reference voltage and the second correction reference voltage and the first reference voltage with the input voltage; and a second output unit configured to determine an output voltage at the current time of the target channel, based on the comparison result of the second comparator. 
     According to some example embodiments, the first correction reference voltage may have a value between the first reference voltage and the second reference voltage, and the second correction reference voltage may have a value between the first reference voltage and the second reference voltage. The first correction reference voltage may be larger than the second correction reference voltage. 
     According to some example embodiments, the first selector may include: a first inverter inverting the first determination value; a first transistor having a gate electrode to which a clock signal is applied and one electrode connected to a first power source; a second transistor having a gate electrode connected to an output end of the first inverter and one electrode connected to the other electrode of the first transistor; a third transistor having a gate electrode to which the first correction reference voltage is applied, one electrode connected to the other electrode of the second transistor, and the other electrode connected to a first node; and a fourth transistor having a gate electrode to which the second reference voltage is applied, one electrode connected to the other electrode of the second transistor, and the other electrode connected to a second node. 
     According to some example embodiments, the first selector may further include: a fifth transistor having a gate electrode to which the clock signal is applied and one electrode connected to the first power source; a sixth transistor having a gate electrode to which the first determination value is applied and one electrode connected to the other electrode of the fifth transistor; a seventh transistor having a gate electrode to which the first reference voltage is applied, one electrode connected to the other electrode of the sixth transistor, and the other electrode connected to the first node; and an eighth transistor having a gate electrode to which the second reference voltage is applied, one electrode connected to the other electrode of the sixth transistor, and the other electrode connected to the second node. 
     According to some example embodiments, the first comparator may include: a ninth transistor having a gate electrode to which the clock signal is applied and one electrode connected to the first power source; a tenth transistor having a gate electrode to which a turn-on level voltage is applied and one electrode connected to the other electrode of the ninth transistor; an eleventh transistor having a gate electrode to which the first input voltage is applied, one electrode connected to the other electrode of the tenth transistor, and the other electrode connected to the second node; and a twelfth transistor having a gate electrode to which the second input voltage is applied, one electrode connected to the other electrode of the tenth transistor, and the other electrode connected to the first node. 
     According to some example embodiments, the first comparator may further include: a thirteenth transistor having a gate electrode to which the clock signal is applied, one electrode connected to the second node, and the other electrode connected to a second power source; a fourteenth transistor having a gate electrode to which the clock signal is applied, one electrode connected to the first node, and the other electrode connected to the second power source; a fifteenth transistor having a gate electrode connected to the second node, one electrode connected to the first power source, and the other electrode connected to a first output terminal; and a sixteenth transistor having a gate electrode connected to the first node, one electrode connected to the first power source, and the other electrode connected to a second output terminal. 
     According to some example embodiments, the first output unit may include: a second inverter having an input end connected to the first output terminal and an output end connected to the second output terminal; a third inverter having an input end connected to the second output terminal and an output end connected to the first output terminal; and a seventeenth transistor having a gate electrode to which an inverting signal of the clock signal is applied, one electrode connected to a power terminal of the second inverter and a power terminal of the third inverter, and the other electrode connected to the second power source. 
     According to some example embodiments, the second selector may include: a fourth inverter inverting the first determination value; an eighteenth transistor having a gate electrode to which the clock signal is applied and one electrode connected to the first power source; a nineteenth transistor having a gate electrode connected to an output end of the fourth inverter and one electrode connected to the other electrode of the eighteenth transistor; a twentieth transistor having a gate electrode to which the first reference voltage is applied, one electrode connected to the other electrode of the nineteenth transistor, and the other electrode connected to a third node; and a twenty-first transistor having a gate electrode to which the second reference voltage is applied, one electrode connected to the other electrode of the nineteenth transistor, and the other electrode connected to a fourth node. 
     According to some example embodiments, the second selector may further include: a twenty-second transistor having a gate electrode to which the clock signal is applied and one electrode connected to the first power source; a twenty-third transistor having a gate electrode to which the first determination value is applied and one electrode connected to the other electrode of the twenty-second transistor; a twenty-fourth transistor having a gate electrode to which the first reference voltage is applied, one electrode connected to the other electrode of the twenty-third transistor, and the other electrode connected to the third node; and a twenty-fifth transistor having a gate electrode to which the second correction reference voltage is applied, one electrode connected to the other electrode of the twenty-third transistor, and the other electrode connected to the fourth node. 
     According to some example embodiments, the second comparator may include: a twenty-sixth transistor having a gate electrode to which the clock signal is applied and one electrode connected to the first power source; a twenty-seventh transistor having a gate electrode to which the turn-on level voltage is applied and one electrode connected to the other electrode of the twenty-sixth transistor; a twenty-eighth transistor having a gate electrode to which the second input voltage is applied, one electrode connected to the other electrode of the twenty-seventh transistor, and the other electrode connected to the fourth node; and a twenty-ninth transistor having a gate electrode to which the first input voltage is applied, one electrode connected to the other electrode of the twenty-seventh transistor, and the other electrode connected to the third node. 
     According to some example embodiments, the second comparator may further include: a thirtieth transistor having a gate electrode to which the clock signal is applied, one electrode connected to the fourth node, and the other electrode connected to the second power source; a thirty-first transistor having a gate electrode to which the clock signal is applied, one electrode connected to the third node, and the other electrode connected to the second power source; a thirty-second transistor having a gate electrode connected to the fourth node, one electrode connected to the first power source, and the other electrode connected to a third output terminal; and a thirty-third transistor having a gate electrode connected to the third node, one electrode connected to the first power source, and the other electrode connected to a fourth output terminal. 
     According to some example embodiments, the second output unit may include: a fifth inverter having an input end connected to the third output terminal and an output end connected to the fourth output terminal; a sixth inverter having an input end connected to the fourth output terminal and an output end connected to the third output terminal; and a thirty-fourth transistor having a gate electrode to which the inverting signal of the clock signal is applied, one electrode connected to a power terminal of the fifth inverter and a power terminal of the sixth inverter, and the other electrode connected to the second power source. 
     According to some example embodiments of the present disclosure, a comparator includes: a first selector configured to select one of a first reference voltage and a first correction reference voltage, based on a first determination value of data at a past time of a first adjacent channel and a second determination value of data at a past time of a second adjacent channel; a first comparator configured to compare the difference between a voltage selected from the first reference voltage and the first correction reference voltage and a second reference voltage with an input voltage at a current time of a target channel; and a first output unit configured to determine an output voltage at the current time of the target channel, based on the comparison result of the first comparator. 
     According to some example embodiments, the comparator may further include: a second selector configured to select one of the second reference voltage and a second correction reference voltage, based on the first determination value and the second determination value; a second comparator configured to compare the difference between a voltage selected from the second reference voltage and the second correction reference voltage and the first reference voltage with the input voltage; and a second output unit configured to determine an output voltage at the current time of the target channel, based on the comparison result of the second comparator. 
     According to some example embodiments, the first selector may include: a first NOR gate receiving the first determination value and the second determination value; a first transistor having a gate electrode to which a clock signal is applied and one electrode connected to a first power source; a second transistor having a gate electrode to which an output value of the first NOR gate is applied and one electrode connected to the other electrode of the first transistor; a third transistor having a gate electrode to which the first correction reference voltage is applied, one electrode connected to the other electrode of the second transistor, and the other electrode connected to a first node; a fourth transistor having a gate electrode to which the second reference voltage is applied, one electrode connected to the other electrode of the second transistor, and the other electrode connected to a second node; a first inverter inverting the output value of the first NOR gate; a fifth transistor having a gate electrode to which the clock signal is applied and one electrode connected to the first power source; a sixth transistor having a gate electrode connected to an output end of the first inverter and one electrode connected to the other electrode of the fifth transistor; a seventh transistor having a gate electrode to which the first reference voltage is applied, one electrode connected to the other electrode of the sixth transistor, and the other electrode connected to the first node; and an eighth transistor having a gate electrode to which the second reference voltage is applied, one electrode connected to the other electrode of the sixth transistor, and the other electrode connected to the second node. 
     According to some example embodiments, the second selector may include: a first NAND gate receiving the first determination value and the second determination value; an eighteenth transistor having a gate electrode to which the clock signal is applied and one electrode connected to the first power source; a nineteenth transistor having a gate electrode to which an output voltage of the first NAND gate is applied and one electrode connected to the other electrode of the eighteenth transistor; a twentieth transistor having a gate electrode to which the first reference voltage is applied, one electrode connected to the other electrode of the nineteenth transistor, and the other electrode connected to a third node; a twenty-first transistor having a gate electrode to which the second reference voltage is applied, one electrode connected to the other electrode of the nineteenth transistor, and the other electrode connected to a fourth node; a fourth inverter inverting the output value of the first NAND gate; a twenty-second transistor having a gate electrode to which the clock signal is applied and one electrode connected to the first power source; a twenty-third transistor having a gate electrode connected to an output end of the fourth inverter and one electrode connected to the other electrode of the twenty-second transistor; a twenty-fourth transistor having a gate electrode to which the first reference voltage is applied, one electrode connected to the other electrode of the twenty-third transistor, and the other electrode connected to the third node; and a twenty-fifth transistor having a gate electrode to which the second correction reference voltage is applied, one electrode connected to the other electrode of the twenty-third transistor, and the other electrode connected to the fourth node. 
     According to some example embodiments of the present disclosure, a receiver includes: a first comparator configured to select one of a first reference voltage and a first correction reference voltage, based on a determination value of data at a past time of at least one adjacent channel, and compare the difference between the selected voltage and a second reference voltage with an input voltage at a current time of a target channel; a second comparator configured to select one of the second reference voltage and a second correction reference value, based on the determination value of the data at the past time of the at least one adjacent channel, and compare the difference between the selected voltage and the first reference voltage with the input voltage; and a multiplexer configured to output one of an output value of the first comparator and an output value of the second comparator as a determination value of data at the current time of the target channel, based on a determination value of data at a past time of the target channel. 
     According to some example embodiments, the first correction reference voltage may have a value between the first reference voltage and the second reference voltage, and the second correction reference voltage may have a value between the first reference voltage and the second reference voltage. The first correction reference voltage may be larger than the second correction reference voltage. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Aspects of some example embodiments will now be described more fully hereinafter with reference to the accompanying drawings; however, they may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be more thorough and more complete, and will more fully convey the scope of the example embodiments to those skilled in the art. 
       In the drawing figures, dimensions may be exaggerated for clarity of illustration. It will be understood that when an element is referred to as being “between” two elements, it can be the only element between the two elements, or one or more intervening elements may also be present. Like reference numerals refer to like elements throughout. 
         FIG. 1  is a diagram illustrating a receiver and a transceiver including the same according to some example embodiments of the present disclosure. 
         FIG. 2  is a diagram illustrating a reception signal with respect to a transmission signal. 
         FIG. 3  is a diagram illustrating a reception signal with respect to another transmission signal. 
         FIG. 4  is a diagram illustrating an example of crosstalk-induced glitch caused by an adjacent reception signal. 
         FIG. 5  is a diagram illustrating another example of the crosstalk-induced glitch caused by the adjacent reception signal. 
         FIG. 6  is a diagram illustrating a receiving unit according to some example embodiments of the present disclosure. 
         FIG. 7  is a diagram illustrating a driving method of the receiving unit according to some example embodiments of the present disclosure. 
         FIG. 8  is a diagram illustrating a first comparator according to some example embodiments of the present disclosure. 
         FIG. 9  is a diagram illustrating a second comparator according to some example embodiments of the present disclosure. 
         FIG. 10  is a diagram illustrating a receiving unit according to some example embodiments of the present disclosure. 
         FIG. 11  is a diagram illustrating a driving method of the receiving unit according to some example embodiments of the present disclosure. 
         FIG. 12  is a diagram illustrating a first comparator according to some example embodiments of the present disclosure. 
         FIG. 13  is a diagram illustrating a second comparator according to some example embodiments of the present disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     Hereinafter, aspects of some example embodiments are described in more detail with reference to the accompanying drawings so that those skilled in the art may easily practice the present disclosure. The present disclosure may be implemented in various different forms and is not limited to the example embodiments described in the present specification. 
     Description of some components that may be irrelevant to understanding the example embodiments may be omitted to more clearly describe the present disclosure, and the same or similar constituent elements will be designated by the same reference numerals throughout the specification. Therefore, the same reference numerals may be used in different drawings to identify the same or similar elements. 
     In addition, the size and thickness of each component illustrated in the drawings are arbitrarily shown for better understanding and ease of description, but the present disclosure is not limited thereto. Thicknesses of several portions and regions are exaggerated for clear expressions. 
       FIG. 1  is a diagram illustrating a receiver and a transceiver including the same according to some example embodiments of the present disclosure. 
     Referring to  FIG. 1 , the transceiver TCS according to some example embodiments of the present disclosure includes a transmitter DV 1  and a receiver DV 2 . 
     The transmitter DV 1  includes transmitting units TX 1 , TX 2 , TX 3 , . . . , and TXn connected to corresponding channels CH 1 , CH 2 , CH 3 , . . . , CHn. 
     The receiver DV 2  includes receiving units RX 1 , RX 2 , RX 3 , . . . , and RXn connected to the corresponding channels CH 1 , CH 2 , CH 3 , . . . , CHn. 
     For example, the transceiver TSC may be a memory system. The channels CH 1  to CHn may constitute a memory bus, and the transmitter DV 1  and the receiver DV 2  may be a transmitter and a receiver at the side of a controller or memory. The memory may be a frame memory of a display device such as a liquid crystal display (LCD) or an organic light emitting display (OLED). The frame memory may be used as a frame buffer in the display device, and store pixel data with respect to a specific frame. 
     However, the receiver DV 2  of this embodiment is not necessarily applied to the memory system, and may be applied to any field as long as the receiver DV 2  is a parallel link system connected to a transmitter through a plurality of channels. 
       FIG. 2  is a diagram illustrating a reception signal with respect to a transmission signal.  FIG. 3  is a diagram illustrating a reception signal with respect to another transmission signal. 
     In  FIGS. 2 and 3 , an ideal case where crosstalk does not exist is assumed. In  FIGS. 2 and 3 , the interval between adjacent sampling times is a unit interval (1UI). 
     In  FIGS. 2 and 3 , a changeable level of a reception signal may be one of no less than a lowest level LL and no more than a highest level HL. An intermediate level IL has a value between the lowest level LL and the highest level HL. 
     Referring to  FIG. 2 , an example reception signal fr_a of the receiver DV 2 , which passes through an arbitrary channel, when the transmitter DV 1  transmits a transmission signal of which binary level is 0, 1, 0 through the channel is illustrated. A case where the other data of the transmission signal, which are not shown in  FIG. 2 , have binary level 0 is assumed. 
     The shape of the reception signal fr_a shown in  FIG. 2  may be acquired when the channel is designed a low pass filter. Therefore, according to some example embodiments, each of the plurality of channels CH 1  to CHn connecting the transmitter DV 1  and the receive DV 2  may be designed as a low pass filter. 
     The reception signal following a response shape shown in  FIG. 2  may be referred to as a duo-binary signal. The response shape shown in  FIG. 2  may be obtained even when the transmitter DV 1  includes an encoder for duo-binary signaling, in addition to when the channel is designed as a low pass filter. 
     There are various duo-binary signaling methods. However, in general, in the case of the reception signal fr_a of  FIG. 2 , a cursor of a sampling time sp 1 _ a  becomes a pre-cursor, a cursor of a sampling time sp 2 _ a  becomes a main cursor, a cursor of a sampling time sp 3 _ a  becomes a first post-cursor, and a cursor of a sampling time sp 4 _ a  becomes a second post-cursor. Various known methods may be used such that a level (magnitude) of the main cursor is equal to that of the first post-cursor so as to properly apply the duo-binary signaling. 
     Referring to  FIG. 3 , an example reception signal spr_b of the receiver DV 2 , which passes through an arbitrary channel, when the transmitter DV 1  transmits a transmission signal of which binary level is 0, 1, 1, 0 through the channel is illustrated. A case where the other data of the transmission signal, which are not shown in  FIG. 3 , have the binary level 0 is assumed. 
     In  FIG. 3 , the reception signal spr_b may be an overlapping signal of a response signal fr_b corresponding to first binary level 1 and a response signal sr_b corresponding to second binary level 1. In general, in the case of the response signal fr_b, a cursor of a sampling time sy 1 _ b  becomes a pre-cursor, a cursor of a sampling time sp 2 _ b  becomes a main cursor, a cursor of a sampling time sp 3 _ b  becomes a first post-cursor, and a cursor of a sampling time sp 4 _ b  becomes a second post-cursor. In general, in the case of the response signal sr_b, a cursor of the sampling time sp 2 _ b  becomes a pre-cursor, a cursor of the sampling time sp 3 _ b  becomes a main cursor, a cursor of the sampling time sp 4 _ b  becomes a first post-cursor, and a cursor of a sampling time sp 5 _ b  becomes a second post-cursor. 
     Hereinafter, a decoding method for a duo-binary signal will be described with reference to  FIGS. 2 and 3 . 
     A determination value of 1UI previous data may be utilized when decoding on a duo-binary signal is performed. When the determination value of the 1UI previous data is 1, a first reference voltage VH may be used when current data is determined. Also, when the determination value of the 1UI previous data is 0, a second reference voltage VL may be used when the current data is determined. The first reference voltage VH may have an intermediate value of the highest level HL and the intermediate level IL among the changeable levels of the reception signal. The second reference voltage VL may have an intermediate value of the lowest level LL and the intermediate level IL among the changeable levels of the reception signal. 
     In an example, referring to  FIG. 2 , because the determination value of the 1UI previous data is 0 at the sampling time sp 2 _ a , the binary level of the current data may be determined based on the second reference voltage VL. The level of the reception signal sampled at the sampling time sp 2 _ a  is the intermediate level IL that is higher than the second reference voltage VL. Therefore, the binary level of the current data may be determined as 1. 
     Next, referring to  FIG. 2 , because the determination of the 1UI previous data is 1 at the sampling time sp 3 _ a , the binary level of the current data may be determined based on the first reference voltage VH. The level of the reception signal sampled at the sampling time sp 3 _ a  is the intermediate level IL that is lower than the first reference voltage VH. Therefore, the binary level of the current data may be determined as 0. 
     In another example, referring to  FIG. 3 , because the determination of the 1UI previous data is 0 at the sampling time sp 2 _ b , the binary level of the current data may be determined based on the second reference voltage VL. The level of the reception signal sampled at the sampling time sp 2 _ b  is the intermediate level IL that is higher than the second reference voltage VL. Therefore, the binary level of the current data may be determined as 1. 
     Next, referring to  FIG. 3 , because the determination of the 1UI previous data is 1 at the sampling time sp 3 _ b , the binary level of the current data may be determined based on the first reference voltage VH. The level of the reception signal sampled at the sampling time sp 3 _ b  is the highest level HL that is higher than the first reference voltage VH. Therefore, the binary level of the current data may be determined as 1. 
     Next, referring to  FIG. 3 , because the determination of the 1UI previous data is 1 at the sampling time sp 4 _ b , the binary level of the current data may be determined based on the first reference voltage VH. The level of the reception signal sampled at the sampling time sp 4 _ b  is the intermediate level IL that is lower than the first reference voltage VH. Therefore, the binary level of the current data may be determined as 0. 
       FIG. 4  is a diagram illustrating an example of crosstalk-induced glitch caused by an adjacent reception signal.  FIG. 5  is a diagram illustrating another example of the crosstalk-induced glitch caused by the adjacent reception signal. 
     When the crosstalk-induced glitch is described, a target channel is referred to as a victim channel, and an adjacent channel that has bad influence on the victim channel is referred to an aggressor channel. In this description, the victim channel as the target channel is assumed as a channel CH 2 , and the aggressor channel is assumed as a channel CH 1 . However, in  FIGS. 10 to 13 , the aggressor channel may include a plurality of channels CH 1  and CH 3 . 
     Meanwhile, crosstalk-induced glitch induced in the channel CH 2  may have bad influence on the channel CH 1 , and the bad influence may return to the channel CH 2 . The influence is relatively insignificant, and description is excessively complicated. Therefore, its description will be omitted. 
     Referring to  FIG. 4 , there is illustrated a case where a rising transition occurs in the aggressor channel CH 1 . A case where the transmitting unit TX 2  is continuously transmitting a signal corresponding to the binary level 1 through the victim channel CH 2  is assumed. 
     As described above, in order for the receiving unit RX 2  to determine a binary level at each of sampling times sp 1 _ c  to sp 5 _ c  as 1, the reception signal has a level of the first reference voltage VH or higher at each of the sampling times sp 1 _ c  to sp 5 _ c , which is ideal. 
     However, when a rising transition occurs in the aggressor channel CH 1 , electromagnetic interference EMIa is caused by mutual inductance between the two channels CH 1  and CH 2 , and therefore, a voltage drop occurs in the victim channel CH 2 . The voltage drop may be referred to as crosstalk-induced glitch. 
     Therefore, the receiving unit RX 2  may sample a reception signal having a level lower than the first reference voltage VH at a sampling time sp 3 _ c  at which the electromagnetic interference EMIa occurs. An error that the binary level of the reception signal at the sampling time sp 3 _ c  is determined as 0 occurs. 
     In the present disclosure, under a situation such as the sampling time sp 3 _ c , a first correction reference voltage VH− is used instead of the first reference voltage VH, so that incidences of a sampling error caused by glitch can be prevented or reduced. 
     Referring to  FIG. 5 , there is illustrated a case where a falling transition occurs in the aggressor channel CH 1 . A case where the transmitting unit TX 2  is continuously transmitting a signal corresponding to the binary level 0 through the victim channel CH 2  is assumed. 
     As described above, in order for the receiving unit RX 2  to determine a binary level at each of sampling times sp 1 _ d  to sp 5 _ d  as 0, the reception signal has a level of the second reference voltage VL or lower at each of the sampling times sp 1 _ d  to sp 5 _ d , which is ideal. 
     However, when a falling transition occurs in the aggressor channel CH 1 , electromagnetic interference EMIb is caused by mutual inductance between the two channels CH 1  and CH 2 , and therefore, a voltage rise occurs in the victim channel CH 2 . The voltage rise may be referred to as crosstalk-induced glitch. 
     Therefore, the receiving unit RX 2  may sample a reception signal having a level higher than the second reference voltage VL at a sampling time sp 3 _ d  at which the electromagnetic interference EMIb occurs. An error that the binary level of the reception signal at the sampling time sp 3 _ d  is determined as 1 occurs. 
     In the present disclosure, under a situation such as the sampling time sp 3 _ d , a second correction reference voltage VL+ is used instead of the second reference voltage VL, so that incidences of a sampling error caused by glitch can be prevented or reduced. 
     According to some example embodiments, the first correction reference voltage VH− may have a value between the first reference voltage VH and the second reference voltage VL, and the second correction reference voltage VL+ may have a value between the first reference voltage VH and the second reference voltage VL. The first correction reference voltage VH− may be larger than the second correction reference voltage VL+. 
     In some example embodiments, the first correction reference voltage VH− may be larger than the intermediate level IL, and the second correction reference voltage VL+ may be smaller than the intermediate level IL (see, e.g.,  FIGS. 2 and 3 ). 
       FIG. 6  is a diagram illustrating a receiving unit according to some example embodiments of the present disclosure. 
     Although the receiving unit RX 2  is illustrated based on the target channel CH 2  in  FIG. 6 , the same contents may be applied to another channel and another receiving unit. Referring to  FIG. 6 , the receiving unit RX 2  may include a first comparator CMP 1 , a second comparator CMP 2 , and a multiplexer MUX. 
     The first comparator CMP 1  may select one of the first reference voltage VH and the first correction reference voltage VH−, based on a determination value D 1 [m−1] of data at a past time of at least one adjacent channel CH 1 , and compare the difference between the selected voltage and the second reference voltage VL with an input voltage at a current time of the target channel CH 2 . 
     When the current time is an mth UI (m is a natural number), the past time may be an (m−1)th UI. That is, the past time may be a 1UI previous time as compared with the current time. In some example embodiments, the past time may be a past time of 2UI time or more as compared with the current time. 
     The second comparator CMP may select one of the second reference voltage VL and the second correction reference voltage VL+, based on the determination value D 1 [m−1] of the data at the past time of the at least one adjacent channel CH 1 , and compare the difference between the selected voltage and the first reference voltage VH with the input voltage. 
     The multiplexer MUX may output one of an output value of the first comparator CMP 1  and an output value of the second comparator CMP 2  as a determination value D 2 [m] of data at a current time of the target channel CH 2 , based on a determination value D 2 [m−1] of data at a past time of the target channel CH 2 . 
     For example, when the determination value D 2 [m−1] at a 1UI previous time corresponds to the binary level 1, the multiplexer MUX may output the output value of the first comparator CMP 1  as the determination value D 2 [m] at the current time. The output value of the second comparator CMP 2  may be neglected. 
     In addition, when the determination value D 2 [m−1] at the 1UI previous time corresponds to the binary level 0, the multiplexer MUX may output the output value of the second comparator CMP 2  as the determination value D 2 [m] at the current time. The output value of the first comparator CMP 1  may be neglected. 
       FIG. 7  is a diagram illustrating a driving method of the receiving unit according to some example embodiments of the present disclosure. 
     As described above, when the determination value D 2 [m−1] of the data at the past time of the target channel CH 2  corresponds to the binary level 1, the output value of the first comparator CMP 1  may be used when the value D 2 [m] of the data at the current time of the target channel CH 2  is determined. 
     As described above with reference to  FIG. 4 , when a rising transition occurs in the adjacent channel CH 1 , the first correction reference voltage VH− may be used instead of the first reference voltage VH. The rising transition at the current time of the adjacent channel CH 1  may occur only when the determination value D 1 [m−1] of the data at the past time of the adjacent channel CH 1  corresponds to the binary level 0. 
     Therefore, according to some example embodiments, when the determination value D 1 [m−1] of the data at the past time of the adjacent channel CH 1  corresponds to the binary level 0, the first comparator CMP 1  may compare the first correction reference voltage VH− and a sampling signal of the target channel CH 2 . In other cases, the first comparator CMP 1  may compare the first reference voltage VH and the sampling signal of the target channel CH 2 . 
     As described above, when the determination value D 2 [m−1] of the data at the past time of the target channel CH 2  corresponds to the binary level 0, the output value of the second comparator CMP 2  may be used when the value D 2 [m] of the data at the current time of the target channel CH 2  is determined. 
     As described above with reference to  FIG. 5 , when a falling transition occurs in the adjacent channel CH 1 , the second correction reference voltage VL+ may be used instead of the first reference voltage VH. The falling transition at the current time of the adjacent channel CH 1  may occur only when the determination value D 1 [m−1] of the data at the past time of the adjacent channel CH 1  corresponds to the binary level 1. 
     Therefore, according to some example embodiments, when the determination value D 1 [m−1] of the data at the past time of the adjacent channel CH 1  corresponds to the binary level 1, the second comparator CMP 2  may compare the second correction reference voltage VL+ and the sampling signal of the target channel CH 2 . In other cases, the second comparator CMP 2  may compare the second reference voltage VL and the sampling signal of the target channel CH 2 . 
       FIG. 8  is a diagram illustrating a first comparator according to some example embodiments of the present disclosure. 
     Referring to  FIG. 8 , the first comparator CMP 1  according to some example embodiments of the present disclosure may include a first selector SLT 1 , a first comparator CPU 1 , and a first output unit OUT 1 . 
     The first selector SLT 1  may include transistors T 1  to T 8  and a first inverter INV 1 . The transistors T 1  to T 8  may be implemented with an N-type transistor (e.g., an NMOS transistor). 
     The first inverter INV 1  may invert the determination value D 1 [m−1] of the data at the past time of the adjacent channel CH 1 . 
     A clock signal CLK may be applied to a gate electrode of a first transistor T 1 , one electrode of the first transistor T 1  may be connected to a first power source VSS, and the other electrode of the first transistor T 1  may be connected to one electrode of a second transistor T 2 . 
     A gate electrode of the second transistor T 2  may be connected to an output end of the first inverter INV 1 , the one electrode of the second transistor T 2  may be connected to the other electrode of the first transistor T 1 , and the other electrode of the second transistor T 2  may be connected to one electrode of a third transistor T 3 . 
     The first correction reference voltage VH− may be applied to a gate electrode of the third transistor T 3 , the one electrode of the third transistor T 3  may be connected to the other electrode of the second transistor T 2 , and the other electrode of the third transistor T 3  may be connected to a first node N 1 . 
     The second reference voltage VL may be applied to a gate electrode of a fourth transistor T 4 , one electrode of the fourth transistor T 4  may be connected to the other electrode of the second transistor T 2 , and the other electrode of the fourth transistor T 4  may be connected to a second node N 2 . 
     The clock signal CLK may be applied to a gate electrode of a fifth transistor T 5 , one electrode of the fifth transistor T 5  may be connected to the first power source VSS, and the other electrode of the fifth transistor T 5  may be one electrode of a sixth transistor T 6 . 
     The determination value D 1 [m−1] may be applied to a gate electrode of the sixth transistor T 6 , the one electrode of the sixth transistor T 6  may be connected to the other electrode of the fifth transistor T 5 , and the other electrode of the sixth transistor T 6  may be connected to one electrode of a seventh transistor T 7 . 
     The first reference voltage VH may be applied to a gate electrode of the seventh transistor T 7 , the one electrode of the seventh transistor T 7  may be connected to the other electrode of the sixth transistor T 6 , and the other electrode of the seventh transistor T 7  may be connected to the first node N 1 . 
     The second reference voltage VL may be applied to a gate electrode of an eighth transistor T 8 , one electrode of the eighth transistor T 8  may be connected to the other electrode of the sixth transistor T 6 , and the other electrode of the eighth transistor T 8  may be connected to the second node N 2 . 
     The first selector SLT 1  may select one of the first reference voltage VH and the first correction reference voltage VH−, based on the determination value D 1 [m−1]. 
     For example, when the determination value D 1 [m−1] corresponds to the binary level 1, the second transistor T 2  may be turned off, and the sixth transistor T 6  may be turned on. When the clock signal CLK having a high level is applied, the first node N 1  may be connected to the first power source VSS through the transistors T 7 , T 6 , and T 5 , and the second node N 2  may be connected to the first power source VSS through the transistors T 8 , T 6 , and T 5 . Therefore, the first reference voltage VH has influence on the discharge speed of the first node N 1 , and the second reference voltage VL has influence on the discharge speed of the second node N 2 . 
     When the determination value D 1 [m−1] corresponds to the binary level 0, the second transistor T 2  may be turned on, and the sixth transistor T 6  may be turned off. When the clock signal CLK having the high level having the high level is applied, the first node may be connected to the first power source VSS through the transistors T 3 , T 2 , and T 1 , and the second node N 2  may be connected to the first power source VSS through the transistors T 4 , T 2 , and T 1 . Therefore, the first correction reference voltage VH− has influence on the discharge speed of the first node N 1 , and the second reference voltage VL has influence on the discharge speed of the second node N 2 . 
     The first comparator CPU 1  may include transistors T 9  to T 16 . Transistors T 13  and T 14  may be implemented with a P-type transistor (e.g., a PMOS transistor), and transistors T 9 , T 10 , T 11 , T 12 , T 15 , and T 16  may be implemented with the N-type transistor. 
     The clock signal CLK may be applied to a gate electrode of a ninth transistor T 9 , one electrode of the ninth transistor T 9  may be connected to the first power source VSS, and the other electrode of the ninth transistor T 9  may be connected to one electrode of a tenth transistor T 10 . 
     A turn-on level voltage LogicH may be applied to a gate electrode of the tenth transistor T 10 , the one electrode of the tenth transistor T 10  may be connected to the other electrode of the ninth transistor T 9 , and the other electrode of the tenth transistor T 10  may be connected to one electrode of an eleventh transistor T 11 . 
     A first input voltage CH 2 Pi may be applied to a gate electrode of the eleventh transistor T 11 , the one electrode of the eleventh transistor T 11  may be connected to the other electrode of the tenth transistor T 10 , and the other electrode of the eleventh transistor T 11  may be connected to the second node N 2 . 
     A second input voltage CH 2 Ni may be applied to a gate electrode of a twelfth transistor T 12 , one electrode of the twelfth transistor T 12  may be connected to the other electrode of the tenth transistor T 10 , and the other electrode of the twelfth transistor T 12  may be connected to the first node N 1 . 
     The clock signal CLK may be applied to a gate electrode of a thirteenth transistor T 13 , one electrode of the thirteenth transistor T 13  may be connected to the second node N 2 , and the other electrode of the thirteenth transistor T 13  may be connected to a second power source VDD. The voltage level of the second power source VDD may be larger than that of the first power source VSS. 
     The clock signal CLK may be applied to a gate electrode of a fourteenth transistor T 14 , one electrode of the fourteenth transistor T 14  may be connected to the first node N 1 , and the other electrode of the fourteenth transistor T 14  may be connected to the second power source VDD. 
     A gate electrode of the fifteenth transistor T 15  may be connected to the second node N 2 , one electrode of the fifteenth transistor T 15  may be connected to the first power source VSS, and the other electrode of the fifteenth transistor T 15  may be connected to a first output terminal CH 2   o   1 . 
     A gate electrode of a sixteenth transistor T 16  may be connected to the first node N 1 , one electrode of the sixteenth transistor T 16  may be connected to the first power source VSS, and the other electrode of the sixteenth transistor T 16  may be connected to a second output terminal CH 2   o   2 . 
     The first comparator CPU 1  may compare the difference between a voltage selected from the first reference voltage VH and the first correction reference voltage VH− and the second reference voltage VL with an input voltage at the current time of the target channel CH 2 . 
     In some embodiments, the input voltage is a differential signal and may include the first input voltage CH 2 Pi and the second input voltage CH 2 Ni. The first comparator CPU 1  may compare the difference between the first input voltage CH 2 Pi and the second input voltage CH 2 Ni with the difference between the voltage selected from the first reference voltage VH and the first correction reference voltage VH− and the second reference voltage VL. 
     First, when the clock signal CLK has a low level, the thirteenth transistor T 13  may be turned on to charge the second node N 2  with the voltage of the second power source VDD. In addition, the fourteenth transistor  14  may be turned on to charge the first node N 1  with the voltage of the second power source VDD. 
     Next, when the clock signal CLK has the high level, the second node N 2  may be connected to the first power source VSS through the transistors T 11 , T 10 , and T 9 , and the first node N 1  may be connected to the first power source VSS through the transistors T 12 , T 10 , and T 9 . 
     Referring to the description of the first selector SLT 1 , when the determination value D 1 [m−1] corresponds to the binary level 1, the discharge speed of the first node N 1  increases when the magnitude of the first reference voltage VH and the second input voltage CH 2 Ni increases, and the discharge speed of the second node N 2  increases when the magnitude of the second reference voltage VL and the first input voltage CH 2 Pi increases. 
     For example, at the sampling times sy 1 _ c , sp 2 _ c , sp 4 _ c , and sp 5 _ c  of  FIG. 4 , the following Equation 1 is satisfied, and therefore, the discharge speed of the second node N 2  may be faster than that of the first node N 1 .
 
CH2Pi−CH2Ni&gt;VH−VL  Equation 1
 
     When the second node N 2  is first discharged, the fifteenth transistor T 15  may be turned off. Because the sixteenth transistor T 16  is still in a turn-on state, the voltage of the first power source VSS is output to the second output terminal CH 2   o   2 , and the voltage of the second power source VDD is output to the first output terminal CH 2   o   1  by inverters INV 2  and INV 3 . A voltage of the first output terminal CH 2   o   1  may be used as the output value of the first comparator CMP 1 . When the voltage of the second power source VDD is output from the first output terminal CH 2   o   1 , the output value of the first comparator CMP 1  may be determined as the binary level 1. 
     However, as the value of CH 2 Pi-CH 2 Ni decreases due to the electromagnetic interference EMIa at the sampling time sp 3 _ c  of  FIG. 4 , Equation 1 may not be satisfied. The discharge speed of the first node N 1  is faster than that of the second node N 2 , and therefore, the first comparator CMP 1  may output the binary level 0. 
     Thus, according to some example embodiments, the following Equation 2 is satisfied at the sampling time sp 3 _ c  of  FIG. 4 , so that the first comparator CMP 1  can output the binary level 1 in spite of the electromagnetic interference EMIa.
 
CH2Pi−CH2Ni&gt;(VH−)−VL  Equation 2
 
     According to Equation 2, although the value of CH 2 Pi-CH 2 Ni decreases due to the electromagnetic interference EMIa at the sampling time sp 3 _ c , the value of (VH−)−VL also decreases as compared with the value of VH−VL, and therefore, Equation 2 may be satisfied. 
     The first output unit OUT 1  may include a seventeenth transistor T 11  and the inverters INV 2  and INV 3 . The seventeenth transistor T 17  may be implemented with the P-type transistor. 
     An input end of a second inverter INV 2  may be connected to the first output terminal CH 2   o   1 , and an output end of the second inverter INV 2  may be connected to the second output terminal CH 2   o   2 . 
     An input end of a third inverter INV 3  may be connected to the second output terminal CH 2   o   2 , and an output end of the third inverter INV 3  may be connected to the first output terminal CH 2   o   1 . 
     An inverting signal CLKB of the clock signal CLK may be applied to a gate electrode of the seventeenth transistor T 17 , one electrode of the seventeenth transistor T 17  may be connected to a power source terminal of the second inverter INV 2  and a power source terminal of the third inverter INV 3 , and the other electrode of the seventeenth transistor T 17  may be connected to the second power source VDD. 
     The first output unit OUT 1  may determine an output voltage at the current time of the target channel CH 2 , based on the comparison result of the first comparator CPU 1 . The output voltage may correspond to at least one of a voltage applied to the first output terminal CH 2   o   1  and a voltage applied to the second output terminal CH 2   o   2 . For example, according to some example embodiments, the voltage applied to the first output terminal CH 2   o   1  is described as the output voltage. However, according to some example embodiments, the voltage applied to the second output terminal CH 2   o   2  may be used as the output voltage. Also, according to some example embodiments, the difference between the voltage applied to the first output terminal CH 2   o   1  and the voltage applied to the second output terminal CH 2   o   2  may be used as the output voltage. 
     The first output unit OUT 1  may serve as a latch. For example, when the inverting clock signal CLKB has the high level, the transistor T 17  may be turned on to maintain the voltages of the output terminals CH 2   o   1  and CH 2   o   2 . 
       FIG. 9  is a diagram illustrating a second comparator according to some example embodiments of the present disclosure. 
     Referring to  FIG. 9 , the second comparator CMP 2  according to some example embodiments of the present disclosure may include a second selector SLT 2 , a second comparator CPU 2 , and a second output unit OUT 2 . 
     The second selector SLT 2  may include transistors T 18  to T 25  and a fourth inverter INV 4 . The transistors T 18  to T 25  may be implemented with the N-type transistor. 
     The fourth inverter INV 4  may invert the determination value D 1 [m−1] of the data at the past time of the adjacent channel CH 1 . 
     The clock signal CLK may be applied to a gate electrode of an eighteenth transistor T 18 , one electrode of the eighteenth transistor T 18  may be connected to the first power source VSS, and the other electrode of the eighteenth transistor T 18  may be connected to one electrode of a nineteenth transistor T 19 . 
     A gate electrode of the nineteenth transistor T 19  may be connected to an output end of the fourth inverter INV 4 , the one end of the nineteenth transistor T 19  may be connected to the other electrode of the eighteenth transistor T 18 , and the other electrode of the nineteenth transistor T 19  may be connected to one electrode of a twentieth transistor T 20 . 
     The first reference voltage VH may be applied to a gate electrode of the twentieth transistor T 20 , the one electrode of the twentieth transistor T 20  may be connected to the other electrode of the nineteenth transistor T 19 , and the other electrode of the twentieth transistor T 20  may be connected to a third node N 3 . 
     The second reference voltage VL may be applied to a gate electrode of a twenty-first transistor T 21 , one electrode of the twenty-first transistor T 21  may be connected to the other electrode of the nineteenth transistor T 19 , and the other electrode of the twenty-first transistor T 21  may be connected to a fourth node N 4 . 
     The clock signal CLK may be applied to a gate electrode of the twenty-second transistor T 22 , one electrode of the twenty-second transistor T 22  may be connected to the first power source VSS, and the other electrode of the twenty-second transistor T 22  may be connected to one electrode of a twenty-third transistor T 23 . 
     The determination value D 1 [m−1] may be applied to a gate electrode of the twenty-third transistor T 23 , the one electrode of the twenty-third transistor T 23 , and the other electrode of the twenty-third transistor T 23  may be connected to one electrode of a twenty-fourth transistor T 24 . 
     The first reference voltage VH may be applied to a gate electrode of the twenty-fourth transistor T 24 , the one electrode of the twenty-fourth transistor T 24  may be connected to the other electrode of the twenty-third transistor T 23 , and the other electrode of the twenty-fourth transistor T 24  may be connected to the third node N 3 . 
     The second correction reference voltage VL+ may be applied to a gate electrode of a twenty-fifth transistor T 25 , one electrode of the twenty-fifth transistor T 25  may be connected to the other electrode of the twenty-third transistor T 23 , and the other electrode of the twenty-fifth transistor T 25  may be connected to the fourth node N 4 . 
     The second selector SLT 2  may select one of the second reference voltage VL and the second correction reference voltage VL+, based on the determination value D 1 [m−1]. 
     For example, the determination value D 1 [m−1] corresponds to the binary level 1, the nineteenth transistor T 19  may be turned off, and the twenty-third transistor T 23  may be turned on. When the clock signal CLK having the high level is applied, the third node N 3  may be connected to the first power source VSS through the transistors T 24 , T 23 , and T 22 , and the fourth node N 4  may be connected to the first power source VSS through the transistors T 25 , T 23 , and T 22 . Therefore, the first reference voltage VH has influence on the discharge speed of the third node N 3 , and the second correction reference voltage VL+ has influence on the discharge speed of the fourth node N 4 . 
     When the determination value D 1 [m−1] corresponds to the binary level 0, the nineteenth transistor T 19  may be turned on, and the twenty-third transistor T 23  may be turned off. When the clock signal CLK having the high level is applied, the third nod N 3  may be connected to the first power source VSS through the transistors T 20 , T 19 , and T 18 , and the fourth node N 4  may be connected to the first power source VSS through the transistors T 21 , T 19 , and T 18 . Therefore, the first reference voltage VH has influence on the discharge speed of the third node N 3 , and the second reference voltage VL has influence on the discharge speed of the fourth node N 4 . 
     The second comparator CPU 2  may include transistors T 26  to T 33 . Transistors T 30  and T 31  may be implemented with the P-type transistor, and transistors T 26 , T 27 , T 28 , T 29 , T 32 , and T 33  may be implemented with the N-type transistor. 
     The clock signal CLK may be applied to a gate electrode of a twenty-sixth transistor T 26 , one electrode of the twenty-sixth transistor T 26  may be connected to the first power source VSS, and the other electrode of the twenty-sixth transistor T 26  may be connected to one electrode of a twenty-seventh transistor T 27 . 
     The turn-on level voltage LogicH may be applied to a gate electrode of the twenty-seventh transistor T 27 , the one electrode of the twenty-seventh transistor T 27  may be connected to the other electrode of the twenty-sixth transistor T 26 , and the other electrode of the twenty-seventh transistor T 27  may be connected to one electrode of a twenty-eighth transistor T 28 . 
     The second input voltage CH 2 Ni may be applied to a gate electrode of the twenty-eighth transistor T 28 , the one electrode of the twenty-eighth transistor T 28  may be connected to the other electrode of the twenty-seventh transistor T 27 , and the other electrode of the twenty-eighth transistor T 28  may be connected to the fourth node N 4 . 
     The first input voltage CH 2 Pi may be applied to a twenty-ninth transistor T 29 , one electrode of the twenty-ninth transistor T 29  may be connected to the other electrode of the twenty-seventh transistor T 27 , and the other electrode of the twenty-ninth transistor T 29  may be connected to the third node N 3 . 
     The clock signal CLK may be applied to a gate electrode of a thirtieth transistor T 30 , one electrode of the thirtieth transistor T 30  may be connected to the fourth node N 4 , and the other electrode of the thirtieth transistor T 30  may be connected to the second power source VDD. The voltage level of the second power source may be larger than that of the first power source VSS. 
     The clock signal CLK may be applied to a gate electrode of a thirty-first transistor T 31 , one electrode of the thirty-first transistor T 31  may be connected to the third node N 3 , and the other electrode of the thirty-first transistor T 31  may be connected to the second power source VDD. 
     A gate electrode of a thirty-second transistor T 32  may be connected to the fourth node N 4 , one electrode of the thirty-second transistor T 32  may be connected to the first power source VSS, and the other electrode of the thirty-second transistor T 32  may be connected to a third output terminal CH 2   o   3 . 
     A gate electrode of a thirty-third transistor T 33  may be connected to the third node N 3 , one electrode of the thirty-third transistor T 33  may be connected to the first power source VSS, and the other electrode of the thirty-third transistor T 33  may be connected to a fourth output terminal CH 2   o   4 . 
     The second comparator CPU 2  may compare the difference between a voltage selected from the second reference voltage VL and the second correction reference voltage VL+ and the first reference voltage VH with an input voltage at the current time of the target channel CH 2 . 
     In some example embodiments, the input voltage is a differential signal, and may include the first input voltage CH 2 Pi and the second input voltage CH 2 Ni. The second comparator CPU 2  may compare the difference between the first input voltage CH 2 Pi and the second input voltage CH 2 Ni with the difference between the voltage selected from the second reference voltage VL and the second correction reference voltage VL+ and the first reference voltage VH. 
     First, when the clock signal CLK has the low level, the thirtieth transistor T 30  may be turned on to charge the fourth node N 4  with the voltage of the second power source VDD. In addition, the thirty-first transistor T 31  may be turned on to charge the third node N 3  with the voltage of the second power source VDD. 
     Next, when the clock signal CLK has the high level, the fourth node N 4  may be connected to the first power source VSS through the transistors T 28 , T 27 , and T 26 , and the first node N 1  may be connected to the first power source VSS through the transistors T 29 , T 27 , and T 26 . 
     Referring to description of the second selector SLT 2 , when the determination value D 1 [m−1] corresponds to the binary level 0, the discharge speed of the third node N 3  increases when the magnitude of the first reference voltage VH and the first input voltage CH 2 Pi increases, and the discharge speed of the fourth node N 4  increases when the magnitude of the second reference voltage VL and the second input voltage CH 2 Ni increases. 
     For example, at the sampling times sy 1 _ d , sp 2 _ d , sp 4 _ d , and sp 5 _ d  of  FIG. 5 , the following Equation 3 is satisfied, and therefore, the discharge speed of the fourth node N 4  may be faster than that of the third node N 3 .
 
CH2Ni-CH2Pi&gt;VH−VL  Equation 3
 
     When the fourth node N 4  is first discharged, the thirty-second transistor T 32  may be turned off. Because the thirty-third transistor T 33  is still in the turn-on state, the voltage of the first power source VSS is output to the fourth output terminal CH 2   o   4 , and the voltage of the second power source VDD is output to the third output terminal CH 2   o   3  by inverters INV 5  and INV 6 . A voltage of the fourth output terminal CH 2   o   4  may be used as the output value of the second comparator CMP 2 . When the voltage of the first power source VSS is output from the fourth output terminal CH 2   o   4 , the output value of the second comparator CMP 2  may be determined as the binary level 0. 
     However, as the value of CH 2 Ni-CH 2 Pi decreases due to the electromagnetic interference EMIb at the sampling time sp 3 _ d  of  FIG. 5 , Equation 3 may not be satisfied. The discharge speed of the third node N 3  is faster than that of the fourth node N 4 , and therefore, the second comparator CMP 2  may output the binary level 1. 
     Thus, according to some example embodiments, the following Equation 4 is satisfied at the sampling time sp 3 _ d  of  FIG. 5 , so that the second comparator CMP 2  can output the binary level 0 in spite of the electromagnetic interference EMIb.
 
CH2Ni-CH2Pi&gt;VH−(VL+)  Equation 4
 
     According to Equation 4, although the value of CH 2 Ni-CH 2 Pi decreases due to the electromagnetic interference EMIb at the sampling time sp 3 _ d , the value of VH− (VL+) also decreases as compared with the value of VH−VL, and therefore, Equation 4 may be satisfied. 
     The second output unit OUT 2  may include a thirty-fourth transistor T 34  and the inverters INV 5  and INV 6 . The thirty-fourth transistor T 34  may be implemented with the P-type transistor. 
     An input end of a fifth inverter INV 5  may be connected to the third output terminal CH 2   o   3 , and an output end of the fifth inverter INV 5  may be connected to the fourth output terminal CH 2   o   4 . 
     An input end of a sixth inverter INV 6  may be connected to the fourth output terminal CH 2   o   4 , and an output end of the sixth inverter INV 6  may be connected to the third output terminal CH 2   o   3 . 
     The inverting signal CLKB of the clock signal CLK may be applied to a gate electrode of the thirty-fourth transistor T 34 , one electrode of the thirty-fourth transistor T 34  may be connected to a power source terminal of the fifth inverter INV 5  and a power source terminal of the sixth inverter INV 6 , and the other electrode of the thirty-fourth transistor T 34  may be connected to the second power source VDD. 
     The second output unit OUT 2  may determine an output voltage at the current time of the target channel CH 2 , based on the comparison result of the second comparator CPU 2 . The output voltage may correspond to at least one of a voltage applied to the third output terminal CH 2   o   3  and a voltage applied to the fourth output terminal CH 2   o   4 . For example, according to some example embodiments, the voltage applied to the fourth output terminal CH 2   o   4  is described as the output voltage. However, according to some example embodiments, the voltage applied to the third output terminal CH 2   o   3  may be used as the output voltage. Also, according to some example embodiments, the difference between the voltage applied to the third output terminal CH 2   o   3  and the voltage applied to the fourth output terminal CH 2   o   4  may be used as the output voltage. 
     The second output unit OUT 2  may serve as a latch. For example, when the inverting clock signal CLKB has the high level, the transistor T 34  may be turned on to maintain the voltages of the output terminals CH 2   o   3  and CH 2   o   4 . 
       FIG. 10  is a diagram illustrating a receiving unit according to some example embodiments of the present disclosure. 
     Referring to  FIG. 10 , the receiving unit RX 2 ′ is different from the receiving unit RX 2  in that first and second comparators CMP 1 ′ and CMP 2  refer to not only the determination value D 1 [m−1] of the data at the past time of the adjacent channel CH 1  but also a determination value D 3 [m−1] of data at a past time of an adjacent channel CH 3 . 
     Referring to  FIG. 1 , a physical distance between the target channel CH 2  and the adjacent channel CH 3  may be similar to that between the target channel CH 2  and the adjacent channel CH 1 . That is, the adjacent channels CH 1  and CH 3  correspond to channels most adjacent to the target channel CH 2 , and provide the largest electrical interference to the target channel CH 2 . 
     Therefore, the receiving unit RX 2 ′ of this embodiment may be designed to consider not only electromagnetic interference with respect to the adjacent channel CH 1  but also electromagnetic interference with respect to the adjacent channel CH 3 . 
       FIG. 11  is a diagram illustrating a driving method of the receiving unit according to some example embodiments of the present disclosure. 
     Referring to  FIG. 11 , when the determination values D 1 [m−1] and D 3 [m−1] of the data at the past times of the adjacent channels CH 1  and CH 3  correspond to the binary level 0, the first comparator CMP 1 ′ may compare the first correction reference voltage VH− and the sampling signal of the target channel CH 2 . In the other cases, the first comparator CMP 1 ′ may compare the first reference voltage VH and the sampling signal of the target channel CH 2 . 
     In addition, when the determination values D 1 [m−1] and D 3 [m−1] of the data at the past times of the adjacent channels CH 1  and CH 3  correspond to the binary level 1, the second comparator CMP 2 ′ may compare the second correction reference voltage VL+ and the sampling signal of the target channel CH 2 . In the other cases, the second comparator CMP 2 ′ may compare the second reference voltage VL and the sampling signal of the target channel CH 2 . 
       FIG. 12  is a diagram illustrating a first comparator according to some example embodiments of the present disclosure. 
     Referring to  FIG. 12 , the first comparator CMP 1 ′ is substantially identical to the first comparator CMP 1 , except that a first selector SLT 1 ′ further includes a first NOR gate NOR 1 , and the connection configuration of a first inverter INV 1 ′ and transistors T 2 ′ and T 6 ′ is changed. Therefore, overlapping descriptions will be omitted. 
     The first selector SLT 1 ′ may select one of the first reference voltage VH and the first correction reference voltage VH−, based on the determination value D 1 [m−1] of the data at the past time of the adjacent channel CH 1  and the determination value D 3 [m−1] of the data at the past time of the adjacent channel CH 3 . 
     The first NOR gate NOR 1  may receive the determination value D 1 [m−1] and the determination value D 3 [m−1]. 
     An output value of the first NOR gate NOR 1  may be applied to a gate electrode of a second transistor T 2 ′, one electrode of the second transistor T 2 ′ may be connected to the other electrode of the first transistor T 1 , and the other electrode of the second transistor T 2 ′ may be connected to the one electrode of the third transistor T 3 . 
     The first inverter INV 1 ′ may invert the output value of the first NOR gate NOR 1 . 
     A gate electrode of a sixth transistor T 6 ′ may be connected to an output end of the first inverter INV 1 ′, one electrode of the sixth transistor T 6 ′ may be connected to the other electrode of the fifth transistor T 5 , and the other electrode of the sixth transistor T 6 ′ may be connected to the one electrode of the seventh transistor T 7 . 
       FIG. 13  is a diagram illustrating a second comparator according to some example embodiments of the present disclosure. 
     Referring to  FIG. 13 , the second comparator CMP 2 ′ is substantially identical to the second comparator CMP 2 , except that a second selector SLT 2 ′ further includes a first NAND gate NAND 1 , and the connection configuration of a fourth inverter INV 4 ′ and transistors T 19 ′ and T 23 ′ is changed. Therefore, overlapping descriptions will be omitted. 
     The first NAND gate NAND 1  may receive the determination value D 1 [m−1] and the determination value D 3 [m−1]. 
     The fourth inverter INV 4 ′ may invert an output value of the first NAND gate NAND 1 . 
     The output value of the first NAND gate NAND 1  may be applied to a gate electrode of a nineteenth transistor T 19 ′, one electrode of the nineteenth transistor T 19 ′ may be connected to the other electrode of the eighteenth transistor T 18 , and the other electrode of the nineteenth transistor T 19 ′ may be connected to the one electrode of the twentieth transistor T 20 . 
     A gate electrode of a twenty-third transistor T 23 ′ may be connected to an output end of the fourth inverter INV 4 ′, one electrode of the twenty-third transistor T 23 ′ may be connected to the other electrode of the twenty-second transistor T 22 , and the other electrode of the twenty-third transistor T 23 ′ may be connected to the one electrode of the twenty-fourth T 24 . 
     In the comparator and the receiver including the same according to the present disclosure, the influence of crosstalk caused by an adjacent channel can be minimized or reduced. 
     Aspects of some example embodiments have been disclosed herein, and although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purpose of limitation. In some instances, as would be apparent to one of ordinary skill in the art as of the filing of the present application, features, characteristics, and/or elements described in connection with a particular embodiment may be used singly or in combination with features, characteristics, and/or elements described in connection with other embodiments unless otherwise specifically indicated. Accordingly, it will be understood by those of skill in the art that various changes in form and details may be made without departing from the spirit and scope of the present disclosure as set forth in the following claims and their equivalents.