Patent Publication Number: US-2022224350-A1

Title: Multi-bit resolution sub-pipeline structure for measuring jump magnitude of transmission curve

Description:
CROSS REFERENCE TO RELATED APPLICATION 
     This is a Sect. 371 National Stage of PCT International Application No. PCT/CN2020/070596, filed on Jan. 7, 2020, which claims the benefit of priority to Chinese Patent Application No. CN 2019104549487, entitled “MULTI-BIT RESOLUTION SUB-PIPELINE STRUCTURE FOR MEASURING JUMP MAGNITUDE OF TRANSMISSION CURVE”, filed with CNIPA on May 29, 2019, the disclosure of which is incorporated herein by reference in its entirety. 
    
    
     FIELD OF TECHNOLOGY 
     The present invention relates to the technical field of integrated circuits, and in particular to a multi-bit resolution sub-pipeline structure for measuring a jump magnitude of a transmission curve, relating to a switched-capacitor based sub-pipeline structure that can be directly applied to a pipelined analog-to-digital converter (A/D converter). 
     BACKGROUND 
     In recent years, pipelined A/D converters have become popular in the fields such as high-performance video, medical imaging, and wireless or wired communications, because pipeline A/D converters can achieve a high sampling rate while achieving high precision, both of which benefit from pipeline technology adopted in the pipeline A/D converters. A basic feature of the pipeline technology is cascading multiple stages of low-precision high-sampling-rate A/D converters and processing digital outputs of each stage of sub-pipeline according to a certain algorithm to obtain a final coded output. Functional units of each stage of a pipelined A/D converter are shown in  FIG. 1( a ) , mainly consisting of a sub-ND converter (SubADC), a sub-D/A converter (SubDAC), a subtraction unit, and a multiplication unit. The sub-ND converter quantizes and encodes an input analog voltage signal V in  to obtain a digital output D 0 ; the sub-D/A converter performs digital-to-analog conversion on the output D o  of the sub-ND converter to obtain an analog output voltage D(V in ); and the output D(V in ) of the sub-D/A converter is subtracted from the input voltage V in  and the result is amplified G times to obtain a residual output voltage signal V res . In contemporary mixed-signal integrated circuit designs, the sub-D/A converter, the subtraction unit, and the multiplication unit are all implemented with switched capacitors, and such a switched-capacitor circuit is called a multiplying D/A converter (MDAC). A typical transmission function curve of a sub-ND converter when a quantization precision of the sub-ND converter is 1 bit is shown in  FIG. 1( b ) , in which a decision level of the sub-A/D converter is 0V; when the input voltage signal V in  is less than 0V, the output D O  of the sub-ND converter is at a logic zero level (D O =0), and in this case the highest point of the residual output voltage signal V res  is a voltage signal V a  corresponding to the point A; when the input voltage V in  is greater than 0V, the output D O  of the sub-ND converter is at a logic high level (D O =1), and in this case the lowest point of the residual output voltage signal V res  is a voltage signal V b  corresponding to the point B; and a jump magnitude of the transmission curve at the decision level is V a -V b  and the jump magnitude is related to a ratio between capacitors in the MDAC. Due to the influence of manufacturing process deviations, the capacitance values of the capacitors in the MDAC deviate from ideal values, which leads to a deviation of the difference of V a -V b  from its ideal value. This error affects the linearity and other performance indicators of the A/D converter. To deal with the influence of the errors on the performance of the A/D converter, it is necessary to measure an actual magnitude of the transmission curve at the decision level and compensate for the errors. 
     However, the traditional measurement method (see IEEE Journal of Solid-State Circuits, vol. 28, pp. 1207-1215, December 1993) is: first, fixing the analog input voltage signal V in  at zero volt and maintain the input to the sub-D/A converter SubDAC at a logic zero level to obtain a corresponding voltage signal V a  of the residual output curve at the point A, and second, fixing the analog input voltage signal V in  at zero volt and maintain the input to the sub-D/A converter SubDAC at a logic high level to obtain a corresponding voltage signal V b  of the residual output curve at the point B, and the difference of V a -V b  is an actual magnitude of the transmission curve. In contemporary high-speed high-precision pipeline ND converter product design, the first-stage sub-pipeline adopts a multi-bit resolution structure to enable the A/D converter to have optimal characteristics such as lower power consumption and higher precision. Therefore, there is an urgent need for a multi-bit resolution sub-pipeline structure for measuring a jump magnitude of a transmission curve. 
     SUMMARY 
     The present invention provides a multi-bit resolution sub-pipeline structure for measuring a jump magnitude of a transmission curve, including: 
     a sub-analog-to-digital converter having n-bit resolution (i.e., an n-bit sub-ADC) configured to quantize input analog voltage signals under a clock signal and a digital control signal and output digital voltage signals, respectively, wherein the analog voltage signals include an in-phase analog voltage signal V inp  and an inverted analog voltage signal V inn ; a positive reference voltage V REFP , and a negative reference voltage V REFN ; 
     a first sub-digital-to-analog converter and a second sub-digital-to-analog converter having n-bit resolution (i.e., an n-bit first sub-DAC, and an n-bit second sub-DAC), each configured to correspondingly convert the digital voltage signals output by the sub-analog-to-digital converter into analog voltage signals, respectively; 
     a decoder having n-bit resolution (i.e., an n-bit decoder) configured to decode an n-bit binary input signal and output a digital control signal; and 
     a switched-capacitor amplification unit configured to, when in a normal mode, perform sampling and residue amplification on the input analog voltage signal; and 
     when in a test mode, measure the jump magnitude of the transmission curve corresponding to each decision level. 
     As described above, the multi-bit resolution sub-pipeline structure for measuring a jump magnitude of a transmission curve of the present invention has the following beneficial effects: 
     The present invention can achieve magnitude measurement of the transmission curve within 2 n  (n is the resolution of the sub-pipeline, and n≤4 for the sub-ND converters of different stages of a current pipeline A/D converter) clock periods (Ts=1/fs, where fs is a working clock frequency of the pipeline), thereby providing a fast measurement speed; and a measurement result is sent to a back-end digital domain of the A/D converter for correction, thereby improving the linearity of the A/D converter by 10-15 dB after the correction. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1 -( a ) is a functional block diagram of a sub-pipeline provided in the present invention; 
         FIG. 1 -( b ) is a schematic diagram of a transmission curve of a sub-pipeline having 1-bit resolution provided in the present invention; 
         FIG. 2  is a general diagram of a sub-pipeline with a function of measuring a magnitude of a transmission curve provided in the present invention; 
         FIG. 3  is a circuit diagram of a sub-ND converter having n-bit resolution provided in the present invention; 
         FIG. 4  is a diagram of a resistive voltage divider provided in the present invention; 
         FIG. 5  is a diagram of a comparator array with a buffer array provided in the present invention; 
         FIG. 6  is a circuit diagram of an output buffer of a comparator provided in the present invention; 
         FIG. 7  is a circuit diagram of a tri-state output NOT gate provided in the present invention; 
         FIG. 8  is a circuit diagram of a sub-D/A converter provided in the present invention; 
         FIG. 9  is a circuit diagram of a switched-capacitor D/A converter provided in the present invention; 
         FIG. 10  is an operating timing diagram in a normal mode provided in the present invention; 
         FIG. 11  is a schematic diagram of a typical transmission curve provided in the present invention; and 
         FIG. 12  is an operating timing diagram in a test mode provided in the present invention. 
     
    
    
     DETAILED DESCRIPTION 
     Embodiments of the present invention will be described below with specific examples, and other advantages and effects of the present invention will be readily apparent to those skilled in the art from the disclosure in the specification. The present invention may also be carried out or applied in other different specific embodiments, and various modifications or changes may also be made to the details in the specification based on different ideas and applications without departing from the spirit of the present invention. It is to be noted that the following embodiments and features in the embodiments may be combined with each other if no conflicts will result. 
     It is to be noted that drawings provided in the following embodiments only schematically illustrate the basic idea of the present invention, so the drawings only show components related to the present invention, and are not drawn according to the numbers, shapes and sizes of the components in actual implementation; the forms, numbers and proportions of the components in actual implementation may be adjusted as needed; and the layout of the components may be more complex. 
     Referring to  FIG. 2 , which is a general diagram of a sub-pipeline with a function of measuring a magnitude of a transmission curve provided in the present invention, the sub-pipeline includes: 
     a sub-analog-to-digital converter having n-bit resolution (i.e., SubADC, or Sub-A/D converter) configured to quantize input analog voltage signals under a clock signal and a digital control signal and output digital voltage signals, respectively, wherein the analog voltage signals include an in-phase analog voltage signal V inp  and an inverted analog voltage signal V inn ; and a positive reference voltage V REFP  and a negative reference voltage V REFN ; 
     a first sub-digital-to-analog converter and a second sub-digital-to-analog converter (SubDAC, or Sub-D/A converter) having n-bit resolution, each configured to correspondingly convert the digital voltage signals output by the sub-analog-to-digital converter into corresponding analog voltage signals, respectively; 
     a decoder having n-bit resolution configured to decode an n-bit binary input signal and output the digital control signal; and 
     a switched-capacitor amplification unit configured to, when in a normal mode, perform sampling and residue amplification on the input analog voltage signals; and when in a test mode, measure the jump magnitude of the transmission curve corresponding to each decision level. 
     From the standpoint of a developer, the modes may be construed as the normal mode and the test mode. However, for a user, by introducing the n-bit input decoder unit, introducing a NON gate G1 and tri-state NON gates G2 and G3 in a comparator output buffer, and allowing MOS switches M6 and M7 of the switched-capacitor amplification unit to have different operating states in the normal mode and the test mode, the sub-pipeline structure not only can perform common analog-to-digital conversion and residual amplification functions, but also can effectively measure the jump magnitude of the transmission curve corresponding to each decision level to improve the linearity of the time-interleaved analog-to-digital converter when analog input signals have high-frequencies. 
     In the above embodiment, as shown in  FIG. 3 , which illustrates a sub-A/D converter having n-bit resolution provided in the present invention, the sub-A/D converter includes: 
     at least two resistive voltage dividers, configured to provide 2 n −1 positive reference voltages and 2 n −1 negative reference voltages, respectively, to a comparator array; and 
     a comparator array connected to the at least two resistive voltage dividers, to compare the input in-phase analog voltage signal V inp  and inverted analog voltage signal V inn  with the 2 n −1 positive reference voltages and 2 n −1 negative reference voltages, respectively, and quantize the analog voltage signals and output 2 n −1 digital voltage signals at each of four ports. 
     Specifically, as shown in  FIG. 4 , which illustrates one of the at least two resistive voltage dividers, which includes an input terminal V RN , an input terminal V RP , 2 n  resistors and 2 n −1 output terminals, where n is a natural number greater than zero; one end of a first resistor R1 is connected to the input terminal V RN  connected to the negative reference voltage V REFN , and the other end of the first resistor R1 is connected to a first output terminal, and so on; and a (2n −1 )th output terminal is connected between a (2 n )th resistor R2 n  and a (2 n-1 )th resistor R2 n-1 , and the other end of the (2 n )th resistor R2 n  is connected to the input terminal V RP  connected to the positive reference voltage V REFP . In addition, each resistor R 1  (i=2, . . . , 2 n −1) has a same designed resistance value which is equal to R ohms, and the resistor R 1  and the resistor R 2   n  have the same resistance design value which is equal to (2 n −2 n-1 +1)×R ohms. 
     Specifically, as shown in  FIG. 5 , which is a diagram of the comparator array with a buffer array, provided in the present invention, detailed description is as follows: 
     The comparator array includes 2 n −1 comparators, and 2 n −1 buffers which form a buffer array. 
     Each comparator has a first input terminal V in , connected to the in-phase analog voltage V inp , a second input terminal V in+  connected to the inverted analog voltage V inn , a third input terminal V ref+  connected to the positive reference voltage V REFP , and a fourth input terminal V ref−  connected to the negative reference voltage V REFN , to compare the magnitudes of the input analog voltages with those of the reference voltages, and correspondingly output, at a first output terminal OP and a second output terminal ON thereof, an in-phase digital voltage signal and an inverted digital voltage signal; specifically, the comparator is a fully differential comparator, and may be a comparator with a switched-capacitor structure or a dynamic comparator. 
     Each buffer is an output buffer for a corresponding comparator of the comparator array, and each buffer has a first input terminal and a second input terminal correspondingly connected to the in-phase digital voltage signal and the inverted digital voltage signal output by a corresponding comparator, a third input terminal connected to the digital control signal in the sub-A/D converter, and a fourth input terminal connected to the clock signal, wherein the buffer provides drive and test capabilities for switches in the sub-D/A converters, and outputs digital voltage signals at a first output terminal, a second output terminal, a third output terminal, and a fourth output terminal thereof. 
     In one embodiment, by changing the resolution of the sub-ND converter, the number of comparators in the sub-ND converter and ratios between capacitors in the switched-capacitor amplification unit, the present invention can implement a multi-bit sub-pipeline with a redundancy function, in which the A/D converter has a logic calibration function, which provides flexibility when designing the converter. 
     Specifically, as shown in  FIG. 6 , which is a diagram of an output buffer of a comparator provided in the present invention, each buffer includes a first NOT gate G1, a second NOT gate G6, a third NOT gate G7, a first tri-state NOT gate G2, a second tri-state NOT gate G3, a first NAND gate G4, a second NAND gate G5, a PMOS transistor M 16  and an NMOS transistor M 17 ; the third input terminal of the buffer is connected to an input terminal of the first NOT gate, an input terminal B of the first tri-state NOT gate, an input terminal B of the second tri-state NOT gate and a gate of the NMOS transistor M 17 , and an output terminal of the first NOT gate is connected to an input terminal C of the first tri-state NOT gate, an input terminal C of the second tri-state NOT gate and a gate of PMOS transistor M 16 ; an input terminal A of the first tri-state NOT gate and an input terminal A of the second tri-state NOT gate are correspondingly connected to the second input terminal and the first input terminal of the buffer; an output terminal of the first tri-state NOT gate is connected to a drain of the PMOS transistor M 16  and an input terminal A of the first NAND gate, and an output terminal of the second tri-state NOT gate is connected to a drain of the PMOS transistor M 17  and an input terminal B of the second NAND gate; wherein a source of the PMOS transistor M 16  is connected to a digital power supply, and a source of the NMOS transistor M 17  is grounded; the fourth input terminal of the buffer is connected to the input terminal B of the first NAND gate and an input terminal A of the second NAND gate; the first NAND gate outputs a first digital voltage signal Y1, and the first digital voltage signal Y1 is processed by the second NOT gate to output a second digital voltage signal Y2; and the second NAND gate outputs a fourth digital voltage signal Y4, and the fourth digital voltage signal Y4 is processed by the third NOT gate to output a third digital voltage signal Y3. 
     Specifically, as shown in  FIG. 7 , which is a circuit diagram of a tri-state NOT gate provided in the present invention, the tri-state NOT gate includes PMOS transistors M 18  and M 19 , and NMOS transistors M 20  and M 21 ; the input terminal A of the tri-state NOT gate is connected to gates of the PMOS transistor M 18  and the NMOS transistor M 21 , and the input terminal B of the tri-state NOT gate is connected to a gate of the PMOS transistor M 19 , and the input terminal C of the tri-state NOT gate is connected to a gate of the NMOS transistor M 20 ; a source of the PMOS transistor M 18  is connected to the digital power supply and a drain thereof is connected to a source of the PMOS transistor M 19 , and drains of the PMOS transistor M 19  and the NMOS transistor M 20  are interconnected and serve as the output terminal of the tri-state NOT gate; and a source of the NMOS transistor M 20  is connected to a drain of the NMOS transistor M 21 , and a source of the NMOS transistor M 21  is grounded. 
     In this embodiment, by introducing the NOT gate G 1 , the tri-state NOT gate G 2  and the tri-state NOT gate G 3  as well as the control signal A3 into the output buffer of a comparator, the, so that the input to each switched-capacitor DA unit in the sub-D/A converters in a holding stage is either the positive reference voltage V REFP  or the negative reference voltage V REFN . All these functions are implemented in the digital domain in a simple and flexible manner without increasing the design complexity in the analog domain. 
     In addition, the comparator in the sub-ND converter of the present invention may be a comparator with a switched-capacitor structure or a dynamic comparator, and thus the present invention is applicable to a pipelined A/D converter without a sample-and-hold structure and a pipelined A/D converter with a sample-and-hold structure. 
     Referring to  FIG. 8 , which is a circuit diagram of a sub-D/A converter provided in the present invention, which includes a first sub-digital-to-analog converter and the second sub-digital-to-analog converter. 
     The first sub-D/A converter and the second sub-D/A converter are each configured to perform digital-to-analog conversion on the input digital voltage signals, have input terminals G 1 , G 2  and G 3  as digital voltage signal input terminals, input terminals V 1  as analog voltage signal input terminals, and input terminals V 2  and V 3  as reference voltage signal input terminals; and each sub-analog-to-digital converter includes 2 n −1 switched-capacitor DAC units, and each switched-capacitor DAC unit includes input terminals G 1 , G 2 , G 3 , V 1 , V 2 , and V 3 . 
     The input terminal G 1  of an ith switched-capacitor DAC unit DA(i) (i=1, 2 n −1) is connected to an input terminal (I), the input terminal V 1  of the ith switched-capacitor DAC unit DA(i) is connected to an input terminal V in , the input terminal G 2  of the ith switched-capacitor DAC unit DA(i) is connected to an input terminal CK1&lt;i&gt;, the input terminal V 2  of the ith switched-capacitor DAC unit DA(i) is connected to an input terminal V RN , the input terminal G 3  of the ith switched-capacitor DAC unit DA(i) is connected to an input terminal CK2&lt;i&gt;, the input terminal V 3  of the ith switched-capacitor DAC unit DA(i) is connected to an input terminal V RP , and an output terminal D of the ith switched-capacitor DAC unit DA(i) is connected to an output terminal V C . 
     Specifically, as shown in  FIG. 9 , which is a circuit diagram of a switched-capacitor DAC provided in the present invention, the switched-capacitor DAC unit includes NMOS switching transistors M 22  and M 23 , a PMOS switching transistor M 24 , and a capacitor C U ; the digital voltage signal input terminals G 1 , G 2  and G 3  of the switched-capacitor DAC unit are correspondingly connected to gates of the NMOS switching transistors M 22  and M 23  and the PMOS switching transistor M 24 ; the analog voltage signal input terminals V 1  and V 2  of the switched-capacitor DAC unit are correspondingly connected to drains of the NMOS switching transistors M 22  and M 23 , and the analog voltage signal input terminal V 3  of the switched-capacitor DAC unit is connected to a source of PMOS switching transistor M 24 ; and sources of the NMOS switching transistors M 22  and M 23  and the drain of the PMOS switching transistor M 24  are jointly connected to the capacitor C U , and the other end of the capacitor C U  is the output terminal of switched-capacitor DAC unit. 
     Specifically, as shown in  FIG. 2 , the first sub-D/A converter and the second sub-D/A converter are respectively connected to the sub-ND converter as follows: 
     The first sub-D/A converter includes an input terminal V in  connected to the in-phase analog voltage signal V inp , an input terminal V RP  connected to the positive reference voltage V REFP , an input terminal V RN  connected to the negative reference voltage V REFN , and clock input terminals connected to clock control signals; and based on inputs of 2 n −1 digital control signals from each of two output terminals DN1 and DP1, the first sub-D/A converter outputs 2 n −1 digital output voltage signals according to the clock control signals; and 
     The second sub-D/A converter includes an input terminal V in  connected to the inverted analog voltage signal V inn , an input terminal V in  connected to the inverted analog voltage signal V inn , an input terminal V RP  connected to the positive reference voltage V REFP , an input terminal V RN  connected to the negative reference voltage V REFN , and clock input terminals connected to clock control signals; and based on inputs of 2 n −1 digital control signals from each of two output terminals DN2 and DP2, the second sub-D/A converter outputs 2 n −1 digital output voltage signals according to the clock signals. 
     Specifically, as shown in  FIG. 2 , the switched-capacitor amplification unit includes sampling capacitors C 1 , C 2 , C 3 , C 4  and C 5 , NMOS switches M 1 , M 2 , M 3 , M 4 , M 5 , M 6 , M 7 , M 8 , M 9 , M 10 , M 11 , M 12 , M 13 , M 14  and M 15 , and a fully differential operational amplifier OTA, wherein one end of the capacitor C 1  is connected to an in-phase input terminal V 1+  of the fully differential operational amplifier OTA, and the other end of the capacitor C 1  is connected to a source of the MOS switch M 1  and a drain of M 10 ; one end of the capacitor C 2  is connected to the in-phase input terminal V 1+  of the fully differential operational amplifier OTA, and the other end of the capacitor C 2  is connected to a source of the MOS switch M 2  and a source of M 3 ; one end of the capacitor C 3  is connected to an inverted input terminal Vi− of the operational amplifier, and the other end of the capacitor C 3  is connected to a source of the MOS switch M 4  and a source of M 5 ; one end of the capacitor C 4  is connected to the inverted input terminal of the operational amplifier, and the other end of the capacitor C 4  is connected to a source of the MOS switch M 6 , a source of M 7  and a source of M 8 ; one end of the capacitor C 5  is connected to the inverted input terminal V i−  of the fully differential operational amplifier OTA, and the other end of the capacitor C5 is connected to a source of the MOS switch M 9  and a drain of M 14 ; the in-phase analog voltage signal V inp  is connected to drains of the NMOS switches M 1  and M 2 ; drains of the NMOS switches M 3  and M 4  are connected to the positive reference voltage V REFP ; the inverted analog voltage signal V inn  is connected to drains of the NMOS switches M 5 , M 8  and M 8 ; the positive reference voltage V REFP  is connected to a drain of the NMOS switch M 6 ; the negative reference voltage V REFN  is connected to a drain of the NMOS switch M 7 ; a drain of NMOS switch M 11  and a source of M 13  are connected to the in-phase input terminal V 1+  of the fully differential operational amplifier OTA; a drain of the NMOS switch M 12  and a drain of M 13  are connected to the inverted input terminal of the operational amplifier OTA; sources of the NMOS switches M 11  and M 12  are connected to an input terminal V B ; a source of the NMOS switch M 10  and a source of M 15  are connected to an output V outp ; a source of the NMOS switch M 14  and a drain of M 15  are connected to an output V outn ; an input terminal ϕ 1  is connected to gates of the NMOS switches M 1  and M 2 ; an input terminal ϕ7 is connected to gates of the NMOS switches M 3  and M 4 ; an input terminal ϕ 5  is connected to gates of the NMOS switches M 5 , M 8  and M 9 ; an input terminal ϕ 8  is connected to a gate of the NMOS switch M 6 ; an input terminal ϕ 9  is connected to a gate of the NMOS switch M 7 ; an input terminal ϕ 3  is connected to a gate of the NMOS switch M 10 ; an input terminal ϕ 4  is connected to a gate of the NMOS switch M 15 ; an input terminal ϕ 6  is connected to a gate of the NMOS switch M 14 ; and an input terminal ϕ 2  is connected to gates of the NMOS switches M 11 , M 12  and M 13 . 
     Specifically, the capacitance value of the capacitor C 2  is equal to the sum of the capacitance values of the capacitor C 3  and the capacitor C 4 , and the capacitance values of C 3  and C 4  are equal to ensure that normal residual amplification can be achieved in the normal mode (operating mode) and the jump magnitude can be measured in the test mode, as described below; and the fully differential operational amplifier OTA as used herein is a conventional high-precision high-speed operational amplifier. 
     In the above embodiment, the decoder is an n-bit decoder (n is the resolution of the sub-ND converter), and the decoder has n inputs and only 2 n −1 outputs; TI&lt;n&gt; is the highest bit, and TI&lt;1&gt; is the lowest bit; when the decimal representation of the decoder input TI&lt;n:1&gt; is equal to zero, the 2 n −1 outputs I&lt;2 n −1&gt; . . . I&lt;1&gt; are all at a zero level; and when the decimal representation of the decoder input TI&lt;n:1&gt; is equal to i (i=1, . . . , 2 n −1), the ith output I&lt;i&gt; of the decoder is equal to a high level, and the rest 2 n −2 outputs I&lt;2 n −1&gt; . . . I&lt;i+1&gt;I&lt;i−1&gt; . . . I&lt;1&gt; are all at a zero level. In normal/operating mode of the sub-pipeline, the n inputs of the decoder are all zero levels; in the test mode of the sub-pipeline, the inputs of the decoder traverse all logic input values, for a total of 2 n  states. 
     A schematic diagram of an operating timing relationship of the NMOS switches in the normal/operating mode of the present invention is shown in  FIG. 10 , in which clock control signals ϕ 1 , ϕ 2 , ϕ 4  and ϕ 5  are in the same phase, and clock control signals ϕ 3 , ϕ 6 , ϕ 7 , ϕ 8  and ϕ 10  are in the same phase, and ϕ 9  is always at a zero level, and in this mode: 
     When ϕ 1 , ϕ 2 , ϕ 4  and ϕ 5  are at a high level, the 2 n −1 outputs DP1&lt;2 n −1&gt; . . . DP1&lt;1&gt; and the 2 n −1 outputs DN2&lt;2 n −1&gt; . . . DN2&lt;1&gt; of the sub-ND converter are all at a high level, and the 2 n −1 outputs DP2&lt;2 n −1&gt; . . . DP2&lt;1&gt; and the 2 n −1 outputs DN1&lt;2 n −1&gt; . . . DN1&lt;1&gt; of the sub-A/D converter are all at a low level; the NMOS switches M 1 , M 2 , M 5 , M 8 , M 9 , M 11 , M 12 , M 13  and M 15  in the switched-capacitor amplification unit are on, and the NMOS transistors M 3 , M 4 , M 6 , M 7 , M 10  and M 14  in the switched-capacitor amplification unit are off; an in-phase analog voltage input signal V inp  is transmitted to one end of the sampling capacitor C 1  through the NMOS switch M 1  and to one end of the sampling capacitor C 2  through the NMOS switch M 2 ; an inverted analog voltage input signal V inn  is transmitted to one end of the sampling capacitor C 3  through the NMOS switch M 5 , to one end of the sampling capacitor C 4  through the NMOS switch M 8  and to one end of the sampling capacitor C 5  through the NMOS switch M 9 ; a bias voltage V B  is transmitted to the other ends of the sampling capacitors C 1  and C 2  and the in-phase input terminal V 1+  of the fully differential operational amplifier OTA through the NMOS switch M 11 , wherein the other ends of the sampling capacitors C 1  and C 2  are connected to each other, and the bias voltage V B  is transmitted to the other ends of the sampling capacitors C 3 , C 4  and C 5  and the inverted input terminal of the fully differential operational amplifier OTA through the NMOS switch M 12 , wherein the other ends of the sampling capacitor C 3 , C 4  and C 5  are connected to each other; the in-phase output terminal V outp  of the fully differential operational amplifier OTA is shorted to the inverted output terminal V outn  of the fully differential operational amplifier OTA through the NMOS switch M 15 , so the switched capacitor amplification unit differentially outputs a voltage signal V outp -V outn =0V; at the same time, the in-phase analog voltage input signal V 1  is transmitted to the sampling capacitor C U  through the NMOS switches in each switched-capacitor DAC unit in the first sub-D/A converter SubDAC(1); and the inverted analog voltage input signal V inn  is transmitted to the sampling capacitor C U  through the NMOS switches in each switched-capacitor DAC unit in the second sub-digital-to-analog converter SubDAC(2). 
     When ϕ t  ϕ 2 , ϕ 4  and ϕ 5  are at a low level, the 2 n −1 outputs DP1&lt;2 n −1&gt; . . . DP1&lt;1&gt;, the 2 n −1 outputs DP2&lt;2 n −1&gt; . . . DP2&lt;1&gt;, the 2 n −1 outputs DN1&lt;2 n −1&gt; . . . DN1&lt;1&gt; and the 2 n −1 outputs DN1&lt;2 n −1&gt;DN1&lt;1&gt; of the sub-ND converter are determined by the amplitudes of input signals; in the switched-capacitor amplification unit, the NMOS switches M 3 , M 4 , M 6 , M 10  and M 14  are on, and the NMOS switches M 1 , M 2 , M 5 , M 7 , M 8 , M 9 , M 11 , M 12 , M 13  and M 15  are off; the positive reference voltage V REFP  is transmitted to one end of the sampling capacitor C 2  through the NMOS switch M 3 , to one end of the sampling capacitor C 3  through the NMOS switch M 4  and to one end of the sampling capacitor C 4  through the NMOS switch M 6 ; one end of the sampling capacitor C 1  connected to the source of the NMOS transistor M 1  is connected to the in-phase output terminal V outp  through the NMOS switch M 10 , and one end of the sampling capacitor C 5  connected to the source of the NMOS transistor M 9  is connected to the inverted output terminal V outn  through the NMOS switch M 14 ; and according to the principle of charge conservation, in this case, the switched-capacitor amplification unit differentially outputs a voltage signal V outp -V outn  given by: 
     
       
         
           
             
               
                 
                   
                     
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                             ⁢ 
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                         . 
                       
                     
                   
                 
               
               
                 
                   ( 
                   1 
                   ) 
                 
               
             
           
         
       
     
     In equation (1), C 1  is the capacitance value of the capacitor C 1 ; C 2  is the capacitance value of the capacitor C 2 ; C 3  is the capacitance value of the capacitor C 3 ; C 4  is the capacitance value of the capacitor C 4 ; C 5  is the capacitance value of capacitor C 5 ; C U,1i  indicates the value of the sampling capacitor C U  in the ith switched-capacitor DA unit in the first sub-D/A converter SubDAC(1); C U,2i  indicates the value of the sampling capacitor C U  in the ith switched-capacitor DA unit in the second sub-D/A converter SubDAC(2); and k indicates that when (1) 10  is equal to a high level, only the in-phase output terminals of the 1st, 2 nd , . . . , and kth comparators in the comparator array are at a high level. 
     An ideal transmission curve of the sub-pipeline, as shown in  FIG. 11 , has a jump at each decision level, and the jump magnitude at the ith decision level is given by: 
     
       
         
           
             
               
                 
                   
                     
                       
                         V 
                         
                           H 
                           , 
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                       - 
                       
                         V 
                         
                           L 
                           , 
                           i 
                         
                       
                     
                     = 
                     
                       
                         ( 
                         
                           
                             
                               C 
                               
                                 U 
                                 , 
                                 li 
                               
                             
                             
                               C 
                               1 
                             
                           
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                                 , 
                                 
                                   2 
                                   ⁢ 
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                               5 
                             
                           
                         
                         ) 
                       
                       × 
                       
                         ( 
                         
                           
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                               ⁢ 
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                               ⁢ 
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                           - 
                           
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                         ) 
                       
                     
                   
                   . 
                 
               
               
                 
                   ( 
                   2 
                   ) 
                 
               
             
           
         
       
     
     A schematic diagram of an operating timing relationship of the NMOS switches in the test mode of the present invention is shown in  FIG. 12 , in which clock control signals ϕ 1 , ϕ 2 , ϕ 4  and ϕ 5  are in the same phase, and clock control signals ϕ 3 , ϕ 6 , ϕ 7 , ϕ 9  and ϕ 10  are in the same phase, and O 8  is always at a zero level. In this mode, the in-phase analog input voltage signal V inp  is fixed at −(V REF p−V REFN )/2 n  and the inverted analog input voltage signal V inn  is fixed at −(V REF p−V REFN )/2 n +1; when the decimal representation of the decoder input signal TI&lt;n:1&gt; is equal to 0 and ϕ 10  is equal to a high level, the 2 n −1 outputs DP1&lt;2 n −1:1&gt; and the 2 n −1 outputs DN2&lt;2 n −1:1&gt; of the comparator array are all at a high level, and the 2 n −1 outputs DP2&lt;2 n −1:1&gt; and the 2 n −1 outputs DN1&lt;2 n −1:1&gt; are all at a high level; and when the decimal representation of the decoder input signal TI&lt;n:1&gt; is equal to i (i=1, . . . , 2 n −1) and ϕ 10  is equal to a high level, the outputs DP2&lt;i&gt; and DN2&lt;i&gt; of the ith comparator in the comparator array are both at a high level and the outputs DP1&lt;i&gt; and DN1&lt;i&gt; thereof are both at a zero level, and among the rest outputs, the outputs DP2&lt;2 n −1&gt; . . . DP2&lt;i+1&gt;DP2&lt;i−1&gt; . . . DP2&lt;1&gt; and DN2&lt;2 n −1&gt; . . . DN2&lt;i+1&gt;DN2&lt;i−1&gt; . . . DN2&lt;1&gt; of the comparator array are all at a zero level, and the outputs DP1&lt;2 n −1&gt; . . . DP2&lt;i+1&gt;DP2&lt;i−1&gt; . . . DP2&lt;1&gt; and DN1&lt;2 n −1&gt; . . . DN1&lt;i+1&gt;DN1&lt;i−1&gt; . . . DN1&lt;1&gt; are all at a high level. In the test mode: 
     when ϕ 1 , ϕ 2 , ϕ 4  and ϕ 5  are at a high level, the states of the NMOS switches in the sub-D/A converters and the NMOS switches in the switched-capacitor amplification unit and the transmission characteristics of the input analog voltage signals are exactly the same as the states of the NMOS switches in the sub-D/A converters and the NMOS switches in the switched-capacitor amplification unit and the transmission characteristics of the input analog voltage signals in the normal mode, which will not be repeatedly described here; and 
     when ϕ 1 , ϕ 2 , ϕ 4  and ϕ 5  are at a low level, the NMOS switch M 6  is off and the NMOS switch M 7  is on in the switched-capacitor amplification unit, and the negative reference voltage V REFN  is transmitted to one end of the sampling capacitor C 4  through the MOS switch M 7 , and the states of the rest NMOS switches in the sub-D/A converter and the rest NMOS switches in the switched-capacitor amplification unit and the transmission characteristics of the input analog voltage signals are the same as the states of the rest NMOS switches in the sub-D/A converter and the rest NMOS switches in the switched-capacitor amplification unit and the transmission characteristics of the input analog voltage signals in the normal mode, which will not be repeated here; and according to the principle of charge conservation, in this case, when the decimal representation of the decoder input TI&lt;n:1&gt; is equal to 0, the switched-capacitor amplification unit differentially outputs a voltage signal V outp −V outn  as expressed by equation (3), and when the decimal representation of the decoder input TI&lt;n:1&gt; is equal to i (i=1, . . . , 2 n −1), the switched-capacitor amplification unit differentially outputs a voltage signal V outp −V outn  as expressed by equation (4): 
     
       
         
           
             
               
                 
                   
                     
                       
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                   ( 
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                                     = 
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                                   , 
                                   
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                           ⁢ 
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                           ⁢ 
                           F 
                           ⁢ 
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                   ( 
                   4 
                   ) 
                 
               
             
           
         
       
     
     The result of equation (3) minus equation (4) is equal to equation (2), i.e., the jump magnitude the transmission curve corresponding to the ith decision level. 
     In the present invention, in the normal mode, when the clock control signals ϕ 1 , ϕ 2 , ϕ 4  and ϕ 5  are at a low level, one end of the capacitor C 4  connected to the source of the NMOS switch M 6  is connected to the input terminal V REFP , and in the test mode, when the clock control signals ϕ 1 , ϕ 2 , ϕ 4  and ϕ 5  are at a low level, one end of the capacitor C 4  connected to the source of the NMOS switch M 7  is connected to the input terminal V REFN , for the purpose of ensuring that the swings of the outputs V outp  and V outn  of the switched-capacitor amplification unit in the test mode are the same as the swings of the outputs V outp  and V outn  of the switched-capacitor amplification unit in the normal operating mode. 
     In the invention, in the test mode, the in-phase analog input voltage signal V 1  is fixed at −(V REFP −V REFN )/2 n  and the inverted analog input voltage signal V inn  is fixed at −(V REFP −V REFN )/2 n +1, for the purpose of ensuring that the analog input voltage in the test mode is lower than the reference voltages of all comparators in the comparator array. 
     The jump magnitude of the transmission curve of the sub-pipeline corresponding to each decision level can be measured so long as the inputs of the decoder traverse all logic input values (for a total of 2 n  states) in the test mode. That is, the present invention can achieve magnitude measurement of the transmission curve within 2 n  (n is the resolution of the sub-pipeline, and n≤4 for sub-ND converters of stages of a current pipeline A/D converter) clock periods (Ts=1/fs, where fs is a working clock frequency of the pipeline), thereby providing a fast measurement speed; and a measurement result is sent to a back-end digital domain of the A/D converter for correction. Relatively speaking, the linearity of the A/D converter can be improved by 10-15 dB after the correction. 
     In summary, by changing the resolution of the sub-A/D converter, the number of comparators in the sub-A/D converter and ratios between capacitance values of capacitors in the switched-capacitor amplification unit, the present invention can implement a multi-bit sub-pipeline with a redundancy function, in which the ND converter has a logic calibration function, which improves the flexibility of the converter design; by introducing the NOT gate G1, the tri-state output NOT gate G2 and the tri-state output NOT gate G3 as well as a control signal A3 in an output buffer of a corresponding comparator unit, it can be forcibly implemented with the control signal A3 that an input to each switched-capacitor DA unit in the sub-D/A converters in a holding stage is the positive reference voltage V REFP  or the negative reference voltage V REFN , and all these functions are implemented in the digital domain in a simple and flexible manner without increasing the design complexity in the analog domain; a comparator in the sub-A/D converter may be a comparator with a switched-capacitor structure or a dynamic comparator, and thus the present invention is applicable to a pipelined A/D converter without a sample-and-hold structure and a pipelined A/D converter with a sample-and-hold structure; and the present invention can achieve magnitude measurement of the transmission curve within 2 n  (n is the resolution of the sub-pipeline, and n≤4 for sub-A/D converters of stages of a current pipeline A/D converter) clock periods (Ts=1/fs, where fs is a working clock frequency of the pipeline), thereby providing a fast measurement speed; and a measurement result is sent to a back-end digital domain of the A/D converter for correction, thereby improving the linearity of the A/D converter by 10-15 dB after the correction. Therefore, the present invention effectively overcomes various shortcomings of the prior art and has a high value for industrial use. 
     The above embodiments are merely illustrative of the principles of the present invention and effects thereof, and are not intended to limit the present invention. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical ideas disclosed in the present invention still fall within the scope of the claims of the present invention.