Patent Publication Number: US-11024354-B1

Title: Low power linear memory readout

Description:
BACKGROUND 
     This invention generally relates to reading electrical signals with low power consumption, and more specifically, to linearly amplifying electrical signals with low power consumption over a wide dynamic range. Embodiments of the invention are used to read low amplitude signals from memory cells. 
     SUMMARY 
     According to an embodiment of the invention, a circuit comprises a front end stage including an impedance conversion network for receiving a signal and providing voltage or current gain, and a wideband multiplier for receiving an output signal from the impedance conversion network and converting the output signal to differential output signals; and a baseband stage including a voltage mode mixer for receiving the differential output signals from the wideband multiplier and providing voltage gain, and a bandpass filter/amplifier for receiving a mixer output signal from the voltage mode mixer and filtering and amplifying the mixer output signal; and wherein DC voltages of the front-end stage are biased independently of a biasing of DC voltages of the baseband stage. 
     According to an embodiment of the invention, a method comprises receiving a signal at a front end stage of a signal readout circuit, including an impedance conversion network of the front end stage providing a voltage or current gain, and a wideband multiplier of the front end stage receiving an output signal from the impedance conversion network and converting the output signal to differential output signals; receiving the differential output signals at a baseband stage of the signal readout circuit, including a voltage mode mixer of the baseband stage providing voltage gain, and a bandpass filter/amplifier of the baseband stage receiving a mixer output signal from the voltage mode mixer and amplifying the mixer output signal; and biasing DC voltages of the front end stage and biasing DC voltages of the baseband stage, and wherein the biasing of the DC voltages of the front end stage is independent of the biasing of the DC voltages of the baseband stage. 
     Embodiments of the invention use a mixer based architecture followed by linear detector at a baseband filter. In embodiments, linear detector at baseband implies that the output of the detector is proportional to the input signal. Input and output in this context emphasize amplitude. So, the output amplitude is a linear function of the input amplitude. 
     Embodiments of the invention use passive amplification in the front-end of a low power memory readout, using inductive elements as an autotransformer. 
     Embodiments of the invention use independent biasing of the mixer and the baseband filter, and provide automatic DC offset cancellation due to the choice of the baseband filter. In embodiments, by construction of the baseband analog processing block (the baseband filter in this case), the capacitors that are used in the filter are in series with the signal propagation, thereby the capacitors block the incoming DC voltage. Hence, the DC offset from the previous blocks are blocked. 
     Embodiments of the invention achieve a flexible analog detection of the amplitude, phase, or frequency of a signal. 
     Embodiments of the invention provide a highly linear low power memory readout scheme due to a mixer first architecture. 
     Embodiments of the invention provide a linear memory readout system that may be used, for example, in MRAM/AI systems. According to an embodiment of the invention, a system comprises a mixer/multiplier front end biased using an inductor element. 
     In embodiments of the invention, the blocks in the mixer/multiplier front end, and the blocks in the gain and filtering section are independently biased with respect to their DC voltages. 
     In embodiments, the baseband filters can be cascaded without any DC buildup and amplification from the previous stages. 
     In embodiments, the capacitive elements used in the gain and filtering section not only provide DC independence, but are part of the filtering function itself. 
     In embodiments, a matching element in the mixer/multiplier front end can provide voltage or current gain and may use MRAM as an inductor. 
     In embodiments, the invention can be used to detect the amplitude, phase or frequency of low power signals read out from memory systems. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  illustrates a prior art circuit for reading low amplitude signals. 
         FIG. 2( a )  shows in more detail a mixer and a baseband filter of the circuit of  FIG. 1 . 
         FIG. 2( b )  shows a baseband filter that may be used in the circuit of  FIG. 1 , and including a fully differential construction. 
         FIG. 3  illustrates a low power circuit for linearly reading signals according to an embodiment of the invention. 
         FIG. 4  shows a baseband filter of the circuit of  FIG. 3 . 
         FIG. 5  shows a low power circuit for linearly reading signals using more than one stage of multiplication, according to another embodiment of the invention. 
         FIGS. 6A and 6B  illustrate frequency shifting in the signal in the process of multiplication, along with the baseband envelope being processed in the circuit of  FIG. 5 . 
         FIG. 7  shows details of a matching network construction in an embodiment of the invention. 
         FIGS. 8A-8F  shows results of a simulation of an embodiment of the invention. 
     
    
    
     DETAILED DESCRIPTION 
     Low power linear readout systems with high dynamic range are essential for next generation memory and sensor subsystems. Next generation memory and sensor elements typically operate around a narrow range of frequencies, and are typically similar to radio frequency (RF) type systems. There is a need to detect a small signal (similar to RF signals) and a need to offer a high dynamic range in the detection process. 
     A traditional readout method uses a sense-amplifier based detection that uses preamplification followed by a latch. This is a highly non-linear process. Also, a sense-amplifier method only works with the amplitude of the signal, and cannot detect frequency. There is a need to construct an ultra low power, linear detector for memory interfaces to detect amplitude, phase, and frequency for the next generation AI hardware solutions. 
       FIG. 1  shows a prior art circuit  100  for reading a low amplitude signal. Generally, circuit  100  comprises matching network  102 , low noise amplifier  104 , mixers  106 ,  110 , baseband filters  112  and  114 , and analog-to-digital converters  116 ,  120 . 
     In the implementation of circuit  100 , matching network  102  receives an input signal and matches the impedance of that signal to the impedance of the rest of circuit  100 . From matching network  102 , the signal is amplified by low noise amplifier  104  and then provided to mixers  106  and  110 . 
     In the depicted example, circuit  100  includes an in-phase channel  122  and a quadrature channel  124  for respectively processing real and imaginary signal components. For the in-phase channel, an in-phase mixer  106  downconverts the input RF signal to an in-phase baseband signal; and similarly, for the quadrature channel, a quadrature mixer  110  downconverts the input RF signal to a quadrature baseband signal. Both the in-phase and quadratue-phase channels receive the same RF signal at their input terminals. 
     In general, each of the mixers  106 ,  110  can include different types of mixer transistors (not shown) that operate with different biasing. For example, each of the mixers may include complementary switches comprising an n-channel metal-oxide semiconductor (NMOS) field-effect mixer transistor, and a p-channel metal-oxide semiconductor (PMOS) field-effect mixer transistor. To bias these different types of mixer transistors, circuit  100  can include a plurality of bias circuits (not shown), such as an NMOS bias circuit and a PMOS bias circuit. 
     In-phase mixer  106  applies a pair of output signals to in-phase baseband filter  112 , and quadrature mixer  110  applies a pair of output signals to quadrature baseband filter  114 . Filter  112  accepts the downconverted signals from mixer  106 , and filters the signals to produce filtered signals, which are applied to analog-to-digital converter  116 . Likewise, filter  114  accepts the downconverted signals from mixer  110 , and filters the signals to produce filtered signals that are applied to analog-to-digital converter  120 . 
     Analog-to-digital converter  116  converts the analog signals input from filter  112  to a digital output signal; and similarly, analog-to-digital converter  120  converts the analog input signals from filter  114  to a digital output signal. 
     With the system of  FIG. 1 , the mixers  106 ,  110  are biased through the matching network  102 , and the interfaces between the mixers and the baseband filters provide signal gain and blocker immunity. Current mode interface means that the baseband filter provides a low impedance at the input, while voltage mode interface means that the baseband filter provides a high impedance at the input. In traditional wireless communications, current mode interface is preferred, as the low impedance is used to implement less voltage swing in the event of a large blocker accompanying a small input signal. This is employed by using an OPAMP in feedback. One common construction is shown in  FIG. 2( a ) . A fully differential construction, an example of which is shown in  FIG. 2( b ) , is typically used. 
     In the construction of  FIG. 2( a ) , the input  202  is directly coupled to the mixer (or any previous blocks driving the baseband filter). The input voltage creates current that is given by V/R 1 , and is provided to the virtual ground of the baseband filter (virtual ground is created by connecting a feedback resistor between the outputs and the inputs of the OPAMP using negative feedback). 
       FIG. 2( b )  shows a baseband filter that may be used in the circuit  100  of  FIG. 1 , and including a fully differential construction. In a fully differential design, an inverting stage is not necessary, as inversion is typically achieved by flipping wires. In the construction of  FIG. 2( b ) , the input  252  is obtained from the mixer, and the baseband filer provides outputs at  254  and  256 . 
     In the circuit of  FIG. 1 , DC offset cancellation is needed at the input of the baseband filter to prevent saturation of the last stage, and the circuit consumes substantial amount of power. In differential signal processing, an input signal X is processed as two separate signal X/2 and −X/2, and provided to a differential amplifier. However, this amplifier is not perfect; it also has some intrinsic offset voltage, voff. So, the signals processed by the amplifier become (X/2+voff) and −X/2. These are amplified by the amplifier gain A, to obtain A*voff at the output, which is the “output DC offset” in response to the “input DC offset”. The DC offset needs to be cancelled/corrected before it is applied to the next stages. For example, three stages of amplification with each amplifier providing a gain of 10, will lead to a cascaded gain of 1000, and will amplify a DC offset of 1 mV to 1V, leaving very minimum room for the signal to be processed. Typically, a current steering digital to analog converter (DAC) provides current to the input nodes of the baseband filter (the virtual ground terminals), to cancel this offset. The DC offset DAC, along with a resistor at the input will provide a voltage −voff, and will cancel the original offset For high dynamic range readout application, DC offset cancelation must be performed. In the event the circuit solutions consume very low power (such as nanoampere levels), implementation of DC offset compensation DAC become prohibitive in terms of power, area, and current accuracy. 
       FIG. 3  illustrates a circuit  300  for reading low amplitude signals according to an embodiment of the invention. The embodiment of circuit  300  shown in  FIG. 3  comprises matching network  302 , mixers  304 ,  306 , and baseband filters  310 ,  312 . In this embodiment, matching network  302  includes capacitor  316  and inductor  320 , and the circuit  300  further comprises mixer  322 , a stage one amplifier  324 , a first cascade  326  of amplifiers, and a second cascade  330  of amplifiers. 
     A local oscillator signal LO1 is used to bias mixer  322 . As represented at  332 , this local oscillator signal is divided into a plurality of signals LO2I, LO2Q, and signal LO2I is used to bias mixer and signal LO@Q is used to bias mixer  312 . 
     In embodiments of the invention, separate biases are used for the front-end  340  and the back-end  342  of circuit  300 . In embodiments of the invention, the mixer  322  can use a different bias compared to that of the baseband filters  310 ,  312 . The DC blocking capacitors that are part of the filters  310 ,  312  provide this independence. In this specific design illustration, the mixer transistor (NMOS type in the Fig., may also be PMOS type in actual implementation) uses a 0V DC bias through the matching network  302 . 0V implies a connection to ground and no additional bias network is needed. The baseband filters  310 ,  312  can use a voltage at half of the supply, V DD /2 to maximize signal swing at the baseband output. In the prior art, a direct connection using current mode interface, leads to using complementary choice of transistors. Mixer using NMOS transistors are directly coupled to the OPAMPs using PMOS transistors at the input, or PMOS transistors are directly coupled to the OPAMPs using NMOS transistors at the input. In embodiments of the invention, this is not necessary. The interface is voltage mode (the baseband filter provides a moderate impedance), the mixer can be independently biased compared to the OPAMP, and each can be maximized for its specific dynamic ranges. 
     In the implementation of circuit  300 , matching network  302  receives an input signal and matches the impedance of that signal to the impedance of the rest of circuit  300 . From matching network  302 , the signal is passed to mixer  322 , which downconverts the input signal; and from mixer  322 , the signal is amplified by stage one amplifier  324  and then passed to mixers  304 ,  306 . 
     In the depicted embodiment, circuit  300  includes an in-phase channel  344  and a quadrature channel  346  for respectively processing real and imaginary signal components. For the in-phase channel  344 , an in-phase mixer  304  downconverts an in-phase baseband signal; and, similarly, for the quadrature channel  346 , a quadrature mixer  306  downconverts a quadrature baseband signal. 
     As mentioned above, local oscillator signal LO1 is divided into a plurality of signals LO2I and LO2Q that are used to bias mixer  304  and mixer  306  respectively. 
     In-phase mixer  304  applies a pair of output signals to in-phase baseband filter  310 , and quadrature mixer  306  applies a pair of output signals to quadrature baseband filter  312 . Filter  310  accepts the downconverted signals from mixer  304  and filters the signals to produce filtered signals, which are applied to a cascade  326  of baseband amplifiers. Similarly, filter  312  accepts the downconverted signals from mixer  306  and filters the signals to produce filtered signals, and these filtered signals are applied to a cascade  330  of baseband amplifiers. 
     Each of the baseband filters  310 ,  312  may act as a low-pass, band-pass, or high-pass filter. Each of the baseband filters can be implemented by a variety of different types of filters, including surface acoustic wave (SAW) filters, bulk acoustic wave (BAW) filters, mechanical filters, crystal filters, ceramic filters, lumped-element filters, and so forth. 
     The outputs of the amplifier cascades  326 ,  330  can be used or processed in any suitable way. For instance, the outputs may be applied to analog-to-digital converter which converts the output signals to digital signals. 
       FIG. 4  shows in more detail a baseband filter  400  that may be used as filter  310  or filter  312  of  FIG. 3 . Generally, filter  400  comprises OPAMP  402 , a pair of input resistors  404 ,  406 , a pair of input capacitors  410 ,  412 , parallel resistors  414 ,  416  and parallel capacitors  420 ,  422 . Resistor  404  and capacitor  410  are located in input line  424  and in series with a first input of amplifier  402 , and resistor  406  and capacitor  412  are located in input line  426  and in series with a second input of the amplifier. Capacitor  420  is positioned in parallel with amplifier  402  and is connected to input line  424  at node  430 , between resistor  404  and capacitor  410 , and to output line  432  at node  434 . Resistor  414  is located in parallel with amplifier  402  and is connected to input line  424  at node  436 , between capacitor  410  and amplifier  402 , and to output line  432  via node  440 . Capacitor  422  is also positioned in parallel with amplifier  402  and is connected to input line  426  at node  442 , between resistor  406  and capacitor  412 , and to output line  442  at node  444 . Resistor  416  is located in parallel with amplifier  402  and is connected to node  446 , between capacitor  412  and amplifier  402 , and to output line  442  via node  450 . 
     In embodiments of the invention, separate biases are used for the front-end and the back-end of the circuit  300 . Also, in embodiments of the invention, matching network  302  comprises a capacitive impedance transformation, or an autotransformer based transformation. In embodiments of the invention, baseband amplification stages can be capacitively coupled to prevent DC buildup. 
       FIG. 5  shows in more detail a circuit  500  for reading low amplitude signals according to an embodiment of the invention. Generally, the embodiment of circuit  500  shown in  FIG. 5  comprises matching network  502 , wideband multiplier  504 , voltage mode mixers  506 , and bandpass filter/amplifiers  510 . In this embodiment, circuit  500  includes two voltage mode mixers  512  and  514  and two filter/amplifiers  516  and  520 . In this embodiment of circuit  500 , matching network  502  includes capacitors C M1    522  and C M2    542  and an inductor  526  having L 1  and L 2  portions. Also, wideband multiplier  504  includes transistor switches  530 ,  532 , voltage mode mixer  512  includes transistor switches  534 ,  536 , and voltage mode mixer  514  includes transistor switches  540 ,  542 . In this embodiment of circuit  500 , bandpass filter/amplifier  516  includes resistors R 1   544 ,  546  and R 2   550 ,  552 , capacitors C 1   554 ,  556  and C 2   560 ,  562  and amplifier  564 ; and bandpass filter/amplifier  520  includes resistors R 1   566 ,  570  and R 2   572 ,  574 , capacitors C 1   576 ,  580  and C 2   582 ,  584 , and amplifier  586 . 
     Local oscillator signals LO 1  are used to dynamically switch transistors  530 ,  532 , and local oscillator signals LO 2  are used to dynamically switch transistors  534 ,  536 ,  540 ,  542  of the voltage mode mixers  512 ,  514 . 
     In the implementation of circuit  500 , matching network  502  receives, at  590 , an input signal from an external device (not shown) and matches the impedance of that signal to the impedance of the rest of circuit  500 . From matching network  502 , the signal is passed to wideband multiplier  504  which downconverts the applied signal and splits the applied signals into two components that are passed to voltage mode mixer  512  and voltage mode mixer  514  respectively. 
     In the example depicted in  FIG. 5 , circuit  500  includes an in-phase channel  592  for processing real signal components, and a quadrature channel  594  for processing imaginary signal components. For the in-phase channel, in-phase mixer  512  downconverts an in-phase signal from mixer  504 ; and likewise, for the quadrature channel, quadrature mixer  514  downconverts a quadrature baseband signal. 
     Local oscillator signals LO 1  are used to dynamically switch transistors  530 ,  532  of wideband multiplier  504 , and local oscillator signals LO 2  are used to dynamically switch transistors  534 ,  536 ,  540 ,  542  of voltage mode mixers  512 ,  514 . 
     In phase mixer  512  applies a pair of output signals to in-phase baseband filter  516 , and quadrature mixer  514  applies a pair of output signals to quadrature baseband filter  520 . Filter  516  accepts the downconverted signals from mixer  512  and filters the signals to produce filtered signals. Similarly, filter  520  accepts the downconverted signals from mixer  514  and filters the signals to produce filtered signals. 
     More specifically, in filter  516 , resistor  544  and capacitor  554  are located in input line  516   a  and in series with a first input of amplifier  564 , and resistor  546  and capacitor  556  are located in input line  516   b  and in series with a second input of the amplifier  564 . Capacitor  560  is positioned in parallel with amplifier  564  and is connected to input line  516   a  at node  516   c , between resistor  544  and capacitor  554 , and to output line  516   d  at node  516   e . Resistor  550  is located in parallel with amplifier  564  and is connected to input line  516   a  at node  516   f , between capacitor  554  and amplifier  564 , and to output line  516   d  via node  516   g . Capacitor  562  is also positioned in parallel with amplifier  564  and is connected to input line  516   b  at node  516   h , between resistor  546  and capacitor  556 , and to output line  516   i  at node  516   j . Resistor  552  is located in parallel with amplifier  564  and is connected to node  516   k , between capacitor  556  and amplifier  564 , and to output line  516   i  via node  516   l.    
     In filter  520 , resistor  566  and capacitor  576  are located in input line  520   a  and in series with a first input of amplifier  586 , and resistor  570  and capacitor  580  are located in input line  520   b  and in series with a second input of the amplifier  586 . Capacitor  582  is positioned in parallel with amplifier  586  and is connected to input line  520   a  at node  520   c , between resistor  566  and capacitor  576 , and to output line  520   d  at node  520   e . Resistor  574  is located in parallel with amplifier  586  and is connected to input line  520   a  at node  520   f , between capacitor  576  and amplifier  586 , and to output line  520   d  via node  520   g . Capacitor  584  is also positioned in parallel with amplifier  586  and is connected to input line  520   b  at node  520   h , between resistor  570  and capacitor  580 , and to output line  520   i  at node  520   j . Resistor  572  is located in parallel with amplifier  586  and is connected to node  520   k , between capacitor  580  and amplifier  586 , and to output line  520   i  at node  520   l.    
     In embodiments of the invention, the matching network  502  provides voltages or current gain and improves the sensitivity of the circuit. The matching network provides capacitive coupling to the external device whose output signal is applied to the matching network. In embodiments, that device may be a device under test (DUT). Hence, the DC level of the memory/sensor elements is completely suppressed using the front-end matching network construction itself. 
     In embodiments of the invention, the tapped inductor  526  of the matching network  502  provides DC bias and impedance transformation. In embodiments, the matching network provides a single pin interface to an external device. This may be important for next generation computing. 
     In embodiments of the invention, components of the matching network  502  can be realized on chip, or fully integrated with the rest of circuit  500 , and components of the matching network can be programmable. In the embodiment of matching network shown in  FIG. 5 , C mi  blocks any DC perturbation at the external device whose output signal is applied to the matching network. 
     In embodiments of the invention, wideband multiplier  504  converts single-ended inputs into differential outputs, and the multiplier can use DC voltage if the received signal is at a low frequency. In embodiments, multiplier  504  can have both I and Q paths, and can use low distortion transistor switches. In embodiments, wideband multiplier  504  can work with lower loading to the clock generator for the local oscillator, and can work with input sinusoidal waveshapes. In embodiments of the invention, multiplier  504  does not need a DC bias current and does not produce any flicker or signal noise, and thermal noise is limited by the dynamic on resistance (r ON ) of the transistors  530 ,  532 . 
     In embodiments, the voltage mode mixer  506  provides voltage gain, and the bias of the filter/amplifier  510  is in the mid-rail range. In embodiments of the invention, the voltage mode mixer  506  provides an optimum or maximum signal swing at the output, and no DC offset compensation is necessary. In embodiments, RF gain steps are implemented by segmenting multiple transistors (not shown) in the voltage mode mixer  506 . In embodiments, RF gain steps are possible by tapping at different points of the transformer  526 ; and in embodiments, RF gain steps are possible by adjusting the bulk voltage of M 1  and M 2 . In embodiments of the invention, RF gain steps are possible by adjusting the duty cycle of the LO waveforms coupled to M 1  and M 2 . 
     In embodiments of the invention, the bandpass filter/amplifier  510  provides one active stage per biquad function. In embodiments, C 1  and C 2  block DC from the previous stage, and this eliminates the expensive DC offset cancellation network (saves both power and area). In embodiments, the wideband multiplier  506  and the baseband filter  510  can be biased independently. Also, in embodiments, the input intercept point 2 (IIP2) terms can be easily filtered out. As IIP2 is primarily a function of transistor mismatch and the quadrature accuracy of the LO signals, a smaller size transistor may be used to reduce area and power consumption. 
     In embodiments of the invention, the DC offset at the output of the bandpass filter  512  is only from one stage of the circuit  500 . In embodiments, subthreshold biasing of the transistors in the bandpass filter is possible, and smaller device sizes in the baseband may be used, compared to the device sizes when they are biased in strong inversion. In embodiments of the invention, there is no DC current through the R 2  resistors, and the resistors R 2  and capacitors C 2  of the bandpass filter can be interchanged without changing the transfer function of the bandpass filter. Also, in embodiments of the invention, an operational transconductance amplifier (OTA) can be implemented in the bandpass filter using a single transistor with common mode feedback (CMFB). 
     In embodiments of the invention, the wideband multiplier  504  can use different LO frequencies, and multiple phases can be used for automatic gain control (AGC) function (using precise duty cycle). In embodiments of the invention, a plurality of wideband multipliers can be used in parallel, and the frequencies of the signals LO 2  applied to multipliers  512 ,  514  can be substantially lower than the frequency of the signal LO 1  applied to multiplier. Also, in embodiments of the invention, double balanced multipliers can be used as mixers, and these mixers can have an array of transistor switches with N phases. 
     Embodiments of the invention use a mixer biased for minimum ON resistance, and a baseband filter biased for maximum gm/I. 
     The ON resistance of a transistor is given by r ON =1/[β*(V GS −V T )], where β is the device transconductance, and given by β=μ*COX, where μ is the majority carrier mobility in the device, COX is the oxide capacitance. So, in this specific embodiment of the invention, the sources of the transistors  530 ,  532  are biased to 0V through the impedance conversion network  502  (also known as matching network). When the transistor is turned ON, by providing V G =V DD , then V GS =V DD −0=V DD , the highest voltage that can be provided to the transistor. An NMOS transistor provides high mobility, and by providing the bias directly from the matching network  502 , leads to maximizing V GS , and minimizing r ON . In the prior art (when an NMOS mixer is biased using the common mode provided by the baseband filter), this voltage cannot be 0V (due to the structures used in the prior art, this voltage cannot be 0V), and the r ON  cannot be minimized. 
     MOS transistors are typically used as transconductors. For a given input voltage, they provide an output current. The ratio of the output current to the input voltage is given by the transconductance, g m , which is a function of the quiescent current through the device. When the transistor is biased in saturation region, g m =sqrt(2*μn*C OX *I*W/L), and when the device is biased in subthreshold, g m  is given by g m =I/V t , where I is the quiescent current (bias current), and Vt is the thermal voltage, given by V t =kT/q (T is absolute temperature, and q is the charge of an electron). 
     In embodiments of the invention, a low frequency analog filter  510  (gain and filtering section) is biased by itself (self biased). 
     In embodiments of the invention, due to the construction, the resistance R 2 , which is coupled between the output and input of the analog filter does not consume any DC current, as no DC current flows to the gate of MOS transistors. Thereby, the output DC voltage equals the input DC voltage, so the output of the OPAMP used in the filter, biases the input. In this way, the baseband filter is self biased. In embodiments of the invention, no DC offset compensation network is used. This saves significant area, and calibration overhead. In an aspect, an embodiment of the invention does not require any special biasing techniques in the analog/baseband section  510 , and the DC blocking capacitors are part of the filter&#39;s transfer function itself. 
       FIGS. 6A and 6B  illustrate the time domain waveforms as the signal passes left to right through the circuit  500  of  FIG. 5 . The first stage, receiving the signal is the matching network  502 , which does not perform any frequency conversion. The matching network provides a scaling of the input signal amplitude. The mixer  504  provides the downconversion. If the input of the receiver is x(t)=A rf *cos(ω rf *t+φ), {wherein Arf is the input amplitude, and ω rf  is the angular frequency of the RF signal}, then the input to the mixer is x2(t)=k1*Arf*cos(ω rf *t+φ), where k is the conversion gain (loss) of the matching network. The mixer  504  works as the multiplier with respect to its local clock (LO, at angular frequency of ω LO ), and the output becomes x3(t)=k1*k2*Arf*cos{(ω rf −ω lo )t+φ}, where k2 is the gain, and ω lF =ω rf −ω LO . 
       FIG. 6A  shows the RF input waveform, and  FIG. 6B  shows the baseband waveform. The time period of the carrier inside the envelope of the first waveform is given by 1/F LO , where F LO =ω LO /(2*Π). Similarly, the time period of the IF waveform is given by 1/F BB , where F BB =ω BB /(2*Π). 
       FIG. 7  shows details of the matching network  702  construction along with the capacitor  704  and tapped inductor  706 , in an embodiment of the invention. In an embodiment, the inductor  706  is fabricated using a back-end-of-line metal stack in a standard semiconductor technology. In this case, CMOS technology and copper metals are used. As an example, there are five layers of metal, and a magnetically coupled transformer should be used for implementing the inductive element. As it is magnetically coupled, the two coils (primary and secondary), can be implemented using a sandwich of two metal layers and three metal layers respectively. For example, the primary coil is M1 and M2, the secondary coil is M3, 4, 5 (as an example). In another example, the upper metal layers and M4 can work as the primary coil, while M5 can work as the secondary coil with no DC connection between them. Hence, for a magnetically coupled transformer, neither the primary terminal, nor the secondary terminal can use the entire stack of metals (e.g. M1/2/3/4/5). In embodiments of the invention, using all metal layers is the best choice to achieve highest quality factor and low loss. 
     The auto-transformer provides advantages. In an auto-transformer, a mid point of the entire structure is connected to, while the entire coil uses all the metallization stack that could be possible to use. In contrast to the magnetically coupled transformer, this type of electrically coupled transformer can maximize the quality factor, and consume smaller lateral area, thereby leading to low power and low area for the front-end of the circuit. Electrically coupled transformers also provide a high coupling factor compared to the magnetically coupled transformers. The design of  FIG. 7  demonstrates one way where the connection from the auto transformer to the circuit is minimized using a very small trace to minimize degradation of the quality factor. This is performed by tapping to the point that is closest to the on-chip circuit. 
     
       
         
           
             
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                   Center 
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                   frequency 
                 
               
               
                 
                   
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     Provides the transfer function of the baseband filter shown in  FIG. 5 . S=jw, where w is the angular frequency, =2*Π*f, where f is frequency in Hz. So, a plot of Av vs. f provides the frequency response of the baseband filter. Av,max is the maximum voltage gain, Q is the quality factor of the filter as defined in Q=Fc/F3 dB, where Fc is the center frequency of the bandpass stage, and F3 dB is the 3 dB bandwidth, given by F2−F1, where F2 and F1 are frequencies where the amplitude Av,3 dB=Av,max-3 dB. Fc is the center frequency. It should be noted that the center frequency (Fc) and the quality factor (Q) are interdependent on each other. 
       FIGS. 8A-8F  sow simulation results of an embodiment of the invention. In this simulation, the RF frequency is equal to 6.5 GHz, and the IF frequency is equal to 6.5 MHz. 
       FIG. 8A : Simulation result from the input of the matching network  502  to the output of the baseband filter  510 . The transfer function is of the entire front-end including all the blocks. This Fig. shows a bandpass characteristics with maximum gain=24 dB. 
       FIG. 8B : Simulation results of mixer  506  and baseband filter  510  together. This Fig is basically  FIG. 8A  minus the matching network voltage gain. 
       FIG. 8C : voltage gain of the mixer  506 . The input to the mixer is an RF signal and the output is the baseband signal, so this Fig. shows the ratio of the signal amplitude at the baseband frequency output vs. the amplitude of the input signal at RF frequency. 
       FIG. 8D : Scattering parameter (S-parameter) plot of the front-end looking at the input of the front-end (into the matching network). Typically a large negative number indicates that the input impedance is substantially close to the reference impedance (typically 50 ohms). In modern integrated receivers, it is acceptable to get closer to a large number but typically −10 dB is used as a compromise between input sensitivity (noise figure) and return loss. 
       FIG. 8E : Shows output noise (noise at the output of the baseband filter, the final output of the receiver). 
       FIG. 8F : shows the input noise with the noise floor shown. 
     The description of the invention has been presented for purposes of illustration and description, and is not intended to be exhaustive or to limit the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope of the invention. The embodiments were chosen and described in order to explain the principles and applications of the invention, and to enable others of ordinary skill in the art to understand the invention. The invention may be implemented in various embodiments with various modifications as are suited to a particular contemplated use.