Patent Publication Number: US-6211548-B1

Title: Metal-gate non-volatile memory cell

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This is a continuation-in-part of U.S. patent application Ser. No. 08/735,910, filed Oct. 25, 1996 now U.S. Pat. No. 5,768,186. To the extent not repeated herein, the contents of Ser. No. 08/735,910 is incorporated by reference herein. 
    
    
     FIELD OF THE INVENTION 
     The present invention relates in general to non-volatile semiconductor memory technology and more particularly to a structure of and a method for producing a non-volatile memory cell having a metal layer used as the control gate. 
     DESCRIPTION OF THE RELATED ART 
     Conventional non-volatile semiconductor memory cell technologies, which use polysilicon floating gate as the storage element, typically comprise two or three layers of polysilicon. FIG. 1 shows the cross section of a conventional double-poly ETOX non-volatile memory cell. The first polysilicon layer  10 , commonly referred to as the floating gate, is used as the storage element. As shown in FIG. 1, the floating gate  10  is encompassed on top by an ONO (Oxide-Nitrate-Oxide) coupling dielectric layer  11  and on bottom by a tunnel oxide dielectric layer  12 , typically around 100 Å thick. 
     The second polysilicon layer  13  is used as the control gate of the memory cell. When a number of memory cells are placed next to one another along one row in a memory array, the second polysilicon layer  13  forms a continuous line, commonly referred to as a wordline. As shown in FIG. 1, n+ source region  14  and n+ drain region  15  are formed in a P-type substrate  18  through an Arsenic implant step. 
     Metal  1  layer  16  contacts the source region  14  and the drain region  15 , and is usually isolated from the control gate  13  by a thick BPSG insulating layer  17 . Importantly, source region  14  and drain region  15  are self-aligned to the edge of the double polysilicon stack. This feature enables scaling of the ETOX cell with minimal complexity. This self-aligned feature is achieved by carrying out the source/drain implant after the formation of the stack of control gate  13  and floating gate  10 . 
     With the advent of sub-micron technology and the rapidly increasing memory sizes, and the development of systems-on-chip, a number of limitations have arisen, to which no viable solutions have yet been offered. 
     One of these limitations is the long wordline RC time delays associated with large memory arrays. As mentioned earlier, in non-volatile memory arrays the second layer polysilicon forms the wordline. The high resistance and capacitance associated with second layer polysilicon results in what is known as the wordline RC time delay. With memory devices rapidly increasing in size, the memory arrays have become quite large. This, coupled with the continued scaling of semiconductor memory technology, has resulted in memory arrays with very long and thin polysilicon wordlines, which in turn have resulted in long RC time delays. The RC time delay, which is in the critical speed path of most memory devices, has become a limiting factor in achieving satisfactory memory device access times. 
     A number of approaches have been used to minimize the wordline RC time delay. One scheme breaks wordlines in half and drives the first half by a row decoder and the second half by a repeater. Each wordline requires one repeater and each repeater consists of two serially connected inverters. Given that two serially connected inverters need to be laid-out within the small pitch of a wordline, even the most efficient layout leads to repeaters excess die area. Therefore, repeaters, though effective in reducing the wordline RC delay, consume a large portion of the die area. 
     A second approach uses of tungsten silicide. Tungsten silicide reduces the resistance of the wordline RC by a factor of 10 as compared to polysilicon. However, with the rapid increase in memory sizes over the past decade, silicide is no longer an effective means of reducing the RC time delay. 
     A third and more effective approach in minimizing the wordline RC delay has been strapping the polysilicon wordline with a metal layer. Due to the very low resistance of metal, strapping the polysilicon effectively shorts the polysilicon wordline, thereby significantly reducing the resistance of the wordline RC. However, in order to strap the poly wordline with metal, contact holes need to be made between the metal and the polysilicon. Since the wordline pitch is usually the tightest pitch, such contact holes increase the wordline pitch and thereby result in significant loss of silicon area. In addition, the metal strap extending across the thin polysilicon wordline overlays a very rough topography caused by the double polysilicon stack. This has been the source of significant yield loss in mass producing non-volatile memories. Therefore, here again the speed improvements are at the cost of a larger die size and yield loss. 
     None of the above approaches offer an effective solution in minimizing the wordline RC time delay without any significant drawbacks. 
     A second impairing limitation involves some of the complexities arising in integrating different technologies. A general trend in the semiconductor industry has been integrating more functions into one chip, thereby replacing a number of discrete devices with one device. To enable such integration, combining different technologies such as SRAM, non-volatile and standard CMOS logic into one single process has become necessary. However, combining these technologies into a single process have proven difficult and complex. Standard CMOS logic technology and non-volatile memory technology have in fact been combined at the expense of a complex process. 
     One example of complexities arising in combining technologies is the classic case of combining SRAM technology using four transistor memory cells and non-volatile memory technology into a single process, a much favored trend in designing microcontrollers. The four transistor SRAM cell requires the use of a highly resistive polysilicon as the load element. In contrast, the non-volatile memory technology requires low resistive polysilicon to minimize such speed impediments as poly interconnect delay, gate resistance, the wordline resistance. Therefore, two conflicting characteristics are required of the polysilicon. Some memory manufacturers have adopted a singly poly non-volatile cell approach to overcome this limitation. However, the size of a single poly cell is typically three to four times larger than the conventional double poly cell. With no viable solution being offered, the development of cost effective products such as flash/SRAM IC devices has been hindered. 
     Theoretically, using metal as the control gate of the memory cell instead of polysilicon would overcome the above two mentioned limitations. The RC time delay limitation is overcome without any area penalty since the wordlines would be formed directly from metal, and as such no contact holes for strapping the wordlines would be needed. With respect to the limitation arising in integration of SRAM and nonvolatile memory technologies, a highly resistive second layer poly can be used exclusively as the load element for the four transistor SRAM cell, while metal and first layer poly can be used as the control gate and the floating gate of the memory cell respectively, thereby, eliminating the above mentioned conflicting characteristics required of the second layer poly. 
     In the early days of the IC industry, when 5 μm lithography metal-gate technology was in use, metal gate MOS transistors were common. However, the practice of using metal as the gate electrode or control gate of MOS devices has long been abandoned. The primary reason for abandonment of this technology was the lack of scalability. Unlike the conventional poly gate technology which lends itself well to scaling, the metal gate technology did not. 
     As mentioned earlier, the scalability of the poly gate technology stems from the self-aligned feature of its fabrication process. More specifically, the source/drain regions are self-aligned to the poly control gate because the source/drain ion implant step is carried out after the deposition and patterning of the poly gate whereby, the edges of the poly control gate are used to define the portions of the boundaries of the source/drain regions which delineate the transistor channel region. Therefore, to achieve the self-aligned feature, the control gate needs to be formed prior to source/drain region formation. In the metal gate MOS technology however, the source/drain ion implant step could not be performed after the deposition and patterning of the metal control gate, and as such the source/drain regions were not self-aligned. Generally, in the MOS technology a thermal annealing step, at temperatures above 900° C., must be carried out after the source/drain implant step in order to activate the arsenic element and form defect free source/drain regions. Due to the high temperature of the anneal cycle, only refractory materials with high melting point (i.e. materials withstanding temperatures greater than 900° C.) , such as tungsten polycide, can be used as the control gate. As a result, aluminum, the commonly used gate metal, due to its low melting point, could only be used if deposited after the thermal annealing step, leading to non-self-aligned source/drain regions. 
     As a result, the non-self-aligned and non-scaleable metal gate MOS technology was abandoned. 
     SUMMARY 
     In accordance with the present invention, a metalgate (MG) non-volatile memory cell as well as a method for producing such cell are disclosed. 
     The MG non-volatile memory cell comprises: 
     a source region and a drain region in a silicon substrate, the source and drain regions being separated by a channel region; 
     a floating gate which is over but insulated from the channel region wherein at least one of the edges of the floating gate is aligned with and used to define the corresponding edge of one of the source and drain regions; and 
     a control gate made from a metal which is over but insulated from the floating gate. 
     The following outlines one set of process steps for producing a MG non-volatile memory cell: 
     (A) a first layer of insulating material is formed on a silicon substrate; 
     (B) a floating gate is formed on the layer of insulating material; 
     (C) source and drain regions are formed in the silicon substrate such that at least one of the edges of the floating gate is aligned with the corresponding edge of one of the source and drain regions; 
     (D) a second layer of insulating material is formed over the floating gate; and 
     (E) a control gate made from a metal is formed over the second layer of insulating material. 
     One feature of the present invention is that the wordline RC delay is significantly reduced without any die area penalty since the wordlines are from metal. 
     Another feature of the present invention is that the source/drain regions of the memory cell are self-aligned to the edges of the floating gate. 
     The above features are achieved using a simple process in which CMOS transistors and the metal-gate non-volatile memory cells are easily integrated. 
     These and other features and advantages of the present invention will become more apparent from the following description and the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 shows the cross section of a conventional double-poly ETOX non-volatile memory cell. 
     FIG. 2A shows a contact-less array in accordance with the present invention. 
     FIG. 2B shows the cross section across line AA in FIG.  2 A. 
     FIGS. 3A to  3 M show the cross sections of a memory device and a MOS transistor at the different stages of the process sequence in accordance with one embodiment of the present invention. 
     FIGS. 4A to  4 F show six different memory cell approaches and the corresponding metal-gate implementation of each. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     In accordance with the present invention, a metal-gate non-volatile memory cell is disclosed. One cell structure and the process for fabricating a metal-gate memory cell of this invention, are described in more detail hereinafter. This description is illustrative only and not limiting. 
     (a) Description of the Cell Structure of the Metal-gate Non-volatile Memory Cell in a Contact-less Array: 
     FIGS. 2A to  2 B show a specific implementation of the present invention. FIG. 2A shows a contact-less array in accordance with the present invention. FIG. 2B shows the cross section at line AA in FIG.  2 A. 
     As shown in FIG. 2A, floating gates  24  are arranged in columns. The floating gates  24  are separated along the vertical direction by field oxide regions  31  and along the horizontal direction by columns of continuous buried bitline  25 . The portions of the columns of buried bitlines  25  that are adjacent to each floating gate  24  form the source/drain regions for each memory cell (this can also be seen in FIG.  2 B). 
     In FIG. 2A, continuous metal lines  23  are shown to run over the floating gates  24  across the array in the horizontal direction. The portions of the metal lines  23  running over the floating gates  24  form the control gate for each memory cell. The metal lines  23  are also referred to as the wordlines. Note that since the wordlines are from metal, no wordline strapping, as in the conventional non-volatile memory arrays with polysilicon wordlines, is required. 
     Also shown in FIG. 2B are LDD (Lightly-Doped Diffusion) oxide spacers  34  at the edges of the control gates  24 . The spacers provide a smoother array topography, resulting in better step coverage for the metal wordlines. 
     The metal control gate  23  and the floating gate  24  are separated by a coupling dielectric  21 . In one embodiment the coupling dielectric  21  comprises a composite layer of Oxide-Nitride-Oxide-Polysilicon (ONOP). The ONOP composite layer comprises, in the order from bottom layer to top layer: a layer of Oxide having a thickness in the range of 80 Å to 250 Å (the preferred thickness being 100 Å), 100 Å of Nitride (N), 50 Å of Oxide, and a layer of Polysilicon (P). 
     In an alternate embodiment, the coupling dielectric  21  comprises a composite layer of Oxide-Polysilicon (OP). The oxide layer has a thickness in the range of 80 Å to 250 Å (with the preferred thickness being 100 Å) and forms the bottom layer. 
     The oxide layers in both the ONOP and OP composite layers may be High Temperature Oxide (HTO) or thermally grown. The polysilicon layer in the ONOP and OP composite layers serves primarily as a buffer layer protecting the underlying layers from subsequent processing steps. The optimum thickness of the polysilicon layer depends on whether a doped or an undoped polysilicon is desired. If undoped, the preferred thickness range is 100 Å to 600 Å. If doped, the preferred thickness range is 400 Å to 1000 Å. 
     Impurities such as arsenic or phosphorous may be used to dope the polysilicon layer. Such doped poly may advantageously be used in the periphery as interconnect, or as the load resistor in a 4-transistor SRAM cell, or for other purposes. In the case of 4-transistor SRAM cell, an optimum thickness is selected for the buffer poly to obtain the desired load resistor characteristics. 
     Also shown in FIG. 2B is the tunnel oxide dielectric layer  22  insulating the floating gates from the underlying silicon substrate. 
     One key deviation from the conventional ETOX cell approach is that in fabricating the metal-gate memory cell, the anneal cycle, which is carried out to remove impurities from the source/drain regions, is carried out prior to rather than after the formation of the control gate, as will be described in more detail below. This change in the sequence of steps eliminates the concern about the low melting point of the aluminum gate during the high temperature anneal cycle. 
     A second key deviation from the conventional ETOX cell approach is that unlike the ETOX cell approach wherein the source/drain regions are self-aligned to the stack of control gate and floating gate, in the present invention the source/drain regions are self-aligned to the edge of the floating gate. 
     The above two deviations from the conventional ETOX cell approach has enabled the direct use of metal as the control gate of the memory cell while the scalability benefits resulting from a self-aligned source/drain process is maintained. 
     (b) Description of the Process Steps Involved in Fabrication of a Metal-gate Non-volatile Memory Cell: 
     FIGS. 3A to  3 M show one embodiment of the present invention. These Figures depict the cross section of a memory device and a MOS periphery transistor at the different stages of the fabrication process. The cross section of a MOS transistor is incorporated in each Figure to illustrate the ease with which the metal-gate memory cell process can be integrated into a standard MOS process. The dimensions shown in these Figures are not to scale and are for illustration purposes only. 
     Prior to the process step of FIG. 3A, islands of field oxide, each having a thickness of approximately 5000, shown as regions  31  in FIG. 2A, are grown over the silicon substrate. The field oxide  31  of FIG. 2A is not shown in FIGS. 3A to  3 M because these figures show the cross section across line AA in FIG. 2A at different stages of the fabrication process. 
     FIG. 3A shows a P-type substrate  10  over which a thin layer of tunnel oxide  11 , having a thickness in the range of 65 Å to 100 Å, is grown. Subsequently, a first layer of polysilicon or polycide  12 , having a thickness in the range of 1500 Å to 3000 Å, is deposited over the tunnel oxide layer  11 . The polysilicon layer  12  is then doped with Phosphor to make it n-type. 
     All the cross sections in the subsequent Figures show a periphery transistor in the periphery region  40  along side memory cells in the array region  50 . In FIG. 3B, the floating gates  13  are defined through a photoresist masking step and a subsequent plasma etching step. The polysilicon portion  16  in FIG. 3B remains undefined. As shown in FIG. 3B, the photoresist  30 , used in defining the polysilicon, is not removed from over the floating gates  13  and the polysilicon  16 . 
     Next, as shown in FIG. 3C, an Arsenic implant step is carried out to form the source/drain regions  15  for the memory cells in the array region  50 . Note that through this process step, the source and drain regions  15  become self-aligned to the edges of the floating gates  13 . 
     With the floating gates  13  covered by photoresist  30  during the Arsenic implant step, the floating gates  13  are protected against any potential damage during the source/drain ion implantation. This helps improve the memory cell retention characteristics, a mechanism which leads to yield loss or loss of otherwise functional dice. 
     Next, as shown in FIG. 3D, the photoresist  30  is stripped and then a high temperature anneal cycle at approximately 900° C. is carried out in order to anneal out the defects of the source/drain regions  15 . Note that the annealing of the source/drain regions  15  is carried out prior to the deposition and formation of the memory cell control gate. 
     As shown in FIG. 3E, a photoresist masking step is carried out through which the gate electrode  26  of the periphery transistor in the periphery region  40  is defined while the entire array region  50  is covered and protected by photoresist  27 . 
     Subsequently, photoresist  27  is stripped from over both the gate electrode  26  and the memory cells. Through another photoresist masking step, the memory cells are covered by photoresist  28  while an implant step is carried out in the periphery region  40  to form Lightly-Doped Diffusion (LDD) n− regions  17 , as shown in FIG.  3 F. 
     As shown in FIG. 3G, the photoresist  28  is stripped from over the memory cells, and an oxide spacer, preferably HTO, is deposited and subsequently etched back to form the LDD oxide spacers  19  at the edges of the gate electrode  26  of the peripheral transistor as well as at the edges of the floating gates  13 . Oxide spacers  19  are commonly used in fabrication of peripheral LDD transistors, however, in the present invention oxide spacers are advantageously used in the array region  50  to provide a smoother array topography. A smoother array topography provides better step coverage for the metal wordlines to be deposited at a later process step. 
     Next, as shown in FIG. 3H, an Arsenic implant step is carried out in the periphery region  40  to form the source/drain regions  20  of the peripheral transistor. During the implant cycle, the array region  50  is covered by an array mask  29  in order to protect the floating gates  13  from receiving the implant. 
     As shown in FIG. 3I, a coupling dielectric  21  is grown over the memory cells as well as the periphery transistor. In one embodiment the coupling dielectric  21  comprises a composite layer of Oxide-Nitride-Oxide-Polysilicon (ONOP). The ONOP composite layer comprises, in the order from bottom layer to top layer: a layer of Oxide having a thickness in the range of 80 Å to 250 Å (the preferred thickness being 100 Å), 100 Å of Nitride (N), 50 Å of Oxide, and a layer of Polysilicon (P). 
     In an alternate embodiment, the coupling dielectric  21  comprises a composite layer of Oxide-Polysilicon (OP). The oxide layer has a thickness in the range of 80 Å to 250 Å (with the preferred thickness being 100 Å) and forms the bottom layer of the OP composite layer. 
     The oxide layers in both the ONOP and OP composite layers may be High Temperature Oxide (HTO) or thermally grown. The polysilicon layer in the ONOP and OP composite layers serves primarily as a buffer layer protecting the underlying layers from subsequent processing steps. The optimum thickness of the polysilicon layer depends on whether a doped or an undoped polysilicon is desired. If undoped, the preferred thickness range is 100 Å to 600 Å. If doped, the preferred thickness range is 400 Å to 1000 Å. 
     Impurities such as arsenic or phosphorous may be used to dope the polysilicon layer. Such doped poly may advantageously be used in the periphery as interconnect, or as the load resistor in a 4-transistor SRAM cell, or for other purposes. In the case of 4-transistor SRAM cell, an optimum thickness is selected for the buffer poly to obtain the desired load resistor characteristics. 
     In FIG. 3J, the composite layer of coupling dielectric  21  is removed from over the peripheral transistor through a conventional photoresist masking and etching step. In FIG. 3K, an insulation layer of BPSG  22  is deposited and a BPSG flow process is subsequently carried out such that approximately 6000 Å of BPSG is formed over the both the array region  50  and the periphery region  40 . 
     In FIG. 3L, contact holes  23  are formed using a contact mask. In forming the contact holes  23  in the periphery region  40 , the BPSG layer  22  is etched down to the silicon surface. This facilitates the later step of contacting the source/drain diffusion regions  20 . In the array region  50 , the whole memory array is opened as a big contact hole  23 , and the BPSG layer  22  is etched down to the coupling dielectric layer  21 , as shown in FIG.  3 L. Depending upon the oxide to poly selectivity of the dry plasma oxide etch, an appropriate thickness must be selected for the buffer polysilicon in the ONOP or OP composite layer to provide sufficient protection for the underlying layers from the BPSG contact etch. For example, for an oxide to poly selectivity of greater than 30, a minimum thickness of 400 Å of buffer poly should provide adequate protection. 
     After the contact hole formation, the metal  1  layer  24  is deposited over the memory cells and the periphery transistor. Using a photoresist masking step, the deposited metal  1  layer  24  is then defined in the array region  50  as the control gate of the memory cells, and in the periphery region  40  as the interconnect for the periphery transistors. As mentioned earlier, the oxide spacer  19 , adjacent to the floating gates  13 , provides for a smooth step coverage of the metal wordlines  24  in the array as shown in FIG.  3 M. 
     The portions of the buffer poly layer remaining exposed between adjacent metal wordlines (not shown in FIG. 3M) is then etched off through a plasma polysilicon etching step using the metal wordline pattern as a mask. This step is required in order to prevent leakage between metal wordlines through the buffer polysilicon. Also, using the metal wordline pattern as a mask in etching the buffer poly ensures that the remaining buffer poly is self-aligned to the metal wordline. 
     Next, conventional process steps (not shown) can be carried out to form subsequent layers of metal as needed. Finally, a conventional passivation layer (not shown) is deposited over the entire silicon die to protect the die from scratches or other damages. 
     FIGS. 4A to  4 F show other embodiments of the present invention. In the upper section of each of these figures, a previously known non-volatile memory cell structure along with its corresponding programming/erase/read logic table are shown. In the lower section of each of these figures, the corresponding metal-gate implementation of the non-volatile memory cell is shown. 
     FIG. 4A shows the ETOX non-volatile memory cell and its program/erase/read table (disclosed in Sameer Shafiq Haddad et al., U.S. Pat. No. 5,077,691), as well as the corresponding metal-gate implementation for a contact-less virtual ground array architecture. FIG. 4B shows the split-gate memory cell and its program/erase/read table, as well as the corresponding metal-gate implementation. FIG. 4C shows the double-poly source-side injection memory cell and its program/read/erase table, as well as the corresponding metal-gate implementation. FIG. 4D shows the triple-poly source-side injection memory cell and its program/read/erase table (disclosed in Wu et al, U.S. Pat. No. 4,794,465, and Iizuka, U.S. Pat. No. 4,462,090), as well as the corresponding metal-gate implementation for a contact-less virtual ground array architecture. FIG. 4E shows the triple-well DIvided Bitline NOR (DINOR) memory cell and its program/read/erase table (disclosed by Tsuji et al. in “New Erase Scheme for DINOR Flash Memory Enhancing Erase/Write Cycling Endurance Characteristics,” IEDM &#39;94, p. 3.4.1-3.4.4), as well as the corresponding metal-gate implementation for a contact-less virtual ground array architecture. FIG. 4F shows the self-aligned dual-bitline split gate flash EEPROM cell disclosed in Ma et al., U.S. Pat. No. 5,278,439, issued Jan. 11, 1994, incorporated herein by reference, as well as the corresponding metal-gate implementation. 
     As apparent from FIGS. 4A to  4 F, due to the simplicity of the metal-gate memory cell concept, it may be applied to any non-volatile memory cell technology, e.g., EPROM, Flash EPROM, EEPROM, Flash EEPROM, and NOVRAM. 
     The above description of the present invention is intended to be illustrative and not limiting. The invention is further intended to include all variations and modifications falling within the scope of the appended claims.