Patent Publication Number: US-7595625-B2

Title: Current mirror

Description:
PRIORITY CLAIM 
     The present application claims priority from European Patent Application No. 05291823.2 filed Sep. 1, 2005, the disclosure of which is hereby incorporated by reference. 
     BACKGROUND OF THE INVENTION 
     1. Technical Field of the Invention 
     The present invention relates generally to a current mirror. 
     More specifically, the invention relates to a current mirror of the type comprising at least a first and a second mirror transistors inserted between a first and a second voltage reference and connected to an input terminal and to an output terminal of the current mirror, respectively. A base current compensation block is inserted between said input terminal and common control terminals of the first and second mirror transistors and connected to a voltage reference. 
     2. Description of Related Art 
     As it is well known, current mirrors are widely used in all kinds of electronic circuits. Basically, a current mirror is a circuit designed to copy a current flowing through one active device by controlling a current in another active device, keeping an output current of an output terminal of the current mirror constant regardless of loading values applied to the output terminal itself. 
     A current mirror realized by using bipolar transistors is schematically shown in  FIG. 1 . 
     In particular, the current mirror  1  comprises a first or input leg comprising a current generator G 1  issuing a reference current Iref, a first mirror transistor Q 1  and a first emitter resistor R 1 , inserted, in series with each other, between a first and a second voltage reference, in particular a supply voltage reference Vcc and ground GND. 
     Furthermore, the current mirror  1  comprises a second or output leg comprising a second mirror transistor Q 2  and a second emitter resistor R 2 , inserted, in series with each other, between an output terminal OUT of the current mirror  1  and ground GND. 
     The first and second mirror transistors, Q 1  and Q 2 , are bipolar transistors and have their base terminals connected to each other. 
     To increase current mirror accuracy, a classic solution is to use emitter resistors and a base current compensation block, as shown in  FIG. 1  and globally indicated at  2 . 
     In particular, the base current compensation block  2  is connected to the common base terminals of the mirror transistors, Q 1  and Q 2 , and to the collector terminal of the first mirror transistor Q 1 . The collector terminal of the first mirror transistor Q 1  is also the input terminal IN of the current mirror  1 . 
     The base current compensation block  2  is used to compensate the base currents of the first and second mirror transistors, Q 1  and Q 2 . A well known realization of this block is described in Analysis and Design of Analog Integrated Circuits, Paul R. Gray, Robert G. Meyer, Third edition, page 276, and schematically shown in  FIG. 2 . 
     In particular, the base current compensation block  2  comprises a compensation transistor Q 3 , inserted between the supply voltage reference Vcc and the common control or base terminals of the mirror transistors, Q 1  and Q 2 , and having a base terminal connected to the collector terminal of the first bipolar mirror transistor Q 1 . The compensation transistor Q 3  is a bipolar transistor. 
     It can be verified that the compensation transistor Q 3  reduces the error of an output current of the output terminal OUT according to the following equation: 
                   Iout   =     Iref     1   +     2       β   F     ⁡     (       β   F     +   1     )                     (   1   )               
where Iout is the output current, Iref is the reference current and βF is the bipolar current gain of Q 1 , Q 2  and Q 3  (supposed to be equal at a first order approximation).
 
     Moreover, the first and second emitter resistors, R 1  and R 2 , increase the matching of the current mirror  1 , as explained in the above cited handbook, pages 317 to 320. 
     Also known is an alternative realization of the base current compensation block  2  using a MOS transistor M 3 , as shown in  FIG. 3 . 
     In this case, as the gate current of a MOS transistor is zero, the output current Iout is equal to the reference current Iref and the base currents of the first and second bipolar mirror transistors, Q 1  and Q 2 , are supplied by the MOS transistor M 3 . 
     While advantageous from many points of view, the known solution has shown several drawbacks, among which is the fact that an input voltage applied to the collector terminal of the first mirror transistor Q 1  should be higher than a threshold value, which turns out to be too high in many applications. In particular, such a threshold voltage is:
         2×Vbe+R 1 ×Iref, for the base current compensation block  2  realized by a bipolar transistor and shown in  FIG. 2 , or   Vgs+Vbe+R 1 ×Iref, for the base current compensation block  2  realized by a MOS transistor and shown in  FIG. 3 ,
 
where:
   Vbe is the base-emitter voltage of the first mirror transistor Q 1 ; and   Vgs is the gate source voltage of the MOS transistor M 3 .       

     As an example, if Vbe=0.8V, Vgs=1V and R 1 ×Iref=0.2V (which are common amounts for these values) the minimum input voltage is about 1.8V or 2V, increasing to 2V or 2.3V with temperature and process variations. 
     SUMMARY OF THE INVENTION 
     There is a need for providing a current mirror having structural and functional characteristics which allow it to obtain a good accuracy and a low input voltage, regardless of output voltage. 
     An embodiment of the present invention is directed to a base current compensation block able to reduce the voltage value at the collector terminal of the first mirror transistor of the current mirror. 
     A further embodiment of the present invention is a current mirror of the type comprising at least a first and a second mirror transistors inserted between a first and a second voltage reference and connected to an in put terminal and to an output terminal of the current mirror, respectively. The current mirror further comprises a base current compensation block inserted between the input terminal and common control terminals of the first and second mirror transistors and connected to a voltage reference. The base current compensation block at least comprises: a bias current generator of a bias current and a first compensation transistor inserted, in series to each other, between the voltage reference and the input terminal; and a second compensation transistor inserted between the voltage reference and the common control terminals of the mirror transistors and having a control terminal connected to a control terminal of the first compensation transistor. 
     In an embodiment, a base current compensation block for a current mirror circuit comprises a bias current generator of a bias current and a first compensation transistor inserted, in series with each other, between a voltage reference and an input terminal of the current mirror circuit, a second compensation transistor inserted between the voltage reference and a common control terminal node of a pair of transistors in the current mirror circuit and having a control terminal connected to a control terminal of the first compensation transistor, and a third compensation transistor inserted between the voltage reference and common control terminals of the first and second compensation transistors, and having a control terminal connected between the bias current generator and the first compensation transistor. 
     In accordance with another embodiment, a current mirror comprises a first and a second mirror transistors inserted between a first and a second voltage reference and connected to an input terminal and to an output terminal of the current mirror, respectively. A first bias current generator of a first bias current is connected in series with the first mirror transistor. The circuit further includes a second bias current generator of a second bias current and a first compensation transistor inserted, in series with the second bias current generator, between a voltage reference and the input terminal. A second compensation transistor is inserted between the voltage reference and the common control terminals of the first and second mirror transistors and has a control terminal connected to a control terminal of the first compensation transistor. 
     The characteristics and advantages of the current mirror according to embodiments of the invention will be apparent from the following description of embodiments thereof given by way of indicative and non limiting example with reference to the annexed drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       A more complete understanding of the method and apparatus of the present invention may be acquired by reference to the following Detailed Description when taken in conjunction with the accompanying Drawings wherein: 
         FIGS. 1-3  schematically show current mirrors realized according to the prior art; 
         FIG. 4  schematically shows a current mirror realized according to an embodiment of the present invention; 
         FIG. 5  schematically shows the current error patterns of the known current mirrors in comparison with the current error pattern of the current mirror according to an embodiment of the present invention; and 
         FIG. 6  schematically shows an alternative embodiment of the current mirror realized according to an embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE DRAWINGS 
     With reference to such figures, and in particular to  FIG. 4 , a current mirror realized according to an embodiment of the present invention is schematically shown and globally indicated at  10 . 
     To structurally and/or functionally equal elements with respect to the circuits described in the prior art section, same reference numbers will be applied. 
     As already described with reference to current mirrors realized according to the prior art, the current mirror  10  comprises a first or input leg in turn including a current generator G 1  issuing a reference current Iref, a first mirror transistor Q 1  and a first emitter resistor R 1 , inserted, in series with each other, between a first and a second voltage reference, in particular a supply voltage reference Vcc and ground GND. 
     Furthermore, the current mirror  10  comprises a second or output leg comprising a second mirror transistor Q 2  and a second emitter resistor R 2 , inserted, in series with each other, between an output terminal OUT of the current mirror  10  and ground GND. 
     The first and second mirror transistors, Q 1  and Q 2 , are bipolar transistors and have their control or base terminals connected to each other. 
     Also, the current mirror  10  comprises a base current compensation block  12  connected to the common base terminals of the mirror transistors, Q 1  and Q 2 , and to the collector terminal of the first mirror transistor Q 1 . The collector terminal of the first mirror transistor Q 1  is also the input terminal IN of the current mirror  10 . 
     Advantageously according to an embodiment of the invention, the base current compensation block  12  comprises a second current generator G 2  of a bias current Ipol and a first compensation transistor Q 4  inserted, in series with each other, between the supply voltage reference Vcc and the input terminal IN of the current mirror  10 . 
     The base current compensation block  12  also comprises a second compensation transistor Q 6  inserted between the supply voltage reference Vcc and the common base terminals of the mirror transistors, Q 1  and Q 2 , and having a base terminal connected to a base terminal of the first compensation transistor Q 4 . 
     Finally, the base current compensation block  12  of the current mirror  10  according to an embodiment of the present invention comprises a third compensation transistor Q 5  inserted between the supply voltage reference Vcc and the common base terminals of the first and second compensation transistors, Q 4  and Q 6 , and having a base terminal connected to a collector terminal of the first compensation transistor Q 4  and, thus, to the second current generator G 2 . 
     In the example shown in  FIG. 4 , the compensation transistors Q 4 , Q 5  and Q 6  are bipolar transistors. 
     Advantageously according to an embodiment of the invention, the base current compensation block  12  reduces a voltage on the collector terminal of the first mirror transistor Q 1 , i.e. the input voltage, to a value equal to:
 
 Vbe +( I ref+ I pol)× R 1
 
where:
         Vbe is the base-emitter voltage of the first mirror transistor Q 1 ;   Iref is the reference current issued by the first current generator G 1 ;   Ipol is the bias current issued by the second current generator G 2 ; and   R 1  is the value of the first emitter resistor connected to the first mirror transistor Q 1 .       

     It should be noted that the above voltage value is the minimum input voltage that can be reached using a current mirror comprising the emitter resistors. 
     In particular, the minimum input voltage of a bipolar current mirror using the emitter resistor R 1  is obtained (making reference to the prior art) when the block  2  of  FIG. 1  is a simple short circuit between the collector and base of Q 1 . However, in that case, the current error calculated according to the above referred equation 1 is higher and equal to: 
     
       
         
           
             Iout 
             = 
             
               Iref 
               
                 1 
                 + 
                 
                   2 
                   
                     β 
                     F 
                   
                 
               
             
           
         
       
     
     Using common values for the transistors and resistors comprised in the current mirror  10 , an input voltage value of 1-1.2V can be obtained. 
     The current mirror  10  shown in  FIG. 4  has an output current Iout given by the following equation: 
                   Iout   =       Iref   +           (       β   F     +   1     )     2           β   F     ⁡     (       β   F     +   1     )       +   1       ⁢   Ipol         1   +     2         β   F   2     ⁡     (       β   F     +   1     )       +   1                   (   2   )               
where Iout is the output current, Iref is the reference current issued by the first current generator G 1 , Ipol is the bias current issued by the second current generator G 2 , and βF is the bipolar current gain of Q 1 , Q 2 , Q 4 , Q 5  and Q 6  (supposed to be equal at a first order approximation).
 
       FIG. 5  shows a comparison of the output current error of the current mirror  10  realized according to an embodiment of the invention and the known current mirror  1  as illustrated in  FIG. 2 . 
     In particular, the current mirror error here plotted is defined as:
         for the known current mirror  1  illustrated in  FIG. 2  (plot Y):       

     
       
         
           
             Error 
             = 
             
               
                 ( 
                 
                   1 
                   - 
                   
                     Iout 
                     Iref 
                   
                 
                 ) 
               
               * 
               100 
             
           
         
       
         
         
           
             for the current mirror  10  according to an embodiment of the invention: 
           
         
       
    
             Error   =       (     1   -     Iout     Iref   +   Ipol         )     *   100           
Ipol being equal respectively to 50%, 20% and 10% of Iref for cases A, B, C.
 
     From the plots of  FIG. 5 , it can be verified that, compared to the classic current mirror, the output current of the current mirror  10  according to an embodiment of the present invention is higher than the reference plus the bias currents (error is negative). 
     It should be also emphasized that, advantageously according to an embodiment of the present invention, the current mirror error can be kept low (1%) for a higher range of the bipolar current gain βF if the bias current Ipol does not exceed 10% of the reference current Iref (plot C). 
     This can be interesting for low performance PNP transistors as shown in  FIG. 6 . 
     In this case, the mirror transistors Q 1  and Q 2  are P type transistors and the emitter resistors R 1  and R 2  are connected to the supply voltage reference Vcc. 
     The base current compensation block  12  is thus connected to ground GND. 
     It should be also remarked that, advantageously according to an embodiment of the invention, the base current compensation block  12  of the current mirror  10  also provides the same advantage (reduction of the input voltage) when emitter resistors R 1  and R 2  are not used. 
     In summary, the current mirror  10  according to an embodiment of the present invention is a bipolar current mirror having good accuracy and low input voltage, regardless of output voltage. 
     From the foregoing it will be appreciated that, although specific embodiments of the invention have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the invention. In particular, it is clear that the base current compensation block  12  can be also realized by using MOS transistors, and further could be realized with a combination of bipolar and MOS transistors. 
     Although preferred embodiments of the device of the present invention have been illustrated in the accompanying Drawings and described in the foregoing Detailed Description, it will be understood that the invention is not limited to the embodiments disclosed, but is capable of numerous rearrangements, modifications and substitutions without departing from the spirit of the invention as set forth and defined by the following claims.