Patent Publication Number: US-11646684-B2

Title: Average current control in stepper motor

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application claim priority to U.S. Provisional Application No. 62/886,983, filed Aug. 15, 2019, titled “Average Current Control in Stepper Motors,” which is hereby incorporated herein by reference in its entirety. 
    
    
     BACKGROUND 
     At least one type of stepper motor includes two cons that receive current from a stepper driver. The current to each coil should be sinusoidal with the current to one coil being 90 degrees out of phase with respect to the current to the other coil. The angular position of the stepper motor is a function of the ratio of the magnitude of the currents through the cons (e.g., the arctangent of the ratio of the magnitudes). Inaccuracies in the coil current magnitudes can cause inaccuracies in the rotational position of the motor. 
     SUMMARY 
     In at least one example, a stepper motor driver includes an H-bridge including first and second outputs. The H-bridge includes a low-side transistor coupled between the first output and a ground. A reference current circuit is configured to produce a reference current. The reference current circuit has a reference output. An averager circuit includes an input and output. The input of the averager circuit is coupled to the first output of the H-bridge. A comparator includes first and second comparator inputs. The first input of the comparator is coupled to the output of the average circuit and the second input of the comparator is coupled to the reference output. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       For a detailed description of various examples, reference will now be made to the accompanying drawings in which: 
         FIG.  1    illustrates a motor control system including an average current controller. 
         FIG.  2    illustrates current waveforms of the motor control system. 
         FIG.  3    shows an example of an H-bridge. 
         FIG.  4    illustrates example waveforms of motor coil current a current through one of the transistors of the H-bridge. 
         FIG.  5    shows an example of a stepper driver usable in the motor control system of  FIG.  1   . 
         FIG.  6    shows an example of averager circuit for use in the stepper driver. 
         FIG.  7    shows another example of averager circuit for use in the stepper driver. 
         FIG.  8    shows an example variable resistor usable in the averager circuit of  FIG.  7   . 
         FIG.  9    illustrates how a comparator&#39;s input offset can be adjusted. 
         FIG.  10    illustrates another technique for determining an average coil current. 
         FIG.  11    shows another example of a stepper driver usable in the motor control system of  FIG.  1   . 
         FIG.  12    shows an flow of the logic implemented by the stepper driver. 
     
    
    
     DETAILED DESCRIPTION 
       FIG.  1    shows an example of a stepper motor system  100 . The example stepper motor system  100  includes a controller  102  coupled to a stepper motor driver  120 , which in turn couples to a stepper motor M. The stepper motor M includes Coil  1  and Coil  2 , and the stepper driver  120  controls the current through the coils. The current through the coils is approximately sinusoidal and the current through Coil  2  is 90 degrees out of phase with respect to Coil  1 . 
     In one example, the controller  102  includes a processor or other type of digital control circuit. The controller  102  couples to the stepper driver  120  by way of a STEP signal, a direction (DIR) signal, and a programming interface. The programming interface may comprise any suitable interface such as a serial peripheral interconnect (SPI). Each rising edge of the STEP signal causes the stepper driver  120  to advance the motor&#39;s position one step, and the DIR signal specifies the direction of the motor change (forward or reverse). The stepper driver  120  includes an average current controller  121  (described below). 
       FIG.  2    illustrates examples of approximately sinusoidal currents I 1  (through Coil  1 ) and I 2  (through Coil  2 ). As can be seen, I 1  and I 2  are 90 degrees out of phase. Each sinusoidal current is formed as a series of discrete steps produced by a digital-to-analog converter within the stepper driver  120 . The stepper driver  120  regulates the current in each coil at each step. Current to a motor coil is controlled by an H-bridge (discussed below). Waveform  210  illustrates the coil current of a given step. At each step, a pair of transistors is turned during a drive mode (DRV) and current through the coil increases as shown. When the coil&#39;s current reaches an upper threshold (TH 1 ), a decay mode begins, and a different pair of transistors within the H-bridge is turned on. As a result, the coil&#39;s current decreases. At each step, the p H-bridge is controlled between alternating drive and decay modes to maintain the peak coil current at a desired level. 
     The average coil current at a given step is lower than the peak coil current. The torque in the motor, however, is a function of the average current, not peak current. By controlling the peak current of each coil, a torque imbalance may occur across the two coils, Coil  1  and Coil 2 . Further, regulating coil current based on the coil&#39;s peak current suffers from delay in the control path. A driver to turn and off the transistors of the H-bridge experiences a delay. A comparator used to compare the peak coil current to a reference value has a delay. The ripple (shown in  FIG.  2    as the difference between the upper and lower coil current values for a given step) due to the delay is a function of the supply voltage to the stepper motor system and the inductance of the motor, which can vary from motor to motor. Ripple is also a function of the off time for the driver during the decay mode. 
       FIG.  3    shows an example of an H-bridge. The example H-bridge includes high side (HS) transistors HS 1  and HS 2  and low side (LS) transistors LS 1  and LS 2 . The transistors in this example comprise n-type metal oxide semiconductor field effect transistors (NMOS) but can be implemented as different types of transistors as desired. The drains of HS 1  and HS 2  are coupled together and to a supply voltage rail, VDD. The sources of LS 1  and LS 2  are coupled together and to ground. The source of HS 1  is coupled to the drain of LS 1  and provides a first H-bridge output  310 . The source of HS 2  is coupled to the drain of LS 2  and provides a second H-bridge output  312 . A coil of the motor M is connected to outputs  310  and  312 . The other motor coil is connected to a separate H-bridge. 
     Each of the transistors has a control input (gate) and can be independently controlled. The stepper motor drive  120  can control the transistors of the H-bridge to implement three modes of operation—the drive mode noted above as well as two different decay modes. The two decay modes include a fast decay (FD) mode and a slow decay (SD) mode. During the drive mode, HS 1  and LS 2  are turned on and HS 2  and LS 1  are turned off thereby resulting current I_DRV flowing through HS 1 , motor M, and LS 1 . During the FD mode, HS 2  and LS 1  are turned on and HS 1  and LS 2  are turned off thereby resulting in current I_FD flowing through LS 1 , motor M, and HS 2 . During the SD mode, LS 1  and LS 2  are turned on and HS 1  and HS 2  are turned off thereby resulting in current I_SD flowing through LS 1 , motor M, and LS 2 . As such, coil current flows through LS 2  only during the drive and SD modes. During the FD mode, the coil current does not flow through LS 2 . 
       FIG.  4    shows example waveforms for the coil current, I_COIL 1  and the drain current through LS 2  (labeled as I_LS 2 ). During the drive mode, the coil current increases. During the FD and SD modes, the coil current decreases with the decay rate being greater during the FD mode than during the SD mode. The I_LS 2  current is equal to coil current, I_COIL 1 , during the DRV and SD modes, and, due to LS 2  being off, is zero during the FD mode. 
     In accordance with disclosed examples, the stepper driver  120  determines the average coil current and controls the transistors of the H-bridge to regulate the average coil current. The average of I_COIL 1  is represented by dashed line  410 . The average coil current level  410  is halfway between the minimum value  420  and the peak value  425 . For the I_LS 2  waveform, within each drive mode operation of the H-bridge, the mid-value  412  between the minimum value  430  (which is the same value as  420 ) and the peak value  435  (the same as  425 ) is represented by dashed line  412 , and dashed line  412  also represents the average value of the coil current. Thus, in accordance with an example, the stepper driver determines the average value of drain current through LS 2  (I_LS 2 ) during only the drive mode and uses the average value in the control of the H-bridge to cause the coil current to be regulated to a desired average value. 
       FIG.  5    illustrates how the average value of I_LS 2  is determined and used to control the coil current.  FIG.  5    shows an example of a stepper driver  500  that can be used to implement stepper driver  120  of  FIG.  1   . The stepper driver  500  includes an H-bridge comprising transistors HS 1 , HS 2 , LS 1 , and LS 2 . Coil  1  is shown in this schematic, but the coil itself is generally not a component of the semiconductor die containing the other components shown for the stepper driver  500 . In addition to the H-bridge, the stepper driver  500  includes a reference current circuit  502 , a comparator  520 , a digital logic and driver  511 , and the average current controller  121 . 
     The reference current circuit  502  includes a voltage-to-current (Vtol) converter  214 , a sine digital-to-analog converter (DAC)  506 , and a sense transistor (SNS FET), which is an NMOS transistor in this example. As shown in the example of  FIG.  5    (and as explained above regarding  FIG.  3   ), the drains of HS 1  and HS 2  are coupled together at a supply voltage rail (VDD), and the sources of LS 1  and LS 2  are coupled together at the ground node. The source of HS 1  is connected to the drain of LS 1  at a node A. Similarly, the source of HS 2  is connected to the drain of LS 2  at a node B. Coil  1  of the motor can be coupled between nodes A and B. A separate H-bridge and sense FET is provided for the other coil (Coil  2 ). 
     The digital logic and driver  211  include logic  512  coupled to a gate driver  413 . The gate driver  413  asserts gate signals Hson 1 , Hson 2 , Lson 1 , and Lson 2  for the gates of transistors HS 1 , HS 2 , LS 1 , and LS 2 , respectively. The comparator  520  includes a positive (+) input, a negative (−) input, and output. The output of comparator  520  is coupled to the digital logic and driver  211 . The comparator&#39;s positive input is coupled to node B which also represents the drain-to-source voltage of transistor LS 2 . The gate of transistor LS 2  is connected to the gate of the SNS FET, and the drain of the SNS FET is coupled to the negative input of comparator  520 . The source of the SNS FET is connected to ground. 
     The sine DAC  506  includes one input that receives microstepping indexer bits (s[n:0]) and another input that receives a reference voltage VREF. The microstepping indexer bits represent control signals for switches internal to the sine DAC  506 . The microstepping indexer bits are generated based on a DAC code, and the sine DAC converts each DAC code to an analog output voltage (Vsine), which is then converted to an analog reference current Iref by Vtol  504 . The transfer function of the sine DAC is sinusoidal meaning that as the DAC codes are increased or decreased linearly, Vsine varies sinusoidally. For example,  FIG.  2    shows the progression of the analog current from Vtol  504  as the DAC code is increased linearly and then decreased linearly. 
     The output of the Vtol converter  504  is coupled to the drain of the SNS FET and to the negative input of the comparator  520 . The reference current (Iref) output by Vtol  504  flows through the SNS FET and produces a voltage on the drain of the SNS FET and thus also on the negative input of comparator. The voltage is a function of the magnitude of Iref. A voltage is created across LS 2  (node B) that is a function of I_LS 2  (drain current through low side transistor, LS 2 ). Comparator  520  produces an output comparator signal that indicates whether the drain-to-source voltage of LS 2  (which is a function of I_LS 2 ) is smaller or larger than the drain-to-source voltage of SNS FET (which is a function of Iref). In other words, comparator  520  determines whether I_LS 2  is larger or smaller than Iref. Logic  512  receives and responds to the comparator&#39;s output signal to control the timing of the transistors within the H-bridge and enter the decay mode for a fixed time period. 
     The average current controller  121  includes an average circuit  550  and an offset compensation amplifier  555 . The input of the averager circuit  550  is coupled to the drain (node B) of LS 2  and the output of average circuit  550  is coupled to the negative input of the offset compensation amplifier  555 . The positive input of the offset compensation amplifier  555  is coupled the drain of SNS FET. The averager circuit  550  determines the average of the drain-to-source voltage of LS 2  in DRV mode. The average circuit  550  generates an averaging control signal  551  that indicates the average of LS 2 &#39;s drain-to-source voltage in DRV mode (which is a function of I_LS 2 ). Offset compensation amplifier  555  compares the averaging control signal  551  to the drain-to-source voltage of SNS FET (Iref) and produces an error control signal  557 , which indicates whether the average of the I_LS 2  current (i.e., the drain current through LS 2 ) is smaller or larger than Iref. 
     The error control signal  557  is provided to a control input of comparator  520  and causes the comparator  520  to adjusts an input offset. The input offset of comparator  520  is the minimum voltage value for which the positive input is determined to be larger than the negative input. For example, if the offset is 1 my, the positive input must be at least 1 my larger than the negative input for the output voltage from comparator  520  to be at a high logic level. The input offset of comparator  520  is adjustable and is adjustable based on the error control signal  557  from offset compensation amplifier  555 . By adjusting the input offset of comparator  520 , the control loop formed by comparing I_LS 2  to Iref and used to control the peak coil current is adjusted to cause the coil current to achieve an average value equal to Iref. If the average of I_LS 2  is less than Iref (i.e., the average coil current is too low), the error control signal  557  causes comparator  520  to decrease its input offset, which will result in the output of comparator  520  becoming logic high for peak values of the I_LS 2  current. Conversely, if the average of I_LS 2  is greater than Iref, the error control signal  557  causes comparator  520  to increase its input offset, which will require I_LS 2  peak current to be smaller before the output of comparator  520  becomes logic high. 
     The example of  FIG.  5    illustrates that the logic  512  of the digital logic and driver  511  outputs two control signal—DRV  515  and SD  517 . In some examples, logic  512  outputs DRV  515  but not SD  517 . DRV  515  is a control signal that indicates (e.g., is high) when the H-bridge is being operated in the drive mode. SD  517  is a control that indicates (e.g., is high) when the H-bridge is being operated in the SD mode. The control signals DRV  515  and SD  517  are provided to control inputs of the averager circuit  550 . 
       FIGS.  6  and  7    illustrate example implementations of an averager circuit that can be used to implement averager circuit  550  of  FIG.  5   . The example averager circuit  600  of  FIG.  6    uses the DRV  515  control signal, while the averager circuit  700  of  FIG.  7    uses both the DRV  515  and SD  517  control signals. Referring first to  FIG.  6   , averager circuit  600  includes switch SW 1 , resistor R 1 , and capacitor C 1 . SW 1  connects between the drain of LS 2  and one terminal of resistor R 1 . The other terminal of resistor R 1  is coupled to C 1  and provides the averaging control signal  551 . R 1  and C 1  form a low-pass filter. The DRV signal  515  controls the on/off state of SW 1 . When H-bridge is being operated in the drive mode, DRV signal  515  causes SW 1  to close thereby causing the low-pass filter comprising R 1  and C 1  to average the drain-to-source voltage of LS 2  as the averaging control signal  551 . 
     The RC time constant of the low-pass filter may be long enough that multiple cycles (i.e., multiple drive mode instantiations for one step) are required for the averager circuit  600  to generate a final value for the averaging control signal  551 . The example averager circuit  700  of  FIG.  7    implements a mode that expedites the averaging control signal  551  to settling at its final value. The averager circuit  700  includes two low-pass filters, each comprising a resistor coupled to a capacitor, and each averaging the drain-to-source voltage of LS 2 . The averager circuit  700  also includes a comparator  710 . One low-pass filter includes SW 1  and C 1 , as well as a resistor R 11 . R 1  in  FIG.  6    has a fixed resistance value, but R 11  in  FIG.  7    has an adjustable resistance value based on the output signal from comparator  710 . The other low-pass filter includes switch SW 2 , resistor R 2 , and capacitor C 2 . R 2  is coupled between SW 2  and C 2 . The connection between R 11  and C 1  is coupled to negative input of comparator  710  and the connection between R 2  and C 2  is coupled to positive input of comparator  710 . Switch SW 1  is closed when the H-bridge is in the drive mode and switch SW 2  is closed when the H-bridge is in the SD mode. Comparator  710  compares the average of LS 2 &#39;s drain-to-source voltage being iteratively produced during the drive mode with the average of LS 2 &#39;s drain-to-source voltage being iteratively produced during the SD mode. The time constant of R 2  and C 2  is smaller than the time constant of R 1  and C 1  (of  FIG.  6   ) and thus average of LS 2 &#39;s drain-to-source voltage produced during the SD mode settles more quickly than the average LS 2 &#39;s drain-to-source voltage being iteratively produced during the drive mode. Referring briefly to  FIG.  4   , the average of LS 2 &#39;s drain-to-source voltage during the SD mode is shown as dashed line  450 . Dashed lines  412  and  450  indicate the average values of the LS 2  drain-to-source voltage, but the LS 2  drain-to-source voltage takes a finite amount of time to settle at the values of 412 and 450. Dashed line  470  shows an example level of the averaging control signal  551  as the low-pass filter begins to settle to its final value of 412. The comparator  710  determines that level  470  is less than 450 (which the low-pass filter of R 2  and C 2  settles at very quickly). In response, the output signal from comparator  710  causes R 11  to change (e.g., decrease) its resistance thereby decreasing the RC time constant of the filter applied the LS 2  drain-to-source voltage during the drive-mode and thus causing the low-pass filter of R 11  and C 1  to begin to settle much faster than would otherwise have been the case. Once the averaging control signal  551  exceeds the level of 450 (LS 2  drain-to-source voltage during SD mode), the comparator  710  causes R 11  to increase its resistance thereby increasing the RC time constant as the averaging control signal  551  begins to become close to its final value of 412. Having a higher RC time constant of averaging control circuit (&gt;current ripple frequency) helps to reduce or avoid ripple and provide an average value of current for offset compensation. 
       FIG.  8    shows an example implementation of R 11 . As shown, R 11  comprises fixed resistors R 81  and R 82 , and transistor M 11  (e.g., an NMOS device). One terminal of R 81  is connected to the drain of M 1 . The other terminal of R 81  is connected to SW 1 . The source of M 1  is connected to C 1 . R 82  is connected across M 11  (between the drain and source) The gate of M 1  is coupled to the output of comparator  710 . Comparator  710  thus controls the gate voltage of M 1 . By controlling the gate-to-source voltage of M 1  and operating M 1  in the linear region, M 1 &#39;s drain-to-source resistance is adjustable. Thus, the effective resistance across R 11  is adjustable based on the output signal from comparator  710 . If M 1  is off, the effective resistance is the sum of the resistance of R 81  and R 82 . If M 1  is on, the effective resistance is the sum of the resistance of R 81  and the on-resistance of M 1 . 
       FIG.  9    shows an example of comparator  520  with input offset control. The comparator  520  in the example of  FIG.  9    includes an offset compensation circuit  920  coupled to an Itrip comparator stage  940 . The Itrip stage includes a current source device M 6  and a differential transistor pair  912  (comprising transistors M 4  and M 5 ). The reference current (Iref) ( FIG.  5   ) produces a voltage that is provided to the gate of M 4  within differential transistor pair  912 , and the gate of M 5  of the differential transistor pair is coupled to node B of the H-bridge. The bias current from M 6  splits between M 4  and M 5  based on the relative sizes of the gate-to-source voltages of M 4  and M 5 . 
     The offset compensation circuit  920  includes a current source device M 3  and a transistor pair M 1  and M 2 . The gate of M 2  is also coupled to SNS FET as is the gate of M 4 . The gate of M 1  is coupled to the output of offset compensation amplifier  555 , as shown. The gate of M 3  (and M 6 ) is biased at PBIAS and generates a current that splits between M 1  and M 2  and into the Itrip comparator  910 . The current from M 3  splits between M 1  and M 2  based on the relative sizes of the gate-to-source voltages of M 1  and M 2 . The current through M 1  adds to the current through M 4  as current I 4 . Similarly, the current through M 2  adds to the current through M 5  as current I 5 . As such, the input offset of comparator  520  is adjustable my altering the gate voltage of M 1  by the offset compensation amplifier. 
       FIG.  10    illustrates an example in which the coil current across all three modes (DRV, SD, and FD) is detected and used to recreate the complete coil current waveform  930 . That current waveform is then averaged ( 940 ). The current through LS 1  flows the opposite direction (source to drain) during FD mode than the current through LS 2  during DRV and SD modes (drain to source). As such, the current LS 2  during DRV and SD modes is added together and the current LS 1  during the FD mode is subtracted by subtractor  1020 . A sense FET can be connected to LS 1  (gates connected together and sources connected together) to generate a scaled copy of the current through LS 1 . 
       FIG.  11    shows an example of stepper driver  1100  that, in many respects, is identical to the stepper driver  500  of  FIG.  5   . One difference, however, is that the error control signal  557  is coupled to logic  1112  of digital logic and driver  1111 . In this implementation, logic  1112  responds to the error control signal  557  by adjusting the timing of the transistors of the H-bridge to thereby regulate the coil current based on a determination of its average value. For example, if the average coil current is too low (lower than IRef), the logic  1112  may increase the time duration of the drive mode relative to the duration of the FD and SD modes—either by increasing the duration of the drive mode or decreasing the duration of the FD and/or SD modes. Alternatively, if the average coil current is too high, the logic  1112  may increase the time duration of the SD mode. 
       FIG.  12    shows an example method illustrating the operation of stepper driver  120 . At  1201 , the method includes averaging the drain-to-source voltage of a transistor within an H-bridge (e.g., a low side transistor such as LS 2 ). At  1202 , the method includes comparing the average to a reference signal. If the average is greater than the reference signal, the method includes at  1203  modifying the stepper driver control to cause a decrease in coil current. If the average is less than the reference signal, the method includes at  1204  modifying the stepper driver control to cause an increase in coil current. Various techniques are described above for how the stepper driver can be modified to cause a change in the coil current. 
     The term “couple” is used throughout the specification. The term may cover connections, communications, or signal paths that enable a functional relationship consistent with the description of the present disclosure. For example, if device A generates a signal to control device B to perform an action, in a first example device A is coupled to device B, or in a second example device A is coupled to device B through intervening component C if intervening component C does not substantially alter the functional relationship between device A and device B such that device B is controlled by device A via the control signal generated by device A. 
     Modifications are possible in the described embodiments, and other embodiments are possible, within the scope of the claims.