Patent Publication Number: US-6703868-B2

Title: Methods, apparatus, and systems for reducing interference on nearby conductors

Description:
BACKGROUND 
     1. Field of the Invention 
     The present invention relates to information transmission. More specifically, the present invention relates to information transmission along conductive structures. 
     2. Background Information 
     Buses of parallel conductors are commonly used on circuit boards to carry data from one location to another. Problems associated with the use of such buses include delays incurred during propagation of the data signals and interference due to coupling of the conductors with one another. 
     Recently, it has become desirable to enable the use of buses of parallel conductors on small-scale structures such as within an integrated circuit (‘chip’). While the propagation delay may be minimal in such applications, undesirable coupling effects become more problematic. For example, capacitive coupling may occur between the parallel conductors, contributing to an increased impedance at high frequencies that limits bandwidth and distorts signal features. Such problems may impose undesirable limits on the maximum clock speed, the minimum size and separation of the conductors, and/or the maximum length of the bus in a particular application. 
     Timing considerations are especially critical in high-speed integrated circuits currently under development. In these circuits the time between state changes is minimal, and any fluctuation in the transition times may cause a delay that increases the error rate of the chip and decreases chip performance. In a chip clocked at 900 megahertz, for example, each cycle has a duration of only 1.1 nanosecond. If the time required to propagate a state transition across a transmission line is longer than a clock cycle, then the clock speed must be reduced. 
     As the conductors become more narrow and closer together, and as the time between state transitions decreases (e.g. as the clock speed increases), interference mechanisms that have negligible effects in other applications become limiting. In a 0.18-micron process, for example, with a pitch of 0.4 microns per wire, coupling effects may impede operation at any speed above a few hundred megahertz. For such reasons, chip designers commonly avoid long runs of parallel conductors in their designs. 
     One effect of coupling interference is an alteration of state transitions as they propagate over the conductors, resulting in a time skew of the signals being transmitted. When a new value is clocked onto a transmission line, an opposite current is induced in an adjacent (victim) transmission line. This induced current (or ‘crosstalk’) causes the skewing of a signal being transmitted on the victim line. 
     Timing within a circuit or assembly may be of critical importance: for example, when circuitry at the emitting and/or receiving sides of the transmission line is controlled by a clock (such as within an application-specific integrated circuit or ‘ASIC’). In such cases, an altered rise time of a state transition may result in a loss of synchronization between different parts of the circuit and the failure of the chip to perform properly. For example, a skew in rise time may cause a state change to be detected at the receiving side at a different time than was intended because the threshold voltage was reached before or after the intended time. 
     One method of reducing the effect of crosstalk among signals on parallel conductors includes increasing the power of the signal before transmission. As a result of recent advancements in integrated circuit technologies, however, this method has become outdated. Reduction in integrated circuit feature dimensions, for example, require a consequent reduction in the power supply voltages in order to maintain acceptably low electric field intensities. 
     An alternative approach to reducing the effect of crosstalk is to shield each transmission line individually in order to reduce the degree of crosstalk between adjacent lines. However, this method is also not viable for chip design because such shielding reduces the amount of surface area available on the chip for transmission lines and other circuit elements. A method of adding additional lines with balanced current and voltage values to counteract the effects of crosstalk and increase the distance between adjacent signal lines suffers from the same problem, as the additional lines will also consume surface area on the chip. 
     Repeaters have been used along transmission lines to decrease the total transmission time to a level at which the skew of the signal is acceptable. In other words, because delay may be due to both the skewing of the state transition and the propagation time, a reduction in the propagation time may reduce the total delay to an acceptable level. Again, however, such a method requires additional surface area on the chip (for the repeaters). Although methods exist to minimize the amount of space required for the repeaters, space limitations are still of major concern to chip designers. Additionally, the signals outputted by the repeaters may still interfere with signals on nearby conductors. 
     Reductions of scale and increased speeds associated with new integrated circuit designs require new and innovative techniques to reduce interference during information transmission. 
     SUMMARY 
     A method of data transmission according to one embodiment of the invention includes transmitting signals on adjacent conductive paths having different sequences of inversions and regenerations. For example, one such sequence may be alternating and/or opposite to another such sequence. Adjacent conductive paths that have one sequence are separated by at least one conductive path that has a different sequence. 
     In apparatus and systems for data transmission according to certain embodiments of the invention, each one of a set of conductive paths (e.g. parallel transmission lines) includes a series of inverting and non-inverting buffers. In one example, the conductive paths are fabricated on the same semiconductor substrate. At least some of the signals may have a series of state transitions synchronized to a data clock signal, which may be transmitted over one of the conductive paths. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram showing an application of a transmitter  10  according to an embodiment of the invention. 
     FIG. 2 is an exemplary illustration of time relations between signals in the application of FIG.  1 . 
     FIG. 3 is a block diagram of an application of an implementation  12  of a transmitter  10  according to an embodiment of the invention. 
     FIG. 4 is an exemplary illustration of time relations between signals in the application of FIG.  3 . 
     FIG. 5 is a block diagram of an application of an implementation  12  of a transmitter  10  according to an embodiment of the invention. 
     FIG. 6 is a block diagram of an implementation  100  of a transmitter  10  according to an embodiment of the invention. 
     FIG. 7 is a block diagram of an implementation  200  of a transmitter  10  according to an embodiment of the invention. 
     FIG. 8 is a block diagram of an implementation  102  of a transmitter  10  according to an embodiment of the invention. 
     FIG. 9 is a block diagram of an implementation  202  of a transmitter  10  according to an embodiment of the invention. 
     FIG. 10 is a block diagram of an implementation  104   a  of a transmitter  10  according to an embodiment of the invention. 
     FIG. 11 is a block diagram of an implementation  104   b  of a transmitter  10  according to an embodiment of the invention. 
     FIG. 12 is a block diagram of an implementation  106  of a transmitter  10  according to an embodiment of the invention. 
     FIG. 13 is a block diagram of an implementation  204  of a transmitter  10  according to an embodiment of the invention. 
     FIG. 14 is a block diagram of an implementation  206  of a transmitter  10  according to an embodiment of the invention. 
     FIG. 15 is a block diagram of an implementation  208  of a transmitter  10  according to an embodiment of the invention. 
     FIG. 16 is a block diagram of an implementation  210  of a transmitter  10  according to an embodiment of the invention. 
     FIG. 17 is a block diagram showing an application of a transmitter  10  and a receiver  112  according to an embodiment of the invention. 
     FIG. 18 is a block diagram of an implementation  500  of a receiver  112  according to an embodiment of the invention. 
     FIG. 19 is a block diagram of an implementation  502  of a receiver  112  according to an embodiment of the invention. 
     FIG. 20 is a block diagram of an implementation  504  of a receiver  112  according to an embodiment of the invention. 
     FIG. 21 is a block diagram of an implementation  506  of a receiver  112  according to an embodiment of the invention. 
     FIG. 22 is a block diagram showing an application of a transmitter  14  according to an embodiment of the invention. 
     FIGS. 23A,  23 B are illustrations showing transitions of signals transmitted on transmission lines that have opposite series of inverting and non-inverting buffers. 
     FIG. 24 is a block diagram showing an application of a transmitter  14  according to an embodiment of the invention. 
     FIG. 25 is a block diagram showing an application of a transmitter  14  according to an embodiment of the invention. 
     FIG. 26 is a block diagram showing an application of an implementation  106   a  of a transmitter  10  according to an embodiment of the invention. 
     FIG. 27 is a block diagram showing an application of an implementation  106   b  of a transmitter  10  according to an embodiment of the invention. 
     FIG. 28 is a block diagram showing an application of two instances  16 - 1  and  16 - 2  of an implementation  16  of a transmitter  10  according to an embodiment of the invention. 
     FIG. 29 is a block diagram showing an application of two instances  18 - 1  and  18 - 2  of an implementation  18  of a transmitter  10  according to an embodiment of the invention. 
     FIG. 30 is a block diagram showing an application of two instances  300 - 1  and  300 - 2  of an implementation  300  of a transmitter  10  according to an embodiment of the invention. 
     FIG. 31 is a block diagram showing an application of two implementations  300  and  302  of a transmitter  10  according to an embodiment of the invention. 
     FIG. 32 is a block diagram showing an application of two instances  300 - 1  and  300 - 2  of an implementation  300  of a transmitter  10  according to an embodiment of the invention. 
     FIG. 33 is a block diagram showing an application of two implementations  300  and  304  of a transmitter  10  according to an embodiment of the invention. 
     FIG. 34 is a block diagram showing an application of two instances  16 - 1  and  16 - 2  of an implementation  16  of a transmitter  10  according to an embodiment of the invention. 
     FIG. 35 is a block diagram showing an application of two instances  16 - 1  and  16 - 2  of an implementation  16  of a transmitter  10  according to an embodiment of the invention. 
     FIG. 36 is a block diagram showing an application of two instances  306 - 1  and  306 - 2  of an implementation  306  of a transmitter  10  according to an embodiment of the invention. 
    
    
     DETAILED DESCRIPTION 
     Signal transmission on sets of conductors may be performed in several different contexts. Between circuit units or assemblies, for example, signals may be transmitted across distances of centimeters or meters on a ribbon cable or another cable having parallel conductors. In a printed circuit board, signals may be transmitted on parallel conductive traces across distances of millimeters or centimeters. In a semiconductor chip, signals may be transmitted across distances of millimeters or microns on parallel conductive paths or structures that may be formed (e.g. deposited or etched) on a substrate. 
     As the characteristics of the signals (such as clock speed) change, effects that were negligible or undetectable in another application may become significant or even limiting. As signal frequencies increase, for example, capacitive effects may allow conduction between nearby conductors, resulting in crosstalk between signals. 
     Conductor dimensions may include the length, width, and thickness of each conductor; the feature pitch (characterizing the separation between conductors as measured on the substrate surface); and the vertical separation between conductors. As conductor dimensions and/or relations between those dimensions change, effects that were negligible or undetectable in another application may become significant or even limiting. 
     In wafer-scale-integration applications, for example, conductive paths less than one-half micron wide (and less than one-half micron apart) may extend in parallel buses that are dozens of centimeters long (i.e. for a length-to-width ratio of 10 6  or more). In one such application, a number of interconnected cells are fabricated on a single semiconductor substrate that may have a diameter of ten to thirty centimeters. One structure of this class (also called large-area integrated circuits or LAICs) holds an array of tens to thousands of cells that communicate over buses having dozens of conductive paths and lengths of ten to thirty centimeters. In one such example, a bus has forty parallel conductive paths and a length of up to twelve inches. 
     The signals transmitted on a set of conductors may have several different forms. For example, a portion of the set of conductors may form a parallel signal bus, with each conductor carrying a designated bit of a multi-bit information value (e.g. a byte or word). In another example, one or more of the conductors may carry data values serially. In a further example, one or more of the conductors may carry other information such as parity or other error-control information, source and/or destination information, control values, a clock signal, etc. 
     In a method for reducing interaction between signals on nearby conductors according to one embodiment of the invention, data transitions on adjacent conductors are separated in time. 
     FIG. 1 shows a block diagram of an application of an implementation  10  of a transmitter according to an embodiment of the invention. Transmitter  10  receives two sets of input signals S 10   a , S 10   b  and transmits two sets of corresponding output signals S 20   a , S 20   b  on a set of conductive paths  15 . In an exemplary implementation, conductive paths  15  are parallel to one another. 
     A time T 1  is defined as the period between a state transition on an input signal S 10   b  and the corresponding state transition on the corresponding output signal S 20   b . A time T 2  is defined as the period between a state transition on an input signal S 10   a  and the corresponding state transition on the corresponding output signal S 20   a . In the application shown in FIG. 1, time T 2  exceeds time T 1  by a delay period T_DLY. 
     FIG. 2 shows a timing diagram for an exemplary application of transmitter  10  as shown in FIG.  1 . In this example, each signal S 10  carries a series of binary values, with a transition from one value to the other being indicated by a state transition synchronous to a rising edge of a data clock signal. Relations between signals as shown in FIG. 2 are presented by way of example only and are not intended to represent limitations on the practice of the invention or of the application shown in FIG.  1 . 
     FIG. 3 shows a block diagram of an application of an implementation  12  of transmitter  10  according to an embodiment of the invention. In this application, transmitter  12  transmits each output signal S 20  on a corresponding one of a set of parallel transmission lines  20 . In one example, one or more of transmission lines  20  may include one or more buffers. These buffers (or repeaters) may be used to regenerate the signal and preserve signal bandwidth. 
     Transmitter  12  also receives a clock signal CLK 0 . Clock signal CLK 0  may have a duty cycle of 50% with substantially equal rise and fall times, although such features are not required for practice of the invention. In one example, clock signal CLK 0  has a period of 8 nanoseconds (ns) and a rise time of 1 ns. 
     FIG. 4 shows a timing diagram for an exemplary application of transmitter  12  as shown in FIG.  3 . In this example, clock signal CLK 0  has the same frequency as the data clock signal. In other applications, the data clock may be the same as clock signal CLK 0 . In further applications, one or more of the input signals S 10  may be timed according to a different frequency or offset than another of the input signals S 10 . Relations between signals as shown in FIG. 4 are presented by way of example only and are not intended to represent limitations on the practice of the invention or of the implementation shown in FIG.  3 . 
     In an exemplary implementation, delay period T_DLY is less than the period T_CLK of the data clock signal. In a further example, delay period T_DLY is at least two times the length of the rise time of the data clock signal. 
     FIG. 5 shows a block diagram of an application of an implementation  12  of transmitter  10  according to an embodiment of the invention. In this application, clock signal CLK 0  is transmitted on a transmission line  20   c   1  parallel to the transmission lines  20  that carry output signals S 20 . In another application, transmitter  12  transmits clock signal CLK 0  onto transmission line  20   c   1 . 
     FIG. 6 shows a block diagram of an implementation  100  of transmitter  10 . Transmitter  100  includes a set of first latches  110   a  that receive clock signal CLK 0  and input signals S 10   a . In response to a specified state transition of clock signal CLK 0  (e.g. a rising or falling edge), first latches  110   a  latch the data values on input signals S 10   a  onto output signals S 20   a . First latches  110   a  may be implemented using flip-flops (e.g. as shown in FIG. 6) and/or other sequential logic devices. 
     Transmitter  100  also includes a set of second latches  110   b  that receive clock signal CLK 0  and input data signals S 10   b . Upon the specified state transition of clock signal CLK 0 , second latches  110   b  latch the data values on input signals S 10   b  onto the inputs of delay elements  120 . Second latches  110   b  may be implemented using flip-flops and/or other sequential logic devices. After a predetermined delay (which may be the same for all delay elements  120  or may differ among them), delay elements  120  impose the data values onto the respective output signals S 20   b.    
     Transmitter  100  produces output signals S 20  for transmission across a set of conductive paths (e.g. as shown in FIGS. 1,  3 , and  5 ), the output signals S 20  being arranged such that adjacent conductive paths that carry outputs signals S 20   b  are separated by at least one conductive path that carries an output signal S 20   a . In an exemplary application, no two output signals  20   a  are carried over adjacent conductive paths and no two output signals  20   b  are carried over adjacent conductive paths. Because transitions on the signals S 20   b  are delayed with respect to those on the signals S 20   a , it may be understood that data transitions on adjacent conductors are separated in time. 
     It may be desirable to perform the time separation among the output signals S 20  by inserting one or more delay elements into a clock path rather than (or in addition to) inserting delay elements into one or more signal paths. FIG. 7 shows a block diagram of an alternative implementation  200  of a transmitter  100  according to an embodiment of the invention. Transmitter  200  includes a set of first latches  110   a  that receive a clock signal CLK 0  and input data signals S 10   a . As above, in response to a specified state transition of clock signal CLK 0  (e.g. a rising or falling edge), first latches  110   a  latch the data values on input signals S 10   a  onto output signals S 20   a.    
     Transmitter  200  includes a delay element  220 - 1 , which receives clock signal CLK 0  and produces a clock signal D_CLK 0  having a predetermined delay with respect to clock signal CLK 0 . Transmitter  200  also includes a set of second latches  110   b  that receive input data signals S 10   b  and delayed clock signal D_CLK 0 . In response to a specified state transition of delayed clock signal D_CLK 0 , second latches  110   b  latch the data values on input signals S 10   b  onto output signals S 20   b . In one implementation, delay element  220 - 1  introduces a predetermined delay that is variable (e.g. according to a control signal from a control unit). 
     In a transmitter according to implementation  100 , it may be desirable for the delays introduced by delay elements  120  to have values at least twice the rise time of clock signal CLK 0  and no greater than one-half of the period of clock signal CLK 0 . In a transmitter according to implementation  200 , it may be desirable for delayed clock signal D_CLK to be delayed with respect to clock signal CLK 0  by a value that is at least twice the rise time of clock signal CLK 0  and no greater than one-half of the period of clock signal CLK 0 . Particular delay values may be selected for specific applications (e.g. based on simulations) to minimize interaction among transitions on the conductive paths. 
     As compared to transmitter  100 , transmitter  200  may be constructed using fewer delay elements (in these particular examples, one delay element as compared to N/2 delay elements, where N is the total number of signal lines S 10 ). Transmitter  200  may also exhibit a more uniform power consumption over time, as no more than half of the latches in transmitter  200  switch at any given time (for an application in which the number of output signals S 20   a  equals the number of output signals S 20   b ). Additionally, for transmitter  200  as shown in FIG. 7, the number of conductive paths is not a factor in the number of delays: regardless of the number of conductors, one delay is sufficient to achieve a separation in time of data transitions on adjacent conductors. This feature may support a longer life expectancy of transmitter  200  and/or of an integrated circuit that includes transmitter  200 . 
     In some applications, it may be desirable to pass one or more of the output signals S 20  through a buffer prior to transmission on the conductive paths (e.g. transmission lines). For example, a buffer  130  may be used to boost the signal to an acceptable level for the intended receiver or to reduce the impact of a capacitive load (e.g. as may be encountered in a long transmission line). FIGS. 8 and 9 show implementations  102  and  202  of transmitters  100  and  200 , respectively, that include buffers  130 . In an exemplary implementation, a buffer  130  is implemented as two consecutive inverters, with the second inverter outputting a stronger signal (e.g. having larger transistors) than the first inverter. 
     It may be desirable to increase the separation in space between data transitions that may interfere. For example, it may be desirable to increase the distance between conductive paths carrying similarly timed data transitions. 
     FIG. 10 shows a block diagram of an implementation  104   a  of transmitter  10  according to an embodiment of the invention in which more than one other output signal S 20  separates adjacent output signals S 20  having the same clock dependence. In this example, output signals S 20   a  are not delayed, output signals S 20   b  are delayed (via delay elements  120   b ) by a first delay period, and output signals S 20   c  are delayed (via delay elements  120   c ) by a second delay period that is longer than the first delay period. Further implementations may be configured to include output signals S 20  having other delay periods, with the conductive paths being arranged to minimize signal interaction (e.g. in order of increasing delay periods as shown in FIG.  10 ). It may be desirable for the shortest delay period between adjacent conductors to have a value that is at least twice the rise time of clock signal CLK 0  and for the longest delay period among the set of conductors to have a value that is no greater than one-half of the period of clock signal CLK 0 . 
     FIG. 11 shows a block diagram of an alternative implementation  104   b  of a transmitter  104   a  as shown in FIG.  10 . In this example, the delay elements  120  all have the same delay period, such that output signals S 20   c  are delayed by twice the delay period of output signals S 20   b.    
     In some cases, it may be desirable to have a uniform delay separation between the output signals on adjacent conductors. FIG. 12 shows a block diagram of an implementation  106  of transmitter  100  according to an embodiment of the invention that has a time separation of one delay unit between output signals S 20  on adjacent conductors (in this example, delay elements  120  all have the same delay period). 
     FIG. 13 shows a block diagram of a transmitter  204  having multiple delayed clock signals D_CLK 0 , D 2 _CLK 0  in which adjacent output signals S 20  having the same clock dependence are separated by more than one other output signal S 20 . FIG. 14 shows a block diagram of a transmitter  206  having multiple delayed clock signals whose output signals S 20  have mutual time relations that are similar to those of the output signals S 20  of transmitter  106  as shown in FIG.  12 . 
     One possible advantage of an implementation  204  of a transmitter as shown in FIG. 13 is that each delay element may be loaded evenly (or nearly evenly), while in an implementation  206  of a transmitter as shown in FIG. 14, an uneven delay element fanout may result. According to the particular application, buffers  130  as described above may optionally be used in implementations of transmitter  10  as shown in FIGS. 10-14. 
     It is possible but not necessary for the number of output signals S 20  to be an integer multiple of the number of sets of latches in the transmitter. FIG. 15 shows an example in which an implementation  208  of transmitter  10  having three sets of latches is arranged to drive an eight-bit bus. 
     Also, it is possible but not necessary for the delay elements to have equal delay periods, or for the delays between sets of latches to be equal. FIG. 16 shows an example in which a unit delay separates the clock signals CLK 0  and D_CLK 0  driving latches  110   a  and  110   b , respectively, while a two-unit delay separates the clock signals D_CLK 0  and D 3 _CLK 0  driving latches  110   b  and  110   c , respectively. Other delay distributions may be implemented according to the particular application (e.g. as indicated by simulations). Also, buffers  130  as shown in FIGS. 15 and 16 may be optionally used according to the particular application. 
     FIG. 17 illustrates an application according to an embodiment of the invention that includes a transmitter  12  and transmission lines  20  as described above. This application also includes a receiver  112  configured to receive output signals S 20  and clock signal CLK 0  and to produce received signals S 60 . Depending on factors such as a time relation between clock signal transitions at the transmitter and clock signal transitions at the receiver, the length of the delay between corresponding transitions on output signals S 20   a  and S 20   b , and a desired relation between transitions on received signals S 60 , the implementation of receiver  112  may vary according to the particular application. In an exemplary application, state transitions on signals S 60  are similarly timed with respect to each other. 
     As a consequence of a delay (whether inherent or deliberate) in transmitting a clock signal to receiver  112  (e.g. over one of the transmission lines), it may be possible to use a signal based on clock signal CLK 0  to control the operation of latches  510  at the receiver. FIG. 18 shows an implementation  500  of receiver  112  according to such an embodiment of the invention. FIG. 19 shows an alternate implementation  502  in which latches  512   b  are configured to latch upon the other transition of the clock signal. 
     FIG. 20 shows an implementation  504  of receiver  112  according to another embodiment of the invention. In this implementation, a clock signal supplied to latches  510   a  is delayed by delay element  520 - 1  with respect to a clock signal CLK 0  as supplied to latches  510   b . In a case where output signals  20   b  are transmitted having a delay with respect to signals  20   a  (e.g. as described above), a net effect may be achieved in which receiver output signals S 60   a  and S 60   b  are essentially synchronous, have essentially the same time relation as they did before entering the transmitter, and/or have some other desired time relation. 
     It may be advantageous to delay the data signals at the receiver instead of delaying the clock signal, as clock delays may complicate downstream synchronous logic operations. FIG. 21 shows an implementation  506  of receiver  112  according to an embodiment of the invention in which signals S 20   a  are delayed by delay elements  520  before being inputted to latches  510   a . As in the example of FIG. 20, in a case where signals  20   b  are transmitted having a delay with respect to signals  20   a , a net effect may be achieved in which receiver output signals S 60   a  and S 60   b  are essentially synchronous, have essentially the same time relation as they did before entering the transmitter, and/or have some other desired time relation. 
     A scheme of delaying a clock signal in the transmitter may be combined with a scheme of delaying alternating latch inputs in the receiver, and vice versa, and either such scheme may also be used in combination with a scheme of using rising and falling edges to control latches in the transmitter or receiver. Receivers as illustrated in FIGS. 18-21 may also be used with other implementations of transmitter  10  as described herein. 
     In a method for reducing interaction between signals on nearby conductors according to a further embodiment of the invention, signals on adjacent conductive paths pass through different alternating sequences of inversions and regenerations. 
     FIG. 22 shows a block diagram of a system for data transmission according to an embodiment of the invention. Transmitter  10  produces a first set of output signals S 30   a  and a second set of output signals S 30   b . A first set of conductive paths  17   a  receives the first set of output signals S 30   a , and a second set of conductive paths  17   b  receives the second set of output signals S 30   b . In an exemplary implementation, conductive paths  17  are parallel to one another. 
     Each of the conductive paths  17  includes a transmission line  22  that has a series of inverting buffers I and non-inverting buffers N. Inverting buffers I invert the state transitions of the signals they pass, and non-inverting buffers N regenerate the state transitions of the signals they pass. In the system shown in FIG. 22, each of the transmission lines  22  has an alternating series of buffers, and the sequence of inversions and regenerations in the series of transmission lines  22   a  is different from (specifically, opposite to) the sequence in the series of transmission lines  22   b.    
     When the same state transition occurs on two adjacent parallel conductors at substantially the same time (e.g. two rising edges), each transition tends to speed the propagation of the other along its respective transmission line. When opposite state transitions occur on two adjacent parallel conductors at substantially the same time (e.g. a rising and a falling edge), each transition tends to slow the propagation of the other along its respective transmission line. 
     In a typical application, the relations between transitions on adjacent transmission lines are not known a priori. For example, the data values being transmitted typically are not known beforehand. As the result, the slowing or speeding of propagation of a particular transition due to nearby transitions becomes unpredictable, and an undesirable timing uncertainty may result. 
     In a system having an alternating and opposite arrangement of inversions and regenerations as shown in FIG. 22, a transition passing from one end of a transmission line to the other will see the same (or nearly the same) number of similar state transitions and opposite state transitions on an adjacent transmission line. As described below, the system may be designed such that this condition is largely independent of the relation of the state transitions originally driven onto adjacent transmission lines  22 , as is now described. 
     FIG. 23A shows an example in which a similar state transition is transmitted over two nearby transmission lines  22   a  and  22   b , and FIG. 23B shows an example in which opposite state transitions are transmitted onto the two transmission lines. In the example of FIG. 23A, transmitting a rising state transition over transmission lines  22   a ,  22   b  causes the following pairs of propagating transitions to appear on the segments of the two transmission lines (from left to right) after each of the four buffers: 
     falling/rising, falling/falling, rising/falling, rising/rising. 
     In the example of FIG. 23B, transmitting a rising state transition over transmission line  22   a  and a falling state transition over transmission line  22   b  causes the following pairs of propagating transitions to appear on the segments of the two transmission lines (from left to right) after each of the four buffers: 
     falling/falling, falling/rising, rising/rising, rising/falling. 
     Although the pairs of propagating transitions appear in a different order in each case, one may see that in both cases, each of the four possible combinations occur once and only once. One may also see that the same is true for the other two possible input combinations (namely, a falling transition over both lines, and falling and rising transitions on lines  22   a  and  22   b , respectively). Therefore, each transition transmitted along one of these transmission lines will see the same combination of transitions on the other line, regardless of whether the transitions are rising or falling, or similar or different. 
     In an application where each transition along transmission lines  22  has the same magnitude, one may expect the effect of each transition along a transmission line to be substantially constant (i.e. with respect to transitions on nearby transmission lines). Therefore, it may be desirable to configure buffers I, N such that each buffer receives a transition of substantially equal magnitude. In implementing a system as shown in FIG. 22, for example, it may be desirable for opposing buffers in adjacent transmission lines  22   a ,  22   b  (e.g. the pair of buffers I 1   a   1  and N 1   b   1 ) to be located at the same distance from transmitter  10 . 
     It may also be desirable for each buffer to produce a transition of substantially equal magnitude. It may also be desirable to place the buffers of each transmission line such that each buffer receives transitions having one uniform magnitude and produces transitions having another uniform magnitude. For example, it may be desirable to have a uniform separation between the buffers of each transmission line  22 . 
     As shown in FIG. 24, the signals carried by the parallel conductors may be used to drive one or more other sets of parallel conductors. A possible advantage of one such system is that a set of parallel conductors may be tapped off of the transmission lines in a short space, permitting transitions on the tapped conductors to have substantially equal magnitudes as well. For example, in an application characterized by a line pitch of 0.4 microns, an eight-bit bus may be tapped off over a length of less than four microns. 
     FIG. 25 shows a block diagram of a system for data transmission according to an embodiment of the invention. In this example, a pair of power rails  30   a ,  30   b  are situated parallel to and on opposite sides of the set of conductive paths  17   a ,  17   b  (here, including transmission lines  22 ). Power rails  30   a ,  30   b  may be coupled to provide an operating voltage to transmitter  10  and/or one or more of the buffers of transmission lines  22 , or these components may be powered from another source. In an exemplary implementation, power rails  30   a ,  30   b  (carrying respectively Vcc and ground potentials) reduce interference by providing a well-defined return path for the signals transmitted across conductive paths  17   a ,  17   b . The arrangement of power rails  30   a ,  30   b  as shown in FIG. 25 may be used to similar effect in other embodiments described herein that include a plurality of conductive paths, such as those shown in FIGS. 1,  3 ,  5 ,  17 ,  22 , and  29 . 
     Data transitions having the same clock dependence may be further separated in space by combining a technique for separation in time between data transitions on adjacent conductors (e.g. as discussed above with reference to FIGS. 1-16) with a technique for passing signals on adjacent conductive paths through different alternating sequences of inversions and regenerations (e.g. as discussed above with reference to FIGS.  22 - 25 ). 
     To illustrate one such example, FIG. 26 shows a combination of an application of a method according to an embodiment of the invention as shown in FIG. 10 with an application of a method according to an embodiment of the invention as shown in FIG. 22, such that similarly timed signals transmitted on adjacent conductive paths pass through different alternating sequences of inversions and regenerations. FIG. 27 shows another such combination in which adjacent conductive paths carrying similarly timed signals include transmission lines having different alternating series of inverting and non-inverting buffers and are also separated by conductive paths carrying differently timed signals. 
     In a method for reducing interaction between signals on nearby conductors according to a further embodiment of the invention, data transitions having the same clock dependence are separated in space. In one such method, a first set of signals is transmitted in one direction on a first set of parallel conductors, and a second set of signals is transmitted in the opposite direction on a second set of parallel conductors that is interleaved with the first set. 
     FIG. 28 shows a block diagram of an application of two instances  16 - 1 ,  16 - 2  of a transmitter according to an embodiment of the invention. In this application, transmitter  16  transmits output signals S 40  on a set of conductive paths  32 , and transmitter  16 - 2  transmits output signals S 50  on a set of conductive paths  34 . Conductive paths  32  and  34  are arranged such that adjacent conductors of one set are separated by at least one conductor of the other set. In an exemplary application, transmitter  16  is an implementation of transmitter  10  as described above. 
     FIG. 29 shows a block diagram of an application of two instances  18 - 1 ,  18 - 2  of a transmitter according to an embodiment of the invention. In this application, each transmitter  18  transmits each output signal S 40 , S 50  on a corresponding one of a set of conductive paths, each path including a parallel transmission line  26 , such that lines carrying signals S 40  are interleaved with lines carrying signals S 50 . Each transmitter  18  also receives the clock signal CLK 0 . In an exemplary application, transmitter  18  is an implementation of transmitter  10  as described above. 
     FIG. 30 shows implementations  300 - 1  and  300 - 2  of a transmitter according to an embodiment of the invention that are applied to receive clock signal CLK 0  and input signals S 12 , S 14  (where n is arbitrarily large) and to transmit corresponding output signals S 40 , S 50  in an interleaved fashion (e.g. as shown in FIG. 28 and 29) over conductive paths (not shown). Each among the sets of input signals S 12 , S 14  may be similar to input signals S 10  as described above. Each transmitter  300  includes a bank of latches  310 ,  312  that latch a value (e.g. state) received at an input onto an output upon a predetermined transition of clock signal CLK 0 . 
     In a system as shown in FIG. 30, it may be desirable to avoid sending data transitions in both directions at once. For example, it may be desirable for a time separation between transitions on an output signal (e.g. S 40 ) to exceed the time required for the signal to propagate from one end of the corresponding conductive path to the other. 
     A time separation between output signals S 40  and S 50  may be achieved at least in part as a consequence of an inherent delay in transmitting clock signal CLK 0  (e.g. over one of a set of conductive paths  32  or parallel transmission lines  26 ) to transmitter  300 - 2 . Alternatively, as shown in FIG. 31, such separation between output signals S 40  and S 52  may be achieved by arranging latches  310  of one transmitter  300  to latch upon one of the transitions (e.g. the rising or falling edges) of clock signal CLK 0  and arranging latches  314  of the other transmitter  302  to latch upon the other transition of clock signal CLK 0 . 
     FIG. 32 shows a further application of transmitters  300 - 1  and  300 - 2  in which a difference in timing between output signals S 40  and S 52  is achieved at least in part by inserting a delay element  320  into the path of clock signal CLK 0  to transmitter  300 - 2 . Such a delay element, for example, may be incorporated into transmitter  300 - 2  and/or may receive clock signal CLK 0  over one of a set of conductive paths carrying output signals S 40 , S 52 . 
     FIG. 33 shows a block diagram of an application including implementations  300  and  304  of a transmitter according to an embodiment of the invention that are applied to receive input signals S 12 , S 14  and transmit corresponding output signals S 40 , S 52 . In this case, the latch output signals of latches  312  are delayed by delay elements  330  before transmission over the conductive paths (not shown). Buffers as described above may also be optionally used with transmitter implementations as shown in FIGS. 28-33. 
     Data transitions may be further separated by combining a technique for passing signals on adjacent conductive paths through different alternating sequences of inversions and regenerations (e.g. as discussed above with reference to FIGS. 22-25) with a technique for transmitting signals on interleaved sets of parallel conductors (e.g. as discussed above with reference to FIGS.  28 - 33 ). To illustrate one such example, FIG. 34 shows a combination of a method according to an embodiment of the invention as shown in FIG. 28 with a method according to an embodiment of the invention as shown in FIG.  22 . In this example, signals on adjacent transmission lines are transmitted in opposite directions, while adjacent transmission lines carrying signals in the same direction include different alternating series of inverting and non-inverting buffers. FIG. 35 shows another such combination in which the transmission lines  22  are arranged in alternating pairs, each pair carrying signals in the same direction through different alternating series of inverting and non-inverting buffers. 
     Similarly timed data transitions may be further separated in space by combining a technique for separation in time between data transitions on adjacent conductors (e.g. as discussed above with reference to FIGS. 1-16) with a technique for transmitting signals on interleaved sets of parallel conductors (e.g. as discussed above with reference to FIGS.  28 - 33 ). To illustrate one such example, FIG. 36 shows a combination of an application of a method according to an embodiment of the invention as shown in FIG. 10 with an application of a method according to an embodiment of the invention as shown in FIG.  29 . This particular example also includes a delay element  320  as shown in FIG. 32 implemented as an inverter  420 . 
     In the example shown in FIG. 36, the latches of transmitter  306 - 2  receive an inversion of clock signal CLK 0 . In another implementation, inverter  420  may be included within the transmission line or within one of the transmitters. In an alternate implementation, latches of one transmitter (e.g. latches  110   a   1 - 110   c   3  of transmitter  306 - 1 ) are configured to latch upon one of the transitions of clock signal CLK 0 , while latches of the other transmitter (e.g. latches  110   a   4 - 110   c   6  of transmitter  306 - 2 ) are configured to latch upon the other transition of clock signal CLK 0  (e.g. as shown in FIG.  31 ). 
     Moreover, a technique for separation in time between data transitions on adjacent conductors (e.g. as discussed above with reference to FIGS. 1-16) may be combined with a technique for passing signals on adjacent conductive paths through different alternating sequences of inversions and regenerations (e.g. as discussed above with reference to FIGS. 22-25) and also with a technique for transmitting signals on interleaved sets of parallel conductors (e.g. as discussed above with reference to FIGS.  28 - 33 ). 
     Several different sequences of the individual conductive paths are possible for each such combination, e.g. as discussed with regard to the combinations described above. In one variation, for example, four adjacent conductive paths may carry differently timed signals in the same direction, while in another variation four adjacent conductive paths carry similarly timed signals in two different directions and through two different alternative sequences of inversions and regenerations. Simulations may be performed to determine the suitability of a particular combined scheme for a particular application. 
     The foregoing presentation of the described embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments are possible, and the generic principles presented herein may be applied to other embodiments as well. For example, the invention may be implemented in part or in whole as a hardwired circuit or as a circuit configuration fabricated into an application-specific integrated circuit. Thus, the present invention is not intended to be limited to the embodiments shown above but rather is to be accorded the widest scope consistent with the principles and novel features disclosed in any fashion herein.