Patent Publication Number: US-10770475-B2

Title: Semiconductor device and manufacturing method of semiconductor device

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     The present application claims priority under 35 U.S.C. § 119(a) to Korean patent application number 10-2018-0053866 filed on May 10, 2018 in the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. 
     BACKGROUND 
     1. Technical Field 
     The present disclosure may generally relate to a semiconductor device and a manufacturing method of a semiconductor device, and more particularly, to a three-dimensional semiconductor device and a manufacturing method of a three-dimensional semiconductor device. 
     2. Related Art 
     A semiconductor device includes a plurality of memory cells capable of storing data. For improving the degree of integration for the semiconductor device, various techniques for reducing the area occupied by the memory cells have been developed. In order to reduce the area occupied by memory cells, each of the memory cells may be finely patterned. However, there is a limitation to how finely the memory cells can be patterned. In order to overcome this limitation, various techniques for three-dimensionally arranging memory cells in a limited area have been developed. 
     SUMMARY 
     In accordance with an embodiment, a semiconductor device includes a well structure including a well dopant and a gate stack structure including a first stack structure, a second stack structure, and a third stack structure. The first, second, and third stack structures are continuously stacked in a first direction over the well structure. The gate stack structure includes a groove formed in its sidewall, the groove defined between the first stack structure and the third stack structure, wherein the first stack structure and the third stack structure protrude farther than the second stack structure in a second direction perpendicular to the first direction. The semiconductor device also includes a channel pattern penetrating the gate stack structure, the channel pattern extending along a surface of a horizontal space between the well structure and the gate stack structure. The semiconductor device also includes a memory pattern extending along an outer wall of the channel pattern, a spacer insulating pattern formed on the sidewall of the gate stack structure, and a doped semiconductor pattern formed on the spacer insulating pattern. The doped semiconductor pattern includes a source dopant and extends toward the horizontal space to contact the channel pattern. 
     In accordance with another embodiment, a semiconductor device includes supports penetrating a well structure. The supports extend farther in a first direction than the well structure. The semiconductor device also includes first and second gate stack structures disposed on the supports, a doped semiconductor pattern disposed between the first gate stack structure and the second gate stack structure, a first channel pattern penetrating the first gate stack structure, a second channel pattern penetrating the second gate stack structure, a first memory pattern extending along an outer wall of the first channel pattern, and a second memory pattern extending along an outer wall of the second channel pattern. The doped semiconductor pattern includes a vertical part extending in the first direction and horizontal protrusion parts protruding toward a sidewall of the first gate stack structure and a sidewall of the second gate stack structure from both sides of the vertical part. The first channel pattern extends along a bottom surface of the first gate stack structure to be in contact with the doped semiconductor pattern, the first channel pattern extending along sidewalls of the supports and a portion of an upper surface of the well structure under the first gate stack structure. The second channel pattern extends along a bottom surface of the second gate stack structure to be in contact with the doped semiconductor pattern, the second channel pattern extending along sidewalls of the supports and a portion the upper surface of the well structure under the second gate stack structure. 
     In accordance with an embodiment, a method of manufacturing a semiconductor device, includes: forming a well structure; forming supports penetrating the well structure, the supports extending in an upper direction from the well structure; forming a first stack structure on the supports; forming a second stack structure on the first stack structure, the second stack structure being penetrated by an etch stop pattern; forming a third stack structure extending to cover the etch stop pattern on the second stack structure; forming a slit penetrating the third stack structure and the etch stop pattern, the slit extending to the inside of the first stack structure; removing the etch stop pattern remaining at both sides of the slit such that an undercut region is defined between the third stack structure and the first stack structure, and a sidewall of the second stack structure is exposed; and replacing sacrificial layers of each of the first to third stack structures with conductive patterns through the slit and the undercut region. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Example embodiments are described herein with reference to the accompanying drawings. The drawings represent a limited number of possible embodiments. Therefore, the provided drawings and descriptions should not be construed as precluding other possible embodiments consistent with the presented claims. Presented embodiments are described to convey the present teachings to those of skill in the art. 
       In the drawing figures, dimensions may be exaggerated for clarity of illustration. It will be understood that when an element is referred to as being “between” two elements, it may be the only element between the two elements, or one or more intervening elements may also be present. Like reference numerals refer to like elements throughout the drawings. 
         FIG. 1  shows a perspective view illustrating a semiconductor device according to a first embodiment of the present disclosure. 
         FIG. 2A  shows a perspective view illustrating a current flow in a channel pattern. 
         FIG. 2B  shows an enlarged sectional view illustrating a capping pattern shown in  FIG. 2A . 
         FIG. 3  shows a plan view illustrating a layout of the semiconductor device according to the first embodiment of the present disclosure. 
         FIG. 4  shows a sectional view of the semiconductor device taken along a line X-X′ shown in  FIG. 3 . 
         FIGS. 5A to 5D, 6A to 6D, 7A to 7G, 8A to 8E, 9A, and 9B  show sectional views illustrating a manufacturing method of the semiconductor device according to the first embodiment of the present disclosure. 
         FIGS. 10A, 10B, 11A, 11B, 12A, 12B, 13A, 13B, 14A, 14B, and 15A to 15C  show views illustrating a manufacturing method of a semiconductor device according to a second embodiment of the present disclosure. 
         FIG. 16  shows a sectional view illustrating a semiconductor device according to a second embodiment of the present disclosure. 
         FIG. 17  shows a block diagram illustrating a configuration of a memory system according to an embodiment of the present disclosure. 
         FIG. 18  shows a block diagram illustrating a configuration of a computing system according to an embodiment of the present disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     The technical spirit of the present disclosure may be changed in various ways and may be implemented by different embodiments having various aspects. The present disclosure is described by a limited number of possible embodiments so that those of skill in the art can understand and practice the present teachings. 
     Although the terms “first” and/or “second” are used herein to describe various elements, these elements should not be limited by these terms. The terms are only used to distinguish one element from another element, the terms are not meant to imply a quantity or order of elements. For instance, a first element and a second element can be referred to as the second element and the first element, respectively, without departing from the teachings of the present disclosure. 
     When one element is referred to as being “coupled” or “connected” to another element, the one element can be directly coupled or connected to the other element or intervening elements may be present between the “coupled” or “connected” elements. In contrast, when an element is referred to as being “directly coupled” or “directly connected” to another element, there are no intervening elements present between the “directly coupled” or “directly connected” elements. Other expressions that explain a relationship between elements, such as “between,” “directly between,” “adjacent to,” or “directly adjacent to,” should be construed in a similar way. 
     Terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting with respect to those embodiments. In the present disclosure, singular forms are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprise,” “include,” “have,” etc., when used in this specification, specify the presence of stated features, numbers, steps, operations, elements, components, and/or combinations thereof but do not preclude the presence or addition of one or more additional features, numbers, steps, operations, elements, components, and/or combinations thereof. 
     In the drawings, the size and relative sizes of layers and areas may be exaggerated for clarity. The drawings are not drawn to scale. In the description of the present disclosure, a number of obvious configurations in light of this disclosure are omitted from the detailed description but not precluded from the present teachings. 
     Presented embodiments relate to a semiconductor device and a manufacturing method of the semiconductor device, which can improve the degree of integration for memory cells of the semiconductor device, enhance the operational reliability of the semiconductor device, and aid in the stability of manufacturing processes for the semiconductor device. 
       FIG. 1  shows a perspective view illustrating a semiconductor device  100  according to a first embodiment of the present disclosure. For convenience of description, not all components are illustrated. 
     Referring to  FIG. 1 , the semiconductor device  100  may include a well structure WE including a well dopant, gate stack structures GST 1  and GST 2  spaced apart from the well structure WE in a first direction I, spacer insulating patterns IS disposed on sidewalls of the gate stack structures GST 1  and GST 2 , a source contact structure SCL formed between adjacent spacer insulating patterns IS, a well contact structure WCL that is aligned under the source contact structure SCL and is connected to the well structure WE, an inter-well-source insulating layer SWI insulating between the well contact structure WCL and the source contact structure SCL, channel patterns CH 1  and CH 2  electrically connected to the source contact structure SCL and the well structure WE, and memory patterns ML 1  and ML 2  respectively surrounding outer walls of the channel patterns CH 1  and CH 2 . 
     The well structure WE may include a doped semiconductor layer including a well dopant. The well dopant may be a p-type dopant. The well dopant may be dispersed at a high concentration when becoming distant from the gate stack structures GST 1  and GST 2  in the well structure WE. For example, the well structure WE may be formed in a structure in which a first doped semiconductor layer D 1 A including the well dopant at a first concentration and a second doped semiconductor layer D 1 B including the well dopant at a second concentration are stacked. The first concentration is higher than the second concentration. Each of the first doped semiconductor layer D 1 A and the second doped semiconductor layer D 1 B may be a doped silicon layer. Although not shown in the drawings, a substrate including a driving circuit may be disposed under the well structure WE. The well structure WE may be disposed to overlap with the driving circuit. 
     The well structure WE may be covered with a buffer layer BU. The buffer layer BU may be formed to prevent the well dopant from diffusing toward the gate stack structures GST 1  and GST 2  from the well structure WE. The buffer layer BU may include an oxide layer. 
     The gate stack structures GST 1  and GST 2  are disposed over the well structure such that the gate stack structures GST 1  and GST 2  are spaced apart from the well structure WE. A space between the gate stack structures GST 1  and GST 2  and the well structure WE is defined as a horizontal space HSP. A gap of the horizontal space HSP is maintained by supports IP shown in  FIGS. 2A and 3 . The supports IP penetrate the well structure WE and protrude farther toward the gate stack structures GST 1  and GST 2  than the well structure WE. The structure and layout of the supports IP are described in more detail below with reference to  FIGS. 2A and 3 . 
     The gate stack structures GST 1  and GST 2  are disposed over the well structure WE to be spaced apart from each other in a second direction II. The second direction II may be a direction normally intersecting the first direction I. Although a case where two gate stack structures GST 1  and GST 2  are disposed is illustrated in the drawings, three or more gate stack structures may be spaced apart from each other along the second direction II. Each of the gate stack structures GST 1  and GST 2  includes a first stack structure ST 1 , a second stack structure ST 2 , and a third stack structure ST 3 , which are continuously stacked along the first direction I. 
     The first stack structure ST 1  may include at least one pair of a first conductive pattern CP 1  and a first interlayer insulating layer ILD 1 , which are alternately stacked in the first direction I. For example, the first stack structure ST 1  may include a pair of a first conductive pattern CP 1  and a first interlayer insulating layer ILD 1 . The first conductive pattern CP 1  is disposed in the lowermost layer of the first stack structure ST 1 . 
     The second stack structure ST 2  may include at least one second conductive pattern CP 2  and at least one second interlayer insulating layer ILD 2 . For example, the second stack structure ST 2  may include a plurality of second conductive patterns CP 2  and a plurality of second interlayer insulating layers ILD 2 . The second conductive patterns CP 2  and the second interlayer insulating layers ILD 2  are alternately stacked in the first direction I. The number of stacked second conductive patterns CP 2  and second interlayer insulating layers ILD 2 , which constitute the second stack structure ST 2 , may vary with embodiment depending on the thickness of an etch stop pattern used in a manufacturing process for the semiconductor device  100 . 
     The third stack structure ST 3  may include at least one third conductive pattern CP 3  and at least one third interlayer insulating layer ILD 3 . For example, the third stack structure ST 3  may include a plurality of third conductive patterns CP 3  and a plurality of third interlayer insulating layers ILD 3 . The third conductive patterns CP 3  and the third interlayer insulating layers ILD 3  are alternately stacked in the first direction I. The number of stacked third conductive patterns CP 3  and third interlayer insulating layers ILD 3 , which constitute the third stack structure ST 3 , may vary with embodiment depending on the stacking number of memory cells and select transistors, which constitute the semiconductor device  100 . The uppermost layer among the third interlayer insulating layers ILD 3  is disposed in the uppermost layer of the third stack structure ST 3 . At least the uppermost layer among the third conductive patterns CP 3  may be penetrated by a select line separating structure DS. 
     The first to third conductive patterns CP 1  to CP 3  may be formed of the same conductive material. The first to third conductive patterns CP 1  to CP 3  may include at least one of a doped silicon layer, a metal layer, and a metal silicide layer. For example, the first to third conductive patterns CP 1  to CP 3  may include tungsten having a low resistance. 
     The first to third conductive patterns CP 1  to CP 3  are used as gate lines SSL, WL, and DSL. The gate lines SSL, WL, and DSL may include a source select line SSL, word lines WL, and a drain select line DSL. The source select line SSL is connected to a gate electrode of a source select transistor, the word lines WL are connected to gate electrodes of memory cells, and the drain select line DSL is connected to a gate electrode of a drain select transistor. 
     A first conductive pattern CP 1  in the lowermost layer adjacent to the well structure WE among the first and second conductive patterns CP 1  and CP 2  may be used as the source select line SSL. Alternatively, each of two or more patterns continuously disposed in the upper direction (+I direction) from the lowermost layer adjacent to the well structure WE among the first and second conductive patterns CP 1  and CP 2  may be used as the source select line SSL. For example, a pattern in the lowermost layer among the second conductive patterns CP 2  may be used as the source select line SSL. 
     A pattern in the uppermost layer disposed most distant from the well structure WE among the third conductive patterns CP 3  may be used as the drain select line DSL. Alternatively, each of two or more patterns continuously disposed in the lower direction (−I direction) from the uppermost pattern among the third conductive patterns CP 3  may be used as the drain select line DSL. For example, each of the uppermost patterns among the third conductive patterns CP 3  and a pattern disposed under the uppermost pattern among the third conductive patterns CP 3  may be used as the drain select line DSL. 
     The other conductive patterns CP 2  and CP 3  disposed between the drain select line DSL and the source select line SSL are used as word lines WL. 
     The select line separating structure DS may extend along the first direction I to penetrate the third conductive patterns CP 3  used as the drain select lines DSL. The select line separating structure DS is formed of an insulating material. The depth of the select line separating structure DS may be controlled so as not to penetrate the word lines WL and the source select line SSL. 
     The first to third interlayer insulating layers ILD 1  to ILD 3  may be formed of an insulating material such as oxide layers. 
     A bottom surface of each of the gate stack structures GST 1  and GST 2  may be protected by a protective layer PL. The protective layer PL extends along the bottom surface of each of the gate stack structures GST 1  and GST 2 , and may be formed of an oxide layer. 
     The gate stack structures GST 1  and GST 2  may be covered with upper insulating layers UI 1  and UI 2 . The upper insulating layers may include a first upper insulating layer UI 1  and a second upper insulating layer UI 2  disposed on the first upper insulating layer UI 1 . Each of the first upper insulating layer UI 1  and the second upper insulating layer UI 2  may be formed of an insulating material such as an oxide layer. 
     A plurality of bit lines BL may be disposed on the second upper insulating layer UI 2 . Each of the bit lines BL for transferring an electrical signal may extend in a horizontal direction vertically intersecting the first direction I. For example, each of the bit lines BL may extend along the second direction II. The layout of the bit lines BL may vary depending on design. As shown in  FIG. 2A , each of the bit lines BL is connected to a pillar part PP corresponding thereto. The pillar part PP is surrounded by a gate stack structure corresponding thereto among the gate stack structures GST 1  and GST 2 . The pillar part PP is described in detail below with reference to  FIG. 2A . The bit lines BL are electrically insulated from the source contact structure SCL by the second upper insulating layer UI 2 . 
     The spacer insulating patterns IS are formed on both sidewalls of each of the gate stack structures GST 1  and GST 2 . The spacer insulating patterns IS insulate between the source contact structure SCL and the gate stack structures GST 1  and GST 2 . The spacer insulating patterns IS may be formed of oxide layers. 
     The source contact structure SCL is formed between adjacent gate stack structures to fill in a space between spacer insulating patterns IS adjacent to each other. For example, the source contact structure SCL may be disposed between a first gate stack structure GST 1  and a second gate stack structure GST 1 , which are opposite to each other. The source contact structure SCL is formed of a conductive material to transfer an electrical signal. The source contact structure SCL may include a source dopant. The source dopant is a dopant of a conductivity type different from that of the well dopant, and may be, for example, an n-type dopant. The source contact structure SCL may protrude farther toward the well structure WE than the gate stack structures GST 1  and GST 2 . The source contact structure SCL extends between end portions of channel patterns CH 1  and CH 2  adjacent to each other. The end portions of the channel patterns CH 1  and CH 2  adjacent to each other are in direct contact with both sidewalls of the source contact structure SCL. 
     The spacer insulating patterns IS and the source contact structure SCL penetrate the first upper insulating layer UI 1 , and may extend toward the second upper insulating layer UI 2 . 
     The well contact structure WCL is in direct contact with the well structure WE and extends toward the source contact structure SCL. The well contact structure WCL has a sidewall in contact with a portion of each of the channel patterns CH 1  and CH 2 . The well structure WE and the channel patterns CH 1  and CH 2  are electrically connected by the well contact structure WCL. The well contact structure WCL may be formed of a conductive layer. For example, the well contact structure WCL may be formed of a semiconductor layer such as a silicon layer. The well contact structure WCL may include the well dopant diffused from the well structure WE. 
     The inter-well-source insulating layer SWI is disposed between the well contact structure WCL and the source contact structure SCL to insulate between the well contact structure WCL and the source contact structure SCL. The inter-well-source insulating layer SWI may be formed of an insulating material such as an oxide layer. 
     Each of the gate stack structures GST 1  and GST 2 , the select line separating structure DS, the spacer insulating patterns IS, the source contact structure SCL, the inter-well-source insulating layer SWI, and the well contact structure WCL may extend along the horizontal direction. For example, each of the gate stack structures GST 1  and GST 2 , the select line separating structure DS, the spacer insulating patterns IS, the source contact structure SCL, the inter-well-source insulating layer SWI, and the well contact structure WCL may extend in a third direction III intersecting the second direction II. The third direction III may normally intersect the first direction I. 
     Each of the channel patterns CH 1  and CH 2  and the memory patterns ML 1  and ML 2  may include first to third parts LP 1  to LP 3  as shown in  FIG. 2A . The first part LP 1  is a part extending along an upper surface of the horizontal space HSP adjacent to the gate stack structure GST 1  or GST 2  corresponding thereto, and the second part LP 2  is a part extending to a lower surface of the horizontal space HSP adjacent to the well structure WE. The horizontal space HSP may be filled with insulating patterns FI 1  and FI 2 . A corresponding insulating pattern FI 1  or FI 2  is disposed between the first part LP 1  and the second part LP 2 , and the first part LP 1  and the second part LP 2  are spaced apart from each other by the corresponding insulating pattern FI 1  or FI 2 . The third part LP 3  is a part extending along a sidewall of each of the supports IP. The first part LP 1  and the second part LP 2  may be connected to each other by the third part LP 3 . 
     Each of the channel patterns CH 1  and CH 2 , as shown in  FIG. 1 , may include a junction JN in which the source dopant is dispersed. The junction JN is defined in each of the channel patterns CH 1  and CH 2  adjacent to the source contact structure SCL. 
       FIG. 2A  shows a perspective view illustrating a current flow in a channel pattern. 
     Referring to  FIG. 2A , the semiconductor device  100  may include supports IP supporting the gate stack structures GST 1  and GST 2  shown in  FIG. 1  to maintain the gap of the horizontal space HSP shown in  FIG. 1 . Although  FIG. 2A  illustrates one support IP, a plurality of supports IP may maintain the gap of the horizontal space HSP shown in  FIG. 1 . An example of the arrangement structure of the plurality of supports is described later with reference to  FIG. 3 . The supports IP penetrate the well structure WE and may extend in the first direction I to protrude farther in the upper direction than the well structure WE. The gate stack structures GST 1  and GST 2  shown in  FIG. 1  are disposed on the supports IP. 
     Each of the channel patterns CH 1  and CH 2  and the memory patterns ML 1  and ML 2  may include pillar parts PP and first to third parts LP 1  to LP 3 . 
     The pillar parts PP are parts penetrating the gate stack structures GST 1  and GST 2  shown in  FIG. 1 , and extend along the first direction I. An example of the arrangement structure of the pillar parts PP is described later with reference to  FIG. 3 . 
     The first part LP 1  of each of the channel patterns CH 1  and CH 2  and the memory patterns ML 1  and ML 2  is adjacent to one corresponding thereto among the gate stack structures GST 1  and GST 2  shown in  FIG. 1 , and extends along the horizontal direction. The second part LP 2  of each of the channel patterns CH 1  and CH 2  and the memory patterns ML 1  and ML 2  is disposed under the first part LP 1 , and is disposed adjacent to the well structure WE. A corresponding insulating pattern FI 1  or FI 2  is disposed between the first part LP 1  and the second part LP 2 , which are opposite to each other. The second part LP 2  extends along the horizontal direction. The third part LP 3  of each of the channel patterns CH 1  and CH 2  and the memory patterns ML 1  and ML 2  extends along a sidewall of the supports IP, which corresponds thereto, and connects the first part LP 1  and the second part LP 2 . 
     The first part LP 1  extends from the pillar parts PP to connect the pillar parts PP to each other. The third part LP 3  is disposed between a corresponding insulating pattern FI 1  or FI 2  and the supports IP, and extends toward the second part LP 2  from the first part LP 1 . 
     According to the above-described structure, each of the channel patterns CH 1  and CH 2  is formed as an integrated pattern including the first to third parts LP 1  to LP 3 . Each of the pillar parts PP may be connected to a bit line BL corresponding thereto via a bit line contact plug BCT. Although  FIG. 2A  illustrates one bit line BL, the semiconductor device  100  may include a plurality of bit lines, and the layout of the bit lines may be variously designed. The bit line contact plug BCT penetrates the upper insulating layers UI 1  and UI 2  shown in  FIG. 1 . 
     Each of the memory patterns ML 1  and ML 2 , which includes a plurality of pillar parts PP and first to third parts LP 1  to LP 3 , may include a tunnel insulating layer TI, a data storage layer DL, and a first blocking insulating layer BI 1 . Each of the tunnel insulating layer TI, the data storage layer DL, and the first blocking insulating layer BI 1  are included in the plurality of pillar parts PP and the first to third parts LP 1  to LP 3 . 
     The tunnel insulating layer TI surrounds each of the channel patterns CH 1  and CH 2 . The first blocking insulating layer BI 1  surrounds each of the channel patterns CH 1  and CH 2  with the tunnel insulating layer TI interposed therebetween. The data storage layer DL is disposed between the tunnel insulating layer TI and the first blocking insulating layer BI 1 . The data storage layer DL may store data changed using Fowler-Nordheim tunneling caused by a difference in voltage between the channel patterns CH 1  and CH 2  and the word line WL shown in  FIG. 1 . To this end, the data storage layer DL may be formed of various materials. For example, the data storage layer DL may be formed of a nitride layer in which charges can be trapped. In addition, the data storage layer DL may include silicon, a phase change material, nanodots, and the like. The first blocking insulating layer BI 1  may include an oxide layer capable of blocking charges. The tunnel insulating layer TI may include a silicon oxide layer. 
     The insulating patterns FI 1  and FI 2  penetrate the gate stack structures GST 1  and GST 2  shown in  FIG. 1  and extend to the inside of the horizontal space HSP shown in  FIG. 1 . A portion of each of the insulating patterns FI 1  and FI 2  is surrounded by pillar parts PP corresponding thereto. The insulating patterns FI 1  and FI 2  may be formed with a height lower than that of the pillar parts PP. Capping patterns CAP surrounded by the pillar parts PP may be disposed on the insulating patterns FI 1  and FI 2 . Each of the capping patterns CAP may be used as a drain junction. 
       FIG. 2B  shows an enlarged sectional view illustrating the capping pattern shown in  FIG. 2A . 
     The capping pattern CAP may include a doped semiconductor layer DSE. The capping pattern CAP may further include an upper end UCH corresponding to an upper portion of each of the pillar parts PP of the channel patterns CH 1  and CH 2  shown in  FIG. 2A . The doped semiconductor layer DSE is surrounded by the upper end UCH. The upper end UCH and the doped semiconductor layer DSE, which constitute the capping pattern CAP, include a drain dopant. The drain dopant may be a dopant of the same conductivity type as the source dopant, and may be, for example, an n-type dopant. The doped semiconductor layer DSE may be a doped silicon layer doped with an n-type dopant. 
     Referring back to  FIG. 2A , the source contact structure SCL shown in  FIG. 1  may include a doped semiconductor pattern DSP in contact with the channel patterns CH 1  and CH 2 . The doped semiconductor pattern DSP may include a vertical part VP extending along the first direction I and horizontal protrusion parts HP protruding from both sides of the vertical part VP. The horizontal protrusion parts HP are parts protruding toward the gate stack structures GST 1  and GST 2  shown in  FIG. 1 . The vertical part VP may extend in parallel to the supports IP and may have a surface facing the supports IP. The doped semiconductor pattern DSP may be formed of a semiconductor layer including a source dopant. For example, the doped semiconductor pattern DPS may be formed of a doped silicon layer doped with an n-type dopant. 
     According to the above-described structure, a first current flow path Ir may be established during a read operation of the semiconductor device  100 . The first current flow path Ir is formed in a selected channel pattern (e.g., CH 1 ). In a read operation, the bit line BL may be precharged to a predetermined level. Also, in the read operation, a turn-on voltage may be applied to the drain select line DSL and the source select line SSL, which are shown in  FIG. 1 . Under this voltage application condition, when a voltage level applied to the word lines WL of the first gate stack structure GST shown in  FIG. 1  is higher than threshold voltages of memory cells connected to the word lines WL, a channel may be formed in the selected channel pattern CH 1 , and a precharge level of the bit line BL may be discharged through a ground (not shown) electrically connected to the doped semiconductor pattern DPS. 
     A second current flow path Ie may be established during an erase operation of the semiconductor device  100 . The second current flow path Ie is formed in a channel pattern (e.g., CH 2 ) connected between the bit line BL and the well structure WE. 
     The inter-well-source insulating layer SWI disposed between the doped semiconductor pattern DSP and the well contact structure WCL can reduce leakage current between the doped semiconductor pattern DPS and the well contact structure WCL during an operation of the semiconductor device  100 . 
     In the embodiment described above, the well contact structure WCL may extend in parallel to the support IP and may have a surface facing the support IP. 
       FIG. 3  shows a plan view illustrating a layout of the semiconductor device  100  according to an first embodiment of the present disclosure. More specifically,  FIG. 3  illustrates a top-down plan view taken from above a plane defined in the I-II directions by the horizontal line A-A′ shown in  FIG. 1 . 
     Referring to  FIG. 3 , each of the pillar parts PP described with reference to  FIG. 2A  may be formed to surround the capping pattern CAP. 
     The pillar parts PP penetrating each of the gate stack structures GST 1  and GST 2  may be divided into a first group GR 1  and a second group GR 2 , which are disposed with the select line separating structure DS interposed therebetween. In order to improve the arrangement density of memory strings, the pillar parts PP of the first group GR 1  and the pillar parts PP of the second group GR 2  may be arranged in a zigzag pattern, as shown. 
     The gate stack structures GST 1  and GST 2  are opposite to each other in the second direction II with the source contact structure SCL interposed therebetween, and may be insulated from the source contact structure SCL by the spacer insulating patterns IS. 
     The semiconductor device  100  may further include a second blocking insulating layer BI 2 . The second blocking insulating layer BI 2  may extend between each of the gate stack structures GST 1  and GST 2  and each of the spacer insulating patterns IS. 
     The supports IP are disposed under the gate stack structures GST 1  and GST 2 . The supports IP may be disposed between the pillar parts PP not to overlap with the pillar parts PP. Alternatively, the supports IP may overlap with portions of the pillar parts PP. 
     The supports IP may be disposed between the pillar parts PP adjacent to each other. The supports IP may be arranged in a zigzag pattern. The layout of the supports IP is not limited to the example shown in  FIG. 3  and may be different for different embodiments. 
     The number of columns configured with the pillar parts PP of the first group GR 1  penetrating each of the gate stack structures GST 1  and GST 2  and the number of columns configured with the pillar parts PP of the second group GR 2  penetrating each of the gate stack structures GST 1  and GST 2  may be different for different embodiments. 
     The select line separating structure DS may overlap with dummy plugs DP. The dummy plugs DP may be arranged in a line along the direction of the select line separating structure DS. The dummy plugs DP may be formed using the same process for forming the pillar parts PP. 
       FIG. 4  shows a sectional view of the semiconductor device  100  taken in the I-II plane along line X-X′ shown in  FIG. 3 .  FIG. 4  shows a sectional view obtained by cutting in the vertical direction, so as not to intersect the supports IP, the gate stack structures GST 1  and GST 2  and illustrates a section of the channel patterns CH 1  and CH 2 . 
     Referring to  FIG. 4 , the first to third stack structures ST 1  to ST 3  included in each of the gate stack structures GST 1  and GST 2  are patterned in a structure in which a groove GV is defined in the sidewall of each of the gate stack structures GST 1  and GST 2 . For example, the first stack structure ST 1  and the third stack structure ST 3  protrude farther in the second direction II of  FIG. 1  than the second stack structure ST 2 . Accordingly, the groove GV is defined between the first stack structure ST 1  and the third structure ST 3 . 
     The first and third conductive patterns CP 1  and CP 3  may protrude farther toward the spacer insulating patterns IS than the second conductive patterns CP 2 . The first and third interlayer insulating layers ILD 1  and ILD 3  may protrude farther toward the spacer insulating patterns IS than the second interlayer insulating layers ILD 2 . The second interlayer insulating layers ILD 2  may protrude farther toward the spacer insulating patterns IS than the second conductive patterns CP 2 . The third interlayer insulating layers ILD 3  may protrude farther toward the spacer insulating patterns IS than the third conductive patterns CP 3 . Accordingly, recesses R may be defined between protrusions P of the first to third interlayer insulating layers ILD 1  to ILD 3  of the first to third stack structures ST 1  to ST 3 . 
     Each of the spacer insulating patterns IS may be formed to fill in the recesses R. A central region of the groove GV is filled with a doped semiconductor pattern DPS disposed between the spacer insulating patterns IS. 
     The doped semiconductor pattern DPS may constitute the source contact structure SCL. The source contact structure SCL may further include the doped semiconductor pattern DPS, a metal silicide layer SC, a metal layer MS, and a metal barrier layer BM. 
     The doped semiconductor pattern DPS is disposed between the gate stack structures GST 1  and GST 2  adjacent to each other, and extends along the first direction I shown in  FIG. 1 . The horizontal protrusion part HP of the doped semiconductor pattern DPS, which is described with reference to  FIG. 2A , is a part that protrudes toward the groove GV and completely fills in the central region of the groove GV. The doped semiconductor pattern DPS may extend toward the well structure WE to be in contact with the first part LP 1  of each of the channel patterns CH 1  and CH 2 . The doped semiconductor pattern DPS may extend toward the well structure WE to be in contact with sidewalls of the insulating patterns FI 1  and FI 2  filling in the horizontal space HSP. 
     The metal layer MS penetrates the first upper insulating layer UI 1  and may be aligned on the doped semiconductor pattern DPS. The metal silicide layer SC is aligned between the metal layer MS and the doped semiconductor pattern DPS. The metal barrier layer BM extends along an interface between the metal silicide layer SC and the metal layer MS and an interface between the spacer insulating patterns IS and the metal layer MS. The metal silicide layer SC and the metal layer MS have a resistance lower than that of the doped semiconductor pattern DPS, and may decrease the resistance of the source contact structure SCL. The metal silicide layer SC may include tungsten silicide, nickel silicide, and the like. The metal layer MS may include tungsten and the like. The metal barrier layer BM prevents diffusion of metal, and may include a titanium nitride layer, a tungsten nitride layer, a tantalum nitride layer, and the like. 
     The first parts LP 1  of the channel patterns CH 1  and CH 2  extend onto the bottom surfaces of the gate stack structures GST 1  and GST 2  from the pillar parts PP. Each of the first parts LP 1  extends onto a lower surface of a spacer insulating pattern IS corresponding thereto, and protrudes farther in the second direction II of  FIG. 1  than the first stack structure ST 1  to be in contact with the doped semiconductor pattern DPS. Each of the first parts LP 1  has a source contact surface in contact with the doped semiconductor pattern DPS. A source dopant in the doped semiconductor pattern DPS is diffused into the first parts LP 1  of the channel patterns CH 1  and CH 2  from the source contact surface. The junction JN that is a diffusion region of the source dopant is defined in each of the first parts LP 1  of the channel patterns CH 1  and CH 2 . 
     The second parts LP 2  extending from the third parts LP 3  of the channel patterns CH 1  and CH 2  described with reference to  FIG. 2A  are disposed on the well structure WE. Each of the second parts LP 2  of the channel patterns CH 1  and CH 2  extends towards the well contact structure WCL to be in contact with the well contact structure WCL. 
     The memory patterns ML 1  and ML 2  extend along the outer walls of the channel patterns CH 1  and CH 2 , respectively. Each of the memory patterns ML 1  and ML 2  and the channel patterns CH 1  and CH 2  extends along the upper surface of the well structure WE, the sidewall of the support IP shown in  FIG. 2A , and the bottom surface of any one of the gate stack structures GST 1  and GST 2 . A surface of the horizontal space HSP may be defined along the upper surface of the well structure WE, the sidewall of the support IP shown in  FIG. 2A , and the bottom surface of each of the gate stack structures GST 1  and GST 2 . 
     Each of the insulating patterns FI 1  and FI 2  has a sidewall in contact with the doped semiconductor pattern DPS, the well contact structure WCL, and the inter-well-source insulating layer SWI. 
     The second blocking insulating layer BI 2  may be formed of an insulating material having a dielectric constant higher than that of the first blocking insulating layer BI 1  of  FIG. 2A  included in each of the memory patterns ML 1  and ML 2 . For example, the second blocking insulating layer BI 2  may be formed of an aluminum oxide layer. The second blocking insulating layer BI 2  may be formed on a sidewall of each of the first to third conductive patterns CP 1  to CP 3 , which faces the pillar parts PP. The second blocking insulating layer BI 2  may extend between the first to third conductive patterns CP 1  to CP 3  and the first to third interlayer insulating layers ILD 1  to ILD 3 . The second blocking insulating layer BI 2  may extend between the first conductive pattern CP 1  and the protective layer PL, and extend between the spacer insulating patterns IS and the first to third interlayer insulating layers ILD 1  to ILD 3 . 
     Although not shown in the drawing, a barrier layer for preventing direct contact between each of the first to third conductive patterns CP 1  to CP 3  and the second blocking insulating layer BI 2  may be further formed between each of the first to third conductive patterns CP 1  to CP 3  and the second blocking insulating layer BI 2 . The barrier layer may include a titanium nitride layer, a tungsten nitride layer, a tantalum nitride layer, and the like. 
     According to the present disclosure, source select transistors may be defined at intersection portions of the pillar parts PP of the channel patterns CH 1  and CH 2  and the source select line SSL, memory cells may be defined at intersection portions of the pillar parts PP of the channel patterns CH 1  and CH 2  and the drain select line DSL, and drain select transistors may be defined at intersection portions of the pillar parts PP of the channel patterns CH 1  and CH 2  and the drain select line DSL. The memory cells are arranged along the pillar parts PP of each of the channel patterns CH 1  and CH 2 , and are three-dimensionally arranged along the first to third directions I to III, thereby constituting a three-dimensional semiconductor device  100 . 
     According to an embodiment of the present disclosure, any etch stop pattern does not remain between the source select line SSL and the junction JN, and the source select line SSL and the junction JN are disposed close to each other. Accordingly, in the present disclosure, the turn-on current of the source select transistor can be increased. Further, in the present disclosure, current loss due to remaining of an etch stop pattern is improved, so that cell current in the channel patterns CH 1  and CH 2  can be increased. Accordingly, the operational reliability of the semiconductor device  100  can be enhanced. 
     According to an embodiment of the present disclosure, the well contact structure WCL can be easily formed by the groove GV formed in the sidewall of each of the gate stack structures GST 1  and GST 2 , so that the level of difficulty of manufacturing processes of the semiconductor device  100  can be lowered. 
     According to an embodiment of the present disclosure, each of the channel patterns CH 1  and CH 2  includes the first part LP 1  electrically connected to the well structure WE including the well dopant through the well contact structure WCL and the second part LP 2  electrically connected to the source contact structure SCL including the source dopant. The source contact structure SCL and the well contact structure WCL are structurally separated from each other by the inter-well-source insulating layer SWI. Thus, the flow of current in a program operation and a read operation can be controlled to face the source contact structure SCL, and holes can be supplied through the well structure WE in an erase operation. Accordingly, operation characteristics of the semiconductor device  100  can be enhanced. 
     The inter-well-source insulating layer SWI disposed between the doped semiconductor pattern DPS of the source contact structure and the well contact structure WCL can reduce leakage current between the junction JN and the well structure WE. Accordingly, the operational reliability of the semiconductor device  100  can be enhanced. 
       FIGS. 5A to 5D, 6A to 6D, 7A to 7G, 8A to 8E, 9A, and 9B  show sectional views illustrating a manufacturing method of the semiconductor device  100  according to the first embodiment of the present disclosure. In particular,  FIGS. 5A to 5D, 6A to 6D, 7A to 7G, 8A to 8E, 9A, and 9B  show manufacturing process sectional views of the semiconductor device  100  taken along line Y-Y′ shown in  FIG. 3 . 
       FIGS. 5A to 5D  show sectional views illustrating a process of forming a well structure, a process of forming supports, and processes of forming first to third stack structures. 
     Although not shown in the drawings, before the well structure is formed, driving transistors constituting a driving circuit for driving the semiconductor device  100  may be formed on a substrate (not shown). The well structure may be formed on the substrate including the driving transistors. 
     Referring to  FIG. 5A , a well structure WE including a well dopant is formed on a substrate (not shown). The process of forming the well structure WE may include a process of forming a first doped semiconductor layer  101  including the well dopant at a first concentration and a process of forming a second doped semiconductor layer  103  including the well dopant at a second concentration lower than the first concentration. The second doped semiconductor layer  103  is formed on the first doped semiconductor layer  101 . Each of the first doped semiconductor layer  101  and the second doped semiconductor layer  103  may be a doped silicon layer. The process of forming the second doped semiconductor layer  103  may include a process of forming an undoped silicon layer on the first doped semiconductor layer  101  and a process of diffusing the well dopant in the first doped semiconductor layer  101  into the undoped silicon layer through a heat treatment process. 
     Subsequently, a buffer layer  105  may be further formed on the well structure WE. The buffer layer  105  may be formed to prevent the well dopant from being diffused from the well structure WE. The buffer layer  105  may be formed of a material different from that of a first lower sacrificial layer  111  formed in a subsequent process. For example, the buffer layer  105  may be formed of an oxide layer. 
     After this, the first lower sacrificial layer  111  and a second lower sacrificial layer  113  are sequentially stacked on the buffer layer  105 . The first lower sacrificial layer  111  and the second lower sacrificial layer  113  may be formed of a material having an etch rate different from those of first and second material layers  121   a  and  123   a  of a first stack structure PST 1  to be formed in a subsequent process. The first lower sacrificial layer  111  and the second lower sacrificial layer  113  may be formed of materials different from each other. For example, the first lower sacrificial layer  111  may be formed of a silicon layer, and the second lower sacrificial layer  113  may include a metal. For one embodiment, the second lower sacrificial layer  113  may be formed of tungsten or titanium nitride (TiN). 
     Subsequently, supports IP may be formed, which penetrate the second lower sacrificial layer  113 , the first lower sacrificial layer  111 , the buffer layer  105 , and the well structure WE. The supports IP are arranged to be spaced apart from each other. The process of forming of the supports IP may include a process of forming a mask pattern, using a photolithography process, a process of forming through-holes by etching the second lower sacrificial layer  113 , the first lower sacrificial layer  111 , the buffer layer  105 , and the well structure WE through an etching process using the mask pattern as an etch barrier, a process of filling the through-holes with an insulating material, a process of planarizing a surface of the insulating material, and a process of removing the remaining mask pattern. 
     An oxide layer may be used as the insulating material for the supports IP. The well structure WE may be patterned in a desired pattern, using the photolithography process for forming the supports IP. Accordingly, manufacturing processes of the semiconductor device  100  can be simplified. 
     The supports IP protrude farther in the upper direction than the well structure WE to further penetrate the second lower sacrificial layer  113  and the first lower sacrificial layer  111 , which are disposed on the well structure WE. 
     After this, a protective layer  115  may be further formed. The protective layer  115  is formed of a material different from those of the first lower sacrificial layer  111  and the second lower sacrificial layer  113 , and may be formed of an oxide layer. 
     Subsequently, the first stack structure PST 1  is formed on the protective layer  115 . The first stack structure PST 1  may include at least one pair of first and second material layers  121   a  and  123   a  that are alternately stacked. The first material layer  121   a  may be formed of an insulating material for sacrificial layers, and the second material layer  123   a  may be formed of an insulating material for interlayer insulating layers. For example, the first material layers  121   a  may be formed of a silicon nitride layer, and the second material layers  123   a  may be formed of a silicon oxide layer. The first material layer  121   a  is disposed in the lowermost layer of the first stack structure PST 1 . 
     After this, a second stack structure PST 2  is formed by alternately stacking first material layers  121   b  and second material layers  123   b  on the first stack structure PST 1 . The first material layers  121   b  of the second stack structure PST 2  are the same as the first material layer  121   a  of the first stack structure PST 1 , and the second material layers  123   b  of the second stack structure PST 2  are the same as the second material layer  123   a  of the first stack structure PST 1 . The lowermost and uppermost layers among the first material layers  121   b  are disposed in the lowermost and uppermost layers of the second stack structure PST 2 . The stacking number of first material layers  121   b  and second material layers  123   b , which constitute the second stack structure PST 2  may be variously changed such that the thickness of the second stack structure PST 2  is equal to or larger than that of an etch stop pattern that serves as an etch stop layer. 
     Subsequently, a planarizing protective layer  125  formed of a material different from that of the first material layers  121   b  is formed on the second stack structure PST 2 . 
     Subsequently, a trench T exposing the first stack structure PST 1  is formed by etching the planarizing protective layer  125  and the second stack structure PST 2 . The trench T may extend along the third direction shown in  FIG. 1 . A photography process may be used to form the trench T. 
     Referring to  FIG. 5B , after an etch stop layer is formed such that the trench T shown in  FIG. 5A  is completely filled therewith, the etch stop layer is polished until the planarizing protective layer  125  is exposed. Accordingly, an etch stop pattern  127 P is formed in only the trench T. The etch stop layer for the etch stop pattern  127 P is formed of a material having an etch rate different from those of the material layers constituting the first and second stack structures PST 1  and PST 2  and material layers constituting a third stack structure PST 3  to be formed in a subsequent process. For example, the etch stop layer for the etch stop pattern  127 P may be formed of a silicon layer. 
     Referring to  FIG. 5C , the planarizing protective layer  125  and the etch stop pattern  127 , which are shown in  FIG. 5B , may be polished such that the first material layer  121   b  disposed in the uppermost layer of the second stack structure PST 2  is exposed. Accordingly, the second stack PST 2  penetrated by the etch stop pattern  127 P is formed. According to the present disclosure, the secondary polishing process is performed in a state in which the surface roughness of the etch stop layer is reduced through the primary polishing process, so that the uppermost layer of the second stack structure PST 2  is exposed. As a result, a phenomenon can be minimized, in which the thickness of the first material layer  121   b  disposed in the uppermost layer of the second stack structure PST 2  is lost due to the planarizing process for forming the etch stop pattern  127 P. 
     Referring to  FIG. 5D , the third stack structure PST 3  extending to cover the etch stop pattern  127 P is formed on the second stack structure PST 2 . The third stack structure PST 3  is formed on the second stack structure PST 2  by alternately stacking first material layers  121   c  and second material layers  123   c . The first material layers  121   c  of the third stack structure PST 3  are the same as the first material layer  121   a  of the first stack structure PST 1  described with reference to  FIG. 5A , and the second material layers  123   c  of the third stack structure PST 3  are the same as the second material layer  123   a  of the first stack structure PST 1  described with reference to  FIG. 5A . The lowermost and uppermost layers among the second material layers  123   c  may be disposed in the lowermost and uppermost layers of the third stack structure PST 3 . The stacking number of first material layers  121   c  and the second material layers  123   c , which constitute the third stack structure PST 3 , may be variously changed. The second material layer  123   c  disposed in the uppermost layer of the third stack structure PST 3  may be formed thicker than the second material layers on the bottom thereof, and be used as a mask. 
     The first to third stack structures PST 1  to PST 3  include first regions P 1 . The first regions P 1  are defined as regions in which the first to third stack structures PST 1  to PST 3  all overlap with one another. Each of the first to third stack structures PST 1  to PST 3  further includes a second region P 2  overlapping with the etch stop pattern  127 P. 
       FIGS. 6A to 6D  show sectional views illustrating a process of opening a channel region and a process of forming a memory layer and a channel layer in the channel region. 
     Referring to  FIG. 6A , a portion of the third stack structure PST 3  may be penetrated by a select line separating structure DS. The select line separating structure DS is formed to separate drain select lines, and the depth to which the select line separating structure DS is formed may be variously changed depending on designs. The select line separating structure DS may be omitted, for some embodiments. 
     Subsequently, holes H are formed, which penetrate the first regions P 1  of the first to third stack structures PST 1  to PST 3  and the protective layer  115 . The second lower sacrificial layer  113  may be exposed through bottom surfaces of the holes H. The first material layers  121   a ,  121   b , and  121   c  and the second material layers  123   a ,  123   b , and  123   c , which are described with reference to  FIGS. 5A to 5D , are etched so as to form the holes H. When the second lower sacrificial layer  113  includes a metal, the width of the bottom surface of each of the holes H can be widely ensured using a different in etch rate between the second lower sacrificial layer  113  and the first material layers  121   a ,  121   b , and  121   c  and the second material layers  123   a ,  123   b , and  123   c.    
     Referring to  FIG. 6D , the second lower sacrificial layer  113  shown in  FIG. 6A  is selectively removed through the holes H. Accordingly, the first lower sacrificial layer  111  and the protective layer  115  are exposed. 
     Referring to  FIG. 6C , the first lower sacrificial layer  111  shown in  FIG. 6B  is selectively removed through the holes H. Accordingly, a horizontal space HSP connected to the holes H is opened. The horizontal space HSP and the holes H are connected to each other to define a channel region CA. While the first lower sacrificial layer  111  is being removed, the first material layer  121   a  disposed in the lowermost layer may be protected without being lost by the protective layer  115 . Gap of the horizontal space HSP may be maintained by the supports IP. A sidewall of each of the supports IP may be exposed by the horizontal space HSP. 
     Referring to  FIG. 6D , a memory layer ML is formed on a surface of the channel region CA shown in  FIG. 6C . The process of forming the memory layer ML may include a process of forming a first blocking insulating layer  131 , a process of forming a data storage layer  133  on the first blocking insulating layer  131 , and a process of forming a tunnel insulating layer  135  on the data storage layer  133 . A material of each of the first blocking insulating layer  131 , the data storage layer  133 , and a tunnel insulating layer  135  is the same as described with reference to  FIG. 2A . Each of the first blocking insulating layer  131 , the data storage layer  133 , and a tunnel insulating layer  135  is conformally formed along the surface of the channel region CA. 
     Subsequently, a channel layer  137  is formed on a surface of the memory layer ML. The channel layer  137  is conformally formed along the surface of the channel region CA shown in  FIG. 6C . The channel layer  137  may be formed of a semiconductor layer. For example, the channel layer  137  may be formed by depositing a silicon layer. The channel layer  137  may be formed as an integrated layer without any interface. 
     After this, a central portion of the channel region CA, which is opened without being filled with the channel layer  137 , is filled with an insulating layer  139 . The insulating layer  139  is formed on the channel layer  137 . The process of forming the insulating layer  139  may include a process of filling the channel region CA of  FIG. 6C  with a material layer having liquidity and a process of curing the material layer having liquidity. Polysilazane (PSZ) may be used as the material having liquidity. 
     A process of recessing a portion of the insulating layer  139  may be further performed such that the height of the insulating layer  139  is lower than that of the channel layer  137 . A central region of the channel layer  137  exposed on the insulating layer  139  may be filled with a doped semiconductor layer  141 . The doped semiconductor layer  141  may be formed of a doped silicon layer including a drain dopant of the same conductivity type as a source dopant. For example, the doped semiconductor layer  141  may include an n-type dopant. 
       FIGS. 7A to 7G  show sectional views illustrating a process of forming a slit and a process of forming gate stack structures. 
     Referring to  FIG. 7A , an upper insulating layer  143  is formed on the third stack structure PST 3 . The upper insulating layer  143  may be formed of an oxide layer, and serve as a mask. 
     Subsequently, the second region P 2  of the third stack structure PST 3  is etched from the upper insulating layer  143 , using a photolithography process. Accordingly, a first slit SI 1  penetrating the third stack structure PST 3  is formed. The etch stop pattern  127 P has an etching resistance with respect to an etching material for etching the third stack structure PST 3 . Accordingly, since it is difficult to remove the etch stop pattern  127 P during the etching process for forming the first slit SI 1 , the depth of the first slit SI 1  can be easily controlled such that the first slit SI 1  completely penetrates the third stack structure PST 3  and does not penetrate the etch stop pattern  127 P. The first slit SI 1  may extend to the inside of the etch stop pattern  127 P. However, the etch stop pattern  127 P defines a bottom surface of the first slit SI 1 , and may remain. 
     Referring to  FIG. 7B , mask patterns  145  are formed on sidewalls of the first slit SI 1 , which face each other. The mask patterns  145  may be formed of the same material as the first material layer  121   a  of the first stack structure PST 1 . The process of forming the mask patterns  145  may include a process of conformally forming a mask layer along a surface of the first slit SI 1  and a process of opening the bottom surface of the first slit SI 1  by etching the mask layer through an etch-back process. 
     Subsequently, the uppermost layer  123   a  of the first stack structure PST 1  is exposed by etching a portion of the etch stop pattern exposed between the mask patterns  145 , and a second slit SI 2  connected to the first slit SI 1  is formed. The etch stop pattern may be separated into first and second side patterns  127 P 1  and  127 P 2  by being penetrated by the second slit SI 2 . 
     Referring to  FIG. 7C , the lowermost layer  121   a  of the first stack structure PST 1  is exposed by etching the first stack structure PST 1  exposed between the mask patterns  145 , and a third slit SI 3  connected to the second slit SI 2  is formed. A bottom surface of the third slit SI 3  is defined by the first material layer  121   a  disposed in the lowermost layer of the first stack structure PST 1 . 
     The second material layer  123   a  of the first stack structure PST 1 , which is blocked by the mask patterns  145  and the first and second side patterns  127 P 1  and  127 P 2 , may remain to protrude farther toward the third slit SI 3  than the sidewall of the second stack structure PST 2 . 
     The first to third slits SI 1  to SI 3  formed by the processes described with reference to  FIGS. 7A to 7C  are connected to each other to constitute a slit. Hereinafter, the structure in which the first to third slits SI 1  to SI 3  are connected to each other is referred to as a slit SI. 
     Referring to  FIG. 7D , the first and second side patterns  127 P 1  and  127 P 2  shown in  FIG. 7C  are selectively removed. Accordingly, the sidewall of the second stack structure PST 2  is exposed, and an undercut region UC is defined between the third stack structure PST 3  and the first stack structure PST 1 . 
     Referring to  FIG. 7E , the first material layers  121   a  to  121   c  of the first to third stack structures PST 1  to PST 3  shown in  FIG. 7D  are removed. Openings OP are defined in regions in which the first material layers  121   a  to  121   c  of the first to third stack structures PST 1  to PST 3  are removed. Since the mask patterns  143  shown in  FIG. 7D  are formed of the same material as the first material layers  121   a  to  121   c , the mask patterns  143  may be removed together with the first material layers  121   a  to  121   c . When the first material layer  121   a  disposed in the lowermost layer of the first stack structure PST 1  shown in  FIG. 7D  is removed, the protective layer  115  may be exposed. The protective layer  115  protects the memory layer ML disposed on the bottom thereof from the etching process. 
     The second material layer  123   a  disposed in the lowermost layer among the second material layers  123   a ,  123   b , and  123   c  may protrude farther toward the slit SI than the second material layers  123   b  and  123   c  disposed above thereof. 
     Referring to  FIG. 7F , a conductive layer  153  is filled in the opening regions OP shown in  FIG. 7E . Before the conductive layer  153  is formed, a second blocking insulating layer  151  may be further formed conformally along surfaces of the opening regions OP and the slit SI. The second blocking insulating layer  151  may be formed of a high dielectric insulating layer. For example, the second blocking insulating layer  151  may include an aluminum oxide layer. The aluminum oxide layer may be deposited in an amorphous state and then crystallized through a heat treatment process. The n-type dopant in the doped semiconductor layer  141  shown in  FIG. 7E  is diffused into an upper end of the channel layer  137  in contact with the doped semiconductor layer  141  through the heat treatment process of crystallizing the second blocking insulating layer  151 . As a result, a doping region is formed in the channel layer  137 . Accordingly, a capping pattern CAP including the doped semiconductor layer  141  and the doping region of the channel layer  137  is defined. The capping pattern CAP may be used as a drain junction. 
     The conductive layer  153  may be formed of a low-resistance metal such as tungsten so as to achieve low-resistance wiring. The low-resistance metal for the conductive layer  153  is not limited to tungsten, and may be formed of various low-resistance metals. 
     Referring to  FIG. 7G , the conductive layer  153  shown in  FIG. 7F  is etched through the slit SI such that the first to third conductive patterns CP 1  to CP 3  can be formed. The first to third conductive patterns CP 1  to CP 3  are patterned not to protrude farther toward the slit SI than the second material layers  123   a  to  123   c  used as first to third interlayer insulating layers. A slit extension part SIE may be connected to the slit SI under the slit SI through an etching process of the conductive layer. The slit extension part SIE completely penetrates the conductive layer, and exposes the second blocking insulating layer  151  on the protective layer  115 . 
     According to the processes described in  FIGS. 7D to 7G , sacrificial layers (i.e., the first material layers) of the first to third stack structures are replaced with conductive patterns. Accordingly, gate stack structures GST 1  and GST 2  may be formed, in which conductive patterns and interlayer insulating layers are alternately stacked. Each of the gate stack structures GST 1  and GST 2  may have a groove GV. The groove GV may be defined by the undercut region UC shown in  FIG. 7D . The shape of a sidewall of each of the gate stack structures GST 1  and GST 2  having the grooves GV may include protrusions and recesses as described with reference to  FIG. 4 . 
       FIG. 8A to 8E  show sectional views illustrating a process of forming spacer insulating patterns, a process of a well contact structure, and a process of forming an inter-well-source insulating layer. 
     Referring to  FIG. 8A , spacer insulating patterns  161  are formed on sidewalls of the slit SI. The spacer insulating patterns  161  may be formed on sidewalls of the gate stack structures GST 1  and GST 2  to cover the first to third conductive patterns shown in  FIG. 7G . The process of forming the spacer insulating patterns  161  may include a process of depositing an oxide layer and a process of etching the oxide layer through an etch-back process. The groove GV defined on the sidewall of each of the gate stack structures GST 1  and GST 2  is not completely filled with the spacer insulating patterns  161 , and a central region of the groove GV may be opened. 
     Subsequently, the second blocking insulating layer  151 , the protective layer  115 , the memory layer ML, and the channel layer  137 , which are exposed between the spacer insulating patterns  161 , are sequentially etched. Accordingly, a first trench T 1  is formed, which is connected to the slit SI and extends to the inside of the insulating layer  139 . 
     Referring to  FIG. 8B , sidewall protective patterns  163  are formed, which extend toward sidewalls of the first trench T 1  from the spacer insulating patterns  161 . The sidewall protective patterns  163  may be formed of a material layer having an etch rate different from that of the oxide layer. For example, the sidewall protective patterns  163  may be formed of a nitride layer. The process of forming the sidewall protective patterns  163  may include a process of depositing a nitride layer and a process of etching the nitride layer through an etch-back process such that a bottom surface of the first trench T 1  can be exposed. 
     Subsequently, a second trench T 2  exposing the well structure WE is formed by etching the insulating layer, the channel layer, the memory layer, and the buffer layer  105 , which are exposed between the sidewall protective patterns  163 . 
     By the first trench T 1  and the second trench T 2 , which are connected to the slit SI, the channel layer may be separated into channel patterns  137 A and  137 B, the memory layer may be separated into memory patterns ML 1  and ML 2 , and the insulating layer may be separated into insulating patterns  139 A and  139 B. The second trench T 2  may extend to the inside of the well structure WE. 
     Referring to  FIG. 8C , a semiconductor layer  171  filling in the second trench T 2  shown in  FIG. 8B  is formed. The semiconductor layer  171  is in contact with an end portion of each of the channel patterns  137 A and  137 B, which are exposed by the second trench T 2  shown in  FIG. 8B , and the well structure WE. The semiconductor layer  171  may include a silicon layer. 
     The semiconductor layer  171  may be formed using a selective growth process. The semiconductor layer  171  may be grown from the well structure WE exposed through the second trench T 2  shown in  FIG. 8B  and the end portion of each of the channel patterns  137 A and  137 B. Alternatively, the semiconductor layer  171  may be formed using a deposition process such as a chemical vapor deposition process. According to the present disclosure, although the deposition process is used, the second trench T 2  shown in  FIG. 8B  can be easily filled with the semiconductor layer  171  through the groove GV defined by the undercut region UC described with reference to  FIG. 7D . That is, the semiconductor layer  171  formed using the deposition process can be easily deposited in the second trench T 2  through the groove GV defined by the undercut region UC. In addition, the groove GV defined by the undercut region UC can prevent a phenomenon in which a central region of an upper end of the slit SI, which is disposed above the groove GV, is completely filled with the semiconductor layer  171  before the second trench T 2  is completely filled with the semiconductor layer  171 . According to the present disclosure, the central region of the upper end of the slit SI, which is disposed above the groove GV, is not filled with the semiconductor layer  171  but opened. According to the present disclosure, although a deposition process that can reduce cost as compared with the selective growth process is introduced, the semiconductor layer  171  can be stably formed in a desired region, so that the manufacturing cost of the semiconductor device  100  can be reduced. 
     Referring to  FIG. 8D , the semiconductor layer opened through the slit SI is etched such that a well contact structure  171 P is patterned. The well contact structure  171 P remains with a height at which the well structure WE and the channel patterns  137 A and  137 B can be connected. The well dopant in the well structure WE may be diffused into the well contact structure  171 P. 
     Subsequently, an inter-well-source insulating layer  179  may be formed by oxidizing an upper portion of the well contact structure  171 P through the first trench T 1 . A portion of each of the channel patterns  137 A and  137 B, which is to be used as a source contact surface in a subsequent process, is not oxidized but may be protected by the sidewall protective patterns  163 . 
     Referring to  FIG. 8E , the sidewall protective patterns  163  shown in  FIG. 8D  are removed. Accordingly, a source contact surface SU 1  of each of the channel patterns  137 A and  137 B and the spacer insulating patterns  161  are exposed. 
       FIGS. 9A and 9B  show sectional views illustrating a process of forming a source contact structure. 
     Referring to  FIG. 9A , a doped semiconductor layer  181  is formed on the inter-well-source insulating layer  179 . The doped semiconductor layer  181  may be a doped silicon layer including a source dopant. The source dopant is an n-type dopant. The doped semiconductor layer  181  may be in contact with the source contact surface of each of the channel patterns  137 A and  137 B, and extend onto the spacer insulating patterns  161 . 
     Referring to  FIG. 9B , the doped semiconductor layer may be recessed such that a portion of the slit SI shown in  FIG. 8E  is opened. After this, a partial thickness of the doped semiconductor layer is silicided through a siliciding process to be changed into a metal silicide layer  183 . The portion that is not changed into the metal silicide layer  183  remains as a doped semiconductor pattern  181 P. Since the metal silicide layer  183  has a resistance lower than that of the doped semiconductor pattern  181 P, the metal silicide layer  183  can lower the resistance of a source contact structure SCL. 
     The siliciding process may include a process of depositing a metal layer and an annealing process of inducing a reaction between the metal layer and the doped semiconductor layer. The source dopant in the doped semiconductor layer may be diffused into the channel patterns  137 A and  137 B from the source contact surface SU 1  of  FIG. 9A  of each of the channel patterns  137 A and  137 B, using the annealing process performed while the siliciding process is being performed. Accordingly, a junction JN may be formed in each of the channel patterns  137 A and  137 B. 
     Various metal layers such as nickel and tungsten may be used as the metal layer for the siliciding process. The metal silicide layer  183  formed through the siliciding process may be nickel silicide, tungsten silicide, etc. 
     Subsequently, a metal barrier layer  185  is formed on surfaces of the spacer insulating patterns  161  and the metal silicide layer  183 . After this, a process of forming a metal layer  187  on the metal barrier layer  185  may be further performed such that the slit is completely filled with the metal layer  187 . The metal layer  187  may include a low-resistance metal layer such as tungsten so as to achieve a low resistance of the source contact structure SCL. The metal barrier layer  185  may include a titanium nitride layer, a tungsten nitride layer, a tantalum nitride layer, and the like so as to prevent diffusion of metal from the metal layer  187 . 
     Subsequently, subsequent processes for forming the second upper insulating layer UI 2  shown in  FIG. 1  and the bit line contact plug BCT and the bit line BL, which are shown in  FIG. 2A , may be performed. 
       FIGS. 10A, 10B, 11A, 11B, 12A, 12B, 13A, 13B, 14A, 14B, and 15A to 15C  show views illustrating a manufacturing method of a semiconductor device  100  according to a second embodiment of the present disclosure.  FIGS. 10A, 10B, 11A, 11B, 12A, 12B, 13A, 13B, 14A, 14B, and 15A to 15C  show a modification of the manufacturing process sectional views of the semiconductor device  100  taken along line Y-Y′ shown in  FIG. 3 .  FIGS. 11B, 12B, and 14B  illustrate plan views taken in the horizontal direction along lines B-B′ shown in  FIGS. 11A, 12A, and 14A . 
     Hereinafter, descriptions of repeated manufacturing processes of the present disclosure are omitted, and only modified manufacturing processes is described in detail. 
     In order to form a structure shown in  FIG. 10A , the processes described in  FIGS. 5A to 5D, 6A to 6D, 7A to 7G, 8A and 8B  may be identically performed. 
     Referring to  FIG. 8B , the insulating patterns  139 A and  139 B are exposed by the second trench T 2 . Subsequently, portions of the insulating patterns  139 A and  139 B exposed by the second trench T 2  shown in  FIG. 8B  are etched. Accordingly, as shown in  FIG. 10A , the horizontal space HSP between the gate stack structures GST 1  and GST 2  and the well structure WE is opened, and an inner wall of each of the channel patterns  137 A and  137 B, which faces the horizontal space HSP, is exposed. The insulating patterns surrounded by pillar parts PP of the channel patterns  137 A and  137 B penetrating the gate stack structures GST 1  and GST 2  may remain as vertical insulating patterns  139 AP and  139 BP. A bottom surface of the vertical insulating patterns  139 AP and  139 BP faces the horizontal space HSP. 
     Referring to  FIG. 10A , the tunnel insulating layer  131  and the first blocking insulating layer  135  of each of the memory patterns ML 1  and ML 2  and the buffer layer  105  may be etched while the portions of the insulating patterns are being removed. The tunnel insulating layer  131 , the first blocking insulating layer  135 , and the buffer layer  105  may be etched slower than the insulating patterns. Accordingly, gaps  270  may be defined between the channel patterns  137 A and  137 B and the data storage layers  133  and between the well structure WE and the data storage layers  133 . 
     After this, a first semiconductor layer  271  is formed to fill in the gaps  270 . The first semiconductor layer  271  is in contact with the end portion of each of the channel patterns  137 A and  137 B and the well structure WE, and extends onto the inner wall of each of the channel patterns  137 A and  137 B. The first semiconductor layer  271  may include a silicon layer. 
     The first semiconductor layer  271  may be formed using a deposition process such as a chemical vapor deposition process. A lower end portion of the slit SI may be blocked by the first semiconductor layer  271  in a state in which the central region of the horizontal space HSP and the central region of the slit SI are not completely filled with the first semiconductor layer  271 . A lower end portion of the second trench T 2  of  FIG. 8B , which extends to the inside of the well structure WE, may be completely filled with the first semiconductor layer  271 . 
     Referring to  FIG. 10B , the first semiconductor layer  271  shown in  FIG. 10A  is etched such that a first semiconductor pattern  271 P opened toward the slit SI is disposed in the horizontal space HSP. The first semiconductor pattern  271 P remains in a state in which it is in contact with the well structure WE and the channel patterns  137 A and  137 B. 
     The first semiconductor pattern  271 P extends onto bottom surfaces of the vertical insulating patterns  139 AP and  139 BP and the inner walls of the channel patterns  137 A and  137 B, which face the central region of the horizontal space HSP. 
     The first semiconductor pattern  271 P may include a well contact structure WCL and first and second auxiliary contact structures AC 1  and AC 2 . The well contact structure WCL is a structure filling in the lower end portion of the second trench T 2  shown in  FIG. 8B  as a portion of the first semiconductor pattern  271 P. The first and second auxiliary contact structures AC 1  and AC 2  are structures filling in the gaps  270  shown in  FIG. 10A  as portions of the first semiconductor pattern  271 P. The first and second auxiliary contact structures AC 1  and AC 2  protrude in parallel to each other in the second direction II shown in  FIG. 1  from a side portion of the well contact structure WCL. The data storage layer  133  of each of the memory patterns ML 1  and ML 2  has a protrusion part extending between the first and second auxiliary contact structures AC 1  and AC 2 . 
     The first auxiliary contact structure AC 1  extends between each of the channel patterns  137 A and  137 B and the data storage layer  133 , and the second auxiliary contact structure AC 2  extends between the well structure WE and the data storage layer  133 . 
     Referring to  FIG. 11A , a first lower insulating layer  273  is formed on the first semiconductor pattern  271 P along the surface shape of the first semiconductor pattern  271 P. The first lower insulating layer  273  may be formed of an oxide layer. The first lower insulating layer  273  may extend onto the sidewall protective patterns  163 . The first lower insulating layer  273  is not completely filled in the horizontal space HSP and the slit SI, and an air gap may be formed in the central region of each of the horizontal space HSP and the slit SI. 
       FIG. 11B  illustrates a plan view taken in the horizontal direction along line B-B′ shown in  FIG. 11A . 
     Referring to  FIG. 11B , each of the sidewalls of the supports IP is surrounded by the first lower insulating layer  273 . One of the memory patterns ML 1  and ML 2 , one of the channel patterns  137 A and  137 B, and the first semiconductor pattern  271 P 1  are disposed between each of the supports IP and the first lower insulating layer  273 . 
     The supports IP may be divided into a plurality of support groups GIP 1  and GIP 2  by using the slit SI shown in  FIG. 11A  as a boundary. Each of the support groups GIP 1  and GIP 2  is surrounded by the first lower insulating layer  273  corresponding thereto. The first lower insulating layer  273  surrounding each of the support groups GIP 1  and GIP 2  fills between supports IP adjacent to each other, and may fix the first semiconductor pattern  271 P such that the first semiconductor pattern  271 P does not move between the supports IP. A first air gap AG 1  may be formed between the supports IP constituting each of the support groups GIP 1  and GIP 2 . 
     Referring to  FIG. 12A , a portion of the first lower insulating layer is etched through the slit SI. Accordingly, the first lower insulating layers between the supports IP adjacent to each other remain as first lower patterns  273 P. In addition, a portion of the first semiconductor pattern  271 P adjacent to the slit SI is exposed. 
       FIG. 12B  illustrates a plan view taken in the horizontal direction along line B-B′ shown in  FIG. 12A . 
     Referring to  FIG. 12B , the supports included in each of the support groups GIP 1  and GIP 2  may be divided into slit-side supports IP_S and the other center supports IP_C. The slit-side supports IP_S are supports adjacent to the slit SI shown in  FIG. 12A . 
     A portion of the first semiconductor pattern  271 P surrounding each of the slit-side supports IP_S may be exposed through the process described with reference to  FIG. 12A . The first lower pattern  273 P may remain on a sidewall of the first semiconductor pattern  271 P, which faces each of the center supports IP_C. 
     Referring to  FIG. 13A , after a second semiconductor layer is formed on the exposed partial surface of the first semiconductor pattern  271 P. And then a third trench T 3  is formed, which exposes the well contact structure WCL of the first semiconductor pattern  271 P. The third trench T 3  is formed through an etching process of the second semiconductor layer, and the second semiconductor layer may be separated into second semiconductor patterns  275 A and  275 B by the third trench T 3 . Each of the second semiconductor patterns  275 A and  275 B has an opening  276  facing the third trench T 3 . 
     The second semiconductor layer may include a silicon layer. The thickness of the second semiconductor patterns  275 A and  275 B may be controlled such that the second semiconductor patterns  275 A and  275 B are not completely filled in the central region of the horizontal space HSP. 
     Referring to  FIG. 13B , a second lower insulating layer  277  is formed on surfaces of the second semiconductor patterns  275 A and  275 B through the slit SI. The second lower insulating layer  277  may fill in a space between the second semiconductor patterns  275 A and  275 B. The second lower insulating layer  277  may extend along the sidewall of the first semiconductor pattern  271 P, which is adjacent to the slit SI. The second lower insulating layer  277  may be formed of an oxide layer. 
     Referring to  FIG. 14A , the second lower insulating layer  277  shown in  FIG. 13B  is etched such that the well contact structure WCL of the first semiconductor pattern  271 P is exposed. Accordingly, a separating trench T 4  penetrating the second lower insulating layer is formed, and the second lower insulating layer is separated into second lower patterns  277 P by the separating trench T 4 . 
     The second lower patterns  277 P may respectively block the openings of the second semiconductor patterns  275 A and  275 B shown in  FIG. 13A . Accordingly, a second air gap AG 2  is defined in each of the second lower patterns  277 P, and the second air gap AG 2  may be sealed in the horizontal space. 
       FIG. 14B  illustrates a plan view taken in the horizontal direction along line B-B′ shown in  FIG. 14A . 
     Referring to  FIG. 14B , the second air gap AG 2  is defined in each of the second lower patterns  277 P opposite to each other with the separating trench T 4  interposed therebetween. Each of the second lower patterns  277 P extends onto a sidewall of a second semiconductor pattern corresponding thereto among the second semiconductor patterns  275 A and  275 B. The second semiconductor patterns  275 A and  275 B extend along the appearance of the sidewalls of the first semiconductor patterns  271 P disposed on the slit-side supports IP_S facing the separating trench T 4 . 
     After the first semiconductor pattern  271 P, the second semiconductor patterns  275 A and  275 B, and the first and second lower patterns  273 P and  277 P are formed using the processes described with reference to  FIGS. 10A, 10B, 11A, 12A, 13A, 13B, and 14A , a process of forming an inter-well-source insulating layer may be continuously performed. 
     Referring to  FIG. 15A , an inter-well-source insulating layer  279  may be formed by oxidizing a portion of each of the first semiconductor pattern  271 P and the second semiconductor patterns  275 A and  275 B. A partial thickness of each of the first semiconductor pattern  271 P and the second semiconductor patterns  275 A and  275 B is oxidized from a surface of each of the first semiconductor pattern  271 P and the second semiconductor patterns  275 A and  275 B, which is exposed by the separating trench T 4  shown in  FIG. 14A . The inter-well-source insulating layer  279  formed through the above-described process is aligned on the well contact structure WCL of the first semiconductor pattern  271 P exposed between the second lower patterns  277 P. 
     Referring to  FIG. 15B , the sidewall protective patterns  163  shown in  FIG. 15A  are removed. Accordingly, a source contact surface SU 2  of each of the channel patterns  137 A and  137 B and the first semiconductor pattern  271 P and the spacer insulating patterns  161  are exposed. 
     A doped semiconductor layer  281  is formed on the inter-well-source insulating layer  279 . The doped semiconductor layer  281  may be a doped silicon layer including a source dopant. The source dopant is an n-type dopant. The doped semiconductor layer  281  is in contact with the source contact surface SU 2  of each of the channel patterns  137 A and  137 B and the first semiconductor pattern  271 P, and fills in a space between the spacer insulating patterns  161 . 
     Referring to  FIG. 15C , a doped semiconductor pattern  281 P, a metal silicide layer  283 , a metal barrier layer  285 , and a metal layer  287  may be formed by performing the same processes as described in  FIG. 9B . Accordingly, a source contact structure SCL is formed. 
     The source dopant in the doped semiconductor layer may be diffused into the channel patterns  137 A and  137 B, the first semiconductor pattern  271 P, and the second semiconductor patterns  275 A and  275 B from the source contact surface SU 2  of each of the channel patterns  137 A and  137 B and the first semiconductor pattern  271 P, which are shown in  FIG. 15B , during an annealing process for forming the metal silicide layer  283  as described in  FIG. 9B . 
     Accordingly, a junction JN may be formed in each of the channel patterns  137 A and  137 B, the first semiconductor pattern  271 P, and the second semiconductor patterns  275 A and  275 B. 
     Subsequently, subsequent processes for forming the second upper insulating layer UI 2  shown in  FIG. 1  and the bit line contact plug BCT and the bit line BL, which are shown in  FIG. 2A , may be performed. 
       FIG. 16  shows a sectional view illustrating a semiconductor device  1600  according to a second embodiment of the present disclosure.  FIG. 16  shows a modification of a section of the semiconductor device  1600 , which is taken along the line X-X′ shown in  FIG. 3 . 
     Hereinafter, characteristic components of the semiconductor device  1600  are described with reference to  FIGS. 15C and 16 , and descriptions of components redundant with those of the semiconductor device  100  are omitted. 
     Referring to  FIGS. 15C and 16 , the semiconductor device  1600  according to the present disclosure may include the first semiconductor pattern  271 P disposed on the surface of each of the channel patterns  137 A and  137 B in the horizontal space HSP. The first semiconductor pattern  271 P may include the well contact structure WCL and the first and second auxiliary contact structures AC 1  and AC 2  as described with reference to  FIG. 10B . The first semiconductor pattern  271 P may be conformally formed along the surface of the horizontal space HSP to open a central region of the horizontal space HSP. The first semiconductor pattern  271 P may extend to be in direct contact with the sidewall of the doped semiconductor pattern  281 P. 
     The well contact structure WCL of the first semiconductor pattern  271 P is aligned under the doped semiconductor pattern  281 P. The first auxiliary contact structures AC 1  protrude between memory patterns ML 1  and ML 2  and the channel patterns  137 A and  137 B from the well contact structure WCL. The second auxiliary contact structures AC 2  protrude between the memory patterns ML 1  and ML 2  and the well structure WE. Accordingly, the first semiconductor pattern  271 P according to the present disclosure can increase the contact area between the channel patterns  137 A and  137 B and the well structure WE. 
     The lower insulating patterns  273 P and  277 P may be formed on the surface of the first semiconductor pattern  271 P. The first air gap AG 1  may be formed in the first lower pattern  273 P among the lower insulating patterns  237 P and  277 P. The second air gap AG 2  may be formed in the second lower pattern  277 P among the lower insulating patterns  237 P and  277 P. The second lower pattern  277 P is disposed between the first lower pattern  273 P and the doped semiconductor pattern  281 P. By the second lower pattern  277 P, the well contact structure WCL of the first semiconductor pattern  271 P may be separated from an upper end portion of the first semiconductor pattern  271 P, which is in contact with the doped semiconductor pattern  281 P. 
     A corresponding second semiconductor pattern among the second semiconductor patterns  275 A and  275 B may be formed on an outer wall of the second lower pattern  277 P. Each of the second semiconductor patterns  275 A and  275 B extends between the first semiconductor pattern  271 P and a second lower pattern  277 P corresponding thereto. Each of the second semiconductor patterns  275 A and  275 B extends between a second lower pattern  277 P corresponding thereto and the first lower pattern  273 P facing the second lower pattern  277 P. 
     The inter-well-source insulating layer  279  may have a U-shaped sectional structure surrounding a lower end of the doped semiconductor pattern  281 P. 
     According to the present disclosure, memory cells are formed along the extending direction of a channel pattern penetrating stack structures, so that the degree of integration of the memory cells can be improved. 
     According to the present disclosure, the loss of cell current flowing through the channel pattern is prevented, so that the operational reliability of the semiconductor device  1600  can be enhanced. 
     According to the present disclosure, the stability of a process of forming a slit by using an etch stop pattern can be enhanced. 
       FIG. 17  shows a block diagram illustrating a configuration of a memory system according to an embodiment of the present disclosure. 
     Referring to  FIG. 17 , the memory system  1100  according to the embodiment of the present disclosure includes a memory device  1120  and a memory controller  1110 . 
     The memory device  1120  may include at least one of the structures shown in  FIGS. 1, 2A, 3, 4, 9B, 15C, and 16 . For example, the memory device  1120  may include: a well structure including a well dopant; a gate stack structure disposed over the well structure, the gate stack structure having a groove formed in a sidewall thereof; and a channel pattern penetrating the gate stack structure, the channel pattern extending along a surface of a horizontal space between the well structure and the gate stack structure. The memory device  1120  may be a multi-chip package configured with a plurality of flash memory chips. 
     The memory controller  1110  is configured to control the memory device  1120 , and may include a static random access memory (SRAM)  1111 , a CPU  1112 , a host interface  1113 , an error correction code (ECC)  1114 , and a memory interface  1115 . The SRAM  1111  is used as an operation memory of the CPU  1112 , the CPU  1112  performs overall control operations for data exchange of the memory controller  1110 , and the host interface  1113  includes a data exchange protocol for a host connected with the memory system  1100 . The ECC  1114  detects and corrects an error included in a data read from the memory device  1120 , and the memory interface  1115  interfaces with the memory device  1120 . In addition, the memory controller  1110  may further include an ROM for storing code data for interfacing with the host, and the like. 
     The memory system  1100  configured as described above may be a memory card or a Solid State Disk (SSD), in which the memory device  1120  is combined with the controller  1110 . For example, when the memory system  1100  is an SSD, the memory controller  1100  may communicated with the outside (e.g., the host) through one among various interface protocols, such as a Universal Serial Bus (USB) protocol, a Multi-Media Card (MMC) protocol, a Peripheral Component Interconnection (PCI) protocol, a PCI-Express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a Serial-ATA (SATA) protocol, a Parallel-ATA (PATA) protocol, a Small Computer Small Interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, and an Integrated Drive Electronics (IDE) protocol. 
       FIG. 18  shows a block diagram illustrating a configuration of a computing system according to an embodiment of the present disclosure. 
     Referring to  FIG. 18 , the computing system  1200  according to the embodiment of the present disclosure may include a CPU  1220 , a random access memory (RAM)  1230 , a user interface  1240 , a modem  1250 , and a memory system  1210 , which are electrically connected to a system bus  1260 . When the computing system  1200  is a mobile device, a battery for supplying an operation voltage to the computing system  1200  may be further included, and an application chip set, a Camera Image Processor (CIS), a mobile D-RAM, and the like may be further included. 
     The memory system  1210  may include a memory device  1212  and a memory controller  1211 . The memory device  1212  and the memory controller  1211  may be configured identically to those described with reference to  FIG. 17 . 
     Example embodiments have been disclosed herein, and although specific terms are employed, the terms are used and are to be interpreted in a generic and descriptive sense only and not for purpose of limitation. In some instances, as would be apparent to one of ordinary skill in the art as of the filing of the present application, features, characteristics, and/or elements described in connection with a particular embodiment may be used singly or in combination with additional features, characteristics, and/or elements described in connection with other embodiments unless otherwise specifically indicated. Accordingly, it will be understood by those of skill in the art that various changes in form and detail may be made without departing from the spirit and scope of the present disclosure as set forth in the following claims.