Patent Publication Number: US-6214696-B1

Title: Method of fabricating deep-shallow trench isolation

Description:
This is a continuation-in-part of an application filed on Apr. 22, 1998, Ser. No. 09,064,976, U.S. Pat. No. 6,137,152. 
    
    
     FIELD OF THE INVENTION 
     The present invention relates to a semiconductor manufacturing process, and more specifically to a process to fabricate a trench isolation. 
     BACKGROUND OF THE INVENTION 
     In integrated circuits, a great number of devices and circuits are fabricated on a single chip. Various kinds of devices like transistors, resistors, and capacitors are formed together. Each device must operate independently without interfering each other, especially under the higher and higher packing density of the integrated circuits. An isolation region is formed on the semiconductor substrate for separating different devices or different functional regions. The isolation region is generally a non-active and insulated region for isolating between devices, wells, and functional regions. 
     LOCOS (local oxidation of silicon) is a widely applied technology used in forming the isolation region. The isolation regions are created by oxidizing the portion of the silicon substrate between each active device and functional regions. The LOCOS technology provides the isolation region with a simple manufacturing process and low cost, especially when compared with other trench isolation processes. However, with the fabrication of semiconductor integrated circuits becoming densely packed, the application of the LOCOS technology is quite limited. For a highly packed circuits like the circuits with devices of deep submicrometer feature sizes, the LOCOS process has several challenges in fulfilling the isolating and packing density specifications. 
     The trench isolation process, or the shallow trench isolation (STI) process, is another isolation process proposed especially for semiconductor chips having high packing density. A trench region is formed in the semiconductor with a depth deep enough for isolating the devices or different wells. In general, a trench is etched and refilled with insulating materials by the trench isolation formation process. The refilled trench regions are employed for the application in the VLSI and ULSI level. In addition, capacitors can also be formed within the trench by filling both insulating and conductive materials sequentially for the application of forming memory cells. 
     Shallow trench isolation has emerged as the solution for deep sub-micron transistor isolation due to its scalability, planar topography and potentially low thermal budget. In U.S. Pat. No. 5,443,794 to Fazan et al., a method for using spacers to form isolation trenches with improved corners is proposed. They mentioned that the limits of the standard LOCOS process have motivated the search for and the development of new isolation schemes. Trench isolation is a promising candidate as it uses a fully recessed oxide, has no bird&#39;s beak, is fully planar, and does not suffer from the field oxide thinning effect. A smooth trench profile with a self-aligned cap or dome is created in their invention. 
     For providing better insulating characteristics, a deep trench isolation scheme has been reported. The deep trench isolation increases the packing density and improve the latch-up immunity in CMOS (complementary metal oxide semiconductor)/bipolar devices. R. Bashir and F. Hebert disclosed a planarized trench isolation and field oxide formation using poly-silicon (PLATOP) in their work: “PLATOP: A Novel Planarized Trench Isolation and Field Oxide Formation Using Poly-Silicon” (IEEE Electron Device Letters, vol. 17, no. 7, 1996). It is disclosed that a process highly applicable to high density and high performance CMOS/bipolar processes is needed. The process should not suffer from the conventional limitations of LOCOS-based isolation. The deep trench isolation is finding abundant use in semiconductor processes to increase packing density and latch-up immunity. The difficulties reported include lateral encroachment by bird&#39;s beak, formation of thick oxide, combination of deep trench and field isolation, and area and loading effects of planarization process. 
     In U.S. Pat. No. 5,474,953 to Shimizu et al., a method is reported for forming an isolation region comprising a trench isolation region and a selective oxidation film involved in a semiconductor device. A semiconductor device including both emitter coupled logic circuits (ECL circuits) involving super high speed performance bipolar transistors and super high integrated CMOS circuits with a low power consumption has been developed and known in the art. Both the CMOS and the bipolar devices are formed on a single chip. Thus, isolation structures fulfilling the needs of the various devices and circuits is highly demanded for providing designed functionality of the circuits. 
     SUMMARY OF THE INVENTION 
     The method includes forming a pad oxide on a substrate. A polysilicon layer is then formed over the pad layer. Next, an oxide layer is formed over the polysilicon layer. An opening is formed in the oxide and the polysilicon layers, and the pad layer. A portion of the substrate is then etched by using the oxide layer as a mask. A sidewall structure is then formed on the opening. Next, a portion of the substrate is also etched for forming a deeper trench by using the sidewall structure as a mask. The sidewall structure and the oxide layer are then removed. Then, an oxide and an oxynitride layer are formed on aforesaid feature. A semiconductor layer is then formed over the oxynitride layer. A portion of the semiconductor layer is oxidized for forming an insulating layer. Finally, a refilling layer is formed over the insulating layer and the substrate is planarized for having a planar surface. After that, the residual polysilicon layer is patterned to form a trasistor on the substrate. A conductive layer can be formed on the polished polysilicon before forming the transistor. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The foregoing aspects and many of the attendant advantages of this invention will become more readily appreciated and better understood by referencing the following detailed description, when taken in conjunction with the accompanying drawings as follows. 
     FIG. 1 illustrates a cross-sectional view of forming an upper-half portion of a trench in accordance with the present invention; 
     FIG. 2 illustrates a cross-sectional view of forming a sidewall structure on the opening in accordance with the present invention; 
     FIG. 3 illustrates a cross-sectional view of forming a lower-half portion of the trench in accordance with the present invention; 
     FIG. 4 illustrates a cross-sectional view of forming a first insulating layer over the trench in accordance with the present invention; 
     FIG. 5 illustrates a cross-sectional view of forming a second insulating layer over the first insulating layer and over the first stacked layer in accordance with the present invention; 
     FIG. 6 illustrates a cross-sectional view of forming a semiconductor layer over the second insulating layer in accordance with the present invention; 
     FIG. 7 illustrates a cross-sectional view of oxidizing a portion of the semiconductor layer for forming a third insulating layer in accordance with the present invention; 
     FIG. 8 illustrates a cross-sectional view of forming a filling layer over the third insulating layer in accordance with the present invention; 
     FIG. 9 illustrates a cross-sectional view of planarizing the substrate and forming a conductive layer in accordance with the present invention, and 
     FIG. 10 illustrates a cross-sectional view of forming transistors on the substrate in accordance with the present invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     The present invention propose a method to form a deep and shallow trench isolation. An upper-half shallow trench is formed followed by the formation of a lower-half deep trench with narrower width, by the defining of a sidewall structure. An oxynitride layer can be used for better dielectric characteristics. By the method in the present invention, the packing density and latch-up immunity of CMOS/bipolar circuits can be improved. The number of masks can also be reduced by the formation of the sidewall structure as an etching mask of the lower-half deep trench. 
     Referring to FIG. 1, a semiconductor substrate  10  is provided for forming isolation region and the active devices. In general, a silicon substrate with a preferable single crystalline silicon in a &lt;100&gt;direction can be used. For different specifications, other substrates with different crystalline orientations or materials can also be used. A pad layer  12  is formed over the semiconductor substrate  10 . An example of first pad layer  12  is an oxide layer which is grown thermally from the semiconductor substrate  10  in an oxygen-containing ambient. Further, the oxide layer  12  can also be silicon dioxide formed using a chemical vapor deposition process, with a tetraethylorthosilicate (TEOS) source, at a temperature between about 600 to 800 degrees centigrade and a pressure of about 0.1 to 10 torr. In the preferred embodiment, the thickness of the gate oxide layer  12  is about 150 angstroms to about 1,000 angstroms. The pad oxide layer  12  is employed to relieve the stress of a first stacked layer formed later. Thus the induced stress by the difference in thermal expansion coefficients between adjacent layers can be relived by applying a pad layer  12  in-between. 
     A first stacked layer  14  is then formed over the pad layer  12 . In such case, a polysilicon layer which is formed by chemical vapor deposition is employed as the stacked layer  14 . In general, the polysilicon can be deposited by any suitable process such as Low Pressure Chemical Vapor Deposition (LPCVD), Plasma Enhance Chemical Vapor Deposition (PECVD). In the preferred embodiment, the reaction gas of the step to form polysilicon includes silane. 
     Following the formation of the first stacked layer  14 , a second stacked layer  16  is formed thereover. The second stacked layer  16  is selected with the materials having a high selectivity when the substrate  10  is etched for forming a trench. Therefore, the critical dimension can be followed accurately by maintaining the dimension of the masking second stacked layer  16  with high etching selectivity. An oxide layer formed by chemical vapor deposition is used as the second stacked layer  16  in the preferred embodiment. The combination of the second stacked layer  16 , the first stacked layer  14 , and the first pad layer  12  serves as a masking layer for defining the active region. 
     An opening  20  is then defined in the second stacked layer  16 , the first stacked layer  14 , and the pad layer  12  by using a photoresist  18 . A lithography process and an etching process are introduced. The lithography process transfers a desired pattern on a mask to the photoresist layer  18 . The opening  20  is recessed down to the substrate  10 . The opening  20  defines the region for forming an upper-half trench. The region cover by the pad layer  12  are utilized to form active devices like CMOS or bipolar transistors. Generally speaking, the opening  20  can be defined with a patterning process including The etching process like a reactive ion etching (RIE) process can be employed to anisotropically etch the second stacked layer  16 , the first stacked layer  14 , and the pad layer  12 . A wide range of the width can be defined with different specifications and feature sizes. As an example, the width of the opening  20  can be 0.5 micrometer to 0.15 micrometer. For circuits with high integrity, a minimum width under the limitation of the lithography technology can be defined. 
     Next, a portion of the substrate  10  is removed for forming an upper-half portion of a trench by using the photoresist layer  18  and the second stacked layer  16  as a mask, as shown in FIG.  1 . The upper-half of the trench is a shallow trench region. The depth of the shallow trench region under the substrate surface  10  ranges between 500 angstroms to 3,000 angstroms in the case. The photoresist layer  18  is then removed. 
     Turning to FIG. 2, a sidewall structure  22  is then formed on the opening  20 . More particularly, the sidewall structure  22  is formed on the sidewall of the second stacked layer  16 , the first stacked layer  14 , the pad layer  12 , and the shallow trench. In the preferred embodiment, the sidewall structure  22  can be an oxide sidewall structure. An oxide layer is formed over the shallow trench and the second stacked layer  16 . The oxide sidewall spacers  22  is then formed by etching back the oxide layer. The spacers can be formed with a thickness of several hundred to several thousand angstroms on each side. Thus a deep trench region narrower than 0.1 micrometer can be defined. 
     Referring to FIG. 3, a portion of the substrate  10  is removed for forming a lower-half portion of the trench. The sidewall structure  22  is used as a mask and a deep trench is formed by etching into the substrate  10 . Preferably, an anisotropic etching process like a reactive ion etching can be used. In such case, the deep trench can be etched with a wide range of depth between about 300 angstroms to 10 micrometer. 
     The sidewall structure  22  and the second stacked layer  16  are then removed, as shown in FIG.  4 . With the oxide material in such case, a wet etching with a HF (hydrofluoric acid) containing solution like BOE solution can be used. The shallow-deep trench is thus exposed. A first insulating layer  26  is then formed over the trench  24  conformably to the top surface of the polysilicon layer  14 . In such case, the first insulating layer  26  can be an oxide layer which is grown thermally from the substrate  10  and the polysilicon layer  14 . The first insulating layer  26  can be grown with a thin thickness thus the stress induced defects by the bird&#39;s beak effect on the active region can be eliminated. The thickness of the oxide layer  26  is between about 30 angstroms to about 200 angstroms. 
     Referring to FIG. 5, a second insulating layer  28  is then formed over the first insulating layer  26 . In addition to the thin oxide layer  26 , the second insulating layer  28  is provided to improve the insulating characteristics of the trench isolation. In such case, an oxynitride layer formed by chemical vapor deposition is used. More specifically, the oxynitride layer  28  can be formed by LPCVD (low pressure chemical vapor deposition). The oxynitride layer  28  provides good dielectric characteristics with low stress problem to the underlying layers of the oxide layer  26  and the substrate  10 . The oxynitride layer  28  also serves as an oxidation buffer layer. With the protection of the oxynitride layer  28 , the substrate  10  can be protected from oxidation in an oxidation process performed later. 
     In the work “Oxidation behaviour of LPCVD Silicon Oxynitride Films” (Applied Surface Science 33/34, p. 757, 1988), the oxidation buffer effect is disclosed by A. E. T. Kuiper et al. It is found that the oxidation of oxynitride is at least one order of magnitude smaller than that of silicon. Layers with a composition near O/N=0.4 were found to have the greatest oxidation resistance. 
     A semiconductor layer  30  is then formed over the second insulating layer  28 , as shown in FIG.  6 . The semiconductor layer  30  can be an undoped amorphous silicon layer which is formed by chemical vapor deposition. The undoped amorphous silicon layer  30  is formed with good step coverage, thus the trench can be filled without unreached space or hole defects. A chemical vapor deposition like a LPCVD process can be applied with reduced temperature between about 400° C. to about 650° C. 
     Referring to FIG. 7, a portion of the silicon layer  30  is oxidized for forming a third insulating layer  32 . A high temperature steam oxidation process with a temperature between about 800° C. to about 1150° C. is employed. In the case, a portion of the silicon layer  30  in the shallow trench region is oxidized and another portion of the silicon layer  30  in the deep trench region is left without oxidization. The amorphous silicon in the deep trench region is transformed to poly crystalline silicon under the high temperature of the oxidization process. 
     Next, a filling layer  34  is formed over the substrate  10 , as shown in FIG.  8 . The filling layer is selected with the materials having similar removing rates with the third insulating layer  32 , namely the thermal oxide layer. Thus, a uniform planarization process can be performed to provide planar topography in a later step. In the case, a BPSG (borophosphosilicate) or a SOG (spin-on-glass) layer can be used. The BPSG layer can be formed by chemical vapor deposition and the SOG can be coated onto the substrate by a spinning process. Both layers can be formed with a planar top surface by the good flowing characteristics. 
     The substrate  10  is then planarized down to the top surface of the polysilicon layer  14 , as shown in FIG. 9. A chemical-mechanical polishing (CMP) process can be used. The filling layer  34 , a portion of the thermal oxide layer  32 , a portion of the oxynitride layer  28  and a portion of the polysilicon layer  14  are removed and a planar top surface is achieved. A conductive layer  36  is then deposited on the polished surface. In a case, the candidate of the conductive layer  36  can be TiSi, Wsi, TiN, Ti, Wn, TaN etc. 
     Therefore, a deep-shallow trench isolation is formed. Turning to FIG. 10, if desired, the conductive layer  36 , the residual polysilicon layer  14  and the pad oxide  12  can be patterned to form transistors  38  adjacent to the isolation structure and interconnection  42  such as word line or bit line on the top of the isolation  32 . The polysilicon layer  14  for forming the thermal oxide  26  can also be used to form the transistor. Thus, the polysilicon serve multi-function and it can integrate the procedure of the fabrication. As is known in the art, the transistor may include the spacer  36   b , source and drain region  40 . The spacer  36   b  is also formed and attached on the on the side of the deep-shallow trench isolation to improve the capability of isolation. The conductive layer on the gate may be transferred into metal silicide  36   a  to reduce the resistance by a well known manner. 
     The method of the present invention is applied with only one mask used. The efforts and cost of using two or more masks in the conventional trench isolation process can be reduced. The packing density and latch-up immunity of CMOS/bipolar circuits can be improved. The substrate  10  with the planarized deep-shallow trench isolation is then used to form the CMOS/bipolar devices on the active region with the improved latch-up immunity provided in the present invention. 
     As is understood by a person skilled in the art, the foregoing descriptions of the preferred embodiment of the present invention is an illustrative of the present invention rather than limitations thereon. They are intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims. The scope of the claims should be accorded the broadest interpretation so as to encompass all such modifications and similar structures. While the preferred embodiment of the invention has been illustrated and described, it will be appreciated that various changes can be made therein without departing from the spirit and scope of the invention.