Patent Publication Number: US-6338099-B1

Title: Device code recognizing circuit

Description:
FIELD OF THE INVENTION 
     The present invention generally relates to a circuit for generating and recognizing a serial ID code of a device, and in particular to a processor-based circuit capable to recognize a device code with a simplified circuit structure. 
     BACKGROUND OF THE INVENTION 
     Processor-based electronic devices and peripheral devices associated therewith are usually provided with a device code to be read and recognized by processors thereof for identification purposes in order to establish proper data connection therebetween. FIG. 8 of the attached drawings shows an example of a conventional device code recognizing circuit which makes use of a number of jumpers (J) and diodes (D) serially connected between an I/O terminal (A 1 ) and a key array (X) of a microprocessor (A). In the example shown in FIG. 8, eight sets of jumpers (J) and diodes (D) are used and respectively connected to eight input terminals (I 0 -I 7 ) of the key array (X). The I/O terminal (A 1 ) sequentially sends out high and low signals for being read by the input terminals (I 0 -I 7 ) and thus there are 2 8 =256 possible combinations of code. However, since the I/O terminal (A 1 ) is connected to the input terminals (I 0 -I 7 ), there must be diodes (D) therebetween in order to avoid undesired currents therethrough and prevent interference with the regular input function of the input terminals (I 0 -I 7 ) serving as part of the key array (X). The more input terminals (I 0 -I 7 ) used, the more diodes (D) are needed. This increases not only costs but also complexity of the circuit. 
     FIG. 9 shows another example of the conventional device code recognizing circuited wherein four I/O terminals (ID 0 -ID 3 ) of a microprocessor (A′) are respectively connected with switches (SW). The switches (SW) allows user&#39;s setting of the device code. No connection between the I/O terminals (ID 0 -ID 3 ) and the input terminals (R 0 -R 7 ) is needed thereby eliminating the current problem encountered in the example of FIG.  8  and simplifying the structure of the circuit. However, the number of combinations of code is limited to only 2 4 =16. To increase the number of possible code combination, additional terminals of the microprocessor (A′) must be used and this imposes additional limitation to the utilization of the microprocessor (A′). 
     Thus, it is desired to have a device code recognizing circuit which overcomes the problems encountered in the prior art. 
     SUMMARY OF THE INVENTION 
     Accordingly, an object of the present invention is to provide a device code recognizing circuit having a simple structure but providing the largest number of possible code combinations. 
     Another object of the present invention is to provide a device code recognizing circuit capable to provide the largest number of possible code combinations with the least number of terminals of a microprocessor. 
     A further object of the present invention is to provide a device code recognizing circuit wherein generation of a device code associated therewith does not interfere with the regular operation of the device. 
     To achieve the above objects, in accordance with the present invention, there is provided a device code recognizing circuit comprising a microprocessor forming an array having input pins and output pins and a code generation circuit connected to the microprocessor. The code generation circuit includes signal input terminals connected to input pins of the array and signal output terminals connected to I/O terminals of the microprocessor. The signal output terminals are sequentially and selectively set to one of low level condition and high impedance condition. The input pins of the microprocessor to which the signal input terminals of the code generation circuit are connected serially read signals from the code generation circuit for provision the signals to the microprocessor to form a device code associated therewith. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention will be apparent to those skilled in the art by reading the following description of preferred embodiments thereof, with reference to the accompanying drawings, in which: 
     FIG. 1 is a device code recognizing circuit constructed in accordance with a first embodiment of the present invention; 
     FIG. 2 is a device code recognizing circuit constructed in accordance with a second embodiment of the present invention; 
     FIG. 3 is an operational flow chart of the device code recognizing circuit of FIG. 2; 
     FIG. 4 is a device code recognizing circuit constructed in accordance with a third embodiment of the present invention; 
     FIG. 5 is an operational flow chart of the device code recognizing circuit of FIG. 4; 
     FIGS. 6 and 7 are examples of interface circuits adapted in the present invention; 
     FIG. 8 is a conventional device code recognizing circuit; and 
     FIG. 9 is another conventional device code recognizing circuit. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     With reference to the drawings and in particular to FIG. 1, wherein a device code recognizing circuit constructed in accordance with a first embodiment of the present invention is shown, the device code recognizing circuit of the present invention comprises a microprocessor  10  having at least one input port having input pins R 0 -R 7  and one output port having output pins S 0 -S 17 . The input and output pins R 0 -R 7 , S 0 -S 17  intersect each other and form a signal input array Y for reading input signals entered by means of for example keyboard or push button pad. The device code recognizing circuit comprises a code generation circuit  20  comprising a number of signal input terminals IP 0 -IP 7  corresponding to the input pins R 0 -R 7  of the array Y and a number of signal output terminals OT 0 -OT 1 . The number of the signal output terminals OT 0 -OT 1  is two in the embodiment illustrated, but may be varied if desired. 
     Each of the signal output terminals OT 0 -OT 1  is connected to one unused I/O terminals ID 0 , ID 1  of the microprocessor  10  and is connected to the input pins R 0 -R 7  via jumpers J 0 -J 7 , J 0 ′-J 7 ′ whereby each I/O terminal ID 0 -ID 1  of the microprocessor  10  is connected to the input pins R 0 -R 7  thereof via the jumpers J 0 -J 7 , J 0 ′-J 7 ′. 
     The operation of the circuit shown in FIG. 1 is that the I/O terminals ID 0 -ID 1  of the microprocessor  10  is sequentially pulled low, namely they are sequentially grounded, while the remaining I/O terminals ID 0 -ID 1  are open thereby being in a high impedance condition, and signals of the input pins R 0 -R 7  are serially read, namely being read one by one. Each I/O terminals ID 0 -ID 1  correspond to 8+1=9 combinations of code, namely open circuit condition of each jumper plus all jumpers closed. Therefore, there are 9 2 =81 combinations of code in this embodiment for there are two I/O terminals ID 0 , ID 1  used. By this way, only two unused I/O terminals ID 0 , ID 1  are used to generate the device code and they do not interfere with the regular operation of the input pins R 0 -R 7  for no high voltage level is applied to the I/O terminals ID 0 , ID 1 . In other words, low voltage level and high impedance condition are adapted to represent logic “0” and “1” in the present invention. 
     Since no high voltage level is generated in the I/O terminals ID 0 , ID 1 , there is no need to use diodes to prevent undesired currents as is required by the prior art. 
     FIG. 2 shows a device code recognizing circuit in accordance with a second embodiment of the present invention. The circuit of the second embodiment circuit makes use of four unused I/O terminals ID 0 -ID 3  of the microprocessor  10 . The four I/O terminals ID 0 -ID 3  are connected to signal output terminals OT 0 -OT 3  of the code generation circuit  20  while the signal input terminals IP 0 -IP 3  of the circuit  20  are connected to the input pins R 0 -R 7  of the microprocessor  10 . The code generation circuit  20  is shown in a simplified form in FIG. 2 with only the lines shorting the signal output terminals OT 0 -OT 3  to the signal input terminals IP 0 -IP 3  shown in the drawing. The code generation circuit  20  comprises jumpers (not shown in FIG. 2) or other elements to short the four I/O terminals ID 0 -ID 3  to some of the input pins R 0 -R 7 . In the embodiment illustrated, the I/O terminals ID 0 -ID 3  are respectively shorted to input pins R 0 , R 1 , R 3 , R 7  and the remaining connections therebetween are open. Since four I/O terminals ID 0 -ID 3  of the microprocessor  10  are used, the code generation code  20  may provide (8+1) 4 =6561 combinations of code. 
     FIG. 3 shows an operational flow chart of the device code recognizing circuit of FIG.  2 . Quite obviously, it is also applicable to the embodiment shown in FIG.  1 . At step  210 , the microprocessor  10  is started. To recognize the device code associated with the device in which the microprocessor  10  is mounted, I/O terminal ID 0  is grounded by the microprocessor  10  and the remaining I/O terminals ID 1 -ID 3  are open, step  220 . The input pins R 0 -R 7  are read by the microprocessor  10 , step  221 . 
     Thereafter, I/O terminal ID 1  is grounded and the remaining I/O terminals ID 0 , ID 2 , ID 3  are open, step  230 . The input pins R 0 -R 7  are read again by the microprocessor  10 , step  231 . Thereafter, I/O terminal ID 2  is grounded and the remaining I/O terminals ID 0 , ID 1 , ID 3  are open, step  240 . The input pins R 0 -R 7  are read again by the microprocessor  10 , step  241 . 
     Thereafter, I/O terminal ID 3  is grounded and the remaining I/O terminals ID 0 -ID 2  are open, step  250 . The input pins R 0 -R 7  are read again by the microprocessor  10 , step  251 . To this point, the device code is obtained as one of the 6561 possible combinations of the circuit  20 . The code is then sent out to a corresponding processor-based device (not shown) to identify the microprocessor  10  that generates the code, step  270 , and then the microprocessor  10  enters a regular operation mode, step  280 . 
     FIG. 4 shows a third embodiment of the present invention wherein the input pins R 0 -R 7  of the array Y of the microprocessor  10  are not involved in the generation and recognition of the device code thereof and only the I/O terminals ID 0 -ID 3  are used in the generation of the device code. The I/O terminals ID 0 -ID 3  are taken as both the signal input terminals IP 0 -IP 3  and the signal output terminals OT 0 -OT 3 . The I/O terminals ID 0 -ID 3  are interconnected with each other to form an array similar to the array Y with jumpers J 0 -J 7  and diodes D 0 -D 7  connected between the I/O terminals ID 0 -ID 3 . In other words, the I/O terminals ID 0 -ID 3  serve as both signal input terminals IP 0 -IP 3  and signal output terminals OT 0 -OT 3  of the circuit  20 . In the embodiment illustrated, I/O terminals ID 2 , ID 3  serve as the signal output terminals with I/O terminals ID 0 , ID 1  as the signal input terminals and vice versa. By this way, only the unused I/O terminals ID 0 -ID 3  are used to generate the device code and interference with the regular operation of the array Y is completely hindered. This embodiment provides  256  possible combinations that is equal to 2 k*2 , where k=(N IO /2) 2  and N IO  is the number of I/O terminals ID 0 -ID 3  and is four in this embodiment. 
     FIG. 5 is an operational flow chart of FIG.  4 . The microprocessor  10  is started at step  310 . ID 3  is grounded and ID 2  is open, step  320 , and ID 0 , ID 1  are read, step  321 . Then, ID 2  is grounded and ID 3  is open, step  330 , and ID 0 , ID 1  are read, step  331 . Thereafter, ID 1  is grounded and ID 0  is open, step  340 , and ID 2 , ID 3  are read, step  341 . Then, ID 0  is grounded and ID 1  is open, step  350 , and ID 2 , ID 3  are read, step  351 . Thereafter, all the I/O terminals ID 0 -ID 3  are open, step  360 , and the microprocessor  10  sends out the device code associated therewith as one of the  256  possible combinations determined by the jumpers J 0 -J 7 , step  370 . The microprocessor  10  enters a regular operation mode, step  380 , thereafter. 
     FIGS. 6 and 7 show two examples of an interface circuit  400  connected between each signal input terminal IP 0 -IP 7  and each signal output terminal OT 0 -OT 7 . The interface circuits  400  and  401  comprise at least one transistor Q, Q′ and at least one buffering element B. In the embodiment of FIG. 6, the transistor Q is an N-channel MOSFET configured as an open drain circuit connected between the corresponding jumper J 0 -J 7 , J 0 ′-J 7 ′ and the signal output terminal OT 0 -OT 3  (or the I/O terminal ID 0 -ID 3 ). In the embodiment of FIG. 7, the transistor Q′ is a P-channel MOSFET configured as an open drain circuit connected between the corresponding jumper J 0 -J 7 , J 0 ′-J 7 ′ and the signal output terminal OT 0 -OT 3  (or the I/O terminal ID 0 -ID 3 ). Such interface circuits  400  and  401  cooperates with the I/O terminals ID 0 -ID 3  that are set to low voltage level or high impedance condition to determine the input signal of the input pins R 0 -R 7 . 
     Although the present invention has been described with respect to preferred embodiments, it is contemplated that a variety of modifications, variations and substitutions may be done without departing from the scope of the present invention that is intended to be defined by the appended claims. For example, the input pins R 0 -R 7 , the output pins S 0 -S 17  and the I/O terminals ID 0 -ID 3  mentioned in the above embodiments may be replaced by other terminals of the microprocessor, such as other I/O ports with proper modifications.