Patent Publication Number: US-2023164980-A1

Title: Semiconductor device and method of fabricating the same

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This U.S. non-provisional patent application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2021-0163706, filed on Nov. 24, 2021, in the Korean Intellectual Property Office, the entire contents of which are hereby incorporated by reference. 
     BACKGROUND 
     1. Field 
     Embodiments relate to a semiconductor device and a method of fabricating the same. 
     2. Description of the Related Art 
     Due to their small-sized, multifunctional, and/or low-cost characteristics, semiconductor devices are being esteemed as important elements in the electronic industry. With the advancement of the electronic industry, there is an increasing demand for a semiconductor device with higher integration density. 
     SUMMARY 
     The embodiments may be realized by providing a semiconductor device including a substrate including an active portion defined by a device isolation pattern; a word line in the substrate, the word line crossing the active portion and extending in a first direction; a bit line crossing the active portion and the word line and extending in a second direction intersecting the first direction; a first pad on an end portion of the active portion; a first contact on the first pad and adjacent to the bit line in the first direction; and an insulating separation pattern on the word line and adjacent to the first contact in the second direction, wherein the first contact includes a barrier pattern on the first pad, and a conductive pattern vertically extending from the barrier pattern, and a side surface of the conductive pattern of the first contact is in direct contact with the insulating separation pattern. 
     The embodiments may be realized by providing a semiconductor device including a substrate including an active portion defined by a device isolation pattern; a word line in the substrate, the word line crossing the active portion and extending in a first direction; a bit line crossing the active portion and the word line and extending in a second direction intersecting the first direction; a bit line spacer covering a side surface of the bit line; a first contact on a center portion of the active portion and connected to the bit line; a first pad on an end portion of the active portion and spaced apart from the first contact in the first direction; a second contact on the first pad and adjacent to the bit line in the first direction; an ohmic contact layer between the first pad and the second contact; an insulating separation pattern on the word line and adjacent to the second contact in the second direction; a second pad on the second contact; and a data storage pattern on the second pad, wherein the bit line spacer includes a first spacer, a second spacer, a third spacer, and a fourth spacer sequentially stacked on the side surface of the bit line, the second contact includes a barrier pattern on the first pad, and a conductive pattern vertically extending from the barrier pattern, and a side surface of the conductive pattern of the second contact is in direct contact with the insulating separation pattern and the fourth spacer of the bit line spacer. 
     The embodiments may be realized by providing a method of fabricating a semiconductor device, the method including forming a device isolation pattern on a substrate to define active portions; forming word lines in the substrate to cross the active portions and to extend in a first direction; forming first pads on the active portions; partially etching the active portions and the first pads to form a first opening; forming a first contact in the first opening; forming bit lines to cross the active portions and the word lines and to extend in a second direction intersecting the first direction; sequentially forming a first spacer, a second spacer, and a third spacer on side surfaces of the bit lines; forming second contacts between the bit lines and between the word lines, the second contacts being in contact with the first pads; and forming insulating separation patterns between the second contacts, wherein each of the second contacts includes a barrier pattern formed on each of the first pads, and a conductive pattern formed on the barrier pattern, and side surfaces of the conductive pattern of each of the second contacts are in direct contact with the insulating separation patterns. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Features will be apparent to those of skill in the art by describing in detail exemplary embodiments with reference to the attached drawings in which: 
         FIG.  1 A  is a plan view of a semiconductor device according to an embodiment. 
         FIGS.  1 B and  1 C  are sectional views, which are respectively taken along lines I-I′ and of  FIG.  1 A  to illustrate a semiconductor device according to an embodiment. 
         FIG.  2    is an enlarged sectional view of a portion (e.g., A of  FIG.  1 C ) of a semiconductor device according to an embodiment. 
         FIG.  3    is a sectional view, which is taken along the line II-II′ of  FIG.  1 A  to illustrate a semiconductor device according to an embodiment. 
         FIG.  4    is an enlarged sectional view of a portion (e.g., B of  FIG.  3   ) of a semiconductor device according to an embodiment. 
         FIGS.  5 A,  6 A,  7 A,  8 A,  11 A,  13 A, and  15 A  are plan views of stages in a method of fabricating a semiconductor device, according to an embodiment. 
         FIGS.  5 B,  6 B,  7 B,  8 B,  9 ,  10 ,  11 B,  12 A,  13 B,  14 A, and  15 B  are sectional views, each of which is taken along a line I-I′ of a corresponding one of  FIGS.  5 A,  6 A,  7 A,  8 A,  11 A,  13 A, and  15 A  to illustrate stages in a method of fabricating a semiconductor device according to an embodiment. 
         FIGS.  5 C,  6 C,  12 B,  13 C,  14 B, and  15 C  are sectional views, each of which is taken along a line II-II′ of a corresponding one of  FIGS.  5 A,  6 A,  7 A,  8 A,  11 A,  13 A, and  15 A  to illustrate stages in a method of fabricating a semiconductor device according to an embodiment. 
     
    
    
     DETAILED DESCRIPTION 
       FIG.  1 A  is a plan view of a semiconductor device according to an embodiment.  FIGS.  1 B and  1 C  are sectional views, which are respectively taken along lines I-I′ and II-II′ of  FIG.  1 A  to illustrate a semiconductor device according to an embodiment. 
     Referring to  FIGS.  1 A,  1 B, and  1 C , a substrate  100  including a plurality of active portions ACT may be provided. The substrate  100  may be a semiconductor substrate. In an implementation, the substrate  100  may be a silicon wafer, a silicon-germanium wafer, a germanium wafer, a silicon-on-insulator (SOI) wafer, a germanium-on-insulator (GOI) wafer, or a single crystalline epitaxial layer grown on a single-crystalline silicon wafer. The substrate  100  may extend in a first direction D 1  and a second direction D 2 , which are not parallel to each other, and may have a top surface that is normal to a third direction D 3 , which are not parallel to both of the first and second directions D 1  and D 2 . In an implementation, the first, second, and third directions D 1 , D 2 , and D 3  may be orthogonal to each other. 
     A device isolation pattern  110  may be on the substrate  100 . The device isolation pattern  110  may define the active portions ACT of the substrate  100 . The device isolation pattern  110  may be formed of or include, e.g., silicon oxide, silicon nitride, or silicon oxynitride, and may have a single-layered or multi-layered structure. As used herein, the term “or” is not an exclusive term, e.g., “A or B” would include A, B, or A and B. 
     Each of the active portions ACT may have an isolated shape. When viewed in the plan view of  FIG.  1 A , each of the active portions ACT may have an elongated bar shape that extends (e.g., lengthwise) in a fourth direction D 4 , which is parallel to the top surface of the substrate  100  but is not parallel to either of the first and second directions D 1  and D 2 . Each of the active portions ACT may correspond to a portion of the substrate  100  surrounded by the device isolation pattern  110 . The active portions ACT may be arranged to be parallel to each other, and each of the active portions ACT may be arranged such that an end thereof is located near a center of another of the active portions ACT adjacent thereto in the first direction D 1 . 
     In an implementation, a top surface of the device isolation pattern  110  may be located at a level lower than top surfaces of the active portions ACT (e.g., in the third direction D 3 ). Upper portions of the active portions ACT may protrude from or above the top surface of the device isolation pattern  110  in the third direction D 3 . The device isolation pattern  110  may expose at least a portion of a side surface of each of the active portions ACT. 
     Word lines WL may cross the active portions ACT and may extend in the first direction D 1 . The word lines WL may be spaced apart from each other in the second direction D 2 . Each pair of the word lines WL may cross a corresponding one of the active portions ACT. The word lines WL may be buried in the substrate  100 . In an implementation, the word lines WL may have top surfaces that are located at a level lower than the top surfaces of the active portions ACT and the top surface of the device isolation pattern  110 . A bottom surface of each of the word lines WL may have a curved shape. The word lines WL may include a conductive material. 
     Word line capping patterns  120  may be on the word lines WL. The word line capping patterns  120  on the word lines WL may extend in the first direction D 1 . Each of the word line capping patterns  120  may cover the entire top surface of a corresponding one of the word lines WL. In an implementation, the word line capping patterns  120  may be formed of or include, e.g., silicon nitride. 
     A gate dielectric layer  125  may cover bottom and side surfaces of each of the word lines WL and side surfaces of each of the word line capping patterns  120 . The gate dielectric layer  125  may be between each of the word lines WL and the substrate  100  (i.e., between each of the word lines WL and the active portions ACT) and between each of the word line capping patterns  120  and the active portions ACT. A top surface of the gate dielectric layer  125  may be at a level lower than the top surfaces of the active portions ACT. In an implementation, the top surface of the gate dielectric layer  125  may be located at substantially the same level as the top surface of the device isolation pattern  110 . The gate dielectric layer  125  may be formed of or include, e.g., silicon oxide, silicon nitride, silicon oxynitride, or high-k dielectric materials. 
     A first impurity region  1   a  may be in a center portion of each active portion ACT, which is between the paired word lines WL. A pair of second impurity regions  1   b  may be at or on opposite end portions of each active portion ACT. Each of the first and second impurity regions  1   a  and  1   b  may have a conductivity type different from the substrate  100 . In the case where the substrate  100  has a first conductivity type (e.g., p-type), each of the first and second impurity regions  1   a  and  1   b  may have a second conductivity type (e.g., n-type) that is different from the first conductivity type. In an implementation, the first impurity region  1   a  may correspond to a common drain region, and the second impurity regions  1   b  may correspond to source regions. 
     The word lines WL and the first and second impurity regions  1   a  and  1   b  adjacent thereto may constitute transistors. The word lines WL may be buried in the substrate  100 , and it may be possible to increase a channel length of the transistor formed within a limited area and hence to suppress or minimize a short channel effect. 
     A first contact DC may be on the first impurity region  1   a  of each of the active portions ACT. The first contact DC may be in a first opening OH 1  to cover a bottom surface of the first opening OH 1 . The first contact DC may electrically connect the first impurity region  1   a  to one of bit lines BL to be described below. The first contact DC may have a circular or elliptical shape, when viewed in the plan view of  FIG.  1 A . An area of the first contact DC may be larger than an overlapping area between one of the bit lines BL and the first impurity region  1   a , which are overlapped with each other in the vertical direction (i.e., the third direction D 3 ). 
     The first contact DC may include a first portion  131  and a second portion  132  on the first portion  131 . In an implementation, as a distance in the third direction D 3  (i.e., from the substrate  100 ) increases, the first portion  131  and the second portion  132  may have an increasing width and a decreasing width, respectively. An upper width of the first contact DC (i.e., an upper width of the second portion  132 ) may be smaller than its lower width (i.e., a lower width of the first portion  131 ). In an implementation, the upper width of the first contact DC may be substantially equal to a lower width of one of the bit lines BL, and the lower width of the first contact DC may be larger than an upper width of each of the active portions ACT. At least a portion of a bottom surface of the first contact DC may be in contact with the device isolation pattern  110 . In an implementation, the first contact DC may be formed of or include, e.g., doped poly silicon. 
     A contact insulating structure  140  may be on an inner side surface of the first opening OH 1  to enclose the first portion  131  of the first contact DC. The contact insulating structure  140  may be an annular or doughnut-shaped structure enclosing the first portion  131  of the first contact DC, when viewed in the plan view of  FIG.  1 A . A bottom surface of the contact insulating structure  140  may be substantially coplanar with the bottom surface of the first contact DC. The first contact DC may be spaced apart from the second impurity regions  1   b , which are placed near the same in the first direction D 1 , with the contact insulating structure  140  interposed therebetween. 
     The contact insulating structure  140  may include a first contact insulating pattern  142 , which is on the inner side surface of the first opening OH 1 , and a second contact insulating pattern  144 , which is between the first contact insulating pattern  142  and the first contact DC. The first contact insulating pattern  142  may extend from the inner side surface of the first opening OH 1  along the bottom surface of the first opening OH 1  and may be in contact with the device isolation pattern  110 . The second contact insulating pattern  144  may be surrounded by the first contact insulating pattern  142  and may be spaced apart from the device isolation pattern  110 . The first and second contact insulating patterns  142  and  144  may be formed of or include different insulating materials from each other. In an implementation, the first contact insulating pattern  142  may be formed of or include, e.g., silicon nitride, the second contact insulating pattern  144  may be formed of or include, e.g., silicon oxide. 
     A gapfill insulating structure  150  may be in the first opening OH 1  to enclose the second portion  132  of the first contact DC. The gapfill insulating structure  150  may be a doughnut-shaped structure enclosing the second portion  132  of the first contact DC, when viewed in the plan view of  FIG.  1 A . The gapfill insulating structure  150  may be in a first recess portion RC 1 . The first contact DC may be spaced apart from first pads XP and second contacts BC, which may be near the same in the first direction D 1 , with the gapfill insulating structure  150  therebetween. 
     The gapfill insulating structure  150  may include a first gapfill insulating pattern  151 , which may conformally cover an inner side surface of the first recess portion RC 1  (i.e., the inner side surface of the first opening OH 1  and a side surface of the second portion  132  of the first contact DC), and a second gapfill insulating pattern  152 , which may fill a space defined by the first gapfill insulating pattern  151 . The first and second gapfill insulating patterns  151  and  152  may fully fill the first recess portion RC 1 . The first gapfill insulating pattern  151  may cover a top surface of the contact insulating structure  140 . The first and second gapfill insulating patterns  151  and  152  may be formed of or include insulating materials different from each other. In an implementation, the first gapfill insulating pattern  151  may be formed of or include, e.g., silicon oxide, the second gapfill insulating pattern  152  may be formed of or include, e.g., silicon nitride. 
     The first contact DC, the contact insulating structure  140 , and the gapfill insulating structure  150  may fully fill the first opening OH 1 . The contact insulating structure  140  and the gapfill insulating structure  150  may help suppress an interference issue between the first contact DC and the first pads XP and between the first contact DC and the second contacts BC. 
     The first pads XP may be on the second impurity regions  1   b  of each of the active portions ACT. The first pads XP may electrically connect the second impurity regions  1   b  to the second contacts BC. Each of the first pads XP may have a shape similar to a rectangle, when viewed in the plan view of  FIG.  1 A . In each of the first pads XP, a side surface adjacent to the first contact DC may be recessed in a direction away from the first contact DC (i.e., in the first direction D 1  or in an opposite direction thereof). An area of each of the first pads XP may be larger than an overlapping area between one of the second impurity regions  1   b  and one of the second contacts BC, which are overlapped with each other in the third direction D 3  (i.e., vertically), and may be larger than an area of a top surface of each of the second impurity regions  1   b.    
     At least a portion of a top surface of each of the first pads XP may be recessed. The recessed top surface of each of the first pads XP may have a concavely curved shape. At least a portion of a bottom surface of each of the first pads XP may be located at a level lower than top surfaces  1   bt  of the second impurity regions  1   b . In an implementation, each of the first pads XP may cover a portion of the side surface of each of the active portions ACT. A portion of the bottom surface of each of the first pads XP may be in contact with the top surface of the device isolation pattern  110 . Another portion of the bottom surface of each of the first pads XP may be in contact with the top surface of the gate dielectric layer  125  on a side surface of each of the word lines WL. In an implementation, the bottom surface of each of the first pads XP may be substantially coplanar with the top surfaces  1   bt  of the second impurity regions  1   b . Ones of the first pads XP, which are adjacent to the first contact DC, may be spaced apart from the first contact DC with the contact insulating structure  140  and the gapfill insulating structure  150  interposed therebetween. 
     An ohmic contact layer OL may be between each of the first pads XP and each of the second contacts BC. Due to the ohmic contact layer OL, the first pads XP may have an ohmic contact property, when they are connected to the second contacts BC. The ohmic contact layer OL may be on the recessed top surface of each of the first pads XP. A bottom surface of the ohmic contact layer OL may have a shape that is curved along the recessed top surface of each of the first pads XP (e.g., in a complementary manner). A top surface of the ohmic contact layer OL may have a curved shape, like a bottom surface of a second recess portion RC 2  to be described below. In an implementation, the ohmic contact layer OL may be formed of or include, e.g., a metal silicide material (e.g., cobalt silicide). 
     First insulating separation patterns  160  may be between the first pads XP. Some of the first insulating separation patterns  160  may be between the device isolation pattern  110  and the bit lines BL to separate the first pads XP from each other in the first direction D 1 , and others of the first insulating separation patterns  160  may be between the word line capping patterns  120  and second insulating separation patterns  240 , which will be described below, to separate the first pads XP from each other in the second direction D 2 . Some of the first insulating separation patterns  160  may extend in the third direction D 3  and may be partially inserted into the device isolation pattern  110 , and in this case, bottom surfaces thereof may be located at a level lower than the top surface of the device isolation pattern  110 . Others of the first insulating separation patterns  160  may have bottom surfaces that are located at a level lower than the top surface of the gate dielectric layer  125  and are in contact with top surfaces of the word line capping patterns  120 . The first insulating separation patterns  160  may be formed of or include, e.g., silicon oxide, silicon nitride, or silicon oxynitride. 
     The bit lines BL may extend in the second direction D 2  to cross the active portions ACT and the word lines WL. The bit lines BL may be spaced apart from each other in the first direction D 1 . Each of the bit lines BL may be on the first impurity region  1   a  of a corresponding one of the active portions ACT and may be in contact with the first contact DC. Each of the bit lines BL may include a first barrier pattern  211  and a first conductive pattern  213 , which are sequentially stacked. 
     Each of the bit lines BL may extend from the first impurity region  1   a  of each of the active portions ACT into regions between the first pads XP, when viewed in the plan view of  FIG.  1 A . Each of the bit lines BL may be on the first insulating separation patterns  160  and between the first pads XP. Buffer insulating patterns  201  may be between each of the bit lines BL and the first insulating separation patterns  160 . In an implementation, the buffer insulating patterns  201  may be formed of or include, e.g., silicon nitride. 
     In an implementation, each of the bit lines BL may further include a poly silicon pattern below the first barrier pattern  211 . The first barrier pattern  211  may be formed of or include, e.g., titanium, titanium nitride, titanium silicon nitride, tantalum, tantalum nitride, or tungsten nitride. The first conductive pattern  213  may be formed of or include a metallic material (e.g., tungsten, aluminum, copper, ruthenium, or iridium). 
     Bit line capping patterns  215  may be on the bit lines BL. The bit line capping patterns  215  may extend in the second direction D 2  on the bit lines BL. Each of the bit line capping patterns  215  may cover the entire top surface of a corresponding one of the bit lines BL. In an implementation, the bit line capping patterns  215  may be formed of or include silicon nitride. 
     Bit line spacers SP may cover side surfaces of the bit lines BL and side surfaces of the bit line capping patterns  215  and may extend in the second direction D 2  or along the bit lines BL and the bit line capping patterns  215 . Each of the bit line spacers SP may be between the bit lines BL and the second contacts BC. Each of the bit line spacers SP may include a first spacer  221 , a second spacer  223 , a third spacer  225 , and a fourth spacer  227 , which are sequentially stacked in a direction away from the side surfaces of the bit lines BL and the side surfaces of the bit line capping patterns  215 . Adjacent ones of the first to third spacers  221 ,  223 , and  225  may include different insulating materials from each other. In an implementation, one of the first to fourth spacers  221 ,  223 ,  225 , and  227  may be an air layer or an air gap. 
     The first spacer  221  may be in direct contact with the side surfaces of the bit lines BL and the side surfaces of the bit line capping patterns  215 . On the first contact DC, a portion of a bottom surface of the first spacer  221  may be in contact with the first gapfill insulating pattern  151  of the gapfill insulating structure  150 . In an implementation, an outer side surface of the first spacer  221  may be aligned to a side surface of the first gapfill insulating pattern  151  (hereinafter, an outer side surface of a spacer means a side surface of the spacer in a direction away from the side surfaces of the bit lines BL). One each of the first insulating separation patterns  160 , another portion of the bottom surface of the first spacer  221  may be in contact with each of the buffer insulating patterns  201 . In an implementation, the first spacer  221  may be formed of or include silicon nitride. 
     The second spacer  223  may be between the first spacer  221  and the third spacer  225 . On the first contact DC, a portion of a bottom surface of the second spacer  223  may be in contact with the second gapfill insulating pattern  152  of the gapfill insulating structure  150 . Another portion of the bottom surface of the second spacer  223  may be in contact with the first pads XP. The second spacer  223  may include a material having an etch selectivity with respect to the first spacer  221  and the third spacer  225 . In an implementation, the second spacer  223  may be formed of or include silicon oxide. In an implementation, the second spacer  223  may be an air layer or an air gap. 
     The third spacer  225  may be between the second spacer  223  and the fourth spacer  227 . On the first contact DC, a portion of a bottom surface of the third spacer  225  may be in contact with the second gapfill insulating pattern  152  of the gapfill insulating structure  150 . In an implementation, an outer side surface of the third spacer  225  may be aligned to a side surface of the second gapfill insulating pattern  152 . Another portion of the bottom surface of the third spacer  225  may be in contact with the first pads XP and the ohmic contact layer OL. In an implementation, the outer side surface of the third spacer  225  may be aligned to or with a side surface of the ohmic contact layer OL (i.e., an inner side surface of the second recess portion RC 2 ). The third spacer  225  may include a material having an etch selectivity with respect to the second spacer  223  and the fourth spacer  227 . In an implementation, the third spacer  225  may be formed of or include silicon nitride. 
     The fourth spacer  227  may be between the third spacer  225  and a second conductive pattern  234  (to be described below) of each of the second contacts BC. In an implementation, the fourth spacer  227  may extend from the outer side surface of the third spacer  225  along top surfaces of the first to third spacers  221 ,  223 , and  225  and a top surface of each of the bit line capping patterns  215 . A bottom surface of the fourth spacer  227  may be in contact with a second barrier pattern  232  (to be described below) of each of the second contacts BC. In an implementation, an outer side surface of the fourth spacer  227  may extend along a side surface of the second conductive pattern  234  of each of the second contacts BC in the third direction D 3  and may be aligned to or with a side surface of the second barrier pattern  232  of each of the second contacts BC. In an implementation, the fourth spacer  227  may include an insulating material different from the third spacer  225 . In an implementation, the fourth spacer  227  may be formed of or include silicon oxide or silicon oxycarbide. In an implementation, the fourth spacer  227  may be an air layer. In an implementation, the fourth spacer  227  may include the same insulating material as the third spacer  225 . In an implementation, the fourth spacer  227  may be formed of or include silicon nitride. 
     The fourth spacer  227  may be connected to the second insulating separation patterns  240 , which are adjacent thereto in the second direction D 2 . In an implementation, the fourth spacer  227  may be formed of or include the same insulating material as the second insulating separation patterns  240 . 
     The second contacts BC may be between the word lines WL, which are adjacent to each other in the second direction D 2 , and between the bit lines BL, which are adjacent to each other in the first direction D 1 . Each of the second contacts BC may extend on or from a corresponding one of the first pads XP in the third direction D 3 . When viewed in the sectional view of  FIG.  1 B , each of the second contacts BC may have first side surfaces BCs 1  that are in direct contact with the bit line spacers SP. In an implementation, each of the first side surfaces BCs 1  may be in contact with the fourth spacer  227  of each of the bit line spacers SP. When viewed in the sectional view of  FIG.  1 C , each of the second contacts BC may have second side surfaces BCs 2  that are in direct contact with each of the second insulating separation patterns  240 . In an implementation, the first side surfaces BCs 1  may be side surfaces of the second contacts BC that are substantially normal to the first direction D 1 , and the second side surfaces BCs 2  may be side surfaces of the second contacts BC that are substantially normal to the second direction D 2 . 
     A bottom surface of each of the second contacts BC may have a curved shape protruding (e.g., downwardly convex) toward the substrate  100  and may be in contact with each of the first pads XP. A top surface of each of the second contacts BC may be substantially coplanar with the uppermost surface of the fourth spacer  227 . 
     Each of the second contacts BC may include the second barrier pattern  232 , which is in contact with a corresponding one of the first pads XP, and the second conductive pattern  234 , which is on the second barrier pattern  232 . The second barrier pattern  232  may extend along the bottom surface of the second recess portion RC 2  to conformally cover a top surface of the ohmic contact layer OL and a portion of a top surface of the gapfill insulating structure  150 . The second barrier pattern  232  may be in contact with the fourth spacer  227  and one of protruding portions  240   p  of each of the second insulating separation patterns  240 . The second barrier pattern  232  may not be between the third spacer  225  and the second conductive pattern  234  and between each of the second insulating separation patterns  240  and the second conductive pattern  234 . In an implementation, the second barrier pattern  232  may be locally at a level that is lower than bottom surfaces BLb of the bit lines BL and bottom surfaces SPb of the bit line spacers SP. In this case, it may be possible to help reduce a parasitic capacitance between the bit lines BL, without a reduction in a contact area between each of the second contacts BC and each of the first pads XP, and hence to improve electrical characteristics and reliability of the semiconductor device. 
     A bottom surface of the second conductive pattern  234  may have a shape that is curved along a top surface of the second barrier pattern  232 . The bottom surface of the second conductive pattern  234  may be at a level lower than the bottom surfaces BLb of the bit lines BL and lower than the bottom surfaces SPb of the bit line spacers SP. The second barrier pattern  232  may cover the bottom surface of the second conductive pattern  234 . 
     The second barrier pattern  232  may be formed of or include, e.g., titanium, titanium nitride, titanium silicon nitride, tantalum, tantalum nitride, or tungsten nitride. The second conductive pattern  234  may include a material different from the first contact DC. The second conductive pattern  234  may be formed of or include a metallic material (e.g., tungsten, aluminum, copper, ruthenium, and iridium). 
     Second openings OH 2  may be between the bit lines BL, which are adjacent to each other in the first direction D 1 , and the second insulating separation patterns  240  may be in the second openings OH 2 . When viewed in the plan view of  FIG.  1 A , the second insulating separation patterns  240  may be between the first pads XP, which are adjacent to each other in the second direction D 2 . The second insulating separation patterns  240  may be in contact with the second side surfaces BCs 2  of the second contacts BC. Each of the second insulating separation patterns  240  may be overlapped with a corresponding one of the word lines WL in the third direction D 3  (i.e., vertically) and may be on a corresponding one of the first insulating separation patterns  160 . Bottom surfaces of the second insulating separation patterns  240  may be located at a level lower than the bottom surfaces of the second contacts BC. In an implementation, the bottom surfaces of the second insulating separation patterns  240  may be located at a level lower than the top surfaces of the first pads XP. As a distance in the third direction D 3  increases, a width of each of the second insulating separation patterns  240  may increase. The second insulating separation patterns  240  may be formed of or include, e.g., silicon oxide, silicon nitride, or silicon oxynitride. 
     In an implementation, the second insulating separation patterns  240  may help prevent or suppress a bridge pattern (e.g., a short circuit) from being formed between the second contacts BC, and thus, it may be possible to improve electrical characteristics and reliability of the semiconductor device. 
     Second pads LP may be on the second contacts BC, respectively. When viewed in the plan view of  FIG.  1 A , the second pads LP may be spaced apart from each other and may have an isolated island shape. In an implementation, six second pads LP, which are placed around one of the second pads LP, may be arranged to form a hexagonal shape. In an implementation, the second pads LP may be arranged to form a honeycomb shape. A bottom surface of each of the second pads LP may be substantially flat. The bottom surface of each of the second pads LP may be in contact with the second conductive pattern  234  of each of the second contacts BC and the fourth spacer  227  of each of the bit line spacers SP. The bottom surface of each of the second pads LP may be in contact with at least a portion of the second insulating separation patterns  240 . 
     Each of the second pads LP may include a third barrier pattern  301  on the second conductive pattern  234  of each of the second contacts BC, and a third conductive pattern  303  on the third barrier pattern  301 . The third barrier pattern  301  may be formed of or include, e.g., titanium, titanium nitride, titanium silicon nitride, tantalum, tantalum nitride, or tungsten nitride. The third conductive pattern  303  may be formed of or include a metallic material (e.g., tungsten, aluminum, copper, ruthenium, or iridium). 
     A third insulating separation pattern LPS may be between adjacent ones of the second pads LP. The third insulating separation pattern LPS may define the second pads LP. A top surface of the third insulating separation pattern LPS may be substantially coplanar with top surfaces of the second pads LP. The third insulating separation pattern LPS may face side surfaces of the second pads LP or to enclose the second pads LP and may extend to a level lower than bottom surfaces of the second pads LP. A bottom surface of the third insulating separation pattern LPS may be located at a level between top surfaces of the bit lines BL and the bottom surfaces of the second pads LP. In the case where the second spacer  223  or the fourth spacer  227  are the air layers, at least a portion of the third insulating separation pattern LPS may protrude in the third direction D 3 . The third insulating separation pattern LPS may be formed of or include, e.g., silicon oxide, silicon nitride, or silicon oxynitride. 
     Data storage patterns DSP may be on the second pads LP, respectively. In an implementation, each of the data storage patterns DSP may be a capacitor including a bottom electrode, a dielectric layer, and a top electrode. In this case, the semiconductor device may be a dynamic random access memory (DRAM) device. In an implementation, each of the data storage patterns DSP may include a magnetic tunnel junction pattern. In this case, the semiconductor device may be a magnetic random access memory (MRAM) device. In an implementation, the data storage patterns DSP may include a phase change material or a variable resistance material. In this case, the semiconductor device may be a phase-change random access memory (PRAM) device or a resistive random access memory (ReRAM) device. In an implementation, each of the data storage patterns DSP may include various structures or materials which may be used to store data. 
       FIG.  2    is an enlarged sectional view of a portion (e.g., A of  FIG.  1 C ) of a semiconductor device according to an embodiment. 
     Referring to  FIG.  2   , one of the second insulating separation patterns  240  is illustrated. The description that follows will refer to one of the second insulating separation patterns  240 , but the others of the second insulating separation patterns  240  may be configured to have substantially the same features as those to be described below. 
     The second insulating separation pattern  240  may include protruding portions  240   p , which (e.g., laterally) protrude from its side surface (e.g., relative to the second side surfaces BCs 2  of each of the second contacts BC) in a horizontal direction (e.g., the second direction D 2  and an opposite direction thereof). Each of the protruding portions  240   p  may be overlapped with the second conductive pattern  234  of each of the second contacts BC in the third direction D 3  (i.e., vertically). Each of the protruding portions  240   p  may be in contact (e.g., direct contact) with the second barrier pattern  232  of each of the second contacts BC. In an implementation, each of the protruding portions  240   p  may be in contact (e.g., direct contact) with the ohmic contact layer OL. 
     A bottom surface  240   b  of the second insulating separation pattern  240  may be located at a level lower than the bottom surfaces of the second contacts BC. In an implementation, the bottom surface  240   b  of the second insulating separation pattern  240  may be located at a level lower than the top surfaces of the first pads XP. 
       FIG.  3    is a sectional view, which is taken along the line II-II′ of  FIG.  1 A  to illustrate a semiconductor device according to an embodiment.  FIG.  4    is an enlarged sectional view of a portion (e.g., B of  FIG.  3   ) of a semiconductor device according to an embodiment. For concise description, an element previously described with reference to  FIGS.  1 A,  1 B,  1 C, and  2    may be identified by the same reference number without repeating an overlapping description thereof. 
     Referring to  FIGS.  3  and  4   , at least one of the second insulating separation patterns  240  may include a first portion  241 , which extends along a side surface of the second conductive pattern  234  of each of the second contacts BC (i.e., the second side surface BCs 2 ) in the third direction D 3 , and a second portion  242  below the first portion  241  and in contact with a side surface of the second barrier pattern  232  of each of the second contacts BC. A width (e.g., in the second direction D 2 ) of the second portion  242  may be smaller than a width of the first portion  241  (e.g., in the second direction D 2 ). 
     The bottom surface  240   b  of the second insulating separation pattern  240 , which is defined as a bottom surface of the second portion  242 , may be in contact (e.g., direct contact) with a top surface of the first insulating separation pattern  160 . The bottom surface  240   b  of the second insulating separation pattern  240  may be located at a level higher than the top surfaces of the first pads XP and the bottom surfaces of the second contacts BC. The bottom surface  240   b  of the second insulating separation pattern  240  may have a curved shape. 
     The second barrier pattern  232  and the second conductive pattern  234  may extend toward a region below the first portion  241  and may be partially between the first portion  241  and the first insulating separation pattern  160 . 
     The second barrier pattern  232  may include a first portion  232   a  on the ohmic contact layer OL and a second portion  232   b , which is connected to the first portion  232   a  and extends to a region on the first insulating separation pattern  160 . The second portion  232   b  of the second barrier pattern  232  may cover a portion of a side surface of the second portion  242 . The second portion  232   b  of the second barrier pattern  232  may be between the first portion  241  and the first insulating separation pattern  160 . 
       FIGS.  5 A,  6 A,  7 A,  8 A,  11 A,  13 A, and  15 A  are plan views of stages in a method of fabricating a semiconductor device, according to an embodiment.  FIGS.  5 B,  6 B,  7 B,  8 B,  9 ,  10 ,  11 B,  12 A,  13 B,  14 A, and  15 B  are sectional views, each of which is taken along a line I-I′ of a corresponding one of  FIGS.  5 A,  6 A,  7 A,  8 A,  11 A,  13 A, and  15 A  to illustrate stages in a method of fabricating a semiconductor device according to an embodiment.  FIGS.  5 C,  6 C,  12 B,  13 C,  14 B, and  15 C  are sectional views, each of which is taken along a line of a corresponding one of  FIGS.  5 A,  6 A,  7 A,  8 A,  11 A,  13 A , and  15 A to illustrate stages in a method of fabricating a semiconductor device according to an embodiment. 
     Hereinafter, a method of fabricating a semiconductor device according to an embodiment will be described in more detail with reference to  FIGS.  5 A to  15 C . 
     Referring to  FIGS.  5 A,  5 B, and  5 C , a device isolation pattern  110  may be formed on a substrate  100 . The device isolation pattern  110  may be formed to define active portions ACT. The formation of the device isolation pattern  110  may include etching a portion of the substrate  100  to form a device isolation trench and filling the device isolation trench with an insulating material. 
     Thereafter, the active portions ACT of the substrate  100  and the device isolation pattern  110  may be patterned to form grooves. A gate dielectric layer  125  may be formed to conformally cover the grooves. Next, a gate conductive layer may be formed to fill the grooves, and then, an etch-back process may be performed on the gate conductive layer to form word lines WL. Next, word line capping patterns  120  may be formed on the word lines WL to fill remaining portions of the grooves. 
     First and second impurity regions  1   a  and  1   b  may be formed in the active portions ACT by injecting impurities into the active portions ACT using the device isolation pattern  110  and the word line capping patterns  120  as a mask or using an additional ion injection mask. 
     Referring to  FIGS.  6 A,  6 B, and  6 C , an upper portion of the device isolation pattern  110  may be selectively removed. A portion of the gate dielectric layer  125  may also be removed during this process. The process of selectively and partially removing the device isolation pattern  110  may be performed using a wet etching process. Accordingly, side surfaces of the active portions ACT may be partially exposed to the outside. In an implementation, the process of selectively removing the upper portion of the device isolation pattern  110  may be omitted. 
     Thereafter, preliminary pads pXP may be formed on the active portions ACT. The formation of the preliminary pads pXP may include forming a pad conductive layer on the substrate  100  and patterning the pad conductive layer. In an implementation, the formation of the pad conductive layer may include forming a poly-silicon layer and injecting impurities into the poly-silicon layer. In an implementation, the poly-silicon layer may be doped in situ when the poly-silicon layer for the pad conductive layer is formed. 
     In the case where the upper portion of the device isolation pattern  110  is selectively removed, a portion of each of the preliminary pads pXP may extend into a region lower than a top surface of each of the active portions ACT. First insulating separation patterns  160  may be formed to fill spaces between the preliminary pads pXP. 
     Referring to  FIGS.  7 A and  7 B , a first opening OH 1  may be formed on the first impurity region  1   a  of each of the active portions ACT. The first opening OH 1  may be formed by etching the first insulating separation patterns  160  and the preliminary pads pXP (e.g., of  FIG.  6 B ) on the active portions ACT. In an implementation, the first impurity region  1   a  may be partially etched by the etching process, and in this case, a level of a top surface of the first impurity region  1   a  may be lowered. Portions of the preliminary pads pXP, which are left after the formation of the first opening OH 1 , may form first pads XP. 
     The first opening OH 1  may be formed to expose a side surface of each of the first pads XP, top and side surfaces of the device isolation pattern  110 , and a top surface of the first impurity region  1   a  of each of the active portions ACT. 
     Referring to  FIGS.  8 A and  8 B , a first contact insulating layer  141  may be formed to cover an inner side surface of the first opening OH 1 , a second contact insulating layer  143  may be formed on a side surface the first contact insulating layer  141 , and a first contact DC may be formed to fill a remaining space of the first opening OH 1  provided with the first and second contact insulating layers  141  and  143 . The first contact insulating layer  141  may extend from the inner side surface of the first opening OH 1  to cover top surfaces of the first pads XP and top surfaces of the first insulating separation patterns  160 . In addition, the first contact insulating layer  141  may include a portion that extends from the inner side surface of the first opening OH 1  to cover at least a portion of a bottom surface of the first opening OH 1 . The first contact DC may be in contact with the first impurity region  1   a  of each of the active portions ACT. The first and second contact insulating layers  141  and  143  may be formed of different insulating materials from each other. The first contact DC may be formed of or include doped poly silicon. 
     Bit lines BL may be formed to cross the active portions ACT in the second direction D 2  and to be in contact with the first contact DC, and bit line capping patterns  215  may be formed on the bit lines BL, respectively. Each of the bit lines BL may include a first barrier pattern  211  and a first conductive pattern  213 , which are sequentially stacked on the first contact insulating layer  141 . The formation of the bit lines BL and the bit line capping patterns  215  may include sequentially forming a first barrier layer, a first conductive layer, and a bit line capping layer on the first contact DC and the first contact insulating layer  141 , forming a mask pattern on the bit line capping layer, patterning the first barrier layer, the first conductive layer, and the bit line capping layer using the mask pattern as an etch mask, and removing the mask pattern. 
     Referring to  FIGS.  8 B and  9   , the first contact insulating layer  141  on the first pads XP may be removed. Next, a first recess portion RC 1  may be formed by partially etching the first and second contact insulating layers  141  and  143  and the first contact DC in the first opening OH 1 . First and second contact insulating patterns  142  and  144  constituting a contact insulating structure  140  may be respectively formed as a result of the partially etching of the first and second contact insulating layers  141  and  143 . The first recess portion RC 1  may be formed to expose a side surface of each of the first pads XP, a top surface of the contact insulating structure  140 , and a side surface of the first contact DC. 
     Referring to  FIG.  10   , a gapfill insulating structure  150  may be formed to fill the first recess portion RC 1 . The formation of the gapfill insulating structure  150  may include forming a first insulating gapfill layer to conformally cover the first recess portion RC 1 , forming a second insulating gapfill layer on the first insulating gapfill layer (e.g., using a deposition process) to fill the first recess portion RC 1 , and etching the first and second insulating gapfill layers to be locally left in the first recess portion RC 1 . As a result of the etching of the first and second insulating gapfill layers, first and second gapfill insulating patterns  151  and  152  may be formed in the first recess portion RC 1 . After the etching of the first and second insulating gapfill layers, portions of the first contact insulating layer  141  may be left between the bit lines BL and the first insulating separation patterns  160 , and such left portions may form buffer insulating patterns  201 . 
     Referring to  FIGS.  11 A and  11 B , preliminary bit line spacers pSP may be formed to cover the side surfaces of the bit lines BL and the side surfaces of the bit line capping patterns  215 . The formation of the preliminary bit line spacers pSP may include sequentially forming first to third spacers  221 ,  223 , and  225  on the side surfaces of the bit lines BL and the side surfaces of the bit line capping patterns  215 . Adjacent ones of the first to third spacers  221 ,  223 , and  225  may be formed of or include different insulating materials from each other. In an implementation, the second spacer  223  may be formed of or include an insulating material having an etch selectivity with respect to the first and third spacer  221  and  225 . The first spacer  221  may have a bottom surface that is in contact with the first gapfill insulating pattern  151  and each of the buffer insulating patterns  201 . The bottom surfaces of the second and third spacers  223  and  225  may be in contact with the top surface of each of the first pads XP. 
     Referring to  FIGS.  12 A and  12 B , second recess portions RC 2  may be formed by partially etching the first pads XP and the gapfill insulating structures  150 . Next, an ohmic contact layer OL may be formed in an upper portion of the first pad XP exposed by the second recess portion RC 2 . The ohmic contact layer OL may be formed of or include a metal silicide (e.g., cobalt silicide). 
     Referring to  FIGS.  13 A,  13 B, and  13 C , a second barrier layer  231  and a second conductive layer  233  may be formed to fill a space between the second recess portion RC 2  and the bit lines BL. The second barrier layer  231  may cover a top surface of the ohmic contact layer OL, a top surface of the gapfill insulating structure  150 , top and side surfaces of the third spacer  225 , top surfaces of the first and second spacers  221  and  223 , and a top surface of each of the bit line capping patterns  215 . The second conductive layer  233  may be formed on the second barrier layer  231  and may fully fill the space between the second recess portion RC 2  and the bit lines BL. In an implementation, the second conductive layer  233  may be formed to have a top surface, which is located at a level higher than the uppermost surface of the second barrier layer  231 . 
     Thereafter, second openings OH 2  may be formed between the bit lines BL and on regions, which are overlapped with the word lines WL in a third direction D 3  (i.e., vertically). The formation of the second openings OH 2  may include forming a mask pattern on the second conductive layer  233  and etching the second conductive layer  233 , the second barrier layer  231 , and at least a portion of each of the first insulating separation patterns  160  using the mask pattern as an etch mask. A top surface of each of the first insulating separation patterns  160 , side surfaces of the second barrier layer  231 , and side surfaces of the second conductive layer  233  may be exposed to the outside through the second openings OH 2 . 
     Referring to  FIGS.  13 B,  13 C,  14 A, and  14 B , a portion of the second barrier layer  231 , which is exposed through the second openings OH 2 , may be selectively removed to form an empty space ES. In an implementation, a portion of the second barrier layer  231 , which is located at a level higher the bottom surfaces of the bit lines BL and the bottom surfaces of the preliminary bit line spacers pSP, may be selectively removed. A remaining portion of the second barrier layer  231 , which is not removed by the selective removal process, may form a second barrier pattern  232 . In addition, a planarization process may be performed to remove an upper portion of the second conductive layer  233 , and a remaining portion of the second conductive layer  233 , which is not removed by the planarization process, may form a second conductive pattern  234 . The second barrier pattern  232  and the second conductive pattern  234  may form a second contact BC. The empty space ES may extend from the top surface of the second barrier pattern  232  along the side surface of the second conductive pattern  234 , when viewed in the sectional view of  FIG.  14 A . In addition, the empty space ES may include a space, which is recessed inward from the side surface of the second conductive pattern  234 , when viewed in the sectional view of  FIG.  14 B . 
     Referring to  FIGS.  14 A,  14 B,  15 A,  15 B, and  15 C , second insulating separation patterns  240  may be formed to fill the second openings OH 2 . A planarization process may be performed on the second insulating separation patterns  240 , and in this case, the second insulating separation patterns  240  may be formed to have top surfaces that are substantially coplanar with the top surfaces of the second contacts BC. 
     When the second insulating separation patterns  240  are formed, a fourth spacer  227  may also be formed to fill the empty space ES. The fourth spacer  227  may cover the side and top surfaces of the third spacer  225 , the top surfaces of the first and second spacers  221  and  223 , and the top surface of each of the bit line capping patterns  215 . The first to fourth spacers  221 ,  223 ,  225 , and  227  may constitute the bit line spacers SP that are in contact with the second contacts BC. In addition, protruding portions  240   p  of each of the second insulating separation patterns  240  may be formed to fill portions of the empty space ES, which are recessed inward from the side surface of the second conductive pattern  234 . 
     Referring back to  FIGS.  1 A,  1 B, and  1 C , second pads LP may be formed on the second contacts BC, respectively, and third insulating separation patterns LPS may be formed between the second pads LP. In an implementation, a third barrier layer and a third conductive layer may be sequentially formed on the second contacts BC and the second insulating separation patterns  240 . Here, the third insulating separation pattern LPS may be formed to penetrate the third barrier layer and the third conductive layer, and as a result, the second pad LP including a third barrier pattern  301  and a third conductive pattern  303  may be formed. Thereafter, data storage patterns DSP may be formed on the second pads LP, respectively. 
     By way of summation and review, to increase the integration density of the semiconductor device, linewidths of patterns constituting the semiconductor device may be reduced. Novel and expensive exposure technologies may be used to reduce the linewidths of the patterns, and it may be difficult to increase the integration density of the semiconductor device. Recently, a variety of new technologies are being studied to increase an integration density of a semiconductor memory device. 
     In a semiconductor device according to an embodiment, a second contact (e.g., a storage node contact) may include a second barrier pattern which is locally provided at a level lower than bottom surfaces of bit lines. In this case, it may be possible to reduce a parasitic capacitance between the bit lines, without a reduction in a contact area of the second contact and a first pad, and thereby to improve electrical characteristics and reliability of the semiconductor device. 
     In a method of fabricating a semiconductor device according to an embodiment, second insulating separation patterns (e.g., pillar-shaped insulating patterns which are between the bit lines and on a region overlapped with word lines) may be formed after the formation of the second contacts. Accordingly, it may be possible to prevent or suppress a bridge pattern (e.g., a short circuit) from being formed between the second contacts and thereby to improve the electrical characteristics and reliability of the semiconductor device. 
     One or more embodiments may provide a semiconductor device with improved electrical characteristics and reliability. 
     Example embodiments have been disclosed herein, and although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purpose of limitation. In some instances, as would be apparent to one of ordinary skill in the art as of the filing of the present application, features, characteristics, and/or elements described in connection with a particular embodiment may be used singly or in combination with features, characteristics, and/or elements described in connection with other embodiments unless otherwise specifically indicated. Accordingly, it will be understood by those of skill in the art that various changes in form and details may be made without departing from the spirit and scope of the present invention as set forth in the following claims.