Patent Publication Number: US-2006001475-A1

Title: Class-AB beta helper to reduce effects of mirror perturbation

Description:
FIELD OF THE INVENTION  
      The present invention relates generally to a preamp writer for a hard disk drive (HDD), and more particularly to stabilizing a write current mirror feeding an H-bridge driving a write head.  
     BACKGROUND OF THE INVENTION  
      In preamp writers for disk drives it has been an ongoing problem to stabilize a write current mirror feeding an H-bridge that drives a write current to a write head. The H-bridge switches high currents to an inductive load, and so the voltage excursions are high. These perturbations wreak havoc on the write current mirror which accepts a divided-down write current (typically 10:1 or 20:1) and which attempts to provide a stable output current at the H-switch.  
      Traditionally, this write current mirror has had a normal beta-helper transistor removed in an attempt to increase write current stability and immunity to the large output perturbations. Removing the beta-helper transistor, however, results in mirror inaccuracy which must normally be compensated for in more complex circuitry which has typically suffered from less accuracy than desired.  
       FIG. 1  shows a traditional write current mirror circuit  10  that lacks a beta helper transistor. Transistor Q 10  is an input transistor, having a collector-base short instead of a beta helper transistor thereacross. Thus, the base currents of input transistor Q 10  and output transistor Q 13  understandably contribute error to the mirror current accuracy. This is especially true with high ratio current mirrors, as circuit  10  which has a 1:20 ratio. Transistors Q 11 , MN 7 , Q 12 , MP 1  and MP 2  are used to reduce this base current error, although this technique generally suffers from considerable inaccuracy due to Early effects and transistor matching difficulties. Transistor Q 13  supplies the mirrored write current, which is switched on and off by transistor MN 8  (shown here always on).  
       FIG. 2  shows a simplified schematic of a normal mirror circuit  20  having a beta helper transistor Q 2 B. Capacitor C 1  is provided to insure AC stability of this mirror circuit  20 , but this beta helper transistor Q 2 B contributes to the time it takes for the mirror circuit  20  to recover from severe perturbations.  
       FIG. 3  shows the waveforms associated with the standard beta helper mirror circuit  20  of  FIG. 2 . Curve  22  is the voltage applied at the mirror output, transistor Q 3 &#39;s collector, which is not untypical of what is seen in a write driver of a H-switch. Curve  24  is the voltage at the bases of transistors Q 1  and Q 3 . When the voltage at transistor Q 3 &#39;s collector swings high at about 1 ns, this base voltage tends to follow as induced by parasitic capacitances and stored charge. As the base voltage of transistors Q 1  and Q 3  rises, transistor Q 2 B, the beta helper, turns off, allowing transistor Q 1  to come into saturation. Curve  26  is the voltage at transistor Q 1 &#39;s collector, and dips dramatically until the voltage at the bases of transistors Q 1  and Q 3  recovers to its original voltage. In the meantime, the current output of the mirror circuit current at transistor Q 3 &#39;s collector, shown as curve  28 , has varied from its quiescent 40 mA up to 80 mA and down to about 20 mA, and taking over 5 ns to recover. This output current  28  is completely unacceptable in a write driver that should be operating at above 1 Gb/s.  
     SUMMARY OF THE INVENTION  
      The present invention achieves technical advantages as a write head mirror circuit having a Class-AB beta helper providing immunity to severe perturbations of mirror current at the mirror output. The typical single transistor beta helper is replaced with a Class-AB beta helper, advantageously preventing the beta helper from turning off, thereby providing output mirror accuracy.  
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       FIG. 1  is a schematic of a prior art write current mirror circuit without a beta helper transistor;  
       FIG. 2  is a schematic of a prior art write current mirror circuit with a beta helper transistor;  
       FIG. 3  is a graph of currents and voltages of the circuit of  FIG. 2  showing the dramatic swing of mirror current;  
       FIG. 4  is a schematic of one embodiment of the invention being a current mirror circuit with a Class-AB beta helper; and  
       FIG. 5  is a graph of voltages and current of the circuit of  FIG. 4  showing the improved generally constant mirror current.  
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT  
      An improved write current mirror circuit  30  according to one embodiment of the invention having a Class-AB beta helper  32  is shown in  FIG. 4 . In addition to transistor Q 7 , the normal beta helper, a PNP transistor Q 8  is added in parallel with transistor Q 7 . The base connections of transistors Q 7  and Q 8  are offset by the voltage developed across the transistors Q 4  and Q 5  in order to set up the correct bias condition. Transistors Q 4  and Q 5 , with current source transistor MN 3 , provide the quiescent bias for transistors Q 7  and Q 8 , comprising the beta helper transistors, advantageously arranged in a Class-AB configuration.  
       FIG. 5  shows the waveforms associated with the Class-AB beta helper mirror  32 , comprising transistors Q 7  and Q 8 , with the same perturbation as depicted for the normal beta helper mirror circuit  20  in  FIGS. 2 and 3 . One advantageous difference is that the input device, transistor Q 6 , does not saturate, as shown by curve  34 , because PNP beta helper transistor Q 8  prevents its base voltage from rising nearly as much. The output mirror current Iw, shown as curve  38 , has nearly as large a variation initially. This can&#39;t be avoided due to the fast excursions of output transistor Q 9 &#39;s collector voltage. However, it can be seen by curve  38 , that advantageously, the mirror current Iw undershoot is far less severe and it settles back in about 1 ns now, which is acceptable for a driver operating at above 1 Gb/s.  
      Though the invention has been described with respect to a specific preferred embodiment, many variations and modifications will become apparent to those skilled in the art upon reading the present application. It is therefore the intention that the appended claims be interpreted as broadly as possible in view of the prior art to include all such variations and modifications.