Patent Publication Number: US-2023141481-A1

Title: Method of forming semiconductor structure and semiconductor structure

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This is a continuation of International Application No. PCT/CN2021/135640, filed on Dec. 6, 2021, which claims the priority to Chinese Patent Application No. 202111060919.6, titled “METHOD OF FORMING SEMICONDUCTOR STRUCTURE AND SEMICONDUCTOR STRUCTURE” and filed on Sep. 10, 2021. The entire contents of International Application No. PCT/CN2021/135640 and Chinese Patent Application No. 202111060919.6 are incorporated herein by reference. 
    
    
     TECHNICAL FIELD 
     The present disclosure relates to, but is not limited to, a method of forming a semiconductor structure and a semiconductor structure. 
     BACKGROUND 
     An integrated circuit (IC) packaging technology is a technology that a plurality of chips are stacked and interconnected by through silicon vias (TSVs). Vertically interconnected TSV structures are separately formed on the plurality of chips and electrical interconnection between different chips is achieved through a subsequent redistribution layer (RDL). 
     An existing TSV technology usually integrates integrated passive devices (IPDs) on a semiconductor substrate. In the technology for the IPDs, resistors, capacitors, and inductors in a circuit are integrated into one chip. However, as the IC continues to become more integrated, a size of the IC is reduced, and a characteristic size of the IPD is also reduced. The size reduction of the IPD leads to a decrease in a quality factor of an inductance in the IPD. Consequently, it is difficult for the inductance generated by the IPD to meet an application requirement of the IC. 
     SUMMARY 
     An overview of the subject matter detailed in the present disclosure is provided below, which is not intended to limit the protection scope of the claims. 
     The present disclosure provides a method of forming a semiconductor structure and a semiconductor structure. 
     A first aspect of the present disclosure provides a method of forming a semiconductor structure. The method of forming a semiconductor structure includes: 
     providing an initial structure, where the initial structure includes a substrate and a dielectric layer provided on the substrate, the dielectric layer is provided on a first side of the substrate, and a bottom surface of the dielectric layer is connected to a first side surface of the substrate; 
     forming a conductive trench, where the conductive trench extends to a second side surface of the substrate from a top surface of the dielectric layer, the conductive trench exposes part of the dielectric layer and part of the substrate, and a distance between a bottom surface of the conductive trench and the second side surface of the substrate is a first spacing; 
     forming a conductive hole, where the conductive hole extends to the second side surface of the substrate from the top surface of the dielectric layer; 
     forming a conductive pillar, where the conductive pillar fills the conductive hole; 
     forming an inductor structure, where the inductor structure fills the conductive trench, and projection of the inductor structure on the substrate is provided as a spiral structure that uses projection of the conductive pillar on the substrate as an inductor center and that surrounds the inductor center; and 
     forming an inductor lead-out structure, where the inductor lead-out structure covers the conductive pillar and the inductor structure that are exposed by the top surface of the dielectric layer. 
     A second aspect of the present disclosure provides a semiconductor structure, where the semiconductor structure includes: 
     a substrate, where the substrate includes a first side and a second side; 
     a dielectric layer, where the dielectric layer is provided on the first side of the substrate, and a bottom surface of the dielectric layer is connected to a first side surface of the substrate; 
     a conductive trench, where the conductive trench extends to a second side surface of the substrate from a top surface of the dielectric layer, the conductive trench exposes part of the dielectric layer and part of the substrate, and a distance between a bottom surface of the conductive trench and the second side surface of the substrate is a first spacing; 
     a conductive hole, where the conductive hole extends to the second side surface of the substrate from the top surface of the dielectric layer; 
     a conductive pillar, where the conductive pillar fills the conductive hole; 
     an inductor structure, where the inductor structure fills the conductive trench, and projection of the inductor structure on the substrate is provided as a spiral structure that uses projection of the conductive pillar on the substrate as an inductor center and that surrounds the inductor center; and 
     an inductor lead-out structure, where the inductor lead-out structure covers the conductive pillar and the inductor structure that are exposed by the top surface of the dielectric layer. 
     Other aspects of the present disclosure are understandable upon reading and understanding of the accompanying drawings and detailed description. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The accompanying drawings incorporated into the specification and constituting part of the specification illustrate the embodiments of the present disclosure, and are used together with the description to explain the principles of the embodiments of the present disclosure. In these accompanying drawings, similar reference numerals represent similar elements. The accompanying drawings in the following description illustrate some rather than all of the embodiments of the present disclosure. Those skilled in the art may obtain other accompanying drawings based on these accompanying drawings without creative efforts.  FIG.  1    is a flowchart of a method of forming a semiconductor structure according to an exemplary embodiment; 
         FIG.  2    is a flowchart of a method of forming a semiconductor structure according to an exemplary embodiment; 
         FIG.  3    is a flowchart of a method of forming a semiconductor structure according to an exemplary embodiment; 
         FIG.  4    is a flowchart of forming an inductor lead-out structure in a method of forming a semiconductor structure according to an exemplary embodiment; 
         FIG.  5    is a schematic diagram of forming a first mask layer on an initial structure in a method of forming a semiconductor structure according to an exemplary embodiment; 
         FIG.  6    is a schematic diagram of projection, of a first pattern and a second pattern that are formed, on a substrate in a method of forming a semiconductor structure according to an exemplary embodiment; 
         FIG.  7    is a schematic diagram of forming a conductive trench and an initial conductive hole in a method of forming a semiconductor structure according to an exemplary embodiment; 
         FIG.  8    is a schematic diagram of a shielding layer in a method of forming a semiconductor structure according to an exemplary embodiment; 
         FIG.  9    is a schematic diagram of forming a conductive hole in a method of forming a semiconductor structure according to an exemplary embodiment; 
         FIG.  10    is a schematic diagram of forming a first mask layer on an initial structure in a method of forming a semiconductor structure according to an exemplary embodiment; 
         FIG.  11    is a schematic diagram of forming a conductive trench in a method of forming a semiconductor structure according to an exemplary embodiment; 
         FIG.  12    is a schematic diagram of forming a second mask layer on an initial structure in a method of forming a semiconductor structure according to an exemplary embodiment; 
         FIG.  13    is a schematic diagram of projection, of a first pattern and a third pattern that are formed, on a substrate in a method of forming a semiconductor structure according to an exemplary embodiment; 
         FIG.  14    is a schematic diagram of forming a conductive hole in a method of forming a semiconductor structure according to an exemplary embodiment; 
         FIG.  15    is a schematic diagram of forming a first barrier layer and a second barrier layer in a method of forming a semiconductor structure according to an exemplary embodiment; 
         FIG.  16    is a schematic diagram of forming a conductive pillar and an inductor structure in a method of forming a semiconductor structure according to an exemplary embodiment; 
         FIG.  17    is a schematic diagram of projection, of a conductive pillar and an inductor structure, formed on a substrate in a method of forming a semiconductor structure according to an exemplary embodiment; 
         FIG.  18    is a schematic diagram of forming a first metal pad and a second metal pad in a method of forming a semiconductor structure according to an exemplary embodiment; 
         FIG.  19    is a schematic diagram of forming a first inductor lead-out portion and a second inductor lead-out portion in a method of forming a semiconductor structure according to an exemplary embodiment; and 
         FIG.  20    is a schematic diagram of forming a redistribution layer in a method of forming a semiconductor structure according to an exemplary embodiment. 
     
    
    
     DETAILED DESCRIPTION 
     To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the following clearly and completely describes the technical solutions in the embodiments of the present disclosure with reference to the accompanying drawings in the embodiments of the present disclosure. Apparently, the described embodiments are some rather than all of the embodiments of the present disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of the present disclosure without creative efforts should fall within the protection scope of the present disclosure. It should be noted that the embodiments in the present disclosure and features in the embodiments may be combined with each other in a non-conflicting manner. 
     An exemplary embodiment of the present disclosure provides a method of forming a semiconductor structure, as shown in  FIG.  1   .  FIG.  1    is a flowchart of a method of forming a semiconductor structure according to an exemplary embodiment of the present disclosure.  FIG.  5    to  FIG.  20    are schematic diagrams of various stages of the method of forming a semiconductor structure. The method of forming a semiconductor structure is described below with reference to  FIG.  5    to  FIG.  20   . 
     The semiconductor structure is not limited in this embodiment. That the semiconductor structure is a dynamic random access memory (DRAM) is used as an example below for description, but this embodiment is not limited thereto. Alternatively, the semiconductor structure in this embodiment may be other structures. 
     As shown in  FIG.  1   , an exemplary embodiment of the present disclosure provides a method of forming a semiconductor structure, including the following steps: 
     Step S 110 : Provide an initial structure, where the initial structure includes a substrate and a dielectric layer provided on the substrate, the dielectric layer is provided on a first side of the substrate, and a bottom surface of the dielectric layer is connected to a first side surface of the substrate. 
     As shown in  FIG.  5   , the substrate  110  includes a semiconductor material. The semiconductor material may be one or more of silicon, germanium, a silicon-germanium compound, and a silicon-carbon compound. The substrate  110  may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate. 
     The dielectric layer  120  may include a dielectric material. The dielectric layer  120  may include silicon oxide. 
     In this embodiment, an isolation layer  130  may further be provided between the substrate  110  and the dielectric layer  120 , and the isolation layer  130  is provided to isolate the substrate  110  from being in direct contact with the dielectric layer  120 . The isolation layer  130  may include an insulating material. The isolation layer  130  may include insulating materials such as silicon nitride and silicon oxide. 
     Step S 120 : Form a conductive trench, where the conductive trench extends to a second side surface of the substrate from a top surface of the dielectric layer, the conductive trench exposes part of the dielectric layer and part of the substrate, and a distance between a bottom surface of the conductive trench and the second side surface of the substrate is a first spacing. 
     As shown in  FIG.  7   , referring to  FIG.  5   , the conductive trench  140  may be formed by removing part of the dielectric layer  120  and part of the substrate  110  through etching by a dry etching or wet etching process. The conductive trench  140  extends to a second side surface of the substrate  110  from a top surface of the dielectric layer  120 , and a distance between a bottom surface of the conductive trench  140  and the second side surface of the substrate  110  is a first spacing L 1 . 
     The thickness of an initial structure  100  is 3 μm to 10 μm. The thickness of the dielectric layer  120  is 0.05 μm to 0.3 μm. The depth of the conductive trench  140  is 1 μm to 10 μm. The distance between the bottom surface of the conductive trench  140  and the second side surface of the substrate  110  is the first spacing L 1  greater than 1 μm. 
     Step S 130 : Form a conductive hole, where the conductive hole extends to the second side surface of the substrate from the top surface of the dielectric layer. 
     As shown in  FIG.  9   , referring to  FIG.  7   , the conductive hole  150  may be formed by removing part of the dielectric layer  120  and part of the substrate  110  through etching, and the conductive hole  150  runs through the initial structure  100 . In this embodiment, the conductive hole  150  is provided in the middle of the conductive trench  140  and the conductive hole  150  is surrounded by the conductive trench  140 . Projection of the conductive trench  140  formed on the substrate  110  is a spiral pattern that uses projection of the conductive hole  150  formed on the substrate  110  as a center. 
     Step S 140 : Form a conductive pillar, where the conductive pillar fills the conductive hole. 
     Forming a conductive pillar  210  includes: As shown in  FIG.  15   , referring to  FIG.  9   , a first barrier layer  211  may be formed by depositing tantalum (Ta) or a tantalum compound by using an atomic layer deposition (ALD) process, where the first barrier layer covers a sidewall of the conductive hole  150 . In this embodiment, a material of the first barrier layer  211  is Ta. As shown in  FIG.  16   , referring to  FIG.  15   , a conductive metal is deposited by using an electroplating process, a first conductive layer  212  is formed by the conductive metal by filling the conductive hole  150 , and the conductive pillar  210  is formed by the first barrier layer  211  and the first conductive layer  212 . In this embodiment, the conductive metal may be copper or a copper compound. 
     Step S 150 : Form an inductor structure, where the inductor structure fills the conductive trench, and projection of the inductor structure on the substrate is provided as a spiral structure that uses projection of the conductive pillar on the substrate as an inductor center and that surrounds the inductor center. 
     As shown in  FIG.  15    and  FIG.  16   , a process of forming the inductor structure  220  and a process of forming the conductive pillar  210  are approximately the same: forming a second barrier layer  221  covering the conductive trench  140  by depositing Ta or a tantalum compound, and forming a second conductive layer  222  by filling a conductive trench  140  by a conductive metal deposited by using an electroplating process. The second barrier layer  221  and the second conductive layer  222  form the inductor structure  220 . In this embodiment, the conductive metal may be copper or a copper compound. As shown in  FIG.  17   , in this embodiment, projection of the inductor structure  220  on the substrate  110  is provided as a spiral structure  220   a  that uses projection of the conductive pillar  210  on the substrate  110  as an inductor center and that surrounds the inductor center. 
     Step S 160 : Form an inductor lead-out structure, where the inductor lead-out structure covers the conductive pillar and the inductor structure that are exposed by the top surface of the dielectric layer. 
     Referring to  FIG.  18    and  FIG.  19   , the inductor lead-out structure  300  includes at least a first inductor lead-out portion  331  and a second inductor lead-out portion  332  that are connected to the inductor structure  220 , and the inductor structure  220  is connected to an external terminal by using the first inductor lead-out portion  331  and the second inductor lead-out portion  332 , such that when a current passes through the conductive pillar  210 , the inductor structure  220  is affected by the induced current to produce an inductance. 
     According to the method of forming a semiconductor structure in this embodiment, the inductor structure surrounding the conductive pillar and the inductor lead-out structure connected to the inductor structure are formed, such that an embedded inductor device with the conductive pillar as a magnetic core and the inductor structure as a winding coil around the conductive pillar is formed in the semiconductor structure. The conductive pillar of the semiconductor structure formed in this embodiment is not only used as an TSV structure used for interconnection, but also used as the magnetic core of the inductor device, such that when the conductive pillar is electrically connected to another interconnection structure, and a current passes through the conductive pillar, the inductor structure induces the current in the conductive pillar to produce an inductance. The semiconductor structure formed in this embodiment can produce an inductance when turned on, to meet the demand for inductance, without integrating passive devices in the semiconductor structure. This can further reduce the size of the semiconductor structure. 
     An exemplary embodiment of the present disclosure provides a method of forming a semiconductor structure, as shown in  FIG.  2   .  FIG.  2    is a flowchart of a method of forming a semiconductor structure according to an exemplary embodiment of the present disclosure. 
     As shown in  FIG.  2   , an exemplary embodiment of the present disclosure provides a method of forming a semiconductor structure, including the following steps: 
     Step S 210 : Provide an initial structure, where the initial structure includes a substrate and a dielectric layer provided on the substrate, the dielectric layer is provided on a first side surface of the substrate, and a bottom surface of the dielectric layer is connected to the first side surface of the substrate. 
     Step S 220 : Form a first mask layer on the top surface of the dielectric layer, where the first mask layer includes a first pattern and a second pattern. 
     As shown in  FIG.  5   , a first mask layer  160  includes both a first pattern  161   a  and a second pattern  162   a,  the first pattern  161   a  exposes part of a top surface of a dielectric layer  120 , and the second pattern  162   a  exposes part of the top surface of the dielectric layer  120 . As shown in  FIG.  6   , projection of the first pattern  161   a  on the substrate  110  is provided as a spiral pattern that uses projection of the second pattern  162   a  on the substrate  110  as a spiral center and that is provided around the spiral center. In this embodiment, the spiral pattern formed by the projection of the first pattern  161   a  is provided to include a plurality of annular patterns, and the plurality of annular patterns are provided outwardly in sequence around the spiral center. 
     Step S 230 : Remove part of the initial structure according to the first pattern and the second pattern to form a conductive trench and an initial conductive hole. 
     As shown in  FIG.  7   , referring to  FIG.  5    and  FIG.  6   , the dielectric layer  120  and the substrate  110  that are exposed by the first pattern  161   a  and the second pattern  162   a  are removed by using a dry etching or wet etching process, and a conductive trench  140  and an initial conductive hole  151  are formed after the etching is performed to a predetermined depth. The conductive trench  140  is provided by using the initial conductive hole  151  as a center and surrounding the initial conductive hole  151 , and distances between bottom surfaces of the conductive trench  140  and the initial conductive hole  151  and a second side surface of the substrate  110  are a first spacing L 1 . 
     Step S 240 : Remove the substrate exposed by the initial conductive hole, to form the conductive hole. 
     As shown in  FIG.  8   , referring to  FIG.  7   , a shielding layer  170  is formed. The shielding layer  170  covers top surfaces of the conductive trench  140  and the dielectric layer  120 . In this embodiment, a material of the shielding layer  170  is a photolithography resistant reagent. Then, the substrate  110  exposed by the initial conductive hole  151  is removed by using a photolithography process, to form a conductive hole  150  running through an initial structure  100 . 
     Step S 250 : Form a conductive pillar, where the conductive pillar fills the conductive hole. 
     Step S 260 : Form an inductor structure, where the inductor structure fills the conductive trench, and projection of the inductor structure on the substrate is provided as a spiral structure that uses projection of the conductive pillar on the substrate as an inductor center and that surrounds the inductor center. 
     Step S 270 : Form an inductor lead-out structure, where the inductor lead-out structure covers the conductive pillar and the inductor structure that are exposed by the top surface of the dielectric layer. 
     The method of forming step S 210  in this embodiment is implemented in the same manner as step S 110  in the foregoing embodiment, and step S 250  to step S 270  are implemented in the same manner as step S 140  to step S 160  in the foregoing embodiment; details are not described again herein. 
     In the semiconductor structure formed in this embodiment, as shown in  FIG.  16   , referring to  FIG.  17   , an inductor structure  220  is provided around a conductive pillar  210 , and projection of the inductor structure  220  formed on the substrate  110  is provided as a spiral structure  220   a  that uses projection of the conductive pillar  210  on the substrate  110  as an inductor center and that surrounds the inductor center. In this embodiment, the spiral structure  220   a  is a spiral annular structure surrounding the inductor center and away from the inductor center along a radial direction. 
     As shown in  FIG.  17   , the spiral structure  220   a  formed by the projection of the inductor structure  220  on the substrate  110  includes a starting end  2201  close to the inductor center and a termination end  2202  away from the inductor center, and the spiral structure  220   a  is a spiral annular structure formed by radially outwardly surrounding the inductor center and extending to the termination end  2202  from the starting end  2201 . As shown in  FIG.  18   , referring to  FIG.  19   , the inductor structure  220  surrounds the conductive pillar  210  for a plurality of circles in an outer circumference of the conductive pillar  210 , and the inductor structure may be connected to an external terminal by using an inductor lead-out structure  300 , such that when the conductive pillar  210  is turned on, the inductor structure  220  is affected by a current conducted in the conductive pillar  210  to produce an inductance. 
     In this embodiment, when the semiconductor structure is to be formed, the first pattern and the second pattern are patterned on the first mask layer, the projection of the first pattern on the substrate is provided as the spiral pattern that uses the projection of the second pattern on the substrate as the spiral center and that is provided around the spiral center, only one time of patterning on the first mask layer is required, and both the first pattern and the second pattern are patterned on the top surface of the dielectric layer, such that the patterning difficulty is reduced and the patterning accuracy is high. 
     An exemplary embodiment of the present disclosure provides a method of forming a semiconductor structure, as shown in  FIG.  3   .  FIG.  3    is a flowchart of a method of forming a semiconductor structure according to an exemplary embodiment of the present disclosure. 
     As shown in  FIG.  3   , an exemplary embodiment of the present disclosure provides a method of forming a semiconductor structure, including the following steps: 
     Step S 310 : Provide an initial structure, where the initial structure includes a substrate and a dielectric layer provided on the substrate, the dielectric layer is provided on a first side of the substrate, and a bottom surface of the dielectric layer is connected to a first side surface of the substrate. 
     Step S 320 : Form a first mask layer on a top surface of the dielectric layer, where the first mask layer includes a first pattern. 
     As shown in  FIG.  10   , a first mask layer  160  is formed on an initial structure  100 . The first mask layer  160  covers a top surface of a dielectric layer  120 , and the first mask layer  160  includes a first pattern  161   a.  Referring to  FIG.  13   , projection of the first pattern  161   a  formed on the substrate  110  is a spiral pattern. 
     Step S 330 : Remove part of the initial structure according to the first pattern to form a conductive trench. 
     As shown in  FIG.  11   , referring to  FIG.  10   , a conductive trench  140  is formed in the initial structure  100 . A distance between a bottom surface of the conductive trench  140  and a second side surface of the substrate is a first spacing L 1 . The implementation of forming the conductive trench  140  is the same as the implementation of forming the conductive trench  140  in step S 230  in the foregoing embodiment. 
     Step S 340 : Form a second mask layer on a second side surface of the substrate, where the second mask layer includes a third pattern, and the third pattern exposes part of the second side surface of the substrate. 
     As shown in  FIG.  12   , referring to  FIG.  11   , a second mask layer  180  is formed. The second mask layer  180  covers the second side surface of the substrate  110 . The second mask layer  180  is patterned according to projection of the conductive trench  140  formed on the substrate  110 , to form a third pattern  181   a  on the second mask layer  180 . The third pattern  181   a  exposes part of the second side surface of the substrate  110 . In this embodiment, a projection image of the conductive trench  140  formed on the substrate  110  is obtained through light, and the third pattern  181   a  is patterned according to the projection of the conductive trench  140  formed on the substrate  110 . As shown in  FIG.  13   , projection of the third pattern  181   a  formed on the substrate  110  is provided as a spiral center of the projection of the conductive trench  140  formed on the substrate  110 . As shown in  FIG.  13   , the spiral pattern formed by the projection of the first pattern  161   a  on the substrate  110  is provided to include a plurality of annular patterns, and the plurality of annular patterns are provided outwardly in sequence around the spiral center. 
     Step S 350 : Remove the substrate and the dielectric layer that are exposed by the third pattern, to form a conductive hole. 
     As shown in  FIG.  14   , referring to  FIG.  12    and  FIG.  13   , the substrate  110  exposed by the third pattern  181   a  is removed through etching by using a dry etching or wet etching process, to transfer the third pattern  181   a  onto the dielectric layer  120 , and the dielectric layer  120  is etched according to the third pattern  181   a,  to form a conductive hole  150  running through the substrate  110 . The conductive hole  150  is provided at a central position of the conductive trench  140 , and the conductive trench  140  uses the conductive hole  150  as a center and spirally surrounds the conductive hole  150  along a direction away from the conductive hole  150 . 
     Step S 360 : Form a conductive pillar, where the conductive pillar fills the conductive hole. 
     Step S 370 : Form an inductor structure, where the inductor structure fills the conductive trench, and projection of the inductor structure on the substrate is provided as a spiral structure that uses projection of the conductive pillar on the substrate as an inductor center and that surrounds the inductor center. 
     Step S 380 : Form an inductor lead-out structure, where the inductor lead-out structure covers the conductive pillar and the inductor structure that are exposed by the top surface of the dielectric layer. 
     The method of forming step S 310  in this embodiment is implemented in the same manner as step S 210  in the foregoing embodiment, and step S 360  to step S 380  are implemented in the same manner as step S 250  to step S 270  in the foregoing embodiment; details are not described again herein. 
     In this embodiment, when the semiconductor structure is formed, the first pattern is patterned on the first mask layer, the conductive trench is formed by etching the initial structure from the top surface of the dielectric layer to the bottom surface of the substrate according to the first pattern, then the second mask layer is formed on the second side surface of the substrate, the third pattern is patterned on the second mask layer according to the projection image of the conductive trench formed on the substrate, and the conductive hole is formed according to the third pattern, without forming a shielding layer for shielding the conductive trench, such that steps of forming and removing the shielding layer are reduced, and further a forming process of the semiconductor structure is simplified. 
     According to an exemplary embodiment of the present disclosure, this embodiment is a further description of step S 380  in the foregoing embodiment. 
     As shown in  FIG.  4   , the forming an inductor lead-out structure includes: 
     Step S 381 : Form a first metal pad, where the first metal pad is disposed on the top surface of the dielectric layer, and the first metal pad covers the conductive pillar exposed by the top surface of the dielectric layer. 
     Step S 382 : Form a second metal pad, where the second metal pad is disposed on the top surface of the dielectric layer, and the second metal pad covers the inductor structure exposed by the top surface of the dielectric layer. 
     Step S 381  and step S 382  may be simultaneously performed. A dielectric material is deposited on the top surface of the dielectric layer  120  to form an auxiliary layer, and the auxiliary layer is patterned by using a light development process and a dry etching or wet etching process, to form an auxiliary pattern on the auxiliary layer. Projection of the auxiliary pattern formed on the substrate  110  coincides with projection of the conductive pillar  210  and the inductor structure  220  formed on the substrate  110 . A conductive metal is deposited to fill the auxiliary pattern, so as to form the first metal pad  310  and the second metal pad  320 . Then, the auxiliary layer is removed. As shown in  FIG.  18   , the first metal pad  310  covers the conductive pillar  210  exposed by the top surface of the dielectric layer  120 , and the second metal pad  320  covers the inductor structure  220  exposed by the top surface of the dielectric layer  120 . In another embodiment of the present disclosure, alternatively, the first metal pad  310  and the second metal pad  320  may be separately formed. 
     Step S 383 : Form a first inductor lead-out portion, where the first inductor lead-out portion covers part of a top surface of the second metal pad. 
     Step S 384 : Form a second inductor lead-out portion, where the second inductor lead-out portion covers part of the top surface of the second metal pad. 
     Step S 383  and S 384  may be alternatively performed. As shown in  FIG.  19   , a first inductor lead-out portion  331  and a second inductor lead-out portion  332  are formed on a top surface of the second metal pad  320  through immersion tin soldering. In this embodiment, referring to  FIG.  17   , projection of the first inductor lead-out portion  331  formed on the substrate  110  is located at a starting end  2201  of a spiral structure  220   a;  projection of the second inductor lead-out portion  332  formed on the substrate  110  is located at a termination end  2202  of the spiral structure  220   a.  In another embodiment of the present disclosure, alternatively, the first inductor lead-out portion  331  and the second inductor lead-out portion  332  may be separately formed. 
     In the method of forming this embodiment, the first inductor lead-out portion is provided on an end of the inductor structure closest to the conductive pillar, the second inductor lead-out portion is provided on an end of the inductor structure farthest away from the conductive pillar, and the first inductor lead-out structure and the second inductor lead-out structure are oppositely provided. In the semiconductor structure formed in this embodiment, the first inductor lead-out portion and the second inductor lead-out portion may be connected to an external terminal, to form a complete inductor device. 
     According to an exemplary embodiment of the present disclosure, most of content of this embodiment is the same as that of the foregoing embodiment, and a difference lies in that, as shown in  FIG.  3   , a method of forming a semiconductor structure in this embodiment further includes: 
     Step S 390 : Form a redistribution layer, where the redistribution layer is provided on the second side surface of the substrate, and the redistribution layer covers the conductive pillar exposed by the second side surface of the substrate. 
     In this embodiment, forming a redistribution layer  400  includes: forming an insulating layer on the second side surface of the substrate  110 , patterning the insulating layer by using an exposure process, a development process, and a dry etching or wet etching process, forming a redistribution pattern on the insulating layer, where the redistribution pattern exposes part of the second side surface of the substrate  110 , and forming the redistribution layer  400  according to the redistribution pattern. As shown in  FIG.  20   , the redistribution layer  400  covers the conductive pillar  210  exposed by the second side surface of the substrate  110 . 
     In this embodiment, the redistribution layer electrically connected to the conductive pillar is formed on the second side surface of the substrate of the semiconductor structure, and an interconnection contact position of the semiconductor structure is changed by using the redistribution layer, such that the semiconductor structure can be adapt to different packaging forms. 
     An exemplary embodiment of the present disclosure provides a semiconductor structure. As shown in  FIG.  20   , referring to  FIG.  14   , the semiconductor structure includes: a substrate  110 , a dielectric layer  120  connected to the substrate  110 , and a conductive trench  140  and a conductive hole  150  that are provided on the dielectric layer  120  and the substrate  110 . The substrate  110  includes a first side and a second side, the dielectric layer  120  is provided on the first side of the substrate  110 , and a bottom surface of the dielectric layer  120  is connected to a first side surface of the substrate  110 . The conductive trench  140  extends to a second side surface of the substrate  110  from the top surface of the dielectric layer  120 , the conductive trench  140  exposes part of the dielectric layer  120  and part of the substrate  110 , and a distance between a bottom surface of the conductive trench  140  and the second side surface of the substrate  110  is a first spacing L 1 . The conductive hole  150  extends to the second side surface of the substrate  110  from the top surface of the dielectric layer  120 . The semiconductor structure further includes a conductive pillar  210  filling the conductive hole  150 , an inductor structure  220  filling the conductive trench  140 , and an inductor lead-out structure  300  covering the conductive pillar  210  and the inductor structure  220  that are exposed by the top surface of the dielectric layer  120 . As shown in  FIG.  17   , projection of the inductor structure  220  on the substrate  110  is provided as a spiral structure  220   a  that uses projection of the conductive pillar  210  on the substrate  110  as an inductor center and that surrounds the inductor center. 
     In the semiconductor structure in this embodiment, the inductor structure  220  spirally wound around the conductive pillar  210  is disposed around the conductive pillar  210 , and the inductor lead-out structure  300  connected to the inductor structure  220  is further disposed on the top surface of the dielectric layer  120 , such that the conductive pillar  210 , the inductor structure  220 , and the inductor lead-out structure  300  together form an inductor device with the conductive pillar  210  as a magnetic core and the inductor structure  220  as a winding coil around the conductive pillar  210 . 
     The conductive pillar  210  of the semiconductor structure in this embodiment is not only used as an TSV structure used for interconnection, but also used as the magnetic core of the inductor device, such that when the conductive pillar  210  is electrically connected to another interconnection structure, and a current passes through the conductive pillar  210 , the inductor structure  220  induces the current in the conductive pillar  210  to produce an inductance. The semiconductor structure in this embodiment does not need to be provided with an inductance through IPD. This can further reduce the size of the semiconductor structure. 
     According to an exemplary embodiment of the present disclosure, most of content of this embodiment is the same as that of the foregoing embodiment, and a difference lies in that, as shown in  FIG.  17   , the spiral structure  220   a  includes a plurality of spiral portions  2200   a  sequentially connected along a clockwise direction or a counterclockwise direction, and spacings between the plurality of spiral portions  2200   a  and the inductor center gradually increase according to a connection sequence. 
     The spiral structure  220   a  is an annular structure that surrounds the inductor center in a predetermined shape along the clockwise direction or the counterclockwise direction. The spiral structure  220   a  may rectangularly or circularly surround the inductor center along the clockwise direction or the counterclockwise direction. In this embodiment, the spiral structure  220   a  is an annular structure rectangularly surrounding the inductor center along the counterclockwise direction. The inductor structure  220  includes a multi-circle structure surrounding an outer circumference of the conductive pillar  210 , and when a current passes through the conductive pillar  210 , each circle of the inductor structure  220  surrounding the conductive pillar  210  is equivalent to one circle of coils surrounding the conductive pillar  210 . The inductor structure  220  and the conductive pillar  210  form an inductor device with the conductive pillar  210  as a magnetic core and the inductor structure  220  as an inductor coil around the magnetic core, and the inductor structure  220  is affected by an induced current of the magnetic core to produce an inductance. 
     According to an exemplary embodiment of the present disclosure, most of content of this embodiment is the same as that of the foregoing embodiment, and a difference lies in that, as shown in  FIG.  17   , the spiral structure  220   a  includes a starting end  2201  close to the inductor center and a termination end  2202  away from the inductor center, and the spiral structure  220   a  is provided to radially outwardly surround the inductor center and extend to the termination end from the starting end  2201 . 
     In this embodiment, a spacing between the starting end  2201  of the spiral structure  220   a  and the inductor center is a first distance L 2 ; spacings between the plurality of spiral portions  2200   a  and the inductor center are increased by the first distance L 2  in a stepped manner according to the connection sequence. 
     In this embodiment, the first distance L 2  is 0.2 μm to 1 μm. The first distance L 2  may be 0.3 μm, 0.4 μm, 0.5 μm, 0.6 μm, 0.7 μm, 0.8 μm, or 0.9 μm. 
     In this embodiment, a spacing between coils of the inductor structure  220  and a minimum distance between the inductor structure  220  and the conductive pillar  210  are provided to be 0.2 μm to 1 μm, which is less than a spacing in a current rule of designing a TSV structure, such that when the conductive pillar  210  is turned on, the inductor structure  220  is affected by a current of the conductive pillar  210  to produce a greater inductance. 
     According to an exemplary embodiment of the present disclosure, most of content of this embodiment is the same as that of the foregoing embodiment, and a difference lies in that, as shown in  FIG.  20   , referring to  FIG.  18    and  FIG.  19   , the inductor lead-out structure  300  includes: a first metal pad  310  and a second metal pad  320  that are disposed on the top surface of the dielectric layer  120 , and the first inductor lead-out portion  331  and the second inductor lead-out portion  332  that are disposed on the second metal pad  320 . The first metal pad  310  covers the conductive pillar  210  exposed by the top surface of the dielectric layer  120 , and the second metal pad  320  covers the inductor structure  220  exposed by the top surface of the dielectric layer  120 . 
     In this embodiment, projection of the first inductor lead-out portion  331  formed on the substrate  110  is located in a range of projection of the starting end  2201  of the spiral structure  220   a  formed on the substrate  110 ; projection of the second inductor lead-out portion  332  formed on the substrate is located in a range of projection of the termination end of the spiral structure  220   a  formed on the substrate  110 . 
     In the semiconductor structure provided in the present disclosure, the inductor structure  220  that uses the conductive pillar  210  as a magnetic core and that is provided spirally around an outer circumference of the conductive pillar is used, such that when the conductive pillar  210  is turned on, the inductor structure  220  induces a current in the conductive pillar  210  to produce an inductance, and the semiconductor structure in this embodiment does not need to be provided with an inductance through IPD. This can further reduce the size of the semiconductor structure. 
     The embodiments or implementations of this specification are described in a progressive manner, and each embodiment focuses on differences from other embodiments. The same or similar parts between the embodiments may refer to each other. 
     In the description of this specification, the description with reference to terms such as “an embodiment”, “an exemplary embodiment”, “some implementations”, “a schematic implementation”, and “an example” means that the specific feature, structure, material, or characteristic described in combination with the implementation(s) or example(s) is included in at least one implementation or example of the present disclosure. 
     In this specification, the schematic expression of the above terms does not necessarily refer to the same implementation or example. Moreover, the described specific feature, structure, material or characteristic may be combined in an appropriate manner in any one or more implementations or examples. 
     It should be noted that in the description of the present disclosure, the terms such as “center”, “top”, “bottom”, “left”, “right”, “vertical”, “horizontal”, “inner” and “outer” indicate the orientation or position relationships based on the accompanying drawings. These terms are merely intended to facilitate description of the present disclosure and simplify the description, rather than to indicate or imply that the mentioned apparatus or element must have a specific orientation and must be constructed and operated in a specific orientation. Therefore, these terms should not be construed as a limitation to the present disclosure. 
     It can be understood that the terms such as “first” and “second” used in the present disclosure can be used to describe various structures, but these structures are not limited by these terms. Instead, these terms are merely intended to distinguish one structure from another. 
     The same elements in one or more accompanying drawings are denoted by similar reference numerals. For the sake of clarity, various parts in the accompanying drawings are not drawn to scale. In addition, some well-known parts may not be shown. For the sake of brevity, a structure obtained by implementing a plurality of steps may be shown in one figure. In order to understand the present disclosure more clearly, many specific details of the present disclosure, such as the structure, material, size, processing process, and technology of the device, are described below. However, as those skilled in the art can understand, the present disclosure may not be implemented according to these specific details. 
     Finally, it should be noted that the above embodiments are merely intended to explain the technical solutions of the present disclosure, rather than to limit the present disclosure. Although the present disclosure is described in detail with reference to the above embodiments, those skilled in the art should understand that they may still modify the technical solutions described in the above embodiments, or make equivalent substitutions of some or all of the technical features recorded therein, without deviating the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present disclosure. 
     INDUSTRIAL APPLICABILITY 
     In the present disclosure, the inductor structure surrounding the conductive pillar is formed, such that when a current passes through the conductive pillar, the inductor structure is induced by the current in the conductive pillar to produce an inductance, without integrating passive devices in the semiconductor structure. This can further reduce the size of the semiconductor structure.