Patent Publication Number: US-2023164920-A1

Title: Embedded component package structure and manufacturing method thereof

Description:
CROSS-REFERENCE TO RELATED PATENT APPLICATIONS 
     This application is a continuation of U.S. patent application Ser. No. 17/342,363 filed Jun. 8, 2021, which is a continuation of U.S. patent application Ser. No. 16/942,609 filed Jul. 29, 2020, which is a continuation of U.S. patent application Ser. No. 16/159,264 filed Oct. 12, 2018, the contents of which are incorporated herein by reference in their entireties. 
    
    
     BACKGROUND 
     Field of the Invention 
     The invention relates in general to a component package structure and a manufacturing method thereof, and more particularly to an embedded component package structure and a manufacturing method thereof. 
     Description of the Related Art 
     In a system-level package structure, a semiconductor embedded in substrate technology that embeds a semiconductor chip into a package substrate has advantages of reduced noise interference upon a package product as well as reduced product size, and has thus become a focus of research and development of manufacturers in the field. To enhance the production yield rate, it is necessary to fix an embedded component in a package substrate to facilitate electrical connection of patterned conductive circuits and the embedded component in subsequent processing. Therefore, there is a need for a solution for enhancing the reliability of bonding and package processes for an embedded component such that the embedded component remains secured in a package substrate. 
     SUMMARY OF THE INVENTION 
     The invention is directed to an embedded component package structure and a manufacturing method thereof capable of enhancing the reliability of a package process. 
     According to an aspect of the present invention, a manufacturing method of an embedded component package structure is provided. The method includes the following steps: providing a carrier and forming a semi-cured first dielectric layer on the carrier, the semi-cured first dielectric layer having a first surface; providing a component on the semi-cured first dielectric layer, and respectively providing heat energies from a top and a bottom of the component to cure the semi-cured first dielectric layer; forming a second dielectric layer on the first dielectric layer to cover the component; and forming a patterned circuit layer on the second dielectric layer, the patterned circuit layer being electrically connected to the component. 
     According to an aspect of the present invention, an embedded component package structure is provided. The embedded component package structure includes a first dielectric layer having a first surface; a component disposed on the first surface of the first dielectric layer, wherein the first dielectric layer surrounds and covers a side of the component, and the first dielectric layer has a covering height greater than 3 μm relative to the first surface; a second dielectric layer disposed on the first dielectric layer and covering the component; and a patterned circuit layer disposed on the second dielectric layer, and the patterned circuit layer is electrically connected to the component. 
     According to an aspect of the present invention, an embedded component package structure is provided. The embedded component package structure includes a first dielectric layer having a first surface; a component disposed on the first surface of the first dielectric layer, wherein a bottom surface of the component is lower than the first surface; a second dielectric layer disposed on the first dielectric layer and covering the component; and a patterned circuit layer disposed on the second dielectric layer, and the patterned circuit layer is electrically connected to the component. 
     The above and other aspects of the invention will become better understood with regard to the following detailed description of the preferred but non-limiting embodiments. The following description is made with reference to the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG.  1    and  FIG.  2    are schematic diagrams of a manufacturing method of an embedded component package structure; 
         FIG.  3    is a schematic diagram of an embedded component package structure according to an embodiment of the present invention; 
         FIG.  4    to  FIG.  8    are schematic diagrams of a manufacturing method of an embedded component package structure according to an embodiment of the present invention; 
         FIG.  9    is a schematic diagram of forming a patterned circuit layer on a carrier; 
         FIG.  10 A  and  FIG.  10 B  are schematic diagrams of forming another patterned circuit layer on a carrier; and 
         FIG.  11    is a schematic diagram of an embedded component package structure according to another embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION 
     Details are given in the non-limiting embodiments below. It should be noted that the embodiments are illustrative examples and are not to be construed as limitations to the claimed scope of the present invention. The same/similar denotations are used to represent the same/similar components in the description below. 
     Referring to  FIG.  1    and  FIG.  2   , before embedding a component  120  (taking a semiconductor chip for example) into a package structure, the component  120  is first placed on a first dielectric layer  110  of a carrier  100 . The first dielectric layer  110  is, for example, a semi-cured prepreg. The carrier  100  is supported by a support platform (not shown) therebelow, and a heat energy is provided by a heating machine (not shown) to heat the first dielectric layer  110  to a predetermined temperature. The temperature provided by the heating machine is higher (approximately 80° C.), thus providing the preheated first dielectric layer  110  with predetermined glue crawling properties and fluidity, which are beneficial for bonding between the component  120  and the first dielectric layer  110  so as to fix the component  120  on the first dielectric layer  110 . However, the curing speed of the first dielectric layer  110  with higher temperature will be faster accordingly. As shown in  FIG.  2   , when the first dielectric layer  110  is fully cured, a second dielectric layer  130  is formed on the first dielectric layer  110 . The second dielectric layer  130  covers the top of the component  120 . 
     In the above package process, when a sucking head  10  sucks the component  120 , a warpage is incurred due to internal stress of the component  120  such that a bottom surface of the component  120  cannot be tightly bonded (not completely bonded) with the first dielectric layer  110 , causing an insufficient adhesion force of the component  120 . Further, in the subsequent curing process, the first dielectric layer  110  may cure at a high speed due to an excessively high temperature (e.g., 80° C. or higher). As a result, the first dielectric layer  110  may fail in effectively covering and surrounding surfaces (i.e., side surfaces) of the component  120 , causing inadequate covering force of the first dielectric layer  110  upon the component  120  and hence susceptibility to falling off, in a way that subsequently lamination of the second dielectric layer  130  and a wire patterning process cannot be performed successfully. 
     To solve the above issues, an embedded component package structure is provided. Referring to  FIG.  3   , the embedded component package structure  200 A includes a circuit substrate  200 , a first dielectric layer  210 , a component  220 , a second dielectric layer  230 , a patterned circuit layer  240  and a patterned insulation protection layer  260 . The circuit substrate  200  has a conductive wiring layer  202 . The first dielectric layer  210  is disposed on the circuit substrate  200  and has a first surface  212 . The component  220  is disposed on the first surface  212  of the first dielectric layer  210 , and a bottom surface B of the component  220  is lower than the first surface  212 , such that the component  220 , such as a semiconductor chip, can be stably mounted on the first dielectric layer  210 . The second dielectric layer  230  is disposed on the first dielectric layer  210  and covering the component  220 . The patterned circuit layer  240  is disposed on the second dielectric layer  230 , and the patterned circuit layer  240  is electrically connected to the component  220 . patterned insulation protection layer  260 . 
     In an embodiment, the first dielectric layer  210  surrounds and covers a side S 1  of the component  220 , and the first dielectric layer  210  has a covering height H 1  greater than 3 pm relative to the first surface  212 , such that the component  220 , such as a semiconductor chip, can be stably mounted on the first dielectric layer  210 . In an embodiment, a height difference H 2  between the bottom surface B of the component  220  and the first surface  212  is preferably, for example, greater than 3 μm. In an embodiment, the covering height H of the first dielectric layer  210  is, for example, greater than or equal to 5 μm and smaller than the thickness W of the component  220 . 
     To solve the above issues, a manufacturing method of an embedded component package structure  200 A is provided by an embodiment. The method is capable of simultaneously providing heat energies from both the top and the bottom of the embedded component to cure the first dielectric layer. Further, a preheated sucking head used for suction and heating of the embedded component can improve the issue of warpage, allowing the embedded component to be more closely or even entirely bonded on the first dielectric layer, increasing the area and height of the embedded component covered by the first dielectric layer and hence keeping the embedded component securely fixed instead of being likely to falling off. 
     Referring to  FIG.  4    to  FIG.  9   , a manufacturing method of the embedded component package structure  200 B according to an embodiment of the present invention includes following steps. A carrier  200  is first provided, and a semi-cured first dielectric layer  210  is formed on the carrier  200 , wherein the semi-cured first dielectric layer  210  has a first surface  212 . A component  220  is provided on the semi-cured first dielectric layer  210 , and heat energies Ha and Hb are at the same time provided respectively from the top and the bottom of the component  220  to cure the first dielectric layer  210 . A second dielectric layer  230  is formed on the first dielectric layer  210  to cover the component  220 . A patterned circuit layer  240  is formed on the second dielectric layer  230 , and the patterned circuit layer  240  is electrically connected to the component  220 . Details of the above steps are given with the accompanying drawings below. 
     Referring to  FIG.  4   , the carrier  200  is, for example, a circuit substrate, which has a conductive wiring layer  202 . The circuit substrate may be, for example, a copper clad laminate (CCL), a metal core PCB (MCPCB) or a ceramic substrate. In another embodiment, the carrier  200  is, for example, a glass substrate, and serves as a substrate for temporary support and does not include any conductive wires. 
     Referring to  FIG.  5   , the semi-cured first dielectric layer  210  is formed on the carrier  200 , and the stable heat energy Ha is provided at the same time by a heating machine (not shown) at the bottom of the carrier  200  so as to keep the first dielectric layer  210  at a predetermined temperature. In this embodiment, the temperature of the heat energy Ha, for example, drops from 80° C. to 50° C., thus preventing an overly high curing speed of the dielectric layer  210  and hence from failure in effectively covering a side surface of the component. On the other hand, after having lowered the temperature of the heat energy Ha, the glue crawling properties and the fluidity of the semi-cured first dielectric layer  210  can be kept within a certain range for facilitating a subsequent bonding process. In general, the material of the first dielectric layer  210  may be a resin material without glass fiber, e.g., one selected from a group consisting of liquid crystal polymer, bismaleimide triazine (BT) resin, a semi-cured prepreg, an ajinomoto build-up (ABF) film, epoxy and polyimide; the present invention is not limited to the above examples. 
     Referring to  FIG.  6 A  and  FIG.  6 B , the component  220  is sucked by the preheated sucking head  20 , and another heat energy Hb is provided by the sucking head  20  to the top of the component  220 . The temperature of the heat energy Hb is between 100° C. and 150° C., e.g., 130° C., which is higher than the temperature of the heat energy Ha transmitted from the bottom of the carrier  200  to the first dielectric layer  210 . As shown in  FIG.  6 B , after the component  220  absorbs the heat energy Hb transmitted from the preheated sucking head  20 , the warpage generated by the internal stress of the component  220  can be mitigated to maintain the bottom surface B of the component  220  as a planar surface, so as to facilitate subsequently bonding the component  220  on the first dielectric layer  210 . 
     Referring to  FIG.  7   , the component  220  is substantially free from warpage (i.e., planarized) after having absorbed the heat energy Hb, and the bottom surface B of the component  220  can be pressed downwards by the sucking head  20  and becomes directly and flatly placed on the first dielectric layer  210 . Further, the component  220  can directly transmit the heat energy Hb to the first surface  212 , such that the first dielectric layer  210  below the component  220  absorbs the heat energy Hb and melts, further increasing the fluidity of the first dielectric layer  210 , which is beneficial for the first dielectric layer  220  to cover and surround a side S 1  of the component  220 . Referring to  FIG.  6 C  and  FIG.  7   , after the first dielectric layer  210  below the component  220  absorbs the heat energy Hb, the temperature of the first dielectric layer  210  around the component  220  can rise from a predetermined temperature (e.g., 50° C.) to about 130° C., thus increasing the glue crawling properties and the fluidity of the first dielectric layer  210  as shown in  FIG.  6 C . When the heated component  220  comes into contact with the first dielectric layer  210 , conditions of glue crawling and adhesion of the first dielectric layer  210  are better than those when the first dielectric layer  110  comes into contact with the non-heated component  120 . As a result, the covering height of the first dielectric layer  210  is relatively increased. 
     As shown in  FIG.  7   , in an embodiment, the covering height H 1  of the first dielectric layer  210  on the side surface S 1  of the component  220  relative to the first surface  212  is greater than, for example, 3 μm, or even greater than or equal to 5 μm. Thus, the component  220  can be securely fixed on the first dielectric layer  210 . In an embodiment, the covering height H of the first dielectric layer  210  is, for example, smaller than the thickness W of the component  220 ; the present invention is not limited to the above examples. 
     Referring to  FIG.  3    and  FIG.  7   , in the package process in  FIGS.  1  and  2   , the first dielectric layer  110  is heated by single-side heating, and undesired warpage of the component  120  is produced in non-heated situation, such that the first dielectric layer  110  cannot effectively cover the side of the component  120 . Further, when the second dielectric layer  130  covers the first dielectric layer  110 , a void VO is likely formed at the periphery of the component  120  (an area near the bottom of the side surface that is not covered by the first dielectric layer  110 ), and the second dielectric layer  130  cannot entirely fill this void VO. Thus, the component  120  can rely only on the bottom surface thereof to contact the first dielectric layer  110 , rendering poor reliability of the component  120  after the package process. Conversely, in the package process in  FIG.  7   , the first dielectric layer  210  is heated by dual-side heating, i.e., the heat energy Hb of a predetermined temperature (e.g., 130° C.) is further provided to the top of the first dielectric layer  210  to assist partially heating and melting the first dielectric layer  210 . In addition, the heat energy Hb is provided to the top of the component  220  for preheating such that the warpage of the component  220  is unlikely incurred. Thus, the first dielectric layer  210  is capable of effectively covering the side S 1  of the component  220 , and controlling the covering height H 1  to be greater than a predetermined value. Therefore, the side surface S 1  of the component  220  can be tightly covered by the first dielectric layer  210  having better glue crawling conditions or adhesion conditions, further enhancing the reliability of the component  220  after the package process. Moreover, when the component  220  is fixed at the first dielectric layer  210 , it can be placed in an oven and be heated by a predetermined temperature (e.g., 180° C.) for a predetermined period (e.g., more than 30 minutes) to fully cure the first dielectric layer  210 . 
     Further, when the component  220  is preheated by the sucking head  20  and placed on the first dielectric layer  210 , the bottom surface B of the component  220  can be preferably aligned with the first surface  212  or be sunk to be lower than the first surface  212  due to the increased fluidity of the melted first dielectric layer  210 . In an embodiment, a height difference H 2  between the bottom surface B of the component  220  and the first surface  212  is preferably, for example, greater than 3 μm. As such, in the manufacturing method of the present invention, a recess or an opening reserved for accommodating the component  220  need not be manufactured on the first surface  212 , thus eliminating an opening process, and additional adhesive for fixing the component  220  is not required at the bottom surface B of the component  220 . In contrast, the dielectric material (i.e., the first dielectric layer  210 ) of the carrier  200  is directly bonded with the bottom surface B of the component  220 , such that the reliability of the component  220  after the package process is relatively enhanced, and the position of the component  220  is accurately aligned to reduce any alignment error. 
     Referring to  FIG.  8   , the second dielectric layer  230  is formed on the first dielectric layer  210  and covers the component  220 . More specifically, the second dielectric layer  230  can completely cover the first dielectric layer  210  and surround the sides of the component  220 . When the second dielectric layer  230  is fully cured, the component  220  is embedded between the first dielectric layer  210  and the second dielectric layer  230  to form an embedded component package structure. The embedded component  220  may be at least one of an active device (e.g., a transistor, an integrated circuit chip, a logic circuit device or a power amplifier) and a passive device (e.g., a capacitor, an inductor or a resistor). The number of the embedded component is not limited to one, the first dielectric layer  210  and the second dielectric layer  230  may be single-layer or multi-layer structures, and the first dielectric layer  210  and the second dielectric layer  230  may be insulation materials made of the same material or different materials; the present invention is not limited to the above examples. 
     Referring to  FIG.  9   , a patterned circuit layer  240  is formed on the second dielectric layer  230 , and the patterned circuit layer  240  may be electrically connected to the component  220 . In an embodiment, the component  220  includes at least one pad  222  located in a via hole V 1 , and the patterned circuit layer  240  extends from the pad  222  of the component  220  into the via hole V 1  and onto the second dielectric layer  230 . Details of a manufacturing method of the patterned via hole V 1  are given below. Firstly, after forming the second dielectric layer  230 , a via hole V 1  passing through the second dielectric layer  230  is formed by means of wet etching or dry etching to expose at least one pad  222  of the component  222 . Next, a patterned circuit layer  240  is formed on the second dielectric layer  230 , and the patterned circuit layer  240  is electrically connected to the component  220  through the pad  222  in the via hole V 1 . In an embodiment, the patterned circuit layer  240  may be electrically connected to the conductive wiring layer  202  through another via hole V 2  passing through the first dielectric layer  210  and the second dielectric layer  230 , so as to form an embedded component package structure  200 A. The patterned circuit layer  240  may be a copper layer or an aluminum layer. A patterned insulation protection layer  260  (as shown in  FIG.  10 B  and  FIG.  3   ), e.g., made of green paint or other insulation materials, may be formed to cover the top of the patterned circuit layer  240 . 
     Referring to  FIG.  10 A  and  FIG.  10 B , after completing the above patterned circuit layer  240 , another patterned circuit layer  250  may be formed on the carrier  200 , so as to manufacture an embedded component package structure  200 C having dual-side (top and bottom) conductive circuits. A manufacturing method of a patterned via hole V 3  is similar to that of the via hole V 1 , and differs only in that, the via hole V 3  passes through the carrier  20  to expose the conductive wiring layer  202  of the carrier  200 . Next, the patterned circuit layer  250  is formed on the other surface (i.e., the bottom surface) of the carrier  200 , and the patterned circuit layer  250  at the bottom is electrically connected to the conductive wiring layer  202  through the via hole V 3 . Further, in another embodiment, the patterned circuit layer  250  at the bottom may be electrically connected to the patterned circuit layer  240  on the top through an interlayer conductive via or directly through a vertically conducted through hole (not shown); the present invention is not limited to the above examples. 
     Referring to  FIG.  10 B , the patterned insulation protection layers  260  and  270  are respectively formed on the patterned circuit layers  240  and  250  at the top and the bottom, and electrical contacts  242  and  252  at the top and the bottom are exposed. The pad  222  of the component  220  may be electrically connected to the electrical contacts  242  and  252  at the top and the bottom through these two patterned circuit layers  240  and  250 . The electrical contacts  242  and  252  are, for example, solder protrusions, lead-less protrusions, copper protrusions or gold protrusions provided for electrically connecting to external electronic signals; the present invention is not limited to the above examples. 
     Referring to  FIG.  9    and  FIG.  11   , in an embodiment, the carrier  200  in  FIG.  9    serves only as a substrate for providing temporary support, and the carrier  200  may be removed or separated to expose the conductive wiring layer  202  of the embedded component package structure  200 D, as shown in  FIG.  11   . In  FIG.  11   , the conductive wiring layer  202  is not limited to being a single-layer structure, and may also be a multi-layer structure. Further, the patterned insulation protection layer  270  and the electrical contact  252  may be formed at the bottom of the conductive wiring layer  202 , as shown in  FIG.  10 B , the present invention is not limited to the above examples. 
     In the embedded component package structure disclosed by the embodiments of the present invention, the first dielectric layer  210  and the second dielectric layer  230  that are laminated and stacked are given as an example. However, the embedded component may also be provided in multiple laminated and stacked dielectric layers instead of being provided in two layers. Further, the embedded component  220  is not limited to being located in the laminated and stacked first dielectric layer  210  and second dielectric layer  230 , and more than one embedded component  220  may also be provided between any two adjacently arranged dielectric layers according to package requirements. 
     While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited thereto. On the contrary, it is intended to cover various modifications and similar arrangements and procedures, and the scope of the appended claims therefore should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements and procedures.