Patent Publication Number: US-2023138397-A1

Title: Control circuit for dc-dc converters with nonlinear adaptive voltage position and control method thereof

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application claims the benefit of CN application 202111284124.3, filed on Nov. 1, 2021, and incorporated herein by reference. 
     TECHNICAL FIELD 
     The present invention generally relates to electronic circuits, and more particularly, relates to adaptive voltage position (AVP) control circuits for DC-DC converters and control methods thereof. 
     BACKGROUND 
     In power supplies for microprocessors with high current and low voltage, the power performance, especially the transient response is vital. Adaptive voltage position (AVP) control is widely used to reduce voltage deviations of the output voltage (i.e., the power supply of microprocessors) during the load step to insure the system stability. 
     The basic principle of traditional AVP control is shown in  FIG.  1   . An output voltage Vo decreases linearly from a voltage V 1  to a voltage V 2 , as an output current Io (i.e. load current) increases from a minimum value (e.g., from zero) to a maximum load point Imax, wherein V 1  may be a reference voltage set according to a voltage identification code (VID) from a processor load. 
     With fast development of the microprocessor, power supplies with higher voltage levels are needed. The output voltage at full load may be very low, which may be close to a lowest threshold of the CPU operational voltage, if traditional AVP control is adopted. Thus, an improved voltage regulator with better output voltage control is in high demand. 
     SUMMARY 
     Embodiments of the present invention are directed to a control circuit for a DC-DC converter, comprising an adaptive voltage position (AVP) control circuit and a switching control circuit. The DC-DC converter comprises at least one switch, and is configured to receive an input voltage and to provide an output voltage and an output current. The AVP control circuit is configured to provide a position signal based on the output voltage, the output current, a voltage identification code and a set of adaptive voltage control commands, wherein the set of adaptive voltage control commands comprises a load line data. The switching control circuit is configured to provide a switching control signal based on the position signal to control the at least one switch of the DC-DC converter. When the output current is smaller than a first current threshold, the control circuit is configured to choose one of a first voltage position curve, a second voltage position curve, and a third voltage position curve as a load line of the output voltage versus the output current according to the load line data, wherein each of the first voltage position curve, the second voltage position curve, and the third voltage position curve is a curve of the output voltage against the output current with a slope. When the output current is larger than the first current threshold and smaller than a second current threshold, the control circuit is configured to choose one of the remaining two voltage position curves as the load line according to the load line data. And when the output current is larger than the second current threshold, the control circuit is configured to choose the remaining voltage position curve as the load line according to the load line data. The control circuit is further configured to control the output voltage to vary along the load line as the output current varies. 
     Embodiments of the present invention are also directed to a control circuit for a DC-DC converter, comprising an adaptive voltage position (AVP) control circuit and a switching control circuit. The DC-DC converter comprises at least one switch, and is configured to receive an input voltage and provide an output voltage and an output current. The AVP control circuit is configured to provide a position signal based on the output voltage, the output current, a voltage identification code, and a set of adaptive voltage control commands. The switching control circuit is configured to provide a switching control signal based on the position signal to control the at least one switch of the DC-DC converter. When the output current is smaller than a current threshold, the control circuit is configured to choose one of a first voltage position curve and a second voltage position curve as a load line of the output voltage versus the output current according to the set of adaptive voltage control commands, and when the output current is larger than the current threshold, the control circuit is configured to choose the remaining voltage position curve as the load line according to the set of adaptive voltage control commands, and the control circuit is further configured to control the output voltage to vary along the load line as the output current varies. 
     Embodiments of the present invention are further directed to an adaptive voltage position (AVP) control method for a DC-DC converter. The DC-DC converter comprises at least one switch, and is configured to receive an input voltage and provide an output voltage and an output current. The AVP control method comprises receiving a set of adaptive voltage control commands and a voltage identification code, generating a position signal based on the output voltage and the output current, the voltage identification code and the set of adaptive voltage control commands, providing a switching control signal based on the position signal to control at least one switch of the DC-DC converter. Wherein when the output current is smaller than a first current threshold, choosing one of a plurality of voltage position curves as a load line of the output voltage versus the output current according to the set of adaptive voltage control commands, and when the output current is larger than the first current threshold, choosing one of the remaining of the plurality of voltage position curves as the load line according to the set of adaptive voltage control commands, and further controlling the output voltage to vary along the load line as the output current varies. And wherein the plurality of voltage position curves comprise a first voltage position curve and a second voltage position curve. 
     These and other features of the present invention will be readily apparent to persons of ordinary skill in the art upon reading the entirety of this disclosure, which includes the accompanying drawings and claims. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWING 
       The present invention can be further understood with reference to the following detailed description and the appended drawings, wherein like elements are provided with like reference numerals. 
         FIG.  1    schematically shows a basic principle of traditional adaptive voltage position (AVP) control. 
         FIG.  2    schematically shows a DC-DC converter  200  in accordance with an embodiment of the present invention. 
         FIG.  3 A- 3 E  show plots of two-stage voltage position control in accordance with an embodiment of the present invention. 
         FIG.  4 A- 4 D  show plots of three-stage voltage position control in accordance with an embodiment of the present invention. 
         FIG.  5    schematically shows an AVP control circuit  224  in accordance with an embodiment of the present invention. 
         FIG.  6    schematically shows a reference voltage generator  31  in accordance with an embodiment of the present invention. 
         FIG.  7    schematically shows a feedback signal generator  32  in accordance with an embodiment of the present invention. 
         FIG.  8    schematically shows a position signal generator  33  in accordance with an embodiment of the present invention. 
         FIG.  9    schematically shows a truth table of a logic circuit  600  of the position signal generator  33  in accordance with an embodiment of the present invention. 
         FIG.  10    schematically shows an AVP control circuit  224  in accordance with another embodiment of the present invention. 
         FIG.  11    schematically shows a reference voltage generator  71  in accordance with an embodiment of the present invention. 
         FIG.  12    schematically shows a feedback signal generator  72  in accordance with an embodiment of the present invention. 
         FIG.  13    schematically shows a position signal generator  73  in accordance with an embodiment of the present invention. 
         FIG.  14    schematically shows a truth table of a logic circuit  600  of the position signal generator  73  in accordance with an embodiment of the present invention. 
         FIG.  15    illustrates an AVP control method  1500  for a DC-DC converter in accordance with an embodiment of the present invention. 
         FIG.  16    illustrates an AVP control method  1600  for a DC-DC converter in accordance with another embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION 
     Reference will now be made in detail to the preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. While the invention will be described in conjunction with the preferred embodiments, it will be understood that they are not intended to limit the invention to these embodiments. On the contrary, the invention is intended to cover alternatives, modifications and equivalents, which may be included within the spirit and scope of the invention as defined by the appended claims. Furthermore, in the following detailed description of the present invention, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be obvious to one of ordinary skill in the art that the present invention may be practiced without these specific details. In other instances, well-known methods, procedures, components, and circuits have not been described in detail so as not to unnecessarily obscure aspects of the present invention. 
     The control circuit for a DC-DC converter illustrated in the embodiments comprises an adaptive voltage position (AVP) control circuit and a switching control circuit. The AVP control circuit receives a voltage identification code and a set of adaptive voltage control commands, and generates a position signal based on an output voltage and an output current under the control of the voltage identification code and the set of adaptive voltage control commands. The switching control circuit generates a switching control signal based on the position signal to control at least one switch of the DC-DC converter. Within different sections of the output current, the control circuit chooses different voltage position curves as a load line of the output voltage versus the output current according to the set of adaptive voltage control commands. In other words, when the output current is smaller than a first current threshold, the control circuit chooses one of a plurality of voltage position curves as the load line, and when the output current is larger than the first current threshold, the control circuit chooses one of the remaining of the plurality of voltage position curves as the load line. For example, when the output current is smaller than the first current threshold, the control circuit chooses one of a first voltage position curve and a second voltage position curve as the load line, and when the output current is larger than the first current threshold, the control circuit chooses the remaining voltage position curve as the load line. In another example, when the output current is smaller than the first current threshold, the control circuit chooses one of the first voltage position curve, the second voltage position curve, and a third voltage position curve as the load line, when the output current is larger than the first current threshold and smaller than a second current threshold, the control circuit chooses one of the remaining two voltage position curves as the load line, and when the output current is larger than the second current threshold, the control circuit chooses the remaining voltage position curve as the load line. Wherein each of the first voltage position curve, the second voltage position curve and the third voltage position curve is a curve of the output voltage against the output current with a slope. Thus, the control circuit controls the output voltage to vary nonlinearly along the load line as the output current varies. The control circuit can provide any kind of nonlinear load line to meet different requirements of the load. 
       FIG.  2    schematically shows a DC-DC converter  200  in accordance with an embodiment of the present invention. In the example of  FIG.  2   , DC-DC converter  200  comprises a switching circuit  21  and a control circuit  22 . Switching circuit  21  is configured to receive an input voltage Vin, and is configured to provide an output voltage Vo and an output current Io to a load. An output capacitor Co is coupled between an output terminal of switching circuit  21  and a ground. For example, the load may comprise but not be limited to central processing unit (CPU), graphics processing unit (GPU), etc. Control circuit  22  is configured to receive a voltage identification code VID provided by the load to determine output voltage Vo and a set of adaptive voltage control commands Vdp_set to determine features of the load line, and is configured to generate a switching control signal Ctrl to control at least one switch of switching circuit  21  based on an output voltage sense signal Vosen representative of output voltage Vo, an output current sense signal Isen representative of output current Io, the voltage identification code VID and the set of adaptive voltage control commands Vdp_set. Thus, output voltage Vo varies nonlinearly as output current Io varies under the control of set of adaptive voltage control commands Vdp_set. Controlled by set of adaptive voltage control commands Vdp_set, DC-DC converter  200  may have a nonlinear load line of any kind to meet different requirements of the load. Generally, the load line represents a voltage droop of output voltage Vo with increasing of output current Io. Switching circuit  21  may comprise a single-phase or multi-phase circuit topology, such as buck, boost or buck-boost circuit, etc. In the example of  FIG.  2   , switching circuit  21  is a single-phase buck circuit for illustration. In the example of  FIG.  2   , switching circuit  21  comprises a switch S 1 , a switch S 2 , an output inductor Lo and an input capacitor Cin. A first terminal of switch S 1  is coupled to an input terminal of switching circuit  21  to receive input voltage Vin. A first terminal of switch S 2  is coupled to a second terminal of switch S 1 , and a second terminal of switch S 2  is coupled to the ground. Switch S 1  and switch S 2  are turned ON and OFF complementarily under the control of switching control signal Ctrl. Output inductor Lo has a first terminal coupled to the second terminal of switch S 1  and the first terminal of switch S 2 , and has a second terminal coupled to the output terminal to provide output voltage Vo. Input capacitor Cin is between the input terminal and the ground. In one embodiment, output current sense signal Isen represents a current flowing through output inductor Lo. In one embodiment, voltage sense signal Vosen is a differential voltage. 
     In one embodiment, control circuit  22  comprises a communication interface circuit  221 , a communication interface circuit  222 , a memory  223 , an AVP control circuit  224 , and a switching control circuit  225 . Communication interface circuit  221  receives voltage identification code VID sent by the load through a communication bus  226 . Voltage identification code VID is received to provide a reference voltage Vref 1  to DC-DC converter  200 . In one example, communication bus  226  comprises a parallel voltage identification (PVID) bus, a serial voltage identification (SVID) bus and an adaptive voltage scaling bus (AVSBus), etc. In one example, interface circuit  221  comprises a PVID interface circuit, an SVID interface circuit and an AVSBus interface circuit, etc. Interface circuit  222  receives set of adaptive voltage control commands Vdp_set through a communication bus  227 . Set of adaptive voltage control commands Vdp_set may be written in by users through a graphical user interface (GUI), or provided by a system controller. In one example, communication bus  227  may comprise a power management bus (PMBus), a system management bus (SMBus), a bidirectional synchronous serial bus I2C, etc., and communication interface circuit  222  may comprise a PMBus interface circuit, an SMBus interface circuit, and I2C interface circuit, etc. Memory  223  is configured to save set of adaptive voltage control commands Vdp_set received through communication interface circuit  222 . 
     In one embodiment, set of adaptive voltage control commands Vdp_set comprises a load line data LL. Within different sections of the output current, control circuit  22  chooses different voltage position curves as the load line according to load line data LL, to control output voltage Vo to vary nonlinearly along the load line as output current Io varies. In one embodiment, the load line comprises a first voltage position curve and a second voltage position curve. In one embodiment, set of adaptive voltage control commands Vdp_set further comprises a voltage position resistance data DRP 1  to control a slope of the first voltage position curve, a voltage offset data OFFSET 2  to participate in controlling an offset of the second voltage position curve, and a voltage position resistance data DRP 2  to control a slope of the second voltage position curve. An offset of the first voltage position curve is controlled by voltage identification code VID, and the offset of the second voltage position curve is controlled by voltage identification code VID and voltage offset data OFFSET 2 . In one embodiment, the load line further comprises a third voltage position curve, and set of adaptive voltage control commands Vdp_set further comprises a voltage offset data OFFSET 3  to participate in controlling an offset of the third voltage position curve and a voltage position resistance data DRP 3  to control a slope of the third voltage position curve, wherein the offset of the third voltage position curve is controlled by voltage identification code VID and voltage offset data OFFSET 3 . 
     AVP control circuit  224  receives voltage identification code VID and set of adaptive voltage control commands Vdp_set, and generates a position signal Set based on output voltage Vo and output current Io under the control of voltage identification code VID and set of adaptive voltage control commands Vdp_set. Switching control circuit  225  generates switching control signal Ctrl based on position signal Set to control the at least one switch of DC-DC converter  200 . In the example of  FIG.  2   , switching control circuit  225  employs constant ON time control for illustration. For example, switching control circuit  225  comprises an RS flip-flop  31  and an ON time control circuit  30 . When position signal Set becomes active, RS flip-flop  31  is set, switch S 1  is turned ON and switch S 2  is turned OFF by switching control signal Ctrl. Until the ON time period of switch S 1  reaches a time period predetermined by ON time control circuit  30 , RS flip-flop  31  is reset, switch S 1  is turned OFF and switch S 1  is turned ON by switching control signal Ctrl. One with ordinary skill in the art should understand that the detailed circuit structure of switching control circuit  225  is not limited by the example shown in  FIG.  2   , and switching control circuit  225  may also comprise any other suitable control methods and circuit topologies. 
       FIG.  3 A- 3 E  show plots of two-stage voltage position control in accordance with embodiments of the present invention.  FIG.  3 A  shows voltage position curves  1101 - 1102  in accordance with an embodiment of the present invention. In one embodiment, voltage position curve  1101  is generated based on voltage identification code VID and voltage position resistance data DRP 1 . Voltage identification code VID is configured to control an offset of voltage position curve  1101 , and voltage position resistance data DRP 1  is configured to control a slope of voltage position curve  1101 . The offset of voltage position curve  1101  equals the level of output voltage Vo when output current Io is zero, i.e., reference voltage Vref 1 . Voltage position resistance data DRP 1  determines the resistance of voltage position resistor Rdroop 1 , and thus controls the slope of voltage position curve  1101 . In one embodiment, voltage position curve  1102  is generated based on voltage identification code VID, voltage offset data OFFSET 2  and voltage position resistance data DRP 2 . Voltage identification code VID and voltage offset data OFFSET 2  are configured to control an offset of voltage position curve  1102 , and voltage position resistance data DRP 2  is configured to control a slope of voltage position curve  1102 . The offset of voltage position curve  1102  equals the level of output voltage Vo when output current Io is zero, i.e., a reference voltage Vref 2 . Voltage position resistance data DRP 2  determines the resistance of voltage position resistor Rdroop 2 , and thus controls the slope of voltage position curve  1102 . In the example of  FIG.  3 A , the resistance of voltage position resistor Rdroop 1  controlled by voltage position resistance data DRP 1  is zero, as a result, the slope of voltage position curve  1101  is zero. Voltage offset data OFFSET 2  corresponds to a positive voltage offset, and reference voltage Vref 2  is higher than reference voltage Vref 1 . The resistance of voltage position resistor Rdroop 2  controlled by voltage position resistance data DRP 2  is larger than the resistance of voltage position resistor Rdroop 1  controlled by voltage position resistance data DRP 1 . 
     In one embodiment, within different sections of output current Io, control circuit  22  chooses different voltage position curves as the load line, and thus controls output voltage Vo to vary between a maximum output voltage Vmax and a minimum output voltage Vmin along the load line as output current Io varies. 
       FIG.  3 B  shows a plot of load line comprising two voltage position curves in accordance with an embodiment of the present invention. In the example of  FIG.  3 B , under the control of load line data LL, voltage position curve  1101  is used as the load line when output current Io is smaller than a current threshold I(k 1 ), and voltage position curve  1102  is used as the load line when output current Io is larger than current threshold I(k 1 ). Current threshold I(k 1 ) equals output current Io at the intersection of voltage position curve  1101  and voltage position curve  1102 . In one embodiment, current threshold I(k 1 ) changes with voltage position curves  1101 - 1102 . One with ordinary skill in the art should understand that voltage position curves  1101 - 1102  are not limited by the example shown in  FIG.  3 B , but may also have any different offset and slope under the control of set of adaptive voltage control commands Vdp_set.  FIG.  3 C  shows the plot of load line comprising two voltage position curves in accordance with another embodiment of the present invention. In the example of  FIG.  3 C , under the control of load line data LL, voltage position curve  1102  is used as the load line when output current Io is smaller than current threshold I(k 1 ), and voltage position curve  1101  is used as the load line when output current Io is larger than current threshold I(k 1 ).  FIG.  3 D  shows a plot of load line comprising two voltage position curves in accordance with another embodiment of the present invention. In the example of  FIG.  3 D , voltage offset data OFFSET 2  corresponds to a positive voltage offset, and reference voltage Vref 2  is larger than reference voltage Vref 1 . The resistance of voltage position resistor Rdroop 2  controlled by voltage position resistance data DRP 2  is larger than the resistance of voltage position resistor Rdroop 1  controlled by voltage position resistance data DRP 1 , and thus the slope of voltage position curve  1102  is larger than the slope of voltage position curve  1101 .  FIG.  3 E  shows a plot of load line comprising two voltage position curves in accordance with another embodiment of the present invention. In the example of  FIG.  3 E , voltage offset data OFFSET 2  corresponds to a negative voltage offset and reference voltage Vref 2  is smaller than reference voltage Vref 1 . The resistance of voltage position resistor Rdroop 2  controlled by voltage position resistance data DRP 2  is smaller than the resistance of voltage position resistor Rdroop 1  controlled by voltage position resistance data DRP 1 , and thus the slope of voltage position curve  1102  is smaller than the slope of voltage position curve  1101 . 
       FIG.  4 A- 4 D  show plots of three-stage voltage position control in accordance with embodiments of the present invention.  FIG.  4 A  shows voltage position curves  1101 - 1103  in accordance with an embodiment of the present invention. Compared with  FIG.  3 A ,  FIG.  4 A  further shows a voltage position curve  1103 . In one embodiment, voltage position curve  1103  is generated based on voltage identification code VID, voltage offset data OFFSET 3  and voltage position resistance data DRP 3 . Voltage identification code VID and voltage offset data OFFSET 3  are configured to control an offset of voltage position curve  1103 , and voltage position resistance data DRP 3  is configured to control a slope of voltage position curve  1103 . The offset of voltage position curve  1103  equals the level of output voltage Vo when output current Io is zero, i.e., a reference voltage Vref 3 . Voltage position resistance data DRP 3  determines the resistance of voltage position resistor Rdroop 3 , and thus controls the slope of voltage position curve  1103 . 
       FIG.  4 B  shows a plot of load line comprising three voltage position curves in accordance with an embodiment of the present invention. In the example of  FIG.  4 B , reference voltage Vref 2  is larger than reference voltage Vref 1 , reference voltage Vref 1  is larger than reference voltage Vref 3 , the resistance of voltage position resistor Rdroop 2  controlled by voltage position resistance data DRP 2  is larger than the resistance of voltage position resistor Rdroop 3  controlled by voltage position resistance data DRP 3 , and the resistance of voltage position resistor Rdroop 3  controlled by voltage position resistance data DRP 3  equals the resistance of voltage position resistor Rdroop 1  controlled by voltage position resistance data DRP 1 . In the example of  FIG.  4 B , when output current Io is smaller than current threshold I(k 1 ), voltage position curve  1101  is chosen as the load line by control circuit  22  according to load line data LL. When output current Io is larger than current threshold I(k 1 ) and smaller than a current threshold I(k 2 ), voltage position curve  1102  is chosen as the load line by control circuit  22  according to load line data LL. When output current Io is larger than current threshold I(k 2 ), voltage position curve  1103  is chosen as the load line by control circuit  22  according to load line data LL. Current threshold I(k 2 ) equals output current Io at the intersection of voltage position curve  1102  and voltage position curve  1103 . In one embodiment, current threshold I(k 2 ) changes with voltage position curves  1102 - 1103 . One with ordinary skill in the art should understand that voltage position curves  1101 - 1103  are not limited by the example shown in  FIG.  4 B , but may also have any different offset and slope under the control of set of adaptive voltage control commands Vdp_set. One with ordinary skill in the art should understand that in different sections of output current Io, control circuit  22  may also choose voltage position curves different from the example shown in  FIG.  4 B  to meet different requirements of the load. 
       FIG.  4 C  shows a plot of load line comprising three voltage position curves in accordance with another embodiment of the present invention. In the example of  FIG.  4 C , reference voltage Vref 1  is larger than reference voltage Vref 2 , reference voltage Vref 2  is larger than reference voltage Vref 3 , the resistance of voltage position resistor Rdroop 1  controlled by voltage position resistance data DRP 1  is larger than the resistance of voltage position resistor Rdroop 2  controlled by voltage position resistance data DRP 2 , and the resistance of voltage position resistor Rdroop 2  controlled by voltage position resistance data DRP 2  is larger than the resistance of voltage position resistor Rdroop 3  controlled by voltage position resistance data DRP 3 .  FIG.  4 D  shows a plot of load line comprising three voltage position curves in accordance with another embodiment of the present invention. In the example of  FIG.  4 D , reference voltage Vref 3  is larger than reference voltage Vref 2 , reference voltage Vref 2  is larger than reference voltage Vref 1 , the resistance of voltage position resistor Rdroop 1  controlled by voltage position resistance data DRP 1  is smaller than the resistance of voltage position resistor Rdroop 2  controlled by voltage position resistance data DRP 2 , and the resistance of voltage position resistor Rdroop 2  controlled by voltage position resistance data DRP 2  is smaller than the resistance of voltage position resistor Rdroop 3  controlled by voltage position resistance data DRP 3 . 
     One with ordinary skill in the art should understand that the load line and the voltage position curves included in which are not limited by the examples shown in  FIG.  3   - FIG.  4   . Users may also design load lines comprising any number of voltage position curves and voltage position curves with any offset and slope via set of adaptive voltage control commands Vdp_set. Within different sections of output current Io, users may also choose different voltage position curves as the load line according to load line data LL to meet different requirements of the load, without changing the hardware of DC-DC converter  200 . 
       FIG.  5    schematically shows an AVP control circuit  224  in accordance with an embodiment of the present invention. The embodiment of  FIG.  5    employs two-stage voltage position control as an example. 
     In the example of  FIG.  5   , AVP control circuit  224  comprises a reference voltage generator  31 , a feedback signal generator  32  and a position signal generator  33 . Reference voltage generator  31  generates reference voltage Vref 1  and reference voltage Vref 2  based on voltage identification code VID and voltage offset data OFFSET 2 . In one embodiment, reference voltage generator  31  generates reference voltage Vref 1  based on voltage identification code VID, and generates reference voltage Vref 2  based on voltage identification code VID and voltage offset data OFFSET 2 , so that reference voltage Vref 2  equals the sum of reference voltage Vref 1  and an offset voltage Voff 2  (Vref 1 +Voff 2 ), wherein offset voltage Voff 2  is controlled by voltage offset data OFFSET 2 . In one embodiment, voltage offset data OFFSET 2  may be positive, zero, or negative. Accordingly, offset voltage Voff 2  may be positive, zero, or negative. In one embodiment, feedback signal generator  32  generates a feedback signal Vfb 1  and a feedback signal Vfb 2  based on output voltage sense signal Vosen and output current sense signal Isen under the control of voltage position resistance data DRP 1  and voltage position resistance data DRP 2 . In one embodiment, position signal generator  33  generates position signal Set based on reference voltage Vref 1 , reference voltage Vref 2 , feedback signal Vfb 1 , feedback signal Vfb 2  and load line data LL. For example, position signal generator  33  generates position signal Set based on a comparison signal Set 1  generated by comparing reference voltage Vref 1  with feedback signal Vfb 1 , a comparison signal Set 2  generated by comparing reference voltage Vref 2  with feedback signal Vfb 2 , and load line data LL. 
       FIG.  6    schematically shows reference voltage generator  31  in accordance with an embodiment of the present invention. In the example of  FIG.  6   , reference voltage generator  31  comprises an operational circuit  302  and a digital-analog converting circuit  311 . Operational circuit  302  receives voltage identification code VID and voltage offset data OFFSET 2 , and sends the sum of voltage identification code VID and voltage offset data OFFSET 2  (VID+OFFSET 2 ) to digital-analog converting circuit  311 . Digital-analog converting circuit  311  generates reference voltage Vref 1  based on voltage identification code VID, and generates reference voltage Vref 2  based on the sum of voltage identification code VID and voltage offset data OFFSET 2  (VID+OFFSET 2 ). 
       FIG.  7    schematically shows a feedback signal generator  32  in accordance with an embodiment of the present invention. In the example of  FIG.  7   , feedback signal generator  32  comprises a current mirror  50 , a voltage position resistor Rdroop, a multiplexer  51  and a multiplexer  52 . Current mirror  50  generates a mirror current M*Io which is proportional to the output current based on output current sense signal Isen, wherein the coefficient M is positive. Voltage position resistor Rdroop has a current sense terminal  511  and a voltage sense terminal  512 . Current sense terminal  511  is coupled to current mirror  50  to receive mirror current M*Io, and voltage sense terminal  512  receives output voltage sense signal Vosen. Voltage position resistor Rdroop has a plurality of nodes Ta( 1 ), Ta( 2 ), . . . Ta(n), and each node corresponds to a voltage. Multiplexer  51  comprises a plurality of input terminals which are respectively coupled to the plurality of nodes of voltage position resistor Rdroop. Multiplexer  51  comprises an output terminal  513  to provide feedback signal Vfb 1 . Multiplexer  51  selects one of the plurality of nodes based on voltage position resistance data DRP 1  to control the resistance of voltage position resistor Rdroop 1  across output terminal  513  and voltage sense terminal  512 , so as to provide feedback signal Vfb 1 . In one embodiment, feedback signal Vfb 1  equals a sum of output voltage sense signal Vosen and a voltage drop generated by mirror current M*Io flowing through voltage position resistor Rdroop 1 . Feedback signal Vfb 1  may be expressed by the following formula (1). Multiplexer  52  comprises a plurality of input terminals which are respectively coupled to the nodes of voltage position resistor Rdroop. Multiplexer  52  comprises an output terminal  523 , configured to provide feedback signal Vfb 2 . Multiplexer  52  selects one node in the plurality of nodes based on voltage position resistance data DRP 2  to control the resistance of voltage position resistor Rdroop 2  across output terminal  523  and voltage sense terminal  512 , so as to get feedback signal Vfb 2 . In one embodiment, feedback signal Vfb 2  equals a sum of output voltage sense signal Vosen and the voltage drop generated by mirror current M*Io flowing through voltage position resistor Rdroop 2 . Feedback signal Vfb 2  may be expressed by the following formula (2). 
         Vfb 1=Vosen+ M*Io*R droop1  (1)
 
         Vfb 2=Vosen+ M*Io*R droop2  (2)
 
       FIG.  8    schematically shows position signal generator  33  in accordance with an embodiment of the present invention. In the example of  FIG.  8   , position signal generator  33  comprises a comparison circuit  61  and a logic circuit  600 . In the example of  FIG.  8   , compare circuit  61  comprises a comparator  601  and a comparator  602 . Comparator  601  has a non-inverting input terminal to receive reference voltage Vref 1 , an inverting input terminal to receive feedback signal Vfb 1 , and an output terminal to provide comparison signal Set 1  by comparing reference voltage Vref 1  with feedback signal Vfb 1 . When feedback signal Vfb 1  is smaller than reference voltage Vref 1 , comparison signal Set 1  becomes active (e.g. logic high). Comparator  602  has a non-inverting input terminal to receive reference voltage Vref 2 , an inverting input terminal to receive feedback signal Vfb 2 , and an output terminal to provide comparison signal Set 2  by comparing reference voltage Vref 2  with feedback signal Vfb 2 . When feedback signal Vfb 2  is smaller than reference voltage Vref 2 , comparison signal Set 2  becomes active (e.g. logic high). Logic circuit  600  receives comparison signal Set 1 , comparison signal Set 2  and load line data LL, and generates position signal Set based on comparison signal Set 1 , comparison signal Set 2  and load line data LL. 
       FIG.  9    schematically shows a truth table of logic circuit  600  of position signal generator  33  in accordance with an embodiment of the present invention. In one embodiment, when load line data LL is in a first status (e.g., LL=“1”), and when feedback signal Vfb 1  is smaller than reference voltage Vref 1  (Set 1 =“1”) and feedback signal Vfb 2  is smaller than reference voltage Vref 2  (Set 2 =“1”), position signal Set becomes active (e.g., Set=“1”) to turn ON the at least one switch of switching circuit  21 , otherwise Set is “0”. In one embodiment, when load line data LL is in a second status (e.g., LL=“0”), and when feedback signal Vfb 1  is smaller than reference voltage Vref 1  (Set 1 =“1”) or feedback signal Vfb 2  is smaller than reference voltage Vref 2  (Set 2 =“1”), position signal Set becomes active (e.g., Set=“1”) to turn ON the at least one switch of control circuit  21 , otherwise Set is “0”. In the example of  FIG.  9   , comparison signals Set 1 -Set 2  and position signal Set are active when at a high voltage level. One with ordinary skill in the art should understand that comparison signals Set 1 -Set 2  and position signal Set may also be set active when at a low voltage level. 
       FIG.  10    schematically shows AVP control circuit  224  in accordance with another embodiment of the present invention. The embodiment of  FIG.  10    employs three-stage voltage position control as an example. 
     In the example of  FIG.  10   , AVP control circuit  224  comprises a reference voltage generator  71 , a feedback signal generator  72  and a position signal generator  73 . Reference voltage generator  71  generates reference voltages Vref 1 -Vref 3  based on voltage identification code VID and voltage offset datas OFFSET 2 -OFFSET 3 . In one embodiment, reference voltage Vref 1  is generated based on voltage identification code VID, reference voltage Vref 2  is generated based on voltage identification code VID and voltage offset data OFFSET 2 , and reference voltage Vref 3  is generated based on voltage identification code VID and voltage offset data OFFSET 3 . For example, reference voltage Vref 3  is equal to a sum of reference voltage Vref 1  and an offset voltage Voff 3  (Vref 1 +Voff 3 ), wherein the offset voltage Voff 3  is controlled by voltage offset data OFFSET 3 . In one embodiment, feedback signal generator  72  generates feedback signals Vfb 1 -Vfb 3  based on output voltage sense signal Vosen and output current sense signal Isen under the control of voltage position resistance datas DRP 1 -DRP 3 . In one embodiment, position signal generator  73  generates position signal Set based on reference voltages Vref 1 -Vref 3 , feedback signals Vfb 1 -Vfb 3 , and load line data LL. For example, comparison signal Set 1  is generated by comparing reference voltage Vref 1  with feedback signal Vfb 1 , comparison signal Set 2  is generated by comparing reference voltage Vref 2  with feedback signal Vfb 2 , a comparison signal Set 3  is generated by comparing reference voltage Vref 3  with feedback signal Vfb 3 , and thus position signal Set is generated based on comparison signal Set 1 , comparison signal Set 2 , comparison signal Set 3  and load line data LL. 
       FIG.  11    schematically shows reference voltage generator  71  in accordance with an embodiment of the present invention. In the example of  FIG.  11   , compared with reference voltage generator  31 , reference voltage generator  71  further comprises an operational circuit  303 . Operational circuit  303  receives voltage identification code VID and voltage offset data OFFSET 3 , and sends a sum of voltage identification code VID and voltage offset data OFFSET 3  (VID+OFFSET 3 ) to digital-analog converting circuit  311 . Digital-analog converting circuit  311  further generates reference voltage Vref 3  based on the sum of voltage identification code VID and voltage offset data OFFSET 3  (VID+OFFSET 3 ). 
       FIG.  12    schematically shows feedback signal generator  72  in accordance with an embodiment of the present invention. In the example of  FIG.  12   , compared with feedback signal generator  32 , feedback signal generator  72  further comprises a multiplexer  53 . Multiplexer  53  comprises a plurality of input terminals which are respectively coupled to the nodes of voltage position resistor Rdroop. Multiplexer  53  comprises an output terminal  524 , which is configured to provide feedback signal Vfb 3 . Multiplexer  53  selects one node in the plurality of nodes based on voltage position resistance data DRP 3  to control the resistance of voltage position resistor Rdroop 3  across output terminal  524  and voltage sense terminal  512 , so as to provide feedback signal Vfb 3 . In one embodiment, feedback signal Vfb 3  equals a sum of output voltage sense signal Vosen and a voltage drop generated by mirror current M*Io flowing through voltage position resistor Rdroop 3 . Feedback signal Vfb 3  may be expressed by the following formula (3). 
         Vfb 3=Vosen+ M*Io*R droop3  (3)
 
       FIG.  13    schematically shows position signal generator  73  in accordance with an embodiment of the present invention. In the example of  FIG.  13   , position signal generator  73  comprises compare circuit  61  and logic circuit  600 . In the example of  FIG.  13   , compared with  FIG.  8   , compare circuit  61  further comprises a comparator  603 , which is configured to generate comparison signal Set 3  based on feedback signal Vfb 3  and reference voltage Vref 3 . Comparator  603  has a non-inverting input terminal to receive reference voltage Vref 3 , an inverting input terminal to receive feedback signal Vfb 3 , and an output terminal to provide comparison signal Set 3  by comparing reference voltage Vref 3  with feedback signal Vfb 3 . When feedback signal Vfb 3  is smaller than reference voltage Vref 3 , comparison signal Set 3  becomes active (e.g. logic high). Logic circuit  600  receives comparison signal Set 1 , comparison signal Set 2 , comparison signal Set 3  and load line data LL, and generates position signal Set based on comparison signal Set 1 , comparison signal Set 2 , comparison signal Set 3  and load line data LL. 
       FIG.  14    schematically shows a truth table of logic circuit  600  of position signal generator  73  in accordance with an embodiment of the present invention. In one embodiment, when load line data LL equals to “00”, and when feedback signal Vfb 1  is smaller than reference voltage Vref 1  (Set 1 =“1”) or feedback signal Vfb 2  is smaller than reference voltage Vref 2  (Set 2 =“1”) or feedback signal Vfb 3  is smaller than reference voltage Vref 3  (Set 3 =“1”), position signal Set becomes active (Set=“1”) to turn ON the at least one switch of switching circuit  21 . In one embodiment, when load line data LL equals to “01”, and when feedback signal Vfb 3  is smaller than reference voltage Vref 3  (Set 3 =“1”), and when feedback signal Vfb 1  is smaller than reference voltage Vref 1  or feedback signal Vfb 2  is smaller than reference voltage Vref 2  (Set 1 =“1” or Set 2 =“1”), position signal Set becomes active (Set=“1”) to turn ON the at least one switch of control circuit  21 . In one embodiment, when load line data LL equals to “10”, and when feedback signal Vfb 1  is smaller than reference voltage Vref 1  (Set 1 =“1”), and when feedback signal Vfb 2  is smaller than reference voltage Vref 2  or feedback signal Vfb 3  is smaller than reference voltage Vref 3  (Set 2 =“1” or Set 3 =“1”), position signal Set becomes active (Set=“1”) to turn ON the at least one switch of switching circuit  21 . In one embodiment, when load line data LL equals to “11”, and when feedback signal Vfb 1  is smaller than reference voltage Vref 1  (Set 1 =“1”), feedback signal Vfb 2  is smaller than reference voltage Vref 2  (Set 2 =“1”), and feedback signal Vfb 3  is smaller than reference voltage Vref 3  (Set 3 =“1”), position signal Set becomes active (Set=“1”) to turn ON the at least one switch of switching circuit  21 . In the example of  FIG.  14   , comparison signals Set 1 -Set 3  and position signal Set is active at a high voltage level. One with ordinary skill in the art should understand that comparison signals Set 1 -Set 3  and position signal Set may also be set active when at a low voltage level. 
       FIG.  15    illustrates an AVP control method  1500  for a DC-DC converter in accordance with an embodiment of the present invention. The AVP control method for DC-DC converters shown in  FIG.  15    comprises steps S 11 -S 15 , wherein the DC-DC converter receives an input voltage, and provides an output voltage and an output current. 
     In step S 11 , receiving a set of adaptive voltage control commands and a voltage identification code, wherein the set of adaptive voltage control commands comprises a first voltage position resistance data to control a slope of a first voltage position curve, a first voltage offset data to participate in controlling an offset of a second voltage position curve, a second voltage position resistance data to control a slope of the second voltage position curve, and a load line data to choose different voltage position curves as a load line within different sections of the output current. 
     In step S 12 , generating a position signal based on the output voltage and the output current under the control of the voltage identification code and the set of adaptive voltage control commands. 
     In step S 13 , generating a switching control signal based on the position signal to control at least one switch in the DC-DC converter. 
     In step S 14 , generating a first voltage position curve based on the voltage identification code and the first voltage position resistance data, and generating a second voltage position curve based on the voltage identification code, the first voltage offset data and the second voltage position resistance data. The offset of the first voltage position curve is controlled by the voltage identification code, the slope of the first voltage position curve is controlled by the first voltage position resistance data, the offset of the second voltage position curve is controlled by the voltage identification code and the first voltage offset data, and the slope of the second voltage position curve is controlled by the second voltage position resistance data. 
     In step S 15 , choosing different voltage position curves as the load line according to the load line data within different sections of the output current, to control the output voltage to vary along the load line as the output current varies. The load line comprises at least the first voltage position curve and the second voltage position curve. 
       FIG.  16    illustrates an AVP control method  1600  for a DC-DC converter comprising steps S 21 -S 25  in accordance with another embodiment of the present invention. 
     In step S 21 , receiving a set of adaptive voltage control commands and a voltage identification code, wherein the set of adaptive voltage control commands comprises a first voltage offset data, a first voltage position resistance data, a second voltage offset data to participate in controlling an offset of a third voltage position curve, a third voltage position resistance data to control a slope of the third voltage position curve, and a load line data. 
     In step S 22 , generating a position signal based on the output voltage and the output current under the control of the voltage identification code and the set of adaptive voltage control commands. 
     In step S 23 , generating a switching control signal based on the position signal to control at least one switch in the DC-DC converter. 
     In step S 24 , generating a first voltage position curve based on the voltage identification code and the first voltage position resistance data, generating a second voltage position curve based on the voltage identification code, the first voltage offset data and the second voltage position resistance data, and generating a third voltage position curve based on the voltage identification code, the second voltage offset data and the third voltage position resistance data. The offset of the first voltage position curve is controlled by the voltage identification code, the slope of the first voltage position curve is controlled by the first voltage position resistance data, the offset of the second voltage position curve is controlled by the voltage identification code and the first voltage offset data, and the slope of the second voltage position curve is controlled by the second voltage position resistance data. The offset of the third voltage position curve is controlled by the voltage identification code and the second voltage offset data, and the slope of the third voltage position curve is controlled by the third voltage position resistance data. 
     In step S 25 , choosing different voltage position curves as the load line within different sections of the output current according to the load line data, to control the output voltage to vary along the load line as the output current varies. The load line comprises at least the first voltage position curve, the second voltage position curve and the third voltage position curve. 
     Obviously many modifications and variations of the present invention are possible in light of the above teachings. It is therefore to be understood that within the scope of the appended claims the invention may be practiced otherwise than as specifically described. It should be understood, of course, the foregoing disclosure relates only to a preferred embodiment (or embodiments) of the invention and that numerous modifications may be made therein without departing from the spirit and the scope of the invention as set forth in the appended claims. Various modifications are contemplated and they obviously will be resorted to by those skilled in the art without departing from the spirit and the scope of the invention as hereinafter defined by the appended claims as only a preferred embodiment(s) thereof has been disclosed.