Patent Publication Number: US-2022223491-A1

Title: Semiconductor package structure

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This application claims the benefit of U.S. Provisional Application No. 63/136,685 filed on Jan. 13, 2021, the entirety of which are incorporated by reference herein. 
    
    
     BACKGROUND OF THE INVENTION 
     Field of the Invention 
     The present invention is related to semiconductor packaging technology, and in particular to a semiconductor package structure. 
     Description of the Related Art 
     With the increase in demand for smaller devices that can perform more functions, package-on-package (PoP) technology has become increasingly popular. PoP technology vertically stacks two or more package structures. By stacking the package structures, the amount of area on the motherboard that it takes up can be reduced, and thus the cell phone&#39;s battery capacity can be increased. 
     However, although existing semiconductor package structures are generally adequate, they are not satisfactory in every respect. For example, in comparison with package structures which are disposed side-by-side, the stacked package structures share less projection area resources, which makes thermal dissipation worse. Thermal dissipation is a critical problem that needs to be solved since it affects the performance of semiconductor package structures. Therefore, further improvements in semiconductor package structures are required. 
     BRIEF SUMMARY OF THE INVENTION 
     Semiconductor package structures are provided. An exemplary embodiment of a semiconductor package structure includes a first redistribution layer, a semiconductor die, a thermal spreader, and a molding material. The semiconductor die is disposed over the first redistribution layer. The thermal spreader is disposed over the semiconductor die. The molding material surrounds the semiconductor die and the thermal spreader. 
     Another exemplary embodiment of a semiconductor package structure includes a substrate, a semiconductor die, a thermal spreader, and a molding material. The substrate has a wiring structure. The semiconductor die is disposed over the substrate and electrically coupled to the wiring structure. The thermal spreader is disposed over the semiconductor die. The molding material is disposed over the substrate and surrounds the semiconductor die and the thermal spreader. 
     Yet another exemplary embodiment of a semiconductor package structure includes a first substrate, a semiconductor die, and a first thermal spreader. The first substrate has a wiring structure. The semiconductor die is disposed over the first substrate and is electrically coupled to the wiring structure. The first thermal spreader is bonded onto the first substrate via a first thermal interface material and is thermally coupled to the semiconductor die, wherein the first thermal interface material and the semiconductor die are disposed on opposite sides of the first thermal spreader. 
     A detailed description is given in the following embodiments with reference to the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The present invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein: 
         FIG. 1  is a cross-sectional view of an exemplary semiconductor package structure in accordance with some embodiments; 
         FIG. 2  is a top view of an exemplary first package structure of a semiconductor package structure in accordance with some embodiments; 
         FIG. 3  is a cross-sectional view of an exemplary semiconductor package structure in accordance with some embodiments; 
         FIG. 4  is a top view of an exemplary first package structure of a semiconductor package structure in accordance with some embodiments; 
         FIG. 5A  is a cross-sectional view of an exemplary semiconductor package structure in accordance with some embodiments; 
         FIG. 5B  is a cross-sectional view of an exemplary semiconductor package structure in accordance with some embodiments; 
         FIG. 6  is a cross-sectional views of an exemplary semiconductor package structure in accordance with some embodiments; and 
         FIG. 7  is a cross-sectional view of an exemplary semiconductor package structure in accordance with some embodiments. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is determined by reference to the appended claims. 
     The present invention will be described with respect to particular embodiments and with reference to certain drawings, but the invention is not limited thereto and is only limited by the claims. The drawings described are only schematic and are non-limiting. In the drawings, the size of some of the elements may be exaggerated for illustrative purposes and not drawn to scale. The dimensions and the relative dimensions do not correspond to actual dimensions in the practice of the invention. 
     A semiconductor package structure with a thermal spreader is described in accordance with some embodiments of the present disclosure. The semiconductor package structure includes a thermal spreader adjacent to the thermal source, so that the efficiency of thermal dissipation can be increased, and thus the performance of the semiconductor package structure can be improved. 
       FIG. 1  is a cross-sectional view of a semiconductor package structure  100  in accordance with some embodiments of the disclosure. Additional features can be added to the semiconductor package structure  100 . Some of the features described below can be replaced or eliminated for different embodiments. To simplify the diagram, only a portion of the semiconductor package structure  100  is illustrated. 
     As shown in  FIG. 1 , the semiconductor package structure  100  includes a first package structure  100   a  and a second package structure  100   b  stacked vertically, in accordance with some embodiments. As shown in  FIG. 1 , the first package structure  100   a  includes a substrate  102 , in accordance with some embodiments. The substrate  102  may have a wiring structure therein. In some embodiments, the wiring structure in the substrate  102  includes conductive layers, conductive vias, conductive pillars, the like, or a combination thereof. The wiring structure in the substrate  102  may be formed of metal, such as copper, aluminum, the like, or a combination thereof. 
     The wiring structure in the substrate  102  may be disposed in inter-metal dielectric (IMD) layers. In some embodiments, the IMD layers may be formed of organic materials, such as a polymer base material, non-organic materials, such as silicon nitride, silicon oxide, silicon oxynitride, the like, or a combination thereof. The substrate  102  may include an insulating core (not shown), such as a fiberglass reinforced resin core, to prevent the substrate  102  from warping. 
     It should be noted that the configuration of the substrate  102  shown in the figures is exemplary only and is not intended to limit the present disclosure. Any desired semiconductor element may be formed in and on the substrate  102 . However, in order to simplify the diagram, only the flat substrate  102  is illustrated. 
     As shown in  FIG. 1 , the first package structure  100   a  includes a plurality of conductive terminals  104  disposed below the substrate  102  and electrically coupled to the wiring structure in the substrate  102 , in accordance with some embodiments. The conductive terminals  104  may be formed of conductive materials, such as metal. In some embodiments, the conductive terminals  104  includes microbumps, controlled collapse chip connection (C4) bumps, solder balls, ball grid array (BGA) balls, the like, or a combination thereof. 
     As shown in  FIG. 1 , the first package structure  100   a  includes a semiconductor die  108  disposed over the substrate  102 , in accordance with some embodiments. In some embodiments, the semiconductor die  108  includes a system-on-chip (SoC) die, a logic device, a memory device, a radio frequency (RF) device, the like, or any combination thereof. For example, the semiconductor die  108  may include a micro control unit (MCU) die, a microprocessor unit (MPU) die, a power management integrated circuit (PMIC) die, a radio frequency front end (RFFE) die, an accelerated processing unit (APU) die, a central processing unit (CPU) die, a graphics processing unit (GPU) die, an input-output (IO) die, a dynamic random access memory (DRAM) controller, a static random-access memory (SRAM), a high bandwidth memory (HBM), an application processor (AP) die, the like, or any combination thereof. 
     According to some embodiments, the first package structure  100   a  may include more than one semiconductor dies. In addition, the first package structure  100   a  may also include one or more passive components (not illustrated) adjacent to the semiconductor die  108 , such as resistors, capacitors, inductors, the like, or a combination thereof. 
     The semiconductor die  108  may be electrically coupled to the wiring structure in the substrate  102  through a plurality of conductive structures  106 . As shown in  FIG. 1 , the conductive structures  106  may be disposed between the substrate  102  and the semiconductor die  108 . In some embodiments, the conductive structures  106  are formed of conductive materials, such as metal. The conductive structures  106  may include conductive pillars, microbumps, controlled collapse chip connection (C4) bumps, solder balls, ball grid array (BGA) balls, the like, or a combination thereof. 
     As shown in  FIG. 1 , the first package structure  100   a  includes a thermal spreader  112  disposed over the semiconductor die  108 , in accordance with some embodiments. The thermal spreader  112  may be disposed directly above the semiconductor die  108 . The thermal spreader  112  may have a higher thermal conductivity than the semiconductor die  108  to improve the efficiency of thermal dissipation of the semiconductor package structure  100 . In some embodiments, the thermal spreader  112  includes a metal, a dummy semiconductor die, or a combination thereof. For example, the thermal spreader  112  may include copper, aluminum, silicon, germanium, or any suitable materials. 
     As shown in  FIG. 1 , the thermal spreader  112  is bonded onto the semiconductor die  108  through an adhesion layer  110 , in accordance with some embodiments. The heat from the thermal source (e.g., the semiconductor die  108 ) may be transferred to the thermal spreader  112  through the adhesion layer  110 . In some embodiments, the adhesion layer  110  includes a die attach film (DAF), an epoxy, the like, or a combination thereof. The thermal conductivity of the thermal spreader  112  may be higher than that of the semiconductor die  108  and that of the adhesion layer  110 . 
     As shown in  FIG. 1 , the first package structure  100   a  includes a plurality of bump structures  114  disposed over the substrate  102  and adjacent to the semiconductor die  108 , in accordance with some embodiments. The bump structures  114  may be electrically coupled to the wiring structure in the substrate  102 . The bump structures  114  may be formed of conductive materials, such as metal. In some embodiments, the bump structures  114  include solder balls. 
     As shown in  FIG. 1 , the bump structures  114  may be disposed on opposite sides of the semiconductor die  108  and the thermal spreader  112 . The configuration of the bump structures  114  shown in the figures is exemplary only and is not intended to limit the present disclosure. 
     As shown in  FIG. 1 , the first package structure  100   a  includes a plurality of conductive pillars  116  disposed directly above the bump structures  114 , in accordance with some embodiments. The conductive pillars  116  may be electrically coupled to the wiring structure in the substrate  102  through the bump structures  114 . In some embodiments, the conductive pillars  116  may be formed of metal, such as copper, tungsten, the like, or a combination thereof. 
     As shown in  FIG. 1 , the first package structure  100   a  includes a molding material  118  surrounding the semiconductor die  108 , the thermal spreader  112 , the bump structures  114 , and the conductive pillars  116 , in accordance with some embodiments. The molding material  118  may adjoin the sidewalls of the semiconductor die  108  and the thermal spreader  112 , and may cover the top surface of the thermal spreader  112  and the top surface of the substrate  102 . 
     In some embodiments, the molding material  118  includes a nonconductive material, such as a moldable polymer, an epoxy, a resin, the like, or a combination thereof. As shown in  FIG. 1 , the top surface of the molding material  118  and the top surfaces of the conductive pillars  116  may be substantially coplanar. The sidewalls of the molding material  118  may be substantially coplanar with the sidewalls of the substrate  102  and the interposer  120  (described below). 
     As shown in  FIG. 1 , the molding material  118  may fill in gaps between the conductive pillars  116 , and between the semiconductor die  108  and the conductive pillars  116 . The molding material  118  may protect the semiconductor die  108 , the bump structures  114 , and the conductive pillars  116  from the environment, thereby preventing these components from damage due to, for example, the stress, the chemicals and/or the moisture. 
     As shown in  FIG. 1 , the first package structure  100   a  includes an interposer  120  disposed over the molding material  118 , in accordance with some embodiments. The interposer  120  and the thermal spreader  112  may be spaced apart by the molding material  118 . 
     The interposer  120  may have a wiring structure therein. The wiring structure in the interposer  120  may be electrically coupled to the substrate  102  through the conductive pillars  116  and the bump structures  114 . In some embodiments, the wiring structure in the interposer  120  includes conductive layers, conductive vias, conductive pillars, the like, or a combination thereof. The wiring structure in the interposer  120  may be formed of metal, such as copper, aluminum, the like, or a combination thereof. 
     The wiring structure in the interposer  120  may be disposed in inter-metal dielectric (IMD) layers. In some embodiments, the IMD layers may be formed of organic materials, such as a polymer base material, non-organic materials, such as silicon nitride, silicon oxide, silicon oxynitride, the like, or a combination thereof. 
     It should be noted that the configuration of the interposer  120  shown in the figures is exemplary only and is not intended to limit the present disclosure. Any desired semiconductor element may be formed in and on the interposer  120 . However, in order to simplify the diagram, only the flat interposer  120  is illustrated. 
     As shown in  FIG. 1 , the second package structure  100   b  is disposed over the first package structure  100   a  and is electrically coupled to the wiring structure in the interposer  120  through a plurality of conductive terminals  122 , in accordance with some embodiments. The conductive terminals  122  may be formed of conductive materials, such as metal. In some embodiments, the conductive terminals  122  include microbumps, controlled collapse chip connection (C4) bumps, solder balls, ball grid array (BGA) balls, the like, or a combination thereof. 
     As shown in  FIG. 1 , the second package structure  100   b  includes a substrate  124 , in accordance with some embodiments. The substrate  124  may have a wiring structure therein. In some embodiments, the wiring structure of the substrate  124  includes conductive layers, conductive vias, conductive pillars, the like, or a combination thereof. The wiring structure of the substrate  124  may be formed of metal, such as copper, titanium, tungsten, aluminum, the like, or a combination thereof. 
     The wiring structure of the substrate  124  may be disposed in inter-metal dielectric (IMD) layers. In some embodiments, the IMD layers may be formed of organic materials, such as a polymer base material, a non-organic material, such as silicon nitride, silicon oxide, silicon oxynitride, the like, or a combination thereof. Any desired semiconductor element may be formed in and on the substrate  124 . However, in order to simplify the diagram, only the flat substrate  124  is illustrated. 
     As shown in  FIG. 1 , the second package structure  100   b  includes semiconductor components  126  disposed over the substrate  124 , in accordance with some embodiments. The semiconductor components  126  may include the same or different devices. For example, the semiconductor components  126  may include memory dies, such as a dynamic random access memory (DRAM). 
     According to some embodiments, the second package structure  100   b  may include more than two semiconductor components  126 . In addition, the second package structure  100   b  may also include one or more passive components (not illustrated), such as resistors, capacitors, inductors, the like, or a combination thereof. 
       FIG. 2  is a top view of a first package structure  100   a  of a semiconductor package structure  100  in accordance with some embodiments. To simplify the diagram, only a portion of the semiconductor package structure  100   a  is illustrated in  FIG. 2 . The first package structure  100   a  in  FIG. 1  may be a cross-sectional view taken along a sectional line A-A′ in  FIG. 2 . 
     As shown in  FIG. 2 , the thermal spreader  112  has a larger projection area on the substrate  102  than that of the semiconductor die  108 , in accordance with some embodiments. As a result, the efficiency of thermal dissipation can be increased. In some embodiments, the thermal spreader  112  has a dimension greater than that of the semiconductor die  108  in the first direction D 1 , as shown in  FIG. 2 . The sidewalls of the thermal spreader  112  may be substantially aligned with the sidewalls of the semiconductor die  108  in the second direction D 2 . 
     The configurations of the thermal spreader  112  and the semiconductor die  108  shown in the figures are exemplary only and are not intended to limit the present disclosure. For example, in some other embodiments, the thermal spreader  112  may have a dimension greater than that of the semiconductor die  108  in the second direction D 2 , and the sidewalls of the thermal spreader  112  may be substantially aligned with the sidewalls of the semiconductor die  108  in the first direction D 1 . Alternatively, the thermal spreader  112  may have dimensions greater than that of the semiconductor die  108  in both of the first direction D 1  and the second direction D 2 . 
     As shown in  FIG. 2 , the conductive pillars  116  are disposed on opposite sides of the semiconductor die  108  and the thermal spreader  112 , in accordance with some embodiments. The conductive pillars  116  may be disposed along the first direction D 1 . The configuration of the conductive pillars  116  shown in the figures is exemplary only and is not intended to limit the present disclosure. For example, the conductive pillars  116  may also be disposed along the first direction D 1  and the second direction D 2  so that the conductive pillars  116  may surround the semiconductor die  108  and the thermal spreader  112 . 
       FIG. 3  is a cross-sectional view of a semiconductor package structure  300 , in accordance with some embodiments of the disclosure. It should be noted that the semiconductor package structure  300  may include the same or similar components as that of the semiconductor package structure  100 , which is illustrated in  FIG. 1 , and for the sake of simplicity, those components will not be discussed in detail again. In the following embodiments, a thermal spreader is disposed in a fan out package structure. 
     As shown in  FIG. 3 , the semiconductor package structure  300  includes a first package structure  300   a  and a second package structure  300   b  stacked vertically, in accordance with some embodiments. The first package structure  300   a  may have a frontside and a backside opposite to the frontside. The first package structure  300   a  may have a first redistribution layer  302  on the frontside and a second redistribution layer  322  on the backside. Therefore, the first redistribution layer  302  may be also referred to as the frontside redistribution layer  302 , and the second redistribution layer  322  may be also referred to as the backside redistribution layer  322 . 
     The first redistribution layer  302  may include one or more conductive layers and passivation layers, wherein the conductive layers may be disposed in the passivation layers. The conductive layers may include metal, such as copper, titanium, tungsten, aluminum, the like, or a combination thereof. 
     In some embodiments, the passivation layers include a polymer layer, for example, polyimide (PI), polybenzoxazole (PBO), benzocyclobutene (BCB), epoxy, the like, or a combination thereof. Alternatively, the passivation layers may include a dielectric layer, such as silicon oxide, silicon nitride, silicon oxynitride, the like, or a combination thereof. The material of the second redistribution layer  322  may be similar to the material of the first redistribution layer  302 , and will not be repeated. 
     As shown in  FIG. 3 , the first redistribution layer  302  includes more conductive layers and passivation layers than the second redistribution layer  322 , in accordance with some embodiments. The first redistribution layer  302  may be thicker than the second redistribution layer  322 , but the present disclosure is not limit thereto. For example, the second redistribution layer  322  may be thicker than or substantially equal to the first redistribution layer  302 . 
     As shown in  FIG. 3 , the first package structure  300   a  includes a plurality of conductive terminals  304  disposed below the first redistribution layer  302  and electrically coupled to the first redistribution layer  302 , in accordance with some embodiments. The conductive terminals  304  may be formed of conductive materials, such as metal. In some embodiments, the conductive terminals  304  includes microbumps, controlled collapse chip connection (C4) bumps, solder balls, ball grid array (BGA) balls, the like, or a combination thereof. 
     As shown in  FIG. 3 , the first package structure  300   a  includes a capacitor  306  disposed below the first redistribution layer  302  and electrically coupled to the first redistribution layer  302 , in accordance with some embodiments. The capacitor  306  may be disposed between the conductive terminals  304 . 
     As shown in  FIG. 3 , the first package structure  300   a  includes a semiconductor die  310  disposed over the first redistribution layer  302 , in accordance with some embodiments. The semiconductor die  310  may be similar to the semiconductor die  108  as shown in  FIG. 1 , and will not be repeated. 
     According to some embodiments, the first package structure  300   a  may include more than one semiconductor dies. In addition, the first package structure  300   a  may also include one or more passive components (not illustrated) adjacent to the semiconductor die  310 , such as resistors, capacitors, inductors, the like, or a combination thereof. 
     The semiconductor die  310  may be electrically coupled to the first redistribution layer  302  through a plurality of conductive structures  308 . As shown in  FIG. 3 , the conductive structures  308  may be disposed between the first redistribution layer  302  and the semiconductor die  310 . The capacitor  306  may be electrically coupled to the semiconductor die  310  through the first redistribution layer  302  and the conductive structures  308 . 
     In some embodiments, the conductive structures  308  are formed of conductive materials, such as metal. The conductive structures  308  may include conductive pillars, microbumps, controlled collapse chip connection (C4) bumps, solder balls, ball grid array (BGA) balls, the like, or a combination thereof. 
     As shown in  FIG. 3 , the first package structure  300   a  includes a thermal spreader  314  disposed over the semiconductor die  310 , in accordance with some embodiments. The thermal spreader  314  may be disposed directly above the semiconductor die  310 . The thermal spreader  314  may have a higher thermal conductivity than the semiconductor die  310  to improve the efficiency of thermal dissipation of the semiconductor package structure  300 . In some embodiments, the thermal spreader  314  includes a metal, a dummy semiconductor die, or a combination thereof. For example, the thermal spreader  314  may include copper, aluminum, silicon, germanium, or any suitable materials. 
     As shown in  FIG. 3 , the thermal spreader  314  is bonded onto the semiconductor die  310  through an adhesion layer  312  and bonded onto the second redistribution layer  322  through an adhesion layer  316 , in accordance with some embodiments. That is, the adhesion layer  316  may be in contact with the second redistribution layer  322  without a molding material extended therebetween. 
     The heat from the thermal source (e.g., the semiconductor die  310 ) may be transferred to the thermal spreader  314  through the adhesion layer  312 , and may further be transferred to the second redistribution layer  322  through the adhesion layer  316 . Therefore, the second redistribution layer  322  may also be served as a thermal dissipation path. In some embodiments, the adhesion layer  312  and the adhesion layer  316  each independently includes a die attach film (DAF), an epoxy, the like, or a combination thereof. The thermal conductivity of the thermal spreader  314  may be higher than that of the semiconductor die  310 , that of the adhesion layer  312 , and that of the adhesion layer  316 . 
     As shown in  FIG. 3 , the first package structure  300   a  includes a plurality of conductive pillars  318  adjacent to the semiconductor die  310  and the thermal spreader  314 , in accordance with some embodiments of the disclosure. The conductive pillars  318  may be formed of metal, such as copper, tungsten, the like, or a combination thereof. In some embodiments, the conductive pillars  318  are formed by a plating process or any other suitable process. 
     As shown in  FIG. 3 , the conductive pillars  318  may have substantially vertical sidewalls. The conductive pillars  318  may be disposed between the first redistribution layer  302  and the second redistribution layer  322 , and may be electrically coupled the first redistribution layer  302  to the second redistribution layer  322 . 
     The configuration of the conductive pillars  318  shown in the figures is exemplary only and is not intended to limit the present disclosure. For example, the number of conductive pillars  318  may be different on opposite sides of the first semiconductor die  312  and the second semiconductor die  306 . 
     As shown in  FIG. 3 , the first package structure  300   a  includes a molding material  320  surrounding the semiconductor die  310 , the thermal spreader  314 , and the conductive pillars  318 , in accordance with some embodiments. The molding material  320  may adjoin the sidewalls of the semiconductor die  310  and the thermal spreader  314 , and may cover the top surface of the first redistribution layer  302  and the bottom surface of the second redistribution layer  322 . 
     As shown in  FIG. 3 , the molding material  320  may fill in gaps between the conductive pillars  318 , and between the semiconductor die  310  and the thermal spreader  314  and the conductive pillars  318 . The molding material  320  may protect the semiconductor die  310 , the thermal spreader  314 , and the conductive pillars  318  from the environment, thereby preventing these components from damage due to, for example, the stress, the chemicals and/or the moisture. 
     In some embodiments, the molding material  320  includes a nonconductive material, such as a moldable polymer, an epoxy, a resin, the like, or a combination thereof. As shown in  FIG. 3 , the top surface of the molding material  320  and the top surfaces of the conductive pillars  318  may be substantially coplanar. The sidewalls of the molding material  320  may be substantially coplanar with the sidewalls of the first redistribution layer  302  and the sidewalls of the second redistribution layer  322 . 
     As shown in  FIG. 3 , the second redistribution layer  322  is disposed over the first semiconductor die  312 , in accordance with some embodiments. The second redistribution layer  322  may cover the top surface of the thermal spreader  314 , the top surfaces of the conductive pillars  318 , and the top surface of the molding material  320 . 
     As shown in  FIG. 3 , the second package structure  300   b  is disposed over the first package structure  300   a  and is electrically coupled to the second redistribution layer  322  through a plurality of conductive terminals  324 , in accordance with some embodiments. The conductive terminals  324  may be similar to the conductive terminals  122  as shown in  FIG. 1 , and will not be repeated. 
     As shown in  FIG. 3 , the second package structure  300   b  includes a substrate  326  and semiconductor components  328  disposed over the substrate  326 , in accordance with some embodiments. The substrate  326  and the semiconductor components  328  may be similar to the substrate  124  and the semiconductor components  126  as shown in  FIG. 1 , respectively, and will not be repeated. 
       FIG. 4  is a top view of a first package structure  300   a  of a semiconductor package structure  300  in accordance with some embodiments. To simplify the diagram, only a portion of the semiconductor package structure  300   a  is illustrated in  FIG. 4 . The first package structure  300   a  in  FIG. 3  may be a cross-sectional view taken along a sectional line B-B′ in  FIG. 4 . 
     As shown in  FIG. 4 , the thermal spreader  314  has a larger projection area on the first redistribution layer  302  than that of the semiconductor die  310 , in accordance with some embodiments. As a result, the efficiency of thermal dissipation can be increased. In some embodiments, the thermal spreader  314  has a dimension greater than that of the semiconductor die  310  in the first direction D 1 , as shown in  FIG. 4 . The sidewalls of the thermal spreader  314  may be substantially aligned with the sidewalls of the semiconductor die  310  in the second direction D 2 . 
     The configurations of the thermal spreader  314  and the semiconductor die  310  shown in the figures are exemplary only and are not intended to limit the present disclosure. For example, in some other embodiments, the thermal spreader  314  may have a dimension greater than that of the semiconductor die  310  in the second direction D 2 , and the sidewalls of the thermal spreader  314  may be substantially aligned with the sidewalls of the semiconductor die  310  in the first direction D 1 . Alternatively, the thermal spreader  314  may have dimensions greater than that of the semiconductor die  310  in both of the first direction D 1  and the second direction D 2 . 
     As shown in  FIG. 4 , the conductive pillars  318  are disposed on opposite sides of the semiconductor die  310  and the thermal spreader  314 , in accordance with some embodiments. The conductive pillars  318  may be disposed along the first direction D 1 . The configuration of the conductive pillars  318  shown in the figures is exemplary only and is not intended to limit the present disclosure. For example, the conductive pillars  318  may also be disposed along the first direction D 1  and the second direction D 2  so that the conductive pillars  318  may surround the semiconductor die  310  and the thermal spreader  314 . 
     In the above embodiments, since the thermal spreader  314  is bonded onto the second redistribution layer  322 , the second redistribution layer  322  may also be a thermal dissipation path. That is, the heat from the semiconductor die  310  can be transferred to the thermal spreader  314  and the second redistribution layer  322  besides the first redistribution layer  302 . As a result, the efficiency of thermal dissipation can be increased. 
       FIG. 5A  is a cross-sectional view of a semiconductor package structure  500   a , in accordance with some embodiments of the disclosure.  FIG. 5A  illustrates an enlarged region between the conductive terminals  304  and  324  of the semiconductor package structure  300  of  FIG. 3 , in accordance with some embodiments of the disclosure. 
     It should be noted that the semiconductor package structure  500   a  may include the same or similar components as that of the semiconductor package structure  300 , which is illustrated in  FIG. 3 , and for the sake of simplicity, those components will not be discussed in detail again. In the following embodiments, an adhesion layer is disposed in a second redistribution layer. 
     As shown in  FIG. 5A , the semiconductor package structure  500   a  includes a first redistribution layer  302  and a second redistribution layer  322 , in accordance with some embodiments. The first redistribution layer  302  may include one or more conductive layers  302   c  and passivation layers  302   p , wherein the conductive layers  302   c  may be disposed in the passivation layers  302   p.    
     The second redistribution layer  322  may include one or more conductive layers  322   c  and passivation layers  322   p , wherein the conductive layers  322   c  may be disposed in the passivation layers  322   p . In some embodiments, one of the passivation layers  322   p  of the second redistribution layer  322  is in contact with the molding material  320 , and is referred to as a first passivation layer  322   p   1 . 
     As shown in  FIG. 5A , the adhesion layer  316  may be in contact with the passivation layers  322   p . The first passivation layer  322   p   1  may have an opening for disposing the adhesion layer  316 . In some embodiments, the adhesion layer  316  is embedded in the first passivation layer  322   p   1 , as shown in  FIG. 5A . In these embodiments, the adhesion layer  316  may be in contact with the conductive layers  322   c  over the first passivation layers  322   p   1 . 
     Alternatively, in some other embodiments, the adhesion layer  316  is not embedded in the first passivation layer  322   p   1 , and is disposed on the bottom surface of the second redistribution layer  322 , as shown in  FIG. 3 . That is, the first passivation layer  322   p   1  does not have an opening. In these embodiments, the adhesion layer  316  may be in contact with the conductive layers in the first passivation layer  322   p   1 . The molding material  320  may cover sidewalls of the adhesion layer  316 . In particular, the top surface of the molding material  320  may be substantially coplanar with the top surface of the adhesion layer  316 . 
     As shown in  FIG. 5A , the adhesion layer  316  is fully embedded in the first passivation layer  322   p   1 , and the top surface of the thermal spreader  314  is substantially coplanar with the top surface of the molding maternal  320 , in accordance with some embodiments. The configurations of the first passivation layer  322   p   1  and the adhesion layer  316  shown in the figures are exemplary only, and may vary with the thickness of the first passivation layer  322   p   1  and the thickness of the adhesion layer  316 . 
     For example, in the embodiments where the thickness of the first passivation layer  322   p   1  is greater than the thickness of the adhesion layer  316 , the adhesion layer  316  may be fully embedded in the first passivation laver  322   p   1 , and the thermal spreader  314  may be partially embedded in the second redistribution layer  322 . In particular, the first passivation layer  322   p   1  may be in contact with the interface of the adhesion layer  316  and the thermal spreader  314 . 
     Alternatively, in the embodiments where the thickness of the first passivation layer  322   p   1  is less than the thickness of the adhesion layer  316 , the adhesion layer  316  may be partially embedded in the second redistribution layer  322 . In particular, the molding material  320  may be in contact with the interface of the adhesion layer  316  and the thermal spreader  314 . 
       FIG. 5B  is a cross-sectional view of a semiconductor package structure  500   b , in accordance with some embodiments of the disclosure.  FIG. 5B  illustrates an enlarged region between conductive terminals  304  and  324  of the semiconductor package structure  300  of  FIG. 3 , in accordance with some embodiments of the disclosure. 
     It should be noted that the semiconductor package structure  500   b  may include the same or similar components as that of the semiconductor package structure  300 , which is illustrated in  FIG. 3 , and for the sake of simplicity, those components will not be discussed in detail again. In the following embodiments, a thermal spreader is disposed on the second redistribution layer without an adhesion layer therebetween. 
     As shown in  FIG. 5B , the semiconductor package structure  500   b  includes a first redistribution layer  302  and a second redistribution layer  322 , in accordance with some embodiments. The first redistribution layer  302  may include one or more conductive layers  302   c  and passivation layers  302   p , wherein the conductive layers  302   c  may be disposed in the passivation layers  302   p.    
     The second redistribution layer  322  may include one or more conductive layers  322   c  and passivation layers  322   p , wherein the conductive layers  322   c  may be disposed in the passivation layers  322   p . In some embodiments, one of the passivation layers  322   p  of the second redistribution layer  322  is in contact with the molding material  320 , and is referred to as a first passivation layer  322   p   1 . 
     As shown in  FIG. 5B , the semiconductor package structure  500   b  includes a thermal spreader  502  disposed on the second redistribution layer  322 , in accordance with some embodiments. The thermal spreader  502  may be formed by the process of forming the conductive layers  322   c , such as plating or any suitable processes. 
     The thermal spreader  502  may include a material similar to the material of the conductive layers  322   c . In some embodiments, the thermal spreader  502  includes conductive materials, such as metal. For example, the thermal spreader  502  may include copper, titanium, tungsten, aluminum, the like, or a combination thereof. 
     As shown in  FIG. 5B , the thermal spreader  502  may be in contact with the passivation layers  322   p . The first passivation layer  322   p   1  may have an opening for disposing the thermal spreader  502 . In some embodiments, the thermal spreader  502  is partially embedded in the first passivation layer  322   p   1 , as shown in  FIG. 5B . In these embodiments, the thermal spreader  502  may be in contact with the conductive layers  322   c  over the first passivation layers  322   p   1 . 
     Alternatively, in some other embodiments, the thermal spreader  502  is not embedded in the first passivation layer  322   p   1 , and is disposed on the bottom surface of the second redistribution layer  322 . That is, the first passivation layer  322   p   1  does not have an opening. In these embodiments, the thermal spreader  502  may be in contact with the conductive layers in the first passivation layer  322   p   1 . In particular, the top surface of the molding material  320  may be substantially coplanar with the top surface of the thermal spreader  502 . 
     As shown in  FIG. 5B , the portion of the thermal spreader  502  in the first passivation layer  322   p   1  (referred to as a first portion) and the other portion of the thermal spreader  502  (referred to as a second portion) are illustrated as one component, but the present disclosure is not limit thereto. For example, according to some other embodiments, the thermal spreader  502  may have an interface between the first portion of the thermal spreader  502  and the second portion of the thermal spreader  502 , such as when the first portion of the thermal spreader  502  and the second portion of the thermal spreader  502  are formed in different processes. 
     Since the thermal spreader  314  is formed in contact with the second redistribution layer  322 , an adhesion layer formed therebetween can be omitted. Consequently, the heat from the semiconductor die  310  can be directly transferred to the second redistribution layer  322 . In addition, the thermal spreader  314  may be formed during the process of forming the second redistribution layer  322 , so that process steps can be reduced. 
       FIG. 6  is a cross-sectional view of a semiconductor package structure  600 , in accordance with some embodiments of the disclosure. It should be noted that the semiconductor package structure  600  may include the same or similar components as that of the semiconductor package structure  300 , which is illustrated in  FIG. 3 , and for the sake of simplicity, those components will not be discussed in detail again. In the following embodiments, a thermal spreader is disposed in a three-dimensional integrated circuit (3D IC) package structure. 
     As shown in  FIG. 6 , the first package structure  300   a  includes a first semiconductor die  602  and a second semiconductor die  606  stacked vertically over the first redistribution layer  302 , in accordance with some embodiments. In some embodiments, each of the first semiconductor die  602  and the second semiconductor die  606  may be similar to the semiconductor die  108  as shown in  FIG. 1 , and will not be repeated. 
     According to some embodiments, the first package structure  300   a  may include more than two semiconductor dies. In addition, the first package structure  300   a  may also include one or more passive components (not illustrated) adjacent to the first semiconductor die  602  and/or the second semiconductor die  606 , such as resistors, capacitors, inductors, the like, or a combination thereof. 
     In some embodiments, the first semiconductor die  602  includes a plurality of through vias  604  therein, which are electrically coupled to the first redistribution layer  302 . The second semiconductor die  606  may be electrically coupled to the first redistribution layer  302  through the through vias  604 . 
     The through vias  604  may be formed of metal, such as copper, tungsten, the like, or a combination thereof. As shown in  FIG. 6 , the through vias  604  may have substantially vertical sidewalls and may extend from the top surface of the first semiconductor die  602  to the bottom surface of the first semiconductor die  602 , but the present disclosure is not limit thereto. The through vias  604  may have other configurations and numbers. 
     As shown in  FIG. 6 , the first package structure  300   a  includes a thermal spreader  610  disposed over the second semiconductor die  606 , in accordance with some embodiments. The thermal spreader  610  may be disposed directly above the second semiconductor die  606 . The thermal spreader  610  may have a higher thermal conductivity than the second semiconductor die  606  to improve the efficiency of thermal dissipation of the semiconductor package structure  600 . In some embodiments, the thermal spreader  610  includes a metal, a dummy semiconductor die, or a combination thereof. For example, the thermal spreader  610  may include copper, aluminum, silicon, germanium, or any suitable materials. 
     As shown in  FIG. 6 , the thermal spreader  610  is bonded onto the second semiconductor die  606  through an adhesion layer  608  and is bonded onto the second redistribution layer  322  through an adhesion layer  614 , in accordance with some embodiments. That is, the adhesion layer  614  may be in contact with the second redistribution layer  322  without a molding material extended therebetween. 
     The heat from the thermal source (e.g., the first semiconductor die  602  and the second semiconductor die  606 ) may be transferred to the thermal spreader  610  through the adhesion layer  608 , and may further be transferred to the second redistribution layer  322  through the adhesion layer  614 . Therefore, the second redistribution layer  322  may also be served as a thermal dissipation path. In some embodiments, the adhesion layer  608  and the adhesion layer  614  each independently includes a die attach film (DAF), an epoxy, the like, or a combination thereof. The thermal conductivity of the thermal spreader  610  may be higher than that of the second semiconductor die  606 , that of the adhesion layer  608 , and that of the adhesion layer  614 . 
     Similar to above description regarding to the first package structure  300   a  in  FIG. 4 , the thermal spreader  610  may have a larger projection area on the first redistribution layer  302  than that of the second semiconductor die  606  to increase the efficiency of thermal dissipation. Furthermore, although not illustrated, the projection area of the thermal spreader  610  on the first redistribution layer  302  may also be larger than that of the first semiconductor die  602 . 
     The configurations of the thermal spreader  610 , the first semiconductor die  602 , the second semiconductor die  606 , and the conductive pillars  318  may be similar to the description regarding to the first package structure  300   a  in  FIG. 4 . For example, the thermal spreader  610  may have a dimension which is greater than that of the first semiconductor die  602  and/or the second semiconductor die  606  in the first direction D 1 . In addition, the sidewalls of the thermal spreader  610  may be substantially aligned with the sidewalls of the semiconductor die  602  and/or the sidewalls of the second semiconductor die  606  in the second direction D 2 . The conductive pillars  318  may be disposed along the first direction D 1 . 
     The details may refer to the description regarding to the first package structure  300   a  in  FIG. 4  and will not be repeated. It should be noted that the configurations of the thermal spreader  610 , the first semiconductor die  602 , the second semiconductor die  606 , and the conductive pillars  318  are exemplary only and are not intended to limit the present disclosure. 
     The configurations of the thermal spreader  610 , the adhesion layer  614 , and the second redistribution layer  322  may be similar to the description regarding to the semiconductor package structure  500   a  in  FIG. 5A  or the description regarding to the semiconductor package structure  500   b  in  5 B. For example, the adhesion layer  614  and/or the thermal spreader  610  may be partially embedded in the second redistribution layer  322  according to some embodiments. The adhesion layer  614  may be omitted according to some other embodiments. 
     The details may refer to the description regarding to the semiconductor package structure  500   a  in  FIG. 5A  or the description regarding to the semiconductor package structure  500   b  in  5 B, and will not be repeated. It should be noted that the configurations of the thermal spreader  610 , the adhesion layer  614 , and the second redistribution layer  322  are exemplary only and are not intended to limit the present disclosure. 
     Referring back to  FIG. 6 , the first package structure  300   a  includes a molding material  612  surrounding the second semiconductor die  606 , the adhesion layer  608 , and the thermal spreader  610 , in accordance with some embodiments. The molding material  612  may cover the top surface of the first semiconductor die  602  and may adjoin the sidewalls of the second semiconductor die  606 . The molding material  612  may protect the second semiconductor die  606 , the adhesion layer  608 , and the thermal spreader  610  from the environment, thereby preventing these components from damage due to, for example, the stress, the chemicals and/or the moisture. 
     The molding material  612  may include a nonconductive material, such as a moldable polymer, an epoxy, a resin, the like, or a combination thereof. As shown in  FIG. 6 , the top surface of the molding material  612  and the top surface of the thermal spreader  610  are substantially coplanar. The sidewalls of the molding material  612  may be substantially coplanar with the sidewalls of the first semiconductor die  602 . 
     As described above, the thermal spreader  610  may have a larger projection area on the first redistribution layer  302  than that of the second semiconductor die  606 . Thus, the molding material  612  may also cover the bottom surface of the thermal spreader  610  or the bottom surface of the adhesion layer  608 . According to some embodiments where the projection area of the thermal spreader  610  on the first redistribution layer  302  is also larger than or substantially equal to that of the first semiconductor die  602 , the sidewalls of the molding material  612  may be substantially coplanar with the sidewalls of the thermal spreader  610 . 
     As shown in  FIG. 6 , the adhesion layer  614  may be disposed between the molding material  612  and the second redistribution layer  322  and between the thermal spreader  610  and the second redistribution layer  322 . Alternatively, in the embodiments where the sidewalls of the molding material  612  are substantially coplanar with the sidewalls of the thermal spreader  610 , the adhesion layer  614  may be disposed between the thermal spreader  610  and the second redistribution layer  322 . 
     In the above embodiment, the heat from the first semiconductor die  602  and the second semiconductor die  606  can be transferred to the thermal spreader  610  and the second redistribution layer  322  besides the first redistribution layer  302 , thereby improving the efficiency of thermal dissipation. 
       FIG. 7  is a cross-sectional view of a semiconductor package structure  700 , in accordance with some embodiments of the disclosure. It should be noted that the semiconductor package structure  700  may include the same or similar components as that of the semiconductor package structure  300 , which is illustrated in  FIG. 3 , and for the sake of simplicity, those components will not be discussed in detail again. In the following embodiments, a passive component may be served as a thermal dissipation path. 
     As shown in  FIG. 7 , the semiconductor package structure  700  includes a substrate  702 , in accordance with some embodiments. The substrate  702  may have a wiring structure therein. In some embodiments, the wiring structure in the substrate  702  includes conductive layers, conductive vias, conductive pillars, the like, or a combination thereof. The wiring structure in the substrate  702  may be formed of metal, such as copper, aluminum, the like, or a combination thereof. 
     The wiring structure in the substrate  702  may be disposed in inter-metal dielectric (IMD) layers. In some embodiments, the IMD layers may be formed of organic materials, such as a polymer base material, non-organic materials, such as silicon nitride, silicon oxide, silicon oxynitride, the like, or a combination thereof. The substrate  702  may include an insulating core (not shown), such as a fiberglass reinforced resin core, to prevent the substrate  702  from warping. 
     It should be noted that the configuration of the substrate  702  shown in the figures is exemplary only and is not intended to limit the present disclosure. Any desired semiconductor element may be formed in and on the substrate  702 . However, in order to simplify the diagram, only the flat substrate  702  is illustrated. 
     As shown in  FIG. 7 , the semiconductor package structure  700  includes a first package structure  300   a  and a second package structure  300   b  stacked vertically over the substrate  702 , in accordance with some embodiments. Some components in the first package structure  300   a  and the second package structure  300   b  may be similar to some components in the first package structure  300   a  and the second package structure  300   b  as shown in  FIG. 3 , and will not be repeated. 
     As shown in  FIG. 7 , the semiconductor package structure  700  includes a thermal spreader  706  bonded onto the substrate  702  via a thermal interface material  704 , in accordance with some embodiments. The thermal spreader  706  may be thermally coupled to the semiconductor die  310 . Therefore, the heat from the semiconductor die  310  can be transferred to the substrate  702  through the thermal interface material  704  and the thermal spreader  706 . 
     In some embodiments, the thermal spreader  706  includes a passive component. For example, the thermal spreader  706  may include a capacitor, which may be electrically coupled to the semiconductor die  310  through the first redistribution layer  302 . As a result, the heat from the semiconductor die  310  can be dissipated without using an additional thermal spreader. 
     As shown in  FIG. 7 , the thermal spreader  706  may be disposed on the land side. That is, the thermal spreader  706  and the semiconductor die  310  may be disposed on opposite sides of the first redistribution layer  302 . The conductive terminals  304  may be disposed adjacent to the thermal spreader  706 . 
     As shown in  FIG. 7 , the thermal interface material  704  and the semiconductor die  310  may be disposed on opposite sides of the thermal spreader  706 . The thermal interface material  704  may include a metal, a polymer having a good thermal conductivity, or any suitable materials. In some embodiments, the thermal interface material  704  includes an adhesive-type material, a gel-type material, the like, or a combination thereof. For example, the thermal interface material  704  may include silicone, polyimide, epoxy, the like, or a combination thereof. 
     As shown in  FIG. 7 , the semiconductor package structure  700  includes a thermal spreader  710  bonded onto the substrate  326  via a thermal interface material  708 , in accordance with some embodiments. The thermal spreader  710  may be thermally coupled to the semiconductor die  310 . Therefore, the heat from the semiconductor die  310  can be transferred to the substrate  326  through the thermal interface material  708  and the thermal spreader  710 . 
     In some embodiments, the thermal spreader  710  includes a passive component. For example, the thermal spreader  710  may include a capacitor, which may be electrically coupled to the semiconductor die  310  or the semiconductor components  328  through the second redistribution layer  322 . As a result, the heat from the semiconductor die  310  or the semiconductor components  328  can be dissipated without using an additional thermal spreader. 
     As shown in  FIG. 7 , the thermal spreader  710  and the semiconductor die  310  may be disposed on opposite sides of the second redistribution layer  322 . The conductive terminals  324  may be disposed adjacent to the thermal spreader  710 . 
     As shown in  FIG. 7 , the thermal interface material  708  and the semiconductor die  310  may be disposed on opposite sides of the thermal spreader  710 . The material of the thermal interface material  708  may be similar to the material of the thermal interface material  704 , and will not be repeated. 
     It should be noted that the configurations of the thermal spreader  706  and the thermal spreader  710  shown in the figures are exemplary only and are not intended to limit the present disclosure. For example, depending on thermal dissipation requirements, the semiconductor package structure  700  may include only one of the thermal spreader  706  and the thermal spreader  710 , or may include more than two thermal spreaders. 
     Although the embodiment as shown in  FIG. 7  is described with a semiconductor package structure which includes redistribution layers (e.g., the first redistribution layer  302  and the second redistribution layer  322 ), the conception according to the present disclosure may be used in any suitable semiconductor package structures. For example, a semiconductor package structure including a substrate and an interposer, such as illustrated in  FIG. 1 , may have a thermal spreader which includes a passive component. In addition, the semiconductor package structure including a substrate and an interposer may also use a thermal interface material as an adhesion layer. 
     In summary, in some embodiments, the semiconductor package structure according to the present disclosure includes a thermal spreader bonded onto to the thermal source, such as a semiconductor die, through an adhesion layer. Therefore, the efficiency of thermal dissipation can be increased, and thus the performance of the semiconductor package structure can be improved. 
     According to some embodiments, the thermal spreader has a larger projection area than that of the semiconductor die to further improve the efficiency of thermal dissipation. Moreover, the thermal spreader may also be bonded onto a redistribution layer, so that the redistribution layer may be served as a thermal dissipation path for enhancing the thermal dissipation. 
     Furthermore, in some embodiments, the thermal spreader may include one or more passive components which may be electrically coupled to the semiconductor die. As a result, the heat from the semiconductor die can be dissipated without using additional thermal spreaders. In addition, the efficiency of thermal dissipation can be further improved by using a thermal interface material as an adhesion layer. 
     While the invention has been described by way of example and in terms of the preferred embodiments, it should be understood that the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.