Patent Publication Number: US-8987949-B1

Title: Linear regulator with multiple outputs and local feedback

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     The present disclosure claims priority to U.S. Provisional App. No. 61/384,007 filed Sep. 17, 2010, and is incorporated herein by reference in its entirety for all purposes. 
    
    
     BACKGROUND 
     The present disclosure relates to supplying power in a mixed signal integrated circuit (IC), and in particular to linear regulator for mixed signal ICs. 
     Unless otherwise indicated herein, the approaches described in this section are not prior art to the claims in this application and are not admitted to be prior art by inclusion in this section. 
     An integrated circuit (IC) that has both analog circuits and digital circuits on a single semiconductor die is commonly referred to as a mixed signal IC. In a mixed signal IC, the digital circuitry typically operates at a high frequency and the analog circuitry operates at DC or a relatively lower frequency as compared to the digital load. The fast-changing digital signals can send noise to the analog circuitry. One path for this noise can occur in the power supply section of the IC. The power supply section should exhibit immunity to noise transients that may arise when the analog and digital circuitry are driven. A common approach is to provide separate drive voltages for the analog circuitry and for the digital circuitry. The power supply section typically provides a current source that is proportional to bandgap voltage. Since the current source may be used for biasing or to produce a reference, the current source should also be as noise-free as possible. 
       FIG. 1  shows a typical configuration for a power supply section in a mixed signal IC. A first operational transconductance amplifier (OTA)  12  is configured with two source followers N 1 , N 2 . An output current of the OTA  12  sets up a voltage V G     —     BIAS  across output capacitor C 1  that serves to bias transistors N 1 , N 2 . Accordingly respective drive voltages V 2.5     —     ANA , V 2.5     —     DIG  serve as separate drive voltages for respective analog and digital circuitry, represented in the figure as “loads”. The resistor network R 1  and R 2  are typically configured to produce drive voltages V 2.5     —     ANA , V 2.5     —     DIG  on the order of 2.5 V. 
     During operation, the loading conditions in the analog circuitry or the digital circuitry may affect the drive voltages. For example, loading in the analog circuitry may suddenly increase, causing a sudden drop in the voltage level across the capacitor CL 1  and bringing V 2.5     —     ANA  below an acceptable value. A similar occurrence may arise for the digital circuitry. If the level for V 2.5     —     DIG  falls below a threshold value, the digital circuitry may go into a sleep state or turn off completely. A possible solution is to place a large capacitor Cx to buffer variations in V G     —     BIAS . However, such a capacitor may have a prohibitively large capacitance. 
     Digital circuitry present an additional concern. Logic gates in the digital circuitry may generate considerable switching noise during operation. These noise transients may be coupled back to the gate of transistor N 2  through an action known as “charge coupling.” Since the transistor N 2  operates as a voltage driver, the device must have relatively large physical dimensions in order to source sufficient current to operate properly. However, the overlap of the gate electrode with the source/drain electrodes in a large dimension device may result in significant capacitive coupling between the gate and the source (CGS). Accordingly, any noise transients in the digital logic sensed by the source terminal of transistor N 2  may be coupled back to the gate terminal of the transistor and thus influence the V G     —     BIAS  voltage level that is connected to the gate. Variations in the V G     —     BIAS  voltage would result in fluctuations in the drive voltage V 2.5     —     ANA , which could adversely affect operation of the analog circuitry. 
       FIG. 1  also includes a second OTA  14  that is configured with transistors P 1  and P 2  connected in a current mirror configuration. Output current I of the OTA  14  is proportional to the bandgap voltage V BG  and 1/(R 3 +R 4 ). The output current I drives the current mirror P 1 /P 2 , which is powered by a power supply voltage V DD , to produce a mirrored current I VBG . The current mirror P 1 /P 2  therefore serves as a current source that is proportional to the bandgap voltage. Separating the circuit that serves as the current source (namely, current mirror P 1 /P 2 ) from the circuit that generates the drive voltages allows for producing a current that exhibits low noise characteristics, although at the cost of space-consuming circuitry. A lower cost alternative is to configure the current mirror P 1 /P 2  with the OTA  12 , thus obviating the OTA  14 . However, the resulting current source may be more susceptible to noise due to switching transients in the digital circuit. 
     SUMMARY 
     In some embodiments, a method in a circuit includes receiving a reference voltage. In an embodiment, the reference voltage may be a bandgap voltage level. A source current that is proportional to the reference voltage may be generated. The source current may then be used to produce a first drive voltage for driving an analog load. A mirrored current may be produced from the source current, and used to control a first transistor produce a second drive voltage for driving a digital load. 
     In some embodiments, a feedback method may be provided to compensate for changes in the second drive voltage which drives the digital load. Accordingly, the method may further include sensing a voltage of the digital load and further controlling the first transistor in response to the sensed voltage in order to change the level of the second drive voltage. 
     In some embodiments, the method may further include producing the first drive voltage by mirroring the source current and using the mirrored current to control a transistor to produce the first drive voltage for driving the analog load. The method may further include a feedback method to compensate for changes in the first drive voltage, including sensing a voltage of the analog load and further controlling the transistor in response to the sensed voltage. 
     In some embodiments, a circuit includes a first circuit having a input for a reference voltage and an output voltage based on the reference voltage. A first source follower may produce a source current responsive to the output voltage. A second circuit may produce a first drive voltage from the source current for driving an analog load. A third circuit may produce a mirrored current from the source current. A second source follower may be controlled by the mirrored current to produce a second drive voltage for driving a digital load. 
     In some embodiments, a local feedback circuit may be provided to compensate for changes in the second drive voltage which drives the digital load. Accordingly, a circuit may be connected to further control the second source follower to change the second drive voltage depending on a difference between the output voltage of the first circuit and a voltage level of the digital load. 
     In some embodiments, the second circuit may include a circuit to produce a mirrored current from the source current. A source follower may be controlled by the mirrored current to produce the first drive voltage for driving the analog load. In some embodiments, a local feedback circuit may be provided to compensate for changes in the first drive voltage. Accordingly, a circuit may be connected to further control the source follower to change the first drive voltage depending on a difference between the output voltage of the first circuit and a voltage level of the analog load. 
     In some embodiments, a current source may be provided based on the source current produced by the first circuit. 
     The following detailed description and accompanying drawings provide a better understanding of the nature and advantages of the present disclosure. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a conventional design for a power supply section of a mixed signal IC. 
         FIG. 2  represents a high level block diagram of a portion of a mixed signal IC in accordance with embodiments of the present disclosure. 
         FIG. 2A  illustrates some examples where a mixed signal IC in accordance with disclosed embodiments may be incorporated. 
         FIG. 3  represents a circuit diagram of a power supply section in accordance with embodiments of the present disclosure. 
         FIG. 3A  shows an embodiment illustrating the feedback current from a local feedback loop can be connected directly to the source follower. 
         FIG. 4  represents an example of embodiments of a power supply section that omits local feedback for the analog drive voltage. 
         FIG. 4A  represents an example of embodiments of a power supply section that omits local feedback for the digital drive voltage. 
         FIG. 5  represents an example embodiment of a power supply section where the analog drive voltage is directly tapped from the regulated voltage and local feedback is omitted. 
     
    
    
     DETAILED DESCRIPTION 
     In the following description, for purposes of explanation, numerous examples and specific details are set forth in order to provide a thorough understanding of the present disclosure. It will be evident, however, to one skilled in the art that the present disclosure as defined by the claims may include some or all of the features in these examples alone or in combination with other features described below, and may further include modifications and equivalents of the features and concepts described herein. 
     Referring to  FIG. 2 , a linear regulator in accordance with embodiments of the present disclosure may be embodied in a mixed signal IC  100 . The mixed signal IC  100  may include digital circuitry  104  and analog circuitry  106 . A power supply section  102  in accordance with embodiments, may provide suitable drive voltages V 2.5     —     DIG  ( 114 ) and V 2.5     —     ANA  ( 116 ) to digital circuitry  104  and analog circuitry  106 , respectively. The power supply section  102  may be powered by a power supply voltage V DD , and produce drive voltages V 2.5     —     DIG  and V 2.5     —     ANA  referenced to a bandgap voltage V BG . The power supply section  102  may also implement a current source to supply a current I VBG  ( 112 ) that is proportional to the bandgap voltage V BG . Typical levels for the drive voltages V 2.5     —     DIG  and V 2.5     —     ANA  are on the order of 2.5 V, but may be other values. 
     Referring to  FIG. 2A , mixed signal ICs may be used in a wide variety of applications where analog functions and digital processes may be interrelated. For example, mixed signal ICs may be incorporated in consumer electronics devices such as cell phones, DVD players, digital cameras, in computer equipment such as printers, network devices, and so on. 
     In some embodiments, the power supply section  102  may be configured as illustrated in  FIG. 3 . A first power supply rail  202  may be connected to a power supply voltage V DD . A second power supply rail  204  may be connected to ground potential. A bandgap voltage reference V BG  may be connected to an input of an op amp  206  to provide a regulated voltage level V reg  that is referenced to the bandgap voltage. In an embodiment, the op amp  206  may be an operational transconductance amplifier (OTA) that outputs a current I out  in response to the bandgap voltage V BG  and a feedback voltage V fb  provided by resistor network R 1  and R 2 . 
     A bias capacitor CI may be charged by the current I out  to set up a bias voltage V g     —     bias  on bias line  208 . A transistor N 1  configured as a source follower may be controlled by the bias voltage V g     —     bias  to conduct a current I 1  (source current) that is sourced from the power supply rail  202  and flows through the resistor network R 1  and R 2 . The feedback loop comprising source follower N 1  and resistors R 1  and R 2  provide the regulated voltage V reg  across the resistors. The values of resistors R 1  and R 2  may be selected to produce a regulated voltage V reg  that is suitable for driving the analog circuitry and/or the digital circuitry. Note that the source current I 1  is proportional to the bandgap voltage V BG  for being a function of R 1  and R 2 . 
     A. Driving an Analog Load 
     Consider first, circuitry in the power supply section  102  relating to driving the analog circuitry (load)  106 . In some embodiments, transistors P 1  and P 2  may be configured as a current mirror P 1 /P 2 . The power supply rail  202  may sink the source current I 1  through the current mirror P 1 /P 2  (in particular through transistor P 1 ) and produce a mirrored current I 2 (=I 1 ) that flows through transistor P 2 . A portion of the mirrored current I 2  flows through diode-connected transistor N 3  and resistor R 3 . Another portion of the mirrored current I 2  also flows into bias capacitor C 2 , charging the capacitor to set up a bias voltage V g     —     ana . 
     A transistor N 4  may be used as a drive transistor that is configured as an open loop source follower to drive the analog circuitry  106 . The transistor N 4  is biased by the bias voltage V g     —     ana  to conduct a drive current I drv     —     ana  from the power supply rail  202 . The drive current I drv     —     ana  charges a drive capacitor CL 1  that is connected to a source terminal of transistor N 4  to set up a drive voltage V 2.5     —     ANA  at node  210   a  across the drive capacitor CL 1 . The drive voltage V 2.5     —     ANA  may be applied to an analog terminal  216  which is connected to the analog circuitry  106 . 
     The bias voltage V g     —     ana  and the drive voltage V 2.5     —     ANA  are functions of bias voltage V g     —     bias  and regulated voltage V reg . The regulated voltage V reg  may therefore serve as a reference for producing the drive voltage V 2.5     —     ANA . 
     The drive voltage V 2.5     —     ANA  may be controlled to a value substantially equal to the regulated voltage V reg . In some embodiments, the resistor R 3  may be set to the sum of R 1  and R 2 . Transistors N 3  and N 1  may be of the same size, and likewise, the transistors P 2  and P 1  may be of the same size. In such a configuration, the bias voltage V g     —     ana  across C 1  is substantially equal to the level of the bias voltage V g     —     bias  across C 2  by virtue of the selection of R 3 , N 3 , and P 2 . In addition, if the source follower transistors N 4  and N 1  are designed so that their current ratio is equal to their size ratio, then the generated drive voltage V 2.5     —     ANA  likewise is substantially equal to the regulated voltage V reg . 
     Depending on the particular requirements of the analog circuitry  106 , the drive voltage V 2.5     —     ANA  may be higher or lower than the regulated voltage V reg . In some embodiments, the R 3 , N 3 , and P 2  elements may be selected to produce a bias voltage V g     —     ana  that is greater than V g     —     bias  or less than V g     —     bias , thus producing a drive voltage V 2.5     —     ANA  that is greater than or less than the regulated voltage V reg  respectively. Nonetheless, V 2.5     —     ANA  remains a function of V reg . It can be appreciated that the drive voltage V 2.5     —     ANA  may also be controlled by varying the designs of the source follower transistors N 4  and N 1 . 
     The discussion will now turn to a description of the circuit  222 . During operation of the analog circuitry  106 , if the load condition in the analog circuitry is low, then the level of the drive voltage V 2.5     —     ANA  is higher than the regulated voltage V reg . For example, the drive voltage V 2.5     —     ANA  may satisfy the following relation: 
                     V     2.5   ⁢   _   ⁢           ⁢   ana       ≤       V     g   ⁢           ⁢   _   ⁢           ⁢   ana       +     V     gs   ⁢           ⁢   4                         V     g   ⁢           ⁢   _   ⁢           ⁢   bias       =       V   reg     +     V     gs   ⁢           ⁢   1           ,               
where V gs4  is the threshold voltage of transistor N 4  and V gs1  is the gate-source voltage of transistor N 1 , and V g     —     ana  is approximately equal to V g     —     bias  due to the selection of R 3 , N 3 , and P 2 .
 
     However, if the load the analog circuitry  106  is sufficiently high, the drive voltage V 2.5     —     ANA  may drop below V reg . Since the source follower N 4  is operating in an open loop (V g     —     ana  does not vary with V 2.5     —     ANA ), it cannot source additional current from the power supply rail  202  to compensate for the drop in the drive voltage V 2.5     —     ANA , and operation of the analog circuitry  106  may be adversely affected. 
     In some embodiments, the power supply section  102  may include a local feedback loop  222  to compensate for occurrences when the drive voltage V 2.5     —     ANA  drops below a threshold value. The local feedback loop  222  may include transistors P 4  and P 5  configured as a current mirror P 4 /P 5 . A sense transistor N 2  may be connected in series with current mirror P 4 /P 5 . The sense transistor N 2  may be biased by the bias voltage V g     —     bias  via bias line  208 . The source terminal of transistor N 2  may be connected to sense the level of the drive voltage V 2.5     —     ANA . Under low loading conditions by the analog circuitry  106 , the relation (V g     —     bias −V 2.5     —     ANA )&lt;V th  is true, where V th  is the threshold voltage of the transistor N 2 . Accordingly, the transistor N 2  is in cutoff mode and no current flows through the current mirror P 4 /P 5 . 
     However, if V 2.5     —     ANA  drops below V reg  by an amount equal to or greater than V th , then the difference (V g     —     bias −V 2.5     —     ANA ) will be greater than the voltage threshold and transistor N 2  becomes conductive. Consequently, a portion of the load current I load     —     ana  flowing into the analog circuitry  106  will be sensed through transistor P 4  and mirrored back via transistor P 5  as a feedback current I fb     —     ana  into resistor R 3 . The increased voltage across R 3  resulted from the mirrored current sourced through P 5  increases the bias voltage V g     —     ana . Refer for a moment to  FIG. 3A . In another embodiment, the mirrored current sourced through P 5  can be connected directly to the capacitor C 2 , which would also increase V g     —     ana . 
     Returning to  FIG. 3 , the increase in V g     —     ana , in turn, controls transistor N 4  to source additional current from the power supply rail  202  into capacitor C 2 , thus increasing the drive voltage V 2.5     —     ANA . When the relation (V g     —     bias −V 2.5     —     ANA )&lt;V th  is once again satisfied, then transistor N 2  turns off, the current mirror P 4 /P 5  turns off, and V g     —     ana  is restored. 
     Operation of the feedback loop  222  therefore can restore the drive voltage V 2.5     —     ANA  when the load of the analog circuitry  106  may otherwise cause the drive voltage to drop below an acceptable level. Moreover, operation of the transistor N 2  provides for automatic cutoff of the feedback loop  222  when the drive voltage V 2.5     —     ANA  is restored. 
     In embodiments, transients from the analog circuitry  106  are effectively isolated from the bias line  208  and thus the bias voltage V g     —     bias . Accordingly, a steady source current I 1  and consequently, a steady regulated voltage V reg  may be achieved. Consider first, the drive transistor N 4 . The size of N 4  is relatively large because it operates to drive the analog circuitry  106 . Accordingly, CGS coupling between its source terminal and gate is high. Any transient from the analog circuitry  106  that may propagate to the terminal  216  will propagate to the source terminal of N 4 , and due to CGS coupling those transients may be strongly coupled to the gate terminal of N 4 . However, since the gate terminal is isolated from bias line  208  via the current mirror P 1 /P 2 , the transients will not propagate to the bias line  208 . In addition, capacitor C 2  may provide a degree of buffering of any transient that may appear on the gate terminal of N 4 . 
     Consider next the transistor N 2 . The size of the transistor N 2  may be smaller than transistor N 4  as N 2  needs to act as a switch, while N 4  must be large enough to drive the analog circuitry  106 . Accordingly, the CGS effect in transistor N 2  is small and so any transient that may propagate from the analog circuitry  106  to the source terminal of N 2  will not be strongly coupled to the gate terminal of N 2 . Therefore, any transient that may be coupled to the gate terminal of N 2 , and hence onto bias line  208 , may be small. 
     B. Driving a Digital Load 
     Consider next, circuitry in the power supply section  102  shown in  FIG. 3  relating to driving the digital circuitry (load)  104 . In some embodiments, transistors P 1  and P 3  may be configured as a current mirror P 1 /P 3 . The power supply rail  202  may sink current through the current mirror P 1 /P 3  (in particular through transistor P 1 ) and produce a mirrored current I 3  (=I 1 ) that flows through transistor P 3 . The mirrored current I 3  flows through diode-connected transistor N 6  and resistor R 4 . The mirrored current I 3  also flows into bias capacitor C 3 , charging the capacitor to set up a bias voltage V g     —     dig . 
     A transistor N 7  may be used as a drive transistor that is configured as an open loop source follower to drive the digital circuitry  104 . The transistor N 7  is controlled (biased) by the bias voltage V g     —     dig  to conduct a drive current I drv     —     dig  from the power supply rail  202 . The drive current I drv     —     dig  charges a drive capacitor CL 2  that is connected to a source terminal of transistor N 7  to set up a drive voltage V 2.5     —     dig  at node  210   b  across the drive capacitor CL 2 . The drive voltage V 2.5     —     DIG  may be applied to a digital terminal  214  which is connected to the digital circuitry  104 . 
     The bias voltage V g     —     dig  and the drive voltage V 2.5     —     DIG  are functions of bias voltage V g     —     bias  and regulated voltage V reg . As with V 2.5     —     ANA , the regulated voltage V reg  may also serve as a reference for producing the drive voltage V 2.5     —     DIG . 
     The drive voltage V 2.5     —     DIG  may be controlled to a value substantially equal to the regulator voltage V reg . In some embodiments, the resistor R 4  may be set to the sum of R 1  and R 2 . Transistor N 6  may be of the same size as transistor N 1 , and likewise, the transistor P 3  may be of the same size as P 1 . In such a configuration, the bias voltage V g     —     dig  is substantially equal to the bias voltage V g     —     bias  by virtue of the selection of R 4 , N 6 , and P 3 . In addition, if the current ratio of the source follower transistor N 7  and the transistor N 1  is equal to their size ratio, then the generated drive voltage V 2.5     —     DIG  likewise is substantially equal to the regulated voltage V reg . 
     Depending on the particular requirements of the digital circuitry  104 , the drive voltage V 2.5     —     DIG  may be set higher or lower than the regulated voltage V reg . In some embodiments, the R 4 , N 6 , and P 3  elements may be selected to produce a bias voltage V g     —     dig  that is greater than V g     —     bias  or less than V g     —     bias  thus producing a drive voltage V 2.5     —     DIG  that is greater than or less than the regulated voltage V reg  respectively. Nonetheless, V 2.5     —     DIG  remains a function of V reg . It can be appreciated that the drive voltage V 2.5     —     DIG  may also be adjusted by varying the designs of the source follower transistor N 7  relative to N 1 . 
     The discussion will now turn to a description of the circuit  224 . During operation of the digital circuitry  104 , if the load condition in the digital circuitry is low, then the drive voltage V 2.5     —     DIG  is higher than the regulated voltage V reg . For example, the drive voltage V 2.5     —     DIG  may satisfy the following relation: 
                     V     2.5   ⁢   _   ⁢           ⁢   dig       ≤       V     g   ⁢           ⁢   _   ⁢           ⁢   dig       +     V     gs   ⁢           ⁢   7                         V     g   ⁢           ⁢   _   ⁢           ⁢   bias       =       V   reg     +     V     gs   ⁢           ⁢   1           ,               
where V gs7  is the threshold voltage of transistor N 7  and V gs1  is the gate-source voltage of transistor N 1 , and V g     —     dig  is approximately equal to V g     —     bias  due to the selection of R 4 , N 6 , and P 3 .
 
     However, if loading in the digital circuitry  104  is sufficiently high, the drive voltage V 2.5     —     DIG  may drop below V reg . Since the source follower N 7  is operating in an open loop (V g     —     dig  does not vary with V 2.5     —     DIG ), it cannot source additional current from the power supply rail  202  to compensate for the drop in the drive voltage V 2.5     —     DIG , and operation of the digital circuitry  104  may be adversely affected. 
     In some embodiments, the power supply section  102  may include a local feedback loop  224  to compensate for the occurrences when the drive voltage V 2.5     —     DIG  drops below a threshold value. The local feedback loop  224  may include transistors P 6  and P 7  configured as a current mirror P 6 /P 7 . A sense transistor N 5  may be connected in series with current mirror P 6 /P 7 . The sense transistor N 5  may be biased by the bias voltage V g     —     bias  on bias line  208 . The source terminal of transistor N 5  may be connected to sense the drive voltage V 2.5     —     DIG . Under low loading conditions by the digital circuitry  104 , the relation (V g     —     bias −V 2.5     —     DIG )&lt;V th  is true, where V th  is the threshold voltage of the transistor N 5 . Accordingly, the transistor N 5  is in cutoff mode and no current flows through the current mirror P 6 /P 7 . 
     However, if V 2.5     —     DIG  drops below V reg  by an amount equal to or greater than V th , then the difference (V g     —     bias −V 2.5     —     DIG ) will greater than the voltage threshold and transistor N 5  becomes conductive. Consequently, a portion of the load current I load     —     dig  flowing into the digital circuitry  104  may be sensed through transistor P 6  and mirrored back via transistor P 7  as a feedback current I fb     —     dig  into resistor R 4 . The increased voltage drop across R 4  resulted from the mirrored current sourced through P 6  increases the bias voltage V g     —     dig . Refer for a moment to  FIG. 3A . In another embodiment, the mirrored current sourced through P 7  can be connected directly to the capacitor C 3 , which would also increase V g     —     dig . 
     Returning to  FIG. 3 , the increase in V g     —     dig , in turn, controls transistor N 7  to source additional current from the power supply rail  202  into capacitor C 3 , thus increasing the drive voltage V 2.5     —     DIG . When the relation (V g     —     bias −V 2.5     —     DIG )&lt;V th  is once again satisfied, then transistor N 5  turns off, the current mirror P 6 /P 7  turns off, and V g     —     dig  is restored. 
     Operation of the feedback loop  224  therefore can restore the drive voltage V 2.5     —     DIG  when loading by the digital circuitry  104  may otherwise cause the drive voltage to drop below an acceptable level. Moreover, operation of the transistor N 5  provides for automatic cutoff of the feedback loop  224  when the drive voltage V 2.5     —     DIG  is restored. 
     In embodiments, transients from the digital circuitry  104  are effectively isolated from bias line  208  and thus the bias voltage V g     —     bias . Accordingly, a steady source current I 1  and consequently, a steady regulated voltage V reg  may be achieved. Consider first, the drive transistor N 7 . The size of N 7  is relatively large because it operates to drive the digital circuitry  104 . Accordingly, CGS coupling between its source terminal and gate is high. Any transient from the digital circuitry  104  that may propagate to the terminal  214  will propagate to the source terminal of N 7 , and due to CGS coupling those transients may be strongly coupled to the gate terminal of N 7 . However, since the gate terminal is isolated from the bias line  208  via the current mirror P 1 /P 3 , the transients will not propagate to the bias line  208 . In addition, capacitor C 3  may provide a degree of buffering of any transient that may appear on the gate terminal of N 7 . 
     Consider next the transistor N 5 . The size of the transistor N 5  may be small relative to the larger transistor N 7  as N 5  needs to act as a switch, while N 7  must be large enough to drive the digital circuitry  104 . Accordingly, the CGS effect in transistor N 5  is small and so any transient that may propagate from the digital circuitry  104  to the source terminal of N 5  will not be strongly coupled to the gate terminal of N 5 . Therefore, any transient that may be coupled to the gate terminal of N 5 , and hence onto bias line  208 , may be small. 
     C. Current Source 
     In some embodiments, the power supply section  102  may include a current source which can provide a stable current that is proportional to the bandgap voltage V BG  and which can be used for biasing or generating a reference current.  FIG. 3  shows a current mirror circuit defined by transistors P 1  and Px. The current mirror produces a mirrored current I x  that mirrors the source current I 1 . The mirrored current I x  is provided to the terminal  212 , which can then be output as a current I VBG  that is proportional to the bandgap voltage V BG . Since the biasing of transistor N 1  is isolated from any transient that may be created by digital and analog circuitry  104 ,  106 , a clean current source (namely, current mirror P 1 /Px) may be provided. 
     Referring to  FIG. 4 , in some embodiments the feedback loop  222  may be omitted from the power supply section  102 . Embodiments represented by  FIG. 4  may be suitable where heavy loading by the analog circuitry  106  is not likely to be encountered. In such a situation, the drive voltage V 2.5     —     ANA  can remain sufficiently constant such that compensation provided by the feedback loop  222  shown in  FIG. 3  may be omitted. Accordingly, the current mirror P 4 /P 5  and the transistor N 2  may be omitted as shown in  FIG. 4 . Referring to  FIG. 4A , in some other embodiments the feedback loop  224  may be omitted from the power supply section  102  in a similar manner. Accordingly, the current mirror P 6 /P 7  and the transistor N 5  may be omitted as shown in the figure. It can be appreciated that in some other embodiments, both feedback loops  222  and  224  may be omitted. 
     Referring to  FIG. 5 , the circuit elements that produce the drive voltage V 2.5     —     ANA  may be omitted from an embodiment of the power supply section  102  in addition to the feedback loop  222 . In some embodiments the drive voltage V 2.5     —     ANA  for the analog circuitry  104  may be produced directly from the regulated voltage V reg .  FIG. 5  shows an embodiment of the power supply section  102  in which the regulated voltage V reg  may be connected directly to the terminal  216  at node  210   c  to produce the drive voltage V 2.5     —     ANA  at the terminal. Accordingly, the circuitry elements transistor P 2  from the current mirror P 1 /P 2 , transistors N 3  and N 4 , resistor R 3 , and capacitor C 2  may be omitted as shown in the figure. 
     Embodiments represented by  FIG. 5  may be suitable where the analog circuitry  106  is not likely to produce transients that require isolation of the analog circuitry (the feedback loop  222  may be omitted). 
     As used in the description herein and throughout the claims that follow, “a”, “an”, and “the” includes plural references unless the context clearly dictates otherwise. Also, as used in the description herein and throughout the claims that follow, the meaning of “in” includes “in” and “on” unless the context clearly dictates otherwise. 
     The above description illustrates various embodiments of the present disclosure along with examples of how aspects of the present disclosure may be implemented. The above examples and embodiments should not be deemed to be the only embodiments, and are presented to illustrate the flexibility and advantages of the present disclosure as defined by the following claims. Based on the above disclosure and the following claims, other arrangements, embodiments, implementations and equivalents will be evident to those skilled in the art and may be employed without departing from the spirit and scope of the disclosure as defined by the claims.