Patent Publication Number: US-11386040-B2

Title: Circuit unit, circuit module and apparatus for data statistics

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application claims priority to Chinese Application No. 201711474618.1, filed Dec. 29, 2017, titled “CIRCUIT UNIT, CIRCUIT MODULE AND APPARATUS FOR DATA STATISTICS.” 
     TECHNICAL FIELD OF THE DISCLOSURE 
     The present disclosure generally relates to technical field of data statistics, and more particularly, to a circuit unit, a circuit module and an apparatus for data statistics. 
     BACKGROUND 
     In many applications, an input data stream needs to be counted to obtain some specific statistical information. For example, during processing of image data, it may be necessary to perform statistics on the data stream of the input image to obtain, for example, local luminance information, holographic histogram information, etc. 
     It is desired that the data statistics may be efficiently realized by using hardware with low consumption. 
     SUMMARY 
     In one aspect, disclosed is a circuit unit for data statistics. The circuit unit may comprise a first subcircuit and a second subcircuit. The first subcircuit may comprise a first register and may be configured to store data received via a first input terminal of the circuit unit in the first register in a case where a first control terminal of the circuit unit receives a first valid control signal. An output terminal of the first register may be coupled to a first output terminal of the circuit unit. The second subcircuit may comprise a second register, and may be configured to store data received via a second input terminal of the circuit unit in the second register in a case where a second control terminal of the circuit unit receives a second valid control signal. The second subcircuit may also be configured to increase the value of data stored in the second register by 1 in a case where a third control terminal of the circuit unit receives a third valid control signal. An output terminal of the second register may be coupled to a second output terminal of the circuit unit. 
     In another aspect, disclosed is also a circuit module for data statistics. The circuit module may comprise one or more abovementioned circuit units, wherein the one or more circuit units may include a first circuit unit, the first input terminal and the second input terminal of the first circuit unit receive input data and an initial counting value respectively via a first input terminal and a second input terminal of the circuit module. The circuit module may also comprise a control logic circuit. The control logic circuit may be configured to determine whether data in the first register of each circuit unit is the same as the input data and whether data in the second register of each circuit unit is equal to 0. The control logic circuit may also be configured to correspondingly provide a first control signal, a second control signal and a third control signal to each circuit unit according to the result of determination, and selectively output data in the first register and the second register of one of the one or more circuit units respectively via a first output terminal and a second output terminal of the circuit module. 
     In another aspect, disclosed is also an apparatus for data statistics. The apparatus may comprise one or more abovementioned circuit modules, wherein the one or more circuit modules may comprise a first circuit module, the first input terminal and the second input terminal of the first circuit module may respectively receive parsed data and a constant value 1. The apparatus may also comprise an update circuit. The update circuit may be coupled between a last circuit module of the one or more circuit modules and a memory, and is configured to update information in the memory based on a data item from the first output terminal of the last circuit module and a statistic value from the second output terminal of the last circuit module, wherein the first circuit module is used as the last circuit module in a case where the one or more circuit modules are one circuit module; a plurality of circuit modules may be connected in series in a case where the one or more circuit modules are a plurality of circuit modules, such that the first input terminal and the second input terminal of each circuit module except for the first circuit module are respectively coupled to the first output terminal and the second output terminal of the previous circuit module, meanwhile, the first output terminal and the second output terminal of each circuit module except for the second circuit module are respectively coupled to the first input terminal and the second input terminal of a subsequent circuit module, wherein the second circuit module is used as the last circuit module. 
     The circuit unit, the circuit module and/or the apparatus according to an embodiment of the present disclosure may use less resources and power consumption to complete data statistics. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  schematically shows a circuit unit for data statistics according to an embodiment of the present disclosure. 
         FIG. 2  schematically shows an example of a circuit structure of a circuit unit for data statistics according to an embodiment of the present disclosure. 
         FIG. 3  schematically shows a circuit module for data statistics according to an embodiment of the present disclosure. 
         FIG. 4  schematically shows an example of a circuit structure of a circuit module for data statistics according to an embodiment of the present disclosure. 
         FIG. 5  schematically shows another example of a circuit structure of a circuit module for data statistics according to an embodiment of the present disclosure. 
         FIG. 6  schematically shows still another example of a circuit structure of a circuit module for data statistics according to an embodiment of the present disclosure. 
         FIG. 7  schematically shows an example of an apparatus for data statistics according to an embodiment of the present disclosure. 
         FIG. 8  schematically shows another example of an apparatus for data statistics according to an embodiment of the present disclosure. 
         FIG. 9  schematically shows an example of an update circuit in an apparatus for data statistics according to an embodiment of the present disclosure. 
         FIG. 10  schematically shows an example of a working process of an apparatus for data statistics according to an embodiment of the present disclosure. 
         FIG. 11  schematically shows another example of a working process of an apparatus for data statistics according to an embodiment of the present disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     Details of a circuit unit, a circuit module, and an apparatus according to an embodiment of the present disclosure are described below in conjunction with the drawings. In various figures, arrows may represent directions in which data are transmitted, and the same reference numbers may be used to represent the same or similar elements or components, and the number  1  or  0  may have different meanings depending on the circumstances. 
     As shown in  FIG. 1 , a circuit unit for data statistics according to an embodiment of the present disclosure may have input terminals Val_i and Cnt_i, output terminals Val_o and Cnt_o, and control terminals Val_c, Cnt_c, and Inc_c, and may comprise a subcircuit UC 1  and a subcircuit UC 2 . 
     The subcircuit UC 1  may comprise a register REG 1 . The register REG 1  may store data input via the input terminal Val_i and may output the stored data via the output terminal Val_o. In one embodiment, the subcircuit UC 1  may be configured to store data input via the input terminal Val_i into the register REG 1  in a case where the control terminal Val_c receives a valid control signal. 
     The subcircuit UC 2  may comprise a register REG 2 . The register REG 2  may store data input via the input terminal Cnt_i and may output the stored data via the output terminal Cnt_o. In one embodiment, the subcircuit UC 2  may be configured to store data input via the input terminal Cnt_i into the register REG 2  in a case where the control terminal Cnt_c receives a valid control signal. The subcircuit UC 2  may also be configured to add 1 to the value of the data stored in the register REG 2  in a case where the control terminal Inc_c receives a valid control signal. 
     A valid control signal may also be called as an enable signal, i.e. a signal that enables an element or component or hardware module or apparatus to start to work or to convert to a valid state. For example, an element or component starts to work or converts to a valid state in a case where it receives a high-level signal, then the high-level signal may be used as an enable signal or a valid control signal for the element or component. In another example, as needed, the valid signal may also be other forms of signals such as a low-level signal, a signal at a certain potential or having a certain voltage value, a signal having a particular frequency, and the like. A binary 1 is also used to represent a valid control signal or enable signal, and correspondingly, a binary 0 may represent an invalid control signal or an inhibiting signal. 
     In an embodiment, as shown in  FIG. 2 , the subcircuit UC 1  may further comprise a selector SELL. For example, the selector SEL 1  may be an alternative type of multiplexer (or multi-way switch), and may have a control terminal, an input terminal corresponding to a valid control signal (represented by 1 in  FIG. 2 , and also referred to as input terminal  1  for short), and an input terminal corresponding to an invalid control signal (represented by 0 in  FIG. 2 , and also referred to as input terminal  0  for short). The control terminal, the input terminal  1 , the input terminal  0  and an output terminal of the selector SEL 1  may be respectively coupled to the control terminal Val_c, the input terminal Val_i, the output terminal of REG 1 , and the input terminal of REG 1 . 
     The selector SEL 1  may output data received via the input terminal  1  in a case where the control terminal receives a valid control signal, otherwise, output data received via the input terminal  0 . Thus, the subcircuit UC 1  may replace the old data in the register REG 1  with new data received via Val_i and output the new data at the output terminal Val_o in a case where the control terminal Val_c receives a valid control signal, otherwise, output the original old data at the output terminal Val_o. 
     In another embodiment, the selector SEL 1  may also be a switch (e.g., an electronic switch realized by a transistor, etc.) with an input terminal, a control terminal and an output terminal, and the switch may turn on the input terminal and the output terminal in a case where the corresponding control terminal receives a valid control signal, otherwise, turn off the connection between the input terminal and the output terminal. The input terminal, the output terminal and the control terminal of the switch may be respectively coupled to the input terminal Val_i, the input terminal of the register REG 1  and the control terminal Val_c, and the output terminal of the register REG 1  may not be necessary to be coupled to the switch. 
     In another embodiment, the selector SEL 1  may also be a combination of one or more logic gate elements which may realize the same function. In one embodiment, the selector SEL 1  may be a portion of the input control circuit of register REG 1 . 
     In an embodiment, as shown in  FIG. 2 , the subcircuit UC 2  may further comprise selectors SEL 2 , SEL 3  and an accumulator INC. 
     Similar to the selector SEL 1  of the subcircuit UC 1 , the selectors SEL 2  and SEL 3  may be alternative type of multiplexers (or multi-way switches) too. An input terminal  1 , an input terminal  0 , a control terminal and an output terminal of the selector SEL 2  may be respectively coupled to the input terminal Cnt_i, the output terminal of the register REG 2 , the control terminal Cnt_c and an input terminal  0  of the selector SEL 3 . An input terminal  1 , the input terminal  0 , a control terminal and an output terminal of the selector SEL 3  may be respectively coupled to an output terminal of the accumulator INC, the output terminal of the selector SEL 2 , the control terminal Inc_c and the input terminal of the register REG 2 , and an input terminal of the accumulator INC may be coupled to the output terminal of the register REG 2 . 
     Similar to the selector SEL 1  in the subcircuit UC 1 , the selectors SEL 2  and SEL 3  may output data received via the corresponding input terminal  1  in a case where the corresponding control terminal receives a valid control signal, otherwise, output data received via the corresponding input terminal  0 . The accumulator INC is used to add 1 to the data in the register REG 2 , and provides the data values obtained after adding 1 to the input terminal  1  of the selector SEL 3 . Thus, the working process of the subcircuit UC 2  may be shown in the following Table 1, (assuming that the old data previously stored in the register REG 2  is CNT 1 , and the new data received via input Cnt_i is CNT 2 ): 
     
       
         
           
               
               
               
               
               
             
               
                 TABLE 1 
               
               
                   
               
               
                 Signal at 
                 Signal at 
                   
                   
                 Data in 
               
               
                 control ter- 
                 control ter- 
                 Data output by 
                 Data output by 
                 register 
               
               
                 minal Cnt_c 
                 minal Inc_c 
                 selector SEL2 
                 selector SEL3 
                 REG2 
               
               
                   
               
             
            
               
                 Invalid 
                 Invalid 
                 CNT1 
                 CNT1 
                 CNT1 
               
               
                 Valid 
                 Invalid 
                 CNT2 
                 CNT2 
                 CNT2 
               
               
                 Invalid 
                 Valid 
                 CNT1 
                 CNT1 + 1 
                 CNT1 + 1 
               
               
                 Valid 
                 Valid 
                 CNT2 
                 CNT1 + 1 
                 CNT1 + 1 
               
               
                   
               
            
           
         
       
     
     That is to say, the subcircuit UC 2  may maintain the data in the register REG 2  unchanged in a case where the control signal received via the control terminal Cnt_c is invalid and the control signal received via the control terminal Inc_c is invalid, and output the old data CNT 1  maintained in the register REG 2  at the output terminal Cnt_o. The subcircuit UC 2  may replace the old data in the register REG 2  with new data received via the input terminal Cnt_i in a case where the control signal received via the control terminal Cnt_c is valid and the control signal received via the control terminal Inc_c is invalid, and output the new data CNT 2  in the register REG 2  at the output terminal Cnt_o. The subcircuit UC 2  may add 1 to the value of the data in the register REG 2  in a case where the control signal received via the control terminal Inc_c is valid, and output the new data CNT 1 +1 in the register REG 2  at the output terminal Cnt_o. 
     In another embodiment, the selector SEL 2  may also be a switch (e.g., an electronic switch realized by a transistor, etc.) with an input terminal, a control terminal and an output terminal, and the switch may turn on the input terminal and the output terminal in a case where the corresponding control terminal receives a valid control signal, otherwise, turn off the connection between the input terminal and the output terminal. In this embodiment, the selector SEL 2  may also be called as a switch SEL 2 , whose input terminal, output terminal and control terminal may be respectively coupled to the input terminal Cnt_i, the input terminal  0  of the selector SEL 3 , and the control terminal Cnt_c, and the output terminal of the register REG 2  may not be necessary to be coupled to the switch SEL 2 . 
     Further, the selector SEL 3  may be a switch (e.g., an electronic switch realized by a transistor, etc.) with an input terminal, a control terminal and an output terminal too, and the switch may turn on the input terminal and the output terminal in a case where the corresponding control terminal receives a valid control signal, otherwise, turn off the connection between the input terminal and the output terminal. In this embodiment, the selector SEL 3  may also be called as a switch SEL 3 , whose input terminal, output terminal and control terminal may be respectively coupled to the output terminal of the accumulator INC, the input terminal of the register REG 2 , and the control terminal Inc_c, and accordingly, the output terminal of the selector SEL 2  or the switch SEL 2  may be coupled to the register REG 2 . In this embodiment, it is possible to control the control signal received via the control terminal Cnt_c and the control signal received via the control terminal Inc_c not to be valid at the same time to avoid collision. 
     In another embodiment, the selectors SEL 2  and/or SEL 3  may also be a combination of one or more logic gate elements which may realize the same function. In one embodiment, the selector SEL 2  and/or the selector SEL 3  and/or the accumulator INC may be a portion of the input control circuit of register REG 2 . 
     In another embodiment, an additional selector or switch may be set between the register REG 1  and the output terminal Val_o and/or between the register REG 2  and the output terminal Cnt_o in the subcircuits UC 1  and/or UC 2 , to control whether the data in the register are output at the output terminal Val_o and/or the output terminal Cnt_o. 
       FIG. 3  shows an example of a circuit module for data statistics according to an embodiment of the disclosure. As shown in  FIG. 3 , a circuit module for data statistics according to the disclosed embodiment may have input terminals Cnt_in and Val_in and output terminals Val_out and Cnt_out, and may comprise a statistical circuit array ARR. The statistical circuit array ARR may comprise one or more circuit units as shown in  FIG. 1  or  FIG. 2 . 
     As shown in  FIG. 3 , the circuit module may further comprise a control logic circuit CON. The control logic circuit CON may be coupled to each circuit unit in the statistical circuit array ARR, and may receive data (D) from the output terminals Val_o and/or Cnt_o of each circuit unit in the statistical circuit array ARR, and may provide corresponding control signals (S) to the control terminals Val_c, Cnt_c and Inc_c of each circuit unit in the statistical circuit array ARR. 
     The control logic circuit may be configured to determine whether the data in the register REG 1  of each circuit unit in the statistical circuit array ARR is the same as the data received via the input terminal Val_in and whether the data in the register REG 2  of each circuit unit is equal to 0, and provide corresponding control signals to the control terminals Val_c, Cnt_c and/or Inc_c of each circuit unit in the statistical circuit array ARR according to the result of the determination. In addition, the control logic circuit may be further configured to selectively output the data in the register REG 1  and the register REG 2  of one circuit unit in the statistical circuit arrays ARR via the output terminal Val_out and the output terminal Cnt_out, respectively. 
       FIG. 4  to  FIG. 6  show different examples of a circuit module according to an embodiment of the present disclosure. 
     In the example of  FIG. 4 , the statistical circuit array ARR may comprise a plurality of circuit units U 1  to Un connected in series, wherein the input terminals Val_i and Cnt_i of the circuit unit U 1  are respectively coupled to the input terminals Val_in and Cnt_in of the circuit module, and the input terminals Val_i and Cnt_i of each circuit unit except for the circuit unit U 1  are respectively coupled to the output terminals Val_o and Cnt_o of the corresponding previous circuit unit, meanwhile the output terminals Val_o and Cnt_o of each circuit unit except for the circuit unit Un are respectively coupled to the input terminals Val_i and Cnt_i of the corresponding subsequent circuit unit. For example, the input terminals Val_i and Cnt_i of the circuit unit U 2  are respectively coupled to the output terminals Val_o and Cnt_o of the circuit unit U 1 . 
     As shown in  FIG. 4 , in an embodiment, the control logic circuit CON may comprise a comparator Xk and a comparator XNk respectively corresponding to each circuit unit Uk, wherein 1≤k≤n. For example, corresponding to the circuit unit U 1 , the control logic circuit CON may comprise a comparator X 1  and a comparator XN 1 ; corresponding to the circuit unit U 2 , the control logic circuit CON may comprise a comparator X 2  and a comparator XN 2 ; corresponding to the circuit unit Un, the control logic circuit CON may comprise a comparator Xn and a comparator XNn. 
     In an embodiment, two input terminals of the comparator XNk may be respectively coupled to the output terminal Val_o of the circuit unit Uk and the input terminal Val_in of the circuit module, so as to compare the data in the register REG 1  of the circuit unit Uk and the data received by the circuit module via the input terminal Val_in. In a case where the two data being compared are identical, the comparator XNk may output a message or signal indicating that the two data being compared are the same, otherwise, the comparator XNk may output a message or signal indicating that the two data being compared are different. For example, the comparator XNk may output a signal matchk, which may be a valid signal (e.g., a high level or any other forms that may represent a binary 1) in a case where the two data being compared are identical, and which may be an invalid signal (e.g., a low level or any other forms that may represent a binary 0) in a case where the two data being compared are different. 
     As shown in  FIG. 4 , the two input terminals of the comparator XN 1  may be respectively coupled to the output terminal Val_o of the circuit unit U 1  and the input terminal Val_in of the circuit module, and the output signal or message match 1  may be 1 in a case where the data in the register REG 1  of the circuit unit U 1  is the same as the data received via the input terminal Val_in, otherwise  0 . 
     Although an XNOR gate element is used in  FIG. 4  to represent the comparator XNk, this does not mean that the comparator XNk must be realized by only one XNOR gate element. In various embodiments, the comparator XNk may comprise one or more logic gate elements, or may comprise an integrated value comparator such as CC14585 or 74LS85, as needed. 
     For example, the comparator XNk may comprise a plurality of XNOR gate elements and an AND gate element, wherein each XNOR gate element may have two input terminals and respectively receive one bit in binary representations of the data in the register REG 1  in the circuit unit Uk and a corresponding one bit in binary representations of the data received via the input Val_in. Then, the output terminal of each XNOR gate element may be respectively coupled to an input terminal of the AND gate element. 
     One input terminal of the comparator Xk may be coupled to the output terminal Cnt_o of the circuit unit Uk, and the other input terminal may receive a constant value 0, so as to compare the data in the register REG 2  of the circuit unit Uk and 0. In a case where the two data being compared are the same, the comparator Xk may output a message or signal indicating that the two data being compared are the same, otherwise, the comparator Xk may output a message or signal indicating that the two data being compared are different. For example, the comparator Xk may output a signal validk which may be a valid signal (e.g., a high level or any other forms that may represent a binary 1) in a case where the two data being compared are different, and which may be an invalid signal (e.g., a low level or any other forms that may represent a binary 0) in a case where the two data being compared are the same. 
     As shown in  FIG. 4 , one input terminal of the comparator X 1  may be coupled to the output terminal Cnt_o of the circuit unit U 1 , and the other input terminal receives a constant value 0, and the output signal or message valid 1  may represent a binary 1 in a case where the data in the register REG 2  of the circuit unit U 1  is not equal to 0, otherwise representing a binary 0. 
     Although an XOR gate element is used in  FIG. 4  to represent the comparator Xk, this does not mean that the comparator Xk must be realized by only one XOR gate element. In various embodiments, the comparator Xk may comprise one or more logic gate elements, or may include an integrated value comparator such as CC14585 or 74LS85, as needed. 
     For example, the comparator Xk may also be set with an input terminal which is coupled to the output terminal Cnt_o of the circuit unit Uk. Further, the comparator Xk may comprise one or more OR gate elements, to perform a logical OR operation on the binary number of all bits of the data in the register REG 2  of the circuit unit Uk, and output the result of the logical OR operation as a signal or message validk. For example, in a case where the register REG 2  of the circuit unit Uk is a 32-bit register and the stored data is 3, then, 2 binary 1 are included in the 32 binary bits of the binary representation of the value 3, and the result of performing a logical OR operation on all 32-bit binary numbers is 1, accordingly, the signal or message validk output by the comparator Xk may be 1. The number of OR gate elements may depend on the number of bits of register REG 2  of circuit unit Uk, the used number of input terminal of the OR gate elements and the arrangement manner of the OR gate elements. 
     As shown in  FIG. 4 , the output terminals of each pair of comparators Xk and XNk may also be coupled to two input terminals of detector Ak, respectively, and the output terminal of detector Ak is coupled to the control terminal Inc_c of the circuit unit Uk. For example, the output terminals of the comparators X 1  and XN 1  may also be coupled to the two input terminals of the detector A 1 , respectively, and the output terminal of the detector A 1  is coupled to the control terminal Inc_c of the circuit unit U 1 . In the example of  FIG. 4 , the detector Ak contains an AND gate element. 
     In another embodiment, the detector Ak may comprise an integrated value comparator such as CC14585 or 74LS85. In this embodiment, the detector Ak may provide a valid control signal to the control terminal Inc_c of the circuit unit Uk in a case where the received two data are the same or both are greater than 0, thereby realizing a function equivalent to the AND gate element. 
     In another embodiment, the detector Ak may comprise, for example, an alternative type of multiplexer (or multi-way switch). For example, the output terminal of the comparator Xk may be coupled to the control terminal of Ak, the output terminal of the comparator XNk may be coupled to the input terminal of Ak corresponding to the valid control signal, a 0 may be provided to an input terminal of Ak corresponding to an invalid control signal, and an output terminal of Ak may be coupled to the control terminal Inc_c of the circuit unit Uk, thereby realizing a function equivalent to the AND gate element. 
     Through the comparator Xk, the comparator XNk and the detector Ak, the control logic circuit CON may provide a valid control signal to the control terminal Inc_c of the circuit unit Uk, in a case where the data in the register REG 1  of the circuit unit Uk is the same as the data received via the input terminal Val_in of the circuit module and the data in the register REG 2  of the circuit unit Uk is not equal to 0. 
     For example, in a case where the circuit module receives data V 1  via the input terminal Val_in, and the data in the registers REG 1  and REG 2  of the circuit unit U 2  are V 1  and 3, respectively, the valid 2  output by the comparator X 2  is 1 (i.e. the data in REG 2  of U 2  is not equal to 0), and the match 2  output by the comparator XN 2  is 1 (i.e. the data in RE 1  of U 2  is the same as V 1 ). The detector A 2  outputs a valid control signal (e.g., 1) in a case where both inputs it received are 1. Accordingly, data  3  in the register REG 2  of the circuit unit U 2  becomes 4 after being processed by the accumulator INC. 
     In another embodiment, the detector Ak may further comprise a signal generator (not shown), so as to generate a valid control signal in a case where the data in the register REG 1  of the circuit unit Uk is the same as the data received via the input terminal Val_in of the circuit module and the data in the register REG 2  of the circuit unit Uk is not equal to 0, for example, a signal meeting certain voltage value requirements or frequency requirements. In another embodiment, such a signal generator may be set between the detector Ak and the control terminal Inc_c of the circuit unit Uk independently of the detector Ak. 
     A portion of the control logic circuit CON for generating the control signal for the control terminal Inc_c of each circuit unit Uk may not be limited to the manner in the example in  FIG. 4 . In another embodiment, for example, the control logic circuit CON may comprise a processor and a counter. The processor may be configured to alternately detect the data in the registers REG 1  and REG 2  of each circuit unit Uk, and to provide a valid control signal to the control terminal Inc_c of the circuit unit Uk in a case where the data in the register REG 1  of the circuit unit Uk is the same as the data received via the input terminal Val_in of the circuit module and the data in the register REG 2  of the circuit unit Uk is not equal to 0, so as to add 1 to the value of the data in the register REG 2  of the circuit unit Uk. The counter may be a loop counter from 1 to n, and may comprise a register, for identifying the circuit unit Uk which is currently detected by the processor. 
     As shown in  FIG. 4 , the control logic circuit CON may further comprise a detector NOR. An input terminal of the detector NOR may be coupled to each comparator XNk, respectively, and an output terminal of the detector NOR may be coupled to the control terminals Val_c and Cnt_c of each circuit unit Uk. The detector NOR may be configured to generate a valid control signal in a case where an output signal or message matchk from each comparator XNk is 0 (i.e. all data in the register REG 1  of each circuit unit Uk is different from the data received via the input terminal Val_in of the circuit module), and to provide the generated valid control signal to the control terminals Val_c and Cnt_c of each circuit unit Uk. 
     In the example of  FIG. 4 , the detector NOR may comprise a NOR gate element, wherein each input terminal of the NOR gate element is coupled to an output terminal of the comparator XNk, respectively, and an output terminal of the NOR gate element is coupled to the control terminals Val_c and Cnt_c of each circuit unit Uk. In another embodiment, the detector NOR may also comprise a signal generator (not shown), so as to generate a valid control signal based on the output of the NOR gate element, for example, a signal that meets certain voltage value requirements or frequency requirements. In another embodiment, such a signal generator may be set among the detector NOR and the control terminals Val_c and Cnt_c of the circuit unit Uk independently of the detector NOR. 
     In a case where the control terminals Val_c and Cnt_c of each circuit unit Uk receive a valid control signal from the control logic circuit CON, the circuit unit U 1  replaces the data in the register REG 1  and the data in the REG 2  of the circuit unit U 1  with data from the input terminals Val_in and Cnt_in of the circuit module, respectively, and each circuit unit Uk transfers the data in the corresponding registers REG 1  and REG 2  to a next circuit unit Uk+1. For example, the circuit unit U 1  provides the old data in its registers REG 1  and REG 2  to U 2 , and replaces the old data with new data; the circuit unit U 2  provides the data in its registers REG 1  and REG 2  to U 3  and updates the data with the data from circuit unit U 1 ; and so on. 
     In the example of  FIG. 4 , the control logic circuit CON may further comprise a detector AND 1  and a control switch SW, to control whether to output the data in the registers REG 1  and REG 2  of the circuit unit Un. 
     As shown in  FIG. 4 , two input terminals of the detector AND 1  may be coupled to the output terminal of the detector NOR and the output terminal of the comparator Xn, respectively, and may output a valid control signal update_valid in a case where the data input by both input terminals are 1 (i.e. the data in the register REG 1  of each circuit unit Uk is different from the data received via the input terminal Val_in, and the data in the register REG 2  of the circuit unit Un is not equal to 0). In an embodiment, detector AND 1  may comprise an AND gate element. 
     The switch SW may have a control terminal, and the control terminal of the switch SW may be coupled to the output terminal of the detector AND 1 . Further, two input terminals of the switch SW are respectively coupled to the output terminals Val_o and Cnt_o of the circuit unit Un, and two output terminals of the switch SW are respectively coupled to the output terminals Val_out and Cnt_out of the circuit module. The switch SW may turn on the output terminal Val_o of the circuit unit Un and the output terminal Val_out of the circuit module, and turn on the output terminal Cnt_o of the circuit unit Un and the output terminal Cnt_out of the circuit module, in a case where its control terminal receives the valid control signal update_valid, otherwise, turn off the connection between the output terminal Val_o of the circuit unit Un and the output terminal Val_out of the circuit module and the connection between the output terminal Cnt_o of the circuit unit Un and the output terminal Cnt_out of the circuit module. 
     Thus, the control logic circuit CON may output the data in the registers REG 1  and REG 2  of the circuit unit Un in a case where the data in the register REG 1  of each circuit unit Uk is different from the data received via the input terminal Val_in and the data in the register REG 2  of the circuit unit Un is not equal to 0. 
     In one embodiment, the switch SW may include a plurality of transistors, wherein the gate, the source and the drain of a transistor are respectively coupled to the output terminal of the detector AND 1 , the output terminal Val_o of the circuit unit Un and the output terminal Val_out of the circuit module; the gate, the source and the drain of another transistor are respectively coupled to the output terminal of the detector AND 1 , the output terminal Cnt_o of the circuit unit Un, and the output terminal Cnt_out of the circuit module, and these transistors may be turned on in a case where their gates receive the valid control signal update_valid. In another embodiment, the switch SW may further include one or more multiplexers or multi-way switches. 
     In another embodiment, the control logic circuit CON may also provide the control signal update_valid output by the detector AND 1  to the outside of the control logic circuit CON. 
       FIG. 5  shows another example of a circuit module according to an embodiment of the present disclosure. Differences between the example of  FIG. 5  and the example of  FIG. 4  are described below, while the same between the two examples would not be described again. 
     Unlike the example in  FIG. 4 , in the example shown in  FIG. 5 , the input terminals Val_i and Cnt_i of each circuit unit Uk in the statistical circuit array ARR are respectively coupled to the input terminals Val_in and Cnt_i of the circuit module, instead of being coupled to the output terminals Val_o and Cnt_o of the previous circuit unit, as shown in  FIG. 4 . 
     Further, in the example shown in  FIG. 5 , a plurality of input terminals of the detector AND 1  are respectively coupled to the output terminal of the detector NOR and the output terminal of each comparator Xk (instead of being coupled only to the output terminal of the detector NOR and the output terminal of the comparator Xn as in the example of  FIG. 4 ). This means that in the example shown in  FIG. 5 , in a case where all data in the register REG 1  of each circuit unit Uk is different from the data received via the input terminal Val_in, the detector AND 1 outputs the valid control signal update_valid only in a case where all data in the register REG 2  of each circuit unit Uk is not equal to 0 (instead of only considering the data in register REG 2  of Un as in the example of  FIG. 4 ). 
     As described above, in the example of  FIG. 4 , the data in the registers REG 1  and REG 2  of the circuit unit Un are fixedly selected as the output object, and the switch SW may be relatively simply used to control the output. However, unlike the example of  FIG. 4 , in the example of  FIG. 5 , the selector need to select one circuit unit Uj (1≤j≤n) from all circuit units U 1  to UN and to output the data in the registers REG 1  and REG 2  of circuit unit Uj in a case where all data in the register REG 1  of each circuit unit Uk is different from the data received via the input terminal VAL_in and all data in the register REG 2  of each circuit unit Uk is not equal to 0. 
     Accordingly, the control logic circuit CON may include a selector US 1 , a multiplexer VSEL, and a multiplexer CSEL. A control terminal of the selector US 1  may be coupled to the output terminal of the detector AND 1 , and select j from 1 to n in a case where its control terminal receives the valid control signal update_valid from the detector AND 1 . A control terminal of the multiplexer VSEL may be coupled to the output terminal of the selector US 1 , a plurality of input terminals of the multiplexer VSEL may be coupled to the output terminal Val_o of each circuit unit Uk, respectively, and the output terminal of the multiplexer VSEL may be coupled to the output terminal Val_out of the circuit module, such that the multiplexer VSEL may output data in the register REG 1  of the circuit unit Uj in response to receiving the j value from the selector US 1  at its control terminal. A control terminal of the multiplexer CSEL may be coupled to the output terminal of the selector US 1 , a plurality of input terminals of the multiplexer CSEL may be coupled to the output terminal Cnt_o of each circuit unit Uk, respectively, and the output terminal of the multiplexer CSEL may be coupled to the output terminal Cnt_out of the circuit module, such that the multiplexer CSEL may output data in the register REG 2  of the circuit unit Uj in response to receiving the j value from the selector US 1  at its control terminal. 
     In one embodiment, the selector US 1  may be coupled to the output terminal Cnt_o of each circuit unit Uk and may include one or more comparators (for example, an integrated value comparator such as CC14585 or 74LS85). In this embodiment, the comparator may compare the data in the register REG 2  of each circuit unit Uk and determine j from 1 to n, such that the value of the data in the register REG 2  of the circuit unit Uj is the largest or smallest among the values of the data in the registers REG 2  of all the circuit units U 1  to Un. 
     In another embodiment, the selector US 1  may include a random number generator (for example, a true random number generator that generates random numbers based on physical processes) to generate a random number j between 1 and n. 
     In another embodiment, the selector US 1  may fixedly select a value j (e.g., n) between 1 and n and fixedly transfer j to the multiplexers VSEL and CSEL, such that the multiplexers VSEL and CSEL fixedly select the data in the registers REG 1  and REG 2  of Uj to output. Thus, the selector US 1 , the multiplexer VSEL, and the multiplexer CSEL may be simplified to, for example, a form similar to the switch SW in the example of  FIG. 4 , and the two input terminals of the switch SW may be respectively coupled to the output terminals Val_o and Cnt_o of Uj. 
     For example, in a case where USn is fixedly selected, the selector US 1 , the multiplexers VSEL and CSEL in  FIG. 5  may simply be realized in the form of the switch SW in  FIG. 4 . Therefore, the control logic circuit CON in the example of  FIG. 4  may be considered as a simplified form of the control logic circuit CON in the example of  FIG. 4 , and in one aspect, the switch SW in the control logic circuit CON in the example of  FIG. 4  may also use, for example, a form of a combination of the selector US 1 , and the multiplexers VSEL and CSEL in the example of  FIG. 5 . 
     Further, in the example of  FIG. 5 , the control logic circuit CON may further comprise a signal controller SCON. The signal controller SCON receives the value j output from the selector US 1 , provides a valid control signal to the control terminals Val_c and Cnt_c of the circuit unit Uj, and provides invalid control signals to the control terminals Val_c and Cnt_c of other circuit units, such that the circuit unit Uj may update the data in the corresponding registers REG 1  and REG 2  with data from the input terminals Cnt_in and Val_in of the circuit module, meanwhile, maintain the data in the registers of other circuit units unchanged. 
     In an embodiment, the signal controller SCON may comprise, for example, an alternative type of n multiplexers (not shown, an input terminal corresponding to a valid control signal may be coupled to a valid signal, and the other input terminal may be coupled to an invalid signal), wherein the output terminal of each multiplexer may be coupled to the control terminals Val_c and Cnt_c of the corresponding circuit unit Uk, and each multiplexer may output a valid control signal in a case where the information (e.g., number j) indicated by the control signal received via the corresponding control terminal is the same as the serial number of the multiplexer (such a determination may be realized, for example, by means of a logic circuit), otherwise output an invalid control signal. 
     Further, in the example of  FIG. 5 , the control logic circuit CON may further comprise a detector NA, a detector AND 2 , and a selector US 2 . 
     The detector NA has a plurality of input terminals respectively coupled to the output terminal of each comparator Xk, and outputs a valid signal in a case where not all of validk are 1 (i.e. there is a REG 2  of a circuit unit whose data is equal to 0). In one embodiment, the detector NA may comprise a NAND gate element. 
     The detector AND 2  has two input terminals respectively coupled to the output terminal of the detector NA and the output terminal of the detector NOR, and output a valid signal in a case where both received input data are 1 (i.e. the data in the register REG 1  of each circuit unit Uk is different from the data received via the input terminal Val_in of the circuit module, and there is a register REG 2  of a circuit unit whose data is equal to 0). In one embodiment, detector AND 2  may include a NAND gate element. 
     The realization manner of the selector US 2  may be similar to the selector US 1 . The difference is that the selector US 2  needs to select one circuit unit Uj from the circuit unit with data equal to 0 in the corresponding register REG 2  (instead of all circuit units). Thus, the logic circuit in the selector US 2  or the multiplexer may also be coupled to the output terminal of each comparator Xk or the output terminal of each circuit unit Uk. Then, the selector US 2  may select (e.g., in an embodiment, randomly selected by means of a random number generator) one circuit unit Uj from all the circuit units that meets the above conditions, the data in the register REG 2  of the circuit unit Uj is equal to 0 and the data in the register REG 1  is also different from the data received via the input terminal Val_in of the circuit module. Then, the selector US 2  may transmit a message (e.g., number j) related to the selected circuit unit Uj to the signal controller SCON. 
     In another embodiment, the selector US 2  may also comprise a counter. For example, the initial value of the counter may be set to 0. When the circuit module receives data via the input terminal Val_in, in a case where all match 1  to matchn are 0 and at least one of valid 1  to validn is 0, i.e. in a case where the detector AND 2  outputs  1 , the counting value of the counter may add 1, and the current counting value is transferred to the signal controller SCON. In this embodiment, the circuit units U 1  to Un would be used successively to store valid data. In another embodiment, the counter may also count from large to small, and in this embodiment, the circuit units Un to U 1  would be sequentially used to store valid data. 
     When receiving the output value j from the selector US 2 , the signal controller SCON provides a valid control signal to the control terminals Val_c and Cnt_c of the circuit unit Uj, and provides invalid control signals to the control terminals Val_c and Cnt_c of other circuit units, such that the circuit unit Uj may update the data in the corresponding registers REG 1  and REG 2  with data from the input terminals Cnt_in and Val_in of the circuit module, at the same time, maintain the data in the registers of other circuit units unchanged. 
     Since the detectors NA and AND 1  would not output  1  simultaneously, the selectors US 2  and US 1  would not function simultaneously. That is to say, the selectors US 1  and US 2  respectively transmit signals or messages about j to the control terminal of the signal controller SCON under different circumstances without causing a collision. Therefore, although the selectors US 1  and US 2  are respectively coupled to different terminals of the signal controller SCON as shown in  FIG. 5 , the two terminals of the signal controller SCON would not receive a valid control signal simultaneously. Therefore, in an embodiment, the signal controller SCON may be set with a control terminal, and the output terminal of the selectors US 1  and US 2  may be coupled to this control terminal. 
       FIG. 6  shows another example of a circuit module according to an embodiment of the present disclosure. In this example, the statistical circuit array ARR comprises only one circuit unit U, and the control logic circuit CON may comprise only a pair of comparators Xu and XNu and a detector Au corresponding to the circuit unit U, wherein similar to the example in  FIG. 4  or  FIG. 5 , two input terminals of the comparator XNu may respectively receive data from the output terminal Val_o of the circuit unit U and the input terminal Val_in of the circuit module, and the output signal matchu of the comparator XNu may be a valid signal (e.g., 1) in a case where the two input data are the same, and an invalid signal (e.g., 0) in a case where the two input data are not the same; the input terminal of the comparator Xu may be coupled to the output terminal Cnt_o of the circuit unit U, and its output signal validu may be valid (e.g., 1) in a case where the data in the register REG 2  of the circuit unit U is not equal to 0, and is invalid (e.g., 0) in a case where the data in the register REG 2  of the circuit unit U is equal to 0; two input terminals of the detector Au may be coupled to the output terminals of the comparators Xu and XNu, respectively, and its output terminal may be coupled to the control terminal Inc_c of the circuit unit U, and may output a valid control signal in a case where both received input signals are valid (e.g., both are 1), otherwise, output an invalid control signal. 
     Since the statistical circuit array ARR in the example of  FIG. 6  comprises only one circuit unit U, the detector NOR in the example of  FIG. 4  or  FIG. 5  is replaced with a NOT gate element or an inverter N, or may comprise a NOT gate element or an inverter N, and the circuit portion of the control logic circuit CON for controlling whether to output the data in the registers REG 1  and REG 2  of the circuit unit U may use the simple form in the example of  FIG. 4 . 
       FIG. 6  is actually an example of an implement of the example in  FIG. 4  or  FIG. 5  in a simple case. 
     Although the respective comparators and detectors of the control logic circuit CON in the examples of  FIG. 4  to  FIG. 6  are shown as a single logic gate element (e.g., in  FIG. 4  to  FIG. 6 , the logic gate symbols recommended by IEEE are used for representing), however, each element is only used to represent basic functions realized by the corresponding comparator or detector or basic elements included in the corresponding comparator or detector in an embodiment, and it does not mean that these comparators and/or detectors must comprise only one logic gate element or must be realized by such logic gate elements. Further, the various multiplexers (or multi-way switches) and switches SW (a simple form of multiplexer) in the examples of  FIG. 4  to  FIG. 6  may be realized by one or more logic gate elements, and may also be realized by one or more electronic switches with a control terminal, such as a transistor, and may also be realized by one or more multiplexers such as 74LS153, 74LS151, and the like. Further, the selectors US 1  and/or US 2  may be voting circuits realized by a multiplexer and/or one or more logic gate elements, and may comprise a random number generator. 
     For example, in the examples of  FIG. 4  to  FIG. 6 , the data in the register REG 2  of each circuit unit in the statistical circuit array ARR may no longer be equal to 0 after the circuit module receives n (wherein n=1, in the example of  FIG. 6 ) parsed data being different from each other. That is to say, the signal validk corresponding to any one of the circuit units Uk (1≤k≤n) may be 0 only during an initial stage, and during this initial stage, the circuit module receives and makes a statistic operation on less than n different parsed data (i.e. the data in REG 2  of at least one circuit unit is 0) and would not output any data via the output terminals Val_out and Cnt_out; however, at any time points after this initial stage, all signals valid 1  to validn may not be 0. 
     Therefore, in an embodiment, the control logic circuit CON may comprise a counter, and this counter may count from 1 to n, and the corresponding counting value may add 1 only in a case where all the signals match 1  to matchn are not 0. The control logic circuit CON may not output any data via the output terminals Val_out and Cnt_out in a case where the value of the counter is less than or equal to n, and output data in the registers REG 1  and REG 2  of the circuit unit Un via the output terminals Val_out and Cnt_out in a case where the value of the counter is greater than n and all of the signals match 1  to matchn are not 0. 
     In this embodiment, it may not be necessary to set the comparators X 1  to Xn or Xu in  FIG. 4  to  FIG. 6 , and the detectors A 1  to An or Au may detect the current value of the counter and the signal values of match 1  to matchn or matchu. The detector AND 1  may only receive the output value of the detector NOR and the current value of the counter, and may output the valid control signal update_valid in a case where the current value of the counter is greater than n and the detector NOR outputs  1 . Further, it is not necessary to set the detectors NA and AND 2  in the example of  FIG. 5 , and the functions of the selector US 1  and the multiplexers USEL and CSEL may be realized using the simple switch SW in the example of  FIG. 4 . It should be understood that the counting manner (including the initial value, the maximum value of counting, etc.) of the counter in this embodiment may not be limited to the above examples. 
     In another embodiment, it is provided a flag bit register which may be a register with at least n bits, n bits of which can be selected and each selected bit is made to be corresponding to one circuit unit Uk, respectively. For example, the rightmost bit corresponds to the circuit unit U 1 , and the second bit of the right corresponds to the circuit unit U 2 , and so on. The corresponding relationship between each bit in the flag bit register and each circuit unit Uk may be arbitrarily set as needed. 
     Each bit of the flag bit register may be set to 0. Then, in a case where a circuit unit Uk stores valid data, the bit in the flag bit register corresponding to Uk may be set to 1. Thereby, the value of the signal validk related to each circuit unit Uk may be simply and conveniently recorded. 
     In this embodiment, it is not necessary to provide the detectors X 1  to Xn or Xu, and each of the detectors A 1  to An or Au may receive an output from a corresponding one of the detectors XN 1  to XNn or Xu and an output Flags of this flag bit register. For example, the detector Ak may output the result of (Flags&amp;(1&lt;&lt;k)) &amp;&amp; matchk, wherein &amp; represents a bitwise AND operation, &lt;&lt;represents shifting to the left, 1&lt;&lt;k represents shifting the binary representation of 1 to the left by k bits, and &amp;&amp; represents logic determination of AND. 
     Further, in this embodiment, the signal controller SCON may conveniently determine whether all of the data in the register REG 2  of each circuit unit Uk are not 0 according to the value Flags in the flag bit register, and may simply and conveniently determine and select the circuit unit Uj with data being 0 in the corresponding register REG 2 . Accordingly, it is not necessary to provide the detectors NA, AND the selector US 2 , and it is not necessary for the detector AND 1  to receive the signals valid 1  to validk, instead, the detector AND 1  determines whether to output a valid control signal update_valid according to the output of the detector NOR and the value in the flag bit register. 
     It should be understood that implementation of the control logic circuit CON according to embodiments of the present disclosure may not be limited to the examples in  FIG. 4  to  FIG. 6 . 
     In a practical application, input data (e.g., one parsed data from the parser, or data from the output Val_out of another circuit module) may be provided to the input terminal Val_in of the circuit module as shown in any of  FIG. 3  to  FIG. 6 , and an initial counting value (e.g., 1 or data from the output terminal Cnt_out of another circuit module) is provided to the input terminal Cnt_in. 
       FIG. 7  and  FIG. 8  show an example of an apparatus for data statistics according to an embodiment of the present disclosure. 
     The apparatus shown in  FIG. 7  comprises a circuit module SC as shown in any of  FIG. 4  to  FIG. 6 , whose input terminal Val_in and Cnt_in may receive an input data Val_new and the constant value 1, respectively. 
     The apparatus shown in  FIG. 8  comprises a plurality of circuit modules SC 1 , SC 2 , . . . , SCn as shown in any one of  FIG. 4  to  FIG. 6  connected in series, wherein the input terminals Val_in and Cnt_in of each circuit module (e.g., SC 2 ) except for SC 1  may be respectively coupled to the output terminals Val_out and Cnt_out of the previous circuit module (e.g., SC 1 ) of this circuit module, and the input terminals Val_in and Cnt_in of the circuit module SC 1  may receive the input data Val_new and the constant value 1, respectively. 
     As shown in  FIG. 7  or  FIG. 8 , the apparatus may further comprise an update circuit UPC. Two input terminals of the update circuit UPC may be coupled to the output terminals Val_out and Cnt_out of the last one circuit module (also referred to herein as the last circuit module, for example, SC in  FIG. 7  or SCn in  FIG. 8 ), respectively, to receive the data Val_update and Cnt_update. 
     As described above, the update_valid of the control logic circuit CON may also be provided to the outside of the control logic circuit CON. Accordingly, in one embodiment, the SC in  FIG. 7  or the update circuit UPC in  FIG. 8  may be made to process the received Val_update and Cnt_update only in a case where the valid signal update_valid is detected or received. 
     Further, as shown in  FIG. 7  or  FIG. 8 , the apparatus may further comprise a parser PAR and/or a memory MEM. 
     The parser PAR may parse an input data stream Data_flow to be performed a statistic operation, and provide each generated parsed data Val_new to the SC or SC 1 . For example, in a case where the Data_flow is an image data stream, the parser PAR may parse information of one or more dimensions of the image from the image data stream, such as a luminance value, a color value of a pixel point in the image, and a serial number of subgraph to which the pixel point belongs and a combination of a plurality of information. For example, in a case where the image to be counted is divided into 4 rows and 3 columns, a total of 12 subgraphs by the image processing algorithm, the parser PAR may obtain the serial number of the subgraph (e.g., may be represented by 4 bits) where each pixel is located. Further, the parser PAR may combine the color information (e.g., RGB or YUV) of the pixel points themselves to generate a pixel information object to be performed a statistic operation as the parsed data Val_new. For example, the parsed data may be represented by 12 bits, wherein 4 bits represent the serial number of the subgraph to which the pixel belongs, and the other 8 bits represent the gray value of the pixel. For example, for a pixel with the gray value  250  in the subgraph (e.g., number is 7) of row  2  and column  0 , the corresponding parsed data may be (7, 250) or (2, 0, 250). 
     It should be understood that the type, the representation manner, and the like of the parsed data Val_new are not limited to the above example. Accordingly, the data stream Data_flow provided to the parser PAR is not limited to the image data stream, and the processing procedure and output in the parser PAR are not limited to the above example. In another embodiment, the parser PAR may be at outside of the apparatus and provide data to the apparatus via, for example, an  110  interface. 
     The memory MEM may be coupled to the update circuit UPC through an interface, and may receive a read address information R_addr from the update circuit UPC and return the stored old statistic value Old_Cnt related to the data Val_update to the update circuit UPC. Further, the stored statistic value related to the data Val_update may also be updated according to a write address W_addr from the update circuit UPC and a new statistic value New_Cnt related to the data Val_update. The memory MEM may be any type of memory realized by using any technology such as SRAM or DRAM, and may comprise one or more, for example, SRAM modules. In another embodiment, the memory MEM may be provided outside of the apparatus and communicate with the apparatus via the I/O interface of the apparatus. 
       FIG. 9  shows an example of the update circuit UPC in  FIG. 7  or  FIG. 8 . 
     As shown in  FIG. 9 , the update circuit UPC may comprise an address calculator ADDR_CAL and an adder (represented by “+” in  FIG. 9 ). 
     An input terminal of the address calculator ADDR_CAL may receive Val_update, calculate an address of the storage location of Val_update in the memory MEM according to Val_update, and transmit the calculated read address to the memory MEM, to generate a read logic for the memory MEM. 
     The adder may receive Cnt_update, and may receive the old statistic value Old_Cnt related to Val_update returned by the memory MEM, then add Cnt_update with Old_Cnt and obtain the new statistic value New_Cnt related to Val_update. Then, the update circuit UPC may transmit the write address W_addr (may be the same as the read address R_addr) and the new statistic value New_Cnt calculated by the adder to the memory MEM, and accordingly generate a write logic for the memory MEM. 
     Assuming that the delay (for example, period number) from obtaining the read address R_addr to starting to input the old statistic value Old_Cnt is m within the memory MEM, the delay in transmitting the old statistic value Old_Cnt from the memory MEM to the update circuit UPC is q, the delay caused by the calculation of the adder is c, the delay in transmitting the new statistic value New_Cnt and the write address W_addr to the memory MEM is w, then, the number of all circuit units of all statistical circuit arrays in all circuit modules SC or SC 1  to SCn coupled between the parser and the update circuit UPC may be made greater than or equal to m+q+c+w−1, to ensure the correctness of the data update, for example, to ensure that the old statistic value Old_Cnt read from the memory MEM each time must be a statistical result that has been previously updated correctly. 
     In a case where the memory MEM does not support performing both read operation and write operation to the same address at the same time, the number of all circuit units may be greater than m+q+c+w−1. For example, in a case where the memory MEM has no read/write path delay (or the read/write path delay may be ignored), if the memory MEM may return the read data in one period, and does not support performing both the read operation and the write operation to the same address at the same time, then, the number of all circuit units is only greater than c (i.e. the delay of the adder in the update circuit UPC). 
     Accordingly, the number of registers required in the apparatus according to embodiments of the present disclosure may only be greater than or equal to 2*(m+q+c+w−1) or greater than 2c, without necessarily providing a corresponding register for each data of all performed statistic operations, thereby the number of required registers may be greatly reduced, thus, hardware cost and power consumption are greatly reduced. 
     In order to coordinate the action of reading, calculation and storage of data and ensure the correctness of data update, as shown in  FIG. 9 , the update circuit UPC may also comprise delay elements D 1 , D 2 , D 3  and D 4 , wherein the delay elements D 1  and D 2  may be coupled in series between the address calculator ADDR_CAL and the memory MEM, and the delay elements D 3  and D 4  may be coupled in series between the output terminal Cnt_out of the last circuit module SC or SCn and the adder. 
     The delay element D 3  may delay the received Cnt_update by a periods to match the delay a caused by the processing in the address calculator ADDR_CAL. The delay elements D 1  and D 4  may output the received data after they are delayed b periods, b may be equal to r+m+q, wherein r represents the delay of transmitting the read address R_addr to the memory MEM. The delay element D 2  may delay the address information (W_addr) from the delay element D 1  related to the write logic of the memory MEM by c periods, to match the delay c caused by the processing in the adder. 
     In another embodiment, a delay element may be used to replace both delay elements D 1  and D 2 , and another delay element may be used to replace both delay elements D 3  and D 4 . In another embodiment, one or both of delay elements D 1  and D 2  may be included in the address calculator ADDR_CAL, and one or both of the delay elements D 3  and D 4  may be included in the adder. In another embodiment, the delay during the data transmission process may also be controlled by a software, and it does not need to provide a delay element in this embodiment. 
     The number of periods required from a pair of Val_update and Cnt_update entering into the update circuit UPC to the reading of the old statistic value Old_Cnt of the Val_update in the memory MEM is a+r+m+q, and the number of periods required from a pair of Val_update and Cnt_update entering into the update circuit UPC to the new statistic New_Cnt updated into the memory MEM is a+b+c+w=a+r+m+q+c+w. 
       FIG. 10  and  FIG. 11  show an example of a working process of an apparatus for data statistics according to an embodiment of the present disclosure. 
     In the example of  FIG. 10 , the apparatus comprises a circuit module for data statistics which includes six circuit units U 1  to U 6  for data statistics, and the six circuit units are connected together in series in the manner of the example in  FIG. 4  (i.e. n=6 in the example of  FIG. 4 ), and each of U 1  to U 6  is represented by two blocks adjacent to each other from top to bottom, and the upper block represents the register REG 1  of the corresponding circuit unit, and the block below represents the register REG 2  of the corresponding circuit unit. In a case where the data (i.e. statistic value) in the register REG 2  is 0, the data in the corresponding register REG 1  may be special invalid data x which is different from any of the parsed data. V 1  to v 7  represent valid parsed data that are different from each other. 
     Initially, each of the circuit units U 1  to U 6  does not store valid parsed data and corresponding statistic value, therefore, the data in the registers REG 2  of all circuit units is 0. 
     In the example of  FIG. 10 , the parsed data Val_new=v 6  is firstly provided to the apparatus. At this time, valid 1  to valid 6  are 0 (i.e. the data in the registers REG 2  of all the circuit units U 1  to U 6  is 0, and accordingly, the data in the registers REG 1  and REG 2  of all the circuit units U 1  to U 6  are invalid data), respectively, meanwhile, match 1  to match 6  are also 0, respectively. Therefore, the control logic circuit CON provides a valid Val_c signal, a valid Cnt_c signal, and an invalid Inc_c signal to each of the circuit units U 1  to U 6 , such that the circuit unit U 1  stores the parsed data v 6  in the corresponding register REG 1  and stores the statistic value 1 in the corresponding register REG 2 . 
     Each of the circuit units U 1  to U 5  respectively transfers the invalid data in the corresponding registers REG 1  and REG 2  to the corresponding subsequent circuit unit, for example, U 1  transfers the invalid data pair (x,0) originally stored in the registers REG 1  and REG 2  of U 1  to U 2 , and U 2  transfers the invalid data pair (x,0) originally stored in the registers REG 1  and REG 2  of U 2  to U 3 , and so on. The control logic circuit CON detects that the data in the circuit unit U 6  is invalid data (valid 6 =0), therefore, the control signal update_valid=0. Accordingly, the control logic circuit CON would not output an invalid data pair (x, 0) in the circuit unit U 6  at the output terminal Val_out and Cnt_out. 
     Then, the parsed data Val_new=V 5  is provided to the apparatus. At this time, the control logic circuit CON detects that valid 1 =1, valid 2  to valid 6  are 0, respectively, and match 1  to match 6  are all 0, respectively. Therefore, the control logic circuit CON provides each of the circuit units U 1  to U 6  with a valid Val_c signal, a valid Cnt_c signal, and an invalid Inc_c signal, such that the circuit unit U 1  transfer the previously stored valid data pair (v 6 , 1 ) to the circuit unit U 2 , and stores the parsed data v 5  in the corresponding register REG 1 , and stores the statistic value 1 in the corresponding register REG 2 . At this time, the data in the circuit unit U 6  is still invalid data (valid 6 =0), therefore, the control signal update_valid is still 0. Accordingly, the control logic circuit CON still could not output an invalid data pair (x,0) in the circuit unit U 6  at the output terminal Val_out and Cnt_out. 
     After processing six (the same as the number of circuit units comprised) different parsed data, each circuit unit would store valid data, respectively, i.e. the data in the register REG 1  of any one of the circuit units is valid data, and the data in the register REG 2  of any one of the circuit units is not 0, after that, the valid 1  to valid 6  in the example of  FIG. 10  would always become 1. 
     In the example of  FIG. 10 , in a case where the circuit units U 1  to U 6  store valid data pairs (v 1 , 2 ), (v 2 , 3 ), (v 3 , 1 ), (v 4 , 2 ), (v 5 , 4 ), and (v 6 , 4 ), respectively, Val_new=v 4  is provided to the apparatus. At this time, the control logic circuit CON may detect match 4 =1, and the other match 1  to match 3 , match 5  and match 6  are 0, respectively, i.e. the data stored in the register REG 1  of the circuit unit U 4  is the same as Val_new. Thus, the control logic circuit CON provides an invalid Val_c signal, an invalid Cnt_c signal, and a valid Inc_c signal to the control terminal of the circuit unit U 4 , and provides an invalid Val_c signal, an invalid Cnt_c signal, and an invalid Inc_c signal to the other circuit units, such that the value of the data in REG 2  of the circuit unit U 4  is incremented by 1, thus, the valid data pair stored in the circuit unit U 4  changes from (v 4 , 2 ) to (v 4 , 3 ), while the data stored in the other circuit units remain unchanged. 
     Meanwhile, although valid 6 =1, since the match 4 =1, therefore, the control signal update_valid is still 0. Accordingly, the control logic circuit CON could not output the data pair (v 6 , 4 ) in the circuit unit U 6  at the output terminals Val_out and Cnt_out. 
     Then, the apparatus receives the parsed data Val_new=v 6 . Similar to the previous case of Val_new=v 4 , the control logic circuit CON may detect match 6 =1, and the other match 1  to match 5  are 0, respectively, i.e. the data stored in the register REG 1  of the circuit unit U 6  are the same as Val_new. Thus, the control logic circuit CON provides an invalid Val_c signal, an invalid Cnt_c signal, and a valid Inc_c signal to the control terminal of the circuit unit U 6 , and provides an invalid Val_c signal, an invalid Cnt_c signal, and an invalid Inc_c signal to the other circuit units, such that the value of the data in REG 2  of circuit unit U 6  is incremented by 1, thus, the valid data pair stored in the circuit unit U 6  changes from (v 6 , 4 ) to (v 6 , 5 ), while the data stored in the other circuit units remain unchanged. Meanwhile, although valid 6 =1, since the match 6 =1, therefore, the control signal update_valid is still 0. Accordingly, the control logic circuit CON could not output the data pair (v 6 , 5 ) in the circuit unit U 6  at the output terminals Val_out and Cnt_out. 
     Then, the apparatus receives the parsed data Val_new=v 7 . At this time, the control logic circuit CON may detect that Val_new=v 7  is different from the data in REG 1  of each of the circuit units U 1  to U 6 , i.e. match 1  to match 6  are 0, respectively. Therefore, the control signal update_valid inside the control logic circuit CON is 1 at this time, such that the switch SW is turned on, thus, the data pair (v 6 , 5 ) stored in the circuit unit U 6  are output via the output terminals Val_out and Cnt_out. 
     In another aspect, the control logic circuit CON may provide a valid Val_c signal, a valid Cnt_c signal, and an invalid Inc_c signal to the control terminals of each of the circuit units U 1  to U 6 , such that each of the circuit units U 1  to U 6  updates the data in the corresponding registers REG 1  and REG 2  with the data received from the corresponding input terminals Val_i and Cnt_i. Since the circuit units U 1  to U 6  are connected in series, as a result, the data pairs in each of the circuit units U 1  to U 5  are respectively shifted backward into the subsequent circuit unit. For example, as shown in  FIG. 10 , (v 1 , 2 ) originally stored in U 1  is shifted backward into U 2 , and (v 5 , 4 ) originally stored in U 5  is shifted backward into U 6 . Meanwhile, the circuit unit U 1  stores a new data pair (v 7 , 1 ). 
     In response to the control logic circuit CON outputting the originally stored data pair (v 6 , 5 ) in the circuit unit U 6  via Val_out and Cnt_out, the update circuit UPC starts to work. The address calculator ADDR_CAL in the update circuit UPC receives Val_update=v 6 , and calculates an address 0xkkkk of storage location of v 6  in the memory MEM, and generates a read logic for the memory MEM based on a read address R_addr (0xkkkk). The memory MEM returns the old statistic value Old_Cnt=6 corresponding to v 6  to the update circuit UPC. The adder in the update circuit UPC receives the statistic value Cnt_update=5 from the control logic circuit CON and the old statistic value Old_Cnt=6 from the memory MEM, performs an add operation based on the both, and obtains a new statistic value New_Cnt=5+6=11. Then, the update circuit UPC generates a write logic based on the memory MEM, and transmits the write address W_addr (0xkkkk) and the new statistic value New_Cnt=11 to the memory MEM. Accordingly, the memory MEM may update the content at the address 0xkkkk from the original (v 6 ,  6 ) to (v 6 , 11 ). 
     Then, the apparatus receives the parsed data Val_new=v 6 . Since there is not the same data as v 6  in the circuit units U 1  to U 6  at this time, therefore, similarly to the case where the apparatus previously received the parsed data v 7 , the control logic circuit CON may detect that Val_new=v 6  is different from the data in REG 1  of each of the circuit units U 1  to U 6 , i.e. match 1  to match 6  are 0, respectively. Therefore, the control signal update_valid inside the control logic circuit CON is 1 at this time, such that the switch SW is turned on, thus, the data pair (v 5 , 4 ) stored in the circuit unit U 6  are output via the output terminals Val_out and Cnt_out. In another aspect, the control logic circuit CON may provide a valid Val_c signal, a valid Cnt_c signal, and an invalid Inc_c signal to the control terminals of each of the circuit units U 1  to U 6 , such that each of the circuit units U 1  to U 6  updates the data in the corresponding registers REG 1  and REG 2  with the data received from the corresponding input terminals Val_i and Cnt_i. Since the circuit units U 1  to U 6  are connected in series, as a result, the data pairs in each of the circuit units U 1  to U 5  are respectively shifted backward into the subsequent circuit unit. For example, as shown in  FIG. 10 , (v 7 , 1 ) originally stored in U 1  is shifted backward into U 2 . At the same time, the circuit unit U 1  stores a new data pair (v 6 , 1 ). 
     In response to the control logic circuit CON outputting the originally stored data pair (v 5 , 4 ) in the circuit unit U 6  via Val_out and Cnt_out, the update circuit UPC starts to work, and updates content related to V 5  in the memory MEM at 0xyyyy based on the data pair. 
     In the example of  FIG. 11 , the apparatus comprises a circuit module for data statistics, the circuit module includes six circuit units for data statistics, and six circuit units are connected in parallel in the manner of the example in  FIG. 5  (i.e. n=6 in the example of  FIG. 5 ). Similarly to the example of  FIG. 10 , in  FIG. 11 , each of U 1  to U 6  is also represented by two block adjacent to each other from top to bottom, and the upper block represents the register REG 1  of the corresponding circuit unit, and the below block represents the register REG 2  of the corresponding circuit unit. Similarly, in a case where the data (i.e. statistic value) in the register REG 2  is 0, the data in the corresponding register REG 1  may be a special invalid data x which is different from any of the parsed data. V 1  to v 7  represent valid parsed data that are different from each other. Further, as in the example in  FIG. 10 , initially, each of the circuit units U 1  to U 6  does not store valid parsed data and corresponding statistic values, therefore, the data in the registers REG 2  of all circuit units are 0. 
     In the example of  FIG. 11 , the parsed data Val_new=v 4  is firstly provided to the apparatus. At this time, valid 1  to valid 6  are 0 (i.e. the data in the registers REG 2  of all the circuit units U 1  to U 6  are 0, and accordingly, the data in the registers REG 1  and REG 2  of all the circuit units U 1  to U 6  are invalid data), respectively, meanwhile, match 1  to match 6  are also  0 , respectively. The control logic circuit CON selects (e.g., randomly) the circuit unit U 4  from the circuit units U 1  to U 6 , and provides a valid Val_c signal, a valid Cnt_c signal, and an invalid Inc_c signal to the circuit unit U 4 , and provides invalid Val_c signals, invalid Cnt_c signals, and invalid Inc_c signals to other circuit units, such that the circuit unit U 4  stores the parsed data v 4  in the corresponding register REG 1  and stores the statistic value 1 in the corresponding register REG 2 , and the data in the registers of other circuit units is still invalid data. Accordingly, the control logic circuit CON may generate an invalid control signal update_valid, such that it could not output any data at the output terminals Val_out and Cnt_out. 
     Then, parsed data Val_new=V 6  is provided to the apparatus. At this time, the control logic circuit CON detects that Val_new is different from the data in the register REG 1  of each circuit unit, and the data in the registers REG 2  of all the circuit units except for the circuit unit U 4  is still 0. Thus, the control logic circuit CON selects (e.g., randomly) the circuit unit U 6  from all other circuit units except for the circuit unit U 4 , for example, by the selector US 2 , and provides a valid Val_c signal, a valid Cnt_c signal, and an invalid Inc_c signal to the circuit unit U 6 , and provides invalid Val_c signals, invalid Cnt_c signals, and invalid Inc_c signals to all other circuit units except for U 6 , such that the circuit unit U 6  stores the parsed data v 6  in the corresponding register REG 1  and stores the statistic value 1 in the corresponding register REG 2 . Since the data in the circuit units U 1 , U 2 , U 3  and U 5  is still invalid data, therefore, the control logic circuit CON still generates an invalid control signal update_valid, such that it would not output any data at the output terminals Val_out and Cnt_out. 
     After processing six (the same as the number of circuit units comprised) different parsed data, each circuit unit would store valid data, respectively, i.e. the data in the register REG 1  of any one of the circuit units is valid data, and the data in the register REG 2  of any one of the circuit units is not 0, after that, valid 1  to valid 6  in the example of  FIG. 10  would always become 1. 
     In the example of  FIG. 11 , in a case where the circuit units U 1  to U 6  store valid data pairs (v 1 , 2 ), (v 2 , 3 ), (v 3 , 1 ), (v 4 , 2 ), (v 5 , 4 ), and (v 6 , 4 ), respectively, Val_new=v 4  is provided to the apparatus. At this time, the control logic circuit CON may detect match 4 =1, and the other match 1  to match 3 , match 5  and match 6  are 0, respectively, i.e. the data stored in the register REG 1  of the circuit unit U 4  is the same as Val_new. Thus, the control logic circuit CON provides an invalid Val_c signal, an invalid Cnt_c signal, and a valid Inc_c signal to the control terminal of the circuit unit U 4 , and provides invalid Val_c signals, invalid Cnt_c signals, and invalid Inc_c signals to the other circuit units, such that the value of the data in REG 2  of circuit unit U 4  is incremented by 1, thus, the valid data pair stored in the circuit unit U 4  changes from (v 4 , 2 ) to (v 4 , 3 ), while the data stored in the other circuit units remain unchanged. At this time, since match 4 =1, the control signal update_valid is 0. Accordingly, the control logic circuit CON could not output any data at the output terminals Val_out and Cnt_out. 
     The apparatus then receives the parsed data Val_new=v 6 . Similar to the previous case of Val_new=v 4 , the control logic circuit CON may detect match 6 =1, and the other match 1  to match 5  are 0, respectively, i.e. the data stored in the register REG 1  of the circuit unit U 6  is the same as Val_new. Thus, the control logic circuit CON provides an invalid Val_c signal, an invalid Cnt_c signal, and a valid Inc_c signal to the control terminal of the circuit unit U 6 , and provides invalid Val_c signals, invalid Cnt_c signals, and invalid Inc_c signals to the other circuit units, such that the value of the data in REG 2  of circuit unit U 6  is incremented by 1, thus, the valid data pair stored in the circuit unit U 6  changes from (v 6 , 4 ) to (v 6 , 5 ), while the data stored in the other circuit units remain unchanged. At this time, since match 6 =1, the control signal update_valid is 0. Accordingly, the control logic circuit CON could not output any data at the output terminals Val_out and Cnt_out. 
     Then, the apparatus receives the parsed data Val_new=v 7 . At this time, the control logic circuit CON may detect that Val_new=v 7  is different from the data in REG 1  of each of the circuit units U 1  to U 6 , i.e. match 1  to match 6  are 0, respectively. The control logic circuit CON makes the internal control signal update_valid to be 1 at this time. Accordingly, the control logic circuit CON selects (e.g., randomly) the circuit unit U 6  from the circuit units U 1  to U 6 , and outputs the data pair (v 6 , 5 ) stored in U 6  via the output terminals Val_out and Cnt_out, and then stores V 7  and  1  into the registers REG 1  and REG 2  of circuit unit U 6 , respectively. 
     In response to the control logic circuit CON outputting the originally stored data pair (v 6 , 5 ) in the circuit unit U 6  via Val_out and Cnt_out, the update circuit UPC starts to work. The address calculator ADDR_CAL in the update circuit UPC receives Val_update=v 6 , and calculates an address 0xkkkk of storage location of v 6  in the memory MEM, and generates a read logic for the memory MEM based on a read address R_addr (0xkkkk). The memory MEM returns the old statistic value Old_Cnt=6 corresponding to v 6  to the update circuit UPC. The adder in the update circuit UPC receives the statistic value Cnt_update=5 from the control logic circuit CON and the old statistic value Old_Cnt=6 from the memory MEM, performs add operation based on the both, and obtains a new statistic value New_Cnt=5+6=11. Then, the update circuit UPC generates a write logic based on the memory MEM, and transmits a write address W_addr (0xkkkk) and the new statistic value New_Cnt=11 to the memory MEM. Accordingly, the memory MEM may update the content at the address 0xkkkk from the original (v 6 ,  6 ) to (v 6 , 11 ). 
     Then, the apparatus receives the parsed data Val_new=v 6 . Since there is not the same data as v 6  in the circuit units U 1  to U 6  at this time, therefore, similarly to the case where the apparatus previously received the parsed data v 7 , the control logic circuit CON may detect that Val_new=v 6  is different from the data in REG 1  of each of the circuit units U 1  to U 6 , i.e. match 1  to match 6  are 0, respectively. The control logic circuit CON makes the internal control signal update_valid to be 1 at this time. Accordingly, the control logic circuit CON selects (e.g., randomly) the circuit unit U 4  from the circuit units U 1  to U 6 , and outputs the data pair (v 4 , 3 ) stored in U 4  via the output terminals Val_out and Cnt_out, and then stores V 6  and  1  into the registers REG 1  and REG 2  of the circuit unit U 4 , respectively. 
     In response to the control logic circuit CON outputting the originally stored data pair (v 4 , 3 ) in the circuit unit U 4  via Val_out and Cnt_out, the update circuit UPC starts to work, and updates content related to V 4  in the memory MEM at 0xyyyy based on the data pair. 
     In the above example, it is assumed that the frequency of parsed data provided by the parser matches the working frequency of hardware in the module or apparatus, e.g., the rate for the module or apparatus used for data statistics to receive parsed data is the same or similar to the rate for the module or device to complete statistics and/or updating of data. In another embodiment, the frequency for the parser to provide parsed data and the working frequency of the hardware may be different. Accordingly, more or fewer circuit units Uk may be used in the apparatus. The Circuit unit, circuit module, and apparatus for data statistics according to embodiments of the present disclosure are not limited to a particular relationship between data stream input and the working frequency of the hardware. 
     As described above, the circuit unit, circuit module, and apparatus for data statistics according to embodiments of the present disclosure may greatly reduce the number of required registers, thus, hardware cost and power consumption are greatly reduced. Further, the apparatus according to an embodiment of the present disclosure may initiate a read/write operation to the memory MEM only in a case where data needs to be updated, such that frequent memory access operation may be avoided, the overall processing efficiency of the apparatus may be greatly improved, and conflicts or statistical errors that may occur in data statistics and data storage may be avoided. 
     Unless otherwise required clearly in the context, throughout the description and claims, the wordings such as “comprise” and “include” are to be construed in an inclusive sense, as opposed to an exclusive or exhaustive sense, that is to say, in a sense of “including but not limited to”. Additionally, when used in the disclosure, the wordings of “herein”, “above”, “below” and similar wordings shall refer to the specification and claims as a whole but not to any specific portion of the disclosure. Where the context permits, the terms in the above description using the singular or plural may also include the plural or the singular. With regard to the wording “or” in a case where referring to a list of two or more items, the wording covers all of the following interpretations of the wording: any item in the list, all items in the list, and any combination of items in the list. Further, in the specification and claims of the present disclosure, in a case where the same term is modified by the different ordinal numeral “first”, “second”, etc., it is intended to distinguish the different entities to which the term refers, rather than to emphasize order or importance. 
     The embodiments of the present disclosure have been described, however, these embodiments are not intended to limit the scope of the present disclosure, and various omissions, substitutions and changes may be made without departing from the spirit of the disclosure.