Patent Publication Number: US-5523915-A

Title: Data storage system

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates to a data storage system for reading and displaying a plurality of stored data records in a predetermined sequence and, more particularly, to a data storage system using a non-volatile memory. 
     2. Description of the Prior Art 
     RAM (random access memory) is well known in the art as a data storage for storing many data records. In the RAM, however, the power source disconnection results in loss of the stored data. In order that the stored data remain when the power supply is cut, a non-volatile memory is used. 
     As a non-volative memory, EEROM or the like is well known, which is capable of electrically writing and erasing data. At present, however, EEROM has a limited write repetition number. That is, when the writing is repeated for more than a predetermined number of times, no further data can be written in that area or erroneous data is written. 
     When it is desired to store a plurality of data records in a predetermined (e.g., alphabetical or numerical) sequence, data sorting is carried out such that those data records succeeding a new data record are moved to next storage locations while the new data record is placed at a free area thus made. 
     With this method, however, it is necessary to shift all data records succeeding a data record to be added. This increases a number of times of writing in the data storage areas. Therefore, the method is not suited to the EEROM or the like with a limited write repetition number. 
     To store ordered data records in the EEPROM, each data record is stored together with immediately preceding and succeeding, i.e., backward and forward data storage area address pointers specifying the address of next data to be read out. 
     With this method of data recording, it is necessary only to set the backward and forward pointers of a data record to be added and to update the forward pointer of the immediately preceding data record and the backward pointer of the immediately succeeding record. This minimizes the number of writing operations in the EEPROM. 
     However, in the event of the failure of such pointers, the data link disconnection occurs so that no further data records can be read out or displayed. 
     SUMMARY OF THE INVENTION 
     It is, therefore, an object of the invention to provide a data storage system capable of displaying the stored data records even in the event of data link disconnection. 
     Another object of the invention is to provide a data storage system capable of reducing data errors in a memory with a limited write repetition number. 
     A further object of the invention is to provide a data storage system capable of writing data records even if a write error occurs during the writing operation. 
     To attain the above objects of the invention, there is provided a data storage system, which comprises data storage means having a plurality of data storage areas for storing data together with backward and forward data storage area address pointers, first read control means for sequentially reading out data stored in the data storage area of the data storage means in accordance with the pointers, and second read control means for reading out the data stored in the data storage areas of the data storage means in a predetermined sequence. 
     With this arrangement, the data storage system can read out and display the stored data reliably even in the event of data link disconnection of the stored data. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIGS. 1 to 9 illustrate a first embodiment of the invention, in which; 
     FIG. 1 is a block diagram showing the hardware arrangement of the data storage system as the first embodiment of the invention; 
     FIG. 2 is a diagram showing a map of an EEPROM 5 shown in FIG. 1; 
     FIG. 3 is a flow chart showing a write-to-EEPROM routine executed by the data storage system of FIG. 1; 
     FIG. 4 shows a new data record in RAM 4 to be added to EEPROM 5; 
     FIG. 5 shows the map of EEPROM 5 after the addition of the data record shown in FIG. 4; 
     FIG. 6 is a flow chart showing a read-forward-from-EEPROM routine executed by the data storage system of FIG. 1; 
     FIG. 7 shows a map of EEPROM 5 with a data record error; 
     FIG. 8 is a diagram showing a data display sequence when normal data are stored in EEPROM 5; and 
     FIG. 9 is a diagram showing a data display sequence when EEPROM 5 contains a data record error; 
     FIGS. 10 to 14 illustrate a second embodiment of the invention, in which: 
     FIG. 10 is a diagram showing an EEPROM map; 
     FIG. 11 is a flow chart showing a write-to-EEPROM routine executed by the second embodiment; 
     FIG. 12 is a diagram showing an example of data stored in the EEPROM; 
     FIG. 13 is a diagram showing EEPROM contents before updating; and 
     FIG. 14 is a view showing EEPROM contents after updating; and 
     FIGS. 15 to 17 illustrate a third embodiment of the invention, in which: 
     FIG. 15 is a diagram showing a storage map of EEPROM 5; 
     FIG. 16 is a diagram showing the configuration of a system field in EEPROM 5; and 
     FIG. 17 is a diagram showing how a data record is written in a spare data storage area in the case of a write failure in regular data storage areas. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Now, preferred embodiments of the invention will be described with reference to the drawings. 
     First Embodiment 
     FIGS. 1 to 9 illustrate a first embodiment of the invention. FIG. 1 is a block diagram showing a hardware arrangement of the data storage system of the embodiment. According to control programs stored in a ROM 2, a control unit (CPU) 1 receives input directory data indicative of names, addresses, etc. from a key input unit 3 and loads it into RAM 4 for temporal storing. Afterwards, CPU 1 saves the data into a non-volatile memory in the form of EEPROM 5. To read out the data records from the EEPROM 5, a forward or reverse retrieval cursor key 3a or 3b in the key input unit 3 is operated. In response to such operation, CPU 2 reads stored data records in accordance with stored pointers (e.g., in an alphabetically forward or reverse sequence) and displays them on a liquid crystal display unit 6. 
     A power supply 7 stabilizes the output voltage of a battery 8 (e.g., solar type)and supplies it to various parts of the system. For writing data in the EEPROM 5, the power supply 7 stabilizes a comparatively high external voltage supplied from external input terminals 9 and supplies it to EEPROM 5. This is because the EEPROM 5 writing requires a higher voltage than the normal operation voltage. 
     The storage configuration of the EEPROM 5 will now be described with reference to FIG. 2. In this embodiment, addresses 1 to 100 are allotted to a system area 10 for storing system data to be described later. Addresses 101 to 400 are allotted to a data area 11 for storing data records. Addresses 401 to 512 are allotted to a spare area 12 for storing data records. 
     The data area 11 is made up of a plurality of (e.g., 300) of record storage areas 11A 1 , 11A 2 , . . . , 11A 300 . Each record storage area 11A is designated by a single address. Each record storage area 11A n  has a field 11a for storing a backward pointer indicative of the address of the immediately preceeding record storage area, a field 11b for storing directory data of name, address, etc., a field 11c for storing a forward pointer indicative of the address of the immediately succeeding record storage area and an error check field 11d for storing a specific error check code. 
     The data records stored in the data area 11 can be displayed in a pointer-dictated sequence (e.g., alphabetical order in this embodiment) by sequentially reading the backward or forward pointers 11a or 11c. Further, in this embodiment a specific code (&#34;10&#34; in this embodiment) is written in the error check field 11d. When reading out data, CPU 1 tests the code to determine whether the record storage area 11A n  is normal or not. This will be described later in more detail. 
     The system area 10 is made up of a plurality of (e.g., 100) of system data storage areas 10A 1  to 10A 100 . Each system data storage area 10A n  has a field 10a for storing a top pointer to the top record area storing the first one of the sequenced data records, a field 10b for storing a bottom pointer to the bottom record area storing the last one of the sequenced data records, a field 10c for storing a current pointer to the record area of the currently displayed data record, a field 10d for storing a free area pointer to the top free address in the data area 11, and field 10e for storing an abnormality flag which is set upon occurrence of a failure of writing data in the data area 11. The spare data area 12 has the same configuration as the regular data area 11. 
     Suppose that four data records are stored in the data area 11 as shown in FIG. 2. The first data record &#34;AIDA . . . &#34; at address &#34;101&#34; has the backward pointer 11a of &#34;104.&#34; This points to the record area storing the last data record &#34;YAGISHITA . . . &#34; The forward pointer &#34;102&#34; of the data record &#34;AIDA . . . &#34; points to the immediately succeeding record area with the data record &#34;DAN . . . &#34; 
     The backward pointer &#34;101&#34; of the second data record &#34;DAN . . . &#34; at address &#34;102&#34; indicates the address of the first data record &#34;AIDA . . . &#34; immediately preceding the data record &#34;DAN . . . &#34; 
     The system area 10 has the top pointer 10a of &#34;101&#34;, which specifies the address of the top data record &#34;AIDA . . . &#34; in the alphabetically sequenced data records. The bottom pointer 10b of &#34;104&#34; indicates the address of the last or bottom data record &#34;YAGISHITA . . . &#34; The free area pointer 10d of &#34;105&#34; specifies the top address of a free area in the data area 11. The abnormal flag 10e normally has a value &#34;0&#34;, and is set to &#34;1&#34; when an abnormality is detected in a data storage area 11A i . 
     The writing operation of the data storage system having the above construction will be described with reference to the flow chart of FIG. 3. 
     Referring to FIG. 3, step S1 loads input data from the key input unit 3 (new data record) to the RAM 4. Then, the write key 3c is operated and detected (step S2). The next step S3 checks if a writing voltage is supplied externally. Then, the affirmative step S4 is executed to see whether the free area pointer 10d is &#34;401&#34; or more. If this is the case, there is no free area in the data area 11, and step S9 visually indicates that the data area is full. If no writing voltage is found (S3), an error is displayed in step S10. 
     If the free area pointer is less than &#34;401&#34; (S4), there is a free area in the data area 11. Thus, step S5 is executed to search for the immediately preceding and succeeding data records, relative to the new data record to be added. To this end, step S5 compares the character string of the new data record with those of data records read out from the data area 11. 
     Then, step S6 writes, in EEPROM 5 at the address specified by the free area pointer, data of the new record from the RAM 4 together with the backward and forward pointers 11a and 11c. Further, check code &#34;10&#34; is written in the error check field 11d. Step S7 updates the forward pointer of the preceding data record and the backward pointer of the succeeding data record such that each pointer points to the new data record now written in EEPROM 5. 
     In this way, the new data record has been written in a free area. Thus, step S8 searches for the next free area and updates the free area pointer 10d to the free area found. The new data record can be the first or last one in the stored data record set. In such case, the top or bottom pointer is updated accordingly, using the address of the new data record. 
     Now, the data writing operation will be described more specifically in the case of writing data record &#34;NAKANO . . . &#34;, shown in FIG. 4, from RAM 4 to EEPROM 5 which stores four directory data records &#34;AIDA . . . &#34;, &#34;DAN . . . &#34;, etc. as shown in FIG. 2. 
     At first, step S5 searches for the data records alphabetically preceding and succeeding the data record &#34;NAKANO . . . &#34; As a result, the data records &#34;KANEMARU . . . &#34; and &#34;YAGISHITA . . . &#34; are found as preceding and succeeding ones, respectively. Thus, the next step S6 writes the data &#34;NAKANO . . . &#34; in the free area address &#34;105&#34; specified by the free area pointer 10d in the system area 10. Further, the backward pointer 11a of &#34;NAKANO . . . &#34; record at address &#34;105&#34; is set to the address &#34;103&#34; of the data record &#34;KANEMARU . . . &#34; immediately preceding the data record &#34;NAKANO . . . &#34; whereas the forward pointer 11c of &#34;NAKANO . . . &#34; record is set to the address &#34;104&#34; of the immediately succeeding data record &#34;YAGISHITA . . . &#34; The check code &#34;10&#34; is also written in the error check field 11d of the address &#34;105.&#34; 
     Then, step S7 updates the forward pointer 11c of the preceding data record &#34;KANEMARU . . . &#34; and the backward pointer of the succeeding data record &#34;YAGISHITA . . . &#34;, each to the address &#34;105&#34; of the added data record &#34;NAKANO . . . &#34; 
     As a result, the directory data record &#34;NAKANO . . . &#34; is preserved in EEPROM 5 with a bidirectional link to the data records &#34;KANEMARU . . . &#34; and &#34;YAGISHITA . . . &#34; as shown in FIG. 5. Further, since at this time the address &#34;105&#34; is no longer any free area, step S8 updates the free area pointer 10d in the system area 10 to free area address &#34;106.&#34; 
     Now, the reading operation from the EEPROM 5 in response to the operation of the forward retrieval cursor key 3a will be described with reference to FIG. 6. At first, step S11 checks as to whether the abnormal flag 10e in the system area 10 has been set to &#34;1&#34;. 
     If this is not the case, step S12 is executed to update the current pointer 10c to the forward pointer 11c of the current data record, thus specifying the next data record to be read out. Step S13 checks as to whether correct error check code &#34;10&#34; has been stored in the error check field 11d of the next data record, now specified by the updated current pointer 10c. 
     If the correct code &#34;10&#34; has been read out from the error check field 11d, this means that the pertinent data record area 11A i  is normal. Thus, step S14 is executed-to read out the name-and-address data of that data record specified by the current pointer 10c and display it on the liquid crystal display 6. 
     If the step S13 has read an erroneous code having a numeral other than &#34;10&#34; from the error check field 11d, this means that the pertinent data record area 11A i  is defective. Thus, step S15 is executed to set the abnormal flag 10e to &#34;1&#34;. Then, the routine goes to the step S14 to read out the name-and-address data in the record area designated by the current pointer 10c display on the liquid crystal display 6. 
     Once the abnormal flag 10e has been set to &#34;1&#34;, this is confirmed by step S11 in response to the next operation of the forward retrieval cursor key 3a. The routine thus goes to step S16 to increment the current pointer 10c by one. The next step S17 checks as to whether the current pointer 10c has exceeded &#34;400&#34;. If this is the case, step S18 is executed to return the current pointer 10c to the data area 11 starting address &#34;101.&#34; 
     After the step S17 finding the current pointer 10c of &#34;400&#34; or less, or after the step 18 returning the current pointer 10c, step S19 is executed to check as to whether the data in the current data record area is normal. This is done by testing the error check code field 11d to see whether it has a correct value of &#34;10&#34; or not. If the data is not normal, the routine goes back to step S16 to increment the current pointer 10c to get access to the data record placed at the next address. 
     If the data is normal, the routine goes to step S14 to display the data in the record area specified by the current pointer 10c on the liquid crystal display 6. 
     Specifically, with the abnormal flag 10e set to &#34;1&#34;, each operation of the forward retrieval cursor key 3a causes the steps S11, S16 to S19 and S14 to be executed. In this way, the data records stored in the data area 11 are displayed in their address-increasing order. 
     Now, examples of display will be described with reference to FIGS. 8 and 9, in which EEPROM 5 has five directory data records. In the first example, the data record areas 11A are all normal as shown in FIG. 5. In the second example there is an abnormal data record area as shown in FIG. 7. 
     When all data record areas 11A are normal, successive operations of the forward retrieval cursor key 3a cause the stored data records to be retrieved in the forward alphabet order by following forward pointers, one after another. Thus, the data records are displayed in the order of &#34;AIDA . . . &#34;, &#34;DAN . . . &#34;, &#34;KANEMARU . . . &#34;, etc, as shown in FIG. 8. By successively operating the reverse retrieval cursor key 3b instead of the key 3a, the data records are displayed in the reverse alphabet order by following backward pointers, one after another. 
     If there is abnormality in the data storage area with the data record &#34;DAN . . . &#34;, for instance, the data storage system reads an erroneous check code (having a value other than &#34;10&#34;) from the record &#34;DAN . . . &#34;, thus setting the abnormal flag 10e to &#34;1&#34;. 
     FIG. 7 shows the contents of EEPROM 5 in which the abnormal flag 10e is set to &#34;1&#34; due to abnormality of the data record area 11A with the data record &#34;DAN . . . &#34; 
     In this case, the abnormal flag 10e has been set. Thus, successive operations of the forward retrieval cursor key 3a cause the data records to be retrieved and displayed in an address increasing order. Specifically, the first operation of the forward retrieval cursor key 3a results in displaying the data record &#34;AIDA . . . &#34; of the top address &#34;101&#34;. The data record &#34;DAN . . . &#34; of the next address &#34;102&#34; is accessed in response to the second operation of key 3a. However, since this data record is defective, it is not displayed but is skipped. Successive operations of the reverse retrieval cursor key 3b instead of the key 3a result in displaying the data records in an address decreasing order. 
     In this manner, a failure of writing in a data storage area 11A in the EEPROM 5 causes setting the abnormal flag 10e. Then data records in the EEPROM 5 are displayed in a predetermined order, here, in an address order without referencing backward or forward pointers. Thus, the present data storage system can display the data records from the EEPROM 5 even in the event of data link disconnection caused by a pointer error. 
     Second Embodiment 
     FIGS. 10 to 14 illustrate a second embodiment of the invention. In this embodiment, the hardware arrangement is the same as that of the first embodiment shown in FIG. 1. Parts like those in the first embodiment are designated by like reference numerals and symbols and are not described in detail. 
     FIG. 10 shows a map of the EEPROM 5 in accordance with the second embodiment. In this embodiment, addresses &#34;1&#34; to &#34;100&#34; are allotted to a system area 14 to be described later, addresses &#34;101&#34; to &#34;400&#34; are allotted to a data area 15, and addresses &#34;401&#34; to &#34;512&#34; are allotted to a spare data area 12. 
     The data area 15 comprises a plurality of (here, 300) data record areas 15A 1 , 15A 2 , . . . , 15A 300 . In this embodiment, a directory data record with data amount exceeding the storage capacity of a single storage area is recorded over a plurality of storage areas. 
     Each data record area 15A has a field 15a for storing a continuation pointer to a data record area where a continuation part of a data record is stored if the data record is occupied by a plurality of data record areas, a field 15b for storing a backward pointer to an alphabetically preceding data record, a field 15c for storing directory or name-and-address data, and a field 15d for storing a forward pointer to an alphabetically succeeding data record. The space data area 12 also comprises a plurality of data record areas and has the same configuration as the data area 15. 
     The system area 14 stores system data for managing the data area 15. The system area 14 comprises a plurality of system data storage areas 14A 1 , 14A 2 , . . . , 14A 100 . Each system data storage area 14A has a field 14a for storing a top pointer specifying the top one of the sequenced data records in the data area 15, a field 14b for storing a bottom pointer indicative of the bottom one of the data records, a field 14c for storing a current pointer specifying a data record currently in display, a field 14d for storing a free area pointer indicative of a free area starting address in the data area 11, and a field 14e for storing a free area pointer indicative of a free area starting address in the data area 11, and a field 14e for storing a free spare area pointer indicative of a free area starting address in the spare data area 12. 
     In accordance with the second embodiment, each time when system data is updated, the data storage system writes it in a different one of the system data areas by selecting first the area 14A1, then 14A2, then 14A3 and so on, thus avoiding repeated writing operations in the same area. 
     FIG. 10 shows three data records &#34;AIDA . . . &#34;, &#34;KAMATA . . . &#34; and &#34;YAGI . . . &#34; stored in the data area 15 in an alphabetical order. The data record &#34;AIDA . . . &#34; is recorded over the addresses &#34;101&#34; and &#34;102&#34; because of its large data quantity. 
     The address &#34;101&#34; stores a first part of the top data record &#34;AIDA . . . &#34; in the alphabet sequence. The continuation pointer 15a at address &#34;101&#34; specifies the continuation address &#34;102&#34; of the continuation part of this data record. The backward pointer 15b of &#34;104&#34; specifies the alphabetically preceding data record, here, the bottom or last data record &#34;YAGISHITA . . . &#34; The forward pointer 15d points to the address &#34;103&#34; of the succeeding data record &#34;KAMATA . . . &#34; 
     The address &#34;103&#34; stores the second data record &#34;KAMATA . . . &#34; in the alphabet sequence. Since this data record occupied a single data storage area 11A, its continuation pointer 15 has a null value. The backward pointer 15b has the value of &#34;101&#34; specifying the preceding data record &#34;AIDA . . . &#34; The forward pointer 15c has the value of &#34;104&#34; pointing to the succeeding data record &#34;YAGI . . . &#34; 
     In the system area 14, the top pointer 14a indicates the address &#34;101&#34; of the top or first data record &#34;AIDA . . . &#34; The bottom pointer 14b indicates the address &#34;104&#34; of the bottom or last data record &#34;YAGISHITA . . . &#34; The current pointer 14c indicates the address &#34;103&#34; of the data record &#34;KAMATA . . . &#34; The free area pointer 14d points to the starting address &#34;105&#34; of the free area in the data area 15. The free spare area pointer 14e points to the top address &#34;401&#34; of the spare data area 12. 
     The EEPROM writing operation of the data storage system of the second embodiment will now be described with reference to the flow chart of FIG. 11. 
     Referring to FIG. 11, step S21 loads input data from the key input unit 3 into RAM 4. Then, the write key 3c is operated. This is detected at step S22. The next step S23 checks as to whether an external write voltage is supplied to the external input terminals 9. If this is the case, the step S24 is executed to check as to whether the free area pointer 14d is at least &#34;401&#34;. If so, all data record storage areas of the data area 15 are occupied by data records. Thus, the routine goes to step S25 to indicate the full state of EEPROM 5 on the liquid crystal display 6. If no external write voltage supply is found at step S23, step S26 is executed to display the error. 
     If the free area pointer 14d is found to be &#34;400&#34; or less (step S24), that is, if there is a free area in the data area 15, step S27 is executed to search for the data records alphabetically preceding and succeeding a data record to be written. To this end, step S27 compares the character string of the data record to be written with those of data records read out from the data area 15. 
     The next step S28 writes the name-and-address data from RAM into the field 15c of the address indicated by the free area pointer 14d, and writes the addresses of the preceding and succeeding data records into the backward and forward pointer fields 15a and 15c, respectively. Once writing the data record, step 28 tests the writing by comparing the data before and after the writing. If mismatched, step 28 executes the second writing and repeats the writing test. 
     If step S29 finds successful writing, step S30 is executed to update the system data in the system area 14. 
     The system data updating step S30 will now be described with reference to FIGS. 10 and 12. 
     First, the description takes up writing an input data record &#34;NAKANO . . . &#34; into EEPROM 5 with data records shown in FIG. 10. 
     Since the free area pointer 14d points to address &#34;105&#34;, the data record &#34;NAKANO . . . &#34; is written in the address &#34;105&#34;. The data writing in the address &#34;105&#34; causes changing the top address of the free area in the data area 15 from &#34;105&#34; to &#34;106&#34;, requiring updating the system data in terms of the free area pointer. At the previous updating, the system data was written at the address &#34;1&#34; in the system area 14 as shown in FIG. 10. At this time, updated system data is written at the next address &#34;2&#34;. 
     Specifically, the free area address &#34;106&#34; is written in the free area pointer field 14d of the address &#34;2&#34; in the system area 14. The current pointer is updated to &#34;105&#34; and written in the field 14c of address &#34;2.&#34; The other pointers are not changed and thus copied into corresponding fields of address &#34;102.&#34; 
     Now, the description takes up correcting or updating a data record in the EEPROM 5 with reference to FIGS. 12 to 14. 
     In FIG. 12 four directory data records &#34;AIDA . . . &#34;, &#34;KAMATA . . . &#34;, &#34;YAGI . . . &#34; and &#34;NAKANO . . . &#34; have been stored in the data area 15 of EEPROM 5. The top pointer 14a in the system area 14 points to the address &#34;101&#34; of the top data record in the data area. The bottom pointer 14b points to the address &#34;104&#34; of the bottom data record. The current pointer 14c points to the address &#34;103.&#34; The free area pointer 14d points to the top address &#34;106&#34; of the free area in the data area 11. The free spare area pointer 14e specifies the top address &#34;401&#34; of the free area in the spare data area 12. 
     It is now desired to write an input data record &#34;OGAWA . . . &#34; while the data record &#34;KAMATA . . . &#34; (to be deleted) at address &#34;103&#34; is in display. To this end, the data storage system writes the data record &#34;OGAWA . . . &#34; in the free area address &#34;106&#34; specified by the free area pointer 14d. At the same time, it searches through the data area 15 (except for &#34;KAMATA . . . &#34;) for the data records alphabetically preceding and succeeding the data record &#34;OGAWA . . . &#34;, and sets the backward and forward pointers 15b and 15d to their addresses. Further, it updates the forward pointer of the preceding data record and the backward pointer of the succeeding data record each equal to the address &#34;106&#34; (see FIG. 13). The data storage system deletes the data record &#34;KAMATA . . . &#34; at address &#34;103.&#34; 
     As a result of this data updating, the top address of the free area is changed. Thus, the system data updating is effected. Since the previous system data has been written at address &#34;2&#34; in the system area 14, the system data updated this time is written in the next address &#34;3&#34;. 
     As a result, system pointers are written in the address &#34;3&#34; of the system area 14 as shown in FIG. 14. Since the area of the address &#34;103&#34; is made free, the free area pointer 14d is updated to &#34;103&#34;. The current pointer 14c is updated to the address &#34;106&#34; of the added data record &#34;OGAWA . . . &#34;. 
     Referring back to FIG. 11, if step S29 has failed twice in writing data in a record area 15A, the area is considered defective. Then the routine goes to step S31 to select the spare free area pointer 14e as the data write address. The routine then goes back to step S28 to write the input data record (i,e., name-and-address data, backward and forward pointers) in the address indicated by the free spare area pointer 14e. In addition, the backward pointer 15b of the succeeding data record and the forward pointer 15d of the preceding data record are updated to the spare data area address. Then, the step S29 and following steps are executed. 
     In this manner, the data storage system of the second embodiment effects the system data updating by changing a system data storage area in which updated system data is written, thus preventing repeated writing in the same storage area. 
     The above configurations of the system and data areas 14 and 15 for storing system data and directory data are by no means limitative, and can be modified. 
     Further, while in the above embodiment data records in EEPROM are sequenced, system data updating feature of the invention is also applicable to unsequenced data records. 
     Third Embodiment 
     FIGS. 15 to 17 illustrate a third embodiment of the invention. In this embodiment, the hardware arrangement is the same as that of the first embodiment shown in FIG. 1, and the flow chart of the operation routine is the same as that of the second embodiment shown in FIG. 11. The third embodiment employs, however, a different data arrangement of EEPROM 5. The data records are classified into open and secret ones. Access to secret data records are prohibited without a pass code. 
     FIG. 15 shows the storage configuration of EEPROM 5 in accordance with the third embodiment. In EEPROM 5, addresses &#34;1&#34; to &#34;400&#34; are allotted to a data area 16, and addresses &#34;401&#34; to &#34;512&#34; are allotted to a spare data area 17. 
     The data area 16 comprises a plurality of (for instance 400) data storage areas 16A 1 , 16A 2 , . . . 16A i . A data record beyond the storage capacity of a single data storage area 16A, is recorded over a plurality of data storage areas 16A. 
     Each data storage area 11A has a system field a (management field) for storing system data (management data), a field b for storing a continuation pointer indicative of the address of a continuation part of a data record (if any), a field c for storing a backward pointer indicative of the address of the alphabetically preceding data record, a field d for storing a forward pointer indicative of the address of the succeeding data record, and a field e for storing directory (name-and-address) data. The spare data area 17 also comprises a plurality of (for instance 112) spare data storage areas 17A 1 , 17A 2 , . . . 17A i  and has the same configuration as the data area 16. 
     FIG. 16 shows the format of a system field a. 
     The system field a is represented by seven bits. The first bit a 1  indicates whether the data record is open or secret. The bit a 1  of &#34;1&#34; indicates a secret data record. For an open data record, the bit a 1  is set to &#34;0.&#34; 
     The second bit a 2  indicates whether the data record is the top record in the alphabetically sequenced data record set stored in the area 16 and 17. The bit a 2  of the top record is set to &#34;1.&#34; For other records, bit a is set to &#34;0.&#34; 
     The third bit a 3  indicates whether the data record is the last record in the alphabetically sequenced record set, and is set to &#34;1&#34; for the last record, otherwise set to &#34;0.&#34; 
     The fourth and fifth bits a 4  and a 5  indicate a number of areas occupied by the data record. The bits a 4  and a 5  are set to &#34;01&#34; for a single-area data record, &#34;10&#34; for a two-area data record, and &#34;11&#34; for a three-area record. 
     The sixth bit a 6  indicates whether the data storage area 16A is the first free area. The bit a 6   is set to &#34;1&#34; for the first free area, otherwise set to &#34;0.&#34; 
     The seventh bit a 7  indicates whether the spare storage area 17A is the top free spare area. The bit a 7  is set to &#34;1&#34; for the top free spare area, otherwise set to &#34;0.&#34; 
     In FIG. 15, the data area 16 stores three data records of &#34;A . . . &#34;, &#34;B . . . &#34;, and &#34;D . . . &#34; at fields e. The data record &#34;A . . . &#34; has a large data quantity and is recorded over addresses &#34;1&#34; and &#34;2.&#34; 
     The continuation pointer b of the record &#34;A . . . &#34; at address &#34;1&#34; points to address &#34;2&#34; of a continuation part of the record. The backward pointer c points to address &#34;3&#34; of, here, the last data record &#34;D . . . &#34; The forward pointer d points to address &#34;4&#34; of the alphabetically succeeding data record &#34;B . . . &#34; 
     The bit a 1  in the system field a of address &#34;1&#34; is set to &#34;0&#34; if the record &#34;A . . . &#34; is open. If the record &#34;A . . . &#34; is secret, it is set to &#34;1.&#34; The bit a 2  is set to &#34;1&#34; since the data record &#34;A . . . &#34; is the top one in the data record set in terms of alphabetical order. The bit a 3  is set to &#34;0.&#34; The bits a 4  and a 5  are set to &#34;10&#34; because the data record &#34;A . . . &#34; occupies the two addresses &#34;1&#34; and &#34;2&#34;. Since these areas are occupied by data, bits a 6  and a 7  are each set to &#34;0&#34;. 
     The continuation pointer b of the second data record &#34;B . . . &#34; at address &#34;4&#34;, has a null value since this data record is not divided. The backward pointer c points to the address &#34;1&#34; of the preceding data record &#34;A . . . &#34; The forward pointer d points to the address &#34;3&#34; of the succeeding data record &#34;D . . . &#34; 
     Now, the data writing operation of the data storage system having the above arrangement will be described with reference to the flow chart of FIG. 11. 
     Referring to FIG. 11, step S21 loads RAM 4 with input data from the key input unit 3. Then the write key is operated and detected (step S22). This causes step S23 to test the external write voltage supply. If the external write voltage is supplied, the routine goes to step S24 to search for a top free area. This is done by looking for an area having bit a 6  of &#34;1&#34; in its system field a. 
     If no such area is found, that is, if there is no free area in the data area 16, the routine goes to step S25 to display, on the liquid crystal display 6, full state of EEPROM 5. If no external write voltage is supplied (step S23), the error is displayed in step S26. 
     If a free area is found in the data area 16 (step 24), step S27 is executed to search for the data records alphabetically preceding and succeeding the data record to be written this time. To this end, step S27 compares the character string of the name-and-address data to be written with those of the name-and-address data records read out from EEPROM 5. 
     The next step S28 writes the name-and-address data from RAM 4 into EEPROM 5 at the free area address with system bit a 6  of &#34;1.&#34; Further step S28 writes backward and forward pointers c and d using the addresses of the preceding and succeeding data records. In addition, step S28 updates the forward pointer of the preceding data record and the backward pointer of the succeeding data record, each equal to the address in which the new data record is written this time. 
     Then step 29 tests the writing by comparing the data before the writing with those after the writing. If the first writing has failed, step 29 executes the second writing, and tests it. 
     If successful writing is found, the routine goes to step S30 to update system fields. Specifically, bit a 6  of the system field a at the new data record address is set to &#34;0&#34; indicative of &#34;data occupied.&#34; Sequential search is performed for a free area. If found, the bit a 6  of the system field at the free area address is set to &#34;1&#34; indicative of a top free area. The new data record can be the top or bottom data record. If this is the case, bit a 2  (top) or a 3  (bottom) of the new data record is set to &#34;1.&#34; 
     If step S29 has failed twice in data writing, that data storage area 16A is considered defective. Thus, the routine goes to step S31 to search for a top free spare area. This is done by successively retrieving the system fields a in the spare data storage areas 17A to find out an area with bit a 7  of &#34;1.&#34; If the top free spare area is found, the new record (i.e., input name-and-address data, backward and forward pointers, and system data) is written in that spare data storage area 17A. Further, the backward pointer c of the succeeding data record and the forward pointer d of the preceding data record are updated to the address of the new data record storage area 17A . 
     In this manner, write failure of a data storage area 16A in the data area 16 is compensated for by writing in a spare data storage area 17. Thus, it is always possible to record data records up to the storage capacity of the data area 16 (i.e., 400 data records in this embodiment). Since the spare data area 17 is used only when write failure in a data storage area 16A has occurred, there will be no or rare write failure in the spare data area 17, thus assuring reliable writing. 
     The description now takes up a case in which writing data record &#34;C . . . &#34; in address &#34;5&#34; was attempted twice but failed. 
     At first, the data storage system searches for a top free spare area by sequentially reading system fields of the spare data storage area 17. The top free spare area is located at address &#34;401.&#34; Then, the data storage system writes the input data record &#34;C . . . &#34; in address &#34;401.&#34; It searches for data records preceding and succeeding the record &#34;C . . . &#34; The preceding data record is &#34;B . . . &#34; at address &#34;4&#34; whereas the succeeding data record is &#34;D . . . &#34; at address &#34;3.&#34; Thus, the backward pointer c of the record &#34;C . . . &#34; is set to the preceding record address &#34;4&#34;, and the forward pointer d is set to the succeeding record address &#34;3.&#34; 
     Further, the forward pointer d of the preceding record &#34;B . . . &#34; and the backward pointer c of the succeeding record &#34;D . . . &#34; are each set to the &#34;C . . . &#34; record address &#34;401.&#34; 
     To summarize, in accordance with the third embodiment, each data storage area 16A, 17A in data and spare areas 16, 17 is provided with a system field a for storing system or management data. The system data indicates on a bit-by-bit basis whether the data record is the top data record, whether it is the bottom data record, whether it is the top free area, whether it is the top free spare area, and so on. This storage allocation takes advantage over a storage allocation using separate areas for system and data in terms of minimizing the required storage capacity. 
     In the third embodiment, the system field a is configured by seven bits, but can be modified. The data records in EEPROM 5 are sequenced. The invention, however, can apply to unsequenced data records. 
     In the embodiments, EEPROM is employed for storing data records. However, other memories, e.g., a RAM, a ferroelectric RAM (FRAM), an EROM, a magnetic disk, etc. could be used. The present data storage system can apply to small size electronic cauculators, electronic diaries, word processors, personal computers, etc.