Patent Publication Number: US-6710617-B2

Title: Variable slew rate control for open drain bus

Description:
FIELD OF THE INVENTION 
     The present invention pertains generally to transmission lines in integrated circuits, and more particularly to a method and circuit for controlling the slew rate of a transitioning signal on a node of integrated circuit using stepwise impedance reduction/augmentation. 
     BACKGROUND OF THE INVENTION 
     Integrated circuits provide communication using digital signals. In the digital world, a digital signal may be in one of a plurality of predefined quantized states. Because digital signals are transmitted using an analog signal along a transmission line, the predefined quantized states of the digital signal are represented by different ranges of voltages within the total voltage range of the signal. For example, a typical digital integrated circuit (IC) based on a binary system will communicate using two states—zero (“0”) or LOW, and one (“1”) or HIGH. The digital state of “0” is represented by the range of voltages between a minimum voltage V MIN  (e.g., 0 volts) of the potential voltage range of the signal and a voltage V LOW  that is low relative to the total range of voltage, whereas the digital state of “1” is represented by the range of voltages between a voltage V HIGH  that is high relative to the total range of voltages and a maximum voltage V MAX  (e.g., 1.5 volts) of the potential voltage range of the signal. In the binary system example, the state of the digital signal is unknown when the voltage level of the signal is between V LOW  and V HIGH . This unknown state typically occurs only during transitions of the signal from either the “0” state to the “1” state or vice versa. 
     At the integrated circuit level, a signal trace takes on the characteristics of a transmission line. Because the transmission signal is actually analog, the transition between digital states does not occur instantaneously, but instead occurs over a period of time T TRANSITION  that is dependent on the physical conditions present on the transmission line. It is well known that signal transitions over a transmission line will suffer a delay known as a propagation delay due to the parasitic resistance, inductance, and capacitance of the line. This delay increases with the length of the line. In addition, it is also well-known that unless the impedance of the transmission line matches that of the load it drives, the signal will degrade. Signal degradation of this type occurs because the mismatch in impedance causes reflections from the load that are passed back to the driver circuit. These reflections may then be re-reflected by the driver circuit, causing further signal degradation. 
     It is also known that when a driver circuit drives multiple loads with differing impedances, the transmission line requires multiple stubs to properly match each of the loads during realtime operation. However, the use of multiple stubs then generates multiple reflections. 
     One way of ensuring proper detection of signal states is to slow the slew rates of the signal. The slew rate is the slope at which the signal edges transition between non-floating states. 
     SUMMARY OF THE INVENTION 
     The present invention is a novel method and circuit for controlling the slope of a transitioning signal on a node of integrated circuit using stepwise impedance reduction/augmentation. The invention allows precise control over the slew rate of the signal, which thereby allows matching of the transition times on both the rising and falling edges of the signal. In accordance with the method of the invention, an open drain node displaying transmission line characteristics is pulled from a first state to a second state over a plurality of sequentially ordered steps. At each step, a predetermined decreasing (or increasing) impedance is connected between the node and a voltage source representing the second state. Preferably, the order of the predetermined impedances decrease (or increase) non-linearly such that said signal transition seen on the node results in a linear slew rate. When the output signal is to transition from the high state to the low state, the pulldown driver decreases the impedance between the node and voltage source in an ordered stepwise manner. When the output signal is to transition from the low state to the high state, the pulldown driver increases the impedance between the node and low voltage source in reverse order stepwise manner. 
     In accordance with one embodiment of the invention, a plurality of serially connected variable delay units generates a plurality of delayed versions of the data signal to be driven onto the transmission line. When the output signal is to be pulled to a given state, a predriver circuit programs a variable impedance network to connect a different one of a plurality of predetermined impedances in ascending or descending order between the node and a voltage source once for each delayed version of transitioned data signal. The shape of the transition edges may be precisely shaped through a combination of the selection of the number of steps, impedance values for each step, and time delay between each step. In one embodiment, the values of the predetermined impedances in order of their connection between the node and voltage source is non-linear to result in a linear slew rate of a resulting output signal on the node. 
     Preferably, the delay time between each step is equal so as to allow the slew rate to be adjusted without affecting the linearity of the slew rate. This also allows slew rate adjustment by a PVT control circuit to account for process, voltage, and temperature variations in the components of the integrated circuit. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING 
     The invention will be better understood from a reading of the following detailed description taken in conjunction with the drawing in which like reference designators are used to designate like elements, and in which: 
     FIG. 1 is a schematic block diagram of an open-drain transmission line implemented in accordance with the invention; 
     FIG. 2 is a block diagram of a conventional open-drain transmission line; 
     FIG. 3 is a schematic diagram of a slew rate control circuit implemented in accordance with the invention; 
     FIG. 4 is a timing diagram illustrating the slew rate control of a data signal using the slew rate control circuit of FIG. 3; 
     FIG. 5 is a schematic diagram of a pre-driver circuit used for the predrive units in the slew rate control circuit of FIG. 3; 
     FIG. 6 is a timing diagram illustrating the relationships between the data signal, predrive signals, and output signal; and 
     FIG. 7 is an operational flowchart of the method of the invention. 
    
    
     DETAILED DESCRIPTION 
     A novel method and system for controlling the slew rate of a signal on a node of an integrated circuit is described in detail hereinafter. Although the invention is described in terms of specific illustrative embodiments, it is to be understood that the illustrative embodiments are shown by way of example only and that the scope of the invention is not intended to be limited thereby. For example, although the illustrative embodiment uses a plurality of CMOS field effect transistors (FETs) to implement the resistive devices switchably connectable to the output node, these devices may be implemented using various other known alternatives. 
     Turning now to FIG. 1, there is shown a block diagram illustrating a conventional open-drain transmission line  2 . As known in the art, an open-collector transmission line is terminated on both the driver end  3  and receiver end  4  with respective pull-up resistors  5  and  6 . More specifically, pull-up resistor  5  is connected at driver end  3  between the transmission line  2  and a HIGH voltage source V DD , while pull-up resistor  6  is connected at receiver end  4  between the transmission line  2  and a HIGH voltage source V DD . In an open-drain transmission line, the pull-up resistors  5  and  6  operate to maintain the transmission line  2  in a HIGH state unless actively pulled to a LOW state. This is achieved using a transistor device, such as n-channel MOSFET (hereinafter NFET)  7 . In particular, the source of NFET  7  is connected to a LOW voltage source (such as ground) and the drain of NFET  7  is connected to the transmission line  2 . The NFET  7  is switched on or off via a DATA signal connected to the gate of NFET  7  to respectively sink current from the line  2  (thereby pulling transmission line  2  to a LOW state) or to isolate the transmission line  2  from the LOW voltage source (thereby allowing the pull-up resistors  5  and  6  to pull the transmission line  2  to a HIGH state). 
     FIG. 2 is a block diagram illustrating a driving end  13  of an open-drain transmission line  20  driven by a driver circuit  10  implemented in accordance with the invention. (For simplicity, the receiving end of the transmission line  20  is not shown.) In particular, the driver circuit  10  allows slew rate control of a signal DATA driven onto the transmission line  20  using stepwise pull-down impedance reduction/augmentation. In particular, if the signal DATA is transitioning from a HIGH state to a LOW state, the pull-down impedance, implemented by variable impedance network  16 , is gradually decreased over a plurality of delayed steps. In contrast, if the signal DATA is transitioning from a LOW state to a HIGH state, the pull-down impedance is gradually increased over a plurality of delayed steps. 
     As illustrated, in the preferred embodiment the driver circuit  10  includes a delay generator circuit  12 , a predriver circuit  14 , and a variable impedance network  16  that may be programmed to switchably connect various pull-down impedances between the transmission line  20  and a LOW voltage source. Delay generator  12  receives a signal DATA to be driven onto the transmission line  20  and produces a plurality of successive delayed versions of the signal DATA. Predriver circuit  14  implements a state machine that receives the signal DATA along with the plurality of successive delayed versions of the signal DATA, and selectively programs the variable impedance network  16  to decrease or increase the pull-down impedance in a stepwise manner depending on whether the signal DATA is transitioning from a HIGH state to a LOW state or from a LOW state to a HIGH state. 
     To more particularly describe the structure and operation of the driver circuit  10 , reference is now made to FIG. 3, which illustrates this circuitry in more detail. Specifically, variable impedance network  16  comprises a plurality of resistive devices  131 ,  132 ,  133 ,  134 , each switchably connectable between the driven end  13  of the transmission line  20  and a LOW voltage source V SS  (e.g., ground). In the preferred embodiment, the resistive devices  131 ,  132 ,  133 ,  134  are implemented using n-channel FETs N 1 , N 2 , N 3 , N 4 , each having a source connected to the LOW voltage source V SS  and a drain connected to the transmission line  20 , and each separately controllable at a gate input to electrically connect the transmission line  20  to the LOW voltage source V SS  or to isolate the transmission line  20  from the LOW voltage source V SS . 
     Delay generator  12  comprises a plurality of serially connected delay units  111 ,  112 ,  113 ,  114 . Each delay unit  111 ,  112 ,  113 ,  114  outputs a respective delayed version DATA(t- 1 ), DATA(t- 2 ), DATA(t- 3 ), DATA(t- 4 ) of its input. Delay unit  111  is connected to receive the signal DATA(t) to be driven onto the transmission line  20 . Each successive delay unit  112 ,  113 ,  114  in the series of delay units is connected to receive the output of its immediate predecessor delay unit in the series. Thus, delay unit  112  is connected to receive the output DATA(t- 1 ) of delay unit  111  (i.e., the delayed version of signal DATA(t), delay unit  113  is connected to receive the output DATA(t- 2 ) of delay unit  112 , and so on. In the present example, then, the last delay unit  114  is connected to receive the delayed output of its immediate predecessor delay unit  113 . 
     Predriver circuit  14  is a state machine that receives the current state of the signal DATA(t) and the outputs DATA(t- 1 ), DATA(t- 2 ), DATA(t- 3 ), DATA(t- 4 ) of each delay unit. Depending on the direction of the signal transition, predriver circuit  14  controls the variable impedance network  16  to electrically connect or isolate different combinations of the resistive devices  131 ,  132 ,  133 ,  134 . More specifically, depending on the direction of signal transition, predriver circuit  14  programs the variable impedance network  16  to decrement or increment the pull-down impedance in a stepwise manner in order to control the slew rate of the signal OUT driven onto the transmission line  20 . 
     In the preferred embodiment, predriver circuit  14  comprises a plurality of individual predrive units  121 ,  122 ,  123 ,  124  each for controlling the electrical connection or isolation of a different respective resistive device  131 ,  132 ,  133 ,  134  in the variable impedance network  16 . In the preferred embodiment, when signal DATA transitions from a HIGH state to a LOW state, each predrive unit  121 ,  122 ,  123 ,  124  turns on its corresponding NFET N 1 , N 2 , N 3 , N 4  one after another in delayed succession. Once an NFET has been switched on, it remains on until turned off in reverse succession by its respective predrive unit when the signal DATA transitions from a LOW state to a HIGH state. 
     In particular, the transmission line  20  is electrically connected to or isolated from the LOW voltage source V SS  according to a plurality of delayed decremental or incremental pull-down impedance steps. This is achieved by selectively electrically connecting/disconnecting different combinations of the resistive devices  131 ,  132 ,  133 ,  134  in an ordered manner to achieve a desired shape of the transition edge of the driven signal. 
     The slew rate and shape of the signal OUT driven onto the transmission line  20  is determined by a number of design factors, including the number of delayed steps, the amount of pulldown resistance increased or decreased at each step, and the amount of delay ΔT between each step. In design, the number of steps chosen and signal frequency will typically dictate the amount of delay between each step, particularly if it is desired to have a constant delay time ΔT between each step. The desired shape of the signal&#39;s transition edges will then dictate the amount of pulldown resistance required at each step, according to the following calculations: 
     The voltage V TL  on transmission line  20  may be defined as: 
     
       
           V   TL   =VDD *( R   pulldown   /R   pulldown   +R ). 
       
     
     Upon selection of the number of steps, delay time ΔT between each step, and signal transition edge shape chosen, the desired transmission line voltage values V TL  may then be determined for each step. Those skilled in the art will appreciate that more control over the signal shape is achieved using more steps. 
     Referring to FIG. 4 as an illustrative example, suppose that the designer desires to achieve a signal shaped as shown by signal OUT. As illustrated, in this example, the desired shape of the rising and falling signal transition edges of the signal OUT are linear with respect to time (i.e., the slew rate is constant) and the slew rate control is to be achieved over four steps. Suppose further that, for simplicity of design, a constant delay ΔT between each step is selected for each delay time ΔT 1 , ΔT 2 , ΔT 3 , ΔT 4 . With these selections made, the desired transmission line voltage values V TL     —     1 , V TL     —     2 , V TL     —     3 , and V TL     —     4  may then be determined. In this case, in order to achieve the desired linear slope on the signal transitions, the transmission line voltage values V TL     —     1 , V TL     —     2 , V TL     —     3 , and V TL     —     4  are also selected linearly spaced. Accordingly, if, for example, V DD  has a value of 1.0 Volts and V SS  has a value of 0 Volts, the desired values of the transmission line voltage over four steps is as follows: V TL     —     1  will be 0.8 Volts, V TL     —     2  will be 0.6 Volts, V TL     —     3  will be 0.4 Volts, and V TL     —     4  will be 0.2 Volts. 
     With the selected transmission line voltage values V TL     —     1 , V TL     —     2 , V TL     —     3 , and V TL     —     4 , the pulldown resistance required for each step may be determined. In particular, the voltage V TL  on transmission line  20  may be defined as: 
     
       
           V   TL   =V   DD *( R   pulldown   /R   pulldown   +R ). 
       
     
     From this equation, the combined resistance of each combination of pulldown resistive devices may be calculated as follows: 
     
       
           R   pulldown     —     n =( R*V   TL     —     n )/( V   DD   −V   TL     —     n ). 
       
     
     TABLE 1 illustrates the calculated values for R pulldown     —     n  for V DD =1.0 Volts, and R pullup =50 Ohms. 
     
       
         
           
               
               
               
               
               
             
               
                   
                 TABLE 1 
               
               
                   
                   
               
               
                   
                 V TL     —     n   
                 Volts 
                 R pulldown     —     n   
                 Ohms 
               
               
                   
                   
               
             
            
               
                   
               
            
           
           
               
               
               
               
               
            
               
                   
                 V TL     —     1   
                 0.8 
                 R pulldown     —     1   
                 200 
               
               
                   
                 V TL     —     2   
                 0.6 
                 R pulldown     —     2   
                 75 
               
               
                   
                 V TL     —     3   
                 0.4 
                 R pulldown     —     3   
                 33 
               
               
                   
                 V TL     —     4   
                 0.2 
                 R pulldown     —     4   
                 12.5 
               
               
                   
                   
               
            
           
         
       
     
     In the embodiment of FIG. 3, resistive devices  131 ,  132 ,  133 ,  134  are implemented with n-channel FETs N 1 , N 2 , N 3 , and N 4 . In this embodiment, the first FET N 1  in the series of FETs N 1 , N 2 , N 3 , and N 4  is turned on with the first step. Once a FET is turned on, it remains on until turned off when the signal transitions to the opposite state, and vice versa. Accordingly, at the second step, FET N 1  remains on, and the next FET N 2  in the series of FETS N 1 , N 2 , N 3 , and N 4  is turned on. At the third step, FETs N 1  and N 2  remain on, and the next FET N 3  in the series is turned on. At the fourth step, FETs N 1 , N 2 , and N 3  remain on, and the next FET N 4  in the series is turned on. 
     In this design, the pull-down resistance for each of the four steps may be derived as follows: 
     Since the admittance Y is defined as Y=1/R, then it follows that: 
     
       
         Y pulldn     —     1 =Y N1   
       
     
     
       
         
           Y 
           pulldn 
           
             — 
           
           2 
           =Y 
           N1 
           +Y 
           N2 
         
       
     
     
       
         
           Y 
           pulldn 
           
             — 
           
           3 
           =Y 
           N1 
           +Y 
           N2 
           +Y 
           N3 
         
       
     
     
       
           Y   pulldn     —     4   =Y   N1   +Y   N2   +Y   N3   +Y   N4 . 
       
     
     The admittance value Y N  of each FET N 1 , N 2 , N 3 , N 4  of FIG. 3 may be derived from the above equations as: 
     
       
         Y N1 =Y pulldn     —     1   
       
     
     
       
         
           Y 
           N2 
           =Y 
           pulldn 
           
             — 
           
           2 
           −Y 
           pulldn 
           
             — 
           
           1 
         
       
     
     
       
         
           Y 
           N3 
           =Y 
           pulldn 
           
             — 
           
           3 
           −Y 
           pulldn 
           
             — 
           
           2 
         
       
     
     
       
           Y   N4   =Y   pulldn     —     4   −Y   pulldn     —     3 , 
       
     
     and therefore: 
     
       
           R   N1 =1 /Y   N1 , 
       
     
     
       
           R   N2 =1 /Y   N2 , 
       
     
     
       
           R   N3 =1 /Y   N3 , 
       
     
     and 
     
       
           R   N4 =1 /Y   N4 . 
       
     
     Accordingly, using the values from TABLE 1, in this example: 
     
       
         R N1 =200 Ohms, 
       
     
     
       
         R N2 =120 Ohms, 
       
     
      R N3 =60 Ohms, 
     and 
     
       
         R N4 =20 Ohms. 
       
     
     It will be appreciated by those skilled in the art that the shape of the signal OUT driven onto transmission line  20  may be controlled by varying the number of steps, the delay amount between each step, and the pulldown impedance defined for each step. 
     As previously described, each of the resistive devices  131 ,  132 ,  133 ,  134  in the variable impedance network  16  is separately controllable to electrically connect, or to electrically isolate, the transmission line  20  to or from the LOW voltage source. Predriver circuit  14  controls the connection or isolation of each resistive device  131 ,  132 ,  133 ,  134  to or from the transmission line  20 . 
     FIG. 5 is a schematic diagram of an example implementation of an individual predrive unit  50  used to implement predrive units  121 ,  122 ,  123 , and  124  of FIG.  3 . As illustrated, predrive unit  50  comprises a CMOS inverter  52  having an input  58  connected to receive the signal DATA to be driven onto the transmission line  20 , and an output  59  connected to control the connection or non-connection of the resistive device  131 ,  132 ,  133 , or  134  associated with the particular predrive unit  50 . The CMOS inverter  52  comprises a p-channel MOSFET  51  (hereinafter PFET) having a drain connected to the transmission line  20  and a source switchably connected to a HIGH voltage source V DD  through a switch PFET  54 , and an NFET  53  having a drain connected to the transmission line  20  and a source switchably connected to a LOW voltage source V SS  through a switch NFET  56 . Each of the drains of inverter PFET  51  and inverter NFET  53  is connected to receive the signal DATA. 
     The switch PFET  54  has a drain connected to the source of inverter PFET  51  and a source connected to the HIGH voltage source V DD . Switch PFET  54  has a gate connected to receive an ON input, which as discussed hereinafter is one of the delayed versions of the signal DATA. The switch NFET  56  has a drain connected to the source of inverter NFET  53  and a source connected to the LOW voltage source V SS . Switch NFET  56  has a gate connected to receive an OFF input, which as also discussed hereinafter is a different one of the delayed versions of the signal DATA. TABLE 2 is a state table illustrating the logic operation of the predrive unit  50 . 
     
       
         
           
               
               
               
               
               
             
               
                 TABLE 2 
               
               
                   
               
               
                 DATA 
                 OFF 
                 ON 
                 PREVIOUS OUTPUT 
                 OUTPUT 
               
               
                   
               
             
            
               
                 Case 1: 
                   
                   
                   
                   
               
               
                 1 
                 1 
                 1 
                 X 
                 0 
               
               
                 0 
                 1 
                 1 
                 0 
                 0 
               
               
                 0 
                 0 
                 1 
                 0 
                 0 
               
               
                 0 
                 0 
                 0 
                 0 
                 1 
               
               
                 1 
                 0 
                 0 
                 1 
                 1 
               
               
                 1 
                 1 
                 0 
                 1 
                 0 
               
               
                 1 
                 1 
                 1 
                 0 
                 0 
               
               
                 Case 2: 
               
               
                 1 
                 1 
                 1 
                 X 
                 0 
               
               
                 0 
                 1 
                 1 
                 0 
                 0 
               
               
                 0 
                 1 
                 0 
                 0 
                 1 
               
               
                 0 
                 0 
                 0 
                 1 
                 1 
               
               
                 1 
                 0 
                 0 
                 1 
                 1 
               
               
                 1 
                 0 
                 1 
                 1 
                 1 
               
               
                 1 
                 1 
                 1 
                 1 
                 0 
               
               
                   
               
            
           
         
       
     
     Predrive unit  50  also may include an optional weak holder circuit  60 , comprising back-to-back inverters, connected to the predrive unit output  59 , which holds the state on the predrive unit output  59  to prevent the output  59  from floating to an intermediate voltage when the predrive unit  50  is not actively driven to output one voltage state or another. 
     Referring again to FIG. 3, with the resistance values of FETS N 1 , N 2 , N 3 , and N 4  defined as above, the predrive units  121 ,  122 ,  123 , and  124  are connected in a manner such that when the signal DATA transitions from a HIGH state to a LOW state, the FETS N 1 , N 2 , N 3 , and N 4  are turned on (to conduct current between the transmission line  20  and LOW voltage source V SS ) in the following order: Step 1-N 1  turns on; Step 2-N 1  remains on and N 2  turns on; Step 3-N 1  and N 2  remain on and N 3  turns on; Step 4-N 1 , N 2 , N 3  remain on and N 4  turns on. 
     Similarly, the predrive units  121 ,  122 ,  123 , and  124  are also connected in a manner such that when the signal DATA transitions from a LOW state to a HIGH state, the FETS N 1 , N 2 , N 3 , and N 4  are turned off (to isolate the transmission line  20  from the LOW voltage source V SS ) in the following order: Step 1-N 4  turns off while N 1 , N 2 , N 3  remain on; Step 2 N 3  turns off while N 1  and N 2  remains on; Step 3-N 2  turns off while N 1  remains on; Step 4-N 1  turns off. 
     In order to achieve the above ordered turning on and turning off of the NFETs N 1 , N 2 , N 3 , N 4 , the output of first delay unit  111  in the series of delay units is connected to the ON input of first predrive unit  121  that drives the highest impedance FET N 1 , and the output of last delay unit  114  in the series of delay units is connected to the OFF input of predrive unit  121 . The output of the next delay unit  112  in the series is connected to the ON input of the next predrive unit  122  that drives the next highest impedance FET N 2 , and the output of the next-to-last delay unit  113  in the series is connected to the OFF input of the predrive unit  122 . The output of the next delay unit  113  in the series is connected to the ON input of the next predrive unit  123  in the series that drives the next highest impedance FET N 3 , and the output of the delay unit  112  in the series is connected to the OFF input of the predrive unit  123 . The output of the last delay unit  114  in the series is connected to the ON input of the last predrive unit  124  that drives the lowest impedance FET N 4 , and the output of the delay unit  111  in the series is connected to the OFF input of the predrive unit  124 . 
     Referring now to the timing diagram shown in FIG. 6, in conjunction with the preferred embodiment driver circuit of FIG. 3, in operation, assuming all of the FETs N 1 , N 2 , N 3 , N 4  begin in the off state and the signal DATA is in the HIGH state, the signal OUT on the transmission line  20  is pulled to a HIGH state by pullup resistor  15 . When the signal DATA transitions from the HIGH state to the LOW state, after a delay time ΔT 1 , the negative true ON input of predrive unit  121  will go LOW, thereby enabling the switch PFET  51  (see FIG. 5) of the predrive unit  121  to connect the source of inverter PFET  51  to the HIGH voltage source V DD . This drives the PREDRIVE signal of the predrive unit  121  (PREDRIVE 1 ) to the HIGH state, thereby turning on FET N 1 . Meanwhile, as shown in FIG. 6, predrive signals PREDRIVE 2 , PREDRIVE 3 , and PREDRIVE 4  remain in the LOW state, and therefore FETs N 2 , N 3 , and N 4  remain off. 
     After the passage of another delay time ΔT 2 , the LOW state of the signal DATA propagates through the second delay unit  112 , and the negative true ON input of predrive unit  122  will go LOW. This will cause the PREDRIVE signal of the predrive unit  122  (PREDRIVE 2 ) to go to the HIGH state, thereby turning on FET N 2 . Meanwhile, as shown in FIG. 6, predrive signals PREDRIVE 3  and PREDRIVE 4  remain in the LOW state, and therefore FETs N 3 , and N 4  remain off. 
     After the passage of a further delay time ΔT 3 , the LOW state of the signal DATA propagates through the third delay unit  113 , and the negative true ON input of predrive unit  123  will go LOW. This will cause the PREDRIVE signal of the predrive unit  123  (PREDRIVE 3 ) to go to the HIGH state, thereby turning on FET N 3 . Meanwhile, as shown in FIG. 6, predrive signal PREDRIVE 4  remains in the LOW state, and therefore FET N 4  remains off. 
     After the passage of yet a further delay time ΔT 4 , the LOW state of the signal DATA propagates through the fourth delay unit  114 , and the negative true ON input of predrive unit  124  will go LOW, causing the PREDRIVE signal of predrive unit  124  (PREDRIVE 4 ) to go to the HIGH state, turning on FET N 4 . 
     All four FETs N 1 , N 2 , N 3 , N 4  remain on until the signal DATA makes a transition from the LOW state to the HIGH state. When this happens, after a delay time ΔT 4 , the OFF input of predrive unit  124  will go HIGH, thereby enabling the switch NFET  53  (see FIG. 5) of predrive unit  124  to connect the source of inverter NFET  53  to the LOW voltage source V SS . This drives the PREDRIVE 4  signal of predrive unit  124  to the LOW state, thereby turning off FET N 4 . Meanwhile, as shown in FIG. 6, predrive signals PREDRIVE 3 , PREDRIVE 2 , and PREDRIVE 1  remain in the HIGH state, and therefore FETs N 3 , N 2 , and N 1  remain on. 
     After the passage of another delay time ΔT 3 , the HIGH state of the signal DATA propagates through the second delay unit  112 , and the OFF input of predrive unit  123  will go HIGH. This will cause the PREDRIVE 3  signal of predrive unit  123  to go to the LOW state, thereby turning off FET N 3 . Meanwhile, as shown in FIG. 6, predrive signals PREDRIVE 2  and PREDRIVE 1  remain in the HIGH state, and therefore FETs N 2 , and N 1  remain on. 
     After the passage of a further delay time ΔT 2 , the HIGH state of the signal DATA propagates through the third delay unit  113 , and the OFF input of predrive unit  122  will go HIGH. This will cause the PREDRIVE 2  signal of predrive unit  122  to go to the LOW state, thereby turning off FET N 2 . Meanwhile, as shown in FIG. 6, predrive signal PREDRIVE 1  remains in the HIGH state, and therefore FET N 1 s remain on. 
     After the passage of yet a further delay time ΔT 1 , the HIGH state of the signal DATA propagates through the fourth delay unit  114 , and the OFF input of predrive unit  121  will go HIGH. This will cause the PREDRIVE 1  signal of predrive unit  121  to go to the LOW state, thereby turning off FET N 1 . 
     It will be appreciated that the shape of the edge transitions of the output signal OUT may be precisely controlled by selecting an appropriate number of steps and setting appropriate values for each of the pulldown impedance and time delay ΔT 1 , ΔT 2 , ΔT 3 , ΔT 4  associated with each step. Thus, if it were desirable to have a non-linear edge transition, the designer could vary the time delay ΔT 1 , ΔT 2 , ΔT 3 , ΔT 4  between each step and/or the pulldown impedance connected at each step. 
     It will also be appreciated that the use of a constant time delay ΔT between each pulldown impedance change step allows one to change the slew rate of the driven signal DATA merely by changing the value of the constant ΔT. By using a variable delay unit whose delay time ΔT is programmable, the delay units  111 ,  112 ,  113 ,  114  can be programmed by a PVT control circuit  110  to adjust the delay to the PVT parameters of the circuit. This feature allows precise slew rate control across circuits that may vary in performance due to differences in PVT parameters. Depending on the implementation of the delay unit, the PVT control circuit  110  may comprise a circuit as simple as a variable resistor or more complicated circuitry that generates a programmed delay value input to the delay unit. 
     FIG. 7 is a flowchart of the operation of the method of the invention. For an open-drain bus, the transmission line is normally pulled high by the pullup resistor unless actively pulled low using a switchable pulldown impedance device. Accordingly, the method begins assuming the transmission line is in a HIGH state. The method also assumes a series of predetermined pulldown impedance values and delay times associated with each step, whose values may optionally be adjusted (step  220  and step  222 ) to achieve a desired slew rate on the transmission line. 
     Upon detection of a transition of the data signal from the HIGH state to the LOW state (step  201 ), a first predetermined pulldown impedance associated with a first step in an ordered sequence of steps is connected (step  202 ) between the transmission line and the LOW voltage source. After delaying (step  203 ) a first delay time associated with the first step in the ordered sequence of steps, a determination is made (step  204 ) as to whether or not more steps exist in the ordered sequence of steps. If another step exists, a next predetermined pulldown impedance associated with a next step in the ordered sequence of steps is connected (step  205 ) between the transmission line and LOW voltage source. A next delay time associated with the next step then passes (step  206 ). Steps  204  through  206  are then repeated until no more steps in the ordered sequence of steps exist. At this point, the method is complete until detection of a transition of the data signal from the LOW state to the HIGH state (step  207 ). 
     Upon detection of a transition of the data signal from the LOW state to the HIGH state (step  207 ), a last predetermined pulldown impedance associated with the last step in the ordered sequence of steps is disconnected (step  208 ) from the transmission line. After delaying (step  209 ) a delay time associated with the last step in the ordered sequence of steps, a determination is made (step  210 ) as to whether or not more previous steps exist in the ordered sequence of steps. If a previous step exists, a next predetermined pulldown impedance associated with the previous step in the ordered sequence of steps is connected (step  211 ) between the transmission line and LOW voltage source. A next delay time associated with the previous step then passes (step  212 ). Steps  210  through  212  are then repeated until no more previous steps in the ordered sequence of steps exist. At this point, the method is complete until detection of a transition of the data signal from the HIGH state to the LOW state (step  201 ), where steps  202  through  206  are then repeated in the manner described previously. 
     The preferred embodiment of the invention has been described in terms of an open-drain bus which is normally in a HIGH state unless actively pulled to a LOW state using a variable pulldown impedance network. It will be appreciated that the principles of the invention may be applied similarly to a bus which is normally in a LOW state unless actively pulled to a HIGH state using a variable pullup impedance network. In this embodiment, the method would perform a stepwise decrease in pullup impedance as the signal transitions from the LOW state to the HIGH state, and a stepwise increase in pullup impedance as the signal transitions from the HIGH state to the LOW state. 
     The method may also be applied to a transmission line having separate pullup and pulldown drivers. 
     It will be appreciated that the invention allows precise control of the slew rate and shape of a transitioning signal on an integrated circuit transmission lien. By choosing the number of steps and selecting appropriate values for the impedance connected/disconnected to the transmission line at each step and the delay time between each step, the shape of the edges of the signal may be essentially “sculpted” by the designer. In addition, when the same delay time is selected between each step, the slew rate can be adjusted to compensate for process, voltage, and temperature variation across different integrated circuits simply by varying the delay time. 
     Although the invention has been described in terms of the illustrative embodiments, it will be appreciated by those skilled in the art that various changes and modifications may be made to the illustrative embodiments without departing from the spirit or scope of the invention. It is intended that the scope of the invention not be limited in any way to the illustrative embodiment shown and described but that the invention be limited only by the claims appended hereto.