Patent Publication Number: US-9413350-B1

Title: Switching circuit for power consumption reduction

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application claims priority to Taiwanese Patent Application No. 104103632 filed on Feb. 3, 2015, the contents of which are incorporated by reference herein. 
     FIELD 
     The subject matter herein generally relates to a switching circuit which can be used in electronic devices for power consumption reduction. 
     BACKGROUND 
     Switching circuits are widely used in electronic devices. In general, a many of switching circuits employ transistors such as meta oxide semiconductor field effect transistors (MOSFET) to function as switches. When the switching circuits are powered on, the transistors may have power consumption more or less. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Implementations of the present technology will now be described, by way of example only, with reference to the attached figures. 
         FIG. 1  is a circuit diagram of a switching circuit of the present disclosure according to a first embodiment. 
         FIG. 2  is a sequence diagram of the switching circuit of  FIG. 1 . 
         FIG. 3  is a circuit diagram of a switching circuit of the present disclosure according to a second embodiment. 
     
    
    
     DETAILED DESCRIPTION 
     It will be appreciated that for simplicity and clarity of illustration, where appropriate, reference numerals have been repeated among the different figures to indicate corresponding or analogous elements. In addition, numerous specific details are set forth in order to provide a thorough understanding of the embodiments described herein. However, it will be understood by those of ordinary skill in the art that the embodiments described herein can be practiced without these specific details. In other instances, methods, procedures, and components have not been described in detail so as not to obscure the related relevant feature being described. The drawings are not necessarily to scale and the proportions of certain parts may be exaggerated to better illustrate details and features. The description is not to be considered as limiting the scope of the embodiments described herein. 
     The term “coupled” is defined as connected, whether directly or indirectly through intervening components, and is not necessarily limited to physical connections. The connection can be such that the objects are permanently connected or releasably connected. The term “comprising”, when utilized, means “including, but not necessarily limited to”; it specifically indicates open-ended inclusion or membership in the so-described combination, group, series and the like. 
     The present disclosure is described in relation to a switching circuit which can be used in electronic devices for power consumption reduction. 
       FIG. 1  is a circuit diagram of a switching circuit  100  of the present disclosure according to a first embodiment. The switching circuit  100  can include a first switch P 1  and a second switch N 1 . In this embodiment, when one of the first switch P 1  and the second switch N 1  is turned on, another thereof is turned off. The first switch P 1  can include a first gate Gp, a first source Sp, and a first drain Dp. A first gate-to-source capacitor P_Cgs is electrically coupled between the first gate Gp and the first source Sp. The second switch N 1  can include a second gate Gn, a second source Sn, and a second drain Dn. A second gate-to-source capacitor N_Cgs is electrically coupled between the second gate Gn and the second source Sn. The first gate-to-source capacitor P_Cgs is a capacitor formed between the first gate Gp and the first source Sp. The second gate-to-source capacitor N_Cgs is a capacitor formed between the second gate Gn and the second source Sn. In at least one embodiment, the first switch P 1  is a P type metal oxide semiconductor field effect transistor (P-MOS), and the second switch N 1  is an N type metal oxide semiconductor field effect transistor (N-MOS). 
     The first gate Gp is electrically connected to a reservoir capacitor Cz via a first pre-driver  11 . The second gate Gn is electrically connected to the reservoir capacitor Cz. The first pre-driver  11  is electrically coupled between the first switch P 1  and the reservoir capacitor Cz. The second pre-driver  12  is electrically coupled between the second switch N 1  and the reservoir capacitor Cz. Both the first pre-driver  11  and the second pre-drive  12  are electrically connected to a same end of the reservoir capacitor Cz. In at least one embodiment, each of the first pre-driver  11  and the second pre-driver  12  can be an integrated circuit (IC) for driving the first switch P 1  and the second switch N 1 , respectively. For example, the first pre-driver  11  and the second pre-driver  12  can be one of a family of FLEXMOS™ automotive grade products for driving logic-level MOSFETs. In other embodiments, the each of the first pre-driver  11  and the second pre-driver  12  can be a buffer circuit including a plurality of inverters connected in serial. 
     The first source Sp is electrically coupled to a power voltage source Vcc. The first drain Dp is electrically coupled to the second source Sn. The second drain Dn is grounded. An output port LX is coupled to both the first drain Dp and the second source Sn. When the first switch P is turned on, the first gate-to-source capacitor P_Cgs is charged by the power voltage source Vcc and accumulates charges therein. When the first switch P 1  is turned off, the first gate-to-source capacitor P_Cgs discharges and the charges stored in the first gate-to-source capacitor P_Cgs flow into the reservoir capacitor Cz via the first pre-driver  11 . Thus, the reservoir capacitor Cz is charged by the charges from the first gate-to-source capacitor P_Cgs and accumulates charges therein. Then, when the second switch N 1  is being turned on, the reservoir capacitor Cz discharges and the charges stored in the reservoir capacitor Cz flow into the second gate-to-source capacitor N_Cgs to charge the second gate-to-source capacitor N_Cgs. In at least one embodiment, the first pre-driver  11  includes a first control terminal P_IN, a power terminal Vc, a current source terminal Vs, and a first output terminal Po. The first control terminal P_IN is configured to receive an external control signal which is configured to control the first switch P 1 . For example, the external control signal can turn on or turn off the first switch P 1 . The power terminal Vc is electrically coupled to the power voltage source Vcc. The first output terminal Po is electrically coupled to the first gate Gp of the first switch P 1 , to transmit the external control signal to the first gate Gp to turn on or turn off the first switch P 1 . 
     Further, the switching circuit  100  can further include a current source Is. In order to prevent reverse current, the first pre-driver  11  and the current source Is are interconnected in serial between the first gate Gp and the reservoir capacitor Cz. The current source Is includes a first end electrically coupled to the current source terminal Vs of the first pre-driver  11  and a second end electrically coupled to the reservoir capacitor Cz. In addition, the first end is electrically coupled to the power voltage source Vcc via a first diode D 1 , and the second end is electrically coupled to a second diode D 2  which is grounded. Each of the first diode D 1  and the second diode D 2  can be a Zener diode having a reverse breakdown voltage (e.g., 5V). The first diode D 1  includes an anode coupled to the power voltage source Vcc and a cathode coupled to the first end of the current source Is. The second diode D 2  includes an anode coupled to the second end of the current source Is and a cathode which is grounded, to protect the second pre-driver  12 . For example, when a voltage output from the current Is is greater than a threshold voltage (e.g., 5V), the second diode D 2  is reverse breakdown, to ground the current source Is. Thus, the voltage which is greater than the threshold voltage will not be outputted to the second pre-driver  12  and the second pre-driver  12  is thus protected. 
     The second pre-driver  12  includes a second control terminal N_IN, a power terminal Vz, a ground terminal GND, and a second output terminal No. The second control terminal N_IN is configured to receive an external control signal for controlling the second switch N 1 . The power terminal Vz is coupled to both the reservoir capacitor Cz and the current source Is. The second output terminal No is electrically coupled to the second gate Gn of the second switch N 1  to transmit the external control signal to the second switch N 1  to turn on or turn off the second switch N 1 . 
     In use, as shown in  FIG. 2 , a curve LX represents a waveform of output signals from the output port LX coupled to the first drain Dp and the second source Sn. A curve P Gate  represents a waveform of a first control signal for controlling the first switch P 1 . A curve N Gate  represents a waveform of a second control signal for controlling the second switch N 1 . A curve I p   _   Cgs  represents a waveform of charges stored in the first gate-to-source capacitor P_Cgs. A curve I N   _   Cgs  represents a waveform of charges stored in the second gate-to-source capacitor N_Cgs. 
     At time T 1 , the first control signal P Gate  is raised from a low level to a high level. At this time, the first switch P 1  is turned off, and the first gate-to-source capacitor P_Cgs discharges and the charges stored in the first gate-to-source capacitor P_Cgs flow into the reservoir capacitor Cz to charge the reservoir capacitor Cz. Thus, the charges stored in the first gate-to-source capacitor P_Cgs gradually reduces. Further, since the second control signal maintains at a high level, the second switch N 1  is still in a turned off state, and the output signal of the output port LX is a high level signal. 
     At time T 1 , the second control signal N Gate  is raised from a low level to a high level. At this time, the second switch N 1  is turned on, and the reservoir capacitor Cz discharges and the charges stored in the reservoir capacitor Cz flow into the second gate-to-source capacitor N_Cgs to charge the second gate-to-source capacitor N_Cgs. Thus, the charges stored in the second gate-to-source capacitor N_Cgs gradually increases. Further, since the second switch N 1  is turned on, the output port LX is grounded via the second switch N 1 , and therefore the output signal of the output port LX is dropped to a low level from the high level. 
     At time T 3 , the second control signal N Gate  is dropped from the high level to the low level. At this time, the second switch N 1  is turned on, and the second gate-to-source capacitor N_Cgs is grounded and discharged. Thus, the charges stored in the second gate-to-source capacitor N_Cgs gradually decreases. 
     At time T 5 , the first control signal P Gate  is dropped from the high level to the low level. At this time, the first switch P 1  is turned on, and the first gate-to-source capacitor P_Cgs is charged by the power voltage source Vcc and accumulates charges therein. Thus, the charges stored in the first gate-to-source capacitor P_Cgs gradually increases. Further, since the first switch P 1  is turned on, the output port LX is electrically coupled to the power voltage source Vcc via the first switch P 1 , and therefore the output signal of the output port LX is the high level signal. 
     The principle of the switching circuit  100  during time period T 5  to T 8  is the same to that of T 1 -T 4 . Detailed descriptions thereof are omitted. 
     Further, as shown in  FIG. 2 , in an operation period of the switching circuit  100 , an amount of time when the first switch P 1  is turned off (e.g., T 1 -T 4 ) is greater than an amount of time when the second switch is turned on (e.g., T 2 -T 3 ). Accordingly, an amount of time when the first switch P 1  is turned on (e.g., T 4 -T 5 ) is less than an amount of time when the second switch is turned off (e.g., T 3 -T 6 ). 
       FIG. 3  is a circuit diagram of the switching circuit  100  according to a second embodiment. The second embodiment is similar to the first embodiment, except that the second Diode D 2  is omitted. Further, the power terminal Vz of the second pre-driver  12  is electrically coupled to an external power source Vin. Since the output voltage of the current source Is should be limited to a preset threshold voltage, such as 5V, the second pre-driver  12  can be powered by the external power source Vin when the second pre-driver  12  needs a greater driving voltage. 
     As described above, when the first switch P 1  is turned off, the charges stored in the first gate-to-source capacitor P_Cgs can be used to charge the second gate-to-source capacitor N_Cgs. Thus, the total power consumption of the switching circuit  100  can be reduced. 
     The embodiments shown and described above are only examples. Even though numerous characteristics and advantages of the present technology have been set forth in the foregoing description, together with details of the structure and function of the present disclosure, the disclosure is illustrative only, and changes may be made in the detail, including in matters of shape, size, and arrangement of the parts within the principles of the present disclosure, up to and including the full extent established by the broad general meaning of the terms used in the claims.