Patent Publication Number: US-8115547-B2

Title: Reconfigurable power amplifier and use of such amplifier for making a multi-standard amplification stage for mobile phone communications

Description:
PRIORITY CLAIM 
     This application is a 371 filing of PCT/FR2008/050059 filed Jan. 14, 2008, which claims the benefit of French Application for Patent No. 07-52699 filed Jan. 16, 2007, the disclosures of which are hereby incorporated by reference. 
     TECHNICAL FIELD 
     The invention relates to high-frequency power amplifiers and relates more particularly to reconfigurable power amplifiers. 
     BACKGROUND 
     One particularly advantageous application of high-frequency power amplifiers relates to the design of an amplification stage for mobile telephony handsets and, more particularly, the design of multi-standard reconfigurable power amplifiers, in other words amplifiers that are capable of adapting to the specifications of various telecommunications standards. 
     Thus, for example, such a reconfigurable power amplifier must be capable of operating both according to the UMTS (WCDMA) standards and also to the GSM, DCS or PCS standards. 
     The notion of reconfigurability indicates that these amplifiers must be capable of dynamically modifying their properties according to the standard being used at a given moment in time, but also according to the power level of an incident signal that is applied to it in order for it to work at an optimum power level. 
     Indeed, according to certain standards, in particular the GSM and GSM 1800 (DCS) standards, owing to the type of modulation employed, the power of the signals is relatively high, which implies a particular constraint for RF applications. 
     For this reason, there is a need in the art to provide a power amplifier that is reconfigurable, in particular in terms of power, in order to dynamically respond to the specific constraints that are imposed on it. 
     SUMMARY 
     According to a first aspect, a reconfigurable power amplifier comprises at least one amplification circuit and means for controlling the amplification circuit so as to adapt its operation according to an input signal that is applied to it. 
     According to a general feature of this amplifier, the control means comprise means for modifying the compression point of the amplification circuit and for adapting the gain of the circuit in such a manner as to increase the power added efficiency (PAE) of the circuit for the modified compression point. 
     Thus, the compression point is made to vary in such a manner as to adapt the linearity of the amplifier according to the operating conditions and the PAE is dynamically modified so as to obtain the maximum PAE at the modified compression point. It has indeed been observed that the efficiency of the amplifier is at maximum for the maximum output power, the efficiency being lower for lower levels of output power. 
     Adjusting the maximum PAE to the level of the modified compression point thus allows the efficiency of the amplifier to be improved at lower powers. 
     According to another feature, the control means comprise means for adapting the level of a biasing current applied to the said circuit. 
     Preferably, the power amplifier is a two-stage amplifier and comprises a first amplification stage and a second amplification stage. The control means then comprise first and second control means for respectively adapting the operation of the first and second stages of amplification. 
     Thus, for example, the first control means comprise means for adapting the compression point of the first stage. 
     With regard to the second control means, these advantageously comprise means for adapting the gain of the second stage. 
     According to another feature, the amplifier also comprises means for modifying the amplification class of the said amplification circuit. 
     In one embodiment, these means comprise means for modifying the equivalent impedance of an output network of the circuit. 
     For example, the amplifier thus comprises switching means for selectively connecting a capacitor and an inductor configured in parallel to the output of the circuit. 
     As far as the means for adapting the level of the biasing current are concerned, in one embodiment, these advantageously comprise an assembly of current sources that may be selectively connected in parallel with one another. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Other aims, features and advantages of the invention will become apparent upon reading the following description, presented solely by way of non-limiting example and with reference to the appended drawings, in which: 
         FIG. 1  is a table illustrating the specifications of various telecommunications standards (GSM, DCS and UMTS); 
         FIG. 2  is a schematic circuit diagram illustrating the general structure of a reconfigurable power amplifier; 
         FIG. 3  illustrates the general principle of the dynamic compensation implemented within the amplifier in  FIG. 1 ; 
         FIG. 4  is a schematic circuit diagram illustrating the generation of the biasing current of the amplification circuits of the amplifier in  FIG. 2 ; 
         FIGS. 5 and 6  illustrate the variation of the compression point of the first amplification stage of the amplifier in  FIG. 2 ; and 
         FIGS. 7 and 8  illustrate the variation of the r.m.s. added power of the amplifier in  FIG. 2 . 
     
    
    
     DETAILED DESCRIPTION OF THE DRAWINGS 
     With reference first of all to  FIG. 1 , a reconfigurable power amplifier must satisfy several demands specific to each telecommunications standard according to which it is designed to operate. 
     Indeed, the current standards use modulations of different types which implies differences with regards to the forms of the RF signals carried. 
     By way of an example, the GSM and GSM 1800 (DCS) standards use a modulation of the GMSK (Gaussian Minimum Shift Keying) type, whereas the UMTS standard uses QPSK (Quaternary Phase Shift Keying) modulation. 
     With regard to the UMTS standard, the transmitted signals have a non-constant envelope, which means that the envelope of the RF signal varies as a function of time. However, it must be preserved in order to avoid the information it contains being altered. It is therefore necessary that the RF amplifiers used for the processing of the signals exhibit a good linearity in order to avoid distortion of the envelope occurring during the amplification. However, the demands in terms of output power are less stringent. 
     In contrast, with regard to the GSM and GSM 1800 (DCS) standards, depending on the GMSK modulation used, the envelope is relatively constant so that amplification with a very high linearity is not needed. On the other hand, as the table seen in  FIG. 1  indicates, the output power must be relatively high. In order to reduce the power consumption, which is a relatively stringent criterion for the fabrication of a reconfigurable power amplifier for mobile telephone handsets, the amplifier must have a high enough operational and power efficiency. 
     For this reason, sinusoidal classes of operation are generally used, in particular class A, class B or class AB power amplifiers, in the fabrication of power stages for telecommunications equipment designed to operate according to the UMTS standard, owing to their excellent linearity, whereas class F power amplifiers are more often used in the design of power stages for telecommunications equipment operating according to the GSM, DCS or PCS standards. 
     In  FIG. 2 , a reconfigurable power amplifier is shown that is capable of meeting the specific constraints of each standard and, in particular, of favoring either the linearity criterion or the efficiency criterion, depending on the standard used. 
     As will be detailed in the following part of the description, this high-frequency power amplifier is designed to modify, dynamically, the compression point (CP) of the amplification stage or stages that it comprises and to modify the amplification class of these stages, in order to either improve the linearity of the amplifier or to improve its efficiency. 
     In the exemplary embodiment shown in  FIG. 2 , the amplifier comprises two amplification stages E 1  and E 2 , one forming a driver stage (E 1 ) and the other a power stage (E 2 ). 
     As is conventional, each stage comprises a transistor, Q d  and Q p  respectively. As can be seen, the transistor Q d  of the first stage E 1  is associated with two inductors L 11  and L 12 , one connected to a source of DC voltage V CC  and the other to ground. 
     Similarly, the transistor Q p  is associated with two inductors L 21  and L 22 , one connected to the voltage V CC  and the other to ground. 
     The control electrode of the transistor Q d  of the first stage receives a high-frequency signal RF in  via an input matching network  1 . 
     The common node between the inductor L 11  and the transistor Q d  is connected to the control electrode of the transistor Q p  of the second stage  2  via a conventional inter-stage matching network  2 . 
     The common node between the inductor L 21  and the transistor Q p  supplies an amplified signal S via an output network  3  essentially comprising an RLC network. 
     Furthermore, each stage is equipped with a biasing circuit,  4  and  5  respectively, whose purpose is to bias the transistor Q d  or Q p . 
     The amplifier is completed by a processing unit  6  receiving, at its input, the signal RF in  and driving the biasing circuits  4  and  5  in order to bias the transistors Q d  and Q p  of the amplification stages E 1  and E 2  as a function of the input signal applied to the amplifier. 
     More particularly, the first biasing circuit  4  of the first stage E 1  is designed to generate a biasing current I biasd  intended for the control electrode of the transistor Q d  in order to make its compression point (CP) vary. 
     The second biasing circuit  5  of the second stage E 2  is, for its part, designed to generate a biasing current I biasp  intended for the second transistor Q p . In addition, the processing unit  6  acts on the output network  3  in order to modify the class of operation of the power stage by modifying the equivalent impedance of this output network  3 . 
     Thus, according to the amplifier seen in  FIG. 2 , this essentially amounts to modifying the compression point of the amplifier and the class of operation in order to either improve the linearity, or to improve the power added efficiency (PAE). 
     This operational parameter PAE is actually formed by the ratio between the added power, in other words the linear difference between the output power and the input power, at a desired RF frequency, over the product of the sum of the currents flowing through each stage and the DC voltage V CC . 
     In other words, the PAE is given, for a two-stage amplifier, by the following equation: 
     
       
         
           
             
               
                 
                   
                     P 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     A 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     E 
                   
                   = 
                   
                     
                       
                         P 
                         
                           RF 
                           ⁡ 
                           
                             ( 
                             out 
                             ) 
                           
                         
                       
                       - 
                       
                         P 
                         
                           RF 
                           ⁡ 
                           
                             ( 
                             
                               i 
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               n 
                             
                             ) 
                           
                         
                       
                     
                     
                       
                         ( 
                         
                           
                             I 
                             1 
                           
                           + 
                           
                             I 
                             2 
                           
                         
                         ) 
                       
                       · 
                       
                         V 
                         CC 
                       
                     
                   
                 
               
               
                 
                   ( 
                   1 
                   ) 
                 
               
             
           
         
       
     
     in which:
         P RF(out)  denotes the output power of the amplifier at the RF frequency;   P RF(in)  denotes the power of the input signal RF in ; and   I 1  and I 2  denote the currents flowing through the transistors Q d  and Q p .       

     As previously indicated, sinusoidal class amplifiers, such as A, B, AB and C class amplifiers, exhibit a good linearity but a relatively low efficiency. 
     In contrast, switching transistors, of class D, E and F according to which the transistors operate in switching mode, exhibit a poorer linearity but a higher efficiency. 
     For this reason, in the UMTS standard, a class A amplifier is generally used for the driver stage and a class AB amplifier for the power stage, whereas it is preferable to use a class AB amplifier for the driver stage and a high-efficiency amplifier (class F) for the power stage in the GSM, DCS or PCS standard. 
     In order to be able make the amplifier operate in multi-standard mode, it is desirable to be able to make the class A/class AB configuration switch into class AB/class F. 
     In the following part of the description, it will thus be considered that this essentially means being able to dynamically make the configuration of a two-stage amplifier switch from the A/AB classes into AB/F class. However, the invention may also be applied, in an analogous manner, to the reconfiguration of power amplifiers operating according to other telecommunications standards. 
     The architectures of the transistors of the classes AB and F are relatively close. They only essentially differ by their biasing point and their output impedance. 
     Thus, by acting on the biasing current I biasd  and I biasp  and by modifying the configuration of the output stage, it is possible to modify the class of operation of each transistor Q d  and Q p . 
     Referring to  FIG. 3 , in which the curve I represents the variation of the output power P out  as a function of the input power P in  and the curve II represents the variation of the PAE as a function of the input power, the amplifier, and in particular the biasing circuit  4  of the first stage E 1 , modifies the biasing current I biasd  of the transistor Q d  in such a manner as to lower the compression point CP 1  corresponding to an operating point (P out , a; P in , a) towards the operating point CP 1 ′, corresponding to the operating point (P out , b; P in , b) as illustrated by the arrow F. 
     However, as is known per se, the PAE is at maximum for the maximum output power, whereas, for the lower power levels, the efficiency is lower. 
     Accordingly, the modification of the compression point is combined with a gain compensation in order to adjust the PAE curve so as to obtain a maximum PAE at the compression point CP 1 ′ thus modified. 
     With reference to  FIGS. 4 and 5  and to  FIG. 6 , in which OCP 1  and ICP 1  respectively denote the output power and the input power at the compression point at 1 dB, as previously indicated, the variation of the compression point is obtained by modifying the biasing current I biasd . 
     For example, the biasing circuit  4  may be formed by a succession of current sources I 1 , I 2 , . . . I n  arranged in parallel and each associated with a switch C 1 , C 2 , C 3 , . . . CN, controlled by the central processing unit  6  as a function of the signal RF in , in such a manner as to generate the biasing current I biasd  applied to the transistor Q d . 
     For this purpose, the processing unit  6  is equipped with a detector providing detection of the power level of the input signal RF in  in order, for example, to lower the compression point when the input power decreases. Referring to  FIG. 5 , this can be achieved by increasing or by reducing the biasing current I biasd  as a function of the input power level. 
     Similarly, referring to  FIGS. 7 and 8 , the PAE can be modified by increasing or by reducing the biasing current I biasd . 
     Referring once again to  FIG. 2 , the modification in amplification class of the amplifier, and in particular of the second stage E 2 , is achieved by modifying the equivalent impedance of the output network  3 . 
     Thus, as shown in  FIG. 2 , the output network  3  of the second stage E 2  is equipped with a resonator formed by the parallel association of an inductor L′ and of a capacitor C′ at the output of the second stage E 2  associated with two switches  7  and  8 , one, namely the switch denoted by the reference  7 , interposed between the second stage E 2 , with interposition of a decoupling capacitor C″ and the resonator L′C′, and the other between the resonator L′C′ and the output impedance RLC of the output network  3 . 
     The switches  7  and  8  are controlled by the central processing unit  6  in such a manner as to short-circuit the resonator LC via a bypass line  9 . The output network  3  can thus be selectively configured, under the control of the central processing unit  6 , in such a manner as to configure the power stage  2  either in the form of a class AB transistor or in the form of a class F transistor, for example depending on the power level of the input signal RF in  detected. 
     Although preferred embodiments of the method and apparatus of the present invention have been illustrated in the accompanying Drawings and described in the foregoing Detailed Description, it will be understood that the invention is not limited to the embodiments disclosed, but is capable of numerous rearrangements, modifications and substitutions without departing from the spirit of the invention as set forth and defined by the following claims.