Patent Publication Number: US-2023141476-A1

Title: Switched Emitter Follower Circuit

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is a national phase entry of PCT Application No. PCT/JP2020/015940, filed on Apr. 9, 2020, which application is hereby incorporated herein by reference. 
    
    
     TECHNICAL FIELD 
     The present invention relates to a switched emitter follower circuit used for a track-and-hold circuit or the like which alternately repeats a track mode in which an output signal follows an input signal at timing synchronized with a clock signal and a hold mode in which the output signal is held constant. 
     BACKGROUND 
     An analog-to-digital converter (ADC) is a device widely used for communication, measurement and the like. The ADC converts an input voltage which is an analog signal at timing synchronized with a clock signal to a quantized digital value and outputs the digital code. The ADC includes a track-and-hold circuit in a front end portion in many cases (see NPL 1). 
     An operation of a track-and-hold circuit wo will be described by using  FIGS.  8 A to  8 C . The simplest operation model of the track-and-hold circuit wo is constituted by an analog switch  103  and a capacitor  104 . The analog switch  103  switches between two states, that is, between a track mode Mt which transmits an input to an output as it is in accordance with High/Low of a clock signal ck and a hold mode Mh in which the input and the output are electrically shut down. The capacitor  104  is used for holding a voltage of an output signal Vout which was shut down from the input in the hold mode at a constant value. 
     A relationship between the clock signal ck and the mode of the track-and-hold circuit  100  may be determined arbitrarily, but in the example in  FIGS.  8 A to  8 C , an example in which the mode becomes the track mode Mt when the clock signal ck is High and becomes the hold mode Mh when the clock signal ck is Low will be described. 
     When the clock signal ck is High, that is, during the track mode Mt, as illustrated in  FIG.  8 B , the switch  103  is turned on, and the output signal Vout follows an input signal Vin. At a moment when the clock signal ck turns to Low from High (at the moment when the mode transfers from the track mode Mt to the hold mode Mh), the switch  103  is turned off as shown in  FIG.  8 C , and the voltage value of the input signal Vin at the moment is held in the capacitor  104  during the hold mode Mh. And at a moment when the clock signal ck becomes High again, the output signal Vout is reset and resumes following of the input signal Vin. 
     One of reasons why the track-and-hold circuit is used for the front end portion of the ADC is that, since the ADC needs a certain period of time for the analog-to-digital conversion, it is necessary to hold the input signal during the conversion. 
     Another reason why the track-and-hold circuit is used for the front end portion of the ADC is to reduce an influence of a noise by a clock jitter. Since the timing of the clock signal is not perfectly equal interval, statistical variation is generated in the timing for holding the input signal. If there is a clock jitter as above, such observation is made that the noise is superposed on the output of the ADC. 
     By using the track-and-hold circuit with extremely few clock jitters for the front end portion, even if the clock jitter occurs to some degree in the ADC in a rear stage, there is no influence of the noise as long as the clock jitter is contained in the hold time of the track-and-hold circuit. 
     Particularly in the recent most advanced ADC, since it is difficult to lower the clock jitter, a higher speed cannot be realized while a noise level is suppressed in a practical range, which causes the clock jitter to become a factor that hinders the higher speed. Thus, realization of the higher speed of the track-and-hold circuit is effective for the higher speed of the ADC. 
     In many cases, an analog circuit is constituted by connecting a switching element also called a transistor, a resistor, a capacitor, and the like. There are several types of the transistors, but a bipolar transistor is often used in the analog circuit which requires a high-speed operation. As a circuit configuration of the existing track-and-hold circuit using the bipolar transistor, the one called a switched emitter follower circuit is known. 
     A typical configuration of the conventional switched emitter follower circuit using the bipolar transistor is illustrated in  FIG.  9   . VCC and VEE in  FIG.  9    are power voltages, Vin is an input signal, Vout is an output signal, and ck+ and ck− are clock signals. The clock signals ck+ and ck− are differential signals. Moreover, (const.) in  FIG.  9    indicates that a voltage or an electric current is constant regardless of time. 
     The switched emitter follower circuit is constituted by bipolar transistors M 1  to M 3 , a capacitor Chold, and a constant current source IS. The constant current source IS is constituted by a transistor and the like in many cases. IEE 1  and IEE 2  are electric currents flowing through the constant current source IS from emitters of the bipolar transistors M 2  and M 3 . Assuming that the electric current flowing through the constant current source IS is IEE, it is IEE 1 +IEE 2 =IEE in compliance with Kirchhoff&#39;s electric current law. 
     A basic operation of the switched emitter follower circuit in  FIG.  9    will be described by using  FIGS.  10 A to  10 E . Here, waveforms of the electric currents IEE 1  and IEE 2  are shown in  FIGS.  10 C and  10 D , and the waveform of the output signal Vout is shown in  FIG.  10 E , when the differential clock signals ck+ and ck− in a period Tck shown in  FIG.  10 A  and the input signal Vin shown in  FIG.  10 B  are applied to the switched emitter follower circuit. t 0 , t 1 , t 2 , t 3 , and t 4  in  FIGS.  10 A to  10 E  indicate time. t 0  to t 4  are aligned at each constant interval Tck/2. 
     When the clock signal is High, that is, when it is ck+&gt;ck− (time t satisfies t 0 ≤t≤t 1  or t 2 ≤t≤t 3 ), the transistor M 2  is turned OFF, and the transistor M 3  is turned ON and thus, it is IEE 1 =IEE, IEE 2 =0. At this time, since base-emitter PN junction of the transistor M 1  is brought into an ON state, an emitter voltage (output signal Vout) of the transistor M 1  follows the input signal Vin. That is, when the time t satisfies t 0 ≤t≤t 1  or t 2 ≤t≤t 3 , the switched emitter follower circuit is in the track mode. 
     On the other hand, when the clock signal is Low, that is, when it is ck+&lt;ck− (time t satisfies t 1 ≤t≤t 2  or t 3 ≤t≤t 4 ), the transistor M 2  is turned ON, and the transistor M 3  is turned OFF and thus, it is IEE 1 =0, IEE 2 =IEE. Therefore, the electric current does not flow through the transistor M 1 , and the base-emitter PN junction of the transistor M 1  is brought into the OFF state and thus, the base and the emitter of the transistor M 1  are electrically separated. At this time, since the emitter voltage (the output signal Vout) of the transistor M 1  at the moment when the clock signal becomes Low from High is held by the capacitor Chold, the output signal Vout is held at a constant value only while the clock signal is Low. That is, when the time t satisfies t 1 ≤t≤t 2  or t 3 ≤t≤t 4 , the switched emitter follower circuit is in the hold mode. 
     As described above, alternate repetition of the track mode and the hold mode in accordance with High/Low of the clock signal is the basic operation of the switched emitter follower circuit. 
     A data rate of the switched emitter follower circuit, that is, the number of times of acquiring data per unit time obviously depends on a clock frequency. However, the frequency of the clock signal that can be input has an upper limit due to restriction conditions of an analog circuit or more specifically, parasitic resistance, parasitic capacitance and the like present in a transistor or wiring. This upper limit on the frequency of the clock signal is a main factor which limits a speed of the switched emitter follower circuit. 
     CITATION LIST 
     Non Patent Literature 
     [NPL 1] S. Yamanaka, K. Sano, K. Murata, “A 20-Gs/s Track-and-Hold Amplifier in InP HBT Technology”, in IEEE Transactions on Microwave Theory and Techniques, vol. 58, No. 9, pp. 2334-2339, September 2010. 
     SUMMARY 
     Technical Problem 
     Embodiments of the present invention was made in order to solve the above problem and has an object to provide a switched emitter follower circuit which can operate at a sampling frequency which is twice of a clock frequency. 
     Means for Solving the Problem 
     The switched emitter follower circuit of embodiments of the present invention comprises a first transistor in which a base is connected to a signal input terminal, a first power voltage is applied to a collector, and an emitter is connected to a signal output terminal; a capacitor in which one end is connected to the collector of the first transistor, and the other end is connected to the emitter of the first transistor; and a Gilbert-cell type multiplication circuit in which a positive-phase clock output terminal is connected to the emitter of the first transistor, and a negative-phase clock output terminal is connected to the base of the first transistor, the Gilbert-cell type multiplication circuit configured to output a multiplication result of a first differential clock signal and a second differential clock signal input from an outside to the positive-phase clock output terminal and the negative-phase clock output terminal. 
     Moreover, the switched emitter follower circuit of embodiments of the present invention comprises a first transistor in which a base is connected to a positive-phase signal input terminal, a first power voltage is applied to a collector, and an emitter is connected to a positive-phase signal output terminal; a second transistor in which a base is connected to a negative-phase signal input terminal, the first power voltage is applied to a collector, and an emitter is connected to a negative-phase signal output terminal; a first capacitor in which one end is connected to the collector of the first transistor and the other end is connected to the emitter of the first transistor; a second capacitor in which one end is connected to the collector of the second transistor and the other end is connected to the emitter of the second transistor; a first Gilbert-cell type multiplication circuit in which a first positive-phase clock output terminal is connected to the emitter of the first transistor, and a first negative-phase clock output terminal is connected to the base of the first transistor, the first Gilbert-cell type multiplication circuit configured to output a multiplication result of a first differential clock signal and a second differential clock signal input from an outside to the first positive-phase clock output terminal and the first negative-phase clock output terminal; and a second Gilbert-cell type multiplication circuit in which a second positive-phase clock output terminal is connected to the emitter of the second transistor, and a second negative-phase clock output terminal is connected to the base of the second transistor, the second Gilbert-cell type multiplication circuit configured to output a multiplication result of the first differential clock signal and the second differential clock signal to the second positive-phase clock output terminal and the second negative-phase clock output terminal. 
     Effects of Embodiments of the Invention 
     According to embodiments of the present invention, by providing the first and second transistors, the first and second capacitors, and the first and second Gilbert-cell type multiplication circuits, a sampling frequency of the switched emitter follower circuit can be raised to twice of a clock frequency while the clock frequency remains as conventional. Therefore, according to embodiments of the present invention, a higher speed of the switched emitter follower circuit can be realized while restriction on an analog circuit remains as conventional. 
     Moreover, in embodiments of the present invention, by providing the first and second transistors, the first and second capacitors, and the first and second Gilbert-cell type multiplication circuits, the sampling frequency of the switched emitter follower circuit can be raised to twice of the clock frequency while the clock frequency remains as conventional. Moreover, in embodiments of the present invention, by having differential constitutions of the first and second transistors for input, resistance of the switched emitter follower circuit against a same-phase noise of the input signal can be reinforced. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG.  1    is a circuit diagram illustrating a constitution of a switched emitter follower circuit according to a first embodiment of the present invention. 
         FIG.  2    is a circuit diagram illustrating a typical constitution of a Gilbert-cell type multiplication circuit. 
         FIG.  3    is a circuit diagram illustrating a constitution of a switched emitter follower circuit according to a second embodiment of the present invention. 
         FIG.  4    is a waveform diagram illustrating a simulation result of the switched emitter follower circuit according to the second embodiment of the present invention. 
         FIG.  5    is a circuit diagram illustrating a constitution of a switched emitter follower circuit according to a third embodiment of the present invention. 
         FIG.  6    is a circuit diagram illustrating a constitution of a switched emitter follower circuit according to a fourth embodiment of the present invention. 
         FIG.  7    is a circuit diagram illustrating an example of a clock distribution circuit of the switched emitter follower circuit according to the fourth embodiment of the present invention. 
         FIGS.  8 A to  8 C  are diagrams for explaining an operation of a track-and-hold circuit. 
         FIG.  9    is a circuit diagram illustrating a constitution of a conventional switched emitter follower circuit. 
         FIGS.  10 A to  10 E  are diagrams illustrating signal waveforms of each portion of the conventional switched emitter follower circuit. 
     
    
    
     DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS 
     First Embodiment 
     Hereinafter, embodiments of the present invention will be described by referring to figures.  FIG.  1    is a circuit diagram illustrating a constitution of a switched emitter follower circuit according to a first embodiment of the present invention. The switched emitter follower circuit of this embodiment is constituted by an NPN bipolar transistor M 1  in which a base is connected to a signal input terminal (Vin), a power voltage VCC is applied to a collector, and an emitter is connected to a signal output terminal (Vout), a capacitor Chold in which one end is connected to the collector of the transistor M 1 , and the other end is connected to the emitter of the transistor M 1 , and a Gilbert-cell type multiplication circuit  10  in which a positive-phase clock output terminal (outp) is connected to the emitter of the transistor M 1 , a negative-phase clock output terminal (outn) is connected to the base of the transistor M 1 , and a multiplication result of a differential clock signal ck 1  and a differential clock signal ck 2  input from an outside is output to the positive-phase clock output terminal and the negative-phase clock output terminal. 
     The Gilbert-cell type multiplication circuit  10  is constituted by an NPN bipolar transistor M 4  in which a positive-phase signal ckp 1  of the differential clock signal ck 1  is input into a base, and a collector is connected to the negative-phase clock output terminal (outn), an NPN bipolar transistor M 5  in which a negative-phase signal ckn 1  of the differential clock signal ck 1  is input into the base, and the collector is connected to the positive-phase clock output terminal (outp), an NPN bipolar transistor M 6  in which the negative-phase signal ckn 1  of the differential clock signal ck 1  is input into the base, and the collector is connected to the negative-phase clock output terminal (outn), an NPN bipolar transistor M 7  in which the positive-phase signal ckp 1  of the differential clock signal ck 1  is input into the base, and the collector is connected to the positive-phase clock output terminal (outp), an NPN bipolar transistor M 8  in which a positive-phase signal ckp 2  of the differential clock signal ck 2  is input into the base, and the collector is connected to the emitters of the transistors M 4  and M 5 , an NPN bipolar transistor M 9  in which a negative-phase signal ckn 2  of the differential clock signal ck 2  is input into the base, and the collector is connected to the emitters of the transistors M 6  and M 7 , and a constant current source IT in which one end is connected to the emitters of the transistors M 8  and M 9 , while a power voltage VEE is applied to the other end and which supplies a constant electric-current to the transistors M 8  and M 9 . 
     The transistors M 4  and M 5  constitute an upper differential pair with the positive-phase signal ckp 1  and the negative-phase signal ckn 1  of the differential clock signal ck 1  as inputs. Similarly, the transistors M 6  and M 7  constitute the upper differential pair. The transistors M 8  and M 9  have the positive-phase signal ckp 2  and the negative-phase signal ckn 2  of the differential clock signal ck 2  as inputs and supply a tail electric current to the upper differential pair constituted by the transistors M 4  and M 5  and the upper differential pair constituted by the transistors M 6  and M 7 . 
     And the positive-phase signal outp of the multiplication result of the differential clock signals ck 1  and ck 2  is output from the collectors (positive-phase clock output terminals) of the transistors M 5  and M 7 , and the negative-phase signal outn of the multiplication result of the differential clock signals ck 1  and ck 2  is output from the collectors (negative-phase clock output terminals) of the transistors M 4  and M 6 . 
     Note that a typical constitution of the Gilbert-cell type multiplication circuit is illustrated in  FIG.  2   . In the constitution in  FIG.  2   , a load resistance R 1  is connected to the negative-phase clock output terminal, a load resistance R 2  is connected to the positive-phase clock output terminal, and inputs are differential signals in 1  and in 2 , but an operation of the circuit is the same as that of the Gilbert-cell type multiplication circuit  10  in  FIG.  1   . 
     The Gilbert-cell type multiplication circuit as above is disclosed in the document “B. Gilbert, “A Precise Four-Quadrant Multiplier with Subnanosecond Response”, IEEE J. Solid-State Circuits, vol. SC-3, pp. 365-373, 1968”, for example. 
     In the constitution in  FIG.  1   , frequencies of the differential clock signals ck 1  and ck 2  are the same. Moreover, in the constitution in  FIG.  1   , the positive-phase signal ckp 1  of the differential clock signal ck 1  is input into the transistors M 4  and M 7 , and the negative-phase signal ckn 1  is input into the transistors M 5  and M 6 , but the inputs of the positive-phase signal ckp 1  and the negative-phase signal ckn 1  may be opposite. Similarly, the positive-phase signal ckp 2  of the differential clock signal ck 2  is input into the transistor M 8 , and the negative-phase signal ckn 2  is input into the transistor M 9 , but the inputs of the positive-phase signal ckp 2  and the negative-phase signal ckn 2  may be opposite. 
     Alternatively, either one of the positive-phase signal ckp 1  and the negative-phase signal ckn 1  may be a DC bias voltage. In this case, it is only necessary to input the clock signal in a single phase to either one of a pair of the transistors M 4  and M 7  and a pair of the transistors M 5  and M 6 , and the DC bias voltage to the other pair. 
     Similarly, either one of the positive-phase signal ckp 2  and the negative-phase signal ckn 2  may be a DC bias voltage. In this case, it is only necessary to input the single-phase clock signal into either one of the transistors M 8  and M 9 , and the DC bias voltage to the other. 
     Due to a nature of the Gilbert-cell type multiplication circuit  10 , the differential clock signals ck 1  and ck 2  do not have to have the same phase, and there is no problem even if the differential clock signals ck 1  and ck 2  have a delay (phase difference). 
     The load current of the transistor M 1  oscillates at a frequency of the multiplication result of the differential clock signals ck 1  and ck 2 , that is, twice of the clock frequency. Therefore, the transistor M 1  performs switching at the frequency twice of the clock frequency. 
     As described above, in this embodiment, the sampling frequency of the switched emitter follower circuit can be made twice of the clock frequency. Therefore, according to this embodiment, a higher speed of the switched emitter follower circuit can be realized. 
     Second Embodiment 
     Subsequently, a second embodiment of the present invention will be described.  FIG.  3    is a circuit diagram illustrating a constitution of a switched emitter follower circuit according to the second embodiment of the present invention. The switched emitter follower circuit of this embodiment is constituted by an NPN bipolar transistor M 1   p  in which a base is connected to a positive-phase signal input terminal (Vinp), the power voltage VCC is applied to a collector, and an emitter is connected to a positive-phase signal output terminal (Voutp), an NPN bipolar transistor M 1   n  in which the base is connected to a negative-phase signal input terminal (Vinn), the power voltage VCC is applied to the collector, and the emitter is connected to a negative-phase signal output terminal (Voutn), a capacitor Choldp in which one end is connected to the collector of the transistor M 1   p , and the other end is connected to the emitter of the transistor M 1   p , a capacitor Choldn in which one end is connected to the collector of the transistor M 1   n , and the other end is connected to the emitter of the transistor M 1   n,  a Gilbert-cell type multiplication circuit lop in which a first positive-phase clock output terminal (outpp) is connected to the emitter of the transistor M 1   p , a first negative-phase clock output terminal (outnp) is connected to the base of the transistor M 1   p , and a multiplication result of the differential clock signal ck 1  and the differential clock signal ck 2  is output to the first positive-phase clock output terminal and the first negative-phase clock output terminal, and a Gilbert-cell type multiplication circuit ion in which a second positive-phase clock output terminal (outpn) is connected to the emitter of the transistor M 1   n,  a second negative-phase clock output terminal (outnn) is connected to the base of the transistor M 1   n , and the multiplication result of the differential clock signal ck 1  and the differential clock signal ck 2  is output to the second positive-phase clock output terminal and the second negative-phase clock output terminal. 
     The Gilbert-cell type multiplication circuit  10   p  is constituted by an NPN bipolar transistor M 4   p  in which the positive-phase signal ckp 1  of the differential clock signal ck 1  is input into a base, and a collector is connected to a first negative-phase clock output terminal (outnp), an NPN bipolar transistor M 5   p  in which a negative-phase signal ckn 1  of the differential clock signal ck 1  is input into the base, and the collector is connected to a first positive-phase clock output terminal (outpp), an NPN bipolar transistor M 6   p  in which the negative-phase signal ckn 1  of the differential clock signal ck 1  is input into the base, and the collector is connected to the first negative-phase clock output terminal (outnp), an NPN bipolar transistor M 7   p  in which the positive-phase signal ckp 1  of the differential clock signal ck 1  is input into the base, and the collector is connected to the first positive-phase clock output terminal (outpp), an NPN bipolar transistor M 8   p  in which a positive-phase signal ckp 2  of the differential clock signal ck 2  is input into the base, and the collector is connected to the emitters of the transistors M 4   p  and M 5   p,  an NPN bipolar transistor M 9   p  in which a negative-phase signal ckn 2  of the differential clock signal ck 2  is input into the base, and the collector is connected to the emitters of the transistors M 6   p  and M 7   p,  and a constant current source ITp in which one end is connected to the emitters of the transistors M 8   p  and M 9   p,  while the power voltage VEE is applied to the other end and which supplies a constant electric-current to the transistors M 8   p  and M 9   p.    
     The Gilbert-cell type multiplication circuit ion is constituted by an NPN bipolar transistor M 4   n  in which the positive-phase signal ckp 1  of the differential clock signal ck 1  is input into a base, and a collector is connected to a second negative-phase clock output terminal (outnn), an NPN bipolar transistor M 5   n  in which the negative-phase signal ckn 1  of the differential clock signal ck 1  is input into the base, and the collector is connected to a second positive-phase clock output terminal (outpn), an NPN bipolar transistor M 6   n  in which the negative-phase signal ckn 1  of the differential clock signal ck 1  is input into the base, and the collector is connected to the second negative-phase clock output terminal (outnn), an NPN bipolar transistor M 7   n  in which the positive-phase signal ckp 1  of the differential clock signal ck 1  is input into the base, and the collector is connected to the second positive-phase clock output terminal (outpn), an NPN bipolar transistor M 8   n  in which a positive-phase signal ckp 2  of the differential clock signal ck 2  is input into the base, and the collector is connected to the emitters of the transistors M 4   n  and M 5   n,  an NPN bipolar transistor M 9   n  in which a negative-phase signal ckn 2  of the differential clock signal ck 2  is input into the base, and the collector is connected to the emitters of the transistors M 6   n  and M 7   n,  and a constant current source ITn in which one end is connected to the emitters of the transistors M 8   n  and M 9   n,  while the power voltage VEE is applied to the other end and which supplies a constant electric-current to the transistors M 8   n  and M 9   n.    
     Operations of the Gilbert-cell type multiplication circuits  10   p  and  10   n  are the same as that of the Gilbert-cell type multiplication circuit  10  in the first embodiment. The positive-phase signal outpp of the multiplication result of the differential clock signals ck 1  and ck 2  is output from the collectors (the first positive-phase clock output terminals) of the transistors M 5   p  and M 7   p  of the Gilbert-cell type multiplication circuit  10   p,  and the negative-phase signal outnp of the multiplication result of the differential clock signals ck 1  and ck 2  is output from the collectors (the first negative-phase clock output terminals) of the transistors M 4   p  and M 6   p . Similarly, the positive-phase signal outpn of the multiplication result of the differential clock signals ck 1  and ck 2  is output from the collectors (the second positive-phase clock output terminals) of the transistors M 5   n  and M 7   n  of the Gilbert-cell type multiplication circuit ion, and the negative-phase signal outnn of the multiplication result of the differential clock signals ck 1  and ck 2  is output from the collectors (the second negative-phase clock output terminals) of the transistors M 4   n  and M 6   n.    
     In this embodiment, the input signal has the differential constitution (Vinp, Vinn), and the transistors for input has the differential constitutions of M 1   p  and M 1   n  in accordance with that and thus, resistance of the switched emitter follower circuit against the same-phase noise of the input signal can be reinforced. A voltage difference of the positive-phase signal Vinp and the negative-phase signal Vinn of the differential input signal is Vin=Vinp−Vinn. The voltage difference of the positive-phase signal Voutp and the negative-phase signal Voutn of the differential output signal is Vout=Voutp−Voutn. That is, since information is given to a difference in the signal, the same positive-phase noise is cancelled by calculating a difference between the positive-phase signal Voutp and the negative-phase signal Voutn of the differential output signal. 
     In order to confirm that the circuit of this embodiment is actually operated, simple verification was conducted by using a circuit simulation software LTspice (Registered Trademark) XVII by Analog Devices Inc. In this circuit simulation, the positive-phase signal Vinp and the negative-phase signal Vinn of the differential input signal was set to a sine wave with a frequency of 200 Hz and an amplitude of 100 mV. Moreover, the positive-phase signal ckp 1  and the negative-phase signal cknm of the differential clock signal ck 1  was set to a sine wave with a frequency of 1 kHz and an amplitude of 100 mV. As the differential clock signal ck 2 , the same signal as the differential clock signal ckm was used. Moreover, capacities of the capacitors Choldp and Choldn were set to 500 nF, and the electric current flowing through the constant current sources ITp and ITn was set to 1 mA. 
     A simulation result of responses of the switched emitter follower circuit in  FIG.  3    for time of 10 ms is illustrated in  FIG.  4   . According to  FIG.  4   , it is known that the sampling is performed at 2 kHz, which is twice of the clock frequency 1 kHz as expected. 
     Third Embodiment 
     Subsequently, a third embodiment of the present invention will be described.  FIG.  5    is a circuit diagram illustrating a constitution of a switched emitter follower circuit according to the third embodiment of the present invention. The switched emitter follower circuit of this embodiment is constituted by the NPN bipolar transistors M 1   p  and M 1   n,  the capacitors Choldp and Choldn, and the Gilbert-cell type multiplication circuits  10   p  and  10   n′.    
     The second embodiment has a structure in which two units of Gilbert-cell type multiplication circuits  10   p  and  10   n,  which are the same type as the Gilbert-cell type multiplication circuit  10  in the first embodiment, are provided. Since a lower movable pair (M 8   p,  M 9   p ) of the Gilbert-cell type multiplication circuit lop and a lower movable pair (M 8   n , M 9   n ) of the Gilbert-cell type multiplication circuit ion perform the totally same operations, the number of transistors to be used can be decreased by grouping them into one. 
     In this embodiment, too, the constitution of the Gilbert-cell type multiplication circuit lop is the same as that of the second embodiment. The constitutions of an upper differential pair constituted by the transistors M 4   n  and M 5   n  and the upper differential pair constituted by the transistors M 6   n  and M 7   n  of the Gilbert-cell type multiplication circuit  10   n ′ are the same as that of the Gilbert-cell type multiplication circuit  10   n.    
     The Gilbert-cell type multiplication circuit  10   n ′ is constituted to share an electric-current source circuit with the Gilbert-cell type multiplication circuit  10   p.  Specifically, the emitters of the transistors M 4   n  and M 5   n  of the Gilbert-cell type multiplication circuit  10   n ′ are connected to the collector of the transistor M 8   p,  and the emitters of the transistors M 6   n  and M 7   n  are connected to the collector of the transistor M 9   p.    
     As described above, in this embodiment, since the number of transistors can be decreased more than the second embodiment, a circuit scale can be made smaller, and power consumption can be reduced. 
     Fourth Embodiment 
     Subsequently, a fourth embodiment of the present invention will be described.  FIG.  6    is a circuit diagram illustrating a constitution of a switched emitter follower circuit according to the fourth embodiment of the present invention. The switched emitter follower circuit of this embodiment is constituted by the NPN bipolar transistor M 1 , the capacitor Chold, the Gilbert-cell type multiplication circuit  10 , and a clock distribution circuit  11  which branches the differential clock signal ck into the differential clock signal ck 1  and the differential clock signal ck 2 . 
     In the first to third embodiments, the two differential clock signals ck 1  and ck 2  are supposed to be input into the switched emitter follower circuit from the outside. 
     On the other hand, in this embodiment, the differential clock signals ck 1  and ck 2  are generated by branching the differential clock signal ck by the clock distribution circuit  11 . As a result, in this embodiment, the number of the differential clock signal to be applied from the outside can be made to be one. 
     One example of a specific constitution of the clock distribution circuit ii is illustrated in  FIG.  7   . The clock distribution circuit  11  is constituted by an NPN bipolar transistor M 10  in which the positive-phase signal ckp of the differential clock signal ck is input into the base, an NPN bipolar transistor M 11  in which the negative-phase signal ckn of the differential clock signal ck is input into the base, an NPN bipolar transistor M 12  in which the power voltage VCC is applied to the base and the collector, and the emitter is connected to the collector of the transistor M 10 , an NPN bipolar transistor M 13  in which the power voltage VCC is applied to the base and the collector, and the emitter is connected to the collector of the transistor M 11 , a constant current source IT 10  in which one end is connected to the emitter of the transistor Mb 10 , and the power voltage VEE is applied to the other end, and a constant current source IT 11  in which one end is connected to the emitter of the transistor M 11 , and the power voltage VEE is applied to the other end. 
     The constitution of  FIG.  7    uses the emitter follower circuit. The differential clock signal ck is output as it is as the differential clock signal ck 1 . Moreover, a signal obtained by shifting the bias voltage of the positive-phase signal ckp of the differential clock signal ck only by a base-emitter voltage of the transistor M 10  is output as the positive-phase signal ckp 2  of the differential clock signal ck 2  from the emitter of the transistor M 10 . Furthermore, a signal obtained by shifting the bias voltage of the negative-phase signal ckn of the differential clock signal ck only by the base-emitter voltage of the transistor M 11  is output as the negative-phase signal ckn 2  of the differential clock signal ck 2  from the emitter of the transistor M 11 . 
     It is needless to say that the constitution of the clock distribution circuit  11  is not limited to  FIG.  7   , and other constitutions may be used. 
     Moreover, in the examples in  FIGS.  6  and  7   , explanation was made by citing the example in which the clock distribution circuit  11  is applied to the first embodiment, but it is needless to say that the clock distribution circuit  11  may be applied to the second and third embodiments. 
     The embodiments illustrated above only show examples of applications so as to aid understanding of a principle of the present invention, and many variations within a range not departing from an idea of the present invention are allowed for the embodiments in actual circumstances. 
     INDUSTRIAL APPLICABILITY 
     Embodiments of the present invention can be applied to a switched emitter follower circuit. 
     REFERENCE SIGNS LIST 
     M 1 , M 4  to M 9 , M 1   p,  M 4   p  to M 9   p,  M 1   n,  M 4   n  to M 9   n  NPN bipolar transistor 
     IT, ITp, ITn Constant current source 
     Chold, Choldp, Choldn Capacitor 
       10 ,  10   p ,  10   n,    10   n ′ Gilbert-cell type multiplication circuit 
       11  Clock distribution circuit.