Patent Publication Number: US-7898941-B2

Title: Method and system for assigning a plurality of MACs to a plurality of processors

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is a non-provisional application claiming the benefit of the priority date of U.S. Provisional Application Ser. No. 60/971,415, filed on Sep. 11, 2007, the entire contents of which are incorporated herein by reference. 
    
    
     BACKGROUND 
     1. Field of Invention 
     The present invention relates to the field of communication systems, and more particularly to improving the quality of fault detection and recovery methods of connectivity between a plurality of clients from a plurality of LANs and a networking device having a bank of processing nodes (units). 
     2. Description of Background Art 
     In systems of networking devices based on plurality of processoring units connected to one or more Ethernet Local Area Networks (LANs), it is challenging to provide Reliability, Availability, and Serviceability (RAS) connection for more than 99.999% of the time while maintaining good separation between the different LANs to achieve security needs. A networking device can be a node in a network that communicates and services a plurality of users. An exemplary networking device can be a multipoint control unit (MCU), a firewall, a content server, a media server, etc. 
     In a common networking device, one or more Media Access Controls (MAC) addresses are associated with one processing unit as long as the system is up and running. A MAC address can refer to an Ethernet Hardware Address (EHA) or a hardware address. A MAC address is an identifier that is attached to most network adapters (i.e., network interface cards (NICs)) as the name of the adapter. In such a common architecture, if a processing node fails to operate or needs to be replaced, there is no way to support the functionality of the processor to a standby processoring unit without switching to another MAC. Using a redundant MAC/Processor pair results in high cost/utilization ratio. Furthermore, one MAC/Processor standby pair would be required for each LAN. A failure occurring on the MAC or somewhere along the physical path (PHY or cable) results in disconnecting the processor even though the processor is not in a permanent fault condition, and would otherwise be capable serving users from other LANs. 
     Thus, it is evident that current technologies of multi processors equipment create significant difficulties in reliable connectivity with external Ethernet LANs. 
     SUMMARY 
     The above-described needs are met using a topology in which a plurality of MACs responsible for tasks specified by the data link layer of an Open System Interconnect module/stack are separated from a plurality of processing nodes (units). The processing nodes are responsible for handling tasks related to the OSI&#39;s layer three and above responsibilities. The above group of MAC controllers functions as a connectivity resource pool for the plurality of processing nodes, which function as a processing resource pool and are separated from the MAC controllers. In such a topology the two resource pools can be connected to one another on the fly, delivering the required Reliability Availability and Serviceability. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a block diagram illustrating an exemplary networking device system based on a plurality of processing units (nodes) and a bank of MAC controllers connected by a interconnect switch array; and 
         FIG. 2  is a flowchart illustrating an assignment process of a MAC controller with a processing node in three phases: before fault detection, during fault detection, and after fault detection. 
     
    
    
     DETAILED DESCRIPTION 
     Like numerals represent like elements in the figures. For convenience, only some elements of the same group may be labeled with numerals. The purpose of the drawings is to describe exemplary embodiments and not for production. Therefore features shown in the figures are chosen for convenience and clarity of presentation only. 
       FIG. 1  schematically illustrates elements of an exemplary networking device system based on plurality of processing nodes/units  100   a - 100   e  and a bank of MAC controllers  102   a - 102   e  connected by an interconnect switch array  101 . The number of processing nodes and the number of MAC controllers are not limited to the ones shown in  FIG. 1 . For example, the system may have two processor nodes and five MAC controllers. Various other combinations can also be arranged. Each MAC controller  102   a - 102   e  is responsible for tasks specified by the data link layer of the OSI module/stack. For example, each MAC controller ( 102 ) can comply with communication protocols employed by the data link layer such as, but are not limited to, 802.3 CSMA/CD, 802.1P and 802.1Q. 
     Referring to  FIG. 1 , the MAC controllers  102   a - 102   e  can be divided in one or more banks. Each bank can be associated with a broadcasting domain such as a local area network (LAN) of a plurality of users. Each broadcasting domain can be associated with a bank of ‘N’ MAC addresses and a bank of ‘N+1’ MAC controllers. The MAC controllers can be physically connected to a broadcast domain. Each of the MAC addresses from this domain can be assigned to a corresponding MAC controller that belongs to the same domain. N is the number of active MAC controllers connected to the same broadcast domain and the ‘+1’ MAC controller is the non-active redundant MAC controller (i.e., a standby MAC controller). A MAC address of a MAC controller can be reused or reassigned to the standby redundant MAC controllers, should the need arise. A broadcast domain is a segment of a computer network, in which all nodes, can reach each other by broadcast at the data link layer. Routers and other higher-layer devices form boundaries between broadcast domains. An exemplary broadcasting message that can be used in a broadcasting domain is when a first computer has only the network address of a second computer (an IP address, for example). The first computer may use the Address Resolution Protocol (ARP) and broadcasts an ARP request with the IP address of the second computer. The second computer, if connected to the same broadcasting domain can respond with its MAC address. 
     Usually MAC addresses are allocated by IEEE organization to vendors of network devices and network interface cards (NIC). Then each vendor can allocate a MAC address per each NIC. A reader who wishes to learn more about the process of allocating MAC addresses is invited to visit IEEE Standards Association website. 
     In the exemplary embodiments that are disclosed, a group of ‘N’ MAC addresses is allocated to a network device, an MCU for example. The group can be managed by a housekeeping computer  103  or  104 . A MAC address, from the group, can be allocated to any one of the Ethernet MAC controllers  102  that is active (connected to a broadcasting domain). A standby Ethernet MAC controller  102  is not associated with a MAC address. Usually the number of MAC controllers  102  is larger than ‘N’, ‘N+1’ for example, in order to include redundancy. 
     When a new connection to a broadcasting domain is established, a processor  100  and an Ethernet MAC controller  102  are selected and associated with each other via interconnected switch array  101 . A MAC address from the group of MAC addresses is transferred by the active housekeeping processor  103  to the selected processor  100  with an instruction to load the MAC address into the associated Ethernet MAC controller  102 . Subsequently, the connection to the broadcasting domain is established. 
     The MAC controller is typically connected to a physical entity (10/100/1000base-T PHY, for example, not shown on  FIG. 1 ) that according to the OSI module/stack is responsible for transmission of unstructured bit streams over a physical medium. The OSI physical layer tasks may comply with 10base-T, 100Base-T, 1000base-T, 1000base-LX, or 1000base-SX, for example. 
     Each processing node  100   a - 100   e  is responsible for handling the tasks related to OSI&#39;s layer three and above. For example, each processing node  100   a - 100   e  can handle IP (Internet Protocol), DHCP (Dynamic Host Configuration Protocol), IPSEC (IP Security) and ICMP (Internet Control Massage Protocol). The OSI Transport layer tasks can include TCP (Transport Control Protocol), UDP (User Datagram Protocol) and RTP (Real-time Transport Protocol), for example. Other tasks relating to the upper layers of the OSI module can include handling audio signals such as G.711, Video signals such as H.261, security related tasks such as SSH (Secure Shell), internet management such as SNMP (Simple Network Management Protocol), Network timing such as NTP (Network Time Protocol), and other applications such as HTTP (Hyper Text Transport Protocol) or FTP (File Transfer Protocol). 
     The interconnect switch array  101  can comply with various standards such as but not limited to PCI express, RapidIO, or a cross bar array implemented by Field Programmable Gate Array, for example. An exemplary switch can be VSC3312 manufactured by Vitsse Semiconductor Corporation, CA USA. A reader who wishes to learn more about switch arrays is invited to visit Vitsse site: www.vitsse.com. Processing nodes  100   a - 100   e  can communicate over an internal network  105  with an active housekeeping processor (processing node)  103 . Network  105  can be a circuit switched network, packet switched network, carrier sense media access network, or any technology that allows two or more processing nodes to communicate with each other. In some embodiments an additional housekeeping set including processor  104  and network  106  can be added for redundancy and reliability. Networks  105  and  106  are separate from the external LANs (not shown in the drawings) that are connected to the other side of the Ethernet MAC controllers  102 . In some embodiments the housekeeping tasks can be executed by one of the processing nodes  100  in addition to its other tasks. 
     During initiation the housekeeping processing unit  103  can assign a MAC address from a bank of addresses associated with a certain LAN to a MAC controller ( 102   a - 102   e ) that belongs to a bank of controllers associated with the same LAN. After initiation, the binding and re-binding of the MAC controller ( 102   a - 102   e ) to a processor ( 100   a - 100   e ) by the interconnect switch array ( 101 ) can be executed as a process such as illustrated in  FIG. 2 , in which a smooth and rapid failover to a redundant MAC controller or processing node is possible. After binding a MAC controller ( 102   a - 102   e ) with a processor ( 100   a - 100   e ), a MAC address is allocated to the processor. The processor ( 100   a - 100   e ) transfers the allocated MAC address to its newly bonded MAC controller via the connection that was established by the processor via the interconnect switch array ( 101 ). 
       FIG. 2  illustrates an assignment process of a MAC controller with a processing node before, during, and after fault detection. The process can be implemented by the active housekeeping processing node  103 , via network  105 , for example. 
     Fault detection is the process in which an abnormal behavior in the system is detected. The flowchart starts during establishing a connection between a client and a processing node and a broadcasting domain. A decision is made in step  200  whether one of the MAC controllers  102   a - 102   e  is available. An available MAC controller is the one that is physically connected to the broadcasting domain over its physical layer. If there are no available MAC controllers, then the process ends. If there is an available MAC controller, the processing node is dynamically assigned and bonded (step  201 ) to the available MAC controller via interconnection switch array  101  ( FIG. 1 ). Once the dynamic assignment of the MAC/Processor pair is completed, a free MAC address from the group of MAC addresses is assigned to the pair. In an example of the present invention, the MAC address is allocated by active housekeeping processor to the assigned processor, which, in turn, loads the MAC address to its associated MAC controller  102 . 
     Then, the process of fault detection stage begins. The exemplary fault detection process presented in  FIG. 2  uses ICMP packets (echo packets) to periodically monitor the user network. The destination of the echo packet can be the default gateway IP address of the LAN to which the MAC controller is connected. The housekeeping processor  103  can request the processing unit  100  to send echo packets and to acknowledge back if an echo reply was received. The housekeeping processor, through this process of requests and acknowledgments, monitors the validity of the connection of the processing unit to the user LAN, thereby detecting a fault if one occurs along the connectivity path. 
     The fault detecting process begins with sending an echo to default gateway IP address (step  202 ) and the decision (step  203 ) if an echo reply was received indicating that the connection with the gateway is alive. The default gateway is the default gateway of the broadcasting domain to which the assigned MAC controller is connected. After T1 seconds (step  204 ) the fault detect process resumes by issuing a new echo packet (step  202 ). If (step  203 ) the echo reply was not received, indicating that a fault was detected, recovery phase is initiated (steps  205  to  209 ). T1 can be a configurable parameter; it can be in the range of few milliseconds to few seconds, depending on the broadcasting domain and the connection between the MAC controller  102  ( FIG. 1 ) and the broadcasting domain. 
     The first stage of the recovery phase is to assign, via interconnect switch array  101  ( FIG. 1 ), a redundant processing node (step  205 ). The second stage is to issue a new echo packet (step  206 ). The third stage is to decide if the echo packet was received (step  207 ). If the echo reply was received, the fault detecting process resumes by issuing a new echo packet (step  202 ). The receipt of echo packet in step  207  indicates that no fault has been detected at that moment. If the echo reply was not received, then it indicates that a fault has been detected. Subsequently, a decision is made whether there is a standby redundant MAC controller (step  208 ) connected to the same broadcast domain as the suspected faulty MAC controller. Preferably, the redundant MAC controller is first assigned to the MAC address of the suspected faulty MAC to enable a smooth transition to the redundant path. In an alternate exemplary embodiment of the present invention the order of binding-rebinding can start with replacing a MAC controller and then a processor. 
     A process (not shown in  FIG. 2 ) may start by disabling the current MAC controller and only then enabling the redundant MAC controller, to avoid MAC address duplication in the case the redundant MAC controller is indeed connected to the same broadcast domain. Using the same MAC address can minimize undesired effects caused once a new connectivity path is presented. When the redundant MAC controller uses the same MAC address (not simultaneously) as the faulty MAC controller, the user&#39;s network is not aware of the replacement. A Layer 2 switch involved in the connection, based on IEEE802.1D transparent bridging method, can be connected to the redundant MAC and automatically learns the new path just by receiving the upcoming echo packet. If a redundant MAC controller is available, the MAC controller is assigned to the processor (step  209 ) and the process of fault detection may continue ( 202 ). 
     The disclosed method and system improves the Reliability Availability and Serviceability of a networking device based on plurality of processing nodes (processors) that need to be connected to the user Ethernet Local Area Networks. The disclosed method and system reduces the unscheduled downtime of a processor system by providing a topology that support failover of any single point of failure a processor system might face. The disclosed method and system also reduces the scheduled downtime of a processor system to enable upgrade for example. Furthermore the disclosure provides a method and an apparatus for network separation, i.e., a firewall gateway, by enabling separation between MAC/Processors pairs. 
     The process  205  of replacing a processor by a redundant processor can include loading the redundant processor with the software and the information which is needed for handling the activities which were executed by the faulty processor. The process is executed by the active housekeeping processor  103  which can record the required information. 
     In the description and claims of the present application, each of the verbs, “comprise” “include” and “have”, and conjugates thereof, are used to indicate that the object or objects of the verb are not necessarily a complete listing of members, components, elements, or parts of the subject or subjects of the verb. 
     In this application the words “unit” and “module” are used interchangeably. Anything designated as a unit or module may be a stand-alone unit or a specialized module. A unit or a module may be modular or have modular aspects allowing it to be easily removed and replaced with another similar unit or module. Each unit or module may be any one of, or any combination of, software, hardware, and/or firmware. Software of a logical module can be embodied on a computer readable medium such as a read/write hard disc, CDROM, Flash memory, ROM, etc. In order to execute a certain task a software program can be loaded to an appropriate processor as needed. 
     The present invention has been described using detailed descriptions of embodiments thereof that are provided by way of example and are not intended to limit the scope of the invention. The described embodiments comprise different features, not all of which are required in all embodiments of the invention. Some embodiments of the present invention utilize only some of the features or possible combinations of the features. Variations of embodiments of the present invention that are described and embodiments of the present invention comprising different combinations of features noted in the described embodiments will occur to persons of the art.