Patent Publication Number: US-2007102785-A1

Title: Semiconductor device with fuse and method of fabricating the same

Description:
This application claims the benefit of Korean Patent Application No. 2005-0107073, filed Nov. 09, 2005, the disclosure of which is incorporated by reference.  
     BACKGROUND  
      1. Field of the Invention  
      The present invention relates to a semiconductor device and a fabrication method thereof and, more particularly, to a semiconductor device with a fuse and a method of fabricating the same.  
      2. Description of Related Art  
      Semiconductor memory devices (chips) fabricated on a semiconductor substrate are generally electrically tested before an assembly process. As a result of the testing, the semiconductor memory devices may be classified into bad chips and good chips. If the bad chips malfunction during the testing due to a single failed cell, the failed cell may be replaced by a redundant cell using a repair process. The repair process can include a laser beam irradiation step of blowing predetermined fuses in order for the redundant cell to take on the address of the failed cell for writing and reading modes.  
      A fuse is generally made of a metal layer, and thus may be protected by an insulating layer before the laser beam irradiation step. A method for protecting the fuse by forming a spacer on sidewalls of the fuse is disclosed in U.S. Pat. No. 6,124,165 (“the &#39;165 patent”). According to the &#39;165 patent, the fuse is simultaneously formed with a bit line, and the top and sidewalls of the fuse are protected by a silicon nitride layer. As a result, the fuse may be protected from damage from outside moisture.  
      Nevertheless, continuous effort is required to fabricate a semiconductor device with an improved fuse region that can effectively protect the fuse and an inner circuit from outside moisture, while simplifying a process of forming the fuse and a fuse window exposing the fuse.  
     SUMMARY  
      Embodiments of the present invention provide a semiconductor device with a fuse that can simplify a repair process while minimizing failures, and a method of fabricating the same.  
      In one embodiment, a semiconductor layer with a fuse is provided. The semiconductor device includes a fuse pattern having a fuse conductive pattern disposed on a semiconductor substrate and a fuse capping pattern disposed on the fuse conductive pattern. An upper insulating layer covers the fuse pattern. A fuse window exposing the fuse pattern through the upper insulating layer is formed. A fuse spacer and a fuse window spacer are disposed on sidewalls of the fuse pattern exposed by the fuse window and sidewalls of the fuse window, respectively. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING  
      The foregoing and other objects, features and advantages of the invention will be apparent from the detailed description of exemplary embodiments of the invention, as illustrated in the accompanying drawings.  
       FIG. 1  is a plan view showing part of an array region of a semiconductor device with a fuse according to an exemplary embodiment of the invention.  
       FIGS. 2 through 10  are cross-sectional views taken along line I-I′ of  FIG. 1 , which illustrate a fabrication method of a semiconductor device with a fuse. 
    
    
     DETAILED DESCRIPTION  
      The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments of the invention are shown. This invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. The drawings may not be to scale, and the thickness of layers and regions may be exaggerated for clarity. Like numbers refer to like elements throughout the specification.  
       FIG. 1  is a plan view showing part of an array region of a semiconductor device with a fuse according to an exemplary embodiment of the invention.  FIG. 10  is a cross-sectional view taken along line I-I′ of  FIG. 1 .  
      Referring to  FIGS. 1 and 10 , an insulating layer  101  is disposed on a surface of a semiconductor substrate  100 . First and second lower interconnections  103   a  and  103   b  are disposed on the insulating layer  101 . The first and second lower interconnections  103   a  and  103   b  may be disposed to be at approximately the same height above the insulating layer  101  and may further be spaced apart from each other. As shown in  FIG. 1 , other lower interconnections may be disposed substantially parallel and adjacent to the first and second lower interconnections  103   a  and  103   b . When the semiconductor device is a semiconductor memory device, the first and second lower interconnections  103   a  and  103 B may be the same conductive layer as a bit line of the semiconductor memory device.  
      A lower insulating layer  105  is disposed on the surface of the semiconductor substrate having the first and second lower interconnections  103   a  and  103   b . Both ends of the first and second lower interconnections  103   a  and  103   b  may be exposed by first and second fuse contact holes ( 111   ah  and  111   bh  of  FIG. 1 ) and first and second lower interconnection contact holes ( 111   ah ′ and  111   bh ′ of  FIG. 1 ) which are disposed through the lower insulating layer  105 . The first and second fuse contact holes are respectively filled with first and second fuse contact plugs  111   a  and  111   b , and the first and second lower interconnection contact holes  111   ah ′ and  111   bh ′ are respectively filled with first and second lower interconnection contact plugs  111   a ′ and  111   b ′. Each contact plug  111   a ,  111   b ,  111   a ′, or  111   b ′ may include a contact barrier pattern  107 ′ and a contact pattern  109 ′ surrounded by the contact barrier pattern  107 ′. The contact barrier pattern  107 ′ may be a titanium nitride layer, and the contact pattern  109 ′ may be a tungsten layer. The contact barrier pattern  107 ′ may be surrounded by an ohmic layer (not illustrated) such as a titanium layer.  
      A fuse pattern  123   f  is disposed to cover the first and second fuse contact plugs  111   a  and  111   b  on the lower insulating layer  105 . The fuse pattern  123   f  may include a fuse conductive pattern  119   f  and a fuse capping pattern  121   f , which may be sequentially stacked. The fuse conductive pattern  119   f  may include a barrier pattern  113 ′ and a metal pattern  115 ′ which are stacked. An anti-reflection pattern  117 ′ may be further provided on the metal pattern  115 ′. The barrier pattern  113 ′, the metal pattern  115 ′, and the anti-reflection pattern  117 ′ may be formed to respectively include a titanium nitride layer, an aluminum layer, and a titanium nitride layer. The fuse capping pattern  121   f  may be a silicon nitride layer. First and second intermediate interconnection patterns  123   a  and  123   b  are disposed on the lower insulating layer  105  to cover the first and second lower interconnection contact plugs  111   a ′ and  111   b ′. The first and second intermediate interconnection patterns  123   a  and  123   b  may further be formed to be at approximately the same level as the fuse pattern  123   f . The first and second intermediate interconnection patterns  123   a  and  123   b  are also disposed at both sides of the fuse pattern  123   f . The first and second intermediate interconnection patterns  123   a  and  123   b  may be formed of the same or similar material as the fuse pattern  123   f . That is, the first intermediate interconnection pattern  123   a  may include a stacked pattern of a first intermediate interconnection  11   9   a  and a first interconnection capping pattern  121   a  disposed the first intermediate interconnection  119   a . In the same way, the second intermediate interconnection pattern  123   b  may include a stacked pattern of a second intermediate interconnection  119   b  and a second interconnection capping pattern  121   b  disposed the second intermediate interconnection  119   b . The first and second intermediate interconnections  119   a  and  119   b  may further be formed of the same or similar material as the fuse conductive pattern  119   f , and the first and second interconnection capping patterns  121   a  and  121   b  may be formed of a similar material as the fuse capping pattern  121   f . That is, the first and second intermediate interconnections  119   a  and  119   b  may each include a barrier pattern  113 ′, a metal pattern  115 ′, and an anti reflection pattern  117 ′.  
      An inter-metal dielectric layer  125  is provided to cover the fuse pattern  123   f , the first and second intermediate interconnection patterns  123   a  and  123   b , and the lower insulating layer  105 . First and second intermediate interconnection contact holes ( 131   ah  and  131   bh  of  FIG. 1 ) are respectively formed through the inter-metal dielectric layer  125  and the first and second interconnection capping patterns  121   a  and  121   b  to respectively expose the first and second intermediate interconnections  119   a  and  119   b . First and second intermediate interconnection contact plugs  131   a  and  131   b  are disposed to respectively fill the first and second intermediate interconnection contact holes  131   ah  and  131   bh . Each of the first and second intermediate interconnection contact plugs  131   a  and  131   b  may include a contact barrier pattern  127 ′ and a contact pattern  129 ′ surrounded by the contact barrier pattern  127 ′. First and second upper interconnections  139   a  and  139   b  are disposed on the inter-metal dielectric layer  125  to cover the first and second intermediate interconnection contact plugs  131   a  and  131   b , respectively. Each of the first and second upper interconnections  139   a  and  139   b  may include a stacked pattern of a barrier pattern  133 ′ and a metal pattern  135 ′. In addition, each of the first and second upper interconnections  139   a  and  139   b  may further include an anti-reflection pattern  137 ′ disposed on the metal pattern  135 ′. The barrier pattern  133 ′, the metal pattern  135 ′, and the anti-reflection pattern  137 ′ may respectively include a titanium nitride layer, an aluminum layer, and a titanium nitride layer. A passivation layer  147  is provided to cover the first and second upper interconnections  139   a  and  139   b . The passivation layer  147  may include a stacked layer of an upper passivation layer  145  including a plasma nitride layer and a lower passivation layer  143  including a plasma oxide layer. The passivation layer  147  and the inter-metal dielectric layer  125  may constitute an upper insulating layer  148 . A fuse window  149   fw  is disposed through the upper insulating layer  148 , i.e., the passivation layer  147  and the inter-metal dielectric layer  125  to expose the fuse pattern  123   f . A fuse spacer  151   s  may be provided on sidewalls of the fuse pattern  123   f  exposed by the fuse window  149   fw . In addition, a fuse window spacer  151   s ′ may be provided on sidewalls of the fuse window  149   fw . The fuse spacer  151   s  and the fuse window spacer  151   s ′ may be formed of a silicon nitride layer.  
      In one embodiment of the present invention, the fuse conductive pattern  119   f  is surrounded by the fuse capping pattern  121   f  and the fuse spacer  151   s  in order to protect it from damage from outside moisture. Moreover, a fuse window spacer  151   s ′ is formed on sidewalls of the fuse window  149   fw  to prevent outside moisture from getting into an inner circuit though the upper insulating layer  148 .  
      A lower bonding pad pattern  123   p  may be formed to be at approximately the same level as the first and second intermediate interconnection patterns  123   a  and  123   b  and the fuse pattern  123   f  on the lower insulating layer  105 . The lower bonding pad pattern  123   p  may be a stacked pattern of a lower bonding pad pattern  119   p  and a pad capping pattern  121   p  disposed thereon. Here, the lower bonding pad  119   p  and the pad capping pattern  121   p  may be formed of a similar material as the fuse conductive pattern  119   f  of the fuse pattern  123   f  and the fuse capping pattern  121   f . A pad contact hole ( 131   ph  of  FIG. 1 ) is formed through the inter-metal dielectric layer  125  and the pad capping pattern  121   p  to expose the lower bonding pad  119   p , and a pad contact plug  131   p  is provided to fill the pad contact hole  131   ph . The pad contact plug  131   p  may be formed of a similar material as the first and second intermediate interconnection contact plugs  131   a  and  131   b . An upper bonding pad  139   p  is disposed on the inter-metal dielectric layer  125  to cover the pad contact plug  131   p . The upper bonding pad  139   p  may be formed to be at approximately the same level as the first and second upper interconnections  139   a  and  139   b , and formed of a similar material as the first and second upper interconnections  139   a  and  139   b . The upper bonding pad  139   p  may also be covered with the passivation layer  147  like the first and second upper interconnections  139   a  and  139   b . The lower bonding pad pattern  123   p , the pad contact plug  131   p , and the upper bonding pad  139   p  constitute a bonding pad  141 .  
      In another embodiment, the bonding pad  141  may not include the lower bonding pad pattern  123   p  and the pad contact plug  131   p . That is, the bonding pad  141  may be formed of only the upper bonding pad  139   p.    
      A pad window  149   pw  may be formed through the passivation layer  147  to expose the upper bonding pad  139   p . A pad window spacer  151   s ″ may be provided on sidewalls of the pad window. The pad window spacer  151   s ″ may be formed of the same or similar material as the fuse spacer  151   s . That is, when the fuse spacer  151   s  is formed of a silicon nitride layer, the pad window spacer  151   s ″ may also be formed of a silicon nitride layer.  
       FIGS. 2 through 10  are cross-sectional views taken along line I-I′ of  FIG. 1 , which illustrate a method of fabricating a semiconductor device according to an exemplary embodiment of the present invention.  
      Referring to  FIGS. 1 and 2 , an insulating layer  101  is formed on a surface of a semiconductor substrate  100 . When the semiconductor device is a semiconductor memory device, a word line (not illustrated) may be provided under the insulating layer  101 . A lower interconnection layer is formed on the insulating layer  101 . The lower interconnection layer may be formed of a tungsten layer or a tungsten silicide layer. The lower interconnection layer is patterned to form first and second lower interconnections  103   a  and  103   b  which may be spaced apart from each other on the insulating layer  101 , The first and second lower interconnections  103   a  and  103   b  may be disposed in a substantially straight line. Bit lines (not illustrated) may be simultaneously formed on the insulating layer  101  during the formation of the first and second lower interconnections  103   a  and  103   b . Subsequently, a lower insulating layer  105  is formed on the substrate having the first and second lower interconnections  103   a  and  103   b . The lower insulating layer  105  may be formed of a silicon oxide layer.  
      Referring to  FIGS. 1 and 3 , the lower insulating layer  105  is patterned to form first and second fuse contact holes ( 111   ah  and  111   bh  of  FIG. 1 ) and first and second lower interconnection contact holes ( 111   ah ′ and  111   bh ′ of  FIG. 1 ) exposing both ends of the first and second lower interconnections  103   a  and  103   b . A contact barrier layer and a contact layer may be sequentially formed on the semiconductor substrate having the contact holes  111   ah ,  111   bh ,  111   ah ′, and  111   bh ′. The contact barrier layer may be formed of a titanium nitride layer, and the contact layer may be formed of a tungsten layer. Before forming the contact barrier layer, an ohmic layer such as a titanium layer may be formed. Further, the lower insulating layer  105  may be exposed by etching back the contact barrier layer and the contact layer. As a result of this etch back, first and second fuse contact plugs  111   a  and  111   b  are respectively formed in the first and second fuse contact holes  111   ah  and  111   bh , and first and second lower interconnection contact holes  111   a ′ and  111   b ′ are respectively formed in the first and second lower interconnection contact plugs  111   ah ′ and  111   bh ′. The first and second fuse contact plugs  111   a  and  111   b  and the first and second lower interconnection contact plugs  111   a ′  111   b ′ include a contact barrier pattern  107 ′ and a contact pattern  109 ′ surrounded by the contact barrier pattern  107 ′.  
      In another embodiment, an etch stop layer (not illustrated) such as a silicon nitride layer may be formed on the lower insulating layer  105  before forming the first and second fuse contact holes  111   ah  and  111   bh  and the first and second lower interconnection contact holes  111   ah ′ and  111   bh ′. In this case, the contact plugs  111   a ,  111   b ,  111   a ′, and  111   b ′ are disposed through the etch stop layer as well as through the lower insulating layer  105 .  
      A conductive layer  119  is formed on the lower insulating layer  105  having the contact plugs  111   a ,  111   b ,  111   a ′, and  111   b ′. The conductive layer  119  may include a barrier layer  113  and a metal layer  115 , which are sequentially stacked. The barrier layer  113  and the metal layer  115  may respectively include a titanium nitride layer and an aluminum layer. An anti-reflection layer  117  may be further formed on the metal layer  115 . The anti-reflection layer  117  may be a titanium nitride layer. The anti-reflection layer  117  may serve to inhibit corrosion of the metal layer  115  and prevent patterning defects due to diffused reflection in a photolithographic process. A capping layer  121  is formed on the conductive layer  119 . The capping layer  121  may be formed of a silicon nitride layer.  
      Referring to  FIGS. 1 and 4 , the capping layer  121  and the conductive layer  119  are patterned to form a fuse pattern  123   f , first and second intermediate interconnection patterns  123   a  and  123   b , and a lower bonding pad pattern  123   p . The fuse pattern  123   p , the first and second intermediate interconnection patterns  123   a  and  123   b , and the lower bonding pad pattern  123   p  may thus be formed of a stacked pattern of the same material. The fuse pattern  123   f  includes a fuse conductive pattern  119   f  and a fuse capping pattern  121   f  formed on the fuse conductive pattern  119   f . The first intermediate interconnection pattern  123   a  includes a first intermediate interconnection  119   a  and a first interconnection capping pattern  121   a  formed on the first intermediate interconnection  119   a . Likewise, the second intermediate interconnection pattern  123   b  includes a second intermediate interconnection  119   b  and a second interconnection capping pattern  121   b  formed on the second intermediate interconnection  119   b . The lower bonding pad pattern  123   p  includes a lower bonding pad  119   p  and a pad capping pattern  121   p  formed on the lower bonding pad  119   p . The fuse conductive pattern  119   f  may be a stacked pattern of a barrier pattern  113 ′ and a metal pattern  115 ′, or a stacked pattern of the barrier pattern  113 ′, the metal pattern  115 ′, and an anti-reflection pattern  117 ′.  
      The fuse pattern  123   f  may be formed to cover first and second fuse contact plugs  111   a  and  111   b  on a region between the first and second lower interconnections  103   a  and  103   b . The first and second intermediate interconnection patterns  123   a  and  123   b  may be formed at both sides of the fuse pattern  123   f  to cover each of the first and second lower interconnection contact plugs  111   a ′ and  111   b ′. The lower bonding pad pattern  123   p  may be spaced apart from the fuse pattern  123   f  and the first and second intermediate interconnection patterns  123   a  and  123   b.    
      Referring to  FIGS. 1 and 5 , an inter-metal dielectric layer  125  is formed on the semiconductor substrate  100  having the fuse pattern  123   f , the first and second intermediate interconnection patterns  123   a  and  123   b , and the lower bonding pad pattern  123   p . The inter-metal dielectric layer  125 , the first and second interconnection capping patterns  121   a  and  121   b , and the pad capping pattern  121   p  may be patterned to respectively form first and second intermediate interconnection contact holes ( 131   ah  and  131   bh  of  FIG. 1 ) and a pad contact hole ( 131   ph  of  FIG. 1 ), which respectively expose top surfaces of the first and second intermediate interconnections  119   a  and  119   b  and the lower bonding pad  119   p . The first and second intermediate interconnection contact holes  131   ah  and  131   bh  and the pad contact hole  131   ph  may be filled with first and second intermediate interconnection contact plugs  131   a  and  131   b  and a pad contact plug  131   p , respectively. Each of the first and second intermediate interconnection contact plugs  131   a  and  131   b  and the pad contact plug  131   p  may include a contact barrier pattern  127 ′ and a contact pattern  129 ′ surrounded by the contact barrier pattern  127 ′. The contact barrier pattern  127 ′ and the contact pattern  129 ′ may be formed of a titanium nitride layer and a tungsten layer, respectively.  
      Referring to  FIGS. 1 and 6 , an upper interconnection layer is formed on the substrate having the contact plugs  131   a ,  131   b , and  131   p . The upper interconnection layer may include a barrier layer and a metal layer which are sequentially stacked. In addition, the upper interconnection layer may further include an anti-reflection layer on the metal layer. The barrier layer, the metal layer, and the anti-reflection layer may be formed of a titanium nitride layer, an aluminum layer, and a titanium nitride layer, respectively. The upper interconnection layer may then be patterned to form first and second upper interconnections  139   a  and  139   b  and an upper bonding pad  139   p . Each of the first and second upper interconnections  139   a  and  139   b  and the upper bonding pad  139   p  may include a barrier pattern  133 ′, a metal pattern  135 ′, and an anti-reflection pattern  137 ′. The first and second upper interconnections  139   a  and  139   b  may be formed to cover the first and second intermediate interconnection contact plugs  131   a  and  131   b , respectively. The first upper interconnection  139   a  may thus be electrically connected to the first intermediate interconnection  119   a  by the first intermediate interconnection contact plug  131   a , and the second upper interconnection  139   b  may be electrically connected to the second intermediate interconnection  119   b  by the second intermediate interconnection contact plug  131   b . The upper bonding pad  139   p  may be electrically connected to the lower bonding pad  119   p  via the pad contact plug  131   p . The lower bonding pad pattern  123   p , the pad contact plug  131   p , and the upper bonding pad  139   p  constitute a bonding pad  141 .  
      Referring to  FIGS. 1 and 7 , a lower passivation layer  143  is formed on the surface of the semiconductor substrate  100  having the first and second upper interconnections  139   a  and  139   b , and the upper bonding pad  139   p . The lower passivation layer  143  may be formed of a plasma oxide layer. An upper passivation layer  145  is formed on the lower passivation layer  143 . The upper passivation layer  145  may be formed of a plasma nitride layer. The upper passivation layer  145  may serve to inhibit outside moisture from penetrating into an integrated circuit formed on the semiconductor substrate  100 , and the lower passivation layer  143  may serve as a buffer layer to relieve stress on the upper passivation layer  145 . The lower passivation layer  143  and the upper passivation layer  145  constitute a passivation layer  147 . The inter-metal dielectric layer  125  and the passivation layer  147  constitute an upper insulating layer  148 .  
      Referring to  FIGS. 1 and 8 , a pad window  149   pw  is formed to expose the top surface of the upper bonding pad  139   p  and a fuse window  149   fw  is formed to expose the fuse pattern  123   f  through the upper insulating layer  148 . To be specific, openings may be formed at areas where the fuse window  149   fw  and the pad window  149   pw  are to be formed by patterning the upper passivation layer  145 . The lower passivation layer  143  and the inter-metal dielectric layer  125  may then be etched using the upper passivation layer  145  having the opening as an etching mask. Here, the fuse capping pattern  121   f  is preferably formed of a material having an etching selectivity with respect to the inter-metal dielectric layer  125  and the lower passivation layer  143 . For example, when the lower passivation layer  143  and the inter-metal dielectric layer  125  are formed of an oxide layer, the fuse capping pattern  121   f  may be formed of a silicon nitride layer. Therefore, the top surface of the fuse conductive pattern  119   f  is protected by the fuse capping pattern  121   f . While forming the fuse window  149   fw , the pad window  149   pw  exposing the top surface of the upper bonding pad  139   p  may be simultaneously formed. Here, the uppermost layer of the upper bonding pad  139   p  is formed of the anti-reflection pattern  137 ′ and may be removed by over-etching.  
      In the present invention, the fuse window  149   fw  and the pad window  149   pw  are formed by performing a patterning process once, thereby simplifying the overall process. Also, a fuse capping pattern  121   f  is the uppermost layer of the fuse pattern  123   f , which may protect the fuse conductive pattern  119   f  from damage while the fuse window  149   fw  is formed.  
      Referring to  FIGS. 1, 9 , and  10 , a fuse spacer layer  151  is formed on the semiconductor substrate  100  having the fuse window  149   fw  and the pad window  149   pw . The fuse spacer layer  151  may be anisotropically etched, thereby forming a fuse spacer layer  151   s  covering sidewalls of the fuse pattern  123   f , a fuse window spacer  151   s ′ covering sidewalls of the fuse window  149   fw  and a pad window spacer  151   s ″ covering sidewalls of the pad window  149   pw . The spacers  151   s ,  151   s ′, and  151   s ″ may be formed of a silicon nitride layer. The fuse spacer  151   s  is formed to cover sidewalls of the fuse pattern  123   f  exposed by the fuse window  149   fw , thereby preventing corrosion of the fuse conductive pattern  123   f  due to outside moisture. According to the present invention, the fuse window spacer  151   s ′ and the pad window spacer  151   s ″ are also formed on sidewalls of the fuse window  149   fw  and the pad window  149   pw , thereby preventing outside moisture from penetrating into an inner circuit.  
      To protect the semiconductor chip, a polyimide layer (not shown) may be further formed on the substrate having the fuse spacer  151   s , the fuse window spacer  151   s ′ and the pad window spacer  151   s″.    
      According to the present invention as described above, a capping pattern is formed to protect the top surface of the fuse before forming a fuse window, thereby enabling simultaneous formation of a pad window exposing the fuse window and a pad. In addition, spacers are also formed on sidewalls of the fuse window and the pad window, not only on sidewalls of the fuse, thereby protecting an inner circuit from damage due to outside moisture which may permeate through the fuse window and the pad window.  
      Exemplary embodiments of the present invention have been disclosed herein and, although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purpose of limitation. Accordingly, it will be understood by those of ordinary skill in the art that various changes in form and details may be made without departing from the spirit and scope of the present invention as set forth in the following claims.