Patent Publication Number: US-2010110110-A1

Title: Driving circuit

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a driving circuit, and more particularly, to a source driver applied to an LCD panel, the driving circuit is capable of reducing the amount of required output buffers, so as to reduce area of the driving circuit efficiently and lower the production cost. 
     2. Description of the Prior Art 
       FIG. 1  shows a simplified block diagram of a source driver  100  applied to an LCD panel in accordance with a prior art. As shown in  FIG. 1 , the source driver  100  comprises: a plurality of signal output terminals S 1 ˜Sn, a data signal generating module  110 , a gray level reference voltage generating module  120 , a digital-to-analog converter (DAC)  130 , and an output buffer and switch module  140 . The data signal generating module  110  is utilized for generating a plurality of digital data signals D 1 ˜Dn, and the gray level reference voltage generating module  120  is utilized for generating a plurality of gray level reference voltages. The DAC  130  is coupled to the data signal generating module  110  and the gray level reference voltage generating module  120 , and is utilized for generating a plurality of voltage signals A 1 ˜An corresponding to the plurality of digital data signals D 1 ˜Dn in accordance with the plurality of gray level reference voltages, respectively. The DAC  130  comprises a plurality of analog output terminals (not shown), respectively for outputting the plurality of voltage signals A 1 ˜An. The data signal generating module  110  further comprises: a shift register, a line latch, and a level shifter. The data signal generating module  110  is well known to those of average skill in this art, and thus further explanation of the details and operations about the data signal generating module  110  are omitted herein for the sake of brevity. 
       FIG. 2  shows a simplified block diagram of the output buffer and switch module  140  in  FIG. 1 . As shown in  FIG. 2 , the output buffer and switch module  140  comprises: a plurality of switch elements SWg 1 ˜SWgn, a plurality of switch elements SWp 1 ˜SWpn, and a plurality of output buffers B 1 ˜Bn. The plurality of switch elements SWg 1 ˜SWgn and the plurality of switch elements SWp 1 ˜SWpn are respectively coupled between the plurality of voltage signals A 1 ˜An of the DAC  130  and the plurality of signal output terminals S 1 ˜Sn. The output buffers B 1 ˜Bn are respectively coupled between the plurality of voltage signals A 1 ˜An of the DAC  130  and the plurality of switch elements SWp 1 ˜SWpn. In addition, the plurality of switch elements SWg 1 ˜SWgn are controlled by switch control signals GM_EN, respectively. The plurality of switch elements SWp 1 ˜SWpn are controlled by switch control signals PM_EN, respectively. 
     Next, please refer to  FIG. 3 .  FIG. 3  shows a timing diagram of the switch control signals PB_EN and the switch control signal GM_EN and a voltage level variation diagram of the plurality of signal output terminals S 1 ˜Sn during the two time periods T 1 ˜T 2 . The plurality of switch elements SWg 1 ˜SWgn and the plurality of switch elements SWp 1 ˜SWpn all are N-type FETs (such as NMOSFETs), and thus, as shown in  FIG. 3 , during the time period T 1 , the switch control signal PB_EN 1  is in a high logic level to conduct the plurality of switch elements SWp 1 ˜SWpn, and the switch control signal GM_EN is in a low logic level to not conduct the switch elements SWg 1 ˜SWgn. In this way, the plurality of voltage signals A 1 ˜An can pull up the voltage level of the plurality of signal output terminals S 1 ˜Sn from VGSx 1 ˜VGSxn to near VGSy 1 ˜VGSyn via the plurality of output buffers B 1 ˜Bn, respectively. Next, during the time period T 2 , the switch control signal PB_EN 1  becomes to be in the low logic level to not conduct the plurality of switch elements SWp 1 ˜SWpn, and the switch control signal GM_EN becomes to be in the high logic level to conduct the plurality of switch elements SWg 1 ˜SWgn. In this way, the voltage levels of the signal output terminals S 1 ˜Sn can be directly calibrated by the plurality of voltage signals A 1 ˜An (i.e. gray level reference voltage) to be VGSy 1 ˜VGSyn, respectively. 
     However, since each signal output terminal of the plurality of signal output terminals S 1 ˜Sn requires an output buffer in this prior art, it results in a over large amount of the required output buffers, and let the source driver  100  has a over large area, and it is not able to reduce the production cost of the source driver  100 . 
     SUMMARY OF THE INVENTION 
     It is therefore one of the objectives of the present invention to provide a driving circuit capable of reducing the amount of required output buffers to reduce area of the driving circuit efficiently and lower the production cost, so as to solve the above problem. 
     In accordance with an embodiment of the present invention, a driving circuit is disclosed. The driving circuit comprises: a plurality of signal output terminals, a data signal generating module, a gray level reference voltage generating module, a digital-to-analog converter (DAC), a first multiplex output module, an output buffer, a second multiplex output module, and a switch module. The data signal generating module is utilized for generating a plurality of digital data signals. The gray level reference voltage generating module is utilized for generating a plurality of gray level reference voltages. The DAC is coupled to the data signal generating module and the gray level reference voltage generating module, and is utilized for generating a plurality of voltage signals corresponding to the plurality of digital data signals in accordance with the plurality of gray level reference voltages, respectively. The first multiplex output module has a first output terminal and a plurality of first input terminals, wherein the plurality of first input terminals respectively receive the plurality of voltage signals, and the first multiplex output module selects a first specific voltage signal from the plurality of voltage signals during a first time period and outputs the first specific voltage signal via the first output terminal. The output buffer is coupled to the first output terminal, and is utilized for generating a first specific driving signal in accordance with the first specific voltage signal. The second multiplex output module has a plurality of second output terminals and a second input terminal, wherein the plurality of second output terminals are respectively coupled to the plurality of signal output terminals, the second input terminal receives the first specific driving signal, and the second multiplex output module outputs the first specific driving signal via a first specific output terminal from the plurality of second output terminals to a first specific signal output terminal. The switch module is coupled between the DAC and the plurality of signal output terminals, and is utilized for outputting the first specific voltage signal to the first specific signal output terminal during a second time period different from the first time period. 
     Briefly summarized, the driving circuit disclosed by the present invention is capable of reducing the amount of required output buffers, so as to reduce area of the driving circuit efficiently and lower the production cost. 
     These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  shows a simplified block diagram of a source driver applied to an LCD panel in accordance with a prior art. 
         FIG. 2  shows a simplified block diagram of the output buffer and switch module in  FIG. 1 . 
         FIG. 3  shows a timing diagram of the switch control signals PB_EN and the switch control signal GM_EN and a voltage level variation diagram of the plurality of signal output terminals S 1 ˜Sn during the two time periods T 1 ˜T 2 . 
         FIG. 4  shows a simplified block diagram of a source driver applied to an LCD panel in accordance with an embodiment of the present invention. 
         FIG. 5  shows a simplified block diagram of the first multiplex output module in  FIG. 4 . 
         FIG. 6  shows a simplified block diagram of the second multiplex output module in  FIG. 4 . 
         FIG. 7  shows a simplified block diagram of the switch module in  FIG. 4 . 
         FIG. 8  shows a timing diagram of three switch control signals PB_EN 1 ˜PB_EN 3  and three switch control signals GM_EN 1 ˜GM_EN 3  and a voltage level variation diagram of three signal output terminals S 1 ˜S 3  during the four time periods T 1 ˜T 4 . 
         FIG. 9  shows a simplified block diagram of the source driver  400  during the time period T 1 . 
         FIG. 10  shows a simplified block diagram of the source driver  400  during the time period T 2 . 
         FIG. 11  shows a simplified block diagram of the source driver  400  during the time period T 3 . 
         FIG. 12  shows a simplified block diagram of the source driver  400  during the time period T 4 . 
     
    
    
     DETAILED DESCRIPTION 
     Certain terms are used throughout the following description and the claims to refer to particular system components. As one skilled in the art will appreciate, manufacturers may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not function. In the following discussion and in the claims, the terms “include”, “including”, “comprise”, and “comprising” are used in an open-ended fashion, and thus should be interpreted to mean “including, but not limited to . . . ” The terms “couple” and “coupled” are intended to mean either an indirect or a direct electrical connection. Thus, if a first device couples to a second device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections. 
     Please refer to  FIG. 4 .  FIG. 4  shows a simplified block diagram of a source driver  400  applied to an LCD panel in accordance with an embodiment of the present invention. As shown in  FIG. 4 , the source driver  400  comprises: a plurality of signal output terminals S 1 ˜Sn, a data signal generating module  410 , a gray level reference voltage generating module  420 , a digital-to-analog converter (DAC)  430 , a first multiplex output module  440 , an output buffer  450 , a second multiplex output module  460 , and a switch module  470 . The data signal generating module  410  is utilized for generating a plurality of digital data signals D 1 ˜Dn, and the gray level reference voltage generating module  420  is utilized for generating a plurality of gray level reference voltages. The DAC  430  is coupled to the data signal generating module  410  and the gray level reference voltage generating module  420 , and is utilized for generating a plurality of voltage signals A 1 ˜An corresponding to the plurality of digital data signals D 1 ˜Dn in accordance with the plurality of gray level reference voltages, respectively. The DAC  430  comprises a plurality of analog output terminals (not shown), respectively for outputting the plurality of voltage signals A 1 ˜An. 
     The first multiplex output module  440  has a first output terminal O and a plurality of first input terminals I 1 ˜In, wherein the plurality of first input terminals I 1 ˜In respectively receive the plurality of voltage signals A 1 ˜An, and the first multiplex output module  440  selects a first specific voltage signal (such as A 1 ) from the plurality of voltage signals A 1 ˜An during a first time period and outputs the first specific voltage signal via the first output terminal. The output buffer  450  is coupled to the first output terminal O, and is utilized for generating a first specific driving signal (not shown) in accordance with the first specific voltage signal. The second multiplex output module  460  has a plurality of second output terminals O 1 ˜On and a second input terminal I, wherein the plurality of second output terminals O 1 ˜On are respectively coupled to the plurality of signal output terminals S 1 ˜Sn, the second input terminal I receives the first specific driving signal, and the second multiplex output module  460  outputs the first specific driving signal via a first specific output terminal (such as O 1 ) from the plurality of second output terminals O 1 ˜On to a first specific signal output terminal (such as S 1 ). The switch module  470  is coupled between the DAC  430  and the plurality of signal output terminals S 1 ˜Sn, and is utilized for outputting the first specific voltage signal to the first specific signal output terminal during a second time period different from the first time period. In the meantime, the first multiplex output module  440  will select a second specific voltage signal (such as A 2 ) different from the first specific voltage signal from the plurality of voltage signals A 1 ˜An during the second time period and outputting the second specific voltage signal via the first output terminal O, and the output buffer  450  will generate a second specific driving signal (not shown) in accordance with the second specific voltage signal to the second input terminal I of the second multiplex output module  460  during the second time period; and the second multiplex output module  460  will output the second specific driving signal via a second specific output terminal (such as O 2 ) different from the first specific output terminal from the plurality of second output terminals O 1 ˜On to a second specific signal output terminal (such as S 2 ). 
     Please refer to  FIG. 5 .  FIG. 5  shows a simplified block diagram of the first multiplex output module  440  in  FIG. 4 . As shown in  FIG. 5 , the first multiplex output module  440  comprises a plurality of switch elements SW 11 ˜SW 1   n , respectively coupled between the plurality of first input terminals I 1 ˜In and the first output terminal O, wherein the plurality of switch elements SW 11 ˜SW 1   n  are controlled by switch control signals PB_EN 1 ˜PB_ENn, respectively. 
     Please refer to  FIG. 6 .  FIG. 6  shows a simplified block diagram of the second multiplex output module  460  in  FIG. 4 . As shown in  FIG. 6 , the second multiplex output module  460  comprises a plurality of switch elements SW 21 ˜SW 2   n , respectively coupled between the plurality of second output terminals O 1 ˜In and the second input terminal I, wherein the plurality of switch elements SW 21 ˜SW 2   n  are controlled by switch control signals PB_EN 1 ˜PB_ENn, respectively. 
     Please refer to  FIG. 7 .  FIG. 7  shows a simplified block diagram of the switch module  470  in  FIG. 4 . As shown in  FIG. 7 , the switch module  470  comprises a plurality of switch elements SW 31 ˜SW 3   n , respectively coupled between the plurality of voltage signals A 1 ˜An and the plurality of signal output terminals S 1 ˜Sn, wherein the plurality of switch elements SW 31 ˜SW 3   n  are controlled by switch control signals GM_EN 1 ˜GM_ENn, respectively. 
     For example, when n=3, Please refer to  FIG. 8 ,  FIG. 9 ,  FIG. 10 ,  FIG. 11 , and  FIG. 12  together.  FIG. 8  shows a timing diagram of three switch control signals PB_EN 1 ˜PB_EN 3  and three switch control signals GM_EN 1 ˜GM_EN 3  and a voltage level variation diagram of three signal output terminals S 1 ˜S 3  during the four time periods T 1 ˜T 4 .  FIG. 9  shows a simplified block diagram of the source driver  400  during the time period T 1 .  FIG. 10  shows a simplified block diagram of the source driver  400  during the time period T 2 .  FIG. 11  shows a simplified block diagram of the source driver  400  during the time period T 3 .  FIG. 12  shows a simplified block diagram of the source driver  400  during the time period T 4 . 
     In this embodiment, the three switch elements SW 11 ˜SW 13 , the three switch elements SW 21 ˜SW 23 , and the three switch elements SW 31 ˜SW 33  all are N-type FETs (such as NMOSFETs). Thus, as shown in  FIG. 8  and  FIG. 9 , during the time period T 1 , the switch control signal PB_EN 1  is in a high logic level to conduct the switch element SW 11  and the switch element SW 21 , and the other switch control signal PB_EN 2 , switch control signal PB_EN 3 , and the switch control signals GM_EN 1  GM_EN 3  are in a low logic level to not conduct the switch element SW 12 , the switch element SW 13 , the switch element SW 22 , the switch element SW 23 , and the switch elements SW 31 ˜SW 33 . In this way, the voltage signal A 1  can pull up the voltage level of the signal output terminal S 1  from VGSx 1  to near VGSy 1  via the output buffer  450 . 
     Next, as shown in  FIG. 8  and  FIG. 10 , during the time period T 2 , the switch control signal PB_EN 1  becomes to be in the low logic level to not conduct the switch element SW 11  and the switch element SW 21 , and the switch control signal PB_EN 2  and the switch control signal GM_EN 1  become to be in the high logic level to conduct the switch element SW 12 , the switch element SW 22 , and the switch element SW 31 , and the other switch control signal PB_EN 3 , the switch control signal GM_EN 2 , and the switch control signal GM_EN 3  are in the low logic level to not conduct the switch element SW 13 , the switch element SW 23 , and the switch elements SW 32 ˜SW 33 . In this way, the voltage signal A 2  can pull up the voltage level of the signal output terminal S 2  from VGSx 2  to near VGSy 2  via the output buffer  450 , and the voltage level of the signal output terminal S 1  can be directly calibrated by the voltage signal A 1  (i.e. a gray level reference voltage) to be VGSy 1 . 
     Next, as shown in  FIG. 8  and  FIG. 12 , during the time period T 4 , the switch control signal PB_EN 1  maintains to be in the low logic level to not conduct the switch element SW 11  and the switch element SW 21 , and the switch control signal GM_EN 1  maintains to be in the high logic level to conduct the switch element SW 31 , and the switch control signal PB_EN 2  maintains to be in the low logic level to not conduct the switch element SW 12  and the switch element SW 22 , and the switch control signal GM_EN 2  maintain to be in the high logic level to conduct the switch element SW 32 , and the switch control signal PB_EN 3  becomes to be in the low logic level to not conduct the switch element SW 13  and the switch element SW 23 , and the switch control signal GM_EN 3  becomes to be in the high logic level to conduct the switch element SW 33 . In this way, the voltage level of the signal output terminal S 3  can be directly calibrated by the voltage signal A 3  (i.e. a gray level reference voltage) to be VGSy 3 , and the voltage level of the signal output terminal S 1  can be maintained by the voltage signal A 1  to be VGSy 1 , and the voltage level of the signal output terminal S 2  can be maintained by the voltage signal A 2  to be VGSy 2 . In addition, please note that the above embodiment is only for an illustrative purpose and is not meant to be a limitation of the present invention. For example, n can be equal to an arbitrary positive integer. 
     Briefly summarized, the source driver disclosed by the present invention is capable of reducing the amount of required output buffers, so as to reduce area of the driving circuit efficiently and lower the production cost. 
     Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention.