Patent Publication Number: US-6982500-B2

Title: Power-down scheme for an on-die voltage differentiator design

Description:
COPYRIGHT NOTICE 
   Contained herein is material that is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction of the patent disclosure by any person as it appears in the Patent and Trademark Office patent files or records, but otherwise reserves all rights to the copyright whatsoever. 
   FIELD OF THE INVENTION 
   The present invention relates to integrated circuits; more particularly, the present invention relates to generating multiple power supply voltages on an integrated circuit. 
   BACKGROUND 
   Recently, power consumption has become an important concern for high performance computer systems. Consequently, low power designs have become significant for present-day very large scale integration (VLSI) systems. The most effective way to reduce power dissipation in an integrated circuit (IC) is by decreasing the power supply voltage (V CC ) at the IC. 
   In order to simultaneously achieve high performance and low power, multi-V CC  design, various techniques have been developed. However, due to the high cost of packaging and routing, it is typically difficult to generate multi-V CC  designs using traditional off-chip voltage regulators. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the invention. The drawings, however, should not be taken to limit the invention to the specific embodiments, but are for explanation and understanding only. 
       FIG. 1  is a block diagram of one embodiment of an integrated circuit; 
       FIG. 2  is a block diagram of one embodiment of a circuit block; and 
       FIG. 3  illustrates one embodiment of a voltage differentiator. 
   

   DETAILED DESCRIPTION 
   A mechanism to power down one or more circuit blocks on an integrated circuit (IC) using on-die voltage differentiators is described. In the following description, numerous details are set forth. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring the present invention. 
   Reference in the specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. The appearances of the phrase “in one embodiment” in various places in the specification are not necessarily all referring to the same embodiment. 
     FIG. 1  is a block diagram of one embodiment of an IC  100 . According to one embodiment, IC  100  is partitioned into twenty-five circuit blocks  110 . In a further embodiment, each circuit block  110  includes a voltage differentiator  120 . Each voltage differentiator  120  generates a local power supply (V CC— local) from an external power supply (V CC— global). In one embodiment, differentiator  120  switches off V CC— local whenever the particular circuit block  110  in which the differentiator  120  is included is operating in a standby state. One of ordinary skill in the art will appreciate that other quantities of circuit blocks  110  may be implemented within IC  100 . 
     FIG. 2  is a block diagram of one embodiment of a circuit block  110 . Circuit block  110  includes voltage differentiator  120 , a functional unit block (FUB)  230  and a control module  250 . FUB  230  is coupled to voltage differentiator  120 . In one embodiment, FUB  230  is logic circuitry that may encompass various components within IC  100  (e.g., microprocessor logic, microcontroller logic, memory logic, etc.). FUB  230  is powered by V CC— local received from voltage differentiator  120 . 
   Control module  250  is coupled to voltage differentiator  120  and FUB  230 . Control module determines the operation mode for circuit block  110  based upon the status of FUB  230  circuitry. According to one embodiment, control module  250  transmits a standby signal (SLP) to voltage differentiator  120 . SLP is used to indicate whether FUB  230  is currently in an operating mode, or in a standby mode. 
   If FUB  230  is in an operating mode, control module  250  transmits a high logic level (e.g., logic 1) to voltage differentiator  120 , indicating that V CC— local is to be generated and forwarded to FUB  230 . If, however, FUB  230  is idle, control module  250  transmits a low logic level (e.g., logic 0) to voltage differentiator  120 , indicating that FUB  230  is to be powered down. Thus, V CC— local is not generated, and power is conserved. 
     FIG. 3  illustrates one embodiment of voltage differentiator  120 . Voltage differentiator  120  includes resistors R 1  and R 2  a comparator  350 , an inverter, a not-and (NAND) gate, a PMOS transistor (P) and a capacitor. Resistors R 1  and R 2  are used to generate a reference voltage (V REF ) for comparator  350 . The reference voltage is specified by the equation V REF =R2* V CC /(R 1 +R 2 ). In one embodiment, V REF  may be tuned to a desired voltage at each circuit block  110  by changing the resistance values of resistors R 1  and R 2 . 
   V REF  is received at one input of comparator  350 . Comparator  350  receives a feedback of V CC— local from transistor P at its second input. Comparator  350  compares V REF  to V CC— local. If V CC— local falls below V REF , the output of comparator  350  is activated at logic 0. According to one embodiment, comparator  350  is an operational amplifier. However, one of ordinary skill in the art will recognize that other comparison logic circuitry may be used to implement comparator  350 . 
   The inverter is coupled to the output of comparator  350  and inverts the output value received from comparator  350 . The output of the inverter is coupled to one input of the NAND gate. The NAND gate receives the SLP signal at its second input. Whenever the output of the NAND gate and the SLP signal are both at logic 1, the NAND gate is activated to logic 0. In other embodiments, the inverter may not be included within voltage differentiator  120 . In such embodiments, the NAND gate may be replaced with an and-gate. 
   The gate of transistor P is coupled to the output of the NAND gate. The source of transistor P is coupled to V CC— global, while the drain is coupled to an input of comparator  350 , the capacitor and FUB  230 . Transistor P is activated whenever the NAND gate is activated to logic 0. 
   During the FUB  230  operating mode (e.g., SLP=logic 1), transistor P is activated whenever V CC— local falls below V REF . In particular, comparator  350  senses such a condition and is activated to logic 0. The inverter inverts the logic 0 signal into a logic 1. Thus, the NAND gate is activated to logic 0, activating the gate of transistor P. Transistor P charges the decouple capacitor, increasing V CC— local. If V CC— local is greater than V REF , transistor P is turned off. Consequently, V CC— local is always close to V REF . 
   During the standby mode, the NAND gate is deactivated because of the received SLP value of logic 0. Accordingly, transistor P is turned off. V CC— local will drop and leakage power attributed to circuit block  110  is significantly reduced. 
   The use of on-die voltage differentiators enables the generation of a local power supply voltage for each circuit block within an IC, which reduces the power dissipation. Moreover, the power down (or standby) control mechanism, combined with the on-die voltage differentiators drastically reduces leakage power during idle time for a circuit block. 
   Whereas many alterations and modifications of the present invention will no doubt become apparent to a person of ordinary skill in the art after having read the foregoing description, it is to be understood that any particular embodiment shown and described by way of illustration is in no way intended to be considered limiting. Therefore, references to details of various embodiments are not intended to limit the scope of the claims which in themselves recite only those features regarded as the invention.