Patent Publication Number: US-2009240876-A1

Title: Information processing apparatus, information processing method and storage system

Description:
CROSS-REFERENCES 
     This application relates to and claims priority from Japanese Patent Application No. 2008-076430, filed on Mar. 24, 2008, the entire disclosure of which is incorporated herein by reference. 
     BACKGROUND 
     The present invention relates to information processing technology of an information processing apparatus to be used in a storage system or the like connected to a communication network. 
     Conventionally, an information processing apparatus has been proposed which comprises a processor, a memory, an interface controller, and a system controller for controlling the communication among the processor and the memory and the interface controller. With this information processing apparatus, when transferring data between the memory and the system controller, the system controller determines whether to add an error detection signal for protecting data based on the address of the memory where the data to be transferred will be read and written so as to protect the data (refer to Japanese Patent Laid-Open Publication No. 2007-207062). 
     With this kind of information processing apparatus, there is a type that stores a control program in a main memory, stores a boot program in a flash memory, arranges a chipset or a system controller between a processor and the flash memory, and relays the transfer of data with the chipset or the system controller. In this information processing apparatus, by arranging the chipset or the system controller between the processor and the flash memory, the chipset or the system controller is able to directly access the flash memory. 
     SUMMARY 
     With the foregoing conventional technology, although the chipset or the system controller is able to directly access the flash memory by arranging the chipset or the system controller between the processor and the flash memory, if the specification of the processor or the chipset is changed, the chipset will not be able to directly access the flash memory if the chipset is simply connected to the flash memory. 
     Thus, an object of the present invention is to propose an information processing apparatus, an information processing method and a storage system using this information processing apparatus capable of accessing the flash memory in accordance with the chipset configuration even if the chipset specification is changed. 
     In order to achieve the foregoing object, the present invention arranges a logical control circuit between a chipset and a flash memory, and causes the logical control circuit to execute information conversion processing for accommodating the logical configuration of the chipset and the flash memory when sending and receiving information between the chipset and the flash memory. 
     According to the present invention, the flash memory can be accessed in accordance with the chipset configuration. 
    
    
     
       DESCRIPTION OF DRAWINGS 
         FIG. 1  is a block configuration diagram of a storage system showing the first embodiment of the present invention; 
         FIG. 2  is a block configuration diagram of a logical control circuit; 
         FIG. 3  is a block configuration diagram explaining the relationship of a logical control circuit and a flash memory; 
         FIG. 4  is a flowchart explaining the read/write access to the flash memory; 
         FIG. 5  is a mapping configuration diagram of a flash area in a memory space; 
         FIG. 6  is a configuration diagram explaining the relationship of a logical control circuit and a flash memory in the second embodiment of the present invention; 
         FIG. 7  is a flowchart explaining the working of the second embodiment; 
         FIG. 8  is a diagram explaining the relationship of a linear address and a physical address in a BIOS area; 
         FIG. 9  is a block configuration diagram of a logical control circuit in the third embodiment of the present invention; and 
         FIG. 10  is a flowchart explaining the working of the third embodiment. 
     
    
    
     DETAILED DESCRIPTION 
     An embodiment of the present invention is now explained with reference to the attached drawings.  FIG. 1  is a block configuration diagram of a storage system applying an information processing apparatus according to the present invention. In  FIG. 1 , the storage system  10  comprises controllers  12 ,  14 , and a storage apparatus  16 , and each controller  12 ,  14  is connected to the storage apparatus  16 , and additionally connected to host computers (host systems)  18 ,  20  via a communication network (not shown). 
     The controllers  12 ,  14 , as a dual configuration information processing apparatus, comprise a host controller  22 , a processor (CPU)  24 , a local memory  26 , a chipset  28 , a data transfer controller  30 , a cache memory  32 , a LAN (Local Area Network) controller  34 , a logical control circuit  36 , a flash memory  38 , a SAS (Serial Attached SCSI) controller  40 , and an expander  42 . The host controller  22  is connected to the host computers  18 ,  20 , and the expander  42  is connected to the storage apparatus  16 . The storage apparatus  16  comprises a plurality of nonvolatile storage mediums  44  such as hard disk drives (HDD). Since the controller  12  and the controller  14  are configured the same, the ensuing explanation will focus only on the controller  12 . 
     The host controller  22  in the controller  12  is configured as an interface for controlling the communication with the host computer  18 , and sending and receiving commands to and from the host computer  18 . The processor (CPU)  24  executes processing according to commands from the host computer  18  based on a control program stored in the local memory  26  and a boot program stored in the flash memory  38 , and also controls the operation of the overall controller  12 . 
     The chipset  28  relays, with the processor  24 , the local memory  26 , the flash memory  38  and the data transfer controller  30  as transfer targets, data concerning these transfer targets. 
     The data transfer controller  30  controls the data transfer between the controller  12  and the controller  14  and the data transfer among the respective components in the controller  12 , and is also loaded with a function for dual writing the write data given from the host computer  18  into the cache memory  32  according to a command from the processor  24 . The cache memory  32  configures a storage area for temporarily storing data to be transferred by the data transfer controller  30 . 
     The local memory  26  stores various control programs (microprograms), and is also configured as a storage area for temporarily storing various commands such as read commands and write commands given from the host computer  18 . 
     The SAS controller  40  and the expander  42 , as a communication controller configuring the interface for controlling the communication with the storage apparatus  16 , transfer data controlled by the data transfer controller  30  to the storage apparatus  16 , and also transfer data from the storage apparatus  16  to the data transfer controller  30 . 
     The flash memory  38  stores, in addition to a boot program, programs concerning the initialization and diagnosis of the respective devices required upon booting such devices; for instance, programs concerning BIOS (Basic Input/Output System) (hereinafter referred to as “BIOS programs”). 
     The logic controller  36  is configured as a device, a PLD (Programmable Logic Device) for instance, to be arranged between the chipset  28  and the flash memory  38 , and for executing information conversion processing to accommodate the logical configuration of the chipset  28  and the flash memory  38  when sending and receiving information between the chipset  28  and the flash memory  38 . The logical control circuit  38 , as shown in  FIG. 2 , comprises an LPC (Low Pin Count) bus interface  46 , a bus converter  48 , a flash memory interface  50 , and a general purpose I/O port (General Purpose Input Output)  52 . 
     The bus converter  48 , as shown in  FIG. 3 , as a device loaded with a LPC (Low Pin Count) bus/flash bus conversion function, comprises buffers  54 ,  56 , a control register  58 , an address register  60 , a first data register  62 , a second data register  64 , and buffers  66 ,  68 . 
     When a signal for accessing the flash memory  38  is input from the chipset  28  via the LPC (Low Pin Count) bus  70  and the buffer  54 , the control register  58  creates a control signal for accessing the flash memory  38  to read and write data, and outputs the control signal to the flash memory  38 . 
     The address register  60  converts the memory address (serial address signal) sent by time-sharing as a 4-bit×7 signal from the LPC bus  70  via the buffer  54  into a 24-bit parallel signal, and outputs the converted signal to the flash memory  38 . 
     The first data register  62  converts the data (serial data signal) sent by time-sharing as a 4-bit×2 signal from the LPC bus  70  via the buffer  54  into an 8-bit parallel signal, and outputs the converted signal to the flash memory  38 . 
     Meanwhile, the second data register  64  divides the 8-bit parallel signal sent from the flash memory  38  via buffer  68  into high 4 bits and low 4 bits, and outputs the divided serial data signal to the LPC bus  70  via the buffer  56 . 
     The operation upon performing read/write access to the flash memory  38  using the logical control circuit  36  is now explained with reference to the flowchart of  FIG. 4 . Foremost, when a 28-bit address signal is output from the chipset  28 , the address register  60  of the bus converter  48  retains the 28-bit address signal sent from the chipset  28  (S 1 ). When the bus converter  48  acquires a write command from the chipset  28 , the first data register  62  retains the 8-bit data output from the chipset  28  (S 2 ). 
     The control register  58  thereafter outputs a control signal for write-accessing the flash memory  38 , the address register  60  outputs an address signal for specifying the access target to the flash memory  38 , and the first data register  62  transfers data to be written to the flash memory  38  (S 3 ). The write access to the flash memory  38  is thereby complete. 
     Meanwhile, when the bus converter  48  acquires a read command, as processing according to the read command, the control register  58  outputs a control signal for read-accessing the flash memory  38  to the flash memory  38 , and the address register  60  outputs an address signal for specifying the access target to the flash memory  38  (S 4 ). 
     When the 8-bit data is output from the flash memory  38  in accordance with the read access, the 8-bit data is input to the second data register  60  (S 5 ). The second data register  64  divides the input 8-bit data into high 4-bit data and low 4-bit data, and outputs the divided data to the chipset  28  via the buffer  56  (S 6 ). The read access to the flash memory  38  is thereby complete. 
     According to this embodiment, even in cases where it is not possible to directly connect the chipset  28  and the flash memory  38  in accordance with changes in the specification of the processor  24  and the chipset  28 , since the logical control circuit  36  executes information conversion processing to accommodate the logical configuration of the chipset  28  and the flash memory  38  when sending and receiving information between the chipset  28  and the flash memory  38 , the processor  24  is able to access the flash memory  38  via the chipset  28  and the logical control circuit  36 . 
     The second embodiment of the present invention is now explained. When the controller  12  is to access the storage apparatus  16  in the storage system  10 , programs for (a) device initialization and (b) device diagnosis must be stored in the flash memory  38 , and the flash memory  38  needs to have a large capacity. Here, if 32 MB is required as the capacity of the flash memory  38  and the area that can be accessed from the chipset  28  to the flash memory  38  is set to 16 MB, although the chipset  28  will be able to access the low 16 MB area, it will not be able to access the high 16 MB area since it is not mapped to the memory space. 
     Thus, in this embodiment, a bank switch function is added to the logical control circuit  36  and a flash memory  38  having a capacity of 16 MB+16 MB is used so that a flash memory area that can only be allocated for a capacity of 16 MB in the memory space can be accessed as an area for a capacity of 32 MB. 
     Specifically, as shown in  FIG. 5  and  FIG. 6 , the flash memory  38  comprises a flash area (16 MB) A 1  to become the access target of the processor  24 , and a 16 MB bank B 0  and a 16 MB bank B 1  as physical areas corresponding to the flash area (16 MB) A 1 . When the address of the main memory area A 2  is “0x0000 0000” to “0xFEFF FFFF,” the flash area A 1  will be allocated with “0xFF00 0000” to “0xFFFF FFFF” as the address. The same address is set to the respective banks B 0 , B 1 . 
     Meanwhile, the bus converter  48  is provided with a bank switch register  72  for commanding switching to select one of the banks B 0 , B 1  in response to an access input from the chipset  28  via the LPC bus  70 , and the control register  58  to be used is loaded with a function for outputting a chip select signal CS 0  for selecting the bank B 0  to the bank B 0  when a command for selecting the bank B 0  is output from the bank switch register  72 , and outputting a chip select signal CS 1  for selecting the bank B 1  to the bank B 1  when a command for selecting the bank B 1  is output from the bank switch register  72 . 
     The working of this embodiment is now explained with reference to the flowchart of  FIG. 7 . Foremost, when the access from the microprocessor  24  is input to the logical control circuit  36  via the chipset  28 , the logical control circuit  36  determines whether to access space of 16 MB or less based on a read/write access from the processor  2  (S 11 ), and sets the bank switch register  72  to the bank B 0  side when accessing space of 16 MB or less (S 12 ). Thereby, the chip select signal CS 0  is output from the control register  58  to the bank B 0 , the bank B 0  is subject to the read/write access, and the processing of this routine is ended. 
     Meanwhile, if space of 16 MB or less is not to be accessed, the logical control circuit  36  sets the bank switch register  72  to the bank B 1  side (S 13 ). Thereby, the chip selector signal CS 1  is output from the control register  58  to the bank B 1 , read/write access is executed to the bank B 1 , and the processing of this routine is ended. 
     According to the present embodiment, since the flash memory  38  comprises a flash area (16 MB) A 1  to become the access target of the processor  24  and a 16 MB bank B 0  and a 16 MB bank B 1  as physical areas corresponding to the flash area (16 MB) A 1 , and the logical control circuit  36  is equipped with a bank switch function for accessing either the bank B 0  or the bank B 1  when the flash area (16 MB) A 1  is accessed, the flash memory area A 1  that can only be allocated for a capacity of 16 MB in the memory space can be accessed as an area for a capacity of 32 MB. 
     The third embodiment of the present invention is now explained. This embodiment explains a case where the flash memory  38  stores a BIOS program in addition to the boot program, and, since a part of the BIOS program will be erased if erase/write processing is executed for each sector in the BIOS program, this embodiment aims to prevent such erasure. 
     Specifically, when executing the initialization of the microprocessor  24  and the chipset  28  by executing the BIOS program, as shown in  FIG. 8 , a boot block area (top address “0xFFFF 0000”) A 11 , a main BIOS area (top address “0xFFF0 0000”) A 12 , a reserve area (top address “0xFFEF 0000”) A 13 , and a shadow BIOS area (“0xFFE0 0000”) A 14  are allocated as logical areas of the flash memory  38 . 
     The boot block area A 11  is an area for storing programs to initialize the processor  24  and the chipset  28 , which are the minimal devices required upon turning on the power. The main BIOS area A 12  is an area for storing programs to set the configuration of the chipset  28 . The shadow BIOS area A 14  is a program area to be executed when the main BIOS area A 12  is destroyed, and the same programs as the main BIOS area A 12  are stored therein. In other words, the main BIOS area A 12  and the shadow BIOS area A 14  configure redundant BIOS. 
     Although the boot block area All and the shadow BIOS area A 14  are fixed as areas that do not require rewriting, the main BIOS area A 12  is an area that is rewritable (supportable) in consideration that the BIOS version may be updated. 
     Here, although the boot block area A 11  and the main BIOS area A 12  must set a mutually continuous address (linear address), the erase/write processing is executed for each sector. Thus, for instance, if the boot block area A 11  and the main BIOS area A 12  are partially contained in the sector 0 (128 KB), the boot block area A 11  will be simultaneously erased during the erase/write processing of the main BIOS area A 12 . 
     Thus, in this embodiment, the logical control circuit  36  is loaded with an address translation function for translating a logical area configured from the boot block area A 11 , the main BIOS area A 12 , the reserve area A 13 , and the shadow BIOS area A 14  into a physical area configured from a boot block area A 21 , a reserve area A 22 , a shadow BIOS area A 23 , a reserve area A 24 , and a main BIOS area A 25 . 
     Here, the logical address of the flash memory  38  is set to “0xFFE0 0000” to “0xFFFF FFFF” and the physical address corresponding to this logical address is set to “0xE00000” to “0xFFFFFF.” If the 20 th  bit in the address from the chipset  28  is “0,” this corresponds to the areas (shadow BIOS area A 14 , reserve area A 13 ) of the logical address of “0xFFE0 0000” to “0xFEF FFFF” and if the 20 th  bit is “1,” this corresponds to the areas (main BIOS area A 12 , boot block area A 11 ) of the logical address of “0xFFF0 0000” to “0xFFFF FFFF.” 
     If the logical address of “0xFFE00000” to “0xFFEE FFFF” is subject to address translation when the 20 th  bit in the address from the chipset  28  is “0,” this logical address is translated into the physical address of “0xF00000” to “0xFEFFFF.” If the logical address of “0xFFF0 0000” to “0xFFFE FFFF” is subject to address translation when the 20 th  bit in the address from the chipset  28  is “1,” this logical address is translated into the physical address of “0xE00000” to “0xEEFFFF.” 
     Among the physical areas, the boot block area A 21  and the reserve area (unused area) A 22  are allocated as areas belonging to the sector 0 (128 KB). The shadow BIOS area A 23  and the reserve area A 24  of the physical area are set with the physical address (“0xF00000” to “0xFEFFFF”) corresponding to the area partially including the shadow BIOS area A 14  and the reserve area A 13  of the logical area, and the main BIOS area A 25  of the physical area is set with the physical address (“0xE00000” to “0xEEFFFF”) corresponding to the main BIOS area A 12  of the logical area. 
     In other words, the logical address (“0xFFFF 0000” to “0xFFFF FFFF”) of the boot block area A 11  is set as an address (linear address) that is continuous from the logical address (“0xFFF0 0000” to “0xFFFE FFFF”) of the main BIOS area A 12 , and the physical address (“0xE00000” to “0xEEFFFF”) of the main BIOS area A 25  is set as an address that is different from the logical address “0xFFF0 0000” to “0xFFFE FFFF” of the main BIOS area A 12 , and as an address that belongs to a sector (sector 10 for instance) that is different from the sector (sector 0) to which the physical address (“0xFF0000” to “0xFFFFF”) of the boot block area A 21  belongs, or as an address that is discontinuous from the physical address (“0xFF0000” to “0xFFFFF”) of the boot block area A 21 . 
     Meanwhile, the logical control circuit  36 , as shown in  FIG. 9 , as a device loaded with the address translation function, comprises AND gates  74 ,  76 ,  78 , a bank register  80 , an address translation register  82 , and a selector  84 . 
     The AND gates  74 ,  76 ,  78  and the bank register  80  and the address translation register  82  are configured as a determination unit for identifying an address from the chipset and determining whether to perform address translation. The selector  84  is configured as an address translator for translating a logical address for accessing the flash memory among the addresses from the chipset  28  into a physical address when a determination result indicating that address translation is necessary is output from the determination unit, and accessing the flash memory  38  according to the converted physical address. 
     When a memory address (address signal) is input from the chipset  28  via the LPC bus  70 , the logical control circuit  36  retains a 28-bit address signal, and the AND gate  74  determines whether the bits of addresses  23  to  21  are all “1”; that is, whether they are 0xE or 0xF with a hexadecimal number, and the AND gate  76  determines whether the bits of addresses  19  to  16  are all other than “1”; that is, whether they are other than 0xF with a hexadecimal number. The respective AND gates  74 ,  76  output a signal of “1” to the AND gate  78  when the determination result is positive, and outputs a signal of “0” to the AND gate  78  in all other cases. 
     When the bank register  80  is set to the bank B 0  side and a validation (Enable) signal is being output from the address translation register  82 , on the condition that a signal of “1” is being output from the AND gates  74 ,  76 , the AND gate  78  outputs a signal of “1” to the selector  84 , and outputs a signal of “0” to the selector  84  in all other cases. The selector  84  inverts the value of the 20 th  bit of the address (i.e., inverts “0” to “1” or inverts “1” to “0”) while the signal of “1” is being output from the AND gate  78  since this means that all condition are satisfied. Meanwhile, if a signal of “0” is output from the AND gate  78 , the signal of the 20 th  bit of the address is output to the flash memory  38  as is since this means that the conditions have not been satisfied. 
     The specific processing contents are now explained with reference to the flowchart of  FIG. 10 . Foremost, the logical control circuit  36  retains 28 bits of address output from the chipset  28  (S 21 ). Subsequently, with the logical control circuit  36 , the AND gate  74  determines whether the bits of addresses  23  to  21  are all “1,” and the AND gate  76  determines whether the bits of addresses  19  to  16  are all other than “1.” Subsequently, the logical control circuit  36  performs processing for setting the address translation register  82  to “1” and setting the bank register  80  to the bank B 0  side (S 22 ). 
     Subsequently, the AND gate  78  in the logical control circuit  36  determines whether the four conditions ((1) bits of addresses  23  to  21  are all “1,” (2) bits of addresses  19  to  16  are all other than “1,” (3) address translation register  82  is “1,” (4) bank register  80  is on bank B 0  side) are all satisfied, and outputs the determination result to the selector  84  (S 23 ). If all four conditions are satisfied, the selector  84  inverts the 20 th  bit of the address (S 24 ), outputs the inverted signal to the flash memory  38 , accesses the flash memory  38  (S 25 ), and then ends the processing of this routine. 
     For example, if the logical address of “0xFFE0 0000” to “0xFFEE FFFF” is subject to address translation, when the 20 th  bit in the address from the chipset  28  is inverted from “1” to “0,” this logical address is translated into a physical address of “0xF00000” to “0xFEFFFF.” Here, the logical control circuit  36  accesses the reserve area A 22  and the shadow BIOS area A 23  of the flash memory  38 , and executes rewriting/erase processing and the like to the shadow BIOS area A 23 . Here, even if the erase processing or the like is executed in sector units, since the boot block area A 21  belongs to a sector that is different from the shadow BIOS area A 23 , it is possible to prevent programs and the like stored in the boot block area A 21  from being erased. 
     If the logical address of “0xFFF0 0000” to “0xFFFE FFFF” is subject to address translation, when the 20 th  bit in the address from the chipset  28  is inverted from “0” to “1,” this logical address is translated into a physical address of “0xE00000” to “0xEEFFFF.” Here, the logical control circuit  36  accesses the main BIOS area A 25  of the flash memory  38 , and executes rewriting/erase processing and the like to the main BIOS area A 25 . Here, even if erase processing or the like is executed in sector units, since the boot block area A 21  belongs to a sector that is different from the main BIOS area A 25 , it is possible to prevent programs and the like stored in the boot block area A 21  from being erased. 
     Meanwhile, if the four conditions are not satisfied, the selector  84  outputs the 20 th  bit of the address as is to the flash memory  38  (S 26 ), accesses the flash memory  38  according to the logical address without performing address translation (S 27 ), and then ends the processing of this routine. 
     According to the foregoing embodiment, in addition to being able to rewrite the entire main BIOS area A 25 , even if erasure processing or the like is executed to the main BIOS area A 25  in sector units, it is possible to prevent the programs and the like stored in the boot block area A 21  from being erased since the boot block area A 21  is set in a sector that is different from the main BIOS area A 25 .