Patent Publication Number: US-8524595-B2

Title: Semiconductor package structures

Description:
This application is a continuation of U.S. patent application Ser. No. 11/761,722, filed Jun. 12, 2007, the entirety of which is incorporated by reference herein. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to semiconductor structures, and more particularly to semiconductor package structures and method for forming the package structures 
     2. Description of the Related Art 
     With advances in electronic products, semiconductor technology has been applied widely in manufacturing memories, central processing units (CPUs), liquid crystal displays (LCDs), light emitting diodes (LEDs), laser diodes and other devices or chip sets. In order to achieve high-integration and high-speed requirements, dimensions of semiconductor integrated circuits have been reduced and various materials, such as copper and ultra low-k dielectrics, have been proposed and are being used along with techniques for overcoming manufacturing obstacles associated with these materials and requirements. Further, package techniques incorporating with small-dimension integrated circuits would provide desired chip packages. 
       FIG. 1  is a cross-sectional view of a traditional package structure. The package structure  101  includes solder balls  120  bonded on substrate  110 . The substrate  110  with the solder balls  120  is then flipped and mounted on substrate  100 . After the mounting step, an under-filler material  130  is filled between the substrates  100  and  110 , protecting the solder balls  120  from particle contamination and electrically isolating the adjacent solder balls  120 . The underfill also provides mechanical support and helps prevent failure of the solder joints. 
     SUMMARY OF THE INVENTION 
     In accordance with some exemplary embodiments, a semiconductor structure includes a plurality of solder structures between a first substrate and a second substrate. A first encapsulation material is substantially around a first one of the solder structures and a second encapsulation material is substantially around a second one of the solder structures. The first one and the second one of the solder structures are near to each other and a gap is between the first encapsulation material and the second encapsulation material. 
     The above and other features will be better understood from the following detailed description of the exemplary embodiments of the invention that is provided in connection with the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Following are brief descriptions of exemplary drawings. They are mere exemplary embodiments and the scope of the present invention should not be limited thereto. 
         FIG. 1  is a cross-sectional view of a traditional package structure. 
         FIGS. 2A-2E  are schematic drawings showing an exemplary method for forming a package structure. 
         FIGS. 2F-2H  are schematic cross-sectional views of exemplary package structures. 
         FIG. 3  is a schematic graph showing at least one thermal process for treating exemplary package structures. 
     
    
    
     DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS 
     This description of the exemplary embodiments is intended to be read in connection with the accompanying drawings, which are to be considered part of the entire written description. In the description, relative terms such as “lower,” “upper,” “horizontal,” “vertical,” “above,” “below,” “up,” “down,” “top” and “bottom” as well as derivatives thereof (e.g., “horizontally,” “downwardly,” “upwardly,” etc.) should be construed to refer to the orientation as then described or as shown in the drawing under discussion. These relative terms are for convenience of description and do not require that the apparatus/device be constructed or operated in a particular orientation. 
       FIGS. 2A-2E  are schematic drawings showing an exemplary method for forming a package structure. 
     Referring to  FIG. 2A , at least one dielectric layer such as dielectric layer  203  is formed over a substrate  200  such as semiconductor wafer with diameter 8 inch, 12 inch or greater than 12 inch. At least one metal trace layer such as metal trace layers  207  are formed over the dielectric layer  203 . At least one pad such as pads  209  are formed over the metal trace layers  207 . At least one isolation layer such as isolation layer  211  is formed over the dielectric layer  203 . At least one passivation layer such as passivation layer  205  is formed over the metal trace layers  207 . In some embodiments, the passivation layer  205  may have a surface substantially level with at least one of the surfaces of the pads  209 . At least one solder structure such as solder structures  213  are formed over the pads. 
     The substrate  200  can be a silicon substrate, a III-V compound substrate, a silicon/germanium (SiGe) substrate, a silicon-on-insulator (SOI) substrate, a display substrate such as a liquid crystal display (LCD), a plasma display, an electro luminescence (EL) lamp display, or a light emitting diode (LED) substrate, for example. In some embodiments, at least one diode, transistor, device, circuit or other semiconductor structure or various combinations thereof (not shown) are formed below the dielectric layer  203  and electrically coupled to each other. 
     In some embodiments, the dielectric layer  203  may be a dielectric layer of an interconnect structure. The dielectric layer  203  may be referred to as an inter-metal dielectric (IMD) layer. The material of the dielectric layer  203  may comprise oxide, nitride, oxynitride, low-k dielectric material, ultra low-k dielectric material or other dielectric material or various combinations thereof. The dielectric layer  203  may be formed by, for example, a chemical vapor deposition (CVD) step, a spin-on glass (SOG) step, or other method that is adequate to form a dielectric layer or various combinations thereof. In some embodiments, at least one metallic layer (not shown) is formed within and/or under the dielectric layer  203 . The metallic layer may be provided for electrical connection between the metal trace layer  207  and at least one diode, transistor, device, circuit or other semiconductor structure or various combinations thereof (not shown) formed below the dielectric layer  203  and electrically coupled thereto. 
     The metal trace layers  207  may be provided for electrical connection between the pads  209  and the metallic layer (not shown) formed within and/or under the dielectric layer  203 . The material of the metal trace layers  207  may comprise at least one of copper (Cu), aluminum (Al), aluminum copper (AlCu), aluminum silicon copper (AlSiCu), or other conductive material or various combinations thereof. The metal trace layers  207  may be formed by, for example, a chemical vapor deposition (CVD) step, a physical vapor deposition (PVD) step, an electroplating step, an electroless-plating step or other step that is adequate to for a thin film layer or various combinations thereof. 
     The pads  209  are provided for electrical connection with the metal trace layers  207  and the solder structures  213 . The material of the pads  209  may comprise at least one material such as copper (Cu), aluminum (Al), aluminum copper (AlCu), aluminum silicon copper (AlSiCu), or other conductive material or various combinations thereof. The pads  209  may be formed by, for example, a chemical vapor deposition (CVD) step, a physical vapor deposition (PVD) step, an electroplating step, an electroless-plating step or other step that is adequate to for a thin film layer or various combinations thereof. In some embodiments, at least one of the pads  209  may include an under bump metallization (UBM) layer formed under the solder structure  213 . 
     The isolation layer  211  may be provided to desirably isolate two adjacent metal trace layers  207 . In some embodiments, the isolation layer  211  may be a stress buffer for releasing stresses of the package structure. The material of the isolation layer  211  may comprise, for example, polymide, oxide, nitride, oxynitride, or other material that is adequate to provide desired electrical isolation and/or stress release or various combinations thereof. 
     The passivation layer  205  is provided to protect the pads  209 , the metal trace layers  207 , the dielectric layer  203  and/or any diode, transistor, device, circuit or other semiconductor structure or various combinations thereof (not shown) formed below the dielectric layer  203 . The material of the passivation layer  205  may comprise at least one of oxide, nitride, oxynitride, polyimide, or other material that is adequate to provide desired protection or various combinations thereof. The passivation layer  205  may be formed by, for example, a chemical vapor deposition (CVD) step, a spin-on glass (SOG) step, or other method that is adequate to form a film layer or various combinations thereof. In some embodiments, the passivation layer  205  may have a thickness “t” between about 0.5 μm and about 100 μm. Other dimension of the thickness “t” of the passivation layer  205  may be used in other embodiments. The scope of the invention is not limited thereto. 
     The solder structures  213  are formed over the pads  209 . The solder structures  213  may comprise, for example, solder balls and/or solder bumps. In some embodiments, the solder structures  213  may comprise at least one material such as eutectic tin-lead (Sn—Pb) solder, high lead solder, lead free solder, metal pillar such as copper pillar or other solder material or various combinations thereof. In some embodiments, the solder structures  213  may have a height between about 0.1 millimeter (mm) and about 0.6 mm. Other dimension of the height of the solder structures  213  may be used in other embodiments. The scope of the invention is not limited thereto. 
     Referring to  FIG. 2B , an encapsulation material  220  is formed over the passivation layer  205 , partially covering the solder structures  213 . The encapsulation material  220  may comprise resin-containing epoxy or polymer-based material like a mixture of resin powder and flux. In some embodiments, the flux may include de-oxidation material. The encapsulation material  220  may be formed by, for example, a spin-coating step. 
     In some embodiments, the encapsulation material  220  may have a thickness between about ⅓ of the height of the solder structure  213  and about 9/10 of the height of the solder structures. In other embodiments, the encapsulation material  220  may have a thickness larger than about 10 um, preferred between about 10 μm and about 30 μm. In still other embodiments, the encapsulation material  220  may be formed to a desired height, such that the encapsulation material  220  can wrap around a major portion of the solder structures as shown in  FIG. 2D  or  2 E. 
     After forming the solder structures  213 , the structure shown in  FIG. 2B  may be subjected to a sawing process so as to create a plurality of individual dies  200   a  as shown in  FIG. 2C . The sawing process may include a laser sawing step, a water sawing step, a blade sawing step, other method that is adequate to cut the substrate  200  or various combinations thereof. 
     Referring to  FIG. 2C , the structure shown in  FIG. 2B  may be flipped, such that the solder structures  213  contact a substrate  230 . The substrate  230  may be a printed circuit board (PCB), a silicon substrate, a III-V compound substrate, a silicon/germanium (SiGe) substrate, a silicon-on-insulator (SOI) substrate, a display substrate such as a liquid crystal display (LCD), a plasma display, an electro luminescence (EL) lamp display, or a light emitting diode (LED) substrate, for example. 
     In some embodiments for providing desired mechanical support, coefficient of thermal expansion (CTE) of the encapsulation material  220  is between the CTE of substrate  300  and substrate  230 . 
     In some embodiments, the substrate  230  may comprise at least one pad (not shown) for electrical connection with the solder structures  213 . In other embodiments, at least one diode, transistor, device, circuit or other semiconductor structure or various combinations thereof (not shown) are formed below the pad (not shown) and electrically coupled to each other. 
     Referring to  FIG. 2D , a thermal process  233  may be applied to the encapsulation material  220 , such that the encapsulation material  220  melts and flows along at least one sidewall such as sidewalls  214  of the solder structures  213   a . Accordingly, the encapsulation material layers  220   a  are formed on the sidewalls  214  of the solder structures  213   a . In some embodiments, the thermal process  233  may be conducted in a furnace, a rapid thermal processing (RTP) apparatus, oven or other thermal processing apparatus or combinations thereof. 
     In some embodiments, the thermal process  233  may heat the encapsulation material  220  between about 100° C. and about 160° C. for a processing time “T 1 ” as shown in  FIG. 3 . In some embodiments, the thermal process  233  may also soften and/or melt the solder structures  213 , such that the height of the solder structures  213   a  may be slightly less than that of the solder structures  213  (shown in  FIG. 2C ). 
     Referring again to  FIG. 2D , as the encapsulation material layers  220   a  flows along the sidewalls  214  of the solder structures  213   a , a gap  240  may be formed between the adjacent encapsulation material layers  220   a . In some embodiments, a part (not shown) of the encapsulation material  220  may remain on the surface  205   a  of the passivation layer  205 . 
     Referring to  FIG. 2E , another thermal process such as a reflow process  243  may be applied to the encapsulation material  220   a  and/or the solder structures  213   a , such that the reflowed solder structures  213   b  may desirably contact the substrate  230 . In some embodiments, the reflow process  243  may be conducted within a furnace, a rapid thermal processing (RTP) apparatus, oven or other thermal processing apparatus or combinations thereof. 
     In some embodiments, the reflow process  243  may desirably soften the solder structures  213   b  such that the stacked structure shown in  FIG. 2E  may be reduced to a desired package height. The reflow process  243  may soften and/or melt the solder structures  213   a , such that the height of the solder structures  213   b  may be slightly less than that of the solder structures  213   a  (shown in  FIG. 2D ). 
     In some embodiments, the reflow process  243  may heat the solder structures  213   a  (shown in  FIG. 2D ) between about 160° C. and about 240° C. for a processing time “T 2 ” as shown in  FIG. 3 . Other process temperatures and/or processing time of the reflow process  243  may be used in other exemplary embodiments. The scope of the present invention is not limited thereto. 
     In other embodiments, the reflow process  243  may heat the encapsulation material layers  220   a  (shown in  FIG. 2D ), such that the encapsulation material layers  220   a  may flow along the sidewalls  214  of the solder structures  213   a  so as to form the encapsulation material layers  220   b  and the solder structures  213   b . Accordingly, the gap  240  may be formed between the adjacent encapsulation material layers  220   b . In some embodiments, a part (not shown) of the encapsulation material  220  (shown in  FIG. 2A ) may remain on the surface  205   a  of the passivation layer  205 . The encapsulation material layers  220   b  may be substantially conformal on the sidewalls  214  of the solder structures  213   b.    
     In some embodiments, the reflow process  243  described in conjunction with  FIG. 2E  may be used to form the desired encapsulation material layers  220   b  and the solder structures  213   b  as shown in  FIG. 2E . In the embodiments, the thermal process  233  described in conjunction with  FIG. 2D  may be omitted. In some embodiments, the reflow process  243  may have a process temperature between about 100° C. and about 240° C. Other process temperatures and/or processing time of the reflow process  243  may be used in other exemplary embodiments. The scope of the present invention is not limited thereto. 
     Referring again to  FIG. 1 , the under-filler  130  is filled between the substrates  100  and  110  after the substrate  100  with the solder bumps  120  is bonded on the substrate  100 . Unlike the under-filler  130 , the encapsulation material  220  (shown in  FIG. 2B ) may be formed before the bonding process and thus may be formed in a semiconductor manufacturing facility, rather than in a package/testing factory. By reflowing the encapsulation material  220  so as to form the encapsulation material layers  220   b , the process for forming the under-filler  130  described in conjunction with  FIG. 1  can be omitted. Accordingly, tools and modules for forming the under-filler  130  can be omitted. 
     It is found that the under-filler  130  tends to trap moisture generated from the filling process itself and/or absorb moisture from environment. It is found that moisture may contribute to IMD delamination occurring at the die edge of the substrate  110  if the under-filler  130  is not well developed. As the processes described in conjunction with  FIGS. 2A-2E  do not apply the under-filler  130  between the substrate  230  and passivation layer  205 , no development of an under-filler material is used. Accordingly, the processes described in conjunction with  FIGS. 2A-2E  are not subject to the concern of the traditional structure shown in  FIG. 1 . 
     Further, at least one gap such as gap  240  is formed between the adjacent solder structures  213   b . With the thermal process  233  and/or the reflow process  243 , moisture within the encapsulation material layers  220   b  may be desirably expelled from the region between the die  200   a  and the substrate  230 . In some embodiments, the gap  240  may be circumferential around at least one of the encapsulation material layers  220   b  between the die  200   a  and the substrate  230 . 
     Referring again to  FIG. 1 , after forming the bumps  120  on a wafer which is sawed to provide a plurality of dies  110 . The die  110  is then flipped and bonded on the substrate  100 . Then the underfill  130  is filled between the die  110  and the substrate  100 . Unlike the traditional process, the encapsulation material layer  220  is formed at the wafer level of the substrate  200  as shown in  FIG. 2B . The substrate  200  is then subject to a dicing process resulting to a plurality of dies  200   a  with the encapsulation material layer  220  formed thereover. The die  200   a  is then flipped and then subject to at least one of the thermal process  233  and the reflow process  243  as shown in  FIGS. 2D and 2E , respectively, so as to flow the encapsulation material layer  220  substantially around the solder structures  213   b . Therefore, the underfilling process used in the traditional process can be optionally omitted. 
       FIGS. 2F-2H  are schematic cross-sectional views of exemplary package structures. 
     Referring to  FIG. 2F , the encapsulation material layers  220   b  may lie on the sidewalls  214  of the solder structures  213   b  near to the surface of the passivation layer  205  and the surface of the substrate  230  without substantially lying on the middle region of the solder structures  213   b.    
     Referring to  FIG. 2G , the encapsulation material layers  220   b  may lie on the sidewalls  214  of the solder structures  213   b  such that the dimension “a” of the material layers  220   b  lying in the region adjacent to the surfaces of the substrate  230  and/or the passication layer  205  is larger than the dimension “b” of the material layers  220   b  lying in the middle region of the solder structures  213   b , forming an hourglass shape. 
     Referring to  FIG. 2H , the encapsulation material layers  220   b  may lie on the sidewalls  214  of the solder structures  213   b  such that the dimension “c” of the material layers  220   b  lying in the region adjacent to the surface of the substrate  230  is larger than the dimension “d” of the material layers  220   b  lying in the region adjacent to the surface of the passivation layer  205 . 
     Although the present invention has been described in terms of exemplary embodiments, it is not limited thereto. Rather, the appended claims should be construed broadly to include other variants and embodiments of the invention which may be made by those skilled in the field of this art without departing from the scope and range of equivalents of the invention.