Patent Publication Number: US-11646733-B2

Title: Digital output driver circuit and method

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is a continuation of U.S. patent application Ser. No. 16/983,596, entitled “Digital Output Driver Circuit and Method,” and filed on Aug. 3, 2020, which claims the benefit of Italian Patent Application No. 102019000015306, filed on Aug. 30, 2019, which applications are hereby incorporated herein by reference. 
    
    
     TECHNICAL FIELD 
     The description relates to driver circuits. 
     BACKGROUND 
     The voltage of the power supply source, which may be higher than the voltage used for communication purposes, represents a factor to be taken into account in Universal Serial Port (USB) Power Delivery (USB-PD) applications. 
     Robust circuitry is thus desirable in order to keep the application safe in case of accidental contacts, for instance. 
     Also, certain solutions already proposed were found to be unsuitable for low cost technology implementations with expected voltages of 3.3 V or higher. 
     SUMMARY 
     Some embodiments contribute in facilitating USB-PD applications that are capable of operating safely also in case of accidental contacts and/or are suitable for low cost technology implementations with expected voltages of 3.3 V or higher. 
     One or more embodiments may be applied in complying with USB power delivery (USB-PD) specifications with the aim of regulating communications on a USB cable (type-C, for instance) prior to applying power supply. 
     Some embodiments relate to a circuit. 
     One or more embodiments relate to a corresponding method. 
     One or more embodiments lend themselves to be implemented by resorting to high(er) voltage metal-oxide-semiconductor field-effect transistor (MOSFET) technology. 
     One or more embodiments facilitate avoiding issues related to MOSFET turning-on, keeping focus on a good matching between rise time and fall time at the circuit output. 
     One or more embodiments may use two N-type MOSFET transistors (briefly, N-MOSFETs) in the output stage providing both falling edge and rising edge regulation. 
     One or more embodiments facilitate adequate operation of both output N-MOSFETs with a good matching between edges. 
     In one or more embodiments, such a good matching can be facilitated by double checking rising times with respect to falling times and delay times between command signals and half-height output (for both edges). 
     One or more embodiments may provide a circuit which is suited for use as a matched digital driver with different technologies including low-cost technologies. 
     Experimental results indicate that an output driver according to one or more embodiments may be adapted for applications where a constant transition time represents a desirable feature. 
     One or more embodiments may be advantageously applied to designing USB interfaces for which a uniform transition time regardless of environmental variations represents a desirable feature. 
     One or more embodiments exhibit a (very) low variation of transition delay time with capacitive output loads larger than internal capacitance. For instance, one or more embodiments can be adapted to operate adequately with a capacitive output load greater than 400 pF as contemplated by USB specifications with internal capacitances having a value smaller than 40 pF. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       One or more embodiments will now be described, by way of example only, with reference to the annexed figures, wherein: 
         FIG.  1    is a circuit diagram of a driver circuit; 
         FIG.  2    is an exemplary circuit diagram of a driver circuit, according to embodiments of the present invention; 
         FIG.  3    is a collection of time diagrams associated with the circuit of  FIG.  2   , according to an embodiment of the present invention; and 
         FIG.  4    shows a possible implementation of the circuit of  FIG.  2    in a USB system, according to an embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS 
     In the ensuing description, various specific details are illustrated in order to provide an in-depth understanding of various examples of embodiments according to the description. The embodiments may be obtained without one or more of the specific details, or with other methods, components, materials, etc. In other cases, known structures, materials, or operations are not illustrated or described in detail so that various aspects of the embodiments will not be obscured. 
     Reference to “an embodiment” or “one embodiment” in the framework of the present description is intended to indicate that a particular configuration, structure, or characteristic described in relation to the embodiment is comprised in at least one embodiment. Hence, phrases such as “in an embodiment,” “in one embodiment,” or the like, that may be present in various points of the present description do not necessarily refer exactly to one and the same embodiment. Furthermore, particular conformations, structures, or characteristics may be combined in any adequate way in one or more embodiments. The references used herein are provided merely for convenience and hence do not define the extent of protection or the scope of the embodiments. 
       FIG.  1    is a circuit diagram of an output driver circuit with controlled slew-rate as discussed in S. K. Shin, et al.: “Slew-Rate-Controlled Output Driver Having Constant Transition Time Over Process, Voltage, Temperature, and Output Load Variations”, IEEE Transactions on Circuits and Systems, TCAS-II, Vol. 54, No. 7, July 2007, p. 601. 
     That conventional solution provides a slew-rate-controlled output driver having a constant transition time irrespective of environmental variations. 
     The solution exemplified in  FIG.  1    employs a capacitive feedback (capacitor C f ) between the circuit output V PAD  as sensed at a PAD node between two output CMOS-Driver transistors MD 1  and MD 2  and a node between two switches S 1  and S 2  in a pre-driver stage. The switches S 1  and S 2  are configured to couple the capacitor C f  (to draw and inject currents i c1  and i c2 ) to respective intermediate points A 1  and A 2  between pairs of complementary P-type and N-type MOSFET transistors M 10 , M 20  and M 30 , M 40  that provide flow paths therethrough for currents I 10  and I 20 , respectively and the control terminals (gates PG and NG) of the CMOS driver transistors MD 1  and MD 2 . 
     As reported, the solution exemplified in  FIG.  1    was designed and fabricated using a 0.13-mum CMOS process to allow transition times which are independent of process, voltage, temperature and output load variations. For instance, a normalized variation on transition time of the output driver due to PVT variations is reported to be improved by 74%-80% as compared to a conventional output driver, with comparison results indicating a normalized variation on transition time due to output load change from 10 pF to 100 pF (10 times variation) in typical process, voltage and temperature corners improved up to 66%. 
     The solution exemplified in  FIG.  1    may comply with USB specifications if supplied with a voltage of 1.2 V. It is noted that such a driver would be vulnerable to an accidental contact of the output (at the PAD node) with a voltage higher than the indicated voltage supply. 
     The output robustness of a solution as exemplified in  FIG.  1    could be improved by adopting “higher voltage” MOSFET technology (e.g., 3.3 V MOSFET). It is noted that such a choice may give rise to functional issues insofar as the voltage threshold of each MOSFET might be greater than 1.2 V. 
     Another option which might be possibly considered would involve applying two different voltages to the CMOS-driver stage (MD 1  and MD 2 ) and to the pre-driver stage (which includes the pairs M 10 , M 20  and M 30 , M 40 ). While on the hand facilitating turn-on of MD 2 , no such effect could be expected for MD 1 . 
     One or more embodiments may address these issues by resorting to a driver circuit  10  as exemplified in  FIG.  2   . 
     The circuit  10  as exemplified in  FIG.  2    comprises a driver stage (CMOS, for instance)  12  including two (output) transistors (N-channel MOSFET, for instance) MN 1  and MN 2 . These transistors have current paths therethrough (source-drain in the case of field effect transistors such MOSFETs) providing a current flow line from a supply voltage line VCC and ground GND with an output node OUT between MN 1  and MN 2 . 
     For instance, as exemplified in  FIG.  2   , MN 1  has its drain coupled to the voltage line VCC and its source coupled to the output node OUT, and MN 2  has its drain coupled to the output node OUT and its source coupled to ground GND. 
     The circuit  10  as exemplified in  FIG.  2    also comprises a pre-driver stage configured to drive the control terminals (gates, in the case of field effect transistors such MOSFETs) MN 1 _G and MN 2 _G of MN 1  and MN 2 , respectively. To that effect, such a pre-driver stage can comprise two sub-stages designated  141  and  142 , coupled between a (possibly common) supply voltage line VDD, which may be brought to a voltage different from the voltage of the line VCC, and ground GND. 
     As exemplified herein, the sub-stage  141  comprises two transistors (N-channel MOSFET, for instance) M 1  and M 2 , and the sub-stage  142  comprises a transistor (N-channel MOSFET, for instance) M 3 . 
     As exemplified in  FIG.  2   , the sub-stage  141  comprises a current line from VDD to ground GND comprising a current generator I 3  coupled to VDD as well as a first switch  1  and a second switch  2  with the first switch  1  between I 3  and the second switch  2 . Another current line from VDD to ground GND comprises a current generator I 4  coupled to VDD as well as the current path (source-drain in the case of field effect transistors such as a MOSFET) through M 2  and a capacitor C 1  with M 2  between I 4  and the capacitor C 1 . As exemplified herein, M 2  has its drain coupled to I 4 , the source coupled to C 1  and to an intermediate point between the switches  1  and  2  and configured to receive at that point a voltage VC 1  across the capacitor C 1 . As exemplified herein, M 2  is in a diode-like configuration with its current path shorted (at the drain in the case of field effect transistors such as a MOSFET) to the control terminal (gate, in the case of a field effect transistor such as a MOSFET). 
     A further current line from VDD to ground GND comprises a current generator I 5  coupled to VDD as well as to M 1  in a diode-like configuration with its current path shorted (at the drain, in the case of field effect transistors such as a MOSFET, for instance) to the control terminal (gate in the case of a field effect transistor such as a MOSFET) and coupled to I 5  and its current path (at the source, in the case of field effect transistor such as a MOSFET) coupled to ground GND. The sub-stage  141  also comprises a third switch  1 ′ and a fourth switch  2 ′. 
     As exemplified in  FIG.  2   , the third switch  1 ′ is coupled between the control terminal (gate, in the case of a field effect transistor such as a MOSFET) shorted to the current path (source-drain, in the case of a field effect transistor such as a MOSFET) of M 2  and the control terminal MN 1 _G (gate, in the case of a field effect transistor such as a MOSFET) of MN 1 . The fourth switch  2 ′ is coupled between the control terminal (gate, in the case of a field effect transistor such as a MOSFET) shorted to the current (gate-to-drain, in the case of a field effect transistor such as a MOSFET) of M 1  and the control terminal MN 1 _G (gate, in the case of a field effect transistor such as a MOSFET) of MN 1 . 
     The switches  1 ′ and  2 ′ are indicated with the same basic designation of the first switch  1  and the second switch  2  discussed in the foregoing to indicate that the switches  1 ,  1 ′ and the switches  2 ,  2 ′ will be operated the same manner, that is with switch  1 ′ being open or closed as a result of switch  1  being open or closed, respectively, and with switch  2 ′ being open or closed as a result of switch  2  being open or closed, respectively. 
     As exemplified in  FIG.  2   , the sub-stage  142  comprises a current line from VDD to ground GND comprising a current generator I 1  coupled to VDD as well as to M 3  in a diode-like configuration with its current path shorted (at the drain in the case of field effect transistors such as a MOSFET) to the control terminal (gate in the case of a field effect transistor such as a MOSFET) with a voltage VM 3  present at that shorting node. Another current line from VDD to ground GND comprising a current generator I 2  coupled to VDD as well as to a fifth switch  2 ″ in turn coupled to M 3  in a diode-like configuration with its current path shorted (at the drain in the case of field effect transistors such as a MOSFET) to the control terminal (gate in the case of a field effect transistor such as a MOSFET). 
     As exemplified in  FIG.  2   , the voltage VM 3  present at that shorting node is adapted to be coupled to the output node OUT via a (second) capacitor C 2  and to the control terminal MN 2 _G (gate, in the case of a field effect transistor such as a MOSFET) of MN 2  via a sixth switch  2 ′″. As exemplified in  FIG.  2   , a seventh switch  1 ″ is provided configured to act between the control terminal MN 2 _G (gate, in the case of a field effect transistor such as a MOSFET) of MN 2  and ground GND with the capability of forcing MN 2 _G to ground level. 
     Again, a same basic designation of the first switch  1  and the second switch  2  discussed in the foregoing being used for the switches  1 ″,  2 ″,  2 ′″ indicates that the switch  1 ″ and the switches  2 ″,  2 ′″ will be operated in the same manner of the switches  1  and  2 , that is with switch  1 ″ being open or closed as a result of switch  1  being open or closed, respectively, and with switches  2 ″,  2 ′″ being open or closed as a result of switch  2  being open or closed, respectively. 
     The current generators I 1 , I 2 , I 3 , I 4  and I 5  can be implemented in any manner known to those of skill in the art for that purpose. The same also applies to the switches  1 ,  2 ,  1 ″,  2 ″ and  2 ′″, which can be implemented as electronic switches such as transistors, for instance. 
     As exemplified in  FIG.  2   , a capacitive load CLOAD can be coupled between the output node OUT and ground GND. It will be appreciated that the load CLOAD may be a distinct element from the embodiments. 
     One or more embodiments lend themselves to be implemented with “higher voltage” MOSFET technology avoiding issues related to MOSFET turn-on, keeping focus on a good matching between rise time and fall time of the output. 
     For instance, the circuit  10  can be implemented with a 3.3 V technology or greater. VCC can be 1.8V or less, as a function of the voltage levels used for (USB, for instance) communication. In one or more embodiments VDD can be set at a same value for both sub-stages  141  and  142 , which is higher than VCC (VCC+1.5 V, for instance) in order to facilitate driving MOSFET transistors effectively. 
     A CMOS-driver section  12  as exemplified herein facilitates achieving desired voltages, slopes and delays to the output node OUT with respect to the clock switching of the switches  1 ,  2 ,  1 ′,  2 ′,  1 ″,  2 ″,  2 ′″ from PHASE  1  ( 1 ,  1 ′,  1 ″ closed and thus conductive—signal  1  “high” in the uppermost diagram in  FIG.  3   ) to PHASE  2  ( 2 ,  2 ′,  2 ″,  2 ′″ closed and thus conductive—signal  2  “high” in the second uppermost diagram in  FIG.  3   ) and vice-versa. 
     The “phases”  1  and  2  indicative of the switch positions may be related to digital bits intended to be transmitted from a transmitted TX over a communication line (USB, for instance) as represented by the load CLOAD, as shown, by way of example, in the lowermost diagram in  FIG.  3    where an on-off (essentially, ASK modulated) two-valued signal at the output node OUT from the circuit  10  whose timing is controlled via phase signals PHASE  1  and PHASE  2  in the two uppermost diagrams. 
     As may be appreciated from these two uppermost diagrams of  FIG.  3   , these “phase” signals may not necessarily be square-wave clock signals. Also, like the load CLOAD, the transmitter TX may be a distinct element from the embodiments. 
     Possible operation of a circuit  10  as exemplified herein can be described (by referring to an exemplary implementation where MN 1 , MN 2 , M 1 , M 2  and M 3  are field effect transistors such as N-type or N-channel MOSFET transistors) and assuming to start from a (PHASE  1 ) condition (switches  1 ,  1 ′ and  1 ″ closed and thus conductive with switches  2 ,  2 ′,  2 ″ and  2 ′″ open and non-conductive) where the (e.g., capacitive) load CLOAD and C 1  completely discharged, that is with the signal at the output node OUT (briefly, the signal OUT) and the voltage VC 1  across C 1  equal to 0 V, as shown in the diagrams in  FIG.  3   . 
     The gate of MN 1  (MN 1 _G) is coupled to the mutually shorted gate and drain of M 1 , thus setting the starting voltage of MN 1 _G slightly under the conduction threshold MN 1  MOSFET. 
     In PHASE  1  the gate of MN 2  (MN 2 _G) is held coupled to ground by the switch  1 ″, so that MN 2  is off (non-conductive). The capacitor C 1  will start charging at a constant current (I 3 +I 4 ), and the voltage VC 1  across C 1  will grow with a constant rate (I 3 +I 4 )/C 1 . The transistor M 2  will operate at a constant current, thus developing a constant voltage between its drain (at a voltage VM) and its source (at a voltage VC 1 ). As consequence, the voltage MN 1 _G will grow at a constant rate, starting from a defined voltage (threshold of M 2 ), as shown, for instance, in the third diagram in  FIG.  3   . 
     As the voltage MN 1 _G goes high, the currents I 3  and I 4  will undergo a saturation effect, reducing their growth rate, with a negligible effect on OUT if VDD is higher than VCC (VDD&gt;VCC+1.5 V, for instance). 
     As visible, for instance, in the diagram at the lowermost of  FIG.  3   , a ramp as applied to MN 1 _G will result in a ramp on OUT (that is, the voltage at the output node OUT), replicated with a same slope. 
     By assuming (which is a judicious assumption under the circumstances considered herein) that the load CLOAD coupled with the output node OUT is essentially a large capacitance (CLOAD&gt;&gt;C 1 ), the constant ramp will result in a constant-current capacitance charging until the voltage across CLOAD reaches VCC with the voltage on MN 1 _G reaching VDD, thus facilitating having MN 1  on (that is conductive) with a (very) low equivalent resistance. 
     The circuit  10  as exemplified herein will operate statically until Phase 1  finishes, with MN 1 _G becoming a high-impedance node and capacitances (C 1  and COUT) “holding” the situation. 
     At the starting point of phase  2  (switches  1 ,  1 ′ and  1 ″ open and thus non-conductive with switches  2 ,  2 ′,  2 ″ and  2 ′″ closed and conductive) CLOAD can be assumed to be fully charged to VCC, that is the signal OUT is equal to VCC, as shown, e.g., in the diagrams in  FIG.  3   . 
     The capacitance C 1  will be shorted by the switch  2  so that the voltage across the capacitance C 1 , namely VC 1 , will be zero (ground level GND). 
     The gate of MN 1  (MN 1 _G) will be coupled to M 1  that has its gate and its drain mutually shorted, thus holding the voltage at MN 1 _G slightly under the threshold of MN 1  MOSFET, which will be in an off state (non-conductive) till the end of the PHASE  2 . 
     As a result of the switch  1 ″ being now open and the switches  2 ″ and  2 ′″ closed, the gate MN 2 _G of MN 2  will switch from ground connection GND to the threshold of M 3  and become increasingly conductive. 
     The currents I 1 +I 2  will rapidly bring the voltage at MN 2 _G to the threshold of MN 2  and so that MN 2  will operate in a saturation state with the capacitance C 2  between its drain and gate with a voltage VC 2  across C 2 . The saturation state of MN 2  facilitates a constant fall time of the signal OUT until the end of the transition. 
     Exiting the saturation state (that is OUT&lt;MN 2 _G—the respective threshold) gives rise to a saturation effect on discharging the load capacitance CLOAD, with a negligible effect insofar as (this is again a judicious assumption under the conditions considered) CLOAD&gt;&gt;C 2 . 
     After the completion of the transition, MN 2 _G goes to VDD and turns MN 2  fully on. 
     One or more embodiments may facilitate a desirable matching of rising and falling edges (Trise and Tfall, respectively) of the signal OUT applied by the circuit  10  to a load such CLOAD, as shown, e.g., in the diagram at the lowermost of  FIG.  3    (Trise is about equal to Tfall). 
     To that effect, complying with the following specifications was found to be advantageous: 
     currents I 1 =I 4  and I 4 =I 5  (starting condition) 
     currents I 1 +I 2 =I 3 +I 4  (charging condition) 
     same dimensions of M 1 , M 2  and M 3  (MOSFETs, for instance) 
     same dimensions of MN 1  and MN 2   
     same capacitance values C 1  and C 2   
     CLOAD&gt;&gt;C 1 , CLOAD&gt;&gt;C 2  (for instance, CLOAD=400 pF and C 1 =C 2 =40 pF). 
     Pre-charging the gates MN 1 _G and MN 2 _G at starting point voltages as already defined was similarly found to be beneficial in matching the “on” delay from digital control switching to the half-height condition of the OUT signal switching (as shown, e.g., by Tdel 1 , Tdel 2  in the lowermost diagram of  FIG.  3   ). 
     One or more embodiments facilitate achieving a high output level in excess of 1.04 V, for instance in the range 1.103 V-1.137 V. 
     One or more embodiments equally facilitate achieving a low output level under 70 mV, for instance in the range 0.3 mV-24.2 mV. 
     Experimental results indicated that, in one or more embodiments, the temperature variation in the signal OUT is in compliance with a USB mask as defined in standards. Variations in matching between components, load capacitance, reference currents and temperature were found to lead to accuracy in the signal OUT (in terms of edges and delays) in compliance with USB standard specifications. 
       FIG.  4    shows a possible implementation of circuit  10  in a USB system, according to an embodiment of the present invention. The communication logic, receiver circuit RX, protection circuit, and power supplier circuit of the USB charger, as well as the communication logic, receiver circuit RX, and protection circuit of the USB load may be implemented in any way known in the art. 
     A circuit (for instance, 10) as exemplified herein may comprise an output stage having a supply node (for instance, VCC) and an output node (for instance, OUT) and comprising a first transistor (for instance, MN 1 ) and a second transistor (for instance, MN 2 ) having current paths therethrough (source-drain, in the exemplary case of field effect transistors such as MOSFET) coupled between the supply node and the output node (in the exemplary case of case of MN 1 ) and between the output node and ground (in the exemplary case of case of MN 2 ) respectively, the first transistor and the second transistor having respective control terminals (for instance, gates such as MN 1 _G, MN 2 _G in the exemplary case of field effect transistors such as MOSFETs). 
     A drive stage (for instance,  141 ,  142 ) is configured to drive the control terminals of the first transistor and the second transistor, the drive stage comprising a first capacitance (for instance, C 1 ) and a second capacitance (for instance, C 2 ), current generator circuitry (for instance, I 1 , I 2 , I 3 , I 4 , I 5 ) coupled to at least one further supply node as well as switching circuitry (for instance,  1 ,  2 ,  1 ′,  2 ′,  1 ″,  2 ″,  2 ′″), the switching circuitry configured to admit: 
     a first configuration (for instance, PHASE  1 ), wherein the control terminal of the second transistor is coupled (for instance, via  1 ″) to ground with the second transistor in an off (non-conductive) state and the first capacitance coupled (for instance, via  1 , M 2 ) to the current generator circuitry (for instance, I 3 , I 4 ) and (for instance, via  1 ′) to the control terminal of the first transistor with the first transistor in an on (conductive) state, wherein a voltage at the output node increases towards the voltage at the supply node, 
     a second configuration (for instance, PHASE  2 ) wherein the control terminal of the first transistor (MN 1 ) is coupled (for instance, via  2 ′) to a turn-off voltage (for instance, VM 1 ) of the first transistor with the first transistor in an off (non-conductive) state and the control terminal of the second transistor is coupled (for instance, via  2 ″,  2 ′″) to the current generator circuitry (for instance, I 1 , I 2 ) with the second transistor in an on (conductive) state, with the second capacitance coupled (for instance, via  2 ′″) between the output node and the control terminal of the second transistor (MN 2 ) wherein the voltage at the output node decreases from the voltage at the supply node towards ground. 
     In a circuit as exemplified herein, the drive stage may comprise a first sub-stage (for instance,  141 ) and a second sub-stage (for instance,  142 ). The first sub-stage is configured to drive the control terminal of the first transistor, the first sub-stage comprising the first capacitance, a first subset (for instance, I 3 , I 4 , I 5 ) of the current generator circuitry coupled to a first further supply node (for instance VDD), as well as a first subset (for instance,  1 ,  2 ,  1 ′,  2 ′) of the switching circuitry. The second sub-stage (for instance,  142 ) is configured to drive the control terminal of the second transistor, the second sub-stage comprising the second capacitance (C 2 ), a second subset (for instance, I 1 , I 2 ) of the current generator circuitry coupled to a second further supply node (for instance, VDD) as well as a second subset (for instance,  1 ″,  2 ″,  2 ′″) of the switching circuitry. 
     In a circuit as exemplified herein, the first sub-stage may comprise a charge current source (for instance, I 3 , I 4 ) with the first subset (for instance,  1 ,  2 ,  1 ′,  2 ′) of the switching circuitry configured to, in the first configuration, couple the first capacitance with the charge current source (for instance, I 3 , I 4 , via  1 ) and with the control terminal (for instance, MN 1 _G via  1 ′) of the first transistor, and a turn-off current generator (for instance, I 5 ) with the first subset of the switching circuitry configured to, in the second configuration, short-circuit (for instance, via  2 ) the first capacitance and couple (for instance, via  2 ′) the turn-off current generator to the control terminal of the first transistor to apply the turn-off voltage thereto. 
     In a circuit as exemplified herein the charge current source in the first sub-stage ( 141 ) may comprise a first current generator (I 3 ) with the first subset ( 1 ) of the switching circuitry configured to, in the first configuration (PHASE  1 ), couple the first capacitance (C 1 ) with the first current generator (I 3 ), and a second current generator (I 4 ) coupled with the first capacitance (C 1 ) via a transistor (M 2 ) having a control terminal and a current path therethrough coupled in a diode-like configuration with the first subset ( 1 ′) of the switching circuitry configured to, in the first configuration (PHASE  1 ), couple the control terminal and the current path through the transistor (M 2 ) in a diode-like configuration with the control terminal (MN 1 _G) of the first transistor (MN 1 ). 
     In a circuit as exemplified herein, the turn-off current generator in the first sub-stage may be coupled to a turn-off voltage generating transistor (for instance, M 1 ) having a control terminal and a current path therethrough coupled in a diode-like configuration with the first subset of the switching circuitry configured to, in the second configuration, couple the control terminal and the current path through the turn-off voltage generating transistor with the control terminal of the second transistor (for instance, via  2 ′). 
     In a circuit as exemplified herein, the second sub-stage may comprise the second subset of the switching circuitry configured (for instance,  1 ″) to, in the first configuration, couple to ground the control terminal of the second transistor, a drive voltage generating transistor (for instance, M 3 ) having a control terminal and a current path therethrough coupled in a diode-like configuration, a first current generator (for instance, I 1 ) coupled with the control terminal and the current path through the drive voltage generating transistor in a diode-like configuration, wherein the drive voltage generating transistor is arranged intermediate the first current generator and ground with its control terminal and the current path therethrough coupled to the output node via the second capacitance, and a second current generator (for instance, I 2 ) with the second subset of the switching circuitry configured to, in the second configuration, couple the control terminal and the current path through the drive voltage generating transistor in a diode-like configuration with the second current generator (for instance, I 2 , via  2 ″) and the control terminal of the second transistor (for instance, MN 2  via  2 ′″). 
     In a circuit as exemplified herein the second current generator (for instance, I 4 ) in the charge current source and the turn-off current generator (for instance, I 5 ) in the first sub-stage and the first current generator (for instance, I 1 ) in the second sub-stage are configured to produce a same current intensity (that is I 1 =I 4  and I 4 =I 5 ), and the summed intensities (for instance, I 1 +I 2 ) of the currents produced by the first current generator (for instance, I 1 ) and the second current generator (for instance, I 2 ) in the second sub-stage are equal to the summed intensities (for instance, I 3 +I 4 ) of the currents produced by the first current generator (for instance, I 3 ) and the second current generator (for instance, I 4 ) in the charge current source in the first sub-stage. 
     In a circuit as exemplified herein, the first transistor and the second transistor may comprise transistors of a homologous type (optionally both N-channel field effect transistors, and/or MOSFET transistors, and/or transistors having the same dimensions. 
     In a circuit as exemplified herein the first capacitance and the second capacitance have a same capacitance value. 
     A circuit as exemplified herein may have a capacitive load (for instance, CLOAD) coupled to the output node, with the capacitive load having a capacitance value which may be substantially larger (for instance, ten times larger) than the capacitance value of the first capacitance and the second capacitance. 
     A method of operating the circuit ( 10 ) In a circuit as exemplified herein may comprise actuating the switching circuitry (for instance, the first,  1 ; second,  2 ; third  1 ′, fourth  2 ′; fifth  1 ″; sixth  2 ″; and seventh  2 ′″ switches) in the drive stage alternatively between the first configuration (for instance, PHASE  1 ) the second configuration (for instance, PHASE  2 ), wherein the voltage at the output node transitions towards and away the voltage at the supply node, as shown, for instance, in the lowermost diagram in  FIG.  3   . 
     A method as exemplified herein may comprise applying to the at least one further supply node (for instance, VDD) of the drive stage a voltage higher than the voltage applied to the supply node (for instance, VCC) of the output stage (for instance, with VDD&gt;Vcc+1.5V). 
     Without prejudice to the underlying principles, the details and the embodiments may vary, even significantly, with respect to what has been described by way of example only without departing from the scope of the embodiments. 
     The extent of protection is determined by the annexed claims.