Patent Publication Number: US-11658410-B2

Title: Apparatus and method for synchronizing power circuits with coherent RF signals to form a steered composite RF signal

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application claims priority to U.S. Provisional Patent Application Ser. No. 62/817,096, filed Mar. 12, 2019, the contents of which are incorporated herein by reference. 
    
    
     FIELD OF THE INVENTION 
     This invention relates generally to high-power Radio Frequency (RF) signal processing. More particularly, this invention is directed toward techniques for synchronizing power circuits with coherent RF signals to form a steered composite RF signal in a far field. 
     BACKGROUND OF THE INVENTION 
     The production of high-power RF signals, such as Megawatts of radiated power, typically requires analog RF signal processing circuitry that consumes large amounts of energy, which results in large amounts of radiated heat. Consequently, expensively rated circuits and elaborate cooling mechanisms are typically required in such systems. 
     Thus, there is a need to produce high-power RF signals with very low average power, such as under five Killowatts. 
     SUMMARY OF THE INVENTION 
     An apparatus has a Radio Frequency (RF) signal generator to produce RF signals phase shifted relative to one another in accordance with RF frequency waveform parameters. Amplifier chains process the RF signals to produce channels of amplified RF signals. Each amplifier chain has amplifiers and at least one amplifier has a tunable gate voltage synchronized with the RF signals. 
    
    
     
       BRIEF DESCRIPTION OF THE FIGURES 
       The invention is more fully appreciated in connection with the following detailed description taken in conjunction with the accompanying drawings, in which: 
         FIG.  1    illustrates a system configured in accordance with an embodiment of the invention. 
         FIG.  2    more fully characterizes components of  FIG.  1   . 
         FIG.  3    illustrates a power sequencer utilized in accordance with an embodiment of the invention. 
         FIG.  4    illustrates power electronics utilized in accordance with an embodiment of the invention. 
         FIG.  5    illustrates power electronics control signals utilized in accordance with an embodiment of the invention. 
         FIG.  6    illustrates an RF signal utilized in accordance with an embodiment of the invention. 
         FIG.  7    illustrates the system of  FIG.  1    utilizing a reflector and mechanical gimbal  702 . 
     
    
    
     Like reference numerals refer to corresponding parts throughout the several views of the drawings. 
     DETAILED DESCRIPTION OF THE INVENTION 
       FIG.  1    illustrates an RF signal generating apparatus  100 . The RF signal may be generated in response to a user command entered at a keyboard. In one embodiment, the RF signal is generated in response to the identification of a target by a target detector  101 , such as a camera utilizing computer vision algorithms. Consider the case of an unmanned aerial vehicle or drone, the target detector  101  collects a signature characterizing the flight attributes of the drone. The target detector  101  also collects free space parameters associated with the drone, such as azimuth angle, elevation and range. Embodiments of the invention collect this information when the target is 500 to 300 meters from the target detector  101 . The signature and free space parameters are passed from the target detector to a central computer  102 . 
     The central computer  102  classifies the target and selects RF waveform parameters, which are passed to an RF signal generator  103 . The RF signal generator  103  creates RF signals in accordance with the RF waveform parameters. Each RF signal has a waveform of the frequency, pulse width, pulse repetition interval and intra-pulse modulation specified by the RF waveform parameters received from the central computer  102 . 
     The RF signal generator  103  produces RF signals for multiple channels that are applied to amplifier chains  104 _ 1  through  104 _N. The RF signals for the multiple channels are phase shifted relative to one another in accordance with RF frequency waveform parameters. In one embodiment, the phase shifting is digitally performed within the RF signal generator  103 . Alternately, analog phase shifters may shift the RF signals prior to applying them to the amplifier chains  104 _ 1  through  104 _N. 
     Each amplifier chain has a serial sequence of solid state power amplifiers, each of which has a gate voltage on set point derived from an automatic calibration operation, as detailed below. Each amplifier chain produces an amplified RF signal. In one embodiment, a mW RF signal from the RF signal generator  103  is amplified to kWs. The amplifier chain may utilize a combination of solid state amplifiers, including silicon laterally-diffused metal-oxide semiconductors, Gallium Nitride, Scandium Aluminum Nitride, GaAs and InP. 
     The channels of RF signals from the amplifier chains  104 _ 1  through  104 _N are applied to an antenna array  106 . Each amplifier chain has a corresponding antenna in the antenna array  106 . The antenna array  106  broadcasts the channels of RF signals as a steered composite RF signal with Megawatts of radiated power. That is, individual RF signals emitted from different antennae in the antenna array  106  interact in free space to generate a composite RF signal that is directed to a specified location corresponding to the location of the target. The antenna array  106  may include a mechanical gimbal to position individual antennae. 
     The RF signal generator  103  also sends control signals to the power sequencer  105 . The control signals gate amplifiers in the amplifier chains  104 _ 1  through  104 _N to produce the channels of RF signals. The control signals ensure that little (e.g., micro to nano amps) leakage or quiescent current is drawn when an RF signal is not being generated. The leakage and quiescent current can be quite large in high power amplifiers circuits if not gated. In one embodiment, the RF signals and power gating signals are turned on and off in 10s of nanoseconds. 
     The amplified RF signals from the amplifier chains  104 _ 1  through  104 _N are applied to an antenna array  106 . The phased array RF signals form a steered composite RF signal to disable a target, typically when it is approximately 100 meters from the antenna array  106 . The steered composite RF signal has Megawatts of radiated power. 
     System  100  also includes an AC power source  107  for the different elements of system  100 . The AC power source may operate with a power distributor  108 , which applies power to the power sequencer  105 . In one embodiment, the power distributor  108  converts from AC to DC power. Generally, the conversion from AC to DC can happen either locally at each amplifier or at the system level. 
       FIG.  2    illustrates details of certain components in system  100 . Central computer  102  includes a processor or central processing unit  200  connected to a memory  202 . The memory  202  stores instructions executed by processor  200 . The instructions include a target classifier  204 . In one embodiment, the target classifier  204  matches the signature of the attributes of the target to a waveform in a waveform look-up table  206 . The waveform selector  208  designates a waveform to disable the target. The designated waveform also includes free space parameters to insure that the steered composite RF signal intercepts the target. The steered composite RF signal is formed by a collection of phase offset RF signals. The central computer passes RF waveform parameters to the RF signal generator  103 . 
     In one embodiment, the RF signal generator  103  is implemented as an RF system on a Chip Field Programmable Gate array (RFSoC FPGA). The RFSoC FPGA  103  includes a gate array  210  and a direct digital synthesizer  212  that creates waveforms of the frequency, pulse width, pulse repetition interval and intra-pulse modulation specified by the RF frequency waveform parameters generated by the central computer  102 . The waveforms are passed to a collection of digital-to-analog (DAC) converters  214 _ 1  through  214 _N. Outputs from the DACs  214 _ 1  through  214 _N are optionally conditioned by filters  216 _ 1  through  216 _N. The filters  216 _ 1  through  216 _N may filter the RF signals to a frequency band of interest. The outputs from the RF signal generator  103  are applied to amplifier chains  104 _ 1  through  104 _N. Each amplifier chain terminates in an antenna of antenna array  106 , such as antennae  220 _ 1  through  220 _N. 
       FIG.  3    is a block diagram of different components of  FIGS.  1  and  2   , including the RF signal generator  103 , power sequencer  105 , and an amplifier chain  104 _ 1 . The RF signal generator  103  receives a control signal from central computer  102  on node  301 . A synchronizing clock signal is received on node  303 . 
     A broadcast signal on node  304 , an Ethernet signal in one embodiment, is sent to a plurality of power sequencing smart slave units  309 . In the one embodiment, the broadcast signal is distributed through a router  307 . The broadcast signal initiates a calibration mode in smart slave circuits  509 , such that they identify the optimal “on” set point gate voltage for the power amps  311 . 
     The RF signal generator  103  sends a very fast signal with deterministic delay, such as a Low Voltage Differential Signal (LVDS) to power sequencer  105 . The power sequencer  105  operates as a master power sequencing gating unit that simultaneously controls smart slave devices  309 . In particular, the power sequencer  105  sends a voltage to the slave units  309  and the slave units  309  offset this master voltage with their individual voltage offsets that they established in calibration mode, so that each power amplifier has an optimal gate voltage. Many power amplifiers have different optimal set gate voltages for “on” operation; the disclosed circuits are configured such that each individual power amp  311  has its own set point. 
     The RF signal generator  103  synchronizes using “on” signals applied to the power sequencers  105 . The RF signal generator  103  also applies an RF signal on node  310 , which is propagated through power amps  311 . The power amp chain may have one or more filters  312 . A coupler  313  may be used to allow power levels to be read back to the RF controller  302 . More particularly, the feedback includes information on the phase, amplitude, power level and timing of the power amplifiers. This feedback is taken into account to update timing and control algorithms. 
     The RF signal is amplified through the power amps  311  and is sent to antenna  314 . The output from the different antennae of the antenna array  106  form a steered composite RF signal. 
       FIG.  4    illustrates the RF signal generator  103  applying an “on” signal to the power sequencer  105 , which operates as a master power gating and sequencing circuit that controls slave power amplifiers  311 . In one embodiment, this signal is a Low voltage differential signal (LVDS) that controls a switch  403 , which causes current from power supply  404  to flow during an “on” state and stops current flow in “off” state. In one embodiment, the power supply voltage  404  is an offset voltage of about 3 volts, which is added to an off voltage V OFF    406  when the switch  403  is closed. Since the offset voltage V OFF    406  is about −5 volts and the power supply voltage  404  is 3 volts, the output voltage on node  409  is about −2 volts, which is approximately the gate voltage that turns on Gallium Nitride transistors  410 . When the switch is open, the output voltage on node  409  defaults back to V OFF , which is −5 volts in one embodiment, which is the gate voltage that turns Gallium Nitride transistors off and reduces leakage current down to about 10 microamps. 
     Node  411  carries a broadcast signal that initiates the auto-calibrate operation of the smart slave circuits  309 . In one embodiment, each smart slave circuit  309  is implemented with an FPGA configured to determine the optimal gate voltage set point for turning on a slave amplifier. 
     Digital to analog converter (DAC)  413  provides an offset voltage that gets added to the master voltage on node  409 . This offset voltage is tuned to each individual power amp  410  to provide optimal set point bias voltage V G1  on node  414  and maximum power out from the power amp  410 . It also enables optimum voltage in the “off” state and minimizes leakage current. The master-slave architecture facilitates fine grained voltage offsets, which is critical to the operation of many transistors, which may be sensitive to gate voltage offsets at the millivolt level. The disclosed technology maximizes voltage offset resolution. 
     The smart slave  309  controls a plurality of DACs  413  and stores different optimum set points for both the on and off states for each power amp. In the auto-calibration mode, the current sensor  415  is used to feed back a current reading to the smart slave  309 . This voltage offset on node  413  is tuned very slightly, by the millivolt in one embodiment, until the current sensed from  415  reaches an optimum current value, as per the data sheets for the power amps  410 . This voltage offset is stored. This process is repeated to minimize the current in “off” state. The current can also be sensed during active operation to determine the viability of the power amp. If the current starts to degrade or change or significantly decrease, this can indicate that the amplifier is damaged and needs to be replaced, or can indicate that the temperature is out of range for optimal operation. 
     The capacitor  416  can be tuned to change the rise and fall time for the gate bias signal on node  414 . In some embodiments, capacitor  416  is real time programmable by the smart control FPGA  309 , such as by a series of switches, to include more or less capacitance in the feedback path  416 . This is important because different power amps  410  each have a different gate capacitance. Capacitor  416  is tuned based on the gate capacitance for optimal operation. Tuning capacitor  416  affects how fast or slow the rise time is on the gate voltage at node  414 , this effects speed and efficiency of the power gating. Changing the charge on capacitor  416  can also change the amount of time the power amp rings or oscillates. In other embodiments, capacitor  416  is configured to tune the rise and fall time for very fast operation. 
       FIG.  5    illustrates waveforms that may be used in conjunction with the circuitry of  FIG.  4   . The supply voltage  501  (V SUPPLY  in  FIG.  4   ) to the power amp ( 410  in  FIG.  4   ) is turned on first. Alternately, it may be left on all the time. The gate voltage waveform  502  is applied to node  414  of  FIG.  4   . Then, the RF signal from RF signal generator  103  is applied to node  414 . This example is for a 65 Volt Gallium Nitride (GaN) solid state power amplifier, but the principle may generally apply to any solid state power amplifier. The drain voltage  501  toggles from 0 Volts to 65 Volts. Then, the source current is tuned from −5 Volts to −2 Volts, where it is considered “open” and the transistor is “on” so that a quiescent current starts to flow. Finally, the RF input signal  503  is applied and the transistor draws active power once the RF power is on, in some embodiments up to 30 amps of current create 1,500 watts of power out of the transistor  410 . 
     The RF signal  503  is sent out as a short pulse, for example, as short as 10 ns or as long as milliseconds. The length of the pulse depends on the type of target. After the RF pulse is complete, the source voltage is pinched off back down to −6 Volts, and then shortly after the drain voltage is tuned from 65 Volts down to 0 Volts and the transistor is off and therefore draws minimal current. 
       FIG.  6    illustrates a timing diagram showing a non-linear pulse train  601  with uneven pulses. The pulse train  801  is sent through power amp  410 , where the RF and voltage bias is turned on and off very quickly (e.g., 10s of nanoseconds). In one embodiment, the pulses are in an arbitrary pattern at a frequency of 1 GHz. 
       FIG.  7    illustrates a system  700  corresponding the system  100  of  FIG.  1   . However, in this embodiment, the antenna array  106  transmits its RF power signal to a reflector  700 . For example, 16 antennae operating at the L-band frequency with half-wavelength spacing may transmit into a 3 meter reflector dish. The reflector dish may have a subreflector. A mechanical gimbal  702  may control the position of the reflector  700  in response to control signals from central computer  102 . 
     The 3 meter reflector dish provides 28.1 dBi, or 645× linear magnification of the energy. In one embodiment, the reflector dish is fed by a 16 element phased array antenna in a 4×4 array. At a 1% duty cycle and 70% power efficiency, the power system only requires 550 watts of DC power output, enabling a small power supply. 
     The foregoing description, for purposes of explanation, used specific nomenclature to provide a thorough understanding of the invention. However, it will be apparent to one skilled in the art that specific details are not required in order to practice the invention. Thus, the foregoing descriptions of specific embodiments of the invention are presented for purposes of illustration and description. They are not intended to be exhaustive or to limit the invention to the precise forms disclosed; obviously, many modifications and variations are possible in view of the above teachings. The embodiments were chosen and described in order to best explain the principles of the invention and its practical applications, they thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. It is intended that the following claims and their equivalents define the scope of the invention.