Patent Publication Number: US-2022231170-A1

Title: Active element and manufacturing method thereof

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application claims the priority benefit of Taiwan application serial no. 110101700, filed on Jan. 15, 2021. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification. 
     BACKGROUND 
     Technical Field 
     The disclosure relates to an element and a manufacturing method thereof, and particularly relates to an active element and a manufacturing method thereof. 
     Description of Related Art 
     A light-emitting element array display device is composed of a plurality of light-emitting elements arranged in an array disposed on a substrate. Inheriting properties of the current light-emitting elements, the light-emitting element array display device is power saving, and has high efficiency, high brightness, fast response speed, etc. In order to drive the light-emitting elements, a low temperature poly-silicon (LTPS) thin film transistor is often used as a driving element, accompanied by an indium-gallium-zinc oxide (IGZO) thin film transistor used as a switching element. However, if the used LTPS thin film transistor has a relatively low subthreshold swing, when a display brightness value is relatively low, the brightness is likely to be changed because of a current change, which reduces the display quality. In addition, if the used IGZO thin film transistor has a relatively high a subthreshold swing, then a switching speed is relatively slow, which may result in image lag. 
     SUMMARY 
     The disclosure is directed to an active element and a manufacturing method thereof, in which poor display quality is improved. 
     The disclosure provides an active element including a substrate, a switching bottom gate, a driving bottom gate, a first gate insulating layer, a switching channel, a driving channel, a second gate insulating layer, a switching top gate, and a driving top gate. The switching bottom gate and the driving bottom gate are disposed on the substrate. The first gate insulating layer is disposed on the substrate and covers the switching bottom gate and the driving bottom gate. 
     The switching channel and the driving channel are disposed on the first gate insulating layer. The driving channel has a low potential end. The low potential end is electrically connected to the driving bottom gate. The second gate insulating layer is disposed on the first gate insulating layer and covers the switching channel and the driving channel. A thickness of the second gate insulating layer is greater than a thickness of the first gate insulating layer. The switching top gate and the driving top gate are disposed on the second gate insulating layer. The switching top gate is electrically connected to the switching bottom gate. 
     In an embodiment of the disclosure, the thickness of the second gate insulating layer is greater than or equal to 4 times of the thickness of the first gate insulating layer. 
     In an embodiment of the disclosure, the thickness of the second gate insulating layer is equal to 5 times of the thickness of the first gate insulating layer. 
     In an embodiment of the disclosure, a material of the switching channel is indium-gallium-zinc oxide (IGZO). 
     In an embodiment of the disclosure, a material of the driving channel is low temperature poly-silicon. 
     In an embodiment of the disclosure, a thickness of a part of the first gate insulating layer between the switching bottom gate and the switching channel is formed to be equal to a thickness of a part of the first gate insulating layer between the driving bottom gate and the driving channel. 
     In an embodiment of the disclosure, a thickness of a part of the second gate insulating layer between the switching bottom gate and the switching channel is formed to be equal to a thickness of a part of the second gate insulating layer between the driving bottom gate and the driving channel. 
     In an embodiment of the disclosure, a part of the switching channel is doped with hydrogen ions. 
     In an embodiment of the disclosure, a part of the driving channel is doped with phosphorus ions or arsenic ions. 
     In an embodiment of the disclosure, the active element further includes a passivation layer disposed on the second gate insulating layer and covering the switching top gate and the driving top gate. 
     The disclosure provides a manufacturing method of an active element including following steps. A switching bottom gate and a driving bottom gate are formed on a substrate. A first gate insulating layer is formed on the substrate. The first gate insulating layer covers the switching bottom gate and the driving bottom gate. A switching channel and a driving channel are formed on the first gate insulating layer. A second gate insulating layer is formed on the first gate insulating layer. The second gate insulating layer covers the switching channel and the driving channel. A thickness of the second gate insulating layer is greater than a thickness of the first gate insulating layer. A switching top gate and a driving top gate are formed on the second gate insulating layer, and the switching top gate is electrically connected to the switching bottom gate, and a low potential end of the driving channel is electrically connected to the driving bottom gate. 
     In an embodiment of the disclosure, the thickness of the second gate insulating layer is formed to be greater than or equal to 4 times of the thickness of the first gate insulating layer. 
     In an embodiment of the disclosure, the thickness of the second gate insulating layer is formed to be equal to 5 times of the thickness of the first gate insulating layer. 
     In an embodiment of the disclosure, a material of the switching channel is indium-gallium-zinc oxide (IGZO). 
     In an embodiment of the disclosure, a material of the driving channel is low temperature poly-silicon. 
     In an embodiment of the disclosure, a thickness of a part of the first gate insulating layer between the switching bottom gate and the switching channel is equal to a thickness of a part of the first gate insulating layer between the driving bottom gate and the driving channel. 
     In an embodiment of the disclosure, a thickness of a part of the second gate insulating layer between the switching bottom gate and the switching channel is equal to a thickness of a part of the second gate insulating layer between the driving bottom gate and the driving channel. 
     In an embodiment of the disclosure, the manufacturing method of the active element further includes performing a doping process to dope a part of the switching channel with hydrogen ions after forming the switching top gate and the driving top gate. 
     In an embodiment of the disclosure, the manufacturing method of the active element further includes performing a doping process to dope a part of the driving channel with phosphorus ions or arsenic ions after forming the switching top gate and the driving top gate. 
     In an embodiment of the disclosure, the manufacturing method of the active element further includes forming a passivation layer on the second gate insulating layer after forming the switching top gate and the driving top gate, where the passivation layer covers the switching top gate and the driving top gate. 
     Based on the above description, in the active element and the manufacturing method thereof of the disclosure, not only the subthreshold swing of the driving element is maintained higher, but also the subthreshold swing of the switching element is reduced, thereby improving the display quality. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The accompanying drawings are included to provide a further understanding of the disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the disclosure and, together with the description, serve to explain the principles of the disclosure. 
         FIG. 1  to  FIG. 4  are cross-sectional views of flows of a manufacturing method of an active element according to an embodiment of the disclosure. 
         FIG. 5  is a diagram of an equivalent circuit of the active element of  FIG. 4 . 
     
    
    
     DESCRIPTION OF THE EMBODIMENTS 
       FIG. 1  to  FIG. 4  are cross-sectional views of flows of a manufacturing method of an active element according to an embodiment of the disclosure. Referring to  1 , the manufacturing method of the active element of the embodiment is to first form a switching bottom gate G 12  and a driving bottom gate G 22  on a substrate  110 . When forming the switching bottom gate G 12  and the driving bottom gate G 22 , for example, a conductor layer is formed first, and then the conductor layer is patterned to form the switching bottom gate G 12  and the driving bottom gate G 22 . Then, a first gate insulating layer  120  is formed on the substrate  110 . The first gate insulating layer  120  covers the switching bottom gate G 12  and the driving bottom gate G 22 . A material of the first gate insulating layer  120  is, for example, a dielectric material such as silicon oxide, silicon nitride, or silicon oxynitride. 
     Then, a switching channel C 10  and a driving channel C 20  are formed on the first gate insulating layer  120 . In the embodiment, a material of the switching channel C 10  is indium-gallium-zinc oxide, and a material of the driving channel C 20  is low temperature poly-silicon, but the disclosure is not limited thereto. For example, a material of the switching channel C 10  may also be zinc oxide (ZnO), tin oxide (SnO), indium-zinc oxide (IZO), gallium-zinc oxide (GZO), zinc-tin oxide (ZTO), indium-tin Oxide (ITO) or other suitable metal oxide semiconductor materials. When the materials of the switching channel C 10  and the driving channel C 20  are different, the switching channel C 10  and the driving channel C 20  may be formed separately one after another. 
     Then, referring to  FIG. 2 , a second gate insulating layer  130  is formed on the first gate insulating layer  120 . The second gate insulating layer  130  covers the switching channel C 10  and the driving channel C 20 . A thickness T 14  of the second gate insulating layer  130  is greater than a thickness T 12  of the first gate insulating layer  120 . Here, the thickness T 14  of a part of the second gate insulating layer  130  between the switching bottom gate G 12  and the switching channel C 10  is compared with the thickness T 12  of a part of the first gate insulating layer  120  between the switching bottom gate G 12  and the switching channel C 10 . In the embodiment, the thickness of the first gate insulating layer  120  at different positions is approximately the same, and the thickness of the second gate insulating layer  130  at different positions is also approximately the same, and only a thickness error caused by process factors exists, but the disclosure is not limited thereto. In addition, the thickness in the figure is only schematic, and does not represent the actual thickness. 
     Then, a switching top gate G 14  and a driving top gate G 24  are formed on the second gate insulating layer  130 . When forming the switching top gate G 14  and the driving top gate G 24 , for example, a conductor layer is comprehensively formed first, and then the conductor layer is patterned to form the switching top gate G 14  and the driving top gate G 24 . 
     Then, a doping process may be performed so that a part of the switching channel C 10  and a part of the driving channel C 20  are suitable for connecting electrodes. For example, a part of the driving channel C 20  may be doped with phosphorous ions or arsenic ions, and a part of the switching channel C 10  may be doped with hydrogen ions, but the disclosure is not limited thereto. 
     In an embodiment, a doping process may be comprehensively performed so that a part of the switching channel C 10  that is not located under the switching top gate G 14  is doped with phosphorous ions, and a part of the driving channel C 20  that is not located under the driving top gate G 24  is doped with phosphorous ions. Then, heating is performed to complete the doping process. Then, hydrogen plasma is comprehensively used to perform another doping process, so that the part of the switching channel C 10  that is not located under the switching top gate G 14  is doped with hydrogen ions, and to repair the silicon broken bonds of the driving channel C 20  with hydrogen ions. 
     In another embodiment, a mask layer for shielding the switching channel C 10  may be formed first, and then the doping process may be comprehensively carried out. At this moment, the switching channel C 10  is shielded by the mask layer and will not be doped with phosphorous ions, and the part of the driving channel C 20  that is not located under the driving top gate G 24  is doped with phosphorous ions. Then, heating is performed to complete the doping process. Then, the aforementioned mask layer is removed, and another doping process is comprehensively performed by using hydrogen plasma, so that the part of the switching channel C 10  that is not located under the switching top gate G 14  is doped with hydrogen ions, and to repair the silicon broken bonds of the driving channel C 20  with hydrogen ions. 
     In another embodiment, the doping process may be comprehensively performed so that the part of the switching channel C 10  that is not located under the switching top gate G 14  is doped with phosphorous ions, and the part of the driving channel C 20  that is not located under the driving top gate G 24  is doped with phosphorous ions. Then, heating is performed to complete the doping process. Then, the mask layer for shielding the switching channel C 10  is formed, and then the hydrogen plasma is comprehensively used to perform another doping process. At this moment, the switching channel C 10  is shielded by the mask layer and will not be doped with hydrogen ions, and the part of the driving channel C 20  is repaired with hydrogen ions. 
     In another embodiment, phosphorus ions may be comprehensively used to perform the doping process. Then, a silicon hydride nitride (SiNx:H) layer is formed, which is disposed on the second gate insulating layer  130  and covers the switching top gate G 14  and the driving top gate G 24 . Then, heating is performed to complete the doping process. In this way, the part of the switching channel C 10  that is not located under the switching top gate G 14  can be doped with phosphorus ions and hydrogen ions, and the part of the driving channel C 20  that is not located under the driving top gate G 24  is doped with phosphorus ions and the part of the driving channel C 20  is repaired with hydrogen ions. 
     Then, referring to  FIG. 3 , a passivation layer  140  is selectively formed on the second gate insulating layer  130 , where the passivation layer  140  covers the switching top gate G 14  and the driving top gate G 24 . The passivation layer  140  is, for example, an organic flat layer, and a material thereof is, for example, polyester (PET), polyolefin, polypropylene, polycarbonate, polyalkylene oxide, polyphenylene, polyether, polyketone, polyalcohol, polyaldehyde, or other suitable materials, but the disclosure is not limited thereto. The material of the passivation layer  140  may also be silicon hydride nitride or silicon oxide. 
     Referring to  FIG. 4 , the switching top gate G 14  is electrically connected to the switching bottom gate G 12 , and a low potential end C 22  of the driving channel C 20  is electrically connected to the driving bottom gate G 22 . In the embodiment, a connecting member B 10  and a connecting member B 20  penetrating through the passivation layer  140  and partially located in the passivation layer  140  are formed. The connecting member B 20  further penetrates through the second gate insulating layer  130 . Moreover, in the step of  FIG. 2 , when the switching top gate G 14  and the driving top gate G 24  are formed, a connecting member G 12 A and a connecting member G 22 A are also formed. Therefore, the switching top gate G 14  may be electrically connected to the switching bottom gate G 12  through the connecting member B 10  and the connecting member G 12 A, and the low potential end C 22  of the driving channel C 20  may be electrically connected to the driving bottom gate G 22  through the connecting member B 20  and the connecting member G 22 A. Here, although the method of electrically connecting the switching top gate G 14  to the switching bottom gate G 12  and electrically connecting the low potential end C 22  of the driving channel C 20  to the driving bottom gate G 22  is described as an example, the disclosure is not limited thereto. 
     Referring to  FIG. 4  again, the active element  100  of the embodiment includes the substrate  110 , the switching bottom gate G 12 , the driving bottom gate G 22 , the first gate insulating layer  120 , the switching channel C 10 , the driving channel C 20 , the second gate insulating layer  130 , the switching top gate G 14  and the driving top gate G 24 . The switching bottom gate G 12  and the driving bottom gate G 22  are disposed on the substrate  110 . The first gate insulating layer  120  is disposed on the substrate  110  and covers the switching bottom gate G 12  and the driving bottom gate G 22 . The switching channel C 10  and the driving channel C 20  are configured on the first gate insulating layer  120 . The driving channel C 20  has the low potential end C 22 . The low potential end C 22  is electrically connected to the driving bottom gate G 22 . The second gate insulating layer  130  is disposed on the first gate insulating layer  120  and covers the switching channel C 10  and the driving channel C 20 . The thickness of the second gate insulating layer  130  is greater than the thickness of the first gate insulating layer  120 . The switching top gate G 14  and the driving top gate G 24  are disposed on the second gate insulating layer  130 . The switching top gate G 14  is electrically connected to the switching bottom gate G 12 . 
       FIG. 5  is a diagram of an equivalent circuit of the active element of  FIG. 4 . Referring to  FIG. 4  and  FIG. 5 , the switching bottom gate G 12 , the switching channel C 10  and the switching top gate G 14  are a part of a switching element T 10 , and the driving bottom gate G 22 , the driving channel C 20  and the driving top gate G 24  are a part of a driving element T 20 . A high potential end of the switching channel C 10  is electrically connected to a data line DL. A low potential end of the switching channel C 10  is electrically connected to the driving top gate G 24 , and the low potential end of the switching channel C 10  is electrically connected to a light-emitting element  50  through a capacitor CP. The switching bottom gate G 12  and the switching top gate G 14  are electrically connected to a scan line GL. A high potential end of the driving channel C 20  is electrically connected to a power supply VDD. The low potential end C 22  of the driving channel C 20  is electrically connected to the driving bottom gate G 22  and the light-emitting element  50 . The other end of the light-emitting element  50  is electrically connected to a common circuit VSS. 
     According to the above description, the driving element T 20  has the driving bottom gate G 22  and the driving top gate G 24 , and a subthreshold swing of the driving element T 20  of such structure is not obviously changed when the thickness of the first gate insulating layer  120  and the thickness of the second gate insulating layer  130  are changed. Therefore, the subthreshold swing of the driving element T 20  may be maintained at a higher state, thereby improving the stability of the light-emitting element  50  at low brightness. In addition, since the thickness T 14  of the second gate insulating layer  130  is greater than the thickness T 12  of the first gate insulating layer  120 , a subthreshold swing of the switching element T 10  may be maintained at a low state, thereby improving a turning on/off speed of the light-emitting element  50 . 
     In the embodiment, the thickness T 12  of the part of the first gate insulating layer  120  between the switching bottom gate G 12  and the switching channel C 10  is equal to the thickness T 22  of the part of the first gate insulating layer  120  between the driving bottom gate G 22  and the driving channel C 20 . Moreover, in the embodiment, the thickness T 14  of the part of the second gate insulating layer  130  between the switching bottom gate G 12  and the switching channel C 10  is equal to the thickness T 24  of the part of the second gate insulating layer  130  between the driving bottom gate G 22  and the driving channel C 20 . Since the thickness of the first gate insulating layer  120  of the embodiment at the above-mentioned different positions is approximately the same, and the thickness of the second gate insulating layer  130  at the above-mentioned different positions is also approximately the same, so that the manufacturing process is relatively simple and the cost is low. 
     In the embodiment, the active element  100  further includes the passivation layer  140  disposed on the second gate insulating layer  130  and covering the switching top gate G 14  and the driving top gate G 24 . 
     In the embodiment, the thickness T 14  of the second gate insulating layer  130  is formed to be greater than or equal to 4 times of the thickness T 12  of the first gate insulating layer  120 . For example, the thickness T 14  of the second gate insulating layer  130  is formed to be equal to 5 times of the thickness T 12  of the first gate insulating layer  120 . In this way, the subthreshold swing of the driving top gate G 24  of the driving element T 20  is increased significantly, while the subthreshold swing of the switching bottom gate G 12  of the switching element T 10  is not affected. 
     In summary, in the active element and the manufacturing method thereof of the disclosure, the double gate design reduces the influence of the thickness change of the gate insulating layer of the switching element on the subthreshold swing of the switching element, and the double gate design makes the thickness change of the gate insulating layer of the driving element to be adapted to adjust the subthreshold swing of the driving element. Therefore, the subthreshold swing of the driving element may be increased under a premise of maintaining a low subthreshold swing of the switching element, thereby improving the display quality.