Patent Publication Number: US-5835711-A

Title: Method and system for implementing multiple leaky bucket checkers using a hybrid synchronous/asynchronous update mechanism

Description:
TECHNICAL FIELD OF THE INVENTION 
     This invention relates in general to computer networks and in specific to systems and methods for monitoring and regulating data sent over a large number of network connections simultaneously. 
     BACKGROUND OF THE INVENTION 
     A network service provider, an entity which provides network connections to a network user or data source, must carefully monitor and regulate the amount of data sent over its network. Otherwise, one or more sources could send too much data within a certain time period and overload the network. This overload could disrupt network service for other sources using the network. 
     Network service providers require techniques for monitoring and regulating network traffic to ensure that a source cannot overload the network. One such technique is the &#34;leaky bucket&#34; (&#34;LKB&#34;) checker. An LKB monitors and controls a network connection&#39;s long term average transmission rate and maximum transmission rate for a fixed time period (the &#34;burst size&#34;). LKB uses transmission credits or tokens which are periodically generated at a fixed rate and which a data source can accumulate up to a maximum limit. Any token received while a source already has the maximum is simply ignored. Each token allows the transmission of a fixed amount of data. Thus, the token generation rate determines the long term sustained transmission rate to which a source is entitled, while the token pool size bounds the maximum burst size the source can transmit. 
     Normally, the hardware for implementing an LKB is located outside of the users&#39; premises in network concentrators. A network concentrator is a device used to combine many different users&#39; network connections into a single link which can then be connected to a central network. An LKB located at the concentrator can monitor and regulate many different users at the same time. 
     An LKB must continually track and update the number of tokens available and/or used by each connection to the concentrator. To do these operations, the LKB tracks the amount of data sent over the connection since the last update, the time that has elapsed since the last update and the number of tokens left in the pool after each update is performed. Specifically, given a token pool size M, a token generation rate G, a current time t, a time that has elapsed since the last update t -   and a packet size s, the update algorithm for calculating the number of tokens, T, remaining in the bucket is: 
     
         T=min{M, T+G(t-t.sup.-)} 
    
     if (s&gt;T) then error (violation) 
     else T=T-s 
     Obviously, to perform this update algorithm on each input of the concentrator requires significant processor resources. The operating rate of the processor that implements the LKB must be such that the time between two clock ticks is no longer than the time between two successive data unit arrivals on a given input link. For example, given operating conditions typical of high-speed networks, i.e., a data unit size of 64 bytes and input link speeds of 800 Megabits/second, the maximum operating tick can last no longer than 640 nsec. Once this base clock rate is determined, the range and precision needed for the different LKB parameters and state variables can be determined. 
     For each connection, it is necessary to store in memory both the value of the LKB parameters for that connection and the state of that LKB at the time of its last update. Based on the above algorithm, the state variables kept and updated for each leaky bucket are t -   and T, while the associated parameters are G and M. 
     Under a purely synchronous approach, as disclosed in U.S. Pat. No. 4,896,316, issued Jan. 23, 1990, the state variables of all connections are updated at every clock tick. This is clearly computationally too intensive when thousands of connections are being monitored. 
     Under a purely asynchronous approach, as disclosed in I. Cidon, I. Gopal and R. Guerin, Bandwidth Management and Congestion Control in plaNET, IEEE Common. Mag. 29, pp. 54-63, October 1991, the state variables of a given connection are only updated upon arrival of a block from that connection. This approach is also likely to lead to large storage and processing costs. For example, t -   is only updated upon packet arrivals. In order to determine the number of bits necessary to represent t - , its maximum possible value must be determined. Assuming that the length between packet arrivals is no greater than M/G, the maximum value of t -   is M/G. This quantity can be as large as 1,000 seconds for a connection with a token generation rate of 16 Kbps and a token pool size of 2 Mbtyes. Under the sample values assumed above for link speed and block size, the operating clock rate is 640 nsec. Therefore, 1,000 seconds represents about 10 9  clock ticks. Representing the value t -  would then require about 30 bits which, when multiplied by the number of connections, is prohibitive in terms of computation and storage costs. 
     In addition, neither of the above approaches allows multiple leaky bucket checkers for each network connection. The processor and storage costs associated with each approach increase correspondingly with the number of leaky bucket checkers per connection. 
     SUMMARY OF THE INVENTION 
     Therefore, it is an object of the present invention to provide a system and method for implementing a leaky bucket checker which can simultaneously monitor a large number of connections. 
     It is a further object of the present invention to provide a system and method for implementing a leaky bucket checker whereby less computational power is required than in the prior art. 
     It is a further object of the present invention to provide a system and method for implementing a leaky bucket checker whereby less storage space is required than in the prior art. 
     It is a further object of the present invention to provide a system and method for implementing a leaky bucket checker whereby multiple leaky buckets can be used to monitor each connection. 
     The above and other objects are achieved by a leaky bucket checker which combines synchronous updates with event driven asynchronous updates triggered by packet arrivals. A synchronous update is performed exactly as an event-driven update by assuming that a packet of length zero has arrived at the time of the update. These updates are performed in a round robin fashion on each connection. Therefore, assuming that one such update can be performed in each clock tick, the maximum bit representation of the last update time state variable can be limited to N bits for 2 N  total connections. Given the reduced processing and storage costs, a great number of network connections and leaky bucket checkers is possible. 
     The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the conception and the specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which: 
     FIG. 1 is a data processing system adopted for execution of a preferred embodiment of the present invention; 
     FIG. 2 is a high-level block diagram of a Leaky Bucket Monitoring Logic chip; 
     FIG. 3 is representation of a data structure stored in the Foreground Memory of the Leaky Bucket Monitoring Logic chip; 
     FIG. 4 is a representation of a data structure stored in the Background Memory of the Leaky Bucket Monitoring Logic chip; and 
     FIG. 5 is a representation of the initial values of the data structure of FIG. 4. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Network connections are characterized by traffic parameters that are functions of the contract they have with the network. Roughly speaking, these parameters specify the average or sustained rate, peak rate and burst size to which the connection is entitled. The leaky bucket (&#34;LKB&#34;) associated with the connection is responsible for monitoring its traffic to insure that it behaves in compliance with its contract. The Leaky Bucket Monitoring Logic (&#34;LBML&#34;), detailed below, implements multiple LKB checkers for a large number of connections and ensures that each individual data stream is compliant with its contract. 
     The LBML maintains two leaky bucket checkers per connection: one checks on incoming green (high priority) packets for compliance with the amount of reserved traffic to which the connection is entitled; the other checks both green and red (low priority) packets for peak rate violations. Data is assumed to arrive in blocks of 64 bytes and so packet sizes are counted in terms of blocks with one token allowing transmission of one 64-byte block. 
     The LBML only performs checking, i.e., determines compliance with the network contract but does not enforce it. However, when a connection is identified as non-compliant, the LBML has the ability to take a number of corrective actions. These actions range from flushing violating packets to tagging them as low priority. However, when a violation is detected the LBML may not always be in a position to take the corrective action on the offending packet itself. Instead, violation information is kept between packets through the use of violation status bits, one for each type of violation (green and peak), that are updated each time the LBML updates the leaky buckets. Thus, any violation penalty can then be applied to the next arriving packet of the appropriate type that belongs to the same connection. Of course, the LBML resets the violation status bits after the penalties are applied. 
     The LBML also maintains, for each connection, a count of quantities such as the number of green packets, red packets and violating packets. This information is useful for monitoring and billing purposes and may also be used by an offline violation detection module that instructs the LBML on what action it should take on the violating packets of a given connection. When a violation occurs, for example, a module may instruct the LBML to flush the packet, mark the packet or do nothing. 
     An important aspect of the leaky bucket checking implementation in the LBML is the range of precision of the leaky bucket parameters for both green packet and peak rate monitoring. In addition to specifying a 64-byte block as being the data unit associated with a token, it is also necessary to specify other network and contract variables. An aggregate network input speed of 800 Mbps, which provides an upper bound on the maximum possible token generation rate, is assumed. The bandwidth allocation granularity is taken to be 16 Kbps, which determines both the minimum token generation rate and the size of its increments. The maximum burst size is chosen to be 2 megabytes. In all cases, 16 bits are sufficient to represent the maximum values. 
     The LBML uses a clock cycle of 40 nsec. The LBML logic performs an update operation on the LKB variables in no greater than 640 nsec. This speed is sufficient to process the incoming data given the parameters stated above, i.e.: 
     800 Mbps/8 bits=10 8  bytes/second; and 
     64-byte packet/10 8  =640 nsec/packet. 
     The LBML maintains the leaky bucket state of all connections in a table that has as many entries as their are connections. The LBML updates each entry in the table by combining synchronous updates with asynchronous event driven updates triggered by packet arrivals. A synchronous update is performed exactly as an event driven one by assuming that packet of zero length has arrived at the time of the update. This update is performed on one of the connections in a round robin fashion every 640 nsec by the LBML. Since the table used to store connection information (leaky bucket parameters and states) is assumed to have about 64K entries, each connection&#39;s leaky bucket state will be updated at least once every 41 msec (64K*640 nsec=41 msec). 
     It is possible that both a synchronous and asynchronous update need to take place for the same connection entry within a single clock tick. It is, therefore, necessary to specify how the LBML arbitrates this situation. If only a synchronous update were performed, then the incoming packet would not be processed. If only the asynchronous update were performed, then, depending on the packet type, some fields of the LKB table might not be updated and could become stale before the next synchronous update. The LBML deals with this situation by updating all fields appropriately in cases where both an asynchronous and a synchronous need to be performed simultaneously. For example, in such instances the green packet leaky bucket parameters are updated even upon receipt of a red packet (a green packet size of zero is assumed). Note that a synchronous update should not trigger any setting or resetting of the violation status bits. 
     As mentioned earlier, the LBML, in addition to performing a leaky bucket checking function, also provides traffic monitoring information for each connection. In particular it keeps track of red and green packet and block counts as well as violation block counts. If the network transport protocol uses a fixed packet size, then blocks and packets are equal and the LBML only need track one variable. Note that green and peak violations are tracked separately, but only block counts are kept. This represents a trade-off between the available storage space for counters and the accuracy of the violation information being tracked. The counting on incoming packets is done before any action, e.g., flushing or marking, has been taken by the LBML, so that the green and red packets and block counts are representative of the traffic stream generated by the user rather than what is forwarded. For example, in the case of an incoming green packet which is marked red because the green violation status bit was set, the green rather than red packet and block counts are incremented. 
     Similarly, violation counts are updated to reflect the sizes of the offending packets, i.e., they reflect the number of blocks in violation at the leaky bucket checker. This again provides the offline monitoring logic with accurate information on the nature and volume of the actual violation traffic for each connection. This information is useful in determining the appropriate penalty that need be applied on violating packets. 
     A representative data processing system for practicing a preferred embodiment of the LBML chip is depicted in FIG. 1. FIG. 1 illustrates a typical hardware configuration of a network concentrator in accordance with the subject invention having central processing unit 110, such as a conventional microprocessor, random access memory (&#34;RAM&#34;) 112, and a number of peripheral cards 116 interconnected via system bus 118. The cards are organized into banks and slots, with each card in a slot within a bank of slots. Each peripheral card receives data from a network link 120 and sends it on system bus 118. 
     A preferred embodiment of the LBML is as a chip 122 located on system bus 118 so that it can process data received by the peripheral cards 116. The data processing system controls LBML chip 122 and uses it to monitor and regulate the data coming through the network links 120. The data processing system combines the data from the network links 120 into a single outgoing link which can then be connected to a central network (not shown). In a typical network environment, a similar data processing system would provide redundant LKB checking on data received by the central network (not shown). 
     The incoming network links 120 can be of any type of high speed data network. A typical network configuration is a Synchronous Optical Network (&#34;SONET&#34;) physical transport layer using Asynchronous Transfer Mode (&#34;ATM&#34;) for the transmission of data. For a more detailed understanding of high speed data networks, the reader is advised to see G. McClain, Ed., Handbook of Networking &amp; Connectivity, pp.123-65, 1994, which is hereby incorporated by reference. 
     FIG. 2 is a high-level block diagram of LBML chip 122. The chip has four major components: Foreground 210, Background 212, Packet Entry FIFO 214 and Control Bus Slave Logic (&#34;CBSL&#34;) 216. In addition, the chip has five external interfaces: System Interface Bus (&#34;SIB&#34;) 218, Control Bus (&#34;CB&#34;) 220, System Interface Logic (&#34;SIL&#34;) 222, Foreground Memory (&#34;FM&#34;) 224 and Background Memory (&#34;BM&#34;) 226. 
     The Foreground component 210 is divided into 3 logic blocks: Foreground Processing Logic (&#34;FPL&#34;) 228, Foreground Memory Test Logic (&#34;FMTL&#34;) 230 and Foreground Memory Interface Logic (&#34;FMIL&#34;) 232. The Background component 212 is also divided into 3 logic blocks: Background Processing Logic (&#34;BPL&#34;) 234, Background Memory Test Logic (&#34;BMTL&#34;) 236 and Background Memory Interface Logic (&#34;BMIL&#34;) 238. 
     Packet Entry FIFO 214 is used to pass data from FPL 228 to BPL 234. Packet Entry FIFO 214 is an internal RAM macro. It has eight entries and each entry holds one set of information regarding a packet. The size of the fields of an incoming packet status are: 16 bits for connection ID, 4 bits for packet status and 12 bits for packet block count. 
     The control interfaces, SIB 218, CB 220 and SIL 222 are standard interfaces and are used to send and receive data from the other logic on the chip. Such interfaces are well understood by those with ordinary skill in the relevant art. 
     THE FOREGROUND COMPONENTS 
     FM 224 is connected to EMIL 232 via 48-bit data bus 240. EMIL 232 is a simple logic interface to FM 224. EMIL 232 can perform two memory operations in one clock cycle. Each of the two memory operations can be a read or write operation. EMIL 232 is also connected to FPL 228, FMTL 230 and BPL 234. 
     FMTL 230 is connected to FM 224 via EMIL 232. FMTL 230 is used to perform basic hardware integrity tests on FM 224. FMTL 230 supports six test patterns: all &#34;0&#34;; all &#34;1&#34;; &#34;A55A&#34;; &#34;0&#34; walk through; &#34;1&#34; walk through; and scan test. 
     FM 224 stores the connection table used by the LKB. There is a connection table entry for each network connection. The data structure used for each connection table entry is shown in FIG. 3. The entry is divided into four 48-bit words 310-316. Starting from the high order bit, the bits of word 310 signify the following: three reserved bits 318 have no function; Valid Connection (&#34;VC&#34;) bit 320 is &#34;1&#34; for a successful connection and otherwise &#34;0&#34;; eight Maximum Packet Size (&#34;MPS&#34;) bits 322 define the maximum packet size the connection can carry; two Service Class (&#34;SC&#34;) bits 324 are set to &#34;01&#34; for real time, &#34;10&#34; for reserve and &#34;11&#34; for non-reserve service; three Packet Command (&#34;PC&#34;) bits 326, three Green LKB Violation Command (&#34;GVC&#34;) bits 328 and three Peak LKB Violation Command (&#34;PVC&#34;) bits 230 are set to &#34;000&#34; for no action, &#34;001&#34; for sampling packet, &#34;010&#34; for changing packet type, &#34;011&#34; for sampling packet type and &#34;100&#34; for flushing packet; the next 22 bits 332 are reserved; Green LKB Violation Status (&#34;GVS&#34;) bit 334 is &#34;1&#34; to indicate a connection green LKB violation; and Peak LKB Violation Status (&#34;PVS&#34;) bit 336 is &#34;1&#34; to indicate a connection peak LKB violation. 
     Word 312 contains the 24-bit fields Green Packet Counter (&#34;GPC&#34;) 338 and Green Block Counter (&#34;GBC&#34;) 340. Word 314 has two 24-bit fields containing Red Packet Counter (&#34;RPC&#34;) 342 and Red Block Counter (&#34;RBC&#34;) 344. Word 216 contains an 8-bit Maximum Packet Size Violation Counter (&#34;MPSVC&#34;) 346, a 16-bit Green LKB Violation Block Counter (&#34;GVBC&#34;) 348, an 8-bit Service Class Violation Counter (&#34;SCVC&#34;) 350 and a 16-bit Peak LKB Violation Block Counter (&#34;PVBC&#34;) 352. If the table entry is for an invalid connection, denoted by a &#34;0&#34; in VC bit 320, the lower 24 bits of word 316 are used as an invalid connection packet counter. 
     FPL 228 receives the incoming packets and performs preliminary processing. FPL 228 detects the Start Of Packet (&#34;SOP&#34;) command from SIB 218. When a SOP command is detected, FPL 228 parses the service class, type and connection ID from the packet header and saves the information in its internal registers (not shown). FPL 228 uses the connection ID from the packet header to fetch the associated connection data table entry (FIG. 3) from FM 224 via FMIL 232. FPL 228 then compares and processes the data parsed from the packet header with the information in the data structure. After packet processing is completed, FPL 228 puts the connection ID, packet status and Packet Block Count (&#34;PBC&#34;) into Packet Entry FIFO 214. The information in Packet Entry FIFO 214 is used by BPL 234 to further process the packets. 
     There are two different types of packet violations: state independent and state dependent. FPL 228 can detect state independent violations because doing so does not require any complex packet processing. Such violations include the maximum packet size, service class and invalid connection violations. If a packet is larger than the maximum packet size allowed on its connection, FPL 228 flushes the packet and marks the fields of the FIFO 214 packet to indicate that MPSVC 346 should be incremented. If the service class information from the packet header does not match the information in the data structure, FPL 228 flushes the packet and marks the fields of the FIFO 214 packet to indicate that SCVC 350 should be incremented. If VC bit 320 in the table entry is &#34;0,&#34; then the connection is invalid and FPL 228 flushes the packet and marks the fields of the FIFO 214 packet to indicate that the lower 24 bits of word 316 (the invalid connection packet counter) should be incremented. 
     The state dependent violations depend on past packets and include green and peak leaky bucket violations. FPL 228 cannot detect these violations, but can use the information in the connection table to process the results of past violations. If an incoming packet is green and the GVS bit 334 is &#34;1&#34;, then FPL 228 executes the instruction defined in GVC 328. If the packet is green or red and PVS bit 336 is &#34;1&#34;, then FPL 228 executes the instruction defined in PVC 330. 
     If there is no violation, FPL 228 performs the action determined by the value of PC bits 326 in the table entry. Then, for all packet types and violation conditions, FPL 228 places information in Packet Entry FIFO 214 indicating the type of packet and violation status. 
     THE BACKGROUND COMPONENTS 
     BM 226 is connected to BMIL 238 via a 32-bit bus with four parity bits. BMTL 36 is connected to BM 226 via BMIL 238. BMIL 238 and BMTL 236 perform the same functions as their corresponding foreground components, FMIL 232 and FMTL 230, respectively. Like FM 224, BM 226 holds a connection table with an entry for each network connection. Each table entry is comprised of four 32-bit words and holds the LKB variables and parameters. FIG. 4 shows the data structure for each connection table entry in BM 226. FIG. 5 shows the initial values for each connection table entry. 
     Word 410 is divided into 16-bit fields 418 and 420. Field 418 contains the Last Update Time (&#34;LUT&#34;). The LUT holds a value representing the tick count of the processor clock. At initial set up, chip microcode writes the current tick count to the LUT field (518). Field 420 of word 410 holds the Peak Token Generation Rate (&#34;PTGR&#34;). The PTGR is a value representing the number of peak tokens generated per tick in units of 1/64K. At initial set up, chip microcode loads the PTGR with a value determined by the target connection&#39;s network contract. A value of `0000`h indicates that peak token monitoring is disabled. 
     Word 412 is divided into 8-bit field 422, 8-bit field 424 and 16-bit field 426. Field 422 contains the Peak LKB Size (&#34;PLKBS&#34;), which is the maximum number of tokens allowed in the peak LKB. The most significant bit of this field is &#34;0&#34; and is reserved. During initial set up, chip microcode loads the PLKBS field with a value determined by the target connection&#39;s network contract (522). Field 424 contains the Peak Token Count (&#34;PTC&#34;), which is the number of peak tokens in the pool. Like field 422, the most significant bit of field 424 is &#34;0&#34; and is reserved. During initial set up, chip microcode loads the PTC field 424 with the field&#39;s maximum value (524). Field 426 contains the Peak Fraction Token Count (&#34;PFTC&#34;), which is the number of fraction peak tokens in the pool in units of 1/64K. At initial set up, chip microcode loads the value `0000`h into this field (526). 
     Word 414 is divided into 16-bit fields 428 and 430. Field 428 contains the Green LKB Size (&#34;GLKBS&#34;), which is the maximum number of tokens allowed in the green LKB. At initial set up, chip microcode loads this field with a value determined by the connection&#39;s network contract (528). Field 430 contains the Green Token Generation Rate (&#34;GTGR&#34;), which is the number of green tokens generated per clock tick in units of 1/64K. At initial set up, chip microcode loads this field with a value determined by the connection&#39;s network contract (530). A value of `0000`h indicates that the green LKB function is disabled. 
     Word 416 is divided into 16-bit fields 432 and 434. Field 432 contains the Green Token Count (&#34;GTC&#34;), which is the number of green tokens currently in the pool. At initial set up, chip microcode loads this field with its maximum value (532). Field 434 contains the Green Fraction Token Count (&#34;GFTC&#34;), which is the number of fraction green tokens in the pool in units of 1/64K. At initial set up, this field is loaded with `0000`h (534). 
     BPL 234 performs both the synchronous and asynchronous packet updates. Every 16clock cycles (640 nsec), BPL 234 performs up to 4 LKB update operations in a pipelined fashion. The order of these update operations is as follows: (1) synchronous peak; (2) synchronous green; (3) asynchronous peak; and (4) asynchronous green. The synchronous LKB operations are performed on the connection specified in the MTC register in CBSL 216. Asynchronous LKB operations are performed on the connection specified in the first packet entry in Packet Entry FIFO 214. 
     BPL 234 receives and processes the packet from Packet Entry FIFO 214 and fetches the table entries from FM 224 and BM 226 for the target connection. The general procedure of an LKB update operation for a target network connection in BPL 234 comprises: (1) fetching LUT 418 and  --  TGR (&#34; --  &#34; can be &#34;P&#34; for Peak or &#34;G&#34; for Green) of the target connection from BM 226; (2) updating LUT 418 of the target connection with the Current Tick (&#34;CT&#34;) value; (3) calculating the Elapsed Time (&#34;ET&#34;), as ET=CT-LUT; (4) fetching  --  LKBS,  --  TC and  --  FTC of the target connection from BM 226; (5) calculating an Accumulated Token Count (&#34;ATC&#34;), as ATC=(TC &amp; FTC)+(ET* --  TGR), where the &#34;&amp;&#34; operator indicates concatenation and &#34;*&#34; indicates multiplication; and (6) calculating a current token count (&#34;CTC&#34;) using the rules: if ATC&gt;=LKBS, then CTC=LKBS, else CTC=ATC. 
     If the LKB update operation is an asynchronous update operation, the following additional steps are also performed: (7) calculating a final token count (&#34;FTC&#34;), as FTC=CTC-PBC; (8) if FTC is negative, updating either GVBC 348 or PVBC 352 (or both), depending on which LKB was violated. 
     Finally, both the synchronous and asynchronous LKB update operations update the  --  TC and  --  FTC fields of the target connection in BM 226 using CTC as calculated above in step 6. At this point, BPL 234 also updates the counters for state independent and state dependent variables in FM 224. If the packet information received from FIFO 214 indicates a state independent violation, then, depending on the violation type, BPL 234 increments MPSVC 346, SCVC 350 or the lower 24 bits of word 316. If there is a Green LKB violation, then BPL 234 increments GVBC 348 and sets GVS 334. If there is a peak LKB violation, BPL 234 increments PVBC 352 and sets PVS 336. Then, BPL 234 increments either GPC 338 and GBC 340 or RPC 342 and RBC 344, depending on whether the packet is green or red. 
     If both a synchronous and an asynchronous update need to take place for the same connection entry within a single clock tick, the update is performed as follows: (1) for green packets, an asynchronous update of the green LKB and an asynchronous update of the peak LKB is performed; (2) for red packets, a synchronous update of the green LKB (using a packet of size 0) and an asynchronous update of the peak LKB is performed. 
     To support the LKB update operations described above in a pipelined fashion, BPL 234 contains a sequential state machine and the following major computing units: (1) a 16-bit by 4-bit 2-input multiplier unit (&#34;MU&#34;); (2) a 16-bit 2-input adder unit (&#34;AU 0&#34;); and a 20-bit 2-input adder unit (&#34;AU 1&#34;). In addition, BPL 234 has several internal registers (&#34;Rn(x,y)&#34;) which are used to hold results from the computational units. The synchronous and asynchronous LKB update procedures performed by BPL 234 are described by the table in Table 1. 
     CBSL 220 supports control bus slave functions and allows FM 224, BM 226 and LBML internal control/status registers to be accessed by central processor 110 through the CB 220 interface. CBSL 220 contains several internal control/status registers and a set of error/statistical counters (not shown). The registers in CBSL 220 include the: 
     (1) Chip ID register. This is a 24-bit wide register. The first 16 bits are used to identify the chip while the last eight identify the chip version number. 
     (2) Chip Status register. This register has six defined bits. Bit 0 is the BIST completion bit. A &#34;1&#34; in bit 0 indicates the completion of the chip&#39;s built in self test (&#34;BIST&#34;). Bit 1 is the BIST status bit. A &#34;1&#34; in bit 1 indicates a successful BIST while a &#34;0&#34; indicates a failed BIST. Bit 2 is the Memory Test Completion bit. Bit 2 is set to &#34;1&#34; to indicate the completion of a memory test. Bit 3 is the Memory Test Status bit. Bit 3 is set to &#34;1&#34; to indicate a successful memory test and to &#34;0&#34; if the test fails. Bit 4 is the CB Address Parity Error bit. Bit 4 is set to &#34;1&#34; to indicate that a CB 220 address parity error has been detected since the chip was last reset. Bit 5 is the CB Data Parity Error bit. Bit 5 is set to &#34;1&#34; to indicate a CB 220 data parity error has been detected since the chip was last reset. 
     (3) Chip Control register. This register has seven defined bits. Bit 0 is the Chip Active bit. Setting bit 0 to &#34;1&#34; enables chip functions. Bit 1 is the Chip Soft-Reset bit. When bit 1 is changed from &#34;1&#34; to &#34;0,&#34; the whole chip, except for the Chip Control register will be reset. Bit 2 is the BIST Execution bit. When Bit 2 is changed from &#34;1&#34; to &#34;0,&#34; the chip BIST is executed. Bit 3 is the Memory Test Execution bit. When bit 3 is changed from &#34;1&#34; to &#34;0,&#34; a memory test is executed as defined by bit 4. Bit 4 is the Memory Test Version bit. When bit 4 is &#34;0,&#34; a full version of the memory test is executed. Otherwise, a quick memory test is executed. Bit 5 is the Reset CB Address Parity Error bit. A &#34;1&#34; in bit 5 resets the CB Address Parity Error bit in the Chip Status register. Bit 6 is the Reset CB Address Parity Error bit. A &#34;1&#34; in bit 6 will reset the CB Data Parity Error bit in the Chip Status register. 
     (4) CB Address Error register. This register has 32 bits and is used to log CB 220 data when a CB 220 data parity error is detected. Bits 0-31 hold the CB 220 address that caused the error. 
     (5) CB Data Error register. This register is 32 bits wide and is used to log CB 220 data when a CB 220 data parity error is detected. Bits 0-31 hold the CB 220 data that caused the error. 
     (6) Monitor Control register. This register has four defined bits. Bits 3 to 0 are the Peak LKB Resolution. This field defines the block size for peak LKB. The block size for the peak LKB is 2 N  *64 bytes, where N is the value in this field. 
     (7) Monitor Tick Counter (&#34;MTC&#34;). This 16-bit register holds the current clock tick of the LKB operation. This register is initialized to `0000`h and is incremented by 1 every 16 clock cycles. The MTC register holds the value copied into LUT 418 by BPL 34 and is used to specify the connection which is synchronously updated. 
     (8) Violation Counter Clear register. This register is 17 bits wide, write-only, and is used to clear SCVC 350 and MPSVC 346. When bit 16 is set to &#34;0&#34; SCVC 350 will be cleared. Otherwise, MPSVC 234 is cleared. Bits 15-0 identify the connection ID to be cleared. 
     (9) SIB Parity Error Counter. This 16-bit counter counts the number of SIB 18 parity errors detected. 
     (10) Foreground Memory Parity Error Counter. This 16-bit counter counts the number of FM 24 parity errors detected. 
     (11) Background Memory Parity Error Counter. This 16-bit counter counts the number of BM 26 parity errors detected. 
     (12) CB Parity Error Counter. This 16-bit counter counts the number of CB 220 parity errors detected. 
     Table 2 is a table which shows the control bus address map for the logical entries defined in the LBML chip. To address a CB entity in the LBML, such as FM 24, the high order address bits must comply with the following format: bits 31-29 hold the bank address; bits 28-25 hold the card slot address; and bits 24-23 hold the binary value &#34;01.&#34; 
     Although the present invention and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims. 
     
                                           TABLE 1                                 
__________________________________________________________________________
LKB Operational State Sequence                                            
C BMOP         AU 0          MU            AU 1                           
__________________________________________________________________________
  R1(31:0) - LUT &amp; PTGR;                                                  
 1                                                                        
  W0 = CT &amp; R1(15:0);                                                     
               R9(15:0) = CT - R1(31:16);                                 
 2                                                                        
  R5(31:0) = PLKBS &amp; PTC &amp;   R3(19:0) = R9(15:0) * R1(3:0);               
  PFTC;                                                                   
 3                           R3(19:0) = R9(15:0) * R1(7:4);               
                                           R4(20:0) = R3(19:0)            
                                           + R5(19:0);                    
 4                           R3(19:0) = R9(15:0) * R1(11:8);              
                                           R6(3:0) = R4(3:0); R10(4:0) =  
                                           (`000` B &amp; R4(20)) +           
                                           R5(23:20); R4(20:0) = R3(19:0) 
                                           + (R10(3:0) &amp;                  
                                           R4(19:4));                     
  R2(31:0) = GLKBS &amp; GTGR;   R3(19:0) = R9(15:0) *                        
                                           R6(7:4) = R4(3:0); R10(4:0) =  
                             R1(15:12)     (`00` B &amp; (R10(4) +            
                                           R4(20)) + (R5(23) &amp; R5(23) &amp;   
                                           R5(23) &amp;                       
                                           R5(23)); R4(20:0) = R3(19:0)   
                                           +                              
                                           (R10(3:0) &amp; R4(19:4));         
 6                                                                        
  R7(31:0) = GTC &amp; GFTC;     R3(19:0) = R9(15:0) * R2(3:0);               
                                           R6(11:8) = R4(3:0); R10(4:0)   
                                           =                              
                                           (`00` B &amp; (R10(4) +            
                                           R4(20)) + (R5(23) &amp; R5(23) &amp;   
                                           R5(23) &amp;                       
                                           R5(23)); R4(20:0) = R3(19:0)   
                                           +                              
                                           (R10(3:0) &amp; R4(19:4));         
 7             VF = (R5(23) == 0 &amp;&amp;                                       
                             R3(19:0) = R9(15:0) * R2(7:4);               
                                           R6(31:12) = R4(19:0); R4(20:0) 
                                           = R3(19:0) +                   
               ((R4(19:4) &gt;= (`00`h &amp;      R7(19:0);                      
               R5(31:24))) ∥ R4(20) == 1)) ∥            
               R5(23) == 1 &amp;&amp; (R4(19:4) &gt;=                                
               (`00`h &amp; R5(31:24))) &amp;&amp;                                    
               (R10(0) == 1 ∥ R4(20) == 1));                     
 8                                                                        
  W1 = R5(31:24) &amp;           R3(19:0) = R9(15:0) * R2(11:8);              
                                           R6(3:0) = R4(3:0); R10(4:0) =  
  R6(23:0), if                             (`000` B &amp; R4(20)) +           
  VF = 0; W1 = R5(31:24)                   R7(23:20); R4(20:0) = R3(19:0) 
                                           + (R10(3:0) &amp;                  
  &amp; R5(31:24) &amp; `0000`h,                   R4(19:4));                     
  if VF = 1;                                                              
 9                                                                        
  R1(31:0) = LUT &amp; PTGR;     R3(19:0) = R9(15:0) *                        
                                           R6(7:4) = R4(3:0); R10(4:0) =  
                             R2(15:12);    (`000` B &amp; (R10(4) +           
                                           R4(20))) + R7(27:24); R4(20:0) 
                                           = R3(19:0) +                   
                                           (R10(3:0) &amp; R4(19:4));         
10                                                                        
  R5(31:0) = PLKBS &amp; PTC &amp;   R3(19:0) = R9(15:0) * R1(3:0);               
                                           R6(11:8) = R4(3:0); R10(R:0)   
                                           =                              
                                           (`00` B &amp; (R10(4) +            
  PFTC;                                    R4(20))) + R7(31:28); R4(20:0) 
                                           = R3(19:0) +                   
                                           (R10(3:0) &amp; R4(19:4));         
11             VF = (R7(31) == 0 &amp;&amp;                                       
                             R3(19:0) = R9(15:0) * R1(7:4);               
                                           R6(31:12) = R4(19:0); R4(20:0) 
                                           = R3(19:0) +                   
               ((R4(19:4) &gt;= R2(31:16)) ∥                        
                                           R4(19:0);                      
               R4(20) == 1)) (R7(31) == 1                                 
               &amp;&amp; (R4(19:4) &gt;= R2(31:16))                                 
               &amp;&amp; (R10(0) == 1 ∥                                 
               R4(20) == 1));                                             
12                                                                        
  W3 = R6(31:0), if VF = 0;  R3(19:0) = R9(15:0) *                        
                                           R6(3:0) = R4(3:0); R10(4:0) =  
  W3 = R2(31:16) &amp; `0000`h, if                                            
                             R1(11:R);     (`000` B &amp; R4(20)) +           
  VF = 1;                                  R5(23:20); R4(20:0) = R3(19:0) 
                                           + (R10(3:0) &amp;                  
                                           R4(19:4));                     
13                                                                        
  R2(31:0) = GLKBS &amp; GTGR;   R3(19:0) = R9(15:0) *                        
                                           R6(7:4) = R4(3:0); R10(R:0) =  
                             R1(15:12);    (`00` B &amp; (R10(4) +            
                                           R4(20)) + (R5(23) &amp; R5(23) &amp;   
                                           R5(23));                       
                                           R4(20:0) =                     
                                           R3(19:0) + (410(3:0) &amp;         
                                           R4(19:4));                     
14                                                                        
  R7(31:0) = GTC &amp; GFTC;     R3(19:0) = R9(15:0) * R2(3:0);               
                                           R6(11:8) = R4(3:0); 410(4:0)   
                                           =                              
                                           (`00` B &amp; (R10(4) +            
                                           R4(20)) + (R5(23) &amp; R5(23) &amp;   
                                           R5(23) &amp; R5(23));              
                                           R4(20:0) - R3(19:0)            
                                           + (R10(3:0) &amp; R4(19:4));       
15             VF = (R5(23) == 0 &amp;&amp;                                       
                             R3(19:0) - R9)15:0) * R2(7:4);               
                                           R6(31:12) - R4(19:0); R4(20:0) 
                                           - R3(19:0) +                   
               (R4(19:4) &gt;= (`00`h &amp;       R7(19:0);                      
               R5(31:24))) ∥ R4(20) == |)) ∥   
               (R5(23) == | &amp;&amp; (R4(19:4) &gt;=                      
               (`00`h &amp; R5(31:24))) &amp;&amp;                                    
               (R10(0) = -| ∥ R4(20) ==|));    
 0             R8(15:0) = R6(15:0); R8(31:16)                             
                             R3(19:0) = R9(15:0) * R2(11:8);              
                                           R6(3:0) = R4(3:0); R10(0) =    
                                           carry of the sums              
               = (`00`h &amp; R6(23:16)) - PBC, if                            
                                           of R4(20) and R5(23:20);       
                                           R4(20:0) =                     
               VF = 0; R8(15:0) = `000`h;  R3(19:0) + (sum of R4(20) and  
               R8(31:16) = (`00`h &amp;        R5(23:20)) &amp; R4(19:4));        
               R5(31:24)) - PBC, if VF = 1;                               
 1                                                                        
  W1 - R5(31:24) &amp; R8(23:0); R3(19:0) - R9(15:0) *                        
                                           R6(7:4) = R4(3:0); R10(4:0) =  
                             R2(15:12);    (`00`B &amp; (R10(0) +             
                                           R4(20)) + R5(27:24); R4(20:0)  
                                           =                              
                                           R3(19:0) + (R10(3:0)           
                                           &amp; R4(19:4));                   
 2                                         R6(11:8) = R4(3:0); R10(4:0)   
                                           =                              
                                           (`00`B &amp; R10(0) =              
                                           R4(20)) = R5(27:24); R4(20:0)  
                                           =                              
                                           R3(19:0) + (410(3:0)           
                                           &amp; R4(19:4));                   
 3             VF = (R5(23) == 0 &amp;&amp;        R6(31:12) = R4(19:0);          
               (R4(19:4) &gt;= (`00`h &amp;                                      
               R5(31:24))) ∥ R4(20) == |)) ∥   
               (R5(23) == 1 &amp;&amp; (R4(19:4) &gt;=                               
               (`00`h &amp; R5(31:24))) &amp;&amp;                                    
               (R10(0) == | ∥ R4(20) == |));   
 4             R8(15:0) = R6(15:0);                                       
               R8(31:16) = (R6(31:16)) -                                  
               PBC, if VF = 0;                                            
               R8(15:0) = `0000`h;                                        
               R8(31:16) = (R2(31:16)) -                                  
               PBC, if VF = 1;                                            
 5                                                                        
  W3 = R8(31:0);                                                          
__________________________________________________________________________
 &amp;: Bit Concatenation                                                     
 ==: Logical &#34;Equal&#34; Operation                                            
   : Logical &#34;AND&#34; Operation                                              
 ∥: Logical &#34;OR&#34; Operation                                       
 
    
     
                                           TABLE 2                                 
__________________________________________________________________________
LBML Control Bus Address Map                                              
                                 Reset Value                              
CB Address                Size                                            
                             R/W 33222222                                 
                                      22221111                            
                                           11111100                       
                                                00000000                  
(A22-A00)   Entity        (bits)                                          
                             Access                                       
                                 10987654                                 
                                      32109876                            
                                           54321098                       
                                                76543210                  
__________________________________________________________________________
`00.sub.-- 0000`h                                                         
            Chip ID Register (CIR)                                        
                          24 rd  nnnnnnnn                                 
                                      00000000                            
                                           00000011                       
                                                00000001                  
`00.sub.-- 0001`h                                                         
            Chip Status Register (CSR)                                    
                           6 rd  nnnnnnnn                                 
                                      nnnnnnnn                            
                                           nnnnnnnn                       
                                                nn00dddd                  
`00.sub.-- 0002`h                                                         
            Chip Control Register (CCR)                                   
                           7 wr  nnnnnnnn                                 
                                      nnnnnnnn                            
                                           nnnnnnnn                       
                                                n0000000                  
`00.sub.-- 0003`h                                                         
            CB Address Error Register                                     
                          32 rd  00000000                                 
                                      00000000                            
                                           00000000                       
                                                00000000                  
            (AER)                                                         
`00.sub.-- 0004`h                                                         
            CB Data Error Register (DER)                                  
                          32 wr  00000000                                 
                                      00000000                            
                                           00000000                       
                                                00000000                  
`00.sub.-- 0005`h                                                         
            Monitor Control Register (MCR)                                
                           4 rd/wr                                        
                                 nnnnnnnn                                 
                                      nnnnnnnn                            
                                           nnnnnnnn                       
                                                nnnn0000                  
`00.sub.-- 0006`h                                                         
            Monitor Tick Counter (MTC)                                    
                          16 rd/wr                                        
                                 nnnnnnnn                                 
                                      nnnnnnnn                            
                                           00000000                       
                                                00000000                  
`00.sub.-- 0007`h                                                         
            Violation Counter Clear Register                              
                          17 wr  nnnnnnnn                                 
                                      nnnnnnn0                            
                                           00000000                       
                                                00000000                  
            (VCCR)                                                        
`00.sub.-- 8000`h                                                         
            SIB Parity Error Counter                                      
                          16 rd/wr                                        
                                 nnnnnnnn                                 
                                      nnnnnnnn                            
                                           00000000                       
                                                00000000                  
            (SIBPEC)                                                      
`00.sub.-- 8001`h                                                         
            Foreground Memory Parity                                      
                          16 rd/wr                                        
                                 nnnnnnnn                                 
                                      nnnnnnnn                            
                                           00000000                       
                                                00000000                  
            Error Counter (FMPEC)                                         
`00.sub.-- 8002`h                                                         
            Background Memory Parity                                      
                          16 rd/wr                                        
                                 nnnnnnnn                                 
                                      nnnnnnnn                            
                                           00000000                       
                                                00000000                  
            Error Counter (BMPEC)                                         
`00.sub.-- 8003`h                                                         
            CB Parity Error Counter                                       
                          16 rd/wr                                        
                                 nnnnnnnn                                 
                                      nnnnnnnn                            
                                           00000000                       
                                                00000000                  
            (RPDBC)                                                       
`01.sub.-- 0000`h-`04.sub.-- FFFF`h                                       
            Background Memory (BM)                                        
                          32 rd/wr                                        
                                 dddddddd                                 
                                      dddddddd                            
                                           dddddddd                       
                                                dddddddd                  
            Structure                                                     
`08.sub.-- 0000`h-0F.sub.-- FFFF`h                                        
            Foreground Memory (FM)                                        
                          24 rd/wr                                        
                                 nnnnnnnn                                 
                                      dddddddd                            
                                           dddddddd                       
                                                dddddddd                  
            Structure                                                     
__________________________________________________________________________
 Reset Value Key                                                          
 0: Zero after POR and software reset                                     
 1: One after POR and software reset                                      
 r: Reserved (reads zero)                                                 
 d: Device dependent                                                      
 X: Don&#39;t Care                                                            
 *: Zero after POR but not altered by software reset                      
 |: One after POR but not altered by software reset                       
 n: Not applicable                                                        
 R: Range