Patent Publication Number: US-11659706-B2

Title: Semiconductor device and method for fabricating the same

Description:
This application is a divisional of U.S. patent application Ser. No. 16/703,528 filed on Dec. 4, 2019, now U.S. Pat. No. 11,233,058 issued Jan. 25, 2022, which claims priority to U.S. Provisional 62/781,659, filed on Dec. 19, 2018, the disclosure of which is expressly incorporated by reference herein in its entirety. 
    
    
     FIELD 
     The present disclosure relates to semiconductor fabrication and more specifically to a capacitor having a hollow U-shaped base and the fabricating method thereof. 
     BACKGROUND 
     As the height of capacitors increases and the size of the memory array shrinks, the aspect ratio of the capacitors increases, weakening the steadiness of the capacitors. The collapse or twist of the capacitors may lead to poor yield rate. 
     SUMMARY 
     The following presents a summary of examples of the present disclosure in order to provide a basic understanding of at least some of its examples. This summary is not an extensive overview of the present disclosure. It is not intended to identify key or critical elements of the present disclosure or to delineate the scope of the present disclosure. The following summary merely presents some concepts of the present disclosure in a general form as a prelude to the more detailed description provided below. 
     In one example, a method for fabricating a semiconductor device is provided. The method includes the actions of: providing a substrate comprising a preliminary pattern formed thereon; forming an opening through the preliminary pattern to expose a conductive portion in the substrate; forming a spacer on a sidewall of the opening; performing a wet etching process to form a hole in the conductive portion; removing the spacer; and depositing a conductive pattern over the sidewall of the opening and a surface of the hole. 
     In another example, a semiconductor device is provided. The semiconductor device includes a substrate, an etch stop pattern, and a conductive pattern. The substrate includes a hole. The etch stop pattern is disposed over the substrate. The conductive pattern includes an upper potion extending upwardly from the substrate, and a lower portion covering a surface of the hole, wherein the upper portion is partially surrounded by the etch stop pattern. 
     In yet another example, a semiconductor device is provided. The semiconductor device includes a substrate, an etch stop pattern, and a conductive pattern. The substrate includes a conductive portion. The etch stop pattern is disposed over the substrate. The conductive pattern includes an upper potion extending upwardly from the substrate, and a lower portion electrically connected to the conductive portion of the substrate, wherein the upper portion is partially surrounded by the etch stop pattern. 
     The details of one or more examples are set forth in the accompanying drawings and description below. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The accompanying drawings illustrate one or more implementations of the present disclosure and, together with the written description, explain the principles of the present disclosure. Wherever possible, the same reference numbers are used throughout the drawings referring to the same or like elements of an embodiment. 
         FIGS.  1 A to  1 H  are cross-sectional views illustrating a method for fabricating a storage node in a semiconductor device in accordance with a first implementation of the present disclosure. 
         FIGS.  2 A to  2 H  are cross-sectional views illustrating a method for fabricating a storage node with a horizontal support layer in a semiconductor device in accordance with a second implementation of the present disclosure. 
         FIGS.  3 A and  3 B  are cross-sectional views illustrating a method for fabricating a storage node with a dual horizontal support layers in a semiconductor device in accordance with a third implementation of the present disclosure. 
         FIGS.  4 A to  4 F  are cross-sectional views illustrating a method for fabricating a storage node in a semiconductor device in accordance with a fourth implementation of the present disclosure. 
         FIGS.  5 A to  5 F  are cross-sectional views illustrating a method for fabricating a storage node with a horizontal support layer in a semiconductor device in accordance with a fifth implementation of the present disclosure. 
         FIGS.  6 A and  6 B  are cross-sectional views illustrating a method for fabricating a storage node with a dual horizontal support layers in a semiconductor device in accordance with a sixth implementation of the present disclosure. 
         FIGS.  7 A to  7 H  are cross-sectional views illustrating a method for fabricating a storage node in a semiconductor device in accordance with a seventh implementation of the present disclosure. 
         FIGS.  8 A and  8 B  are cross-sectional views illustrating a method for fabricating a storage node with a horizontal support layer in a semiconductor device in accordance with an eighth implementation of the present disclosure. 
         FIGS.  9 A and  9 B  are cross-sectional views illustrating a method for fabricating a storage node with a dual horizontal support layer in a semiconductor device in accordance with a ninth implementation of the present disclosure. 
         FIG.  10    is a cross-sectional view illustrating a circuit element in the semiconductor devices shown in  FIGS.  1 A to  9 B . 
     
    
    
     DETAILED DESCRIPTION 
     To facilitate an understanding of the principles and features of the various implementations of the present disclosure, various illustrative implementations are explained below. Although exemplary implementations of the present disclosure are explained in detail, it is to be understood that other implementations are contemplated. Accordingly, it is not intended that the present disclosure is limited in its scope to the details of construction and arrangement of components set forth in the following description or illustrated in the drawings. The present disclosure is capable of other implementations and of being practiced or carried out in various ways. 
       FIGS.  1 A to  1 H  are cross-sectional views illustrating a method for fabricating a storage node in a semiconductor device  100  in accordance with some implementations of the present disclosure. 
     As shown in  FIG.  1 A , the semiconductor device  100  includes a substrate  130  and a preliminary pattern  110  formed on the substrate  130 . The semiconductor device  100  may be a dynamic random access memory (DRAM) device. The substrate  130  includes a landing portion  155 , a dielectric plug  158  having a first dielectric element  156 , and a second dielectric element  157 . The landing portion  155  may be formed of a metal material, such as tungsten, titanium, or tantalum. The first dielectric element  156  may be formed of a dielectric material, such as silicon nitride (SiN), by a chemical vapor deposition (CVD) process. The second dielectric element  157  may also be formed of a dielectric material, such as SiN, by an atomic layer deposition (ALD) process. In some embodiments, the substrate  130  may be a silicon wafer. A circuit element  1090  including a gate structure, an impurity region, and/or a contact plug may be provided in the substrate  130 . 
     The preliminary pattern  110  includes an etch stop layer  111 , a sacrificial layer  112  formed on the etch stop layer  111 , and mask patterns  113  formed over the sacrificial layer  112 . For example, the preliminary pattern  110  may be formed by sequentially stacking the etch stop layer  111 , the sacrificial layer  112 , and the mask patterns  113  using a deposition technique, such as ALD process, a plasma assisted atomic layer deposition (PAALD), a CVD process, a plasma enhanced chemical vapor deposition (PECVD) process, a low pressure chemical vapor deposition (LPCVD) process, a high density plasma chemical vapor deposition (HDP-CVD) process, a spin coating process, a sputtering process, or the like. In one implementation, the preliminary pattern  110  has a thickness falling in the range of 1 to 1.3 microns (μm). 
     In some embodiments, the etch stop layer  111  may include a material selected from SiN, silicon boron nitride (SiBN), silicon carbon nitride (SiCN), silicon carbide (SiC), silicon oxynitride (SiON), silicon oxycarbide (SiOC), or the like. The sacrificial layer  112  may be formed of a silicon oxide-based material, such as silicon oxide (SiOx), plasma enhanced oxide (PEOX), boro silicate glass (BSG), phospho silicate glass (PSG), boro phospho silicate glass (BPSG), tetraethyl orthosilicate (TEOS), boro tetraethyl orthosilicate (BTEOS), phosphorous tetraethyl orthosilicate (PTEOS), or boro phospho tetraethyl orthosilicate (BPTEOS). The mask patterns  113  may be made of a combination of SiN and polysilicon. Alternatively, the mask patterns  113  may be made of a metal material. 
     As shown in  FIG.  1 B , an etching process is performed on the mask patterns  113  to form one or more first openings  160   a  in the sacrificial layer  112  to expose the etch stop layer  111 . For example, a dry etching process such as a plasma etching process, an inductively coupled plasma (ICP) process, a transformer coupled plasma (TCP) process or a reactive ion etching (RIE) process may be used. The resulting first opening(s)  160   a  may be a tapered trench. The upper width of the first opening(s)  160   a  is wider than the lower width thereof. Accordingly, a plurality of tapered pillars  112   a  are formed on the etch stop layer  111 . Each of the tapered pillars  112   a  protrudes upward and is in alignment with a corresponding dielectric plug  158 . 
     As shown in  FIG.  1 C , an etching process is performed to form one or more second openings  160   b  in the etch stop layer  111  to expose the substrate  130 . For example, a dry etching process such as a plasma etching process, an ICP process, a TCP process or a RIE process may be used. The resulting second openings  160   b  may each include a recess. A portion of the landing portion  155  may be exposed by at least one of the second openings  160   b . A top surface  155   a  of the portion of the landing portion  155  is defined by the bottom of at least one of the second openings  160   b . Accordingly, a plurality of etch stop patterns  111   a  are formed below the tapered pillars  112   a . In some embodiments, an opening  160  including the first opening  160   a  and the second opening  160   b  may be formed by a single etching process. 
     Referring to  FIGS.  1 D and  1 E , a dielectric layer  170  is formed on a sidewall  165  of the opening  160  by a deposition process such as a CVD process or ALD process. The dielectric layer  170  may be a spacer covering the etch stop patterns  111   a , the tapered pillars  112   a , and a portion of the top surface  155   a  of the landing portion  155  to serve as a hard mask for the subsequent etching process. The width W 1  of the non-covered area on the top surface  155   a  falls in the range of 30 to 40 nanometers (nm). In one implementation, the dielectric layer  170  has a uniform thickness of 70 angstroms (Å). 
     As shown in  FIG.  1 E , an etching process is performed to form a hole  180  in each of the landing portions  155 . For example, a dry etching process may be performed. The hole  180  penetrates the landing portion  155  by a predetermined depth. For example, the depth of the hole  180  is 0.2 microns and the width of the hole  180  falls in the range of 30 to 40 nanometers. 
     As shown in  FIG.  1 F , subsequent to the formation of the hole  180 , the dielectric layer  170  may be removed by an etching process such as a plasma etching process, an ICP process, a TCP process or a RIE process. 
     As shown in  FIG.  1 G , a conductive pattern  190  is formed over the substrate  130  by a deposition process such as a CVD process or ALD process. The conductive pattern  190  may be a lower electrode or a storage node of a capacitor of a DRAM device. The conductive pattern  190  may be formed of a metal material such as titanium nitride, titanium, tungsten, or the like. The conductive pattern  190  includes an upper portion  190   a  and a lower portion  190   b . The lower portion  190   b  fills the hole  180 . The upper portion  190   a  covers the sidewall  165  of the opening  160  and the top surface  155   a  of the landing portion  155 . In one implementation, the upper portion  190   a  is partially surrounded by the etch stop patterns  111   a . In some embodiments, the conductive pattern  190  may be formed by a single deposition process or a plurality of deposition processes. 
     As shown in  FIG.  1 H , the mask patterns  113  and the tapered pillars  112   a  are removed. For example, the mask patterns  113  are removed by a dry etching process, and the tapered pillars  112   a  are removed by a wet etching process. In some embodiments, the conductive pattern  190  is electrically connected to the landing portion  155 . The upper portion  190   a  extends upwardly from the substrate  130  and has a vertical length falling in the range of 1 to 1.3 microns. The lower portion  190   b  is buried in the landing portion  155  and has a vertical length (or depth) of 0.2 microns. Accordingly, a ratio of the vertical length of the upper portion  190   a  to the vertical length of the lower portion  190   b  falls in a range of 4 to 7. In one implementation, the upper portion  190   a  has a truncated hollow circular cone structure. 
     According to the exemplary implementations described with reference to  FIGS.  1 A to  1 H , the capacitor has an improved structural stability. The lower portion  190   b  of the conductive pattern  190  has a Y-shaped structure serving as a fixture base to enhance the structural stability of the conductive pattern  190 , therefore preventing the capacitor from deformation. Furthermore, the lower portion  190   b  increases the contact area between the conductive pattern  190  and the landing portion  155 , therefore increasing the capacitance of the capacitor. 
       FIGS.  2 A to  2 H  are cross-sectional views illustrating a method for fabricating a storage node having a horizontal support layer in a semiconductor device  200  in accordance with some implementations of the present disclosure. In  FIGS.  2 A to  2 H , detailed descriptions regarding processes and/or materials that are substantially the same as or similar to those described above with reference to  FIGS.  1 A to  1 H  are omitted herein, and like reference numerals are used to designate like elements. 
     As shown in  FIG.  2 A , the semiconductor device  200  includes a substrate  130 , a preliminary pattern  110  formed on the substrate  130 . The semiconductor device  200  may be a DRAM device. The substrate  130  includes a landing portion  155 , a dielectric plug  158  having a first dielectric element  156 , and a second dielectric element  157 . The landing portion  155  may be formed of a metal material. The first dielectric element  156  may be formed of a dielectric material. The second dielectric element  157  may also be formed of a dielectric material. In some embodiments, the substrate  130  may be a silicon wafer. 
     The preliminary pattern  110  includes an etch stop layer  111 , a first sacrificial layer  115  formed on the etch stop layer  111 , a support layer  114  formed on the first sacrificial layer  115 , a second sacrificial layer  115  formed on the support layer  114 , and mask patterns  113  formed over the second sacrificial layer  116 . For example, the preliminary pattern  110  may be formed by sequentially stacking the etch stop layer  111 , the first sacrificial layer  115 , the support layer  114 , the second sacrificial layer  116 , and the mask patterns  113  using a deposition technique. The first sacrificial layer  115 , the support layer  114 , the second sacrificial layer  116  may be a laminate structure. In one implementation, the preliminary pattern  110  has a thickness falling in the range of 1 to 1.3 microns. 
     In some embodiments, the etch stop layer  111  may be made of SiN or SiBN. The first and second sacrificial layers  115 ,  116  may be formed of a silicon oxide-based material. The support layer  114  may be formed of SiN or SiCN. The mask patterns  113  may be made of a combination of SiN and polysilicon. The mask patterns  113  may also be made of a metal material. 
     As shown in  FIG.  2 B , an etching process is performed on the mask patterns  113  to form one or more first openings  160   a  in the sacrificial layer  112  and expose the etch stop layer  111 . For example, a dry etching process may be used. The resulting first opening(s)  160   a  may be a tapered trench. The upper width of the first opening(s)  160   a  is wider than the lower width thereof. Accordingly, a plurality of tapered pillars  117  are formed on the etch stop layer  111 . The tapered pillars  117  includes a portion  115   a  of the first sacrificial layer  115 , a portion  114   a  of the support layer  114 , a portion  116   a  of the second sacrificial layer  116 . Each of the tapered pillars  117  protrudes upward and is in alignment with a corresponding dielectric plug  158 . 
     Referring to  FIGS.  2 C to  2 F , processes substantially the same as or similar to those illustrated with reference to  FIGS.  1 C to  1 F  may be used to form the hole  180  as shown in  FIG.  2 F . The method for forming the hole  180  includes the action of: performing a dry etching process to form the second openings  160   b  (e.g., a recess) penetrating the etch stop layer  111  and partially expose the landing portion  155  of the substrate  130 . The bottom of the second openings  160   b  defines an exposed top surface  155   a  of the landing portion  155 . The method further includes the action of: forming the dielectric layer  170  on the sidewall  165  of the opening  160 . The dielectric layer  170  conformally covers the tapered pillars  117 , the etch stop patterns  111   a , and a portion of the top surface  155   a  of the landing portion  155 . That is to say, the dielectric layer  170  extends from the landing portion  155  to the top of the tapered pillars  117 . In some examples, the action of forming the dielectric layer  170  includes performing a deposition process to form a deposited layer, and an etch-back process to remove a portion of the deposited layer. The method further includes the action of: performing an etching process to form the hole  180  in the landing portion  155 . The mask patterns  113  and the dielectric layer  170  serve as a mask while forming the hole  180 . In one implementation, the hole  180  is in the middle between two adjacent dielectric plugs  158 , and isolated from the two dielectric plugs  158  and the circuit element  1090 . The method further includes the action of: performing an etching process to remove the dielectric layer  170 . 
     As shown in  FIG.  2 G , a conductive pattern  190  is formed over the substrate  130  by a deposition process. The conductive pattern  190  may be formed of a metal material to serve as an electrode or a storage node of a capacitor of the DRAM device. The upper portion  190   a  of the conductive pattern  190  conformally covers the tapered pillars  117 , the etch stop patterns  111   a , and a portion of the top surface  155   a  of the landing portion  155 . That is to say, the upper portion  190   a  extends from the landing portion  155  to the top of the tapered pillars  117 . The lower portion  190   b  of the conductive pattern  190  fills the hole  180 . 
     As shown in  FIG.  2 H , the mask patterns  113 , the portion  116   a  of the first sacrificial layer  115 , and the portion  115   a  of the second sacrificial layer  116  are removed. For removing the portion  116   a , the mask patterns  113  is removed by a dry etching process to expose surface of the portion  116   a  under the mask patterns  113 . Subsequently, a wet etching process is used to remove the portion  116   a . For removing the portion  115   a , some the portions  114   a  is removed by a dry etching process to expose surface of the portion  115   a  under the removed portions  114   a  (not shown). Subsequently, a wet etching process is used to remove the portion  115   a.    
     In some embodiments, the conductive pattern  190  has a Y-shaped structure. Since both the upper portion  190   a  and the lower portion  190   b  contact with the landing portion  155 , the conductive pattern  190  is electrically connected to the landing portion  155 . In one implementation, the upper portion  190   a  is partially surrounded by the etch stop patterns  111   a  at the bottom of the upper portion  190   a  and partially surrounded by the portion  114   a  of the support layer  114  at the middle of the upper portion  190   a . For example, the support layer  114  is connected to an outer sidewall of the upper portion  190   a  as shown in  FIG.  2 H . 
       FIGS.  3 A to  3 B  are cross-sectional views illustrating a method for fabricating a storage node having a dual horizontal support layers in a semiconductor device  300  in accordance with some implementations of the present disclosure. In  FIGS.  3 A to  3 B , detailed descriptions regarding materials that are substantially the same as or similar to those described above with reference to  FIGS.  2 A to  2 H  are omitted herein, and like reference numerals are used to designate like elements. 
     Referring to  FIGS.  3 A to  3 B , processes substantially the same as or similar to those with reference to  FIGS.  2 A to  2 H  may be used to form the conductive pattern  190  as shown in  FIG.  3 B . The method to form the conductive pattern  190  includes the actions of: providing a substrate  130  including a preliminary pattern formed thereon; forming one or more openings  160  through the preliminary pattern to expose the substrate  130 ; forming a spacer (dielectric layer)  170  on a sidewall  165  of the opening(s)  160 ; performing a dry etching process to form a hole  180  in the substrate; removing the spacer  170 ; and depositing a conductive pattern  190  over the sidewall  165  and in the hole  180 . The preliminary pattern includes an etch stop layer contacting the substrate  130 , a laminate structure formed on the etch stop layer  111 , and a plurality of mask patterns  113  formed over the laminate structure. The laminate structure includes two sacrificial layers  315   a ,  316   a  and two support layers  314   a ,  324   a . The method further includes removing the sacrificial layers  315   a ,  316   a  by processes previously described in  FIG.  2 H . 
     According to the exemplary implementations described with reference to  FIGS.  2 A to  2 H and  3 A to  3 B , the capacitor has an improved structural stability. The lower portion  190   b  of the conductive pattern  190  has a Y-shaped structure serving as a fixture base. The support portions/layers  114   a ,  314   a ,  324   a  provide horizontal support between the conductive patterns  190 . The enhancement of the structural stability of the conductive pattern  190  prevents the capacitor from deformation. Furthermore, the lower portion  190   b  increases the contact area between the conductive pattern  190  and the landing portion  155 , therefore increasing the capacitance of the capacitor. 
       FIGS.  4 A to  4 F  are cross-sectional views illustrating a method for fabricating a storage node in a semiconductor device  400  in accordance with some implementations of the present disclosure. As shown in  FIG.  4 A , the semiconductor device  400  includes a substrate  430 , a preliminary pattern  410  formed on the substrate  430 . The semiconductor device  400  may be a dynamic random access memory (DRAM) device. The substrate  430  includes a landing portion  455  and a dielectric plug  458  having a first dielectric element  456 , and a second dielectric element  457 . The landing portion  455  may be formed of a metal material, such as tungsten, titanium, or tantalum. The first dielectric element  456  may be formed of a dielectric material such as SiN by a CVD process. The second dielectric element  457  may be formed of a dielectric material such as SiN by an ALD process. In some embodiments, the substrate  430  may be a silicon wafer. A circuit element  4090  including a gate structure, an impurity region, and/or a contact plug may be provided in the substrate  430 . 
     Referring to  FIGS.  4 A to  4 B , processes substantially the same as or similar to those illustrated with reference to  FIGS.  1 A to  1 D  may be performed to form the dielectric layer  470  as shown in  FIG.  4 B . 
     As shown in  FIG.  4 C , an etching process is performed to form a hole  480  in the landing portion  455 . For example, a wet etching process may be performed. The hole  480  penetrates the landing portion  455  by a predetermined depth. For example, the depth of the hole  480  may be 0.2 microns and the length of the widest portion of the hole  480  may fall in the range of 50 to 60 nanometers. 
     As shown in  FIG.  4 D , subsequent to the formation of the hole  480 , the dielectric layer  470  may be removed by an etching process such as a plasma etching process, an ICP process, a TCP process or a RIE process. 
     As shown in  FIG.  4 E , a conductive pattern  490  is formed over the substrate  430  by a deposition process, such as a CVD process or ALD process. The conductive pattern  490  may be a lower electrode or a storage node of a capacitor of the DRAM device. The conductive pattern  490  may be formed of a metal material, such as titanium nitride, titanium, tungsten, or the like. The conductive pattern  490  includes an upper portion  490   a  and a lower portion  490   b . The lower portion  490   b  covers a surface of the hole  480 . The upper portion  490   a  covers the sidewall  465  of the opening  460  and the top surface  455   a  of the landing portion  455 . In one implementation, the upper portion  490   a  is partially surrounded by the etch stop patterns  411   a . In some embodiments, the conductive pattern  490  may be formed by a single deposition process or a plurality of deposition processes. 
     As shown in  FIG.  4 F , the mask patterns  413  and the tapered pillars  412   a  are removed. For example, the mask patterns  413  are removed by a dry etching process, and the tapered pillars  412   a  are removed by a wet etching process. In some embodiments, the conductive pattern  490  is electrically connected to the landing portion  455 . The upper portion  490   a  extends upwardly from the substrate  430  and may have a vertical length falling in the range of 1 to 1.3 microns. The lower portion  490   b  may have a vertical length of 0.2 microns. Accordingly, a ratio of the vertical length of the upper portion  490   a  to the vertical length of the lower portion  190   b  may fall in a range of 4 to 7. In one implementation, the upper portion  490   a  has a truncated hollow circular cone structure (not shown). 
     According to the exemplary implementations described with reference to  FIGS.  4 A to  4 F , the capacitor has an improved structural stability. The lower portion  490   b  of the conductive pattern  490  has a hollow U-shaped structure serving as a fixture base to enhance the structural stability of the conductive pattern  490 , therefore preventing the capacitor from deformation. Furthermore, the lower portion  490   b  increases the contact area between the conductive pattern  490  and the landing portion  455 , therefore increasing the capacitance of the capacitor. 
       FIGS.  5 A- 5 F  are cross-sectional views illustrating a method for fabricating a storage node with a horizontal support layer in the semiconductor device  500  in accordance with some implementations of the present disclosure. In  FIGS.  5 A to  5 H , detailed descriptions regarding processes and/or materials that are substantially the same as or similar to those described above with reference to  FIGS.  4 A to  4 F  are omitted herein, and like reference numerals are used to designate like elements. 
     Referring to  FIGS.  5 A to  5 B , processes substantially the same as or similar to those illustrated with reference to  FIGS.  2 A to  2 D  may be performed to form the dielectric layer  470  as shown in  FIG.  5 B . 
     Referring to  FIGS.  5 C to  5 D , processes substantially the same as or similar to those illustrated with reference to  FIGS.  4 C to  4 D  may be used to form the hole  480  as shown in  FIG.  5 D . The method for forming the hole  480  may include the action of: performing an etching process to form the hole  480  in the landing portion  455 . The mask patterns  413  and the dielectric layer  470  may serve as a mask while forming the hole  480 . In one implementation, the hole  480  is in the middle between two adjacent dielectric plugs  458 , and isolated from the two dielectric plugs  458  and the circuit element  4090 . The method may further include the action of: performing an etching process to remove the dielectric layer  470 . 
     As shown in  FIG.  5 E , a conductive pattern  490  is formed over the substrate  430  by a deposition process. The conductive pattern  490  may be formed of a metal material to serve as an electrode or a storage node of a capacitor of the DRAM device. The upper portion  490   a  of the conductive pattern  490  may conformally cover the tapered pillars  417 , the etch stop patterns  411   a , and a portion of the top surface  455   a  of the landing portion  455 . That is to say, the upper portion  190   a  extends from the landing portion  455  to the top of the tapered pillars  417 . The lower portion  190   b  of the conductive pattern  490  may cover a surface of the hole  480 . 
     Referring to  FIG.  5 F , processes substantially the same as or similar to those illustrated with reference to  FIG.  2 H  may be used to remove the mask patterns  413 , the portion  416   a  of the first sacrificial layer  415 , and the portion  415   a  of the second sacrificial layer  416 , as shown in  FIG.  5 F . 
     In some embodiments, the conductive pattern  190  has a U-shaped structure. Since the lower portion  490   b  contact with the landing portion  455 , the conductive pattern  490  is electrically connected to the landing portion  455 . In one implementation, the upper portion  490   a  is partially surrounded by the etch stop patterns  411   a  at the bottom of the upper portion  490   a  and partially surrounded by the portion  414   a  of the support layer  414  at the middle of the upper portion  490   a . For example, the portion  414   a  is connected to an outer sidewall of the upper portion  490   a  as shown in  FIG.  5 F . 
       FIGS.  6 A to  6 B  are cross-sectional views illustrating a method for fabricating a storage node with a dual horizontal support layers in the semiconductor device  500  in accordance with some implementations of the present disclosure. In  FIGS.  6 A to  6 B , detailed descriptions regarding processes and/or materials that are substantially the same as or similar to those described above with reference to  FIGS.  5 A to  5 F  are omitted herein, and like reference numerals are used to designate like elements. 
     Referring to  FIGS.  6 A to  6 B , processes substantially the same as or similar to those described in  FIGS.  5 A to  5 F  may be used to form the conductive pattern  490  as shown in  FIG.  6 B . The method for forming the conductive pattern  490  may include the actions of: providing a substrate  430  including a pattern formed thereon; forming one or more openings  460  through the pattern to expose the substrate  430 ; forming a spacer (dielectric layer)  470  on a sidewall  465  of the opening  460 ; performing a dry etching process to form a hole  480  in the substrate; removing the spacer  470 ; and depositing a conductive pattern  490  over the sidewall  465  and in the hole  480 . The pattern may include an etch stop layer contacting the substrate  430 , a laminate structure formed on the etch stop layer  411 , and a plurality of mask patterns  413  formed over the laminate structure. The laminate structure may include two sacrificial layers  515   a ,  516   a  and two support layers  514   a ,  524   a . The method may further include removing the sacrificial layers  515   a ,  516   a  by processes previously described in  FIG.  5 F . 
     According to the exemplary implementations described with reference to FIGS.  4 A to  4 F and  6 A to  6 B, the capacitor has an improved structural stability. The lower portion  490   b  of the conductive pattern  190  has a hollow U-shaped structure serving as a fixture base. The support layer  414   a ,  514   a ,  524   a  provides horizontal support between the conductive patterns  490 . The enhancement of the structural stability of the conductive pattern  490  prevents the capacitor from deformation. Furthermore, the lower portion  490   b  increases the contact area between the conductive pattern  490  and the landing portion  455 , therefore increasing the capacitance of the capacitor. 
       FIGS.  7 A- 7 H  are cross-sectional views illustrating a method for fabricating a storage node in a semiconductor device  700  in accordance with some implementations of the present disclosure. As shown in  FIG.  7 A , the semiconductor device  700  includes a substrate  730 , a preliminary pattern  710  formed on the substrate  730 . The semiconductor device  700  may be a dynamic random access memory (DRAM) device. The substrate  730  includes a landing portion  755 , a dielectric plug  758  having a first dielectric element  756 , and a second dielectric element  757 . The landing portion  755  may be formed of a metal material, such as tungsten, titanium, or tantalum. The first dielectric element  756  maybe formed of a dielectric material such as SiN by a CVD process. The second dielectric element  757  maybe formed of a dielectric material such as SiN by an ALD process. In some embodiments, the substrate  730  may be a silicon wafer. A circuit element  7090  including a gate structure, an impurity region, and/or a contact plug may be provided in the substrate  730 . Further detailed descriptions regarding materials in  FIG.  7 A  that are substantially the same as or similar to those described above with reference to  FIG.  1 A  are omitted herein, and like reference numerals are used to designate like elements. 
     Referring to  FIG.  7 B , processes substantially the same as or similar to those illustrated with reference to  FIG.  1 B  may be used to form one or more openings  160   a  as shown in  FIG.  7 B . 
     As shown in  FIG.  7 C , a dielectric layer  770  is formed on a sidewall  765  of the openings  760  by a deposition process such as a CVD process or ALD process. The dielectric layer  770  may be a spacer covering the tapered pillars  712   a , and a portion of the etch stop patterns  711   a  to serve as a hard mask for the subsequent etching process. The width W 7  of the non-covered area of the etch stop patterns  711   a  may fall in the range of 30 to 40 nanometers. In one implementation, the dielectric layer  770  has a uniform thickness of 70 angstroms. 
     As shown in  FIG.  7 D , an etching process is performed to form a hole  780  in the landing portion  755 . For example, a dry etching process may be performed. The hole  780  penetrates the etch stop patterns  711   a  and the landing portion  755  by a predetermined depth. The depth of the hole  780  may be 0.2 microns, and the width of the hole  180  may fall in the range of 30 to 40 nanometers. In some embodiments, the hole  780  may be formed by a single etching process or a plurality of etching processes. 
     As shown in  FIG.  7 E , an etching process is performed to expand the hole  780  in the landing portion  755 . For example, a wet etching process may be performed. The width w 7   e  of the widest portion of the expanded hole  780  may fall in the range of 50 to 60 nanometers. 
     As shown in  FIG.  7 F , subsequent to the formation of the expanded hole  780 , the dielectric layer  770  may be removed by an etching process such as a plasma etching process, an ICP process, a TCP process or a RIE process. 
     As shown in  FIG.  7 G  a conductive pattern  790  is formed over the substrate  730  by a deposition process, such as a CVD process or ALD process. The conductive pattern  790  may be a lower electrode or a storage node of a capacitor of the DRAM device. The conductive pattern  790  may be formed of a metal material, such as titanium nitride, titanium, tungsten, or the like. The conductive pattern  790  includes an upper portion  790   a , a middle portion  790   c  and a lower portion  790   b . The lower portion  190   b  may fill the hole  780 . The middle portion  790   c  may be surrounded by the etch stop patterns  711   a . The upper portion  790   a  may cover the sidewall  765  of the opening  760  and a top surface  711   s  of the etch stop patterns  711   a . In some embodiments, the conductive pattern  790  may be formed by a single deposition process or a plurality of deposition processes. 
     As shown in  FIG.  7 H , the mask patterns  713  and the tapered pillars  712   a  are removed. For example, the mask patterns  713  may be removed by a dry etching process, and the tapered pillars  712   a  may be removed by a wet etching process. In some embodiments, the conductive pattern  790  is electrically connected to the landing portion  755 . The upper portion  790   a  of the conductive pattern  790  extends upwardly from the substrate  130  and has a vertical length falling in the range of 1 to 1.3 microns. The middle portion  790   c  may fill the gaps within the etch stop patterns  711   a . The lower portion  790   b  is buried in the landing portion  755  and may have a vertical length of 0.2 microns. Accordingly, a ratio of the vertical length of the upper portion  790   a  to the vertical length of the lower portion  790   b  may fall in a range of 4 to 7. In one implementation, the upper portion  790   a  has a truncated hollow circular cone structure (not shown). 
     According to the exemplary implementations described with reference to  FIGS.  7 A to  7 H , the capacitor has an improved structural stability. The lower portion  790   b  of the conductive pattern  790  has a filled U-shaped structure, and the middle portion  790   c  of the conductive pattern  790  has a neck structure, serving as a fixture base to enhance the structural stability of the conductive pattern  190 , therefore preventing the capacitor from deformation. Furthermore, the lower portion  790   b  increases the contact area between the conductive pattern  790  and the landing portion  755 , therefore increasing the capacitance of the capacitor. 
       FIGS.  8 A to  8 B  are cross-sectional views illustrating a method for fabricating a storage node with a horizontal support layer in a semiconductor device  800  in accordance with some implementations of the present disclosure. In  FIGS.  8 A to  8 B , detailed descriptions regarding processes and/or materials that are substantially the same as or similar to those described above with reference to  FIGS.  7 A to  7 H  are omitted herein, and like reference numerals are used to designate like elements. 
     Referring to  FIGS.  8 A to  8 B , processes substantially the same as or similar to those illustrated with reference to  FIGS.  7 A to  7 H  may be used to form the conductive pattern  790  as shown in  FIG.  8 B . The method for forming the conductive pattern  790  may include the action of: providing a substrate  730  including a preliminary pattern formed thereon; forming one or more openings  760  through the preliminary pattern to expose the etch stop layer  711 ; forming a spacer (dielectric layer)  770  on a sidewall  765  of the opening  760 ; performing a dry etching process to form a hole  780  in the substrate  730 ; performing a wet etching process to expand the hole  780  in the substrate  730 ; removing the spacer  770 ; and depositing a conductive pattern  790  over the sidewall  765  and in the hole  780 . The preliminary pattern may include an etch stop layer contacting the substrate  730 , a laminate structure formed on the etch stop layer  711 , and a plurality of mask patterns  713  formed over the laminate structure. The laminate structure includes two sacrificial layers  715   a ,  716   a  and a support layer  714   a . The method may further include removing the sacrificial layers  715   a ,  716   a  by processes previously described in  FIGS.  2 H and  5 F . 
       FIGS.  9 A to  9 B  are cross-sectional views illustrating a method for fabricating a storage node with a horizontal support layer in a semiconductor device  900  in accordance with some implementations of the present disclosure. In  FIGS.  9 A to  9 B , detailed descriptions regarding processes and/or materials that are substantially the same as or similar to those described above with reference to  FIGS.  7 A to  7 H  are omitted herein, and like reference numerals are used to designate like elements. Referring to  FIGS.  9 A to  9 B , processes substantially the same as or similar to those illustrated with reference to  FIGS.  8 A to  8 B  may be used to form conductive pattern  790  as shown in  FIG.  9 B . 
     According to the exemplary implementations described with reference to  FIGS.  8 A to  8 B and  9 A to  9 B , the capacitor has an improved structural stability. The lower portion  790   b  of the conductive pattern  790  has a filled U-shaped structure, and the middle portion  790   c  of the conductive pattern  790  has a neck structure, serving as a fixture base. The support layers  714   a ,  914   a ,  924   a  provide horizontal support between the conductive patterns  790 . The enhancement of the structural stability of the conductive pattern  790  prevents the capacitor from deformation. Furthermore, the lower portion  790   b  increases the contact area between the conductive pattern  790  and the landing portion  755 , therefore increasing the capacitance of the capacitor. 
       FIG.  10    is a cross-sectional view illustrating a circuit element  1090  in the semiconductor device  100  to  900 . The circuit element  1090  may include first dielectric layers  1091   a ,  1091   b , outer spacers  1092   a ,  1092   b , second dielectric layers  1093   a ,  1093   b , inner spacers  1094   a ,  1094   b , a mask  1095 , and a gate line  1094 . In some embodiments, the first dielectric layers  1091   a ,  1091   b , the outer spacers  1092   a ,  1092   b , the inner spacers  1094   a ,  1094   b , and the mask  1095  may be made of material selected from SiN, SiBN, SiCN, SiC, SiON, and SiOC. The second dielectric layer  1093  may be made of silicon oxide-based material, such as SiOx, PEOX, BSG, PSG, BPSG, TEOS, BTEOS, PTEOS, and BPTEOS. The space filled by the second dielectric layers  1093   a ,  1093   b  may be air-gaps when the second dielectric layers  1093   a ,  109   b  are removed. The gate line  1096  may be made of a metal material, such as tungsten, titanium, or tantalum. 
     The terminology used herein is for the purpose of describing particular implementations only and is not intended to be limiting of implementations of the present disclosure. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. 
     The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present disclosure has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to implementations of the present disclosure in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of implementations of the present disclosure. The implementation was chosen and described in order to best explain the principles of implementations of the present disclosure and the practical application, and to enable others of ordinary skill in the art to understand implementations of the present disclosure for various implementations with various modifications as are suited to the particular use contemplated. 
     Although specific implementations have been illustrated and described herein, those of ordinary skill in the art appreciate that any arrangement which is calculated to achieve the same purpose may be substituted for the specific implementations shown and that implementations of the present disclosure have other applications in other environments. This present disclosure is intended to cover any adaptations or variations of the present disclosure. The following claims are in no way intended to limit the scope of implementations of the present disclosure to the specific implementations described herein. 
     Various examples have been described. These and other examples are within the scope of the following claims.