Patent Publication Number: US-2007103396-A1

Title: Method for driving discharge display panel to lower rated voltage of driving apparatus and driving apparatus having lower rated voltage

Description:
BACKGROUND OF THE INVENTION  
      1. Field of the Invention  
      The invention relates to a method of driving a discharge display panel and a driving apparatus having a lower rated voltage. More particularly, the invention relates to a method of driving a discharge display panel that includes, e.g., X electrode lines, Y electrode lines, and address electrode lines, and a driving apparatus capable of performing such a method.  
      2. Description of the Related Art  
      A conventional discharge display apparatus, e.g., a plasma display apparatus, may display gray levels of an image(s) by dividing a unit frame period into a plurality of subfields. Each of the subfields may include a reset period, an addressing period, and a sustain period. Each of the subfields may have a unique gradation weight, and the sustain period for each subfield may be set in proportion to the respective gradation weight.  
      In such a conventional discharge display apparatus, a potential(s) of the Y electrode lines, which are often called scan electrode lines, may rise to a highest potential during the reset period. Thereafter, the potential of the Y electrode lines may fall to a lower potential before falling to a lowest potential. In this case, the highest potential may not affect a rated voltage of a driving apparatus because two potentials may be combined by a capacitor. However, the rated voltage of the driving apparatus may still correspond to the potential of the highest-potential power supply employed by the discharge display apparatus.  
      More particularly, an upper limit of a reset voltage pulse is generally higher than, e.g., an upper limit of a sustain voltage pulse. Although a difference between the upper limit of the sustain voltage pulse and the upper limit of the reset voltage pulse may result from charge stored in a capacitor, generally, a rated voltage of the driving circuit may correspond, e.g., to a potential of the upper limit of the sustain voltage pulse.  
     SUMMARY OF THE INVENTION  
      The invention is therefore directed to a method of driving a discharge display panel and a driving apparatus, which substantially overcome ones or more of the problems due to limitations and disadvantages of the related art.  
      It is therefore a feature of an embodiment of the invention to provide a method of driving a discharge display panel to lower a rated voltage of a driving apparatus.  
      At least one of the above and other features of advantages of the invention may be realized by providing  
      A method of driving a discharge display panel, including X electrode lines, Y electrode lines and address electrode lines, to display at least one frame of an image, wherein the frame includes a plurality of subfields, and during a reset period of at least one of the plurality of subfields, the method includes increasing a potential of the Y electrode lines to a first potential with positive polarity, maintaining the Y electrode lines at the first potential for a setting time, dropping the potential of the Y electrode lines from the first potential to a ground potential, maintaining the Y electrode lines at the ground potential for a predetermined period of time, and gradually dropping the potential of the Y electrode lines from the ground potential to a second potential with negative polarity.  
      Increasing the potential of the Y electrode lines to the first potential may include gradually increasing the potential of the Y electrode lines from a third potential with positive polarity to the first potential with positive polarity. Increasing the potential of the Y electrode lines to the first potential may include substantially instantaneously increasing the potential of the Y electrode lines from the ground potential to the third potential and maintaining the Y electrodes lines at the third potential for a predetermined period of time. Increasing the potential of the Y electrode lines to the first potential involves gradually increasing the potential of the Y electrode lines from the third potential to the first potential.  
      The method may include applying the ground potential to the X electrode lines while increasing the potential of the Y electrode lines from the third potential with positive polarity to the first potential with positive polarity, and while maintaining the Y electrode lines at the first potential during the setting time. The method may include applying a fifth potential with positive polarity lower than the first potential with positive polarity to the X electrode lines, while dropping the potential of the Y electrode lines from the first potential to the second potential.  
      The address electrode lines may be maintained at the ground potential during the reset period. The method may include applying a pulse of the second potential with negative polarity to respective ones of the Y electrode lines to be selected, and applying a fourth potential with negative polarity higher than that second potential with negative polarity to unselected ones of the Y electrode lines. The discharge display panel may be a plasma display panel.  
      At least one of the above and other features of advantages of the invention may be separately realized by providing a method of driving a discharge display panel including X electrode lines, Y electrode lines, and address electrode lines by using a driving apparatus of a discharge display apparatus, the method including dividing a unit frame into a plurality of subfields for a time-sharing gray-scale display, and dividing each of the subfields into a reset period, an addressing period, and a sustain period, wherein the reset period of at least one of the subfields may include a potential rising period during which a potential applied to the Y electrode lines gradually rises to a first potential with positive polarity; a high-potential maintaining period during which the potential applied to the Y electrode lines is maintained at the first potential with positive polarity for a setting time, a stabilizing period during which the potential applied to the Y electrode lines is maintained at a ground potential, and a potential falling period during which the potential applied to the Y electrode lines gradually falls from the ground potential to a second potential with negative polarity.  
      The driving apparatus may include an X driver driving the X electrode lines, an Y driver driving the Y electrode lines, and an address driver driving the address electrode lines, wherein the Y driver may include a reset/sustain circuit generating potentials to be applied to the Y electrode lines during the reset and sustain periods, a scan driving circuit generating potentials to be applied to the Y electrode lines during the addressing period; and a switching output circuit applying the potentials from the reset/sustain circuit and the potentials from the scan driving circuit to the Y electrode lines, wherein the switching output circuit may include upper transistors and lower transistors respectively corresponding to the Y electrode lines, and the method may include applying potentials to the Y electrode lines through the upper transistors of the switching output circuit during the potential rising period, the high-potential maintaining period, and the stabilizing period.  
      During the potential falling period, the method may include applying potentials to the Y electrode lines through the lower transistors of the switching output circuit. The potential applied to the Y electrode lines may gradually rise from a third potential with positive polarity to the first potential with positive polarity. During the addressing period, a pulse of the second potential with negative polarity may be applied to some of the Y electrode lines to be scanned, and a fourth potential with negative polarity higher than the second potential with negative polarity may be applied to the remaining Y electrode lines. The third potential with positive polarity may be generated by a difference between the second potential with negative polarity and the fourth potential with negative polarity during the potential rising period.  
      The ground potential may be applied to the X electrode lines during the potential rising period. A fifth potential with positive polarity lower than the first potential with positive polarity may be applied to the X electrode lines. The discharge display panel may be a plasma display panel.  
      At least one of the above and other features of advantages of the invention may be separately realized by providing a driving apparatus for driving a discharge panel including X electrode lines, Y electrode lines and address electrode lines, the driving apparatus including a processor for dividing a unit frame into a plurality of subfields for a time-sharing gray scale display, and dividing each of the subfields into a reset period, an addressing period, and a sustain period, and a Y driver for driving the Y electrode lines, the Y driver including a reset/sustain circuit for generating potentials to be applied to the Y electrodes lines during the reset and sustain periods, the reset/sustain circuit including potential increasing device for increasing a potential of the Y electrode lines to a first potential with positive polarity, high-potential maintaining device for maintaining the potential of the Y electrode lines at the first potential for a setting time, stabilizing device for stabilizing the Y electrode lines by applying a ground potential to the Y electrode lines, and potential dropping device for allowing the potential applied to the Y electrode lines to gradually fall from the ground potential to a second potential with negative polarity.  
      The driving apparatus may include a scan driving circuit for generating potentials to be applied to the Y electrode lines during the addressing period; and a switching output circuit for applying the potentials from the reset/sustain circuit with potentials from the scan driving circuit to the Y electrode lines, wherein the switching output circuit may include upper transistors and lower transistors respectively corresponding to the Y electrode lines, and the potential increasing device, the high-potential maintaining device and the stabilizing device may use the upper transistors of the switching circuit to control the potentials applied to the Y electrode lines. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
      The above and other features and advantages of the invention will become more apparent to those of ordinary skill in the art by describing in detail exemplary embodiments thereof with reference to the attached drawings in which:  
       FIG. 1  illustrates an internal perspective view of a plasma display panel with a three-electrode surface discharge structure, as an exemplary discharge display device;  
       FIG. 2  illustrates a schematic cross-sectional view of one display cell in the exemplary plasma display panel illustrated in  FIG. 1 ;  
       FIG. 3  illustrates a timing diagram of driving signals that may be applied to Y electrode lines of the plasma display panel illustrated in  FIG. 1  using an address-display separation driving method according to an exemplary embodiment of the invention;  
       FIG. 4  illustrates a block diagram of a driving apparatus employable for driving the plasma display panel illustrated in  FIG. 1 ;  
       FIG. 5  illustrates an exemplary timing diagram of driving signals that may be employed to drive the plasma display panel illustrated in  FIG. 1  during a single exemplary subfield of the driving method employing one or more aspects of the invention;  
       FIG. 6  illustrates a distribution of wall charges at time t 5  of the timing diagram illustrated in  FIG. 5 ;  
       FIG. 7  illustrates a distribution of wall charges at time t 8  of the timing diagram illustrated in  FIG. 5 ;  
       FIG. 8  illustrates an exemplary scan driving circuit and an exemplary switching output circuit that may be employed in the Y driver of the driving apparatus illustrated in  FIG. 4 ;  
       FIG. 9  illustrates an exemplary reset/sustain circuit illustrated in  FIG. 8 ;  
       FIG. 10  illustrates exemplary control signals that may be supplied, during a reset period, to transistors illustrated in  FIGS. 8 and 9 ; and  
       FIG. 11  illustrates an exemplary circuit diagram of the X driver included in the driving apparatus illustrated in  FIG. 4 . 
    
    
     DETAILED DESCRIPTION OF THE INVENTION  
      Korean Patent Application No. 10-2005-0106393, filed on Nov. 8, 2005, in the Korean Intellectual Property Office, and entitled: “Method of Driving Discharge Display Panel to Lower Rated Voltage of Driving Apparatus,” is incorporated by reference herein in its entirety.  
      The invention will now be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments of the invention are illustrated. The invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.  
      In the figures, the dimensions of layers and regions may be exaggerated for clarity of illustration. It will also be understood that when a layer or element is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. Further, it will be understood that when a layer is referred to as being “under” another layer, it can be directly under, and one or more intervening layers may also be present. In addition, it will also be understood that when a layer is referred to as being “between” two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present. Like reference numerals refer to like elements throughout.  
       FIG. 1  illustrates an internal perspective view of a plasma display panel  1  including a three-electrode surface discharge structure, as an exemplary display device that may employ a driving method employing one or more aspects of the invention.  FIG. 2  illustrates a schematic cross-sectional view of one display cell in the plasma display panel  1  illustrated  FIG. 1 .  
      Referring to  FIGS. 1 and 2 , the plasma display panel may include address electrode lines A R1 , . . . , A Bm , upper and lower dielectric layers  11  and  15 , Y-electrode lines Y 1 , . . . , Y n , X-electrode lines X 1 , . . . , X n , phosphors  16 , barrier ribs  17 , and a protective layer  12 , e.g., MgO layer, between front and rear glass substrates  10  and  13 .  
      The address electrode lines A R1 , . . . , A Bm  may be formed in a predetermined pattern on an upper surface of the rear glass substrate  13 . The lower dielectric layer  15  may cover the address electrode lines A R1 , . . . , A Bm . The barrier ribs  17  may extend on an upper surface of the lower dielectric layer  15 . The barrier ribs  17  may extend along a direction that is substantially parallel to a direction along which the address electrode lines A R1 , . . . A Bm . The barrier ribs  17  may partition discharge areas associated with, e.g., respective display cells, and may prevent cross-talk between the display cells. The phosphors  16  may be provided, e.g., between adjacent ones of the barrier ribs  17 .  
      The X-electrode lines X 1 , . . . , X n  and Y electrode lines Y 1 , . . . , Y n  may be formed in a predetermined pattern on a lower surface of the front glass substrate  10 . The X-electrode lines X 1 , . . . , X n  and the Y-electrode lines Y 1 , . . . , Y n  may extend along a direction orthogonal to the direction along which the address electrode lines A R1 , . . . , A Bm  extend. Each intersection may define a corresponding display cell. Each of the X-electrode lines X 1 , . . . , X n  and each of the Y-electrode lines Y 1 , . . . , Y n  may be formed by coupling transparent electrode lines, e.g., X na  and Y na  illustrated in  FIG. 2 , which may include a transparent conductive material, e.g., ITO (Indium Tin Oxide), with metal electrode lines, e.g., X nb  and Y nb  illustrated in  FIG. 2 . The metal electrode lines may help enhance conductivity of the X-electrode lines X 1 , . . . , X n  and each of the Y-electrode lines Y 1 , . . . , Y n . The upper dielectric layer  11  may cover the X-electrode lines X 1 , . . . , X n  and Y electrode lines Y 1 , . . . , Y n . The protective layer  12  may help protect the plasma display panel  1  from a strong electric field. The protective layer  12  may be, e.g., an MgO layer, and may be formed on a lower surface of the front electronic layer  11 . A discharge space  14  may be filled with plasma-forming gas and may be sealed.  
       FIG. 3  illustrates a timing diagram of driving signals that may be applied to Y electrode lines Y 1 , . . . , Y n  of the plasma display panel  1  illustrated in  FIG. 1  using an address-display separation driving method according to an exemplary embodiment of the invention. Referring to  FIG. 3 , each unit frame may be partitioned into a plurality of subfields, e.g., 8 subfields SF 1 , . . . , SF 8 , in order to implement time-sharing gray-scale display. The subfields SF 1 , SF 8  may be divided into reset periods R 1 , . . . , R 8 , addressing periods A 1 , . . . , A 8 , and sustain periods S 1 , . . . , S 8 , respectively.  
      Discharge conditions of all the display cells may be completely and/or substantially completely equalized during the respective reset periods R 1 , . . . , R 8 .  
      During each of the addressing periods A 1 , . . . , A 8 , the display data signal may be sequentially applied to the address electrode lines, e.g., A R1  A Bm  of  FIG. 1 , while injection pulses corresponding to each of the Y electrode lines Y 1 , . . . , Y n  may be sequentially applied to the address electrode lines A R1 , . . . A Bm . Accordingly, if a display data signal with a high level is applied while the injection pulses are applied, wall charges may be generated by address discharge in a corresponding discharge cell, and no wall charge may be generated in the remaining discharge cells.  
      During each of the sustain periods S 1 , . . . , S 8 , sustain pulses may be alternately applied to all the Y electrode lines Y 1 , . . . , Y n  and all the X electrode lines X 1 , . . . , X n , so that the discharge cells in which the wall charges were formed during the previous respective addressing period A 1 , . . . , A 8  may undergo display discharge. Accordingly, luminance of the plasma display panel may be proportional to a length of a sustain period S 1 , . . . , S 8  occupied by a unit frame. The length of the sustain period S 1 , . . . , S 8  occupied by a unit frame may be 255T, where T is a unit of time. Accordingly, the length of the sustain period S 1 , . . . , S 8  may be represented by 256 gradations, including a no-display case in which nothing may be displayed, during the unit frame.  
      Referring to  FIG. 3 , a sustain period S 1  of a first subfield SF 1  may be set to a time 1T corresponding to  2   0 , a sustain period S 2  of a second subfield SF 2  may be set to a time 2T corresponding to  2   1 , a sustain period S 3  of a third subfield SF 3  may be set to a time 4T corresponding to  2   2 , a sustain period S 4  of a fourth subfield SF 4  may be set to a time 8T corresponding to  2   3 , a sustain period S 5  of a fifth subfield SF 5  may be set to a time 16T corresponding to  2   4 , a sustain period S 6  of a sixth subfield SF 6  may be set to a time 32T corresponding to  2   5 , a sustain period S 7  of a seventh subfield SF 7  may be set to a time 64T corresponding to  2   6 , and a sustain period S 8  of an eighth subfield SF 8  may be set to a time 128T corresponding to  2   7 , respectively.  
      Accordingly, by appropriately selecting respective ones of the respective subfields, e.g., eight subfields, to be displayed, a display with corresponding gradation, e.g., 256 gradations may be implemented. The gradations may include a zero (0) gradation, which may correspond to nothing being displayed, e.g., solid black.  
       FIG. 4  illustrates a block diagram of a driving apparatus employable for driving the plasma display panel illustrated in  FIG. 1 . Referring to  FIG. 4 , the driving apparatus may include an image processor  56 , a logic controller  52 , an address driver  53 , an X driver  54 , and a Y driver  55 . The image processor  56  may convert external analog image signals into digital signals to generate clock signals, vertical and horizontal synchronization signals, and internal image signals, e.g., red (R), green (G), and blue (B) image data each including, e.g., 8 bits. The logic controller  52  may generate driving control signals S A , S Y , and S X  according to the internal image signals that may be output from the image processor  56 . The address driver  53  may process an address signal S A  among the driving control signals S A , S Y , and S X  output from the logic controller  52 , generate a display data signal, and transmit the display data signal to the address electrode lines (A R1 , . . . , A Bm  of  FIG. 1 ). The X driver  54  may process an X driving control signal S X  among the driving control signals S A , S Y , and S X  output from the controller  52  and drive the X electrode lines (X 1 , . . . , X n  of  FIG. 1 ). The Y driver  55  may process a Y driving control signal S Y  among the driving control signals S A , S Y , and S X  output from the logic controller  52  and drive the Y electrode lines (Y 1 , . . . , Y n  of  FIG. 1 ).  
       FIG. 5  illustrates an exemplary timing diagram of driving signals that may be employed to drive the plasma display panel illustrated in  FIG. 1  during a single exemplary subfield SF of the driving method employing one or more aspects of the invention. In  FIG. 5 , reference numeral S AR1 . . . ABm  corresponds to a driving signal that may be applied to each of the address electrode lines (A R1 , A G1 , . . . , A Gm , A Bm  of  FIG. 1 ), reference numeral S X1 . . . . Xn  corresponds to a driving signal that may be applied to each of the X electrode lines (X 1 , . . . , X n  of  FIG. 1 ), and reference numeral S Y1 , . . . , S Yn  corresponds to a driving signal that may be applied to each of the Y electrode lines (Y 1 , . . . , Y n  of  FIG. 1 ).  
       FIG. 6  illustrates a distribution of wall charges at time t 5  of the timing diagram illustrated in  FIG. 5 , i.e., after a gradually increasing potential is applied to all the Y electrode lines Y 1 , . . . , Y n  during the reset period R.  FIG. 7  illustrates a distribution of wall charges at time t 8  of the timing diagram illustrated in  FIG. 5 , i.e., after the reset period R is terminated. In  FIGS. 6 and 7 , components having the same reference numerals as those of  FIG. 2  operate in the same manner as the respective components of  FIG. 2 .  
      Referring to  FIG. 5 , during a potential rising period between time t 3  and time t 4  of the reset period R of the unit subfield SF, potential applied to the Y electrode lines Y 1 , . . . , Y n  may consistent rises from a third potential |V SCL −V SCH | with positive polarity to a first potential V SET +|V SCL −V SCH | with positive polarity, e.g., 355 V. The first potential V SET +|V SCL −V SCH | may be a higher than the third potential |V SCL −V SCH | by a sixth potential V SET . The third potential |V SCL −V SCH | with positive polarity may be generated by a difference between a second potential V SCL  with negative polarity and a fourth potential V SCH  with negative polarity. Because the third potential |V SCL −V SCH | and the sixth potential V SET  may be combined by a capacitor, a rated voltage of a reset/sustain circuit (RSC) may be lower than the first potential V SET +|V SCL −V SCH |, which will be described in detail later with reference to  FIGS. 8 through 10 .  
      A ground potential V G  may be applied to the X electrode lines X 1 , . . . , X n  and the address electrode lines A R1 , . . . , A Bm . Accordingly, a weak discharge may be generated between the Y electrode lines Y 1 , . . . , Y n  and the X electrode lines X 1 , . . . , X n , while a weaker discharge may be generated between the Y electrode lines Y 1 , . . . , Y n  and the address electrode lines A R1 , . . . , A Bm .  
      A reason why the discharge between the Y electrode lines Y 1 , . . . , Y n  and the X electrode lines X 1 , . . . , X n  may be stronger than the discharge between the Y electrode lines Y 1 , . . . , Y n  and the address electrode lines A R1 , . . . A Bm  may be because wall charges with negative polarities may be formed around the Y electrode lines Y 1 , . . . , Y n  and more wall charges with positive polarity may be formed around the X electrode lines X 1 , . . . , X n  than the address electrode lines A R1 , . . . , A Bm . That is, many wall charges with negative polarities may be formed around the Y electrode lines Y 1 , . . . , Y n , wall charges with positive polarities may be formed around the X electrode lines X 1 , . . . , X n , and a fewer number of wall charges with positive polarities may be formed around the address electrode lines A R1 , . . . , A Bm  (see  FIG. 6 ).  
      During a high-potential maintaining period between a t 4  timing and a t 5  timing of the reset period R, the potential applied to the Y electrode lines Y 1 , . . . , Y n  during the setting period may be maintained at the first potential V SET +|V SCL −V SCH | with positive polarity.  
      More particularly, during the high-potential maintaining period between the time t 4  and the time t 5  after the potential rising period between the time t 2  and time t 4 , the potential applied to the Y electrode lines Y 1 , . . . , Y n  may be maintained at the first potential V SET +|V SCL −V SCH | with positive polarity. That is, e.g., after the potential rising period between time t 3  and time t 4 , the potential of the Y electrode lines Y 1 , . . . , Y n  may not immediately drop to a fifth potential V S  with positive polarity, which may be lower than the first potential V SET +|V SCL −V SCH | with positive polarity. In embodiments of the invention, the potential of the Y electrode lines Y 1 , . . . , Y n  may be maintained at the first potential V SET +|V SCL −V SCH | with positive polarity before being allowed to substantially constantly and/or gradually fall from the first potential V SET +|V SCL −V SCH | with positive polarity to, e.g., a voltage less than the fifth potential Vs, e.g., the ground voltage Vg.  
      Accordingly, the rated voltage of the driving apparatus may be lowered because two potentials can be combined using the capacitor. That is, the first potential may not affect the rated voltage of the reset/sustain circuit RSC, and the rated voltage of the RSC may be determined by whichever is higher between the third potential |V SCL −V SCH | and the sixth potential V SET . Each of the third potential |V SCL −V SCH | and the sixth potential V SET  may be lower than the fifth potential V S . The determination of the rated voltage of the RSC will be described in detail later with reference to  FIGS. 8 through 10 .  
      During a stabilizing period between a time t 6  and a time t 7  timing, the potential applied to the Y electrode lines Y 1 , . . . , Y n  may be maintained at the ground potential V G  while the potential applied to the X electrode lines X 1 , . . . , X n  may be maintained at the fifth potential V S . Accordingly, electromagnetic waves generated after the potential applied to the Y electrode lines Y 1 , . . . , Y n  falls from the first potential V SET +|V SCL −V SCH | with positive polarity can be eliminated by the ground potential V G .  
      During a potential falling period between the time t 7  timing and a time t 8  of the reset period R, the potential applied to the Y electrode lines Y 1 , . . . , Y n  may gradually fall from the ground potential V G  to the second potential V SCL  with negative polarity while the potential applied to the X electrode lines X 1 , X n  may be maintained at the fifth potential V S . Accordingly, some of the wall charges with negative polarity, which may be formed around the Y electrode lines Y 1 , . . . , Y n  may move to and stay around the X electrode lines X 1 , . . . , X n  due to a discharge between the X electrode lines X 1 , . . . , X n  and the Y electrode lines Y 1 , . . . , Y n  (see  FIG. 7 ). In addition, because the ground potential V G  may be applied to the address electrode lines A R1 , . . . , A Bm , the number of wall charges around the address electrode lines A R1 , . . . , A Bm  may increase slightly.  
      In the following addressing period A, a display data signal may be transmitted to the address electrode lines A R1 , . . . , A Bm  and scan pulses having the ground potential V G  may be sequentially transmitted to the Y electrode lines Y 1 , . . . , Y n . The Y electrode lines Y 1 , . . . , Y n  may be biased by the fourth potential V SCH , so that smooth addressing may be performed. As the display data signal is transmitted to each of the address electrode lines A R1 , . . . , A Bm , an addressing potential V A  with positive polarity may be applied to selected display cells, while the ground potential V G  may be applied to the remaining display cells, i.e., non-selected display cells. Therefore, if the display data signal having the positive-polarity addressing potential V A  is transmitted while the scan pulses having the ground potential V G  are applied, wall charges may be formed by address discharge in the corresponding display cells. No wall charges may be formed in the remaining display cells to which, e.g., the display data signal having the ground potential V G  is applied. In embodiments of the invention, the fifth potential V S  may be applied to the X electrode lines X 1 , . . . , X n , to help improve the accuracy and efficiency of the address discharge process.  
      In the following sustain period S, sustain pulses of the fifth potential V S  with positive polarity may be alternately applied to all the Y electrode lines Y 1 , . . . , Y n , and all the X electrode lines X 1 , . . . , X n , so that discharge for sustain may be generated in the display cells addressed in the previous addressing period A, i.e., display cell with the wall charges formed in the previous addressing period A.  
       FIG. 8  illustrates an exemplary scan driving circuit and an exemplary switching output circuit that may be employed in the Y driver  55  of the driving apparatus illustrated in  FIG. 4 . Referring to  FIG. 8 , the Y driver  55  may include a reset/sustain circuit RSC, a scan driving circuit AC, and a switching output circuit SIC. The reset/sustain circuit RSC may generate driving signals to be transmitted to the Y electrode lines Y 1 , . . . , Y n  during the reset period R and the sustain period S. The scan driving circuit AC may generate driving signals to be transmitted to the Y electrode lines Y 1 , . . . , Y n  during the addressing period A. In the switching output circuit SIC, upper transistors YU 1 , . . . , YUn and lower transistors YL 1 , . . . , YLn may be connected such that common output lines of the upper transistors YU 1 , . . . , YUn and the lower transistors YL 1 , . . . , YLn may respectively correspond to the Y electrode lines Y 1 , . . . , Y n . Exemplary operation of the Y driver  55  will be described with reference to  FIGS. 8 and 5 .  
      During the addressing period A, a high-power transistor S SCL  of the scan driving circuit AC may be on. Accordingly, the second potential V SCL  with negative polarity, which may be a potential of a scan pulse, may be applied to the lower transistors YL 1 , . . . , YLn of the switching output circuit SIC through the high-power transistor S SCL  and a zener diode ZD. In addition, the fourth potential V SCH  with negative polarity, which may be a bias potential for scanning, may be applied to the upper transistors YU 1 , . . . , YUn of the switching output circuit SIC through a diode D M . Therefore, during the addressing period A, a difference voltage |V SCL −V SCH | between the second potential V SCL  with negative polarity and the fourth potential V SCH  with negative polarity may be applied to a high-power capacitor C M .  
      In this state, a lower transistor connected to a Y electrode line to be scanned may be turned on, and an upper transistor connected to the respective Y electrode may be turned off. Lower transistors connected to the remaining Y electrode lines may be turned off, and upper transistors connected to the remaining Y electrode lines may be turned on. Accordingly, the second potential V SCL  with negative polarity, which may be the potential of the scan pulse, may be applied to the Y electrode line to be scanned, and the fourth potential V SCH  with negative polarity, which may be the bias potential for scanning, may be applied to the remaining Y electrode lines.  
       FIG. 9  illustrates an exemplary reset/sustain circuit illustrated in  FIG. 8 . Exemplary operation of the Y driver  55  during the reset period R and the sustain period S will be described with reference to the reset/sustain circuit RSC illustrated in  FIG. 9 .  FIG. 10  illustrates exemplary control signals that may be supplied, during a reset period, to transistors illustrated in  FIGS. 8 and 9 . A method of transmitting an output signal O X  of an X driver  64  to the X electrode lines X 1 , . . . , X n  will be described with reference to  FIG. 10 .  
      Referring to  FIG. 10 , a control signal C YU  may be transmitted to all of the upper transistors YU 1 , . . . , YUn of the switching output circuit SIC included in the Y driver  55  illustrated in  FIG. 8 . A control signal C YL  may be transmitted to all of the lower transistors YL 1 , . . . , YLn of the switching output circuit SIC included in the Y driver  55  illustrated in  FIG. 8 . A control signal C SSCL  may be transmitted to the high-power transistor S SCL  of the scan driving circuit AC included in the Y driver  55  illustrated in  FIG. 8 . A control signal C ST5  may be transmitted to a fifth transistor ST 5  included in the reset/sustain circuit RSC of  FIG. 9 . A control signal C ST8  may be transmitted to an eighth transistor ST 8  included in the reset/sustain circuit RSC illustrated in  FIG. 9 . A control signal C ST2  may be transmitted to a second transistor ST 2  included in the reset/sustain circuit RSC illustrated in  FIG. 9 . A control signal C ST4  may be transmitted to a fourth transistor ST 4  included in the reset/sustain circuit RSC illustrated in  FIG. 9 . A control signal C ST7  may be transmitted to a seventh transistor ST 7  included in the reset/sustain circuit RSC illustrated in  FIG. 9 . Exemplary operation of the reset/sustain circuit RSC illustrated  FIG. 9  will be described with reference to  FIGS. 5, 8 ,  9 , and  10 .  
      During a first period between time t 1  and time t 2  of the reset period R of a unit subfield SF, the lower transistors YL 1 , . . . , YLn of the switching output circuit SIC included in the Y driver  55  may be on, and the fourth transistor ST 4  of the reset/sustain circuit RSC may be on. Accordingly, the ground potential V G  may be applied to the Y electrode lines Y 1 , . . . , Y n .  
      During a second period between time t 2  and time t 3  of the reset period R of the unit subfield SF, the high-power transistor S SCL  of the scan driving circuit AC and the upper transistors YU 1 , . . . , YUn of the switching output circuit SIC may be turned on. Accordingly, an initial potential of an upper electrode of the high-power capacitor C M  may rise to the third potential |V SCL −V SCH | with positive polarity, which may be the difference potential between the second potential V SCL  with negative polarity and the fourth potential V SCH  with negative polarity. In addition, as the lower transistors YL 1 , . . . , YLn of the switching output circuit SIC are turned off and the upper transistors YU 1 , . . . , YUn thereof are turned on, the third potential |V SCL −V SCH | with positive polarity may be applied to the Y electrode lines Y 1 , . . . , Y n .  
      During a third period, e.g., the potential rising period, between the time t 3  and the time t 4 , the upper transistors YU 1 , . . . , YUn of the switching output circuit SIC may be on, the high-power transistor S SCL  thereof may be turned off, and the fifth transistor ST 5  of the reset/sustain circuit RSC may be turned on. In addition, as a control potential with positive polarity, which may be gradually rising, may be applied to a base of an eighth transistor ST 8 , the potential of the Y electrode lines Y 1 , . . . , Y n  may gradually rise from the third potential |V SCL −V SCH | with positive polarity to the first potential V SET +|V SCL −V SCH | with positive polarity, e.g., 355 V. The first potential V SET +|V SCL −V SCH | may be higher than the third potential |V SCL −V SCH | by the sixth potential V SET .  
      Here, since the third potential |V SCL −V SCH | and the sixth potential V SET  may be combined using the capacitor, the rated voltage of the reset/sustain circuit RSC may be lower than the first potential V SET +|V SCL −V SCH | 
      During a fourth period, e.g., the high-potential maintaining period, e.g., between the t 4  timing and the t 5  timing, the upper transistors YU 1 , . . . , YUn of the switching output circuit SIC and the fifth transistor ST 5  of the reset/sustain circuit RSC may remain on, and a highest set potential with positive polarity may be applied to the base of the eighth transistor ST 8 . Accordingly, during the fourth period, e.g., the setting period, between the time t 4  and the time t 5 , the potential applied to the Y electrode lines Y 1 , . . . , Y n  may be maintained at the first potential V SET +|V SCL −V SCH | with positive polarity.  
      As described above, during the high-potential maintaining period, e.g., between the time t 4  and the time t 5 , after the potential rising period, e.g., between the time t 2  and the time t 4 , the potential may be maintained and may not fall to the fifth potential V S  with positive polarity. The fifth potential V S  may be lower than the first potential V SET +|V SCL −V SCH | with positive polarity. Instead, as discussed above, the potential may be maintained, e.g., at the first potential V SET +|V SCL −V SCH | with positive polarity. Accordingly, the rated voltage of the driving apparatus may be lowered because the plurality of potentials, e.g., two potentials, can be combined using the capacitor. That is, the first potential may not affect the rated voltage of the reset/sustain circuit RSC, and the rated voltage of the RSC may be determined by whichever is higher between, e.g., the third potential |V SCL −V SCH | and the sixth potential V SET . Each of the third potential |V SCL −V SCH | and the sixth potential V SET  may be lower than the fifth potential V S .  
      During a fifth period, e.g., between the time t 5  and the time t 6  of the reset period R, the upper transistors YU 1 , . . . , YUn of the switching output circuit SIC and the fifth transistor ST 5  of the reset/sustain circuit RSC may remain on, and the second transistor ST 2  of the reset/sustain circuit RSC may be turned on. Accordingly, unnecessary charges remaining in the display cells, i.e., electrical capacitors, may be collected by a capacitor C SY  for power reproduction through an output terminal O RS , the fifth transistor ST 5 , a tuning coil L Y , a second diode D 2 , and the second transistor ST 2 .  
      During a sixth period, e.g., the stabilization period, between the time t 6  timing and the time t 7 , the upper transistors YU 1 , . . . , YUn of the switching output circuit SIC and the fifth transistor ST 5  of the reset/sustain circuit RSC may remain on, and the fourth transistor ST 4  of the reset/sustain circuit RSC may be turned on. Accordingly, the ground potential V G  may be applied to the Y electrode lines Y 1 , . . . , Y n  through the fourth transistor ST 4  of the reset/sustain circuit RSC, the fifth transistor ST 5 , the output terminal O RS , and the lower transistors YL 1 , . . . , YLn of the switching output circuit SIC. Therefore, electromagnetic waves generated after the potential applied to the Y electrode lines Y 1 , . . . , Y n  falls from the first potential V SET +|V SCL −V SCH | with positive polarity may be eliminated by the ground potential V G .  
      During a seventh period, e.g., the potential falling period, between the time t 7  and the time t 8  of the reset period R, a gradually rising potential with positive polarity may be applied to a gate of a seventh transistor ST 7  while the upper transistors YU 1 , . . . , YUn of the switching output circuit SIC may be turned off, the lower transistors YL 1 , . . . , YLn of the switching output circuit SIC are turned on, and the fifth transistor ST 5  of the reset/sustain circuit RSC may be turned off. Consequently, channel resistance of the seventh transistor ST 7  may gradually decrease. Accordingly, the potential applied to the Y electrode lines Y 1 , . . . , Y n  may gradually fall from the ground potential V G  to the second potential V SCL  with negative polarity.  
      During the following addressing period A, all the transistors ST 1  through ST 8  of the reset/sustain circuit RSC may be turned off, and the output terminal O RS  of the reset/sustain circuit RSC may be put in an electrically floating state.  
      During the following sustain period S, the upper transistors YU 1 , YUn of the switching output circuit SIC may be turned off and the lower transistors YL 1 , . . . , YLn may be turned on. Exemplary operation of the reset/sustain circuit RSC is described below.  
      In a unit pulse applied to all the Y electrode lines Y 1 , . . . , Y n , while, e.g., the potential applied to all the Y electrode lines Y 1 , . . . , Y n  falls from the fifth potential V S  with positive polarity to the ground potential V G , only the second and fifth transistors ST 2  and ST 5  may be turned on. Accordingly, unnecessary charges remaining in the display cells, i.e., electrical capacitors, may be collected by the capacitor C SY  for power reproduction. The collected charges may be applied to all the Y electrode lines Y 1 , . . . , Y n  and may be reused. For example, such collected charges may be reused while the potential applied to the Y electrode lines Y 1 , . . . , Y n  is driven to rise from the ground potential V G  to the fifth potential V S  with positive polarity.  
      In a unit pulse applied to all the Y electrode lines Y 1 , . . . , Y n  during the sustain period S, while, e.g., the potential applied to the Y electrode lines Y 1 , . . . , Y n  rises from the ground potential V G  to the fifth potential V S  with positive polarity, the first and fifth transistors ST 1  and ST 5  may be turned on. Accordingly, the charges collected by the capacitor C SY  for power reproduction may be applied to all the Y electrode lines Y 1 , . . . , Y n  through a first field effect transistor ST 1 , a first diode D 1 , the tuning coil L Y , a fifth field effect transistor ST 5 , and the output terminal O RS .  
      Then, the third and fifth transistors ST 3  and ST 5  may be turned on. Thus, the fifth potential V S  with positive polarity may be applied to all the Y electrode lines Y 1 , . . . , Y n . The third and fifth transistors ST 3  and ST 5  may be turned on when the sustain pulses stop rising.  
      When the potential applied to the Y electrode lines Y 1 , . . . , Y n  falls from the fifth potential V S  to the ground potential V G , the second and fifth transistors ST 2  and ST 5  may be turned on. Accordingly, unnecessary charges remaining in the display cells, i.e., electrical capacitors, may be collected by the capacitor C SY  for power reproduction through the output terminal O RS , the fifth transistor ST 5 , the tuning coil L Y , the second diode D 2 , and the second transistor ST 2 .  
      Finally, the fourth and fifth transistors ST 4  and ST 5  may be turned on, and the ground potential V G  may be applied to all the Y electrode lines Y 1 , Y n .  
       FIG. 11  illustrates an exemplary circuit diagram of the X driver included in the driving apparatus illustrated in  FIG. 4 . Exemplary operation of the X driver  64  using a driving method employing one or more aspects of the invention will be described with reference to  FIGS. 11 and 5 .  
      In the potential rising period between, e.g., the time t 1  and the time t 2  of the reset period R of the unit subfield SF, a fourth transistor ST 4   a  may be turned on. Thus, an output signal O X  of the X driver  64  may become the ground potential V G .  
      In the stabilizing period between, e.g., the time t 2  the time t 3 , the potential falling period between the time t 3  and the time t 4 , and the addressing period between the time t 4  and the time t 6 , a third transistor ST 3   a  may be turned on. Thus, the potential of the output signal O X  may become the fifth potential V S .  
      In a unit pulse applied to all the X electrode lines X 1 , . . . , X n  during, e.g., the following sustain period S, a second transistor ST 2   a  may be turned on while the potential applied to the X electrode lines X 1 , . . . , X n  may fall from the fifth potential V S  to the ground potential V G . Accordingly, unnecessary charges remaining in the display cells, i.e., electrical capacitors, may be collected by a capacitor C SX  for power reproduction. The collected charges are applied to all the X electrode lines X 1 , . . . , X n  and thus reused while the potential applied to all the X electrode lines X 1 , . . . , X n  rises from the ground potential V G  to the fifth potential V S  with positive polarity.  
      In the unit pulse applied to all the X electrode lines X 1 , . . . , X n  during the sustain period S, while the potential applied to the X electrode lines X 1 , . . . , X n , rises from the ground potential V G  to the fifth potential V S  with positive polarity, the first transistor ST 1   a  is turned on. Accordingly, the charges collected by the capacitor C SX  for power reproduction may be applied to all the X electrode lines X 1 , . . . , X n  through the first transistor ST 1   a , a fifth diode D 5 , a tuning coil L X , and the output terminal O X    
      Then, a third transistor ST 3   a  is turned on, and the fifth potential V S  with positive polarity may be applied to all the X electrode lines X 1 , . . . , X n . The third transistor ST 3   a  is turned on when the sustain pulses stop rising.  
      When the potential applied to the X electrode lines X 1 , . . . , X n  falls from the fifth potential V S  to the ground potential V G , the second transistor ST 2   a  is turned on. Accordingly, unnecessary charges remaining in the display cells, i.e., electrical capacitors, may be collected by the capacitor C SX  for power reproduction through the tuning coil L X , a sixth diode D 6 , and the second transistor ST 2   a.    
      Finally, the fourth transistor ST 4   a  may be turned on, and the ground potential V G  may be applied to all the X electrode lines X 1 , . . . , X n .  
      As described above, according to a method of driving a discharge display panel, after a potential rising period, the highest potential may be maintained during a high-potential maintaining period before falling to a lower potential. Accordingly, a rated voltage of a driving apparatus employing such a driving method may be lowered because two potentials may be combined using a charge storage device, e.g., a capacitor. Thus, the highest potential does not affect the rated voltage of the driving apparatus.  
      Although exemplary embodiments of the driving method may be described in relation to an exemplary plasma display device, embodiments of the invention are not limited to use with a plasma display device. Plasma display devices are merely one type of device that may employ a driving method employing one or more aspects of the invention. For example, driving methods employing one or more aspects of the invention may be employed by various discharge display devices including, e.g., a three electrode structure.  
      Exemplary embodiments of the invention have been disclosed herein, and although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purpose of limitation. Accordingly, it will be understood by those of ordinary skill in the art that various changes in form and details may be made without departing from the spirit and scope of the invention as set forth in the following claims.