Patent Publication Number: US-9887007-B1

Title: Variable-resistance memory and writing method thereof

Description:
CROSS REFERENCE TO RELATED APPLICATION 
     The present application is based on, and claims priority from, Taiwan Application Serial Number 105135853, filed on Nov. 4, 2016, the disclosure of which is hereby incorporated by reference herein in its entirety. 
     TECHNICAL FIELD 
     The disclosure relates to a variable-resistance memory and a writing method thereof. 
     BACKGROUND 
     A variable-resistance memory stores different data based on different resistance. For example, a low resistance value may represent “0”, and a high resistance value may represent “1”. In general, different data, which is written to the variable-resistance memory, may correspond to different writing operations of the variable-resistance memory. 
     For example, when writing “0” (which is represented by a low resistance), the variable-resistance memory may perform the low resistance during the writing operation. In such cases, the variable-resistance memory usually makes the current below the clamping current to control the resistance of the component in the variable-resistance memory. In general, the resistance of the component is controlled by the voltage on the word line (WL), but the clamping current may change due to the process variation of the transistors. 
     On the other hand, when writing “1” (which is represented by a high resistance), the voltage on the word line should be controlled carefully. If the voltage on the word line is too low, then the writing operation may fail or perform the resistance which is too low. If the voltage on the word line is too high, then the components in the variable-resistance memory may be damaged, which causes the malfunction of the variable-resistance memory. In general, when writing “1” (which is represented by a high resistance) to the variable-resistance memory, it usually protects the circuit by performing the writing-verification operation. For example, the writing-verification operation may verify the variable-resistance memory. If the data is not written into the variable-resistance memory successfully, then the writing-verification operation increases the voltage on the word line and performs the writing operation again. The verification and the writing operation of the writing-verification operation are executed repeatedly until the verification shows that the data is successfully written into the variable-resistance memory. The writing-verification operation described above may spend extra energy and operation time. 
     SUMMARY 
     One exemplary embodiment provides a variable-resistance memory. The variable-resistance memory comprises a variable-resistance memory cell, a voltage-signal-generation circuit, a switch circuit, a detection circuit, and a controller. 
     The variable-resistance memory cell comprises a variable-resistance component and a transistor. A first terminal of the transistor is connected to a first terminal of the variable-resistance component. The voltage-signal-generation circuit is coupled to a control terminal of the transistor. The switch circuit is coupled to a second terminal of the transistor and a second terminal of the variable-resistance component. The detection circuit is coupled to a voltage source, wherein a first terminal and a second terminal of the detection circuit are coupled to the switch circuit. The controller is coupled to the voltage-signal-generation circuit, the switch circuit, and the detection circuit. 
     The controller executes control actions when the controller performs the first writing operation on the variable-resistance memory cell. The control actions include controlling the switch circuit to make the second terminal of the variable-resistance component couple to the first terminal of the detection circuit and make the second terminal of the transistor couple to the second terminal of the detection circuit; activating the detection circuit to let the detection circuit continuously detect a first current flowing through the variable-resistance component; and activating the voltage-signal-generation circuit to let the voltage-signal-generation circuit provide a voltage signal to the control terminal of the transistor. 
     If the detection circuit determines that the first current is less than a first predetermined current when the controller performs the first writing operation on the variable-resistance memory cell, then the detection circuit transmits a detection signal to the controller to make the controller stop performing the first writing operation. 
     One exemplary embodiment provides a writing method of a variable-resistance memory. The writing method includes performing, by a controller, a first writing operation on a variable-resistance memory cell. The first writing operation includes controlling, by the controller, a switch circuit to make a first terminal of a variable-resistance component of the variable-resistance memory cell couple to a first terminal of a detection circuit and make a first terminal of a transistor of the variable-resistance memory cell couple to a second terminal of the detection circuit; activating, by the controller, the detection circuit to let the detection circuit continuously detect a first current flowing through the variable-resistance component; activating, by the controller, a voltage-signal-generation circuit to let the voltage-signal-generation circuit provide a voltage signal to a control terminal of the transistor; and if the detection circuit determines that the first current is less than a first predetermined current, then the detection circuit transmits a detection signal to the controller to make the controller stop performing the first writing operation. 
    
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
       The present disclosure can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein: 
         FIG. 1  is a schematic view of a variable-resistance memory according to an exemplary embodiment; 
         FIG. 2A-2B  are schematic views of variable-resistance memory circuits according to some exemplary embodiments; 
         FIG. 3A  is a schematic view of a voltage-signal-generation circuit according to an exemplary embodiment; 
         FIG. 3B  is an output signal waveform of the voltage-signal-generation circuit of  FIG. 3A ; 
         FIG. 4A  is a schematic view of a voltage-signal-generation circuit according to an exemplary embodiment; 
         FIG. 4B  is an output signal waveform of the voltage-signal-generation circuit of  FIG. 4A ; 
         FIG. 5A  is a schematic view for a writing operation according to an exemplary embodiment; 
         FIG. 5B  is the voltage and current waveforms correspond to the writing operation of  FIG. 5A ; 
         FIG. 6A  is a schematic view for another writing operation according to an exemplary embodiment; 
         FIG. 6B  is the voltage and current waveforms correspond to the writing operation of  FIG. 6A ; 
         FIG. 7  is a flow diagram of a writing operation according to an exemplary embodiment; 
         FIG. 8  is a flow diagram of a writing operation according to an exemplary embodiment. 
     
    
    
     DETAILED DESCRIPTION 
     In the following detailed description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the disclosed embodiments. It will be apparent, however, that one or more embodiments may be practiced without these specific details. In other instances, well-known structures and devices are schematically shown in order to simplify the drawing. 
       FIG. 1  is a schematic view of a variable-resistance memory  100  according to an exemplary embodiment. The variable-resistance memory  100  stores data based on different resistance. The variable-resistance memory  100  includes a variable-resistance memory array  101 , a voltage-signal-generation circuit  102 , a switch circuit  103 , a detection circuit  104 , and a controller  105 . When the controller  105  performs a writing operation on at least one variable-resistance memory cell of the variable-resistance memory array  101 , the controller  105  controls the switch circuit  103  to make the variable-resistance memory cell, which is selected and performed the writing operation by the controller  105 , couple to the detection circuit  104 . Afterward, the detection circuit  104  may provide voltage to the selected variable-resistance memory cell and detect the current flowing through the selected variable-resistance memory cell. 
     After the selected variable-resistance memory cell is coupled to the detection circuit  104  through the switch circuit  103 , the controller  105  activates the voltage-signal-generation circuit  102  to provide a voltage signal of the voltage-signal-generation circuit  102  to the selected variable-resistance memory cell. The voltage signal may gradually change over time, and the current flowing through the selected variable-resistance memory cell may be changed based on the voltage signal. 
     When the voltage value of the voltage signal is substantially equal to a specific voltage value, the resistance of the variable-resistance component of the variable-resistance memory cell performs a resistance conversion, such as the variable-resistance component may be converted from high resistance to low resistance or converted from low resistance to high resistance. The detection circuit  104  then detects the current variation caused by the resistance conversion (i.e. the current variation of the selected variable-resistance memory cell) and transmits a detection signal corresponding to the resistance conversion to the controller  105 . The controller  105  stops performing the writing operation on the selected variable-resistance memory cell based on the detection result of the detection circuit  104 . 
     In some embodiments, the voltage signal of the voltage-signal-generation circuit  102  may have a voltage waveform which gradually increases during the writing operation, but the embodiments are not limited thereto. 
       FIG. 2A  is a schematic view of a variable-resistance memory  200  according to some exemplary embodiments.  FIG. 2  depicts a first writing operation of a selected variable-resistance memory cell  201  in a variable-resistance memory array of a variable-resistance memory  200 . In this embodiment, the variable-resistance memory  200  includes a variable-resistance memory cell  201 , a voltage-signal-generation circuit  202 , a switch circuit  203 , a detection circuit  204 , and a controller  205 . 
     The variable-resistance memory cell  201  includes a variable-resistance component R 21  and a transistor M 21 . The variable-resistance component R 21  and the transistor M 21  are connected to each other. The voltage-signal-generation circuit  202  is connected to a control terminal of the transistor M 21  (e.g., a gate terminal of the transistor M 21 ) and utilized to provide voltage signal V s1  to the control terminal of the transistor M 21 , wherein the control terminal is connected to a word line WL of the variable-resistance memory array. The switch circuit  203  is connected to a terminal d 20  of the transistor M 21 , a terminal d 10  of the variable-resistance component R 21 , and terminals d 11  and d 21  of the detection circuit  204 . The terminal d 20  is connected to a source line SL of the variable-resistance memory array, and the terminal d 10  is connected to a bit line BL of the variable-resistance memory array. In this embodiment, the detection circuit  204  is coupled to a voltage source (not shown in  FIG. 2A ), and the controller  205  is connected to, and utilized to control, the voltage-signal-generation circuit  202 , the switch circuit  203 , and the detection circuit  204 . 
     As shown in  FIG. 2A , controller  205  may perform the first writing operation on the variable-resistance memory cell  201 . In such cases, the controller  205  may control the switch circuit  203  to couple the terminal d 10  of the variable-resistance component R 21  and the terminal d 20  of the transistor M 21  to the terminal d 11  and the terminal d 21  of the detection circuit  204 , respectively. Under these conditions, the detection circuit  204  can provide voltage V d1  to the variable-resistance memory cell  201  and detect the current I 1  of the variable-resistance memory cell  201 . Afterward, the controller  205  may activate voltage-signal-generation circuit  202  to transmit a voltage signal V s1  to the control terminal of the transistor M 21 . In this embodiment, the current I 1  which flows through the transistor M 21  and the variable-resistance component R 21  may be changed according to the voltage signal V s1 . When the current I 1  increases, the voltage measured across the variable-resistance component R 21  also increases. Accordingly, when the voltage signal V s1  of the voltage-signal-generation circuit  202  is substantially equal to a specific voltage value, the specific voltage value causes the current I 1 , which flows through the transistor M 21  and the variable-resistance component R 21 , to be substantially equal to a specific current, which makes the variable-resistance component R 21  receive sufficient bias voltage to perform a resistance conversion. The resistance conversion changes the resistance of the variable-resistance component R 21  from low resistance to high resistance. After the variable-resistance component R 21  performs the resistance conversion, the current I 1  is reduced because of the resistance conversion, and the detection circuit  204  detects that the current I 1  is less than a predetermined current. In such cases, the detection circuit  204  transmits a detection signal corresponding to the current I 1 , which is less than the predetermined current, to the controller  205 . The controller  205  stops performing the first writing operation on the variable-resistance memory cell  201  based on the detection signal. 
     In some embodiments, when the variable-resistance memory cell  201  is not selected to be written and the controller  205  performs at least one writing operation on one or more of other variable-resistance memory cells, the controller  205  controls the switch circuit  203  to disconnect the connection between the variable-resistance memory cell  201  and the detection circuit  204 . In some embodiments, when the variable-resistance memory cell  201  is not selected to be written and the controller  205  performs at least one writing operation on one or more of other variable-resistance memory cells, the controller controls the switch circuit  203  to make the terminal d 10  and terminal d 20  of the variable-resistance memory cell  201  connect to the same voltage node, such as voltage supply or ground. In some embodiments, the transistor M 21  may be an N-type metal-oxide-semiconductor field effect transistor (MOSFET), and the voltage signal V s1  of the voltage-signal-generation circuit  202  has a voltage waveform which increases during the first writing operation. In some embodiments, the transistor M 21  may be a P-type MOSFET, and the voltage signal V s1  of the voltage-signal-generation circuit  202  has a voltage waveform which decreases during the first writing operation. In some embodiments, the transistor M 21  may be any component whose conductive current and the input voltage are proportional to each other. In some embodiments, when the controller  205  stops performing the first writing operation on the variable-resistance memory cell  201 , the controller  205  controls the switch  203  to disconnect the connection between the transistor M 21  and the detection circuit  204  or disconnect the connection between the variable-resistance component R 21  and the detection circuit  204 . In some embodiments, when the controller  205  stops performing the first writing operation on the variable-resistance memory cell  201 , the controller  205  turns off the voltage-signal-generation  202  or the detection circuit  204 . In some embodiments, variable-resistance component R 21  may be adopted by a Spin Torque Transfer (STT) random access memory (RAM), a unipolar resistance random access memory, or a bipolar resistance random access memory, etc. 
     An embodiment of a second writing operation for the variable-resistance memory cell  201  of the variable-resistance memory  200  is illustrated in  FIG. 2B . In this embodiment, the controller  205  may control the switch circuit  203  to couple the terminal d 10  of the variable-resistance component R 21  and the terminal d 20  of the transistor M 21  to the terminal d 21  and the terminal d 11  of the detection circuit  204 , respectively. Under these conditions, the detection circuit  204  can provide voltage V d2  to the variable-resistance memory cell  201  and detect the current I 2  of the variable-resistance memory cell  201 . Afterward, the controller  205  may activate voltage-signal-generation circuit  202  to transmit a voltage signal V s2  to the control terminal of the transistor M 21 . In this embodiment, the current I 2  which flows through the transistor M 21  and the variable-resistance component R 21  may be changed according to the voltage signal V s2 . When the current I 2  increases, the voltage measured across the variable-resistance component R 21  also increases. Accordingly, when the voltage signal V s2  of the voltage-signal-generation circuit  202  is substantially equal to a second specific voltage value (or the specific voltage value described above), the second specific voltage value (or the specific voltage value described above) causes the current I 2 , which flows through the transistor M 21  and the variable-resistance component R 21 , to be substantially equal to a second specific current (or the specific current described above), which makes the variable-resistance component R 21  receive sufficient bias voltage to perform a second resistance conversion. In this embodiment, the second resistance conversion changes the resistance of the variable-resistance component R 21  from high resistance to low resistance. After the variable-resistance component R 21  performs the second resistance conversion, the current I 2  is increased because of the resistance conversion, and the detection circuit  204  detects that the current I 2  is greater than a second predetermined current. In such cases, the detection circuit  204  transmits a second detection signal corresponding to the current I 2 , which is greater than the second predetermined current, to the controller  205 . The controller  205  stops performing the second writing operation on the variable-resistance memory cell  201  according to the second detection signal. 
     In some embodiments, the transistor M 21  may be an N-type metal-oxide-semiconductor field effect transistor (MOSFET), and the voltage signal V s2  of the voltage-signal-generation circuit  202  has a voltage waveform which increases during the second writing operation. In some embodiments, the transistor M 21  may be a P-type MOSFET, and the voltage signal V s2  of the voltage-signal-generation circuit  202  has a voltage waveform which decreases during the second writing operation. In some embodiments, when the controller  205  stops performing the second writing operation on the variable-resistance memory cell  201 , the controller  205  controls the switch  203  to disconnect the connection between the transistor M 21  and the detection circuit  204  or disconnect the connection between the variable-resistance component R 21  and the detection circuit  204 . In some embodiments, when the controller  205  stops performing the second writing operation on the variable-resistance memory cell  201 , the controller  205  turns off the voltage-signal-generation  202  or the detection circuit  204 . In some embodiments, the switch circuit  203  may include a plurality of switch components, such as transistors. In some embodiments, the sizes of the components of the detection circuit  204  may be increased (e.g., transistor with larger size or passive component with larger size) to reduce the impact of the process variation. In some embodiments, the voltage signal V s1  and the voltage signal V s2  may have the same voltage waveform. 
     In this embodiment, voltage signal V s1  and voltage signal Vs 2  respectively control current I 1  and I 2  through transistor M 21 . When a variable-resistance memory cell (e.g., variable-resistance memory cell  201 ) of the variable-resistance memory array is not operating (i.e. the variable-resistance memory cell is not selected to be read or written), the leakage current of the variable-resistance memory cell can be reduced based on the arrangement of the transistor M 21 . Additionally, the voltage signal V s1  or voltage signal Vs 2  provided by the voltage-signal-generation circuit  202  during the writing operation may not be affected by the variation of the variable-resistance component R 21 , so the malfunction of writing operation may be avoided. 
       FIG. 3A  is a schematic view of a voltage-signal-generation circuit  300  according to an exemplary embodiment. The voltage-signal-generation circuit  300  includes the counter  301  and digital-to-analog convertor  302 . In one embodiment, the counter  301  may be a two-bit counter, and the digital-to-analog convertor  302  may be a two-bit digital-to-analog convertor. In that case, the output voltage V o3  of the voltage-signal-generation circuit  300  may be illustrated as  FIG. 3B . As shown in  FIG. 3B , the voltage-signal-generation circuit  300  can generate a voltage waveform that gradually increases over a period of time, such as the voltage waveform represented by the voltage V 1  to voltage V 4 , wherein the voltage V 1  to voltage V 4  correspond to the output signal of the two-bit counter. 
       FIG. 4A  is a schematic view of a voltage-signal-generation circuit  400  according to an exemplary embodiment. The voltage-signal-generation circuit  400  includes transistors M 41 -M 47 , a NAND logic gate  401 , an operational amplifier  402 , a NOT logic gate  403 , and a capacitor C. The voltage-signal-generation circuit  400  is connected to a supply voltage V DD , voltage V 5 , and voltage V 6 . The output voltage V o4  of the voltage-signal-generation circuit  400  is illustrated in  FIG. 4B . As shown in  FIG. 4B , based on the control signal EN, the output voltage V o4  may have a voltage waveform which gradually increases over a period of time (i.e. from the voltage V 5  to the voltage V 6 ). In this embodiment, transistors M 41 , M 43 , and M 46  are P-type MOSFET, and the transistors M 42 , M 44 , M 45 , and M 47  are N-type MOSFET. 
       FIG. 5A  is a schematic view for a writing operation of a variable-resistance memory  500  according to an exemplary embodiment.  FIG. 5A  depicts a variable-resistance memory circuit  500  including a variable-resistance memory cell  501 , a switch circuit  503 , and a detection circuit  504 . The circuit arrangement in  FIG. 5A  may correspond to the circuit arrangement of the second writing operation in  FIG. 2B . 
     The variable-resistance memory cell  501  includes a transistor M 51  and a variable-resistance component R 51 . The gate of the transistor M 51  receives a voltage signal V 5g  transmitted from a voltage-signal-generation circuit of the variable-resistance memory  500 . The detection circuit  504  includes a current mirror circuit consisting of transistors M 52  and M 53 , the operational amplifier  506 , and the resistor R 5 , wherein the detection circuit  504  is coupled to a supply voltage V DD  and a voltage V b5 . In this embodiment, the detection circuit  504  continuously detects the current I 5  flowing through the transistor M 51  and the variable-resistance component R 51 . 
     The writing operation of the variable-resistance memory  500  may be illustrated in  FIG. 5B . As shown in  FIG. 5B , the current I 5 , which flows through the transistor M 51  and the variable-resistance component R 51 , increases based on the voltage signal V 5g . At time t 51 , the variable-resistance component R 51  performs the resistance conversion, which converts the resistance of the variable-resistance component R 51  from high resistance to low resistance. Accordingly, the current I 5  rapidly increases. At time t 52 , the current I 5  is greater than or equal to a predetermined current I 5t . The current mirror circuit of the detection circuit  504  provides a current corresponding to the I 5  to the resistor R 5 , which makes the voltage measured across the resistor R 5  higher than the voltage V 5b . In such cases, the output voltage V o5  of the detection circuit  504  is changed from the voltage V L  to the voltage V H , and then the detection circuit  504  transmits the output voltage V o5  to a controller of the variable-resistance memory  500 . Afterward, the controller controls the switch circuit  503  to disconnect the connection linked by the switch circuit  503  based on the output voltage V o5  with the voltage V H  (i.e. the detection signal), which terminates the writing operation. 
     In some embodiments, variable-resistance component R 51  may be adopted by a Spin Torque Transfer (STT) RAM, a unipolar resistance random access memory, or a bipolar resistance random access memory. In some embodiments, the detection circuit  504  may use large components (e.g. transistors or resistors with a relatively large size compared to other components in the same circuit design), which may reduce the impact of the process variation and control the current I 5  accurately. 
       FIG. 6A  is a schematic view for a writing operation of a variable-resistance memory  600  according to an exemplary embodiment.  FIG. 6A  depicts a variable-resistance memory  600  including a variable-resistance memory cell  601 , a switch circuit  603 , and a detection circuit  604 . The circuit arrangement in  FIG. 6A  may correspond to the circuit arrangement of the first writing operation in  FIG. 2A . 
     The variable-resistance memory cell  601  includes a transistor M 61  and a variable-resistance component R 61 . The gate of the transistor M 61  receives a voltage signal V 6g  transmitted from a voltage-signal-generation circuit of the variable-resistance memory  600 . The detection circuit  604  includes a current mirror circuit that consists of transistors M 62  and M 63 , the operational amplifier  606 , and the resistor R 6 , wherein the detection circuit  604  is coupled to a supply voltage V DD  and the voltage V b6 . In this embodiment, the detection circuit  604  continuously detects the current I 6  flowing through the transistor M 61  and the variable-resistance component R 61 . 
     The writing operation of the variable-resistance memory  600  may be illustrated in  FIG. 6B . As shown in  FIG. 6B , the current I 6 , which flows through the transistor M 61  and the variable-resistance component R 61 , increases based on the voltage signal V 6g . At time t 61 , the variable-resistance component R 61  performs the resistance conversion, which converts the resistance of the variable-resistance component R 61  from low resistance to high resistance. Accordingly, the current I 6  rapidly decreases. At time t 62 , the current I 6  is lower than or equal to a predetermined current I 6t . The current mirror circuit of the detection circuit  604  provides a current corresponding to the I 6  to the resistor R 6 , which makes the voltage measured across the resistor R 6  lower than the voltage V 6b . In such cases, the output voltage V o6  of the detection circuit  604  is changed from the voltage V H  to the voltage V L , and then the detection circuit  604  transmits the output voltage V o6  to a controller of the variable-resistance memory  600 . Afterward, the controller controls the switch circuit  603  to disconnect the connection linked by the switch circuit  603  based on the output voltage V o6  with the voltage V L  (i.e. the detection signal), which terminates the writing operation. In this embodiment, when the variable-resistance memory  600  performs the writing operation based on the resistance conversion, which converts the low resistance to high resistance, the variable-resistance memory  600  can continuously detects the current I 6  flowing through the transistor M 61  and the variable-resistance component R 61  to efficiently determine whether the writing operation is complete. In other words, according to the embodiments shown in  FIG. 6A-6B , the present embodiment provides a writing-verification operation. The writing-verification operation of the present embodiment is more time efficient and more power efficient than the writing-verification operation which executes the writing operation and the verification operation separately. 
     In some embodiments, a variable-resistance component R 61  may be adopted by a Spin Torque Transfer (STT) RAM, a unipolar resistance random access memory, or a bipolar resistance random access memory. In some embodiments, after the controller of the variable-resistance memory  600  activates the voltage-signal-generation circuit to transmit the voltage signal V 6g  to the gate of the transistor M 61 , the controller delays reception of the output voltage V o6  of the detection circuit  604  for a predetermined time. 
       FIG. 7  is a flow diagram  700  of a writing operation according to an exemplary embodiment. The flow diagram  700  may be applied to the circuit in  FIG. 2A  or  FIG. 6A . In step  701 , a controller controls a switch circuit to couple a variable-resistance memory cell to a detection circuit. In step  702 , the controller activates the detection circuit to make the detection circuit continuously detect a first current flowing through the variable-resistance memory cell. In step  703 , the controller activates a voltage-signal-generation circuit to make the voltage-signal-generation circuit provide a voltage signal to the variable-resistance memory cell. In step  704 , the detection circuit determines whether the first current is less than a first predetermined current. If the first current is less than the first predetermined current, the writing operation proceeds to step  705 . Otherwise, the writing operation proceeds to step  704 . In step  705 , the detection circuit transmits a detection signal to the controller to make the controller stop performing the writing operation. 
     In some embodiments, after the controller activates the voltage-signal-generation circuit, the controller delays reception of the detection signal for a predetermined time. 
       FIG. 8  is a flow diagram  800  of a writing operation according to an exemplary embodiment. The flow diagram  800  may be applied to the circuit in  FIG. 2B  or  FIG. 5A . In step  801 , a controller controls a switch circuit to couple a variable-resistance memory cell to a detection circuit. In step  802 , the controller activates the detection circuit to make the detection circuit continuously detect a first current flowing through the variable-resistance memory cell. In step  803 , the controller activates a voltage-signal-generation circuit to make the voltage-signal-generation circuit provide a voltage signal to the variable-resistance memory cell. In step  804 , the detection circuit determines whether the first current is greater than a predetermined current. If the first current is greater than the predetermined current, the writing operation proceeds to step  805 . Otherwise, the writing operation proceeds to step  804 . In step  805 , the detection circuit transmits a detection signal to the controller to make the controller stop performing the first writing operation. 
     It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed embodiments. It is intended that the specification and examples be considered as exemplary only, with a true scope of the disclosure being indicated by the following claims and their equivalents.