Patent Publication Number: US-2021184156-A9

Title: Array substrate, method for manufacturing the same, and display device

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This patent application claims the benefit and priority of Chinese Patent Application No. 201910001327.3 filed on Jan. 2, 2019, the disclosure of which is incorporated by reference herein in its entirety as part of the present application. 
     BACKGROUND 
     Embodiments of the present disclosure relate to a field of display technologies, and in particular, to an array substrate, a method for manufacturing the same, and a display device. 
     Organic Light Emitting Diode (OLED) display devices are becoming the most promising display devices in recent years due to their advantages such as self-illumination, all-solid-state, and high contrast. 
     The top-emitting OLED display device can significantly improve the aperture ratio of the OLED display device and increase the Pixels Per Inch (PPI), thus it becomes a hot spot for the development of OLED high resolution display technology. 
     BRIEF DESCRIPTION 
     Embodiments of the present disclosure provide an array substrate, a method for manufacturing the same, and a display device. 
     One aspect of the present disclosure provides an array substrate. The array substrate includes a substrate, a first dielectric layer disposed on the substrate, the first dielectric layer having recesses, a first conductive layer covering the first dielectric layer, and auxiliary conductive portions disposed in the recesses and contacting the first conductive layer. 
     In an embodiment of the present disclosure, the first dielectric layer includes a pixel defining layer. The pixel defining layer has openings for defining pixels and inter-pixel portions disposed between the openings. The recesses are disposed in the inter-pixel portions of the pixel defining layer. 
     In an embodiment of the present disclosure, recesses are configured to have at least one of the following configurations: 1) the recesses include first recesses extending in a row direction, 2) the recesses include second recesses extending in a column direction, and 3) the recesses include the first recesses extending in the row direction and the second recesses extending in the column direction. 
     In an embodiment of the present disclosure, the array substrate further includes a second conductive layer disposed on the substrate, a projection of at least a portion of the second conductive layer on the substrate overlapping with a projection of the openings on the substrate, and a light emitting layer disposed between the first conductive layer and the second conductive layer. 
     In an embodiment of the present disclosure, the first conductive layer is transparent and the second conductive layer is reflective. 
     In an embodiment of the present disclosure, the auxiliary conductive portions are disposed over the first conductive layer. 
     In an embodiment of the present disclosure, the auxiliary conductive portions are disposed between the first dielectric layer and the first conductive layer. 
     Another aspect of the present disclosure provides a display device including the array substrate as described above. 
     Another aspect of the present disclosure provides a method for manufacturing an array substrate. The method includes providing a substrate, forming a first dielectric layer on the substrate, forming recesses in the first dielectric layer, and forming a first conductive layer and auxiliary conductive portions. The first conductive layer covers the first dielectric layer, and the auxiliary conductive portions are disposed in the recesses and contact the first conductive layer. 
     In an embodiment of the present disclosure, the auxiliary conductive portions are formed by inkjet printing. 
     In an embodiment of the present disclosure, the first dielectric layer includes a pixel defining layer. The pixel defining layer is formed to have openings for defining pixels and inter-pixel portions disposed between the openings. Forming the recesses includes removing a portion of the inter-pixel portions of the pixel defining layer to form the recesses. 
     In an embodiment of the present disclosure, forming the recesses includes at least one of the following options: 1) removing the portion of the inter-pixel portions in a row direction to form first recesses, 2) removing the portion of the inter-pixel portions in a column direction to form second recesses, and 3) removing the portion of the inter-pixel portions in the row direction to form the first recesses and removing the portion of the inter-pixel portions in the column direction to form the second recesses. 
     In an embodiment of the present disclosure, the method further includes forming a second conductive layer in the openings and on the substrate before forming the first conductive layer, and forming a light emitting layer on the second conductive layer and the inter-pixel portions. 
     In an embodiment of the present disclosure, forming the first conductive layer and the auxiliary conductive portions includes forming the first conductive layer on the first dielectric layer, and forming the auxiliary conductive portions on the first conductive layer in the recesses. 
     In an embodiment of the present disclosure, forming the first conductive layer and the auxiliary conductive portions includes forming the auxiliary conductive portions in the recesses, and forming the first conductive layer to cover the first dielectric layer and the auxiliary conductive portions. 
     Adaptive and further aspects and scope will become apparent from the description provided herein. It should be understood that various aspects of this disclosure may be implemented individually or in combination with one or more other aspects. It should also be understood that the description and specific examples herein are intended for purposes of illustration only and are not intended to limit the scope of the present disclosure. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The drawings described herein are for illustrative purposes only of selected embodiments and not all possible implementations, and are not intended to limit the scope of the present application. 
         FIG. 1  shows a schematic cross-sectional view of an OLED display device; 
         FIG. 2  shows a schematic cross-sectional view of an array substrate in accordance with an embodiment of the present disclosure; 
         FIG. 3  shows a schematic cross-sectional view of an array substrate in accordance with an embodiment of the present disclosure; 
         FIG. 4  shows a schematic planar-structural view of an array substrate in accordance with an embodiment of the present disclosure; 
         FIG. 5  shows another schematic planar-structural view of an array substrate in accordance with an embodiment of the present disclosure; 
         FIG. 6  shows still another schematic planar-structural view of an array substrate in accordance with an embodiment of the present disclosure; 
         FIG. 7  shows a flow chart of a method for manufacturing an array substrate in accordance with an embodiment of the present disclosure; and 
         FIGS. 8-14  show schematic cross-sectional views of a method for manufacturing an array substrate in accordance with an embodiment of the present disclosure. 
     
    
    
     Corresponding reference numerals indicate corresponding parts or features throughout the several views of the drawings. 
     DETAILED DESCRIPTION 
     As used herein and in the appended claims, the singular form of a word includes the plural, and vice versa, unless the context clearly dictates otherwise. Thus, the references “a”, “an”, and “the” are generally inclusive of the plurals of the respective terms. Similarly, the words “comprise”, “comprises”, and “comprising” are to be interpreted inclusively rather than exclusively. Likewise, the terms “include”, “including” and “or” should all be construed to be inclusive, unless such a construction is clearly prohibited from the context. Where used herein the term “examples,” particularly when followed by a listing of terms is merely exemplary and illustrative, and should not be deemed to be exclusive or comprehensive. 
     Additionally, further to be noted, when the elements and the embodiments thereof of the present disclosure are introduced, the articles “a/an”, “one”, “the” and “said” are intended to represent the existence of one or more elements. Unless otherwise specified, “a plurality of” means two or more. The expressions “comprise”, “include”, “contain” and “have” are intended as inclusive and mean that there may be other elements besides those listed. The terms such as “first” and “second” are used herein only for purposes of description and are not intended to indicate or imply relative importance and the order of formation. 
     The flow diagrams depicted herein are just one example. There may be many variations to this diagram or the steps (or operations) described therein without departing from the spirit of the disclosure. For instance, the steps may be performed in a differing order or steps may be added, deleted, or modified. All of these variations are considered a part of the claimed disclosure. 
     Example embodiments will now be described more fully with reference to the accompanying drawings. 
     At present, top-emitting OLED display devices have the advantages of higher aperture ratio and high efficiency. However, in view of optical properties, cathodes in top-emitting OLED display devices typically use a thin metal layer (as shown in  FIG. 1 ), which can result in poor conductivity of the cathodes. Further, when applied to a device of a larger size (for example, a notebook computer of 13 inches or more), the thin cathode layer used in the top-emitting OLED display device significantly affects the IR drop of the display panel, thereby causing poor brightness uniformity of the display panel. 
     Embodiments of the present disclosure provide an array substrate capable of increasing the conductivity of a thin cathode layer and reducing IR drop caused by the thin cathode layer, thereby improving the brightness uniformity of the display panel. 
     In an embodiment of the present disclosure, the array substrate includes a substrate, a first dielectric layer disposed on the substrate, the first dielectric layer having recesses, and a first conductive layer covering (e.g., in a conformal manner) the first dielectric layer, and auxiliary conductive portions disposed in the recesses and contacting the first conductive layer. 
     On one hand, the first conductive layer may cover the first dielectric layer, and the auxiliary conductive portions may be disposed over the first conductive layer in the recesses, as shown in  FIG. 2 . 
       FIG. 2  shows a schematic cross-sectional view of an array substrate in accordance with an embodiment of the present disclosure. As shown in  FIG. 2 , an array substrate  100  includes a substrate  1 , a first dielectric layer  3  disposed on the substrate  1 , wherein the first dielectric layer  3  has recesses  31 , a first conductive layer  5  covering the first dielectric layer  3 , and auxiliary conductive portions  6  disposed on the first conductive layer  5  in the recesses  31 . 
     On the other hand, the auxiliary conductive portions may be disposed in the recesses, and the first conductive layer may cover the first dielectric layer and the auxiliary conductive portions, as shown in  FIG. 3 . 
       FIG. 3  shows a schematic cross-sectional view of an array substrate in accordance with an embodiment of the present disclosure.  FIG. 3  differs from  FIG. 2  only in that the auxiliary conductive portions  6  is disposed in the recesses  31  and is disposed between the first dielectric layer  3  and the first conductive layer  5 . 
     In an exemplary embodiment of the present disclosure, as shown in  FIGS. 2 and 3 , the auxiliary conductive portions  6  non-conformally fill the recesses  31 . 
     In an exemplary embodiment of the present disclosure, a resistivity of the auxiliary conductive portions  6  is smaller than a resistivity of the first conductive layer  5 . In an embodiment of the present disclosure, a combination of the auxiliary conductive portions and the first conductive layer can reduce IR drop. 
     In an exemplary embodiment of the present disclosure, as shown in  FIGS. 2 and 3 , the first dielectric layer  3  may include a pixel defining layer  3 . The pixel defining layer  3  may have openings  32  for defining pixels and inter-pixel portions  33  disposed between the openings  32 . As shown in  FIGS. 2 and 3 , the recesses  31  are disposed in the inter-pixel portions  33  of the pixel defining layer  3 . It should be noted that the recesses  31  are disposed in the inter-pixel portions  33 , which won&#39;t affect the light emitting area of the display device including the array substrate  100 . Further, the auxiliary conductive portions  6  disposed in the recesses  31  won&#39;t affect the illumination of the pixels within the openings  32 . 
     In an exemplary embodiment of the present disclosure, as shown in  FIGS. 2 and 3 , the array substrate  100  further includes a second conductive layer  2  disposed on the substrate  1 , and a light emitting layer  4  disposed between the first conductive layer  5  and the second conductive layer  2 . In an embodiment of the present disclosure, a projection of at least a portion of the second conductive layer  2  on the substrate  1  overlaps with a projection of the openings  32  on the substrate. As an example, the array substrate according to an embodiment of the present disclosure may include a top-emitting OLED display device. It will be appreciated that the combination of the auxiliary conductive portions  6  and the first conductive layer  5  can reduce a resistance of the cathode of the top-emitting OLED display device, thereby increasing the conductivity of the cathode and reducing the IR drop caused by the resistance, and thus improving the brightness uniformity of the display panel. 
     Further, the above light emitting layer  4  is disposed between the first conductive layer  5  and the second conductive layer  2  and covers the pixel defining layer  3 . In an exemplary embodiment of the present disclosure, the first conductive layer  5  may be transparent, and the second conductive layer  2  may be reflective. As an example, the first conductive layer  5  may have a light transmittance of 40% to 50%, which should not be construed as a limit to the disclosure. 
     As an example, the array substrate according to an embodiment of the present disclosure may include a top-emitting OLED display device. For example, the second conductive layer  2  may be an anode of the top-emitting OLED display device. For example, the light emitting layer  4  may be a light emitting layer of the top-emitting OLED display device. For example, the first conductive layer  5  may be a cathode of the top-emitting OLED display device. 
     In an exemplary embodiment of the present disclosure, a material of the first conductive layer  5  may include a metal or a transparent conductive oxide. As an example, the material of the first conductive layer  5  may include magnesium or silver. As an example, the thickness of the first conductive layer  5  may be about 10-20 nm. 
     In an exemplary embodiment of the present disclosure, a material of the auxiliary conductive portions  6  may include a nano-metal material. As an example, the nano-metal material can be, for example, silver. 
       FIG. 4  shows a schematic planar-structural view of an array substrate in accordance with an embodiment of the present disclosure. Referring to  FIGS. 2, 3, and 4 , the recesses  31  in the inter-pixel portions  33  (or the pixel defining layer  3 ) of the array substrate  100  may include first recesses  311  extending in the row direction X. 
       FIG. 5  shows another planar-structural view of an array substrate in accordance with an embodiment of the present disclosure. Referring to  FIGS. 2, 3, and 5 , the recesses  31  in the inter-pixel portions  33  (or the pixel defining layer  3 ) of the array substrate  100  may include second recesses  312  extending in a column direction Y. 
       FIG. 6  shows still another schematic planar-structural view of an array substrate in accordance with an embodiment of the present disclosure. Referring to  FIGS. 2, 3, and 6 , the recesses  31  in the inter-pixel portions  33  (or the pixel defining layer  3 ) of the array substrate  100  may include the first recesses  311  extending in the row direction X and the second recesses  312  extending in the column direction Y. 
     It can be appreciated that those skilled in the art can set the recesses in the row direction and/or the column direction according to actual needs. 
     Embodiments of the present disclosure also provide a display device including the array substrate as described above, which can increase the conductivity of a thin cathode layer and reduce the IR drop caused by the thin cathode layer, thereby improving the brightness uniformity of the display panel. For example, the display device can be an OLED display device. 
     Embodiments of the present disclosure also provide a method for manufacturing an array substrate. 
       FIG. 7  shows a flow chart of a method for manufacturing an array substrate in accordance with an embodiment of the present disclosure. As shown in  FIG. 7 , the method for manufacturing an array substrate includes steps S 701 -S 704 . The manufactured array substrate is shown in  FIGS. 2 and 3 . 
     Next, a method for forming the array substrate as shown in  FIG. 2  will be described with reference to  FIGS. 7 to 12 . 
     As shown in  FIG. 8 , in step S 701 , the substrate  1  is provided. 
     As shown in  FIG. 9 , in step S 702 , a first dielectric layer  3  is formed on the substrate  1 . 
     As shown in  FIG. 10 , in step S 703 , recesses  31  are formed in the first dielectric layer  3 . 
     In an exemplary embodiment of the present disclosure, the first dielectric layer  3  includes a pixel defining layer  3 . The pixel defining layer  3  is formed to have openings  32  for defining pixels and inter-pixel portions  33  disposed between the openings  32 . 
     In an exemplary embodiment of the present disclosure, forming the recesses  31  includes removing a portion of the inter-pixel portions  33  of the pixel defining layer  3  to form the recesses  31 . It should be noted that the recesses  31  are disposed in the inter-pixel portions  33  and won&#39;t affect the light emitting area of the display device including the array substrate  100 . 
     Further, in an exemplary embodiment of the present disclosure, referring to  FIG. 4 , forming the recesses  31  includes removing the portion of the inter-pixel portions  33  in a row direction X to form first recesses  311 . 
     As another example, referring to  FIG. 5 , forming the recesses  31  includes removing the portion of the inter-pixel portions  33  in a column direction Y to form second recesses  312 . 
     As still another example, referring to  FIG. 6 , forming the recesses  31  includes removing the portion of the inter-pixel portions  33  in the row direction X to form the first recesses  311  and removing the portion of the inter-pixel portions  33  in the column direction Y to form the second recesses  312 . 
     It can be understood that a person skilled in the art can form recesses along the row and/or column direction according to actual needs. 
     In step S 704 , a first conductive layer and auxiliary conductive portions are formed. The first conductive layer covers the first dielectric layer, and the auxiliary conductive portions are disposed in the recesses and contact the first conductive layer. 
     Optionally, on one hand, step S 704  may include forming the first conductive layer to cover the first dielectric layer, and forming the auxiliary conductive portions on the first conductive layer in the recesses. In this embodiment, the cross-sectional structure of the formed array substrate is shown in  FIG. 2 . 
     Specifically, as shown in  FIG. 11 , the first conductive layer  5  is formed to cover the first dielectric layer  3 . 
     As shown in  FIG. 12 , the auxiliary conductive portions  6  are formed on the first conductive layer  5  in the recesses  31 . 
     Optionally, on the other hand, step S 704  may include forming auxiliary conductive portions on the first dielectric layer in the recesses, and forming the first conductive layer to cover the first dielectric layer and the auxiliary conductive portions. In this embodiment, the cross-sectional structure of the formed array substrate is as shown in  FIG. 3 . 
     Specifically, as shown in  FIG. 13 , the auxiliary conductive portions  6  are formed on the first dielectric layer  3  in the recesses  31 . 
     As shown in  FIG. 14 , the first conductive layer  5  is formed to cover the first dielectric layer  3  and the auxiliary conductive portions  6 . 
     In an exemplary embodiment of the present disclosure, the auxiliary conductive portions  6  are formed by inkjet printing. It should be noted that since the presence of the recesses  31 , forming the auxiliary conductive portions  6  by the inkjet printing method won&#39;t contaminate the pixels to be formed within the openings  32 , thereby not affecting the light emitting effect of the finally formed display device. 
     In an exemplary embodiment of the present disclosure, the auxiliary conductive portions  6  are formed to non-conformally fill the recesses  31 . 
     In an exemplary embodiment of the present disclosure, a resistivity of the auxiliary conductive portions  6  is smaller than a resistivity of the first conductive layer  5 . In an embodiment of the present disclosure, a combination of the auxiliary conductive portions and the first conductive layer can reduce IR drop. Furthermore, the auxiliary conductive portions  6  disposed within the recesses  31  won&#39;t affect the illumination of the pixels within the openings  32 . 
     In an exemplary embodiment of the present disclosure, referring to  FIG. 2  and  FIG. 3 , prior to forming the first conductive layer  5 , the method for manufacturing the array substrate  100  further includes forming a second conductive layer  2  in the openings  32  and on the substrate  1 , and forming a light emitting layer  4  on the second conductive layer  2  and the inter-pixel portions  33 . 
     In an exemplary embodiment of the present disclosure, the method for forming the first conductive layer, the second conductive layer, and the light emitting layer may include methods commonly used by those skilled in the art, for example, sputtering, chemical vapor deposition, plasma enhanced chemical vapor deposition, and the like. A person skilled in the art may select according to actual needs, which is not specifically limited herein. 
     In addition, other descriptions of the respective components of the embodiment are similar to the above-described embodiments, which will not be described herein again. 
     The foregoing description of the embodiment has been provided for purpose of illustration and description. It is not intended to be exhaustive or to limit the disclosure. Individual elements or features of a particular embodiment are generally not limited to that particular embodiment, but, where applicable, are interchangeable and can be used in a selected embodiment, even if not specifically shown or described. The same may also be varied in many ways. Such variations are not to be regarded as a departure from the disclosure, and all such modifications are included within the scope of the disclosure.