Patent Publication Number: US-11042642-B2

Title: Method and apparatus for data transmission in a TEE system

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is a continuation of and claims the benefit of priority of U.S. patent application Ser. No. 16/785,312, filed Feb. 7, 2020, which is a continuation of PCT Application No. PCT/CN2020/071288, filed Jan. 10, 2020, which claims priority to Chinese Patent Application No. 201910641063.8, filed Jul. 16, 2019, and each application is hereby incorporated by reference in their entirety. 
    
    
     TECHNICAL FIELD 
     Implementations of the present specification related to the field of TEE technologies, and more specifically, to a method and apparatus for data transmission in a TEE system. 
     BACKGROUND 
     A trusted execution environment (TEE) is a secure and trusted zone in a processor, and can guarantee security, confidentiality, and integrity of code and data stored in it. The TEE provides an isolated execution environment. The code and data can run in this trusted zone, and it can be ensured that calculation is not interfered by a conventional operating system during a running process. As such, the confidentiality and integrity of the code and data can be guaranteed. The TEE (EAL2+) provides a higher level of security compared with a conventional operating system, and provides more functions and better performance compared with SE (EAL5). The TEE has multiple implementations, such as Intel SGX, AMD SEV, ARM TrustZone (trusted zone), etc. Because the TEE provides an isolated execution environment, communication between a non-TEE and the TEE is generally called through a special instruction, such as SMC call (TrustZone) or ECall/OCall (SGX). For example, during log printing performed on a TEE side by calling an OCall function, after a CPU is switched from the TEE side to a non-TEE side and context information such as registers are restored, waiting for the log printing to complete on the non-TEE side is generally needed before returning to the TEE side and certain performance losses are caused. 
     Therefore, a more effective solution for data transmission in a TEE system is needed. 
     SUMMARY 
     Implementations of the present specification are intended to provide a more effective solution for data transmission in a TEE system to reduce issues in the existing technology. 
     To achieve the preceding objective, one aspect of the present specification provides a method for data transmission in a TEE system, where the TEE system includes a TEE side and a non-TEE side, the non-TEE side includes a shared memory, the shared memory includes a first address, a second address, and multiple consecutive third addresses, where the first address is used to store a write offset address, the write offset address indicates a writeable start address in the multiple third addresses, the second address is used to store a read offset address, the read offset address indicates a readable start address in the multiple third addresses, the third addresses are used to store data from the TEE side, and the method is executed by a first thread on the TEE side, including: obtaining first data; calling a predetermined function by using the first data as an input parameter, so as to switch to the non-TEE side; obtaining the write offset address by reading the first address; obtaining the read offset address by reading the second address; determining whether a quantity of bytes of the first data is less than or equal to a quantity of writable bytes, where the quantity of writable bytes is determined based on the write offset address and the read offset address, and each address corresponds to one byte; when the quantity of bytes of the first data is less than or equal to the quantity of writable bytes, writing the first data into third addresses starting from the write offset address; updating the write offset address in the first address; and returning to the TEE side. 
     In an implementation, the first data is any one of the following data: logs, monitoring data, and statistical data. 
     In an implementation, the method further includes performing waiting when the quantity of bytes of the first data is greater than the quantity of writable bytes. 
     In an implementation, the shared memory further includes a fourth address used to store a quantity of pieces of discarded data, and the method further includes: when the quantity of bytes of the first data is greater than the quantity of writable bytes, discarding the first data, and incrementing the quantity of pieces of discarded data stored in the fourth address by one. 
     In an implementation, the quantity of pieces of discarded data is an atomic variable. 
     In an implementation, the write offset address is before the read offset address, and the quantity of writeable bytes is equal to a difference obtained by subtracting the write offset address from the read offset address. 
     In an implementation, the write offset address is after the read offset address, and the quantity of writable bytes is equal to a difference obtained by subtracting a quantity of unwritable bytes from a quantity of the third addresses, where the quantity of unwritable bytes is equal to a difference obtained by subtracting the read offset address from the write offset address. 
     In an implementation, the write offset address is the same as the read offset address, and the quantity of writeable bytes is equal to a quantity of all the third addresses. 
     In an implementation, the TEE system is an SGX system, and the predetermined function is an OCall function. 
     Another aspect of the present specification provides an apparatus for data transmission in a TEE system, where the TEE system includes a TEE side and a non-TEE side, the non-TEE side includes a shared memory, the shared memory includes a first address, a second address, and multiple consecutive third addresses, where the first address is used to store a write offset address, the write offset address indicates a writeable start address in the multiple third addresses, the second address is used to store a read offset address, the read offset address indicates a readable start address in the multiple third addresses, the third addresses are used to store data from the TEE side, and the apparatus is deployed in a first thread on the TEE side, including: a first acquisition unit, configured to obtain first data; a call unit, configured to call a predetermined function by using the first data as an input parameter, so as to switch to the non-TEE side; a second acquisition unit, configured to obtain the write offset address by reading the first address; a third acquisition unit, configured to obtain the read offset address by reading the second address; a determining unit, configured to determine whether a quantity of bytes of the first data is less than or equal to a quantity of writable bytes, where the quantity of writable bytes is determined based on the write offset address and the read offset address, and each address corresponds to one byte; a writing unit, configured to, when the quantity of bytes of the first data is less than or equal to the quantity of writable bytes, write the first data into third addresses starting from the write offset address; an update unit, configured to update the write offset address in the first address; and a return unit, configured to return to the TEE side. 
     In an implementation, the apparatus further includes a waiting unit, configured to perform waiting when the quantity of bytes of the first data is greater than the quantity of writable bytes. 
     In an implementation, the shared memory further includes a fourth address used to store a quantity of pieces of discarded data, and the apparatus further includes a discarding unit, configured to, when the quantity of bytes of the first data is greater than the quantity of writable bytes, discard the first data, and increment the quantity of pieces of discarded data stored in the fourth address by one. 
     Another aspect of the present specification provides a computer-readable storage medium, where the computer-readable storage medium stores a computer program, and when the computer program is running on a computer, the computer is enabled to perform the method according to any one of the preceding implementations. 
     Another aspect of the present specification provides a computing device, including a memory and a processor, where the memory stores executable code, and when executing the executable code, the processor implements the method according to any one of the preceding implementations. 
     In the solution for data transmission in a TEE system according to the implementations of the present specification, a high-performance asynchronous data transmission system is provided for a TEE, such as an asynchronous log printing system, to reduce overheads for printing logs of the TEE system and increase an execution speed of the TEE system while satisfying some basic requirements for a log system. 
    
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
       The implementations of the present specification are described with reference to the accompanying drawings so that the implementations of the present specification can be clearer. 
         FIG. 1  is a schematic diagram illustrating a TEE system  100  and a data flow in the TEE system  100 , according to an implementation of the present specification; 
         FIG. 2  is a schematic flowchart illustrating a method for data transmission in a TEE system, according to an implementation of the present specification; 
         FIG. 3  is a schematic diagram illustrating a data structure in a shared memory, according to an implementation of the present specification; 
         FIG. 4  to  FIG. 8  separately show a write offset address and a read offset address in a process of transmitting data by using the shared memory; 
         FIG. 9  shows a data structure in a shared memory, according to another implementation of the present specification; 
         FIG. 10  is a schematic flowchart illustrating a method for data transmission in a TEE system, according to an implementation of the present specification; and 
         FIG. 11  shows an apparatus  1100  for data transmission in a TEE system, according to an implementation of the present specification. 
     
    
    
     DESCRIPTION OF IMPLEMENTATIONS 
     The following describes the implementations of the present specification with reference to the accompanying drawings. 
       FIG. 1  is a schematic diagram illustrating a TEE system  100  and a data flow in the TEE system  100 , according to an implementation of the present specification. As shown in the figure, the system  100  includes a TEE side  11  and a non-TEE side  12 . A dedicated buffer register  121  is preconfigured on the non-TEE side  12  as a shared memory for buffering specific data (such as logs) transmitted from the TEE side. A first thread runs on the TEE side  11 . The first thread can obtain first data (for example, log data). The first thread calls, for example, a printing function (_pringf), to store the first data into the buffer register  121 . For example, if the TEE system is an SGX system, the _pringf function can be switched to a non-TEE side thread by calling an OCall function. On the non-TEE side  12 , the first thread writes logs into the buffer register  121 , and then returns to the TEE side to perform subsequent steps. A second thread runs on the non-TEE side  12 . For example, the second thread reads stored data from the buffer register  121  through polling by periodically calling a pop function, for example, reads second data in one read. After reading the second data, the second thread sends the second data to a specific program (for example, log 4cplus in a log system) on the non-TEE side for data printing. 
     In the schematic diagram above, to ensure data security when the first thread and the second thread access the shared memory at the same time, a specific data structure is designed to allow the preceding process. The following provides a detailed description thereof. 
       FIG. 2  is a schematic flowchart illustrating a method for data transmission in a TEE system, according to an implementation of the present specification. The TEE system includes a TEE side and a non-TEE side, the non-TEE side includes a shared memory, the shared memory includes a first address, a second address, and multiple consecutive third addresses, where the first address is used to store a write offset address, the write offset address indicates a writeable start address in the multiple third addresses, the second address is used to store a read offset address, the read offset address indicates a readable start address in the multiple third addresses, the third addresses are used to store data from the TEE side, and the method is executed by a first thread on the TEE side, including: 
     Step S 202 : Obtain first data. 
     Step S 204 : Call a predetermined function by using the first data as an input parameter, so as to switch to the non-TEE side. 
     Step S 206 : Obtain the write offset address by reading the first address. 
     Step S 208 : Obtain the read offset address by reading the second address. 
     Step S 210 : Determine whether a quantity of bytes of the first data is less than or equal to a quantity of writable bytes, where the quantity of writable bytes is determined based on the write offset address and the read offset address, and each address corresponds to one byte. 
     Step S 212 : When the quantity of bytes of the first data is less than or equal to the quantity of writable bytes, write the first data into third addresses starting from the write offset address. 
     Step S 214 : Update the write offset address in the first address. 
     Step S 216 : Return to the TEE side. 
       FIG. 3  is a schematic diagram illustrating a data structure in the shared memory, according to an implementation of the present specification. As shown in  FIG. 3 , the shared memory includes the first address, the second address, and the multiple consecutive third addresses. The figure schematically shows 10 third addresses, and the 10 consecutive third addresses can be, for example, identified as “1, 2, . . . , 10”. One byte can be written to each address in the memory, where the first address is used to store the write offset address, and the write offset address indicates the writeable start address in the third addresses; the second address is used to store the read offset address, and the read offset address indicates the readable start address in the third addresses; the third addresses are used to store data that needs to be transmitted from the TEE side to the non-TEE side. For example, initially, when data has not been stored from the TEE side into the shared memory, the writable start address in the third addresses is the 1st address, that is, address “1”. Therefore, the write offset address stored in the first address is “1”. In this case, since only a previous address of the write offset address can be read at most during data reading, the read offset address in the second address at this time is also address “1”. The figure schematically shows a third address (namely, address “1”) corresponding to the read offset address (denoted by R) and the write offset address (denoted by W) respectively. Understandably, in the shared memory, the multiple third addresses need to be consecutive, but location relationships between the first address, the second address, and the third address are not limited. For example, the first address and the second address can be located at both ends of the third addresses, or the first address and the second address can be located after the third addresses, and so on. In addition, although  FIG. 3  schematically shows that the shared memory includes 10 consecutive third addresses, in actual applications, a quantity of third addresses included in the shared memory can be determined based on a specific quantity of bytes of data to be transmitted. For example, the data to be transmitted is a log on the TEE side. For example, the log usually contains tens of bytes. Therefore, the shared memory can be set to include hundreds of consecutive third addresses. 
     When the TEE side wants to transmit specific data to the non-TEE side, the TEE side executes the method by running the first thread on the TEE side, so as to write the data to the third addresses of the shared memory. For example, the first thread belongs to a process used for transmitting data from the TEE side to the non-TEE side. After the data is written into the shared memory through the method, the data is transferred to a target program by using another thread on the non-TEE side. Therefore, data transmission in the method is asynchronous, and the method is applicable to data with a low real-time requirement, a large transmission volume, and a high performance requirement. Thus, the specific data is, for example, logs, monitoring data, or statistical data. 
     First, in step S 202 , the first data is obtained. 
     For example, the first data is logs generated by the TEE. For example, after generating the logs, the TEE side stores them in a predetermined memory location on the TEE side. The first thread can be preconfigured to periodically read logs from the predetermined memory location, so that data to be transmitted can be periodically obtained and the method can be periodically executed. 
     In step S 204 , the predetermined function is called by using the first data as an input parameter, so as to switch to the non-TEE side. 
     The TEE system is, for example, an SGX system. In the SGX system, an enclave (enclave) is included as a TEE. In the enclave, the first thread can be switched to a non-enclave side (that is, the non-TEE side) by calling the OCall function. The OCall function is a data transmission method provided in the SGX system. After calling the OCall function, a thread on an enclave side switches a CPU to the non-enclave side. Specifically, after the OCall function is called by using the first data as an input parameter, an enclave-side register is backed up on the enclave side, and the first data is transmitted to the non-TEE side by using the first data as an input parameter. Then, non-enclave-side register information is restored on the non-enclave side, including storing the first data into a register as an input parameter. After the first thread is switched to the non-TEE side, a subsequent step can be performed by calling another function. 
     In step S 206 , the write offset address is obtained by reading the first address. In step S 208 , the read offset address is obtained by reading the second address. 
     Besides the preceding case that the write offset address and the read offset address shown in  FIG. 3  each indicate address “1” in the third addresses,  FIG. 4  to  FIG. 8  separately show a write offset address and a read offset address in a process of transmitting data by using the shared memory. In  FIG. 4  to  FIG. 8 , each block corresponds to one address. Data inside the block is one byte. A number below the block is its address identifier. As described above, “R” and “W” correspond to the read offset address and the write offset address, respectively. 
     In  FIG. 4 , four bytes “ab\n\0” have been sequentially written into third addresses starting from address 1 by using the method, and data has not been read from the shared memory on the non-TEE side. In this case, the write offset address (W) stored in the first address points to an address (namely, address 5) after the address storing “\0”, and the read offset address (R) stored in the second address still points to address 1. 
     In  FIG. 5 , four bytes “cd\n\0” have been written sequentially into third addresses starting from address 5 by using the method again, and data still has not been read from the shared memory on the non-TEE side. In this case, the write offset address (W) points to an address (namely, address 9) after an address storing the second “\0”, and the read offset address (R) still points to address 1. 
     In  FIG. 6 , data has been read starting from the read offset address on the non-TEE side by using a method described below. The data can be read from a previous address of the write offset address at most, that is, the written eight bytes “ab\n\0cd\n\0” in the shared memory are read in the reading process. In this case, the write offset address stored in the first address still points to address 9, and the read offset address stored in the second address points to an address (namely, address 9) after an address storing the second “\0”. 
     In  FIG. 7 , four bytes “ef\n\0” have further been sequentially written into third addresses starting from address 9 by using the method shown in  FIG. 2 . In this case, the read offset address is unchanged and is still address 9. In the data writing process, after all of the 10 addresses are written, each address from address 1 to the previous address (namely, address 8) of the read offset address (address 9 in this case) is writable because data in addresses before the read offset address has been read. Therefore, further writing jumps from address 10 to address 1, and after the writing is complete, the write offset address points to address 3. 
     In  FIG. 8 , data has been read again from the shared memory on the non-TEE side. Specifically, data is read starting from the read offset address (address 9) to a previous address (address 2) of the write offset address. After the read, the write offset address in the first address still points to address 3, and the read offset address in the second address also points to address 3. 
     In step S 210 , it is determined whether the quantity of bytes of the first data is less than or equal to the quantity of writable bytes, where the quantity of writable bytes is determined based on the write offset address and the read offset address, and each address corresponds to one byte. 
     A person skilled in the art can easily determine a writable address in the multiple third addresses based on the write offset address and the read offset address. Since one address corresponds to one byte, the quantity of writable bytes can be determined. 
     For example, in the cases shown in  FIG. 3 ,  FIG. 6 , and  FIG. 8 , if the read offset address and the write offset address point to the same address, the quantity of writeable bytes is a quantity of all the third addresses, that is, 10. 
     In the cases shown in  FIG. 4  and  FIG. 5 , the write offset address is after the read offset address. Therefore, the quantity of writable bytes is obtained by subtracting a quantity of unwritable bytes from the quantity of third addresses, where the quantity of unwritable bytes is a difference obtained by subtracting the read offset address from the write offset address. For example, in  FIG. 4 , the write offset address is 5 and the read offset address is 1. Therefore, the quantity of unwritable bytes is 5−1=4, and the quantity of writable bytes is 10−4=6, which corresponds to a total of six addresses from address 5 to address 10. 
     In the case shown in  FIG. 7 , the write offset address is before the read offset address. In this case, the quantity of writable bytes is a difference obtained by subtracting the write offset address from read offset address. For example, in  FIG. 7 , the write offset address is 3 and the read offset address is 9. Therefore, the quantity of writable bytes is 9−3=6, which corresponds to a total of six addresses from address 3 to address 8. 
     In step S 212 , when the quantity of bytes of the first data is less than or equal to the quantity of writable bytes, the first data is written into the third addresses starting from the write offset address. 
     For example, when data stored in the shared memory is shown in  FIG. 4 , the quantity of writable bytes is 6, as described above. When the first data to be written is four bytes “ef\n\0”, since 4&lt;6, the four bytes “ef\n\0” can be written into four addresses 5, 6, 7, and 8. 
     When data stored in the shared memory is shown in  FIG. 7 , the quantity of writable bytes is 6, as described above. When the first data to be written is eight bytes “ghijkl\n\0”, the quantity of bytes of the first data is greater than the quantity of writable bytes, and therefore the data cannot be written into the shared memory. In this case, the writing thread can wait until the quantity of writable bytes in the shared memory is sufficient, or can discard the first data and return.  FIG. 9  shows a data structure in a shared memory, according to another implementation of the present specification. In this data structure, a fourth address is included in addition to the first address, the second address, and the third addresses shown in  FIG. 3 . The fourth address stores a quantity of pieces of discarded data. After the first data is discarded as described above, the quantity of pieces of discarded data in the fourth address is incremented by 1. In an implementation, the quantity of pieces of discarded data is an atomic variable, so that data security can be ensured when dual threads simultaneously operate on the TEE side and the non-TEE side. 
     In step S 214 , the write offset address in the first address is updated. 
     For example, after “ab\n\0” is written into the third addresses in  FIG. 3 , the initial write offset address “1” is updated to a write offset address “5”, to facilitate reading of the write offset address during the next write or read. For example, during writing into the third addresses shown in  FIG. 4 , the latest write offset address “5” can be read, so as to calculate the quantity of writeable bytes. 
     In step S 216 , the first thread returns to the TEE side. 
     The first thread can be preconfigured to return to the TEE side after step S 214  is completed. Therefore, the first thread automatically returns to the TEE side after step S 214  is performed, so as to perform subsequent steps on the TEE side, for example, repeating the method again. 
       FIG. 10  is a schematic flowchart illustrating a method for data transmission in a TEE system, according to an implementation of the present specification. The TEE system includes a TEE side and a non-TEE side, the non-TEE side includes a shared memory, the shared memory includes a first address, a second address, and multiple consecutive third addresses, where the first address is used to store a write offset address, the write offset address indicates a writeable start address in the multiple third addresses, the second address is used to store a read offset address, the read offset address indicates a readable start address in the multiple third addresses, the third addresses are used to store data from the TEE side, and the method is executed by the non-TEE side, including: 
     Step S 1002 : Obtain the write offset address by reading the first address. 
     Step S 1004 : Obtain the read offset address by reading the second address. 
     Step S 1006 : Read unread bytes in written data in the third addresses as second data, where the unread bytes are determined based on the write offset address and the read offset address, and each address corresponds to one byte. 
     Step S 1008 : Update the read offset address in the second address. 
     The method can be executed by a second thread on the non-TEE side, and the second thread can also belong to the preceding process used for transmitting data from the TEE side to the non-TEE side. 
     For step S 1002  and step S 1004 , reference can be made to the descriptions of step S 206  and step S 208 , and details are omitted here for simplicity. 
     In step S 1006 , the unread bytes in the written data in the third addresses are read as the second data, where the unread bytes are determined based on the write offset address and the read offset address, and each address corresponds to one byte. 
     A person skilled in the art can easily determine the unread bytes in the third addresses based on the write offset address and the read offset address. 
     For example, in the cases shown in  FIG. 3 ,  FIG. 6 , and  FIG. 8 , if the read offset address and the write offset address point to the same address, the third addresses do not include any unread byte. 
     In the cases shown in  FIG. 4  and  FIG. 5 , the write offset address is after the read offset address, and all unread bytes in the third addresses include bytes in the read offset address to a previous address of the write offset address. For example, in  FIG. 4 , the write offset address is 5 and the read offset address is 1. Therefore, all the unread bytes are bytes in addresses 1 to 4. 
     In the case shown in  FIG. 7 , the write offset address is before the read offset address. In this case, all the unread bytes are bytes in the third addresses other than read bytes, and the read bytes include bytes in the write offset address to a previous address of the read offset address. For example, in  FIG. 7 , the write offset address is 3 and the read offset address is 9. Therefore, the read bytes are bytes in all of addresses 3 to 8, and all the unread bytes are bytes in addresses 1, 2, 9, and 10. Understandably, in the present step, not all unread bytes in the third addresses are read, and it is possible that only some of the unread bytes are read. For example, the following can be preconfigured: Only 3 bytes are read at a time. Therefore, the first three bytes of all unread bytes can be read in one read, and remaining one unread byte can be read in the next read. 
     In step S 1008 , the read offset address in the second address is updated. 
     For example, after eight bytes “ab\n\0cd\n\0” are read from the third addresses shown in  FIG. 5 , the read offset address is updated from “1” to “9”, to facilitate reading of the read offset address during the next write or read. 
     In an implementation, the second data is log data, and the method further includes: after updating the read offset address in the second address, sending the second data to a log printing program on the non-TEE side for printing the second data. For example, the printing includes displaying on a display or storing into a hard disk, etc. 
       FIG. 11  shows an apparatus  1100  for data transmission in a TEE system, according to an implementation of the present specification. The TEE system includes a TEE side and a non-TEE side, the non-TEE side includes a shared memory, the shared memory includes a first address, a second address, and multiple consecutive third addresses, where the first address is used to store a write offset address, the write offset address indicates a writeable start address in the multiple third addresses, the second address is used to store a read offset address, the read offset address indicates a readable start address in the multiple third addresses, the third addresses are used to store data from the TEE side, and the apparatus is deployed in a first thread on the TEE side, including: a first acquisition unit  1101 , configured to obtain first data; a call unit  1102 , configured to call a predetermined function by using the first data as an input parameter, so as to switch to the non-TEE side; a second acquisition unit  1103 , configured to obtain the write offset address by reading the first address; a third acquisition unit  1104 , configured to obtain the read offset address by reading the second address; a determining unit  1105 , configured to determine whether a quantity of bytes of the first data is less than or equal to a quantity of writable bytes, where the quantity of writable bytes is determined based on the write offset address and the read offset address, and each address corresponds to one byte; a writing unit  1106 , configured to, when the quantity of bytes of the first data is less than or equal to the quantity of writable bytes, write the first data into third addresses starting from the write offset address; an update unit  1107 , configured to update the write offset address in the first address; and a return unit  1108 , configured to return to the TEE side. 
     In an implementation, the apparatus further includes a waiting unit  1109 , configured to perform waiting when the quantity of bytes of the first data is greater than the quantity of writable bytes. 
     In an implementation, the shared memory further includes a fourth address used to store a quantity of pieces of discarded data, and the apparatus further includes a discarding unit  1110 , configured to, when the quantity of bytes of the first data is greater than the quantity of writable bytes, discard the first data, and increment the quantity of pieces of discarded data stored in the fourth address by one. 
     Another aspect of the present specification provides a computer-readable storage medium, where the computer-readable storage medium stores a computer program, and when the computer program is running on a computer, the computer is enabled to perform the method according to any one of the preceding implementations. 
     Another aspect of the present specification provides a computing device, including a memory and a processor, where the memory stores executable code, and when executing the executable code, the processor implements the method according to any one of the preceding implementations. 
     In the implementations of the present specification, because the shared memory is used simultaneously by the TEE and the non-TEE, no lock can be used to ensure thread security due to special nature of the TEE. Therefore, in the present solution, thread security is ensured by using a lock-free data structure and a special design. Specifically, the shared memory includes the first address to the fourth address. For the first address and the second address, when data is written on one side, data is only read on the other side. Therefore, the two sides do not simultaneously write data. In addition, when data is read on one side and written on the other side, because the write offset address is updated after the write is completed, and the read offset address is updated after the read is completed, the offset addresses are not updated before data processing is completed. Therefore, data that has not been fully written is not read, and the written data does not overwrite unread data. Although the data stored in the third addresses can be read and written simultaneously on both sides, read and write ranges are controlled by the write offset address and the read offset address. Therefore, the read and write ranges are actually separate zones and do not interfere with each other. In addition, although the quantity of pieces of discarded data in the fourth address can also be read and written at the same time, data security is ensured by setting the quantity of pieces of discarded data as an atomic variable. 
     Through the design of the preceding lock-free data structure, a high-performance asynchronous data transmission system is provided for the TEE, such as an asynchronous log printing system, to reduce overheads for printing logs of the TEE system and increase an execution speed of the TEE system while satisfying some basic requirements for a log system. 
     It should be understood that the descriptions such as “first” and “second” in some implementations of the present specification are only used to distinguish between similar concepts for simplicity of description, and have no other limiting effects. 
     Some implementations of the present specification are described in a progressive way. For same or similar parts of the implementations, references can be made to the implementations mutually. Each implementation focuses on a difference from other implementations. Particularly, a system implementation is similar to a method implementation, and therefore is described briefly. For related parts, references can be made to related descriptions in the method implementation. 
     Specific implementations of the present specification are described above. Other implementations fall within the scope of the appended claims. In some situations, the actions or steps described in the claims can be performed in an order different from the order in the implementations and the desired results can still be achieved. In addition, the process depicted in the accompanying drawings does not necessarily need a particular execution order to achieve the desired results. In some implementations, multi-tasking and concurrent processing is feasible or can be advantageous. 
     A person of ordinary skill in the art can be further aware that, in combination with the examples described in the implementations of the present specification, units and algorithm steps can be implemented by electronic hardware, computer software, or a combination thereof. To clearly describe interchangeability between the hardware and the software, compositions and steps of each example are generally described above based on functions. Whether the functions are performed by hardware or software depends on particular applications and design constraint conditions of the technical solutions. A person of ordinary skill in the art can use different methods to implement the described functions for each particular application, but it should not be considered that the implementation goes beyond the scope of the present application. 
     Steps of methods or algorithms described in the implementations of the present specification can be implemented by hardware, a software module executed by a processor, or a combination thereof. The software module can reside in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. 
     In the described specific implementations, the objective, technical solutions, and benefits of the present specification are further described in detail. It should be understood that the descriptions are merely specific implementations of the present specification, but are not intended to limit the protection scope of the present specification. Any modification, equivalent replacement, or improvement made without departing from the spirit and principle of the present specification should fall within the protection scope of the present specification.