Patent Publication Number: US-11658666-B1

Title: Fractional-N ADPLL with reference dithering

Description:
BACKGROUND 
     A phase locked loop (PLL) generates an output signal with a defined phase relationship to an input reference signal. The output signal is matched to the phase of the input reference signal by a feedback loop in which the phase difference between the input reference signal and the output signal is determined by a phase detector. In a digital phase locked loop, the phase detector outputs a digital signal. The output from the phase detector (indicating phase error) is received by a loop filter. The loop filter in turn provides an output signal to a frequency-controlled oscillator. In an all-digital phase locked loop (ADPLL), the phase detector outputs a digital signal, the loop filter is a digital loop filter, and the frequency-controlled oscillator is a digitally controlled oscillator. 
     An integer ADPLL includes a reference phase generator configured to integrate an input frequency control word (FCW), a phase detector, a loop filter, a digitally controlled oscillator (DCO), and a feedback path including a counter and a time-to-digital converter (TDC). The FCW of an integer ADPLL is a constant integer value that describes the ratio between the DCO frequency and a reference frequency. The DCO frequency can only be an integer multiple of the reference frequency in an integer ADPLL. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The present disclosure may be better understood, and its numerous features and advantages made apparent to those skilled in the art by referencing the accompanying drawings. The use of the same reference symbols in different drawings indicates similar or identical items. 
         FIG.  1    is a block diagram of a system including a fractional-N ADPLL with single delay line reference dithering in accordance with some embodiments. 
         FIG.  2    is a graph of a probability distribution of a uniformly distributed random number in accordance with some embodiments. 
         FIG.  3    is a graph of a probability distribution of a uniformly distributed random number after high pass filtering with a first order high pass filter in accordance with some embodiments. 
         FIG.  4    is a block diagram of a system including a fractional-N ADPLL having a frequency reference dithered by a variable delay line in accordance with some embodiments. 
         FIG.  5    is a diagram of a variable delay line in accordance with some embodiments. 
         FIG.  6    is a diagram of a delay line with constant delays in accordance with some embodiments. 
         FIG.  7    is a block diagram of a fractional-N ADPLL having a frequency reference dithered by a delay line with digital control and a dynamic matching element in accordance with some embodiments. 
         FIG.  8    is a block diagram of a delay line divided into a coarse resolution delay line and a fine resolution delay line in accordance with some embodiments. 
         FIG.  9    is a graph illustrating noise in a fractional-N ADPLL without dithering by a delay line. 
         FIG.  10    is a graph illustrating noise reduction in a fractional-N ADPLL having a frequency reference dithered by a delay line in accordance with some embodiments. 
         FIG.  11    is a flow diagram of a method of dithering a phase of a reference clock signal at an input of a fractional-n ADPLL with a dithering signal having a triangular distribution in accordance with some embodiments. 
     
    
    
     DETAILED DESCRIPTION 
     By dithering the FCW, an integer ADPLL can function as a fractional-N ADPLL. For example, addition of a delta-sigma modulator can produce a fractional-N frequency resolution in the parts per million (ppm) range. However, dithering the FCW with a delta-sigma modulator generates an offset to an integer frequency which causes the phase to move over the entire phase range. By moving over the phase range, quantization effects cause a regular pattern that leads to spurious tones (also referred to as spurs) in the feedback path. Furthermore, the shaped noise with contributions mainly at high frequencies generated by the delta-sigma modulator can negatively impact the ADPLL performance. Phase locked loops are often required to achieve a specific noise performance and the maximum allowable phase noise may be determined by an intended application for a phase locked loop. Depending on the application of the phase locked loop, spurious tones can lead to serious performance degradation of an entire system. For example, if the phase locked loop is used as a local oscillator in a transceiver, spurious tones lead to unwanted mixing of side channels and result in a reduced signal to noise ratio. If the phase locked loop is used as a clock source of a digital circuit, spurious tones lead to additional clock uncertainty and can cause timing violations. If the phase locked loop is used in high-speed interfaces, spurious tones degrade the jitter performance and can lead to an increased bit error rate. Fractional-N ADPLLs and fractional-N PLLs in general are particularly prone to exhibiting spurs in their output spectrum when the ratio of output to input frequency is close to an integer value, severely limiting their application in such cases. 
       FIGS.  1 - 9    illustrate techniques for reducing spurious tones introduced by delta sigma modulation of the FCW to implement a fractional-N ADPLL. By adding a randomly modulated delay having a triangular distribution to a frequency reference at an input of the fractional-n ADPLL, spurious tones are reduced for multiple TDC resolutions without requiring active control or calibration. In some embodiments, the randomly modulated delay is added via a delay line. The delay line is analog in some embodiments and digital in other embodiments and is controlled by a digital signal. The range of the randomly modulated delay spans at least q to −q, where q is the quantization step (sometimes referred to as the “quantization step size”) of the TDC. 
     In some embodiments, the delay line generates the randomly modulated delay based on a uniformly distributed random number with a flat spectrum that is shaped by a high pass filter. The high pass filtering is performed by a first order high pass filter that differentiates the uniformly distributed random number in some embodiments. After differentiation, the random number follows a triangular distribution which still covers the range of at least spans at least q to −q, where q is the quantization step of the TDC. Due to high-pass filtering, low frequency components of the noise added by the delay line are rejected. In addition, the PLL acts as a low-pass filter that rejects most of the high-pass shaped dither signal added by the delay line. As a result, the dither signal does not add significant noise to the PLL&#39;s output spectrum. 
     In some embodiments in which the delay line is implemented in an analog manner, the delay line includes a number of unit delay cells and a delay line controller varies either the delay of each unit delay cell or the number of unit delay cells that the dither signal traverses. In some embodiments in which the delay line implements digital control, the delay line includes dynamic element matching to increase linearity. To facilitate both expanded range and resolution of the randomly modulated delay, in some embodiments the delay line is split into a fine delay line and a coarse delay line with differing unit delays. 
       FIG.  1    illustrates a system  100  including an example fractional-N ADPLL  150  with single delay line reference dithering in accordance with some embodiments. The fractional-N ADPLL  150  receives a system clock signal CKR  128 . Based on the system clock signal CKR  128 , the system  100  produces an output signal CLK_OUT  136 . The output signal CLK_OUT  136  includes an output frequency labeled and an output phase. Upon receiving a new system clock signal CKR  128  having one or more of a new frequency reference and a new phase reference, the fractional-N ADPLL  150  first tunes to, and locks to, a new output signal CLK_OUT  136  having a new output frequency and a new output phase. The system  100  includes a fractional-N ADPLL  150  and a variable delay line  122 , a high pass filter  124 , and a random number source  126 . The fractional-N ADPLL  150  includes a reference phase generator  110 , a phase detector  112 , a loop filter  114 , a digitally controlled oscillator (DCO)  116 , a counter  118 , and a time-to-digital converter (TDC)  120 . Components in the fractional-N ADPLL  150  that are analog are illustrated with shading. Other components in the fractional-N ADPLL  150  are digital and are illustrated without shading. 
     The reference phase generator  110  includes an adder  106  and a register  108  arranged to integrate an input integer frequency control word signal having FCW.i  132  and FCW.f  134  which are dithered by a delta-sigma modulator  104  with a fractional frequency control word signal. Both are added at  102 . The system clock signal CKR  128  is derived from a reference signal FREF  130  by sampling the reference signal FREF  130  with the DCO  116  clock, and provides an output signal with a stable frequency that is used to clock the register  108  of the reference phase generator  110 . The reference phase generator  110  is configured to convert the FCW.i  132  and FCW.f  134  from the frequency domain to the phase domain and provide a reference phase ramp PHI_REF The phase detector  112  compares the reference phase ramp PHI_REF with a feedback ramp PHV derived from the output of the DCO  116 , and outputs a phase error signal PHE. The feedback ramp PHV is determined by combining (e.g., by fixed point concatenation) the output from the counter  118  and the TDC  120 . 
     The loop filter  114  is controlled by an ADPLL control block (not shown) and receives the phase error signal PHE and performs a filtering operation. The loop filter  114  provides three output signals for controlling the DCO  116 : a process voltage temperature control signal PVT, an acquisition control signal ACQ, and a tracking signal TR. Each of these control signals controls a switched capacitor bank of the DCO  116  to vary the output frequency of the DCO  116 , which is an integer multiple of the reference frequency FREF  130  when the fractional-N ADPLL  150  is operated in integer mode and the loop is settled. Other frequency control mechanisms, such as digital to analog converters with varactors, or a current-controller oscillator controlled by a current digital-to-analog converter (DAC), are used in alternative arrangements. 
     The output from the DCO  116  is received as an input signal at the TDC  120 . The TDC  120  measures and quantizes the timing difference between transitions of the output signal from the system clock signal CKR  128  and the transitions in the output from the DCO  116 . The TDC  120  produces a TDC output labeled PHV_F. The counter  118  accumulates a count of the transitions in the output from the DCO  116  and produces an output labeled as PHV_I. The combination of the signals from the TDC  120  and the counter  118  results in an input PHV to the phase detector  112 . The phase detector  112  sums a signal from the reference phase generator  110  and a negative value of a phase based on the TDC  120  output PHV_F and the counter  118  output PHV_I to produce a phase difference signal labeled PHE which serves as an input to the loop filter  114 . 
     To facilitate the reduction of spurious tones that can be caused by regular quantization patterns in the feedback path from dithering of the fractional frequency control word FCW.f  134  by the delta-sigma modulator  104  and adding it to the integer frequency control word FCW_i  132 , the system  100  introduces a randomly modulated delay  140  (also referred to as a dithering signal) with controlled properties to dither the phase of the reference frequency  130  at the input to the fractional-N ADPLL  150 . For example, if the reference frequency FREF  130  is 40 megahertz and the ratio of the output frequency CLK_OUT  136  to the input frequency is 60.0001, an offset of 4 kilohertz will appear as a spur in the output frequency CLK-OUT  136  signal and additional spurs will occur at multiples of the calculated offset frequency. To reduce such spurs, the system  100  dithers the phase error by adding noise in the form of a randomly modulated delay  140  (also referred to as a dithering signal) to the feedback signal (also referred to as a frequency reference or reference clock signal) of the fractional-N ADPLL  150 . The randomly modulated delay  140  is added via a variable delay line  122  that receives a uniformly distributed random number  138  generated by a random number source  126  such as a linear feedback shift register (LFSR) that is shaped by a high pass filter  124 . In some embodiments, the variable delay line  122  is implemented in the analog domain and in other embodiments the variable delay line  122  is implemented in the digital domain. 
     After filtering by the high pass filter  124 , the random number has a triangular distribution and is used as a delay control  142  for the variable delay line  122 . The amplitude of the randomly modulated delay  140  is large enough to cover more than the least significant bits (LSB) of the feedback path. In some embodiments, the dither range is selected to be larger because spur suppression is relatively insensitive to large dither ranges and smaller dither ranges lead to less effective spur suppression. In some embodiments, the variable delay line  122  is divided into a coarse resolution portion (not shown) and a fine resolution portion (not shown) to enable a high dithering signal amplitude with high timing resolution. In addition, in some embodiments the dithering signal  140  is noise shaped to prevent impact to inband phase noise of the fractional-N ADPLL  150 . 
       FIG.  2    is a graph  200  of a probability distribution of a uniformly distributed random number generated by the random number source  126  in accordance with some embodiments. The value range of the uniformly distributed random number is normalized to have a value range from −1 to 1. Because the random number is uniformly distributed, the probability P of the random number having any value within the range of −1 to 1 is the same, giving the probability distribution a flat shape or spectrum. 
       FIG.  3    is a graph  300  of a probability distribution of the uniformly distributed random number after high pass filtering with a first order high pass filter such as high pass filter  124  in accordance with some embodiments. The high pass filter  124  differentiates the uniformly distributed random number such that the graph  300  of the probability distribution of the differences between the normalized values of the uniformly distributed random number follows a triangular distribution. The range of the triangular distribution covers at least spans at least q to −q, where q is the quantization step of the TDC  120 . In the illustrated example, the minimum and maximum differences between normalized values of the uniformly distributed random number range from −2 to 2. The probability P of the difference between normalized values of the uniformly distributed random number being zero is high, whereas the probability P of the differences between normalized values of the uniformly distributed random number having a value within the range of −2 to 2 diminishes linearly as the differences approach the extents of the range. 
     Due to high pass filtering by the high pass filter  124 , low frequency components of the noise are rejected. Further, because the phase locked loop acts as a low-pass filter, most of the high-pass shaped dither signal is rejected such that the dither signal does not add significant noise to the output spectrum of the fractional-N ADPLL  150 . The order of the low pass loop filter  114  is selected such that the noise introduced by the delta-sigma modulator  104  is cancelled and contributes only −20 dB/decade to the overall noise characteristics of the fractional-N ADPLL  150 . In some embodiments, the delta-sigma modulator  104  is implemented as a multi-stage noise shaping (MASH 1-1-1) structure with a noise shaping characteristic of +60 dB/decade and the loop filter  114  is implemented as at least a third order filter. In other embodiments, other implementations of the delta-sigma modulator  104  are used, and characteristics of the loop filter  114  are selected to reject delta-sigma quantization noise from the output. 
       FIG.  4    is a block diagram  400  of the fractional-N ADPLL  150  having the reference frequency  130  dithered by the variable delay line  122  in accordance with some embodiments. The random number  138  generated by the random number source  126  is filtered by the high pass filter  124  to produce noise  402  having a triangular distribution. The noise  402  is added to the reference frequency  130  at the variable delay line  122  to produce the randomly modulated delay  140  that is input to the fractional-N ADPLL  150 . The resulting randomly modulated delay  140  produces a triangularly distributed and noise shaped non-subtractive reference dither that reduces fractional-N spurs in the fractional-N ADPLL  150  without adversely affecting the overall phase noise. The randomly modulated delay  140  in conjunction with the higher order loop filter  114  cancels the delta-sigma quantization noise without requiring active control or calibration. 
       FIG.  5    is a diagram of a variable delay line  500  in accordance with some embodiments. In some embodiments in which the variable delay line  500  is implemented in an analog manner, the variable delay line includes a plurality of unit delay cells  502 ,  504 . In other embodiments, the analog variable delay line  500  is implemented using non-unit weighted delays (not shown). The variable delay line  500  varies either the delay of each unit delay cell  502 ,  504 , or the number of cells that a signal that is to be delayed traverses. In some embodiments, the variable delay line  500  varies the delay of a logic gate by limiting the supply current  510  and increasing the load capacitance  508  at the output of the unit delay cell  502 ,  504 . Varying the delay of the logic gate is achieved in either the analog domain or the digital domain. For example, to increase the load, a varactor can be used for analog control, while switched capacitances can be used to provide digital control. As another example, varying the supply current is performed in some embodiments via voltage-controlled current sources to provide analog control, while switching the amount of fixed current source provides digital control. In the illustrated example, latches are used as non-inverting buffers, the delays of which are modulated by switching capacitive loads using CMOS transmission gates. 
       FIG.  6    is a diagram of a delay line  600  with unit delay cells  602 ,  604  applying constant delays in accordance with some embodiments. In the illustrated example, the delays of the unit delay cells  602 ,  604  are not varied. Instead, the number of elements the reference traverses is varied by tapping the delay line at different points. 
       FIG.  7    is a block diagram of a system  700  including the fractional-N ADPLL  150  having a frequency reference dithered by the variable delay line  122  with digital control and a dynamic element matching module  702  in accordance with some embodiments. To generate the control signal for the variable delay line  122  with analog control, in some embodiments thermal noise serves as a uniform random source and the triangularly distributed random signal, such as noise  402  in  FIG.  4   , is generated by high-pass filtering the output from the uniform random source. 
     To generate a digital control signal, in some embodiments the system  700  includes a linear-feedback shift register (LFSR)  704  as a uniform pseudo-random source and a simple finite impulse response high-pass filter  706  with a z-domain transfer function 1−z −1  to generate the triangularly distributed random signal. The LFSR  704  produces a statistically even predictable stream of bits having approximately the same number of zeros as ones on average. In the illustrated example, the system  700  includes the dynamic element matching module  702  to increase linearity when using a digitally controlled variable delay line  122 . In some embodiments, the dynamic element matching module  702  includes one or more dynamic element matching circuits. Mismatches among nominally identical circuit elements cause non-linear distortion that appears as spurs caused by the delay line. The spurs become visible in the output clock and can therefore be measured in the phase error signal. By randomizing the mismatches, the dynamic element matching module  702  causes the error resulting from the mismatches to be pseudo-random noise that eliminates the spurs from the delay line. 
     In some embodiments that implement the variable delay line  122  with digital control, the system  700  monitors the timing relationship between the control signal and the reference propagating through the variable delay line  122 . The system  700  ensures that the control signals do not change while a reference clock edge propagates through the variable delay line  122 . In some embodiments, the system  700  clocks the control signal generation circuitry with the output of the variable delay line  122 . 
       FIG.  8    is a block diagram of a delay line  800  divided into a coarse resolution variable delay line  818  and a fine resolution variable delay line  808  in accordance with some embodiments. Splitting the delay line  800  into the coarse resolution variable delay line  818  and the fine resolution variable delay line  808  enables a large dithering amplitude with high timing resolution. The coarse resolution variable delay line  818  receives a random number  814  generated by a random number source  812  that is filtered by a high pass filter  816 , while the fine resolution variable delay line  808  receives a random number  804  generated by a random number source  802  that is filtered by a high pass filter  806 . In the illustrated example, the fine resolution variable delay line  808  is controlled independently of the coarse resolution variable delay line  818 . In some embodiments, the fine resolution variable delay line  808  introduces a variable delay on the order of 100 femtoseconds, while the coarse resolution variable delay line  818  introduces a variable delay on the order of 10 picoseconds. Whereas a single variable delay line such as that illustrated in  FIG.  1    includes on the order of 1000 stages in some embodiments, a divided variable delay line such as that illustrated in  FIG.  8    includes on the order of 20 stages for each of the coarse resolution variable delay line  818  and the fine resolution variable delay line  808  in some embodiments while achieving similar suppression of tones in the quantization noise. 
       FIG.  9    is a graph  900  illustrating noise in a fractional-N ADPLL without dithering by a delay line. The graph  900  depicts the output noise spectrum of an example fractional-N ADPLL with a ratio of output to input frequency of 66.0001 without dither enabled. The spectrum contains large spurs, for example, at 10 kilohertz, which limit the usage of the fractional-N ADPLL. 
       FIG.  10    is a graph  1000  illustrating noise reduction in a fractional-N ADPLL having a frequency reference dithered by a delay line in accordance with some embodiments. The graph  900  depicts the output noise spectrum of an example fractional-N ADPLL with a ratio of output to input frequency of 66.0001 with dither enabled. The spectrum is free of any visible spurs. 
       FIG.  11    is a flow diagram of a method  1100  of dithering a phase of a reference clock signal at an input of a fractional-n ADPLL with a dithering signal having a triangular distribution in accordance with some embodiments. The method  1100  is described with respect to an example implementation of the system  100  of  FIG.  1   . The system  100  includes the fractional-N ADPLL  150  in which the frequency control word is modulated by the delta-sigma modulator  104 , which introduces spurious tones due to regular quantization patterns in the feedback path. At block  1102 , the random number source  126  generates a uniformly distributed random number  138  having a flat spectrum. In some embodiments, the random number source  126  is implemented as the LFSR  704 . 
     At block  1104 , the high pass filter  124  high-pass filters the uniformly distributed random number  138  to produce a random number having a triangular distribution to use as the delay control  142  input to the variable delay line  122 . In some embodiments, the high pass filter  124  is a first order high pass filter that differentiates the uniformly distributed random number  138  such that the probability distribution of the differences between the normalized values of the uniformly distributed random number follows a triangular distribution. At block  1106 , the triangularly distributed random number is input to the variable delay line  122 . 
     At block  1108 , the variable delay line  122  generates a randomly modulated delay  140  having a triangular distribution. In some embodiments, the variable delay line  122  is controlled by a digital signal and is implemented in either the analog domain or the digital domain. In some embodiments in which the variable delay line  122  is implemented in the analog domain, the variable delay line  122  includes a plurality of unit delay cells  502 ,  504  and varies either the delay of each unit delay cell  502 ,  504  or the number of unit delay cells  502 ,  504  that the signal that is to be delayed traverses. In some embodiments in which the variable delay line  122  is implemented in the digital domain, a dynamic element matching module  702  is included to randomize mismatch to eliminate spurs from the variable delay line  122 . Further, in some embodiments the variable delay line  122  is implemented as a single delay line, while in other embodiments the variable delay line  122  is split into a coarse resolution variable delay line  818  and a fine resolution variable delay line  808 . 
     At block  1110 , the randomly modulated delay  140  is input to the fractional-N ADPLL  150  to reduce spurious tones resulting from delta-sigma modulation of the frequency control word  132 . In some embodiments, additional control signals can be added to control the amount of dither to support dithering for multiple TDC resolutions. 
     In some embodiments, certain aspects of the techniques described above may implemented by one or more processors of a processing system executing software. The software comprises one or more sets of executable instructions stored or otherwise tangibly embodied on a non-transitory computer readable storage medium. The software can include the instructions and certain data that, when executed by the one or more processors, manipulate the one or more processors to perform one or more aspects of the techniques described above. The non-transitory computer readable storage medium can include, for example, a magnetic or optical disk storage device, solid state storage devices such as Flash memory, a cache, random access memory (RAM) or other non-volatile memory device or devices, and the like. The executable instructions stored on the non-transitory computer readable storage medium may be in source code, assembly language code, object code, or other instruction format that is interpreted or otherwise executable by one or more processors. 
     A computer readable storage medium may include any storage medium, or combination of storage media, accessible by a computer system during use to provide instructions and/or data to the computer system. Such storage media can include, but is not limited to, optical media (e.g., compact disc (CD), digital versatile disc (DVD), Blu-Ray disc), magnetic media (e.g., floppy disc, magnetic tape, or magnetic hard drive), volatile memory (e.g., random access memory (RAM) or cache), non-volatile memory (e.g., read-only memory (ROM) or Flash memory), or microelectromechanical systems (MEMS)-based storage media. The computer readable storage medium may be embedded in the computing system (e.g., system RAM or ROM), fixedly attached to the computing system (e.g., a magnetic hard drive), removably attached to the computing system (e.g., an optical disc or Universal Serial Bus (USB)-based Flash memory), or coupled to the computer system via a wired or wireless network (e.g., network accessible storage (NAS)). 
     Note that not all of the activities or elements described above in the general description are required, that a portion of a specific activity or device may not be required, and that one or more further activities may be performed, or elements included, in addition to those described. Still further, the order in which activities are listed are not necessarily the order in which they are performed. Also, the concepts have been described with reference to specific embodiments. However, one of ordinary skill in the art appreciates that various modifications and changes can be made without departing from the scope of the present disclosure as set forth in the claims below. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the present disclosure. 
     Benefits, other advantages, and solutions to problems have been described above with regard to specific embodiments. However, the benefits, advantages, solutions to problems, and any feature(s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential feature of any or all the claims. Moreover, the particular embodiments disclosed above are illustrative only, as the disclosed subject matter may be modified and practiced in different but equivalent manners apparent to those skilled in the art having the benefit of the teachings herein. No limitations are intended to the details of construction or design herein shown, other than as described in the claims below. It is therefore evident that the particular embodiments disclosed above may be altered or modified and all such variations are considered within the scope of the disclosed subject matter. Accordingly, the protection sought herein is as set forth in the claims below.