Patent Publication Number: US-2018038843-A1

Title: Scalable and high throughput biosensing platform

Description:
RELATED APPLICATION 
     This application is a continuation of U.S. patent application Ser. No. 15/040,584, filed Feb. 10, 2016, which is a continuation of PCT Patent Application No. PCT/EP2014/068443, filed Aug. 29, 2014, which claims priority to Portuguese Patent Application No. 107138, filed Aug. 30, 2013, the disclosures of which are incorporated herein by reference in their entirety. 
    
    
     TECHNICAL FIELD 
     The present disclosure relates in general to biological analysis, and in particular to scalable, multi-channel high performance biosensing platforms, which are capable of high throughput biological analysis. 
     BACKGROUND ART 
     Conventional biological analysis methods are being gradually replaced by sophisticated and compact biochip-based point-of-care devices. These biochip-based point-of-care devices perform common blood or glucose analysis at a fraction of the cost of conventional biological analysis methods. Also, biochip-based point-of-care devices typically require a much shorter analysis time compared to conventional biological analysis methods. Given the high potential of these biochip-based point-of-care technologies, research in biodetection methods and in biochips themselves, has significantly grown in the past decade. 
     From continued research in biodetection methods, new and more efficient biological analysis methods have become possible, providing a valuable tool for several applications, namely, but not limited to: clinical diagnostics, forensics, veterinarian, food industry, agriculture, and drug screening. 
     DISCLOSURE OF INVENTION 
     According to aspects of the present disclosure, a biological detection system is provided. The biological detection system is characterized by a biochip and a biosensing platform. The biochip has at least two blocks of sensors, each block of sensors having a signal acquisition channel that is independently accessible such that each block of sensors can be read in parallel. The biosensing platform has drive circuitry to drive each block of sensors of the biochip. In an exemplary implementation, the same or different driving signals can be applied to each block of sensors of the biochip. Also, the biosensing platform further has a set of acquisition interfaces arranged such that a select one acquisition interface is coupled to a corresponding one signal acquisition channel of the biochip. The biosensing platform also has a set of co-processors such that a select co-processor is uniquely associated with a corresponding one of the acquisition interfaces. Still further, the biosensing platform has a central controller that controls the drive circuitry. The central controller also interfaces with the set of acquisition interfaces. Still further, the central controller interfaces with the set of co-processors to read data from the biochip. Moreover, the biosensing platform may provide a direct user interface, a remote interface or combination thereof. 
     According to further aspects of the present disclosure, a method of operating a biological detection system having a biochip, is provided. The method may be used, for instance, to calibrate drive circuitry to achieve a desired signal to noise ratio of signal data read from the biochip. The method is characterized by setting drive circuitry to generate a set of drive signals and by reading sensor data from the biochip. The method is also characterized by performing digital processing with a low frequency resolution on sensor data extracted from the biochip, using a subset of sensors that access a common signal acquisition channel of the biochip. The method is further characterized by using the result of the digital processing with a low frequency resolution to define a preliminary indication of a target frequency to measure a sensor data output from the signal acquisition channel, and by identifying a range or band of target frequencies. Yet further, the method is characterized by performing filtering and signal demodulation to displace a frequency (band) of interest from the identified range of target frequencies down to a base band and by designating a bit and frequency resolution from the base band that maximizes the signal to noise ratio of the data read from the signal acquisition channel. 
     The method may be further characterized by using a modulation technique to drive the biochip and correspondingly, performing demodulation to extract sensor data from the biochip. In another exemplary implementation, performing digital processing is further characterized by performing a fast Fourier transform with a low frequency resolution on sensor data extracted from the biochip, using a subset of sensors that access a common signal acquisition channel of the biochip. In yet another exemplary implementation, digital signal processing may be implemented for performing one or more complex correction algorithms, which may include a Kalman filter, drift compensation, and a temperature controller, on the result from the Fourier transform. 
    
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         FIG. 1  is a schematic representation of a system for biological analysis that integrates a biochip and an embedded biosensing platform, according to aspects of the present disclosure; 
         FIG. 2A  is an exploded view schematic representation of a biochip of the system for biological analysis illustrated in  FIG. 1 ; 
         FIG. 2B  is an exploded view schematic representation of a biosensing platform of the system for biological analysis illustrated in  FIG. 1 ; 
         FIG. 2C  is an exploded view schematic representation of an interface of the system for biological analysis illustrated in  FIG. 1 ; 
         FIG. 3  is a block diagram of a biosensing platform, according to aspects of the present disclosure herein; and 
         FIG. 4  is a method of operating a biological detection system having a biochip and a biosensing platform, according to aspects of the present disclosure. 
     
    
    
     MODES FOR CARRYING OUT THE INVENTION 
     According to various aspects of the present disclosure, systems, methods, and computer implemented processes are utilized to implement scalable, multi-channel high performance biosensing platforms, which are capable of high throughput biological analysis. For instance, aspects of the present disclosure find use in applications such as gene expression profiling, where thousands of biosensors analyze a given sample in parallel. In this regard, the biosensing platform described herein, integrates the complexity and computational needs of the electronic sensing system, into portable and standalone embedded systems with adequate computational capabilities for such high throughput analysis. 
     According to aspects of the present disclosure, systems are provided to deliver the computational power required by advanced biochip technology, and to allow simultaneous acquisition and processing at high sampling rates, through a high-performance and configurable acquisition and processing architecture. For instance, as will be described in greater detail herein, a biosensing platform is provided, which uses multiple dedicated co-processors performing Fast Fourier Transform (FFT)-based signal filtering, as well as other complex correction algorithms. An additional dedicated processor is used to synthesize the stimulus signals for the sensors, and a central processor is provided to control the whole system. With this approach, a fully autonomous embedded system is provided, which enables standalone operation of the platform, thus providing increased flexibility and usability. 
     Biological Detection System 
     Referring now to the drawings, and in particular, to  FIG. 1 , a biological detection system  100  is illustrated in schematic form, which is capable of biological analysis according to aspects of the present disclosure. In general, the biological detection system  100  includes a biochip  102  and a biosensing platform  104 . 
     The biological detection system  100  also integrates with an interface  106  to provide a complete lab-on-chip solution. The interface  106  may include for instance, local user interface peripherals (such as a keyboard, mouse, display, etc.), a remote interface, or a combination thereof, which can exchange data with electronics of the biosensing platform  104 . 
     Referring generally to  FIG. 1  and  FIG. 2A , the biochip  102  (e.g., a magnetoresistive biochip) includes one or more “blocks”  108  of sensors. For instance, as illustrated, there are n blocks of sensors where n is any integer greater than zero. In this manner, particular blocks are referenced as  108 - 1 ,  108 - 2 , . . . ,  108 - n , etc. Each block  108  of sensors has a signal acquisition channel  110  that may be independently accessible such that each block  108  of sensors can be read in parallel, as will be described in greater detail herein. The biochip sensors (e.g., the blocks  108  of sensors) achieve a high sensitivity, high Signal-to-Noise Ratio (SNR) and high dynamic range when used in conjunction with the biosensing platform  104  described herein. 
     As best illustrated to the left of the biochip  102 , an exploded view (of block  108 - 1  by way of example) illustrates that each block  108  includes a plurality of sensors. Each of the plurality of sensors can be of a various type (e.g. magnetic, temperature). By way of illustration, and not by way of limitation, there are 256 sensors in each block  108 , arranged in an array of 16 rows and 16 columns. According to aspects of the present disclosure, more than 256 sensors are required for many important applications (e.g., gene expression profiling). To address this requirement, the illustrative biochip  102  combines CMOS with thin film fabrication technologies to provide the required number of sensors on a small biochip package. Thus, for instance, a biochip  102  with over 1,000 sensors is realized by implementing n=4 blocks  108 , each with 256 sensors. However, in practice, each block  108  can have any number of sensors in its array. For instance, each block  108  can include  16  sensors or more in certain illustrative implementations. 
     In certain illustrative implementations, each block  108  of the biochip  102  may have a single acquisition channel. Each acquisition channel (or block of sensors themselves) can include integrated on-chip signal conditioning circuitry, and necessary readout circuitry to address and access the individual sensors of a corresponding block  108 . For instance, by using a sensor reading technique, such as Time-Division Multiplexing (TDM), a control device is able to address each of the biosensors (  256  biosensors in the above-example) through that single channel. For instance, each sensor can be read out individually using time-multiplexed reading techniques, such as by using a first multiplexer (“row multiplexer”) to select a desired row, and a second multiplexer (“column multiplexer”) to select a desired column. The sensor that is read out through the signal acquisition channel is thus the sensor at the intersection of the row selected by the row multiplexer and the column selected by the column multiplexer. In an illustrative implementation, the biochip  102  is characterized by each block of sensors having an array of at least 16 sensors and a corresponding time division multiplexer to read out individual sensors from a corresponding block. Moreover, in practical implementations, since there are multiple blocks  108  of sensors, the biochip  102  can provide a multichannel capability that includes up to, and/or in excess of 1000 sensors in certain exemplary implementations. 
     Referring now to  FIG. 1  and  FIG. 2B , the biosensing platform  104  includes in general, drive circuitry  112  that generates the necessary drive signal(s) for the corresponding biochip  102 . More particularly, the biosensing platform  104  includes drive circuitry  112  to drive each block  108  of sensors of the biochip  102 . In this regard, the manner in which the drive signals from the biosensing platform  104  couple to the biochip  102  will depend upon the particular implementation of the biochip  102 . However, by way of example, the drive circuitry may include circuitry to generate bias currents and oscillating magnetic fields that are applied to the sensors of the biochip  102 . 
     For instance, the drive circuitry  112  can include a single circuit with multiple outputs. Alternatively, the drive circuitry can include multiple independent circuits, e.g., an independent circuit for each block  108  of the corresponding biochip  102 . Still further, the one or more circuits that make up the drive circuitry  112  can be software-based, hardware based, or a combination of the above. In this regard, drive signals can be fully or partially programmable, controlled by set points, parameters or other program variables, made adjustable by control signals, e.g., programmed by control voltages or other control signals, etc. 
     As illustrated, the drive circuitry  112  is controlled by a central processor  114 . Thus for example, in an illustrative implementation, the drive circuitry  112  is controlled by the central processor  114  to have an adjustable frequency. Moreover, the central processor  122  can control the drive circuitry to generate arbitrary signal shapes and amplitudes. For instance, the drive circuitry  112  can utilize Direct Digital Synthesizers (DDSs) that can be combined with arbitrary signal generators deployed in a reconfigurable fabric, which are controlled by the central processor  114 , to provide the correct signals to the corresponding biochip  102 . 
     The biosensing platform  104  also includes multiple (e.g., a set of) acquisition interfaces  116 . As illustrated, the biosensing platform  104  includes n acquisition interfaces  116  where n is any integer greater than zero. In the illustrated example, a select one acquisition interface  116  is coupled to a corresponding one signal acquisition channel  110  of each block  108  of the biochip  102 . Thus, where the biochip  102  has  4  blocks  108 , each block having a single, signal acquisition channel  110 , the corresponding biosensing platform  104  includes  4  acquisition interfaces  116 , each acquisition interface  116  connected to a corresponding unique one of the biochip signal acquisition channels  110 . 
     In the illustrative schematic representation, each acquisition interface  116  includes a converter  118 , e.g., an analog to digital converter, which receives the signal from its corresponding signal acquisition channel  110 . The analog to digital converter converts the sensor signal into a digital representation that can be further processed, as will be described in greater detail herein. As an illustrative example, an acquisition interface  116  is configured to measure sensor data from the corresponding signal acquisition channel  110  at a specific binding frequency or frequency band that is determined by the modulation induced by the magnetic field, the bias current, the sensor&#39;s response to these AC signals, and the system&#39;s noise and cross-talk. For instance, each analog to digital converter  118  may have a sampling frequency of at least 1 kHz and at least 12-bit resolution to accomplish the desired sampling. 
     The output of the analog to digital converter  118  couples to a controller  120 , e.g., a serial peripheral interface controller. Each acquisition interface  116  may also include signal conditioning circuitry as necessary to interface with the analog signals from the biosensor  102 . The controllers  120  are each controlled by the central processor  114 . 
     Moreover, in an exemplary implementation, each controller  120  couples to a corresponding co-processor  122 . In this manner, each controller  120  conveys information from its corresponding analog to digital converter  118  to its corresponding co-processor  122 . Thus, the illustrated biosensing platform  104  includes a set of co-processors  122  (e.g., n co-processors where n is any integer greater than zero) such that a select co-processor  122  is uniquely associated with a corresponding one of the acquisition interfaces  116 . In alternative implementations, there need not be a one-to-one correspondence between acquisition interfaces  116  and co-processors  122 . For instance, there may be a single co-processor  122  for all channels (acquisition interfaces  116  ). Also, a single co-processor  122  can be utilized to service a subset of acquisition interfaces  116 . 
     Each dedicated co-processor  122  performs digital processing, e.g., Fast Fourier Transform (FFT)-based signal filtering on the data from the corresponding acquisition interface. Each co-processor  122  can also/alternatively perform other complex correction algorithms, e.g., a complex correction algorithm including a Kalman filter. Yet further, each co-processor  122  can be used to implement a temperature controller, a complex modulator and demodulator, etc. The co-processors  122  also communicate with the central processor  114 , which controls the biosensing platform  104 . 
     In this manner, to read data from the biochip, the central processor  114  of the biosensing platform  104  controls the drive circuitry  112 . The central processor  114  also interfaces with the set of acquisition interfaces  116  (e.g., via the controllers  120  ). Yet further, the central processor  114  interfaces with the set of co-processors  122 . Also, the central processor  114 , a dedicated co-processor  122  or other processor (not shown) can be utilized to synthesize the stimulus signals for the data read from the sensors of the biochip  102 . 
     The illustrated biosensing platform  104  further includes a main memory  124 . The main memory can couple to the central processor  114  and/or to one or more of the co-processors  122 . For instance, the central processor  114  and the co-processors  122  can share the main memory  124 . In this regard, main memory  124  may be used to store programming, control information, calibration information, data, etc. As such, in certain applications, a computer processing device (e.g., personal computer or server computer) need not be connected to the biosensing platform  104  in order for the system to be operational. This allows, for instance, flexible standalone use. At a suitable time, the biosensing platform  104  can be coupled to the computer processing device, e.g., to download collected signal data, etc. 
     In this regard, the biosensing platform  104  includes electronic circuitry for addressing the biochip  102 , for driving control signals and for conditioning and acquiring the biochip signals. The acquired signals are processed by a set of co-processors  122  and are transmitted to the central processor  114 , e.g., which executes software that functions as a digital analyzer where, through the interface  106 , e.g., a conventional graphical user-interface, the experiment is controlled by the operator or analyst. The biosensing platform  104  provides multiple signal acquisition channels  110  operating at a high sampling rate, thus producing a high volume of data. As such, the biosensing platform  104  also includes the necessary computation power that is required to handle the volume of data. 
     Referring to  FIG. 1  and  FIG. 2C , the interface  106  may comprise a monitor, keyboard, mouse or other computer peripherals, a graphical user interface, network interface, etc. In an illustrative implementation, the biological detection system includes a biosensing platform implemented in two components, including a programmable logic component and a processing system component, wherein the drive circuitry  112  (e.g., drive signal synthesizer), the co-processors  122  and the acquisition interfaces  116  are implemented in the programmable logic component, and the central processor  114  and the main memory  124  are implemented in the processing system. 
     The central processor  114  may further communicate over a network, which provides communications links between various processing devices, and may be supported by networking components that interconnect the processing devices, including for example, routers, hubs, firewalls, network interfaces, wired or wireless communications links and corresponding interconnections, cellular stations and corresponding cellular conversion technologies, e.g., to convert between cellular and tcp/ip, etc. Moreover, the network(s) may comprise connections using one or more intranets, extranets, local area networks (LAN), wide area networks (WAN), wireless networks (WIFI), the Internet, including the world wide web, cellular and/or other arrangements for enabling communication between the processing devices, in either real time or otherwise, e.g., via time shifting, batch processing, etc. 
     Example Implementation 
     With reference to  FIG. 1 , and  FIGS. 2A-2C  generally, a laboratory assay begins by labeling biological targets under analysis with Magnetic Particles (MPs). Then, a bias current, i B , and an oscillating magnetic field signal, h B , are applied to the sensors of the biochip  102 , e.g., via the drive circuitry  112  of the biosensing platform  104 . Upon biomolecular recognition and washing, the sensors detect the fringe fields created by the MPs that have been captured by biological probes placed above the sensors. The biological information is then extracted by measuring the variations of the sensor voltage signal, v bind . 
     To reduce the system cost and complexity, the sensors of each block  108  are measured using Time-Division Multiplexing (other modulation and multiplexing techniques can alternatively be applied). Since reaching a low noise level typically requires a high number of samples per sensor, biochip reading times can be slow, e.g., about  4  minutes. Such biomolecular recognition at a low speed, may be acceptable for certain biochips. However, such slow recognition does not scale when the number of sensors grows to 1000 or more. To circumvent issues of slow speeds, the biochip  102  is organized in groups of sensors, e.g.,  256  sensor elements per block  108 , and each sensor is time multiplexed within its corresponding block, as noted above. With this approach, the total reading time is constrained to the number of sensors within each group, as processing is performed in parallel. Thus biochip size can be scaled without increasing the overall reading time. Nevertheless, this also imposes significant hardware resources in the platform electronics. Each group  108  of the biochip  102  is serviced by a dedicated acquisition channel interface  116  of the biosensing platform  104 , e.g., comprising signal conditioning circuits and an Analog-to-Digital Converter (ADC)  118 . Furthermore, the data from each channel is processed in parallel, to allow the observation of the assay evolution in real-time. 
     Additional characteristics of the biochip must also be considered. According to an exemplary implementation, to avoid the effect of low frequency noise and maximize the attained SNR, the applied signals from the drive circuitry  112 , e.g., applied signals i B  and h B  in the FIGURES, include an AC component. Consequently, v bind  measured at a specific binding frequency, f bind , which is determined by the modulation induced by the magnetic field h B  {f 2 }, the bias current i B  {f 1 }, the sensor&#39;s response to these AC signals, and the system&#39;s noise and cross-talk. At each sensor block multiple modulation frequencies can be applied in both magnetic field and bias current. 
     Due to the complexity of the biochip technology and of the circuitry that drives and measures the sensors, it may not be easy to determine a good a-priori estimate of the frequency at which the SNR is maximum. To optimize the biological sensitivity, f bind  should be adapted in real-time, by changing the frequencies of i B  and/or h B . However, this introduces the added difficulty of determining the signal amplitude at an unknown frequency. According to illustrative aspects of the disclosure herein, a flexible and tractable method is to use an FFT of the signal acquired at each of the 1000+ sensors, to compute the signal amplitude v bind  at the frequency f bind . Although it ensures a good adaptability, this approach may require a sampling frequency of at least 50 kHz and a frequency resolution as low as 1 Hz, for a 24-bit resolution in each sensor. That said, aspects of the present invention can function suitably, for instance, with a sampling frequency of at least 1 kHz and at least a 12-bit resolution. Regardless, this imposes large memory and hardware requirements, constraining the scalability of the system. Additionally, other complex correction algorithms can be implemented by each co-processor  122 , namely but not limited to: drift correction, temperature controller, Kalman filters, complex modulator and/or demodulator (e.g. spread spectrum). 
     Architecture 
     The computational performance required by the biosensing platform  104  to ensure the resolution and reliability of bio-recognition assays can be achieved by optimizing the processors&#39; architecture and by increasing the exploited parallelism with the usage of multicore structures. Nonetheless, it would be insufficient to exclusively address the performance limitations, since the bottleneck may also arise in the communication channels, such as the one connecting the acquisition circuits to the processing unit. Furthermore, due to the significant complexity of the underlying algorithms, the processing unit must be able to store and manipulate large datasets, making it clear that a high memory bandwidth and capacity are necessary to take full advantage of the enhanced processing capabilities. 
     As described more fully herein, the architecture to fulfill the requirements of the high throughput biosensing platform is depicted in  FIG. 1 . In general, when implementing the biosensing platform  104 , a high-speed serial interface may be selected in order to provide a fast communication between the ADCs  118  and the set of dedicated co-processors  122  (e.g., cores) where the most computational intensive tasks are handled. All components, including the generator of the stimuli signals, are configured by a central processor  114 , e.g., also referred to herein as a General Purpose Processor (GPP) which, aside from acting as the main system controller, can also perform auxiliary computations on the acquired data and user interface tasks as well as communication tasks. The central processor  114  shares its main memory  124  with the co-processors  122 . A user interface, controlled through the central processor  114 , is preferable performed through interface  106  which includes a set of I/O devices, such as the input peripherals used to control the experiment and a display on which the results are presented to the user. A network interface, controlled through the central processor  114 , is also included, allowing the processed data to be transferred to an external database, easily available to other users. 
     Central Processor and Main Memory 
     The central processor  114 , e.g., the GPP, is a suitable device to configure the several system components, and thus the central processor  114  plays a key role on easing the system integration. In certain illustrative implementations, Operating System (OS) support is necessary, in order to benefit from the available software packages that provide complex system management functionalities and high-level interfaces to the standard I/O and memory peripherals. A processor-memory interconnection subsystem (subsystem that interconnects the central processor  114  to the main memory  124  ) can be equipped with DMA channels (or equivalent), allowing the central processor  114  to communicate with streaming peripherals within a shared memory space. 
     High-Throughput Sensor Interface 
     Each acquisition channel is linked to one biochip sensor group  108  and directly feeds one specialized co-processor  122  with the data sampled by the ADC  118 . In an exemplary implementation, since each ADC  118  can operate at a maximum rate of 96 Mbit/s, the absence of a high-speed data channel would seriously compromise the overall throughput. In the exemplary implementation, standard Low-Voltage Differential Signaling (LVDS) was chosen as a cost-effective and noise tolerant solution to achieve high transmission rates. On top of this physical layer, a Serial Peripheral Interface (SPI)  118  bus protocol is utilized, to provide configuration and addressing capabilities based on an SPI master/slave controller. 
     Specialized Co-Processors 
     The specialized co-processors  122  are responsible for measuring the amplitude of the sensors binding signal, v bind , from the biosensor  102 , at a specific frequency. This signal is estimated using a zoom-in FFT approach together with other complex processing algorithms like Kalman filters that improve the overall data accuracy. In a first step, an FFT is performed with a low frequency resolution, and by using a subset of sensors in the same channel. This provides a coarse and preliminary identification of the best f bind  frequency to measure the v bind , while keeping the hardware resources and power consumption at tolerable levels. After identifying the fbind range, band-pass filtering and signal demodulation are performed, to displace the frequency of interest down to base band. This allows the computation of multiple FFTs (one per channel) with a higher bit and frequency resolution, while still confining the required resources. Also, to increase the signal to noise ratio and achieve system scalability, the zoom-in procedure can be performed as many times as required. Complex demodulators (e.g. spread spectrum) can also be implemented in the co-processors to achieve a higher multiplexing capability. 
     Due to the involved computational complexity, a reconfigurable field programmable gate array (FPGA) device is regarded as a suitable technology to accommodate the multi-core infrastructure of specialized FFT co-processors, filters and demodulators  122 . An FPGA combines the required high performance level, while still conferring the flexibility to change or update the adopted processing algorithms. In particular, multiple configurations can be stored in memory for each zoom-in level. In run-time, the user starts by observing the coarse signal spectrum of the initial subset of sensors. Then, the most favorable demodulation frequency and spectrum band is selected. This will trigger the FPGA reconfiguration and the deployment of the specialized co-processors in hardware, configured with the target demodulation frequency. At this point, the user can observe the binding signal for each sensor. 
     I/O Peripherals and User Interface 
     A set of I/O peripherals  106  are utilized to make the biosensing platform  104  a standalone analysis and diagnosis system. These modules not only allow the user to take full control of the experiment, but also offer the visualization means for clinical interpretation purposes. The standard set of computer peripherals (i.e. USB keyboard/touch screen panel and HDMI monitor) is typically utilized as interfaces to the biosensing platform  104  to enhance the usability experience. 
     Stimulus Signal Generator 
     Referring now to  FIG. 3 , a portion of the biological detection system  100  of  FIG. 1  is illustrated. In particular,  FIG. 3  illustrates a partial view of the biosensing platform  104 . For instance, only a single signal acquisition interface  116  is illustrated for convenience of illustration and discussion. Also, the biochip  102  and the interface devices  106  have been omitted for convenience of discussion. 
     Reference AC signals must be supplied by the drive generator  112  to the biosensors of the biochip  102 , to produce a measurable response (e.g., i B  and h B  discussed above). The amplitude, shape and frequency ranges of these stimuli are partially constrained by the considered biochip technology. However, the noise level that the measurements are exposed to is inversely proportional to the frequency of these signals. Thus the accuracy of the results is strongly constrained by this parameter. As a consequence, a variable and configurable frequency generator component of the drive circuitry  112 , which can be adjusted and parametrized by the central processor  114  (e.g., GPP), ensures the adaptability of the biosensing platform  104  to multiple generations of the biochip  102 . The required signal generators can be implemented by using Direct Digital Synthesizers (DDSs) deployed in a reconfigurable fabric, which can be combined with additional hardware in the reconfigurable fabric to achieve complex modulation like spread spectrum, and controlled by the central processor  114 . 
     Exemplary Implementation 
     In a working exemplary embodiment, a XILINX ZYNQ 7000 Extensible Processing Platform was utilized to build the biosensing platform  104  as an embedded system. This particular System on a Chip (SoC) includes a state of the art reconfigurable fabric and it offers most of the features required for the system described more fully with regard to  FIGS. 1-3 . 
     ZYNQ SoC Architecture 
     The ZYNQ SoC integrates two independent modules in the same chip: a Processing System (PS), featuring a processor  132 , e.g., a dual-core ARM CORTEX-A9 processor, and Programmable Logic (PL), consisting of reconfigurable fabric compatible with XILINX 7-Series FPGAs. In addition to the ARM processors and the associated DDR-memory controller, the PS also integrates a collection of industry-standard communication interfaces  134  (Gigabit Ethernet, USB, I2C and SPI). At boot time, the PS configures the PL by means of the Processor Configuration Access Port (PCAP) and initializes the system clocks. Through the PCAP, the ARM processor is able to exploit the software-driven dynamic partial reconfiguration capabilities of the reconfigurable fabric, thus promoting an adapted and optimized usage of the reconfigurable part of this SoC. 
     The PS-PL interconnection can be achieved by using an interface, e.g., the Advanced eXtensible Interface (AXI) bus protocol, through any of the provided connectivity ports, namely, General-Purpose (AXI-GP), High-Performance (AXI-HP), and Accelerator Coherency Port (AXI-ACP). For instance, as illustrated, two master and two slave AXI-GP interfaces  136  connect the PL to a PS central interconnect  138 , allowing for low throughput data and control transfers. When high throughput is required, a separate interface  140 , e.g., an AXI-HP interface, connects directly to the main memory  142 . In this interface  140 , read and write operations are mediated by an asynchronous 1 kB FIFO with a configurable data width of 32 or 64 bits. The AXI-ACP interface connects the PL directly to the Snoop Control Unit (SCU), to ensure data coherency at the L2 shared cache of the ARM processors. All these ports can be individually enabled and configured. On the PL side, these interfaces are implemented using the existing reconfigurable logic, thus having an associated cost in terms of hardware resources. 
     Implementation 
     While the ARM processor on the PS is used to control the platform, the reconfigurable fabric on the PL is used to implement the dedicated co-processors and to support the interface with the biochip. The base software layer running in the PS is implemented in an exemplary implementation, using the LINARO UBUNTU GNU/Linux OS, which provides optimized tools and software packages for ARM SoCs. By adopting this OS, the PS provides a rich interface to the user by using the existing set of computer peripherals. 
       FIG. 3  depicts the block diagram of the implemented architecture, considering a single-channel  116 . It corresponds to the initial zoom-in phase, where an FFT is computed over a small subset of sensors from a single acquisition channel to determine the binding frequency, f bind  that maximizes the signal to noise ratio. In the multi-channel implementation, where parallel channels read biological information of 1000+ sensors, the Co-processor channel  1 X in  FIG. 3  is replicated as necessary, according to the blocks  108 /acquisition channels  116  of the biochip  102 . 
     Several AXI interfaces connect the reconfigurable fabric to the ARM processor and to the associated main memory, either for control or for high throughput data transfers. By following the design strategy commonly adopted in DMA-based peripherals, each devised co-processor provides a slave interface for configuration purposes, along with a master controller that writes in the shared memory bus. Data consistency between the dedicated co-processors and the GPP is achieved by using a contiguous region in the main memory, marked as non-cacheable and excluded from the system&#39;s memory management. The OS is able to read this memory region by remapping the region into the kernel virtual address space, thus allowing it to be easily accessed by a custom device driver. 
     FFT Co-Processor 
     In an illustrative implementation, the FFT co-processors (e.g., co-processor  122 ) in the PL are based on the XILINX FFT IP core v7.1, and adopt a pipeline operation to produce an output per clock cycle in a stream-based processing scheme. The cores are configured to receive 24-bit fixed-point real inputs, although a higher precision is used inside the cores to decrease numerical error propagation between intermediate stages. Furthermore, embedded DSP blocks are used in the butterfly computations to allow for a better balance in the DSP/BRAM usage within the available reconfigurable fabric. A significant amount of BRAMs is needed for data and phase factor storage when the FFTs are computed with a high amount of points. However, the adoption of the zoom-in approach allows the total memory requirements per channel, to be kept at reasonable levels. In all zoom-in levels, the synchronous reset and start bit signals are obtained from a control register, allowing for an operation fully controlled by the PS. Also, since the considered signal processing algorithm requires the squaring of the FFT complex output, an additional squaring block is introduced at FIFO output. 
     PL-PS Data Streaming and Interface 
     In an illustrative implementation, the communication between the several logic blocks on the reconfigurable fabric and the ARM GPP is ensured by specifically defined control and data channels. By following a memory-mapped I/O approach, a set of control registers are made accessible to the programs executing on the ARM, providing convenient software reset and start flags triggering functionalities. These registers are placed on an AXI bus, mastered by the CPU through an AXI-GP interface port. An AXI-HP port is used to transfer the FFT output frames directly to the main memory, where they can be subsequently accessed by the CPU. Since this shared memory region is contiguous and is not directly managed by the OS kernel (as explained above), an AXI Burst Master Controller is used to provide these co-processing channels  144  with a direct memory access. This solution provides a data-transfer performance equivalent to a conventional DMA engine, but reduces the hardware requirements by approximately 7 times. 
     When multichannel processing is considered, the architecture in  FIG. 3  is expanded to incorporate as many co-processing blocks as the number of channels, e.g., blocks  108 /acquisition channels  116  of the biochip  102  (dashed box labeled Co-processing channel  144  in the lower part of  FIG. 3 ). The co-processing blocks are then connected to the AXI-HP port, which provides a communication channel between the co-processors and the main memory capable of supporting data transfers of up to 1.2 GByte/s (estimate). This is well above the 72 KBit/s bit-rate of the ADC in certain biosensor applications. Even considering that higher bit-rates are required for the disclosed biosensing platform, this bandwidth is enough to support multiple channels (the biochips  102  comprise 4 channels), and still provides enough resources for future expansions. However, it should be noticed that a continuous data transmission must be assured to achieve a throughput of 1.2 GByte/s. To guarantee this requisite, a dual clock domain FIFO memory is used to implement a bridge between the FFT processing channels and the AXI-HP bus connected to the main memory. 
     System I/O and User Interface 
     In an illustrative implementation, two different interfaces are supported by the biosensing platform: i) an SPI-based interconnection with each channel ADC and with stimuli generator, ii) the interface with the human operator. The connections to the biosensing ADC and with the stimuli generator can be accomplished by an open-source core implementation of the SPI protocol, available at OpenCores.org. The selection of this particular core takes into account its particular characteristics in terms of versatility and resource efficiency. 
     Referring generally to  FIG. 1 ,  FIG. 2C , and  FIG. 3 , in an illustrative implementation, the interface  106 , e.g., graphical user interface, is accomplished by using an HDMI graphics port and an USB keyboard, USB touch-screen panel or other suitable interface. Although an HDMI interface already exists in the ZYNQ platform, the controller has to be implemented on the reconfigurable fabric. The controller module was obtained from a reference design targeting an HDMI output interface, along with the physical and data streaming blocks required to handle DMA video streams. These DMA engines are connected to two separate AXI-HP ports, enabling them to directly gather video data from the main memory. The HDMI control logic (also on the PL side), is connected to an AXI-GP interface and is mapped into the memory-space of the OS, allowing the usage of existing software device drivers. 
     Method Calibrating a Biological Detection System 
     Referring to  FIG. 4 , according to further aspects of the present disclosure, a method  400  of operating a biological detection system having a biochip, is characterized. The method  400  may be used, for instance, to calibrate drive circuitry signals for the best signal to noise ratio. The method  400  is implemented by setting at  402 , drive circuitry to generate a set of drive signals and reading at  404 , sensor data from a biochip. The method  400  is also characterized by performing at  406 , digital processing, with a low frequency resolution on sensor data extracted from the biochip, using a subset of sensors that access a common signal acquisition channel of the biochip. The method  400  is further characterized by using the result of the digital processing with a low frequency resolution to define at  408 , a preliminary indication of a target frequency to measure a sensor data output from the signal acquisition channel, and by identifying at  410 , a range or band of target frequencies. Yet further, the method is characterized by performing at  412 , filtering and signal demodulation to displace a frequency (band) of interest from the identified range of target frequencies down to a base band and by designating at  414 , a bit and frequency resolution from the base band that maximizes the signal to noise ratio of the data read from the signal acquisition channel. 
     In further aspects, the method may be further characterized by performing demodulation where sensor data extracted from the biochip results from using modulation techniques. In another exemplary implementation, performing digital processing is further characterized by performing a fast Fourier transform with a low frequency resolution on sensor data extracted from the biochip, using a subset of sensors that access a common signal acquisition channel of the biochip. In this regard, the method may also be further characterized by performing complex correction algorithms including at least one of a: Kalman filter, drift compensation, and a temperature controller, on the result from the Fourier transform. 
     Experimental Results 
     To properly evaluate the scalable multichannel architecture, experimental results were obtained by using a ZEDBOARD featuring a ZYNQ XC7Z020, one of the smallest and less power demanding ZYNQ SoCs, and was synthesized and mapped using the XILINX 14.3 development tools. The presented analysis starts by considering a single channel architecture implementation with the largest allowed FFT core, which is used to determine, with maximum accuracy, the biosensors binding frequency region. Experimental results are presented in Table 1 and show that the FFT-size (64k samples) is limited by the amount of available block RAMs in the PL. Furthermore, the results show that the resources required by the remaining structure corresponds to only 33.5% of the available LUTs, only 8 BRAMs and 19 DSPs. From this, it can be concluded that the majority of the PL hardware resources are made available to be used by the co-processing channel(s). 
     
       
         
           
               
             
               
                 TABLE 1 
               
             
            
               
                   
               
               
                 System resources for a single channel 64K FFT. 
               
            
           
           
               
               
               
               
            
               
                 Component 
                 LUT (53200) 
                 BRAM (140) 
                 DSP48 (220) 
               
               
                   
               
            
           
           
               
               
               
               
               
               
               
            
               
                 64k FFT core 
                 7157  
                 (13.5%) 
                 106  
                 (75.7%) 
                 103  
                 (46.8%) 
               
               
                 Squaring module 
                 149  
                 (0.3%) 
                 0  
                 — 
                 16  
                 (7.2%) 
               
               
                 Drive signals (DDS) 
                 174  
                 (0.3%) 
                 2  
                 (1.4%) 
                 3  
                 (1.4%) 
               
               
                 AXI wrapper 
                 572  
                 (1.1%) 
                 0  
                 — 
                 0  
                 — 
               
               
                 SPI Master 
                 131  
                 (0.2%) 
                 0  
                 — 
                 0  
                 — 
               
               
                 Core system 
                 13857  
                 (26.0%) 
                 6  
                 (4.3%) 
                 0  
                 — 
               
               
                 Full system 
                 25097  
                 (47.2%) 
                 114  
                 (82.1%) 
                 122  
                 (55.4%) 
               
               
                   
               
            
           
         
       
     
     To evaluate the scalability and adaptability of the architecture to the case when zoom-in is performed and multiple channels are required, bit-streams with smaller FFT cores were generated and the number of channels was maximized by balancing the usage of DSPs, BRAMs and LUTs. Table 2 presents the resources used by a single co-processing channel  144 , considering FFTs with increasing number of points, and the maximum number of co-processing channels  144  supported on the PL. It should be noticed that for the 1k-, 2k- and 4k-FFT the maximum number of channels is constrained by the number of available DSP48 elements; for larger FFTs the limitation lies in the BRAMs. Also, in the 32k-FFT, to support 2 channels, some block RAMs were implemented using LUTs. 
     
       
         
           
               
             
               
                 TABLE 2 
               
             
            
               
                   
               
               
                 Co-processing channel hardware requirements. 
               
            
           
           
               
               
               
            
               
                 FFT size 
                 Hardware resources (per channel) 
                 Maximum 
               
            
           
           
               
               
               
               
               
            
               
                 (#samples) 
                 LUT (53200) 
                 BRAM (140) 
                 DSP48 (220) 
                 #channels 
               
               
                   
               
            
           
           
               
               
               
               
               
               
               
               
            
               
                 1024 
                 3686 
                 (7%) 
                 8 
                 (6%) 
                 24 
                 (11%) 
                 8 
               
               
                 2048 
                 4375 
                 (8%) 
                 11 
                 (8%) 
                 31 
                 (14%) 
                 6 
               
               
                 4096 
                 4765 
                 (9%) 
                 14 
                 (10%) 
                 31 
                 (14%) 
                 6 
               
               
                 16384 
                 7201 
                 (14%) 
                 28 
                 (20%) 
                 40 
                 (18%) 
                 4 
               
               
                 32768 
                 7916 
                 (15%) 
                 55 
                 (39%) 
                 49 
                 (22%) 
                 2 
               
               
                 65536 
                 7254 
                 (14%) 
                 106 
                 (76%) 
                 103 
                 (47%) 
                 1 
               
               
                   
               
            
           
         
       
     
     The presented results suggest that it is possible to achieve a multichannel processing system composed of 8 FFT channels of 1024 points. Hence, with up to 256 biosensors per channel, a total of 2,048 biosensors can be processed and the sweep time is reduced by a factor of 8. Additional multiplexing can be achieved by using other complex modulation techniques like multi carriers or spread spectrum. This demonstrates the adaptability of the proposed system to multichannel processing, while keeping the required amount of hardware resources compatible with this entry level ZYNQ SoC. The FFT cores are capable of operating above 180 MHz, producing  1  output sample per clock cycle. Considering that the system must support an ADC sample rate of up to 4 Msps, which corresponds to the state of the art in high resolution converters, this suggests that the FFT cores do not impose any limitation to the signal analysis performance. 
     On the other hand, the AXI-HP allows an estimated maximum transfer rate of 1.2 GByte/s, while, for a data width of 32 bits, the FFT core outputs a bit-rate of at most 128 Mbit/s. Hence, the AXI-HP bandwidth does not limit the system operation, supporting multiple acquisition channels. Considering that the developed biochip features 4 sensor blocks (1024 sensors), the bit rate could still be increased if faster ADCs become available. 
     From these results, it can be concluded that the architecture herein, mapped on a ZYNQ SoC, provides the computational resources required to implement a fully embedded and high performance biosensing platform. Furthermore, the implemented prototype also demonstrated that a scalable and adaptable platform can be obtained with the existing reconfiguration capabilities, capable of adapting to biochips with higher sensor count and different computational needs. 
     Miscellaneous 
     According to aspects of the present disclosure, systems are provided to deliver the computational power required by advanced biochip technology, and to allow simultaneous acquisition and processing at high sampling rates, through a high-performance and configurable acquisition and processing architecture. For instance, as described in greater detail herein, a biosensing platform is provided, which uses multiple dedicated co-processors performing Fast Fourier Transform (FFT)-based signal filtering, as well as other complex correction and modulation/multiplexing algorithms. An additional dedicated processor is used to synthesize the stimulus signals for the sensors, and a central processor is provided to control the whole system. With this approach, a fully autonomous embedded system is provided, which enables standalone operation of the platform, thus providing increased flexibility and usability. 
     In this manner, new high density biochips are regarded as highly promising solutions for numerous applications, where high throughput analysis is required. However, existing electronic platforms are not able to acquire and process the higher amount of produced data. The scalable multi-channel and high-throughput architecture herein meets the needs to acquire and process this higher amount of data, e.g., even when implemented on a single ZYNQ SoC. For instance, even when using one of the smallest ZYNQ&#39;s, experimental results demonstrate that the system supports  8  times more sensors and a 1000+ times higher sampling frequency than the previous generation of the biosensing platform. By taking advantage of the reconfigurable characteristics of this SoC, results also suggest that the chosen platform allows to implement a scalable system supporting co-processors with configurable FFT sizes, enabling optimized and adjustable signal measurement for each biochip, without sacrificing efficiency in hardware resource usage, allowing the developed system to be expanded in order to deal with the requirements of future biochips. 
     The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. 
     The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. Aspects of the invention were chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated.