Patent Publication Number: US-4224639-A

Title: Digital synchronizing circuit

Description:
The present invention relates to a circuit arrangement for vertical synchronization of a television receiver. 
     The normal practice is for the vertical deflection circuit to consist of an astable multivibrator circuit, synchronized by the vertical sync pulse separated in the known way from the received video signal. The only means of noise protection on this circuit is the sync separator and the pull-in range of the multivibrator; the smaller the range is, the more protection there is against noise since the sync signal has less time to synchronize the multivibrator. In practice, the pull-in range can never be very small as it must allow recovery of the multivibrator circuit tolerances and drifts so that noise immunity is never really satisfactory. This leads to vertical trembling of the picture and even loss of the picture altogether in the case of a low signal/noise ratio or pulse disturbances such as those caused by electric machines, etc. 
     As synchronization is direct, the phase is not very stable as a result of interference on the sync pulse front caused by unwanted noise signals, such as line-frequency pulses, which result in poor stability and interlacing of the picture on the screen. Vertical synchronization circuits are known (French Pat. No. 2248659) which use a digital technique to obtain a vertical deflection signal by frequency division of another signal derived from the line deflection signals, that is, which rely on the principle that, for a given television standard, the number of lines in a frame is a constant. In theory, these circuits could eliminate entirely the drawbacks of the known systems already mentioned. In practice, however, it is not enough to generate a signal with the exact field frequency of the television signal. A given phase relationship must also be established between it and sync pulses. The phase of the frequency divider must be determined by applying the sync signals as reset pulses. 
     The present invention seeks to provide a digital circuit arrangement for generating a vertical deflection signal which mitigates the problems encountered in known systems. 
     According to the present invention, there is provided a circuit arrangement for vertical synchronization of a television receiver with respect to received sync signals, the arrangement comprising a frequency divider connected to receive pulses derived from an incoming line frequency signal to generate vertical sync pulses, a circuit for detecting coincidence between the vertical sync pulses generated by the divider and received vertical sync pulses, a further circuit operative to produce no more than one pulse during each vertical deflection cycle indicative of any phase error between the generated and the received vertical sync pulses and a control circuit connected to the coincidence detecting circuit and to the said further circuit for resetting the divider to rephase the generated vertical sync pulses for synchronism with the received vertical sync pulses. 
    
    
     The invention will now be described further, by way of example, with reference to the accompanying drawings, in which: 
     FIG. 1 shows a block circuit diagram of a vertical or frame synchronizing circuit according to the present invention which employs negative logic elements; 
     FIG. 2 shows a variant of the circuit in FIG. 1; and 
     FIG. 3 shows the waveforms present at certain points in the circuits of FIGS. 1 and 2. 
    
    
     In FIG. 1, an input terminal C, on which a double-line-frequency signal is available, is connected to the clock input (CP) of a counter 1 which divides by 625, and the output (U) of which is connected to a first input (CP) of a D-type flip-flop 2, to a first input (Set) of an R-S flip-flop 3 and to a first input of an OR gate 7. 
     A second input terminal S, at which a sync signal is available, is connected to the second inputs, D and Reset respectively, of flip-flops 2 and 3 and to a first input of an AND gate 5, the second input Q 2  of which is connected to the output of flip-flop 3 by way of a delay circuit 4. 
     The output of AND gate 5 is connected to a first input of an AND gate 6 the second input of which is connected to the output of flip-flop 2 (Q 1 ) and the output of which is connected to the reset input (R) of the counter 1 and to the second input of OR gate 7, the output of which is connected to output terminal V. 
     The circuit of FIG. 1 will now be described with reference to FIG. 3 which comprises voltage waveforms &#34;A&#34; to &#34;O&#34;, the point in the circuit of FIG. 1 at which the voltage occurs being indicated in the right hand side of FIG. 3. FIG. 3 shows three possible forms of the voltage at the point S and the resultant waveforms at the points Q 1 , Q 2  and R when the voltage at U is as shown in FIG. 3a. 
     In the case of the voltage at S being in accordance with FIG. 3b, the synchronization signals are present and in phase with the sync pulses generated on line U by the counter 1 but the synchronization signal includes additional spurious pulses. The waveform 3c which is the output of Q 1  of the D-type flip-flop 2 is the result of detecting the presence of sync signals on the line S at the instant that the counter 1 stops counting. If the sync pulse is present at the leading edge of the pulse in the waveform U then the voltage at Q 1  remains low. If, however, no sync pulse is present then the output voltage at Q 1  goes high. 
     The output Q 2  is the result of delaying by a time T, determined by the delay circuit 4 pulses produced by the flip-flop 3 which is set by the pulses U and reset by the pulses S. 
     In the case of the waveform shown in FIGS. 3a to 3e, the voltage at Q 1  never goes high and consequently the AND gate 6 is permanently blocked with the result that the signal U is passed by the OR gate 7 as the output at V. This is the desired operation since the incoming pulses are in phase with the sync pulses and one wishes to ignore the intervening spurious pulses. 
     In the case of the waveform shown in FIGS. 3f to 3i, the first sync pulse is present but the second is omitted, possibly due to a weak signal. At the second pulse U, the output of the flip-flop 2 goes high and the output of the flip-flop 3 also goes high but the AND gate 5 is blocked during the second cycle by the absence of a sync signal at the point S and the AND gate 6 remains blocked. Once again, therefore, the signal passed on to the output V consists only of the pulses U. The circuit therefore automatically compensates for a missing sync signal. 
     In the case of the waveforms 31 to 30, the wide sync pulses are present but are out of phase with the pulses U and it is therefore necessary to resynchronize the counter 1. In addition, there are spurious signals on the line S which should be ignored. 
     At the leading edge of the pulse U, a spurious signal is present on the line S and consequently the flip-flop 2 changes to a low level. It is, however, unlikely that a spurious signal should always coincide with the pulses U and a case where there is no pulse present in shown in the second illustrated cycle. On this occasion, the output of the flip-flop 2 goes high. Furthermore, the flip-flop 3 is set by the pulse U and is not reset until some time later when the sync pulse is received and consequently a delayed signal, the width of which corresponds to the phase error, is produced at the point Q 2 . When this signal is compared with the incoming signal S in the AND gate 5, a pulse of width T is generated at the output of the gate 5 which is also passed by the gate 6 to the OR gate 7. The pulse R acts as a new synchronization signal and additional resets the counter 1 so as to bring the counter 1 back into phase with the received synchronization signals. 
     The circuit shown in FIG. 2 is generally similar to that of FIG. 1 and integers serving the functions already described have been allocated the same reference numerals and will not be described further. In FIG. 2, the reference numeral 60 designates a four bit presettable down counter, the inputs J i  of which are connected in parallel to the output Q 1  of the flip-flop 2 by way of an inverter 65 and to a first input of an OR gate 62. The clock input (CP) of the counter 60 is connected to the output of the AND gate 5 and to a first input of two AND gates 63 and 64, respectively. The reset input (PS) is connected to the output of the AND gate 63 while the outputs (QI) of the counter are connected to the four inputs of a NOR gate 61, the output of which is connected to a second input of the OR gate 62 and to a second input of the AND gate 64. The output of AND gate 64 is applied to the second input of the OR gate 7. 
     The operation of the circuit of FIG. 2 differs from that of FIG. 1 insofar as concerns the integers 60 to 65 which replace the gate 6. In the embodiment of FIG. 1, an output signal at the gate 5 coinciding with a high level at the point Q 1  would immediately reset the counter 1. However, to avoid a spuriously generated signal at the output of gate 5 having this effect, in the embodiment of FIG. 2, it takes a phase error detected in sixteen consecutive cycles to reset the counter 1. So long as Q 1  is low, a &#34;1&#34; is present at all the inputs of the counter 60 and this remains set to its maximum count. When the output at Q 1  goes high, the action of the inverter 65 is to apply a &#34;0&#34; to the inputs and consequently the counter 60 counts down with each input pulse from the AND gate 5 to its clock input (CP). When the counter has counted down sixteen consecutive pulses from the gate 5 indicating a phase error, the output count is zero and the NOR gate 61 produces a &#34;1&#34; output signal which acts on the gate 64 to reset the counter 1 and also to reset the counter 60 by way of the OR gate 62 and the AND gate 63. 
     The advantages of the present invention will be clear from the preceding description and in particular it will be noted that the invention provides circuits that are unaffected by random noise in addition to the normal sync pules or by the temporary omission of a sync pulse. The phase of the field frequency signal is very stable and well defined so that there is no vertical oscillation or trembling of the picture on the screen. 
     Phase is closely associated with the double-line-frequency clock so that interlacing of the two fields is perfect with consequent improvement in definition. 
     Performance in the presence of disturbance is even better on the FIG. 2 circuit in cases where there are disturbance and also missing synchronisms in that a delay is introduced by the circuit before synchronization is lost. 
     Many variations can be made: 
     For example, further selection can be made of the sync pulses (for example, on the basis of length using a shift register in the usual way) before they are sent to the inputs of flip-flops 2 and 3. 
     The 625 divider can be replaced by one with a different modulus in the case of standards with a different number of lines per frame, or it may even be a variable-modulus type in the case of multistandard receivers. OR gate 7 can be eliminated and the output picked up directly on terminal U of the divider in cases where temporary overscanning has no important effect on the operation of the vertical deflection stages. Counter 60 may be the up-down type designed for counting up and down depending on whether or not the output of counter 1 synchronisms coincide so as to get a proper average, etc.