Patent Publication Number: US-7711391-B2

Title: Multiple processor communication circuit cards and communication devices that employ such cards

Description:
TECHNICAL FIELD 
     Embodiments of the invention relate generally to the field of data and/or voice communication, and more particularly to communication circuit cards and communication devices that employ such cards. 
     BACKGROUND 
     In the current state of wireless communication, communication devices such as cellular telephones may employ communication circuit cards. Examples of such cards include subscriber identity module (SIM) cards that may be inserted into a slot of a communication device such as a Global System for Mobile Communications (GSM) compliant wireless mobile telephone. Typically, a SIM card is employed to store various subscriber information including information and/or algorithms needed to authenticate a subscriber to a network, personal directories, personal settings, and so forth. Conventional SIM cards typically include a processor and various memories such as volatile, nonvolatile, and Electrically Erasable Programmable Read Only Memory (EEPROM) memories. The dimensions (i.e., form factor) of these SIM cards including the locations of the input/output (I/O) terminals or contacts, the signaling protocols, and so forth, are typically dictated by communication standards, such as those set forth by the International Organization for Standardization and the International ElectroTechnical Commission (ISO/IEC), the 3 rd  Generation Partnership Project (3GPP), the GSM Consortium, and/or by other groups or agreements. 
     The term “wireless mobile phone” as used herein refers to the class of telephone devices equipped to enable a user to make and receive calls wirelessly, notwithstanding the user&#39;s movement, as long as the user is within the communication reach of a service or base station of a wireless network service provider. Unless specifically excluded, the term “wireless mobile phone” is to include the analog subclass as well as the digital subclass (of all signaling protocols). 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Embodiments of the invention are illustrated by way of example and not by way of limitation in the figures of the accompanying drawings, in which like references indicate similar elements and in which: 
         FIG. 1  illustrates a communication device and a multi-processor communication circuit card that fits into a slot of the communication device in accordance with various embodiments; 
         FIG. 2  illustrates a block diagram of a two-processor communication circuit card embodiment of the multi-processor circuit card of  FIG. 1 , in accordance with various embodiments; and 
         FIG. 3  illustrates a block diagram of the communication device of  FIG. 1 , in further detail, in accordance with various embodiments. 
     
    
    
     DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS 
     Illustrative embodiments of the present invention include communication circuit cards that employ at least two processors, or at least one processor and an attendant microcontroller, and communication devices that employ such cards, as well as methods for operating and communicating with such cards. 
     Various aspects of the illustrative embodiments will be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. However, it will be apparent to those skilled in the art that alternate embodiments may be practiced with only some of the described aspects. For purposes of explanation, specific numbers, materials, and configurations are set forth in order to provide a thorough understanding of the illustrative embodiments. However, it will be apparent to one skilled in the art that alternate embodiments may be practiced without the specific details. In other instances, well-known features are omitted or simplified in order not to obscure the illustrative embodiments. 
     Further, various operations will be described as multiple discrete operations, in turn, in a manner that is most helpful in understanding the illustrative embodiments; however, the order of description should not be construed as to imply that these operations are necessarily order dependent. In particular, these operations need not be performed in the order of presentation. 
     The phrase “in various embodiments” is used repeatedly. The phrase generally does not refer to the same embodiments; however, it may. The terms “comprising,” “having,” and “including” are synonymous, unless the context dictates otherwise. 
       FIG. 1  depicts the backside of a communication device and a multi-processor communication circuit card that fits into a slot in the communication device in accordance with various embodiments. For the embodiments, the communication device  100  may be a wireless mobile phone (also referred to as cellular telephone) such as a GSM compliant cellular phone having a slot  102  disposed within a backside opening  101  and for receiving a multi-processor communication circuit card  104  (herein “circuit card  104 ”) that includes at least two processors. The circuit card  104  may be a SIM card having a form factor complying with, for example, ISO/IEC, 3GPP, GSM consortium, or other standards. The circuit card  104  may include at least two processors (not depicted), a first and a second processor, and a plurality of I/O terminals  106  on the underside of the circuit card  104  as indicated by the dotted lines. Note, however, that in other embodiments, the circuit card  104  may include at least one processor and an attendant microcontroller. However, for ease of understanding, for the purpose of this application, the term “processor” shall be broadly construed to include controller, microcontroller and other elements of the like. The I/O terminals  106  make up the interface of the circuit card  104  that will couple with a core circuitry (not shown) of the communication device  100  via contacts  124 . Although nine terminals  106  are depicted, in other embodiments, more or fewer terminals may be present in the circuit card  104 . Further, while the circuit card  104  is depicted as engaging communication device  100  from its backside, in alternate embodiments, the circuit card  104  may engage with the communication device  100  via other locations. 
     In a conventional SIM card that is compliant with a communication standard such as ISO/IEC, 3GPP, GSM consortium, and/or other standards, only some of the I/O terminals of the conventional SIM card are currently being used while other terminals may be left unused. That is, used or dedicated terminals are terminals that are designated to be used for particular purposes specified by the standards. These include, for example, power, ground or reference, clock, input, and output signals. Unused or undedicated terminals are terminals that are not currently assigned for use in any particular way by the standards. It is contemplated, however, that in the future, more or all of the terminals of a SIM card may become used or dedicated terminals. 
     When the circuit card  104  is inserted into the slot  102  of the communication device  100 , the I/O terminals or simply terminals  106  will couple with corresponding contacts  124  disposed in the slot  102 . Each of the terminals  106  (as well as their corresponding contacts  124  on the communication device  100 ) may be dedicated or undedicated terminals in accordance with, for example, a communication standard (e.g., ISO/IEC, 3GPP, GSM consortium, or other standards). That is, in some embodiments, some of the terminals  106  and contacts  124  may be dedicated terminals and contacts while other terminals and contacts will be undedicated terminals and contacts. In other embodiments, however, all of the terminals  106  and contacts  124  may be dedicated terminals and contacts. 
     In brief, the communication device  100  may direct groups of signals to the circuit card  104  via one or more of the contacts  124  and one or more of the terminals  106 . As the circuit card  104  receives the groups of signals, each group of signals is routed to either the first or the second processor integrated into the circuit card  104  depending upon whether the first or the second processor is to receive the group. Each group of signals may include signals such as one or more inputs, power, clock, and so forth. In some embodiments, each signal of a group of signals may be received by the circuit card  104  during the same time increment. That is, for these embodiments, the signals of a group of signals may be received via, for example, different terminals at the same moment of time or substantially within the same time period. In other embodiments, however, the signals of a group of signals may be received during different points of time. 
       FIG. 2  depicts a block diagram of a two-processor communication circuit card embodiment of the multi-processor circuit card  104  of  FIG. 1 , in accordance with various embodiments. The circuit card  104 , which may be embodied in a substrate, may include a switch  202  that is coupled to a plurality of terminals  106 , and to a first and second processor  204  and  206 . The switch  202  may be any type of switching circuitry or any other type of device capable of selectively routing signals. The first processor  204  may be further coupled to a nonvolatile memory  208 , volatile memory  210 , and EEPROM  212 , via bus  214 . The second processor  206  may be further coupled to nonvolatile memory  207 , which may include customize logic. The non-volatile memory  207  may include data and/or instructions designed to personalize, customize, and/or enhance functions of a communication device that receives the circuit card  104 . Note that in alternative embodiments, the second processor  206  may be coupled to various other components such as volatile memory and/or EEPROM. In still other embodiments, the first and second processor  204  and  206  may be coupled to one or more common components (e.g., nonvolatile memory  208 , volatile memory  210  and EEPROM  212 ). In still other embodiments, additional components such as additional processors may be included in the circuit card  104 . In yet other embodiments, the second processor  206  may be replaced with an attendant microprocessor. 
     The first processor  204  may be a microprocessor such as those found in conventional single-processor SIM cards. In various embodiments, the first processor  204  may be adapted to implement or execute communication functions in accordance with a communication standard. These functions may include functions that may be typically performed by a processor of a conventional SIM card such as retrieving or storing subscriber information and retrieving personal telephone numbers. The communication standard, may be any communication standard (e.g., ISO/IEC, 3GPP, GSM consortium, or any other standard). 
     In contrast, the second processor  206  may be adapted to at least implement functions beyond communications functions specified by the communication standard of the first processor  204 . That is, the second processor  206  may perform functions that may not be typically performed by, for example, a conventional SIM card processor that performs communications functions in accordance with a communication standard. In some embodiments, when the circuit card  104  is coupled to a communication device  100 , the second processor  206  may increase the processing power of the communication device  100 , personalize and/or customize communication device  100 , or provide enhanced functions to communication device  100 . 
     In various embodiments, the switch  202  may be adapted to facilitate selective routing of signals received through one or more of the terminals  106  to either the first processor  204  or the second processor  206 . Note that the term “signals,” as used herein, is broadly defined and may mean a variety of signals including, for example, input signals, clock, power, and so forth. For the embodiments, the signals that are received may be grouped into groups of signals, each group directed to either the first or the second processors  204  and  206 . In order to properly channel each group of signals to the proper circuit card processor (e.g., first or second processor  204  and  206 ), the switch  202  may route each group of signals based on the logic endowed with the switch  202 . The term “group of signals” as used herein may refer to a single signal or a plurality of signals. Further note that the phrases “groups of signals” and “signal groups” are synonymous. 
     The switch logic may be integrated into the switch  202  or may be stored in nonvolatile memory such as flash memory that may be coupled to the switch  202 . At least two types of signal groups may be received through one or more terminals  106 . Those signal groups that are to be processed by the first processor  204  and those signal groups that are to be processed by the second processor  206 . The switch  202  may route a group of signals received through the terminals  106  based on various criteria. Various routing logic may be employed to properly route groups of signals to the proper processor (i.e., the first or the second processor  204  or  206 ). The use of a particular routing logic for routing groups of signals may depend on, in some circumstances, whether many, few, or no terminals are undedicated (i.e., unused) terminals, and if none of the terminals  106  are undedicated terminals, whether few or many signal patterns are undefined. In brief, unique signal patterns may form when one or more signals of a group of signals arrive at selected terminals during an increment of time or session. The formation of unique signal patterns may occur even when all of the terminals are dedicated terminals. The various routing logic used for properly routing groups of signals to the first or the second processor  204  or  206  will be described in greater detail below. Note that although the various routing logic described below are described as they relate to specific circumstances, those skilled in the art will recognize that they may be applied in other circumstances. 
     In various embodiments, when a group of signals is initially received through one or more of the terminals  106 , the switch  202  may be adapted to initially make a determination whether the entire group of signals is received either through a first or a second type of one or more terminals  106 . Based on this determination, the switch  202  may route the group of signals to either the first or the second processor  204  and  206 . For the embodiments, the first type of one or more terminals may be dedicated or used terminal(s) in accordance with, for example, a communication standard (e.g., ISO/IEC, 3GPP, GSM consortium, or other standards), while the second type of one or more terminals may be undedicated or unused terminal(s) in accordance with, for example, the communication standard. If an entire group of signals is received through the first type of one or more terminals, then the switch  202  may direct the group of signals to the first processor  204 . On the other hand, if the entire group of signals is received through the second type of one or more terminals then the switch  202  may direct the group of signals to the second processor  206 . 
     In other embodiments, the switch  202  may be adapted to make a determination whether at least one signal from the group of signals is received through the second type of one or more terminals (e.g., undedicated terminals). If at least one signal from the group of signals is received through the second type of one or more terminals, then the switch  202  may route the entire group of signals to the second processor  206 . If, on the other hand, no signals from the group of signals are received through the second type of one or more terminals, then the switch  202  may route the entire group of signals to the first processor  204 . 
     In still other embodiments in which, for example, all or substantially all terminals  106  are used by the communication standard, and sufficient combinations of the terminals  106  remain undefined by the communication standard, and are available to form an augmenting communication protocol for the communication device  100  to communicate with the second processor  206 , one or more of the signals from the group of signals may include one or more corresponding identifier tags (defined by particular combinations of the terminals  106 ) to denote communication with the second processor  206 . For these embodiments, the switch  202  may be adapted to examine the signal pattern of a group of signals depicted by the relevant combinations of terminals that the one or more signals of the group of signals are received through, and the identifier tag or tags included with the one or more signals, to determine whether the received group of signals is to be routed to the second processor  206 . 
     In various embodiments, one or more undefined signal patterns may be associated with a group of signals received through the terminals  106  even in situations whereby all of the terminals  106  are dedicated terminals. This is because, although all of the terminals  106  may be dedicated, not all of the terminals  106  will actually be used at all times. For example, by employing headers, incorporated with identifier tag or tags into, unique signaling patterns may be depicted. These unique signaling patterns may designate that a group of signals is to be routed to the first processor  204  or to the second processor  206 . 
     Based on the determination, the switch  202  may route the group of signals to either the first or the second processor  204  or  206 . In some embodiments, if the signals of a group of signals include data packets, then the identifier tags may be included in the header of the data packets. 
     In still other embodiments in which, for example, all or substantially all of the terminals  106  are used by the communication standard, and insufficient combinations of terminals  106  remain undefined by the communication standard for use to form an augmenting communication protocol for communication device  100  to communicate with second processor  206 , two combinations of signals at one or more terminals  106  may define a first and a second signal pattern to denote a start and an end of communication session with second processor  206 . In other words, the switch  202  is adapted to route all signals to second processor  206  after receiving signals at the particular combination of terminals  106  denoting the beginning of a communication session with second processor  206 , until after receiving signals at the same or other particular combination of terminals  106  denoting the end of a communication session. Switch  202  routes received signals to first processor  204  in all other times. 
       FIG. 3  depicts a block diagram of the communication device  100  of  FIG. 1 , in further detail, in accordance with some embodiments. For the embodiments, the communication device  100  may include core circuitry  302  that is coupled to an antenna (not shown), I/O devices  304 , and contacts  124 . The I/O devices  304  may be, for example, a key pad, display, and so forth. The core circuitry  302  may include processor(s)  306  including a digital signal processor (DSP), volatile memory  308 , nonvolatile memory  310 , EEPROM  312 , transceiver  314 , and bus  316 . The core circuitry  302  may be adapted to selectively direct and/or receive signals to and from one or more of the contacts  124 . Note that although specific components are depicted as being included in the core circuitry  302 , in another embodiments, one or more of the components depicted may be absent. Further, additional components not depicted may be included in the core circuitry  302 . Further still, one or more of the core circuitry components depicted may be replaced with alternative equivalent or nonequivalent components. 
     In various embodiments, the core circuitry  302  may be adapted to direct groups of signals to the contacts  124  or receive groups of signals from the contacts  124 . The groups of signals to be directed may be groups of signals received through the transceiver  314  or may be internally generated by the communication device as a result of, for example, input from a user or internally generated by, for example, the processor(s)  306 . In some embodiments, the core circuitry  302  may be adapted to direct or receive one or more signals of a group of signals, or both, to and from selective contacts in order to facilitate the directing or receiving groups of signals to and from a first processor  204  or a second processor  206  of a circuit card  104 . In various embodiments, the core circuitry  302  is adapted to determine whether a received circuit card  104  has a second processor  206  in addition to the first processor  204  of the circuit card  104 . 
     In various embodiments, the core circuitry  302  may be adapted to selectively communicate with the first and second processors  204  and  206  of a received circuit card  104  by selectively directing signals to or receiving signals from I/O terminals  106  that are used or unused by a communication standard, on determining whether a circuit card  104  inserted into the slot  102  of the communication device  100  has a second processor  206 . If it is determined that the inserted circuit card  104  does not include a second processor  206 , the core circuitry  302  may communicate with the circuit card  104  in a, for example, conventional manner. 
     In yet other embodiments, as described earlier in which, for example, all or substantially all terminals  106  are used by the communication standard, and sufficient combinations of the terminals  106  remain undefined, and are available for defining an augmenting communication protocol, the core circuitry  302 , on determining the presence of second processor  206 , may direct signals to the second processor  206  by including in a subsets of signals identifier tags (defined by certain otherwise undefined combinations of terminals  106 ). Similarly, core circuitry  302  may be further adapted to recognize received signals as having been sent by second processor  206  by detecting for presence of the identifier tags (defined by certain otherwise undefined combinations of terminals  106 ). 
     In yet other embodiments, as described earlier in which, for example, all or substantially all terminals  106  are used by the communication standard, and insufficient combinations of the terminals  106  remain undefined for defining an augmenting communication protocol, the core circuitry  302  may be adapted to direct or receive signals to the second processor  206  after first directing signals to, or receiving signals from a combination of terminals  106  denoting the start of a communication session with the second processor  206 , on determining the presence of second processor  206  in the received circuit card  104 . The core circuitry  302  would be further adapted to direct signals to, or receive signals from the same or another combination of terminals  106  denoting the end of a communication session with the second processor  206 . 
     Accordingly, multi-processor communication circuit cards and communication devices that employ such cards have been described in terms of the above-illustrated embodiments. It will be appreciated by those of ordinary skill in the art that a wide variety of alternate and/or equivalent implementations calculated to achieve the same purposes may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. Those of ordinary skill in the art will readily appreciate that the present invention may be implemented in a very wide variety of embodiments. This description therefore is intended to be regarded as illustrative instead of restrictive on embodiments of the present invention.