Patent Publication Number: US-2023161516-A1

Title: Control method for requesting status of flash memory, flash memory system

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     The present application is a continuation application of and claims the priority benefit of U.S. application Ser. No. 17/138,644, filed on Dec. 30, 2020. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification. 
    
    
     TECHNICAL FIELD 
     The invention relates to a flash memory, and in particular to a control method of a flash memory and a flash memory system. 
     DESCRIPTION OF RELATED ART 
     Currently, the NAND flash memory controllers are facing a significant increase in the number of NAND flash memory dies to be controlled, which results in an increase in the number of pads of the controller and the size of the die will also increase. In addition, the ready/busy (R/B) signals of all logic units are also connected to a shared R/B signal line. Therefore, if it needs to confirm which logical unit is busy when the shared R/B signal line is busy, a “read status command” has to be issued to inquire whether the specified logical unit is ready or busy. 
     Generally speaking, the implementation of the R/B state of NAND flash memory uses an open drain design.  FIG.  1    shows a schematic circuit diagram of an open drain of a NAND flash memory. As shown in  FIG.  1   , there are multiple NAND flash memory dies  0 ,  1 ,  2 , . . . in one channel and the R/B status outputs are connected to a common open drain output, respectively.  FIGS.  2 A and  2 B  illustrate that two current design methods for the multi-channel NAND flash memory. 
     As shown in  FIG.  2 A , in this configuration, the R/B signal line of each NAND flash die in each channel is independent, that is, each flash memory die  10 _ 0 ˜ 10 _m- 1  is provided with an R/B signal line to connect to the flash memory controller  20 , and therefore, in each channel, the number of the pads of the flash memory controller  20 , which corresponds to the number of the R/B signal lines, has to be also provided. 
       FIG.  2 B  illustrates another configuration of a NANA flash memory. As shown in  FIG.  2 B , in this configuration, each flash memory die  10 _ 0 ˜ 10 _m- 1  in each channel shares an R/B signal line, that is, is shorted together. However, under this configuration, the flash memory controller  20  may not confirm which NAND flash memory die  10 _ 0 ˜ 10 _m- 1  is busy, and additional time must be spent to confirm the read/busy status of each flash memory die  10 _ 0 ˜ 10 _m- 1 . In other words, in this configuration, although the number of pads can be reduced, additional time is required to confirm the R/B status of each flash memory die  10 _ 0 ˜ 10 _m- 1 . 
     Therefore, there is a need in the art that can reduce the number of pads and no additional time is required to confirm which flash memory die is busy. 
     SUMMARY 
     According to an embodiment, the disclosure provides a control method for a flash memory, wherein the flash memory includes an external data bus to which a plurality of flash memory dies are coupled. The control method comprising: in a setup stage, under an operation mode of command input, issuing by a host controller a setup command, wherein the setup command comprises mapping information that each of ports of the external data bus is mapped respectively to a status index of each of the plurality of the flash memory dies; and in a request stage, under the operation mode of command input, issuing by the host controller a request command to each of the plurality of flash memory dies, and under the operation mode of data output, in response to the request command, transmitting a status of the status index of each of the plurality of the flash memory dies to the host controller through each of the ports of the external data bus respectively. 
     According to another embodiment, the present disclosure provides control method for a flash memory, wherein the flash memory includes an external data bus to which a plurality of flash memory dies are coupled, the control method comprising: issuing by a host controller a setup command, wherein the setup command comprises mapping information that each of ports of the external data bus is mapped respectively to a status index of each of the plurality of the flash memory dies; issuing by the host controller a request command to each of the plurality of the flash memory dies. In response to the request command received from the host controller, each of the plurality of the flash memory dies in each channel is configured to transmit a status of the status index of each of the plurality of the flash memory dies is transmitted to the host controller through each of the ports of the external data bus respectively. 
     According to another embodiment, the present disclosure provides a flash memory system, comprising: at least one external data bus having a plurality of ports; a plurality of flash memory dies respectively coupled to the at least one external data bus; and a host controller, coupled to the at least one external data bus and configured to control the plurality of the flash memory dies. The host issues a setup command, wherein the setup command comprises mapping information that each of the ports of the external data bus is mapped respectively to a status index of each of the plurality of the flash memory dies. The host controller issues a request command to each of the plurality of the flash memory dies, and in response to the request command, each of the plurality of the flash memory dies, a status of the status index of each of the plurality of flash memory dies is transmitted to the host controller through each of the ports of the external data bus respectively. 
     According to another embodiment, the present disclosure provides a flash memory system. The flash memory system comprises at least one external data bus having a plurality of ports; a plurality of flash memory dies; and a host controller. The plurality of flash memory dies are respectively coupled to the at least one external data bus, wherein each of the flash memory dies has a plurality of output ports respectively coupled to each of the ports of the external data bus. The host controller is coupled to the at least one external data bus. The host controller is configured to issue a setup command, wherein the setup command comprises mapping information that each port of the external data bus is mapped respectively in association with the setup command to each of the plurality of the flash memory dies. Each of the plurality of flash memory dies further comprises: a first multiplexor, a demultiplexor and a second multiplexor. The first multiplexor is configured to selects one of a plurality of inputs thereof and to output the selected input to the external data bus according to a selection signal, and the plurality of the inputs are coupled to at least an internal data bus, a status index bus and a mapping status bus. The demultiplexor is configured to receive configured to receive a status index of each of the plurality of the flash memory dies, wherein outputs of the demultiplexor are coupled to the mapping status bus of the first multiplexor. In response to a request command from the host controller, the demultiplexor is configured to select one of the outputs based on the mapping information to transmit the status index of the status index of each of the plurality of the flash memory dies to the host controller through the selected output port. The second multiplexor is coupled to an input of the demultiplexor and configured to select the status index from a plurality of status indices based on status select information. 
     In summary, under the configuration of the embodiment, the vendor-specific commands and data bus are used to substitute the R/B signal line of flash memory die, and therefore, the original R/B signal lines and pads of each flash memory die can be reduced, so that the multi-channel flash memory controller correspondingly does not require the R/B pad. Therefore, the number of pads of the controller can be effectively reduced. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The accompanying drawings are included to provide a further understanding of the disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the disclosure and, together with the description, serve to explain the principles of the disclosure. 
         FIG.  1    is a schematic diagram of an open drain output of a conventional multi-channel NAND flash memory die configuration. 
         FIG.  2 A  and  FIG.  2 B  are schematic diagrams of the conventional multi-channel NAND flash memory configuration. 
         FIG.  3 A  is a schematic diagram of a multi-channel flash memory configuration according to an embodiment of the disclosure. 
         FIG.  3 B  is a schematic structural diagram of a NAND flash memory die according to an embodiment of the disclosure. 
         FIGS.  3 C and  3 D  further illustrates a schematic diagram of circuit configuration for the I/O control unit and the control logic unit of the NAND flash memory die. 
         FIG.  3 E  is a circuit configuration of the demultiplexor shown in  FIG.  3 D . 
         FIG.  4 A  is a schematic structural diagram of a NAND flash memory die according to another embodiment of the disclosure. 
         FIG.  4 B  illustrates a schematic diagram of circuit configuration for the I/O control unit of  FIG.  4 A . 
         FIG.  5    illustrates a schematic diagram of another circuit configuration for the I/O control unit of  FIG.  4 A . 
         FIG.  6 A  is a timing diagram illustrating an operation flow of each flash memory die of a control method of a NAND flash memory according to an embodiment of the disclosure. 
         FIG.  6 B  is a timing diagram illustrating an operation flow of each flash memory die of a control method of a NAND flash memory according to another embodiment of the disclosure. 
         FIG.  7 A  shows a schematic diagram of an operation flow for the host controlling the NAND flash memory dies on the channel. 
         FIG.  7 B  is a schematic diagram of another operation flow for the setting stage of FIG.  7 A. 
         FIG.  8    is a schematic diagram illustrating the operation timing of the multi-channel flash memory controller according to an embodiment of the disclosure. 
     
    
    
     DESCRIPTION OF THE EMBODIMENTS 
       FIG.  3 A  is a schematic diagram of a multi-channel flash memory configuration according to an embodiment of the disclosure.  FIG.  3 B  is a schematic structural diagram of a NAND flash memory die according to an embodiment of the disclosure, that is, a schematic structural diagram of each NAND flash memory die in each channel in  FIG.  3 A . Although  FIG.  3 A  shows a multi-channel flash memory configuration, but the embodiment will describe an example of one channel flash memory configuration. The method or configuration may be applicable to one channel or multi-channel flash memory configuration. 
     As shown in  FIG.  3 A , a multi-channel NAND flash memory controller  200  or a host  200  can be connected with n channels ( 0 ˜n- 1 ) of flash memory dies. Each channel can comprise a plurality of flash memory dies. For example, there are m NAND flash memory dies  100 _ 0 ˜ 100 _m- 1  in each of the flash memory channels  0 ˜n- 1 . In addition, each of the m NAND flash memory dies  100 _ 0 ˜ 100 _m- 1  of each channel has at least chip enable signals (chip enable) CE_ 0 ˜CE_m- 1 , which are respectively connected to the multi-channel NAND flash memory controller  200 . In addition, the input/control unit of each NAND flash memory die  100 _ 0 ˜ 100 _m- 1  can transmit data to and receive data from the multi-channel NAND flash memory controller  200  through a data bus (an external data bus) DQ. 
     Furthermore, as shown in  FIG.  3 A , in this configuration, each NAND flash memory die  100 _ 0 ˜ 100 _m- 1  does not use R/B pads as in the prior art to transmit the ready and busy (R/B) status (a status index signal) corresponding to each NAND flash memory die  100 _ 0 ˜ 100 _m- 1 . According to an embodiment of the present disclosure, each port of the data bus DQ (using 8 ports as an example, such as DQ [7:0]) is used to transmit the R/B signal for each NAND flash memory die  100 _ 0 ˜ 100 _m- 1 . The data bus DQ may be referred as an external bus. In other words, in the embodiment, the internal R/B port is mapped to a designated DQ port to perform R/B status detection of the NAND flash memory dies  100 _ 0 ˜ 100 _m- 1 . 
     The status index here may be various internal states, parameters, etc. of the flash memory dies of each channel, such as ready/busy for host, ready/busy for flash array. In this embodiment, the ready/busy state for host (R/B for host) will be used as an example of the status index. In this way, this embodiment will not use external R/B pads and signal lines, so the number of pads of the controller can be reduced. The detailed operation flow will be described in detail later. The R/B for host status indicates whether the data buffer (such as the data buffer  118  in  FIG.  3 B ) of the flash memory die is empty for receiving next data transmitted from the host, but the data is not yet written to the memory array. The R/B for flash array status indicates whether the data is written to the memory array. 
       FIG.  3 B  is a schematic structural diagram of a NAND flash memory die according to an embodiment of the disclosure. As shown in  FIG.  3 B , the NAND flash memory die  100 _ 0  (the structure of the NAND flash memory dies  100 _ 1 ˜ 100 _m- 1  is the same) is basically the same as the structure of the general NAND flash memory die, the difference is in that circuit blocks for mapping the R/B signal lines to the DQ ports are provided. 
     As shown in  FIG.  3 B , the NAND flash memory die  100 _ 0  of the embodiment is also provided with basic circuit blocks, such as a control logic unit (control logic)  102 , an I/O control unit (I/O control interface)  104 , a memory array  120 , an X-decoder  124 , a Y-decoder  122 , and page buffer  126 , the high voltage circuit  110 , a command register  112 , an address register  114 , a status register  116 , a data buffer  118 , and a data bus DQ. The functions and operations of the basic circuit blocks of the NAND flash memory dies  100 _ 0  are basically the same as or similar to the existing architecture, and the actual architecture does not affect the implementation of this embodiment, so detailed descriptions are omitted here. 
     According to the present embodiment, the NAND flash memory die  100 _ 0  has at least a mapping status register  106 , and in this embodiment an example of R/B mapping to DQ port is used. The mapping status register  106  can store a value that is a one-to-one mapping relationship between each port DQ 0 ˜DQ 7  of the data bus DQ respectively to the R/B signal lines of the NAND flash memory dies  100 _ 0 ˜ 100 _m- 1 . Namely, the mapping status register  106  of the NAND flash memory die  100 _ 0  stores data that indicates which DQ port will be assigned to the R/B signal lines of the NAND flash memory dies  100 _ 0  for outputting the R/B for host status. For example, if the NAND flash memory dies  100 _ 0  will use the DQ 0 , data stored in the mapping status register  106  of the NAND flash memory die  100 _ 0  may be a value of “0”, which is the same for other NAND flash memory die  100 _ 1 ˜ 100 _m- 1 . Each NAND flash memory die only stores the DQ port to be used in the mapping status register  106 . In addition, the host (flash memory controller  200 ) may be provided with a correspondence table recording that each port (DQ [7:0]) is used to output the status indicator of which NAND flash die. 
     In this way, when the multi-channel NAND flash memory controller  200  issues a request signal (refer to a request stage to be detailed later) to each flash memory die  100 _ 0 ˜ 100 _m- 1  in order to acquire the status of the R/B signal line, the I/O control unit  104  of each flash memory die  100 _ 0 ˜ 100 _m- 1  can issue an R/B signal at the corresponding DQ port. In this way, the multi-channel NAND flash memory controller  200  can acquire once the status of the R/B signal line of each flash memory die  100 _ 0 ˜ 100 _m- 1  from each port DQ 0 ˜DQ 7  on the data bus DQ. 
     With the above structure, the logic control unit  102  does not require to use the internal R/B signal to transmit the R/B status through the R/B pads of the I/O control unit  104 , and therefore the external R/B signal lines and pads are not required. Thus, the R/B pads of the multi-channel NAND flash memory controller  200  are also not required, and the number of pads can be reduced. As shown by the dashed-line in the lower left corner of  FIG.  3 B , this embodiment can completely omit this part of the hardware structure. 
       FIGS.  3 C and  3 D  further illustrate a schematic diagram of the hardware structure of I/O control unit  104  of the present embodiment of  FIG.  3 B . The NAND flash memory die shown in  FIGS.  3 C and  3 D  only depicts circuit blocks related to this embodiment, and the other portions are omitted. As shown in  FIG.  3 C , the I/O control unit  104  may further include a multiplexor (first multiplexor)  131  having a plurality of internal buses as inputs thereof. For example, each internal bus can include  8  signal lines. Through the internal buses, the multiplexor  131  can select one of the inputs thereof, i.e., one of the internal data buses (for general data transmission), the status bus (transmission of status index of flash memory die) and the mapping status bus (such RB to DQ port) can be selected to output through the port (DQ [7:0]) according to a selection signal line of the logic control unit  102 . The DQ bus can output various output signals, such as data status of the flash memory die or the R/B status (i.e., R/B to DQ port) of the embodiment. In this embodiment, the R/B for host status is used as an example. In addition, the mapping status register  106  stores data for indicating which port is used to output the R/B status. As shown in  FIG.  3 D , the demultiplexor  130  has an input, outputs and a select line. The output of the demultiplexor  130  and one of the inputs of the multiplexor  131  are coupled through the mapping status bus ([7:0]). The input of the demultiplexor  130  receives the R/B for host from the mapping status register  106 . The demultiplexor  130  receives the data stored in the mapping status register  106  through the select line so as to output the status of the R/B for host of the flash memory die through the corresponding port (one of the mapping status bus ([7:0])). Therefore, the multiplexor  131  in  FIG.  3 C  can select the corresponding port to output the status of the R/B for host. 
     In addition,  FIG.  3 E  shows a schematic diagram of a circuit configuration of the demultiplexor  130  in  FIG.  3 D . As shown in  FIG.  3 E , the DEMUX  130  further comprises a decoder  130   a  and a plurality of pass gates. In the embodiment, a tri-state gate is used as an example for the pass gate. The tri-state gates  130   b _ 0 ˜ 130   b _ 7  (8 tri-state gates are used to correspond to the DQ port [7:0] respectively in this embodiment). The output of each tri-state gate  130   b _ 0 ˜ 130   b _ 7  is coupled to its corresponding DQ port DQ [7:0]. The decoder  130   a  may receive and decode the data from the mapping status register  106 , and thereby the R/B for host status input to the DEMUX  130  may pass through the corresponding tri-state gate (one of the tri-state gate  130   b _ 0 ˜ 130   b _ 7 ) and is output from the corresponding DQ port DQ [7:0]. For example, if the NAND flash memory die  100 _ 1  uses the DQ port DQ 1  for outputting the R/B for host status, the mapping status register  106  may store data of a value “1”. For example, when a value of the data stored in the mapping status register  106  is 1, it means that the DEMUX  130  decodes the value to a signal of 0000_0010 by the decoder  130   a , and then the tri-state gates  130   b _ 0 ˜ 130 _ 7  enables the port DQ 1  based on the received signal 0000_0010 and the other ports become high impedance status. Namely, the S/B for host status is output through DQ 1 . At this time, the decoder  130  makes the tri-state gate  130   b _ 1  to be enabled and the other tri-state gate  130   b _ 0 , 130   b _ 2 ˜ 130   b _ 7  to be disabled to be in the high impedance status, so that the multiplexor  131  in  FIG.  3 C  may select the DQ 1  to output the R/B for host status. 
     In the embodiment, each NAND flash memory die only selects one DQ ports as the output for outputting the status index (the R/B for host status in this embodiment. On the other hand, the other DQ ports of the NAND flash memory die are in a status of high impedance. 
     As described above, the status of the internal R/B signal line can be transmitted to the NAND flash memory controller  200  by using the corresponding DQ port through the data bus DQ. For example, the R/B signal line of the flash memory die  100 _ 0  is mapped to the DQ port DQ 0 , and the R/B signal line of the flash memory die  100 _ 1  is mapped to the DQ port DQ 1 . 
     Therefore, in this way, for each channel of multiple flash memory dies  100 _ 0 ˜ 100 _m- 1 , the multi-channel NAND flash memory controller  200  can obtain the R/B status of multiple flash memory dies  100 _ 0 ˜ 100 _m- 1  at a time on the data bus DQ through the DQ ports DQ 0 ˜DQ 7 . Therefore, the NAND flash memory controller  200  does not require additionally the external R/B signal lines and pads, which the number of the pads of the controller can be effectively reduced. 
       FIG.  4 A  is a schematic diagram showing a configuration of a NAND flash memory die according to another embodiment, and  FIG.  4 B  is a schematic diagram showing a circuit configuration of the I/O control unit in  FIG.  4 A . As shown in  FIG.  4 A , in addition to the mapping status register  106   a , the I/O control unit  104  further includes a status select register  106   b  is further included. The data (mapping information) stored in the mapping status register  106   a  may hint the NAND flash memory die  100 _ 0  ( . . .  100 _m- 1 ) that which port among the DQ port [7:0] will be used to output the status index (such as the R/B for host status), and the data (status selection information) stored in the status select register  106   b  may hint the NAND flash memory die  100 _ 0  ( . . .  100 _m- 1 ) that which status index will be selected to be output. 
     In the above description related to  FIGS.  3 B to  3 E , one status index is used as an example, that is, the R/B for host status. However, as mentioned above, the application of the present disclosure is not limited to the R/B for host status, but can be other status indices or parameters of the NAND flash memory die  100 _ 0  ( . . .  100 _m- 1 ). In other words, in this embodiment, one of the plurality of status indices of the NAND flash memory die  100 _ 0  ( . . .  100 _m- 1 ) may be selected to be output through the corresponding DQ port. 
     As shown in  FIG.  4 B , in the configuration of this embodiment, in addition to the DEMUX  130 , a multiplexor  132  (second multiplexor) is further included. In addition, the logic control unit  102  may further include a plurality of status registers, and one of the status registers may be selected to output to the multiplexor  132 . The multiplexor  132  may receive plural statuses from the plurality of status registers, such as the R/B for host, the R/B for flash array and other status. In addition, the multiplexor  132  is further coupled to the status select register  106   b . The multiplexor  132  may select one of the status registers such as the R/B for host, the R/B for flash array and other status based on the data received from the status select register  106   b . Therefore, the DEMUX  130  can output the status selected by the status select register  106   b  from the corresponding port according to the data stored in the mapping status register  106   a.    
     As shown in  FIG.  4 B , the multiplexor  132  is coupled to the DEMUX  130 . The status index selected by the multiplexor  132  is input to the DEMUX  130 . The operation of the DEMUX  130  is the same as the DEMUX  130  in  FIGS.  3 D and  3 E . The DEMUX  130  may receive and decode the data from the mapping status register  106   a . In this way, the status index selected by the multiplexor  132  may be output from the corresponding DQ port (selected by the multiplexor  131  in  FIG.  3 C ) assigned by the data stored in the mapping status register  106   a . Therefore, the multiplexor  132  may select one of the plural status indices to use the data bus DQ to transmit the status. 
     Namely, as shown in  FIG.  4 B , according to the signal of the status select register  106   b  as a selection line, the multiplexor  132  selects, as an output, one from the R/B for host status, R/B for flash array status and other status. For example, the multiplexor  132  selects the R/B for flash array status as a status to be output according to the selection of the status select register  106   b . At this time, the DEMUX  130  receives the signal (i.e., the R/B for flash array status) output from the multiplexor  132 , and selects port 6 (an example) based on decoding the data of the mapping status register  106   a . In this example, in the output results of eight ports of the DEMUX  130 , the ports 0˜5 and 7 are in high impedance status, and the port 6 is used to output the R/B for flash array status. 
     Next, according to the selection line of the control logic unit  102 , the multiplexor  131  ( FIG.  3 C ) uses the output (the port 6 for outputting the R/B for flash array status, the other ports are in high impedance status) of the eight ports of the DEMUX  130  as one of selections of the multiplexor  131 . If the host issues the request command according to the embodiment, the port in the output of the eight ports of the DEMUX  130  will be selected as the output DQ [7:0]. 
     According to this variation example, the DQ port of the data bus DQ are not only limited to map to a single status index, but can be dynamically controlled by the host, that is, the multi-channel NAND flash memory controller  200  to select the required status index to transmit status through the data bus DQ, and therefore, the control of the NAND flash memory die can be operated more flexibly. Except for the multiplexor  132 , the DEMUX  130  operates in the same manner as in  FIGS.  3 D to  3 E , so their corresponding descriptions are omitted. 
       FIG.  5    is a schematic diagram showing a circuit configuration of an I/O control unit of the flash memory die according to another embodiment. As shown in  FIG.  5   , the circuit configuration of the demultiplexor and the multiplexor are different from those shown in  FIG.  4 B . Referring to  FIG.  5   , the DEMUX  130 ′, for example, includes decoder  130   a ′ and a plurality of tri-state gates  130 ′ b _ 0 ˜ 130 ′ b _ 7  (8 tri-state gates are depicted as an example), and the decoder  130 ′ a  is further coupled to each tri-state gate  130 ′ b _ 0 ˜ 130 ′ b _ 7 . The multiplexor unit  132 ′ further includes a decoder  132 ′ a  and a plurality of multiplexors  132 ′ b _ 0 ˜ 132 ′ b _ 7  (for example, 8) multiplexors), and the decoder  132 ′ a  is further coupled to each multiplexor  132 ′ b _ 0 ˜ 132 ′ b _ 7 . Each multiplexor  132 ′ b _ 0 ˜ 132 ′ b _ 7  of the multiplexor unit  132 ′ is respectively coupled to the tri-state gates  130 ′ b _ 0 ˜ 130 ′ b _ 7  of the DEMUX  130 ′. In addition, each multiplexor  132 ′ b _ 0 ˜ 132 ′ b _ 7  receives plural statuses from a plurality of status registers, such as the R/B for host, the R/B for flash array and other status. 
     The decoder  132 ′ a  of the multiplexor unit  132 ′ receives and decodes the data from the status select register  106   b , and thereby each of the multiplexors  132 ′ b _ 0 ˜ 132 ′ b _ 7  may select one of the status registers input thereto. For example, the multiplexor  132 ′ b _ 0  may select one of the status registers such as the R/B for host, the R/B for flash array and other status and then provides the selected status index to the corresponding tri-state gate  130 ′ b _ 0 , the multiplexor  132 ′ b _ 1  may also select and provide one status index to the corresponding tri-state gate  130 ′ b _ 1 , and the others are the same. In addition, the decoder  130 ′ a  of the DEMUX  130 ′ may receive and decode the data from the mapping status register  106   a , so that the corresponding tri-state gates  130 ′ b _ 0 ˜ 130 ′ b _ 7  are enabled and the status indices may be respectively output through the corresponding DQ port [7:0]. 
     For example, the DEMUX  130  will select which ports are used to output the status, and the other ports are in the high impedance status. As an example, if the decoded result of the decoder  130 ′ a  is 0000_1100, it means that the ports 2 and 3 are used to output status and the other ports are in the high impedance status. In addition, the status select register  106   b  stores the status to be output for each port. The multiplexor (the second multiplexor)  132 ′ will determine that each port of the 8 ports will select which status as its output. For example, if the decoded result of the decoder  132 ′ a  is 111_1211 and assumes “1” represents the R/B for host status and “2” represents the R/B for flash array, the port 2 of the eight ports of the multiplexor  132 ′ is used to output the R/B for flash array status and the other ports (i.e., the ports 0-1, 3-7) are used to output the R/B for host status. As a result, the multiplexor  131  (see  FIG.  3 C ) select the eight ports are that the port 2 is for outputting the R/B for flash array status, the port 3 is for outputting R/B for host status, and the other 6 ports are in the high impedance status. 
     In this embodiment, in comparison with the case that one flash memory die only assigns one DQ port to output the status index as shown in  FIG.  3 E , one flash memory die may assign multiple DQ ports respectively corresponding to one status index. Therefore, for one flash memory die, the status indices may be output through the corresponding DQ ports at the same time. In this embodiment, since the flash memory die may output multiple status indices, a corresponding relationship between the status indices and DQ ports will be stored in the status select register  106   b  in a certain data format. 
     Next, the operation method of the above-mentioned circuit configuration will be described, and referring to  FIGS.  6 A to  6 C , how the DQ ports of the data bus DQ are mapped to the R/B signal lines will be described in details. Here,  FIGS.  6 A to  6 C  are diagrams for explaining the timing of operations after the flash memory die receives the command from the host. 
       FIG.  6 A  is a timing diagram illustrating an operation flow of each flash memory die of a control method of a NAND flash memory according to an embodiment of the disclosure, which is a timing diagram for the flash memory die level. As shown in  FIG.  4 A , the control method of this embodiment divides the operation mode of the data bus DQ into two stages, namely a setup stage and a request stage. This embodiment mainly uses the time period when the data bus DQ is in an idle state. In this example, the data bus DQ has 8 ports as an example DQ 0 ˜DQ 7 , but could be properly modified on demand for NAND flash memory die. In addition, the operation for host level will be explained with reference to  FIG.  7 A . 
     As shown in  FIG.  6 A , in the setup stage, under the operation mode of CMD input (based on the specification of data transmission of the data bus DQ), at this time, the cycle type is to set the R/B command, i.e., when each NAND flash memory die  100 _ 0  ( . . .  100 _m- 1 ) receives a setup command issued by the NAND flash memory controller (host)  200 , and then each port DQ 0 ˜DQ 7  of the data bus DQ is assigned to correspond to the R/B status (status index) of each flash memory die  100 _ 0 ˜ 100 _m- 1  in the channel of the flash memory. 
     Here, the setup command may use vendor-specific commands to respectively correspond to the ports DQ 0 ˜DQ 7  of the data bus DQ of the NAND flash memory dies  100 _ 0 ˜ 100 _m- 1  of each channel. For example, a general NAND flash memory die  100 _ 0 ˜ 100 _m- 1  can be provided with 8 different vendor-specific commands, and each vendor-specific command can correspond to a specific DQ port. For example, command  20   h  can be assigned to port DQ 0 , command  21   h  can be assigned to port DQ 1 , and so on. In this way, different vendor-specific commands can be used to assign correspondingly to each port. That is, as shown in  FIG.  6 A , under the cycle type of setting the R/B command, the internal chip enable signal CE# enables the die, and a command  20   h  is issued at DQ [7:0] of the data bus DQ. 
     In this way, through the setup stage, the vendor-specific commands can be used to map each port DQ 0 ˜DQ 7  one-to-one to the internal R/B signal line of each NAND flash memory die, and the data (value) for indicating the corresponding relationship is stored in the R/B to DQ port correspondence register  106  shown in  FIGS.  3 B to  3 E . 
     For the host level, in the setup stage, the operation flow diagram is shown in step S 100  of  FIG.  7 A , under the operation mode of command input, the host (such as flash memory controller  200 ) issuing the setup command, so that each port DQ 0 ˜DQ 7  of the data bus of each of the plurality of flash memory dies  100 _ 0 ˜ 100 _m- 1  is respectively mapped to the status index (R/B status) of each of the flash memory dies  100 _ 0 ˜ 100 _m- 1 . 
     Referring again to  FIG.  6 A , then in the request stage, each NAND flash memory die  100 _ 0  ( . . .  100 _m- 1 ) receives a request command issued by the NAND flash memory controller  200 , i.e., another vendor-specific command is issued to each of the NAND flash memory dies  100 _ 0 ˜ 100 _m- 1 . 
     In the request stage, as shown in  FIG.  6 A , when the operation mode is command input, at this time, the cycle type is to request R/B command, i.e., the multi-channel NAND flash memory controller  200  issues the request command to the NAND flash memory dies  100 _ 0 ˜ 100 _m- 1  to request the status of the R/B signal of each of the NAND flash memory dies  100 _ 0 ˜ 100 _m- 1 . Then, under the operation mode of data output, in response to the request command, each of the NAND flash memory dies  100 _ 0 ˜ 100 _m- 1  will use the corresponding DQ port DQ 0 ˜DQ 7  to transmit the R/B for host status of each NAND flash memory die  100 _ 0 ˜ 100 _m- 1  to the NAND flash memory controller  200  through the data bus DQ. 
     For the host level, in the request stage, the operation flow diagram is shown in step S 200  of  FIG.  7 A . Under the operation mode of command input, the host issues the request command to each of the flash memory dies  100 _ 0 ˜ 100 _m- 1 . Next, in step S 300 , under the operation mode of data output, each of the flash memory dies  100 _ 0 ˜ 100 _m- 1  in each channel transmits the status of the status index (the R/B for host status) through the corresponding ports DQ 0 ˜DQ 7  of the data bus DQ to the host. 
     In this way, for the flash memory dies  100 _ 1 ˜ 100 _m- 1  in the channel, the NAND flash memory controller  200  can acquire the R/B for host status of the flash memory dies  100 _ 1 ˜ 100 _m- 1  at a time through the ports DQ 0 ˜DQ 7  of the data bus DQ without using the external R/B signal lines and pads, so that the number of pads of the controller can be reduced. 
       FIG.  6 B  is a timing diagram illustrating an operation flow of each flash memory die of a control method of a NAND flash memory according to another embodiment of the disclosure.  FIG.  7 B  is a schematic diagram of an operation flow in the setup stage for the host level. 
     As shown in  FIG.  6 B , in this embodiment, the setup stage can further include two cycles. In this embodiment, only the setup stage is different from the setup stage of  FIG.  6 A , but the request stage is basically the same. Therefore, only the operation of the setup stage is explained. 
     As shown in  FIG.  6 B , in the setup stage, the operation mode is divided into two cycles, the first cycle is the command input (CMD input) cycle, and the second cycle is an address input (ADDR input) cycle. Both form the cycle type of setting the R/B command. 
     After the enable signal CE# of the NAND flash memory die enables the die, under the operation mode of command input, the NAND flash memory die receives a prepare command issued by the NAND flash memory controller (host)  200 . The preparation command can also be defined by a vendor-specific command, such as the command Feh shown in  FIG.  6 B . The preparation command mainly notifies or hints that each NAND flash memory die  100 _ 0 ˜ 100 _m- 1  is prepared to be assigned a corresponding DQ port for transmitting the R/B status. 
     Then, in the second cycle that is the address input cycle, i.e., under the operation mode of the address input shown in  FIG.  4 B , the multi-channel NAND flash memory controller  200  will issue a specific address value, which corresponds to a specific DQ port and corresponds to a R/B signal line of a NAND flash memory die. For example, at this stage, the value  00   h  corresponds to DQ 0 , the value  01   h  corresponds to DQ 1 , and so on. 
     Therefore, in this embodiment, in the first cycle of the setup stage, the multi-channel NAND flash memory controller  200  can first issue, for example, a command Feh to notify each of the NAND flash memory dies  100 _ 0 ˜ 100   m - 1  that the R/B signal lines thereof are ready to be related to the port DQ 0 —DQ 7  of the data bus DQ, that is, the ports DQ 0 ˜DQ 7  are prepared to be respectively mapped to the R/B signal lines of the NAND flash memory dies  100 _ 0 ˜ 100   m - 1 . Then, in the second cycle of address input, by assigning the addresses values, the R/B signal line of each NAND flash memory die  100 _ 0 ˜ 100   m - 1  can be respectively associated to the port DQ 0 ˜DQ 7 . In this way, through the setup stage having two cycles, the vendor-specific commands and the address values can also be used to map the ports DQ 0 ˜DQ 7  respectively to the internal R/B signal lines of the NAND flash memory dies, and the data (value) for indicating the corresponding relationship is stored in the mapping status register  106  shown in  FIGS.  3 B to  3 E . 
     the operation flow diagram of this setup stage for the host level is shown in  FIG.  7 B . In the setup stage, the setup command issued by the host can further include: in step S 102 , under the operation mode of command input mode, a preparation command (such as the above command Feh) is issued on the data bus DQ to notify each of the flash memory dies  100 _ 0 ˜ 100 _m- 1  that each port DQ 0 ˜DQ 7  of the data bus DQ is prepared to be assigned to the R/B signal line (status index) of each of the flash memory dies  100 _ 0 ˜ 100 _m- 1 . Next, in step S 104 , under the operation mode of address input, the host issues an address signal ADDR (such as  00   h ,  01   h , etc. above) on the data bus DQ. In this way, each port DQ 0 ˜DQ 7  of the data bus DQ of each flash memory die  100 _ 0 ˜ 100 _m- 1  is respectively corresponding to the R/B signal line (status index) of each of the flash memory dies  100 _ 0 ˜ 100 _m- 1 . 
       FIG.  8    is a schematic diagram illustrating the operation timing of the multi-channel flash memory controller according to an embodiment of the disclosure. When the flash memory starts to operate, data input and output have not been performed on the data bus DQ, that is, when the flash memory is in the idle state, the setup stage as shown in  FIG.  6 A  or  FIG.  6 B  can be performed to carry out the operation of setting R/B command for the flash memory dies  0 ˜flash memory die  3 . Then, the port DQ 0 ˜DQ 3  of the data bus DQ are respectively assigned to be the R/B signal lines of the flash memory die  0 ˜flash memory die  3 . In other words, in the stage of setting flash memory die, the die  0  is set to output the R/B for host status using DQ 0 , and the other ports are in the high impedance status, and the die  1  is set to output the R/B for host status using DQ 1 , and the other ports are in the high impedance status. The setting is the same for other dies. 
     In addition, in the setup stage, when the controller (host) sets one of the flash memory dies  0 - 3 , such that the port DQ 0  of the flash memory die is selected to output the R/B for host status, the DQ 0  of each of the flash memory dies, which is corresponding to the DQ 0  of the flash memory die  0 , will output the high impedance status. Similarly, the settings for the flash memory dies  1 - 3  are performed in the same way. 
     In this way, subsequently, the status of the R/B signal lines of each flash memory die  0 ˜flash memory die  3  can be transmitted respectively through the port DQ 0 ˜DQ 3  of the data bus DQ to the multi-channel flash memory controller  200 . At this time, the internal R/B signal lines of the flash memory dies  0 ˜ 3  are in the ready status. 
     Next, the flash memory die enters the operation mode, that is, various operations such as writing data to each flash memory die can be performed. At this time, the internal R/B signals of the flash memory dies  0 ˜ 3  are in the busy status. 
     Then, after a period of time, the multi-channel flash memory controller issues a request RB command to each flash memory die  0 ˜ 3 . When each flash memory die  0 ˜ 3  receives the request RB command, the status of the R/B signal lines of the flash memory dies are transmitted to the multi-channel flash memory controller through the corresponding ports DQ 0 ˜DQ 7 . In this way, the multi-channel flash memory controller can acquire the R/B status of each flash memory die  0 ˜ 3  during the period from RB to DQ in  FIG.  6   . 
     In the request stage, the host will issue the request commends to all flash memory dies, and each flash memory dies  0 - 3  will map the eight outputs of the DEMUX  130  to port DQ [7:0] respectively, and finally the port DQ [7:0] for each flash memory dies  0 - 3  will transmit to the DQ bus. In this way, as shown in  FIG.  8   , a result of outputting X 1   h , X 3   h , . . . on the DO bus can be acquired. Since the host will distribute the corresponding port for each flash memory dies  0 - 3  in a setup stage, no outputs through multiple ports will be performed at the same time to preventing from signal interference. On the other words, two flash memory dies will not use the same port to output the status at the same time. Using the channel  0  in  FIG.  3 A  as an example, during the status output, the flash memory die  0  outputs zzzz_zzz1 on its DQ [7:0], the flash memory die  1  outputs zzzz_zz0z on its DQ [7:0], the flash memory die  2  outputs zzzz_z0zz on its DQ [7:0], and the flash memory die  3  outputs zzzz_0zzzz on its DQ [7:0]. Finally, the DQ bus will output zzzz_0001 to indicate the status of the flash memory dies  0 - 3 . 
     Therefore, under the configuration of the embodiment, the vendor-specific commands and data bus are used to substitute the R/B signal lines of flash memory die, and therefore, the original R/B signal lines and pads of each flash memory die can be reduced, and the multi-channel flash memory controller correspondingly does not require the R/B pad. Therefore, the number of pads of the controller can be effectively reduced, and the size and circuit complexity of the flash memory die is also not increased. In addition, the operation mode of this embodiment is performed using the operation mode of the data input and output, that is, the idle period of the data bus is used to set the R/B signal and DQ port, so that no additional operation is required and the assignment of R/B signals to the DQ ports can be easily made. In addition, the mapping status values can be output to the data bus DQ (external data bus) at the same time, so that times for sequentially polling the status of each flash memory die can be reduced. 
     It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed embodiments without departing from the scope or spirit of the disclosure. In view of the foregoing, it is intended that the disclosure covers modifications and variations provided that they fall within the scope of the following claims and their equivalents.