Patent Publication Number: US-7211900-B2

Title: Thin semiconductor package including stacked dies

Description:
CLAIM OF PRIORITY 
     This application is a continuation of U.S. application Ser. No. 10/600,931, filed on Jun. 20, 2003, now U.S. Pat. No. 6,982,488 entitled “Semiconductor Package And Method Of Fabricating Same”, which is a divisional of U.S. application Ser. No. 09/648,284, filed Aug. 24, 2000 entitled “Semiconductor Package And Method For Fabricating The Same”, now U.S. Pat. No. 6,798,049, issued Sep. 28, 2004. 
    
    
     BACKGROUND OF THE INVENTION 
     a. Field of the Invention 
     The present invention relates, in general, to a semiconductor package and method for fabricating the same and, more particularly, to a semiconductor package and method for fabricating the same that allows a plurality of semiconductor chips to be fixedly stacked in a single, thin package. 
     b. Description of the Prior Art 
     Currently, there is a tendency in which a plurality of semiconductor chips are packaged and mounted on the motherboard of an electronic device such as a PCS phone, a cellular phone or a notebook to perform various functions within a minimum time, and semiconductor packages in which semiconductor chips are packaged and the electronic devices on which the semiconductor packages are mounted are miniaturized. In the meantime, in order to allow a semiconductor package to be thinned, there has been fabricated a semiconductor package in which an opening is formed in a circuit board and a semiconductor is disposed in the opening. 
     With reference to  FIG. 7 , the construction of such a semiconductor package  100 ′ is described as follows. 
     As depicted in the drawing, reference numeral  20 ′ designates a circuit board  20 ′ that has an opening  27 ′. A semiconductor  2 ′ on the upper surface of which a plurality of input/output pads  4 ′ are formed is disposed in the opening  27 ′ of the circuit board  20 ′. The circuit board  20 ′ comprises a base resin layer  21 ′. A circuit pattern including a plurality of bond fingers  22 ′ and ball lands  23 ′ are formed on the upper surface of the base resin layer  21 ′. The surface of the circuit pattern is coated with a cover coat  24 ′ with the bond fingers  22 ′ and the ball lands  23 ′ being exposed upward out of the cover coat  24 ′. The input/output pad  4 ′ of the semiconductor chip  2 ′ is electrically connected to the bond fingers  22 ′ of the circuit board  20 ′ by means of connection means  30 ′. Additionally, an encapsulation  40 ′ is formed around the semiconductor chip  2 ′ and the connection means  30 ′ so as to protect them from the external environment. A plurality of conductive balls  50 ′ are respectively fusion-welded on the ball lands  23 ′ to allow the package to be easily mounted on a motherboard. 
     However, in the conventional semiconductor package  100 ′, since only a single semiconductor chip  2 ′ is disposed in the opening  27 ′, there is an inherent shortcoming in the high density, function and capacity of semiconductor package  100 ′. 
     Furthermore, in a case where the semiconductor chip  2 ′ disposed in the opening of the circuit board  20 ′ is a memory chip, such as a flash memory chip, SRAM chip or the like, since a plurality of semiconductor packages  100 ′ must be mounted on a motherboard (not shown), there occurs a problem in which the mounting density is limited. 
     Recently, there is an increased desire for a semiconductor in which an ASIC (application specific integrated circuit) semiconductor chip and a memory semiconductor chip are packaged together. However, the desire is not satisfied by the conventional semiconductor package. 
     In order to overcome the problem, there has been developed a stack type semiconductor package in which a plurality of semiconductors respectively having various functions are packaged into a single semiconductor package by stacking the semiconductor chips together. The construction of the stack type semiconductor package is depicted in  FIGS. 8A and 8B .  FIG. 8A  is a cross section of the package.  FIG. 8B  is a plan view showing the package in a state where the package is not coated with an encapsulation. 
     In the conventional stack type semiconductor package, a circuit board  10  on which bond fingers  12  are formed includes a resin layer  11 , circuit patterns  19  are formed on the upper and lower surfaces of the resin layer  11 , and a first semiconductor chip  1  is bonded on the center portion of the circuit board  10  with a bonding layer  7  interposed between the circuit board  10  and the first semiconductor chip  1 . Reference numeral  14  designates conductive via holes for connecting the upper circuit pattern  19  to the lower circuit pattern.  19 , and reference numeral  15  designates cover coats for protecting the circuit patterns  19  from the external environment. 
     In addition, a second semiconductor chip  2  is bonded on the upper surface of the first semiconductor chip  1  with a bonding layer  7  interposed between the first and second semiconductor chip  1  and  2 . The input/output pads  4 A of the first semiconductor chip  1  and the input/output pads  4 A of the second semiconductor chip  2  are formed along rectangular directions to prevent them from being overlapped. That is, as illustrated in  FIG. 8B , the input/output pads  4 A of the first semiconductor chip  1  and the input/output pads  4 A of the second semiconductor chip  2  are prevented from being overlapped, in such a way that the input/output pads  4 A of the first semiconductor chip  1  are arranged along the front and rear edges of the first semiconductor chip  1  and the input/output pads  4 A of the second semiconductor chip  2  are arranged along the side edges of the second semiconductor chip  2 . The input/output pads  4 A of the first semiconductor chip  1  and the second semiconductor chip  2  are respectively connected to the bond fingers  12  of the circuit board  10  by means of connection means  20 , such as conductive wires. A plurality of conductive balls  40  are respectively fusion-welded on a plurality of ball lands  13 , which are formed on the lower surface of the circuit board  10 , to transmit signals to a mother board. In the meantime, the first semiconductor chip  1 , the second semiconductor chip  2  and the connection means  20  are encapsulated with an encapsulation  30  to protect them from the external environment. 
     However, in the conventional stack type semiconductor package  101 ′, the first semiconductor chip is bonded on the circuit board and the second semiconductor chip is bonded on the first semiconductor chip. Accordingly, the package is very thick which is contrary to recent trends. 
     Additionally, since the height difference between the input/output pads and the circuit board is excessively enlarged, the loop height of the connection means, such as conductive wires that connect the second semiconductor chip to the circuit pattern, tends to be enlarged. Accordingly, since the loop angle becomes an acute angle, the sweeping phenomenon of the conductive wires occurs easily by the filling pressure during a molding process, thereby causing the inferiority of the package. 
     As another example of the conventional semiconductor package, a composite stack type semiconductor package  102 ′ is illustrated in  FIG. 9 . 
     As depicted in the drawing, the conventional composite stack type semiconductor package is fabricated by stacking a plurality of conventional Ball Grid Array (BGA) semiconductor packages. 
     In each of the BGA semiconductor packages, a semiconductor chip  1  is positioned in the opening of a circuit board  10  on the upper and lower surfaces of which ball lands  13  are formed, the input/output pads (not shown) of the semiconductor chip  1  are respectively connected to the bond fingers  12  of conductive material formed on the upper surface of the circuit board  10  by conductive wires  20 , the ball lands  13  are electrically connected to the bond fingers  12  through conductive via holes  14 , conductive balls  40  are fusion-welded on the ball lands  13 , and an encapsulation  30  is formed on the upper surface of the circuit board  10  to protect the semiconductor chip  1  and the conductive wires  20  from the external environment. In this case, the bond fingers  12  formed on the upper surface of the circuit board  10  are exposed to the outside, and projected pads  8  are respectively formed on the bond fingers  12 . 
     In this conventional BGA package, since the semiconductor chip is disposed in the opening in the central portion of the circuit board, the semiconductor package can be fabricated to be relatively thin. Additionally, a plurality of BGA packages are stacked in such a way that one BGA package is bonded on another BGA package with the solder balls on the lower surface of the upper BGA being fusion-welded on the projected pads on the upper surface of the lower BGA, thereby increasing the mounting density of the package. 
     However, in the conventional composite stack type semiconductor package  102 ′, since projected pads are formed on the periphery of the circuit board of the BGA package  103 ′ and solder balls are fusion-welded on the projected pads, the semiconductor package causes inconvenience in having an extra step to form the projected pads, and has a limitation on the reduction of the thickness of electronic devices owing to the thickness of the projected pads. Additionally, in each of BGA packages, since a single chip is mounted in each package, there occur limitations on the maximization of the memory capacity of each package and the increase of the mounting density of each package. 
     SUMMARY OF THE INVENTION 
     Accordingly, the present invention has been made keeping in mind the above problems occurring in the prior art, and a first object of the present invention is to provide a semiconductor package in which at least two semiconductor chips are mounted at the position of the opening of a circuit board, thereby allowing the semiconductor package to be thinned and achieving high mounting density, high function and high capacity. 
     A second object of the present invention is to provide a semiconductor package in which solder ball lands are formed on the upper and lower surfaces of its circuit board and a plurality of sub-semiconductor packages are stacked using the solder ball lands, thereby allowing the semiconductor package to be thinned still more and maximizing mounting density and memory capacity. 
     A third object of the present invention is to provide a method for fabricating a semiconductor package in accordance with the first object, which is capable of eliminating a wire sweeping phenomenon. 
     In one embodiment of the invention, there is provided a semiconductor package, comprising: a circuit board having, a resin layer provided with an opening at its center portion, and a circuit pattern formed on at least one of the upper and lower surfaces of the resin layer, the circuit pattern including one or more bond fingers and ball lands exposed to the outside; at least two semiconductor chips on one surface of each of which a plurality of input/output pads are formed, the semiconductor chips being stacked at a position of the opening of the circuit board; electric connection means respectively connecting the input/output pads of the semiconductor chips to the bond fingers of the circuit board; an encapsulation with which the semiconductor chips are encapsulated so as to protect them from the external environment; and a plurality of conductive balls fusion-bonded on the ball lands of the circuit board; wherein at least one of the semiconductor chips exists within the opening of the circuit board. 
     In accordance with another embodiment of the invention, there is provided a semiconductor package, comprising: a first semiconductor chip on one surface of which a plurality of input/output pads are formed; a second semiconductor chip bonded by means of a bonding agent on one surface of the first semiconductor on which the input/output pads are formed; a circuit board having, a resin layer provided with an opening at its center portion, the opening being of a size for accommodating the first and second semiconductor chips, two circuit patterns formed on at least one of the upper and lower surfaces of the resin layer, and at least one cover coat with which the circuit pattern is coated; electric connection means respectively connecting the input/output pads of the first and second semiconductor chips to the bond fingers of the circuit board; an encapsulation with which the first and second semiconductor chips are encapsulated so as to protect them from the external environment; and a plurality of conductive balls fusion-bonded on the ball lands of the circuit board. 
     In various embodiments, one or both of the first and second semiconductor chips are rectangular in plan view, and the input/output pads of the first semiconductor chip and the input/output pads of the second semiconductor chip are respectively arranged along different directions in their sectional view or plan view. 
     In one embodiment, the first semiconductor chip is exposed out of the encapsulation at a surface opposite to a surface on which the second semiconductor chip is bonded. 
     In one embodiment, the input/output pads of the first and second semiconductor chips are arranged in directions opposite to those in which the conductive balls are arranged. Alternatively, the input/output pads of the first and second semiconductor chips are arranged in same directions as those in which the conductive balls are arranged. 
     The circuit board in one embodiment is fabricated in such a way that circuit patterns are formed on the upper and lower surfaces of the resin layer and the circuit patterns are electrically connected to each other through conductive via holes. 
     In accordance with another embodiment of the present invention, there is provided a semiconductor package, comprising: a circuit board having, a resin layer provided with an opening at its center portion, and two circuit patterns formed on the upper and lower surfaces of the resin layer, the circuit patterns including a plurality of bond fingers and ball lands exposed to the outside, wherein the circuit patterns are connected to each other through one or more via holes; a first semiconductor chip on a lower surface of which a plurality of input/output pads are formed, the first semiconductor chip being disposed in the opening of the circuit board; a second semiconductor chip on the upper surface of which a plurality of input/output pads are formed, the second semiconductor chip being bonded on the upper surface of the first semiconductor chip; connection means connecting the input/output pads of the first and second semiconductor chips to the bond fingers formed on the upper and lower surfaces of the circuit board; a first encapsulation with which a predetermined area of the lower surface of the circuit board covering the first semiconductor chip and the opening is encapsulated; a second encapsulation with which a predetermined area of the upper surface of the circuit board covering the second semiconductor chip and the opening is encapsulated; and a plurality of conductive balls fusion-bonded on the ball lands of the circuit board. 
     The package may further include a third semiconductor, the third semiconductor being connected to the bond fingers of the circuit board with connection means. 
     The package may further include a fourth semiconductor chip bonded on the lower surface of the first semiconductor chip, and connection means connecting the fourth semiconductor chip to the bond fingers of the circuit board. 
     The first encapsulation may be formed of a liquid phase encapsulation material and the second encapsulation may be formed of an epoxy molding compound. 
     The package may further include a dam formed along the upper surface of the circuit board in the vicinity of the opening so as to prevent a bonding agent for bonding the second semiconductor chip on the first semiconductor chip from overflowing. 
     In accordance with an embodiment of the present invention for accomplishing the second object, there is provided a semiconductor package, comprising: a semiconductor chip within an opening of a circuit board on the upper and lower surfaces of which two circuit patterns are respectively formed, the lower surface of the semiconductor chip and the lower surface of the circuit board being on a same plane; electric connection means respectively connecting the input/output pads of the semiconductor chips to the circuit pattern formed on the upper surface of the circuit board; a plurality of conductive via holes electrically connecting the circuit patterns formed on the upper and lower surfaces of the circuit board to each other; a plurality of ball lands on which a plurality of conductive balls are fusion-bonded, the ball lands being formed on the circuit patterns formed on the upper and lower surfaces of the circuit board; and an encapsulation for protecting the semiconductor chip and the connection means from the external environment. 
     The semiconductor chip may consist of at least two stacked sub-semiconductor chips, input/output pads of the sub-semiconductor chips being electrically connected to the circuit pattern formed on the upper surface of the circuit board by the connection means. 
     The semiconductor package may further include one or more additional semiconductor packages wherein a plurality of solder balls are fusion-bonded on the ball lands formed on the lower surface of the circuit board of each semiconductor package, all the semiconductor packages being fixedly stacked together with the solder balls of the lower surface of the circuit board of one semiconductor package being fusion-bonded on the ball lands of the upper surface of the circuit board of another semiconductor package. 
     In accordance with an embodiment of the present invention, there is provided a method for fabricating a semiconductor package, comprising: providing a circuit board, the circuit board having a resin layer and two circuit patterns, the resin layer being provided with an opening at its center portion, the circuit patterns being formed on the upper and lower surfaces of the resin layer and including a plurality of bond fingers and ball lands exposed to the outside, wherein the circuit patterns are connected to each other through one or more via holes; disposing a first semiconductor chip, on the lower surface of which a plurality of input/output pads are formed, in the opening of the circuit board, and connecting the input/output pads of the first semiconductor chip to the bond fingers of the circuit board with connection means; primarily encapsulating a predetermined area of the lower surface of the circuit board covering the first semiconductor chip and the opening with an encapsulating material; bonding a second semiconductor chip, on the upper surface of which a plurality of input/output pads are formed, on the upper surface of the first semiconductor chip, and connecting the input/output pads of the second semiconductor chip to the bond fingers of the circuit board with connection means; secondly encapsulating a predetermined area of the upper surface of the circuit board covering the second semiconductor chip and the opening with an encapsulating material; and fusion-bonding a plurality of conductive balls on the ball lands of the circuit board. 
     The first semiconductor chip may consist of at least two sub-semiconductors, i.e., two chips stacked upon each other. 
     The second semiconductor chip also may consist of at least two sub-semiconductors. 
     The method may further include the step of bonding another semiconductor chip on the lower surface of the first semiconductor chip after the step of disposing the first semiconductor within the opening of the circuit board. 
     The method may further include the step of bonding another semiconductor chip on the upper surface of the second semiconductor chip after the step of bonding the second semiconductor. 
     In accordance with another embodiment of the present invention, there is provided a method for fabricating a semiconductor package, comprising: providing a circuit board, the circuit board having a resin layer and two circuit patterns, the resin layer being provided with an opening at its center portion, the circuit patterns being formed on the upper and lower surfaces of the resin layer and including a plurality of bond fingers and ball lands exposed to the outside, wherein the circuit patterns are connected to each other through one or more via holes; bonding at least one semiconductor chip over the opening of the circuit board, and connecting the input/output pads of the semiconductor chip to the bond fingers of the circuit board with connection means; primarily encapsulating the upper surface of the opening of the circuit board and the semiconductor chip with an encapsulating material; disposing at least one semiconductor chip, on the lower surface of which a plurality of input/output pads are formed, within the opening of the circuit board, and connecting the input/output pads of the semiconductor chip to the bond fingers of the circuit board with connection means; secondly encapsulating a predetermined area of the lower surface of the circuit board covering the semiconductor chip and the opening with an encapsulating material; and fusion-bonding a plurality of conductive balls on the ball lands of the circuit board. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The above and other objects, features and other advantages of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which: 
         FIGS. 1A and 1B  are cross sections showing semiconductor packages in accordance with a first embodiment of the present invention; 
         FIGS. 2A ,  2 B and  2 C are cross sections showing semiconductor packages in accordance with a second embodiment of the present invention; 
         FIGS. 3A to 3C  are cross sections showing semiconductor packages in accordance with a third embodiment of the present invention; 
         FIGS. 4A to 4F  are cross sections showing a method for fabricating a semiconductor package in accordance with the present invention; 
         FIGS. 5A to 5F  are cross sections showing another method for fabricating a semiconductor package in accordance with the present invention; 
         FIG. 6  is a cross section showing a stack type semiconductor package  109  in accordance with a fourth embodiment of the present invention; 
         FIG. 7  is a cross section showing a conventional semiconductor package; 
         FIG. 8A  is a cross section showing a conventional stack type semiconductor package; 
         FIG. 8B  is a plan view showing the conventional stack type semiconductor package with its encapsulation being removed; and 
         FIG. 9  is a cross section showing a conventional composite stack type semiconductor package. 
     
    
    
     DETAILED DESCRIPTION OF THE EXEMPLARY EMBODIMENTS 
     This application claims priority to Korean patent applications 99-35108, 99-65926 and 99-65934, which were filed in the KIPO on Aug. 24, 1999, Dec. 30, 1999 and Dec. 30, 1999, respectively, and are incorporated herein by reference in their entireties. Certified copies have been filed herewith. 
       FIGS. 1A and 1B  are cross sections showing semiconductor packages  101  and  102  in accordance with a first embodiment of the present invention. In the drawings, reference numeral  1  designates a first semiconductor chip  1  on the lower surface of which input/output pads (not shown) are formed. A second semiconductor  2  is bonded on the surface on which the input/output pads are formed with a bonding layer  7  interposed between the first and second semiconductor chips  1  and  2 . The bonding layer  7  may be formed of an epoxy bonding agent or double-sided tape. Input/output pads  2   a  are formed on the lower surface of the second semiconductor  2 , also. 
     At least one of the first and second semiconductor chips  1  and  2  is shaped in the form of an oblong rectangle in this example (though both may be oblong), so that the input/output pads of the first semiconductor chip  1  and the input/output pads  2   a  of the second semiconductor chip  2  are prevented from disturbing each other, thereby allowing a connecting process to be easily performed by means of connection means  20 , such as conductive wires, leads, or extensions of the bond fingers. Of course, both of the first and second semiconductor chips may be shaped in the form of oblong rectangles. Additionally, the input/output pads of the first semiconductor chip  1  and the input/output pads  2   a  of the second semiconductor chip are formed on different positions in their sectional view or plan view (although not visible in  FIGS. 1A and 1B ), so that the connecting process is easily performed by means of connection means  20 . That is, if the input/output pads of the first semiconductor chip  1  are formed along the front and rear edges of the first semiconductor chip  1 , the input/output pads  2   a  of the second semiconductor chip  2  are formed along the side edges of the second semiconductor chip  2 . 
     A circuit board  10  is disposed around the first semiconductor chip  1 . A predetermined-sized opening  16  is formed in the center portion of the circuit board  10 , and the first semiconductor chip  1  is accommodated in the opening  16 . In the circuit board  10 , a conductive pattern  19  is minutely formed on the lower surface of a resin layer  11 , and the circuit pattern  19  is coated with a cover coat  15  for protecting the circuit pattern  19  from the external environment. 
     The input/output pads of the first and second semiconductor chips  1  and  2  are respectively connected to the circuit pattern  19  formed on the lower surface of the resin layer  11  by means of electric connection means  20 , such as conductive wires. As a result, electric signals can be transmitted via the connection means from the first and second semiconductor chips  1  and  2  to the circuit pattern  19  or from the circuit pattern  19  to the first and second semiconductor chips  1  and  2 . 
     The first and second semiconductor chips  1  and  2  and the connection means  20  are encapsulated with an encapsulation material for protecting them from dust, moisture, mechanical impact and the like. The area that is encapsulated with the encapsulation material is referred to as an encapsulation  30 . A plurality of conductive balls  40  are fusion-bonded on the circuit pattern  19  formed on the lower surface of the resin layer  11  to allow the package to be mounted on a motherboard. The conductive balls  40  are preferably solder balls. 
     In this case, since the direction along which the input/output pads of the first semiconductor chip  1  and the input/output pads  2   a  of the second semiconductor chip  2  are arranged is the same as that of the circuit pattern  19  or the conductive balls  40 , an additional circuit pattern and an additional cover coat may be formed on the upper surface of the circuit board  10 . 
     The upper surface of the first semiconductor chip  1 , that is, the surface that is not in contact with the second semiconductor chip  2 , is exposed out of the encapsulation  30  to dissipate heat out of the package. As illustrated in  FIG. 1B , a heat-conductive layer  60  of copper, aluminum or the like may be formed on the upper surfaces of the first semiconductor chip  1  and the resin layer  11  to improve the performance of heat dissipation. 
     Although the input/output pads of the first and second semiconductor chips  1  and  2  are depicted to be formed on the lower surfaces of the first and second semiconductor chips  1  and  2  in  FIGS. 1A and 1B , the input/output pads of the first and second semiconductor chips  1  and  2  may be formed on the upper surfaces of the first and second semiconductor chips  1  and  2  as depicted in  FIG. 2A . In this case, a circuit pattern  19  is formed on the upper surface of the circuit board  10 , that is, the upper surface of the resin layer  11 , and the circuit pattern  19  is connected to the lower circuit pattern through conductive via holes  14  to secure signal passages. The upper circuit pattern  19  is coated with a cover coat  15  to protect the upper circuit pattern  19  from the external environment. 
       FIGS. 2A ,  2 B and  2 C are cross sections showing semiconductor packages  103 ,  104  and  105  in accordance with a second embodiment of the present invention. 
     The semiconductor packages  103 ,  104  and  105  of the second embodiment are similar to the semiconductor packages  101  and  102  of the first embodiment. The difference between them is described as follows. 
     In the drawings, reference numeral  1  designates a first semiconductor chip  1  on the upper surface of which input/output pads  1   a  are formed. A second semiconductor  2  is bonded on the surface of first semiconductor chip  1 , on which input/output pads are not formed, by means of a bonding layer  7 . Input/output pads  2   a  (not shown) are formed on the upper surface of the second semiconductor  2 , also. The lower surface of the second semiconductor chip  2  is exposed out of an encapsulation  30  to improve the performance of heat dissipation. 
     A circuit board  10  is disposed around the first semiconductor chip  1 . A predetermined-sized opening  16  is formed in the center portion of the circuit board  10 , and the first semiconductor chip  1  is accommodated in the opening  16 . In the circuit board  10 , conductive patterns  19  are minutely formed on the upper and lower surfaces of a resin layer  11 , and the circuit patterns  19  are coated with cover coats  15  for protecting the circuit patterns  19  from the external environment. The conductive patterns  19  formed on the upper and lower surfaces of a resin layer  11  are connected to each other through conductive via holes  14 . 
     The input/output pads  1   a  of the first semiconductor chip  1  are connected to the circuit patterns  19  formed on the upper surface of the resin layer  11  by means of electric connection means  20 , and the input/output pads  2   a  (not shown) of the second semiconductor chip  2  are connected to the circuit pattern  19  formed on the lower surface of the resin layer  11  by means of electric connection means  20 , e.g., bond wires. As a result, electric signals are transmitted from the first and second semiconductor chips  1  and  2  to a mother board or from the mother board to the first and second semiconductor chips  1  and  2 , through the connection means, the circuit patterns  19 , the conductive via holes  14  and the circuit pattern  19 . 
     In accordance with the second embodiment, a thin semiconductor package can be obtained because the first semiconductor chip  1  is disposed in the opening of the circuit board  10 , and the sweeping phenomenon of the connection means  20  is prevented because the loop height of the connection means connecting the second semiconductor chip  2  to the circuit board  10  is relatively small. Low loop wire bonds may be used. 
     As illustrated in  FIG. 2B , the sizes of the first and second semiconductor chips  1  and  2  may be different. That is, the size of the first semiconductor chip  1  is smaller than the size of the second semiconductor chip  2 , and the second semiconductor chip  2  is bonded on the first semiconductor chip  1  using a bonding agent  7 . In this case, there is an advantage in which the input/output pads of the first and second semiconductor chips are formed along a same direction. Of course, in this case, the semiconductor chip can be thinned by, for example, polishing or etching the backside of the wafer before dicing. 
     As depicted in  FIG. 2C , a plurality of openings  16  are formed on the circuit board  10  and a plurality of semiconductor chips are stacked in each of openings  16 . Accordingly, package  105  houses four semiconductor chips. 
     In the semiconductor packages in accordance with the first and second embodiments  101  to  105 , since an opening is formed on the circuit board and reduces the thickness of the package, the semiconductor package can be thin notwithstanding that a plurality of semiconductor chips are stacked. 
     Additionally, since a plurality of semiconductor chips are stacked, various semiconductor chips having various functions can be provided in a single semiconductor package, for example, a memory chip and a logic chip or a processor chip can be stacked. 
     Furthermore, since the height difference between the input/output pads of the second semiconductor chip and the circuit board is equal to the height difference between the input/output pads of the first semiconductor chip and the circuit board, the hoop height of the connection means is relatively small. Accordingly, the possibility of the occurrence of the sweeping phenomenon of the connection means can be reduced notwithstanding that the semiconductor chips are stacked. 
       FIGS. 3A to 3C  are cross sections showing semiconductor packages  106 ,  107  and  108  in accordance with a third embodiment of the present invention. 
     As shown in  FIG. 3A , reference numeral  10  designates a circuit board  10  for transmitting signals between a semiconductor chip and a motherboard. The circuit board  10  includes a resin layer  11  having an opening  16  at its center portion. Circuit patterns are formed on the upper and lower surfaces of the resin layer  11 . In detail, the upper circuit pattern having bond fingers  12  is formed on the upper surface of the resin layer  11 , while the lower circuit pattern having bond fingers and ball lands is formed on the lower surface of the resin layer  11 . The circuit patterns formed on the upper and lower surfaces of the resin layer  11  are connected to each other through conductive via holes  14 . The resin layer  11  is coated with cover coats  15  of a predetermined thickness at its upper and lower surfaces, with the bond fingers  12  and the ball lands  13  being exposed to the outside through the respective cover coats  15 , so that the circuit patterns can be protected from the external environment. 
     A first semiconductor chip  1  is disposed in the opening  16  of the circuit board  10 . A plurality of input/output pads  1  a are formed on the lower active surface of chip  1 . 
     A second semiconductor chip  2  is bonded on the upper surface of the first semiconductor chip  1  by means of a bonding agent  34 . A plurality of input/output pads  2   a  are formed on the upper surface of the second semiconductor chip  2 . 
     A dam  17  of a predetermined height is formed on the upper surface of the circuit board  10  to prevent the bonding agent  34 , which is used to bond the second semiconductor chip  2  on the first semiconductor chip  1 , from contaminating the bond fingers  12 . The dam  17  is preferably made of the same material as that of a general cover coat. Alternatively, the bonding agent  34  may be a preformed adhesive film. 
     Even though a third semiconductor chip  3  that is smaller than the second semiconductor chip  2  may be bonded on the upper surface of the second semiconductor chip  2 , the present invention is not limited to this. Of course, a plurality of input/output pads  3   a  are formed on the upper surface of the third semiconductor chip  3 . 
     The input/output pads  1   a ,  2   a  and  3   a  of the first, second and third semiconductor chips  1 ,  2  and  3  are respectively connected to the bond fingers  12  formed on the upper and lower surfaces of the circuit board  10  by means of connection means  20 , such as an aluminum or gold wire. That is, the input/output pads  1  a of the first semiconductor chip  1  are connected to the bond fingers  12  formed on the lower surface of the circuit board  10 , while the input/output pads  2   a  and  3   a  of the second and third semiconductor chips  2  and  3 , respectively, are connected to the bond fingers  12  formed on the upper surface of the circuit board  10 . 
     The predetermined areas of the upper and lower surfaces of the circuit board  10  covering the first, second and third semiconductor chips  1 ,  2  and  3  and the opening  16  are encapsulated with an insulative encapsulant material. In more detail, the predetermined area of the lower surface of the circuit board  10  covering the first semiconductor chip  1  and the opening  16  is encapsulated with a first encapsulation  31 , preferably, a liquid phase encapsulation. However, the first encapsulation  31  is not limited to the liquid phase encapsulation. Additionally, the predetermined area of the upper surface of the circuit board  10  covering the second and third semiconductor chips  2  and  3  and the opening  16  is encapsulated with a second encapsulation  32 , preferably, an epoxy molding compound encapsulation. However, the second encapsulation  32  is not limited to the epoxy molding compound encapsulation. 
     In  FIG. 3A , only a central portion of the upper surface of circuit board  10  is encapsulated. The encapsulant  32  is individually molded or otherwise formed. Peripheral portions of the upper surface of circuit board  10  are not covered by encapsulant  32 . 
     As illustrated in  FIG. 3B , the entire upper surface of the circuit board  10  may be encapsulated with the second encapsulation  32 . The peripheral sides of the encapsulant  32  and circuit board  10  are orthogonal, as would be produced by a saw cut. 
     A plurality of conductive balls  40 , such as solder balls, are respectively fusion-welded on the ball lands  13  of the circuit board  10 , that is, the ball lands  13  formed on the lower surface of the circuit board  10 , so that the package can be mounted on a motherboard with the conductive balls  40  fusion-bonded on the predetermined pattern of a motherboard. 
     As illustrated in  FIG. 3C , the fourth semiconductor chip  4  may be bonded on the lower surface of the first semiconductor chip  1 , but this embodiment is not limited to this. A plurality of input/output pads  4   a  are formed on the lower surface of the fourth semiconductor chip  4 , and the input/output pads  4   a  are respectively connected to the bond fingers  12  formed on the lower surface of the circuit board  10  by connection means  20 . Chips  1 – 4  may be thinned by polishing or etching the backside (inactive side) of the wafer of dies before dicing. 
       FIGS. 4A to 4F  are cross sections showing a method for fabricating a semiconductor package in accordance with the present invention. 
     First of all, there is provided a circuit board  10 . The circuit board  10  includes a resin layer  11  having an opening  16  at its center portion. Two circuit patterns respectively including bond fingers  12  and the ball lands  13  are respectively formed on the upper and lower surfaces of the resin layer  11 . The circuit patterns are connected to each other through conductive via holes  14 , which are filled or plated with metal, conductive ink, or some other conductive material. 
     At this time, a film  18  is bonded on the upper surface of the opening  16  to close the opening  16 , so that semiconductor chips  1 ,  2  and  3  are disposed and bonded easily. Film  18  in may be an adhesive, heat resisting material. For example, film  18  may be a one or two sided adhesive tape or film. Depending on the type of bonding agent subsequently used to affix semiconductor chip  2  to semiconductor chip  1 , a ring dam  17  of a predetermined height may be provided on the upper surface of the circuit board in the vicinity of the opening  16  to prevent the bond fingers from being contaminated by a viscous bonding agent. 
     Thereafter, as shown in  FIG. 4B , a first semiconductor chip  1  is disposed in the opening  16  of the circuit board  10  on film  18  forming a bond thereto, and is electrically connected to the bond fingers  12  formed on the lower surface of the circuit board  10  by connection means  20 . 
     In this case, first semiconductor chip  1  is a single chip. Alternatively, a previously-formed stack of chips may be disposed in opening  16  in order to make the embodiment of  FIG. 3C . Of course, the embodiment of  FIG. 3C  also may be made by disposing a single chip  1  in opening  16  and then stacking a chip  4  thereon with an adhesive layer  34  therebetween. 
     Subsequently, as depicted in  FIG. 4C , a predetermined area covering the first semiconductor chip  1  and the opening  16  are encapsulated with a first encapsulation  31 . In this case, the first encapsulation  31  is preferably formed of liquid phase encapsulation, but this embodiment is not limited to this. Film  18  acts as a stop to keep encapsulant  31  within opening  16 . After curing encapsulant  31 , film  18  is removed, which exposes the backside, upper surface of chip  1  and a portion of encapsulant  31  in a common plane with the upper surface of circuit board  10 . Alternatively, film  18  may not be removed so as to be present in the completed package. 
     Thereafter, as shown in  FIG. 4D , a second semiconductor chip  2 , on the upper surface of which a plurality of input/output pads  2   a  are formed, is bonded on the exposed upper surface of the first semiconductor chip  1  and encapsulant  31  by means of a bonding agent, denoted as adhesive layer  34 . Adhesive layer  34  may be a double sided tape or film or may be a viscous epoxy adhesive applied on film  18  within dam  17 . Adhesive layer  34  may be applied on film  18  if film  18  has not been removed. Alternatively, if film  18  remains and itself is double sided adhesive, then an additional bonding agent may not be necessary to bond second chip  2  to first chip  1 . 
     In this case, a third semiconductor chip  3  is bonded on the upper surface of the second semiconductor chip  2  with an non-conductive adhesive layer  34 . After chip  2  has been attached to chip  1 . Alternatively, chips  2  and  3  may be stacked and then the backside of chip  2  maybe attached to chip  1 . 
     Next, as shown in  FIG. 4E , the input/output pads  2   a ,  3   a  of the second semiconductor chip  2  and the third semiconductor chip  3 , respectively, are connected to the bond fingers  12  formed on the upper surface of the circuit board  10  by connection means  20 , e.g., bond wires. 
     Thereafter, the second and third semiconductor chips  2  and  3  positioned over the opening  16  are encapsulated with a second encapsulation  32 . In this case, the second encapsulation  32  may be formed by molding an epoxy molding compound, but this embodiment is not limited to this. 
     Finally, as shown in  FIG. 4F , a plurality of conductive balls  40 , such as solder balls, are respectively fusion-welded on the ball lands  13  of the circuit board  10 , so that the package is capable of being mounted on a motherboard. 
     In one embodiment, circuit board  10  is part of strip of identical interconnected units of circuit boards  10  that are arranged in an array (e.g., in a line or in a matrix having rows and columns of circuit boards  10 ). A package is assembled at each of the units in parallel process steps, and then after completion, the strip is severed with a saw or the like along the perimeter of each unit so as to singulate individual packages each having a circuit board  10 . The saw forms orthogonal peripheral sides on circuit board  10 . In the embodiment of  FIG. 3B , sawing through a block of encapsulant  32  that spans a plurality of the circuit boards  10  of the array produces orthogonal peripheral sides on circuit board  10  and encapsulant  32 . Such parallel processing may also be used to assemble the other embodiments of packages described herein (e.g., the method of  FIGS. 5A to 5F ) provided below. 
       FIGS. 5A to 5F  are cross sections showing another method for fabricating a semiconductor package  106  in accordance with the present invention. 
     As shown in  FIG. 5A , there is provided a circuit board  10 . The circuit board  10  includes a resin layer  11  having an opening  16  at its center portion. Two circuit patterns including bond fingers  12  and the ball lands  13  and being exposed to the outside are respectively formed on the upper and lower surfaces of the resin layer  11 . The upper and lower circuit patterns are connected to each other through conductive via holes  14 . 
     Subsequently, as depicted in  FIG. 5B , a film  18  is applied over opening  32 . An adhesive layer  34  is applied to film  18  and the portions of the upper surface of circuit board  10  within dam  17 . Alternatively, film  18  may be an adhesive tape or film. Second and third semiconductor chips  2  and  3  are bonded to film  18  and the upper surface of the circuit board  10  over opening  16 . In this embodiment, the peripheral edges of the lower surface of semiconductor chip  2  are bonded to the upper surface of circuit board  10  around opening  16 , but it is not necessary that there be such overlap. The input/output pads  2   a  and  3   a  of the second and third semiconductor chips  2  and  3 , respectively, are then respectively connected to the bond fingers  12  of the circuit board  10  by means of connection means  20 . The area of semiconductor chip  1  is larger than the area of opening  16  such that peripheral edges of chip  2  superimpose and are supported by the upper surface of resin layer  11 . 
     Thereafter, as shown in  FIG. 5C , the predetermined area of the upper surface covering the circuit board  10  and the second and third semiconductor chips  2  and  3  are encapsulated with an encapsulation material to form a second encapsulation  32 . 
     Subsequently, as illustrated in  FIG. 5D , a first semiconductor chip  1  having a plurality of input/output pads  1   a  at its lower surface is disposed in the opening  16  of the circuit board  10  under the second and third semiconductor chips  2  and  3 . First semiconductor chip  1  is bonded to the inactive backside of semiconductor chip  2  through film  18 . Again, film  18  may be a double sided adhesive, or additional adhesive may be applied to the exposed surface of film  18  within opening  16  prior to the mating of chip  1  thereto. The input/output pads  1   a  of the first semiconductor chip  1  are connected to the bond fingers  12  of the circuit board  10  by means of connection means  20 . 
     Thereafter, as shown in  FIG. 5E , first semiconductor chip  1  and a portion of the lower surface of circuit board  10  are covered with an encapsulation material to form a first encapsulation  31 . Encapsulant  31  also fills opening  16 . 
     Finally, a plurality of conductive balls  40  are respectively fusion-welded on the ball lands  13  of the circuit board  10 , so that the package is capable of being mounted on a motherboard. 
     In the semiconductor packages  106 ,  107  and  108  and method for fabricating the same in accordance with the present invention, a plurality of semiconductor chips are mounted in the opening of the circuit board while being stacked, so that the high density, high function and high capacity of the semiconductor packages are achieved. 
     Furthermore, in the case of a memory semiconductor chip, the capacity of the semiconductor package can be maximized with the minimum size of the semiconductor package. 
     Additionally, since an ASIC (application specific integrated circuit) semiconductor chip and a memory semiconductor chip may be packaged together in such a single semiconductor package, many electronic functions can be satisfied by the single semiconductor package. 
     The embodiments of  FIGS. 1A ,  1 B,  2 A,  2 B, and  2 C may be made by similar methods. For example, a circuit board  10  provided with an opening  16  (or plural openings  16  as in  FIG. 2C ) may have a temporary film applied over the opening. Subsequently, chips  1  and  2  may be serially mounted on the film, or may be mounted as a stack thereon. After encapsulation with encapsulant  30 , the temporary film may be removed, thereby exposing the backside of chip  1  ( FIGS. 1A ,  1 B) or chip  2  ( FIGS. 2A–2C ). Subsequently, a thermally conductive layer  60  may be applied over the exposed surface of chip  1  ( FIG. 1B ). 
       FIG. 6  is a cross section showing a stack type semiconductor package  109  in accordance with a fourth embodiment of the present invention. 
     The semiconductor package  109  of  FIG. 6  is similar to the semiconductor package  102 ′ of  FIG. 9 , except that at least one of semiconductor chip  1  or  2  is disposed in the opening  16  of the circuit board  10 , cover coats  15  are applied on the conductive circuit patterns  19  formed on the upper and lower surfaces of the circuit board  10  to insulate and protect the circuit patterns  19 , and a plurality of ball lands  13  are respectively formed on the circuit patterns  19  formed on the upper and lower surfaces of the circuit board  10 . Accordingly, the description of the similar parts is omitted here. 
     As shown in  FIG. 6 , four semiconductor packages are integrated into a combined semiconductor package with one laid on the top of another, in such a way that a plurality of conductive balls  40  are fusion-bonded on the lower surface of the circuit board  10  of each semiconductor package  103  and, thereafter, a plurality of conductive balls  40  formed on the lower surface of the circuit board  10  of one semiconductor package  103  are fusion-bonded on the ball lands  13  formed on the upper surface of the circuit board  10  of another semiconductor package  103 . 
     In the composite stack type semiconductor package in accordance with the fourth embodiment, since a plurality of semiconductor packages are integrated into a single body in such a simple way that the conductive balls  40  of one semiconductor package  103  are fusion-bonded on the ball lands  13  of another semiconductor package  103 , the semiconductor packages are easily integrated together without a change in construction. Additionally, since the conductive balls  40  of one semiconductor package  103  are fusion-bonded on the ball lands  13  of another semiconductor package  103 , the thickness of the composite stack type semiconductor package  109  is saved by the elimination of the thickness of the projected pads  8  when compared with a conventional stack type semiconductor  102 ′ (refer to  FIG. 9 ). 
     In accordance with the fourth embodiment, at least one semiconductor chip is disposed within the opening of the circuit board. The embodiment of  FIG. 6  has two semiconductor chips are disposed within the opening of the circuit board, which increases density. The chips may be thinned by backside polishing or etching. If the thickness of the circuit board is sufficient, stacked three or more very thin semiconductor chips may be disposed in the opening. Furthermore, a plurality of semiconductor packages having two or more stacked semiconductor chips themselves may be stacked together, as illustrated in  FIG. 6 . 
     As described above, in the semiconductor package  108  in accordance with the fourth embodiment, a composite stack type semiconductor can be fabricated easily by forming solder ball lands on the upper and lower surfaces of the circuit board, so that the semiconductor package can be thinned and the mounting density and memory capacity of the semiconductor package can be maximized. Additionally, two or more semiconductor chips are disposed in a single semiconductor package, so that the mounting density of semiconductor chips and the memory capacity of a semiconductor package. 
     Although various embodiments of the present invention have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims.