Patent Publication Number: US-8970272-B2

Title: High-speed low-power latches

Description:
BACKGROUND 
     I. Field 
     The present disclosure relates generally to electronics, and more specifically to latches. 
     II. Background 
     A latch is a circuit that can store one bit of information and can be controlled by a clock signal or some other control signal. A latch may have two operating modes, a tracking mode and a holding mode, which may be selected by the clock signal. These operating modes may also be referred to by other names. The output of the latch may follow an input signal during the tracking mode, e.g., when the clock signal is at logic high. A data value may be captured by the latch, e.g., when the clock signal transitions to logic low. The captured value may be retained and provided to the latch output during the holding mode, e.g., when the clock signal is at logic low. A latch may also be triggered by low logic, rising edge, or falling edge of a clock signal. 
     Latches are commonly used in various circuits and applications. For example, latches may be used in frequency dividers, which are often used in receivers and transmitters. A frequency divider may receive a VCO signal from a voltage controlled oscillator (VCO), divide the VCO signal in frequency by a factor of N, and provide a divider signal having a frequency that is 1/N-th the frequency of the VCO signal, where N may be an integer or non-integer value. Since the VCO signal may be at a high frequency, high-speed latches that consume low power are highly desirable. 
     SUMMARY 
     High-speed low-power latches that may be used for various circuits and applications are described herein. In an aspect, a high-speed low-power latch includes first, second and third sets of transistors. The first set of transistors selects a tracking mode or a holding mode for the latch based on a clock signal having non-rail-to-rail or rail-to-rail voltage swing. The second set of transistors captures a data value based on an input signal and provides an output signal during the tracking mode. The third set of transistors stores the data value and provides the output signal during the holding mode. The input and output signals have rail-to-rail voltage swing. The clock signal and the input and output signals may be differential signals. 
     In one design, the first set includes at least one pull-down transistor and/or at least one pull-up transistor that are enabled or disabled based on the clock signal. In one design, the second set includes first and second switching transistors that receive non-inverted and inverted input signals, respectively, and provide inverted and non-inverted output signals, respectively. The second set may include additional switching transistors. In one design, the third set includes first and second latching transistors coupled as a first inverter and third and four latching transistors coupled as a second inverter. The first and second inverters are cross-coupled. 
     In another aspect, a frequency divider includes multiple latches coupled in series. Each latch receives a clock signal having non-rail-to-rail voltage swing and provides an output signal having rail-to-rail voltage swing. The multiple latches divide the clock signal in frequency and provide a divider signal having a frequency that is a fraction of the frequency of the clock signal. 
     In yet another aspect, a signal generator includes at least one latch and a control circuit that performs automatic duty cycle adjustment. The at least one latch receives a clock signal and generates an output signal. The control circuit senses a duty cycle of a feedback signal derived from the output signal. The control circuit then generates a control signal to adjust the operation of the at least one latch to obtain 50% duty cycle for the feedback signal. In one design, the signal generator further includes a bias circuit that receives an oscillator signal and provides the clock signal. The control circuit provides a bias voltage as the control signal, and the clock signal has a direct current (DC) level determined by the bias voltage. The duty cycle may be adjusted by turning on at least one transistor in the at least one latch either stronger or weaker based on the DC level of the clock signal. 
     Various aspects and features of the disclosure are described in further detail below. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  shows a block diagram of a local oscillator (LO) signal generator. 
         FIGS. 2A and 2B  show schematic diagrams of a conventional current mode logic (CML) latch and a conventional complementary metal oxide semiconductor (CMOS) static latch, respectively. 
         FIGS. 3A to 3E  show schematic diagrams of five designs of high-speed low-power latches. 
         FIG. 4  shows a process for latching an input signal. 
         FIG. 5  shows a block diagram of an LO signal generator with automatic duty cycle adjustment. 
         FIG. 6  shows a process for performing automatic duty cycle adjustment. 
         FIG. 7  shows a block diagram of a wireless communication device. 
     
    
    
     DETAILED DESCRIPTION 
     The high-speed low-power latches described herein may be used for various circuits and applications. For clarity, an exemplary use of the high-speed low-power latches in a frequency divider is described below. 
       FIG. 1  shows a block diagram of a design of an LO signal generator  100 , which may be part of a receiver or a transmitter. Within LO signal generator  100 , a VCO  110  generates a VCO signal at a frequency of f 0 . A frequency divider  120  divides the VCO signal by two in frequency and provides a divider signal having a frequency of f 0 /2. Within frequency divider  120 , a voltage level shifter  122  receives the VCO signal, shifts the DC level and/or varies the amplitude of the VCO signal, and provides a clock signal. Latches  124  and  126  are coupled in series. Latch  124  has its data input coupled to an inverted data output of latch  126  and its clock input receiving the clock signal. Latch  126  has its data input coupled to a data output of latch  126 , its clock input receiving the clock signal, and its data output providing the divider signal. A driver (DRV)  130  receives the divider signal and provides an LO signal to a mixer  140 . For a transmitter, mixer  140  upconverts a baseband input signal with the LO signal and provides an upconverted output signal. For a receiver, mixer  140  downconverts a radio frequency (RF) input signal with the LO signal and provides a downconverted output signal. 
     High-speed frequency dividers, such as frequency divider  120  in  FIG. 1 , are commonly used in communication systems and typically consume large amount of power. In many communication systems, frequency dividers are used to divide VCO signals and generate LO signals for mixers, e.g., as shown in  FIG. 1 . The VCO signals typically have non-rail-to-rail voltage swing whereas the LO signals typically have rail-to-rail voltage swing. Rail-to-rail voltage swing refers to voltage swing between an upper (V DD ) supply voltage and a lower (V SS ) supply voltage, which may be circuit ground. Non-rail-to-rail voltage swing refers to voltage swing over a fraction of the range from V DD  to V SS . 
     Most conventional latches operate with the same input and output voltage swing. For example, a CML latch receives a non-rail-to-rail clock signal and generates a non-rail-to-rail output signal. A CMOS static latch receives a rail-to-rail clock signal and generates a rail-to-rail output signal. A voltage level shifter may be used to convert a non-rail-to-rail signal to a rail-to-rail signal. For example, the voltage level shifter may convert a non-rail-to-rail VCO signal to a rail-to-rail clock signal for a CMOS static latch, as shown in  FIG. 1 . Alternatively, the voltage level shifter may convert a non-rail-to-rail output signal from a CML latch to a rail-to-rail divider signal (not shown in  FIG. 1 ). In any case, the voltage level shifter typically consumes a large amount of power, especially at high frequency. 
       FIG. 2A  shows a schematic diagram of a conventional CML latch  200 , which may be used for a frequency divider. Within conventional CML latch  200 , N-channel metal oxide semiconductor (NMOS) transistors  212  and  222  have their sources coupled to node A and their gates coupled to a clock (CLK) input and an inverted clock (CLKB) input, respectively. A current source  210  is coupled between node A and circuit ground. 
     NMOS transistors  214  and  216  have their sources coupled to the drain of NMOS transistor  212 , their gates coupled to a data (D) input and an inverted data (  D ) input, respectively, and their drains coupled to an inverted data (  Q ) output and a data (Q) output, respectively. NMOS transistors  224  and  226  have their sources coupled to the drain of NMOS transistor  222 , their gates coupled to the Q and  Q  outputs, respectively, and their drains coupled to the  Q  and Q outputs, respectively. A resistor  218  is coupled between the V DD  supply and the  Q  output, and a resistor  228  is coupled between the V DD  supply and the Q output. 
     Conventional CML latch  200  operates as follows. In the tracking mode, NMOS transistor  212  is turned on, NMOS transistor  222  is turned off, and the voltages at the Q and  Q  outputs are determined by a differential input signal on the D and  D  inputs. In the holding mode, NMOS transistor  212  is turned off, NMOS transistor  222  is turned on, and NMOS transistors  224  and  226  maintain the voltages at the Q and  Q  outputs. Current source  210  provides bias current for either NMOS transistors  214  and  216  or NMOS transistors  224  and  226  at any given moment. CML latch  200  thus consumes power all the time. A differential clock signal at the CLK and CLKB inputs, a differential input signal at the D and  D  inputs, and a differential output signal at the Q and  Q  outputs of conventional CML latch  200  are non-rail-to-rail signals. For example, with a 1.3 Volts (V) supply voltage, the clock signal may range from 0.3 to 1.0V, and the input and output signals may range from 0.8 to 1.3V. 
     Conventional CML latch  200  has several disadvantages. First, conventional CML latch  200  accepts a non-rail-to-rail clock signal and provides a non-rail-to-rail output signal. A voltage level shifter is needed to convert the non-rail-to-rail output signal to a rail-to-rail output signal. Second, conventional CML latch  200  consumes high power for good performance. 
       FIGS. 2A and 2B  illustrate an instance of signals present in the prior art DPLL 10 during operation. 
     Within conventional CMOS static latch  250 , an NMOS transistor  252  has its source coupled to circuit ground and its gate coupled to a clock input. An NMOS transistor  254  has its source coupled to the drain of NMOS transistor  252 , its gate coupled to a data input, and its drain coupled to a data output. A P-channel MOS (PMOS) transistor  256  has its gate coupled to the data input and its drain coupled to the data output. A PMOS transistor  258  has its source coupled to the VDD supply, its gate coupled to an inverted clock input, and its drain coupled to the source of PMOS transistor  256 . 
     Conventional CMOS static latch  250  operates as follows. In the tracking mode, MOS transistors  252  and  258  are turned on, and an output signal at the Q output is determined by an input signal at the D input. In the holding mode, MOS transistors  252  and  258  are turned off, and the output signal is maintained by a capacitive load at the Q output. conventional CMOS static latch  250  may not be operable at low frequency due to leakage current in the capacitive load. 
     Conventional CMOS static latch  250  has several disadvantages. First, CMOS static latch  250  accepts a rail-to-rail clock signal. A voltage level shifter is needed to convert a non-rail to-rail rail VCO signal to a rail-to-rail clock signal, as shown in  FIG. 1 . Second, conventional CMOS static latch  250  generates a single-ended output signal, and some applications require a differential output signal. 
     In an aspect, high-speed low-power latches that can accept a non-rail-to-rail or rail-to-rail clock signal and provide a rail-to-rail differential output signal are described herein. No voltage level shifter is needed for these latches. Several designs of the high-speed low-power latches are described below. 
       FIG. 3A  shows a schematic diagram of a design of a high-speed low-power latch  300 . Within latch  300 , an NMOS transistor M 0   310  has its source coupled to circuit ground, its gate coupled to a CLK input, and its drain coupled to node X. An NMOS transistor M 6   312  has its source coupled to node X, its gate coupled to a D input, and its drain coupled to a  Q  output. A PMOS transistor M 7   314  has its source coupled to node Y, its gate coupled to the D input, and its drain coupled to the  Q  output. An NMOS transistor M 8   322  has its source coupled to node X, its gate coupled to a  D  input, and its drain coupled to a Q output. A PMOS transistor M 9   324  has its source coupled to node Y, its gate coupled to the  D  input, and its drain coupled to the Q output. A PMOS transistor M 1   350  has its source coupled to the V DD  supply, its gate coupled to the CLKB input, and its drain coupled to node Y. 
     An NMOS transistor M 2   332  and a PMOS transistor M 3   334  are coupled as an inverter  330  and have their gates coupled together and to the Q output, their drains coupled together and to the  Q  output, and their sources coupled to circuit ground and the V DD  supply, respectively. An NMOS transistor M 4   342  and a PMOS transistor M 5   344  are coupled as an inverter  340  and have their gates coupled together and to the  Q  output, their drains coupled together and to the Q output, and their sources coupled to circuit ground and the V DD  supply, respectively. Inverters  330  and  340  are cross-coupled, and each inverter has its output coupled to the input of the other inverter. 
     Latch  300  receives a differential clock signal composed of a non-inverted clock (Clockp) signal and an inverted clock (Clockn) signal at the CLK and CLKB inputs, respectively. The Clockp and Clockn signals are also referred to as complementary clock signals. The Clockp and Clockn signals may have non-rail-to-rail or rail-to-rail voltage swing and may also have the same or different DC levels. Latch  300  also receives a differential input signal composed of a non-inverted input (Dinp) signal and an inverted input (Dinn) signal at the D and  D  inputs, respectively. Latch  300  provides a differential output signal composed of a non-inverted output (Qoutp) signal and an inverted output (Qoutn) signal at the Q and  Q  outputs, respectively. The complementary input signals and the complementary output signals may have rail-to-rail voltage swing. 
     Latch  300  includes the following three sets of transistors:
         A first set of pull-down transistor M 0  and pull-up transistor M 1 ,   A second set of switching transistors M 6  to M 9 , and   A third set of latching transistors M 2  to M 5 .       

     Latch  300  operates as follows. When the CLK input is high during the tracking mode, the pull-down and pull-up transistors M 0  and M 1  are turned on and are stronger than the latching transistors M 2  to M 5 . The switching transistors M 6  to M 9  set the Q and  Q  outputs according to the complementary input signals at the D and  D  inputs. The latching transistors amplify the voltages at the Q and  Q  outputs to rail-to-rail level. The Q and  Q  outputs thus track the voltages on the D and  D  inputs during the tracking mode. The latching transistors capture the data value at the Q and  Q  outputs when the CLK input transitions from high to low. When the CLK input is low during the holding mode, the pull-down and pull-up transistors M 0  and M 1  are partially turned off and are weaker than the latching transistors. The latching transistors then maintain the Q and  Q  outputs in accordance with the captured data value. 
     The first set of pull-down and pull-up transistors thus controls whether latch  300  operates in the tracking mode or the holding mode based on the clock signal. The second set of switching transistors determines a data value for latch  300  based on the input signal during the tracking mode. The third set of latching transistors provides signal amplification during the tracking mode and stores the data value during the holding mode. The second set of switching transistors provides the output signal during the tracking mode, and the third set of latching transistors provides the output signal during the holding mode. 
       FIG. 3B  shows a schematic diagram of a design of a high-speed low-power latch  302 . Within latch  302 , MOS transistors  310  through  344  are coupled as described above for  FIG. 3A  with the following differences. PMOS transistor M 1 A  314  has its gate coupled to the CLKB input and its source coupled to the V DD  supply. PMOS transistor M 1 B  324  has its gate coupled to the CLKB input and its source coupled to the V DD  supply. PMOS transistor  350  is omitted in latch  302 .
         Latch  302  includes the following three sets of transistors:   A first set of pull-down transistor M 0  and pull-up transistors M 1 A and M 1 B,   A second set of switching transistors M 6  and M 8 , and       

     A third set of latching transistors M 2  to M 5 . 
     Latch  302  operates in similar manner as latch  300  in  FIG. 3A . When the CLK input is high during the tracking mode, the pull-down and pull-up transistors M 0 , M 1 A and M 1 B are turned on and are stronger than the latching transistors M 2  to M 5 . The Q and  Q  outputs are set by the switching transistors M 6  and M 8  according to the complementary input signals at the D and  D  inputs and are amplified by the latching transistors to rail-to-rail level. The latching transistors capture the data value at the Q and  Q  outputs when the CLK input transitions from high to low. The latching transistors maintain the Q and  Q  outputs in accordance with the captured data value during the holding mode when the CLK input is low. 
       FIG. 3C  shows a schematic diagram of a design of a high-speed low-power latch  304 . Within latch  304 , MOS transistors  312  through  350  are coupled as described above for  FIG. 3A  with the following differences. NMOS transistor M 0 A  312  and NMOS transistor M 0 B  322  have their gates coupled to the CLK input and their sources coupled to circuit ground. NMOS transistor  310  is omitted in latch  304 . 
     Latch  304  includes the following three sets of transistors:
         A first set of pull-down transistors M 0 A and M 0 B and pull-up transistor M 1 ,   A second set of switching transistors M 7  and M 9 , and   A third set of latching transistors M 2  to M 5 .       

     Latch  304  operates in similar manner as latch  300  in  FIG. 3A . When the CLK input is high during the tracking mode, the pull-down and pull-up transistors M 0 A, M 0 B and M 1  are turned on and are stronger than the latching transistors M 2  to M 5 . The Q and  Q  outputs are set by the switching transistors M 7  and M 9  according to the complementary input signals at the D and  D  inputs and are amplified by the latching transistors to rail-to-rail level. The latching transistors capture the data value at the Q and  Q  outputs when the CLK input transitions from high to low. The latching transistors maintain the Q and  Q  outputs in accordance with the captured data value during the holding mode when the CLK input is low. 
       FIG. 3D  shows a schematic diagram of a design of a high-speed low-power latch  306 . Latch  306  includes all MOS transistors in latch  302  in  FIG. 3B  except for PMOS transistors  334  and  344 , which are omitted in latch  306 . 
     Latch  306  includes the following three sets of transistors:
         A first set of pull-down transistor M 0  and pull-up transistors M 1 A and M 1 B,   A second set of switching transistors M 6  and M 8 , and   A third set of latching transistors M 2  and M 4 .       

     Latch  306  operates in similar manner as latch  302  in  FIG. 3B . During the tracking mode, latching transistors M 2  and M 4  can provide amplification for high-to-low transition. During the holding mode, the latching transistors maintain the Q and  Q  outputs in accordance with the captured data value. 
       FIG. 3E  shows a schematic diagram of a design of a high-speed low-power latch  308 . Latch  308  includes all MOS transistors in latch  302  in  FIG. 3B  except for NMOS transistors  332  and  342 , which are omitted in latch  308 . 
     Latch  308  includes the following three sets of transistors:
         A first set of pull-down transistor M 0  and pull-up transistors M 1 A and M 1 B,   A second set of switching transistors M 6  and M 8 , and   A third set of latching transistors M 3  and M 5 .       

     Latch  308  operates in similar manner as latch  302  in  FIG. 3B . During the tracking mode, latching transistors M 3  and M 5  can provide amplification for low-to-high transition. During the holding mode, the latching transistors maintain the Q and  Q  outputs in accordance with the captured data value. 
       FIGS. 3A through 3E  show five example designs of the high-speed low-power latches. These latches can operate at high speed and wide frequency range. Switching transistors M 6  to M 9  and latching transistors M 2  to M 5  can operate like switches and may be small MOS transistors. This may then reduce parasitic capacitances on the Q and  Q  outputs and allow the latches to operate at high frequency. These latches can also amplify a non-rail-to-rail clock signal and provide rail-to-rail digital signals with low power consumption. These latches can also provide a differential output signal, which may be required by some applications. 
     The high-speed low-power latches described herein may be used for various circuits and applications and are well suited for frequency dividers implemented on RF integrated circuits (RFICs). These integrated frequency dividers often require high speed but low power. The high-speed low-power latches can enable a frequency divider to divide a non-rail-to-rail clock signal in frequency and amplify the clock signal. Consequently, these latches can eliminate the need for a voltage level shifter to amplify the non-rail-to-rail clock signal to obtain a rail-to-rail clock signal. 
       FIG. 4  shows a design of a process  400  for latching an input signal. A tracking mode or a holding mode for a latch may be selected with a first set of transistors controlled by a clock signal having non-rail-to-rail or rail-to-rail voltage swing (block  412 ). A data value for the latch may be captured during the tracking mode with a second set of transistors controlled by an input signal having rail-to-rail voltage swing (block  414 ). The data value may be stored during the holding mode with a third set of transistors (block  416 ). An output signal having rail-to-rail voltage swing may be provided with the second set of transistors during the tracking mode and with the third set of transistors during the holding mode (block  418 ). 
     In one design, the first set includes at least one pull-down transistor and/or at least one pull-up transistor that may be enabled for the tracking mode or disabled for the holding mode. In one design of block  414 , the transistors in the second set may be switched by the input signal to obtain the output signal during the tracking mode, and the output signal may be amplified with the transistors in the third set during the tracking mode. 
     An output signal from a latch has a duty cycle, which is the percentage of time that the output signal is at logic high in each cycle. It may be desirable to have a duty cycle that is as close to 50% as possible. For example, the output signal from the latch may be used to generate an LO signal, and upconversion or downconversion performance may be adversely impacted by deviations from 50% duty cycle. 
     In the designs shown in  FIGS. 3A through 3E , the settling time during the tracking mode may be varied in order to adjust the duty cycle of the latch output signal. The settling time and hence the duty cycle may be adjusted by performing one or more of the following:
         Change the DC level of the complementary clock signals,   Change the V DD  supply voltage for pull-up transistors M 1 , M 1 A and M 1 B,   Change the V DD  supply voltage for latching transistors M 3  and M 5 ,   Change the V SS  supply voltage for latching transistors M 2  and M 4 , and   Change the V SS  supply voltage for pull-down transistors M 0 , M 0 A and M 0 B.       

     For clarity, adjustment of the setting time and duty cycle by changing the DC level of the complementary clock signals are described below. The settling time during the tracking mode depends on the strength of the pull-down and pull-up transistors M 0  and M 1 , which in turn is dependent on the bias voltages at the gates of these transistors. The gate bias voltages may be set by the DC level of the complementary clock signals. Thus, by tuning the DC level of the complementary clock signals provided to the gates of the pull-down and pull-up transistors, the rising and falling edges of the complementary output signals at the Q and  Q  outputs may be tuned correspondingly. For example, if the DC level is increased, then the pull-down transistor M 0  will become stronger, and the falling edge of the complementary output signals will become faster, and the duty cycle will decrease. The converse is true if the DC level is decreased. 
     In another aspect, the duty cycle of an output signal from a latch may be automatically adjusted with a feedback loop to achieve 50% duty cycle. In one design, the feedback loop senses the duty cycle of a feedback signal derived from the output signal and generates a bias voltage. The DC level of the clock signal is varied by the bias voltage such that the duty cycle can be adjusted to be approximately 50%. 
       FIG. 5  shows a block diagram of a design of an LO signal generator  500  with automatic duty cycle adjustment. In this design, LO signal generator  500  includes a VCO  510 , a bias circuit  520 , a frequency divider  530 , an LO driver  540 , and a control circuit  550 . 
     VCO  510  generates a differential VCO signal composed of Voutp and Voutn signals at a frequency of f 0 . Bias circuit  520  receives the differential VCO signal and provides a differential clock signal composed of Clockp and Clockn signals. Within bias circuit  520 , AC coupling capacitors  522  and  524  receive the Voutp and Voutn signals at a first end and provide the Clockp and Clockn signals at a second end. Resistors  526  and  528  have one end coupled to the second end of capacitors  522  and  524 , respectively, and the other end receiving a bias voltage, Vbias. 
     Frequency divider  530  divides the clock signal by two in frequency and provides a differential divider signal composed of Doutp and Doutn signals at a frequency of f 0 /2 Frequency divider  530  includes two latches  532  and  534  coupled in series. Latch  532  has its CLK and CLKB inputs receiving the Clockp and Clockn signals, respectively, and its D and  D  inputs coupled to the  Q  and Q outputs, respectively, of latch  534 . Latch  534  has its CLK and CLKB inputs receiving the Clockn and Clockp signals, respectively, and its D and  D  inputs coupled to the Q and  Q  outputs, respectively, of latch  532 . Latch  534  provides the Doutp and Doutn signals at its Q and  Q  outputs, respectively. Latches  532  and  534  may each be implemented with latch  300  in  FIG. 3A , latch  302  in  FIG. 3B , latch  304  in  FIG. 3C , latch  306  in  FIG. 3D , or latch  308  in  FIG. 3E . 
     LO driver  540  receives the Doutp and Doutn signals from frequency divider  530  and provides a differential LO signal composed of Loutp and Loutn signals. Within LO driver  540 , inverters  542  and  544  are coupled in series, with the input of inverter  542  receiving the Doutp signal and the output of inverter  544  providing the Loutp signal. Inverters  546  and  548  are coupled in series, with the input of inverter  546  receiving the Doutn signal and the output of inverter  548  providing the Loutn signal. 
     Control circuit  550  senses the duty cycle of a feedback signal and generates the bias voltage such that the duty cycle of the feedback signal is approximately 50%. In general, the feedback signal may be derived based on the divider signal, the LO signal, etc. In the design shown in  FIG. 5 , a P-MOS transistor  564  and an NMOS transistor  566  have their gates coupled together and receiving the feedback signal and their drains coupled together and to node Z. A current source  562  is coupled between the V DD  supply and the source of PMOS transistor  564 . A current source  568  is coupled between the source of NMOS transistor  566  and circuit ground. A capacitor  570  is coupled between node Z and circuit ground. A unity gain buffer  572  has its non-inverting input coupled to node Z, its inverting input coupled to its output, and its output providing the bias voltage. 
     The automatic duty cycle adjustment operates as follows. Current source  562  provides a sourcing current of Ibias, and current source  568  provides a sinking current of Ibias. If the duty cycle is 50%, then current source  562  charges capacitor  570  for half a cycle, current source  568  discharges capacitor  570  for the other half cycle, and capacitor  570  has a net charge of zero in each cycle. If the duty cycle is greater than 50%, then current source  562  charges capacitor  570  for more than half a cycle, and capacitor  570  has a net positive charge in each cycle. The voltage across capacitor  570  thus increases when the duty cycle is greater than 50% and decreases when the duty cycle is less than 50%. Buffer  572  has a gain of one, and the bias voltage is equal to the voltage across capacitor  570 . When the duty cycle is greater than 50%, the bias voltage increases. The higher bias voltage makes the pull-down transistor stronger, which shortens the settling time and reduces the duty cycle. The converse is true when the duty cycle is less than 50%. Control circuit  550  thus changes the bias voltage and hence the common mode voltage of the Clockp and Clockn signals until the feedback signal has 50% duty cycle. 
       FIG. 5  shows one design of control circuit  550  for generating the bias voltage based on the sensed duty cycle of the feedback signal. In another design, the feedback signal may be buffered and coupled to a lowpass filter, which may provide a filtered signal having a voltage that is proportional to the duty cycle of the feedback signal. A comparator may then compare the filtered signal against a reference voltage and may generate the bias voltage based on the comparison result. The bias voltage may also be generated in other manners. A common bias voltage may be generated for both the Clockp and Clockn signals, as shown in  FIG. 5 . Alternatively, different bias voltages may be generated for the Clockp and Clockn signals. 
     As noted above, the duty cycle may also be adjusted by changing the V DD  supply voltage for the pull-up or latching transistors or by changing the V SS  supply voltage for the pull-down or latching transistors. A control circuit may sense the duty cycle of the feedback signal and may vary the V DD  or V SS  supply voltage accordingly. 
       FIG. 6  shows a design of a process  600  for performing automatic duty cycle adjustment. An output signal may be generated with at least one latch operating based on a clock signal (block  612 ). A duty cycle of a feedback signal derived from the output signal may be sensed (block  614 ). A control signal may be generated to adjust the operation of the at least one latch to obtain 50% duty cycle for the feedback signal (block  616 ). The control signal may comprise a bias voltage, a supply voltage, etc. In one design of block  616 , a capacitor may be charged during a first logic level of the feedback signal and discharged during a second logic level of the feedback signal. A bias voltage may be generated based on the voltage across the capacitor. In one design, a DC level of the clock signal may be adjusted based on the bias voltage from the control signal (block  618 ). In other designs, the upper or lower supply voltage for at least one transistor may be adjusted. 
     The clock signal may be divided in frequency with the at least one latch, and the output signal may have a frequency that is a fraction of the frequency of the clock signal (block  620 ). An LO signal and the feedback signal may be generated based on the output signal (block  622 ). 
     The high-speed low-power latches described herein may be used for various systems and applications such as communication, networking, computing, etc. The use of the latches in a wireless communication device is described below. 
       FIG. 7  shows a block diagram of a wireless device  700  that may be used for wireless communication. Wireless device  700  may be a cellular phone, a personal digital assistant (PDA), a terminal, a handset, a wireless modem, a laptop computer, etc. Wireless device  700  is capable of providing bi-directional communication via a transmit path and a receive path. 
     In the transmit path, a digital processor  710  may process data to be transmitted and provide one or more streams of chips to a transceiver unit  720 . Within transceiver unit  720 , one or more digital-to-analog converters (DACs)  722  may convert the one or more streams of chips to one or more analog signals. The analog signal(s) may be filtered by a filter  724 , amplified by a variable gain amplifier (VGA)  726 , and frequency upconverted from baseband to RF by a mixer  728  to generate an upconverted signal. The frequency upconversion may be performed based on an LO signal from a transmit LO signal generator  730 . The upconverted signal may be filtered by a filter  732 , amplified by a power amplifier (PA)  734 , routed through a duplexer (D)  736 , and transmitted via an antenna  740 . 
     In the receive path, an RF signal may be received by antenna  740 , routed through duplexer  736 , amplified by a low noise amplifier (LNA)  744 , filtered by a filter  746 , and frequency downconverted from RF to baseband by a mixer  748  with an LO signal from a receive LO signal generator  750 . The downconverted signal from mixer  748  may be buffered by a buffer (BUF)  752 , filtered by a filter  754 , and digitized by one or more analog-to-digital converters (ADCs)  756  to obtain one or more streams of samples. The sample stream(s) may be provided to digital processor  710  for processing. 
       FIG. 7  shows a specific transceiver design. In general, the signal conditioning for each path may be performed with one or more stages of amplifier, filter, and mixer.  FIG. 7  shows some circuit blocks that may be used for signal conditioning on the transmit and receive paths. The high-speed low-power latches described herein may be used in digital processor  710  and/or transceiver unit  720 . 
     In the design shown in  FIG. 7 , transceiver unit  720  includes two LO signal generators  730  and  750  for the transmit and receive paths, respectively. LO signal generators  730  and  750  may each be implemented with LO signal generator  500  in  FIG. 5  or some other design utilizing the high-speed low-power latches described herein. A phase locked loop (PLL)  760  may receive control information from digital processor  710  and provide controls for VCOs within LO signal generators  730  and  750  to generate LO signals at the proper frequencies. 
     The high-speed low-power latches described herein may be implemented on an IC, an analog IC, an RFIC, a mixed-signal IC, an application specific integrated circuit (ASIC), a printed circuit board (PCB), an electronics device, etc. The high-speed low-power latches may also be fabricated with various IC process technologies such as CMOS, NMOS, PMOS, bipolar junction transistor (BJT), bipolar-CMOS (BiCMOS), silicon germanium (SiGe), gallium arsenide (GaAs), etc. 
     An apparatus implementing the high-speed low-power latches described herein may be a stand-alone device or may be part of a larger device. A device may be (i) a stand-alone IC, (ii) a set of one or more ICs that may include memory ICs for storing data and/or instructions, (iii) an RFIC such as an RF receiver (RFR) or an RF transmitter/receiver (RTR), (iv) an ASIC such as a mobile station modem (MSM), (v) a module that may be embedded within other devices, (vi) a receiver, cellular phone, wireless device, handset, or mobile unit, (vii) etc. 
     In one or more exemplary designs, the functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage media may be any available media that can be accessed by a computer. By way of example, and not limitation, such computer-readable media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer. Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, includes compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk and blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media. 
     The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples and designs described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.