Patent Publication Number: US-10761772-B2

Title: Memory system including a plurality of chips and a selectively-connecting bus

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is based upon and claims the benefit of priority from U.S. Provisional Application No. 62/094,505, filed on Dec. 19, 2014; the entire contents of which are incorporated herein by reference. 
    
    
     FIELD 
     Embodiments described herein relate generally to a memory system. 
     BACKGROUND 
     Among memory systems having a nonvolatile semiconductor memory such as a NAND flash memory incorporated therein, there are ones having a plurality of command queues. For these, it is desired to appropriately process commands respectively stored in the plurality of command queues. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a block diagram showing the configuration of a memory system according to a first embodiment; 
         FIG. 2  is a diagram showing the connection configuration of a NAND I/F and a NAND flash memory in the first embodiment; 
         FIG. 3  is a block diagram showing the configuration of a NAND memory chip in the first embodiment; 
         FIG. 4  is a block diagram showing the configuration of the NAND I/F in the first embodiment; 
         FIG. 5  is a timing chart showing the operation of the memory system according to the first embodiment; 
         FIG. 6  is a diagram showing the configuration of a NAND I/F in a second embodiment; 
         FIG. 7  is a timing chart showing the operation of a memory system according to the second embodiment; 
         FIG. 8  is a diagram showing the configuration of a NAND I/F in a third embodiment; and 
         FIG. 9  is a flow chart showing the operation of a memory system according to the third embodiment. 
     
    
    
     DETAILED DESCRIPTION 
     In general, according to one embodiment, there is provided a memory system including a nonvolatile semiconductor memory, a bus, and a controller. The nonvolatile semiconductor memory includes a first chip and a second chip. The bus is connected to the first chip and the second chip in common. The controller issues a first command to the first chip via the bus. The controller queues a second command whose access destination is identified to be the first chip at a first timing while the first chip is executing the first command. The controller issues to the second chip a third command whose access destination is identified to be the second chip after the first timing, via the bus in priority over the second command, while the first chip is executing the first command or after the execution of the first command finishes. 
     Exemplary embodiments of a memory system will be explained below in detail with reference to the accompanying drawings. The present invention is not limited to the following embodiments. 
     First Embodiment 
     A memory system  100  according to the first embodiment will be described using  FIG. 1 .  FIG. 1  is a block diagram showing the configuration of the memory system  100 . The memory system  100  is connected to a host  1  via a communication path  3  and functions as an external storage device for the host  1 . The memory system  100  is, for example, a flash memory for embedded use compliant with UFS (Universal Flash Storage) Standard, eMMC (embedded Multi Media Card) Standard, or the like, or an SSD (Solid State Drive). The host  1  is, for example, a personal computer, a mobile telephone, an imaging device, or the like. 
     The memory system  100  has a NAND flash memory (nonvolatile semiconductor memory)  20  and a controller  10 . 
     The NAND flash memory  20  stores, for example, management information of the memory system  100  and user data therein. The management information of the memory system  100  includes a logical-physical conversion table (L2P table). The logical-physical conversion table (L2P table) is address conversion information which maps logical addresses (LBA: Logical Block Address) that the host  1  uses when accessing the memory system  100  to physical addresses in the NAND flash memory  20  (each=a block address+a page address+an intra-page storage location). 
     The NAND flash memory  20  includes multiple NAND memory chips  21 - 0  to  21 - 3 . The NAND memory chips  21 - 0  to  21 - 3  can operate independently of each other. Although  FIG. 1  illustrates the case where the NAND flash memory  20  includes four NAND memory chips  21 - 0  to  21 - 3 , the number of NAND memory chips included in the NAND flash memory  20  may be three or less, or five or greater. 
     The controller  10  has a CPU (processor)  11 , a host interface (host I/F)  12 , a buffer memory  13 , and a NAND interface (NAND I/F)  14 . 
     The CPU  11  controls the memory system  100  overall. The CPU  11  includes firmware FW and performs control operation according to the firmware FW. For example, the CPU  11  performs control over reading data from the NAND flash memory  20  according to a read request from the host  1 . 
     The buffer memory  13  can be used as a work area of the CPU  11 . For example, the CPU  11  reads the logical-physical conversion table (L2P table) from the NAND flash memory  20  to store into the buffer memory  13 . For example, the CPU  11  performs logical-physical conversion processing to convert the logical address included in a read request from the host  1  into a physical address using the logical-physical conversion table (L2P table) stored in the buffer memory  13 . 
     Further, the buffer memory  13  can be used as a buffer for storing data. For example, the buffer memory  13  is used as a buffer for storing data read from the NAND memory chips  21 . The buffer memory  13  is constituted by, e.g., an SRAM or DRAM, but may be constituted by a register or the like. 
     The host interface (host I/F)  12  is an interface to connect to the host  1 . When receiving a request from the host  1 , the host I/F  12  transfers the received request to the CPU  11 . 
     The NAND I/F  14  reads/writes data and management information from/into the NAND flash memory  20  under control of the CPU  11 . The details of the NAND I/F  14  will be described later. 
     The memory system  100  can be a system compliant with the UFS standard. The UFS standard can incorporate a multitask system as a standard feature. Hence, in the memory system  100 , the controller  10  may consecutively receive multiple requests (multiple host commands) from the host  1 . At this time, the controller  10  needs to process the multiple requests consecutively received from the host  1  efficiently internally to respond to the host  1  quickly. It needs to be considered how efficiently the controller  10  can process the multiple requests so as to reduce the total processing time from when the controller  10  receives the multiple requests until returning the respective responses to the requests to the host  1  rather than concentrating on one request to finish processing it quickly. To this end, the performance of transfer between the controller  10  and the NAND flash memory  20  needs to be improved by efficiently controlling the NAND memory chips  21 - 0  to  21 - 3  in the NAND flash memory  20 . That is, a technique of efficiently controlling multiple NAND memory chips  21 - 0  to  21 - 3  to operate is required for the controller  10 . 
     In the memory system  100 , multiple NAND memory chips  21 - 0  to  21 - 3  are incorporated for one controller  10 . For example, as shown in  FIG. 2 , the NAND I/F  14  has the NAND memory chips  21 - 0  to  21 - 3  share one channel of an IO bus IO[7:0], a DQS line, a DQSZ line, an REZ line, an RE line, a WEZ line, an ALE line, and a CLE line.  FIG. 2  is a diagram showing the connection configuration of the NAND I/F  14  and the NAND flash memory  20 . The one channel includes the IO bus IO[7:0] and the NAND memory chips  21 - 0  to  21 - 3  sharing the IO bus  10 [7:0]. 
     Each NAND memory chip  21 - 0  to  21 - 3  outputs an Ry/By signal RBZ indicating whether the memory chip is in a busy state or a ready state to the NAND I/F  14 . Let RBZ=L indicate being in the busy state and RBZ=H indicate being in the ready state. 
     Further, the NAND I/F  14  switches a NAND memory chip to be accessed from among the multiple NAND memory chips  21 - 0  to  21 - 3  with chip enable signals CEZ 0  to CEZ 3  (hereinafter referred to as CE 0  to CE 3 ). One chip enable signal from among the chip enable signals CE 0  to CE 3  selectively becomes a low (L) level while the other chip enable signals are kept at a high (H) level, and the NAND I/F  14  can selectively access the NAND memory chip  21  to which the chip enable signal of the L level is supplied. 
     For example, the NAND I/F  14  transfers a command (and data) to one NAND memory chip  21  selected with the chip enable signal CE 0  to CE 3  via the one IO bus IO[7:0]. Or the NAND I/F  14  receives data (or a response) transferred from one NAND memory chip  21  selected with the chip enable signal CE 0  to CE 3  via the one IO bus IO[7:0]. 
     Next, the internal configuration of each NAND memory chip  21  will be described using  FIG. 3 .  FIG. 3  is a diagram showing the configuration of the NAND memory chip  21 . 
     In the NAND memory chip  21 , for example, when receiving the chip enable signal of the L level, a control circuit  21   e  can accept a command from the NAND I/F  14  and control each part according to the command. When receiving the chip enable signal of the H level, the control circuit  21   e  does not accept a command from the NAND I/F  14 . 
     The NAND memory chip  21  has a memory cell array  21   a  and a page buffer  21   b . The memory cell array  21   a  is formed of multiple memory cells arranged in a matrix. Each individual memory cell may be a binary memory (SLC: Single Level Cell) to store one bit per memory cell, or a multivalued memory (MLC: Multi Level Cell) to store two or more bits per memory cell. Each individual memory cell, if being a multivalued memory, can store a multiple value using an upper page and a lower page. The memory cell array  21   a  comprises multiple physical blocks that are units for erasure, and each individual physical block is configured with multiple physical pages (hereinafter simply referred to as pages) that are units for reading and writing. 
     The page buffer  21   b  has, e.g., one page worth of storage capacity. The page buffer  21   b  is used as a buffer for the NAND memory chip  21  to transmit/receive data to/from the NAND I/F  14 . Further, the page buffer  21   b  is used as a buffer for the NAND memory chip  21  to input/output data to/from the memory cell array  21   a.    
     For example, where a command according to a read request is executed, the NAND memory chip  21  receives a read command (Cmd00h-Adr-Cmd30h) from the NAND I/F  14 . Cmd00h and Cmd30h are commands to the NAND memory chip  21 . Adr is an address in the NAND memory chip  21  that is the target of the read command. When receiving a read command, the NAND memory chip  21  reads data of interest from the memory cell array  21   a  into the page buffer  21   b . In other words, after receiving a read command, the NAND memory chip  21  can perform internal operation according to the read command without using the one IO bus IO[7:0] (that is, without access from the NAND I/F  14 ). The NAND memory chip  21  outputs the Ry/By signal RBZ set to indicate the busy state while reading data of interest from the memory cell array  21   a  into the page buffer  21   b . After finishing reading data of interest from the memory cell array  21   a  into the page buffer  21   b , the NAND memory chip  21  switches the Ry/By signal RBZ from the busy state to the ready state. The NAND memory chip  21  transfers the data stored in the page buffer  21   b  to the NAND I/F  14  via the one IO bus IO[7:0]. 
     Next, the NAND I/F  14  will be described using  FIGS. 4 and 5 .  FIG. 4  is a diagram showing the configuration of the NAND I/F  14 .  FIG. 5  is a timing chart showing the operation of the memory system  100 . 
     The NAND I/F  14  has multiple command queues  14   d - 0  to  14   d - 3  and a control circuit  14   c  as shown in  FIG. 4 . Although  FIG. 4  illustrates the case where the NAND I/F  14  has four command queues  14   d - 0  to  14   d - 3 , the number of command queues  14   d  that the NAND I/F  14  has may be three or less, or five or greater. Further, although  FIG. 4  illustrates the case where the queue depth of each command queue  14   d  is at five stages, it may be at four or fewer stages or six or more stages. 
     Each command queue  14   d  queues commands supplied from the CPU  11  therein. Each command queue  14   d  is a queue buffer having a FIFO (First In First Out) structure, and the commands are dequeued in the order in which they were queued. Each command queue  14   d  corresponds to one request, and multiple subcommands into which the one request is divided can be queued therein. Commands queued in the command queue  14   d  move closer by one to the head each time the command at the head queue is dequeued. The multiple command queues  14   d - 0  to  14   d - 3  are connected serially and configured such that the dequeued command is queued into the command queue  14   d  of the next stage. That is, the command queues  14   d - 0  to  14   d - 3  as a whole can function as one command queue. 
     The CPU  11  realizes which command queue  14   d  of the command queues  14   d - 0  to  14   d - 3  is empty. The CPU  11  divides a request received by the host I/F  12  to create multiple subcommands and queues the created subcommands into an empty command queue  14   d.    
     For example, commands dequeued from the command queue  14   d - 0  are executed by the control circuit  14   c . The control circuit  14   c  has an access control circuit  14   a  and an access processing circuit  14   b . The access control circuit  14   a  puts commands dequeued from the command queue  14   d  into the access processing circuit  14   b  to make them executable. The access processing circuit  14   b  executes the inputted command to access the NAND memory chip  21 . While the control circuit  14   c  is executing the command (accessing the NAND memory chip  21 ), the CPU  11  can queue the next command into an empty command queue  14   d . For example, where commands are sequentially queued into the command queues  14   d - 0  to  14   d - 3 , commands queued in the command queue  14   d - 0  are put into the access processing circuit  14   b , and after the execution thereof finishes, commands queued in the command queue  14   d - 1  are put into the access processing circuit  14   b  through the command queue  14   d - 0  to be executed. After the execution of commands queued in the command queue  14   d - 1  finishes, commands queued in the command queue  14   d - 2  are put into the access processing circuit  14   b  through the command queues  14   d - 1 ,  14   d - 0  to be executed. This processing is sequentially repeated for the execution of commands. Thus, commands can be consecutively executed for the NAND flash memory  20 . 
     For example, as shown in  FIG. 5 , when read requests  201 ,  204 ,  207 ,  210  are consecutively received and transferred by the host I/F  12  to the CPU  11 , the CPU  11  sequentially performs respective preprocessing  202 ,  205 ,  208 ,  211  corresponding to the read requests  201 ,  204 ,  207 ,  210 . 
     For example, the preprocessing  202  corresponding to the read request  201  includes logical-physical conversion processing and division processing. The logical-physical conversion processing converts the logical address included in the read request  201  into a physical address using the logical-physical conversion table (L2P table) stored in the buffer memory  13 . The division processing divides the read request  201  to create multiple subcommands  203   a  to  203   c . The multiple subcommands  203   a  to  203   c  include access to the NAND memory chip  21 - 0  and correspond to the chip enable signal CE 0 . The multiple commands include a read setup (CE 0 ReadSetUp) command  203   a , a ready wait (CE 0 ReadyWait) command  203   b , and a read data out (CE 0 ReadDataOut) command  203   c . The read setup command  203   a , ready wait command  203   b , and read data out command  203   c  are ones that should be executed in this order. The read setup command  203   a , ready wait command  203   b , and read data out command  203   c  form one read command (first command)  203 . 
     Likewise, the preprocessing  205  corresponding to the read request  204  divides the read request  204  to create multiple subcommands  206   a  to  206   c . The multiple subcommands  206   a  to  206   c  include access to the NAND memory chip  21 - 0  and correspond to the chip enable signal CE 0 . The multiple subcommands include a read setup (CE 0 ReadSetUp) command  206   a , a ready wait (CE 0 ReadyWait) command  206   b , and a read data out (CE 0 ReadDataOut) command  206   c . The read setup command  206   a , ready wait command  206   b , and read data out command  206   c  are ones that should be executed in this order. The read setup command  206   a , ready wait command  206   b , and read data out command  206   c  form one read command (second command)  206 . 
     The preprocessing  208  corresponding to the read request  207  divides the read request  207  to create multiple subcommands  209   a  to  209   c . The multiple subcommands  209   a  to  209   c  include access to the NAND memory chip  21 - 1  and correspond to the chip enable signal CE 1 . The multiple subcommands include a read setup (CE 1 ReadSetUp) command  209   a , a ready wait (CE 1 ReadyWait) command  209   b , and a read data out (CE 1 ReadDataOut) command  209   c . The read setup command  209   a , ready wait command  209   b , and read data out command  209   c  are ones that should be executed in this order. The read setup command  209   a , ready wait command  209   b , and read data out command  209   c  form one read command  209 . 
     The preprocessing  211  corresponding to the read request  210  divides the read request  210  to create multiple subcommands  212   a  to  212   c . The multiple subcommands  212   a  to  212   c  include access to the NAND memory chip  21 - 2  and correspond to the chip enable signal CE 2 . The multiple subcommands include a read setup (CE 2 ReadSetUp) command  212   a , a ready wait (CE 2 ReadyWait) command  212   b , and a read data out (CE 2 ReadDataOut) command  212   c . The read setup command  212   a , ready wait command  212   b , and read data out command  212   c  are ones that should be executed in this order. The read setup command  212   a , ready wait command  212   b , and read data out command  212   c  form one read command  212 . 
     Here, consider the case where the NAND I/F  14  processes the read commands  203 ,  206 ,  209 ,  212  in the order in which the corresponding read requests  201 ,  204 ,  207 ,  210  are received by the host I/F  12 . In this case, because the subcommands  203   a  to  203   c  are queued in the command queue  14   d - 0 , empty command queues are the command queues  14   d - 1 ,  14   d - 2 ,  14   d - 3 . The read commands  206  ( 206   a  to  206   c ),  209  ( 209   a  to  209   c ),  212  ( 212   a  to  212   c ), for which the respective preprocessing  205 ,  208 ,  211  sequentially finish during the execution of the read command  203 , are queued in the empty command queues  14   d - 1 ,  14   d - 2 ,  14   d - 3  respectively. Then the control circuit  14   c  executes the read command  206  after finishing the execution of the read command  203 , executes the read command  209  after finishing the execution of the read command  206 , and executes the read command  212  after finishing the execution of the read command  209 . Thus, as to the multiple read requests  201 ,  204 ,  207 ,  210  consecutively received by the host I/F  12 , the time PT 1  from when the first read request  201  is received until the execution of the command corresponding to the last read request  201  finishes tends to be elongated. 
     For example, if the request from the host  1  is a random read request, it is difficult to realize the access destination of the command until the logical-physical conversion processing finishes. During the execution of the read command  203  (during access to the NAND memory chip  21 - 0 ), immediately after the preprocessing  208  finishes, the NAND I/F  14  can realize that the access destination of the read command  209  is the NAND memory chip  21 - 1  (corresponding to the chip enable signal CE 1 ) by referring to the result of the logical-physical conversion processing (such as a physical address). At this time, because of being in an idle state, the NAND memory chip  21 - 1  can accept a command immediately, but is kept waiting due to the processing order of the command queues  14   d , so that the total processing time PT 1  of the four read requests  201 ,  204 ,  207 ,  210  is elongated. 
     Going back to the past, at the time when the first read command  203  is queued into the command queue  14   d - 0 , the logical-physical conversion processing for the subsequent read commands  206 ,  209 ,  212  has not finished, so that access destinations in the NAND memory chips  21  are not known, and hence the NAND I/F  14  cannot even wait. Further, because it is unknown when the next host command will come in, the NAND I/F  14  cannot even wait. Although it is a multitask system, requests each in the form of a single command sequentially come in from the host  1 , and hence the controller  10  has to process them sequentially, which may not be efficient in processing multiple requests (multiple host commands) consecutively received from the host  1 . 
     Accordingly, in the present embodiment, a priority command queue  14   e  having priority over the command queues  14   d  is provided in the NAND I/F  14 , and if a command including access to a chip other than the chip currently being accessed is queued into the priority command queue  14   e , then that command is executed in priority over commands from the command queues  14   d , thereby improving processing efficiency (transfer performance) for multiple requests from the host  1 . Hereinafter the command queues  14   d  are called ordinary command queues  14   d  in order to distinguish from the priority command queue  14   e.    
     Specifically, as shown in  FIG. 4 , the NAND I/F  14  further has multiple priority command queues  14   e - 0  to  14   e - 2 . Although  FIG. 4  illustrates the case where the NAND I/F  14  has three priority command queues  14   e - 0  to  14   e - 2 , the number of priority command queues  14   e  that the NAND I/F  14  has may be two or less, or four or greater. Further, although  FIG. 4  illustrates the case where the queue depth of each priority command queue  14   e  is at five stages, it may be at four or fewer stages or six or more stages. 
     Each priority command queue  14   e  queues commands supplied from the CPU  11  therein. Each priority command queue  14   e  is a queue buffer having a FIFO (First In First Out) structure, and the commands are dequeued in the order in which they were queued. Each priority command queue  14   e  corresponds to one request, and some (e.g., the head subcommand) of multiple subcommands into which the one request is divided can be queued therein. Subcommands queued in the priority command queue  14   e  move closer by one to the head each time the command at the head queue is dequeued. The multiple priority command queues  14   e - 0  to  14   e - 2  are connected serially and configured such that the dequeued command is queued into the priority command queue  14   e  of the next stage. That is, the priority command queues  14   e - 0  to  14   e - 2  as a whole can function as one command queue. 
     The CPU  11  realizes which command queue  14   e  of the priority command queues  14   e - 0  to  14   e - 2  is empty. The CPU  11  divides a request received by the host I/F  12  to create multiple subcommands and determines whether the access destination of the created subcommands is different from that of the command currently being executed. If the access destination of the created subcommands is different from that of the command currently being executed, the CPU  11  queues the head subcommand (read setup command) of those subcommands into an empty priority command queue  14   e . At the same time, the CPU  11  queues the second and later subcommands (ready wait command, read data out command) of those subcommands into an empty ordinary command queue  14   d.    
     The access control circuit  14   a  in the control circuit  14   c  grants an access right to a command from a selected command queue of the ordinary command queues  14   d  and the priority command queues  14   e . The access right is a right to access the NAND flash memory  20  via the access processing circuit  14   b . The access processing circuit  14   b  executes the command granted an access right and accesses the NAND memory chip  21  specified by the command. 
     For example, when a command is queued into an ordinary command queue  14   d , the control circuit  14   c  grants an access right to the command from the ordinary command queue  14   d  and accesses a given NAND memory chip  21  according to the command. While accessing the NAND memory chip  21 , when realizing that a command according to a subsequent host command (request from the host  1 ) has been queued into a priority command queue  14   e , the control circuit  14   c  grants an access right to the command from the priority command queue  14   e  after finishing the execution of multiple subcommands into which one request was divided (i.e., one read command) and executes the command. The control circuit  14   c  continues executing until switching ordinary command queues  14   d  occurs, which time is good to stop. 
     For example, at the timing when switching from the ordinary command queue  14   d - 0  to the ordinary command queue  14   d - 1  occurs, the next access right is passed to the priority command queue  14   e , so that the control circuit  14   c  can execute a command from the priority command queue  14   e  in priority over others. When finishing executing all commands from the priority command queue  14   e , the access right returns to a command from the ordinary command queue  14   d . Thereafter, if at least one command is queued into a priority command queue, the control circuit  14   c  passes the access right to the command from the priority command queue  14   e  to execute that command. 
     That is, if a subcommand is queued into a priority command queue  14   e  during the execution of multiple subcommands (one read command) into which one request was divided and which have been queued in an ordinary command queue  14   d , after the execution of the read command finishes, the access control circuit  14   a  in the control circuit  14   c  switches from a first state to a second state to have the subcommand in the priority command queue  14   e  executed. The first state is one where the access right is granted to a command (or subcommand) from the ordinary command queue  14   d . The second state is one where the access right is granted to a command (or subcommand) from the priority command queue  14   e.    
     Then, after the execution of the command from the priority command queue  14   e , if there is a command queued next in the priority command queue  14   e , the access control circuit  14   a  has that command executed. After the execution of the command in the priority command queue  14   e , if there is not another command queued in the priority command queue  14   e , the access control circuit  14   a  returns from the second state to the first state to have the command queued next to the already-executed command in the ordinary command queue  14   d  executed. 
     For example, as shown in  FIG. 5 , when the first read request  201  of multiple read requests to be consecutively received is received by the host I/F  12  and transferred to the CPU  11 , the CPU  11  performs the preprocessing  202  such as the logical-physical conversion processing to realize that the NAND memory chip, the access destination, is  21 - 0  corresponding to the chip enable signal CE 0 . At the same time, the CPU  11  divides the read request  201  to create multiple subcommands  203   a  to  203   c . The CPU  11  queues the subcommands  203   a  to  203   c  into the ordinary command queue  14   d - 0  (see  FIG. 4 ). The control circuit  14   c  of the NAND I/F  14  grants the access right to the command queued in the ordinary command queue  14   d - 0 . Accordingly, the control circuit  14   c  executes the read command  206 . For example, the control circuit  14   c  dequeues the read setup (CE 0 ReadSetUp) command  203   a  from the ordinary command queue  14   d - 0  to execute. 
     The control circuit  14   c  selectively makes the chip enable signal CE 0  active and accesses the NAND memory chip  21 - 0  according to the read setup (CE 0 ReadSetUp) command  203   a . The control circuit  14   c  transfers a read command (Cmd00h-Adr-Cmd30h) to the NAND memory chip  21 - 0  according to the read setup (CE 0 ReadSetUp) command  203   a . That is, the control circuit  14   c  issues the read command (Cmd00h-Adr-Cmd30h) to the NAND memory chip  21 - 0  via the IC bus IO[7:0]. The read command (Cmd00h-Adr-Cmd30h) instructs the NAND memory chip  21  to perform read processing for, e.g., 4 KB of data. 
     After finishing the execution of the read setup (CE 0 ReadSetUp) command  203   a , the control circuit  14   c  dequeues the ready wait (CE 0 ReadyWait) command  203   b  from the ordinary command queue  14   d - 0  to execute. The control circuit  14   c  waits for the Ry/By signal RBZ from the NAND memory chip  21 - 0  to switch from the busy state to the ready state according to the ready wait (CE 0 ReadyWait) command  203   b.    
     When realizing that the Ry/By signal RBZ has switched from the busy state to the ready state, the control circuit  14   c  finishes the ready wait (CE 0 ReadyWait) command  203   b  and dequeues the read data out (CE 0 ReadDataOut) command  203   c  from the ordinary command queue  14   d - 0  to execute. The control circuit  14   c  reads data from the NAND memory chip  21 - 0  according to the read data out (CE 0 ReadDataOut) command  203   c  and transfers the read data to a read buffer in the buffer memory  13  via the CPU  11 . As such, the control circuit  14   c  issues the read command  203  (the read setup command  203   a , ready wait command  203   b , read data out command  203   c ) to the NAND memory chip  21 - 0  via the IO bus IO[7:0]. 
     In contrast, during the execution of the read command  203 , when the next read request  204  from the host  1  is received and transferred by the host I/F  12  to the CPU  11 , likewise the CPU  11  performs the preprocessing  205  such as the logical-physical conversion processing to realize that the NAND memory chip, the access destination, is  21 - 0  corresponding to the chip enable signal CE 0 . At the same time, the CPU  11  divides the read request  204  to create multiple subcommands  206   a  to  206   c . Because the read command  203  from the ordinary command queue  14   d - 0  is being executed (the NAND memory chip  21 - 0  is being accessed), the CPU  11  queues the subcommands  206   a  to  206   c  into the ordinary command queue  14   d - 1  (see  FIG. 4 ). 
     In addition, when the next read request  207  is received and transferred by the host I/F  12  to the CPU  11 , likewise the CPU  11  performs the preprocessing  208  such as the logical-physical conversion processing to realize that the NAND memory chip, the access destination, is the NAND memory chip  21 - 1  corresponding to the chip enable signal CE 1 . At the same time, the CPU  11  divides the read request  207  to create multiple subcommands  209   a  to  209   c . Although the read command  203  from the ordinary command queue  14   d  is being executed (the NAND memory chip  21 - 0  is being accessed), because the NAND memory chip  21 - 1  corresponding to the chip enable signal CE 1  is in an idle state, the CPU  11  queues the read setup (CE 1 ReadSetUp) command  209   a , the head, of the subcommands  209   a  to  209   c  into the priority command queue  14   e - 0  (see  FIG. 4 ). 
     Further, when the next read request  210  is received and transferred by the host I/F  12  to the CPU  11 , likewise the CPU  11  performs the preprocessing  211  such as the logical-physical conversion processing to realize that the NAND memory chip, the access destination, is the NAND memory chip  21 - 2  corresponding to the chip enable signal CE 2 . At the same time, the CPU  11  divides the read request  210  to create multiple subcommands  212   a  to  212   c . Although the subcommands  203   a  to  203   c  from the ordinary command queue  14   d  are being executed (the NAND memory chip  21 - 0  is being accessed), because the NAND memory chip  21 - 2  corresponding to the chip enable signal CE 2  is in the idle state, the CPU  11  queues the read setup (CE 2 ReadSetUp) command  212   a , the head, of the subcommands  212   a  to  212   c  into the priority command queue  14   e - 1  (see  FIG. 4 ). 
     As such, the read setup command, the head, of the multiple subcommands into which one request is divided is queued into the priority command queue  14   e . By executing the read setup command in advance of the rest to transfer the read command (Cmd00h-Adr-Cmd30h) to the NAND memory chip  21 , the control circuit  14   c  can have the NAND memory chip  21  internally operate according to the read command (Cmd00h-Adr-Cmd30h), without accessing the NAND memory chip  21 . By accessing another NAND memory chip  21  during this time, the NAND flash memory  20  can be made to operate efficiently. 
     When the execution of the subcommands  203   a  to  203   c  from the ordinary command queue  14   d - 0  (i.e., one read command  203 ) finishes, the control circuit  14   c  realizes that commands are queued in the priority command queues  14   e - 0 ,  14   e - 1 . The control circuit  14   c  grants the access right to commands from the priority command queue  14   e  and dequeues the read setup (CE 1 ReadSetUp) command  209   a  from the priority command queue  14   e - 0  to execute. The control circuit  14   c  selectively makes the chip enable signal CE 1  active and accesses the NAND memory chip  21 - 1  according to the read setup (CE 1 ReadSetUp) command  209   a . The control circuit  14   c  transfers a read command (Cmd00h-Adr-Cmd30h) to the NAND memory chip  21 - 1  according to the read setup (CE 1 ReadSetUp) command  209   a . That is, the control circuit  14   c  issues the read command (Cmd00h-Adr-Cmd30h) to the NAND memory chip  21 - 1  via the TO bus IO[7:0]. The read command (Cmd00h-Adr-Cmd30h) instructs the NAND memory chip  21  to perform read processing for, e.g., 4 KB of data. As such, the control circuit  14   c  issues the read setup command  209   a  to the NAND memory chip  21 - 1  via the IO bus IO[7:0]. 
     When finishing the execution of the read setup (CE 1 ReadSetUp) command  209   a , the control circuit  14   c  dequeues the read setup (CE 2 ReadSetUp) command  212   a  from the priority command queue  14   e - 1  via the priority command queue  14   e - 0  to execute. The control circuit  14   c  selectively makes the chip enable signal CE 2  active and accesses the NAND memory chip  21 - 2  according to the read setup (CE 2 ReadSetUp) command  212   a . The control circuit  14   c  transfers a read command (Cmd00h-Adr-Cmd30h) to the NAND memory chip  21 - 2  according to the read setup (CE 2 ReadSetUp) command  212   a . That is, the control circuit  14   c  issues the read command (Cmd00h-Adr-Cmd30h) to the NAND memory chip  21 - 2  via the TO bus IO[7:0]. The read command (Cmd00h-Adr-Cmd30h) instructs the NAND memory chip  21  to perform read processing for, e.g., 4 KB of data. As such, the control circuit  14   c  issues the read setup command  212   a  to the NAND memory chip  21 - 2  via the TO bus IO[7:0]. 
     When finishing the execution of the read setup (CE 2 ReadSetUp) command  212   a , the control circuit  14   c  gives the access right back to commands from the ordinary command queue  14   d  and executes the subcommands  206   a  to  206   c  queued next to the subcommands  203   a  to  203   c  in the ordinary command queue  14   d . The control circuit  14   c  transfers a read command (Cmd00h-Adr-Cmd30h) to the NAND memory chip  21 - 0  according to the read setup (CE 0 ReadSetUp) command  206   a . That is, the control circuit  14   c  issues the read command (Cmd00h-Adr-Cmd30h) to the NAND memory chip  21 - 0  via the IO bus IO[7:0]. Then the control circuit  14   c  sequentially dequeues the ready wait (CE 0 ReadyWait) command  206   b  and read data out (CE 0 ReadDataOut) command  206   c  from the ordinary command queue  14   d - 1  via the ordinary command queue  14   d - 0  to execute. As such, the control circuit  14   c  issues the read command  206  (the read setup command  206   a , ready wait command  206   b , and read data out command  206   c ) to the NAND memory chip  21 - 0  via the IO bus IO[7:0]. 
     When finishing the read data out (CE 0 ReadDataOut) command  206   c , the control circuit  14   c  dequeues the ready wait (CE 1 ReadyWait) command  209   b  from the ordinary command queue  14   d - 2  via the ordinary command queues  14   d - 1 ,  14   d - 0  to execute. At this time, because the read setup (CE 1 ReadSetUp) command  209   a , the head, of the subcommands  209   a  to  209   c  was issued in advance, the busy time of the NAND memory chip  21 - 1  ended during other processing, so that the NAND memory chip  21 - 1  is ready. When selectively making the chip enable signal CE 1  active, the control circuit  14   c  can realize that the Ry/By signal RBZ from the NAND memory chip  21 - 0  has switched from the busy state to the ready state and finish the ready wait (CE 1 ReadyWait) command  209   b . The control circuit  14   c  dequeues the read data out (CE 1 ReadDataOut) command  209   c  from the ordinary command queue  14   d - 2  via the ordinary command queues  14   d - 1 ,  14   d - 0  to execute. The control circuit  14   c  transfers the transferred data to the read buffer in the buffer memory  13  via the CPU  11  according to the read data out (CE 1 ReadDataOut) command  209   c . As such, the control circuit  14   c  issues the ready wait command  209   b , read data out command  209   c  to the NAND memory chip  21 - 0  via the IO bus IO[7:0]. 
     When finishing the read data out (CE 1 ReadDataOut) command  209   c , the control circuit  14   c  dequeues the ready wait (CE 2 ReadyWait) command  212   b  from the ordinary command queue  14   d - 3  via the ordinary command queues  14   d - 2 ,  14   d - 1 ,  14   d - 0  to execute. At this time, because the read setup (CE 2 ReadSetUp) command  212   a , the head, of the subcommands  212   a  to  212   c  was issued in advance, the busy time of the NAND memory chip  21 - 2  ended during other processing, so that the NAND memory chip  21 - 2  is ready. When selectively making the chip enable signal CE 2  active, the control circuit  14   c  can realize that the Ry/By signal RBZ from the NAND memory chip  21 - 0  has switched from the busy state to the ready state and finish the ready wait (CE 2 ReadyWait) command  212   b . The control circuit  14   c  dequeues the read data out (CE 2 ReadDataOut) command  212   c  from the ordinary command queue  14   d - 3  via the ordinary command queues  14   d - 2 ,  14   d - 1 ,  14   d - 0  to execute. The control circuit  14   c  transfers the transferred data to the read buffer in the buffer memory  13  via the CPU  11  according to the read data out (CE 2 ReadDataOut) command  212   c . As such, the control circuit  14   c  issues the ready wait command  212   b , read data out command  212   c  to the NAND memory chip  21 - 0  via the IO bus IO[7:0]. Here, processing for the four read requests  201 ,  204 ,  207 ,  210  finishes. 
     As described above, in the first embodiment, the priority command queues  14   e  having priority over the ordinary command queues  14   d  are provided in the NAND I/F  14 . If a command including access to a chip other than the chip currently being accessed by a command from a command queue  14   d  is queued into the priority command queue  14   e , then the control circuit  14   c  executes that command in priority over commands in the ordinary command queues  14   d . Thus, a command (or subcommand) subsequent but including access to a NAND memory chip  21  being in the idle state can be executed in priority over others, so that the multiple NAND memory chips can be made to operate efficiently in parallel, thus improving overall transfer performance. Therefore, as compared with the processing time PT 1  in the case of processing the read commands  203 ,  206 ,  209 ,  212  in the order in which the corresponding read requests  201 ,  204 ,  207 ,  210  are received, the total processing time PT 2  from when the controller  10  receives multiple requests until returning the respective responses to the requests to the host  1  can be shortened by an amount ΔPT. 
     For example, where requests from the host  1  are random read requests (for a unit of 4 KB), respective read processing according to multiple read requests consecutively received by the host I/F  12  can be efficiently performed for multiple NAND memory chips  21  in parallel. Thus, in the memory system  100 , the number of times of read processing for 4 KB of data that can be performed per unit time can be improved. For example, if the number of NAND memory chips incorporated in the memory system  100  is four, the processing time of the controller  10  can be shortened by a factor of ¼ at a maximum, and if the number of NAND memory chips is eight, it can be shortened by a factor of ⅛ at a maximum, so that the overall transfer performance can be improved. In other words, because multiple NAND memory chips can be efficiently accessed, in the memory system  100 , the number of times of read processing for 4 KB of data per given time can be greatly improved. 
     Further, in the first embodiment, if a command is queued into a priority command queue  14   e  during the execution of multiple subcommands (one read command) into which one request was divided and which have been queued in an ordinary command queue  14   d , the control circuit  14   c  in the NAND I/F  14  executes the command from the priority command queue  14   e  after finishing the execution of the read command. The control circuit  14   c  executes the command (subcommand) from the priority command queue  14   e  in priority over the command queued next in the ordinary command queues  14   d  after finishing the execution of the read command. Thus, a command (subcommand) subsequent but including access to a NAND memory chip being in the idle state can be executed in priority over others. 
     Yet further, in the first embodiment, if a command (subcommand) is queued into a priority command queue  14   e  during the execution of multiple subcommands (one read command) into which one request was divided and which have been queued in an ordinary command queue  14   d , after the execution of the read command finishes, the access control circuit  14   a  in the NAND I/F  14  switches from the first state to the second state to have the command from the priority command queue  14   e  executed. The first state is one where the access right is granted to a command from the ordinary command queue  14   d . The second state is one where the access right is granted to a command from the priority command queue  14   e . The access right is a right to access the NAND flash memory  20  via the access processing circuit  14   b . As such, command queues to be used can be switched by hardware control by the access control circuit  14   a , and hence command queues to be used can be switched at higher speed as compared with the case of switching by the firmware FW. 
     Although  FIGS. 4, 5  show as an example the case where four times of read request are received from the host  1 , the number of times of read request consecutively received from the host  1  may be three or less, or five or greater. 
     Second Embodiment 
     Next, a memory system  100   i  according to the second embodiment will be described. Description will be made below focusing on the differences from the first embodiment. 
     Although in the first embodiment a command from the priority command queue is executed after the execution of multiple subcommands into which one request was divided finishes, in the second embodiment a command from the priority command queue is executed by interrupting a command being executed. 
     Specifically, as shown in  FIG. 6 , in the memory system  100   i , a NAND I/F  14   i  has a control circuit  14   ci  instead of the control circuit  14   c  (see  FIG. 4 ).  FIG. 6  is a diagram showing the configuration of the NAND I/F  14   i . The control circuit  14   ci  has an access control circuit  14   ai  instead of the access control circuit  14   a  and further has a buffer circuit  14   f . The command being executed by the access processing circuit  14   b  is saved into the buffer circuit  14   f.    
     If a command is queued into a priority command queue  14   e  during the execution of multiple subcommands (one read command) into which one request was divided and which have been queued in an ordinary command queue  14   d , the control circuit  14   ci , during the execution of the read command, interrupts to execute the command from the priority command queue  14   e . That is, while executing a second or later one of multiple subcommands into which one request was divided, the control circuit  14   ci  interrupts to execute a subcommand from the priority command queue  14   e . After accessing a given NAND memory chip  21  according to the read setup command, the head, of the multiple subcommands, the control circuit  14   ci  suspends the execution of the second and later subcommands and executes a subcommand (read setup command) from the priority command queue  14   e  to access another NAND memory chip  21 . After accessing the other NAND memory chip  21  according to the subcommand (read setup command) from the priority command queue  14   e , the control circuit  14   ci  resumes the execution of the suspended subcommands unless another subcommand is queued in the priority command queue  14   e.    
     For example, if a command is queued into a priority command queue  14   e  during the execution of multiple subcommands into which one request was divided and which have been queued in an ordinary command queue  14   d , the access control circuit  14   ai  saves the subcommand being executed into the buffer circuit  14   f . At the same time, the access control circuit  14   ai  switches from the first state to the second state to have the subcommand from the priority command queue  14   e  executed. The first state is one where the access right is granted to a command (or subcommand) from the ordinary command queue  14   d . The second state is one where the access right is granted to a command (or subcommand) from the priority command queue  14   e . The access right is a right to access the NAND flash memory  20  via the access processing circuit  14   b.    
     After the execution of the subcommand from the priority command queue  14   e , if another subcommand is queued in the priority command queue  14   e , then the access control circuit  14   ai  executes that subcommand. After the execution of the subcommand from the priority command queue  14   e , if another subcommand is not queued in the priority command queue  14   e , then the access control circuit  14   ai  returns from the second state to the first state to have the subsequent command (subcommand) queued in the buffer circuit  14   f  executed. 
     For example, as shown in  FIG. 7 , the memory system  100   i  operates differently than in the first embodiment in the following points.  FIG. 7  is a timing chart showing the operation of the memory system  100   i.    
     The CPU  11  realizes that the access destination of the subcommands  209   a  to  209   c  is the NAND memory chip  21 - 1  to queue the read setup (CE 1 ReadSetUp) command  209   a , the head subcommand, into the priority command queue  14   e - 0  (see  FIG. 6 ). Accordingly, the control circuit  14   ci  saves the ready wait (CE 0 ReadyWait) command  203   b  being executed from the access processing circuit  14   b  into the buffer circuit  14   f . Then the control circuit  14   ci  grants the access right to a subcommand from the priority command queue  14   e  and dequeues the read setup (CE 1 ReadSetUp) command  209   a  from the priority command queue  14   e - 0  to execute. The control circuit  14   ci  selectively makes the chip enable signal CE 1  active and accesses the NAND memory chip  21 - 1  according to the read setup (CE 1 ReadSetUp) command  209   a . The control circuit  14   ci  transfers a read command (Cmd00h-Adr-Cmd30h) to the NAND memory chip  21 - 1  according to the read setup (CE 1 ReadSetUp) command  209   a . The read command (Cmd00h-Adr-Cmd30h) instructs the NAND memory chip  21  to perform read processing for, e.g., 4 KB of data. 
     When the execution of the read setup (CE 1 ReadSetUp) command  209   a  finishes, the control circuit  14   ci  returns the access right to commands from the ordinary command queue  14   d  and returns the ready wait (CE 0 ReadyWait) command  203   b  from the buffer circuit  14   f  to the access processing circuit  14   b . The control circuit  14   ci  resumes the execution of the ready wait (CE 0 ReadyWait) command  203   b . The control circuit  14   ci  waits for the Ry/By signal RBZ from the NAND memory chip  21 - 0  to switch from the busy state to the ready state according to the ready wait (CE 0 ReadyWait) command  203   b . When realizing that the Ry/By signal RBZ has switched from the busy state to the ready state, the control circuit  14   ci  finishes the ready wait (CE 0 ReadyWait) command  203   b  and dequeues the read data out (CE 0 ReadDataOut) command  203   c  from the ordinary command queue  14   d - 0  to execute. The control circuit  14   ci  reads data from the NAND memory chip  21 - 0  according to the read data out (CE 0 ReadDataOut) command  203   c  and transfers the read data to the read buffer in the buffer memory  13  via the CPU  11 . 
     While the control circuit  14   ci  is transferring data from the NAND memory chip  21 - 0  to the read buffer, the read setup (CE 2 ReadSetUp) command  212   a  is queued into the priority command queue  14   e - 1  (see  FIG. 6 ). Accordingly, the control circuit  14   ci  saves the read data out (CE 0 ReadDataOut) command  203   c  being executed from the access processing circuit  14   b  into the buffer circuit  14   f . For example, the control circuit  14   c  makes the chip enable signal CE 0  non-active, so that the NAND memory chip  21 - 0  can suspend data transfer to the NAND I/F  14 I. 
     Then the control circuit  14   ci  grants the access right to the command from the priority command queue  14   e  and dequeues the read setup (CE 2 ReadSetUp) command  212   a  from the priority command queue  14   e - 1  via the priority command queue  14   e - 0  to execute. The control circuit  14   ci  selectively makes the chip enable signal CE 2  active and accesses the NAND memory chip  21 - 2  according to the read setup (CE 2 ReadSetUp) command  212   a . The control circuit  14   ci  transfers a read command (Cmd00h-Adr-Cmd30h) to the NAND memory chip  21 - 2  according to the read setup (CE 2 ReadSetUp) command  212   a . The read command (Cmd00h-Adr-Cmd30h) instructs the NAND memory chip  21  to perform read processing for, e.g., 4 KB of data. 
     When the execution of the read setup (CE 2 ReadSetUp) command  212   a  finishes, the control circuit  14   ci  returns the access right to subcommands from the ordinary command queue  14   d  and returns the read data out (CE 0 ReadDataOut) command  203   c  from the buffer circuit  14   f  to the access processing circuit  14   b . The control circuit  14   ci  resumes the execution of the read data out (CE 0 ReadDataOut) command  203   c . For example, the control circuit  14   c  makes the chip enable signal CE 0  active, so that the NAND memory chip  21 - 0  can resume data transfer to the NAND I/F  14 I. The control circuit  14   ci  transfers the transferred data to the read buffer in the buffer memory  13  via the CPU  11  according to the read data out (CE 0 ReadDataOut) command  203   c.    
     As described above, in the second embodiment, in the NAND I/F  14   i , if a command (subcommand) is queued into a priority command queue  14   e  during the execution of multiple subcommands (one read command) from the ordinary command queue  14   d , the control circuit  14   ci , during the execution of the second or later subcommand of the multiple subcommands, interrupts to execute the subcommand from the priority command queue  14   e . That is, the control circuit  14   ci  suspends the execution of the second and later subcommands of multiple subcommands from the ordinary command queue  14   d  to execute a subcommand from the priority command queue  14   e  and, after executing the subcommand from the priority command queue  14   e , resumes the execution of the suspended subcommands. Thus, a command (subcommand) subsequent but including access to a NAND memory chip being in the idle state can be executed in priority over others at a further earlier timing than in the first embodiment. As a result, as compared with the processing time PT 1  in the case of processing the read commands  203 ,  206 ,  209 ,  212  in the order in which the corresponding read requests  201 ,  204 ,  207 ,  210  are received, the total processing time PT 2 ′ from when the controller  10  receives multiple requests until returning the respective responses to the requests to the host  1  can be further shortened by an amount ΔPT′ (&gt;ΔPT). 
     Third Embodiment 
     Next, a memory system  100   j  according to the third embodiment will be described. Description will be made below focusing on the differences from the second embodiment. 
     Although in the second embodiment ordinary command queues and priority command queues having higher priority over the ordinary command queues are provided in the NAND I/F  14   i , in the third embodiment, a dedicated command queue is provided for each NAND memory chip. 
     Specifically, as shown in  FIG. 8 , in the memory system  100   j , a NAND I/F  14   j  has a control circuit  14   cj  instead of the control circuit  14   ci  (see  FIG. 6 ) and multiple chip-oriented command queues  14   gi - 0  to  14   gi - 3  instead of the ordinary command queues  14   d - 0  to  14   d - 3  and the priority command queues  14   e - 0  to  14   e - 2  (see  FIG. 6 ).  FIG. 8  is a diagram showing the configuration of the NAND I/F  14   j . The control circuit  14   cj  has an access control circuit  14   aj  instead of the access control circuit  14   ai  and further has a NAND monitoring circuit  14   h.    
     The multiple chip-oriented command queues  14   gi - 0  to  14   gi - 3  correspond to the multiple NAND memory chips  21 - 0  to  21 - 3 . For example, the chip-oriented command queue  14   gi - 0  corresponds to the NAND memory chip  21 - 0 , and commands whose access destination is the NAND memory chip  21 - 0  are queued therein. 
     Each chip-oriented command queue  14   gi  queues commands supplied from the CPU  11  therein. Each command queue  14   d  is a queue buffer having a FIFO (First In First Out) structure, and the commands are dequeued in the order in which they were queued. Commands queued in the chip-oriented command queue  14   gi  move closer by one to the head each time the command at the head queue is dequeued. The multiple command queues  14   d - 0  to  14   d - 3  are each connected to the control circuit  14   cj , and each dequeued command is put into the control circuit  14   cj.    
     The differences from the second embodiment are that the NAND I/F  14   j  has a chip-oriented command queue  14   gi  for each NAND memory chip  21 . Thus, the CPU  11  can queue commands (subcommands) into the chip-oriented command queue  14   gi  for each NAND memory chip  21  that is the access destination of them without paying attention to order of priority when queuing commands. 
     The NAND monitoring circuit  14   h  in the control circuit  14   cj  monitors the respective states of the NAND memory chips  21 - 0  to  21 - 3  according to commands (subcommands) executed in the access processing circuit  14   b . For example, the NAND monitoring circuit  14   h  can monitor a NAND memory chip  21  for which a read setup command is not yet executed or a ready wait command has been executed as being in a ready state (idle state). The NAND monitoring circuit  14   h  can monitor a NAND memory chip  21  for which a read setup command has been executed and the execution of a ready wait command is not yet finished as being in the busy state. The access control circuit  14   aj  grants an access right to a selected command queue of the chip-oriented command queues  14   gi - 0  to  14   gi - 3  according to the monitoring result of the NAND monitoring circuit  14   h . The access right is a right to access the NAND flash memory  20  via the access processing circuit  14   b.    
     The access control circuit  14   aj  starts executing a command from a chip-oriented command queue  14   gi  into which a command was queued first from among the chip-oriented command queues  14   gi - 0  to  14   gi - 3 . The NAND monitoring circuit  14   h  monitors the state of each NAND memory chip  21  seeing the command (subcommand) executed for the NAND memory chip  21  to supply the monitoring results to the access control circuit  14   aj . The access control circuit  14   aj  switches chip-oriented command queues  14   gi  to be used based on the monitoring results of the NAND monitoring circuit  14   h . Thus, the multiple NAND memory chips  21 - 0  to  21 - 3  can be accessed efficiently. 
     For example, if a command (subcommand) is queued into another chip-oriented command queue  14   gi  during the execution of a command from a given chip-oriented command queues  14   gi , the access control circuit  14   aj  determines whether to be able to suspend the command being executed to access another NAND memory chip  21 . If it can access another NAND memory chip  21  during the execution of the command including access to a given NAND memory chip  21  (e.g., in the case where the subcommand being executed is a ready wait command or a read data out command), the access control circuit  14   aj  temporarily saves the command (subcommand) being executed from the access processing circuit  14   b  into the buffer circuit  14   f . The access control circuit  14   aj  preferentially grants an access right to the command (subcommand from the other chip-oriented command queue  14   gi ) including access to the other NAND memory chip to have the command executed. When the execution thereof finishes, the access control circuit  14   aj  returns the saved command (subcommand) from the buffer circuit  14   f  to the access processing circuit  14   b  and returns the access right to the command (subcommand) to have it resume being executed. 
     Note that if a command (subcommand) is queued into another chip-oriented command queue  14   gi  during the execution of a command from a given chip-oriented command queues  14   gi , the access control circuit  14   aj  may switch chip-oriented command queues  14   gi  to be used on a round robin basis. For example, if there is no order of priority about the access destinations in the NAND memory chips  21 - 0  to  21 - 3 , by switching chip-oriented command queues  14   gi  on a round robin basis, they can be made to operate such that the order in access is not biased. 
     For example, as shown in  FIG. 9 , the memory system  100   j  can operate differently than in the first embodiment in the following points. 
     The controller  10  waits until a read request comes in from the host  1  (while No at S 1 ) and, when a read request comes in from the host  1  (Yes at S 1 ), receives the read request by the host I/F  12  (S 2 ). The controller  10  performs preprocessing such as the logical-physical conversion according to the read request. At the same time, the controller  10  divides the read request to create multiple subcommands to identify the NAND memory chip  21  that is the access destination of the multiple subcommands (S 3 ). The controller  10  queues the multiple subcommands created at S 3  into the chip-oriented command queue  14   gi  corresponding to the NAND memory chip  21  that is the access destination from among the chip-oriented command queues  14   gi - 0  to  14   gi - 3  (S 4 ). 
     When commands are queued into one or more chip-oriented command queues  14   gi , if the subcommand at the head queue of a chip-oriented command queue  14   gi  is one including access to a NAND memory chip  21  (e.g., a read setup command), the controller  10  determines whether the NAND memory chip  21  that is the access destination is in the idle state (ready state) (S 5 ). If none of the NAND memory chips  21  that are the access destinations is in the idle state (No at S 5 ), the controller  10  waits. If the NAND memory chips  21  that are the access destinations of some subcommands are in the idle state (Yes at S 5 ), the controller  10  selects one of the NAND memory chips  21  that are the access destinations on a round robin basis (S 6 ). The controller  10  decides on a command to grant an access right to according to the selected NAND memory chip  21  that is the access destination. The controller  10  dequeues the command granted the access right from the chip-oriented command queue  14   gi  to execute (S 7 ). Thus, the NAND memory chip  21  that is the access destination goes into the busy state (S 8 ). Then the process returns to S 5 , and the process of S 5  to S 8  is performed also for the other commands. 
     As described above, in the third embodiment, a chip-oriented command queue  14   gi  is provided for each NAND memory chip  21  in the NAND I/F  14   j . If a command is queued into another chip-oriented command queue  14   gi  during the execution of multiple subcommands (one read command) into which one request was divided and which have been queued in a given chip-oriented command queue  14   gi , the control circuit  14   ci , during the execution of a second or later one of the multiple subcommands, interrupts to execute the subcommand from the other chip-oriented command queue  14   gi . Thus, a command (subcommand) subsequent but including access to a NAND memory chip being in the idle state can be executed in priority over others at a further earlier timing than in the first embodiment. As a result, as compared with the processing time PT 1  in the case of processing the read commands  203 ,  206 ,  209 ,  212  in the order in which the corresponding read requests  201 ,  204 ,  207 ,  210  are received, the total processing time PT 2 ′ from when the controller  10  receives multiple requests until returning the respective responses to the requests to the host  1  can be further shortened by an amount ΔPT′ (&gt;ΔPT) (see  FIG. 7 ). 
     Further, in the third embodiment, since the NAND I/F  14   j  has a chip-oriented command queue  14   gi  for each NAND memory chip  21 , the CPU  11  need not consider priority when queuing a command into a chip-oriented command queue  14   gi . The access control circuit  14   aj  switches chip-oriented command queues  14   gi  to be used based on the monitoring results of the NAND monitoring circuit  14   h . Thus, the multiple NAND memory chips  21 - 0  to  21 - 3  are accessed efficiently. That is, as compared with the case where the CPU  11  controls into which command queue a command (subcommand) is to be queued according to the firmware FW, access to the multiple NAND memory chips  21 - 0  to  21 - 3  can be efficiently controlled following the current state better, so that the improvement of the transfer performance can be effectively achieved. 
     While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions. 
     For example, although in the above embodiments the case where requests from the host  1  are read requests has been described, the present invention can be applied to requests other than read requests such as write requests or erase requests. Further, although in the above embodiments the case where accesses to multiple NAND memory chips are of the same type (a read request) has been described, the present invention can be applied to a combination of different types of accesses such as a combination of write requests and erase requests. For example, a write request is issued to one NAND memory chip, and while the NAND memory chip is operating internally according to the write request, by issuing an erase request to another NAND memory chip, the NAND memory chip can be made to start operating according to the erase request without waiting for the completion of the write request. That is, in dealing with multiple requests from the host  1  during a given time, the processing performance of the controller  10  can be greatly improved, and the processing performance for all commands from the host  1  can be improved. 
     Although in the above embodiments description has been made taking a NAND flash memory as an example of the nonvolatile semiconductor memory, the nonvolatile semiconductor memory is not limited to a NAND flash memory. Another nonvolatile semiconductor memory such as an MRAM (Magnetoresistive Random Access Memory) may be used.