Patent Publication Number: US-2022238681-A1

Title: Transistor Gates and Methods of Forming

Description:
PRIORITY CLAIM AND CROSS-REFERENCE 
     This application is a continuation of U.S. application Ser. No. 16/943,110, filed Jul. 30, 2020, which claims the benefit of U.S. Provisional Application No. 63/038,970, filed on Jun. 15, 2020, which application is hereby incorporated herein by reference. 
    
    
     BACKGROUND 
     Semiconductor devices are used in a variety of electronic applications, such as, for example, personal computers, cell phones, digital cameras, and other electronic equipment. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers of material over a semiconductor substrate, and patterning the various material layers using lithography to form circuit components and elements thereon. 
     The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continual reductions in minimum feature size, which allow more components to be integrated into a given area. However, as the minimum features sizes are reduced, additional problems arise that should be addressed. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. 
         FIG. 1  illustrates an example of a nanostructure field-effect transistor (nano-FET) in a three-dimensional view, in accordance with some embodiments. 
         FIGS. 2, 3, 4, 5, 6A, 6B, 7A, 7B   8 A,  8 B,  9 A,  9 B,  10 A,  10 B,  11 A,  11 B,  11 C,  12 A,  12 B,  12 C,  12 D,  13 A,  13 B,  13 C,  14 A,  14 B,  15 A,  15 B,  16 A,  16 B,  17 A,  17 B,  18 A,  18 B,  19 A,  19 B,  19 C,  19 D,  22 A,  22 B,  23 A,  23 B,  23 C,  24 A,  24 B,  24 C,  25 A,  25 B, and  25 C are cross-sectional and top down views of intermediate stages in the manufacturing of nano-FETs, in accordance with some embodiments. 
         FIG. 20  is a cross-sectional view of a nano-FET, in accordance with some embodiments. 
         FIG. 21  is a cross-sectional view of a nano-FET, in accordance with some embodiments. 
         FIGS. 26A, 26B, and 26C  are cross-sectional views of a nano-FET, in accordance with some embodiments. 
     
    
    
     DETAILED DESCRIPTION 
     The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. 
     Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature&#39;s relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated  90  degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. 
     In transistor gate stacks, the thickness of work function metal (WFM) layer(s) affects the threshold voltage (V TH ) of the transistor. However, it has been determined that thickness variations due to merged regions of the WFM layers (e.g., between nanowires of a nano-FETs) may not significantly affect the electrical characteristics of the transistor. Further, by not depositing a barrier layer around the WFM layer (e.g., to prevent portions of the WFM layer form merging), manufacturing ease can be improved. This is particularly true in advanced semiconductor nodes with small feature sizes as barrier layer materials (e.g., tantalum nitride, or the like) can be difficult to deposit in small spaces. Thus, by omitting such barrier layers in the gate stacks and allowing the WFM layers to merge in certain areas, manufacturing ease can be improved and manufacturing defects (e.g., resulting from poor barrier layer deposition) can be reduced without significantly impacting the electrical performance of the resulting transistor. 
       FIG. 1  illustrates an example of nano-FETs (e.g., nanowire FETs, nanosheet FETs, or the like) in a three-dimensional view, in accordance with some embodiments. The nano-FETs comprise nanostructures  55  (e.g., nanosheets, nanowire, or the like) over fins  66  on a substrate  50  (e.g., a semiconductor substrate), wherein the nanostructures  55  act as channel regions for the nano-FETs. The nanostructure  55  may include p-type nanostructures, n-type nanostructures, or a combination thereof. Isolation regions  68  are disposed between adjacent fins  66 , which may protrude above and from between neighboring isolation regions  68 . Although the isolation regions  68  are described/illustrated as being separate from the substrate  50 , as used herein, the term “substrate” may refer to the semiconductor substrate alone or a combination of the semiconductor substrate and the isolation regions. Additionally, although a bottom portion of the fins  66  are illustrated as being single, continuous materials with the substrate  50 , the bottom portion of the fins  66  and/or the substrate  50  may comprise a single material or a plurality of materials. In this context, the fins  66  refer to the portion extending between the neighboring isolation regions  68 . 
     Gate dielectrics  100  are over top surfaces of the fins  66  and along top surfaces, sidewalls, and bottom surfaces of the nanostructures  55 . Gate electrodes  102  are over the gate dielectrics  100 . Epitaxial source/drain regions  92  are disposed on the fins  66  on opposing sides of the gate dielectrics  100  and the gate electrodes  102 . 
       FIG. 1  further illustrates reference cross-sections that are used in later figures. Cross-section A-A′ is along a longitudinal axis of a gate electrode  102  and in a direction, for example, perpendicular to the direction of current flow between the epitaxial source/drain regions  92  of a nano-FET. Cross-section B-B′ is perpendicular to cross-section A-A′ and is parallel to a longitudinal axis of a fin  66  of the nano-FET and in a direction of, for example, a current flow between the epitaxial source/drain regions  92  of the nano-FET. Cross-section C-C′ is parallel to cross-section A-A′ and extends through epitaxial source/drain regions of the nano-FETs. Subsequent figures refer to these reference cross-sections for clarity. 
     Some embodiments discussed herein are discussed in the context of nano-FETs formed using a gate-last process. In other embodiments, a gate-first process may be used. Also, some embodiments contemplate aspects used in planar devices, such as planar FETs or in fin field-effect transistors (FinFETs). 
       FIGS. 2 through 24C  are cross-sectional views of intermediate stages in the manufacturing of nano-FETs, in accordance with some embodiments.  FIGS. 2 through 5, 6A, 13A, 14A, 15A, 16A, 17A, 18A, 19A, 20, 21, 22A, 23A, 24A, 25A, and 26A  illustrate reference cross-section A-A′ illustrated in  FIG. 1 .  FIGS. 6B, 7B, 8B, 9B, 10B, 11B, 11C, 12B, 12D, 13B, 14B, 15B, 16B, 17B, 18B, 19B, 22B, 23B, 24B, 25B , and  26 B illustrate reference cross-section B-B′ illustrated in  FIG. 1 .  FIGS. 7A, 8A, 9A, 10A, 11A, 12A, 12C, 13C, 22C, 23C, 24C, 25C, and 26C  illustrate reference cross-section C-C′ illustrated in  FIG. 1 . 
     In  FIG. 2 , a substrate  50  is provided. The substrate  50  may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p-type or an n-type dopant) or undoped. The substrate  50  may be a wafer, such as a silicon wafer. Generally, an SOI substrate is a layer of a semiconductor material formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is provided on a substrate, typically a silicon or glass substrate. Other substrates, such as a multi-layered or gradient substrate may also be used. In some embodiments, the semiconductor material of the substrate  50  may include silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including silicon-germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and/or gallium indium arsenide phosphide; or combinations thereof. 
     The substrate  50  has an n-type region  50 N and a p-type region  50 P. The n-type region  50 N can be for forming n-type devices, such as NMOS transistors, e.g., n-type nano-FETs, and the p-type region  50 P can be for forming p-type devices, such as PMOS transistors, e.g., p-type nano-FETs. The n-type region  50 N may be physically separated from the p-type region  50 P (as illustrated by divider  20 ), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) may be disposed between the n-type region  50 N and the p-type region  50 P. Although one n-type region  50 N and one p-type region  50 P are illustrated, any number of n-type regions  50 N and p-type regions  50 P may be provided. 
     Further in  FIG. 2 , a multi-layer stack  64  is formed over the substrate  50 . The multi-layer stack  64  includes alternating layers of first semiconductor layers  51 A-C (collectively referred to as first semiconductor layers  51 ) and second semiconductor layers  53 A-C (collectively referred to as second semiconductor layers  53 ). For purposes of illustration and as discussed in greater detail below, the second semiconductor layers  53  will be removed and the first semiconductor layers  51  will be patterned to form channel regions of nano-FETs in the p-type region  50 P. Also, the first semiconductor layers  51  will be removed and the second semiconductor layers  53  will be patterned to form channel regions of nano-FETs in the n-type regions  50 N. Nevertheless, in some embodiments the first semiconductor layers  51  may be removed and the second semiconductor layers  53  may be patterned to form channel regions of nano-FETs in the n-type region  50 N, and the second semiconductor layers  53  may be removed and the first semiconductor layers  51  may be patterned to form channel regions of nano-FETs in the p-type regions  50 P. 
     In still other embodiments, the first semiconductor layers  51  may be removed and the second semiconductor layers  53  may be patterned to form channel regions of nano-FETS in both the n-type region  50 N and the p-type region  50 P. In other embodiments, the second semiconductor layers  53  may be removed and the first semiconductor layers  51  may be patterned to form channel regions of non-FETs in both the n-type region  50 N and the p-type region  50 P. In such embodiments, the channel regions in both the n-type region  50 N and the p-type region  50 P may have a same material composition (e.g., silicon, or the like) and be formed simultaneously.  FIGS. 26A, 26B, and 27C  illustrate a structure resulting from such embodiments where the channel regions in both the p-type region  50 P and the n-type region  50 N comprise silicon, for example. 
     The multi-layer stack  64  is illustrated as including three layers of each of the first semiconductor layers  51  and the second semiconductor layers  53  for illustrative purposes. In some embodiments, the multi-layer stack  64  may include any number of the first semiconductor layers  51  and the second semiconductor layers  53 . Each of the layers of the multi-layer stack  64  may be epitaxially grown using a process such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), or the like. In various embodiments, the first semiconductor layers  51  may be formed of a first semiconductor material suitable for p-type nano-FETs, such as silicon germanium, or the like, and the second semiconductor layers  53  may be formed of a second semiconductor material suitable for n-type nano-FETs, such as silicon, silicon carbon, or the like. The multi-layer stack  64  is illustrated as having a bottommost semiconductor layer suitable for p-type nano-FETs for illustrative purposes. In some embodiments, the multi-layer stack  64  may be formed such that the bottommost layer is a semiconductor layer suitable for n-type nano-FETs. 
     The first semiconductor materials and the second semiconductor materials may be materials having a high-etch selectivity to one another. As such, the first semiconductor layers  51  of the first semiconductor material may be removed without significantly removing the second semiconductor layers  53  of the second semiconductor material in the n-type region  50 N, thereby allowing the second semiconductor layers  53  to be patterned to form channel regions of n-type NSFETS. Similarly, the second semiconductor layers  53  of the second semiconductor material may be removed without significantly removing the first semiconductor layers  51  of the first semiconductor material in the p-type region  50 P, thereby allowing the first semiconductor layers  51  to be patterned to form channel regions of p-type NSFETS. In other embodiments, the channel regions in the n-type region  50 N and the p-type region  50 P may be formed simultaneously and have a same material composition, such as silicon, silicon germanium, or the like.  FIGS. 26A, 26B, and 27C  illustrate a structure resulting from such embodiments where the channel regions in both the p-type region  50 P and the n-type region  50 N comprise silicon, for example. 
     Referring now to  FIG. 3 , fins  66  are formed in the substrate  50  and nanostructures  55  are formed in the multi-layer stack  64 , in accordance with some embodiments. In some embodiments, the nanostructures  55  and the fins  66  may be formed in the multi-layer stack  64  and the substrate  50 , respectively, by etching trenches in the multi-layer stack  64  and the substrate  50 . The etching may be any acceptable etch process, such as a reactive ion etch (RIE), neutral beam etch (NBE), the like, or a combination thereof. The etching may be anisotropic. Forming the nanostructures  55  by etching the multi-layer stack  64  may further define first nanostructures  52 A-C (collectively referred to as the first nanostructures  52 ) from the first semiconductor layers  51  and define second nanostructures  54 A-C (collectively referred to as the second nanostructures  54 ) from the second semiconductor layers  53 . The first nanostructures  52  and the second nanostructures  54  may further be collectively referred to as the nanostructures  55 . 
     The fins  66  and the nanostructures  55  may be patterned by any suitable method. For example, the fins  66  and the nanostructures  55  may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fins  66 . 
       FIG. 3  illustrates the fins  66  in the n-type region  50 N and the p-type region  50 P as having substantially equal widths for illustrative purposes. In some embodiments, widths of the fins  66  in the n-type region  50 N may be greater or thinner than the fins  66  in the p-type region  50 P. Further, while each of the fins  66  and the nanostructures  55  are illustrated as having a consistent width throughout, in other embodiments, the fins  66  and/or the nanostructures  55  may have tapered sidewalls such that a width of each of the fins  66  and/or the nanostructures  55  continuously increases in a direction towards the substrate  50 . In such embodiments, each of the nanostructures  55  may have a different width and be trapezoidal in shape. 
     In  FIG. 4 , shallow trench isolation (STI) regions  68  are formed adjacent the fins  66 . The STI regions  68  may be formed by depositing an insulation material over the substrate  50 , the fins  66 , and the nanostructures  55 , and between adjacent fins  66 . The insulation material may be an oxide, such as silicon oxide, a nitride, the like, or a combination thereof, and may be formed by high-density plasma CVD (HDP-CVD), flowable CVD (FCVD), the like, or a combination thereof. Other insulation materials formed by any acceptable process may be used. In the illustrated embodiment, the insulation material is silicon oxide formed by an FCVD process. An anneal process may be performed once the insulation material is formed. In an embodiment, the insulation material is formed such that excess insulation material covers the nanostructures  55 . Although the insulation material is illustrated as a single layer, some embodiments may utilize multiple layers. For example, in some embodiments a liner (not separately illustrated) may first be formed along a surface of the substrate  50 , the fins  66 , and the nanostructures  55 . Thereafter, a fill material, such as those discussed above, may be formed over the liner. 
     A removal process is then applied to the insulation material to remove excess insulation material over the nanostructures  55 . In some embodiments, a planarization process such as a chemical mechanical polish (CMP), an etch-back process, combinations thereof, or the like may be utilized. The planarization process exposes the nanostructures  55  such that top surfaces of the nanostructures  55  and the insulation material are level after the planarization process is complete. 
     The insulation material is then recessed to form the STI regions  68 . The insulation material is recessed such that upper portions of the fins  66  in the regions  50 N and  50 P protrude from between neighboring STI regions  68 . Further, the top surfaces of the STI regions  68  may have a flat surface as illustrated, a convex surface, a concave surface (such as dishing), or a combination thereof. The top surfaces of the STI regions  68  may be formed flat, convex, and/or concave by an appropriate etch. The STI regions  68  may be recessed using an acceptable etching process, such as one that is selective to the material of the insulation material (e.g., etches the material of the insulation material at a faster rate than the material of the fins  66  and the nanostructures  55 ). For example, an oxide removal using, for example, dilute hydrofluoric (dHF) acid may be used. 
     The process described above with respect to  FIGS. 2 through 4  is just one example of how the fins  66  and the nanostructures  55  may be formed. In some embodiments, the fins  66  and/or the nanostructures  55  may be formed using a mask and an epitaxial growth process. For example, a dielectric layer can be formed over a top surface of the substrate  50 , and trenches can be etched through the dielectric layer to expose the underlying substrate  50 . Epitaxial structures can be epitaxially grown in the trenches, and the dielectric layer can be recessed such that the epitaxial structures protrude from the dielectric layer to form the fins  66  and/or the nanostructures  55 . The epitaxial structures may comprise the alternating semiconductor materials discussed above, such as the first semiconductor materials and the second semiconductor materials. In some embodiments where epitaxial structures are epitaxially grown, the epitaxially grown materials may be in situ doped during growth, which may obviate prior and/or subsequent implantations, although in situ and implantation doping may be used together. 
     Additionally, the first semiconductor layers  51  (and resulting first nanostructures  52 ) and the second semiconductor layers  53  (and resulting second nanostructures  54 ) are illustrated and discussed herein as comprising the same materials in the p-type region  50 P and the n-type region  50 N for illustrative purposes only. As such, in some embodiments one or both of the first semiconductor layers  51  and the second semiconductor layers  53  may be different materials or formed in a different order in the p-type region  50 P and the n-type region  50 N. 
     Further in  FIG. 4 , appropriate wells (not separately illustrated) may be formed in the fins  66 , the nanostructures  55 , and/or the STI regions  68 . In embodiments with different well types, different implant steps for the n-type region  50 N and the p-type region  50 P may be achieved using a photoresist or other masks (not separately illustrated). For example, a photoresist may be formed over the fins  66  and the STI regions  68  in the n-type region  50 N and the p-type region  50 P. The photoresist is patterned to expose the p-type region  50 P. The photoresist can be formed by using a spin-on technique and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, an n-type impurity implant is performed in the p-type region  50 P, and the photoresist may act as a mask to substantially prevent n-type impurities from being implanted into the n-type region  50 N. The n-type impurities may be phosphorus, arsenic, antimony, or the like implanted in the region to a concentration in a range from about 10 13  atoms/cm 3  to about 10 14  atoms/cm 3 . After the implant, the photoresist is removed, such as by an acceptable ashing process. 
     Following or prior to the implanting of the p-type region  50 P, a photoresist or other masks (not separately illustrated) is formed over the fins  66 , the nanostructures  55 , and the STI regions  68  in the p-type region  50 P and the n-type region  50 N. The photoresist is patterned to expose the n-type region  50 N. The photoresist can be formed by using a spin-on technique and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, a p-type impurity implant may be performed in the n-type region  50 N, and the photoresist may act as a mask to substantially prevent p-type impurities from being implanted into the p-type region  50 P. The p-type impurities may be boron, boron fluoride, indium, or the like implanted in the region to a concentration in a range from about 10 13  atoms/cm 3  to about 10 14  atoms/cm 3 . After the implant, the photoresist may be removed, such as by an acceptable ashing process. 
     After the implants of the n-type region  50 N and the p-type region  50 P, an anneal may be performed to repair implant damage and to activate the p-type and/or n-type impurities that were implanted. In some embodiments, the grown materials of epitaxial fins may be in situ doped during growth, which may obviate the implantations, although in situ and implantation doping may be used together. 
     In  FIG. 5 , a dummy dielectric layer  70  is formed on the fins  66  and/or the nanostructures  55 . The dummy dielectric layer  70  may be, for example, silicon oxide, silicon nitride, a combination thereof, or the like, and may be deposited or thermally grown according to acceptable techniques. A dummy gate layer  72  is formed over the dummy dielectric layer  70 , and a mask layer  74  is formed over the dummy gate layer  72 . The dummy gate layer  72  may be deposited over the dummy dielectric layer  70  and then planarized, such as by a CMP. The mask layer  74  may be deposited over the dummy gate layer  72 . The dummy gate layer  72  may be a conductive or non-conductive material and may be selected from a group including amorphous silicon, polycrystalline-silicon (polysilicon), poly-crystalline silicon-germanium (poly-SiGe), metallic nitrides, metallic silicides, metallic oxides, and metals. The dummy gate layer  72  may be deposited by physical vapor deposition (PVD), CVD, sputter deposition, or other techniques for depositing the selected material. The dummy gate layer  72  may be made of other materials that have a high etching selectivity from the etching of isolation regions. The mask layer  74  may include, for example, silicon nitride, silicon oxynitride, or the like. In this example, a single dummy gate layer  72  and a single mask layer  74  are formed across the n-type region  50 N and the p-type region  50 P. It is noted that the dummy dielectric layer  70  is shown covering only the fins  66  and the nanostructures  55  for illustrative purposes only. In some embodiments, the dummy dielectric layer  70  may be deposited such that the dummy dielectric layer  70  covers the STI regions  68 , such that the dummy dielectric layer  70  extends between the dummy gate layer  72  and the STI regions  68 . 
       FIGS. 6A through 18C  illustrate various additional steps in the manufacturing of embodiment devices.  FIGS. 6A, 7A, 8A, 9A, 10A, 11A, 12A, 12C, 13A, 13C, 14A, 15A, and 18C  illustrate features in either the regions  50 N or the regions  50 P. In  FIGS. 6A and 6B , the mask layer  74  (see  FIG. 5 ) may be patterned using acceptable photolithography and etching techniques to form masks  78 . The pattern of the masks  78  then may be transferred to the dummy gate layer  72  and to the dummy dielectric layer  70  to form dummy gates  76  and dummy gate dielectrics  71 , respectively. The dummy gates  76  cover respective channel regions of the fins  66 . The pattern of the masks  78  may be used to physically separate each of the dummy gates  76  from adjacent dummy gates  76 . The dummy gates  76  may also have a lengthwise direction substantially perpendicular to the lengthwise direction of respective fins  66 . 
     In  FIGS. 7A and 7B , a first spacer layer  80  and a second spacer layer  82  are formed over the structures illustrated in  FIGS. 6A and 6B , respectively. The first spacer layer  80  and the second spacer layer  82  will be subsequently patterned to act as spacers for forming self-aligned source/drain regions. In  FIGS. 7A and 7B , the first spacer layer  80  is formed on top surfaces of the STI regions  68 ; top surfaces and sidewalls of the fins  66 , the nanostructures  55 , and the masks  78 ; and sidewalls of the dummy gates  76  and the dummy gate dielectrics  71 . The second spacer layer  82  is deposited over the first spacer layer  80 . The first spacer layer  80  may be formed of silicon oxide, silicon nitride, silicon oxynitride, or the like, using techniques such as thermal oxidation or deposited by CVD, ALD, or the like. The second spacer layer  82  may be formed of a material having a different etch rate than the material of the first spacer layer  80 , such as silicon oxide, silicon nitride, silicon oxynitride, or the like, and may be deposited by CVD, ALD, or the like. 
     After the first spacer layer  80  is formed and prior to forming the second spacer layer  82 , implants for lightly doped source/drain (LDD) regions (not separately illustrated) may be performed. In embodiments with different device types, similar to the implants discussed above in  FIG. 4 , a mask, such as a photoresist, may be formed over the n-type region  50 N, while exposing the p-type region  50 P, and appropriate type (e.g., p-type) impurities may be implanted into the exposed fins  66  and nanostructures  55  in the p-type region  50 P. The mask may then be removed. Subsequently, a mask, such as a photoresist, may be formed over the p-type region  50 P while exposing the n-type region  50 N, and appropriate type impurities (e.g., n-type) may be implanted into the exposed fins  66  and nanostructures  55  in the n-type region  50 N. The mask may then be removed. The n-type impurities may be any of the n-type impurities previously discussed, and the p-type impurities may be any of the p-type impurities previously discussed. The lightly doped source/drain regions may have a concentration of impurities in a range from about 1×10 15  atoms/cm 3  to about 1×10 19  atoms/cm 3 . An anneal may be used to repair implant damage and to activate the implanted impurities. 
     In  FIGS. 8A and 8B , the first spacer layer  80  and the second spacer layer  82  are etched to form first spacers  81  and second spacers  83 . As will be discussed in greater detail below, the first spacers  81  and the second spacers  83  act to self-align subsequently formed source/drain regions, as well as to protect sidewalls of the fins  66  and/or nanostructure  55  during subsequent processing. The first spacer layer  80  and the second spacer layer  82  may be etched using a suitable etching process, such as an isotropic etching process (e.g., a wet etching process), an anisotropic etching process (e.g., a dry etching process), or the like. In some embodiments, the material of the second spacer layer  82  has a different etch rate than the material of the first spacer layer  80 , such that the first spacer layer  80  may act as an etch stop layer when patterning the second spacer layer  82  and such that the second spacer layer  82  may act as a mask when patterning the first spacer layer  80 . For example, the second spacer layer  82  may be etched using an anisotropic etch process wherein the first spacer layer  80  acts as an etch stop layer, wherein remaining portions of the second spacer layer  82  form second spacers  83  as illustrated in  FIG. 8A . Thereafter, the second spacers  83  act as a mask while etching exposed portions of the first spacer layer  80 , thereby forming first spacers  81  as illustrated in  FIG. 8A . 
     As illustrated in  FIG. 8A , the first spacers  81  and the second spacers  83  are disposed on sidewalls of the fins  66  and/or the nanostructures  55 . As illustrated in  FIG. 8B , in some embodiments, the second spacer layer  82  may be removed from over the first spacer layer  80  adjacent the masks  78 , the dummy gates  76 , and the dummy gate dielectrics  71 , and the first spacers  81  are disposed on sidewalls of the masks  78 , the dummy gates  76 , and the dummy gate dielectrics  71 . In other embodiments, a portion of the second spacer layer  82  may remain over the first spacer layer  80  adjacent the masks  78 , the dummy gates  76 , and the dummy gate dielectrics  71 . 
     It is noted that the above disclosure generally describes a process of forming spacers and LDD regions. Other processes and sequences may be used. For example, fewer or additional spacers may be utilized, different sequence of steps may be utilized (e.g., the first spacers  81  may be patterned prior to depositing the second spacer layer  82 ), additional spacers may be formed and removed, and/or the like. Furthermore, the n-type and p-type devices may be formed using different structures and steps. 
     In  FIGS. 9A and 9B , first recesses  86  are formed in the fins  66 , the nanostructures  55 , and the substrate  50 , in accordance with some embodiments. Epitaxial source/drain regions will be subsequently formed in the first recesses  86 . The first recesses  86  may extend through the first nanostructures  52  and the second nanostructures  54 , and into the substrate  50 . As illustrated in  FIG. 9A , top surfaces of the STI regions  68  may be level with bottom surfaces of the first recesses  86 . In various embodiments, the fins  66  may be etched such that bottom surfaces of the first recesses  86  are disposed below the top surfaces of the STI regions  68 ; or the like. The first recesses  86  may be formed by etching the fins  66 , the nanostructures  55 , and the substrate  50  using anisotropic etching processes, such as RIE, NBE, or the like. The first spacers  81 , the second spacers  83 , and the masks  78  mask portions of the fins  66 , the nanostructures  55 , and the substrate  50  during the etching processes used to form the first recesses  86 . A single etch process or multiple etch processes may be used to etch each layer of the nanostructures  55  and/or the fins  66 . Timed etch processes may be used to stop the etching of the first recesses  86  after the first recesses  86  reach a desired depth. 
     In  FIGS. 10A and 10B , portions of sidewalls of the layers of the multi-layer stack  64  formed of the first semiconductor materials (e.g., the first nanostructures  52 ) exposed by the first recesses  86  are etched to form sidewall recesses  88  in the n-type region  50 N, and portions of sidewalls of the layers of the multi-layer stack  64  formed of the second semiconductor materials (e.g., the second nanostructures  54 ) exposed by the first recesses  86  are etched to form sidewall recesses  88  in the p-type region  50 P. Although sidewalls of the first nanostructures  52  and the second nanostructures  54  in the recesses  88  are illustrated as being straight in  FIG. 10B , the sidewalls may be concave or convex. The sidewalls may be etched using isotropic etching processes, such as wet etching or the like. The p-type region  50 P may be protected using a mask (not shown) while etchants selective to the first semiconductor materials are used to etch the first nanostructures  52  such that the second nanostructures  54  and the substrate  50  remain relatively unetched as compared to the first nanostructures  52  in the n-type region  50 N. Similarly, the n-type region  50 N may be protected using a mask (not shown) while etchants selective to the second semiconductor materials are used to etch the second nanostructures  54  such that the first nanostructures  52  and the substrate  50  remain relatively unetched as compared to the second nanostructures  54  in the p-type region  50 P. In an embodiment in which the first nanostructures  52  include, e.g., SiGe, and the second nanostructures  54  include, e.g., Si or SiC, a dry etch process with tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH 4 OH), or the like may be used to etch sidewalls of the first nanostructures  52  in the n-type region  50 N, and a dry etch process with hydrogen fluoride, another fluorine-based gas, or the like may be used to etch sidewalls of the second nanostructures  54  in the p-type region  50 P. 
     In  FIGS. 11A-11C , first inner spacers  90  are formed in the sidewall recesses  88 . The first inner spacers  90  may be formed by depositing an inner spacer layer (not separately illustrated) over the structures illustrated in  FIGS. 10A and 10B . The first inner spacers  90  act as isolation features between subsequently formed source/drain regions and a gate structure. As will be discussed in greater detail below, source/drain regions will be formed in the recesses  86 , while the first nanostructures  52  in the n-type region  50 N and the second nanostructures  54  in the p-type region  50 P will be replaced with corresponding gate structures. 
     The inner spacer layer may be deposited by a conformal deposition process, such as CVD, ALD, or the like. The inner spacer layer may comprise a material such as silicon nitride or silicon oxynitride, although any suitable material, such as low-dielectric constant (low-k) materials having a k-value less than about 3.5, may be utilized. The inner spacer layer may then be anisotropically etched to form the first inner spacers  90 . Although outer sidewalls of the first inner spacers  90  are illustrated as being flush with sidewalls of the second nanostructures  54  in the n-type region  50 N and flush with the sidewalls of the first nanostructures  52  in the p-type region  50 P, the outer sidewalls of the first inner spacers  90  may extend beyond or be recessed from sidewalls of the second nanostructures  54  and/or the first nanostructures  52 , respectively. 
     Moreover, although the outer sidewalls of the first inner spacers  90  are illustrated as being straight in  FIG. 11B , the outer sidewalls of the first inner spacers  90  may be concave or convex. As an example,  FIG. 11C  illustrates an embodiment in which sidewalls of the first nanostructures  52  are concave, outer sidewalls of the first inner spacers  90  are concave, and the first inner spacers  90  are recessed from sidewalls of the second nanostructures  54  in the n-type region  50 N. Also illustrated are embodiments in which sidewalls of the second nanostructures  54  are concave, outer sidewalls of the first inner spacers  90  are concave, and the first inner spacers  90  are recessed from sidewalls of the first nanostructures  52  in the p-type region  50 P. The inner spacer layer may be etched by an anisotropic etching process, such as RIE, NBE, or the like. The first inner spacers  90  may be used to prevent damage to subsequently formed source/drain regions (such as the epitaxial source/drain regions  92 , discussed below with respect to  FIGS. 12A-12C ) by subsequent etching processes, such as etching processes used to form gate structures. 
     In  FIGS. 12A-12C , epitaxial source/drain regions  92  are formed in the first recesses  86 . In some embodiments, the source/drain regions  92  may exert stress on the second nanostructures  54  in the n-type region  50 N and on the first nanostructures  52  in the p-type region  50 P, thereby improving performance. As illustrated in  FIG. 12B , the epitaxial source/drain regions  92  are formed in the first recesses  86  such that each dummy gate  76  is disposed between respective neighboring pairs of the epitaxial source/drain regions  92 . In some embodiments, the first spacers  81  are used to separate the epitaxial source/drain regions  92  from the dummy gates  76  and the first inner spacers  90  are used to separate the epitaxial source/drain regions  92  from the nanostructures  55  by an appropriate lateral distance so that the epitaxial source/drain regions  92  do not short out with subsequently formed gates of the resulting nano-FETs. 
     The epitaxial source/drain regions  92  in the n-type region  50 N, e.g., the NMOS region, may be formed by masking the p-type region  50 P, e.g., the PMOS region. Then, the epitaxial source/drain regions  92  are epitaxially grown in the first recesses  86  in the n-type region  50 N. The epitaxial source/drain regions  92  may include any acceptable material appropriate for n-type nano-FETs. For example, if the second nanostructures  54  are silicon, the epitaxial source/drain regions  92  may include materials exerting a tensile strain on the second nanostructures  54 , such as silicon, silicon carbide, phosphorous doped silicon carbide, silicon phosphide, or the like. The epitaxial source/drain regions  92  may have surfaces raised from respective upper surfaces of the nanostructures  55  and may have facets. 
     The epitaxial source/drain regions  92  in the p-type region  50 P, e.g., the PMOS region, may be formed by masking the n-type region  50 N, e.g., the NMOS region. Then, the epitaxial source/drain regions  92  are epitaxially grown in the first recesses  86  in the p-type region  50 P. The epitaxial source/drain regions  92  may include any acceptable material appropriate for p-type nano-FETs. For example, if the first nanostructures  52  are silicon germanium, the epitaxial source/drain regions  92  may comprise materials exerting a compressive strain on the first nanostructures  52 , such as silicon-germanium, boron doped silicon-germanium, germanium, germanium tin, or the like. The epitaxial source/drain regions  92  may also have surfaces raised from respective surfaces of the multi-layer stack  64  and may have facets. 
     The epitaxial source/drain regions  92 , the first nanostructures  52 , the second nanostructures  54 , and/or the substrate  50  may be implanted with dopants to form source/drain regions, similar to the process previously discussed for forming lightly-doped source/drain regions, followed by an anneal. The source/drain regions may have an impurity concentration of between about 1×10 19  atoms/cm 3  and about 1×10 21  atoms/cm 3 . The n-type and/or p-type impurities for source/drain regions may be any of the impurities previously discussed. In some embodiments, the epitaxial source/drain regions  92  may be in situ doped during growth. 
     As a result of the epitaxy processes used to form the epitaxial source/drain regions  92  in the n-type region  50 N and the p-type region  50 P, upper surfaces of the epitaxial source/drain regions  92  have facets which expand laterally outward beyond sidewalls of the nanostructures  55 . In some embodiments, these facets cause adjacent epitaxial source/drain regions  92  of a same NSFET to merge as illustrated by  FIG. 12A . In other embodiments, adjacent epitaxial source/drain regions  92  remain separated after the epitaxy process is completed as illustrated by  FIG. 12C . In the embodiments illustrated in  FIGS. 12A and 12C , the first spacers  81  may be formed to a top surface of the STI regions  68  thereby blocking the epitaxial growth. In some other embodiments, the first spacers  81  may cover portions of the sidewalls of the nanostructures  55  further blocking the epitaxial growth. In some other embodiments, the spacer etch used to form the first spacers  81  may be adjusted to remove the spacer material to allow the epitaxially grown region to extend to the surface of the STI region  68 . 
     The epitaxial source/drain regions  92  may comprise one or more semiconductor material layers. For example, the epitaxial source/drain regions  92  may comprise a first semiconductor material layer  92 A, a second semiconductor material layer  92 B, and a third semiconductor material layer  92 C. Any number of semiconductor material layers may be used for the epitaxial source/drain regions  92 . Each of the first semiconductor material layer  92 A, the second semiconductor material layer  92 B, and the third semiconductor material layer  92 C may be formed of different semiconductor materials and may be doped to different dopant concentrations. In some embodiments, the first semiconductor material layer  92 A may have a dopant concentration less than the second semiconductor material layer  92 B and greater than the third semiconductor material layer  92 C. In embodiments in which the epitaxial source/drain regions  92  comprise three semiconductor material layers, the first semiconductor material layer  92 A may be deposited, the second semiconductor material layer  92 B may be deposited over the first semiconductor material layer  92 A, and the third semiconductor material layer  92 C may be deposited over the second semiconductor material layer  92 B. 
       FIG. 12D  illustrates an embodiment in which sidewalls of the first nanostructures  52  in the n-type region  50 N and sidewalls of the second nanostructures  54  in the p-type region  50 P are concave, outer sidewalls of the first inner spacers  90  are concave, and the first inner spacers  90  are recessed from sidewalls of the second nanostructures  54  and the first nanostructures  52 , respectively. As illustrated in  FIG. 12D , the epitaxial source/drain regions  92  may be formed in contact with the first inner spacers  90  and may extend past sidewalls of the second nanostructures  54  in the n-type region  50 N and past sidewalls of the first nanostructures  52  in the p-type region  50 P. 
     In  FIGS. 13A-13C , a first interlayer dielectric (ILD)  96  is deposited over the structure illustrated in  FIGS. 6A, 12B, and 12A  (the processes of  FIGS. 7A-12D  do not alter the cross-section illustrated in  FIGS. 6A ), respectively. The first ILD  96  may be formed of a dielectric material, and may be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. Dielectric materials may include phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped silicate glass (USG), or the like. Other insulation materials formed by any acceptable process may be used. In some embodiments, a contact etch stop layer (CESL)  94  is disposed between the first ILD  96  and the epitaxial source/drain regions  92 , the masks  78 , and the first spacers  81 . The CESL  94  may comprise a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, or the like, having a different etch rate than the material of the overlying first ILD  96 . 
     In  FIGS. 14A-14C , a planarization process, such as a CMP, may be performed to level the top surface of the first ILD  96  with the top surfaces of the dummy gates  76  or the masks  78 . The planarization process may also remove the masks  78  on the dummy gates  76 , and portions of the first spacers  81  along sidewalls of the masks  78 . After the planarization process, top surfaces of the dummy gates  76 , the first spacers  81 , and the first ILD  96  are level within process variations. Accordingly, the top surfaces of the dummy gates  76  are exposed through the first ILD  96 . In some embodiments, the masks  78  may remain, in which case the planarization process levels the top surface of the first ILD  96  with the top surface of the masks  78  and the first spacers  81 . 
     In  FIGS. 15A and 15B , the dummy gates  76 , and the masks  78  if present, are removed in one or more etching steps, so that second recesses  98  are formed. Portions of the dummy gate dielectrics  71  in the second recesses  98  are also removed. In some embodiments, the dummy gates  76  and the dummy gate dielectrics  71  are removed by an anisotropic dry etch process. For example, the etching process may include a dry etch process using reaction gas(es) that selectively etch the dummy gates  76  at a faster rate than the first ILD  96  or the first spacers  81 . Each second recess  98  exposes and/or overlies portions of the nanostructures  55 , which act as channel regions in subsequently completed nano-FETs. Portions of the nanostructures  55  which act as the channel regions are disposed between neighboring pairs of the epitaxial source/drain regions  92 . During the removal, the dummy gate dielectrics  71  may be used as etch stop layers when the dummy gates  76  are etched. The dummy gate dielectrics  71  may then be removed after the removal of the dummy gates  76 . 
     In  FIGS. 16A through 21B , nanostructures are defined in the p-type region  50 P and the n-type region  50 N, and gate dielectric layers and gate electrodes are formed for replacement gates according to some embodiments. The formation of the gate dielectric layers in the n-type region  50 N and the p-type region  50 P may occur simultaneously such that the gate dielectric layers in each region are formed from the same materials, and the formation of the gate electrodes may occur simultaneously such that the gate electrodes in each region are formed from the same materials. In some embodiments, the gate dielectric layers in each region may be formed by distinct processes, such that the gate dielectric layers may be different materials and/or have a different number of layers, and/or the gate electrodes in each region may be formed by distinct processes, such that the gate electrodes may be different materials and/or have a different number of layers. Various masking steps may be used to mask and expose appropriate regions when using distinct processes. In the following description, the gate electrodes of the n-type region  50 N and the gate electrodes of the p-type region  50 P are formed separately. 
     In  FIGS. 16A and 16B , the second nanostructures  54  in the p-type region  50 P may be removed by forming a mask (not shown) over the n-type region  50 N and performing an isotropic etching process such as wet etching or the like using etchants which are selective to the materials of the second nanostructures  54 , while the first nanostructures  52 , the substrate  50 , and the STI regions  68  remain relatively unetched as compared to the second nanostructures  54 . In embodiments in which the second nanostructures  54  include, e.g., SiGe, and the first nanostructures  52  include, e.g., Si or SiC, hydrogen fluoride, another fluorine-based gas, or the like may be used to remove the second nanostructures  54  in the p-type region  50 P. 
     As illustrated in  FIG. 16A , the first nanostructures  52  may have a height H 1  and a width W 1 , and a ratio of the height H 1  to the width W 1  may be in a range of about 0.05 to about 4. In some embodiments, the ratio is sufficient to avoid affecting I on  of the device while still being controllable during the deposition process. For example, it has been observed that when the ratio of the height H 1  to the width W 1  is greater than  4 , the channel region of the nano-FET may be too thick and negatively affect I on  of the resulting device. It has been observed when the ratio of the height H 1  to the width W 1  is greater than  4 , the channel region may be too thin to be controlled during deposition due to a physical limitation of the film deposition process. 
     In other embodiments, the channel regions in the n-type region  50 N and the p-type region  50 P may be formed simultaneously, for example by removing the first nanostructures  52  in both the n-type region  50 N and the p-type region  50 P or by removing the second nanostructures  54  in both the n-type region  50 N and the p-type region  50 P. In such embodiments, channel regions of n-type NSFETs and p-type NSFETS may have a same material composition, such as silicon, silicon germanium, or the like.  FIGS. 26A, 26B, and 27C  illustrate a structure resulting from such embodiments where the channel regions in both the p-type region  50 P and the n-type region  50 N are provided by the second nanostructures  54  and comprise silicon, for example. In such embodiments, the second nanostructures  54  may have a same dimension as discussed above for the first nanostructures  52  in  FIG. 16A . 
       FIGS. 17A through 19B  illustrate forming the gate dielectrics  100  and the gate electrodes  102  in the p-type region  50 P, and the n-type region  50 N may be masked at least while forming the gate electrodes  102  in the p-type region  50 P (e.g., as described below in  FIGS. 18A through 19B ). 
     In  FIGS. 17A and 17B , gate dielectrics  100  are deposited conformally in the second recesses  98  in the p-type region  50 P. The gate dielectrics  100  comprise one or more dielectric layers, such as an oxide, a metal oxide, the like, or combinations thereof. For example, in some embodiments, the gate dielectrics  100  may comprise a first gate dielectric  101  (e.g., comprising silicon oxide, or the like) and a second gate dielectric  103  (e.g., comprising a metal oxide, or the like) over the first gate dielectric  101 . In some embodiments, the second gate dielectric  103  includes a high-k dielectric material, and in these embodiments, the second gate dielectric  103  may have a k value greater than about 7.0, and may include a metal oxide or a silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The first gate dielectric  101  may be referred to as an interfacial layer, and the second gate dielectric  103  may be referred to as a high-k gate dielectric in some embodiments. 
     The structure of the gate dielectrics  100  may be the same or different in the n-type region  50 N and the p-type region  50 P. For example, the n-type region  50 N may be masked or exposed while forming the gate dielectrics  100  in the p-type region  50 P. In embodiments where the n-type region  50 N is exposed, the gate dielectrics  100  may be simultaneously formed in the n-type regions  50 N. The formation methods of the gate dielectrics  100  may include molecular-beam deposition (MBD), ALD, PECVD, and the like. 
     In  FIGS. 18A and 18B , a conductive material  105  is deposited conformally on the gate dielectrics  100  in the p-type region  50 P. In some embodiments, the conductive material  105  is a p-type WFM layer, comprising titanium nitride, tantalum nitride, tungsten nitride, molybdenum nitride, or the like. The conductive material  105  may be deposited by CVD, ALD, PECVD, PVD, or the like. In some embodiments, the conductive material  105  may be deposited on exposed surfaces of the gate dielectrics  100  to a sufficient thickness such that the conductive material  105  merges in regions  50 I between adjacent first nanostructures  52  (e.g., the first nanostructures  52 A,  52 B, and  52 C). For example, the conductive material  105  may be deposited on surfaces of the first nanostructures  52  in the regions  50 I, and as the conductive material  105  increases in thickness during the deposition, separated portions of the conductive material  105  may touch and merge along seams  105 S. Specifically, deposition of the conductive material  105  may continue until a first portion  105 A of the conductive material  105  merges with a second portion  105 B of the conductive material  105  in the regions  50 I. 
     As illustrated in  FIG. 18A , the conductive material  105  may have a thickness T 1  outside of the regions  50 I (e.g., the unmerged regions of the conductive material  105 ) and a thickness T 2  in the regions  50 I (e.g., the merged regions of the conductive material  105 ). For example, the conductive material  105  may have the thickness T 1  on sidewalls of the first nanostructures  52  and on a topmost surface of the first nanostructures  52 . The thickness T 1  may be of a sufficient thickness to fill the space between neighboring first nanostructures  52 , for example, the first nanostructures  52 A,  52 B, and  52 C. For example, the thickness T 1  may be at least one half of the thickness T 2 , and a ratio of the thickness T 2  to the thickness T 1  may be no more than about 2:1. 
     In some embodiments, the thickness T 1  may be in a range from about 30 Å to about 50 Å. It has been observed that when the thickness T 1  is greater than about 50 Å, the volume of the conductive material  105  may be unnecessarily large and limit the process window of forming a filling metal for the gate electrode (e.g., the fill metal  117  discussed below). It has been observed that when the thickness T 1  is less than about 30 Å, the conductive layer  10  may not sufficiently fill the space between neighboring ones of the first nanostructures  52 , which may result in unstable threshold voltage performance in the resulting transistor. 
     At its narrowest point between the first nanostructures  52 A, the conductive material  105  has a width W 2 . In some embodiments, the width W 2  is in a range of about 10 nm to about 180 nm. It has been observed that when the width W 2  is greater than about 180 nm, process control of depositing the conductive material  105  and patterning/etching films in the regions  50 I may be negatively affected (e.g., similar to the effects of a high aspect ratio). It has been observed than when the width W 2  is less than about 10 nm, the effective channel length may be too short, which negatively affects I on  of the resulting transistor. 
     Further, in some embodiments, the ratio of the thickness T 2  to the width W 2  is in a range of about 0.03 to about 1. It has been observed that when the ratio of the thickness T 2  to the width W 2  is greater than about 1, the conductive layer  104  may be too thick, which negatively affects I on  of the resulting transistor. It has been observed than when the ratio of the thickness T 2  to the width W 2  is less than about 0.03, process control for depositing the conductive material  105  in the regions  50 I may be negatively affected (e.g., similar to the effects of a high aspect ratio). 
     The conductive material  105  fills a remaining space between the first nanostructures  52 . For example, the regions  50 I span an entire distance between adjacent ones of the first nanostructures  52  (e.g., between the first nanostructures  52 A and  52 B or between the first nanostructures  52 B and  52 C). The regions  50 I may by filled with a first portion (e.g., first gate dielectrics  100 A) of the gate dielectrics  100 , a merged portion of the conductive material  105  over and contacting the first gate dielectrics  100 A, and a second portion (e.g., second gate dielectrics  100 B) of the gate dielectrics  100  over and contacting the merged portion of the conductive material  105 . The first gate dielectrics  100 A include interfacial layer  101 A and high-k gate dielectric  103 A, and the second gate dielectrics  100 B include interfacial layer  101 B and high-k gate dielectric  103 B. That is, the conductive material  105  may extend continuously and completely fill an area between portions of the gate dielectrics  100  on adjacent ones of the first nanostructures  52 . Notably, there is no barrier layer separating different areas of the conductive material  105  in the regions  50 I. For example, the gate electrode may be free of any barrier layers in the regions  50 I. By omitting a barrier layer in the inner regions  50 I, the manufacturing process can be simplified. Further, it has been observed that the thickness variation of the conductive material  105  (e.g., the difference between the thicknesses T 1  and T 2 ) does not significantly impact the electrical performance of the resulting transistor. For example, in experimental data, transistors with a conductive material  105  having varying thicknesses (e.g., as illustrated in  FIGS. 18A and 18B ) had an effective work function of about 4.89 V. In comparison, transistors with a more uniform WFM layer (e.g., as provided by an intervening barrier layer preventing the WFM layer from merging in the regions  50 I) had an effective work function of about 4.90V. Accordingly, various embodiments allow transistors to be manufactured more easily with a similar effective work function and without significantly degrading the electrical performance of the resulting transistor. 
     In  FIGS. 19A, 19B, 19C, and 19D , remaining portions of the gate electrodes  102  are deposited to fill the remaining portions of the second recesses  98 . For example, an adhesion layer  115  and a fill metal  117  may be deposited over the conductive material  105 . The resulting gate electrodes  102  are formed for replacement gates and may comprise the conductive material  105 , the adhesion layer  115 , and the fill metal  117 .  FIG. 19C  illustrates a top down view along line X-X′ of  FIG. 19B  (e.g., in the regions  50 I) while  FIG. 19D  illustrates a top down view along line Y-Y′ of  FIG. 19B  (e.g., through the first nanostructures  52 ). 
     In some embodiments, the adhesion layer  115  is deposited conformally on the conductive material  105  in the p-type region  50 P. In some embodiments, the adhesion layer  115  comprises titanium nitride, tantalum nitride, or the like. The adhesion layer  115  may be deposited by CVD, ALD, PECVD, PVD, or the like. The adhesion layer  115  may alternately be referred to as a glue layer and improves adhesion between the conductive material  105  and the overlying fill metal  117 , for example. 
     The fill metal  117  may then be deposited over the adhesion layer  115 . In some embodiments, the fill metal  117  comprises cobalt, ruthenium, aluminum, tungsten, combinations thereof, or the like, which is deposited by CVD, ALD, PECVD, PVD, or the like. In some embodiments, the fill metal  117  may comprise tungsten deposited using a CVD process. It has been observed that CVD provides an improved deposition rate for the fill metal  117 . In some embodiments, the CVD process to deposit the fill metal  117  may include supplying a first precursor (e.g., WF 6 , or the like) and a second precursor (e.g., SiH 4 , or the like) in the CVD process chamber. In some embodiments, the first precursor and the second precursor may be supplied simultaneously during the CVD process for the fill metal  117 . 
     In the p-type region  50 P, the gate dielectrics  100 , the conductive material  105 , the adhesion layer  115 , and the fill metal  117  may each be formed on top surfaces, sidewalls, and bottom surfaces of the first nanostructures  52 . The gate dielectrics  100 , the conductive material  105 , the adhesion layer  115 , and the fill metal  117  may also be deposited on top surfaces of the first ILD  96 , the CESL  94 , the first spacers  81 , and the STI regions  68 . After the filling of the second recesses  98 , a planarization process, such as a CMP, may be performed to remove the excess portions of the gate dielectrics  100 , the conductive material  105 , the adhesion layer  115 , and the fill metal  117 , which excess portions are over the top surface of the first ILD  96 . The remaining portions of material of the gate electrodes  102  and the gate dielectrics  100  thus form replacement gate structures of the resulting nano-FETs. The gate electrodes  102  and the gate dielectrics  100  may be collectively referred to as “gate structures.” 
     Although  FIGS. 19A and 19B  illustrate the gate dielectrics  100  and the gate electrodes  102  as having straight sidewalls and squared corners, the gate dielectrics  100  and the gate electrodes  102  may have a different configuration. For example,  FIG. 20  illustrates a cross-sectional view of the gate dielectrics  100  and the gate electrodes  102  according to another embodiment. In  FIG. 20 , like reference numerals indicate like elements as  FIGS. 19A and 19B  formed using like processes. However, in  FIG. 20 , due to the first nanostructures  52  having rounded corners, the gate dielectrics  100  and the gate electrodes  102  may likewise have rounded corners. 
     Further, although  FIGS. 19A and 19B  illustrate a bottommost one of the first nanostructures  52  touching an underlying fin  66 , the bottommost one of the first nanostructures  52  (e.g., the first nanostructure  52 A) may be separated from the underlying fin  66  as illustrated by  FIG. 21 . In  FIG. 20 , like reference numerals indicate like elements as  FIGS. 19A and 19B  formed using like processes. The structure of  FIG. 21  may be formed, for example, by disposing a second nanostructure  54  between the first nanostructure  52  and the fin  66 , and then subsequently removing the second nanostructure  54  as described above. As a result, portions of the gate dielectrics  100  and the conductive material  105  may be disposed between a bottommost one of the first nanostructures  52  and the fin  66 . 
       FIGS. 22A and 22B  illustrate a gate stack in the n-type region  50 N. Forming the gate stack in the n-type region  50 N may include first removing the first nanostructures  52  in the n-type region  50 N. The first nanostructures  52  may be removed by forming a mask (not shown) over the p-type region  50 P and performing an isotropic etching process such as wet etching or the like using etchants which are selective to the materials of the first nanostructures  52 , while the second nanostructures  54 , the substrate  50 , and the STI regions  68  remain relatively unetched as compared to the first nanostructures  52 . In embodiments in which the first nanostructures  52 A- 52 C include, e.g., SiGe, and the second nanostructures  54 A- 54 C include, e.g., Si or SiC, tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH 4 OH) or the like may be used to remove the first nanostructures  52  in the n-type region  50 N. 
     The gate stack is then formed over and around the second nanostructures  54  in the n-type region  50 N. The gate stack includes the gate dielectrics  100  and gate electrodes  127 . In some embodiments, the gate dielectrics  100  in the n-type region  50 N and the p-type region  50 P may be formed simultaneously. Further, at least portions of the gate electrodes  127  may be formed either before or after forming the gate electrodes  102  (see  FIGS. 19A and 19B ), and at least portions of the gate electrodes  127  may be formed while the p-type region  50 P is masked. As such, the gate electrodes  127  may comprise different materials than the gate electrodes  102 . For example, the gate electrodes  127  may comprise a conductive layer  121 , a barrier layer  123 , and a fill metal  125 . The conductive layer  121  may be an n-type work function metal (WFM) layer comprising an n-type metal, such as, titanium aluminum, titanium aluminum carbide, tantalum aluminum, tantalum carbide, combinations thereof, or the like. The conductive layer  121  may be deposited by CVD, ALD, PECVD, PVD, or the like. The barrier layer  123  may comprise titanium nitride, tantalum nitride, tungsten carbide, combinations thereof, or the like, and the barrier layer  123  may further function as an adhesion layer. The barrier layer  123  may be deposited by CVD, ALD, PECVD, PVD, or the like. The fill metal  125  may comprise cobalt, ruthenium, aluminum, tungsten, combinations thereof, or the like, which is deposited by CVD, ALD, PECVD, PVD, or the like. The fill metal  125  may or may not have a same material composition and be deposited concurrently with the fill metal  117 . 
     After the filling of the second recesses  98 , a planarization process, such as a CMP, may be performed to remove the excess portions of the gate dielectrics  100  and the gate electrodes  127 , which excess portions are over the top surface of the first ILD  96 . The remaining portions of material of the gate electrodes  127  and the gate dielectrics  100  thus form replacement gate structures of the resulting nano-FETs of the n-type region  50 N. The CMP processes to remove excess materials of the gate electrodes  102  in the p-type region  50 P and to remove excess materials of the gate electrodes  127  in the n-type region  50 N may be performed concurrently or separately. 
     In  FIGS. 23A-23C , the gate structure (including the gate dielectrics  100 , the gate electrodes  102 , and the gate electrodes  127 ) is recessed, so that a recess is formed directly over the gate structure and between opposing portions of first spacers  81 . A gate mask  104  comprising one or more layers of dielectric material, such as silicon nitride, silicon oxynitride, or the like, is filled in the recess, followed by a planarization process to remove excess portions of the dielectric material extending over the first ILD  96 . Subsequently formed gate contacts (such as the gate contacts  114 , discussed below with respect to  FIGS. 24A and 24B ) penetrate through the gate mask  104  to contact the top surface of the recessed gate electrodes  102  and  127 . 
     As further illustrated by  FIGS. 23A-23C , a second ILD  106  is deposited over the first ILD  96  and over the gate mask  104 . In some embodiments, the second ILD  106  is a flowable film formed by FCVD. In some embodiments, the second ILD  106  is formed of a dielectric material such as PSG, BSG, BPSG, USG, or the like, and may be deposited by any suitable method, such as CVD, PECVD, or the like. 
     In  FIGS. 24A-24C , the second ILD  106 , the first ILD  96 , the CESL  94 , and the gate masks  104  are etched to form third recesses  108  exposing surfaces of the epitaxial source/drain regions  92  and/or the gate structure. The third recesses  108  may be formed by etching using an anisotropic etching process, such as RIE, NBE, or the like. In some embodiments, the third recesses  108  may be etched through the second ILD  106  and the first ILD  96  using a first etching process; may be etched through the gate masks  104  using a second etching process; and may then be etched through the CESL  94  using a third etching process. A mask, such as a photoresist, may be formed and patterned over the second ILD  106  to mask portions of the second ILD  106  from the first etching process and the second etching process. In some embodiments, the etching process may over-etch, and therefore, the third recesses  108  extend into the epitaxial source/drain regions  92  and/or the gate structure, and a bottom of the third recesses  108  may be level with (e.g., at a same level, or having a same distance from the substrate), or lower than (e.g., closer to the substrate) the epitaxial source/drain regions  92  and/or the gate structure. Although  FIG. 23B  illustrates the third recesses  108  as exposing the epitaxial source/drain regions  92  and the gate structure in a same cross section, in various embodiments, the epitaxial source/drain regions  92  and the gate structure may be exposed in different cross-sections, thereby reducing the risk of shorting subsequently formed contacts. 
     After the third recesses  108  are formed, silicide regions  110  are formed over the epitaxial source/drain regions  92 . In some embodiments, the silicide regions  110  are formed by first depositing a metal (not shown) capable of reacting with the semiconductor materials of the underlying epitaxial source/drain regions  92  (e.g., silicon, silicon germanium, germanium) to form silicide or germanide regions, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other noble metals, other refractory metals, rare earth metals or their alloys, over the exposed portions of the epitaxial source/drain regions  92 , then performing a thermal anneal process to form the silicide regions  110 . The un-reacted portions of the deposited metal are then removed, e.g., by an etching process. Although silicide regions  110  are referred to as silicide regions, silicide regions  110  may also be germanide regions, or silicon germanide regions (e.g., regions comprising silicide and germanide). In an embodiment, the silicide region  110  comprises TiSi, and has a thickness in a range between about 2 nm and about 10 nm. 
     Next, in  FIGS. 25A-25C , contacts  112  and  114  (may also be referred to as contact plugs) are formed in the third recesses  108 . The contacts  112  and  114  may each comprise one or more layers, such as barrier layers, diffusion layers, and fill materials. For example, in some embodiments, each of the contacts  112  and  114  includes a barrier layer and a conductive material, and is electrically coupled to the underlying conductive feature (e.g., the gate electrodes  102 , the gate electrodes  127 , and/or silicide region  110  in the illustrated embodiment). The contacts  114  are electrically coupled to the gate electrodes  102  and  127  and may be referred to as gate contacts, and the contacts  112  are electrically coupled to the silicide regions  110  and may be referred to as source/drain contacts. The barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material may be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process, such as a CMP, may be performed to remove excess material from a surface of the second ILD  106 . 
       FIGS. 26A-C  illustrate cross-sectional views of a device according to some alternative embodiments.  FIGS. 26A  illustrates reference cross-section A-A′ illustrated in  FIG. 1 .  FIG. 26B  illustrates reference cross-section B-B′ illustrated in  FIG. 1 .  FIG. 26C  illustrates reference cross-section C-C′ illustrated in  FIG. 1 . In  FIGS. 26A-C , like reference numerals indicate like elements formed by like processes as the structure of  FIGS. 25A-C . However, in  FIGS. 26A-C , channel regions in the n-type region  50 N and the p-type region  50 P comprise a same material. For example, the second nanostructures  54 , which comprise silicon, provide channel regions for p-type NSFETs in the p-type region  50 P and for n-type NSFETs in the n-type region  50 N. The structure of  FIGS. 26A-C  may be formed, for example, by removing the first nanostructures  52  from both the p-type region  50 P and the n-type region  50 N simultaneously; depositing the gate dielectrics  100  and the gate electrodes  102  around the second nanostructures  54  in the p-type region  50 P; and depositing the gate dielectrics  100  and the gate electrodes  104  around the first nanostructures  54  in the n-type region  50 N. 
     Various embodiments provide a gate stack of a transistor (e.g., a nano-FET) without a barrier layer between adjacent nanostructures. It has been determined that thickness variations due to merged regions of the WFM layers (e.g., between nanowires of a nano-FETs) may not significantly affect the electrical characteristics of the transistor (e.g., relatively similar effective work functions have been observed). By not depositing a barrier layer around the WFM layer (e.g., to prevent portions of the WFM layer form merging), manufacturing ease can be improved. This is particularly true in advanced semiconductor nodes with small feature sizes as barrier layer materials (e.g., tantalum nitride, or the like) can be difficult to deposit in small spaces. Thus, by omitting such barrier layers in the gate stacks and allowing the WFM layers to merge in certain areas, manufacturing ease can be improved and manufacturing defects (e.g., resulting from poor barrier layer deposition) can be reduced without significantly impacting the electrical performance of the resulting transistor. 
     In some embodiments, a device includes a first nanostructure; a second nanostructure over the first nanostructure; a first high-k gate dielectric disposed around the first nanostructure; a second high-k gate dielectric being disposed around the second nanostructure; and a gate electrode over the first high-k gate dielectric and the second high-k gate dielectric. A portion of the gate electrode between the first nanostructure and the second nanostructure comprises a first portion of a p-type work function metal filling an area between the first high-k gate dielectric and the second high-k gate dielectric. Optionally, in some embodiments, the first portion of the p-type work function metal comprises a seam between the first nanostructure and the second nanostructure. Optionally, in some embodiments, the first portion of the p-type work function metal has a first thickness, wherein a second portion of the p-type work function metal on a sidewall of the first nanostructure has a second thickness, and wherein the first thickness is greater than the second thickness. Optionally, in some embodiments, a ratio of the first thickness to the second thickness is no more than 2:1. Optionally, in some embodiments, the second thickness is in a range of 30 Å to 50 Å. Optionally, in some embodiments, a ratio of the second thickness to a minimum width of the p-type work function metal is in a range of 0.03 to 1. Optionally, in some embodiments, the minimum width of the p-type work function metal is in a range of 10 nm to 180 nm. Optionally, in some embodiments, the portion of the gate electrode between the first nanostructure and the second nanostructure is free of any barrier layers. Optionally, in some embodiments, the gate electrode further comprises an adhesion layer over the p-type work function metal, the adhesion layer does not extend between the first nanostructure and the second nanostructure. Optionally, in some embodiments, a ratio of a height of the first nanostructure to a width of the first nanostructure is in a range of 0.05 to 4. 
     In some embodiments, a transistor comprises a first nanostructure over a semiconductor substrate; a second nanostructure over the first nanostructure; a gate dielectric surrounding the first nanostructure and the second nanostructure; and a gate electrode over the gate dielectric. The gate electrode comprises: a p-type work function metal, wherein the p-type work function metal extends continuously from a first portion of the gate dielectric on the first nanostructure to a second portion of the gate dielectric on the second nanostructure; an adhesion layer over the p-type work function metal; and a fill metal over the adhesion layer. Optionally, in some embodiments, the p-type work function metal has a first thickness on a top surface of the second nanostructure and a second thickness between the first nanostructure and the second nanostructure, wherein the first thickness is less than the second thickness. Optionally, in some embodiments, the p-type work function metal comprises a seam between the first nanostructure and the second nanostructure. Optionally, in some embodiments, the p-type work function metal comprises titanium nitride. Optionally, in some embodiments the transistor further comprises an interfacial layer under the gate dielectric, the interfacial layer surrounding the first nanostructure and the second nanostructure, and the gate dielectric comprises a high-k material. 
     In some embodiments, a method comprises first nanostructure and a second nanostructure, the first nanostructure is disposed over the second nanostructure; and depositing a p-type work function metal over the gate dielectric. Depositing the p-type work function metal comprises: depositing a first portion of the p-type work function metal on a top surface of the second nanostructure and a second portion of the p-type work function metal on a bottom surface of the second nanostructure; and continuing to deposit the p-type work function metal until the first portion of the p-type work function metal merges with the second portion of the p-type work function metal. Optionally, in some embodiments, the method further includes depositing an adhesion layer over the p-type work function metal; and depositing a fill metal over the adhesion layer. Optionally, in some embodiments, depositing the p-type work function metal comprises depositing the p-type work function metal to have: a first thickness between the first nanostructure and the second nanostructure; and a second thickness on a sidewall of the first nanostructure, the first thickness is greater than the second thickness. Optionally, in some embodiments, a ratio of the first thickness to the second thickness is no more than 2:1. Optionally, in some embodiments, depositing the p-type work function metal comprises forming a seam between the first portion of the p-type work function metal and the second portion of the p-type work function metal. 
     The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.