Patent Publication Number: US-8115336-B1

Title: Power saving circuit

Description:
INCORPORATION BY REFERENCE 
     This Application is a continuation of U.S. application Ser. No. 11/777,758, filed Jul. 13, 2007, which claims priority under 35 U.S.C. §119(e) to U.S. Provisional Application No. 60/831,804, filed Jul. 19, 2006. The disclosures of the applications referenced above are incorporated herein by reference. 
    
    
     BACKGROUND 
     The present disclosure relates to a power saving circuit, and more particularly to a power saving circuit capable of controlling an amount of current flowing through a load circuit by regulating a voltage of a node. 
     Power saving circuits are incorporated into a vast number of devices used in everyday life. For example, power saving circuits are used in automobile engines, cellular telephones, magnetic hard disk drives, fiber optic communication systems, and even children&#39;s toys. 
     Unfortunately, many power saving circuits suffer from such performance shortfalls as limited cross-talk control and interference decoupling. In a power sharing configuration, any variance in the power requirement of a first circuit may substantially vary the power available to a second circuit, thus having a detrimental effect on the operation of the second circuit. The variance in the power requirement of a circuit may be due to either a predetermined change in the operation of the circuit, manufacturing process variations, response to environmental circumstances, or the like. 
     Power saving circuits having limited cross-talk and interference control may not sufficiently lessen the effect of the variance of one circuit&#39;s power requirements on another circuit, and thus, result in improper operation of the circuits and inefficient use of power. Accordingly, it should be appreciated that, either due to the internal or external factors discussed above, a particular power saving circuit may cross-couple dynamic current or voltage fluctuations of one circuit to another to the detriment of the system incorporating the power saving circuit. 
     SUMMARY OF THE DISCLOSURE 
     A power saving circuit (PSC) is disclosed that includes a first circuit and a second circuit electrically coupled in series in a power sharing configuration. The PSC may further include a regulator that is electrically coupled to a first node between the first and second circuits. The regulator can supply current to the first node when the first circuit requires less current or the second circuit requires more current, and the regulator can remove current from the first node when the first circuit requires more current or the second circuit requires less current. 
     The regulator determines whether to supply or remove current by comparing a first reference voltage with a first node voltage, so that when the first node voltage is less than the first reference voltage, the regulator increases an amount of current supplied to the first node, and when the first node voltage is greater than the first reference voltage, the regulator decreases an amount of current supplied to the first node. 
     The PSC can further include a first voltage controlling circuit that is coupled between the first circuit and the first node, and a second voltage controlling circuit that is coupled between the first node and the second circuit. The first voltage controlling circuit can include a first transistor coupled in series between the first circuit and the first node, and a first amplifier having its non-inverting input coupled to a second reference voltage, its inverting input coupled to a second node between the first circuit and the first transistor, and its output coupled to the gate of the first transistor. Similarly, the second voltage controlling circuit can include a second transistor coupled in series between the second circuit and the first node, and a second amplifier having its non-inverting input coupled to a third reference voltage, its inverting input coupled to a third node between the second circuit and the first transistor, and its output coupled to the gate of the second transistor. 
     The first voltage controlling circuit compares the second reference voltage with a voltage of the second node, so that when the second node voltage is less than the second reference voltage, the first voltage controlling circuit increases a resistance between the source and drain of the first transistor, and when the second node voltage is greater than the second reference voltage, the first voltage controlling circuit decreases a resistance between the source and drain of the first transistor. Similarly, the second voltage controlling circuit compares the third reference voltage with a of the third node, so that when the third node voltage is less than the third reference voltage, the second voltage controlling circuit increases a resistance between the source and drain of the second transistor, and when the third node voltage is greater than the third reference voltage, the second voltage controlling circuit decreases a resistance between the source and drain of the second transistor. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Embodiments of the power-saving circuit (PSC) will be described with reference to the following drawings, wherein like numerals designate like elements, and wherein: 
         FIG. 1  shows a block diagram of an exemplary circuit configuration of PSC; 
         FIG. 2  shows a first exemplary PSC scheme; 
         FIG. 3  shows a second exemplary PSC scheme; 
         FIG. 4  shows a flow-chart of an exemplary PSC process for regulating voltage at one node; and 
         FIG. 5  shows a flow-chart of an exemplary PSC process for regulating voltage at more than one node. 
     
    
    
     DETAILED DESCRIPTION OF EMBODIMENTS 
     In the following descriptions, many of the exemplary circuits are shown to include n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) in a variety of configurations. While MOSFET devices are used by example, the disclosed circuits may be implemented using any number of other transistor types, such as J-FETs, bipolar transistors, and the like. Additionally, while n-channel devices are used in the following examples, the same general approaches may also apply to circuits incorporating p-channel FETs or PNP bipolar transistors, for example. 
     Still further, while the terms “drain” and “source” are used for ease of explanation and to adhere to traditional engineering usage, it should be recognized that a drain and source of a FET transistor may be considered interchangeable, and for the following descriptions merely thought of as a first end and a second end of a semiconductor channel unless otherwise stated or apparent to one of ordinary skill in the art. 
       FIG. 1  shows a block diagram of an exemplary configuration of a power-saving circuit (PSC)  100  that may include a first circuit  110 , a regulator  150 , and a second circuit  120  coupled in series between a supply voltage V DD  and a ground GND. Generally, the arrangement is a power sharing configuration between the first circuit  110  and second circuit  120 . As can be seen, currents I 1  and I 2  are the electric currents flowing through first circuit  110  and second circuit  120 , respectively. 
     In this configuration, regulator  150  can be any device that ensures that a voltage of at least one node (not shown) located between first circuit  110  and second circuit  120  is substantially constant during operation by regulating the amount of current flowing through that node. For example, a regulator  150  can include one or more voltage amplifiers, current amplifiers, operational amplifiers, transconductance amplifiers, transimpedance amplifiers, differential pairs, pulse width modulation devices, switching regulators, or the like. By regulating an amount of current at the node, the dynamic current usage of the first circuit  110  can be isolated from the second circuit  120 , and vice versa. Thus, the operation of the first circuit  110  should not interfere with that of the second circuit  120 , and vice versa. 
     It should be understood that first and second circuits  110  and  120  are not limited to any particular circuit and can be any digital, analog, or mixed signal load circuit including any combination of active and passive electronic devices or the like. 
     During operation, the PSC  100  operates to reduce or eliminate interference between first circuit  110  and second circuit  120 , which can occur as a result of the power sharing configuration. For example, when first circuit  110  and second circuit  120  dynamically require more or less power, and therefore require more or less current, a change in the power requirements of the first circuit  110  can affect the current available to second circuit  120 , and vice versa. By monitoring a voltage between first and second circuits  110  and  120 , regulator  150  can adjust the current passing between the first and second circuits  110  and  120  so that dynamic current usage by first circuit  110  does not affect the current usage of second circuit  120 , and vice versa. 
     While  FIG. 1  only shows first and second circuits  110  and  120 , and a single voltage regulator  150 , it should be understood that any number of circuits may be provided with any number of voltage regulators. Furthermore, in order to facilitate ease of understanding, the operation of the exemplary embodiments of the PSC will be described with the assumption that first and second circuits  110  and  120  are treated as variable resistors. 
     As shown in  FIG. 2 , regulator  250 , which corresponds to regulator  150 , can include an amplifier AMP A  and a capacitor C 201 . In this case, amplifier AMP A  of PSC  200  has a non-inverting terminal coupled to a reference voltage supply circuit (not shown) that applies a reference voltage V REF     —     A  to the non-inverting terminal. Further, both an inverting input terminal and an output terminal of amplifier AMP A , as well as first circuit  110  and second circuit  120  are coupled together at node A. As also shown, capacitor C 201  can be coupled in series between node A and power supply GND in order to further stabilize the voltage at node A and also possibly to reduce or prevent any high frequency components of the current flowing through node A. 
     In the configuration shown in  FIG. 2 , amplifier AMP A  maintains node A at a reference voltage V REF     —     A . As described above, during operation, first and second circuits  110  and  120  may dynamically require more or less power, and thus, more or less current. As the requirement for current of either one or both of first and second circuits  110  and  120  changes, these circuits adjust their respective equivalent resistance in order to change an amount of current they draw, and thus, change the voltage at node A. Amplifier AMP A  senses this voltage change and adjusts the voltage at node A back to reference voltage V REF     —     A  by feeding or sinking an amount of electric current I 3  at node A. 
     For example, when first circuit  110  draws a first current I 1  from V DD , second circuit  120  draws a second current I 2  from node A, and when first currents I 1  and I 2  are equal, the voltage at node A is equal to reference voltage V REF     —     A . Under these circumstances, because amplifier AMP A  detects no change in the voltage at node A, it does not pass an additional third current I 3  through node A. 
     If, however, first circuit  110  requires more current, amplifier AMP A  will sink third current I 3  from node A, and allow first circuit  110  to draw more current from V DD , thus, satisfying first circuit&#39;s  110  need for more current while maintaining node A at reference voltage V REF     —     A . Specifically, when first circuit  110  requires more current, it will lower its equivalent resistance. Consequently, this will decrease the voltage drop across terminals  1  and  2  of first circuit  110 , and thus, increase the voltage at node A to a voltage greater than V REF     —     A . Amplifier AMP A  will sense that node A is at a voltage greater than V REF     —     A , and will begin to sink third current I 3  from node A. 
     In this case, first current I 1  will increase by an amount equivalent to third current I 3 . The increase of first current I 1  will increase the voltage drop across terminals  1  and  2  of first circuit  110 , and, as a result, lower the voltage at node A back to reference voltage V REF     —     A . Accordingly, second current I 2  will remain substantially unchanged because the additional current that first circuit  110  will be drawing from V DD  will be drawn out by amplifier AMP A  at node A. This situation results in a relationship between I 1 , I 2 , and I 3  illustrated by equation (1) shown below.
 
 I   1   =I   2   +I   3   (1)
 
     On the other hand, if first circuit  110  requires less current, amplifier AMP A  will feed third current I 3  into node A, and allow first circuit  110  to draw less current from V DD , thus, satisfying first circuit&#39;s  110  need for less current while maintaining node A at reference voltage V REF     —     A . Specifically, when first circuit requires less current, it will increase its equivalent resistance. Consequently, this will increase the voltage drop across terminals  1  and  2  of first circuit  110 , and thus, lower the voltage at node A to a voltage less than V REF     —     A . Amplifier AMP A  will sense that node A is at a voltage less than V REF     —     A , and will begin to feed third current I 3  into node A. 
     In this case, first current I 1  will decrease by an amount equivalent to third current I 3 . The decrease of first current I 1  will decrease the voltage drop across terminals  1  and  2  of first circuit  110 , and, as a result, raise the voltage at node A back to reference voltage V REF     —     A . Accordingly, second current I 2  will remain substantially unchanged because amplifier AMP A  will supply second circuit  120  to compensate for the reduction in first current I 1  passing through first circuit  110 . This situation results in a relationship between I 1 , I 2 , and I 3  illustrated by equation (2) shown below.
 
 I   1   =I   2   −I   3   (2)
 
     When second circuit  120  requires more current, amplifier AMP A  will feed third current I 3  into node A, and allow second circuit  120  to draw more current from node A, thus, satisfying second circuit&#39;s  120  need for more current while maintaining node A at reference voltage V REF     —     A . Specifically, when second circuit requires more current, it will lower its equivalent resistance. Consequently, this will decrease the voltage drop across terminals  1  and  2  of second circuit  120 , and thus, lower the voltage at node A to a voltage less than V REF     —     A . Amplifier AMP A  will sense that node A is at a voltage less than V REF     —     A , and will begin to feed third current I 3  into node A. 
     In this case, second current I 2  will increase by an amount equivalent to third current I 3 . The increase of second current I 2  will increase the voltage drop across terminals  1  and  2  of second circuit  120 , and, as a result, increase the voltage at node A back to reference voltage V REF     —     A . Accordingly, first current I 1  will remain substantially unchanged because the additional current required by second circuit  120  will be supplied by amplifier AMP A  via node A. This situation results in a relationship between I 1 , I 2 , and I 3  illustrated by equation (3) shown below.
 
 I   2   =I   1   +I   3   (3)
 
     Conversely, when second circuit  120  requires less current, amplifier AMP A  will sink third current I 3  from node A, and allow second circuit  120  to draw less current from node A, thus, satisfying second circuit&#39;s  120  need for less current while maintaining node A at reference voltage V REF     —     A . Specifically, when second circuit requires less current, it will raise its equivalent resistance. Consequently, this will raise the voltage drop across terminals  1  and  2  of second circuit  120 , and thus, raise the voltage at node A to a voltage greater than V REF     —     A . Amplifier AMP A  will sense that node A is at a voltage greater than V REF     —     A , and will begin to sink third current I 3  from node A. 
     In this case, second current I 2  will decrease by an amount equivalent to third current I 3 . The decrease of second current I 2  will decrease the voltage drop across terminals  1  and  2  of second circuit  120 , and, as a result, lower the voltage at node A back to reference voltage V REF     —     A . Accordingly, first current I 1  will remain substantially unchanged because the additional current not used by second circuit  120  will be drawn out of node A via amplifier AMP A . This situation results in a relationship between I 1 , I 2 , and I 3  illustrated by equation (4) shown below.
 
 I   2   =I   1   −I   3   (4)
 
       FIG. 3  shows an exemplary schematic diagram of PSC  300  that includes first circuit  110 , second circuit  120 , transistors T P  and T N , capacitors C 301  and C 302 , and amplifiers AMP A , AMP B , and AMP C . PSC  300  includes nodes A, B, C, P, and N. As shown, node A couples drain terminals of transistors T P  and T N  and an inverting input terminal and an output terminal of AMP A ; node B couples second terminals of first circuit  110  and capacitor C 301 , a source terminal of transistor T P , and an inverting input terminal of amplifier AMP B ; node C couples first terminals of second circuit  120  and capacitor C 302 , a source terminal of transistor T N , and an inverting input terminal of amplifier AMP C ; node P couples an output terminal of amplifier AMP B  and a gate terminal of transistor T P ; and node N couples an output terminal of amplifier AMP C  and a gate terminal of transistor T N . A reference voltage supply circuit (not shown) is coupled to and applies reference voltages V REF     —     A , V REF     —     B , and V REF     —     C  to non-inverting terminals of amplifiers AMP A , AMP B , and AMP C , respectively. First terminals of first circuit  110  and capacitor C 301  are coupled to V DD ; and second terminals of second circuit  120  and capacitor C 302  are coupled to GND. 
     Capacitors C 301  and C 302  can be added in order to reduce or prevent the high frequency noise components of first and second currents I 1  and I 2 , respectively. 
     Reference voltages V REF     —     A , V REF     —     B , and V REF     —     C  are the voltages at which amplifiers AMP A , AMP B , and AMP C  maintain nodes A, B, and C, respectively. It should be understood that the reference voltages can be set to various voltages depending on circuit design parameters. 
     Transistors T P  and T N  and amplifiers AMP A , AMP B , and AMP C  compose a regulator  350 . Regulator  350  is similar to regulator  250  in that it includes amplifier AMP A  for regulating the voltage at node A. Regulator  350 , however, differs from regulator  250  in that it additionally includes transistors T P  and T N  coupled to amplifiers AMP B  and AMP C , respectively, for isolating first circuit  110  from second circuit  120  and regulating the voltages at nodes B and C. Because the voltages at nodes B and C are regulated, voltage variations at node A have a very minimal effect on the voltages at nodes B and C. Thus, with minimal voltage variations at nodes B and C, the currents through transistors T P  and T N , and hence the currents through first and second circuits  110  and  120 , can remain substantially constant. 
     For example, during operation, when first circuit  110  requires more current, it will lower its equivalent resistance. As a result, this will decrease the voltage drop across terminals  1  and  2  of first circuit  110  and increase the voltage at node B to a voltage greater than V REF     —     B . Amplifier AMP B  will sense that node B is at a voltage greater than V REF     —     B , and will decrease the voltage at node P so as to lower the channel resistance of transistor T P  and pull down the voltage at node B to reference voltage V REF     —     B . Lowering the channel resistance of transistor T P , however, will decrease the voltage drop across the source and drain of transistor T P , and thus, raise the voltage at node A. This, in turn, will trigger AMP A  to sink third current I 3  from node A in order to pull the voltage at node A back down to V REF     —     A . 
     During the period when the voltage at node A is pulled up, the voltage at node C may begin to rise. However, AMP C  will sense the change in the voltage at node C and, due to its high gain response, will immediately adjust the channel resistance of transistor T N  so as to pull the voltage at node C back down to reference voltage V REF     —     C . In this manner, amplifier AMP C  will maintain the voltage at node C at reference voltage V REF     —     C  to reduce or prevent fluctuation of second current I 2  flowing through second circuit  120 . 
     First current I 1 , however, will increase by an amount equivalent to third current I 3 , satisfying first circuit&#39;s  110  requirement for more current, and resulting in a relationship between I 1 , I 2 , and I 3  illustrated by equation (1) shown above. 
     On the other hand, when first circuit  110  requires less current, it will raise its equivalent resistance. As a result, this will increase the voltage drop across terminals  1  and  2  of first circuit  110  and decrease the voltage at node B to a voltage less than V REF     —     B . Amplifier AMP B  will sense that node B is at a voltage less than V REF     —     B , and will increase the voltage at node P so as to raise the channel resistance of transistor T P  and pull up the voltage at node B to reference voltage V REF     —     B . Raising the channel resistance of transistor T P , however, will increase the voltage drop across the source and drain of transistor T P , and thus, lower the voltage at node A. This, in turn, will trigger AMP A  to feed third current I 3  into node A in order to pull the voltage at node A back up to V REF     —     A . 
     During the period when the voltage at node A is pulled down, the voltage at node C may begin to fall. However, AMP C  will sense the change in the voltage at node C and, due to its high gain response, will immediately adjust the channel resistance of transistor T N  so as to pull the voltage at node C back up to reference voltage V REF     —     C . In this manner, amplifier AMP C  will maintain the voltage at node C at reference voltage V REF     —     C  to prevent or reduce fluctuation of second current I 2  flowing through second circuit  120 . 
     First current I 1 , however, will decrease by an amount equivalent to third current I 3 , satisfying first circuit&#39;s  110  requirement for less current, which results in a relationship between I 1 , I 2 , and I 3  illustrated by equation (2) shown above. 
     When second circuit  120  requires more current, it will lower its equivalent resistance. As a result, this will decrease the voltage drop across terminals  1  and  2  of second circuit  120  and decrease the voltage at node C to a voltage less than V REF     —     C . Amplifier AMP C  will sense that node C is at a voltage less than V REF     —     C , and will increase the voltage at node N so as to lower the channel resistance of transistor T N  and pull up the voltage at node C to reference voltage V REF     —     C . Lowering the channel resistance of transistor T N , however, will decrease the voltage drop across the source and drain of transistor T N , and thus, lower the voltage at node A. This, in turn, will trigger AMP A  to feed third current I 3  into node A in order to pull the voltage at node A back down to V REF     —     A . 
     During the period when the voltage at node A is pulled down, the voltage at node B may begin to fall. However, AMP B  will sense the change in the voltage at node B and, due to its high gain response, will immediately adjust the channel resistance of transistor T P  so as to pull the voltage at node B back up to reference voltage V REF     —     B . In this manner, amplifier AMP B  will maintain the voltage at node B at reference voltage V REF     —     B  to prevent or reduce fluctuation of first current I 1  flowing through first circuit  110 . 
     Second current I 2 , however, will increase by an amount equivalent to third current I 3 , satisfying second circuit&#39;s  120  requirement for more current, which results in a relationship between I 1 , I 2 , and I 3  illustrated by equation (3) shown above. 
     Conversely, when second circuit  120  requires less current, it will raise its equivalent resistance. As a result, this will increase the voltage drop across terminals  1  and  2  of second circuit  120  and increase the voltage at node C to a voltage greater than V REF     —     C . Amplifier AMP C  will sense that node C is at a voltage greater than V REF     —     C , and will decrease the voltage at node N so as to increase the channel resistance of transistor T N  and pull up the voltage at node C to reference voltage V REF     —     C . Increasing the channel resistance of transistor T N , however, will increase the voltage drop across the source and drain of transistor T N , and thus, increase the voltage at node A. This, in turn, will trigger AMP A  to sink third current I 3  from node A in order to pull the voltage at node A back down to V REF     —     A . 
     During the period when the voltage at node A is pulled up, the voltage at node B may begin to rise. However, AMP B  will sense the change in the voltage at node B and, due to its high gain response, will immediately adjust the channel resistance of transistor T P  so as to pull the voltage at node B back down to reference voltage V REF     —     B . In this manner, amplifier AMP B  will maintain the voltage at node B at reference voltage V REF     —     B  to prevent or reduce fluctuation of first current I 1  flowing through first circuit  110 . 
     Second current I 2 , however, will decrease by an amount equivalent to third current I 3 , satisfying second circuit&#39;s  120  requirement for less current, which results in a relationship between I 1 , I 2 , and I 3  illustrated by equation (4) shown above. 
       FIG. 4  shows a flow-chart  1000  of an exemplary PSC process. The exemplary PSC process can be implemented in a circuit where dynamic current usage of one component needs to be isolated from another component, such as the PSC circuit shown in  FIG. 2 . 
     The process begins and proceeds to step S 1002  where a determination is made as to whether a voltage V A  is equal to reference voltage V REF     —     A . If voltage V A  is determined to not be equal to reference voltage V REF     —     A , then the process proceeds to step S 1004 . Otherwise, the process proceeds to step S 1010 . 
     In step S 1004 , a determination is made as to whether voltage V A  is greater than reference voltage V REF     —     A . If voltage V A  is determined to be greater than reference voltage V REF     —     A , then the process proceeds to step S 1006 . Otherwise, the process proceeds to step S 1008 . 
     In step S 1008 , the process raises voltage V A  and returns to step S 1002 . In step S 1006 , the process lowers voltage V A  and returns to step S 1002 . For example, in PSC  200 , regulator  250  increases the voltage at node A if the voltage at node A is less than reference voltage V REF     —     A , and decreases the voltage at node A if the voltage at node A is greater than reference voltage V REF     —     A . 
     In step S 1010 , the process determines whether the PSC is powered off. If the PSC is not powered off, then the process returns to step S 1002 . Otherwise, the process ends. 
       FIG. 5  shows a flow-chart  2000  of an exemplary PSC process for regulating voltage at more than one node. The exemplary PSC process can be implemented in a circuit where dynamic current usage of one or more components needs to be isolated from another component, such as the PSC circuit shown in  FIG. 3 . 
     The process begins and proceeds to steps S 2002 , S 2010 , and S 2018 . In step S 2002  a determination is made as to whether voltage V A  is equal to reference voltage V REF     —     A . If voltage V A  is determined to not be equal to reference voltage V REF     —     A , then the process proceeds to step S 2004 . Otherwise, the process proceeds to step S 2026 . 
     In step S 2004 , a determination is made as to whether voltage V A  is greater than reference voltage V REF     —     A . If voltage V A  is determined to be greater than reference voltage V REF     —     A , then the process proceeds to step S 2006 . Otherwise, the process proceeds to step S 2008 . 
     In step S 2008 , the process raises voltage V A  and returns to step S 2002 . In step S 2006 , the process lowers voltage V A  and returns to step S 2002 . For example, in PSC  300 , regulator  350  increases the voltage at node A if the voltage at node A is less than reference voltage V REF     —     A , and decreases the voltage at node A if the voltage at node A is greater than reference voltage V REF     —     A . 
     In step S 2010  a determination is made as to whether voltage V B  is equal to reference voltage V REF     —     B . If voltage V B  is determined to not be equal to reference voltage V REF     —     B , then the process proceeds to step S 2012 . Otherwise, the process proceeds to step S 2026 . 
     In step S 2012 , a determination is made as to whether voltage V B  is greater than reference voltage V REF     —     B . If voltage V B  is determined to be greater than reference voltage V REF     —     B , then the process proceeds to step S 2014 . Otherwise, the process proceeds to step S 2016 . 
     In step S 2016 , the process raises voltage V B  and returns to step S 2010 . In step S 2014 , the process lowers voltage V B  and returns to step S 2010 . For example, in PSC  300 , regulator  350  increases the voltage at node B if the voltage at node B is less than reference voltage V REF     —     B , and decreases the voltage at node B if the voltage at node B is greater than reference voltage V REF     —     B . 
     In step S 2018  a determination is made as to whether voltage V C  is equal to reference voltage V REF     —     C . If voltage V C  is determined to not be equal to reference voltage V REF     —     C , then the process proceeds to step S 2020 . Otherwise, the process proceeds to step S 2026 . 
     In step S 2020 , a determination is made as to whether voltage V C  is greater than reference voltage V REF     —     C . If voltage V C  is determined to be greater than reference voltage V REF     —     C , then the process proceeds to step S 2022 . Otherwise, the process proceeds to step S 2024 . 
     In step S 2024 , the process raises voltage V C  and returns to step S 2018 . In step S 2022 , the process lowers voltage V C  and returns to step S 2018 . For example, in PSC  300 , regulator  350  increases the voltage at node C if the voltage at node C is less than reference voltage V REF     —     C , and decreases the voltage at node C if the voltage at node C is greater than reference voltage V REF     —     C . 
     In step S 2026 , the process determines whether the PSC is powered off. If the PSC is not powered off, then the process returns to steps S 2002 , S 2010 , and S 2018 . Otherwise, the process ends. 
     It should be understood that additional steps can be added where a determination is made as to whether a voltage at one or more additional nodes is equal to its respective reference voltage and is adjusted in a manner similar to that described above in steps S 2002  through S 2026 . 
     Voltages V A , V B , and V C  can be regulated either independently, simultaneously, or sequentially in a temporally overlapping or non-overlapping manner. For example, in PSC  300 , when first circuit  110  requires more current, the voltage at node B will be adjusted first. However, after amplifier AMP B  begins adjusting the voltage at node B, amplifier AMP C  may start adjust the voltage at node C prior to when amplifier AMP A  begins to sink third current I 3  from node A to adjust the voltage at node A. 
     For purposes of explanation, in the above description, numerous specific details are set forth in order to provide a thorough understanding of the PSC. It will be apparent, however, to one skilled in the art that the PSC can be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form in order to avoid obscuring the PSC. 
     While the PSC has been described in conjunction with the specific embodiments thereof, it is evident that many alternatives, modifications, and variations will be apparent to those skilled in the art. Accordingly, embodiments of the PSC as set forth herein are intended to be illustrative, not limiting. There are changes that may be made without departing from the spirit and scope of the invention.