Patent Publication Number: US-2022240373-A1

Title: Inhomogeneous dielectric medium high-speed stripline trace system

Description:
BACKGROUND 
     The present disclosure relates generally to information handling systems, and more particularly to providing high-speed stripline traces in an inhomogeneous medium in an information handling system. 
     As the value and use of information continues to increase, individuals and businesses seek additional ways to process and store information. One option available to users is information handling systems. An information handling system generally processes, compiles, stores, and/or communicates information or data for business, personal, or other purposes thereby allowing users to take advantage of the value of the information. Because technology and information handling needs and requirements vary between different users or applications, information handling systems may also vary regarding what information is handled, how the information is handled, how much information is processed, stored, or communicated, and how quickly and efficiently the information may be processed, stored, or communicated. The variations in information handling systems allow for information handling systems to be general or configured for a specific user or specific use such as financial transaction processing, airline reservations, enterprise data storage, or global communications. In addition, information handling systems may include a variety of hardware and software components that may be configured to process, store, and communicate information and may include one or more computer systems, data storage systems, and networking systems. 
     Information handling systems such as, for example, server devices, storage devices, networking device, desktop computing devices, laptop/notebook computing devices, tablet computing devices, mobile phones, and/or other computing devices known in the art, often include multi-layer printed circuit boards. Such circuit boards often utilize stripline traces, which are data signal transmission line traces suspended in a dielectric medium between two ground layers. For example, a plurality of differential trace pairs may be provided in the circuit board, with each differential trace pair including a pair of stripline traces, in order to allow data signals to be transmitted between components in the computing device using the differential trace pairs. In many embodiments, the dielectric medium in which the different trace pairs are suspended may be provided by a core dielectric layer and a prepreg dielectric layer. For example, the manufacture of the circuit board may include providing a first Copper Clad Layer (CCL) that includes a core dielectric layer sandwiched between a first copper layer and a second copper layer. That first CCL may then have its second copper layer etched to provide differential trace pairs. A second CCL may then be provided that includes a third copper layer (as well as a fourth copper layer/core dielectric layer configured similarly to the first CCL in some examples), and the third copper layer may be adhered to the first CCL (that was etched with the differential trace pairs) using a prepreg dielectric material that provides a prepreg dielectric layer in the circuit board. As such, the circuit board will include the first copper layer and the third copper layer as ground layers, with the differential trace pairs suspended in the dielectric medium provided by the core dielectric layer and the prepreg dielectric layer. 
     For relatively lower signal transmission frequencies (e.g., 20 GHz and below), the dielectric medium in which the differential trace pairs are suspended may be treated as homogeneous around the traces/differential trace pair. However, that dielectric medium is most often not actually homogeneous due to the dielectric constants of the core dielectric layer and the prepreg dielectric layer differing as a result of, for example, the use of different resins in the core dielectric layer and the prepreg dielectric layer, the use of different glass percentages in the core dielectric layer and the prepreg dielectric layer, and/or other core/prepreg dielectric layer differences that are difficult in practice to match/balance in order to provide a homogenous dielectric medium. As signal transmission speeds increase, the inhomogeneous dielectric medium may cause issues in the circuit board. 
     For example, the principle operating mode of a stripline trace is transverse electromagnetic (TEM) when the dielectric medium is homogeneous, but becomes quasi-TEM when the dielectric medium is inhomogeneous (e.g., due to the core/prepreg dielectric layer differences discussed above). Furthermore, a quasi-TEM mode can operate to create a potential difference in the ground layers that can produce a parallel plate mode resonance in the ground layers that is a parasitic mode for stripline traces that can effect the signals transmitted thereon, and that parallel plate mode will be more easily produced in the ground layers at portions of stripline traces that have bends or transitions to other layers. The effects of this parasitic parallel plate mode on signals transmitted via stripline traces can be observed in the multiple-tens-of-gigahertz frequency ranges, and results in higher order modes that can cause a divergence of differential-mode and common-mode insertion losses in the circuit board. As such, high-speed stripline traces in an inhomogeneous medium can cause crosstalk noise and signal integrity issues in the circuit board. Conventional solutions to such issues rely on enforcing the balancing/matching of core dielectric layer and prepreg dielectric layer properties, which is particularly difficult when the thicknesses of the core dielectric layer and the prepreg dielectric layer diverge, and requires multiple laminates and circuit board housings to be qualified for the products that will utilize them. 
     Accordingly, it would be desirable to provide an inhomogeneous dielectric medium high-speed signal trace system that addresses the issues discussed above. 
     SUMMARY 
     According to one embodiment, an Information Handling System (IHS) includes a chassis; a processing system that is housed in the chassis; and a board that is housed in the chassis and that supports the processing system, wherein the board includes: a first ground layer; a second ground layer; a first dielectric layer that has a first dielectric constant and that is located adjacent the first ground layer; a second dielectric layer that has a second dielectric constant that is different than the first dielectric constant and that is located between the first dielectric layer and the second ground layer; a first differential trace pair that is located between the first dielectric layer and the second dielectric layer and that is coupled to the processing system; a plurality of first vias that extend between the first ground layer and the second ground layer and that are spaced part from each other and the first differential trace pair; and a plurality of second vias that extend between the first ground layer and the second ground layer, that are spaced part from each other and the first differential trace pair, and that are located opposite the first differential trace pair from the plurality of first vias. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a schematic view illustrating an embodiment of an Information Handling System (IHS). 
         FIG. 2A  is a schematic view illustrating an embodiment of a circuit board. 
         FIG. 2B  is a cross-sectional schematic view illustrating an embodiment of the circuit board of  FIG. 2A . 
         FIG. 3  is a schematic view illustrating an embodiment of the operation of the circuit board of  FIGS. 2A and 2B  provided with a conventional configuration. 
         FIG. 4A  is a schematic view illustrating an embodiment of the operation of the circuit board of  FIGS. 2A and 2B  provided with a conventional configuration. 
         FIG. 4B  is a graph view illustrating an embodiment of the operation of the circuit board of  FIGS. 2A and 2B  provided with a conventional configuration. 
         FIG. 4C  is a graph view illustrating an embodiment of the operation of the circuit board of  FIGS. 2A and 2B  provided with a conventional configuration. 
         FIG. 4D  is a graph view illustrating an embodiment of the operation of the circuit board of  FIGS. 2A and 2B  provided with a conventional configuration. 
         FIG. 5  is a flow chart illustrating an embodiment of a method for providing high speed signals via stripline traces in an inhomogeneous dielectric medium. 
         FIG. 6A  is a schematic view illustrating an embodiment of the circuit board of  FIGS. 2A and 2B  provided with the inhomogeneous dielectric medium high-speed signal trace system of the present disclosure. 
         FIG. 6B  is a cross-sectional schematic view illustrating an embodiment of the circuit board of  FIG. 6A . 
         FIG. 7A  is a schematic view illustrating an embodiment of the operation of the circuit board of  FIGS. 6A and 6B . 
         FIG. 7B  is a graph view illustrating an embodiment of the operation of the circuit board of  FIGS. 6A and 6B . 
         FIG. 7C  is a graph view illustrating an embodiment of the operation of the circuit board of  FIGS. 6A and 6B . 
         FIG. 7D  is a graph view illustrating an embodiment of the operation of the circuit board of  FIGS. 6A and 6B . 
     
    
    
     DETAILED DESCRIPTION 
     For purposes of this disclosure, an information handling system may include any instrumentality or aggregate of instrumentalities operable to compute, calculate, determine, classify, process, transmit, receive, retrieve, originate, switch, store, display, communicate, manifest, detect, record, reproduce, handle, or utilize any form of information, intelligence, or data for business, scientific, control, or other purposes. For example, an information handling system may be a personal computer (e.g., desktop or laptop), tablet computer, mobile device (e.g., personal digital assistant (PDA) or smart phone), server (e.g., blade server or rack server), a network storage device, or any other suitable device and may vary in size, shape, performance, functionality, and price. The information handling system may include random access memory (RAM), one or more processing resources such as a central processing unit (CPU) or hardware or software control logic, ROM, and/or other types of nonvolatile memory. Additional components of the information handling system may include one or more disk drives, one or more network ports for communicating with external devices as well as various input and output (I/O) devices, such as a keyboard, a mouse, touchscreen and/or a video display. The information handling system may also include one or more buses operable to transmit communications between the various hardware components. 
     In one embodiment, IHS  100 ,  FIG. 1 , includes a processor  102 , which is connected to a bus  104 . Bus  104  serves as a connection between processor  102  and other components of IHS  100 . An input device  106  is coupled to processor  102  to provide input to processor  102 . Examples of input devices may include keyboards, touchscreens, pointing devices such as mouses, trackballs, and trackpads, and/or a variety of other input devices known in the art. Programs and data are stored on a mass storage device  108 , which is coupled to processor  102 . Examples of mass storage devices may include hard discs, optical disks, magneto-optical discs, solid-state storage devices, and/or a variety of other mass storage devices known in the art. IHS  100  further includes a display  110 , which is coupled to processor  102  by a video controller  112 . A system memory  114  is coupled to processor  102  to provide the processor with fast storage to facilitate execution of computer programs by processor  102 . Examples of system memory may include random access memory (RAM) devices such as dynamic RAM (DRAM), synchronous DRAM (SDRAM), solid state memory devices, and/or a variety of other memory devices known in the art. In an embodiment, a chassis  116  houses some or all of the components of IHS  100 . It should be understood that other buses and intermediate circuits can be deployed between the components described above and processor  102  to facilitate interconnection between the components and the processor  102 . 
     Referring now to  FIGS. 2A and 2B , an embodiment of a circuit board  200  is illustrated that is described in some embodiments below as being provided with a convention configuration for purposes of discussing the deficiencies in such conventional configurations, as well as being configured with the inhomogeneous dielectric medium high-speed signal trace system in other embodiments. One of skill in the art in possession of the present disclosure will appreciate that the embodiment of the circuit board  200  illustrated in  FIG. 2B  is a cross-sectional view of the embodiment of the circuit board  200  illustrated in  FIG. 2A  taken along like  2 B. In the illustrated embodiment, the circuit board  200  includes a pair of ground layers  202  and  204 , a dielectric medium between the ground layers  202  and  204  that is provided by a core dielectric layer  206  that engages the ground layer  202  and a prepreg dielectric layer  208  that engages the core dielectric layer  206  and the ground layer  204 , and differential trace pairs that are suspended in the dielectric medium between the ground layers  202  and  204  and that are provided in the illustrated embodiment by a differential trace pair  210  with traces  210   a  and  210   b , and a differential trace pair  212  with traces  212   a  and  212   b . While not explicitly illustrated herein, one of skill in the art in possession of the present disclosure will recognize how a processing system (e.g., the processor  102  discussed above with reference to  FIG. 1 ), a memory system (e.g., the system memory  114  discussed above with reference to  FIG. 1 ), and/or other components may be mounted to and/or otherwise coupled to the circuit board, and communicatively connected together by the differential trace pairs  210  and  212  (e.g., the processing system may be coupled to the memory system or other components via one or more differential trace pairs). 
     For example, the manufacture of the circuit board  200  may include providing a first Copper Clad Layer (CCL) that includes a core dielectric layer sandwiched between a first copper layer and a second copper layer. That first CCL may then have its second copper layer etched to provide the differential trace pairs  210  and  212 . A second CCL may then be provided that includes a third copper layer (as well as a fourth copper layer and core dielectric layer similar to the first CCL in some examples), and the third copper layer may be adhered to the first CCL (that was etched with the differential trace pairs  210  and  212 ) using a prepreg dielectric material that provides the prepreg dielectric layer  208 . As such, the circuit board  200  will include the first copper layer and the third copper layer as ground layers  202  and  204 , respectively, with the differential trace pairs  210  and  212  suspended in the dielectric medium provided by the core dielectric layer  206  and the prepreg dielectric layer  208 . However, while a specific portion of a circuit board  200  has been illustrated and described, one of skill in the art in possession of the present disclosure will recognize that circuit boards provided with a conventional configuration and/or with the inhomogeneous dielectric medium high-speed signal trace system of the present disclosure may include a variety of components and component configurations (e.g., additional layers, etc.) while remaining within the scope of the present disclosure as well. 
     Referring now to  FIG. 3 , an embodiment of the operation of the circuit board  200  when it is provided with a conventional configuration is illustrated. In the embodiment illustrated in  FIG. 3 , the dielectric medium provided by the core dielectric layer  206  and the prepreg dielectric layer  208  may be treated as homogeneous due to, for example, the balancing/matching of core dielectric layer/prepreg dielectric layer constituents (e.g., resins, glass percentages, etc.) and/or the transmission of relatively lower frequency signals (e.g., under 20 GHz in the examples below). As illustrated in  FIG. 3 , the transmission of data signals using the differential trace pair  210  (when the dielectric medium provided by the core dielectric layer  206  and the prepreg dielectric layer  208  may be treated as homogeneous) produces magnetic field(s)  300  around the traces  210   a  and  210   b  that are relatively contained in that the strength of those magnetic field(s) reduces below a magnetic field strength threshold at a distance from the traces  210   a  and  210   b  (illustrated by a dashed line in  FIG. 3 ) that does not reach the neighboring differential trace pair  212 . As discussed above, the principle operating mode of a stripline trace is transverse electromagnetic (TEM) when the dielectric medium is homogeneous and, as such, the parallel plate mode of the ground layers  202  and  204  would be orthogonal to the TEM mode and thus not excited by that TEM mode, thus providing for the relatively “contained” magnetic field(s)  300 . 
     However, as also discussed above, the dielectric medium provided by the core dielectric layer  206  and the prepreg dielectric layer  208  may be treated as inhomogeneous due to, for example, the inability to balance/match the core dielectric layer/prepreg dielectric layer constituents (e.g., resins, glass percentages, etc.) and/or the transmission of relatively higher frequency signals (e.g., above 20 GHz in the examples below). With reference to  FIG. 4A , the transmission of data signals using the differential trace pair  210  (when the dielectric medium provided by the core dielectric layer  206  and the prepreg dielectric layer  208  is treated as inhomogeneous) produces magnetic field(s)  400  around the traces  210   a  and  210   b  that are relatively uncontained and that experience “spreading” in that the strength of those magnetic field(s) is above a magnetic field strength threshold at a distance from the traces  210   a  and  210   b  (illustrated by a dashed line in  FIG. 3 ) that reaches the neighboring differential trace pair  212  (e.g., the trace  212   a  in  FIG. 4A ). 
     As discussed above, the principle operating mode of a stripline trace is quasi-TEM when the dielectric medium is inhomogeneous (e.g., due to the core/prepreg dielectric layer differences discussed above), and the quasi-TEM mode can operate to create a potential difference in the ground layers that can produce the parallel plate mode resonance discussed above that is a parasitic mode for stripline traces. For example, electric fields in the core dielectric layer  206  and the prepreg dielectric layer  208  (e.g., that provide the inhomogeneous dielectric medium) will have different wave speeds, and as waves propagate in their propagation direction, the phase difference between the electric fields in the core dielectric layer  206  and the prepreg dielectric layer  208  will increase. As will be appreciated by one of skill in the art in possession of the present disclosure, that increasing electric field phase difference may operate to excite the parallel plate mode in the ground layers  202  and  204  that may then impact signals transmitted by the differential trace pairs  210  and/or  212 . 
     As illustrated in  FIG. 4B , the effects of the parasitic parallel plate mode on signals transmitted via stripline traces can be observed in the multiple-tens-of-gigahertz frequency ranges, and results in higher order modes that can cause a divergence of differential-mode insertion losses  400  and common-mode insertion losses  402  in the circuit board (e.g., a divergence which begins at approximately 8 GHz and becomes relatively significant at approximately 20 GHz and above in  FIG. 4B ). As such, a stripline trace in an inhomogeneous medium that transmits a relatively high-speed signal (e.g., the trace  210   b  in the circuit board  200  in the example of  FIG. 4A ) can product a magnetic field that can cause crosstalk noise and other signal integrity issues in the circuit board (e.g., in the trace  212   a  in the circuit board  200  in the example of  FIG. 4A ).  FIG. 4C  illustrates the magnetic field(s) produced by the differential trace pair  210  in  FIG. 4A  (with the differential trace pair  210  modeled as running from right to left in  FIG. 4C ), with a portion  404   a  of the magnetic field(s) centered around the differential trace pair  210 , and portions  404   b  of the magnetic field(s) uncontained and experiencing “spreading” on either side of the differential trace pair  210  (e.g., with a magnetic field strength that exceeds a magnetic field strength threshold).  FIG. 4D  illustrates an eye diagram  406  for the trace  212   a  in  FIG. 4A  with an eye  406   a  that, as discussed below, is relatively degraded due to the crosstalk noise and/or other signal integrity issues produced by the magnetic field(s)  400  provided by the differential trace pair  210 . As such, one of skill in the art in possession of the present disclosure will appreciate that the provisioning of differential trace pairs in a inhomogeneous dielectric medium between a pair of ground layers can excite a parallel plate mode in those ground layers when transmitting relatively high speed signals, and that parallel plate mode can propagate through the ground layers and couple to the traces in the differential trace pairs, causing cross talk noise and/or other signal integrity issues known in the art. 
     Referring now to  FIG. 5 , an embodiment of a method  500  for providing high speed signals via stripline traces in an inhomogeneous dielectric medium is illustrated. As discussed below, the systems and methods of the present disclosure provide differential trace pairs in an inhomogeneous dielectric medium between ground layers with vias that extend between those ground layers on each side of the differential trace pair in order to reduce parallel plate mode conversions by those ground layers when relatively high-speed signals are transmitted by those differential trace pairs. For example, the inhomogeneous dielectric medium high-speed signal trace system of the present disclosure may include first and second ground layers, a first dielectric layer that has a first dielectric constant and that is located adjacent the first ground layer, and a second dielectric layer that has a second dielectric constant that is different than the first dielectric constant and that is located between the first dielectric layer and the second ground layer. A first differential trace pair is located between the first and second dielectric layer. A plurality of first vias extend between the first ground layer and the second ground layer and are spaced part from each other and the first differential trace pair, and a plurality of second vias extend between the first ground layer and the second ground layer, are spaced part from each other and the first differential trace pair, and are located opposite the first differential trace pair from the plurality of first vias. The plurality of first and second vias prevent the magnetic field produced in response to the transmission of signals by the first differential trace pair from having the magnetic field strength that is greater than the magnetic field strength threshold at a second differential trace pair that is located adjacent the first differential trace pair. As discussed below, the inhomogeneous dielectric medium high-speed signal trace system of the present disclosure only allows the magnetic field(s) to couple between the traces in the differential trace pair producing them, thus minimizing parallel plate mode conversions by the ground layers, reducing crosstalk with neighboring differential trace pairs, reducing electromagnetic interference (EMI) radiation by the circuit board, and providing other benefits that would be apparent to one of skill in the art in possession of the present disclosure. 
     The method  500  begins at block  502  where a circuit board is provided with the inhomogeneous dielectric medium high-speed signal trace system of the present disclosure. In an embodiment of block  502 , the circuit board  200  may be provided with the inhomogeneous dielectric medium high-speed signal trace system of the present disclosure by providing vias that extend between the ground layers and on each side of the differential trace pairs in the circuit board  200 . For example, with reference to  FIGS. 6A and 6B , a plurality of vias  600  may be provided in the circuit board  200  such that they extend through the core dielectric layer  206  and the prepreg dielectric layer  208  and between the ground layers  202  and  204  on a first side of the differential trace pair  210  that is opposite the trace  210   a  from the trace  210   b , and a plurality of vias  602  may be provided in the circuit board  200  such that they extend through the core dielectric layer  206  and the prepreg dielectric layer  208  and between the ground layers  202  and  204  on a second side of the differential trace pair  210  that is opposite the trace  210   b  from the trace  210   a . For example, the plurality of vias  600  and  602  may be provided by a copper material or other conductive materials known in the art. 
     In a specific example, the plurality of vias  600  may be spaced between 5-50 mils from the trace  210   a  in the differential trace pair  210  and spaced between 50-250 mils from each other, and the plurality of vias  602  may be spaced between 5-50 mils from the trace  210   b  in the differential trace pair  210  and spaced between 50-250 mils from each other. However, while the plurality of vias  600  and  602  are illustrated and described with specific, substantially equal spacing between them and the differential trace pair  210 , one of skill in the art in possession of the present disclosure will recognize that unequal spacing of the vias  600  and  602  and/or different spacing distances will fall within the scope of the present disclosure as well. Furthermore, while vias  600  and  602  are illustrated and described as being provided on opposite sides of the differential trace pair  210  at block  502  above, one of skill in the art in possession of the present disclosure will appreciate that similar vias may be provided on opposite sides of the differential trace pair  212  (as well as on opposite sides of other differential trace pairs) in a similar manner while remaining within the scope of the present disclosure as well. 
     The method  500  then proceeds to block  504  where signals are received at the circuit board. In an embodiment, at block  504 , data signals may be received at the circuit board  200  via, for example, components mounted to and/or otherwise coupled to the circuit board  200  (e.g., the processing system, memory system, or other components discussed above). In specific examples, the data signals received by the circuit board  200  at block  504  may be generated and transmitted at relatively high frequencies (e.g., 20 GHz and above), and provided to traces in a differential trace pair (e.g., the traces  210   a  and  210   b  in the differential trace pair  210  in the example below) that is coupled to the component that generated and provided those data signals to the circuit board  200 . 
     The method  500  then proceeds to block  506  where the signals are transmitted via trace(s) in the circuit board. In an embodiment, at block  506 , the traces  210   a  and  210   b  in the differential trace pair  210  may operate to transmit the data signals received by the circuit board  200  at block  504  at the relatively high frequencies (e.g., 20 GHz and above) at which they were received. As will be appreciated by one of skill in the art in possession of the present disclosure, the data signals transmitted by the traces  210   a  and  210   b  in the differential trace pair  210  at block  506  may include complementary data signals transmitted as a differential pair of signals (e.g., with a respective one of each of the complementary data signals transmitted on each trace  210   a  and  210   b ). 
     The method  500  then proceeds to block  508  where vias on opposite sides of the trace(s) prevent magnetic field(s) produced by the trace(s) from having a magnetic field strength that is greater than a magnetic field strength threshold. With reference to  FIG. 7A , in an embodiment of block  508  and in response to the transmission of the data signals by the traces  210   a  and  210   b  in the differential trace pair  210  at block  506 , magnetic field(s)  700  will be produced by the traces  210   a  and  210   b  in the differential trace pair  210 . However, as can be seen in  FIG. 7A , the plurality of vias  600  and  602  on opposite sides of the differential trace pair  210  provide a “via cage” that contain the magnetic field(s)  700  such that the strength of those magnetic field(s)  700  reduces below a magnetic field strength threshold at the vias  600  and  602 . As such, the positioning of the plurality of vias  602  between the trace  210   b  in the differential trace pair  210  and the trace  212   a  in the differential trace pair  212  operates to prevent the magnetic field(s)  700  from reaching the trace  212   a  in the neighboring differential trace pair  212  (e.g., from having a magnetic field strength above the magnetic field strength threshold at the trace  212   a ). For example, the spacing between the differential trace pairs  210  and  212  may follow high-speed design rules that provide a spacing of approximately 20-40 miles, although one of skill in the art in possession of the present disclosure will recognize how the system of the present disclosure may be configured to provide the benefits discussed above for differential trace pairs with different spacings while remaining within the scope of the present disclosure. As such, the magnetic field(s)  700  produced by the differential trace pair  210  are substantially prevented from reaching the neighboring trace  212   a , minimizing parallel plate mode conversions and reducing parallel plate mode effects due to the “stitching” of the ground layers  202   a  and  204  with the vias  600  and  602  in order to confine those magnetic field(s)  700 . 
     As illustrated in  FIG. 7B , the plurality of vias  600  and  602  on opposite sides of the differential trace pair  210  prevent mode conversions and corresponding higher order modes that would otherwise cause a divergence of differential-mode insertion losses  700  and common-mode insertion losses  702  in the circuit board (e.g., as occurs with the differential-mode insertion losses  400  and common-mode insertion losses  402  as discussed above with reference to  FIG. 4B ). Furthermore,  FIG. 7C  illustrates the magnetic field(s) produced by the differential trace pair  210  in  FIG. 7A  (with the differential trace pair  210  modeled as running from right to left in  FIG. 7C ), with a portion  702  of the magnetic field(s) centered around the differential trace pair  210  similarly as in  FIG. 4C , and with portions  704   b  of the magnetic field(s) contained and prevented from “spreading” on either side of the differential trace pair  210  (e.g., with a magnetic field strength that exceeds a magnetic field strength threshold) by the vias  600  and  602  (i.e., as occurs with the portions  404   b  of the magnetic fields discussed above with regard to  FIG. 4C ). Further still,  FIG. 7D  illustrates an eye diagram  706  for the trace  212   a  in  FIG. 7A  with an eye  706   a  that one of skill in the art in possession of the present disclosure will recognize shows a clear improvement from the eye  406   a  in the eye diagram  406  discussed above with reference to  FIG. 4D . As such, one of skill in the art in possession of the present disclosure will appreciate that the configuration of the vias on opposite sides of a differential trace pair in a inhomogeneous dielectric medium between a pair of ground layers according to the teachings of the present disclosure can reduce or prevent the excitement of a parallel plate mode in those ground layers when transmitting relatively high speed signals, in turn reducing cross talk noise in neighboring traces and/or other signal integrity issues known in the art. 
     Thus, systems and methods have been described that provide for the configuration of differential trace pairs in an inhomogeneous dielectric medium between ground layers with vias that extend between those ground layers on each side of the differential trace pairs in order to reduce parallel plate mode conversions by those ground layers when relatively high-speed signals are transmitted by those differential trace pairs. For example, the inhomogeneous dielectric medium high-speed signal trace system of the present disclosure may include first and second ground layers, a first dielectric layer that has a first dielectric constant and that is located adjacent the first ground layer, and a second dielectric layer that has a second dielectric constant that is different than the first dielectric constant and that is located between the first dielectric layer and the second ground layer. A first differential trace pair is located between the first and second dielectric layer. A plurality of first vias extend between the first ground layer and the second ground layer and are spaced part from each other and the first differential trace pair, and a plurality of second vias extend between the first ground layer and the second ground layer, are spaced part from each other and the first differential trace pair, and are located opposite the first differential trace pair from the plurality of first vias. The plurality of first and second vias prevent the magnetic field produced in response to the transmission of the signals by the first differential trace pair from having the magnetic field strength that is greater than the magnetic field strength threshold at a second differential trace pair that is located adjacent the first differential trace pair. As such, the inhomogeneous dielectric medium high-speed signal trace system of the present disclosure improves high-speed signal performance even in the presence of an inhomogeneous dielectric medium, provides a cost-effective solution to dampen parallel plate mode between ground layers and ensure relatively higher signal quality, reduces crosstalk with neighboring traces, reduces mode conversion that could otherwise result in radiation and other negative side effects, and result in relatively lower insertion losses even in the presence of skew (the impact of which can aggravate parallel plate mode in the ground layers). 
     Although illustrative embodiments have been shown and described, a wide range of modification, change and substitution is contemplated in the foregoing disclosure and in some instances, some features of the embodiments may be employed without a corresponding use of other features. Accordingly, it is appropriate that the appended claims be construed broadly and in a manner consistent with the scope of the embodiments disclosed herein.