Patent Publication Number: US-9903764-B2

Title: Integrated circuit for estimating power of at least one node using temperature and a system including the same

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application claims priority under 35 U.S.C. §119 to U.S. provisional patent application No. 62/057,422, filed Sep. 30, 2014 and U.S. provisional patent application No. 62/060,093, filed Oct. 6, 2014, the disclosures of which are incorporated by reference herein in their entireties. 
    
    
     TECHNICAL FIELD 
     Exemplary embodiments of the inventive concept relate to an integrated circuit, and more particularly, to an integrated circuit for estimating a power of at least one node using a temperature of the node and a system including the same. 
     DISCUSSION OF RELATED ART 
     A system on chip (SoC) is an integrated circuit that integrates components of a computer or other electronic systems into a single chip. The SoC includes a plurality of elements that require power to operate and generate heat. 
     The temperature of the elements during a given time depends on power consumed during the given time. In addition, heat generated by one of the elements may be transferred to at least one other nearby element. 
     In general, power consumption of an element included in a SoC is measured first and then a temperature of the element is estimated using the measured power consumption. However, there are elements included in the SoC whose power consumption is not directly measured. Therefore, power consumption measured for the SoC may be inaccurate. 
     SUMMARY 
     Exemplary embodiments of the inventive concept provide an integrated circuit for estimating power consumption of at least one node using a temperature measured at (or estimated for) the node and a system including the same. 
     An exemplary embodiment of the inventive concept provides a power estimation circuit comprising: a power estimation manager circuit configured to receive power data and temperature data; and a storage circuit that includes a first region storing resistive-capacitive (RC) thermal modeling data, a second region storing the power data and a third region storing the temperature data, wherein the power estimation manager circuit is configured to estimate power consumption of a first node at a second time point, which occurs after a first time point, using the RC thermal modeling data, the power data and the temperature data. 
     The RC thermal modeling data includes RC thermal modeling data between the first node and each of a plurality of second nodes, the power data includes power data of the second nodes at the first and second time points and estimated power consumption of the first node at the first time point, and the temperature data includes temperature data for the first node at the first time point and temperature data for the first node at the second time point. 
     The power estimation manager circuit is configured to correct the power data of at least one of the second nodes by using the estimated power consumption of the first node at the second time point. 
     The storage circuit includes a buffer, a register, a flip-flop or a random access memory. 
     The first and second nodes include a system component, a function block which is included in a system component, a function component which is included in a function block, or a circuit element which is included in a function component. 
     An exemplary embodiment of the inventive concept provides an application processor comprising: a plurality of nodes; a plurality of temperature sensors; a power estimation circuit including: a power estimation manager circuit configured to receive power data and temperature data for the nodes; and a storage circuit that includes a first region storing RC thermal modeling data for the nodes, a second region storing the power data and a third region storing the temperature data, wherein the power estimation manager circuit is configured to estimate power consumption of a first node at a second time point, which occurs after a first time point, using the RC thermal modeling data, the power data and the temperature data, wherein the application processor further comprises: a power management unit configured to provide the power data to the power estimation circuit; and a power monitoring unit configured to monitor traffic flow between the first node and a bus and a plurality of second nodes and the bus. 
     The RC thermal modeling data includes RC thermal modeling data between the first node and each of the plurality of second nodes, the power data includes power data of the second nodes at the first and second time points and estimated power consumption of the first node at the first time point, and the temperature data includes temperature data for the first node at the first time point and temperature data for the first node at the second time point. 
     At least one of the temperature sensors is used to measure temperatures of the first node at the first and second time points. 
     The power estimation manager circuit is configured to correct the power data of at least one of the second nodes by using the estimated power consumption of the first node at the second time point. 
     At least one of the temperature sensors is used to measure temperatures of the first node at different time points. 
     The storage circuit includes a buffer, a register, a flip-flop or a random access memory. 
     The first and second nodes include a system component, a function block which is included in a system component, a function component which is included in a function block, or a circuit element which is included in a function component. 
     The estimated power consumption of the first node at the second time point is provided to the power management unit from the power estimation circuit. 
     The power data is provided to the power estimation circuit from the power monitoring unit. 
     An exemplary embodiment of the inventive concept provides a mobile system comprising: an application processor including a plurality of nodes and a power estimation circuit, the power estimation circuit including: a power estimation manager circuit configured to receive power data and temperature data for the nodes; and a storage circuit that includes a first region storing RC thermal modeling data for the nodes, a second region storing the power data and a third region storing the temperature data, wherein the power estimation manager circuit is configured to estimate power consumption of a first node at a second time point, which occurs after a first time point, using the RC thermal modeling data, the power data and the temperature data. 
     The RC thermal modeling data includes RC thermal modeling data between the first node and each of a plurality of second nodes, the power data includes power data of the second nodes at the first and second time points and estimated power consumption of the first node at the first time point, and the temperature data includes temperature data for the first node at the first time point and temperature data for the first node at the second time point. 
     The power estimation manager circuit is configured to correct the power data of at least one of the second nodes by using the estimated power consumption of the first node at the second time point. 
     The mobile system further comprises: a display and a memory connected to the application processor. 
     The mobile system further comprises: a power management integrated circuit configured to provide the power data to the power estimation manager circuit. 
     The estimated power consumption of the first node at the second time point is used to determine overall power consumption of the application processor. 
     The overall power consumption of the application processor is used to determine overall power consumption of the mobile system. 
     Skin temperature of the mobile system is estimated based on the overall power consumption of the mobile system. 
     An exemplary embodiment of the inventive concept provides a method of estimating power consumption in an integrated circuit comprising: receiving temperature data for a first node at a second time point which occurs after a first time point; estimating power consumption of the first node at the second time point by using the temperature data for the first node at the second time point, temperature data for the first node at the first time point, RC thermal modeling data between the first node and each of a plurality of second nodes, power data of the second nodes at the first and second time points, and estimated power consumption of the first node at the first time point; and storing the estimated power consumption of the first node at the second time point. 
     The method further comprises: correcting the power data of at least one of the second nodes by using the estimated power consumption of the first node at the second time point. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The above and other features of the inventive concept will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings in which: 
         FIG. 1  is a block diagram of a computing system according to an exemplary embodiment of the inventive concept; 
         FIG. 2  is a block diagram of a power estimation circuit illustrated in  FIG. 1 , according to an exemplary embodiment of the inventive concept; 
         FIG. 3  is a diagram for explaining resistive-capacitive (RC) thermal modeling, according to an exemplary embodiment of the inventive concept; 
         FIG. 4A  shows an equation for explaining a method of estimating a power consumption of a first node using the power estimation circuit illustrated in  FIG. 2 , according to an exemplary embodiment of the inventive concept; 
         FIGS. 4B and 4C  show equations for explaining a method of compensating power data of second nodes using the power estimation circuit illustrated in  FIG. 2 , according to an exemplary embodiment of the inventive concept; 
         FIG. 5  is a flowchart of the method of compensating power data of a second node using the power estimation circuit illustrated in  FIG. 2 , according to an exemplary embodiment of the inventive concept; 
         FIG. 6  is a block diagram of a computing system according to an exemplary embodiment of the inventive concept; 
         FIG. 7  is a block diagram of a computing system according to an exemplary embodiment of the inventive concept; 
         FIG. 8  is a block diagram of a computing system according to an exemplary embodiment of the inventive concept; and 
         FIG. 9  is a flowchart of an operation of the computing system illustrated in  FIG. 1, 6, 7 , or  8  according to an exemplary embodiment of the inventive concept. 
     
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
     The inventive concept now will be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments thereof are shown. This inventive concept may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like numbers may refer to like elements throughout the specification and drawings. 
     It will be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. 
     As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. 
     In an exemplary embodiment of the inventive concept, a node may be a heat source that generates heat according to power supplied to the node or a heat sink that absorbs or dissipates heat. In an exemplary embodiment of the inventive concept, power may be calculated (e.g., estimated or measured) based on an operating voltage or an operating current. 
     In an exemplary embodiment of the inventive concept, a node may be a system component, e.g., a power management integrated circuit (PMIC), a system on chip (SoC), a memory, a battery, or a display panel, which is included in an electronic system and generates heat according to power consumption, but the inventive concept is not restricted thereto. 
     In an exemplary embodiment of the inventive concept, a node may be a function block, which is included in a system component, e.g., a SoC, and generates heat according to power consumption. The function block may be hardware, a hardware module, or an electronic circuit which has unique features. The function block may include at least one function component. 
     The function component may be a central processing unit (CPU), a graphics processing unit (GPU), a processor, each core (or less than all cores) in a multi-core processor, a memory, a universal serial bus (USB) device, a bus, a digital signal processor (DSP), an image signal processor (ISP), a wired interface, a wireless interface, a controller, embedded software, a codec, a video module (e.g., a camera interface, a Joint Photographic Experts Group (JPEG) processor, a video processor, or a mixer), a three-dimensional (3D) graphic core, an audio system, or a driver. 
     In an exemplary embodiment of the inventive concept, a node may be at least one circuit or element included in the function component. 
       FIG. 1  is a block diagram of a computing system  100 A according to an exemplary embodiment of the inventive concept. The computing system  100 A may include a PMIC  110 A, an IC  200 A, a memory  300 , and a display  350 . As an example, the PMIC  110 A, the IC  200 A, the memory  300 , and the display  350  may be nodes as system components. 
     Computing systems  100 A,  100 B,  100 C, and  100 D, which will be described hereinafter (with further reference to  FIGS. 6-8 ), may be implemented as personal computers (PCs), data servers, or mobile computing devices. A mobile computing device may be implemented as a laptop computer, a cellular phone, a smart phone, a tablet PC, a personal digital assistant (PDA), an enterprise digital assistant (EDA), a digital still camera, a digital video camera, a portable multimedia player (PMP), a personal navigation device or portable navigation device (PND), a handheld game console, a mobile internet device (MID), a wearable computer, an internet of things (IoT), an internet of everything (IoE), or an e-book. 
     The PMIC  110 A may generate a plurality of operating voltages PW 1  through PW 8  for operating the computing system  100 A. The PMIC  110 A may generate the operating voltages PW 1  through PW 8  using a supply voltage output from a power supply (e.g., a battery) of the computing system  100 A, but the inventive concept is not restricted thereto. 
     The PMIC  110 A may include a storage device REG for storing power data PWI about the operating voltages PW 1  through PW 8 . The storage device REG may be implemented as a register, e.g., a special function register (SFR), but the inventive concept is not restricted thereto. 
     ICs  200 A,  200 B,  200 C, and  200 D, which will be described hereinafter (with further reference to  FIGS. 6-8 ), may be SoCs, application processors (APs), mobile APs, or controllers used as hosts that control the memory  300  and/or the display  350 . 
     The IC  200 A may include a plurality of function blocks  201 ,  210 ,  220 ,  230 ,  240 ,  250 , and  260 . Each of the function blocks  201 ,  210 ,  220 ,  230 ,  240 ,  250 , and  260  may be a node. 
     The IC  200 A may include a CPU  210 , a power estimation circuit  220 , a first function block  230 , a second function block  240 , a memory controller  250 , and a display controller  260 . 
     The IC  200 A may also include one or more temperature sensors TS 1  through TS 5 . The temperature sensors TS 1  through TS 5  may respectively sense temperatures of the respective function blocks  210 ,  230 ,  240 ,  250 , and  260  and may generate temperature data TI 1  through TI 5 , respectively, according to sensing results. Although the temperature sensors TS 1  through TS 5  for measuring the temperatures of the respective function blocks  210 ,  230 ,  240 ,  250 , and  260  are illustrated in  FIG. 1 , the numbers and positions of temperature sensors may vary. For example, two temperature sensors may be used to sense one function block, or the temperature sensor TS 5  for sensing the temperature of the display controller  260  may be placed farther/closer from/to a bus architecture  201 . 
     The IC  200 A may further include a power management unit  205  and a performance monitoring unit (PMU)  270 . The power management unit  205  will be described later with reference to  FIG. 6 . The PMU  270  will be described later with reference to  FIG. 8 . 
     The CPU  210  may control the operations of the power estimation circuit  220 , the first function block  230 , the second function block  240 , the memory controller  250 , and/or the display controller  260  through the bus architecture  201 . The bus architecture  201  may be implemented as an advanced microcontroller bus architecture (AMBA), an advanced high-performance bus (AHB), an advanced peripheral bus (APB), an Advanced eXtensible Interface (AXI), or an advanced system bus (ASB), but the inventive concept is not restricted thereto. 
     The CPU  210  may control resistive-capacitive (RC) thermal modeling data input from an outside of the IC  200 A to be stored in the power estimation circuit  220 . RC thermal modeling will be described in detail with reference to  FIG. 3  later. 
     In an exemplary embodiment of the inventive concept, the CPU  210  may generate RC thermal modeling data and may control the RC thermal modeling data to be stored in the power estimation circuit  220 . 
     The CPU  210  may use a netlist, a timing library, a standard parasitic exchange format (SPEF) file, or a standard delay format (SDF) file, which are provided from an outside of the IC  200 A, to generate the RC thermal modeling data. The timing library may include a cell delay description and the SPEF file may include an interconnection delay description. 
     At least one of the temperature sensors TS 1  through TS 5  may be used to measure or estimate temperatures of a first node at different time points including a first time point and a second time point. 
     The power estimation circuit  220  may receive the power data PWI about powers (or power consumption) of second nodes connected to the first node at the different time points including the first and second time points. 
     The power estimation circuit  220  may estimate a power consumption of the first node at the second time point using RC thermal modeling data between each of the second nodes and the first node, a temperature measured at the first node at each of the different time points, a power measured at each of the second nodes at each of the different time points, and a power of the first node estimated by the power estimation circuit  220  at the first time point. 
     A method of estimating a power consumption of the first node will be described with reference to  FIGS. 3 and 4A  later. 
     The power estimation circuit  220  may compensate (or correct) power data measured (or estimated or calculated) for each of the second nodes, using the power consumption (or power consumption data) estimated for the first node at the second time point. A method of compensating (or correcting) power data of the second nodes will be described in detail with reference to  FIGS. 4B, 4C, and 5  later. 
     In an exemplary embodiment of the inventive concept, the power estimation circuit  220  may estimate power consumption of a node from a temperature of the node using the method which will be described with reference to  FIG. 4A . Nodes whose power consumption may be estimated by this method include nodes whose power consumption might not be estimated by prior techniques, nodes whose power consumption might not be estimated with high accuracy, or nodes whose power consumption estimates are complicated to obtain. 
     The first function block  230  may be implemented as an ISP, but the inventive concept is not restricted thereto. The second function block  240  may be implemented as a GPU, but the inventive concept is not restricted thereto. 
     The memory controller  250  may control the operation of the memory  300 . For example, the memory controller  250  may write data to the memory  300  or read data from the memory  300  according to the control of the CPU  210 . 
     Although one memory controller  250  and one memory  300  are illustrated in  FIG. 1 , the inventive concept is not restricted thereto. In an exemplary embodiment of the inventive concept, a memory may be a memory set including a plurality of memories and a plurality of memory controllers may control the operation of the plurality of memories, respectively. 
     The memories may include a volatile memory and/or a non-volatile memory. When the memories include a dynamic random access memory (DRAM) and a flash-based memory (e.g., NAND flash memory or NOR flash memory), the memory controllers may include a DRAM controller and a flash-based memory controller. 
     The display controller  260  may transmit data from the CPU  210 , the first function block  230 , the second function block  240 , or the memory controller  250  to the display  350  according to the control of the CPU  210 . 
     A mobile industry processor interface (MIPI®), a display serial interface (DSI), an embedded DisplayPort (eDP), or a high-definition multimedia interface (HDMI) may be connected between the display controller  260  and the display  350 , but the inventive concept is not restricted thereto. 
     The display  350  may be a device that can display data and may include a display panel and a controller that controls the operation of the display panel. The display  350  may or may not include a backlight unit controlled by the controller. 
     The display  350  may be implemented as a flat panel display. The flat panel display may be a thin film transistor liquid crystal display (TFT-LCD), a light emitting diode (LED) display, organic LED (OLED) display, an active matrix OLED (AMOLED) display, a flexible display, a double sided display, or a transparent display. 
     Although it is illustrated in  FIG. 1  that the first temperature sensor TS 1  is placed near the CPU  210 , the second temperature sensor TS 2  is placed near the first function block  230 , the third temperature sensor TS 3  is placed near the second function block  240 , the fourth temperature sensor TS 4  is placed near the memory controller  250 , and the fifth temperature sensor TS 5  is placed near the display controller  260 , the inventive concept is not restricted thereto. For example, the temperature sensor TS 4  may be placed closer to the bus between the memory controller  250  and the memory  300 . 
     In an exemplary embodiment of the inventive concept, the computing systems  100 A,  100 B,  100 C, and  100 D may also include a temperature sensor that senses a temperature of the memory  300  and/or the display  350 . The temperature sensors TS 1  through TS 5  may be embedded in the function blocks  210 ,  230 ,  240 ,  250 , and  260 , respectively, in an exemplary embodiment of the inventive concept. When each of the function blocks  210 ,  230 ,  240 ,  250 , and  260  is implemented as a chip, the temperature sensors TS 1  through TS 5  may be integrated into the function blocks  210 ,  230 ,  240 ,  250 , and  260 , respectively. 
     When a chip corresponding to each of the function blocks  210 ,  230 ,  240 ,  250 , and  260  is packaged into a package, each of the temperature sensors TS 1  through TS 5  may be embedded in the package corresponding to one of the function blocks  210 ,  230 ,  240 ,  250 , and  260 . In an exemplary embodiment of the inventive concept, each of the temperature sensors TS 1  through TS 5  may be embedded in a printed circuit board (PCB) of the chip corresponding to one of the function blocks  210 ,  230 ,  240 ,  250 , and  260 . 
     As described above, the temperature sensors TS 1  through TS 5  may be positioned in any place inside or outside the function blocks  210 ,  230 ,  240 ,  250 , and  260 , respectively, to measure the temperatures of the respective function blocks  210 ,  230 ,  240 ,  250 , and  260 . 
     Although the operating voltages PW 1  through PW 8  generated by the PMIC  110 A are respectively applied to the function blocks  210 ,  260 ,  220 ,  230 ,  240 ,  250 ,  300 , and  350  as illustrated in  FIG. 1 , this is just an example. In other words, at least two of the operating voltages PW 1  through PW 8  may be the same. In addition, as shown in  FIG. 1 , the seventh and eighth operating voltages PW 7  and PW 8  may be directly applied to the memory  300  and display  350  from the PMIC  110 A. The first to sixth operating voltages PW 1  to PW 6  may be directly applied to the power management unit  205  from the PMIC  110 A. The power management unit  205  may then provide the operating voltages PW 1  to PW 6  to their respective function blocks  210 ,  260 ,  220 ,  230 ,  240  and  250 . 
     The first operating voltage PW 1  may be applied to a first power domain including the CPU  210 . The second operating voltage PW 2  may be applied to a second power domain including the display controller  260 . The third operating voltage PW 3  may be applied to a third power domain including the power estimation circuit  220 . The fourth operating voltage PW 4  may be applied to a fourth power domain including the first function block  230 . The fifth operating voltage PW 5  may be applied to a fifth power domain including the second function block  240 . The sixth operating voltage PW 6  may be applied to a sixth power domain including the memory controller  250 . The seventh operating voltage PW 7  may be applied to a seventh power domain including the memory  300 . The eighth operating voltage PW 8  may be applied to the display  350 . 
       FIG. 2  is a block diagram of the power estimation circuit  220  illustrated in  FIG. 1 , according to an exemplary embodiment of the inventive concept. Referring to  FIG. 2 , the power estimation circuit  220  may include a power estimation manager circuit  221  and a buffer  223 . The operation of the power estimation manager circuit  221  may be controlled by the CPU  210 . 
     The power estimation manager circuit  221  may receive the power data PWI about the operating voltages PW 1  through PW 8  and temperature data TI and may store the power data PWI and the temperature data TI. In an exemplary embodiment of the inventive concept, the power estimation manager circuit  221  may store the power data PWI and the temperature data TI in the buffer  223  according to the control of the CPU  210 . As shown in  FIG. 2 , the power estimation manager circuit  221  includes a bus wrapper  221 - 1  configured to receive the power data PWI and the temperature data T 1 . The power estimation manager circuit  221  further includes a plurality of de-multiplexers  221 - 3 ,  221 - 4  and  221 - 5  connected to the buffer  223  and a microcontroller  221 - 2  configured to exchange data between the de-multiplexers  221 - 3 ,  221 - 4  and  221 - 5  and the bus wrapper  221 - 1 . The power estimation manager circuit  221  may also output estimated power EPW (to be described in detail later with reference to  FIG. 4A ) to the power management unit  205 . 
     The power data PWI may be read (or fetched) from the storage device REG in the PMIC  110 A. The temperature data TI may include temperature data TI 1  through TI 5  output from at least one of the temperature sensors TS 1  through TS 5 . 
     The buffer  223  may include a first region  223 - 1  storing RC thermal modeling data, a second region  223 - 2  storing the power data PWI, and a third region  223 - 3  storing the temperature data TI. For example, the buffer  223  may be a register but is not restricted thereto. For example, the buffer  223  may be a flip-flop or a static random access memory (SRAM). 
     In an exemplary embodiment of the inventive concept, the RC thermal modeling data may be stored in a translation lookaside buffer (TLB) and the power data PWI and the temperature data TI may be stored in the buffer  223 . In this case, the first region  223 - 1  (for example, the TLB) storing the RC thermal modeling data may be separated from the regions  223 - 2  and  223 - 3  storing the power data PWI and the temperature data TI. 
       FIG. 3  is a diagram for explaining RC thermal modeling, according to an exemplary embodiment of the inventive concept. Referring to  FIG. 3 , a node NODEi targeted for estimation of a power consumption may be connected to a plurality of nodes NODE 1  through NODEn, where “n” is a natural number of at least 2. In this case, the node NODEi may be a node whose power consumption might not be estimated by prior techniques, a node whose power consumption might not be estimated with high accuracy, or a node whose power consumption estimate is complicated to obtain. 
     A reference character R 1   i  denotes a modeling resistance between the nodes NODE 1  and NODEi. A reference character C 1   i  denotes a modeling capacitance between the nodes NODE 1  and NODEi. 
     A reference character R 2   i  denotes a modeling resistance between the nodes NODE 2  and NODEi. A reference character C 2   i  denotes a modeling capacitance between the nodes NODE 2  and NODEi. 
     A reference character R 3   i  denotes a modeling resistance between the nodes NODE 3  and NODEi. A reference character C 3   i  denotes a modeling capacitance between the nodes NODE 3  and NODEi. 
     A reference character Rni denotes a modeling resistance between the nodes NODEn and NODEi. A reference character Cni denotes a modeling capacitance between the nodes NODEn and NODEi. 
       FIG. 4A  shows an equation for explaining a method of estimating a power consumption of a first node using the power estimation circuit  220  illustrated in  FIG. 2 , according to exemplary embodiment of the inventive concept. Referring to  FIGS. 3 and 4A , it is assumed that a first time point T(t−dt) is a previous time point, a second time point T(t) is a current time point, and there is a time difference “dt” between the first time point T(t−dt) and the second time point T(t). It is also assumed that an initial temperature of the node NODEi is a room temperature and an initial power of the node NODEi is zero. 
     For ease of description, it is assumed that the first node, e.g., node NODEi, is the first function block  230  and a plurality of second nodes, e.g., NODE 1  through NODEn (where n=4), are the CPU  210 , the second function block  240 , the memory controller  250 , and the display controller  260 , respectively. 
     In the equation illustrated in  FIG. 4A , it is assumed that Ti(t) is a temperature of the first function block  230  measured by the temperature sensor TS 2  at the second time point T(t), P1(t) is a power of the CPU  210  measured (or estimated) at the second time point T(t), P1(t−dt) is a power of the CPU  210  measured (or estimated) at the first time point T(t−dt), and Ti(t−dt) is a temperature of the first function block  230  measured by the temperature sensor TS 2  at the first time point T(t−dt). 
     It is also assumed that P2(t) is a power of the second function block  240  measured (or estimated) at the second time point T(t), P2(t−dt) is a power of the second function block  240  measured (or estimated) at the first time point T(t−dt), and Pi(t−dt) is a power estimated by the power estimation circuit  220  at the first time point T(t−dt). 
     Accordingly, only Pi(t) is an unknown value in the equation illustrated in  FIG. 4A . As shown in  FIG. 4A , the power estimation circuit  220  may calculate the unknown value Pi(t) using the known values. In other words, the power estimation circuit  220  may estimate (or calculate) a power consumed in the first function block  230  at the second time point T(t) and may generate an estimated power EPW (=Pi(t)). 
     As shown in  FIG. 2 , the first region  223 - 1  of the buffer  223  stores the RC thermal modeling data R 1   i  through Rni and C 1   i  through Cni; the second region  223 - 2  of the buffer  223  stores the power data P1(t−dt) through Pi(t−dt), and P1(t) through P4(t) . . . ; and the third region  223 - 3  of the buffer  223  stores the temperatures Ti(t−dt) and Ti(t). 
     The temperature sensor TS 2  may measure the temperatures Ti(t−dt) and Ti(t) of the first node  230  at different time points including the first time point T(t−dt) and the second time point T(t). 
     The power estimation manager circuit  221  may receive the temperature data TI, e.g., the temperatures Ti(t−dt) and Ti(t) of the first node  230 , from the temperature sensor TS 2  and may store the temperatures Ti(t−dt) and Ti(t) in the third region  223 - 3  of the buffer  223 . 
     The PMIC  110 A may measure (or calculate) powers of each of the second nodes  210 ,  240 ,  250 , and  260  connected to the first node  230  at different time points including the first time point T(t−dt) and the second time point T(t) and may store the power data PWI corresponding to the measurement result in the storage device REG. 
     The power estimation manager circuit  221  may read the power data PWI from the storage device REG and may store the power data PWI that has been read in the second region  223 - 2  of the buffer  223 . 
     The power estimation manager circuit  221  may receive and store the RC thermal modeling data R 1   i  through R 4   i  and C 1   i  through C 4   i  in the first region  223 - 1  of the buffer  223 . 
     The power estimation manager circuit  221  may estimate a power consumption of the first node  230  at the second time point T(t) using the RC thermal modeling data R 1   i  through R 4   i  and C 1   i  through C 4   i  between the each of the second nodes  210 ,  240 ,  250 , and  260  and the first node  230 , the temperatures Ti(t−dt) and Ti(t) of the first node  230  measured at the time points T(t−dt) and T(t), the powers P1(t−dt) through P4(t−dt) and P1(t) through P4(t) of the second nodes  210 ,  240 ,  250 , and  260  measured at the time points T(t−dt) and T(t), and the power Pi(t−dt) of the first node  230  estimated by the power estimation manager circuit  221  at the first time point T(t−dt), and thus, the power estimation manager circuit  221  may generate the estimated power consumption EPW(=Pi(t)). 
       FIGS. 4B and 4C  show equations for explaining a method of correcting power data of the second nodes using the power estimation circuit  220  illustrated in  FIG. 2 , according to an exemplary embodiment of the inventive concept.  FIG. 5  is a flowchart of the method of correcting the power data of each of the second nodes using the power estimation circuit  220  illustrated in  FIG. 2 , according to an exemplary embodiment of the inventive concept. 
     Referring to  FIGS. 1 through 5 , the power estimation manager circuit  221  may estimate the power consumption Pi(t) of the first node  230  at the current (or second) time point T(t) using the temperature Ti(t) of the first node  230  measured at the second time point T(t), RC thermal modeling data stored in the first region  223 - 1 , power data stored in the second region  223 - 2 , and thermal data stored in the third region  223 - 3 , as described with reference to  FIGS. 3 and 4A , in operation S 110 . 
     The power estimation manager circuit  221  may correct the power data P1(t) through P4(t) of the respective second nodes  210 ,  240 ,  250 , and  260  using the power consumption Pi(t) estimated for the first node  230  in operation S 120 . 
     Referring to  FIG. 4B , the power estimation manager circuit  221  may correct the power P1(t), which had been measured for the CPU  210  at the second time point T(t), at a third time point T(t+dt1). It is assumed that a time difference “dt1” is much shorter than the time difference “dt”. Since the time difference “dt1” is very short, the power estimation manager circuit  221  may use data that had been used at the second time point T(t) at the third time point T(t+dt1). 
     In other words, when P1(t) is set as an unknown value by the power estimation manager circuit  221  at the third time point T(t+dt1), the power estimation manager circuit  221  may calculate a power P1′(t) using the equation illustrated in  FIG. 4B . In this case, the power P1(t) may be corrected or changed to the power P1′(t). The power estimation manager circuit  221  may update the power P1(t) stored in the buffer  223  with the power P1′(t). 
     Referring to  FIG. 4C , the power estimation manager circuit  221  may correct the power P2(t), which had been measured for the second function block  240  at the second time point T(t), at a fourth time point T(t+dt2). It is assumed that a time difference “dt2” is much shorter than the time difference “dt”. Since the time difference “dt2” is very short, the power estimation manager circuit  221  may use data that had been used at the second time point T(t) at the fourth time point T(t+dt2). 
     In other words, when P2(t) is set as an unknown value by the power estimation manager circuit  221  at the fourth time point T(t+dt2), the power estimation manager circuit  221  may calculate a power P2′(t) using the equation illustrated in  FIG. 4C . In this case, the power P2(t) may be corrected or changed to the power P2′(t). The power estimation manager circuit  221  may update the power P2(t) stored in the buffer  223  with the power P2′(t). 
     As described above with reference to  FIGS. 4B and 4C , the power estimation manager circuit  221  may correct the power P3(t) of the memory controller  250  at a time point different from the fourth time point T(t+dt2) using a method the same as or similar to the method of correcting the power P1(t) or P2(t) to the power P1′(t) or P2′(t). In addition, the power estimation manager circuit  221  may correct the power P4(t) of the display controller  260  at another time point different from the fourth time point T(t+dt2) using a method the same as or similar to the method of correcting the power P1(t) or P2(t) to the power P1′(t) or P2′(t). 
     As described above with reference to  FIGS. 4A through 4C , the power estimation manager circuit  221  may correct or change the power data P1(t) through P4(t) of the respective second nodes  210 ,  240 ,  250 , and  260  measured at the second time point T(t) using the estimated power Pi(t). Therefore, the power data P1(t) through P4(t) measured or estimated for the second nodes  210 ,  240 ,  250 , and  260 , respectively, may be made more accurate. 
       FIG. 6  is a block diagram of the computing system  100 B according to an exemplary embodiment of the inventive concept. Referring to  FIG. 6 , the computing system  100 B may include a PMIC  110 B, a power measurement circuit  115 A, an IC  200 B, the memory  300 , and the display  350 . As described above, the PMIC  110 B, the IC  200 B, the memory  300 , and the display  350  may be nodes as system components. 
     The PMIC  110 B may generate the operating voltages PW 1  through PW 8  applied to the IC  200 B, the memory  300 , and the display  350 . 
     The power measurement circuit  115 A placed between the PMIC  110 B and the IC  200 B may measure (or estimate or calculate) a power corresponding to each of the operating voltages PW 1  through PW 6  output from the PMIC  110 B and may generate the power data PWI according to the measurement result. The power estimation circuit  220  may use the power data PWI to estimate a power of the first node  230 . 
     The operations and structure of the IC  200 B illustrated in  FIG. 6  are the same as or similar to those of the IC  200 A illustrated in  FIG. 1 . Thus, detailed descriptions of the operations and structure of the IC  200 B will be omitted. 
       FIG. 7  is a block diagram of a computing system  100 C according to an exemplary embodiment of the inventive concept. Referring to  FIG. 7 , the computing system  100 C may include the PMIC  110 B, a power measurement circuit  115 B, an IC  200 C, the memory  300 , and the display  350 . As described above, the PMIC  110 B, the IC  200 C, the memory  300 , and the display  350  may be nodes as system components. 
     The PMIC  110 B may generate the operating voltages PW 1  through PW 8  applied to the IC  200 C, the memory  300 , and the display  350 . 
     The power measurement circuit  115 B integrated into or placed in the IC  200 C may measure (or estimate or calculate) a power corresponding to each of the operating voltages PW 1  through PW 6  output from the PMIC  110 B and may generate the power data PWI according to the measurement result. The power estimation circuit  220  may use the power data PW 1  to estimate a power of the first node  230 . 
     Apart from the position of the power measurement circuit  115 B, the operations and structure of the IC  200 C illustrated in  FIG. 7  are the same as or similar to those of the IC  200 B illustrated in  FIG. 6 . Thus, detailed descriptions of the operations and structure of the IC  200 C will be omitted. 
       FIG. 8  is a block diagram of a computing system  100 D according to an exemplary embodiment of the inventive concept. Referring to  FIG. 8 , the computing system  100 D may include the PMIC  110 B, an IC  200 D, the memory  300 , and the display  350 . As described above, the PMIC  110 B, the IC  200 D, the memory  300 , and the display  350  may be nodes as system components. 
     The PMIC  110 B may generate the operating voltages PW 1  through PW 8  applied to the IC  200 D, the memory  300 , and the display  350 . 
     A PMU  270  may be connected to bus architectures  201 - 1  and  201 - 2 , but the position of the PMU  270  may vary. The bus architectures  201 - 1  and  201 - 2  illustrated in  FIG. 8  are the same as or similar to the bus architecture  201  illustrated in  FIG. 1 . 
     The PMU  270  may monitor bus traffic or data traffic between the first node  230  and each of the second nodes  210 ,  240 ,  250 , and  260  and may generate the power data PWI for each of the second nodes  210 ,  240 ,  250 , and  260  based on the monitoring result. The power estimation circuit  220  may use the power data PWI to estimate a power of the first node  230 . The rest of the components of the IC  200 D are the same as or similar to those of the IC  200 A of  FIG. 1 . Thus, detailed descriptions of the operations and structure of the IC  200 D will be omitted. 
       FIG. 9  is a flowchart of an operation of the computing system  100 A,  100 B,  100 C, or  100 D illustrated in  FIG. 1, 6, 7 , or  8  according to an exemplary embodiment of the inventive concept. Referring to  FIGS. 1 through 9 , the temperature sensor TS 2  may measure the temperatures Ti(t−dt) and Ti(t) of the first node  230  at different time points including the first time point T(t−dt) and the second time point T(t) in operation S 210 . 
     As an example, the PMIC  110 A illustrated in  FIG. 1 , the power measurement circuit  115 A illustrated in  FIG. 6 , the power measurement circuit  115 B illustrated in  FIG. 7 , or the PMU  270  illustrated in  FIG. 8  may measure (or estimate) powers of each of the second nodes  210 ,  240 ,  250 , and  260  connected to the first node  230  at the different time points including the first time point T(t−dt) and the second time point T(t) and may generate the power data PWI corresponding to the measurement result in operation S 220 . As another example, the PMU  270  illustrated in each of  FIGS. 1 and 6-8  can perform this operation. 
     The power estimation circuit  220 , and more particularly, the power estimation manager circuit  221  may estimate a runtime power consumption of the first node  230  at the second time point T(t) using the RC thermal modeling data R 1   i  through R 4   i  and C 1   i  through C 4   i  between the first node  230  and the second nodes  210 ,  240 ,  250 , and  260 , the temperatures Ti(t−dt) and Ti(t) of the first node  230  measured at the different time points, the powers P1(t−dt) through P4(t−dt) and P1(t) through P4(t) of the second nodes  210 ,  240 ,  250 , and  260  measured at the different time points, and the power Pi(t−dt) of the first node  230  estimated by the power estimation circuit  220  at the first time point T(t−dt), and thus, may output the estimated power consumption Pi(t) in operation S 230 . 
     As described above with reference to  FIGS. 4B and 4C , the power estimation circuit  220 , and more particularly, the power estimation manager circuit  221  may correct the power data P1(t) through P4(t) for the respective second nodes  210 ,  240 ,  250 , and  260  using the estimated power consumption Pi(t) of the first node  230  in operation S 240 . 
     As described above with reference to  FIGS. 1 through 9 , data about the power consumption Pi(t) estimated by the power estimation circuit  220  for the first node  230  and/or corrected power data for the second nodes  210 ,  240 ,  250 , and  260  may be stored in the buffer  223 . 
     The CPU  210  may transmit the data stored in the buffer  223  to the PMIC  110 A or  110 B in an exemplary embodiment of the inventive concept. Accordingly, the PMIC  110 A or  110 B may control the operating voltages PW 1  through PW 8  using that data. 
     The CPU  210  may transmit the data stored in the buffer  223  to a clock management unit included in the IC  200 A,  200 B,  200 C, or  200 D in an exemplary embodiment of the inventive concept. Accordingly, the clock management unit may control a frequency of a clock signal applied to each of the nodes  210 ,  230 ,  240 ,  250 , and  260  using that data. 
     As described above, the data about the power consumption Pi(t) estimated for the first node  230  and/or the corrected power data for the second nodes  210 ,  240 ,  250 , and  260  may be used for power management of the computing system  100 A,  100 B,  100 C, or  100 D. 
     The computing system  100 A,  100 B,  100 C, or  100 D can accurately estimate the runtime power consumption of the first node  230  using a method of estimating a power consumption according to an exemplary embodiment of the inventive concept. In addition, the computing system  100 A,  100 B,  100 C, or  100 D can accurately estimate the overall power consumption of the IC  200 A,  200 B,  200 C, or  200 D using a method of estimating a power consumption and/or a method of correcting power data according to an exemplary embodiment of the inventive concept. Moreover, the computing system  100 A,  100 B,  100 C, or  100 D can accurately control its skin temperature using the method of estimating a power consumption and/or the method of correcting power data according to an exemplary embodiment of the inventive concept. 
     While the inventive concept has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the inventive concept as defined by the following claims.