Patent Publication Number: US-2023162788-A1

Title: Memory system and memory device

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is a continuation of and claims benefit under 35 U.S.C. § 120 to U.S. application Ser. No. 17/647,229, filed Jan. 6, 2022, which is a continuation of and claims benefit under 35 U.S.C. § 120 to U.S. application Ser. No. 17/018,684, filed Sep. 11, 2020, which is based upon and claims the benefit of priority from Japanese Patent Application No. 2019-170378, filed Sep. 19, 2019, the entire contents of each of which are incorporated herein by reference. 
    
    
     FIELD 
     Embodiments described herein relate generally to a memory system. 
     BACKGROUND 
     A memory system including a memory device and a controller that controls the memory device is known. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG.  1    illustrates components and connections in a memory system according to a first embodiment, and related components; 
         FIG.  2    illustrates functional blocks of a memory controller according to the first embodiment; 
         FIG.  3    illustrates components and connections in a memory device according to the first embodiment; 
         FIG.  4    illustrates an example of several components and connections in a memory cell array according to the first embodiment; 
         FIG.  5    illustrates a mapping between a threshold voltage distribution of memory cell transistors and data according to the first embodiment; 
         FIG.  6    illustrates an example of processing data for data writes in the memory controller according to the first embodiment; 
         FIG.  7    illustrates a flow of data writes in the memory system according to the first embodiment; 
         FIG.  8    illustrates an example of positions where page data are written in the memory device according to the first embodiment; 
         FIG.  9    illustrates a flow of an input and output signal for data writes and ready/busy states in the memory system according to the first embodiment; 
         FIG.  10    illustrates an input and output signal, a ready/busy signal, and the potential of a selected word line over time in a data read in the memory system according to the first embodiment; 
         FIG.  11    illustrates an example of a flow of data reads in the memory system according to the first embodiment; 
         FIG.  12    illustrates the input and output signal during data reads over time in the memory system according to the first embodiment; 
         FIG.  13    illustrates an example for reference of the positions where page data are written in a memory device; 
         FIG.  14    illustrates an example for reference of an input and output signal during data reads over time in a memory system; 
         FIG.  15    illustrates a mapping between a threshold voltage distribution of memory cell transistors and data according to a second embodiment; 
         FIG.  16    illustrates an example of positions where page data are written in the memory devices according to the second embodiment; 
         FIG.  17    illustrates an input and output signal during data reads over time in the memory system according to the second embodiment; 
         FIG.  18    illustrates an input and output signal during data reads over time in the memory system according to the second embodiment; 
         FIG.  19    illustrates a second example of positions where page data are written in the memory devices according to the second embodiment; 
         FIG.  20    illustrates components and connections in a memory device according to a third embodiment; 
         FIG.  21    illustrates an example of positions where page data are written in the memory devices according to the third embodiment; 
         FIG.  22    illustrates an input and output signal during data reads over time in the memory system according to the third embodiment; 
         FIG.  23    illustrates an input and output signal during data reads over time in the memory system according to the third embodiment; 
         FIG.  24    illustrates a second example of positions where page data are written in the memory devices according to the third embodiment; 
         FIG.  25    illustrates an example of positions where page data are written in the memory devices according to a modification of the third embodiment; 
         FIG.  26    illustrates a mapping between a threshold voltage distribution of memory cell transistors and data according to a fourth embodiment; 
         FIG.  27    illustrates an example of positions where page data are written in the memory devices according to the fourth embodiment; 
         FIG.  28    illustrates an input and output signal during data reads over time in the memory system according to the fourth embodiment; 
         FIG.  29    illustrates an input and output signal during data reads over time in the memory system according to the fourth embodiment; 
         FIG.  30    illustrates an input and output signal during data reads over time in the memory system according to the fourth embodiment; 
         FIG.  31    illustrates an input and output signal during data reads over time in the memory system according to the fourth embodiment; 
         FIG.  32    illustrates a second example of positions where page data are written in the memory devices according to the fourth embodiment; 
         FIG.  33    illustrates an example of positions where page data are written in the memory devices according to a fifth embodiment; 
         FIG.  34    illustrates an example of positions where page data are written in the memory devices according to a modification of the fifth embodiment; 
         FIG.  35    illustrates a mapping between a threshold voltage distribution of memory cell transistors and data according to a sixth embodiment; 
         FIG.  36    illustrates an example of positions where page data are written in the memory devices according to the sixth embodiment; 
         FIG.  37    illustrates an input and output signal during data reads over time in the memory system according to the sixth embodiment; 
         FIG.  38    illustrates an input and output signal during data reads over time in the memory system according to the sixth embodiment; 
         FIG.  39    illustrates a second example of mapping between a threshold voltage distribution of memory cell transistors and data according to the sixth embodiment; 
         FIG.  40    illustrates an example of positions where page data are written in the memory devices according to a modification of the sixth embodiment; 
         FIG.  41    illustrates an example of positions where page data are written in the memory devices according to a seventh embodiment; 
         FIG.  42    illustrates an example of positions where page data are written in the memory devices according to a modification of the seventh embodiment; 
         FIG.  43    illustrates an example of positions where page data are written in the memory device according to an eighth embodiment; 
         FIG.  44    illustrates a mapping between a threshold voltage distribution of memory cell transistors and data according to a ninth embodiment; 
         FIG.  45    illustrates an example of positions where page data are written in the memory devices according to the ninth embodiment; 
         FIG.  46    illustrates an example of positions where page data are written in the memory device according to a 10th embodiment; 
         FIG.  47    illustrates a mapping between a threshold voltage distribution of memory cell transistors and data according to an 11th embodiment; 
         FIG.  48    illustrates an example of positions where page data are written in the memory devices according to the 11th embodiment; 
         FIG.  49    illustrates an input and output signal during data reads over time in the memory system according to the 11th embodiment; 
         FIG.  50    illustrates components and connections in the memory devices according to a 12th embodiment; 
         FIG.  51    illustrates components and connections in an address converter according to the 12th embodiment; 
         FIG.  52    illustrates a state of the address converter according to the 12th embodiment; 
         FIG.  53    illustrates a flow of an input and output signal for data writes in the memory system according to the 12th embodiment; 
         FIG.  54    illustrates an example of positions where page data are written as recognized by the memory controller according to the 12th embodiment; 
         FIG.  55    illustrates an input and output signal during data reads over time in the memory system according to the 12th embodiment; 
         FIG.  56    illustrates an example for reference of an input and output signal for data writes in a memory system; 
         FIG.  57    illustrates components and connections in the memory devices according to a 13th embodiment; 
         FIG.  58    illustrates components and connections in an address converter according to the 13th embodiment; 
         FIG.  59    illustrates a state of the address converter according to the 13th embodiment; 
         FIG.  60    illustrates a flow of an input and output signal for data writes in the memory system according to the 13th embodiment; 
         FIG.  61    illustrates a flow of an input and output signal for data writes in the memory system according to the 13th embodiment; 
         FIG.  62    illustrates an example of positions where page data are written as recognized by the memory controller according to the 13th embodiment; 
         FIG.  63    illustrates an input and output signal during data reads over time in the memory system according to the 13th embodiment; 
         FIG.  64    illustrates an input and output signal during data reads over time in the memory system according to the 13th embodiment; 
         FIG.  65    illustrates an example for reference of an input and output signal for data writes in a memory system; 
         FIG.  66    illustrates functional blocks of a memory controller according to a 14th embodiment; 
         FIG.  67    illustrates a flow of data reads in the memory system according to the 14th embodiment;  FIG.  68    illustrates a first example of the state of a command queue during operations over time in the memory system according to the 14th embodiment; 
         FIG.  69    illustrates a second example of the state of a command queue during operations over time in the memory system according to the 14th embodiment; 
         FIG.  70    illustrates a third example of the state of a command queue during operations over time in the memory system according to the 14th embodiment; 
         FIG.  71    illustrates components and connections in a memory system according to a 15th embodiment, and related components; 
         FIG.  72    illustrates functional blocks of a memory controller according to the 15th embodiment; 
         FIG.  73    illustrates a first example of positions where page data are written in the memory devices according to the 15th embodiment; 
         FIG.  74    illustrates a second example of positions where page data are written in the memory devices according to the 15th embodiment; and 
         FIG.  75    illustrates a third example of positions where page data are written in the memory devices according to the 15th embodiment. 
     
    
    
     DETAILED DESCRIPTION 
     In general, according to one embodiment, a memory system includes n (where n is a natural number equal to or greater than 2) memory cells, each capable of storing j (where j is a natural number equal to or greater than  2 ) bits of data; and a controller. The controller is configured to write a first portion of each of first data to n-th data from among n×j data with consecutive logical addresses to the n memory cells one by one. The first data has a lowest logical address among the n×j pieces of data. The first data to the n-th data have ascending consecutive logical addresses. The controller is configured to write the first portion of one of the first to n-th data to as first bit of the j bits, and write the first portion of another one of the first to n-th data except said one of the first to n-th data as a second bit of the j bits. 
     Embodiments will now be described with reference to the figures. In the following description, components with substantially the same functionalities and configurations will be referred to with the same reference numerals, and repeated descriptions may be omitted. The entire description for a particular embodiment also applies to another embodiment unless it is explicitly mentioned otherwise or obviously eliminated. 
     Each functional block can be implemented as hardware, computer software, or combination of the both. For this reason, in order to clearly illustrate that each block can be any of hardware, software or combination thereof, descriptions will be made in terms of their functionalities in general. It is not necessary that functional blocks are distinguished as in the following examples. For example, some of the functions may be implemented by functional blocks different from those illustrated below. Furthermore, an illustrated functional block may be divided into functional sub-blocks. 
     Moreover, any step in a flow of a method of an embodiment is not limited to any illustrated order, and can occur in an order different from an illustrated order and/or can occur concurrently with another step. 
     In the specification and the claims, a phrase of a particular first component being “coupled” to another second component includes the first component being coupled to the second component either directly or via one or more components which are always or selectively conductive. 
     First Embodiment 
     &lt;1.1. Structure (Configuration)&gt; 
       FIG.  1    illustrates components and connections in a memory system according to a first embodiment, and related components. As illustrated in  FIG.  1   , a memory system  100  includes two or more memory devices MC and a memory controller  2 . The memory system  100  may be a solid-state drive (SSD) or an SD(TM) card, for example. As an example,  FIG.  1    and the following description are based on an example in which the memory system  100  includes four memory devices MC, namely memory devices MC 0 , MC 1 , MC 2 , and MC 3 . The memory devices MC may be semiconductor memory chips, for example. 
     The memory controller  2  is connected to the memory devices MC. The memory controller  2  receives requests from a host device  200 , and operates on the basis of the request from the host device  200  to control the memory devices MC. The memory controller  2  controls the memory devices MC on the basis of the requests from the host device  200 , for example. Specifically, the memory controller  2  writes data in the memory devices MC and reads data from the memory devices MC. 
     The memory controller  2  is connected to the memory devices MC through a NAND bus. The NAND bus transfers a plurality of types of control signals and an  8 -bit input and output signal DQ. Some types of control signals among the plurality of types of control signals as well as the input and output signal DQ are shared by the memory devices MC 0 , MC 1 , MC 2 , and MC 3 . On the other hand, other control signals are provided individually for each memory device MC. The control signals include signals  − CE, CLE, ALE,  − WE,  − RE, and  − WP, data strobe signals DQS and DQS, and a ready/busy signal RB. The sign “ − ” denotes inverted logic, and indicates that a signal denoted by “ − ” is asserted when at a low level. The ready/busy signal RB is prepared individually for each memory device MC, or in other words, the ready/busy signal RB includes ready/busy signals RB 0 , RB 1 , RB 2 , and RB 3  that respectively correspond to the memory devices MC 0 , MC 1 , MC 2 , and MC 3 . A chip enable signal  − CE is prepared individually for each memory device MC, or in other words, the chip enable signal CE includes chip enable signals  − CE 0 ,  − CE 1 ,  − CE 2 , and  − CE 3  that respectively correspond to the memory devices MC 0 , MC 1 , MC 2 , and MC 3 . 
     When asserted, the chip enable signals  − CE 0 ,  − CE 1 ,  − CE 2 , and  − CE 3  enable the memory devices MC 0 , MC 1 , MC 2 , and MC 3 , respectively. An asserted signal CLE informs a memory device MC that the input and output signal DQ that is input into that memory device MC in parallel to that signal CLE is a command. An asserted signal ALE informs a memory device MC that the input and output signal DQ that is input into that memory device MC in parallel to that signal ALE is an address signal. An asserted signal  − WE instructs the memory device MC to fetch the input and output signal DQ that are input into the memory device  1  in parallel to the signal  − WE. An asserted signal  − RE instructs a memory device MC to output the input and output signal DQ. The ready/busy signals RB 0 , RB 1 , RB 2 , and RB 3  indicate whether the memory device MC that outputs respective signals is in a ready state or a busy state. The busy state is indicated by the low level. The memory device MC accepts commands from the memory controller  2  in the ready state, while it does not accept any commands from the memory controller  2  in the busy state. 
     The input and output signal DQ has a width of  8  bits, and includes information such as a command (CMD), write data or read data (DAT), an address (Add), and a status (STA). The notation “DQ” suffixed by “&lt;M:0&gt;” (where M is a natural number) indicates that the corresponding signal has bits from the 0th bit to the Mth bit. 
     The data strobe signals DQS and  − DQS designate the timing of capturing the input and output signal DQ. 
     &lt;1.1.1. Memory Controller&gt; 
       FIG.  1    also illustrates a hardware configuration of the memory controller  2 . As illustrated in  FIG.  1   , the memory controller  2  includes a host interface  21 , a central processing unit (CPU)  22 , a random access memory (RAM)  23 , a read only memory (ROM)  24 , a memory interface  25 , and an error correction circuit (error correction code, or ECC)  26 . The memory controller  2  executes various operations and some of the functions of the host interface  21  and the memory interface  25  by the CPU  22  executing firmware (or, programs) stored in the ROM  24  and loaded in the RAM  23 . The firmware is configured such that the memory controller  2  can be made to perform the operations described as each of the embodiments herein. With this arrangement, a data manager  211 , a read controller  212 , and a write controller  213  described later are configured to operate as described in each of the embodiments. 
     The host interface  21  is connected to the host device  200  through a bus, and manages communication between the memory controller  2  and the host device  200 . The memory interface  25  is connected to the memory devices MC and manages communication between the memory controller  2  and the memory devices MC. 
     The error correction circuit (ECC circuit)  26  encodes data that will be written to the memory devices MC. Also, the error correction circuit  26  decodes data read from the memory devices MC. The encoding and decoding are processes necessary for detecting and correcting errors. Specifically, the error correction circuit  26  performs error-correcting coding processes on the data that will be written to the memory devices MC (substantial write data). Depending on the method of generating the error-correcting code, data that is different from the substantial write data containing the information for error correction by the error-correcting coding may be generated. Data containing redundant data after the error-correcting coding is written to the memory devices MC as the write data. Also, in the error-correcting decoding process, the error correction circuit  26  detects errors in the data read from the memory devices MC, and if errors exist, attempts to correct the errors. 
       FIG.  2    illustrates functional blocks of the memory controller  2  according to the first embodiment. Each functional block is realizable by operations by the CPU  22  following firmware in the RAM  23 , a portion of the memory space in the RAM  23 , and/or dedicated hardware (or, a circuit). 
     As illustrated in  FIG.  2   , the memory controller  2  includes a data manager  211 , a read controller  212 , and a write controller  213 . The data manager  211  manages logical addresses of data supplied from the host device  200  and positions (or, physical addresses) of the data in the memory devices MC. For this purpose, the data manager  211  includes an address conversion table  221 . 
     The read controller  212  executes a process for reading data from the memory devices MC, on the basis of commands received from the host device  200  for example. Specifically, when requested to read particular data in the memory system  100  from the host device  200  for example, the read controller  212  references the logical address of the read-requested data and the address conversion table  221  to determine the physical address where the read-requested data is stored. The read controller  212  transmits a command set giving an instruction to read data from the determined physical address to the memory device MC through the memory interface  25 . 
     The write controller  213  executes a process for writing data to the memory devices MC, on the basis of a command received from the host device  200  for example. Specifically, when requested to store certain data in the memory system  100  from the host device  200  for example, the write controller  213  determines the position in the memory device MC where the data that should be written (or, write data) is to be written, and stores the relationship between the logical address of the write data and the physical address of the write position in the address conversion table  221 . Subsequently, the write controller  213  transmits a command set giving an instruction to write the write data to the determined physical address to the memory device MC through the memory interface  25 . 
     &lt;1.1.2. Memory Device&gt; 
       FIG.  3    illustrates functional blocks of the memory devices MC according to the first embodiment. Each memory device MC includes the functional blocks illustrated in  FIG.  3   . Each memory device MC includes components such as a plurality of planes (PB 0  and PB 1 ), an input and output circuit  11 , and a sequencer  12 .  FIG.  3    illustrates an example in which the memory device MC includes two planes PB 0  and PB 1 , but the first embodiment is not limited to this example, and three or more planes PB may also be provided. 
     The input and output circuit  11  is connected to the memory controller  2  through the NAND bus. The sequencer  12  receives commands and address signals from the input and output circuit  11 , and controls the planes PB on the basis of the commands and address signals. 
     The planes PB are independent of each other, and can execute data read, write, and erase operations independently of each other. Each plane PB includes a memory cell array  13 , a potential generator  14 , a driver  15 , a sense amplifier  16 , and a row decoder  17 . In other words, the plane PB 0  includes a memory cell array  13 _ 0 , a potential generator  14 _ 0 , a driver  15 _ 0 , a sense amplifier  16 _ 0 , and a row decoder  17 _ 0 . The plane PB 1  includes a memory cell array  13 _ 1 , a potential generator  14 _ 1 , a driver  15 _ 1 , a sense amplifier  16 _ 1 , and a row decoder  17 _ 1 . 
     Each memory cell array  13  includes a plurality of memory blocks (or, blocks) BLK (i.e., BLK 0 , BLK 1 , . . . ). Different planes PB include blocks BLK with different addresses. Each block BLK is a set of a plurality of string units SU (i.e, SU 0 , SU 1 , . . . ). Each string unit SU is a set of a plurality of NAND strings (or, strings) STR (i.e., STR 0 , STR 1 , . . . ), which are not illustrated. Each string STR includes a plurality of memory cell transistors MT. 
     The potential generator  14  generates various potentials necessary for various operations, including data write, read, and erase operations, under control by the sequencer  12 . The potential generators  14 _ 0  and  14 _ 1  can operate independently of each other and generate potentials independently of each other. 
     The driver  15  receives a plurality of potentials from the potential generator  14  belonging to the same plane PB (or, corresponding potential generator  14 ), and supplies one or more potentials selected from among the received potentials to the corresponding row decoder  17 . The row decoder  17  receives various potentials from the driver  15 , receives an address signal from the input and output circuit  11 , and transfers the potentials from the corresponding driver  15  to a block BLK selected on the basis of the received address signal from among the corresponding memory cell array  13 . 
     The sense amplifier  16  senses the states of the memory cell transistors MT in the corresponding memory cell array  13 , and on the basis of the sensed states, generates read data and transfers write data to the memory cell transistors MT. 
     &lt;1.1.3. Memory cell array&gt; 
       FIG.  4    illustrates an example of several components and connections in the memory cell array  13  according to the first embodiment, illustrating the components and connections of a single block BLK 0 , and related components. A plurality of the blocks BLK, such as all of the blocks BLK for example, include all of the components and connections illustrated in  FIG.  4   . 
     One block BLK includes a plurality of (for example, four) string units SU 0  to SU 3 . 
     In each block BLK, each of p (where p is a natural number) bit lines BL 0  to BL(p−1) is connected to one string STR from each of the string units SU 0  to SU 3 . 
     Each string STR includes one select gate transistor ST, a plurality of (eight in the figure as an example) memory cell transistors MT such as MT 0  to MT 7 , and one select gate transistor DT such as DT 0 , DT 1 , DT 2 , or DT 3 . The transistors ST, MT, and DT are serially coupled in this order between a source line CELSRC and one bit line BL. A memory cell transistor MT includes a control gate electrode (word line WL) and a charge storage layer insulated from the surroundings, and can store data in a nonvolatile manner based on the amount of charge in the charge storage layer. 
     Strings STR respectively coupled to different bit lines BL make one string unit SU. In each string unit SU, the control gate electrodes of the memory cell transistors MT 0  to MT 7  are respectively coupled to word lines WL 0  to WL 7 . A set of memory cell transistors MT sharing a word line WL in one string unit SU is referred to as a cell unit (or, memory cell set) CU. Also, the gate electrodes of the respective select gate transistors DT of the plurality of strings STR in each string unit SU are coupled to each other. 
     The transistors DT 0  to DT 3  (in  FIG.  4   , DT 2  and DT 3  are not illustrated) belong to the string units SU 0  to SU 3 , respectively. The gate of the transistor DT 0  of each of the plurality of strings STR in the string unit SU 0  is coupled to a select gate line SGDLO. Similarly, the gates of the transistors DT 1 , DT 2 , and DT 3  of each of the plurality of strings STR in each of the string units SU 1 , SU 2 , and SU 3  are coupled to select gate lines SGDL 1 , SGDL 2 , and SGDL 3 . 
     &lt;1.1.4. Cell Transistors&gt; 
       FIG.  5    will be referenced to describe the memory cell transistors MT. Each memory device MC can store two or more bits of data in each of the memory cell transistors MT.  FIG.  5    illustrates a mapping between a threshold voltage distribution of memory cell transistors MT that store four bits of data per memory cell transistor MT and data in the memory system according to the first embodiment. The threshold voltage of each memory cell transistor MT has a magnitude according to the stored data. In the case of storing four bits per memory cell transistor MT, each memory cell transistor MT can be in a state corresponding to a threshold voltage from among  16  states. The 16 states are referred to as the “0”, “1”, “2”, “3”, “4”, “5”, “6”, “7”, “8”, “9”, “10”, “11”, “12”, “13”, “14”, and “15” states. Memory cell transistors MT in the “0” state, “1” state, “2” state, “3” state, “4” state, “5” state, “6” state, “7” state, “8” state, “9” state, “10” state, “11” state, “12” state, “13” state, “14” state, and “15” state have threshold voltages ascending in that order. The “0” state corresponds to the erase state. 
     By a data write, a write-target memory cell transistor MT may be kept in the “0” state or changed to any of the “1” state, “2” state, “3” state, “4” state, “5” state, “6” state, “7” state, “8” state, “9” state, “10” state, “11” state, “12” state, “13” state, “14” state, or “15” state, on the basis of the data to be written. A memory cell transistor MT in the “0” state is a memory cell transistor MT whose threshold voltage is not raised even after a data write, but in the following, an operation in which a memory cell transistor MT is kept in the “0” state by a data write is also referred to as a write. 
     Four bits of data are assignable in any format to each state. In the first embodiment, each state is treated as having the following four-bit data. In the following “ABCD” notation, A, B, C, and D represent the values of the top, upper, middle, and lower bits, respectively.
     “0” State: “1111”   “1” State: “1110”   “2” State: “0110”   “3” State: “0010”   “4” State: “0000”   “5” State: “0001”   “6” State: “0011”   “7” State: “0111”   “8” State: “0101”   “9” State: “1101”   “10” State: “1001”   “11” State: “1011”   “12” State: “1010”   “13” State: “1000”   “14” State: “1100”   “15” State: “0100”   

     Even a plurality of memory cell transistors MT that store identical four-bit data can have different threshold voltages due to variations in the characteristics of the memory cell transistors MT. 
     In order to determine the data stored in a data-read-target memory cell transistor (selected memory cell transistor) MT, the state of the selected memory cell transistor MT is determined. The range within which the threshold voltage of the selected memory cell transistor MT falls is used to determine the state of the selected memory cell transistor MT. To determine the range of the threshold voltage of the selected memory cell transistor MT, it is determined whether or not the selected memory cell transistor MT has a threshold voltage exceeding a particular read voltage VCGR. The memory cell transistor MT having a threshold voltage equal to or higher than the read voltage VCGR remains OFF even while receiving the read voltage VCGR at its control gate electrode. In contrast to this, the memory cell transistor MT having a threshold voltage lower than the read voltage VCGR remains ON while receiving the read voltage VCGR at its control gate electrode. 
     The reads for determining whether the selected memory cell transistor MT is in a state above the “0” state, “1” state, “2” state, “3” state, “4” state, “5” state, “6” state, “7” state, “8” state, “9” state, “10” state, “11” state, “12” state, “13” state, and “14” state are referred to as 1R (read), 2R, 3R, 4R, 5R, 6R, 7R, 8R, 9R, 10R, 11R, 12R, 13R,  14 R, and 15R, respectively. In 1R, 2R, 3R, 4R, 5R, 6R, 7R, 8R, 9R, 10R, 11R, 12R, 13R, 14R, and 15R, read voltages V 1 , V 2 , V 3 , V 4 , V 5 , V 6 , V 7 , V 8 , V 9 , V 10 , V 11 , V 12 , V 13 , V 14 , and V 15  may be used, respectively. The read voltages V 1 , V 2 , V 3 , V 4 , V 5 , V 6 , V 7 , V 8 , V 9 , V 10 , V 11 , V 12 , V 13 , V 14 , and V 15  have default magnitudes, for example. 
     The read voltage V 1  is higher than the highest threshold voltage of the memory cell transistor MT in the “0” state, and lower than the lowest threshold voltage of the memory cell transistor MT in the “1” state immediately after being written. 
     Similarly, for each of the cases of a (where a is a natural number) from 2 to 15, the read voltage Vα is higher than the highest threshold voltage of the memory cell transistor MT in the “(α−1)” state immediately after being written, and lower than the lowest threshold voltage of the memory cell transistor MT in the “α” state immediately after being written. 
     The group of data of the bits at the same positions (or, digits) of the memory cell transistors MT in a cell unit CU forms a page. The group of data of the most-significant (or, first-digit) bits (or, top bits) of the memory cell transistors MT in each cell unit CU is referred to as the top page. The group of data of the second most-significant bits (or, upper bits) of the memory cell transistors MT in each cell unit CU is referred to as the upper page. The group of data of the third most-significant bits (or, middle bits) of the memory cell transistors MT in each cell unit CU is referred to as the middle page. The group of data of the least-significant (or, fourth-digit) bits (or, lower bits) of the memory cell transistors MT in each cell unit CU is referred to as the lower page. 
     The data of each page is determined by reads using a plurality of read voltages VCGR with different magnitudes. Which magnitudes of the read voltage VCGR to use are determined on the basis of which combinations of four-bit data are mapped to each state from the “0” state to the “15” state. In the example of the mapping to the groups of bits (or, bit sets) of the states in  FIG.  5   , the state of each bit in the lower page is determined by 1R, 5R, and 12R. In other words, the selected memory cell transistor MT determined to be between the read voltage V 1  and the read voltage V 5  by 1R and 5R can be determined to be storing 0 in the lower bit. In a similar manner, by using 1R, 5R, and 12R to determine whether each selected memory cell is in the “0” state, in any of the “1”, “2”, “3”, and “4” states, in any of the “5”, “6”, “7”, “8”, “9”, “10”, and “11” states, or in any of the “12”, “13”, “14”, and “15” states, it is possible to determine whether each selected memory cell is storing “0” data or holding “1” data in the lower bit. The use of one or more read voltages to read (or, determine) the data in the lower page of the selected cell unit CU is referred to as a lower page read. 
     Reads of the middle page, the upper page, and the top page are similar, and are performed as follows based on the example of the mapping of states and bit sets in  FIG.  5   . 
     The value of the middle bit of each selected memory cell transistor MT can be determined by 4R, 6R, 8R, 11R, and 13R. The use of one or more read voltages to read the data in the middle page of the selected cell unit CU is referred to as a middle page read. 
     The value of the upper bit of each selected memory cell transistor MT can be determined by 3R, 7R, 10R, and  14 R. The use of one or more read voltages to read the data in the upper page of the selected cell unit CU is referred to as an upper page read. 
     The value of the top bit of each selected memory cell transistor MT can be determined by 2R, 9R, and 15R. The use of one or more read voltages to read the data in the top page of the selected cell unit CU is referred to as a top page read. 
     In the mapping of states and bit sets in  FIG.  5   , three, five, four, and three read voltages VCGR are used for the lower, middle, upper, and top page reads, respectively. Such a mapping is referred to as a “3543 mapping” using the numbers of read voltages VCGR needed for the lower, middle, upper, and top page reads. In other words, the notation “HIJK mapping” (wherein H, I, J, and K are natural numbers) indicates mapping in which H, I, J, and K read voltages VCGR are used for the lower, middle, upper, and top page reads, respectively. 
     A page whose data can be determined by applying the smallest number of read voltages VCGR may be referred to as a fast page. Also, a page whose data can be determined by applying a number of read voltages VCGR other than the smallest number may be referred to as a non-fast page. In the example of the  3543  mapping in  FIG.  5   , the lower page and the top page correspond to fast pages, while the middle page and the upper page correspond to non-fast pages. 
     &lt;1.2. Operations&gt; 
     &lt;1.2.1. Data Writes&gt; 
     The memory controller  2  writes data to the memory devices MC as described below. 
       FIG.  6    illustrates an example of processing data for data writes in the memory controller  2  according to the first embodiment. As illustrated in the uppermost row of  FIG.  6   , the memory controller  2  receives a request (or, command) to store data of a certain size in the memory system  100 , together with the target data of the store request, from the host device  200 . The store-request-target data is referred to as the store-requested data. 
     When received by the memory controller  2 , the store-requested data is held in the RAM  23 . The write controller  213  generates a plurality of page data from the store-requested data as illustrated in the lowermost row of  FIG.  6   . Each piece of page data corresponds to one square on the lowermost row of  FIG.  6   , has a size equal to or less than the size of the page, and the write thereof is managed in data units of the page size. Hereinafter, data of the page size may be simply referred to as page data. When written, the page data corresponds to write data. Each piece of page data to be written (or, write page data) has a logical address assigned by the write controller  213 . In the example of  FIG.  6   , each piece of write page data has a unique logical address from PG 0  to PG 7 . Such generation of a plurality of write page data from store-requested data can be performed according to any method, an example of which is described below. 
     As illustrated on the second row of  FIG.  6   , by dividing the store-requested data into a plurality of parts (referred to as data units DU) and performing error-correcting coding on each data unit DU, the write controller  213  generates write page data derived from the data units DU. In the example of  FIG.  6   , the store-requested data is divided into eight data units DU (DU 0  to DU 7 ). The data units DU 0  to DU 7  can be arranged in that order or arranged at arbitrary positions in the store-requested data. Each data unit DU has a size enabling the set of one data unit DU and redundant data generated for that data unit DU to be equal to or smaller than the page size. The write controller  213  controls the error correction circuit  26  to generate redundant data RD 0  to RD 7  for each of the data units DU 0  to DU 7 . 
     The write controller  213  assigns a logical address to the write page data containing the set of each data unit DU and the corresponding redundant data RD. In the example of  FIG.  6   , the logical address PG 0  is assigned to the write page data containing the set of the data unit DU 0  and the redundant data RD 0 . Similarly, for each of the cases of β from 1 to 7, the logical address PGβ, is assigned to the write page data containing the data unit DUβ and the redundant data RDβ. Hereinafter, the write page data assigned the logical address PG 0  may be referred to as the write page data (or simply the page data) PG 0 . Similarly, the write page data assigned the logical address PGz (where z is a natural number) may be referred to as the write page data PGz. 
     Data processing as illustrated in  FIG.  6    can be performed in order of ascending values of z in “DUz” for the data units DU 0  to DU 7 , for example. However, the first embodiment is not limited to this example, and the data units DU 0  to DU 7  can be processed in any order. 
     The memory controller  2  (particularly, the write controller  213 ) writes the write page data PGz to the memory devices MC according to the method described below. 
     The memory controller  2  writes n pieces of page data PG having consecutive logical addresses one at a time to n planes PB capable of operating independently or to n memory devices MC, and additionally, writes one (first page data) from among the n pieces of page data PG to a certain fast page, and writes the remaining (n−1) pieces of page data PG to pages (fast pages or non-fast pages) other than the page to which the first page data is written. As an example, the write page data PG is written page by page to one cell unit CU, but an embodiment is not strictly limited thereto, and the write page data PG may also be written to only one memory cell transistor of one selected cell unit in one cell unit CU. A specific example according to the first embodiment of a write with features like the above is described below. 
       FIG.  7    illustrates a flow of data writes in the memory system  100  according to the first embodiment. Particularly,  FIG.  7    illustrates a flow for writing eight pieces of page data PG with consecutive logical addresses as illustrated in  FIG.  6    to a certain memory device MCw (where w is 0 or a natural number). Hereinafter, the selected cell unit CU of the plane PBk of the memory device MCw is referred to as the “selected cell unit CUswk”. 
     The eight pieces of page data PG are written to four pages of a selected cell unit CUsw 0  in the plane PB 0  and four pages of a selected cell unit CUsw 1  in the plane PB 1  of a certain memory device MC. Hereinafter, the memory device MC 0  is used as an example. The area where the page data PG is written is referred to as a memory area unit MA. The addresses of the two selected cell units CUs forming a memory area unit MA (the addresses of the connected word lines WL) may be same or different between the planes PB 0  and PB 1 . Hereinafter, in the current example of a certain number (in this example, eight) of consecutive logical addresses, the memory area unit MA is the set of the lower, middle, upper and top pages of the cell unit CUs 00  in the plane PB 0  and the lower, middle, upper, and top pages of the cell unit CUs 01  in the plane PB 1 . Hereinafter, the case of writing write page data PG 0  to PG 7  like in  FIG.  6    will be described as an example. The same applies to any other eight pieces of page data PGz to PG(z+7) with consecutive logical addresses, and the write of the page data PG 0  to PG 7  described below respectively applies. 
     The write controller  213  divides the plurality of page data PG into a plurality of groups according to the rules described below, and writes the page data PG in each group to the memory devices MC according to the rules described below. Hereinafter, a group of page data PG is referred to as a data set. 
     The write controller  213  forms a data set from two pieces of page data PG with consecutive logical addresses. Specifically, the write controller  213  forms a data set from page data PGx (where x is 0 or a natural number) and PG(x+1). Subsequently, the write controller  213  writes one of the two pieces of write data in the data set to the plane PB 0 , and writes the other piece to the plane PB 1 . Furthermore, the write controller  213  writes the page data PGx having the lower logical address out of the page data PGx and PG(x+1) to a fast page among the four pages, and writes the write page data PG(x+1) having the higher logical address out of the page PGx and PG(x+1) to a non-fast page among the four pages. 
     As illustrated in  FIG.  7   , the memory controller  2  sets a parameter r to the lowest logical address among the plurality of page data PG that will be written to a single memory area unit MA (step ST 1 ). In the example illustrated in  FIG.  7   , r is set to 0. The write controller  213  writes the data set of the page data PGr and PG(r+1). The write of a data set is repeated multiple times, and in the first loop, r is 0. First, the write controller  213  writes the page data PGr to a free (or, erased) fast page of the plane PB 0  in the memory area unit MA (step ST 3 ). Next, the write controller  213  writes the page data PG(r+1) to a free non-fast page of the plane PB 1  in the memory area unit MA (step ST 4 ). The write controller  213  writes the data set of the page data PG(r+2) and PG(r+3). Specifically, first, the write controller  213  writes the page data PG(r+2) to a free fast page of the plane PB 1  in the memory area unit MA (step ST 6 ). Next, the write controller  213  writes the page data PG(r+3) to a free non-fast page of the plane PB 0  in the memory area unit MA (step ST 7 ). 
     The write controller  213  determines whether or not the write of all of the page data PG that will be written to the memory area unit MA has been completed (step ST 8 ). In this example, it is determined whether r=7. If completed (Yes branch), the flow in  FIG.  7    ends. If the write of all page data PG has not been completed (No branch), the process proceeds to step ST 9 . 
     In step ST 9 , the write controller  213  sets r=r+4. In other words, 4 is added to the current value of r. Step ST 9  continues to step ST 3 . 
       FIG.  8    illustrates an example of positions where the page data PG is written in the memory device MC according to the first embodiment. Specifically,  FIG.  8    illustrates an example of the positions where the page data PG is written by the write in  FIG.  7   , and illustrates the memory device MC 0  as an example. 
     As illustrated in  FIG.  8   , the page data PG 0  is written to a fast page, such as the lower page for example, of the plane PB 0 , while the page data PG 1  is written to a non-fast page, such as the middle page for example, of the plane PB 1 . 
     The page data PG 2  is written to a fast page, such as the lower page for example, of the plane PB 1 , while the page data PG 3  is written to a non-fast page, such as the middle page for example, of the plane PB 0 . 
     The page data PG 4  is written to a fast page, such as the top page for example, of the plane PB 0 , while the page data PG 5  is written to a non-fast page, such as the upper page for example, of the plane PB 1 . 
     The page data PG 6  is written to a fast page, such as the top page for example, of the plane PB 1 , while the page data PG 7  is written to a non-fast page, such as the upper page for example, of the plane PB 0 . 
     The write in  FIG.  8    is an example, and the first embodiment is not limited to this example. For example, page data having a lower logical address (for example, the page data PG 0  and/or PG 2 ) may be written to the top page, while the page data PG 1  and PG 3  may be written to the upper page. In this case, page data having a higher logical address (for example, the page data PG 4  and/or PG 5 ) may be written to the lower page, while the page data PG 6  and PG 7  may be written to the middle page. 
       FIG.  9    illustrates a flow of the input and output signal DQ for data write and ready/busy states in the memory system  100  according to the first embodiment. More specifically,  FIG.  9    illustrates an example of the input and output signal DQ flowing from the memory controller  2  to the memory device MC 0  for performing the data write in  FIG.  8   . 
     For example, the memory controller  2  instructs the memory device MC 0  to write the page data PG 0  to PG 7  in order of ascending logical address.  FIG.  9    is based on this example. 
     As illustrated in  FIG.  9   , first, the memory controller  2  transmits the signal DQ for writing the page data PG 0 . In other words, the memory controller  2  transmits the page data PG 0  and a command set giving an instruction to write the page data PG 0  to the lower page of the selected cell unit CUs 00  of the plane PB 0 . For this purpose, the memory controller  2  transmits a command  01   h,  a command  80   h,  an address Add, the page data PG 0 , and a command  1 Ah, in that order, for example. The command  01   h  designates the lower page. In other words, the command  01   h  designates that the target of the instruction indicated by the set of commands following the command  01   h  is the lower page. The command  80   h  indicates a write, and the command  1 Ah indicates that the data that will be written to the selected cell unit CUs follows. The address Add designates the plane PB 0  while also designating the block BLK and string unit SU containing the cell unit CUs 00  as well as the word line (selected word line) WL coupled to the cell unit CUs 00 . The address Add is transmitted over five cycles for example, and is illustrated as one cycle in the diagram. Upon receiving the command  1 Ah, the memory device MC 0  temporarily enters a busy state, and after that enters a ready state. 
     Thereafter, the memory controller  2  sequentially transmits signals DQ for writing the page data PG 1  to PG 7  in a similar manner to the signal DQ for writing the page data PG 0 . The differences between the signals DQ for writing the page data PG 1  to PG 7  and the signal DQ for writing the page data PG 0  are the designated plane PB, the designated page, and the page data PG. The differences between the signal DQ for writing the page data PG 7  and the signal DQ for writing the page data PG 0  are the designated plane PB and the designated page data, and in addition, a command  10   h  is included instead of the command  1 Ah. To designate the middle page, the upper page, and the top page, the memory controller  2  transmits the commands  02   h,    03   h,  and  04   h,  respectively, instead of the command  01   h.    
     Specifically, to write the page data PG 1 , the memory controller  2  transmits the page data PG 1  and a command set giving an instruction to write the page data PG 1  to the middle page of the plane PB 1 . 
     After transmitting the signal DQ for writing the page data PG 1 , the memory controller  2  transmits the page data PG 2  and a command set giving an instruction to write the page data PG 2  to the lower page of the plane PB 1 . 
     After transmitting the signal DQ for writing the page data PG 2 , the memory controller  2  transmits the page data PG 3  and a command set giving an instruction to write the page data PG 3  to the middle page of the plane PB 0 . 
     After transmitting the signal DQ for writing the page data PG 3 , the memory controller  2  transmits the page data PG 4  and a command set giving an instruction to write the page data PG 4  to the top page of the plane PB 0 . 
     After transmitting the signal DQ for writing the page data PG 4 , the memory controller  2  transmits the page data PG 5  and a command set giving an instruction to write the page data PG 5  to the upper page of the plane PB 1 . 
     After transmitting the signal DQ for writing the page data PG 5 , the memory controller  2  transmits the page data PG 6  and a command set giving an instruction to write the page data PG 6  to the top page of the plane PB 1 . The memory device MC 0  receives the command  10   h  in the command set designating the write of the page data PGδ, and writes the page data PG 0 , PG 3 , PG 4 , and PG 7  to the cell unit CUs 00  of the plane PB 0 . 
     After transmitting the signal DQ for writing the page data PGδ, the memory controller  2  transmits the page data PG 7  and a command set giving an instruction to write the page data PG 7  to the upper page of the plane PB 0 . When the memory device MC 0  receives the command  10   h  in the command set designating the write of the page data PG 7 , the memory device MC 0  writes the page data PG 1 , PG 2 , PG 5 , and PG 6  to the cell unit CUs 00  of the plane PB 1 . During the writes, the memory device MC 0  stays in the busy state. When the writes is completed, the memory device MC 0  returns to the ready state. 
     &lt;1.2.2. Data Read&gt; 
       FIG.  10    illustrates the input and output signal DQ, the ready/busy signal RB, and the potentials of the selected word lines WL over time in data reads in the memory system  100  according to the first embodiment.  FIG.  10    successively illustrates data reads from the lower page, the middle page, the upper page, and the top page of the selected cell unit CUs in a certain plane PB. However,  FIG.  10    is intended to merely illustrate data reads from the lower page, the middle page, the upper page, and the top page of the selected cell unit CUs, and the illustrated order of the data-read-target pages has no significance. 
     As illustrated in  FIG.  10   , to read from the lower page, the memory controller  2  transmits a command set giving an instruction to read data from the lower page of the selected cell unit CUs. For this purpose, the memory controller  2  transmits the command  01   h,  a command  00   h,  the address Add, and a command  30   h,  in that order, for example. The command  00   h  declares that the transmission of an address follows, and the command  30   h  gives an instruction to read data from the page of the designated address. An address Add designates the plane PB, the block BLK and string unit SU that contain the selected cell unit CUs, and the selected word line WL. Upon receiving the command  30   h,  the memory device MC starts a lower page read. 
     To read data from the designated page, the memory device MC applies a plurality of read voltages VCGR determined according to the designated page to the selected word line WL. Subsequently, the memory device performs a single-level reads using respective read voltages VCGR, and hold the results in the latch in the sense amplifier  16 . A single-level read refers to obtaining a set of one-bit data determined on the basis of whether or not the selected memory cell transistor MT has a threshold voltage equal to or higher than the read voltage VCGR. By taking a single-level read at each read voltage VCGR, a result of the single-level read with the read voltage VCGR is obtained, and by performing logical operations on the single-level read data respectively based on the plurality of single-level reads obtained in this way, page data is obtained. Details are as follows. 
     As illustrated in  FIG.  10    and also described with reference to  FIG.  5   , to perform a lower page read, the memory device MC successively applies the read voltages V 1 , V 5 , and V 12 . The memory device MC performs a single-level read (1R, 5R, or 12R) while each of the read voltages V 1 , V 5 , and V 12  is applied, holds the results in a data latch, and performs logical operations on the results of the single-level reads to obtain the lower page data. The memory device MC, following an instruction (the signal  − RE) from the memory controller  2 , transmits the obtained lower page data (L-DAT) to the memory controller  2 . 
     The middle page read, the upper page read, and the top page read are similar. For the middle page read, the memory device MC successively applies the read voltages V 4 , V 6 , V 8 , V 11 , and V 13 . The memory device MC performs a single-level read (4R, 6R, 8R, 11R, or 13R) while corresponding one of the read voltages V 4 , V 6 , V 8 , V 11 , and V 13  is applied, holds the results in a data latch, and performs logical operations on the results of the single-level reads to obtain the middle page data. The memory device MC, following an instruction from the memory controller  2 , transmits the obtained middle page data (M-DAT) to the memory controller  2 . 
     For the upper page read, the memory device MC successively applies the read voltages V 3 , V 7 , V 10 , and V 14 . Additionally, the memory device MC performs a single-level read ( 3 R, 7R, 10R, or  14 R) while corresponding one of the read voltages V 3 , V 7 , V 10 , and V 14  is applied, holds the results in a data latch, and performs logical operations on the results of the single-level reads to obtain the upper page data. The memory device MC, following an instruction from the memory controller  2 , transmits the obtained upper page data (U-DAT) to the memory controller  2 . 
     For the top page read, the memory device MC successively applies the read voltages V 2 , V 9 , and V 15 . The memory device MC performs a single-level read (2R, 9R, or 15R) while corresponding one of the read voltages V 2 , V 9 , and V 15  is applied, holds the results in a data latch, and performs logical operations on the results of the single-level reads to obtain the top page data. The memory device MC, following an instruction from the memory controller  2 , transmits the obtained top page data (T-DAT) to the memory controller  2 . 
       FIG.  11    illustrates an example of a flow of data reads in the memory system  100  according to the first embodiment. Particularly,  FIG.  11    illustrates a data read from one memory area unit MA of a certain memory device MC. The memory area unit MA is inside the memory device MC 0 , for example. 
     As illustrated in  FIG.  11   , in step ST 11 , the memory controller  2  transmits a command set giving an instruction to read page data PGt (where t is 0 or an even natural number) to the memory device MC 0 . When the memory device MC 0  receives the command set, the memory device MC 0  in step ST 12  starts the read of the page data PGt. 
     In step ST 13 , the memory controller  2  instructs the memory device MC to read the page data PG(t+1). When the memory device MC 0  receives the command set, the memory device MC 0  in step ST 14  starts the read of the page data PG(t+1). 
     In step ST 16 , the read of the page data PGt in the memory device MC 0  is completed. In step ST 17 , the memory controller  2  instructs the memory device MC 0  to output the page data PGt. 
     In step ST 18 , the read of the page data PG(t+1) in the memory device MC 0  is completed. In step ST 19 , the memory controller  2  instructs the memory device MC 0  to output the page data PG(t+1). 
     In step ST 21 , the memory controller  2  determines whether data reads from all pages in the read-target memory area unit MA have been completed. In the current example, this determination corresponds to determining whether t is 7. 
     In the case where the data reads from all pages in the read-target memory area unit MA have not been completed (No branch), the memory controller  2  sets t==t+2 in step ST 22 . Step ST 22  continues to step ST 11 . In the case where the data reads from all pages in the read-target memory area unit MA have been completed (Yes branch), the process ends. 
       FIG.  12    illustrates the flow of the input and output signal DQ during data reads over time in the memory system  100  according to the first embodiment. 
     Particularly,  FIG.  12    illustrates the states between the operations in  FIG.  11   , and illustrates reads from the memory area unit MA, or in other words, data reads from the four pages of each of the selected cell units CUs 00  and CUs 01 , which are respectively from the plane PB 0  and the plane PB 1 . 
     The memory controller  2  reads data in units of data sets from a memory area unit MA, and reads some page data PG in parallel from each data set. Data sets can be read in any order, but reads can be performed in order of ascending logical address of the page data PG for example. Hereinafter, a specific example is described. 
     As illustrated in  FIG.  12   , the memory controller  2  instructs the memory device MC 0  to read the data sets of the page data PG 0  and PG 1  in parallel. For this purpose, the memory controller  2  transmits a command set giving an instruction for a lower page read to the selected cell unit CUs 00  of the plane PB 0 , and also transmits a command set giving an instruction for a middle page read to the selected cell unit CUs 01  of the plane PB 1 . The lower page read with respect to the selected cell unit CUs 00  of the plane PB 0  and the middle page read with respect to the selected cell unit CUs 01  of the plane PB 1  are performed in parallel. The transmitted command sets give an instruction for such a parallel read (multi-plane read) from the planes PB 0  and PB 1 . 
     As an example, the memory controller  2  transmits a command set giving an instruction for a multi-plane read of the data in the lower page of the selected cell unit CUs 00  of the plane PB 0 . Such a command includes the command  01   h  specifying the lower page, the command  00   h,  the address Add specifying the read-target plane PB 0  and selected cell unit CUs 00 , and the command  32   h,  for example. The command  32   h  indicates that a command set for a multi-plane read follows. Upon receiving the command set, the memory device MC 0  enters the busy state from a time t 1 . Because the command set indicates the data read indicated by the command set as well as indicating that a command set for a multi-plane read follows, after entering the busy state for a short time from the time t 1 , the memory device MC 0  returns to the ready state at a time t 2 . 
     Also, in response to the receipt of the command set by the time t 1 , the memory device MC 0  starts a lower page read (in the diagram, “lower read”) with respect to the selected cell unit CUs 00  of the plane PB 0  from the time t 1 . As described above, the lower page read includes 1R, 5R, and 12R. 
     The memory controller  2  transmits a command set for performing a middle page read as well as a multi-plane read with respect to the selected cell unit CUs 01  of the plane PB 1  from the time t 2 . In other words, the memory device MC 0  transmits a command set giving an instruction for a middle page read with respect to the selected cell unit CUs 01  of the plane PB 1  from the time t 2 . The command set indicates that a command set designating a data read of the target of the multi-plane read does not follow, and includes the command  02   h  indicating the middle page, the command  00   h,  the address Add, and the command  30   h,  for example. Upon receiving the command set, the memory device MC 0  remains in the busy state. 
     Also, in response to the receipt of the command set by a time t 3 , the memory device MC 0  starts a middle page read (in the diagram, “middle read”) with respect to the selected cell unit CUs 01  of the plane PB 1  from the time t 3 . The middle page read with respect to the selected cell unit CUs 01  of the plane PB 1  and the ongoing lower page read with respect to the selected cell unit CUs 00  of the plane PB 0  are performed in parallel. As described above, the middle page read includes 4R, 6R, 8R, 11R, and 13R. 
     The lower page read with respect to the selected cell unit CUs 00  of the plane PB 0  is completed at a time t 4 , and the lower page data, that is, the page data PG 0 , can be output from the memory device MC 0 . The memory device MC 0  (particularly, the sequencer  12 ) detects the completion of the read and enters the ready state from the time t 4 . The memory controller  2  detects the transition to the ready state, instructs the memory device MC 0  to output the page data PG 0 , and receives the page data PG 0 . At the time t 4 , the middle page read in the plane PB 1  is not yet completed. 
     While the page data PG 0  is being output, the middle page read in the plane PB 1  proceeds. The middle page read is completed at a time t 5 , and the middle page data, that is, the page data PG 1 , can be output from the memory device MC 0 . For example, after the receipt of the page data PG 0  is completed, the memory controller  2  transmits a status read command to the memory device MC 0  and checks the completion of the middle page read. The status read command is a command instructing the memory device MC to transmit information related to the internal state of the memory device MC. Upon receiving the status read command, the memory device MC can transmit a status indicating whether the process according to the last-received command (in the current example, the middle page read) is completed or not, for example. The memory controller  2  learns of the completion of the middle page read through the status read command, and from a time t 5 , instructs the memory device MC 0  to output the page data PG 1 , and receives the page data PG 1 . 
     Thereafter, in a similar manner to the page data PG 0  and PG 1 , the memory device MC 0  performs multi-plane reads of the remaining data sets in the selected cell units CUs 00  and CUs 01 . An overview of this process is described below. 
     When the receipt of the page data PG 1  is completed, the memory controller  2  reads the page data in the next data set in parallel. As an example, the memory controller  2  performs a multi-plane read to read the data set of the page data PG 2  and PG 3  in parallel. For this purpose, the memory controller  2  transmits a command set giving an instruction for a multi-plane read of the data in the lower page of the selected cell unit CUs 01  of the plane PB 1 , for example. Upon receiving the command set, the memory device MC 0  starts a lower page read with respect to the selected cell unit CUs 01  of the plane PB 1  from a time t 6 . 
     The memory controller  2  transmits a command set giving an instruction to perform a multi-plane read of the data in the middle page of the selected cell unit CUs 00  of the plane PB 0  from a time t 7 . Upon receiving the command set, the memory device MC 0  starts a middle page read with respect to the selected cell unit CUs 00  of the plane PB 0  from a time t 8 . The middle page read in the plane PB 0  proceeds in parallel with the ongoing lower page read in the plane PB 1 . 
     The lower page read in the plane PB 1  is completed at a time t 9 , and the lower page data, that is, the page data PG 2 , can be output from the memory device MC 0 . The memory controller  2  instructs the memory device MC 0  to output the page data PG 2 , and receives the page data PG 2  from a time t 9 . 
     While the page data PG 2  is being output, the middle page read in the plane PB 0  continues. After that, the middle page read is completed, and the middle page data, that is, the page data PG 3 , can be output from the memory device MC 0 . The memory controller  2  uses a status read to learn of the completion of the middle page read, and from a time t 10 , instructs the memory device MC 0  to output the page data PG 3 , and receives the page data PG 3 . 
     When the receipt of the page data PG 3  is completed, the memory controller  2  reads the page data in the next data set in parallel. As an example, the memory controller  2  performs a multi-plane read to read the data set of the page data PG 4  and PG 5  in parallel. For this purpose, the memory controller  2  transmits a command set giving an instruction for a multi-plane read of the data in the top page of the selected cell unit CUs 00  of the plane PB 0 , for example. Upon receiving the command set, the memory device MC 0  starts a top page read with respect to the selected cell unit CUs 00  of the plane PB 0  from a time t 11 . 
     The memory controller  2  transmits a command set giving an instruction to perform a multi-plane read of the data in the upper page of the selected cell unit CUs 01  of the plane PB 1  from a time t 12 . Upon receiving the command set, the memory device MC 0  starts an upper page read with respect to the selected cell unit CUs 01  of the plane PB 1  from a time t 13 . The upper page read in the plane PB 1  proceeds in parallel with the ongoing top page read in the plane PB 0 . 
     The top page read in the plane PB 0  is completed at a time t 14 , and the top page data, that is, the page data PG 4 , can be output from the memory device MC 0 . The memory controller  2  instructs the memory device MC 0  to output the page data PG 4 , and receives the page data PG 4  from a time t 14 . 
     While the page data PG 4  is being output, the upper page read in the plane PB 0  continues. After that, the upper page read is completed, and the upper page data, that is, the page data PG 5 , can be output from the memory device MC 0 . The memory controller  2  uses a status read to learn of the completion of the upper page read, and from a time t 15 , instructs the memory device MC 0  to output the page data PG 5 , and receives the page data PG 5 . 
     When the receipt of the page data PG 5  is completed, the memory controller  2  reads the page data in the next data set in parallel. As an example, the memory controller  2  performs a multi-plane read to read the data set of the page data PG 6  and PG 7  in parallel. For this purpose, the memory controller  2  transmits a command set giving an instruction for a multi-plane read of the data in the top page of the selected cell unit CUs 01  of the plane PB 1 , for example. Upon receiving the command set, the memory device MC 0  starts a top page read with respect to the selected cell unit CUs 01  of the plane PB 1  from a time t 16 . 
     The memory controller  2  transmits a command set giving an instruction to perform a multi-plane read of the data in the upper page of the selected cell unit CUs 00  of the plane PB 0  from a time t 17 . Upon receiving the command set, the memory device MC 0  starts an upper page read with respect to the selected cell unit CUs 00  of the plane PB 0  from a time t 18 . The upper page read in the plane PB 0  proceeds in parallel with the ongoing top page read in the plane PB 1 . 
     The top page read in the plane PB 1  is completed at a time t 19 , and the top page data, that is, the page data PGδ, can be output from the memory device MC 0 . The memory controller  2  instructs the memory device MC 0  to output the page data PGδ, and receives the page data PG 6  from a time t 19 . 
     While the page data PG 6  is being output, the upper page read in the plane PB 0  continues. After that, the upper page read is completed, and the upper page data, that is, the page data PG 7 , can be output from the memory device MC 0 . The memory controller  2  uses a status read to learn of the completion of the upper page read, and from a time t 20 , instructs the memory device MC 0  to output the page data PG 7 , and receives the page data PG 7 . 
     &lt;1.3. Advantages (Advantageous Effects)&gt; 
     According to the memory system  100  of the first embodiment, the memory controller  2  is capable of obtaining data in a short time as described below. 
     The page data PG 0  to PG 7  are assumed to be written to a certain memory device MC (for example, MC 0 ), as illustrated in  FIG.  13    and also described below.  FIG.  13    illustrates an example for reference of the positions where the page data PG is written in the memory device MC 0 . 
     As illustrated in  FIG.  13   , as the simplest form of writes, each data set of the page data PG 0  to PG 7  is written to the same pages from among the lower pages, middle pages, upper pages, and top pages in different planes PB. In other words, the page data PG 0  is written to the lower page of the plane PB 0 , while the page data PG 1  is written to the lower page of the plane PB 1 . The page data PG 2  is written to the middle page of the plane PB 0 , while the page data PG 3  is written to the middle page of the plane PB 1 . The page data PG 4  is written to the upper page of the plane PB 0 , while the page data PG 5  is written to the upper page of the plane PB 1 . The page data PG 6  is written to the top page of the plane PB 0 , while the page data PG 7  is written to the top page of the plane PB 1 . 
     As a result of such a write, it is anticipated that reads of the page data PG 0  to PG 7  will be performed as follows. In other words, the page data PG 0  and PG 1  are read in parallel, the page data PG 2  and PG 3  are read in parallel, the page data PG 4  and PG 5  are read in parallel, and the page data PG 6  and PG 7  are read in parallel. The command sets, flow of data, and transitions of the ready/busy signal RB during the above series of reads are illustrated in  FIG.  14   .  FIG.  14    illustrates an example for reference of the input and output signal DQ during data reads over time in the memory system  100 . 
     As illustrated in  FIG.  14   , the memory controller  2  instructs the memory device MC 0  to read the page data PG 0  and PG 1 . Upon receiving the command set, the memory device MC 0  starts a lower page read with respect to the selected cell unit CUs 00  of the plane PB 0 , and subsequently starts a lower page read with respect to the selected cell unit CUs 01  of the plane PB 1 . The two reads are both reads from the lower page, and therefore are completed at substantially the same timings. Upon reaching a state where the page data PG 0  and PG 1  can be output, the memory controller  2  instructs the memory device MC 0  to output one piece of the data, such as the page data PG 0  for example, and receives the page data PG 0 . When the receipt of the page data PG 0  is completed, the memory controller  2  instructs the memory device MC 0  to output the page data PG 1 . Therefore, the data reads from the two planes PB 0  and PB 1  require an amount of time equal to the operating time of the plane PB 0  or PB 1 , the time to output the page data PG 0 , and the time to output the page data PG 1 . 
     Because it is necessary to apply three or four different read voltages VCGR for each page read, reading data from many pieces of page data is time-consuming, such as in the case of reading data from all pages in the memory area unit MA. 
     On the other hand, the page data PG 1  cannot be output while the page data PG 0  is being output even if the preparations for outputting the page data PG 1  are completed, and effective utilization of such time is a consideration. 
     The memory controller  2  according to the first embodiment determines a write destination for each group of first page data and second page data having consecutive logical addresses, and writes the first page data to a fast page in a first plane PB out of two planes PB capable of operating independently in parallel, while writing the second page data to a non-fast page in the other of the two planes, namely a second plane PB. The memory controller  2  reads in parallel the first and second page data written in this way. With this operation, the read of the first page data from the memory cell array  13  is completed first, and while the first page data is being output from the memory device MC, the read of the second page data from the memory cell array  13  can proceed. Therefore, the output of the first page data and part of the read of the second page data are performed in parallel, and the wait time until the output preparations are completed and the data can be output like in the reference example ( FIG.  14   ) is greatly reduced. For this reason, by proceeding with the read of the second page data during the output of the first page data, the first and second page data can be read and output efficiently. 
     Such an advantage of the first embodiment is obtained by configuring the memory area unit MA such that the following conditions are satisfied. Namely, it is necessary to make it possible to read from both a non-fast page and a fast page in parallel. To achieve the above, page data PG with consecutive ascending logical addresses of a number equal to y (or, the number of pages per cell unit CU)/b (or, the number of fast pages per cell unit CU) form a data set, and the memory area unit MA is formed over independently operable planes PB of a number equal to the number of pieces of page data PG in the data set. In the first embodiment, a cell unit CU has a memory area of four pages in size, and a cell unit CU has two fast pages. For this reason, in the first embodiment, the memory area unit MA needs two independently operable planes PB, and the memory area unit MA spreads over the two independently operable planes PB 0  and PB 1  in a single memory device MC. 
     Second Embodiment 
     The second embodiment is similar to the first embodiment, but the mapping is different from the first embodiment. Hereinafter, the features that differ from the first embodiment will be described mainly. 
     The configuration of the memory system  100  and the memory devices MC according to the second embodiment is the same as that of the first embodiment. 
     &lt;2.1. Mapping&gt; 
     In the second embodiment, a  4434  mapping is used.  FIG.  15    illustrates a mapping between a threshold voltage distribution of memory cell transistors MT that store four bits of data per memory cell transistor MT and data in the memory system according to the second embodiment. As illustrated in  FIG.  15   , in the second embodiment, each memory device MC is treated as having the following four-bit data for each state.
     “0” State: “1111”   “1” State: “1110”   “2” State: “1010”   “3” State: “1000”   “4” State: “1001”   “5” State: “0001”   “6” State: “0000”   “7” State: “0010”   “8” State: “0110”   “9” State: “0100”   “10” State: “1100”   “11” State: “1101”   “12” State: “0101”   “13” State: “0111”   “14” State: “0011”   “15” State: “1011”   

     In the 4434 mapping, the data of each page is determined using the following read voltages.
     Lower page read: 1R, 4R, 6R, and 11R   Middle page read: 3R, 7R, 9R, and 13R   Upper page read: 2R, 8R, and  14 R   Top page read: 5R, 10R, 12R, and 15R   

     In the 4434 mapping, the upper page corresponds to the fast page, while the lower page, the middle page, and the top page correspond to non-fast pages. 
     &lt;2.2. Data Writies&gt; 
     In the second embodiment, each cell unit CU stores data of four pages in size, and the four pages include just one fast page. Based on this configuration, in the second embodiment, the memory area unit MA spreads over four independently operable planes PB. For this reason, y (the number of pages per cell unit CU)/b (the number of fast pages per cell unit CU)=4, and therefore four pieces of write page data PG with consecutive logical addresses form a data set, and the memory area unit MA is formed over four independently operable planes PB. 
     Specifically, the memory area unit MA according to the second embodiment spreads over the planes PB 0  and PB 1  of the memory device MC 0  and the planes PB 0  and PB 1  of the memory device MC 1 . Hereinafter, the memory area unit MA according to the second embodiment is referred to as the memory area unit MA 2 . 
       FIG.  16    illustrates an example of the memory area unit MA 2  and positions where page data are written in the memory devices MC according to the second embodiment. As illustrated in  FIG.  16   , the memory area unit MA 2  is the set of the lower, middle, upper, and top pages of a cell unit CUs 00  in a plane PB 0  of a memory device MC 0 , the lower, middle, upper, and top pages of a cell unit CUs 01  in a plane PB 1  of the memory device MC 0 , the lower, middle, upper, and top pages of a cell unit CUs 10  in a plane PB 0  of a memory device MC 1 , and the lower, middle, upper, and top pages of a cell unit CUs 11  in a plane PB 1  of the memory device MC 1 . 
     Based on such features of the memory area unit MA 2 , 16 pieces of page data PG with consecutive logical addresses are stored in a single memory area unit MA 2 . As a specific example,  FIG.  16    illustrates an example of the positions where 16 pieces of page data PG 0  to PG 15  with consecutive logical addresses are written in the memory area unit MA 2 . 
     For each of the cases where γ is 0, 4, 8, and 12, the page data PGγ, PG(γ+1), PG(γ+2), and PG(γ+3) form a data set. As illustrated in  FIG.  16   , the page data PGγ, 
     PG(γ+1), PG(γ+2), and PG(γ+3) in each data set are written one by one to the planes PB 0  and PB 1  of each of the memory devices MC 0  and MC 1 , and in addition, one of the page data PGγ, PG(γ+1), PG(γ+2), and PG(γ+3) is written to a fast page (upper page) while the remaining three are written to non-fast pages. Also, each piece of page data included in a data set and written to a non-fast page is written to any of the lower, middle, and top pages. Furthermore, the pages to which the page data PG 0  to PG 15  are written are determined such that four data sets are written to the memory area unit MA 2 . Insofar as writes are performed in this way, the positions where the page data PG 0  to PG 15  are written are not limited to the example in  FIG.  16   . As an example, the page data PG written to the non-fast pages can be written to different one of lower, middle, and top pages. 
     As illustrated in  FIG.  16   , the page data PG 0  is written to the upper page of the selected cell unit CUs 00  in the plane PB 0  of the memory device MC 0 . The page data PG 1  is written to the middle page of the selected cell unit CUs 01  in the plane PB 1  of the memory device MC 0 . The page data PG 2  is written to the lower page of the selected cell unit CUs 10  in the plane PB 0  of the memory device MC 1 . The page data PG 3  is written to the top page of the selected cell unit CUs 11  in the plane PB 1  of the memory device MC 1 . 
     The page data PG 4  is written to the upper page of the selected cell unit CUs 00  in the plane PB 1  of the memory device MC 0 . The page data PG 5  is written to the middle page of the selected cell unit CUs 00  in the plane PB 0  of the memory device MC 0 . The page data PG 6  is written to the lower page of the selected cell unit CUs 11  in the plane PB 1  of the memory device MC 1 . The page data PG 7  is written to the top page of the selected cell unit CUs 10  in the plane PB 0  of the memory device MC 1 . 
     The page data PG 8  is written to the upper page of the selected cell unit CUs 10  in the plane PB 0  of the memory device MC 1 . The page data PG 9  is written to the middle page of the selected cell unit CUs 11  in the plane PB 1  of the memory device MC 1 . The page data PG 10  is written to the top page of the selected cell unit CUs 00  in the plane PB 0  of the memory device MC 0 . The page data PG 11  is written to the lower page of the selected cell unit CUs 01  in the plane PB 1  of the memory device MC 0 . 
     The page data PG 12  is written to the upper page of the selected cell unit CUs 11  in the plane PB 1  of the memory device MC 1 . The page data PG 13  is written to the middle page of the selected cell unit CUs 10  in the plane PB 0  of the memory device MC 1 . The page data PG 14  is written to the top page of the selected cell unit CUs 01  in the plane PB 1  of the memory device MC 0 . The page data PG 15  is written to the lower page of the selected cell unit CUs 00  in the plane PB 0  of the memory device MC 0 . 
     &lt;2.3. Data reads&gt; 
       FIGS.  17  and  18    illustrate the flow of the input and output signal DQ during data reads over time in the memory system  100  according to the second embodiment.  FIG.  18    illustrates the state following  FIG.  17   . 
     As illustrated in  FIGS.  17  and  18   , a data read from any of the non-fast pages proceeds in parallel with a data read of a fast page (upper page). 
     To read the data set containing the page data PG 0  to PG 3 , the memory controller  2  first instructs the memory device MC 0  to read the page data PG 0  stored in the fast page. The memory device MC 0  receives the instruction and starts an upper page read in the plane PB 0  of the memory device MC 0  for obtaining the page data PG 0 . Next, the memory controller  2  instructs the memory devices MC 0  and MC 1  to read the page data PG 1 , PG 2 , and PG 3 . The middle page read in the plane PB 1  of the memory device MC 0  for obtaining the page data PG 1 , the lower page read in the plane PB 0  of the memory device MC 1  for obtaining the page data PG 2 , and the top page read in the plane PB 1  of the memory device MC 1  for obtaining the page data PG 3  proceed in parallel with the top page read in the plane PB 0  of the memory device MC 0 . 
     When the read of the page data PG 0  is completed, the memory device MC 0  outputs the page data PG 0  in accordance with the instruction from the memory controller  2 . While the memory device MC 0  is outputting the page data PG 0 , the middle page read in the plane PB 1  of the memory device MC 0 , the lower page read in the plane PB 0  of the memory device MC 1 , and the top page read in the plane PB 1  of the memory device MC 1  can proceed. 
     Thereafter, the memory controller  2  similarly reads the data set containing the page data PG 4  to PG 7 , reads the data set containing the page data PG 8  to PG 11 , and reads the data set containing the page data PG 12  to PG 15 . For reading any of the data sets, a data read from the fast page of each data set is started first, and after that, data reads from the non-fast pages are started. Subsequently, in each data set, a lower page read, a middle page read, an upper page read, and a top page read proceed in parallel over the planes PB 0  and PB 1  of each of the memory devices MC 0  and MC 1 . 
     &lt;2.4. Another Example of Writes&gt; 
     An example of data writes includes write as illustrated in  FIG.  19   .  FIG.  19    illustrates a second example of positions where page data are written in the memory devices MC according to the second embodiment. 
     As illustrated in  FIG.  19   , the page data PG 0  is written to the upper page of the selected cell unit CUs 00  in the plane PB 0  of the memory device MC 0 . The page data PG 1  is written to the top page of the selected cell unit CUs 01  in the plane PB 1  of the memory device MC 0 . The page data PG 2  is written to the lower page of the selected cell unit CUs 10  in the plane PB 0  of the memory device MC 1 . The page data PG 3  is written to the middle page of the selected cell unit CUs 11  in the plane PB 1  of the memory device MC 1 . 
     The page data PG 4  is written to the upper page of the selected cell unit CUs 01  in the plane PB 1  of the memory device MC 0 . The page data PG 5  is written to the top page of the selected cell unit CUs 10  in the plane PB 0  of the memory device MC 1 . The page data PG 6  is written to the lower page of the selected cell unit CUs 11  in the plane PB 1  of the memory device MC 1 . The page data PG 7  is written to the middle page of the selected cell unit CUs 00  in the plane PB 0  of the memory device MC 0 . 
     The page data PG 8  is written to the upper page of the selected cell unit CUs 10  in the plane PB 0  of the memory device MC 1 . The page data PG 9  is written to the top page of the selected cell unit CUs 11  in the plane PB 1  of the memory device MC 1 . The page data PG 10  is written to the lower page of the selected cell unit CUs 00  in the plane PB 0  of the memory device MC 0 . The page data PG 11  is written to the middle page of the selected cell unit CUs 01  in the plane PB 1  of the memory device MC 0 . 
     The page data PG 12  is written to the upper page of the selected cell unit CUs 11  in the plane PB 1  of the memory device MC 1 . The page data PG 13  is written to the top page of the selected cell unit CUs 00  in the plane PB 0  of the memory device MC 0 . The page data PG 14  is written to the lower page of the selected cell unit CUs 01  in the plane PB 1  of the memory device MC 0 . The page data PG 15  is written to the middle page of the selected cell unit CUs 10  in the plane PB 0  of the memory device MC 1 . 
     &lt;2.5. Advantages&gt; 
     According to the second embodiment, the memory area unit MA 2  spreads over two memory devices MC including independently operable planes PB, first page data out of a data set containing four pieces of page data having four consecutive logical addresses is written to a fast page (upper page), while the remaining page data are written to different pages than the page where the first page data is written from among the lower, middle, upper, and top pages. During reads of a data set written in this way, reads of the page data other than the first page data of the data set can proceed while the first page data is being output. For this reason, in the case of the  4434  mapping, data can be read and output with the same efficiency as the first embodiment. 
     Third Embodiment 
     The third embodiment resembles the second embodiment. In the third embodiment, the  4434  mapping is used like in the second embodiment. Hereinafter, the features that differ from the second embodiment will be described mainly. 
     The configuration of the memory system  100  according to the third embodiment is the same as that of the first embodiment. On the other hand, the third embodiment differs from the first embodiment in the details of the memory devices MC. 
     &lt;3.1. Configuration of Memory Devices&gt; 
     In the third embodiment, unlike the first embodiment, the plurality of planes PB in each memory device MC cannot operate independently. 
       FIG.  20    illustrates functional blocks of a memory device MC according to the third embodiment. The memory devices MC according to the third embodiment may be referred to as the memory devices MCa. As illustrated in  FIG.  20   , unlike the first embodiment ( FIG.  3   ), each memory device MCa does not include the potential generator  14 _ 0  and the driver  15 _ 0  for the plane PB 0  and also does not include the potential generator  14 _ 1  and the driver  15 _ 1  for the plane PB 1 . Instead, each memory device MCa shares a potential generator  14  and a driver  15 . 
     Based on such a configuration of the memory device MCa, for a multi-plane read from the planes PB 0  and PB 1 , the same read voltage VCGR is applied to the planes PB 0  and PB 1 . Therefore, in the planes PB 0  and PB 1 , the same pages from among the lower, middle, upper, and top pages become the targets of the parallel data reads. 
     &lt;3.2. Data Writes&gt; 
     In the third embodiment, each cell unit CU stores data of four pages in size, and the four pages include just one fast page. Based on this configuration, in the third embodiment, the memory area unit MA needs to spread over four independently operable planes PB. In the third embodiment, the planes PB 0  and PB 1  in each memory device MC cannot operate independently. For this reason, the memory area unit MA needs to spread over four memory devices MC. 
     To this end, the memory area unit MA according to the third embodiment spreads over a plane PB of the memory device MC 0 , a plane PB of the memory device MC 1 , a plane PB of the memory device MC 2 , and a plane PB of the memory device MC 3 . The memory area unit MA according to the third embodiment is referred to as the memory area unit MA 3 . 
       FIG.  21    illustrates an example of the memory area unit MA 3  and positions where page data are written in the memory devices MC according to the third embodiment. As illustrated in  FIG.  21   , the memory area unit MA 3  is the set of the lower, middle, upper, and top pages of a selected cell unit CUs 0   w  in a plane PBw of the memory device MC 0 , the lower, middle, upper, and top pages of a cell unit CUs 1   w  in a plane PBw of the memory device MC 1 , the lower, middle, upper, and top pages of a cell unit CUs 2   w  in a plane PBw of a memory device MC 2 , and the lower, middle, upper, and top pages of a cell unit CUs 3   w in a plane PBw of the memory device MC 3 .    
     Based on such features of the memory area unit MA 3 , 16 pieces of page data PG with consecutive logical addresses are stored in a single memory area unit MA 3 . As a specific example,  FIG.  21    illustrates the positions where 16 pieces of page data PG 0  to PG 15  with consecutive logical addresses are written in the memory area unit MA 3 . 
     For each of the cases where y is 0, 4, 8, and 12, the page data PGγ, the page data PG(γ+1), the page data PG(γ+2), and the page data PG(γ+3) form a data set. 
     As illustrated in  FIG.  21   , the page data PGγ, PG(γ+1), PG(γ+2), and PG(γ+3) in each data set are written one by one to the memory devices MC 0  to MC 3 , and in addition, one of the page data PGγ, PG(γ+1), PG(γ+2), and PG(γ+3) is written to a fast page while the remaining three are written to non-fast pages. Also, the page data included in a data set and written to a non-fast page is written to any of the lower, middle, and top pages. Furthermore, the pages to which the page data PG 0  to PG 15  are written are determined such that four data sets are written to the memory area unit MA 3 . Insofar as writes are performed in this way, the positions where the page data PG 0  to PG 15  are written are not limited to the example in  FIG.  21   . As an example, the page data written to the non-fast pages can be written to different one of lower, middle, and top pages. 
     As illustrated in  FIG.  21   , the page data PG 0  is written to the upper page of the selected cell unit CUs 0   w  of the memory device MC 0 . The page data PG 1  is written to the middle page of the selected cell unit CUs 1   w  of the memory device MC 1 . The page data PG 2  is written to the lower page of the selected cell unit CUs 2   w  of the memory device MC 2 . The page data PG 3  is written to the top page of the selected cell unit CUs 3   w of the memory device MC 3 .    
     The page data PG 4  is written to the upper page of the selected cell unit CUs 1   w  of the memory device MC 1 . The page data PG 5  is written to the middle page of the selected cell unit CUs 0   w  of the memory device MC 0 . The page data PG 6  is written to the lower page of the selected cell unit CUs 3   w  of the memory device MC 3 . The page data PG 7  is written to the top page of the selected cell unit CUs 2   w  of the memory device MC 2 . 
     The page data PG 8  is written to the upper page of the selected cell unit CUs 2   w  of the memory device MC 2 . The page data PG 9  is written to the middle page of the selected cell unit CUs 3   w  of the memory device MC 3 . The page data PG 10  is written to the top page of the selected cell unit CUs 0   w  of the memory device MC 0 . The page data PG 11  is written to the lower page of the selected cell unit CUs 1   w  of the memory device MC 1 . 
     The page data PG 12  is written to the upper page of the selected cell unit CUs 3   w  of the memory device MC 3 . The page data PG 13  is written to the middle page of the selected cell unit CUs 2   w  of the memory device MC 2 . The page data PG 14  is written to the top page of the selected cell unit CUs 1   w  of the memory device MC 1 . The page data PG 15  is written to the lower page of the selected cell unit CUs 0   w  of the memory device MC 0 . 
     &lt;3.3. Data Reads&gt; 
       FIGS.  22  and  23    illustrate the flow of the input and output signal DQ during data reads over time in the memory system  100  according to the third embodiment.  FIG.  23    illustrates the state following  FIG.  22   . 
     As illustrated in  FIGS.  22  and  23   , a data read from any of the non-fast pages proceeds in parallel with a data read of a fast page (upper page). 
     To read the data set containing the page data PG 0  to PG 3 , the memory controller  2  first instructs the memory device MC 0  to read the page data PG 0  stored in the fast page. The memory device MC 0  receives the instruction and starts an upper page read of the memory device MC 0  for obtaining the page data PG 0 . Next, the memory controller  2  instructs the memory device MC 1  to perform a middle page read for the page data PG 1 , instructs the memory device MC 2  to perform a lower page read for the page data PG 2 , and instructs the memory device MC 3  to perform a top page read for the page data PG 3 . The upper page read in the memory device MC 0 , the middle page read in the memory device MC 1 , the lower page read in the memory device MC 2 , and the top page read in the memory device MC 3  proceed in parallel. 
     When the read of the page data PG 0  is completed, the memory device MC 0  outputs the page data PG 0  in accordance with the instruction from the memory controller  2 . While the memory device MC 0  is outputting the page data PG 0 , the middle page read in the memory device MC 1 , the lower page read in the memory device MC 2 , and the top page read in the memory device MC 3  can proceed. 
     Thereafter, the memory controller  2  similarly reads the data set containing the page data PG 4  to PG 7 , reads the data set containing the page data PG 8  to PG 11 , and reads the data set containing the page data PG 12  to PG 15 . For reading any of the data sets, a data read from the fast page of each data set is started first, and after that, data reads from the non-fast pages are started. Thus, in each data set, a lower page read, a middle page read, an upper page read, and a top page read proceed in parallel over the memory devices MC 0 , MC 1 , MC 2 , and MC 3 . 
     &lt;3.4. Another Example of Data Writes&gt; 
     An example of data writes includes writes as illustrated in  FIG.  24   .  FIG.  24    illustrates a second example of positions where page data are written in the memory devices MC according to the third embodiment. 
     As illustrated in  FIG.  24   , the page data PG 0  is written to the upper page of the selected cell unit CUs 0   w  of the memory device MC 0 . The page data PG 1  is written to the top page of the selected cell unit CUs 1   w  of the memory device MC 1 . The page data PG 2  is written to the lower page of the selected cell unit CUs 2   w  of the memory device MC 2 . The page data PG 3  is written to the middle page of the selected cell unit CUs 3   w  of the memory device MC 3 . 
     The page data PG 4  is written to the upper page of the selected cell unit CUs 1   w  of the memory device MC 1 . The page data PG 5  is written to the top page of the selected cell unit CUs 2   w  of the memory device MC 2 . The page data PG 6  is written to the lower page of the selected cell unit CUs 3   w  of the memory device MC 3 . The page data PG 7  is written to the middle page of the selected cell unit CUs 0   w  of the memory device MC 0 . 
     The page data PG 8  is written to the upper page of the selected cell unit CUs 2   w  of the memory device MC 2 . The page data PG 9  is written to the top page of the selected cell unit CUs 3   w  of the memory device MC 3 . The page data PG 10  is written to the lower page of the selected cell unit CUs 0   w  of the memory device MC 0 . The page data PG 11  is written to the middle page of the selected cell unit CUs 1   w  of the memory device MC 1 . 
     The page data PG 12  is written to the upper page of the selected cell unit CUs 3   w  of the memory device MC 3 . The page data PG 13  is written to the top page of the selected cell unit CUs 0   w  of the memory device MC 0 . The page data PG 14  is written to the lower page of the selected cell unit CUs 1   w  of the memory device MC 1 . The page data PG 15  is written to the middle page of the selected cell unit CUs 2   w  of the memory device MC 2 . 
     &lt;3.5. Advantages&gt; 
     According to the third embodiment, the memory area unit MA 3  spreads over four memory devices MC, first page data out of a data set containing four pieces of page data having four consecutive logical addresses is written to a fast page (upper page), while the remaining page data are written to different pages than the page where the first page data is written from among the lower, middle, upper, and top pages. During reads of a data set written in this way, reads of the page data other than the first page data of the data set can proceed while the first page data is being output. For this reason, data can be read and output with the same efficiency as the first embodiment, even in the case where the memory devices MC do not include a plurality of independently operable planes PB. 
     &lt;3.6. Modification&gt; 
     The third embodiment may also be applied to multi-plane operations. However, in each memory device MC according to the third embodiment, the planes PB 0  and PB 1 , although capable of operating in parallel, are not capable of operating independently, and therefore data reads are performed in parallel from the same pages of cell units CU with the same address in the blocks BLK of the same address in each of the planes PB 0  and PB 1 . Based on the above, two pieces of page data PG with consecutive logical addresses are written to the same pages in the planes PB 0  and PB 1  of the same memory device MC. 
     A memory area unit MA 3   a  according to a modification of the third embodiment spreads over the planes PB 0  and PB 1  of the memory device MC 0 , the planes PB 0  and PB 1  of the memory device MC 1 , the planes PB 0  and PB 1  of the memory device MC 2 , and the planes PB 0  and PB 1  of the memory device MC 3 . 
       FIG.  25    illustrates an example of the memory area unit MA 3   a  and positions where page data are written in the memory devices MC according to the modification of the third embodiment. For each of the cases where γ is 0, 4, 8, and 12, the page data PGγ, the page data PG(γ+1), the page data PG(γ+2), the page data PG(γ+3), the page data PG(γ+4), the page data PG(γ+5), the page data PG(γ+6), and the page data PG(γ+7) form a data set. 
     As illustrated in  FIG.  25   , the memory area unit MA 3   a  is the set of the lower, middle, upper, and top pages of a cell unit CUs 00  in a plane PB 0  of a memory device MC 0 , the lower, middle, upper, and top pages of a cell unit CUs 01  in a plane PB 1  of the memory device MC 0 , the lower, middle, upper, and top pages of a cell unit CUs 10  in a plane PB 0  of a memory device MC 1 , the lower, middle, upper, and top pages of a cell unit CUs 11  in a plane PB 1  of the memory device MC 1 , the lower, middle, upper, and top pages of a cell unit CUs 20  in a plane PB 0  of a memory device MC 2 , the lower, middle, upper, and top pages of a cell unit CUs 21  in a plane PB 1  of a memory device MC 2 , the lower, middle, upper, and top pages of a cell unit CUs 30  in a plane PB 0  of a memory device MC 3 , and the lower, middle, upper, and top pages of a cell unit CUs 31  in a plane PB 1  of a memory device MC 3 . 
     Based on such features of the memory area unit MA 3   a,  32 pieces of page data PG with consecutive logical addresses are stored in a single memory area unit MA 3   a.  As a specific example,  FIG.  25    illustrates the positions where 32 pieces of write page data PG 0  to PG 31  with consecutive logical addresses are written in the memory area unit MA 3   a.    
     For each of the cases where γ is 0, 8, 16, and 24, the page data PGγ, PG(γ+1), PG(γ+2), PG(γ+3), PG(γ+4), PG(γ+5), PG(γ+6), and PG(γ+7) form a data set. In addition, the page data PGγ and PG(γ+1) form a pair, the page data PG(γ+2) and PG(γ+3) form a pair, the page data PG(γ+4) and PG(γ+5) form a pair, and the page data PG(γ+6) and PG(γ+7) form a pair. The two pieces of page data PG that form a pair are written to the same page in different planes PB of the same memory device MC. 
     As illustrated in  FIG.  25   , the pairs of page data PG in each data set are written one by one to the memory devices MC 0  to MC 3 , and one of the pairs of page data PG in each data is written to fast pages while the remaining three pairs are written to non-fast pages. 
     Also, the pairs of page data PG included in a data set and written to non-fast pages are written to any of the lower, middle, and top pages. Furthermore, the pages to which the page data PG 0  to PG 31  is written are determined such that four data sets are written to the memory area unit MA 3   a.  Insofar as writes are performed in this way, the positions where the page data PG 0  to PG 31  are written is not limited to the example in  FIG.  25   . As an example, the page data PG written to the non-fast pages can be written to different one of lower, middle, and top pages. 
     As illustrated in  FIG.  25   , the page data PG 0  is written to the upper page of the selected cell unit CUs 00  in the plane PB 0  of the memory device MC 0 . The page data PG 1  is written to the upper page of the selected cell unit CUs 01  in the plane PB 1  of the memory device MC 0 . 
     The page data PG 2  is written to the middle page of the selected cell unit CUs 10  in the plane PB 0  of the memory device MC 1 . The page data PG 3  is written to the middle page of the selected cell unit CUs 11  in the plane PB 1  of the memory device MC 1 . 
     The page data PG 4  is written to the lower page of the selected cell unit CUs 20  in the plane PB 0  of the memory device MC 2 . The page data PG 5  is written to the lower page of the selected cell unit CUs 21  in the plane PB 1  of the memory device MC 2 . 
     The page data PG 6  is written to the top page of the selected cell unit CUs 30  in the plane PB 0  of the memory device MC 3 . The page data PG 7  is written to the top page of the selected cell unit CUs 31  in the plane PB 1  of the memory device MC 3 . 
     The page data PG 8  is written to the upper page of the selected cell unit CUs 10  in the plane PB 0  of the memory device MC 1 . The page data PG 9  is written to the upper page of the selected cell unit CUs 11  in the plane PB 1  of the memory device MC 1 . 
     The page data PG 10  is written to the middle page of the selected cell unit CUs 00  in the plane PB 0  of the memory device MC 0 . The page data PG 11  is written to the middle page of the selected cell unit CUs 01  in the plane PB 1  of the memory device MC 0 . 
     The page data PG 12  is written to the lower page of the selected cell unit CUs 30  in the plane PB 0  of the memory device MC 3 . The page data PG 13  is written to the lower page of the selected cell unit CUs 31  in the plane PB 1  of the memory device MC 3 . 
     The page data PG 14  is written to the top page of the selected cell unit CUs 20  in the plane PB 0  of the memory device MC 2 . The page data PG 15  is written to the top page of the selected cell unit CUs 21  in the plane PB 1  of the memory device MC 2 . 
     The page data PG 16  is written to the upper page of the selected cell unit CUs 20  in the plane PB 0  of the memory device MC 2 . The page data PG 17  is written to the upper page of the selected cell unit CUs 21  in the plane PB 1  of the memory device MC 2 . 
     The page data PG 18  is written to the middle page of the selected cell unit CUs 30  in the plane PB 0  of the memory device MC 3 . The page data PG 19  is written to the middle page of the selected cell unit CUs 31  in the plane PB 1  of the memory device MC 3 . 
     The page data PG 20  is written to the top page of the selected cell unit CUs 00  in the plane PB 0  of the memory device MC 0 . The page data PG 21  is written to the top page of the selected cell unit CUs 01  in the plane PB 1  of the memory device MC 0 . 
     The page data PG 22  is written to the lower page of the selected cell unit CUs 10  in the plane PB 0  of the memory device MC 1 . The page data PG 23  is written to the lower page of the selected cell unit CUs 11  in the plane PB 1  of the memory device MC 1 . 
     The page data PG 24  is written to the upper page of the selected cell unit CUs 30  in the plane PB 0  of the memory device MC 3 . The page data PG 25  is written to the upper page of the selected cell unit CUs 31  in the plane PB 1  of the memory device MC 3 . 
     The page data PG 26  is written to the middle page of the selected cell unit CUs 20  in the plane PB 0  of the memory device MC 2 . The page data PG 27  is written to the middle page of the selected cell unit CUs 21  in the plane PB 1  of the memory device MC 2 . 
     The page data PG 28  is written to the top page of the selected cell unit CUs 10  in the plane PB 0  of the memory device MC 1 . The page data PG 29  is written to the top page of the selected cell unit CUs 11  in the plane PB 1  of the memory device MC 1 . 
     The page data PG 30  is written to the lower page of the selected cell unit CUs 00  in the plane PB 0  of the memory device MC 0 . The page data PG 31  is written to the lower page of the selected cell unit CUs 01  in the plane PB 1  of the memory device MC 0 . 
     For data reads, the basic principle is the same as the data reads according to the third embodiment described with reference to  FIGS.  22  and  23   , the difference being that pairs of page data PG are read in parallel. In other words, when each read command set illustrated in  FIGS.  22  and  23    is received by each memory device MC, the memory device MC reads data in parallel from the same pages of cell units CU with the same address instructed by the read command set in each of the planes PB 0  and PB 1 . The data obtained by such reads is a pair of page data PG. The memory controller  2  instructs each memory device MC to output a pair of page data PG, and receives the pair of page data PG. 
     Fourth Embodiment 
     The fourth embodiment is similar to the second embodiment, and is different from the second embodiment in the mapping. Hereinafter, the features that differ from the second embodiment will be described mainly. 
     The configuration of the memory system  100  and the memory devices MC according to the fourth embodiment is the same as that of the first embodiment. 
     &lt;4.1. Mapping&gt; 
     In the fourth embodiment, a  1248  mapping is used.  FIG.  26    illustrates a mapping between a threshold voltage distribution of memory cell transistors MT that store four bits of data per memory cell transistor MT and data in the memory system according to the fourth embodiment. As illustrated in  FIG.  26   , in the fourth embodiment, each memory device MC treats each state as having the following four-bit data.
     “0” State: “1111”   “1” State: “0111”   “2” State: “0011”   “3” State: “1011”   “4” State: “1001”   “5” State: “0001”   “6” State: “0101”   “7” State: “1101”   “8” State: “1100”   “9” State: “0100”   “10” State: “0000”   “11” State: “1000”   “12” State: “1010”   “13” State: “0010”   “14” State: “0110”   “15” State: “1110”   

     In the 1248 mapping, the data of each page is determined using the following read voltages.
     Lower page read: 8R   Middle page read: 4R and 12R   Upper page read: 2R, 6R, 10R, and  14 R   Top page read: 1R, 3R, 5R, 7R, 9R, 11R, 13R, and 15R   

     In the 1248 mapping, the lower page corresponds to the fast page, while the middle page, the upper page, and the top page correspond to non-fast pages. 
     &lt;4.2. Data Writes&gt; 
     In the fourth embodiment, each cell unit CU stores data of four pages in size, and the four pages include just one fast page. Based on this configuration, in the fourth embodiment, the memory area unit MA 2  of the second embodiment is used. 
       FIG.  27    illustrates an example of positions where page data are written in the memory devices MC according to the fourth embodiment. As a specific example,  FIG.  27    illustrates the positions where 16 pieces of write page data PG 0  to PG 15  with consecutive logical addresses are written in the memory area unit MA 2 . 
     For each of the cases where γ is 0, 4, 8, and 12, the page data PGγ, PG(γ+1), PG(γ+2), and PG(γ+3) form a data set. 
     As illustrated in  FIG.  27   , the page data PGγ, PG(γ+1), PG(γ+2), and PG(γ+3) in each data set are written one by one to the planes PB 0  and PB 1  of each of the memory devices MC 0  and MC 1 , and in addition, one of the page data PGγ, PG(γ+1), PG(γ+2), and PG(γ+3) is written to a fast page (lower page) while the remaining three are written to non-fast pages. Also, each piece of page data PG included in a data set and written to a non-fast page is written to any of the middle, upper, and top pages. Furthermore, the pages to which the page data PG 0  to PG 15  are written are determined such that four data sets are written to the memory area unit MA 2 . Insofar as writes are performed in this way, the positions where the page data PG 0  to PG 15  are written are not limited to the example in  FIG.  27   . As an example, the page data PG written to the non-fast pages can be written to different one of middle, upper, and top pages. 
     As illustrated in  FIG.  27   , the page data PG 0  is written to the lower page of the selected cell unit CUs 00  in the plane PB 0  of the memory device MC 0 . The page data PG 1  is written to the middle page of the selected cell unit CUs 01  in the plane PB 1  of the memory device MC 0 . The page data PG 2  is written to the upper page of the selected cell unit CUs 10  in the plane PB 0  of the memory device MC 1 . The page data PG 3  is written to the top page of the selected cell unit CUs 11  in the plane PB 1  of the memory device MC 1 . 
     The page data PG 4  is written to the lower page of the selected cell unit CUs 01  in the plane PB 1  of the memory device MC 0 . The page data PG 5  is written to the middle page of the selected cell unit CUs 10  in the plane PB 0  of the memory device MC 1 . The page data PG 6  is written to the upper page of the selected cell unit CUs 11  in the plane PB 1  of the memory device MC 1 . The page data PG 7  is written to the top page of the selected cell unit CUs 00  in the plane PB 0  of the memory device MC 0 . 
     The page data PG 8  is written to the lower page of the selected cell unit CUs 10  in the plane PB 0  of the memory device MC 1 . The page data PG 9  is written to the middle page of the selected cell unit CUs 11  in the plane PB 1  of the memory device MC 1 . The page data PG 10  is written to the upper page of the selected cell unit CUs 00  in the plane PB 0  of the memory device MC 0 . The page data PG 11  is written to the top page of the selected cell unit CUs 01  in the plane PB 1  of the memory device MC 0 . 
     The page data PG 12  is written to the lower page of the selected cell unit CUs 11  in the plane PB 1  of the memory device MC 1 . The page data PG 13  is written to the middle page of the selected cell unit CUs 00  in the plane PB 0  of the memory device MC 0 . The page data PG 14  is written to the upper page of the selected cell unit CUs 01  in the plane PB 1  of the memory device MC 0 . The page data PG 15  is written to the top page of the selected cell unit CUs 10  in the plane PB 0  of the memory device MC 1 . 
     &lt;4.3. Data Reads&gt; 
       FIGS.  28  to  31    illustrate the flow of the input and output signal DQ during data reads over time in the memory system  100  according to the fourth embodiment.  FIGS.  28  to  31    illustrate temporally successive states in order. 
     As illustrated in  FIGS.  28  and  31   , a data read from any of the non-fast pages proceeds in parallel with a data read of a fast page (lower page). 
     To read the data set containing the page data PG 0  to PG 3 , the memory controller  2  first instructs the memory device MC 0  to read the page data PG 0  stored in the fast page. The memory device MC 0  receives the instruction and starts a lower page read in the plane PB 0  of the memory device MC 0  for obtaining the page data PG 0 . Next, the memory controller  2  instructs the memory device MC 0  to perform a middle page read for the page data PG 1 , instructs the memory device MC 1  to perform an upper page read for the page data PG 2 , and instructs the memory device MC 1  to perform a top page read for the page data PG 3 . The lower page read in the plane PB 0  of the memory device MC 0 , the middle page read in the plane PB 1  of the memory device MC 0 , the upper page read in the plane PB 0  of the memory device MC 1 , and the top page read in the plane PB 1  of the memory device MC 1  proceed in parallel. 
     When the read of the page data PG 0  is completed, the memory device MC 0  outputs the page data PG 0  in accordance with the instruction from the memory controller  2 . While the memory device MC 0  is outputting the page data PG 0 , the middle page read in the memory device MC 0 , the upper page read in the memory device MC 1 , and the top page read in the memory device MC 1  can proceed. 
     Thereafter, the memory controller  2  similarly reads the data set containing the page data PG 4  to PG 7 , reads the data set containing the page data PG 8  to PG 11 , and reads the data set containing the page data PG 12  to PG 15 . For reading any of the data sets, a data read from the fast page of each data set is started first, and after that, data reads from the non-fast pages are started. Thus, in each data set, a lower page read, a middle page read, an upper page read, and a top page read proceed in parallel over the planes PB 0  and PB 1  of each of the memory devices MC 0  and MC 1 . 
     &lt;4.4. Another Example of Writes&gt; 
     An example of data writes includes writes as illustrated in  FIG.  32   .  FIG.  32    illustrates a second example of positions where page data are written in the memory devices MC according to the fourth embodiment. 
     As illustrated in  FIG.  32   , the page data PG 0  is written to the lower page of the selected cell unit CUs 00  in the plane PB 0  of the memory device MC 0 . The page data PG 1  is written to the middle page of the selected cell unit CUs 01  in the plane PB 1  of the memory device MC 0 . The page data PG 2  is written to the upper page of the selected cell unit CUs 10  in the plane PB 0  of the memory device MC 1 . The page data PG 3  is written to the top page of the selected cell unit CUs 11  in the plane PB 1  of the memory device MC 1 . 
     The page data PG 4  is written to the lower page of the selected cell unit CUs 01  in the plane PB 1  of the memory device MC 0 . The page data PG 5  is written to the middle page of the selected cell unit CUs 00  in the plane PB 0  of the memory device MC 0 . The page data PG 6  is written to the upper page of the selected cell unit CUs 11  in the plane PB 1  of the memory device MC 1 . The page data PG 7  is written to the top page of the selected cell unit CUs 10  in the plane PB 0  of the memory device MC 1 . 
     The page data PG 8  is written to the lower page of the selected cell unit CUs 10  in the plane PB 0  of the memory device MC 1 . The page data PG 9  is written to the middle page of the selected cell unit CUs 11  in the plane PB 1  of the memory device MC 1 . The page data PG 10  is written to the upper page of the selected cell unit CUs 01  in the plane PB 1  of the memory device MC 0 . The page data PG 11  is written to the top page of the selected cell unit CUs 00  in the plane PB 0  of the memory device MC 0 . 
     The page data PG 12  is written to the lower page of the selected cell unit CUs 11  in the plane PB 1  of the memory device MC 1 . The page data PG 13  is written to the middle page of the selected cell unit CUs 10  in the plane PB 0  of the memory device MC 1 . The page data PG 14  is written to the upper page of the selected cell unit CUs 00  in the plane PB 0  of the memory device MC 0 . The page data PG 15  is written to the top page of the selected cell unit CUs 01  in the plane PB 1  of the memory device MC 0 . 
     &lt;4.5. Advantages&gt; 
     According to the fourth embodiment, the  1248  mapping is used instead of the 4434 mapping in the second embodiment, but other than the features based on this point, the fourth embodiment has the same features as the second embodiment. The same advantages as the second embodiment are also obtained with the  1248  mapping. 
     Fifth Embodiment 
     The fifth embodiment is similar to the third embodiment, and is different from the third embodiment in the mapping. 
     The configuration of the memory system  100  and the memory devices MC according to the fifth embodiment is the same as that of the first embodiment. 
     In the fifth embodiment, the 1248 mapping is used like in the fourth embodiment. 
     &lt;5.1. Data Writes&gt; 
     In the fifth embodiment, like the third embodiment, each cell unit CU stores data of four pages in size, and the four pages include just one fast page. Based on this configuration, in the fifth embodiment, the memory area unit MA 3  spreads over four memory devices MC as in the third embodiment. 
       FIG.  33    illustrates an example of the memory area unit MA 3  and positions where page data are written in the memory devices MC according to the fifth embodiment. 
     For each of the cases where γ is 0, 4, 8, and 12, the page data PGγ, the page data PG(γ+1), the page data PG(γ+2), and the page data PG(γ+3) form a data set. 
     As illustrated in  FIG.  33   , the page data PGγ, PG(γ+1), PG(γ+2), and PG(γ+3) in each data set are written one by one to the memory devices MC 0  to MC 3 , and one of the page data PGγ, PG(γ+1), PG(γ+2), and PG(γ+3) is written to a fast page (lower page) while the remaining three are written to non-fast pages. In addition, each piece of page data PG included in a data set and written to a non-fast page is written to any of the middle, upper, and top pages. Furthermore, the pages to which the page data PG 0  to PG 15  are written are determined such that four data sets are written to the memory area unit MA 3 . Insofar as writes are performed in this way, the positions where the page data PG 0  to PG 15  are written are not limited to the example in  FIG.  33   . As an example, the page data written to the non-fast pages can be written to different one of middle, upper, and top pages. 
     As illustrated in  FIG.  33   , the page data PG 0  is written to the lower page of the selected cell unit CUs 0   w  of the memory device MC 0 . The page data PG 1  is written to the middle page of the selected cell unit CUs 1   w  of the memory device MC 1 . The page data PG 2  is written to the upper page of the selected cell unit CUs 2   w  of the memory device MC 2 . The page data PG 3  is written to the top page of the selected cell unit CUs 3   w  of the memory device MC 3 . 
     The page data PG 4  is written to the lower page of the selected cell unit CUs 1   w  of the memory device MC 1 . The page data PG 5  is written to the middle page of the selected cell unit CUs 2   w  of the memory device MC 2 . The page data PG 6  is written to the upper page of the selected cell unit CUs 3   w  of the memory device MC 3 . The page data PG 7  is written to the top page of the selected cell unit CUs 0   w  of the memory device MC 0 . 
     The page data PG 8  is written to the lower page of the selected cell unit CUs 2   w  of the memory device MC 2 . The page data PG 9  is written to the middle page of the selected cell unit CUs 3   w  of the memory device MC 3 . The page data PG 10  is written to the upper page of the selected cell unit CUs 0   w  of the memory device MC 0 . The page data PG 11  is written to the top page of the selected cell unit CUs 1   w  of the memory device MC 1 . 
     The page data PG 12  is written to the lower page of the selected cell unit CUs 3   w  of the memory device MC 3 . The page data PG 13  is written to the middle page of the selected cell unit CUs 0   w  of the memory device MC 0 . The page data PG 14  is written to the upper page of the selected cell unit CUs 1   w  of the memory device MC 1 . The page data PG 15  is written to the top page of the selected cell unit CUs 2   w  of the memory device MC 2 . 
     &lt;5.2. Data reads&gt; 
     Data reads follow the basic principle described for the other embodiments, and particularly resembles the third embodiment. In other words, data are read in parallel for each data set, and a data read from any of the non-fast pages proceeds in parallel with a data read of a fast page (lower page). 
     To read the data set containing the page data PG 0  to PG 3 , the memory controller  2  first instructs the memory device MC 0  to read the page data PG 0  stored in the fast page. Next, the memory controller  2  instructs the memory device MC 1  to perform a middle page read for the page data PG 1 , instructs the memory device MC 2  to perform an upper page read for the page data PG 2 , and instructs the memory device MC 3  to perform a top page read for the page data PG 3 . 
     When the read of the page data PG 0  is completed, the memory device MC 0  outputs the page data PG 0  in accordance with the instruction from the memory controller  2 . While the memory device MC 0  is outputting the page data PG 0 , the middle page read in the memory device MC 1 , the upper page read in the memory device MC 2 , and the top page read in the memory device MC 3  can proceed. 
     Thereafter, the memory controller  2  similarly reads the data set containing the page data PG 4  to PG 7 , reads the data set containing the page data PG 8  to PG 11 , and reads the data set containing the page data PG 12  to PG 15 . For reading any of the data sets, a data read from the fast page of each data set is started first, and after that, data reads from the non-fast pages are started. 
     &lt;5.3. Advantages&gt; 
     According to the fifth embodiment, the  1248  mapping is used instead of the  4434  mapping in the third embodiment, but other than the features based on this point, the fifth embodiment has the same features as the third embodiment. The same advantages as the third embodiment are also obtained with the  1248  mapping. 
     &lt;5.4. Modification&gt; 
     Like the modification of the third embodiment, the fifth embodiment may also be applied to multi-plane operations in which independent operation is unavailable. In this modification, like the modification of the third embodiment, the memory area unit MA 3   a  is used. Hereinafter, the features that differ from the modification of the third embodiment will be described mainly. 
       FIG.  34    illustrates an example of positions where page data are written in the memory devices MC according to the modification of the fifth embodiment. For each of the cases where γ is 0, 4, 8, and 12, the page data PGγ, the page data PG(γ+1), the page data PG(γ+2), the page data PG(γ+3), the page data PG(γ+4), the page data PG(γ+5), the page data PG(γ+6), and the page data PG(γ+7) form a data set. 
     As illustrated in  FIG.  34   , the page data PG 0  is written to the lower page of the selected cell unit CUs 00  in the plane PB 0  of the memory device MC 0 . The page data PG 1  is written to the lower page of the selected cell unit CUs 01  in the plane PB 1  of the memory device MC 0 . 
     The page data PG 2  is written to the middle page of the selected cell unit CUs 10  in the plane PB 0  of the memory device MC 1 . The page data PG 3  is written to the middle page of the selected cell unit CUs 11  in the plane PB 1  of the memory device MC 1 . 
     The page data PG 4  is written to the upper page of the selected cell unit CUs 20  in the plane PB 0  of the memory device MC 2 . The page data PG 5  is written to the upper page of the selected cell unit CUs 21  in the plane PB 1  of the memory device MC 2 . 
     The page data PG 6  is written to the top page of the selected cell unit CUs 30  in the plane PB 0  of the memory device MC 3 . The page data PG 7  is written to the top page of the selected cell unit CUs 31  in the plane PB 1  of the memory device MC 3 . 
     The page data PG 8  is written to the lower page of the selected cell unit CUs 10  in the plane PB 0  of the memory device MC 1 . The page data PG 9  is written to the lower page of the selected cell unit CUs 11  in the plane PB 1  of the memory device MC 1 . 
     The page data PG 10  is written to the middle page of the selected cell unit CUs 20  in the plane PB 0  of the memory device MC 2 . The page data PG 11  is written to the middle page of the selected cell unit CUs 21  in the plane PB 1  of the memory device MC 2 . 
     The page data PG 12  is written to the upper page of the selected cell unit CUs 30  in the plane PB 0  of the memory device MC 3 . The page data PG 13  is written to the upper page of the selected cell unit CUs 31  in the plane PB 1  of the memory device MC 3 . 
     The page data PG 14  is written to the top page of the selected cell unit CUs 00  in the plane PB 0  of the memory device MC 0 . The page data PG 15  is written to the top page of the selected cell unit CUs 01  in the plane PB 1  of the memory device MC 0 . 
     The page data PG 16  is written to the lower page of the selected cell unit CUs 20  in the plane PB 0  of the memory device MC 2 . The page data PG 17  is written to the lower page of the selected cell unit CUs 21  in the plane PB 1  of the memory device MC 2 . 
     The page data PG 18  is written to the middle page of the selected cell unit CUs 30  in the plane PB 0  of the memory device MC 3 . The page data PG 19  is written to the middle page of the selected cell unit CUs 31  in the plane PB 1  of the memory device MC 3 . 
     The page data PG 20  is written to the upper page of the selected cell unit CUs 00  in the plane PB 0  of the memory device MC 0 . The page data PG 21  is written to the upper page of the selected cell unit CUs 01  in the plane PB 1  of the memory device MC 0 . 
     The page data PG 22  is written to the top page of the selected cell unit CUs 10  in the plane PB 0  of the memory device MC 1 . The page data PG 23  is written to the top page of the selected cell unit CUs 11  in the plane PB 1  of the memory device MC 1 . 
     The page data PG 24  is written to the lower page of the selected cell unit CUs 30  in the plane PB 0  of the memory device MC 3 . The page data PG 25  is written to the lower page of the selected cell unit CUs 31  in the plane PB 1  of the memory device MC 3 . 
     The page data PG 26  is written to the middle page of the selected cell unit CUs 00  in the plane PB 0  of the memory device MC 0 . The page data PG 27  is written to the middle page of the selected cell unit CUs 01  in the plane PB 1  of the memory device MC 0 . 
     The page data PG 28  is written to the upper page of the selected cell unit CUs 10  in the plane PB 0  of the memory device MC 1 . The page data PG 29  is written to the upper page of the selected cell unit CUs 11  in the plane PB 1  of the memory device MC 1 . 
     The page data PG 30  is written to the top page of the selected cell unit CUs 20  in the plane PB 0  of the memory device MC 2 . The page data PG 31  is written to the top page of the selected cell unit CUs 21  in the plane PB 1  of the memory device MC 2 . 
     For data reads, the basic principle is the same as data reads according to the fifth embodiment, the difference being that pairs of page data PG are read in parallel, like the modification of the third embodiment. 
     Sixth Embodiment 
     The sixth embodiment resembles the third embodiment. In the sixth embodiment, each memory device MC stores three bits of data per memory cell transistor MT. 
     The configuration of the memory system  100  and the memory devices MC according to the sixth embodiment is the same as that of the third embodiment. 
     &lt;6.1. Mapping&gt; 
     In the sixth embodiment, a  133  mapping is used. The notation “HIJ mapping” indicates that H, I, and J read voltages VCGR are used for the lower, middle, and upper page reads, respectively. 
       FIG.  35    illustrates a mapping between a threshold voltage distribution of memory cell transistors MT that store three bits of data per memory cell transistor MT and data according to the sixth embodiment. As illustrated in  FIG.  35   , in the sixth embodiment, each memory device MC treats each state as having the following three-bit data. In the following “ABC” notation, A, B, and C represent the values of the upper, middle, and lower bits, respectively.
     “0” State: “111”   “1” State: “101”   “2” State: “001”   “3” State: “011”   “4” State: “010”   “5” State: “110”   “6” State: “100”   “7” State: “000”   

     In the  133  mapping, the data of each page is determined using the following read voltages.
     Lower page read: 4R   Middle page read: 1R, 3R, and 6R   Upper page read: 2R, 5R, and 7R   

     In the  133  mapping, the lower page corresponds to the fast page, while the middle page and the upper page correspond to non-fast pages. 
     &lt;6.2. Data Writes&gt; 
     In the sixth embodiment, each cell unit CU stores data of three pages in size, and the three pages include just one fast page. Based on this configuration, in the sixth embodiment, the memory area unit MA needs to spread over three independently operable planes PB. In the sixth embodiment, the planes PB 0  and PB 1  in each memory device MC cannot operate independently. For this reason, the memory area unit MA needs to spread over three memory devices MC. 
     To this end, the memory area unit MA according to the sixth embodiment spreads over a plane PB of the memory device MC 0 , a plane PB of the memory device MC 1 , and a plane PB of the memory device MC 2 . The memory area unit MA according to the sixth embodiment is referred to as the memory area unit MA 4 . 
       FIG.  36    illustrates an example of the memory area unit MA 4  and positions where page data are written in the memory devices MC according to the sixth embodiment. As illustrated in  FIG.  36   , the memory area unit MA 4  is the set of the lower, middle, and upper pages of a cell unit CUs 0   w  in a plane PBw of the memory device MC 0 , the lower, middle, and upper pages of a cell unit CUs 1   w  in a plane PBw of the memory device MC 1 , and the lower, middle, and upper pages of a cell unit CUs 2   w  in a plane PBw of a memory device MC 2 . 
     Based on such features of the memory area unit MA 4 , nine pieces of page data PG with consecutive logical addresses are stored in a single memory area unit MA 4 . As a specific example,  FIG.  36    illustrates the positions where nine pieces of page data PG 0  to PG 8  with consecutive logical addresses are written in the memory area unit MA 4 . 
     For each of the cases where y is  0 ,  3 , and  6 , the page data PGγ, the page data PG(γ+1), and the page data PG(γ+2) form a data set. 
     As illustrated in  FIG.  36   , the page data PGγ, PG(γ+1), and PG(γ+2) in each data set are written one by one to the memory devices MC 0  to MC 2 , and in addition, one of the page data PGγ, PG(γ+1), and PG(γ+2) is written to a fast page while the remaining two are written to non-fast pages. Also, the page data included in a data set and written to a non-fast page is written to any of the middle and upper pages. Furthermore, the pages to which the page data PG 0  to PG 8  are written are determined such that three data sets are written to the memory area unit MA 4 . Insofar as writes are performed in this way, the positions where the page data PG 0  to PG 8  are written is not limited to the example in  FIG.  36   . As an example, the page data written to the non-fast pages are written to different one of middle and upper pages. 
     As illustrated in  FIG.  36   , the page data PG 0  is written to the lower page of the selected cell unit CUs 0   w  of the memory device MC 0 . The page data PG 1  is written to the middle page of the selected cell unit CUs 1   w  of the memory device MC 1 . The page data PG 2  is written to the upper page of the selected cell unit CUs 2   w  of the memory device MC 2 . 
     The page data PG 3  is written to the lower page of the selected cell unit CUs 1   w  of the memory device MC 1 . The page data PG 4  is written to the middle page of the selected cell unit CUs 2   w  of the memory device MC 2 . The page data PG 5  is written to the upper page of the selected cell unit CUs 0   w  of the memory device MC 0 . 
     The page data PG 6  is written to the lower page of the selected cell unit CUs 2   w  of the memory device MC 2 . The page data PG 7  is written to the middle page of the selected cell unit CUs 0   w  of the memory device MC 0 . The page data PG 8  is written to the upper page of the selected cell unit CUs 1   w  of the memory device MC 1 . 
     &lt;6.3. Data Reads&gt; 
       FIGS.  37  and  38    illustrate the flow of the input and output signal DQ during data reads over time in the memory system  100  according to the sixth embodiment.  FIG.  38    illustrates the state following  FIG.  37   . 
     As illustrated in  FIGS.  37  and  38   , a data read from any of the non-fast pages proceeds in parallel with a data read of a fast page (lower page). 
     To read the data set containing the page data PG 0  to PG 2 , the memory controller  2  first instructs the memory device MC 0  to read the page data PG 0  stored in the fast page. The memory device MC 0  receives the instruction and starts a lower page read of the memory device MC 0  for obtaining the page data PG 0 . Next, the memory controller  2  instructs the memory device MC 1  to perform a middle page read for the page data PG 1 , and instructs the memory device MC 2  to perform an upper page read for the page data PG 2 . The lower page read in the memory device MC 0 , the middle page read in the memory device MC 1 , and the upper page read in the memory device MC 2  proceed in parallel. 
     When the read of the page data PG 0  is completed, the memory device MC 0  outputs the page data PG 0  in accordance with the instruction from the memory controller  2 . While the memory device MC 0  is outputting the page data PG 0 , the middle page read in the memory device MC 1  and the upper page read in the memory device MC 2  can proceed. 
     Thereafter, the memory controller  2  similarly reads the data set containing the page data PG 3  to PG 5 , and reads the data set containing the page data PG 6  to PG 8 . For reading any of the data sets, a data read from the fast page of each data set is started first, and after that, data reads from the non-fast pages are started. Thus, in each data set, a lower page read, a middle page read, and an upper page read proceed in parallel over the memory devices MC 0 , MC 1 , and MC 2 . 
     &lt;6.4. Another Example of Mapping&gt; 
     In the sixth embodiment, other mappings may be used. Such mappings include a  124  mapping.  FIG.  39    illustrates a second example of a mapping between a threshold voltage distribution of memory cell transistors MT that store three bits of data per memory cell transistor MT and data according to the sixth embodiment. As illustrated in  FIG.  39   , in the second example, each memory device MC treats each state as having the following three-bit data.
     “0” State: “111”   “1” State: “011”   “2” State: “001”   “3” State: “101”   “4” State: “100”   “5” State: “000”   “6” State: “010”   “7” State: “110”   

     In the  124  mapping, the data of each page is determined using the following read voltages.
     Lower page read: 4R   Middle page read: 2R and 6R   Upper page read: 1R, 3R, 5R, and 7R   

     Also in the  124  mapping, the lower page corresponds to the fast page, while the middle page and the upper page correspond to non-fast pages. 
     Data writes and reads are the same as for the  133  mapping, the difference being only in the time taken for the middle page read and the upper page read. 
     &lt;6.5. Advantages&gt; 
     According to the sixth embodiment, the memory area unit MA 4  spreads over three memory devices MC, first page data out of a data set containing three pieces of page data having three consecutive logical addresses is written to a fast page (lower page), while the remaining page data are written to different pages than the page where the first page data is written from among the lower, middle, and upper pages. During reads of a data set written in this way, reads of the page data other than the first page data of the data set can proceed while the first page data is being output. For this reason, even in the case of storing three bits of data per memory cell transistor MT, data can be read and output efficiently according to the same basic principle as the first embodiment. 
     &lt;6.6. Modification&gt; 
     Like the modification of the third embodiment, the sixth embodiment may also be applied to multi-plane operations in which independent operation is unavailable. 
     In this modification, a memory area unit MA 4 a is used. The memory area unit MA 4 a according to a modification of the sixth embodiment spreads over the planes PB 0  and PB 1  of the memory device MC 0 , the planes PB 0  and PB 1  of the memory device MC 1 , and the planes PB 0  and PB 1  of the memory device MC 2 . 
       FIG.  40    illustrates an example of the memory area unit MA 4 a and positions where page data are written in the memory devices MC according to the modification of the sixth embodiment. For each of the cases where γ is 0, 6, and 12, the page data PGγ, the page data PG(γ+1), the page data PG(γ+2), the page data PG(γ+3), the page data PG(γ+4), and the page data PG(γ+5) form a data set. 
     As illustrated in  FIG.  40   , the page data PG 0  is written to the lower page of the selected cell unit CUs 00  in the plane PB 0  of the memory device MC 0 . The page data PG 1  is written to the lower page of the selected cell unit CUs 01  in the plane PB 1  of the memory device MC 0 . 
     The page data PG 2  is written to the middle page of the selected cell unit CUs 10  in the plane PB 0  of the memory device MC 1 . The page data PG 3  is written to the middle page of the selected cell unit CUs 11  in the plane PB 1  of the memory device MC 1 . 
     The page data PG 4  is written to the upper page of the selected cell unit CUs 20  in the plane PB 0  of the memory device MC 2 . The page data PG 5  is written to the upper page of the selected cell unit CUs 21  in the plane PB 1  of the memory device MC 2 . 
     The page data PG 6  is written to the lower page of the selected cell unit CUs 10  in the plane PB 0  of the memory device MC 1 . The page data PG 7  is written to the lower page of the selected cell unit CUs 11  in the plane PB 1  of the memory device MC 1 . 
     The page data PG 8  is written to the middle page of the selected cell unit CUs 20  in the plane PB 0  of the memory device MC 2 . The page data PG 9  is written to the middle page of the selected cell unit CUs 21  in the plane PB 1  of the memory device MC 2 . 
     The page data PG 10  is written to the upper page of the selected cell unit CUs 00  in the plane PB 0  of the memory device MC 0 . The page data PG 11  is written to the upper page of the selected cell unit CUs 01  in the plane PB 1  of the memory device MC 0 . 
     The page data PG 12  is written to the lower page of the selected cell unit CUs 20  in the plane PB 0  of the memory device MC 2 . The page data PG 13  is written to the lower page of the selected cell unit CUs 21  in the plane PB 1  of the memory device MC 2 . 
     The page data PG 14  is written to the middle page of the selected cell unit CUs 00  in the plane PB 0  of the memory device MC 0 . The page data PG 15  is written to the middle page of the selected cell unit CUs 01  in the plane PB 1  of the memory device MC 0 . 
     The page data PG 16  is written to the upper page of the selected cell unit CUs 10  in the plane PB 0  of the memory device MC 1 . The page data PG 17  is written to the upper page of the selected cell unit CUs 11  in the plane PB 1  of the memory device MC 1 . 
     For data reads, the basic principle is the same as data reads according to the sixth embodiment, the difference being that pairs of page data PG are read in parallel, like the modification of the fifth embodiment. 
     The modification may also be applied to the  124  mapping. 
     Seventh Embodiment 
     The seventh embodiment resembles the first embodiment and the sixth embodiment. In the seventh embodiment, like the sixth embodiment, each memory device MC stores three bits of data per memory cell transistor MT. 
     The configuration of the memory system  100  and the memory devices MC according to the seventh embodiment is the same as that of the first embodiment. 
     &lt;7.1. Data Writes&gt; 
     In the seventh embodiment, like the sixth embodiment, the  133  mapping or the  124  mapping is used, and the memory area unit MA needs to spread over three independently operable planes PB. To this end, the memory area unit MA according to the seventh embodiment spreads over the plane PB 0  of the memory device MC 0 , the plane PB 1  of the memory device MC 0 , and any plane PB (for example, PB 0 ) of the memory device MC 1 . The memory area unit MA according to the seventh embodiment is referred to as the memory area unit MA 5 . 
       FIG.  41    illustrates an example of the memory area unit MA 5  and positions where page data are written in the memory devices MC according to the seventh embodiment. As illustrated in  FIG.  41   , the memory area unit MA 5  is the set of the lower, middle, and upper pages of the cell unit CUs 00  in the plane PB 0  of the memory device MC 0 , the lower, middle, and upper pages of the cell unit CUs 01  in the plane PB 1  of the memory device MC 0 , and the lower, middle, and upper pages of the cell unit CUs 10  in the plane PB 0  for example of the memory device MC 1 . 
     The page data PG 0  is written to the lower page of the selected cell unit CUs 00  in the plane PB 0  of the memory device MC 0 . The page data PG 1  is written to the middle page of the selected cell unit CUs 01  in the plane PB 1  of the memory device MC 0 . The page data PG 2  is written to the upper page of the selected cell unit CUs 10  in the plane PB 0  of the memory device MC 1 . 
     The page data PG 3  is written to the lower page of the selected cell unit CUs 01  in the plane PB 1  of the memory device MC 0 . The page data PG 4  is written to the middle page of the selected cell unit CUs 10  in the plane PB 0  of the memory device MC 1 . The page data PG 5  is written to the upper page of the selected cell unit CUs 00  in the plane PB 0  of the memory device MC 0 . 
     The page data PG 6  is written to the lower page of the selected cell unit CUs 10  in the plane PB 0  of the memory device MC 1 . The page data PG 7  is written to the middle page of the selected cell unit CUs 00  in the plane PB 0  of the memory device MC 0 . The page data PG 8  is written to the upper page of the selected cell unit CUs 01  in the plane PB 1  of the memory device MC 0 . 
     &lt;7.2. Data Reads&gt; 
     Data reads follow the basic principle described for the other embodiments, and particularly resembles the sixth embodiment. In other words, data are read in parallel for each data set, and a data read from any of the non-fast pages proceeds in parallel with a data read of a fast page (lower page). A feature that differs from the sixth embodiment is that the command set for data reads is different on the basis of three independent planes PB that store the three pieces of page data PG of a data set spreading over two memory devices MC. 
     &lt;7.3. Advantages&gt; 
     According to the seventh embodiment, the memory area unit MA 5  spreads over two memory devices MC, and, like the sixth embodiment, first page data out of a data set containing three pieces of page data having three consecutive logical addresses is written to a fast page (lower page), while the remaining page data are written to different pages than the page where the first page data is written from among the lower, middle, and upper pages. Therefore, like the sixth embodiment, even in the case of storing three bits of data per memory cell transistor MT, data can be read and output efficiently according to the same basic principle as the first embodiment. 
     &lt;7.4. Modification&gt; 
     The memory area unit MA may also be formed over six planes PB with three memory devices MC. This modification relates to such an example. 
     In this modification, a memory area unit MA 6  is used. The memory area unit MA 6  spreads over the planes PB 0  and PB 1  of the memory device MC 0 , the planes PB 0  and PB 1  of the memory device MC 1 , and the planes PB 0  and PB 1  of the memory device MC 2 . 
       FIG.  42    illustrates an example of the memory area unit MA 6  and positions where page data are written in the memory devices MC according to the modification of the seventh embodiment. As illustrated in  FIG.  42   , the memory area unit MA 6  is the set of the lower, middle, and upper pages of a cell unit CUs 00  in a plane PB 0  of a memory device MC 0 , the lower, middle, and upper pages of a cell unit CUs 01  in a plane PB 1  of the memory device MC 0 , the lower, middle, and upper pages of a cell unit CUs 10  in a plane PB 0  of a memory device MC 1 , the lower, middle, and upper pages of a cell unit CUs 11  in a plane PB 1  of the memory device MC 1 , the lower, middle, and upper pages of a cell unit CUs 20  in a plane PB 0  of a memory device MC 2 , and the lower, middle, and upper pages of a cell unit CUs 21  in a plane PB 1  of the memory device MC 2 . 
     The page data PG 0  is written to the lower page of the selected cell unit CUs 00  in the plane PB 0  of the memory device MC 0 . The page data PG 1  is written to the middle page of the selected cell unit CUs 01  in the plane PB 1  of the memory device MC 0 . The page data PG 2  is written to the upper page of the selected cell unit CUs 10  in the plane PB 0  of the memory device MC 1 . 
     The page data PG 3  is written to the lower page of the selected cell unit CUs 11  in the plane PB 1  of the memory device MC 1 . The page data PG 4  is written to the middle page of the selected cell unit CUs 20  in the plane PB 0  of the memory device MC 2 . The page data PG 5  is written to the upper page of the selected cell unit CUs 21  in the plane PB 1  of the memory device MC 2 . 
     The page data PG 6  is written to the lower page of the selected cell unit CUs 01  in the plane PB 1  of the memory device MC 0 . The page data PG 7  is written to the middle page of the selected cell unit CUs 10  in the plane PB 0  of the memory device MC 1 . The page data PG 8  is written to the upper page of the selected cell unit CUs 11  in the plane PB 1  of the memory device MC 1 . 
     The page data PG 9  is written to the lower page of the selected cell unit CUs 20  in the plane PB 0  of the memory device MC 2 . The page data PG 10  is written to the middle page of the selected cell unit CUs 21  in the plane PB 1  of the memory device MC 2 . The page data PG 11  is written to the upper page of the selected cell unit CUs 00  in the plane PB 0  of the memory device MC 0 . 
     The page data PG 12  is written to the lower page of the selected cell unit CUs 10  in the plane PB 0  of the memory device MC 1 . The page data PG 13  is written to the middle page of the selected cell unit CUs 11  in the plane PB 1  of the memory device MC 1 . The page data PG 14  is written to the upper page of the selected cell unit CUs 20  in the plane PB 0  of the memory device MC 2 . 
     The page data PG 15  is written to the lower page of the selected cell unit CUs 21  in the plane PB 1  of the memory device MC 2 . The page data PG 16  is written to the middle page of the selected cell unit CUs 00  in the plane PB 0  of the memory device MC 0 . The page data PG 17  is written to the upper page of the selected cell unit CUs 01  in the plane PB 1  of the memory device MC 0 . 
     Eighth Embodiment 
     The eighth embodiment resembles the first embodiment and the sixth embodiment, and relates to an example in which each memory device MC includes three independently operable planes PB. In the eighth embodiment, like the sixth embodiment, each memory device MC stores three bits of data per memory cell transistor. 
     The configuration of the memory system  100  and the memory devices MC according to the eighth embodiment is the same as that of the first embodiment, except that the memory devices MC include three planes PB. Hereinafter, the features that differ from the sixth embodiment will be described mainly. 
     &lt;8.1. Configuration of Memory Devices&gt; 
     Each memory device MC includes a plane PB 2  in addition to the components and connections illustrated in  FIG.  3   . The plane PB 2  is independent from the planes PB 0  and PB 1 , and can execute data read, write, and erase operations independently. To this end, the plane PB 2  includes a memory cell array  13 _ 2 , a potential generator  14 _ 2 , a driver  15 _ 2 , a sense amplifier  16 _ 2 , and a row decoder  17 _ 2  (not illustrated). The memory cell array  13 _ 2 , the potential generator  14 _ 2 , the driver  15 _ 2 , the sense amplifier  16 _ 2 , and the row decoder  17 _ 2  include the same components and connections as the memory cell array  13 _ 0 , the potential generator  14 _ 0 , the driver  15 _ 0 , the sense amplifier  16 _ 0 , and the row decoder  17 _ 0  of the plane PB 0 , respectively. 
     &lt;8.2. Data Writes&gt; 
     In the eighth embodiment, like the sixth embodiment, the  133  mapping or the  124  mapping is used, and the memory area unit MA needs to spread over three independently operable planes PB. To this end, the memory area unit MA according to the eighth embodiment spreads over the plane PB 0  of a certain memory device MCw, the plane PB 1  of the memory device MCw, and the plane PB 2  of the memory device MCw. The memory area unit MA according to the eighth embodiment is referred to as the memory area unit MA 7 . 
       FIG.  43    illustrates an example of the memory area unit MA 7  and positions where page data are written in the memory device MC according to the eighth embodiment, and illustrates the memory device MC 0  as an example. As illustrated in  FIG.  43   , the memory area unit MA 7  is the set of the lower, middle, and upper pages of the cell unit CUs 00  in the plane PB 0  of the memory device MC 0 , the lower, middle, and upper pages of the cell unit CUs 01  in the plane PB 1  of the memory device MC 0 , and the lower, middle, and upper pages of a cell unit CUs 02  in the plane PB 2  of the memory device MC 0 . 
     The page data PG 0  is written to the lower page of the selected cell unit CUs 00  in the plane PB 0  of the memory device MC 0 . The page data PG 1  is written to the middle page of the selected cell unit CUs 01  in the plane PB 1  of the memory device MC 0 . The page data PG 2  is written to the upper page of the selected cell unit CUs 02  in the plane PB 2  of the memory device MC 0 . 
     The page data PG 3  is written to the lower page of the selected cell unit CUs 01  in the plane PB 1  of the memory device MC 0 . The page data PG 4  is written to the middle page of the selected cell unit CUs 02  in the plane PB 2  of the memory device MC 0 . The page data PG 5  is written to the upper page of the selected cell unit CUs 00  in the plane PB 0  of the memory device MC 0 . 
     The page data PG 6  is written to the lower page of the selected cell unit CUs 02  in the plane PB 2  of the memory device MC 0 . The page data PG 7  is written to the middle page of the selected cell unit CUs 00  in the plane 
     PB 0  of the memory device MC 0 . The page data PG 8  is written to the upper page of the selected cell unit CUs 01  in the plane PB 1  of the memory device MC 0 . 
     &lt;8.3. Data Reads&gt; 
     Data reads follow the basic principle described for the other embodiments, and particularly resembles the sixth embodiment. In other words, data are read in parallel for each data set, and a data read from any of the non-fast pages proceeds in parallel with a data read of a fast page (lower page). A feature that differs from the sixth embodiment is that the command set for data reads is different on the basis of three independent planes PB that store the three pieces of page data of a data set being included in a single memory device MC. 
     &lt;8.4. Advantages&gt; 
     According to the eighth embodiment, the memory area unit MA 7  spreads over three independently operable planes PB in a single memory device MC, and, like the sixth embodiment, first page data out of a data set containing three pieces of page data having three consecutive logical addresses is written to a fast page (lower page), while the remaining page data are written to different pages than the page where the first page data is written from among the lower, middle, and upper pages. Therefore, like the sixth embodiment, even in the case of storing three bits of data per memory cell transistor MT, data can be read and output efficiently according to the same basic principle as the first embodiment. 
     Ninth Embodiment 
     The ninth embodiment resembles the first embodiment and the sixth embodiment. In the ninth embodiment, like the sixth embodiment, the memory devices MC store three bits of data per memory cell transistor. 
     The configuration of the memory system  100  and the memory devices MC according to the ninth embodiment is the same as that of the sixth embodiment. 
     &lt;9.1. Mapping&gt; 
     In the ninth embodiment, a  232  mapping is used.  FIG.  44    illustrates an example of a mapping between eight states of the memory cell transistors MT in the memory devices MC and three-bit data according to the ninth embodiment. As illustrated in  FIG.  44   , in the ninth embodiment, the memory devices MC treats each state as having the following three-bit data.
     “0” State: “111”   “1” State: “110”   “2” State: “100”   “3” State: “000”   “4” State: “010”   “5” State: “011”   “6” State: “001”   “7” State: “101”   

     In the  232  mapping, the data of each page is determined using the following read voltages.
     Lower page read: 1R and 5R   Middle page read: 2R, 4R, and 6R   Upper page read: 3R and 7R   

     In the  232  mapping, the lower page and the upper page correspond to fast pages, while the middle page corresponds to the non-fast page. 
     &lt;9.2. Data Writes&gt; 
     In the ninth embodiment, each cell unit CU stores data of three pages in size, and the three pages include two fast pages. Based on this configuration, in the ninth embodiment, the memory area unit MA needs to spread over three independently operable planes PB. Like the sixth embodiment, the memory area unit MA 4  is used. 
       FIG.  45    illustrates an example of positions where page data are written in the memory devices MC according to the ninth embodiment. 
     As illustrated in  FIG.  45   , the page data PG 0  is written to the upper page of the selected cell unit CUs 0   w  of the memory device MC 0 . The page data PG 1  is written to the lower page of the selected cell unit CUs 1   w  of the memory device MC 1 . The page data PG 2  is written to the middle page of the selected cell unit CUs 2   w  of the memory device MC 2 . 
     The page data PG 3  is written to the upper page of the selected cell unit CUs 1   w  of the memory device MC 1 . The page data PG 4  is written to the lower page of the selected cell unit CUs 2   w  of the memory device MC 2 . The page data PG 5  is written to the middle page of the selected cell unit CUs 0   w  of the memory device MC 0 . The page data PG 6  is written to the upper page of the selected cell unit CUs 2   w  of the memory device MC 2 . The page data PG 7  is written to the lower page of the selected cell unit CUs 0   w  of the memory device MC 0 . The page data PG 8  is written to the middle page of the selected cell unit CUs 1   w  of the memory device MC 1 . 
     The writes in  FIG.  45    are an example, are the lower page may also be used as the fast page. 
     &lt;9.3. Data Reads&gt; 
     Data reads follow the basic principle described for the other embodiments, and particularly resembles the sixth embodiment. In other words, data is read in parallel for each data set, and a data read from any of the non-fast pages proceeds in parallel with a data read of a fast page (lower or upper page). A feature that differs from the sixth embodiment is that the command set for data reads is different on the basis of three independent planes PB that store the three pieces of page data of a data set extending over three memory devices MC. 
     &lt;9.4. Advantages&gt; 
     According to the ninth embodiment, like the sixth embodiment, the memory area unit MA 4  spreads over three memory devices MC, first page data out of a data set containing three pieces of page data having three consecutive logical addresses is written to a fast page, while the remaining page data are written to different pages than the page where the first page data is written from among the lower, middle, and upper pages. Therefore, like the sixth embodiment, even in the case of storing three bits of data per memory cell transistor MT, data can be read and output efficiently according to the same basic principle as the first embodiment. 
     &lt;9.5. Modification&gt; 
     Like the modification of the sixth embodiment, the ninth embodiment may also be applied to multi-plane operations in which independent operation is unavailable. 
     10th Embodiment 
     The 10th embodiment resembles the eighth embodiment and the ninth embodiment, and relates to an example in which each memory device MC includes three independently operable planes. In the 10th embodiment, like the sixth embodiment, the memory devices MC store three bits of data per memory cell transistor. 
     The configuration of the memory system  100  and the memory devices MC according to the 10th embodiment is the same as the eighth embodiment. 
     &lt;10.1. Data Writing&gt; 
     In the 10th embodiment, the  232  mapping is used like the ninth embodiment, and the memory area unit MA 7  is used like the eighth embodiment. 
       FIG.  46    illustrates an example of positions where page data are written in the memory device MC according to the 10th embodiment, and illustrates the memory device MC 0  as an example. As illustrated in  FIG.  46   , the page data PG 0  is written to the upper page of the selected cell unit CUs 00  in the plane PB 0  of the memory device MC 0 . The page data PG 1  is written to the lower page of the selected cell unit CUs 01  in the plane PB 1  of the memory device MC 0 . The page data PG 2  is written to the middle page of the selected cell unit CUs 02  in the plane PB 2  of the memory device MC 0 . 
     The page data PG 3  is written to the upper page of the selected cell unit CUs 01  in the plane PB 1  of the memory device MC 0 . The page data PG 4  is written to the lower page of the selected cell unit CUs 02  in the plane PB 2  of the memory device MC 0 . The page data PG 5  is written to the middle page of the selected cell unit CUs 00  in the plane PB 0  of the memory device MC 0 . 
     The page data PG 6  is written to the upper page of the selected cell unit CUs 02  in the plane PB 2  of the memory device MC 0 . The page data PG 7  is written to the lower page of the selected cell unit CUs 00  in the plane PB 0  of the memory device MC 0 . The page data PG 8  is written to the middle page of the selected cell unit CUs 01  in the plane PB 1  of the memory device MC 0 . 
     &lt;10.2. Data Reads&gt; 
     Data reads follow the basic principle described for the other embodiments, and particularly resembles the sixth embodiment. In other words, data are read in parallel for each data set, and a data read from any of the non-fast pages proceed in parallel with a data read of a fast page (upper page). A feature that differs from the sixth embodiment is that the page read first in the reads of each data set is different. 
     &lt;10.3. Advantages&gt; 
     According to the 10th embodiment the memory area unit MA 7  spreads over three independently operable planes PB in a single memory device MC, and, like the sixth embodiment, first page data out of a data set containing three pieces of page data having three consecutive logical addresses is written to a fast page (upper page), while the remaining page data are written to different pages than the page where the first page data is written from among the lower, middle, and upper pages. Therefore, like the sixth embodiment, even in the case of storing three bits of data per memory cell transistor MT, data can be read and output efficiently according to the same basic principle as the first embodiment. 
     11th Embodiment&gt; 
     The 11th embodiment resembles the third embodiment. In the 11th embodiment, the memory devices MC store two bits of data per memory cell transistor. 
     The configuration of the memory system  100  and the memory devices MC according to the 11th embodiment is the same as that of the third embodiment. 
     &lt;11.1. Mapping&gt; 
     In the 11th embodiment, a 12 mapping is used. The notation “HI mapping” indicates that H and I read voltages VCGR are used for the lower and upper page reads, respectively. 
       FIG.  47    illustrates an example of a mapping between four states of the memory cell transistors MT in the memory devices MC and two-bit data according to the 11th embodiment. As illustrated in  FIG.  47   , in the 11th embodiment, the memory devices MC treat each state as having the following two-bit data.
     “0” State: “11”   “1” State: “10”   “2” State: “00”   “3” State: “01”   

     In the 12 mapping, the data of each page is determined using the following read voltages.
     Lower page read: 2R   Upper page read: 1R and 3R   

     In the 12 mapping, the lower page corresponds to the fast page, while the upper page corresponds to the non-fast page. 
     To designate pages with respect to the memory devices MC that store two-bit data per memory cell transistor MT like the 11th embodiment, the command  01   h  and the command  02   h  are used. The command  01   h  designates the lower page. The command  02   h  designates the lower page. 
     &lt;11.2. Data Writes&gt; 
     In the 11th embodiment, each cell unit CU stores data of two pages in size, and the two pages include just one fast page. Based on this configuration, in the 11th embodiment, the memory area unit MA needs to spread over two independently operable planes PB. In the 11th embodiment, the planes PB 0  and PB 1  in each memory device MC cannot operate independently. For this reason, the memory area unit MA needs to spread over two memory devices MC. 
     To this end, the memory area unit MA according to the 11th embodiment spreads over a plane PB of the memory device MC 0  and a plane PB of the memory device MC 1 . The memory area unit MA according to the 11th embodiment is referred to as the memory area unit MA 8 . 
       FIG.  48    illustrates an example of the memory area unit MA 8  and positions where page data are written in the memory devices MC according to the 11th embodiment. As illustrated in  FIG.  48   , the memory area unit MA 8  is the set of the lower and upper pages of a cell unit CUs 0   w  in a plane PBw of the memory device MC 0 , and the lower and upper pages of a cell unit CUs 1   w  in a plane PBw of the memory device MC 1 . 
     Based on such features of the memory area unit MA 8 , four pieces of page data with consecutive logical addresses are stored in a single memory area unit MA 8 . As a specific example,  FIG.  48    illustrates the positions where four pieces of write page data PG 0  to PG 3  with consecutive logical addresses are written in the memory area unit MA 8 . 
     For each of the cases where γ is 0 and 2, the page data PGy and the page data PG(γ+1) form a data set. 
     As illustrated in  FIG.  48   , the page data PGy and PG(γ+1) of each data set are written one by one to the memory devices MC 0  and MC 1 , and in addition, one of the page data PGy and PG(γ+1) is written to a fast page while the remaining one is written to a non-fast page. 
     As illustrated in  FIG.  48   , the page data PG 0  is written to the lower page of the selected cell unit CUs 0   w  of the memory device MC 0 . The page data PG 1  is written to the upper page of the selected cell unit CUs 1   w  of the memory device MC 1 . The page data PG 2  is written to the lower page of the selected cell unit CUs 0   w  of the memory device MC 1 . The page data PG 3  is written to the upper page of the selected cell unit CUs 0   w  of the memory device MC 0 . 
     &lt;11.3. Data Reads&gt; 
       FIG.  49    illustrates the flow of the input and output signal DQ during data reads over time in the memory system  100  according to the 11th embodiment. 
     As illustrated in  FIG.  49   , a data read from any of the non-fast pages proceeds in parallel with a data read of a fast page (lower page). 
     To read the data set containing the page data PG 0  and PG 1 , the memory controller  2  first instructs the memory device MC 0  to read the page data PG 0  stored in the fast page. The memory device MC 0  receives the instruction and starts a lower page read of the memory device MC 0  for obtaining the page data PG 0 . Next, the memory controller  2  instructs the memory device MC 1  to perform an upper page read for the page data PG 1 . The lower page read in the memory device MC 0  and the upper page read in the memory device MC 1  proceed in parallel. 
     When the read of the page data PG 0  is completed, the memory device MC 0  outputs the page data PG 0  in accordance with the instruction from the memory controller  2 . While the memory device MC 0  is outputting the page data PG 0 , the upper page read in the memory device MC 1  can proceed. 
     Thereafter, the memory controller  2  similarly reads the data set containing the page data PG 2  and PG 3 . For reading any of the data sets, a data read from the fast page of each data set is started first, and after that, data reads from the non-fast pages are started. Thus, in each data set, a lower page read and an upper page read proceed in parallel over the memory devices MC 0  and MC 1 . 
     &lt;11.4. Advantages&gt; 
     According to the 11th embodiment, the memory area unit MA 8  spreads over two memory devices MC, first page data out of a data set containing two pieces of page data having two consecutive logical addresses is written to a fast page, while the remaining page data is written to a non-fast page. During reads of a data set written in this way, a read of the page data PG other than the first page data of the data set can proceed while the first page data is being output. For this reason, even in the case of storing two bits of data per memory cell transistor MT, data can be read and output efficiently according to the same basic principle as the first embodiment. 
     &lt;11.5. Modification&gt; 
     The 11th embodiment may also be applied to independently operable planes PB 0  and PB 1  in a single memory device MC. In other words, the memory device MC has the same configuration as the first embodiment, the memory area unit MA spreads over the planes PB 0  and PB 1  of a single memory device MC 0  for example, and is the set of the lower and upper pages of the plane PB 0  and the lower and upper pages of the plane PB 1 . 
     12th Embodiment 
     The 12th embodiment relates to another configuration for achieving data writes according to the 11th embodiment. Hereinafter, the features that differ from the 11th embodiment will be described mainly. 
     The configuration of the memory system  100  according to the 12th embodiment is the same as the first embodiment. 
     &lt;12.1. Configuration of Memory Devices&gt; 
       FIG.  50    illustrates functional blocks of the memory devices MC according to the 12th embodiment. As illustrated in  FIG.  50   , each memory device MC includes an address converter  18  in addition to the components and connections according to the first embodiment ( FIG.  3   ). The memory devices MC according to the 12th embodiment may be referred to as the memory devices MCb in some cases. 
     The address converter  18  receives an address signal from the input and output circuit  11 , and converts a certain portion of the address signal, namely the portion indicating the address for a certain element, to a different address according to a predetermined rule. The portions other than the portion to be converted are output unchanged by the address converter  18 . The output from the address converter  18  is supplied to components such as the sequencer  12 , the row decoder  17 , and the sense amplifier  16 . 
       FIG.  51    illustrates components and connections in the address converter  18  according to the 12th embodiment. As illustrated in  FIG.  51   , the address converter  18  includes selectors S 1  and S 2 . 
     Each of the selectors S 1  and S 2  includes a first input node, a second input node, a control input node, and an output node. Each of the first input node and the second input node is associated with a one-bit value. The first input node is associated with “0”, and the second input node is associated with “1”. Hereinafter, the first input node may be referred to as the “0” input node, while the second input node may be referred to as the “1” input node in some cases. 
     Each of the selectors S 1  and S 2  receives a signal CHIP_ADD&lt;0&gt; at the control input node, where &lt;0&gt;indicates that the signal of the preceding name has one bit (the “0th” bit). The signal CHIP_ADD&lt;0&gt; has the identification (ID) of the memory device MC that includes the address converter  18 , or in other words, a value based on a unique number that specifies one from among all of the memory devices MC included in the memory system  100 . For example, the signal CHIP_ADD&lt;0&gt;has the value “0” in the memory device MC 0  and the signal CHIP_ADD&lt;0&gt; has the value “1” in the memory device MC 1 . 
     The selector S 1  receives a signal Lower_SEL_pre at the “0” input node. The signal Lower_SEL_pre is supplied from the input and output circuit  11  for example, and is asserted when the command  01   h,  which designates the lower page, is received by the memory device MC. The signal Lower_SEL_pre is used to generate a signal informing the sequencer  12  of the page targeted by the process instructed by the command set following the command  01   h,  or in other words the command set associated with the command  01   h.  In other words, when the command  01   h  is received, a signal designating the page targeted by the command set associated with the command  01   h  is generated, and the generated signal is supplied to the sequencer  12 . 
     The selector S 1  receives a signal Upper_SEL_pre at the “1” input node. The signal Upper_SEL_pre is supplied from the input and output circuit  11  for example, and is asserted when the command  02   h,  which designates the upper page, is received by the memory device MC. The signal Upper_SEL_pre is used to generate a signal informing the sequencer  12  of the page targeted by the process instructed by the command set following the command  02   h,  or in other words the command set associated with the command  02   h.  In other words, when the command  02   h  is received, a signal designating the page targeted by the command set associated with the command  02   h  is generated, and the generated signal is supplied to the sequencer  12 . 
     Of the “0” input node and the “1” input node, the selector S 1  outputs the one associated with the same value as the value of the signal received by the control input node as a signal Lower_SEL. Specifically, the selector S 1  outputs the signal received by the “0” input node while a “0” value signal is being received at the control input node, and outputs the signal received by the “1” input node while a “1” value signal is being received at the control input node. The signal Lower_SEL is supplied to the sequencer  12  and informs the sequencer  12  of the designation of the lower page. Using the signal Lower_SEL, the sequencer  12  recognizes that the lower page is the target of the command set associated with the page designation command ( 01   h  or  02   h ) that serves as the basis for generating the signal Lower_SEL. 
     The selector S 2  receives the signal Upper_SEL_pre at the “0” input node, and receives the signal Lower_SEL_pre at the “1” input node. Of the “0” input node and the “1” input node, the selector S 2  outputs the one associated with the same value as the value of the signal received by the control input node as a signal Upper_SEL. Specifically, the selector S 2  outputs the signal received by the “0” input node while a “0” value signal is being received at the control input node, and outputs the signal received by the “1” input node while a “1” value signal is being received at the control input node. The signal Upper_SEL is supplied to the sequencer  12  and informs the sequencer  12  of the designation of the upper page. Using the signal Upper_SEL, the sequencer  12  recognizes that the upper page is the target of the command set associated with the page designation command ( 01   h  or  02   h ) that serves as the basis for generating the signal Upper_SEL. 
       FIG.  52    illustrates an example of a state of the address converter  18  according to the 12th embodiment. In particular,  FIG.  52    illustrates the address converter  18  in the memory device MC 1 . As illustrated in  FIG.  52   , because the address converter  18  is in the memory device MC 1 , the signal CHIP_ADD&lt;0&gt; has the value “1” (has a high level). For this reason, as indicated by the bold lines, each of the selectors S 1  and S 2  couples its own “1” input node to its own output node. Accordingly, the interconnect transmitting the signal Lower_SEL_pre is coupled to the output node of the selector S 2 , and the signal Lower_SEL_pre is converted to the signal Upper_SEL. Also, the interconnect transmitting the signal Upper_SEL_pre is coupled to the output node of the selector S 1 , and the signal Upper_SEL_pre is converted to the signal Lower_SEL. 
     According to such conversion, when the command  01   h  designating the lower page is received by the memory device MC 1 , the sequencer  12  is informed that the target of the command set following the command  01   h  is the upper page. When the command  02   h  designating the upper page is received by the memory device MC 1 , the sequencer  12  is informed that the target of the command set following the command  02   h  is the lower page. 
     Note that the address converter  18  of the memory device MC 0  receives the signal CHIP_ADD&lt;0&gt; having the value “0” (having a low level). For this reason, the signal Lower_SEL has the same logic level as the signal Lower_SEL_pre, and the signal Upper_SEL has the same logic level as the signal Upper_SEL_pre. Accordingly, when the command  01   h  designating the lower page is received by the memory device MC 0 , the sequencer  12  is informed that the target of the command set following the command  01   h  is the lower page. When the command  02   h  designating the upper page is received by the memory device MC 0 , the sequencer  12  is informed that the target of the command set following the command  02   h  is the upper page. 
     &lt;12.2. Data Writes&gt; 
       FIG.  53    illustrates a flow of the input and output signal DQ for data writes in the memory system according to the 12th embodiment. To write data to the memory devices MC 0  and MC 1  as illustrated in  FIG.  48   , the memory controller  2  transmits command sets and the page data PG 0  to PG 3  to the memory devices MC 0  and MC 1  as illustrated in  FIG.  53   . 
     First, to instruct the memory device MC 0  to write the page data PG 0 , the memory controller  2  transmits the page data PG 0  and a command set instructing the memory device MC 0  to write the page data PG 0  to the lower page of a selected cell unit CUs 0   w.  For this purpose, the memory controller  2  transmits the command  01   h,  the command  80   h,  an address Add designating the selected cell unit CUs 0   w,  the page data PG 0 , and the command  1 Ah, in that order, for example. When the command set and the page data PG 0  are received by the memory device MC 0 , the sequencer  12  recognizes an instruction to write the page data PG 0  to the lower page of the selected cell unit CUs 0   w  of the memory device MC 0 . 
     To instruct the memory device MC 1  to write the page data PG 1 , the memory controller  2  transmits the page data PG 1  and a command set instructing the memory device MC 1  to write the page data PG 1  to the lower page of a certain selected cell unit CUs 1   w.  For this purpose, the memory controller  2  transmits the command  01   h,  the command  80   h,  an address Add designating the selected cell unit CUs 1   w,  the page data PG 1 , and the command  1 Ah, in that order, for example. When the command set and the page data PG 1  are received by the memory device MC 1 , the designation of the lower page by the command  01   h  is converted to a designation of the upper page by the address converter  18 . Accordingly, the sequencer  12  recognizes an instruction to write the page data PG 1  to the upper page of the selected cell unit CUs 1   w  of the memory device MC 1 . 
     To instruct the memory device MC 1  to write the page data PG 2 , the memory controller  2  transmits the page data PG 2  and a command set instructing the memory device MC 1  to write the page data PG 2  to the upper page of the selected cell unit CUs 1   w.  For this purpose, the memory controller  2  transmits the command  02   h,  the command  80   h,  an address Add designating the selected cell unit CUs 1   w,  the page data PG 2 , and the command  10   h,  in that order, for example. When the command set and the page data PG 2  are received by the memory device MC 1 , the designation of the upper page by the command  02   h  is converted to a designation of the lower page by the address converter  18 . Accordingly, the sequencer  12  recognizes an instruction to write the page data PG 2  to the lower page of the selected cell unit CUs 1   w  of the memory device MC 1 . 
     To instruct the memory device MC 0  to write the page data PG 3 , the memory controller  2  transmits the page data PG 3  and a command set instructing the memory device MC 0  to write the page data PG 3  to the upper page of the selected cell unit CUs 0   w.  For this purpose, the memory controller  2  transmits the command  02   h,  the command  80   h,  an address Add designating the selected cell unit CUs 0   w,  the page data PG 3 , and the command  10   h,  in that order, for example. When the command set and the page data PG 3  are received by the memory device MC 0 , the sequencer  12  recognizes an instruction to write the page data PG 3  to the upper page of the selected cell unit CUs 0   w  of the memory device MC 0 . 
     The transmission of commands as illustrated in  FIG.  53    means that the memory controller  2  recognizes that the page data PG 0  to PG 3  have been written to the positions illustrated in  FIG.  54   . In other words, the memory controller  2  recognizes that the page data PG 0  has been written to the lower page of the selected cell unit CUs 0   w  of the memory device MC 0 , the page data PG 1  has been written to the lower page of the selected cell unit CUs 1   w  of the memory device MC 1 , the page data PG 2  has been written to the upper page of the selected cell unit CUs 1   w  of the memory device MC 1 , and the page data PG 3  has been written to the upper page of the selected cell unit CUs 0   w  of the memory device MC 0 . The address conversion table  221  also indicates such correspondences between the page data PG and the physical addresses. 
     On the other hand, by the transmission of the commands and the page data PG as illustrated in  FIG.  53   , the page data PG 0  to PG 3  are actually written in the memory devices MC 0  and MC 1  as illustrated in  FIG.  48   . 
     &lt;12.3. Data Reads&gt; 
       FIG.  55    illustrates the flow of the input and output signal DQ during data reads over time in the memory system  100  according to the 12th embodiment. It should be noted that the memory controller  2  recognizes that the positions where the page data PG 0  to PG 3  are written are like in  FIG.  54   . 
     As illustrated in  FIG.  55   , the memory controller  2  reads the page data PG 0  and PG 1  in parallel. For this purpose, first, the memory controller  2  transmits a command set instructing the memory device MC 0  to perform a data read from the lower page of the selected cell unit CUs 0   w.  When the command set is received by the memory device MC 0 , the memory device MC 0  obtains the page data PG 0  stored in the lower page of the selected cell unit CUs 0   w.    
     Next, the memory controller  2  transmits a command set instructing the memory device MC 1  to perform a data read from the lower page of the selected cell unit CUs 1   w.  When the command set is received by the memory device MC 1 , the designation of the lower page by the command  01   h  is converted to a designation of the upper page by the address converter  18 . Accordingly, the memory device MC 1  obtains the page data PG 1  stored in the upper page of the selected cell unit CUs 1   w.    
     Next, the memory controller  2  reads the page data PG 2  and PG 3  in parallel. For this purpose, first, the memory controller  2  transmits a command set instructing the memory device MC 1  to perform a data read from the upper page of the selected cell unit CUs 1   w.  When the command set is received by the memory device MC 1 , the designation of the upper page by the command  02   h  is converted to a designation of the lower page by the address converter  18 . Accordingly, the memory device MC 1  obtains the page data PG 2  stored in the lower page of the selected cell unit CUs 1   w.    
     Next, the memory controller  2  transmits a command set instructing the memory device MC 0  to perform a data read from the upper page of the selected cell unit CUs 0   w.  When the command set is received by the memory device MC 0 , the memory device MC 0  obtains the page data PG 2  stored in the upper page of the selected cell unit CUs 0   w.    
     &lt;12.4. Advantages&gt; 
     In cases where the 12th embodiment is not used, writes of the page data PG as illustrated in  FIG.  48    according to the 11th embodiment typically requires the transmission of command sets and page data according to a sequence as illustrated in  FIG.  56   . In other words, the memory device MC and the page where the page data PG actually is to be written are designated. For example, the command set for writing the page data PG 1  designates the upper page, while the command set for writing the page data PG 2  designates the lower page. However, such a sequence has little regularity, and is not arranged well sequentially, such as writing data to the lower pages of the memory devices MC 0  and MC 1 , and then writing data to the upper pages of the memory devices MC 0  and MC 1 , for example. 
     According to the 12th embodiment, the transmission of the command sets for writing data sets as illustrated in the 11th embodiment is highly regular. In other words, for example, the writes of all data specifying the lower pages is complete, and then the writesg of data designating the upper pages can occur. Even with such command transmission, data is written as illustrated in the 11th embodiment. For this reason, the instructions for data writes by the memory controller  2  are simple, and the processing load on the memory controller  2  is light. 
     &lt;12.5. Modification&gt; 
     The conversion of designated pages by the address converter  18  or  19  like in the 12th embodiment is also applicable to embodiments other than the third and 11th embodiments. 
     13th Embodiment 
     The 13th embodiment relates to another configuration for achieving data writes according to the third embodiment. Hereinafter, the features that differ from the third embodiment will be described mainly. 
     The configuration of the memory system  100  according to the 13th embodiment is the same as the first embodiment. 
     The description below relates to an example of a configuration for achieving the writes illustrated in  FIG.  24    from among the various specific examples of data writes according to the third embodiment. Persons skilled in the art are capable of using the principles described below to design a configuration for achieving another example of data writes (for example,  FIG.  21   ) according to the third embodiment. 
     &lt;13.1. Configuration of Memory Devices&gt; 
       FIG.  57    illustrates components and connections in the memory devices according to a 13th embodiment. As illustrated in  FIG.  57   , each memory device MC includes an address converter  19  in addition to the components and connections according to the first embodiment ( FIG.  3   ). The memory devices MC according to the 13th embodiment may be referred to as the memory devices MCc in some cases. 
     The address converter  19  receives an address signal from the input and output circuit  11 , and converts a certain portion of the address signal, namely the portion indicating the address for a certain element, to a different address according to a predetermined rule. The portions other than the portion to be converted are output unchanged by the address converter  19 . The output from the address converter  19  is supplied to components such as the sequencer  12 , the row decoder  17 , and the sense amplifier  16 . 
       FIG.  58    illustrates components and connections in the address converter  19  according to the 13th embodiment. As illustrated in  FIG.  58   , the address converter  19  includes selectors S 11 , S 12 , S 13 , and S 14 . 
     Each of the selectors S 11  to S 14  includes a first input node, a second input node, a third input node, a fourth input node, a control input node, and an output node. Each of the first input node to the fourth input node is associated with a two-bit value. The first input node is associated with “10”. The second input node is associated with “11”. The third input node is associated with “00”. The fourth input node is associated with “01”. Hereinafter, the first input node may be referred to as the “10” input node, the second input node may be referred to as the “11” input node, the third input node may be referred to as the “00” input node, and the fourth input node may be referred to as the “01” input node. 
     Each of the selectors S 11  to S 14  receives a signal CHIP_ADD&lt;1:0&gt; at the control input node, where the signal CHIP_ADD&lt;1:0&gt; has a value based on the ID of the memory device MC that includes the address converter  19 . For example, the signal CHIP_ADD&lt;1:0&gt; has the value “00” in the memory device MC 0 , has the value “01” in the memory device MC 1 , has the value “10” in the memory device MC 2 , and has the value “11” in the memory device MC 3 . 
     The selector S 1 l receives a signal Lower_SEL_pre at the “10” input node. 
     The selector S 1 l receives a signal Middle_SEL_pre at the “11” input node. The signal Middle_SEL_pre is supplied from the input and output circuit  11  for example, and is asserted when the command  02   h,  which designates the middle page, is received by the memory device MC. The signal Middle_SEL_pre is used to generate a signal informing the sequencer  12  of the page targeted by the process instructed by the command set following the command  02   h,  or in other words the command set associated with the command  02   h.  In other words, when the command  02   h  is received, a signal designating the page targeted by the command set associated with the command  02   h  is generated, and the generated signal is supplied to the sequencer  12 . 
     The selector S 1 l receives a signal Upper_SEL_pre at the “00” input node. The signal Upper_SEL_pre is supplied from the input and output circuit  11  for example, and is asserted when the command  03   h,  which designates the upper page, is received by the memory device MC. The signal Upper_SEL_pre is used to generate a signal informing the sequencer  12  of the page targeted by the process instructed by the command set following the command  03   h,  or in other words the command set associated with the command  03   h.  In other words, when the command  03   h  is received, a signal designating the page targeted by the command set associated with the command  03   h  is generated, and the generated signal is supplied to the sequencer  12 . 
     The selector S 1 l receives a signal Top_SEL_pre at the “01” input node. The signal Top_SEL_pre is supplied from the input and output circuit  11  for example, and is asserted when a command  04   h,  which designates the top page, is received by the memory device MC. The signal Top_SEL_pre is used to generate a signal informing the sequencer  12  of the page targeted by the process indicated by the command set following the command  04   h,  or in other words the command set associated with the command  04   h.  In other words, when the command  04   h  is received, a signal designating the page targeted by the command set associated with the command  04   h  is generated, and the generated signal is supplied to the sequencer  12 . 
     Of the “10” input node, the “11” input node, the “00” input node, and the “01” input node, the selector S 11  outputs the one associated with the bit sequence having the same value as the value of the signal received by the control input node as the signal Lower_SEL. Specifically, while a “10” value signal is being received at the control input node, the selector S 11  outputs the signal received by the “10” input node. While a “11” value signal is being received at the control input node, the selector S 1 l outputs the signal received by the “11” input node. While a “00” value signal is being received at the control input node, the selector S 1 l outputs the signal received by the “00” input node. While a “01” value signal is being received at the control input node, the selector S 1 l outputs the signal received by the “01” input node. 
     The selector S 12  receives the signal Top_SEL_pre at the “10” input node, the signal Lower_SEL_pre at the “11” input node, the signal Middle_SEL_pre at the “00” input node, and the signal Upper_SEL_pre at the “01” input node. In a similar manner as the selector S 11 , of the “10” input node, the “11” input node, the “00” input node, and the “01” input node, the selector S 12  outputs the one associated with the bit sequence having the same value as the value of the signal received by the control input node as the signal Middle_SEL. The signal Middle_SEL is supplied to the sequencer  12  and informs the sequencer  12  of the designation of the middle page. Using the signal Middle_SEL, the sequencer  12  recognizes that the middle page is the target of the command set associated with the page designation command ( 01   h,    02   h,    03   h,  or  04   h ) that serves as the basis for generating the signal Middle_SEL. 
     The selector S 13  receives the signal Upper_SEL_pre at the “10” input node, the signal Top_SEL_pre at the “11” input node, the signal Lower_SEL_pre at the “00” input node, and the signal Middle_SEL_pre at the “01” input node. In a similar manner as the selector S 11 , of the “10” input node, the “11” input node, the “00” input node, and the “01” input node, the selector S 13  outputs the one associated with the bit sequence having the same value as the value of the signal received by the control input node as the signal Upper_SEL. 
     The selector S 14  receives the signal Middle_SEL_pre at the “10” input node, the signal Upper_SEL_pre at the “11” input node, the signal Top_SEL_pre at the “00” input node, and the signal Lower_SEL_pre at the “01” input node. In a similar manner as the selector S 11 , of the “10” input node, the “11” input node, the “00” input node, and the “01” input node, the selector S 14  outputs the one associated with the bit sequence having the same value as the value of the signal received by the control input node as the signal Top_SEL. The signal Top_SEL is supplied to the sequencer  12  and informs the sequencer  12  of the designation of the top page. Using the signal Top_SEL, the sequencer  12  recognizes that the top page is the target of the command set associated with the page designation command ( 01   h,    02   h,    03   h,  or  04   h ) that serves as the basis for generating the signal Top_SEL. 
       FIG.  59    illustrates an example of a state of the address converter  19  according to the 13th embodiment. In particular,  FIG.  59    illustrates the address converter  19  in the memory device MC 0 . As illustrated in  FIG.  59   , because the address converter  19  is in the memory device MC 0 , the signal CHIP_ADD&lt;1:0&gt; has the value “00” (each bit is at a low level). For this reason, as indicated by the bold lines, each of the selectors S 1  to S 4  couples its own “00” input node to its own output node. Accordingly, the interconnect transmitting the signal Lower_SEL_pre is coupled to the output node of the selector S 13 , and the signal Lower_SEL_pre is converted to the signal Upper_SEL. The interconnect transmitting the signal Middle_SEL_pre is coupled to the output node of the selector S 12 , and the signal Middle_SEL_pre is converted to the signal Middle_SEL. The interconnect transmitting the signal Upper_SEL_pre is coupled to the output node of the selector S 11 , and the signal Upper_SEL_pre is converted to the signal Lower_SEL. The interconnect transmitting the signal Top_SEL_pre is coupled to the output node of the selector S 14 , and the signal Top_SEL_pre is converted to the signal Top_SEL. 
     According to such conversion, when the command  01   h  designating the lower page is received by the memory device MC 0 , the sequencer  12  is informed that the target of the command set following the command  01   h  is the upper page. When the command  03   h  designating the upper page is received by the memory device MC 0 , the sequencer  12  is informed that the target of the command set following the command  03   h  is the lower page. 
     On the other hand, when the command  02   h  designating the upper page is received by the memory device MC 0 , the sequencer  12  is informed that the target of the command set following the command  02   h  is the middle page. When the command  04   h  designating the top page is received by the memory device MC 0 , the sequencer  12  is informed that the target of the command set following the command  04   h  is the top page. 
     In the address converter  19  of the memory devices MC 1 , MC 2 , and MC 3 , conversion is performed in a different form from the address converter  19  of the memory device MC 0  according to the same basic principle as the basic principle in the address converter  19  of the memory device MC 0 . 
     In the address converter  19  of the memory device MC 1 , the signal Lower_SEL_pre is converted to the signal Top_SEL. The signal Middle_SEL_pre is converted to the signal Upper_SEL. The signal Upper_SEL_pre is converted to the signal Middle_SEL. The signal Top_SEL_pre is converted to the signal Lower_SEL. 
     In the address converter  19  of the memory device MC 2 , the signal Lower_SEL_pre is converted to the signal Lower_SEL. The signal Middle_SEL_pre is converted to the signal Top_SEL. The signal Upper_SEL_pre is converted to the signal Upper_SEL. The signal Top_SEL_pre is converted to the signal Middle_SEL. 
     In the address converter  19  of the memory device MC 3 , the signal Lower_SEL_pre is converted to the signal Middle_SEL. The signal Middle_SEL_pre is converted to the signal Lower_SEL. The signal Upper_SEL_pre is converted to the signal Top_SEL. The signal Top_SEL_pre is converted to the signal Upper_SEL. 
     &lt;13.2. Data Writes&gt; 
       FIGS.  60  and  61    illustrate the flow of the input and output signal DQ for writes in the memory system  100  according to the 13th embodiment.  FIG.  61    illustrates the state following  FIG.  60   . 
     To write data to the memory devices MC 0  to MC 3  as illustrated in  FIGS.  60  and  61   , the memory controller  2  transmits command sets and the page data PG 0  to PG 15  to the memory devices MC 0  to MC 3  as illustrated in  FIGS.  60  and  61   . 
     First, to instruct the memory device MC 0  to write the page data PG 0 , the memory controller  2  transmits the page data PG 0  and a command set instructing the memory device MC 0  to write the page data PG 0  to the lower page of a selected cell unit CUs 0   w.  For this purpose, the memory controller  2  transmits the command  01   h,  the command  80   h,  an address Add designating the selected cell unit CUs 0   w,  the page data PG 0 , and the command  1 Ah, in that order, for example. When the command set and the page data PG 0  are received by the memory device MC 0 , the designation of the lower page by the command  01   h  is converted to a designation of the upper page by the address converter  19 . Accordingly, the sequencer  12  recognizes an instruction to write the page data PG 0  to the upper page of the selected cell unit CUs 0   w  of the memory device MC 0 . 
     To instruct the memory device MC 1  to write the page data PG 1 , the memory controller  2  transmits the page data PG 1  and a command set instructing the memory device MC 1  to write the page data PG 1  to the lower page of a selected cell unit CUs 1   w.  For this purpose, the memory controller  2  transmits the command  01   h,  the command  80   h,  an address Add designating the selected cell unit CUs 1   w,  the page data PG 1 , and the command  1 Ah, in that order, for example. When the command set and the page data PG 1  are received by the memory device MC 1 , the designation of the lower page by the command  01   h  is converted to a designation of the top page by the address converter  19 . Accordingly, the sequencer  12  recognizes an instruction to write the page data PG 1  to the top page of the selected cell unit CUs 1   w  of the memory device MC 1 . 
     To instruct the memory device MC 2  to write the page data PG 2 , the memory controller  2  transmits the page data PG 2  and a command set instructing the memory device MC 2  to write the page data PG 2  to the lower page of a selected cell unit CUs 2   w.  For this purpose, the memory controller  2  transmits the command  01   h,  the command  80   h,  an address Add designating the selected cell unit CUs 2   w,  the page data PG 2 , and the command  1 Ah, in that order, for example. When the command set and the page data PG 2  are received by the memory device MC 2 , the designation of the lower page by the command  01   h  is informed as a designation of the lower page by the address converter  19 . Accordingly, the sequencer  12  recognizes an instruction to write the page data PG 2  to the lower page of the selected cell unit CUs 2   w  of the memory device MC 2 . 
     To instruct the memory device MC 3  to write the page data PG 3 , the memory controller  2  transmits the page data PG 3  and a command set instructing the memory device MC 3  to write the page data PG 3  to the lower page of a selected cell unit CUs 3   w.  For this purpose, the memory controller  2  transmits the command  01   h,  the command  80   h,  an address Add designating the selected cell unit CUs 3   w,  the page data PG 3 , and the command  1 Ah, in that order, for example. When the command set and the page data PG 3  are received by the memory device MC 3 , the designation of the lower page by the command  01   h  is converted to a designation of the middle page by the address converter  19 . Accordingly, the sequencer  12  recognizes an instruction to write the page data PG 3  to the middle page of the selected cell unit CUs 3   w  of the memory device MC 3 . 
     Thereafter, in a similar manner, instructions for writing the page data PG 4  to PG 15  are issued by the memory controller  2 . The command sets for writing the page data PG 4  to PG 7  include the command  02   h,  the command  80   h,  the address Add, the page data PG, and the command  1 Ah. In the memory device MC 1 , the designation of the middle page by the command  02   h  is converted to a designation of the upper page by the address converter  19 . In the memory device MC 2 , the designation of the middle page by the command  02   h  is converted to a designation of the top page by the address converter  19 . In the memory device MC 3 , the designation of the middle page by the command  02   h  is converted to a designation of the lower page by the address converter  19 . In the memory device MC 0 , the designation of the middle page by the command  02   h  is maintained as a designation of the middle page. 
     The command sets for writing the page data PG 8  to PG 11  include the command  03   h,  the command  80   h,  the address Add, the page data PG, and the command  1 Ah. In the memory device MC 2 , the designation of the upper page by the command  03   h  is maintained as a designation of the upper page. In the memory device MC 3 , the designation of the upper page by the command  03   h  is converted to a designation of the top page by the address converter  19 . In the memory device MC 0 , the designation of the upper page by the command  03   h  is converted to a designation of the lower page by the address converter  19 . In the memory device MC 1 , the designation of the upper page by the command  03   h  is converted to a designation of the middle page by the address converter  19 . 
     The command sets for writing the page data PG 12  to PG 15  include the command  04   h,  the command  80   h,  the address Add, the page data PG, and the command  10   h.  In the memory device MC 3 , the designation of the top page by the command  04   h  is converted to a designation of the upper page by the address converter  19 . In the memory device MC 0 , the designation of the middle page by the command  04   h  is maintained as a designation of the top page. In the memory device MC 1 , the designation of the top page by the command  04   h  is converted to a designation of the lower page by the address converter  19 . In the memory device MC 2 , the designation of the top page by the command  04   h  is converted to a designation of the middle page by the address converter  19 . 
     The transmission of commands as illustrated in  FIGS.  60  and  61    means that the memory controller  2  recognizes that the page data PG 0  to PG 15  have been written as illustrated in  FIG.  62   . In other words, the memory controller  2  recognizes that the page data PG 0  has been written to the lower page of the selected cell unit CUs 0   w  of the memory device MC 0 , the page data PG 1  has been written to the lower page of the selected cell unit CUs 1   w  of the memory device MC 1 , the page data PG 2  has been written to the lower page of the selected cell unit CUs 2   w  of the memory device MC 2 , and the page data PG 3  has been written to the lower page of the selected cell unit CUs 3   w  of the memory device MC 3 . 
     The memory controller  2  recognizes that the page data PG 4  has been written to the middle page of the selected cell unit CUs 1   w  of the memory device MC 1 , the page data PG 5  has been written to the middle page of the selected cell unit CUs 2   w  of the memory device MC 2 , the page data PG 6  has been written to the middle page of the selected cell unit CUs 3   w  of the memory device MC 3 , and the page data PG 7  has been written to the middle page of the selected cell unit CUs 0   w  of the memory device MC 0 . 
     The memory controller  2  recognizes that the page data PG 8  has been written to the upper page of the selected cell unit CUs 2   w  of the memory device MC 2 , the page data PG 9  has been written to the upper page of the selected cell unit CUs 3   w  of the memory device MC 3 , the page data PG 10  has been written to the upper page of the selected cell unit CUs 0   w  of the memory device MC 0 , and the page data PG 11  has been written to the upper page of the selected cell unit CUs 1   w  of the memory device MC 1 . 
     The memory controller  2  recognizes that the page data PG 12  has been written to the top page of the selected cell unit CUs 3   w  of the memory device MC 3 , the page data PG 13  has been written to the top page of the selected cell unit CUs 0   w  of the memory device MC 0 , the page data PG 14  has been written to the top page of the selected cell unit CUs 1   w  of the memory device MC 1 , and the page data PG 15  has been written to the top page of the selected cell unit CUs 2   w  of the memory device MC 2 . The address conversion table  221  also indicates such correspondences between the page data PG and the physical addresses. 
     On the other hand, by the transmission of the commands and the page data PG as illustrated in  FIGS.  60  and  61   , the page data PG 0  to PG 15  are actually written in the memory devices MC 0  to MC 3  as illustrated in  FIG.  24   . 
     &lt;13.3. Data Reades&gt; 
       FIGS.  63  and  64    illustrate the flow of the input and output signal DQ during data reads over time in the memory system  100  according to the 13th embodiment.  FIG.  64    illustrates the state following  FIG.  63   . It should be noted that the memory controller  2  recognizes that the positions where the page data PG 0  to PG 15  are written are like in  FIG.  24   . 
     As illustrated in  FIGS.  63  and  64   , the memory controller  2  reads the page data PG 0  to PG 3  in parallel. For this purpose, first, the memory controller  2  transmits a command set instructing the memory device MC 0  to perform a data read from the lower page of the selected cell unit CUs 0   w.  When the command set is received by the memory device MC 0 , the designation of the lower page by the command  01   h  is converted to a designation of the upper page by the address converter  19 . Accordingly, the memory device MC 0  obtains the page data PG 0  stored in the upper page of the selected cell unit CUs 0   w.    
     The memory controller  2  transmits a command set instructing the memory device MC 1  to perform a data read from the lower page of the selected cell unit CUs 1   w.  When the command set is received by the memory device MC 1 , the designation of the lower page by the command  01   h  is converted to a designation of the top page by the address converter  19 . Accordingly, the memory device MC 1  obtains the page data PG 1  stored in the top page of the selected cell unit CUs 1   w.    
     The memory controller  2  transmits a command set instructing the memory device MC 2  to perform a data read from the lower page of the selected cell unit CUs 2   w.  When the command set is received by the memory device MC 2 , the designation of the lower page by the command  01   h  is maintained as a designation of the lower page by the address converter  19 . Accordingly, the memory device MC 2  obtains the page data PG 2  stored in the lower page of the selected cell unit CUs 2   w.    
     The memory controller  2  transmits a command set instructing the memory device MC 3  to perform a data read from the lower page of the selected cell unit CUs 3   w.  When the command set is received by the memory device MC 3 , the designation of the lower page by the command  01   h  is converted to a designation of the middle page by the address converter  19 . Accordingly, the memory device MC 3  obtains the page data PG 3  stored in the middle page of the selected cell unit CUs 3   w.    
     Thereafter, in a similar manner, instructions for reading the page data PG 4  to PG 15  are issued by the memory controller  2 . The command sets for reading the page data PG 4  to PG 7  include the command  02   h,  the command  00   h,  the address Add, and the command  30   h.  The designation of the middle page by the command  02   h  is converted as described for data writes. For this reason, an upper page read in the memory device MC 1 , a top page read in the memory device MC 2 , a lower page read in the memory device MC 3 , and a middle page read in the memory device MC 0  are performed. As a result, the page data PG 4  to PG 7  are obtained. 
     The command sets for reading the page data PG 8  to PG 11  include the command  03   h,  the command  00   h,  the address Add, and the command  30   h.  The designation of the upper page by the command  03   h  is converted as described for data writes. For this reason, an upper page read in the memory device MC 2 , a top page read in the memory device MC 3 , a lower page read in the memory device MC 0 , and a middle page read in the memory device MC 1  are performed. As a result, the page data PG 8  to PG 11  are obtained. 
     The command sets for reading the page data PG 12  to PG 15  include the command  04   h,  the command  00   h,  the address Add, and the command  30   h.  The designation of the top page by the command  04   h  is converted as described for data writes. For this reason, an upper page read in the memory device MC 3 , a top page read in the memory device MC 0 , a lower page read in the memory device MC 1 , and a middle page read in the memory device MC 2  are performed. As a result, the data written as the page data PG 12  to PG 15  is obtained. 
     &lt;13.4. Advantages&gt; 
     In cases where the 13th embodiment is not used, writes of the page data PG as illustrated in  FIG.  24    according to the 13th embodiment typically requires the transmission of command sets and page data according to a sequence as illustrated in  FIG.  65   . In other words, the memory device MC and the page where the page data PG actually is to be written are designated. For example, the command set for writing the page data PG 0  designates the upper page of the memory device MC 0 , the command set for writing the page data PG 1  designates the top page of the memory device MC 1 , the command set for writing the page data PG 2  designates the lower page of the memory device MC 2 , and the command set for writing the page data PG 3  designates the middle page of the memory device MC 3 . However, such a sequence has little regularity, and is not arrange well sequentially, such as writing data to the lower pages of the memory devices MC 0  to MC 3 , then writing data to the middle pages of the memory devices MC 0  to MC 3 , then writing data to the upper pages of the memory devices MC 0  to MC 3 , and then writing data to the top pages of the memory devices MC 0  to MC 3 , for example. 
     According to the 13th embodiment, the transmission of the command sets for writing data sets as illustrated in the 13th embodiment is highly regular. In other words, for example, a sequence such as all data-writes designating the lower page, then all data-writes designating the middle page, then all data-writes designating the upper page, and then all data-writes designating the top page is possible. Even with such command transmission, data is written as illustrated in the 13th embodiment. For this reason, the instructions for data writing by the memory controller  2  are simple, and the processing load on the memory controller  2  is light. 
     &lt;13.5. Modification&gt; 
     The conversion of designated pages by the address converter  18  or  19  like in the 13th embodiment is also applicable to embodiments other than the third and 11th embodiments. 
     14th Embodiment 
     The 14th embodiment relates to details of read, and is applicable to the reading of data stored in any format. Hereinafter, the features that differ from the first embodiment will be described mainly. 
     &lt;14.1. Configuration&gt; 
       FIG.  66    illustrates functional blocks of a memory controller  2  according to the 14th embodiment. Each functional block is realizable by operations by the CPU  22  following firmware in the RAM  23 , a portion of the memory space in the RAM  23 , and/or dedicated hardware (or, a circuit). 
     The memory controller  2  includes a command generator  231 , a command queue  232 , and a command delivery unit  233 . Of the plurality of functions provided by the read controller  212 , the command generator  231  is responsible for generating the command sets described in the first to  13 th embodiments. The command generator  231  generates command sets according to a first-in first-out rule, for example. In other words, the command generator  231  generates command sets in the same order as the order in which the command generator  231  determines the generation of the command sets, on the basis of information such as instructions from the host device  200 . 
     The command queue  232  holds the command sets generated by the command generator  231  in the generated order. In other words, a command set generated earlier is assigned a higher order of priority. 
     The command delivery unit  233  transmits the command sets held in the command queue  232  to the memory interface  25  in an order rearranged according to a certain rule. The memory interface  25  transmits the command sets to the memory device MC in the order in which the command sets were received from the command delivery unit  233 . 
     &lt;14.2. Operations&gt; 
     The following description and related diagrams relate to an example of the storage of two bits of data per memory cell transistor, the same as that described in the 11th embodiment. However, the 14th embodiment is also applicable to an example of the storage of three or more bits of data per memory cell transistor. The details can be inferred by persons skilled in the art on the basis of the principles described below. 
     The memory device MC uses the same  12  mapping as the 11th embodiment, such that each cell unit CU stores data of two pages in size, and the two pages include just one fast page. Also, like the 11th embodiment, the following description relates to an example in which the planes PB 0  and PB 1  in each memory device MC cannot operate independently. 
       FIG.  67    illustrates a flow of data reads in the memory system  100  according to the 14th embodiment, and more specifically, illustrates a flow of operations by the read controller  212 . As illustrated in  FIG.  67   , the command generator  231  determines whether N read command sets are being held in the command queue  232  (step ST 31 ). N is any number. As described later, the read controller  212  rearranges, for each N command set, an order in which to deliver the N command sets. For this reason, the order in which the command sets are generated and the order in which the command sets are delivered may be different, and there is a possibility of a delay in the delivery of a command set generated earlier. It is possible to determine N such that this delay does not violate the constraints that the memory system  100  should satisfy. The following description is based on an example where N is 4. 
     In the case where N read command sets are not being held in the command queue  232  (No branch of step ST 31 ), the process proceeds to step ST 32 . In step ST 32 , the command generator  231  generates a read command set on the basis of the occurrence of processes to be executed. Step ST 32  continues to step ST 31 . 
     In the case where N read command sets are being held in the command queue  232  (Yes branch of step ST 31 ), the process proceeds to step ST 33 . In step ST 33 , the command delivery unit  233  determines whether the N command sets include a command set targeting a memory device MC and a command set targeting another memory device MC. In the case where command sets targeting different memory devices MC are not included (No branch of step ST 33 ), the process proceeds to step ST 35 . In step ST 35 , the command delivery unit  233  transmits the N command sets to the target memory devices MC through the memory interface  25  in the current arrangement, that is, in the current order of priority. 
     In the case where command sets targeting different memory devices MC are included, the process proceeds to step ST 36 . In step ST 36 , the command delivery unit  233  rearranges the order of the N command sets in the command queue  232  such that the command set targeting a memory device MC is followed by the command set targeting another memory device MC. For example, in the case where four command sets arranged in the generated order target the memory devices MC 0 , MC 0 , MC 1 , and MC 1 , respectively, the command delivery unit  233  rearranges the command sets into the order of a command set targeting the memory device MC 0 , a command set targeting the memory device MC 1 , a command set targeting the memory device MC 0 , and a command set targeting the memory device MC 1 . 
     Hereinafter, rearranging the order of command sets CS and changing the priorities assigned to command sets CS refer to the same process. 
     The command delivery unit  233  determines whether the N command sets include a command set for a non-fast page and a command set for a fast page (step ST 38 ). In the case where the N command sets do not include both a read command set for a non-fast page and a read command set for a fast page (No branch of step ST 38 ), the process proceeds to step ST 35 . 
     In the case where the N command sets include both a read command set for a non-fast page (non-fast page command set) CS and a read command set targeting a fast page (fast page command set) CS (Yes branch of step ST 38 ), the process proceeds to step ST 39 . In step ST 39 , the command delivery unit  233  rearranges the N command sets such that a fast page command set CS is followed by a non-fast page command set CS, while also maintaining the arrangement in which consecutive command sets CS target different memory devices MC. To this end, in the arrangement of the N command sets, the command delivery unit  233  can substitute each fast page command set with a different command set for the memory device MC targeted by the fast page command set among the N command sets. Through the rearrangement in step ST 39 , at least one fast page command set CS is moved to the front of the order of the N command sets CS. 
     Step ST 39  continues to step ST 35 . When step ST 35  ends, the flow in  FIG.  67    ends. In the case where a read command set still exists, the flow in  FIG.  67    starts from step ST 31 . 
     Hereinafter,  FIGS.  68  to  70    will be referenced to describe three examples of rearranging read command sets. 
       FIGS.  68  to  70    illustrate states of the command queue  232  during operations over time in the memory system  100  according to the 14th embodiment. Specifically,  FIGS.  68  to  70    respectively illustrate a first example, a second example, and a third example of the state of the command queue during the flow of  FIG.  67   , and relate to an example of N=4. 
     The portion (a) of  FIG.  68    illustrates the state at the start of step ST 33 . As an example, the four command sets include command sets CS 00 , CS 01 , CS 10 , and CS 11 . The command set CS 00  designates a read from a non-fast page of the memory device MC 0 . The command set CS 01  designates a read from a non-fast page of the memory device MC 0 . The command set CS 10  designates a read from a non-fast page of the memory device MC 1 . The command set CS 11  (shaded in the diagram) designates a read from a fast page of the memory device MC 1 . The command sets CS 00 , CS 01 , CS 10 , and CS 11  are generated in that order. For this reason, the command sets CS 00 , CS 01 , CS 10 , and CS 11  are arranged by decreasing priority in that order. 
     The portion (b) of  FIG.  68    illustrates the state at the end of step ST 36 . The command sets CS 00 , CS 01 , CS 10 , and CS 11  have been rearranged such that a command targeting the memory device MC 0  is adjacent to a command targeting the memory device MC 1 . As a result, for example, the command sets CS 00 , CS 10 , CS 01 , and CS 11  are arranged by decreasing priority in that order. 
     The portion (c) of  FIG.  68    illustrates the state at the end of step ST 39 . The command set CS 11  targeting a fast page is moved to the front of the order of priority. Even after the move, the remaining command sets CS 00 , CS 01 , and CS 10  are still rearranged such that a command targeting the memory device MC 0  is adjacent to a command targeting the memory device MC 1 . As a result, the command sets CS 11 , CS 00 , CS 10 , and CS 01  are arranged by decreasing priority in that order. 
     The portion (a) of  FIG.  69    illustrates the state at the start of step ST 33 . As an example, the four command sets include command sets CS 00 , CS 01 , CS 11 , and CS 02 . The command set CS 02  designates a read from a non-fast page of the memory device MC 0 . The command sets CS 00 , CS 01 , CS 11 , and CS 02  are generated in that order. 
     The portion (b) of  FIG.  69    illustrates the state at the end of step ST 39 . As a result of rearrangement, the only fast page command set CS 11  is positioned at the beginning of the order of priority, and is followed by a command set that targets the memory device MC 0 , which is different from the memory device MC 1 , which is the target of the fast page command set CS 11 , such as the command set CS 00  for example. Because there is no other command set CS targeting the memory device MC 1 , the command set CS 00  is followed by the command sets targeting the memory device MC 0 , such as the command sets CS 01  and CS 02  in that order, for example. 
     The portion (a) of  FIG.  70    illustrates the state at the start of step ST 33 . As an example, the four command sets include command sets CS 00 , CS 03 , CS 10 , and CS 11 . The command set CS 03  designates a read from a fast page of the memory device MC 0 . The command sets CS 00 , CS 03 , CS 10 , and CS 11  are generated in the above order. 
     The portion (b) of  FIG.  70    illustrates the state at the end of step ST 39 . As a result of rearrangement, the fast page command set CS 03  is positioned at the beginning of the order of priority, and is followed by the command set CS 11 , which targets the memory device MC 1 , which is different from the memory device MC 0 , which is the target of the command set CS 03 . The command set CS 00  targeting the memory device MC 0 , which is different from the memory device MC 1 , which is the target of the command CS 11 , follows next, and is followed by the remaining command set CS 10 . 
     &lt;14.3. Advantages&gt; 
     Depending on the order in which the read command sets are generated, if the read command sets are transmitted in the generated order, the execution of the reads may be time-consuming in some cases. For example, the command sets CS 00 , CS 01 , CS 10 , and CS 11  generated in the order illustrated in the portion (a) of  FIG.  68    can be rearranged such that command sets CS targeting different memory devices MC are adjacent to each other, as illustrated in the portion (b) of  FIG.  68   . This arrangement makes it possible to proceed with reads by a plurality of command sets in parallel. However, the command set CS 11  targeting a fast page comes after the command set CS 01  targeting a non-fast page. For this reason, even though preparations are complete for the output of page data PG by the command set CS 11 , it is necessary to wait for the read and the output of the obtained page data PG by the command set CS 01 . 
     According to the 14th embodiment, a plurality of command sets CS are transmitted from the memory controller  2  in an order such that a fast page command set CS is positioned in front and is also followed by a command set CS targeting another memory device MC, and also such that a fast page command set CS is followed by a non-fast page command set CS, regardless of the generated order. 
     For this reason, the start of a read from a certain fast page of a certain memory device MC is followed by the start of a read from a certain non-fast page of another memory device MC, while in addition, the non-fast page read is started after the start of the fast page read in another memory device MC, regardless of the order in which the read command sets are generated. This makes it possible to output the data of the fast page while the non-fast page read is in progress. Consequently, it is possible to read and output data with the same efficiency as the first embodiment according to the same principle as the first embodiment. 
     &lt;14.4. Modification&gt; 
     The description so far relates to an example in which the command delivery unit  233  is included in the read controller  212 . The 14th embodiment is not limited to this example. For example, the command delivery unit  233  may also be a part of the functions of the memory interface  25 . 
     15th Embodiment 
     The 15th embodiment relates to an extension of the first to 11th embodiments, and is applicable to the first to 14th embodiments. 
     &lt;15.1. Structure (Configuration)&gt; 
       FIG.  71    illustrates components and connections in a memory system according to a 15th embodiment, and related components. As illustrated in  FIG.  71   , the memory system  100  according to the 15th embodiment is different from the configuration according to the first embodiment ( FIG.  1   ) with regard to the memory controller  2  and the memory devices MC. In general, the memory system  100  according to the 15th embodiment includes two or more sets of the memory interface  25  according to the first embodiment and one or more memory devices MC connected to that memory interface  25 . Hereinafter, the memory system  100  and the memory controller  2  according to the 15th embodiment may be referred to as the memory system  100 A and the memory controller  2 A, respectively, for distinction. 
     The memory controller  2 A includes a plurality of memory interfaces  25 .  FIG.  71    and the following description are based on an example in which the memory system  100  includes two sets, and consequently the memory controller  2 A includes two memory interfaces  25 A and  25 B. The memory interfaces  25 A and  25 B have the same configuration as the memory interface  25 . 
     The memory interface  25 A is connected to one or more memory devices MCA (MCA 0 , MCA 1 , and so on). The memory interface  25 B is connected to one or more memory devices MCB (MCB 0 , MCB 1 , and so on). Each memory interface  25  and the memory devices MCS connected to each memory interface  25  are connected similarly to the connection between the memory interface  25  and the one or more memory devices MC in the first embodiment ( FIG.  1   ). 
       FIG.  72    illustrates functional blocks of the memory controller  2 A according to the 15th embodiment. Each functional block is realizable by operations by the CPU  22  following firmware in the RAM  23 , a portion of the memory space in the RAM  23 , and/or dedicated hardware (or, a circuit). As illustrated in  FIG.  72   , the memory controller  2 A includes the memory interfaces  25 A and  25 B instead of the memory interface  25 . 
     &lt;15.2. Operations&gt; 
     The memory controller  2 A writes data to the memory devices MC as described below. Hereinafter, the case of an extension of the second embodiment is described as an example. In other words, the  4434  mapping is used, and each memory device MC includes the planes PB 0  and PB 1  capable of operating independently. Also, in each of the memory device MCA and the memory device MCB, the memory area unit MA 2  is configured as in the second embodiment. The memory area unit MA 2  of the memory device MCA is referred to as the memory area unit MA 2 A, and the memory area unit MA 2  of the memory device MCB is referred to as the memory area unit MA 2 B. 
     The memory area unit MA 2 A is the set of the lower, middle, upper, and top pages of a cell unit CUs 00  in a plane PB 0  of a memory device MCA 0 , the lower, middle, upper, and top pages of a cell unit CUs 01  in a plane PB 1  of the memory device MCA 0 , the lower, middle, upper, and top pages of a cell unit CUs 10  in a plane PB 0  of a memory device MCAT, and the lower, middle, upper, and top pages of a cell unit CUs 11  in a plane PB 1  of the memory device MCA 1 . 
     The memory area unit MA 2 B is the set of the lower, middle, upper, and top pages of a cell unit CUs 00  in a plane PB 0  of a memory device MCB 0 , the lower, middle, upper, and top pages of a cell unit CUs 01  in a plane PB 1  of the memory device MCB 0 , the lower, middle, upper, and top pages of a cell unit CUs 10  in a plane PB 0  of a memory device MCB 1 , and the lower, middle, upper, and top pages of a cell unit CUs 11  in a plane PB 1  of the memory device MCB 1 . 
     Based on such features of the memory area units MA 2 A and MA 2 B, 32 pieces of page data PG with consecutive logical addresses are stored in a single memory area unit MA 2 A or MA 2 B. Additionally, 16 pieces of page data PG with certain logical addresses are held in the memory area unit MA 2 A, while the 16 pieces of page data PG with the remaining logical addresses are held in the memory area unit MA 2 B. 
     Next,  FIGS.  73  to  75    will be referenced to describe specific first to third examples of writing.  FIGS.  73  to  75    respectively illustrate first to third examples of the memory area units MA 2  and positions where page data are written in the memory devices MC according to the 15th embodiment. In general, 32 pieces of page data PG with consecutive logical addresses are written in a distributed manner to the memory area units MA 2 A and MA 2 B, similarly to the second embodiment. 
     &lt; 15 . 2 . 1 . First Example&gt; 
     As illustrated in  FIG.  73   , the 32 pieces of page data PG with consecutive logical addresses are alternately written to the memory area units MA 2 A and MA 2 B in order of ascending logical address. In other words, page data PG( 2 y) is written to the memory area unit MA 2 A according to a rule by which the descriptions regarding the page data PG 0  to PG 15  in the second embodiment are applied to the page data PG( 2 γ) for the cases of γ from 0 to 15, respectively. Additionally, page data PG(2γ+1) is written to the memory area unit MA 2 B according to a rule by which the descriptions regarding the page data PG 0  to PG 15  in the second embodiment are applied to the page data PG(2γ+1) for the cases of γ from 0 to 15, respectively. Details are as follows. 
     For each of the cases where δ is 0, 1, 8, 9, 16, 17, 24, and 25, the page data PGδ, PG(δ+2), PG(δ+4), and PG(δ+6) form a data set. 
     As illustrated in  FIG.  73   , for each of the cases where δ is 0, 8, 16, and 24, each one of the page data PGδ, PG(δ+2), PG(δ+4), and PG(δ+6) of each data set is written to a different one of all combinations of the planes PB 0  and PB 1  of the memory devices MCA 0  and MCAT, and in addition, one of the page data PGδ, PG(δ+2), PG(δ+4), and PG(δ+6) is written to a fast page (upper page) while the remaining three are written to non-fast pages. Also, each piece of page data included in a data set and written to a non-fast page is written to any of the lower, middle, and top pages. Furthermore, the pages to which the page data PG 0 , PG 2 , PG 4 , PGδ, PG 8 , PG 10 , PG 12 , PG 14 , PG 16 , PG 18 , PG 20 , PG 22 , PG 24 , PG 26 , PG 28 , and PG 30  are written are determined such that four data sets are written to the memory area unit MA 2 A. Insofar as the pages are written in this way, the positions where the page data PG 0 , PG 2 , PG 4 , PGδ, PG 8 , PG 10 , PG 12 , PG 14 , PG 16 , PG 18 , PG 20 , PG 22 , PG 24 , PG 26 , PG 28 , and PG 30  are written are not limited to the example in  FIG.  73   . As an example, the page data PG written to the non-fast pages can be written to different one of lower, middle, and top pages. 
     Also, for each of the cases where δ is 1, 9, 17, and 25, each one of the page data PGδ, PG(δ+2), PG(δ+4), and PG(δ+6) of each data set are written to a different one of all combinations of the planes PB 0  and PB 1  of the memory devices MCB 0  and MCB 1 , and in addition, one of the page data PGδ, PG(δ+2), PG(δ+4), and PG(δ+6) is written to a fast page (upper page) while the remaining three are written to non-fast pages. Also, each piece of page data included in a data set and written to a non-fast page is written to any of the lower, middle, and top pages. Furthermore, the pages to which the page data PG 1 , PG 3 , PG 5 , PG 7 , PG 9 , PG 11 , PG 13 , PG 15 , PG 17 , PG 19 , PG 21 , PG 23 , PG 25 , PG 27 , PG 29 , and PG 31  are written are determined such that four data sets are written to the memory area unit MA 2 B. Insofar as the pages are written in this way, the positions where the page data PG 1 , PG 3 , PG 5 , PG 7 , PG 9 , PG 11 , PG 13 , PG 15 , PG 17 , PG 19 , PG 21 , PG 23 , PG 25 , PG 27 , PG 29 , and PG 31  are written are not limited to the example in  FIG.  73   . As an example, the page data PG written to the non-fast pages can be written to different one of lower, middle, and top pages. 
     As illustrated in  FIG.  73   , the page data PG 0  is written to the upper page of the selected cell unit CUs 00  in the plane PB 0  of the memory device MCA 0 . The page data PG 1  is written to the upper page of the selected cell unit CUs 00  in the plane PB 0  of the memory device MCB 0 . The page data PG 2  is written to the middle page of the selected cell unit CUs 01  in the plane PB 1  of the memory device MCA 0 . The page data PG 3  is written to the middle page of the selected cell unit CUs 01  in the plane PB 1  of the memory device MCB 0 . The page data PG 4  is written to the lower page of the selected cell unit CUs 10  in the plane PB 0  of the memory device MCA 1 . The page data PG 5  is written to the lower page of the selected cell unit CUs 10  in the plane PB 0  of the memory device MCB 1 . The page data PG 6  is written to the top page of the selected cell unit CUs 11  in the plane PB 1  of the memory device MCA 1 . The page data PG 7  is written to the top page of the selected cell unit CUs 11  in the plane PB 1  of the memory device MCB 1 . 
     The page data PG 8  is written to the upper page of the selected cell unit CUs 00  in the plane PB 1  of the memory device MCA 0 . The page data PG 9  is written to the upper page of the selected cell unit CUs 00  in the plane PB 1  of the memory device MCB 0 . The page data PG 10  is written to the middle page of the selected cell unit CUs 00  in the plane PB 0  of the memory device MCA 0 . The page data PG 11  is written to the middle page of the selected cell unit CUs 00  in the plane PB 0  of the memory device MCB 0 . The page data PG 12  is written to the lower page of the selected cell unit CUs 11  in the plane PB 1  of the memory device MCA 1 . The page data PG 13  is written to the lower page of the selected cell unit CUs 11  in the plane PB 1  of the memory device MCB 1 . The page data PG 14  is written to the top page of the selected cell unit CUs 10  in the plane PB 0  of the memory device MCA 1 . The page data PG 15  is written to the top page of the selected cell unit CUs 10  in the plane PB 0  of the memory device MCB 1 . 
     The page data PG 16  is written to the upper page of the selected cell unit CUs 10  in the plane PB 0  of the memory device MCA 1 . The page data PG 17  is written to the upper page of the selected cell unit CUs 10  in the plane PB 0  of the memory device MCB 1 . The page data PG 18  is written to the middle page of the selected cell unit CUs 11  in the plane PB 1  of the memory device MCA 1 . The page data PG 19  is written to the middle page of the selected cell unit CUs 11  in the plane PB 1  of the memory device MCB 1 . The page data PG 20  is written to the top page of the selected cell unit CUs 00  in the plane PB 0  of the memory device MCA 0 . The page data PG 21  is written to the top page of the selected cell unit CUs 00  in the plane PB 0  of the memory device MCB 0 . The page data PG 22  is written to the lower page of the selected cell unit CUs 01  in the plane PB 1  of the memory device MCA 0 . The page data PG 23  is written to the lower page of the selected cell unit CUs 01  in the plane PB 1  of the memory device MCB 0 . 
     The page data PG 24  is written to the upper page of the selected cell unit CUs 11  in the plane PB 1  of the memory device MCA 1 . The page data PG 25  is written to the upper page of the selected cell unit CUs 11  in the plane PB 1  of the memory device MCB 1 . The page data PG 26  is written to the middle page of the selected cell unit CUs 10  in the plane PB 0  of the memory device MCA 1 . The page data PG 27  is written to the middle page of the selected cell unit CUs 10  in the plane PB 0  of the memory device MCB 1 . The page data PG 28  is written to the top page of the selected cell unit CUs 01  in the plane PB 1  of the memory device MCA 0 . The page data PG 29  is written to the top page of the selected cell unit CUs 01  in the plane PB 1  of the memory device MCB 0 . The page data PG 30  is written to the lower page of the selected cell unit CUs 00  in the plane PB 0  of the memory device MCA 0 . The page data PG 31  is written to the lower page of the selected cell unit CUs 00  in the plane PB 0  of the memory device MCB 0 . 
     Data reads are the same as those in the second embodiment, except for occurring in the memory devices MCA and MCB in parallel. In other words, in each of the memory area units MA 2 A and MA 2 B, reads can proceed according to a rule by which the descriptions regarding the 16 pieces of page data PG with consecutive logical address in the second embodiment are applied to 16 pieces of page data PG with alternating logical addresses. 
     &lt;15.2.2. Second Example&gt; 
     As illustrated in  FIG.  74   , the 32 pieces of page data PG with consecutive logical addresses are alternately written to the memory area units MA 2 A and MA 2 B in order of ascending logical address for every four pieces of page data PG with certain logical addresses. Specifically, the page data PGγ, PG(γ+1), PG(γ+4), and PG(γ+5) are written to the memory area unit MA 2 A according to a rule where the descriptions regarding the page data PG 0  to PG 15  in the second embodiment are applied to the page data PGγ, PG(γ+1), PG(γ+4), and PG(γ+5) in ascending order for each of the cases where γ is 0, 8, 16, and 24. Furthermore, the page data PGγ, PG(γ+1), PG(γ+4), and PG(γ+5) are written to the memory area unit MA 2 B according to a rule where the descriptions regarding the page data PG 0  to PG 15  in the second embodiment are applied to the page data PGγ, PG(γ+1), PG(γ+4), and PG(γ+5) in ascending order for each of the cases where γ is 2, 10, 18, and 26. Details are as follows. 
     For each of the cases where δ is 0, 2, 8, 10, 16, 18, 24, and 26, the page data PGδ, PG(δ+1), PG(δ+4), and PG(δ+5) form a data set. 
     As illustrated in  FIG.  74   , for each of the cases where δ is 0, 8, 16, and 24, each one of the page data PGδ, PG(δ+1), PG(δ+4), and PG(δ+5) of each data set is written to a different one of all combinations of the planes PB 0  and PB 1  of the memory devices MCA 0  and MCAT, and in addition, one of the page data PGS, PG(δ+1), PG(δ+4), and PG(δ+5) is written to a fast page (upper page) while the remaining three are written to non-fast pages. Also, each piece of page data included in a data set and written to a non-fast page is written to any of the lower, middle, and top pages. Furthermore, the pages to which the page data PG 0 , PG 1 , PG 4 , PG 5 , PG 8 , PG 9 , PG 12 , PG 13 , PG 16 , PG 17 , PG 20 , PG 21 , PG 24 , PG 25 , PG 28 , and PG 29  are written are determined such that four data sets are written to the memory area unit MA 2 A. Insofar as the pages are written in this way, the positions where the page data PG 0 , PG 1 , PG 4 , PG 5 , PG 8 , PG 9 , PG 12 , PG 13 , PG 16 , PG 17 , PG 20 , PG 21 , PG 24 , PG 25 , PG 28 , and PG 29  are written are not limited to the example in  FIG.  74   . As an example, the page data PG written to the non-fast pages can be written to different one of lower, middle, and top pages. 
     Also, for each of the cases where δ is 2, 10, 18, and 26, each of the page data PGδ, PG(δ+1), PG(δ+4), and PG(δ+5) of each data set is written to a different one of all combinations of the planes PB 0  and PB 1  of the memory devices MCB 0  and MCB 1 , and in addition, one of the page data PGδ, PG(δ+1), PG(δ+4), and PG(δ+5) is written to a fast page (upper page) while the remaining three are written to non-fast pages. Also, each piece of page data included in a data set and written to a non-fast page is written to any of the lower, middle, and top pages. Furthermore, the pages to which the page data PG 2 , PG 3 , PGδ, PG 7 , PG 10 , PG 11 , PG 14 , PG 15 , PG 18 , PG 19 , PG 22 , PG 23 , PG 26 , PG 27 , PG 30 , and PG 31  are written are determined such that four data sets are written to the memory area unit MA 2 B. Insofar as the pages are written in this way, the positions where the page data PG 2 , PG 3 , PGδ, PG 7 , PG 10 , PG 11 , PG 14 , PG 15 , PG 18 , PG 19 , PG 22 , PG 23 , PG 26 , PG 27 , PG 30 , and PG 31  are written are not limited to the example in  FIG.  74   . As an example, the page data PG written to the non-fast pages can be written to different one of lower, middle, and top pages. 
     Data reads are the same as those in the second embodiment, except for occurring in the memory devices MCA and MCB in parallel. In other words, in each of the memory area units MA 2 A and MA 2 B, reads can proceed according to a rule where the descriptions regarding the 16 pieces of page data PG with consecutive logical address in the second embodiment are applied to 16 pieces of page data PG with two consecutive logical addresses every four logical addresses. 
     &lt;15.2.3. Third Example&gt; 
     As illustrated in  FIG.  75   , the 32 pieces of page data PG with consecutive logical addresses are alternately written to the memory area units MA 2 A and MA 2 B in order of ascending logical address for every four pieces of page data PG with consecutive logical addresses. Specifically, the page data PGγ, PG(γ+1), PG(γ+2), and PG(γ+3) are written to the memory area unit MA 2 A according to a rule where the descriptions regarding the page data PG 0  to PG 15  in the second embodiment are applied to the page data PGγ, PG(γ+1), PG(γ+2), and PG(γ+3) in ascending order for each of the cases where γ is 0, 8, 16, and 24. Furthermore, the page data PGγ, PG(γ+1), PG(γ+2), and PG(γ+3) are written to the memory area unit MA 2 B according to a rule where the descriptions regarding the page data PG 0  to PG 15  in the second embodiment are applied to the page data PGγ, PG(γ+1), PG(γ+2), and PG(γ+3) in ascending order for each of the cases where γ is 4, 12, 20, and 28. Details are as follows. 
     For each of the cases where δ is 0, 4, 8, 12, 16, 20, 24, and 28, the page data PGδ, PG(δ+1), PG(δ+2), and PG(δ+3) form a data set. 
     As illustrated in  FIG.  75   , for each of the cases where δ is 0, 8, 16, and 24, each of the page data PGδ, PG(δ+1), PG(δ+2), and PG(δ+3) of each data set is written to a different one of all combinations of the planes PB 0  and PB 1  of the memory devices MCA 0  and MCAT, and in addition, one of the page data PGδ, PG(δ+1), PG(δ+2), and PG(δ+3) is written to a fast page (upper page) while the remaining three are written to non-fast pages. Also, each piece of page data included in a data set and written to a non-fast page is written to any of the lower, middle, and top pages. Furthermore, the pages to which the page data PG 0 , PG 1 , PG 2 , PG 3 , PG 8 , PG 9 , PG 10 , PG 11 , PG 16 , PG 17 , PG 18 , PG 19 , PG 24 , PG 25 , PG 26 , and PG 27  are written are determined such that four data sets are written to the memory area unit MA 2 A. Insofar as the pages are written in this way, the positions where the page data PG 0 , PG 1 , PG 2 , PG 3 , PG 8 , PG 9 , PG 10 , PG 11 , PG 16 , PG 17 , PG 18 , PG 19 , PG 24 , PG 25 , PG 26 , and PG 27  are written are not limited to the example in  FIG.  75   . As an example, the page data PG written to the non-fast pages can be written to different one of lower, middle, and top pages. 
     Also, for each of the cases where δ is 4, 12, 20, and 28, each of the page data PGδ, PG(δ+1), PG(δ+2), and PG(δ+3) of each data set is written to a different one of every combination of the planes PB 0  and PB 1  of the memory devices MCB 0  and MCB 1 , and in addition, one of the page data PGδ, PG(δ+1), PG(δ+2), and PG(δ+3) is written to a fast page (upper page) while the remaining three are written to non-fast pages. Also, each piece of page data included in a data set and written to a non-fast page is written to any of the lower, middle, and top pages. Furthermore, the pages to which the page data PG 4 , PG 5 , PGδ, PG 7 , PG 12 , PG 13 , PG 14 , PG 15 , PG 20 , PG 21 , PG 22 , PG 23 , PG 28 , PG 29 , PG 30 , and PG 31  are written are determined such that four data sets are written to the memory area unit MA 2 B. Insofar as the pages are written in this way, the positions where the page data PG 4 , PG 5 , PGδ, PG 7 , PG 12 , PG 13 , PG 14 , PG 15 , PG 20 , PG 21 , PG 22 , PG 23 , PG 28 , PG 29 , PG 30 , and PG 31  are written are not limited to the example in  FIG.  75   . As an example, the page data PG written to the non-fast pages can be written to different one of lower, middle, and top pages. 
     Data reads are the same as those in the second embodiment, except for occurring in the memory devices MCA and MCB in parallel. In other words, in each of the memory area units MA 2 A and MA 2 B, reads can proceed according to a rule where the descriptions regarding the 16 pieces of page data PG with consecutive logical address in the second embodiment are applied to 16 pieces of page data PG with consecutive logical addresses every four logical addresses. 
     &lt;15.3. Modification&gt; 
     As described above, the 15th embodiment is applicable to any of the first embodiment and the third to 11th embodiments. In this case, the principles of the 15th embodiment described as being applied to the second embodiment above are applied to the applied embodiment. In other words, writes in the applied embodiment proceeds in parallel in the memory devices MCA and MCB as described above. The details can be inferred by persons skilled in the art from the description of the 15th embodiment. 
     &lt;15.4. Advantages&gt; 
     According to the 15th embodiment, the first to 11th embodiments can be applied to each of a plurality of memory devices MC connected to different memory interfaces  25 . Consequently, the same advantages as the applied embodiment are obtained, even in the case where the memory system  100  includes a plurality of memory interfaces  25 . 
     While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.