Patent Publication Number: US-10777578-B2

Title: Three-dimensional memory device and manufacturing method thereof

Description:
CROSS-REFERENCE TO RELATED PATENT APPLICATION 
     This application also claim the priority benefit of a prior application serial no. CN 201711114898.5 filed Nov. 13, 2017. The entirety of the aforementioned patent applications is hereby incorporated by reference herein and made a part of this specification. 
     FIELD OF THE DISCLOSURE 
     The disclosure relates to a three-dimensional memory device and manufacturing method thereof in particular, to a vertical three-dimensional memory device and manufacturing method thereof. 
     BACKGROUND OF THE DISCLOSURE 
     With recent evolvement of electronic devices, it has become a trend to develop memory devices having larger data storage capacity. In order to save data after the power is turned off, non-volatile memories, such as flash memory or ferroelectric random access memory (Fe-RAM), have received more attention. However, in order to process high-speed and large-capacity data, it is necessary to further develop a memory device which operates faster and has larger data storage capacity. 
     Furthermore, the ferroelectric material used in a conventional memory device is usually a material having a perovskite structure. A thickness of the ferroelectric material layer having the perovskite structure has to be greater than 200 nm to allow the ferroelectric material layer to exhibit a ferroelectric characteristic, so that the size of a ferroelectric field effect transistor (FeFET) is difficult to be reduced. 
     However, to replace the material having the perovskite structure with other ferroelectric materials, it is necessary to ensure that the ferroelectric characteristic of the ferroelectric material is unaffected during the fabrication processes or remains unchanged with increase of usage time, otherwise writing, reading and storing of data may be affected. Accordingly, the conventional memory device leaves room for improvement. 
     SUMMARY OF THE DISCLOSURE 
     The present disclosure is to provide a three-dimensional memory device and a manufacturing method thereof, in which the three-dimensional memory device includes vertically stacked memory cells so as to have higher data storage capacity. 
     In order to achieve the aforementioned objects, according to an embodiment of the disclosure, a three-dimensional memory device is provided. The three-dimensional memory device includes a plurality of bottom source lines, a stacked structure, a plurality of bit lines, and a plurality of pillar structures. The bottom source lines extend in a first horizontal direction. The stacked structure is disposed on the bottom source lines and includes a plurality of composite structures which are spaced apart from one another and respectively located at different levels. Each of the composite structures includes a gate conductive layer and a ferroelectric layer surrounding the gate conductive layer. The bit lines are disposed on the stacked structure and extend in a second horizontal direction, and the bit lines traverse the bottom source lines. Each of the pillar structures passes through the stacked structure and is connected between the corresponding bit line and the corresponding bottom source line. Each of the composite structures and the corresponding one of the pillar structures define a memory cell. Each of the pillar structures includes a barrier layer, a gate insulating layer, and a channel layer, and each of the ferroelectric layers and the corresponding one of the gate insulating layers are insulated from each other by the corresponding one of the barrier layers. 
     According to another embodiment of the disclosure, a manufacturing method of a three-dimensional memory device is provided. In the manufacturing method, a plurality of bottom source lines extending in a first horizontal direction are formed. Subsequently, an initial stacked structure on the bottom source lines is formed, in which the initial stacked structure includes a plurality of insulating layers and a plurality of interlayers which are alternately stacked. Thereafter, a plurality of pillar structures passing through the initial stacked structure are formed, in which each of the pillar structures corresponds to at least one of the bottom source lines and includes a barrier layer, a gate insulating layer, and a channel layer. Thereafter, the interlayers of the initial stacked structure are removed, in which the insulating layers and the pillar structures jointly define a plurality of spaces, and each of the spaces being defined by two adjacent insulating layers and the corresponding pillar structure. A plurality of composite structures are formed respectively in the spaces, in which each of the composite structures includes a gate conductive layer and a ferroelectric layer surrounding the gate conductive layer, and the ferroelectric layer is isolated from the gate insulating layer by the barrier layer. A plurality of bit lines extending in a second horizontal direction are formed on the stacked structure, in which each of the pillar structures is connected between the corresponding bit line and the corresponding bottom source line. 
     In the three-dimensional memory device and manufacturing method thereof provided in the embodiments of the present disclosure, each of the pillar structure includes the barrier layer, the gate insulating layer, and the channel layer, and the ferroelectric layer is isolated from the gate insulating layer by the barrier layer. As such, in the manufacturing processes of the three-dimensional device, the barrier layer can prevent atoms in the gate insulating layer from diffusing into the ferroelectric layer, and thus influence on the ferroelectric characteristic of the ferroelectric layer, which is induced by the atoms diffusing from the gate insulating layer, is avoided. In addition, the three-dimensional memory device includes a plurality of memory cells which are vertically stacked and serially connected. As a result, the data storage capacity per unit area is increased. 
     These and other aspects of the present disclosure will become apparent from the following description of the embodiment taken in conjunction with the following drawings and their captions, although variations and modifications therein may be affected without departing from the spirit and scope of the novel concepts of the disclosure. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The present disclosure will become more fully understood from the detailed description and the accompanying drawings, in which: 
         FIG. 1  is a partial top view of a three-dimensional memory device according to an embodiment of the present disclosure. 
         FIG. 2  is a partial sectional view taken along line II-II of  FIG. 1 . 
         FIG. 3  is a flowchart of a manufacturing method of a three-dimensional memory device according to an embodiment of the present disclosure. 
         FIG. 4  is a partial sectional view of the three-dimensional memory device in step S 101  of  FIG. 3 . 
         FIG. 5A  is a partial sectional view of the three-dimensional memory device in step S 102  of  FIG. 3 . 
         FIG. 5B  is a partial top view of the three-dimensional memory device in step S 102  of  FIG. 3 . 
         FIG. 5C  is a partial sectional view of the three-dimensional memory device in step S 102  of  FIG. 3 . 
         FIG. 5D  is a partial sectional view of the three-dimensional memory device in step S 102  of  FIG. 3 . 
         FIG. 5E  is a partial sectional view of the three-dimensional memory device in step S 102  of  FIG. 3 . 
         FIG. 5F  is a partial sectional view of the three-dimensional memory device in step S 102  of  FIG. 3 . 
         FIG. 5G  is a partial sectional view of the three-dimensional memory device in step S 102  of  FIG. 3 . 
         FIG. 6A  is a partial sectional view of the three-dimensional memory device in step S 103  of  FIG. 3 . 
         FIG. 6B  is a partial sectional view of the three-dimensional memory device in step S 103  of  FIG. 3 . 
         FIG. 6C  is a partial top view of the three-dimensional memory device in step S 103  of  FIG. 3 . 
         FIG. 6D  is a partial sectional view of the three-dimensional memory device in step S 103  of  FIG. 3 . 
         FIG. 7A  is a partial sectional view of the three-dimensional memory device in step S 104  of  FIG. 3 . 
         FIG. 7B  is a partial sectional view of the three-dimensional memory device in step S 104  of  FIG. 3 . 
         FIG. 7C  is a partial sectional view of the three-dimensional memory device in step S 104  of  FIG. 3 . 
         FIG. 7D  is a partial sectional view of the three-dimensional memory device in step S 104  of  FIG. 3 . 
         FIG. 8A  is a partial top view of the three-dimensional memory device in step S 105  of  FIG. 3 . 
         FIG. 8B  is a partial sectional view of the three-dimensional memory device in step S 105  of  FIG. 3 . 
     
    
    
     DETAILED DESCRIPTION OF THE EXEMPLARY EMBODIMENTS 
     Referring to  FIG. 1  to  FIG. 2 ,  FIG. 1  is a partial top view of a three-dimensional memory device according to an embodiment of the present disclosure, and  FIG. 2  is a partial sectional view taken along line II-II of  FIG. 1 . 
     A three-dimensional memory device  1  in the embodiment of the present disclosure includes a plurality of bottom source lines SL 1 -SL 2 , a stacked structure  10 , a plurality of bit lines BL 1 -BL 3 , and a plurality of pillar structures T 11 -T 23 . 
     The bottom source lines SL 1 -SL 2  extend in a first horizontal direction D 1  and are arranged in parallel. As shown in  FIG. 1 , the bottom source lines SL 1 -SL 2  in the present embodiment are arranged in parallel along a second horizontal direction D 2 . Furthermore, the bottom source lines SL 1 -SL 2  are disposed on another substrate (not shown in  FIG. 1 ) and spaced from each other. In one embodiment, the three-dimensional memory device  1  further includes a plurality of insulating portions  14 , and each of the insulating portions  14  is disposed between two adjacent bottom source lines SL 1 -SL 2 , so that the two adjacent bottom source lines SL 1 -SL 2  are insulated from each other. In one embodiment, the bottom source lines SL 1 -SL 2  can be made of semiconductor heavily doped with impurities of N-type or P-type conductivity, for example, heavily-doped polysilicon. 
     Furthermore, the stacked structure  10  is disposed on the bottom source lines SL 1 -SL 2 . Reference is made to  FIG. 1 . The stacked structure  10  includes a plurality of cell regions R 1  and a plurality of isolation portions S 1 , and two adjacent cell regions R 1  are spaced apart from each other by one of the isolation portion S 1 . It should be noted that  FIG. 1  only shows one cell region R 1  and two isolation portions S 1  for illustration. As shown in  FIG. 1 , two isolation portions S 1  are respectively located at two opposite sides of the cell region R 1  to define the range of the cell region R 1 . In the embodiment, the isolation portions S 1  can be made of an insulation material, and each of the isolation portions S 1  extends from the top surface to the bottom surface of the stacked structure  10 . 
     Reference is made to  FIG. 2 . In the embodiment, the stacked structure  10  includes a plurality of insulating layers  11  and a plurality of composite structures  12 , in which the composite structures  12  are respectively located at different levels and spaced apart from one another. 
     Specifically, the composite structures  12  and the insulating layers  11  are alternately stacked in a vertical direction. That is to say, any two adjacent composite structures  12  are spaced apart from each other by one of the insulating layers  11 . To be more specific, each of the composite structures  12  is arranged in a space defined by two adjacent insulating layers  11 . Furthermore, each of the composite structures  12  includes a gate conductive layer  120  and a ferroelectric layer  121  surrounding the gate conductive layer  120 . 
     It should be noted that the gate conductive layers  120  which are respectively located at different levels can serve as word lines of the three-dimensional memory device  1 . That is to say, by applying read voltages, write voltages or erase voltages to the gate conductive layers  120  which are located at different levels, the three-dimensional memory device  1  can be read or written. In one embodiment, the gate conductive layers  120  can be made of titanium nitride, tantalum nitride, tungsten nitride, iridium, platinum, palladium or any combination thereof. 
     Each of the ferroelectric layers  121  surrounds the corresponding one of the gate conductive layers  120 . The material of the ferroelectric layer  121  includes a ferroelectric material and dopants. The ferroelectric material can be hafnium oxide, hafnium zirconium oxide, hafnium silicon oxide, or zirconium titanium oxide, and the dopants can be silicon, aluminum, lanthanum, yttrium, strontium, gadolinium, niobium, nickel, tantalum, or any combination thereof. The direction of the resultant electric dipole moment of the ferroelectric layer  121 , i.e., the polarization direction, may be changed according to a voltage applied to the corresponding one of the gate conductive layer  120 . 
     Reference is made to  FIG. 1  again. A plurality of bit lines BL 1 -BL 3  extending in a second horizontal direction D 2  are disposed on the stacked structure  10  and arranged in parallel along the first horizontal direction D 1 . Accordingly, the bit lines BL 1 -BL 3  traverse the bottom source lines SL 1 -SL 2 . As shown in the top view of  FIG. 1 , an intersection is formed between each of the bit lines BL 1 -BL 3  and each of the bottom source lines SL 1 -SL 2 . These intersections are arranged in an array. In the embodiment, the bottom source lines SL 1 -SL 2  and the bit lines BL 1 -BL 3  are both made of heavily-doped semiconductors. In one embodiment, the bottom source lines SL 1 -SL 2  and the bit lines BL 1 -BL 3  are both made of polysilicon heavily doped with impurities of N-type or P-type conductivity. 
     Furthermore, a plurality of pillar structures T 11 -T 23  pass through the stacked structure  10 , and each of the pillar structures T 11 -T 23  is connected between the corresponding one of the bit lines BL 1 -BL 3  and the corresponding one of the bottom source lines SL 1 -SL 2 . As shown in  FIG. 1 , the pillar structures T 11 -T 23  respectively correspond to the intersections and pass through the stacked structure  10 . Moreover, the cell regions R 1  each have the plurality of the pillar structures T 11 -T 23  located therein. In the embodiment shown in  FIG. 1 , six (2 by 3) pillar structures T 11 -T 23  are located in the cell region R 1 . The number of the pillar structures T 11 -T 23  can be determined according to the number of the bottom source lines (two bottom source lines SL 1 -SL 2  are shown in  FIG. 1 ) passing across the cell region R 1 , and the number of the bit lines BL 1 -BL 3  (three bit lines are shown in  FIG. 1 ) passing across the cell region R 1 . 
     However, the number of the pillar structures T 11 -T 23  in each cell region R 1  can be adjusted according to practical demands, and the scope of the disclosure is not limited to that of the example provided herein. The number of the pillar structures in each cell region R 1  can be increased by increasing the number of the bottom source lines SL 1 -SL 2  passing across the cell region R 1  or the number of the bit lines BL 1 -BL 3  passing across the cell region R 1  so as to increase the number of the intersections defined by the bottom source lines SL 1 -SL 2  and the bit lines BL 1 -BL 3 . 
     Referring to  FIG. 2 , each of the pillar structures T 11 -T 23  passes through the composite structures  12  stacked in the vertical direction (Z-direction). Between the composite structures  12  which are stacked vertically and one of the pillar structures T 11 -T 23  which passes through them, a plurality of memory cells C 11 -C 17  which are serially connected are formed. In other words, in one of the cell regions R 1 , each of the composite structures  12  and the corresponding pillar structure (for example, the pillar structure T 11 ) define one of the memory cells C 11 -C 17 . Accordingly, by controlling voltages applied to the gate conductive layers  120 , voltages applied to the corresponding bottom source lines SL 1 -SL 2 , and voltages applied to the corresponding bit lines BL 1 -BL 3 , respectively, the data can be written into or read from the selected one of the memory cells C 11 -C 17 . 
     Referring to  FIG. 2 , it should be noted that the ferroelectric layer  121  of each of the composite structures  12  conformingly covers a part of the side surface of the corresponding one of the pillar structures T 11 -T 23 , an upper surface of one of the insulating layers  11 , and a lower surface of another one of the insulating layers  11 . 
     Furthermore, as shown in  FIG. 2 , each of the pillar structures T 11 -T 23 , from the outside to the inside, sequentially includes a barrier layer  20 , a gate insulating layer  21 , a channel layer  22 , and a core insulation column  23 . 
     In the embodiment of the present disclosure, the outermost layer of each of the pillar structures T 11 -T 33  is the barrier layer  20 . Accordingly, the ferroelectric layer  121  and the gate insulating layer  21  are isolated from each other by the barrier layer  20 . Furthermore, the material of the barrier layer  20  is a conductive material, such as titanium nitride, tantalum nitride, tungsten nitride, iridium, platinum, palladium or any combination thereof. In another embodiment, the material of the barrier layer  20  is heavily-doped semiconductor. Accordingly, in the three-dimensional memory device  1  of the embodiment of the present disclosure, the barrier layer  20  can serve as a floating gate of any one of the memory cells C 11 -C 17 . 
     Accordingly, in one embodiment, when the barrier layer  20  is made of a conductive material, the barrier layer  20  is insulated from both the corresponding one of the bottom source lines SL 1 -SL 2  and the corresponding one of the bit lines BL 1 -BL 3 . To be more specific, in the embodiment, each of the pillar structures T 11 -T 23  further includes a loop-shaped insulating portion  24  to isolate the barrier layer  20  from the corresponding one of the bit lines BL 1 -BL 3 . 
     As shown in  FIG. 2 , each loop-shaped insulating portion  24  is located at one end, which is closer to the bit lines BL 1 -BL 3 , of the corresponding one of the pillar structures T 11 -T 23 . The loop-shaped insulating portion  24  is arranged between the barrier layer  20  and the corresponding one of the bit lines BL 1 -BL 3 . 
     As shown in  FIG. 2 , the gate insulating layer  21  is interposed between the channel layer  22  and the barrier layer  20 , and the channel layer  22  is interposed between the gate insulating layer  21  and the core insulation column  23 . In one embodiment, the material of the gate insulating layer  21  can be silicon nitride, silicon oxide, or the combination thereof, and the material of the channel layer  22  can be lightly-doped polysilicon. Specifically, the material of the channel layer  22  usually has the conductivity type opposite to the conductivity type of the material of the bit line BL 1 -BL 3  (and the bottom source line SL 1 -SL 2 ). For example, when the material of the channel layer  22  is P-type semiconductor, the material of the bit lines BL 1 -BL 3  (and the bottom source line SL 1 -SL 2 ) is N-type semiconductor. 
     Accordingly, in the three-dimensional memory device  1  of the present disclosure, each of the memory cells C 11 -C 17  has a metal-ferroelectric layer-metal-insulator-semiconductor, i.e., MFMIS, structure. 
     Furthermore, it should be noted that if atoms in the gate insulating layer  21  or channel layer  22  diffuse into the ferroelectric layer  121 , the ferroelectric characteristic of the ferroelectric layer  121  are likely to be affected. For example, when the material of the ferroelectric layer  121  is hafnium oxide doped with silicon, the silicon concentration of the ferroelectric layer  121  has to fall within a predetermined range in order for the ferroelectric layer  121  to have a better ferroelectric characteristic. If silicon atoms in the gate insulating layer  21  or in the channel layer  22  diffuse into the ferroelectric layer  121  during the fabrication processes or the operation procedures, the silicon concentration of the ferroelectric layer  121  would be changed so that the ferroelectric characteristic of the ferroelectric layer  121  may not be as anticipated 
     As such, data retention of the three-dimensional memory device  1  may be negatively affected as well. Accordingly, the ferroelectric layer  121  of the embodiment is isolated from the gate insulating layer  21  and the channel layer  22  by the barrier layer  22  to prevent atoms of the gate insulating layer  21  or the channel layer  22  from diffusing into the ferroelectric layer  121 , and thus influence on the ferroelectric characteristic of the ferroelectric layer  121  is avoided. 
     Reference is made to  FIG. 2 . The channel layer  22  is electrically connected between the corresponding one of the bottom source lines SL 1 -SL 2  and the corresponding one of the bit lines BL 1 -BL 3 . In the embodiment, the three-dimensional memory device  1  further includes a dielectric layer  13  disposed on the stacked structure  10 . The dielectric layer  13  is in contact with the bit lines BL 1 -BL 3 , and the dielectric layer  13  has a plurality of openings  13   h  respectively corresponding to the pillar structures T 11 -T 23 . Furthermore, each of the bit lines BL 1 -BL 3  includes a plurality of conductive portions E 1 , and the conductive portions E 1  are respectively filled in the openings  13   h  to be electrically connected to the channel layers  22  of the corresponding pillar structures T 11 -T 23 , respectively. 
     However, in other embodiments, the dielectric layer  13  can be omitted. In this situation, the bit lines BL 1 -BL 3  can be directly disposed on the top insulating layer  11   a  of the insulating layers  11  to be electrically connected to the channel layers  22  of the corresponding pillar structures T 11 -T 23 . 
     Accordingly, during operation of the three-dimensional memory device  1 , by applying the voltages to gate conductive layers  120 , the corresponding one of the bottom source lines SL 1 -SL 2 , and the corresponding one of the bit lines BL 1 -BL 3 , the write states of the memory cells C 11 -C 17  can be controlled. 
     Specifically, the direction of the resultant electric dipole moment of the ferroelectric layer  121  in one of the composite structures  12 , i.e., the polarization direction of the ferroelectric layer  121 , may be changed according to a write voltage applied to the corresponding gate conductive layer  120 . Since the polarization direction of the ferroelectric layer  121  determines the resistance or the conductance of the channel layer  22 , a voltage that is equal to or greater than a threshold voltage is applied to the corresponding gate conductive layer  120  to change the resistance of the channel layer  22 , and thereby to change the write state of one of the memory cells C 11 -C 17 . Subsequently, by measuring the current of the channel layer  22 , the write state (such as “1” or “0”) of the selected memory cell can be determined. 
     One of the memory cells C 11 -C 17  shown in  FIG. 2  is selected as an example to explain the operation principle of the three-dimensional memory device  1  of the embodiment in the present disclosure. In addition, assuming that the material of the channel layer  22  is P-type semiconductor, and the material of the bit lines BL 1 -BL 3  (and the bottom source lines SL 1 -SL 3 ) is N-type semiconductor. In this situation, when a positive bias, which is sufficient for changing the polarization direction of the ferroelectric layer  121 , is applied to the corresponding gate conductive layer  120 , the polarization direction of the ferroelectric layer  121  facilitates electrons to easily accumulate in the channel layer  22 , such that the selected one of the memory cells C 11 -C 17  is set in a first state with better conductivity. 
     Furthermore, when a negative bias, which is sufficient to change the polarization direction of the ferroelectric layer  121 , is applied to the corresponding gate conductive layer  120 , the polarization direction of the ferroelectric layer  121  facilitates electron holes to be formed in the channel layer  22 , such that the selected one of the memory cells C 11 -C 17  is set in a second state with poor conductivity. 
     When reading the three-dimensional memory device  1 , the write states of the memory cells C 11 -C 17  can be determined by measuring the total current of the channel layer  22 . Specifically, by controlling the voltages respectively applied to the gate conductive layers  120 , the voltage applied to the corresponding one of the bottom source lines SL 1 -SL 2  and the voltage applied to the corresponding one of the bit lines BL 1 -BL 3 , the total current of the channel layer  22  can be measured. When the selected one of the memory cells C 11 -C 17  is in the first state of better conductivity, the measured total current would be greater than a predetermined value. On the contrary, when the selected one of the memory cells C 11 -C 17  is in the second state of poor conductivity, the measured total current would be lower than the predetermined value. In one embodiment, the first state can be defined as “1”, and the second state can be defined as “0”. 
     It should be noted that when one of the memory cells C 11 -C 17  is selected, and a read voltage is applied to the gate conductive layer  120  corresponding to the selected one of the memory cells C 11 -C 17 , the read voltage is usually less than the threshold voltage to prevent the polarization direction of the ferroelectric layer  121  from being disturbed. The aforementioned threshold voltage refers to the minimum voltage for changing the polarization direction of the ferroelectric layer  121 . 
     Subsequently, referring to  FIG. 3 ,  FIG. 3  is a flowchart of a manufacturing method of a three-dimensional memory device according to an embodiment of the present disclosure. In step S 100 , a plurality of bottom source lines extending in a first horizontal direction are formed. In step S 101 , an initial stacked structure is formed on the bottom source lines, in which the initial stacked structure includes a plurality of insulating layers and a plurality of interlayers. The insulating layers and interlayers are alternately stacked. 
     In step S 102 , a plurality of pillar structures passing through the initial stacked structure are formed. Each of the pillar structures corresponds to at least one of the bottom source lines and includes a barrier layer, a gate insulating layer, and a channel layer. 
     In step S 103 , the interlayers of the initial stacked structure are removed so as to form a plurality of spaces among the insulating layers and the pillar structures, each of the spaces being defined by two adjacent ones of the insulating layers and the neighboring pillar structure. 
     In step S 104 , a plurality of composite structures is respectively formed in the spaces to form a stacked structure. Each of the composite structures includes a gate conductive layer and a ferroelectric layer surrounding the gate conductive layer, and the ferroelectric layer is isolated from the gate insulating layer by the barrier layer. In step S 105 , a plurality of bit lines extending in a second horizontal direction are formed on the stacked structure, in which each of the pillar structures is connected between the corresponding bit line and the corresponding bottom source line. 
     The details and the processes of the manufacturing method of the three-dimensional memory device according to an embodiment of the present disclosure will be further described in the following description. Reference is made to  FIG. 4 , which is a partial sectional view of the three-dimensional memory device in step S 101  of  FIG. 3 . The bottom source lines SL 1 -SL 2  extend in the first horizontal direction D 1  and are arranged in parallel along a second horizontal direction D 2 . 
     Furthermore, in the step of forming the bottom source lines SL 1 -SL 2 , the manufacturing method of the three-dimensional memory device according to an embodiment of the present disclosure further includes a step of forming a plurality of insulating portions  14 , each of which is disposed between two adjacent bottom source lines SL 1 -SL 2  so that the two adjacent bottom source lines SL 1 -SL 2  are insulated from each other. In one embodiment, the bottom source lines SL 1 -SL 2  are disposed on another substrate (not shown in the drawings). In addition, the bottom source lines SL 1 -SL 2  are made of a conductive material, such as heavily-doped polysilicon. 
     Subsequently, an initial stacked structure  10 ′ is formed on the bottom source lines SL 1 -SL 2 . As shown in  FIG. 4 , the initial stacked structure  10 ′ includes the insulating layers  11  and interlayers  12 ′. The insulating layers  11  and the interlayers  12 ′ are stacked alternately. In the embodiment of the present disclosure, the material of the insulating layers  11  is different from that of the interlayers  12 ′. Furthermore, compared to the insulating layers  11 , the interlayers  12 ′ can have a high etching selectivity. For example, the material of the interlayers  12 ′ can be silicon nitride, and the material of the insulating layers  11  can be silicon oxide. 
     Furthermore, it should be noted that both of the top layer and the bottom layer of the initial stacked structure  10 ′ are insulating layers  11 . That is to say, the insulating layers  11  includes a bottom insulating layer  11   b  located at the bottom side of the initial stacked structure  10 ′, and a top insulating layer  11   a  located at the top side of the initial stacked structure  10 ′. The interlayers  12 ′ are interposed between the top insulating layer  11   a  and the bottom insulating layer  11   b.    
     Subsequently, the details of the step S 102  in  FIG. 3  will be described. Reference is made to  FIG. 5A  and  FIG. 5B .  FIG. 5A  is a partial sectional view of the three-dimensional memory device in step S 102  of  FIG. 3 , and  FIG. 5B  is a partial top view of the three-dimensional memory device in step S 102  of  FIG. 3 . 
     To be more specific, a plurality of pillar-shaped openings H 1  which are separate from one another are formed in the initial stacked structure  10 ′. It should be noted that in the present embodiment, the initial stacked structure  10 ′ has been divided into a plurality of cell regions R 1 , and each of the cell regions R 1  has the pillar-shaped openings H 1  formed therein and spaced apart from one another. In the embodiment of  FIG. 5A  and  FIG. 5B , the pillar-shaped openings H 1  in only one of the cell regions R 1  is illustrated. 
     As shown in  FIG. 5B , each of the pillar-shaped openings H 1  corresponds to one of the bottom source lines SL 1 -SL 2 . In other words, on each of the bottom source lines SL 1 -SL 2 , a number of the pillar-shaped openings H 1  have been formed. Furthermore, referring to  FIG. 5A , each of the pillar-shaped openings H 1  extends from a top surface of the initial stacked structure  10 ′ to the bottom insulating layer  11   b  so that each of the interlayers  12 ′ is exposed from an inner sidewall surface of the corresponding pillar-shaped opening H 1 . 
     Reference is made to  FIG. 5C . Subsequently, a barrier layer  20  is formed on the inner sidewall surface of each of the pillar-shaped openings H 1 . Specifically, an isolation material layer is formed to cover the entire top surface of the initial stacked structure  10 ′ and inner surfaces (which includes the inner sidewall surfaces and bottom surfaces) of the pillar-shaped openings H 1 . Subsequently, portions of the isolation material layer which cover the top surface of the initial stacked structure  10 ′ and the bottom surfaces of the pillar-shaped openings H 1  are removed, and the portions of the isolation material layer covering the inner sidewall surfaces of the pillar-shaped openings H 1  remain to form the barrier layers  20  shown in  FIG. 5C . The material of the barrier layers  20  can be a conductive material, such as titanium nitride, tantalum nitride, tungsten nitride, iridium, platinum, palladium or any combination thereof. 
     Reference is made to  FIG. 5D . Subsequently, an etching step is performed by using the barrier layers  20  as a mask to form extending holes h 1  at the bottom sides of the pillar-shaped openings H 1 . Specifically, portions of the insulating layer  11   b  beneath the pillar-shaped openings H 1  are removed by the etching step so as to partially expose the corresponding bottom source lines SL 1 -SL 2 . Accordingly, each extending hole h 1  extends from the bottom surface of the corresponding pillar-shaped opening H 1  to a top surface of the corresponding bottom source line SL 1  or SL 2 . 
     Subsequently, a pillar portion is formed in each of the pillar-shaped openings H 1 . Reference is made to  FIG. 5E . An initial gate insulating layer  21 ′ and an outer channel portion  22   a  are sequentially formed in each of the pillar-shaped openings H 1  to form a tube-shaped stacked layer. Specifically, the initial gate insulating layer  21 ′ and the outer channel portion  22   a  are formed on the inner sidewalls of the pillar-shaped openings H 1  and the inner walls of the extending holes h 1 . Thereafter, a portion of the tube-shaped stacked layer located at the bottom of the extending hole h 1  is removed. That is to say, only a portion of the initial gate insulating layer  21 ′ and a portion of the outer channel layer  22   a , which cover the bottom surface of the extending hole h 1 , are removed. In the instant embodiment, the outer channel layers  22   a  are made of polysilicon, and the initial gate insulating layers  21 ′ are made of silicon oxide. 
     As shown in  FIG. 5F , an inner channel portion  22   b  is formed in each of the pillar-shaped openings H 1 , and the inner channel portion  22   b  covers the tube-shaped stacked layer and the bottom of the extending hole h 1 . In each pillar-shaped opening H 1 , the outer channel portion  22   a  and the inner channel portion  22   b  jointly form a channel layer  22 . To be more specific, the material of the inner channel layers  22   b  is the same as that of the outer channel layers  22   a . Each channel layer  22  fabricated by the aforementioned steps will be in contact with the corresponding one of the bottom source lines SL 1 -SL 2 . 
     As shown in  FIG. 5F , an insulation material is filled into remaining spaces of the pillar-shaped openings H 1  to form a plurality of core insulating columns  23 . To sum up, by performing the aforementioned steps, a pillar portion (not labelled) can be formed in each of the pillar-shaped openings H 1 . The pillar portion includes the gate insulating layer  21 , the channel layer  22 , and the core insulating column  23 . The channel layer  22  can be in contact with the corresponding one of the bottom source lines SL 1 -SL 2  through the extending hole h 1 . 
     Reference is made to  FIG. 5G . After the steps of forming the pillar portions, portions of the barrier layers  20  located at the top insulating layer  11   a  can be removed so as to form a plurality of loop-shaped openings  11   h  which respectively surround the pillar portions. Subsequently, an insulation material is filled in the loop-shaped openings  11   h  to form a plurality of loop-shaped insulating portions  24 . As such, the barrier layers  20  can be insulated from the bit lines, which will be formed in the following step, by the corresponding loop-shaped insulating portions  24 . In another embodiment, it is also workable to isolate the barrier layers  20  from the bit lines by using other insulating materials to cover the barrier layers, and thus the step of forming the loop-shaped insulating portions  24  can be omitted. 
     By performing the steps shown in  FIG. 5A  to  FIG. 5G , the pillar structures T 11 -T 23  passing through the initial stacked structure  10 ′ can be fabricated. Each of the pillar structures T 11 -T 23  includes the barrier layer  20 , the gate insulating layer  21 , the channel layer  22 , and the core insulating column  23 . Furthermore, as mentioned above, the channel layer  22  of each of the pillar structures T 11 -T 23  is directly connected to the corresponding one of the bottom source lines SL 1 -SL 2 . 
     Reference is made to  FIG. 6A  to  FIG. 6D , which correspond to the step S 103  shown in  FIG. 3 . As shown in  FIG. 6A , in the embodiment, before the step S 103 , a dielectric layer  13  can be formed first to cover the pillar structures T 11 -T 23 . The dielectric layer  13  may be an oxide layer, and the material of the dielectric layer  13  is different from that of the interlayers  12 ′ in the initial stacked structure  10 ′ to prevent the dielectric layer  13  from being removed during subsequent processes. 
     Reference is made to  FIG. 6B  and  FIG. 6C , which respectively show a partial sectional view and a partial top view of the three-dimensional memory device in step S 103  of  FIG. 3 . 
     As shown in  FIG. 6C , a plurality of trenches H 2  extending in the first horizontal direction D 1  are formed in the initial stacked structure  10 ′. Only two trenches H 2  shown in  FIG. 6C  are illustrated. Specifically, the trenches H 2  are formed in the initial stacked structure  10 ′ along predefined boundaries of the cell regions R 1  so that the initial stacked structure  10 ′ is divided into the cell regions R 1  which are spaced apart from one another. 
     As shown in  FIG. 6C , each of the trenches H 2  of the embodiment extends from one side of the initial stacked structure  10 ′ to another opposite side along the first horizontal direction D 1 . Furthermore, as shown in  FIG. 6B , each of the trenches H 2  extends from the top surface of the dielectric layer  13  to the bottom surface of the initial stacked structure  10 ′. As such, each of the interlayers  12 ′ is partially exposed from the sidewall surface of the corresponding trench H 2 . 
     As shown in  FIG. 6D , the interlayers  12 ′ in the initial stacked structure  10 ′ are removed. In the embodiment, since the material of the interlayers  12 ′ is different from that of the insulating layers  11 , the interlayers  12 ′ can be selectively removed by performing a selective etching step such that the insulating layers  11  remain. In one embodiment, when the material of the interlayers  12 ′ is silicon nitride, an etchant, such as phosphoric acid, can be used to remove the interlayers  12 ′. 
     As shown in  FIG. 6D , after the interlayers  12 ′ are removed, the insulating layers  11  and the pillar structures T 11 -T 23  cooperatively define a plurality of spaces  12   h . Each of the spaces  12   h  is defined by two adjacent insulating layers  11  and the neighboring one of the pillar structures T 11 -T 23 . It should be noted that, as shown in  FIG. 6D , in one of the cell regions R 1 , each of the spaces  12   h , which is defined by two adjacent insulating layers  11  (for example, the bottom insulating layer  11   b  and the adjacent insulating layer  11 ) and the neighboring one of the pillar structures T 11 -T 23 , is not blocked off by the neighboring pillar structure and allows a fluid (such as, a gas) to flow therein. 
     Furthermore, the spaces  12   h  which are respectively located at different levels in the same cell region R 1  are separated from one another by the insulating layers  11 , respectively. However, the spaces  12   h  are in spatial communication with one another by the trenches H 2 . 
     Reference is made to  FIG. 7A  to  FIG. 7D , which correspond to the step S 104  shown in  FIG. 3 . As shown in  FIG. 7A , specifically, the step of forming the composite structures includes forming of ferroelectric layers  121  which cover the sidewalls of the trenches H 2 , the upper and lower surfaces of the insulating layers  11 , and portions of the sidewall surfaces of the pillar structures T 11 -T 23 . The ferroelectric layers  121  can be formed by a chemical vapor deposition process. 
     Reference is made to  FIG. 7B . The gate conductive layers  120  are filled into the remaining spaces in the spaces  12   h . It should be noted that the ferroelectric layer  121  that is formed in each space  12   h  defined between two adjacent insulating layers  11  only covers the upper surface of one of the insulting layer  11 , the lower surface of the other insulating layer  11 , and a portion of the sidewall surface of the neighboring one of the pillar structures T 11 -T 23 , but does not fill the entire space  12   h . During the step of forming the gate conductive layers  120 , the remaining spaces between two adjacent insulating layers  11  are filled with the gate conductive layers  120 . 
     Reference is made to  FIG. 7C . Subsequently, portions of the ferroelectric layers  121  and portions of the gate conductive layers  120 , which cover the sidewalls of the trenches H 2 , are removed, such that one composite structure  12  is formed in each of the spaces  12   h . Accordingly, the stacked structure  10  including the plurality of composite structures  12  can be fabricated. In other words, each of the composite structures  12  includes a gate conductive layer  120  and a ferroelectric layer  121  surrounding the gate conductive layer  120 , and the ferroelectric layer  121  can be isolated from the gate insulating layer  21  by the barrier layer  20 . 
     Reference is made to  FIG. 7D . After the composite structures  12  are formed, an isolation material is filled in each of the trenches H 2  so as to form an isolation portion S 1  in each of the trenches H 2 . 
     Reference is made to  FIG. 8A  and  FIG. 8B , which correspond to the step S 105  shown in  FIG. 3 . As shown in  FIG. 8A , a plurality of the bit lines BL 1 -BL 3  extending in the second horizontal direction D 2  are formed on the stacked structure  10 . Furthermore, each of the pillar structures T 11 -T 23  is located at the corresponding one of the intersections where the bit lines BL 1 -BL 3  extend across the bottom source lines SL 1 -SL 2 . Additionally, as shown in  FIG. 8B , each of the pillar structures T 11 -T 23  is connected between the corresponding one of the bit lines BL 1 -BL 3  and the corresponding one of the bottom source lines SL 1 -SL 2 . To be more specific, the channel layer  22  of each of the pillar structures T 11 -T 23  is electrically connected between the corresponding one of the bit lines BL 1 -BL 3  and the corresponding one of the bottom source lines SL 1 -SL 2 . 
     In the embodiment, before the step of forming the bit lines BL 1 -BL 3 , a plurality of openings  13   h  respectively corresponding to the pillar structures T 11 -T 23  are formed in the dielectric layer  13 . Subsequently, a plurality of conductive portions E 1  are formed respectively in the openings  13   h , so that each of the bit lines BL 1 -BL 3  can be electrically connected to the channel layers  22  of the corresponding pillar structures T 11 -T 23 . 
     In another embodiment, if the dielectric layer  13  is not formed in the prior steps, the bit lines BL 1 -BL 3  will be directly formed on the top insulating layer  11   a  so as to be electrically connected to the channel layers  22  of the corresponding pillar structures T 11 -T 23 . 
     According to the manufacturing methods provided in the embodiments of the present disclosure, the three-dimensional memory device can be fabricated. Furthermore, each column of the composite structures  12  in the three-dimensional memory device  1  and the corresponding one of the pillar structures T 11 -T 23  can jointly define the memory cells C 11 -C 17 , each of which has the MFMIS structure. Accordingly, the three-dimensional memory device  1  according to the embodiments of the present disclosure can function as a NAND flash memory. 
     In summary, one of the advantages of the present disclosure is that in the three-dimensional memory device  1  and the manufacturing method thereof, each of the pillar structures T 11 -T 23  includes the barrier layer  20 , the gate insulating layer  21 , and the channel layer  22 , and the ferroelectric layer  121  is isolated from the gate insulating layer  21  by the barrier layer  20 . Accordingly, during the fabrication processes of the three-dimensional memory device  1 , the barrier layer  20  can prevent atoms in the gate insulating layer  21  from diffusing into the ferroelectric layer  121 , and then influence on the ferroelectric characteristic of the ferroelectric layer  121  can be avoided. Furthermore, the three-dimensional memory device  1  of the embodiment in the present disclosure includes the memory cells C 11 -C 17  which are vertically stacked and connected in series, such that the data storage capacity per unit area can be increased. 
     The foregoing description of the exemplary embodiments of the disclosure has been presented only for the purposes of illustration and description and is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. Many modifications and variations are possible in light of the above teaching. 
     The embodiments were chosen and described in order to explain the principles of the disclosure and their practical application so as to enable others skilled in the art to utilize the disclosure and various embodiments and with various modifications as are suited to the particular use contemplated. Alternative embodiments will become apparent to those skilled in the art to which the present disclosure pertains without departing from its spirit and scope.