Patent Publication Number: US-10761982-B2

Title: Data storage device and method for operating non-volatile memory

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This Application claims priority of Taiwan Patent Application No. 106137606, filed on Oct. 31, 2017, the entirety of which is incorporated by reference herein. 
     BACKGROUND OF THE INVENTION 
     Field of the Invention 
     The present invention relates to data storage devices and methods for operating non-volatile memory. 
     Description of the Related Art 
     There are various forms of non-volatile memory (NVM) for long-term data retention, such as flash memory, magnetoresistive RAM, ferroelectric RAM, resistive RAM, spin transfer torque-RAM (STT-RAM), and so on. A non-volatile memory may be combined with a controller to form a data storage device to be accessed by a host. 
     Considering the wear leveling of the different storage cells of a non-volatile memory, the physical space of a non-volatile memory is dynamically allocated for data storage. Thus, the physical space of the non-volatile memory is dynamically mapped to the host-identified logical addresses. A mapping table is required to manage the mapping relationship between logical addresses at the host side and physical space of the non-volatile memory. When performing data writing, a report showing whether or not the write data was successfully written to the non-volatile memory has to be returned immediately to guarantee the reliability of the mapping table. However, frequent reporting may affect the performance of the non-volatile memory. 
     BRIEF SUMMARY OF THE INVENTION 
     A data storage device in accordance with an exemplary embodiment of the disclosure has a non-volatile memory and a controller operating the non-volatile memory. The controller has a microprocessor and a volatile memory. The microprocessor allocates the volatile memory to provide a cache area. According to an asynchronous event request (AER) issued by a host, the microprocessor uses the cache area to collect sections of write data requested by the host, programs the sections of write data collected in the cache area to the non-volatile memory together, and reports failed programming of the sections of write data to the host by asynchronous event request (AER) completion information. 
     In another exemplary embodiment, a method for operating a non-volatile memory is disclosed, comprising: providing at least one volatile memory; allocating the volatile memory to provide a cache area; issuing an asynchronous event request (AER) by a host; and, according to the asynchronous event request, using the cache area to collect sections of write data requested by the host, programming the sections of write data collected in the cache area to the non-volatile memory together, and reporting failed programming of the sections of write data to the host by asynchronous event request completion information. 
     A detailed description is given in the following embodiments with reference to the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The present invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein: 
         FIG. 1  is a block diagram depicting a data storage device  100  in accordance with an exemplary embodiment of the disclosure; 
         FIG. 2  illustrates an open-channel architecture in accordance with an exemplary embodiment of the disclosure; and 
         FIGS. 3A and 3B  are flowcharts illustrating how the host  106  manages a data writing request. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The following description shows exemplary embodiments of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims. 
     A non-volatile memory for long-term data retention may be a flash memory, a magnetoresistive RAM, a ferroelectric RAM, a resistive RAM, a spin transfer torque-RAM (STT-RAM) and so on. A non-volatile memory may be used to implement a data storage device or a data center. The following discussion is regarding flash memory in particular as an example. 
     A flash memory is often used as a storage medium in today&#39;s data storage devices, for implementations of a memory card, a USB flash device, an SSD and so on. In another exemplary embodiment, a flash memory is packaged with a controller to form a multiple-chip package and named eMMC. 
     A data storage device using a flash memory as a storage medium can be applied to a variety of electronic devices, including a smartphone, a wearable device, a tablet computer, a virtual reality device, etc. A calculation module of an electronic device may be regarded as a host that operates a data storage device equipped on the electronic device to access a flash memory within the data storage device. The storage media uses a communication interface (or communication protocol) compatible with the host side to exchange or transmit commands or data. 
     A data center may be built with flash memories as the storage medium. For example, a server may operate an array of SSDs to form a data center. The server may be regarded as a host that operates the SSDs to access the flash memories within the SSDs. 
     The host distinguishes the flash memory storage contents by logical addresses (for example, according to a logical block address LBA or a global host page number GHP, etc.). A flash memory is generally divided into a plurality of blocks. Each block includes a plurality of pages. Each page may be further divided into several storage units. In order to optimize the use of the flash memory, the physical space of the flash memory is dynamically mapped to the host-identified logical addresses. A mapping table, L2P, is required to manage the mapping relationship between logical addresses at the host side and physical space of the non-volatile memory. 
     Various operations of the flash memory need to refer to, or may change the contents of the mapping table. For example, the reading of the flash memory needs to refer to the mapping table, and the writing of the flash memory needs to update the mapping table. To reuse a storage space of a flash memory, the dirty space has to be erased in block units. Since there is an upper limit for the erasures that each block can withstand, the issue of wear leveling for flash memory operations needs to be considered. In addition, data updating is not rewriting the same space. The newer version of data is written to a spare space and the old data is regarded as invalid. A block may sporadically retain valid data, so the demand for garbage collection is correspondingly generated. By garbage collection, the sporadic valid data retained in a block is moved to a spare space. The block with only invalid data left can be erased and released for reuse. The techniques of wearing leveling and garbage collection involve mapping table management. Even other technologies that promote the operational efficiency of flash memory may also be related to the mapping table. How to ensure the accuracy of the mapping table without affecting the system efficiency is an important issue in the technical field. 
       FIG. 1  is a block diagram depicting a data storage device  100  in accordance with an exemplary embodiment of the disclosure. The data storage device  100  has a flash memory  102  and a controller  104 . A host  106  is connected to the data storage device  100  to access the flash memory  102  by operating the controller  104 . 
     The controller  104  includes a microprocessor  112 , a static random access memory (SRAM)  114  and a dynamic random access memory (SRAM)  116 . The (DRAM)  116  is not limited to being combined with the microprocessor  112  in the same package and can be replaced with other storage media. In another exemplary embodiment, the data storage device  100  does not use the dynamic random access memory (DRAM)  116 , and uses the static random access memory (SRAM)  114  as the removed dynamic random access memory (DRAM)  116 . 
     In order to achieve the purpose of the present invention, in this case, the microprocessor  112  uses the static random access memory  114  to record an asynchronous event request (AER) issued by the host  106 . Due to the AER marked in the static random access memory  114 , the microprocessor  112  monitors the execution results of access commands that the host  106  issues to access the flash memory  102 . For example, according to a recorded asynchronous event request (AER), an execution result of a write command requested by the host  106  is monitored. The microprocessor  112  further allocates the dynamic random access memory (DRAM)  116  to provide a cache area  118  as well as manages an error log  120 . Instead of immediately programming (storing) write data of each write command to the flash memory  102 , the microprocessor  112  caches the write data in the cache area  118 . When a specific condition is satisfied, the write data is retrieved from the cache area  118  and programmed to the flash memory  102 . 
     When the write data fails to be programmed to the flash memory  102  (e.g. an error occurs during programming the write data cached in the cache area  118  to the flash memory  102 ), the microprocessor  112  reports the failure to the host  106  by asynchronous event request (AER) completion information which includes the information about the failed programming. When receiving the AER completion information, the host  106  analyzes the AER completion information and executes an appropriate error handling mechanism for this programming failure. Based on the AER design, the host  106  does not need to spend time waiting for the complete execution result of each write command and effectively reduces the latency due to write commands. Thus, data writing of the flash memory  102  is accelerated. Each AER may be paired to one report of AER completion information. Each AER may relate to at least one write command. Each report of AER completion information is preferably generated only when the programming fails. 
     In addition, the microprocessor  112  records details of the programming failure of the flash memory  102  in the error log  120 . The write data failed to be programmed to the flash memory  102  is indicated in the error log  120 . The host  106  may request the microprocessor  112  to return the error log  120  to the host  106 . 
     In an exemplary embodiment, the cache area  118  is an always-on region of the dynamic random access memory (DRAM)  116 . When an unexpected power-off event occurs, the contents of the cache area  118  do not be lost. After the power is restored, the cached write data is programmed to the flash memory  102  and thereby the programming is completed. 
     In an exemplary embodiment, when an unexpected power-off event occurs, the microprocessor  112  executes a cache flushing procedure to program the write data cached in the cache area  118  to a particular block of the flash memory  102 . After the power is restored, the write data programmed in the particular block may be read and cached back to the cache area  118 . 
       FIG. 2  illustrates an open-channel architecture in accordance with an exemplary embodiment of the disclosure. As shown, the host  106  communicates with the controller  104  via a non-volatile memory interface communication protocol NVMe. The controller  104  is electrically connected with the flash memory  102  and provides a NAND flash controller (NFC) to operate the flash memory  102 . In the open-channel architecture, the L2P mapping table is managed in a flash translation layer (FTL) of the host  106 . Thus, in addition to indicating write data, a write command transmitted by the host  106  further indicates a physical address (rather than a logical address of the write data) allocated for the write data. 
     This case effectively balances the immediate update of the L2P mapping table and the acceleration of data writing. The aforementioned asynchronous event request (AER) may be defined by the high-speed non-volatile memory interface NVMe, and failure messages of programming may be defined to form the AER completion information. The host  106  sends an asynchronous event request (AER) to the controller  104  through the high-speed non-volatile memory interface NVMe to speed up the execution of write commands and monitor the programming result. In an exemplary embodiment, considering the programming efficiency, the controller  104  halt the programming on the flash memory  102  until accumulates write data to a predefined amount, for example, 16 KB (e.g. one page), or 64 KB (e.g., one super page across  4  blocks). When the programming fails, the controller  104  informs the host  106  of the failure by AER completion information. The host  106  then starts the subsequent error handling mechanism. 
     After issuing an asynchronous event request (AER), the host  106  may issue a plurality of write commands to the controller  104  corresponding to the AER. Based on the ARE completion information returned from the controller  104 , the host  106  is aware of whether the plurality of write commands fails. When a programming error occurs, the host  106  gets the error log  120  from the controller  104  and starts an error handling mechanism. For example, the host  106  issues another write command to operate the controller  104  to program the write data to the newly-allocated physical address. Note that the host  106  also updates the L2P mapping table managed in the flash memory translation layer FTL. The open-channel architecture that manages the mapping table on the host  106  side thus benefits the control of the flash memory  102 . 
       FIGS. 3A and 3B  are flowcharts illustrating how the host  106  manages a data writing request. In step S 302 , the host  106  sends an asynchronous event request (AER) to the controller  104 . The microprocessor  112  marks the asynchronous event request (AER) in the static random access memory  114 . Due to the marked AER, the controller  104  can use asynchronous event request (AER) completion information to report the failed data programming. 
     In step S 304 , the host  106  issues a write command to the microprocessor  112 . A write command may indicate at least one section of write data and physical addresses allocated to correspond to the different sections of write data. Each section of write data may be allocated to correspond to one particular physical address. The physical address may indicate a storage unit, a page, or a super page of the data storage device  100 . 
     In step  306 , the microprocessor  112  uses the cache area  118  to collect the sections of write data and the physical addresses indicated in the write command. 
     In step S 308 , the microprocessor  112  reports to the host  106  that the write command has been successfully received (e.g. with write data successfully collected in the cache area  118 ). In another exemplary embodiment, the microprocessor  112  may transmit an acknowledgement message back to the host  106  about the success reception of the write command, so that the host  106  proceeds to subsequent operations. 
     By step S 310 , the microprocessor  112  determines whether the accumulated amount of write data cached in the cache area  118  exceeds a predefined amount, such as 16 KB (one page). If not, the flow returns to step S 304  to process the next write command issued by the host  106 . On the contrary, when the accumulated write data exceeds the predefined amount, the flow proceeds to the steps illustrated in  FIG. 3B . 
     Referring to  FIG. 3B , in step S 312 , the microprocessor  112  programs the write data accumulated to the predefined amount to the flash memory  102  according to the physical address indicated in the corresponding write commands. The microprocessor  112  retrieves the write data of the predefined amount from the cache area  118  and programs the retrieved write data of the predefined amount to the flash memory  102 . In an exemplary embodiment, four sections of write data (each section containing 4 KB) are retrieved from the cache area  118  and written to the flash memory  102  according to four physical addresses indicated in the corresponding write commands. The four physical addresses may be sequential addresses or indicate the storage cells within the same page. 
     In step S 314 , the microprocessor  112  monitors whether a programming failure occurs. If yes, step S 316  is performed. The microprocessor  112  records the failed programming in AER completion information, and returns the AER completion information to the host  106 . 
     In step S 318 , the host  106  requests the microprocessor  112  to transmit the error log  120  back. The host  106  is aware of the programming failure by the AER completion information. For the details of the programming failure, the host  106  requests the microprocessor  112  to transmit the error log  120  back. When receiving the request for the error log  120 , the microprocessor  112  may generate the error log  120  and record a command identification number of the failed programming or the physical address of the failed programming in the error log  120 . In another exemplary embodiment, the microprocessor  112  generates the error log  120  in step S 316  rather than in step S 318 . 
     In step S 320 , the microprocessor  112  transmits the error log  120  to the host  106 . Thereafter, the host  106  starts an error handling mechanism. For example, the host  106  outputs another write command to the microprocessor  112  to program the write data of the previously failed programming. Another physical address is indicated in the new write command and the L2P mapping table is updated accordingly. 
     When the microprocessor  112  determines in step S 314  that there is no programming failure, step S 304  is performed to process another write command issued by the host  106 . 
     In addition, there are many ways to transfer commands. The first one is direct transfer without using a queue between the host  106  and the microprocessor  112 . The second one is indirect transfer, by which the commands are pushed into a submission queue, and then the microprocessor  112  is notified to obtain the commands from the submission queue. When the execution of a command is completed, the microprocessor  112  stacks completion elements in a completion queue. The microprocessor  112  further notifies the host  106  to get the completion elements stacked in the completion queue. Based on the completion elements, the host  106  confirms the execution of the command. The direct or indirect transfer of commands is selected according to the user&#39;s needs. 
     A technique that receives commands from a host, collects write data, programs the collected write data to a non-volatile memory in a series, and uniformly returns the programming result of the collected write data is considered within the scope of the disclosure. Based on the above contents, the present invention further relates to methods for operating a non-volatile memory. 
     While the invention has been described by way of example and in terms of the preferred embodiments, it should be understood that the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.