Patent Publication Number: US-2023154796-A1

Title: Plasma diced wafers and methods thereof

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application claims the benefit of U.S. Provisional Application Ser. No. 63/281,031, filed on Nov. 18, 2021, which is incorporated by reference in its entirety for all purposes. 
    
    
     FIELD OF THE INVENTION 
     The present disclosure generally relates to plasma dicing of semiconductor wafers. More specifically, the present disclosure is directed to reliable dies from plasma dicing. 
     BACKGROUND 
     In semiconductor processing, a wafer is processed to form a plurality of devices thereon. After the devices are formed, the wafer is diced to separate the devices into individual dies. Conventional techniques for dicing employ the use of a dicing saw. The saw cuts the wafer along the x-direction and the y-direction saw lines, one at a time, to separate the wafer into individual dies. Sawing, however, takes time, which slows down the processing throughput. In addition, mechanical sawing causes vibration when cutting the wafer. The vibration may cause cracks in the dies, such as the back-end dielectric, which may impact yields negatively. 
     To combat the issues of sawing, plasma dicing has been investigated. Plasma dicing entails mounting a wafer onto a wafer ring and inserting the wafer ring with the wafer into a plasma chamber for etching. Unlike mechanical sawing, the plasma etch process singulates the wafer into individual dies in a single plasma etch step without any vibration issues. This significantly improves throughput as well as avoids reliability issues due to cracking. 
     The present disclosure is directed to reliable plasma dicing of wafers for singulating it into individual dies. 
     SUMMARY 
     Reliable plasma dicing of wafers is disclosed. In one embodiment, the present disclosure is directed to a device. The device includes device opposing top and bottom device surfaces and device sidewall. The device also includes a device substrate with opposing active and inactive substrate surfaces and side substrate surfaces. The inactive substrate surface serves as the bottom device surface. The device also includes a BEOL dielectric having opposing top and bottom BEOL dielectric surfaces and side BEOL surfaces. The device further includes a passivation layer having opposing top and bottom passivation surfaces and side passivation surfaces. The bottom passivation surface is disposed on the top BEOL dielectric surface. The top passivation surface serves as the top device surface. The passivation layer serves as a plasma dicing mask for plasma dicing a wafer with a plurality of devices. The side substrate surfaces, side BEOL surfaces and side passivation surfaces serve as the device sidewalls. The device sidewalls include a first device sidewall portion from the top BEOL surface to an upper portion of the device substrate. The first device sidewall portion is a scalloped device sidewall portion. The device sidewalls also include a second device sidewall portion from a bottom of the upper portion of the device substrate to the bottom substrate surface. The second device sidewall portion is a vertical device sidewall portion. 
     In another embodiment, a method of forming devices is disclosed. The method includes providing a processed wafer processed with a plurality of devices arranged in rows and columns separated by first and second saw streets in first and second orthogonal directions. The processed wafer includes a wafer having opposing inactive and active wafer surfaces. A BEOL dielectric, which includes opposing top and bottom BEOL dielectric surfaces, has its bottom BEOL surface disposed on the active wafer surface. A passivation layer has its bottom passivation surface disposed on the top BEOL dielectric surface. Laser is used to cut the passivation layer to form passivation openings to expose the top BEOL dielectric surface in kerf regions within the first and second saw streets. A first plasma etch is performed to etch a first portion of the processed wafer in the kerf regions from the top BEOL surface to an upper portion of the wafer. The first plasma etch produces scalloped sidewalls in the kerf regions. A second plasma etch is performed to etch a second portion of the processed wafer in the kerf regions. The second portion includes a remaining portion of the wafer from a bottom of the upper portion of the wafer to the inactive wafer surface to singulate the processed wafer into individual devices. The second plasma etch produces vertical sidewalls in the second portion. 
     In yet another embodiment, it relates to a device. The device includes a device substrate, a BEOL dielectric disposed on an active substrate surface of the substrate and a passivation layer disposed on a top passivation surface of the passivation layer. The passivation layer serves as a plasma dicing mask for plasma dicing a wafer with a plurality of devices. Device sidewalls are defined by the side substrate surfaces of the substrate, side BEOL surfaces of the BEOL dielectric and side passivation surfaces of the passivation layer. The device sidewalls include a first device sidewall portion from the top BEOL surface to an upper portion of the device substrate. The first device sidewall portion includes a scalloped device sidewall portion with first plasma etched sidewalls, and a second device sidewall portion from a bottom of the upper portion of the device substrate to the bottom substrate surface. The second device sidewall portion includes a vertical device sidewall portion with second plasma etched sidewalls. 
     These and other advantages and features of the embodiments herein disclosed, will become apparent through reference to the following description and the accompanying drawings. Furthermore, it is to be understood that the features of the various embodiments described herein are not mutually exclusive and can exist in various combinations and permutations. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       In the drawings, like reference characters generally refer to the same parts throughout the different views. Also, the drawings are not necessarily to scale, with emphasis instead generally being placed upon illustrating the principles of the invention. In the following description, various embodiments of the present invention are described with reference to the following drawings, in which: 
         FIG.  1   a    shows a simplified top view of an embodiment of a processed wafer; 
         FIG.  1   b    shows a simplified cross-sectional view of a portion of a processed wafer which includes a saw street between two adjacent dies; 
         FIGS.  2   a - 2   b    show simplified cross-sectional views of embodiments of a plasma diced die after plasma dicing; 
         FIGS.  3   a - 3   c    show simplified cross-sectional views depicting a process for plasma dicing a wafer; and 
         FIGS.  4   a - 4   g    show simplified cross-sectional views depicting another process for plasma dicing a wafer. 
     
    
    
     DETAILED DESCRIPTION 
     Embodiments relate to plasma dicing of wafers into individual dies. The plasma dicing, according to various embodiments, results in reliable plasma diced dies. The present plasma wafer dicing avoids notching on the backside of the wafer or dies, improving process reliability and yields. 
       FIG.  1   a    shows a top view of an embodiment of a wafer  110 . The wafer, as shown, is a semiconductor wafer with first and second major surfaces. On a first or active (frontside) surface, the wafer is processed to form a plurality of dies  120 . The dies, for example, are arranged in rows (x-direction) and columns (y-direction). Separating the rows and columns of dies are first and second saw streets or dicing lines. For example, x-direction dicing line SS x  and y-direction dicing lines SS y  separate the rows and columns of dies on the wafer. 
     A detailed portion  112  of the wafer which includes adjacent dies in the x-direction and y-direction is shown. As shown, a saw street includes a kerf region within the saw street. For example, an x-direction saw street SS x  includes an x-direction kerf region  116   x  disposed within the saw street. Likewise, ay-direction saw street SS y  includes a y-direction kerf region  116   y  within the saw street. In one embodiment, the kerf region may be about 70 to 80% of the saw street width. Other kerf region widths with respect to the width of the saw street may also be useful. 
     As shown, the saw streets are defined by the edges of the dies. A kerf region, as shown, is disposed within the saw streets. Typically, test circuitry is disposed within the kerf region for testing the dies on the wafer. During plasma dicing, the kerf region is removed. For example, the gap region between the kerf region and saw street remains after plasma dicing. Other configurations of the saw streets and kerf regions may also be useful. 
       FIG.  1   b    shows a simplified cross-sectional view of a portion of a processed wafer which includes a saw street between two adjacent dies. As shown, a wafer  110  serves as a substrate for processed dies  120 . In one embodiment, the wafer is processed to form dies in parallel separated by orthogonal saw streets SS in the x-direction and the y-direction. As shown, between the saw streets is the kerf region  116 . Gap regions  117  exist between the saw street and the kerf region. 
     In general, the fabrication of devices may involve the formation of features on a substrate that makes up circuit components, such as transistors, resistors, capacitors as well as other circuit components. The components are interconnected, enabling the device to perform the desired functions. To form the features and interconnections, layers are repeatedly deposited on the substrate and patterned as desired using lithographic techniques. For example, a wafer is patterned by exposing a photoresist layer with an exposure source using a reticle containing the desired pattern. After exposure, the photoresist layer is developed, transferring the pattern of the reticle to the photoresist layer. This forms a photoresist etch mask. An etch is performed using the etch mask to replicate the pattern on the wafer below, which may include one or more layers, depending on the stage of the process. In the formation of the devices, numerous reticles may be used for different patterning processes. 
     In one embodiment, features corresponding to the circuit components are formed in, on or above the surface of the wafer. For example, doped regions serving as wells, S/D contacts and well contacts may be formed by ion implantation processes in the substrate while other features, such as gates, capacitors, resistors, isolation regions and other components, may be formed on and above the surface of the substrate. 
     A back-end-of-line dielectric (BEOL)  130  may be formed on the substrate over the circuit components. The BEOL dielectric layer includes a pre-metal interlayer dielectric (ILD) layer disposed over the circuit components and a plurality of intermetal dielectric (IMD) layers disposed over the pre-metal ILD layer. The number of IMD layers may depend on the CMOS process or technology. 
     The pre-metal ILD layer includes pre-metal contacts which are connected to contact regions of the components. For example, the pre-metal contacts are connected to S/D regions, transistor gates and well contacts. The pre-metal contacts, for example, may be tungsten (W) contacts. Other types of contacts may also be useful. The pre-metal ILD layer may be formed from multiple dielectric layers. Various dielectric materials, such as silicon oxide (SiO 2 ), may be used to form the pre-metal ILD layer. 
     As for an IMD layer, it includes a metal dielectric layer below a via dielectric level. The dielectric layers of the IMD layer may be SiO 2 . Other types of dielectric materials or combinations of dielectric materials or layers may also be useful to form the IMD layer. The metal level includes metal lines and the via level includes via contacts. The uppermost metal level may serve as a pad level in which bond pads for external connections to the dies are disposed. The metal lines and via contacts may be formed using damascene techniques, such as a single or a dual damascene process. In the case of a single damascene process, the contacts and metal lines are formed in separate processes. In the case of a dual damascene process, the metal lines and contacts are formed in the same process. Other configurations of the IMD layers may also be useful. 
     Above the BEOL dielectric is a passivation stack  150 . The passivation stack includes multiple dielectric passivation layers. For example, the passivation layer may include silicon oxide, silicon nitride and/or silicon oxynitride layers. The uppermost layer may be silicon nitride. For example, the uppermost passivation layer can be etched selectively from the BEOL dielectric. Other configurations of the passivation layer or stack may also be useful. The passivation stack protects the die. Bond openings may be formed in the passivation stack to expose the bond pads. Bond openings facilitate interconnecting the die and package substrate during the package assembly process. In one embodiment, the passivation stack is patterned to define openings for plasma dicing of the wafer to singulate it into individual dies. In one embodiment, plasma etch openings correspond to the kerf region within the saw streets. For example, the plasma dicing process removes the kerf regions, leaving the gap regions remaining. 
       FIGS.  2   a - 2   b    show simplified cross-sectional views of embodiments of plasma diced dies after plasma dicing. Referring to  FIG.  2   a   , a simplified cross-section view of an embodiment of a plasma diced die  220  is shown. The cross-section view may be along the x-direction or the y-direction. The die includes a substrate  210  with circuit components. Above the substrate is a BEOL dielectric  230  with interconnections for the circuit components. For example, the BEOL dielectric includes an ILD layer with multiple IMD layers thereover. An uppermost metal level dielectric of the IMD layer may serve as a pad level with bond pads. 
     A passivation stack  250  is disposed over the top of the BEOL dielectric. For example, the passivation stack is disposed over the pad level with bond pads. In one embodiment, the passivation stack includes multiple dielectric passivation layers. For example, the passivation layer may include silicon oxide, silicon nitride and/or silicon oxynitride layers. Other configurations of passivation stacks may also be useful. The passivation stack may include pad openings (not shown) to expose the bond pads for external connections to the internal circuit components of the die. For example, power and input/output (I/O) connections are provided to the die via the bond pads. 
     In one embodiment, the passivation stack includes flat sidewalls  255 . The flat sidewalls, for example, form planar surfaces. For example, the passivation stack includes 2 pairs of opposing flat sidewalls. In one embodiment, the flat sidewalls are in the vertical direction. For example, the vertical sidewall walls are orthogonal to the major surfaces of the wafer or substrate of the die, such as the top or bottom substrate surface. The vertical sidewalls are formed by the mask opening process to define the plasma dicing mask. In one embodiment, the vertical sidewalls are formed by a single laser beam cutting using a single cut. The single cut, for example, may be effected by a single pass or multiple passes. 
     As for the BEOL dielectric and an upper portion of the substrate, they include scalloped sidewalls  219 . The scalloped sidewalls, for example, result from a plasma process using deposition and etch cycles. For example, each cycle of deposition and etch forms 1 scallop shaped sub-portion. The scalloped shaped sidewalls form a first or an upper portion of the die sidewall profile below the passivation stack. In one embodiment, a second or lower portion of the substrate includes flat sidewalls. For example, the lower portion of the substrate includes flat or vertical sidewalls. The vertical sidewalls result from a uni-directional plasma etch process. The lower portion of the substrate forms a second portion of the die sidewall profile below the passivation stack. In one embodiment, the thickness of the second portion of the die sidewall profile may be about 5%-50% of the thickness of the substrate. Other thicknesses for the second portion, such as 5%-20% of the thickness of the substrate, may also be useful. The flat sidewall profile of the second portion prevents backside notching of the die, improving reliability. 
     As described, scalloped sidewalls, although not flat, facilitates forming a vertical or substantially vertical die sidewall. For example, the die sidewall below the passivation layer is effectively vertical (about 90° with respect to the horizontal surfaces of the substrate 0. 
       FIG.  2   b    shows a simplified cross-sectional view of another embodiment of a plasma diced die  220 . The die is similar to that shown in  FIG.  2   a   . Common elements may not be described or described in detail. 
     The die includes a substrate  210  with circuit components and a BEOL dielectric  230  thereon. A passivation stack  250  is disposed over the top of the BEOL dielectric. In one embodiment, the passivation stack includes flat sidewalls  256 . The flat sidewall surface, for example, forms a planar surface. In one embodiment, the flat sidewalls are chamfered passivation sidewalls  256 . For example, the chamfered passivation sidewalls are angled with respect to the first and second major surfaces (e.g., of the wafer of the die. The angle, for example, may be about 50°-60°. Other angles for the chamfered sidewalls may also be useful. The chamfered sidewalls are formed by the mask opening process to define the plasma dicing mask. In one embodiment, the chamfered sidewalls are formed by split-beam laser cutting using multiple cuts. For example, the chamfered sidewalls for formed by laser cutting using 3 cuts. Other numbers of cuts may also be useful. Providing a passivation layer with chamfered sidewalls reduces or prevents cracking of the passivation layer. In addition, the chamfered sidewalls improve plasma dicing since they facilitate the flow of plasma downwards. 
     As for the BEOL dielectric and an upper portion of the substrate, they include scalloped sidewalls  219 . The scalloped shaped sidewalls form a first or upper portion of the die sidewall profile below the passivation stack. In one embodiment, a lower portion of the substrate includes flat sidewalls. For example, the lower portion of the substrate includes flat or vertical sidewalls. The lower portion of the substrate forms a second portion of the die sidewall profile below the passivation stack. The vertical sidewall profile in the lower portion of the substrate prevents backside notching of the die, improving reliability. 
       FIGS.  3   a - 3   c    shows simplified cross-sectional views of an embodiment of a process  300  for plasma dicing a processed wafer to singulate it into individual dies  320 . Illustratively, a portion of the wafer is shown. The portion of the wafer is similar to that shown in  FIG.  1   a    and the dies are similar to the die described in  FIG.  2   a   . Common elements may not be described or described in detail. 
     Referring to  FIG.  3   a   , the portion of the processed wafer shown includes two adjacent dies  320  with a saw street SS therebetween and a kerf region  316  therein. Gap regions  317  separate the edges of the SS and kerf region. The processed wafer includes a wafer  310  processed with circuit components, a BEOL dielectric  330  with interconnects over the wafer and a passivation stack  350  on the BEOL dielectric. 
     In preparation for plasma dicing, the processed wafer is mounted onto an adhesive dicing tape  380 . The tape, for example, may be mounted onto a tape frame (not shown). In one embodiment, the wafer is processed to form mask openings defining plasma dicing channels. In one embodiment, the plasma dicing channels correspond to the kerf regions of the wafer. In one embodiment, laser processing is employed to form the mask openings. For example, a laser beam  370  is used to pattern the passivation stack to form mask openings which expose the kerf regions of the wafer. For example, a single laser beam having the desired with of the kerf region is employed. In one embodiment, the laser beam cuts the passivation stack in the x-direction and y-direction to expose the kerf regions one kerf region at a time. For example, each pass of the laser beam forms one cut to expose one kerf region. In some cases, several laser beam passes can also be used to cut one kerf region. For example, multiple passes may be used to form the cut of the kerf region. 
     In  FIG.  3   b   , the laser beam forms openings in the passivation stack to expose the kerf region  316 . In one embodiment, the laser beam forms mask openings in the passivation stack with flat sidewalls  355 . In one embodiment, the flat sidewalls are vertical sidewalls. The mask opening process is finished when the laser beam cuts the passivation stack so that all kerf regions are exposed. Each kerf region is exposed with one cut of the laser beam. As discussed, a cut can be effected by a single pass or multiple passes of the laser beam. After mask processing is completed, the wafer is transferred to a plasma dicing tool. For example, the wafer is transferred to a plasma chamber of a plasma dicing tool. 
     As shown in  FIG.  3   c   , plasma etching is performed to singulate the processed wafer into individual dies  320 . For example, plasma etches the wafer with the patterned passivation stack  350  serving as a dicing mask. For example, plasma  390  flows downwards to dice the wafer. In one embodiment, the plasma etch process includes first and second processes. 
     In one embodiment, the first etch process forms a first portion of the processed wafer. The first portion of the processed wafer includes the BEOL dielectric  330  and an upper portion of the wafer  310 . In one embodiment, the first plasma process employs deposition and etch cycles. The first plasma process forms die sidewalls with scalloped sidewalls  319 . As the passivation stack serves as an etch mask, it is unaffected by the plasma. Each cycle of deposition and etch forms 1 scallop shaped sub-portion. 
     After the first portion of the processed wafer is etched, the second plasma etch commences to form a second portion of the processed wafer. The second portion includes a lower portion of the wafer  310 . In one embodiment, the second plasma process is a uni-directional plasma etch process, forming flat sidewalls  318  for the lower portion of wafer  310 . In one embodiment, the flat sidewalls are vertical sidewalls. The vertical sidewall profile prevents backside notching of the die, improving reliability. 
       FIGS.  4   a - 4   d    shows simplified cross-sectional views of another embodiment of a process  400  for plasma dicing a processed wafer to singulate it into individual dies  420 . Illustratively, a portion of the processed wafer is shown. The portion of the processed wafer is similar to that shown in  FIG.  1   a   , the dies are similar to the die described in  FIG.  2   b    and the process is similar to that described in  FIGS.  3   a - 3   c   . Common elements may not be described or described in detail. 
     Referring to  FIG.  4   a   , the portion of the processed wafer shown includes two adjacent dies  420  with a saw street SS and a kerf region  416 . Gap regions  417  separate the edges of the SS and kerf region. The processed wafer includes a wafer  410  processed with circuit components, a BEOL dielectric  430  with interconnects over the wafer and a passivation stack  450  on the BEOL dielectric. The processed wafer is mounted onto a dicing tape  480 . The tape, for example, may be mounted onto a tape frame (not shown). 
     In one embodiment, the wafer is processed to form mask openings defining plasma dicing channels which, for example, correspond to the kerf regions of the processed wafer. In one embodiment, laser processing is employed to form the mask openings. For example, a laser beam is used to pattern the passivation stack to form mask openings which expose the kerf regions of the wafer. In one embodiment, the laser beam cuts the passivation stack in the x-direction and y-direction to expose the kerf regions one kerf region at a time. For example, each pass of the laser beam forms one cut to expose one kerf region. In some cases, several laser beam passes can also be used to cut one kerf region. 
     In one embodiment, laser processing includes forming one mask opening (in the x-direction or the y-direction) using multiple passes with a split laser beam  470  to from mask openings having chamfered sidewalls. As shown, a first pass is performed using a split laser beam with first and second beams  4701  and  4702 . The beams are configured to form partial openings in the passivation layer. The outer edges of the partial openings correspond to the outer edges of the kerf region. For example, the pitch of the split beams can be configured to be spaced apart so that the outer edges of the first and second partial openings correspond to the outer edges of the kerf region. 
     In  FIG.  4   b   , the first cut of the laser process using split beams is completed. The first cut forms the first partial openings  453  in the passivation stack  450 . In one embodiment, the partial openings are v-shaped openings. The partial openings extend about 5-10 um into the passivation stack. Extending the partial openings by other depths into the passivation layer may also be useful. The depth, for example, may depend on the thickness of the passivation layer. 
     Referring to  FIG.  4   c   , a second cut of the laser process using split beams is performed. For example, first and second split beams  4701  and  4702  of the laser beam  470  are employed for the second cut. In one embodiment, the second pass continues etching the partial openings. 
     In one embodiment, the split beams are configured with a smaller or narrower pitch to form a W-shaped opening  454 , as shown in  FIG.  4   d   . In one embodiment, the lower vertices of the W-shaped openings extend into the BEOL dielectric. This ensures that the mask opening exposes the kerf region in the BEOL dielectric. The opening, for example, is about 5-10 um into the BEOL dielectric. Extending the opening by other depths into the BOEL dielectric may also be useful. The W-shaped opening includes chamfered sidewalls  456  for the passivation stack  450 . As shown, a notch is disposed between the chamfered sidewalls and extends above the BEOL dielectric. 
     Referring to  FIG.  4   e   , a third cut of the laser or mask opening process is performed. The third cut, for example, employs a single beam or merged split beams. For example, the beam is not split like the first and second passes. As such, the unsplit beam is wider than the split beams. The third cut is configured to remove the notch to complete the mask opening process for the kerf region in the x-direction or y-direction. 
     In  FIG.  4   f   , the third cut is completed, forming a V-shaped opening  455 . The V-shaped opening forms chamfered sidewalls  456  in the passivation stack. The vertex of the V-shaped opening extends into the BEOL dielectric, ensuring complete exposure of the BEOL in the kerf region. The mask opening process is finished when all kerf regions are exposed. After mask processing is completed, the wafer is transferred to a plasma dicing tool. For example, the wafer is transferred to a plasma chamber of a plasma dicing tool. 
     As described, each mask opening for a kerf region is exposed by a 3 step laser cutting process. Other configurations of processing forming mask openings may also be useful. Also, it is understood that the mask processing may perform the first mask opening process for the whole wafer, followed by the second mask opening process for the whole wafer and finally the third mask opening process for the whole wafer. Other configurations of the mask opening process may also be useful. For example, the process may perform the opening of each kerf region, one kerf region at a time. 
     As shown in  FIG.  4   g   , plasma etching is performed to singulate the processed wafer into individual dies  420 . For example, plasma etches the wafer with the patterned passivation stack  450  serving as a dicing mask. For example, plasma  490  flows downwards to dice the wafer. In one embodiment, the plasma etch process includes first and second processes. 
     In one embodiment, the first etch process forms a first portion of the wafer. The first portion of the wafer includes the BEOL dielectric  430  and an upper portion of the wafer  410 . In one embodiment, the first plasma process employs deposition and etch cycles. The first plasma process forms die sidewalls with scalloped sidewalls. As the passivation stack serves as an etch mask, it is unaffected by the plasma. Each cycle of deposition and etch forms 1 scallop shaped sub-portion. 
     After the first portion of the wafer is etched, the second plasma etch commences to form a second portion of the wafer. The second portion includes a lower portion of the wafer  410 . In one embodiment, the second plasma process is a uni-directional plasma etch process, forming flat sidewalls for the lower portion of wafer  410 . In one embodiment, the flat sidewalls are vertical sidewalls. The vertical sidewall profile prevents backside notching of the die, improving reliability. 
     The present disclosure may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The foregoing embodiments, therefore, are to be considered in all respects illustrative rather than limiting the invention described herein. The scope of the invention is thus indicated by the appended claims, rather than by the foregoing description, and all changes that come within the meaning and range of equivalency of the claims are intended to be embraced therein.