Patent Publication Number: US-8996209-B2

Title: Method for operating a railway section and corresponding railway section

Description:
BACKGROUND OF THE INVENTION 
     Field of the Invention 
     The invention relates to a method for operating a railway section with section elements, for example signals, switches, and track vacancy detection devices, which are each activated by a processor that is safe in respect of signaling technology which cyclically executes a test routine, and also to a railway section for carrying out the method. 
     Section elements are understood to be all facilities which are used in the track systems area for the safety and control of rail traffic. These may involve, for example, axle counters, switch drives, signals or track breakage detectors. Usually the section elements and the processors that activate them have power supplied to them permanently, so that they are ready to operate at all times and it is possible to carry out test routines. Axle counters and switch contacts are permanently supplied with a no-load current for example and processors that are safe in respect of signaling, for example in the form of electronic setting units, are switched on all the time. This consumes a great deal of energy. 
     The requirements for signaling safety are defined in CENELEC Standard EN50129,from SIL0—not safe in respect of signaling—to SIL4—highly safe in respect of signaling. Processors that are safe in respect of signaling, according to SIL3 and SIL4 are generally embodied as multichannel processors and carry out test routines cyclically within a defined period of time during the startup phase and after startup. If the cyclic checking is not performed successfully within the defined period of time, safety-relevant operation is no longer possible and as a rule a safety-relevant switch-off is performed. The cyclic checking is carried out in the time windows in which the safe processor does not have to carry out any logic for normal operation. 
     Since the test routines make the startup times very long, for example appr. 30 s, the processor remains permanently switched on for safety&#39;s sake, through which the activated section elements also remain switched on and a high power demand results. 
     BREIF SUMMARY OF THE INVENTION 
     The underlying object of the invention is to specify a generic method for operating a railway section, as well as a railway section suitable for carrying out the method, which make it possible to reduce the power consumption. 
     As regards the method the object is achieved by the processor being operated depending on demand in active mode or in sleep mode, wherein the processor in sleep mode is switched into active mode for the duration of the test routine by means of a timer logic that is safe in respect of signaling technology. 
     The object is also achieved by a railway section for carrying out the method in which the processor is embodied as able to be operated depending on demand in active mode and sleep mode and is switchable during sleep mode into active mode for the duration of the test routine by means of a timer logic that is safe in respect of signaling technology. 
     The fact that the section elements are very largely operated in a low-load state in the sleep mode of the activating processor results in a significant saving in energy and thus in costs. Low-load state can in such cases mean energy-saving mode as a type of standby operation or even a completely no-load state, i.e. switched-off state. Full-load state, i.e. fully functional operating state of the section element, is only provided when actually required, namely only when a rail vehicle needs the respective section element. In this way for example signals can be activated by the processor that is safe in respect of signaling technology such that power is only supplied in the area of visibility of the approaching rail vehicle and the signal, as soon as the visibility area is left, is switched to dark by the processor. 
     Since a true processor start-up time is dispensed with and the processor almost only has to be switched on and is already in the tested state in sleep mode on account of the test routine, it can be ensured that the processor is immediately ready for use after a switch-on request. Only a period of approximately 30 ms is needed for the switching on of the processor, while starting up a processor requires approximately 30 s. The processor that is safe in respect of signaling technology is in the tested state both in active mode and also in sleep mode. In active mode the cyclic testing is undertaken as previously during the time window in which the safe processor does not have to carry out any logic for normal operation. In sleep mode the processor is switched back into active mode by the timer logic that is safe in respect of signaling technology in good time, so that it can execute the cyclic tests even before the defined period of time elapses. The timer logic is preferably embodied as three-channel logic at the SIL4 safety level. 
     By restricting the periods in which the processor and the activated section elements are ready to operate to the periods actually required, a significant saving in energy can be produced, especially for lightly-used sections of line or branch lines. 
     The ready-to-operate state can be established in such cases at any time by a track vacancy detection signal for example. With available track vacancy systems, based on axle counters for example, their very safely created output signal can in this way be almost used other than for its intended purpose or used jointly. 
     In accordance with the claimed invention there is provision for the section elements to be connected to devices for local power supply. In this way, as well as energy savings, a good starting point for future wireless concepts of railway safety technology is produced. Decentralized, i.e. local supply of energy to section elements, for example by means of battery or solar panel, also enables section elements at remote locations to be operated entirely independently of fixed lines or radio channels with fixed assignments. 
     The invention is explained below with reference to diagrams in figures. 
    
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING 
       In the figures: 
         FIG. 1  shows the major modules of a processor that is safe in respect of signaling technology and 
         FIG. 2  shows a multichannel processor architecture. 
     
    
    
     DESCRIPTION OF THE INVENTION 
     The processor  1  that is safe in respect of signaling technology depicted in  FIG. 1  essentially consists of function blocks for the actual processor functionality  2 , an active mode  3  and a sleep mode  4 . The active mode  3  contains logic for cyclic execution of a test routine  5 , through which safety requirements for an SIL3 or SIL0 status of the processor  1  are fulfilled. So that this test routine  5  can also be executed during sleep mode  4 , timer logic  6  is provided in sleep mode  4 , which switches over  7  the processor  1  into the active mode  3  for executing the cyclic test routine  5 . After the ending of the test routine  5 , the processor  1  is switched back B into the sleep mode  4 . In this way the processor  1  is permanently, i.e. even during the sleep mode  4 , in the tested state and can, on request, switch its actual processor functionality  2 , namely the activation of assigned section elements, immediately from sleep mode  4  into active mode  3 . The processor functionality  2  is requested in such cases by a demand-dependent signal from outside, for example by an activated communication signal  9  or by a supervisor signal  10 . Because of the timer logic  6  which starts the test routine  5  in sleep mode  4 , there is no actual processor startup in which the test routine  5  would have to be executed and which would therefore cause an impermissibly long period during which functions of the processor  1  are unavailable. Instead, for demand-dependent switchover from sleep mode  4  into active mode  3 , the processor  1  almost merely has to be woken up. 
       FIG. 2  shows a two-channel processor architecture in conjunction with a three-channel timer logic. Each of the three functionally-identical timer channels  6 . 1 ,  6 . 2  and  6 . 3  is connected in this case to the first  1 . 1  and the second processor channel  1 . 2 . The processor channels  1 . 1  and  1 . 2  in such cases execute the test routine  5 . 1  and  5 . 2  and the demand-dependent processor functionality  2 . 1  and  2 . 2  independently of one another. For unique channel separation resistors  11 . 1 ,  11 . 2  and  11 . 3  are connected upstream from the second processor channel  1 . 2 . 
     Only the processor architecture presented in  FIGS. 1 and 2  guarantees sufficient safety in respect of signaling technology to introduce a sleep mode  4  and thus to significantly reduce the energy requirement of the processor  1  and of the section elements under its control. Ultimately this also produces the possibility of a decentralization, in particular as regards the supply of power, which can for example be based on solar power.