Patent Publication Number: US-9431346-B2

Title: Graphene-metal E-fuse

Description:
BACKGROUND 
     The present invention generally relates to microelectronic interconnect structures, and particularly to hybrid graphene-metal lines. 
     Metal interconnect structures are the primary means of connecting microelectronic devices. Such interconnect structures typically take the shape of wires, trenches, or vias formed in dielectric layers above the microelectronic devices and may typically be formed by depositing a dielectric layer, etching a trench in the dielectric layer and filling the trench with a metal, for example copper. 
     However, as the dimensions of microelectronic devices continue to shrink, metal lines may possess inherent limitations that reduce performance and reliability. For example, the resistivity of metal lines may be too high to effectively transmit current to and from the microelectronic devices. Other materials such a graphene have lower resistivity and can therefore improve device performance. However, graphene presents numerous challenges which discourage its inclusion in typical interconnect structures. Therefore, a method incorporating graphene into metal interconnect structures is desirable. 
     SUMMARY 
     According to one embodiment of the present invention, a structure is provided. The structure may include an M x  level including a first M x  metal, a second M x  metal, and a third M x  metal abutting and electrically connected in sequence with one another, the second M x  metal including graphene; and an M x+1  level above the M x  level, the M x+1  level including an M x+1  metal and a via, the via electrically connects the third M x  metal to the M x+1  metal in a vertical orientation. 
     According to another exemplary embodiment of the present invention, a method is provided. The method may include forming an M x  level including a first M x  metal, a second M x  metal, and a third M x  metal abutting and electrically connected in sequence with one another, the second M x  metal including graphene, and forming an M x+1  level above the M x  level, the M x+1  level including an M x+1  metal and a via, the via electrically connecting the third M x  metal to the M x+1  metal in a vertical orientation. 
     According to another exemplary embodiment of the present invention, a method is provided. The method may include etching, in an M x  dielectric layer, a first trench and a second trench, filling the first trench and the second trench with a metal to form a first M x  metal, and a second M x  metal, and forming a third trench abutting and in between the first M x  metal and the second M x  metal. The method may further include filling the third trench with graphene to form a third M x  metal, the graphene of the third M x  metal is in direct contact with the metal of both the first M x  metal and the second M x  metal, etching, in an M x+1  dielectric layer, a dual damascene opening including a via opening and a trench, the via opening being directly above and exposing an upper surface of the second M x  metal, and filling the via opening and the trench with the metal to form an M x+1  via and an M x+1  metal, the M x+1  via being adjacent to the third M x  metal and in direct contact with the second M x  metal in the M x  dielectric layer. 
    
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
       The following detailed description, given by way of example and not intended to limit the invention solely thereto, will best be appreciated in conjunction with the accompanying drawings, in which: 
         FIG. 1  is a flow chart of a method of forming a hybrid graphene-metal interconnect structure, according to an exemplary embodiment of the present invention; 
         FIG. 2A  is a cross-sectional view of an interconnect structure having an M x  level including an M x  dielectric, a first M x  metal, a second M x  metal, and an M x  capping layer, and an M x+1  level including an M x+1  dielectric, according to an exemplary embodiment of the present invention; 
         FIG. 2B  is a cross-sectional view depicting forming a first trench and a second trench in the M x+1  level, according to an exemplary embodiment of the present invention; 
         FIG. 2C  is a cross-sectional view depicting forming a first M x+1  metal in the first trench of the M x+1  level, a second M x+1  metal in the second trench of the M x+1  level, and an M x+1  capping layer above the M x+1  dielectric, according to an exemplary embodiment of the present invention; 
       FIG. 2D is a cross-sectional view depicting etching a M x+1  line trench in the M x+1  level, according to an exemplary embodiment of the present invention; 
         FIG. 2E  is a cross-sectional view depicting depositing a line barrier layer in the M x+1  line trench, according to an exemplary embodiment of the present invention; 
         FIG. 2F  is a cross-sectional view depicting planarizing the M x+1  level, according to an exemplary embodiment of the present invention; 
         FIG. 2G  is a cross-sectional view depicting filling the M x+1  line trench with graphene, according to an exemplary embodiment of the present invention; 
         FIG. 2H  is a top view depicting the formed graphene line of  FIG. 2G , according to an exemplary embodiment of the present invention; 
         FIG. 2I  is a top view depicting the formed graphene line of  FIG. 2G , according to an exemplary embodiment of the present invention; 
         FIG. 3  is a flow chart of a method of forming a hybrid graphene-metal interconnect structure, according to another exemplary embodiment of the present invention; 
         FIG. 4A  is a cross-sectional view depicting forming a first end trench, a second end trench, and an intermediate trench in the M x+1  level, according to an exemplary embodiment of the present invention; 
         FIG. 4B  is a cross-sectional view depicting forming a first M x+1  end metal in the first end trench of the M x+1  level, a second M x+1  end metal in the second end trench of the M x+1  level, an M x+1  intermediate metal in the intermediate trench of the M x+1  level, and an M x+1  capping layer above the M x+1  dielectric according to an exemplary embodiment of the present invention; 
         FIG. 4C  is a cross-sectional view depicting etching a first M x+1  line trench in the M x+1  level between the first M x+1  end metal and the M x+1  intermediate metal and a second M x+1  line trench in the M x+1  level between the second M x+1  end metal and the M x+1  intermediate metal, according to an exemplary embodiment of the present invention; 
         FIG. 4D  is a cross-sectional view depicting depositing a line barrier layer in the first M x+1  line trench and the second M x+1  line trench, according to an exemplary embodiment of the present invention; 
         FIG. 4E  is a cross-sectional view depicting planarizing the M x+1  level, according to an exemplary embodiment of the present invention; 
         FIG. 4F  is a cross-sectional view depicting filling the first M x+1  line trench and the second M x+1  line trench with graphene, according to an exemplary embodiment of the present invention; 
         FIG. 4G  is a top view depicting the formed hybrid graphene-metal line of  FIG. 4F , according to an exemplary embodiment of the present invention; 
         FIG. 4H  is a top view depicting the formed hybrid graphene-metal line of  FIG. 4F , according to an exemplary embodiment of the present invention; 
         FIG. 5  is a top view depicting a hybrid graphene line including a plurality of metal portions and a plurality of graphene portions, according to an exemplary embodiment of the present invention; 
         FIG. 6  is a cross-sectional view depicting an electronic fuse structure according to an exemplary embodiment of the present invention; 
         FIG. 7  is a cross-sectional view of  FIG. 6  along section line A-A; 
         FIG. 8  is a cross-sectional view depicting an electronic fuse structure according to an exemplary embodiment of the present invention; 
         FIG. 9  is a cross-sectional view of  FIG. 8  along section line B-B; 
         FIG. 10  is a cross-sectional view depicting an electronic fuse structure according to an exemplary embodiment of the present invention; 
         FIG. 11  is a cross-sectional view of  FIG. 10  along section line C-C; 
         FIG. 12  is a cross-sectional view depicting an electronic fuse structure according to an exemplary embodiment of the present invention; and 
         FIG. 13  is a cross-sectional view of  FIG. 6  along section line D-D. 
     
    
    
     Elements of the figures are not necessarily to scale and are not intended to portray specific parameters of the invention. For clarity and ease of illustration, scale of elements may be exaggerated. The detailed description should be consulted for accurate dimensions. The drawings are intended to depict only typical embodiments of the invention, and therefore should not be considered as limiting the scope of the invention. In the drawings, like numbering represents like elements. 
     DETAILED DESCRIPTION 
     Detailed embodiments of the claimed structures and methods are disclosed herein; however, it can be understood that the disclosed embodiments are merely illustrative of the claimed structures and methods that may be embodied in various forms. This invention may, however, be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of this invention to those skilled in the art. In the description, details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the presented embodiments. 
     References in the specification to “one embodiment”, “an embodiment”, “an example embodiment”, etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to affect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described. 
     For purposes of the description hereinafter, the terms “upper”, “lower”, “right”, “left”, “vertical”, “horizontal”, “top”, “bottom”, and derivatives thereof shall relate to the disclosed structures and methods, as oriented in the drawing figures. The terms “overlying”, “atop”, “on top”, “positioned on” or “positioned atop” mean that a first element, such as a first structure, is present on a second element, such as a second structure, wherein intervening elements, such as an interface structure may be present between the first element and the second element. The term “direct contact” means that a first element, such as a first structure, and a second element, such as a second structure, are connected without any intermediary conducting, insulating or semiconductor layers at the interface of the two elements. 
     In the interest of not obscuring the presentation of embodiments of the present invention, in the following detailed description, some processing steps or operations that are known in the art may have been combined together for presentation and for illustration purposes and in some instances may have not been described in detail. In other instances, some processing steps or operations that are known in the art may not be described at all. It should be understood that the following description is rather focused on the distinctive features or elements of various embodiments of the present invention. 
     Embodiments of the invention generally relate to methods of forming hybrid grapheme-metal lines as part of a back-end-of-the-line (BEOL) interconnect level.  FIG. 1  is a flow chart of a method of forming a hybrid graphene-metal line, according to an embodiment of the present invention. Referring to  FIG. 1 , the method  10  includes a step  11 , providing an interconnect structure including an M x  level and an M x+1  level; a step  13 , forming a first trench and a second trench in the M x+1  level; a step  15 , filling the first trench and the second trench with a first M x+1  metal and a second M x+1  metal, respectively; a step  17 , etching a line trench in the M x+1  level spanning from the first M x+1  metal to the second M x+1  metal; a step  19 , depositing a line barrier layer in the line trench; and a step  21 , filling the line trench with graphene. 
     At  11 , described in conjunction with  FIG. 2A , an interconnect structure  100  may be provided. The interconnect structure  100  may include an M x  level  101  and an M x+1  level  201 . The M x  level  101  and the M x+1  level  201  may be any adjacent interconnect levels in the interconnect structure  100 . It should be noted that while only two interconnect levels are shown, the interconnect structure  100  may include multiple interconnect levels below the M x  level  101 . The M x  level  101  may include an M x  dielectric  110 , a first M x  metal  120   a , a second M x  metal  120   b , and an M x  capping layer  130 . In some embodiments, the M x  level  101  may not include the first M x  metal  120   a  and/or the second M x  metal  120   b . The M x+1  level  201  may include an M x+1  dielectric  210 . 
     With continued reference to  FIG. 2A , The M x  dielectric  110  may include any suitable dielectric material, for example, silicon oxide, silicon nitride, hydrogenated silicon carbon oxide, silicon based low-k dielectrics, porous dielectrics, or organic dielectrics including porous organic dielectrics. The M x  dielectric  110  may be formed using known suitable deposition techniques, such as, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition, spin on deposition, or physical vapor deposition (PVD). The M x  dielectric  110  may have a thickness ranging from approximately 70 nm to approximately 140 nm, although greater and lesser thicknesses are explicitly contemplated. 
     With continued reference to  FIG. 2A , the first M x  metal  120   a  and the second M x  metal  120   b  may be, for example, typical lines, vias, or wires found in a typical interconnect structure. The first M x  metal  120   a  and the second M x  metal  120   b  may be made of a conductive interconnect material including, for example, copper, aluminum, or tungsten. The conductive interconnect material may be formed using a filling technique such as electroplating, electroless plating, chemical vapor deposition, physical vapor deposition or a combination of methods. The conductive interconnect material may further include a dopant, such as, for example, manganese, magnesium, copper, aluminum, or other known dopants. In some embodiments, various barriers or liners (not shown) may be formed in the M x  level  101  between first M x  metal  120   a  and the M x  dielectric  110  and between second M x  metal  120   b  and the M x  dielectric  110 . In one embodiment, a liner may include, for example, a tantalum nitride layer, followed by a tantalum layer. Other barrier liners may include manganese, cobalt or ruthenium, either alone or in combination with any other suitable liner. 
     With continued reference to  FIG. 2A , the M x  capping layer  130  may include, for example, silicon nitride, silicon carbide, silicon carbon nitride, hydrogenated silicon carbide, or other known capping materials. The M x  capping layer  130  may have a thickness ranging from approximately 20 nm to approximately 60 nm and ranges there between, although greater and lesser thicknesses are explicitly contemplated. 
     With continued reference to  FIG. 2A , the M x+1  dielectric  210  may be substantially similar to the M x  dielectric  110  described above and may be formed by similar known deposition techniques. Because a portion of the M x+1  dielectric  210  may be removed during subsequent fabrication steps, the M x+1  dielectric  210  may have an initial thickness greater than desired in the ultimate structure. In some embodiments, the M x+1  dielectric  210  may have an initial thickness ranging from approximately 90 nm to approximately 200 nm, although greater and lesser thicknesses are explicitly contemplated. 
     At  13 , described in conjunction with  FIG. 2B , a first trench  220   a  and a second trench  220   b  may be formed in the M x+1  level  201 . The first trench  220   a  and the second trench  220   b  may be formed using a dual damascene process. The first trench  220   a  may include a via portion  224   a  and a line portion  222   a  and the second trench  220   b  may include a via portion  224   b  and a line portion  222   b . Via portions  224   a  and  224   b  may be formed through the M x  capping layer  130  to expose a portion of the first M x  metal  120   a  and the second M x  metal  120   b , respectively. In some embodiments, via portions  224   a  and/or  224   b  may be absent. Line portions  222   a  and  222   b  may have a depth ranging from approximately 50 nm to approximately 160 nm, although greater and lesser thicknesses are explicitly contemplated. Because a portion of line portions  222   a  and  222   b  may be removed during subsequent fabrication steps, Line portions  222   a  and  222   b  may have an initial depth greater than desired in the ultimate structure. 
     At  15 , described in conjunction with  FIG. 2C , a first M x+1  metal  234   a  and a second M x+1  metal  234   b  may be formed in the first trench  220   a  and the second trench  220   b , respectively. The first M x+1  metal  234   a  and the second M x+1  metal  234   b  may be made of a conductive interconnect material, including, for example, gold, copper, aluminum, or tungsten, and may be formed using a filling technique such as electroplating, electroless plating, chemical vapor deposition, physical vapor deposition or a combination of methods. The conductive interconnect material may further include a dopant, such as, for example, manganese (Mn), magnesium (Mg), copper (Cu), aluminum (Al) or other known dopants. 
     With continued reference to  FIG. 2C , liners  232   a  and  232   b  may be formed in the first trench  220   a  and the second trench  220   b , respectively, using typical deposition techniques, such as CVD or ALD, prior to forming the first M x+1  metal  234   a  and the second M x+1  metal  234   b . Liners  232   a  and  232   b  layer may include typical interconnect barrier materials, such as tantalum, tantalum nitride, and combinations thereof or titanium, titanium nitride and combinations thereof. Other liner materials may include manganese, cobalt or ruthenium, either alone or in combination with any other suitable liner. In other embodiments the thin liner layer may be a silicon nitride or SiNCOH layer. Liners  232   a  and  232   b  may have a thickness ranging from approximately 1 nm to approximately 10 nm, although greater and lesser thicknesses are explicitly contemplated. 
     With continued reference to  FIG. 2C , a sacrificial protective layer  240  may be formed above the M x+1  level  201 . While the sacrificial protective layer  240  may be excluded in some embodiments, it may be included to at least protect the first M x+1  metal  234   a  and the second M x+1  metal  234   b  during subsequent processing steps. In some embodiments, the sacrificial protective layer  240  may be substantially similar to the M x  capping layer  130  and be formed using similar methods. In other embodiments, any suitable protective layer may be used. 
     At  17 , described in conjunction with  FIG. 2D , a line trench  250  may be formed in the M x+1  level  201  between the first M x+1  metal  234   a  and the second M x+1  metal  234   b . The line trench  250  may span the distance between the first M x+1  metal  234   a  and the second M x+1  metal  234   b  so that the line trench  250  exposes a portion of the first M x+1  metal  234   a  and the second M x+1  metal  234   b . In an alternate embodiment, the line trench  250  may be etched so that a portion of the liners  232   a  and  232   b  may be preserved between the line trench  250  and the first M x+1  metal  234   a  and the second M x+1  metal  234   b . The line trench  250  may have a depth less than or equal to about 50% of the depth of the line portions  222   a ,  222   b , above. In an embodiment, the line trench  250  may have a depth ranging from approximately 25 nm to approximately 80 nm, measured from the top surface of the dielectric layer  210 , although greater and lesser depths are explicitly contemplated. The line trench  250  may be formed by any suitable anisotropic etching technique, including, for example, reactive ion etching (RIE) or plasma etching. Exemplary etching techniques may be fluorine-based, including, for example, CF 4  plasma etching. 
     At  19 , described in conjunction with  FIG. 2E-2F , a line barrier layer  260  may be formed in the line trench  250 . Referring to  FIG. 2E , the line barrier layer  260  may include a barrier material and a graphene seed material. The barrier material may improve adherence of the graphene seed material to the sidewalls of the line trench  250  while also serving as an electromigration barrier between a graphene line to be subsequently formed in the line trench  250  and the first M x+1  metal  234   a  and the second M x+1  metal  234   b . Exemplary barrier materials include the materials of the liners  232   a  and  232   b , including tantalum, tantalum nitride, and combinations thereof or titanium, titanium nitride and combinations thereof. The graphene seed material may be any material capable of aiding the formation of the graphene line to be subsequently formed in the line trench  250 . In an exemplary embodiment, the graphene seed material may be ruthenium. Alternatively, the graphene seed material may include ruthenium, nickel, palladium, iridium, copper, or any combination thereof. The most appropriate graphene seed material may depend on the specific graphene deposition or growth process used. 
     Referring to  FIG. 2F , the M x+1  level  201  may be planarized using, for example, chemical-mechanical planarization (CMP) to remove excess material from the line barrier layer  260  and the sacrificial protective layer  240 . The CMP process may use the first M x+1  metal  234   a  and the second M x+1  metal  234   b  as a planarization stop, though some amount of overpolishing, resulting in removal of a top portion of first M x+1  metal  234   a  and the second M x+1  metal  234   b , may be acceptable. After planarization, the depth of the line trench  250  may be reduced to a range from approximately 2 nm to approximately 5 nm, including the thickness of the line barrier layer  260 , although greater and lesser depths are explicitly contemplated. 
     At  21 , described in conjunction with  FIG. 2G , a graphene line  270  may be formed in the line trench  250 , so that the graphene line  270  abuts and is electrically connected to the first M x+1  metal  234   a  and the second M x+1  metal  234   b  while being separated from the first M x+1  metal  234   a  and the second M x+1  metal  234   b  by the line barrier layer  260 . The graphene line  270  may be formed using any method known in the art capable of forming a graphene region that conducts electricity between the first M x+1  metal  234   a  and the second M x+1  metal  234   b . In an exemplary embodiment, the graphene line  270  may include multilayer graphene deposited using CVD with either solid or liquid precursors at a temperature ranging from approximately 300° C. and approximately 400° C., although greater and lesser temperatures are explicitly contemplated. It may be preferable to use a graphene formation process within this temperature range or lower to avoid damage to other elements of the interconnect structure  100  or any underlying microelectronic devices (not shown). However, graphene formation processes that require higher temperatures may also be acceptable. In particular, the graphene line  270  may easily be integrated in to current semiconductor process flows. Graphene may be a suitable material from which to form an interconnect structure, unlike carbon nanotubes, because of its 2D characteristics. For example, carbon nanotubes, which have a similar composition to graphene however packaged in a different shape, may not be suitable to form the graphene line  270 . In particular, carbon nanotubes are substantially one dimensional as opposed to graphene layers which are substantially two dimensional, thus affecting electron mobility. Also, purification processes and processing temperatures in excess of 3000° C. may be required to fabricate carbon nanotubes, which may be detrimental to surrounding structures existing at the time of fabrication. 
     With continued reference to  FIG. 2G , the graphene line  270  electrically connects the first M x+1  metal  234   a  and the second M x+1  metal  234   b . In other embodiments where the graphene line  270  is made of multi-layer graphene, current may travel from one graphene layer into another. However, there is generally higher electrical resistance between individual graphene layers. Therefore, current may travel primarily in a direction parallel to the length of the graphene line  270 . 
     After forming the graphene line  270 , an M x+1  capping layer (not shown) and an M x+2  dielectric layer (not shown) may be deposited above the M x+1  dielectric layer and the process described above in conjunction with  FIGS. 2B-2G  may be repeated to form an M x+2  level containing an additional hybrid graphene metal line. Due to the material properties of the graphene line  270 , it may be difficult to form a reliable electrical connection directly to the graphene line  270 . However, because both ends of the graphene line  270  are attached to a metal structure (i.e., the first M x+1  metal  234   a  and the second M x+1  metal  234   b ), it may be possible to avoid making any electrical connections to the graphene line  270 . Instead, electrical connections from the M x+2  level may be made to the first M x+1  metal  234   a  and the second M x+1  metal  234   b.    
       FIGS. 2H-2I  depict top views of  FIG. 2G , according to several embodiments of the present invention. Referring to  FIG. 2H , the graphene line  270  may have a width (x) and the first M x+1  metal  234   a  and the second M x+1  metal  234   b  may have a width of (y), where (x) and (y) are approximately equal. In an exemplary embodiment, (x) may range from approximately 5 nm to approximately 40 nm and (y) may range from approximately 5 nm to approximately 40 nm. However, embodiments where the graphene line  270 , the first M x+1  metal  234   a , and the second M x+1  metal  234   b  have greater or lesser widths are explicitly contemplated. 
     Due to the potentially greater conductivity of the graphene line  270 , the first M x+1  metal  234   a  and the second M x+1  metal  234   b  may restrict the flow of current through the M x+1  level  201  in embodiments where the first M x+1  metal  234   a  and the second M x+1  metal  234   b  have approximately the same width as the graphene line  270 . To improve current flow, in some embodiments the graphene line  270  may have a width (x) and the first M x+1  metal  234   a  and the second M x+1  metal  234   b  may have a width of (z), where (z) is greater than (x). In some embodiments (z) may range from approximately 100% to approximately 300% of (x). In an exemplary embodiment where (z) is approximately 300% of (x), (x) may range from approximately 5 nm to approximately 40 nm and (z) may range from approximately 15 nm to approximately 120 nm, although greater and lesser widths are explicitly contemplated. 
       FIG. 3  is a flow chart of a method of forming a hybrid graphene-metal line, according to an embodiment of the present invention. The hybrid graphene-metal line includes two metal ends and at least one intermediate metal connected to the metal ends by graphene lines. By controlling the lengths of the graphene lines and the intermediate metals, the overall performance of the hybrid graphene-metal line may be increased. 
     Referring to  FIG. 3 , the method  30  includes a step  31 , providing an interconnect structure including an M x  level and an M x+1  level; a step  33 , forming a first end trench, a second end trench, and an intermediary trench in the M x+1  level; a step  35 , filling the first end trench, the second end trench, and the intermediary trench with a first M x+1  end metal, a second M x+1  end metal and an M x+1  intermediary metal, respectively; a step  37 , etching line trenches in the M x+1  level spanning from the first M x+1  end metal to the M x+1  intermediary metal and from spanning from the second M x+1  end metal to the M x+1  intermediary metal; a step  39 , depositing line barrier layers in the line trenches; and a step  41 , filling the line trenches with graphene. 
     At  31 , the interconnect structure  100  described above in conjunction with  FIG. 4A  may be provided. 
     At  33 , described in conjunction with  FIG. 4A , a first end trench  420   a , a second end trench  420   b , and an intermediate trench  420   c  may be formed in the M x+1  level  201 . The first end trench  420   a  and the second end trench  420   b  may be formed by substantially the same methods as the first trench  220   a  ( FIG. 2B ) and the second trench  220   b  ( FIG. 2B ). The intermediate trench  420   c  may be formed in the M x+1  level  201  between the first end trench  420   a  and the second end trench  420   b  using, for example, a dual damascene process. 
     At  35 , described in conjunction with  FIG. 4B , a first M x+1  end metal  434   a , a second M x+1  end metal  434   b , and an M x+1  intermediate metal  434   c  may be formed in the first end trench  420   a , the second end trench  420   b , and the intermediate trench  420   c  respectively. The first M x+1  end metal  434   a , the second M x+1  end metal  434   b , and the M x+1  intermediate metal  434   c  may be made of substantially the same materials and formed by substantially the same methods as the first M x+1  metal  234   a  and a second M x+1  metal  234   b.    
     With continued reference to  FIG. 4B , liners  432   a - 432   c  may be formed in the first end trench  420   a , the second end trench  420   b , and the intermediate trench  420   c , respectively, prior to forming, the first M x+1  end metal  434   a , the second M x+1  end metal  434   b , and the M x+1  intermediate metal  434   c . Liners  432   a - 432   c  may be made of substantially the same materials and formed by substantially the same methods as liners  232   a  and  232   b.    
     With continued reference to  FIG. 4B , a sacrificial protective layer  440  may be formed above the M x+1  level  201 . The sacrificial protective layer  440  may be made of substantially the same materials and formed by substantially the same methods as the sacrificial protective layer  240 . 
     At  37 , described in conjunction with  FIG. 4C , a first line trench  450   a  and a second line trench  450   b  may be formed in the M x+1  level  201 . The first line trench  450   a  may span the distance between the first M x+1  end metal  434   a  and the M x+1  intermediate metal  434   c  so that the first line trench  450   a  exposes a portion of the first M x+1  end metal  434   a  and the M x+1  intermediate metal  434   c . The second line trench  450   b  may span the distance between the second M x+1  end metal  434   b  and the M x+1  intermediate metal  434   c  so that the first line trench  450   b  exposes a portion of the second M x+1  end metal  434   b  and the M x+1  intermediate metal  434   c . The first line trench  450   a  and the second line trench  450   b  may have a depth ranging from approximately 25 nm to approximately 80 nm, measured from the top surface of the dielectric layer  210 , although greater and lesser depths are explicitly contemplated. The first line trench  450   a  and the second line trench  450   b  formed by substantially the same methods as the line trench  250 . 
     At  39 , described in conjunction with  FIG. 4D-4E , a line barrier layer  460  may be formed in the first line trench  450   a  and the second line trench  450   b . The line barrier  460  may be made of substantially the same materials and formed by substantially the same methods as the line barrier layer  260 . 
     Referring to  FIG. 4E , the M x+1  level  201  may be planarized using, for example, chemical-mechanical planarization (CMP) to remove excess material from the line barrier layer  460  and the sacrificial protective layer  440 . The CMP process may use the first M x+1  end metal  434   a  the second M x+1  end metal  434   b , and the M x+1  intermediate metal  434   c  as a planarization stop, though some amount of overpolishing, resulting in removal of a top portion of first M x+1  end metal  434   a , the second M x+1  end metal  434   b , and the M x+1  intermediate metal  434   c  may be acceptable. After planarization, the depth of the line trenches  450   a - 450   b  may be reduced to a range from approximately 2 nm to approximately 5 nm, including the thickness of the barrier layer  460 , although greater and lesser depths are explicitly contemplated. 
     At  41 , described in conjunction with  FIG. 4F , graphene lines  470   a - 470   b  may be formed in the first line trench  450   a  and the second line trench  450   b , so that the graphene lines  470   a - 470   b  abut and are electrically connected to the M x+1  end metal  434   a  the second M x+1  end metal  434   b , and the M x+1  intermediate metal  434   c  while being separated from M x+1  end metal  434   a  the second M x+1  end metal  434   b , and the M x+1  intermediate metal  434   c  by the line barrier layer  460 . The graphene lines  470   a - 470   b  may be made of substantially the same materials and formed by substantially the same methods as the graphene line  270 . 
     After forming the graphene lines  470   a - 470   b , an M x+1  capping layer (not shown) and an M x+2  dielectric layer (not shown) may be deposited above the M x+1  dielectric layer  210  and the process described above in conjunction with  FIGS. 4A-4F  may be repeated to form an M x+2  level containing an additional hybrid graphene metal line. Because both ends of the hybrid graphene metal line of the M x+1  level  201  are metals (i.e., the first M x+1  end metal  434   a  and the second M x+1  end metal  434   b ), it may be possible to avoid making any electrical connections to the graphene lines  470   a - 470   b . Instead, electrical connections from the M x+2  level may be made to the first M x+1  end metal  434   a  and the second M x+1  end metal  434   b.    
       FIGS. 4G-4H  depict top views of  FIG. 4F , according to several embodiments of the present invention. Referring to  FIG. 4G , the first M x+1  end metal  434   a , the second M x+1  end metal  434   b , and the M x+1  intermediate metal  434   c  may have the same width y as the first M x+1  metal  234   a  and the second M x+1  metal  234   b , and the graphene lines  470   a - 470   b  may have the same width x as the graphene line  270 , as depicted in  FIG. 2H . Referring to  FIG. 4H , the first M x+1  end metal  434   a , the second M x+1  end metal  434   b , and the M x+1  intermediate metal  434   c  may have the same width z as the first M x+1  metal  234   a  and the second M x+1  metal  234   b , and the graphene lines  470   a - 470   b  may have the same width x as the graphene line  270 , as depicted in  FIG. 2I . 
     With continued reference to  FIGS. 4G-4H , the first M x+1  end metal  434   a , the second M x+1  end metal  434   b , and the M x+1  intermediate metal  434   c  may have a length (r) and the graphene lines  470   a - 470   b  may have a length (s). In some embodiments, the lengths (r) and (s) may be optimized to improve the reliability of the interconnect structure  100 . For example, one potential issue with metal lines in interconnect structure is electromigration, where the force generated by current flowing through a metal results in distortion of the metal. However, there is a critical length, or electromigration threshold length, below which the effects of electromigration may be negligible in a metal line. The electromigration threshold length may alternatively be referred to and known as a Blech Length. An interconnect or a metal line that has a length smaller than the electromigration threshold length or the Blech Length will not likely fail by electromigration. In such cases, a mechanical stress buildup causes an atom back flow process which reduces or even compensates the effective material flow towards the anode. By keeping the length (r) below this critical length, the impact of electromigration on the first M x+1  end metal  434   a , the second M x+1  end metal  434   b , and the M x+1  intermediate metal  434   c  may be substantially reduced if not eliminated. Further, typical graphene deposition or growth processes may have an increased defect concentration as the length of the graphene layer increases. By controlling the length (s), it may be possible to maintain defect levels in the graphene lines  470   a - 470   b  below a desired concentration. In an exemplary embodiment, the length (r) may range from approximately 5 μm to approximately 20 μm and the length(s) may range from approximately 1 μm to approximately 10 μm, though greater and lesser lengths are explicitly contemplated. 
     Referring to  FIG. 5 , in further embodiments, a hybrid graphene-metal interconnect structure  500  may be formed including a plurality of metal portions  510  and a plurality of graphene portions  520  connecting the plurality of metal portions  510 . The plurality of metal portions will include a first end metal substantially similar to the first M x+1  end metal  434   a  ( FIG. 4F ), a second end metal substantially similar to the second M x+1  end metal  434   b  ( FIG. 4F ), and one or more intermediate metals substantially similar to the M x+1  intermediate metal  434   c  ( FIG. 4F ). Each of the plurality of graphene portions  520  will be substantially similar to the graphene lines  470   a - 470   b . By increasing the number of intermediate metals in the plurality of metal portions and increasing the number of the plurality of graphene portions  520  while maintaining a length (r) for each of the plurality of metal portions  510  and a length (s) for each of the plurality of graphene portions  520 , it may be possible to fabricate a hybrid graphene-metal line of any length while reducing the impact of electromigration in the metal portions and controlling the defect concentration in the plurality of graphene portions  520 . 
     In an alternative embodiment, the advantages of the hybrid graphene metallization scheme described above may be exploited to produce an electronic fuse (e-fuse) having improved characteristics, for example, improved programming reliability, lower programming currents and shorter programming times. 
     The e-fuse is a structure that may be programmed in accordance with the application of a suitable electrical current. For example, an electrical current may be provided through the e-fuse to eventually cause the resistance of the e-fuse to exceed a predetermined threshold. A suitable electrical current depends on the e-fuse design and may range from about 10 mA to about 25 mA, and ranges there between. Alternatively, programming may occur at a threshold current density. For example, a typical current density of 1000 MA/cm 2  may be required to program the e-fuse. Additionally, a circuit is considered to be programmed, and open, when the e-fuse resistance increases more than an order of magnitude over the initial pre-programmed resistance of the e-fuse. 
     During programming of the e-fuse, one or more voids may form in unexpected locations due to non-optimized processing. Location of the voids may be uncontrollable and may affect the yield and reliability of the e-fuse. The voids may be due in part to the electromigration of conductive interconnect material within the e-fuse. 
     The basic principle of the alternative embodiment includes methods of making a hybrid e-fuse structure. The methods result in structures which include a hybrid metallization scheme. Ideally only the targeted e-fuse will be programmed while maintaining the integrity of all surrounding circuits. One embodiment by which to fabricate an e-fuse having hybrid metallization, is described in detail below by referring to the accompanying drawings  FIGS. 6 and 7 . In the present embodiment, a vertical e-fuse may be fabricated in two successive metallization levels, and may include hybrid metallization in direct contact with a via. 
     Referring now to  FIGS. 6 and 7 , a structure  600  is shown.  FIG. 7  is a cross section view, section A-A, of  FIG. 6 . The structure  600  may include an M x  level  602 , an M x+1  level  604 , and an M x+2  level  606 . The M x  level  602  may include a first M x  metal  608 , a second M x  metal  610 , an M x  dielectric layer  612 , and an M x  cap  614 . The M x  level  602  may represent any interconnect level in the structure  600 . In an embodiment, the M x  level  602  may represent a metallization level directly above a contact level or an active device level. The M x+1  level  604  may include a first M x+1  metal  616 , a second M x+1  metal  618 , a third M x+1  metal  620 , an M x+1  dielectric layer  622 , and an M x+1  cap  624 . The M x+2  level  606  may include an M x+2  via  626 , an M x+2  metal  628 , an M x+2  dielectric layer  630 , and an M x+2  cap  632 . It should be noted that while only three interconnect levels are shown, in some embodiments the structure  600  may have multiple interconnect levels either above, below, or above and below the M x  level  602  and the M x+2  level  606 . 
     The M x  dielectric layer  612  may be substantially similar to the M x  dielectric  110  described above. In an embodiment, the M x  dielectric layer  612  may include any suitable dielectric material, for example, silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), hydrogenated silicon carbon oxide (SiCOH), silicon based low k dielectrics, or porous dielectrics. Known suitable deposition techniques, such as, for example, chemical vapor deposition, plasma enhanced chemical vapor deposition, atomic layer deposition, or physical vapor deposition may be used to form the M x  dielectric layer  612 . The M x  dielectric layer  612  may have a typical thickness ranging from about 100 nm to about 450 nm and ranges there between, although a thickness less than 100 nm and greater than 450 nm may be acceptable. 
     The first and second M x  metals  608 ,  610  may be substantially similar to the first and second M x  metals  120   a ,  120   b  described above with reference to  FIG. 2A . In general, the first and second M x  metals  608 ,  610  may be formed using any known technique, and may include any suitable conductive interconnect material, for example, copper, aluminum or tungsten. Both the first and second M x  metals  608 ,  610  may include a typical line or wire found in a typical semiconductor circuit. The first and second M x  metals  608 ,  610  may be substantially similar structures and may be fabricated using, for example, a typical single damascene technique in which a conductive interconnect material may be deposited in a trench formed in the M x  dielectric layer  612 . 
     In an embodiment, the first and second M x  metals  608 ,  610  may include various barrier liners (not shown). One barrier liner may include, for example, tantalum nitride (TaN), followed by an additional layer including tantalum (Ta). One barrier liner may include, for example, titanium (Ti), followed by an additional layer including titanium nitride (TiN). Other barrier liners may include cobalt (Co) or ruthenium (Ru) either alone or in combination with any other suitable liner. The conductive interconnect material may include, for example, copper (Cu), aluminum (Al), or tungsten (W). The conductive interconnect material may be formed using a filling technique such as electroplating, electroless plating, chemical vapor deposition, physical vapor deposition or a combination of methods. The conductive interconnect material may alternatively include a dopant, such as, for example, manganese (Mn), magnesium (Mg), copper (Cu), aluminum (Al) or other known dopants. A seed layer (not shown) may optionally be deposited using any suitable deposition technique, for example chemical vapor deposition or physical vapor deposition, prior to filling the trench. The seed layer may also include similar dopants as the conductive interconnect material. 
     With continued reference to  FIG. 6 , the M x  cap  614  may be deposited over the structure  600 . The M x  cap  614  may electrically insulate the M x  level  602  from additional interconnect levels that may be subsequently formed above the M x  level  602 , for example the M x+1  level  604 . The M x  cap  614  may be used to improve interconnect reliability and prevent copper from diffusing into an M x+1  dielectric that may be subsequently formed above. The M x  cap  614  may be deposited using typical deposition techniques, for example, chemical vapor deposition. The M x  cap  614  may include any suitable dielectric material, for example, silicon nitride (Si 3 N 4 ), silicon carbide (SiC), silicon carbon nitride (SiCN), hydrogenated silicon carbide (SiCH), or other known capping materials. The M x  cap  614  may have a thickness ranging from about 15 nm to about 55 nm and ranges there between, although a thickness less than 15 nm and greater than 55 nm may be acceptable. 
     Next, the M x+1  level  604  may be formed above the M x  level  602 . First, the M x+1  dielectric  622  may be deposited. The M x+1  dielectric  622  may be substantially similar in all respects to the M x  dielectric layer  612  described above. The first M x+1  metal  616 , the second M x+1  metal  618 , the third M x+1  metal  620 , the M x+1  dielectric layer  622 , and the M x+1  cap  624  may be formed in accordance with the techniques described above. More specifically, the first M x+1  metal  616  and the third M x+1  metal  620  may be substantially similar to the first and second M x  metals  608 ,  610  described above. In an embodiment, the first M x+1  metal  616  and the third M x+1  metal  620  may be made of copper fabricated using a single damascene technique. In addition, the second M x+1  metal  618  may be substantially similar, in all respects, to the graphene line  270  described above with reference to  FIGS. 2G, 2H, and 2I . 
     In the present case, the second M x+1  metal  618  may be fabricated such that is abuts and is in electrical contact with each of the first M x+1  metal  616  and the third M x+1  metal  620 . Also, in general, the second M x+1  metal  618  may have cross sectional dimensions smaller than either of the first M x+1  metal  616  or the third M x+1  metal  620 . More specifically, the second M x+1  metal  618  may have a height (h 1 ) approximately 50% less than either a height (h 2 ) of the first M x+1  metal  616  or a height (h 3 ) of the third M x+1  metal  620 . Finally, like the M x  cap  614 , the M x+1  cap  624  may be deposited above the structure  600 . The M x+1  cap  624  may be substantially similar, in all respects, to the M x  cap  614  described above. 
     Next, the M x+2  level  606  may be formed above the M x+1  level  604 . First, the M x+2  dielectric layer  630  may be deposited. The M x+2  dielectric layer  630  may be substantially similar in all respects to the M x  dielectric layer  612  described above. The M x+2  via  626 , the M x+2  metal  628 , the M x+2  dielectric layer  630 , and the M x+2  cap  632  may be formed in accordance with the techniques described above. More specifically, the M x+2  metal  628  may be substantially similar to the first and second M x  metals  608 ,  610  described above. In an embodiment, the M x+2  metal  628  may be made of copper fabricated using a single damascene technique. In addition, the M x+2  via  626  may be formed using a single or dual damascene technique, as describe above with reference to the first and second M x  metals  608 ,  610 . In some cases, both the M x+2  metal  628  and the M x+2  via  626  may be formed simultaneously using a dual damascene techniques as is well known in the art. 
     Vias, generally, may be used to form electrical connections between the metallization of two interconnect levels. The M x+2  via  626  may extend vertically from the third M x  metal  620  up to the M x+2  metal  628 . Generally, the M x+2  via  626  may have a diameter or width of a typical via opening formed in the BEOL. In one embodiment, the M x+2  via  626  may have an aspect ratio of about 4:1 or more, and a diameter or width ranging from about 10 nm to about 100 nm and ranges there between, although a via diameter less than 10 nm and greater than 100 nm may be acceptable. Most typically, the M x+2  via  626  may have a diameter or width less than a width (z) of either the second M x+1  metal  620  or the third M x+1  metal  620 . Finally, like the M x  cap  614 , the M x+2  cap  632  may be deposited above the structure  600 . The M x+2  cap  632  may be substantially similar, in all respects, to the M x  cap  614  described above. 
     In the present embodiment, it should be noted that the hybrid metallization, and more specifically the second M x+1  metal  618  and the third M x+1  metal  620 , may be fabricated in close proximity to the M x+2  via  626  such that the dimensions of the third M x+1  metal  620  remain small enough to substantially reduce or eliminate electromigration effects. If the length of a metal line is less than the “Blech” length, copper ion motion will not occur, shutting down the electromigration process. Mechanical stress at lengths less than the “Blech” length opposes the drift of copper ions. A typical Blech length may be about 10 microns for typical interconnect structures consisting of copper. Therefore, a length (l) of the third M x+1  metal  620  may preferably be less than the Blech length in order to substantially reduce or eliminate electromigration effects. 
     With continued reference to  FIGS. 6 and 7 , a final e-fuse structure is shown according to one embodiment. The first M x+1  metal  616 , the second M x+1  metal  618 , the third M x+1  metal  620 , and the M x+2  via  626  may together form the final e-fuse structure. In the present embodiment the M x+1  via  626  may function as the fuse link and function as a point of failure according to known electromigration failure mechanisms in which the conductive material of the M x+1  via  626  migrates in the path of the flow of electrons and produces a void. More specifically, a void may form at or near a bottom of the M x+1  via  626  as a result of increased current density and heating in the via. Assuming electrons flow from the first M x+1  metal  616  to the M x+2  metal  628 , the addition of the second M x+1  metal  618  between the first M x+1  metal  616  and the third M x+1  metal  620  improves the electromigration resistance of the third M x+1  metal  620 , as described above. Also, assuming a similar current path, the void may typically form at or near a bottom of the M x+1  via  626 . In general, it should be noted that the electromigration resistance of the M x+2  via  626  remains unchanged and may be unaffected by the existence or placement of the second M x+1  metal  618 . 
     Increased electromigration resistance of the third M x+1  metal  620  may help prevent the migration of the conductive interconnect material from the third M x+1  metal  620  to the M x+2  via  626 . This in turn may encourage or enhance the formation of a void to form at or near a bottom of the M x+2  via  626  according to know electromigration failure principles. 
     Stated differently, the existence and placement of the second M x+1  metal  618  may be designed to improve the electromigration resistance of the third M x+2  metal  620  by limiting its size or length (l). By doing so, the conductive material of the third M x+1  metal  620  may not migrate into the M x+2  via  626  and may not backfill any void which may be formed in the M x+2  via  626  due to the effects of electromigration. Therefore, a void may be allowed to form in the M x+2  via  626  and increase the resistance of the e-fuse circuit above some predetermined level to be considered programed as briefly mentioned above. 
     The advantages of the hybrid graphene metallization scheme described above may be exploited to produce an electronic fuse (e-fuse) having improved characteristics according to another embodiment. Another embodiment by which to fabricate an e-fuse having hybrid metallization, is described in detail below by referring to the accompanying drawings  FIGS. 8 and 9 . In the present embodiment, a horizontal e-fuse may be fabricated in a single metallization level including a hybrid metallization scheme. 
     Referring now to  FIGS. 8 and 9 , a structure  700  is shown.  FIG. 9  is a cross section view, section B-B, of  FIG. 8 . The structure  700  may include the Mx level  602 , the M x+1  level  604 , and the M x+2  level  606 . In the present embodiment, the M x  level  602  may include the first M x  metal  608 , the second M x  metal  610 , the M x  dielectric layer  612 , and the M x  cap  614 . Like above, the M x  level  602  may represent any interconnect level in the structure  700 . The M x+1  level  604  may include the first M x+1  metal  616 , a fuse link  702 , the third M x+1  metal  620 , the M x+1  dielectric layer  622 , and the M x+1  cap  624 . The M x+2  level  606 , although not illustrated, may include any assortment of interconnect features, similar but not limited to those described above. The fuse link  702  of the present embodiment may be substantially similar, in all respects, to the graphene line  270  described above with reference to  FIGS. 2G, 2H, and 2I . 
     With continued reference to  FIGS. 8 and 9 , the fuse link  702  may generally have cross sectional dimensions smaller than either of the first M x+1  metal  616  or the third M x+1  metal  620 . The fuse link  702  may be designed with smaller cross sectional dimensions than either of the first M x+1  metal  616  or the third M x+1  metal  620  to intentionally increase the current density within the fuse link  702 . The intentional increase in the current density within the fuse link  702  may be designed such that it causes failure within the fuse link  702 . In one embodiment, the fuse link  702  may have a height (h 4 ) approximately 25% or less than either a height (h 2 ) of the first M x+1  metal  616  or a height (h 3 ) of the third M x+1  metal  620 . For example, in an embodiment, the height (h 2 ) of the first M x+1  metal  616  and the height (h 3 ) of the third M x+1  metal  620  may range from approximately 50 nm to approximately 160 nm, and the height (h 4 ) of the fuse link  702  may range from approximately 2 nm to approximately 5 nm. However, greater or lesser heights are explicitly contemplated. 
     In one embodiment, the fuse link  702  may have a width (w 1 ) approximately 50% or less than either a width (w 2 ) of the first M x+1  metal  616  or a width (w 3 ) of the third M x+1  metal  620 . For example, in an embodiment, the width (w 2 ) of the first M x+1  metal  616  and the width (w 3 ) of the third M x+1  metal  620  may range from approximately 10 nm to approximately 80 nm, and the width (w 1 ) of the fuse link  702  may range from approximately 5 nm to approximately 40 nm. However, greater or lesser widths are explicitly contemplated. 
     In one embodiment, the fuse link  702  may have a length (l 1 ) smaller than either a length (l 2 ) of the first M x+1  metal  616  or a length (l 3 ) of the third M x+1  metal  620 . For example, in an embodiment, the length (l 2 ) of the first M x+1  metal  616  and the length (l 3 ) of the third M x+1  metal  620  may range from approximately 2 μm to approximately 20 μm, and the length (l 1 ) of the fuse link  702  may range from approximately 1 μm to approximately 10 μm. In all cases the fuse link  702  may be less than 10 nm in order to control its temperature and failure. 
     As mentioned above, the current density within the fuse link  702  may be substantially increased due to its reduced dimensions relative to the adjoining metals. For example, the first and second M x+1  metal  616 ,  620  may typically have a current density of approximately 300 MA/cm 2 , and a graphene fuse link  702  may typically have a current density of approximately 12,500 MA/cm 2 . In the present embodiment, the fuse link  702  may have a higher or substantially higher resistance as compared to the first and second M x+1  metal  618 ,  620 . For example, a graphene fuse link  702  may have a resistivity of approximately 10 −6  Ohm cm, which may be approximately 2 times lower than the resistivity of either the first or second M x+1  metal  618 ,  620 . Because of its reduced dimensions and its increased resistance, the fuse link  702  may generate a substantial amount of heat when exposed to a typical programming current. Stated differently, when a typical programming current is applied across the fuse link  702 , a temperature of the fuse link  702  may be approximately 1000° C. or greater. 
     Finally, like the Mx cap  614 , the M x+1  cap  624  may be deposited above the structure  600 . The M x+1  cap  624  may be substantially similar, in all respects, to the M x  cap  614  described above. 
     Referring now to  FIGS. 10 and 11 , a structure  800  is shown.  FIG. 11  is a cross section view, section C-C, of  FIG. 10 . The structure  800  may be substantially similar to the structure  700  depicted in  FIGS. 8 and 9 ; however the fuse link  702  may have an alternative shape. More specifically, as illustrated, the fuse link  702  may have shape similar to that of a bone or the letter “H,” where a center portion is smaller than either end portion. In the present example, the wider end portions of the fuse link  702  may be in direct contact with the first M x+1  metal  616  and the third M x+1  metal  620 . Stated differently, the narrow center portion of the fuse link  702  may be separated from either of the first M x+1  metal  616  or the third M x+1  metal  620  by a wider end portion of the fuse link  702 . The narrow center portion of the fuse link  702  may have a width (w 1 ) similar to that described above. Either end portion of the fuse link  702  may have a width (w 4 ) larger than the width (w 1 ) of the center portion of the fuse link  702 , but smaller than a width (w 2 , w 3 ) of either the first M x+1  metal  616  or the third M x+1  metal  620 . In an embodiment, the widths (w 4 ) of the end portions of the fuse link  702  need not be the same. Either end portion of the fuse link  702  may have a length (l 4 ) smaller than the length (l 1 ) of the center portion of the fuse link  702 , and smaller than a length (l 2 , l 3 ) of either the first M x+1  metal  616  or the third M x+1  metal  620 . 
     Referring now to  FIGS. 12 and 13 , a structure  900  is shown.  FIG. 13  is a cross section view, section D-D, of  FIG. 12 . The structure  900  may be substantially similar to the structure  900  depicted in  FIGS. 10 and 11 ; however the fuse link  702  may have a similar shape with different proportions and dimensions. In the present embodiment, either end portion of the fuse link  702  may have a length (l 4 ) larger than the length (l 1 ) of the center portion of the fuse link  702 , but larger than a length (l 2 , l 3 ) of either the first M x+1  metal  616  or the third M x+1  metal  620 . 
     The embodiments disclosed herein have the capability to improve the failure mechanism of the e-fuse structure by lowering the programming current and reducing the programming times. In turn, effectively improving the reliability and efficiency of the e-fuse structure. 
     The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiment, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein. It is therefore intended that the present invention not be limited to the exact forms and details described and illustrated but fall within the scope of the appended claims.