Patent Publication Number: US-2005138512-A1

Title: Semiconductor integrated circuit

Description:
BACKGROUND OF THE INVENTION  
      1. Field of the Invention  
      The present invention relates to a semiconductor integrated circuit with a scan test function.  
      2. Description of the Related Art  
      Large-scale semiconductor integrated circuits (called ‘LSIs’ herein below) are often provided with a plurality of functions and/or complicated functions. These LSIs have a test circuit that includes a scan path and a scan path register. The test circuit is used to find defects in the LSI during fabrication of the LSI. One of such LSIs is disclosed in Japanese Patent Kokai (Laid Open Publication) No. 2002-296323.  
       FIG. 2  of the accompanying drawings illustrates a schematic configuration of an LSI having scan path registers.  
      This LSI includes an input-side combination circuit  1 A, which is supplied with input data DI 1  to DI x  from an input terminal and generates intermediate signals SA 1  to SA m , an intermediate combination circuit  1 B, which is supplied with intermediate signals S 2   1  to S 2   m  and issues intermediate signals SB 1  to SB n , and an output-side combination circuit  1 C, which is supplied with intermediate signals S 3   1  to S 3   n  and issues output data DO 1  to DO y  to an output terminal. A plurality of signal wires (m signal wires) extend between the combination circuits  1 A and  1 B, and scan path registers (SPR)  2 - 1  to  2 - m  are provided on the m signal wires respectively. Likewise, n signal wires extend between the combination circuits  1 B and  1 C, and scan path registers  3 - 1  to  3 - n  are provided on the n signal wires respectively.  
      All the scan path registers  2 - 1  to  2 - m  and  3 - 1  to  3 - n  have the same constitution. Each scan path register includes a selector for selecting a first signal or a second signal and a flip-flop (hereinafter referred to as ‘FF’) that holds and releases the signal selected by the selector in accordance with a clock signal. Each selector has first and second inputs.  
      The first input of the selector of the scan path register  2 - 1  is supplied with the intermediate signal SA 1  from the combination circuit  1 A. The second input of the selector of the scan path register  2 - 1  is connected to a scan input terminal and is supplied with the signal Sin. The signal produced by the FF of the scan path register  2 - 1  is supplied to the combination circuit  1 B as the intermediate signal S 2 , and is supplied to the second input of the selector of the subsequent (or downstream) scan path register  2 - 2  via a scan path.  
      In a similar manner, the first input of the selector of the scan path register  2 - i  (that is, i=2 to m) is supplied with the intermediate signal SAi from the combination circuit  1 A and the second input of the selector is supplied with the intermediate signal S 2   i-1 , which is produced by the FF of an upstream scan path register  2 -(i- 1 ).  
      The first input of the selector of the scan path register  3 - 1  is supplied with the intermediate signal SB 1  from the combination circuit  1 B, and the second input of the selector is supplied with the intermediate signal S 2   m  from the FF of the scan path register  2 - m . Likewise, the first input of the selector of the scan path register  3 - j  (where j=2 to n) is supplied with the intermediate signal SB j  from the combination circuit  1 B, while the second input of the selector is supplied with the intermediate signal S 2   j-1 , which is generated by the FF of the scan path register  3 -(j- 1 ).  
      The output of the FF of the scan path register  3 - n  is connected to the scan output terminal such that the signal Sout is issued.  
      In an LSI that includes such scan path registers, a fabrication test is performed by means of the following procedure using the scan path registers incorporated beforehand.  
      (1) Serial Input Operation  
      All the selectors of the scan path registers  2 - 1  to  2 - m  and  3 - 1  to  3 - n  are switched to the respective second inputs by means of a control signal (not shown). As a result, all of the scan path registers  2 - 1  to  2 - m  and  3 - 1  to  3 - n  are vertically connected to form an m+n stage shift register. A common clock signal is supplied to the FF of each of the scan path registers  2 - 1  to  2 - m  and  3 - 1  to  3 - n  and a test-pattern signal is inputted to each of the scan path registers  2 - 1  to  2 - m  and  3 - 1  to  3 - n  in series from the scan input terminal Sin in sync with the clock signal. The test pattern is thus held in each of the scan path registers  2 - 1  to  2 - m  and  3 - 1  to  3 - n.    
      (2) Parallel Operation  
      The test pattern is then supplied to the combination circuits  1 B and  1 C as a test signal. Meanwhile, the test pattern is supplied to the combination circuit  1 A in parallel as the input data DI 1  to DI x  from the input terminal. Subsequently, signals corresponding to the inputted test pattern are issued in parallel at the respective outputs of the combination circuits  1 A,  1 B and  1 C.  
      At this time, all of the selectors of the scan path registers  2 - 1  to  2 - m  and  3 - 1  to  3 - n  are switched to the respective first inputs so that the signals from the selectors are supplied to the inputs of the FFs of the corresponding scan path registers  2 - 1  to  2 - m  and  3 - 1  to  3 - n  respectively. Next, by supplying a common clock signal to the FFs, signals issued in parallel by the combination circuits  1 A and  1 B are held in the corresponding FFs. Meanwhile, the output signals of the combination circuit  1 C are issued in parallel from the output terminals as the output data DO 1  to DO y .  
      (3) Serial Output Operation  
      After the signals issued in parallel by the combination circuits  1 A and  1 B are held in the corresponding FFs, the selectors of the scan path registers  2 - 1  to  2 - m  and  3 - 1  to  3 - n  are switched back to the respective second inputs to constitute an m+n stage shift register. A common clock signal is supplied to the FF of each of the scan path registers  2 - 1  to  2 - m  and  3 - 1  to  3 - n . The data held in the FFs of the scan path registers  2 - 1  to  2 - m  and  3 - 1  to  3 - n  are thus issued in series via the scan output terminal Sout in sync with the clock signal.  
      (4) Comparative Judgment Operation  
      Based on circuit constitution information of the combination circuits  1 A,  1 B and  1 C, expectation values for the output data to be generated in response to a predetermined test pattern are compared with the data actually generated in series by the serial output operation ( 3 ) and the output data DO 1  to DO y  of the parallel operation ( 2 ). If the actually generated data match the expectation values, the LSI&#39;s function with respect to the test pattern is judged as normal. A plurality of test patterns is prepared in accordance with the functions targeted for testing, and, when the actual data match the expectation values for all the test patterns, the whole LSI is judged as normal.  
      In order to test the functions of the LSI by using this test circuitry, specific circuit constitution information such as a netlist must be used with respect to the combination circuits  1 A,  1 B, and  1 C beforehand and the test patterns corresponding with a variety of function tests must be prepared together with expectation values for the respective test patterns.  
      However, when a company X fabricates an LSI that incorporates a certain combination circuit upon receiving a license from another company Y, the company X is sometimes unable to obtain specific circuit constitution information of this combination circuit. In this case, a scan separation block is used in order to test the combination circuit and another combination circuit separately.  
       FIG. 3  of the accompanying drawings shows a schematic configuration of an LSI that includes a conventional scan separation block.  
      This LSI includes circuit blocks  10 A and  10 B, and a scan separation block that is constituted by a plurality of scan separation circuits  20 - 1  to  20 - n  connected between the circuit blocks  10 A and  10 B. The scan separation circuits  20 - 1  to  20 - n  are provided for the signals SA 1  to SAn, respectively. The scan separation circuits  20 - 1  to  20 - n  all have the same constitution. Each scan separation circuit includes three selectors  21 ,  22 , and  23  and a single FF  24 . Each selector has two input terminals A and B, and a single output terminal. The FF  24  has an input terminal D and an output terminal.  
      In the scan separation circuit  20 - 1 , the signal SA 1  from the circuit block  10 A is supplied to the input terminal A of the selector  21  and the input terminal A of the selector  22 . The signal S 2   1  for the circuit block  10 B is issued from the output terminal of the selector  21 . The output terminal of the selector  22  is connected to the input terminal B of the selector  23 , and a serial signal Sin from a scan input terminal (not shown) is supplied to the input terminal A of the selector  23 . The output terminal of the selector  23  is connected to the input terminal D of the FF  24 . The output terminal of the FF  24  is connected to the input terminal B of the selector  21  and the input terminal B of the selector  22 . The output terminal of the FF  24  is also connected to the input terminal A of the selector  23  of the subsequent-stage scan separation circuit  20 - 2  so that a serial signal is supplied to the input terminal A of the selector  23  of the downstream scan separation circuit  20 - 2 .  
      The output terminal of the FF  24  in the final-stage scan separation circuit  20 - n  is connected to the input terminals B of the selectors  21  and  22  and to an external device. The output signal from the FF  24  is therefore issued to the external device as a serial signal Sout from the scan output terminal of the LSI.  
      The LSI that includes this type of scan separation block performs the normal operation and the fabrication test. In the normal operation, each selector  21  is switched to the input terminal A. In the fabrication test, the following is conducted.  
      (1) Test for Circuit Block  10 A  
      A test pattern is supplied from the parallel input terminals or scan path registers, as described in connection with  FIG. 2 , to the input (not shown) of the circuit block  10 A. The selectors  22  and  23  of each of the scan separation circuits  20 - 1  to  20 - n  are switched to the input terminals A and B respectively. As a result, the signals SA 1  to SAn, which are generated by the circuit block  10 A, are supplied to the input terminals D of the FFs  24  of the scan separation circuits  20 - 1  to  20 - n , respectively. By supplying a common clock signal to all the FFs  24 , the signals SA 1  to SAn, which are generated in parallel from the circuit block  10 A, are held in the corresponding FFs  24 .  
      Next, the selector  23  of each of the scan separation circuits  20 - 1  to  20 - n  is switched to the input terminal A. As a result, the FFs  24  of the scan separation circuits  20 - 1  to  20 - n  are vertically connected to form an n-stage shift register. A common clock signal is then supplied to the FFs  24  of the scan separation circuits  20 - 1  to  20 - n . Therefore, the data held in the FFs  24  are issued as a serial signal Sout from the scan output terminal in sync with the clock signal.  
      It is then determined whether the combination circuit  11 A is functioning properly by comparing expectation values for the output data to be issued by the circuit block  10 A in response to the test pattern, with the actually issued data (i.e., the serial signal Sout).  
      (2) Test for Circuit Block  10 B  
      The selector  23  in each of the scan separation circuits  20 - 1  to  20 - n  is switched to the input terminal A. As a result, the FFs  24  of the scan separation circuits  20 - 1  to  20 - n  are vertically connected to form an n-stage shift register. A common clock signal is then supplied to the FFs  24  of the scan separation circuits  20 - 1  to  20 - n  and the test-pattern serial signal Sin is inputted from the scan input terminal in sync with the clock signal. As a result, the test patterns are held in the FFs  24  of the scan separation circuits  20 - 1  to  20 - n.    
      Next, the selectors  21 ,  22 , and  23  in each of the scan separation circuits  20 - 1  to  20 - n  are switched to the input terminals B, respectively. As a result, the test patterns held in the FFs  24  are supplied in parallel to the input side of the circuit block  10 B.  
      The signals that are generated in parallel from the output side (not shown) of the circuit block  10 B that correspond with the supplied test patterns are read by the parallel output terminals or scan path registers, as described in connection with  FIG. 2 . It is then determined whether the circuit block  10 B is functioning properly by comparing expectation values for the output data to be generated by the circuit block  10 B in response to the test pattern with the actually generated data.  
      In the conventional test performed on the circuit blocks  10 A and  10 B in the LSI that includes the scan separation circuits  20 , a test for the signal path that passes through the input terminal A of the selector  21  in each scan separation circuit  20  is not performed. Hence, the test on the circuit blocks  10 A and  10 B is unable to detect a fault in the signal path passing through the input terminal A of the selector  21  in the scan separation circuit  20 . Therefore, even if the LSI is judged as normal in the test, the LSI sometimes malfunctions. This malfunctioning is often found after the LSI is incorporated in another device.  
     SUMMARY OF THE INVENTION  
      According to one aspect of the present invention, there is provided a semiconductor integrated circuit that includes a first circuit block, a second circuit block, and a scan separation block provided between the first and second circuit blocks. The scan separation block passes a signal between the first and second circuit blocks during normal operation, and separates the first and second circuit blocks from each other during a test operation. The scan separation block includes at least one first scan separation circuit. Each first scan separation circuit has a first holding circuit for holding a first test signal in sync with a clock and a first selector for selecting either a second signal issued by the first circuit block or the first test signal issued by the first holding circuit. The first selector is connected between the second circuit block and the first holding circuit. An output of the first selector is also inputted to the first holding circuit.  
      The scan separation circuit of the LSI has the holding circuit for holding a signal that is selected by the selector and then issued to another circuit block. The signal path from one circuit block to the other circuit block can therefore be tested by means of a scan test.  
      Preferably, the first and second circuit blocks are connected to each other by a plurality of signal wires. Preferably, one scan separation circuit is provided on each signal wire. The scan separation circuits may be connected to form a multi-stage structure.  
      The scan separation block may include at least one second scan separation circuit. Each second scan separation circuit may include a second selector and a second holding circuit. The second selector may select either a test signal supplied by an external input terminal (or the test signal supplied from the earlier-stage scan separation circuit) or the signal selected by the first selector. The second holding circuit may hold the output signal of the second selector in accordance with a clock signal and supply this output signal to the first selector as the test signal. The second holding circuit may also issue the test signal to the external output terminal or to the second selector of the subsequent-stage scan separation circuit.  
      Other objects, aspects and advantages of the present invention will become apparent to those skilled in the art to which the present invention pertains from the following detailed description and appended claims when read and understood in conjunction with the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       FIG. 1  illustrates a schematic configuration of an LSI that includes a scan separation block according to an embodiment of the present invention;  
       FIG. 2  illustrates a schematic configuration of an LSI that includes one scan path register; and  
       FIG. 3  illustrates a schematic configuration of an LSI that includes a conventional scan separation block. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION  
      Referring to  FIG. 1 , an LSI having a scan separation block according to an embodiment of the present invention will be described. Similar reference numerals and symbols are used in FIGS.  1  to  3 .  
      This LSI includes circuit blocks  10 A and  10 B, and a scan separation block  50  that connects the circuit blocks  10 A and  10 B. The scan separation block  50  is constituted by a first group of scan separation circuits  30 - 1  to  30 - m  and a second group of scan separation circuits  40 - 1  to  40 - n . The scan separation circuits  30 - 1  and  30 - m  are respectively provided for the signals SA 1  to SAm that are issued to the circuit block  10 B from the circuit block  10 A. The scan separation circuits  40 - 1  to  40 - n  are respectively provided for the signals SB 1  to SBn that are issued to the circuit block  10 A from the circuit block  10 B.  
      The scan separation circuits  30 - 1  to  30 - m  have the same constitution. Each scan separation circuit includes two selectors  31  and  32  and one FF  33 . Each selector has an input terminal A and an input terminal B.  
      In the scan separation circuit  30 - 1 , the signal SA 1  from the circuit block  10 A is supplied to the input terminal A of the selector  31  and the signal S 3   1  for the circuit block  10 B is issued from the output terminal of the selector  31 . The signal S 3   1  is also supplied to the input terminal B of the selector  32  and the serial signal SAin from the scan input terminal (SAin) is supplied to the input terminal A of the selector  32 . The output terminal of the selector  32  is connected to the input terminal D of the FF  33 . The output terminal of the FF  33  is connected to the input terminal B of the selector  31  and to the input terminal A of the selector  32  of the subsequent-stage scan separation circuit  30 - 2 . A serial signal is introduced to the input terminal A of the selector  32  of the downstream scan separation circuit  30 - 2  from the FF  33  of the scan separation circuit  30 - 1 .  
      The output terminal of the FF  33  in the final-stage scan separation circuit  30 - m  is connected to the input terminal B of the selector  31  and is connected to the scan output terminal such that a serial signal SAout is issued to the scan output terminal.  
      Each of the scan separation circuits  40 - 1  to  40 - n  has a similar constitution to the scan separation circuit  30  and includes two selectors  41  and  42  and one FF  43 . These scan separation circuits  40 - 1  to  40 - n  are also connected vertically in the same manner as the scan separation circuits  30 - 1  to  30 - m , such that a serial signal SBin from the scan input terminal is supplied to the initial-stage scan separation circuit  40 - 1 , and the final-stage scan separation circuit  40 - n  is connected to the scan output terminal such that a serial signal SBout is issued to the scan output terminal.  
      Next, the operation of the LSI that includes the scan separation block  50  will be described.  
      (1) Normal Operation  
      The selector  31  of each of the scan separation circuits  30 - 1  to  30 - m  is switched to the input terminal A, and the selector  41  of each of the scan separation circuits  40 - 1  to  40 - n  is switched to the input terminal A. As a result, the signals SA 1  to SAm generated by the circuit block  10 A are supplied to the circuit block  10 B as the signals S 3   1  to S 3   m  respectively after passing via the selectors  31  of the scan separation circuits  30 - 1  to  30 - m  respectively. The signals SB 1  to SBn generated by the circuit block  10 B are supplied to the circuit block  10 A as the signals S 4   1  to S 4   n  respectively after passing via the selectors  41  of the scan separation circuits  40 - 1  to  40 - n  respectively.  
      (2) Test for Circuit Block  10 A  
      A test pattern is supplied to the input side (not shown) of the circuit block  10 A.  
      The selector  42  of each of the scan separation circuits  40 - 1  to  40 - n  is switched to the input terminal A. As a result, the FFs  43  of the scan separation circuits  40 - 1  to  40 - n  are vertically connected to form an n-stage shift register. A common clock signal CKB is then supplied to the FFs  43  of the scan separation circuits  40 - 1  to  40 - n . The test-pattern serial signal SBin from the scan input terminal is introduced to each of the scan separation circuits  40 - 1  and  40 - n  in sync with this clock signal CKB. As a result, the test pattern is held in the FF  43  of each of the scan separation circuits  40 - 1  to  40 - n.    
      Next, the selectors  41  and  42  in each of the scan separation circuits  40 - 1  to  40 - n  are switched to the respective input terminals B. As a result, the test patterns held in the FFs  43  are supplied in parallel to the circuit block  10 A via the respective selectors  41 .  
      Thus, the circuit block  10 A performs all possible operations based on signals supplied to the input side of the circuit block  10 A, and generates the signals SA 1  to SAm as well as an output signal from the output terminal (not shown).  
      Thereafter, the selectors  31  and  32  in each of the scan separation circuits  30 - 1  to  30 - m  are switched to the input terminals A and B respectively. As a result, the signals SA 1  to SAm generated by the circuit block  10 A are supplied to the input terminals D of the FFs  33  via the selectors  31  and  32  of the scan separation circuits  30 - 1  to  30 - m , respectively. By supplying a common clock signal CKA to the FF  33  in the scan separation circuits  30 - 1  to  30 - m , the signals SA 1  to SAm, which are generated in parallel by the circuit block  10 A, are held in the FFs  33  of the corresponding scan separation circuits  30 - 1  to  30 - m  respectively.  
      Next, the selector  32  in each of the scan separation circuits  30 - 1  to  30 - m  is switched to the input terminal A. The FFs  33  of the scan separation circuits  30 - 1  to  30 - m  are vertically connected to form an m-stage shift register. A common clock signal CKA is then supplied to the FFs  33  of the scan separation circuits  30 - 1  to  30 - m . As a result, the data held in the FFs  33  are issued from the scan output terminal as a serial signal SAout in sync with the clock signal CKA.  
      It is determined whether the circuit block  10 A is functioning properly by comparing expectation values for the output data to be generated by the circuit block  10 A in response to the test pattern with the data that is actually generated as the serial signal SAout.  
      (3) Test for Circuit Block  10 B  
      The circuit block  10 B has symmetry with the circuit block  10 A. Therefore, a process that is generally the reverse of the test ( 2 ) is performed for the circuit block  10 B. The test pattern (i.e., the serial signal SAin) is introduced to the circuit block  10 B from the scan separation circuits  30 - 1  to  30 - m . It can be determined whether the circuit block  10 B is functioning properly by reading the generated signals SB 1  to SBn as the serial signal SBout by means of the scan separation circuits  40 - 1  to  40 - n.    
      In this embodiment, each scan separation circuit  30 - i  ( 40 - j ) includes the selector  31  ( 41 ), which switches between the signal SA i  (SB j ) generated by the circuit block  10 A ( 10 B) and a test signal and then supplies the selected signal to the circuit block  10 B ( 10 A). Each scan separation circuit  30 - i  ( 40 - j ) also includes the selector  32  ( 42 ), which switches between the output signal of the selector  31  ( 41 ) and a test serial signal. Each scan separation circuit  30 - i  ( 40 -J) also includes the FF  33  ( 43 ), which holds the signal issued by the selector  32  ( 42 ) before supplying this signal to the selector  31  ( 41 ) and outputting this signal as the test serial signal. As a result, the test for the circuit blocks  10 A and  10 B can check the signals passing through all the signal paths in the LSI. Thus, the LSI does not malfunction after the LSI is mounted in the device.  
      Each of the scan separation circuits  30  and  40  in  FIG. 1  has one less selector than the scan separation circuit  20  in  FIG. 3 . Therefore, it is possible to reduce the circuit pattern area by approximately 10%.  
      The scan separation circuit  30  (or  40 ) with this constitution is applicable to a scan separation circuit with an extended function that masks a portion of the test pattern before issuing the test pattern to a circuit block in parallel.  
      In addition to general LSIs, practical applications of the present invention include integrated circuits (ASIC) conceived for a specific purpose.  
      This application is based on a Japanese Patent Application No. 2003-401411 filed on Dec. 1, 2003, and the entire disclosure thereof is incorporated herein by reference.