Patent Publication Number: US-8971076-B2

Title: Power factor correction circuit

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a power factor correction circuit employing a DC/DC converter. 
     2. Description of the Related Art 
     Various kinds of consumer electronics devices such as TVs, refrigerators, etc., or otherwise electronic devices such as laptop computers, cellular phone terminals, and PDAs (Personal Digital Assistants), are each configured to operate receiving electric power from an external circuit, and to be capable of charging a built-in battery using electric power received from an external power supply. Such consumer electronics devices and electronic devices (which will collectively be referred to as “electronic devices” hereafter) each include a built-in power supply apparatus configured to perform AC/DC conversion of commercial AC voltage. Alternatively, such a power supply apparatus is configured as a built-in component included within an external power supply adapter (AC adapter) for such an electronic device. 
     The power supply apparatus includes a rectifier circuit (diode bridge circuit) configured to rectify an AC voltage, and an insulating DC/DC converter configured to step down the rectified voltage, and to supply the voltage thus stepped down to a load. AC/DC conversion by means of such a power supply apparatus involves the development of current pulses having a very high amplitude. Such current pulses lead to problems of increased radiation noise, increased network loss, and increased high-frequency components over the entire high-frequency region. In order to solve such problems, in a case in which a given electronic device requires not less than a certain amount of power consumption, there is a need to mount a PFC (power factor correction) circuit on such an electronic device. The PFC circuit is configured to monitor an AC input voltage and an input current, and to perform phase adjustment such that the phase of the AC input voltage and the phase of the input current match each other. 
     RELATED ART DOCUMENTS 
     Patent Documents 
     [Patent Document 1] 
     
         
         Japanese Patent Application Laid Open No. 2010-114993 
       
    
     Various ranges of commercial AC voltages are employed in various countries or regions. Such a voltage range is on the order of 85 V through 265 V, taking into account the margin of error and fluctuation. In a case in which the PFC circuit is not provided with any countermeasure function, such an arrangement has a problem in that the maximum power consumption of the PFC circuit increases in proportion to the square of the input voltage. 
     SUMMARY OF THE INVENTION 
     The present invention has been made in view of such a situation. Accordingly, it is an exemplary purpose of an embodiment of the present invention to provide a PFC circuit configured to be capable of suppressing an increase in the maximum power consumption due to an increase in the input electric power, and a control circuit thereof. 
     An embodiment of the present invention relates to a control circuit for a power factor correction circuit that comprises a DC/DC converter. The control circuit comprises: an input voltage detection terminal configured to receive a first voltage having a full-wave rectified waveform; a first error amplification circuit configured to amplify a difference between a predetermined reference voltage and a first detection voltage that corresponds to an output voltage of the DC/DC converter so as to generate a second voltage; a voltage level judgment circuit configured to generate a third voltage having a discrete level that corresponds to an amplitude level of the first voltage; a multiplying/dividing circuit configured to multiply the first voltage by the second voltage, and to divide the resulting product by the third voltage, so as to generate a fourth voltage; a comparator configured to make a comparison between the fourth voltage and a second detection voltage that corresponds to a current that flows through a switching transistor included in the DC/DC converter; and a driving circuit configured to turn on the switching transistor for each predetermined period, and to turn off the switching transistor according to an output signal of the comparator every time the second detection voltage becomes higher than the fourth voltage. 
     Another embodiment of the present invention also relates to a control circuit. The control circuit comprises: an input voltage detection terminal configured to receive a first voltage having a full-wave rectified waveform; a first error amplification circuit configured to amplify a difference between a predetermined reference voltage and a first detection voltage that corresponds to an output voltage of the DC/DC converter so as to generate a second voltage; a voltage level judgment circuit configured to generate a third voltage having a discrete level that corresponds to an amplitude level of the first voltage; a multiplying/dividing circuit configured to multiply the first voltage by the second voltage, and to divide the resulting product by the third voltage, so as to generate a fourth voltage; a second error amplification circuit configured to amplify a difference between the fourth voltage and a second detection voltage that corresponds to a current that flows through a switching transistor included in the DC/DC converter; and a driving circuit configured to drive the switching transistor according to the error signal. 
     With such embodiments, when the amplitude of the AC voltage becomes large, the third voltage is increased in a stepwise manner according to an increase in the amplitude of the AC voltage. Thus, such an arrangement is capable of suppressing an increase in the amplitude of the fourth voltage due to an increase in the AC voltage. A feedback operation is performed such that the waveform that corresponds to a current that flows through the switching transistor matches the waveform of the fourth voltage. Thus, such an arrangement is capable of suppressing an increase in the maximum power consumption due to an increase in the amplitude of the AC voltage. 
     Also, the multiplying/dividing circuit may comprise: a first voltage/current conversion circuit configured to apply the first voltage to a first resistor so as to generate a first current; a second voltage/current conversion circuit configured to apply the second voltage to a second resistor so as to generate a second current; a third voltage/current conversion circuit configured to apply a predetermined voltage to a third resistor so as to generate a third current; and a multiplier configured to generate a fourth current by multiplying the first current by the second current, and by dividing the resulting product by the third current, and to apply the resulting fourth current to a fourth resistor, so as to generate a fourth voltage. 
     With the resistance values of the first resistor through the fourth resistor as R 1  through R 4 , the fourth voltage is proportional to R 3 ×R 4 /(R 1 ×R 2 ). Thus, even if the resistance values of the first resistor through the fourth resistor fluctuate at the same rate due to temperature fluctuation, process variation, or the like, such an arrangement is capable of reducing the effects of such fluctuation on the fourth voltage, thereby improving the temperature characteristics of the PFC circuit. 
     Also, the multiplier may comprise: a differential amplifier comprising a differential pair formed of a first bipolar transistor and a second bipolar transistor, a fourth bipolar transistor and a fifth bipolar transistor arranged such that the respective emitters thereof are connected to the corresponding collectors of the first and second bipolar transistors, and a current source configured to supply a tail current to the differential pair; a third bipolar transistor arranged on a path of a current that corresponds to the third current, such that its emitter is connected to the base of the first bipolar transistor, and its base is connected to the collector of the second bipolar transistor; a sixth bipolar transistor arranged on a path of a current that corresponds to the second current, such that its emitter is connected to the base of the second bipolar transistor; and a seventh bipolar transistor arranged on a path of a current that corresponds to the first current, such that its emitter is connected to the base of the sixth bipolar transistor, and its base is biased to the same bias level as that of the fourth and fifth bipolar transistors. Also, the multiplier may be configured to generate the fourth current according to a current that flows through the first and fourth bipolar transistors. Also, the fourth resistor may be arranged on a path of the fourth current. 
     With such a configuration, by multiplying the first current by the second current, and dividing the resulting product by the third current, the fourth current is thereby generated. 
     Also, the voltage level judgment circuit may comprise: multiple comparators each configured to generate a comparison signal which is asserted when the first voltage is higher than its predetermined threshold voltage; multiple latch circuits each configured to latch its state when the corresponding comparison signal is asserted, and to be reset for each predetermined period; and a voltage generating unit configured to generate the third voltage having a level that corresponds to the states of the multiple latch circuits. 
     Also, the voltage level judgment circuit may be configured to set the third voltage to its highest level during a period starting from the start-up operation. 
     Also, the first error amplification circuit may include a first current source configured such that it is switched to the on state, in which the second voltage is raised, when the first detection voltage is lower than a first threshold voltage. 
     Such an arrangement is capable of suppressing a rise in the output voltage of the DC/DC converter. 
     Also the first error amplification circuit may include a second current source configured such that it is switched to the on state, in which the second voltage is reduced, when the first detection voltage is higher than a second threshold voltage. 
     Such an arrangement is capable of reducing the effects of a sharp change in the load of the DC/DC converter. 
     Yet another embodiment of the present invention relates to a power factor correction circuit. The power factor correction circuit comprises: an output circuit for a DC/DC converter comprising a switching transistor; and a control circuit according to any one of the aforementioned embodiments, configured to drive the switching transistor. 
     Yet another embodiment of the present invention relates to an electronic device. The electronic device comprises: a rectifier circuit configured to perform full-wave rectification of a commercial AC voltage; the aforementioned power factor correction circuit configured to receive an output voltage of the rectifier circuit; and a DC/DC converter configured to receive an output voltage of the power factor correction circuit, to step down the output voltage, and to output the output voltage thus stepped down to a load. 
     It is to be noted that any arbitrary combination or rearrangement of the above-described structural components and so forth is effective as and encompassed by the present embodiments. 
     Moreover, this summary of the invention does not necessarily describe all necessary features so that the invention may also be a sub-combination of these described features. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Embodiments will now be described, by way of example only, with reference to the accompanying drawings which are meant to be exemplary, not limiting, and wherein like elements are numbered alike in several Figures, in which: 
         FIG. 1  is a circuit diagram which shows a configuration of an electronic device according to a first embodiment; 
         FIG. 2  is a circuit diagram which shows a configuration of a PFC circuit according to the first embodiment; 
         FIG. 3  is a circuit diagram which shows a part of the configuration of a control circuit; 
         FIG. 4  is a circuit diagram which shows a part of the configuration of the control circuit; 
         FIG. 5  is a circuit diagram which shows a first modification of the control circuit; 
         FIG. 6  is a circuit diagram which shows a configuration of a PFC circuit according to a second modification; 
         FIG. 7  is a circuit diagram which shows a configuration of a PFC circuit according to a second embodiment; 
         FIG. 8  is a circuit diagram which shows an example configuration of a voltage level judgment circuit shown in  FIG. 7 ; 
         FIG. 9  is a diagram which shows the operation of the voltage level judgment circuit shown in  FIG. 8 ; 
         FIG. 10  is a graph which shows the relation between the amplitude of the first voltage and the maximum power consumption in the PFC circuit shown in  FIG. 7 ; and 
         FIG. 11  is a circuit diagram which shows a modification of the PFC circuit shown in  FIG. 7 . 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The invention will now be described based on preferred embodiments which do not intend to limit the scope of the present invention but exemplify the invention. All of the features and the combinations thereof described in the embodiment are not necessarily essential to the invention. 
     In the present specification, the state represented by the phrase “the member A is connected to the member B” includes a state in which the member A is indirectly connected to the member B via another member that does not substantially affect the electric connection therebetween, or that does not damage the functions or effects of the connection therebetween, in addition to a state in which the member A is physically and directly connected to the member B. 
     Similarly, the state represented by the phrase “the member C is provided between the member A and the member B” includes a state in which the member A is indirectly connected to the member C, or the member B is indirectly connected to the member C via another member that does not substantially affect the electric connection therebetween, or that does not damage the functions or effects of the connection therebetween, in addition to a state in which the member A is directly connected to the member C, or the member B is directly connected to the member C. 
     First Embodiment 
       FIG. 1  is a circuit diagram which shows a configuration of an electronic device  1  according to an embodiment. 
     The electronic device  1  is configured as a consumer electronics device such as a TV, refrigerator, air conditioner, or the like, or otherwise as a computer. The electronic device  1  includes a microcomputer  2 , a signal processing circuit  4 , a DC/DC converter  100 , a rectifier circuit  102 , and a PFC (power factor correction circuit)  200 . The electronic device  1  is partitioned into a primary side and a secondary side that are electrically insulated from each other by means of an insulating transformer (not shown) of the DC/DC converter  100 . 
     The rectifier circuit  102  is configured as a diode rectifier circuit, for example, and is configured to receive an AC voltage such as commercial AC voltage or the like, and to perform full-wave rectification of the AC voltage thus received so as to generate an AC voltage V AC . 
     The PFC circuit  200  is configured as a step-up DC/DC converter (switching regulator), and is configured to receive the AC voltage V AC  from the rectifier circuit  102 , and to generate an output voltage V DC . The PFC circuit  200  is configured to improve the power factor by performing phase adjustment such that the phase of the AC voltage V AC  and the phase of the input current I AC  match each other. 
     The DC/DC converter  100  is configured to receive the output voltage V DC  of the PFC circuit  200 , to step down the output voltage V DC , and to output the output voltage thus stepped down to the microcomputer  2  and the signal processing circuit  4 , which each function as a load. 
     The microcomputer  2  is configured to integrally control the overall operation of the electronic device  1 . The signal processing circuit  4  is a block configured to perform predetermined signal processing, examples of which include an interface circuit configured to communicate with an external device, an image processing circuit, an audio processing circuit, and so forth. It is needless to say that, in practice, the electronic device  1  includes multiple signal processing circuits  4  according to the functions thereof. 
     The above is the overall configuration of the electronic device  1 . Next, description will be made regarding the PFC circuit  200  which can be suitably employed in such an electronic device  1 . 
       FIG. 2  is a circuit diagram which shows a configuration of the PFC circuit  200  according to the first embodiment. 
     The PFC circuit  200  includes a step-up DC/DC converter, and mainly includes a control circuit  210  and an output circuit  212 . The output circuit  212  has a typical topology including an inductor L 1 , a diode D 1 , a capacitor C 1 , and a switching transistor M 1 , and accordingly, detailed description thereof will be omitted. The input voltage V AC  is stepped down by means of switching performed by the switching transistor M 1 , thereby generating the output voltage V DC . It should be noted that it can be said that the PFC circuit  200  has the same configuration as that of a DC/DC converter. However, the PFC circuit  200  is configured to receive the input voltage V AC  as a full-wave rectified AC voltage, and to output the output voltage V DC  as a DC voltage. Thus, it can be said that the operation of the PFC circuit  200  is the same operation as that of an AC/DC converter. 
     A pair of resistors R 11  and R 12  is configured to divide the output voltage V DC  of the PFC circuit  200 , so as to generate a first detection voltage V S  that corresponds to the output voltage V DC . The first detection voltage V S  is input to an output voltage detection terminal (P_VS terminal) of the control circuit  210 . 
     A detection resistor R S  is arranged on a path of the switching transistor M 1 . A second detection voltage V I  occurs between both terminals of the detection resistor R S , which is proportional to the current I M1  that flows through the switching transistor M 1 . The second detection voltage V I  is input to a current detection terminal (CS terminal) of the control circuit  210  as a feedback signal. The second detection voltage V I  has an intermittent waveform that corresponds to the switching operation of the switching transistor M 1 . It can be assumed that the envelope curve of the second detection voltage V I  matches the input current I AC  of the PFC circuit  200 . 
     Furthermore, the full-wave rectified AC voltage V AC  is divided by a pair of resistors R 21  and R 22 . The AC voltage V BO  thus divided is input to an input voltage detection terminal (P_BO terminal) of the control circuit  210 . 
     Description will be made below regarding a specific configuration of the control circuit  210 . The control circuit  210  includes a first V/I conversion circuit  10 , a second V/I conversion circuit  12 , a third V/I conversion circuit  14 , an offset circuit  16 , a first error amplification circuit  18 , a multiplier  20 , a second error amplification circuit  30 , and a driving circuit  40 . 
     The first V/I conversion circuit  10  includes a first resistor R 1 , and is configured to apply a first voltage V 1  that corresponds to the full-wave rectified AC voltage V AC  input to the DC/DC converter (PFC circuit  200 ) to the first resistor R 1 , so as to generate a first current I 1 . The first voltage V 1  has a full-wave rectified waveform.
 
 I 1= K 1× V 1/ R 1  (1)
 
     Here, K 1  represents a proportional constant. 
     The offset circuit  16  is arranged at a previous stage of the first V/I conversion circuit  10 , and is configured to apply, to the AC voltage V AC  obtained by full-wave rectification and voltage-division, an offset toward the high electric potential side. The output signal of the offset circuit  16  is input to the first V/I conversion circuit  10  as the first voltage V 1 . 
     The first error amplification circuit  18  is configured to amplify the difference between the first detection voltage V S  that corresponds to the output voltage V DC  of the DC/DC converter and a predetermined reference voltage V REF  so as to generate a second voltage V 2 . 
     The second V/I conversion circuit  12  includes a second resistor R 2 , and is configured to apply the second voltage V 2  to the second resistor R 2 , thereby converting the second voltage V 2  into a second current I 2 .
 
 I 2 =K 2× V 2/ R 2  (2)
 
     Here, K 2  represents a proportional constant. 
     The third V/I conversion circuit  14  includes a third resistor R 3 , and is configured to apply a predetermined voltage V BGR  (=V 3 ) to the third resistor R 3  so as to generate a third current I 3 . The predetermined voltage V BGR  is preferably configured as a constant voltage which is independent of the temperature, and is preferably generated by an unshown band gap reference circuit.
 
 I 3= K 3× V   BGR   /R 3  (3)
 
     Here, K 3  represents a proportional constant. 
     The multiplier  20  is configured to generate a fourth current I 4  by multiplying the first current I 1  by the second current I 2 , and by dividing the resulting product by the third current I 3 . The multiplier  20  includes a fourth resistor R 4 , and is configured to generate a fourth voltage V 4  by means of the fourth current I 4  flowing through the fourth resistor R 4 .
 
 V 4= I 4× R 4  (4)
 
     The second error amplification circuit  30  is configured to amplify the difference between the second detection voltage V I  that corresponds to the current I M1  that flows through the switching transistor M 1  of the output circuit  212  and the fourth voltage V 4  output from the multiplier  20 , so as to generate an error voltage V ERR . 
     The driving circuit  40  is configured to drive the switching transistor M 1  according to the error voltage V ERR . The driving circuit  40  is configured to generate a driving signal S DRV  having a duty ratio that corresponds to the error voltage V ERR , by means of a pulse modulation method such as pulse width modulation (PWM), pulse frequency modulation (PFM), or the like, for example, and to output the driving signal S DRV  thus generated to the gate of the switching transistor M 1  via an output terminal SWOUT. The configuration of the driving circuit  40  is not restricted in particular, and is preferably configured using known techniques. 
       FIG. 2  shows an example of the driving circuit  40  configured to operate in a PWM manner. The driving circuit  40  includes a ramp wave generating unit  42 , a comparator  44 , an oscillator  46 , an RS flip-flop  48 , and a driver  50 . 
     The ramp wave generating unit  42  is configured to generate a cyclic voltage V RAMP  having a sawtooth waveform or otherwise a triangle waveform having a predetermined frequency (for example, 65 kHz). The comparator  44  is configured to compare the error voltage V ERR  with the cyclic voltage V RAMP , and to generate a reset signal S RST  having a level that transits every time the error voltage V ERR  crosses the cyclic voltage V RAMP . The reset signal S RST  provides a positive edge every time V ERR  crosses V RAMP  upward from the lower side. 
     The oscillator  46  is configured to generate a set signal S SET  having a predetermined frequency. The RS flip-flop  48  is arranged such that the set signal S SET  is received via its set terminal (S) and the reset signal S RST  is received via its reset terminal (R). The output (Q) of the RS flip-flop  48  transits to high level for each positive edge of the set signal S SET , and transits to low level for each positive edge of the reset signal S RST . 
     The generation of the set signal S SET  is not restricted to such an operation of the oscillator  46 . For example, instead of such an oscillator  46 , such an arrangement may include a zero-crossing comparator configured to generate a set signal S SET  having a level that transits (a positive edge) when the current that flows through the inductor L 1  drops to substantially zero. For example, by providing an auxiliary winding to the inductor L 1 , such an arrangement is capable of suitably detecting the current that flows through the inductor L 1 . In this case, such an arrangement is capable of using energy stored in the inductor L 1  with high efficiency as compared with an arrangement employing the oscillator  46 . The set signal S SET  may be generated using other methods. The same can be said of a modification which will be described later with reference to  FIG. 5 . 
     The output of the RS flip-flop  48  is configured as a pulse-width modulated signal S PWM . The driver  50  is configured to perform switching of the switching transistor M 1  according to the PWM signal S PWM . 
     The duty ratio of the PWM signal S PWM  is adjusted by means of the feedback loop including the first error amplification circuit  18  and the feedback loop including the second error amplification circuit  30  such that the first detection voltage V S  matches the reference voltage V REF  and the envelope waveform of the current I M1  that flows through the switching transistor M 1  matches the waveform of the full-wave rectified input voltage V AC . 
     The above is the overall configuration of the PFC circuit  200 . Next, description will be made regarding a specific example configuration of the control circuit  210 . 
       FIG. 3  is a circuit diagram which shows a part of the configuration of the control circuit  210 . 
     The offset circuit  16  is configured to receive the input voltage V BO  obtained by dividing the full-wave rectified AC voltage V AC , and to apply an offset to the input voltage V BO  thus received so as to generate the first voltage V 1 . 
     The first V/I conversion circuit  10  includes a transistor M 11 , an operational amplifier OA 1 , and a current mirror circuit CM 1 , in addition to the first resistor R 1 . The first resistor R 1  is arranged such that one terminal thereof is grounded. The transistor M 11  is arranged such that one terminal (source) thereof is connected to the first resistor R 1  and the inverting input terminal of the operational amplifier OA 1 . The first voltage V 1  is input to the non-inverting input terminal of the operational amplifier OA 1 . A current I M11  flows through the transistor M 11  and the resistor R 1 .
 
 I   M11   =V 1/ R 1
 
     A current mirror circuit CM 1  is configured as a cascode current mirror circuit including transistors M 12  through M 15  and a resistor R 2 , and to mirror the current I M11 , thereby outputting the first current I 1 . In a case in which the mirror ratio of the current mirror circuit CM 1  is 1, K 1 =1 holds true, and accordingly, the following Expression (1a) holds true.
 
 I 1= V 1/ R 1  (1a)
 
     The second V/I conversion circuit  12  and the third V/I conversion circuit  14  are each configured in the same manner as the first V/I conversion circuit  10 . It should be noted that, with the second V/I conversion circuit (third V/I conversion circuit  14 ), the current mirror circuit CM 2  (CM 3 ) is configured including transistors M 22  and M 23  (M 32  and M 33 ). It should be noted that the current mirror circuits CM 2  and CM 3  are each configured as a cascode current mirror circuit. Conversely, the current mirror circuit CM 1  of the first V/I conversion circuit  10  may be configured in the same manner as the current mirror circuits CM 2  and CM 3 . In a case in which the current mirror circuits CM 2  and CM 3  each have a mirror ratio of 1, the following Expressions (2a) and (3a) hold true.
 
 I 2 =V 2/ R 2  (2a)
 
 I 3= V   BGR   /R 3  (3a)
 
     The first error amplification circuit  18  includes an error amplifier EA 1 , an output buffer  19 , a first current source CS 1 , and a second current source CS 2 . 
     The error amplifier EA 1  is configured to amplify the difference between the reference voltage V REF  and the first detection voltage V S . The output buffer  19  has a push-pull configuration, and is configured to generate the second voltage V 2  that corresponds to the output of the error amplifier EA 1 . 
     When the first detection voltage V S  is lower than a predetermined first threshold voltage V TH1 , the first current source CS 1  is set to the on state. The first threshold voltage V TH1  is preferably set to be a value that is lower than the reference voltage V REF , e.g., is preferably set to be a value on the order of 15% lower than the reference voltage V REF . In the on state, the first current source CS 1  supplies current to the output terminal of the first error amplification circuit  18 , thereby raising the second voltage V 2 . The rise of the second voltage V 2  raises the output voltage V DC  of the PFC circuit  200 . 
     When the first detection voltage V S  is higher than a predetermined second threshold voltage V TH2 , the second current source CS 2  is turned on, which draws the current from the output terminal of the first error amplification circuit  18 , thereby reducing the second voltage V 2 . The reduction in the second voltage V 2  reduces the output voltage V DC  of the PFC circuit  200 . 
     The comparator CMP 1  is configured to compare the first detection voltage V S  with the threshold voltage and to generate a low-voltage lockout signal (VSUVLO signal) which is set to high level when V S &gt;V TH1 . When the VSUVLO signal is low level, the first current source CS 1  is set to the on state. Moreover, the comparator CMP 2  is configured to compare the first detection voltage V S  with the predetermined threshold voltage V TH2 , and to generate an overvoltage protection signal (DOVP signal) which is set to high level when V S &gt;V TH2 . When the DOVP signal is high level, the second current source CS 2  is set to the on state. 
       FIG. 4  is a circuit diagram which shows a part of the configuration of the control circuit  210 . The multiplier includes bipolar transistors Q 1  through Q 9 , a current source  22 , a resistor R 5 , and current mirror circuits CM 41  through CM 43 , in addition to the fourth resistor R 4 . 
     The current mirror circuits CM 41  through CM 43  are configured to mirror the first current I 1  through the third current I 3 , respectively. The transistors Q 1 , Q 2 , Q 4 , and Q 5 , and the current source  22  form a differential amplifier. The first transistor Q 1  and the second transistor Q 2  form a differential pair. The fourth transistor Q 4  and the fifth transistor Q 5  function as the loads of the first transistor Q 1  and the second transistor Q 2 , respectively. The emitters of the transistors Q 4  and Q 5  are connected to the collectors of the transistors Q 1  and Q 2 , respectively. The current source  22  is configured to supply a tail current to the differential pair (Q 1 , Q 2 ). 
     The third transistor Q 3  is arranged on a path of a current I 3 ′ that corresponds to the third current I 3  such that its emitter is connected to the base of the first transistor Q 1 , and its base is connected to the collector of the second transistor Q 2 . The sixth transistor Q 6  is arranged on a path of a current I 2 ′ that corresponds to the second current I 2 , such that its emitter is connected to the base of the second transistor Q 2 . The seventh transistor Q 7  is arranged on a path of a current I 1 ′ that corresponds to the first current I 1 , such that its emitter is connected to the base of the sixth transistor Q 6 , and its base is biased to the same bias level as that of the fourth transistor Q 4  and the fifth transistor Q 5 . 
     The eighth transistor Q 8  and the ninth transistor Q 9  form a current mirror circuit CM 44 , which is configured to mirror a current I 4 ′ (=I C1 ) that flows through a path formed of the first transistor Q 1  and the fourth transistor Q 4 , thereby generating the fourth current I 4 . The fourth resistor R 4  is arranged on a path of the fourth current I 4 . A voltage drop V R4  across the fourth resistor R 4  is output as the fourth voltage V 4 . 
     With the base-emitter voltages of the first transistor Q 1  through the seventh transistor Q 7  as VF 1  through VF 7 , respectively, and with the collector currents that flow through the respective transistors Q 1  through Q 7  as I C1  through I C7 , respectively, the following Expression (5) holds true.
 
 VF 1 +VF 3 +VF 5= VF 2 +VF 8 +VF 7  (5)
 
     The collector current that flows through the bipolar transistor is represented by the following Expression (6).
 
 I   C   ∝I   S ×exp( V   F   /V   T )  (6)
 
     Here, V T  represents kT/q, I S  represents the saturation current, q represents the electron charge (=1.602×10 −19  [C]), k represents the Boltzmann constant (1.38×10 −23  [J/K]), and T represents the absolute temperature [(K)]. The following Expression (7) is obtained based upon the Expressions (5) and (6).
 
 I   C1   ×I   C3   ×I   C5   =I   C2   ×I   C6   ×C   7   (7)
 
     With such an arrangement, the transistors Q 2  and Q 5  are arranged on the same current path, and accordingly I C2 =I C5  holds true. Thus, the following Expressions (8) and (9) are obtained.
 
 I   C1   ×I   C3   =I   C6   ×I   C7   (8)
 
 I   C1   =I   C6   ×I   C7   /I   C3   (9)
 
     For simplicity of description, let us say that the current mirror circuits CM 41  through CM 43  each have a mirror ratio of 1. In this case, I C7 =I 1 ′=I 1 , I C6 =I 2 ′=I 2 , and I C3 =I 3 ′=I 3  hold true. Thus, the following Expression (10) is obtained.
 
 I   C1   =I 2× I 1/ I 3  (10)
 
     In a case in which the current mirror circuit CM 44 , which comprises the transistors Q 8  and Q 9 , has a mirror ratio of 1, the following Expression (11) is obtained using the current I C1  that flows through the first transistor Q 1 .
 
 I 4= I   C1   =I 2× I 1/ I 3  (11)
 
     By substituting the Expressions (1a) through (3a) into the Expression (11), the following Expression (12) is obtained.
 
 I 4=( V 1× V 2)/ V 3× R 3/( R 1× R 2)  (12)
 
     Based upon the Expression (4) and Expression (12), the following Expression (13) is obtained.
 
 V 4=( V 1× V 2)/ V 3×( R 3× R 4)/( R 1× R 2)  (13)
 
     The second error amplification circuit  30  includes an error amplifier EA 2  and output buffer  32 , and is configured in the same manner as the first error amplification circuit  18  shown in  FIG. 3 . 
     The above is the configuration of the PFC circuit  200  according to the embodiment. Next, description will be made regarding the operation of the PFC circuit  200 . 
     The first voltage V 1  has the same full-wave rectified waveform as that of the AC voltage V AC . The second voltage V 2  and the third voltage V 3  are each configured as a DC voltage. Thus, the fourth voltage V 4  has a full-wave rectified waveform having the same phase as that of the AC voltage V AC . 
     Furthermore, as described above, by means of the system including the second error amplification circuit  30 , the duty ratio of the PWM signal S PWM  is feedback controlled such that the envelope curve of the current I M1  that flows through the switching transistor M 1  matches the fourth voltage V 4 . Thus, the feedback operation is performed such that the current I M1  that flows through the switching transistor M 1  matches the AC voltage V AC , and accordingly, the waveform and the phase of the input current I AC  of the PFC circuit  200  match those of the AC voltage V AC , thereby improving the power factor. 
     Description will be made directing attention to the aforementioned Expression (13). The resistances R 1  through R 4  are paired. Thus, even if the respective resistance values R 1 -R 4  fluctuate due to temperature fluctuation or otherwise due to process variation (which will be collectively referred to as “temperature fluctuation, etc.”), the resistance ratio is maintained at a constant value. That is to say, with regard to the term (R 3 ×R 4 )/(R 1 ×R 2 ), the effect of temperature fluctuation, etc., on the denominator and its effect on the numerator cancel each other out, and accordingly, the value of this term is maintained at substantially the same value. That is to say, such an arrangement is capable of suppressing effects of temperature fluctuation, etc., on the fourth voltage V 4 , thereby suppressing the effects of temperature fluctuation, etc., on the waveform of the input current I AC . 
     The PFC circuit  200  has yet another advantage described below. 
     The divided AC voltage V BO  has a full-wave rectified waveform. Thus, the divided AC voltage V BO  drops to substantially 0 V. If the AC voltage V BO  is directly input to the first V/I conversion circuit  10 , the voltage range of the AC voltage V BO  deviates from the input voltage range of the operational amplifier OA 1 , leading to the operation of the operational amplifier OA 1  in a dead band, which distorts the waveform of the first current I 1  from that of an ideal full-wave rectified waveform. Such waveform distortion worsens the total harmonic distortion (THD). In contrast, with the control circuit  210  according to the embodiment, by providing the offset circuit  16 , such an arrangement is capable of preventing the first V/I conversion circuit  10  from operating in the dead band, thereby improving the total harmonic distortion. 
     The PFC circuit  200  is required to respond to an envelope curve signal having a frequency on the order of 50 Hz to 60 Hz, leading to a very low response speed of the feedback loop. Accordingly, such a feedback control operation by means of only the error amplifiers EA 1  and EA 2  cannot suppress drops or rises in the output voltage V DC  due to sharp fluctuations in the load. In contrast, with the control circuit  210  according to the embodiment, in the low-voltage state (V S &lt;V TH1 ), the first current source CS 1  is turned on, which raises the second voltage V 2  with a quicker response than with the error amplifier EA 1 , thereby promptly raising the output voltage V DC . Furthermore, in the overvoltage state (V S &gt;V TH2 ), the second current source CS 2  is turned on, which lowers the second voltage V 2  with a quicker response than with the error amplifier EA 1 , thereby promptly reducing the output voltage V DC . 
     Description has been made above regarding the present invention with reference to the embodiment. The above-described embodiment has been described for exemplary purposes only, and is by no means intended to be interpreted restrictively. Rather, it can be readily conceived by those skilled in this art that various modifications may be made by making various combinations of the aforementioned components or processes, which are also encompassed in the technical scope of the present invention. Description will be made below regarding such modifications. 
     Description has been made with reference to  FIG. 2  regarding the control circuit  210  configured to perform a so-called average current mode control operation. However, the present invention is not restricted to such an arrangement. Also, the present invention can be applied to an arrangement configured to perform a peak current mode control operation.  FIG. 5  is a circuit diagram which shows a PFC circuit including a control circuit  210   a  according to a first modification. The control circuit  210   a  configured to perform a peak current mode control operation includes a comparator  45 , instead of the second error amplification circuit  30  shown in  FIG. 2 . The comparator  45  is configured to compare the fourth voltage V 4  with the second detection voltage V I , and to output a reset signal S RST  which is set to high level when V I &gt;V 4 . The reset signal S RST  is input to the reset terminal of the RS flip-flop  48  of a driving circuit  40   a . That is to say, the driving circuit  40   a  turns on the switching transistor M 1  for each cycle according to the set signal S SET  received from the oscillator  46 , and turns off the switching transistor M 1  according to the reset signal S RST  every time the second detection voltage V I  becomes higher than the fourth voltage V 4 . 
     With the control circuit  210   a  shown in  FIG. 5 , the feedback control is performed such that the peak value of the second detection voltage V I , i.e., the peak value of the current I M1  that flows through the switching transistor M 1  matches the fourth voltage V 4 , thereby stabilizing the output voltage V DC . The control circuit  210   a  configured to operate in such a peak current mode provides high efficiency as compared with an arrangement configured to operate in an average current mode. 
       FIG. 6  is a circuit diagram which shows a PFC circuit  200   b  according to a second modification. A rectifier circuit  102  and a filter  101  are arranged at a previous stage of the PFC circuit  200   b . It is needless to say that such a filter  101  may be arranged at a previous stage of the PFC circuit  200  described above with reference to  FIG. 1 . 
     The AC voltage V AC  subjected to noise removal by the filter  101  is full-wave rectified by the rectifier circuit  102 , and is smoothed by the smoothing capacitor C 30 . The voltage thus smoothed (which will be referred to as the “input voltage V IN ”) is input to the PFC circuit  200   b . With such a modification, the PFC circuit  200   b  operates as a DC/DC converter configured to convert a DC voltage into a DC voltage. 
     The PFC circuit  200   b  mainly includes a control circuit  210   b  and an output circuit  212 . As such a control circuit  210   b , the average current mode control circuit  210  shown in  FIG. 2  or otherwise the peak current mode control circuit  210   a  may be employed. 
     A resistor R 31  and a capacitor C 31  are arranged in series, and are arranged in parallel with the capacitor C 30 . The voltage Vcc at a connection node that connects the resistor R 31  and the capacitor C 31  is supplied to the power supply terminal VCC of the control circuit  210 . 
     The detection resistor R S  is arranged between the source of the switching transistor M 1  and an output terminal P 32  of the rectifier circuit  102 . The current that flows through the switching transistor M 1 , i.e., the current I M1  that corresponds to the input current of the PFC circuit  200   b , flows through the detection resistor R. Accordingly, the second detection voltage V I  (voltage drop), which corresponds to the current I M1  that flows through the switching transistor M 1 , occurs between both terminals of the detection resistor R S . The second detection voltage V I  is input as a feedback signal to the current detection terminal (CS terminal) of the control circuit  210 . It should be noted that the detection resistor R S  may be arranged between the source of the switching transistor M 1  and the ground terminal in the same way as with the above-described embodiment. Conversely, in the above-described embodiment, such a detection resistor R S  may be arranged at the same position as that shown in  FIG. 6 . 
     The diodes D 21  and D 22  are configured to perform full-wave rectification of the commercial AC voltage V AC  input to the rectifier circuit  102 . The AC voltage V BO  thus full-wave rectified is divided by the resistors R 21  and R 22 , and the voltage thus divided is input to the input voltage detection terminal (P_BO terminal) of the control circuit  210 . 
     The above is the configuration of the PFC circuit  200   b  according to the second modification. Such a second modification provides the same advantages as those of the PFC circuit  200  according to the embodiment. 
     Second Embodiment 
     Description has been made in the first embodiment regarding a technique for improving the temperature characteristics. Description will be made in a second embodiment regarding a technique for suppressing an increase in the maximum power consumption due to an increase in the input electric power of the PFC circuit, according to a combination of the first embodiment and the second embodiment, or otherwise according to the second embodiment alone. 
       FIG. 7  is a circuit diagram which shows a configuration of a PFC circuit  200   c  including a control circuit  210   c  according to the second embodiment. A peripheral circuit of the control circuit  210   c  has the same configuration as that shown in  FIG. 6 , and accordingly, description thereof will be omitted. It should be noted that the peripheral circuit of the control circuit  210   c  may be configured in the same way as shown in  FIG. 5 . 
     Description will be made below regarding a specific configuration of the control circuit  210   c . The control circuit  210   c , which is configured to operate in the peak current mode, includes a voltage level judgment circuit  15 , a first error amplification circuit  18 , a multiplying/dividing circuit  17 , a comparator  45 , and a driving circuit  40   a.    
     The first error amplification circuit  18  is configured to amplify the difference between a first detection voltage V S  that corresponds to the output voltage V DC  of the DC/DC converter and a predetermined reference voltage V REF  so as to generate a second voltage V 2 . The output terminal of the first error amplification circuit  18  is connected to a P_EO terminal. A phase compensation circuit  18   a , which includes a capacitor and a resistor, is connected to the P_EO terminal. 
     The voltage level judgment circuit  15  is configured to receive a first voltage V 1  that corresponds to the voltage V BO  input to the P_BO terminal, to judge the level of the amplitude Vamp of the first voltage V 1 , and to generate a third voltage V 3  having a discrete level that corresponds to the judged level. For example, when Vamp&lt;Vth 1 , the third voltage V 3  is set to a first level Va. When Vth 1 &lt;Vamp&lt;Vth 2 , the third voltage V 3  is set to the second level Vb. When Vth 2 &lt;Vamp&lt;Vth 3 , the third voltage V 3  is set to the third level Vc. When Vth 3 &lt;Vamp, the third voltage V 3  is set to the fourth level Vd. Here, Va, Vb, Vc, and Vd are determined such that Va&lt;Vb&lt;Vc&lt;Vd. 
     The multiplying/dividing circuit  17  is configured to multiply the first voltage V 1  by the second voltage V 2 , and to divide the resulting product by the third voltage V 3 , so as to generate the fourth voltage V 4 . That is to say, the following Expression holds true.
 
 V 4= K 4× V 1· V 2/ V 3  (14)
 
     Here, K 4  represents a constant. The multiplying/dividing circuit  17  may be configured employing a combination of the first V/I conversion circuit  10 , the second V/I conversion circuit  12 , the third V/I conversion circuit  14 , and the multiplier  20 , as described in the first embodiment. In this case, such an arrangement provides the advantage of improved temperature characteristics as in the first embodiment. It should be noted that the configuration of the multiplying/dividing circuit  17  is not restricted to such an arrangement. Also, other configurations may be employed. 
     The other configuration of the control circuit  210   c  is the same as that of the control circuit  210   a  shown in  FIG. 5 , configured to operate in the peak current mode. The control circuit  210   c  shown in  FIG. 7  may include the offset circuit  16 . 
       FIG. 8  is a circuit diagram which shows an example configuration of the voltage level judgment circuit  15  shown in  FIG. 7 . 
     The voltage level judgment circuit  15  includes multiple comparators CMP 1  through CMP 3 , multiple latch circuits LA 1  through LA 3 , and a voltage generating unit  52 . 
     The i-th comparator CMPi is configured to generate a comparison signal S 1 _i which is asserted (set to high level) when the first voltage V 1  is higher than the corresponding threshold voltage Vthi. 
     When the corresponding comparison signal S 1 _i is asserted, the i-th latch circuit LAi latches this state. The states of the multiple latch circuits LA 1  through LA 3  are each reset for each predetermined period defined by the timer circuit  54 . The predetermined period T 1  is preferably set to be longer the half the period of the AC voltage V AC . For example, in a case in which an AC voltage V AC  of 50 Hz is employed, the period of the AC voltage V AC  is 20 ms, and accordingly, the predetermined period T 1  is set to be longer than 10 ms. 
     The voltage generating unit  52  is configured to generate the third voltage V 3  having a level that corresponds to the states of the multiple latch circuits LA 1  through LA 3 . For example, the voltage generating unit  52  may include a resistor string  56  that comprises multiple resistors R 40  through R 44  connected in series and switches SW 41  through SW 43  respectively connected in parallel with the resistors R 41  through R 43 . When the output signal S 2 _i of the corresponding latch circuit LAi is high level, the i-th switch SW 4   i  is turned on, and when the output signal S 2 _i is low level, the switch SW 4   i  is turned off. The voltage level of the third voltage V 3  generated by the voltage generating unit  52  is increased according to an increase in the amplitude of the first voltage V 1 . The numbers of such comparators, latch circuits, and resistors are preferably determined according to the number of switchable levels of the third voltage V 3 , which will be clearly understood by those skilled in this art. 
     It should be noted that the configuration of the voltage generating unit  52  is not restricted in particular, as long as it is capable of generating the third voltage having a level which represents the states of the multiple latch circuits. 
       FIG. 9  is a diagram which shows the operation of the voltage level judgment circuit  15  shown in  FIG. 8 . With such an example shown in  FIG. 9 , the amplitude level of the first voltage V 1  satisfies the relation Vth 2 &lt;Vamp&lt;Vth 3 , and accordingly, the level of the third voltage V 3  is set to the third level Vc. 
     It should be noted that the voltage level judgment circuit  15  preferably sets the third voltage V 3  to the highest level Vd during a period starting from the start-up of the PFC circuit  200   c . Such an arrangement is capable of suppressing the maximum power consumption during a given period immediately after the PFC circuit  200   c  starts up regardless of the amplitude level of the first voltage V 1  (AC voltage V AC ). This means that such an arrangement limits the current that flows through the switching transistor M 1 , thereby providing a so-called soft-start operation in which the output voltage V DC  of the PFC circuit  200   c  rises at a slow rate. 
     The above is the configuration of the control circuit  210   c . Next, description will be made regarding the operation of the PFC circuit  200   c  shown in  FIG. 7 . 
     The maximum power consumption P of the PFC circuit  200   c  shown in  FIG. 7  is represented by the following Expression (15). Here, L represents the inductance of the inductor L 1 , I L  represents the current that flows through the inductor L 1 , and f SW  represents the switching frequency of the switching transistor M 1 .
 
 P   MAX =½× L×I   L   2   ×f   SW   (15)
 
     The current I L  that flows through the inductor L 1  is represented by the following Expression (16) using a coefficient K 5 .
 
 I   L =( V 4/ R   S )× K 5  (16)
 
     By substituting the Expression (14) into the Expression (16), the following Expression (16)′ is obtained.
 
 I   L =( K 4× V 1× V 2/ V 3)/ R   S   ×K 5=α× V 1× V 2/ V 3  (16)′
 
     By substituting Expression (16)′ into Expression (15), the following Expression (17) is obtained.
 
 P   MAX =½ ×L ×(α× V 1× V 2/ V 3) 2   ×f   SW   (17)
 
       FIG. 10  is a graph which shows the relation between the amplitude Vamp of the first voltage V 1  and the maximum power consumption P MAX  in the PFC circuit  200   c  shown in  FIG. 7 . 
     As indicated by the solid line (II), in a case in which the third voltage V 3  is configured as a fixed voltage, the maximum power consumption P increases in proportion to the square of V AC  according to an increase in the amplitude Vamp of the first voltage V 1 , i.e., according to an increase in the AC voltage V AC . In contrast, with the PFC circuit  200   c  shown in  FIG. 7 , as indicated by the solid line (I), by increasing the third voltage V 3  according to the amplitude Vamp, such an arrangement is capable of suppressing a limitless increase in the maximum power consumption P. 
     Furthermore, such an arrangement allows the designer of the PFC circuit  200  to determine the respective threshold voltages Vth 1  through Vth 3  and the respective voltage levels Va through Vd of the third voltage V 3 . Thus, such an arrangement allows the horizontal direction of the relational curve indicated by the solid line (I) to be adjusted by adjusting the threshold voltages Vth 1  through Vth 3 . Also, such an arrangement allows the vertical direction of the relational curve indicated by the solid line (I) to be adjusted by adjusting the voltage levels Va through Vd. 
     The above is the description of the PFC circuit  200   c  according to the second embodiment. The PFC circuit  200   c  shown in  FIG. 7  is configured as a peak current mode PFC circuit. Also, the present embodiment can be applied to an average current mode PFC circuit.  FIG. 11  is a circuit diagram which shows a modification of the PFC circuit shown in  FIG. 7 . A PFC circuit  200   d  shown in  FIG. 11  includes an average current mode control circuit  210   d . The peripheral circuit of the control circuit  210   d  has the same configuration as that shown in  FIG. 6 , and accordingly, description thereof will be omitted. It should be noted that the peripheral circuit of the control circuit  210   d  may be configured in the same way as shown in  FIG. 2 . The control circuit  210   d  includes a voltage level judgment circuit  15  instead of the third V/I conversion circuit  14  included in the control circuit  210  shown in  FIG. 2 . 
     With such an average current mode control circuit  210   d , such an arrangement is also capable of suppressing a limitless increase in the maximum power consumption P as shown in  FIG. 10 . 
     Description has been made in the embodiment regarding an arrangement in which the DC/DC converter  100  is mounted on the electronic device  1 . However, the present invention is not restricted to such an arrangement. Rather, the present invention can be applied to various kinds of power supply apparatuses. For example, the DC/DC converter  100  is applicable to an AC adapter configured to supply electric power to an electronic device. Examples of such an electronic device include laptop computers, desktop computers, cellular phone terminals, CD players, and so forth, which are not restricted in particular. 
     While the preferred embodiments of the present invention have been described using specific terms, such description is for illustrative purposes only, and it is to be understood that changes and variations may be made without departing from the spirit or scope of the appended claims.