Patent Publication Number: US-10312084-B2

Title: Semiconductor device and fabrication method thereof

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This application is a division of U.S. application Ser. No. 14/946,795 filed Nov. 20, 2015, which is included herein in its entirety by reference. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to the manufacture of semiconductor devices, and more specifically, to an improved dual epitaxial process for semiconductor MOS devices. 
     2. Description of the Prior Art 
     As known in the art, metal-oxide-semiconductor field-effect transistors (MOSFETs) have been scaled down through various technology nodes. To enhance carrier mobility and improve device performance, strained source/drain features (e.g., stressor regions) have been introduced. Stress distorts or strains the semiconductor crystal lattice, which affects the band alignment and charge transport properties of the semiconductor. 
     Typically, compressive strain increases charge carrier mobility in a p-type metal-oxide-semiconductor field-effect transistor (pMOSFET) channel and tensile strain increases charge carrier mobility in an n-type metal-oxide semiconductor field-effect transistor (nMOSFET) channel. Silicon-germanium (SiGe) is a typical epitaxial material utilized to induce compressive strain in pMOS channel for increased hole mobility. Tensile strain may be achieved for increased electron mobility in nMOS channel by the introduction of silicon carbide (SiC) or silicon phosphate (SiP). 
     However, the prior art dual epitaxial process for semiconductor MOS devices suffers from selective loss defect and SiGe fall-on issue (i.e. SiGe grains grown in nMOS region). It is therefore desirable to have improved methods and structures for utilizing such epitaxial material regions. 
     SUMMARY OF THE INVENTION 
     It is one objective of the invention to provide an improved semiconductor MOS device and an improved dual epitaxial process for fabricating such semiconductor MOS device, in order to solve the above-mentioned prior art problems and shortcomings. 
     In one aspect of the invention, a semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate, an inter-layer dielectric (ILD) layer on the semiconductor substrate, a gate in the ILD layer, an offset liner on a sidewall of the gate, a spacer on the offset liner, a dense oxide film on the spacer, a contact etch stop layer on the dense oxide film, and a contact plug adjacent to the contact etch stop layer. The semiconductor device further includes a source region in the semiconductor substrate and a drain region spaced apart from the source region. A channel is located between the source region and the drain region. The dense oxide film has a thickness that is smaller or equal to 12 angstroms. 
     According to one embodiment, the semiconductor device is an n-type metal-oxide-semiconductor field-effect transistor (nMOSFET) and a SiP epitaxial layer is disposed either in the source region or in the drain region. The offset liner comprises carbon and nitrogen doped silicon oxide. The spacer comprises carbon and nitrogen doped silicon oxide. 
     In another aspect of the invention, a method for fabricating the semiconductor device is disclosed. A semiconductor substrate having a main surface is provided. A gate is formed on the main surface of the semiconductor substrate. An offset liner is formed on the sidewall of the gate. An ion implantation process is performed to form lightly doped drain (LDD) region in the semiconductor substrate. A spacer is formed on a sidewall of the gate. A cavity is recessed into the main surface of the semiconductor substrate. The cavity is adjacent to the spacer. An epitaxial layer is grown in the cavity. The spacer is then subjected to a surface treatment to form a dense oxide film on the spacer. A mask layer is deposited on the dense oxide film. The dense oxide film has a thickness that is smaller or equal to 12 angstroms. 
     According to one embodiment, the surface treatment includes: (a) making the spacer contact with diluted HF; (b) making the spacer contact with sulfuric acid and hydrogen peroxide mixture (SPM) solution; and (c) making the spacer contact with ozone water. 
     These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The accompanying drawings are included to provide a further understanding of the embodiments, and are incorporated in and constitute apart of this specification. The drawings illustrate some of the embodiments and, together with the description, serve to explain their principles. In the drawings: 
         FIG. 1  to  FIG. 6  are schematic, cross-sectional diagrams showing a method for fabricating a semiconductor MOS device according to one embodiment of the invention, wherein: 
         FIG. 1  to  FIG. 5  illustrate an exemplary dual epitaxial process for forming the semiconductor MOS device; 
         FIG. 6  illustrates an exemplary cross-sectional view of the semiconductor MOS device after CESL and ILD deposition; and 
         FIG. 7  illustrates an exemplary cross-sectional view of the semiconductor MOS device after high-k/metal gate (HK/MG) process and contact formation. 
     
    
    
     DETAILED DESCRIPTION 
     The present invention has been particularly shown and described with respect to certain embodiments and specific features thereof. The embodiments set forth herein below are to be taken as illustrative rather than limiting. It should be readily apparent to those of ordinary skill in the art that various changes and modifications in form and detail may be made without departing from the spirit and scope of the invention. 
     The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims, along with the full scope of equivalents to which such claims are entitled. 
       FIG. 1  to  FIG. 6  are schematic, cross-sectional diagrams showing a method for fabricating a semiconductor MOS device according to one embodiment of the invention. As shown in  FIG. 1 , a semiconductor substrate  10  is provided. For example, the semiconductor substrate  10  may comprise a silicon substrate or a silicon-on-insulator (SOI) substrate, but is not limited thereto. For the sake of simplicity, only two regions: a pMOS region  101  and an nMOS region  102  are shown in the figures. The isolation regions such as shallow trench isolation (STI) regions for defining active areas are not shown. Suitable ion wells such as P wells or N wells may be formed in the semiconductor substrate  10 , which are also not shown in the figures. 
     The semiconductor substrate  10  has a main surface  10   a . A gate  12  and a gate  14 , for example, both are a polysilicon gate, are formed on the main surface  10   a  of the semiconductor substrate  10  in the pMOS region  101  and the nMOS region  102 , respectively. According to one embodiment, the gate  12  and the gate  14  may be dummy poly gates, and may be replaced with high k dielectric and metal gates in a later manufacturing stage. 
     According to one embodiment, the gate  12  may include, but not limited to, a gate oxide layer  121 , a polysilicon layer  122  on the gate oxide layer  121 , a thin silicon nitride layer  123  on the polysilicon layer  122 , and a hard mask oxide layer  124  on the thin silicon nitride layer  123 . According to one embodiment, the gate  14  may include, but not limited to, a gate oxide layer  141 , a polysilicon layer  142  on the gate oxide layer  141 , a thin silicon nitride layer  143  on the polysilicon layer  142 , and a hard mask oxide layer  144  on the thin silicon nitride layer  143 . It is understood that the shown layers of the gates  12  and  14  are for illustration purposes only. It is understood that other layers or materials may be employed in the gates  12  and  14 . 
     Still referring to  FIG. 1 , subsequently, an offset liner  126  is formed on the sidewall of the gate  12  and an offset liner  146  is formed on the sidewall of the gate  14 . According to one embodiment, the offset liners  126  and  146  may comprise carbon and nitrogen doped silicon oxide (SiOCN). After forming the offset liners  126  and  146 , an ion implantation process is performed to form lightly doped drain (LDD) regions  112  in the semiconductor substrate  10  in the pMOS region  101 , and an ion implantation process is performed to form LDD regions  114  in the semiconductor substrate  10  in the nMOS region  102 . 
     As shown in  FIG. 2 , subsequently, a SiP epitaxial growth process is performed to form SiP epitaxial layer in the nMOS region  102 . For example, the pMOS region  101  is covered with a mask layer  150 . The mask layer  150  may be a composite layer comprising, for example, a first dielectric layer  151  and a second dielectric layer  152 , but is not limited thereto. According to one embodiment, the first dielectric layer  151  may comprise SiOCN. According to one embodiment, the second dielectric layer  152  may comprise silicon nitride, for example, a silicon-rich silicon nitride layer. A spacer  151   a  is formed on the sidewall of the gate  14  in the nMOS region  102 . According to one embodiment, the spacer  151   a  may comprise SiOCN. 
     The first dielectric layer  151  and the second dielectric layer  152  may be formed by using chemical vapor deposition (CVD) methods, for example, Low-Pressure CVD (LPCVD), Plasma-Enhanced CVD (PECVD), or Atomic Layer Deposition (ALD), but is not limited thereto. 
     After forming the spacer  151   a  on the sidewall of the gate  14  in the nMOS region  102 , an etching process such as a dry etching process is performed to etch the semiconductor substrate  10  thereby forming a cavity  204  on each side of the gate  14 . The cavity  204  is recessed into the main surface  10   a  of the semiconductor substrate  10  and is adjacent to the spacer  151   a . An epitaxial growth process is then performed to grow a first epitaxial layer  214  such as SiP in the cavity  204 . 
     As shown in  FIG. 3 , after forming the first epitaxial layer  214  in the nMOS region  102 , the spacer  151   a  is subjected to a surface treatment to forma dense oxide film  161  on the spacer  151   a . The dense oxide film  161  may be a densified silicon oxide film. According to one embodiment, the dense oxide film  161  has a thickness that is smaller or equal to 12 angstroms. 
     According to one embodiment, the surface treatment includes the following sequence: (a) making the spacer  151   a  contact with diluted HF; (b) making the spacer  151   a  contact with sulfuric acid and hydrogen peroxide mixture (SPM) solution; and (c) making the spacer  151   a  contact with ozone water. According to one embodiment, the surface treatment may be carried out at room temperature, but is not limited thereto. 
     The diluted HF may create highly active dangling bonds on the surface of the spacer  151   a . By contacting with the SPM solution, the highly active dangling bonds may be transformed into chemical Si—O bonding. The subsequent ozone water treatment makes the chemical silicon oxide become more compact and also repairs the interface between the dense oxide film  161  and the spacer  151   a . The dense oxide film  161  is formed only in the nMOS region  102  because the MOS region  101  is still covered with the mask layer  150  when performing the surface treatment. 
     As shown in  FIG. 4 , a mask layer  250  such as a silicon-rich silicon nitride layer is deposited in a blanket fashion. The mask layer  250  conformally covers the pMOS region  101  and the nMOS region  102 . In the pMOS region  101 , the mask layer  250  is deposited directly on the mask layer  150  and is in direct contact with the second dielectric layer  152 . In the nMOS region  102 , the mask layer  250  is in direct contact with the dense oxide film  161 , the first epitaxial layer  214 , and the hard mask oxide layer  144 . The mask layer  250  such as a silicon-rich silicon nitride layer may be deposited by using an ALD process including a plurality of ALD cycles. The dense oxide film  161  on the spacer  151   a  helps to deposit a high-quality, highly uniform silicon nitride film at the first 15-20 ALD cycles during the aforesaid ALD process. 
     As shown in  FIG. 5 , subsequently, the nMOS region  102  may be covered with a resist layer (not shown) such as a photoresist layer and the mask layer  250  in the pMOS region  101  is exposed. The exposed mask layer  250  is then removed from the pMOS region  101 . A dry etching process is then performed to etch the semiconductor substrate  10  thereby forming a cavity  202  on each side of the gate  12  and a spacer  151   b  on the sidewall of the gate  12 . The cavity  202  is recessed into the main surface  10   a  of the semiconductor substrate  10  and is adjacent to the spacer  151   b . The resist layer (not shown) in the nMOS region  102  is then removed. 
     Subsequently, a pre-clean process may be performed. The pre-clean process may use either an aqueous solution of hydrogen fluoride (HF), or a gas phase HF to remove the surface defects or contaminations, but is not limited thereto. Other pre-clean methods may be employed. After the pre-clean process, the remaining thickness of the mask layer  250  in the nMOS region  102  may be equal to or less than 20 angstroms. An epitaxial growth process is then performed to grow a second epitaxial layer  212  such as SiGe in the cavity  202 . Since the remaining mask layer  250  comprises high-quality ALD deposited Si-rich silicon nitride, the SiGe growth in the nMOS region  102  may be avoided. 
     As shown in  FIG. 6 , after the dual epitaxial process as set forth through  FIG. 1  to  FIG. 5 , a typical high-k/metal gate (HK/MG) process may be performed to form the semiconductor MOS devices  2  and  4  in the pMOS region  101  and nMOS region  102 , respectively. First, for example, the remaining mask layer  250  may be removed from the nMOS region  102 . When removing the remaining mask layer  250 , the dense oxide film  161  may function as a protection layer or a stop layer that protects the integrity of the underlying spacer  151   a . Subsequently, a contact etch stop layer (CESL)  320  such as a silicon nitride layer and an inter-layer dielectric (ILD) layer  330  such as a silicon oxide layer may be deposited in a blanket fashion. 
     As shown in  FIG. 7 , a chemical mechanical polishing (CMP) process may be performed to remove an upper portion of the ILD layer  330 , a portion of the CESL  320 , a portion of the spacer  151   a , a portion of the spacer  151   b , a portion of the offset spacer  126 , a portion of the offset spacer  146 , the hard mask oxide layer  124 , the hard mask oxide layer  144 , the thin silicon nitride layer  123 , and the thin silicon nitride layer  143 , thereby exposing a top surface of the polysilicon layer  122  and a top surface of the polysilicon layer  142 . Thereafter, the polysilicon layers  122  and  142  are removed to form gate trenches. Subsequently, replacement gate structures  410  and  420  may be formed within the gate trenches in the pMOS region  101  and nMOS region  102 , respectively. The replacement gate structure  410  may comprise a high-k dielectric layer  412   a  and a metal gate  414   a . The replacement gate structure  420  may comprise a high-k dielectric layer  412   b  and a metal gate  414   b.    
     According to one embodiment, for example, the metal gates  414   a ,  414   b  may comprise at least a metal film including, but not limited to, tantalum nitride (TaN) or titanium nitride (TiN), titanium carbide (TiC), tantalum carbide (TaC), tungsten carbide (WC), titanium aluminide (TiAl), aluminum titanium nitride (TiAlN), aluminum, tungsten, titanium aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP). 
     According to one embodiment, for example, the high-k dielectric layers  412   a ,  412   b  may comprise hafnium oxide (HfO 2 ), hafnium silicon oxide (HfSiO 4 ), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al 2 O 3 ), lanthanum oxide (La 2 O 3 ), tantalum oxide (Ta 2 O 5 ), yttrium oxide (Y 2 O 3 ), zirconium oxide (ZrO 2 ), strontium titanate oxide (SrTiO 3 ), zirconium silicon oxide (ZrSiO 4 ), hafnium zirconium oxide (HfZrO 4 ), strontium bismuth tantalate (SrBi 2 Ta 2 O 9 , SBT), lead zirconate titanate (PbZr x Ti 1-x O 3 , PZT), or barium strontium titanate (Ba x Sr 1-x TiO 3 , BST). 
     After forming the high-k dielectric layers  412   a ,  412   b  and metal gates  414   a ,  414   b , contact plugs  512  and  514  are formed in the ILD layer. The contact plugs  512  and  514  may be referred to as M0 contact. Optionally, a dielectric layer (not shown) may be deposited in a blanket fashion before the contact plugs  512  and  514  are formed. The contact plugs  512  and  514  may be in direct contact with the CESL  320  in the pMOS region  101  and nMOS region  102 , respectively. 
     Still referring to  FIG. 7 , the present invention in one aspect discloses a semiconductor MOS device  4 . According to one embodiment, the semiconductor MOS device  4  is an n-type metal-oxide-semiconductor field-effect transistor (nMOSFET) device. The semiconductor MOS device  4  includes a semiconductor substrate  10 , an inter-layer dielectric (ILD) layer  330  (shown in  FIG. 6 ) on the substrate  10 , a gate  420  in the ILD layer  330 , an offset liner  146  on a sidewall of the gate  420 , a spacer  151   a  on the offset liner  146 , a dense oxide film  161  on the spacer  151   a , a contact etch stop layer  320  on the dense oxide film  161 , and a contact plug  514  adjacent to the contact etch stop layer  320 . The contact etch stop layer  320  is in direct contact with the dense oxide film  161 . 
     The semiconductor MOS device  4  further includes a source region S in the semiconductor substrate  10  and a drain region D spaced apart from the source region S. A channel  134  is located between the source region S and the drain region D. The dense oxide film  161  has a thickness that is smaller or equal to 12 angstroms. 
     According to one embodiment, a SiP epitaxial layer  214  is disposed either in the source region S or in the drain region D. The offset liner  146  comprises carbon and nitrogen doped silicon oxide. The spacer  151   a  comprises carbon and nitrogen doped silicon oxide. 
     Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.