Patent Publication Number: US-9905190-B2

Title: Driving circuit applied to LCD apparatus

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates to a display apparatus, especially to a driving circuit applied to a LCD apparatus. 
     2. Description of the Prior Art 
     Please refer to  FIG. 1 .  FIG. 1  illustrates a schematic diagram of the conventional driving circuit applied to the LCD apparatus. As shown in  FIG. 1 , the driving circuit  1  includes a first channel CH 1  and a second channel CH 2 . Wherein, the first channel CH 1  includes latching units  10 A and  11 A, a level shifting unit  12 A, a digital-analog converting unit  13 A and an operational amplifying unit  14 A; the second channel CH 2  includes latching units  10 B and  11 B, a level shifting unit  12 B, a digital-analog converting unit  13 B and an operational amplifying unit  14 B. The input terminals of the latching units  10 A and  10 B are coupled to two output terminals of the shifting register SR respectively. 
     The transistor SW 1  is coupled between the output terminal of the operational amplifying unit  14 A and a positive voltage (3V). The gate of the transistor SW 1  is coupled to the switches PSW 1  and PSW 2  respectively, wherein the switch PSW 1  is coupled to another positive voltage (6V) and the switch PSW 2  is coupled between the digital-analog converting unit  13 A and the operational amplifying unit  14 A. When the digital-analog converting unit  13 A inputs an input voltage higher than the positive voltage 3V into the operational amplifying unit  14 A, the switch PSW 1  will be switched on and the switch PSW 2  will be switched off. Otherwise, the switch PSW 2  will be switched on and the switch PSW 1  will be switched off. 
     Similarly, the transistor SW 2  is coupled between the output terminal of the operational amplifying unit  14 B and a negative voltage (−3V). The gate of the transistor SW 2  is coupled to the switches PSW 3  and PSW 4  respectively, wherein the switch PSW 3  is coupled to another negative voltage (−6V) and the switch PSW 4  is coupled between the digital-analog converting unit  13 B and the operational amplifying unit  14 B. When the digital-analog converting unit  13 B inputs an input voltage higher than the positive voltage 3V into the operational amplifying unit  14 B, the switch PSW 3  will be switched on and the switch PSW 4  will be switched off. Otherwise, the switch PSW 4  will be switched on and the switch PSW 3  will be switched off. 
     Compared with the ordinary amplifier OP driving data by driving the voltage source having AVDD level or NAVDD level all the time to charge to a target voltage level, the power saving mechanism of this driving circuit structure is to drive the voltage source having VCI level or NVCI level to pre-charge to a specific voltage level at first and then drive the voltage source having AVDD level or NAVDD level to continuously charge to the target voltage level. 
     By doing so, if AVDD=2*VCI and NAVDD=2*NVCI, there will be about half of the power consumption can be saved before driving the voltage source having AVDD level or NAVDD level to charge. 
     However, the above-mentioned driving circuit structure has the following drawbacks: 
     (1) When the value of the data becomes zero, the charges stored in the data line capacitor will not be collected. 
     (2) Using the most significant bit (MSB) of the data and pre-charging to the VCI level or NVCI level may cause over-charging and more power consumption. 
     SUMMARY OF THE INVENTION 
     Therefore, the invention provides a driving circuit applied to a LCD apparatus to solve the above-mentioned problems. 
     An embodiment of the invention is a driving circuit. In this embodiment, the driving circuit is applied to a LCD apparatus. The driving circuit includes a first channel data line, a first reference voltage generation unit, a first external storage capacitor, a first comparing unit, a first switching unit and a first operation unit. The first channel data line is configured to transmit a first data. The first reference voltage generation unit is configured to generate a first reference voltage. A terminal of the first external storage capacitor is coupled to a ground terminal. Two input terminals of the first comparing unit are coupled to the first reference voltage generation unit and another terminal of the first external storage capacitor respectively to receive the first reference voltage and a first capacitor voltage respectively and an output terminal of the first comparing unit outputs a first comparing result. The first switching unit is coupled to the another terminal of the first external storage capacitor and the first channel data line respectively. first operation unit coupled to the output terminal of the first comparing unit, the first channel data line and the first switching unit respectively, wherein the first operation unit generates a first operational result according to the first comparing result and a most significant bit (MSB) of the first data and then selectively switches on the first switching unit according to the first operational result. 
     In an embodiment, the first reference voltage generation unit includes a plurality of resistors coupled in series between a first voltage and a second voltage to provide the first reference voltage. 
     In an embodiment, the first voltage is higher than the second voltage and the first reference voltage is a positive voltage. 
     In an embodiment, the first data transmitted by the first channel data line has a positive voltage. 
     In an embodiment, the driving circuit includes a first determining unit coupled to the first channel data line, wherein the first determining unit is configured to determine whether a first level of the first data is a high voltage level or a low voltage level. 
     In an embodiment, when the first data is discharged from the first level to a zero level, if the first determining unit determines that the first level of the first data is the high voltage level and the first comparing result is that the first capacitor voltage is lower than the first reference voltage, then the first operation unit switches on the first switching unit to make charges on the first channel data line to be stored in the first external storage capacitor; if the first determining unit determines that the first level of the first data is the low voltage level, then the first operation unit switches off the first switching unit to prevent the charges stored in the first external storage capacitor from flowing back to the first channel data line. 
     In an embodiment, when the first data is charged from a zero level to a first setting level, if the first determining unit determines that the first level of the first data is the high voltage level and the first comparing result is that the first capacitor voltage is higher than the first reference voltage, then the first operation unit switches on the first switching unit to make the first channel data line be pre-charged by charges stored in the first external storage capacitor; if the first determining unit determines that the first level of the first data is the low voltage level, then the first operation unit switches off the first switching unit to prevent the first channel data line from being over-charged. 
     In an embodiment, the driving circuit includes a second channel data line, a second reference voltage generation unit, a second external storage capacitor, a second comparing unit, a second switching unit and a second operation unit. The second channel data line is configured to transmit a second data. The second reference voltage generation unit is configured to generate a second reference voltage. A terminal of the second external storage capacitor is coupled to a ground terminal. Two input terminals of the second comparing unit are coupled to the second reference voltage generation unit and another terminal of the second external storage capacitor respectively to receive the second reference voltage and a second capacitor voltage respectively and an output terminal of the second comparing unit outputs a second comparing result. The second switching unit is coupled to the another terminal of the second external storage capacitor and an output terminal of the second channel data line. The second operation unit is coupled to the output terminal of the second comparing unit, the second channel data line and the second switching unit respectively, wherein the second operation unit generates a second operational result according to the second comparing result and a most significant bit (MSB) of the second data and then selectively switches on the second switching unit according to the second operational result. 
     In an embodiment, the second reference voltage generation unit includes a plurality of resistors coupled in series between a third voltage and a fourth voltage to provide the second reference voltage. 
     In an embodiment, the third voltage is lower than the fourth voltage and the second reference voltage is a negative voltage. 
     In an embodiment, the second data transmitted by the second channel data line has a negative voltage. 
     In an embodiment, the driving circuit includes a second determining unit coupled to the second channel data line, wherein the second determining unit is configured to determine whether a second level of the second data is a high voltage level or a low voltage level. 
     In an embodiment, when the second data is charged from the second level to a zero level, if the second determining unit determines that the second level of the second data is the low voltage level and the second comparing result is that the second capacitor voltage is higher than the second reference voltage, then the second operation unit switches on the second switching unit to make the second channel data line be pre-charged by charges stored in the second external storage capacitor; if the second determining unit determines that the second level of the second data is the high voltage level, then the second operation unit switches off the second switching unit to prevent the second channel data line from being over-charged. 
     In an embodiment, when the second data is discharged from a zero level to a second setting level, if the second determining unit determines that the second level of the second data is the low voltage level and the second comparing result is that the second capacitor voltage is lower than the second reference voltage, then the second operation unit switches on the second switching unit to make charges on the second channel data line to be stored to the second external storage capacitor; if the second determining unit determines that the second level of the second data is the high voltage level, then the second operation unit switches off the second switching unit to prevent the charges stored in the second external storage capacitor from flowing back to the second channel data line. 
     Compared to the prior arts, the driving circuit applied to the LCD apparatus in the invention can collect the charges discharged from the data line capacitor on the panel and then use the collected charges to pre-charge to a specific voltage level when the data line capacitor is charged next time, and then continuously charged to the target voltage level through the operational amplifier to save the power consumption. In addition, the driving circuit applied to the LCD apparatus in the invention determines whether to switch on the switch on the pre-charging path or not based on the external capacitor voltage detection result of the comparator and the pre-charging source is a passive capacitor which can effectively prevent the data line capacitor from being over-charged. 
     The advantage and spirit of the invention may be understood by the following detailed descriptions together with the appended drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE APPENDED DRAWINGS 
         FIG. 1  illustrates a schematic diagram of the conventional driving circuit applied to the LCD apparatus. 
         FIG. 2  illustrates a schematic diagram of the driving circuit applied to the LCD apparatus in a preferred embodiment of the invention. 
         FIG. 3A ˜ FIG. 3E  illustrate timing diagrams of the levels of the signals shown in  FIG. 2 . 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     A preferred embodiment of the invention is a driving circuit. In this embodiment, the driving circuit is applied to a LCD apparatus. 
     Please refer to  FIG. 2 .  FIG. 2  illustrates a schematic diagram of the driving circuit applied to the LCD apparatus in this embodiment. 
     As shown in  FIG. 2 , the driving circuit  2  can include a first channel CH 1  and a second channel CH 2 . Wherein, the first channel CH 1  includes latching units  20 A and  21 A, a level shifting unit  22 A, a digital-analog converting unit  23 A and an operational amplifying unit  24 A. And, the latching units  20 A and  21 A, the level shifting unit  22 A, the digital-analog converting unit  23 A and the operational amplifying unit  24 A are coupled in series in order through a first channel data line DL 1 ; the second channel CH 2  includes latching units  20 B and  21 B, a level shifting unit  22 B, a digital-analog converting unit  23 B and an operational amplifying unit  24 B. And, the latching units  20 B and  21 B, the level shifting unit  22 B, the digital-analog converting unit  23 B and the operational amplifying unit  24 B are coupled in series in order through a second channel data line DL 2 . 
     The input terminal of the latching unit  20 A of the first channel CH 1  and the input terminal of the latching unit  20 B of the second channel CH 2  are coupled to two output terminals of the shifting register SR respectively. Two switches SW 3  and SW 4  are coupled in series between the output terminal of the operational amplifying unit  24 A of the first channel CH 1  and the output terminal of the operational amplifying unit  24 B of the second channel CH 2 ; a node between the two switches SW 3  and SW 4  is coupled to the ground terminal GND. 
     It should be noticed that if the first channel CH 1  is a positive voltage channel and the second channel CH 2  is a negative voltage channel, then the first data DATA 1  transmitted by the first channel data line DL 1  has positive voltage and the second data DATA 2  transmitted by the second channel data line DL 2  has negative voltage. The level shifting unit  22 A, the digital-analog converting unit  23 A and the operational amplifying unit  24 A can be a P-type level shifter, a P-type level digital-analog converter and a P-type operational amplifier respectively; the level shifting unit  22 B, the digital-analog converting unit  23 B and the operational amplifying unit  24 B can be a N-type level shifter, a N-type level digital-analog converter and a N-type operational amplifier respectively. 
     In this embodiment, the driving circuit  2  also includes a first reference voltage generation unit RVG 1 , a first external storage capacitor ESC 1 , a first comparing unit CMP 1 , a first switching unit SW 1 , a first operation unit OU 1  and a first determining unit AD 1 . The first channel data line DL 1  is used to transmit a first data DATA 1 . The first reference voltage generation unit RVG 1  is used to generate a first reference voltage VREF 1 . A terminal of the first external storage capacitor ESC 1  is coupled to the ground terminal GND. 
     Two input terminals of the first comparing unit CMP 1  are coupled to the first reference voltage generation unit RVG 1  and another terminal of the first external storage capacitor ESC 1  respectively and receive a first reference voltage VREF 1  and a first capacitor voltage VC 1  respectively and output a first comparison result SCP 1  through the output terminal of the first comparing unit CMP 1 . 
     The first switching unit SW 1  is coupled to another terminal of the first external storage capacitor ESC 1 , the output terminal of the operational amplifying unit  24 A and the output terminal of the first operation unit OU 1 . In practical applications, the first switching unit SW 1  is a P-type transistor, but not limited to this. In addition, a switch SWHZ 1  can be disposed between the first switching unit SW 1  and the output terminal of the first operation unit OU 1 . 
     The first determining unit AD 1  is coupled to the latching unit  21 A to determine whether the first voltage level of the first data DATA 1  stored in the latching unit  21 A is a high voltage level or a low voltage level. 
     The first operation unit OU 1  is coupled to the output terminal of the first comparing unit CMP 1 , the first determining unit AD 1  and the gate of the first switching unit SW 1 . The first operation unit OU 1  receives the first comparison result SCP 1  and the most significant bit MSB 1  of the first data DATA 1  respectively and generates a first operational result according to the first comparison result SCP 1  and the most significant bit MSB 1  of the first data DATA 1  and then selectively outputs a first switch control signal SNF 1  to the first switching unit SW 1  to switch on the first switching unit SW 1  according to the first operational result. 
     Similarly, the driving circuit  2  also includes a second reference voltage generation unit RVG 2 , a second external storage capacitor ESC 2 , a second comparing unit CMP 2 , a second switching unit SW 2 , a second operation unit OU 2  and a second determining unit AD 2 . The second channel data line DL 2  is used to transmit a second data DATA 2 . The second reference voltage generation unit RVG 2  is used to generate a second reference voltage VREF 2 . A terminal of the second external storage capacitor ESC 2  is coupled to the ground terminal GND. 
     Two input terminals of the second comparing unit CMP 2  are coupled to the second reference voltage generation unit RVG 2  and another terminal of the second external storage capacitor ESC 2  respectively and receive a second reference voltage VREF 2  and a second capacitor voltage VC 2  respectively and output a second comparison result SCP 2  through the output terminal of the second comparing unit CMP 2 . 
     The second switching unit SW 2  is coupled to another terminal of the second external storage capacitor ESC 2 , the output terminal of the operational amplifying unit  24 B and the output terminal of the second operation unit OU 2 . In practical applications, the second switching unit SW 2  is an N-type transistor, but not limited to this. In addition, a switch SWHZ 2  can be disposed between the second switching unit SW 2  and the output terminal of the second operation unit OU 2 . 
     The second determining unit AD 2  is coupled to the latching unit  21 B to determine whether the second voltage level of the second data DATA 2  stored in the latching unit  21 B is a high voltage level or a low voltage level. 
     The second operation unit OU 2  is coupled to the output terminal of the second comparing unit CMP 2 , the second determining unit AD 2  and the gate of the second switching unit SW 2 . The second operation unit OU 2  receives the second comparison result SCP 2  and the most significant bit MSB 2  of the second data DATA 2  respectively and generates a second operational result according to the second comparison result SCP 2  and the most significant bit MSB 2  of the second data DATA 2  and then selectively outputs a second switch control signal SNF 2  to the second switching unit SW 2  to switch on the second switching unit SW 2  according to the second operational result. 
     In an embodiment, the first reference voltage generation unit RVG 1  can include N resistors R 1 ˜RN, and the N resistors R 1 ˜RN are coupled in series between the first voltage VGMP and the second voltage VGSP to provide the first reference voltage VREF 1 . Wherein, the first voltage VGMP is higher than the second voltage VGSP, and the first reference voltage VREF 1  is a positive voltage, and N is a positive integer. 
     At first, how to store data line charges through the storing capacitor in the discharging process will be introduced as follows. 
     When the first data DATA 1  is discharged from the first level to a zero level, the first determining unit AD 1  will determine whether the first level of the first data DATA 1  is the high voltage level or the low voltage level. If the first determining unit AD 1  determines that the first level of the first data DATA 1  is the high voltage level and the first comparing result SCP 1  of the first comparing unit CMP 1  is that the first capacitor voltage VC 1  is lower than the first reference voltage VREF 1 , then the first operation unit OU 1  will switch on the first switching unit SW 1  to make charges on the first channel data line DL 1  to be stored in the first external storage capacitor ESC 1 ; if the first determining unit AD 1  determines that the first level of the first data DATA 1  is the low voltage level, then the first operation unit OU 1  will switch off the first switching unit SW 1  to prevent the charges stored in the first external storage capacitor ESC 1  from flowing back to the first channel data line DL 1 . 
     From above, it can be found that in the discharging process, only when the first level is a high voltage level and the first capacitor voltage VC 1  is lower than the first reference voltage VREF 1 , the first switching unit SW 1  can be switched on, so that the charges on the first channel data line DL 1  can be smoothly stored in the first external storage capacitor ESC 1  without the condition that the charges flowing back to the first channel data line DL 1 . 
     Then, the condition that the data line is pre-charged by the data line charge stored in the storing capacitor during the charging process will be introduced as follows. 
     When the first data DATA 1  is charged from a zero level to a first setting level, the first determining unit AD 1  will determine that the first level of the first data DATA 1  is the high voltage level or the low voltage level. If the first determining unit AD 1  determines that the first level of the first data DATA 1  is the high voltage level and the first comparing result SCP 1  of the first comparing unit CMP 1  is that the first capacitor voltage VC 1  is higher than the first reference voltage VREF 1 , then the first operation unit OU 1  will switch on the first switching unit SW 1  to make the first channel data line DL 1  be pre-charged by the charges stored in the first external storage capacitor ESC 1 ; if the first determining unit AD 1  determines that the first level of the first data DATA 1  is the low voltage level, then the first operation unit OU 1  will switch off the first switching unit SW 1  to prevent the first channel data line DL 1  from being over-charged. 
     From above, it can be found that during the charging process, the first switching unit SW 1  will be switched on only when the first level of the first data DATA 1  is the high voltage level and the first capacitor voltage VC 1  is higher than the first reference voltage VREF 1 , so that the first channel data line DL 1  can be smoothly pre-charged by the charges stored by the first external storage capacitor ESC 1  and the first channel data line DL 1  can be prevented from being over-charged. 
     Similarly, the second reference voltage generation unit RVG 2  can include N resistors R 1 ˜RN, and the N resistors R 1 ˜RN are coupled in series between the third voltage VGSN and the fourth voltage VGMN to provide the second reference voltage VREF 2 . Wherein, the third voltage VGSN is lower than the fourth voltage VGMN, and the second reference voltage VREF 2  is a negative voltage. 
     When the second data DATA 2  is charged from the second level to a zero level, if the second determining unit AD 2  determines that the second level of the second data is the low voltage level and the second comparing result SCP 2  of the second comparing unit CMP 2  is that the second capacitor voltage VC 2  is higher than the second reference voltage VREF 2 , then the second operation unit OU 2  will switch on the second switching unit SW 2  to make the second channel data line DL 2  be pre-charged by the charges stored in the second external storage capacitor ESC 2 ; if the second determining unit AD 2  determines that the second level of the second data DATA 2  is the high voltage level, then the second operation unit OU 2  will switch off the second switching unit SW 2  to prevent the second channel data line DL 2  from being over-charged. 
     When the second data DATA 2  is discharged from a zero level to a second setting level, if the second determining unit AD 2  determines that the second level of the second data is the low voltage level and the second comparing result SCP 2  of the second comparing unit CMP 2  is that the second capacitor voltage VC 2  is lower than the second reference voltage VREF 2 , then the second operation unit OU 2  will switch on the second switching unit SW 2  to make the charges on the second channel data line DL 2  to be stored to the second external storage capacitor ESC 2 ; if the second determining unit AD 2  determines that the second level of the second data DATA 2  is the high voltage level, then the second operation unit OU 2  will switch off the second switching unit SW 2  to prevent the charges stored in the second external storage capacitor ESC 2  from flowing back to the second channel data line DL 2 . 
     Then, please refer to  FIG. 3A ˜ FIG. 3E .  FIG. 3A ˜ FIG. 3E  illustrate timing diagrams of the levels of the signals shown in  FIG. 2 . Wherein,  FIG. 3A  illustrates the timing diagram of the control signal of the switch SWHZ 1 ;  FIG. 3B  illustrates the timing diagram of the control signal of the switch SW 3 ;  FIG. 3C  illustrates the timing diagram of the first data DATA 1 ;  FIG. 3D  illustrates the timing diagram of the first comparing result SCP 1  of  FIG. 2 ;  FIG. 3E  illustrates the timing diagram of the first switch control signal SNF 1  of the first switching unit SW 1  of  FIG. 2 . 
     At the time T 1 , the control signal of the switch SWHZ 1  in  FIG. 3A  is changed from the high level to the low level, and it represents that the output terminal of the first operation unit OU 1  and the first switching unit SW 1  and the panel data lines are disconnected; the control signal of the switch SW 3  in  FIG. 3B  is at the low level, it represents that the first switching unit SW 1  and the panel data lines are not coupled to the ground terminal GND; the first data DATA 1  in  FIG. 3C  has a target high level and ready to start the charging process; the first comparing result SCP 1  in  FIG. 3D  is at the low level, it represents that the first comparing result SCP 1  is that the first capacitor voltage VC 1  is lower than the first reference voltage VREF 1 ; since the first data DATA 1  has the high level and the first capacitor voltage VC 1  is lower than the first reference voltage VREF 1 , the first switch control signal SNF 1  of the first switching unit SW 1  in  FIG. 3E  will be changed from the low level to the high level, it represents that the first switching unit SW 1  will be switched on and conducted at this time. 
     At the time T 2 , the control signal of the switch SWHZ 1  in  FIG. 3A  is maintained the low level, and it represents that the output terminal of the first operation unit OU 1  and the first switching unit SW 1  and the panel data lines are maintained disconnected; the control signal of the switch SW 3  in  FIG. 3B  is changed from the low level to the high level, it represents that the first switching unit SW 1  and the panel data lines are coupled to the ground terminal GND; the level of the first data DATA 1  in  FIG. 3C  is continuously decreased from the high level, it represents that the charges on the data line are discharged to the storage capacitor; the first comparing result SCP 1  in  FIG. 3D  is maintained at the low level, it represents that the first comparing result SCP 1  is still that the first capacitor voltage VC 1  is lower than the first reference voltage VREF 1 ; since the first data DATA 1  no longer has the high level, the first switch control signal SNF 1  of the first switching unit SW 1  in  FIG. 3E  will be changed from the high level to the low level, it represents that the first switching unit SW 1  will be switched off and not conducted at this time. 
     At the time T 3 , the control signal of the switch SWHZ 1  in  FIG. 3A  is maintained the low level, and it represents that the output terminal of the first operation unit OU 1  and the first switching unit SW 1  and the panel data lines are maintained disconnected; the control signal of the switch SW 3  in  FIG. 3B  is changed from the high level to the low level, it represents that the first switching unit SW 1  and the panel data lines are not coupled to the ground terminal GND; the level of the first data DATA 1  in  FIG. 3C  is continuously decreased toward the target low level, it represents that the discharging process will be ended soon and it will be changed to the charging process from the storage capacitor to the data line; the first comparing result SCP 1  in  FIG. 3D  is changed from the low level to the high level, it represents that the first comparing result SCP 1  is that the first capacitor voltage VC 1  is higher than the first reference voltage VREF 1 ; the first switch control signal SNF 1  of the first switching unit SW 1  in  FIG. 3E  is maintained the low level, it represents that the first switching unit SW 1  is still switched off and not conducted at this time. 
     At the time T 4 , the control signal of the switch SWHZ 1  in  FIG. 3A  is changed from the low level to the high level, and it represents that the output terminal of the first operation unit OU 1  and the first switching unit SW 1  and the panel data lines are electrically connected; the control signal of the switch SW 3  in  FIG. 3B  is maintained the low level, it represents that the first switching unit SW 1  and the panel data lines are not coupled to the ground terminal GND; the level of the first data DATA 1  in  FIG. 3C  is decreased to the target low level; the first comparing result SCP 1  in  FIG. 3D  is maintained the high level, it represents that the first comparing result SCP 1  is that the first capacitor voltage VC 1  is higher than the first reference voltage VREF 1 ; the first switch control signal SNF 1  of the first switching unit SW 1  in  FIG. 3E  is maintained the low level, it represents that the first switching unit SW 1  is still switched off and not conducted at this time. 
     At the time T 5 , the control signal of the switch SWHZ 1  in  FIG. 3A  is changed from the high level to the low level, and it represents that the output terminal of the first operation unit OU 1  and the first switching unit SW 1  and the panel data lines are disconnected; the control signal of the switch SW 3  in  FIG. 3B  is maintained the low level, it represents that the first switching unit SW 1  and the panel data lines are not coupled to the ground terminal GND; the first data DATA 1  having the target low level in  FIG. 3C  is ready to discharge; the first comparing result SCP 1  in  FIG. 3D  is maintained the high level, it represents that the first comparing result SCP 1  is that the first capacitor voltage VC 1  is higher than the first reference voltage VREF 1 ; the first switch control signal SNF 1  of the first switching unit SW 1  in  FIG. 3E  is maintained the low level, it represents that the first switching unit SW 1  is still switched off and not conducted at this time. 
     At the time T 6 , the control signal of the switch SWHZ 1  in  FIG. 3A  is maintained the low level, and it represents that the output terminal of the first operation unit OU 1  and the first switching unit SW 1  and the panel data lines are disconnected; the control signal of the switch SW 3  in  FIG. 3B  is changed from the low level to the high level, it represents that the first switching unit SW 1  and the panel data lines are coupled to the ground terminal GND; the first data DATA 1  in  FIG. 3C  is continuously increased, and the data line is charged; the first comparing result SCP 1  in  FIG. 3D  is maintained the high level, it represents that the first comparing result SCP 1  is that the first capacitor voltage VC 1  is higher than the first reference voltage VREF 1 ; the first switch control signal SNF 1  of the first switching unit SW 1  in  FIG. 3E  is maintained the low level, it represents that the first switching unit SW 1  is still switched off and not conducted at this time. 
     At the time T 7 , the control signal of the switch SWHZ 1  in  FIG. 3A  is maintained the low level, and it represents that the output terminal of the first operation unit OU 1  and the first switching unit SW 1  and the panel data lines are disconnected; the control signal of the switch SW 3  in  FIG. 3B  is changed from the high level to the low level, it represents that the first switching unit SW 1  and the panel data lines are not coupled to the ground terminal GND; the first data DATA 1  in  FIG. 3C  is continuously increased, and the data line is charged to the high level; the first comparing result SCP 1  in  FIG. 3D  is maintained the high level, it represents that the first comparing result SCP 1  is that the first capacitor voltage VC 1  is higher than the first reference voltage VREF 1 ; the first switch control signal SNF 1  of the first switching unit SW 1  in  FIG. 3E  is changed from the low level to the high level, it represents that the first switching unit SW 1  is switched on and conducted at this time. 
     At the time T 8 , the control signal of the switch SWHZ 1  in  FIG. 3A  is changed from the low level to the high level, and it represents that the output terminal of the first operation unit OU 1  and the first switching unit SW 1  and the panel data lines are electrically connected; the control signal of the switch SW 3  in  FIG. 3B  is maintained the low level, it represents that the first switching unit SW 1  and the panel data lines are not coupled to the ground terminal GND; the first data DATA 1  in  FIG. 3C  has the target high level; the first comparing result SCP 1  in  FIG. 3D  is maintained the high level, it represents that the first comparing result SCP 1  is that the first capacitor voltage VC 1  is higher than the first reference voltage VREF 1 ; the first switch control signal SNF 1  of the first switching unit SW 1  in  FIG. 3E  is changed from the high level to the low level, it represents that the first switching unit SW 1  is switched off and not conducted at this time. 
     Compared to the prior arts, the driving circuit applied to the LCD apparatus in the invention can collect the charges discharged from the data line capacitor on the panel and then use the collected charges to pre-charge to a specific voltage level when the data line capacitor is charged next time, and then continuously charged to the target voltage level through the operational amplifier to save the power consumption. In addition, the driving circuit applied to the LCD apparatus in the invention determines whether to switch on the switch on the pre-charging path or not based on the external capacitor voltage detection result of the comparator and the pre-charging source is a passive capacitor which can effectively prevent the data line capacitor from being over-charged. 
     With the example and explanations above, the features and spirits of the invention will be hopefully well described. Those skilled in the art will readily observe that numerous modifications and alterations of the device may be made while retaining the teaching of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.