Patent Publication Number: US-10325814-B2

Title: Patterning of vertical nanowire transistor channel and gate with directed self assembly

Description:
This is a Continuation of application Ser. No. 15/247,826 filed Aug. 25, 2016 Continuation of application Ser. No. 14/997,458 filed Jan. 15, 2016 now U.S. Pat. No. 9,431,518 issued Aug. 30, 2016 which is a Continuation of application Ser. No. 14/733,925 filed Jun. 8, 2015 now U.S. Pat. No. 9,269,630 issued Feb. 23, 2016 which is Continuation of application Ser. No. 13/719,113 filed Dec. 18, 2012 now U.S. Pat. No. 9,054,215 issued Jun. 9, 2015 which are hereby incorporated by reference. 
    
    
     TECHNICAL FIELD 
     Embodiments of the invention generally relate to transistor fabrication for microelectronics, and more particularly pertain to patterning of a vertical nanowire transistor using directed self-assembly (DSA). 
     BACKGROUND 
     In vertically oriented transistors, well-controlled material layer thickness define functional lengths, such as gate length (L g ), and material composition may be advantageously tailored to achieve band gap and mobility differentiation. Current drive can also be continuously scaled by lithographic patterning of the channel width (W g ) and corresponding cross-section of the nanowire. However, in practical applications, one may need to print nanowire features (e.g., holes) on the order of 15 nm or less in diameter while having very good critical dimension (CD) uniformity, good circularity, and of minimal feature pitch for highest density. In addition the channel pattern must be accurately aligned to the gate stack and contact metallization. 
     Lithographic printing of holes less than 15 nm with sufficient CD uniformity, circularity, and pitch is beyond the capability of known ArF or EUV resist. Techniques whereby holes are printed larger and then shrunk fail to achieve desired pitches (e.g., &lt;30 nm). Such pitches are also below the resolution of even two mask patterning techniques, and as such would require at least three mask patterning steps along with a very aggressive shrink process employing an expensive lithography toolset. 
     Techniques to pattern a vertical nanowire transistor to dimensions below 15 nm and pitches below 30 nm, which are manufacturable at lower cost are therefor advantageous. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Embodiments of the present invention are illustrated by way of example, and not limitation, in the figures of the accompanying drawings in which: 
         FIG. 1  is an isometric illustration of a vertical nanowire transistor, in accordance with an embodiment; 
         FIG. 2  is a flow diagram illustrating a method of forming a vertical nanowire transistor, in accordance with an embodiment; 
         FIGS. 3A, 3B, 3C, 3D, and 3E  illustrate plan views of single-channel structures formed as operations in the method of  FIG. 2  are performed, in accordance with an embodiment; 
         FIGS. 4A, 4B, 4C, 4D, and 4E  illustrate cross-sectional views of the structures illustrated in  FIG. 3A-3E , in accordance with an embodiment; 
         FIGS. 5A, 5B, 5C, 5D, 5E, and 5F  illustrate plan views of single-channel structures formed as operations in the method of  FIG. 2  are performed, in accordance with an embodiment; 
         FIGS. 6A, 6B, 6C, 6D, 6E, and 6F  illustrate cross-sectional views of the structures illustrated in  FIG. 5A-5D , in accordance with an embodiment; 
         FIGS. 7A, 7B, and 7C  illustrate plan views of dual-channel structures formed as operations in the method of  FIG. 2  are performed, in accordance with an embodiment; 
         FIGS. 8A, 8B, and 8C  illustrate cross-sectional views of the structures illustrated in  FIG. 7A-7C , in accordance with an embodiment; 
         FIGS. 9A, 9B, 9C, 9D, and 9E  illustrate cross-sectional views of single-channel structures formed as operations in the method of  FIG. 2  are performed, in accordance with an embodiment; 
         FIGS. 10A, 10B, 10C, 10D, 10E, 10F and 10G  illustrate cross-sectional views of single-channel structures formed as operations in the method of  FIG. 2  are performed, in accordance with an embodiment; 
         FIG. 11  is a functional block diagram of a mobile computing platform employing non-planar transistors, in accordance with an embodiment of the present invention; and 
         FIG. 12  illustrates a functional block diagram of computing device in accordance with one embodiment. 
     
    
    
     DETAILED DESCRIPTION 
     In the following description, numerous details are set forth. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without these specific details. In some instances, well-known methods and devices are shown in block diagram form, rather than in detail, to avoid obscuring the present invention. Reference throughout this specification to “an embodiment” or “in one embodiment” means that a particular feature, structure, function, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. Thus, the appearances of the phrase “in an embodiment” in various places throughout this specification are not necessarily referring to the same embodiment of the invention. Furthermore, the particular features, structures, functions, or characteristics may be combined in any suitable manner in one or more embodiments. For example, a first embodiment may be combined with a second embodiment anywhere the two embodiments are not structurally or functionally exclusive of the other. 
     The terms “coupled” and “connected,” along with their derivatives, may be used herein to describe structural relationships between components. It should be understood that these terms are not intended as synonyms for each other. Rather, in particular embodiments, “connected” may be used to indicate that two or more elements are in direct physical or electrical contact with each other. “Coupled” my be used to indicated that two or more elements are in either direct or indirect (with other intervening elements between them) physical or electrical contact with each other, and/or that the two or more elements co-operate or interact with each other (e.g., as in a cause an effect relationship). 
     The terms “over,” “under,” “between,” and “on” as used herein refer to a relative position of one material layer with respect to other layers. As such, for example, one layer disposed over or under another layer may be directly in contact with the other layer or may have one or more intervening layers. Moreover, one layer disposed between two layers may be directly in contact with the two layers or may have one or more intervening layers. In contrast, a first layer “on” a second layer is in direct contact with that second layer. 
       FIG. 1  is an isometric illustration of an exemplary vertical nanowire transistor  101 , which may be fabricated in accordance with embodiments of the present invention. For the vertical nanowire transistor  101 , a semiconductor nanowire is vertically oriented with respect to the substrate  105  so that the longitudinal length L is along the z dimension (perpendicular to a surface plane of the substrate  105 ) and the width W defines an area of the substrate  105  occupied by the nanowire. As for a laterally oriented transistor, the vertical transistor  101  comprises one or more semiconductor materials along the longitudinal length L corresponding to functional regions of the transistor including the channel region  145 B disposed between an extrinsic source/drain region  135 B, source/drain region  130 B and source/drain region  120 B. Depending on the embodiment a drain of the transistor  101  may be “down,” on the substrate  105 , or the transistor may be inverted to have “source down.” In the vertical form, the transistor  101  has critical dimensions, such as channel length and L g  (i.e., portions of the longitudinal length L) defined by material layer thickness, which can be very well-controlled (e.g., to 5-10 Å) by either epitaxial growth processes, implantation processes, or deposition processes. 
     Generally, substrate  105  and the first and second semiconductor material layers  111 C,  111 B may be any known in the art including group IV materials (e.g., Si, Ge, SiGe), III-N materials (e.g., GaN, AlGaN, etc.), or group III-V materials (e.g., InAlAs, AlGaAs, etc.). The drain/source regions  130 B,  120 B are of semiconductor material layers  111 A,  111 D, which may be the same material as for the channel region  145 B, or a different material. The source/drain contact  122 B may include a semiconductor  111 E disposed on the source/drain region  120 , such as a p+ tunneling layer and/or a highly doped (e.g., n+) low band gap capping layer. A low resistivity ohmic contact metal may further be included in the source contact  122 B. 
     The transistor  101  includes a gate stack  150 B coaxially wrapping completely around the nanowire within the channel region  145 B. Similarly, the source/drain contacts  122 B and  132 B are also illustrated as coaxially wrapping around the source/drain regions  120 B,  130 B, though they need not. Disposed between the gate stack  150 B, a first dielectric spacer (not depicted) is disposed on the source/drain contact  132 B and coaxially wraps completely around the extrinsic source/drain region  135 B along a first longitudinal length. A second dielectric spacer  156  is disposed on the gate stack  150 B and coaxially wraps completely around the source/drain region  120 B along a second longitudinal length with the source/drain contact  132 B disposed on the second dielectric spacer. 
       FIG. 2  is a flow diagram illustrating a method  201  of forming a vertical nanowire transistor, such as the transistor  101 , in accordance with an embodiment. Generally, the method  201  entails employing a directed self-assembly (DSA) material, such as a di-block co-polymer, to pattern features that ultimately define a channel region of a vertical nanowire transistor based on one lithographic operation, potentially without need for a scanner. 
     The method  201  begins with lithographically patterning a guide opening in a mask layer at operation  205 . The guide opening is to provide an edge that a DSA material aligns to, and is more particularly a closed polygon, and advantageously curved, and more particularly circular. Any number of guide openings may be concurrently printed at operation  205 , for example a 1-D or 2-D array of guide openings may be printed using any conventional lithographic process know in the art. As used herein, a 1-D array entails a row or column of guide openings with minimum pitch between adjacent ones in the row or column dimension and more than minimum pitch between adjacent rows or columns, while a 2-D array entails rows and columns of guide openings with minimum pitch between all guide openings in both row and column dimensions. The size and shape of the guide can be changed to allow more than one channel hole to be patterned in a given guide layer opening as for example  FIG. 7   b.    
       FIGS. 3A-3D  illustrate plan views of a single-channel transistor structure formed as operations in the method  201  are performed, in accordance with an embodiment. A circular guide opening  315  is shown in  FIG. 3A , and represents one repeating unit for a 1-D or 2-D array that is printed at operation  205 .  FIGS. 4A-4D  illustrate cross-sectional views of the structures illustrated in  FIG. 3A-3D , respectively, along the A′-A line depicted in  FIG. 3A . In the exemplary embodiment, the circular guide opening  315  has a critical dimension (CD 1 ) of no more than 20 nm with the polygon edge  306  defining a hole  305  ( FIG. 4A ) through a thickness of the mask  340 , which may be a photoresist or hardmask material. Any conventional resist formulation suitable for the lithography tool employed may be utilized in photoresist embodiments. The mask  340  is disposed over a semiconductor layer having a z-height thickness (T 1 ) corresponding to a desired transistor channel length (L g ) that is to provide the channel region of the nanowire transistor. For the exemplary embodiment illustrated in  FIG. 4A , the mask  340  is disposed directly on the channel semiconductor layer  315  (e.g., single crystalline silicon, SiGe, etc.), although an intervening material layer, such as a hardmask material layer (e.g., Si x N y , SiO 2 , etc.), may be disposed between the photoresist layer  340  and channel semiconductor layer  315 . 
     Returning to  FIG. 2 , the method  201  continues with operation  210  where the DSA material is deposited into the guide opening(s) formed at operation  205 . In preparation for application of the DSA material the surface of layer  315  may be treated so that it is equally attractive/repulsive to the polymer A and polymer B. As shown in  FIGS. 3B and 4B , a DSA material  350  fills the guide opening  315  and is contained by the guide opening edges  306 . The DSA material  350  generally comprises at least first and second polymers (i.e., a polymer A and a polymer B). When applied over the substrate, for example by spin coating, the polymers A and B are in an intermixed state. Beyond the basic chemistry of the polymers A and B, the polymers A and B may each be chosen to have desired distribution of molecular weights and the DSA material  350  may be selected to have a desired polymer A-to-polymer B ratio (A:B), as a function of the geometry and CD of the guide operation  315  and the desired CD of the transistor channel region. While any DSA material known in the art may be utilized, in the exemplary embodiment one of the polymer A and polymer B is present in a photoresist employed as the mask  340 . For example, where the mask  340  comprises polystyrene, polymer A or polymer B is also polystyrene. In one such embodiment, the other of the polymers is PMMA (poly(methyl methacrylate)). 
     The method  201  ( FIG. 2 ) continues with operation  215  where the DSA material is segregated into interior and exterior polymer regions. Segregation of the polymer A from the polymer B occurs while the DSA material  350  is annealed at an elevated temperature for a duration sufficient to permit adequate migration of the polymers, as a function of the dimensions of the guide opening  315 , and the molecular weights of the polymers, etc. With the guide opening  315  enclosing the DSA material  350 , segregation can be engineered so as one of the polymers (e.g., polymer A) migrates away from the guide edge  306  while the other of the polymers (e.g., polymer B) migrates toward the guide edge  306 . An interior polymer region  350 A comprising predominantly a first polymer is then completely surrounded by an exterior polymer region  350 B comprising predominantly a second polymer. In the exemplary embodiment shown in  FIGS. 3C and 4C , the interior polymer region  350 A is spaced apart from the guide opening edge to have a diameter of CD 2 , reduced from that of CD 1 . For appropriately chosen DSA constituents, under layer and guide opening edge surface properties, the interior polymer region  350 A form integer numbers of substantially identical cylinders or spheres embedded within the exterior polymer region  350 B. While in the exemplary single channel embodiment illustrated in  FIGS. 3A-3E  a single interior polymer region  350 A is formed, multiples of such regions may be formed where the guide opening is sized sufficiently large in at least one dimension. With the segregation mechanics being a well-controlled function of the co-polymer properties of the DSA material, the interior polymer region(s) maintain a consistent distance from each other and from the guide opening edges. As such, the interior polymer region  350 A is effectively self-aligned to the guide opening edge  306 . 
     Following the bake and/or cure performed at operation  215 , the method  201  continues to operation  220  where a semiconductor channel region of the transistor is defined within the interior of the guide opening by removing one of the interior and exterior polymer regions selectively to the other. In the exemplary embodiment illustrated in  FIGS. 3D and 4D , the exterior polymer region  350 B is removed (e.g., dissolved) selectively to the interior polymer region  350 A. As further shown, the exterior polymer region  350 B is also removed selectively to the mask  340  such that two edges are defined at operation  220 : an edge of the interior polymer region  350 A, and the guide opening edge  306  with the edge of the interior polymer region  350 A being self-aligned to the guide opening edge  306 . 
     An annular trench  375  is then etched through the channel semiconductor layer  315  and the interior polymer region  350 A removed, along with the mask  340 . The exposed portion of the channel semiconductor layer  325  may be recessed with any etch process known in the art for the given semiconductor material (Si, SiGe, etc.), to form a sidewall of a channel region  315 A associated with the transistor L g  aligned with an edge of the interior polymer region  350 A. As used herein, “aligned” permits some nominal etch bias (positive or negative) to be incurred which may change the CD of the channel region  315 A from that of CD 2 , but the dimension of the channel region  315 A is nevertheless based on that of the interior polymer region  350 A and as such, significantly smaller than the dimension of the guide opening (CD 1 ). For example, the sidewalls of the channel region  315 A may be aligned to the interior polymer region  350 A with an anisotropic etch through the channel region  315 A followed by an isotropic etch that recesses the sidewalls of the channel region  315 A relative to the CD of the interior polymer region  350 A. In one embodiment where the guide opening CD 1  is less than 20 nm, the channel region  315 A has a CD 2  of less than 15 nm. The trench  375  may be stopped on an underlying semiconductor material  310  (e.g., single crystalline Si, SiGe, Ge, etc.), on a basis of compositional etch selectivity or on the basis of a timed etch, for example. Depending on the embodiment, the underlying semiconductor material  310  is either already heavily doped to a particular conductivity typed, may be doped upon its exposure, or is partially removed and regrown as a doped material. In the embodiment illustrated in  FIGS. 3D and 4D , the semiconductor material  310  heavily doped to function as a source/drain region (e.g., source/drain region  111 A and/or extrinsic source/drain region  111 B in  FIG. 1 ). 
     With the semiconductor channel region defined at operation  220 , the method  201  continues with depositing a gate material over a sidewall of the semiconductor channel region at operation  225 . Generally, any gate dielectric deposition process known in the art may be performed, including deposition of a sacrificial gate dielectric which is to be subsequently replaced later in the fabrication process (e.g., as in a conventional “gate-last” type process flow). However, in the exemplary embodiment, at operation  225 , a non-sacrificial high-k (e.g., &gt;9) gate dielectric  380  is deposited on the semiconductor surface exposed at the bottom of the trench  375  and on the trench sidewalls  380 A and  380 B. As one example, a metal oxide, such as but not limited to HfO 2 , or ZrO 2 , is deposited by atomic layer deposition at operation  225  as the gate dielectric  380 . 
     The method  201  then completes with operation  230  where the semiconductor channel region  315 A is surrounded with a gate electrode material. In the exemplary embodiment, operation  230  comprises filling the cylindrical trench  375  with a gate electrode material  390 . The gate electrode material  390  may include any conventional gate electrode material, such as but not limited to polysilicon, a work function metal, and/or a fill metal. Techniques known in the art, such as but not limited to deposition and polish, may be utilized to planarize the gate electrode material  390  with the channel region  315 A, or an overlying hardmask layer. As shown in  FIGS. 3E and 4E , the gate dielectric  380  electrically isolates the gate electrode material  390  from the channel region  315 A, as well as from the underlying source/drain region  310  and peripheral semiconductor material  315 B. Notably, the dimensions of the gate electrode material  390  are therefore fully self-aligned to the guide opening edge  306  as well as self-aligned to the channel region  315 A with only the z-height thickness of the gate electrode material  390  left to vary as a function of the desired transistor channel length. The vertical transistor can then be completed with conventional techniques (e.g., deposition or epitaxial growth of the source/drain semiconductor  111 D, on the exposed surface of the semiconductor channel region  315 A, deposition of contact metallization, etc.). 
       FIGS. 5A-5F  illustrate plan views of single-channel structures formed as operations in the method  201  are performed, in accordance with an alternate embodiment.  FIGS. 6A-6F  illustrate cross-sectional views of the structures illustrated in  FIG. 5A-5F , in accordance with an embodiment. Generally, in the embodiment illustrated in  FIGS. 5A-5F , operations  205 - 215  are as were described in the context of  FIGS. 3A-3D  with the exception that the mask  340  is deposited on a dielectric layer  415  (e.g., Si x N y , SiON, SiO 2 , etc.) disposed over the semiconductor layer  310 . Following segregation of the co-polymers into the interior polymer region  350 A and exterior polymer region  350 B, at operation  220  the interior polymer region  350 A is removed selectively to the exterior polymer region  350 B, as is illustrated in  FIGS. 5D and 6D . In this exemplary embodiment, the mask  340  is also removed leaving an annular mask consisting of the exterior polymer region  350 B. The dielectric layer  415  is then etched to expose the underlying crystalline surface of the semiconductor material  310 . As shown in  FIG. 6E , the operation  220  further includes removing the exterior polymer region  350 B and epitaxially growing (e.g., with MOCVD, etc.) the semiconductor channel region  315 A from the exposed crystalline semiconductor surface with the dielectric layer  415  serving as a growth stopping hardmask. Given the size of the semiconductor channel region  315 A (e.g., &lt;15 nm), the grown semiconductor material layer may have advantageously good crystallinity as a result of aspect ratio trapping. After formation of the semiconductor channel region  315 A, the second portion of the dielectric layer  415  is recessed to form a cylindrical trench exposing a sidewall of the semiconductor channel region. In the exemplary embodiment depicted, the dielectric layer  415  is completely removed, exposing a surface of the semiconductor layer  310 . For one such embodiment, the semiconductor layer  310  is appropriately doped to serve as the source/drain semiconductor region of the nanowire transistor with the channel region  315 A then epitaxially grown directly a surface of the source/drain semiconductor region. 
     As shown in  FIGS. 5F and 6F , the method  201  then continues through operation  225  to form the gate dielectric on the sidewalls  380 A, over the semiconductor material layer  310  and on the sidewalls  380 B, substantially as is described elsewhere herein in reference to  FIGS. 3E and 4E . The gate electrode material  390  is then deposited at operation  230  to again surround the channel region  315 A. 
     While  FIGS. 3A-3E and 4A-4E , as well as  FIG. 5A-5F and 6A-6F , illustrate single channel embodiments of the method  201 ,  FIGS. 7A-7C  illustrate plan views of dual-channel structures formed as operations in the method  201  are performed, in accordance with an embodiment.  FIGS. 8A-8C  further illustrate cross-sectional views of the structures illustrated in  FIG. 7A-7C . Generally, the method  201  is practiced substantially as described elsewhere herein for single-channel embodiments with the DSA material defining two (or more) interior polymer regions, each of which becomes the basis for defining a semiconductor channel region of a vertical nanowire transistor. For such multi-channel embodiments, the DSA material is leveraged to self-align the channel regions to a surrounding gate and also reduce pitch between adjacent channel regions relative to the pitch employed to print the guide openings. In exemplary embodiments, the pitch of two adjacent channel regions is below the resolution limit of a scanner employed to print the guide openings. 
       FIGS. 7A and 8A  illustrate the guide opening  315  initially patterned (e.g., printed or etched) into the mask  340  (e.g., at operation  205 ) is larger in a first dimension (e.g., axis B 1 ) than in a second dimension (e.g., axis A 1 ). Generally, the longer length B 1  exceeds a threshold characteristic of the DSA material (e.g., 40 nm) while the shorter length A 1  does not (e.g., A 1  may be approximately the diameter of a guide opening for a single-channel embodiment (e.g., less than 20 nm). In embodiments, the longer length B 1  is at least twice the shorter length A 1 . For certain surface conditions, such an elongated guide opening  315 , when filled with a DSA material having proper co-polymer properties, anneals into the two interior polymer regions  350 A 1  and  350 A 2  illustrated in  FIGS. 7B and 8B . Both of the interior polymer regions  350 A 1  and  350 A 2  are surrounded by a contiguous exterior polymer region  350 B with the material properties of each segregated region being as described elsewhere herein in the context of single-channel embodiments. Upon segregation, the interior polymer regions  350 A 1  and  350 A 2  have essentially identical dimensions (e.g., CD 3  as shown in  FIG. 8C ). In the exemplary embodiments where the guide opening has at least one dimension that is less than 20 nm, the interior polymer regions  350 A 1  and  350 A 2  each have a width that is less than 15 nm, and in further such embodiments the pitch of the interior polymer regions  350 A 1  and  350 A 2  is also less than 15 nm. 
     With the plurality of interior polymer regions  350 A 1  and  350 A 2  materially distinguished from the exterior polymer region  350 B, the method  201  proceeds through operations  220 ,  225 ,  230  substantially as described for single-channel embodiments (e.g., as illustrated either by  FIGS. 3A-3E, 4A-4E ) to define the channel semiconductor layer  315  into the two channel regions  315 A 1  and  315 A 2  controlled by a shared gate electrode  390  through the gate dielectrics  350 A 1  and  350 A 2 , respectively. As such, segregation capabilities of the DSA material may be utilized to make multi-wired vertical transistors which may be individually sized for optimal gate control (reduced short channel effects) while providing a desired amount of drive current (determined by the number of discrete channels formed). 
     In embodiments, not only are the channel region and gate of a vertical transistor defined based on segregation of a DSA material, so too are other functional regions of the transistor, such as, but not limited to, the source drain regions, as illustrated by the  FIGS. 9A-9E and 10A-10G .  FIGS. 9A, 9B, 9C, 9D, and 9E  illustrate cross-sectional views of single-channel structures formed as operations in the method of  FIG. 2B  are performed, in accordance with an embodiment. Generally, in this exemplary embodiment, source/drain regions, as well as the channel region, of a vertical nanowire transistor are regrown in regions defined by segregation of a DSA material. 
       FIG. 9A  begins at the completion of operation  215  where DSA material has been segregated in the interior polymer region  350 A and exterior polymer region  350 B. The substrate in this embodiment includes a dielectric layer  925  disposed over a degenerately doped semiconductor layer  945 , that is further disposed over a crystalline semiconductor substrate layer  903 . The interior polymer region  350 A is removed selectively to the exterior polymer region  350 B, as described elsewhere herein, and also selectively to the mask  340 , as shown in  FIG. 9B . An interior trench is then etched through the dielectric layer  925  and the layer  945  in the region where the interior polymer region  350 A was removed to expose the semiconductor  903 . With the mask  340  then removed, a peripheral portion of the dielectric layer  925  is removed to leave an annular perimeter of dielectric  925  surrounding the interior trench. A selective epitaxial process is then employed to form the nanowire transistor from the seeding surface of the exposed semiconductor substrate layer  903  within the interior trench and periphery region. As shown in  FIG. 9D , a first (bottom) crystalline source/drain semiconductor layer  310  is grown from the semiconductor substrate layer  903  and from the semiconductor layer  945 . Regrowth of the source/drain semiconductor layer  310  may improve crystallinity in the channel region subsequently grown as advantageous defect trapping may occur in the source/drain semiconductor layer  310 . Furthermore, regrowth of the source/drain semiconductor layer  310  serves to selectively form a connection to the now embedded conductive semiconductor layer  945  with crystalline or polycrystalline semiconductor formed over the semiconductor layer  945 . A semiconductor channel region  315  is then epitaxially grown from the source/drain semiconductor layer  310 . A second (top) source/drain semiconductor layer  320  is further grown over the semiconductor channel region  315 . The regrown film is polished back to planarize against the dielectric layer  925  as a polish stop. Due to initial non-planarity between the interior trench and the periphery, the planarization process removes the regrown semiconductor in the periphery back to the bottom source/drain semiconductor layer  310  while the top source/drain semiconductor layer  320  is retaining in the interior region as a portion of the vertical nanowire transistor. 
     The gate dielectric is formed at operation  220  by first recessing the annular portion of the dielectric layer  925  remaining where the exterior polymer region  350 B was originally disposed. This exposes a sidewall of the semiconductor channel region  315 . The dielectric layer  925  may be completely recessed with an etch selective to the underlying conductive layer  945 , in which case the gate dielectric formed at operation  225  serves to insulate the gate electrode material  390  from the conductive layer  945 . Alternatively, the dielectric layer  925  may be recessed only partially (e.g., with a timed etch back) to increase the thickness of dielectric between the gate electrode material  390  and underlying conductive layer  945 . As such, the top surface of the vertical nanowire transistor structure illustrated in  FIG. 9E  is planarized and provides top-side access to all functional regions of the transistor for contact (e.g., silicidation) and interconnect metallization. 
       FIGS. 10A, 10B, 10C, 10D, and 10E  illustrate cross-sectional views of single-channel structures formed as operations in the method of  FIG. 2B  are performed, in accordance with an embodiment. In this exemplary embodiment, a stack of semiconductor materials including two source/drain layers and a channel layer are etched based on a DSA material. This embodiment may therefore be considered a special case of the embodiment illustrated by  FIGS. 3A-3E, 4A-4E .  FIG. 10A  begins with the DSA material segregated into the interior and exterior polymer regions  350 A,  350 B. The substrate includes a semiconductor material layer stack including compositionally distinct (through either doping or differing lattice atoms) material layers. For the exemplary embodiment, the semiconductor material stack includes a bottom source/drain layer  1010  disposed on a substrate  1003 , a channel layer  1015  disposed on the bottom source/drain layer  1010 , and a top source/drain layer  1020  disposed over the channel layer  1015 . Disposed over the semiconductor stack is a dielectric (hardmask) layer  1030 . 
     As shown in  FIG. 10B , the exterior polymer region  350 B is removed selectively to the interior polymer region  350 A and the mask  340 . An annular trench is then etched through most of the stack to expose the bottom source/drain layer  1010 , as shown in  FIG. 10C . A dielectric spacer  1040  ( FIG. 10D ) is formed along sidewalls of the semiconductor stacks and a silicide  1050  is formed on the exposed both source/drain layer  1010 . Dielectric material  1060  is then deposited within the trench, planarized, and recessed (etched back) to a z-height (thickness) sufficient to re-expose the channel region sidewall. An isotropic etch removes the dielectric spacer  1040  and the gate dielectric  380  is deposited in the trench over the recessed dielectric material  1060  an on the channel semiconductor sidewall. The gate electrode material is then deposited in the trench, planarized with a top surface of the dielectric  1030  and then recess etched to a z-height (thickness) sufficient to control the channel region. Finally, a dielectric  1070  is deposited in the trench, planarized with the top surface of the dielectric  1030 . The dielectric  1030  may then be removed selectively to the dielectric  1070  to expose the top source/drain  1020  in preparation for contact metallization. Hence, the vertically-oriented nanowire transistor with sub-lithographic wire dimensions (e.g., &lt;15 nm) are self-alignedly fabricated, along with local interconnects, on the basis of a single lithographic mask and DSA material. 
       FIG. 11  is a functional block diagram of a SOC implementation of a mobile computing platform, in accordance with an embodiment of the present invention. The mobile computing platform  1100  may be any portable device configured for each of electronic data display, electronic data processing, and wireless electronic data transmission. For example, mobile computing platform  1100  may be any of a tablet, a smart phone, laptop computer, etc. and includes a display screen  1105 , the SOC  1110 , and a battery  1115 . As illustrated, the greater the level of integration of the SOC  1110 , the more of the form factor within the mobile computing device  1100  that may be occupied by the battery  1115  for longest operative lifetimes between charging, or occupied by memory (not depicted), such as a solid state drive, DRAM, etc., for greatest platform functionality. 
     The SOC  1110  is further illustrated in the expanded view  1120 . Depending on the embodiment, the SOC  1110  includes a portion of a silicon substrate  1160  (i.e., a chip) upon which one or more of a power management integrated circuit (PMIC)  1115 , RF integrated circuit (RFIC)  1125  including an RF transmitter and/or receiver, a controller thereof  1111 , and one or more central processor core, or memory  1177 . In embodiments, the SOC  1110  includes one or more vertical nanowire transistors (FETs) in conformance with one or more of the embodiments described herein. In further embodiments, manufacture of the SOC  1110  includes one or more of the methods described herein for fabricating a vertically-oriented nanowire transistor (FET). 
       FIG. 12  is a functional block diagram of a computing device  1200  in accordance with one embodiment of the invention. The computing device  1200  may be found inside the platform  1100 , for example, and further includes a board  1202  hosting a number of components, such as but not limited to a processor  1204  (e.g., an applications processor) and at least one communication chip  1206 . In embodiments, at least the processor  1204  includes a vertical nanowire transistor (FET) having structures in accordance with embodiments describe elsewhere herein, and/or fabricated in accordance with embodiments further described elsewhere herein. The processor  1204  is physically and electrically coupled to the board  1202 . The processor  1204  includes an integrated circuit die packaged within the processor  1204 . The term “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. 
     In some implementations the at least one communication chip  1206  is also physically and electrically coupled to the board  1202 . In further implementations, the communication chip  1206  is part of the processor  1204 . Depending on its applications, computing device  1200  may include other components that may or may not be physically and electrically coupled to the board  1202 . These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., RAM or ROM) in the form of flash memory or STTM, etc., a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, touchscreen display, touchscreen controller, battery, audio codec, video codec, power amplifier, global positioning system (GPS) device, compass, accelerometer, gyroscope, speaker, camera, and mass storage device (such as hard disk drive, solid state drive (SSD), compact disk (CD), and so forth). 
     At least one of the communication chips  1206  enables wireless communications for the transfer of data to and from the computing device  1200 . The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip  1206  may implement any of a number of wireless standards or protocols, including but not limited to those described elsewhere herein. The computing device  1200  may include a plurality of communication chips  1206 . For instance, a first communication chip  1206  may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip  1206  may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others. 
     It is to be understood that the above description is intended to be illustrative, and not restrictive. For example, while flow diagrams in the figures show a particular order of operations performed by certain embodiments of the invention, it should be understood that such order is not required (e.g., alternative embodiments may perform the operations in a different order, combine certain operations, overlap certain operations, etc.). Furthermore, many other embodiments will be apparent to those of skill in the art upon reading and understanding the above description. Although the present invention has been described with reference to specific exemplary embodiments, it will be recognized that the invention is not limited to the embodiments described, but can be practiced with modification and alteration within the spirit and scope of the appended claims. The scope of the invention should, therefore, be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.