Patent Publication Number: US-9425303-B1

Title: Controlling current or mitigating electromagnetic or radiation interference effects using multiple and different semi-conductive channel regions generating structures

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     The present application claims priority to U.S. Provisional Patent Application Ser. No. 62/116,129, filed Feb. 13, 2015, entitled “SYSTEMS AND METHODS FOR CONTROLLING CURRENT OR MITIGATING ELECTROMAGNETIC OR RADIATION INTERFERENCE EFFECTS USING MULTIPLE AND DIFFERENT SEMI-CONDUCTIVE CHANNEL REGIONS GENERATING STRUCTURES FORMED BY MULTIPLE DIFFERENT SEMI-CONDUCTIVE ELECTRICAL CURRENT OR VOLTAGE CONTROL STRUCTURES,” the disclosure of which is expressly incorporated by reference herein. 
    
    
     STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT 
     The invention described herein was made in the performance of official duties by employees of the Department of the Navy and may be manufactured, used and licensed by or for the United States Government for any governmental purpose without payment of any royalties thereon. This invention (Navy Case 200,100) is assigned to the United States Government and is available for licensing for commercial purposes. Licensing and technical inquiries may be directed to the Technology Transfer Office, Naval Surface Warfare Center Crane, email: Cran_CTO@navy.mil. 
    
    
     BACKGROUND AND SUMMARY OF THE INVENTION 
     Vertical Double-Diffused Metal Oxide Field Effect Transistors (VDMOSFETs) are used because of their high-current, high-voltage capabilities.  FIGS. 1 a  and 1 b    respectively represent simplified cross-sectional views of a basic design/layout of N-channel and P-Channel VDMOSFETs  1 ,  3 , respectively (a structure is cut parallel to sources along a metal oxide semiconductor (MOS) gate—cut lines are shown as AB in  FIGS. 2 a  and 2 b   ). A VDMOSFET  1  as shown is made of a doped substrate (e.g., N-channel devices use N+ substrates  104 ; whereas,  FIG. 1 b    shows a P-channel device using P+ substrates  113 ). A conductive layer contacting bottom of a substrate  104  (for N-channel) or substrate  113  (for P-channel) forms a drain contact  102 . At top of substrate  104  or  113  is a lighter-doped epitaxial layer (N-channel devices use N-type silicon  103 ; referring to  FIG. 1 b   , P-channel devices use P-type silicon  112 ). In an alternative embodiment (not shown), a second epitaxial layer (referred to as a buffer layer in this example) can be added between layers  103  and  104  (for N-channel) to enhance single-event burnout (SEB) performance. At a surface of the exemplary epitaxial layer  103 , a region of opposite doping  105 ,  105 ′ is implanted/diffused to form a doped region (hereinafter referred to as body) (e.g., N-channel devices use P-type doping (P-body)  105 ,  105 ′ and P-channel devices use N-type doping (N-body)  114 ,  114 ′). To ensure good contact between source contact and body, e.g.,  101  and  105 , a higher doped region, e.g.,  106 , can be implanted/diffused into the exemplary body (e.g., N-channel device use a higher doped P region  106 ,  106 ′ and P-channel devices use a higher doped N region  115 ,  115 ′). Once doped regions, e.g., various bodies (e.g., P-body  105 ,  105 ′ or N-body  115 ,  115 ′) are manufactured, an opposite doping of exemplary body region (e.g., N-body  107 ,  107 ′, P-body  116 ,  116 ′) can be implanted/diffused to define source regions (e.g., N-channel devices use N-type doping (e.g., N-body)  107  and P-channel devices use P-type doping (P-body)  116 ). A source contact conductive layer  101  (or  FIG. 1 b   ,  101 ′) can be deposited connecting source and body regions (e.g., P-body  106 /N-body  107  or N-body  115 /P-body  116 ) forming a portion of an electrical conductive path (shown as one segment of dashed lines through these areas) for an electrical power supply (not shown). A dielectric material (e.g., a gate oxide  108 ) can be placed on top of epitaxial region (N type silicon  103 ) and over/between N source  107  and N source  107 ′. In  FIG. 1 a   , MOS gate  109  is formed with a conductive layer placed on top of gate oxide  108 . A portion of P-Body  105 ,  105 ′ ( FIG. 1 a   ) respectively between N-Source  107  or  107 ′ and N Type Silicon epitaxial layer  103  respectively defines semi-conductive channel regions  111 ,  111 ′. Referring to  FIG. 1 b   , a portion of N-Body  114 ,  114 ′ respectively between P-Source  116  or  116 ′ and the P Type Silicon epitaxial layer  112  respectively defines semi-conductive channel regions  111 ″,  111 ′″. Dashed lines show electrical conductive paths that are formed during operation of  FIGS. 1 a  and 1 b    VDMOSFETs. 
     Attempts have been made, including numerous modifications/improvements in the design, layout, and fabrication of vertical power metal oxide semiconductor field effect transistors (MOSFETs) to enhance their electrical and radiation performance (e.g., increase power density, decrease on-resistance, increase radiation hardness, etc.). For example, radiation-tolerant power, MOSFETs were first introduced to address requirements of various military and space applications. Since then, numerous radiation issues have been discovered and significant research has been devoted to resolving specific radiation issues (e.g., total ionizing dose (TID), single-event gate rupture (SEGR), and SEB issues). 
     Under some types of MOSFET operation, application of an appropriate gate voltage (a gate voltage greater than the device&#39;s gate threshold voltage) forms a conducting path between source and drain allowing current to flow (device is turned on). Higher gate voltages equates to higher current flow. One effect of TID is to trap charge in gate oxide, which causes MOS gate threshold voltage to shift (e.g., gate voltage required to turn on the device can change with TID). If this TID-induced shift is sufficiently large, n-channel devices cannot be turned off and become non-functional. When threshold voltage of re-channel device shifts below zero volts and becomes negative (e.g., n-channel devices have positive threshold voltages), that device is said to have failed by going into depletion mode. An exemplary MOS gate threshold voltage shift of p-channel devices has an opposite effect. P-channel devices become impossible to turn-on without applying an excessive gate voltage that can damage device. Methods have been attempted to help resolve TID issues in power MOSFETs. One method seeks to decrease gate oxide thickness (e.g., a thinner gate oxide traps less charge but makes device more susceptible to SEGR). Another method seeks to ensure high quality of final gate oxide by manufacturing radiation-hardened gate oxides but these rad-hard oxides can be expensive and exhibit variability in radiation hardness from processing lot to processing lot. Another method seeks to apply higher gate voltages to turn-on or turn-off the device but threshold voltages can shift beyond a safe operating voltage; higher gate voltages can also make devices more susceptible to SEGR. 
       FIGS. 3 a  and 3 b    represent a simplified cross sectional view of a basic design/layout of N-channel and P-Channel Junction Field Effect Transistors (JFETs), respectively (the exemplary structure is cut parallel to the drain and source and along the JFET gate). Unlike MOSFETs, the JFETs use a reverse biased P-N junction to control current flow by modulating the depletion layer width. The JFET consists of a doped semiconductor layer (N-Channel JFETs use N-Type Substrates  122 ; whereas, P-Channel JFETs use P-Type Substrates  123 ). A conductive layer can be deposited onto opposite ends of substrate forming the drain contact  120  and source contact  121  of the JFET. Toward a middle of  122  or  123 , a region is implanted/diffused with opposite doping of the substrate (N-Channel JFET uses a P-type Silicon  117 ; whereas, P-Channel JFETs use N-Type Silicon  119 ) forming the PN junction. A conductive layer is deposited onto these opposite doped regions to form the gate contact  118 . 
     Unlike MOSFETs, JFETs exhibit a natural hardness to TID radiation. TID issues in MOSFETs are directly related to trapped charge in gate oxide used to modulate conductive channel; whereas, JFETs do not use dielectric materials to form a conductive channel making it naturally hard to TID. 
     Power MOSFETs subjected to space-like environments or other particle-enriched environments are prone to SEGR and SEB, which can adversely affect the device&#39;s performance and may even cause system failure. For SEB, a main area of concern is the interaction of a charged particle with the inherent parasitic bipolar transistor where the source acts like an emitter, the body acts like a base and the drain acts like a collector (e.g., see  FIG. 4 ). For SEGR, the main area of concern is the interaction of a charged particle strike within neck region defined by the epitaxial region under the gate oxide between adjacent body regions (e.g., see  FIG. 4 ). When a charge particle traverses a semiconductor material, it sheds energy in accordance with its linear energy transfer (LET) function for that material and that energy can create electron-hole pairs along particle&#39;s path. In presence of an electric field, these electron-hole pairs can separate producing unwanted current flow. A resultant current flow under certain conditions can lead to SEB or SEGR. SEB can occur if this current flow is sufficient to locally turn on the parasitic bipolar transistor which if not interrupted may lead to thermal runaway (device fails catastrophically). SEB mechanisms can be more complex than presented here but the intent is to only provide a cursory explanation of SEB. SEGR can occur if this current flow disrupts the depletion field in the epitaxial layer under the gate and couples a portion of the drain potential across the gate dielectric sufficient to damage gate dielectric (e.g., see  FIG. 5 ). SEGR mechanisms can be more complex than presented here but the intent is to only provide a cursory explanation of SEGR. 
     Some high-voltage applications involving RF mixers, amplifiers, gain control, and detectors may employ two devices to perform the intended application. If an electrical circuit uses two devices to accomplish the intended application, there can be added costs, more space, and added weight when compared to a single device option. 
     One exemplary embodiment of the invention, such as a planar Dual-Gate Vertical Double-Diffused Metal Oxide Semiconductor Field Effect Transistor (DGVDMOSFET), can be a layout/design of an innovative structure integrating and combining aspects of improved VDMOSFETs and operational gates of JFETs. Therefore, an exemplary improved DGVDMOSFET has advantages of both VDMOSFETs and JFETs creating an exemplary innovative new device and related methods thereof: the DGVDMOSFET. Presently, dual-gate MOSFETs can be built by packaging two MOSFETs into a hybrid-type package with two MOSFETs placed in series but this implementation does not address radiation issues and increases overall cost, weight and size. Another implementation can be to fabricate two lateral MOSFETs in series using a monolithic type layout. However, use of lateral MOSFETs can limit a drain-to-source blocking voltages of such devices to applications that are typically less than 100V due to surface area considerations (blocking voltage is basically determined by the lateral spacing between drain and source and doping) and does not address radiation issues. Drain-to-source blocking voltage of the VDMOS can be determined by the epitaxial layer thickness and doping; therefore, an exemplary DGVDMOSFET can be fabricated for blocking voltages that exceed 1000V providing a new device for high-voltage applications. This exemplary device can be useful in RF type applications such as mixers, gain control, amplifiers, and detectors. 
     Exemplary embodiments of the invention, e.g., DGVDMOSFET, can also enhance operational performance in radiation environments, specifically SEB, SEGR, and TID environments. Existing power VDMOSFETs can be prone to catastrophic failure from SEB and SEGR, if operated in radiation environments where particles such as neutrons, protons, and heavy ions are present. An exemplary DGVDMOSFET structure can provide an enhanced barrier (e.g., enhanced depletion region) to reduce interactions of radiation particles with exemplary embodiments of the invention from suffering from SEB and SEGR conditions. Existing power VDMOSFETs can also be prone to TID-induced threshold voltage (VTH) shifts from ionizing radiation environments, which can lead to device failure in their intended application. An exemplary embodiment&#39;s independent JFET gate can provide a radiation hardened by design (RHBD) approach to reduce TID effects providing enhanced operational performance beyond an operational failure point of VDMOSFETs (e.g., an exemplary improved JFET gate can allow the exemplary structure to be turned off even after the MOS gate becomes non-functional from TID-induced threshold voltage shifts). 
       FIG. 6  provides one simplistic application of a dual gate transistor e.g., DGVDMOSFET  200  or  200 ′, used in a RF mixer circuit. Dual gate transistors can be useful in many types of RF applications. 
     Additional features and advantages of the present invention will become apparent to those skilled in the art upon consideration of the following detailed description of the illustrative embodiment(s) exemplifying some best modes of carrying out the invention as presently perceived. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The detailed description of the drawings particularly refers to the accompanying figures in which: 
         FIG. 1 a    shows a simplified cross sectional side view of a N-channel VDMOSFET; 
         FIG. 1 b    shows a simplified cross sectional side view of a P-channel VDMOSFET; 
         FIG. 2 a    shows a simplified top view of the  FIG. 1 a    N-channel VDMOSFET; 
         FIG. 2 b    shows a simplified top view of the  FIG. 1 b    P-channel VDMOSFET; 
         FIG. 3 a    shows a simplified cross sectional view of a N-channel JFET; 
         FIG. 3 b    shows a simplified cross sectional view of a P-channel JFET; 
         FIG. 4  shows a simplified three-dimensional cross-sectional view of the  FIG. 1 a    N-channel VDMOSFET showing parasitic bipolar and neck region; 
         FIG. 5  shows a simplified pictorial evolution of SEGR stages of a simplified N-channel VDMOSFET such as shown in  FIG. 1   a;    
         FIG. 6  shows a simplified dual gate transistor used in an exemplary RF mixer application; 
         FIG. 7 a    shows a simplified cross sectional view of an exemplary N-channel DGVDMOSFET in accordance with one embodiment of the invention; 
         FIG. 7 b    shows a simplified cross sectional view of an exemplary P-channel DGVDMOSFET in accordance with one embodiment of the invention; 
         FIG. 8 a    shows a simplified cross sectional side view of an exemplary N-channel DGVDMOSFET in accordance with one embodiment of the invention; 
         FIG. 8 b    shows a simplified cross sectional side view of an exemplary P-channel DGVDMOSFET in accordance with one embodiment of the invention; 
         FIG. 8 c    shows a simplified schematic of N-channel DGVDMOSFET in accordance with one embodiment of the invention; 
         FIG. 8 d    shows a simplified schematic P-channel DGVDMOSFET in accordance with one embodiment of the invention; 
         FIG. 9 a    shows one exemplary application (Standard DC Mode Configuration) of an exemplary DGVDMOSFET in accordance with one embodiment of the invention; 
         FIG. 9 b    shows one exemplary result or output (Standard DC Mode (I-V) response) from the  FIG. 9 a    exemplary application in accordance with one embodiment of the invention; 
         FIG. 10 a    shows another exemplary application (Enhanced DC Mode Configuration) of an exemplary DGVDMOSFET in accordance with one embodiment of the invention; 
         FIG. 10 b    shows one exemplary result or output (enhanced DC mode (I-V) response) associated with the  FIG. 10 a    exemplary Enhanced DC Mode configuration associated with one element (e.g., MOS Gate  209  Control) of the exemplary  FIG. 10 a    DGVDMOSFET exemplary application; 
         FIG. 10 c    shows one exemplary result or output (enhanced DC mode (I-V) response) associated with the  FIG. 10 a    exemplary Enhanced DC Mode configuration associated with another element (e.g., JFET  195  Control) of the exemplary  FIG. 10 a    DGVDMOSFET exemplary application; 
         FIG. 11 a    shows another exemplary application (Dual gate AC Mode Configuration) of an exemplary DGVDMOSFET in accordance with one embodiment of the invention; 
         FIG. 11 b    shows one exemplary result or output (dual gate AC mode response e.g., a simplistic mixer output) from the  FIG. 11 a    exemplary application; 
         FIG. 12  shows exemplary methods of operation of exemplary embodiments of the invention comprising various modes of operation; 
         FIG. 13  shows another exemplary method of operation of an exemplary embodiment of the invention comprising another mode of operation; 
         FIGS. 14 a -14 c    show another exemplary method of operation of an exemplary embodiment of the invention comprising another mode of operation; 
         FIGS. 15 a -15 b    show another exemplary method of operation of an exemplary embodiment of the invention comprising another mode of operation; 
         FIGS. 16 a -16 c    show another exemplary method of operation of an exemplary embodiment of the invention comprising another mode of operation; 
         FIGS. 17 a -17 c    show another exemplary method of operation of an exemplary embodiment of the invention comprising another mode of operation; 
         FIGS. 18 a -18 b    show another exemplary method of operation of an exemplary embodiment of the invention comprising another mode of operation; 
         FIG. 19  shows an exemplary system application (linear voltage regulator) of an exemplary DGVDMOSFET in accordance with one embodiment of the invention; 
         FIG. 20  shows another exemplary system application (switching voltage regulator) of an exemplary DGVDMOSFET in accordance with one embodiment of the invention; 
         FIG. 21  shows another exemplary system application (RF amplifier) of an exemplary DGVDMOSFET in accordance with one embodiment of the invention; and 
         FIG. 22  shows another exemplary system application (RF Mixer) of an exemplary DGVDMOSFET in accordance with one embodiment of the invention. 
     
    
    
     DETAILED DESCRIPTION OF THE DRAWINGS 
     The embodiments of the invention described herein are not intended to be exhaustive or to limit the invention to precise forms disclosed. Rather, the embodiments selected for description have been chosen to enable one skilled in the art to practice the invention. 
     One exemplary embodiment of the invention describes a design/layout of an innovative device, a DGVDMOSFET, which allows dual gate control of a modified VDMOSFET to be fabricated into a monolithic device (integrate improved elements and functions within a combined VDMOSFET and JFET). An exemplary DGVDMOSFET has dual independent gates to control current between drain and source. An embodiment includes an exemplary basic fabrication steps (design/layout) of an exemplary DGVDMOSFET incorporating aspects of improvements to a planar VDMOSFET. 
       FIGS. 7 a  and 7 b    represents simplified top-views of cutaway cross-sectional views of two exemplary DGVDMOSFETs  200  (N-channel version),  200 ′ (P-channel version) that includes a JFET structure, e.g.,  211 ,  217 , and  218  ( FIG. 7 a   ) or  211 ′,  219 ,  220  ( FIG. 7 b   ). The DGVDMOSFET (e.g.,  200 ,  200 ′) design/layout can be fabricated using stripe; rectangular; hexagonal; and other commonly used cell layout schemes. The  FIGS. 7 a , 7 b    views are simplified cutaways showing a lateral slice view of these devices versus a three-dimensional view of a device shown in  FIG. 4 . Many cells (e.g., DGVDMOSFET  200  and/or  200 ′) can be integrated in parallel providing different current and on-resistance capabilities depending upon number of cells integrated together. 
       FIG. 7 a    includes a N-Type Silicon ( 203 ) epitaxial layer formed with a MOSFET structure section having a first and second portions  191 ,  193  (comprising  209 / 201 / 205 / 207  and  209 / 201 ,  205 / 207 ) with the JFET  195  (comprising  211 ,  217 ,  218 ) formed between the two MOSFET structure portions  191 ,  193 . The first MOSFET portion  191  includes a MOS Gate  209  disposed with one section over a P-Body  205  and an N+ Type Source section  207  where a Source Contact  201  is disposed within the N+ Type Source section  207 . The N+ Type Source section  207  is disposed within the P-body  205  section. The second MOSFET portion  193  includes a section of MOS Gate  209  (in this example MOS Gate  209 s are coupled in a three-dimensional structure connecting them which are not shown due to the cutaway nature of this view) which is disposed with one section over the P-Body  205  and the N+ Type Source section  207  where the Source Contact  201  is disposed within the N+ Type Source section  207 . The N+ Type Source section  207  is disposed within the P-body  205  section (in this example both P-bodies  205 / 205 , Source Contacts  201 , and N+ Type Sources  207  are coupled in a three-dimensional structure connecting them which is not shown due to the cutaway nature of this view). The first and second MOSFET structure portions  191 ,  193  and the JFET  195  section are disposed within an N-Type Silicon epitaxial layer  203 . 
       FIG. 7 b    includes a P-Type Silicon ( 212 ) epitaxial layer formed with a MOSFET structure section having a first and second portions  197 ,  199  (comprising  209 ′/ 201 ′/ 214 / 216  and  209 ′/ 201 ′/ 214 / 216 ) with the JFET  198  (comprising  211 ′,  219 ,  220 ) formed between the two MOSFET structure portions  197 ,  199 . Both  FIGS. 7 a  and 7 b    have a cut line (A-B) representing a vertical cut line which defines respective views in  FIGS. 8 a  and 8 b   . The first MOSFET portion  197  includes a section of a MOS Gate  209 ′ disposed with one section over a N-body  214  and an P+ Type Source section  216  where a Source Contact  201 ′ is disposed within the P+ Type Source section  216 . The P+ Type Source section  216  is disposed within the N-Body  214  section. The second MOSFET portion  199  includes the MOS Gate  209 ′ section (in this example both MOS Gate  209 ′ sections are coupled in a three-dimensional structure which is not shown connecting them due to the cutaway of this view) which is disposed with one section over the N-Body  214  and the P+ Type Source section  216  where the Source Contact  201 ′ is disposed within the P+ Type Source section  216 . The P+ Type Source section  216  is disposed within the N-body  214  section. In this example, N-bodies  214 / 214 , Source Contacts  201 ′, and P+ Type Sources  216  are coupled in a three-dimensional structure which is not shown connecting them due to the cutaway nature of this view. The first and second MOSFET structure portions  197 ,  199  and the JFET  198  section are disposed within a P-Type Silicon epitaxial layer  212 . In this exemplary embodiment, the JFET section  198  is disposed within the P Type epitaxial layer  212  such that it decouples the MOSFET section  197 ,  199  on either side of it and is disposed so that the JFET section&#39;s  198  outer boundary is in proximity to an outer boundary section of one side of both MOSFET sections  197 ,  199  on either side of the JFET section  198 . 
       FIG. 8 a    shows a simplified side cross-sectional view of the exemplary  FIG. 7 a    N-channel DGVDMOSFET along  FIG. 7 a    A-B cut lines in accordance with one embodiment of the invention.  FIG. 8 a    adds elements to the  FIG. 7 a    structure that cannot be seen in the top cross-sectional cutaway view. For example,  FIG. 8 a    shows two Gate Oxide  208  sections respectively disposed between both MOS Gate Contact  209  sections and N+ Type Source  207 /P-Body  205  sections/N Type epitaxial layer  203 . Two categories of semi-conductive channel regions (SCR) are shown  123 ,  125 . A First Type SCR  123  is created as a result of design of the MOSFET sections  191 ,  193 —for example, SCR  123  can be a region in lateral proximity to the N+Source Type  207  that is underneath a portion of Gate Oxide area  208  and a section of P-Body  205  that is underneath a portion of Gate Oxide  208  that is next to a boundary section of N Type epitaxial layer  203 . A Second Type SCR  125  is formed in another region  125 , e.g., underneath a section of Gate Oxide  208  and disposed between P-Body  205  and a section of JFET  195 , e.g., P-Body  217  that forms a lower section of the JFET  195  section. A JFET Gate Contact  211  is shown in contact with P Type Body  218  which is in turn surrounded at least in part by P Type layer  217 . In this example, dashed grey-lines  194  are shown which exemplify production of an electrical field effect created by JFET section  195  when it is biased with an electrical power supply. Two sets of black dashed lines  192 ,  192 ′ show two separate exemplary electrical paths that are controlled by the MOSFET sections  191 ,  193 . In this example, there are two First Type SCRs  123  formed at a boundary section of both MOSFET sections in proximity to the N Type epitaxial layer  203 . In this example, there are two Second Type SCRs  125  formed as a result of the  FIG. 7 a   / 8   a  design on either side of the JFET section  195  and between the two MOSFET sections  191 ,  193 . In this embodiment, the First Type SCRs  123  respectively regulates current through the MOSFET sections  191 ,  193 . The Second Type SCRs  125  perform a second current regulation function associated with electrical signals passing through the MOSFET by opening or closing a semi-conductive path in a section of the N-Type epitaxial layer  203 . These dual SCR regions ( 123 / 125 ) provides two independent gate type functions or capabilities that are useful for mixing signals as well as providing benefits from a radiation hardening or performance perspective. The MOSFET  191 ,  193  sections are sensitive to radiation degradation which can be compensated for or eliminated by use of the Second Type SCR  125  by means of the electrical field effect  194  passing through the epitaxial layer  203  which reduces or cuts off electrical flow path  192 / 192 ′. Various negative effects can be mitigated or eliminated by embodiments of this invention such as TID, SEB, and SEGR. As an example, TID effects can cause the First Type SCR  123  to be permanently turned on; however, TID effects do not fully or partially affect the Second Type SCR  125 . Also, radiation induced currents can cause failure of the MOSFET sections  191 ,  193 ; an addition of the JFET structure  195  reduces radiation induced current through these MOSFET sections  191 ,  193  facilitating increased radiation tolerance. Additional elements shown in  FIG. 8 a    include N Type substrate  204  disposed beneath the N Type epitaxial layer  203  as well as a drain contact  202  disposed beneath the N Type substrate  204 . 
       FIG. 8 b    shows a simplified side cross sectional view of the exemplary  FIG. 7 b    P-channel DGVDMOSFET along  FIG. 7 b    A-B cut lines in accordance with one embodiment of the invention.  FIG. 8 b    adds elements to the  FIG. 7 b    structure that cannot be seen in the top cross-sectional cutaway view. The  FIG. 8 b    structure differs from the  FIG. 8 a    design in that references to N type silicon becomes P-type silicon references and references to P type silicon become N-type references. Different elements numbers are also used for elements which are different in structure or material composition to the  FIG. 8 a    design. References to the first and second MOSFET sections  197 ,  199  differ as well as JFET section  198 . 
     For example,  FIG. 8 b    shows two Gate Oxide  208 ′ sections respectively disposed between both MOS Gate Contact  209 ′ sections and P+ Type Source  216 /N-body  214  sections/P-Type epitaxial layer  212 . Two categories of semi-conductive channel regions are shown  123 ,  125  which perform a same or similar function as the  FIG. 8 a    structure&#39;s SCRs. A First Type SCR  123  is created as a result of design of the MOSFET sections  197 ,  199 —for example, SCR  123  can be a region in lateral proximity to the P+Source  216 , that can be formed underneath a portion of Gate Oxide area  208 ′ and a section of N-Body  214  which is underneath a portion of Gate Oxide  208 ′ that is next to a boundary section of P Type epitaxial layer  212 . A Second Type SCR  125  is formed in another region, e.g., underneath a section of Gate Oxide  208 ′ and disposed between N-Body  214  and a section of JFET  198 , e.g., N-Body  219  that forms a lower section of the JFET  198  section. A JFET Gate Contact  211 ′ is shown in contact with N Type Body  220  which is in turn surrounded at least in part by N body  219 . In this example, dashed grey-lines  194  are shown which exemplify production of an electrical field effect created by the JFET section  198  when it is biased with an electrical power supply (not shown). Two sets of black dashed lines  192 ,  192 ′ shows two separate exemplary electrical path that is controlled by the MOSFET sections  197 ,  199 . In this example, there are two First Type SCRs  123  formed at a boundary section of both MOSFET sections  197 ,  199  in proximity to the P Type epitaxial layer  212 . In this example, there are two Second Type SCRs  125  formed as a result of the  FIG. 7 b   / 8   b  design on either side of the JFET section  198  and between the two MOSFET sections  197 ,  199 . In this embodiment, the First Type SCRs  123  respectively regulates current through the MOSFET sections  197 ,  199 . The Second Type SCRs  125  perform a second current regulation function associated with electrical signals passing through the MOSFETs  197 ,  199  by opening or closing a semi-conductive path in a section of the P-Type epitaxial layer  212 . These dual SCR regions ( 123 / 125 ) provides two independent gate type functions or capabilities which are useful for mixing signals as well as providing benefits from a radiation hardening or performance perspective. The MOSFET  197 ,  199  sections are sensitive to radiation degradation which can be compensated for or eliminated by use of the Second Type SCR  125  by means of the electrical field effect  194  passing through the P type epitaxial layer  212  which selectively reduces or cuts off electrical flow path  192 / 192 ′. Various negative effects can be mitigated or eliminated by embodiments of this invention such as TID, SEB, and SEGR. As an example, TID effects can cause the First Type SCR  123  can be permanently turned on; however, TID effects do not fully or partially affect the Second Type SCR  125 . Also, radiation induced currents can cause failure of the MOSFET sections  197 ,  199 ; an addition of the JFET structure  198  reduces radiation induced current through these MOSFET sections  197 ,  199  facilitating increased radiation tolerance. Additional elements shown in  FIG. 8 b    include P Type substrate  213  disposed beneath the P Type epitaxial layer  212  as well as a drain contact  202 ′ disposed beneath the P Type substrate  213 . 
     A control and sensor system could also be provided for (not shown) which would operate embodiments such as the  FIG. 7 a   / 8   a  (and/or  7   b / 8   b ) MOSFET  191 ,  193  (or  197 ,  199 ) and the JFET  195  (or  198 ) in response to detected radiation fields or energy. For example, a control section can have a pulse width modulator (not shown) which would operate the MOSFET sections  191 ,  193  (or  197 ,  199 ) and JFET  195  (or  198 ) in order to reduce or adjust radiation-induced currents or other aspects of operation of this system. A look up table can be utilized by the control section (not shown) which can correlate operation of the MOSFET sections  191 ,  193  (or  197 ,  199 ) and the JFET section  195  (or  198 ) which in turn generates effects in the First and/or Second Type SCRs  123 ,  125  to increase radiation hardening as well as facilitate additional modulation schemes performed by an embodiment of the invention. 
       FIG. 8 c    shows a simplified schematic of N-channel DGVDMOSFET in accordance with one embodiment of the invention. The  FIG. 8 c    drawing shows an example of a symbolic representation of the  FIG. 7 a   / 8   a  embodiment that show a combination of the two MOSFET sections  191 ,  193  as well as the JFET section  195  as well as input/outputs such as MOS Gate  209 , JFET Gate Contact  211 , Source  201 , and Drain  202 . Additional elements that are optional include two diodes (e.g., parasitic element diodes) that respectively couple drain  202  to source  201 ; the other diode couples between drain  202  and JFET gate terminal  211 . 
       FIG. 8 d    shows a simplified schematic of P-channel DGVDMOSFET in accordance with one embodiment of the invention. The  FIG. 8 d    drawing shows an example of a symbolic representation of the  FIG. 7 b   / 8   b  embodiment that show a combination of the two MOSFET sections  197 ,  199  as well as the JFET section  198  as well as input/outputs such as MOS Gate  209 ′, JFET Gate Contact  211 ′, Source  201 ″, and Drain  202 ′. Additional elements that are optional include two diodes (e.g., parasitic element diodes) that respectively couple drain  202 ′ to source  201 ; the other diode couples between drain  202 ′ and JFET gate terminal  211 ′. 
       FIG. 9 a    shows one exemplary application (Standard DC Mode Configuration) of exemplary DGVDMOSFET symbol shown in  FIG. 8 c    in accordance with one embodiment of the invention.  FIG. 9 a    schematic shows an external gate circuit (e.g., power supply (VG  241 )) and an external drain circuit (e.g., power supply (VD  243 )) coupled to DGVDMOSFET embodiment  200 . Referring back to  FIGS. 7 a   / 8   a  in view of  FIGS. 9 a   / 9   b , if JFET gate contact  211  is connected directly to the source contact  201 , one embodiment of the DGVDMOSFET  200  can be configured to function similar to a standard VDMOSFET providing similar electrical characteristics and performance of standard VDMOSFET; however, an exemplary embodiment DGVDMOSFET  200  may exhibit higher on-resistance and lower power density.  FIG. 9 b    shows an example of five exemplary standard DC mode I-V responses or outputs (I-V responses  233 ,  235 ,  236 ,  237  and  239 ) of  FIG. 9 a    exemplary application (Standard DC Mode configuration) in accordance with one embodiment of the invention.  FIG. 9 b    also presents three regions of exemplary operation (cut-off  233 , linear  231 , and saturation  232 ). Cut-off  233  can be operable in  FIG. 9 a    exemplary application if power supply VG  241  delivers a voltage less than MOS&#39;s gate threshold voltage (Vth_MOS) to effect a reduction or elimination of DGVDMOSFET&#39;s current flow through MOS&#39;s semi-conductive channel region  123 . Linear  231  can be operable in  FIG. 9 a    exemplary application if power supply VG  241  delivers a voltage greater than MOS&#39;s gate threshold voltage (Vth_MOS) to enter a resistive DGVDMOSFET current flow through MOS&#39;s semi-conductive channel region  123 , where power supply VD  243  delivers a voltage less than the difference of VG  241  and Vth_MOS. Saturation  232  can be operable in  FIG. 9 a    exemplary application if power supply VG  241  delivers a voltage greater than MOS&#39;s gate threshold voltage (Vth_MOS) to enter saturated DGVDMOSFET current flow (saturation) through MOS&#39;s semi-conductive channel region  123 , where power supply VD  243  delivers a voltage greater than the difference of VG  241  and Vth_MOS.  FIG. 9 b    does not necessarily represent an actual DGVDMOSFET&#39;s I-V response but is only provided to show how one embodiment of an exemplary DGVDMOSFET would operate in a standard DC mode configuration. Operation of an exemplary DGVDMOSFET in a standard DC mode configuration may not enhance TID performance but may provide higher SEB and SEGR performance. 
       FIG. 10 a    shows another exemplary application (Enhanced DC mode configuration) of exemplary DGVDMOSFET  200  symbol shown in  FIG. 8 c    in accordance with one embodiment of the invention.  FIG. 10 a    schematic shows a MOS gate power supply (VG  253 ), a JFET gate power supply (VG 2   251 ), and a drain power supply (VD  255 ) coupled to the DGVDMOSFET embodiment  200 . In this exemplary configuration, the MOSFET gate  191 , 193  and the JFET gate  195  can be used separately or together to assist in controlling DGVDMOSFET&#39;s current flow. The exemplary DGVDMOSFET  200  can be configured to function similar to a standard VDMOSFET (e.g., VG 2   251  voltage can be set to zero or other fixed voltage) providing similar electrical and performance of a standard VDMOSFET; can be configured to function similar to a standard JFET (e.g., VG  253  voltage can be greater than the MOS&#39;s threshold voltage) providing similar electrical and performance of a standard JFET; or can be configured to function similar to JFET connected in series to VDMOSFET (e.g., VG  253  and VG 2   251  voltages can be used to control current flow) providing similar electrical and performance of a series connection. The exemplary embodiment DGVDMOSFET  200  may exhibit higher on-resistance and lower power density compared to either a standard VDMOSFET or JFET but the exemplary DGVDMOSFET&#39;s die area is comparable to either a standard VDMOSFET&#39;s or JFET&#39;s die area (e.g., of comparable voltage and current capabilities). In this exemplary configuration, the exemplary DGVDMOSFET  200  offers enhanced operational and performance capabilities with respect to TID, SEB, and SEGR. Enhanced TID performance can occur because the exemplary JFET gate  195  can continue to function even after high levels of TID exposure (e.g., TID&gt;1 Mrd) and can be used to control current flow through the DGVDMOSFET&#39;s semi-conducting channel region  125  even after MOSFET  191 , 193  sections become non-functional due to TID-induced voltage shift of MOS&#39;s threshold voltage. Enhanced SEGR performance can occur because the exemplary JFET gate  195  can be used to produce an electrical field  194  as shown in  FIG. 8 a   / FIG. 8 b    (e.g., depletion layer), where an electrical field  194  provides an additional barrier to retard drain potentials from coupling to the exemplary MOSFET gate oxide  208  during heavy ion strikes. Additional enhanced SEGR performance can occur because MOSFET  191 , 193  sections can be configured to conduct current (e.g.,  FIG. 10 c   , linear  251  or saturation  254 ) and JFET gate  195  can be configured to block current (e.g.,  FIG. 10 c   , cut-off  256 ), where under this exemplary configuration coupling of drain voltage to the gate oxide  208  is minimized. Enhanced SEB performance can occur because the exemplary JFET gate  195  can be used to produce an electrical field  194  (e.g., formation of a depletion field), where formation of electrical field  194  collects a portion of heavy ion generated photocurrent to effect a reduction in heavy ion generated photocurrent collected through the MOSFET  191 ,  193 . Additional enhanced SEB performance can occur because MOSFET  191 ,  193  can be configured to conduct current (e.g.,  FIG. 10 c   , linear  251  or saturation  254 ) and JFET gate  195  can be configured to block current (e.g.,  FIG. 10 c   , cut-off  256 ), where under this exemplary configuration a portion of the heavy ion generated photocurrent can be collected directly through the source  207  reducing heavy ion generated photocurrent collected through the body  205 .  FIG. 10 a    represents an exemplary DGVDMOSFET schematically connected to operate in an enhanced DC mode configuration.  FIG. 10 b    represents an exemplary current-voltage (I-V) response of an exemplary DGVDMOSFET  200  when exemplary JFET gate  195  is at a fixed bias and the MOSFET  191 ,  193  sections modulate current flow.  FIG. 10 b    demonstrates an example of five exemplary enhanced DC mode I-V responses or outputs (I-V responses  247 ,  248 ,  249 , and  250 ) of  FIG. 10 a    exemplary application (enhance DC mode configuration) in accordance with one embodiment of the invention.  FIG. 10 b    also depicts three regions of exemplary operation (cut-off  247 , linear  245 , and saturation  246 ). Cut-off  247  can be operable in  FIG. 10 a    exemplary example if power supply VG  253  delivers a voltage less than MOS&#39;s gate threshold voltage (Vth_MOS) to effect a reduction or elimination of DGVDMOSFET&#39;s current flow through MOS&#39;s semi-conductive channel region  123 . Linear  245  can be operable in  FIG. 10 a    exemplary example if power supply VG  253  delivers a voltage greater than MOS&#39;s gate threshold voltage (Vth_MOS) to enter a resistive DGVDMOSFET current flow through MOS&#39;s semi-conductive channel region  123 , where power supply VD  255  delivers a voltage less than the difference of VG and Vth_MOS. Saturation  246  can be operable in  FIG. 10 a    exemplary example if power supply VG  253  delivers a voltage greater than MOS&#39;s gate threshold voltage (Vth_MOS) to enter limited DGVDMOSFET current flow (saturation) through MOS&#39;s semi-conductive channel region  123 , where power supply VD  255  delivers a voltage greater than the difference of VG and Vth_MOS.  FIG. 10 c    represents a current-voltage (I-V) characteristic of an exemplary DGVDMOSFET  200  when exemplary MOSFET  191 ,  193  is at a fixed bias and the JFET gate  195  modulates current flow.  FIG. 10 c    shows examples of exemplary responses or outputs (I-V responses  256 ,  257 ,  258 ,  259  and  260 ) of enhanced DC Mode operation from  FIG. 10 a    exemplary application in accordance with one embodiment of the invention.  FIG. 10 c    also depicts exemplary examples of three regions of exemplary operation, cut-off  256 , Linear  252 , and saturation  254 . Cut-off  252  can be operable in  FIG. 10 a    exemplary example when power supply VG 2   251  delivers a voltage less than JFET&#39;s gate threshold voltage (Vth_JFET) to effect a reduction or elimination of DGVDMOSFET&#39;s current flow through JFET&#39;s semi-conductive channel region  125 . Linear  252  can be operable in  FIG. 10 a    exemplary example when power supply VG 2   251  delivers a voltage greater than JFET&#39;s gate threshold voltage (Vth_JFET) to enter a resistive DGVDMOSFET current flow through JFET&#39;s semi-conductive channel region  125 , where power supply VD  255  delivers a voltage less than the difference of VG and Vth_JFET. Saturation  254  can be operable in  FIG. 10 a    exemplary example when power supply VG 2   251  delivers a voltage greater than JFET&#39;s gate threshold voltage (Vth_JFET) to enter limited DGVDMOSFET current flow (saturation) through JFET&#39;s semi-conductive channel region  125 , where power supply VD  255  delivers a voltage greater than the difference of VG and Vth_JFET.  FIGS. 10 b  and 10 c    do not represent actual DGVDMOSFET&#39;s I-V characteristics and are only provided to demonstrate application of an exemplary DGVDMOSFET in enhanced DC mode. 
       FIG. 11 a    shows another exemplary application (e.g., enhanced AC mode configuration) of exemplary DGVDMOSFET  200  symbol shown in  FIG. 8 c    in accordance with one embodiment of the invention.  FIG. 11 a    schematic shows a MOS gate power supply (VG)  267 , a MOS gate alternating current (AC) power supply (VAC)  265 , a JFET gate power supply (VG 2 )  263 , a JFET gate AC power supply (VAC 2 )  261 , and a drain power supply (VD)  266  coupled to the DGVDMOSFET embodiment  200 . In this exemplary configuration, the MOSFET gate  191 , 193  and the JFET gate  195  can be operated separately or together to assist in controlling DC current flow and AC current flow in phase or out of phase to allow a variety of different radio frequency (RF) type applications such as RF mixers, RF amplifiers, and RF gain control. This exemplary operational mode provides application designers functionality of two independent gates in a variety of RF type applications. The  FIG. 11 a    exemplary embodiment represents a simplistic RF mixer application using exemplary DGVDMOSFET  200  in a dual-gate AC mode operation.  FIG. 11 b    represents one exemplary output using a RF mixer type circuit.  FIG. 11 b    does not represent an actual DGVDMOSFET output but is provided to demonstrate its potential application. 
     Exemplary embodiments of a DGVDMOSFET (e.g.,  200 ,  200 ′) can provide for a design/layout of a monolithic structure with two independent gate terminals to modulate drain-to-source current flow (e.g., can replace two devices, where devices are slaved together). With two independent gate terminals to modulate current flow (or modulate signal), an exemplary embodiment can be used as a radio frequency (RF) mixer, modulator, demodulator, gain control element and more in analog circuits. Exemplary gate functionality can be operated out of phase or operated in phase depending upon the desired circuit application allowing greater circuit design flexibility in this example due to how two-gate functionality in accordance with an embodiment of the invention can be independent in operation. A monolithic solution lowers costs, size, and weight and increase reliability which are important factors in a majority of strategic and space systems. 
     In one example, conventional non-radiation hardened VDMOSFETs cannot operate in TID environments without degraded performance of the MOSFET sections  191 ,  193  where a MOS gate may become non-functional (non-functional performance of commercial VDMOSFETs with ionizing radiation can be less than 10 krd(Si)). An addition of an exemplary JFET gate  195  provides a different configuration and method to control current flow. An exemplary JFET gate  195  is not directly degraded by TID radiation (e.g., functional performance of JFETs with ionizing radiation can be greater than 1 Mrd(Si)). If MOSFET sections  191 ,  193  are degraded or become non-functional due to TID, then an exemplary JFET gate  195  can be used to extend the operating performance of device. 
     An exemplary embodiment can be designed and fabricated to operate at drain-to-source voltages from a few volts to voltages over a thousand volts. A drain-to-source breakdown voltage (BVDSS) of an exemplary embodiment can be determined by epitaxial doping and epitaxial thickness. An exemplary design and layout of an overall embodiment can be minimal. Therefore, exemplary embodiments with different blocking voltages can be realized. 
     An exemplary embodiment can be designed and fabricated to handle different currents. The current handling capability of a fabricated device can be increased by placing an exemplary embodiment into an array of parallel cells that can be a few cells to several thousand cells placed in parallel. Therefore, embodiments with different current capabilities can be realized. 
     An exemplary JFET gate  195  can maintain operational capability in particle-rich radiation environment such as a space environment. For example, an exemplary JFET gate  195  can increase failure threshold voltages for SEB and SEGR, which increases the operational capabilities of exemplary embodiments in a particular type of radiation environment (higher failure thresholds equate to higher radiation performance). Higher SEB and SEGR failure threshold voltages are desirable in short- and long-term applications where embodiments of the invention are subjected to particles (SEB and SEGR can be catastrophic). 
     SEB performance can be improved with an exemplary embodiment as particle-induced photocurrent, which normally flows into Body  205  or  214  can decrease as a portion of induced photocurrent can flow into the exemplary JFET  195 &#39;s Body  217  or  219 . Reducing induced photocurrent flowing into exemplary Body  205  can increase a threshold for SEB. 
     SEGR performance can be improved using an embodiment of the invention because particle-induced coupling of a portion of the drain potential across an exemplary gate oxide  208  can be impeded by an added depletion field induced by an exemplary JFET section  195 . 
     An exemplary embodiment can provide for two independent body diodes (e.g., a source body diode and a JFET body diode). Having two independent diodes allows more flexibility in circuit designs. As an example, a source body diode or JFET body diode can be used as a freewheeling diode in switching applications. 
     An exemplary embodiment can be fabricated using different semiconductor and dielectric materials e.g., Silicon (Si) and Silicon Dioxide (SiO2). Other semiconductor materials such as silicon carbide (SiC) and Gallium Arsenide (GaAs) can be used instead of silicon for, e.g., an epitaxial layer and doped implants/diffusions. Use of other semiconductor materials such as SiC provides structures with different characteristics and higher performance characteristics. As an example, SiC has a higher band gap, breakdown field, and thermal conductivity when compared to silicon. These types of characteristics yield higher current density, higher voltages, and better thermal conductivity. Other dielectric materials can be used to form, e.g., gate oxide  208 . Alternative materials can include but are not limited to SiN, Al2O3, and HfO2. Use of other dielectrics provides different performance characteristics such as increasing or decreasing oxide capacitance which affects switching performance. 
       FIG. 12  shows exemplary methods of operation  300  of exemplary embodiments of the invention. These methods of operation can be triggered based on determinations that operation of one or more functionalities of an exemplary embodiment of the invention is needed such as, for example, detecting a condition to alter operation of the MOSFET sections  191 ,  193  in response to an electromagnetic interference event. Another determination for need to operate exemplary functionality is determining additional or different current or voltage control operations are desirable such as in RF system operation such as described above. Once a determination of a need for operation has been determined, operation of an exemplary embodiment of the invention can commence such as, for example, at step  301 , a standard DC mode of operation can be initiated comprising providing an exemplary embodiment of the invention such as described above; at step  303 , shorting JFET Gate  211  to Source  201 ; at step  305 , applying DC voltage to drain  202 ; at step  307 , applying voltage to MOS Gate  209  to control output, current and voltage, between drain  202  and source  201 . A second mode can comprise initiating an Enhanced DC Mode of Operation using a design such as described herein/above at step  317 ; at step  319 , apply DC voltage to drain  202 ; steps  321 / 325  can be executed concurrently or separately following a step shown as respectively preceding these steps comprising applying DC voltage to JFET gate  211  and applying DC voltage to MOS gate  209 ; steps  323  and  327  can be executed concurrently or separately comprising applying voltage to MOS gate  209  to control current/voltage between drain  202  and source  201  as well as applying voltage to JFET gate  211  to control current/voltage between drain  202  and source  201 . At step  331 , exemplary processing provides an Enhanced AC Mode configuration in accordance with an exemplary embodiment of the invention, such as discussed above/herein and initiates an Enhanced AC Mode Operation at step  331 ; at Step  333 , applying DC voltage to drain  202 ; at step  335 , applying DC voltage and AC input to JFET Gate  211 ; at step  337 , applying DC voltage and AC input to MOS gate  209 ; and at Step  339 , producing output using said Enhanced AC Mode Configuration of a mixer of AC inputs of JFET Gate  211  and MOS Gate  209 . 
       FIG. 13  shows another exemplary method of operation in accordance with another embodiment of the invention. Again, processing begins with providing an embodiment and configuration of an exemplary embodiment of the invention such as, for example, an Alternative Enhanced DC Mode of Operation Configuration, such as discussed herein/above at step  317 ; at step  319 , applying DC voltage to drain  202 ; steps  321 ,  325 , and  341  (each following step  319 ) can be executed substantially concurrently or separately following a step shown as preceding these steps wherein step  321  comprises applying DC voltage to JFET Gate  211 , applying DC voltage to MOS Gate  209 , and under an “Off State” condition (e.g., when MOS Gate is turned off or not having power applied to one or more portions of it), apply reverse bias to the JFET Gate  211 ; steps  323 ,  327 , and  343  (respectively following step  321 ,  325 , and  341 ) can be executed substantially concurrently or separately following a step shown as preceding these steps wherein step  323  comprises applying voltage to MOS Gate  209  to control current flow between drain  202  and source  201 , step  327  comprises applying voltage to JFET Gate  211  to control current flow between drain  202  and source  201 , and reducing effects from radiation or electromagnetic interference at step  343  by operation or modulation of the exemplary Alternative Enhanced DC Mode configuration. 
       FIGS. 14 a -14 c    show another exemplary method of operation  401  in accordance with another embodiment of the invention. Again, a process begins by initiating standard DC mode configuration step  403  by connecting the JFET gate  211  to the source  201  step  405  and by connecting drain  202  to an external circuit (e.g., power supply) step  407 . The next step is a determination depending upon system requirements of how to configure exemplary functionality such as whether to initiate MOS cut-off mode step  409 ; whether to initiate MOS linear mode step  411 ; whether to initiate MOS saturation mode step  413 ; or whether to initiate Switch mode step  421 . MOS cut-off mode step  415  is initiated by connecting MOS gate  209  to an external circuit that delivers a gate voltage to MOS gate  209  up to a voltage less than the MOS&#39;s threshold voltage (Vth_MOS) to effect a reduction or elimination of DGVDMOSFET current flow through the semi-conductive channel region (e.g., SCR  123 ). MOS linear mode step  417  is initiated by connecting MOS gate  209  to an external circuit that delivers a gate voltage to MOS gate  209  that is greater than the MOS&#39;s threshold voltage (Vth_MOS) to effect and to modulate a resistive current-voltage (I-V) response through MOS&#39;s semi-conductive channel region (e.g., SCR  123 ). To function in linear mode step  417 , drain voltages must be less than the difference between the gate voltage (VG) and the gate threshold voltage (VTH_MOS) (e.g., VD&lt;VG−Vth_MOS). MOS saturation mode step  419  is initiated by connecting MOS gate  209  to an external circuit that delivers a gate voltage to MOS gate  209  that is greater than the MOS&#39;s threshold voltage (Vth_MOS) to effect and to modulate a resistive current-voltage (I-V) response through MOS&#39;s semi-conductive channel region (e.g., SCR  123 ). To function in saturation mode step  419 , drain voltages must be greater than the difference between the gate voltage (VG) and the gate threshold voltage (VTH_MOS) (e.g., VD&gt;VG−Vth_MOS). Switch mode step  423  is initiated by connecting MOS gate  209  to an external circuit to deliver a gate voltage VG to MOS gate  209  to switch the DGVDMOSFET&#39;s I-V response between cut-off step  415  and linear step  417 ; between linear step  417  and saturation step  419 ; or between cut-off step  415  and saturation step  419  to effect a predetermined DGVDMOSFET&#39;s (I-V) response operable to a duty cycle to effect said predetermined I-V response. 
       FIGS. 15 a -15 b    show another exemplary method of operation  501  in accordance with another embodiment of the invention. Again, a process begins by initiating enhanced DC mode step  503  by connecting the MOS gate  209  to an external circuit executing cut-off mode step  507  and by connecting drain  202  to an external circuit (e.g., power supply) step  505 . The process continues by initiating an enhanced radiation mode step  513  providing a configuration to enhance performance of the DGVDMOSFET functionality when the embodiment of the invention is subjected to radiation effects (e.g., TID  515 , SEB  517 , and SEGR  519 ), by executing JFET cut off mode step  509 . Cut off  511  is initiated by connecting JFET gate  211  to an external circuit that delivers a gate voltage to JFET gate  211  up to a voltage less than JFET&#39;s threshold voltage (Vth_JFET) to effect a reduction or elimination of DGVDMOSFET current flow through the semi-conductive channel region (e.g., SCR  125 ). 
       FIGS. 16 a -16 c    show another exemplary method of operation  601  in accordance with another embodiment of the invention. Again, a process begins by initiating enhanced DC mode step  603  by connecting the MOS gate  209  to an external circuit executing linear mode step  607  and by connecting drain  202  to an external circuit (e.g., power supply) step  605 . The process continues by initiating enhanced radiation mode step  615  providing a configuration to enhance performance of the DGVDMOSFET functionality when the embodiment of the invention is subjected to radiation effects (e.g., TID  617 , SEB  619 , and SEGR  621 ), by executing JFET cut off mode step  609 . Other processes can be employed by initiating JFET linear mode step  611 ; or by initiating switch mode step  625 . Cut off step  613  is initiated by connecting JFET gate  211  to an external circuit that delivers a gate voltage to JFET gate  211  up to a voltage less than the JFET&#39;s threshold voltage (Vth_JFET) to effect a reduction or elimination of DGVDMOSFET current flow through JFET&#39;s semi-conductive channel region (e.g., SCR  125 ). Linear mode step  623  is initiated by connecting JFET gate  211  to an external circuit that delivers a gate voltage to JFET gate  211  that is greater than JFET&#39;s threshold voltage (Vth_JFET) to effect and to modulate a resistive current-voltage (I-V) response through JFET&#39;s semi-conductive channel region (e.g., SCR  125 ). To function in linear mode step  623 , drain voltages must be less than the difference between the gate voltage (VG) and the gate threshold voltage (VTH_JFET) (e.g., VD&lt;VG−Vth_JFET). The process can evolve by initiating switch mode step  625 . Switch mode step  627  is initiated by connecting JFET gate  211  to an external circuit to deliver a gate voltage VG to JFET gate  211  to switch DGVDMOSFET&#39;s I-V response between cut-off step  613  and linear step  623  to affect a predetermined DGVDMOSFET&#39;s (I-V) response operable to a duty cycle to effect said predetermined I-V response. 
       FIGS. 17 a -17 c    show another exemplary method of operation  701  in accordance with another embodiment of the invention. Again, a process begins by initiating enhanced DC mode step  703  by connecting the MOS gate  209  to an external circuit executing saturation mode step  707  and by connecting drain  202  to an external circuit (e.g., power supply) step  705 . The process continues by initiating enhanced radiation mode step  717  providing a configuration to enhance performance of the DGVDMOSFET functionality when the embodiment of the invention is subjected to radiation effects (e.g., TID  719 , SEB  721 , and SEGR  723 ), by executing JFET cut off mode step  709 . Other processes can be employed by initiating JFET saturation mode step  711 ; or by initiating switch mode step  725 . Cut off step  713  is initiated by connecting JFET gate  211  to an external circuit that delivers a gate voltage to JFET gate  211  up to a voltage less than the JFET&#39;s threshold voltage (Vth_JFET) to effect a reduction or elimination of DGVDMOSFET current flow through JFET&#39;s semi-conductive channel region (e.g., SCR  125 ). Saturation mode step  715  is initiated by connecting JFET gate  211  to an external circuit that delivers a gate voltage to JFET gate  211  that is greater than JFET&#39;s threshold voltage (Vth_JFET) to effect and to modulate a saturated current-voltage (I-V) response through JFET&#39;s semi-conductive channel region (e.g., SCR  125 ). To function in saturation mode step  715 , drain voltages must be greater than the difference between the gate voltage (VG) and the gate threshold voltage (VTH_JFET) (e.g., VD&gt;VG−Vth_JFET). Another process can evolve by initiating switch mode step  725 . Switch mode step  727  is initiated by connecting JFET gate  211  to an external circuit to deliver a gate voltage VG to JFET gate  211  to switch DGVDMOSFET&#39;s I-V response between cut-off step  613  and saturation step  715  to effect a predetermined DGVDMOSFET&#39;s (I-V) response operable to a duty cycle to effect said predetermined I-V response. 
       FIGS. 18 a -18 b    show another exemplary method of operation  801  in accordance with another embodiment of the invention. Again, a process begins by initiating enhanced AC mode step  803  by connecting the drain  202  to an external circuit (e.g., power supply) step  805 . The process continues by initiating either linear mode (MOS linear mode step  807  and JFET linear mode step  809 ) or saturation mode (MOS saturation mode step  811  and JFET saturation mode step  813 ). Another process can be employed by initiating RF mode step  815 . RF mode of MOS gate step  817  begins by connecting the MOS gate  209  to an external AC circuit to deliver an AC voltage to MOS gate  209  to modulate DGVDMOSFET&#39;s I-V response to effect a modulation of AC input into DGVDMOSFET&#39;s response. RF mode of JFET gate step  819  begins by connecting the JFET gate  211  to an external AC circuit to deliver an AC voltage to JFET gate  211  to modulate DGVDMOSFET&#39;s I-V response to effect a modulation of AC input into DGVDMOSFET&#39;s response. RF mode of both MOS gate and JFET gate step  821  begins by connecting MOS gate  209  and JFET gate  211  to external AC circuits to deliver AC voltages (in phase or out of phase) to said gates to modulate DGVDMOSFET response to said AC inputs. 
       FIG. 19  shows a block diagram of an exemplary application (a linear voltage regulator  901 ) where an exemplary DGVDMOSFET  905  is connected to an unregulated DC power source  903  (e.g., 28 volt solar array). The exemplary JFET gate  211  is connected to source  201 . The source  201  is connected to an output sensing circuit  907  (e.g., a resistor divider network). The sensing network  907  provides an input to an external feedback amplifier  909  with the other input being a reference voltage  911 . If regulated DC output voltage  915  is lower or higher than expected output voltage, said feedback amplifier  909  adjusts the MOS gate voltage until expected output voltage is achieved. 
       FIG. 20  shows a block diagram of an exemplary application (a switching voltage regulator  931 ) where an exemplary DGVDMOSFET  935  is connected to an unregulated DC power source  933  (e.g., 28 volt solar array). The exemplary MOS gate  209  is connected to a MOS gate circuit  937  where MOS gate  209  is configured to operate in saturation mode. The source  201  is connected to an output sensing circuit  939  (e.g., a resistor divider network). The sensing network  939  provides an input to an external feedback amplifier  941  with the other input being a reference voltage  943 . If regulated DC output voltage  947  is lower or higher than expected output voltage, said feedback amplifier  941  adjusts the JFET gate drive circuit  945  (e.g., pulse width modulator) to adjust the duty cycle in switch mode until desired output voltage is achieved. 
       FIG. 21  shows a block diagram of an exemplary application (RF amplifier  961 ) where an exemplary DGVDMOSFET  965  is connected to DC power source  963  (e.g., regulated voltage). The exemplary JFET gate  211  is connected to source  201 . The exemplary MOS gate  209  is connected to RF input with a DC offset circuit  969  where MOS gate  209  is configured to operate in linear AC mode. The drain  202  is connected to a DC blocking circuit  967  (e.g., capacitor), where DC blocking circuit  967  removes DC voltage from RF output  971 . 
       FIG. 22  shows a block diagram of an exemplary application (RF mixer  981 ) where an exemplary DGVDMOSFET  985  is connected to DC power source  983  (e.g., regulated voltage). The exemplary JFET gate  211  is connected to local oscillator (LO) with DC offset circuit  987 , where the JFET gate  211  is configured to operate in linear AC mode. The exemplary MOS gate  209  is connected to RF input with DC offset circuit  989  where the MOS gate  209  is configured to operate in linear AC mode. The drain  202  is also connected to DC blocking circuit  991  (e.g., capacitor), where DC blocking circuit  991  removes DC voltage from RF mixer output  993 . 
     Although the invention has been described in detail with reference to certain preferred embodiments, variations and modifications exist within the spirit and scope of the invention as described and defined in the following claims.