Patent Publication Number: US-6670771-B2

Title: Organic electroluminescence display and driving method and apparatus thereof

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This application claims priority to and the benefit of Korea Patent Application No. 2002-0015438 filed on Mar. 21, 2002 in the Korean Intellectual Property Office, the contents of which are incorporated herin by reference. 
     BACKGROUND OF THE INVENTION 
     (a) Field of the Invention 
     The present invention relates to an organic electroluminescence (hereinafter, “EL”) display and a scan driver, and, more particularly, to an organic EL display and a scan driver with low power consumption. 
     (b) Description of the Related Art 
     In general, an organic EL display is a display that emits light by electrical excitation of fluorescent organic compound and displays images by driving each of M×N organic luminescent cells with voltage or current. 
     The organic cell has a structure of an anode (ITO), an organic thin film and a cathode layer (metal). The organic thin film is formed as a multi-layered structure including an emission layer (“EML”), an electron transport layer (“ETL”), and a hole transport layer (“HTL”) so as to increase luminescence efficiency by balancing electron and hole concentrations. In addition, it can include an electron injection layer (“EIL”) and a hole injection layer (“HIL”) separately. 
     Organic EL displays that use organic luminescent cells like the above are configured as a passive matrix or an active matrix that includes thin film transistors (TFTs). In the passive matrix configuration, organic luminescent cells are formed between anodes and cathodes lines that cross each other and are driven by driving those lines. While in the active matrix configuration, each organic luminescent cell is coupled to a TFT usually through ITO electrode and are driven by controlling the gate voltage of the corresponding TFT. 
     The organic EL display is generally composed of an organic EL display panel, a scan driver, and a data driver. The organic EL display panel includes a plurality of data lines transmitting data signals representing image signals, a plurality of scan lines transmitting selection signals and pixel circuits provided in pixel areas defined by two adjacent data lines and two adjacent scan lines. When the scan driver applies the selection signals to the scan lines, transistors are turned on by the selection signals, and then, the data signals representing the image signals are applied to gates of driving transistors from the data driver through the data lines, and currents flow through organic EL devices via the transistors in correspondence to the data signals applied to the gates thereof. Thereby, lights are emitted. 
     In this case, as shown in FIG. 1A, the scan driver is composed of master-slave type flip-flops and NAND gates, and each flip-flop includes four inverters as shown in FIG.  1 B. If inverters and NAND gates composed of PMOS transistors or NMOS transistors, which are easy to manufacture compared with CMOS transistors, are used, static currents flow. 
     FIGS. 2A and 2B are circuit diagrams to represent output parts where the static currents are generated when PMOS transistors or NMOS transistors are used in the inverters or NAND gates. 
     As shown in FIG. 2A, in the case where logic circuits are composed of PMOS transistors, when a load is attached to GND side, and output V out  is high level, the static currents flow. As shown in FIG. 2B, in the case where logic circuits are composed of NMOS transistors, when a load is attached to VDD side, and output V out  is low level, the static currents flow. Accordingly, when the inverter using PMOS transistors has a low level input and when the NAND gate using PMOS transistors has at least one low level input, the output thereof is high level, and thereby the currents flow. However, in case of a flip-flop composed of four inverters, two inverters receive low level inputs and the other two inverters receive high level inputs. Thus, the static currents always flow in the half of the inverters within the flip-flop. 
     In the organic EL display panel, so as to use PMOS transistors connected to the scan lines as normally-off switches, inputs applied to the PMOS transistors, i.e., outputs of NAND gates (in case of being composed of PMOS transistors) must become high levels. Accordingly, the static currents flow in the NAND gates during most of time. 
     When the static currents flow as above, there is a problem that static power loss is increased, and thereby power consumptions are increased in the scan driver. 
     SUMMARY OF THE INVENTION 
     In accordance with the present invention power consumption is decreased by reducing static currents in a scan driver. 
     A scan driver is divided into several parts and a clear signal is applied to a non-operating scan driver. 
     An organic EL display according to the present invention includes an organic EL display panel, a data driver applying data signals to data lines, and a scan driver applying selection signals to scan lines. The organic EL display panel includes a plurality of scan lines transmitting selection signal, a plurality of data lines transmitting data signals representing image signals, and a plurality of pixel circuits coupled to the scan lines and the data lines. 
     The scan driver is composed of more than two scan driving units and a selection controller generating clear signals, and each scan driving unit includes a plurality of flip-flops coupled with each other in series and a plurality of buffer units receiving outputs of the flip-flops to drive the respective scan lines. Each of the flip-flops is composed of a plurality of logic gates (NOR gates or NAND gates) and a plurality of switching elements. The clear signals keep outputs of logic gates of scan driving units as a constant value for the scan driving units not to generate the selection signal. 
     The flip-flop is composed of a first to a fourth logic gates, and the first logic gate receives the clear signal and output of the previous flip-flop, inputted through a first switching element, as input. A second logic gate receives the output of the first logic gate and the clear signal as input, and the output terminal of the second logic gate is coupled via a second switching element to the output of the previous flip-flop inputted through the first switching element. A third logic gate receives the clear signal and the output of the first logic gate inputted through a third switching element as input, and output of the third logic gate becomes output of the flip-flop. A fourth logic gate receives the clear signal and the output of the third logic gate, and the output terminal of the fourth logic gate is coupled via a fourth switching element to the output of the first logic gate inputted through the third switching element. 
     In addition, the selection controller may further generate reset signals for setting initial values of the scan driving units. The first and the fourth logic gates preferably further receive the reset signals as inputs. 
     Furthermore, the buffer unit preferably includes a fifth logic gate receiving output of the flip-flop and the clear signal. The buffer unit may include an inverter coupled to output terminal of the fifth logic gate and a buffer coupled to output terminal of the inverter. 
     The first to the fifth logic gates are preferably composed of the same conductive type thin film transistors. 
     The first to the fifth logic gates are NOR gates, which may be composed of PMOS transistors. Or, the first to the fifth logic gates are NAND gates, which may be composed of NMOS transistors. 
     A method of driving the organic EL display in accordance with the present invention includes: dividing the scan driver into a plurality of scan driving units, applying a first clear signal, with level for making outputs of the logic gates constant regardless of other inputs, to the other scan driving units while the selection signal is generated from a n-th scan driving unit, and applying a second clear signal with level opposite to that of the first clear signal to the n-th scan driving unit; applying the second clear signal to a (n+1)-th scan driving unit adjacent to the n-th scan driving unit before the (n+1)-th scan driving unit receives the selection signal outputted from the last flip-flop of the n-th scan driving unit; and applying the first clear signal to the n-th scan driving unit when the selection signal begins to be outputted from the (n+1)-th scan driving unit. 
     In addition, a reset signal for setting an initial value of the (n+1)-th scan driving unit may be applied thereto before the second clear signal is applied to the (n+1)-th scan driving unit. 
     The logic gates are preferably NOR gates composed of PMOS transistors. Or, the logic gates are NAND gates composed of NMOS transistors. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIGS. 1A and 1B are circuit diagrams illustrating a scan driver and a flip-flop according to the prior art, respectively. 
     FIGS. 2A and 2B are circuit diagrams illustrating output parts where static currents are generated in case of using PMOS transistors or NMOS transistors in an inverter or a NAND gate in a scan driver according to the prior art, respectively. 
     FIG. 3 is a diagram illustrating an organic EL display according to an embodiment of the present invention. 
     FIG. 4 is a diagram illustrating a scan driver of the organic EL display according to an embodiment of the present invention. 
     FIG. 5 is a circuit diagram illustrating a first scan driving unit according to an embodiment of the present invention. 
     FIG. 6 is a circuit diagram illustrating a flip-flop according to an embodiment of the present invention. 
     FIGS. 7A and 7B are circuit diagrams illustrating 2-input and 3-input NOR gates used in a flip-flop according to an embodiment of the present invention, respectively. 
     FIG. 8 is a circuit diagram illustrating a buffer unit according to an embodiment of the present invention schematically. 
     FIG. 9 is a circuit diagram illustrating the buffer unit according to an embodiment of the present invention in detail; and 
     FIG. 10 is a timing diagram of a scan driver according to an embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION 
     In the specification, similar parts are denoted by the same reference numerals. When a part is connected to another part, the part is not only directly connected to another part but is also electrically connected (coupled) to another part while another device intervenes between them. 
     First, referring to FIGS. 3 and 4, an organic EL display and a scan driver thereof according to a first embodiment of the present invention will be described in detail. 
     FIG. 3 is a diagram illustrating an organic EL display according to the first embodiment of the present invention. FIG. 4 is a diagram illustrating a scan driver of the organic EL display according to the first embodiment of the present invention. 
     As shown in FIG. 3, the organic EL display according to the first embodiment of the present invention includes organic EL display panel  100 , scan driver  200 , and data driver  300 . 
     Organic EL display panel  100  includes a plurality of data lines Y 1  to Y N  transmitting data signals (data voltages or data currents) representing image signals, a plurality of scan lines transmitting selection signals X 1  to X M , and a plurality of pixel circuits  110 . Transistors connected to the scan lines are PMOS transistors in order to be used as normally off switches in organic EL display panel  100 . Pixel circuits  110  are provided in pixel areas defined by two adjacent data lines and two adjacent scan lines. 
     Scan driver  200  applies the selection signals to scan lines X 1  to X M , and data driver  300  applies the data signals representing image signals to data lines Y 1  to Y N . 
     As shown in FIG. 4, scan driver  200  according to the first embodiment of the present invention includes first to third scan driving units  210 ,  220 , and  230  and block selecting controller  240 . 
     First to third scan driving units  210 ,  220 , and  230  are to divide a conventional driver into three parts. Such division is not to be limited to three parts and can be divided into several parts as configurations and operations that may be different according to the number of parts are apparent to those skilled in the art, and thus, description thereof will be omitted. For example, in case a scan driver of 240 outputs is divided into three parts, each of first to third scan driving units  210 ,  220 , and  230  becomes a scan driving unit of 80 outputs. 
     Block selecting controller  240  outputs clear signals VC 1 , VC 2 , and VC 3  for removing static currents and reset signals RST 1 , RST 2 , and RST 3  for setting initial values of the first to third scan driving unit  210 ,  220 , and  230  to control operations of the first to third scan driving unit  210 ,  220 , and  230 . 
     Hereinafter, referring to FIG. 5 to FIG. 9 the scan driving unit will be described in detail. 
     FIG. 5 is a circuit diagram illustrating a first scan driving unit according to an embodiment of the present invention. FIG. 6 is a circuit diagram illustrating a flip-flop according to an embodiment of the present invention. 
     FIGS. 7A and 7B are circuit diagrams illustrating 2-input and 3-input NOR gates used in the flip-flop according to an embodiment of the present invention. FIG.  8  is a circuit diagram illustrating a buffer unit according to an embodiment of the present invention. FIG. 9 is a circuit diagram illustrating the buffer unit according to an embodiment of the present invention in detail. 
     As shown in FIG. 5, first scan driving unit  210  is composed of a plurality of flip-flops FF 1  to FF m  and a plurality of buffers buf 1  to buf m  having the outputs of the flip-flops as the inputs. Flip-flops FF 1  to FF m  have an input signal V in , clock signals clk and clkb, and clear signal VC 1  as inputs. Each of the buffer units buf 1  to buf m  includes an OR gate and a buffer having the output of the OR gate as the input, and the OR gate has an OE signal, output V out  of the flip-flop, and clear signal VC 1  as inputs. 
     In the first embodiment of the present invention to divide the scan driver, which applies selection signals to M scan lines X 1  to X M , into scan driving units  210 ,  220  and  230  of three parts, the number (m) of flip-flops FF 1  to FF m  and the number (m) of buffer unit buf 1  to buf m  of first scan driving unit  210  correspond to M/3, respectively. 
     One of the flip-flops FF of flip-flips FF 1  to FF m , as shown in FIG. 6, is composed of two 2-input NOR gates NOR 2  and NOR 3  and two 3-input NOR gates NOR 1  and NOR 4 , and clear signal VC 1  is inputted to all of NOR gates NOR 1  to NOR 4  and reset signal RST 1  is inputted only to 3-input NOR gates, NOR 1  and NOR 4 . 
     In detail, NOR gate NOR 1  of flip-flop FF receives not only clear signal VC 1  and reset signal RST 1  but also output V out  of the previous flip-flop via PMOS transistor P 0  turned on/off by clock clk, as V in . The output of NOR gate NOR 1  becomes the input of NOR gate NOR 2  together with clear signal VC 1 , and the output of NOR gate NOR 2  is connected to the drain of PMOS transistor P 0  via PMOS transistor P 1  turned on/off by clock clkb. In addition, the output of NOR gate NOR 1  is inputted to NOR gate NOR 3  together with clear signal VC 1  via PMOS transistor P 2  turned on/off by clock clkb. 
     The output of NOR gate NOR 3  is inputted to NOR gate NOR 4  together with clear signal VC 1  and reset signal RST 1 , and the output of NOR gate NOR 4  is connected to the drain of PMOS transistor P 2  via PMOS transistor P 3  turned on/off by clock clk. In addition, the output of NOR gate NOR 3  becomes output V out  of flip-flop FF to be input V in  of adjacent flip-flop. 
     The 2-input NOR gates NOR 2  and NOR 3  and 3-input NOR gates NOR 1  and NOR 4  may be configured, for example, as shown in FIGS. 7A and 7B. 
     As shown in FIG. 7A, each of 2-input NOR gates NOR 2  and NOR 3  is composed of 3 PMOS transistors, and the two inputs of NOR gates NOR 2  and NOR 3  are connected to the gates of PMOS transistors P 4  and P 5 , respectively. The source of PMOS transistor P 4  is connected to power source VDD, and the drain thereof is connected to the source of PMOS transistor P 5 . The drain of PMOS transistor P 5  becomes the output of the NOR gate, and this drain is connected to the source of PMOS transistor P 7 . The gate and the drain of PMOS transistor P 7  are connected with each other to be grounded. 
     As shown in FIG. 7B, 3-input NOR gates NOR 1  and NOR 4  further includes PMOS transistor P 6  of which the gate is connected to one input of the 3-input NOR gate between PMOS transistors P 5  and P 7  of the 2-input NOR gate shown in FIG.  7 A. 
     The flip-flop configured as above works as a shift register to transmit input V in  to the next flip-flop by the turning on/off of transistors in synchronization with the cycles of clocks clk and clkb. 
     In addition, in one buffer unit buf of buffer units buf 1  to buf m , as shown in FIG. 8, the OR gate is composed of NOR gate NOR 5  and an inverter INV 1 , and the buffer is composed of two inverters INV 2  and INV 3 . Herein, NOR gate NOR 5  and inverters INV 1 , INV 2  and INV 3  are composed of, for example, PMOS transistors as shown in FIG.  9 . 
     The second and third scan driving units  220  and  230  have the same configurations as the first scan driving unit except that clear signals VC 2  and VC 3  and reset signals RST 2  and RST 3  are inputted as a clear signal and a reset signal, respectively. Thus, a detailed description thereof will be omitted. 
     Next, referring to FIG. 10, a driving method of the scan driver according to the first embodiment of the present invention will be described. 
     FIG. 10 is a timing diagram of input/output waveforms of the scan driving unit according to the first embodiment of the present invention. 
     As shown in FIG. 10, while the selection signal of low level turning on pixel circuit is outputted from first scan driving unit  210 , that is, one of outputs V out1  to V out80  of the first scan driving unit is low level, clear signal VC 1  inputted to first scan driving unit  210  is low level, and clear signals VC 2  and VC 3  inputted to second and third scan driving units  220  and  230  are high levels. 
     In addition, while one of outputs V out80  to V out160  of second scan driving unit  220  is low level, clear signal VC 2  inputted to second scan driving unit  220  is low level, and clear signals VC 1  and VC 3  are high levels. While one of outputs V out161  to V out240  of third scan driving unit  230  is low level, clear signal VC 3  inputted to third scan driving unit  230  is low level, and clear signals VC 1  and VC 2  are high levels. 
     When the clear signal is high level as above, the outputs of the NOR gate, which is composed of the PMOS transistors in flip-flop FF as shown in FIGS. 7A and 7B, are always low levels, and the static currents do not flow to the GND side. In addition, as shown in FIG. 9, the outputs of the NOR gate, which is composed of the PMOS transistors forming the OR gate of buffer unit buf, are also low levels, and the static currents do not flow as described in the prior art. In this way, by inputting the clear signal to the scan driving unit, which does not output the selection signal turning on the pixel circuit, it is possible to remove the static currents. 
     Next, a process to shift from first scan driving unit  210  to second driving unit  220  will be described. 
     Second scan driving unit  220  receives last output V out80  of first scan driving unit  210  to perform an operation. Although clear signal VC 1  is low level till the end of the pulse of last output V out80  thereof, clear signal VC 1  is kept to be low level for another half clock for an operation margin of a circuit. In addition, while first scan driving unit  210  is operating, reset signal RST 2  are inputted thereto prior to input V out80  of second scan driving unit  220  by one clock in order to set an initial value of second driving unit  220  cleared by clear signal VC 2  of high level. And, the clear signal is kept low level in order to operate second scan driving unit  220 . Reset signal RST 2  is inputted thereto prior to clear signal VC 2  by more than half clock for an operation margin of a circuit. 
     In addition, a process to shift from second scan driving unit  220  to third scan driving unit  230  is the same as the process to shift from first scan driving unit  210  to second scan driving unit  220 , and thus, the description thereof will be omitted. 
     Next, the organic EL display, a scan driver, and a driving method thereof according to a second embodiment of the present invention will be described. 
     The organic EL display and the scan driver thereof according to the second embodiment of the present invention are the same as that of the first embodiment except that logic circuits are composed of NMOS transistors instead of PMOS transistors. 
     In detail, the first embodiment using PMOS transistors employs signals of high levels as clear signals VC 1 , VC 2 , and VC 3  for removing the static currents and configures logic circuits by using NOR gate, of which the output is always fixed with low level when a signal of high level is inputted. On the contrary, the second embodiment using the NMOS transistors employs signals of low level as clear signals VC 1 , VC 2 , and VC 3  for removing the static currents and configures logic circuits by using NAND gate, of which the output is always fixed with high level when a signal of low level is inputted. 
     In other words, flip-flops FF 1  to FF m  are composed of NAND gates NAND 1  to NAND 4  and NMOS transistors instead of NOR gates NOR 1  to NOR 4  and PMOS transistors. Buffer units buf 1  to buf m  are formed using an AND gate and a buffer. The AND gate is composed of a NAND gate and an inverter, and the buffer is composed of two inverters. 
     More detailed configurations and driving method thereof are apparent to those skilled in the art through previous description, and thus, the description thereof will be omitted. 
     In addition, although reset signals RST 1 , RST 2 , and RST 3  are applied to first to third scan driving units  210 ,  220 , and  230  in order to set initial values thereof, the reset signal may be not applied thereto in a practical operation of a circuit. 
     Since, in the present invention, the scan driver is divided into several parts to be driven and the clear signals are applied to non-operating units, it is possible to reduce the static currents flowing through the load, and accordingly, to decrease a power consumption. 
     Although specific embodiments of the present invention have been described in detail hereinabove, it should be clearly understood that many variations and/or modifications of the basic inventive concepts taught herein which may be apparent to those skilled in the present art will still fall within the spirit and scope of the present invention, as defined in the appended claims.