Patent Publication Number: US-11393697-B2

Title: Semiconductor chip gettering

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application is a divisional application of and claims priority from U.S. patent application Ser. No. 16/226,790, filed on Dec. 20, 2018. 
    
    
     BACKGROUND 
     Conventional semiconductor chips or dies are routinely fabricated en masse in large groups as part of a single semiconductor wafer. At the conclusion of the processing steps to form the individual dies, a so-called dicing or sawing operation is performed on the wafer to cut out the individual dies. Thereafter, the dies may be packaged or directly mounted to a printed circuit board of one form or another. 
     A typical conventional semiconductor wafer is manufactured with scores or more dies. This fabrication process consists of a large number of manufacturing steps, such as photolithography, ion implants, anneals, etches, chemical and physical vapor deposition and plating to name a few. Significant effort is expended by semiconductor manufacturers toward the goal of achieving nearly identical manufacturing outcomes for the individual semiconductor dies of a wafer. 
     Transistors in conventional wafer fab processes are susceptible to metal contamination from metals such as copper and sodium. Copper can also be introduced as an impurity at the die packaging stage or even during operation (known as in-field contamination). Copper is widely used for chip conductors due to its desirable conductivity. However, copper exhibits a relatively high diffusivity in silicon. To tackle the problem of copper contamination, some conventional wafer processes incorporate fabrication of a gettering layer on the backside of wafers. Some conventional wafer level gettering layer formation techniques include intrinsic gettering and extrinsic gettering. Intrinsic gettering involves introducing bulk micro defects by controlled formation of oxide precipitates in the silicon ingot from which the wafers are cut. Two conventional wafer level extrinsic gettering layer formation techniques include deposition of backside films, such as silicon oxide, silicon nitride or epitaxial silicon, which impart localized strains to create lattice defects, and backside wafer grinding. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The foregoing and other advantages of the invention will become apparent upon reading the following detailed description and upon reference to the drawings in which: 
         FIG. 1  is a pictorial view of an exemplary semiconductor chip device; 
         FIG. 2  is a plan view of the exemplary semiconductor chip device; 
         FIG. 3  is a portion of  FIG. 2  shown at greater magnification; 
         FIG. 4  is a sectional view of  FIG. 3  taken at section  3 - 3 ; 
         FIG. 5  is a sectional view like  FIG. 4 , but depicting alternate exemplary laser ablation crater formation; 
         FIG. 6  is a sectional view like  FIG. 5 , but depicting alternate exemplary laser ablation crater formation; 
         FIG. 7  is a pictorial view of a portion of an exemplary semiconductor chip and laser spots; 
         FIG. 8  is a pictorial view of a portion of an exemplary semiconductor chip and exemplary laser targeting; 
         FIG. 9  is a sectional view like  FIG. 5 , but depicting alternate exemplary laser ablation crater formation; 
         FIG. 10  is a plan view of an exemplary semiconductor chip with completed exemplary laser ablation craters; and 
         FIG. 11  is a pictorial view of an exemplary semiconductor chip device undergoing thermal interface material application. 
     
    
    
     DETAILED DESCRIPTION 
     Conventional gettering formation techniques are wafer level processes performed before singulation. Conventional intrinsic gettering by way of introducing bulk micro defects through controlled formation of oxide precipitates in silicon ingots is inexact and may not provide reliable copper contamination protection. Conventional wafer level extrinsic gettering layer formation techniques through deposition of backside films requires expensive foundry equipment. Conventional backside wafer grinding can cause wafer warpage and breakage and can be difficult if not impossible for very thin wafers of less than 100 microns. 
     The disclosed new arrangements and techniques utilize laser pulses to irradiate singulated die backsides. The laser pulses create multitudes of laser ablation craters. When the laser ablation craters are created, structural defects are created in the semiconductor material proximate the backsides. The structural defects create amorphous regions which function as gettering regions. The techniques do not require expensive foundry machinery, and can be performed on chips, with sub-100 micron thicknesses or not, without the grinding risks. Although laser scribing has been conventionally done on die backsides for engraving die and vendor markings, such conventional scribing is performed with laser parameters designed to avoid causing structural defects and typically only over a fraction of die backside surface areas. 
     In accordance with one aspect of the present invention, an apparatus is provided that includes a semiconductor chip that has a first side and a second side opposite the first side. The first side has a plurality of laser ablation craters. Each of the ablation craters has a bottom. A gettering region is in the semiconductor chip beneath the laser ablation craters. The gettering region includes plural structural defects. At least some of the structural defects emanate from at least some of the bottoms of the laser ablation craters. 
     In accordance with another aspect of the present invention, an apparatus is provided that includes a package substrate and a semiconductor chip mounted on the package substrate. The semiconductor chip has a first side and a second side opposite the first side. The second side faces the package substrate. The first side has a plurality of laser ablation craters. Each of the ablation craters has a bottom. A gettering region is in the semiconductor chip beneath the laser ablation craters. The gettering region includes plural structural defects. At least some of the structural defects emanates from at least some of the bottoms of the laser ablation craters. 
     In accordance with another aspect of the present invention, a method of manufacturing is provided that includes irradiating a first side of a semiconductor chip with laser pulses that have a pulse duration to create a plurality of laser ablation craters. Each of the ablation craters has a bottom. The pulse duration is long enough to create a gettering region in the semiconductor chip beneath the laser ablation craters. The gettering region includes plural structural defects. At least some of the structural defects emanate from at least some of the bottoms of the laser ablation craters. 
     In the drawings described below, reference numerals are generally repeated where identical elements appear in more than one figure. Turning now to the drawings, and in particular to  FIG. 1 , therein is depicted a pictorial view of an exemplary semiconductor chip device  100  that includes a semiconductor chip  105  mounted on a circuit board  110 . The semiconductor chip  105  can be virtually any type of integrated circuit, a non-exhaustive list of examples includes a central processing unit (CPU), an integrated circuit dedicated to video processing, a graphics processing unit (GPU), an accelerated processing unit (APU) that combines CPU and GPU functions, an application specific integrated circuit or other device. The semiconductor chip  105  can be composed of silicon, gallium arsenide or other types of semiconductor materials, and can be monolithic semiconductor or a semiconductor on insulator substrate, such as silicon on oxide or silicon on sapphire. The semiconductor chip  105  is flip-chip mounted on the package substrate  110  in this illustrative arrangement. However, other mounting schemes are envisioned. 
     The circuit board  110  can be a package substrate or other type of circuit board, and can be a multi-layer organic, a ceramic or other type of circuit board. To interface electrically with another device such as a socket (not shown) the package substrate  110  can include plural interconnects  115 , which in this illustrative arrangement are pins that form a pin grid array. However, the skilled artisan will appreciate that other types of interconnects, such as ball grid arrays, land grid arrays or others can be used. The upper surface  120  of the circuit board  110  is populated with plural passive components  125 , which can be capacitors, resistors, inductors or others. 
       FIG. 1  depicts the back side  130  of the semiconductor chip  105  undergoing a laser treatment. A laser  140  is used to deliver laser pulses  145  to the back side  130 . The purpose of the laser treatment is to intentionally damage the semiconductor material at the back side  130  to create an amorphous region that will include various types of defects such as cracks, voids and others that act as a gettering region to attract various contaminants that may be present in the semiconductor chip  105 , such as copper, sodium, potassium, iron or others. The laser pulses  145  create ablation craters in the backside  130 . At this point a small group  150  of the ablation craters have been created. The parameters for the laser pulses  145  such as wave length, pulse duration, angle of incidence and others are selected to create by way of ablation and thermal expansion, the aforementioned intentionally damaged areas of the back side  130 . 
       FIG. 2  is an overhead view of the package substrate  100  and the semiconductor chip  105  showing the same features as  FIG. 1 . Note that just the small group  150  of the ablation craters has been created at this point. It should be understood that the small group  150  of ablation craters is not drawn to scale and may be much smaller than what is depicted in  FIGS. 1 and 2 . Note the location of the dashed rectangle  155  in  FIG. 2 , the dashed rectangle  155  surrounds the small group  150  of ablation craters and a portion of a corner of the semiconductor chip  105 . That portion of  FIG. 2  circumscribed by the dashed rectangle  155  will be shown at greater magnification in  FIG. 3 . 
     Attention is now turned to  FIG. 3 , which as just noted, is the portion of  FIG. 2  circumscribed by the dashed rectangle  155 . A corner portion of the semiconductor chip  105 , and in particular the upper surface  130  thereof, is depicted as well as a small portion of the circuit board  110  upon which the semiconductor chip  105  is mounted. The individual ablation craters  152   a ,  152   b ,  152   c ,  152   d ,  152   e  and  152   f  of the small group  150  of ablation craters have been ablated into the back side  130  of the semiconductor chip  105  using the laser pulses  145  described above. The dashed circle  160  represents the next targeted area of the backside  130  and the approximate size of the laser spot that will burn the next ablation crater. Although the laser spot that will hit the area at the dashed circle  160  is typically circular, the actual footprints of the ablation craters  152   a ,  152   b ,  152   c ,  152   d ,  152   e  and  152   f , while generally tracking the footprint of the laser spot, but will typically be somewhat irregular as shown due to the irregularities in the heating and ablation of the bask side  130  of the semiconductor chip  105 . The ablation craters  152   a ,  152   b ,  152   c ,  152   d ,  152   e  and  152   f  can be fabricated with some spacing x.sub.1 along an x axis and some spacing y.sub.1 along a y axis, where the x and y axes are just to conveniently describe directions. Smaller values for x.sub.1 and y.sub.1 yield more disruptions of the lattice structure and stronger gettering. Indeed, x.sub.1 and y.sub.1 could be set to zero to create, in essence, fewer, but larger ablation craters. Laser spot size and laser pulse length are chosen to yield some typical lateral dimension x.sub.2 of the ablation craters  152   a ,  152   b ,  152   c ,  152   d ,  152   e  and  152   f  In this exemplary arrangement, the dimension x.sub.2 can be about 100 to 1000 nm. 
     Additional details of the ablation craters  152   a ,  152   b  and  152   c  and the semiconductor chip  105  can be understood by referring now also to  FIG. 4 , which is a sectional view of  FIG. 3  taken at section  4 - 4 . Note that due to the location of section  4 - 4 , the three ablation craters  152   a ,  152   b  and  152   c  are visible. The following discussion of the ablation craters  152   a ,  152   b ,  152   c ,  152   d ,  152   e  and  152   f  will be illustrative of the others. The creation of each of the ablation craters  152   a ,  152   b  and  152   c  involves a combination of ablation of the semiconductor material of the chip  105  and in particular the back side  130  thereof and a rapid heating, which produces not only the ablation craters  152   a ,  152   b  and  152   c  but also rapid thermal expansion of the material of the chip  105  surrounding the craters  152   a ,  152   b  and  152   c . The ablation process will typically yield roughened sidewalls  163  and bottoms  164  of the ablation craters  152   a ,  152   b  and  152   c . Localized melting occurs at the sidewalls  163  and bottoms  164 . The melting, sputter evaporation and rapid thermal expansion produces a variety of structural defects in the semiconductor material of the semiconductor chip  105 , such as, cracks  165  and voids  170 . These cracks  165  and voids  170  disrupt the crystal lattice of the semiconductor material in the chip  105  producing, in essence, an amorphous region  175  which functions as a gettering region to attract impurities  180 , such as, copper or other impurities. The amorphous region  175  can consist of plural gettering regions, one proximate each of the ablation craters  152   a ,  152   b  and  152   c , or if spaced closely enough laterally, one expansive gettering region. The structure and position of the cracks  165  and  170  for each of the ablation craters  152   a ,  152   b  and  152   c  will be highly irregular in number, size and position. However, at least some of the structural defects emanate from the bottoms  164  of the ablation craters  152   a ,  152   b ,  152   c ,  152   d ,  152   e  and  152   f  When the laser pulse  145  strikes the next area to be burned, the aforementioned ablation plus rapid thermal expansion will occur. In this illustrative arrangement, the angle of incidence .PHI..sub.1=0.degree. (i.e., perpendicular) for the laser radiation  145 . However, as described in more detail below, other angles of incidence are envisioned. Laser spot size and laser pulse length are chosen to yield some typical average depth z.sub.1 of the ablation craters  152   a ,  152   b ,  152   c ,  152   d ,  152   e  and  152   f . The average depth z.sub.1 is an average depth since the bottoms  164  are not smooth, and are instead rough and irregular. The average depth z.sub.1 can be about 100 to 2000 nm. 
     Note that the semiconductor chip  105  can be electrically connected to the circuit board  110  by way of plural interconnects  195 , which can be solder bumps, micro bumps, conductive pillars, or other types of interconnect structures. Again, the circuit board  110  is depicted as a pin grid array with pin interconnects  115  but others can be used as well as described above. The semiconductor chip  105  includes an active or device region  190  populated with multitudes of circuit structures, such as transistors, capacitors, resistors and others. The device region  190  is electrically connected to the interconnect structures by multitudes of conductor structures not shown for simplicity of illustration. 
     The parameters for the laser energy  145  are selected to cause ablation and lattice disruption but without overheating or damaging the semiconductor chip  105  to an extent that would damage the device region  190 . The following table lists some exemplary laser ablation parameters assuming silicon as the material to be ablated: 
     
       
         
           
               
               
               
             
               
                   
                 TABLE 
               
               
                   
                   
               
             
            
               
                   
                 Laser Wavelength 
                 355 nm or 532 nm 
               
               
                   
                 Laser Spot Size 
                 100 to 1000 nm 
               
               
                   
                 Laser Pulse Duration 
                 &gt;15 nano seconds (ns) 
               
               
                   
                 Laser Pulses Per Ablation Crater 
                 1 to 3 
               
               
                   
                 Laser Energy Density 
                 10 9  to 10 11  J-cm 2   
               
               
                   
                 Laser Type 
                 Nd: YAG solid state 
               
               
                   
                   
               
            
           
         
       
     
     Conventional laser scribing uses a laser pulse duration that is shorter than the time it will take for the generated heat to flow to the surrounding silicon. This thermal conduction time is about 50 pico seconds (ps), so conventional laser scribing pulses are typically kept shorter than 50 ps to avoid damage to the silicon crystal structure. However, the disclosed laser ablation techniques seek to cause damage to the crystal structure in the semiconductor chip  105  near the ablation craters  152   a ,  152   b ,  152   c ,  152   d ,  152   e  and  152   f . Accordingly, the laser pulse duration is much longer than the conventional scribing technique, but not so long as to cause damage to the active region  190 . The parameters in the table above can be varied while maintaining the technical objective of causing structural damage to create the gettering region  175  and the disclosed alternative gettering regions without harming the functionality of the chip  105  and the disclosed alternative chips. 
     As noted above, various values for average depths z.sub.1 can be used for the ablation craters  152   a ,  152   b ,  152   c ,  152   d ,  152   e  and  152   f . In this illustrative arrangement, all the ablation craters  152   a ,  152   b ,  152   c ,  152   d ,  152   e  and  152   f  are subjected to the same pulse duration and energy and thus have approximately the same average depth z.sub.1. It should be understood that the creation of the ablation craters  152   a ,  152   b ,  152   c ,  152   d ,  152   e  and  152   f  and additional ablation craters can span the entire back side  130  of the semiconductor chip  105  or some subset thereof as desired. 
       FIG. 5  is a sectional view like  FIG. 4 , but depicting an alternate exemplary laser treatment. Here, the semiconductor chip  105  subjected to the irradiation by the laser pulses  145  but at some angle of incidence .PHI..sub.2, which is non-zero to create ablation craters  252   a ,  252   b  and  252   c , which have slanted side walls  263  and generally horizontal bottoms  264 . The creation of the ablation craters  252   a ,  252   b  and  252   c  and additional ablation craters, as in the other disclosed arrangements, creates the aforementioned defects such as cracks  165  and voids  170 , some of which emanate from the bottoms  264 , and thereby establishes an amorphous gettering region  275  to attract the contaminant particles  180 . It is anticipated that .PHI..sub.2 can be virtually any angle greater than zero and less than about 60.degree. 
     In the arrangement illustrated in  FIG. 5 , the ablation craters  252   a ,  252   b  and  252   c  are all created using the laser energy  145  at the same angle of incidence .PHI..sub.2. However, the skilled artisan will appreciate that other techniques can be used. For example, and as shown in  FIG. 6 , which is a sectional view like  FIG. 5 , a semiconductor chip  305  can be subjected to laser treatment with laser pulsed  145 . Here one laser pulse  145  is directed at some angle of incidence .PHI..sub.2 to the semiconductor chip  305  to create an ablation crater  352   a  with a tilt that roughly matches .PHI..sub.2 and thereafter another laser pulse  145  is directed at some angle of incidence −.PHI..sub.2 to the semiconductor chip  305  to create an adjacent ablation crater  352   b  with a tilt of roughly −.PHI..sub.2 and so on and so forth across the backside  330  of the semiconductor chip  305  again with the goal of creating the aforementioned cracks  165 , voids  170  and other defects, some of which emanate from the bottoms  364 , to establish an amorphous gettering region  375  that attracts impurities  180 . 
       FIGS. 7 and 8  depict in pictorial form a few of the alternative methods and arrangements envisioned by the present detailed disclosure. Turning first to  FIG. 7 , therein is depicted a pictorial view of a portion of a semiconductor chip  405  that can be like the chip  105  or other alternative arrangements disclosed herein. Note that only a small portion of the chip  405  is depicted. As shown in  FIG. 7 , the laser  140  can be controlled to do a variety of variations of spot size and spot size positioning.  FIG. 7  depicts four laser spots  460   a ,  460   b ,  460   c  and  460   d . Each of the laser spots  460   a ,  460   b ,  460   c  and  460   d  represents the laser spot size and the laser target location on the chip  405 . For example,  FIG. 7  shows one laser spot size  460   a  with some diameter d.sub.1 and next door another possible laser spot size  460   b  with some diameter d.sub.2 that is smaller than d.sub.1. The point here is that spot sizes  460   a  or  460   b  can be varied to achieve different sizes of ablation craters and spacings of ablation craters if desired.  FIG. 7  also depicts another variation where a couple of other laser spots  460   c  and  460   d  are overlapped. This illustrates that the laser  140  can be manipulated so that a given laser spot, for example  460   c , is positioned as shown and then the next laser spot  460   d  is targeted to laterally overlap where the laser spot  460   c  hit in order to fabricate overlapping ablation craters. The overlapping can be with more than just one laser spot overlapping at a time to achieve ablation craters that overlap one another at multiple locations etc. Another technique that can be employed is to use different energies for different locations. For example, the laser spot  460   a  can be delivered to the chip  405  with some energy level and another or other laser spot, such as the laser spot  460   b , can be delivered to the chip  405  at some other energy, lower or higher, as desired. 
     Attention is now turned to  FIG. 8 , which is a pictorial view of a small portion of another semiconductor chip  505 . Here, a spherical coordinate system  507  is overlaid on the chip  505  and used to illustrate that the laser  140  can be rotated in spherical coordinates about angles .PHI. and .THETA. to achieve a variety of different aiming points and angular orientations of a given ablation crater, one of which is shown, and labeled  552   a . Thus, for example, the laser  140  can be positioned according to some angles .PHI. and .THETA. and fired such that the laser pulse  145  creates the ablation crater  552   a  with a certain side wall slope and azimuthal orientation. Then, either the laser  140  or the chip  505  itself can be rotated through some other azimuthal angle .THETA. and another pulse delivered to generate another ablation crater with or without altering the inclination angle .PHI.. In other words, the chip  505  can be blasted with the laser pulses  145  from a variety of angular positions .PHI. and .THETA. of the laser  140  to achieve a great variety of different types of texturing of the semiconductor chip  505 . As noted above, operation of the laser  140  can be tailored to yield laterally overlapping craters, such as the overlapping craters  552   b  and  552   c.    
     In yet another arrangement depicted in  FIG. 9 , which is a sectional view like  FIG. 6 , a semiconductor chip  605  can undergo laser treatment with laser pulses  145  to produce ablation craters  652   a ,  652   b  and  652   c  that have different average depths z.sub.1, z.sub.2, z.sub.3 where z.sub.1 is greater than z.sub.2, and z.sub.2 is greater than z.sub.3, etc. across the upper surface  630  of the chip  605 . This can be accomplished by way of either changing the wave length of the laser  145  or using short successively shorter pulses in order to achieve shallower ablation craters  652   a ,  652   b  and  652   c  say at average depths z.sub.2 and z.sub.3 relative to z.sub.1, etc. This type of treatment can be beneficial where a particular portion of the semiconductor chip  605  is more sensitive to excessive heating than others and therefore shallower craters  652   c  can be created in those sensitive zones. Again, the goal is to by way of ablation and rapid thermal expansion to create the aforementioned defects  165  and  170 , some of which emanate from the bottoms  664 , which make up the gettering region  675  of the chip  605 . Of course the techniques illustrated in  FIG. 9  could be combined with non-zero angles of incidence .PHI..sub.2 and/or −.PHI..sub.2 for the laser pulses  145  such as that depicted in  FIGS. 5 and 6 . 
       FIG. 10  is an overhead view depicting the fully treated semiconductor chip  105  which has an intentionally damaged and highly textured backside  130 . As noted above, while the entirety of the backside  130  can be subjected to laser treatment, in other arrangements, only sub-sets of the backside  130  need undergo laser treatment. 
       FIG. 11  depicts a pictorial view of the semiconductor chip package  100  following the laser treatment of the semiconductor chip  105  thereof. With the chip laser treated, a thermal interface material  723  can be applied to the semiconductor chip  105  and of course any of the disclosed alternatives to facilitate the subsequent mounting of a heat spreader or sink (not shown) on the semiconductor chip  105 . The thermal interface material  723  is advantageously composed of a variety of organic materials such as silicone, with or without conductive fillers such as silver or other particles or other types of thermal greases. 
     The disclosed arrangements utilize laser treatments on the semiconductor chips  105 ,  205 ,  305 , etc. at the package stage. However, it should be understood that the laser treatment could be performed before or after the chips  105 ,  205 ,  305 ,  405 ,  505 ,  605  etc. are singulated from larger workpieces, such as wafers, but before they are mounted on a package or other type of circuit board. 
     While the invention may be susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and have been described in detail herein. However, it should be understood that the invention is not intended to be limited to the particular forms disclosed. Rather, the invention is to cover all modifications, equivalents and alternatives falling within the spirit and scope of the invention as defined by the following appended claims.