Patent Publication Number: US-6342415-B1

Title: Method and system for providing reduced-sized contacts in a semiconductor device

Description:
FIELD OF THE INVENTION 
     The present invention relates to semiconductor devices, more particularly to a method and system for reducing charge gain and charge loss due to contacts in semiconductor devices, such as a flash memory device. 
     BACKGROUND OF THE INVENTION 
     A conventional semiconductor device, such as a memory, includes a large number of cells, which are typically floating gate devices such as floating gate transistors. For example, FIG. 1 depicts a portion of a conventional semiconductor device  10 . The semiconductor device  10  includes cells  20 ,  30 , and  40  formed on a substrate  11 . Each cell includes a gate stack  21 ,  31  and  41 . Each gate stack  21 ,  31  and  41  includes a floating gate  22 ,  32  and  42 , respectively, and a control gate  24 ,  34  and  44 , respectively. The cells  20 ,  30  and  40  also include drains  29  and  39  and sources  19  and  49 . As depicted in FIG. 1, the cells  20  and  40  share a common drain  29 , while the cells  20  and  30  share a common source  19 . Typically, each cell  20 ,  30  and  40  also includes spacers  26  and  28 ,  36  and  38 , and  46  and  48 , respectively. 
     In order to make electrical contact to one or more of the cells  20 ,  30  and  40 , a conventional electrical contact  52  is provided. The conventional contact  52  is provided within a conventional contact hole  50 . The conventional contact hole  50  is provided in an insulating layer  54  which otherwise covers the cells  20 ,  30  and  40 . The insulating layer  54  insulates the cells  20 ,  30  and  40 . The conventional contact hole  50  is filled with a conductive material to form the conventional contact  52 . 
     Although the conventional semiconductor device  10  functions, one of ordinary skill in the art will readily realize that the conventional semiconductor device  10  is subject to unanticipated charge gain and charge loss because of the spacing of the contact  52  from a particular cell, such as the cell  20 . The current trend in semiconductor technology is toward higher densities. In order to reduce the space occupied by a given conventional semiconductor device  10 , the components of the semiconductor device are more densely packed and made smaller. Thus, the cells  20 ,  30  and  40  and the conventional contact  52  are relatively close. The thickness of the spacers  26  and  28 ,  36  and  38  and  46  and  48  is between approximately one thousand and two thousand Angstroms. The conventional contact  52  is approximately 0.28 to 0.4 μm wide. However, in general, it is difficult to provide conventional contacts  52  which are less than 0.28-0.3 μm wide. For example, in some conventional technology, the widths of the conventional contacts  52  are centered around 0.28 μm. This distance is approximately the smallest that an aperture in a photoresist mask (not shown) can be made using conventional photolithographic techniques. The photoresist mask is used in forming the conventional contact hole  50  by etching the underlying areas of the insulating layer  54 . The conventional contact  52  is also closely spaced to neighboring cells  20 ,  30  and  40 . In particular, the distance between the base of the conventional contact  52  and the edge of a nearest gate in a gate stack, such as the gate stack  21 , is very small. In some cases, the distance between the gate stack and the contact may be between 0.15 and 0.3 μm. 
     The small spacing between the conventional contact  52  and the gate stack of particular cell, such as the cell  20 , causes unanticipated charge gain and charge loss from the cell  20 . Because the conventional contact  52  is typically separated from the edge of the gate stack  21  by such a small distance, the portion of the insulating layer  54  between the conventional contact  52  and the gate stack  21  is very thin. The combination of the spacer  26  and the insulating layer  54  may not provide sufficient insulation to prevent the gate stack  21  from being electrically coupled to the conventional contact  52  through the spacer  26  and insulating layer  54 . For example, charge on the conventional contact  52  may travel to the gate stack  21  when a user does not desire the floating gate  22  to store charge. Similarly, a charge stored on the floating gate  22  may travel to the conventional contact  52 . Thus, a charge intentionally stored on the floating gate  22  may bleed away. Consequently, the cell  20  is subject to unanticipated charge gain and charge loss. As a result, the cell  20  may not function as desired. 
     Accordingly, what is needed is a system and method for providing contacts in a semiconductor device which has reduced charge gain and charge loss. The present invention addresses such a need. 
     SUMMARY OF THE INVENTION 
     The present invention provides a method and system for providing a contact in a semiconductor device including a plurality of gates. The method and system comprise providing an insulating layer substantially surrounding at least a portion of the plurality of gates and providing at least one contact within the insulating layer. The at least one contact has a reduced width of less than approximately 0.28 μm. 
     According to the system and method disclosed herein, the present invention provides a greater spacing between the contact and the closest gate stack without increasing the spacing between gate stacks or between the center of the contact and the gate stack. Consequently, a higher density of devices can be achieved while reducing the charge gain and charge loss through the contact. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a diagram of a conventional semiconductor device 
     FIG. 2 is a diagram of a semiconductor device including a contact in accordance with the present invention. 
     FIG. 3A is a flow chart depicting one embodiment of a method for providing a semiconductor device in accordance with the present invention. 
     FIG. 3B is a flow chart depicting one embodiment of a method for providing the contact in accordance with the present invention. 
     FIG. 3C is a flow chart depicting one embodiment of a method for providing the contact hole in accordance with the present invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The present invention relates to an improvement in semiconductor processing. The following description is presented to enable one of ordinary skill in the art to make and use the invention and is provided in the context of a patent application and its requirements. Various modifications to the preferred embodiment will be readily apparent to those skilled in the art and the generic principles herein may be applied to other embodiments. Thus, the present invention is not intended to be limited to the embodiment shown, but is to be accorded the widest scope consistent with the principles and features described herein. 
     A conventional semiconductor device, such as a flash memory, includes a large number of cells, which are typically floating gate devices such as floating gate transistors. The cells also include sources and drains. Typically, each cell also includes spacers. In order to make electrical contact to the source or drain of one or more of the cells, a conventional contact hole is filled with a conductive material to provide a conventional contact. The conventional contact hole is provided in a conventional insulating layer that may otherwise cover and insulate the cells. 
     Although the conventional semiconductor device functions, one of ordinary skill in the art will readily realize that the conventional semiconductor device is subject to unanticipated charge gain and charge loss because of the spacing of the contact and a nearest cell. The cells and conventional contacts of a conventional semiconductor device are relatively close. In addition, the width of the conventional contacts is limited by conventional photolithographic techniques to between about 0.28 μm and 0.4 μm. Furthermore, conventional contacts having widths of less than 0.28-0.3 μm are difficult to produce. Thus, the distance between the base of the conventional contact and the edge of nearest gates of a gate stack is very small. The small spacing between the conventional contact and the gate stack causes undesirable charge gain and charge loss from the cell. Because the conventional contact is typically separated from the edge of the nearest gate stack by such a small distance, the portion of the insulating layer and any spacer between the conventional contact may allow charge stored on the cell to travel to the contact, thereby bleeding away. For similar reasons, a charge on the contact may travel to the nearest cell. Consequently, the cell is subject to unanticipated charge gain and charge loss. As a result, the semiconductor device may malfunction, which is undesirable. 
     The present invention provides a method and system for providing a contact in a semiconductor device including a plurality of gates. The method and system comprise providing an insulating layer substantially surrounding at least a portion of the plurality of gates and providing at least one contact within the insulating layer. The at least one contact has a reduced width that is less than approximately 0.28 μm. 
     The present invention will be described in terms of a particular device having certain components and particular techniques for performing certain steps. However, one of ordinary skill in the art will readily recognize that this method and system will operate effectively for other devices having other components and other techniques. Furthermore, the present invention will be described in terms of a particular semiconductor memory device. However, nothing prevents the method and system from being utilized with another semiconductor device. 
     To more particularly illustrate the method and system in accordance with the present invention, refer now to FIG. 2, depicting one embodiment of a semiconductor device  100 , such as a memory, including a contact in accordance with the present invention. The semiconductor device  100  includes a number of cells  120 ,  130  and  140 , which are typically floating gate devices such as floating gate transistors. Each cell  120 ,  130  and  140  includes a gate stack  121 ,  131  and  141 . Each gate stack  121 ,  131  and  141  includes a floating gate  122 ,  132  and  142 , respectively, and a control gate  124 ,  134  and  144 , respectively. The cells  120 ,  130  and  140  also include drains  129  and  139  and sources  19  and  149 . The cells  120  and  140  are depicted as sharing a common drain  129 , while the cells  120  and  130  are depicted as sharing a common source  119 . Typically, each cell  120 ,  130  and  140  also includes spacers  126  and  128 ,  136  and  138 , and  146  and  148 , respectively. Preferably, the spacers  126 ,  128 ,  136 ,  138 ,  146  and  148  are approximately one thousand to two thousand Angstroms thick. 
     In order to make electrical contact to one or more of the cells  120 ,  130  and  140 , an electrical contact  152  in accordance with the present invention is used. The electrical contact  152  is provided within a contact hole  150  in accordance with the present invention. The contact hole  150  is provided in an insulating layer  154  which otherwise covers the cells  120 ,  130  and  140 . The insulating layer  154  insulates the cells  120 ,  130  and  140 . The contact hole  150  is filled with a conductive material to form the contact  152 . 
     The contact hole  150  and, therefore, the contact  152  have a reduced with that is less than approximately 0.28 μm. In a preferred embodiment, the width of the contact hole  150  and the contact  152  is greater than approximately 0.2 μm and less than approximately 0.25 μm. It is currently believed that such a width will provide a greater distance to the nearest gate stack  121  while maintaining a contact resistance that is sufficiently low to allow the contact  152  to function. In a preferred embodiment, the distance between the base of the contact hole and the nearest gate stack, such as the gate stack  121 , has increased by 0.05-0.1 μm. 
     Because the contact  152  has a reduced width, the edge of the contact  152  is separated from the edge of the nearest gate stack  121  by a greater distance than in the conventional semiconductor device  10  depicted in FIG.  1 . Referring to FIG. 2, because the edge of the contact  150  is a greater distance from the edge of the gate stack  121 , there is more of the insulating layer  154  between the contact  152  and the edge of the gate stack  121 . As a result, the insulating layer  154  is better able to electrically insulate the contact  152  from the edge of the gate stack  121 . In a preferred embodiment, there is sufficient insulation to electrically insulate the contact  152  from the gate stack  121 . Consequently, charge intentionally stored by the memory cell  120 , for example on the floating gate  122 , is much less likely to travel through the insulating layer  154  to the contact  152 . Similarly, charge on the contact  152  is much less likely to travel through the insulating layer to the gate stack  121 . As a result, unwanted charge gain and charge loss may be reduced or eliminated in a semiconductor device which has components relatively densely packed. 
     FIG. 3A depicts one embodiment of a method  200  for providing a semiconductor device in accordance with the present invention. The memory cells  120 ,  130  and  140  are provided, via step  202 . In a preferred embodiment, step  202  includes at least providing the gate stacks  121 ,  131 , and  141 . Step  202  may also include providing the spacers  126 ,  128 ,  136 ,  138 ,  146 , and  148 . The insulating layer  154  is then provided on the cells  120 ,  130  and  140 , via step  204 . One or more contacts  152  having a reduced width of less than 0.28 μm, such as the contact  152 , are then provided, via step  206 . In a preferred embodiment, the width of the contact hole  150  and the contact  152  is greater than approximately 0.2 μm and less than approximately 0.25 μm. It is currently believed that such a width will provide a greater distance to the nearest gate stack  121  while maintaining a contact resistance that is sufficiently low to allow the contact  152  to function. Also in a preferred embodiment, the edges of the contacts  152  provided in step  206  will be separated from the closest edge of the nearest gate stack by 0.05-0.1 μm more than in the conventional semiconductor device  10  shown in FIG.  1 . Referring back to FIG. 3A, because the contacts  152  provided in step  206  have a reduced width, more of the insulating layer  154  lies between the contacts  152  and the nearest gate stack  120  without altering the spacing of the center of the contacts  152  from the center of the memory cells  120 ,  130  and  140 . Thus, there is a smaller likelihood of unanticipated charge gain or charge loss without otherwise reducing the density of components of the semiconductor device  100 . 
     FIG. 3B depicts one embodiment of a method  210  for performing the step  206  of providing contacts  152  having reduced widths. One or more contact holes  150  having reduced widths are provided in the insulating layer  154 , via step  212 . The contact hole  150  is filled with a conductive material to form a contact  152  having a reduced width, via step  214 . 
     FIG. 3C depicts one embodiment of a method  220  for performing the step  210  of providing the contact hole(s) having a reduced width. An antireflective coating is provided on the insulating layer  154 , via step  222 . A resist structure having apertures above the desired positions of the contact holes is provided, via step  224 . The resist structure is provided using ultraviolet light using a phase shift mask. In one embodiment, light having a wavelength of approximately  248  nm is used in conjunction with a phase shift mask. In a preferred embodiment, the apertures in the resist structure are approximately the same size as the desired size of the contact hole  150 . The etch for the contact hole  150  is then performed, via step  226 . In a preferred embodiment, the contacts are etched using a C4F 8 /O 2 /Ar etch chemistry. The method  220  ensures that the contact hole  150  and, therefore, the contact  152  will have a reduced width. In a preferred embodiment, the width of the contact hole  150  and the contact  152  is between approximately 0.2 μm and 0.28 μm. Thus, the components of the semiconductor device  100  can be more densely packed without suffering from the undesirable and unanticipated charge gain or charge loss. 
     A method and system has been disclosed for providing a contact having a reduced size. Although the present invention has been described in accordance with the embodiments shown, one of ordinary skill in the art will readily recognize that there could be variations to the embodiments and those variations would be within the spirit and scope of the present invention. Accordingly, many modifications may be made by one of ordinary skill in the art without departing from the spirit and scope of the appended claims.