Patent Publication Number: US-2011073922-A1

Title: Contact forming method, semiconductor device manufacturing method, and semiconductor device

Description:
TECHNICAL FIELD 
     This invention relates to a MIS-type semiconductor device widely used in an IC, LSI, and the like and, in particular, to formation of a low-resistance contact between a highly-concentrated Si portion and a metal silicide in a source region and a drain region. 
     BACKGROUND ART 
     In a semiconductor device, it is strongly desired to achieve improvement in performance, such as improvement in operating frequency. However, in the semiconductor device, the improvement in performance is prevented by a series resistance between two main electrodes through which an electric current flows mainly. As a significant factor of the series resistance, a contact resistance between a highly-concentrated Si (silicon) layer and a metal silicide in a source region and a drain region is recognized. According to performance prediction by ITRS (International Technology Roadmap for Semiconductor) of the 2007 edition, it is shown that a current contact resistivity is 1×10 −7  Ωcm 2  and a predicted value for 2010 is 7.0×10 −8  Ωcm 2 . At present, however, a manufacturing method for achieving a low contact resistance has not yet been established. 
     Non-Patent Document 1 describes that the contact resistance must be reduced. 
       FIG. 1  shows a contact resistivity dependence of a saturation current in a MIS (Metal Insulator Semiconductor) transistor. It is understood that, if the contact resistivity is 1×10 −7  Ωcm 2  according to a conventional technique, only about 35% of original capacity of the transistor is extracted. 
     It is known that a contact resistance Rc between the highly-concentrated Si layer and metal/metal silicide is represented by the following Formula (I). 
     
       
         
           
             
               
                 
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     In Formula (I), R c  is the contact resistance between the highly-concentrated Si layer and the metal/metal silicide, φ b  is a work function difference between the highly-concentrated Si layer and the metal/metal silicide, m n  is an electron effective mass, m p  is a hole effective mass, n is an electron density in an n +  region, p is a hole density in a p +  region, ε s  is a permittivity of silicon, and h is a Planck&#39;s constant. 
     As apparent from Formula (I), as a method of reducing the contact resistance Rc, it is essential to reduce the work function difference between the highly-concentrated Si layer and the metal silicide and to maximize an impurity concentration of the highly-concentrated Si layer. 
     PRIOR ART DOCUMENTS 
     Non-Patent Documents 
     
         
         Non-Patent Document 1: Tadahiro Ohmi, Akinobu Teramoto, Rihito Kuroda, and Naoto Miyamoto, “Revolutional Progress of Silicon Technologies Exhibiting Very High Speed Performance Over a 50-GHz Clock Rate”, IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 54, NO. 6, pp. 1471-1477, June 2007 
         Non-Patent Document 2: Hajime Kumami, Wataru Shindo, Satoshi Hondo, Tadahiro Ohmi, “Plasma-Induced Dopant (As, P, Sb, B) Deactivation by Low-Energy Ion Irradiation during Silicon Epitaxial Growth”, The Institute of Electronics, Information and Communication Engineers, Vol. 99, No. 231, Silicon Materials and Devices, ED99-97, SDM99-71, ICD99-79, pp. 97, 1999 
       
    
     SUMMARY OF THE INVENTION 
     Problem to be Solved by the Invention 
     However, in a case of a p-type MOS (Metal Oxide Semiconductor) transistor, there is a problem that, in a conventional process, B (boron) used in the highly-concentrated Si layer is easily deactivated by a plasma damage due to ion irradiation during manufacture of a semiconductor device (See Non-Patent Document 2). The reason is as follows. As shown in  FIG. 2 , B is a trivalent atom and originally has covalent-bonding hands smaller in number by one with respect to Si to be covalently bonded. Furthermore, B has an atomic radius smaller than that of Si so that an atomic distance becomes long. Therefore, a coulomb force for covalent bonding is reduced. 
     Accordingly, in the conventional technique, even by the use of a metal silicide having a small work function difference with respect to the highly-concentrated Si layer, deactivation of a highly-concentrated Si region is unavoidable. Therefore, it is not possible to maximize an impurity concentration of the highly-concentrated Si layer. Thus, in the conventional technique, it has been difficult to reduce a resistivity at the contact. 
     Further, with the miniaturization of the semiconductor device, it is required to achieve expansion of the highly-concentrated Si layer in the source region and the drain region and ultra-shallow junction depth. It is noted here that, upon silicidation, in a case of a metal material requiring a high consumption of silicon, the highly-concentrated Si layer may be entirely silicided as a result of silicide formation to cause disruption of the junction. Accordingly, in the conventional technique, it is difficult to achieve the expansion of the highly-concentrated Si layer and the ultra-shallow junction depth. 
     It is therefore an object of the present invention to provide a contact forming method capable of increasing an impurity concentration by minimizing deactivation of impurities due to plasma damage of a highly-concentrated impurity layer in a contact region. 
     It is another object of the present invention to provide a semiconductor device having a low-resistivity contact formed of a metal silicide having a composition comprising a greater content of a metal with respect to Si. 
     Means to Solve the Problem 
     According to a first aspect of the invention, it can be provided a method of forming a contact to a source region and a drain region of a semiconductor device. The method forms a metal film for the contact without performing heat treatment after ion implantation for forming a highly-concentrated Si layer and performs one or both of activation of the highly-concentrated Si layer and silicidation by subsequent heat treatment. 
     According to a second aspect of the invention, it can be provided a semiconductor device manufacturing method including the steps of ion-implanting a p-type or an n-type impurity into a Si layer portion to become a p-type or an n-type contact region of a semiconductor device, forming a metal film for a contact on a surface of the contact region without performing heat treatment for activating the implanted ions after the ion-implanting step, and forming a silicide of a metal of the metal film by causing the metal to react with the Si layer portion by heating. 
     According to a third aspect of the invention, it can be provided a semiconductor device manufacturing method including the steps of ion-implanting a p-type or an n-type impurity into a Si layer portion to become a p-type or an n-type contact region of a semiconductor device to amorphize a surface of the Si layer portion, forming a metal film for a contact on a surface of an amorphous Si portion, and forming a silicide of a metal of the metal film by causing the metal to react with the amorphous Si portion by heating. 
     In the first through third aspects, it is preferable that a metal of the metal film for a contact is a metal adapted to form a silicide having a work function difference of not greater than 0.3 eV with respect to the highly-concentrated Si layer or a Si layer and it is desirable that a metal of the metal film for a contact is at least one of palladium, cobalt, nickel, rhodium, rhenium, osmium, iridium, platinum, and gold. 
     In the first through third aspects, it is preferable that the method further includes a step of activating, by heat treatment after the metal film is formed, ions implanted by the ion implantation. In this case, it is desirable that the silicide forming step and the activating step are performed at the same time. 
     Further, the contact region may be a source or a drain region of a field-effect transistor. It is desirable that the contact region is a p-type region and that a p-type impurity ion-implanted into the contact region is boron. It is also desirable that the metal is palladium. 
     According to a fourth aspect of the invention, it can be provided a semiconductor device having a source region and a′drain region each formed of Si, a contact portion to at least one of the source region and the drain region containing a silicide of a predetermined metal, the metal forming the silicide is a metal such that the silicide has a composition comprising a greater content of the metal with respect to Si. 
     In the semiconductor device, it is desirable that the predetermined metal is palladium and the silicide is Pd 2 Si with a (104) surface. 
     EFFECT OF THE INVENTION 
     According to the present invention, it is possible to increase an impurity concentration by avoiding deactivation of a highly-concentrated impurity region at a contact portion. Therefore, a resistivity at the contact can be reduced. 
     Further, according to the present invention, palladium requiring a low consumption of silicon Si is used in silicidation. Therefore, it is possible to prevent disruption of a junction as a result of silicide formation and to enable expansion of the highly-concentrated Si layer in a source region and a drain region and ultra-shallow junction depth. Thus, miniaturization of a semiconductor device can be accomplished. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a view showing a contact resistivity dependence of a saturation current in a MIS transistor. 
         FIG. 2  is a schematic diagram of silicon crystals and a view for describing a coulomb force. 
         FIG. 3  shows X-ray analysis reciprocal lattice space mapping images when palladium is deposited on a Si (100) surface and heat treatment is executed at different temperatures to perform silicidation. 
         FIG. 4  shows X-ray analysis reciprocal lattice space mapping images when palladium is deposited on a Si (110) surface and heat treatment is executed at different temperatures to perform silicidation. 
         FIG. 5  shows X-ray analysis reciprocal lattice space mapping images when palladium is deposited on a Si (551) surface and heat treatments executed at different temperatures to perform silicidation. 
         FIG. 6  is a schematic diagram of a CMOS which is a first embodiment of the present invention and which is obtained by using shallow trench isolation, two-layer wiring, and chemical mechanical polishing. 
         FIG. 7  is a view for describing a part of a manufacturing process for obtaining the CMOS in  FIG. 6 . 
         FIG. 8  is a view for describing the rest of the manufacturing process subsequent to  FIG. 7 . 
         FIG. 9  is a schematic diagram of a Kelvin resistance for contact resistivity evaluation, which is a second embodiment of the present invention. 
         FIG. 10  is a view showing a current-voltage characteristic of the Kelvin resistance for contact resistivity evaluation, which is the second embodiment of the present invention. 
         FIG. 11  is a view showing a current-voltage characteristic of a Kelvin resistance manufactured by a conventional manufacturing method. 
     
    
    
     EMBODIMENT FOR CARRYING OUT THE INVENTION 
     In a recent semiconductor device, due to a series resistance in a highly-concentrated layer region and a contact region connected between main electrodes, it is difficult to achieve high performance in electric current driving ability. The reason is as follows. During manufacture of a semiconductor device using the plasma technique, due to influence of plasma, such as ion damage, deactivation of impurities in a highly-concentrated layer is caused to occur to increase the series resistance. Further, in order to reduce a resistance in the contact region, it is required to reduce a work function difference between silicon Si and a metal silicide. Furthermore, in miniaturization of the semiconductor device, it is desired to use, for a metal silicide used in the contact region, a metal material requiring a low consumption of silicon so as to provide a composition comprising a greater content of a metal with respect to silicon. 
     In an embodiment of the present invention which will be described hereinbelow, a process is executed which uses a contact material suitable for forming the metal silicide having a small work function difference with respect to the highly-concentrated Si layer and having a composition comprising a greater content of a metal with respect to Si and which is capable of suppressing deactivation of impurities in the highly-concentrated layer. 
     First Embodiment 
       FIGS. 3 to 5  show X-ray analysis reciprocal lattice space mapping images when palladium is deposited on each of Si (100), Si (110), and Si (551) surfaces and heat treatment is executed at different temperatures to perform silicidation. It is understood that, in any of  FIGS. 3 to 5 , as the temperature is increased, Pd 2 Si of a composition comprising a greater content of a metal with respect to Si is formed and that a surface orientation is changed from a (001) surface to a (401) surface. Table 1 shows a work function difference (unit being eV) with respect to p-type Si in this case. It is understood that, by achieving the (401) surface of Pd 2 Si, a work function difference of substantially not greater than 0.3 eV is achieved regardless of a surface orientation of Si. 
     
       
         
           
               
               
               
               
               
               
             
               
                   
                 TABLE 1 
               
               
                   
                   
               
               
                   
                 as-depo 
                 300° C. 
                 400° C. 
                 500° C. 
                 600° C. 
               
               
                   
                   
               
             
            
               
                   
               
            
           
           
               
               
               
               
               
               
            
               
                 (100) 
                 Pd 
                 Pd 2 Si 
                 Pd 2 Si 
                 Pd 2 Si 
                 Pd 2 Si 
               
               
                   
                 0.299 eV 
                 0.341 eV 
                 0.340 eV 
                 0.300 eV 
                 0.290 eV 
               
               
                 (110) 
                 Pd 
                 Pd + Pd 2 Si 
                 Pd 2 Si 
                 Pd 2 Si 
                 Pd 2 Si 
               
               
                   
                 0.306 eV 
                 0.347 eV 
                 0.342 eV 
                 0.343 eV 
                 0.302 eV 
               
               
                 (551) 
                 Pd 
                 Pd + Pd 2 Si 
                 Pd 2 Si 
                 Pd 2 Si 
                 Pd 2 Si 
               
               
                   
                 0.302 eV 
                 0.347 eV 
                 0.341 eV 
                 0.341 eV 
                 0.287 eV 
               
               
                   
               
            
           
         
       
     
       FIG. 6  shows a schematic diagram of a CMOS which is a first embodiment of the present invention and which is obtained by shallow trench isolation (STI), two-layer wiring, and chemical mechanical polishing (CMP). 
     A manufacturing process for obtaining a structure in  FIG. 6  will be described using  FIGS. 7 and 8 . 
     First, referring to  FIG. 7 , device isolation regions  1  are formed by a STI structure like in a conventional method and an n-well  2  and a p-well  3  are formed and activated. Thereafter, as a gate insulating film  4 , a silicon oxide film is formed to a thickness of 2 nm. On the silicon oxide film, gate electrodes  5  are formed of polysilicon. 
     Next, in order to form a p +  region  6  for the n-well  2  and to form an n +  region  7  for the p-well  3 , boron and phosphorus are ion-implanted into the n-well  2  and the p-well  3  at a dose of 6×10 15  cm 2  to form the highly-concentrated regions  6  (p +  region) and 7 (n +  region) of 20 nm, respectively.  FIG. 7  shows a schematic diagram of this state. 
     In the conventional method, heat treatment is then performed for the purpose of activation of the highly-concentrated regions  6  and  7 . However, in the process of the present invention, without performing the heat treatment at this stage, an oxide film is deposited by CVD (Chemical Vapor Deposition) and etching is performed to form sidewalls  8  as shown in  FIG. 8 . After the sidewalls  8  are formed, palladium is deposited to a thickness of 20 nm as a contact metal to the highly-concentrated regions  6  and  7  and the gate electrodes  5 . 
     In the present embodiment, heat treatment is then performed in a nitrogen atmosphere at 550° C. for 1 hour to simultaneously achieve not only silicidation (formation of a contact silicide layer  9 ) but also activation of the highly-concentrated layers  6  and  7 , which is not performed before. Because of the heat treatment at a low temperature, diffusion of the highly-concentrated regions can be prevented. At this time, Pd 2 Si is formed by silicidation only at a base having a thickness of 13.6 nm, consuming silicon of the highly-concentrated layers  6  and  7 . A schematic diagram of this state is shown in  FIG. 8 . 
     Subsequently, unreacted metal portions  10  are removed in a manner similar to the conventional method. As shown in  FIG. 6 , interlayer insulating films  11  and  12  are formed, contact holes are formed and electrodes  13  and wirings  14  are formed of aluminum to reach completion. In  FIG. 6 , one of the highly-concentrated layers  6  and  7  is a source (S) and the other of the highly-concentrated layers  6  and  7  is a drain (D). 
     As described above, after ion implantation for forming the highly-concentrated layers is performed, a metal film is formed without performing heat treatment for activating impurities. Thereafter, by heat treatment, formation of the highly-concentrated Si layers by impurity activation and formation of the metal silicide are performed at the same time. Thus, a transistor is formed which has a work function difference of not greater than 0.3 eV and which achieves a contact resistivity of 8.0×10 −10  Ωcm 2 . 
     Second Embodiment 
       FIG. 9  shows a schematic diagram of a Kelvin resistance for contact resistivity evaluation, which is a second embodiment of the present invention. Boron is ion-implanted at a dose of 6×10 15  cm 2  into a device region  31  of a Si (100) surface to form a highly-concentrated p region  32 . Thereafter, without performing heat treatment, an interlayer insulating film  33  is formed. Subsequently, in the interlayer insulating film  33 , a contact hole  34  for exposing a contact region is formed. Thereafter, as a metal film, palladium is deposited to 20 nm. Heat treatment is performed in a nitrogen gas atmosphere at 550° C. for 3 hours to form a highly-concentrated Si layer  32  by impurity activation and to form a metal silicide  35 . At this time, the metal silicide  35  thus formed is Pd 2 Si having a composition comprising a greater content of a metal with respect to Si and has a film thickness of 14 nm, a (104) surface as a surface orientation, and a work function difference of not greater than 0.3 eV with respect to p-type Si. Thereafter, an electrode/wiring  36  is formed of aluminum to reach completion. 
       FIG. 10  shows a current-voltage characteristic of the Kelvin resistance for contact resistivity evaluation which is the second embodiment of the present invention. 
       FIG. 11  shows a current-voltage characteristic of a Kelvin resistance according to the conventional technique by performing heat treatment after ion implantation, forming a highly-concentrated Si layer, thereafter performing deposition of an interlayer insulating film and formation of a contact region, then forming a metal film, and again performing heat treatment to silicide the metal film. By using a high pressure as a metal deposition pressure, plasma damage during sputtering deposition is reduced, deactivation of the highly-concentrated Si region is prevented, and a resistivity is reduced to some extent. 
     On the other hand, in the second embodiment, impurities are activated after the metal film is deposited, so that plasma damage caused by sputtering deposition is minimized. Further, by forming the metal film on amorphous Si after ion implantation and siliciding the metal film by heat treatment, silicidation easily progresses. As a consequence, resistivity is further reduced as compared with  FIG. 11  and a low contact resistivity of 8.0×10 −10  Ωcm 2  is achieved. 
     At this time, a surface orientation of silicon may be not only a (100) surface but also any surface orientation such as a (110) surface, a (551) surface, or the like. Further, the metal may be not only palladium but also any metal material which is at least one of cobalt, nickel, rhodium, rhenium, osmium, iridium, platinum, and gold and which is adapted to form a silicide having a work function difference of not greater than 0.3 eV with respect to the highly-concentrated layer. 
     When p-type or n-type impurities are ion-implanted into a silicon portion to become a contact region, a surface of the silicon portion is amorphized. In the conventional technique, an amorphous surface is crystallized when ions are subsequently activated by heat treatment and, therefore, a metal for a silicide adheres to the crystallized silicon surface. However, in the present invention, since the metal film for a silicide is formed on the amorphized silicon surface, the metal reacts with an amorphous silicon portion to thereby form a silicide of the metal. As a result, formation of a silicide becomes easy and a further reduced contact resistivity is obtained. 
     In the foregoing, the present invention has been described with reference to a plurality of embodiments. However, the present invention is not limited to the above-mentioned embodiments. Within the spirit and the scope of the present invention described in the claims, the structure and the details of the present invention may be modified in various manners which can be understood by persons skilled in the art. For example, at least one of the activation of the highly-concentrated layer and the silicidation must be performed. If both steps are performed, these steps need not simultaneously be performed but may be performed separately. 
     This application is based upon and claims the benefit of priority from Japanese patent application No. 2008-129692, filed on May 16, 2008, the disclosure of which is incorporated herein in its entirety by reference.