Patent Publication Number: US-9418726-B1

Title: Data reception chip

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This Application claims priority of China Patent Application No. 201510837617.3, filed on Nov. 26, 2015, the entirety of which is incorporated by reference herein. 
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The invention relates to a data reception chip, and more particularly to a data reception chip is capable of generating a reference voltage. 
     2. Description of the Related Art 
     Generally, memories comprise read only memories (ROMs) and random access memories (RAMs). Common types of ROM include programmable ROMs (PROMs), erasable PROMs (EPROMs), electrically EPROMs (EEPROMs), and flash memories. Common types of RAM include static RAMs (SRAMs) and dynamic RAMs (DRAMs). 
     A data reception chip is utilized to access memories. However, when the data reception chip accesses a memory, if the data reception chip receives an external signal, the accessing operation may easily be interfered with by external noise led into the data reception chip by the external signal, affecting the accuracy of the data received by the data reception chip. 
     BRIEF SUMMARY OF THE INVENTION 
     In accordance with an embodiment, a data reception chip is coupled to an external memory comprising a first input-output pin to output first data and comprises a comparison module and a voltage generation module. The comparison module is coupled to the first input-output pin to receive the first data and compares the first data with a first reference voltage to identify the value of the first data. The voltage generation module is configured to generate the first reference voltage and comprises a first resistor, a second resistor, a first capacitor and a second capacitor. The second resistor is serially connected to the first resistor. The first and second resistors divide a first operation voltage to generate the first reference voltage. The second capacitor is serially connected to the first capacitor. The first and second capacitors direct the first reference voltage to track the noise of the first operation voltage. 
     The reference voltage generated by the data reception chip of the invention is capable of tracking the change of received signal to reduce the error rate. In other embodiments, the number of pins on the data reception chip is reduced. 
     A detailed description is given in the following embodiments with reference to the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The invention can be more fully understood by referring to the following detailed description and examples with references made to the accompanying drawings, wherein: 
         FIGS. 1A and 1B  are schematic diagrams of exemplary embodiments of a control system, according to various aspects of the present disclosure; 
         FIGS. 2A-2D and 3A-3D  are schematic diagrams of exemplary embodiments of a voltage generation module, according to various aspects of the present disclosure; 
         FIG. 4  is a flowchart of an exemplary embodiment of the voltage generation module shown in  FIG. 3C ; and 
         FIG. 5  is a schematic diagram of an exemplary embodiment of a data reception chip, according to various aspects of the present disclosure. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims. 
       FIG. 1A  is a schematic diagram of an exemplary embodiment of a control system, according to various aspects of the present disclosure. The control system  100 A comprises an external memory  110  and a data reception chip  120 A. The external memory  110  may be a non-volatile memory or a volatile memory. In one embodiment, the external  110  is a dynamic random access memory (DRAM), but the disclosure is not limited thereto. As shown in  FIG. 1A , while the external memory  110  comprises input-output pins IO 0 ˜IO 7 , it should be appreciated that the number of input-output pins need not be limited to eight, but may be greater or fewer in number in other embodiments. The input-output pins IO 0 ˜IO 7  transmit data DQ&lt; 0 &gt;˜DQ&lt; 7 &gt;, respectively. 
     The data reception chip  120 A is coupled to the external memory  110  and operates according to operation voltages VPP and VSS. In one embodiment, the data reception chip  120 A is a memory controller. In this embodiment, the data reception chip  120 A comprises a comparison module  121 A and a voltage generation module  122 . While the comparison module  121 A comprises comparators CMA 0 ˜CMA 7 , it should be appreciated that the number of comparators need not be limited to eight, but may be greater or fewer in number in other embodiments. The comparators CMA 0 ˜CMA 7  are coupled to the input-output pins IO 0 ˜IO 7  to receive the data DQ&lt; 0 &gt;˜DQ&lt; 7 &gt;, respectively. The comparators CMA 0 ˜CMA 7  compare the data DQ&lt; 0 &gt;˜DQ&lt; 7 &gt; with a reference voltage VREF to identify the values of the DQ&lt; 0 &gt;˜DQ&lt; 7 &gt;, respectively. For example, when the data DQ&lt; 0 &gt; is greater than the reference voltage VREF, it means that the value of the data DQ&lt; 0 &gt; is 1. On the contrary, when the data DQ&lt; 0 &gt; is less than the reference voltage VREF, it means that the value of the data DQ&lt; 0 &gt; is 0. 
     In this embodiment, the comparators CMA 0 ˜CMA 7  receive the same reference voltage VREF, but the disclosure is not limited thereto. In other embodiments, the reference voltage received by at least one of the comparators CMA 0 ˜CMA 7  is different from the reference voltage received by one of the rest of the comparators CMA 0 ˜CMA 7 . 
     To compensate for the equivalent resistance of each of the transmission lines between the comparator module  121 A and the input-output pins IO 0 ˜IO 7 , the data reception chip  120 A comprises a plurality of terminal resistors in this embodiment. Each terminal resistor is coupled to a comparator and receives the operation voltage VPP. For brevity,  FIG. 1A  only shows a single terminal resistor Rodt. The terminal resistor Rodt is coupled to the first input terminal of the comparator CMA 0 , wherein the first input terminal of the comparator CMA 0  further receives the data DQ&lt; 0 &gt;. In other embodiments, the terminal resistor Rodt can be omitted to reduce the element cost. 
     The voltage generation module  122  receives the operation voltages VPP and VSS and generates the reference voltage VREF according to the operation voltages VPP and VSS. The voltage generation module  122  is integrated into the data reception chip  120 A so that no external noise is allowed into the data reception chip  120 A. Furthermore, the data reception chip  120 A does not utilize an additional pin to receive the reference voltage VREF, meaning that the size of the data reception chip  120 A and the number of input-output pins of the data reception chip  120 A can be reduced. 
     In this embodiment, the comparators CMA 0 ˜CMA 7  receive the same reference voltage VREF generated by a single voltage generation module, such as  122 , but the disclosure is not limited thereto.  FIG. 1B  is a schematic diagram of another exemplary embodiment of a control system, according to various aspects of the present disclosure.  FIG. 1B  is similar to  FIG. 1A  with the exception that the data reception chip  120 B comprises voltage generation modules  130 ˜ 137 . The voltage generation modules  130 ˜ 137  generate reference voltages VREF 0 ˜VREF 7 , respectively. The comparators CMB 0 ˜CMB 7  receive the reference voltages VREF 0 ˜VREF 7 , respectively. 
     The invention does not limit the number of voltage generation modules. In some embodiments, the data reception chip  120 B comprises many voltage generation modules, and the number of voltage generation modules may be 2 or more. In one embodiment, the number of voltage generation modules is the same as the number of comparators. In another embodiment, the number of voltage generation modules is less than the number of comparators. In this case, a voltage generation module may provide a reference voltage to a plurality of comparator. In some embodiments, at least one of the reference voltages VREF 0 ˜VREF 7  is different from one of the remaining of the reference voltages VREF 0 ˜VREF 7 . In this case, a voltage, such as 0.5V, occurs between two different reference voltages. The above reference voltages are generated inside of the data reception chip, and they are approximately synchronized with the operation voltage VPP. The comparison module processes the received signal according to the operation voltage VPP. Therefore, the above reference voltages are capable of tracking the changes in the received signal so that the difference between the reference voltage and the received signal is maintained. Therefore, the data reception chip is capable of accurately determining the values of the received signal to reduce an error rate. In one embodiment, the operation voltage of the comparator module  121 A is the operation voltage VPP. When the operation voltage is shifted, the compared result generated by the comparator module  121 A is affected by the shifted operation voltage. However, since the reference voltage VREF tracks the change of the operation voltage, the shifted operation voltage can be compensated by the reference voltage VREF. 
       FIGS. 2A-2D  are schematic diagrams of exemplary embodiments of a voltage generation module, according to various aspects of the present disclosure. In  FIG. 2A , the voltage generation module  200 A comprises resistors R 1  and R 2 . The resistor R 1  is serially connected to the resistor R 2 . The resistors R 1  and R 2  divide the operation voltage VPP to generate the reference voltage VREF. In  FIG. 2B , the voltage generation module  200 B comprises resistors R 1 ˜R 2  and a capacitor C 0 . The resistor R 1  is serially connected to the resistor R 2  between the operation voltages VPP and VSS. The capacitor C 0  is configured to filter the noise of the operation voltage VPP. In this embodiment, the capacitor C 0  is connected to the resistor R 2  in parallel to filter noise with a high frequency. In  FIG. 2C , the voltage generation module  200 C comprises a capacitor C 1  and resistors R 1 ˜R 2 . The resistor R 1  is connected to the resistor R 2  in series between the operation voltages VPP and VSS. The capacitor C 1  is configured to filter the noise of the operation voltage VSS. In this embodiment, the capacitor C 1  is connected to the resistor R 1  in parallel to filter noise with a high frequency. In  FIG. 2D , the voltage generation module  200 D comprises capacitors C 2 ˜C 3  and resistors R 1 ˜R 2 . The resistor R 1  is connected to the resistor R 2  in series between the operation voltages VPP and VSS to generate the reference voltage VREF. The capacitors C 2 ˜C 3  direct the reference voltage VREF to track the noise of the operation voltage VPP. In particular, the reference voltage VREF has a DC component and a AC component. The resistors R 1  and R 2  divide the operation voltage VPP to obtain the DC component. The AC component occurs only when the frequency of the noise in the circuit is high. When the frequency of the noise in the circuit is low, the AC component is zero. When the circuit has the noise with a high frequency, the capacitors C 2  and C 3  divide the operation voltage VPP to obtain the AC component. In this embodiment, when the circuit has the noise with a low frequency, the resistors R 1  and R 2  divide the operation voltage VPP to obtain the reference voltage VREF. When the circuit has the noise with the high frequency, the resistors R 1  and R 2  divide the operation voltage VPP to obtain the DC component of the reference voltage VREF, and the capacitors C 2  and C 3  divide the operation voltage VPP to obtain the AC component of the reference voltage VREF. The DC component and the AC component constitute the reference voltage VREF. 
       FIGS. 3A-3D  schematic diagrams of exemplary embodiments of a voltage generation module, according to various aspects of the present disclosure. In  FIG. 3A , the voltage generation module  300 A comprises resistors R 1 ˜R N  and a selection unit  310 . The resistors R 1 ˜R N  are connected to each other in series between the operation voltages VPP and VSS and divide the operation voltage VPP to generate divided voltages V 1 ˜V N . The selection unit  310  selects one of the voltages V 1 -V N  to serve as the reference voltage VREF according to a control signal S C . The invention does not limit the resistance of the resistors R 1 -R N . In one embodiment, the resistors R 1 ˜R N  each have the same resistance. In another embodiment, the resistance of at least one of the resistors R 1 ˜R N  is different from one of the rest of the the resistors R 1 ˜R N . 
     In  FIG. 3B , the voltage generation module  300 B is similar to the voltage generation module  300 A, except that the voltage generation module  300 B also comprises capacitors C 4 ˜C 5 . The capacitors C 4 ˜C 5  are configured to direct the reference voltage VREF to track the noise of the operation voltage VPP. As shown in  FIG. 3B , the capacitor C 4  is coupled between the operation voltage VPP and the reference voltage VREF, and the capacitor C 5  is coupled between the operation voltage VSS and the reference voltage VREF. In particular, the reference voltage VREF has a DC component and a AC component. The DC component can be obtain when the resistors divide the operation voltage VPP. The AC component occurs only when the circuit has the noise with a high frequency. When the circuit has the noise with a low frequency, the AC component is zero. When the circuit has the noise with the high frequency, the capacitors C 4  and C 5  divide the operation voltage VPP to obtain the AC component. In this embodiment, when the circuit has the noise with the low frequency, the resistors divide the operation voltage VPP to obtain the reference voltage VREF. When the circuit has the noise with the high frequency, the resistors divide the operation voltage VPP to obtain the DC component of the reference voltage VREF, and the capacitors C 4  and C 5  divide the operation voltage VPP to obtain the AC component of the reference voltage VREF. The DC component and the AC component constitute the reference voltage VREF. 
     In  FIG. 3C , the voltage generation module  300 C is similar to the voltage generation module  300 A except that the voltage generation module  300 C comprises a processing module  320 . The processing module  320  compares the compared results Out 0 ˜Out 7  of the comparison module  121 A or  121 B shown in  FIG. 1A  or  FIG. 1B  with pre-determined data to determine whether the data received by the comparison module  121 A or  121 B are correct and then generates the control signal S C  according to the determined results to adjust the reference voltage VREF. In one embodiment, the control signal S C  is a digital signal. 
       FIG. 4  is a flowchart of a control method for the voltage generation module  300 C shown in  FIG. 3 , according to various aspects of the present disclosure. First, the level of the reference voltage VREF is set to an initial level (step S 411 ). In one embodiment, the processing module  320  outputs a pre-determined control signal S C . The selection unit  310  selects a maximum level or a minimum level among the divided voltages V 1 -V N  as the initial level according to the pre-determined control signal S C . 
     External data is received and compared with the reference voltage VREF (step S 412 ). Taking  FIG. 1A  as an example, the comparator CMA 0  receives the data DQ&lt; 0 &gt; and compares the data DQ&lt; 0 &gt; with the reference voltage VREF to identify the value of the data DQ&lt; 0 &gt;. 
     The processing module  320  determines whether the compared result (e.g. Out 0 ) generated by the comparator CMA 0  is equal to pre-determined data (step S 413 ). When the compared result of the comparator CMA 0  is not equal to the pre-determined data, it means that the reference voltage VREF is not appropriate. Therefore, the processing module  320  utilizes the control signal S C  to increase or reduce the reference voltage VREF (step S 414 ) and performs step S 412  to continually compare the data DQ&lt; 0 &gt; with the increased or reduced reference voltage VREF. 
     When the compared result of the comparator CMA 0  is still not equal to the pre-determined data, the processing module  320  continually utilizes the control signal S C  to adjust the reference voltage VREF until the compared result of the comparator CMA 0  is equal to the pre-determined data. When the compared result of the comparator CMA 0  is equal to the pre-determined data, the processing module  320  performs a specific operation (step S 415 ). In one embodiment, the specific operation is to direct the selection unit  310  to maintain the reference voltage VREF. In another embodiment, the specific operation is to perform step S 414  to continually adjust the reference voltage VREF and compare the data DQ&lt; 0 &gt; with the adjusted reference voltage VREF. In this case, the processing module  320  determines whether some of the divided voltages V 1 ˜V N  are appropriate. 
     For example, assuming that when the reference voltage VREF is equal to 0.5 mV˜0.8 mV, the compared result of the comparator CMA 0  is equal to the pre-determined data. In one embodiment, the processing module  320  utilizes the control signal S C  to maintain the reference voltage VREF within 0.5 mV˜0.8 mV. In some embodiments, the processing module  320  calculates an average value, such as (0.5+0.8)/2, and then utilizes the control signal S C  to fix the level of the the reference voltage VREF at 0.65 mV, but the disclosure is not limited thereto. In other embodiments, the processing module  320  utilizes other calculation method to define an appropriate reference voltage VREF. 
     In some embodiments, each when the processing module  320  determines whether the compared result of the comparator CMA 0  is equal to the pre-determined data, the processing module  320  records the determined result. Then, the processing module  320  defines an appropriate reference voltage VREF that can help the comparison module to correctly identify the values of the data DQ&lt; 0 &gt;˜DQ&lt; 7 &gt;. In other embodiments, the processing module  320  utilizes the control signal S C  to gradually increase or reduce the reference voltage VREF to fine the appropriate reference voltage VREF. 
       FIG. 3D  is similar to  FIG. 3C  except that the voltage generation module  300 D further comprises a compensation module  330 . The compensation module  330  utilizes the processing module  320  to adjust the control signal S C  according to at least one of the operation voltage VPP, the temperature and the operation time of the data reception chip, such as  120 A or  120 B. In other embodiments, the processing module  320  can be omitted. In this case, the compensation module  330  generates the control signal S C . In some embodiments, the compensation module  330  is integrated into the processing module  320 . In one embodiment, the compensation module  330  is configured to track the changes of process, voltage and temperature and the aging of the elements within the data reception chip  121 A or  121 B. 
       FIG. 5  is a schematic diagram of another exemplary embodiment of a data reception chip, according to various aspects of the present disclosure. The data reception chip  500  comprises a comparison module  510 , a voltage generation module  520  and a switching module  530 , a detection module  540  and a logic unit  550 . In one embodiment, the data reception chip  500  is a memory controller to access an external memory, such as a double-data-rate three synchronous dynamic random access memory (DDR3 SDRAM) or a DDR4 SDRAM. 
     The comparison module  510  receives data DQ&lt; 0 &gt;˜DQ&lt; 7 &gt; and compares the data DQ&lt; 0 &gt;˜DQ&lt; 7 &gt; with a reference voltage VREF, respectively. In one embodiment, the reference voltage is generated by an internal voltage generation module  520  within the data reception chip  500 . In another embodiment, the reference voltage VREF is generated by an external voltage generation module  570  outside of the data reception chip  500 . In this case, the voltage generation module  570  provides the reference voltage VREF to the comparison module  510  via the test pin  560 . The rest pin  560  is configured to transmit signals testing the data reception chip  500 . In one embodiment, the voltage generation modules  520  and  570  are to be installed simultaneously. In another embodiment, only the voltage generation module  570  is installed outside of the data reception chip  500 , and the voltage generation module  570  provides the reference voltage to the data reception chip  500  via a test pin. 
     For example, when the data DQ&lt; 0 &gt;˜DQ&lt; 7 &gt; are provided by a DDR3 SDRAM, the switch  580  is turned on to transmit the reference voltage VREF generated by the voltage generation module  570  to the comparison module  510 . In one embodiment, the switch  580  is controlled by an external logic unit (not shown). At this time, the voltage generation module  520  is disabled. When the data DQ&lt; 0 &gt;˜DQ&lt; 7 &gt; are provided by a DDR4 SDRAM, the switch  580  is turned off. At this time, the voltage generation module  520  is enabled to generate the reference voltage VREF to the comparison module  510 . 
     The switching module  530  is coupled between the comparison module  510  and the detection module  540  to transmit detection signals DT 1 ˜DT N . In this embodiment, the switching module  530  comprises switches SW 1 ˜SW N . The switches SW 1 ˜SW N  are controlled by the logic unit  550 . When the switches SW 1 ˜SW N  are turned on, the detection signals are transmitted to the test pin  560 . In one embodiment, when one of the switches SW 1 ˜SW N  is turned on, the other switches are turned off. 
     The detection module  540  is coupled between the switching module  530  and the logic unit  550  and detects the internal state (e.g. the current, the voltage of the temperature) of the logic unit  550  to generate detection signals DT 1 ˜DT N . At least one of the detection signals DT 1 ˜DT N  is a current signal, a voltage signal or a temperature signal. In this embodiment, the detection module  540  comprises a plurality of detector, but the disclosure is not limited thereto. In some embodiments, the detection module  540  only comprises a single detector. 
     In this embodiment, a tester can utilize the test pin  560  to obtain the detection signals DT 1 ˜DT N  and determine whether the data reception chip  500  is normal according to the detection signals DT 1 ˜DT N . After the tester finishes the test work, the tester provides a turn-off signal to the logic unit  550  to turn off the switching module  530 . When the tester wants to test the data reception chip  500 , the tester provides a turn-on signal to control the logic unit  550  to turn on the switching module  530 . 
     The invention does not limit the internal structure of the logic unit  550 . In one embodiment, the logic unit  550  comprises at least one microprocessor, at least one microcontroller, at least one memory, at least one logic gate. Any circuit structure can be utilized by the logic unit  550 , as long as the circuit structure is capable of processing external data. Additionally, since the data reception chip  500  receives the reference voltage VREF generated by the voltage generation module  570  via the test pin  560 , the number of pins of the data reception chip  500  can be reduced. 
     Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. 
     While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.