Patent Publication Number: US-5298802-A

Title: Semiconductor integrated circuit device with a plurality of logic circuits having active pull-down functions

Description:
This is a continuation of application Ser. No. 557,109, filed Jul. 25, 1990; which is a continuation-in-part application of Ser. No. 330,461 filed on Mar. 30, 1989, now U.S. Pat. No. 4,999,520. 
    
    
     BACKGROUND OF THE INVENTION 
     The present invention relates to a logic circuit, particularly to the art effectively applied to a high speed logic circuit to be formed within a semiconductor integrated circuit, namely to the art effectively applied, for example, to NTL (Non-Threshold Logic), or ECL (Emitter Coupled Logic) and, moreover, to the art effectively applied to the basic logic circuit within a bipolar gate array integrated circuit (for example, refer to Nikkei Electronics, No. 420, pp. 117-120, May 4, 1987, Nikkei McGraw-Hill, Inc.). 
     The present invention also relates to a technique effective for use in an NTL or ECL circuit provided with an active pull-down circuit. 
     Some NTL and ECL circuits proposed receive low amplitude digital input signals and conduct high speed logic operations. Moreover, an NTL circuit has been proposed with an output emitter follower and an ECL circuit with an emitter follower formed by adding the output emitter follower circuit to an NTL circuit and an ECL circuit (hereinafter, the NTL circuit with an output emitter follower is called an NTL circuit and the ECL circuit with an output emitter follower is called an ECL circuit, respectively), a high speed logic integrated circuit comprising the basic configuration of the NTL circuit and the high speed logic circuit comprising the basic configuration of an ECL circuit and an NTL circuit. 
     FIG. 32 is a configuration example of the logic circuit of prior art. 
     The logic circuit LOG 7  shown in the same figure is formed as an NTL comprising a first transistor Q 36  forming a grounded emitter type phase inversion circuit and a second transistor Q 37  forming an emitter follower output circuit, and a negative logic output V 010  can be obtained for an input V i7  as shown in FIG. 33 by applying an inversion output extracted from the collector of transistor Q 36  to the base of transistor Q 37 . 
     In this case, this logic circuit LOG 7  is provided with a collector load resistance R 34 , an emitter bias resistance R 35 , a speedup capacitance C a8  for improving switching operation of transistor Q 36  and an emitter load resistance R 36  of transistor Q 37 . 
     The NTL circuit is described, for example, in Japanese Patent Laid-Open No. 63-124615. 
     SUMMARY OF THE INVENTION 
     The inventors of the present invention, however, have found that the NTL circuit technique described above is accompanied by the following problems. 
     Namely, as the operation waveforms of logic circuit LOG 7  described are shown in FIG. 33, when the input V i7  is changed to low level L from high level H and thereby the output V 010  is changed to the high level H from the low level L, a load capacitance CL 3  is actively charged by the emitter follower operation of transistor Q 37  and thereby the output V 010  can immediately be boosted up to the high level H from the low level L. 
     However, when the input V i7  is changed to the high level H from the low level L and thereby the output V 010  is changed to the low level L from the high level H, it is required to wait for the charge of load capacitance CL 3  to be passively discharged by the emitter load resistance R 36 . Therefore, a comparatively longer delay time t pd2  is generated at the change of output V 010  to the low level L from the high level H. 
     In above logic circuit LOG 7 , it is necessary for ensuring a short falling time of output V 010  to sufficiently lower the resistance value of emitter load resistance R 36  of the transistor Q 37  to cause a discharge current I 9  from the load capacitance CL 3  to easily flow. However, when the value of emitter load resistance R 36  is lowered, a current steadily flowing into the emitter load resistance R 36  when the output V 010  is high level H increases, also resulting in increase of current dissipation of the circuit. 
     As described above, the logic circuit described has a problem that it is difficult to simultaneously satisfy the low power consumption and high speed operation. 
     Moreover, a problem also rises that if the circuit elements are superminiaturized by the monolithic semiconductor integrated circuit technology since the logic circuit described, for example, is used as the basic logic circuit of a large capacity gate array integrated circuit, malfunction may easily be generated due to the influence of α-rays. 
     For the logic circuit formed by ECL, the improved circuit is indicated in the U.S. Pat. No. 4,539,493. 
     It is therefore an object of the present invention to provide a semiconductor integrated circuit which simultaneously satisfies high speed characteristic and low power consumption Another object of the present invention is to provide a semiconductor integrated circuit which is resistive to the influence of α-rays. 
     These and other objects and novel features of the present invention will be become apparent from the following description of the specification and the accompanying drawings of the present invention. 
     A typical disclosure of the present invention will be summarized hereinafter. 
     Namely, in the logic circuit forming NTL, the input circuit is formed by a phase split circuit, the emitter follower output circuit is driven with an inverted output of this phase split circuit, on the other hand, an emitter load of emitter follower output circuit is formed by a transistor and the emitter load transistor is temporarily conductively driven with a charging current of the capacitance which is charged by the rising edge of a non-inverted output of such phase split circuit. 
     According to the means described above, in the transition period wherein the emitter follower output circuit transistor is changed to the non-conductive from the conductive condition at the transition of input logic, the emitter load transistor of the emitter follower output circuit temporarily becomes conductive quickly discharging the load capacitance, and in the steady state other than the transition period, the emitter load transistor keeps an almost non-conductive state. 
     Thereby, the objects for simultaneously satisfying low power consumption and high speed characteristics, enabling the wired logic and receiving little influence from α-rays can be attained. 
     Moreover, according to investigations by the inventors of the present invention, the current circuit speed of the NTL circuit is 70 ps/gate (under the loading condition) but it may be improved in the future up to 30 ps/gate by applying the present invention to the logic circuit, namely the NTL circuit of FIG. 32. In addition, the power consumption of this NTL circuit may be lowered up to 1/2 to 1/5 in comparison with the ECL circuit of the prior art. 
     Furthermore, according to investigations by the inventors of the present invention, a logic circuit to which the present invention is applied is a low amplitude circuit and therefore realizes high speed operation. In addition, the power supply voltage of the logic circuit (logic part) to which the present invention is applied is a low voltage circuit (low voltage part) allowing a voltage as low as -2.0--1.2 V and therefore realizes low power supply voltage. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 illustrates the first principle of a first logic circuit to which the present invention is applied; 
     FIG. 2 is an input/output characteristic diagram of the first logic circuit of FIG. 1; 
     FIG. 3 illustrates waveforms operation examples of the first logic circuit of FIG. 1; 
     FIG. 4 is a sectional view of bipolar transistor and collector load resistance included in the first logic circuit shown in FIG. 1; 
     FIG. 5 is a first circuit diagram for realizing the first principle diagram of the first logic circuit shown in FIG. 1; 
     FIG. 6 is a characteristic graph indicating relationship between base voltage and collector current of a pull-down transistor included in the first logic circuit shown in FIG. 5; 
     FIG. 7A illustrates waveforms indicating the simulation of the input and output signals of the first logic circuit shown in FIG. 5; 
     FIG. 7B illustrates waveforms indicating relationship between collector current of emitter follower transistor and collector current of pull down transistor included in the first logic circuit shown in FIG. 5 during the simulation operation; 
     FIG. 8 is a circuit diagram providing a plurality of differential capacitances in the first logic circuit shown in FIG. 5; 
     FIG. 9 is a layout diagram indicating a plurality of differential capacitances included in the first logic circuit shown in FIG. 8; 
     FIG. 10 is a circuit diagram indicating application example of the first logic circuit shown in FIG. 5; 
     FIG. 11 is a circuit diagram indicating the first application example of the first logic circuit shown in FIG. 10; 
     FIG. 12 is a circuit diagram indicating the second application example of the first logic circuit shown in FIG. 10; 
     FIG. 13 is a circuit diagram coupling the first logic circuit shown in FIG. 10 to another logic circuit; 
     FIG. 14 is a circuit diagram stabilizing an output of the first logic circuit shown in FIG. 10; 
     FIG. 15 is a layout of the first logic circuit shown in FIG. 14; 
     FIG. 16 is a second circuit diagram for realizing the first principle diagram of the first logic circuit shown in FIG. 1; 
     FIG. 17 is a circuit diagram indicating an application example of the first logic circuit shown in FIG. 16; 
     FIG. 18 is a third circuit diagram for realizing the first principle diagram of the first logic circuit shown in FIG. 1; 
     FIG. 19 is a circuit diagram providing a constant voltage generating circuit in the first logic circuit shown in FIG. 5; 
     FIG. 20 is a circuit diagram indicating the second principle diagram of the first logic circuit to which the present invention is applied; 
     FIG. 21 illustrates waveforms indicating operation example of the first logic circuit shown in FIG. 20; 
     FIG. 22 is a circuit diagram for realizing the second principle diagram of the first logic circuit shown in FIG. 20; 
     FIG. 23 is a circuit diagram indicating the second logic circuit to which the present invention is applied; 
     FIG. 24 is a circuit diagram indicating the third logic circuit to which the present invention is applied; 
     FIG. 25 is a circuit diagram indicating a fourth logic circuit to which the present invention is applied; 
     FIG. 26 is a circuit diagram indicating the fifth logic circuit to which the present invention is applied; 
     FIG. 27 is a schematic plan view indicating a large capacity gate array integrated circuit to which the present invention is applied; 
     FIG. 28 is a circuit diagram forming a cell of a large capacity gate array integrated circuit shown in FIG. 27 with the first logic circuit; 
     FIG. 29 is a sectional view of a large capacity gate array shown in FIG. 28 sealed by microchip carrier; 
     FIG. 30 is a sectional view forming a capacitance chip on the carrier shown in FIG. 29; 
     FIG. 31 is diagram indicating mounting of a microchip carrier shown in FIG. 29 on a mounting substrate; 
     FIG. 32 is a circuit diagram indicating an configuration example of the logic circuit discussed prior to the present invention; 
     FIG. 33 illustrates waveforms indicating operation example of the logic circuit shown in FIG. 32; 
     FIG. 34 is a circuit diagram showing an embodiment in which an active pull-down circuit according to the present invention is applied to an NTL circuit; 
     FIG. 35 is a circuit diagram showing another embodiment in which an active pull-down circuit according to the present invention is applied to an NTL circuit; 
     FIG. 36 is a circuit diagram showing a further embodiment in which an active pull-down circuit according to the present invention is applied to an NTL circuit; 
     FIG. 37 is a circuit diagram showing an embodiment in which an active pull-down circuit according to the present invention is applied to an ECL circuit; 
     FIG. 38 is a circuit diagram showing another embodiment in which an active pull-down circuit according to the present invention is applied to an NTL circuit; and 
     FIG. 39 is a circuit diagram showing an example of an active pull-down circuit investigated by the present inventor in the process of accomplishing the present invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 1 illustrates a first principle diagram of the first logic circuit to which the present invention is applied. In the following figures, the like elements are given the like numerals, a bipolar transistor shown is an NPN transistor, and logic circuits shown in the figures form, although not limited particularly,.the one of cells as the basic logic circuit of the large capacity gate array integrated circuit as shown in FIG. 27 described later, which is formed, together with the other cells, on a single P type semiconductor substrate such as a single crystal silicon. In FIG. 1, the logic circuit LOG 1  is formed by a phase split circuit 1, an emitter follower output circuit 2 which is driven by an inverted output -V i  of this phase split circuit 1, an active pull-down circuit 3, and a differential capacitance C al  which differentiates the rising edge of the non-inverted output +V i  of the phase split circuit 1. 
     In this case, the phase split circuit 1 described is formed by a bipolar transistor Q 1 , a collector load resistance R 2  located in series between the collector of such bipolar transistor Q 1  and a high level power source voltage V cc  and an emitter load resistance R 3  located in series between the emitter of bipolar transistor Q 1  and a low level power source voltage V ee . 
     The emitter follower output circuit 2 is formed by an emitter follower transistor Q 2 . The emitter of emitter follower transistor Q 2  is connected to the low level power source voltage V ee  through the pull-down transistor Q 3  described later and simultaneously with a load capacitance CL 1  generated equitably by distributed capacitance of an output lead wire and input capacitance of logic circuit in the next stage. 
     The active pull-down circuit 3 is formed by the pull-down transistor Q 3 , which is an emitter load of the emitter follower output circuit 2 and such differential capacitance C al  is conductively driven temporarily by differentiating the rising edge of non-inverted output +V i . 
     The differential capacitance C al  is connected, at the one electrode, with the emitter of bipolar transistor Q 1  and, at the other electrode, with the base of pull-down transistor Q 3 . The base of pull-down transistor Q 3  is connected in parallel with a resistance R 1 . This resistance R 1  forms, together with the differential capacitance C al , a differential time constant and simultaneously a discharge path for the remaining charge of the base of pull-down transistor Q 3 . 
     To the base of bipolar transistor Q 1  forming the phase split circuit 1, the digital input signal V i1  is supplied from the other logic circuits not illustrated in the large capacity gate array integrated circuit. Here, the power source voltage V cc  of circuit is set to the ground potential, while the power source Voltage V ee  of circuit is set to a predetermined negative power source voltage (for example, -2 V). Moreover, the digital input signal V i1  is given comparatively small signal amplitude, for example, with the high level V H  thereof set to -0.8 V or with the low level V L  to -1.4 V. 
     FIG. 2 is an input/output characteristic graph the logic circuit LOG 1  shown in FIG. 1. In FIG. 2, the level of digital output signal V o1  of the logic circuit LOG 1  shown in FIG. 1 will be explained. 
     When the digital input signal V i1  is set to the predetermined low level V L , the collector current I cl  of bipolar transistor Q 1  becomes a comparatively small value as indicated below when the base emitter voltage of bipolar transistor Q 1  and current conduction rate are respectively designated as V BE1  and α 1 . 
     
         I.sub.cl =(V.sub.L -V.sub.BE1 -V.sub.ee)×α.sub.1 /α.sub.3 
    
     In this case, a voltage of node n 1  is set to such a high level as 
     
         V.sub.V.sub.HC =-R.sub.2 ×Ic.sub.1 
    
     The high level V HC  of node n 1  is further shifted as much as base emitter voltage V BE2  of transistor Q 2  forming the output emitter follower circuit. Thereafter, the digital output signal V o1  of the logic circuit LOG 1  is set to the high level as indicated below. 
     
         V.sub.H =V.sub.HC -V.sub.BE2 
    
     The high level V H  of digital output signal V o1  is set to the high level V H  of digital input signal by setting the collector load resistance R 2  and emitter load resistance R 3 . 
     Meanwhile, the digital input signal V o1  is set to the predetermined high level V H , the collector current I Cl , of bipolar transistor Q 1  becomes a comparatively large value as indicated below when the base emitter voltage of bipolar transistor Q 1  and current conduction rate are defined respectively as V BE1 , and α 1&#39; . 
     
         I.sub.cl&#39; =(V.sub.H -V.sub.BE1&#39; -V.sub.ee)×α.sub.1&#39; /R.sub.3 
    
     In this case, a voltage of node n 1  is set to a level as low as 
     
         V.sub.LC =-R.sub.2 ×I.sub.cl&#39; 
    
     The low level V LC  of node n 1  is set to the low level of digital output signal V o1  of the logic circuit LOG 1  after it is shifted as much as the base emitter voltage V BE2 , of the emitter follower transistor Q 2 . In this case, the low level V L  of digital output signal V o1  is indicated as 
     
         V.sub.L =V.sub.LC -V.sub.BE2&#39; 
    
     The low level V L  of the digital output signal V o1  can be set to the low level V L  of digital input signal V i1  by setting the collector load resistance R 2  and emitter load resistance R 3 . 
     FIG. 3 illustrates waveforms indicating an operation example of the logic circuit LOG 1  shown in FIG. 1. 
     In FIG. 3, potentials of digital input signal V i1  and digital output signal V o1  are plotted on the vertical axis, while the time is shown on the horizontal axis. 
     As indicated in the same figure, when the digital input signal V i1  changes to the low level V L  from the high level V H , the load capacitance CL 1  is quickly charged by the emitter follower operation of the emitter follower transistor Q 2 . Thereby, the digital output signal V o1  immediately rises up to the high level V H  from the low level V L  as in the case of the ECL circuit of the prior art. 
     When the digital input signal V i1  changes to the high level V H  from the low level V L , a charging current I l  of the differential capacitance C al  flows toward the base of pull-down transistor Q 3  from the emitter of bipolar transistor Q 1 . Thereby, the pull-down transistor Q 3  is temporarily conductively driven, quickly discharging the load capacitance CL 1 . Namely, the differential capacitance C al  differentiates the rising edge of non-inverted output +V i  of the phase split circuit 1 and this differential output temporarily conductively drives the pull-down transistor Q 3 . As a result, a large discharge current I 2  is extracted from the load capacitance CL 1  and the digital output signal V o1  immediately drops to the low level V L  from the high level V H . 
     As described above, a delay time t pd1  when the digital output signal V o1  drops is sharply curtailed in the logic circuit LOG 1  described above and as shown in FIG. 3, the rising time becomes almost equal to the falling time of the digital output signal V o1  and the differential output forces the pull-down transistor Q 3  to be driven temporarily and conductively. Therefore, the load driving capability becomes very high in case the load capacitance CL 1  is light and even in case it is heavy, and the input impulse response can be improved because the load driving capability is high. Accordingly, since the rising time of digital output signal V o1  is almost equal to the falling time, dependency on input waveform of digital input signal V i  for the circuit speed of logic circuit LOG 1  can be reduced and the pull-down transistor Q 3  equivalently forming the emitter load of emitter follower output circuit 2 is transitionally and conductively driven only when the digital input signal V i1  changes to the high level V H  from the low level V L  while the digital output signal V o1  changes to the low level V L  from the high level V H , and in the steady state other than the transition period, the pull-down transistor Q 3  inhibits the emitter current according to keeping almost non-conductive state. Thereby, the logic circuit LOG 1  described above attains the high speed characteristic simultaneously with low power consumption. 
     In addition, in the logic circuit LOG 1  described, the emitter load in the normal condition is equivalently in the high impedance condition and thereby a current flowing from the output load side is suppressed to a low level while the low level V L  output is obtained. Thereby, it can be done easily to connect in common the outputs of a plurality of logic circuits to form a wired logic circuit. 
     Moreover, in such logic circuit LOG 1 , for example, even if the bipolar transistor Q 1  or Q 3  forming the phase split circuit 1 is effected by the α-ray, such influence of α-rays can be alleviated as explained for FIG. 4. 
     FIG. 4 is a sectional view of a bipolar transistor Q 1  and collector load resistance R 2  of logic circuit LOG 1  shown in FIG. 1. 
     In FIG. 4, P-Sub designates P type semiconductor substrate; N+--B1, N+ type buried layer; N--E p  i, N type epitaxial layer; p--B1, base region of bipolar transistor Q 1  ; P--R, resistance layer of collector load resistance R 2  ; N+--E1, emitter region of bipolar transistor Q 1  ; N+--C, collector contact layer of bipolar transistor Q 1  ; p+, channel stop region; D 4 , depletion layer region and F, field oxide film. B, E, C respectively designate aluminum electrodes of base, emitter and collector of the bipolar transistor Q 1 . R--A1 designates the electrode of collector load resistance R 2  formed by aluminum and is connected to the power source voltage V cc . The collector load resistance R 2  may also be formed by the polysilicon layer. 
     Under the steady condition, when the α-ray α is incident to the bipolar transistor Q 1 , the holes ⊕ and electrons ⊖ are generated in the depletion layer region D r . The electrons ⊖ are collected to the collector potential, thereby providing the effect as it were region of bipolar transistor Q 1  having the higher potential, thereby providing the effect as it were applying a leak current to the P type semiconductor substrate from the collector region of the bipolar transistor Q 1 . In this case, a virtual collector current generated by the α-ray lowers the collector current of bipolar transistor Q 1  but almost does not have any effect on the emitter voltage of bipolar transistor Q 1  since the base voltage is constant. Accordingly, the pull-down transistor Q 3  maintains the non-conductive condition without receiving the effect of the α-ray. While the pull-down transistor Q 3  sustains the non-conductive condition, the charges of load capacitance CL 1  are not discharged quickly even if only the collector voltage of bipolar transistor Q 1  is lowered temporarily by the α-ray. Moreover, when the α-ray is incident to the pull-down transistor Q 3 , the collector voltage of pull-down transistor Q 3  is caused to become low as in the case of explanation about operation of pull-down transistor Q 3  for the α-ray, but the collector of pull-down transistor Q 3  is clamped by operations of emitter follower transistor Q 2  and it does not drop largely. Therefore, the pull-down transistor Q 3  maintains the non-conductive condition and the charges of load capacitance CL 1  is not discharged quickly. In addition, it is impossible for the α-ray entering the emitter follower transistor Q 1  (or pull-down transistor Q 3 ) to be incident to the pull-down transistor Q 3  (or bipolar transistor Q 1 ) from the characteristic of the α-ray and it is almost far from possibility that a couple of α-rays are respectively incident to the bipolar transistor Q 1  and pull-down transistor Q 3 . Accordingly, the digital output signal V o1  does not become low so much as the drop of the collector voltage of bipolar transistor Q 1 , for example, even when the α-ray is incident to the bipolar transistor Q 1  or pull-down transistor Q 3 . Namely, the influence of the α-ray can be eased. 
     FIG. 5 shows a first embodiment for realizing the logic circuit LOG 1  shown in FIG. 1 with the present invention. FIG. 6 illustrates the characteristic graph for explaining the relationship between the base voltage V B3  and collector current I C3  of the pull-down transistor Q 3  included to the logic circuit LOG 1  shown in FIG. 5. 
     Explanation will be made focusing on the difference from FIG. 1. In the logic circuit LOG 1  of an embodiment shown in the same figure, although not limited particularly, the collector load resistance R 2 , emitter load resistance R 3  and resistance R 1  are respectively set to 3 kΩ, 2 kΩ and 40 kΩ and the differential capacitance C al  is set to 0.2 PF. Moreover, in this embodiment, a high resistance R 4  of 20 kΩ is provided for stabilizing the emitter voltage of the emitter follower transistor Q 2  in the steady state. Moreover, a bias circuit 4 which biases the pull-down transistor Q 3  in the steady state to the condition just before the conductive condition is also provided. This bias circuit 4 is formed by the bipolar transistor Q 4  to which the predetermined base control voltage V b1  supplied from the external or internal circuit of the cell formed by the logic circuit LOG 1  is applied and the predetermined bias voltage V b  is supplied to the base of pull-down transistor Q 3 . 
     Here, the predetermined base control voltage V b1  to be supplied to the base of bipolar transistor Q 4  is set to such a predetermined voltage as will provide a voltage value for setting the pull-down transistor Q 3  to the very weak ON condition, namely the bias voltage V b  which is generated the collector current I c3  of the pull-down transistor Q 3  to I c3&#39;  (for example, 10-100 μA) as shown in FIG. 6. 
     Thereby, if the driving sensitivity of pull-down transistor Q 3  is enhanced and the capacitance value of the differential capacitance C al  is lowered to a small value, the pull-down transistor Q 3  is reliably driven conductively and the load capacitance CL 1  can be quickly discharged at the transition time where the digital input signal V o1  is changed to the high level V H  from the low level V L . 
     As described, the falling time of the digital output signal V o1  to the low level V L  from the high level v H  is further shortened and moreover the load capacitance CL 1  can be discharged more quickly even in case the load capacitance CL 1  is a heavy load. Moreover, a conductive driving level of the pull-down transistor Q 3  is determined by a capacitance value of differential capacitance C al  and the voltage value of bias voltage V b . Namely, the load driving capability of the logic circuit LOG 1  can be controlled by changing the capacitance value of differential capacitance C al  or the voltage value of base control voltage V b1  of bipolar transistor Q 4  and the falling rate of digital output signal V o1  can also be controlled. The high impedance resistance R 4  for stabilizing emitter voltage of emitter follower transistor Q 2  in the steady state is not always required in case the base control voltage V b1  of the bipolar transistor Q 4  is set to a constant value. 
     FIG. 7A illustrates waveforms indicating the simulation of input and output signals of the logic circuit LOG 1  shown in FIG. 5. FIG. 7B also illustrates waveforms indicating the collector current of emitter follower transistor Q 2  and the collector current of pull-down transistor Q 3  during the simulation. 
     In such simulation, the collector load resistance R 2  is set to 1.9 kΩ, emitter load resistance R 3  to 1.3 kΩ, resistance R 1  to 20 kΩ, differential capacitance C al  to 0.7 pF, load capacitance CL 1  to 3 PF, base control voltage V b1  to -0.52 V, power source voltage V cc  to 0 V and power source voltage V ee  to -1.985 V. The high resistance R 4  shown in FIG. 5 is not provided for this simulation. 
     In FIG. 7A, the time is plotted on the horizontal axis in the unit of seconds. On the other hand, the voltage of digital input signal V i1  and digital output signal V o1  is plotted on the vertical axis in the unit of volts. The digital input voltage V i1  and digital output signal V o1  respectively include some errors as shown in the waveforms of FIG. 7A, and the high level or low level including such errors are also respectively indicated as the high level V H  and low level V L  in FIG. 7A. In FIG. 7B, the horizontal axis indicates the time like FIG. 7A in the unit of seconds and the current of vertical axis indicates the collector current I c2  of emitter follower transistor Q 2  and collector current I c3  of pull-down transistor Q 3  in the unit of amperes. 
     In FIG. 7A and FIG. 7B, when the digital input signal V i1  changes to the high level V H  from the low level V L , the collector current I c2  quickly increases due to the emitter follower operation of the emitter follower transistor Q 2  and thereby the load capacitance CL 1  is quickly charged, followed by the digital output signal V o1  rising up immediately to the high level V H . 
     When the digital input signal V i1  changes to the high level V H  from the low level V L , the pull-down transistor Q 3  is temporarily driven conductively with an output of the differential capacitance C al  as described previously and thereby the collector current I c3  of pull-down transistor Q 3  quickly increases and the load capacitance CL 1  is quickly discharged. Therefore, the digital output signal V o1  falls to the low level V L  from the high level V H  with a delay time t pd1&#39;  of about 0.6×10 -9  sec. 
     FIG. 8 indicates an embodiment providing a plurality of differential capacitances in the logic circuit LOG 1  shown in FIG. 5. FIG. 9 illustrates a layout of a plurality of differential capacitances shown in FIG. 8. 
     Explanation will now be made hereunder focusing on the difference from the embodiment of FIG. 5 with reference to FIG. 8. In the logic circuit LOG 1  shown in the same figure, the differential capacitances C alA , C alB  and C alC  are provided in place of the differential capacitance C al . 
     In FIG. 9, the regions Po and Po&#39; enclosed by a broken line indicate the polysilicon layer, respectively. A lA  -A lC  indicate wirings formed by the aluminum layer and C oA  -C oC  indicate contact holes. 
     The differential capacitances C lA , C lB  and C lC  are respectively formed in the doubled polysilicon layers formed from the polysilicon layers Po, Po&#39;, interposing dielectric films not illustrated. The wirings A lA  -A lC  and contact holes C oA  -C oG  coupled with the differential capacitances C alA , C alB  and C alC  are selected by CAD (Computer Aided Design) and DA (Design Automation). The differential capacitances C alA , C alB  or C alC  are coupled between the emitter of bipolar transistor Q 1  and the base of pull-down transistor Q 3  with the mask to form the pattern of selected wirings A lA , A lB  or A lC  and contact holes C oA , C oB  or C oG . 
     As described above, the logic circuit LOG 1  can select adequate load driving capability and falling rate of the digital output signal V o1  for the load capacitance CL 1  by selecting the differential capacitances C alA , C alB  or C alC . 
     FIG. 10 shows an embodiment indicating an application example of the logic circuit LOG 1  shown in FIG. 5 to which the present invention is applied. 
     Focusing to difference from FIG. 5, in the logic circuit LOG 1 , the bipolar transistor Q 1  forming the phase split circuit 1 comprises the bipolar transistors Q lA  and Q lB  forming a 2-input logic circuit and the digital input signals V i1A  and V i1B  are respectively supplied to the bases of bipolar transistors Q lA  and Q lB . 
     Operations of embodiment shown in FIG. 10 will then be explained hereunder. 
     When the digital input Signals V i1A  and V i1B  are all set to the low level V L , the voltage of emitters connected in common of the bipolar transistors Q lA  and Q lB  becomes the low level and a comparatively small collector current flows into the collector load resistance R 2 . Therefore, the node n 1  becomes high level V HC  like the embodiment of FIG. 1, while the digital output signal V o1  becomes predetermined high level V H . 
     On the other hand, any one of the digital input signals V i1A  and V i1B  becomes high level V H , the voltage of emitters connected in common of the transistors Q lA   and Q lB  becomes high level and a comparatively large collector current flows into the collector load resistance R 2 . Thereby, the digital output signal V o1  is set to the predetermined low level V L . 
     Namely, the logic circuit LOG 1  of this embodiment functions as the 2-input NOR gate circuit in which the digital output signal V o1  satisfies following logical expression. ##EQU1## 
     As described above, in the embodiment of FIG. 5, the bipolar transistor Q 1 , of the logic circuit LOG 1 , forming the phase split circuit 1 is provided in parallel and these are replaced by a couple of transistors Q lA  and Q lB  which respectively receive the digital input signals V i1A  and V i1B  corresponding to the bases of these transistors. When the digital input signals V i1A  and V i1B  are all low level V L , the digital output signal V o1  is set selectively to the high level V H  and thereby the logic circuit LOG 1  of this embodiment functions as the 2-input NOR gate. It is natural that the logic circuit LOG 1  realizes low power consumption, like the embodiment of FIG. 1, without interference on the high operation rate. In addition, with increase or decrease in the number of bipolar transistors provided in parallel, the NOR gate circuit having a desired fan-in number can be realized. 
     FIG. 11 illustrates a first application example comprising a wired logic 5 by connecting a couple of 2-input logic circuits LOG 1  show in FIG. 10, as described, as the cell of large capacity gate array integrated circuit. In FIG. 11, the resistance R 4  shown in FIG. 10 may also be provided separately, although not illustrated. Moreover, since a pair of logic circuits LOG 1  are indicated, the one is designated as LOG 1A  and the other as LOG 1B . Moreover, the digital input signals V i1A , V i1B  are also indicated in the manner that the digital input signals of logic circuit LOG 1A  as V i1A , V i1B  and the digital input signals of logic LOG lB  as V i1A&#39; , V i1B&#39; , corresponding to the logic circuits LOG lA , LOG lB . 
     As is already described, the emitter load is equivalently in the high impedance during the steady state and a current flowing from the load side during output of the low level V L  is suppressed to a small level. Thereby, it can be realized easily to form a wired logic 5 by connecting in common the respective outputs without flowing of a steady current to the wires l i  and l 2 . Namely, the digital output signal V o2  indicated below can be realized by forming the wired logics. 
     
         V.sub.o2 =(V.sub.i1A +V.sub.i1B +V.sub.i1A&#39; +V.sub.i1B&#39;) 
    
     Moreover, if the wires 11 and 12 are formed by aluminum, for example, the electromigration is not easily generated because a steady current does not flow and thereby superminiaturization of wires l 1  and l 2  can be realized and in addition high speed operation and high integration density of large capacity gate array integrated circuit can also be realized. 
     The electromigration is explained, for example, on page 393, of the book entitled &#34;SEMICONDUCTOR DEVICE--BASIC THEORY AND PROCESS TECHNOLOGY&#34;, issued on May 25, 1987, SANGYO TOSHO Inc. 
     FIG. 12 is a second application example comprising a latch circuit using a pair of 2-input logic circuit LOG 1  shown in FIG. 10 as the cell of the large capacity gate array integrated circuit as described previously. 
     In FIG. 12, the resistance R 4  shown in FIG. 10 may also be provided separately, although not illustrated. Moreover, a pair of logic circuits LOG 1  are provided in FIG. 12 and the one is designated as LOG 1c , while the other as LOG 1D . 
     As is already described, both logic circuits LOG 1C , LOG 1D  assure the storing Operations with very high reliability because the digital output signal V o1  does not easily receive the influence of α-ray. 
     FIG. 13 indicates an embodiment in which the logic circuit LOG 1  shown in FIG. 10 and the logic circuit LOG 2  forming the ECL are respectively combined as the cells of large capacity gate array integrated circuit. 
     In FIG. 13, the logic circuit LOG 2  is formed by differential transistors Q 5  and Q 6  coupled between the power source voltage V cc  and power source voltage V eel&#39;  differential amplifier circuit 6 formed by resistances R 5 , R 6  and constant current source IS 1  and emitter follower output circuit 7 formed by bipolar transistors Q 7  and Q 8  which are coupled between the power source voltage V cc  and power source voltage V ee  and receive output of the differential amplifier circuit 6 and resistances R 7  and R 8 . Moreover, the digital output signal V o1  of logic circuit LOG 1  is supplied to the base of bipolar transistor Q 5  and the reference voltage V refl  to the base Of bipolar transistor Q 6 . In the logic circuit LOG 1 , the high resistance R 4  of FIG. 10, although not illustrated, may be provided by different manner. The power source voltage V eel  is set to the predetermined negative voltage and for example set to -3 V. 
     Operations of the logic circuits LOG 1 , LOG 2  in the embodiment of FIG. 13 are explained hereunder. 
     The logic circuit LOG 1  is the same as the embodiment shown in FIG. 10 and therefore it is omitted here. When the digital output signal V o1  of logic circuit LOG 1  is in the high level V H , it conductively drives the bipolar transistor Q 5  because it is higher than the potential of reference voltage V refl  and the digital output signals V o3 , V o4  of the emitter follower output circuit 7 respective become the low level V L  and high level V H . When the digital output signal V o1  of logic circuit LOG 1  is low level V L , it conductively drives the bipolar transistor Q 6  because it is lower than the reference voltage V refl  and the digital output signals V o3 , V o4  of the emitter follower output circuit are respectively output as the high level V H  and low level V L . 
     The logic circuit LOG 1  and the logic circuit LOG 2  forming ECL can be arranged simultaneously on a semiconductor substrate of the large capacity gate array integrated circuit by adequately providing the resistances R 1  -R 8  in Order to assure compatibility of the logic amplitudes of the high level and low level of the digital output signal V o1  of the logic circuit LOG 1  and the logic amplitude of the logic circuit LOG 2 . 
     FIG. 14 indicates an embodiment for stabilizing outputs of logic circuit LOG 1  shown in FIG. 10. FIG. 15 is a layout of the logic circuit LOG 1  shown in FIG. 14. 
     In FIG. 14, explanation is made focusing on the difference from FIG. 10. The logic circuit LOG 1  comprises a bias circuit 4 for biasing the pull-down transistor Q 3  in the steady state to the condition just before the conductive condition and a clamp circuit 8 to prevent overshoot of the digital output signal V o1  to the negative voltage side which may be generated when the pull-down transistor temporarily becomes conductive and the discharge current at this time is extracted excessively. Moreover, a pair of power supply lines are respectively provided for the power source voltages V cc  and V ee  in Order to prevent malfunction by conductivity at the steady state of the pull-down transistor Q 3  due to variation of power source voltages V ee  and V cc  depending on temperature characteristic of the power supply lines of power source voltages V ee  and V cc , and the power source voltages supplied from respective power supply lines are indicated as V cc1 , V cc2 , V ee2  and V ee3 . 
     The clamp Circuit 8 is formed by the bipolar transistor Q 9  to which the predetermined base control voltage V b  of low impedance is applied from the logic circuit not illustrated, and the voltage of digital output signal V o1  is boosted above the low level V L  with the emitter follower operation of transistor Q 9 . 
     In FIG. 15, N+--B1 of the region enclosed by the dotted line designates N+ type burred layer; N+--E2, the emitter region of corresponding bipolar transistors. The region P--B2 enclosed by a broken line designates the base region of corresponding bipolar transistor; the regions Po, Po&#39; enclosed by the broken line respectively designate the polysilicon layer, the region enclosed by a solid line designates the wirings Al 1  -Al 12  formed by aluminum and each Co, the contact B 1  -B 4  and B 9 , E 1  -E 4  and E 9  designate the base and emitter of the bipolar transistors Q 1  -Q 4  and Q 9  ; C 3  is collector of the emitter follower transistor Q 3  ; CC 1  and CC 2  designate the common collectors described later. The collector load resistance R 2  is not a resistance formed by the diffused layer shown in FIG. 4 but the resistance formed by the polysilicon layer. 
     In FIG. 15, the digital input Signals V i1A  and V i1B  are supplied to the bases B 1A  and B 1B  of bipolar transistors Q 1A , Q 1B  through the corresponding wirings Ali and Al 2  formed by aluminum layer. The power source voltage V ee2  is coupled to the emitters E 1A  and E 1B  of the bipolar transistors Q 1A , Q 1B  through the wirings Al 3  and Al 4  formed by aluminum layer and the load resistance R 3  formed by the polysilicon layer P o . Moreover, these emitters El A , El B  are also coupled to the one electrode of differential capacitance C al  through the wiring Al 4  formed by the aluminum layer. The collectors of bipolar transistors Q 1A , Q 1B  are formed as the common collector CC 1  and is connected to the power source voltage V cci  through the wirings Al 5  and Al 6  and collector load resistance R 2  formed by the polysilicon layer P o . This common collector CC 1  is coupled to the base B 2  of emitter follower transistor Q 2  through the wiring Al 6  formed by the aluminum layer. 
     The differential capacitance C al  is formed by interposing a dielectric film not illustrated between the doubled polysilicon layers formed by the polysilicon layers P o , P o  &#39; and the one electrode of the differential capacitance C al  is coupled to the emitters E 1A  and E 1B  of the bipolar transistors Q 1A , Q 1B  and emitter load resistance R 3  through the wiring Al 4  formed by the aluminum layer. The other electrode of differential capacitance C al  is coupled to the base B 3  of pull-down transistor Q 3 , resistance R 1  formed by polysilicon layer P o  and emitter E 4  of bipolar transistor Q 4  through the wiring Al 7  formed by the aluminum layer. 
     The pull-down transistor Q 3  is connected, at its base B 3 , to the differential capacitance C al , resistance R 1  and emitter E 4  of bipolar transistor Q 4  through the wiring Al 7  formed by the aluminum layer, as described above. The emitter E 3  of pull-down transistor Q 3  is connected to the power source voltage V ee3  and the resistance R 1  formed by the polysilicon layer P o  through the wiring Al 8  formed by the aluminum layer. The collector C 3  of pull-down transistor Q 3  is connected to the emitter E 2  of emitter follower transistor Q 2 , emitter E 9  of bipolar transistor Q 9  and the resistance R 4  formed by the polysilicon layer P o  through the wiring Al 9  formed by the aluminum layer and this wiring Al 9  of aluminum layer is used for outputting the digital output signal V o1 . 
     The emitter E 2  of emitter follower transistor Q 2  is connected, as described above, to the collector C 3  of pull-down transistor Q 3 , resistance R 4 , and emitter E 9  of bipolar transistor Q 9 . The base B 2  of emitter follower transistor Q 2  is connected, as described, to the common collector CC 1  and collector load resistance R 2  of the bipolar transistors Q 1A , Q 1B  through the wiring Al 6  formed by the aluminum. The collector of emitter follower transistor Q 2  is coupled in common with the collectors CC 2  of bipolar transistors Q 4 , Q 9  and this common collector is connected to the power source voltage V cc2  through the wiring Al 10  formed by the aluminum layer. 
     Regarding the emitter E 4  and collector of the bipolar transistor Q 4 , the emitter E 4  is coupled to the base B 3  of pull-down transistor Q 3 , differential capacitance C al  and resistance R 1  through the wiring Al 7  formed by the aluminum layer, while the collector is formed as the common collector CC 2  together with the collectors of emitter follower transistor Q 2  and bipolar transistor Q 4 . The base B 4  of bipolar transistor Q 4  is connected to the wiring Al 11  formed by the aluminum layer and the base control voltage Vb 1  is supplied through this wiring. 
     The emitter E 9  and collector of the bipolar transistor Q 9  are connected, as described above, to the resistance R 4 , emitter E 2  of emitter follower transistor Q 2  and collector C 3  of pull-down transistor Q 3  through the wiring Al 9  formed by the aluminum layer, while the collector is formed as the common collector CC 2  together with the collector of bipolar transistor Q 9  and collector of emitter follower transistor Q 4 . The base B 9  of bipolar transistor Q 9  is coupled to the wiring Al 12  formed by the aluminum layer and the base control voltage V b2  is supplied through this wiring. 
     As described above, the overshoot of digital output signal V o1  toward the negative voltage is prevented and low level V L  of digital output signal V o1  can be ensured. Moreover, since the collectors of bipolar transistors Q 1A  and Q 1B  forming the phase split circuit 1 or the collectors of bipolar transistor Q 4  of bias circuit 4 and the bipolar transistor Q 9  of clamp circuit 8 are formed on the same region of a semiconductor substrate, thereby realizing a superminiaturized cell. 
     FIG. 16 indicates a second embodiment for realizing the first principle diagram of the logic circuit LOG 1  shown in FIG. 1 to which the present invention is applied. 
     FIG. 16 will be explained focusing on difference from the embodiment of FIG. 1. The logic circuit LOG 1  of this embodiment also is provided with a bias circuit 9. 
     The bias circuit 9 is formed by the resistance R 9  coupled between the emitter of emitter follower transistor Q 2  and the differential capacitance C al . This bias circuit 9 increases a charging current for driving the pull-down transistor Q 3  with the differential capacitance C al  by DC-feedback of the digital output signal V o1  to the base of pull-down transistor Q 3  through the resistance R 9  when the digital output signal is in the high level V H . 
     Thereby, good falling characteristic can be obtained even when the load capacitance CL 1  changes. 
     FIG. 17 indicates an embodiment of the wired logic 10 formed by wiring a couple of logic circuits LOG 1  shown in FIG. 16 as the cells of large capacity gate array integrated circuit. 
     In FIG. 17, Since a pair of logic circuits LOG 1  are shown, the one is designated as LOG 1E  and the other as LOG 1F . Moreover, the digital input signal V i1  is also indicated as V i1  and V i1&#39; , respectively for the logic circuits LOG 1E  and LOG 1F . As is already described, a pair of logic circuits LOG 1E , LOG 1F  can easily form the wired logic 10 since a current flowing from the load side when the output is low level V L  is suppressed to a lower level. 
     In FIG. 17, the digital output signal V o5  =(V i1  +V i1&#39; ) for the digital input signals V i1 , V i1&#39; , can be realized by forming the wired logic 10. In the same figure, the wired logic 10 is formed by non-connection of a part of the cell formed by the logic circuit LOG 1F  namely non-application of the bias circuit 9, resistance R 1  and pull-down transistor Q 3  of the logic circuit LOG 1D . Accordingly, a current flowing from the load side is suppressed smaller than that in the embodiment of FIG. 11 and moreover electromigration of wirings l 3  and l 4  is not easily generated and superminiaturization can then be realized. 
     FIG. 18 indicates a third embodiment for realizing the first principle diagram of the logic circuit LOG 1  shown in FIG. 1 by the present invention. 
     Explanation will be made focusing on difference from FIG. 1. The logic circuit LOG 1  is formed as a load means of the emitter follower transistor Q 2  forming the output emitter follower circuit and moreover with addition of serial resistances R 10  and R 11 . A resistance R 12  is provided, although not particularly limited, between the node connected in common of the resistances R 10  and R 11  and the base of pull-down transistor Q 3 . The base of pull-down transistor Q 3  is coupled with capacitance to the emitter of the bipolar transistor Q 1  through the differential capacitance C al . Here, the resistances R 10  and R 11  are designed to have comparatively large resistance values and the resistance R 12  is designed to have a predetermined resistance value which makes sufficiently large an input impedance of the pull-down transistor Q 3 . Thereby, the resistance R 12  forms a bias circuit 11, together with the resistances R 10  and R 11 , which gives the predetermined bias voltage V b , to the base of pull-down transistor Q 3  and also forms a differential circuit, together with the differential capacitance C al , which transmits level change of digital input signal V i1  to the base of pull-down transistor Q 3 . 
     When the digital input signal V i1  is fixed to the predetermined low level V L  and the digital output signal V o1  to the predetermined high level V H , the bias voltage V b , predetermined by the resistance ratio of resistances R 10  and R 11  is applied to the base of pull-down transistor Q 3 . This bias voltage V b , is set to the predetermined voltage value which makes the pull-down transistor Q 3  to weak ON condition as in the case of the embodiment shown in FIG. 5. Thereby, the pull-down transistor Q 3  is set to the very weak ON condition without giving influence on the digital output signal V o1 . 
     When the digital input signal V i1  changes to the high level V H  from the low level V L , the base voltage of pull-down transistor Q 3  becomes temporarily high since level change of of digital input signal V i1  is transmitted through the differential circuit formed by the differential capacitance C al  and resistance R 12 . Therefore, the pull-down transistor Q 3  becomes perfect ON condition temporarily and the digital output signal V o1  is quickly Changed to the low level V L  from the high level V H . 
     While the digital input signal V i1  is fixed to the predetermined high level V H  and the digital output signal V o1  to the predetermined low level V L , the base voltage of pull-down transistor Q 3  is set to the low level and the pull-down transistor Q 3  is set to almost the cut-off condition. Under this condition, when the digital input signal V i1  changes to the low level V L  from the high level V H , the base voltage of pull-down transistor Q 3  is temporarily lowered because level change of digital input signal V i1  is transmitted through the differential circuit. Thereby, the transistor Q 3  is further set to deep cut-off condition and the digital output signal V o1  is quickly changed to the high level from the low level V L  through the emitter follower transistor Q 2 . 
     As described above, the base of pull-down transistor Q 3  in the logic circuit LOG 1  of this embodiment is capacitively coupled to the emitter of bipolar transistor Q 1  through the differential capacitance C al  and also coupled to the node connected in common of the resistances R 10  and R 11  through the resistance R 12 . The resistance R 12  forms the differential circuit, together with the differential capacitance C al , which sends level change of digital input signal V i1  to the base of pull-down transistor Q 3  and also forms a bias circuit 11, together with the resistances R 10  and R 11 , which gives the predetermined bias voltage V b , to the base of pull-down transistor Q 3 . The logic circuit LOG 1  of this embodiment enhances the driving sensitivity of the pull-down transistor Q 3  by supplying the bias voltage V b , to the base of pull-down transistor Q 3 . The malfunction due to the change of power source voltage V ee  of pull-down transistor Q 3  shown in FIG. 14 can be reduced by supplying the bias voltage V b , with the digital output signal V o1 . 
     FIG. 19 indicates an embodiment in which a constant voltage circuit is added to the logic circuit LOG 1  shown in FIG. 5. 
     Emphasis is placed on difference from FIG. 5 for the following explanation. In the same figure, a diode D 1  is provided between the base of bipolar transistor Q 4  and power source voltage V cc . Moreover, a resistance R 13  is provided, although not particularly limited, between the base of bipolar transistor Q 4  and the power source voltage V ee , while a capacitance C a2  between the base of bipolar transistor Q 4  and the emitter of emitter follower transistor Q 2 , namely the output terminal of the logic circuit LOG 1 . Thereby, the resistance R 13   forms, together with the diode D 1 , a constant voltage generating circuit which gives the predetermined base control voltage V b3  to the base of bipolar transistor Q 4  and also forms, together with the capacitance C a2 , a differential circuit which sends level change at the output terminal to the base of bipolar transistor Q 4 . Here, the resistance R 13  is designed to have a comparatively large resistance value and does not prevent power saving of the logic circuit LOG 1 . 
     When the level Of digital output signal V i1  is fixed to the high level V H  or low level V L , a predetermined base control voltage V DF1  which is determined by the forward voltage V DF1  of diode D 1  is supplied to the base of bipolar transistor Q 4 . This base control voltage V b3  is set, as in the case of the base control voltage V b1  in the embodiment shown in FIG. 5, to the predetermined voltage value which applies a bias voltage V b  to the base of pull-down transistor Q 3  so that it is set to a very weak ON condition. From these facts, the pull-down transistor Q 3  functions similar to the embodiment of FIG. 5 and thereby the logic circuit LOG 1  of this embodiment realizes low power consumption without giving influence on the high speed operation characteristic. 
     Here, a differential circuit consisting of the capacitance C a2  and resistance R 13  is provided, as described above, between the output terminal of logic circuit LOG 1  of this embodiment and the base of bipolar transistor Q 4 . This differential circuit sets the digital output signal V o1  to the low level V L , causes discharging of differential capacitance C a1  and improves response characteristic for the pulsewise input signal. 
     As described, in the logic circuit LOG 1  of this embodiment, the diode D 1  is provided between the base of bipolar transistor Q 4  forming the bias circuit 4 and the power source voltage V cc  and a capacitor C a2  is provided between the base thereof and the output terminal of the logic circuit LOG 1 . Moreover, the resistance R 13  which forms a constant voltage generating circuit together with the diode D 1  and forms a differential circuit together with the capacitance C a2  is provided between the base of bipolar transistor Q 4  and the power source voltage V ee . 
     This resistance R 13  is designed to have a comparatively large resistance value. Thereby, the logic circuit LOG 1  of this embodiment simplifies the constant voltage generating circuit for giving the predetermined base control voltage V b3  to the base of bipolar transistor Q 4  and further improves response characteristic for the pulsewise input signal by feedback operation to be carried out through the bipolar transistors Q 4  and Q 3 . As described above, since the resistances R 4  and R 13  are designed to have comparatively large resistance value, low power consumption of the logic circuit LOG 1  can be realized. 
     FIG. 20 is the second principle diagram of the logic circuit to which the present invention is applied. 
     In FIG. 20, this circuit is basically the same as the embodiment of FIG. 1 and the phase split circuit 1, emitter follower output circuit 2 and active pull-down circuit 3, etc. correspond to those in the embodiment of FIG. 1. 
     Following explanation will be made placing emphasis on difference from FIG. 1. In the same figure, the phase split circuit 1 is formed by the bipolar transistors Q 1c  and Q 1D  which receive the digital input signals V i1C  and V i1D . Moreover, even in case the logic of digital input signals V i1C , V i1D  changes to the high level V H  and low level V L  with a little time difference, the digital output signal V o1  quickly responds to such change. Therefore, a capacitance C a3  is provided for urging discharge operation of differential capacitance C al  for conductively driving the emitter load transistor Q 3 . 
     FIG. 21 illustrates the waveforms for explaining the operations of logic circuit LOG 1  shown in FIG. 20. 
     In the operation example of the same figure, since the logic of a pair of digital input signals V i1C , and V i1D  changes to the high level V H  only with a little time difference, the digital output signal V o1  becomes high level V H  only within a very short period. 
     In FIG. 20 and FIG. 21, when, in the period to wherein the digital input signal V i1c  and V i1d  are respectively high level V H  and low level V L , the differential capacitance C al  is charged to the saturated condition, viewed from the side of phase split circuit 1, because the common emitter voltage of bipolar transistors Q 1c , Q 1D , namely the non inverted output +V i  of phase split circuit 1 is high level. Moreover, the capacitance C a3  is in the noncharged condition viewed from the output side because the emitter voltage of emitter follower transistor Q 2 , namely the digital output signal V o1  is low level. 
     Next, in the period t 1  wherein the digital input signal V i1C  changes to the low level V L  from the high level V H  and the digital input signals V i1c  and V i1D  become low level V L , the non-inverted output +V i  of the phase split circuit 1 falls to the low level from the high level and thereby, the differential capacitance C al  in the charging condition starts in turn the discharge operation. Simultaneously, since the emitter voltage of emitter follower transistor Q 2 , namely the digital output signal V o1  rises to the high level V H  from the low level V L , the capacitance C a3  in the non-charging condition starts in turn the charging operation. That is, discharge operation of the differential capacitance C al  is accelerated by the charging Operation of capacitance C a3 . As a result, the differential capacitance C al  charged is sufficiently discharged within a very short period from the timing where the non-inverted output +V i  of the phase split circuit 1 falls to the low level from the high level. 
     Thereby, in the period t 2  where the digital input signal V i1D  changes to the high level V H  from the low level V L  and the non-inverted output +V i  of phase split circuit 1 rises to the high level from the low level, the differential capacitance C al  allows the charging current to flow until sufficiently driving the pull-down transistor Q 3 . Accordingly, the digital output signal V o1  can immediately be lowered to the low level from the high level. 
     Here, if the capacitance C a3  is not provided, since the period t 1  in which the logical OR of the digital input signals V i1C  and V i1D  becomes the low level is very short period, the differential capacitance C al   cannot sufficiently discharge the electric charge charged when the non-inverted output +V i  is high level. Therefore, in the period in which the non-inverted output +V i  changes to the high level from the low level, namely in the period t 2  in which the digital output signal V o1  changes to the low level from the high level, the differential capacitance C al  can no longer supply the sufficient charging current to the base of pull-down transistor Q 3 . As a result, as indicated by a dotted line in FIG. 21, level shift to the low level of the digital output signal V o1  is much delayed. 
     As described above, even when the digital input signals V i1C  and V i1D  of the logic circuit LOG 1  of the embodiment shown in FIG. 20 change within a very short period, such level change can be sent certainly to the digital output signal V o1 . 
     FIG. 22 indicates an embodiment for realizing the logic circuit LOG 1  shown in FIG. 20 by the present invention. Focusing on the difference from FIG. 20, in the logic circuit LOG 1  of the embodiment shown in the same figure, a clamp circuit 13 which rejects overshoot of digital output signal V o1  in the negative voltage side like the clamp circuit 8 shown in FIG. 14 and a resistance R 14  for assuring the level of digital output signal V o1  like the high resistance R 4  shown in FIG. 5 are provided, together with the bias circuit 12 which biases the pull-down transistor Q 3  in the steady state to the condition immediately before the conductive condition like the bias circuit shown in FIG. 5. Like the circuit of FIG. 5, the bias circuit 12 is configurated by the bipolar transistor Q 10  to which the predetermined base control voltage V b4  supplied from the external or internal circuit of the cell formed by the logic circuit LOG 1  and the predetermined bias voltage V b&#39; , is supplied to the base of pull-down transistor Q 3  by applying the predetermined bias current to the resistance R 1  connected in parallel to the base of pull-down transistor Q 3 . Like the bias voltage V b  shown in FIG. 5 and FIG. 6, the predetermined bias voltage V b&#39; , is a voltage value for setting the pull-down transistor Q 3  to the very weak ON condition, namely a voltage value which result sin the collector current I c3  of the pull-down transistor of about 10-100 μA. 
     The clamp circuit 13 is formed by the bipolar transistor Q 11  to which the predetermined base control voltage V b5  is applied like the circuit shown in FIG. 14 and the voltage of digital output signal V o1  is boosted exceeding the predetermined low level V L  by the emitter follower operation of the bipolar transistor Q 11 . 
     FIG. 23 indicates an embodiment of the second logic circuit to which the present invention is applied. 
     In FIG. 23, the logic circuit LOG 3  is formed by the phase inverting circuit 14 which receives the complementary digital input signals V i2 , V i3  and outputs the phase-inverted digital input signals V i2 , V i3 , emitter follower output circuits 15, 16 which are driven by outputs of the phase inverting circuit 14, active pull-down circuits 17, 18, differential capacitances C a4 , C a5  for differentiating rising edges of the digital input Signals V i2 , V i3  supplied through bipolar transistors Q 15 , Q 16 , and bias circuits 19, 20. 
     The phase inverting circuit 14 is formed by the bipolar transistors Q 12  -Q 14  and resistances R 15  -R 17 , the predetermined base control voltage V b6  (for example, 1.85 V) is supplied to the base of bipolar transistor Q 14  and thereby it forms a constant current circuit together with the resistance R 17 . As described the phase inverting circuit 14 inverts the phase of the complementary digital input signals V i2 , V i3  and outputs such signals to the emitter follower output circuits 15, 16. 
     The emitter follower output circuits 15, 16 are respectively formed by the emitter follower transistors Q 17 , Q 18 . The emitters of emitter follower transistors Q 17 , Q 18  are respectively connected to the power source voltage V ee  through the pull-down transistors Q 19 , Q 20  described later and also connected to the load capacitance CL 2  generated equivalently by the distributed capacitance of the output wirings. 
     The active pull-down circuits 17, 18 are respectively formed by the pull-down transistors Q 19 , Q 20 . The pull-down transistors Q 19 , Q 20  are emitter loads of the emitter output circuits 15, 16 and switchingly connect the output of emitter follower transistors Q 17 , Q 18 , namely the digital output signals V o6 , V o7  of the logic circuit LOG 3  respectively to the power source voltage V ee .. 
     The differential capacitances C a4 , C a5  differentiate the in-phase signals of the digital input signals V i2 , V i3  supplied through the bipolar transistors Q 15 , Q 16 . when the respective digital input signals V i2 , V i3  rise to the high level from the low level and conductively drive the pull-down transistors Q 19 , Q 20  temporarily. 
     The bias circuits 19, 20 comprise the resistances R 22 , R 23  which feed the voltages of digital output signals V o6 , V o7  back to the bases of pull-down transistors Q 19 , Q 20  and the resistances R 20 , R 21  which pull down the bases of pull-down transistors Q 19 , Q 20  to the side of emitter. 
     The bipolar transistors Q 15 , Q 16  form the emitter follower to the respective digital input signals V i2 , V i3 , buffer-amplify the digital input signals V i2 , V i3  in the in-phase condition and then sends such signals to the differential capacitances C a4 , C a5 . 
     As described previously, the power source voltages V ee , V ee1  are negative power source voltages and set, for example, to -2 V, -3 V, respectively. In addition, the power source voltage V cc  is the ground potential as described previously. 
     Operations of logic circuit LOG 3  thus configurated as described above will be explained hereunder. 
     In FIG. 23, when the digital input signal V i2  is low level, the base input of the emitter follower transistor Q 17  of the emitter follower output circuit 15 becomes high level. Thereby, the emitter follower transistor Q 17  is conductively driven and the digital output signal V o6  becomes high level. In this timing, the pull-down transistor Q 19  keeps the non-conductive condition. 
     Here, when the digital input signal V i2  changes to the high level from the low level, the base input of the emitter follower transistor Q 17  becomes the low level from the high level and the emitter follower transistor Q 17  is Changed to the non-conductive condition from the conductive condition. In this case, when the digital input signal V i2  rises to the high level from the low level, a charging current I 3  of the differential capacitance C a4  flows into the pull-down transistor Q 19 . 
     Accordingly, the pull-down transistor Q 19  becomes conductive temporarily while the emitter follower transistor Q 17  changes to the conductive condition from the non-conductive condition, forcing the charges of load capacitance C L2  to quickly discharge. Thereby, the digital output signal V o6  immediately falls to the low level from the high level after the digital input signal V i2  changes to the high level from the low level. 
     In the same way, the digital output signal V o7  also falls immediately to the low level from the high level after the digital input signal V i3  changes to the high level from the low level. 
     As described previously, when the digital output signals V o6 ,V o7  fall to the low level from the high level, the pull-down transistors Q 19 , Q 20  are temporarily set to the conductive condition with the differential output. Thereby, the load capacitance CL 2  is forced to discharge and the digital output signals V o6 , V o7  quickly fall. In other cases, the pull down transistors Q 19 , Q 20  are kept at the non conductive condition and a current steadily consumed is kept small. 
     Further, in the logic circuit LOG 3 , the base bias condition of pull-down transistors Q 19 , Q 20  changes depending on the load condition of the digital output signals V o6 , V o7 . Namely, when a load capacitance CL 2  is still charged with remaining charges, the conductive driving level of the pull-down transistors Q 19 , Q 20  is enhanced because the high voltage by the remaining charges increases the base bias level of the pull-down transistors Q 19 , Q 20 . Thereby, the pull-down effect, namely the effect of lowering the digital output signals V o6 , V o7  can also be enhanced. 
     In addition, when the digital output signals V o6 , V o7  are high level, a charging current I 4  is supplied to charge the differential capacitances C a4 , C a5  output signals V o6 , V o7 . Therefore, the charging current for driving the pull-down transistors Q 19 , Q 20  from the differential capacitances C a4 , C a5  also increases by DC feedback of the voltage of digital output signals V o6 , V o7  to the base to pull-down transistors Q 19 , Q 20 . 
     Thereby, good falling characteristic of the logic circuit LOG 3  comprising the emitter follower output circuits 15, 16 can be obtained without relation to change of load capacitance CL 2 . 
     FIG. 24 shows an embodiment indicating a third logic circuit to which the present invention is applied. 
     In FIG. 24, the emitter follower output circuit 15, active pull-down circuit 17, bias circuit 19 and differential capacitance C a4  correspond to those of embodiment shown in FIG. 23 and operate in the same way. 
     Moreover in FIG. 24, the logic circuit LOG 4  is formed by the D latch circuit 21 which is configurated using the clocked gate by the 2-stage cascade differential circuit consisting of the bipolar transistors Q 21  -Q 25  and resistances R 24  -R 26  and emitter follower output circuit formed by the bipolar transistors Q 28 , Q 29  which provide outputs of D latch circuit 14 as the latch outputs Q, Q, and the resistances R 27 , R 28 . 
     The D latch circuit 21 executes the D latch operations by the internal feedback of outputs of clocked gate through the emitter follower by the emitter follower transistor Q 17 . The bipolar transistor Q 25  forms a constant current source, together With the resistance R 26 , by receiving the predetermined base control voltage V b7  (for example, -1.85 V). The digital input signal V i4  is data input; CK is clock input; +Q, -Q are latch outputs; V ref2 , V ref3  are reference voltages and V ee1 , V ee  are negative power source voltages. 
     Here, the emitter of emitter follower transistor Q 17  forming the emitter follower output circuit 15 within the D latch circuit is connected with the pull-down transistor Q 19 . In addition, the base of pull-down transistor Q 19  is Self-biased, as in the case of the embodiment of FIG. 23, with the resistance R 22  and receives the charging current of the differential capacitance C a4  from the side of D latch circuit 21. 
     Thereby, the D latch circuit 21 of the logic circuit LOG 4  described above is capable of executing the high speed data latch operation by improvement of falling characteristic of the emitter follower output circuit 15 provided in the feedback path in such D latch circuit 21. Moreover, since the bipolar transistor Q 21  and pull-down transistor Q 19  are resistive to the α-ray like the bipolar transistor Q 1  and pull-down transistor Q 3  shown in FIG. 1, the D latch circuit 21 executes highly reliable holding operation. 
     FIG. 25 shows an embodiment of the fourth logic circuit to which the present invention is applied. 
     In FIG. 25, the emitter follower output circuits 15, 16, active pull-down circuits 17, 18, bias circuits 19, 20, differential capacitances C a4 , C a5  respectively correspond to those of embodiment shown in FIG. 23 and operate in the same way. 
     Referring to FIG. 25, the logic circuit LOG 4  is formed by a current switching circuit 22 consisting of the bipolar transistors Q 30  -Q 33  and resistances R 29  -R 31 , emitter follower output circuits 15, 16 respectively providing output of the current switching circuit, active pull-down circuits 17, 18, bias circuits 19, 20 and differential capacitances C a4 , C a5 . 
     The current switching circuit 22 provides an output respectively to the emitter follower transistors Q 17 , Q 18  in accordance with the digital input signals V i5 , V i6  and reference voltages V ref4 . The bipolar transistor Q 33  receives the predetermined base control voltage V b8  (for example, 1.85 V) and forms a constant current source in combination with the resistance R 32 . As described above, output of current switching circuit 22 is output by the emitter follower of the emitter follower transistors Q 17 , Q 18  as the digital output signals V o8 , V o9 . 
     Respective digital output signals V o8 , V o9  are connected by switching to the power source voltage V ee   in the low level side by the pull-down transistors Q 19 , Q 29 . 
     On the other hand, the differential capacitance C a4  differentiates the rising edge of digital output signal V o9  and supplies the charging current to the base of pull-down transistor Q 19  to temporarily drive the transistor. Meanwhile, the differential capacitance C a5  differentiates the rising edge of digital output signal V o10  and supplies the charging current to the base of pull-down transistor Q 20  in order to temporarily drive the transistor. 
     Moreover, in the pull-down transistors Q 19 , Q 20 , the bias is applied depending on the load capacitance CL 2  by the feedback of the voltage of digital output signals V o8  V o9  to the base through the resistance R 22 , R 23  and by the pull-down of the base to the emitter side through the resistances R 20 , R 21 , and simultaneously the differential output generated when the differential capacitances C a4 , C a5  are charged respectively to the digital output signals V o8 , V o9 , is enhanced because the differential capacitances C a4 , C a5  are charged from the side of digital output signals V o8 , V o9  when the these digital output signals are high level. 
     Thereby, as in the case of the embodiment of FIG. 23 described above, the rising characteristic of the digital output signals V o8 , V o9  output as the complementary signal can be improved. 
     FIG. 26 indicates an embodiment of the fifth logic circuit to which the present invention is applied. 
     In FIG. 26, the logic circuit LOG 6  is a modification of the embodiment shown FIG. 25 and has the same basic configuration. Explanation will be made focusing on the difference from FIG. 25. The logic circuit LOG 6  includes the complementary signal circuit 23 in which the digital input signals V i5 , V i6  are negative input of V i5  and the complementary signal can be formed by high level or low level of the digital input signal V i5  and the constant current source which is formed by the bipolar transistor Q 31  and resistance R 31  shown in FIG. 25 is designated by IS 2 . Moreover, the bias circuits 24, 25 are formed by the bipolar transistors Q 34 , Q 35  in place of the resistances R 22 , R 23  different from the bias circuits 19, 20 of the embodiment shown in FIG. 25 and the resistances R 20 , R 21  shown in FIG. 25 are indicated as the resistances R 33 , R 32 . 
     FIG. 27 is a schematic plan view of a large capacity gate array integrated circuit to which the present invention is applied. FIG. 28 indicates an embodiment in which the cell of large capacity gate array integrated circuit of FIG. 27 is designated by the logic circuit LOG 1  of FIG. 14. FIG. 29 indicates a sectional view of the semiconductor chip forming a large capacity gate array integrated circuit shown in FIG. 27 sealed with the microchip carrier. 
     FIG. 30 indicates a sectional view in which a capacitance chip is formed on the carrier shown in FIG. 29. FIG. 31 shows that the microchip carrier shown in FIG. 29 is mounted on the mounting substrate. 
     In FIG. 27, a large capacity gate array GA allows, although not particularly limited, arrangement of many basic cells at the internal side of input/output buffer region I/O formed by the ECL circuit. Each basic cell forms the logic circuit, for example, the logic circuit LOG 1  shown in FIG. 5, FIG. 8, FIG. 10, FIG. 14, FIG. 16, FIG. 18, FIG. 19, FIG. 22, logic circuits LOG 3  -LOG 6  shown in FIG. 23 - FIG. 26 or logic circuit LOG 2  shown in FIG. 13. The unused cell cell&#39; of the basic cells is the capacitive cells in order to prevent malfunction under the steady state of the pull-down transistor shown in the explanation for FIG. 14. Moreover, in the large capacity gate array integrated circuit GA, the capacitive element CE is formed between the basic cells Cell in order to prevent malfunction described above. Moreover, the large capacity gate array GA is provided with a base control voltage generating circuit 24 in order to form the base control voltage V b1  (V b4 ) in accordance with the control voltage V c  supplied from the external terminal In case the logic circuit of each embodiment is formed with the large capacity gate array integrated circuit GA, many logic circuits can be formed with high density due to the high speed operation characteristic and low power consumption characteristic. In addition, since the wired logic can be formed, the application efficiency of the logic circuit can be remarkably enhanced and a very large scale and high performance semiconductor integrated circuit device can be obtained efficiently with the gate array configuration. 
     In FIG. 28, the left logic circuit is designated as LOG 1 , while the right logic circuit as LOG 1&#39; . Many logic circuits LOG 1  are connected between the power source voltage V cc2  and V ee3 . Moreover, the inductances L 1 , L 2  are inductance of CCB bump electrode 29 shown in FIG. 29, while the inductances L 3 , L 4  are inductance of carrier 25A shown in FIG. 29. Moreover, the capacitance C a6  is the capacitance in the chip and is equal to the capacitance of the capacitance element CE and unused cell cell&#39; shown in FIG. 27 and the capacitance C a7  is the capacitance of carrier 25A shown in FIG. 29, namely the layered capacitance 32 or capacitance chip 33 shown in FIG. 29 and FIG. 30. 
     In FIG. 28, when the digital output signal V o1  of logic LOG 1  falls to the low level from the high level, the pull-down transistor Q 3  is temporarily driven conductively as described previously. In this case, since the emitter follower transistor Q 2  is not yet sufficiently driven non-conductively, a current I 5  temporarily flows. The power source voltage V ee3  changes according to being flow the current I 5  to the inductances L 1 , L 2 , L 3  and L 4  therefore the pull-down transistor Q 3  is conductively driven due to change of emitter voltage of such pull-down transistor Q 3  at the steady state of the logic circuit connected to the power source voltages V cc2  and V ee3 , for example, the logic circuit LOG 1&#39; , resulting in possibility of malfunction. However, in this embodiment, many logic circuits LOG 1  are connected between the power source voltages V cc2  and V ee3 . The pull-down transistor Q 3  under the steady state of the logic circuit LOG 1  is in the very weak ON condition and the collector current I c3  is about 10-100 μA as described previously. Moreover, since the emitters of pull-down transistors Q 3  of a plurality of logic circuits LOG 1  are connected in common to the power source voltage V ee3 , a kind of emitter coupled circuit is formed. In addition, a small number of pull-down transistors Q 3  are conductively driven simultaneously in the large capacity gate array GA. Therefore, since a part of through current I 5  flows onto a loop like the current I 6 , the through current flowing into the inductances L 1 , L 2 , L 3  and L 4  decreases, suppressing variation of power source voltage V ee3 . However, since the logic circuit LOG 1  is a super high speed circuit, variation of power source voltage V ee3  is suppressed and moreover the chip capacitance C a6  of the large capacity gate array integrated circuit GA and the capacitance C a7  of the carrier 25A shown in FIG. 29 and FIG. 30 are formed in the large capacity gate array integrated circuit GA of this embodiment. A part of the through current I 5  further flows on the loop current I 6 , I 7 , I 8  and thereby variation of power source voltage V ee3  is suppressed. 
     In FIG. 29, 25 designates microchip carrier; 25A, carrier for mounting chip; 25B, cap; 26, 27, solder; 28, semiconductor chip; 29, CCB (Controlled Collapse Bonding) bump electrode; 30, bump electrode for mounting; 31, wiring. The arrow mark at the end of leader line indicates the entire part of microchip carrier 25. 
     The CCB bump electrode 29 is connected to the input/output terminal of gate array integrated circuit GA and power source terminals of power source voltages V cc  and V ee  and is also connected to the bump electrode 30 for mounting through the wiring 31. 
     The microchip carrier 25 of this embodiment forms a layered capacitance 32 on the chip mounting carrier 25A in order to prevent malfunction under the steady state of the pull-down transistor Q 3 . 
     The CCB bump electrode 29 is described in the Japanese Laid-open Patent No. 62-249429 and the microchip carrier 25 is described in the Japanese Patent Application No. 62-146397. 
     In FIG. 30, the basic configuration is the same as that of microchip carrier 25 shown in FIG. 29. Focusing on difference from the microchip carrier 25 of FIG. 29, this embodiment prevents malfunction of the pull-down transistor Q 3  under the steady state by not forming the layered capacitance 32 on the carrier 25A, forming the capacitance chip 33 on the carrier 25A and connecting such chip to the wiring 31 through the CCB bump electrode 29. 
     In FIG. 31, 34 designates a mounting substrate; 35 is pin. Many microchip carriers 25 are mounted on the substrate 34 as shown in FIG. 31. The mounting bump electrode 30 is connected to the pin 35 by a plurality of wired layers (not illustrated) included in the substrate 31. The substrate 34 is sealed by the cap, although not illustrated. 
     As described, in the large capacity gate array integrated circuit GA of this embodiment, a plurality of logic circuits LOG 1  are provided between the power source voltages V cc2  and V ee3  in order to prevent malfunction of the pull-down transistor Q 3  under the steady state due to variation of the power source voltage V ee3 . In addition, such malfunction can be further prevented by forming capacitance on the chip 28 and carrier 25A. Moreover, such malfunction is prevented more successfully by sealing the package of the large capacity gate array integrated circuit GA by the method in which the microchip carrier 25 is sealed using the CCB bump electrode 29 having smaller inductance than that in the method using the lead wire. Moreover, since the base control voltage V b1  (V b4 ) of the bias circuits 4 and 8 and bipolar transistors Q 4  and Q 10  can be controlled by changing the control voltage VC shown in FIG. 27. Accordingly, the falling time of the digital output signal V o1  of the logic circuit LOG 1  can be delayed, for testability of the large capacity gate array integrated circuit GA, by controlling the bias voltage V b  (V b&#34; ) of the pull-down transistor Q 3 . 
     As explained in the embodiments above, in case the present invention is applied to the large capacity gate array or high speed logic integrated circuit basically configurated by the NTL circuit or ECL circuit, following effects can be obtained. 
     (1) The load means can be temporarily short-circuited at the beginning of the low level output and level of output signal can be changed quickly by providing the pull-down transistor which is capacitively connected to the emitter of the transistor receiving the input signal at its base and temporarily shows a large conductance for the low level output. 
     (2) With the item (1), following effect can be obtained. Namely, good response characteristic of input pulse to the NTL circuit can be obtained and level change at the rising and falling edges is almost equal. The high load driving capability for the NTL circuit can be realized and the output signal in the range from light to heavy load can be changed quickly by forced removable of capacitance of load means for the low level output with the pull-down transistor. Since the pull-down transistor such as NTL circuit shows high impedance under the steady state, a wired OR circuit which does not easily generate electromigration can be formed. Employment of the NTL circuit having the configuration indicated in the item (1) results in resistivity to the α-ray. With use of the NTL circuit of the configuration described above, the pull-down transistor can be formed without use of a particular element such as PNP transistor and output signal level can be changed quickly. Since the pull-down transistor can be formed on a single semiconductor substrate together with the other circuit elements, high speed level change of the output signal can be realized by the device technology. Since the NTL circuit is a low amplitude circuit, operation rate can further be improved. Low power consumption of the NTL circuit can be attained by making large the resistance value of load means and making small an operation current of the output emitter follower circuit. 
     (3) Following effects can be obtained from the items (1) and (2). The NTL circuit is a low voltage circuit and low power consumption can also be realized for the NTL circuit. Since the rising and falling times of output signal are almost equal, simplified delay calculation of the NTL circuit can be realized easily and dependence on the input waveform of the circuit operation rate of NTL circuit can be reduced. The load driving capability of the NTL circuit can further be improved by providing the bias circuit to the base of pull-down transistor of the NTL circuit of the configuration described above. The low power consumption can also be realized without interfering the high speed operation of the NTL circuit. 
     (4) Following effects can be obtained from the items (1) to (3). The load driving capability of NTL circuit and falling rate of output signal can be set adequately by providing adequate capacitance between the pull-down transistor and the transistor receiving the input signal. The load driving capability of NTL circuit and falling rate of output signal can be changed by configurating the bias circuit with the transistor to be controlled with the predetermined base voltage and changing the predetermined base voltage in accordance with the control voltage supplied from the external terminal and variation of speed of a plurality of NTL circuits can be suppressed and the testability efficiency of the large capacity gate array integrated circuit formed by the NTL circuit can be improved. The falling rate of output signal can always be improved effectively irrespective of external environment of the load means of the NTL circuit by forming the bias circuit with the resistance which feeds back the output signal. The circuit configuration described above can also be used in the gate circuit or latch circuit by ECL circuit in addition to the NTL circuit, resulting in wide range operation principle of the present invention. 
     (5) From the items (1) to (4), high integration density can be realized because the lower power consumption can be realized without impeding high speed operation of the high speed logic integrated circuit including the NTL circuit. 
     While the present invention has been explained based on the embodiment thereof, the present invention is naturally not limited and allows various changes or modifications without departure from the scope of the invention. 
     For example, in each embodiment, the high level V H  and low level V L  of the digital input signals V i1  -V i6  and digital output signals v o1  -V o9  can be set to the desired levels. In addition, the power source voltage V cc  of circuit may be replaced with a positive source source voltage by setting the power source voltage V ee  of circuit to the ground potential and the polarity thereof can also be inverted by replacing the bipolar transistor with the PNP transistor. The phase split circuit 1, phase inversion circuit 14, D latch circuit 21, current switching circuit 22 and complementary signal circuit 23 shown in the embodiments of FIG. 5, FIG. 8, FIG. 10-FIG. 14, FIG. 16-FIG. 19 and FIG. 22-FIG. 26 may be formed using the NOS (metal-oxide-semiconductor) transistor, and a speed-up capacitance may be provided to the resistance R 3  to be provided between the emitter of bipolar transistor Q 1  forming the phase split circuit 1 and the power source voltage V ee  in the embodiment shown in FIG. 5, FIG. 8, FIG. 10-FIG. 14, FIG. 16-FIG. 19 and FIG. 22. Moreover, the embodiments shown in FIG. 10, FIG. 14 and FIG. 22 are capable of providing a desired number of fan-in by replacing the bipolar transistor Q 1  forming the phase split circuit 1 with a plurality of transistors connected in parallel. In FIG. 18, the base of pull-down transistor Q 23  forming the active pull-down circuit may be coupled directly to the nodes connected in common of the resistances R 10  and R 11  without passing through the resistance R 12 . In FIG. 19, the diode D 1  provided between the bipolar transistor Q 4  forming the bias circuit 3 and the power source voltage V cc  of the circuit may be replaced with a plurality of diodes or transistors in accordance with the level of constant voltage V b3  and the capacitance C a2  may be removed. In addition, combination of a practical circuit configuration and power source voltage in each embodiment can employ various forms. 
     In the above explanation, the inventions by the inventors of the present invention are applied to the NTL circuit and ECL circuit of the gate array which is the application field as the background of the present invention, but the application field is not limited thereto and the present invention can also be applied, for example, to the semiconductor integrated circuit device such as MPU (microprocessor) of which application field is fixed. The present invention can be applied at least to the logic circuit including the output emitter follower circuit or various kinds of semiconductor integrated circuit device including such logic circuit. 
     Another aspect of the present invention will now be discussed As noted previously, a conventional logic circuit such as the ECL circuit having an emitter follower output transistor can have a good rising characteristic of the signal by virtue of the low output impedance of the emitter follower output transistor. However, since the falling characteristic of the signal is dependent on the time constant determined by the capacitance of the load and the resistance of the emitter follower, an LSI for a gate array designed to achieve high-speed operation and high packaging density inevitably consumes a great amount of power. Therefore, an active pull-down circuit is proposed, for example, in the gazette of Japanese Laid-Open Patent Publication No. 50-134356, which circuit improves the falling characteristic of the output signal of an emitter follower output circuit while it keeps low the power consumption in the steady state. 
     There is also an NTL circuit which, different from such as the above described ECL circuit discriminating between high level and low level by reference to the threshold voltage, has no special logic threshold. In the NTL circuit, the signal is amplified by being passed through a plurality of gate circuits. When input/output transfer characteristics of a plurality of gate circuits cross virtually at the center voltage, an input level higher than the cross point is progressively amplified and finally converges to the high level side. In a logic gate circuit, a plurality of logic gates are arranged in multiple stages, and therefore, even if there is fluctuation of the transfer characteristic in the NTL circuit, level correction is achieved by passing a signal through other logic gates having similar fluctuation and, therefore, fluctuation of the transfer characteristic practically poses no problem. Such NTL circuit is described, for example, in Genji Baba, &#34;Modern Dictionary of Electronic Devices&#34;, published by Radio Technology Company on Mar. 20, 1976, p. 72. As patents relating to NTL circuits, there are those disclosed in Japanese Patent Publication Nos. 42-21132, 42-2294, and 45- 32005 published respectively in 1967, 1967 and 1970. 
     In FIG. 39 is shown a circuit diagram of an example of an ECL circuit provided with an active pull-down circuit which the present inventors investigated. A transistor Q44 provided for an emitter-follower output transistor Q33, in the steady state, is biased to its base-emitter voltage V BE  by a bias circuit made up of a resistor R48 and a transistor Q45 so that virtually no current is passed therethrough. At the time when the signal is changed and thereby the transistor Q43 is switched from on state to off state, the transistor Q44 is turned on by a signal with reverse phase transmitted from an emitter-follower transistor Q49 through a capacitor C41, and thereby, the output terminal OUT is quickly discharged. 
     However, if the signal level should change while the discharging through the capacitor C41 is going on, a sufficient falling characteristic of the output signal would not be obtained. In order to obtain a sufficient falling characteristic of the output signal, it is necessary to take such measures as to increase the capacitance of the capacitor C41 or increase the steady-state current flowing through the transistor Q44. If such measures are taken, however, there arise problems of fluctuation of the falling characteristic of the output signal, deterioration in the rising characteristic due to undershooting made by the output signal, and increase in the power consumption, which the present inventors found out through their investigation. 
     Accordingly, another object of the present invention is to provide a logic circuit which, while keeping power consumption low, achieves high-speed signal outputting. 
     This and other objects and novel features of the present invention will become apparent from the description given hereinbelow and the accompanying drawings. 
     A representative aspect of this aspect of the present invention is as follows. An emitter follower output transistor receiving an output signal generated by the logic portion is connected in series with an active pull-down transistor supplied, at the base, with a signal, which has reverse phase to that of the input signal supplied to the base of the output transistor, through a capacitance element. Between the base and emitter thereof, there is provided a bias circuit formed of a transistor supplied with a predetermined bias voltage and an emitter resistor, and there is further provided a capacitance element for feeding back the output signal to the emitter of the transistor forming the bias circuit. 
     According to the above-described arrangement, the base potential of the active pull-down transistor, at the time of the fall of the output signal, is lowered by the turning on of the bias transistor caused by the signal given thereto through the feedback capacitance element, and thereby, excessive action of the active pull-down transistor is suppressed and, hence, occurrence of undershooting of the output can be prevented. 
     FIG. 34 shows a circuit diagram of an embodiment in which an active pull-down circuit according to the present invention is applied to an NTL circuit. Circuit elements in the diagram are formed on one semiconductor substrate of single crystalline silicon or the like by known fabrication technology of bipolar integrated circuit. 
     The circuit formed of transistors Q41 and Q42 receiving signals from input terminals IN1 and IN2, a resistor R41 provided for the collectors connected with each other of the transistors Q41 and Q42 and a resistor R42 for the emitters connected with each other of the same constitutes an NTL circuit. More specifically, when the signal at the input terminal IN1 or IN2 is high, the transistor Q41 or Q42 is turned on, whereby an output signal determined by the ratio of resistance between the resistors R41 and R42 at a level as low as approximately -0.5 V is produced, and when the signals at the input terminals IN1 and IN2 are both low, both the transistors Q41 ad Q42 are turned off, whereby a signal b at a level as high as 0 V is generated at the collector. Hence the NTL circuit constitutes a two-input NOR gate logic circuit. 
     The collector output signal b of the transistors Q41 and Q42 is supplied to the base of an emitter-follower output transistor Q43. The transistor Q43 has its emitter connected in series with an active pull-down transistor Q44. The base of the transistor Q44 is supplied with an output signal c with reverse phase obtained from the emitter of the transistors Q41 and Q42 through a capacitor C41. In order to pass a relatively small idling current through the transistor Q44 in the steady state, a bias circuit as described below is provided. 
     Between the base and emitter of the transistor Q44, there are inserted a transistor Q46 receiving a predetermined bias voltage VB2 and its emitter resistor R44. Further, to the base of the transistor Q44 is connected the emitter of a transistor Q45 receiving a predetermined bias voltage VB1. The collector of the transistor Q45 is connected with the ground potential point. 
     Further, in order to prevent occurrence of an undershoot of the output signal, there is provided in the present embodiment a capacitor C42 allowing the output signal to be fed back to the emitter of the bias transistor Q42. 
     For example, when the signals at the input terminals IN1 and IN2 are both at low level and hence both the transistors Q41 and Q42 are in the off state, their collector output becomes as high as 0 V, the ground potential. This high level is subjected to a level shift through the base and emitter of the emitter-follower output transistor Q43, and as a result, the potential at the output terminal OUT is brought to a level as high as approximately -0.8 V. 
     From this state, if the signal a at the input terminal IN1 changes from low level to high level, the output signal b changes from high level to low level. As a result, the output transistor Q43 is virtually put into an off state and the output signal c with reverse phase obtained from the emitter of the transistor Q41 is changed from low level to high level, and this change to high level causes, through the capacitor C41, the base potential of the transistor Q44 to he temporarily held high. Thereby, the transistor Q44 is turned on and the output signal d of the output terminal OUT is quickly changed from high level to low level. Then, this change causes, through the capacitor C42, the emitter potential of the transistor Q46 to go to low level in a manner as if it were an A.C. wave. Thereby, a collector current flows through the transistor Q46, and this causes the base potential of the transistor Q44 to lower. In other words, the high potential transmitted from the capacitor C41 to the base of the transistor Q44 in accordance with the change of the signal c to high level is repressed by the low level signal fed back through the capacitor C42. Thus, an undershoot of the output signal d is prevented from occurring. 
     Since the occurrence of the undershoot of the output signal d can be prevented as described above, it becomes possible to set the capacitance of the capacitor C41 to a considerably high value for improvement of the falling characteristic to the low level of the signal d and yet to prevent occurrence of the undershoot of the signal d by the feedback control with the capacitor C42. This means in substance that the rising characteristic of the base potential of the transistor Q44 can be prevented from deteriorating. 
     For the capacitor C41, a relatively large capacitance value can be set up without substantially increasing the layout area by utilizing the base take-out electrode of the transistor Q42. Also for the feedback capacitor C42, the take-out electrode of the emitter of the transistor Q46 and others can be utilized so as to achieve reduction in the layout area. 
     The operating voltage supply for the output circuit through which a relatively large current flows can be arranged separate from thai for the input logic portion through which a relatively small current flows. That is, the separation is made such that the power source lines for the input logic portion are comprised of Vcc and -VEE, while those for the output portion are comprised of Vcc&#39; and -VEE&#39;. By virtue of such arrangement, the level margin of the signal can be prevented from being degraded by noises which are produced in the power line Vcc&#39; or -VEE&#39; during the operation of the output circuit and transmitted to the input logic portion. 
     FIG. 35 shows a circuit diagram of another embodiment in which an active pull-down circuit according to the present invention is applied to an NTL circuit. 
     In this embodiment, the output signal d is fed back to the base of the transistor Q45 through a capacitor C43. Though not limitative, the bias voltages supplied to the bases of the transistors Q46 and Q45 are provided by a series circuit of diodes D41 and D42 and a resistor R45. More specifically, the base of the transistor Q46 is supplied with a forward voltage V F  across the diode D41 The base of the transistor Q45 is supplied with a forward voltage 2 V F  across the diodes D41 and D42. The resistor R45 forms a constant bias current to be passed through the diodes D41 and D42. That is, a constant current -(VEE-2 V F )/R45 is passed through the resistor R45 and this constant current is passed through the transistors Q45 and Q46. 
     In the described arrangement, the circuit producing the bias voltages VB1 and VB2 can be formed of such simple circuit elements as the resistor R45 and the diodes D41 and D42. 
     The feedback capacitor C43 improves the rising characteristic of the output signal d. More specifically, when the output signal d goes from low level to high level, this change in level acts through the capacitor C43 on the transistor Q45 to raise its base potential. Thereby, the action of the capacitor C41 when the level of the signal c with reverse phase changes from high level to low level exerted on the transistor Q4 to lower its base potential is repressed. Generally, when the base potential of the transistor Q44 goes lower than that in the steady state, the transistor Q44 is turned on after the steady state has been restored. Hence, the response characteristic when the signal c is quickly changed from low level to high level is deteriorated. In the present embodiment, by virtue of the feedback signal transmitted through the capacitor C43, the base potential of the transistor Q44, when the output signal d goes high, is prevented from going lower than the bias point by the action exerted thereon through the capacitor C41. 
     Thus, in the present embodiment, the response characteristics to the switched input are greatly improved by means of the feedback capacitors C42 and C43. 
     FIG. 36 shows a circuit diagram of a further embodiment in which an active pull-down circuit according to the present invention is applied to an NTL circuit. 
     When an active pull-down circuit is used, it is required to provide a circuit to generate a bias voltage VB1 allowing an idling current to flow through the pull-down transistor Q44 as described above. The bias circuit in the present embodiment is structured of diodes D41 and D42 and a resistor R45 in series connection, the same as that used in the above described embodiment. 
     More specifically, a forward voltage 2 V F  produced by the diodes D41 and D42 is supplied to the base of the transistor Q45. Thus, the transistor Q45 and the diodes D41 and D42 are arranged in a current mirror configuration and it is made possible to allow a constant current provided by the resistor R45 to flow through the transistors Q45 and Q44. With such arrangement, the bias circuit when the active pull-down circuit is used can be simply structured. 
     FIG. 37 shows an embodiment in which an active pull-down circuit according to the present invention is applied to an ECL circuit. 
     In the ECL circuit, an output signal and a signal with reverse phase are obtained from a differential transistor circuit. Accordingly, the signal with reverse phase to be transmitted to the base of the active pull-down transistor Q44 is obtained from the emitter of an emitter follower output transistor Q49 receiving the collector output of an inverting output transistor Q47 supplied with a reference voltage VBB. 
     In the present case, the load resistor in the differential transistor circuit is divided into two, RC2 and RC3, whereby the level of the signal transmitted to the base of the active pull-down transistor Q44 through the capacitor C41 is set up, and the response characteristic of the base of the active pull-down Q44 can be optimally set up. Thus, the undershoot produced by an excessively high level of the signal transmitted to the base of the transistor Q44 through the capacitor C41 and excessive reverse biasing of the transistor Q44 at the timing of the rise of the output signal can be prevented from occurring. 
     The bias circuit of the present invention is structured of the diodes D41 and D42 and the resistor R45 connected in series the same as the bias circuit used in the above described embodiment. More specifically, a forward voltage 2 V F  produced by the diodes D41 and D42 is supplied to the base of the transistor Q45. Thus, the transistor Q45 and the diodes D41 and D42 are arranged in a current mirror configuration and it is made possible to allow a constant current provided by the resistor R45 to flow through the transistors Q41 and Q42. With such arrangement, the bias circuit when the active pull-down circuit is used can be simply provided. Instead of the above described arrangement, the bias circuit may be such that supplies a predetermined bias voltage VB1 to the base of the transistor Q45. 
     FIG. 38 shows a circuit diagram of another embodiment of an active pull-down circuit according to the resent invention applied to an NTL circuit. 
     In this embodiment, a diode D43 is used as a variable capacitance element for having the output signal fed back to the base of the active pull-down transistor Q44. In this arrangement, when the input signal IN1 goes high, the diode D43 is reversely biased and its capacitance value is decreased. Thereby, the portion escaping through the diode D43 out of the pulse current to be supplied to the base of the transistor Q44 through the capacitor C41 can be reduced. In contrast with this, when the input signal IN1 goes low, the lowering of the potential at the base of the transistor Q44 by the action exerted thereon through the capacitor C41 can be compensated for by the rise of the output signal at the output terminal OUT fed back thereto through the diode D43. At this time, the reverse bias voltage is lowered and, proportionally to it, the capacitance is increased, and hence a great fed back quantity can be obtained. In short, the diode D43 has the same function as that of the capacitor C43 in FIG. 2. In the case of the circuit of FIG. 35, the capacitor C43 and the capacitor C41 are separated by the transistor Q45 and no problem is posed. In the case of the present embodiment, since the capacitor C41 and the feedback capacitance element are in series connection, the signal to be transmitted to the base of the transistor Q44 through the capacitor C41 may escape to the output terminal side through the feedback capacitance element, but this escaping can be prevented by the use of the diode D43 as a variable capacitance element. 
     The transistor Q45 receiving the bias voltage VB1 is for allowing a bias current to flow through the transistor Q44 and the transistor Q45&#39;, and the resistor R44&#39;, provided for its emitter are for producing a bias voltage provided to the diode D43 as a reverse bias voltage so that it may act as the capacitance element. 
     Functional effects obtained from the above described embodiments are as follows: 
     (1) An emitter follower output transistor receiving an output signal generated by the logic portion is connected in series with an active pull-down transistor supplied, at the base, with a signal, which has reverse phase to that of the input signal supplied to the base of the output transistor, through a capacitance element. Between the base and emitter thereof, there is provided a bias circuit formed of a transistor supplied with a predetermined bias voltage and an emitter resistor, and there is further provided a capacitance element for feeding back the output signal to the emitter of the transistor forming the bias circuit. According to the above described arrangement, the base potential of the active pull-down transistor, at the time of the fall of the output signal, is lowered by the turning on of the bias transistor caused by the signal given thereto through the feedback capacitance element, and thereby, excessive action of the active pull-down transistor is suppressed and, hence, occurrence of undershooting of the output can be prevented while the falling characteristic of the output signal is improved. 
     (2) An emitter follower output transistor receiving an output signal generated by the logic portion is connected in series with an active pull-down transistor supplied, at the base, with a signal, which has reverse phase to that of the input signal supplied to the base of the output transistor, through a capacitance element. As a bias circuit provided for the base of the active pull-down transistor, a bias current supplying transistor whose emitter is connected with the base of the active pull-down transistor, two forward diodes disposed between the base of the bias current supplying transistor and the emitter of the active pull-down transistor, and a resistance element allowing a bias current to flow through the forward diodes. Thus, an effect is obtained that configuration of the circuit can be simplified. 
     (3) When the logic circuit is constituted of an ECL circuit, the load resistor for forming the reverse output signal in the differential transistor circuit is divided in two, whereby the signal level supplied to the base of the active pull-down transistor is made adjustable. Thus, an effect is obtained that setting for optimal operation of the active pull-down transistor can be achieved with a simple circuit configuration. 
     While the invention made by the present inventor has been described concretely as related to some embodiments, it is apparent that the present invention is not limited to the above described embodiments but various modifications may be made without departing from the spirit of the present invention. For example, in the circuits of embodiments in FIG. 34 and FIG. 35, the input logic portion may be replaced by an ECL circuit. The load resistor RL provided for the output terminal OUT in the circuit for each embodiment is just for generally representing a load and it does not mean that such a resistance element is connected. The power supply lines and operating voltages of the logic portion and the output portion may be separated according to the need. The number of the input terminals may he increased or decreased according to the need. 
     The present invention can he widely applied to logic circuits comprised of a high-speed logic portion such as NTL and ECL and an active pull-down circuit.