Patent Publication Number: US-2023163206-A1

Title: Semiconductor device and method for manufacturing semiconductor device

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application is based upon and claims the benefit of priority of the prior Japanese Patent Application No. 2021-189997, filed on Nov. 24, 2021, the entire contents of which are incorporated herein by reference. 
     FIELD 
     The embodiments discussed herein are related to a semiconductor device and a method for manufacturing a semiconductor device. 
     BACKGROUND 
     Conventionally, there is a nitride semiconductor device including a nitride semiconductor layer and an ohmic electrode in contact with a side surface of the nitride semiconductor layer, the side surface being a non-polar surface. Unevenness is formed in a surface of the nitride semiconductor layer, and the side surface is a side surface of a recess. The recesses are arranged in a checkered pattern or a stripe shape on the surface of the nitride semiconductor layer. 
     Japanese Laid-open Patent Publication No. 2008-227014 is disclosed as related art. 
     SUMMARY 
     According to an aspect of the embodiments, a semiconductor device includes: a substrate; an electron traveling layer provided above the substrate; an electron supply layer provided above the electron traveling layer; a gate electrode, a source electrode, and a drain electrode provided above the electron supply layer; a plurality of first protrusions that extend from a lower end of the source electrode through an inside of the electron supply layer to below an upper surface of the electron traveling layer, and that are formed of electrode material of the source electrode; and a plurality of second protrusions that extend from a lower end of the drain electrode through the inside of the electron supply layer to below the upper surface of the electron traveling layer, and that are formed of electrode material of the drain electrode, wherein a first volume ratio of the plurality of first protrusions in a first area where the plurality of first protrusions is provided is 60% or less, and a second volume ratio of the plurality of second protrusions in a second area where the plurality of second protrusions is provided is 60% or less. 
     The object and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the claims. 
     It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are not restrictive of the invention. 
    
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         FIG.  1 A  is a view illustrating a cross-sectional structure of a semiconductor device  100  of a first embodiment; 
         FIG.  1 B  is a view illustrating a cross-sectional structure of the semiconductor device  100  of the first embodiment; 
         FIG.  2 A  is an enlarged perspective view illustrating a part of an inside of the semiconductor device  100 ; 
         FIG.  2 B  is a view illustrating a cross-sectional structure of a part of the semiconductor device  100 ; 
         FIG.  3 A  is a view illustrating an offset amount X 1  of an end portion of a protrusion  160 S with respect to a source electrode  150 S of the semiconductor device  100 ; 
         FIG.  3 B  is a graph illustrating a relationship between the offset amount X 1  and a contact resistance Rc; 
         FIG.  4    is a graph illustrating a relationship between a volume ratio of the protrusion  160 S in an area  160 SA and the contact resistance Rc; 
         FIG.  5 A  is a view illustrating a position H in a height direction of a bottom surface of the protrusion  160 S; 
         FIG.  5 B  is a graph illustrating a relationship between the position H and the contact resistance Rc; 
         FIG.  6 A  is a view illustrating a width Wm and an interval Ws of the protrusion  160 S; 
         FIG.  6 B  is a graph illustrating a relationship between density of the protrusion  160 S and the contact resistance Rc; 
         FIG.  7 A  is a view for describing a method for manufacturing the semiconductor device  100 ; 
         FIG.  7 B  is a view for describing the method for manufacturing the semiconductor device  100 ; 
         FIG.  7 C  is a view for describing the method for manufacturing the semiconductor device  100 ; 
         FIG.  7 D  is a view for describing the method for manufacturing the semiconductor device  100 ; 
         FIG.  7 E  is a view for describing the method for manufacturing the semiconductor device  100 ; 
         FIG.  7 F  is a view for describing the method for manufacturing the semiconductor device  100 ; 
         FIG.  7 G  is a view for describing the method for manufacturing the semiconductor device  100 ; 
         FIG.  7 H  is a view for describing the method for manufacturing the semiconductor device  100 ; 
         FIG.  7 I  is a view for describing the method for manufacturing the semiconductor device  100 ; 
         FIG.  8 A  is a view illustrating a cross-sectional structure of a semiconductor device  100 A of a second embodiment; 
         FIG.  8 B  is a view illustrating a cross-sectional structure of the semiconductor device  100 A of the second embodiment; 
         FIG.  8 C  is a view illustrating a cross-sectional structure of a part of the semiconductor device  100 A; 
         FIG.  8 D  is a view for describing a method for manufacturing the semiconductor device  100 A of the second embodiment; 
         FIG.  8 E  is a view for describing the method for manufacturing the semiconductor device  100 A of the second embodiment; 
         FIG.  8 F  is a view for describing a method for manufacturing the semiconductor device  100 A of the second embodiment; 
         FIG.  8 G  is a view for describing the method for manufacturing the semiconductor device  100 A of the second embodiment; 
         FIG.  9 A  is a view illustrating a cross-sectional structure of a semiconductor device  100 B of a third embodiment; 
         FIG.  9 B  is a view illustrating a cross-sectional structure of the semiconductor device  100 B of the third embodiment; 
         FIG.  10 A  is a view illustrating a cross-sectional structure of a semiconductor device  100 C of a fourth embodiment; 
         FIG.  10 B  is a view illustrating a cross-sectional structure of a part of the semiconductor device  100 C; 
         FIG.  10 C  is a view for describing a method for manufacturing the semiconductor device  100 C of the fourth embodiment; 
         FIG.  10 D  is a view for describing the method for manufacturing the semiconductor device  100 C of the fourth embodiment; 
         FIG.  10 E  is a view for describing the method for manufacturing the semiconductor device  100 C of the fourth embodiment; 
         FIG.  10 F  is a view for describing the method for manufacturing the semiconductor device  100 C of the fourth embodiment; 
         FIG.  10 G  is a view for describing the method for manufacturing the semiconductor device  100 C of the fourth embodiment; 
         FIG.  10 H  is a view for describing the method for manufacturing the semiconductor device  100 C of the fourth embodiment; 
         FIG.  10 I  is a view for describing the method for manufacturing the semiconductor device  100 C of the fourth embodiment; 
         FIG.  11 A  is a view illustrating a cross-sectional structure of a semiconductor device  100 D of a fifth embodiment; 
         FIG.  11 B  is a view illustrating a cross-sectional structure of a part of the semiconductor device  100 D; and 
         FIG.  11 C  is a view illustrating a cross-sectional structure of a part of the semiconductor device  100 D. 
     
    
    
     DESCRIPTION OF EMBODIMENTS 
     By the way, regarding the existing nitride semiconductor device, there is no disclosure regarding a volume ratio of the ohmic electrode in an area where the recess is formed. The volume ratio affects a contact resistance between a source electrode and a drain electrode, and the semiconductor layer. 
     Therefore, an object is to provide a semiconductor device and a method for manufacturing the semiconductor device capable of reducing a contact resistance. 
     Hereinafter, embodiments to which a semiconductor device and a method for manufacturing the semiconductor device of the present disclosures are applied will be described. Hereinafter, components having substantially the same functional configuration are denoted by the same reference numerals, and redundant description may be omitted. 
     First Embodiment 
       FIGS.  1 A and  1 B  are views illustrating a cross-sectional structure of a semiconductor device  100  of a first embodiment.  FIG.  2 A  is an enlarged perspective view illustrating a part of an inside of the semiconductor device  100 .  FIG.  2 B  is a view illustrating a cross-sectional structure of a part of the semiconductor device  100 .  FIG.  1 A  is a cross section parallel to an entire XZ plane of the semiconductor device  100 , and illustrates a cross section corresponding to the cross section taken along line A-A in  FIG.  2 A .  FIG.  1 B  is a cross section parallel to the entire XZ plane of the semiconductor device  100 , and illustrates a cross section corresponding to the cross section taken along line B-B in  FIG.  2 A . Furthermore, since  FIG.  2 A  is a part of an inside of the semiconductor device  100 ,  FIG.  2 A  includes a cross section parallel to the YZ plane on −X direction side and a cross section parallel to the XZ plane on −Y direction side. To illustrate a structure in an easy-to-see manner, hatching is omitted. Furthermore,  FIG.  2 B  is a cross-sectional view illustrating a portion corresponding to a part of a width in a Y direction of the semiconductor device  100 , the portion being further enlarged as compared with the portion in  FIG.  2 A . Hatching is given to  FIG.  2 B . 
     Hereinafter, description will be given, defining an XYZ coordinate system. A direction parallel to an X axis (X direction), a direction parallel to a Y axis (Y direction), and a direction parallel to a Z axis (Z direction) are orthogonal to each other. The X direction is an example of a first direction, and the Y direction is an example of a second direction. Furthermore, hereinafter, for convenience of the description, the −Z direction side may be referred to as a lower side or below, and the +Z direction side may be referred to as an upper side or above. However, these references do not represent a universal upper-lower relationship. Plan view means to view an XY plane. Hereinafter, length, width, thickness, and the like of each part may be exaggerated so that the configuration can be easily understood. 
     Configuration of Semiconductor Device  100   
     The semiconductor device  100  includes a substrate  110 , an initial layer  111 , an electron traveling layer  120 , a spacer layer  130 , an electron supply layer  140 , a gate electrode  150 G, a source electrode  150 S, a drain electrode  150 D, a protrusion  160 S, a protrusion  160 D, and a passivation film  170 . The protrusion  160 S is an example of a first protrusion, and the protrusion  160 D is an example of a second protrusion. 
     The semiconductor device  100  is a GaN-based high electron mobility transistor (HEMT) in which the electron traveling layer  120  is formed of gallium nitride (i-GaN) without intentional doping of impurities and the electron supply layer  140  is formed of aluminum gallium nitride (AlGaN) or the like. Note that the electron supply layer  140  is not limited to AlGaN, and details will be described below. 
     Configuration of Substrate  110   
     As the substrate  110 , for example, a substrate of silicon carbide (SiC), silicon (Si), sapphire, gallium nitride (GaN), aluminum nitride (AlN), diamond, or the like can be used. 
     Configuration of Initial Layer  111   
     The initial layer  111  is provided on an upper surface of the substrate  110 . A nitride semiconductor is used for the initial layer  111 , and for example, AlN, GaN, AlGaN or a laminated structure thereof is used. The initial layer  111  is a nitride semiconductor layer that may be treated as a buffer layer, a strain relaxation layer, or a defect reduction layer. 
     Configuration of Electron Traveling Layer  120   
     The electron traveling layer  120  is a nitride semiconductor layer provided on an upper surface of the initial layer  111  and formed of i-GaN as an example. The electron traveling layer  120  is a layer on which a channel is formed. In the vicinity of an interface between the electron traveling layer  120  and the spacer layer  130 , a two-dimensional electron gas (2DEG)  120 A is generated by an action of piezoelectric polarization or spontaneous polarization in i-GaN. A position of the 2DEG  120 A is indicated by the broken line. A direction in which a current flows in the electron traveling layer  120  is the −X direction. 
     Configuration of Spacer Layer  130   
     The spacer layer  130  is provided on an upper surface of the electron traveling layer  120 , and is, for example, a nitride semiconductor layer formed of AlN or AlGaN. The spacer layer  130  is provided to suppress deterioration of electron mobility due to alloy scattering in the electron traveling layer  120  and to enable a large current. An interface between the spacer layer  130  and the electron traveling layer  120  is an interface between the channel and the spacer layer  130 . 
     Configuration of Electron Supply Layer  140   
     The electron supply layer  140  is provided on an upper surface of the spacer layer  130 , and is a nitride semiconductor layer formed of, for example, aluminum gallium nitride (AlGaN), indium aluminum nitride (InAlN), indium aluminum gallium nitride (InAlGaN), aluminum nitride (AlN), or scandium aluminum nitride (ScAlN). By arranging the electron supply layer  140  and the electron traveling layer  120  via the spacer layer  130 , the 2DEG  120 A is generated in the vicinity of the interface between the electron traveling layer  120  and the spacer layer  130 . A composition ratio of Al in the electron supply layer  140  is favorably 45% or more from the viewpoint of increasing an electron concentration. In the case of using such an electron supply layer  140  having a high Al composition ratio, it is favorable to provide the spacer layer  130 . 
     Configuration of Gate Electrode  150 G 
     The gate electrode  150 G is arranged so as to be connected to the electron supply layer  140  from above the passivation film  170  through a through hole penetrating the passivation film  170 . The gate electrode  150 G is made of, for example, a laminated film of nickel (Ni) as a first layer and gold (Au) as a second layer laminated on the first layer. As an example, the laminated film has Ni of 5 nm to 30 nm and Au of 100 nm to 300 nm. 
     Configuration of Source Electrode  150 S 
     The source electrode  150 S is provided on an upper surface of the electron supply layer  140  on the −X direction side of the gate electrode  150 G. The source electrode  150 S is made of, for example, a laminated film of titanium (Ti) as a first layer and Al as a second layer laminated on the first layer. As an example, the laminated film has Ti of 2 nm to 50 nm and Al of 100 nm to 300 nm. 
     Configuration of Drain Electrode  150 D 
     The drain electrode  150 D is provided on an upper surface of the electron supply layer  140  on the +X direction side of the gate electrode  150 G. Similar to the source electrode  150 S, the drain electrode  150 D is made of, for example, a laminated film of titanium (Ti) as a first layer and Al as a second layer laminated on the first layer. As an example, the laminated film has Ti of 2 nm to 50 nm and Al of 100 nm to 300 nm. 
     Configuration of Protrusion  160 S and Area  160 SA 
     The protrusion  160 S extends from a lower surface (lower end) of the source electrode  150 S through an inside of the electron supply layer  140  and the spacer layer  130  to below the upper surface of the electron traveling layer  120 , and is formed of an electrode material of the source electrode  150 S. The protrusion  160 S is provided to improve an ohmic contact of the source electrode  150 S. 
     A plurality of the protrusions  160 S is provided, and the plurality of protrusions  160 S is a plurality of thin plate-shaped protrusions extending in the X direction connecting the source electrode  150 S and the drain electrode  150 D in plan view and arrayed in the Y direction in plan view. Each of the plurality of protrusions  160 S is a thin plate-shaped protrusion extending in the X direction and parallel to the XZ plane. The protrusion  160 S extending in the X direction means that a longitudinal direction of the protrusion  160 S is the X direction in plan view. The plurality of protrusions  160 S is a plurality of thin wall portions, and is arranged like a plurality of fins protruding downward from the lower surface of the source electrode  150 S. The protrusions  160 S are formed as a plurality of thin wall portions protruding downward from the lower surface of the source electrode  150 S in order to increase a contact area with the electron supply layer  140 , the spacer layer  130 , and the electron traveling layer  120  to obtain favorable ohmic contact. Note that, as an example, the length in the X direction of the protrusion  160 S is equal to the length in the longitudinal direction of the protrusion  160 D. 
     Note that a part of the semiconductor device  100  enlarged and illustrated in  FIG.  2 A  is a part above a lower surface of the electron traveling layer  120  and corresponding to a part of the width in the Y direction of the source electrode  150 S. For example,  FIG.  2 A  illustrates a part of the plurality of protrusions  160 S arranged in the Y direction. Such a configuration is similar for the protrusion  160 D located below the drain electrode  150 D. 
     Here, an area where the plurality of protrusions  160 S is provided on a lower side of the source electrode  150 S is referred to as an area  160 SA. The area  160 SA is an example of a first area. The area  160 SA includes the plurality of protrusions  160 S and the nitride semiconductor layers of the electron traveling layer  120 , the spacer layer  130 , and the electron supply layer  140  provided between the plurality of protrusions  160 S. The area  160 SA has, for example, a size equal to the source electrode  150 S in plan view and a size equal to the protrusion  160 S in XZ plane view. 
     Note that in a case where the protrusion  160 S at an end on the +Y direction side is offset in the −Y direction with respect to an end portion on the +Y direction side of the source electrode  150 S, an end portion in the +Y direction of the area  160 SA may be a side surface in the +Y direction (a side surface parallel to the XZ plane) of the protrusion  160 S at the end on the +Y direction side. Similarly, in a case where the protrusion  160 S at an end on the −Y direction side is offset in the +Y direction with respect to an end portion on the −Y direction side of the source electrode  150 S, an end portion in the −Y direction of the area  160 SA may be a side surface in the −Y direction (a side surface parallel to the XZ plane) of the protrusion  160 S at the end on the −Y direction side. Here, as an example, description will be given on the assumption that the area  160 SA has a size equal to the source electrode  150 S in plan view. 
       FIG.  1 A , which is a cross section taken along line A-A in  FIG.  2 A , is a cross section including the protrusion  160 S, and  FIG.  1 B , which is a cross section taken along line B-B in  FIG.  2 A , is a cross section not including the protrusion  160 S. Therefore,  FIG.  1 A  illustrates the protrusion  160 S and the area  160 SA. In  FIG.  1 A , the area  160 SA is slightly enlarged and illustrated outside a contour of the protrusion  160 S, but the sizes of the area  160 SA and the protrusion  160 S in the XZ plane are the same. Furthermore,  FIG.  1 B  also illustrates the area  160 SA. 
     Since such a plurality of protrusions  160 S extends to below the upper surface of the electron traveling layer  120 , the protrusions  160 S are in contact with the 2DEG  120 A. Furthermore, the 2DEG  120 A also occurs in a portion of the electron traveling layer  120 , the portion being included in the area  160 SA. 
     Configuration of Protrusion  160 D and Area  160 DA 
     The protrusion  160 D extends from a lower surface (lower end) of the drain electrode  150 D through an inside of the electron supply layer  140  and the spacer layer  130  to below the upper surface of the electron traveling layer  120 , and is formed of an electrode material of the drain electrode  150 D. A plurality of the protrusions  160 D is provided, and the plurality of protrusions  160 D is a plurality of thin plate-shaped protrusions extending in the X direction and arrayed in the Y direction in plan view. Each of the plurality of protrusions  160 D is a thin plate-shaped protrusion extending in the X direction and parallel to the XZ plane. The protrusion  160 D extending in the X direction means that a longitudinal direction of the protrusion  160 D is the X direction in plan view. The plurality of protrusions  160 D is a plurality of thin wall portions similar to the plurality of protrusions  160 S, and is arranged like a plurality of fins protruding downward from the lower surface of the drain electrode  150 D. The protrusions  160 D are formed as a plurality of thin wall portions protruding downward from the lower surface of the drain electrode  150 D in order to increase a contact area with the electron supply layer  140 , the spacer layer  130 , and the electron traveling layer  120  to obtain favorable ohmic contact. As an example, the length in the X direction of the protrusion  160 D is equal to the length in the longitudinal direction of the protrusion  160 S. 
     Here, an area where the plurality of protrusions  160 D is provided on a lower side of the drain electrode  150 D is referred to as an area  160 DA. The area  160 DA is an example of a second area. The area  160 DA includes the plurality of protrusions  160 D and the nitride semiconductor layers of the electron traveling layer  120 , the spacer layer  130 , and the electron supply layer  140  provided between the plurality of protrusions  160 D. The area  160 DA has, for example, a size equal to the drain electrode  150 D in plan view and a size equal to the protrusion  160 D in XZ plane view. 
     Note that in a case where the protrusion  160 D at an end on the +Y direction side is offset in the −Y direction with respect to an end portion on the +Y direction side of the drain electrode  150 D, an end portion in the +Y direction of the area  160 DA may be a side surface in the +Y direction (a side surface parallel to the XZ plane) of the protrusion  160 D at the end on the +Y direction side. Similarly, in a case where the protrusion  160 D at an end on the −Y direction side is offset in the +Y direction with respect to an end portion on the −Y direction side of the drain electrode  150 D, an end portion in the −Y direction of the area  160 DA may be a side surface in the −Y direction (a side surface parallel to the XZ plane) of the protrusion  160 D at the end on the −Y direction side. Here, as an example, description will be given on the assumption that the area  160 DA has a size equal to the drain electrode  150 D in plan view. 
       FIG.  1 A , which is a cross section taken along line A-A in  FIG.  2 A , is a cross section including the protrusion  160 D, and  FIG.  1 B , which is a cross section taken along line B-B in  FIG.  2 A , is a cross section not including the protrusion  160 D. Therefore,  FIG.  1 A  illustrates the protrusion  160 D and the area  160 DA. In  FIG.  1 A , the area  160 DA is slightly enlarged and illustrated outside a contour of the protrusion  160 D, but the sizes of the area  160 DA and the protrusion  160 D in the XZ plane are the same. Furthermore,  FIG.  1 B  also illustrates the area  160 DA. 
     Since such a plurality of protrusions  160 D extends to below the upper surface of the electron traveling layer  120 , the protrusions  160 D are in contact with the 2DEG  120 A. Furthermore, the 2DEG  120 A also occurs in a portion of the electron traveling layer  120 , the portion being included in the area  160 DA. 
     In such a semiconductor device  100 , the protrusions  160 S and  160 D extend in the X direction and are provided parallel to the direction (−X direction) in which the current flows in the electron traveling layer  120 , and thus do not divide the current flow in the electron traveling layer  120 . Although details of a manufacturing method will be described below, when forming recesses in the electron supply layer  140 , the spacer layer  130 , and the electron traveling layer  120  in order to form the protrusions  160 S and  160 D, a portion near the upper surface of the electron traveling layer  120  is not divided in the X direction, and thus there is an advantage that the area where the 2DEG is obtained does not need to be divided in the X direction. Note that the protrusions  160 S and  160 D extend along the X direction and does not need to extend parallel to the X direction. 
     Configuration of Passivation Film  170   
     The passivation film  170  is an insulating film and is a protective film provided on the upper surface of the electron supply layer  140 , the upper surface being not covered by the source electrode  150 S and the drain electrode  150 D. The passivation film  170  can be made of SiN or the like. A film thickness of the passivation film  170  is between 2 nm and 100 nm, and is, for example, 50 nm. 
     Offset Amounts of Protrusions  160 S and  160 D 
       FIG.  3 A  is a view illustrating an offset amount X 1  of an end portion of the protrusion  160 S with respect to the source electrode  150 S of the semiconductor device  100 .  FIG.  3 B  is a graph illustrating a relationship between the offset amount X 1  and a contact resistance Rc. In  FIG.  3 B , a horizontal axis represents the offset amount X 1  (μm), and a vertical axis represents the contact resistance Rc between the source electrode  150 S and the electron traveling layer  120 . The contact resistance Rc is represented by resistivity (Ω·mm). Note that  FIG.  3 B  illustrates an experimentally obtained result. 
     The offset amount X 1  is the offset amount of the end portion on the +X direction side of the protrusion  160 S with respect to the end portion on the +X direction side of the source electrode  150 S, as illustrated in  FIG.  3 A , and exhibits a positive value in a case where the end portion on the +X direction side of the protrusion  160 S is located on the −X direction side with respect to the end portion on the +X direction side of the source electrode  150 S, as illustrated in  FIG.  3 A . For example, the offset amount X 1  exhibits a negative value in a case where the end portion on the +X direction side of the protrusion  160 S is offset on the +X direction side with respect to the end portion on the +X direction side of the source electrode  150 S. 
     As illustrated in  FIG.  3 B , in a case where the offset amount X 1  becomes a negative value (X 1 &lt;0), the protrusion  160 S more protrudes in the +X direction and is closer to the gate electrode  150 G than the end portion on the +X direction side of the source electrode  150 S. In this case, the contact resistance Rc was found to increase (worse). This is because the resistance that increases by a reduced amount of the area of the 2DEG  120 A in plan view in the area  160 SA including the protrusion  160 S is added to the contact resistance Rc due to the extension of the protrusion  160 S on the +X direction side. 
     On the other hand, in a case where the position of the end portion on the +X direction side of the source electrode  150 S and the position of the end portion on the +X direction side of the protrusion  160 S are equal to each other in the X direction, or the end portion on the +X direction side of the protrusion  160 S is more away from the gate electrode  150 G than the end portion on the +X direction side of the source electrode  150 S (X 1 ≥0), the contact resistance Rc decreased from X 1 =0 μm to X 1 =about 0.1 μm, and the contact resistance Rc increased as X 1  increased. A value that could be said to be favorable was obtained up to about 0.3 μm of X 1 . When X 1  exceeded 0.3 μm, the contact resistance Rc tended to further increase. This is because a series resistance in the section of 2DEG  120 A, which increases by the distance X 1  away, is added. The contact resistance Rc being 0.4 Ω·mm or less, which is one index, is from X 1 =0 μm to 0.25 μm. 
     From the above, it is favorable that the position of the end portion on the +X direction side of the source electrode  150 S and the position of the end portion on the +X direction side of the protrusion  160 S are equal to each other in the X direction, or the end portion on the +X direction side of the protrusion  160 S is more away from the gate electrode  150 G than the end portion on the +X direction side of the source electrode  150 S (X 1 ≥0), and moreover, it is favorable that the offset amount X 1  is 0 μm to 0.25 μm, both inclusive. 
     Note that, here, the offset amount X 1  of the end portion on the +X direction side of the protrusion  160 S with respect to the end portion on the +X direction side of the source electrode  150 S has been described, but the same similarly applies to the offset amount of the end portion on the −X direction side of the protrusion  160 D with respect to the end portion on the −X direction side of the drain electrode  150 D. 
     Volume Ratio of Protrusions  160 S and  160 D Inside Areas  160 SA and  160 DA 
       FIG.  4    is a graph illustrating a relationship between a volume ratio of the protrusion  160 S in the area  160 SA and the contact resistance Rc. This relationship was experimentally obtained. Here, the volume ratio of metal material of the plurality of protrusions  160 S in the area  160 SA will be described, but the same similarly applies to the volume ratio of metal material of the plurality of protrusions  160 D in the area  160 DA. 
     In  FIG.  4   , characteristics of the contact resistance Rc with respect to the volume ratio in a case where the offset amount X 1  is −0.12 μm are illustrated by the solid line, and characteristics of the contact resistance Rc with respect to the volume ratio in a case where the offset amount X 1  is 0.08 μm are illustrated by the broken line. 
     As illustrated in  FIG.  4   , it was found that the contact resistance Rc increased as the volume ratio increased when the volume ratio was increased from 47.5%. It is considered that this is because when the volume ratio increases, the volume of the protrusion  160 S increases and the 2DEG  120 A of the electron traveling layer  120  located between the plurality of protrusions  160 S decreases. 
     Since an increase rate of the contact resistance Rc becomes much larger when the volume ratio is increased from 47.5% and exceeds 60% in both the cases where the offset amounts X 1  are −0.12 μm and 0.08 μm, it was found that the volume ratio of the plurality of protrusions  160 S in the area  160 SA was favorably 60% or less. 
     Positions of Bottom Surfaces of Protrusions  160 S and  160 D and Contact Resistance Rc 
       FIG.  5 A  is a view illustrating a position H in a height direction of a bottom surface of the protrusion  160 S.  FIG.  5 B  is a graph illustrating a relationship between the position H and the contact resistance Rc. The relationship illustrated in  FIG.  5 B  was experimentally obtained. Here, the position of the bottom surface of the protrusion  160 S will be described, but the same similarly applies to the position of the bottom surface of the protrusion  160 D. 
     Here, the height direction is the Z direction, and the bottom surface of the protrusion  160 S is a lower surface of the protrusion  160 S. The position H represents the position (nm) in the height direction of the bottom surface of the protrusion  160 S from the upper surface of the electron traveling layer  120 . Since the upper surface of the electron traveling layer  120  is the interface between the channel and the spacer layer  130 , the position H is the position in the height direction of the bottom surface of the protrusion  160 S from the interface between the channel and the spacer layer  130 . Furthermore, in a case where the position H is 0 nm, the bottom surface of the protrusion  160 S is located at the same height as the interface between the channel and the spacer layer  130 , and the position H takes a positive value in a case where the bottom surface of the protrusion  160 S is higher than the interface between the channel and the spacer layer  130  (located on the +Z direction side). The position H takes a negative value in a case where the bottom surface of the protrusion  160 S is lower than the interface between the channel and the spacer layer  130  (located on the −Z direction side). 
     As illustrated in  FIG.  5 B , when the value of the position H was increased from −28 nm to 0 nm, the contact resistance Rc gradually decreased as the position H moved from −28 nm to −8 nm, and it was found that a favorable value of the contact resistance Rc was obtained when the contact resistance was −20 nm or higher. Furthermore, it was also found that the position H was substantially constant from −8 nm to −3 nm, and sharply increased when the value was increased above −3 nm. For example, the contact resistance Rc sharply increased when the value of the position H exceeded 0 nm. 
     Thus, it was found that the contact resistance Rc was low in a case where the bottom surface of the protrusion  160 S was located on the lower side of the upper surface of the electron traveling layer  120  (the interface between the channel and the spacer layer  130 ), but the contact resistance Rc sharply increased when the bottom surface of the protrusion  160 S was away above the interface between the channel and the spacer layer  130 . 
     From the above, it was found that the contact resistance Rc exhibited a favorable value in the range where the position H was −20 nm to −3 nm, both inclusive. Here, when the position H of the bottom surface of the protrusion  160 S is represented by a position in a depth direction where depth from the upper surface of the electron traveling layer  120  is positive, the position H being −20 nm to −3 nm, both inclusive means that the bottom surface of the protrusion  160 S is located at a position of 3 nm to 20 nm, both inclusive, in the depth direction from the upper surface of the electron traveling layer  120 . 
     Density of Protrusions  160 S and  160 D 
       FIG.  6 A  is a view illustrating a width Wm and an interval Ws of the protrusion  160 S.  FIG.  6 B  is a graph illustrating a relationship between density of the protrusion  160 S and the contact resistance Rc. The relationship illustrated in  FIG.  6 B  was obtained by simulation. Here, the relationship between the density of the protrusion  160 S and the contact resistance Rc will be described, but the same similarly applies to the relationship between the density of the protrusion  160 D and the contact resistance Rc. 
     The width Wm is a width in the Y direction of the protrusion  160 S. The interval Ws is an interval between adjacent protrusions  160 S, and corresponds to a width in the Y direction of the nitride semiconductor layers (the electron traveling layer  120 , the spacer layer  130 , and the electron supply layer  140 ) between the adjacent protrusions  160 S. 
     Density D of the protrusion  160 S is density indicating how many protrusions  160 S are arranged in 1 μm in the Y direction in the area  160 SA. The density D (μm −1 ) of the protrusion  160 S can be expressed by the following equation (1). The unit of the density D is synonymous with pieces/μm. 
         D =( Wm+Ws ) −1    (1)
 
     When the interval Ws was set to 5.0 μm, 0.5 μm, and 0.2 μm to change the density D, and the contact resistance Rc was calculated, the results illustrated in  FIG.  6 B  were obtained. When the interval Ws is fixed and the density D is changed, the width Wm is changed. At any interval Ws, the contact resistance Rc tends to increase as the density D decreases. This is because metal portion of the protrusion  160 S decreases. 
     Here, a lower limit of the density D was set to 0.2 μm −1  from the viewpoint of obtaining a favorable contact resistance Rc. Furthermore, an upper limit of the density D was set to 5.0 μm −1  when fabricating the plurality of protrusions  160 S arrayed in the Y direction in the area  160 SA. This is because it is difficult to fabricate the plurality of protrusions  160 S when the density D exceeds 5.0 μm −1 . 
     Furthermore, it is found that the density D at which the contact resistance Rc becomes equal to or less than a predetermined value (for example, 0.5 Ω·mm) is obtained by setting the interval Ws to various values such as 5.0 μm, 0.5 μm, and 0.2 μm from  FIG.  6 B . Therefore, the contact resistance Rc may be reduced by selecting the interval Ws according to the density D. 
     From the above, it was found that the density D was favorable in the range of 0.2 μm −1  to 5.0 μm −1 , both inclusive. 
     Method for Manufacturing Semiconductor Device  100   
       FIGS.  7 A to  7 I  are views for describing a method for manufacturing the semiconductor device  100 .  FIGS.  7 A,  7 C, and  7 H  illustrate cross sections parallel to the XZ plane during a manufacturing process of the semiconductor device  100 .  FIGS.  7 B,  7 D,  7 E,  7 F,  7 G, and  7 I  are views illustrating cross-sectional structures of a part of the semiconductor device  100  during the manufacturing process thereof, and are views illustrating cross sections parallel to the YZ plane corresponding to a part of the semiconductor device  100  illustrated in  FIG.  2 B .  FIGS.  7 A and  7 B  illustrate cross sections in the same manufacturing process,  FIGS.  7 C and  7 D  illustrate cross sections in the same manufacturing process, and  FIGS.  7 H and  7 I  illustrate cross sections in the same manufacturing process. 
     First, as illustrated in  FIGS.  7 A and  7 B , the initial layer  111 , the electron traveling layer  120 , the spacer layer  130 , and the electron supply layer  140  are epitaxially grown on the substrate  110  by metal organic chemical vapor deposition (MOCVD) in this order. By forming the electron supply layer  140  above the electron traveling layer  120 , the 2DEG  120 A is generated directly below the interface of the electron traveling layer  120  with the spacer layer  130 . 
     Next, an inactive area is formed by an element separation process (not illustrated), and an active area is defined. For example, a resist pattern having an opening is formed in an area where an element separation area is formed by photolithography. Next, an inactive area is formed by injecting argon (Ar) ions into the nitride semiconductor layers (the electron traveling layer  120 , the spacer layer  130 , and the electron supply layer  140 ) in an area where no resist pattern is formed. The inactive area may be formed by removing a part of the nitride semiconductor layers in the area where no resist pattern is formed by dry etching with reactive ion etching (RIE) or the like using a chlorine-based gas. After forming the element separation area, the resist pattern is removed with an organic solvent or the like. 
     Next, as illustrated in  FIGS.  7 C and  7 D , the source electrode  150 S, the drain electrode  150 D, the protrusion  160 S, and the protrusion  160 D are formed. For example, it is as illustrated in  FIGS.  7 E to  7 G .  FIGS.  7 E to  7 G  illustrate the cross-sectional structures of the portion including the three protrusions  160 S, of the cross section including the four protrusions  160 S illustrated in  FIG.  7 I . 
     As illustrated in  FIG.  7 E , a pattern of a resist  10  having an opening portion  11  is formed in a portion where the protrusions  160 S and  160 D are to be formed by photolithography or electron beam (EB) lithography. 
     Next, as illustrated in  FIG.  7 F , a portion of the electron supply layer  140 , the spacer layer  130 , and the electron traveling layer  120  is removed to form a recess  160 H, the portion being located directly below the opening portion  11  in which the resist  10  does not exist. For the removal, dry etching such as RIE using a chlorine-based gas is used. Etching depth when forming the recess  160 H is deeper than the interface between the channel and the spacer layer  130  (the upper surface of the electron traveling layer  120 ), and further, the depth of the recess  160 H from the interface between the channel and the spacer layer  130  is favorably 3 nm to 20 nm, both inclusive. Thereafter, the resist  10  is removed. 
     Here, the recess  160 H has a longitudinal direction parallel to the X direction by extending in the X direction, similar to the protrusions  160 S and  160 D to be formed later. Therefore, since the portion near the upper surface of the electron traveling layer  120  is not divided in the X direction, the area where the 2DEG  120 A can be obtained does not need to be divided in the X direction. For example, in a case where the recess  160 H has a longitudinal direction in the Y direction, the area where the 2DEG  120 A can be obtained is divided in the X direction. Since the recess  160 H has the longitudinal direction parallel to the X direction, the portion near the upper surface of the electron traveling layer  120  is not divided in the X direction. Therefore, it is possible to suppress an increase in a sheet resistance Rsh in the electron traveling layer  120  and increase the current. 
     Next, a resist pattern having an opening portion is formed on an area where the source electrode  150 S and the drain electrode  150 D are to be formed of the upper surface of the electron supply layer  140  by photolithography. Thereafter, metal is vapor-deposited by a vacuum vapor deposition method. As the metal, for example, a laminated film having Ti of 2 nm to 50 nm in the first layer and Al of 100 nm to 300 nm in the second layer is conceivable. At this time, the protrusions  160 S and  160 D are formed inside the recesses  160 H for the protrusions  160 S and  160 D. Thereafter, by removing the metal other than the source electrode  150 S and the drain electrode  150 D by a lift-off technique, the structure illustrated in  FIG.  7 G  is obtained. The source electrode  150 S and drain electrode  150 D and the protrusions  160 S and  160 D are made of the same electrode material. 
     Next, by performing heat treatment (alloying treatment) at 500° C. to 650° C. in a nitrogen atmosphere, ohmic contact is established between the source electrode  150 S and the protrusion  160 S, and the drain electrode  150 D and the protrusion  160 D. As a result, the source electrode  150 S, the drain electrode  150 D, the protrusion  160 S, and the protrusion  160 D are formed. Furthermore, surface damage of the nitride semiconductor layer can be minimized. 
     The protrusions  160 S and  160 D have the structure in which thin metal wall portions used for the source electrode  150 S and the drain electrode  150 D and the nitride semiconductor layer are alternately arrayed in the Y direction, and the longitudinal direction (X direction) in plan view of the nitride semiconductor layer and the thin metal wall portions to be arrayed is the same as the current flow direction (−X direction). Furthermore, as described with reference to  FIG.  4   , the volume ratio of the metal of the protrusions  160 S and  160 D in the areas  160 SA and  160 SD is favorably 60% or less from the viewpoint of reducing the contact resistance Rc. Furthermore, the areas  160 SA and  160 DA in which the protrusions  160 S and  160 D are respectively arranged are favorably more separated than the source electrode  150 S and the drain electrode  150 D from the viewpoint of reducing the contact resistance Rc, as viewed from the gate electrode  150 G, and the offset amount X 1  is favorably 0 μm to 0.25 μm, both inclusive, as described with reference to  FIGS.  3 A and  3 B . 
     Next, as illustrated in  FIG.  7 H , an insulating film that becomes the passivation film  170  is formed on the electron supply layer  140  by plasma chemical vapor deposition (CVD). The cross section parallel to the YZ plane including the source electrode  150 S at this time is illustrated in  FIG.  7 I . The insulating film can be formed of SiN or the like, and the film thickness is between 2 nm and 100 nm, for example, 50 nm. Note that the insulating film may be formed by atomic layer deposition (ALD) or sputtering. Furthermore, the insulating film may be formed of an oxide of Si, Al, hafnium (Hf), zirconium (Zr), tantalum (Ta), or the like other than SiN, a nitride, an oxynitride, or a laminated film thereof. 
     Next, when the gate electrode  150 G is formed, the cross-sectional structure illustrated in  FIGS.  1 A and  1 B  is obtained. For example, a resist pattern having an opening portion is formed in an area where the gate electrode  150 G is to be formed, and metal is vapor-deposited by a vacuum vapor deposition method. As the metal, for example, a laminated film having Ni of 5 nm to 30 nm in the first layer and Au of 100 nm to 300 nm in the second layer can be formed. Then, the metals other than the gate electrode  150 G are removed together with the resist by lift-off. Through the above processes, the semiconductor device  100  having the structures illustrated in  FIGS.  1 A,  1 B,  2 A, and  2 B  can be fabricated. 
     Effects 
     As described above, in the semiconductor device  100 , the protrusions  160 S and  160 D extend from the lower surfaces (lower ends) of the source electrode  150 S and the drain electrode  150 D through the inside of the electron supply layer  140  and the spacer layer  130 , respectively, to below the upper surface of the electron traveling layer  120 , and are formed of the electrode material of the source electrode  150 S and the drain electrode  150 D. Therefore, the protrusions  160 S and  160 D are in contact with the 2DEG  120 A generated inside the electron traveling layer  120 . Furthermore, the volume ratios of the plurality of protrusions  160 S and the plurality of protrusions  160 D in the areas both  160 SA and  160 DA are 60% or less. Therefore, the contact resistance Rc can be suppressed low. 
     Therefore, the semiconductor device  100  capable of reducing the contact resistance Rc and the method for manufacturing the semiconductor device  100  can be provided. Furthermore, the source electrode  150 S and the drain electrode  150 D, which have the low contact resistance Rc at a relatively low temperature (&lt;650° C.), can be formed even in the structure in which an Al composition ratio in the electron supply layer  140  is set to 45% or more, and the spacer layer  130  is included. 
     Furthermore, in next-generation communication beyond fifth generation (5G)/sixth generation (6G) (B5G), use of ultra-high frequency radio waves such as 100 GHz band or 300 GHz band is being examined to implement 100 Gbps-class communication speed. These bands are frequency bands so-called millimeter wave bands. A problem when using radio waves of the ultra-high frequency bands is that the communication distance is short, and for example, this problem is caused by a larger amount of attenuation in the atmosphere than that of the radio waves used in the communication generation of 5G or earlier. However, there is still a problem of absence of an amplifier with sufficient output. Therefore, there is an urgent need to implement a high-output amplifier that operates in the ultra-high frequency band, and the semiconductor device  100  can increase the current in the electron traveling layer  120  by reducing the contact resistance and thus can be used as an amplifier such as a power amplifier that amplifies a signal in the ultra-high frequency band. 
     Furthermore, examples of the existing technique for obtaining the ohmic contact include a recess ohmic technique, selective regrowth, and ion implantation. The recess ohmic technique is a technique for thinning (recessing) an electron supply layer that becomes a barrier between metal and a channel, and has an advantage that the heat treatment is conducted at a relatively low temperature of about 600° C., but there is a problem of a difficulty in reducing the contact resistance Rc between the metal and the nitride semiconductor layer. Furthermore, the selective regrowth is a growing method for forming n-GaN by a crystal growth technique, but the method requires a high-temperature process of about 800° C. during crystal growth, and there is a problem that an increase in the sheet resistance Rsh due to surface damage is not avoided. Furthermore, the ion implantation is a method for forming n-GaN by an ion implantation technique, but the method requires a high-temperature process of about 1000° C. or higher to activate impurities, and there is a problem that an increase in the sheet resistance Rsh due to surface damage is not avoided. From this kind of circumstance, there are two requirements for the technique for obtaining the ohmic contact: low resistance between the metal and the nitride semiconductor layer, and the heat treatment temperature of 650° C. or less. The semiconductor device  100  is very promising in meeting these two requirements. 
     Furthermore, the plurality of protrusions  160 S is a plurality of thin plate-shaped protrusions extending along the X direction connecting the source electrode  150 S and the drain electrode  150 D in plan view, and arrayed in the Y direction intersecting the X direction in plan view, and the plurality of protrusions  160 D is a plurality of thin-shaped protrusions extending in the X direction and arrayed in the Y direction. Therefore, the plurality of protrusions  160 S and  160 D extends in the electron traveling layer  120  along the direction in which the current flows (−X direction), and do not divide the current flow in the electron traveling layer  120 . In the manufacturing process, when forming the recess  160 H (see  FIG.  7 F ) in the electron supply layer  140 , the spacer layer  130 , and the electron traveling layer  120  in order to form the protrusions  160 S and  160 D, the portion near the upper surface of the electron traveling layer  120  is not divided in the X direction, and thus the area where the 2DEG  120 A is obtained does not need to be divided in the X direction. Furthermore, even if the protrusion  160 S is provided, an increase in the sheet resistance Rsh of the electron traveling layer  120  can be suppressed. Therefore, the semiconductor device  100  capable of increasing the current in the electron traveling layer  120  can be provided. 
     Furthermore, the end portions of the plurality of protrusions  160 S on the drain electrode  150 D side in the X direction are offset in the direction away from the drain electrode  150 D with respect to the end portion of the source electrode  150 S on the drain electrode  150 D side in the X direction. Similarly, the end portions of the plurality of protrusions  160 D on the source electrode  150 S side in the X direction are offset in the direction away from the source electrode  150 S with respect to the end portion of the drain electrode  150 D on the source electrode  150 S side in the X direction. Therefore, the contact resistance Rc between the source electrode  150 S and the drain electrode  150 D, and the electron traveling layer  120  can be reduced. 
     Furthermore, the offset amount X 1  in the X direction of the plurality of protrusions  160 S and  160 D is 0 μm to 0.25 μm, both inclusive. Therefore, the contact resistance Rc between the source electrode  150 S and the drain electrode  150 D, and the electron traveling layer  120  can be more effectively reduced, and the semiconductor device  100  capable of more effectively reducing the contact resistance Rc and the method for manufacturing the semiconductor device can be provided. 
     Furthermore, the bottom surfaces of the plurality of protrusions  160 S and  160 D are located at the positions of 3 nm to 20 nm, both inclusive, in the depth direction from the upper surface of the electron traveling layer  120 . Even with the configuration, the contact resistance Rc between the source electrode  150 S and the drain electrode  150 D, and the electron traveling layer  120  can be more effectively reduced, and the semiconductor device  100  capable of more effectively reducing the contact resistance Rc and the method for manufacturing the semiconductor device can be provided. 
     Furthermore, since the electron traveling layer  120  has the 2DEG  120 A inside the area  160 SA and the area  160 SA, even if the protrusions  160 S and  160 D are formed at positions in the depth direction reaching the inside of the electron traveling layer  120 , the channel by the 2DEG  120 A inside the areas  160 SA and  160 DA can be generated, and the semiconductor device  100  having favorable operation characteristics and the method for manufacturing the semiconductor device can be provided. 
     Furthermore, since the density D of the protrusion  160 S in the Y direction in the area  160 SA and the density D of the protrusion  160 D in the Y direction in the area  160 DA are 0.2 μm −1  to 5.0 μm −1 , both inclusive, it is possible to achieve reduction in the contact resistance Rc by selecting the interval Ws according to the density D. 
     Second Embodiment 
       FIGS.  8 A and  8 B  are views illustrating a cross-sectional structure of a semiconductor device  100 A of a second embodiment.  FIG.  8 C  is a view illustrating a cross-sectional structure of a part of the semiconductor device  100 A. The cross sections illustrated in  FIGS.  8 A and  8 B  respectively correspond to the cross sections illustrated in  FIGS.  1 A and  1 B  of the first embodiment, and the cross section illustrated in  FIG.  8 C  corresponds to the cross section illustrated in  FIG.  2 B . 
     Configuration of Semiconductor Device  100 A 
     The semiconductor device  100 A has a configuration in which a metal portion  165  is added to an inside of a spacer layer  130  and an electron supply layer  140  among nitride semiconductor layers inside areas  160 SA and  160 DA with respect to the semiconductor device  100  of the first embodiment. Hereinafter, differences from the semiconductor device  100  of the first embodiment will be mainly described. 
     The metal portion  165  is a substantially columnar metal portion extending from an upper surface of the electron supply layer  140  to the inside of the spacer layer  130 . Such a metal portion  165  is formed by forming a pit (hole) penetrating the nitride semiconductor layers from the upper surface of the electron supply layer  140  to the inside of the spacer layer  130  inside the areas  160 SA and  160 DA, and embedding an inside of the pit with metal material of a source electrode  150 S and a drain electrode  150 D by vapor deposition or the like. Note that  FIGS.  8 B and  8 C  illustrate a state in which the metal portion  165  extends to a lower surface of the spacer layer  130 . However, when the pit is formed by wet etching, an etching solution may be selected such that the etching is automatically stopped inside the spacer layer  130 . Thereby, a lower end of the pit is located between an upper surface and the lower surface of the spacer layer  130  (inside the spacer layer  130 ), and a lower end of the metal portion  165  is also located inside the spacer layer  130 . 
     Since the metal portion  165  is provided inside the electron supply layer  140  and the spacer layer  130  in the areas  160 SA and  160 DA, the metal portion does not exist in the cross section illustrated in  FIG.  8 A  and exists in the cross section illustrated in  FIG.  8 B  not including the protrusions  160 S and  160 D. The cross-sectional structure in an XZ plane is illustrated in  FIG.  8 C . 
     In the nitride semiconductor layers provided with the metal portion  165  inside the areas  160 SA and  160 DA, a ratio of the metal portion  165  is adjusted such that elements constituting the nitride semiconductor layers occupy 80% or more in volume ratio. For example, in the nitride semiconductor layers provided with the metal portion  165  inside the areas  160 SA and  160 DA, the ratio of the metal portion  165  is adjusted such that the metal constituting the metal portion  165  becomes lower than 20% in volume ratio. 
     The metal portion  165  is provided to reduce a contact resistance Rc, but if the ratio of the metal portion  165  is too large, the resistance of the metal portion  165  is added to the contact resistance Rc. The figure of 80% is a value obtained by experiment and simulation. 
     Method for Manufacturing Semiconductor Device  100 A 
     Since a method for manufacturing the semiconductor device  100 A is the same as the method for manufacturing the semiconductor device  100  of the first embodiment up to the processes described with reference to  FIGS.  7 A and  7 B  in the first embodiment, processes after the processes illustrated in  FIGS.  7 A and  7 B  will be described with reference to  FIGS.  8 D to  8 G .  FIGS.  8 D to  8 G  are views for describing the method for manufacturing the semiconductor device  100 A of the second embodiment. 
     It is assumed that an initial layer  111 , an electron traveling layer  120 , the spacer layer  130 , and the electron supply layer  140  are formed on a substrate  110  (see  FIGS.  7 A and  7 B ), and an element separation process has been completed. 
     Next, as illustrated in  FIG.  8 D , a pit  140 P is formed. In the nitride semiconductor layers provided with the metal portion  165  inside the areas  160 SA and  160 DA, the number and size of the pits  140 P in which the metal portion  165  is to be formed later may be adjusted so that the elements constituting the nitride semiconductor layers occupy 80% or more in volume ratio. 
     A protective film (for example, SiN) having an opening portion is formed in an area for forming the pit  140 P in an area for forming the areas  160 SA and  160 DA, and the pit  140 P is formed by wet etching. As a chemical solution, for example, tetra methylammonium hydroxide (TMAH), potassium hydroxide, sodium hydroxide, sulfuric acid, hydrogen peroxide solution, or a mixed solution thereof may be used. Solution temperature and stirring speed may be changed in order to increase etching power. For example, by heating and immersing TMAH of about 25 wt % at about 80° C., etching proceeds starting from crystal defects or the like, and the pit  140 P having a diameter of several nm to several tens of nm is formed. Furthermore, it is also possible to automatically stop the etching in a depth direction in the spacer layer  130 . Thereafter, the protective film is removed. Thereby, in the area for forming the areas  160 SA and  160 DA, the pit  140 P reaching the spacer layer  130  from the upper surface of the electron supply layer  140  can be formed. 
     Next, a pattern of resist  10 A having an opening portion  11  is formed in a portion for forming the protrusions  160 S and  160 D by photolithography or EB lithography. Moreover, when the electron supply layer  140 , the spacer layer  130 , and the electron traveling layer  120  directly below the opening portion  11  where the resist  10 A does not exist are removed, the structure illustrated in  FIG.  8 E  is obtained. Dry etching such as RIE using a chlorine-based gas is used to remove the electron supply layer  140 , the spacer layer  130 , and the electron traveling layer  120 . An etching depth at this time is deeper than an interface between a channel and the spacer layer  130 , and the depth with respect to the interface between the channel and the spacer layer  130  (the upper surface of the electron traveling layer  120 ) is favorably 3 nm to 20 nm, both inclusive. Thereafter, when the resist  10 A is removed, the state illustrated in  FIG.  8 F  is obtained. 
     Next, a resist pattern having an opening portion is formed in an area where the source electrode  150 S and the drain electrode  150 D are to be formed by photolithography, and the metal is vapor-deposited by a vacuum vapor deposition method. As the metal, for example, a laminated film having Ti of 2 nm to 50 nm in the first layer and Al of 100 nm to 300 nm in the second layer may be used. Thereafter, when the metal other than the source electrode  150 S and the drain electrode  150 D is removed together with the resist by a lift-off technique, the structure in  FIG.  8 G  in which the metal portion  165  is formed inside the pit  140 P together with the source electrode  150 S and the protrusion  160 S is obtained.  FIG.  8 G  illustrates the portion where the source electrode  150 S exists in a Y direction, but the same similarly applies to the portion where the drain electrode  150 D exists. 
     Moreover, by performing heat treatment (alloying treatment) at 500° C. to 650° C. in a nitrogen atmosphere, ohmic contact is established among the source electrode  150 S and the protrusion  160 S, the drain electrode  150 D and the protrusion  160 D, and the metal portion  165 . 
     Thereafter, by forming a gate electrode  150 G and a passivation film  170 , similarly to the semiconductor device  100  of the first embodiment, the semiconductor device  100 A of the second embodiment is completed. In the semiconductor device  100 A, the protrusions  160 S and  160 D are formed in the areas  160 SA and  160 DA, respectively, as in the semiconductor device  100  of the first embodiment, and the metal portion  165  is formed inside the spacer layer  130  and the electron supply layer  140  of the nitride semiconductor layers inside the areas  160 SA and  160 DA. 
     In the nitride semiconductor layers provided with the metal portion  165  inside the areas  160 SA and  160 DA, the ratio of the metal portion  165  is adjusted such that the elements constituting the nitride semiconductor layers occupy 80% or more in volume ratio. 
     Therefore, the semiconductor device  100 A capable of further reducing the contact resistance by the protrusions  160 S and  160 D and the metal portion  165 , and the method for manufacturing the semiconductor device  100 A can be provided. 
     Third Embodiment 
       FIGS.  9 A and  9 B  are views illustrating cross-sectional structures of a semiconductor device  100 B of a third embodiment. The cross section illustrated in  FIG.  9 A  corresponds to the cross section illustrated in  FIG.  1 A  of the first embodiment, and the cross section illustrated in  FIG.  9 B  corresponds to the cross section illustrated in  FIG.  2 B . 
     The semiconductor device  100 B has a configuration in which a cap layer  180  is added between the upper surface of the electron supply layer  140 , and the gate electrode  150 G, the source electrode  150 S, and the drain electrode  150 D of the semiconductor device  100  of the first embodiment. Hereinafter, differences from the semiconductor device  100  of the first embodiment will be mainly described. 
     The cap layer  180  is an example of a sheet resistance reduction layer provided at an interface between the electron supply layer  140 , and the source electrode  150 S and the drain electrode  150 D, and which reduces a sheet resistance Rsh of a 2DEG  120 A. 
     The cap layer  180  can be formed of, for example, GaN, and is, for example, a nitride semiconductor layer (GaN cap layer) that can be fabricated by MOCVD after the process of  FIG.  7 B  in the method for manufacturing the semiconductor device  100  of the first embodiment. Such a cap layer  180  is also provided in an area  160 SA as illustrated in  FIG.  9 B . Furthermore, the cap layer  180  is similarly provided in an area  160 DA as well. By adding the cap layer  180  to the nitride semiconductor layers in the areas  160 SA and  160 DA, density of the 2DEG  120 A can be further increased and the sheet resistance Rsh of an electron traveling layer  120  can be reduced. 
     Therefore, according to the third embodiment, the semiconductor device  100 B capable of reducing a contact resistance Rc by the protrusions  160 S and  160 D and capable of reducing the sheet resistance Rsh by the cap layer  180 , and the method for manufacturing the semiconductor device  100 B can be provided. 
     Fourth Embodiment 
       FIG.  10 A  is a view illustrating a cross-sectional structure of a semiconductor device  100 C of a fourth embodiment.  FIG.  10 B  is a view illustrating a cross-sectional structure of a part of the semiconductor device  100 C. The cross section illustrated in  FIG.  10 A  corresponds to the cross section illustrated in  FIG.  1 A  of the first embodiment, and the cross section illustrated in  FIG.  10 B  corresponds to the cross section illustrated in  FIG.  2 B . 
     Configuration of Semiconductor Device  100 C 
     A semiconductor device  100 C has a configuration including a passivation film  170 C instead of the passivation film  170  of the semiconductor device  100  of the first embodiment. Hereinafter, differences from the semiconductor device  100  of the first embodiment will be mainly described. 
     The passivation film  170 C is an example of a sheet resistance reduction layer provided at an interface between an electron supply layer  140 , and a source electrode  150 S and a drain electrode  150 D, and which reduces a sheet resistance Rsh of a 2DEG  120 A, as in the cap layer  180  of the semiconductor device  100 B of the third embodiment. 
     Method for Manufacturing Semiconductor Device  100 C 
       FIGS.  10 C to  10 J  are views for describing a method for manufacturing the semiconductor device  100 C of the fourth embodiment. A process of epitaxially growing an initial layer  111 , an electron traveling layer  120 , a spacer layer  130 , and the electron supply layer  140  on a substrate  110  by MOCVD and an element separation process are similar to the method for manufacturing the semiconductor device  100  of the first embodiment, and thus description is omitted here. 
     Next, as illustrated in  FIGS.  10 C and  10 D , an insulating film to be the passivation film  170 C is formed on the electron supply layer  140  by plasma CVD. The insulating film is formed of SiN or the like, and a film thickness is between 2 nm and 100 nm, for example, 50 nm. Note that the insulating film may be formed by ALD or sputtering. Furthermore, the insulating film may be formed of an oxide such as Si, Al, Hf, Zr, or Ta other than SiN, a nitride, an oxynitride, or a laminated film thereof. Furthermore, at this stage, heat treatment may be performed at 650° C. or lower in order to reduce the sheet resistance Rsh of the electron traveling layer  120 . 
     Next, as illustrated in  FIGS.  10 E and  10 F , protrusions  160 S and  160 D, the source electrode  150 S, and the drain electrode  150 D are formed. For example, description will be given with reference to  FIGS.  10 G to  10 I .  FIGS.  10 G to  10 I  illustrate portions corresponding to the source electrode  150 S and the protrusion  160 S, but the same similarly applies to portions corresponding to the drain electrode  150 D and the protrusion  160 S. Therefore, the portions corresponding to the source electrode  150 S and the protrusion  160 S and the portions corresponding to the drain electrode  150 D and the protrusion  160 S will be described. 
     As illustrated in  FIG.  10 G , a pattern of a resist  10 C having an opening portion  11  is formed in a portion for forming the protrusions  160 S and  160 D by photolithography or EB lithography. 
     Next, the passivation film  170 C in an area directly below the opening portion  11  in which the resist  10 C does not exist is removed. For example, in a case of using SiN for the passivation film  170 C, dry etching such as RIE using a fluorine-based gas is used. Next, the electron supply layer  140 , the spacer layer  130 , and the electron traveling layer  120  in an area where the resist  10 C and the passivation film  170 C do not exist are removed. For the removal, dry etching such as RIE using a chlorine-based gas is used. An etching depth at this time is deeper than an interface between a channel and the spacer layer  130 , and the depth with respect to the interface between the channel and the spacer layer  130  (the upper surface of the electron traveling layer  120 ) is favorably 3 nm to 20 nm, both inclusive. Thereafter, when the remaining resist  10 C is removed, the state illustrated in  FIG.  10 H  is obtained. 
     Next, a resist pattern having an opening is formed in an area where the source electrode  150 S and the drain electrode  150 D are to be formed by photolithography, and metal for forming the source electrode  150 S and the drain electrode  150 D is vapor-deposited by a vacuum vapor deposition method. As the metal, for example, a laminated film having Ti of 2 nm to 50 nm in the first layer and Al of 100 nm to 300 nm in the second layer may be used. Thereafter, when the metal other than the source electrode  150 S and the drain electrode  150 D is removed by a lift-off technique, the structure illustrated in  FIG.  10 I  is obtained.  FIG.  10 I  illustrates the portion where the source electrode  150 S exists in the Y direction, but the same similarly applies to the portion where the drain electrode  150 D exists. 
     Moreover, by performing heat treatment (alloying treatment) at 500° C. to 650° C. in a nitrogen atmosphere, ohmic contact is established between the source electrode  150 S and the protrusion  160 S, and the drain electrode  150 D and the protrusion  160 D. 
     Thereafter, a resist pattern having an opening portion is formed on the passivation film  170 C in an area where a gate electrode  150 G is to be formed, and the metal is vapor-deposited by a vacuum vapor deposition method. As the metal, for example, a laminated film having Ni of 5 nm to 30 nm in the first layer and Au of 100 nm to 300 nm in the second layer can be formed. Then, the metals other than the gate electrode  150 G are removed together with the resist by lift-off. Through the above processes, the semiconductor device  100 D of the fourth embodiment illustrated in  FIG.  10 A  is completed. 
     In the semiconductor device  100 C, the passivation film  170 C is provided between the electron supply layer  140 , and the source electrode  150 S and the drain electrode  150 D in the areas  160 SA and  160 DA, so that density of the 2DEG  120 A is further increased and the sheet resistance Rsh of the electron traveling layer  120  can be reduced. 
     Therefore, according to the fourth embodiment, the semiconductor device  100 C capable of reducing the contact resistance Rc by the protrusions  160 S and  160 D and capable of reducing the sheet resistance Rsh by the passivation film  170 C, and the method for manufacturing the semiconductor device  100 C can be provided. 
     Fifth Embodiment 
       FIG.  11 A  is a view illustrating a cross-sectional structure of a semiconductor device  100 D of a fifth embodiment.  FIGS.  11 B and  11 C  are views illustrating cross-sectional structures of a part of the semiconductor device  100 D. The cross section illustrated in  FIG.  11 A  corresponds to the cross section illustrated in  FIG.  1 A  of the first embodiment, and the cross section illustrated in  FIG.  11 B  is a cross section including a source electrode  150 S corresponding to the cross section illustrated in  FIG.  2 B . Furthermore,  FIG.  11 C  illustrates a cross section including a drain electrode  150 D corresponding to the cross section illustrated in  FIG.  11 B . Hereinafter, differences from the semiconductor device  100  of the first embodiment will be mainly described. 
     As illustrated in  FIG.  11 A , the cross-sectional structure of the semiconductor device  100 D in an XZ plane is similar to that of the semiconductor device  100  of the first embodiment illustrated in  FIG.  1 A . Furthermore, as illustrated in  FIG.  11 B , the cross section of a YZ plane including the source electrode  150 S is similar to that of the semiconductor device  100  of the first embodiment illustrated in  FIG.  2 B . 
     In the semiconductor device  100 D, as illustrated in  FIG.  11 C , a width in the Y direction of a protrusion  160 D is set wider than a width in the Y direction of a protrusion  160 S illustrated in  FIG.  11 B . Since lengths in an X direction of the protrusions  160 S and  160 D are equal, a volume ratio of the protrusion  160 D in an area  160 DA is larger than a volume ratio of the protrusion  160 S in an area  160 SA. As an example, the volume ratio of the protrusion  160 S in the area  160 SA is 50% or less, and the volume ratio of the protrusion  160 D in the area  160 DA is higher than 50% and 60% or less. 
     By setting such a volume ratio relationship, a contact resistance Rc of the source electrode  150 S becomes lower than a contact resistance Rc of the drain electrode  150 D. This is because the protrusion  160 S is smaller than the protrusion  160 D, and resistance components with a low 2DEG  120 A are larger in the area  160 SA than in the area  160 DA. 
     By keeping the contact resistance Rc of the source electrode  150 S low, mutual conductance is improved and high frequency amplification capability can be improved. Furthermore, by relatively increasing the contact resistance Rc of the drain electrode  150 D, voltage drop in the drain electrode  150 D becomes large, and it becomes possible to alleviate electric field concentration in an end portion on a drain electrode  150 D side, of a gate electrode  150 G. Thereby, this contributes to higher withstand voltage and lower current collapse, leading to improvement in output power of the semiconductor device  100 D. This is particularly useful in a case of using the semiconductor device  100 D as a power amplifier. 
     The semiconductor device and the method for manufacturing the semiconductor device according to the exemplary embodiments of the present disclosure have been described. However, the present disclosure is not limited to the embodiments disclosed in detail, and the various changes and alterations could be made hereto without departing from the scope of claims. 
     All examples and conditional language provided herein are intended for the pedagogical purposes of aiding the reader in understanding the invention and the concepts contributed by the inventor to further the art, and are not to be construed as limitations to such specifically recited examples and conditions, nor does the organization of such examples in the specification relate to a showing of the superiority and inferiority of the invention. Although one or more embodiments of the present invention have been described in detail, it should be understood that the various changes, substitutions, and alterations could be made hereto without departing from the spirit and scope of the invention.