Patent Publication Number: US-7898781-B2

Title: Arc fault detection apparatus employing a comparator with a continuously variable threshold

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     Not applicable 
     STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT 
     Not applicable 
     BACKGROUND OF THE INVENTION 
     The present invention relates generally to arc fault detection apparatus and methods, and more specifically to an arc fault detection apparatus and method that provides for better discrimination of electrical arcing events from nuisance loads by employing a comparator circuit with a variable threshold voltage that varies continuously with the input line voltage. 
     Arc fault detection apparatus are known that may be employed to provide discrimination between electrical arcing events and nuisance loads. For example, an arc fault detection apparatus may include a current sensor, an input sense circuit, an arcing sense circuit, a power supply, a tripping (firing) circuit, a processing unit, and an electromechanical interface. In a typical mode of operation, the current sensor monitors the power input via the electromechanical interface, and provides high frequency components of the power input to the input sense circuit. The input sense circuit then filters and rectifies the AC signal at its input, and provides this sensed signal to the arcing sense circuit, which, in turn, provides voltage levels indicative of possible electrical arcing to the processing unit. Next, the processing unit measures the voltage levels and analyzes the voltage measurements using one or more algorithms to determine whether the voltage levels resulted from an arc fault or a nuisance load. In the event the detected levels resulted from an arc fault, the processing unit activates the firing circuit, thereby tripping the electromechanical interface to disconnect the power input from the power output. By making a determination as to whether the AC signal sensed by the input sense circuit resulted from an electrical arc fault or a nuisance load before tripping the electromechanical interface, the susceptibility of the arc fault detection apparatus to nuisance tripping is reduced. 
     In a typical embodiment of the above-described arc fault detection apparatus, the arcing sense circuit includes a comparator circuit with a constant threshold voltage. The input sense circuit provides the filtered and rectified AC signal at its output to this comparator circuit, which operates to compare the level of this sensed signal with the level of the constant threshold voltage. When a significant change in the load current occurs (i.e., when a significant “di/dt event” occurs), the level of the sensed signal may exceed the constant threshold voltage level, causing the output of the comparator circuit to be driven to its rail. The comparator circuit then provides one or more voltage levels to the processing unit, which measures the voltage levels and analyzes the voltage measurements to determine whether the detected di/dt event(s) resulted from an arc fault or a nuisance load. 
     Although the arc fault detection apparatus described above has been successfully employed in many different applications for detecting electrical arcing, there is a need for an arc fault detection apparatus that provides for better discrimination of electrical arcing events from nuisance loads. For example, the creation and cessation of electrical arcs can cause sudden changes in the load current (i.e., sudden di/dt events) to occur near the zero crossing points of the input line voltage, typically within a specified time window centered on the zero crossing points. The Applicants have recognized, however, that nuisance loads can cause sudden di/dt events to occur both within and outside of these specified time windows. The Applicants have also recognized that some types of nuisance loads can cause a greater number of sudden di/dt events to occur outside of these specified time windows than within these time windows. 
     Because the arc fault detection apparatus described above employs a comparator circuit with a constant threshold voltage within its arcing sense circuit, the comparator circuit compares voltage levels corresponding to sudden di/dt events with the same constant threshold voltage level, whether or not these di/dt events occurred within or outside of the specified time windows centered on the line voltage zero crossing points. Moreover, because the levels of sudden di/dt events resulting from nuisance loads that occur outside of these specified time windows can exceed the level of the constant threshold voltage, the above-described arc fault detection apparatus may incorrectly characterize such sudden di/dt events as arc faults, thereby resulting in nuisance tripping. 
     It would therefore be desirable to have improved arc fault detection apparatus and methods that avoid the drawbacks of the above-described arc fault detection apparatus. 
     BRIEF SUMMARY OF THE INVENTION 
     In accordance with the present invention, an arc fault detection apparatus is disclosed that provides for better discrimination of electrical arcing events from nuisance loads. The presently disclosed arc fault detection apparatus achieves such improved arc fault discrimination by employing a comparator circuit with a variable threshold voltage that varies continuously with the input line voltage. 
     In one embodiment, the presently disclosed arc fault detection apparatus includes a current sensor, an input sense circuit, an arcing sense circuit, a power supply, a tripping (firing) circuit, a processing unit, and an electromechanical interface. In one mode of operation, the current sensor monitors the power input via the electromechanical interface, and provides high frequency components of the power input to the input sense circuit. The input sense circuit then filters and rectifies the AC signal at its input, and provides this sensed signal to the arcing sense circuit, which, in turn, provides voltage levels indicative of possible electrical arcing to the processing unit. Next, the processing unit measures the voltage levels and analyzes the voltage measurements using one or more algorithms to determine whether the voltage levels resulted from an arc fault or a nuisance load. In the event the detected levels resulted from an arc fault, the processing unit activates the firing circuit, thereby tripping the electromechanical interface to disconnect the power input from the power output. 
     In the presently disclosed embodiment, the arcing sense circuit includes a comparator circuit with a variable threshold voltage that varies continuously with the input line voltage. In one embodiment, the variable threshold voltage varies in-phase with a rectified version of the line voltage, and varies continuously within a specified voltage range. The comparator circuit receives the filtered and rectified AC signal generated by the input sense circuit, and compares the level of this sensed signal with the level of the continuously variable threshold voltage. In one embodiment, the variable threshold voltage varies continuously from a first voltage level at approximately the midpoint of a specified time window centered on each zero crossing point of the periodic line voltage to a higher second voltage level at each end of the specified time window, and varies continuously from the second voltage level at each end of the specified time window to a still higher third voltage level at approximately the midpoint between successive time windows. 
     If the level of the sensed signal provided by the input sense circuit corresponds to a sudden change in the load current (i.e., a sudden “di/dt event”) that occurs within the specified time window centered on a zero crossing point of the line voltage, then the comparator circuit compares the level of this sensed signal with the level of the variable threshold voltage which varies continuously from the first voltage level at about the midpoint of the specified time window to the higher second voltage level at the ends of the specified time window. Alternatively, if the level of the sensed signal corresponds to a sudden di/dt event that occurs outside of the respective time windows centered on the line voltage zero crossing points, then the comparator circuit compares the level of this sensed signal with the level of the variable threshold voltage which varies continuously from the second voltage level at each end of a respective time window to the still higher third voltage level at about the midpoint between successive time windows. 
     Arc faults generally cause sudden di/dt events to occur within one or more of the above-described time windows centered on the zero crossing points of the line voltage, while some types of nuisance loads can cause increased numbers of sudden di/dt events to occur outside of these time windows. By employing the comparator circuit with the variable threshold voltage that varies continuously with the line voltage from a first voltage level to a higher second voltage level within these time windows, and that varies continuously with the line voltage from the second voltage level to a still higher third voltage level outside of these time windows, the susceptibility of the disclosed arc fault detection apparatus to nuisance tripping is reduced. 
     Other features, functions, and aspects of the invention will be evident from the Detailed Description of the Invention that follows. 
    
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
       The invention will be more fully understood with reference to the following Detailed Description of the Invention in conjunction with the drawings of which: 
         FIG. 1   a  is a block diagram of a prior embodiment of an arc fault detection apparatus; 
         FIG. 1   b  is a schematic diagram illustrating a current sensor, an input sense circuit, and an arcing sense circuit included in the arc fault detection apparatus of  FIG. 1   a , in which the arcing sense circuit includes a comparator circuit with a constant threshold voltage; 
         FIG. 1   c  is a timing diagram illustrating the relationship between the constant threshold voltage employed by the comparator circuit of  FIG. 1   b , the input line voltage, and a number of sudden di/dt events caused by a nuisance load; 
         FIG. 2   a  is a block diagram of an arc fault detection apparatus according to the present invention; 
         FIG. 2   b  is a schematic diagram illustrating a current sensor, an input sense circuit, and an arcing sense circuit included in the arc fault detection apparatus of  FIG. 2   a , in which the arcing sense circuit includes a comparator circuit with a variable threshold voltage; 
         FIG. 2   c  is a schematic diagram illustrating a power supply and a reference voltage generator included in the arc fault detection apparatus of  FIG. 2   a;    
         FIG. 2   d  is a timing diagram illustrating the relationship between the variable threshold voltage employed by the comparator circuit of  FIG. 2   b , and sudden di/dt events caused by a nuisance load; 
         FIG. 2   e  is a timing diagram illustrating the relationship between the variable threshold voltage employed by the comparator circuit of  FIG. 2   b , and sudden di/dt events caused by electrical arcing; and 
         FIG. 3  is a flow diagram illustrating a method of operating the arc fault detection apparatus of  FIG. 2   a.    
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     An arc fault detection apparatus is disclosed that provides for better discrimination of electrical arcing events from nuisance loads. The presently disclosed arc fault detection apparatus includes an arcing sense circuit having a comparator circuit with a variable threshold voltage that varies continuously with the input line voltage. The disclosed arc fault detection apparatus has reduced susceptibility to nuisance tripping in the presence of sudden changes in the load current occurring outside of a specified time window centered on each zero crossing point of the line voltage. 
       FIG. 1  depicts a prior embodiment  100  of an arc fault detection apparatus. For example, the arc fault detection apparatus  100  is like the apparatus described in U.S. Pat. No. 7,190,561 issued Mar. 13, 2007 entitled APPARATUS FOR DETECTING ARC FAULTS, which is assigned to and commonly owned by the same assignee as the present invention, and which is hereby incorporated herein by reference in its entirety. As shown in  FIG. 1   a , the arc fault detection apparatus  100  comprises a current sensor  104 , an input sense circuit  114 , an arcing sense circuit  112 , a power supply  106 , a tripping (firing) circuit  110 , a processing unit  108 , and an electromechanical interface  102 . In a typical mode of operation, the current sensor  104  monitors the power input via the electromechanical interface  102 , and provides high frequency components of the power input to the input sense circuit  114 . Next, the input sense circuit  114  filters and rectifies the AC signal at its input, and provides this sensed signal to the arcing sense circuit  112 . The arcing sense circuit  112  then provides voltage levels indicative of possible electrical arcing to the processing unit  108  over a line  130 . Next, the processing unit  108  measures the voltage levels and analyzes the voltage measurements using one or more algorithms to determine whether the voltage levels resulted from an arc fault or a nuisance load. In the event it is determined that the detected levels resulted from an arc fault, the processing unit  108  activates the firing circuit  110 , thereby tripping the electromechanical interface  102  to disconnect the power input from the power output. 
       FIG. 1   b  depicts typical implementations of the current sensor  104 , the input sense circuit  114 , and the arcing sense circuit  112  included in the arc fault detection apparatus  100 . As shown in  FIG. 1   b , the current sensor  104  includes a transformer TR 1 , which monitors the power input by monitoring an alternating current (AC) i flowing through a load coupleable to the power output via a load line phase terminal and a load line neutral terminal. The transformer TR 1  is operative to magnetically couple the high frequency components of the AC current i p  from its primary coil to its secondary coil, thereby providing an AC current i s  to the input sense circuit  114 . 
     The input sense circuit  114  includes capacitors C 1 -C 2 , resistors R 1 -R 2 , and diodes D 1 -D 4 . As shown in  FIG. 1   b , the secondary coil of the transformer TR 1  is connected between the two capacitors C 1 -C 2 . The resistors R 1 -R 2  are connected in series across the capacitors C 1 -C 2  and the transformer secondary coil, and the common node connection of the resistors R 1 -R 2  is connected to ground. The capacitors C 1 -C 2  are operative to perform high pass filtering of the AC signal provided by the transformer secondary coil, and the resistors R 1 -R 2  provide a ground reference for the secondary coil. The cathode of the diode D 1  is connected to the common node connection of the capacitor C 1 , the resistor R 1 , and the anode of the diode D 3 . Similarly, the cathode of the diode D 2  is connected to the common node connection of the capacitor C 2 , the resistor R 2 , and the anode of the diode D 4 . The cathodes of the diodes D 3 -D 4  are connected to a node  115  that provides the output of the input sense circuit  114  to the arcing sense circuit  112 . The diodes D 1 -D 4  are configured to form a full wave rectified bridge, and therefore the output provided at the node  115  is a full wave rectified signal. 
     The arcing sense circuit  112  includes resistors R 3 -R 7 , capacitors C 3 -C 4 , a diode D 5 , and a comparator  120 . As shown in  FIG. 1   b , the resistor R 3  and the capacitor C 3  are connected between the node  115  and ground, and the resistor R 4  is connected between the node  115  and the non-inverting input of the comparator  120 . The resistors R 5 -R 6  are configured to form a voltage divider that provides a constant threshold voltage (V CT ) to the inverting input of the comparator  120 . When the voltage level of the signal provided at the node  115  exceeds the level of the constant threshold voltage (V CT ) at the inverting input of the comparator  120 , the comparator  120  charges the capacitor C 4  through the diode D 5  and the resistor R 7 . The diode D 5  is operative to prevent reverse current flow from the capacitor C 4 . The comparator  120  continues to charge the capacitor C 4  so long as the voltage level at the non-inverting input of the comparator  120  remains greater than the constant threshold voltage (V CT ), which in this prior embodiment is equal to V CC *R 6 /(R 5 +R 6 ). 
     Accordingly, each time a significant change in the load current (i.e., a significant “di/dt event”) is detected at the non-inverting input of the comparator  120 , the output of the comparator  120  is driven to its positive rail, thereby generating a pulse for charging the capacitor C 4  through the diode D 5  and the resistor R 7 . The common node connection of the diode D 5  and the capacitor C 4  is connected to an input of the processing unit  108  (see  FIG. 1   a ), which is operative to take measurements of the voltage level across the capacitor C 4 , and to analyze the voltage measurements using one or more algorithms to determine whether the detected levels resulted from an arc fault or a nuisance load. In the event it is determined that the detected levels resulted from an arc fault, the processing unit  108  activates the firing circuit  110  (see  FIG. 1   a ) to trip the electromechanical interface  102  and disconnect the power input from the power output. 
       FIG. 1   c  is a timing diagram depicting the relationship between the constant threshold voltage (V CT ) employed by the comparator  120 , the input line voltage, and a number of sudden di/dt events such as events e 1 -e 8 , which may be caused by a nuisance load such as a vacuum cleaner. It is noted that the creation and cessation of electrical arcs can cause sudden di/dt events to occur near the zero crossing points of the periodic line voltage, typically within a specified time window centered on one or more of the zero crossing points. For example, electrical arc typically require a minimum voltage in the range of about 10 volts to 50 volts to sustain themselves, depending upon the corresponding arc current. Sudden changes in the line current associated with electrical arc creation and cessation therefore typically occur within about 1 msec of the zero crossing point of the line voltage, as illustrated by the equation below.
 54 volts=115 Vrms* 2 0.5 *sin(2π*60 Hz*1 msec)
 
It is noted that inductive and capacitive loads can broaden this +/−1 msec time window. It should be appreciated that a time window of any other suitable duration may be employed.
 
       FIG. 1   c  depicts five such time windows ranging from −t 1  to t 1 , from t 2  to t 3 , from t 4  to t 5 , from t 6  to t 7 , and from t 8  to t 9 . As shown in  FIG. 1   c , the voltage levels of the sudden di/dt events caused by the nuisance load and occurring within each of these time windows −t 1  to t 1 , t 2  to t 3 , t 4  to t 5 , t 6  to t 7 , and t 8  to t 9  are less than the level of the constant threshold voltage (V CT ), and therefore the levels of these sudden di/dt events are not high enough to cause the output of the comparator  120  to be driven to its rail. However, some of the voltage levels of the sudden di/dt events caused by the nuisance load that occur outside of these specified time windows, such as the levels of the events e 1 -e 8  occurring between the respective time windows, exceed the level of the constant threshold voltage (V CT ). The levels of these events e 1 -e 8  are therefore high enough to cause the output of the comparator  120  to be driven to its rail, thereby generating a pulse for charging the capacitor C 4 . Based on voltage measurements made across the capacitor C 4 , the processing unit  108  may incorrectly characterize the events e 1 -e 8  caused by the nuisance load as arc faults, resulting in nuisance tripping. 
       FIG. 2   a  depicts an illustrative embodiment  200  of an arc fault detection apparatus, in accordance with the present invention. The arc fault detection apparatus  200  provides for better discrimination of electrical arcing events from nuisance loads by employing an arcing sense circuit including a comparator circuit with a variable threshold voltage that varies continuously with the line voltage. The arc fault detection apparatus  200  has reduced susceptibility to nuisance tripping in the presence of sudden changes in the load current that occur outside of a specified time window centered on each zero crossing point of the line voltage. 
     As shown in  FIG. 2   a , the arc fault detection apparatus  200  comprises a current sensor  205 , an input sense circuit  215 , an arcing sense circuit  213 , a power supply  206 , a tripping (firing) circuit  210 , a processing unit  208 , and an electromechanical interface  202 . In one mode of operation, the current sensor  205  monitors the power input via the electromechanical interface  202 , and provides high frequency components of the power input to the input sense circuit  215 . Next, the input sense circuit  215  filters and rectifies the AC signal at its input, and provides this sensed signal to the arcing sense circuit  213 . The arcing sense circuit  213  then provides voltage levels indicative of possible electrical arcing to the processing unit  208  over a line  230 . For example, the processing unit  208  may be implemented using the MSP430F1122 micro-controller sold by Texas Instruments Inc., Dallas, Tex., USA, or any other suitable processor/controller. Next, the processing unit  208  measures the voltage levels and analyzes the voltage measurements using one or more algorithms to determine whether the voltage levels resulted from an arc fault or a nuisance load. In the event it is determined that the detected levels resulted from an arc fault, the processing unit  208  activates the firing circuit  210 , thereby tripping the electromechanical interface  202  to disconnect the power input from the power output. 
       FIG. 2   b  depicts illustrative embodiments of the current sensor  205 , the input sense circuit  215 , and the arcing sense circuit  213  included in the arc fault detection apparatus  200 . As shown in  FIG. 2   b , the current sensor  205  includes a transformer TR 2 , which monitors the power input by monitoring an alternating current (AC) i flowing through a load coupleable to the power output via a load line phase terminal and a load line neutral terminal. The transformer TR 2  is operative to magnetically couple the high frequency components of the AC current i p  from its primary coil to its secondary coil, thereby providing an AC current i s  to the input sense circuit  215 . 
     The input sense circuit  215  includes capacitors C 5 -C 8 , resistors R 8 -R 11 , and diodes D 6 -D 7 . As shown in  FIG. 2   b , the secondary coil of the transformer TR 2  is connected between the two capacitors C 5 -C 6 . The resistors R 8 -R 9  are connected in series across the capacitors C 5 -C 6  and the transformer secondary coil, and the common node connection of the resistors R 8 -R 9  is connected to ground. The resistors R 8 -R 9  provide a ground reference for the secondary coil of the transformer TR 2 . The capacitor C 7  is connected between the anode of the diode D 6  and the common node connection of the capacitor C 5  and the resistor R 8 . Similarly, the capacitor C 8  is connected between the anode of the diode D 7  and the common node connection of the capacitor C 6  and the resistor R 9 . The anode of the diode D 6  is pulled-up to the supply voltage V CC  by the resistor R 10 , and the anode of the diode D 7  is pulled-up to the supply voltage V CC  by the resistor R 11 . The cathodes of the diodes D 6 -D 7  are connected to a node  217  that provides the output of the input sense circuit  215  to the arcing sense circuit  213 . The diodes D 6 -D 7  are configured to provide a full wave rectified signal to the arcing sense circuit  213  at the node  217 . The capacitors C 5 -C 8  and the resistors R 8 -R 11  within the input sense circuit  215 , and the inductance of the secondary coil of the transformer TR 2  within the current sensor  205 , are operative to perform band-pass filtering of the AC signal provided by the transformer secondary coil. In one embodiment, the values of the components C 5 -C 8  and R 8 -R 11 , and the inductance of the transformer secondary coil, are selected to provide a pass band ranging from about 8 kHz to about 100 kHz, or any other suitable pass band. 
     The arcing sense circuit  213  includes resistors R 12 -R 17 , R 25 , capacitors C 9 -C 10 , C 13 , a diode D 15 , and a comparator  220 . As shown in  FIG. 2   b , the resistor R 12  and the capacitor C 9  are connected between the node  217  and ground, and the capacitor C 10  and the resistor R 14  are connected in series between the node  217  and the non-inverting input of the comparator  220 . The resistor R 13  is connected between ground and the common node connection of the capacitor C 10  and the resistor R 14 . The resistors R 15 -R 17  are configured to form a voltage divider that provides a threshold voltage to the inverting input of the comparator  220 . This threshold voltage is modulated with the full wave rectified line voltage, which is provided by the power supply  206  to the common node connection of the resistors R 15 -R 16  over a line  240  via the resistor R 17 . In the illustrated embodiment, this threshold voltage is modulated with the full wave rectified line voltage to generate a variable threshold voltage (V CVT ) that varies continuously with the line voltage. When a significant di/dt event(s) causes the voltage level of the sensed signal provided to the non-inverting input of the comparator  220  via the input resistor R 14  to exceed the level of the continuously variable threshold voltage (V CVT ) at the inverting input of the comparator  220 , the output of the comparator  220  is driven to its positive rail, thereby generating a pulse for charging the capacitor C 13  through the diode D 15  and the resistor R 25 . The common node connection of the diode D 15  and the capacitor C 13  is connected to an input of the processing unit  208  (see  FIG. 2   a ), which is operative to take measurements of the voltage level across the capacitor C 13 , and to analyze the voltage measurements using one or more algorithms to determine whether the detected levels resulted from an arc fault or a nuisance load. 
       FIG. 2   c  depicts an illustrative embodiment of the power supply  206 . As shown in  FIG. 2   c , power supply  206  includes resistors R 18 -R 24 , capacitors C 11 -C 12 , diodes D 8 -D 11  and D 13 -D 14 , and a metal oxide varistor (MOV 1 ). The metal oxide varistor (MOV 1 ) is connected between the line phase and line neutral terminals of the power input to prevent excessive line voltage. The diodes D 8 -D 11  are configured to form a full wave rectified bridge operative to convert the power input to a full wave rectified signal. This full wave rectified signal is provided to the serially-connected resistors R 18 -R 21 , which limit the amount of current provided to the zener diode D 14 . The diode D 13  prevents reverse current flow from the capacitor C 11 , which is connected between ground and the common node connection of the diode D 13  and the resistor R 22 . The resistor R 22  and the capacitor C 12  are operative to perform low pass filtering of the full wave rectified signal, thereby generating the supply voltage V CC . As shown in  FIG. 2   c , the line  240  is connected to the common node connection of the resistors R 20 -R 21  to provide the full wave rectified line voltage to the arcing sense circuit  213  (see also  FIG. 2   b ). 
       FIG. 2   d  is a timing diagram depicting the relationship between the continuously variable threshold voltage (V CVT ) employed by the comparator  220 , and the sudden di/dt events caused by the nuisance load described above with reference to  FIG. 1   c . As discussed above with reference to  FIG. 2   b , the threshold voltage provided by the voltage divider R 15 -R 17  is modulated with the full wave rectified line voltage provided over the line  240  to generate the variable threshold voltage (V CVT ), which varies continuously with the line voltage. In the illustrated embodiment, the variable threshold voltage (V CVT ) varies in-phase with the full wave rectified line voltage, and varies continuously within a specified voltage range ranging from V CVT1  to V CVT3 . For example, the supply voltage V CC  may be equal to about 3.4 volts or any other suitable voltage level, and the specified voltage range may correspond to a voltage range ranging from about 0.2 volts to about 0.5 volts or any other suitable voltage range. In the illustrated embodiment, the variable threshold voltage (V CVT ) varies continuously from the voltage level V CVT1  at approximately the midpoint of the specified time windows −t 1  to t 1 , t 2  to t 3 , t 4  to t 5 , t 6  to t 7 , and t 8  to t 9  centered on the zero crossing points of the line voltage to the voltage level V CVT2  at each end of the specified time windows, and varies continuously from the voltage level V CVT2  at the ends of the specified time windows to the voltage level V CVT3  at approximately the midpoint between successive time windows. 
     As described above with reference to  FIG. 1   c , the levels of the sudden di/dt events e 1 -e 8  occurring between the time windows −t 1  to t 1  and t 2  to t 3 , between the time windows t 2  to t 3  and t 4  to t 5 , between the time windows t 4  to t 5  and t 6  to t 7 , and between the time windows t 6  to t 7  and t 8  to t 9  exceed the level of the constant threshold voltage (V CT ) employed by the prior arc fault detection apparatus  100 . Because the variable threshold voltage (V CVT ) employed by the arc fault detection apparatus  200  varies in-phase with the full wave rectified line voltage and varies continuously within the specified voltage range ranging from V CVT1  to V CVT3 , as described above, the levels of the sudden di/dt events e 1 -e 8  occurring between these respective time windows are less than the level of the variable threshold voltage (V CVT ). The levels of these sudden di/dt events are therefore not high enough to cause the output of the comparator  220  to be driven to its positive rail. Accordingly, the likelihood of the processing unit  208  incorrectly characterizing these events e 1 -e 8  as arc faults is effectively eliminated. 
       FIG. 2   e  is a timing diagram depicting the relationship between the continuously variable threshold voltage (V CVT ) employed by the comparator  220 , and sudden di/dt events caused by electrical arcing, such as an arc in series with a resistive load. As described above with reference to  FIG. 2   d , the variable threshold voltage (V CVT ) varies in-phase with the full wave rectified line voltage, and varies continuously within the specified voltage range ranging from V CVT1  to V CVT3 . Specifically, the variable threshold voltage (V CVT ) varies continuously from the voltage level V CVT1  to the voltage level V CVT2  within the specified time windows −t 1  to t 1 , t 2  to t 3 , t 4  to t 5 , t 6  to t 7 , and t 8  to t 9  centered on the zero crossing points of the line voltage, and varies continuously within the higher voltage range ranging from the voltage level V CVT2  to the voltage level V CVT3  outside of these specified time windows. 
     As shown in  FIG. 2   e , the sudden di/dt events caused by electrical arcing occur within or just outside of the time windows t 2  to t 3 , t 4  to t 5 , and t 6  to t 7  centered on the corresponding line voltage zero crossing points. For example, the events e 9 -e 10  occurring within the time window t 2  to t 3  exceed the level of the variable threshold voltage (V CVT ), while the remaining sudden di/dt events occurring within this window t 2  to t 3  are less than the level of V CVT . Further, the events e 11 -e 12  occurring within the time window t 4  to t 5  exceed the level of the variable threshold voltage (V CVT ), while the remaining sudden di/dt event occurring within this window t 4  to t 5  is less than the level of V CVT . Moreover, the events e 15 -e 16  occurring within the time window t 6  to t 7  exceed the level of the variable threshold voltage (V CVT ), while the remaining sudden di/dt event occurring within this window t 6  to t 7  is less than the level of V CVT . Accordingly, the levels of the events e 9 -e 10 , e 11 -e 12 , and e 15 -e 16  occurring within the respective time windows are high enough to cause the output of the comparator  220  to be driven to its positive rail, thereby allowing the processing unit  208  to correctly characterize these events e 9 -e 10 , e 11 -e 12 , and e 15 -e 16  as arc faults based on the voltage levels provided by the comparator  220 . 
     In addition, the event e 14  occurring just outside of the time window t 6  to t 7  exceeds the level of the variable threshold voltage (V CVT ), while the events e 13  and e 17  occurring just outside of the time windows t 4  to t 5  and t 6  to t 7 , respectively, are less than the level of V CVT . The level of the event e 14  is therefore high enough to cause the output of the comparator  220  to be driven to its positive rail, while the levels of the events e 13  and e 17  are not high enough to drive the output of the comparator  220  to its rail. Accordingly, based on the voltage levels provided by the comparator  220 , the processing unit  208  will correctly characterize the event e 14  as an arc fault, and will avoid nuisance tripping in response to the events e 13  and e 17 . It should be appreciated that the prior arc fault detection apparatus  100  would be susceptible to nuisance tripping in response to the event e 17 , in the case where the constant threshold voltage (V CT ) is equal to V CVT1 . 
     A method of operating the presently disclosed arc fault detection apparatus is described below with reference to  FIG. 3 . As shown in  FIG. 3 , the presently disclosed method includes sensing at least one signal associated with a power input, in which the sensed signal is indicative of at least one potential arcing event (see step  300 ), and comparing whether a level of the sensed signal exceeds a level of a variable threshold voltage, in which the variable threshold voltage varies in-phase with a full wave rectified input line voltage (see step  302 ). In the event the sensed signal occurs within one of a plurality of specified time windows centered on a plurality of zero crossing points, respectively, of the input line voltage, the level of the sensed signal is compared with a level of the variable threshold voltage that varies continuously from a first voltage level at a midpoint of the specified time window to a higher second voltage level at respective ends of the specified time window (see step  304 ). In the event the sensed signal occurs outside of the plurality of specified time windows, the level of the sensed signal is compared with a level of the variable threshold voltage that varies continuously from the higher second voltage level to a still higher third voltage level at a midpoint between successive ones of the plurality of specified time windows (see step  306 ). A comparison signal is then generated indicating whether the sensed signal level exceeds the variable threshold voltage level, thereby providing an indication as to whether the potential arcing event corresponds to an arc fault or a nuisance condition (see step  308 ). 
     Having described the above illustrative embodiments, other alternative embodiments or variations may be made. For example, it was described that a significant di/dt event can cause the voltage level of the full wave rectified signal provided to the non-inverting input of the comparator  220  (see  FIG. 2   b ) to exceed the level of the continuously variable threshold voltage (V CVT ), thereby causing the output of the comparator  220  to be driven to its positive rail. In an alternative embodiment, this comparator circuit may be replaced with an operational amplifier (op amp) circuit configured to produce, in response to such a significant di/dt event(s), one or more voltage levels or pulse widths having corresponding magnitudes proportional to the magnitude of the sudden di/dt event. Further, the processing unit  208  (see  FIG. 2   b ) may be configured to characterize such sudden di/dt events as arc faults or nuisance loads based at least in part on the magnitudes of these voltage levels or pulse widths. 
     In addition, it was described that the presently disclosed arc fault detection apparatus may be employed to monitor a resistive load for the occurrence of electrical arcing events. In alternative embodiments, the disclosed arc fault detection apparatus may be employed to monitor a capacitive load, an inductive load, or any other suitable type of load, for the occurrence of such arcing events. 
     It is noted that the presently disclosed arc fault detection apparatus and method may be employed in any suitable digital, analog, or mixed signal environment for detecting and distinguishing between electrical arc faults and nuisance conditions. For example, the presently disclosed apparatus and method may be employed in any suitable residential, commercial, industrial, or military application for detecting and distinguishing between electrical arc faults and nuisance conditions with increase reliability. 
     It will be appreciated by those of ordinary skill in the art that modifications to and variations of the above-described arc fault detection apparatus employing a continuously variable threshold voltage may be made without departing from the inventive concepts disclosed herein. Accordingly, the invention should not be viewed as limited except as by the scope and spirit of the appended claims.