Patent Publication Number: US-7586801-B2

Title: Multi-port semiconductor memory device

Description:
The present patent application is a Continuation of application Ser. No. 11/541,236, filed Sep. 28, 2006 now U.S. Pat. No. 7,349,272. 

   FIELD OF THE INVENTION 
   The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device including a plurality of ports for transmitting information with external devices. 
   DESCRIPTION OF RELATED ARTS 
   Most memory devices such as a random access memory (RAM) include only one port for transmitting data with external chipsets. The port is constituted with a plurality of input/output (I/O) pins. The memory device including single port employs a parallel I/O interface for concurrently transmitting multi-bit data through a plurality of data lines connected to the plurality of I/O pins respectively. The I/O interface uses a data transmission scheme for transmitting data via data lines, each of which is connected between two devices. The data line uses a bus for transmitting signals such as an address signal, a data signal, and a control signal. 
   The parallel I/O interface provides a high data process speed because it can simultaneously transmit multi-bit data through a plurality of data lines. Therefore, the parallel I/O interface is widely used in a short distance transmission that requires a high speed. However, because a large number of buses are included for the parallel I/O interface, a data transmission cost increases when the data transmission is performed between long distance. Due to the limitation of the single port, a plurality of memory devices is independently configured so as to support various multi-media functions in terms of hardware of a multi-media system. While an operation for a certain function is carried out, an operation for another function cannot be concurrently carried out. Considering the disadvantage of the parallel I/O interface, many attempts to change the parallel I/O interface into serial I/O interface have been made. Also, considering compatible expansion with devices having other serial I/O interfaces, the change to serial I/O interface in I/O environment of the semiconductor memory device is required. Moreover, appliance devices for audio and video are embedded into display devices, such as a high definition television (HDTV) and a liquid crystal display (LCD) TV. Because these appliance devices require independent data processing, there is a demand for multi-port memory devices having a serial I/O interface using a plurality of ports. 
   A conventional multi-port memory device having a serial I/O interface includes a processor for processing serial I/O signals, and a DRAM core for performing a parallel low-speed operation. The processor and the DRAM core are implemented on the same wafer, that is, a single chip. 
     FIG. 1  is block diagram of a conventional semiconductor memory device including a serial I/O interface. 
   As shown, the semiconductor memory device includes two ports PORT 0  and PORT 1  and four banks BANK 0  to BANK 3 . Each port is connected to a plurality of serial I/O pads, e.g., TX 0 +, TX 0 −, RX 0 +, and RX 0 −. Each of the ports PORT 0  and PORT 1  and each of the banks BANK 0  to BANK 3  in the semiconductor memory device are connected via a global data bus. The global data bus includes reception buses PRX 0 &lt; 0 : 3 &gt; and PRX 1 &lt; 0 : 3 &gt; and transmission buses PTX 0 &lt; 0 : 3 &gt; and PTX 1 &lt; 0 : 3 &gt;. The reception buses PRX 0 &lt; 0 : 3 &gt; and PRX 1 &lt; 0 : 3 &gt; transmit a data signal from a corresponding port to a corresponding bank. The transmission buses PTX 0 &lt; 0 : 3 &gt; and PTX 1 &lt; 0 : 3 &gt; transmit a data signal from a corresponding bank to a corresponding port. The reception bus, e.g., PRX 0 &lt; 0 : 3 &gt;, can transmit a parallel data signal output from a corresponding port, e.g., PORT 0 , to every bank BANK 0  to BANK 3 . The transmission bus, e.g., PTX 0 &lt; 0 : 3 &gt;, transmits a parallel data signal output from every bank BANK 0  to BANK 3  to a corresponding port, e.g., PORT 0 . 
   The data signal output from the port, e.g., PORT 0 , includes information designating a destination out of the banks BANK 0  to BANK 3  and second ports PORT 0  and PORT 1 . Therefore, signals indicating which ports the signals access and which banks access through the ports are inputted to the first to fourth banks BANK 0  to BANK 3 . Accordingly, the port information is selectively transferred to the banks and the bank information is transferred to the first and second ports PORT 0  and PORT 1  via the global I/O data buses. 
   The ports PORT 0  and PORT 1  respectively include a serializer/deserializer (SERDES) device. A deserializer included in the SERDES device converts the data signal serially input from the serial reception I/O pads RX+ and RX− to a parallel format and transmits the data signal in parallel to a core area of the corresponding bank via the reception buses PRX 0 &lt; 0 : 3 &gt; and PRX 1 &lt; 0 : 3 &gt;. A serializer included in the SERDES device converts the data signal input from the core area to a serial format. 
     FIG. 2  is a block diagram of the port shown in  FIG. 1 . 
   As shown, the port, e.g., PORT 0 , communicates with an external device by employing a serial I/O interface via the serial I/O pads, e.g., TX 0 +, TX 0 −, RX 0 +, and RX 0 −. The data signals input from the serial reception I/O pads RX+ and RX− and output to the serial transmission I/O pads TX+ and TX− are serial signals of a high speed. Generally, the high speed signal includes differential signals for smooth data recognition. The differential signals are distinguished by indicating the serial I/O pads TX 0 +, TX 0 −, RX 0 + and RX 0 − with “+” and “−”. 
   The port, e.g., PORT 0 , includes a driver  21 , a serializer  22 , an input latch  23 , a clock generator  24 , a sampler  25 , a deserializer  26 , and an output unit  27 . 
   The driver  21  outputs the data signal serialized by the serializer  22  to an external device through the serial transmission I/O pads TX 0 + and TX 0 − in a differential type. The serializer  22  serializes the data signal in parallel format input from the input latch  23  in synchronism with the internal clock and outputs the data signal in serial format to the driver  21 . The input latch  23  latches the data signal outputted via the transmission bus PTX 0 &lt; 0 : 3 &gt; from the banks in synchronism with the internal clock and transmits the latched signals to the serializer  22 . The sampler  25  samples data signal input from the external device through the serial reception I/O pads RX 0 + and RX 0 − in synchronism with the internal clock and transmits the sampled signal to the deserializer  26 . The deserializer  26  parallelizes the external signals input from the sampler  25  in synchronism with the internal clock and outputs the parallel data signal to the output unit  27 . The output unit  27  transmits the data signal from the deserializer  26  to the banks via the reception bus PRX 0 &lt; 0 : 3 &gt;. The clock generator  24  receives a reference clock RCLK from the external device to generate an internal clock. In some case, the internal clock has the same period and phase as the reference clock RCLK. In other case, the internal clock is generated by modifying the period or the phase of the reference clock RCLK. Further, the clock generator  24  can generate a single internal clock or generate a plurality of internal clocks which have various periods and phases. 
   The other port PORT 1  included in the semiconductor memory device shown in  FIG. 1  has the same structure with that of the port PORT 0  shown in  FIG. 2 . 
   An operation of the ports, e.g., PORT 0 , will be described below in detail. 
   First, a process of deserializing the data signal and transmitting the parallel data signal via the reception bus PRX 0 &lt; 0 : 3 &gt; will be described. The data signal from the external device is input through the reception pads RX 0 + and RX 0 − in a frame format at high speed. 
   The external signals are sampled through the sampler  25  in synchronism with the internal clock output from the clock generator  24 . The sampler  25  transmits the sampled data signal to the deserializer  26 . The deserializer  26  deserializes the data signal input from the sampler  25  in synchronism with the internal clock and outputs the deserialized data signal as the parallel data signal to the output unit  27 . The output unit  27  transmits the parallel data signal to the banks via the reception bus PRX 0 &lt; 0 : 3 &gt;. 
   Next, a process of serializing the parallel data signal output via the transmission bus PTX 0 &lt; 0 : 3 &gt; and transmitting the serial data signal to the external devices through the serial transmission I/O pads TX 0 + and TX 0 − will be described below. 
   The parallel data signal are transmitted to the input latch  23  via the transmission bus PTX 0 &lt; 0 : 3 &gt;. The input latch  23  latches the data signal in synchronism with the internal clock and transmits the latched signal to the serializer  22 . The serializer  22  serializes the data signal transmitted from the input latch  23  in synchronism with the internal clock to transmit the serialized data signal to the driver  21 . The driver  21  outputs the serialized data signal to the external devices through the serial transmission I/O pads TX 0 + and TX 0 −. 
   As described above, the conventional semiconductor memory device includes the ports performing the data communication with the external devices in the high-speed serial I/O interface and converting the data signal into serial/parallel format. Such ports are essential for the semiconductor memory device to concurrently perform several functions with the external devices. Accordingly, it is important to detect a performance error of the ports for reliable operation of the semiconductor memory device and the system including it. 
   SUMMARY OF THE INVENTION 
   Embodiments of the present invention are directed to a semiconductor memory device for reliably performing a data communication with external devices through a plurality of ports. 
   In accordance with an aspect of the present invention, there is provided a semiconductor memory device including: a plurality of ports, a plurality of banks, a global data bus, a test mode determiner, a test input/output (I/O) controller; and a plurality of selectors. The ports perform a serial I/O data communication with external devices. The banks perform a parallel I/O data communication with the ports. The global data bus transmits a signal between the banks and the ports. The test mode determiner determines an operation mode of the semiconductor memory device by generating a test mode enable signal in response to a test mode control signal. The test I/O controller transmits and receives a test signal with the ports in response to the test mode enable signal during a port test mode. Each of the selectors receives the test signal output from the corresponding port in series and feedback the test signal to the corresponding port. The operation mode includes the port test mode for testing an operation of the ports and a normal operation mode for data communication between the external devices and the banks. 
   In accordance with another aspect of the present invention, there is provided a semiconductor memory including a plurality of first pads, a plurality of second pads, a plurality of ports, a plurality of banks, a first and a second data bus, a test mode determiner, a test I/O controller, and a plurality of selectors. The first pads provide a serial I/O data communication. The second pads provide a parallel I/O data communication. The ports perform the serial I/O data communication with external devices. The banks perform the parallel I/O data communication with the ports. The first data bus transmits a first signal from the ports to the banks. The second data bus transmits a second signal from the banks to the ports. The test mode determiner generates a test mode enable signal and a port selection signal in response to a test mode control signal. The test I/O controller transmits and receives a test signal with the ports in response to the test mode enable signal during a port test mode. Each of the selectors receives the test signal output from the corresponding port in series and feeds back the test signal to the corresponding port in response to the port selection signal. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The above and other objects and features of the present invention will become apparent from the following description of preferred embodiments taken in conjunction with the accompanying drawings, in which: 
       FIG. 1  is block diagram of a conventional semiconductor memory device including a serial I/O interface; 
       FIG. 2  is a block diagram of a port shown in  FIG. 1 ; 
       FIG. 3  is a block diagram of the semiconductor memory device in accordance with an embodiment of the present invention; 
       FIG. 4  is a block diagram of a parallel test I/O controller shown in  FIG. 3  in accordance with an embodiment of the present invention; 
       FIG. 5  is a schematic circuit diagram of a first selector shown in  FIG. 3 ; 
       FIG. 6  is a schematic circuit diagram of a second selector shown in  FIG. 3 ; 
       FIG. 7  is a schematic circuit diagram of a bank output driver shown in  FIG. 3 ; 
       FIG. 8  is a schematic circuit diagram for explaining an operation of the semiconductor memory device during the port test mode; 
       FIG. 9  is a block diagram of the parallel test I/O controller shown in  FIG. 3  in accordance with another embodiment of the present invention; 
       FIG. 10  is a schematic circuit diagram of a selector shown in  FIG. 9 ; 
       FIG. 11  is a block diagram of the semiconductor memory device in accordance with sill another embodiment of the present invention; 
       FIG. 12  is a block diagram of a port shown in  FIG. 11 ; and 
       FIG. 13  is a schematic circuit diagram of a latch connected to the global data lines of the present invention. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
   Hereinafter, a delay locked loop (DLL) device in accordance with the present invention will be described in detail referring to the accompanying drawings. 
     FIG. 3  is a block diagram of the semiconductor memory device in accordance with an embodiment of the present invention. 
   As shown, the semiconductor memory device includes two ports PORT 0  and PORT 1 , four banks BANK 0  to BANK 3 , a plurality of serial input/output (I/O) pads TX 0 +, TX 0 −, RX 0 +, RX 0 −, TX 1 +, TX 1 −, RX 1 +, and RX 1 −, a plurality of parallel I/O pads IN&lt; 0 : 3 &gt;, T&lt; 0 : 1 &gt;, and OUT&lt; 0 : 3 &gt;. The semiconductor memory device further includes a test mode determiner  31  and a parallel test I/O controller  32 . 
   The serial I/O pads TX 0 +, TX 0 −, RX 0 +, RX 0 −, TX 1 +, TX 1 −, RX 1 +, and RX 1 − are used for communication between external devices and the ports PORT 0  and PORT 1  at a high speed. The serial I/O pads includes serial transmission I/O pads TX 0 +, TX 0 −, TX 1 + and TX 1 − for transmitting a serial output data signal output from the ports PORT 0  and PORT 1  to the external devices at a high speed and serial reception I/O pads RX 0 +, RX 0 −, RX 1 +, and RX 1 − for transmitting a serial input data signal from the external devices to the ports PORT 0  and PORT 1  at a high speed. 
   The parallel I/O pads includes test reception pads IN&lt; 0 : 3 &gt;, test transmission pads OUT&lt; 0 : 3 &gt;, and a test control pad T&lt; 0 : 1 &gt;. The test reception pads IN&lt; 0 : 3 &gt; transmits a parallel test input signal from an external test device to the parallel test I/O controller  32 . The test transmission pads OUT&lt; 0 : 3 &gt; transmits a parallel test output signal from the parallel test I/O controller  32  to the external test device. The test control pad T&lt; 0 : 3 &gt; transmits a parallel test control signal from the external test device to the test mode determiner  31 . The number of the test reception pads IN&lt; 0 : 3 &gt; and the test transmission pads OUT&lt; 0 : 3 &gt; can be varied. In case shown in  FIG. 3 ,  4  bit data is transmitted via the test reception pads IN&lt; 0 : 3 &gt; and the test transmission pads OUT&lt; 0 : 3 &gt;. The test control pad T&lt; 0 : 1 &gt; can be replaced with a serial I/O pad. The test control signal can be directly input to the parallel test I/O controller  32  and, in this case, the test control pad T&lt; 0 : 1 &gt; can be removed. 
   The test mode determiner  31  determines an operation mode of the semiconductor memory device out of a normal operation mode and a port test mode in response to the test control signal. The test mode determiner  31  decodes the test control signal and generates a test mode enable signal TMEN. Further, the test mode determiner  31  generates port selection signal TMEN_P 0  and TMEN_P 1  for selecting a target port out of the ports PORT 0  and PORT 1  which will be tested. The test mode enable signal TMEN is activated as a logic high level during a test mode. In some embodiment, the test mode enable signal TMEN can be generated by logically combining the port selection signal TMEN_P 0  and TMEN_P 1 . 
   The parallel test I/O controller  32  activated by the test mode enable signal TMEN transmits the test input signal input through the test reception pads IN&lt; 0 : 3 &gt; to transmission bus PTX 0 &lt; 0 : 3 &gt; or PTX 1 &lt; 0 : 3 &gt; and outputs the test output signal from reception bus PRX 0 &lt; 0 : 3 &gt; or PRX 1 &lt; 0 : 3 &gt; through the test transmission pads OUT&lt; 0 : 3 &gt;. The test output signal is generated by the corresponding bank in response to the corresponding test input signal. The transmission buses PTX 0 &lt; 0 : 3 &gt; and PTX 1 &lt; 0 : 3 &gt; and the reception buses PRX 0 &lt; 0 : 3 &gt; or PRX 1 &lt; 0 : 3 &gt; are global buses connected between ports PORT 0  and PORT 1  and the banks BANK 0  to BANK 3 . 
     FIG. 4  is a block diagram of the parallel test I/O controller  32 A shown in  FIG. 3  in accordance with an embodiment of the present invention. 
   As shown, the test parallel I/O controller  32 A includes a test input signal transmitter  321 A and a test output signal transmitter  322 A. The test input signal transmitter  321 A transmits the test input signal input through the test reception pads IN&lt; 0 : 3 &gt; to transmission bus, e.g., PTX 0 &lt; 0 : 3 &gt;. The test output signal transmitter  322 A transmits the test output signal from reception bus, e.g., PRX 0 &lt; 0 : 3 &gt; to the test transmission pads OUT&lt; 0 : 3 &gt;. The test input signal transmitter  321 A includes a receiver  3211 A, an aligner  3212 A, and a driver  3213 A. The receiver  3211 A receives the test input signal input from the external test device via the test reception pads IN&lt; 0 : 3 &gt;. The aligner  3212 A aligns the test input signal from the receiver  3211 A in synchronism with an internal clock ICLK. The internal clock ICLK generated by the clock generator  24  is shown in  FIG. 2 . The clock generator can be implemented with a phase locked loop (PLL) and a delay locked loop (DLL). The driver  3213 A outputs the test input signal aligned by the aligner  3212 A to the transmission bus, e.g., PTX 0 &lt; 0 : 3 &gt;. The test output signal transmitter  322 A includes a receiver  3221 A, an aligner  3222 A, and a driver  3223 A. The receiver  3221 A receives the test output data output from the port, e.g., PORT 0 , through the reception bus, e.g., RX 0 &lt; 0 : 3 &gt;. The aligner  3222 A aligns the test output signal in synchronism with the internal clock ICLK. The driver  3223 A outputs the test output signal aligned by the aligner  3222 A to the test transmission pads OUT&lt; 0 : 3 &gt;. 
   During a normal operation mode, the port, e.g., PORT 0 , deserializes the serial input data signal and transmits the deserialized input data signal to the reception bus, e.g., PRX&lt; 0 : 3 &gt;. Also, the port, e.g., PORT 0 , serializes the data signal input through the transmission bus, e.g., PTX 0 &lt; 0 : 3 &gt;, and outputs as the serial output signal through the serial transmission I/O pads TX 0 + and TX 0 −. During a port test mode, the port, e.g., PORT 0 , serializes the test input signal input through the transmission bus, e.g., PTX 0 &lt; 0 : 3 &gt; and outputs to the transmission pads TX 0 + and TX 0 −. Further, the port, e.g., PORT 0 , serializes test transmission signals TXP 0  and TXN 0  selected by a selector, e.g., a first selector  33 , and outputs to the reception bus, e.g., PRX&lt; 0 : 3 &gt;. 
   The first selector  33  selects one of the serial input data signals and the test transmission signals TXP 0  and TXN 0  and outputs as reception signals RXP 0  and RXN 0  in response to the test mode enable signal TMEN. 
     FIG. 5  is a schematic circuit diagram of the first selector  33  shown in  FIG. 3 . 
   As shown, the first selector  33 A includes two inverters INV  1  and INV 2  and four transmission gates TG 1 , TG 2 , TG 3 , and TG 4 . During the port test mode, the test mode enable signal TMEN is activated as a logic high level. The second and the fourth transmission gates TG 2  and TG 4  turned on. Accordingly, the test transmission signals TXP 0  and TXN 0  are fed back as the reception signals RXP 0  and RXN 0  to the port PORT 0 . During a normal operation mode, the test mode enable signal TMEN is inactive as a logic low level and, therefore, the first and the third transmission gates TG 1  and TG 3  are turned on. Accordingly, the serial input data signal is fed back to the port PORT 0  as the reception signal RXP 0  and RXN 0 . 
     FIG. 6  is a schematic circuit diagram of a second selector  34  shown in  FIG. 3 . 
   As shown, the second selector  34  configured between the serial reception pads RX 1 + and RX 1 − and the port PORT 1  has the similar structure with the first selector  33 A shown in  FIG. 5 . That is, the second selector  34  transmits test transmission signals TXP 1  and TXN 1  to the ports during the port test mode and transmits the serial input data signal input through serial reception I/O pads RX 1 + and RX 10  during the normal operation mode. 
   Meanwhile, each of the banks BANK 0  to BANK 3  respectively includes bank output drivers DRVP 0  and DRVP 1 . The bank output drivers DRVP 0  and DRVP 1  are controlled not to transmit a data from the corresponding bank to the transmission bus, e.g., PTX 0 &lt; 0 : 3 &gt;, during the port test mode. 
     FIG. 7  is a schematic circuit diagram of the bank output driver DRVP 0  shown in  FIG. 3 . 
   As shown, the bank output driver DRVP 0  includes four inverters INV 5  to INV 8 , a NOR gate NOR, a NAND gate NAND, a PMOS transistor MP, and an NMOS transistor MN. During the port test mode, the bank output driver DRVP 0  is blocked to transmit the data DOUT from the corresponding bank to the transmission bus PTX 0 &lt; 0 : 3 &gt; in response to the test mode enable signal TMEN of the logic high level. Meanwhile, the bank output driver DRVP 0  transmits the data DOUT to the transmission bus PTX 0 &lt; 0 : 3 &gt; in response to the test mode enable signal TMEN of the logic low level during the normal operation mode. The bank output driver DRVP 0  shown in  FIG. 7  is included for every bank in the semiconductor memory device. Another bank output driver DRVP 1  included in the banks BANK 0  to BANK 3  has the similar structure to the bank output driver DRVP 0 . 
     FIG. 8  is a schematic circuit diagram for explaining an operation of the semiconductor memory device during the port test mode. 
   In case shown in  FIG. 8 , the semiconductor memory device tests an operation of the port PORT 0 . The test mode determiner  31  generates the test mode enable signal TMEN determining the operation mode of the semiconductor memory device based on a test mode control signal input through the test control pad T&lt; 0 : 1 &gt;. The test mode enable signal TMEN has a logic high level for the port test mode and has a logic low level for the normal operation mode. 
   During the normal operation mode, the parallel test I/O controller  32  is disabled in response to the test mode enable signal TMEN of the logic low level. The parallel test input signal input through the test reception pads IN&lt; 0 : 3 &gt; is not transmitted to the transmission bus PTX 0 &lt; 0 : 3 &gt;. The first selector  33  selects the serial input data signal input through the serial reception I/O pads RX 0 + and RX 0 − and transmits as the reception signals RXP 0  and RXN 0  to the port PORT 0  in response to the test mode enable signal TMEN of the logic low level. The port PORT 0  samples the serial input data signal, deserializes the sampled input data signal, and transmits the desrialized input data signal to the reception bus PRX 0 &lt; 0 : 3 &gt;. Because the parallel test I/O controller  32  is disabled, the input data signal loaded at the reception bus PRX 0 &lt; 0 : 3 &gt; is not transmitted to the test transmission pads OUT&lt; 0 : 3 &gt; but only transmitted to a corresponding bank input driver RCVP 0 . The input data signal transmitted to the bank input driver RCVP 0  in parallel is transmitted to a memory cell array in a core area of the semiconductor memory device. 
   Meanwhile, the input data signal output from the port, e.g., PORT 0 , can be transmitted to any banks BANK 0  to BANK 3  through the reception bus, e.g., PRX&lt; 0 : 3 &gt;. Therefore, it is required to designate a destination bank of the input data signal. To this end, the input data signal includes an additional bit, i.e., a bank data bit, for designating a corresponding destination bank. Though it is not described in the drawings, each of the ports PORT 0  and PORT 1  includes an additional circuit for decoding the bank data bit and each of the banks BANK 0  to BANK 3  includes a bank controller for determining whether the input signal data is valid for the corresponding bank. 
   Returning to  FIG. 8 , a data signal stored in the memory cell array in the corresponding bank is loaded at the transmission bus PTX 0 &lt; 0 : 3 &gt; through the bank output driver DRVP 0 . The data signal loaded to the transmission bus PTX 0 &lt; 0 : 3 &gt; is transmitted to the port PORT 0 . The port PORT 0  serializes the data signal and outputs the serial data signal to the external device through the serial transmission I/O pads TX 0 + and TX 0 −. 
   During the port test mode, the test mode determiner  31  outputs the test mode enable signal TMEN of the logic high level in response to the test mode control signal. The parallel test I/O controller  32  transmits the test input signal input through the test reception pads IN&lt; 0 : 3 &gt; to the transmission bus PTX 0 &lt; 0 : 3 &gt; in parallel. The output driver DRVO becomes a high impedance state in response to the test mode enable signal. Therefore, the signal from the cell area of the bank is not transmitted to the transmission bus PRX 0 &lt; 0 : 3 &gt;. 
   The port PORT 0  receives and serializes the test input signal through the transmission bus PTX 0 &lt; 0 : 3 &gt; and outputs the serialized test input signal through the serial transmission I/O pads TX 0 + and TX 0 −. The serialized test input signal output from the port PORT 0  is also transmitted to the first selector  33  as the test transmission signals TXP 0  and TXN 0 . The first selector  33  selects the test transmission signals TXP 0  and TXN 0  and outputs as the reception signals RXP 0  and RXN 0  in response to the test mode enable signal TMEN of the logic high level. The port PORT 0  deserializes the reception signals RXP 0  and RXN 0  and transmits to the reception bus PRX 0 &lt; 0 : 3 &gt;. The reception signals RXP 0  and RXN 0  loaded at the reception bus PRX 0 &lt; 0 : 3 &gt; is input to the parallel test I/O controller  32 . The parallel test I/O controller  32  outputs the reception signals RXP 0  and RXN 0  as the test output signal to the external test device through the test transmission pads OUT&lt; 0 : 3 &gt;. The external test device receiving the test output signal determines whether the port PORT 0  operates correctly. 
     FIG. 9  is a block diagram of the parallel test I/O controller  32 B shown in  FIG. 3  in accordance with another embodiment of the present invention. 
   As shown, the parallel test I/O controller  32 B includes a test input signal transmitter  321 B and a test output signal transmitter  322 B. The test input signal transmitter  321 B transmits the test input signal input through the test reception pads IN&lt; 0 : 3 &gt; to transmission buses PTX 0 &lt; 0 : 3 &gt; and PTX 1 &lt; 0 : 3 &gt;. The test output signal transmitter  322 B transmits the test output signal from reception buses PRX 0 &lt; 0 : 3 &gt; and PRX 1 &lt; 0 : 3 &gt; to the test transmission pads OUT&lt; 0 : 3 &gt;. 
   The test input signal transmitter  321 B includes a receiver  3211 B, an aligner  3212 B, and a first and a second driver  3213 B and  3214 B. The receiver  3211 B and the aligner  3212 B are similar to the receiver  3211 A and the aligner  3212 A shown in  FIG. 4 . The number of drivers included in the test input signal transmitter  321 B is corresponding to the number of ports included in the semiconductor memory device. The semiconductor memory device shown in  FIG. 3  includes two ports PORT 0  and PORT 1 . Accordingly, two drivers  3213 B and  3214 B are included in the test input signal transmitter  321 B. The first and the second drivers  3213 B and  3214 B are respectively controlled by the port selection signals TMEN_P 0  and TMEN_P 1 . The port selection signals TMEN_P 0  and TMEN_P 1  are generated based on test mode control signal input to test mode determiner  31  through the test control pad T&lt; 0 : 1 &gt;. In another embodiment, the port selection signals TMEN_P 0  and TMEN_P 1  can be generated by using test signals input from the external test device. 
   The test output signal transmitter  322 B includes a driver  3221 B, an aligner  3222 B, and a receiver  3223 B. The test output signal transmitter  322 B further includes a selector  3224 B. The driver  3221 B, the aligner  3222 B, and the receiver  3223 B are similar to those shown in  FIG. 4 . The selector  3224 B selects one of the signals input through the reception buses PRX 0 &lt; 0 : 3 &gt; and PRX 1 &lt; 0 : 3 &gt; in response to the port selection signals TMEN_P 0  and TMEN_P 1 . For example, when the first port selection signal TMEN_P 0  is a logic low level, the selector  3224 B selects the signal input through the first reception bus PRX 0 &lt; 0 : 3 &gt;. 
     FIG. 10  is a schematic circuit diagram of the selector  3224 B shown in  FIG. 9 . 
   As shown, the selector  3224 B includes two transmission gates TG 9  and TG 10 . The ninth transmission gate TG 9  transmits the signal input through the first reception bus PRX 0 &lt; 0 : 3 &gt; in response to the first port selection signal TMEN_P 0  of the logic low level. The tenth transmission gate TG 10  transmits the signal input through the second reception bus PRX 1 &lt;O: 3 &gt; in response to the second port selection signal TMEN_P 1  of the logic level. 
     FIG. 11  is a block diagram of the semiconductor memory device in accordance with still another embodiment of the present invention. 
   Comparing to the semiconductor memory device shown in  FIG. 3 , the semiconductor memory device shown in  FIG. 11  commonly uses the serial I/O pads, e.g., TX 0 +, TX 0 −, RX 0 +, and RX 0 −, for the normal operation mode and the port test mode. That is, the semiconductor memory device uses the serial transmission I/O pads, e.g., TX 0 + and TX 0 −, instead of the test transmission pads OUT&lt; 0 : 3 &gt; and uses the serial reception I/O pads, e.g., RX 0 + and RX 0 −, instead the test reception pads IN&lt; 0 : 3 &gt; during the port test mode. Accordingly, the number of I/O pads included in the semiconductor memory device is reduced and the internal circuitry of the ports, e.g., PORT 0 , is changed as described below. The other constituents shown in  FIG. 11  such as a test mode determiner  122 , a parallel test I/O controller  123 , global buses, e.g., PTX 0 &lt; 0 :n&gt;, and a plurality of selectors are similar to those shown in  FIG. 3 . 
     FIG. 12  is a block diagram of the port PORT 0  shown in  FIG. 11 . 
   The port, e.g., PORT 0 , outputs the transmission signals to the serial transmission I/O pads, e.g., TX 0 + and TX 0 −, during the normal operation mode and outputs the test transmission signals TXP 0  and TXN 0  to the selector  121  during the port test mode. As shown in  FIG. 12 , the port PORT 0  includes a test output driver  138  in addition to the blocks shown in  FIG. 2 . That is, a driver  131 , a serializer  132 , an input latch  133 , a clock generator  134 , a sampler  135 , a deserializer  136 , and an output unit  137  are similar to those shown in  FIG. 2 . The test output driver  138  transmits the test transmission signals TXP 0  and TXN 0  from the serializer  132  to the selector  121  in series during the port test mode in response to the test mode enable signal TMEN of a logic high level. Meanwhile, the driver  131  transmits the transmission signal in response to an inverted test mode enable signal TMENb. The inverted test mode enable signal TMENb has an opposite phase with the test mode enable signal TMEN. During the port test mode, the driver  131  becomes a high impedance state in response to the inverted test mode enable signal of a logic low level and does not transmit the transmission signal to the transmission I/O pads TX 0 + and TX 0 −. Every port shown in  FIG. 11  has the similar structure with that shown in  FIG. 12 . 
   The operation of the semiconductor memory device shown in  FIG. 11  is described below. A test mode control signal is input through the test control pad T&lt; 0 : 3 &gt;. The test mode determiner  122  decides the operation mode of the semiconductor memory device by generating the test mode enable signal TMEN in response to the test mode control signal. The test mode control signal has a logic high level for the port test mode and has a logic low level for the normal operation mode. 
   During the normal operation mode, the parallel test I/O controller  123  is disabled by the test mode enable signal TMEN of a logic low level. Accordingly, external signals input through the serial reception I/O pads, e.g., RX 0 + and RX 0 −, are not transmitted to the reception buses, e.g., PRX 0 &lt; 0 :n&gt;. The external signals are input to the selector, e.g.,  121 . The selector  121  receiving the external signals and serial test signals TXP 0  and TXN 0  selects the external signals in response to the first port selection signal TMEN_P 0  of a logic low level and transmits the external signals as the reception signals RXP 0  and RXN 0  to the first port PORT 0 . The first port PORT 0  samples and deserializes the reception signals RXP 0  and RXN 0  and, then, transmits to the reception bus PRX 0 &lt; 0 :n&gt;. Because the parallel test I/O controller  123  is disabled, the reception signals RXP 0  and RXN 0  loaded at the reception bus PRX 0 &lt; 0 :n&gt; are not transmitted to the parallel test I/O controller  123  but only transmitted to a corresponding bank input driver RCVP 0 . The reception signals RXP 0  and RXN 0  transmitted to the bank input driver RCVP 0  in parallel are transmitted to a memory cell array in a core area of the semiconductor memory device. Meanwhile, the signal output from the port PORT 0  can be transmitted to any banks BANK 0  to BANK 3  through the reception bus, e.g., PRX&lt; 0 : 3 &gt;. Therefore, the port PORT 0  determines the destination bank for the reception signals RXP 0  and RXN 0 . Meanwhile, a data signal stored in the memory cell array in the corresponding bank is loaded at the transmission bus PTX 0 &lt; 0 :n&gt; through the bank output driver DRVP 0 . The data signal loaded to the transmission bus PTX 0 &lt; 0 :n&gt; is transmitted to the port PORT 0 . The port PORT 0  serializes the data signal and outputs the serial data signal to the external device through the serial transmission I/O pads TX 0 + and TX 0 −. 
   During the port test mode, the test mode determiner  122  outputs the test mode enable signal TMEN of a logic high level in response to the test mode control signal. The parallel test I/O controller  123  transmits a test input signal input through the serial reception I/O pads, e.g., RX 0 + and RX 0 −, to the transmission bus PTX 0 &lt; 0 :n&gt; in parallel. The output driver DRVO included in the banks becomes a high impedance state in response to the test mode enable signal TMEN and, accordingly, does not transmit data signal from the bank to the transmission bus PTX 0 &lt; 0 :n&gt;. The port PORT 0  serializes the test input signal input through the transmission bus PTX 0 &lt; 0 :n&gt; and outputs the serialized test input signal as the test transmission signals TXP 0  and TXN 0  to the first selector  121  through the test output driver  138  shown in  FIG. 12 . The first selector  121  receiving the test transmission signals TXP 0  and TXN 0  and the external input signal input through the serial reception I/O pads RX 0 + and RX 0 − selects the test transmission signals TXP 0  and TXN 0  in response to the port selection signal of the logic low level. The port PORT 0  deserializes the reception signals RXP 0  and RXN 0  and transmits to the reception bus PRX 0 &lt; 0 :n&gt;. The reception signals RXP 0  and RXN 0  loaded at the reception bus PRX 0 &lt; 0 :n&gt; is input to the parallel test I/O controller  123 . The parallel test I/O controller  123  outputs the reception signals RXP 0  and RXN 0  as the test output signal to the external test device through the serial transmission I/O pads TX 0 + and TX 0 −. The external test device receiving the test output signal determines whether the port PORT 0  operates correctly. 
     FIG. 13  is a schematic circuit diagram of a latch connected to the global data lines of the present invention. The latch is used for reliable data transmission. 
   The semiconductor memory device of the present invention including several ports in order to perform a data communication with external devices makes it possible to reliably detect an operation error of the ports. Further, the semiconductor memory device can test the ports for converting the parallel/serial data regardless of the fault of the DRAM core in the banks 
   The present application contains subject matter related to Korean patent application Nos. 2005-90917 and 2006-32946, filed in the Korean Patent Office on Sep. 29, 2005 and on Apr. 11, 2006, the entire contents of which is incorporated herein by reference. 
   While the present invention has been described with respect to the particular embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.