Patent Publication Number: US-2022229962-A1

Title: Simulation method and device, power wire topology network, test circuit and storage medium

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This is a continuation of International Application No. PCT/CN2021/104786 filed on Jul. 6, 2021, which claims priority to Chinese Patent Application No. 202110070959.2 filed on Jan. 19, 2021. The disclosures of these applications are hereby incorporated by reference in their entirety. 
    
    
     BACKGROUND 
     At present, the design process of integrated circuit design includes circuit design, pre-simulation, layout design, post-simulation and other processes. Herein, the circuit design is specifically to complete the design of a circuit according to circuit functions, and the pre-simulation specifically performs the simulation of the circuit functions, including the simulation of power consumption, current, voltage, temperature, input and output features and other parameters. The pre-simulation does not consider the influence of parasitic capacitance resistance generated by metal wire routing in the circuit. After the layout design is completed, the parasitic capacitance resistance is extracted again, and the extracted parasitic capacitance resistance is added to the circuit for post-simulation and circuit design verification and optimization. If the verification fails, the layout design is adjusted until to pass the verification, and then the finial layout is determined. 
     SUMMARY 
     This disclosure relates to, but is not limited, to a simulation method and device, a power wire topology network, a test circuit and a storage medium. 
     Embodiments of this application provide a simulation method, including the following operations. 
     A power wire topology network is generated according to a power wire layout, the power wire topology network includes a plurality of first layer of metal wires arranged in a transverse direction, a plurality of second layer of metal wires arranged in a longitudinal direction, power child nodes and a parasitic element, and the parasitic element is located between the two power child nodes. 
     The minimum voltage of a power input node of each circuit module in a circuit corresponding to the power wire topology network is determined, and the power input node is one of the power child nodes in each circuit module. 
     Time sequence simulation is performed according to the minimum voltage of the power input node of each circuit module and the post-simulation circuit network list of an integrated circuit. 
     Embodiments of this application further provide a simulation device, which includes a memory and a processor. 
     The memory is configured to store an executable instruction of the processor. 
     The processor is configured to: 
     generate a power wire topology network according to a power wire layout. The power wire topology network includes a plurality of first layer of metal wires arranged in a transverse direction, a plurality of second layer of metal wires arranged in a longitudinal direction, power child nodes and a parasitic element, and the parasitic element is located between the two power child nodes; 
     determine the minimum voltage of a power input node of each circuit module in a circuit corresponding to the power wire topology network. The power input node is one of the power child nodes in each circuit module; and 
     perform time sequence simulation according to the minimum voltage of the power input node of each circuit module and the post-simulation circuit network list of an integrated circuit. 
     Embodiments of this application further provide a computer-readable storage medium, which stores a computer execution instruction, and when being executed by a processor, the computer execution instruction is configured to implement any method in the first aspect and various possible implementation modes of the first aspect. 
     Embodiments of this application further provide a computer program product, which includes a computer program, and when being executed by a processor, the computer program is configured to implement any method in the first aspect and various possible implementation modes of the first aspect. 
     Embodiments of this application further provide a power wire topology network, which includes a plurality of first layer of metal wires arranged in a transverse direction, a plurality of second layer of metal wires arranged in a longitudinal direction, power child nodes and a parasitic element. 
     The parasitic element is located between the two power child nodes. 
     Herein, the intersections of the first layer of metal wires and the second layer of metal wires are the power child nodes. 
     Embodiments of this application further provide a test circuit, which includes at least one power source and the power wire topology network in any one of the fifth aspect and various possible implementation modes of the fifth aspect. 
     The input current of each current source is the current of each circuit module in the circuit corresponding to the power wire topology network. 
     A quantity of the power source is same as that of the circuit module included in the circuit corresponding to the power wire topology network. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       To better clarify the technical solution of this application or the related art, the drawings required to illustrate the embodiments or the related art will be simply described below. It is apparent that the drawings described below merely illustrate some embodiments of this application. Those ordinarily skilled in the art can obtain other drawings without creative labor on the basis of those drawings. 
         FIG. 1  is a flow schematic diagram of a simulation method according to embodiments of this application. 
         FIG. 2  is a schematic diagram of a power wire layout. 
         FIG. 3  is a schematic diagram of a power wire topology network generated by the power wire layout shown in  FIG. 2 . 
         FIG. 4  is a schematic diagram of a power wire topology network generated by the power wire layout shown in  FIG. 2 . 
         FIG. 5  is a schematic diagram of a circuit module included in a circuit corresponding to the power wire topology network shown in  FIG. 3 . 
         FIG. 6  is a flow schematic diagram of a simulation method according to embodiments of this application. 
         FIG. 7  is a schematic diagram of the test circuit corresponding to  FIG. 4 . 
         FIG. 8  is a flow schematic diagram of a simulation method according to embodiments of this application. 
         FIG. 9  is a schematic diagram of a circuit structure obtained through adding the minimum voltage of a power input node of each circuit module into a power input node of each circuit module. 
         FIG. 10  is a structural schematic diagram of a simulation device according to embodiments of this application. 
         FIG. 11  is a structural schematic diagram of a simulation device according to embodiments of this application. 
     
    
    
     DETAILED DESCRIPTION 
     In order to make the purpose, technical solution and advantages of this application clearer, the technical solutions in this application are clearly and completely elaborated below in combination with the drawings. It is apparent that the described embodiments are only a part of the embodiments of this application but not all. Based on the embodiments of this application, all the other embodiments obtained by those of ordinary skill in the art on the premise of not contributing creative effort should belong to the protection scope of this application. 
     During a typical simulation process, on one hand, repeated verification is required, and on the other hand, the network list scale of the layout post-simulation including the parasitic capacitance resistance is very large and the simulation time is long, resulting in a slow simulation speed. 
     In the current integrated circuit design process, if the network list scale of the post-simulation including the parasitic capacitance resistance of the power wire layout is very large, the simulation time is very long, therefore actual project demands cannot be met. However, if the post-simulation network list does not include a power wire parasitic element, the influence of the power layout parasitism on the time sequence feature cannot be accurately evaluated, thereby reducing simulation precision. In order to solve this problem, this application provides a simulation method and device, a power wire topology network, a test circuit and a storage medium. In the simulation method provided by this application, the power wire topology network is generated according to the power wire layout first, and then the minimum voltage of the power input node of each circuit module in the circuit corresponding to the power wire topology network is determined, finally, the time sequence simulation is performed according to the minimum voltage of the power input node of each circuit module and the integrated circuit post-simulation circuit network list. Herein, the integrated circuit post-simulation circuit network list is a layout post-simulation network list not including the parasitic capacitance resistance, namely, the simulation time is approximately the same as the pre-simulation time not including a power parasitic effect. Therefore, the post-simulation result can be quickly obtained, the simulation speed is improved, and the time sequence simulation considers the minimum voltage of the power input node of each circuit module. The difference between the minimum voltage and the ideal power voltage is the power wire IR-Drop, therefore the influence of the power wire IR-Drop on the time sequence parameter of the integrated circuit can be evaluated through the normal time sequence simulation, and the simulation precision can be improved. The time sequence parameter includes, for example, time delay and other time sequence parameters, thereby achieving the compromise between simulation precision and simulation speed. 
     The simulation method provided by this application can be applied before the layout design and during the layout design. The power wire IR-Drop in the power wire layout will generate influence on the time sequence parameter of the integrated circuit. The simulation method provided by the application determines the minimum voltage of the power input node of each circuit module in the circuit corresponding to the power wire topology network through generating the power wire topology network according to the power wire layout, namely determines the power wire IP-Drop. The time sequence simulation is performed according to the minimum voltage of the power input node of each circuit module and the post-simulation circuit network list of the integrated circuit, the influence of the power wire IP-Drop on the time sequence parameter of the integrated circuit can be evaluated through the simulation result, therefore guidance can be provided to the design of the integrated circuit. When the layout design is completed, the parasitic resistance and parasitic capacitance of the whole circuit are extracted and subjected to post-simulation, the time sequence result can be checked again according to the post-simulation result, such that the final guidance can be provided to the layout design. Therefore, the error of the layout design can be reduced, and the development period and development cost of the integrated circuit design are reduced. 
     The simulation method and device, the power wire topology network, the test circuit and the storage medium process/structure are described in details below through embodiments. 
       FIG. 1  is a flow schematic diagram of a simulation method according to embodiments of this application. An executive body of the simulation method in this embodiment can be a simulation device or a piece of simulation equipment, which can be applied before the layout design. As shown in  FIG. 1 , the simulation method of this embodiment may include the following operations. 
     At S 101 , a power wire topology network is generated according to a power wire layout, the power wire topology network includes a plurality of first layer of metal wires arranged in a transverse direction, a plurality of second layer of metal wires arranged in a longitudinal direction, power child nodes and a parasitic element, and the parasitic element is located between the two power child nodes. 
     In some embodiments,  FIG. 2  is a schematic diagram of a power wire layout. As shown in  FIG. 2 , the power wire layout is composed of four first layer of metal wires M 1  and three second layer of metal wires M 2 , the first layer of metal wires M 1  can be located above or below the second layer of metal wires M 2 , and each first layer of metal wire M 1  has an intersection with each second layer of metal wire. 
     The power wire topology network is generated according to the power wire layout. Taking the power wire layout shown in  FIG. 2  as an example,  FIG. 3  is a schematic diagram of a power wire topology network generated by the power wire layout shown in  FIG. 2 . As shown in  FIG. 3 , the power wire topology network includes the plurality of first layer of metal wires M 1  arranged in a transverse direction, the plurality of second layer of metal wires M 2  arranged in a longitudinal direction, the power child nodes (VDD 11 -VDD 31 ) and the parasitic element Q. Herein, the intersections of the first layer of metal wires and the second layer of metal wires in the power wire layout are the power child nodes, the parasitic element is located between the two power child nodes, and one parasitic element is arranged between every two power child nodes. 
     The power wire topology network is generated according to the power wire layout, as an implementable mode, the power wire topology network can include the following operations. 
     At S 1011 , the intersections of the first layer of metal wires and the second layer of metal wires are determined as the power child nodes. 
     At S 1012 , the parasitic element is arranged every two power child nodes, and the parasitic element includes a first parasitic resistance, a second parasitic resistance and a parasitic capacitance. Herein, a first end of the first parasitic resistance is connected to a first power child node, a second end of the first parasitic resistance is connected to a first end of the second parasitic resistance and a first end of the parasitic capacitance, a second end of the second parasitic resistance is connected to the second power child node, and a second end of the parasitic resistance is connected to a grounding terminal. 
     At S 1013 , the power wire topology network is obtained according to the first layer of metal wires, the second layer of metal wires, the power child nodes and the parasitic element. 
     Taking the power wire layout shown in  FIG. 2  as an example,  FIG. 4  is a schematic diagram of a power wire topology network generated by the power wire layout shown in  FIG. 2 . As shown in  FIG. 4 , the parasitic element Q is arranged between every two power child nodes, the parasitic element Q includes a first parasitic resistance R 1 , a second parasitic resistance R 2  and a parasitic capacitance C 1 . Taking the parasitic element between the power child node VDD 31  and the power child node VDD 32  as an example, the first end of the first parasitic resistance R 1  is connected to the first power child node VDD 31 , the second end of the first parasitic resistance R 1  is connected to the first end of the second parasitic resistance R 2  and the first end of the parasitic capacitance C 1 , the second end of the second parasitic resistance R 2  is connected to the second power child node VDD 32 , and the second end of the parasitic capacitance C 1  is connected with the grounding terminal. 
     Herein, the resistance values of the first parasitic resistance R 1  and the second parasitic resistance R 2  are each R/2, and the capacitance value of the parasitic capacitance is C. R and C are determined according to the following formula. 
     
       
      
       R=Rsh*L/W;  
      
     
     
       
      
       C=Cu*L*W.  
      
     
     Herein, L is the length of a metal wire between the power child nodes, W is the width of the metal wire between the power child nodes, Rsh is the sheet resistance value of the metal, and Cu is the capacitance value of a unit area. 
     It should be understood that the metal wires between different power child nodes have different lengths and widths, when the generated power wire topology network is subjected to a subsequent simulation, the initial length and the initial width of the metal wire between the power child nodes can be set according to an empirical value, such that an initial power wire topology network is obtained. The time sequence simulation is performed through S 102  and S 103  according to the initial power wire topology network, the length and width of the metal wire between every two power child noes in the initial power wire topology network can be adjusted according to the simulation result, such that the adjusted power wire topology network can be obtained. The time sequence simulation is performed through S 102  and S 103  according to the adjusted power wire topology network until the power wire topology network of which the power wire IR-Drop has less influence on the time sequence parameter of the integrated circuit is determined through the simulation. The embodiments of this application do not make any limitations to the specific adjustment rules for the length and width of the metal wire between every two power child nodes. 
     At S 102 , the minimum voltage of a power input node of each circuit module in a circuit corresponding to the power wire topology network is determined, and the power input node is one of the power child nodes in each circuit module. 
     In some embodiments, taking the power wire topology network shown in  FIG. 3  or  FIG. 4  as an example,  FIG. 5  is a schematic diagram of a circuit module included in a circuit corresponding to the power wire topology network shown in  FIG. 3 . As shown in  FIG. 5 , the circuit corresponding to the power wire topology network shown in  FIG. 3  includes six circuit modules (X 1 -X 6 ), the power input node of each circuit module is VDD shown in  FIG. 5 , and it can be seen that the power input node of each circuit module is one of the power child nodes in each circuit module. 
     Herein, the minimum voltage of the power input node of each circuit module in the circuit corresponding to the power wire topology network is determined, taking the circuit module shown in  FIG. 5  as an example, namely, the minimum voltage of the power input node VDD of each circuit module in the circuit module X 1 -X 6  is determined. 
     At S 103 , the time sequence simulation is performed according to the minimum voltage of the power input node of each circuit module and the post-simulation circuit network list of the integrated circuit. 
     Herein, the post-simulation circuit network list of the integrated circuit is a layout post-simulation network list not including the parasitic capacitance resistance, and the simulation result obtained in S 103  is the time sequence analysis result considering the influence of the maximum IR-Drop. 
     According to the simulation method provided by the embodiments, the power wire topology network is generated according to the power wire layout first, and then the minimum voltage of the power input node of each circuit module in the circuit corresponding to the power wire topology network is determined, finally, the time sequence simulation is performed according to the minimum voltage of the power input node of each circuit module and the post-simulation circuit network list of the integrated circuit. Herein, the post-simulation circuit network list of the integrated circuit is a layout post-simulation network list not including the parasitic capacitance resistance, namely, the simulation time is approximately the same as the pre-simulation time not including a power parasitic effect. Therefore, the post-simulation result can be quickly obtained, the simulation speed is improved, and the time sequence simulation considers the minimum voltage of the power input node of each circuit module. The difference between the minimum voltage and the ideal power voltage is the power wire IR-Drop, thus the influence of the power wire IR-Drop on the time sequence parameter of the integrated circuit can be evaluated through the normal time sequence simulation, and the simulation precision can be improved, thereby achieving the compromise between simulation precision and simulation speed. 
       FIG. 6  is a flow schematic diagram of a simulation method according to embodiments of this application. As shown in  FIG. 6 , the simulation method of this embodiment is based on the method shown in  FIG. 5 , optionally, the S 102  can be implemented by the following steps. 
     At S 1021 , a first simulation is performed by a preset power voltage according to the power wire topology network, so as to obtain the current of each circuit module in the circuit corresponding to the power wire topology network. 
     In some embodiments, taking six circuit modules shown in  FIG. 5  as an example, the first simulation is performed by the preset power voltage according to the power wire topology network shown in  FIG. 4 , and the current of the obtained six circuit modules is as shown in Table 1. 
     
       
         
           
               
             
               
                 TABLE 1 
               
             
            
               
                   
               
               
                 Current of Six Circuit Modules 
               
            
           
           
               
               
               
            
               
                   
                 Circuit module 
                 Current 
               
               
                   
               
               
                   
                 X1 
                 I1 (t) 
               
               
                   
                 X2 
                 I2 (t) 
               
               
                   
                 X3 
                 I3 (t) 
               
               
                   
                 X4 
                 I4 (t) 
               
               
                   
                 X5 
                 I5 (t) 
               
               
                   
                 X6 
                 I6 (t) 
               
               
                   
               
            
           
         
       
     
     Herein, current In (t), n=1, 2, . . . , 6 is a curve that changes over time. 
     At S 1022 , the circuit simulation is performed according to the parasitic element between the power child nodes and the current of each circuit module, so as to obtain the voltage waveform of the power input node of each circuit module. 
     As an implementable mode, the above S 1022  can include the following operations. 
     First, the current source is set for each circuit module according to the current of each circuit module, so as to obtain a test circuit. 
     In some embodiments, the current source can be set for the power wire topology network, one current source is set for each circuit module, and the quantity of the current source is the same as that of the circuit module included in the circuit corresponding to the power wire topology network. The input current of each set current source is the current In (t) of each circuit module, and then the test circuit is obtained. 
     Taking the power wire topology network shown in  FIG. 4  as an example,  FIG. 7  is a schematic diagram of the test circuit corresponding to  FIG. 4 . The test circuit in this embodiment is also named as the IR-Drop test circuit. As shown in  FIG. 7 , the first end of each current source P is connected to the power input node of each circuit module, and the second end of each current source P is connected to the grounding terminal. Taking the circuit module X 1  as an example, the first end of the current source P is connected to the power input node VDD 31  of the circuit module X 1 , and the second end of the current source P is connected with the grounding terminal. 
     Then, the test circuit is subjected to circuit simulation according to the parasitic element between the power child nodes and the current of each circuit module, so as to obtain the voltage waveform of the power input node of each circuit module. 
     In some embodiments, the test circuit is subjected to the circuit simulation after the test circuit is obtained, so as to obtain the voltage waveform of the power input node of each circuit module. Taking the test circuit shown in  FIG. 7  as an example, for each circuit module in the test circuit, taking the circuit module X 1  as an example, the circuit simulation is performed according the current In (t) of the circuit module X 1  and parasitic element Q between the power child node VDD 31  and the power child node VDD 32  in the circuit module X 1 . The simulation can be performed by a Simulation Program with Integrated Circuit Emphasis (Spice), so as to obtain the voltage waveform VDD 31  ( t ) of the power input node VDD 31  of each circuit module X 1 , and description is made herein by taking a circuit module X 1  as an example. It can be understood that the test circuit is subjected to the simulation, so as to obtain the voltage waveform VDD 31 ( t )-VDD 24 ( t ) of the power input nodes of the six circuit modules. 
     At S 1023 , the minimum voltage of the power input node of each circuit module is determined according to the voltage waveform of the power input node of each circuit module. 
     In some embodiments, the voltage waveform is an oscillogram of a voltage value that changes with time, the minimum voltage value of each voltage waveform can be found out according to the voltage waveform, namely, the minimum voltage of the power input node of each circuit module is the voltage during a time period, and the voltage is recorded as VDDn min in Table 2. Table 2 shows a relationship among the current In (t) corresponding to each module in the test circuit shown in  FIG. 7 , the voltage waveform VDDn (t) of the power input node of each circuit module and the minimum voltage VDDn min of the power input node of each circuit module. 
     
       
         
           
               
               
               
               
             
               
                 TABLE 2 
               
               
                   
               
               
                   
                   
                   
                 Minimum 
               
               
                   
                   
                   
                 voltage of the power 
               
               
                 Circuit 
                   
                 Voltage waveform 
                 input node of each 
               
               
                 module 
                 Current 
                 of the power input node 
                 circuit module 
               
               
                   
               
             
            
               
                 X1 
                 I2 (t) 
                 VDD31 (t) 
                 VDD31min 
               
               
                 X2 
                 I2 (t) 
                 VDD32 (t) 
                 VDD32min 
               
               
                 X3 
                 I3 (t) 
                 VDD33 (t) 
                 VDD33min 
               
               
                 X4 
                 I4 (t) 
                 VDD22 (t) 
                 VDD22min 
               
               
                 X5 
                 I5 (t) 
                 VDD23 (t) 
                 VDD23min 
               
               
                 X6 
                 I6 (t) 
                 VDD24 (t) 
                 VDD24min 
               
               
                   
               
            
           
         
       
     
     According to the simulation method provided by the embodiments, the first simulation is performed with a preset power voltage according to the power wire topology network, so as to obtain the current of each circuit module in the circuit corresponding to the power wire topology network. The circuit simulation is performed according to the parasitic element between the power child nodes and the current of each circuit module, so as to obtain the voltage waveform of the power input node of each circuit module, and then the minimum voltage of the power input node of each circuit module is determined according to the voltage waveform of the power input node of each circuit mode, so as to determine the minimum voltage of the power input node of each circuit module in the circuit corresponding to the power wire topology network. 
       FIG. 8  is a flow schematic diagram of a simulation method according to embodiments of this application. As shown in  FIG. 8 , the simulation method of this embodiment is based on the method shown in  FIG. 6 , optionally, the S 103  can be implemented by the following steps. 
     At S 1031 , the minimum voltage of the power input node of each circuit module is added to the power input node of each circuit module, so as to obtain the circuit embedding the minimum voltage. 
     In some embodiments,  FIG. 9  is a schematic diagram of a circuit structure obtained through adding the minimum voltage of a power input node of each circuit module to a power input node of each circuit module. 
     At S 1032 , the circuit embedding the minimum voltage is subjected to time sequence simulation according to the post-simulation circuit network list of the integrated circuit. 
     In some embodiments, the circuit embedding the minimum voltage is subjected to time sequence simulation according to the post-simulation circuit network list of the integrated circuit, and the obtained simulation result is the time sequence analysis result considering the influence of the maximum pressure drop. According to the simulation method of this embodiment, the influence of the power wire IP-Drop on the time sequence parameter of the integrated circuit is accurately evaluated without adding the simulation time. All results are based on Spice and layout post-simulation network list, and the simulation precision is ensured, thereby achieving the compromise between simulation precision and simulation speed. 
       FIG. 10  is a structural schematic diagram of a simulation device according to embodiments of this application. As shown in  FIG. 10 , the simulation device of this embodiment can include a generating module  11 , a determining module  12  and a simulation module  13 . Herein, the generating module  11  is configured to generate the power wire topology network according to the power wire layout, the power wire topology network includes a plurality of first layer of metal wires arranged in a transverse direction, a plurality of second layer of metal wires arranged in a longitudinal direction, power child nodes and a parasitic element, and the parasitic element is located between the two power child nodes. 
     The determining module  12  is configured to determine the minimum voltage of a power input node of each circuit module in a circuit corresponding to the power wire topology network, and the power input node is one of the power child nodes in each circuit module. 
     The simulation module  13  is configured to perform the time sequence simulation according to the minimum voltage of the power input node of each circuit module and the post-simulation circuit network list of an integrated circuit. 
     In some embodiments, the generating module  11  is configured to determine the intersections of the first layer of metal wires and the second layer of metal wires as the power child nodes. 
     The parasitic element is arranged between every two power child nodes, and the parasitic element includes a first parasitic resistance, a second parasitic resistance and a parasitic capacitance. Herein, a first end of the first parasitic resistance is connected to the first power child node, a second end of the first parasitic resistance is connected to a first end of the second parasitic resistance and a first end of the parasitic resistance, a second end of the second parasitic resistance is connected to the second power child node, and a second end of the parasitic resistance is connected to a grounding terminal. 
     The power wire topology network is obtained according to the first layer of metal wires, the second layer of metal wires, the power child nodes and the parasitic element. 
     In some embodiments, the resistance values of the first parasitic resistance and the second parasitic resistance are each R/2, and the capacitance value of the parasitic capacitance is C. 
     R and C are determined by the following formula. 
     
       
      
       R=Rsh*L/W;  
      
     
     
       
      
       C=Cu*L*W.  
      
     
     Herein, L is the length of a metal wire between the power child nodes, W is the width of the metal wire between the power child nodes, Rsh is the sheet resistance value of the metal, and Cu is the capacitance value of a unit area. 
     In some embodiments, the determining module  12  is configured to: 
     perform the first simulation by a preset power voltage according to the power wire topology network, so as to obtain the current of each circuit module in the circuit corresponding to the power wire topology network; 
     perform the circuit simulation according to the parasitic element between the power child nodes and the current of each circuit module, so as to obtain the voltage waveform of the power input node of each circuit module; and 
     determine the minimum voltage of the power input node of each circuit module according to the voltage waveform of the power input node of each circuit module. 
     In some embodiments, the determining module  12  is configured to: set the current source for each circuit module according to the current of each circuit module, so as to obtain a test circuit; and 
     perform circuit simulation on the test circuit according to the parasitic element between the power child nodes and the current of each circuit module, so as to obtain the voltage waveform of the power input node of each circuit module. 
     In some embodiments, the simulation module  13  is configured to add the minimum voltage of the power input node of each circuit module to the power input node of each circuit module, so as to obtain the circuit embedding the minimum voltage; and 
     perform time sequence simulation on the circuit embedding the minimum voltage according to the post-simulation circuit network list of the integrated circuit. 
     According to the device provided by the embodiments of this application, the above method embodiments can be executed, the implementation principles and technical effects can refer to the above method embodiments, and details will not be made herein. 
       FIG. 11  is a structural schematic diagram of a simulation device according to embodiments of this application. As shown in  FIG. 0.11 , the simulation device of this embodiment can include a memory  101  and a processor  102 . 
     The memory  101  is configured to store an executable instruction of the processor  102 . 
     The processor  102  is configured to: 
     generate a power wire topology network according to a power wire layout. The power wire topology network includes a plurality of first layer of metal wires arranged in a transverse direction, a plurality of second layer of metal wires arranged in a longitudinal direction, power child nodes and a parasitic element, and the parasitic element is located between the two power child nodes; 
     determine the minimum voltage of a power input node of each circuit module in a circuit corresponding to the power wire topology network, and the power input node is one of the power child nodes in each circuit module; and 
     perform time sequence simulation according to the minimum voltage of the power input node of each circuit module and the post-simulation circuit network list of the integrated circuit. 
     Optionally, the memory  101  can be independent, or integrated with the processor  102 . 
     When memory  101  is independent of a device other than the processor  102 , the simulation device of this embodiment can further include a bus  103 . 
     The bus  103  is configured to connect the memory  101  and the processor  102 . 
     Optionally, this embodiment further includes a communication interface  104 , which can be connected to the processor  102  through the bus  103 . 
     The device can be configured to execute various steps and/or processes in the above method embodiments. 
     Embodiments of this application further provide a computer-readable storage medium, which stores a computer execution instruction, and when the instruction runs on a computer, the computer executes the method of the above embodiment. 
     Embodiments of this application further provide a computer program product, which includes a computer program, and when being executed by a processor, the computer program implements the method of the above embodiment. 
     Embodiments of this application further provide a power wire topology network and a test circuit, which are described below in combination with  FIG. 3 ,  FIG. 4  and  FIG. 7 . 
     Embodiments of this application further provide a power wire topology network, which includes a plurality of first layer of metal wires arranged in a transverse direction, a plurality of second layer of metal wires arranged in a longitudinal direction, power child nodes and a parasitic element. The parasitic element is located between the two power child nodes, and the intersections of the first layer of metal wires and the second layer of metal wires are the power child nodes. 
     Taking the power wire topology network show in  FIG. 3  as an example, as shown in  FIG. 3 , the power wire topology network includes a plurality of first layer of metal wires M 1  arranged in a transverse direction, a plurality of second layer of metal wires M 2  arranged in a longitudinal direction, power child nodes (VDD 11 -VDD 31 ) and a parasitic element Q. Herein, the intersections of the first layer of metal wires M 1  and the second layer of metal wires M 2  are the power child nodes, the parasitic element is located between the two power child nodes, and one parasitic element is arranged between every two power child nodes. 
     Optionally, the parasitic element includes a first parasitic resistance, a second parasitic resistance and a parasitic capacitance. Herein, a first end of the first parasitic resistance is connected to the first power child node, a second end of the first parasitic resistance is connected to a first end of the second parasitic resistance and a first end of the parasitic capacitance, a second end of the second parasitic resistance is connected to the second power child node, and a second end of the parasitic capacitance is connected to a grounding terminal. 
     Taking the power wire layout shown in  FIG. 4  as an example, as shown in  FIG. 4 , the parasitic element Q includes a first parasitic resistance R 1 , a second parasitic resistance R 2  and a parasitic capacitance C 1 . Taking the parasitic element between the power child node VDD 31  and the power child node VDD 32  as an example, the first end of the first parasitic resistance R 1  is connected to the first power child node VDD 31 , the second end of the first parasitic resistance R 1  is connected to the first end of the second parasitic resistance R 2  and the first end of the parasitic capacitance C 1 , the second end of the second parasitic resistance R 2  is connected to the second power child node VDD 32 , and the second end of the parasitic capacitance C 1  is connected with the grounding terminal. 
     Optionally, the resistance values of the first parasitic resistance and the second parasitic resistance are each R/2, and the capacitance value of the parasitic capacitance is C. 
     R and C are determined by the following formula. 
     
       
      
       R=Rsh*L/W;  
      
     
     
       
      
       C=Cu*L*W.  
      
     
     Herein, L is the length of a metal wire between the power child nodes, W is the width of the metal wire between the power child nodes, Rsh is the sheet resistance value of the metal, and Cu is the capacitance value of a unit area. 
     It should be noted that the power wire topology network show in  FIG. 3  and  FIG. 4  are only for examples, and the quantity of the first layer of metal wires M 1  and the second layer of metal wires M 2  can be randomly set in actual design. 
     The power wire topology network provided by this embodiment can be configured to implement the above simulation method. For example, the power wire topology network can be directly simulated through S 102 -S 103  in the simulation method shown in  FIG. 1 , thus the post-simulation result can be quickly obtained, the simulation speed is improved, and the time sequence simulation considers the minimum voltage of the power input node of each circuit module. The difference between the minimum voltage and the ideal power voltage is power wire IR-Drop, therefore the influence of the power wire IR-Drop on the time sequence parameter of the integrated circuit can be evaluated through the normal time sequence simulation, and the simulation precision can be improved, thereby achieving the compromise between simulation precision and simulation speed. 
     Embodiments of this application further provide a test circuit, which includes at least one current source and the power wire topology network in the above embodiment, such as the power wire topology network shown in  FIG. 3  or  FIG. 4 . In the test circuit, the input current of each current source is the current of each circuit module in the circuit corresponding to the power wire topology network, and the quantity of the current source is the same as that of the circuit module included in the circuit corresponding to the power wire topology network. 
     In some embodiments, the first end of each current source is the power input node of each circuit module, the second end of each current source is connected to the grounding terminal, and the power input node is one of the power child nodes in each circuit module. 
     Optionally, the current of each circuit module in the circuit corresponding to the power wire topology network is obtained based on that the power wire topology network is subjected to the first simulation with the preset power voltage. 
     Taking the test circuit shown in  FIG. 7  as an example, there are six current sources in the test circuit shown in  FIG. 7 , and the quantity of the power source is the same as the quantity  6  of the circuit module. The first end of each current source P is connected to the power input node of each circuit module, and the second end of each current source P is connected to the grounding terminal. Taking the circuit module X 1  as an example, the first end of the current source P is connected to the power input node VDD 31  of the circuit module X 1 , and the second end of the current source P is connected with the grounding terminal. 
     The test circuit provided by this embodiment can be configured to how to determine the minimum voltage of the power input node of each circuit module in the circuit corresponding to the power wire topology network in the above simulation method. The circuit simulation can be directly performed through the test circuit, so as to obtain the voltage waveform of the power input node of each circuit module. The minimum voltage of the power input node of each circuit module can be determined according to the voltage waveform of the power input node of each circuit module, therefore the time sequence simulation can be performed according to the minimum voltage of the power input node of each circuit module and the post-simulation circuit network list of the integrated circuit. 
     Finally, it should be noted that the above embodiments are merely used for illustrating the technical solution of this application instead of limiting it. Although this application is described in details with reference to the abovementioned embodiments. Those of ordinary skill in the art should understand that they can still make modifications to the technical solution recorded in the abovementioned embodiments, or make equivalent replacements to part or all of technical characteristics. However, these modifications or replacement do not separate the nature of the corresponding technical solution from the scope of the technical solution of various embodiments of this application.