Patent Publication Number: US-8115244-B2

Title: Transistor of volatile memory device with gate dielectric structure capable of trapping charges

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     The present patent application is a divisional application claiming the benefit of application Ser. No. 11/375,792, filed Mar. 14, 2006 abandoned, which is a divisional application claiming the benefit of application Ser. No. 10/883,184, filed Jun. 30, 2004 abandoned. 
    
    
     FIELD OF THE INVENTION 
     The present invention relates to a volatile memory technology; and, more particularly, to a transistor of a volatile memory with a gate dielectric structure of oxide-nitride-oxide and a method for fabricating the same. 
     DESCRIPTION OF RELATED ARTS 
     As known, each cell in a volatile dynamic random access memory (DRAM) device includes one transistor and one capacitor. 
       FIG. 1  is a cross-sectional view of a conventional transistor in a cell region of a DRAM device. Two wells  103  and  104  are sequentially formed in a silicon substrate  101 . Since an N-channel transistor is typically adopted for the DRAM device, the aforementioned two wells are a deep N-type well  103  formed in the silicon substrate  101  of P-type and a deep P-type well  104  defined within the deep N-type well  103 . 
     Also, a device isolation layer  102  is formed in the silicon substrate  101  by performing a shallow trench isolation (STI) process. After the formation of the device isolation layer  102 , a field region in which the device isolation layer  102  is formed and an active region are defined. A plurality of gate structures  107  including a gate oxide layer  106  are formed on an active region. Herein, the gate oxide layer  106  is made of silicon dioxide (SiO 2 ). A channel ion implantation region  105  for controlling a threshold voltage is formed in each of channel regions defined within portions of the P-type well  104  disposed beneath the gate structures  107 . Also, there is a source/drain  108  in each predetermined region of the silicon substrate  101  allocated between the gate structures  107 . 
     The transistor having the above described structure has a threshold voltage (V TH ) defined as follows. 
     
       
         
           
             
               
                 
                   
                     V 
                     TH 
                   
                   = 
                   
                     
                       
                         Φ 
                         MS 
                       
                       - 
                       
                         
                           Q 
                           EFF 
                         
                         
                           C 
                           OX 
                         
                       
                       + 
                       
                         2 
                         · 
                         
                            
                           
                             Φ 
                             F 
                           
                            
                         
                       
                       - 
                       
                         
                           Q 
                           B 
                         
                         
                           C 
                           OX 
                         
                       
                     
                     = 
                     
                       
                         Φ 
                         MS 
                       
                       - 
                       
                         
                           Q 
                           EFF 
                         
                         
                           C 
                           OX 
                         
                       
                       + 
                       
                         2 
                         · 
                         
                            
                           
                             Φ 
                             F 
                           
                            
                         
                       
                       + 
                       
                         
                           2 
                           · 
                           
                             
                               
                                 ɛ 
                                 s 
                               
                               · 
                               q 
                               · 
                               
                                 N 
                                 A 
                               
                               · 
                               
                                  
                                 
                                   Φ 
                                   F 
                                 
                                  
                               
                             
                           
                         
                         
                           C 
                           OX 
                         
                       
                     
                   
                 
               
               
                 
                   Eq 
                   . 
                   
                       
                   
                   ⁢ 
                   1 
                 
               
             
           
         
       
     
     Herein, ‘Φ MS ’, ‘Q EFF ’, ‘C OX ’, ‘Φ F ’, ‘Q B ’, ‘∈ s ’, ‘q’, and ‘N A ’ express a linear function between the gate structure  107  and the channel ion implantation region  105 , a charge amount of a total effective oxide layer per unit area when a gate voltage (V G ) equals to the threshold voltage (V TH ), a capacitance of the gate oxide layer per unit area, a Fermi potential of a semiconductor region, a charge amount per unit area of a depletion layer in the semiconductor region, a permittivity of the semiconductor region, a charge amount of electrons, and a doping concentration of an impurity implanted into the semiconductor region, respectively. 
     The charge amount of the total effective oxide layer per unit area ‘Q EFF ’ is expressed as follows. 
     
       
         
           
             
               
                 
                   
                     Q 
                     EFF 
                   
                   = 
                   
                     
                       Q 
                       SS 
                     
                     + 
                     
                       Q 
                       
                         it 
                         ⁡ 
                         
                           ( 
                           
                             
                               Φ 
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               S 
                             
                             = 
                             
                               
                                 2 
                                 · 
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                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               F 
                             
                           
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                     + 
                     
                       
                         ∫ 
                         0 
                         
                           T 
                           OX 
                         
                       
                       ⁢ 
                       
                         
                           
                             x 
                             · 
                             
                               ρ 
                               ⁡ 
                               
                                 ( 
                                 x 
                                 ) 
                               
                             
                           
                           
                             T 
                             OX 
                           
                         
                         · 
                         
                           ⅆ 
                           x 
                         
                       
                     
                   
                 
               
               
                 
                   Eq 
                   . 
                   
                       
                   
                   ⁢ 
                   2 
                 
               
             
           
         
       
     
     Herein, ‘Q ss ’, ‘Q il ’, ‘Φ s ’, ‘ρ(x)’, and ‘T OX ’ express a surface state fixed charge amount in an interface between the semiconductor region and the gate oxide layer  106 , an interface state charge amount in an interface between the semiconductor region and the gate oxide layer  106 , a surface potential of the semiconductor region, an average charge density of the gate oxide layer  106  measured from an interface having a distance ‘x’ between the semiconductor region and the gate oxide layer  106  to a predetermined distance ‘x+dx’, and a thickness of the gate oxide layer  106 , respectively. 
     Therefore, on the basis of the equations 1 and 2, the threshold voltage (V TH ) of the transistor in a cell region can be defined as follows. 
     
       
         
           
             
               
                 
                   
                     
                       
                         V 
                         TH 
                       
                       = 
                       
                         
                           Φ 
                           MS 
                         
                         - 
                         
                           
                             1 
                             
                               C 
                               OX 
                             
                           
                           · 
                           
                             [ 
                             
                               
                                 Q 
                                 ss 
                               
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                                 Q 
                                 
                                   it 
                                   ( 
                                   
                                     
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                                     = 
                                     
                                       
                                         2 
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     Meanwhile, advancement in DRAM technology has led to a gradual decrease in a minimum design rule, which in turn, causes a channel length and a width of the transistor of the DRAM device to be decreased. Thus, the threshold voltage of the transistor decreases because of a short channel effect and an inverse narrow width effect. As a result of this decreased threshold voltage, a punch-through phenomenon more frequently occurs between a source and a drain. 
     However, for a normal operation of the DRAM device, it is necessary to maintain the threshold voltage of the transistor of the DRAM device, and a voltage inducing the punch-through phenomenon should be higher than an operation voltage. 
     Therefore, doping concentrations of a channel region and a well region of the transistor need to be increased in order to obtain a decrease in the threshold voltage and to prevent the punch-through phenomenon. That is, as shown in the equation 3, a value of ‘V TH ’ is increased by increasing a value of ‘N A ’, a width of a depletion layer between the source and the drain is decreased to increase the voltage inducing the punch-through phenomenon. 
     Nevertheless, the increase in the doping concentration of the channel region and the well region causes potentials of the source and the drain to be increased, further resulting in adverse effects of increasing junction leakage and deteriorating a refresh characteristic of the DRAM device. These described adverse effects are shown in  FIGS. 2A and 2B . Particularly,  FIG. 2A  is a graph showing that the junction leakage increases as a doping concentration of boron into the P-type well increases.  FIG. 2B  is a graph showing that a data retention time decreases as the doping concentration of the P-type well increases. 
     As described above, in the transistor of the conventional DRAM device, the threshold voltage characteristic, the punch-through characteristic and the refresh characteristic have an offset relationship with each other. Characteristics of the transistor of the DRAM device are retained through compromising those characteristics. 
     However, as the design rule of the DRAM device has been decreased to the size less than 100 nm, it may become much difficult to satisfy the threshold voltage characteristic, the punch-through characteristic and the refresh characteristic simultaneously only by increasing the doping concentrations of the channel region and the well region. 
     SUMMARY OF THE INVENTION 
     It is, therefore, an object of the present invention to provide a transistor of a volatile memory device capable of obtaining an intended level of a threshold voltage along with a lowered doping concentration of a channel ion implantation region and a method for fabricating the same. 
     In accordance with an aspect of the present invention, there is provided a transistor in a cell region of a volatile memory device, including: a substrate of a first conductive type; a gate dielectric structure capable of trapping charges and formed on the substrate; a gate formed on the gate dielectric structure; a gate insulation layer formed on the gate; a source/drain of a second conductive type formed in a predetermined region of the substrate disposed beneath each lateral side of the gate; and a channel ion implantation region of the first conductive type formed in a predetermined region of the substrate disposed beneath the gate. 
     In accordance with another aspect of the present invention, there is provided a volatile memory device, including: a first transistor for use in a memory cell provided with a gate dielectric structure including: a bottom gate dielectric layer; a middle gate dielectric layer for trapping charges; and a top gate dielectric layer; and a second transistor for use in a logic circuit provided with a gate dielectric structure of a single oxide layer. 
     In accordance with still another aspect of the present invention, there is provided a volatile memory device, including: a first N-channel metal oxide semiconductor (NMOS) transistor for use in a memory cell provided with a gate dielectric structure including: a bottom gate dielectric layer; a middle gate dielectric layer; and a top gate dielectric layer; a second NMOS transistor for use in a logic circuit provided with a gate dielectric structure of a single oxide layer; and a P-channel metal oxide semiconductor (PMOS) transistor for use in a logic circuit provided with a gate dielectric structure including; a bottom gate dielectric layer; a middle gate dielectric layer; and a top gate dielectric layer. 
     In accordance with still another aspect of the present invention, there is provided a volatile memory device, including: a transistor for use in a memory cell, the transistor including: a substrate of a first conductive; a gate dielectric structure capable of trapping charges and formed on the substrate; a gate formed on the gate dielectric structure; a gate insulation layer formed on the gate; a source/drain of a second conductive type formed in a predetermined portion of the substrate disposed beneath each lateral side of the gate; and a channel ion implantation region of the first conductive type formed in a predetermined region of the substrate disposed beneath the gate; and a voltage generating unit for controlling a threshold voltage of the transistor for use in the memory cell by implanting charges to the gate dielectric structure through supplying a predetermined voltage to each of the substrate, the gate and the source/drain. 
     In accordance with still another aspect of the present invention, there is provided a method for forming a gate dielectric structure of a volatile memory device, wherein the volatile memory device is defined with a cell region where a transistor for use in a memory cell is formed and a peripheral region where a transistor for use in a logic circuit is formed, including the steps of: sequentially forming a first oxide layer, a dielectric layer for trapping charges and a second oxide layer on a substrate; selectively etching the second oxide layer and the dielectric layer disposed in the peripheral region; etching the first oxide layer exposed in the peripheral region as simultaneously as etching the second oxide layer in the cell region; and forming a third oxide layer in the cell region and in the peripheral region. 
     In accordance with still another aspect of the present invention, there is provided a method for forming a gate dielectric structure in a volatile memory device, wherein the volatile memory device is defined with a cell region where a first NMOS transistor for use in a memory cell is formed and a peripheral region where a second NMOS transistor for use in a logic circuit and a PMOS transistor for use in a logic circuit are formed, the method including the steps of: sequentially forming a first oxide layer, a dielectric layer for trapping charges and a second oxide layer on a substrate; selectively etching the second oxide layer and the dielectric layer in a first predetermined region of the peripheral region where the second NMOS transistor is formed; removing the first oxide layer exposed in the first predetermined region as simultaneously as etching the second oxide layer disposed in the cell region and in a second predetermined region of the peripheral region where the PMOS transistor is formed; and forming a third oxide layer in the cell region and in the peripheral region. 
     In accordance with further aspect of the present invention, there is provided a method for forming a gate dielectric structure in a volatile memory device, wherein the volatile memory device is defined with a cell region where a first NMOS transistor for use in a memory cell is formed and a peripheral region where a PMOS transistor for use in a logic circuit and a second NMOS transistor for use in a logic circuit are formed, including the steps of: sequentially forming a first oxide layer, a dielectric layer for trapping charges and a second oxide layer on a substrate; selectively etching the second oxide layer and the dielectric layer in a first predetermined region of the peripheral region where the second NMOS transistor is formed; selectively etching a portion of the second oxide layer in a second predetermined region of the peripheral region where the PMOS transistor is formed to make the second oxide layer have a decreased thickness; removing the first oxide layer exposed in the first predetermined region as simultaneously as removing the second oxide layer in the second predetermined region and a portion of the second oxide layer in the cell region; and forming a third oxide layer in the cell region and the peripheral region. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The above and other objects and features of the present invention will become better understood with respect to the following description of the preferred embodiments given in conjunction with the accompanying drawings, in which: 
         FIG. 1  is a cross-sectional view showing a transistor of a conventional dynamic random access memory (DRAM) device; 
         FIG. 2A  is a graph showing that a characteristic of junction leakage increasing in proportion to a doping concentration of boron into a P-type well; 
         FIG. 2B  is a graph showing that a data retention time decreases as a doping concentration of a P-type well increases; 
         FIG. 3  is a cross-sectional view showing a transistor of a DRAM device wherein the transistor has a gate dielectric structure of oxide, nitride and oxide (ONO) in accordance with the present invention; 
         FIG. 4A  shows cross-sectional views of a DRAM device provided with NMOS transistors in a cell region having a gate dielectric structure of ONO and NMOS and PMOS transistors in a peripheral region having a gate dielectric structure of a single oxide layer in accordance with a first embodiment of the present invention; 
         FIG. 4B  shows cross-sectional views of a DRAM device provided with NMOS transistors in a cell region and a PMOS transistor in a peripheral region each having a gate dielectric structure of ONO and an NMOS transistor in the peripheral region having a gate dielectric structure of a single oxide layer in accordance with a second and a third embodiments of the present invention; 
         FIGS. 5A to 5D  are cross-sectional views illustrating a method for fabricating the DRAM device shown in  FIG. 4A  in accordance with the first embodiment of the present invention; 
         FIGS. 6A to 6D  are cross-sectional views illustrating a method for fabricating the DRAM device shown in  FIG. 4B  in accordance with the second embodiment of the present invention; and 
         FIGS. 7A to 7E  are cross-sectional views illustrating a method for fabricating the DRAM device shown in  FIG. 4B  in accordance with the third embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     A transistor of a volatile memory device with a gate dielectric structure capable of trapping charges and a method for fabricating the same in accordance with preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. 
       FIG. 3  is a cross-sectional view showing a transistor of a dynamic random access memory (DRAM) device in accordance with the present invention. Herein, the transistor has a gate dielectric structure of oxide, nitride and oxide (ONO). 
     As shown, two wells  303  and  304  are formed in a silicon substrate  301 . In a DRAM device, a transistor in a cell region is typically an N-channel transistor, while a P-channel transistor is used in a peripheral circuit region. Thus, the two wells are a deep N-type well  303  formed in the silicon substrate  301  of P-type and a deep P-type well  304  defined within the N-type well  303 . 
     A device isolation layer  302  is formed in the silicon substrate  301  by performing a shallow trench isolation (STI) method. After the formation of the device isolation layer  302 , an active region and a field region in which the device isolation layer  302  is formed are defined. 
     Next, a plurality of gate dielectric structures  350  are formed in the active region of the silicon substrate  301 . Then, a plurality of gates  309  are formed on the corresponding gate dielectric structures  350 . A channel ion implantation region  305  for controlling a threshold voltage is formed in each of channel regions defined within portions of the P-type well  304  disposed beneath the corresponding gates  309 . Also, there is a source/drain  311  in each predetermined region of the silicon substrate  301  allocated between the gates  309 . 
     Herein, the gate dielectric structure  350  includes a first oxide layer  306 , which is a bottom gate dielectric layer, a nitride layer  307 , which is a middle gate dielectric layer and serves as a charge trapping layer, and a second oxide layer  308 , which is a top gate dielectric layer. In other words, the gate dielectric structure  350  has a structure of oxide, nitride and oxide (ONO). 
     Especially, the nitride layer  307  of the gate dielectric structure  350  plays a role in increasing a threshold voltage of a transistor in a cell region by capturing electrons during sequential processes for fabricating a semiconductor device. This increased threshold voltage can be offset by the channel ion implantation region  305  having a low concentration. As a result, the transistor in accordance with the present invention can obtain an intended threshold voltage along with the channel ion implantation region  305  having a low concentration, thereby obtaining a lowered potential. This lowered potential further results in improvements on junction leakage and refresh characteristics. 
     Meanwhile, the DRAM device in accordance with the present invention has a separate voltage generator for controlling a threshold voltage by implanting charges, e.g., electrons or holes, to the gate dielectric structure of the transistor. Because of this separate voltage generator, it is possible to control a threshold voltage after the fabrication of the transistor. If the threshold voltage needs to be controlled depending on the use of a circuit, the threshold voltage can be controlled by implanting electrons or holes to the nitride layer  307  of the gate dielectric structure  350  by supplying a predetermined voltage individually to a gate, a drain and a source. This control of the threshold voltage on operation of the transistor of the DRAM device with the gate dielectric structure of ONO is shown in Table 1 provided below. Herein, the gate, the drain and the source are a word line, a bit line BL and a storage node (SN) of a capacitor, respectively. 
     
       
         
           
               
               
               
               
               
               
             
               
                   
                 TABLE 1 
               
               
                   
                   
               
               
                   
                   
                   
                   
                 P-well in 
                   
               
               
                   
                   
                   
                   
                 Cell Region 
               
               
                   
                 Gate 
                 BL 
                 SN 
                 (=Bulk) 
                 Remarks 
               
               
                   
                   
               
             
            
               
                   
               
            
           
           
               
               
               
               
               
               
            
               
                 V TH  control 
                 V P   
                 0 V 
                 0 V 
                 OV or V BB   
                 Control to 
               
               
                 11 
                   
                   
                   
                   
                 increase V TH   
               
               
                 V TH  control 
                 V P   
                 V P   
                 OV 
                 0 V or V BB   
                 through 
               
               
                 12 
                   
                   
                   
                   
                 electron 
               
               
                   
                   
                   
                   
                   
                 implantation 
               
               
                 V TH  control 
                 0 V or V N   
                 V P   
                 V P   
                 V P   
                 Control to 
               
               
                 21 
                   
                   
                   
                   
                 decrease 
               
               
                 V TH  control 
                 OV or V N   
                 V P   
                 0 
                 OV or V BB   
                 V TH  through 
               
               
                 22 
                   
                   
                   
                   
                 hole 
               
               
                   
                   
                   
                   
                   
                 implantation 
               
               
                 Read/Write 
                 0~V PP   
                 0~V DL   
                 0~V DL   
                 V BB   
                 Same as a 
               
               
                   
                   
                   
                   
                   
                 conventional 
               
               
                   
                   
                   
                   
                   
                 operation 
               
               
                   
                   
                   
                   
                   
                 recipe 
               
               
                   
               
            
           
         
       
     
     Herein, ‘V p ’, ‘V pp ’ and ‘V DL ’ are greater than approximately OV, and V N  and V BB  are less than approximately OV. 
     As shown in Table 1, when a voltage is supplied to the gate, the drain and the source as like the case of V TH  control and the V TH  control  12 , electrons are implanted into the nitride layer of the gate dielectric structure, thereby increasing the threshold voltage. On the other hand, when a voltage is supplied individually to the gate, the drain, the source, and the P-well, holes are implanted into the nitride layer of the gate dielectric structure, thereby decreasing the threshold voltage. 
     Eventually, in a conventional transistor of a DRAM device, it is required to optimize a punch-through voltage, a refresh time and a threshold voltage simultaneously, however, the transistor having the gate dielectric structure of ONO in accordance with the present invention is first fabricated by simultaneously optimizing the punch-through voltage and the refresh time under consideration of an amount of captured charges during the formation of the nitride layer of the gate dielectric structure of ONO. The threshold voltage characteristic can be optimized after the fabrication of the above transistor depending on needs. 
     As shown in Table 1, as like the read and write operation in the conventional DRAM device, wherein the transistor has only an oxide layer as the gate dielectric structure, the read and write operation on data of the DRAM device can be driven with a high speed under a low voltage. 
       FIGS. 4A and 4B  are cross-sectional views showing a DRAM device integrated with N-channel metal oxide semiconductor (NMOS) transistors in a cell region and P-channel metal oxide semiconductor (PMOS) and NMOS transistors in a logic circuit region, i.e., a peripheral region. Particularly,  FIG. 4A  shows a first embodiment that the NMOS transistors in the cell region have a gate dielectric structure of ONO and the NMOS and PMOS transistors in the peripheral region have a gate dielectric structure of a single oxide layer.  FIG. 4B  shows that the NMOS transistors in the cell region and the PMOS transistor in the peripheral region individually have a gate dielectric structure of ONO and the NMOS transistor in the peripheral region has a gate dielectric structure of a single oxide layer in accordance with second and a third embodiments of the present invention. Also, it should be noted that the same reference numerals are used for the same constitution elements described in the first embodiment and the second embodiment. 
     Referring to  FIG. 4A , each of the NMOS transistors in the cell region has a gate dielectric structure  450  of ONO including a first oxide layer  410 , a nitride layer  411  and a second oxide layer  413 A. Herein, the first oxide layer  410 , the nitride layer  411  and the second oxide layer  413 A are a bottom gate dielectric layer, a middle gate dielectric layer functioning as a charge trapping layer and a top gate dielectric layer, respectively. On the other hand, the NMOS transistor and the PMOS transistor in the peripheral region individually have a gate dielectric structure of a single oxide layer, denoted with a reference numeral  413 B for the PMOS transistor and with a reference numeral  413 C for the NMOS transistor. 
     Herein, an effective thickness (T OX ) of the gate dielectric structure  450  including the first oxide layer  410 , the oxide layer  411  and the second oxide layer  413 A in the cell region is equal to or greater than that of the gate dielectric structure of the single oxide layer  413 B or  413 C in the peripheral region. 
     Also, as described above, the nitride layer  411  of the gate dielectric structure  450  in the cell region serves as the charge trapping layer. In addition to the use of nitride for the charge trapping layer, it is still possible to use aluminum oxide and hafnium oxide capable of capturing charges. 
     More specific to the first embodiment, in the cell region where the NMOS transistors are formed, a deep N-type well  403  is formed in a substrate  401 , and a deep P-type well  404  is defined within the deep N-type well  403 . A plurality of gate dielectric structures  450  are formed on predetermined portions of the P-type well  403 . Herein, as described above, each of the gate dielectric structures  450  includes the first oxide layer  410 , the nitride layer  411  and the second oxide layer  413 A. Also, a plurality of gates  414 A are formed on the corresponding gate dielectric structures  450 . Also, a gate insulation layer  415  is formed on each of the gate  414 A. Also, there are channel ion implantation regions  407  each formed in a predetermined region disposed beneath the corresponding gate  414 A, i.e., each channel region of the P-type well  404  and sources/drains  416 A each formed in a predetermined region of the substrate  401  disposed between each two of the gates  414 A. 
     Also, in the peripheral region where the PMOS transistors are formed, there is an N-type well  405  defined within a substrate  401 . A gate dielectric structure of a single oxide layer  413 B is formed on a predetermined portion of the N-type well  405 . A gate  414 B and a gate insulation layer  415  are sequentially formed on the gate dielectric structure of the single oxide layer  413 B. A channel ion implantation region  408  is formed in a channel region of the N-type well  405  disposed beneath the gate  414 B and the gate dielectric structure of the single oxide layer  413 B, and a source/drain  416 B is formed in each predetermined region of the substrate  401  disposed beneath each lateral side of the gate  414 B. 
     Further, in the peripheral region where the NMOS transistor is formed, there is a P-type well  406  defined within the substrate  401 . A gate dielectric structure of a single oxide layer  413 C is formed on a predetermined portion of the P-type well  406 . A gate  414 C and a gate insulation layer  415  are sequentially formed on the gate dielectric structure of the single oxide layer  413 C. A channel ion implantation region  409  is formed in a channel region of the P-type well  406  disposed beneath the gate  414 C and the gate dielectric structure of the single oxide layer  413 C, and a source/drain  416 C is formed in each predetermined region of the substrate  401  disposed beneath each lateral side of the gate  414 C. 
     Referring to  FIG. 4B , in a cell region where NMOS transistors are formed, a deep N-type well  403  is formed in a substrate  401 , and a deep P-type well  404  is defined within the deep N-type well  403 . A plurality of gate dielectric structures  450 A are formed on predetermined portions of the P-type well  404 . Herein, each of the gate dielectric structures  450 A includes a first oxide layer  410 A, a nitride layer  411 A and a second oxide layer  413 A. The nitride layer  411 A is a charge trapping layer. Also, a plurality of gates  414 A are formed on the corresponding gate dielectric structures  450 A. A gate insulation layer  415  is then formed on each of the gates  414 A. Also, there are channel ion implantation regions  107  each formed in a predetermined region disposed beneath the gate  414 A and the gate dielectric structure  450 A, i.e., each channel region of the P-type well  404 , and sources/drains  416 A each formed in a predetermined portion of the substrate  401  disposed between each two of the gates  414 A. 
     In a peripheral region where an PMOS transistor is formed, a deep N-type well  405  is formed in a substrate  401 . A gate dielectric structure  450 B is formed on a predetermined portion of the P-type well  405 . Herein, the gate dielectric structure  450 B includes a first oxide layer  410 B, a nitride layer  411 B and a second oxide layer  413 B. A gate  414 B and a gate insulation layer  415  are then sequentially formed on the gate dielectric structure  450 B. Also, there are a channel ion implantation region  408  formed in a predetermined region disposed beneath the gate  414 B and the gate dielectric structure  450 B, i.e., a channel region of the N-type well  405 , and a source/drain  416 B formed in each predetermined portion of the substrate  401  disposed beneath each lateral side of the gate  414 B. 
     Further, in the peripheral region where an NMOS transistor is formed, there is a P-type well  406  defined within the substrate  401 . A gate dielectric structure of a single oxide layer  413 C is formed on a predetermined portion of the P-type well  406 . A gate  414 C and a gate insulation layer  415  are sequentially formed on the gate dielectric structure of the single oxide layer  413 C. A channel ion implantation region  409  is formed in a channel region of the P-type well  406  disposed beneath the gate  414 C and the gate dielectric structure of the single oxide layer  413 C, and a source/drain  416 C is formed in each predetermined region of the substrate  401  disposed beneath each lateral side of the gate  414 C. 
     In accordance with the second and the third embodiments, a thickness of an effective oxide layer of the gate dielectric structure  450 A in the cell region is equal to or greater than that of an effective oxide layer of the gate dielectric structure  450 B in the peripheral region and that of an effective oxide layer of the gate dielectric structure of the single oxide layer  413 C in the peripheral region. Also, the nitride layer  411 A of the gate dielectric structure  450 A in the cell region is a charge trapping layer, and can be replaced with an oxynitride layer, aluminum oxide layer, or a hafnium oxide layer capable of trapping charges. 
       FIGS. 5A to 5D  are cross-sectional views illustrating a method for fabricating the DRAM device shown in  FIG. 4A . 
     Referring to  FIG. 5A , a field oxide layer  502  is formed in a substrate  501  made of silicon. In a cell region, a deep N-type well  503  and a deep P-type well  504  are formed. In a peripheral region, an N-type well  505  and a P-type well  506  are formed. A P-type impurity is ion implanted into each of the P-type wells  504  and  506  formed in the cell region and the peripheral region, respectively, thereby forming channel ion implantation regions  507  and  509  in the cell region and the peripheral region, respectively. Meanwhile, an N-type impurity is ion implanted into the N-type well  505  to form a channel ion implantation region  508  in the peripheral region. 
     Next, a gate dielectric structure is formed. More specifically, a first oxide layer  510 , which is a bottom gate dielectric layer, is formed on the substrate  501 . Then, middle gate dielectric layer  511  is formed on the first oxide layer  510 . Herein, the middle gate dielectric layer  511  is made of a material capable of trapping charges, and this type of material is selected from a group consisting of nitride, oxynitride, alumina (Al 2 O 3 ) and hafnium oxide (HfO 2 ). The oxynitride layer can be formed by applying a dinitrogen oxide (N 2 O) treatment or a nitrogen oxide (NO) treatment to the first oxide layer  510 . After the formation of the middle gate dielectric layer  511 , a second oxide layer  512  is formed on the middle gate dielectric layer  511 . Herein, the second oxide layer  512  serves as a buffer oxide layer. 
     Referring to  FIG. 5B , although not illustrated, a photosensitive layer is formed on the above resulting substrate structure and is patterned such that the photosensitive layer remains in the cell region. The second oxide layer  512  and the middle gate dielectric layer  511  in the peripheral region are etched. Then, the photosensitive layer is removed, and the first oxide layer  510  in the peripheral region is etched thereafter. When the first oxide layer  510  in the peripheral region is etched, the second oxide layer  512  in the cell region is etched away, or a portion of the second oxide layer  12  remains. Herein, the etching process proceeds by performing one of a dry etching process a wet etching process. 
     Referring to  FIG. 5C , a third oxide layer  513  serving as a top gate dielectric layer is formed on the middle gate dielectric layer  511  in the cell region, while in the peripheral region, the third oxide layer  513  is formed on the substrate  501 . Herein, in the cell region, a gate dielectric structure including the first oxide layer  510 , the middle gate dielectric layer  511  and the third oxide layer  513  is formed. 
     At this time, the third oxide layer  513  is preferably formed by performing a thermal oxidation process. In case that the middle gate dielectric layer  511  is made of nitride, a thickness of the third oxide layer  513  formed on the nitride-based middle gate dielectric layer  511  in the cell region is thinner than that of the third oxide layer  513  formed in the peripheral region. Thus, it is preferable to control a thickness of the remaining second oxide layer  512 , or to control the thickness of the third oxide layer  513  such that a thickness of an effective oxide layer of the gate dielectric structure in the cell region is equal to or greater than a thickness of the third oxide layer  513  in the peripheral region. 
     That is, when the second oxide layer  512  in the cell region is etched, a remaining thickness of the second oxide layer  512  is controlled to form the gate dielectric structure in the cell region by including the first oxide layer  510 , the middle dielectric layer  511 , the second oxide layer  512  and the third oxide layer  513 , or by including the first oxide layer  510 , the middle dielectric layer  511  and the third oxide layer  513  and to form the gate dielectric structure in the peripheral region by including only the third oxide layer  513 . 
     Referring to  FIG. 5D , a gate material  514  and a gate insulation layer  515  are formed on the third oxide layer  513  and are then patterned by performing an etching process with use of a gate mask. Afterwards, typical DRAM fabrication processes, e.g., a source/drain formation process, proceed to complete the fabrication of the DRAM device. 
     Meanwhile, the DRAM device shown in  FIG. 4B  is fabricated by the same processes described in  FIGS. 5A to 5D  in the exception that a second oxide layer and a middle gate dielectric layer disposed in a PMOS region where a PMOS transistor is formed in the peripheral region are masked during the etching of the second oxide layer and the middle gate dielectric layer in the peripheral region. 
     With reference to  FIGS. 6A to 6D  and  FIGS. 7A to 7E , detailed description on a method for fabricating the DRAM device shown in  FIG. 4B  will be described in detail hereinafter. Also, in  FIGS. 6A to 7E , the same reference numerals are used for the same constitution elements described in  FIGS. 5A to 5D . 
       FIGS. 6A to 6D  are cross-sectional views showing a method for fabricating the DRAM in accordance with a second embodiment of the present invention. 
     Referring to  FIG. 6A , a field oxide layer  502  is formed in a substrate  501  made of silicon. In a cell region, a deep N-type well  503  and a deep P-type well  504  are formed. In a peripheral region, an N-type well  505  and a P-type well  506  are formed. A P-type impurity is ion implanted into each of the P-type wells  504  and  506  respectively formed in the cell region and the peripheral region to form channel ion implantation regions  507  and  509  in the cell region and the peripheral region, respectively. Meanwhile, an N-type impurity is ion implanted into the N-type well  505  to form a channel ion implantation region  508  in the peripheral region. 
     Next, gate dielectric structure is formed. More specifically, a first oxide layer  510 , which is a bottom gate dielectric layer, is formed on the substrate  501 . Then, a middle gate dielectric layer  511  is formed on the first oxide layer  510 . Herein, the middle gate dielectric layer  511  is made of a material capable of trapping charges, and this type of material is selected from a group consisting of nitride, oxynitride, alumina (Al 2 O 3 ) and hafnium oxide (HfO 2 ). The oxynitride layer can be formed by applying a dinitrogen oxide (N 2 O) treatment or a nitrogen oxide (NO) treatment to the first oxide layer  510 . After the formation of the middle gate dielectric layer  511 , a second oxide layer  512  is formed on the middle gate dielectric layer  511 . Herein, the second oxide layer  512  serves as a buffer oxide layer. 
     Referring to  FIG. 6B , in a predetermined region of the peripheral region where an NMOS transistor will be formed (hereinafter referred to the NMOS region), the second oxide layer  512  and the middle gate dielectric layer  511  are selectively are etched, thereby obtaining a patterned second oxide layer  512 A and a patterned middle gate dielectric layer  511 A. Also, the etching process proceeds by employing one of a dry etching process or a wet etching process. 
     Referring to  FIG. 6C , the first oxide layer  510  exposed in the NMOS region is etched as simultaneously as the second oxide layer  512  disposed in the cell region and the patterned second oxide layer  512 A in a predetermined region of the peripheral region where a PMOS transistor will be formed (hereinafter referred to as the PMOS region) are etched. After this etching process, a patterned middle gate dielectric layer  511 A and a patterned first oxide layer  510 A are obtained in the PMOS region. 
     Referring to  FIG. 6D , a third oxide layer  513  serving as a top gate dielectric layer is formed on the above resulting structure. The third oxide layer  513  is preferably formed by performing a thermal oxidation process. Afterwards, a gate material  514  and a gate insulation layer  515  are formed on the third oxide layer  513  and are then patterned by performing an etching process with use of a gate mask. Afterwards, typical DRAM fabrication processes, e.g., a source/drain formation process, proceed to complete the fabrication of the DRAM device. 
       FIGS. 7A to 7E  are cross-sectional views showing a method for fabricating the DRAM device in accordance with a third embodiment of the present invention. 
     Referring to  FIG. 7A , a first oxide layer  510 , a middle gate dielectric layer  511  and a second oxide layer  512  are sequentially formed on a semi-finished substrate structure including various device elements. Herein, the semi-finished substrate structure is prepared by using the same processes described in  FIGS. 5A to 5D , and detailed description on the employed processes is omitted. Herein, the middle gate dielectric layer  511  is made of a material capable of trapping charges, and this type of material is selected from a group consisting of nitride, oxynitride, Al 2 O 3  and HfO 2 . The oxynitride layer can be formed by applying an N 2 O treatment or an NO treatment to the first oxide layer  510 . Also, the second oxide layer  512  serves as a buffer oxide layer. 
     Referring to  FIG. 7B , in an NMOS region, the second oxide layer  512  and the middle dielectric layer  511  are selectively etched, thereby obtaining a patterned second oxide layer  512 A and a patterned middle gate dielectric layer  511 A. At this time, the etching process proceeds by employing one of a dry etching process and a wet etching process. 
     As shown in  FIG. 7C , a portion of the patterned second oxide layer  512 A in a PMOS region is selectively etched. 
     Referring to  FIG. 7D , the first oxide layer  510  exposed in the NMOS region and a remaining portion of the patterned second oxide layer  512 A in the PMOS region are removed. As simultaneously as these removals, a portion of the second oxide layer  512  in the cell region is also removed. Herein, a remaining portion of the second oxide layer  512  is denoted with a reference numeral  512 A. 
     Referring to  FIG. 7E , a third oxide layer  513  serving as a top gate dielectric layer is formed on the above resulting structure. The third oxide layer  513  is preferably formed by performing a thermal oxidation process. Afterwards, a gate material  514  and a gate insulation layer  515  are formed on the third oxide layer  513  and are then patterned by performing an etching process with use of a gate mask. Afterwards, typical DRAM fabrication processes, e.g., a source/drain formation process, proceed to complete the fabrication of the DRAM device. 
     As described in the above first to third embodiments of the present invention, through a complete removal of the second oxide layer in the cell region and in the peripheral region, or through a control of a remaining thickness of the second oxide layer, it is possible to make a thickness of an effective oxide layer of a gate dielectric structure in the cell region and that of an effective oxide layer of a gate dielectric structure in the PMOS region equal to or greater than that of a gate dielectric structure in the NMOS region, or to make a thickness of the effective oxide layer of the gate dielectric structure in the PMOS region equal to that of the effective oxide layer of the gate dielectric structure in the NMOS region, but less than that of the effective oxide layer of the gate dielectric structure in the cell region. 
     That is, by controlling an etch target thickness of the second oxide layer when the second oxide layer formed in the cell region and the PMOS region is etched, the gate dielectric structure in the cell region and that in the PMOS region of the peripheral region includes the first oxide layer, the middle dielectric layer capable of trapping charges, the remaining portion of the second oxide layer and the third oxide layer  513 , or includes the first oxide layer, the middle dielectric layer and the third oxide layer, while the gate dielectric structure in the NMOS region of the peripheral region includes only the third oxide layer. 
     It is also possible to make the gate dielectric structure in the cell region include the first oxide layer, the middle dielectric layer, the remaining second oxide layer and the third oxide layer, while the gate dielectric structure in the PMOS transistor includes the first oxide layer, the middle dielectric layer and the third oxide layer. At this time, the gate dielectric structure in the NMOS region of the peripheral region includes only the third oxide layer. 
     In accordance with the first to the third embodiments of the present invention, it is possible to control a threshold voltage value by using a nitride layer capable of trapping charges as a dielectric layer. Thus, even if the design rule is decreased to below approximately 100 nm, a doping concentration of the channel ion implantation region can be decreased, thereby improving a junction leakage current characteristic and a refresh characteristic as simultaneously as obtaining an intended threshold voltage value and a punch through characteristic. 
     The present application contains subject matter related to the Korean patent application No. KR 2004-0019363, filed in the Korean Patent Office on Mar. 22, 2004, the entire contents of which being incorporated herein by reference. 
     While the present invention has been described with respect to certain preferred embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.