Patent Publication Number: US-5892495-A

Title: Scanning circuit and image display apparatus

Description:
FIELD OF THE INVENTION 
     The present invention relates to a scanning circuit suitable for a driving circuit for driving a matrix-type display apparatus, and relates to an image display apparatus incorporating the scanning circuit. 
     BACKGROUND OF THE INVENTION 
     A matrix-type display apparatus includes a plurality of data lines to which picture signals are inputted, and a plurality of scanning lines provided so as to intersect the data lines so that the picture signals thus inputted to the data lines are scanned during each scanning period. At intersections of the data and scanning lines, there are provided pixels which carry out display in accordance with the picture signals supplied by the data lines. The pixels in whole are provided in a matrix form over the screen. Such a matrix-type display apparatus requires scanning signals issued by a scanning circuit so as to sample the inputted picture signals during one scanning period. 
     A conventional scanning circuit is provided with, for example, a shift register 51 and AND circuits AG 51  through AG 55 , as shown in FIG. 8. 
     As shown in FIG. 9, clocked inverters 51a and 51b and an inverter 51c constitute a one-stage circuit, and a plurality of such circuits are cascaded, thereby constituting the shift register 51. The shift register 51 shifts a start pulse supplied by a pulse line PL, sequentially from one stage of the circuits to next, in response to a clock signal supplied by a clock line CKL. The start pulse thus supplied to each circuit is outputted through output lines SOL 51  through SOL 56  provided to the respective stages. 
     To be more concrete, as shown in FIG. 10, the start pulse STP is transferred to the stages one by one in synchronization with the clock signal CK, and is outputted through the output lines SOL 51  through SOL 56  as shift pulses SP 51  through SP 56 , respectively. The shift pulses S 51 , S 52 , S 53 , S 54 , S 55 , and S 56  are outputted in this order at the following timings: The odd-numbered shift pulses SP 51 , SP 53 , and SP 55  are outputted at timings in synchronization with rises of the clock signal CK, while the even-numbered shift pulses SP 52 , SP 54 , and SP 56  are outputted at timings in synchronization with falls of the clock signal CK. 
     Pairs of the output lines SOL 51  through SOL 56 , one pair being composed of neighboring two output lines, are connected to the AND circuits AG 51  through AG 55 , respectively. The two shift pulses are inputted to each of the AND circuits AG 51  through AG 55  through the respective two output lines, and each AND circuit AG conducts an AND operation on the two shift pulses. As a result, scanning signals SS 51  through SS 55  which have respective timings and the same pulse duration as that of the clock signal CK are outputted by the AND circuits AG 51  through AG 55  to output lines OL 51  through OL 55 , respectively. 
     Another conventional scanning circuit is a decoder-type scanning circuit provided with, for example, as shown in FIG. 11(a), address lines AL 61  through AL 63 , address lines IAL 61  through IAL 63 , and AND circuits AG 61  through AG 68  which constitute a decoder. 
     As shown in FIG. 11(b), inputted to the address line AL 61  is a bit signal BS 61  with a cycle of T and a duty factor of 50 percent. Inputted to the address lines AL 62  and AL 63  are a bit signal BS 62  with a cycle of 2T and a bit signal BS 63  with a cycle of 4T, respectively. On the other hand, inputted to the address lines IAL 61  through IAL 63  are bit signals IBS 61  through IBS 63 , respectively, which are obtained by inverting the bit signals BS 61  through BS 63 . 
     The AND circuit AG 61  is connected to the address lines IAL 61  through IAL 63 . The AND circuit AG 62  is connected to the address lines AL 61 , IAL 62 , and IAL 63 . The AND circuit AG 63  is connected to the address lines AL 62 , IAL 61 , and IAL 63 . The AND circuit AG 64  is connected to the address lines AL 61 , AL 62 , and IAL 63 . The AND circuit AG 65  is connected to the address lines AL 63 , IAL 61 , and IAL 62 . The AND circuit AG 66  is connected to the address lines AL 61 , AL 63 , and IAL 62 . The AND circuit AG 67  is connected to the address lines AL 62 , AL 63 , and IAL 61 . The AND circuit AG 68  is connected to the address lines AL 61  through AL 63 . 
     The AND circuits AG 61  through AG 68  are thus supplied with three bit signals each, one combination of three bit signals constituting the address signal never being the same as another, and conduct AND operations on the address signal. As a result, a pulse with a pulse duration of T/2 is supplied, sequentially with a delay of T/2 each time, from the AND circuits AG 61  through AG 68  to output lines OL 61  through OL 68 , respectively. Thus, scanning signals SS 61  through SS 68  shown in FIG. 11(b) are outputted. Combinations of binary values of the respective bits constituting the address signal to which the output timings of the pulse correspond are shown in Table 1 below. 
     
                       TABLE 1
______________________________________
ADDRESS SIGNAL       SCANNING
BS.sub.61
        BS.sub.62     BS.sub.63
                             SIGNAL
______________________________________
0       0             0      SS.sub.61
0       0             1      SS.sub.62
0       1             0      SS.sub.63
0       1             1      SS.sub.64
1       0             0      SS.sub.65
1       0             1      SS.sub.66
1       1             0      SS.sub.67
1       1             1      SS.sub.68
______________________________________
 
    
     The following description will discuss comparison between two data line driving circuits for use in a matrix-type display apparatus, to which the above-described scanning circuits are respectively applied. 
     The clock signal inputted to the shift register and the least significant bit (bit signal BS 61 ) of the address signal inputted to the decoder are determined depending on a dot frequency f d  respectively and have a frequency equivalent to half of the dot frequency f d . Note that the dot frequency f d  is a reciprocal of a period of time required for reading a quantity of data which is equivalent to one pixel of the matrix-type display apparatus. 
     The following description will discuss comparison between the two data line driving circuits about their consumption of power. 
     Given a frequency f, a load capacity C, and a power source voltage V, power consumption P is defined as P=fCV 2 . Here, to simplify the calculation, the load capacity C is restricted to gate input capacities of transistors composing the respective scanning circuits. 
     In the data line driving circuit using the shift register, as shown in FIG. 12, the clocked inverters 51a, disposed on a line through which the start pulse STP is transferred, are equipped with an N-type transistor T n51  and a P-type transistor T p51  each, to which a clock signal CK and an inverted clock signal /CK are respectively inputted. Each stage of the circuits constituting the shift register 51 has two clocked inverters, namely, clocked inverters 51a and 51b. 
     Therefore, given that the transistors T n51  and T p51  have an input capacity C g  each and that the shift register 51 has L outputs, the single clock line CKL has a load capacity C sf  of 2LC g . In addition, the clock line CKL is actually composed of two signal lines for outputting the clock signal CK and the inverted clock signal /CK, respectively. 
     Accordingly, the power consumption P sf  of the shift register 51 is obtained by the following equation: ##EQU1## wherein the frequency of the clock signal is f d  /2, as described above. 
     The data line driving circuit of the decoder type has a decoder actually composed of CMOS circuits. Therefore, instead of the AND circuits AG, either NAND circuits 52 (see FIG. 13) or NOR circuits (not shown), which execute logical operation similar to that by the AND circuits AG. Each NAND circuit 52 has pairs of an N-type transistor T n52  and a P-type transistor T p52 , and the number of the pairs in one NAND circuit 52 corresponds to the number of address lines AL and IAL connected to one NAND circuit 52, that is, the number of inputs thereto. Note that the NAND circuit 52 shown in FIG. 13 is arranged so that two inputs are supplied to the NAND circuit 52. 
     Therefore, in the case where the NAND circuits 52 are connected to address lines AL at a rate of L/2 NAND circuits 52 per one address line AL, the total number of the transistors T n52  and T p52  connected to one address line AL is L. Accordingly, when the respective input capacities of the transistors T n52  and T p52  are defined as C g  each, the load capacity C a  per one address line AL is given as LC g  (=C sf  /2). 
     The frequency of the least significant bit of the address signal is f d  /2, as described above. When the number of the provided address lines AL is m, the bits of the address signal are set so as to have frequencies f d  /2, f d  /2 2 , f d  /2 3 , f d  /2 4 , . . . , f d  /2 m-2 , f d  /2 m-1 , f d  /2 m , from the least significant bit to the most significant bit. Furthermore, when the data line driving circuit has m address lines AL, it also has the same number m of address lines IAL to which the inverted clock signals are inputted. Therefore, the total number of the address lines AL and IAL is 2m. 
     Therefore, the power consumption P a  of the decoder is obtained by the following equation: ##EQU2## Thus, the power consumption of the data line driving circuit of the decoder type is substantially the same as that of the data line driving circuit of the shift register type. 
     Comparison is made between the two data line driving circuits about scanning speed, in the following description. 
     In the case with the data line driving circuit of the shift register type, a signal is subsequently transferred from one stage to another in the shift register 51, wherein an input signal to one stage is supplied by its previous stage. Therefore, the input signal has been affected by delay or rounding of the waveform which has been caused in the previous stages. In addition, an operational speed is affected by respective driving capacities of the individual transistors, the output signal from the previous stages, and input capacities of the following stages. Furthermore, a period while the P-type transistor and the N-type transistor in each inverter are simultaneously in the ON state is prolonged due to the rounding of the signal waveform. Such phenomena cause a current to increase, thereby increase the power consumption. 
     In the data line driving circuit of the decoder type, the address signal is directly inputted from the respective address lines AL to the corresponding logical circuits in the decoder. Therefore, the address signal is not affected by other circuits. Furthermore, whereas each stage of the shift register 51 is connected to two circuit systems, namely, the following stage and an output buffer (not shown), each logical circuit of the decoder is connected only to a buffer so as to supply an output thereto. Accordingly, one logical circuit of the decoder has an input load of a following stage, which is only half of that of one stage of the shift register, thereby having a higher operating speed. 
     Since the input load (capacity) of the following stage for the decoder is half of that of the shift register 51 as mentioned above, the decoder has less rounding of the signal waveform compared with the shift register. Accordingly, the current of the decoder is smaller than that of the shift register 51. Therefore, the decoder is superior in the power consumption as well. 
     In addition, the data line driving circuit of the decoder type is superior in the yield, as described below. 
     The data line driving circuit of the shift register type presents a problem pointed out in the Japanese Laid-open Patent Publication 7-191636/1995. Each stage of a shift register has 10 transistors, and each AND circuit thereof has 6 transistors, for example. Therefore, one data line driving circuit is composed of a large number of transistors. This leads to a low non-defective ratio of the data line driving circuit of the shift register type. In addition, in the case where the data line driving circuit and a display panel are integrally provided by using polycrystalline silicon, this leads to a problem that a ratio of non-defective operation of transistors further decreases due to dispersion in characteristics, electrostatic breakdown, etc. 
     In contrast, since the data line driving circuit of the decoder type has less transistors per one output, as described in the foregoing publication, it has a non-defective ratio higher than that of the data line driving circuit of the shift register type. 
     As has been described, the data line driving circuit of the decoder type is superior to the data line driving circuit of the shift register type in practical application. 
     Regarding the scanning circuit of the decoder type described above, an output is selected according to the combinations of the binary values of the bits constituting the address signal, as shown in FIG. 11(b). When the address signal carries, sometimes plural bits among those constituting the address signal are simultaneously switched, for example, from &#34;011&#34; to &#34;100&#34;, as shown in Table 1. Such a switching tends to cause phase shift due to delays of the address signal or the like, thereby resulting in glitches. 
     In the case where the scanning circuit of the decoder type is applied to a data line driving circuit for use in a matrix-type display apparatus, frequencies of the address signal to be inputted to the decoder are determined depending on a dot frequency f d  in accordance with the standard of the image display apparatus. For example, concerning a VGA (video graphics array)-standard image display apparatus, a frequency f a  of a least significant bit of the address signal to be supplied to the decoder is obtained by the following equation, in consideration of a blanking period: ##EQU3## wherein H represents the number of dots in a horizontal direction, and V represents the number of dots in a vertical direction. 
     Models of image display apparatuses have recently been diversified, while there has been an increasing demand for higher display quality of the image display apparatuses. To cope with such a demand, application of higher frequencies to driving circuits for use in data line driving circuits has been attempted. For example, in the case with a matrix-type display apparatus of an XGA (extended graphics array) standard, with the least significant bit of the address signal to be supplied to a decoder provided in a driving circuit is required to have a frequency of around 40 MHz. Since the power consumption is given as P=fCV 2 , as described above, it increases in proportion to the frequency. Thus, the frequency greatly affects the power consumption. 
     On the other hand, there has also been an increasing demand for a matrix-type display apparatus consuming less power, and technical innovation has been promoted so as to meet the demand. 
     The address signal inputted to the decoder changes in the highest frequencies in those used in the scanning circuit of the image display apparatus. Furthermore, as described above, since the address lines are connected to the logical circuits at a rate of L/2 logical circuits per one address line, the address lines have a great input load capacity each. Power consumption due to the input load capacity accounts for a considerable part of the total power consumption of the data line driving circuit. Therefore, reduction in the power consumption by input members for inputting to the decoder is an important task so as to achieve reduction in the power consumption of the data line driving circuit. 
     Moreover, the following problem has been presented in the case where a display panel and a driving circuit are integrally formed by using polycrystalline silicon thin film transistors: for example, as mentioned in the Japanese Examined Patent Publication No. 5-22917/1993, a mobility of carriers in the silicon thin film is a fraction of carriers in silicon monocrystals. Furthermore, since refinement of the apparatus and improvement of process for such refined apparatus has been delaying, a limit of an operational speed of the polycrystalline silicon film transistor is lower than one several tenth of that of a conventional integrated circuit. 
     A conventional image display apparatus provided with a driver which is realized by an integrated circuit for an exclusive use as a driver does not have such a problem as described above, thereby being driven by a single driver system. In contrast, the scanning circuit exhibits a low operational speed, in the case where the foregoing scanning circuit is adapted to a data line driving circuit (driver) which is built in an active matrix substrate in a matrix-type image display apparatus with a high resolution. Therefore, the data line driving circuit is required to have a plurality of driver systems, so as to solve the problem of the low operational speed. 
     This stems from that the transistors are affected by variations of characteristics of the circuit, in addition to that the individual transistors each have a low driving capacity. Therefore, a scanning circuit which can be operated at lower frequencies has been sought for. 
     SUMMARY OF THE INVENTION 
     The object of the present invention is to provide a decoder-type scanning circuit which can optimize an address signal thereby avoiding a phase shift occurring to an output signal when the address signal carries. Another object of the present invention is to provided a decoder-type scanning circuit realized in a simple circuit arrangement which operates at low frequencies thereby consuming less power. 
     To achieve the above objects, a scanning circuit of the present invention comprises: 
     m address lines for respectively supplying bit signals, each bit signal being indicative of each bit of an address signal; and 
     a decoder for conducting logical operations on the address signal having m bits so as to sequentially output L (L≦2 m ) scanning signals, 
     wherein each bit of the address signal is associated with the address lines so that only one bit of the address signal is switched each time when the address signal carries. 
     With the described arrangement of the scanning circuit, only one bit of the address signal is switched each time when the address signal carries, thereby causing substantially no phase shift resulting from delays of the address signal or the like. Therefore, it is possible to prevent glitches. 
     The foregoing scanning circuit is preferably arranged so as to satisfy the following condition (a) or (b). 
     (a) The bit signal indicative of the least significant bit of the address signal has a frequency of 1/4 of a dot frequency, the dot frequency being a reciprocal of a period of time required for reading in data corresponding to each pixel, and the bit signals, indicative of the two bits at the high end respectively, have a same frequency and a phase difference of 90° from one another. This is one of the typical arrangements of the address signal which ensure that the condition on the association of the respective bits of the address signal with the address lines is satisfied. 
     With the described arrangement, since the frequency of the bit signal indicative of the least significant bit of the address signal is set to 1/4 of the dot frequency, the frequencies for the address signal, that is, the frequencies at which the scanning circuit operates are lowered. When power consumption of the foregoing scanning circuit is calculated in the same manner as the case with the above-described conventional decoder-type scanning circuit, the result is drastically lower than that of the conventional case. This shows that the foregoing arrangement ensures the reduction of the power consumption of the scanning circuit. 
     (b) The foregoing scanning circuit further comprises first and second sampling circuits for respectively sampling first and second picture signals constituting an original picture signal in response to the scanning signals supplied from the decoder, one pair of the first and second sampling circuits being provided per one scanning signal output line. 
     With this arrangement, in the scanning circuit wherein the original picture signal is divided and sampled, a period of time required for one sampling operation by the first and second sampling circuit is longer than a period of time required for one sampling operation in a scanning circuit wherein the whole original picture signal is sampled. Therefore, frequencies for the scanning signals can be lowered in the scanning circuit in accordance with the foregoing arrangement, thereby resulting in that the frequencies at which the scanning circuit operates can be lowered. 
     Moreover, the scanning circuit arranged so as to satisfy the condition (a) or (b) is preferably composed of thin film transistors. To be more specific, in the scanning circuit having the first and second sampling circuits, the decoder and the first and second sampling circuits are composed of the thin film transistors. In the scanning circuit without the first and second sampling circuits, the decoder is composed of the thin film transistors. Such a scanning circuit, having an address signal with lower frequencies as described above, can have requisite operating characteristics even though being realized by thin film transistors having operating characteristics inferior to those of transistors on a monocrystalline silicon substrate, for example, realized by polycrystalline silicon thin film transistors. 
     So as to achieve the above-described object, an image display apparatus of the present invention comprises: 
     pixel electrodes for supplying a picture signal to pixels provided in a matrix form; 
     a plurality of data lines for supplying the picture signal to the pixel electrodes; 
     a plurality of scanning lines orthogonally crossing the data lines so as to sequentially select the pixel electrodes to be supplied with the picture signal; 
     a data line driving circuit for outputting the picture signal to the data lines; and 
     a scanning line driving circuit for outputting a selection signal, 
     wherein at least either the data line driving circuit or the scanning line driving circuit includes a scanning circuit, the scanning circuit including: 
     m address lines for respectively supplying bit signals, each bit signal being indicative of each bit of an address signal; and 
     a decoder for conducting logical operations on the address signal having m bits so as to sequentially output L scanning signals (L≦2 m ), 
     each bit of the address signal being associated with the address lines so that only one bit of the address signal is switched each time when the address signal carries. 
     The image display apparatus thus arranged can execute stable display operations, since it is possible to prevent glitches in the scanning circuit from occurring. 
     The image display apparatus also can achieve a decrease in power consumption, by installing the scanning circuit which satisfies the above-mentioned condition (a) or (b) thereby having lower frequencies at which the scanning circuit operates. 
     Another image display apparatus of the present invention comprises: 
     pixel electrodes for supplying a picture signal to pixels provided in a matrix form; 
     a plurality of data lines for supplying the picture signal to the pixel electrodes; 
     a plurality of scanning lines orthogonally crossing the data lines so as to sequentially select the pixel electrodes to be supplied with the picture signal; 
     a data line driving circuit for outputting the picture signal to the data lines, the data line driving circuit including a scanning circuit, the scanning circuit including m address lines and a decoder, the address lines respectively supplying bit signals, each bit signal being indicative of each bit of an address signal, a decoder conducting logical operations on the address signal having m bits so as to sequentially output L (L≦2 m ) scanning signals, the decoder being composed of thin film transistors, each bit of the address signal being associated with the address lines so that only one bit of the address signal is switched each time when the address signal carries; 
     a scanning line driving circuit for outputting a selection signal to the scanning line; and 
     switching elements for outputting the picture signal supplied from the data lines to the pixel electrodes in accordance with the selection signals supplied to the scanning lines; 
     wherein the pixel electrodes, the switching elements, and the data line driving circuit are provided on either an amorphous silicon thin film, a polycrystalline silicon thin film, or a monocrystalline silicon thin film, formed on an insulating substrate. 
     In the image display apparatus thus arranged, the pixels and the driving circuits are integrally provided on the insulating substrate. On such an insulating substrate, thin film transistors provided on the amorphous silicon thin film, the polycrystalline silicon thin film, or the monocrystalline silicon thin film have operating characteristics inferior to those of transistors provided on a monocrystalline silicon substrate. However, since the data line driving circuit incorporates the above-described scanning circuit which has low operational frequencies, the data line driving circuit can be composed of thin film transistors having inferior characteristics. Therefore, an image display apparatus provided with an active matrix substrate of a driver built-in type, which is composed of such thin film transistors, can be easily obtained. 
    
    
     For fuller understanding of the nature and advantages of the invention, reference should be made to the ensuing detailed description taken in conjunction with the accompanying drawings. 
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1(a) is a circuit diagram illustrating an arrangement of principal parts of a scanning circuit in accordance with the first embodiment of the present invention. 
     FIG. 1(b) is a timing chart illustrating operations of the scanning circuit. 
     FIG. 2(a) is a block diagram illustrating an arrangement of principal parts of an active matrix-type liquid crystal display apparatus incorporating the scanning circuit. 
     FIG. 2(b) is a circuit diagram illustrating a detailed arrangement of a pixel of the active matrix-type liquid crystal display apparatus. 
     FIG. 3 is a circuit diagram illustrating an arrangement of principal parts of another scanning circuit in accordance with the first embodiment of the present invention. 
     FIG. 4(a) is a circuit diagram illustrating an arrangement of principal parts of still another scanning circuit in accordance with the first embodiment of the present invention. 
     FIG. 4(b) is a timing chart illustrating operations of the scanning circuit shown in FIG. 4(a) 
     FIG. 5 is a circuit diagram illustrating an arrangement of an AND circuit with 10 inputs provided in the scanning circuit of FIG. 1(a) and the scanning circuit of FIG. 4(a). 
     FIG. 6 is a circuit diagram illustrating an arrangement of principal parts of a scanning circuit in accordance with the second embodiment of the present invention. 
     FIG. 7 is a waveform chart illustrating waveforms of picture signals to be inputted to picture lines of the scanning circuit shown in FIG. 6. 
     FIG. 8 is a circuit diagram illustrating an arrangement of principal parts of a conventional shift register-type scanning circuit. 
     FIG. 9 is a circuit diagram illustrating an arrangement of a shift register of the scanning circuit shown in FIG. 8. 
     FIG. 10 is a timing chart illustrating operations of the scanning circuit shown in FIG. 8. 
     FIG. 11(a) is a circuit diagram illustrating an arrangement of principal parts of a conventional decoder-type scanning circuit. 
     FIG. 11(b) is a timing chart illustrating operations of the scanning circuit shown in FIG. 11(a). 
     FIG. 12 is a circuit diagram illustrating an arrangement of a clocked inverter in the shift register shown in FIG. 9. 
     FIG. 13 is a circuit diagram illustrating an arrangement of an NAND circuit composed of CMOS circuits, which is provided in the scanning circuit shown in FIG. 11(a). 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     First Embodiment 
     The following description will discuss one embodiment of the present invention, with reference to FIGS. 1 through 6. 
     A matrix-type image display apparatus in accordance with the present embodiment is an active-matrix type liquid crystal display apparatus, which has, as shown in FIG. 2(a), a liquid crystal panel 1 provided with a plurality of data lines DL and a plurality of scanning lines SL, a data line driving circuit 2, a scanning line driving circuit 3, and an address signal generating circuit 4. The liquid crystal panel 1 is composed of two glass substrates stuck to each other and liquid crystal filled therebetween. 
     On the liquid crystal panel 1, the data lines DL and the scanning lines SL are orthogonally provided. Each area closed by two neighboring data lines DL and two neighboring scanning lines SL has a pixel 5. Therefore, the pixels 5 are provided in a matrix form in whole. 
     As shown in FIG. 2(b), each pixel 5 is composed of a switching element SW which is a field effect transistor (thin film transistor), and a pixel capacitor C P . The pixel capacitor C P  has a liquid crystal capacitor C L , and a supplemental capacitor C S  which is used when necessary. 
     The data line DL and an electrode of the pixel capacitor C P , that is, a pixel electrode E P , are connected through a source and a drain of the switching element SW. A gate of the switching element SW is connected to the scanning line SL, and the other electrode of the pixel capacitor C P  is a common electrode which is shared by all the pixels 5. Transmittance or reflectance of the liquid crystal are modulated in accordance with voltages applied to the respective liquid crystal capacitors C L  so as to carry out display. 
     The data line driving circuit 2 sequentially selects picture signals inputted thereto during a period of a predetermined duration and supplies the picture signals to the data lines DL, while the data line driving circuit 2 has a scanning circuit which will be described later. The scanning line driving circuit 3 sequentially selects the scanning lines SL, and controls the closing and opening of the respective switching elements SW in the pixels 5. 
     The switching element SW in the active matrix-type liquid crystal display apparatus of the present embodiment is a thin film transistor. The thin film transistors constituting the switching elements SW are provided on either an amorphous silicon thin film, a polycrystalline silicon thin film, or a monocrystalline silicon thin film, formed on a glass substrate of the liquid crystal panel 1. The data line driving circuit 2 and the scanning line driving circuit 3 are monolithically provided, together with the switching elements SW and the pixel electrodes E P , on the same glass substrate. The data line driving circuit 2 and the scanning line driving circuit 3 are also composed of thin film transistors similar to those for the switching elements SW. 
     The following description will discuss the scanning circuit provided in the data line driving circuit 2. 
     The scanning circuit is provided with m address lines AL l  through AL m  and m address lines IAL l  through IAL m , and L AND circuits AG 1  through AG L  (L≦2 m ) constituting a decoder 6. 
     Note that m=3 and L=8 in the scanning circuit of the present embodiment, so as to simplify explanation. In addition, in the following description, the address lines AL 1  through AL 3  and the address lines IAL 1  through IAL 3  are referred to simply as address lines AL and address lines IAL, respectively, unless individual lines are referred to. Likewise, the bit signals BS 1  through BS 3  and IBS 1  through IBS 3  are referred to as bit signals BS and IBS. 
     As shown in FIG. 1(b), supplied to the address line AL 1  is the bit signal BS 1  which has a constant cycle of T and a duty factor of 50 percent. The bit signal BS 1  is the least significant bit of a signal supplied to the decoder 6, and has a frequency of 1/4 of the dot frequency. The bit signals BS and IBS are issued by the address signal generating circuit 4 shown in FIG. 2(a). 
     On the other hand, supplied to the address line AL 2  is the bit signals BS 2  which has a cycle of 2T and has a phase difference of 90° to the bit signal BS 1 . Supplied to the address line AL 3  is the bit signal BS 3  which has a cycle of 2T and has a phase difference of 90° to the bit signal BS 2 . 
     Furthermore, supplied to the address lines IAL 1  through IAL 3  are the bit signals IBS 1  through IBS 3 , respectively, which are signals obtained by inverting the bit signals BS 1  through BS 3 . An address signal has bits which respectively correspond to bit signals BS 1  through BS 3 . The bit signals BS 1  and BS 3  are the least and most significant bits, respectively, in the address signal. 
     The AND circuit AG 1  is connected to the address lines IAL 1  through IAL 3 .The AND circuit AG 2  is connected to the address lines AL 1 , IAL 2 , and IAL 3 . The AND circuit AG 3  is connected to the address lines AL 1 , AL 2 , and IAL 3 . The AND circuit AG 4  is connected to the address lines AL 2 , IAL 1 , and IAL 3 . The AND circuit AG 5  is connected to the address lines AL 2 , AL 3 , and IAL 1 . The AND circuit AG 6  is connected to the address lines AL 1  through AL 3 . The AND circuit AG 7  is connected to the address lines AL 1 , AL 3 , and IAL 2 . The AND circuit AG 8  is connected to the address lines AL 3 , IAL 1 , and IAL 2 . 
     The AND circuits AG i  through AG 8  are thus supplied with three bit signals each, which are selected among the bit signals BS and IBS and the combination of which is not same as any other, and each circuit conducts an AND operation on the inputted three bit signals. The respective AND circuits AG i  through AG 8  are realized by CMOS (complementary metal-oxide semiconductor) circuits. To be more concrete, they are composed of NAND circuits and inverters. Alternatively, NOR circuits composed of CMOS may substitute for AND circuits AG i  through AG 8 . 
     In the scanning circuit arranged as above, the bit signals BS and IBS of FIG. 1(b) are supplied to the AND circuits AG i  through AG 8  through the address lines AL and IAL. Then, as shown in FIG. 1(b), scanning signals SS 1  through SS 8  are outputted from the AND circuits AG i  through AG 8  to the output lines OL 1  through OL 8 . The scanning signals SS 1  through SS 8  are pulses with a pulse duration of T/4 each, which sequentially rise with a delay of the pulse duration T/4 each, so that the pulses do not overlap one another. 
     The bit signal BS 1  (the least significant bit) has a frequency of 1/4 of the dot frequency f d  at which the pulse is outputted as described above, that is, a frequency f d  /4. The bit signal BS 2  (the second bit) and the bit signal BS 3  (the most significant bit) respectively have a frequency f d  /8, which is equivalent to 1/2 of the frequency of the bit signal BS 1 , and have a phase difference of 90° one another. 
     Table 2 below shows combinations of the binary values of the bits constituting the address signal, which correspond to the respective scanning signals SS 1  through SS 8 . It is arranged that only one bit signal is switched, each time the address signal carries. 
     
                       TABLE 2
______________________________________
ADDRESS SIGNAL       SCANNING
BS.sub.3
        BS.sub.2      BS.sub.1
                             SIGNAL
______________________________________
0       0             0      SS.sub.1
0       0             1      SS.sub.2
0       1             1      SS.sub.3
0       1             0      SS.sub.4
1       1             0      SS.sub.5
1       1             1      SS.sub.6
1       0             1      SS.sub.7
1       0             0      SS.sub.8
______________________________________
 
    
     The following description will discuss a scanning circuit in the case where m=4 and L=6. 
     Table 3 shows combinations of binary values of bits constituting an address signal in the above case, the combinations corresponding to respective scanning signals, though no concrete circuit arrangement is shown. In this case, 16 scanning signals SS 1  through SS 16  are outputted in accordance with the address signal having 4 bits (bit signals BS 1  through BS 4 ). In this scanning circuit it also, it is arranged that only one bit is switched each time when the address signal carries. 
     
         ______________________________________
ADDRESS SIGNAL         SCANNING
BS.sub.4 BS.sub.3
                BS.sub.2    BS.sub.1
                                 SIGNAL
______________________________________
0        0      0           0    SS.sub.1
0        0      0           1    SS.sub.2
0        0      1           1    SS.sub.3
0        0      1           0    SS.sub.4
0        1      1           0    SS.sub.5
0        1      1           1    SS.sub.6
0        1      0           1    SS.sub.7
0        1      0           0    SS.sub.8
1        1      0           0    SS.sub.9
1        1      0           1    .sub. SS.sub.10
1        1      1           1    .sub. SS.sub.11
1        1      1           0    .sub. SS.sub.12
1        0      1           0    .sub. SS.sub.13
1        0      1           1    .sub. SS.sub.14
1        0      0           1    .sub. SS.sub.15
1        0      0           0    .sub. SS.sub.16
______________________________________
 
    
     The bit signal BS 1  (the least significant bit) has a frequency of 1/4 of the dot frequency f d , namely, a frequency f d  /4. The bit signal BS 2  (the second bit) has a frequency f d  /8, which is equivalent to 1/2 of the frequency of the bit signal BS 1 . The bit signal BS 3  (the third bit) and the bit signal BS 4  (the most significant bit) have a frequency f d  /16 each, which is equivalent to 1/4 of the frequency of the bit signal BS 1 , and have a phase difference of 90° one another. 
     Thus, irrelevant to what number the &#34;m&#34; takes, the scanning circuit is arranged as described below: 
     (1) only one bit is switched each time when the address signal carries; 
     (2) the least significant bit has a frequency of 1/4 of the dot frequency; and 
     (3) the two bits at the high end have the same frequency, and have a phase difference of 90° one another. 
     With the arrangement described in the item (1), glitches can be prevented, since it no longer happens that plural bits in those constituting the address signal are switched at once when the address signal carries. This ensures that the scanning circuit stably operates. With the arrangements described in the items (2) and (3), reduction of the power consumption can be achieved as described below. 
     In the case where the number of the address lines is m, bits (bit signals) of the address signal from the least significant bit to the most significant bit have frequencies f d  /2 2 , f d  /2 3 , f d  /2 4 . . . , f d  /2 m-1 , f d  /2 m , and f d  /2 m , respectively. 
     Since (1) the load capacity C a2  per one address line of the address lines AL and IAL is the same as the load capacity C a  per one address line of a conventional scanning circuit of the decoder type and (2) the scanning circuit has m address lines AL and the same number of the address lines IAL, the power consumption P a2  of the scanning circuit is given as: ##EQU4## Namely, the scanning circuit of the present embodiment consumes power equivalent to half of that consumed by the conventional scanning circuit. 
     Note that the decoder 6 in the scanning circuit of the present embodiment, which is composed of the AND circuits AG i  through AG 8 , may be a dynamic type as shown in FIG. 3, instead of being realized by the foregoing CMOS circuits. Each of AND circuits AG i  through AG 8  of the dynamic-type decoder 6 is composed of a P-type transistor T p  and three transistors T n1  through T n3  which are connected in series. The P-type transistor T p  is for resetting, while the transistors T n1  through T n3  are respectively connected to the address lines AL and IAL. 
     In each AND circuit AG, the transistor T n1  and the transistor T p  are connected to each other at a node, and the node is connected to a gate of a transistor T p  of an AND circuit AG of the previous stage while the node is also connected to a buffer BF. Note that the node of the AND circuit of the first stage, namely, AND circuit AG i , is connected to the gate of the transistor T p  of the AND circuit of the last stage, namely, the AND circuit AG 8 . 
     The decoder 6 arranged as described above operates as follows. 
     An AND circuit AG i  of a certain stage outputs a &#34;LOW&#34; (ON) signal, when it is supplied with an address signal having a combination of bit values which causes all the transistors T n1  through T n3  to become in the ON state. Then, an AND circuit AG i+1  of the following stage outputs a &#34;LOW&#34; (ON) signal, due to a change occurring to the bit value combination in the address signal. In this state, one of the transistors T n1  through T n3  of the AND circuit AG i  becomes in the OFF state, thereby causing the AND circuit AG i  composed of the transistors T n1  through T n3  to become in the OFF state. 
     Since the AND circuit AG i+1  outputs a &#34;LOW&#34; (ON) signal, the transistor T p  of the AND circuit AG i  is supplied with the &#34;LOW&#34; (ON) signal and becomes in the ON state. This causes the AND circuit AG i  to output a &#34;HIGH&#34; (OFF) signal. 
     Thus, the decoder 6 of the dynamic type can execute a scanning operation as the decoder of the CMOS type does. Furthermore, whereas one address line is connected to the respective gates of P-type and N-type transistors in the decoder of the CMOS type, one address line is connected only to the respective gates of the N-type transistors T n1  through T n3  in the decoder of the dynamic type. Therefore, each AND circuit of the decoder 6 of the dynamic type has an input gate capacity of 1/2 of that of the decoder of the CMOS type. As a result, the decoder of the dynamic type consumes 1/2 power. 
     In the scanning circuit in accordance with the present embodiment, the address lines IAL may be omitted, as shown in FIG. 4(a). In this case, respective signals supplied to the three address lines AL 1  through AL 3  and outputted to the output lines OL 1  through OL 8  have waveforms shown in FIG. 4(b). In such a scanning circuit wherein only three address lines AL 1  through AL 3  are provided, AND circuits AG i1  through AG i8  are arranged so as to invert inputs where necessary, in order to obtain the output signals described above. 
     In the scanning circuit shown in FIG. 3 whose decoder 6 is a dynamic type, the address signal is inputted only to the N-type transistors T n1  through T n3 . Therefore, the address lines AL and IAL each have a load capacity C a3  equivalent to 1/2 (C a  /2) of that of the conventional scanning circuit. Therefore, the total power consumption P a3  is given as: 
     
         P.sub.a3 =f.sub.d ×C.sub.a3 ×V.sup.2 =f.sub.d C.sub.a V.sup.2 /2=P.sub.a /4 
    
     It is found that the scanning circuit in this case consumes power equivalent to 1/4 of that of the conventional scanning circuit. 
     On the other hand, in the scanning circuit shown in FIG. 4(a), the address lines AL 1  through AL 3  each are connected to the transistors in each of the AND circuits AG i1  through AG i8 , so as to correspond to the L outputs. Therefore, the load capacity C a4  of each address line is two times (2C a ) greater than that of the conventional scanning circuit. However, since address lines IAL are unnecessary, the power consumption P a4  as a whole is given as: ##EQU5## Thus, the foregoing scanning circuit has a power consumption equivalent to 1/2 of that of the conventional scanning circuit. 
     Furthermore, in the case with a VGA-standard image display apparatus having a data line driving circuit 2 with 640 outputs (therefore, L=640), since m=10, 10 transistors connected in series need to be provided in each AND circuit AG. A decoder composed of such AND circuits AG tends to present a problem that an operational speed lowers. However, by arranging the AND circuits AG as shown in FIG. 5, the problem is solved. 
     According to the arrangement shown in FIG. 5, 5 inputs are processed by a pair of NAND circuits 11 and 12, and respective outputs of the NAND circuits 11 and 12 are supplied to an NOR circuit 13. An output of the NOR circuit 13, and an output of another group of a pair of NAND circuits 11 and 12 and an NOR circuit 13 are supplied to an NAND circuit 14. 
     Incidentally, in the case where the scanning circuit in accordance with the present embodiment is adapted to a data line driving circuit 2 of an image display apparatus wherein a liquid crystal panel 1 and the data line driving circuit 2 are integrally provided by using polycrystalline silicon thin film transistors, frequencies of the address signal can be reduced to 1/2 of the conventional scanning circuit. Therefore, power consumption of the data line driving circuit 2 can be decreased. 
     Note that though the active matrix-type liquid crystal display apparatus has been taken as an example in the present embodiment, the image display apparatus of the present invention may be any other type, provided that the scanning circuit of the present invention can be adapted to the image display apparatus. 
     Second Embodiment 
     The following description will discuss another embodiment of the present invention with reference to FIGS. 6 and 7. The members having the same structure (function) as those in the above-mentioned embodiment will be designated by the same reference numerals and their description will be omitted. 
     A scanning circuit in accordance with the present embodiment is provided with a decoder unit 21, picture lines VL 1  and VL 2 , and sampling circuits S 1  through S 8 , as shown in FIG. 6. The decoder unit 21 has any of the arrangements of FIGS. 1(a), 3, and 4 of the first embodiment. The decoder unit 21 in accordance with the present embodiment has four output lines OL 1  through OL 4 . 
     The sampling circuits S 1  and S 2 , the sampling circuits S 3  and S 4 , the sampling circuits S 5  and S 6 , and the sampling circuits S 7  and S 8  are connected to the output lines OL 1  through OL 4  of the decoder unit 21, respectively. In addition, the odd-number&#39;th sampling circuits S 1 , S 3 , S 5 , and S 7  are connected to the picture line VL 1 , while the even-numbered sampling circuits S 2 , S 4 , S 6 , and S 8  are connected to the picture line VL 2 . 
     To the picture lines VL 1  and VL 2 , division picture signals obtained by dividing an original picture signal are inputted. In the case where the original picture signal has, for example, a staircase waveform as shown in FIG. 7, signals with respective waveforms W 1  and W 2  are produced from the original picture signal. In the waveform W 1 , a certain level of the original picture signal is maintained for a period of time twice longer than that of the original picture signal, while in the waveform W 2 , a level of the original picture signal which is one level upper than the foregoing level is maintained for a period of time twice longer than that of the original picture signal. Therefore, the waveforms W 1  and W 2  alternately have the levels of the original picture signal, thereby the waveform W 1  having every other level and the waveform W 2  having the others, and maintain them for the periods respectively twice longer than those of the original picture signal. The signals with the waveforms W 1  and W 2  thus arranged are inputted to the picture lines VL 1  and VL 2 , respectively. 
     In the scanning circuit thus arranged, the decoder 21 are supplied with an address signal which has the same combinations of the binary values of the bits as those of the address signal of the scanning circuit in accordance with the first embodiment and whose least significant bit has a frequency (f d  /8) equivalent to half of that of the address signal of the first embodiment (see Table 2, and FIGS. 1(b) or 4(b)). Therefore, a signal (scanning signal) which has a frequency equivalent to half of the dot frequency is supplied to the output lines OL 1  through OL 4  of the decoder 21. In accordance with the scanning signal, one pair is selected in the pairs of the sampling circuits S 1  and S 2 , the sampling circuits S 3  and S 4 , the sampling circuits S 5  and S 6 , and the sampling circuits S 7  and S 8 . Then, the picture signals from the picture lines VL 1  and VL 2  are supplied through a pair of the selected sampling circuits S to two data lines DL connected to the sampling circuits S, respectively. 
     To be more concrete, when the scanning signal is outputted from the output line OL 1 , the sampling circuits S 1  and S 2  are selected. Therefore, the picture signal from the picture line VL 1  is sampled by the sampling circuit S 1 , and is outputted to the data line DL 1 , while the picture signal from the picture line VL 2  is sampled by the sampling circuit S 2 , and is outputted to the data line DL 2 . 
     Likewise, when the scanning signal is sequentially outputted from the output lines OL 2  through OL 4 , the sampling circuits S 3  and S 4 , the sampling circuits S 5  and S 6 , and the sampling circuits S 7  and S 8  are respectively selected. As a result, the picture signal from the picture line VL 1  is outputted to the data line DL 3 , DL 5 , and DL 7 , while the picture signal from the picture line VL 2  is outputted to the data line DL 4 , DL 6 , and DL 8 . 
     Thus, since the scanning circuit of the present embodiment has the data lines DL at a rate of two data lines DL per one output line tL of the decoder unit 21, the address signal to be supplied to the decoder 21 has a frequency of 1/2 of that of the scanning signal wherein the output lines OL and the data lines DL connected thereto are 1:1. Therefore, the address signal for driving the data lines DL has the highest frequency of 1/8 of the dot frequency. With this arrangement, it is possible to lower the driving frequencies without decreasing the number of pixels in the image display apparatus. 
     Note that here it is set that th e decoder unit 21 has four outputs and the scanning circuit has eight outputs, but the respective numbers of their outputs are not restricted as such. Provided that the decoder unit 21 has L/2 outputs when the number of the outputs of the scanning circuit is L, the &#34;L&#34; may take any number. 
     In the case where the address signal with m combinations of bit values (m: the number of the address lines) is supplied to the scanning circuit of the present embodiment, the bits (bit signals) of the address signal respectively have frequencies of f d  /2 3 , f d  /2 4 , f d  /2 5 , . . . , f d  /2 m , f d  /2 m+1 , and f d  /2 m+1 , from the least significant bit to the most significant bit. Here also, the two bits at the high end have a same frequency and a phase difference of 90° one another. 
     A load capacity C b  per one address line is the same as that of the conventional scanning circuit of the decoder type, namely, C a . The scanning circuit of the present embodiment, as the conventional scanning circuit, has m address lines, and the same number of inverting address lines. Therefore, power consumption of the scanning circuit P b  is given as: ##EQU6## Therefore, the scanning circuit of the present embodiment consumes power equivalent to 1/4 of that of the conventional scanning circuit. In the case where the decoder of the dynamic type (see FIG. 3) of the first embodiment is adapted to the scanning circuit of the present embodiment, the power consumption falls fifty percent. Therefore, the power consumption of the scanning circuit in accordance with the foregoing arrangement becomes 1/8 of that of the conventional scanning circuit. 
     Incidentally, in the case where the scanning circuit in accordance with the present embodiment is adapted to a data line driving circuit (see FIG. 2(a)) of an image display apparatus wherein a liquid crystal panel and the data line driving circuit are integrally provided by using polycrystalline silicon thin film transistors, frequencies of the address signal can also be reduced to 1/4 of those of the conventional scanning circuit. Therefore, power consumption of the data line driving circuit can be decreased. According to this arrangement, the sampling circuits S 1  through S 8  are also composed of polycrystalline silicon thin film transistors. 
     Note that the number of the divisions of the picture signal, that is, the number of the data lines DL connected to the output lines OL of the decoder unit 21, is not restricted to 2 in the case of the scanning circuit of the present embodiment, but it may be 3, or 4. 
     The arrangements wherein the scanning circuit is adapted to the data line driving circuit of the matrix-type image display apparatus have been taken as examples for the first and second embodiments of the present invention. But, the present invention is not restricted to these arrangements. The present invention may have an arrangement wherein any of the scanning circuits is adapted to a scanning line driving circuit, or another arrangement wherein it is adapted to another circuit. 
     The invention being thus described, it will be obvious that the same may be varied in many ways. Such variations are not to be regarded as a departure from the spirit and scope of the invention, and all such modifications as would be obvious to one skilled in the art are intended to be included within the scope of the following claims.