Patent Publication Number: US-2023138949-A1

Title: Array substrate and display apparatus

Description:
TECHNICAL FIELD 
     The present invention relates to display technology, more particularly, to an array substrate and a display apparatus. 
     BACKGROUND 
     Organic Light Emitting Diode (OLED) display is one of the hotspots in the field of flat panel display research today. Unlike Thin Film Transistor-Liquid Crystal Display (TFT-LCD), which uses a stable voltage to control brightness, OLED is driven by a driving current required to be kept constant to control illumination. The OLED display panel includes a plurality of pixel units configured with pixel-driving circuits arranged in multiple rows and columns. Each pixel-driving circuit includes a driving transistor having a gate terminal connected to one gate line per row and a drain terminal connected to one data line per column. When the row in which the pixel unit is gated is turned on, the switching transistor connected to the driving transistor is turned on, and the data voltage is applied from the data line to the driving transistor via the switching transistor, so that the diving transistor outputs a current corresponding to the data voltage to an OLED device. The OLED device is driven to emit light of a corresponding brightness. 
     SUMMARY 
     In one aspect, the present disclosure provides an array substrate, comprising a base substrate; a semiconductor material layer on the base substrate; and a plurality of voltage supply lines on a side of the semiconductor material layer away from the base substrate; wherein, in a respective subpixel, the semiconductor material layer comprises an active layer of a third transistor, an active layer of a fifth transistor, an active layer of a driving transistor, and a third node portion that is connected to the active layer of the third transistor, the active layer of the fifth transistor, and the active layer of the driving transistor in the respective subpixel, and at least 30% of an orthographic projection of the third node portion on the base substrate is non-overlapping with an orthographic projection of a respective voltage supply line on the base substrate. 
     Optionally, the third node portion comprises contiguously a first portion and a second portion: the first portion is connected to the active layer of the fifth transistor, the active layer of the driving transistor, and the second portion; the second portion connects the first portion to the active layer of the third transistor; and an orthographic projection of the first portion is non-overlapping with the orthographic projection of the respective voltage supply hue on the base substrate. 
     Optionally, the array substrate further comprises a gate insulating layer on a side of the semiconductor material layer away from the base substrate; and a plurality of gate lines on a side of the gate insulating layer away from the base substrate: wherein an orthographic projection of the active layer of the third transistor on the base substrate overlaps with an orthographic projection of a respective gate line on the base substrate; and an orthographic projection of the active layer of the fifth transistor on the base substrate overlaps with an orthographic projection of a respective light emitting control signal line on the base substrate. 
     Optionally, in the respective subpixel, the respective voltage supply line comprises contiguously a first wide portion, a narrow portion, and a second wide portion; wherein an orthographic projection of the first wide portion on the base substrate is at least partially overlapping with an orthographic projection of the second portion on the base substrate; an orthographic projection of the narrow portion on the base substrate is non-overlapping with an orthographic projection of the semiconductor material layer on the base substrate; an orthographic projection of the second wide portion on the base substrate is at least partially overlapping with an orthographic projection of the active layer of the fifth transistor on the base substrate and an orthographic projection of a respective light emitting control signal line on the base substrate; and the narrow portion has an average line width smaller than an average line width of the first wide portion and smaller than an average line width of the second wide portion. 
     Optionally, the array substrate further comprises an insulating layer on a side of the semiconductor material layer away from the base substrate; a second capacitor electrode of a storage capacitor on a side of the insulating layer away from the base substrate; and an inter-layer dielectric layer on a side of the second capacitor electrode away from the base substrate; wherein the first wide portion connects to the second capacitor electrode of a storage capacitor through a ninth via extending through the inter-layer dielectric layer. 
     Optionally, in the respective subpixel, the respective voltage supply line further comprises a first segment connected to the first wide portion; and an orthographic projection of the first segment on the base substrate is at least partially overlapping with an orthographic projection of the active layer of the third transistor on the base substrate and an orthographic, projection of a respective gate line on the base substrate. 
     Optionally, in an adjacent subpixel immediately adjacent to the respective subpixel, the semiconductor material layer comprises an active layer of a second transistor, an active layer of a fourth transistor, an active layer of a driving transistor, and a second node portion that is connected to the active layer of the second transistor, the active layer of the fourth transistor, and the active layer of the driving transistor in the adjacent subpixel; and an orthographic projection of the second node portion on the base substrate is non-overlapping with the orthographic projection of the respective voltage supply line on the base substrate. 
     Optionally, at least a narrow portion of the respective voltage supply line in the respective subpixel is between the second node portion and the third node portion; and an orthographic projection of the narrow portion on the base substrate is non-overlapping with an orthographic projection of the second node portion on the base substrate, and is non-overlapping with an orthographic projection of the third node portion on the base substrate. 
     Optionally, the array substrate further comprises a plurality of gate lines on a side of the semiconductor material layer away from the base substrate; wherein, in the respective subpixel, a respective gate line comprises a main portion extending along an extension direction of the respective gate line, and a gate protrusion protruding away from the main portion; an orthographic projection of the gate protrusion on the base substrate at least partially overlaps with an orthographic projection of the active layer of the third transistor on the base substrate; and at least 90% of the orthographic projection of the gate protrusion on the base substrate is non-overlapping with an orthographic projection of a respective voltage supply line on the base substrate. 
     Optionally, the array substrate further comprises a plurality of reset control signal lines on a side of the semiconductor material layer away from the base substrate; wherein, in the respective subpixel, the respective voltage supply line comprises contiguously a third segment, a fourth segment, and a fifth segment, the fourth segment connecting the third segment and the fifth segment; an orthographic projection of the fourth segment on the base substrate is at least partially overlapping with an orthographic projection of a respective reset control signal line on the base substrate; and the fourth segment has an average line width smaller than an average line width of the third segment and smaller than an average line width of the fifth segment, 
     In another aspect, the present disclosure provides an array substrate, comprising a base substrate; a semiconductor material layer on the base substrate; a plurality of gate lines on a side of the semiconductor material layer away from the base substrate; and a plurality of voltage supply lines on a side of the plurality of gate lines away from the base substrate; wherein, in a respective subpixel, a respective gate line comprises a main portion extending along an extension direction of the respective gate line, and a gate protrusion protruding away from the main portion; wherein, in the respective subpixel, the semiconductor material layer comprises an active layer of a third transistor; an orthographic projection of the gate protrusion on the base substrate at least partially overlaps with an orthographic projection of the active layer of the third transistor on the base substrate; and at least 90% of the orthographic projection of the gate protrusion on the base substrate is non-overlapping with an orthographic projection of a respective voltage supply line on the base substrate. 
     Optionally, the orthographic projection of the gate protrusion on the base substrate is non-overlapping with the orthographic projection of the respective voltage supply line on the base substrate. 
     Optionally, the array substrate further comprises a plurality of reset control signal lines on a side of the semiconductor material layer away from the base substrate an interference preventing block on a side of the plurality of reset control signal lines away from the base substrate; and an inter-layer dielectric layer on a side of the interference preventing block away from the base substrate; wherein, in the respective subpixel, the respective voltage supply line comprises contiguously a first segment, a second segment, a third segment, and a fourth segment; wherein an orthographic projection of the first segment on the base substrate is at least partially overlapping with an orthographic projection of the active layer of the third transistor on the base substrate and at least partially overlapping with an orthographic projection of the respective gate line on the base substrate; an orthographic projection of the fourth segment on the base substrate is at least partially overlapping with an orthographic projection of a respective reset control signal line on the base substrate; the second segment connects the first segment to the third segment; the third segment connects the second segment to the fourth segment; and the third segment is connected to an interference preventing block through a third via extending through the inter-layer dielectric layer. 
     Optionally, the third segment has an average line width greater than an average line width of the second segment. 
     In another aspect, the present disclosure provides an array substrate, comprising a base substrate; a plurality of reset control signal lines on the base substrate; and a plurality of voltage supply lines on a side of the plurality of reset control signal lines away from the base substrate; wherein, in a respective subpixel, a respective voltage supply line comprises contiguously a third segment, a fourth segment, and a fifth segment, the fourth segment connecting the third segment and the fifth segment; an orthographic projection of the fourth segment on the base substrate is at least partially overlapping with an orthographic projection of a respective reset control signal, line on the base substrate; and the fourth segment has an average line width smaller than an average line width of the third segment and smaller than an average line width of the fifth segment. 
     Optionally, the array substrate further comprises a plurality of reset signal lines on a side of the plurality of reset control signal lines away from the base substrate; wherein an orthographic projection of the fifth segment on the base substrate is at least partially overlapping with an orthographic projection of a respective reset signal line on the base substrate. 
     Optionally, the array substrate further comprises an interference preventing block on a side of the plurality of reset control signal lines away from the base substrate; and an inter-layer dielectric layer on a side of the interference preventing block away from the base substrate; wherein the third segment connects to an interference preventing block through a third via extending through the inter-layer dielectric layer. 
     Optionally, the array substrate further comprises a semiconductor material layer on the base substrate; wherein, in a subpixel in a previous stage and immediately adjacent to the respective subpixel, the semiconductor material layer comprises an active layer of a sixth transistor; and an orthographic projection of the respective reset control signal line on the base substrate is at least partially overlapping with the orthographic projection of the active layer of the sixth transistor on the base substrate; and at least 80% of the orthographic projection of the active layer of the sixth transistor in the subpixel in the previous stage on the base substrate is non-overlapping with an orthographic projection of the fourth segment on the base substrate. 
     In another aspect, the present disclosure provides a display apparatus, comprising the array substrate described herein or fabricated by a method described herein, and an integrated circuit connected to the array substrate. 
    
    
     
       BRIEF DESCRIPTION OF THE FIGURES 
       The following drawings are merely examples for illustrative purposes according to various disclosed embodiments and are not intended to limit the scope of the present invention. 
         FIG.  1    is a plan view of an array substrate in sonic embodiments according to the present disclosure. 
         FIG.  2 A  is a circuit diagram illustrating the structure of a pixel driving circuit in some embodiments according to the present disclosure. 
         FIG.  2 B  is a circuit diagram illustrating the structure of a pixel driving circuit in some embodiments according to the present disclosure. 
         FIG.  3 A  is a diagram illustrating the structure of a plurality of subpixels of an array substrate in some embodiments according to the present disclosure. 
         FIG.  3 B  is a diagram illustrating the structure of a semiconductor material layer in a plurality of subpixels of an array substrate depicted in  FIG.  3 A . 
         FIG.  3 C  is a diagram illustrating the structure of a first conductive layer in a plurality of subpixels of an array substrate depicted in  FIG.  3 A . 
         FIG.  3 D  is a diagram illustrating the structure of a second conductive layer in a plurality of subpixels of an array substrate depicted in  FIG.  3 A . 
         FIG.  3 E  is a diagram illustrating the structure of a first signal line layer in a plurality of subpixels of an array substrate depicted in  FIG.  3 A . 
         FIG.  3 F  is a diagram illustrating the structure of a second signal line layer in a plurality of subpixels of an array substrate depicted in  FIG.  3 A . 
         FIG.  4 A  is a cross-sectional view along an A-A′ line in  FIG.  3 A . 
         FIG.  4 B  is a cross-sectional view along a B-B′ line in  FIG.  3 A . 
         FIG.  4 C  is a cross-sectional view along a C-C′ line in  FIG.  3 A . 
         FIG.  4 D  is a cross-sectional view along a D-D′ line in  FIG.  3 A . 
         FIG.  4 E  is a cross-sectional view along an E-E′ line in  FIG.  3 A . 
         FIG.  4 F  is a cross-sectional view along an F-F′ line in  FIG.  3 A . 
         FIG.  4 G  is a cross-sectional view along a G-G′ line in  FIG.  3 A . 
         FIG.  5 A  is a diagram illustrating a semiconductor material layer, a first conductive layer, and a first signal line layer in an array substrate in some embodiments according to the present disclosure. 
         FIG.  5 B  is a zoom-in view of a region around a third node in  FIG.  5 A . 
         FIG.  5 C  is a diagram illustrating a partial structure of a semiconductor material layer in a respective subpixel in  FIG.  5 B . 
         FIG.  5 D  is a diagram illustrating a partial structure of a respective voltage supply line in  FIG.  5 B . 
         FIG.  5 E  is a diagram illustrating a partial structure of a semiconductor material layer in an adjacent subpixel in  FIG.  5 B . 
         FIG.  6 A  is a zoom-in view of a region around an interference preventing block in  FIG.  3 A . 
         FIG.  6 B  is a diagram illustrating a partial structure of a respective gate line in  FIG.  6 A . 
         FIG.  6 C  is a diagram illustrating a partial structure of a respective voltage supply line in  FIG.  6 A . 
         FIG.  6 D  is a diagram illustrating a partial structure of a semiconductor material layer in a respective subpixel in  FIG.  6 A . 
     
    
    
     DETAIL ED DESCRIPTION 
     The disclosure will now be described more specifically with reference to the following embodiments. It is to be noted that the following descriptions of some embodiments are presented herein for purpose of illustration and description only. It is not intended to be exhaustive or to be limited to the precise form disclosed. 
     The present disclosure provides, inter alia array substrate and a display apparatus that substantially obviate one or more of the problems due to limitations and disadvantages of the related art. In one aspect, the present disclosure provides an array substrate. In some embodiments, the array substrate includes a base substrate; a semiconductor material layer on the base substrate; and a plurality of voltage supply lines on a side of the semiconductor material layer away from the base substrate. Optionally, in a respective subpixel, the semiconductor material layer includes an active layer of a third transistor, an active layer of a fifth transistor, an active layer of a driving transistor, a third node portion that is connected to the active layer of the third transistor, the active layer of the fifth transistor, and the active layer of the driving transistor in the respective subpixel. Optionally, at least 30% of an orthographic projection of the third node portion on the base substrate is non-overlapping with an orthographic projection of a respective voltage supply line on the base substrate. 
     Various appropriate pixel driving circuits may be used in the present array substrate. Examples of appropriate driving circuits include 3T1C, 2T1C, 4T1C, 4T2C, 5T2C, 6T1C, 7T1C, 7T2C, 8T1C, and 8T2C. In some embodiments, the respective one of the plurality of pixel driving circuits is an 7T1C driving circuit. Various appropriate light emitting elements may be used in the present array substrate. Examples of appropriate light emitting elements include organic light emitting diodes, quantum dots light emitting diodes, and micro light emitting diodes. Optionally, the light emitting element is micro light emitting diode. Optionally, the light emitting element is an organic light emitting diode including an organic light emitting layer. 
       FIG.  1    is a plan view of an array substrate in some embodiments according to the present disclosure. Referring to  FIG.  1   , the array substrate includes an array of subpixels Sp. Each subpixel includes an electronic component, e.g., a light emitting element. In one example, the light emitting element is driven by a respective pixel driving circuit PDC. The array substrate includes a plurality of gate lines GL, a plurality of data lines DL, a plurality of sensing signal lines SL, a plurality of voltage supply line (e.g., a high voltage supply line Vdd), and a respective second Voltage supply line (e.g., a low voltage supply line Vss), each of which electrically connected to the respective pixel driving circuit PDC. Light emission in a respective subpixel sp is driven by a respective pixel driving circuit PDC. In one example, a high voltage signal (e.g., a VDD signal) is input, through the high voltage support line Vdd, to the respective pixel driving circuit PDC connected to an anode of the light emitting element; a low voltage signal (e.g., a VSS signal) is input, through a low voltage supply line Vss, to a cathode of the light emitting element. A voltage difference between the high voltage signal (e.g., the VDD signal) and the low voltage signal (e.g., the VSS signal) is a driving voltage ΔV that drives light emission in the light emitting element. The array substrate according to the present disclosure includes a plurality of sensing signal lines SL respectively connected to sensing sub-circuits in the plurality of pixel driving circuits. 
       FIG.  2    is a circuit diagram illustrating the structure of a pixel driving circuit in some embodiments according to the present disclosure. Referring to  FIG.  2   , in some embodiments, the pixel driving circuit includes a driving transistor Td; a storage capacitor Cst having a first capacitor electrode Ce 1  and a second capacitor electrode Ce 2 ; a first transistor T 1  having a gate electrode connected to a respective reset control signal line rstN in a present stage, a source electrode connected to a respective reset signal line VintN in a present stage of a plurality of reset signal line, and a drain electrode connected to a first capacitor electrode Ce 1  of the storage capacitor Cst and a gate electrode of the driving transistor Td; a second transistor T 2  having a gate electrode connected to a respective gate line of a plurality of wire lines GL, a source electrode connected to a respective data line of a plurality of data lines DL, and a drain electrode connected to a source electrode of the driving transistor Td; a third transistor T 3  having a gate electrode connected to the respective gate line, a source electrode connected to the first capacitor electrode Ce 1  of the storage capacitor Cst and the gate electrode of the driving transistor Td, and a drain electrode connected to a drain electrode of the driving transistor Td; a fourth transistor T 4  having a gate electrode connected to a respective light emitting control signal line of a plurality of light emitting control signal lines em, a source electrode connected to a respective voltage supply line of a plurality of voltage supply lines Vdd, and a drain electrode connected to the source electrode of the driving transistor Td and the drain electrode of the second transistor T 2 ; a fifth transistor T 5  having a gate electrode connected to the respective light emitting control signal line, a source electrode connected to drain electrodes of the driving transistor Td and the third transistor T 3 , and a drain electrode connected to an anode of a light emitting element LE; and a sixth transistor T 6  having a gate electrode connected to a reset control signal line rst(N+1) in a next stage, a source electrode connected to a reset signal line Vint(N+1) in the next stage, and a drain electrode connected to the drain electrode of the fifth transistor and the anode of the light emitting element LE. The second capacitor electrode Ce 2  is connected to the respective voltage supply line and the source electrode of the fourth transistor T 4 . The pixel driving circuit further includes a switching transistor Tw having a gate electrode connected to a switching control signal lines SW, a source electrode connected to the respective data line, and a drain electrode connected to the source electrode of the second transistor T 2 . 
       FIG.  2 B  is a circuit diagram illustrating the structure of a pixel driving circuit in some embodiments according to the present disclosure. Referring, to  FIG.  2 B , in some embodiments, the third transistor T 3  is a “double gate” transistor, and the first transistor T 1  is a “double gate” transistor. Optionally, in a “double gate” first transistor, the active layer of the first transistor crosses over a respective reset control signal lines twice (alternatively, the respective reset control signal line crosses over the active layer of the first transistor T 1  twice). Similarly, in a “double gate” third transistor, the active layer of the third transistor T 3  crosses over a respective gate line of the plurality of gate lines GL twice (alternatively, the respective gate line crosses over the active layer of the third transistor T 3  twice). 
     The pixel driving circuit further include a first node N 1 , a second node N 2 , a third node N 3 , and a fourth node N 4 . The first node N 1  is connected to the gate electrode of the driving transistor Td, the first capacitor electrode Ce 1 , and the source electrode of the third transistor T 3 . The second node N 2  is connected to the drain electrode of the fourth transistor T 4 , the drain electrode of the second transistor T 2 , and the source electrode of the driving transistor Td. The third node N 3  is connected to the drain electrode of the driving transistor Td, the drain electrode of the third transistor T 3 , and the source electrode of the fifth transistor T 5 . The fourth node N 4  is connected to the drain electrode of the fifth transistor T 5 , the drain electrode of the sixth transistor T 6 , the drain electrode of the sensing transistor Ts, and the anode of the light emitting element LE. 
       FIG.  3 A  is a diagram illustrating the structure of a respective subpixel of an array substrate in some embodiments according to the present disclosure. Referring to  FIG.  3 A , the array substrate in some embodiments includes a plurality of subpixels (e.g., a red subpixel, a green subpixel, and a blue subpixel). The array substrate in some embodiments includes a plurality of gate lines GL respectively extending along a first direction DR 1 , a plurality of data lines DL respectively extending along a second direction DR 2 ; and a plurality of voltage supply lines Vdd respectively extending along the second direction DR 2 . Optionally, the array substrate thither includes a plurality of reset control signal lines (including a reset control signal line of a present stage rstN and a reset control signal line of a next stage rst(N+1)) respectively extending along the first direction DR 1 ; a plurality of reset signal lines (including a reset signal line of a present stage VintN and a reset signal line of a next stage Vinit(N+1)) respectively extending along the first direction DR 1 ; and a plurality of light emitting control signal lines em respectively extending along the first direction DR 1 . Corresponding positions of the plurality of transistors in a pixel driving circuit are depicted in  FIG.  3 A . The pixel driving circuit includes the first transistor T 1 , the second transistor T 2 , the third transistor T 3 , the fourth transistor T 4 , the fifth transistor T 5 , the sixth transistor T 6 , the sensing transistor Ts, and the driving transistor Td. 
       FIG.  3 B  is a diagram illustrating the structure of a semiconductor material layer in a respective subpixel of an may substrate depicted in  FIG.  3 A .  FIG.  3 C  is a diagram illustrating the structure of a first conductive layer in a respective subpixel of an array substrate depicted in  FIG.  3 A .  FIG.  3 D  is a diagram illustrating the structure of a second conductive layer in a respective subpixel of an array substrate depicted in  FIG.  3 A .  FIG.  3 E  is a diagram illustrating the structure of a first signal line layer in a respective subpixel of an array substrate depicted in  FIG.  3 A .  FIG.  3 F  is a diagram illustrating the structure of a second signal line layer in a plurality of subpixels of an array substrate depicted in  FIG.  3 A .  FIG.  4 A  is a cross-sectional view along an A-A′ line in  FIG.  3 A .  FIG.  4 B  is a cross-sectional view along a B-B′ line in  FIG.  3 A . Referring to  FIG.  3 A  to  FIG.  3 F , and  FIG.  4 A  to  FIG.  4 B , in some embodiments, the array substrate includes a base substrate BS, a semiconductor material layer SML on the base substrate BS, a gate insulating layer GI on a side of the semiconductor material layer SML away from the base substrate BS, a first conductive layer on a side of the gate insulating layer GI away from the semiconductor material layer SML, an insulating layer IN on a side of the first conductive layer away from the gate insulating layer GL a second conductive layer on a side of the insulating layer IN away from the first conductive layer, an inter-layer dielectric layer ILD on a side of the second conductive layer away from the insulating layer IN, a first signal line layer on a side of the inter-layer dielectric layer ILD away from the second conductive layer, a first planarization layer PLN 1  on a side of the signal line layer away from the inter-layer dielectric layer ILD, a second signal line layer on a side of the first planarization layer PLN 1  away from the first signal line layer, and a second planarization layer PLN 2  on a side of the second signal line layer away from the first planarization layer PLN 1 . 
     Referring to  FIG.  2 A .  FIG.  2 B ,  FIG.  3 A , and  FIG.  3 B , in some embodiments, in a respective subpixel sp, the semiconductor material layer has a unitary structure. In  FIG.  3 B , the respective subpixel sp is annotated with labels indicating regions corresponding to the plurality of transistors in the respective pixel driving circuit, including the first transistor T 1 , the second transistor T 2 , the third transistor T 3 , the fourth transistor T 4 , the fifth transistor T 5 , the sixth transistor T 6 , and the driving transistor Td. The respective subpixel sp is further annotated with labels indicating components of each of the plurality of transistors in the pixel driving circuit. For example, the first transistor T 1  includes an active layer ACT 1 , a source electrode S 1 , and a drain electrode D 1 . The second transistor T 2  includes an active layer ACT 2 , a source electrode S 2 , and a drain electrode D 2 . The third transistor T 3  includes an active layer ACT 3 , a source electrode S 3 , and a drain electrode D 3 . The fourth transistor T 4  includes an active layer ACT 4 , a source electrode S 4 , and a drain electrode D 4 . The fifth transistor T 5  includes an active layer ACT 5 , a source electrode S 5 , and a drain electrode D 5 . The sixth transistor T 6  includes an active layer ACT 6 , a source electrode S 6 , and a drain electrode D 6 . The driving transistor Td includes an active layer ACTd a source electrode Sd, and a drain electrode Dd. In one example, the active layers (ACT 1 , ACT 2 , ACT 3 , ACT 4 , ACT 5 , ACT 6 , and ACTd), the source electrodes (S 1 , S 2 , S 3 , S 4 , S 5 , S 6 , and Sd), and the drain electrodes (D 1 , D 2 , D 3 , D 4 , D 5 , D 6 , and Dd) of the transistors (T 1 , T 2 , T 3 , T 4 , T 5 , T 6 , and Td) in the respective subpixel sp are parts of a unitary structure in the respective subpixel. In another example, the active layers (ACT 1 , ACT 2 , ACT 3 , ACT 4 , ACT 5 , ACT 6 , and ACTd), the source electrodes (S 1 , S 2 , S 3  S 4 , S 5 , S 6 , Ss, and Sd), and the drain electrodes (D 1 , D 2 , D 3 , D 4 , D 5 , D 6 , and Dd) of the transistors (T 1 , T 2 , T 3 , T 4 , T 5 , T 6 , and Td) are in a same layer. 
     As used herein, the active layer refers to a component of the transistor comprising at least a portion of the semiconductor material layer whose orthographic projection on the base substrate overlaps with an orthographic projection of a gate electrode on the base substrate. As used herein, a source electrode refers to a component of the transistor connected to one side of the active layer, and a drain electrode refers to a component of the transistor connected to another side of the active layer. In the context of a double-gate type transistor (for example, the third transistor T 3 ), the active layer refers to a component of the transistor comprising a first portion of the semiconductor material layer whose orthographic projection on the base substrate overlaps with an orthographic projection of a first gate on the base substrate, a second portion of the semiconductor material layer whose orthographic projection on the base substrate overlaps with an orthographic projection of a second gate on the base substrate, and a third portion between the first portion and the second portion. In the context of a double-gate type transistor, a source electrode refers to a component of the transistor connected to a side of the first portion distal to the third portion, and a drain electrode refers to a component of the transistor connected to a side of the second portion distal to the third portion. 
     Referring to  FIG.  2 A ,  FIG.  2 B ,  FIG.  3 A ,  FIG.  3 C ,  FIG.  4 A , and  FIG.  4 B , the first conductive layer in some embodiments includes a plurality of gate lines GL, a plurality of reset control signal lines (including a respective reset control signal line of a present stage rstN and a reset control signal line of a next stage rst(N+1)), a plurality of light emitting control signal lines em, and a first capacitor electrode Ce 1  of the storage capacitor Cst. Various appropriate electrode materials and various appropriate fabricating methods may be used to make the first conductive layer. For example, a conductive material may be deposited on the substrate by a plasma-enhanced chemical vapor deposition (PECVD) process and patterned. Examples of appropriate conductive materials for making the first conductive layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum copper alloy, copper molybdenum alloy, molybdenum aluminum alloy, aluminum chromium alloy, copper chromium alloy, molybdenum chromium alloy, copper molybdenum aluminum alloy, and the like. Optionally, the plurality of gate lines GL, the plurality of reset control signal lines, the plurality of light emitting control signal lines em, and the first capacitor electrode Ce 1  are in a same layer. 
     As used herein, the term “same layer” refers to the relationship between the layers simultaneously formed in the same step. In one example, the plurality of gate lines GL and the first capacitor electrode Ce 1  are in a same layer when they are formed as a result of one or more steps of a same patterning process performed in a same layer of material. In another example, the plurality of gate lines GL and the first capacitor electrode Ce 1  can be formed in a same layer by simultaneously performing the step of forming the plurality of gate lines GL, and the step of forming the first capacitor electrode Ce 1 . The term “same layer” does not always mean that the thickness of the layer or the height of the layer in a cross-sectional view is the same. 
     Referring to  FIG.  2 A ,  FIG.  2 B ,  FIG.  3 A , and  FIG.  3 D , the second conductive layer in some embodiments includes a plurality of reset signal lines (including a respective reset signal line of a present stage VintN and a reset signal line of a next stage Vinit(N+1)), an interference preventing block IPB and a second capacitor electrode Ce 2  of the storage capacitor Cst. The interference preventing block IPB can effectively reduce the cross-talk, particularly vertical cross-talk between the N 1  node of the adjacent data lines. Various appropriate conductive materials and various appropriate fabricating methods may be used to make the second conductive layer. For example, a conductive material may be deposited on the substrate by a plasma-enhanced chemical vapor deposition (PECVD) process and patterned. Examples of appropriate conductive materials for making the second conductive layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum copper alloy, copper molybdenum alloy, molybdenum aluminum alloy, aluminum chromium alloy, copper chromium alloy, molybdenum chromium alloy, copper molybdenum aluminum alloy, and the like. Optionally, the plurality of reset signal lines, the second capacitor electrode Ce 2 , and the interference preventing block IPB are in a same layer. 
     Referring to  FIG.  2 A ,  FIG.  2 B ,  FIG.  3 A ,  FIG.  3 B , and  FIG.  3 E , the first signal line layer in some embodiments includes a plurality of voltage supply lines Vdd, a node connecting line Cln, a first initialization connecting line Cli 1 , a second initialization connecting line Cli 2 , and an anode contact pad ACP. The node connecting line Cln connects the first capacitor electrode Ce 1  and the source electrode of the third transistor T 3  in a respective subpixel sp together. The first initialization connecting line Cli 1  connects a respective reset signal line of the plurality of reset signal lines (e.g., the reset signal line of the present stage VintN) and the source electrode S 1  of the first transistor T 1  in the respective subpixel sp together. The second initialization connecting line Cli 2  connects a respective reset signal line of the plurality of reset signal lines (e.g., the reset signal line of the next stage Vinit(N+1)) and the source electrode S 6  of the sixth transistor T 6  in the respective subpixel sp together. The anode contact pad ACP connects a source electrode S 5  of the fifth transistor T 5  in the respective subpixel sp to an anode in the respective subpixel sp. Various appropriate conductive materials and various appropriate fabricating methods may be used to make the signal line layer. For example, a conductive material may be deposited on the substrate by a plasma-enhanced chemical vapor deposition (PECVD) process and patterned. Examples of appropriate conductive materials for making the first signal line layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum copper alloy, copper molybdenum alloy, molybdenum aluminum alloy, aluminum chromium alloy, copper chromium alloy, molybdenum chromium alloy, copper molybdenum aluminum alloy, and the like. Optionally, the plurality of voltage supply lines Vdd the node connecting line cln, the first initialization connecting line Cli 1 , the second initialization connecting line Cli 2  and the anode contact pad ACP are in a same layer. 
     Referring to  FIG.  2 A .  FIG.  2 B ,  FIG.  3 A ,  FIG.  3 B , and  FIG.  3 F , the second signal line layer in some embodiments includes a plurality of data line DL. Optionally, the second signal line layer further includes an anode contact pad ACP in a respective subpixel of the plurality of subpixels sp. The anode contact pad ACP is electrically connected to a source electrode of the fifth transistor T 5  in the respective subpixel of the plurality of subpixels sp through a relay electrode in the respective subpixel of the plurality of subpixels sp. Referring to Referring to  FIG.  2 A .  FIG.  3 A ,  FIG.  3 F ,  FIG.  3 G , and  FIG.  4 B , in some embodiments, a respective data line of the plurality of data lines DL is connected to a connecting portion CP through a via v 4 - 1  extending through the first planarization layer PLN- 1 , and the connecting portion CP is connected to a source electrode S 2  of the second transistor through a via v 4 - 2  extending through the inter-layer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI. 
     Referring to  FIG.  2 A ,  FIG.  3 A ,  FIG.  3 D ,  FIG.  3 E , and  FIG.  4 A , in some embodiments, an orthographic projection of the second capacitor electrode Ce 2  on a base substrate BS completely covers, with a margin, an orthographic projection of the first capacitor electrode Ce 1  on the base substrate BS except for a hole region H in which a portion of the second capacitor electrode Ce 2  is absent. In some embodiments, the first signal line layer includes a node connecting line Cln on a side of the inter-layer dielectric layer ILD away from the second capacitor electrode Ce 2 . The node connecting line Cln is in a same layer as the plurality of voltage supply lines Vdd. Optionally, the array substrate further includes a first via v 1  in the hole region H and extending through the inter-layer dielectric layer ILD and the insulating layer IN. Optionally, the node connecting line Cln is connected to the first capacitor electrode Ce 1  through the first via v 1 . In some embodiments, the first capacitor electrode Ce 1  is on a side of the gate insulating layer IN away from the base substrate BS. Optionally, the array substrate further includes a first via v 1  and a second via v 2 . The first via v 1  is in the hole region H and extends through the inter-layer dielectric: layer ILD and the insulating layer IN. The second via v 2  extends through the inter-layer dielectric layer ILD, the insulating layer LN, and the gate insulating layer GI. Optionally, the node connecting line Cln is connected to the first capacitor electrode Ce 1  through the first via v 1 , and is connected node connecting line Cln is connected the semiconductor material layer SML through the second via v 2 . Optionally, the node connecting line Cln is connected to the source electrode S 3  of third transistor, as depicted in  FIG.  4 A . 
     Retelling to Retelling to  FIG.  2 A ,  FIG.  3 A ,  FIG.  3 E , and  FIG.  4 B , in some embodiments, the interference preventing block IPB is in a same layer as the second capacitor electrode Ce 2 . The respective voltage supply line of the plurality of voltage supply lines Vdd is connected to the interference preventing block IPB through a third via v 3 . Optionally, the third via v 3  extends through the inter-layer dielectric layer ILD. Optionally, an orthographic projection of the interference preventing block IPB on the base substrate BS partially overlaps with an orthographic projection of the respective voltage supply line of the plurality of voltage supply lines Vdd on the base substrate BS. Optionally, the orthographic projection of the interference preventing block IPB on the base substrate BS at least partially overlaps with an orthographic projection of an active layer ACT 3  of the third transistor T 3  on the base substrate BS. Optionally, the orthographic projection of the interference preventing block IPB on the base substrate BS at least partially overlaps with an orthographic projection of a drain electrode D 1  of the first transistor T 1  on the base substrate BS. Moreover, the respective voltage supply line of the plurality of voltage supply lines Vdd is connected to the second capacitor electrode Ce 2  through a ninth via v 9 . Optionally, the ninth via v 9  extends through the inter-layer dielectric layer ILD. Optionally, an orthographic projection of the second capacitor electrode Ce 2  on the base substrate BS partially overlaps with an orthographic projection of the respective voltage supply line of the plurality of voltage supply lines Vdd on the base substrate BS. 
     Referring to Referring to  FIG.  2 A ,  FIG.  3 A .  FIG.  3 E , and  FIG.  4 B , in some embodiments, a respective data line of the plurality of data lines DL is connected to a connecting portion CP through a via v 4 - 1  extending through the first planarization layer PLN- 1 , and the connecting portion CP is connected to a source electrode S 2  of the second transistor through a via v 4 - 2  extending through the inter-layer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI. 
       FIG.  4 C  is a cross-sectional view along a C-C′ line in  FIG.  3 A . Referring to  FIG.  2 A ,  FIG.  2 B ,  FIG.  3 A ,  FIG.  3 B ,  FIG.  3 E , and  FIG.  4 C , in some embodiments, the first initialization connecting line Cli 1  connects a respective reset signal line of the plurality of reset signal lines (e.g., the reset signal line of the present stage VintN) and the source electrode S 1  of the first transistor T 1  in the respective subpixel sp together. The respective reset signal line of the plurality of reset signal lines (e.g., the reset signal line of the present stage VintN) is configured to provide a reset signal to the source electrode S 1  of the first transistor T 1  in the respective subpixel, through the first initialization connecting line Cli 1 . Optionally, the first initialization connecting line Cli 1  is connected to the reset signal line of the present stage VintN through a fifth main via v 5  extending through the inter-layer dielectric layer ILD. Optionally, the first initialization connecting line Cli 1  is connected to the source electrode S 1  of the first transistor T 1  in the respective subpixel through a sixth main via v 6  extending through the inter-layer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI. 
       FIG.  4 D  is a cross-sectional view along a D-D′ line in  FIG.  3 A . Referring to  FIG.  2 A ,  FIG.  2 B ,  FIG.  3 A ,  FIG.  3 B ,  FIG.  3 E , and  FIG.  4 D , in some embodiments, the second initialization connecting line Cli 2  connects a respective reset signal line of the plurality of reset signal lines (e.g., the reset signal line of the next stage Vinit(N+1)) and the source electrode S 6  of the sixth transistor T 6  in the respective subpixel sp together. The respective reset signal line of the plurality of reset signal lines (e.g., the reset signal line of the next stage Vinit(N+1)) is configured to provide a reset signal to the source electrode S 6  of the sixth transistor T 6  in the respective subpixel, through the second initialization connecting line Cli 2 . Optionally, the second initialization connecting line Cli 2  is connected to the reset signal line of the next stage Vinit(N+1) through a seventh main via v 7  extending through the inter-layer dielectric layer ILD. Optionally, the second initialization connecting line Cli 2  is connected to the source electrode S 6  of the sixth transistor T 6  in the respective subpixel through an eighth main via v 8  extending through the inter-layer dielectric layer ILD, the insulating layer EN, and the gate insulating layer GI. 
       FIG.  5 A  is a diagram illustrating a semiconductor material layer, a first conductive layer, and a first signal line layer in an array substrate in some embodiments according to the present disclosure.  FIG.  5 B  is a zoom-in view of a region around a third node in  FIG.  5 A . Referring to  FIG.  3 A ,  FIG.  3 B ,  FIG.  4 A .  FIG.  4 B ,  FIG.  5 A , and  FIG.  5 B , in some embodiments, the array substrate includes a base substrate BS; a semiconductor material layer SML on the base substrate; and a plurality of voltage supply lines Vdd on a side of the semiconductor material layer SML away from the base substrate BS. Optionally, in a respective subpixel sp, the semiconductor material layer SML includes an active layer ACT 3  of a third transistor T 3 , an active layer ACT 5  of a fifth transistor T 5 , an active layer ACTd of a driving transistor Td, a third node portion NP 3  that is connected to the active layer ACT 3  of the third transistor T 3 , the active layer ACT 5  of the fifth transistor T 5 , and the active layer ACTd of the driving transistor Td in the respective subpixel sp. Referring to  FIG.  2 A ,  FIG.  2 B ,  FIG.  3 A ,  FIG.  5 A , and  FIG.  5 B , the third node portion NP 3  is a portion of the semiconductor material layer having the third node N 3 . 
     In one example, boundaries of the third node portion NP 3  are defined by respective boundaries of adjacent active layers. In another example, boundaries of adjacent active layers are in turn defined by orthographic projections of respective gate electrodes on the semiconductor material layer SML. For example, boundaries of the active layer ACT 3  of the third transistor T 3  are defined by an orthographic projection the respective gate line on the semiconductor material layer SML; boundaries of the active layer ACT 5  of the fifth transistor T 5  are defined by an orthographic projection the respective light emitting control signal line on the semiconductor material layer SML; and boundaries of the active layer ACTd of the driving transistor Td are defined by an orthographic projection the first capacitor electrode Ce 1  (functioning as a gate electrode of the driving transistor Td) on the semiconductor material layer SML. Accordingly, in some embodiments, the boundaries of the third node portion NP 3  are defined an adjacent boundary of the active layer ACT 3  of the third transistor T 3 , an adjacent boundary of the active layer ACT 5  of the fifth transistor T 5 , and an adjacent boundary of the active layer ACTd of the driving transistor Td. 
     The inventors of the present disclosure discover that, a parasitic capacitance between the respective voltage supply line and the third node N 3  can unnecessarily increase the minimum charging time for charging the driving transistor T 3  (e.g., by charging the N 1  node). The inventors of the present disclosure discover that, surprisingly and unexpectedly, minimizing the parasitic capacitance between the respective voltage supply line and the third node N 3  can decrease the minimum charging time for charging the driving transistor T 3 , achieving faster response and enhancing image display quality. 
     Accordingly, the respective voltage signal line in the present disclosure is one having non-uniform line width. For example, a portion of the respective voltage signal line around the third node N 3  has a line width smaller than those of the portions immediately adjacent to the portion around the third node N 3 . The intricate structure of the respective voltage signal line in the present disclosure reduces overlapping between the respective voltage signal line and the. third node portion NP 3 , thereby reducing the parasitic capacitance between the respective voltage supply line and the third node N 3 . 
     In some embodiments, at least 30% (e.g., at least 35%, at least 40%, at least 45%, at least 50%, at least 55%, at least 60%, at least 65%, at least 70%, at least 75%, at least 80%, at least 85%, at least 90%, at least 95%, or at least 99%) of an orthographic projection of the third node portion on the base substrate is non-overlapping with an orthographic projection of a respective voltage supply line on the base substrate. Optionally, at least 50% of the orthographic projection of the third node portion on the base substrate is non-overlapping with the orthographic projection of the respective voltage supply line on the base substrate. 
       FIG.  4 E  is a cross-sectional view along an E-E′ line in  FIG.  3 A .  FIG.  4 F  is a cross-sectional view along an F-F′ line in  FIG.  3 A . Referring to  FIG.  4 E  and  FIG.  5 A , along a row direction (e.g., perpendicular to the extending direction of the respective voltage supply line), the orthographic projection of at least a portion of the respective voltage supply line on the base substrate BS is non-overlapping with the orthographic projection of at least a portion of the semiconductor material layer SMT on the base substrate BS. and the orthographic projection of at least a portion of the respective voltage supply line is between a source electrode Sd of a driving transistor Td in an adjacent subpixel Asp immediately adjacent to a respective subpixel RSp and a drain electrode Dd of a driving transistor Td in the respective subpixel RSp. Along a column direction (e.g., parallel to the extending direction of the respective voltage supply line), the orthographic projection of the respective Voltage supply line on the base substrate BS is at least partially non-overlapping with the orthographic projection of the semiconductor material layer SML on the base substrate BS. In one example, along the column direction, the orthographic projection of the respective voltage supply line on the base substrate BS is at least partially non-overlapping with an orthographic projection of the drain electrode Dd of a driving transistor Id in the respective subpixel RSp on the base substrate BS and is at least partially non-overlapping with an orthographic projection of a source electrode  55  of the fifth transistor T 5  in the respective subpixel RSp on the base substrate BS. 
       FIG.  5 C . is a diagram illustrating a partial structure of a semiconductor material layer in a respective subpixel in  FIG.  5 B . Referring to  FIG.  3 A ,  FIG.  5 A ,  FIG.  5 B , and  FIG.  5 C , the third node portion NP 3  in some embodiments includes contiguously a first portion P 1  and a second portion P 2 . The first portion P 1  is connected to the active layer ACT 5  of the fifth transistor T 5 , the active layer ACTd of the driving transistor Td, and the second portion P 2 . The second portion P 2  connects the first portion P 1  to the active layer ACT 3  of the third transistor T 3 . Referring to  FIG.  3 A ,  FIG.  5 A ,  FIG.  5 B ,  FIG.  5 C , and  FIG.  4 F , in some embodiments, an orthographic projection of the first portion P 1  is non-overlapping with the orthographic projection of the respective voltage supply line on the base substrate BS, wherein an orthographic projection of the second portion P 2  is at least partially overlapping with the orthographic projection of the respective voltage supply line on the base substrate BS. An orthographic projection of the active layer ACT 3  of the third transistor T 3  on the base substrate BS overlaps with an orthographic projection of a respective gate line of the plurality of gate lines GL on the base substrate BS. An orthographic projection of the active layer ACT 5  of the fifth transistor T 5  on the base substrate BS overlaps with an orthographic projection of a respective light emitting control signal line of the plurality of light emitting control signal lines em on the base substrate BS. 
     Optionally, the first portion P 1  includes at least a portion of a drain electrode Dd of the driving transistor Td in the respective subpixel RSp. Optionally, the first portion P 1  includes at least a portion of a source electrode S 5  of the fifth transistor T 5  in the respective subpixel RSp. Optionally, the second portion P 2  includes at least a portion of a drain electrode D 3  of the third transistor T 3  in the respective subpixel RSp. 
       FIG.  5 D  is a diagram illustrating a partial structure of a respective voltage supply line in  FIG.  5 B . Referring to  FIG.  3 A ,  FIG.  5 A ,  FIG.  5 B , and  FIG.  5 D , in the respective subpixel RSp, the respective voltage supply line of the plurality of voltage supply lines Vdd in some embodiments includes contiguously a first wide portion WP 1 , a narrow portion NP, and a second wide portion WP 2 . The narrow portion NP connects the first wide portion WP 1  and the second wide portion WP 2  together. 
     Referring to  FIG.  3 A ,  FIG.  5 A ,  FIG.  5 B ,  FIG.  5 D ,  FIG.  4 E , and  FIG.  4 F , in some embodiments, an orthographic projection of the first wide portion WP 1  on the base substrate BS is at least partially overlapping with an orthographic projection of the second portion P 2  on the base substrate BS. Optionally, the orthographic projection of the first wide portion WP 1  on the base substrate BS covers an orthographic projection of the second portion P 2  on the base substrate BS. In some embodiments, an orthographic projection of the narrow portion NP on the base substrate BS is non-overlapping with an orthographic projection of the semiconductor material layer SML on the base substrate BS. In some embodiments, an orthographic projection of the second wide portion WP 2  on the base substrate BS is at least partially overlapping with an orthographic projection of the active layer ACT 5  of the fifth transistor T 5  on the base substrate BS and an orthographic projection of a respective light emitting control signal line of the plurality of light emitting control signal lines em on the base substrate BS. 
     In some embodiments, the first wide portion WPI has an average line width wp 1 ; the narrow portion NP has an average line width wn; and the second wide portion WP 2  has an average line width wp 2 . Optionally, the average line width wn is smaller than the average line width wp 1 , and is smaller than the average line width wp 2 . 
     Referring to  FIG.  3 A ,  FIG.  5 A ,  FIG.  5 B ,  FIG.  5 D , and  FIG.  4 B , in some embodiments, the first wide portion WP 1  is a portion of the respective voltage supply line that connects to the second capacitor electrode Ce 2  of a storage capacitor through a ninth via v 9  extending through the inter-layer dielectric layer ILD. 
     Referring to  FIG.  3 A ,  FIG.  5 A ,  FIG.  5 B ,  FIG.  5 D ,  FIG.  4 E , and  FIG.  4 F , in some embodiments, in the respective subpixel RSp, the respective voltage supply line of the plurality of voltage supply lines Vdd in some embodiments includes contiguously a first segment F 1 , a first wide portion WP 1 , a narrow portion NP, and a second wide portion WP 2 . The narrow portion NP connects the first wide portion WP 1  and the second wide portion WP 2 . together. The first wide portion WP 1  connects the first segment F 1  and the narrow portion NP together. An orthographic projection of the first segment F 1  on the base substrate BS is at least partially overlapping with an orthographic projection of the active layer ACT 3  of the thud transistor T 3  in the respective subpixel RSp on the base substrate BS and an orthographic projection of a respective gate line of the plurality of gate lines GL on the base substrate BS. An orthographic projection of a boundary between the first segment F 1  and the first wide portion WP 1  on the base substrate BS overlaps with an orthographic projection of a boundary between the active layer ACT 3  of the third transistor T 3  and the second portion P 2  on the base substrate BS. 
       FIG.  5 A  depicts a respective subpixel RSp and an adjacent subpixel Asp immediately adjacent to the respective subpixel RSp. In one example, the respective subpixel RSp and the adjacent subpixel Asp are two immediately adjacent subpixels along the row direction (e.g., parallel to an extending direction of the respective gate line).  FIG.  5 E  is a diagram illustrating a partial structure of a semiconductor material layer in an adjacent subpixel in  FIG.  5 B . Referring to  FIG.  3 A ,  FIG.  5 A ,  FIG.  5 B ,  FIG.  5 D ,  FIG.  5 E , and  FIG.  4 E , in the adjacent subpixel ASp immediately adjacent to the respective subpixel RSp, the semiconductor material layer SML includes an active layer ACT 2  of a second transistor T 2 , an active layer ACT 4  it a fourth transistor T 4 , an active layer ACTd of a driving transistor Td, and a second node portion NP 2 . The second node portion NP 2  is connected to the active layer ACT 2  of the second transistor T 2 , the active layer ACT 4  of the fourth transistor T 4 , and the active layer ACTd of the driving transistor Td in the adjacent subpixel ASp. Referring to  FIG.  2 A ,  FIG.  2 B ,  FIG.  3 A ,  FIG.  5 A ,  FIG.  5 B , and  FIG.  5 E , the second node portion NP 2  is a portion of the semiconductor material layer having the second node N 2 . In some embodiments, at least 80% (e.g., at least 85%, at least 90%, at least 95%, at least 99%, or 100%) of an orthographic projection of the second node portion NP 2  on the base substrate BS is non-overlapping with the orthographic projection of the respective voltage supply line on the base substrate BS. Referring to  FIG.  4 E , in one example, an orthographic projection of the second node portion NP 2  on the base substrate BS is non-overlapping with the orthographic projection of the respective voltage supply line on the base substrate BS. 
     Referring to  FIG.  3 A ,  FIG.  5 A  to  FIG.  5 E ,  FIG.  4 E , and  FIG.  4 F , at least a narrow portion NP of the respective voltage supply line in the respective subpixel RSp is between the second node portion NP 2  and the third node portion NP 3 , more specifically, between the second node portion NP 2  and the first portion P 1 . An orthographic projection of the narrow portion NP on the base substrate BS is non-overlapping with an orthographic projection of the second node portion NP 2  on the base substrate BS, and is non-overlapping with an orthographic projection of the third node portion NP 3  on the base substrate BS. 
     The inventors of the present disclosure discover that, overlapping between the plurality of voltage supply lines Vdd and the plurality of gate lines GL increases loading in the plurality of gate lines GL. Reducing the overlapping area between the plurality of voltage supply lines Vdd and the plurality of gate lines GL can effectively reduce loading in the plurality of gate lines GL, achieving faster response and enhancing image display quality. 
     Accordingly, the respective voltage signal line in the present disclosure is one having non-uniform line width.  FIG.  6 A  is a zoom-in view of a region around an interference preventing block in  FIG.  3 A .  FIG.  6 B  is a diagram illustrating a partial structure of a respective gate line in  FIG.  6 A . Referring to  FIG.  3 A ,  FIG.  6 A , and  FIG.  6 B , in the respective subpixel, a respective gate line of the plurality of gate lines GL in some embodiments includes a main portion MP extending along an extension direction of the respective gate line, and a gate protrusion GP protruding away from the main portion MP, e.g., toward the interference preventing block IPB. Optionally, the gate protrusion GP protrudes away from the main portion MP along the column direction, e.g., a direction perpendicular to the extension direction of the respective gate line. 
     In some embodiments, as discussed above, the third transistor T 3  is a double gate transistor. In some embodiments, the gate protrusion GP is one of the double gates m the third transistor T 3 . In some embodiments, and referring to  FIG.  4 A , an orthographic projection of the gate protrusion GP on the base substrate BS at least partially overlaps with an orthographic projection of the active layer ACT 3  of the third transistor T 3  on the base substrate BS. To reducing loading in the plurality of gate lines GL, at least 90% (e.g., at least 95%, at least 98%, at least 99%, or 100%) of the orthographic projection of the gate protrusion GP on the base substrate BS is non-overlapping with an orthographic projection of a respective voltage supply line of the plurality of voltage supply lines Vdd on the base substrate BS. Referring to  FIG.  3 A ,  FIG.  6 A ,  FIG.  6 B , and  FIG.  4 A , optionally, the orthographic projection of the gate protrusion GP on the base substrate BS is non-overlapping with the orthographic projection of the respective voltage supply line on the base substrate BS. 
       FIG.  6 C  is a diagram illustrating a partial structure of a respective voltage supply line in  FIG.  6 A . Referring to  FIG.  3 A ,  FIG.  6 A ,  FIG.  6 B , and  FIG.  6 C , in some embodiments, in the respective subpixel, the respective voltage supply line of the plurality of voltage supply lines Vdd includes contiguously a first segment F 1 , a second segment F 2 , a third segment F 3 , and a fourth segment F 4 . The second segment F 2  connects the first segment F 1  to the third segment F 3 . The third segment F 3  connects the second segment F 2  to the fourth segment F 4 . Referring to  FIG.  3 A ,  FIG.  6 A ,  FIG.  6 B ,  FIG.  6 C , and  FIG.  4 B , the third segment F 3  is a segment of the respective voltage supply line that is connected to an interference preventing block IPB through a thud via v 3  extending through the inter-layer dielectric layer ILD. 
     Referring to  FIG.  4 F , in some embodiments, an orthographic projection of the first segment F 1  on the base substrate BS is at least partially overlapping with an orthographic projection of the active layer ACT 3  of the third transistor T 3  on the base substrate BS and at least partially overlapping with an orthographic projection of the respective gate line of the plurality of gate lines GL on the base substrate BS. An orthographic projection of the fourth segment F 4  on the base substrate BS is at least partially overlapping with an orthographic projection of a respective reset control signal line (e.g., the respective reset control signal line rstN in a present stage) on the base substrate BS. 
     Referring to  FIG.  6 C , the second segment F 2  has an average line width of wf 2 . The third segment F 3  has air average line width of wf 3 . Optionally, the average line width of wf 3  is greater than the average line width of wf 2 . 
       FIG.  6 D  is a diagram illustrating a partial structure of a semiconductor material layer in a respective subpixel in  FIG.  6 A . Referring to  FIG.  3 A ,  FIG.  6 A ,  FIG.  6 B ,  FIG.  6 C , and  FIG.  6 D , in some embodiments, the active layer ACT 3  of the third transistor T 3  includes a first overlapping portion Po 1 , a second overlapping portion Po 2 , and an intermediate portion Pi connecting the first overlapping portion Pol and the second overlapping portion Po 2 . Referring to  FIG.  4 F , an orthographic projection of the first overlapping portion Po 1  on the base substrate BS is covered by an orthographic projection of the respective gate line of the plurality of gate lines GL on the base substrate BS. Referring to  FIG.  4 A , an orthographic projection of the second overlapping portion Po 2  cm the base substrate BS is covered by an orthographic projection of the gate protrusion GP on the base substrate BS. Referring to  FIG.  4 F , an orthographic projection of the intermediate portion Pi on the base substrate BS is at least partially overlapping with an orthographic projection of the respective gate line of the plurality of gate lines GL on the base substrate BS. 
     Referring to  FIG.  3 A ,  FIG.  6 A ,  FIG.  6 B ,  FIG.  6 C ,  FIG.  6 D , and  FIG.  4 F , in some embodiments, an orthographic projection of the first overlapping portion Po 1  on the base substrate BS is at least partially overlapping with an orthographic projection of the main portion MP on the base substrate BS. Referring to  FIG.  3 A ,  FIG.  6 A ,  FIG.  6 B ,  FIG.  6 C ,  FIG.  6 D , and  FIG.  4 A , in some embodiments, an orthographic projection of the second overlapping portion Po 2  on the base substrate BS is at least partially overlapping with the orthographic projection of the gate protrusion GP on the base substrate BS. Referring to  FIG.  3 A ,  FIG.  6 A ,  FIG.  6 B .  FIG.  6 C ,  FIG.  6 D ,  FIG.  4 A , and  FIG.  4 F , in some embodiments, an orthographic projection of the intermediate portion Pi on the base substrate BS is non-overlapping with an orthographic projection of the respective gate line on the base substrate BS. Optionally, the orthographic projection of the respective voltage supply line of the plurality of voltage supply lines Vdd on the base substrate BS is at least partially overlapping with the orthographic projection of the intermediate portion Pi on the base substrate BS, and is at least partially overlapping with the orthographic projection of the first overlapping portion Po 1  on the base substrate BS. 
     The inventors of the present disclosure discover that, overlapping between the plurality of voltage supply lines Vdd and the plurality of reset control signal line increases loading in the plurality of reset control signal line. Reducing the overlapping area between the plurality of voltage supply lines Vdd and the plurality of reset control signal line can effectively reduce loading in the plurality of reset control signal line, achieving faster response and enhancing image display quality. 
     Accordingly, the respective voltage signal line in the present disclosure is one having non-uniform line width. For example, a portion of the respective voltage signal line crossing over a respective reset control signal line has a line width smaller than those of the portions immediately adjacent to the portion crossing over the respective reset control signal line. The intricate structure of the respective voltage signal line in the present disclosure reduces overlapping between the respective voltage signal line and the respective reset control signal line, thereby reducing the parasitic capacitance between the respective voltage supply line and the respective reset control signal line. 
     Referring to  FIG.  3 A .  FIG.  6 A ,  FIG.  6 B ,  FIG.  6 C , and  FIG.  6 D , in some embodiments, in a respective subpixel, a respective voltage supply line includes contiguously a third segment F 3 , a fourth segment F 4 , and a fifth segment F 5 . The fourth segment F 4  connects the third segment F 3  and the fitly segment F 5 . In some embodiments, the fourth segment F 4  crosses over a respective reset control signal line (e.g., the respective reset control signal line rstN in a present stage or the respective reset control signal line rst(N+1) in a next stage). An orthographic projection of the fourth segment F 4  on the base substrate BS is at least partially overlapping with an orthographic projection of a respective reset control signal line on the base substrate BS. 
     Referring to  FIG.  6 C , in some embodiments, the third segment F 3  has an average line width wf 3 ; the fourth segment F 4  has an average line width wf 4 ; and the fifth segment F 5  has an average line width wf 5 . Optionally, the average line width wf 4  is smaller than the average line width wf 3 , and is smaller than the average line width wf 5 . 
     Referring to  FIG.  3 A ,  FIG.  6 A ,  FIG.  6 B ,  FIG.  6 C ,  FIG.  6 D , and  FIG.  4 F , in some embodiments, an orthographic projection of the fifth segment F 5  on the base substrate BS is at least partially overlapping with an orthographic projection of a respective reset signal line (e.g., the respective reset signal line VintN in the present stage or the respective reset signal line Vint(N+1) in the next stage) on the base substrate BS. Referring to  FIG.  3 A ,  FIG.  6 A ,  FIG.  6 B ,  FIG.  6 C , and  FIG.  4 B , the thud segment F 3  is a segment of the respective voltage supply line that is connected to an interference preventing block IPB through a third via v 3  extending through the inter-layer dielectric layer ILD. 
       FIG.  4 G  is a cross-sectional view along a G-G′ line in  FIG.  3 A . Referring to  FIG.  3 A ,  FIG.  6 A .  FIG.  6 B ,  FIG.  6 C ,  FIG.  6 D , and  FIG.  4 G , in a subpixel PSASp in a previous stage and immediately adjacent to the respective subpixel RSp, the semiconductor material layer includes an active layer ACT 6  of a sixth transistor T 6 . An orthographic projection of the respective reset control signal line (e.g., the respective reset control signal line in the present stage rstN) on the base substrate BS is at least partially overlapping with the orthographic projection of the active layer ACT 6  of the sixth transistor T 6  on the base substrate BS. In some embodiments, at least 80% (e.g., at least 85%, at least 90%, at least 95%, at least 99%, or 100%) of the orthographic projection of the active layer ACT 6  of the sixth transistor T 6  in the subpixel PSASp in the previous stage on the base substrate BS is non-overlapping with an orthographic projection of the fourth segment F 4  on the base substrate BS. Referring to  FIG.  4 G , the orthographic projection of the active layer ACT 6  of the sixth transistor T 6  in the subpixel PSASp in the previous stage on the base substrate BS is non-overlapping with an orthographic projection of the fourth segment F 4  on the base substrate BS. 
     In another aspect, the present disclosure provides a display panel including the array substrate described herein or fabricated by a method described herein, and a counter substrate facing the array substrate. Optionally, the display panel is an organic light emitting diode display panel. Optionally, the display panel is micro light emitting diode display panel. 
     In another aspect, the present invention provides a display apparatus, including the array substrate described herein or fabricated by a method described herein, and one or more integrated circuits connected to the array substrate. Examples of appropriate display apparatuses include, but are not limited to, an electronic paper, a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital album, a GPS, etc. Option ills the display apparatus is an organic light emitting diode display apparatus. Optionally, the display apparatus is a liquid crystal display apparatus. 
     In another aspect, the present disclosure provides a method of fabricating an array substrate. In some embodiments, the method includes forming a semiconductor material layer on a base substrate; and forming a plurality of voltage supply lines on a side of the semiconductor material layer away from the base substrate. Optionally, in a respective subpixel, the semiconductor material layer is formed to include an active layer of a third transistor, an active layer of a fifth transistor, an active layer of a driving transistor, and a third node portion. The third node portion is formed to be connected to the active layer of the third transistor, the active layer of the fifth transistor, and the active layer of the driving transistor in the respective subpixel. Optionally, at least 30% of an orthographic projection of the third node portion on the base substrate is non-overlapping with an orthographic projection of a respective voltage supply line on the base substrate. 
     In some embodiments, the method of fabricating an array substrate includes forming a semiconductor material layer on a base substrate; forming a plurality of gate lines on a side of the semiconductor material layer away from the base substrate; and forming a plurality of voltage supply lines on a side of the plurality of gate lines away from the base substrate. Optionally, in a respective subpixel, a respective gate line is formed to include a main portion extending along an extension direction of the respective gate line, and a gate protrusion protruding away from the main portion. Optionally, in the respective subpixel, the semiconductor material layer is formed to include an active layer of a third transistor. Optionally, an orthographic projection of the gate protrusion on the base substrate at least partially overlaps with an orthographic projection of the active layer of the third transistor on the base substrate. Optionally, at least 90% of the orthographic projection of the gate protrusion on the base substrate is non-overlapping with an orthographic projection of a respective voltage supply line on the base substrate. 
     In some embodiments, the method of fabricating an array substrate includes forming a plurality of reset control signal lines on the base substrate; and forming a plurality of voltage supply lines on a side of the plurality of reset control signal lines away from the base substrate. Optionally, in a respective subpixel, a respective voltage supply line is formed to include a third segment, a fourth segment, and a fifth segment contiguously arranged. Optionally, the fourth segment is formed to connect the third segment and the fifth segment. Optionally, an orthographic projection of the fourth segment on the base substrate is at least partially overlapping with an orthographic projection of a respective reset control signal line on the base substrate. Optionally, the fourth segment has an average line width smaller than an average line width of the third segment and smaller than an average line width of the fifth segment. 
     The foregoing description of the embodiments of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form or to exemplary embodiments disclosed. Accordingly, the foregoing description should be regarded as illustrative rather than restrictive. Obviously, many modifications and variations will be apparent to practitioners skilled in this art. The embodiments are chosen and described in order to explain the principles of the invention and its best mode practical application, thereby to enable persons skilled in the art to understand the invention for various embodiments and with various modifications as are suited to the particular use or implementation contemplated. It is intended that the scope of the invention be defined by the claims appended hereto and their equivalents in which all terms are meant in their broadest reasonable sense unless otherwise indicated. Therefore, the term “the invention”, “the present invention” or the like does not necessarily limit the claim scope to a specific embodiment, and the reference to exemplary embodiments of the invention does not imply a limitation on the invention, and no such limitation is to be inferred. The invention is limited only by the spirit and scope of the appended claims. Moreover, these claims may refer to use “first”, “second”, etc. following with noun or element. Such terms should be understood as a nomenclature and should not be construed as giving the limitation on the number of the elements modified by such nomenclature unless specific number has been given. Any advantages and benefits described may not apply to all embodiments of the invention. It should be appreciated that variations may be made in the embodiments described by persons skilled in the art without departing from the scope of the present invention as defined by the following claims. Moreover, no element and component in the present disclosure is intended to be dedicated to the public regardless of whether the element or component is explicitly recited in the following claims.