Patent Publication Number: US-8980731-B2

Title: Methods of forming a semiconductor device

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This U.S. non-provisional patent application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2012-0103552, filed on Sep. 18, 2012, the disclosure of which is hereby incorporated by reference in its entirety. Also, this application is a continuation-in-part of U.S. patent application Ser. No. 13/167,858, filed on Jun. 24, 2011, which claims priority under 35 U.S.C. §119 to Korean Patent Application Nos. 10-2010-0060186, filed on Jun. 24, 2010, and 10-2011-0041678, filed on May 2, 2011, the disclosures of which are hereby incorporated by reference in their entireties. 
    
    
     BACKGROUND 
     The present disclosure herein relates to semiconductor devices and methods of fabricating the same, and more particularly, to semiconductor memory devices and methods of fabricating the same. 
     Integration density of semiconductor devices has increased as the electronics industry has advanced. Higher integration of semiconductor devices may be a factor in determining product price. For example, as integration density of semiconductor devices increases, product prices of semiconductor devices may decrease. Accordingly, demand for higher integration of semiconductor devices has increased. Because integration density of semiconductor devices may be determined by the area occupied by a unit memory cell, integration density may be influenced by the level of fine pattern forming technology. However, pattern fineness may be limited due to expensive semiconductor equipment and/or difficulties in semiconductor fabrication processes. 
     Three-dimensional semiconductor memory devices have been proposed for increasing integration density. Production of three-dimensional semiconductor memory devices, however, may be expensive when compared with two-dimensional semiconductor memory devices and may have concerns regarding providing reliable product characteristics. 
     SUMMARY 
     Embodiments of the inventive concept may provide semiconductor devices including gate patterns and insulation patterns repeatedly and alternatingly stacked on a substrate. The semiconductor devices may also include a through region penetrating the gate patterns and the insulation patterns. The semiconductor devices may further include a channel structure extending from the substrate through the through region. The channel structure may include a first channel pattern having a first shape. The first channel pattern may include a first semiconductor region on a sidewall of a portion of the through region, and a buried pattern dividing the first semiconductor region. The channel structure may also include a second channel pattern having a second shape. The second channel pattern may include a second semiconductor region in the through region. A grain size of the second semiconductor region may be larger than that of the first semiconductor region. 
     In some embodiments, grains of the second semiconductor region may have longer lengths in a direction substantially perpendicular to a top surface of the substrate than widths in a direction substantially parallel to the top surface of the substrate. 
     In some embodiments, the first channel pattern may be recessed within the top surface of the substrate. 
     In other embodiments, the second channel pattern may be on the first channel pattern, and the gate patterns may include an uppermost cell gate pattern and an upper selection gate pattern on the uppermost cell gate pattern, and a boundary between the first channel pattern and the second channel pattern may be between the uppermost cell gate pattern and the upper selection gate pattern. 
     In still other embodiments, the first shape is a tube shape within the first semiconductor region. 
     In even other embodiments of the inventive concept, a semiconductor device may include a third channel pattern between the first channel pattern and the second channel pattern, and may include a third semiconductor region having a grain size larger than a grain size of the first semiconductor region and smaller than a grain size of the second semiconductor region. 
     In yet other embodiments, the first channel pattern may be on the second channel pattern such that the second channel pattern is between the substrate and the first channel pattern, and the gate patterns may include a lower selection gate pattern and a lowermost cell gate pattern on the lower selection gate pattern, and a boundary between the first channel pattern and the second channel pattern may be between the lower selection gate pattern and the lowermost cell gate pattern. 
     In further embodiments, the second channel pattern includes a wider channel region than the first channel pattern. 
     In some embodiments, a drain region may be in the through region, and the first semiconductor region and the second semiconductor region may be between the drain region and the substrate. 
     In still further embodiments of inventive concept, a semiconductor device may further include a data storage layer between the gate patterns and the first channel pattern and between the gate patterns and the second channel pattern. 
     In some embodiments, the data storage layer may include a first data storage layer, and the semiconductor device may further include a second data storage layer extending along upper surfaces, lower surfaces, and sidewalls of the gate patterns. 
     In some embodiments, a top surface of the buried pattern may extend from the first semiconductor region through a portion of the second semiconductor region. 
     In even further embodiments of the inventive concept, a method of fabricating a semiconductor device may include: stacking first and second material layers repeatedly and alternatingly on a substrate; patterning the first and second material layers to form a first through region exposing the substrate; forming a first semiconductor layer in the first through region on the substrate and on sidewalls of the first and second material layers; forming a buried layer filling the first through region on the first semiconductor layer; removing a portion of the buried layer to form a second through region between the sidewalls of the first and second material layers; and forming a second semiconductor layer in the second through region, the second semiconductor layer having a grain size larger than the first semiconductor layer. 
     In yet further embodiments of the inventive concept, before forming the second through region, a method of fabricating a semiconductor device may further include performing a first heat treatment on the first semiconductor layer to crystallize the first semiconductor layer. 
     In further embodiments of the inventive concept, after forming the second semiconductor layer, a method of fabricating a semiconductor device may further include performing a second heat treatment on the second semiconductor layer and the portions of the first semiconductor layer in the second through region to crystallize the second semiconductor layer. 
     In still further embodiments, the second heat treatment may be a laser heat treatment. 
     In further embodiments, the first material layer may be a sacrificial layer and the second material layer may be an insulation layer having an etch selectivity with respect to the first material layer, and the sacrificial layer may include an uppermost cell gate sacrificial layer and an upper selection gate sacrificial layer, and a bottom surface of the second through region may be formed between the uppermost cell gate sacrificial layer and the upper selection gate sacrificial layer. 
     In further embodiments, the first material layer may include an uppermost cell gate layer and an upper selection gate layer on the uppermost cell gate layer, the second material layer may include an insulation layer, and a bottom surface of the second through region may be formed between the uppermost cell gate layer and the upper selection gate layer. The bottom surface of the second through region may be defined by a top surface of the buried layer and a top surface of the first semiconductor layer. 
     In some embodiments, removing the portion of the buried layer may include etching the buried layer such that a top surface of the buried layer is higher than that of the first semiconductor layer. 
     In some embodiments of the inventive concept, a method of fabricating a semiconductor device may include: stacking first and second material layers sequentially on a substrate; penetrating the first and second material layers to form a first preliminary semiconductor layer extending vertically from the substrate; performing a laser heat treatment process on the first preliminary semiconductor layer to form a first semiconductor layer; stacking a third material layer and a fourth material layer alternatingly and repeatedly on the second material layer; and penetrating the third and fourth material layers to form a second semiconductor layer connected to the first semiconductor layer. 
     In other embodiments, forming the second semiconductor layer may include: forming a through region by etching the third and fourth material layers and some of an upper portion of the first semiconductor layer; forming a second preliminary semiconductor layer in the through region; and performing a second heat treatment on the second preliminary semiconductor layer. 
     In still other embodiments, the second heat treatment may be a laser heat treatment. 
     In even other embodiments of the inventive concept, before forming the third and fourth material layers, a method of fabricating a semiconductor device may further include: patterning the first and second material layers to form a first trench exposing the substrate; forming a trench sacrificial layer along a lower portion and a sidewall of the first trench; and forming a trench insulation layer filling the first trench on the trench sacrificial layer. 
     In yet other embodiments of the inventive concept, a method of fabricating a semiconductor device may further include: patterning the third and fourth material layers to expose the trench insulation layer; and removing the trench insulation layer. 
     In further embodiments of the inventive concept, a method of fabricating a semiconductor device may further include forming a data storage layer on an inner sidewall of the through region. 
     In some embodiments, methods of forming semiconductor devices may include forming insulation layers and sacrificial layers on a substrate, and patterning the insulation layers and the sacrificial layers to form a first through region therethrough exposing the substrate. Methods may also include forming a first preliminary semiconductor layer in the first through region, and forming a first semiconductor layer by performing a first heat treatment process on the first preliminary semiconductor layer. Methods may also include forming a second through region in a portion of the first through region, forming a second preliminary semiconductor layer in the second through region, and forming a second semiconductor layer by performing a second heat treatment process on the second preliminary semiconductor layer. The second semiconductor layer may have a grain size larger than that of the first semiconductor layer. Methods may additionally include patterning the insulation layers and the sacrificial layers to form a first trench exposing the substrate. Methods may also include forming recess regions between the insulation layers by removing the sacrificial patterns, and forming a data storage layer in the recess regions. Methods may further include forming a gate conductive layer in the first trench and in the recess regions such that the data storage layer is between the gate conductive layer and the first and second semiconductor layers. 
     In some embodiments, methods may further include forming gate electrodes in the recess regions by removing portions of the gate conductive layer that are outside of the recess regions. 
     In some embodiments, removing portions of the gate conductive layer may include forming a second trench in the first trench. 
     In some embodiments, the methods may include, before forming the first preliminary semiconductor layer, forming a first data storage layer in the first through region. Also, forming the first preliminary semiconductor layer may include forming the first preliminary semiconductor layer on the first data storage layer, and the data storage layer formed in the recess regions may include a second data storage layer. 
     In some embodiments, methods may also include forming a device isolation pattern in the second trench. 
     In some embodiments, methods may further include forming a buried layer in the first through region to divide the first preliminary semiconductor layer. Forming the second through region may include removing a portion of the buried layer. 
     In some embodiments, methods may additionally include forming a buried layer in the second through region to divide the second preliminary semiconductor layer. Forming the second through region may include removing a portion of the first semiconductor layer in the first trench. 
     Methods of forming a semiconductor device, according to various embodiments, may include forming sacrificial layers and insulating layers that are alternately and repeatedly stacked on a substrate. The methods may include forming a channel opening penetrating the sacrificial layers and the insulating layers. The channel opening may expose a top surface of the substrate. The methods may include forming a first semiconductor pattern conformally covering an inner sidewall of the channel opening. The methods may include forming an insulation pattern on the first semiconductor pattern and in the channel opening. The methods may include forming a second semiconductor pattern on the insulation pattern to substantially fill the channel opening. The methods may include injecting dopants into the first semiconductor pattern. The methods may include melting a portion of the first semiconductor pattern adjacent an uppermost one of the sacrificial layers to form a third semiconductor pattern. 
     In some embodiments, melting the portion of the first semiconductor pattern may include performing a laser thermal treating process. 
     According to some embodiments, forming the third semiconductor pattern may further include re-crystallizing the melted first semiconductor pattern. 
     In some embodiments, the dopants may include first conductivity type dopants and the methods may further include injecting second conductivity type dopants into the second semiconductor pattern after re-crystallizing the melted first semiconductor pattern. 
     According to some embodiments, the dopants may include first conductivity type dopants and the methods may further include injecting second conductivity type dopants into the second semiconductor pattern after injecting the first conductivity type dopants into the portion of the first semiconductor pattern and before melting the portion of the first semiconductor pattern. 
     In some embodiments, a grain size of the third semiconductor pattern may be greater than a grain size of the first semiconductor pattern. 
     According to some embodiments, the methods may further include conformally forming a data storage layer covering the inner sidewall of the channel opening before forming the first semiconductor pattern. 
     In some embodiments, the methods may further include, after forming the third semiconductor pattern, successively patterning the insulating layers and the sacrificial layers to form trenches exposing top surfaces of the substrate on opposing sides of the channel opening, removing the sacrificial layers exposed by the trenches to form recess regions, forming a data storage layer covering inner surfaces of the recess regions, and forming gate conductive patterns respectively filling the recess regions. 
     According to some embodiments, the recess regions may expose a portion of the first semiconductor pattern and a portion of the third semiconductor pattern, respectively. 
     In some embodiments, a portion of the third semiconductor pattern may be exposed by an uppermost one of the recess regions. 
     Methods of forming a semiconductor device, according to various embodiments, may include forming first and second layers that are alternately and repeatedly stacked on a substrate. The methods may also include forming an opening penetrating the first and second layers. The methods may additionally include forming a first semiconductor pattern in the opening. The methods may further include forming an insulation pattern on the first semiconductor pattern and in the opening. The methods may also include forming a second semiconductor pattern on the insulation pattern. The methods may additionally include providing (e.g., injecting/implanting, among other techniques) dopants in the first semiconductor pattern. Moreover, the methods may include thermally treating (e.g., by an annealing process, among other techniques) a portion of the first semiconductor pattern to form a third semiconductor pattern that includes a substantially uniform distribution of the dopants. 
     In some embodiments, the distribution of the dopants in the third semiconductor pattern may be more uniform than a distribution of the dopants in the portion of the first semiconductor pattern before thermally treating the portion of the first semiconductor pattern. 
     According to some embodiments, the third semiconductor pattern may be configured to provide a channel region of an adjacent transistor. 
     In some embodiments, the third semiconductor pattern may be adjacent at least a portion of uppermost ones of the first and second layers, respectively. 
     According to some embodiments, the uppermost one of the first layers may include a gate electrode of the adjacent transistor. 
     In some embodiments, the first and second layers may include sacrificial layers and insulating layers, respectively. 
     According to some embodiments, the first and second layers may include data storage layers and insulating layers, respectively. 
     In some embodiments, the methods may include removing an upper portion of the insulation pattern before forming the second semiconductor pattern. 
     According to some embodiments, the dopants may include first conductivity type dopants and the methods may further include forming a conductive pad by providing second conductivity type dopants in the second semiconductor pattern. 
     In some embodiments, thermally treating the portion of the first semiconductor pattern may include melting the portion of the first semiconductor pattern. Forming the third semiconductor pattern may further include re-crystallizing the melted portion of the first semiconductor pattern. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The foregoing and other features and advantages of the disclosure will become more apparent by describing in detail exemplary embodiments thereof with reference to the following drawings. In the drawings: 
         FIG. 1  is a circuit diagram of a semiconductor device according to some embodiments; 
         FIG. 2  is a perspective view of a semiconductor device according to some embodiments; 
         FIG. 3  is an enlarged view of the area ‘A’ in  FIG. 2 ; 
         FIGS. 4 through 12  are cross-sectional views illustrating a method of fabricating a semiconductor device according to some embodiments; 
         FIG. 13  is a perspective view of a semiconductor device according to some embodiments; 
         FIG. 14  is an enlarged view of the area ‘B’ in  FIG. 13 ; 
         FIGS. 15 through 20  are cross-sectional views illustrating a method of fabricating a semiconductor device according to some embodiments; 
         FIG. 21  is a perspective view of a semiconductor device according to some embodiments; 
         FIG. 22  is an enlarged view of the area ‘C’ in  FIG. 21 ; 
         FIGS. 23 through 31  are cross-sectional views illustrating a method of fabricating a semiconductor device according to some embodiments; 
         FIG. 32  is a perspective view of a semiconductor device according to some embodiments; 
         FIG. 33  is an enlarged view of the area ‘E’ in  FIG. 32 ; 
         FIGS. 34 through 42  are cross-sectional views illustrating a method of fabricating a semiconductor device according to some embodiments; 
         FIG. 43  is a perspective view of a semiconductor device according to some embodiments; 
         FIG. 44  is an enlarged view of the area ‘F’ in  FIG. 43 ; 
         FIGS. 45 through 49  are cross-sectional views illustrating a method of fabricating a semiconductor device according to some embodiments; 
         FIG. 50  is a perspective view of a semiconductor device according to some embodiments; 
         FIG. 51  is an enlarged view of a channel structure in  FIG. 50 ; 
         FIGS. 52 through 62  are cross-sectional views and upper surface views illustrating a method of fabricating a semiconductor device according to some embodiments; 
         FIG. 63  is a perspective view of a semiconductor device according to some embodiments; 
         FIG. 64  is an enlarged view of a channel structure in  FIG. 63 ; 
         FIGS. 65 through 72  are cross-sectional views and upper surface view illustrating a method of fabricating a semiconductor device according to some embodiments; 
         FIGS. 73 and 74  are perspective views illustrating structures of data storage layers according to some embodiments; 
         FIGS. 75A through 75L  are cross-sectional views illustrating a method of fabricating a semiconductor device according to some embodiments; 
         FIG. 76  is an enlarged view of a region ‘A’ in  FIG. 75L  that illustrates a vertical non-volatile memory device according to some embodiments; 
         FIG. 77  is a graph illustrating a concentration of dopants doped in a semiconductor layer in a method of fabricating a vertical non-volatile memory device according to some embodiments; 
         FIG. 78  is a schematic block diagram illustrating an example of a memory system including the semiconductor device formed according to some embodiments; 
         FIG. 79  is a schematic block diagram illustrating an example of a memory card having the semiconductor device formed according to some embodiments; and 
         FIG. 80  is a schematic block diagram illustrating an example of a data processing system mounting the semiconductor device formed according to some embodiments. 
     
    
    
     DETAILED DESCRIPTION 
     Example embodiments are described below with reference to the accompanying drawings. Many different forms and embodiments are possible without deviating from the spirit and teachings of this disclosure and so the disclosure should not be construed as limited to the example embodiments set forth herein. Rather, these example embodiments are provided so that this disclosure will be thorough and complete, and will convey the scope of the disclosure to those skilled in the art. In the drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. Like reference numbers refer to like elements throughout. 
     Example embodiments are described herein with reference to cross-section illustrations that are schematic illustrations of idealized example embodiments (and intermediate structures). As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, example embodiments may not be construed as limited to the particular shapes of regions illustrated herein but may be construed to include deviations in shapes that result, for example, from manufacturing. 
     The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the embodiments. As used herein, the singular forms “a”, “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and/or “including,” when used herein, specify the presence of stated features, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and/or groups thereof. 
     It will be understood that when an element is referred to as being “coupled,” “connected,” or “responsive” to, or “on,” another element, it can be directly coupled, connected, or responsive to, or on, the other element, or intervening elements may also be present. In contrast, when an element is referred to as being “directly coupled,” “directly connected,” or “directly responsive” to, or “directly on,” another element, there are no intervening elements present. As used herein the term “and/or” includes any and all combinations of one or more of the associated listed items. Moreover, The terms “substantially” and “about” mean that the recited number or value can vary by +/−20%. 
     It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, a first element could be termed a second element without departing from the teachings of the present embodiments. 
     Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which these embodiments belong. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. 
       FIG. 1  is a circuit diagram of a semiconductor device according to some embodiments of the inventive concept. 
     Referring to  FIG. 1 , a semiconductor memory device according to some embodiments may include a common source line CSL, a plurality of bit lines BL 0 , BL 1 , BL 2  and BL 3 , and a plurality of cell strings CSTR arranged between the common source line CSL and the bit lines BL 0 -BL 3 . 
     The common source line CSL may be a conductive thin film disposed on a semiconductor substrate, or an impurity region formed in the substrate. The bit lines BL 0 -BL 3  may be conductive patterns (e.g., metal lines) that are spaced apart from the semiconductor substrate and disposed thereon. The bit lines BL 0 -BL 3  are arranged in two-dimensions, and the plurality of cell strings CSTR are connected in parallel to each of the bit lines BL 0 -BL 3 . Therefore, the cell strings CSTR are two-dimensionally arranged on the common source line CSL or the substrate. 
     Each of the cell strings CSTR may include a ground selection transistor GST connected to the common source line CSL, a string selection transistor SST connected to the bit lines BL 0 -BL 3 , and a plurality of memory cell transistors MCT arranged between the ground and string selection transistors GST and SST. The ground selection transistor GST, the string selection transistor SST, and the memory cell transistors MCT may be connected in series. In addition, a ground selection line GSL, a plurality of word lines WL 0 -WL 3 , and a plurality of string selection lines SSL, which are arranged between the common source line CSL and the bit lines BL 0 -BL 3 , may be used as gate electrodes of the ground selection transistor GST, the memory cell transistors MCT, and the string selection transistors SST, respectively. 
     The ground selection transistors GST may be arranged at a substantially equal distance from the substrate, and gate electrodes thereof may be connected in common to the ground selection line GSL, thus enabling the gate electrodes of the GSTs to be in an equipotential state. For this purpose, the ground selection line GSL may be a conductive pattern having a plate shape or a comb shape which is arranged between the common source line CSL and the memory cell transistor MCT most adjacent thereto. Similarly, the gate electrodes of the memory cell transistors MCT, which are arranged at a substantially equal distance from the common source line CSL, may also be connected in common to one of the word lines WL 0 -WL 3 , thereby enabling the gate electrodes of the MCTs to be in an equipotential state. For this purpose, each of the word lines WL 0 -WL 3  may be a conductive pattern having a plate shape or a comb shape which is parallel to an upper surface of the substrate. Meanwhile, since one cell string CSTR includes the plurality of memory cell transistors MCT having different distances from the common source line CSL from each other, the multi-layered word lines WL 0 -WL 3  are arranged between the common source line CSL and the bit lines BL 0 -BL 3 . 
     Each of the cell strings CSTR may include a semiconductor pillar which vertically extends from the common source line CSL to be connected to the bit lines BL 0 -BL 3 . The semiconductor pillars may be formed to penetrate the ground selection line GSL and the word lines WL 0 -WL 3 . In addition, the semiconductor pillar may include a body portion and impurity regions formed at one end or both ends of the body portion. For example, a drain region may be formed at an upper end of the semiconductor pillar. 
     Meanwhile, a data storage layer may be arranged between the word lines WL 0 -WL 3  and the semiconductor pillar. According to some embodiments, the data storage layer may be a charge storage layer. For example, the data storage layer may be one of insulation layers including a trap insulation layer, a floating gate electrode, or conductive nano dots. 
     Between the ground selection line GSL and the semiconductor pillar or between the string selection line SSL and the semiconductor pillar, a dielectric layer, which may be used for a gate dielectric of the ground selection transistor GST or the string selection transistor SST, may be arranged. The gate dielectric of at least one of the ground and string selection transistors GST and SST may be formed with the same material as the data storage layer of the memory cell transistor MCT, but may be a gate dielectric (e.g., silicon oxide layer) for a typical metal-oxide-semiconductor field-effect-transistor (MOSFET). 
     The ground and string selection transistors GST and SST and memory cell transistors MCT may be MOSFETs using the semiconductor pillar as a channel region. According to some embodiments, the semiconductor pillar, together with the ground selection line GSL, the word lines WL 0 -WL 3  and the string selection lines SSL, may constitute a metal-oxide-semiconductor (MOS) capacitor. In this case, the ground selection transistor GST, the memory cell transistors MCT and the string selection transistor SST may be electrically connected by sharing an inversion layer formed by a fringe field from the ground selection line GSL, the word lines WL 0 -WL 3  and the string selection lines SSL. 
       FIG. 2  is a perspective view of a semiconductor device according to some embodiments of the inventive concept, and  FIG. 3  is an enlarged view of the area ‘A’ in  FIG. 2 . 
     Referring to  FIGS. 2 and 3 , a substrate  100  is provided. The substrate  100  may be a silicon substrate, a germanium substrate or a silicon-germanium substrate. The substrate  100  may have a structure doped with a first-type dopant. First material layers and second material layers including a material different from the first material layers, which are repeatedly and alternatingly stacked on the substrate  100 , may be provided. The first material layers are gate patterns  157 U,  157   m ,  157  and  157 L, and the second material layers may be insulation patterns  120 Ua,  120   a  and  120 La. The gate patterns may include a lower selection gate pattern  157 L, cell gate patterns  157   m  and  157  and an upper selection gate pattern  157 U. The cell gate patterns may include an uppermost cell gate pattern  157   m  and a cell gate pattern  157  thereunder. A buffer insulation layer  105  may be provided between the substrate  100  and the lower selection gate pattern  157 L. The buffer insulation layer  105  may be a silicon oxide layer. The lower selection gate pattern  157 L and the upper selection gate pattern  157 U may be formed thicker than the cell gate patterns  157   m  and  157 . The insulation patterns may include an uppermost insulation pattern  120 Ua, a lowermost insulation pattern  120 La and an insulation pattern  120   a  between the uppermost insulation pattern  120 Ua and the lowermost insulation pattern  120 La. The gate patterns  157 U,  157   m ,  157  and  157 L and the insulation patterns  120 Ua,  120   a  and  120 La may extend in a horizontal direction, for example, a y direction. While only six of the gate patterns  157 U,  157   m ,  157  and  157 L and the insulation patterns  120 Ua,  120   a  and  120 La are illustrated, respectively, some patterns are omitted for the simplicity of the description. Also, although only one of each of the selection gate patterns  157 U and  157 L are illustrated, they may be provided in plurality. 
     The gate patterns  157 U,  157   m ,  157  and  157 L may include at least one of metal, metal silicide, conductive metal nitride, and a doped semiconductor material. The insulation patterns  120 Ua,  120   a  and  120 La may be provided in a space that is spaced apart between the gate patterns  157 U,  157   m ,  157  and  157 L. The insulation patterns  120 Ua,  120   a  and  120 La may be oxide layers. 
     A channel structure  139  extending vertically from the substrate  100  may be provided. The channel structure  139  may be provided in a first through region  125  which penetrates the gate patterns  157 U,  157   m ,  157  and  157 L and the insulation patterns  120 Ua,  120   a  and  120 La. The channel structure  139  may include a semiconductor pattern  136  and a buried pattern  156 . 
     Referring to  FIG. 3 , the channel structure  139  may include a first channel pattern G 1  and a second channel pattern G 2 . The first channel pattern G 1  may be formed at a lower portion of the first through region  125 , and the second channel pattern G 2  may be formed over the first channel pattern G 1 . The first channel pattern G 1  may include a first semiconductor region  191  provided at a lower portion and a portion of an inner sidewall of the first through region  125 , and the buried pattern  156  may be provided in the first semiconductor region  191 . That is, the first channel pattern G 1  of the channel structure  139  may have a macaroni shape or a shell shape in which the buried pattern  156  is filled in the tube-shaped first semiconductor region  191 . The buried pattern  156  may be a dielectric pattern. Alternatively, the second channel pattern G 2  may include a second semiconductor region  192  completely filling a remaining portion of the first through region  125  which is partially filled with the first channel pattern G 1 . That is, the second channel pattern G 2  of the channel structure  139  may have a shape even without including the buried pattern  156 . A grain size of the second semiconductor region  192  may be larger than that of the first semiconductor region  191 . 
     A boundary between the first channel pattern G 1  and the second channel pattern G 2  may be provided between the uppermost cell gate pattern  157   m  and the upper selection gate pattern  157 U. That is, a top surface of the buried pattern  156  may be higher (e.g., closer to the second channel pattern G 2 ) than a top surface of the uppermost cell gate pattern  157   m.    
     A third channel pattern G 3  may be provided between the first channel pattern G 1  and the second channel pattern G 2 . The third channel pattern G 3  may include a third semiconductor region  193  having a grain size larger than the grain size of the first semiconductor region  191  and smaller than the grain size of the second semiconductor region  192 . The first through third semiconductor regions  191 - 193  may constitute the semiconductor pattern  136 . 
     The channel structures  139  arranged in a first direction (x-axis direction) constitute one row, and the channel structures  139  arranged in a second direction (y-axis direction) constitute one column. Hereinafter, throughout the specification, the first, the second and a third directions may denote the x-axis, the y-axis and the z-axis directions in  FIG. 2 , respectively. A plurality of rows and a plurality of columns may be arranged on the substrate  100 . A device isolation pattern  175  may be arranged between a pair of adjacent ones of the rows. That is, the device isolation pattern  175  may extend in the second direction. The device isolation pattern  175  may include an insulating material. For example, the device isolation pattern  175  may be formed of a high-density plasma oxide layer, a spin on glass (SOG) layer and/or a chemical vapor deposition (CVD) oxide layer, or the like. A first impurity region  170  may be formed in the substrate  100  under a bottom surface of the device isolation pattern  175 . The first impurity region  170  may have a line shape extending in the second direction (y-axis direction). The first impurity region  170  may be a region doped with a second-type dopant. The second-type may provide a conductivity type different from the first-type. 
     A data storage layer  150  may be provided between the gate patterns  157 U,  157   m ,  157  and  157 L and the channel structure  139 . The data storage layer  150  may include a charge storage layer  152  for storing charges. In addition, the data storage layer  150  may further include a tunnel insulation layer  151  between the charge storage layer  152  and the channel structure  139 , and a blocking layer  153  between the charge storage layer  152  and the gate patterns  157 U,  157   m ,  157  and  157 L. The charge storage layer  152  may be formed of a material having traps which store charges. For example, the charge storage layer  152  may include at least one of a silicon nitride layer, a metal nitride layer, a metal oxynitride layer, a metal silicon oxide layer, a metal silicon oxynitride layer and nano dots. The blocking layer  153  may include at least one of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer and a high-k dielectric layer. The high-k dielectric layer may include at least one of a metal oxide layer, a metal nitride layer and a metal oxynitride layer. The high-k dielectric layer may include hafnium (Hf), zirconium (Zr), aluminum (Al), tantalum (Ta), lanthanum (La), cerium (Ce), praseodymium (Pr) and the like. A dielectric constant of the blocking layer  153  may be larger than that of the tunnel insulation layer  151 . 
     A drain region D may be provided to the channel structure  139  adjacent the uppermost insulation pattern  120 Ua on the upper selection gate pattern  157 U. Bit lines BL, which extend alongside in a direction (e.g., x direction) crossing the gate patterns  157 U,  157   m ,  157  and  157 L and are electrically connected to the drain region D, are provided. The bit lines BL may include a conductive material. 
     According to some embodiments, a selection transistor region is provided having an active region wider than an active region of a cell region. Also, the selection transistor region may have a channel region with a large grain size. Therefore, the selection transistor region may secure a wide channel region and reduce resistance. 
       FIG. 4  illustrates a method of fabricating a semiconductor device according to some embodiments. Referring to  FIG. 4 , a substrate  100  is prepared. The substrate  100  may be a semiconductor substrate. For example, the substrate  100  may be a silicon substrate, a germanium substrate, a silicon-germanium substrate, a compound semiconductor substrate, or the like. The substrate  100  may be doped with a first-type dopant. 
     First material layers and second material layers including a material different from the first material layers may be repeatedly and alternatingly stacked on the substrate  100 . The first material layers may be sacrificial layers  110 L,  110   m ,  110  and  110 U. The second material layers may be insulation layers  120 L,  120  and  120 U. The sacrificial layers  110 L,  110   m ,  110  and  110 U may be formed of a material having an etch selectivity with respect to the insulation layers  120 L,  120  and  120 U. For example, the insulation layers  120 L,  120  and  120 U may be formed of oxide, and the sacrificial layers  110 L,  110   m ,  110  and  110 U may include nitride and/or oxynitride, or the like. The sacrificial layers  110 L,  110   m ,  110  and  110 U may each be formed of the same material. Likewise, the insulation layers  120 L,  120  and  120 U may each be formed of the same material. 
     An upper selection gate sacrificial layer  110 U and a lower selection gate sacrificial layer  110 L among the sacrificial layers  110 L,  110   m ,  110  and  110 U may be formed thicker than the cell gate sacrificial layers  110   m  and  110  between the upper selection gate sacrificial layer  110 U and the lower selection gate sacrificial layer  110 L. Alternatively, the sacrificial layers  110 L,  110   m ,  110  and  110 U may be formed with the same thickness. The upper selection gate sacrificial layer  110 U occupies a space where an upper selection gate pattern is formed, and the cell gate sacrificial layers  110   m  and  110  may occupy a space where cell gate patterns are formed. The cell gate sacrificial layer may include an uppermost cell gate sacrificial layer  110   m  and a cell gate sacrificial layer  110  thereunder. The lower selection gate sacrificial layer  110 L may occupy a space where a lower selection gate pattern is formed. The uppermost insulation layer  120 U among the insulation layers  120 L,  120  and  120 U may be formed thicker than the insulation layers  120  and  120 L thereunder. 
     Before forming the sacrificial layers  110 L,  110   m ,  110  and  110 U and the insulation layers  120 L,  120  and  120 U, a buffer insulation layer  105  may be formed on the substrate  100 . The sacrificial layers  110 L,  110   m ,  110  and  110 U and the insulation layers  120 L,  120  and  120 U may be formed on the buffer insulation layer  105 . The lower selection gate sacrificial layer  110 L may be formed directly on the buffer insulation layer  105 . The buffer insulation layer  105  may be formed of a dielectric material having an etch selectivity with respect to the sacrificial layers  110 L,  110   m ,  110  and  110 U. For example, the buffer insulation layer  105  may be formed of an oxide, such as a thermal oxide, for example. 
     Referring to  FIG. 5 , the buffer insulation layer  105 , the insulation layers  120 L,  120  and  120 U and the sacrificial layers  110 L,  110   m ,  110  and  110 U are continuously patterned such that a first through region  125  exposing an upper surface of the substrate  100  may be formed. The first through region  125  may be formed using an anisotropic etching process. The first through region  125  may have a hole shape. The first through region  125  may be two-dimensionally arranged along a first direction and a second direction perpendicular to the first direction. The first direction and the second direction are parallel to the upper surface of the substrate  100 . The first through region  125  may have a round shape, an oval shape, or a polygonal shape in plan view. 
     Referring to  FIG. 6 , a first preliminary semiconductor layer  131  may be formed along a sidewall and a lower portion of the first through region  125 . The first preliminary semiconductor layer  131  may be a silicon layer. A buried layer  155  filling the first through region  125  may be formed on the first preliminary semiconductor layer  131 . For example, when the insulation layers  120 L,  120  and  120 U are oxide layers, the buried layer  155  may be a nitride layer or oxynitride layer. The first preliminary semiconductor layer  131  and the buried layer  155  may be formed by chemical vapor deposition (CVD) or atomic layer deposition (ALD). After the first preliminary semiconductor layer  131  and the buried layer  155  are deposited, the uppermost insulation layer  120 U may be exposed by a planarization process. 
     Referring to  FIG. 7 , a first semiconductor layer  132  may be formed by performing a first heat treatment process on the first preliminary semiconductor layer  131 . The first preliminary semiconductor layer  131  is recrystallized by the first heat treatment process, thereby enabling it to have a relatively small grain size like the first channel pattern G 1  in  FIG. 3 . The first heat treatment process may be a solid phase crystallization process. 
     A portion of the buried layer  155  is removed such that a buried pattern  156  and a second through region  126  may be formed. The removal of the buried layer  155  may be performed with a solution having an etch selectivity with respect to the buried layer  155 . A portion of the first semiconductor layer  132  may be etched during forming the second through region  126 . A bottom surface of the second through region  126  may be provided between the uppermost cell gate sacrificial layer  110   m  and the upper selection gate sacrificial layer  110 U. A second preliminary semiconductor layer  134  filling the second through region  126  may be formed. The second preliminary semiconductor layer  134  may be formed with the same method as the first preliminary semiconductor layer  131 . 
     Referring to  FIGS. 3 and 8 , a second heat treatment process may be performed on the second preliminary semiconductor layer  134 . The second heat treatment process may be performed on a portion of the first semiconductor layer  132  constituting a sidewall of the second through region  126 . As a result of the second heat treatment, the second channel pattern G 2  in  FIG. 3  may be formed. The second channel pattern G 2  includes a second semiconductor region  192 . The first channel pattern G 1  includes a first semiconductor region  191  and the buried pattern  156 . The second semiconductor region  192  may have a larger grain size than the first semiconductor region  191  due to recrystallization by the second heat treatment process. For example, the second semiconductor region  192  may be substantially mono-crystalline. The second heat treatment process may be a laser heat treatment process. The laser heat treatment process may include at least a liquid phase melting operation of a semiconductor layer. Therefore, a semiconductor layer having a larger grain size than a semiconductor layer that is formed by solid phase crystallization may be formed during recrystallization. 
     A third channel pattern G 3  including a third semiconductor region  193 , which has a grain size larger than a grain size of the first semiconductor region  191  and smaller than a grain size of the second semiconductor region  192 , may be provided between the first channel pattern G 1  and the second channel pattern G 2 . The third channel pattern G 3  may be formed by recrystallization that has partially progressed during the second heat treatment process. Before or after the second heat treatment process, a planarization process is performed to expose the uppermost insulation layer  120 U. The first through third semiconductor regions  191 - 193  constitute a semiconductor pattern  136 , and the semiconductor pattern  136  and the buried pattern  156  may constitute a channel structure  139 . 
     Referring to  FIG. 9 , the insulation layers  120 L,  120  and  120 U and the sacrificial layers  110 L,  110   m ,  110  and  110 U are continuously patterned to form a first trench  140 . The first trench  140  defines sacrificial patterns  110 La,  110   ma ,  110   a  and  110 Ua and insulation patterns  120 La,  120   a  and  120 Ua which are alternatingly and repeatedly stacked. Forming the first trench  140  may be performed by an anisotropic etching process. The first trench  140  may extend in the second direction. Therefore, the sacrificial patterns  110 La,  110   ma ,  110   a  and  110 Ua and the insulation patterns  120 La,  120   a  and  120 Ua may also have line shapes extending in the second direction. 
     The sacrificial patterns  110 La,  110   ma ,  110   a  and  110 Ua and the insulation patterns  120 La,  120   a  and  120 Ua are exposed at a sidewall of the first trench  140 . The substrate  100  may be exposed at a bottom of the first trench  140 . Alternatively, the buffer insulation layer  105  may be exposed at the bottom of the first trench  140 . 
     Referring to  FIG. 10 , the sacrificial patterns  110 La,  110   ma ,  110   a  and  110 Ua exposed by the first trench  140  are removed by performing a selective etching process such that recess regions  145 L,  145 ,  145 U may be formed. The selective etching process may be an isotropic etching process. The selective etching process may be performed by a wet etching and/or an isotropic dry etching. An etch rate of the sacrificial patterns  110 La,  110   ma ,  110   a  and  110 Ua by the selective etching process may be larger/faster than etch rates of the insulation patterns  120 La,  120   a  and  120 Ua, the buffer insulation layer  105  and the semiconductor pattern  136 . Therefore, after performing the selective etching process, the insulation patterns  120 La,  120   a  and  120 Ua, the buffer insulation layer  105  and the channel structure  139  may remain. The recess regions  145 L,  145 ,  145 U may expose portions of a sidewall of the channel structure  139  which were in contact with the sacrificial patterns  110 La,  110   ma ,  110   a  and  110 Ua, respectively. 
     Referring to  FIGS. 3 and 11 , after the recess regions  145 L,  145 ,  145 U are formed, a data storage layer  150  may be disposed on the substrate  100 . The data storage layer  150  may be formed using a deposition technology (e.g., CVD or ALD, etc.) which can provide excellent step coverage. Therefore, the data storage layer  150  may be substantially formed conformally. The data storage layer  150  may be formed conformally along inner surfaces of the recess regions  145 L,  145 ,  145 U. The data storage layer  150  may fill a portion of the recess regions  145 L,  145 ,  145 U. 
     As described in  FIG. 3 , forming the data storage layer  150  may include forming a tunnel insulation layer  151 , a charge storage layer  152  and a blocking layer  153  in sequence. 
     The tunnel insulation layer  151  may be formed to cover a sidewall of the channel structure  139 . The tunnel insulation layer  151  may be a single layer or multiple layers. For example, the tunnel insulation layer  151  may include at least one of a silicon oxynitride layer, a silicon nitride layer, a silicon oxide layer and a metal oxide layer. 
     The charge storage layer  152  may be spaced apart from the channel structure  139  by the tunnel insulation layer  151 . The charge storage layer  152  may include charge trap sites capable of storing charges. For example, the charge storage layer  152  may include at least one of a silicon nitride layer, a metal nitride layer, a metal oxynitride layer, a metal silicon oxide layer, a metal silicon oxynitride layer and nano dots. 
     The blocking layer  153  may cover the charge storage layer  152 . The blocking layer  153  may include at least one of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer and a high-k dielectric layer. The high-k dielectric layer may include at least one of a metal oxide layer, a metal nitride layer and a metal oxynitride layer. The high-k dielectric layer may include hafnium (Hf), zirconium (Zr), aluminum (Al), tantalum (Ta), lanthanum (La), cerium (Ce), praseodymium (Pr) and the like. A dielectric constant of the blocking layer  153  may be larger than a dielectric constant of the tunnel insulation layer  151 . 
     After the data storage layer  150  is formed, a gate conductive layer  158  may be disposed on the substrate  100 . The gate conductive layer  158  may fill the recess regions  145 L,  145 ,  145 U. The gate conductive layer  158  may fill at least a portion of the first trench  140 . The gate conductive layer  158  may be electrically isolated from the channel structure  139  and the substrate  100  by the data storage layer  150 . The gate conductive layer  158  may be formed by a CVD method, a physical vapor deposition (PVD) method, or an ALD method. The gate conductive layer  158  may include at least one of metal, metal silicide, conductive metal nitride, a doped semiconductor material and the like. 
     Referring to  FIG. 12 , after forming the gate conductive layer  158 , portions of the gate conductive layer  158  that are positioned outside of the recess regions  145 L,  145 ,  145 U are removed to form gate electrodes  157 L,  157   m ,  157  and  157 U in the recess regions  145 L,  145 ,  145 U. For example, the portions of the gate conductive layer  158  outside of the recess regions  145 L,  145 ,  145 U may be removed by forming a second trench  141 . Forming the second trench  141  may be performed by a wet etching and/or a dry etching process. The gate electrodes  157 L,  157   m ,  157  and  157 U may be positioned at other stacks in the third direction from an upper surface of the substrate  100  and may be isolated from each other. 
     The gate electrodes  157 L,  157   m ,  157  and  157 U and the insulation patterns  120 La,  120   a  and  120 Ua stacked alternatingly may be defined as one stack structure. A plurality of stack structures extending in the second direction may be arranged on the substrate  100  spaced apart from each other in the first direction. 
     The gate electrodes  157 L,  157   m ,  157  and  157 U correspond to portions of the gate conductive layers  158  positioned in the recess regions  145 L,  145 ,  145 U, respectively. A lowermost pattern among the gate electrodes is a lower selection gate pattern  157 L, and an uppermost pattern may be an upper selection gate pattern  157 U. Cell gate patterns  157   m  and  157  may be provided between the lower selection gate pattern  157 L and the upper selection gate pattern  157 U. The cell gate patterns may include an uppermost cell gate pattern  157   m  and a cell gate pattern  157  thereunder. 
     A first impurity region  170  may be formed in the substrate  100  under a bottom surface of the second trench  141 . The first impurity region  170  may have a line shape extending in the second direction. The first impurity region  170  is a region doped with a second-type dopant. The first impurity region  170  may be formed by implanting second-type dopant ions into the substrate  100 . The uppermost insulation pattern  120 Ua may be used as an ion implantation mask. The data storage layer  150  positioned on the bottom surface of the second trench  141  may be used as an ion implantation buffer layer. 
     A drain region D may be formed at an upper portion of the channel structure  139 . The drain region D may be doped with the second-type dopant. A bottom surface of the drain region D may be higher than a top surface of the upper selection gate pattern  157 U. Alternatively, the bottom surface of the drain region D may have a height close to the upper surface of the upper selection gate pattern  157 U. The drain region D and the first impurity region  170  may be formed at the same time. Alternatively, the drain region D may be formed before forming the first impurity region  170 . As such, the drain region D may be formed before forming the second trench  141  and after forming the channel structure  139 . Alternatively, the drain region D may also be formed after forming the first impurity region  170 . 
     A device isolation pattern  175  filling the second trench  141  may be formed. Forming the device isolation pattern  175  may include forming a device isolation layer filling the second trench  141  and performing a planarization process on an upper surface of the data storage layer  150  using the uppermost insulation pattern  120 Ua as an etch stop layer. The device isolation pattern  175  may include an insulating material. For example, the device isolation pattern  175  may be formed of a high-density plasma oxide layer, a spin on glass (SOG) layer and/or a chemical vapor deposition (CVD) oxide layer, or the like. After forming the device isolation pattern  175 , the exposed data storage layer  150  may be etched such that the uppermost insulation pattern  120 Ua may be exposed. As such, the drain region D may be exposed. 
     Referring again to  FIG. 2 , a bit line BL, which is electrically connected to the drain region D, may be formed. The bit line BL may extend in the first direction. The bit line BL may be formed on the uppermost insulation pattern  120 Ua and the device isolation pattern  175 . Alternatively, an interlayer dielectric, which covers the uppermost insulation pattern  120 Ua and the device isolation pattern  175 , is formed, and then the bit line BL may be formed on the interlayer dielectric. As such, the bit line BL may be electrically connected to the drain region D via a contact plug penetrating the interlayer dielectric. 
     According to some embodiments, a semiconductor device having channel pattern regions with different shapes from each other may be formed. Also, the selection transistor region may have a channel region with large grain size. Therefore, the selection transistor region may secure a wide channel region and reduce resistance. 
       FIG. 13  is a perspective view of a semiconductor device according to some embodiments, and  FIG. 14  is an enlarged view of the area ‘B’ in  FIG. 13 . 
     A structure and a method of forming the semiconductor device illustrated in  FIGS. 13 and 14  may be similar to those illustrated in  FIGS. 2-12 . Therefore, for descriptive simplicity, the description related to the overlapping technical characteristics may be omitted. 
     Referring to  FIGS. 13 and 14 , a substrate  200  is provided. First material layers and second material layers including a material different from the first material layers, which are repeatedly and alternatingly stacked on the substrate  200 , may be provided. The first material layers are gate layers  210 U,  210   m ,  210  and  210 L, and the second material layers may be insulation layers  220 U,  220  and  220 L. The gate layers may include a lower selection gate layer  210 L, cell gate layers  210   m  and  210  and an upper selection gate layer  210 U. The cell gate layers may include an uppermost cell gate layer  210   m  and a cell gate layer  210  thereunder. The uppermost cell gate layer  210   m  may be a dummy gate layer. A buffer insulation layer  205  may be provided between the substrate  200  and the lower selection gate layer  210 L. The buffer insulation layer  205  may be a silicon oxide layer. The lower and upper selection gate layers  210 L and  210 U may be formed thicker than the cell gate layers  210   m  and  210 . The gate layers  210 U,  210   m ,  210  and  210 L and the insulation layers  220 U,  220  and  220 L may extend in a horizontal direction, for example, a y direction. Although only six of the gate layers  210 U,  210   m ,  210  and  210 L and the insulation layers  220 U,  220  and  220 L are illustrated, respectively, some layers are omitted for the simplicity of the description. Also, although one of each of the selection gate layers  210 U and  210 L are illustrated, a plurality thereof may be provided. 
     A first through region  225 , which extends from the substrate  200  by penetrating the gate layers  210 U,  210   m ,  210  and  210 L and the insulation layers  220 U,  220  and  220 L, may be provided. A blocking layer  253 , a charge storage layer  252  and a tunnel insulation layer  251  may be sequentially provided on a sidewall of the first through region  225 . A vertical channel structure  239  extending vertically from the substrate  200  may be provided in the first through region  225 . The vertical channel structure  239  may include a semiconductor pattern  246  and a buried pattern  256 . 
     The vertical channel structure  239  may include a first channel pattern G 1  and a second channel pattern G 2 . The first channel pattern G 1  may be formed at a lower portion of the first through region  225 , and the second channel pattern G 2  may be formed over the first channel pattern G 1 . The first channel pattern G 1  may include a first semiconductor region  291  provided at a lower portion and on a portion of an inner sidewall of the first through region  225 , and the buried pattern  256  may be provided in the first semiconductor region  291 . That is, the first channel pattern G 1  of the first vertical channel structure  239  may have a macaroni shape or a shell shape. Alternatively, the second channel pattern G 2  may include a second semiconductor region  292  completely filling a remaining portion of the first through region  225  which is partially filled by the first channel pattern G 1  That is, the second channel pattern G 2  of the first vertical channel structure  239  may have a shape even without including the buried pattern  256 . A grain size of the second semiconductor region  292  may be larger than a grain size of the first semiconductor region  291 . 
     A boundary between the first channel pattern G 1  and the second channel pattern G 2  may be provided between the uppermost cell gate layer  210   m  and the upper selection gate layer  210 U. That is, a top surface of the buried pattern  256  may be higher (e.g., closer to the second channel pattern G 2 ) than a top surface of the uppermost cell gate layer  210   m.    
     A third channel pattern G 3  may be provided between the first channel pattern G 1  and the second channel pattern G 2 . The third channel pattern G 3  may include a third semiconductor region  293  having a grain size which is larger than the grain size of the first semiconductor region  291  and is smaller than the grain size of the second semiconductor region  292 . The first through third semiconductor regions  291 - 293  may constitute the semiconductor pattern  246 . The semiconductor pattern  246  may have an intrinsic state. 
     A drain region D may be provided to the vertical channel structure  239  adjacent the uppermost insulation layer  220 Ua on the upper selection gate layer  210 U. Bit lines BL, which extend alongside in a direction (e.g., a first direction) crossing the gate layers  210 U,  210   m ,  210  and  210 L, and are electrically connected to the drain region D, may be provided. The bit lines BL may include a conductive material. 
       FIG. 15  illustrates a method of fabricating a semiconductor device according to some embodiments. Referring to  FIG. 15 , first material layers and second material layers including a material different from the first material layers may be repeatedly and alternatingly stacked on a substrate  200 . The first material layers may be gate layers  210 U,  210   m ,  210  and  210 L. The second material layers may be insulation layers  220 L,  220  and  220 U. The gate layers  210 U,  210   m ,  210  and  210 L, for example, may be formed of impurity-doped polycrystalline silicon or a metallic material. For example, the insulation layers  220 L,  220  and  220 U may be formed of a silicon oxide layer or a silicon nitride layer. 
     The gate layers  210 U,  210   m ,  210  and  210 L may include an upper selection gate layer  210 U, a lower selection gate layer  210 L and cell gate layers  210   m  and  210  between the upper selection gate layer  210 U and the lower selection gate layer  210 L. The cell gate layer may include an uppermost cell gate layer  210   m  and a cell gate layer  210  thereunder. The gate layers  210 U,  210   m ,  210  and  210 L may be formed with the same thickness. Alternatively, the upper and lower selection gate layers  210 U and  210 L may be formed thicker than the cell gate layers  210   m  and  210 . An uppermost insulation layer  220 U among the insulation layers  220 L,  220  and  220 U may be formed thicker than the insulation layers  220  and  220 L thereunder. 
     Before forming the gate layers  210 U,  210   m ,  210  and  210 L and the insulation layers  220 L,  220  and  220 U, a buffer insulation layer  205  may be formed on the substrate  200 . The gate layers  210 U,  210   m ,  210  and  210 L and the insulation layers  220 L,  220  and  220 U may be formed on the buffer insulation layer  205 . The lower selection gate layer  210 L may be formed directly on the buffer insulation layer  205 . The buffer insulation layer  205  may be formed of oxide, particularly, thermal oxide. 
     Referring to  FIGS. 14 and 16 , the buffer insulation layer  205 , the insulation layers  220 L,  220  and  220 U and the gate layers  210 U,  210   m ,  210  and  210 L are continuously patterned such that a first through region  225  exposing an upper surface of the substrate  200  may be formed. The first through region  225  may be formed using an anisotropic etching process. The first through region  225  may have a hole shape. A plurality of the first through regions  225  may be spaced apart from each other. 
     A data storage layer  250 , which covers a sidewall of the first through region  225 , may be formed. As described in  FIG. 14 , forming the data storage layer  250  may include forming a blocking layer  253 , a charge storage layer  252  and a tunnel insulation layer  251  on the sidewall of the first through region  225  in sequence. A preliminary data storage layer (not illustrated), which conformally covers an inner wall of the first through region  225  and the substrate  200 , may be formed, and a spacer  240 , which covers an inner sidewall of the preliminary data storage layer, may be formed. The preliminary data storage layer is etched using the spacer  240  as an etch mask such that the data storage layer  250  exposing the substrate  200  may be formed. The substrate  200  may be etched together with the data storage layer  250 . During an etching process for exposing the substrate  200 , the preliminary data storage layer, which is disposed on an upper surface of the uppermost insulation layer  220 U, is etched also, thereby exposing the upper surface of the uppermost insulation layer  220 U. The spacer  240  may be formed of amorphous or polycrystalline silicon. 
     Referring to  FIG. 17 , a first preliminary semiconductor layer  242  may be formed along a sidewall and a lower portion of the first through region  225 . The first preliminary semiconductor layer  242  may be a silicon layer. A buried layer  255  filling the first through region  225  may be formed on the first preliminary semiconductor layer  242 . The first preliminary semiconductor layer  242  and the buried layer  255  may be formed by CVD or ALD. After the first preliminary semiconductor layer  242  and the buried layer  255  are deposited, the uppermost insulation layer  220 U may be exposed by a planarization process. 
     Referring to  FIG. 18 , a first semiconductor layer  244  may be formed by performing a first heat treatment process on the first preliminary semiconductor layer  242  and the spacer  240 . The first preliminary semiconductor layer  242  and the spacer  240  are recrystallized by the first heat treatment process, thereby enabling a relatively small grain size like the first channel pattern G 1  in  FIG. 14 . The first heat treatment process may be a solid phase crystallization process. 
     A portion of the buried layer  255  is removed such that the buried pattern  256  is formed and a second through region  226  may be formed. The removal of the buried layer  255  may be performed with a solution having an etch selectivity with respect to the buried layer  255 . A portion of the first semiconductor layer  244  may be etched during forming the second through region  226 . A bottom surface of the second through region  226  (and/or a top surface of the buried pattern  256 ) may be provided between the uppermost cell gate layer  210   m  and the upper selection gate layer  210 U. 
     Referring to  FIG. 19 , a second preliminary semiconductor layer  245  filling the second through region  226  may be formed. The second preliminary semiconductor layer  245  may be formed with the same method as the first preliminary semiconductor layer  242 . 
     Referring to  FIGS. 14 and 20 , a second heat treatment process may be performed on the second preliminary semiconductor layer  245  of  FIG. 19 . The second heat treatment process may be performed on a portion of the first semiconductor layer  244  constituting a sidewall of the second through region  226 . As a result of the second heat treatment, the second channel pattern G 2  in  FIG. 14  may be formed. The second channel pattern G 2  includes a second semiconductor region  292 . The first channel pattern G 1  includes a first semiconductor region  291  and a buried pattern  256 . The second semiconductor region  292  may have a larger grain size than the first semiconductor region  291  due to recrystallization by the second heat treatment process. The second heat treatment process may be a laser heat treatment process. A third channel pattern G 3  including a third semiconductor region  293 , which has a grain size larger than a grain size of the first semiconductor region  291  and smaller than a grain size of the second semiconductor region  292 , may be provided between the first channel pattern G 1  and the second channel pattern G 2 . The third channel pattern G 3  may be formed by recrystallization that has partially progressed during the second heat treatment process. The first through third semiconductor regions  291 - 293  constitute a semiconductor pattern  246 , and the semiconductor pattern  246  and the buried pattern  256  may constitute a vertical channel structure  239 . 
     A drain region D may be formed at an upper portion of the vertical channel structure  239 . The drain region D may be doped with a second-type dopant. A bottom surface of the drain region D may be higher than a top surface of the upper selection gate layer  210 U. Alternatively, the bottom surface of the drain region D may have a height close to the top surface of the upper selection gate layer  210 U. 
     Referring again to  FIG. 13 , a bit line BL, which is electrically connected to the drain region D, may be formed. The bit line BL may extend in the first direction (x-axis direction). The bit line BL may be formed on the uppermost insulation layer  220 U. Alternatively, an interlayer dielectric covering the uppermost insulation layer  220 U may be formed, and then the bit line BL may be formed on the interlayer dielectric. As such, the bit line BL may be electrically connected to the drain region D via a contact plug penetrating the interlayer dielectric. 
     According to some embodiments, semiconductor device channel pattern regions with different shapes and grain sizes from each other may be formed. Also, the selection transistor region may have a channel region with large grain size. Therefore, the selection transistor region may secure a wide channel region and reduce resistance. 
       FIG. 21  is a perspective view of a semiconductor device according to some embodiments, and  FIG. 22  is an enlarged view of the area ‘C’ in  FIG. 21 . 
     A structure and a method of forming the semiconductor device illustrated in  FIGS. 21 and 22  according to some embodiments are similar to those of  FIGS. 2-12 . Therefore, for descriptive simplicity, the description related to the overlapping technical characteristics may be omitted. 
     Referring to  FIGS. 21 and 22 , first material layers and second material layers including a material different from the first material layers, which are repeatedly and alternatingly stacked on the substrate  100 , may be provided. The first material layers are gate patterns  157 U,  157   n ,  157  and  157 L, and the second material layers may be insulation patterns  120 Ua,  120   a  and  120 La. The gate patterns may include a lower selection gate pattern  157 L, cell gate patterns  157   n  and  157  and an upper selection gate pattern  157 U. The cell gate patterns may include a lowermost cell gate pattern  157   n  and a cell gate pattern  157  thereabove. The insulation patterns may include an uppermost insulation pattern  120 Ua, a lowermost insulation pattern  120 La and an insulation pattern  120   a  between the uppermost and lowermost insulation patterns  120 Ua and  120 La. A buffer insulation layer  105  may be provided between the substrate  100  and the lower selection gate pattern  157 L. 
     A channel structure  139  extending vertically from the substrate  100  is provided. The channel structure  139  may include a first channel pattern G 1  in a first through region  127  which penetrates the lower selection gate pattern  157 L and the lowermost insulation pattern  120 La. The channel structure  139  may include a second channel pattern G 2  in a second through region  128  which penetrates the upper selection gate pattern and the cell gate patterns  157 U,  157  and  157   n  and the uppermost insulation pattern and insulation patterns  120 Ua and  120   a . The first channel pattern G 1  may include a first semiconductor layer  182  filling the first through region  127 . The first semiconductor layer  182  may have a larger grain size than a second semiconductor layer  184 . The second channel pattern G 2  may include the second semiconductor layer  184  provided on sidewalls and a lower portion of the second through region  128 , and a buried pattern  156  filling the second through region  128 . That is, the second channel pattern G 2  of the channel structure  139  may have a macaroni shape or a shell shape. A bottom surface of the buried pattern  156  may be lower (e.g., closer to the first channel pattern G 1 ) than a bottom surface of the lowermost cell gate pattern  157   n . Alternatively, the first channel pattern G 1  may include the second semiconductor layer  184  filling the first through region  127 . That is, the second channel pattern G 2  of the channel structure  139  may have a shape even without including the buried pattern  156 . 
     The second semiconductor layer  184  may have a grain size smaller than a grain size of the first semiconductor layer  182 . A third channel pattern G 3  may be provided between the first channel pattern G 1  and the second channel pattern G 2 . The third channel pattern G 3  may have a structure where the first semiconductor layer  182  and the second semiconductor layer  184  are overlapped. The third channel pattern G 3  may be provided adjacent the lowermost insulation pattern  120 La. A bottom surface of the second channel pattern G 2  may be positioned between the lower selection gate pattern  157 L and the lowermost cell gate pattern  157   n . The first and second semiconductor layers  182  and  184  may have an intrinsic state. 
     The channel structures  139  arranged in the first direction constitute one row, and the channel structures  139  arranged in the second direction constitute one column. A plurality of rows and a plurality of columns may be arranged on the substrate  100 . A device isolation pattern  175  may be arranged between a pair of adjacent ones of the rows. That is, the device isolation pattern  175  may extend in a second direction. The device isolation pattern  175  may include an insulating material. A first impurity region  170  may be formed in the substrate  100  under a bottom surface of the device isolation pattern  175 . The first impurity region  170  may have a line shape extending in the second direction (y-axis direction). The first impurity region  170  may be a region doped with a second-type dopant. 
     A data storage layer  150  may be provided between the gate patterns  157 U,  157   n ,  157  and  157 L and the channel structure  139 . The data storage layer  150  may include the charge storage layer  152  configured to store charges. In addition, the data storage layer  150  may further include a tunnel insulation layer  151  between the charge storage layer  152  and the channel structure  139 , and a blocking layer  153  between the charge storage layer  152  and the gate patterns  157 U,  157   n ,  157  and  157 L. The charge storage layer  152  may be formed of a material having traps which store charges. 
     A drain region D may be provided to the channel structure  139  adjacent the uppermost insulation pattern  120 Ua on the upper selection gate pattern  157 U. Bit lines BL, which extend in a direction crossing the gate patterns  157 U,  157   n ,  157  and  157 L and are electrically connected to the drain region D, are provided. The bit lines BL may include a conductive material. 
     According to some embodiments, a selection transistor region having an active region wider than an active region of a cell region is provided. Also, the selection transistor region may have a channel region with a large grain size. Therefore, the selection transistor region may secure a wide channel region and reduce resistance. 
       FIG. 23  illustrates a method of fabricating a semiconductor device according to some embodiments. Referring to  FIG. 23 , a substrate  100  is prepared. A lower selection gate sacrificial layer  110 L and a lowermost insulation layer  120 L may be sequentially stacked on the substrate  100 . A buffer insulation layer  105  may be provided between the lower selection gate sacrificial layer  110 L and the substrate  100 . Referring to  FIG. 24 , a first through region  127  may be formed at portions of the lower selection gate sacrificial layer  110 L and the lowermost insulation layer  120 L. The first through region  127  may have a shape which gradually becomes narrower as it extends downward (e.g., closer to the substrate  100 ). A first preliminary semiconductor layer  181  filling the first through region  127  may be formed. The first preliminary semiconductor layer  181  may be a silicon layer. 
     Referring to  FIG. 25 , a first semiconductor layer  182  may be formed by performing a first heat treatment process on the first preliminary semiconductor layer  181 . The first semiconductor layer  182  may have a larger grain size than a second semiconductor layer. The first heat treatment process may be a laser heat treatment process. A portion of the first semiconductor layer  182  may constitute the first channel pattern G 1  in  FIG. 22 . 
     Referring to  FIG. 26 , sacrificial layers  110  and  110 U and insulation layers  120  and  120 U may be alternatingly and repeatedly stacked on the lowermost insulation layer  120 L. The sacrificial layers may include an upper selection gate sacrificial layer  110 U and sacrificial layers  110  between the lower selection gate sacrificial layer  110 L and the upper selection gate sacrificial layer  110 U. The insulation layers may include an uppermost layer  120 U and insulation layers  120  between the uppermost insulation layer  120 U and the lowermost insulation layer  120 L. The upper selection gate sacrificial layer  110 U occupies a space where an upper selection gate pattern may be formed, and the sacrificial layers  110  may occupy a space where cell gate patterns are formed. The lower selection gate sacrificial layer  110 L may occupy a space where the lower selection gate pattern is formed. 
     The sacrificial layers  110 U and  110  and the insulation layers  120 U and  120  are continuously patterned such that a second through region  128  exposing an upper portion of the first semiconductor layer  182  may be formed. The second through region  128  may have a shape which gradually becomes narrower as it extends downward (e.g., toward the substrate  100 ). During the patterning, the upper portion of the first semiconductor layer  182  may be etched. A bottom surface of the second through region  128  may be higher (e.g., farther from the substrate) than the lower selection gate sacrificial layer  110 L. A bottom surface of the second through region  128  may be lower (e.g., closer to the substrate) than bottom surfaces of the sacrificial layers  110 . 
     Referring to  FIG. 27 , a second preliminary semiconductor layer  183  may be formed on the bottom surface and sidewalls of the second through region  128 . The second preliminary semiconductor layer  183  may be formed with the same method as the first preliminary semiconductor layer  181 . A buried pattern  156  filling the second through region  128  may be formed on the second preliminary semiconductor layer  183 . 
     Referring to  FIGS. 22 and 28 , a second semiconductor layer  184  may be formed by performing a second heat treatment process on the second preliminary semiconductor layer  183 . As illustrated in  FIG. 22 , the second semiconductor layer  184  may have a smaller grain size than the first semiconductor layer  182 . The second heat treatment process may be a solid phase crystallization process. The second semiconductor layer  184  and the buried pattern  156  may constitute a second channel pattern G 2 . A third channel pattern G 3  may be a portion where the first semiconductor layer  182  and the second semiconductor layer  184  overlap each other. The first and second semiconductor layers  182  and  184  and the buried pattern  156  may constitute a channel structure  139 . 
     The insulation layers  120 U,  120  and  120 L and the sacrificial layers  110 U,  110  and  110 L are continuously patterned such that a first trench  140  may be formed. The first trench  140  defines the sacrificial patterns  110 La,  110   a  and  110 Ua and the insulation patterns  120 La,  120   a  and  120 Ua which are alternatingly and repeatedly stacked. Forming the first trench  140  may be performed by an anisotropic etching process. The first trench  140  may extend in the second direction. Therefore, the sacrificial patterns  110 La,  110   a  and  110 Ua and the insulation patterns  120 La,  120   a  and  120 Ua may have also line shapes extending alongside in the second direction. The sacrificial patterns  110 La,  110   a  and  110 Ua and the insulation patterns  120 La,  120   a  and  120 Ua are exposed at a sidewall of the first trench  140 . The substrate  100  may be exposed at a bottom of the first trench  140 . 
     Referring to  FIG. 29 , the sacrificial patterns  110 La,  110   a  and  110 Ua exposed in the first trench  140  are removed by performing a selective etching process such that recess regions  145 L,  145 ,  145 U may be formed. The selective etching process may be an isotropic etching process. The selective etching process may be performed by a wet etching and/or an isotropic dry etching. An etch rate of the sacrificial patterns  110 La,  110   a  and  110 Ua by the selective etching process may be larger/faster than etch rates of the insulation patterns  120 La,  120   a  and  120 Ua, the buffer insulation layer  105  and the channel structure  139 . Therefore, after the performing of the selective etching process, the insulation patterns  120 La,  120   a  and  120 Ua, the buffer insulation layer  105  and the channel structure  139  may remain. 
     Referring to  FIGS. 21 and 30 , after the recess regions  145 L,  145 ,  145 U are formed, a data storage layer  150  may be formed on the substrate  100 . Forming the data storage layer  150  may include forming a tunnel insulation layer  151 , a charge storage layer  152  and a blocking layer  153  in sequence. After the data storage layer  150  is formed, the gate conductive layer  158  may be disposed on the substrate  100 . The gate conductive layer  158  may fill the recess regions  145 L,  145 ,  145 U. The gate conductive layer  158  may fill at least a portion of the first trench  140 . The gate conductive layer  158  may be electrically isolated from the channel structure  139  and the substrate  100  by the data storage layer  150 . 
     Referring to  FIG. 31 , portions of the gate conductive layer  158  positioned outside the recess regions  145 L,  145 ,  145 U are removed to form gate electrodes  157 L,  157   n ,  157  and  157 U in the recess regions  145 L,  145 ,  145 U. The gate conductive layer  158  positioned outside the recess regions  145 L,  145 ,  145 U may be removed by forming a second trench  141 . Forming the second trench  141  may be performed by a wet etching and/or a dry etching process. The gate electrodes  157 L,  157   n ,  157  and  157 U may have a structure isolated from each other. A lowermost pattern among the gate electrodes is a lower selection gate pattern  157 L, and an uppermost pattern may be an upper selection gate pattern  157 U. Cell gate patterns  157   n  and  157  may be provided between the lower selection gate pattern  157 L and the upper selection gate pattern  157 U. The cell gate patterns may include a lowermost cell gate pattern  157   n  and a cell gate pattern  157  thereabove. 
     A first impurity region  170  may be formed in the substrate  100  under a bottom surface of the second trench  141 . A drain region D may be formed at an upper portion of the channel structure  139 . The drain region D may be doped with the second-type dopant. A device isolation pattern  175  filling the second trench  141  may be formed. 
     Referring again to  FIG. 21 , bit line BL, which is electrically connected to the drain region D, may be formed. The bit line BL may extend in the first direction. The bit line BL may be formed on the uppermost insulation pattern  120 Ua and the device isolation pattern  175 . 
       FIG. 32  is a perspective view of a semiconductor device according to some embodiments, and  FIG. 33  is an enlarged view of the area ‘E’ in  FIG. 32 . 
     A structure and a forming method of the semiconductor devices in  FIGS. 32 and 33  may be similar to those illustrated in  FIGS. 21-31 . Therefore, for descriptive simplicity, the description related to the overlapping technical characteristics may be omitted. 
     Referring to  FIGS. 32 and 33 , first material layers and second material layers including a material different from the first material layers, which are repeatedly and alternatingly stacked on the substrate  100 , may be provided. The first material layers are gate patterns  157 U,  157   n ,  157  and  157 L, and the second material layers may be insulation patterns  120 Ua,  120   a  and  120 La. The gate patterns may include a lower selection gate pattern  157 L, cell gate patterns  157   n  and  157  and an upper selection gate pattern  157 U. The cell gate patterns may include a lowermost cell gate pattern  157   n  and a cell gate pattern  157  thereabove. The insulation patterns may include an uppermost insulation pattern  120 Ua, a lowermost insulation pattern  120 La and an insulation pattern  120   a  between the uppermost and lowermost insulation patterns  120 Ua and  120 La. A buffer insulation layer  105  may be provided between the substrate  100  and the lower selection gate pattern  157 L. 
     A channel structure  139  extending vertically from the substrate  100  is provided. The channel structure  139  may include a first channel pattern G 1  in a first through region  127  which penetrates the lower selection gate pattern  157 L and the lowermost insulation pattern  120 La. The channel structure  139  may include a second channel pattern G 2  in a second through region  128  which penetrates the upper selection gate pattern and the cell gate patterns  157 U,  157  and  157   n  and the uppermost insulation pattern and insulation patterns  120 Ua and  120   a . The first channel pattern G 1  may include a first semiconductor layer  182  filling the first through region  127 . The second channel pattern G 2  may include a second semiconductor layer  184  filling the second through region  128 . 
     A third channel pattern G 3  may be provided between the first channel pattern G 1  and the second channel pattern G 2 . The third channel pattern G 3  may be a structure where the first semiconductor layer  182  and the second semiconductor layer  184  are overlapped. The third channel pattern G 3  may be formed adjacent the lowermost insulation pattern  120 La. A bottom surface of the second semiconductor layer  184  may be positioned between the lower selection gate pattern  157 L and the lowermost cell gate pattern  157   n . A data storage layer  150  may be provided between the gate patterns  157 U,  157   n ,  157  and  157 L and the channel structure  139 . 
       FIG. 34  illustrates a method of forming a semiconductor device according to some embodiments. Referring to  FIG. 34 , a substrate  100  is prepared. A lower selection gate sacrificial layer  110 L and a lowermost insulation layer  120 L may be sequentially stacked on the substrate  100 . A buffer insulation layer  105  may be provided between the lower selection gate sacrificial layer  110 L and the substrate  100 . Referring to  FIG. 35 , a first through region  127  may be formed at the lower selection gate sacrificial layer  110 L and the lowermost insulation layer  120 L. The first through region  127  may have a round shape, an oval shape or a polygonal shape in plan view. A first preliminary semiconductor layer  181  filling the first through region  127  may be formed. A third trench  143 , which penetrates the lower selection gate sacrificial layer  110 L and the lowermost insulation layer  120 L, may be formed between the first through regions  127 . The third trench  143  may have a shape extending in the second direction. The third trench  143  may be formed together with the first through region  127 . A trench sacrificial layer  173  may be formed on a bottom and a sidewall of the third trench  143 . The trench sacrificial layer  173  may be formed with the same material as the lower selection gate sacrificial layer  110 L. A trench insulation layer  171  filling the third trench  143  may be formed on the trench sacrificial layer  173 . The trench insulation layer  171  may be formed with the same material as the lowermost insulation layer  120 L. Referring to  FIG. 36 , a first semiconductor layer  182  may be formed by performing a first heat treatment process on the first preliminary semiconductor layer  181 . The first heat treatment process may be a laser heat treatment process. 
     Referring to  FIG. 37 , sacrificial layers  110  and  110 U and insulation layers  120  and  120 U may be alternatingly and repeatedly stacked on the lowermost insulation layer  120 L. The sacrificial layers may include the upper selection gate sacrificial layer  110 U and the sacrificial layers  110  between the lower selection gate sacrificial layer  110 L and the upper selection gate sacrificial layer  110 U. The insulation layers may include the uppermost insulation layer  120 U and the insulation layers  120  between the uppermost insulation layer  120 U and the lowermost insulation layer  120 L. 
     The sacrificial layers  110 U and  110  and the insulation layers  120 U and  120  are continuously patterned such that a second through region  128  exposing an upper portion of the first semiconductor layer  182  may be formed. During the patterning, the upper portion of the first semiconductor layer  182  may be etched. The second through region  128  may have a round shape, an oval shape or a polygonal shape in plan view. A bottom surface of the second through region  128  may be higher (e.g., farther from the substrate  100 ) than an upper surface of the lower selection gate sacrificial layer  110 L. The bottom surface of the second through region  128  may be lower (e.g., closer to the substrate  100 ) than a bottom surface of the sacrificial layers  110 . 
     Referring to  FIG. 38 , a second preliminary semiconductor layer  183  filling the second through region  128  may be formed. The second preliminary semiconductor layer  183  may be formed with the same method as the first preliminary semiconductor layer  181 . 
     Referring to  FIG. 39 , a second semiconductor layer  184  may be formed by performing a second heat treatment process on the second preliminary semiconductor layer  183 . The second heat treatment process may be a laser heat treatment or a solid phase crystallization process. The first and second semiconductor layers  182  and  184  may constitute a channel structure  139 . 
     The insulation layers  120 U and  120  and the sacrificial layers  110 U and  110  are continuously patterned such that a first trench  140  may be formed. A forming process of the first trench  140  may include a removal process of the trench insulation layer  171 . The removal process of the trench insulation layer  171  may be a wet etching process. The formation of the first trench  140  may be performed together with the formation of the second through region  128 . The first trench  140  defines sacrificial patterns  110 La,  110   a  and  110 Ua and insulation patterns  120 La,  120   a  and  120 Ua which are alternatingly and repeatedly stacked. Forming the first trench  140  may be performed by an anisotropic etching process. The trench sacrificial layer  173  may be exposed at a bottom of the first trench  140 . 
     Referring to  FIG. 40 , the sacrificial patterns  110 La,  110   a  and  110 Ua and the trench sacrificial layer  173 , which are exposed in the first trench  140 , are removed by performing a selective etching process such that recess regions  145 L,  145 ,  145 U may be formed. The selective etching process may be an isotropic etching process. The selective etching process may be performed by a wet etching and/or an isotropic dry etching, or the like. Etch rates of the sacrificial patterns  110 La,  110   a  and  110 Ua and the trench sacrificial layer  173  by the selective etching process may be larger/faster than etch rates of the insulation patterns  120 La,  120   a  and  120 Ua, the buffer insulation layer  105  and the channel structure  139 . Therefore, after the performing of the selective etching process, the insulation patterns  120 La,  120   a  and  120 Ua, the buffer insulation layer  105  and the channel structure  139  may remain. 
     Referring to  FIGS. 33 and 41 , after the recess regions  145 L,  145 ,  145 U are formed, a data storage layer  150  may be formed on the substrate  100 . Forming the data storage layer  150  may include forming a tunnel insulation layer  151 , a charge storage layer  152  and a blocking layer  153  in sequence. After the data storage layer  150  is formed, the gate conductive layer  158  may be disposed on the substrate  100 . The gate conductive layer  158  may be electrically isolated from the channel structure  139  and the substrate  100  by the data storage layer  150 . 
     Referring to  FIG. 42 , portions of the gate conductive layer  158  positioned outside of the recess regions  145 L,  145 ,  145 U are removed to form gate electrodes  157 L,  157   n ,  157  and  157 U in the recess regions  145 L,  145 ,  145 U. The portions of the gate conductive layer  158  outside of the recess regions  145 L,  145 ,  145 U may be removed by forming a second trench  141 . A first impurity region  170  may be formed in the substrate  100  under a bottom surface of the second trench  141 . A drain region D may be formed at a top portion of the channel structure  139 . A device isolation pattern  175  may be formed in the second trench  141 . 
     Referring again to  FIG. 32 , bit line BL, which is electrically connected to the drain region D, may be formed. The bit line BL may extend in the first direction. The bit line BL may be formed on the uppermost insulation pattern  120 Ua and the device isolation pattern  175 . 
       FIG. 43  is a perspective view of a semiconductor device according to some embodiments, and  FIG. 44  is an enlarged view of the area ‘F’ in  FIG. 43 . 
     A portion of a structure and a forming method of  FIGS. 43 and 44  are similar to those of  FIGS. 13-20 . Therefore, for the conciseness of the description, the description related to the overlapping technical characteristics may be omitted. 
     Referring to  FIGS. 43 and 44 , a substrate  200  is provided. First material layers and second material layers including a material different from the first material layers, which are repeatedly and alternatingly stacked on the substrate  200 , may be provided. The first material layers are gate layers  210 U,  210   n ,  210  and  210 L, and the second material layers may be insulation layers  220 U,  220  and  220 L. The gate layers may include a lower selection gate layer  210 L, cell gate layers  210   n  and  210  and an upper selection gate layer  210 U. The cell gate layers may include a lowermost cell gate layer  210   n  and a cell gate layer  210  thereabove. The uppermost cell gate layer  210   n  may be a dummy gate layer. A buffer insulation layer  205  may be provided between the substrate  200  and the lower selection gate layer  210 L. 
     A vertical channel structure  239  extending vertically from the substrate  200  may be provided. The vertical channel structure  239  may include a first channel pattern G 1  in a first through region  227  which penetrates the lower selection gate layer  210 L and the lowermost insulation layer  220 L. The first channel pattern G 1  may include a first semiconductor layer  282  filling the first through region  227 . A lower tunnel insulation layer  254  may be provided between an inner sidewall of the first through region  227  and the first semiconductor layer  282 . The lower tunnel insulation layer  254  may be an oxide layer. 
     The vertical channel structure  239  may include a second channel pattern G 2  in a second through region  228  which penetrates the upper selection gate layer and the cell gate layers  210 U,  210  and  210   n  and the uppermost insulation layer and the insulation layer  220 U and  220 . The second channel pattern G 2  may include a second semiconductor layer  284  filling the second through region  228 . A data storage layer  250  may be provided between inner sidewalls of the second through region  228  and the second semiconductor layer  284 . The data storage layer  250  may include a blocking layer  253 , a charge storage layer  252  and a tunnel insulation layer  251  which are stacked in sequence. 
     A third channel pattern G 3  may be provided between the first channel pattern G 1  and the second channel pattern G 2 . The third channel pattern G 3  may be a region in which the first semiconductor layer  282  and the second semiconductor layer  284  overlap. The third channel pattern G 3  may be disposed adjacent the lowermost insulation pattern  220 L. A bottom surface of the second semiconductor layer  284  may be positioned between the lower selection gate layer  210 L and the lowermost cell gate layer  210   n . Although it was illustrated for convenience only that the data storage layer  250  and the lower tunnel insulation layer  254  are aligned, alternatively, the first semiconductor layer  282  may be provided between the data storage layer  250  and the lower tunnel insulation layer  254 . 
       FIG. 45  illustrates a method of fabricating a semiconductor device according to some embodiments. Referring to  FIG. 45 , a lower selection gate layer  210 L and a lowermost insulation layer  220 L may be sequentially stacked on a substrate  200 . A buffer insulation layer  205  may be provided between the lower selection gate layer  210 L and the substrate  200 . 
     Referring to  FIG. 46 , a first through region  227  may be formed by continuously patterning the lower selection gate layer  210 L and the lowermost insulation layer  220 L. A lower tunnel insulation layer  254  may be formed on a sidewall of the first through region  227 . An insulation layer (not illustrated) is formed in the first through region  227 , and then a first spacer  281  is formed on a sidewall of the insulation layer. Then, the lower tunnel insulation layer  254  may be formed by etching the insulation layer using the first spacer  281  as an etch mask. The first spacer  281  may be formed of amorphous or polycrystalline silicon. 
     Referring to  FIG. 47 , a first semiconductor layer  282  filling the first through region  227  may be formed. The first semiconductor layer  282  may be formed by forming a first preliminary semiconductor layer (not illustrated), and then performing a first heat treatment process on the first preliminary semiconductor layer and the first spacer  281 . The first heat treatment process may be a laser heat treatment process. 
     Referring to  FIG. 48 , gate layers  210   n ,  210  and  210 U and insulation layers  220  and  220 U may be formed repeatedly and alternatingly on the lowermost insulation layer  220 L. A second through region  228 , which exposes an upper portion of the first semiconductor layer  282 , may be formed by patterning the gate layers  210   n ,  210  and  210 U and the insulation layers  220  and  220 U. During the forming of the second through region  228 , the upper portion of the first semiconductor layer  282  may be etched. A data storage layer  250  may be formed on sidewalls of the second through region  228 . The data storage layer  250  may be formed by forming a preliminary data storage layer in the second through region  228 , and then etching using a second spacer  283  as an etch mask. The second spacer  283  may be formed of amorphous or polycrystalline silicon. 
     Referring to  FIG. 49 , a second semiconductor layer  284  filling the second through region  228  may be formed. The second semiconductor layer  284  may be formed by forming a second preliminary semiconductor layer (not illustrated) filling the second through region  228 , and then performing a second heat treatment on the second preliminary semiconductor layer and the second spacer  283 . The first semiconductor layer  282  and the second semiconductor layer  284  may constitute a vertical channel structure  239 . A drain region D may be formed at a top portion of the vertical channel structure  239 . 
       FIG. 50  is a perspective view of a semiconductor device according to some embodiments, and  FIG. 51  is an enlarged view of a channel structure in  FIG. 50 . 
     Referring to  FIGS. 50 and 51 , a stack structure is provided on a substrate  100 . The stack structure may include gate patterns and insulation patterns which are repeatedly and alternatingly stacked on the substrate  100 . The gate patterns may include a lower selection gate pattern  157 L, cell gate patterns  157   m  and  157 , and an upper selection gate pattern  157 U. The cell gate patterns may include an uppermost cell gate pattern  157   m  and the cell gate patterns  157  therebelow. A buffer insulation layer  105  may be provided between the substrate  100  and the lower selection gate pattern  157 L. The insulation patterns may include an uppermost insulation pattern  120 Ua, a lowermost insulation pattern  120 La, and intermediate insulation patterns  120   a  between the uppermost insulation pattern  120 Ua and the lowermost insulation pattern  120 La. 
     Channel structures  139 , which extend from the substrate  100  to penetrate the gate patterns  157 U,  157   m ,  157  and  157 L and the insulation patterns  120 Ua,  120   a  and  120 La, may be provided. The channel structures  139  may be provided in first through regions  125  penetrating the gate patterns  157 U,  157   m ,  157  and  157 L and the insulation patterns  120 Ua,  120   a  and  120 La. 
     The channel structures  139  may include a first region P 1  including a first semiconductor layer  132 , and a second region P 2  including a second semiconductor layer  133 . The first region P 1  may be an active region of the cell gate patterns  157   m  and  157  and the lower selection gate pattern  157 L, and the second region P 2  may be an active region of the upper selection gate pattern  157 U. The second region P 2  may be provided on the first region P 1 . A boundary between the first region P 1  and the second region P 2  may be provided between the upper selection gate pattern  157 U and the uppermost cell gate pattern  157   m . The second region P 2  may be adjacent the upper selection gate pattern  157 U, and the first region P 1  may be adjacent the cell gate patterns  157   m  and  157 . That is, when the upper selection gate pattern  157 U is a gate electrode of a string selection transistor, a portion of the second region P 2  may be a channel region of the string selection transistor. When the cell gate patterns  157   m  and  157  are gate electrodes of memory cell transistors, a portion of the first region P 1  may be a channel region of the memory cell transistors. 
     A grain size of the second region P 2  may be larger than that of the first region P 1 . For example, grains of the second region P 2  may have longer lengths in a direction (z direction) perpendicular to a surface of the substrate  100  (e.g., a top surface of the substrate  100 ) than widths in a direction (x direction or y direction) parallel to the surface of the substrate  100 . For example, aspect ratios of the grains in the second region P 2  may be about 2:100. For example, the lengths of the grains in the second region P 2  in the z direction may be greater than a thickness of the upper selection gate pattern  157 U. That is, the string selection transistor may have a channel region with a relatively larger grain size than the memory cell transistors. Therefore, the area of grain boundaries in the channel region of the string selection transistor may be reduced. Accordingly, electrical characteristics of a semiconductor device, such as a leakage current generated by grain boundaries, may be improved. 
     The channel structures  139  may further include a buried pattern  156  surrounded by the first region P 1 . For example, lower portions of the channel structures  139  may have a macaroni shape or a shell shape in which the buried pattern  156  is filled in the semiconductor pattern  136  formed along lower surfaces and inner walls of the first through regions  125 . The buried pattern  156  may be spaced apart from the substrate  100  by means of the semiconductor pattern  136 . Alternatively, upper portions of the channel structures  139  may not include the buried pattern  156 . For example, the upper portions of the channel structures  139  may be regions in which the semiconductor patterns  136  are completely filled in the first through regions  125 . Therefore, the string selection transistor may secure a relatively wider channel region than the memory cell transistors. 
     An upper surface of the buried pattern  156  may be provided between the upper selection gate pattern  157 U and the uppermost cell gate pattern  157   m . For example, the buried pattern  156  may include at least one of a silicon oxide layer or a silicon nitride layer. The semiconductor pattern  136  may include at least one of silicon having a first conductive type or an intrinsic state, or silicon-germanium. 
     The channel structures  139  arranged in the x direction constitute one row, and the channel structures  139  arranged in the y direction constitute one column. A plurality of rows and a plurality of columns may be arranged on the substrate  100 . A device isolation pattern  175  may be arranged between a pair of adjacent ones of the rows. That is, the device isolation pattern  175  may extend in the y direction. The device isolation pattern  175  may include an insulating material. For example, the device isolation pattern  175  may be formed of a high-density plasma oxide layer, a spin on glass (SOG) layer and/or a chemical vapor deposition (CVD) oxide layer, etc. A first impurity region  170  may be formed in the substrate  100  under the device isolation pattern  175 . For example, the first impurity region  170  may have a line shape extending in the y direction. The first impurity region  170  may be a region doped with a second conductive type impurity. The second conductive type may be a conductive type different from the first conductive type. A data storage layer  150  may be provided between the gate patterns  157 U,  157   m ,  157  and  157 L and the channel structures  139 . 
     A second impurity region  198  may be provided in an upper portion of the semiconductor pattern  136  adjacent the uppermost insulation pattern  120 Ua. The second impurity region  198  may be an impurity region having the same conductive type as the first impurity region  170 . Bit lines BL may extend in a direction (e.g., x direction) crossing the gate patterns  157 U,  157   m ,  157  and  157 L and may be electrically connected to the second impurity region  198 . The bit lines BL may be connected to the channel structures  139  through contact plugs  199 . The bit lines BL may include at least one of metal, conductive metal nitride, or a doped semiconductor material. 
     According to some embodiments, the selection transistor may have a channel region with a relatively larger grain size than the memory cell transistors. Therefore, increases in leakage current due to the grain boundaries may be reduced/mitigated. Also, since the selection transistor may secure a relatively wider channel region than the memory cell transistors, channel resistance may be reduced. 
       FIGS. 52 through 62  are cross-sectional views and upper surface views illustrating a method of fabricating a semiconductor device according to some embodiments. 
     Referring to  FIG. 52 , a substrate  100  is prepared. The substrate  100  may be a semiconductor substrate. For example, the substrate  100  may be a silicon substrate, a germanium substrate, a silicon-germanium substrate, or a compound semiconductor substrate. For example, the substrate  100  may be doped with a first conductive type impurity. 
     A stack structure, in which first material layers and second material layers are repeatedly and alternatingly stacked, may be provided on the substrate  100 . The second material layers may include a material different from the first material layers. For example, the first material layers may be sacrificial layers  110 L,  110   m ,  110  and  110 U. The second material layers may be insulation layers  120 L,  120  and  120 U. The sacrificial layers  110 L,  110   m ,  110  and  110 U may be formed of a material having an etch selectivity with respect to the insulation layers  120 L,  120  and  120 U. Before forming the sacrificial layers  110 L,  110   m ,  110  and  110 U and the insulation layers  120 L,  120  and  120 U, a buffer insulation layer  105  may be formed on the substrate  100 . 
     The buffer insulation layer  105 , the insulation layers  120 L,  120  and  120 U and the sacrificial layers  110 L,  110   m ,  110  and  110 U are continuously patterned such that first through regions  125  exposing the substrate  100  may be formed. The first through regions  125  may be formed by using an anisotropic etching process. During formation of the first through regions  125 , an upper portion of the substrate  100  may be etched as a result of over-etching. 
     Referring to  FIG. 53 , preliminary channel structures may be formed in the first through regions  125 . Forming the preliminary channel structures may include forming first preliminary semiconductor layers  131  along sidewalls and lower portions of the first through regions  125 . The first preliminary semiconductor layer  131  may be a silicon layer. The first preliminary semiconductor layers  131  may not completely fill the first through regions  125 . A buried layer  155  filling the first through region  125  may be formed on the first preliminary semiconductor layer  131 . For example, the buried layer  155  may include at least one of a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer. The first preliminary semiconductor layer  131  and the buried layer  155  may be formed by chemical vapor deposition (CVD) or atomic layer deposition (ALD). According to some embodiments, forming the first preliminary semiconductor layer  131  may include recrystallization by means of a first heat treatment process. When the semiconductor layer is substantially amorphous after deposition, the semiconductor layer may become a polycrystalline silicon layer having relatively small grains by means of the recrystallization. The first heat treatment process may be a solid phase crystallization process. The first preliminary semiconductor layer  131  and the buried layer  155  are deposited, and then the uppermost insulation layer  120 U may be exposed by a planarization process. Alternatively, the planarization process may not be performed. 
     Referring to  FIGS. 54 through 56 , an upper portion of the preliminary channel structure may be etched. For example, a first semiconductor layer  132  may be formed by etching the upper portion of the first preliminary semiconductor layer  131 .  FIG. 55  is an enlarged view of the first semiconductor layer  132  in  FIG. 54 , and  FIG. 56  is an upper surface view of the first semiconductor layer  132 . A top surface of the first semiconductor layer  132  may be exposed by second through regions  126 . The etching process may be performed to a depth of the second through region  126  that is between a top surface of the uppermost cell gate sacrificial layer  110   m  and a bottom surface of the upper selection gate sacrificial layer  110 U. That is, bottom surfaces of the second through regions  126  may be disposed between the top surface of the uppermost cell gate sacrificial layer  110   m  and the bottom surface of the upper selection gate sacrificial layer  110 U. 
     A buried pattern  156  may be formed by etching an upper portion of the buried layer  155 . For example, a top surface of the buried pattern  156  may be disposed between the top surface of the uppermost cell gate sacrificial layer  110   m  and the bottom surface of the upper selection gate sacrificial layer  110 U. A height of the top surface of the buried pattern  156  may be the same as or higher (e.g., closer to the bottom surface of the upper selection gate sacrificial layer  110 U) than a height of the top surface of the first semiconductor layer  132 . The bottom surfaces of the second through regions  126  may be defined by the top surface of the buried pattern  156  and the top surface of the first semiconductor layer  132 . Therefore, in comparison with a device that does not have the buried pattern  156 , the top surface of the first semiconductor layer  132  may expose a relatively small number of grains by means of the second through regions  126 . 
     The second through regions  126  may be formed by various etching processes such as dry etching, wet etching, or combinations thereof. According to some embodiments, etching processes for forming the first semiconductor layer  132  and the buried pattern  156  may be performed at the same time. As such, the etching process may be performed by an etching recipe having slightly different etch rates with respect to the first semiconductor layer  132  and the buried pattern  156 . As the etching process is performed, a step height between the top surface of the first semiconductor layer  132  and the top surface of the buried pattern  156  may be generated due to the difference in the etch rates. 
     In some embodiments, etching processes for forming the first semiconductor layer  132  and the buried pattern  156  may be performed at different times and/or using different processes. In some embodiments, the first preliminary semiconductor layer  131  and the buried layer  155  are etched together, and an additional process further etching one of the first preliminary semiconductor layer  131  or the buried layer  155  may be performed. During the etching of the buried layer  155 , a portion of the uppermost insulation layer  120 U or the upper selection gate sacrificial layer  110 U may be etched together. 
     Referring to  FIGS. 57 through 59 , a second semiconductor layer  133  filling the second through regions  126  may be formed.  FIG. 58  is an enlarged view of the first and second semiconductor layers  132  and  133  in  FIG. 57 , and  FIG. 59  is an upper surface view of the second semiconductor layer  133 . The second semiconductor layer  133  may include at least one of silicon or silicon-germanium. The second semiconductor layer  133  may be formed through an epitaxial growth process that uses the top surface of the first semiconductor layer  132  exposed by the second through regions  126  as a seed. That is, the epitaxial process may be performed by using grains constituting the top surface of the first semiconductor layer  132  as a seed. In comparison with a device that does not have the buried pattern  156 , the first semiconductor layer  132  exposes a relatively small number of grains. Therefore, when the second semiconductor layer  133  is grown by using the first semiconductor layer  132  as a seed, the second semiconductor layer  133  may be composed of a relatively small number of grains as illustrated in  FIG. 59 . Each of the grains grown by using the first semiconductor layer  132  as a seed may form grain boundaries by contacting one another on the buried pattern  156 . Although some grains are combined together or one grain is divided into a plurality of grains during the growth process, the growth may be maintained only in some seed grains until the completion of the process. However, the number of grains formed in the second semiconductor layer  133  may be similar to the number of the seed grains. The grains constituting the second semiconductor layer  133  may have a shape with a relatively long extension in a direction perpendicular to the top surface of the substrate  100 . The second semiconductor layer  133  may be formed higher than the top surface of the uppermost insulation layer  120 U, and may be planarized to have substantially the same height as the uppermost insulation layer  120 U. The second semiconductor layer  133  may have an intrinsic state or may be doped with a first conductive type impurity. 
     Referring to  FIG. 60 , the sacrificial layers  110 U,  110   m ,  110  and  110 L may be removed. The removal process may include forming a first trench  140  by continuously patterning the insulation layers  120 U,  120  and  120 L and the sacrificial layers  110 U,  110   m ,  110  and  110 L. The insulation layers  120 U,  120  and  120 L may be separated into the insulation patterns  120 Ua,  120   a  and  120 La by means of forming the first trench  140 . Forming the first trench  140  may be performed by an anisotropic etching process. Recess regions  145 L,  145  and  145 U may be formed by removing the sacrificial patterns  110 La,  110   ma ,  110   a  and  110 Ua exposed by the first trench  140  through performing a selective etching process. An etch rate of the sacrificial patterns  110 La,  110   ma ,  110   a  and  110 Ua in the selective etching process may be faster/larger than etch rates of the insulation patterns  120 La,  120   a  and  120 Ua, the buffer insulation layer  105  and the semiconductor pattern  136 . Therefore, after the performing of the selective etching process, the insulation patterns  120 La,  120   a  and  120 Ua, the buffer insulation layer  105  and the channel structures  139  may remain. The recess regions  145 L,  145  and  145 U may expose portions of sidewalls of the channel structures  139  that were in contact with the sacrificial patterns  110 La,  110   ma ,  110   a  and  110 Ua, respectively. 
     Referring to  FIG. 61 , a data storage layer  150  may be formed in the recess regions  145 L,  145  and  145 U. The data storage layer  150  may be formed by using deposition technology (e.g., CVD or ALD, etc.) that can provide excellent step coverage. Therefore, the data storage layer  150  may be substantially formed conformally along the recess regions  145 L,  145  and  145 U. The data storage layer  150  may fill a portion of the recess regions  145 L,  145  and  145 U. 
     After forming the data storage layer  150 , a gate conductive layer  158  filling the recess regions  145 L,  145  and  145 U may be formed. The gate conductive layer  158  may fill at least a portion of the first trench  140 . The gate conductive layer  158  may be electrically isolated from the channel structures  139  and the substrate  100  by the data storage layer  150 . 
     Referring to  FIG. 62 , after forming the gate conductive layer  158 , a portion of the gate conductive layer  158  outside of the recess regions  145 L,  145  and  145 U is removed to form gate electrodes  157 L,  157   m ,  157  and  157 U in the recess regions  145 L,  145  and  145 U. The gate conductive layer  158  outside of the recess regions  145 L,  145  and  145 U may be removed by a wet etching and/or a dry etching process. As a result, a second trench  141  may be formed. 
     A lowermost pattern among the gate electrodes is a lower selection gate pattern  157 L, and an uppermost pattern may be an upper selection gate pattern  157 U. Cell gate patterns  157   m  and  157  may be provided between the lower selection gate pattern  157 L and the upper selection gate pattern  157 U. The cell gate patterns may include an uppermost cell gate pattern  157   m  and cell gate patterns  157  thereunder. 
     A first impurity region  170  may be formed in the substrate  100  under a bottom surface of the second trench  141 . The first impurity region  170  may extend along the second trench  141 . The first impurity region  170  may be formed by implanting second conductive type impurity ions. The uppermost insulation pattern  120 Ua may be used as an ion implantation mask. 
     Second impurity regions  198  may be formed at upper portions of the channel structures  139  (e.g., on the second semiconductor layer  133 ). Each of the second impurity regions  198  may be doped with the second conductive type impurity. A bottom surface of the second impurity region(s)  198  may be higher than a top surface of the upper selection gate pattern  157 U. The second impurity region(s)  198  may be formed at the same time as the first impurity region  170 . Alternatively, the second impurity region  198  may be formed before forming the first impurity region  170 . As such, the second impurity region  198  may be formed after forming the channel structures  139  and before forming the second trench  141 . Alternatively, the second impurity region  198  may be formed after forming the first impurity region  170 . 
     A device isolation pattern  175  filling the second trench  141  may be formed. Forming the device isolation pattern  175  may include forming a device isolation layer filling the second trench  141  on the substrate  100  and performing a planarization process on an upper surface of the data storage layer  150  using the uppermost insulation pattern  120 Ua as an etch stop layer. The device isolation pattern  175  may include an insulating material. For example, the device isolation pattern  175  may be formed of a high-density plasma oxide layer, a spin on glass (SOG) layer and/or a chemical vapor deposition (CVD) oxide layer, etc. After forming the device isolation pattern  175 , the exposed data storage layer  150  is etched such that the uppermost insulation pattern  120 Ua may be exposed. As such, the second impurity region  198  may be exposed together with the uppermost insulation pattern  120 Ua. 
     Referring again to  FIG. 50 , bit lines BL, which are electrically connected to the second impurity regions  198 , may be formed. The bit lines BL may extend in the x direction. An interlayer dielectric (not shown), which covers the uppermost insulation pattern  120 Ua and the device isolation pattern  175 , is formed, and the bit lines BL may be formed on the interlayer dielectric(s). The bit lines BL may connect via contact plugs  199  penetrating the interlayer dielectric(s) to the second impurity regions  198 . The contact plugs  199  may include at least one of metal, conductive metal nitride, or a doped semiconductor material. 
       FIG. 63  is a perspective view of the semiconductor device according to some embodiments, and  FIG. 64  is an enlarged view of a channel structure in  FIG. 63 . For descriptive simplicity, the description related to technical characteristics overlapping with other Figures may not be provided below. 
     Referring to  FIGS. 63 and 64 , a stack structure is provided on a substrate  100 . The stack structure may include gate patterns and insulation patterns which are repeatedly and alternatingly stacked on the substrate  100 . The gate patterns may include a lower selection gate pattern  157 L, cell gate patterns  157   m  and  157 , and an upper selection gate pattern  157 U. Channel structures  139 , which extend from the substrate  100  to penetrate the gate patterns  157 U,  157   m ,  157  and  157 L and the insulation patterns  120 Ua,  120   a  and  120 La, may be provided. The channel structures  139  may be provided in first through regions  125  penetrating the gate patterns  157 U,  157   m ,  157  and  157 L and the insulation patterns  120 Ua,  120   a  and  120 La. 
     The channel structures  139  may include a first region P 1  containing a first semiconductor layer  132 , and a third region P 3  containing a second semiconductor layer  133 . The first region P 1  may be an active region of the cell gate patterns  157   m  and  157  and the lower selection gate pattern  157 L, and the third region P 3  may be an active region of the upper selection gate pattern  157 U. The third region P 3  may be provided on the first region P 1 . A boundary between the first region P 1  and the third region P 3  may be provided between the upper selection gate pattern  157 U and the uppermost cell gate pattern  157   m . The first and second semiconductor layers  132  and  133  may constitute a portion of a semiconductor pattern  136 . The third region P 3  may be adjacent the upper selection gate pattern  157 U, and the first region P 1  may be adjacent the cell gate patterns  157   m  and  157 . That is, when the upper selection gate pattern  157 U is a gate electrode of a string selection transistor, a portion of the third region P 3  may be a channel region of the string selection transistor. When the cell gate patterns  157   m  and  157  are gate electrodes of memory cell transistors, a portion of the first region P 1  may be a channel region of the memory cell transistors. 
     A grain size in the third region P 3  may be larger than that in the first region P 1 . For example, grains of the third region P 3  may have longer lengths in a direction (z direction) perpendicular to the substrate  100  than widths in a direction (x direction or y direction) parallel to a surface of the substrate  100 . For example, aspect ratios of the grains in the third region P 3  may be within a range of about 5 to about 100. For example, the lengths of the grains in the third region P 3  in the z direction may be greater than a thickness of the upper selection gate pattern  157 U. That is, the string selection transistor may have a channel region with a relatively larger grain size than the memory cell transistors. Therefore, the area of grain boundaries in the channel region of the string selection transistor may be reduced. Accordingly, electrical characteristics of a semiconductor device such as a leakage current generated by grain boundaries may be improved. 
     The channel structures  139  may further include a buried pattern  156  surrounded by the semiconductor pattern  136 . For example, the semiconductor pattern  136  is provided along bottom surfaces and inner walls of the first through regions  125 , and the buried pattern  156  may be filled in the semiconductor pattern  136 . The buried pattern  156  may be spaced apart from the substrate  100  by means of the semiconductor pattern  136 . A top surface of the buried pattern  156  may be higher (e.g., closer to a top surface of the uppermost insulation pattern  120 Ua) than a top surface of the upper selection gate pattern  157 U. 
     A device isolation pattern  175  extending between the channel structures  139  may be provided. A first impurity region  170  may be formed in the substrate  100  under the device isolation pattern  175 . The first impurity region  170  may have a line shape extending in the y direction. The first impurity region  170  may be a region doped with a second conductive type impurity. The second conductive type may be a conductive type different from the first conductive type. 
     First and second data storage layers DA 1  and DA 2  may be provided between the gate patterns  157 U,  157   m ,  157  and  157 L and the channel structures  139 . The first data storage layer DA 1  may extend vertically along the sidewalls of the first through regions  125 . The second data storage layer DA 2  may extend along upper surfaces, lower surfaces and sidewalls of the gate patterns  157 U,  157   m ,  157  and  157 L. 
     A second impurity region  198  may be provided in an upper portion of the semiconductor pattern  136  adjacent the uppermost insulation pattern  120 Ua. The second impurity region  198  may be an impurity region having the same conductive type as the first impurity region  170 . Bit lines BL may extend in a direction (e.g., x direction) crossing the gate patterns  157 U,  157   m ,  157  and  157 L, and may be electrically connected to the second impurity region  198 . The bit lines BL may be connected to the channel structures  139  through contact plugs  199 . The bit lines BL may include at least one of metal, conductive metal nitride, or a semiconductor material. 
       FIGS. 65 through 72  are cross-sectional views and upper surface views illustrating a method of fabricating a semiconductor device according to some embodiments. 
     Referring to  FIG. 65 , a stack structure, in which first material layers and second material layers are repeatedly and alternatingly stacked, may be provided on a substrate  100 . The first material layers may be sacrificial layers  110 L,  110   m ,  110  and  110 U. The second material layers may be insulation layers  120 L,  120  and  120 U. Buffer insulation layer  105 , the insulation layers  120 L,  120  and  120 U and the sacrificial layers  110 L,  110   m ,  110  and  110 U are continuously patterned such that first through regions  125  exposing the substrate  100  may be formed. 
     First data storage layers DA 1  may be formed along sidewalls and bottom surfaces of the first through regions  125 . The first data storage layer DA 1  may include at least one insulation layer. 
     Referring to  FIG. 66 , preliminary channel structures may be formed in the first through regions  125 . Forming the preliminary channel structures may include sequentially forming first preliminary semiconductor layers  131  and buried layers  155  in the first through regions  125 . The first preliminary semiconductor layer  131  may be formed on the first data storage layer DA 1 . Before forming the first preliminary semiconductor layer  131 , a lower portion of the first data storage layer DA 1  may be etched to expose the substrate  100 . Therefore, the first preliminary semiconductor layer  131  may be electrically connected to the substrate  100 . The etching of the first data storage layer DA 1  may be performed by using a spacer (not shown) as an etch mask after forming the spacer exposing the lower portion of the first data storage layer DA 1  on the sidewalls of the first through regions  125 . The spacer may include a silicon material. The spacer may be removed (or, alternatively, may not be removed) after the etching process, and may constitute a portion of the first preliminary semiconductor layer  131 . Forming the first preliminary semiconductor layer  131  may include a recrystallization process by means of a first heat treatment process. The first preliminary semiconductor layer  131  may become a polycrystalline silicon layer having relatively small grains by means of the recrystallization process. For example, the first heat treatment process may be a solid phase crystallization process. The first preliminary semiconductor layer  131  and the buried layer  155  are deposited, and then the uppermost insulation layer  120 U may be exposed by a planarization process. Alternatively, the planarization process may not be performed. 
     Referring to  FIGS. 67 through 69 , an upper portion of the preliminary channel structure may be etched. For example, a first semiconductor layer  132  is formed by etching the upper portion of the first preliminary semiconductor layer  131 .  FIG. 68  is an enlarged view of the first semiconductor layer  132  in  FIG. 67 , and  FIG. 69  is an upper surface view of the first semiconductor layer  132 . The first semiconductor layer  132  may have a top surface exposed by second through regions  126 . The etching process may be performed to a depth between a top surface of the uppermost cell gate sacrificial layer  110   m  and a bottom surface of the upper selection gate sacrificial layer  110 U. That is, bottom surfaces of the second through regions  126  may be disposed between the top surface of the uppermost cell gate sacrificial layer  110   m  and the bottom surface of the upper selection gate sacrificial layer  110 U. 
     A buried pattern  156  may be formed by etching an upper portion of the buried layer  155 . For example, a top surface of the buried pattern  156  may be higher than a top surface of the upper selection gate sacrificial layer  110 U and may be lower than a top surface of the uppermost insulation layer  120 U. During the etching of the buried layer  155 , an upper portion of the first data storage layer DA 1  may also be etched. Alternatively, the upper portion of the first data storage layer DA 1  may not be etched. 
     The top surface of the first semiconductor layer  132  may define the bottom surface of the second through regions  126 . Therefore, the top surface of the first semiconductor layer  132  may expose a relatively small number of grains in the second through regions  126  (e.g., in comparison with a device not having the buried pattern  156 ). 
     The second through regions  126  may be formed by various etching processes such as dry etching, wet etching, or combinations thereof. According to some embodiments, etchings for forming the first semiconductor layer  132  and the buried pattern  156  may be performed at the same time. As such, the etching process may be performed by an etching recipe having a relatively higher etch rate with respect to the first semiconductor layer  132 . In some embodiments, etching processes for forming the first semiconductor layer  132  and the buried pattern  156  may be performed at different times and/or using different processes. In some embodiments, the buried pattern  156  may be formed after forming a second semiconductor layer  133 . 
     Referring to  FIGS. 70 and 71 , a second semiconductor layer  133  filling the second through regions  126  may be formed.  FIG. 71  is an enlarged view of the first and second semiconductor layers  132  and  133  in  FIG. 70 . An upper surface view of the second semiconductor layer  133  may be substantially the same as  FIG. 59 . The second semiconductor layer  133  may include at least one of silicon or silicon-germanium. The second semiconductor layer  133  may be formed through an epitaxial growth process that uses the first semiconductor layer  132  exposed by the second through regions  126  as a seed. That is, the epitaxial process may be performed by using grains constituting the top surface of the first semiconductor layer  132  as a seed. The first semiconductor layer  132  exposes a relatively small number of grains (e.g., in comparison with a device not having the buried pattern  156 ). Therefore, when the second semiconductor layer  133  is grown by using the first semiconductor layer  132  as a seed, the second semiconductor layer  133  may be composed of a relatively small number of grains as illustrated in  FIG. 59 . Each of the grains grown by using the first semiconductor layer  132  as a seed may form grain boundaries by contacting one another on the buried pattern  156 . Although some grains may be combined together or one grain may be divided into a plurality of grains during the growth process, the growth may be maintained only in some seed grains until the completion of the process. However, the number of grains formed in the second semiconductor layer  133  may be similar to the number of the seed grains. The grains constituting the second semiconductor layer  133  may have a shape that extends long in a direction perpendicular to the top surface of the substrate  100 . The second semiconductor layer  133  may be formed higher than the top surface of the uppermost insulation layer  120 U, and the second semiconductor layer  133  may be subsequently planarized to have substantially the same height as the uppermost insulation layer  120 U. The second semiconductor layer  133  may have an intrinsic state or may be doped with a first conductive type impurity. 
     Referring to  FIG. 72 , the sacrificial layers  110 U,  110   m ,  110  and  110 L may be removed to form recess regions (not shown), and a second data storage layer DA 2  and gate electrodes  157 L,  157   m ,  157  and  157 U are formed in the recess regions. A lowermost pattern among the gate electrodes is a lower selection gate pattern  157 L, and an uppermost pattern may be an upper selection gate pattern  157 U. Cell gate patterns  157   m  and  157  may be provided between the lower selection gate pattern  157 L and the upper selection gate pattern  157 U. The cell gate patterns may include an uppermost cell gate pattern  157   m  and cell gate patterns  157  thereunder. 
     A first impurity region  170  may be formed in the substrate  100  under a bottom surface of the second trench  141 . The first impurity region  170  may be formed by implanting second-type dopant ions. Second impurity regions  198  may be formed at upper portions of the channel structures  139 . The second impurity region  198  may be doped with the second-type dopant. A bottom surface of the second impurity region  198  may be higher than a top surface of the upper selection gate pattern  157 U. The second impurity region  198  may be formed at the same time as the first impurity region  170 . A device isolation pattern  175  filling the second trench  141  may be formed. 
     Referring again to  FIG. 63 , bit lines BL, which are electrically connected to the second impurity regions  198 , may be formed. The bit lines BL may extend in the x direction. The bit lines BL may connect via contact plugs  199  penetrating interlayer dielectric(s) (not shown) to the second impurity regions  198 . The contact plugs  199  may include at least one of metal, conductive metal nitride, or a doped semiconductor material. 
       FIGS. 73 and 74  are perspective views illustrating structures of data storage layers according to some embodiments. 
       FIG. 73  is a perspective view illustrating the data storage layer  150  according to some embodiments. For example, the data storage layer  150  of  FIG. 73  may be the data storage layer  150  illustrated in  FIG. 50 . 
     Buried pattern DP and semiconductor pattern SP are provided in first through regions  125 , and a data storage layer  150  may be provided on a sidewall of the semiconductor pattern SP. The data storage layer  150  may include a tunnel insulation layer TIL, a charge storage layer CL, and a blocking insulation layer BLL that are sequentially stacked in recess regions  145 . Layers constituting the data storage layer  150  may be formed by using deposition technology (e.g., chemical vapor deposition or atomic layer deposition technology), which can provide excellent step coverage. 
     The charge storage layer CL may be one of various insulation layers having abundant trap sites and one of various insulations layers including nanoparticles, and may be formed by using one of chemical vapor deposition or atomic layer deposition technology. For example, the charge storage layer CL may include one of various insulation layers including a trap insulation layer, a floating gate electrode, or conductive nano dots. For example, the charge storage layer CL may include at least one of a silicon nitride layer, a silicon oxynitride layer, a Si-rich nitride layer, nanocrystalline Si, and a laminated trap layer. 
     The tunnel insulation layer TIL may include one of various materials having a larger bandgap than the charge storage layer CL, and may be formed by using one of chemical vapor deposition or atomic layer deposition technology. For example, the tunnel insulation layer TIL may be a silicon oxide layer formed by using one of the foregoing deposition technologies. In addition, a predetermined heat treatment carried out after the deposition process may be further performed on the tunnel insulation layer TIL. The heat treatment may be a rapid thermal nitridation (RTN) or an annealing process performed in an atmosphere including at least one of nitrogen or oxygen. 
     The blocking insulation layer BLL may be a single insulation layer. Alternatively, the blocking insulation layer BLL may include first and second blocking insulation layers (not shown). The first and second blocking insulation layers may be formed of different materials, and one of the first and second blocking insulation layers may be one of various materials having a bandgap that is smaller than the tunnel insulation layer TIL and larger than the charge storage layer CL. Also, the first and second blocking insulation layers may be formed by using one of chemical vapor deposition or atomic layer deposition technology, and at least one of the first and second blocking insulation layers may be formed through a wet oxidation process. According to some embodiments, the first blocking insulation layer is one of high-k dielectric layers such as an aluminum oxide layer and a hafnium oxide layer, and the second blocking insulation layer may be a material having a dielectric constant smaller than the first blocking insulation layer. According to some embodiments, the second blocking insulation layer is one of high-k dielectric layers, and the first blocking insulation layer may include a material having a dielectric constant smaller than the second blocking insulation layer. 
       FIG. 74  is a perspective view illustrating a structure of a data storage layer according to some embodiments. For example, the data storage layers DA 1  and DA 2  of  FIG. 74  may be the data storage layers illustrated in  FIG. 63 . The data storage layer according to some embodiments may include a first data storage layer DA 1  and a second data storage layer DA 2 . The first data storage layer DA 1  may be formed in the first through regions  125 , and may extend along a sidewall of the first through regions  125 . The second data storage layer DA 2  may be formed in the recess regions  145 . The first and second data storage layers DA 1  and DA 2  may include one or more of the blocking insulation layer BLL, the charge storage layer CL, and the tunnel insulation layer TIL. 
       FIGS. 75A through 75L  are cross-sectional views illustrating a method of fabricating a semiconductor device according to some embodiments. 
     Referring to  FIG. 75A , sacrificial layers  110 L,  110   m  and  110 U and insulating layers  120 L,  120   m  and  120 U may be alternately and repeatedly stacked on a substrate  10 . The substrate  10  may include one of various materials, such as materials having semiconductor properties, insulating materials, and a semiconductor or conductor covered by an insulating material. For example, the substrate  10  may be a silicon substrate, a germanium substrate, a silicon-germanium substrate, or a compound semiconductor substrate. The substrate  10  may be doped to have a first conductivity type. 
     The sacrificial layers  110 L,  110   m  and  110 U may be formed of a material having an etch selectivity with respect to the insulating layers  120 L,  120   m  and  120 U. For example, while the sacrificial layers  110 L,  110   m  and  110 U are etched using a predetermined etch recipe, the insulating layers  120 L,  120   m  and  120 U may be only slightly etched or an etch rate of the insulating layers  120 L,  120   m  and  120 U may otherwise be reduced/minimized. For example, each of the sacrificial layers  110 L,  110   m  and  110 U may be formed of a silicon layer, a silicon oxide layer, a silicon carbide layer, a silicon oxynitride layer, or a silicon nitride layer. Each of the insulating layers  120 L,  120   m  and  120 U may be formed of a silicon layer, a silicon oxide layer, a silicon carbide layer, a silicon oxynitride layer, or a silicon nitride layer. The sacrificial layers  110 L,  110   m  and  110 U may be formed of a different material from the insulating layers  120 L,  120   m  and  120 U. 
     A thickness of a lower sacrificial layer  110 L may be equal to or greater than those of upper sacrificial layers  110 U and middle sacrificial layers  110   m . An upper insulating layer  120 U may have a thickness equal to or greater than those of middle insulating layers  120   m . A thickness of a lower insulating layer  120 L may be substantially equal to the thickness of the upper insulating layer  120 U and greater than those thicknesses of the middle insulating layers  120   m . However, the inventive concepts are not limited to the thicknesses of the sacrificial layers  110 L,  110   m  and  110 U and the insulating layers  120 L,  120   m  and  120 U described above. The thicknesses of the sacrificial and insulating layers  110 L,  110   m ,  110 U,  120 L,  120   m  and  120 U may be variously modified. Additionally, the number of the stacked sacrificial layers  110 L,  110   m  and  110 U and the number of the stacked insulating layers  120 L,  120   m  and  120 U may also be variously modified. 
     A buffer insulating layer  12  may be formed on the substrate  10  before the sacrificial and insulating layers  110 L,  110   m ,  110 U,  120 L,  120   m  and  120 U are formed. The buffer insulating layer  12  may be formed of a silicon oxide layer, among other materials. 
     Referring to  FIG. 75B , the sacrificial layers  110 L,  110   m  and  110 U, the insulating layers  120 L,  120   m  and  120 U and the buffer insulating layer  12  may be successively patterned to form channel openings  130 . In detail, a mask pattern may be formed on the upper insulating layer  120 U, and then the layers  110 L,  110   m ,  110 U,  120 L,  120   m ,  120 U and  12  may be anisotropically etched using the mask pattern as an etch mask until a top surface of the substrate  10  is exposed. Thus, the channel openings  130  may be formed. Each channel opening  130  may have a hole-shape. In a plan view, each channel opening  130  may have a circular shape, an elliptical shape, or a polygonal shape. 
     Referring to  FIG. 75C , a first semiconductor pattern  150  and a channel insulation pattern  152  are formed in each of the channel openings  130 . In detail, a first semiconductor layer may be conformally formed on inner sidewalls of the channel openings  130  and the upper insulating layer  120 U, and then a channel insulating layer may be formed on the first semiconductor layer to fill the channel openings  130 . Thereafter, the first semiconductor layer and the channel insulating layer may be planarized until a top surface of the upper insulating layer  120 U is exposed, thereby forming the first semiconductor patterns  150  and the channel insulation patterns  152 . 
     The first semiconductor layer may be formed by an atomic layer deposition (ALD) process or a chemical vapor deposition (CVD) process. The first semiconductor patterns  150  may be formed of poly-crystalline silicon. The first semiconductor pattern  150  may have a pipe-shape, a hollow cylindrical shape, or a cup-shape in the channel opening  130 . 
     The channel insulating layer may be formed by a spin-on-glass (SOG) process, an ALD process, or a CVD process. The filling insulation patterns  152  may be formed of an insulating material or silicon oxide. 
     Referring to  FIG. 75D , upper portions of the channel insulation patterns  152  may be removed to form filling insulation patterns  152   a . The upper portions of the channel insulation patterns  152  may be removed to form the filling insulation patterns  152   a  exposing upper portions of the first semiconductor patterns  150 . A dry etching process or a wet etching process may be performed on the upper portions of the channel insulation patterns  152  for forming the filling insulation patterns  152   a . A top surface of the filling insulation pattern  152   a  may be higher (e.g., farther from an upper surface of the substrate  10 ) than a top surface of the uppermost sacrificial layer  110 U. 
     Second semiconductor patterns  160  may be formed to fill the channel openings  130  having the respective filling insulation patterns  152   a  therein. In detail, a second semiconductor layer may be formed to cover top surfaces of the filling insulation patterns  152   a  and upper sidewalls of the first semiconductor patterns  150  exposed by the filling insulation patterns  152   a . The second semiconductor layer may also be formed on the top surface of the upper insulating layer  120 U. The second semiconductor layer may be planarized until the top surface of the upper insulating layer  120 U is exposed, thereby forming the second semiconductor patterns  160 . The second semiconductor layer may be formed by an ALD process or a CVD process. 
     Referring to  FIGS. 75E and 75F , a dopant injecting process  161  may be performed on the first semiconductor patterns  150 . In detail, first conductivity type dopants may be injected into the first semiconductor patterns  150  by using the upper insulating layer  120 U as a mask. For example, the first conductivity type dopants may be P-type dopants. The P-type dopants may include one of boron, aluminum, and gallium. When the first conductivity type dopants are injected into the first semiconductor patterns  150 , the first conductivity type dopants may also be injected into the second semiconductor patterns  160 . 
     A laser thermal treating process may be performed on the first semiconductor patterns  150  to form third semiconductor patterns  162 . In more detail, a laser may be irradiated to at least portions of the upper portions of the first semiconductor patterns  162  by the laser thermal treating process. The upper portions of the first semiconductor patterns  150  may be melted by the laser beam, and then the melted portions of the first semiconductor patterns  150  may be re-crystallized to form the third semiconductor patterns  162 . The third semiconductor patterns  162  may be disposed to be higher (e.g., farther from an upper surface of the substrate  10 ) than a top surface of the uppermost layer of the middle sacrificial layers  110   m . In particular, a bottom end/surface of the third semiconductor pattern  162  may be higher than the top surface of the uppermost layer of the middle sacrificial layers  110   m , and a top end/surface of the third semiconductor pattern  162  may be disposed at a level equal to (e.g., coplanar with) or lower than a bottom surface of the second semiconductor pattern  160 . In other words, a portion of the first semiconductor pattern  150  adjacent the upper sacrificial layers  110 U may be melted and then be re-crystallized to form the third semiconductor pattern  162 . A grain size of the third semiconductor pattern  162  may be greater than a grain size of the first semiconductor pattern  150  due to the laser thermal treating process. 
     While the laser thermal treating process is performed to melt the portion of the first semiconductor pattern  150  adjacent the upper sacrificial layers  110 U, the first conductivity type dopants non-uniformly distributed in the first semiconductor pattern  150  may become uniformly distributed. In other words, the first conductivity type dopants may be uniformly distributed in the third semiconductor pattern  162 . 
     Referring to  FIG. 75G , dopants may be injected into the second semiconductor patterns  160  to form conductive pads D. In more detail, dopant ions may be implanted into the second semiconductor pattern  160  and a portion of the first semiconductor pattern  150  disposed on the third semiconductor pattern  162  to form the conductive pad D. The conductive pad D may be doped with dopants of a conductivity type different from the conductivity type of the first and third semiconductor patterns  150  and  162 . For example, the conductive pad D may be doped with second conductivity type dopants. As an example, the second conductivity type dopants may include one of phosphorus, arsenic, and antimony. The conductive pad D may constitute a diode along with the third semiconductor pattern  162  thereunder. 
     Alternatively, the conductive pad D may be formed in the portion of the first semiconductor pattern  150  and the second semiconductor pattern  160  before the laser thermal treating (e.g., annealing) process is performed. The conductive pad D may be doped with dopants of a conductivity type different from that of the first semiconductor pattern  150 . After the conductive pad D is formed, the laser thermal treating process may be performed on at least a portion of the upper portion of the first semiconductor pattern  150  to form the third semiconductor pattern  162 . 
     Referring to  FIG. 75H , the sacrificial layers  110 L,  110   m  and  110 U and the insulating layers  120 L,  120   m  and  120 U may be successively patterned to form trenches  165 . An etch mask may be formed on the upper insulating layer  120 U, and then the layers  120 U,  120   m ,  120 L,  110 U,  110   m ,  110 L and  12  under the etch mask may be anisotropically etched until the top surface of the substrate  10  is exposed. Thus, the trenches  165  may be formed. Additionally, a stack structure may be formed between the trenches  165  adjacent each other. The stack structure may include a buffer insulating pattern  15 , sacrificial patterns  130 L,  130   m  and  130 U and insulating patterns  140 L,  140   m  and  140 U. The sacrificial patterns  130 L,  130   m  and  130 U and the insulating patterns  140 L,  140   m  and  140 U may be alternately and repeatedly stacked on the buffer insulating pattern  15  in the stack structure. The stack structure may include the channel opening  130 . In other words, the trenches  165  may be formed at both sides of the channel opening  130 . The trenches  165  may expose sidewalls of the sacrificial patterns  130 L,  130   m  and  130 U, the insulating patterns  140 L,  140   m  and  140 U and the buffer insulating pattern  15 . The trenches  165  may have line-shapes or rectangular shapes, among other shapes, in a plan view. 
     Referring to  FIG. 75I , the sacrificial patterns  130 L,  130   m  and  130 U exposed by the trenches  165  may be removed to form upper recess regions  170 U, middle recess regions  170   m , and a lower recess region  170 L. The recess regions  170 L,  170   m  and  170 U may horizontally extend from the trenches  165  between the insulating patterns  140 L,  140   m  and  140 U. The lower and middle recess regions  170 L and  170   m  may expose respective portions of the first semiconductor pattern  150 . The upper recess regions  170 U may expose portions of the third semiconductor pattern  162 , respectively. 
     The sacrificial patterns  130 L,  130   m  and  130 U may be etched using an etch recipe having an etch selectivity with respect to the insulating patterns  140 L,  140   m  and  140 U and the first semiconductor pattern  150  to form the recess regions  170 L,  170   m  and  170 U. The sacrificial patterns  130 L,  130   m  and  130 U may be etched by a dry etching process and/or a wet etching process. 
     Referring to  FIG. 75J , a data storage layer  180  may be formed to cover inner surfaces of the recess regions  170 L,  170   m  and  170 U, and then a gate conductive layer  185  may be formed to fill the recess regions  170 L,  170   m  and  170 U in which the data storage layer  180  is formed. In some embodiments, the gate conductive layer  185  may fill the trenches  165 . Alternatively, the gate conductive layer  185  may be conformally formed in the trenches  165 . 
     The data storage layer  180  may be conformally formed on the inner surfaces of the recess regions  170 L,  170   m  and  170 U by a deposition technique having an excellent step coverage property. The deposition technique may be a CVD process or an ALD process. The data storage layer  180  may consist of a single layer or a plurality of layers. The data storage layer  180  may include a blocking insulating layer of a charge trap type non-volatile memory transistor. Additionally, the data storage layer  180  may further include a charge storage layer, or the charge storage layer and a tunnel insulating layer. 
     The gate conductive layer  185  may be formed by a CVD process, a physical vapor deposition (PVD) process, or an ALD process. The gate conductive layer  185  may include at least one of doped silicon, metal materials, metal nitrides, and metal silicides. In some embodiments, the gate conductive layer  185  may include a metal nitride such as tantalum nitride and/or a metal material such as tungsten. 
     Referring to  FIG. 75K , the gate conductive layer  185  disposed in the trenches  165  may be removed to form gate conductive patterns  190 L,  190   m  and  190 U in the recess regions  170 L,  170   m  and  170 U, respectively. In some embodiments, the gate conductive layer  185  disposed in the trenches  165  may be anisotropically etched to form the gate conductive patterns  190 L,  190   m  and  190 U. The lowermost pattern of the gate conductive patterns  190 L,  190   m  and  190 U may be a ground selection gate pattern  190 L, and upper patterns of the gate conductive patterns  190 L,  190   m  and  190 U may be string selection gate patterns  190 U. Cell gate patterns  190   m  may be disposed between the ground selection gate pattern  190 L and the string selection gate patterns  190 U. 
     After the gate conductive patterns  190 L,  190   m  and  190 U are formed, dopant regions  19  may be formed in the substrate  10 . The dopant regions  19  may be formed by an ion implantation process and may be formed in the substrate  10  under the trenches  165 . The dopant regions  19  may have a conductivity type different from the conductivity type of the substrate  10 . 
     The string selection gate patterns  190 U may be gate electrodes of string selection transistors. If the first conductivity dopants are non-uniformly distributed in a channel region adjacent the string selection gate patterns  190 U, threshold voltages of the string selection transistors may also be non-uniform to cause operation errors of the string selection transistors. However, according to various embodiments of the present inventive concepts, the third semiconductor pattern  162 , in which the first conductivity type dopants are uniformly distributed, may be used as the channel region of the string selection transistors, so that the threshold voltages of the string selection transistors may be substantially uniform. Thus, it may be possible to improve electrical characteristics of the semiconductor device. 
     Referring to  FIG. 75L , after the dopant regions  19  are formed, electrode separating patterns  210  may be formed to fill the trenches  165 , respectively. Next, upper plugs  215  may be formed to connect to the conductive pads D, respectively, and then an upper interconnection  220  may be formed to connect to the upper plugs  215 . The electrode separating patterns  210  may include at least one of silicon oxide, silicon nitride, and silicon oxynitride. The upper plugs  215  may include at least one of doped silicon and metallic materials. 
     The upper interconnection  220  may be electrically connected to the conductive pads D, the third semiconductor patterns  162  and the first semiconductor patterns  150  through the upper plugs  215 . The upper interconnection  220  may cross over (e.g., overlap) the gate conductive patterns  190 L,  190   m  and  190 U and/or the trenches  165 . 
       FIG. 76  is an enlarged view of a region ‘A’ in  FIG. 75L  that illustrates a vertical non-volatile memory device according to some embodiments. Referring to  FIG. 76 , in some embodiments, before the first semiconductor pattern  150  and the filling insulation pattern  152   a  are formed in the channel opening  130 , a data storage layer  180  may be formed to cover the inner sidewall of the channel opening  130 . The data storage layer  180  may include at least a tunnel insulating layer TIL. In some embodiments, the data storage layer  180  may include a blocking insulating layer BIL, a charge storage layer CL and the tunnel insulating layer TIL as illustrated in  FIG. 76 . 
     Before the gate conductive patterns are formed, a horizontal insulating layer  195  may be conformally formed to cover the inner surfaces of the recess regions  170   m . Thus, the horizontal insulating layer  195  may cover a portion of the data storage layer  180  exposed by the recess region  170   m . The horizontal insulating layer  195  may include a silicon oxide layer. The cell gate patterns  190   m  may be formed to fill the recess regions  170   m  having the horizontal insulating layer  195 . 
       FIG. 77  is a graph illustrating a concentration of dopants doped in a semiconductor layer in a method of fabricating a vertical non-volatile memory device according to some embodiments. Referring to  FIG. 77 , a reference designator A represents a concentration profile of the dopants in the first semiconductor pattern after the ion implantation process and before the laser thermal treating process. A reference designator B represents a concentration profile of the dopants in the first semiconductor pattern (e.g., including the third semiconductor pattern  162  that is derived from the first semiconductor pattern  150 ) after the laser thermal treating process. The concentration profile B is more uniform than the concentration profile A in a depth range from about 0.0 nanometers (nm) to about 30.0 nm, as illustrated in  FIG. 77 . 
       FIG. 78  is a schematic block diagram illustrating an example of a memory system including a semiconductor memory device formed according to some embodiments. 
     Referring to  FIG. 78 , the memory system  600  may be applied to a personal digital assistant (PDA), a portable computer, a web tablet, a wireless phone, a mobile phone, a digital music player, a memory card and all devices which may transmit and/or receive data in a wireless environment. 
     The memory system  600  includes an input/output device  620 , a controller  610 , a memory  630 , an interface  640 , and a bus  650 . The memory  630  and the interface  640  intercommunicate through the bus  650 . 
     The controller  610  includes at least one micro processor, a digital signal processor, a micro controller, and/or other process devices capable of performing similar functions to the above elements. The memory  630  may be used to store a command performed by the controller  610 . The input/output device  620  may input data or a signal from outside of the memory system  600  or may output data or a signal outside of the memory system  600 . For example, the input/output device  620  may include a keyboard, a key pad, and/or a display device. 
     The memory  630  includes a non-volatile memory device according to some embodiments. For example, the memory  630  may include a semiconductor device illustrated in  FIGS. 1-74 . The memory  630  may further include another kind of memory, such as a randomly accessible volatile memory and/or various other kinds of memories. 
     The interface  640  may serve to transmit/receive data to/from a communication network. 
       FIG. 79  is a schematic block diagram illustrating an example of a memory card having a semiconductor memory device formed according to some embodiments. For example, the memory card in  FIG. 79  may include a semiconductor memory device illustrated in  FIGS. 1-76 . 
     Referring to  FIG. 79 , the memory card  700 , which may support a high volume of data storage capacity, is provided with a flash memory device  710  according to some embodiments. The memory card  700  according to some embodiments includes a memory controller  720  which controls various data exchanges between a host and the flash memory  710 . 
     A static random access memory (SRAM)  721  may be used as a working memory of a processing unit, such as a central processing unit (CPU)  722 . A host interface  723  may have a data exchange protocol of the host contacting the memory card  700 . An error correction code  724  may detect and correct an error which is included in the data read out from the multi-bit flash memory device  710 . A memory interface  725  may be configured to interface with the flash memory device  710 . The processing unit  722  performs various control operations for data exchange of the memory controller  720 . Although not illustrated in the drawings, the memory card  700  according to the inventive concept may be further supplied with a read only memory (ROM) (not illustrated), or the like, which stores code data for interfacing with the host. 
       FIG. 80  is a schematic block diagram illustrating an example of a data processing system mounting a semiconductor memory device formed according to some embodiments. For example, the semiconductor memory device may include a semiconductor memory device illustrated in  FIGS. 1-76 . 
     Referring to  FIG. 80 , a flash memory system  810  is mounted on a data processing system such as a mobile device or a desktop computer. The data processing system  800  according to some embodiments includes the flash memory system  810 , a modem  820 , a central processing unit (CPU)  830 , a random access memory (RAM)  840  and a user interface  850  which is electrically connected to a system bus  860 . The flash memory system  810  includes a flash memory  811  and a memory controller  812  controlling the flash memory  811 . The flash memory system  810  may be substantially similar/equal to the memory system  600  or the flash memory system  710 . In the flash memory system  810 , the data processed by the central processing unit  830  or the data input from the outside are stored. Herein, the above-described flash memory system  810  may be include a solid state disk (SSD), and the data processing system  800  may thus stably store a high volume of data in the flash memory system  810 . Due to the increase in reliability, the flash memory system  810  may reduce the resources required for an error correction, thereby providing a high-speed data exchange function to the data processing system  800 . Although not illustrated in the drawings, the data processing system  800  according to some embodiments may be further supplied with an application chipset, a camera image processor (CIS) and/or an input/out device or the like. 
     Also, the flash memory device or the memory system according to some embodiments may be mounted in various types of packages. Examples of the packages of the semiconductor devices according to some embodiments may include package on package (PoP), ball grid arrays (BGAs), chip scale packages (CSPs), a plastic leaded chip carrier (PLCC), a plastic dual in-line package (PDIP), a die in waffle pack, a die in wafer form, a chip on board (COB), a ceramic dual in-line package (CERDIP), a plastic metric quad flat pack (MQFP), a thin quad flat pack (TQFP), a small outline package (SOP), a shrink small outline package (SSOP), a thin small outline package (TSOP), a thin quad flat package (TQFP), a system in package (SIP), a multi chip package (MCP), a wafer-level fabricated package (WFP), a wafer-level processed package (WSP) and so on. 
     According to some embodiments, a channel pattern, where a cell gate pattern and a selection gate pattern have different structures from each other, can be provided. A selection transistor region, which has an active region wider than an active region of a cell region, can be provided. 
     While the inventive concepts have been particularly shown and described with reference to various embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the inventive concepts as defined by the following claims. Therefore, the above-disclosed subject matter is to be considered illustrative and not restrictive.