Patent Publication Number: US-2017358536-A1

Title: Method of manufacturing semiconductor devices and corresponding device

Description:
BACKGROUND 
     Technical Field 
     The description relates to manufacturing semiconductor devices. 
     One or more embodiments may apply, e.g., to thermo-mechanical stress reduction in integrated circuits, e.g., for automotive and consumer products. 
     Description of the Related Art 
     Various types of integrated circuits (ICs) may adopt technologies such as BCD (Bipolar-CMOS-DMOS) technology. 
     BCD technology may be advantageously used, e.g., for producing integrated circuits with both power electronics and logical control electronics. BCD technology provides a family of silicon processes, each of which combines the strengths of three different process technologies onto a single chip: bipolar for precise analog functions, CMOS (Complementary Metal Oxide Semiconductor) for digital design and DMOS (Double Diffused Metal Oxide Semiconductor) for power and high-voltage elements. 
     Implementing BCD technology may involve top layer copper metal interconnections, called Re-Distribution Layer (RDL). 
     This may involve using a copper RDL module as the final metal. Such a module may include a copper (Cu) line/pad/power metallization (e.g., 10 micrometer-10×10 −6  meter-high) covered by a layer or stack of, e.g., nickel (Ni) and palladium (Pd) layers. 
     Also, silicon nitride (SiN) or silicon carbide (SiC) may be used in manufacturing ICs to provide a passivation layer for microchips, e.g., to provide a barrier against water molecules and other sources of corrosion and instability in microelectronics. 
     Taking into account mechanical stress issues on passivation materials (e.g., Si nitrides) induced by the thermo-mechanical expansion/contraction of metallic materials (Ni, Pd, Cu, titanium (Ti), tungsten (W)) may facilitate achieving satisfactory results. In that respect, a contribution to the local stress on passivation was observed to be related to Ni expansion, with stress increasing during thermal treatment due to the Cu/Ni/Pd thermal expansion coefficient mismatch, while these effects were found to increase as Ni thickness increases. 
     BRIEF SUMMARY 
     According to one or more embodiments, a method includes manufacturing a semiconductor device including a metallization. The manufacturing includes providing a capping stack onto said metallization, wherein said capping stack includes a pair of nickel layers and a layer of ductile material positioned between the nickel layers. 
     One or more embodiments may also relate to a corresponding device. 
     The claims are an integral part of the technical disclosure of one or more embodiments has provided herein. 
     One or more embodiments may facilitate taking into account mechanical stress issues in passivation materials (e.g., Si nitrides) which may be induced by thermo-mechanical expansion/contraction of metallic materials such as Ni, Pd, Cu, Ti, W. 
     One or more embodiments may involve an alternate deposition (e.g., electro-less or e-less deposition) of Ni/Pd to reduce stress effects. 
     Even without wishing to be bound to any specific theory in that respect, the ductility of an, e.g., Pd interlayer may be held to absorb the mechanical stress during the thermal cycle. 
     In one or more embodiments, a thin ductile (e.g., Pd) layer may be formed between two Ni layers, in order to reduce and decouple stress contributions. 
     One or more embodiments may benefit from Ni deposition on Pd being practicable without Ni surface chemical pre-treatment. 
     One or more embodiments may involve Ni/Pd electro-less deposition (named e-less) multilayer deposition on, e.g., RDL copper: four layers of Ni and Pd deposited in alternate sequence (Ni/Pd/Ni/Pd) in order to reduce the mechanical stress over a thermal cycle. 
     One or more embodiments may adopt other types of (e.g., e-less) deposition different from (e.g., Cu) Ni—Pd—Ni—Pd. 
     Depositions such as:
         (Cu) Ni—Pd—Ni—Pd—Au   (Cu) Ni—Au—Ni—Pd   (Cu) Ni—Au—Ni—Pd—Au
 
are exemplary of such alternative deposition options.
       

    
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
       One or more embodiments will now be described, purely by way of example, with reference to the annexed figures, in which: 
         FIG. 1  is a top view of a stack arrangement which may incorporate one or more embodiments, 
         FIG. 2  is a reproduction of a SEM-microscope cross-section across a conventional (single) stack arrangement, and 
         FIG. 3  is a reproduction of a SEM microscope cross-section across a (double) stack arrangement according to embodiments. 
     
    
    
     It will be appreciated that for the sake of clarity of representation certain features of the figures (e.g., layer thicknesses) may not be drawn to scale. 
     DETAILED DESCRIPTION 
     In the ensuing description, one or more specific details are illustrated, aimed at providing an in-depth understanding of examples of embodiments in the present description. The embodiments may be obtained without one or more of the specific details, or with other methods, components, materials, etc. In other cases, known structures, materials, or operations are not illustrated or described in detail so that certain aspects of embodiments will not be obscured. 
     Reference to “an embodiment” or “one embodiment” in the framework of the present description is intended to indicate that a particular configuration, structure, or characteristic described in relation to the embodiment is comprised in at least one embodiment. Hence, phrases such as “in an embodiment” or “in one embodiment” that may be present in one or more points of the present description do not necessarily refer to one and the same embodiment. Moreover, particular conformations, structures, or characteristics may be combined in any adequate way in one or more embodiments. 
     The references used herein are provided merely for convenience and hence do not define the extent of protection or the scope of the embodiments. 
     U.S. Pat. No. 6,815,789, which is incorporated herein by reference in its entirety, discloses a semiconductor electronic device comprising a die of semiconductor material and a support, the die of semiconductor material including an integrated electronic circuit and a plurality of contact pads associated with the electronic circuit and connected electrically to the support by wire leads. Each contact pad comprises a lower layer of aluminum, copper, or alloys thereof, and an upper layer comprising at least one film of a metal and/or metallic alloy selected from a group comprising nickel, palladium, and alloys thereof, and being deposited by an electroless chemical process. 
     While not referring to RDL technology and, more to the point, not disclosing multiple layers of the type contemplated in one or more embodiments the disclosure of U.S. Pat. No. 6,815,789 provides some background information on such processes. 
       FIG. 1  is a top view of a portion of a semiconductor device S produced, e.g., by BCD-RDL technology including a stack arrangement which may incorporate one or more embodiments. 
     The semiconductor device S (e.g., an integrated circuit—IC) may be produced an RDL process including (in a manner known per se) a sequence of steps leading to the formation of RDL metallizations  10 , e.g., Cu with an underlying barrier layer  12 , e.g., titanium tungsten (TiW) or other barrier materials such as TiN/Ti/TiN and tantalum/tantalum nitride (Ta/TaN), as shown in  FIG. 2 . 
     A combined (stacked) outer surface coating or “capping” may then be provided on the outer surface of the metallization  10 , the coating or capping having a thickness of, e.g., approximately 2 micron (2×10 −6  m). 
     In a conventional arrangement as exemplified in  FIG. 2 , such a stacked capping (that is, a multi-layer) may include a Ni—Pd layer with, e.g., Ni at  14 , Pd at  16 . In other conventional arrangements, the stacked capping may include Ni—Pd—Au or Ni—Au multiple layers. 
     While successfully adopted in production, such a Ni/Pd layer may exhibit a certain amount of stress, e.g., if exposed to temperatures in the range of, e.g., 300°-400° C. 
     Specifically, it was observed that such a “single” Ni—Pd stack  14 ,  16  can induce too high a stress on a passivation layer during a thermal cycle. 
     One or more embodiments as exemplified in  FIG. 3  may reduce the local stress due to, e.g., the Ni layer by resorting to “multiple” stacked arrangement, including, starting from the (e.g., Cu) metallization  10 :
         a first Ni layer  141 ,   a first (thin) Pd layer  161 ,   a second Ni layer  142 ,   a second Pd layer  162 .       

     In one or more embodiments, a (thin, e.g., 0.1-0.5 micron 0.1-0.5×10 −6  m) layer  161  of a ductile material, e.g., Pd may be provided between two Ni layers  141 ,  142 . 
     In one or more embodiments, the presence of the layer  161  (Pd, or possibly, other ductile materials such as, e.g., Au) may lead to the Ni stress being “de-coupled” into two separate contributes, lower in magnitude due to the ductility of the layer  161 . 
     Even without wishing to be bound to any specific theory in that respect, the ductility of an, e.g., Pd interlayer may be held to absorb the mechanical stress during a thermal cycle. 
     Also, one or more embodiments may benefit from Ni deposition on, e.g., Pd being practicable without any Ni surface chemical pre-treatment. 
     Additionally, no differences may be observed on wafers (dice) by optical inspection, see, e.g., the exemplary enlarged view of  FIG. 1 . 
     In one or more embodiments by resorting to an alternate deposition of, e.g., Ni/Pd/Ni/Pd (see, e.g.,  141 ,  161 ,  142 ,  162 ) on, e.g., copper could reduce the stress effect due to the ductility of Pd interlayer that can absorb the mechanical stress during the thermal cycle. 
     One or more embodiments may facilitate meeting with request specifications for power packages used, e.g., in the automotive field. 
     As indicated, one or more embodiments may include stacked depositions other than Ni (layer  141 )-Pd (layer  161 )-Ni (layer  142 )-Pd (layer  162 ). 
     Such alternative depositions may include, e.g.,
         using another ductile material (e.g., Au) for the layer  161 , and/or   an outer layer (e.g., Au as schematically indicated in chain line as  18  in  FIG. 3 ) at the outer surface of the stack.       

     Depositions such as:
         (Cu) Ni—Pd—Ni—Pd—Au   (Cu) Ni—Au—Ni—Pd   (Cu) Ni—Au—Ni—Pd—Au
 
are thus exemplary of such alternative deposition options.
       

     The following may be exemplary thickness values for layers in a stack according to one or more embodiments:
         layer  141 : 0.1-0.5 micron (0.1-0.5×10 −6  m)   layer  161 : 0.1-0.5 micron (0.1-0.5×10 −6  m   layer  142 : 0.5-1.5 micron (0.5-1.5)×10 −6  m   layer  162 : 0.2-0.5 micron (0.2-0.5×10 −6  m       

     One or more embodiments may thus provide a method of manufacturing semiconductor devices including at least one metallization (e.g.,  10 ), the method including:
         providing (e.g., by e-less deposition) a capping stack (e.g.,  141 ,  161 ,  142 ,  162 ) onto said metallization, wherein said stack includes at least one nickel layer,   including in said stack a pair of nickel layers (e.g.,  141 ,  142 ) having sandwiched therebetween a layer of ductile material (e.g.,  161 ).       

     In one or more embodiments, said ductile material may be selected out of palladium (Pd) and gold (Au). 
     One or more embodiments may include providing said metallization as a copper metallization, optionally as a Re-Distribution Layer—RDL metallization. 
     One or more embodiments may include providing in said stack, opposed said metallization, at least one outer layer (e.g.,  162 ,  18 ) of ductile material. 
     One or more embodiments may include providing in said stack, opposed said metallization, a first outer layer (e.g.,  162 ) including palladium and an outermost layer (e.g.,  18 ) including gold. 
     One or more embodiments may include providing a barrier layer (e.g.,  12 ) underlying said at least one metallization. 
     In one or more embodiments, said barrier layer underlying said at least one metallization may include TiW. 
     One or more embodiments may include providing the capping stack adjoining said barrier layer (see, e.g.,  FIG. 3 , bottom right) to provide full coverage of said at least one metallization. 
     One or more embodiments may provide a semiconductor device including:
         at least one metallization (e.g.,  10 ), and   a capping stack (e.g.,  141 ,  161 ,  142 ,  162 ;  18 ) provided onto said metallization, wherein said stack includes a pair of nickel layers having a layer of ductile material therebetween.       

     In one or more embodiments:
         said ductile material ( 161 ) may be selected out of palladium and gold, and/or   the stack may include, opposed said metallization, at least one outer layer of ductile material.       

     Without prejudice to the underlying principles, the details and embodiments may vary, even significantly, with respect to what has been disclosed merely by way of example, without departing from the extent of protection. 
     The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.