Patent Publication Number: US-10776079-B2

Title: True random number generation device and generation method thereof

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application claims the priority benefit of Taiwan application serial no. 107118626, filed on May 31, 2018. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification. 
     BACKGROUND 
     Technical Field 
     The disclosure relates to a true random number generation device and a true random number generation method that provide numbers of a plurality of bits. 
     Description of Related Art 
     Currently, common random number generation devices may be divided into pseudo random number generation devices and true random number generation devices. 
     The pseudo random number generation device is mainly implemented by a linear feedback shift register, and may generate evenly-distributed pseudo random numbers of a plurality of bits. However, the pseudo random numbers generated by the pseudo random number generation device are still periodic. Consequently, the generating rule of the pseudo random numbers may be solved by a logic operation. Compared to the pseudo random number generation device, the true random number generation device has no periodicity. Consequently, the true random numbers generated by the true random number generation device are unpredictable. However, since a plurality of true random number generation devices are required to generate true random numbers of a plurality of bits, the design of the true random number generation device takes up more layout space. Besides, the true random number generation device is primarily based on an analog circuit and results in more power consumption in operation. Accordingly, it is not easy for the true random number generation device to generate true random numbers with more bits. 
     SUMMARY 
     The disclosure provides a true random number generation device and a true random number generation method for generating unpredictable true random numbers of a plurality of bits. 
     The true random number generation device in this disclosure includes a selection signal providing circuit and a linear feedback shift register. The selection signal providing circuit is configured to provide a true random selection signal. The linear feedback shift register is coupled to the selection signal providing circuit. The linear feedback shift register is configured to generate a plurality of true random numbers. The linear feedback shift register includes true random number generators of a plurality of stages, and the true random number generators of the plurality of stages are coupled to one another in series. A Nth stage true random number generator among the true random number generators receives a clock signal, a N−1th bit true random number and the true random selection signal. The Nth stage true random number generator generates a plurality of Nth stage output logic values according to the clock signal and the N−1th bit true random number, and selects one of the plurality of Nth stage output logic values to be a Nth bit true random number according to the true random selection signal. Herein N is a natural number greater than or equal to 2. 
     A true random number generation method in this disclosure is adapted to generate true random numbers of a plurality of bits. The true random number generation method in one of exemplary embodiments is provided hereinafter. A true random selection signal is provided. A clock signal and a N−1th bit true random number are received, and a plurality of Nth stage output logic values are generated according to the clock signal and the N−1th bit true random number. One of the plurality of Nth stage output logic values is selected to be a Nth bit true random number according to the true random selection signal. Herein N is a natural number greater than or equal to 2. 
     Based on the foregoing, in this disclosure, the plurality of output logic values are generated according to the clock signal and the true random number of the previous-stage bit, and one of the plurality of output logic values is selected to be the true random number according the true random selection signal, thereby generating the unpredictable true random numbers of a plurality of bits. 
     To make the aforementioned and other features and advantages of the disclosure more comprehensible, several embodiments accompanied with drawings are described in detail as follows. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The accompanying drawings are included to provide a further understanding of the disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the disclosure and, together with the description, serve to explain the principles of the disclosure. 
         FIG. 1  is a schematic view showing a true random number generation device according to a first embodiment of the disclosure. 
         FIG. 2  is a circuit diagram schematically showing a true random number generation device according to a second embodiment of the disclosure. 
         FIG. 3  is a flowchart showing a true random number generation method according to an embodiment of the disclosure. 
         FIG. 4  is a circuit diagram schematically showing a true random number generation device according to a third embodiment of the disclosure. 
     
    
    
     DESCRIPTION OF THE EMBODIMENTS 
     Please refer to  FIG. 1 .  FIG. 1  is a schematic view showing a true random number generation device according to a first embodiment of the disclosure. In the embodiment shown in  FIG. 1 , a true random number generation device  100  includes a selection signal providing circuit  110  and a linear feedback shift register  120 . The selection signal providing circuit  110  is configured to provide a true random selection signal SS. The linear feedback shift register  120  is coupled to the selection signal providing circuit  110 . In this embodiment, the linear feedback shift register  120  is configured to generate true random numbers TRN( 1 ) to TRN(N) of a plurality of bits. The linear feedback shift register  120  includes true random number generators  121 ( 1 ) to  121 (N) of a plurality of stages. The true random number generators  121 ( 1 ) to  121 (N) are coupled to one another in series. In this embodiment, the 2nd stage true random number generator  121 ( 2 ) receives a clock signal CLK and a 1st bit true random number TRN( 1 ). The 2nd stage true random number generator  121 ( 2 ) generates a plurality of 2nd stage output logic values according to the clock signal CLK and the 1st bit true random number TRN( 1 ), and selects one of the plurality of 2nd stage output logic values to be a 2nd bit true random number TRN( 2 ) according to the true random selection signal SS. The 3rd stage true random number generator (not shown) receives the clock signal CLK and the 2nd bit true random number TRN( 2 ). The 3rd stage true random number generator generates a plurality of 3rd stage output logic values according to the clock signal CLK and the 2nd bit true random number TRN( 2 ), and selects one of the plurality of 3rd stage output logic values to be a 3rd bit true random number TRN( 3 ) according to the true random selection signal SS, and so on and so forth. 
     In this embodiment, the linear feedback shift register  120  further includes a logic operation circuit  122 . The logic operation circuit  122  is coupled to at least two of the true random number generators  121 ( 1 ) to  121 (N). The logic operation circuit  122  is configured to receive at least two of the true random numbers and to perform a logic operation to generate a logic operation result LR. For example, the logic operation circuit  122  is coupled to the true random number generators  121 ( 1 ) and  121 (N). The logic operation circuit  122  is configured to receive the 1st bit true random number TRN( 1 ) provided by the true random number generator  121 ( 1 ) and the Nth bit true random number TRN(N) provided by the true random number generator  121 (N), and to perform a logic operation on the 1st bit true random number TRN( 1 ) and the Nth bit true random number TRN(N) to generate the logic operation result LR. After generating the logic operation result LR, the logic operation circuit  122  provides the logic operation result LR to the 1st stage true random number generator  121 ( 1 ). The 1st stage true random number generator  121 ( 1 ) is configured to receive the clock signal CLK and the logic operation result LR, and to generate a plurality of 1 st stage output logic values according to the clock signal CLK and the logic operation result LR. Besides, the 1st stage true random number generator  121 ( 1 ) selects one of the plurality of 1st stage output logic values to be the 1st bit true random number TRN( 1 ) according to the true random selection signal SS. 
     The logic operation circuit in this disclosure may be one or more in number, which is not particularly limited herein. 
     Next, the 1st stage true random number generator  121 ( 1 ) provides the 1st bit true random number TRN( 1 ) to the 2nd stage true random number generator  121 ( 2 ), and the cycle continues accordingly. The true random number generators  121 ( 1 ) to  121 (N) may generate unpredictable true random numbers TRN( 1 ) to TRN(N) respectively and continuously. The linear feedback shift register  120  organizes the true random numbers TRN( 1 ) to TRN(N) of a plurality of bits to generate a set of true random numbers of a plurality of bits in a binary form. In this disclosure, the number of the true random number generators is greater than or equal to 2, and the number of the true random numbers as generated is also greater than or equal to 2. In the true random number generation device of this disclosure, the number of the true random number generators may be arranged according to the required bits of the true random numbers. 
     In this embodiment, the selection signal providing circuit  110  may be a circuit complying with the calculation principle of chaotic algorithm, and is configured to provide the true random selection signal SS in a single-bit form. 
     It should be noted here that the true random selection signal SS in this embodiment is an unpredictable true random number. Accordingly, in the true random number generators  121 ( 1 ) to  121 (N) of the plurality of stages, by means of the true random selection signal SS, one of the plurality of output logic values of the true random number generators  121 ( 1 ) to  121 (N) of the plurality of stages may be randomly selected to generate the true random numbers TRN( 1 ) to TRN(N) of a plurality of bits, respectively. Besides, the true random selection signal SS may be a true random number in a single-bit form. Consequently, the selection signal providing circuit  110  may occupy less layout space. Compared to the selection signal providing circuit that provides true random numbers of a plurality of bits, the selection signal providing circuit  110  configured to provide single-bit true random numbers may have lower power consumption. 
     Furthermore, please refer to  FIG. 2 .  FIG. 2  is a circuit diagram schematically showing a true random number generation device according to a second embodiment of the disclosure. In the embodiment shown in  FIG. 2 , for the purpose of convenient illustration, a linear feedback shift register  220  includes three true random number generators  221 ( 1 ) to  221 ( 3 ). The true random number generator  221 ( 1 ) includes a flip-flop  2212 ( 1 ), an inverter  2214 ( 1 ) and a selection circuit  2216 ( 1 ). The true random number generator  221 ( 2 ) includes a flip-flop  2212 ( 2 ), an inverter  2214 ( 2 ) and a selection circuit  2216 ( 2 ). The true random number generator  221 ( 3 ) includes a flip-flop  2212 ( 3 ), an inverter  2214 ( 3 ) and a selection circuit  2216 ( 3 ). 
     In this embodiment, the flip-flop  2212 ( 1 ) has a data input terminal D( 1 ), a clock input terminal CK( 1 ) and a data output terminal Q( 1 ). The data input terminal D( 1 ) is configured to receive a logic operation result LR, and the clock input terminal CK( 1 ) is configured to receive a clock signal CLK. The flip-flop  2212 ( 1 ) generates a first logic value R 1 ( 1 ) according to the logic operation result LR and the clock signal CLK, and outputs the first logic value R 1 ( 1 ) via the data output terminal Q( 1 ). An input terminal of the inverter  2214 ( 1 ) is coupled to the data output terminal Q( 1 ) of the flip-flop  2212 ( 1 ). The inverter  2214 ( 1 ) is configured to receive the first logic value R 1 ( 1 ) and to generate a second logic value R 2 ( 1 ) after an inverse calculation is performed. In other words, in this embodiment, a plurality of 1st stage output logic values include the first logic value R 1 ( 1 ) and the second logic value R 2 ( 1 ). The selection circuit  2216 ( 1 ) is coupled to the data output terminal Q( 1 ) of the flip-flop  2212 ( 1 ), an output terminal of the inverter  2214 ( 1 ) and a selection signal providing circuit  210 . The selection circuit  2216 ( 1 ) is controlled by a true random selection signal SS in a single-bit form, and selects one of the first logic value R 1 ( 1 ) and the second logic value R 2 ( 1 ) to be a 1st bit true random number TRN( 1 ) according to the true random selection signal SS. 
     For example, when the logic value of the true random selection signal SS is “0”, the selection circuit  2216 ( 1 ) then selects the first logic value R( 1 ) to be the 1st bit true random number TRN( 1 ). On the contrary, when the logic value of the true random selection signal SS is “1”, the selection circuit  2216 ( 1 ) then selects the second logic value R 2 ( 1 ) to be the 1st bit true random number TRN( 1 ). 
     In this embodiment, the selection circuit  2216 ( 1 ) may be implemented by a 2-to-1 multiplexer. The selection circuit  2216 ( 1 ) has a first input terminal, a second input terminal, a control terminal and an output terminal. The first input terminal of the selection circuit  2216 ( 1 ) is coupled to the data output terminal Q( 1 ) for receiving the first logic value R 1 ( 1 ). The second input terminal of the selection circuit  2216 ( 1 ) is coupled to the output terminal of the inverter  2214 ( 1 ) for receiving the second logic value R 2 ( 1 ). The control terminal of the selection circuit  2216 ( 1 ) is coupled to the selection signal providing circuit  210  for receiving the true random selection signal SS. The output terminal of the selection circuit  2216 ( 1 ) is configured to provide the 1st bit true random number TRN( 1 ). In other embodiments, the selection circuit  2216 ( 1 ) may be implemented by a transmission gate. 
     The flip-flop  2212 ( 2 ) has a data input terminal D( 2 ), a clock input terminal CK( 2 ) and a data output terminal Q( 2 ). The data input terminal D( 2 ) is configured to receive the 1st bit true random number TRN( 1 ), and the clock input terminal CK( 2 ) is configured to receive the clock signal CLK. The flip-flop  2212 ( 2 ) generates a first logic value R 1 ( 2 ) according to the 1st bit true random number TRN( 1 ) and the clock signal CLK, and outputs the first logic value R 1 ( 2 ) via the data output terminal Q( 2 ). In other words, in this embodiment, a plurality of 2nd stage output logic values include the first logic value R 1 ( 2 ) and a second logic value R 2 ( 2 ). An input terminal of the inverter  2214 ( 2 ) is coupled to the data output terminal Q( 2 ) of the flip-flop  2212 ( 2 ). The inverter  2214 ( 2 ) is configured to receive the first logic value R 1 ( 2 ) and to perform an inverse calculation on the first logic value R 1 ( 2 ) to generate the second logic value R 2 ( 2 ). The selection circuit  2216 ( 2 ) is coupled to the data output terminal Q( 2 ) of the flip-flop  2212 ( 2 ), an output terminal of the inverter  2214 ( 2 ) and the selection signal providing circuit  210 . The selection circuit  2216 ( 2 ) is controlled by the true random selection signal SS to receive the first logic value R 1 ( 2 ) and the second logic value R 2 ( 2 ). The selection circuit  2216 ( 2 ) selects one of the first logic value R 1 ( 2 ) and the second logic value R 2 ( 2 ) to be a 2nd bit true random number TRN( 2 ) according to the true random selection signal SS. 
     The flip-flop  2212 ( 3 ) has a data input terminal D( 3 ), a clock input terminal CK( 3 ) and a data output terminal Q( 3 ). The data input terminal D( 3 ) is configured to receive the 2nd bit true random number TRN( 2 ), and the clock input terminal CK( 3 ) is configured to receive the clock signal CLK. The flip-flop  2212 ( 3 ) generates a first logic value R 1 ( 3 ) according to the 2nd bit true random number TRN( 2 ) and the clock signal CLK, and outputs the first logic value R 1 ( 3 ) via the data output terminal Q( 3 ). An input terminal of the inverter  2214 ( 3 ) is coupled to the data output terminal Q( 3 ) of the flip-flop  2212 ( 3 ). The inverter  2214 ( 3 ) is configured to receive the first logic value R 1 ( 3 ) and to perform an inverse calculation on the first logic value R 1 ( 3 ) to generate a second logic value R 2 ( 3 ). In other words, in this embodiment, a plurality of 3rd stage output logic values include the first logic value R 1 ( 3 ) and the second logic value R 2 ( 3 ). The selection circuit  2216 ( 3 ) is coupled to the data output terminal Q( 3 ) of the flip-flop  2212 ( 3 ), an output terminal of the inverter  2214 ( 3 ) and the selection signal providing circuit  210 . The selection circuit  2216 ( 3 ) is controlled by the true random selection signal SS to receive the first logic value R 1 ( 3 ) and the second logic value R 2 ( 3 ). The selection circuit  2216 ( 3 ) selects one of the first logic value R 1 ( 3 ) and the second logic value R 2 ( 3 ) to be a 3rd bit true random number TRN( 3 ) according to the true random selection signal SS. 
     In this embodiment, a logic operation circuit  222  includes an XOR gate XOR. The XOR gate XOR has two input terminals. The two input terminals of the XOR gate XOR are respectively coupled to the true random number generators  221 ( 1 ) and  221 ( 3 ) to receive the 1st bit true random number TRN( 1 ) and the 3rd bit true random number TRN( 3 ). The XOR gate XOR performs a logic operation on the 1st bit true random number TRN( 1 ) and the 3rd bit true random number TRN( 3 ) to generate the logic operation result LR. In this embodiment, if a logic calculation based on the XOR gate XOR is performed with the 1st bit true random number TRN( 1 ) and the 3rd bit true random number TRN( 3 ) being the same, a logic operation circuit  322  then provides a logic value of “0” as the logic operation result LR. Otherwise, the logic operation circuit  322  provides a logic value of “1” as the logic operation result LR. 
     Please refer to  FIG. 2  and  FIG. 3  simultaneously.  FIG. 3  is a flowchart showing a true random number generation method according to an embodiment of the disclosure. In step S 310 , a true random selection signal SS is provided. In step S 320 , a clock signal and a N−1th bit true random number are received, and a plurality of Nth stage output logic values are generated according to the clock signal and the N−1th bit true random number. Taking the true random number generator  221 ( 2 ) as an example, the true random number generator  221 ( 2 ) receives the clock signal CLK and the 1st bit true random number TRN( 1 ), and generates the first logic value R 1 ( 2 ) and the second logic value R 2 ( 2 ) of the 2nd stage output logic values according to the 1st bit true random number TRN( 1 ). Next, in step S 330 , one of the plurality of Nth stage output logic values is selected to be a Nth bit true random number according to the true random selection signal SS. Similar to the foregoing example, the true random number generator  221 ( 2 ) selects one of the first logic value R 1 ( 2 ) and the second logic value R 2 ( 2 ) to be the 2nd bit true random number TRN( 2 ) according to the true random selection signal SS. 
     Please refer to  FIG. 4 .  FIG. 4  is a circuit diagram schematically showing a true random number generation device according to a third embodiment of the disclosure. Different from  FIG. 2 , in a 1st stage true random number generator  421 ( 1 ) of this embodiment, a flip-flop  4212 ( 1 ) may provide a first logic value R 1 ( 1 ) via a data output terminal Q( 1 ), and provide a second logic value BR 1 ( l ) via an inverted data output terminal BQ( 1 ). A first input terminal of a selection circuit  4216 ( 1 ) is coupled to the data output terminal Q( 1 ) and is configured to receive the first logic value R 1 ( 1 ), and a second input terminal of the selection circuit  4216 ( 1 ) is coupled to the inverted data output terminal BQ( 1 ) and is configured to receive the second logic value BR 1 ( 1 ). Accordingly, the selection circuit  4216 ( 1 ) selects one of the first logic value R 1 ( 1 ) and the second logic value BR 1 ( 1 ) to be a 1st bit true random number TRN( 1 ) according to a true random selection signal SS. 
     In a 2nd stage true random number generator  421 ( 2 ), a flip-flop  4212 ( 2 ) may provide a first logic value R 1 ( 2 ) via a data output terminal Q( 2 ), and provide a second logic value BR 1 ( 2 ) via an inverted data output terminal BQ( 2 ). A first input terminal of a selection circuit  4216 ( 2 ) is configured to receive the first logic value R 1 ( 2 ), and a second input terminal of the selection circuit  4216 ( 2 ) is configured to receive the second logic value BR 1 ( 2 ). Accordingly, the selection circuit  4216 ( 2 ) selects one of the first logic value R 1 ( 2 ) and the second logic value BR 1 ( 2 ) to be a 2nd bit true random number TRN( 2 ) according to the true random selection signal SS. The configuration of a 3rd stage true random number generator  421 ( 3 ) is also similar to that of the 2nd stage true random number generator  421 ( 2 ), so details thereof are not repeated hereinafter. 
     To summarize, in this disclosure, the plurality of output logic values are generated according to the clock signal and the true random number of the previous-stage bit. The true random selection signal is an unpredictable true random number. Accordingly, by means of the true random selection signal, one of the plurality of output logic values is randomly selected to be the true random number, thereby making the true random number unpredictable. Besides, even the true random selection signal in a single-bit form may achieve the foregoing effect. Consequently, the selection signal providing circuit may occupy less layout space and have lower power consumption. 
     Although the embodiments are already disclosed as above, these embodiments should not be construed as limitations on the scope of the disclosure. It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed embodiments without departing from the scope or spirit of the disclosure. In view of the foregoing, it is intended that the disclosure covers modifications and variations provided that they fall within the scope of the following claims and their equivalents.