Patent Publication Number: US-6215353-B1

Title: Stable voltage reference circuit

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates to a temperature-compensated, solid-state voltage reference. 
     2. Description of the Related Art 
     Stable voltage references traditionally called “bandgap references” are commonly used in a wide variety of applications, including telecommunications. These references typically combine a small voltage, which is directly proportional to absolute temperature, with a larger voltage, which has a negative temperature coefficient. The two voltages are produced by two different diodes operating at current densities typically in the range of 10:1. The voltage difference between the two is then amplified by a DC amplifier with a gain that is established by the ratio of a polysilicon resistor divider. The goal of this voltage combination is to produce a substantially constant reference voltage over a wide temperature range. 
     There are, however, several sources of problems one encounters when trying to realize accurate, stable voltages using these conventional temperature-compensating voltage references. For example, the small difference between the voltages is directly proportional to absolute temperature. This voltage difference is typically only about 60 mV, but it varies approximately 0.2 mV per degree Celsius. 
     Because the voltage that is proportional to absolute temperature is small, the initial amplifier offset voltage can produce large changes in the reference voltage. For example, a 1.2 mV change in amplifier offset voltage can produce a 10 mV change in the initial reference voltage. In addition, small variations in the amplifier offset voltage or stress-induced changes in the polysilicon resistor divider ratio can produce large changes in the reference voltage. 
     Other sources of error include small variations in temperature between the diode elements themselves. For example, a temperature difference of less than 0.5° C. between diode elements or amplifier input elements can produce a voltage difference of 1 mV at the reference output. Such errors can be significant, particularly during the time after switching from standby to full power in the chip that incorporates the reference. 
     A typical design goal for a voltage reference is the production of a device with better than one percent accuracy over a wide temperature range. Despite considerable research effort, only a few manufacturers of integrated circuits have been able to obtain such accuracy. Even where this accuracy has been achieved, however, it has typically been necessary to add complex circuits to the basic design discussed above. This, in turn, has required considerable chip area in order to compensate for several undesirable effects in the basic reference circuit. These circuits commonly include, for example, trimming circuits capable of adjusting the reference voltage after wafer probe and packaging. 
     In addition to increased chip area, these designs normally also require significant testing time to adjust the reference voltage. Unfortunately, reference voltage adjustments made at the wafer probe do not generally hold through the packaging process. Stress induced by the packaging process typically causes an accuracy in the voltage reference of better than one percent to become worse than one percent after packaging. 
     What is needed is therefore a voltage reference that provides the desired accuracy not only in theory but in practice, even after packaging, that does not require complex additional circuitry or long testing periods, and that can be implemented using easily calibrated and matched components. 
     SUMMARY OF THE INVENTION 
     The invention meets this need by providing a stable voltage reference circuit that has a single reference diode junction, which may be implemented, for example, as a single diode junction or as a junction of a diode-coupled transistor. A current generating arrangement alternately generates and applies to the diode junction a first current and a second current. The second current is larger than the first current, and a voltage over the diode junction thereby alternates between a first AC input voltage (V 1 ) that has a positive temperature dependence (dV 1 /dT) and a second AC input voltage (V 2 ) that has a negative temperature dependence (dV 2 /dT). Combining circuitry is included for adding the first and second input voltages and for thereby generating an output voltage (Vref) substantially constant with absolute temperature. 
     The current generating arrangement preferably comprises two different current sources—a first current source that generates the first current and a second current source that generates the second current. A first switch then alternately switches the first and second currents into the single reference diode junction. 
     The combining circuitry preferably includes an amplifier that has, for the first input voltage, a gain substantially equal to the ratio of the negative temperature dependence divided by the positive temperature dependence. The amplifier is preferably part of an amplification arrangement in which the amplifier is an AC amplifier with input and feedback elements that include a monolithic capacitor network. 
     The preferred embodiment of the voltage reference circuit includes a capacitor network that determines the gain of the amplifier. This capacitor network preferably includes a first capacitor with a first capacitance (C 1 ) in a first signal path for the first input voltage and a second capacitor with a second capacitance (C 2 ) in a second signal path for the second input voltage, in which both signal paths lead to a summing junction of the amplification means and the ratio of C 2  to C 1  is equal to the gain of the amplification means. 
     A second switch is preferably included in the invention and is connected, via the second capacitor, to the summing junction. The second switch alternately connects the summing junction, via the second capacitor, to the first input voltage when the first input voltage is equal to a maximum input voltage and otherwise to a system ground. 
     In the preferred embodiment of the invention, the voltage reference circuit further has a feedback path from the output voltage (Vref) to a summing junction of the amplification amplifier. A third switch is then preferably included in the feedback path to alternately connect the summing junction, via a third capacitor, to either the output voltage Vref or to circuit ground. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 shows the main components of a matched-diode voltage reference according to the prior art. 
     FIG. 2 shows the voltage reference according to the invention, which has a single reference diode junction. 
     FIG. 3 illustrates the voltage over the single diode or diode-connected transistor. 
     FIG. 4 shows a MOS implementation of a resitive element used in the preferred embodiment of the invention. 
    
    
     DETAILED DESCRIPTION 
     Although FIG. 1 shows the main components of a matched-diode voltage reference according to the prior art, it is helpful to study its structure at least cursorily because the concepts used in the invention will then become clearer, as will the advantages of the invention. 
     In the conventional arrangement illustrated in FIG. 1, two currents I 1  and I 2  are generated in a conventional manner and are passed to ground through respective diodes D 1  and D 2 . In practice, these elements will typically be implemented as diode-connected PNP transistors, with the emitter-base junctions forming the “diodes.” These elements are therefore referred to below as either “diodes” or “transistors” D 1  and D 2 , since, regardless of how they are implemented, their functions and electrical properties will be the same. In this discussion, “I 1 ” and “I 2 ” refer to the currents through resistors R 1 , for I 1 , and through R 2 +R 3 , for I 2 .) It is known that: 
     
       
           I=k·A· exp ( V/V   t ), 
       
     
     where: 
     I is the emitter current; 
     k is a known constant; 
     A is the emitter-base junction area; 
     V is the emitter-base junction voltage; and 
     V t  is a known, temperature-dependent voltage parameter that is roughly 0.026 V at the standard temperature of 27° C. (300° K), which is a typical operating temperature for voltage reference circuits. 
     Dual-diode voltage reference circuits such as the one illustrated in FIG. 1 typically apply equal currents (I 1 =I 2 ) to the emitters, but the emitter areas are unequal, which results in different emitter current densities. For example, if the diode D 1  has an emitter area A 1 , then the diode D 2  may have an emitter area A 2 =r·A 1 . Substituting these values in the expression above, setting I 1 =I 2  (or, equivalently, letting A 1 =A 2  and generating I 1 =r·I 2 ), and taking the ratio of I 1  to I 2 , one finds the following difference between the voltages V 1 , V 2  at the D 1 , D 2  emitters to be: 
     
       
           V   1 − V   2 = V   t ·In [( A   2 / A   1 )·(I 1 /I 2 )]= V   t ·In ( r ) 
       
     
     Now assume that r=10, which is a typical value. Then (V 1 −V 2 )—the difference voltage—becomes 0.060 V, that is, 60 mV, for V t =0.026. Note, however, that V t  is proportional to absolute temperature and is often referred to in the literature as the “thermal voltage.” V 1 −V 2  is therefore proportional to absolute temperature and is commonly referred to as the “PTAT voltage.” On the other hand, as long as I 1  and I 2  are kept equal and within normal ranges, the PTAT voltage remains relatively constant at 60 mV, independent of I 1  and I 2 . 
     As is well known, the voltage V 2  across a conventionally fabricated transistor (diode-connected) such as D 2  is approximately 650 mV. It can also be shown that, at the standard temperature of about +27° C., this voltage V 2  decreases approximately 1.6 mV/° C.; at −40° C., however, V 2  decreases about 1.8 mV/° C.; and at +85° C., it decreases around 2.0 mV/° C. In other words, the temperature sensitivity of the voltage over the D 2  junction is non-linear—it “bends” downward as the temperature increases. 
     On the other hand, as the expression (V 1 −V 2 )=V t ·In (r) shows, the PTAT voltage increases linearly with increasing temperature (since V t , increases). It can be shown that, in this example, the PTAT voltage (V 1 −V 2 ) increases approximately 0.22 mV/° C. and that this temperature dependency is essentially linear at all expected operating temperatures. Increases in temperature that cause the PTAT or “diode difference” voltage to rise therefore will cause the larger voltage V 2  itself to fall. 
     Quantitatively, the change in the PTAT voltage (V 1 −V 2 ) is approximately +0.22 mV/° C., whereas the change in V 2  at mid-range temperature is approximately −1.87 mV/° C., which is 8.5 times greater than the change in the PTAT voltage. This PTAT voltage is then amplified by the gain-setting resistor ratio R 3 /(R 2 +R 3 ), where the gain is chosen to be 8.5, which produces an output of 510 mV with a temperature dependence of 8.5*(0.22)=+1.87 mV/° C. In other words, the PTAT voltage is amplified so that the resulting amplified signal&#39;s temperature dependence is of the same magnitude but of opposite polarity as that of the voltage V 2 . 
     Near the middle of the operating temperature range, the deviations in the amplified PTAT voltage and in V 2  thus theoretically “cancel” each other upon addition. To perform this “addition,” the amplified PTAT voltage and the voltage V 1  over the junction of transistor D 1  (which, as is mentioned above, is connected to function as a diode) are summed by these scaling resistors R 2 , R 3  in the output stage of FIG.  1 . In the illustrated example, the resistors R 1 , R 2  and R 3  are assumed to have been selected using conventional methods to produce the desired output reference voltage, Vref of, for example, 1.2 V, which is nearly temperature-independent and approximately equal to the bandgap voltage of silicon. 
     As is mentioned above, there are several problems with this conventional design. First the polysilicon resistor divider ratio R 2 /(R 2 +R 3 ) must be precisely and exactly matched, as must the currents over the transistor junctions, which are set by the ratio R 1 /(R 2 +R 3 ). Second, the “diode” temperatures must be as nearly equal as possible. Observe not only that the exact matching of resistors is relatively difficult, but also that the task is complicated by the fact that the resistor values used are subject to local values of wafer stress, which change with temperature and after encapsulation in the packaging process. Third, the DC offset voltage of the operational amplifier G 1  changes with temperature and packaging stress, particularly if it is fabricated using MOS technology. 
     FIG. 2 illustrates the stable voltage reference circuit according to the invention. The various components and their interconnections are described first. Thereafter, values are assigned to the components in order to demonstrate how the circuit works and why it works better than the prior art. 
     In the invention, two primary current sources I 1  and I 2  (or a single current generator that is able to switch between generating currents I 1  and I 2 ) are provided as before, but only a single primary reference diode is needed. In the preferred embodiment of the invention, the diode is constructed from a diode-connected PNP transistor Q 1 . The function and properties of Q 1  are therefore the same as for a “normal” diode. Using MOS technology to fabricate the transistor, Q 1  has a typical emitter area of 50 μm 2 , the N-Well serves as the base and is connected to circuit ground, and the collector is the P-type substrate. 
     In FIG. 2, two voltage values Vdd and Vss are shown. Vdd is the highest voltage and is provided by any conventional voltage source (not shown); Vss is the substrate voltage. 
     According to the invention, the first current source I 1  is always connected to Q 1 , whereas the second current source I 2  is switched by a conventional solid-state switch SW 1  either into Q 1 , or via a dummy load such as a diode-connected transistor Q 2  to ground. As the switch SW 1  switches between these two states, it creates an alternating voltage signal Vin that is converted to an alternating charge signal by an input capacitor C 1 . This alternating charge signal is then delivered to the summing junction J 1  of a gain element G 2 . 
     The Vin switching waveform is shown in FIG.  3 . The figure shows Vin switching between a base voltage Vbase and a maximum voltage Vmax with an AC amplitude equal to ΔV, which, in this example, is about 60 mV. The voltage ΔV is proportional to absolute temperature but is AC in nature, as opposed to the DC nature of the PTAT voltage in circuits of the prior art. Because the PTAT voltage is AC in nature, it can be amplified using AC gain elements. Moreover, the DC offset voltage of AC gain elements does not affect the accuracy of the AC output signal. 
     The summing junction J 1  is also connected, via a second capacitor C 2 , to a second solid state switch SW 2 . Switch SW 2  connects the C 2  input alternately to ground and to Vin. Switch SW 2  is phased, using known techniques, so that it connects C 2  to Q 1  when the voltage Vin is equal to Vmax. This occurs during the same clock phase when I 2  is connected to Q 1  by SW 1 . The charge delivered through C 2  is therefore proportional to Vmax. 
     In the prior art circuit of FIG. 1, the PTAT voltage was derived from two separate diodes by setting their current densities to be different by a factor of 10. IN contrast, in the circuit of the present invention, the PTAT voltage is derived from a single diode operating with a current density difference resulting from the difference between I 1  and I 2 . Where the desired current ratio is m, the required ratio I 2 /I 1 =m−1. Therefore if m=10 and I 1  is chosen to be 15 μA in the preferred embodiment of the present invention, I 2 =I 1  (m−1) or 135 μA. 
     With reference to FIG. 3, it can be shown that the temperature dependence of ΔV is proportional to Vo(Tk/300), where Vo is the voltage at a baseline temperature of 300° K and Tk is the temperature in degrees Kelvin. Thus the PTAT temperature coefficient d(ΔV)/dT=+0.22 mV/° C. 
     On the other hand, Vmax has the non-linear temperature dependency described previously, that is approximately −1.6 mV/° C. at −40° C., −1.8 mV/° C. at 27° C., and −2.0 mV/° C. at +85° C. In other words, ΔV depends linearly on absolute temperature (T) whereas Vmax does not. For a nominal design where a near-zero temperature coefficient of voltage is desired near the middle of the operating temperature range, the 27° C. value of −1.8 mV/° C. may be assumed for the temperature coefficient of Vmax. 
     As in the prior art, the negative temperature dependence of 1.8 mV/° C. for Vmax is approximately equal to 8.5 times the positive temperature dependence of 0.22 mV/° C. for ΔV. In one embodiment of this invention, the capacitance of C 1 , which couples the PTAT voltage source Vin to the summing junction J 1 , is therefore chosen to be 8.5 times the capacitance of C 2 , which couples the Vmax negative temperature coefficient voltage source to the same summing junction J 1 . 
     The switching frequency of all switches is the same and may be chosen using normal design considerations. It should be low enough to ensure proper settling of all gain elements. In one prototype of the invention, for example, the switching frequency of SW 1  was chosen to be 9 MHz because gain-element settling time constants of a few nano-seconds (ns) are easily achieved using 0.35 μm CMOS technology. 
     The voltage reference circuit according to this invention achieves the correct output voltage Vref preferably by means of a feedback loop. This feedback loop includes a connection from the output voltage point Vref back to an input switch SW 3 , which alternately switches Vref and circuit ground to the input of a capacitor C 3 . The third switch SW 3  is synchronized, again, using any known technique, to the first two switches SW 1  and SW 2  such that SW 3  grounds the input of C 3  when switch SW 1  connects the second current source I 2  to Vin (that is, to Q 1 ) and switch SW 2  connects the capacitor C 2  to Vin (Q 1 ). 
     When the desired reference voltage Vref has been driven to the correct amplitude, the negative charge pulled from the summing junction J 1  through C 3  when SW 3  switches to ground will approximately equal the sum of the positive charge deposited on the input through C 1  as Vin switches from Vbase to Vmax and the positive charge deposited on the input when the input to C 2  switches from ground to Vmax. 
     Any charge errors will be amplified by the AC-coupled gain element G 2  in accordance with the value of the value of a feedback capacitor C 4 , which is coupled between the output of gain element G 2  and the summing junction J 1 , to produce an AC output voltage V 2 . When the negative charge pulled from summing junction J 1  through the capacitor C 3  is not quite equal to the positive charge from capacitors C 1  and C 2 , then the small positive charge will result in a negative output at V 2  when a switch SW 4  connects the summing junction J 2  of an amplifier G 3  to the output voltage V 2  via the capacitor C 5 . 
     A feedback resistor or resistive element R 4  is also included between the output of the gain element G 3  and the summing junction, in parallel with the feedback capacitor C 4 . The current across this resistor R 4  will typically be very small, on the order of 1 pA. The resistance of R 4  may therefore be high, on the order of 100 MΩ or higher, without causing any undesirable effects on the DC performance of the circuit. 
     The gain element G 2  therefore operates as a conventional AC amplifier and is not subject to the offset voltage inaccuracies of the prior art DC amplifiers used to amplify the small (approximately 60 mV) PTAT signal. The AC gain of element G 2  with respect to the signal Vin may therefore be quite high. For example, the gain from Vin to G 2  output is C 1 /C 4  and may, in a typical implementation, have a value such as 17 for C 1 =17 unit capacitors and C 4 =1 unit capacitor. 
     The invention preferably also includes a second, output stage, in which the switch SW 4  connects a summing junction J 2  of a gain element G 3  to capacitor C 5 , which forms a second-stage input capacitor, only when the switch SW 1  connects the second current source I 2  to Q 1 . In this case, a negative V 2  output causes a negative charge to be pulled from the summing junction J 2  through C 5 . This, in turn, causes the output of the gain element G 3  to rise in voltage as the charge is integrated across a feedback capacitor C 6 , which is connected between the output of G 3  and the summing junction J 2 . The voltage across C 6  will continue to rise on each successive switching cycle until the charge through C 3  approximately balances the sum of the charges through C 1  and C 2 . 
     When the switch SW 4  is not connected to the summing junction J 2 , it grounds the output of input capacitor C 5  so that the charge produced through C 5  is proportional only to the AC voltage output of the gain element G 2 , that is, not to the DC voltage. The operation of the AC amplifier element G 2  in combination with the switch SW 4  is known in the art as a carrier amplifier-demodulator. As such, the output voltage of switch SW 4  depends only on the AC component of the G 2  signal and not on the DC components, which are subject to variation from causes such as DC offset. 
     When the switch SW 4  closes to ground, the output of G 2  charges C 5  to a given voltage. On the opposite switch phase, the output of G 2  moves through an AC voltage depending on the error charge from the sum of the charges through C 1 , C 2  and C 3  to a new voltage. During the voltage change, SW 4  connects the C 5  output to the input of gain element G 3  so that only the charge from the voltage difference is passed through C 5 . 
     The charge produced through capacitor C 5  is thus integrated by the combination of the gain element G 3  and feedback capacitor C 6 , and this combination, in connection with the switch SW 4 , functions in a manner similar to a switched-capacitor integrator. As is known in the art, a switched-capacitor integrator has an advantage over a simple gain amplifier in that small input charge errors are integrated across the feedback capacitor (C 6 ) to drive the closed-loop error voltage toward zero. 
     Although the invention as described above provides a stable reference voltage, the invention preferably also include noise-canceling circuitry to further improve its performance. As illustrated in FIG. 2, this noise-canceling circuitry includes a third diode or diode-coupled transistor Q 3  and a third current source  13  that is coupled both to the substrate voltage Vss through Q 3  and to a capacitor C 12 B, which is connected to the “positive” input of the gain element G 3 . A capacitor C 34 B connects this positive input to ground. A noise cancellation capacitor C 5 B is also connected to ground. A switch SW 4 B connects the charge on C 5 B to either ground, or to the “positive” input of the gain element G 4 , which is also grounded through a capacitor C 6 B. 
     A resistor or resistive element R 4 B is connected from the positive input of G 2  to ground. Resistor R 4 B is preferably constructed in a similar fashion to resistor R 4 . Exact matching of the R 4  construction is not required, however, since DC characteristics are not critical and, without any semiconductor junctions connected to the input circuit, the current flow across either resistor is far below the level of a picoamp. 
     In the preferred embodiment of the invention, the resistive elements R 4  and R 4 B are constructed using an NMOS and PMOS device as shown in FIG.  4 . When the signal V 2  at the output of the amplifier G 2  (see FIG. 2) is near ground potential, the resistance of both MOS devices is very high and the amplifier feedback time constant R 4 ·C 4  is very long. 
     For large positive amplitude signals, or when the amplifier output DC value rises to voltages above ground of several hundred millivolts, the resistance of the NMOS device drops to provide negative feedback. For large negative amplitude signals, or when the output DC value drops to voltages below ground of several hundred millivolts, the resistance of the PMOS device drops to provide negative feedback. The action of the NMOS and PMOS devices thus tends to maintain the amplifier output approximately centered around ground potential. 
     The circuit elements I 3 , Q 3 , C 12 B, R 4 B, C 34 B and C 5 B have little effect on input charge amplification. They are rather present to provide some cancellation of any noise on input current sources I 1  and I 2 . It is well known in the art that for best noise cancellation, the current generated by I 3  should be comparable in amplitude to (I 1 +I 2 )/2, which, in one prototype of the invention, was roughly 75 μA. Also, the element Q 3  should be of construction similar to that of Q 1 . Furthermore, the various capacitors&#39; values should be chosen as follows: C 12 B=C 1 +C 2 , and C 34 B=C 3 +C 4 . 
     Circuit elements C 5 B, SW 4 B and C 6 B provide input noise cancellation for the integrating amplifier G 3 . It is well known that for best noise cancellation, C 5 B=C 5 , SW 4 B should switch in phase with SW 4 , and C 6 B=C 6 . A seventh capacitor C 7  is preferably also included from the output of the integrating amplifier G 3  to ground in order to absorb all additional noise generated by integrating amplifier G 3 , particularly during the switching of the G 3  input switch SW 4 . The capacitor C 7  may be a large off-chip ceramic capacitor of value such as 0.1 μF. Moreover, a resistive element R 5  is preferably included between output of G 3  and the capacitor C 7  in order to act as a loop stabilization resistance; R 5  should be chosen using normal design methods to provide a small high-frequency gain for stage G 3 . 
     The gain elements G 2  and G 3  are preferably implemented in conventional MOS technology and operational transconductance amplifiers (OTAs). The transconductances (gm) of G 2  and G 3  should, in typical implementations, be set at approximately 1 milli-mho. A value of 3 k Ohms for R 3  then gives a gm×R 3  value of 3 as the high-frequency, open-loop forward gain of stage G 3 . 
     Each of the capacitors used in the invention may be either a single device or a group of capacitors connected in parallel to provide the required capacitance. The choice will depend on conventional design considerations and is not essential to the invention. In the preferred embodiment of the invention, however, at least the capacitors C 1 , C 2 , and C 3  are fabricated as monolithic capacitor networks, since networks provide better tolerances and more stable capacitance ratios. The number of unit capacitors used for C 1 , C 2 , and C 3  may be chosen using normal design methods and is determined by the requirement for achieving a low temperature coefficient for the output voltage Vref. 
     It has been previously stated that in one embodiment of the present invention, the C 1  capacitance is chosen to be 8.5 times the C 2  capacitance. In order to construct C 1  and C 2  from unit capacitors, C 1  may, for example, be a network of  17  unit capacitors, while C 2  is a network of two unit capacitors. If C 3  is chosen to be two unit capacitors, then, for input charge balance, Vref (C 3 )=Vmax(C 2 )+ΔV(C 1 ). Or Vref=Vmax(C 2 /C 3 )+ΔV(C 1 /C 3 ). 
     The capacitance of C 12 B should be the equal to the sum of the capacitances for C 1 +C 2 , so that, given the values above, it should therefore be made up of a network of 19 capacitors. Similarly, C 34 B=C 3 +C 4  and should comprise three unit capacitors. The ratio C 5 /C 6  sets the integrator scale factor; setting this ratio to 1/8, for example, provides for stability in the overall Vref control loop. The value for C 5  may be selected to be, for example, four unit capacitors, or some other value that is significantly larger than the capacitances of the MOS switch devices. The capacitance of C 6  would in such case be 4*8=32 unit capacitors. Given these values of C 5  and C 6 , the capacitance values for C 5 B and C 6 B should therefore be chosen as C 5 B=4 and C 6 B=32 unit capacitors. 
     The size of the unit capacitors in the preferred embodiment is 100 femto-Farads (fF). The choice of 100 fF is typical of unit capacitors constructed in 0.35 μm CMOS technology. The design is not critical with regard to the size of the unit capacitors. With a baseline bias current of, for example, I 1 =15 μA, which was, in one prototype, selected for the diode-connected PNP device Q 1 , there is a sufficiently low drive resistance to drive the 19 unit capacitors in the C 1 +C 2  circuits quite rapidly. 
     It is well known that the highest dynamic resistance at the Q 1  emitter circuit is Vt/I 1 , where Vt, the thermal voltage, is approximately 26 mV and I 1  is the lowest current, or 15 μA. In that case, the highest resistance is approximately 1.7 kOhms, which is capable of driving the  19  unit capacitors and circuit parasitic capacitance with a time constant faster than 5 ns. 
     The MOS switch device widths and lengths are not critical and are constructed in accordance with standard design practice. They are preferably constructed at approximately three times minimum width. Using 0.35 μm CMOS technology, the width will therefore typically be about 1.0 μm and the length will typically be about 0.35 μm. 
     This invention teaches the use of a single diode or diode-connected transistor to provide both polarities of temperature compensation in a precision voltage reference. Note that Q 2  is provided only as a dummy load and Q 3  is used only in the optional noise-canceling circuit. This use of a single diode (or diode-connected transistor) to provide both polarities of temperature coefficient in combination with MOS capacitors and AC amplifiers has several advantages. The first is that there are no errors present due to the temperature or lithography differences between diodes of unequal area. The second is that it is possible to fabricate the invention with highly accurate circuits using MOS technologies rather than the bipolar technology required for most highly accurate designs.