Patent Publication Number: US-9431910-B1

Title: Energy recycling system and recycling method thereof

Description:
RELATED APPLICATIONS 
     This application claims priority to Taiwanese Application Serial Number 104110509, filed Mar. 31, 2015, which is herein incorporated by reference. 
     BACKGROUND 
     1. Field of Invention 
     The present disclosure relates to an energy recycling system and an energy recycling method thereof. More particularly, the present disclosure relates to an energy recycling system, which makes energy transferred between working circuits, and an energy recycling method thereof. 
     2. Description of Related Art 
     Due to the rise of environmental awareness, all circuits require energy saving, for example high power circuits for electrical generating systems, moderate power circuits such as electrical appliances and mobile phones, or even low power circuits such as logic circuits. Therefore, an energy saving system has entered the mainstream of present day technology. However, there are still many problems in the energy recycling system of the logic circuits which must be solved, such as utilizing a large number of transistors in order to provide the voltage source with multiple phases, the configuration of circuits being too complicated which may need a fully customized design, the voltage source generated being unstable, or the energy recycling system being only suited to the system with the bulk capacitor. 
     SUMMARY 
     The following presents a simplified summary of the disclosure in order to provide a basic understanding to the reader. This summary is not an extensive overview of the disclosure and it does not identify key/critical components of the present disclosure or delineate the scope of the present disclosure. Its sole purpose is to present some concepts disclosed herein in a simplified form as a prelude to the more detailed description that is presented later. 
     One aspect of the present disclosure is to provide an energy recycling system. The energy recycling system includes several working circuits and a first energy recycling circuit. The working circuits include at least one first working circuit and at least one second working circuit, wherein the first working circuits and the second working circuits are alternately coupled with each other in series. The first energy recycling circuit includes an inductor and several pairs of switches. The first energy recycling circuit, coupled between the first working circuits and the second working circuits, a first alternating-current-type (AC-type) voltage source is supplied to the first working circuits and the second working circuits. The energy loss of the first AC-type voltage source is replenished by a direct-current-type (DC-type) voltage source. The pairs of switches, configured for conducting in different time sequences and transferring the energy of the first AC-type voltage source between the first working circuits, the inductor and the second working circuits. 
     Another aspect of the present disclosure is to provide a circuit layout method utilized in the aforementioned energy recycling system. The method includes: disposing a first metal trace configured for transferring the first AC-type voltage source; and disposing a second metal trace above and vertically overlapping to the first metal trace, wherein the second metal trace is configured for transferring the second AC-type voltage source, and the first metal trace and the second metal trace are not electrically coupled with each other. 
     Still another aspect of the present disclosure is to provide an energy recycling method utilized in an energy recycling system including at least one working circuit and at least one second working circuit and a first energy recycling circuit, wherein the first working circuits and the second working circuits are alternately coupled with each other in series, and the first working circuits have a first equivalent parasitic capacitor, and the second working circuits have a second equivalent parasitic capacitor. The energy recycling method includes: in the initial time sequence, transference of the energy of the first AC-type voltage source from a DC-type voltage source to the first equivalent parasitic capacitor; in a secondary time sequence, transference of the energy of the first AC-type voltage source from the first equivalent parasitic capacitor to an inductor; and in a tertiary time sequence, transference of the energy of the first AC-type voltage source from the inductor to the second equivalent parasitic capacitor, wherein the initial time sequence, the secondary time sequence and the tertiary time sequence are different time sequences. 
     It is to be understood that both the foregoing general description and the following detailed description are by examples, and are intended to provide further explanation of the disclosure as claimed. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The disclosure can be more fully understood by reading the following detailed description of the embodiment, with reference made to the accompanying drawings as follows: 
         FIG. 1  is a schematic diagram illustrating an energy recycling system according to an embodiment of the present disclosure; 
         FIG. 2  is a schematic diagram illustrating the alternate connection of the first working circuits and the second working circuits with each other in series in  FIG. 1 ; 
         FIG. 3  is a waveform diagram illustrating the control signals of the first pair of switches to the fourth pair of switches and the first AC-type voltage source of the first energy recycling circuit in  FIG. 1 ; 
         FIG. 4  is a schematic diagram illustrating an energy recycling system according to another embodiment of the present disclosure; 
         FIG. 5  is a waveform diagram illustrating the control signals of the fifth pair of switches to the tenth pair of switches and the second AC-type voltage source of the energy recycling system in  FIG. 4 ; 
         FIG. 6  is a schematic diagram illustrating the logic circuit and its waveform of the energy recycling system in  FIG. 4 ; 
         FIG. 7  is a schematic diagram illustrating the register circuit, the first memory circuit and their waveform of the energy recycling system in  FIG. 4 ; 
         FIG. 8  is a schematic diagram of a circuit layout method according to an embodiment of the present disclosure; and 
         FIG. 9  is a schematic diagram of an energy recycling method according to an embodiment of the present disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     Reference will now be made in detail to the present embodiments of the disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts. 
     It will be understood that, although the terms first, second, third etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention. 
     It will be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. 
       FIG. 1  is a schematic diagram illustrating an energy recycling system  100  according to an embodiment of the present disclosure. As shown in  FIG. 1 , the energy recycling system  100  is configured to provide electricity to load circuits for processing logic operation of signals. In practice, the load circuits can be central processing units (CPUs), comparators, memory modules, gate drivers, shift registers, inverters or any other logical circuits for processing logic operation of signals. In the present disclosure, the energy recycling system  100  reuses the electricity by transferring the energy alternately between the load circuits 
     For example, the abovementioned load circuits may include several working units, and each of the working circuits may be coupled with each other in series and respectively process different functions to data signals, such as signal amplifying, signal determining, signal comparing and signal registering. In the embodiment, the working units of the load circuits can be separated according to the odd-even order of the working units into first working circuits (odd-ordered) and second working circuits (even-ordered). 
     As shown in  FIG. 1 , the energy recycling system  100  includes first working circuits  1101 ˜ 110   n , second working circuits  1201 ˜ 120   n  and a first energy recycling circuit  130 . The first working circuits  1101 ˜ 110   n  have a first equivalent parasitic capacitor C 1  and the second working circuits  1201 ˜ 120   n  have a second equivalent parasitic capacitor C 2 . The first energy recycling circuit  130  further includes a first pair of switches SW 1 , a second pair of switches SW 2 , a third pair of switches SW 3 , a fourth pair of switches SW 4  and an inductor L. The first working circuits  1101 ˜ 110   n  and the second working circuits  1201 ˜ 120   n  are configured to process the logic operation of signals. In practice, the first working circuits  1101 ˜ 110   n  and the second working circuits  1201 ˜ 120   n  can be central processing units (CPUs), comparators, memory modules, gate drivers, shift registers, inverters or any other logical circuits for processing the logic operation of the signals. 
     Reference is also made to  FIG. 2 , the loading circuits such as the first working circuits  1101 ˜ 110   n  and the second working circuits  1201 ˜ 120   n  are alternately coupled with each other in series. In addition, First memory circuits KA 1 ˜KAn and second memory circuits KB 1 ˜KBn are coupled between each of the working circuits, and it should be noted that  FIG. 2  only illustrates KA 1  and KA 2  to represent KA 1 ˜KAn, and KB 1  and KB 2  to represent KB 1 ˜KBn. The first working circuit  1101  may transmit the signals to the second working circuit  1102  after the signals are processed, and then in the same manner, the signals may be transmitted to the first working circuit  1102  and the second working circuit  1202 . Therefore, the order of processing of the signals is alternately changed between the first working circuits  1101 ˜ 110   n  and the second working circuits  1201 ˜ 120   n . It should be noted that the first working circuits  1101 ˜ 110   n  and the second working circuits  1201 ˜ 120   n  are respectively coupled to different supply voltages, for example, the first working circuits  1101 ˜ 110   n  are coupled with a first high level supply voltage VDD 1  and a first low level supply voltage VSS 1 , on the other hand, the second working circuits  1201 ˜ 120   n  are coupled with a first high level supply voltage VDD 2  and a first low level supply voltage VSS 2 . In order to make the energy recycling system easier to understand,  FIG. 1  illustrates the first working circuits  1101 ˜ 110   n  and the second working circuits  1201 ˜ 120   n  in an overlapped manner. 
     Each of the first working circuits  1101 ˜ 110   n  and the second working circuits  1201 ˜ 120   n  has a parasitic capacitor (which is not shown in drawings of the present disclosure). Any overlap of metal in the circuits may form the parasitic capacitor, therefore, the parasitic capacitor is naturally formed by the circuits and is not coupled or connected as an external capacitor unit. In this embodiment, all of the parasitic capacitors of the first working circuits compose the first equivalent parasitic capacitor C 1 , and all of the parasitic capacitors of the second working circuits compose the second equivalent parasitic capacitor C 2 , as shown in  FIG. 1 . 
     The first energy recycling circuit  130  is coupled between the first working circuits  1101 ˜ 110   n  and the second working circuits  1201 ˜ 120   n . In the embodiment, a DC-type voltage source  140  includes a high level DC supply voltage VDD and a low level DC supply voltage VSS. The first energy recycling circuit  130  converts the DC voltage source  140  to a first AC-type voltage source  301 ,  302  by conducting the pairs of switches (i.e., the first pair of switches SW 1 , the second pair of switches SW 2 , the third pair of switches SW 3  and the fourth pair of switches SW 4 ) in different time sequences, and then respectively supplies the first AC-type voltage source  301 ,  302  to the first working circuits  1101 ˜ 110   n  and the second working circuits  1201 ˜ 120   n . While the pairs of switches conduct in different time sequences, the resonant circuit including the first equivalent parasitic capacitor C 1 , the second equivalent parasitic capacitor C 2  and the inductor L converts the DC-type voltage source  140  to the first AC-type voltage source  301 ,  302 , and reference is also made to  FIG. 3 . 
       FIG. 3  is a waveform diagram illustrating the control signals of the first pair of switches SW 1  to the fourth pair of switches SW 4  and the first AC-type voltage source  301 ,  302  of the first energy recycling circuit  130  in  FIG. 1 . The first AC-type voltage source  301  includes a first high level supply voltage VDD 1  (i.e., the upper half portion of the first AC-type voltage source  301 ) and a first low level supply voltage VSS 1  (i.e., the lower half portion of the first AC-type voltage source  301 ). The first AC-type voltage source  302  includes a first high level supply voltage VDD 2  (i.e., the upper half portion of the first AC-type voltage source  302 ) and a first low level supply voltage VSS 2  (i.e., the lower half portion of the first AC-type voltage source  302 ). The first AC-type voltage source  301 ,  302  are respectively supplied to the first working circuits  1101 ˜ 110   n  and the second working circuits  1201 ˜ 120   n.    
     As shown in  FIG. 1  and  FIG. 3 , the first pair of switches SW 1  conducts in  0 -t 1  time sequence, and thus the DC-type voltage source  140  is coupled with the first equivalent parasitic capacitor C 1 , and the first equivalent parasitic capacitor C 1  can be charged. Therefore, in the time sequence, the potential difference between two terminals of the first equivalent parasitic capacitor C 1  is largest, i.e., the potential difference between the first high level supply voltage VDD 1  and the first low level supply voltage VSS 1  is largest, and the energy is transferred from the DC-type voltage source  140  to the first equivalent parasitic capacitor C 1 . 
     After the first pair of switches SW 1  is cut off, the second pair of switches SW 2  conducts in t 2 -t 3  time sequence, and thus the first equivalent parasitic capacitor C 1  is coupled with the inductor L, and the inductor L can be charged. Therefore, in the time sequence, the potential difference between the first high level supply voltage VDD 1  and the first low level supply voltage VSS 1  gradually decreases, and the energy is transferred from the first equivalent parasitic capacitor C 1  to the inductor L. 
     After the second pair of switches SW 2  is cut off, the third pair of switches SW 3  conducts in t 3 -t 4  time sequence, and thus the inductor L is coupled with the second equivalent parasitic capacitor C 2 , and the second equivalent parasitic capacitor C 2  can be charged. Therefore, in the time sequence, the potential difference between the first high level supply voltage VDD 2  and the first low level supply voltage VSS 2  gradually increases, and the energy transferred from the inductor L to the second equivalent parasitic capacitor C 2 . In this manner, the energy can be successively transferred from the DC-type voltage source  140  to the first equivalent parasitic capacitor C 1 , the inductor L and the second equivalent parasitic capacitor C 2 . 
     In addition, the energy loss from transferring or the energy consumed in processing the operation of the signals by the second working circuits  1201 ˜ 120   n  can be replenished by conducting the fourth pair of switches SW 4 . While the fourth pair of switches SW 4  conducts, the energy can be transferred from the DC-type voltage source  140  to the second equivalent parasitic capacitor C 2 . That is to say, the energy loss is replenished by the DC-type voltage source  140 . Similarly, the third pair of switches SW 3  and the second pair of switches SW 2  may successively conduct, and the energy can thus be transferred to the first equivalent parasitic capacitor C 1 . Finally, the pairs of switches may repeat the energy transferring in the next period T 1  according to the clock signal CLK. 
     As shown in  FIG. 2 , the order of processing the signals is alternately changed between the first working circuits  1101 ˜ 110   n  and the second working circuits  1201 ˜ 120   n . Therefore, by transferring the energy between the first working circuits  1101 ˜ 110   n , the inductor L and the second working circuits  1201 ˜ 120   n , the energy can be transferred to the working circuits while the working circuits are processing the signals, and the energy loss caused by the other working circuits which are not processing the signals can be prevented. 
       FIG. 4  is a schematic diagram illustrating an energy recycling system  400  according to another embodiment of the present disclosure. In the embodiment, The energy recycling system includes the first energy recycling circuit  130 , a second energy recycling circuit  410 , the first working circuits  1101 ˜ 110   n , the second working circuits  1201 ˜ 120   n , the first memory circuits KA 1 ˜KAn and the second memory circuits KB 1 ˜KBn. The second energy recycling circuit  410  includes the pairs of switches SW 5 ˜SW 10  and the inductor L. The first working circuits  1101 ˜ 110   n  include logic circuits CA 1 ˜CAn and register circuits LA 1 ˜LAn. The second working circuits  1201 ˜ 120   n  include logic circuits CB 1 ˜CBn and register circuits LB 1 ˜LBn. 
     Similarly, the second energy recycling circuit  410  converts the DC-type voltage source  140  to a second AC-type voltage source  501 ,  502  by conducting the pairs of switches SW 5 ˜SW 10  in different time sequences, and then respectively supplies the second AC-type voltage source  501 ,  502  to the first memory circuits KA 1 ˜KAn and the second memory circuits KB 1 ˜KBn and reference is also made to  FIG. 5 .  FIG. 5  is a waveform diagram illustrating the control signals of the fifth pair of switches SW 5  to the tenth pair of switches SW 10  and the second AC-type voltage source  501 ,  502  of the energy recycling system  400  in  FIG. 4 . The second AC-type voltage source  501  includes a second high level supply voltage VDDK 1  (i.e., the upper half portion of the second AC-type voltage source  501 ) and a second low level supply voltage VSSK 1  (i.e., the lower half portion of the second AC-type voltage source  501 ). The second AC-type voltage source  502  includes a second high level supply voltage VDDK 2  (i.e., the upper half portion of the second AC-type voltage source  502 ) and a second low level supply voltage VSSK 2  (i.e., the lower half portion of the second AC-type voltage source  502 ). The second AC-type voltage source  501 ,  502  are respectively supplied to the first memory circuits KA 1 ˜KAn and the second memory circuits KB 1 ˜KBn. 
     It should be noted that, the pairs of switches SW 5 ˜SW 10  are coupled between the inductor L and the DC-type voltage source  140 . While the memory circuits (i.e., the first memory circuits KA 1 ˜KAn or the second memory circuits KB 1 ˜KBn) are preparing to process the storage operation, the energy should be transferred from the inductor L to the memory circuits, therefore the fifth pair of switches SW 5  and the eighth pair of switches SW 8  may conduct at this time (which is in accordance with t 8 -t 9  time sequence and t 3 -t 4  time sequence in  FIG. 5 ). While the memory circuits are processing the storage operation, the memory circuits should be coupled with the stable DC-type voltage source  140  in order to prevent the energy from being insufficient, in which the insufficient energy may cause storing errors during the storage operation. Therefore the sixth pair of switches SW 6  and the ninth pair of switches SW 9  may conduct at this time (which is in accordance with t 10 -t 16  time sequence and t 5 -t 11  time sequence in  FIG. 5 ). While the energy should be transferred from memory circuits to the inductor L, the seventh pair of switches SW 7  and the tenth pair of switches SW 10  may conduct at this time (which is in accordance with t 7 -t 8  time sequence and t 12 -t 13  time sequence in  FIG. 5 ). Finally, the pairs of switches SW 5 ˜SW 10  may repeat the energy transferring in the next period T 1  according to the clock signal CLK. As shown in  FIG. 2 , the order of storing the signals is alternately changed between the first memory circuits KA 1 ˜KAn and the second memory circuits KB 1 ˜KBn. 
     Therefore, by transferring the energy between the first memory circuits KA 1 ˜KAn, the inductor L and the second memory circuits KB 1 ˜KBn, the energy can be transferred to the memory circuits while the memory circuits are processing the storage operation, and the energy loss caused by the other memory circuits which are not processing the storage operation can be prevented. 
     As shown in  FIG. 4  and  FIG. 6 ,  FIG. 6  is a schematic diagram illustrating the logic circuit CA 1  and its waveform of the energy recycling system  400  in  FIG. 4 . In the embodiment, the logic circuit CA 1  is configured to process the logic operation of signals, and the logic circuit CA 1  can be an inverter, which includes a p-type transistor, n-type transistor and an output capacitor COUT, but the present disclosure is not limited in this regard. In practice, the logic circuit CA 1  can be a central processing unit (CPU), a comparator or one of any other logical circuits for processing the logic operation of signals. 
     It should be noted that, in general, the inverter would be coupled with a stable DC-type voltage source, however the logic circuit CA 1  in the embodiment is coupled with the abovementioned first AC-type voltage source  301 . Therefore, the logic circuit CA 1  outputs the output signal VOUT 1  not only according to an input signal IN 1  but also according to the first AC-type voltage source  301 . For example, while the input signal IN 1  is at low level potential, the logic circuit CA 1  may output an upper half portion of an alternating-current signal as the output signal VOUT 1  (before the time t 601 ) according to the first high level supply voltage VDD 1 . On the other hand, while the input signal IN 1  is at high level potential, the logic circuit CA 1  may output an lower half portion of the alternating-current signal as the output signal VOUT 1  (after the time t 601 ) according to the first low level supply voltage VSS 1 . In the abovementioned manner, the function of inverter can be operated. Therefore, in the embodiment, the logic circuit CA 1 ˜CAn and the logic circuit CB 1 ˜CBn can not only reduce the energy loss through the first energy recycling circuit  130  but also save the costs and space of the IC chips by utilizing the simple configuration and fewer amount of transistors. 
       FIG. 7  is a schematic diagram illustrating the register circuit LA 1 , the first memory circuit KA 1  and their waveform of the energy recycling system  400  in  FIG. 4 . As shown in  FIG. 4 , the logic circuit CA 1 , the register circuit LA 1  and the first memory circuit KA 1  are coupled with each other in series. While the above mentioned logic circuit CA 1  transmits the output signal VOUT 1  to the register circuit LA 1 , similarly, the register circuit LA 1  may output a memory signal SAVE according to the output signal VOUT 1  and the first AC-type voltage source  301 . In addition, the control signal A and the control signal A′ (whose waveform is complementary to the control signal A and not shown in  FIG. 7 ) utilized in the register circuit LA 1  and the first memory circuit KA 1  are just one embodiment, and the control signals can be different according to different designs of circuits, and the present disclosure is not limited in this regard. 
     The first memory circuit KA 1  is configured to store the memory signal SAVE form the register circuit LA 1  and provide the next working circuit with the signal for processing (which is shown in  FIG. 2 , the first memory circuit KA 1  is coupled with the second working circuit  1201 ). As mentioned above, the first memory circuit KA 1  is coupled with the second AC-type voltage source  501 , and thus the first memory circuit KA 1  may generate the output signal IN 2  according to the memory signal SAVE and the second AC-type voltage source  501 . It should be noted that, either the input signal IN 1  or the input signal IN 2  shown in  FIG. 4  is actually not labeled for just one logic circuit, that is to say, all of the input signals of the logic circuits CA 1 ˜CAn are all labeled as the input signals IN 1 , and all of the input signals of the logic circuits CB 1 ˜CBn are all labeled as the input signals IN 2 . For example, the input signal IN 1  received by the logic circuit CA 1  is transmitted to the register circuit LA 1  and the first memory circuit KA 1 , and then the first memory circuit KA 1  generates the input signal IN 2  to the logic circuit CB 1 . In this manner, the input signal IN 2  received by the logic circuit CB 1  is transmitted to the register circuit LB 1  and the second memory circuit KB 1 , and then the second memory circuit KB 1  generates the input signal IN 1  to the logic circuit CA 2 . 
       FIG. 8  is a schematic diagram of a circuit layout method according to an embodiment of the present disclosure. As described in the abovementioned embodiment, the first AC-type voltage source  301  and the second AC-type voltage source  501  in the energy recycling system  400  respectively supply to the first working circuits  1101 ˜ 110   n  and the first memory circuits KA 1 ˜KAn, and thus the first AC-type voltage source  301  and the second AC-type voltage source  501  should be transferred in different metal traces in the circuit layout. As shown in the left half portion of  FIG. 8 , the metal traces  810 ,  812  are disposed on the same plane to transfer the first AC-type voltage source  301  and the second AC-type voltage source  501  respectively. That is to say, the metal traces  810 ,  812  respectively occupy the two different areas on the IC chip. In the circuit layout method of the embodiment as shown in the right half portion of  FIG. 8 : disposing a metal trace  820  configured for transferring the first AC-type voltage source  301 ; and disposing a metal trace  822  above and vertically overlapping to the metal trace  820 , in which the second metal trace is configured for transferring the second AC-type voltage source. It should be noted that the metal trace  820  and the metal trace  822  are not electrically coupled with each other, that is to say, the metal trace  820  and the metal trace  822  are disposed on different planes. By utilizing the circuit layout method, the areas occupied by the metal traces on the IC chip can be greatly reduced. 
       FIG. 9  is a schematic diagram of an energy recycling method  900  according to an embodiment of the present disclosure. Firstly, in an initial time sequence, step S 902  is executed for transferring the energy of the first AC-type voltage source from a direct-current-type (DC-type) voltage source to the first equivalent parasitic capacitor. Afterward, in a secondary time sequence, step S 904  is executed for transferring the energy of the first AC-type voltage source from the first equivalent parasitic capacitor to an inductor. Afterward, in a tertiary time sequence, step S 906  is executed for transferring the energy of the first AC-type voltage source from the inductor to the second equivalent parasitic capacitor. It should be noted that the initial time sequence, the secondary time sequence and the tertiary time sequence are different time sequences. The energy loss of the first AC-type voltage source is replenished by the DC-type voltage source. 
     To summarize, the present disclosure provides an energy recycling system and an energy recycling method thereof. The AC-type voltage source can be generated from the DC-type voltage source through the resonant circuit of the working circuits, in which the resonant circuit includes the equivalent parasitic capacitor of the working circuits and the inductor L (coupled as an external inductor unit or the parasitic inductor). Therefore, the energy can be transferred to the working circuits while the working circuits are processing the signals and the energy loss from transferring or the energy consumed in processing the operation of the signals by the working circuits can be replenished by connecting to the DC-type voltage source periodically. By utilizing the present disclosure, not only the dynamic power loss but also the severe leakage power loss caused from the advanced process can be reduced. 
     Although the present disclosure has been described in considerable detail with reference to certain embodiments thereof, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein. 
     It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present disclosure without departing from the scope or spirit of the disclosure. In view of the foregoing, it is intended that the present disclosure cover modifications and variations of this disclosure provided they fall within the scope of the following claims.