Patent Publication Number: US-9893680-B2

Title: Regulating cascode circuit with self-calibration capability

Description:
FIELD 
     The present disclosure is related to a regulating cascode circuit with self-calibration capability. 
     BACKGROUND 
     Voltage controlled oscillators (VCOs) usually include a regulating cascode circuit and a current controlled oscillator (CCO). In an existing VCO using a low input-output (IO) supply voltage, some transistors in the regulating cascode circuit function out of a saturation mode at some process, voltage, and temperature (PVT) conditions or corners. In such a situation, the power supply rejection ratio (PSRR) of the VCO is decreased and affects performance of the phase lock loop (PLL) having the VCO. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The details of one or more embodiments of the disclosure are set forth in the accompanying drawings and the description below. Other features and advantages will be apparent from the description, drawings, and claims. 
         FIG. 1  is a diagram of a circuit having a cascode core circuit, in accordance with some embodiments. 
         FIG. 2  is a diagram of a circuit implementing the voltage detector and the current adjustor in the circuit of  FIG. 1 , in accordance with some embodiments. 
         FIG. 3  is a diagram of a circuit functioning as a combined circuit of the voltage detector and the current adjustor in  FIG. 2 , in accordance with some embodiments. 
         FIG. 4  is a diagram of a current bias in  FIG. 1 , in accordance with some embodiments. 
         FIG. 5  is a diagram of a circuit implementing the application circuit in  FIG. 1 , in accordance with some embodiments. 
         FIG. 6  is a diagram of a circuit implementing the application circuit in  FIG. 1 , in accordance with some further embodiments. 
         FIG. 7  is a diagram of a circuit having a cascode core circuit, in accordance with some further embodiments. 
         FIG. 8  is a diagram of a circuit implementing the voltage detector and the current adjustor in the circuit of  FIG. 7 , in accordance with some embodiments. 
         FIG. 9  is a diagram of a circuit functioning as a combined circuit of the voltage detector and the current adjustor in  FIG. 8 , in accordance with some embodiments. 
         FIG. 10  is a diagram of a current bias in  FIG. 7 , in accordance with some embodiments. 
         FIG. 11  is a diagram of a circuit implementing the application circuit in  FIG. 7 , in accordance with some embodiments. 
         FIG. 12  is a diagram of a circuit implementing the application circuit in  FIG. 7 , in accordance with some further embodiments. 
         FIG. 13  is a flowchart of a method of selecting the transistor in  FIG. 3 , in accordance with some embodiments. 
         FIG. 14  is a table illustrating various process, voltage, and temperature corners in which the circuit in  FIG. 1  operates, in accordance with some embodiments. 
         FIG. 15  is a flowchart of a method illustrating an operation of the circuit in  FIG. 1 , in accordance with some embodiments. 
     
    
    
     Like reference symbols in the various drawings indicate like elements. 
     DETAILED DESCRIPTION 
     Embodiments, or examples, illustrated in the drawings are disclosed below using specific language. It will nevertheless be understood that the embodiments and examples are not intended to be limiting. Any alterations and modifications in the disclosed embodiments, and any further applications of the principles disclosed in this document are contemplated as would normally occur to one of ordinary skill in the pertinent art. 
     Some embodiments have at least one of the following features and/or advantages. A head voltage of a ring oscillator is detected. A bias current of a regulating cascode circuit is adjusted. As a result, transistors in the regulating cascode circuit continue to function in the saturation region. Various embodiments of the present disclosure are applicable for low supply voltage applications. For example, in some embodiments having a nominal operational voltage of 2.5V, a low voltage of 1.8 V is used. In some embodiments, a single N-type metal oxide semiconductor (NMOS) transistor functions as both a voltage detector and a current adjustor. A power supply rejection ratio (PSRR) gains 7.4 dB higher than that of an existing approach. The PSRR of a voltage controlled oscillator (VCO) is less than −60 dB for different process, voltage, and temperature (PVT) corners. 
     In a semiconductor manufacturing process, some transistors are typical or normal transistors, and are called in the typical corner or manufactured by a typical process. Some transistors switch faster than the typical transistors, and are called in the fast corner or manufactured by a fast process. Some transistors switch slower than the typical transistors, and are called in the slow corner or manufactured by a slow process. In this document, a first letter in a term having two letters corresponds to a PMOS transistor while a second letter corresponds to an NMOS transistor. For example, a reference TT refers to a PMOS transistor and an NMOS transistor in the typical corner. A reference FF refers to a PMOS and an NMOS transistor in the fast corner, and a reference SS refers to a PMOS and an NMOS transistor in the slow corner. 
     Circuit Having a Cascode Core 
       FIG. 1  is a diagram of a circuit  100  in accordance with some embodiments. To avoid obscuring the drawing, voltages VsgM 3 , VdMV 2 I, VsdMV 2 I, VodMV 2 I, VthMV 2 I, VmMV 2 I, VdM 5 , VsdM 5 , VodM 5 , VthM 5  and VmM 5  are not shown. 
     Voltage VsgM 3  is a voltage drop between a source and a gate of transistor M 3 . 
     Voltage VdMV 2 I is a voltage at a drain of transistor MV 2 I. Voltage VsdMV 2 I is a voltage drop between a source and the drain of transistor MV 2 I. Voltage VodMV 2 I is an override voltage of transistor MV 2 I, which is a voltage difference between a voltage at a gate and a threshold voltage VthMV 2 I of transistor MV 2 I. Voltage VmMV 2 I or voltage margin VmMV 2 I is a difference between voltage VsdMV 2 I and voltage VodMV 2 I. Mathematically, VmMV 2 I=VsdMV 2 I−VodMV 2 I. 
     Voltage VdM 5  is a voltage at a drain of transistor M 5 . Voltage VsdM 5  is a voltage drop between a source and the drain of transistor M 5 . Voltage VodM 5  is an override voltage of transistor M 5 , which is a voltage difference between a voltage at a gate and a threshold voltage VthM 5  of transistor M 5 . Voltage VmM 5  or voltage margin VmM 5  is a difference between voltage VsdM 5  and voltage VodM 5 . Mathematically, VmM 5 =VsdM 5 −VodM 5 . 
     Circuit  100  includes a regulating cascode circuit  105  used in conjunction with an application circuit  140 . Application circuit  140  receives and functions based on a current IVD provided by regulating cascode circuit  105 . For example, when application circuit  140  is a current controlled oscillator (CCO), regulating cascode circuit  105  together with application circuit  140  functions as, and is called, a voltage controlled oscillator (VCO). In such a condition, a voltage VD at the drain of transistor M 5  is called the head voltage of the CCO. A capacitor CAP is a load capacitor for application circuit  140 , and is used to stabilize voltage VD. 
     Regulating cascode circuit  105  receives a voltage VCOIN and provides current IVD to application circuit  140 , and is therefore considered a current bias circuit for application circuit  140 . Regulating cascode circuit  105  includes a cascode core circuit  108 , a voltage detector  110 , a current adjustor  120 , and a current bias  130 . 
     A current ID is called an operational current or bias current of cascode core  108 . Current ID flows from the source to the drain of a PMOS transistor M 3 . Current ID changes when voltage VsgM 3  changes, which in turn changes when voltage VD changes. In other words, both current ID and voltage VsgM 3  depend on voltage VD. In some embodiments, when the absolute value of voltage VD increases, the absolute value of current ID and of voltage VsgM 3  decrease. 
     Current IVD flows from the source to the drain of a PMOS transistor MV 2 I. When the absolute value of voltage VD increases, the absolute value of current IVD decreases. But when the absolute value of voltage VD decreases, the absolute value of current IVD increases. 
     Cascode core circuit  108  includes PMOS transistors MV 2 I, M 3 , and M 5  that perform a cascoding function of regulating cascode circuit  105 . Transistors MV 2 I and M 5  are connected in a series or in a cascode manner. A source of PMOS transistor MV 2 I receives operational voltage VDD. A drain of PMOS transistor MV 2 I is coupled to a source of PMOS transistor M 5 . The drain of PMOS transistor M 5  provides voltage VD for use by application circuit  140 , and is called an output node of cascode core circuit  108 . A gate of PMOS transistor MV 2 I receives voltage VCOIN, and is called an input node of cascode core circuit  108 . The drain of transistor MV 2 I and the source of transistor M 5  are also coupled to a gate of transistor M 3 . A drain of transistor M 3  is coupled to the gate of transistor M 5 . A source of transistor M 3  receives an operational voltage VDD. 
     Cascode core circuit  108  functions as a voltage-to-current converter. For example, cascode core circuit  108 , based on voltage VCOIN at the gate of transistor MV 2 I, generates current IVD, which flows from the source to the drain of transistor MV 2 I. Current IVD then flows through the source and the drain of transistor M 5 , and is used by application circuit  140 . For another example, when transistors M 3 , MV 2 I, and M 5  operate in a saturation mode, transistor M 3  functions as an amplifier. Transistor M 3  then forces voltage VdMV 2 I at the drain of transistor MV 2 I to be at a fixed voltage. As a result, current IVD provided to application circuit  140  is a fixed current. 
     When transistor M 5  and/or transistor MV 2 I operate out of the saturation mode into a triode mode, application circuit  140  operates in a slower frequency. In various embodiments of the present disclosure, both transistors MV 2 I and M 5  and other circuitry in circuit  100  are designed such that transistors MV 2 I and M 5  do not enter the triode mode, but remain in the saturation mode when the absolute value of voltage VCOIN decreases and/or the absolute value of voltage VD increases. For example, when the absolute value of voltage VCOIN decreases and/or the absolute value of voltage VD increases, the absolute value of voltage VsgM 3 , which is equal to the absolute value of voltage VsdMv 2 I, is designed to decrease, and is greater than the absolute value of voltage VodMV 2 I so that transistor MV 2 I continue to operate in the saturation mode. Voltage VsgM 3  is also designed such that voltage VDD−voltage VsgM 3 −voltage VD is greater than the absolute value of voltage VodM 5  so that transistor M 5  continues to operate in the saturation mode. For another example, in some embodiments, the absolute value |ΔVsgM 3 | of voltage ΔVsgM 3  is designed to be substantially equal to the absolute value of voltage |ΔVD|. Effectively, the amount of increase in the absolute value of voltage VD is substantially the same as the amount of decrease in the absolute value of voltage VsgM 3 . 
     When voltage VD changes, voltage detector  110  detects a change in voltage VD and provides the result to current adjustor  120  to adjust current ID 2 , or effectively, to adjust current ID. For illustration, at a particular voltage VCOIN, transistors MV 2 I and M 5  operate in the saturation mode. For various reasons, the VCO formed by regulating cascode circuit  105  and the CCO functioning as application circuit  140  slows down. The absolute value of voltage VCOIN and of current IVD is decreased to compensate for the slow down of the VCO. In response to the decrease of the absolute value of current IVD, the CCO causes the absolute value of voltage VD to increase. Additionally, the absolute values of currents IVD, ID 1 , ID 2  increase because:
 
 IVD=KMV 2 I *( VsgMV 2 I−VthMV 2 I ) 2   =KMV 2 I *( VDD−VCOIN−VthMV 2 I ) 2 ;
 
 ID 1= KM 1 A *( VsgM 1 A−VthM 1 A ) 2   =KM 1 A *( VDD−VCOIN−VthM 1 A ) 2 ; and
 
 ID 2= KN 300*( VgsN 300 −VthN 300) 2   =KN 300*( VD−VthN 300) 2 .
 
     Where KMV 2 I, KM 1 A, and KN 300  are constant values of corresponding transistors MV 2 I, M 1 A, and N 300 . Voltage VsgM 1 A is a voltage drop across the source and the gate of transistor M 1 A. Voltage VthM 1 A is the threshold voltage of transistor M 1 A. Voltage VgsN 300  is a voltage drop across the gate and the source of transistor N 300 , and voltage VthN 300  is the threshold voltage of transistor N 300 . Transistor N 300  is shown in  FIG. 3  while transistor M 1 A is shown in  FIG. 4 . 
     Because current ID is the difference between current ID 1  and ID 2  (ID=ID 1 −ID 2 ), the absolute value of current ID decreases, which causes the absolute value of voltage VsgM 3  or of voltage VsdMV 2 I to decrease, and the absolute value of voltage VsdM 5  to increase. In some embodiments, the absolute value of voltage VsdM 5  is designed to increase such that the absolute value of voltage VsdM 5  is higher than the absolute value of voltage VodM 5  by a predetermined voltage margin VmM 5 , such as 100 mV, at various operating PVT corners. As a result, transistor M 5  continues to operate in the saturation mode. In other words, transistor M 5  is prevented from leaving the saturation mode to enter the triode mode. At that time, the absolute value of voltage VsgM 3  or of voltage VsdM 2 I is greater than the absolute value of voltage VodMV 2 I. As a result, transistor MV 2 I continues to function in the saturation mode. In some embodiments, the absolute value of voltage VsdMV 2 I is designed to be higher than the absolute value of voltage VodMV 2 I by a predetermined voltage margin VmMV 2 I, such as 100 mV, in various operating PVT corners. 
     Various embodiments of the present disclosure are advantageous over other existing approaches in which the transistor corresponding to transistor M 5  and/or the transistor corresponding to transistor MV 2 I enter the triode mode when the absolute value of voltage VD increases. 
     In some embodiments, the absolute value of voltage VD in the SS corner is increased compared with the absolute value of voltage VD in the TT corner. As a result, without mechanisms of the present disclosure, transistor MV 2 I and/or transistor M 5  could operate in the triode mode when transistor MV 2 I and/or transistor M 5  are in the SS corner. In various embodiments, both transistors MV 2 I and M 5  are designed such that transistors MV 2 I and M 5  do not enter the triode mode when transistor MV 2 I and/or transistor M 5  are in the SS corner. For illustration, a change in voltage VD from the TT corner to the SS corner is called voltage ΔVD and is obtained through simulation. Further, the absolute value of voltage VsgM 3  in the SS corner is designed to be lower than the absolute value of voltage VsgM 3  in the TT corner. Stated differently, the absolute value of voltage VsgM 3  decreases. The decrease in the absolute value of voltage VsgM 3  from the TT corner to the SS corner is called voltage ΔVsgM 3 . In some embodiments, ΔVsgM 3  is designed to compensate for ΔVD. As a result, in the SS corner, transistors MV 2 I and M 5  continue to operate in the saturation region. 
     In some embodiments, 
     
       
         
           
             
               
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     Wherein VthM 3  is the threshold voltage of transistor M 3 , K is a mathematical constant value of transistor M 3 , Cox is the oxide capacitance, μ is the electron mobility through the channel, W is the width, and L is the length of transistor M 3 . 
     In various embodiments, each of the absolute value of voltage VsdM 5  and of voltage VsdMV 2 I is designed to be greater than the corresponding absolute value of override voltages VodM 5  and VodMV 2 I to keep the corresponding transistors M 5  and MV 2 I to operate in the saturation mode. In some embodiments, overdrive voltages VodM 5  and VodMV 2 I are obtained through simulation. 
     Voltage detector  110  provides a voltage to current adjustor  120  based on voltage VD. Current adjustor  120 , based the voltage provided by voltage detector  110 , adjusts current ID 2 , and effectively, adjusts current ID, to keep transistor M 5  operate in the saturation mode in different PVT corners. Details of voltage detector  110  and current adjustor  120  are described with reference to  FIG. 2  and  FIG. 3 . 
     Current bias  130  generates current ID for cascode core circuit  108 . Current bias  130  changes current ID based on current ID 2 . Current ID is the difference between current ID 1  and current ID 2 , and depends on voltage VD at the drain of transistor M 5 . 
     Various embodiments of the disclosure are advantageous over some existing approaches. In those existing approaches, the transistors in the cascode core circuit operate out of the saturation mode into the triode mode in some PVT corners, such as at the temperature corner of −40° C. As a result, the total resistance of the cascode core circuit in those existing approaches is reduced, resulting in a lower PSSR. 
     Further, transistors MV 2 I and M 5  of the present disclosure operate in the saturation mode in the SS corner. For example, when transistors MV 2 I and M 5  are in the SS corner, the absolute value of voltage VD is increased compared with the absolute value of voltage VD in the SS corners. The operation of circuit  100  in response to the increase in the absolute value of voltage VD is explained above. In other words, the absolute value of voltage VsgM 3  is designed to decrease to keep transistors MV 2 I and M 5  operate in the saturation mode as explained above. In contrast, in some existing approaches, transistors corresponding to transistors MV 2 I and/or M 5  operate in the triode region in the SS corner. 
     Voltage Detector and Current Adjustor 
       FIG. 2  is a diagram of a circuit  200 , in accordance with some embodiments. Circuit  200  includes an implementation of voltage detector  110  and current adjustor  120  in  FIG. 1 . 
     Voltage detector  110  is implemented by an operational amplifier (OP)  205 . OP  205  receives voltage VD and a reference voltage VREF as inputs, and generates a voltage VOUT. In some embodiments, reference voltage VREF is selected to be 0 V so that voltage VOUT is the difference between voltage VD and voltage VREF. Effectively, voltage VOUT is a change in voltage VD with reference to voltage VREF. 
     Mathematically,
 
 V OUT= VD−V REF.
 
     Current adjustor  120  includes NMOS transistors N 1 , N 2 , and a resistor R. Current ID 2  flows through a drain of transistor N 1 . A current IR flows through a drain of transistor N 2 . Transistors N 1  and N 2  form a current mirror because gates of transistors N 1  and N 2  are coupled together and to the drain of transistor N 2 . As a result, current ID 2  equals current IR. 
     Resistor R is a voltage controlled resistor wherein a resistance of resistor R varies based on voltage VOUT. Effectively, a voltage value of voltage VOUT results in a corresponding resistance value of resistor R and a corresponding current value of current IR. Because current ID 2  equals current IR, a voltage value of voltage VOUT results in a corresponding current value of current ID 2 . As current ID 2  changes, current ID in  FIG. 1  also changes. Effectively, current adjustor  120  adjusts current ID based on the change in voltage VD with reference to reference voltage VREF. For example, when the absolute value of voltage VD increases, the absolute value of voltage VOUT increases, and the resistance of resistor R decreases. An absolute value of a voltage dropped across resistor R decreases. An absolute value of a voltage dropped across the gate and the source of transistor N 2 , which is also a voltage dropped across the gate and the source of transistor N 1 , increases. As a result, the absolute value of current ID 2  increases. 
       FIG. 3  is a circuit diagram an NMOS transistor N 300 , in accordance with some embodiments. Transistor N 300  functions as both voltage detector  110  and current adjustor  120  in  FIG. 1 . In other words, transistor N 300  functions as circuit  200  in  FIG. 2 . Reference voltage VREF is at the source of transistor N 300  while voltage VD is at a gate of transistor N 300 . Current ID 2  flows through a drain and a source of transistor N 300 . In some embodiments, voltage VREF is set at the ground reference. By operation of NMOS transistor N 300 , a change in voltage VD at the gate of transistor N 300  results in a corresponding change in a voltage drop across the gate and the source of transistor N 300 , and also a change in current ID 2 . Effectively, NMOS transistor N 300  provides a change in a current value of current ID 2  based on a change in a voltage value of voltage VD. For example, when the absolute value of voltage VD increases, the absolute value of current ID 2  increases by operation of transistor N 300 . 
     Current Bias 
       FIG. 4  is a diagram of a circuit  400 , in accordance with some embodiments. Circuit  400  is an implementation of current bias  130  in  FIG. 1 . Based on voltage VCOIN, a PMOS transistor M 1 A generates a current flowing from a source to a drain of transistor M 1 A, which, effectively, is a current IM 1 B that flows from a drain to a source of an NMOS transistor M 1 B. NMOS transistors M 1 B and M 1 C form a current mirror. Gates of transistors M 1 B and M 1 C are coupled together and to the drain of transistor M 1 B. Current IM 1 B flows through the drain of transistor M 1 B while a current ID 1  flows through a drain of transistor M 1 C. As a result, current ID 1  equals current IM 1 B. In some embodiments, a value of current ID 1  is determined, resulting in a corresponding value of current IM 1 B. Voltage VCOIN is adjusted to provide current IM 1 B. Effectively, current ID 1  is provided based on voltage VCOIN. 
     Application Circuit 
       FIG. 5  is a diagram of a circuit  500 , in accordance with some embodiments. Circuit  500  is an embodiment of application circuit  140  in  FIG. 1 . Circuit  500  is formed by a plurality of inverters  505 - 1  to  505 -N in which N is an odd number. Circuit  500  is called a ring oscillator or a current controlled oscillator (CCO), and functions based on current IVD and voltage VD provided by regulating cascode circuit  105  in  FIG. 1 . 
       FIG. 6  is a diagram of a circuit  600 , in accordance with some embodiments. Circuit  600  is another embodiment of application circuit  140  in  FIG. 1 . Circuit  600  includes NMOS transistors N 510  and N 520  that form a current mirror. Gates of transistors N 510  and N 520  are coupled together and to a drain of transistor N 510 . Current IVD and voltage VD are provided by regulating cascode circuit  105  in  FIG. 1 . A current I 520  equals to current IVD. As a result, in some embodiments, a current value of current I 520  is predetermined, and voltage VCOIN in  FIG. 1  is adjusted to provide a corresponding value of current IVD. Effectively, the predetermined value of current I 520  is provided based on voltage VCOIN and current IVD. 
     Circuit Having a Cascode Core, Some Further Embodiments 
       FIG. 7  is a diagram of a circuit  700  in which transistors MN 3 , MNV 2 I, and MN 5  in cascode core circuit  708  are NMOS transistors, in accordance with some embodiments. 
     Compared with circuit  100  in  FIG. 1 , voltage detector  710 , current adjustor  720 , current bias  730 , and application circuit  740  correspond to voltage detector  110 , current adjustor  120 , current bias  130 , and application circuit  140  in  FIG. 1 , respectively. Capacitor CAPN corresponds to capacitor CAP. Currents IDN 1 , IDN 2 , IDN, and IVDN correspond to currents ID 1 , ID 2 , ID, and IVD, respectively. Voltages VDN and VCOINN correspond to voltages VD and VCOIN, respectively. 
     To avoid obscuring the drawing, voltages VdMNV 2 I, VdsMNV 2 I, VgsMN 3 , VdsMN 5 , VthMNV 2 I, VthMN 5 , VodMNV 2 I, and VodMN 5  are not shown. Voltage VdMNV 2 I is the voltage at the drain of transistor MNV 2 I. Voltage VdsMNV 2 I is the voltage drop between the drain and the source of transistor MNV 2 I. Voltage VgsMN 3  is the voltage drop between the gate and the source of transistor MN 3 . Voltage VdsMN 5  is the voltage drop between the drain and the source of transistor MN 5 . Voltages VthMNV 2 I and VthMN 5  are the threshold voltages of corresponding transistors MNV 2 I and MN 5 . Voltage VodMNV 2 I is an override voltage of transistor MNV 2 I, and voltage VodNM 5  is an override voltage of transistor M 5 . 
     Circuit  700  includes a regulating cascode circuit  705  used in conjunction with an application circuit  740 . Application circuit  740  receives and functions based on current IVDN provided by regulating cascode circuit  705 . For example, when application circuit  740  is a current controlled oscillator (CCO), regulating cascode circuit  705  together with application circuit  740  functions as, and is called, a voltage controlled oscillator (VCO). In such a condition, voltage VDN at the drain of transistor MN 5  is called the head voltage of the CCO. Capacitor CAPN is a load capacitor for application circuit  740 , and is used to stabilize voltage VDN. 
     Regulating cascode circuit  705  receives voltage VCOINN and provides current IVDN to application circuit  740 , and is therefore considered a current bias circuit for application circuit  740 . Regulating cascode circuit  705  includes a cascode core  708 , a voltage detector  710 , a current adjustor  720 , and a current bias  730 . 
     Current IDN is called the operational current or bias current of cascode core circuit  708 . Current IDN flows from a drain to a source of NMOS transistor MN 3 . Current IDN changes when voltage VgsMN 3  changes, which in turn changes when voltage VDN changes. In other words, both current IDN and voltage VgsMN 3  depend on voltage VDN. In some embodiments, when voltage VDN decreases, current IDN and voltage VgsM 3  increase. 
     Current IVDN flows from the drain to the source of NMOS transistor MNV 2 I. When voltage VDN decreases, current IVDN increases. But when voltage VDN increases, current IVDN decreases. 
     Cascode core circuit  708  includes NMOS transistors MNV 2 I, MN 3 , and MN 5  that perform the cascoding function of regulating cascode circuit  705 . Transistors MNV 2 I and MN 5  are connected in a series or a cascode manner. The source of NMOS transistor MNV 2 I receives a reference voltage or ground. The drain of NMOS transistor MNV 2 I is coupled to the source of NMOS transistor MN 5 . The drain of NMOS transistor MN 5  provides voltage VDN for use by application circuit  740 , and is called an output node of cascode core circuit  708 . The gate of NMOS transistor MNV 2 I receives voltage VCOINN, and is called an input node of cascode core circuit  708 . The drain of transistor MNV 2 I and the source of transistor MN 5  are also coupled to the gate of transistor MN 3 . The drain of transistor MN 3  is coupled to the gate of transistor MN 5 . The source of transistor MN 3  receives a reference voltage or ground. 
     Cascode core circuit  708  functions as a voltage-to-current converter. For example, cascode core circuit  708 , based on voltage VCOINN at the gate of transistor MNV 2 I, generates current IVDN, which flows from the drain to the source of transistor MNV 2 I. Current IVDN also flows through the drain and the source of transistor MN 5 , and is used by application circuit  740 . For another example, when transistors MN 3 , MNV 2 I, and MN 5  operate in the saturation mode, transistor MN 3  functions as an amplifier. Transistor MN 3  then forces voltage VdMNV 2 I at the drain of transistor MN 2 VI to be at a fixed voltage. As a result, current IVDN provided to application circuit  740  is a fixed current. 
     When transistor MN 5  and/or transistor MNV 2 I operate out of the saturation mode into the triode mode, application circuit  740  operates in a slower frequency. In various embodiments, both transistors MNV 2 I and MN 5  are designed such that transistors MNV 2 I and MN 5  do not enter the triode mode, but remain in the saturation mode when voltage VCOINN increases and/or voltage VD decreases. In such a situation, application circuit  740  operates at the same frequency. For example, voltage VgsMN 3  is designed to increase when voltage VCOINN increases and/or voltage VDN decreases. The absolute value of voltage VgsMN 3  is designed to be greater than the absolute value of voltage VodMV 2 I so that transistor MNV 2 I operates in the saturation mode. Voltage VgsM 3  is also designed such that voltage VDD−voltage VgsM 3 −voltage VDN is greater than voltage VodM 5  so that transistor M 5  operates in the saturation mode. For another example, in some embodiments, the absolute value |ΔVgsM 3 | of voltage ΔVgsM 3  is designed to be substantially equal to the absolute value of voltage |ΔVD|. Effectively, the amount of decrease in voltage VDN is substantially the same as the amount of increase in voltage VgsM 3 . 
     When voltage VDN changes, voltage detector  710  detects the change in voltage VDN and provides the result to current adjustor  720 , which adjusts current IDN 2 , or effectively, current IDN. For illustration, at a particular voltage VCOINN, transistors MNV 2 I and MN 5  operate in the saturation mode. 
     For illustration, at a particular voltage VCOINN, transistors MV 2 I and M 5  operate in the saturation mode. For various reasons, the VCO formed by regulating cascode circuit  705  and the CCO function as application circuit  740  slows down. Voltage VCOINN and current IVD are increased to compensate for the slow down of the VCO. In response to the increase of current IVDN, the CCO causes voltage VDN to decrease. Additionally, currents IVDN, IDN 1 , IDN 2  decrease because
 
 IVDN=KMNV 2I*( VgsMNV 2 I−VthMNV 2 I ) 2   =KMNV 2 I *( VCOINN−VthMNV 2 I ) 2  
 
 IDN 1 =KMN 1 A *( VgsMN 1 A−VthMN 1 A ) 2   =KMN 1 A *( VCOINN−VthMN 1 A ) 2  
 
 IDN 2 =KP 900*( VsgP 900 −VthP 900) 2   =KP 900*( VDD−VDN−VthP 900) 2  
 
     Where KMNV 2 I, KMN 1 A, and KP 900  are constant values of corresponding transistors MNV 2 I, MN 1 A, and P 900 . Voltage VgsMN 1 A is a voltage drop across the source and the gate of transistor MN 1 A. Voltage VthMN 1 A is the threshold voltage of transistor MN 1 A. Voltage VsgP 900  is a voltage drop across the source and the gate of transistor P 900 , and voltage VthP 900  is the threshold voltage of transistor P 900 . Transistor P 900  is shown in  FIG. 9  while transistor MN 1 A is shown in  FIG. 10 . 
     Because current IDN is the difference between current IDN 1  and IDN 2  (IDN=IDN 1 −IDN 2 ), current IDN increases, which causes voltage VgsMN 3  and voltage VdsMNV 2 I to increase, and voltage VdsNM 5  to decrease. In some embodiments, voltage VdsM 5  is designed to decrease such that the absolute value of voltage VdsMN 5  is greater than the absolute value of voltage VodMN 5 . As a result, transistor MN 5  continues to operate in the saturation mode. In other word, transistor MN 5  is prevented from leaving the saturation mode to enter the triode mode. At that time, transistor MNV 2 I continues to function in the saturation mode because the absolute value of voltage VgsM 3  is greater than the absolute value of voltage VodMV 2 I. In some embodiments, the absolute value of voltage VdsMNV 2 I is designed to be higher than the absolute value of voltage VodMNV 2 I by a predetermined voltage margin VmMNV 2 I, such as 100 mV, in various operating PVT corners. 
     Various embodiments of the present disclosure are advantageous over other existing approaches in which the transistor corresponding to transistor MN 5  and/or the transistor corresponding to transistor MNV 2 I enter the triode mode when voltage VDN decreases. 
     In some embodiments, voltage VDN in the SS corner is decreased compared with voltage VDN in the TT corner. Without mechanisms of the present disclosure, transistor MNV 2 I and/or transistor MN 5  could operate in the triode mode when transistor MNV 2 I and/or transistor MN 5  are in the SS corner. In various embodiments, both transistors MNV 2 I and MN 5  are designed such that transistors MNV 2 I and MN 5  do not enter the triode mode when transistor MNV 2 I and/or transistor MN 5  are in the SS corner. For illustration, a change in voltage VDN from the TT corner to the SS corner is called voltage ΔVDN and is obtained through simulation. Further, the absolute value of voltage VgsMN 3  in the SS corner is designed to be lower than the absolute value of voltage VgsMN 3  in the TT corner. Stated differently, voltage VgsMN 3  increases. The increase in voltage VgsMN 3  from the TT corner to the SS corner is called voltage ΔVgsMN 3 . In some embodiments, ΔVgsMN 3  is designed to compensate for ΔVDN. As a result, in the SS corner, transistors MV 2 I and M 5  continue to operate in the saturation region. 
     In some embodiments, 
     
       
         
           
             
               
                 VdsMNV 
                 ⁢ 
                 
                     
                 
                 ⁢ 
                 2 
                 ⁢ 
                 I 
               
               = 
               
                 VgsMN 
                 ⁢ 
                 
                     
                 
                 ⁢ 
                 3 
               
             
             ; 
           
         
       
       
         
           
             
               
                 VdsMN 
                 ⁢ 
                 
                     
                 
                 ⁢ 
                 5 
               
               = 
               
                 VDN 
                 - 
                 
                   VdsMNV 
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   2 
                   ⁢ 
                   I 
                 
               
             
             ; 
             and 
           
         
       
       
         
           
             
               
                 VgsMN 
                 ⁢ 
                 
                     
                 
                 ⁢ 
                 3 
               
               = 
               
                 
                   
                     IDN 
                     
                       KMN 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       3 
                     
                   
                 
                 + 
                 
                   VthMN 
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   3 
                 
               
             
             , 
             
               
                 KMN 
                 ⁢ 
                 
                     
                 
                 ⁢ 
                 3 
               
               = 
               
                 
                   1 
                   2 
                 
                 ⁢ 
                 µ 
                 ⁢ 
                 
                     
                 
                 ⁢ 
                 
                   
                     Cox 
                     ⁡ 
                     
                       ( 
                       
                         W 
                         / 
                         L 
                       
                       ) 
                     
                   
                   . 
                 
               
             
           
         
       
     
     Wherein VthMN 3  is the threshold voltage of transistor MN 3 , KMN 3  is a mathematical constant of transistor MN 3 , Cox is the oxide capacitance, μ is the electron mobility through the channel, W is the width, and L is the length of transistor MN 3 . 
     In various embodiments, each of the absolute values of voltage VdsMN 5  and of voltage VdsMNV 2 I is designed to be greater than the absolute value of the corresponding override voltages VodMN 5  and VodMNV 2 I to keep the corresponding transistors MN 5  and MNV 2 I to operate in the saturation mode. In some embodiments, overdrive voltages VodMN 5  and VodMNV 2 I are obtained through simulation. 
     Voltage detector  710  provides a voltage to current adjustor  720  based on voltage VDN. Current adjustor  720 , based the voltage provided by voltage detector  710 , adjusts current IDN 2 , and effectively, adjusts current IDN, to keep transistor MN 5  operate in the saturation mode in desired conditions. Details of voltage detector  710  and current adjustor  720  are described with reference to  FIG. 8  and  FIG. 9 . 
     Current bias  730  generates current IDN for cascode core circuit  708 . Current bias  730  changes current IDN based on current IDN 2 . Current IDN is the difference between current IDN 1  and current IDN 2 , and depends on voltage VDN at the drain of transistor MN 5 . 
     Various embodiments of the disclosure are advantageous over some existing approaches. In those existing approaches, the transistors in the cascoding core circuit operate out of the saturation mode into the triode mode in some PVT corners, such as at the temperature corner of −40° C. As a result, the total resistance of the cascoding core circuit in those existing approaches is reduced, resulting in a lower PSSR. 
     Further, transistors MNV 2 I and MN 5  of the present disclosure operate in the saturation mode in the SS corner. For example, when transistors MNV 2 I and MN 5  are in the SS corner, voltage VDN is decreased compared with voltage VDN in the SS corners. The operation of circuit  700  in response to the decrease in voltage VDN is explained above. In other words, voltage VgsMN 3  is designed to increase to keep transistors MNV 2 I and MN 5  to operate in the saturation mode as explained above. In contrast, in some existing approaches, transistors corresponding to transistors MNV 2 I and/or MN 5  operate in the triode region in the SS corner. 
     Voltage Detector and Current Adjustor, Further Embodiments 
       FIG. 8  is a diagram of a circuit  800 , in accordance with some embodiments. Circuit  800  includes an implementation of voltage detector  710  and current adjustor  720  in  FIG. 7 . 
     Voltage detector  710  is implemented by an operational amplifier (OP)  805 . OP  805  receives voltage VDN and a reference voltage VREFN as inputs and generates a voltage VOUTN. In some embodiments, voltage VREFN is selected to be 0 V so that voltage VOUTN is the difference between voltage VDN and voltage VREFN. Effectively, voltage VOUTN is a change in voltage VDN with reference to voltage VREFN. 
     Mathematically,
 
 V OUT N=VDN−V REF N.  
 
     Current adjustor  720  includes PMOS transistors P 1 , P 2 , and resistor RN. A current IDN 2  flows through a drain of transistor P 1 . A current IRN flows through a drain of transistor P 2 . Transistors P 1  and P 2  form a current mirror because gates of transistors P 1  and P 2  are coupled together and to the drain of transistor P 2 . As a result, current IDN 2  equals current IRN. 
     Resistor RN is a voltage controlled resistor wherein the resistance of resistor RN varies based on voltage VOUTN. A voltage value of voltage VOUTN results in a corresponding resistance value of resistor RN and a corresponding current value of current IRN. Because current IDN 2  equals current IRN, a voltage value of voltage VOUTN results in a corresponding current value of current IDN 2 . As current IDN 2  changes, current IDN in  FIG. 7  also changes. Effectively, current adjustor  720  adjusts current IDN based on a change in voltage VDN with reference to reference voltage VREFN. For example, when voltage VDN decreases, voltage VOUTN decreases, and the resistance of resistor RN increases. A voltage dropped across resistor RN increases. A voltage dropped across a gate and a source of transistor P 2 , which is also a voltage dropped across a gate and a source of transistor P 2 , decreases. As a result, current IDN 2  decreases. 
       FIG. 9  is a circuit diagram a PMOS transistor P 900 , in accordance with some embodiments. Transistor P 900  functions as both voltage detector  710  and current adjustor  720  in  FIG. 7 . In other words, transistor P 900  functions as circuit  800  in  FIG. 8 . A reference voltage VREFN is at a source of transistor P 900  while voltage VDN is at a gate of transistor P 900 . Current ID 2  flows through the drain and the source of transistor P 900 . In some embodiments, voltage VREFN is set at operational voltage VDD. By operation of PMOS transistor P 900 , a change in voltage VDN at the gate of transistor P 900  results in a corresponding change in the voltage drop across the gate and the source of transistor P 900 , and also a change in current IDN 2 . Effectively, PMOS transistor P 900  provides a change in a current value of current IDN 2  based on a change in a voltage value of voltage VDN. For example, when voltage VDN decreases, by operation of transistor P 900 , current IDN 2  decreases. 
     Bias Current, Further Embodiments 
       FIG. 10  is a diagram of a circuit  1000 , in accordance with some embodiments. Circuit  1000  is an implementation of current bias  730  in  FIG. 7 . An NMOS transistor MN 1 A, based on voltage VCOINN, generates a current flowing from a drain to a source of transistor MN 1 A, which, effectively, is a current IMP 1 B that flows from a source to a drain of PMOS transistor MP 1 B. PMOS transistors MP 1 B and a PMOS transistor MP 1 C form a current mirror. Gates of transistors MP 1 B and MP 1 C are coupled together and to the drain of transistor MP 1 B. Current IMP 1 B flows through the drain of transistor MP 1 B while current IDN 1  flows through a drain of transistor MP 1 C. As a result, current IDN 1  equals current IMP 1 B. In some embodiments, a value of current IDN 1  is determined, resulting in a corresponding value for current IMP 1 B. Voltage VCOINN is adjusted to provide current IMP 1 B. Effectively, current IDN 1  is provided based on current VCOINN. 
     Application Circuit, Further Embodiments 
       FIG. 11  is a diagram of a circuit  1100 , in accordance with some embodiments. Circuit  1100  is an embodiment of application circuit  740  in  FIG. 7 . Circuit  1100  is formed by a plurality of inverters  1105 - 1  to  1105 -M in which M is an odd number. Circuit  1100  is called a ring oscillator or a current controlled oscillator (CCO), and functions based on current IVDN and voltage VDN. 
       FIG. 12  is a diagram of a circuit  1200 , in accordance with some embodiments. Circuit  1200  is another embodiment of application circuit  740  in  FIG. 7 . Circuit  1200  includes PMOS transistors P 1210  and P 1220  that form a current mirror. Gates of transistors P 1210  and P 1220  are coupled together and to a drain of transistor P 1210 . Current IVDN and voltage VDN are from transistor MN 5  in  FIG. 7 . 
     A current I 1230  equals to current IVDN. As a result, in some embodiments, a current value of current I 1230  is predetermined. Voltage VCOINN in  FIG. 7  is adjusted to provide a corresponding value of current IVDN. Effectively, the predetermined value of current I 1230  is provided based on voltage VCOINN and current IVDN. 
     Exemplary Methods 
       FIG. 13  is a flowchart of a method  1300  of selecting a transistor N 300  in  FIG. 3  for use in circuit  100  in  FIG. 1 , in accordance with some embodiments. In this illustration, bias current  130  and application circuit  140  are not used in circuit  100 . Initially, transistor N 300  is not connected to circuit  100 . 
     In step  1305 , transistors M 5  and MV 2 I are set up by simulation to be in the TT corner, and to operate in the saturation mode. For example, the absolute value of voltage VsdM 5  is setup to be greater than the absolute value of voltage VodM 5 . Similarly, the absolute value of voltage VsdMV 2 I is setup to be greater than the absolute value of voltage VodMv 2 I. An operating temperature is 25° C., and operational voltage VDD is at 1.8 V. 
     In step  1310 , voltage margins VmM 5  and VmMV 2 I of respective transistors M 5  and MV 2 I are checked with a low voltage and a high temperature (LVHT) condition and the low voltage and a low temperature (LVLT) condition. In some embodiments, in the LVLT condition, operational voltage VDD is 90% of typical voltage VDD or 90% of 1.8 V, and the temperature is at 40° C. In the LVHT condition, operational voltage VDD is 90% of typical voltage VDD, and the temperature is at 125° C. 
     In step  1315 , transistor N 300  is configured as part of circuit  100  in  FIG. 1 . 
     In step  1320 , voltage margins VmM 5  and VmMV 2 I of corresponding transistors M 5  and MV 2 I are checked by simulation at various PVT corners in which circuit  100  is expected to operate. Exemplary PVT corners are shown in  FIG. 14 . 
     In step  1325 , it is determined whether voltage margins VmM 5  and VmMV 2 I are satisfied in each of various PVT corners. For example, at a particular PVT corner, it is determined whether the absolute value of voltage VsdM 5  is greater than the absolute value of voltage VodM 5  by a predetermined voltage, such as 100 mV. Similarly, at a particular PVT corner, it is determined whether the absolute value of voltage VsdMV 2 I is greater than the absolute value of voltage VodMV 2 I by another predetermined voltage, such as 100 mV. 
     If voltage margins VmM 5  and VmMV 2 I are not satisfied, the size of transistor N 300  is changed in step  1330  to increase current ID 2 . For illustration W represents a width and L represents a length of transistor N 300 . In some embodiments, a ratio W/L of transistor N 300  is increased to increase current ID 2 . Voltage margins VmM 5  and VmMV 2 I are then checked again at various PVT corners in step  1320 . 
     In step  1335 , when voltage margins VmM 5  and VmMV 2 I are acceptable, transistor N 300  is selected for use in circuit  100 . For example, at each PVT corner, the absolute value of voltage VsdM 5  is greater than the absolute value of voltage VodM 5  by the predetermined voltage of 100 mV. Similarly, at each PVT corner, the absolute value of voltage VsdMV 2 I is greater than the absolute value of voltage VodMV 2 I by the predetermined voltage of 100 mV. As a result, both transistors M 5  and MV 2 I operate in the saturation mode in various PVT corners. 
     In the flow diagram shown in  FIG. 13 , transistor N 300  as depicted in  FIG. 3  is used in circuit  100  for illustration. When circuit  200  is used in place of transistor N 300 , the resistance of resistor R is adjusted in step  1330  to adjust current ID 2  for voltage margins VmM 5  and VmMV 2 I of corresponding transistors M 5  and MV 2 I to be satisfied in various PVT corners. When transistor N 900  is used in circuit  700 , selecting transistor P 900  for use in circuit  700  is similar to selecting transistor N 300  for use in circuit  100 . When circuit  800  is used in place of transistor P 900  in circuit  700 , the resistance of resistor RN is adjusted in step  1330  to adjust current IDN 2  for voltage margins VmMN 5  and VmMNV 2 I of corresponding transistors MN 5  and MNV 2 I to be satisfied in various PVT corners. 
       FIG. 14  is a table  1400  illustrating various PVT corners used by circuit  100 , in accordance with some embodiments. The device process column corresponds to the letter P in the reference “PVT.” The supply voltage column corresponds to the letter V, and the temperature column corresponds to the letter T. As illustratively shown in  FIG. 14 , at each process corner TT, SS, and FF, operational voltage value VDD, 90% of voltage VDD value, and 110% of voltage VDD value are used. At each operational voltage value, temperatures 25° C., 125° C. and −40° C. are used. In some embodiments, typical operational voltage VDD value is at 1.8 V. 
       FIG. 15  is a flow chart of a method  1500  illustrating an operation of circuit  100 , in accordance with some embodiments. In this illustration, circuit  200  in  FIG. 2  is used to function as voltage detector  110  and current adjustor  120  in  FIG. 1 . 
     In operation  1505 , circuit  100  is operated. For illustration, both transistors MV 2 I and M 5  operate in the saturation mode. 
     In operation  1510 , for illustration, the absolute value of voltage VD increases a voltage value ΔVD. 
     In operation  1515 , voltage detector  110  detects the increase ΔVD of voltage VD. 
     In operation  1520 , voltage detector  110  provides voltage VOUT in  FIG. 2  to voltage adjustor  120  based on voltage ΔVD. In some embodiments, voltage VREF is 0 V. Voltage VOUT is therefore ΔVD. 
     In operation  1525 , current adjustor  120  adjusts resistor R, and generates corresponding currents IR and current ID 2 . Because ID=ID 1 −ID 2 , current adjustor  120 , effectively, adjusts current ID 2  and current ID. In some embodiments, current ID 2  increases and current ID therefore decreases when the absolute value of voltage VD increases. 
     In operation  1530 , the absolute value of voltage VsgM 3  decreases in response to the decrease in the absolute value of current ID. The absolute value of voltage VsdMV 2 I also decreases. 
     In operation  1535 , the absolute value of voltage VsdM 5 , which is VDD−VsgM 3 −VD, increases such that the absolute value of voltage VsdM 5  is greater than the absolute value of voltage VodM 5 , which is VsgM 5 −VthM 5 . As a result, transistor M 5  continues to operate in the saturation mode. At the same time, the absolute value of voltage VsdMV 2 I also increases to be greater than the absolute value of voltage VodMV 2 I such that transistor MV 2 I continues to operate in the saturation mode. 
     In the illustration of  FIG. 15 , circuit  200  in  FIG. 2  is used in circuit  100 . When transistor N 300  is used in place of circuit  200 , the operation of circuit  100  is similar. An operation of circuit  700  when the absolute value of voltage VDN decreases to keep transistors MNV 2 I and MN 5  continue operating in the saturation mode is similar to the operation of circuit  100  when the absolute value of voltage VD increases to keep transistors MV 2 I and M 5  continue operating in the saturation mode. 
     A number of embodiments have been described. It will nevertheless be understood that various modifications may be made without departing from the spirit and scope of the disclosure. For example, various transistors being shown as a particular dopant type (e.g., N-type or P-type Metal Oxide Semiconductor (NMOS or PMOS)) are for illustration. Embodiments of the disclosure are not limited to a particular type. Selecting different dopant types for a particular transistor is within the scope of various embodiments. The low or high logical level of various signals used in the above description is also for illustration. Various embodiments are not limited to a particular level when a signal is activated and/or deactivated. Selecting different levels is within the scope of various embodiments. 
     In some embodiments, a circuit comprises a cascode core circuit and a current adjustor circuit. The cascode core circuit has an output node and a current path (ID). The current adjustor circuit is configured to change a current on the current path in response to a change in a voltage at the output node. The cascode core circuit comprises a first transistor, a second transistor, and a third transistor. A first terminal of the first transistor is coupled to a second terminal of the second transistor and to a third terminal of the third transistor. A first terminal of the second transistor is configured as the output node. A first terminal of the third transistor is coupled to a third terminal of the second transistor. The current path is through the first terminal of the third transistor. 
     In some embodiments, in a method of operating a cascode core circuit having a first transistor, a second transistor, and a third transistor, each of the first transistor and the second transistor of the cascode core circuit is operated in a saturation mode. The first transistor and the second transistor are continued to operate in the saturation mode in which a current of the cascode core circuit is adjusted in response to a change in a voltage at a first terminal of the second transistor. A first terminal of the first transistor is coupled to a second terminal of the second transistor and to a third terminal of the third transistor. A first terminal of the third transistor is coupled to a third terminal of the second transistor. The current of the cascode core circuit flows through the first terminal of the third transistor. 
     In some embodiments, a method of configuring a current adjustor for use with a cascode core circuit that includes a first transistor, a second transistor, and a third transistor is performed. In the method, each of the first transistor and the second transistor are operated in a first condition in which the first transistor and the second transistor each operate in a saturation mode at a first temperature and at a first operational voltage value. A current value of the current adjustor is selected such that the first transistor and the second transistor each operate in a second condition and in a third condition. In the second condition, the first transistor and the second transistor each operate in the saturation mode, at a second operational voltage value lower than the first operational voltage value, and at a second temperature higher than the first temperature. In the third condition, the first transistor and the second transistor each operate in the saturation mode, at a third operational voltage lower than the first operational voltage value, and at a third temperature lower than the first temperature. A first terminal of the first transistor is coupled to a second terminal of the second transistor and to a third terminal of the third transistor. A first terminal of the third transistor is coupled to a third terminal of the second transistor. A current path is through the first terminal of the third transistor. A current on the current path is adjusted based on a voltage at a first terminal of the second transistor and by the current value of the current adjustor. 
     In various embodiments, a transistor functions as a switch. A switching circuit used in place of a transistor is within the scope of various embodiments. Various figures show resistors and capacitors for illustration. Equivalent circuitry may be used. For example, a resistive device, circuitry or network such as a combination of resistors, resistive devices, circuitry, etc., can be used in place of the resistor. Similarly, a capacitive device, circuitry or network such as a combination of capacitors, capacitive devices, circuitry, etc., can be used in place of the capacitor. 
     The above illustrations include exemplary steps, but the steps are not necessarily performed in the order shown. Steps may be added, replaced, changed order, and/or eliminated as appropriate, in accordance with the spirit and scope of disclosed embodiments.