Patent Publication Number: US-6218224-B1

Title: Nitride disposable spacer to reduce mask count in CMOS transistor formation

Description:
RELATED APPLICATIONS 
     This application contains subject matter similar to subject matter disclosed in U.S. patent application Ser. No. 09/305,098, filed on May 5, 1999, U.S. patent application Ser. No. 09/271,290, filed on Mar. 17, 1999, U.S. patent application Ser. No. 09/273,161, filed on Mar. 26, 1999 and U.S. patent application Ser. No. 09/268,713, filed on Mar. 17, 1999. 
    
    
     FIELD OF THE INVENTION 
     The present invention relates to a method of manufacturing a semiconductor device on a semiconductor substrate. The invention has particular applicability in manufacturing a plurality of semiconductor devices of different conductivity types on a single substrate. 
     BACKGROUND ART 
     Metal oxide semiconductor (MOS) devices typically comprise a pair of ion implanted source/drain regions in a semiconductor substrate, a channel region separating the source/drain regions, and a thin gate oxide and a conductive gate comprising polysilicon or other conductive material formed above the channel region. In a typical integrated circuit, a plurality of MOS devices of different conductivity types, such as n-type and p-type, are formed on a common substrate. 
     A traditional approach to forming MOS devices of different conductivity types on a single substrate is illustrated in FIGS. 1A-1G. As shown in FIG. 1A, field oxide areas  115  are formed, as by local oxidation of silicon (LOCOS) or shallow trench isolation (STI), in semiconductor substrate  100 , then a thin gate oxide  105  is thermally grown, and conductive gates  110 , such as polysilicon, are formed. A photoresist mask M 1  is thereafter formed on the areas to be subsequently implanted with p-type impurities, and substrate  100  is implanted, as by ion implantation, with n-type impurities NLDD to form lightly or moderately doped regions  120 , also called “shallow source/drain extensions” (see FIG.  1 B). Adverting to FIG. 1C, mask M 1  is then removed, and the areas previously implanted with impurities NLDD are masked with photoresist mask M 2 . Substrate  100  is thereafter implanted, as by ion implantation, with p-type impurities PLDD to form lightly or moderately doped regions  125 . 
     Next, as shown in FIG. 1D, sidewall spacers  130  are formed on the side surfaces of the gates  110 , as by depositing a blanket layer of a dielectric material, such as silicon nitride, and anisotropically etching. A photoresist mask M 3  is thereafter formed on the regions implanted with p-type impurities (see FIG.  1 E), and substrate  100  is implanted, as by ion implantation, with n-type impurities NS/D to form source/drain regions  135 , which include lightly or moderately doped regions  120 . Adverting to FIG. 1F, mask M 3  is then removed, and the areas previously implanted with impurities NS/D are masked with photoresist mask M 4 . Substrate  100  is thereafter implanted, as by ion implantation, with p-type impurities PS/D to form source/drain regions  140 . Mask M 4  is then removed, leaving the structure shown in FIG.  1 G. 
     Source/drain implants NS/D, PS/D are typically implanted at a higher energy and dosage than lightly or moderately doped implants NLDD, PLDD, so source/drain implants NS/D, PS/D penetrate deeper into substrate  100  than lightly or moderately doped implants NLDD, PLDD. Additionally, sidewall spacers  130  prevent moderate or heavy source/drain implants NS/D, PS/D from entering substrate  100  adjacent to or under gates  110  to obtain the desired device performance characteristics. Thus, source/drain regions  135 ,  140  have a step corresponding to spacer  130 . 
     Disadvantageously, the above-described methodology employs four photoresist masks (M 1 -M 4 ), each of which requires the steps of spinning on the photoresist, exposing it with a stepper, developing the photoresist, and stripping off the mask after ion implantation. Each of these steps adds to the cost of the semiconductor device and decreases manufacturing throughput, and also subjects the device to additional handling, thereby increasing the likelihood of defects. 
     Moreover, masks M 1 -M 4  are all “critical masks”; i.e., extremely complex and difficult to design and use. The large number of fine features required to form the masks challenge the capabilities of the photolithographic process necessary to implement them, thereby increasing manufacturing costs and reducing production throughput. As design rules are reduced to 0.18 μm and under; e.g., 0.15 μm and under, to meet increasing demands for miniaturization and higher circuit density, shrinking feature sizes cause masks such as M 1 -M 4  to become even more difficult and costly to design and use. 
     Copending U.S. patent applications Ser. No. 09/271,290, Ser. No. 09/277,161 and Ser. No. 09/268,713 disclose a methodology for manufacturing MOS semiconductor devices with a reduced number of critical masks wherein conductive gates are formed on the main surface of a semiconductor substrate, and disposable sidewall spacers are formed on side surfaces of the gates. A mask is then formed on some of the gates, the mask extending onto the main surface adjacent to those gates to cover intended source/drain regions to be implanted with impurities of a first conductivity type. 
     Moderate or heavy source/drain implants of a second impurity type are thereafter formed in the substrate, as by ion implantation, adjacent to the unmasked gates. The disposable sidewall spacers on the unmasked gates are then removed, and lightly or moderately doped source/drain extension implants of the second impurity type are formed in the substrate, as by ion implantation. The first mask is then removed and a second photoresist mask is formed on the previously uncovered gates, the mask extending onto the main surface to cover the previous source/drain implants. Moderate or heavy source/drain implants with impurities of the first conductivity type are then formed, the remaining disposable sidewall spacers are removed, and lightly or moderately doped source/drain extension implants of the first conductivity type formed. The substrate is thereafter heated to diffuse and electrically activate the implants, thereby forming source/drain regions in the substrate. 
     By reversing the lightly or moderately doped source/drain extension and moderate or heavy source/drain implantation sequence of conventional MOS formation methodologies and employing disposable spacers, the methodologies of the copending applications reduce the critical masking steps from four to two. However, since the disposable spacers are removed during the transistor formation process, another spacer must be formed on the gate sidewalls if silicided contacts are to be formed on the source/drain regions and the gate. Moreover, since there are no spacers on the gate sidewalls when the lightly or moderately doped source/drain extension implants are performed, impurities are implanted immediately adjacent to the gate, and diffuse under the gate when the substrate is heated to form the source/drain junctions, resulting in increased gate to source/drain overlap capacitance and, therefore, degraded device AC performance. For optimal transistor performance, the source/drain junctions are typically located proximal to, but not under, the gate edges. Thus, the methodologies of the copending applications result in source/drain junction placement that adversely affects the electrical characteristics of the finished device. 
     Accordingly, there exists a need for a method of manufacturing MOS semiconductor devices with a reduced number of critical masks that does not degrade device performance. 
     SUMMARY OF THE INVENTION 
     An advantage of the present invention is a method of forming a plurality of MOS devices of different conductivity types on a common substrate using a minimal number of critical masks, thereby reducing manufacturing costs and increasing production throughput, which method enables optimization of the location of the source/drain junctions of the finished device. 
     Additional advantages and other features of the present invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present invention. The advantages of the present invention may be realized and obtained as particularly pointed out in the appended claims. 
     According to the present invention, the foregoing and other advantages are achieved in part by a method of manufacturing a semiconductor device, which method comprises forming first and second conductive gates on a main surface of a semiconductor substrate with a gate dielectric layer therebetween; forming sidewall spacers on side surfaces of the gates and extending onto the main surface; forming nitride disposable spacers on the sidewall spacers and extending onto the main surface; forming a first mask on the first gate and extending onto a first portion of the main surface; ion implanting impurities, using the second gate, sidewall spacers and disposable spacers thereon as a mask, to form first moderate or heavy source/drain implants; removing the disposable spacers from the sidewall spacers of the second gate; ion implanting impurities, using the second gate and sidewall spacers thereon as a mask, to form first lightly or moderately doped source/drain extension implants; removing the first mask; forming a second mask on the second gate and extending onto a second portion of the main surface; ion implanting impurities, using the first gate, sidewall spacers and disposable spacers thereon as a mask, to form second moderate or heavy source/drain implants; removing the disposable spacers on the sidewall spacers of the first gate; and ion implanting impurities, using the first gate and sidewall spacers thereon as a mask, to form second lightly or moderately doped source/drain extension implants. 
     Additional advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description, wherein only the preferred embodiment of the present invention is shown and described, simply by way of illustration of the best mode contemplated for carrying out the present invention. As will be realized, the present invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Reference is made to the attached drawings, wherein elements having the same reference numeral designations represent like elements throughout, and wherein: 
     FIGS. 1A-1G schematically illustrate sequential phases of a conventional method of forming MOS semiconductor devices. 
     FIGS. 2A-2J schematically illustrate sequential phases of a method in accordance with an embodiment of the present invention. 
    
    
     DESCRIPTION OF THE INVENTION 
     Conventional methodologies for manufacturing MOS semiconductor devices employ an unduly large number of photoresist masking steps, which increases the cost of the finished device and reduces manufacturing yield. The present invention addresses and solves these problems stemming from conventional complex manufacturing processes, while maintaining the ability to optimize device performance. 
     Embodiments of the present invention include forming conductive gates on the main surface of a semiconductor substrate, sidewall spacers, such as oxide spacers, on the side surfaces of the gates, and nitride disposable spacers on the sidewall spacers. As used throughout the present disclosure and claims, the term “substrate” denotes a semiconductor substrate or an epitaxial layer formed on the semiconductor substrate. A mask is then formed on some of the gates, the mask extending onto the main surface adjacent to those gates to cover intended source/drain regions to be implanted with impurities of a first conductivity type. 
     Moderate or heavy source/drain implants of a second impurity type are thereafter formed in the substrate, as by ion implantation, adjacent to the unmasked gates. The disposable spacers on the sidewall spacers of the unmasked gates are then removed, and lightly or moderately doped source/drain extension implants of the second impurity type are formed in the substrate, as by ion implantation. The first mask is then removed and a second photoresist mask is formed on the previously uncovered gates, the mask extending onto the main surface to cover the previous source/drain implants. 
     Moderate or heavy source/drain implants with impurities of the first conductivity type are then formed, the remaining disposable spacers are removed, and lightly or moderately doped source/drain extension implants of the first conductivity type formed. By reversing the lightly or moderately doped source/drain extension and moderate or heavy source/drain implantation sequence of conventional MOS formation methodologies and employing disposable spacers, the critical masking steps are reduced from four to two, thereby significantly reducing production cycle time, the amount of handling of the devices during processing, and the potential for defects. Moreover, due to the provision of sidewall spacers on the gates during the formation of the lightly or moderately doped source/drain extension implants, the location of these implanted impurities relative to the edges of the gate can be tailored to optimize the performance of the finished device. 
     An embodiment of the present invention is illustrated in FIGS. 2A-2J. Referring to FIG. 2A, field oxide regions  205  are formed in a semiconductor substrate  200 , as by STI or LOCOS. A gate oxide layer  210  is formed, as by thermal oxidation, on main surface  200   a  of substrate  200 , followed by conductive gates  215   a,    215   b,  such as by deposition of a polysilicon layer, masking of the polysilicon layer, and etching. Gates  215   a  will be associated with source/drain regions formed by implantation of n-type impurities, and gates  215   b  will be associated with source/drain regions formed by implantation of p-type impurities. 
     A layer  220  of an insulating material, such as silicon dioxide, is then deposited, as by low pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD), to a thickness of about 100 Å to about 300 Å (see FIG.  2 B). The oxide layer  220  is then anisotropically etched to form sidewall spacers  225   a,    225   b  on the side surfaces of gates  215   a,    215   b,  respectively. After the etching procedure, sidewall spacers  225   a,    225   b  preferably extend onto main surface  200   a  about 75 Å to about 240 Å (see FIG.  2 C). 
     Next, as shown in FIG. 2D, a conformal layer of silicon nitride  230  is deposited, as by LPCVD, PECVD or rapid thermal chemical vapor deposition (RTCVD), to a thickness of about 600 Å to about 1200 Å. The nitride layer  230  is then anisotropically etched to form disposable spacers  235   a,    235   b  on sidewall spacers  225   a,    225   b,  respectively. After the etching procedure, spacers  235   a,    235   b  extend onto main surface  200   a  about 360 Å to about 800 Å, depending on the thickness of conformal nitride layer  230  (see FIG.  2 E). 
     The sum D of the distance sidewall spacers  225   a,    225   b  extend onto main surface  200   a  and the distance disposable spacers  235   a,    235   b  extend onto main surface  200   a  is preferably about 435 Å to about 1100 Å. The distance sidewall spacers  225   a,    225   b  extend onto main surface  200   a  determines the placement of subsequently formed lightly or moderately doped source/drain extension junctions with respect to the edges  215   c  of gates  215   a,    215   b.  Likewise, the distance disposable spacers  235   a,    235   b  extend onto main surface  200   a  determines the placement of subsequently formed moderately or heavily doped source/drain junctions with respect to gate edges  215   c.  Since the locations of these source/drain junctions significantly affect transistor electrical characteristics, the sizes of sidewall spacers  225   a,    225   b  and disposable spacers  235   a,    235   b  can be tailored to optimize the performance of the finished devices. 
     Next, referring to FIG. 2F, a photoresist mask M 1  is formed on gates  215   b  and extending onto main surface  200   a  to cover portions of main surface  200   a  corresponding to subsequently formed p-type moderate or heavy source/drain implants. N-type impurities NS/D, such as arsenic, phosphorus and/or other materials to enhance transistor characteristics, are then implanted, as by ion implantation, in substrate  200  to form n-type moderate or heavy source/drain implants  240 . Adverting to FIG. 2G, disposable spacers  235   a  are thereafter removed, as by wet or dry etching selective to removing nitride (i.e., not reactive with the photoresist of mask M 1 ). N-type impurities NLDD, such as arsenic, phosphorus and/or other materials to enhance transistor characteristics, are then implanted, as by ion implantation, in substrate  200  to form n-type lightly or moderately doped source/drain extension implants  245 , which form n-type stepped source/drain implants  250  in conjunction with n-type moderate or heavy source/drain implants  240 . As in conventional MOS processing, impurities NLDD are implanted at a dosage about 1-2 orders of magnitude lower than that of impurities NS/D, and at a substantially lower energy; e.g., less than about 10 keV versus about 30 keV for NS/D. 
     Referring to FIG. 2H, mask M 1  is thereafter removed, and photoresist mask M 2  is formed on gates  215   a  and extending onto main surface  200   a  to cover the previously implanted n-type stepped source/drain implants  250 . P-type impurities PS/D, such as boron and/or other materials to enhance transistor characteristics, are then implanted, as by ion implantation, in substrate  200  to form p-type moderate or heavy source/drain implants  255 . Adverting to FIG. 2I, disposable spacers  235   b  are thereafter removed, as by wet or dry etching. P-type impurities PLDD, such as boron and/or other materials to enhance transistor characteristics, are then implanted, as by ion implantation, in substrate  200  to form p-type lightly or moderately doped source/drain extension implants  260  which form p-type stepped source/drain implants  265  in conjunction with p-type moderate or heavy source/drain implants  255 . As in conventional MOS processing, impurities PLDD are implanted at a dosage about 1-2 orders of magnitude lower than that of impurities PS/D, and at a substantially lower energy; e.g., less than about 10 keV versus about 20 keV for PS/D. 
     The materials of sidewall spacers  225   a,    225   b  and disposable spacers  235   a,    235   b  are chosen such that disposable spacers  235   a,    235   b  are removable without drastically altering the shape of sidewall spacers  225   a,    225   b.  In other words, when disposable spacers  235   a,    235   b  are etched off sidewall spacers  235   a,    235   b,  the profile of sidewall spacers  235   a,    235   b  is preferably preserved. Silicon nitride is advantageously employed as a material for disposable spacers  235   a,    235   b  because it can be easily etched without damage to previously formed oxide features such as sidewall spacers  225   a,    225   b,  as well as field oxide  205 . Moreover, silicon nitride can be easily etched without damage to gate oxide  210  protecting main surface  200   a,  thereby avoiding gouging of the silicon of substrate  200 . 
     After removing mask M 2 , as shown in FIG. 2J, substrate  200  is heated to diffuse and electrically activate implanted impurities NLDD, PLDD, NS/D and PS/D in stepped source/drain implants  250  and  265  to form source/drain regions  270 ,  275 , as by rapid thermal annealing at a temperature of about 900° C. to about 1100° C. for less than about 30 seconds. Preferably, NS/D and NLDD implants are performed at a higher energy than the PS/D and PLDD implants, resulting in the n-type stepped source/drain implants  250  being deeper than p-type stepped source/drain implants  265  prior to the heating step. N-type impurities diffuse less quickly when heated than p-type impurities. Thus, by employing higher energy to form n-type stepped source/drain implants  250  deeper than p-type stepped source/drain implants  265 , the depths of both n-type and p-type junctions  270 J,  275 J are optimized after the heating step, resulting in improved device performance. 
     Sidewall spacers  225   a,    225   b  prevent impurities of lightly or moderately doped source/drain extension implants  245 ,  260  from being implanted at or under gate edges  215   c.  As a result, impurities are not diffused under gates  215   a,    215   b  during the heating step, and source/drain regions  270 ,  275  extend to the proximity of gate edges  215   c  after the heating step, thereby further improving device performance. 
     In another embodiment of the invention, a first heating step is performed, such as rapid thermal annealing at a temperature of about 900° C. to about 1100° C. for less than about 30 seconds, after formation of n-type source/drain regions  250  and removal of mask M 1 , to tailor the depth of junctions  270 J. A second heating step is then performed after formation of p-type source/drain regions  265  and removal of mask M 2 , such as rapid thermal annealing at a temperature of about 900° C. to about 1100° C. for less than about 30 seconds. As explained above, N-type impurities diffuse less quickly when heated than p-type impurities. Thus, by employing a two-step heating process to apply heat to n-type stepped source/drain implants  250  for a longer period of time than p-type stepped source/drain implants  265 , the depths of both n-type and p-type junctions  270 J,  275 J are optimized, resulting in improved device performance. 
     Subsequent processing steps include conducting a silicidation process to form electrodes on gates  215   a,    215   b  and on source/drain regions  270 ,  275 , employing sidewall spacers  225   a,    225   b  as insulators. Alternatively, a dielectric layer can be deposited over main surface  200   a  and gates  215   a,    215   b,  and contact holes to source/drain regions  270 ,  275  and gates  215   a,    215   b  patterned. 
     Due to the use of disposable spacers  235   a,    235   b,  the present methodology enables two implants (a moderate or heavy source/drain implant and a lightly or moderately doped source/drain extension implant) to be performed with a single mask, thereby reducing the number of critical masks needed for the formation of a plurality of MOS transistors of different conductivity types from four to two. Thus, production costs are reduced, as well as production cycle time, the amount of handling to which the devices are subject during processing, and the potential for defects, resulting in improved manufacturability and yield. 
     Furthermore, sidewall spacers  225   a,    225   b  prevent dopants from being implanted at or under gate edges  215   c.  As a result, dopants do not diffuse under gates  215   a,    215   b  during source/drain junction formation (i.e., the heating step), thereby enabling optimization of junction location proximal to gate edges  215   c  and improved performance vis-a-vis devices produced according to the methodology of copending U.S. patent applications Ser. No. 09/271,290, Ser. No. 09/277,161, and Ser. No. 09/268,713. 
     The present invention is applicable to the manufacture of various types of semiconductor devices, particularly high density semiconductor devices having a design rule of about 0.18μ and under. 
     The present invention can be practiced by employing conventional materials, methodology and equipment. Accordingly, the details of such materials, equipment and methodology are not set forth herein in detail. In the previous descriptions, numerous specific details are set forth, such as specific materials, structures, chemicals, processes, etc., in order to provide a thorough understanding of the present invention. However, it should be recognized that the present invention can be practiced without resorting to the details specifically set forth. In other instances, well known processing structures have not been described in detail, in order not to unnecessarily obscure the present invention. 
     Only the preferred embodiment of the present invention and but a few examples of its versatility are shown and described in the present disclosure. It is to be understood that the present invention is capable of use in various other combinations and environments and is capable of changes or modifications within the scope of the inventive concept as expressed herein.