Patent Publication Number: US-2023157010-A1

Title: Integrated circuit including efuse cell

Description:
RELATED APPLICATIONS 
     This application is continuation of U.S. application Ser. No. 16/990,995, filed Aug. 11, 2020, now U.S. Pat. No. 11,569,248, issued Jan. 31, 2023, which is herein incorporated by reference. 
    
    
     BACKGROUND 
     A non-volatile memory (NVM) is provided in an integrated circuit (IC). The NVM is able to retain data after the IC is turned off. Some of the NVM utilize technologies including, for example, electrical fuse (eFuse), to implement reprogram the IC. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. 
         FIG.  1    is a circuit schematic diagram of a circuit, in accordance with some embodiments of the present disclosure. 
         FIG.  2    is a circuit schematic diagram of an electrical fuse (eFuse) circuit corresponding to the eFuse circuit shown in  FIG.  1   , in accordance with some embodiments of the present disclosure. 
         FIG.  3 A  is a circuit schematic diagram of an eFuse cell corresponding to one of the eFuse cells shown in  FIG.  2   , in accordance with some embodiments of the present disclosure. 
         FIG.  3 B  is a layout structure of an eFuse cell corresponding to the eFuse cell shown in  FIG.  3 A , in accordance with some embodiments of the present disclosure. 
         FIG.  4 A  is a circuit schematic diagram of an eFuse cell corresponding to the eFuse cells shown in  FIG.  2   , in accordance with some embodiments of the present disclosure. 
         FIG.  4 B  is a layout structure of an eFuse cell corresponding to the eFuse cell shown in  FIG.  4 A , in accordance with some embodiments of the present disclosure. 
         FIG.  4 C  is a cross-section schematic diagram of an eFuse cell corresponding to the eFuse cell shown in  FIG.  4 B , in accordance with some embodiments of the present disclosure. 
         FIG.  5 A  is a layout structure of an eFuse cell corresponding to the eFuse cell shown in  FIG.  4 A , in accordance with some embodiments of the present disclosure. 
         FIG.  5 B  is a cross-section schematic diagram of an eFuse cell corresponding to the eFuse cell shown in  FIG.  5 A , in accordance with some embodiments of the present disclosure. 
         FIG.  6 A  is a circuit schematic diagram of an eFuse cell corresponding to the eFuse cells shown in  FIG.  2   , in accordance with some embodiments of the present disclosure. 
         FIG.  6 B  is a layout structure of an eFuse cell corresponding to the eFuse cell shown in  FIG.  6 A , in accordance with some embodiments of the present disclosure. 
         FIG.  7    is a schematic diagram of a circuit path for an eFuse cell corresponding to the eFuse cells shown in  FIG.  2   , in accordance with some embodiments of the present disclosure. 
         FIG.  8 A  is a flow chart of a method for generating an integrated circuit (IC) layout diagram including an eFuse cell, in accordance with some embodiments of the present disclosure. 
         FIG.  8 B  is a flow chart of a method for generating an integrated circuit (IC) including an eFuse cell, in accordance with some embodiments of the present disclosure. 
         FIG.  9    is a block diagram of a system for designing an IC layout design, in accordance with some embodiments of the present disclosure. 
         FIG.  10    is a block diagram of an IC manufacturing system, and an IC manufacturing flow associated therewith, in accordance with some embodiments. 
     
    
    
     DETAILED DESCRIPTION 
     The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. 
     The terms used in this specification generally have their ordinary meanings in the art and in the specific context where each term is used. The use of examples in this specification, including examples of any terms discussed herein, is illustrative, and in no way limits the scope and meaning of the disclosure or of any exemplified term. Likewise, the present disclosure is not limited to various embodiments given in this specification. 
     Although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the embodiments. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. 
     In this document, the term “coupled” may also be termed as “electrically coupled”, and the term “connected” may be termed as “electrically connected”. “Coupled” and “connected” may also be used to indicate that two or more elements cooperate or interact with each other. 
     Furthermore, spatially relative terms, such as “underlying,” “below,” “lower,” “overlying,” “upper” and the like, may be used throughout the description for ease of understanding to describe one element or feature&#39;s relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The structure may be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. 
     As used herein, “around”, “about”, “approximately” or “substantially” shall generally refer to any approximate value of a given value or range, in which it is varied depending on various arts in which it pertains, and the scope of which should be accorded with the broadest interpretation understood by the person skilled in the art to which it pertains, so as to encompass all such modifications and similar structures. In some embodiments, it shall generally mean within 20 percent, preferably within 10 percent, and more preferably within 5 percent of a given value or range. Numerical quantities given herein are approximate, meaning that the term “around”, “about”, “approximately” or “substantially” can be inferred if not expressly stated, or meaning other approximate values. 
     Reference is now made to  FIG.  1   .  FIG.  1    is a circuit schematic diagram of a memory circuit  100 , in accordance with some embodiments of the present disclosure. In some embodiments, the memory circuit  100  is also referred to a non-volatile memory (NVM) circuit. 
     For illustration in  FIG.  1   , the memory circuit  100  includes a program selection unit  110 , a read selection unit  120 , a sense amplifier  130 , a reference circuit  140  and an electrical fuse (eFuse) circuit FA. The program selection unit  110  is coupled to the eFuse circuit FA, and is configured to receive a program signal including, for example, a program voltage VDDQ. The selection unit  120  is coupled between the sense amplifier  130  and the eFuse circuit FA, and is configured to receive a read signal including, for example, a read voltage VDD, coupled from the sense amplifier  130 . The sense amplifier  130  is coupled to the selection unit  120 , and is configured to receive the read signal. The eFuse circuit FA is coupled to both of the program selection unit  110  and the selection unit  120  at a node VQ. The reference circuit  140  is coupled to the sense amplifier  130 . 
     With continued reference to  FIG.  1   , a program path P 1  and a read path P 2  are also illustrated, for programming and reading the eFuse circuit FA, respectively. 
     The program path P 1  includes the program selection unit  110  that couples the program signal to the node VQ. In some embodiments, the program selection unit  110  includes a selection transistor T 1  which, in some embodiments, is p-type metal oxide semiconductor transistors (PMOS transistor). 
     The read path P 2  includes the read selection unit  120  and part of the sense amplifier  130  (i.e., a transistor T 3  shown in  FIG.  1   ). In some embodiments, the read selection unit  120  includes a selection transistor T 2  which, in some embodiments, is n-type metal oxide semiconductor transistors (NMOS transistor). The read selection unit  120  couples the read voltage signal to the node VQ. In some embodiments, the sense amplifier  130  includes transistors T 3  and T 4  which, in some embodiments, are PMOS. The transistors T 3  and T 4  form a current mirror, and couple the read path P 2  to the reference circuit  140  which includes, in some embodiments, a resistor Rref and a transistor T 5 . 
     The program path P 1  and the read path P 2  are selectively coupled to the node VQ by the program selection unit  110  and the read selection unit  120 , based on the memory circuit  100  being in a program operation or a read operation. 
     In the program operation, the program selection unit  110  and the read selection unit  120  disconnects the read path P 2 , and couple the node VQ to the program voltage VDDQ. The program voltage VDDQ is large enough, so the program signal provides a programming current through the eFuse circuit FA, to make some eFuse of the eFuse circuit FA be blown. 
     In the read operation, the program selection unit  110  and the read selection unit  120  disconnects the program path P 1 , and couple the node VQ to the sense amplifier  130 . The sense amplifier  130  determines whether a logic high (H) or a logic low (L) voltage exists at the node VQ based on the current through the eFuse circuit FA. If one eFuse of the eFuse circuit FA has been blown, the resistance of the eFuse would be large and the voltage at the node VQ would be high (i.e., H). If one eFuse of the eFuse circuit FA has not been blown, the voltage at the node VQ would be low (i.e., L). 
     The configuration of the memory circuit  100  as illustrated above is given for illustrative purposes. Various configurations of the memory circuit  100  are within the contemplated scope of the present disclosure. For example, in various embodiments, the program selection unit  110  is implemented by a NMOS transistor, and the read selection unit  120  is implemented by a PMOS transistor. 
     Reference is now made to  FIG.  2   .  FIG.  2    is a circuit schematic diagram of an eFuse circuit FA corresponding to the eFuse circuit FA shown in  FIG.  1   , in accordance with some embodiments of the present disclosure. 
     For illustration in  FIG.  2   , the eFuse circuit FA is arranged as an array and is arranged in rows and columns. The array is illustrated as having two columns and four rows of eFuse cells. Each rows of eFuse cells is coupled to corresponding word line including, for example of eFuse cell  220 , word line WL 0 , and each columns of eFuse cells is coupled to respective two bit lines including, for example, bit lines BL 0  and BL 1 . Each eFuse cells is individually accessible through the word line and the bit lines combination. 
     The eFuse cells included in the eFuse circuit FA shown in  FIG.  2    are designated as  220 ,  230 ,  240 ,  250 ,  260 ,  270 ,  280  and  290 . The eFuse cells  220 ,  240 ,  260  and  280  are arranged in one column connected to the bit line BL 0  and the bit line BL 1 . The eFuse cells  230 ,  250 ,  270  and  290  are arranged in another column connected to the bit line BL 2  and the bit line BL 3 . The eFuse cells  220  and  230  are arranged in one row connected to the word line WL 0 . Similarly, the eFuse cells  240  and  250  are arranged in the same row connected to the word line WL 1 , the the eFuse cells  260  and  270  are arranged in the same row connected to the word line WL 2 , and the eFuse cells  280  and  290  are arranged in the same row connected to the word line WL 3 . 
     Each eFuse cells  220 ˜ 290  includes two eFuse elements and one transistor element, and such configuration of each of eFuse cells is also indicated as 1T2R. With reference to  FIG.  2   , for example, the eFuse cell  220  includes the eFuse elements  221  and  222 , and the transistor element  223 . The eFuse elements  221  and  222  are coupled to the bit line BL 0  and the bit line BL 1 , respectively. The transistor element  223  is coupled between the eFuse elements  221  and  222 , and is further coupled to the word line WL 0 . Similarly, the eFuse cell  240  includes the eFuse elements  241  and  242 , and the transistor element  243 . The eFuse elements  241  and  242  are coupled to the bit line BL 0  and the bit line BL 1 , respectively. The transistor element  243  is coupled between the eFuse elements  241  and  242 , and is further coupled to the word line WL 1 . The eFuse cell  260  includes the eFuse elements  261  and  262 , and the transistor element  263 . The eFuse elements  261  and  262  are coupled to the bit line BL 0  and the bit line BL 1 , respectively. The transistor element  263  is coupled between the eFuse elements  261  and  262 , and is further coupled to the word line WL 2 . The eFuse cell  280  includes the eFuse elements  281  and  282 , and the transistor element  283 . The eFuse elements  281  and  282  are coupled to the bit line BL 0  and the bit line BL 1 , respectively. The transistor element  283  is coupled between the eFuse elements  281  and  282 , and is further coupled to the word line WL 3 . 
     The configuration of the eFuse circuit FA as illustrated above is given for illustrative purposes. Various configurations of the eFuse circuit FA are within the contemplated scope of the present disclosure. For example, in various embodiments, the word lines WL 0 , WL 1 , WL 2 , WL 3  and WL 4  are arranged in columns, and the bit lines BL 0 , BL 1 , BL 2  and BL 3  are arranged in rows. 
     Reference is now made to  FIG.  3 A .  FIG.  3 A  is a circuit schematic diagram of an eFuse cell  300 A corresponding to one of the eFuse cells including, for example, eFuse cells  220  shown in  FIG.  2   , in accordance with some embodiments of the present disclosure. 
     For illustration in  FIG.  3 A , the eFuse cell  300 A includes a fuse R 1  coupled to the bit line BL 0 , a fuse R 2  coupled to the bit line BL 1 , and a transistor T 1  coupled to the word line WL 0 . Since one transistor (i.e., the transistor T 1 ) coupled to two fuses (i.e., the fuses R 1  and R 2 ) included in one eFuse cell (i.e., the eFuse cell  300 A), the configuration of such eFuse cell is also indicated as 1T2R. Alternatively stated, for 1T2R as an eFuse cell, one word line (e.g., WL 0 ) and two bit line (e.g, BL 0  and BL 1 ) are included in one cell, in order to operate two bits in the program operation controlled by one word line and two bit lines. In some embodiments, the fuse R 1  corresponds to the eFuse element  221  shown in  FIG.  2   , the fuse R 2  corresponds to the eFuse element  222  shown in  FIG.  2   , and the transistor T 1  corresponds to the transistor element  223  shown in  FIG.  2   . Alternatively stated, the eFuse cell  300 A illustrates an equivalent circuit of the eFuse cell  220 . 
     The fuse R 1  and the fuse R 2  are coupled together, and each of the fuse R 1  and the fuse R 2  is coupled to the transistor T 1  which, in some embodiments, is NMOS. Alternatively stated, the transistor T 1  is coupled through the fuse R 1  to the bit line BL 0  for receiving data signals transmitted from the bit line BL 0 , and the transistor T 1  is also coupled through the fuse R 2  to the bit line BL 1  for receiving data signals transmitted from the bit line BL 1 . In addition, the transistor T 1  is coupled to the word line WL 0  for being controlled by the word line WL 0 . 
     The above implementation of the eFuse cell  300 A is provided for illustrative purposes. Various implementations of the eFuse cell  300 A are within the contemplated scope of the present disclosure. For example, in addition to the transistor T 1 , the eFuse cell  300 A includes two transistors (not shown) which, in some embodiments, are NMOS, coupled to the fuse R 1  and the fuse R 2  respectively. Alternatively stated, one transistor coupled between the fuse R 1  and the bit line BL 0 , for being controlled by the bit line BL 0 , and the other transistor coupled between the fuse R 2  and the bit line BL 1 , for being controlled by the bit line BL 1 . To explain in another way, the transistors discussed above are indicated as bit line selector transistors. 
     Reference is now made to  FIG.  3 B .  FIG.  3 B  is a layout structure  300 B of an eFuse cell corresponding to the eFuse cell  300 A shown in  FIG.  3 A , in accordance with some embodiments of the present disclosure. For illustration in  FIG.  3 B , the layout structure  300 B includes a transistor T 1 , a fuse element R 1  and a fuse element R 2 . The fuse element R 1  is disposed next to the fuse element R 2  in a layout view. In some embodiments, the fuse element R 1  is separated apart from the fuse element R 2  by a width of a fuse conductive segment cf 1 . In some embodiments, the fuse element R 1  and the fuse element R 2  are indicated as one pair of fuse element. For illustration in  FIG.  3 B , both of the element R 1  and the fuse element R 2  are arranged below the transistor T 1  in the layout view. In various embodiments, the transistor T 1  is partially overlapped with the fuse element R 1  in the layout view. For simplicity of illustration,  FIG.  3 B  only shows a portion of the layout structure  300 B. Other elements of the layout structure  300 B are within the contemplated scope of the present disclosure. 
     In some embodiments, the transistor T 1  is also referred to at least one selection transistors including, for example, a NMOS transistor, for being controlled by the word line WL 0  (which is also shown in  FIG.  3 A ). In some embodiments, the transistor T 1  corresponds to the transistor T 1  shown in  FIG.  3 A . 
     In some embodiments, the fuse element R 1  and the fuse element R 2  are also referred to eFuses and are coupled together, for being controlled by a same transistor (i.e., the transistor T 1 ) and also being controlled by the respective bit lines including, for example, BL 0  and BL 1  (which are shown in  FIG.  3 A  or  FIG.  6 B ). In some embodiments, the fuse element R 1  corresponds to the fuse R 1  shown in  FIG.  3 A . In other some embodiments, the fuse element R 2  corresponds to the fuse R 2  shown in  FIG.  3 A . In various embodiments, the fuse element R 1  and the fuse element R 2  are coupled through a conductive segment (i.e., a conductive segment CS 1  which is discussed below with reference to  FIGS.  5 A and  5 B ) to the transistor T 1 . 
     With continued reference to  FIG.  3 B , the transistor T 1  includes an active area AA, gates G and connection structures MD. The gates G are disposed above the active area AA, and the gates G extend to cross over the active area AA. The gates G are arranged separated. The connection structures MD are disposed above the active area AA, and the connection structures MD extend to cross over the active area AA. The connection structures MD and the gates G are arranged separated to each other, and are arranged alternately ordered. 
     The gates G and the connection structures MD are disposed below the word line WL 0 . Vias VG are disposed directly above the gates G, and couple the gates G to the word line WL 0 . The gates G are coupled to the word line WL 0  through vias VG and are configured to receive data signals transmitted from the word line WL 0 . In some embodiments, with reference to  FIG.  3 B , the word line WL 0  is arranged above the transistor T 1  in the layout view. In some other embodiments, the word line WL 0  is arranged below the transistor T 1  in the layout view. In various embodiments, the vias VG are disposed above the connection structures MD, and couple the connection structures MD to the word line WL 0 . 
     In some embodiments, the gates G are polysilicon gates. the active area AA is implemented by a doped region/area, in order for the formation of the transistor T 1  included in the eFuse cell  300 A as shown in  FIG.  3 A . In some embodiments, the active region AA is made of p-type doped material. In some other embodiments, the active region AA is made of n-type doped material. In some embodiments, the active region AA is configured for forming channels of transistors. In alternative embodiments, to form fin field-effect transistors (FinFETs), the active region AA is configured for forming fin structures. 
     The fins may be patterned by any suitable method. For example, the fins may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fins. 
     In some embodiments, in FinFETs, the connection structures MD are also referred to as fin connection structures or fin connection layer. For simplicity of illustration, few layout structures including, for example, gates G and connection structures MD are illustrated in the transistor T 1 . Various layout structures in the transistor T 1  are within the contemplated scope of the present disclosure. 
     With continued reference to  FIG.  3 B , the fuse element R 1  includes fuse segments  11 ,  21 ,  31  and  41 , a fuse line  51 , and fuse walls  61  and  63 . All of the fuse segments  11 ,  21 ,  31  and  41 , the fuse line  51 , and the fuse walls  61  and  63  are disposed in a same metal layer (i.e., the second metal layer M 2  shown in  FIG.  5 B , which is discussed below with reference to  FIGS.  5 A and  5 B ) above the transistor T 1 . In some embodiments, with reference to  FIG.  3 B , the fuse segments  11  and  21 , and the fuse wall  61  is partially overlapped with the gates G and connection structures MD in the layout view. 
     The fuse segments  11 ,  21 ,  31  and  41  are arranged separated from each other, and are arranged on sides of the fuse line  51 . The fuse walls  61  and  63  are arranged separated from each other, and are arranged on sides of the fuse line  51 . In some embodiments, the fuse segments  11  and  31  are referred as a pair of fuse segments, and are arranged on opposite sides of one end of the fuse line  51 . Also, the fuse segments  21  and  41  are referred as a pair of fuse segments, and are arranged on opposite sides of the other end of the fuse line  51 . In addition, the fuse walls  61  and  63  are referred as a pair of fuse walls, and are arranged on opposite sides of middle of the fuse line  51 . 
     In the program operations, in some embodiments, the fuse line  51  is blown, and the fuse walls  61  and  63  blocks residue including, for example, metal or oxide, from the blown fuse line  51 , for avoiding the residue interfering with other component of the eFuse cell. 
     In some embodiments, the fuse element R 1  is coupled through vias V 1  to the bit line BL 0  (which is shown in  FIG.  3 A  or  FIG.  6 B ) which is disposed in another metal layer above the fuse element R 1  (i.e., the third metal layer M 3  which is discussed below with reference to  FIG.  6 B ). In some embodiments, with reference to  FIG.  3 B , vias V 1  are arranged in the fuse segments  11  and  31 , and part of the fuse line  51 , for coupling the fuse element R 1  through the vias V 1  to the bit line BL 0 . Alternatively stated, the transistor T 1  is coupled through the fuse element R 1  to vias V 1 , and to the bit line BL 0 . 
     With continued reference to  FIG.  3 B , the fuse element R 2  includes fuse segments  12 ,  22 ,  32  and  42 , a fuse line  52 , and fuse walls  62  and  64 . Similar to the fuse element R 1 , all of the fuse segments  12 ,  22 ,  32  and  42 , the fuse line  52 , and the fuse walls  62  and  64  are disposed in the same metal layer where the fuse element R 1  disposed. With reference to  FIG.  3 B , the fuse conductive segment cf 1  is arranged between the fuse segment  21  and the fuse segment  12 , for coupling the fuse element R 1  and the fuse element R 2  to each other. In some embodiments, the fuse conductive segment cf 1  is arranged directly abuts between the fuse segment  21  and the fuse segment  12 . In some embodiments, the fuse conductive segment cf 1  is disposed in same metal layer where the fuse elements R 1 -R 2  are disposed. Therefore, the fuse segment  12  is coupled through the fuse conductive segment cf 1  to the fuse segment  21 . Alternatively stated, the fuse element R 1  is coupled through the fuse conductive segment cf 1  to the fuse element R 2 . 
     Similar to the fuse element R 1 , the fuse segments  12 ,  22 ,  32  and  42  are arranged separated from each other, and are arranged on sides of the fuse line  52 . The fuse walls  62  and  64  are arranged separated from each other, and are arranged on sides of the fuse line  52 . In some embodiments, the fuse segments  12  and  32  are referred as a pair of fuse segments, and are arranged on opposite sides of one end of the fuse line  52 . Also, the fuse segments  22  and  42  are referred as a pair of fuse segments, and are arranged on opposite sides of the other end of the fuse line  52 . In addition, the fuse walls  62  and  64  are referred as a pair of fuse walls, and are arranged on opposite sides of middle of the fuse line  52 . 
     In the program operations, in some embodiments, the fuse line  52  is blown, and the fuse walls  62  and  64  blocks residue including, for example, metal or oxide, from the blown fuse line  52 , for avoiding the residue interfering with other component of the eFuse cell. 
     In some embodiments, the fuse element R 2  is coupled through vias V 1  to the bit line BL 1  (which is shown in  FIG.  3 A  or  FIG.  6 B ) which is disposed in the same metal layer where the bit line BL 0  is disposed. In some embodiments, with reference to  FIG.  3 B , vias V 1  are arranged in the fuse segments  22  and  42 , and part of the fuse line  52 , for coupling the fuse element R 2  through the vias V 1  to the bit line BL 1 . Alternatively stated, the transistor T 1  is coupled through the fuse element R 2  to vias V 1 , and to the bit line BL 1 . 
     In some approaches, an eFuse cell, corresponding to, for example, the eFuse cell  300 A shown in  FIG.  3 A , includes one fuse coupled to one bit line and one transistor coupled to one word line. The eFuse cell is also indicated as 1T1R. A size of a layout structure of the eFuse cell is limited to metal spacing rule and gate pitch. A program path (which is discussed below with reference to  FIG.  7   ) refers to an equivalent circuit path of the eFuse cell in program operation, and a length of the program path corresponds to the size of the layout structure. The length of the program path is effected by the size of a layout structure of the eFuse cell. A resistance of the program path corresponding to the eFuse cell increases as the length of the program path being longer, and it would cause poor performance of the eFuse cell. 
     Compared to the above approaches, in the embodiments of the present disclosure, for example with reference to  FIGS.  3 A- 3 B , the eFuse cell which is indicated as 1T2R may reduce the size of the corresponding layout structure by two fuses sharing one transistor. Accordingly, the resistance of the program path corresponding to the eFuse cell in the program operation may be reduced, and the performance of the eFuse cell may be enhanced. 
     Reference is now made to  FIG.  4 A .  FIG.  4 A  is a circuit schematic diagram of an eFuse cell  400 A corresponding to the eFuse cells including, for example, eFuse cells  220  and  240  shown in  FIG.  2   , in accordance with some embodiments of the present disclosure. 
     For illustration in  FIG.  4 A , the eFuse cell  400 A includes a fuse R 1 , a fuse R 2 , a fuse R 3 , a fuse R 4 , a transistor T 1 , and a transistor T 2 . Since two transistors (i.e., the transistors T 1  and T 2 ) coupled to four fuses (i.e., the fuses R 1 -R 4 ) included in one eFuse cell (i.e., the eFuse cell  400 A), the configuration of such eFuse cell is also indicated as 2T4R. Alternatively stated, for 2T4R as an eFuse cell, two word lines (e.g., WL 0  and WL 1 ) and four bit line (e.g, BL 0  and BL 1 ) are included in one cell, in order to operate four bits in the program operation controlled by two word lines and two bit lines. In some embodiments, the fuses R 1  and R 2  and the transistor T 1  are the same as those of the eFuse cell  300 A shown in  FIG.  3 A . Accordingly, they are not further detailed herein. 
     Compared to the eFuse cell  300 A, the eFuse cell  400 A further includes the fuse R 3  coupled to the bit line BL 0 , the fuse R 4  coupled to the bit line BL 1 , and the transistor T 2  coupled to the word line WL 1 . In some embodiments, the fuse R 3  corresponds to the eFuse element  241  shown in  FIG.  2   , the fuse R 4  corresponds to the eFuse element  242  shown in  FIG.  2   , and the transistor T 2  corresponds to the transistor element  243  shown in  FIG.  2   . Alternatively stated, the eFuse cell  400 A illustrates an equivalent circuit of the eFuse cells  220  and  240 . 
     Similar to the fuses R 1  and R 2 , the fuse R 3  and the fuse R 4  are coupled together, and each of the fuse R 3  and the fuse R 4  is coupled to the transistor T 2  which, in some embodiments, is NMOS. Alternatively stated, the transistor T 2  is coupled through the fuse R 3  to the bit line BL 0  for receiving data signals transmitted from the bit line BL 0 , and the transistor T 2  is also coupled through the fuse R 4  to the bit line BL 1  for receiving data signals transmitted from the bit line BL 1 . In addition, the transistor T 2  is coupled to the word line WL 1  for being controlled by the word line WL 1 . In some embodiments, the transistors T 1  and T 2  have the same configuration or structure, and the fuses R 1 -R 4  have the same configuration or structure. 
     The above implementation of the eFuse cell  400 A is provided for illustrative purposes. Various implementations of the eFuse cell  400 A are within the contemplated scope of the present disclosure. For example, the transistors T 1  and T 2  are implemented by PMOS. 
     Reference is now made to  FIG.  4 B .  FIG.  4 B  is a layout structure  400 B of an eFuse cell corresponding to the eFuse cell  400 A shown in  FIG.  4 A , in accordance with some embodiments of the present disclosure. For illustration in  FIG.  4 B , the layout structure  400 B includes a transistor T 1 , a fuse element R 1 , a fuse element R 2 , a transistor T 2 , a fuse element R 3  and a fuse element R 4 . In some embodiments, the layout structure  400 B is symmetric with respect to horizontal direction in the layout view. In some embodiments, the fuse elements R 1  and R 2  and the transistor T 1  are the same as those of the layout structure  300 B shown in  FIG.  3 B . In some embodiments, the transistor T 2  has the same structure as the transistor T 1 . Accordingly, they are not further detailed herein. 
       FIG.  4 C  is a schematic diagram  400 C illustrating a cross-section view, viewing at a cross line LINE  1  of one of the gates G of the transistor T 1  shown in  FIG.  4 B , in accordance with some embodiments of the present disclosure. For ease of understanding, the embodiments with respect to  FIG.  4 C  are discussed with reference to  FIG.  4 B . 
     The gates G are disposed above and across over the active area AA in the layout view of the layout structure  400 B, as well as shown in  FIG.  4 C . In some embodiments, the vias VG are disposed above and overlap the gates G, in the layout view of the layout structure  400 B, as well as shown in  FIG.  4 C . Accordingly, in  FIG.  4 C , the schematic diagram  400 C only illustrates two gates G and the corresponding two vias VG disposed above the active area AA, for simplicity of illustration. In some embodiments, gate segments Cg are disposed above and overlap the gates G in the layout view, which is only shown in  FIG.  4 C  and not shown in  FIG.  4 B  for simplicity. In various embodiments, the gate segments Cg are configured to couple the gates G through the vias VG to the word line WL 0  or WL 1 . However, the present disclosure is not limited to the embodiments of  FIGS.  4 B- 4 C . Various positions or numbers of the vias VG are within the contemplated scope of the present disclosure. 
     The word lines WL 0  and WL 1  are disposed above and across over the gates G and the connection structures MD in the layout view of the layout structure  400 B, as well as shown in  FIG.  4 C . In some embodiments, the word lines WL 0  and WL 1  are formed in a metal-zero (M 0 ) layer, which is disposed above the gates G, the connection structures MD, and the active area AA. In some embodiments, the word lines WL 0  and WL 1  are coupled through the vias VG to the gates G or the connection structures MD. For example, with reference to  FIG.  4 C , the word line WL 0  is configured to couple through the via VG to the gate G of the transistor T 1  (which is shown in  FIG.  4 B ), and the word line WL 1  is configured to couple through the via VG to the gate G of the transistor T 2  (which is shown in  FIG.  4 B ). 
     Compared to the layout structure  300 B, the layout structure  400 B further includes a transistor T 2 , a fuse element R 3  and a fuse element R 4 . The transistor T 2  is arranged next to the transistor T 1  in the layout view. The transistor T 2  is arranged apart from the fuse elements R 3  and R 4  in the layout view. 
     The fuse element R 3  is arranged next to the fuse element R 4  in the layout view. In some embodiments, the fuse element R 3  is separated apart from the fuse element R 4  by a width of a fuse conductive segment cf 2 . In some embodiments, the fuse element R 3  and the fuse element R 4  are indicated as one pair of fuse element different from the other pair of fuse element including the fuse elements R 1 -R 2 . For illustration in  FIG.  3 B , both of the element R 3  and the fuse element R 4  are arranged below the transistors T 1  and T 2  in the layout view. Alternatively stated, both of the element R 3  and the fuse element R 4  are arranged apart from the transistors T 1  and T 2  in the layout view. To explain in another way, all of the fuse elements R 1 -R 4  are arranged as an array and are arranged below the transistors T 1  and T 2  in the layout view. For simplicity of illustration,  FIG.  4 B  only shows a portion of the layout structure  400 B. Other elements of the layout structure  400 B are within the contemplated scope of the present disclosure. 
     In some embodiments, the transistor T 2  has the similar function as the transistor T 1 , and is also referred to at least one selection transistors including, for example, a NMOS transistor, for being controlled by the word line WL 1 . In some embodiments, the transistor T 2  corresponds to the transistor T 2  shown in  FIG.  4 A . 
     In some embodiments, the fuse elements R 3  and R 4  have the similar function as the fuse elements R 1  and R 2 . The fuse element R 3  and the fuse element R 4  are also referred to eFuses and are coupled together, for being controlled by a same transistor (e.g., the transistor T 2 ) and also being controlled by respectively the bit lines including, for example, BL 0  and BL 1  (which are shown in  FIG.  4 A ). In some embodiments, the fuse element R 3  corresponds to the fuse R 3  shown in  FIG.  3 A . In other some embodiments, the fuse element R 4  corresponds to the fuse R 4  shown in  FIG.  3 A . In various embodiments, the fuse element R 3  and the fuse element R 4  are coupled through a conductive segment (i.e., a conductive segment CS 2  which is discussed below with reference to  FIGS.  5 A and  5 B ) to the transistor T 2 . 
     With continued reference to  FIG.  4 B , the gates G of the transistor T 2  are coupled to the word line WL 1  through vias VG and are configured to receive data signals transmitted from the word line WL 1 . In some embodiments, with reference to  FIG.  4 B , the word line WL 1  is arranged next to the word line WL 0 , and the word lines WL 0  and WL 1  are arranged above the transistors T 1  and T 2  in the layout view. In various embodiments, the word lines WL 0  and WL 1  are arranged below the transistors T 1  and T 2  in the layout view. In some embodiments, with reference to  FIG.  4 B , the gates G and connection structures MD of the transistor T 2  is partially overlapped with the fuse segments  12  and  22 , and the fuse wall  62  in the layout view. 
     With continued reference to  FIG.  4 B , the fuse element R 3  includes fuse segments  13 ,  23 ,  31  and  41 , a fuse line  53 , and fuse walls  63  and  65 . The fuse element R 3  and the fuse element R 1  share at least one of adjacent fuse segments or adjacent fuse walls, including, for example, the fuse segments  31  and  41 , and the fuse wall  63 . Similar to the fuse elements R 1 -R 2 , all of the fuse segments  13 ,  23 ,  31  and  41 , the fuse line  53 , and the fuse walls  63  and  65  are disposed in the same metal layer where the fuse elements R 1  and R 2  disposed. 
     Similar to the fuse elements R 1 -R 2 , the fuse segments  13 ,  23 ,  31  and  41  are arranged separated from each other, and are arranged on sides of the fuse line  53 . The fuse walls  63  and  65  are arranged separated from each other, and are arranged on sides of the fuse line  53 . In some embodiments, the fuse segments  31  and  13  are referred as a pair of fuse segments, and are arranged on opposite sides of one end of the fuse line  53 . Also, the fuse segments  41  and  23  are referred as a pair of fuse segments, and are arranged on opposite sides of the other end of the fuse line  53 . In addition, the fuse walls  63  and  65  are referred as a pair of fuse walls, and are arranged on opposite sides of middle of the fuse line  53 . 
     In the program operations, in some embodiments, the fuse line  53  is blown, and the fuse walls  63  and  65  blocks residue including, for example, metal or oxide, from the blown fuse line  53 , for avoiding the residue interfering with other component of the eFuse cell including, for example, the fuse element R 1 . 
     In some embodiments, the fuse element R 3  is coupled through vias V 1  to the bit line BL 0  (which is shown in  FIG.  4 A ) which is disposed in the same metal layer where the bit line BL 0  is disposed. In some embodiments, with reference to  FIG.  4 B , vias V 1  are arranged in the fuse segments  13  and  31 , and part of the fuse line  53 , for coupling the fuse element R 3  through the vias V 1  to the bit line BL 0 . Alternatively stated, the transistor T 2  is coupled through the fuse element R 3  to vias V 1 , and to the bit line BL 0 . 
     With continued reference to  FIG.  4 B , the fuse element R 4  includes fuse segments  14 ,  24 ,  32  and  42 , a fuse line  54 , and fuse walls  64  and  66 . The fuse element R 4  and the fuse element R 2  share at least one of adjacent fuse segments or adjacent fuse walls, including, for example, the fuse segments  32  and  42 , and the fuse wall  64 . Similar to the fuse elements R 1 -R 3 , all of the fuse segments  14 ,  24 ,  32  and  42 , the fuse line  54 , and the fuse walls  64  and  66  are disposed in the same metal layer where the fuse elements R 1 -R 3  disposed. With reference to  FIG.  4 B , the fuse conductive segment cf 2  is arranged between the fuse segment  23  and the fuse segment  14 , for coupling the fuse element R 3  and the fuse element R 4  to each other. In some embodiments, the fuse conductive segment cf 2  is arranged directly abuts between the fuse segment  23  and the fuse segment  14 . In some embodiments, the fuse conductive segment cf 2  is disposed in same metal layer where the fuse elements R 1 -R 4  are disposed. Therefore, the fuse segment  23  is coupled through the fuse conductive segment cf 2  to the fuse segment  14 . Alternatively stated, the fuse element R 3  is coupled through the fuse conductive segment cf 2  to the fuse element R 4 . In some embodiments, the conductive segment cf 1  and the conductive segment cf 2  have the same layout structure. 
     Similar to the fuse elements R 1 -R 3 , the fuse segments  14 ,  24 ,  32  and  42  are arranged separated from each other, and are arranged on sides of the fuse line  54 . The fuse walls  64  and  66  are arranged separated from each other, and are arranged on sides of the fuse line  54 . In some embodiments, the fuse segments  32  and  14  are referred as a pair of fuse segments, and are arranged on opposite sides of one end of the fuse line  54 . Also, the fuse segments  42  and  24  are referred as a pair of fuse segments, and are arranged on opposite sides of the other end of the fuse line  54 . In addition, the fuse walls  64  and  66  are referred as a pair of fuse walls, and are arranged on opposite sides of middle of the fuse line  54 . 
     In the program operations, in some embodiments, the fuse line  54  is blown, and the fuse walls  64  and  66  blocks residue including, for example, metal or oxide, from the blown fuse line  54 , for avoiding the residue interfering with other component of the eFuse cell including, for example, the fuse element R 2 . 
     In some embodiments, the fuse element R 4  is coupled through vias V 1  to the bit line BL 1  (which is shown in  FIG.  4 A ) which is disposed in the same metal layer where the bit line BL 0  is disposed. In some embodiments, with reference to  FIG.  4 B , vias V 1  are arranged in the fuse segments  24  and  42 , and part of the fuse line  54 , for coupling the fuse element R 4  through the vias V 1  to the bit line BL 1 . Alternatively stated, the transistor T 2  is coupled through the fuse element R 4  to vias V 1 , and to the bit line BL 1 . 
     Reference is now made to  FIG.  5 A .  FIG.  5 A  is a layout structure  500 A of an eFuse cell corresponding to the eFuse cell  400 A shown in  FIG.  4 A , in accordance with some embodiments of the present disclosure. In some embodiments, the fuse elements R 1 -R 4  and the transistors T 1 -T 2  are the same as those of the layout structure  400 B shown in  FIG.  4 B . Accordingly, they are not further detailed herein. 
       FIG.  5 B  is a schematic diagram  500 B illustrating a cross-section view, viewing at a cross line LINE  2  of one of the connection structures MD of the transistor T 1  shown in  FIG.  5 A , in accordance with some embodiments of the present disclosure. For ease of understanding, the embodiments with respect to  FIG.  5 B  are discussed with reference to  FIG.  5 A . 
     Compared to the layout structure  400 B, the layout structure  500 A further includes the conductive segment CS 1  and the conductive segment CS 2 . 
     The connection structures MD are disposed above and across over the active area AA in the layout view of the layout structure  500 A, as well as shown in  FIG.  5 B . In some embodiments, the vias VD are disposed above and overlap the connection structures MD, which is only shown in  FIG.  5 B  and not shown in  FIG.  5 A  for simplicity. Accordingly, in  FIG.  5 B , the schematic diagram  500 B only illustrates two connection structures MD and the corresponding two vias VD disposed above the active area AA, for simplicity of illustration. However, the present disclosure is not limited to the embodiments of  FIGS.  5 A- 5 B . Various positions or numbers of the vias VG are within the contemplated scope of the present disclosure. 
     The word lines WL 0  and WL 1  are disposed above and across over the gates G and the connection structures MD in the layout view of the layout structure  500 A, as well as shown in  FIG.  5 B . In some embodiments, the word lines WL 0  and WL 1  are formed in a metal-zero (M 0 ) layer, which is disposed above the gates G, the connection structures MD, and the active area AA. In some embodiments, the word lines WL 0  and WL 1  are coupled through the vias VD to the connection structures MD. For example, with reference to  FIG.  5 B , the word line WL 0  is configured to couple through the via VD to the connection structures MD of the transistor T 1  (which is shown in  FIG.  5 A ), and the word line WL 1  is configured to couple through the via VD to the connection structures MD of the transistor T 2  (which is shown in  FIG.  5 A ). 
     For illustration in  FIG.  5 A , the conductive segment CS 1  is disposed above and across over the part of the gates G and connection structures MD of the transistor T 1  in the layout view of the layout structure  500 A, as well as shown in  FIG.  5 B . In some embodiments, the conductive segment CS 1  is formed in a first metal (M 1 ) layer, which is disposed above the M 0  layer. In some embodiments, the conductive segment CS 1  is coupled through the vias V 0  (not shown in  FIG.  5 A ) to the word line WL 0 , and through the vias VD to the connection structures MD of the transistor T 1 . Alternatively stated, the transistor T 1  is coupled through the vias VD to the word line WL 0 , and through the vias V 0  to the conductive segment CS 1 . 
     Furthermore, the conductive segment CS 1  is also disposed above and partially overlapped with the fuse element R 1  in the layout view of the layout structure  500 A, as well as shown in  FIG.  5 B . Specifically, the conductive segment CS 1  is overlapped with the fuse segment  21  of the fuse element R 1 . In some embodiments, the fuse element R 1  is formed in a second metal (M 2 ) layer, which is disposed above the M 1  layer. In some embodiments, the conductive segment CS 1  is coupled through the vias V 1  to fuse element R 1 . Alternatively stated, the fuse element R 1  is coupled through the vias V 1  to the conductive segment CS 1 . 
     Therefore, the fuse element R 1  is coupled through the vias V 1  to the conductive segment CS 1 , through the vias V 0  to the word line WL 0 , and through the vias VD to the connection structures MD of the transistor T 1 . Alternatively stated, the transistor T 1  is coupled through the vias VD to the word line WL 0 , through the vias V 0  to the conductive segment CS 1 , and through the vias V 1  to the fuse element R 1 . Based on the above discussion, since the fuse element R 1  is coupled to the fuse element R 2 , the transistor T 1  is also coupled to the fuse element R 2  by the same path as coupled to the fuse element R 1 . 
     With continued reference to  FIG.  5 A , the conductive segment CS 2  is disposed above and across over the part of the gates G and connection structures MD of the transistor T 2  in the layout view of the layout structure  500 A, as well as shown in  FIG.  5 B . In some embodiments, the conductive segment CS 2  is formed in the M 1  layer. In some embodiments, the conductive segment CS 1  is coupled through the vias V 0  (not shown in  FIG.  5 A ) to the word line WL 1 , and through the vias VD to the connection structures MD of the transistor T 2 . Alternatively stated, the transistor T 2  is coupled through the vias VD to the word line WL 1 , and through the vias V 0  to the conductive segment CS 2 . 
     In addition, the conductive segment CS 2  is also disposed above and partially overlapped with the fuse elements R 2  and R 4  in the layout view of the layout structure  500 A, as well as shown in  FIG.  5 B . Specifically, the conductive segment CS 2  is overlapped with the fuse segments  12  and  32  and part of the fuse line  52  of the fuse element R 2 , and is also overlapped with the fuse segments  14  and  32  and part of the fuse line  54  of the fuse element R 4 . In some embodiments, the fuse elements R 1 -R 4  are formed in the M 2  layer. In some embodiments, the conductive segment CS 2  is coupled through the vias V 1  to fuse element R 4 . Alternatively stated, the fuse element R 4  is coupled through the vias V 1  to the conductive segment CS 2 . 
     Therefore, the fuse element R 4  is coupled through the vias V 1  to the conductive segment CS 2 , through the vias V 0  to the word line WL 1 , and through the vias VD to the connection structures MD of the transistor T 2 . Alternatively stated, the transistor T 2  is coupled through the vias VD to the word line WL 1 , through the vias V 0  to the conductive segment CS 2 , and through the vias V 1  to the fuse element R 4 . Based on the above discussion, since the fuse element R 4  is coupled to the fuse element R 3 , the transistor T 2  is also coupled to the fuse element R 3  by the same path as coupled to the fuse element R 2 . 
     In some embodiments, a length of the conductive segment CS 1  and a length of the conductive segment CS 2  are different. In some embodiments, with continued reference to  FIG.  5 A , the length of the conductive segment CS 1  is shorter than the length of the conductive segment CS 2 . In some other embodiments, a width of the conductive segment CS 1  and a width of the conductive segment CS 2  are different. In some embodiments, with continued reference to  FIG.  5 A , the width of the conductive segment CS 1  is equal to the width of the conductive segment CS 2 . 
     In some embodiments, the conductive segments CS 1  and CS 2  are formed in the same metal layer, for example, with reference to  FIG.  5 B , in the M 1  layer. In some other embodiments, the conductive segments CS 1  and CS 2  are formed in different metal layer, for example, the conductive segment CS 1  formed in the M 1  layer and the conductive segment CS 2  formed in the M 2  layer. In various embodiments, the transistor T 1  is coupled to the fuse elements R 1  and R 2  without the conductive segment CS 1 , and the transistor T 2  is coupled to the fuse elements R 3  and R 4  without the conductive segment CS 2 . 
     In some approaches, an eFuse cell, corresponding to, for example, the eFuse cell  400 A shown in  FIG.  4 A , includes two fuses coupled to two bit lines respectively, and two transistor coupled to two word lines respectively. Each of the transistors is coupled to one fuse, and such eFuse cell is also indicated as 2T2R. The size of a layout structure of the eFuse cell is limited to design rule including, for example, metal spacing rule of fuse and gate pitch of transistor, and it leads to increase the length of the program path (which is discussed below with reference to  FIG.  7   ). The resistance of the program path corresponding to the eFuse cell increases since then, and it would cause poor performance of the eFuse cell. 
     Compared to the above approaches, in the embodiments of the present disclosure, for example with reference to  FIGS.  4 A- 5 B , the eFuse cell which is indicated as 2T4R may reduce the size of the corresponding layout structure by four fuses sharing two transistor correspondingly, and by double word lines arrangement. Accordingly, the configuration of the layout structure is optimized to implement the eFuse cell, and the resistance of the program path corresponding to the eFuse cell in the program operation may be reduced by the reduction of the eFuse cell size, and the performance of the eFuse cell may be further enhanced. 
     Reference is now made to  FIG.  6 A .  FIG.  6 A  is a circuit schematic diagram of an eFuse cell  600 A corresponding to the eFuse cells including, for example, eFuse cells  220 ,  240 ,  260  and  280  shown in  FIG.  2   , in accordance with some embodiments of the present disclosure. 
     For illustration in  FIG.  6 A , the eFuse cell  600 A includes fuses R 1 -R 8  and transistors T 1 -T 4 . Since four transistors (i.e., the transistors T 1 -T 4 ) coupled to eight fuses (i.e., the fuses R 1 -R 8 ) included in one eFuse cell (i.e., the eFuse cell  600 A), the configuration of such eFuse cell is also indicated as 4T8R. Alternatively stated, for 4T8R as an eFuse cell, four word lines (e.g., WL 0 -WL 3 ) and two bit lines (e.g, BL 0  and BL 1 ) are included in one cell, in order to operate eight bits in the program operation controlled by four word lines and two bit lines. In some embodiments, the fuses R 1 -R 4  and the transistors T 1 -T 2  are the same as those of the eFuse cell  400 A shown in  FIG.  4 A . Accordingly, they are not further detailed herein. 
     Compared to the eFuse cell  400 A, the eFuse cell  600 A further includes the fuse R 5  coupled to the bit line BL 0 , the fuse R 6  coupled to the bit line BL 1 , and the transistor T 3  coupled to the word line WL 2 . In addition, the eFuse cell  600 A further includes the fuse R 7  coupled to the bit line BL 0 , the fuse R 8  coupled to the bit line BL 1 , and the transistor T 4  coupled to the word line WL 3 . In some embodiments, the fuse R 5  corresponds to the eFuse element  261  shown in  FIG.  2   , the fuse R 6  corresponds to the eFuse element  262  shown in  FIG.  2   , and the transistor T 3  corresponds to the transistor element  263  shown in  FIG.  2   . In some embodiments, the fuse R 7  corresponds to the eFuse element  281  shown in  FIG.  2   , the fuse R 8  corresponds to the eFuse element  282  shown in  FIG.  2   , and the transistor T 4  corresponds to the transistor element  283  shown in  FIG.  2   . Alternatively stated, the eFuse cell  600 A illustrates an equivalent circuit of the eFuse cells  220 ,  240 ,  260  and  280 . 
     Similar to the eFuse cell  400 A discussed above, one transistor is coupled to two fuses, for example, the fuses R 5  and R 6  are coupled together, and each of them is coupled to the transistor T 3  which, in some embodiments, is NMOS. The fuses R 7  and R 8  are coupled together, and each of them is coupled to the transistor T 4  which, in some embodiments, is NMOS. Alternatively stated, the transistor T 3  is coupled through the fuse R 5  to the bit line BL 0 , and the transistor T 3  is also coupled through the fuse R 6  to the bit line BL 1 . In addition, the transistor T 3  is coupled to the word line WL 2 . The transistor T 4  is coupled through the fuse R 7  to the bit line BL 0 , and the transistor T 4  is also coupled through the fuse R 8  to the bit line BL 1 . In addition, the transistor T 4  is coupled to the word line WL 3 . 
     The above implementation of the eFuse cell  600 A is provided for illustrative purposes. Various implementations of the eFuse cell  600 A are within the contemplated scope of the present disclosure. For example, the transistors T 1 -T 4  are implemented by PMOS. 
     Reference is now made to  FIG.  6 B .  FIG.  6 B  is a layout structure  600 B of an eFuse cell corresponding to the eFuse cell  600 A shown in  FIG.  6 A , in accordance with some embodiments of the present disclosure. For illustration in  FIG.  6 B , the layout structure  600 B includes transistors T 1 -T 4 , fuse elements R 1 -R 8 . In some embodiments, the fuse elements R 1  and R 2  and the transistor T 1  are the same as those of the layout structure  300 B shown in  FIG.  3 B , and are also the same as those of the layout structure  400 B shown in  FIG.  4 B  or the layout structure  500 A shown in  FIG.  5 A . In some embodiments, the fuse elements R 3  and R 4  and the transistor T 2  are the same as those of the layout structure  400 B shown in  FIG.  4 B  or the layout structure  500 A shown in  FIG.  5 A . In some embodiments, the transistors T 1 -T 4  have the same structure as discussed above, and the fuse elements R 1 -R 8  have the same structure as well as discussed above. Accordingly, they are not further detailed herein. 
     Compared to the layout structure  500 A, the layout structure  600 B further includes transistors T 3 -T 4  and fuse elements R 5 -R 8 . The transistors T 3 -T 4  are arranged apart from the transistors T 1 -T 2  and the fuse elements R 1 -R 5  in the layout view. The transistor T 3  is arranged next to the fuse elements R 7 , and the transistor T 4  is arranged next to the fuse elements R 8 . 
     The fuse element R 5  is arranged next to the fuse element R 6  in the layout view. In some embodiments, the fuse element R 5  is separated apart from the fuse element R 6  by a width of a fuse conductive segment (which is discussed above with reference to  FIG.  3 B,  4 B or  5 A ). In some embodiments, the fuse element R 5  and the fuse element R 6  are indicated as one pair of fuse element. For illustration in  FIG.  6 B , the fuse element R 5  is arranged between the fuse element R 3  and the fuse element R 7 , and the fuse element R 6  is arranged between the fuse element R 4  and the fuse element R 8 . In addition, the elements R 5  and R 6  are arranged below the transistors T 1  and T 2 , and are arranged above the transistors T 3  and T 4 , in the layout view. Alternatively stated, both of the element R 5  and the fuse element R 6  are arranged apart from the transistors T 1 -T 4  in the layout view. 
     The fuse element R 7  is arranged next to the fuse element R 8  in the layout view. In some embodiments, the fuse element R 7  is separated apart from the fuse element R 8  by a width of a fuse conductive segment (which is discussed above with reference to  FIG.  3 B,  4 B or  5 A ). In some embodiments, the fuse element R 7  and the fuse element R 8  are indicated as one pair of fuse element. For illustration in  FIG.  6 B , the fuse element R 7  is arranged next to the transistor T 3 , and the fuse element R 8  is arranged next to the transistor T 4 . In addition, the elements R 5  and R 6  are arranged below the transistors T 1  and T 2 , and are arranged above the transistors T 3  and T 4 , in the layout view. Alternatively stated, both of the element R 5  and the fuse element R 6  are arranged apart from the transistors T 1 -T 4  in the layout view. To explain in another way, all of the fuse elements R 1 -R 8  are arranged as an array and are arranged surrounded by the transistors T 1 -T 4  in the layout view. For simplicity of illustration,  FIG.  6 B  only shows a portion of the layout structure  600 B. Other elements of the layout structure  600 B are within the contemplated scope of the present disclosure. 
     In some embodiments, with reference is to  FIG.  6 B , the layout structure  600 B is symmetrical with respect to the line A, except for some vias VG disposed in the word lines W 10 -WL 3 . 
     In some approaches, an eFuse cell, corresponding to, for example, the eFuse cell  600 A shown in  FIG.  6 A , includes four fuses coupled to four bit lines respectively, and four transistor coupled to four word lines respectively. Each of the transistors is coupled to one fuse, and such eFuse cell is also indicated as 4T4R. As discussed above with reference to other some approaches, the resistance of the eFuse cell in program operation increases, and the performance of the eFuse cell decreases accordingly. 
     Compared to the above approaches, in the embodiments of the present disclosure, for example with reference to  FIGS.  6 A- 6 B , the eFuse cell which is indicated as 4T8R may reduce the size of the corresponding layout structure by eight fuses sharing four transistor correspondingly, and by double word lines arrangement. Furthermore, for one eFuse cell, it may program eight bits at once. Accordingly, the configuration of the layout structure is optimized to implement the eFuse cell, and the resistance of the program path corresponding to the eFuse cell in the program operation may be reduced, and the performance of the eFuse cell may be further enhanced. 
     Reference is now made to  FIG.  7   .  FIG.  7    is a schematic diagram of a circuit path for an eFuse cell corresponding to at least one of the eFuse cells shown in  FIG.  2   , in accordance with some embodiments of the present disclosure. For illustration in  FIG.  7   , the program path for a eFuse cell including, for example, the eFuse cell  300 A shown in  FIG.  3 A , the eFuse cell  400 A shown in  FIG.  4 A  or the eFuse cell  600 A shown in  FIG.  6 A . The program path is illustrated as a physical layout in the left side of  FIG.  7    and also as represented by an equivalent circuit path in the right side of  FIG.  7   . The program path as the physical layout corresponds to the program path as the equivalent circuit path with the same reference numbers for illustration. 
     For illustration in  FIG.  7   , the program path extends between a power supply VQPS to a ground. A resistor RVQPS is coupled between the power supply VQPS and a power switch P 1  which, in some embodiments, is a PMOS switch, and the resistor RVQPS is associated with the connection of the power supply VQPS to the power switch transistor P 1 . A voltage VDDQ (which is also shown in  FIG.  1   ) is provided at the drain of the PMOS power switch transistor P 1 . 
     The program path further extends to a program selection transistor P 2  which, in some embodiments, is a PMOS, along the Y-direction. In some embodiments, the program selection transistor P 2  corresponds to the read selection unit  120  in  FIG.  1   . The resistance of the program path between the program selection transistor P 2  and the power switch P 1  is identified as RVQ_YPASS, and is indicated as a resistor RVQ_YPASS as well. 
     The program path further extends from the program selection transistor P 2  to the eFuse cell and the resistance between thereof is identified as Rdrop. The resistance of the eFuse cell is identified as Rfuse. Furthermore, the program path extends from the eFuse cell to a program transistor (e.g., at least one of the transistors T 1 -T 4  shown in  FIGS.  6 A- 6 B ), and the resistance between thereof is identified as Rdrain. The program path further extends through a selection transistor P 3  which, in some embodiments, is a NMOS, to ground, and the resistance between thereof is identified as Rvss. 
     The table below compares parameters for a 5 nm generation when using a 1T1R layout structure for each of eFuse cells (which is indicated as 1T1R in the table) and when using the improved 1T2R layout structure for each of eFuse cells (which is indicated as 1T2R in the table), in accordance with some embodiments of the present disclosure, described above in connection with  FIGS.  3 A- 6 B . 
     
       
         
           
               
               
               
               
             
               
                   
               
               
                   
                 Parameter (ohms) 
                 1T1R 
                 1T2R 
               
               
                   
               
             
            
               
                   
                 RVQ_YPASS 
                  41.95 
                  30.83 
               
               
                   
                 Rdrop 
                  62.06 
                  42.31 
               
               
                   
                 Total 
                 235.55 
                 206.68 
               
               
                   
               
            
           
         
       
     
     In some embodiments, the resistance RVQ_YPASS is reduced from about 41.95 ohm to about 30.83 ohm, and the resistance Rdrop is reduced from about 62.06 ohm to about 42.31 ohm, by the 1T2R layout structure. The overall resistance of the program path is reduced from about 235.55 ohm to about 206.68 ohm, by the 1T2R layout structure. Accordingly, during the program operation, the resistance of the eFuse cell is reduced about 15%-30%, and a current (not shown) is increased about 10%-20%. 
       FIG.  8 A  is a flow chart of a method  800 A for generating an integrated circuit (IC) layout diagram including an eFuse cell including, for example, the layout structure  300 B shown in  FIG.  3 B , the layout structure  400 B shown in  FIG.  4 B , the layout structure  500 A shown in  FIG.  5 A , or the layout structure  600 B shown in  FIG.  6 B , in accordance with some embodiments of the present disclosure. For illustration in  FIG.  8 A , the method  800 A includes operations S 810   a , S 820   a , S 830   a  and S 840   a . Following illustrations of the method  800 A in  FIG.  8 A  with reference to the eFuse cell and the layout structure thereof in  FIGS.  3 A- 6 B  include exemplary operations. However, the operations in  FIG.  8 A  are not necessarily performed in the order shown. Alternatively stated, operations may be added, replaced, changed order, and/or eliminated as appropriate, in accordance with the spirit and scope of various embodiments of the present disclosure. 
     In operation S 810   a , a first fuse element formed in a first conductive layer is arranged. In some embodiments, the first fuse element corresponds to the eFuse element including, for example, the eFuse element  221  shown in  FIG.  2   , the eFuse element R 1  shown in  FIGS.  3 A- 6 B . In some embodiments, the first conductive layer corresponds to the M 2  layer discussed with reference to  FIGS.  5 A- 5 B . 
     In operation S 820   a , a second fuse element formed in the first conductive layer is arranged, and the second fuse element coupled to the first fuse element is arranged. In some embodiments, the second fuse element corresponds to the eFuse element including, for example, the eFuse element  222  shown in  FIG.  2   , the eFuse element R 2  shown in  FIGS.  3 A- 6 B . 
     In some embodiments, at least one of the operations S 810   a  or the operation S 820   a  further includes other operations as the following. A fuse line formed in the first conductive layer is arranged. A pair of fuse segments disposed on opposite sides of the fuse line formed in the first conductive layer is arranged. A fuse conductive segment disposed between one of the pair of fuse segments and the other fuse element (e.g., the second fuse element if the first fuse element is arranged in such operation) is arranged, to couple one of the pair of fuse segments to the other fuse element (e.g., the second fuse element). 
     In some embodiments, the fuse line corresponds to the fuse line including, for example, the fuse line  51  shown in  FIGS.  3 B,  4 B,  5 A and  6 B . In some embodiments, the pair of fuse segments corresponds to the fuse segments including, for example, the fuse segments  11  and  31  shown in  FIGS.  3 B,  4 B,  5 A and  6 B . In some embodiments, the fuse conductive segment corresponds to the fuse conductive segment including, for example, the fuse conductive segment cf 1  shown in  FIGS.  3 B,  4 B,  5 A and  6 B . 
     In operation S 830   a , a transistor formed in a second conductive layer disposed below the first conductive layer is arranged, to couple through the first fuse element to a first data line for receiving a first data voltage, and to couple through the second fuse element to a second data line for receiving a second data voltage. In some embodiments, the transistor corresponds to the transistor including, for example, the transistor element  223  shown in  FIG.  2   , the transistor T 1  shown in  FIGS.  3 A- 6 B . In some embodiments, the second conductive layer corresponds to the active area AA discussed with reference to  FIGS.  5 A- 5 B . In some embodiments, the first data line corresponds to the bit line BL 0  shown in  FIGS.  2 - 6 B , and the second data line corresponds to the bit line BL 1  shown in  FIGS.  2 - 6 B . 
     In operation S 840   a , the IC layout diagram including the first fuse element, the second fuse element, and the transistor is generated. In some embodiments, the IC layout diagram corresponds to the layout diagram including, for example, the layout structure  300 B shown in  FIG.  3 B , the layout structure  400 B shown in  FIG.  4 B , the layout structure  500 A shown in  FIG.  5 A , and the layout structure  600 B shown in  FIG.  6 B . In some embodiments, the integrated circuit including the eFuse cell, as discussed above, is fabricated based on the IC layout diagram generated in operation S 840   a.    
       FIG.  8 B  is a flow chart of a method  800 B for fabricating an integrated circuit (IC) including an eFuse cell including, for example, the eFuse cell  300 A shown in  FIG.  3 A , the eFuse cell  400 A shown in  FIG.  4 A  or the eFuse cell  600 A shown in  FIG.  6 A , in accordance with some embodiments of the present disclosure. For illustration in  FIG.  8 B , the method  800 B includes operations S 810   b , S 820   b , S 830   b  and S 840   b.    
     With reference to  FIG.  8 B , in operation S 810   b , a first fuse element is formed in a first conductive layer. In some embodiments, the first fuse element corresponds to the eFuse element including, for example, the eFuse element  221  shown in  FIG.  2   , or the eFuse element R 1  shown in  FIG.  3 A,  4 A , or  6 A. In some embodiments, the first conductive layer corresponds to the M 2  layer as discussed above with reference to  FIGS.  5 A- 5 B . 
     In operation S 820   b , a second fuse element that is coupled to the first fuse element is formed in the first conductive layer. In some embodiments, the second fuse element corresponds to the eFuse element including, for example, the eFuse element  222  shown in  FIG.  2   , or the eFuse element R 2  shown in  FIG.  3 A,  4 A or  6 A . 
     In some embodiments, at least one of the operation S 810   b  or the operation S 820   b  includes operations as follows. A fuse line is formed in the first conductive layer. A pair of fuse segments that are disposed on opposite sides of the fuse line are formed in the first conductive layer. A fuse conductive segment that is disposed between one of the pair of fuse segments and the other fuse element (e.g., the second fuse element if the first fuse element is formed in such operation) is formed. The fuse conductive segment is coupled through one of the pair of fuse segments to the other fuse element (e.g., the second fuse element). 
     In operation S 830   b , a transistor is formed in a second conductive layer that is disposed below the first conductive layer. In some embodiments, the transistor corresponds to the transistor including, for example, the transistor element  223  shown in  FIG.  2   , the transistor T 1  shown in  FIG.  3 A,  4 A , or  6 A. In some embodiments, the second conductive layer corresponds to the active area AA discussed with reference to  FIGS.  5 A- 5 B . 
     In operation S 840   b , the transistor is coupled through the first fuse element to a first data line for receiving a first data voltage, and the transistor is coupled through the second fuse element to a second data line for receiving a second data voltage. In some embodiments, the first data line corresponds to the bit line BL 0  shown in  FIG.  2 ,  3 A,  4 A , or  6 A, and the second data line corresponds to the bit line BL 1  shown in  FIG.  2 ,  3 A,  4 A,  6 A . 
     Based on the above operations, the IC including the first fuse element, the second fuse element, and the transistor is generated. In some embodiments, the IC corresponds to a device including, for example, eFuse cell  300 A shown in  FIG.  3 A , the eFuse cell  400 A shown in  FIG.  4 A  or the eFuse cell  600 A shown in  FIG.  6 A . 
     Following illustrations of the method  800 B in  FIG.  8 B  with reference to the eFuse cell and the layout structure thereof in  FIGS.  3 A- 6 B  include exemplary operations. However, the operations in  FIG.  8 B  are not necessarily performed in the order shown. Alternatively stated, operations may be added, replaced, changed order, and/or eliminated as appropriate, in accordance with the spirit and scope of various embodiments of the present disclosure. 
     Reference is now made to  FIG.  9   .  FIG.  9    is a block diagram of electronic design automation (EDA) system  900  for designing the integrated circuit layout design, in accordance with some embodiments of the present disclosure. EDA system  900  is configured to implement one or more operations of the method  800 A disclosed in  FIG.  8 A  or the method  800 B disclosed in  FIG.  8 B , and further explained in conjunction with  FIGS.  3 A- 6 B . In some embodiments, EDA system  900  includes an APR system. 
     In some embodiments, EDA system  900  is a general purpose computing device including a hardware processor  920  and a non-transitory, computer-readable storage medium  960 . Storage medium  960 , amongst other things, is encoded with, i.e., stores, computer program code (instructions)  961 , i.e., a set of executable instructions. Execution of computer program code (instructions)  961  by hardware processor  920  represents (at least in part) an EDA tool which implements a portion or all of, e.g., the method  800 A or  800 B. 
     The processor  920  is electrically coupled to computer-readable storage medium  960  via a bus  950 . The processor  920  is also electrically coupled to an I/O interface  910  and a fabrication tool  970  by bus  950 . A network interface  930  is also electrically connected to processor  920  via bus  950 . Network interface  930  is connected to a network  940 , so that processor  920  and computer-readable storage medium  960  are capable of connecting to external elements via network  940 . The processor  920  is configured to execute computer program code  961  encoded in computer-readable storage medium  960  in order to cause EDA system  900  to be usable for performing a portion or all of the noted processes and/or methods. In one or more embodiments, processor  920  is a central processing unit (CPU), a multi-processor, a distributed processing system, an application specific integrated circuit (ASIC), and/or a suitable processing unit. 
     In one or more embodiments, computer-readable storage medium  960  is an electronic, magnetic, optical, electromagnetic, infrared, and/or a semiconductor system (or apparatus or device). For example, computer-readable storage medium  960  includes a semiconductor or solid-state memory, a magnetic tape, a removable computer diskette, a random access memory (RAM), a read-only memory (ROM), a rigid magnetic disk, and/or an optical disk. In one or more embodiments using optical disks, computer-readable storage medium  960  includes a compact disk-read only memory (CD-ROM), a compact disk-read/write (CD-R/W), and/or a digital video disc (DVD). 
     In one or more embodiments, storage medium  960  stores computer program code  961  configured to cause EDA system  900  (where such execution represents (at least in part) the EDA tool) to be usable for performing a portion or all of the noted processes and/or methods. In one or more embodiments, storage medium  960  also stores information which facilitates performing a portion or all of the noted processes and/or methods. In one or more embodiments, storage medium  960  stores library  962  of standard cells including such standard cells as disclosed herein, for example, an eFuse cell including transistor T 1  discussed above with respect to  FIGS.  3 A- 3 B , or an eFuse cell including transistors T 1 -T 2  discussed above with respect to  FIGS.  4 A- 5 B , or an eFuse cell including transistors T 1 -T 4  discussed above with respect to  FIGS.  6 A- 6 B . 
     EDA system  900  includes I/O interface  910 . I/O interface  910  is coupled to external circuitry. In one or more embodiments, I/O interface  910  includes a keyboard, keypad, mouse, trackball, trackpad, touchscreen, and/or cursor direction keys for communicating information and commands to processor  920 . 
     EDA system  900  also includes network interface  930  coupled to processor  920 . Network interface  930  allows EDA system  900  to communicate with network  940 , to which one or more other computer systems are connected. Network interface  930  includes wireless network interfaces such as BLUETOOTH, WIFI, WIMAX, GPRS, or WCDMA; or wired network interfaces such as ETHERNET, USB, or IEEE-1364. In one or more embodiments, a portion or all of noted processes and/or methods, is implemented in two or more EDA systems  900 . 
     EDA system  900  also includes the fabrication tool  970  coupled to the processor  920 . The fabrication tool  970  is configured to fabricate integrated circuits, including, for example, the memory circuit  100  illustrated in  FIG.  1   , based on the design files processed by the processor  920  and/or the IC layout designs as discussed above. 
     EDA system  900  is configured to receive information through I/O interface  910 . The information received through I/O interface  910  includes one or more of instructions, data, design rules, libraries of standard cells, and/or other parameters for processing by processor  920 . The information is transferred to processor  920  via bus  950 . EDA system  900  is configured to receive information related to a UI through I/O interface  910 . The information is stored in computer-readable medium  960  as user interface (UI)  963 . 
     In some embodiments, a portion or all of the noted processes and/or methods is implemented as a standalone software application for execution by a processor. In some embodiments, a portion or all of the noted processes and/or methods is implemented as a software application that is a part of an additional software application. In some embodiments, a portion or all of the noted processes and/or methods is implemented as a plug-in to a software application. In some embodiments, at least one of the noted processes and/or methods is implemented as a software application that is a portion of an EDA tool. In some embodiments, a portion or all of the noted processes and/or methods is implemented as a software application that is used by EDA system  900 . In some embodiments, a layout diagram which includes standard cells is generated using a tool such as VIRTUOSO® available from CADENCE DESIGN SYSTEMS, Inc., or another suitable layout generating tool. 
     In some embodiments, the processes are realized as functions of a program stored in a non-transitory computer readable recording medium. Examples of a non-transitory computer readable recording medium include, but are not limited to, external/removable and/or internal/built-in storage or memory unit, for example, one or more of an optical disk, such as a DVD, a magnetic disk, such as a hard disk, a semiconductor memory, such as a ROM, a RAM, a memory card, and the like. 
       FIG.  10    is a block diagram of IC manufacturing system  1000 , and an IC manufacturing flow associated therewith, in accordance with some embodiments. In some embodiments, based on a layout diagram, at least one of (A) one or more semiconductor masks or (B) at least one component in a layer of a semiconductor integrated circuit is fabricated using IC manufacturing system  1000 . 
     In  FIG.  10   , IC manufacturing system  1000  includes entities, such as a design house  1020 , a mask house  1030 , and an IC manufacturer/fabricator (“fab”)  1050 , that interact with one another in the design, development, and manufacturing cycles and/or services related to manufacturing an IC device  1060 . The entities in IC manufacturing system  1000  are connected by a communications network. In some embodiments, the communications network is a single network. In some embodiments, the communications network is a variety of different networks, such as an intranet and the Internet. The communications network includes wired and/or wireless communication channels. Each entity interacts with one or more of the other entities and provides services to and/or receives services from one or more of the other entities. In some embodiments, two or more of design house  1020 , mask house  1030 , and IC fab  1050  is owned by a single larger company. In some embodiments, two or more of design house  1020 , mask house  1030 , and IC fab  1050  coexist in a common facility and use common resources. 
     Design house (or design team)  1020  generates an IC design layout diagram  1022 . IC design layout diagram  1022  includes various geometrical patterns, for example, an layout structured depicted in  FIG.  3 B ,  FIG.  4 B ,  FIG.  5 A  and/or  FIG.  6 A , designed for an IC device  1060 , for example, memory circuit  100 , eFuse cell  300 A,  400 A and  600 A, discussed above with respect to  FIG.  1   ,  FIG.  3 A ,  FIG.  4 A  and/or  FIG.  6 A . The geometrical patterns correspond to patterns of metal, oxide, or semiconductor layers that make up the various components of IC device  1060  to be fabricated. The various layers combine to form various IC features. For example, a portion of IC design layout diagram  1022  includes various IC features, such as an active region, gate electrode, source and drain, conductive segments or vias of an interlayer interconnection, to be formed in a semiconductor substrate (such as a silicon wafer) and various material layers disposed on the semiconductor substrate. Design house  1020  implements a proper design procedure to form IC design layout diagram  1022 . The design procedure includes one or more of logic design, physical design or place and route. IC design layout diagram  1022  is presented in one or more data files having information of the geometrical patterns. For example, IC design layout diagram  1022  can be expressed in a GDSII file format or DFII file format. 
     Mask house  1030  includes mask data preparation  1032  and mask fabrication  1044 . Mask house  1030  uses IC design layout diagram  1022  to manufacture one or more masks  1045  to be used for fabricating the various layers of IC device  1060  according to IC design layout diagram  1022 . Mask house  1030  performs mask data preparation  1032 , where IC design layout diagram  1022  is translated into a representative data file (“RDF”). Mask data preparation  1032  provides the RDF to mask fabrication  1044 . Mask fabrication  1044  includes a mask writer. A mask writer converts the RDF to an image on a substrate, such as a mask (reticle)  1045  or a semiconductor wafer  1053 . The IC design layout diagram  1022  is manipulated by mask data preparation  1032  to comply with particular characteristics of the mask writer and/or requirements of IC fab  1050 . In  FIG.  10   , data preparation  1032  and mask fabrication  1044  are illustrated as separate elements. In some embodiments, data preparation  1032  and mask fabrication  1044  can be collectively referred to as mask data preparation. 
     In some embodiments, data preparation  1032  includes optical proximity correction (OPC) which uses lithography enhancement techniques to compensate for image errors, such as those that can arise from diffraction, interference, other process effects and the like. OPC adjusts IC design layout diagram  1022 . In some embodiments, data preparation  1032  includes further resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist features, phase-shifting masks, other suitable techniques, and the like or combinations thereof. In some embodiments, inverse lithography technology (ILT) is also used, which treats OPC as an inverse imaging problem. 
     In some embodiments, data preparation  1032  includes a mask rule checker (MRC) that checks the IC design layout diagram  1022  that has undergone processes in OPC with a set of mask creation rules which contain certain geometric and/or connectivity restrictions to ensure sufficient margins, to account for variability in semiconductor manufacturing processes, and the like. In some embodiments, the MRC modifies the IC design layout diagram  1022  to compensate for limitations during mask fabrication  1044 , which may undo part of the modifications performed by OPC in order to meet mask creation rules. 
     In some embodiments, data preparation  1032  includes lithography process checking (LPC) that simulates processing that will be implemented by IC fab  1050  to fabricate IC device  1060 . LPC simulates this processing based on IC design layout diagram  1022  to create a simulated manufactured device, such as IC device  1060 . The processing parameters in LPC simulation can include parameters associated with various processes of the IC manufacturing cycle, parameters associated with tools used for manufacturing the IC, and/or other aspects of the manufacturing process. LPC takes into account various factors, such as aerial image contrast, depth of focus (“DOF”), mask error enhancement factor (“MEEF”), other suitable factors, and the like or combinations thereof. In some embodiments, after a simulated manufactured device has been created by LPC, if the simulated device is not close enough in shape to satisfy design rules, OPC and/or MRC are be repeated to further refine IC design layout diagram  1022 . 
     It should be understood that the above description of data preparation  1032  has been simplified for the purposes of clarity. In some embodiments, data preparation  1032  includes additional features such as a logic operation (LOP) to modify the IC design layout diagram  1022  according to manufacturing rules. Additionally, the processes applied to IC design layout diagram  1022  during data preparation  1032  may be executed in a variety of different orders. 
     After data preparation  1032  and during mask fabrication  1044 , a mask  1045  or a group of masks  1045  are fabricated based on the modified IC design layout diagram  1022 . In some embodiments, mask fabrication  1044  includes performing one or more lithographic exposures based on IC design layout diagram  1022 . In some embodiments, an electron-beam (e-beam) or a mechanism of multiple e-beams is used to form a pattern on a mask (photomask or reticle)  1045  based on the modified IC design layout diagram  1022 . Mask  1045  can be formed in various technologies. In some embodiments, mask  1045  is formed using binary technology. In some embodiments, a mask pattern includes opaque regions and transparent regions. A radiation beam, such as an ultraviolet (UV) beam, used to expose the image sensitive material layer (for example, photoresist) which has been coated on a wafer, is blocked by the opaque region and transmits through the transparent regions. In one example, a binary mask version of mask  1045  includes a transparent substrate (for example, fused quartz) and an opaque material (for example, chromium) coated in the opaque regions of the binary mask. In another example, mask  1045  is formed using a phase shift technology. In a phase shift mask (PSM) version of mask  1045 , various features in the pattern formed on the phase shift mask are configured to have proper phase difference to enhance the resolution and imaging quality. In various examples, the phase shift mask can be attenuated PSM or alternating PSM. The mask(s) generated by mask fabrication  1044  is used in a variety of processes. For example, such a mask(s) is used in an ion implantation process to form various doped regions in semiconductor wafer  1053 , in an etching process to form various etching regions in semiconductor wafer  1053 , and/or in other suitable processes. 
     IC fab  1050  includes wafer fabrication  1052 . IC fab  1050  is an IC fabrication business that includes one or more manufacturing facilities for the fabrication of a variety of different IC products. In some embodiments, IC Fab  1050  is a semiconductor foundry. For example, there may be a manufacturing facility for the front end fabrication of a plurality of IC products (front-end-of-line (FEOL) fabrication), while a second manufacturing facility may provide the back end fabrication for the interconnection and packaging of the IC products (back-end-of-line (BEOL) fabrication), and a third manufacturing facility may provide other services for the foundry business. 
     IC fab  1050  uses mask(s)  1045  fabricated by mask house  1030  to fabricate IC device  1060 . Thus, IC fab  1050  at least indirectly uses IC design layout diagram  1022  to fabricate IC device  1060 . In some embodiments, semiconductor wafer  1053  is fabricated by IC fab  1050  using mask(s)  1045  to form IC device  1060 . In some embodiments, the IC fabrication includes performing one or more lithographic exposures based at least indirectly on IC design layout diagram  1022 . Semiconductor wafer  1053  includes a silicon substrate or other proper substrate having material layers formed thereon. Semiconductor wafer  1053  further includes one or more of various doped regions, dielectric features, multilevel interconnects, and the like (formed at subsequent manufacturing steps). 
     Moreover, various circuits or devices to implement the transistors in the aforementioned embodiments are within the contemplated scope of the present disclosure. 
     Furthermore, in some embodiments of this document, at least one of the transistors is implemented with at least one metal oxide semiconductor (MOS) transistor, at least one bipolar junction transistor (BJT), etc., or the combination thereof. Various circuits or devices to implement the transistors in the aforementioned embodiments are within the contemplated scope of the present disclosure. 
     In some embodiments, an integrated circuit is disclosed. The integrated circuit includes a transistor, a first fuse element and a second fuse element. The transistor is formed in a first conductive layer. The first fuse element is formed in a second conductive layer and coupled between the transistor and a first data line. The second fuse element is formed in the second conductive layer and coupled between the transistor and a second data line. The first fuse element and the second fuse element are disposed at a same side of the transistor. 
     In some embodiments, the second conductive layer is disposed above the first conductive layer, and the first fuse element and the second fuse element are disposed above the first conductive layer. 
     In some embodiments, the integrated circuit further includes a conductive segment. The conductive segment is formed in a third conductive layer disposed between the first conductive layer and the second conductive layer. The conductive segment, part of the first fuse element and part of the transistor are overlapped in a layout view, and the first fuse element is coupled through the conductive segment to the transistor. 
     In some embodiments, the first fuse element includes a fuse line and a pair of fuse segments. The pair of fuse segments are disposed on opposite sides of the fuse line. One of the pair of fuse segments is coupled through a fuse conductive segment formed in the second conductive layer to the second fuse element. 
     In some embodiments, the first fuse element includes a first fuse line and a pair of first fuse segments. The pair of first fuse segments is disposed on opposite sides of an end of the first fuse line. The second fuse element includes a second fuse line and a pair of second fuse segments. The pair of second fuse segments disposed on opposite sides of an end of the second fuse line. One of the pair of the first fuse segments is coupled through a fuse conductive segment formed in the second conductive layer to one of the pair of second fuse segments. 
     In some embodiments, one of the pair of the first fuse segments, which is coupled to one of the pair of second fuse segments, is further coupled to the transistor through a conductive segment formed in a third conductive layer disposed between the first conductive layer and the second conductive layer. 
     In some embodiments, an integrated circuit is disclosed. The integrated circuit includes a plurality of electrical fuse cells. The plurality of electrical fuse cells include a first conductive segment, a first transistor and a pair of first fuse elements. The first transistor is formed in a first conductive layer. The pair of first fuse elements are formed in a second conductive layer and coupled to a pair of data lines. The pair of first fuse elements are coupled together and are coupled through the first conductive segment to the first transistor. The first conductive segment and the pair of first fuse elements are disposed at a same side of the first transistor. 
     In some embodiments, the plurality of electrical fuse cells further include a second transistor, a first program line and a second program line. The second transistor is formed in the first conductive layer and disposed next to the first transistor. The first program line is formed in a third conductive layer disposed between the first conductive layer and the second conductive layer. The first transistor is coupled to the first program line. The second program line is formed in the third conductive layer and disposed next to the first program line. The second transistor is coupled to the second program line. Both of the first program line and the second program line are disposed above or below all of the first transistor, the second transistor and the pair of first fuse elements in a layout view. 
     In some embodiments, the integrated circuit further includes a third conductive layer. The third conductive layer is disposed between the first conductive layer and the second conductive layer. The first conductive segment is formed in the third conductive layer and is partially overlapped with first transistor and one of the pair of first fuse elements in a layout view. 
     In some embodiments, one of the pair of first fuse elements includes a fuse line, a first pair of fuse segments and a second pair of fuse segments. The first pair of fuse segments are disposed on opposite sides of a first end of the fuse line. The second pair of fuse segments are disposed on opposite sides of a second end of the fuse line. The first end and the second end are opposite from each other. One of the first pair of fuse segments is overlapped with the first conductive segment in a layout view. The second pair of fuse segments and part of the fuse line are overlapped. 
     In some embodiments, one of the pair of first fuse elements includes a first fuse line and a pair of first fuse segments. The pair of first fuse segments are disposed on opposite sides of an end of the first fuse line. The other one of the pair of first fuse elements includes a second fuse line and a pair of second fuse segments. The pair of second fuse segments disposed on opposite sides of an end of the second fuse line. One of the pair of first fuse segments is coupled through a fuse conductive segment formed in the second conductive layer to one of the pair of second fuse segments, and is overlapped with the first conductive segment in a layout view. 
     In some embodiments, the integrated circuit further includes a first program line and a second program line. The first program line is formed in a third conductive layer disposed between the first conductive layer and the second conductive layer. The first transistor is coupled to the first program line. The second program line is formed in the third conductive layer and is disposed next to the first program line. Both of the first program line and the second program line are disposed above or below the plurality of electrical fuse cells in a layout view. the plurality of electrical fuse cells further include a second transistor and a pair of second fuse elements. The second transistor is formed in the first conductive layer and is disposed next to the first transistor. The second transistor is coupled to the second program line. The pair of second fuse elements are formed in the second conductive layer and are coupled together by a fuse conductive segment. The pair of first fuse elements are disposed between the pair of second fuse elements and the second transistor in a layout view. The second transistor is coupled through one of the pair of second fuse elements to a first data line of the pair of data lines for receiving a first data signal, and the second transistor is coupled through the other one of the pair of second fuse elements to a second data line of the pair of data lines for receiving a second data signal. 
     In some embodiments, the plurality of electrical fuse cells further include a second conductive segment. The second conductive segment is disposed next to the first conductive segment. The pair of second fuse elements are coupled through the second conductive segment to the second transistor. The first conductive segment and the second conductive segment are formed in a fourth conductive layer disposed between the second conductive layer and the third conductive layer. The second conductive segment and the first conductive segment have different length. 
     In some embodiments, the integrated circuit further includes a third program line and a fourth program line. The third program line is formed in the third conductive layer and is disposed apart from both of the first program line and the second program line. The fourth program line is formed in the third conductive layer and is disposed next to the third program line. Both of the third program line and the fourth program line are disposed above or below the plurality of electrical fuse cells in a layout view. The plurality of electrical fuse cells further include a third transistor, a fourth transistor, a pair of third fuse elements and a pair of fourth fuse elements. The third transistor is formed in the first conductive layer. The third transistor is coupled to the third program line. The fourth transistor is formed in the first conductive layer and is disposed next to the third transistor. The fourth transistor is coupled to the fourth program line. The pair of third fuse elements are formed in the second conductive layer and are coupled together. The pair of second fuse elements are disposed between the pair of first fuse elements and the pair of third fuse elements. The pair of fourth fuse elements are formed in the second conductive layer and are coupled together. The pair of third fuse elements are disposed between the pair of second fuse elements and the pair of fourth fuse elements. The third transistor is coupled through one of the pair of third fuse elements to the first data line for receiving the first data signal, and the second transistor is coupled through the other one of the pair of second fuse elements to the second data line for receiving the second data signal. 
     In some embodiments, an integrated circuit includes a first transistor, a second transistor, a first fuse element, a second fuse element, a third fuse element, and a fourth fuse element. The first transistor is coupled to a first data line. The second transistor is coupled to a second data line. The first fuse element is coupled to the first transistor and disposed at a first side of the first transistor. The second fuse element is coupled to the first transistor and disposed at the first side of the second transistor. The third fuse element is coupled to the second transistor and disposed at the first side of the first fuse element. The fourth fuse element is coupled to the second transistor and disposed at the first side of the second fuse element. 
     In some embodiments, the first fuse element is between the first transistor and the third fuse element. 
     In some embodiments, the second fuse element is between the second transistor and the fourth fuse element. 
     In some embodiments, the first fuse element is disposed at a second side of the third fuse element. 
     In some embodiments, the second fuse element is disposed at a second side of the fourth fuse element. 
     In some embodiments, the second transistor is arranged next to the first transistor in a layout view. 
     The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.