Patent Publication Number: US-2021183902-A1

Title: Thin film transistor array

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     The present application is a continuation of International Application No. PCT/JP2019/033100, filed Aug. 23, 2019, which is based upon and claims the benefits of priority to Japanese Application No. 2018-161978, filed Aug. 30, 2018. The entire contents of all of the above applications are incorporated herein by reference. 
     BACKGROUND OF THE INVENTION 
     Field of the Invention 
     The present invention relates to thin film transistor arrays. The thin film transistor arrays according to the present invention can be used in display devices. Furthermore, the thin film transistor arrays according to the present invention are suitable for low power consumption applications. 
     Discussion of the Background 
     Transistors using semiconductor substrates, or amorphous silicon (a-Si) or polysilicon (poly-Si) thin film transistor (TFT) arrays using glass substrates based on integrated circuit technology have been produced for application to liquid crystal displays or other displays. TFTs serve as switches. Specifically, when a TFT is turned on by a selected voltage applied to a row wire (gate wire), a signal voltage provided to a column wire (source wire) is written into a pixel electrode connected to the drain electrode. The voltage written is held in a storage capacitor disposed between a capacitor electrode and the drain electrode or the pixel electrode. (In the case of TFT arrays, since the source and the drain are interchangeable depending on the polarity of a write voltage, the names “source” and “drain” cannot be assigned to electrodes based on operations thereof. Therefore, for the sake of convenience, one is described as “source” while the other is described as “drain”. In the present invention, an electrode connected to a wire is termed a source, and one connected to a pixel electrode is termed a drain.) 
     In TFT arrays, there is a phenomenon called gate feedthrough in which a pixel potential changes upon switching of a gate potential from ON to OFF. The pixel potential changes due to a gate-feedthrough voltage Vgf=ΔVg·Cgd/(Cgd+Cs+Cp). Here, ΔVg is an amount of change in the gate potential, Cgd is a gate-drain capacitance, Cs is a storage capacitance (capacitance between the pixel electrode and the capacitor), and Cp is a capacitance due to a display medium. If Cp is large, the storage capacitance Cs can be omitted. If Cp is small, Cs becomes necessary, and if Cp is much smaller than Cs, Cp can be ignored. Conventionally, for the purpose of reducing the gate-feedthrough voltage, a device has been devised to reduce Cgd (Patent Literature (PTL) 1). As shown in  FIG. 21 , the drain electrode is formed in the shape of a line having a constant width with a rounded tip, and the source electrode is formed in a U shape to surround the drain electrode, to make an area Sgd of overlap between the gate electrode and the drain electrode small, making Cgd small. Meanwhile, no importance has been given to gate-source capacitance Cgs. 
     In recent years, electronic paper display devices in which the thin film transistor array and an electrophoretic medium are combined have been developed and show promise as display devices that consume less power than liquid-crystal displays. This is because general liquid-crystal display devices can display data only while being driven and need to be continuously driven to keep the data displayed, whereas electrophoretic electronic paper keeps data displayed thereon even after driving ends and therefore does not need to be continuously driven. 
     Furthermore, the technique of combining electronic paper with radio-frequency identification (RFID), which is an identification technique, to form a display part of a container has been disclosed (PTL 2). By displaying the content stored in the RFID device on a display, the data can visually verified. 
     PTL 1: JP 2014-187093 A 
     PTL 2: JP 2003-233786 A 
     SUMMARY OF THE INVENTION 
     According to an aspect of the present invention, a thin film transistor array includes an insulating substrate, column wirings formed on the insulating substrate, row wirings formed on the insulating substrate and extending perpendicularly to the column wirings, and pixels formed on the insulating substrate at crossing points of the column and row wirings. Each of the pixels includes a pixel electrode and a thin film transistor that includes a gate electrode, a source electrode, a drain electrode, and a semiconductor pattern. The source electrode has a linear shape having a constant width in a plan view, the drain electrode includes a U-shaped portion positioned around the source electrode such that a gap of a predetermined width is formed between the U-shaped portion and the source electrode in the plan view, the semiconductor pattern connects at least the source electrode and the drain electrode such that a channel region is formed, the gate electrode overlaps the channel region via a gate insulating film and includes the channel region in the plan view, and the source electrode is connected to one of the column wirings, the gate electrode is connected to one of the row wirings by a gate connecting wiring, and the drain electrode is connected to the pixel electrode by a drain connecting wiring. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       A more complete appreciation of the invention and many of the attendant advantages thereof will be readily obtained as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings, wherein: 
         FIG. 1  includes plan views and cross-sectional views showing one example of a thin film transistor array according to a first embodiment of the present invention, during production. 
         FIG. 2  is a set of diagrams including plan views and cross-Sectional views showing one example of a thin film transistor array according to a modification, during production. 
         FIG. 3  includes plan views and cross-sectional views showing one example of a thin film transistor array according to a second embodiment of the present invention, during production. 
         FIG. 4  includes plan views and cross-sectional views showing one example of a thin film transistor array according to a modification, during production. 
         FIG. 5  includes plan views and cross-sectional views showing one example of a thin film transistor array according to a third embodiment of the present invention, during production. 
         FIG. 6A  is a plan view showing a U-shaped part, a tip part, a U-shaped region, and an opening region. 
         FIG. 6B  is a plan view showing the drain electrode. 
         FIG. 6C  is a plan view showing the U-shaped part, the tip part, the U-shaped region, and the opening region. 
         FIG. 6D  is a plan view showing the drain electrode. 
         FIG. 6E  is a plan view showing the U-shaped part, the tip part, the U-shaped region, and the opening region. 
         FIG. 6F  is a plan view showing the drain electrode. 
         FIG. 7A  is an enlarged plan view of the thin film transistor shown in  FIG. 1 . 
         FIG. 7B  is an enlarged plan view of a variation of the thin film transistor shown in  FIG. 1 . 
         FIG. 8  is an enlarged plan view of a thin film transistor shown in  FIG. 3 . 
         FIG. 9  is a plan view showing a source electrode and a source connecting wiring. 
         FIG. 10A  includes plan views and cross-sectional views showing one example of a thin film transistor array according to a modification, during production. 
         FIG. 10B  includes plan views and cross-sectional views showing a continuation of a manufacturing process shown in  FIG. 10A . 
         FIG. 10C  includes plan views and cross-sectional views showing a continuation of a manufacturing process shown in  FIG. 10B . 
         FIG. 11A  includes plan views and cross-sectional views showing one example of a thin film transistor array according to a modification, during production. 
         FIG. 11B  includes plan views and cross-sectional views showing a continuation of a manufacturing process shown in  FIG. 11A . 
         FIG. 11C  includes plan views and cross-sectional views showing a continuation of a manufacturing process shown in  FIG. 11B . 
         FIG. 12A  includes plan views and cross-sectional views showing one example of a thin film transistor array according to a modification, during production. 
         FIG. 12B  includes plan views and cross-sectional views showing a continuation of a manufacturing process shown in  FIG. 12A . 
         FIG. 13A  includes plan views and cross-sectional views showing one example of a thin film transistor array according to a variation that is in the middle of production. 
         FIG. 13B  includes plan views and cross-sectional views showing a continuation of a manufacturing process shown in  FIG. 13A . 
         FIG. 14A  includes plan views and cross-sectional views showing one example of a thin film transistor array according to a modification, during production. 
         FIG. 14B  includes plan views and cross-sectional views showing a continuation of a manufacturing process shown in  FIG. 14A . 
         FIG. 14C  includes plan views and cross-sectional views showing a continuation of a manufacturing process shown in  FIG. 14B . 
         FIG. 15A  includes plan views and cross-sectional views showing one example of a thin film transistor array according to a modification, during production. 
         FIG. 15B  includes plan views and cross-sectional views showing a continuation of a manufacturing process shown in  FIG. 15A . 
         FIG. 15C  includes plan views and cross-sectional views showing a continuation of a manufacturing process shown in  FIG. 15B . 
         FIG. 16A  includes plan views and cross-sectional views showing one example of a thin film transistor array according to a modification, during production. 
         FIG. 16B  includes plan views and cross-sectional views showing a continuation of a manufacturing process shown in  FIG. 16A . 
         FIG. 16C  includes plan views and cross-sectional views showing a continuation of a manufacturing process shown in  FIG. 16B . 
         FIG. 17A  includes plan views and cross-sectional views showing one example of a thin film transistor array according to a modification, during production. 
         FIG. 17B  includes plan views and cross-sectional views showing a continuation of a manufacturing process shown in  FIG. 17A . 
         FIG. 17C  includes plan views and cross-sectional views showing a continuation of a manufacturing process shown in  FIG. 17B . 
         FIG. 18  shows calculation of a voltage waveform, an electric current waveform, and an amount of electric power in a column wiring. 
         FIG. 19  shows calculation of a voltage waveform, an electric current waveform, and an amount of electric power in a row wiring. 
         FIG. 20  is a diagram illustrating calculation of a voltage waveform, an electric current waveform, and an amount of electric power in a pixel TFT. 
         FIG. 21  includes a plan view and a cross-sectional view showing one example of a conventional thin film transistor array. 
     
    
    
     DESCRIPTION OF THE EMBODIMENTS 
     The embodiments will now be described with reference to the accompanying drawings, wherein like reference numerals designate corresponding or identical elements throughout the various drawings. 
     Embodiments of the present invention will be described in detail hereinafter with reference to the drawings. Note that in the drawings used in the following, for simplicity of explanation, the scale is not shown accurately. The same or corresponding components in the embodiments and the variations are denoted by the same reference signs, and description thereof will be omitted. 
     First Embodiment 
       FIG. 1  shows a portion of a thin film transistor array according to a first embodiment of the present invention.  FIG. 2  shows a portion of a thin film transistor array according to a modification thereof. In  FIGS. 1 and 2 , (a) is a diagram during production for showing features in an easy-to-understand manner, and (b) is a final drawing. The thin film transistor array shown in  FIGS. 1 and 2  includes a plurality of column wirings  4 L extending in the longitudinal direction (first direction), a plurality of row wirings  2 L extending in the lateral direction (second direction) orthogonal to the plurality of column wirings  4 L, and a plurality of pixels provided corresponding to crossing points of the column wirings  4 L and the row wirings  2 L. 
     Each pixel includes at least a thin film transistor and a pixel electrode  10 . The thin film transistor includes a gate electrode  2 , a source electrode  4 , and a drain electrode  5 . In a plan view, the source electrode  4  is in the shape of a line having a constant width, the drain electrode  5  includes a U-shaped part  5 U in a U shape surrounding the source electrode  4  with a gap having a predetermined width therebetween, and at least a portion of a semiconductor pattern  6  connects the source electrode  4  and the drain electrode  5  to form a channel region  6 C. The U shape is a shape resulting from connecting one tip of one of two parallel straight parts to one tip of the other. The portion connecting the tips (the bottom of the character U) may be straight or may be curved. The gate electrode  2  at least partially overlaps the channel region  6 C via a gate insulating film  3 , the source electrode  4  is connected to the column wiring  4 L, the gate electrode  2  is connected to the row wiring  2 L via a gate connecting wiring  2 C, and the drain electrode  5  is connected to the pixel electrode  10  via at least a drain connecting wiring  5 C. 
     In the case of  FIGS. 1 and 2 , the tip of the source electrode  4  is rounded. Furthermore, the bottom of the U shape of the drain electrode  5  is also rounded. The straight parts of the U shape of the drain electrode  5  are distanced from the straight part of the source electrode  4  by a predetermined channel length, and the round bottom of the U shape of the drain electrode  5  is distanced from the rounded tip portion of the source electrode  4  by the predetermined channel length. With this structure, both side edges and the tip edge of the source electrode  4  can be used to form the channel region  6 C, and the area of the source electrode  4  can be reduced while a channel width W for obtaining a required on-state current is sufficiently secured, and an area Sgs of overlap between the gate electrode and the source electrode can be reduced, leading to a reduction in Cgs. 
     The gate connecting wiring  2 C is narrower than the gate electrode  2  and overlaps neither of one of the drain electrodes  5  nor the drain connecting wiring  5 C. Thus, gate-drain capacitance Cgd can be minimized. 
     As shown in  FIG. 6A , the drain electrode  5  includes a U-shaped part  5 U proximate to the source electrode  4  at a predetermined distance (with a gap having a predetermined width) and two tip parts  5 T extending away from the source electrode  4 . The tip parts  5 T may be rounded. Alternatively, the tip parts  5 T may not be provided. The constant gap portion between the U-shaped part  5 U of the drain electrode  5  and the source electrode  4  is a U-shaped region  6 U of the channel. In  FIG. 6A , the bottom of the U shape of the drain electrode  5  is rounded, is in the shape of a semicircle, and is concentric with the rounded tip of the source electrode  4 , and the distance between the source electrode  4  and the drain electrode  5  (that is, the width of the U-shaped region  6 U of the channel) is constant not only on both sides of the straight part of the source electrode  4 , but also at the tip part of the source electrode  4 . Therefore, this can function effectively as a transistor not only on both sides of the straight part of the source electrode  4 , but also at the tip part of the source electrode  4 . Note that regarding the phrase “the distance between the source electrode  4  and the drain electrode  5  (that is, the width of the U-shaped region  6 U of the channel) is constant”, it is sufficient that the distance be substantially constant; minor design differences or slight process-induced variations are within the scope of the present invention. For example, the tip of the source electrode  4  and the bottom of the U shape of the drain electrode  5  do not need to be perfectly concentric, and the center points thereof may be slightly displaced. Furthermore, the tip of the source electrode  4  and the round bottom of the U shape of the drain electrode  5  do not need to be exactly circular. 
       FIG. 6C  is a variation of  FIG. 6A . As shown in  FIG. 6C , the drain electrode  5  includes a U-shaped part  5 U proximate to the source electrode  4  at a predetermined distance therefrom (with a gap having a predetermined width) and two tip parts  5 T extending away from the source electrode  4 . The tip parts  5 T of the drain electrode  5  may be rounded. Alternatively, the tip parts  5 T may not be provided. The constant gap portion between the U-shaped part  5 U of the drain electrode  5  and the source electrode  4  is a U-shaped region  6 U of the channel. In  FIG. 6C , at least a portion of the bottom of the U shape of the drain electrode  5  that faces the tip of the source electrode  4  is not rounded, the tip of the source electrode  4  is rectangular, and the distance between the source electrode  4  and the drain electrode  5  (that is, the width of the U-shaped region  6 U of the channel) is constant not only on both sides of the straight part of the source electrode  4 , but also on the side of the tip part of the source electrode  4 . Therefore, this can function effectively as a transistor not only on both sides of the straight part of the source electrode  4 , but also at the tip part of the source electrode  4 . Note that regarding the phrase “the distance between the source electrode  4  and the drain electrode  5  (that is, the width of the U-shaped region  6 U of the channel) is constant”, it is sufficient that the distance be substantially constant; minor design differences or slight process-induced variations are within the scope of the present invention. Furthermore, a portion of the bottom of the U shape of the drain electrode  5  that does not face the tip part of the source electrode  4  may be rounded.  FIG. 6E  is a special example of  FIG. 6C . As shown in  FIG. 6E , the drain electrode  5  includes a U-shaped part  5 U proximate to the source electrode  4  at a predetermined distance (with a gap having a predetermined width) and two tip parts  5 T extending away from the source electrode  4 . The tip parts  5 T of the drain electrode  5  may be rounded. Alternatively, the tip parts  5 T may not be provided. The constant gap portion between the U-shaped part  5 U of the drain electrode  5  and the source electrode  4  is a U-shaped region  6 U of the channel. In  FIG. 6E , the bottom of the U shape of the drain electrode  5  is straight at the center, but round on both sides, the tip of the source electrode  4  is rectangular, the bottom edge of the rounded portion of the U shape of the drain electrode  5  matches a vertex of the source electrode  4 , and the distance between the source electrode  4  and the drain electrode  5  (that is, the width of the U-shaped region  6 U of the channel) is constant not only between both sides of the straight part of the source electrode  4  and the straight parts of the drain electrode  5 , but also between the at the tip surface of the source electrode  4  and the straight part of the bottom of the U shape of the drain electrode  5  and between two vertices of the tip of the source electrode  4  and two rounded parts of the U shape of the drain electrode  5 . Therefore, transistor functions are effective not only on both sides of the straight part of the source electrode  4 , but also on at the tip part of the source electrode  4 , and furthermore at the vertices of the source electrode  4 . Note that regarding the phrase “the distance between the source electrode  4  and the drain electrode  5  (that is, the width of the U-shaped region  6 U of the channel) is constant”, it is sufficient that the distance be substantially constant; minor design differences or slight process-induced variations are within the scope of the present invention. 
     In  FIGS. 6A, 6C, and 6E , with respect to a straight line separating the U-shaped part  5 U and the tip parts  5 T of the drain electrode  5  as a boundary, the area on the U-shaped part  5 U side is called a U-shaped region of the TFT, and the area on the side on which the U-shaped part  5 U is open and the tip parts  5 T are included is called an opening region of the TFT. 
     As shown in  FIGS. 6B, 6D, and 6F , the outer edge of the drain electrode  5  is an outer edge  5 UO of the U-shaped part  5 U, and the inner edge of the drain electrode  5  is an inner edge  5 UI of the U-shaped part  5 U. 
     In  FIGS. 1 and 2 , the contour of the gate electrode  2  is smaller than the outer edge  5 UO of the drain electrode  5 , but is larger than the inner edge  5 UI of the drain electrode  5  in the U-shaped region in the plan view, as shown in  FIG. 7A . In other words, at least a portion of the outline (the profile in plan view) of the gate electrode  2  is formed so as to overlap the U-shaped part  5 U of the drain electrode  5  in the U-shaped region in the plan view. Since the contour of the gate electrode  2  is smaller than the outer edge  5 UO of the drain electrode  5 , the area Sgd of overlap between the gate electrode and the drain electrode is small, and the gate-drain capacitance Cgd is also small. Furthermore, since the contour of the gate electrode  2  is larger than the inner edge  5 UI of the drain electrode  5 , the current in the channel region  6 C can be reliably controlled. 
     In (a) in  FIGS. 1 and 2 , the outer profile of the gate electrode  2  is smaller than the contour of the semiconductor pattern  6  in the U-shaped region, the gate electrode  2  protrudes from the opening region, and the semiconductor pattern  6  does not protrude from the opening region in plan view, as shown in  FIG. 7A . In other words, at least a portion of the outline of the gate electrode  2  overlaps the semiconductor pattern  6  in the U-shaped region and is formed outside the opening of the U-shaped part  5 U, and at least a portion of the outline of the semiconductor pattern  6  is formed inside the opening of the U-shaped part  5 U in plan view. As a result of the outline of the gate electrode  2  being smaller than the contour of the semiconductor pattern  6  in the U-shaped region, the area Sgd of overlap between the gate electrode and the drain electrode is small, and Cgd is also small. Furthermore, the gate electrode  2  protrudes from the opening region and the semiconductor pattern  6  does not protrude from the opening region, and thus the electric current in the channel region  6 C can be reliably controlled. Note that a portion of the gate electrode  2  that protrudes from the opening region may be rounded as shown in the upper part of  FIG. 7A  or may be straight as shown in the lower part of  FIG. 7A . The channel region  6 C matches the U-shaped region  6 U of the channel. In this case, Vg-Id characteristics may slightly change due to the effects of a parasitic transistor caused by the edge of the semiconductor pattern  6 , but this causes no problem because driving of electronic paper does not require precise electric current control. 
     Alternatively, as shown in  FIG. 7B , the contour of the gate electrode  2  may be smaller than the contour of the semiconductor pattern  6  in the U-shaped region, the gate electrode  2  may protrude from the opening region, and the semiconductor pattern  6  may protrude from the opening region, but a portion of the contour of the semiconductor pattern  6  may be formed inside the contour of the gate electrode  2  in the opening region in plan view. In other words, at least a portion of the outline of the gate electrode  2  overlaps the semiconductor pattern  6  in the U-shaped region and is formed outside the opening of the U-shaped part  5 U of the drain electrode in the opening region, and at least a portion of the outline of the semiconductor pattern  6  is formed outside of the opening of the U-shaped part  5 U and is formed inside the contour of the gate electrode  2  in plan view. As a result of the outline of the gate electrode  2  being smaller than the contour of the semiconductor pattern  6  in the U-shaped region, the area Sgd of overlap between the gate electrode and the drain electrode is small, and Cgd is also small. Furthermore, the gate electrode  2  protrudes from the opening region, and the semiconductor pattern  6  protrudes from the opening region, but is formed inside the contour of the gate electrode  2 , and thus the electric current in the channel region  6 C can be reliably controlled. Note that a portion of the gate electrode  2  that protrudes from the opening region may be round as shown in the upper part of  FIG. 7B  or may be straight as shown in the lower part of  FIG. 7B . The channel region  6 C is made up of two regions, namely, a main part including the U-shaped region  6 U of the channel and an auxiliary part slightly protruding from the opening side. 
     In (a) in  FIG. 1 , the contour of the semiconductor pattern  6  is smaller than the outer edge  5 UO of the drain electrode  5  in the U-shaped region in plan view. Therefore, the semiconductor pattern other than the channel region  6 C can be entirely covered by the source electrode  4  and the drain electrode  5  in the U-shaped region, and when the TFT is covered by a capacitor electrode  8  to be described later, an area Sdc of overlap between the drain electrode  5  and the capacitor electrode  8  can be fixed, resulting in stabilization of characteristics. In  FIG. 2 , the contour of the semiconductor pattern  6  is larger than the outer edge  5 UO of the drain electrode  5  in the U-shaped region in plan view. In this case, since there is the semiconductor pattern  6  around the drain electrode  5 , the amount of objects to be etched at the time of etching the channel region  6 C is large, which leads to the advantageous effect that the etching rate is equalized. 
     Note that (b) in  FIG. 1  and (b) in  FIG. 2  are examples in which there is no storage capacitance. When the display medium has large capacitance, charge is stored in the capacitance of the display medium and the electric potential is maintained, meaning that there is no need to provide storage capacitance inside the TFT array. This is the case, for example, when the display medium is liquid crystals and when the display medium is thin. In contrast, when the capacitance of the display medium is not sufficiently large, the storage capacitance Cs is used. 
       FIGS. 10A to 13B  show examples in which the storage capacitance Cs is provided.  FIGS. 10A to 10C  show a manufacturing process of a thin film transistor array according to a variation in which a first conductive layer including the gate electrode  2  and the row wiring  2 L, the gate insulating layer  3 , a second conductive layer including the source electrode  4 , the column wiring  4 L, and the drain electrode  5 , an interlayer insulating film  7 , a third conductive layer including the capacitor electrode  8  and a capacitor wiring  8 L, a capacitor insulating film  9 , and a fourth conductive layer including the pixel electrode  10  are stacked at least in the stated order. Note that a specific manufacturing method will be described in an example to be described later. 
     In the manufactured thin film transistor array, the semiconductor pattern  6  is adjacent to the source electrode  4  and the drain electrode  5  and forms the U-shaped region  6 U of the channel. Since the source electrode  4  is in the shape of a line having a constant width, the width of the source electrode  4  can be reduced almost to the limit of resolution, and as a result of the area of the source electrode  4  being small, the area Sgs of overlap between the gate electrode  2  and the source electrode  4  is small, and the gate-source capacitance Cgs is small. When the dielectric constant of the gate insulating film  3  is denoted as cgi and the thickness of the gate insulating film  3  is denoted as Dgi, Cgs=ϵgi·Sgs/Dgi. Note that the area Sgsl of overlap between the row wiring  2 L and the column wiring  4 L cannot be ignored and should be added, resulting in Cgs=εgi·(Sgs+Sgsl)/Dgi. 
     The column wiring  4 L overlaps neither of the capacitor electrode  8  nor the capacitor wiring  8 L in the plan view. Removing the overlap between the column wiring  4 L and the capacitor electrode  8  can lead to a reduction in the source-capacitor capacitance Csc. When the TFT is covered by the capacitor electrode  8 , since the source electrode  4  is in the shape of a line having a constant width, the width of the source electrode  4  can be reduced almost to the limit of resolution, and as a result of the area of the source electrode  4  being small, the area Ssc of overlap between the source electrode  4  and the capacitor electrode  8  is small, and the source-capacitor capacitance Csc is small. When the dielectric constant of the interlayer insulating film  7  is denoted as εil and the thickness of the interlayer insulating film  7  is denoted as Dil, Csc=εil·Ssc/Dil. (When the TFT is not covered by the capacitor electrode  8  as a variation of (d) in  FIG. 10B , the area Ssc of overlap between the source electrode  4  and the capacitor electrode  8  is substantially zero, and the source-capacitor capacitance C SC  is substantially zero.) 
     The pixel electrode  10  belongs to a layer different from a layer including the drain electrode  5 , and there are the capacitor insulating film  9  and the interlayer insulating film  7  between the pixel electrode  10  and the drain electrode  5 ; thus, the drain electrode  5  is connected to the pixel electrode  10  via the drain connecting wiring  5 C, a drain pad  5 P, the opening of the interlayer insulating film  7 , and the opening of the capacitor insulating film  9 . A major part of the column wiring  4 L desirably overlaps the pixel electrode  10  in plan view. When a major part of the column wiring  4 L overlaps the pixel electrode  10 , the electric potential at the column wiring  4 L has no impact on the color of the display medium. Although capacitance Csp due to the overlap between the column wiring  4 L and the pixel electrode  10  is generated, the capacitance Csp is not very large because two layers, the capacitor insulating film  9  and the interlayer insulating film  7 , are sandwiched. When the dielectric constant of the capacitor insulating film  9  is denoted as cci and the thickness of the capacitor insulating film  9  is denoted as Dci, Csp=Ssp/(Dci/εci+Dik/εil). 
       FIGS. 11A to 11C  show a manufacturing process of a thin film transistor array according to a variation in which a first conductive layer including the source electrode  4 , the column wiring  4 L, and the drain electrode  5 , the gate insulating layer  3 , a second conductive layer including the gate electrode  2  and the row wiring  2 L, the interlayer insulating film  7 , a third conductive layer including the capacitor electrode  8  and the capacitor wiring  8 L, the capacitor insulating film  9 , and a fourth conductive layer including the pixel electrode  10  are stacked at least in the stated order. 
     In the thin film transistor array in  FIGS. 11A to 11C , the gate-source capacitance Cgs is small as in  FIGS. 10A to 10C . 
     The column wiring  4 L overlaps neither of the capacitor electrode  8  nor the capacitor wiring  8 L in the plan view. Removing the overlap between the column wiring  4 L and the capacitor electrode  8  can lead to a reduction in the source-capacitor capacitance C SC . Since a major part of the source electrode  4  is covered by the gate electrode  2 , the area Ssc of overlap between the source electrode  4  and the capacitor electrode  8  is small, and the source-capacitor capacitance Csc is also small. When the dielectric constant of the interlayer insulating film  7  is denoted as εil and the thickness of the interlayer insulating film  7  is denoted as Dil, Csc=Ssc/(Dil/εil+Dgi/εgi). When the TFT is covered by the capacitor electrode  8 , an area Sgc of overlap between the gate electrode  2  and the capacitor electrode  8  is generated. When the dielectric constant of the interlayer insulating film  7  is denoted as εil and the thickness of the interlayer insulating film  7  is denoted as Dil, Cgc=εil·Sgc/Dil. (When the TFT is not covered by the capacitor electrode  8  as a variation shown by (d) in  FIG. 11B , the area Sgc of overlap between the gate electrode  2  and the capacitor electrode  8  is substantially zero, but the area Sgcl of overlap between the row wiring  2 L and the capacitor wiring  8 L cannot be ignored; thus, the gate-capacitor capacitance Cgc is εil·Sgcl/Dil.) 
     The pixel electrode  10  belongs to a layer different from a layer to which the drain electrode  5  belongs, and there are the capacitor insulating film  9 , the interlayer insulating film  7 , the gate insulating film  3  between the pixel electrode  10  and the drain electrode  5 ; thus, the drain electrode  5  is connected to the pixel electrode  10  via the drain connecting wiring  5 C, the drain pad  5 P, the opening of the gate insulating film  3 , the opening of the interlayer insulating film  7 , and the opening of the capacitor insulating film  9 . A major part of the column wiring  4 L desirably overlaps the pixel electrode  10  in plan view. When a major part of the column wiring  4 L overlaps the pixel electrode  10 , the electric potential at the column wiring  4 L has no impact on the color of the display medium. Although capacitance Csp due to the overlap between the column wiring  4 L and the pixel electrode  10  is generated, the capacitance Csp is not very large because three layers, the capacitor insulating film  9 , the interlayer insulating film  7 , and the gate insulating film  3  are sandwiched. When the dielectric constant of the capacitor insulating film  9  is denoted as cci and the thickness of the capacitor insulating film  9  is denoted as Dci, Csp=Ssp/(Dci/εci+Dil/εil+Dgi/εgi). 
       FIGS. 12A and 12B  show a manufacturing process of a thin film transistor array according to a variation in which a first conductive layer including the gate electrode  2 , the row wiring  2 L, and a drain sub-electrode  5 S, the gate insulating film  3 , a second conductive layer including the source electrode  4 , the column wiring  4 L, the drain electrode  5 , the capacitor electrode  8 , and the capacitor wiring  8 L, the interlayer insulating film  7 , and a third conductive layer including the pixel electrode  10  are stacked at least in the stated order. 
     In the thin film transistor array in  FIGS. 12A and 12B , the gate-source capacitance Cgs is small as in  FIGS. 10A to 10C . 
     The area of overlap between the column wiring  4 L and the capacitor electrode  8  is zero, and the source-capacitor capacitance C SC  is substantially zero. The pixel electrode  10  belongs to a layer different from a layer to which the drain electrode  5  belongs, and the interlayer insulating film  7  is located between the pixel electrode  10  and the drain electrode  5 ; thus, the drain electrode  5  is connected to the pixel electrode  10  via the drain connecting wiring  5 C, the drain pad  5 P, and the opening of the interlayer insulating film  7 . A major part of the column wiring  4 L desirably overlaps the pixel electrode  10  in plan view. When a major part of the column wiring  4 L overlaps the pixel electrode  10 , the electric potential at the column wiring  4 L has no impact on the color of the display medium. Although capacitance Csp due to the overlap between the column wiring  4 L and the pixel electrode  10  is generated, the capacitance Csp is not very large because the interlayer insulating film  7  is thick. Csp=εil·Ssp/Dil 
       FIGS. 13A and 13B  show a manufacturing process of a thin film transistor array according to a variation in which a first conductive layer including the gate electrode  2 , the row wiring  2 L, the capacitor electrode  8 , and the capacitor wiring  8 L, the gate insulating film  3 , a second conductive layer including the source electrode  4 , the column wiring  4 L, the drain electrode  5 , and the pixel electrode  10 , and the interlayer insulating film  7  are stacked at least in the stated order. 
     In the thin film transistor array in  FIGS. 13A and 13B , the gate-source capacitance Cgs is small as in  FIGS. 10A to 10C . 
     The source electrode  4  and the capacitor electrode  8  do not overlap each other, but the column wiring  4 L and the capacitor wiring  8 L have an area Sscl of overlap, and the source-capacitor capacitance is Csc=εil·Sscl/Dgi. The pixel electrode  10  is in the same layer as the drain electrode  5 , and the drain electrode  5  is connected to the pixel electrode  10  via the drain connecting wiring  5 C. The interlayer insulating film  7  covers at least the source electrode  4 , the column wiring  4 L, and the semiconductor pattern  6 , and does not cover the pixel electrode  10 . Since the column wiring  4 L and the pixel electrode  10  are in the same layer, an area Ssp of overlap is zero, and source-pixel capacitance Csp is substantially zero. 
       FIGS. 14A to 14C  are a variation of  FIG. 2 .  FIGS. 14A to 14C  show a manufacturing process of a thin film transistor array according to a variation in which a first conductive layer including the gate electrode  2  and the row wiring  2 L, the gate insulating layer  3 , a second conductive layer including the source electrode  4 , the column wiring  4 L, and the drain electrode  5 , the interlayer insulating film  7 , a third conductive layer including the capacitor electrode  8  and the capacitor wiring  8 L, the capacitor insulating film  9 , and a fourth conductive layer including the pixel electrode  10  are stacked at least in the stated order. 
     In the thin film transistor array in  FIGS. 14A to 14C , the gate-source capacitance Cgs is small as in  FIGS. 10A to 10C . 
     The column wiring  4 L overlaps neither of the capacitor electrode  8  nor the capacitor wiring  8 L in the plan view. Removing the overlap between the column wiring  4 L and the capacitor electrode  8  can lead to a reduction in the source-capacitor capacitance C SC . When the TFT is covered by the capacitor electrode  8 , since the source electrode  4  is in the shape of a line having a constant width, the width of the source electrode  4  can be reduced almost to the limit of resolution, the area S SC  of overlap between the source electrode  4  and the capacitor electrode  8  is small, and the source-capacitor capacitance C SC  is small. When the dielectric constant of the interlayer insulating film  7  is denoted as εil and the thickness of the interlayer insulating film  7  is denoted as Dil, Csc=εil·Ssc/Dil. (When the TFT is not covered by the capacitor electrode  8  as a variation of (d) in  FIG. 14B , the area Ssc of overlap between the source electrode  4  and the capacitor electrode  8  is substantially zero, and the source-capacitor capacitance C SC  is substantially zero.) 
     The pixel electrode  10  belongs to a layer different from a layer including the drain electrode  5 , and there are the capacitor insulating film  9  and the interlayer insulating film  7  between the pixel electrode  10  and the drain electrode  5 ; thus, the drain electrode  5  is connected to the pixel electrode  10  via the drain connecting wiring  5 C, a drain pad  5 P, the opening of the interlayer insulating film  7 , and the opening of the capacitor insulating film  9 . A major part of the column wiring  4 L desirably overlaps the pixel electrode  10  in plan view. When a major part of the column wiring  4 L overlaps the pixel electrode  10 , the electric potential at the column wiring  4 L has no impact on the color of the display medium. Although capacitance Csp due to the overlap between the column wiring  4 L and the pixel electrode  10  is generated, the capacitance Csp is not very large because two layers, the capacitor insulating film  9  and the interlayer insulating film  7 , are sandwiched. When the dielectric constant of the capacitor insulating film  9  is denoted as cci and the thickness of the capacitor insulating film  9  is denoted as Dci, Csp=Ssp/(Dci/εci+Dil/εil). 
     Possible variations of  FIG. 2  include a structure similar to those shown in  FIGS. 11A to 13B , which are variations of  FIG. 1 . 
     The importance of reducing Cgs, Csc, and Csp is described below. The TFT array includes five different electrodes, the gate electrode  2 , the source electrode  4 , the drain electrode  5 , the capacitor electrode  8 , and the pixel electrode  10 , but since the pixel electrode  10  is connected to the drain electrode  5 , the TFT array includes practically four different electrodes. Capacitance between these electrodes is of  4 C 2 =6 kinds, namely, Cgs, Csc, Csp, Cgd, Cgc, and Cs. The storage capacitance Cs is desirably large to some extent, but the other capacitances are desirably small. 
     Assume that there are M column wirings  4 L and N row wirings  2 L. In this case, Cgs, Csc, and Csp//Cs are connected to the column wirings  4 L. Here, “//” means a series circuit of the capacitance; for example, Csp//Cs=1/(1/Csp+1/Cs). Note that since Csp &lt;&lt;Cs, Csp//Cs≈Csp. There are N pixels connected to a single column wiring  4 L, and therefore the capacitance is C=N(Cgs+Csc+Csp//Cs). 
     The column wiring  4 L changes voltage according to data in each row and therefore, the amount of charge/discharge becomes largest when voltages having opposite polarities are written in respective adjacent rows. The amount of electric power consumed by a single column wiring  4 L in a single frame can be calculated as indicated in  FIG. 18 . Here, the voltage waveform in the column wiring  4 L is denoted as V 4 , voltages for white writing and black writing are denoted as ±Vs, column wiring resistance (in a strict sense, the sum of column wiring resistance and series resistance (such as output resistance of a source driver)) is denoted as R. In  FIG. 18 , the horizontal axis denotes time t. At the source driver, the voltage and electric current of a positive power supply are denoted as Vp and Ip, respectively, the voltage and electric current of a negative power supply are denoted as Vn and In, respectively, and the voltage and electric current of a GND line are denoted as V 0 =0 and I 0 , respectively. The electric power consumed by the positive power supply is denoted as Pp, the electric power consumed by the negative power supply is denoted as Pn, and the electric power consumed by the GND line is P 0 =0. The integral of each charging waveform is indicated as being evaluated in a range t=0 to ∞ in order to simplify the equations, but it is sufficient that t be sufficiently larger than a time constant CR; for example, even if t=0 to 3CR, 95% of the amount of electric power is covered and approximately the same. The amount of electric power consumed by a single column wiring in a single frame is (2N−1)C(Vs) 2 . Thus, the amount of electric power consumed by the M column wirings in a single frame is M×(2N−1)×N(Cgs+Csc+Csp//Cs)×(Vs) 2 =MN(2N−1) (Cgs+Csc+Csp//Cs) (Vs) 2 , which can be regarded as 2M(N 2 ) (Cgs+Csc+Csp//Cs)(Vs) 2  when N is sufficiently larger than 1. The amount of electric power consumption is smallest when the voltage at the column wiring remains the same; in this case, the amount of electric power consumed in a single frame is zero. 
     Here, Cgs, Cgc, and Cgd//Cs are connected to the row wirings  2 L. There are M pixels connected to a single row wiring  2 L, and therefore the capacitance is C=M(Cgs+Cgc+Cgd//Cs). Note that since Cgd&lt;&lt;Cs, Cgd//Cs≈Cgd. In a single frame, the gate voltage changes twice in total, specifically once from OFF to ON and once from ON to OFF. When an amount of change in the gate voltage is denoted as ΔVg, the amount of electric power consumed by a single row wiring in a single frame can be calculated as shown in  FIG. 19 . The voltage waveform in the row wiring  2 L is denoted as V 2 . Note that  FIG. 19  shows the case of a p-channel TFT; in the case of an n-channel TFT, the equations for the amount of electric power consumption are the same although the plus/minus signs of the voltage are reversed. A positive voltage at the gate is denoted as Vp, a negative voltage at the gate is denoted as Vn, and row wiring resistance (in a strict sense, the sum of row wiring resistance and series resistance (such as output resistance of the gate driver)) is denoted as R. In  FIG. 19 , the horizontal axis denotes time t. At the gate driver  14 , the voltage and electric current of a positive power supply are denoted as Vp and Ip, respectively, and the voltage and electric current of a negative power supply are denoted as Vn and In, respectively. The electric power consumed by the positive power supply is denoted as Pp, and the electric power consumed by the negative power supply is denoted as Pn. The integral of each charging waveform is indicated as being evaluated in a range t=0 to ∞ in order to simplify the equations, but it is sufficient that t be sufficiently larger than a time constant CR; for example, even if t=0 to 3CR, 95% of the amount of electric power is covered and approximately the same. The amount of electric power consumed by a single row wiring in a single frame is C(ΔVg) 2 . The amount of electric power consumed by the N row wirings in a single frame is N×M(Cgs+Cgc+Cgd//Cs)×(ΔVg) 2 =MN(Cgs+Cgc+Cgd//Cs)(ΔVg) 2 . 
     Here, Cgd and Cs are connected to the TFT. The capacitance is C=Cgd+Cs. In a single frame, the pixel voltage changes once when the pixel displays data different from previously displayed data. The amount of charging is largest in the case of changing data displayed at all the pixels. In this case, when an amount of change in the voltage in the column wiring is denoted as Vs, the amount of electric power consumed in a single frame can be calculated as shown in  FIG. 20 . The voltage waveform at the pixel is denoted as Vpixel. TFT resistance (in a strict sense, the sum of TFT resistance and series resistance (such as column wiring resistance)) is denoted as R. In  FIG. 20 , the horizontal axis denotes time t. When a drain voltage is written as Vd=Vs, the electric current is Itft and the electric power consumption is Ptft. The integral of the charging waveform is evaluated for the range t=0 to ∞ in order to simplify the equations, but it is sufficient that t be sufficiently larger than the time constant CR; for example, even if t=0 to 3CR, 95% of the amount of electric power is covered and approximately the same. The amount of electric power consumed by a single TFT in a single frame is (Cs+Cgd)(Vs) 2 , and when there are MN TFTs, is MN(Cs+Cgd)(Vs) 2 . In the case of Vd=−Vs, the same value is obtained. The amount of electric power consumption is smallest when the pixel potential remains the same; in this case, the amount of electric power consumed in a single frame is zero. 
     A coefficient of the amount of electric power consumed as described above is MN 2  for the column wiring, MN for the row wiring, and MN for the pixel. Normally, M, N, or the like is several tens to several hundreds. Furthermore, typically, Cgs, Csc, Csp, Cgc, and Cgd are smaller than Cs roughly by approximately two orders of magnitude. Thus, the maximum amount of electric power consumed by the column wiring in a single frame is substantially equal to the maximum amount of electric power consumed by the pixel in a single frame, and the amount of electric power consumed by the row wiring in a single frame is smaller than these by two orders of magnitude. 
     In the case of electronic paper, the same image is often drawn throughout two or more frames (approximately ten frames). In this case, electric power is consumed for rewriting in the first frame, but, in the second to the tenth frames, the electric potential is the same and therefore, almost no electric power is consumed. Thus, the maximum amount of electric power consumed by the column wiring in approximately ten frames is larger, and the maximum amount of electric power consumed by the pixel in approximately ten frames is smaller, by an order of magnitude, than the maximum amount of electric power consumed by the column wiring in approximately ten frames, and the maximum amount of electric power consumed by the row wiring in approximately ten frames is even smaller, by an order of magnitude, than the maximum amount of electric power consumed by the pixel in approximately ten frames. Therefore, reducing the capacitance (Cgs, Csc, Csp) connected to the column wiring is important for reducing the amount of electric power consumption. 
     Thus, the structures shown in  FIGS. 1, 2, and 10A to 14C  have the advantageous effect of reducing the amount of electric power consumption. Specifically, using the above-described thin film transistor array in a display device enables a reduction in the power consumption upon rewriting of the display device, enabling a reduction in the frequency of battery replacement for a display device of a type that includes an internal battery. Furthermore, in the case of a display device of the type that converts RF waves into electric power, a possible rewrite range thereof can be extended. 
     Note that the width of the U-shaped part  5 U of the drain electrode  5  may be, but is not required to be, constant. Although the inner edge  5 UI needs to be in a U shape, the outer edge  5 UO is not required to be in a U shape. 
     Furthermore, the width of the source electrode  4  is desirably less than or equal to the width of the column wiring  4 L, as shown in  FIG. 9 . The area of the source electrode  4  has an impact on Cgs, and when the capacitor electrode  8  covers the source electrode  4 , has an impact on Csc as well, resulting in a significant impact on the amount of electric power consumption in the column wiring. Therefore, the width of the source electrode  4  should be as small as possible. Meanwhile, the area of the column wiring  4 L has an impact on Csp, but has a limited impact on the amount of electric power consumption in the column wiring because the insulating film relating to Csp is thick. The column wiring  4 L is long and therefore electrical resistance thereof may cause a delay in signal response and deteriorate the display, and if the column wiring  4 L is disconnected, all the subsequent pixels are affected. Therefore, the column wiring  4 L may be broader than the source electrode  4 . 
     Furthermore, instead of the source electrode  4  extending with a constant width and being directly connected to the column wiring  4 L, a source connecting wiring  4 C narrower than the source electrode  4  may connect the source electrode  4  and the column wiring  4 L, as shown in the lower part of  FIG. 9 . Even in the case where the source electrode  4  cannot be made so narrow, Cgs, Csc, and the like can be reduced by reducing the width of the source connecting wiring  4 C located between the TFT and the column wiring  4 L. 
     Examples of the material of an insulating substrate  1  may include inorganic materials such as glass, and organic materials such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyether sulfone (PES), polycarbonate, polyimide (PI), polyether imide (PEI), polystyrene (PS), polyvinyl chloride (PVC), polyethylene (PE), polypropylene (PP), nylon (Ny), and epoxy. 
     Examples of the materials of the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer may include metals such as Al, Ag, Cu, Cr, Ni, Mo, Au, Pt, and Nb, alloys thereof, conductive oxides such as ITO, carbon, and conductive polymers. The first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer may be formed by printing and baking an ink, or by forming a layer over the insulating substrate  1  by sputtering or the like and then performing photolithography, etching, and resist stripping. Alternatively, resist-printing, etching, and resist stripping may be performed after formation of the layer over the insulating substrate  1  by sputtering or the like, to form the first to the fourth conductive layers. 
     Examples of the materials of the gate insulating film  3 , the interlayer insulating film  7 , and the capacitor insulating film  9  may include inorganic materials such as SiO 2 , SiON, and SiN, and organic materials such as polyvinyl phenol (PVP) and epoxy. The gate insulating film  3 , the interlayer insulating film  7 , and the capacitor insulating film  9  may be formed by vacuum deposition such as sputtering or CVD, or by applying and baking a solution. 
     Examples of the material of the semiconductor pattern  6  may include inorganic semiconductors such as amorphous Si and poly-Si, organic semiconductors such as polythiophene-based, acene-based, and allylamine-based materials, and oxide semiconductors such as In 2 O 3 -based, Ga 2 O 3 -based, ZnO-based, SnO 2 -based, InGaZnO-based, InGaSnO-based, and InSnZnO-based materials. The semiconductor pattern  6  may be formed by forming a layer over the insulating substrate  1  by plasma CVD or the like and then performing photolithography, etching, and resist stripping. Alternative methods include printing and baking a solution by using inkjet printing, dispensing, relief printing, or the like. A contact layer for improving electrical contact with the source electrode  4 , the drain electrode  5 , and the like may be provided above the semiconductor pattern  6 . The contact layer above the channel may be removed by etching after formation of the source electrode  4  and the drain electrode  5 . 
     Second Embodiment 
     Next, a thin film transistor array according to the second embodiment of the present invention is described, focusing on differences from the thin film transistor array according to the first embodiment.  FIG. 3  shows a portion of a thin film transistor array according to the second embodiment of the present invention.  FIG. 4  shows a portion of a thin film transistor array according to a variation. In  FIGS. 3 and 4 , (a) is a production drawing for showing features in an easy-to-understand manner, and (b) is a final drawing. The thin film transistor array shown in  FIGS. 3 and 4  includes a plurality of column wirings  4 L extending in the longitudinal direction (first direction), a plurality of row wirings  2 L extending in the lateral direction (second direction) orthogonal to the plurality of column wirings  4 L, and pixels provided corresponding to crossing points of the column wirings  4 L and the row wirings  2 L. 
     In the case of  FIGS. 3 and 4 , a tip of the source electrode  4  is rounded. Furthermore, the bottom of the U shape of the drain electrode  5  is also rounded. With this structure, both side edges and the tip edge of the source electrode  4  can be used to form the channel region  6 C, and the area of the source electrode  4  can be reduced while a channel width W for obtaining a required on-state current is sufficiently secured, and an area Sgs of overlap between the gate electrode and the source electrode can be reduced, leading to a reduction in Cgs. 
     In (a) in  FIG. 3 , the contour of the gate electrode  2  is smaller than the outer edge  5 UO of the drain electrode  5 , but is larger than the inner edge  5 UI of the drain electrode  5  in the U-shaped region in plan view, as shown in  FIG. 8 . In other words, at least a portion of the outline of the gate electrode  2  overlaps the U-shaped part  5 U of the drain electrode  5  in the U-shaped region in plan view. Since the contour of the gate electrode  2  is smaller than the outer edge  5 UO of the drain electrode  5  in the U-shaped region, the area Sgd of overlap between the gate electrode and the drain electrode is small, and the gate-drain capacitance Cgd is also small. Furthermore, since the contour of the gate electrode  2  is larger than the inner edge  5 UI of the drain electrode  5 , the current in the channel region  6 C can be reliably controlled. 
     In (a) in  FIG. 4 , the contour of the gate electrode  2  is larger than the outer edge  5 UO of the drain electrode  5  in the U-shaped region in plan view. In this case, the drain connecting wiring  5 C and the gate electrode  2  have an overlap  5 CX, and the gate-drain capacitance Cgd becomes large for the overlap  5 CX. 
     In (a) in  FIGS. 3 and 4 , the contour of the gate electrode  2  is larger than the contour of the semiconductor pattern  6  in the U-shaped region, and the gate electrode  2  and the semiconductor pattern  6  protrude from the opening region in plan view, as shown in  FIG. 8 . In other words, at least a portion of the outline of the gate electrode  2  is formed outside the outline of the semiconductor pattern  6  in the U-shaped region, and at least a portion of the outline of each of the gate electrode  2  and the semiconductor pattern  6  is formed outside the opening of the U-shaped part  5 U in the opening region in plan view. Since the contour of the gate electrode  2  is larger than the contour of the semiconductor pattern  6 , incident light from the back side is shielded by the gate electrode  2  and does not reach the semiconductor pattern  6 . Accordingly, malfunctions due to external light can be reduced. Particularly, in (a) in  FIG. 4 , the contour of the gate electrode  2  is larger than that in (a) in  FIG. 3 , leading to a significant malfunction prevention effect. Furthermore, as a result of the gate electrode  2  and the semiconductor pattern  6  protruding from the opening region, the effect of the parasitic transistor generated from the edge of the semiconductor pattern  6  can be reduced. Note that a portion of the gate electrode  2 , the semiconductor pattern  6 , or the like that protrudes from the opening region may be round as shown in the upper part of  FIG. 8  or may be straight as shown in the lower part of  FIG. 8 . The channel region  6 C is made up of two regions, namely, a main part including the U-shaped region  6 U of the channel and an auxiliary part slightly protruding from the opening side. 
     Note that (b) in  FIG. 3  and (b) in  FIG. 4  are examples in which there is no storage capacitance. When the display medium has large capacitance, charge is stored in the capacitance of the display medium and the electric potential is maintained, meaning that there is no need to provide storage capacitance inside the TFT array. This is the case, for example, when the display medium is liquid crystals and when the display medium is thin. In contrast, when the capacitance of the display medium is not sufficiently large, the storage capacitance Cs is used. 
       FIGS. 15A to 15C  show examples of  FIG. 3  with the storage capacitance Cs.  FIGS. 16A to 16C  show examples of  FIG. 4  with the storage capacitance Cs.  FIGS. 15A to 15C  and  FIGS. 16A to 16C  each show a manufacturing process of a thin film transistor array according to a variation in which a first conductive layer including the gate electrode  2  and the row wiring  2 L, the gate insulating layer  3 , a second conductive layer including the source electrode  4 , the column wiring  4 L, and the drain electrode  5 , the interlayer insulating film  7 , a third conductive layer including the capacitor electrode  8  and the capacitor wiring  8 L, the capacitor insulating film  9 , and a fourth conductive layer including the pixel electrode  10  are stacked at least in the stated order. 
     In the thin film transistor arrays shown in  FIGS. 15A to 15C  and  FIGS. 16A to 16C , the gate-source capacitance Cgs, the source-capacitor capacitance Csc, and the capacitance Csp due to the overlap between the column wiring  4 L and the pixel electrode  10  can be reduced for substantially the same reason as in  FIGS. 10A to 10C . 
     Possible variations of  FIG. 3  include a structure similar to those shown in  FIGS. 11A to 13B , which are variations of  FIG. 1 . 
     Possible variations of  FIG. 4  include a structure similar to those shown in  FIGS. 11A to 13B , which are variations of  FIG. 1 . 
     Furthermore, for the reason described above, the structures shown in  FIGS. 3, 4 , and  15 A to  16 C have the advantageous effect of reducing the amount of electric power consumption. 
     Note that in the case of (a) in  FIG. 3 , the width of the U-shaped part  5 U of the drain electrode  5  may be, but is not required to be, constant. Although the inner edge  5 UI needs to be in a U shape, the outer edge  5 UO is not required to be in a U shape. In the case of (a) in  FIG. 4 , the width of the U-shaped part  5 U of the drain electrode  5  should be constant and small. If the outer edge  5 UO of the drain electrode  5  is large in (a) in  FIG. 4 , the area Sgd of overlap between the gate electrode and the drain electrode becomes large, leading to large gate-drain capacitance Cgd. 
     The widths of the source electrode  4  and the column wiring  4 L are substantially the same as those in the thin film transistor array according to the first embodiment. 
     The thin film transistor array according to the second embodiment can be manufactured using substantially the same materials as those used to manufacture the thin film transistor array according to the first embodiment. 
     Third Embodiment 
     Next, a thin film transistor array according to the third embodiment of the present invention is described, focusing on differences from the thin film transistor array according to the first embodiment.  FIGS. 5( a ) and 5( b )  show a portion of the thin film transistor array according to the third embodiment of the present invention.  FIG. 5( a )  is a manufacturing process diagram for showing features in an easy-to-understand manner, and  FIG. 5( b )  is a final drawing. The thin film transistor array shown in  FIGS. 5( a ) and 5( b )  includes a plurality of column wirings  4 L extending in the longitudinal direction (first direction), a plurality of row wirings  2 L extending in the lateral direction (second direction) orthogonal to the plurality of column wirings  4 L, and pixels provided corresponding to crossing points of the column wirings  4 L and the row wirings  2 L. 
     Each pixel includes at least a thin film transistor and a pixel electrode  10 . The thin film transistor includes a gate electrode  2 , a source electrode  4 , and a drain electrode  5 . In a plan view, the source electrode  4  is in the shape of a line having a rounded tip and a constant width, the drain electrode  5  includes a U-shaped part  5 U in a U shape surrounding the source electrode  4  with a gap having a predetermined width therebetween, and at least a portion of a semiconductor pattern  6  connects the source electrode  4  and the drain electrode  5  to form a channel region  6 C. At this time, a U-shaped insulative etching stopper layer  6 S is formed on the semiconductor pattern  6  to include the gap having the predetermined width, and the semiconductor pattern  6  becomes the channel region  6 C below the etching stopper layer  6 C and below the source electrode  4  and the drain electrode  5 . The gate electrode  2  at least partially overlaps the channel region  6 C via a gate insulating film  3 , the source electrode  4  is connected to the column wiring  4 L, the gate electrode  2  is connected to the row wiring  2 L via a gate connecting wiring  2 C, and the drain electrode  5  is connected to the pixel electrode  10  via at least a drain connecting wiring  5 C. Note that as with the outer edge  5 UO and the inner edge  5 UI of the U-shaped part  5 U of the drain electrode  5  shown in  FIG. 6 , the outer line and the inner line of the U shape of the etching stopper layer  6 S are referred to as an outer edge  6 SO and an inner edge  6 SI, respectively. 
     With this structure, the inner edge  6 SI of the etching stopper layer  6 S that is close to the both side edges and the tip edge of the source electrode  4  can be used to form the channel region  6 C, the area of the source electrode  4  can be reduced while the channel width W for obtaining a required on-state current is sufficiently secured, and the area Sgs of overlap between the gate electrode and the source electrode can be reduced, leading to a reduction in Cgs. 
     The gate connecting wiring  2 C is narrower than the gate electrode  2  and overlaps neither of one of the drain electrodes  5  nor the drain connecting wiring  5 C. Thus, gate-drain capacitance Cgd can be minimized. 
     In  FIG. 5( a ) , the contour of the gate electrode  2  is smaller than the outer edge  5 UO of the drain electrode  5 , but is larger than the outer edge  6 SO of the etching stopper layer  6 S in the U-shaped region in plan view, as shown in  FIG. 9 . In other words, at least a portion of the outline of the gate electrode  2  is formed outside the outer edge  6 SO of the etching stopper layer  6 S and overlaps the U-shaped part  5 U of the drain electrode  5  in the U-shaped region in plan view. Since the contour of the gate electrode  2  is smaller than the outer edge  5 UO of the drain electrode  5  in the U-shaped region, the area Sgd of overlap between the gate electrode and the drain electrode is small, and the gate-drain capacitance Cgd is also small. Furthermore, since the contour of the gate electrode  2  is larger than the outer edge  6 SO of the etching stopper layer  6 S, the gate electrode  2  includes the etching stopper layer  6  in plan view, and thus the electric current in the channel region  6 C can be reliably controlled. 
     Note that  FIG. 5( b )  is an example in which there is no storage capacitance. When the display medium has large capacitance, charge is stored in the capacitance of the display medium and the electric potential is maintained, meaning that there is no need to provide storage capacitance inside the TFT array. This is the case, for example, when the display medium is liquid crystals and when the display medium is thin. In contrast, when the capacitance of the display medium is not sufficiently large, the storage capacitance Cs is used. 
       FIGS. 17A to 17C  show examples in which there is the storage capacitance Cs.  FIGS. 17A to 17C  show the TFT in a manufacturing process of a thin film transistor array according to a variation in which a first conductive layer including the gate electrode  2  and the row wiring  2 L, the gate insulating layer  3 , a second conductive layer including the source electrode  4 , the column wiring  4 L, and the drain electrode  5 , the interlayer insulating film  7 , a third conductive layer including the capacitor electrode  8  and the capacitor wiring  8 L, the capacitor insulating film  9 , and a fourth conductive layer including the pixel electrode  10  are stacked at least in the stated order. 
     In the manufactured thin film transistor array, the etching stopper layer  6 S in the U shape is formed on the semiconductor pattern  6 , the semiconductor pattern  6  contacts the source electrode  4  inside the inner edge  6 SI of the etching stopper layer  6 S and contacts the drain electrode  5  outside the outer edge  6 SO of the U shape of the etching stopper layer  6 S in plan view, and the semiconductor pattern  6  immediately below the etching stopper layer  6 S forms the U-shaped region  6 U of the channel. In plan view, the source electrode  4  is in the shape of a line having a constant width, and because the inner edge  6 SI of the etching stopper layer  6 S needs to be located inside the source electrode  4 , the width of the source electrode  4  cannot be reduced almost to the limit of resolution, but can be reduced to some extent. Therefore, as a result of the area of the source electrode  4  being small, the area Sgs of overlap between the gate electrode  2  and the source electrode  4  is small, and the gate-source capacitance Cgs is small. When the dielectric constant of the gate insulating film  3  is denoted as cgi and the thickness of the gate insulating film  3  is denoted as Dgi, Cgs=εgi·Sgs/Dgi. Note that the area Sgsl of overlap between the row wiring  2 L and the column wiring  4 L cannot be ignored and should be added, resulting in Cgs=εgi·Sgs+Sgsl)/Dgi. 
     The column wiring  4 L overlaps neither of the capacitor electrode  8  nor the capacitor wiring  8 L in the plan view. Removing the overlap between the column wiring  4 L and the capacitor electrode  8  can lead to a reduction in the source-capacitor capacitance Csc. When the TFT is covered by the capacitor electrode  8 , since the source electrode  4  is narrow to some extent, the area of the source electrode  4  is small, and thus the area Ssc of overlap between the source electrode  4  and the capacitor electrode  8  is small, leading to small source-capacitor capacitance Csc. When the dielectric constant of the interlayer insulating film  7  is denoted as εil and the thickness of the interlayer insulating film  7  is denoted as Dil, Csc=εil·Ssc/Dil. (When the TFT is not covered by the capacitor electrode  8  as a variation of (d) in  FIG. 17B , the area Ssc of overlap between the source electrode  4  and the capacitor electrode  8  is substantially zero, and the source-capacitor capacitance Csc is substantially zero.) 
     The pixel electrode  10  belongs to a layer different from a layer including the drain electrode  5 , and there are the capacitor insulating film  9  and the interlayer insulating film  7  between the pixel electrode  10  and the drain electrode  5 ; thus, the drain electrode  5  is connected to the pixel electrode  10  via the drain connecting wiring  5 C, a drain pad  5 P, the opening of the interlayer insulating film  7 , and the opening of the capacitor insulating film  9 . A major part of the column wiring  4 L desirably overlaps the pixel electrode  10  in plan view. When a major part of the column wiring  4 L overlaps the pixel electrode  10 , the electric potential at the column wiring  4 L has no impact on the color of the display medium. Although capacitance Csp due to the overlap between the column wiring  4 L and the pixel electrode  10  is generated, the capacitance Csp is not very large because two layers, the capacitor insulating film  9  and the interlayer insulating film  7 , are sandwiched. When the dielectric constant of the capacitor insulating film  9  is denoted as cci and the thickness of the capacitor insulating film  9  is denoted as Dci, Csp=Ssp/(Dci/εci +Dil/εil ). 
     Possible variations of  FIG. 5  include a structure similar to those shown in  FIGS. 11A to 13B , which are variations of  FIG. 1 . 
     Furthermore, for the reason described in the first embodiment, the structures shown in  FIGS. 5 and 17A to 17C  have the advantageous effect of reducing the amount of electric power consumption. 
     Note that in the case of  FIG. 5( a ) , the width of the U-shaped part  5 U of the drain electrode  5  may be, but is not required to be, constant. Although the inner edge  5 UI needs to be in a U shape, the outer edge  5 UO is not required to be in a U shape. Furthermore, the width of the etching stopper layer  6 S may be, but is not required to be, constant. 
     The widths of the source electrode  4  and the column wiring  4 L are substantially the same as those in the thin film transistor array according to the first embodiment. 
     The thin film transistor array according to the third embodiment can be manufactured using substantially the same materials as those used to manufacture the thin film transistor array according to the first embodiment. 
     EXAMPLES 
     Example 1 
     A TFT array as shown in (a) in  FIG. 10A  to (e) in  FIG. 10C  was produced. As the first conductive layer, Mo was deposited on the insulating substrate (glass substrate)  1  by sputtering, and the gate electrode  2  and the row wiring  2 L were formed by photoresist coating, Mo etching, and resist stripping ((a) in  FIG. 10A ). Next, SiN was deposited as the gate insulating film  3 , amorphous Si was deposited as the semiconductor, n+amorphous Si was deposited as the contact layer, and the semiconductor pattern  6  was formed by resist coating, Si etching, and resist stripping ((b) in  FIG. 10A ). Furthermore, Mo was deposited as the second conductive layer, the source electrode  4 , the column wiring  4 L, the drain electrode  5 , the drain connecting wiring  5 C, and the drain pad  5 P were formed by resist coating, Mo etching, and resist stripping, and the contact layer on the channel region  6 C was removed by short-period Si etching ((c) in  FIG. 10B ). 
     SiN was deposited as the interlayer insulating film  7 , Mo was deposited as the third conductive layer, and the capacitor electrode  8  and the capacitor wiring  8 L were formed by resist coating, Mo etching, and resist stripping ((d) in  FIG. 10B ). Next, SiN was deposited as the capacitor insulating film  9 , an opening was formed in the capacitor insulating film  9  and the interlayer insulating film  7  by resist coating, SiN etching, and resist stripping, and then Mo was deposited as the fourth conductive layer, and the pixel electrode  10  was formed by resist coating, Mo etching, and resist stripping ((e) in  FIG. 10C ). 
     The area Sgs of overlap between the gate electrode and the source electrode was 126 μm 2 , the area Ssc of overlap between the source electrode and the capacitor electrode was 166 μm 2 , the area Ssp of overlap between the column wiring and the pixel electrode was 1016 μm 2 , the thickness Dgi of the gate insulating film  3  was 0.5 μm, the thickness Dil of the interlayer insulating film  7  was 1 μm, the thickness Dci of the capacitor insulating film  9  was 0.5 μm, and the relative dielectric constant of SiN is 7. Thus, Cgs=16 fF, Csc=10 fF, and Csp=42 fF. When the number of columns M=640, the number of rows N=480, and Vs=15 V, the amount of electric power consumed by the column wirings was 4.5 mJ per frame. 
     Example 2 
     A TFT array shown in (a) in  FIG. 14A  to (e) in  FIG. 14C  was produced. The method and material used to form each part were the same as those in Example 1. 
     The area Sgs of overlap between the gate electrode and the source electrode was 126 μm 2 , the area Ssc of overlap between the source electrode and the capacitor electrode was 166 μm 2 , the area Ssp of overlap between the column wiring and the pixel electrode was 1016 μm 2 , the thickness Dgi of the gate insulating film  3  was 0.5 the thickness Dil of the interlayer insulating film  7  was 1 the thickness Dci of the capacitor insulating film  9  was 0.5 and the relative dielectric constant of SiN is 7. Thus, Cgs=16 fF, Csc=10 fF, and Csp=42 fF. When the number of columns M=640, the number of rows N=480, and Vs=15 V, the amount of electric power consumed by the column wirings was 4.5 mJ per frame. 
     Example 3 
     A TFT array shown in (a) in  FIG. 15A  to (e) in  FIG. 15C  was produced. The method and material used to form each part were the same as those in Example 1. The area Sgs of overlap between the gate electrode and the source electrode was 142 μm 2 , the area Ssc of overlap between the source electrode and the capacitor electrode was 166 μm 2 , the area Ssp of overlap between the column wiring and the pixel electrode was 1016 μm 2 , the thickness Dgi of the gate insulating film  3  was 0.5 the thickness Dil of the interlayer insulating film  7  was 1 the thickness Dci of the capacitor insulating film  9  was  0 .5 and the relative dielectric constant of SiN is 7. Thus, Cgs=18 fF, Csc=10 fF, and Csp=42 fF. When the number of columns M=640, the number of rows N=480, and Vs=15 V, the amount of electric power consumed by the column wirings was 4.6 mJ per frame. 
     Example 4 
     A TFT array shown in (a) in  FIG. 16A  to (e) in  FIG. 16C  was produced. The method and material used to form each part were the same as those in Example 1. 
     The area Sgs of overlap between the gate electrode and the source electrode was 158 μm 2 , the area Ssc of overlap between the source electrode and the capacitor electrode was 166 μm 2 , the area Ssp of overlap between the column wiring and the pixel electrode was 1016 μm 2 , the thickness Dgi of the gate insulating film  3  was 0.5 μm, the thickness Dil of the interlayer insulating film  7  was 1 μm, the thickness Dci of the capacitor insulating film  9  was 0.5 μm, and the relative dielectric constant of SiN is 7. Thus, Cgs=20 fF, Csc=10 fF, and Csp=42 fF. When the number of columns M=640, the number of rows N=480, and Vs=15 V, the amount of electric power consumed by the column wirings was 4.8 mJ per frame. 
     Example 5 
     A TFT array shown in (a) in  FIG. 17A  to (e) in  FIG. 17C  was produced. As the first conductive layer, Mo was deposited on the insulating substrate (glass substrate)  1  by sputtering, and the gate electrode  2  and the row wiring  2 L were formed by photoresist coating, Mo etching, and resist stripping ((a) in  FIG. 17A ). Next, SiN was deposited as the gate insulating film  3 , amorphous Si was deposited as the semiconductor, SiN was deposited as the etching stopper layer, and the etching stopper layer  6 C was formed by resist coating, Si etching, and resist stripping ((b) in  FIG. 17A ). Furthermore, n+ amorphous Si was deposited as the contact layer, Mo was deposited as the second conductive layer, the source electrode  4 , the source connecting wiring  4 C, the column wiring  4 L, the drain electrode  5 , the drain connecting wiring  5 C, and the drain pad  5 P were formed by resist coating, Mo etching, Si etching, and resist stripping, and the semiconductors of the parts other than the etching stopper layer  6 S, the source electrode  4 , the source connecting wiring  4 C, the column wiring  4 L, the drain electrode  5 , and the drain connecting wiring  5 C were removed; thus, the semiconductor pattern  6  was obtained ((c) in  FIG. 17B ). 
     The method and material used to form each part after the interlayer insulating film  7  were the same as those in Example 1. 
     The area Sgs of overlap between the gate electrode and the source electrode was 233 μm 2 , the area Ssc of overlap between the source electrode and the capacitor electrode was 273 μm 2 , the area Ssp of overlap between the column wiring and the pixel electrode was 1016 μm 2 , the thickness Dgi of the gate insulating film  3  was 0.5 μm, the thickness Dil of the interlayer insulating film  7  was 1 μm, the thickness Dci of the capacitor insulating film  9  was 0.5 μm, and the relative dielectric constant of SiN is 7. Thus, Cgs=29 fF, Csc=17 fF, and Csp=42 fF. When the number of columns M=640, the number of rows N=480, and Vs=15 V, the amount of electric power consumed by the column wirings was 5.8 mJ per frame. 
     In the foregoing cases, each measurement was conducted using examples in which the bottom of the U shape of the drain electrode is round, is in the shape of a semicircle, and is concentric with the rounded tip of the source electrode, and the distance between the source electrode and the drain electrode is substantially constant not only on both sides of the straight part of the source electrode, but also at the tip part of the source electrode. However, as long as the distance between the source electrode and the drain electrode is substantially constant, substantially the same result can be obtained even in the embodiment shown in  FIGS. 6C to 6E  in which at least a portion of the bottom of the U shape of the drain electrode that faces the tip of the source electrode is not round and the tip of the source electrode is rectangular. 
     Comparative Example 
     The TFT array shown in  FIG. 1  with the drain electrode  5  changed to be linear and the source electrode  4  changed to be in the U shape as in the TFT array shown in  FIG. 21  was produced by substantially the same method as in Example 1. 
     The area Sgs of overlap between the gate electrode and the source electrode was 293 μm 2 , the area Ssc of overlap between the source electrode and the capacitor electrode was 317 μm 2 , the area Ssp of overlap between the column wiring and the pixel electrode was 1016 μm 2 , the thickness Dgi of the gate insulating film  3  was 0.5 μm, the thickness Dil of the interlayer insulating film  7  was 1 μm, the thickness Dci of the capacitor insulating film  9  was 0.5 μm, and the relative dielectric constant of SiN is 7. Thus, Cgs=36 fF, Csc=20 fF, and Csp=42 fF. When the number of columns M=640, the number of rows N=480, and Vs=15 V, the amount of electric power consumed by the column wirings was 6.5 mJ per frame. 
     The present application addresses the following. Displays can be categorized into a type rewriting data using power from an integral battery, and a type rewriting data by converting radio waves, from the reader/writer that rewrites data in the RFID device, into electric power and using the converted electric power. Either of these types has an issue of reducing power consumption during rewriting. In the case of displays incorporating batteries, the batteries are required to be frequently changed if power consumption is high. In displays using electric power from RF waves, if power consumption is high, rewriting can be performed only at short range over which radio signals are strong. Therefore, there is a demand for a thin film transistor array that consumes less power upon rewriting. 
     The present invention has an aspect to provide a thin film transistor array with reduced power consumption. 
     One aspect of the present invention for solving the aforementioned problem is a thin film transistor array including: an insulating substrate; a plurality of column wirings extending in a first direction on the insulating substrate and a plurality of row wirings extending in a second direction that is perpendicular to the first direction; and a plurality of pixels disposed on the insulating substrate and each including a thin film transistor and a pixel electrode, the plurality of pixels corresponding to crossing points of the plurality of column wirings and the plurality of row wirings, wherein the thin film transistors including respective gate electrodes, source electrodes, drain electrodes and semiconductor patterns, the source electrode is in a shape of a line having a constant width in plan view, the drain electrode includes a U-shaped part in a U shape surrounding the source electrode with a gap having a predetermined width therebetween in the plan view, the semiconductor pattern forms a channel region at least between the source electrode and the drain electrode, the gate electrode overlaps the channel region via a gate insulating film and includes the channel region in the plan view, and the source electrode is connected to one of the plurality of column wirings, the gate electrode is connected to one of the plurality of row wirings by a gate connecting wiring, and the drain electrode is connected to the pixel electrode by a drain connecting wiring. 
     According to embodiments of the present invention, a thin film transistor array having reduced power consumption can be provided. Specifically, using the present invention in displays enables a reduction in the power consumption during rewriting of the display device, enabling a reduction in the frequency of battery replacement for a display device of the type that includes an internal battery. Furthermore, the range at which displays of the type converting RF waves into electric power can be rewritten can be increased. 
     INDUSTRIAL APPLICABILITY 
     The embodiments of the present invention can be used in a display device such as electronic paper. 
     REFERENCE SIGNS LIST 
       1  . . . Insulating substrate 
       2  . . . Gate electrode 
       2 C . . . Gate connecting electrode 
       2 L . . . Row wiring 
       3  . . . Gate insulating film 
       4  . . . Source electrode 
       4 C . . . Source connecting electrode 
       4 L . . . Column wiring 
       5  . . . Drain electrode 
       5 U . . . U-shaped part of drain electrode 
       5 UI . . . Inner edge of drain electrode 
       5 UO . . . Outer edge of drain electrode 
       5 C . . . Drain connecting wiring 
       5 P . . . Drain pad 
       5 S . . . Drain sub-electrode 
       6  . . . Semiconductor pattern 
       6 C . . . Channel 
       6 U . . . U-shaped region of channel 
       6 S . . . Etching stopper layer 
       6 SI . . . Inner edge of etching stopper layer 
       6 SO . . . Outer edge of etching stopper layer 
       7  . . . Interlayer insulating film 
       8  . . . Capacitor electrode 
       8 L . . . Capacitor wiring 
       9  . . . Capacitor insulating film 
       10  . . . Pixel electrode 
     Obviously, numerous modifications and variations of the present invention are possible in light of the above teachings. It is therefore to be understood that within the scope of the appended claims, the invention may be practiced otherwise than as specifically described herein.