Patent Publication Number: US-11656297-B2

Title: Power electronic instrument for continuously monitoring stability and stabilizing a DC microgrid

Description:
CROSS-REFERENCES TO RELATED APPLICATIONS 
     This application claims the benefit of U.S. Provisional Patent Application No. 62/990,770 entitled “A POWER ELECTRONIC INSTRUMENT FOR CONTINUOUSLY MONITORING STABILITY AND STABILIZING A DC MICROGRID” and filed on Mar. 17, 2020 for Rohail Hassan, et al., which is incorporated herein by reference for all purposes. 
    
    
     FIELD 
     This invention relates to direct current (“DC”) microgrids and more particularly relates to stability control of DC microgrids. 
     BACKGROUND 
     Owing to the continued push towards electrified transportation and integration of renewables, the DC microgrids of the future are expected to be much more dynamic than they have been in the past. Future DC microgrids are expected to incorporate different kinds of sources such as renewable energy and fuel-based generators. They are expected to be reconfigurable, have bidirectional converters interfacing energy storage, and may have constant power, intermittent or plug and play loads. Examples of such systems can be found in all-electric aircraft, electric ships and DC fast charging stations and are expected to be configured as shown in  FIG.  1   . Stable operation of these microgrids is challenged by the negative incremental resistance behavior of the constant power loads as well as interactions among the controllers of the interconnected converters. 
     Traditional methods of designing the system to handle all possible scenarios lead to an overdesigned system including oversized filters and slow controllers. To avoid system overdesign, active stabilizing techniques and adaptive tuning techniques have been proposed. In some references, online measurements of system health or frequency response were used to auto-tune the digital controllers of the converters to improve transient performance and stability. In other references, an active stabilizer was proposed to add virtual damping in the system based on a measured oscillation frequency at the onset of instability. Application of these auto-tuning and active damping techniques requires online measurement of system impedances or system health, for which several methods have been proposed. 
     These methods typically use wide-band perturbation followed by a Fourier transform to measure impedances and derive the system stability or tuning parameters from them. Wideband perturbation have been proposed in some instances to measure alternating current (“AC”) grid impedance for adaptive control. Cross-correlation methods have also been proposed to find the input and output impedances of cascaded converters. A common drawback of the existing methods is that they are computationally intensive and, for microgrids with multiple sources and loads, require an additional converter to perform the analysis. 
     SUMMARY 
     An apparatus to monitor power system stability of a DC power system comprising a DC bus includes a switching power converter with a control loop. The switching power converter is connected to a direct current (“DC”) bus of a DC power system. The apparatus includes a monitoring loop injected into the control loop. The monitoring loop includes a sensor circuit configured to monitor voltage of the DC bus and current to the DC bus and a small signal injector configured to produce a periodic signal that includes a variable amplitude and a variable frequency and to inject the periodic signal on a reference signal of the control loop. The monitoring loop includes a stability measurement circuit configured to vary a frequency input to the small signal injector until a fundamental component of the periodic signal has a frequency equal to a system minor loop gain crossover frequency of an impedance ratio of a converter closed loop output impedance and an impedance of the DC power system. The impedance ratio is based on the monitored voltage and current. The monitoring loop includes a measurement output circuit configured to output a DC power system stability margin at the system minor loop gain crossover frequency. 
     Another apparatus for dynamic virtual impedance (“DVI”) includes a switching power converter with a control loop. The switching power converter is connected to a DC bus of a DC power system. A DVI loop is injected into the control loop. The DVI loop includes a sensor circuit configured to monitor voltage of the DC bus and current to the DC bus. The DVI loop includes a stability margin monitoring circuit configured to output a DC power system stability margin at the system minor loop gain crossover frequency. The DVI loop includes a DVI signal injector configured to inject a DVI signal onto the control loop based on the voltage of the DC bus or the current to the DC bus, the system minor loop gain crossover frequency and a stability margin error signal. The stability margin error signal includes a difference between the DC power system stability margin and a stability margin reference. The DVI signal emulates an impedance in parallel or series to an output of the switching power converter. 
     Another apparatus to monitor power system stability of a DC power system comprising a DC bus includes a switching power converter with a control loop. The switching power converter is connected to a DC bus of a DC power system. The apparatus includes a monitoring loop injected into the control loop. The monitoring loop includes a sensor circuit configured to monitor voltage of the DC bus and current to the DC bus and a small signal injector configured to produce a periodic signal with a variable amplitude and a variable frequency and to inject the periodic signal on a reference signal of the control loop. The monitoring loop includes a stability measurement circuit configured to vary a frequency input to the small signal injector until a fundamental component of the periodic signal has a frequency equal to a system minor loop gain crossover frequency of an impedance ratio of a converter closed loop output impedance and an impedance of the DC power system represented by a ratio of the monitored voltage of the DC bus and a DC power system voltage. 
     The DC power system voltage is replicated as a product of the monitored current to the DC bus and a model of an output impedance of the switching power converter. The stability measurement circuit derives a crossover error signal based on a difference between the monitored voltage of the DC bus and the DC power system voltage and the stability measurement circuit varies the frequency to the small signal injector until the fundamental component of the periodic signal has a frequency equal to a system minor loop gain crossover frequency by varying the frequency to the small signal injector based on the crossover error signal. The monitoring loop includes a measurement output circuit configured to output a DC power system stability margin at the system minor loop gain crossover frequency. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       In order that the advantages of the invention will be readily understood, a more particular description of the invention briefly described above will be rendered by reference to specific embodiments that are illustrated in the appended drawings. Understanding that these drawings depict only typical embodiments of the invention and are not therefore to be considered to be limiting of its scope, the invention will be described and explained with additional specificity and detail through the use of the accompanying drawings, in which: 
         FIG.  1    is a schematic block diagram of one embodiment representative future DC microgrid system; 
         FIG.  2    is a schematic block diagram of one embodiment of a generic DC microgrid showing an arbitrary system partitioning; 
         FIG.  3 A  is a schematic block diagram of one embodiment of a continuous stability margin monitor; 
         FIG.  3 B  is a schematic block diagram of another embodiment of a continuous stability margin monitor; 
         FIG.  3 C  is a schematic block diagram of a) an embodiment of a differential error and compensator and b) an alternate embodiment of a ratio error and compensator for the continuous stability margin monitor of  FIG.  3 A ; 
         FIG.  4    is a schematic block diagram of one embodiment of a waveform of the current reference with square-wave perturbation; 
         FIG.  5    is a schematic block diagram of one embodiment of a hardware setup system diagram; 
         FIG.  6    is a frequency response of the envelope models: (a) f inj  loop and, (b) amplitude loop; 
         FIG.  7 A  is a Bode plot of Z ESC  and Z away,ESC  for load converter powers from 0 W to 30 W; 
         FIG.  7 B  is a Nyquist plots of the system minor loop gain for load converter powers from 0 W to 30 W; 
         FIG.  7 C  is a Bode plot indicating measurement of the system phase margin; 
         FIG.  8    is DC bus voltage, ESC current input from DC bus, system crossover frequency and system phase margin during initialization of the continuous monitor; 
         FIG.  9    is DC bus voltage, load converter input current, system crossover frequency and system phase margin during load transient; 
         FIG.  10    is a comparison of the experimental performance of the continuous monitor with theoretical analysis results; 
         FIG.  11    is a schematic block diagram of one embodiment of dynamic virtual impedance; (a) concept and (b) a Bode plot of an implementation example indicating how parameters affect the dynamic virtual impedance; and 
         FIG.  12    is a schematic block diagram of one embodiment of dynamic virtual impedance (“DVI”). 
     
    
    
     DETAILED DESCRIPTION 
     Reference throughout this specification to “one embodiment,” “an embodiment,” or similar language means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, appearances of the phrases “in one embodiment,” “in an embodiment,” and similar language throughout this specification may, but do not necessarily, all refer to the same embodiment, but mean “one or more but not all embodiments” unless expressly specified otherwise. The terms “including,” “comprising,” “having,” and variations thereof mean “including but not limited to” unless expressly specified otherwise. An enumerated listing of items does not imply that any or all of the items are mutually exclusive and/or mutually inclusive, unless expressly specified otherwise. The terms “a,” “an,” and “the” also refer to “one or more” unless expressly specified otherwise. 
     Furthermore, the described features, structures, or characteristics of the invention may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided, such as examples of programming, software modules, user selections, network transactions, database queries, database structures, hardware modules, hardware circuits, hardware chips, etc., to provide a thorough understanding of embodiments of the invention. One skilled in the relevant art will recognize, however, that the invention may be practiced without one or more of the specific details, or with other methods, components, materials, and so forth. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the invention. 
     The schematic flow chart diagrams included herein are generally set forth as logical flow chart diagrams. As such, the depicted order and labeled steps are indicative of one embodiment of the presented method. Other steps and methods may be conceived that are equivalent in function, logic, or effect to one or more steps, or portions thereof, of the illustrated method. Additionally, the format and symbols employed are provided to explain the logical steps of the method and are understood not to limit the scope of the method. Although various arrow types and line types may be employed in the flow chart diagrams, they are understood not to limit the scope of the corresponding method. Indeed, some arrows or other connectors may be used to indicate only the logical flow of the method. For instance, an arrow may indicate a waiting or monitoring period of unspecified duration between enumerated steps of the depicted method. Additionally, the order in which a particular method occurs may or may not strictly adhere to the order of the corresponding steps shown. 
     Although various arrow types and line types may be employed in the flowchart and/or block diagrams, they are understood not to limit the scope of the corresponding embodiments. Indeed, some arrows or other connectors may be used to indicate only the logical flow of the depicted embodiment. For instance, an arrow may indicate a waiting or monitoring period of unspecified duration between enumerated steps of the depicted embodiment. It will also be noted that each block of the block diagrams and/or flowchart diagrams, and combinations of blocks in the block diagrams and/or flowchart diagrams, can be implemented by special purpose hardware-based systems that perform the specified functions or acts, or combinations of special purpose hardware and program code. 
     As used herein, a list with a conjunction of “and/or” includes any single item in the list or a combination of items in the list. For example, a list of A, B and/or C includes only A, only B, only C, a combination of A and B, a combination of B and C, a combination of A and C or a combination of A, B and C. As used herein, a list using the terminology “one or more of” includes any single item in the list or a combination of items in the list. For example, one or more of A, B and C includes only A, only B, only C, a combination of A and B, a combination of B and C, a combination of A and C or a combination of A, B and C. As used herein, a list using the terminology “one of” includes one and only one of any single item in the list. For example, “one of A, B and C” includes only A, only B or only C and excludes combinations of A, B and C. As used herein, “a member selected from the group consisting of A, B, and C,” includes one and only one of A, B, or C, and excludes combinations of A, B, and C.” As used herein, “a member selected from the group consisting of A, B, and C and combinations thereof” includes only A, only B, only C, a combination of A and B, a combination of B and C, a combination of A and C or a combination of A, B and C. 
     An apparatus to monitor power system stability of a DC power system comprising a DC bus includes a switching power converter with a control loop. The switching power converter is connected to a direct current (“DC”) bus of a DC power system. The apparatus includes a monitoring loop injected into the control loop. The monitoring loop includes a sensor circuit configured to monitor voltage of the DC bus and current to the DC bus and a small signal injector configured to produce a periodic signal that includes a variable amplitude and a variable frequency and to inject the periodic signal on a reference signal of the control loop. The monitoring loop includes a stability measurement circuit configured to vary a frequency input to the small signal injector until a fundamental component of the periodic signal has a frequency equal to a system minor loop gain crossover frequency of an impedance ratio of a converter closed loop output impedance and an impedance of the DC power system. The impedance ratio is based on the monitored voltage and current. The monitoring loop includes a measurement output circuit configured to output a DC power system stability margin at the system minor loop gain crossover frequency. 
     In some embodiments, the monitored current to the DC bus equals output current from the switching power converter such that a ratio of the converter closed loop output impedance and the impedance of the DC power system is represented by a ratio of the monitored voltage of the DC bus and a DC power system voltage. The stability measurement circuit derives the DC power system voltage by multiplying the monitored current to the DC bus by a model of an output impedance of the switching power converter. 
     In other embodiments, the system minor loop gain crossover frequency occurs when the monitored voltage of the DC bus equals the DC power system voltage and the stability measurement circuit derives a crossover error signal based on a difference between the monitored voltage of the DC bus and the DC power system voltage. The stability measurement circuit varies the frequency to the small signal injector until the fundamental component of the periodic signal has a frequency equal to the system minor loop gain crossover frequency by varying the frequency to the small signal injector based on the crossover error signal. In other embodiments, the measurement output circuit derives the DC power system stability margin as a difference between 180 degrees and a phase shift between the monitored voltage of the DC bus and the DC power system voltage. In other embodiments, the stability measurement circuit derives the crossover error signal based on a difference between a peak value of the monitored voltage of the DC bus and a peak value of the DC power system voltage. 
     In some embodiments, the stability measurement circuit includes an amplitude monitoring circuit configured to maintain an amplitude of the monitoring loop at an amplitude reference value. In other embodiments, the small signal injector varies the amplitude of the periodic signal in response to an amplitude error signal from the amplitude monitoring circuit and the amplitude monitoring circuit varies the amplitude error signal as a function of the amplitude reference value and the monitored voltage of the DC bus. In other embodiments, the periodic signal includes a sinusoidal waveform or a square waveform. In other embodiments, the stability measurement circuit includes a voltage bandpass filter configured to output the monitored voltage of the DC bus at the system minor loop gain crossover frequency and a current bandpass filter configured to output the monitored current to the DC bus at the system minor loop gain crossover frequency. 
     Another apparatus for dynamic virtual impedance (“DVI”) includes a switching power converter with a control loop. The switching power converter is connected to a DC bus of a DC power system. A DVI loop is injected into the control loop. The DVI loop includes a sensor circuit configured to monitor voltage of the DC bus and current to the DC bus. The DVI loop includes a stability margin monitoring circuit configured to output a DC power system stability margin at a system minor loop gain crossover frequency. The DVI loop includes a DVI signal injector configured to inject a DVI signal onto the control loop based on the voltage of the DC bus or the current to the DC bus, the system minor loop gain crossover frequency and a stability margin error signal. The stability margin error signal includes a difference between the DC power system stability margin and a stability margin reference. The DVI signal emulates an impedance in parallel or series to an output of the switching power converter. 
     In some embodiments, the apparatus includes a stability tuning circuit configured to continuously tune a center frequency, an amplitude at the center frequency and/or a width of an impedance flat region of the emulated impedance. In other embodiments, the stability tuning circuit continuously tunes the center frequency in response to changes to the system minor loop gain crossover frequency and the stability tuning circuit continuously tunes the amplitude at the center frequency in response to the stability margin error. 
     In some embodiments, the stability margin monitoring circuit includes a small signal injector configured to produce a periodic signal with a variable amplitude and a variable frequency and to inject the periodic signal on a reference signal of the control loop. In the embodiment, the stability margin monitoring circuit includes a stability measurement circuit configured to vary a frequency input to the small signal injector until a fundamental component of the periodic signal has a frequency equal to the system minor loop gain crossover frequency of an impedance ratio of a converter closed loop output impedance and an impedance of the DC power system. The impedance ratio is based on the monitored voltage and current. 
     In other embodiments, the monitored current to the DC bus equals output current from the switching power converter such that a ratio of the converter closed loop output impedance and the impedance of the DC power system is represented by a ratio of the monitored voltage of the DC bus and a DC power system voltage. The stability measurement circuit derives the DC power system voltage by multiplying the monitored current to the DC bus by a model of an output impedance of the switching power converter. In other embodiments, the system minor loop gain crossover frequency occurs when the monitored voltage of the DC bus equals the DC power system voltage and the stability measurement circuit derives a crossover error signal based on a difference between the monitored voltage of the DC bus and the DC power system voltage. The stability measurement circuit varies the frequency to the small signal injector until the fundamental component of the periodic signal has a frequency equal to the system minor loop gain crossover frequency by varying the frequency to the small signal injector based on the crossover error signal. 
     In some embodiments, the impedance emulated by the DVI signal includes an inductance-resistance-capacitance circuit with a center frequency at the system minor loop gain crossover frequency with a capacitance characteristic at low frequency and an inductance characteristic at high frequency and the center frequency is a resonant frequency of the inductance and capacitance. In other embodiments, the control loop is a current control loop and the DVI signal is a current injection signal derived by multiplying the monitored voltage of the DC bus by a reciprocal of a DVI impedance defined as: 
               1       Z   vi     ⁡     (   s   )         =       s   ⁢         (     2   ⁢   π   ⁢           ⁢   f     )     ⁢     b       r           s   2     +       s   ⁡     (     2   ⁢   π   ⁢           ⁢   f     )       ⁢     b       +       (     2   ⁢   π   ⁢           ⁢   f     )     2               
where:
 
     r is the control output emulating a virtual resistance, 
     f is the system minor loop gain crossover frequency, 
     b is a parameter to modify the frequency of DVI, 
     s is a LaPlace variable, and 
     Z vi (s) is the DVI impedance. 
     Another apparatus to monitor power system stability of a DC power system comprising a DC bus includes a switching power converter with a control loop. The switching power converter is connected to a DC bus of a DC power system. The apparatus includes a monitoring loop injected into the control loop. The monitoring loop includes a sensor circuit configured to monitor voltage of the DC bus and current to the DC bus and a small signal injector configured to produce a periodic signal with a variable amplitude and a variable frequency and to inject the periodic signal on a reference signal of the control loop. The monitoring loop includes a stability measurement circuit configured to vary a frequency input to the small signal injector until a fundamental component of the periodic signal has a frequency equal to a system minor loop gain crossover frequency of an impedance ratio of a converter closed loop output impedance and an impedance of the DC power system represented by a ratio of the monitored voltage of the DC bus and a DC power system voltage. 
     The DC power system voltage is replicated as a product of the monitored current to the DC bus and a model of an output impedance of the switching power converter. The stability measurement circuit derives a crossover error signal based on a difference between the monitored voltage of the DC bus and the DC power system voltage and the stability measurement circuit varies the frequency to the small signal injector until the fundamental component of the periodic signal has a frequency equal to the system minor loop gain crossover frequency by varying the frequency to the small signal injector based on the crossover error signal. The monitoring loop includes a measurement output circuit configured to output a DC power system stability margin at the system minor loop gain crossover frequency. 
     In some embodiments, the apparatus includes a DVI signal injector configured to inject a DVI signal onto the control loop based on the voltage of the DC bus or the current to the DC bus, the system minor loop gain crossover frequency and a stability margin error signal. The stability margin error includes a difference between the DC power system stability margin and a stability margin reference. The DVI signal emulates an impedance in series or parallel to an output of the switching power converter. In other embodiments, the apparatus includes a stability tuning circuit configured to continuously tune a center frequency, an amplitude at the center frequency and/or a width of an impedance flat region of the emulated impedance. The stability tuning circuit continuously tunes the center frequency in response to changes to the system minor loop gain crossover frequency and wherein the stability tuning circuit continuously tunes the amplitude at the center frequency in response to the stability margin error. 
     A novel system stability monitor is presented herein which can be added onto any existing converter in the system as an auxiliary function and that continuously monitors the stability margin of the interconnected system. The stability margin evaluation is enabled by Nodal Stability Analysis which is a generalized impedance-based stability analysis method especially suited for dynamic DC microgrids with various interconnected sources, loads and bidirectional converters. The monitor itself is a continuous monitoring method developed to monitor the phase margin of a converter loop gain. The proposed continuous monitor injects a controlled single-frequency perturbation using one of the converters already in the system, with a small amplitude that does not affect the normal operation. The proposed method can be used in any interconnected system for proactively monitoring and maintaining the system stability, and its continuous nature would enable development of new techniques in adaptive stability enhancement of DC microgrids. 
     Nodal Stability Analysis 
     The proposed continuous system stability monitoring technique evaluates stability using measurements at the terminal of the converter that incorporates it. The approach relies on measurements directly available to the converter, namely the DC link voltage at its output and its own output current. This data provides information about the system impedance as seen from the output terminals of the monitoring converter. The proposed approach uses impedance-based stability analysis to evaluate the stability margin. However, the monitoring converter cannot divide the system into source and load subsystems as required by traditional impedance-based stability analysis methods. This is because the impedance that the monitoring converter sees is the parallel combination of all sources, loads and bidirectional converters connected in the system and there is no way for it to distinguish sources from loads in the impedance measurement at its output terminals. 
     Hence, traditional methods cannot be used with the proposed monitor. The Nodal Stability Analysis summarized here presents an impedance-based analysis method that does not require identification or grouping of sources and loads, making it the ideal candidate for such applications. 
     Consider a DC microgrid comprising n converters connected to a common DC bus, as shown in  FIG.  2   , where all converters are represented by their Thevenin equivalent. The small-signal DC bus voltage is given by: 
                       V   bus     =       (       ∑     i   =   1     n     ⁢           ⁢       v   i       z   oi         )     ⁢     Z   bus         ,           (   1   )               
where:
 
 Z   bus =( Z   o1   /Zo 2// . . . // Z   on ),  (2)
 
     All variables in equations (1) and (2) are functions of the Laplace variable s, V i  and Z oi  are the Thevenin equivalent voltage and output impedance of the i-th converter, respectively, and Z bus  is the overall bus impedance from the parallel combination of all the converter output impedances. Assuming the converters are individually stable when connected to an ideal DC bus, the system stability is given by the stability of Z bus . The stability of the DC bus impedance Z bus  is determined by expanding equation (2). One such expansion of Z bus  is given by: 
     
       
         
           
             
               
                 
                   
                     
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     where Z away,1  is the parallel combination of all converter impedances except Z ol . The expansion shown in equation (3) corresponds to partitioning the system at the terminal of the arbitrary converter  1 , as shown in  FIG.  2   . Equation (3) shows Z bus  expressed in the form of a closed loop system representing interactions of all the interconnected converters and with a minor loop gain represented by the ratio of the output impedance Z ol  and the impedance of the rest of the system, Z away,I . From equation (3), the DC bus impedance is stable if the minor loop gain Z ol /Z away,I  satisfies the Nyquist stability criterion. 
     It is shown through hardware results that the minor loop gain Z o /Z away  can be evaluated at the terminal of any converter in the system, and it is not necessary to group or identify source and load converters in Z away  to perform the analysis. This property is utilized herein to develop the continuous monitoring technique which evaluates the system stability by continuously measuring the crossover frequency and phase margin of the minor loop gain given by the ratio of Z o  to Z away . 
     Continuous Stability Margin Monitor 
     From equation (3), the minor loop gain of the microgrid system is given by Z o /Z away . If both impedances are perturbed using the same current perturbation i o , then the minor loop gain can be written as: 
                       Minor   ⁢           ⁢   loop   ⁢           ⁢   gain     =         z   o       z   away       =           v   s     ⁢     I   o           v   o     ⁢     I   o         =       v   s       v   o             ,           (   4   )               
where v s  is the response of Z o  and v o  is the response of Z away , to i o . Utilizing the freedom of system partitioning, any converter in the system can be assigned the monitoring task. Typically, converters are switching power converters that include a control loop. The switching power converters contemplated herein have a DC output and are connected to a DC bus. The input to the switching power converters may be alternating current (“AC”) or DC. The control loop generally controls switching in the switching power converters. As used herein, a switching power converter may be called a converter.
 
     The converter assigned to stability monitoring would inject a current perturbation in the system and directly measure v o  (the response of Z away ) and i o , as indicated in the overall schematic of the continuous monitor in  FIGS.  3 A and  3 B . The measured i o  is then used with the analytical model of the converter output impedance to calculate v s . With v s  and v o , the system stability margin can be determined since the frequency at which the amplitudes of v s  and v o  match is the minor loop gain crossover frequency, and the phase margin of the minor loop gain is the phase difference of v s  and v o  at that minor loop gain crossover frequency. 
       FIG.  3 A  is a schematic block diagram of one embodiment of a continuous stability margin monitor. The sine-wave generator injects a small sine wave onto a reference signal where the frequency of the sine wave has a variable injection frequency f inj  and amplitude A. The injection frequency f inj  is adjusted to match the minor loop gain crossover frequency, which occurs when v ofp  matches v sfp  where v ofp  is a representation of the voltage of the switching power converter and v sfp  is a voltage transformation of the output current i o . The amplitude A is controlled to match a reference amplitude A ref . 
       FIG.  3 B  is a schematic block diagram of another embodiment of a continuous stability margin monitor.  FIG.  3 B  is a particular implementation of the continuous stability monitor of  FIG.  3 A  that determines when v ofp  matches v sfp  by determining a difference between v ofp  and v sfp  and by determining the amplitude input A by determining a difference between v ofp  and A ref .  FIG.  3 B  includes a square wave pulse generator, which is typically less expensive than a sine wave generator. A sine wave generator may also be used with the circuit of  FIG.  3 B . 
     The sine wave generator of  FIG.  3 A  and the pulse generator of  FIG.  3 B  E, are small signal injectors that produce a periodic signal comprising a variable amplitude and a variable frequency and to inject the periodic signal on a reference signal of the control loop. Typically, the amplitude of the period signal is large enough to be detected above ambient noise but is much smaller than an amplitude of the reference signal upon which the periodic signal is injected. 
       FIG.  3 C  is a schematic block diagram of a) an embodiment of a differential error and compensator and b) an alternate embodiment of a ratio error and compensator for the continuous stability margin monitor of  FIG.  3 A . The differential error and compensator in  FIG.  3 C  (a) is similar to  FIG.  3 B . The f inj  integrator is compensation term for the injection frequency input f inj  and the amplitude integrator is a compensation term for the amplitude input A. 
     In  FIGS.  3 A and  3 B , a monitoring loop is injected into the control loop of the switching power converter where the injection point is the summation block of the reference signal and an injected signal. In  FIGS.  3 A and  3 B , the control loop is a current control loop and the monitoring loop injects a current signal i inj  onto the current reference signal i ref 0 . In other embodiments, the control loop is a voltage loop and the monitoring loop is injected onto a voltage reference signal. 
     The monitoring loop includes a sensor circuit configured to monitor voltage of the DC bus v o  and current to the DC bus i o . Typically, the sensor circuit monitors voltage of the DC bus v o  with a connection to a positive output terminal of the output bus and monitors current of the DC bus i o  with a current sensor. The current sensor may be a resistor, a hall effect sensor, or other current sensor suitable for monitoring DC current. 
     The monitoring loop includes a small signal injector, a stability measurement circuit and a measurement output circuit. The small signal injector is configured to produce a periodic signal comprising a variable amplitude and a variable frequency and is configured to inject the periodic signal on the reference signal of the control loop. The stability measurement circuit is configured to vary a frequency input to the small signal injector until a fundamental component of the periodic signal has a frequency equal to a system minor loop gain crossover frequency of an impedance ratio of a converter closed loop output impedance Z o  and an impedance of the DC power system Z away . The impedance ratio is based on the monitored voltage v o  and current i o  of the DC bus. The measurement output circuit is configured to output a DC power system stability margin PM sys  at the system minor loop gain crossover frequency f inj . 
     As in equation (4), the monitored current to the DC bus equals output current from the switching power converter i o  such that a ratio of the converter closed loop output impedance Z o  and the impedance of the DC power system Z away  is represented by a ratio of the monitored voltage of the DC bus v o  and a DC power system voltage v s . The stability measurement circuit derives the DC power system voltage v s  by multiplying the monitored current to the DC bus i o  by a model of an output impedance of the switching power converter Z o  (s), which is described further below. 
     A. Injection and Response Filtering. 
     As shown in  FIG.  3 B , a small signal injector in the form of a pulse generator outputs a square wave current reference i inj  with frequency f inj  and amplitude ±A, which is added on top of the base current reference i ref0  and fed into the converter output current controller. The overall current reference, i ref , looks like that shown in  FIG.  4   . The stability measurement circuit in  FIG.  3 B  includes the circuitry feeding the pulse generator. In some embodiments, the stability measurement circuit includes a voltage bandpass filter configured to output the monitored voltage of the DC bus v o  at the system minor loop gain crossover frequency f inj  and a current bandpass filter configured to output the monitored current to the DC bus i o  at the system minor loop gain crossover frequency f inj . 
     The resulting i o  from the converter and the response voltage v o  are measured and fed into a voltage bandpass filter tuned at the injection frequency f inj . Each bandpass filter is made online tunable and is of the form: 
                         G   bp     ⁡     (   s   )       =         (       2   ⁢   π   ⁢           ⁢     f   inj       Q     )     ⁢   s         s   2     +         2   ⁢   π   ⁢           ⁢     f   inj       Q     ⁢   s     +       (     2   ⁢   π   ⁢           ⁢     f   inj       )     2           ,           (   5   )               
where Q is the quality factor of the filter (usually set high), and f inj  is the same frequency at which i inj  is generated. The dynamic parameter f inj  in equation (5) requires that the parameters of the voltage bandpass filters be evaluated continuously as f inj  changes, making it helpful if the rate of change of f inj  be much smaller than the value of f inj . The outputs of the bandpass filters, i of  and v of , contain only the frequency component of i o  at f inj  and its response to Z away  respectively. Filtered current, i of  is then fed into the analytical model of Z o  to calculate v sf . The model of Z o  (labeled z o (s) in  FIG.  3 B ) is based the topology of the converter (labeled “converter power stage” in  FIG.  3 B ). Z o  is a frequency dependent function. In some embodiments, Z o  is frequency dependent for a range of frequencies above and below an expected f inj .
 
     In some embodiments the stability measurement circuit includes a peak-detection algorithm (e.g. envelope detectors in  FIG.  3 B ) to find the peak-to-peak amplitudes of v of  and v sf  at the injection frequency f inj , given by v ofp  and v sfp . The error between v ofp  and v sfp  is integrated to find the frequency where the error is zero, i.e. where v sfp =v ofp . For example, as depicted in  FIG.  3 B , an output of a summation block v env,err  that subtracts v ofp  from v sfp  is fed into a compensation block that may include an integrator. In various embodiments, the f inj  integrator is a proportional-integral (“PI”) control, a proportional-integral-derivative (“PID”) control, or the like. Likewise the amplitude integrator may be a proportional-integral (“PI”) control, a proportional-integral-derivative (“PID”) control, or the like. 
     B. Injection Control and Phase Margin Evaluation. 
     The stability measurement circuit includes an amplitude monitoring circuit configured to maintain an amplitude A of the monitoring loop at an amplitude reference value A ref . It is desirable to limit the amplitude of the voltage perturbation resulting from the injected current, and also to make sure that the response is detectable. To achieve that, the amplitude of voltage perturbation, v ofp , is compared to a reference amplitude A ref  and fed into a slow integrator or other suitable compensator which outputs the amplitude of the current injection A. From equation (4), the goal is to inject a perturbation at the impedance crossover frequency where v sfp =v ofp . This allows us to define a feedback error (crossover error signal):
 
 v   env,err   =v   sfp   −v   ofp   (6)
 
which is integrated, in one embodiment, to output the injection frequency f inj . The f inj  integrator (also called the frequency integrator) or other suitable compensation changes the injection frequency until it reaches the impedance crossover frequency. Correct operation of this frequency integrator requires the correct sign of the error to be used and, in some embodiments, a good estimate for the integrator initial condition is also used, which can be estimated from analytical models or a one-time measurement using a frequency sweep or other wide-band methods. According to equation (4), as the error of equation (6) goes to zero, the injection frequency, f inj , will converge to the crossover frequency of the minor loop gain equation (4), and given by
 
 f   c,sys   =f   inj | f     in,j,err     =0 ,  (7)
 
here f c,sys  is the minor loop gain crossover frequency. Also, when equation (6) goes to zero, the system phase margin, hereby called PM sys , is proportional to the phase difference between v of  and v sf , and is given by:
 
 PM   sys =180(1−2Δ t   zc   f   inj )| f     env,err     =0 ,  (8)
 
where Δ tzc  is the time difference between the zero crossings of v sf  and v of .
 
     Thus, the measurement output circuit is configured to output this DC power system stability margin PM sys  at the system minor loop gain crossover frequency f inj . The measurement output circuit derives the DC power system stability margin PM sys  as a difference between 180 degrees and a phase shift between the monitored voltage of the DC bus v o  and the DC power system voltage v s . 
     Analysis and Design of the Continuous Monitor 
     This section discusses modeling of the dynamics of the continuous monitor and the design of its two controllers, namely the f inj  integrator and amplitude integrator. An experimental setup from which the models are derived is discussed before the modeling of the monitor dynamics themselves. 
     A. Hardware Test Setup. 
     To validate the proposed stability margin monitor, a test setup emulating essential parts of a DC microgrid, namely a source converter, a load converter and a bidirectional converter (emulating an energy storage interface) was built as shown in  FIG.  5   . All converters in  FIG.  5    are synchronous buck converters which are chosen for their well understood behavior and impedance models. The source converter and the load converter are each rated for 100 W and have the same control structure as in some references. The source converter has an inner current control loop regulating its output current and an outer voltage controller with droop. The load converter regulates the voltage at its own output, thereby appearing as a constant power load to the DC bus. The impedance models of the source and the load converters are same as in some references. 
     An energy storage converter (“ESC”), as depicted in  FIG.  5   , is chosen as the continuous monitor of the system. The control structure for the ESC is as shown in  FIG.  3 B . The ESC regulates its output current with a constant reference while an injected signal is added on top of the constant current reference. The impedance model of the ESC is given by: 
     
       
         
           
             
               
                 
                   
                     
                       Z 
                       ESC 
                     
                     = 
                     
                       
                         
                           z 
                           L 
                         
                         + 
                         
                           
                             v 
                             in 
                           
                           ⁢ 
                           
                             G 
                             ci 
                           
                         
                       
                       
                         1 
                         + 
                         
                           
                             z 
                             L 
                           
                           
                             z 
                             C 
                           
                         
                       
                     
                   
                   , 
                 
               
               
                 
                   ( 
                   9 
                   ) 
                 
               
             
           
         
       
     
     where V in  is the input voltage of the ESC, G ci  is the current controller, Z L  is the impedance of the inductor of the synchronous buck including its ESR, and Z c  is the impedance of the output shunt filter branch. To evaluate the system stability, the following minor loop gain is evaluated, 
                       Minor   ⁢           ⁢   Loop   ⁢           ⁢   Gain     =         z   ESC       z     away   ,   ESC         =         z   ESC         z   sc     //     z   Load         =       v   sf       v   of             ,           (   10   )               
where Z sc  is the impedance of the source converter while Zion is the impedance of the load converter. The parallel combination of the source and load converter impedances is seen by the ESC. The controller bandwidths of the three converters are listed in Table 1 below.
 
                     TABLE I                  Control Parameters of Converters In Test Setup                                         Current control   Voltage control   Droop               bandwidth (Hz)   bandwidth (Hz)   Resistance                                                 Source   1000   500   0.0194           Converter                       Bidirectional   2000   N/A   N/A           ESC                       Load   N/A   160   N/A           Converter                        
To help in validating the proposed monitor over a wide operation range, the parameters are intentionally chosen such that the system crossover frequency and phase margin changes significantly as the load converter increases its power.
 
B. Modeling of the Continuous Monitor Dynamics.
 
     Following an approach similar to other references, we can find the transfer function from f inj  to envelope error, i.e.: 
                         G       f     in   ⁢        j       ,     v   err         (     j   ⁢     ω   m       )     =           V   ^       env   ,   err       (     j   ⁢     ω   m       )           f   ^       in   ⁢   j       (     j   ⁢     ω   m       )         ,           (   11   )               
where v env,err  is given by equation (6). Similar to other references, the overall transfer function of equation (11) can be evaluated by evaluating the difference of two transfer functions:
 
                         G       f     in   ⁢        j       ,     v     s   ,   env           (     j   ⁢     ω   m       )     =           V   ^       s   ,   env       (     j   ⁢     ω   m       )           f   ^       in   ⁢        j       (     j   ⁢     ω   m       )         ,           (   12   )                         and                                       G       f     in   ⁢        j       ,     v     o   ,   env           (     j   ⁢     ω   m       )     =           V   ^       o   ,   env       (     j   ⁢     ω   m       )           f   ^       in   ⁢        j       (     j   ⁢     ω   m       )         ,           (   13   )               
where v s,env  represents the small-signal variations in v sfp  and v o,env  represents the small-signal variations in v ofp . The overall transfer function is then found as:
 
 G   f     inj     ,v   err ( j ω)= G   f     inj     ,v     s,env   ( j ω) G   f     inj     ,v     o,env   ( j ω),  (14)
 
     The derivation of the envelope dynamics treats the small-signal variations in frequency as frequency modulation of the square wave generation, filtered by the bandpass filter of equation (5). It can be shown that equations (12) and (13) can be evaluated as: 
                         G       f     in   ⁢   j       ,     v   env         (     j   ⁢     ω   m       )     =         4   ⁢     V   in       π     ⁢           A   0     ⁢     A   l   *       +       A   o   *     ⁢     A   u                A   0                ,           (   15   )                             where   ⁢           A   0       ,       A   l     ⁢         and   ⁢           A   u     ⁢         are   ⁢         defined   ⁢           as   :                                           A   0     =       G   plant     (     j   ⁢     ω   m       )       ,   
       A   l     =       -     1     2   ⁢     w   m           ⁢       G   plant     [     j   ⁡   (       ω     in   ⁢   j       -     ω   m       )     ]         ,   
       A   u     =       1     2   ⁢     w   m         ⁢         G   plant     [     j   ⁢     (       ω     in   ⁢   j       +     ω   m       )       ]     .                 (   16   )               
For evaluating equation (12), G plant (jwm)  in equation (16) is given by:
 
 G   plant,v     s   ( jω   m )= G   i,ESC ( jω   m ) Z   ESC ( jω   m ) G   bp ( jω   m ),  (17)
 
where G i,ESC  (jω m ) is the closed loop current transfer function of ESC. For evaluating (13), G plant  (jω m ) in (16) is given by:
 
 G   plant,v     o   ( jω   m )= G   i,ESC ( jω   m ) Z   away,ESC ( jω   m ) G   bp ( jω   m ),  (18)
 
The dynamics of the perturbation amplitude control loop are also derived by following a reference, which treats the small-signal variations in A as amplitude modulation. It can be shown that for the square wave perturbation of  FIG.  3 B  the amplitude loop has the transfer function:
 
     
       
         
           
             
               
                 
                   
                     
                       
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                   ( 
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                   where 
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     For the hardware setup described in above, the frequency response of the f inj  loop and amplitude loop models were evaluated with an estimated system crossover frequency, f c,sys , of 168 Hz and a perturbation amplitude A of 63 mA. The responses are shown in  FIG.  6   . It is evident from  FIG.  6    that the transfer functions exhibit low pass filter characteristics with a dominant pole pair which is highly damped. C. Design of the Monitor Controllers. 
     Unlike designing the controller for monitoring a converter loop gain other references, our goal is to design the controllers for monitoring the minor loop gain of a dynamic system that has multiple converters and whose impedance changes with operating point. We cannot, therefore, rely on complete models for our design as we are not assuming that Z away  is known. Hence, we would like to simplify the small-signal models developed above and derive a measurement-based strategy to design the monitor controllers. From above analysis, both the amplitude loop and the frequency loop exhibit low-pass filter characteristics and a dominant pole with a pole frequency of: 
                       ω   1     =         ω   inj   2     -     2   ⁢     ω   inj     ⁢     ω   0     ⁢       1   +     1     2   ⁢     Q   2               +     ω   0   2           ,           (   22   )               
where ω 0  is the resonant frequency of the bandpass filter, Q is the quality factor of the bandpass filter and ω 1  is the pole frequency of the dominant pole pair. In the continuous monitor presented here, the bandpass filter resonant frequency is the same as the injection frequency such that ω inj =ω 0 , so the frequency of the dominant pole-pair for the continuous monitor becomes
 
     
       
         
           
             
               
                 
                   
                     
                       ω 
                       1 
                     
                     = 
                     
                       
                         2 
                       
                       ⁢ 
                       
                         ω 
                         inj 
                       
                       ⁢ 
                       
                         
                           1 
                           - 
                           
                             
                               1 
                               - 
                               
                                 1 
                                 
                                   4 
                                   ⁢ 
                                   
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                   , 
                 
               
               
                 
                   ( 
                   23 
                   ) 
                 
               
             
           
         
       
     
     Equation (23) shows that the dominant pole frequency is linearly dependent on f inj  and that it reduces with increasing Q. While a high Q is desired to extract the single frequency component at f inj , a very high Q cannot be used as it would place Wi at a low frequency, reducing the achievable bandwidth for the monitor controllers. In the circuit of  FIG.  5   , a Q of 5 was used. The DC gain of the f inj  loop is proportional to the slope of G plant  in equation (16) and is given by: 
                       G     f       in   ⁢   j     ,   0         =           4   ⁢   A     π     ⁢       (     δ   ⁢            G   plant     (     j   ⁢   ω     )            )     δω         ❘     ω   =     ω   inj             ,           (   24   )               
where:
 
 G   plant ( j ω)= G   plant,v     s   ( j ω)− G   plant,v     0   ( j ω),  (25)
 
     The DC gain of the f inj  loop can thus be estimated by measuring v env,err  in equation (6) at two frequencies around an estimated f c,sys  and finding the slope. Furthermore, the initial value of A, the amplitude of square perturbation, can be set as: 
                     A   =       π   4     ⁢       A   ref              z   away     (     j   ⁢     ω     c   ,   sys         )                ,           (   26   )               
where A ref  is the desired amplitude of voltage perturbation and ∥Z away(jωc,sys) ∥ can be estimated from measurement. Similarly, the DC gain of the amplitude loop is given by a reference as:
 
                       G     A   ,   0       =       4   π     ⁢            G     plant   ,     v   0         (     j   ⁢     ω     c   ,   sys         )              ,           (   27   )               
where ∥G plant, vo(j(t)c,sys) ∥ can be estimated by measuring ∥v o ∥/∥i ref ∥ at the estimate f c,sys . With these simplifications, and observing from  FIG.  6    the dominant pole characteristics, the f inj  integrator can be designed as
 
                       k     i   ,     f   inj         =       2   ⁢   π   ⁢     f     c   ,   f           G       f   inj     ,   0           ,           (   28   )               
where f c,f  is the desired crossover frequency of the f inj  loop and k i,finj  is the integrator gain. Similarly, the amplitude controller can be designed as
 
                       k     i   ,   A       =       2   ⁢   π   ⁢     f     c   ,   A           G     A   ,   0           ,           (   29   )               
where f c,f  is the desired crossover frequency of the amplitude loop and k i,A  is the integrator gain. For both controllers, the crossover frequency is placed much lower than the pole frequency given by equation (23). Once these controllers are designed in continuous time, a suitable method can be used to convert it to discrete time before implementing in a microcontroller or FPGA.
 
Experimental Results
 
     The hardware tests establish the practicality and applicability of the proposed stability margin monitor in a wide variety of systems by initializing the continuous monitor using only online measurements and the simplified models presented above. Furthermore, tests are performed to evaluate the performance of the continuous monitor with system operating points changing. This is done by varying the load converter power from 0 W to 30 W and monitoring the change in system minor loop gain crossover frequency and phase margin. 
     A. Analysis of Test Cases. 
     As mentioned in above, the current and voltage controllers of the converters in the test setup are designed such that the system crossover frequency, f c,sys , given by equation (7) and the system phase margin, PM sys , given by equation (8) changes significantly as the load power increases. To have a baseline for comparison, the analytical models of Z ESC  and Z away,ESC  are computed, where the impedance models of Z sc  and Z Load  are given in a reference. The frequency response of Z ESC  and Z away,ESC , and the Nyquist plot of the minor loop gain equation (4) are shown in  FIGS.  7 A and  7 B . It is evident from the bode plots in  FIG.  7 A  that, as the load converter increases its power it changes the impedance seen by the ESC, resulting in a change of f c,sys . Similarly, it can be seen from both the bode and Nyquist plots in  FIG.  7 B  that the phase margin PM sys  reduces as the load power increases.  FIG.  7 C  is a Bode plot indicating measurement of the system phase margin.  FIG.  7 C  illustrates a phase difference between voltages v of  and v sf  where v of  is a representation of the voltage of the switching power converter and v sf  is a voltage transformation of the output current i o . The system phase margin PM sys  is depicted as the difference between where the phase of voltage v of  at 180 degrees where the phase of v sf  is at 180 degrees. 
     B. Initialization of the Continuous Monitor. 
     A DC microgrid such as that shown in  FIG.  1    is expected to be dynamic with sources and loads coming on and going off during normal operation of the system. This implies that, for the continuous monitor, Z away  cannot be known a priori. However, the operation and controller design of the stability margin monitor depend on Z away . Hence a measurement-based initialization of the continuous monitor is proposed herein based on the model simplification presented above. 
     To better explain the initialization steps, the experimental results of the continuous monitor initialization for the hardware setup of  FIG.  5    is shown in  FIG.  8    where, from the top, the first trace shows the DC bus voltage v dc , the second trace shows the current i in,ESC  that the ESC draws from the bus, the third trace shows the identified system crossover frequency f c,sys  and the last trace shows the identified system phase margin PM sys . The initialization steps shown in  FIG.  8    are as follows.
         1) Time t 1 : At time t 1 , the source converter starts up, ramps up the DC link voltage and starts regulating it in closed loop.   2) Time t 2 : At time t 2 , the ESC starts up, enables closed loop regulation of the output current control and ramps up the current drawn from the DC link to 4 A.   3) Time t 3 : At time t 3 , the continuous monitor enables the injection of square wave perturbation. The frequency of injection, f inj , is set to be the initial estimate of f c,sys  (180 Hz) which can be estimated from a one-time frequency sweep or a wide-band injection. The amplitude of perturbation is ramped up from zero to an initial value computed from equation (26).   4) Time t 4 : At time t 4 , the DC gain of the amplitude loop is estimated from equation (27) by setting:       

                              G     plant   ,   vo       (     j   ⁢     ω   inj       )          =       v   ofp     A       ,           (   30   )               
where A is the value of the initial amplitude of injection. Then the integrator gain for the perturbation amplitude controller is computed using equation (29) and the integrator is enabled. From t 4  onwards, the perturbation amplitude is regulated to be 150 mV which is 3% of the rated DC bus voltage of 5 V.
         5) Time t 5 : At time t 5 , the envelope error, v env,err , is recorded for an f inj  of 180 Hz and then f inj  is ramped up to 200 Hz. 6) Time t 6 : At time t 6 , the envelope error, v env,err , is recorded for f inj  of 200 Hz. This value and the value at t 5  are used in equation (24) to compute the DC gain of the f inj  loop and then the f inj  integrator gain is computed using equation (28). Finally, the f inj  integrator and PM sys  computation are enabled, after which, the ESC monitors fc,sys and PM sys  continuously.
 
C. Performance of the Continuous Monitor
       

     Once the continuous monitor has been initialized, the load converter power is ramped up to 30 watts (“W”), at which point PM sys  is low (˜20°). Then, the load power is ramped down to 0 W at a rate of 5 watts per second (“W/s”). The response of the system and the monitor outputs (fc,sys and PM sys ) for this transient are shown in  FIG.  9    where, from the top, the first trace shows the DC bus voltage v dc , the second trace shows the load converter input current i in,Load , the third trace shows the identified system crossover frequency f c,sys  and the last trace shows the identified system phase margin PM sys . 
     From the v dc  trace in  FIG.  9   , it is evident that the amplitude of perturbation is regulated before, during and after the load transient. As the load power reduced from 30 W to 0 W, the identified f c,sys  changed from 124 Hz to 168 Hz and the identified PM sys  changed from 18° to 37°. To compare the performance of the monitor with the analytical models, the identified f c,sys  and PM sys  were recorded for load powers from 0 W to 30 W and plotted against theoretical values found using the Nyquist plots of  FIG.  7 B . The comparison is shown in  FIG.  10   , where the left y-axis shows frequency in Hz and the right y-axis shows the phase margin in degrees.  FIG.  10    shows that the continuous monitor was able to identify f c,sys  and PM sys  with reasonable accuracy. 
     A novel method to monitor the system stability margin of a DC microgrid online in a continuous fashion has been proposed herein. The continuous monitoring technique can be embedded into any one of the converters already present in the system to evaluate the system stability margin without much additional computational cost. The proposed small-signal analysis of the continuous monitor and simplification method allow the online measurement-based design and tuning of the monitor controllers, with an estimated system crossover frequency to start. To validate the proposed analysis and design, hardware results are provided for the auto-initialization and operation of the proposed continuous monitor and compared with the theoretical prediction over a range of operating conditions. The continuous monitor proposed herein is applicable to other systems with multiple sources, loads and bidirectional converters connected. The monitored system crossover frequency and phase margin can be used in active stabilization, active damping and system central controller for system stabilization. 
     The proposed stability measurement system measures the system minor loop gain online and continuously by using a small perturbation in the system and measuring the terminal voltage and current. The proposed stability measurement system has potential to be applied in several applications such as electric and hybrid electric ships, including ships that have DC power distribution system, DC fast charging stations for charging of electric vehicles, and electric and hybrid electric aircraft having regulated DC power distribution system. 
     The usage of this invention would be to enable the customers to continuously monitor the system stability and make sure that the system operates reliably, is able to absorb disturbances, and take proactive measures to increase stability before the system reaches dangerously low margins. 
     Main aspects of the proposed stability measurement system:
         A power converter connected to a DC microgrid that continuously measures the small-signal stability margin of the DC link as well as the critical frequency for small-signal stability;   The invention uses a small perturbation injected through its controller, senses the DC-terminal output current and DC-terminal voltage, and calculates the DC microgrid system minor loop gain;   The invention uses the system minor loop gain calculation to drive the injection frequency to the crossover frequency of the system minor loop gain, thereby evaluating the phase margin at the crossover frequency;   The invention limits the amplitude of the perturbation in the system by using the sensed DC-terminal voltage and controlling the amplitude of perturbation to regulate that voltage; and   The proposed stability monitor can be incorporated into any power electronic converter topology in a DC microgrid if it has:
           i. Sensing of the DC-terminal voltage and output current,   ii. A controller capable of influencing the DC link voltage and current,   iii. Known analytical model of the small-signal output impedance, and   iv. Computational capability to evaluate the required functions of the stability monitor.   
               

     In the block diagram of the proposed stability monitor shown in  FIG.  3 B , a converter connected to a DC microgrid has a controller that regulates output current i o  (which could be a current or voltage associated with the converter) at a reference given by i ref . A perturbation i inj  is added on top of it that comprises a square wave with a frequency f inj  and amplitude A, as shown in  FIG.  4   . 
     The injection i inj  is added on top of a steady state reference i ref0  to generate the reference ref that is the input of the controller. Through the controller and the converter power stage, the perturbation is injected into the terminal voltage v o  and current i o . The response of the system is measured by measuring v o  and i o  and using the bandpass filters tuned at the injection frequency, f inj , the component of v o  and i o  at the injection frequency, v of  and i of  respectively, are evaluated. The filtered current i of  is fed to an analytical closed-loop output impedance model of the converter, Z 0  (s), to evaluate its response to the perturbation, v sf . An envelope detection algorithm is used in the ‘Envelope Detector’ block to determine the amplitude of v of  and v sf , denoted by v ofp  and v sfp  respectively. The amplitudes v ofp  and v sfp  are used by ‘Envelope Error’ block to generate an error v env,err  for the controller ‘f inj  Controller’, which is used to bring the frequency f inj  to a value where the minor loop gain equals 1. When the f inj  controller reaches zero error, the injection frequency f inj  is at the crossover frequency of the minor loop gain. Then, the ‘Phase Calculation’ block calculates the phase difference of v of  and v sf  which gives us the stability margin. Furthermore, the ‘Amplitude Error’ block compares the amplitude of the voltage perturbation v ofp  to a reference A ref  and generates an error for the ‘Amplitude Controller’ block that adjusts the injection amplitude A to regulate the amplitude of the voltage perturbation. 
     A Power Electronic Instrument for Active Stability Regulation of Interconnected Converters Based on Dynamic Virtual Impedance 
     As stated above, DC microgrid comprises of several power electronic converters that are interconnected and share a DC link, as depicted in  FIG.  1   . The individual converters in a DC microgrid may serve various purposes such as sourcing power, drawing power or providing energy storage backup for the DC link, etc. The converters may also have various isolated or non-isolated topologies, with varying control actions implemented into each converter. All the above results in the converters having different behavior as seen from the DC link, and thus, for stable operation of the DC microgrid, their compatibility needs to be ensured. One method of ensuring compatibility is by evaluating the impedances of the inter-connected converters and ensuring that they satisfy the impedance-based stability criteria, as discussed above.  FIG.  2    shows a representation of a DC microgrid where each connected converter is represented by its small-signal Thevenin equivalent. The stability of the DC microgrid is evaluated by evaluating the system minor loop gain given by: 
                       Minor   ⁢         loop   ⁢         gain     =       z   o       z   away         ,           (   31   )               
where Z o  is the output impedance of one of the converters in the DC microgrid and Z away  is the combined impedance of the rest of the system. The system crossover frequency is defined as the frequency at which the magnitude of the minor loop gain is 1. The phase of the minor loop gain at the crossover frequency gives information about the stability margin (phase margin) of the DC microgrid, as discussed above.
 
     For systems in which cost, weight and/or volume prohibit system overdesign to ensure stability, active stability enhancement methods are employed. Of the many methods proposed in literature for stability enhancement, virtual impedance based methods modify the impedance of a converter to bring the phase of the minor loop gain closer to zero. Several implementations of virtual impedance have been discussed in literature, but all have drawbacks. 
     The embodiments below propose a power electronic apparatus that can regulate the stability of a DC microgrid system by emulating a dynamic virtual impedance (“DVI”), which is defined as a second order system emulating a series RLC branch connected in parallel to the converter output as shown in  FIG.  11 ( a ) .  FIG.  11 ( b )  shows an example implementation of DVI and shows its dependence on the parameters, where the impedance Z vi (s) is defined by the following equation. 
     
       
         
           
             
               
                 
                   
                     
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     In the above equation ‘f’, ‘b’ and ‘r’ are defined as the center frequency, bandwidth and resistance value respectively, and are input parameters to the DVI. The DVI can be implemented into a power converter as shown in  FIG.  12   . 
     As shown in  FIG.  12   , DVI is implemented as a transfer function from the output voltage, v o , to a small contribution into the reference of the current controller, i vi . The value of f inj  can come from any health monitoring system that can provide the critical frequency of the system at which resonance is suspected (or the frequency where the magnitude of the system minor loop gain is equal to 1). In some embodiments, the health monitoring system is any of the monitoring loops of  FIGS.  3 A,  3 B and  3 C , as described above. 
     Changes in f inj  move the frequency response of DVI horizontally, as shown in  FIG.  11 ( b ) . The parameter r defines the magnitude of DVI at the critical frequency, which comes from the output of a phase margin (PM) regulator that takes in input from a health monitoring system which monitors the system stability margin. Changes in r move the frequency response vertically, as shown in  FIG.  11 ( b ) . The parameter b defines the width of the frequency response over which the DVI behaves resistive. A value of 10 for b results in the resistive behavior spanning 1 decade centered around f inj , a value of 100 for b results in the resistive behavior spanning 2 decades centered around f inj , and so on. For values of b lower than 1, Z vi  will behave like a notch filter with a magnitude of r at the notch frequency f inj . 
     The power converter  1202 , in some embodiments, is a switching power converter as described above and depicted in  FIGS.  2 ,  3 A,  3 B, and  11   ( a ). The rest of the system  1204  is also as described above and illustrated in  FIGS.  2 ,  3 A,  3 B, and  11   ( a ). The health monitoring system  1206  is also as described above and depicted in  FIGS.  3 A,  3 B and  3 C  and elsewhere. In some embodiments, the phase margin (“PM”) controller  1208 , in some embodiments, is implemented with a summation block that determines an error between the system phase margin PM sys  and the phase margin reference PM ref  and integrated or compensated in some other way by a PI controller, a PID controller, etc. to produce parameter r. The DVI impedance  1210 , in some embodiments, is implemented as equation (32) with inputs of the minor loop gain crossover frequency f inj , the parameter r and the monitored voltage of the DC bus. 
     In some embodiments, the PM controller  1208  and DVI impedance  1210  form a DVI injector configured to inject a DVI signal i v , onto a control loop of the power converter  1202  based on the voltage of the DC bus v o  or the current to the DC bus i o . In the embodiment depicted in  FIG.  12   , the control loop is a current loop and the DVI injector is configured to so the DVI signal i vi  is injected in the current loop. The DVI injector has inputs of the current to the DC bus i o , the system minor loop gain crossover frequency f inj  and a stability margin error signal r. The stability margin error includes a difference between the DC power system stability margin PM sys  and a stability margin reference PM ref , but also may be multiplied by a compensation factor, such as a PI control term, a PID control term, etc. The DVI signal emulates an impedance in series or parallel to an output of the switching power converter  1202 . In the embodiment depicted, the DVI signal emulates an impedance in parallel with the output of the switching power converter  1202 , as depicted in  FIG.  11 ( a ) . In some embodiments the DVI impedance is formulated to be in series with the switching power converter  1202  for a voltage control loop. 
     In some embodiments, the DVI impedance transforms the analytic expression in equation (32) is transformed using a bilinear transform, for example the Tustin bilinear transform, to convert the DVI impedance into a discrete transfer function. The discrete transfer function, in some embodiments, is implemented using a micro controller or a field-programmable gate array (“FPGA”). In other embodiments, the DVI impedance is implemented using hardware circuits or other method known to those of skill in the art. 
     In some embodiments, the DVI impedance  1210  includes a stability tuning circuit configured to continuously tune a center frequency, an amplitude at the center frequency and/or a width of an impedance flat region of the emulated impedance. In other embodiments, the stability tuning circuit continuously tunes the center frequency in response to changes to the system minor loop gain crossover frequency f inj  and the stability tuning circuit continuously tunes the amplitude at the center frequency in response to the stability margin error r. 
     While the DVI injector injects a DVI signal i vi  into the current control loop of  FIG.  12   , which controls output current of the switching power converter  1202 , in other embodiments the DVI injector injects the DVI signal in another location. For example, the DVI injector may inject a DVI signal into an input current control loop. In the embodiment, the effect of the DVI impedance  1210  would be scaled by the conversion ratio of the switching power converter  1202 . One of skill in the art will recognize other ways that the DVI impedance  1210  may be injected into the switching power converter  1202 . 
     This invention has potential to be applied in several applications such as: Electric and hybrid electric ships, including ships that have DC power distribution system, DC fast charging stations for charging of electric vehicles, and Electric and hybrid electric aircraft having regulated DC power distribution system. The usage of the embodiments described herein would be to enable the customers to enhance system stability using control, allowing them to avoid system overdesign, reduce the required size of the passive filters in the system and reduce system cost and volume. Furthermore, this will allow customers to make sure that the system operates reliably and is able to absorb disturbances. 
     Some of the main aspects of the embodiments described herein include:
         a. A power electronic apparatus that regulates the stability margin of the system by emulating a dynamic virtual impedance on the DC bus;   b. The invention emulates a virtual impedance on the bus in a way that decouples the tuning parameters of the impedance (center frequency, magnitude, resistance width) so that they can be part of independent feedback loops;   c. The invention uses system health information (stability margin and crossover frequency), that can come from any health monitoring system, and explicitly regulates the system stability margin to the desired value by continuously adjusting the DVI, allowing for a wide range of system operating conditions; and   d. The proposed stability regulator can be incorporated into any power electronic converter topology in a DC microgrid if it has:
           i. Sensing of the DC-terminal voltage and output current,   ii. A controller with a bandwidth capable of influencing the DC link voltage and current,   iii. A health monitoring system that provides the system minor loop gain crossover frequency and stability margin   iv. Computational capability to evaluate the required functions of the stability regulator.   
               

     The present invention may be embodied in other specific forms without departing from its spirit or essential characteristics. The described embodiments are to be considered in all respects only as illustrative and not restrictive. The scope of the invention is, therefore, indicated by the appended claims rather than by the foregoing description. All changes which come within the meaning and range of equivalency of the claims are to be embraced within their scope.