Patent Publication Number: US-RE44473-E

Title: Method for fabricating semiconductor device with vertical channel transistor

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     The present invention claims priority of Korean patent application number 2007-0136437, filed on Dec. 24, 2007, which is incorporated by reference in its entirety. 
     BACKGROUND OF THE INVENTION 
     The present invention relates to semiconductor device fabrication technology, and more particularly, to a method for fabricating a semiconductor device with a vertical channel transistor. 
     As the integration degree of a semiconductor device increases, a channel length of a transistor is gradually reduced, causing device characteristics to be deteriorated due to a short channel effect. To avoid the short channel effect, there have been proposed various methods of reducing a depth of a junction region or relatively increasing a channel length by recessing a channel region of a transistor. 
     However, there is an increasing demand for a smaller-sized transistor as the integration density of a semiconductor memory device such as a dynamic random access memory (DRAM) approaches gigabit scale. Recently, a transistor of a DRAM requires a device area of 4F 2  (F: minimum feature size). Therefore, it is difficult to meet the requirement for a device area despite the scaling-down of a channel length in a typical planar transistor structure where a gate electrode is formed over a substrate and junction regions are formed at both sides of the gate electrode. 
     SUMMARY OF THE INVENTION 
     To meet such a requirement for a limited device area, a vertical channel transistor has been suggested, which will be described in detail with reference to  FIG. 1 . 
       FIG. 1  illustrates a perspective view and a plan view of a vertical channel transistor. Referring to  FIG. 1 , a plurality of pillars P, which are arranged in a first direction (X-X′) and a second direction (Y-Y′) crossing the first direction, are formed over a substrate  100 . The pillar P is formed by etching the substrate  100  using a hard mask pattern (not shown). The pillar P may have a cylindrical structure. 
     Buried bit lines  101 , surrounding the pillar P and extending in the first direction, are formed in the substrate  100  between columns of the pillars P arranged in the first direction. The buried bit lines  101  are isolated from each other by a trench T for device isolation. 
     A surround type gate electrode (not shown) surrounding the pillar P is formed on a circumferential surface of the pillar P. A word line  102  is formed such that it is electrically connected to the surround type gate electrode and extends in the second direction. A storage electrode  104  is formed on top of the pillar P. A contact plug  103  may be interposed between the pillar P and the storage electrode  104 . 
     In the vertical channel transistor where a channel is formed vertically with respect to a surface of the substrate, a channel length can be increased without being limited to a device area, thus preventing the short channel effect. However, there is a limitation in a process for forming the word line  102 , resulting in a device failure. Hereinafter, one method for fabricating the vertical channel transistor in the substrate and the limitation thereof will be described in detail with reference to  FIGS. 2A to 2C . 
       FIGS. 2A to 2C  illustrate a method for fabricating a semiconductor device having a vertical channel transistor. Particularly,  FIGS. 2A to 2C  illustrate cross-sectional views taken along line Y-Y′ of  FIG. 1 , i.e., the second direction. Like reference numerals in  FIGS. 2A to 2C  denote like elements in  FIG. 1 . Since the accompanying drawings are provided to explain the limitation in a specific process for forming a word line, detailed descriptions for unrelated parts will be omitted herein. 
     Referring to  FIG. 2A , a semiconductor substrate  100  is provided, including a plurality of pillars P arranged in a first direction and a second direction crossing the first direction. A surround type gate electrode  203  is formed surrounding a lower portion of the pillar P. Buried bit lines  101  are formed in the substrate  100  between the pillars P arranged in the first direction, surrounding the pillar P and extending in the first direction. The buried bit lines  101  are isolated from each other by a trench T for device isolation. A first hard mask pattern  201  is formed on the pillar P and a spacer  202  is formed on sidewalls of an upper portion of the pillar P and sidewalls of the first hard mask pattern  201 . 
     An oxide layer  204  is formed over a resultant structure, and then planarized through chemical mechanical polishing (CMP) process until the first hard mask pattern  201  is exposed. After a second hard mask  205  is formed on the planarized resultant structure, a photoresist pattern  207  is formed over the hard mask  205  for the purpose of forming a word line. An anti-reflective layer  206  may be formed under the photoresist pattern  207  to prevent reflection during photo exposure process. 
     Referring to  FIG. 2B , the second hard mask  205  is etched, using the photoresist pattern  207  as an etch barrier, to form a second hard mask pattern  205 A exposing the oxide layer  204  corresponding to a region where a word line will be formed. Here, an overlay error of a mask during the process of forming the photoresist pattern  207  may lead to misalignment between the second hard mask pattern  205 A and the first hard mask pattern  201  and the pillar P (see dotted circle regions in  FIG. 2B ). Such a phenomenon of overlay error and misalignment becomes more serious as a semiconductor device is highly integrated and smaller-sized. 
     Referring to  FIG. 2C , the oxide layer  204  is dry-etched using the second hard mask pattern  205 A as an etch barrier until an upper portion of the surround type gate electrode  203  is exposed, thereby forming a trench for a word line. Thereafter, a conductive layer for a word line is formed over a resultant structure, and an etch-back process is performed on the conductive layer to a predetermined point lower than the top surface of the pillar P. As a result, a word line  102  is formed partially filling the trench for the word line. The word line  102  extends in the second direction and is electrically connected to the surround type gate electrode  203 . 
     During the dry etching of the oxide layer  204  and the etch-back process of the conductive layer for the word line, the first hard mask pattern  201  and the spacer  202  may be lost due to the misalignment between the second hard mask pattern  205 A and the first hard mask pattern  201  and the pillar P. This, in accordance with this less preferred technique, may cause an upper portion of the pillar P to be attacked and lost (see “A” in  FIG. 2C ). 
     Hence, it is required to develop a new, more preferred fabrication technique capable of preventing the pillar P from being attacked by minimizing the losses of the hard mask pattern  201  and the spacer  202  even though the misalignment occurs due to an overlay error of a mask. 
     At least one preferred embodiment of the present invention is therefore directed to providing a method for fabricating a semiconductor device with a vertical channel transistor, which can minimize losses of a hard mask pattern and a spacer to prevent a pillar from being damaged, by dividing a process of forming a trench for a word line into two sub processes and performing a process of forming a buffer layer between the two sub processes. 
     In accordance with an aspect of the present invention, there is provided a method for fabricating a semiconductor memory device with a vertical channel transistor. The method includes forming a plurality of pillars each having a hard mask pattern thereon over a substrate, each of the plurality of pillars comprising an upper pillar and a lower pillar; forming a surround type gate electrode surrounding the lower pillar; forming an insulation layer filling a space between the pillars; forming a preliminary trench by primarily etching the insulation layer using a mask pattern for a word line until a portion of the upper pillar is exposed; forming a buffer layer over a resultant structure including the preliminary trench except on a bottom of the preliminary trench; and forming a trench for a word line by secondarily etching the insulation layer until the surround type gate electrode is exposed. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  illustrates a perspective view and a plan view of a vertical channel transistor in accordance with one embodiment of the present invention. 
         FIGS. 2A to 2C  illustrate a method for fabricating a vertical channel transistor in a semiconductor device. 
         FIGS. 3A to 3J  illustrate a method for fabricating a vertical channel transistor in a semiconductor device in accordance with a preferred embodiment of the present invention. 
     
    
    
     DESCRIPTION OF SPECIFIC EMBODIMENTS 
       FIGS. 3A to 3J  illustrate a method for fabricating a vertical channel transistor in a semiconductor device in accordance with an embodiment of the present invention. In particular,  FIGS. 3A to 3J  illustrate cross-sectional views taken along line Y-Y″ of  FIG. 1 , i.e., a second direction. 
     Referring to  FIG. 3A , a plurality of first hard mask patterns  301 , which are arranged in a first direction and a second direction crossing the first direction, are formed over a substrate  300 . Preferably, the first hard mask pattern  301  has a multi-layered structure of an oxide layer  301 A and a nitride layer  301 B. The substrate  300  is etched to a predetermined depth using the first hard mask pattern  301  as an etch barrier to thereby form an upper pillar Pa. 
     Referring to  FIG. 3B , a spacer  302  is formed on sidewalls of the first hard mask pattern  301  and the upper pillar Pa. Preferably, the spacer  302  is formed of a nitride. The exposed substrate  300  is etched to a predetermined depth using the first hard mask pattern  301  and the spacer  302  as etch barriers, thereby forming a preliminary lower pillar Pb under the upper pillar Pa. As a result, preliminary pillars P arranged in the first and second directions are formed, each of which includes the upper pillar Pa and the preliminary lower pillar Pb. Although an initial plan view shape of the first hard mask pattern  301  is rectangular, the first hard mask pattern  301  and the pillar P may have a substantially cylindrical structure while undergoing etching processes. 
     Referring to  FIG. 3C , the exposed substrate  300  is isotropically etched, using the first hard mask pattern  301  and the spacer  302  as etch barriers, to recess the preliminary lower pillar Pb to a predetermined depth A. As a result, a pillar P′ for an active region is formed, which includes the upper pillar Pa and a lower pillar PbA. 
     Referring to  FIG. 3D , a gate dielectric layer  303  is formed on the surface of the substrate  300  exposed by the isotropic etch. A conductive layer for a gate electrode, for example, a polysilicon layer, is formed over a resultant structure, and then an etch-back process is performed on the conductive layer until the gate dielectric layer  303  is exposed. Thus, a surround type gate electrode  304  is formed, which surrounds a circumferential surface of the lower pillar PbA. 
     Referring to  FIG. 3E , impurities  305  are doped into the substrate  300  between the pillars P′ to form an impurity region for a buried bit line. Then, a trench T for device isolation, which extends in the first direction, is formed to a depth enough to penetrate the impurity region in the substrate  300  between columns of the pillars P′ arranged in the first direction. Consequently, buried bit lines are formed, which surround the pillar P′ and extend in the first direction. 
     Referring to  FIG. 3F , an oxide layer  306  is formed over a resultant structure and then planarized using a CMP process until the first hard mask pattern  301  is exposed. Thereafter, a second hard mask is formed over the planarized resultant structure and patterned using a photoresist pattern (not shown), thereby forming a second hard mask pattern  307  exposing the oxide layer  306  corresponding to a region where a word line will be formed. Preferably, the second hard mask pattern  307  is formed of an amorphous carbon. 
     Referring to  FIG. 3G , a primary dry etching process is performed on the oxide layer  306  using the second hard mask pattern  307  as an etch barrier until a portion of the upper pillar Pa (preferably, about half the upper pillar Pa) is exposed, thereby forming a preliminary trench  308  for a word line. Compared to the method explained referring to  FIGS. 2A to 2C , where the oxide layer is dry-etched until the surround type gate electrode is exposed, the etching amount of the oxide layer  306  is significantly reduced. Therefore, losses of the first hard mask pattern  301  and the spacer  302  on sidewalls thereof are negligible during the primary dry etching process, preventing the upper pillar Pa from being damaged or lost during a subsequent process. 
     Then, the second hard mask pattern  307  is removed. If the second hard mask pattern  307  is formed of an amorphous carbon, the second hard mask pattern  307  can be removed easily through a removal process using oxygen (O 2 ) plasma. 
     Referring to  FIG. 3H , to protect the first hard mask pattern  301  and the spacer  302  on the sidewalls thereof, a buffer layer  309  is formed over a resultant structure where the preliminary trench  308  is formed. The buffer layer  309  is formed of an insulation material. Especially, it is preferable that the buffer layer  309  is formed of ozone-undoped silicate glass (O 3 -USG), a boro-phospho silicate glass (BPSG), or a plasma enhanced tetra ethyl ortho silicate (PETEOS). The buffer layer  309  formed on the first hard mask pattern  301  and the sidewalls of the preliminary trench  308  are relatively thicker than the buffer layer  309  formed on a bottom of the preliminary trench  308 . A reference numeral  308 A represents a narrowed preliminary trench after the buffer layer  309  is formed. 
     Referring to  FIG. 3I , the thin buffer layer  309  formed on the bottom of the preliminary trench  308  is removed to expose the oxide layer  306 , preferably by a wet etching process using a buffer oxide etchant (BOE) solution. 
     Referring to  FIG. 3J , a second dry etching process is performed on the oxide layer  306  until an upper portion of the surround type gate electrode  304  is exposed, thereby forming a trench  308 B for a word line. Since the hard mask pattern  301  and the spacer  302  are protected by the buffer layer  309 , it is possible to prevent the upper pillar Pa from being attacked or damaged. Thereafter, the buffer layer  309  is removed. 
     Although not shown herein, a conductive layer is filled into the trench  308 B to form a word line (not shown) extending in the second direction and electrically connecting the surround type gate electrode  304 . 
     In the above preferred method of forming the semiconductor memory device with the vertical channel transistor, the process of forming the trench for a word line comprises the first and second dry etching processes, and the buffer layer  309  is formed after the formation of the preliminary trench  308  by the first dry etching process. Accordingly, the trench  308 B for a word line is formed in a state that the hard mask pattern  301  and the spacer  302  are protected by the buffer layer  309 . This makes it possible to effectively prevent the upper pillar Pa from being damaged or lost as could occur with the less preferred technique. 
     As described above, in accordance with the preferred embodiment of present invention, a process of forming a trench for a word line comprises two sub processes, and a process of forming a buffer layer is performed between the two sub processes. Consequently, it is possible to minimize losses of a hard mask pattern and spacer, thereby preventing damage or loss of a pillar. 
     While the present invention has been described with respect to the specific embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.