Patent Publication Number: US-9905172-B2

Title: Liquid crystal display device and related alignment method

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This document is a Continuation of U.S. patent application Ser. No. 13/787,840, filed Mar. 7, 2013 which claims priority to Taiwan Patent Application No. 101123864, filed Jul. 3, 2012, now Taiwan Patent No. I460709. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention is related to a liquid crystal display device and related alignment method, and more particularly, to a liquid crystal display device and related alignment method with ESD protection and reduced mura. 
     2. Description of the Prior Art 
     With rapid development of large-size liquid crystal display (LCD) panels, the ability to provide multi-viewing angles have become a major feature. Because of the advantages of multi-viewing angles and low response time, multi-domain vertical alignment (MVA) LCD panels have become the mainstream products of the large-size display panels. 
     Conventional MVA LCD panels provide multi-viewing angle function by making the liquid crystal molecules in different areas slant in different directions using protrusions (bumps). However, in addition to complicating manufacturing processes, protrusions may also block part of light, thereby lowering the aperture ratio and the brightness performance. 
     Therefore, polymer stabilized alignment or phase separation alignment (PSA) technology has been developed in which polymers are used to replace the protrusions in MVA LCD panels. The core of PSA technology is to forma polymer-alignment layer over a conventionally coated polyimide by mixing a UV-curable monomer into the liquid crystal molecules. The monomer is then activated by UV radiation while applying a curing voltage. The monomer reacts with the polymer layer to form a surface that fixes the pre-tilt angle of the liquid crystal molecules. 
       FIG. 1  is a diagram illustrating a prior art LCD device  600 . The LCD device  600  includes an LCD panel, a gate driving circuit, a source driving/testing circuit, a multiplexer, and an alignment circuit. The LCD panel is manufactured using PSA technology in which a plurality of data lines, a plurality of gate lines, and a plurality of pixels (not shown) are disposed. The gate driving circuit may provide gate driving signals for turning on each column of pixels. The source driving/testing circuit may provide data signal DIN for charging corresponding rows of pixel. According to the data signal DIN and switch control signals SW 1 ˜SWM, the multiplexer may output data signal DOUT 1 ˜DOUTM to the LCD panel. 
     During the alignment period, the multiplexer in the prior art LCD device is floating. Unstable curing voltage or electrostatic discharge (ESD) may influence the alignment process and cause image mura which downgrades display quality. 
     SUMMARY OF THE INVENTION 
     An embodiment of the present invention provides an LCD device having a display panel, a multiplexer, an alignment circuit and a short bar circuit. The display panel includes a plurality of pixels; a plurality of data lines disposed along a first direction and respectively coupled to the plurality of pixels; and a plurality of gate lines disposed along a second direction and respectively coupled to the plurality of pixels. The multiplexer is disposed on a first side of the display panel and configured to provide a plurality of output data signals according to a plurality of switch control signals and an input data signal. The multiplexer includes an input end for receiving the input data signal; a plurality of output ends coupled to the plurality of data lines for respectively outputting the plurality of output data signals; and a plurality of switches configured to control transmission paths between the input end and the plurality of output ends according to the plurality of switch control signals. The alignment circuit is configured to provide a curing voltage to the plurality of data lines during an alignment period. The short bar circuit is configured to couple the multiplexer to a predetermined voltage during the alignment period. 
     An embodiment of the present invention further provides an alignment method for use in an LCD device. The alignment method includes providing the LCD device which includes a display panel having a plurality of pixels and a plurality of data lines; a multiplexer having an input end, a plurality of output ends coupled to the pixels, and a plurality of switches configured to control transmission paths between the input end and the plurality of output ends according to a plurality of switch control signals, respectively; providing a curing voltage to the plurality of data lines and a UV light to the display panel during an alignment period; and coupling the multiplexer to a predetermined voltage for maintaining the plurality of switch control signals at a same level during the alignment period. 
     These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a diagram illustrating a prior art LCD device. 
         FIGS. 2 ˜ 6  are diagrams illustrating the structure and the operation of LCD devices according to embodiments of the present invention. 
     
    
    
     DETAILED DESCRIPTION 
       FIGS. 2 ˜ 6  are diagrams illustrating the structure and the operation of LCD devices according to embodiments of the present invention. The LCD device  100  depicted in  FIG. 2  includes an LCD panel  10 , a gate driving circuit  20 , a source driving/testing circuit  30 , a multiplexer  40 , a first alignment circuit  50 , and a short bar circuit  60 . The LCD device  200  depicted in  FIG. 3  includes an LCD panel  10 , a gate driving circuit  20 , a source driving/testing circuit  30 , a multiplexer  40 , a first alignment circuit  50 , and a second alignment circuit  55 . The LCD device  300  depicted in  FIG. 4  and the LCD device  400  depicted in  FIG. 5  each include an LCD panel  10 , a gate driving circuit  20 , a source driving/testing circuit  30 , a multiplexer  40 , a first alignment circuit  50 , a second alignment circuit  55 , and a short bar circuit  60 . The LCD device  500  depicted in  FIG. 6  includes an LCD panel  10 , a gate driving circuit  20 , a source driving/testing circuit  30 , a multiplexer  40 , a first alignment circuit  50 , a short bar circuit  60 , and an ESD protection circuit  70 . 
     In the embodiments of the present invention, the LCD panel  10  may be manufactured using PSA technology in which a plurality of data lines DL 1 ˜DLM (M is an integer larger than 1), a plurality of gate lines GL 1 ˜GLN (N is an integer larger than 1), and a plurality of pixels PX are disposed on the active area. The gate driving circuit  20  is configured to provide gate driving signals for turning on each row of pixels. The source driving/testing circuit  30  and the multiplexer  40  are configured to provide data signals for charging each column of pixels. 
     Referring to  FIG. 2  for a first embodiment of the present invention, the LCD device  100  performs alignment process using single-sided driving scheme and with ESD protection. During the alignment period, the first alignment circuit  50  is configured to provide a curing voltage VPSA to the data lines DL 1 ˜DLM, and the short bar circuit  60  is configured to couple the multiplexer  40  to a predetermined voltage VMUX for turning off the multiplexer  40 . The turned-off multiplexer  40  may prevent the ESD generated by the source driving/testing circuit  30  from reaching the data lines DL 1 ˜DLM, thereby improving image mura. 
     Referring to  FIG. 3  for a second embodiment of the present invention, the LCD device  200  performs alignment process using dual-sided driving scheme and with ESD protection. The first alignment circuit  50  and the second alignment circuit  55  are respectively disposed on opposite sides of the LCD panel  10 . During the alignment period, the first alignment circuit  50  is configured to provide a curing voltage VPSA to the first side of the data lines DL 1 ˜DLM, the second alignment circuit  55  is configured to provide a curing voltage VPSA to the second side of the data lines DL 1 ˜DLM, and the multiplexer  40  is floating. The second alignment circuit  55  may share the ESD generated by the source driving/testing circuit  30 , thereby improving image mura. 
     Referring to  FIG. 4  for a third embodiment of the present invention, the LCD device  300  performs alignment process using dual-sided driving scheme and with ESD protection. The first alignment circuit  50  and the second alignment circuit  55  are respectively disposed on opposite sides of the LCD panel  10 , wherein the first alignment circuit  50  is disposed between the LCD panel  10  and the multiplexer  40 . During the alignment period, the first alignment circuit  50  is configured to provide a curing voltage VPSA to the first side of the data lines DL 1 ˜DLM, the second alignment circuit  55  is configured to provide a curing voltage VPSA to the second side of the data lines DL 1 ˜DLM, and the short bar circuit  60  is configured to couple the multiplexer  40  to a predetermined voltage VMUX for turning off the multiplexer  40 . The turned-off multiplexer  40  may prevent the ESD generated by the source driving/testing circuit  30  from reaching the data lines DL 1 ˜DLM, thereby improving image mura. 
     Referring to  FIG. 5  for a fourth embodiment of the present invention, the LCD device  400  performs alignment process using dual-sided driving scheme and with ESD protection. The first alignment circuit  50  and the second alignment circuit  55  are respectively disposed on opposite sides of the LCD panel  10 , wherein the multiplexer  40  is disposed between the LCD panel  10  and the second alignment circuit  55 . During the alignment period, the short bar circuit  60  is configured to couple the multiplexer  40  to a predetermined voltage VMUX for turning on the multiplexer  40 , the first alignment circuit  50  is configured to provide a curing voltage VPSA to the first side of the data lines DL 1 ˜DLM, and the second alignment circuit  55  is configured to provide a curing voltage VPSA to the second side of the data lines DL 1 ˜DLM via the turned-on multiplexer  40 . The second alignment circuit  55  may share the ESD present at the input end of the multiplexer  40 , thereby improving image mura. 
     Referring to  FIG. 6  for a fifth embodiment of the present invention, the LCD device  500  performs alignment process using single-sided driving scheme and with ESD protection. During the alignment period, the first alignment circuit  50  is configured to provide a curing voltage VPSA to the data lines DL 1 ˜DLM, and the short bar circuit  60  is configured to couple the multiplexer  40  to a predetermined voltage VMUX for turning off the multiplexer  40 . The ESD protection circuit  70  is disposed between the source driving/testing circuit  30  and the input end of the multiplexer  40 . The ESD protection circuit  70  may share the ESD generated by the source driving/testing circuit  30 , and the turned-off multiplexer  40  may prevent the ESD generated by the source driving/testing circuit  30  from reaching the data lines DL 1 ˜DLM, thereby improving image mura. 
     In the embodiment illustrated in  FIG. 6 , the ESD protection circuit  70  may include a first diode and a second diode. The anode of the first diode is coupled to a low level voltage VGL, and the cathode of the first diode is coupled to the input end of the multiplexer  40 . The anode of the second diode is coupled to the input end of the multiplexer  40 , and the cathode of the second diode is coupled to a high level voltage VGH. However, the embodiment of the ESD protection circuit  70  depicted in  FIG. 6  is merely for illustrative purpose and does not limit the scope of the present invention. 
     In the embodiments of the present invention, the gate driving circuit  20  may include pull-up switches T 1 ˜TN and shift registers SR 1 ˜SRN. Each pull-up switch includes a first end for receiving a bias voltage VGH, a second end coupled to a corresponding gate line, and a control end for receiving a control signal CTL. During the alignment period, the control signal CTL is set to low level for turning on the pull-up switches T 1 ˜TN so that the bias voltage VGH may turn on the pixels PX for receiving the curing voltage VPSA. During the display period, the control signal CTL is set to high level for turning off the pull-up switches T 1 ˜TN, thereby preventing the bias voltage VGH from reaching the gate lines GL 1 ˜GLN. At the same time, the control signal CTL is inverted to low level by a voltage buffer  66  for turning off the switches B 1 ˜BN, thereby preventing the pixels PX from receiving the curing voltage VPSA. 
     In the embodiments of the present invention, the multiplexer  40  may adopt 1-to-M scheme and may include an input end, M output ends and M switches A 1 ˜AM. The input end of the multiplexer  40  is coupled to the source driving/testing circuit  30  for receiving an input signal DIN. The switches A 1 ˜AM are configured to control the signal transmission paths between the input end and the output ends of the multiplexer  40  according to the control signals SW 1 ˜SWM, respectively. Therefore, the multiplexer  40  may output data signals DOUT 1 ˜DOUTM to the data lines DL 1 ˜DLM, respectively. 
     In the embodiments of the present invention, the alignment circuits  50  and  55  may each include M switches B 1 ˜BN, transmission logic gates  62  and  64 , and a voltage buffer  66 . The switches B 1 ˜BN include first ends respectively coupled to the data lines DL 1 ˜DLM, second ends for receiving a curing voltage VPSA, and control ends coupled to the output end of the voltage buffer  66 . Each of the transmission logic gates  62  and  64  includes a first end coupled to the control ends of the pull-up switches T 1 ˜TN, a second control end for receiving a bias voltage VGL, and an input end for receiving a bias voltage VCOM. The output end of the transmission logic gate  62  is coupled to the input end of the voltage buffer  66 , and the output end of the transmission logic gate  64  is coupled to receive the bias voltage VGL. The bias voltage VGH may be a high level voltage, the bias voltage VGL may be a low level voltage, and the bias voltage VCOM may be a common voltage. 
     In the embodiments of the present invention, the short bar circuit  60  may include M switches C 1 ˜CM, transmission logic gates  72  and  74 , and a voltage buffer  76 . The switches C 1 ˜CM include first ends respectively coupled to the control ends of the switches A 1 ˜AM, second ends for receiving a predetermined voltage VMUX, and control ends coupled to the output end of the voltage buffer  76 . Each of the transmission logic gates  72  and  74  includes a first end coupled to the control ends of the pull-up switches T 1 ˜TN, a second control end for receiving a bias voltage VGL, and an input end for receiving a bias voltage VCOM. The output end of the transmission logic gate  72  is coupled to the input end of the voltage buffer  76 , and the output end of the transmission logic gate  74  is coupled to receive the bias voltage VGL. The bias voltage VGH may be a high level voltage, the bias voltage VGL may be a low level voltage, and the bias voltage VCOM may be a common voltage. 
     During the alignment period, the control signal CTL is set to turn on the switches B 1 ˜BM so that the data lines DL 1 ˜DLM may be coupled to the curing voltage VPSA. Meanwhile, the control signal CTL is set to turn on the switches C 1 ˜CM so that the control ends of the switches A 1 ˜AM may be coupled to the predetermined voltage VMUX. 
     In the LCD devices  100 ,  200 ,  300  and  500  according to embodiments of the present invention, the predetermined voltage VMUX may be set to the turn-off voltage of the switches A 1 ˜AM or smaller than the turn-on voltage of the switches A 1 ˜AM so as to turn off the multiplexer  40  during the alignment period. The turned-off multiplexer  40  may prevent the ESD generated by the source driving/testing circuit  30  from reaching the data lines DL 1 ˜DLM, thereby improving image mura. 
     In the LCD device  400  according to embodiments of the present invention, the predetermined voltage VMUX may be set to the turn-on voltage of the switches A 1 ˜AM or larger than the turn-on voltage of the switches A 1 ˜AM so as to turn on the multiplexer  40  during the alignment period. The second alignment circuit  55  may share the ESD present at the input end of the multiplexer  40 , thereby improving image mura. 
     During the alignment period, the multiplexer in the LCD device of the present invention is coupled to a predetermined voltage in order to prevent unstable curing voltage or ESD from influencing the curing process. The display quality can thus be improved by reducing image mura. 
     Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.