Patent Publication Number: US-9433108-B2

Title: Method of fabricating a circuit board structure having an embedded electronic element

Description:
CROSS-REFERENCES TO RELATED APPLICATIONS 
     This application claims under 35 U.S.C. §119(a) the benefit of Taiwanese Application No. 102102423, filed Jan. 23, 2013, the entire contents of which is incorporated herein by reference. 
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to circuit board structures and fabrication methods thereof, and more particularly, to a circuit board structure having at least an embedded electronic element and a fabrication method thereof. 
     2. Description of Related Art 
     Along with the progress of semiconductor packaging technologies, various package types have been developed for semiconductor devices. For example, an electronic element can be embedded in and electrically connected to a packaging substrate so as to form a package. Such a package has reduced size and improved electrical performance and therefore has become a main trend. 
       FIGS. 1A to 1F  are schematic cross-sectional views showing a circuit board structure having embedded electronic elements and a fabrication method thereof according to the prior art. 
     Referring to  FIG. 1A , a substrate  10  is provided, which has opposite first and second surfaces  10   a ,  10   b  and a cavity  100  penetrating the first and second surfaces  10   a ,  10   b . An adhesive layer  11  is formed on the second surface  10   b  of the substrate  10  to cover one end of the cavity  100 , and a plurality of electronic elements  12  are disposed on the adhesive layer  11  in the cavity  100 . Each of the electronic elements  12  has a first active surface  12   a  having a plurality of first electrode pads  121   a  and a second active surface  12   b  opposite to the first active surface  12   a  and having a plurality of second electrode pads  121   b . The first active surfaces  12   a  and the first electrode pads  121   a  of the electronic elements  12  are exposed from the first surface  10   a  of the substrate  10 . 
     Referring to  FIG. 1B , a first dielectric layer  13   a  is laminated on the first surface  10   a  of the substrate  10  and the first active surfaces  12   a  of the electronic elements  12 . Further, the first dielectric layer  13   a  flows into the cavity  100  so as to cover side surfaces of the electronic elements  12 . 
     Referring to  FIG. 1C , the adhesive layer  11  is removed to expose the second active surfaces  12   b  and the second electrode pads  121   b  of the electronic elements  12  from the second surface  10   b  of the substrate  10 . Then, a second dielectric layer  13   b  is laminated on the second surface  10   b  of the substrate  10  and the second active surfaces  12   b  of the electronic elements  12 . Thereafter, the first dielectric layer  13   a  is covered with a first copper foil  14   a , and the second dielectric layer  13   b  is covered with a second copper foil  14   b.    
     Referring to  FIG. 1D , a brown oxide treatment is applied to the first and second copper foils  14   a ,  14   b , and a laser drilling process is performed to form a plurality of first openings  130   a  through the first copper foil  14   a  and the first dielectric layer  13   a  to expose the first electrode pads  121   a  and form a plurality of second openings  130   b  through the second copper foil  14   b  and the second dielectric layer  13   b  to expose the second electrode pads  121   b.    
     Referring to  FIG. 1E , a conductive layer  15  is formed on walls of the first and second openings  130   a ,  130   b  by electroless plating. 
     Referring to  FIG. 1F , an electroplating process is performed through the conductive layer  15  so as to form a plurality of first conductive vias  16   a  in the first openings  130   a  and form a plurality of second conductive vias  16   b  in the second openings  130   b , thus electrically connecting the first and second copper foils  14   a ,  14   b  through the first and second conductive vias  16   a ,  16   b.    
     However, in the above-described method, the laser drilling, electroless plating and electroplating processes are complicated, costly and time-consuming. 
     Therefore, there is a need to provide a circuit board structure having at least an embedded electronic element and a fabrication method thereof so as to overcome the above-described drawbacks. 
     SUMMARY OF THE INVENTION 
     In view of the above-described drawbacks, the present invention provides a circuit board structure having at least an embedded electronic element, which comprises: a substrate having opposite first and second surfaces; at least an electronic element embedded in the substrate, wherein the electronic element has a first active surface having a plurality of first electrode pads and a second active surface opposite to the first active surface and having a plurality of second electrode pads, the first active surface and the first electrode pads of the electronic element being exposed from the first surface of the substrate; a plurality of first conductive bumps formed on the first electrode pads of the electronic element, wherein each of the first conductive bumps is bonded to the corresponding first electrode pad through a bottom portion thereof and the bottom portion is greater in width than an opposite top portion of the first conductive bump; a first dielectric layer formed on the first surface of the substrate and the first active surface of the electronic element and penetrated by the first conductive bumps; and a first metal layer formed on the first dielectric layer and the first conductive bumps and in contact with the first conductive bumps. 
     The present invention further provides a method for fabricating a circuit board structure having at least an embedded electronic element, which comprises the steps of: providing a substrate having opposite first and second surfaces and embedding at least an electronic element in the substrate, wherein the electronic element has a first active surface having a plurality of first electrode pads and a second active surface opposite to the first active surface and having a plurality of second electrode pads, the first active surface and the first electrode pads of the electronic element being exposed from the first surface of the substrate; forming a plurality of first conductive bumps on the first electrode pads of the electronic element; and covering the first surface of the substrate and the first active surface of the electronic element with a first dielectric layer and a first metal layer stacked on the first dielectric layer, wherein the first conductive bumps penetrate the first dielectric layer so as to be in contact with the first metal layer. 
     Therefore, the present invention dispenses with the conventional laser drilling, electroless plating and electroplating processes so as to simplify the fabrication process, reduce the fabrication cost and save the fabrication time. 
    
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         FIGS. 1A to 1F  are schematic cross-sectional views showing a circuit board structure having embedded electronic elements and a fabrication method thereof according to the prior art; and 
         FIGS. 2A to 2G  are schematic cross-sectional views showing a circuit board structure having at least an embedded electronic element and a fabrication method thereof according to the present invention. 
     
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
     The following illustrative embodiments are provided to illustrate the disclosure of the present invention, these and other advantages and effects can be apparent to those in the art after reading this specification. 
     It should be noted that all the drawings are not intended to limit the present invention. Various modifications and variations can be made without departing from the spirit of the present invention. Further, terms such as “top”, “bottom”, “end”, “a” etc. are merely for illustrative purposes and should not be construed to limit the scope of the present invention. 
       FIGS. 2A to 2G  are schematic cross-sectional views showing a circuit board structure having at least an embedded electronic element and a fabrication method thereof according to the present invention. 
     Referring to  FIG. 2A , a substrate  20  is provided, which has opposite first and second surfaces  20   a ,  20   b  and a cavity  200  penetrating the first and second surfaces  20   a ,  20   b . An adhesive layer  21  is formed on the second surface  20   b  of the substrate  20  for covering one end of the cavity  200 , and at least an electronic element  22  is disposed on the adhesive layer  21  in the cavity  200 . In the present embodiment, a plurality of electronic elements  22  are disposed on the adhesive layer  21  in the cavity  200 . Each of the electronic elements  22  has a first active surface  22   a  having a plurality of first electrode pads  221   a  and a second active surface  22   b  opposite to the first active surface  22   a  and having a plurality of second electrode pads  221   b . The first active surface  22   a  and the first electrode pads  221   a  of the electronic element  22  are exposed from the first surface  20   a  of the substrate  20 . The electronic element  22  can be a capacitor, such as a multi-layer ceramic capacitor (MLCC). 
     Referring to  FIG. 2B , a plurality of first conductive bumps  23   a  made of such as silver paste are formed on the first electrode pads  221   a  by printing and heated so as to be cured. Each of the first conductive bumps  23   a  is bonded to the corresponding first electrode pad  221   a  through a bottom portion thereof and the bottom portion is greater in width than an opposite top portion of the first conductive bump  23   a.    
     Referring to  FIGS. 2C and 2D , the first surface  20   a  of the substrate  20  and the first active surfaces  22   a  of the electronic elements  22  are covered with a first dielectric layer  24   a  and a first metal layer  25   a  stacked on the first dielectric layer  24   a . Further, the first dielectric layer  24   a  flows into the cavity  200  to cover side surfaces of the electronic elements  22 . The first dielectric layer  24   a  and the first metal layer  25   a  can be made of a resin-coated copper foil. The first conductive bumps  23   a  penetrate the first dielectric layer  23   a  so as to be in contact with the first metal layer  25   a . Then, the adhesive layer  21  is removed to expose the second active surfaces  22   b  and the second electrode pads  221   b  of the electronic elements  22  from the second surface  20   b  of the substrate  20 . 
     Referring to  FIG. 2E , a plurality of second conductive bumps  23   b  made of such as silver paste are formed on the second electrode pads  221   b  by printing and heated so as to be cured. Each of the second conductive bumps  23   b  is bonded to the corresponding second electrode pad  221   b  through a bottom portion thereof and the bottom portion is greater in width than an opposite top portion of the second conductive bump  23   b.    
     Referring to  FIGS. 2F and 2G , the second surface  20   b  of the substrate  20  and the second active surfaces  22   b  of the electronic elements  22  are covered with a second dielectric layer  24   b  and a second metal layer  25   b  stacked on the second dielectric layer  24   b . The second conductive bumps  23   b  penetrate the second dielectric layer  24   b  so as to be in contact with the second metal layer  25   b , thereby electrically connecting the first metal layer  25   a  and the second metal layer  25   b  through the first conductive bumps  23   a  and the second conductive bumps  23   b . As such, a circuit board structure  2  having a plurality of embedded electronic elements  22  is formed. 
     The present invention further provides a circuit board structure  2  having at least an embedded electronic element, which has: a substrate  20  having opposite first and second surfaces  20   a ,  20   b ; at least an electronic element  22  embedded in the substrate  20 , wherein the electronic element  22  has a first active surface  22   a  having a plurality of first electrode pads  221   a  and a second active surface  22   b  opposite to the first active surface  22   a  and having a plurality of second electrode pads  221   b , the first active surface  22   a  and the first electrode pads  221   a  of the electronic element  22  being exposed from the first surface  20   a  of the substrate  20 ; a plurality of first conductive bumps  23   a  formed on the first electrode pads  221   a  of the electronic element  22 , wherein each of the first conductive bumps  23   a  is bonded to the corresponding first electrode pad  221   a  through a bottom portion thereof and the bottom portion is greater in width than an opposite top portion of the first conductive bump  23   a ; a first dielectric layer  24   a  formed on the first surface  20   a  of the substrate  20  and the first active surface  22   a  of the electronic element  22  and penetrated by the first conductive bumps  23   a ; and a first metal layer  25   a  formed on the first dielectric layer  24   a  and the first conductive bumps  23   a  and in contact with the first conductive bumps  23   a.    
     In the above-described circuit board structure  2 , a cavity  200  is formed in the substrate  20  to penetrate the first and second surfaces  20   a ,  20   b , thus allowing the electronic element  22  to be disposed in the cavity  200  and exposing the second active surface  22   b  and the second electrode pads  221   b  of the electronic element  22  from the second surface  20   b  of the substrate  20 . Therefore, the circuit board structure  2  further has: a plurality of second conductive bumps  23   b  formed on the second electrode pads  221   b , wherein each of the second conductive bumps  23   b  is bonded to the corresponding second electrode pad  221   b  through a bottom portion thereof and the bottom portion is greater in width than an opposite top portion of the second conductive bump  23   b ; a second dielectric layer  24   b  formed on the second surface  20   b  of the substrate  20  and the second active surface  22   b  of the electronic element  22  and penetrated by the second conductive bumps  23   b ; and a second metal layer  25   b  formed on the second dielectric layer  24   b  and the second conductive bumps  23   b  and in contact with the second conductive bumps  23   b.    
     In the present embodiment, the first conductive bumps  23   a  are made of silver paste. The electronic element  22  is a capacitor, such as a multi-layer ceramic capacitor (MLCC). 
     Therefore, the present invention dispenses with the conventional laser drilling, electroless plating and electroplating processes so as to simplify the fabrication process, reduce the fabrication cost and save the fabrication time. 
     The above-described descriptions of the detailed embodiments are only to illustrate the preferred implementation according to the present invention, and it is not to limit the scope of the present invention. Accordingly, all modifications and variations completed by those with ordinary skill in the art should fall within the scope of present invention defined by the appended claims.