Patent Publication Number: US-7710373-B2

Title: Liquid crystal display device for improved inversion drive

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a liquid crystal display (LCD) device, a liquid crystal driver and a method for driving an LCD panel, and in particular a technique to drive the LCD panel by an inversion drive method. 
     2. Description of the Related Art 
     The inversion drive is regarded as one of the techniques that are widely used to drive the liquid crystal display panel. The inversion drive is a driving method which inverts the polarities of data signals provided to data lines (or signal lines) at appropriate time and spatial intervals in order to prevent image “burn-in” of the LCD panel. The inversion drive reduces DC components of drive voltages applied to the liquid crystal capacitors within respective pixels, and effectively prevents the image “burn-in” phenomenon. 
     The inversion drive includes two kinds of methods: a common constant driving method and a common inversion driving method. The common constant drive method involves inverting the polarities of data signals while sustaining the potential level of a common electrode (or an opposite electrode) unchanged; the potential level of the common electrode is referred to as the common potential V COM , hereinafter. On the other hand, the common inversion drive method is a driving method which inverts both the data signal and the common potential V COM . The common constant drive method has an advantage of excellent stability in the common potential V COM  compared to the common inversion driving method. As well-known to those skilled in the art, the stability of the common potential V COM  is important in terms of suppressing flickers. 
     One of the typical common constant driving methods is a dot inversion drive in which the polarities of data signals applied to respective pixels are spatially inverted with respect to both horizontal and vertical directions. It should be noted that the polarities of the data signals are defined with respect to the common electrical potential V COM  in this specification. The dot inversion drive further improves the stability of the common potential V COM , and effectively suppressing the flickers. Most typically, the spatial interval in which the polarities of the data signals are inverted is one pixel with respect to both the horizontal and vertical directions. However, the dot inversion drive in this specification should be understood as including the case that the spatial interval in which the polarities of data signals are inverted is two or more pixels, and the case that the spatial interval in which the polarities of data signals is inverted is different between the horizontal direction and the vertical direction. 
     In the dot inversion drive, the potential levels of the data lines are inverted in order to invert the data signals written into the pixels with respect to the vertical direction. The polarities of the potential levels of the data lines when the data signals are written into pixels in a specific horizontal line are opposite to the polarities of the potential levels of the data lines when the data signals are applied to pixels in the adjacent horizontal line. 
     A problem accompanied by the inversion of the potential level of the data lines is that increased power is required to invert the potential levels of the data lines due to an extremely large capacity of the data lines, which will undesirably cause the increase of power consumption in liquid crystal display devices. The increased power consumption to invert the potential level of the data lines is one of the serious problems, particularly in a liquid crystal display device within a cellular phone terminal. 
     One approach has been proposed as a technique to suppress the power consumption in the liquid crystal display devices, which involves short-circuiting data lines before inverting the potential levels of the data lines. Japanese Laid-Open Patent Application No. Jp-A Heisei 11-95729, for example, discloses a technique in which adjacent data lines are short-circuited before inverting the potential levels of the data lines within the liquid crystal display device adapted to dot inversion drive with the spatial interval to invert the data signals configured to one pixel. Short-circuiting the data lines effectively allows electric charges accumulated in the data lines to be effectively utilized, and thereby suppresses the power consumption in the liquid crystal display device. Japanese Laid-Open Patent Application No. Jp-A 2002-62855 also discloses a technique in which data lines are not short-circuited in a non-inverting period during which the polarities of potential levels of data lines are not inverted for the further suppressing the power consumption. 
     Another important factor to suppress the power consumption of the liquid crystal display device is reduction of power consumption in operational amplifiers used for driving data lines. 
     The techniques disclosed in these patent applications, however, suffer from a problem of useless power consumption in the operational amplifiers. This is because the driving capabilities of the operational amplifiers are not controlled in the disclosed liquid crystal drivers. In an architecture of the liquid crystal drivers in which a pair of data lines are short-circuited before inverting the potential levels of the pair of data lines, the operational amplifiers need to have a sufficient drive capability to charge (or discharge) the respective data lines from an average potential level of the pair of the data lines to the potential levels indicated by the associated pixel data. Accordingly, when the difference between the average potential level of the pair of the above data lines and the potential levels indicated by the pixel data is small, the drive capability of the operational amplifiers should be small; however, the liquid crystal drivers disclosed in the above-mentioned patent applications do not have function of controlling the drive capability of the operational amplifiers. In the conventional techniques, the operational amplifiers are required to be designed with a drive capability to cope with a maximum difference between the average electrical potential of the pair of the data lines and the electrical potentials indicated by the with the pixel data. This undesirably increases power consumption of the operational amplifiers. 
     With respect to the above-described problem, techniques are disclosed which reduce power consumption of the operational amplifiers by controlling the drive capability and the use/no-use in the operational amplifiers. Japanese Laid-Open Patent Application No. Jp-A Heisei 5-41651, for example, discloses a technique in which a drive capability of each amplifier is controlled in response to a difference between an output signal provided from the operational amplifier and an input signal voltage. In this technique, the drive capabilities of respective operational amplifiers are increased when a difference between the output signal and the input signal voltage is large, and the drive capabilities of the operational amplifiers are decreased for a small difference. Since reduction in the drive capability effectively reduces power consumption of the operational amplifiers, the power consumption of operational amplifiers is suppressed by reducing the driving capabilities of the operational amplifiers when a large drive capability is not required. 
     Japanese Laid-Open Patent Application No. Jp-A 2004-45839 further discloses a technique to deactivate operational amplifiers in response to pixel data associated with pixels in the horizontal line and pixel data of the corresponding pixels in the adjacent horizontal line. More specifically, this patent application discloses that data lines are driven by D/A converters without using operational amplifiers when the pixel data of all the pixels in the horizontal line are identical to the pixel data of the corresponding pixels in the adjacent horizontal line. When the pixel data of one pixel in a horizontal line is detected as being different from that of the corresponding pixel in the adjacent horizontal line, the operational amplifiers are used to drive the data lines. 
     However, these techniques do not provide a technique for controlling the drive capability of the operational amplifiers suitable for architecture in which the data lines are short-circuited before driving data lines. 
     SUMMARY OF THE INVENTION 
     In an aspect of the present invention, a liquid crystal display device is composed of first and second data lines, first and second operational amplifiers, and a short-circuiting circuit. The first operational amplifier is configured to drive the first data line to a potential of a first polarity during a first period, and to drive the second data line to a potential of the first polarity during a second period following the first period. The second operational amplifier is configured to drive the second data line to a potential of a second polarity complementary to the first polarity during the first period, and to drive the first data line to a potential of the second polarity during the second period. The short-circuiting circuit is configured to short-circuit the first and second data lines during a short-circuiting period between the first and second periods. Drive capabilities of the first and second operational amplifiers are controlled in response to a short-circuit potential of the first and second data lines during the short-circuiting period. 
     The liquid crystal display device thus constructed controls the drive capabilities of the first and second operational amplifiers in response to the potential of the first and second data lines when the first and second data lines are short-circuited, and thereby effectively reduces the power consumption. 
     More specifically, the drive capability of the first operational amplifier during the second period is controlled in response to a difference between the short-circuit potential and a potential to which the second data line is driven during the second period, and the drive capability of the second operational amplifier during the second period is controlled in response to a difference between the short-circuit potential and a potential to which the first data line is driven during the second period. Such architecture allows driving the first and second data lines with large drive capability when the differences between the short-circuit potential and the potentials to which the first and second data lines are to be driven are large, and vice versa. 
     The control based on the differences between the short-circuit potential and the potentials to which the first and second data lines are to be driven may be achieved in response to pixel data. For example, when the first operational amplifier is responsive to first pixel data for driving the first data line during the first period, and is responsive to second pixel data for driving the second data line during the second period, and the second operational amplifier is responsive to third pixel data for driving the second data line during the first period, and is responsive to fourth pixel data for driving the first data line during the second period, it is preferable that the drive capability of the first operational amplifier during the second period is controlled in response to the second pixel data in addition to the short-circuit potential, and the drive capability of the second operational amplifier during the second period is controlled in response to the fourth pixel data in addition to the short-circuit potential. 
     In a preferred embodiment, the drive capability of the first operational amplifier during the second period may be controlled in response to the first and third pixel data in addition to the second pixel data, and the drive capability of the second operational amplifier during the second period may be controlled in response to the first and third pixel data in addition to the fourth pixel data. The use of the pixel data is preferable for facilitating the control of the drive capabilities. 
     In another aspect of the present invention, a liquid crystal display device is composed of first and second data lines; first and second operational amplifiers, and a short-circuiting circuit. The first operational amplifier is responsive to first pixel data for providing a data signal of a first polarity for one of the first and second data lines during a first period, and is responsive to second pixel data for providing a data signal of the first polarity for another of the first and second data lines during a second period following the first period. The second operational amplifier is responsive to third pixel data for providing a data signal of a second polarity complementary to the first polarity for the other of the first and second data lines during the first period, and is responsive to second pixel data for providing a data signal of the second polarity for the one of the first and second data lines. The short-circuiting circuit is configured to short-circuit the first and second data lines during a short-circuiting period between the first and second periods. Drive capabilities of the first and second operational amplifiers are controlled in response to the first and third pixel data. 
     The liquid crystal display device thus constructed can recognize the short-circuit potential of the first and second data lines during the short-circuiting period from the first and third pixel data, and configure the first and second operational amplifiers with appropriate drive capabilities in accordance with the short-circuit potential. This effectively reduces the power consumption of the liquid crystal display device. 
     As thus described, the present invention effectively reduces the power consumption of a liquid crystal display device adopting dot inversion drive in which data lines are short-circuited before respective data lines are driven. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The above and other advantages and features of the present invention will be more apparent from the following description taken in conjunction with the accompanied drawings, in which: 
         FIG. 1  is a block diagram illustrating a structure of a liquid crystal display device in a first embodiment of the present invention; 
         FIG. 2  is a block diagram illustrating a structure of a data driver of the liquid crystal display device in the first embodiment; 
         FIG. 3  is a detailed diagram illustrating the structure of the data driver in the first embodiment; 
         FIG. 4  is a block diagram illustrating a structure of a data processing section within the data driver in the first embodiment; 
         FIG. 5A  is a schematic circuit diagram illustrating a preferred structure of operational amplifiers within the data driver in the first embodiment; 
         FIG. 5B  is a schematic circuit diagram illustrating another preferred structure of operational amplifiers within the data driver in the first embodiment; 
         FIG. 6  is a timing chart illustrating an operation of the data driver in the first embodiment; 
         FIG. 7  is a schematic diagram illustrating an operation of the data processing section and a control data latch within the data driver in the first embodiment; 
         FIG. 8  is a schematic diagram illustrating an operation of the data processing section and the control data latch of the data driver in the first embodiment; 
         FIG. 9  is a timing chart illustrating an exemplary operation of the data driver in the first embodiment; 
         FIG. 10  is a block diagram illustrating a structure of a data driver of a liquid crystal display device in a second embodiment of the present invention; 
         FIG. 11  is a block diagram illustrating a structure of the data driver of the liquid crystal display device in the second embodiment; 
         FIG. 12  is a timing chart illustrating an operation of the data driver in the second embodiment; 
         FIG. 13  is a block diagram illustrating a structure of a data driver of a liquid crystal display device in a third embodiment; 
         FIG. 14  is a block diagram illustrating a structure of the data driver in the third embodiment; and 
         FIG. 15  is a block diagram showing another configuration of the data driver in the third embodiment. 
     
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The invention will be now described herein with reference to illustrative embodiments. Those skilled in the art would recognize that many alternative embodiments can be accomplished using the teachings of the present invention and that the invention is not limited to the embodiments illustrated for explanatory purposed. It should be noted that same or similar reference numerals denote same, corresponding or similar elements in the drawings. 
     First Embodiment 
     1. Overall Structure of LCD Device 
       FIG. 1  is a block diagram illustrating a structure of a liquid crystal display device  10  in a first embodiment of the present invention. The liquid crystal display device  10  is composed of an LCD (liquid crystal display) panel  1 , an LCD controller  2 , a plurality of data drivers  3  (one shown), a gate driver  4  and a standard grayscale voltage generator  5 . The LCD panel  1  includes data lines X 1  to X n  (n is an even number of 2 or more), gate lines Y 1  to Y m  (m is a natural number of 2 or more) and pixels P provided at respective intersections of the data lines and the gate lines. For better understanding the figure, only two of the pixels are shown in  FIG. 1 . In the following explanations, a pixel provided at an intersection of the data line X j  and the gate line Y 1  is referred to as pixel P j,i . Each pixel P j,i  has a pixel electrode  1   b  opposed to a common electrode  1   a  and a TFT (thin film transistor)  1   c . When a data signal is provided onto the data line X j  with the TFT  1   c  of the pixel P j,i  turned on, the data signal is applied to a liquid crystal capacitor within the pixel P j,i  (that is, a capacitor composed of the common electrode  1   a  and the pixel electrode  1   b ). 
     The LCD controller  2  controls the data drivers  3  and the gate driver  4  to display a desired image on the LCD panel  1 . In detail, the LCD controller  2  receives pixel data from an image processing LSI  6  such as a CPU (central processor unit) and a DSP (digital signal processor), and transfers the received pixel data to the data drivers  3 . The pixel data indicate graylevels of the respective pixels of the LCD panel  1 . The pixel data associated with the pixel P j,i  is referred to as pixel data D j,I , hereinafter. The LCD controller  2  additionally receives various control signals from the image processing LSI  6 , including a vertical sync signal V sync , a horizontal sync signal H sync , a data enable signal DE, a clock signal DCLK and other control signals, and generates data driver control signals  7  for controlling the data drivers  3 , and gate driver control signals  8  for controlling the gate driver  4 , in response to the control signals received from the image processing LSI  6 . In this embodiment, the data driver control signals  7  include a start pulse signal SPR, a shift direction instructing signal R/L, a clock signal CLK, a latch signal STB, and a polarity signal POL. The start pulse signal SPR is a signal allowing the data drivers  3  to latch the pixel data, and the shift direction instructing signal R/L is used to control the latching of the pixel data by the data drivers  3 . The latch signal STB is used to control data transfer within the data drivers  3 , and the polarity signal POL is used to determine the polarities of the data signals fed to the respective data lines. 
     Each data driver  3  are designed to drive the data lines X 1  to X n  within the LCD panel  1  in response to the pixel data received form the LCD controller  2  and the data driver control signals  7 . In detail, during a j-th horizontal period in which pixels P j, 1  to P j, n  of a j-th line are driven, the data driver  3  drives the data line X 1  to X n  in response to pixel data D j, 1  to D j, n , respectively. Grayscale voltages V 1  to V 2M  received from the standard grayscale voltage generator  5  are used to drive the data line X 1  to X n . M is a number of allowed grayscale levels of the pixels. When the pixel data D j, i  is p-bit data, M is 2p. The grayscale voltages V 1  to V M  have a positive polarity with respect to the common potential V COM  (i.e. the potential of the common electrode  1   a ), satisfying the following formula:
 
 V   1   &gt;V   2   &gt; . . . &gt;V   M &gt;0.
 
     Meanwhile, grayscale voltages V N+1  to V 2M  have a negative polarity, satisfying the following formula:
 
0 &gt;V   M+1   &gt;V   M+2   &gt; . . . &gt;V   2M .
 
     When the data lines X 1  to X n  are driven to the positive potential levels, grayscale voltages are selected from the grayscale voltages V 1  to V M  for the respective data lines X 1  to X n , so that the data lines X 1  to X n  are driven to the positive potential levels corresponding to the selected grayscale voltages. When the data lines X 1  to X n  are driven to the negative potential levels, grayscale voltages are selected from the grayscale voltages V M+1  to V 2M  for the respective data lines X 1  to X n  so that the data lines X 1  to X n  are driven to the negative potential levels corresponding to the selected grayscale voltages. 
     The gate driver  4  drives the gate lines Y 1  to Y m  in response to the gate driver control signals  8  received from the LCD controller  2 . 
     2. Configuration of Data Driver 
       FIG. 2  is a block diagram illustrating a structure of the data drivers  3 . The data drivers  3  are designed to be adapted to a dot inversion drive in which polarities of the data signals are inverted with spatial intervals of one pixel. In other words, the data driver  3  is configured to drive a pair of data lines X 2k−1  and X 2k  with data signals of opposite polarities. 
     More specifically, each data driver  3  includes a shift register circuit  11 , a data register circuit  12 , a latch circuit  13 , a drive capability switching circuit  30 , an input-side switch circuitry  14 , a level shift circuit  15 , a decoder (D/A converter)  16 , a driver output stage  17 , an output-side switch circuitry  18 , a grayscale voltage buffer  19  and output terminals  20 , to  20 , that are connected to the data lines X 1  to X n , respectively. The data register circuit  12  includes registers  12   1  to  12   n , and the latch circuit  13  includes latches  13   1  to  13   n  connected to the outputs of registers  12   1  to  12   n , respectively. The input-side switch circuitry  14  includes switch circuits  14   1  to  14   n/2 . One switch circuit  14   i  is provided for every two latches  13   2i−1 , and  13   2i . The level shift circuit  15  includes level shifters  15   1  to  15   n . The decoder  16  includes selectors  16   1  to  16   n  that are connected to the outputs of the level shifters  15   1  to  15   n . The driver output stage  17  includes operational amplifiers  17   1  to  17   n . The output-side switch circuitry  18  includes switch circuits  18   1  to  18   n/2 , One switch circuit  17   i  is provided for every two operational amplifiers  18   2i−1  and  18   2i . The output-side switch circuitry  18  further includes short-circuit switches  21   1  to  21   n/2 . One of short-circuit switch  21   i  is provided for every two output terminals  20 . The grayscale voltage buffer  19  includes voltage followers  19   a  and  19   b.    
     The shift register circuit  11  is designed to generate trigger pulse signals SR 1  to SR n  to allow the data register circuit  12  to latch the pixel data. The shift register circuit  11  sequentially activates the trigger pulse signals SR 1  to SR n  during each horizontal period. More specifically, the shift register circuit  11  is composed of n-bit shift registers having parallel outputs, operating in response to the start pulse signal SPR, the shift direction instructing signal R/L and the clock signal CLK. When the start pulse signal SPR is activated, a bit of logical “1” is shifted within the shift register circuit  11  in a direction indicated by the shift direction instructing signal R/L, in synchronization with the clock signal CLK, so that the trigger pulse signals SR, to SR, sequentially activated when associated bits take logical “1”. When the shift direction instructing signal R/L is placed in the “H” level, the trigger pulse signals SR 1 , SR 2 , . . . SR n  are activated in this order. When the shift direction instructing signal R/L is placed in the “L” level, the trigger pulse signals are activated in the opposite order. Since the LCD panel  1  is driven by the multiple data drivers  3 , a specific data driver  3  is designed to activate a start pulse signal SPL at the same timing as the trigger pulse signal SR n , and to feed the start pulse signal SPL to the adjacent data driver  3 . The adjacent data driver  3  uses the start pulse signal SPL received as the start pulse signal SPR therewithin. 
     The data register circuit  12  latches the pixel data received from an LCD controller  2  into the registers  12   1  to  12   n , in response to the trigger pulse signals SR 1  to SR n , respectively. In detail, the pixel data D j,1  to D j,n  associated with the pixels P j,1  to P j,n  in the j-th line are latched into the registers  12   1  to  12   n , respectively in response to the trigger pulse signals SR 1  to SR n . 
     The latch circuit  13  is responsive to the latch signal STB for latching the pixel data from the data register circuit  12  into the latches  13   1  to  13   n . The pixel data stored in the latches  13   1  to  13   n  are used to drive the data lines X 1  to X n  in the current horizontal period. It should be noted that the pixel data latched into the data register circuit  12  is a pixel data used to drive the data lines X 1  to X n  in the following horizontal period. 
     The input-side switch circuitry  14  switches electrical connections between the latches  13   1  to  13   n  and the level shifters  15   1  to  15   n  in response to the polarity signal POL. In detail, as shown in  FIG. 3 , each switch circuit  14   k  in the input-side switch circuitry  14  includes four contact switches  22  to  25 . The contact switch  22  is connected between the latch  13   2k−1  and the level shifter  15   2k−1  and the contact switch  23  is connected between the latch  13   2k  and the level shifter  15   2k  on the other hand, the contact switch  24  is connected between the latch  132   k−1  and the level shifter  15   2k  and the contact switch  25  is connected between the latch  13   2k  and the level shifter  15   2k−1 . The switch circuit  14   k  thus configured provides electrical connections between one of the latches  13   2k−  1 and  13   2k  and the input of the level shifters  15   2k−1 , and between the other and the input of the level shifter  15   2k . 
     Referring back to  FIG. 2 , the level shift circuit  15 , the decoder  16 , and the driver output stage  17  are a circuitry which generates data signals in response to the pixel data received from the latches  13   1  to  13   n . The level shift circuit  15 , the decoder  16  and the driver output stage  17  are divided into two sections: a section generating positive data signals and a section generating negative data signals. The odd numbered level shifters  15   1 ,  15   3 , . . .  15   n−1 , selectors  16   1 ,  16   3 , . . . ,  16   n−1 , and operational amplifier  17   1 ,  17   3 , . . .  17   n−1  are used to generate the positive data signals. On the other hand, the even-numbered level shifters  15   2 ,  15   4 , . . .  15   n , selectors  16   2 ,  16   4 , . . .  16   n , and operational amplifier  17   2 ,  17   4 , . . . ,  17   n  are used to generate the negative data signals. 
     More specifically, as shown in  FIG. 3 , the odd-numbered level shifter  15   2k−1  converts the output signal level of the latch connected thereto (i.e. the latch  13   2k−1  or the latch  13   2k ) to the input signal level of the selector  16   2k−1 . The selector  16   2k−1  is provided with the positive grayscale voltages V 1  to V M  through the voltage follower  19   a . The selector  16   2k−1  selects one of the grayscale voltages V 1  to V M  in response to the pixel data received from the latch connected thereto, and provide the selected grayscale voltage to the operational amplifier  17   2k−1 . The grayscale voltage selected by the selector  16   2k−1  increases as the increase in the value of the associated pixel data (i.e. the grayscale level of the associated pixel). The operational amplifier  17   2k−1  generates a data signal of a positive level in response to the provided grayscale voltage. The voltage level of the data signal generated by the operational amplifier  17   2k−1  is increased as the increase in the value of the associated pixel data (i.e. the grayscale level of the associated pixel). 
     Correspondingly, the even-numbered level shifter  15   2k  converts the output signal level of the latch connected thereto (i.e. the latch  13   2k−1  or the latch  13   2k ) to the input signal level of the selector  16   2k . The selector  16   2k  is provided with negative grayscale voltages V M+1  to V 2M  (0&gt;V M+1 &gt;V M+2 &gt; . . . &gt;V 2M ) through the voltage follower  19   b . The selector  16   2k  selects one of the grayscale voltages V M+1  to V 2M  in response to the pixel data received from the latch connected thereto, and provides the selected grayscale voltage to the operational amplifier  17   2k . The grayscale voltage selected by the selector  16   2k−1  decreases as the increase in the value of the associated pixel data (i.e. the grayscale level of the associated pixel). The operational amplifier  17   2k  generates a data signal having a negative level in response to the provided grayscale voltage. The voltage level of the data signal generated by the operational amplifier  17   2k  decreases as the increase of the value of the associated pixel data (i.e. the grayscale level of the associated pixel). 
     The output-side switch circuitry  18  switches electrical connections between the outputs of the operational amplifier  17   1  to  17   n  and the output terminals  20   1  to  20   n  in response to the polarity signal POL. As shown in  FIG. 3 , each switch circuit  18   k  within the output-side switch  18  includes four contact switches  26  to  29 . The contact switch  26  is connected between the operational amplifier  17   2k−1  and the output terminal  20   2k−1 , and the contact switch  27  is connected between the operational amplifier  17   2k  and the output terminal  20   2k . On the other hand, the contact switch  28  is connected between the operational amplifier  17   2k−1  and the output terminal  20   2k , and the contact switch  29  is connected between the operational amplifier  17   2k  and the output terminal  20   2k−1 . The switch circuit  18   k  thus configured provides electrical connections between one of the operational amplifiers  17   2k−1  and  17   2k  and the output terminals  20   2k−1 , and between the other of the operational amplifier  17   2k−1  and  17   2k  and the output terminal  20   2k . 
     The output-side switch circuitry  18  is further designed to short-circuit a pair of adjacent output terminals  20  (that is a pair of adjacent data lines). When the latch signal STB is activated during a blanking period which is prepared at the beginning of each horizontal period, the short-circuit switch  21   k  in the output-side switch circuitry  18  short-circuits the adjacent output terminals  20   2k−1  and  20   2k  (that is, the data lines X 2k−1  and X 2k ). 
     In the data drivers  3  thus configured, the polarities of data signals fed to the output terminal  20   1  to  20   n  (that is, the data lines X 1  to X n ) are switched in accordance with the polarity signal POL. The polarity switching is achieved by the input-side switch circuitry  14  and the output-side switch circuitry  18 . When the polarity signal POL is pulled up to the “H” level, the output-side switch circuitry  18  connects the odd-numbered operational amplifier  17   1 ,  17   3 , . . . to the odd-numbered output terminals  20   1 ,  20   3 , . . . (i.e. the odd-numbered data lines X 1 , X 3 , . . . ) , and connects the even-numbered operational amplifier  17   2 ,  17   4 , . . . to the even-numbered output terminals  20   2 ,  20   4 , . . . (i.e. the even-numbered data lines X 2 , X 4 , . . . ). Therefore, the odd-numbered data lines X 1 , X 3 , . . . are driven by positive data signals, and the even-numbered data lines X 2 , X 4 , . . . are driven by negative data signals. When the polarity signal POL is pulled-down to the “L” level, the connections are switched vice versa. The input-side switch circuitry  14  switches the electrical connections between the latches  13   1  to  13   n  and the selectors  16   1  to  16   n  in accordance with the connections between the outputs of the operational amplifiers  17   1  to  17   n  and the data lines X 1  to X n . Among the pixel data stored in the latches  13   1  to  13   n , the pixel data associated with to the data lines driven by the positive data signals are transferred to the-odd numbered selectors  16   1 ,  16   3 , . . . , and the pixel data associated with the data lines driven by the negative data signals are transferred to the even-numbered selectors  16   2 ,  16   4 , . . . . The input-side switch circuitry  14  is operated to achieve such connection switching. 
     In one aspect, the liquid crystal display device  10  in this embodiment is directed to optimize the control of the drive capabilities of the operational amplifiers  17   1  to  17   n  within the data drivers  3  for reducing power consumption of the liquid crystal display device  10 . More specifically, the drive capabilities of the operational amplifiers  17   2k−1  and  17   2k  are optimized so as to be driven in accordance with the potential level of the data lines X 2k−1  and X 2k  when the data lines X 2k−1  and X 2k  are short-circuited during the blanking period within each horizontal period, in this embodiment. 
     In detail, the drive capability of the operational amplifier  17   2k−1  (or the operational amplifier  17   2k ) which drives the data line X 2k−1  is reduced in the case that the difference is small between the potential level of the data lines X 2k−1  and X 2k  when the data lines X 2k−1  and X 2k  are short-circuited, and the potential level to which the data line X 2k−1  should be driven thereafter. This effectively avoids unnecessary power consumption in the operational amplifier  17   2k−1  Correspondingly, the drive capability of operational amplifier  17   2k−1  (or the operational amplifier  17   2k ) is increased in the case that the difference is large between the electrical potential of the data lines X 2k−1  and X 2k  when the data lines X 2k−1  and X 2k  were short-circuited, and the potential level to which the data line X 2k−1  should be driven thereafter. Increasing the drive capability is important for reducing the time of duration required for driving the data line X 2k−1 . The data line X 2k  is driven in the same manner. 
     In order to achieve the drive capability control, each data driver  3  is provided with the drive capability switching circuit  30  which generates control data for controlling the drive capabilities of the operational amplifiers  17   1  to  17   n . The operational amplifiers  17   1  to  17   n  are designed so that that the drive capabilities thereof are variable or controllable in response to the control data received from the drive capability switching circuit  30 . A detailed description is given of the drive capability switching circuit  30  and the operational amplifiers  17   1  to  17   n  in the following. 
     3. Structure of Drive Capability Switching Circuit and Operational Amplifiers 
     The drive capability switching circuit  30  includes data processing sections  31   1  to  31   n/2  and control data latches  32   1  to  32   n . One data processing section  31   k  is provided for every two data lines. The control data latches  32   1  to  32   n  are respectively associated with the operational amplifiers  17   1  to  17   n . The data processing sections  31   1  to  31   n/2  have a function to generate control data for controlling the drive capabilities of the operational amplifiers  17   1  to  17   n . The control data latches  32   1  to  32   n  transfer the generated control data to the operational amplifiers  17   1  to  17   n . 
       FIG. 4  is a circuit diagram partially illustrating the structure of the drive capability switching circuit  30 , especially illustrating the portion associated with the data processing section  31   k  and the control data latches  32   2k−1  and  32   2k . The data processing section  31   k  generates a pair of control data AS 2k−1  and AS 2k  used for controlling the driving capabilities of the operational amplifiers  17   2k−1  and  17   2k . The data processing section  31   k  sends one of the control data AS 2k−1  and AS 2k  to the data control latch  32   2k−1 , and sends the other to the data control latch  32   2k . The control data latch  32   2k−1  latches the control data from the data processing section  31   k  in response to the latch signal STB, and transfers the latched control data to the operational amplifier  17   2k−1 . Correspondingly, the control data latch  32   2k  latches the control data from the data processing section  31   k  in response to the latch signal STB, and transfers the latched control data to the operational amplifier  17   2k . 
     In detail, each data processing section  31   k  includes a potential difference calculation circuit  33 , control data registers  34  and  35 , and a switch circuit  36 . The potential difference calculation circuit  33  generates the control data AS 2k−1  and AS 2k  in response to the differences between the potential level of the data lines X 2k−1  and X 2k  when the data lines X 2k−1  and X 2k  are short-circuited during the blanking period of the next horizontal period, and the potential levels to which the data lines X 2k−1  and X 2k  are to be driven in the next horizontal period. Specifically, the potential difference calculation circuit  33  receives pixel data of the current horizontal period from the latches  13   2k−1  and  13   2k  in the latch circuit  13 , and receives pixel data of the next horizontal period from the registers  12   2k−1  and  12   2k  in the data register circuit  12 . The potential difference calculation circuit  33  then generates the control data AS 2k−1  and AS 2k  on the basis of the received pixel data, in order to control the driving capabilities of the operational amplifiers  17   2k−1  and  17   2k . More specifically, the control data AS j,2k−1  and AS j,2k  used for driving the pixels D j,2k−1  and D j,2k  during the j-th horizontal period are calculated as follows:
 
 AS   j,2k−1 =|( D   j−1,2k   −D   j−1,2k−1 )/2− D   j,2k−1 |,  (1a)
 
and
 
 AS   j,2k =|( D   j−1,2k−1   −D   j−1,2k )/2− D   j,2k |.  (1b)
 
     The control data AS j,2k−1  and AS j,2k  have values corresponding to the differences between the electrical potential of the data lines X 2k−1  and X 2k  when short-circuited in the blanking period of the j-th horizontal period, and the potential levels to which the data lines X 2k−1  and X 2k  are respectively driven during the j-th horizontal period. In detail, (D j−1,2k −D j−1,2k−1 )/2 in Formula (1a) represents the potential level of the data lines X 2k−1  and X 2k  short-circuited, and D j,2k−1  in Formula (1a) represents the potential level to which the data lines X 2k−1  is to be driven thereafter. Correspondingly, (D j−1,2k−1 −D j−1,2k )/2 in Formula (1b) represents the potential level of the data lines X 2k−1  and X 2k  when the data lines X 2k−1  and X 2k  are short-circuited, and D j, 2k  in Formula (1b) represents the potential level to which the data line X 2k  is to be driven thereafter. As described below, increased drive capabilities are given to the operational amplifiers  17   2k−1  and  17   2k  as the increase in the values of the control data AS j,2k−1  and AS j,2k . Optimization of controlling the drive capabilities of the operational amplifiers  17   2k−1  and  17   2k  is thus achieved. 
     In the strict sense, the potential levels of the data lines are not proportional to the grayscale level values indicated in the pixel data. Instead, the association of the potential levels of the data lines with the grayscale level value indicated in the pixel data is expressed by a curved line so-called “gamma curve”. In order to achieve more proper control based on the difference between the potential level of the data lines X 2k−1  and X 2k  when short-circuited and the potential levels to which the data lines X 2k−1  and X 2k  are driven during the j-th horizontal period, the control data AS j, 2k−1  and AS j, 2k  is preferably determined by the following formulae:
 
 AS   j, 2k−1 =|{γ( D   j−1, 2k )+γ( D   j−1, 2k−1 )}/2−γ( D   j, 2k−1 )|,  (1a)′
 
 AS   j, 2k =|{γ( D   j−1, 2k )+γ( D   j−1, 2k−1 )}/2−γ( D   j, 2k )|,  (1b)′
 
where γ(D j,i ) is the potential level associated with the pixel data D j, i  in the gamma curve. Although the calculation in accordance with the gamma curve is preferable, it should be also noted that the above-mentioned calculation based on formulae (1a) and (1b) is advantageous for simplicity in implementation.
 
     The control data registers  34  and  35  latch the control data AS 2k−1  and AS 2k , respectively, in response to the falling of the trigger pulse signal activated at the latest timing among the trigger pulse signals SR 1  to SR n . This operation addresses completing the calculation of the control data AS 2k−1  and AS 2k  by the potential difference calculation circuit  33 , and the latching of the control data AS 2k−1  and AS 2k  into the control data registers  34  and  35  before capturing the pixel data of the next horizontal period stored in the data register circuit  12  into the latches  13   1  to  13   n  in response to the latch signal STB. 
     The switch circuit  36  is responsive to the polarity signal POL for switching electrical connections between the control data registers  34  and  35  and the control data latches  32   2k−1  and  32   2k . In detail, the switch circuit  36  includes four contact switches: contact switches  37 ,  38 ,  39  and  40 . The contact switch  37  is connected between the control data register  34  and the control data latch  32   2k−1 , and the contact switch  38  is connected between the control data register  35  and the control data latch  32   2k . On the other hand, the contact switch  39  is connected between the control data register  34  and the control data latch  32   2k , and the contact  40  is connected between the control data register  35  and the control data latch  32   2k−1 . The switch circuit  36  thus configured transfers one of the control data AS 2k−1  and AS 2k  latched by the control data registers  34  and  35  to the control data latch  32   2k−1 , and transfers the other to the control data latch  32   2k . The transfer destinations of the control data AS 2k−1  and AS 2k  are switched in response to the polarity signal POL. The necessity of the switch circuit  36  is based on the fact that the transfer destinations of the pixel data stored in the latches  13   2k−1  and  13   2k  of the latch circuit  13  are switched by the switch circuit  14   k . When the pixel data D j, 2k−1  are transferred to the selector  16   2k  and the operational amplifier  17   2k  is driven in response to the pixel data D j, 2k−1 , f or example, the control data AS 2k−1  associated with the pixel data D j, 2k−1  is required to be transferred to the operational amplifier  17   2k  through the control data latch  32   2k . 
     The control data transferred to the control data latch  32   2k−1  is further transferred to the operational amplifier  17   2k−1  for controlling the drive capability of the operational amplifier  17   2k−1 . Correspondingly, the control data transferred to the control data latch  32   2k  is further transferred to the operational amplifier  17   2k  for controlling the drive capability of the operational amplifier  17   2k . 
     The drive capability of the operational amplifiers  17   1  to  17   n  is increased as the increase in the values of the control data transferred thereto, to thereby configure the respective operational amplifiers  17   1  to  17   n  with appropriate drive capabilities depending on the differences between the potential levels of the corresponding pairs of the adjacent data lines when short-circuited and the potential levels to which the respective data lines are driven thereafter. When the operational amplifier  17   2k−1  is driven in response to the pixel data D j, 2k−1  during the j-th horizontal period, for example, the control data AS j, 2k−1  fed to the operational amplifier  17   2k−1  is increased as the increase in the difference between the potential level of the data lines X 2k−1  and X 2k  when the data lines X 2k−1  and X 2k  are short-circuited during the blanking period and the potential level to which the data line X 2k−1  is driven thereafter, and vice versa. The drive capability of the operational amplifier  17   2k−1  is increased in accordance with the increase of the control data AS j, 2k−1  to achieve the optimization of the drive capability of the operational amplifiers  17   2k−1 . 
       FIG. 5A  is a circuit diagram illustrating an exemplary structure of the operational amplifiers  17   1  to  17   n  adapted to the above-described operation. Each operation amplifier  17   2k−1  ( 17   2k ) includes a bias voltage generating circuit  41 , a current source  42  and a voltage follower  43 . The bias voltage generating circuit  41  generates a bias voltage Vb in response to the control data AS received from the control data latches  32   2k−1  (or  32   2k ). The generation of the bias voltage Vb is increased in accordance with the increase of the control data AS. The current source  42  is responsive to the bias voltage Vb for feeding a bias current Ib to the voltage follower  43 . The bias current Ib is increased as the increase in the bias voltage Vb. The voltage follower  43  receives the bias current Ib to drive the output terminal  20   2k−1  (or  20   2k ), that is, the data line X 2k−1  (or X 2k ), to the potential level corresponding to the grayscale voltage received from the selector  16   2k−1  (or  16   2k ). The voltage follower  43  incorporates a differential amplifier and an output stage (not shown), which operate on the bias current Ib. Accordingly, the drive capability of the voltage follower  43  is increased as the increase in the bias current Ib. In the operational amplifier  17   2k−1  ( 17   2k ) thus configured, the increase of the control data AS increases the bias current Ib, and thereby increases the drive capability of the operational amplifier  17   2k−1  ( 17   2k ). 
       FIG. 5B  is a circuit diagram illustrating another exemplary structure of the operational amplifiers  17   1  to  17   n . In the operational amplifiers in  FIG. 5B , a plurality of switches SW 1  to SWq and constant current sources  44   1  to  44   q  generating currents of the same intensity are provided in replace of the bias voltage generating circuit  41  and the current source  42 . The switch SW i  and the constant current source  44   i  are connected in series between the voltage follower  43  and a ground terminal. Selected one(s) out of the switches SW 1  to SWq is turned on in response to the control data AS, the number of the switches turned on being determined in response to the value of the control data AS. The voltage follower  43  is fed with the bias current Ib having the intensity proportional to the number of the switches SW that are turned on. Accordingly, in the structure shown in  FIG. 5B , the bias current Ib is also increased as the increase in the control data AS, and consequently the drive capability of the operational amplifier  17   2k−1  ( 17   2k ) is increased. 
     4. Operation of Data Driver 
     A detailed explanation will be given of an exemplary operation of the data driver  3  in the following, in particular of a procedure of generating control data used for the control of the operational amplifiers  17   1  to  17   n  in the j-th horizontal period and a procedure of controlling the drive capabilities on the basis of the control data.  FIG. 6  is a timing chart illustrating the operation of the data driver  3  during a (j−1)-th horizontal period (i.e. a period in which pixels in the (j−1)-th line are driven) and the j-th horizontal period. 
     Control data used in the j-th horizontal period for controlling the drive capabilities of the operational amplifiers  17   1  to  17   n  are generated in the (j−1)-th horizontal period. Such generating procedure of the control data is preferable for the prompt control of the drive capabilities of the operational amplifiers  17   1  to  17   n  in the j-th horizontal period; it is not preferable to generate the control data used in the j-th horizontal period in the current j-th horizontal period, since it may cause undesirable delay for the operational amplifiers  17   1  to  17   n  to start outputting the data signals in the j-th horizontal period. 
     In detail, when the latch signal STB is activated in the blanking period within the (j−1)-th horizontal period, every adjacent two data lines are short-circuited by the short-circuit switches  21   1  to  21   n . Further, in response to the activation of the latch signal STB, pixel data D j−1,1  to D j−1,n  used for generating data signals in the (j−1)-th horizontal period are transferred from the data register circuit  12  to the latch circuit  13 . The data lines X 1  to X n  are driven during the (j−1)-th horizontal period in response to the pixel data D j−1,1  to D j−1,n  that are transferred to the latch circuit  13 . The polarities of the data signals fed to the respective data lines are determined by the polarity signal POL. In this embodiment, in response to the polarity signal POL being set to the “H” level, data signals of the positive polarity are fed to the odd-numbered data lines X 1 , X 3 , . . . , and data signals of the negative polarity are fed to the even-numbered data lines X 2 , X 4 , . . . . 
     While the data lines X 1  to X n  are driven during the (j−1)-th horizontal period, pixel data used for driving the data lines X 1  to X n  in the j-th horizontal period are transferred to the data register circuit  12  from the LCD controller  2 . More specifically, in response to the activation of the start pulse signal SPR, the trigger pulse signals SR 1  to SR n  are sequentially activated, and then the pixel data D j,1  to D j,n  are sequentially transferred in synchronization of the sequential activations of the trigger pulse signals SR 1  to SR n . This results in that the registers  12   1  to  12   n  store the pixel data D j,1  to D j,n  within the data register circuit  12 . 
     After the pixel data D j, 1  to D j, n  are stored in the registers  12   1  to  12   n , the data processing sections  31   1  to  31   n  within the drive capability switching circuit  30  calculate control data used in the j-th horizontal period. In detail, as shown in  FIG. 7 , the potential difference calculation circuit  33  in the data processing section  31   k  calculates the control data AS j, 2k−1  and AS j, 2k  from the pixel data D j, 2k−1  and D j, 2k−1  stored in the registers  12   2k−1  and  12   2k , and from the pixel data D j−1, 2k−1  and D j−1, 2k−1  stored in the latches  13   2−k  and  13   2k , on the basis of Formulae (1a) and (1b) above-described. 
     The calculated control data are latched to the control data registers  34  and  35  in the data processing sections  31   1  to  31   n  at the end of the (j−1)-th horizontal period. Specifically, in response to the falling of the trigger pulse SR n , which is activated at the latest timing among the trigger pulses SR 1  to SR n , the control data AS j,2k−1  is latched into the data register  34  in the data processing section  31   k , and the control data AS j,2k  is latched into the control data register  35 . 
     When the j-th horizontal period is started, as shown in  FIG. 6 , the polarity signal POL is inverted in the blanking period, and then the latch signal STB is activated. In response to the activation of the latch signal STB, ever two adjacent data lines are short-circuited by the short-circuit switches  21   1  to  21   n . In detail, the data lines X 2k−1  and X 2k  are short-circuited by the short-circuit switch  21   k . The potential level of the data lines X 2k−1  and X 2k  after the short-circuit is the average of potential levels to which the data lines X 2k−1  and X 2k  are driven in the previous (j−1)-th horizontal period. 
     Moreover, as shown in  FIG. 7 , the control data stored in the control data registers  34  and  34  within the data processing section  31   1  to  31   n  are transferred to the operational amplifiers  17   1  to  17   n  through the control data latches  32   1  to  32   n . In detail, when the latch signal STB is activated in the blanking period of the j-th horizontal period, the control data AS j,2k−1  stored in the control data register  34  within the data processing section  31   k  is transferred to selected one of the control data latches  32   2k−1  and  32   2k , and the control data AS j, 2k  stored in the control data register  35  within the data processing section  31   k  is transferred to the other of the control data latches  32   2k−1  and  32   2k . 
     The transfer destinations of the control data are switched in accordance with the polarity signal POL. In this embodiment, as shown in  FIG. 7 , the control data AS j,2k−1  stored in the control data register  34  within the data processing section  31   k  is transferred to the control data latch  32   2k , and the control data AS j,2k  stored in the control data register  35  is transferred to the control data latch  32   2k−1 , in response to the polarity signal POL being set to the “L” level. As shown in  FIG. 8 , it goes vice versa when the polarity signal POL is set to the “H” level. Switching the transfer destinations of the control data in accordance with the polarity signal POL is to provide the operational amplifiers with appropriate control data associated with the transfer destinations of the pixel data. In the operation shown in  FIG. 7 , the control data AS j,2k−1  is transferred to the operational amplifier  17   2k  in accordance with tha fact that the operational amplifier  17   2k  is driven in response to the pixel data D j,2k−1 . 
     The operational amplifiers  17   1  to  17   n  are configured with drive capabilities corresponding to the transferred control data. In the operation shown in  FIG. 7 , the operational amplifier  17   2k−1  is fed with the control data AS j,2k , and the drive capability of the operational amplifier  17   2k−1  is controlled in accordance with the control data AS j, 2k . Correspondingly, the operational amplifier  17   2k  is fed with the control data AS j, 2k−1 , and the drive capability of the operational amplifier  17   2k  is controlled in accordance with the control data AS j, 2k−1 . This achieves optimization in the drive capability control of the operational amplifiers  17   2k−1  and  17   2k , and thus thereby effectively reduces power consumption of the data driver  3 . 
       FIG. 9  is a timing chart showing an example of the operation of the data driver  3 . In this example, it is assumed that the data line X 2k−1  is driven to a positive potential level V x11  and the data line X 2k  is driven to a negative potential level V x21  in the j−1-th horizontal period. When the data lines X 2k−1  and X 2k  are short-circuited in the blanking period of the following j-th horizontal period, the potential level of the data lines X 2k−1  and X 2k  is set to the average level V r2 [=(V x11 +V x21 )/2]. Thereafter, in the j-th horizontal period, the data line X 2k−1  is driven to the negative potential level V x21  and the data line X 2k  is driven to the positive potential level V x22 . In accordance with the small difference ΔV x21  between the average level V r2  and the potential level V x21 , the operational amplifier  17   2k−1  that drives the data line X 2k−1  is set to have a low drive capability, as indicated by the diagonal hatching (lower left to upper right) in  FIG. 9 . The operational amplifiers are configured with a low drive capability if high drive capability is not needed, and thereby the static current consumption, i.e. power consumption in the amplifier is reduced. 
     When the data lines X 2k−1  and X 2k  are short-circuited in the blanking period of the next (j+1)-th horizontal period, the potential level of the data lines X 2k−1  and X 2k  is transitioned to the average level V r3 [=(V x21 +V x22 )/2]. Thereafter, in the (j+1)-th horizontal period, the data line X 2k−1  is driven to a positive potential level V x31  and the data line X 2k  is driven to a negative potential level V x32 . In response to the large difference ΔV x32  between the average level V r3  and the potential level V x32 , the operational amplifier driving the data line X 2k  is configured with a high drive capability, as indicated by the diagonal hatching (upper left to lower right) in  FIG. 9 . The operational amplifiers are configured with a high drive capability if needed, which will result in a prompt driving of the data lines. 
     Second Embodiment 
       FIG. 10  is a block diagram showing an exemplary structure of a liquid crystal display device  10 A in a second embodiment of the present invention. The main difference between the liquid crystal display device  10 A in this embodiment and the liquid crystal display device  10  in the first embodiment is that the generation of the control data AS is implemented by an LCD controller  2 A instead of the data driver  3 A. 
     More specifically, the LCA controller  2 A includes a line memory  51  having a capacity for pixel data of pixels in one line, and a drive capability switching section  52  which generates the control data AS used for controlling the drive capability of the operational amplifier  17   1  to  17   n . The line memory  51  stores the pixel data D j−1,1  to D j−1,n  associated with the pixels in the (j−1)-th line, when the control data AS j, 1  to AS j,n  are calculated, which are used for driving the pixel P j,1  to P j,n  in the j-th horizontal period. When the pixel data D j,1  to D j,n  of the j-th line pixel are provided to the LCD controller  2 A from the image processing LSI  6 , the drive capability switching section  52  generates the control data AS j,1  to AS j,n  from the pixel data D j,1  to D j,n  and the pixel data D j−1,1  to D j−1,n  stored in the line memory  51 . The control data AS j−1,n  to AS j,n  are calculated on the basis of Formulae (1a) and (1b) above-described. The generated control data AS j,1  to AS j,n  are transferred to the data driver  3 A. The transfer of the control data AS j,1  to AS j,n  is carried out in synchronization of the transfer of the pixel data D j,1  to D j,n  to the data driver  3 . 
     In accordance with the fact that the line memory  51  is provided within the LCD controller  2 A and the generation of the control data AS is implemented by the LCD controller  2 A, the structure of the data driver  3 A is changed from that of the data driver  3  in the first embodiment as follows. 
     As shown in  FIG. 11 , the input-side switch circuitry  14  is removed from the data driver  3 A. Instead, the line memory  51  provided in the present embodiment is utilized to switch the order of transferring the pixel data to the data driver  3 A in response to the polarity signal POL. More specifically, as shown in  FIG. 12 , the order of transferring the pixel data D j,1  to D j,n  of the j-th line pixel is switched when the polarity signal POL is set to the “L” level so that the pixel data are transferred to the data driver  3 A in the order of D j,2 , D j,1 , D j,4 , D j,3  . . . . On the other hand, the order of the pixel data transfer is not switched when the polarity signal POL is set to the “H” level; the pixel data are transferred to the data driver  3 A in the order of D j, 1 , D j, 2 , . . . . This achieves an operation equivalent to the operation of the data driver  3  shown in  FIG. 2 , which incorporates the input-side switch circuitry  14 . The structure of the data driver  3 A shown in  FIG. 11 , which excludes the input-side switch circuitry  14 , is preferable for simplifying the structure of the data driver  3 A. 
     In addition, as shown in  FIG. 11 , the data driver  3 A additionally includes control data registers  53   1  to  53   n  and control data latches  54   1  to  54   n . These registers and lathes are provided to transfer the control data AS received from the LCD controller  2 A to the operational amplifiers  17   1  to  17   n  at an appropriate timing. The control data registers  53   1  to  53   n  receive the control data AS from the LCD controller  2 A in response to the trigger pulse signals SR 1  to SR n . The control data latches  54   1  to  54   n  latch the control data AS from the control data registers  53   1  to  53   n  in response to the latch signal STB, and transfer the latched control data AS to the operational amplifiers  17   1  to  17   n . Similarly to the data register circuit  12 , the control data registers  53   1  to  53   n  are used to store the control data AS used in the next horizontal period, while the control data latches  54   1  to  54   n  are used to store the control data used in the current horizontal period. 
     The control data are transferred from the control data latches  54   1  to  54   n  to the operational amplifiers  17   1  to  17   n , and the drive capabilities of the operational amplifiers  17   1  to  17   n  are controlled in accordance with the transferred control data. As is the case of the first embodiment, the drive capability control of the operational amplifiers  17   1  to  17   n  effectively reduces power consumption of the data driver  3 A. 
     Third Embodiment 
     Referring to  FIG. 13 , a data driver  3 B is configured in a third embodiment, so that all the data lines X 1  to X n  are short-circuited during the blanking periods of the respective horizontal periods. More specifically, as shown in  FIG. 14 , (n−1) short-circuit switches  21   1  to  21   (n−1)  are connected between any adjacent data lines X 1  to X n . The short-circuit switches  21   1  to  21   (n−1)  are turned on in the blanking periods of the respective horizontal periods, and the data lines X 1  to X n  are thus short-circuited to have an identical potential level. 
     Accordingly, the calculation method of the control data AS is modified so that the drive capabilities of the operational amplifiers  17   1  to  17   n  are controlled in response to the potential level of the data lines X 1  to X n  when the data lines X 1  to X n  are short-circuited. More specifically, the drive capability switching section  52 B within the LCD controller  2 B calculates the control data AS j,1  to AS j,n  used in the j-th horizontal period according to formulae below: 
                       AS     j   ,       2   ⁢   k     -   1         =              ∑     i   =   1       i   =     n   /   2         ⁢       (       D       j   -   1     ,     2   ⁢   i         -     D       j   -   1     ,       2   ⁢   i     -   1           )     /   n       -     D     j   ,       2   ⁢   k     -   1                  ,           (     2   ⁢   a     )                   AS     j   ,     2   ⁢   k         =              ∑     i   =   1       i   =     n   /   2         ⁢       (       D       j   -   1     ,       2   ⁢   i     -   1         -     D       j   -   1     ,     2   ⁢   i           )     /   n       -     D     j   ,     2   ⁢   k                  ,           (     2   ⁢   a     )               
The first term of Formula (2a) corresponds to the potential level of the data line X 1  to X n  when the data line X 1  to X n  are short-circuited, and the second term (D 1,2k−1 ) of Formula (2a) corresponds to the potential level to which the data line X 2k−1  is driven thereafter. The same applies to Formula (2b).
 
     The calculated control data AS j,1  to AS j,n  are transferred to the data driver  3 B in synchronization of the transfer of the pixel data D j,1  to D j,n . The data driver  3 B controls the drive capabilities of the operational amplifiers  17   1  to  17   n  in the j-th horizontal period by corresponding to the control data AS j,1  to AS j,n . 
     Due to the drive capability control thus described, the drive capabilities of the respective operational amplifiers are appropriately controlled during the j-th horizontal period in response to the differences between the electrical potential of the data lines X 1  to X n , when the data lines X 1  to X n  are short-circuited, and the electrical potential levels to which the respective data lines are driven thereafter. 
     When the liquid crystal display device  10 B is designed so that all the data lines X 1  to X n  are short-circuited, it is preferable to calculate the control data AS j,1  to AS j,n  by the LCD controller  2 B in order to simplify the circuit configuration of the data driver  3 B. As understood from Formulae (2a) and (2b), it is necessary in this embodiment to prepare the pixel data associated with all the data lines X 1  to X n  for the generation of each of the control data AS j,1  to AS j,n . An attempt to implement such calculations inside the data driver  3 B may complicate the circuit configuration of the data driver  3 B. Collective calculation of the control data AS j,1  to AS j,n  in the LCD controller  2 B effectively avoids the complicated circuit configuration of the data driver  3 B. 
     As shown in  FIG. 15 , the data driver  3 B may be configured so that the data lines X 1  to X n  can be provided with an intermediate potential ½ V LCD [=(V 1 +V 2M )/2] through a switch  21   n , when the data driver  3 B is designed so that all the data lines X 1  to X n  can be short-circuited. 
     In this case, the control data AS j,1  to AS j,n  used in the j-th horizontal period are expressed in formulae below, instead of the formulae (1a), (1b), (2a) and (2b):
 
 AS   j,2k−1   =|D   1/2LCD   −D   j,2k−1 |, and  (3a)
 
 AS   j,2k   =|D   1/2LCD   −D   j,2k |,  (3b)
 
where D 1/2LCD  is a fixed grayscale level value corresponding to the intermediate potential ½V LCD . When the intermediate electrical potential ½V LCO  is identical to the common potential V COM , D 1/2LCD  may be set to zero. The control data AS j,1  to AS j,n  are thus calculated so that the drive capabilities of the respective operational amplifiers in the j-th horizontal period are appropriately controlled in response to the differences between the potential level of the data lines X 1  to X n  when the data lines X 1  to X n  are short-circuited, and the potential levels to the respective data lines are driven, thereafter.
 
     CONCLUSION 
     As described above, the liquid crystal display device controls the drive capabilities of the operational amplifiers in response to the differences between the potential level of adjacent two or all of the data lines when they are short-circuited in the blanking period and the potentials to the respective data lines are driven thereafter. This effectively reduces the power consumption of the liquid crystal display device. 
     It is apparent that the present invention is not limited to the above-described embodiments, which may be modified and changed without departing from the scope of the invention. For example, the present invention is not limited to the configuration in which two data lines are short-circuited or the configuration in which all the data lines are short-circuited. In a liquid crystal display device adapted to a dot inversion drive that inverts the polarities of data signals at a spatial cycle of two pixels, for example, the data driver may be designed to short-circuit every four data lines including two data lines driven to positive potential levels and two data lines driven to negative potential levels.