Patent Publication Number: US-2009224330-A1

Title: Semiconductor Memory Device and Method for Arranging and Manufacturing the Same

Description:
REFERENCE TO PRIORITY APPLICATIONS 
     This application, which claims the benefit of Korean Patent Application No. 2008-63617, filed Jul. 1, 2008, is a continuation-in-part application of U.S. patent application Ser. No. 11/953,289 filed on Dec. 10, 2007, which is a continuation of U.S. patent application Ser. No. 11/191,496, filed Jul. 28, 2005, now U.S. Pat. No. 7,315,466. The disclosures of these applications are hereby incorporated herein by reference. 
     REFERENCE TO RELATED APPLICATION 
     This application is related to U.S. patent application Ser. No. 12/408,932 filed on Mar. 23, 2009, the disclosure of which is incorporated herein by reference. 
    
    
     FIELD OF THE INVENTION 
     The present invention relates to integrated circuit devices and, more particularly, to integrated circuit memory devices and methods of manufacturing integrated circuit memory devices. 
     BACKGROUND OF THE INVENTION 
     Conventional semiconductor memory devices may include a memory cell array having a plurality of memory cells, which store data and a peripheral circuit which controls data input/output to/from the memory cell array. A static memory cell (e.g., SRAM cell) includes a plurality of transistors, and a dynamic memory cell (e.g., DRAM cell) includes one transistor and one capacitor. The peripheral circuit may include an inverter, a NAND gate and a NOR gate, where each of the gates includes transistors. In the typical memory cell and peripheral circuit, all of a plurality of transistors are arranged on the same layer above a semiconductor substrate. Thus, as the capacity of the memory cell array (i.e., the number of the memory cells) is increased, the layout area size is also increased, which may lead to large chip size. 
     For the foregoing reason, research has been performed to reduce the layout area size even as a capacity of the memory cell array is increased. For example, a method of reducing layout area size of the memory cell array by stacking transistors in a memory cell has been introduced (see, e.g.,  FIGS. 5A and 6A ). 
     However, if layout area size of the peripheral circuit as well as layout area size of the memory cell array is reduced, the total area size of the semiconductor memory device can be reduced as much. Besides, as transistors that form the memory cell are stacked, the transistors, which form the memory cell, should have different structure. 
     SUMMARY OF THE INVENTION 
     It is an object of the present invention to provide a semiconductor memory device which has a peripheral circuit suitable for a memory cell array having stacked transistors. 
     It is another object of the present invention to provide methods for arranging and manufacturing a semiconductor memory device which has a peripheral circuit suitable for a memory cell array having stacked transistors. 
     A first embodiment of the present invention includes a plurality of inverters including at least one first pull-up transistor and first pull-down transistor and inverting and outputting an input signal, respectively; and a plurality of NAND gates including at least two second pull-up transistor and second pull-down transistor and generating an output signal having a high level if at least one of at least two input signals has a low level, respectively, wherein the at least one first pull-up transistor and first pull-down transistor and the at least two second pull-up transistor and second pull-down transistor are stacked and arranged on at least two layers. 
     A second embodiment of a semiconductor device of the present invention includes a plurality of inverters including at least one first pull-up transistor and first pull-down transistor and inverting and outputting an input signal, respectively; a plurality of NAND gates including at least two second pull-up transistor and second pull-down transistor and generating an output signal having a high level if at least one of at least two input signals has a low level, respectively; and a plurality of NOR gates including at least two third pull-up transistor and third pull-down transistor and generating an output signal having a high level if all of at least two input signals have a low level, respectively, wherein the at least one first pull-up transistor and first pull-down transistor, the at least two second pull-up transistor and second pull-down transistor, and the at least two third pull-up transistor and third pull-down transistor are stacked and arranged on at least two layers. 
     In the first and second aspects of the semiconductor memory devices, the first to third pull-up transistors are PMOS transistors, and the first to third pull-down transistors are NMOS transistors. In the first and second aspects of the semiconductor memory devices, a transistor to be arranged on a first layer is a bulk transistor, and a transistor to be arranged on a second or more layer is a thin film transistor. In the first and second aspects of the semiconductor memory devices, some of the first to third pull-up transistors and some of the first to third pull-down transistors are arranged together on the first layer. Only the first to third pull-up transistors or only the first to third pull-down transistors are arranged on the second or more layer. 
     A third embodiment of a semiconductor memory device of the present invention includes a memory cell array including a plurality of memory cells which are accessed in response to a plurality of word line selecting signals and a plurality of column selecting signals; a row decoder for decoding a row address to generate the plurality of word line selecting signals; and a column decoder for decoding a column address to generate the plurality of column selecting signals, wherein the row (column) decoder includes a plurality of inverters, each of the plurality of inverters includes at least one pull-up transistor and pull-down transistor, the pull-up and pull-down transistors are stacked and arranged on at least two layers. 
     The column (row) decoder includes a plurality of inverters, each of the plurality of inverters includes at least one pull-up transistor and pull-down transistor, and the pull-up and pull-down transistors are stacked and arranged on at least two layers. 
     The plurality of memory cells include a plurality of NMOS transistors, and the plurality of NMOS transistors are stacked and arranged on the at least two layers. The pull-up transistor is a PMOS transistor, and the pull-down transistor is an NMOS transistor. A transistor to be arranged on a first layer is a bulk transistor, and a transistor to be arranged on a second or more layer is a thin film transistor. Some of the pull-up transistors and some of the pull-down transistors are arranged together on the first layer. Only the pull-up transistors or only the pull-down transistors are arranged on the second or more layer. 
     A fourth embodiment of a semiconductor memory device of the present invention includes a memory cell array including a plurality of memory cells which are accessed in response to a plurality of word line selecting signals and a plurality of column selecting signals; a row decoder for decoding a row address to generate the plurality of word line selecting signals; and a column decoder for decoding a column address to generate the plurality of column selecting signals, wherein the row (column) decoder includes a plurality of inverters and a plurality of NAND gates, each of the plurality of inverters includes at least one first pull-up transistor and first pull-down transistor, each of the plurality of NAND gates includes at least two second pull-up transistors and second pull-down transistors, and the first and second pull-up transistors and the first and second pull-down transistors are stacked and arranged on at least two layers. 
     The column (row) decoder includes a plurality of inverters and a plurality of NAND gates, each of the plurality of inverters includes at least one first pull-up transistor and first pull-down transistor, each of the plurality of NAND gates includes at least two second pull-up transistors and second pull-down transistors, the first and second pull-up transistors and the first and second pull-down transistors are stacked and arranged on at least two layers. 
     The plurality of memory cells include a plurality of NMOS transistors, and the plurality of NMOS transistors are stacked and arranged on the at least two layers. The first and second pull-up transistors are PMOS transistors, and the first and second pull-down transistors are NMOS transistors. A transistor to be arranged on a first layer is a bulk transistor, and a transistor to be arranged on a second or more layer is a thin film transistor. Some of the first and second pull-up transistors and some of the first and second pull-down transistors are arranged together on the first layer. Only the first and second pull-up transistors or only the first and second pull-down transistors are arranged on the second or more layer. 
     A fifth embodiment of a semiconductor memory device of the present invention includes a memory cell array including a plurality of memory cells which are accessed in response to a plurality of word line selecting signals and a plurality of column selecting signals; and a peripheral circuit including a row decoder for decoding a row address to generate the plurality of word line selecting signals, a column decoder for decoding a column address to generate the plurality of column selecting signals, and a controller for controlling input/output of data to/from the memory cell array, wherein the peripheral circuit includes a plurality of inverters, a plurality of NAND gates, and a plurality of NOR gates, each of the plurality of inverters includes at least one first pull-up transistor and first pull-down transistor, each of the plurality of NAND gates includes at least two second pull-up transistors and second pull-down transistors, each of the plurality of NOR gates includes at least three third pull-up transistors and third pull-down transistors, and the first to third pull-up transistors and the first to third pull-down transistors are stacked and arranged on at least two layers. 
     The plurality of memory cells include a plurality of NMOS transistors, and the plurality of NMOS transistors are stacked and arranged on the at least two layers. The first to third pull-up transistors are PMOS transistors, and the first to third pull-down transistors are NMOS transistors. A transistor to be arranged on a first layer is a bulk transistor, and a transistor to be arranged on a second or more layer is a thin film transistor. Some of the first to third pull-up transistors and some of the first to third pull-down transistors are arranged together on the first layer. Only the first to third pull-up transistors or only the first to third pull-down transistors are arranged on the second or more layer. 
     A sixth embodiment of a semiconductor device includes a semiconductor substrate having a cell region and a peripheral circuit region; bulk transistors arranged on the semiconductor substrate of the cell region; an interlayer insulator pattern arranged in the cell region to cover the bulk transistors; thin film transistors arranged on the interlayer insulator pattern; a peripheral body pattern arranged to contact the semiconductor substrate of the peripheral circuit region; and peripheral transistors arranged in the peripheral body pattern, the peripheral transistors arranged to be located on the substantially same imaginary horizontal line as the thin film transistors of the cell region. The peripheral body pattern is a single crystal semiconductor structure. The thin film transistors are single crystal thin film transistors. The bulk transistors and the thin film transistors are cell transistors of an SRAM memory cell. 
     The bulk transistors include first and second bulk transistors, the thin film transistors include first and second thin film transistors, and the first and second thin film transistors are arranged to respectively overlap the first and second bulk transistors. The semiconductor device further includes first and second lower thin film transistors respectively arranged between the first and second bulk transistors and the first and second thin film transistors, wherein the first and second lower thin film transistors are arranged to respectively overlap the first and second bulk transistors. 
     The semiconductor device further includes a first node plug for electrically connecting a first ion-doped region of the first bulk transistor, a first ion-doped region of the first lower thin film transistor, and a first ion-doped region of the first upper thin film transistor through the interlayer insulator; and a second node plug for electrically connecting a first ion-doped region of the second bulk transistor, a first ion-doped region of the second lower thin film transistor, and a first ion-doped region of the second upper thin film transistor through the interlayer insulator. The first and second bulk transistors are first and second n-channel driving transistors, respectively, and the first ion-doped regions of the first and second bulk transistors are drain regions. A gate electrode of the first driving transistor is electrically connected to the second node plug, and a gate of the second driving transistor is electrically connected to the first node plug. 
     The first and second lower thin film transistors are respectively first and second p-channel load transistors, the first and second thin film transistors are first and second n-channel transmission transistors, the first ion-doped regions of the first and second lower thin film transistors are drain regions, and the first ion-doped regions of the first and second thin film transistors are source regions. Gate electrodes of the first and second load transistors are arranged to overlap gate electrodes of the first and second driving transistors, the gate electrode of the first load transistor is electrically connected to the second node plug, and the gate electrode of the second load transistor is electrically connected to the first node plug. Gate electrodes of the first and second thin film transistors are electrically connected to each other to form a word line. At least the peripheral transistor includes a metal silicide layer arranged on a surface of a peripheral gate electrode. At least the peripheral transistor includes a metal silicide layer arranged on surfaces of peripheral source and drain regions. 
     A first aspect of an arrangement method of a semiconductor memory device according to the present invention includes stacking and arranging two transmission transistors, two first pull-up transistors, two first pull-down transistors which constitute each of a plurality of memory cells of a memory cell array on at least two layers; and stacking and arranging at least one second pull-up transistors and second pull-down transistors which constitute each of a plurality of inverters of a peripheral circuit and at least two third pull-up transistors and third pull-down transistors which constitute each of a plurality of NAND gates on the least two layers. 
     The first to third pull-up transistors are PMOS transistors, and the first to third pull-down transistors are NMOS transistors. A transistor to be arranged on a first layer is a bulk transistor, and a transistor to be arranged on a second or more layer is a thin film transistor. 
     A transistor to be arranged on the first layer among the at least two layers of the peripheral circuit is one which is possible to be arranged together with some of the second and third pull-up transistors and the second and third pull-down transistors regardless of a type of a transistor to be arranged on the first layer of the memory cell array. Only the second and third pull-up transistors or only the second and third pull-won transistors which have the same type as transistors which are respectively arranged on a second or more layer of the at least two layers of the peripheral circuit are arranged. 
     A second aspect of an arrangement method of a semiconductor memory device according to the present invention includes stacking and arranging two transmission transistors, two first pull-up transistors, two first pull-down transistors which constitute each of a plurality of memory cells of a memory cell array on at least two layers; and stacking and arranging at least one second pull-up transistors and second pull-down transistors which constitute each of a plurality of inverters of a peripheral circuit, at least two third pull-up transistors and third pull-down transistors which constitute each of a plurality of NAND gates, and at least two fourth pull-up transistors and fourth pull-down transistors which constitute each of a plurality of NOR gates on the least two layers. 
     The first to fourth pull-up transistors are PMOS transistors, and the first to third pull-down transistors are NMOS transistors. A transistor to be arranged on a first layer is a bulk transistor, and a transistor to be arranged on a second or more layer is a thin film transistor. 
     A transistor to be arranged on the first layer among the at least two layers of the peripheral circuit is one which is possible to be arranged together with some of the second to fourth pull-up transistors and the second to fourth pull-down transistors regardless of a type of a transistor to be arranged on the first layer of the memory cell array. Only the second to fourth pull-up transistors or only the second to fourth pull-won transistors which have the same type as transistors which are respectively arranged on a second or more layer of the at least two layers of the peripheral circuit are arranged. 
     A first aspect of a method of manufacturing a semiconductor device includes preparing a semiconductor substrate having a cell region and a peripheral circuit region; forming a bulk transistor on the semiconductor substrate of the cell region; forming an interlayer insulator pattern which exposes the semiconductor substrate of the peripheral circuit region on the semiconductor substrate having the bulk transistor; forming a cell body pattern and a peripheral body pattern on the interlayer insulator pattern and the exposed portion of the semiconductor substrate, wherein the peripheral body pattern contacts the exposed portion of the semiconductor substrate; and forming a cell thin film transistor and a peripheral transistor in the cell body pattern and the peripheral body pattern, respectively. 
     The step of forming the cell body pattern and the peripheral body pattern includes forming a semiconductor layer on the semiconductor substrate having the interlayer insulator pattern; and planarizing the semiconductor layer to form a cell semiconductor layer and a peripheral semiconductor layer on the interlayer insulator pattern and the semiconductor substrate of the peripheral circuit region, wherein the peripheral semiconductor layer is thicker than the semiconductor layer. The semiconductor layer is formed of a non-single crystal semiconductor layer. 
     The method of the first aspect further includes crystallizing the semiconductor layer using a solid phase epitaxial layer which employs the semiconductor substrate as a seed layer before or after planarizing the semiconductor layer. The step of forming the interlayer insulator pattern includes forming an interlayer insulator on the semiconductor substrate having the bulk transistor; and patterning the interlayer insulator to form a contact hole which exposes the semiconductor substrate of the peripheral circuit region and a predetermined region of the semiconductor substrate of the cell region. 
     The step of forming the cell body pattern and the peripheral body pattern includes forming a single crystal semiconductor structure on the interlayer insulator pattern and the exposed portion of the semiconductor substrate of the peripheral circuit region; and planarizing the single crystal semiconductor structure. 
     The single crystal semiconductor structure is formed by using a selective epitaxial growth technique which employs the semiconductor substrate exposed by the contact hole and the exposed semiconductor substrate of the peripheral circuit region as a seed layer. The step of forming the cell thin film transistor and the peripheral transistor includes a cell gate electrode and a peripheral gate electrode which respectively cross the cell body pattern and the peripheral body pattern; ion-doping the cell body pattern and the peripheral body pattern using the gate electrodes as an ion-doping mask to form cell source and drain regions in the cell body pattern and peripheral source and drain regions in the peripheral body pattern. The method of the first aspect further includes forming selectively a metal silicide layer on surfaces of the peripheral gate electrode and/or the peripheral source and drain regions. 
     A second aspect of a method of manufacturing a semiconductor device includes preparing a semiconductor substrate having a cell region and a peripheral circuit region; forming a bulk transistor on the semiconductor substrate of the cell region; forming a first interlayer insulator pattern which exposes the semiconductor substrate of the peripheral circuit region on the semiconductor substrate having the bulk transistor, the first interlayer insulator pattern having a first contact hole which exposes a predetermined region of an ion-doped region of the bulk transistor; forming a cell lower body pattern for covering the first contact hole on the first interlayer insulator pattern; forming a cell lower thin film transistor in the cell lower body pattern; forming a second interlayer insulator pattern for covering the cell lower thin film transistor on the first interlayer insulator pattern, the second interlayer insulator pattern having a second contact hole which exposes a predetermined region of an ion-doped region of the cell lower thin film transistor; forming a cell upper body pattern for covering the second contact hole on the second interlayer insulator pattern and a peripheral body pattern in the peripheral circuit region; and forming a cell upper thin film transistor in the cell upper body pattern and a peripheral transistor in the peripheral body pattern. 
     The method of the second aspect further includes forming the cell lower body pattern and a peripheral body pattern for covering the semiconductor substrate of the peripheral circuit region. The step of forming the cell lower body pattern and the peripheral lower body pattern includes forming a first single crystal semiconductor structure which fills the first contact hole and covers the first interlayer insulator pattern and the semiconductor substrate of the peripheral circuit region; and planarizing the first single crystal semiconductor structure. 
     The step of forming the cell upper body pattern and the peripheral body pattern includes forming a second single crystal semiconductor structure which fills the second contact hole and covers the second interlayer insulator pattern and the semiconductor substrate of the peripheral circuit region; planarizing the second single crystal semiconductor structure; and patterning the second single crystal semiconductor structure to form a cell upper body pattern in the cell region and a peripheral upper body pattern in the peripheral circuit region, thereby forming a peripheral body pattern having the peripheral lower body pattern and the peripheral upper body pattern. The single crystal semiconductor structures are formed by using an epitaxial technique. 
     The step of forming the cell lower body pattern includes forming a first single crystal semiconductor structure which fills the first contact hole and covers the first interlayer insulator pattern and the semiconductor substrate of the peripheral circuit region; and patterning the first single crystal semiconductor structure to expose the semiconductor substrate of the peripheral circuit region. 
     The step of forming the cell upper body pattern and the peripheral body pattern includes forming a second single crystal semiconductor structure which fills the second contact hole and covers the second interlayer insulator pattern and the semiconductor substrate of the peripheral circuit region, the second single crystal semiconductor structure having a plane upper surface; and patterning the second single crystal semiconductor structure to form the cell upper body pattern in the cell region and the peripheral body pattern in the peripheral circuit region. The single crystal semiconductor structures are formed by using an epitaxial technique. 
     The bulk transistor is an n-channel driving transistor, the cell lower thin film transistor is a p-channel load transistor, and the cell upper thin film transistor is an n-channel transmission transistor. The step of forming the cell upper thin film transistor and the peripheral transistor includes forming a cell upper gate electrode and a peripheral gate electrode which respectively cross the cell upper body pattern and the peripheral body pattern; and ion-doping the cell upper body pattern and the peripheral body pattern using the gate electrode as an ion doping mask to form cell source and drain regions in the cell upper body pattern and peripheral source and drain regions in the peripheral body pattern. The method of the second aspect further includes forming selectively a metal silicide layer on surfaces of the peripheral gate electrode and/or the peripheral source and drain regions. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a block diagram illustrating a typical semiconductor memory device; 
         FIG. 2  is a block diagram illustrating a row decoder or a column decoder of the semiconductor memory device of  FIG. 1 ; 
         FIGS. 3A to 3D  are circuit diagrams illustrating a static memory cell of a memory cell array, and an inverter, a NAND gate, and a NOR gate which constitute a peripheral circuit in the conventional semiconductor memory device; 
         FIG. 4A  is a view illustrating arrangement of transistors which constitute the static memory cell and transistors which constitute the inverter, the NAND gate and the NOR gate in the conventional semiconductor memory device; 
         FIGS. 5A to 5D  are views respectively illustrating different arrangement of transistors of the static memory cell and transistors which constitute the inverter, the NAND gate and the NOR gate of the peripheral circuit in the conventional semiconductor memory device; 
         FIGS. 6A to 6D  are views respectively illustrating another different arrangement of transistors of the static memory cell and transistors which constitute the inverter, the NAND gate and the NOR gate of the peripheral circuit in the conventional semiconductor memory device; 
         FIGS. 7A to 7D  are views respectively illustrating arrangement of transistors of a static memory cell and transistors which constitute an inverter, a NAND gate and a NOR gate of a peripheral circuit of a semiconductor memory device according to a first embodiment of the present invention; 
         FIGS. 8A to 8D  are views respectively illustrating arrangement of transistors of a static memory cell and transistors which constitute an inverter, a NAND gate and a NOR gate of a peripheral circuit of a semiconductor memory device according to a second embodiment of the present invention; 
         FIGS. 9A to 9D  are views respectively illustrating arrangement of transistors of a static memory cell and transistors which constitute an inverter, a NAND gate and a NOR gate of a peripheral circuit of a semiconductor memory device according to a third embodiment of the present invention; 
         FIGS. 10A to 16D  are plane views illustrating respective arrangement of the memory cell, the inverter, the NAND gate, and the NOR gate according to an embodiment of the present invention; 
         FIGS. 17A and 17B  are cross-sectional views respectively taken along line I-I′ and II-II′ of  FIG. 16A , illustrating the structure of the memory cell according to the embodiment of the present invention; 
         FIGS. 18 to 20  are cross-sectional views taken along line X-X′ of  FIGS. 10B to 16B ,  FIGS. 10C to 16C , and  FIGS. 10D to 16D , illustrating the structure of the memory cell according to the embodiment of the present invention; 
         FIGS. 21A and 21B  are views illustrating stacking structure of the memory cell array and the peripheral circuit according to a first embodiment of the present invention; 
         FIGS. 22A and 22B  are views illustrating stacking structure of the memory cell array and the peripheral circuit according to a second embodiment of the present invention; 
         FIGS. 23A and 23B  are views illustrating stacking structure of the memory cell array and the peripheral circuit according to a third embodiment of the present invention; 
         FIGS. 24A and 24B  are views respectively illustrating arrangement of transistors of a static memory cell and transistors which constitute an inverter of a peripheral circuit of a semiconductor memory device according to a fourth embodiment of the present invention; 
         FIG. 25  is a plan view illustrating the inverter of the peripheral circuit of  FIG. 24B ; and 
         FIGS. 26A and 26B  to  FIGS. 34A and 34B  are cross-sectional views illustrating a method of manufacturing the memory cell and the inverter. 
         FIG. 35A  is a view taken along lines I-I′ of  FIG. 16A  and III-III′ of  FIG. 25 , illustrating the structures of the memory cell and inverter of a semiconductor memory device according to another embodiment of the present invention, and  FIG. 35B  is a view taken along lines I-I′ of  FIG. 16A  and III-III′ of  FIG. 25 , illustrating the structures of the memory cell and inverter of a semiconductor memory according to another embodiment of the present invention; 
         FIG. 36  is a schematic view illustrating arrangement of the memory cell with reference to the layout of the inverter of  FIG. 16B  according to an embodiment of the present invention; and 
         FIGS. 37 to 44  are views illustrating a method of manufacturing the semiconductor memory device having another structure. 
     
    
    
     DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION 
     The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the thickness of layers and regions are exaggerated for clarity. Like numbers refer to like elements throughout the specification. 
       FIG. 1  is a block diagram illustrating a typical semiconductor memory device. The semiconductor memory device of  FIG. 1  includes a memory cell array  10 , a row decoder  12 , a data I/O gate  14 , a column decoder  16 , a data I/O circuit  18 , and a controller  20 . In  FIG. 1 , wl 1  to wlm denote word line selecting signals, y 1  to yn denote column selecting signals, WL 1  to WLm denote word lines, and BL 1 ,BL 1 B to BLn,BLnB denote bit line pairs. Functions of components of the semiconductor memory device of  FIG. 1  will be described below. 
     The memory cell array  10  includes a plurality of static memory cells MC 11  to MCmn respectively connected between each of the word lines WL 1  to WLm and each of the bit line pairs BL 1 ,BL 1 B to BLn,BLnB, receives data din and writes it onto a selected memory cell during write operations, and reads data stored in a selected memory cell and outputs the data dout during read operations. The row decoder  12  decodes a row address RA to generate the word line selecting signals wl 1  to wlm in response to an active command ACT. The data I/O gate  14  transmits data Din as data din during the write operations and transmits data dout as data Dout during the read operations, in response to the column selecting signals y 1  to yn. The column decoder  16  decodes a column address CA to generate the column selecting signals y 1  to yn, in response to read and write commands RD, WR. The data I/O circuit  18  receives data DIN and outputs data Din in response to the write command WR, and receives data Dout and outputs data DOUT in response to the read command RD. The controller  20  receives a command COM to generate the active command ACT, the read command RD, and the write command WR. 
       FIG. 2  is a block diagram illustrating the row decoder or the column decoder of the semiconductor memory device of  FIG. 1 . The decoder of  FIG. 2  includes two pre-decoders  30  and  32  and a main decoder  34 . The two pre-decoders  30  and  32  and the main decoder  34  include a two-input NAND gate NA and an inverter NV, respectively. The decoder of  FIG. 2  is configured to receive 4-bit address A 1  to A 4  to generate 16 decoding signals DRA 1  to DRA 16 . Functions of components of the decoder of  FIG. 2  will be explained below. 
     Each of the pre-decoders  30  and  32  decodes two 2-bit addresses A 1 ,A 2  and A 3 ,A 4  to output pre-decoded signals DRA 1 B 2 B to DRA 12  and DRA 3 B 4 B to DRA 34 . The main decoder  34  decodes the pre-decoded signals DRA 1 B 2 B to DRA 12  and DRA 3 B 4 B to DRA 34  to generate decoding signals DRA 1  to DRA 16 . The static memory cell of the memory cell array of the semiconductor memory device includes six (6) transistors, and the column or row decoder includes logic gates such as an inverter and a NAND gate. The inverter includes two transistors, and the NAND gate includes at least 4 transistors. The column or row decoder of  FIG. 2  includes the two-input NAND gate and thus is comprised of four transistors, but in case where the decoder of  FIG. 2  includes a 3- or 4-input NAND gate, it is comprised of 6 or 8 transistors. The data I/O circuit  18  and the controller  20  further includes a NOR gate in addition to the inverter and the NAND gate. 
       FIG. 3A  is a circuit diagram illustrating the static memory cell of the memory cell array of  FIG. 1 .  FIGS. 3B to 3D  are circuit diagrams respectively illustrating an inverter, a NAND gate, and a NOR gate which constitute the peripheral circuit. As shown in  FIG. 3A , the static memory cell includes PMOS transistors PU 1  and PU 2  and NMOS transistors PD 1 , PD 2 , T 1 , and T 2 . The PMOS transistors PU 1  and PU 2  are pull-up transistors, and the NMOS transistors are pull-down transistors, and the NMOS transistors T 1  and T 2  are transmission transistors. Operation of the static memory cell of  FIG. 3A  will be described below. 
     If the word line WL is selected so that the NMOS transistors T 1  and T 2  are turned on, data is transmitted between the bit line BL and the storage node a, and data is transmitted between an inverted bit line BLB and a storage node b. If data of the storage node b has a high level, the NMOS transistor PD 1  makes the storage node a have a low level, and if data of the storage node b has a low level, the PMOS transistor PU 1  makes the storage node a have a high level. Likewise, if data of the storage node a has a high level, the NMOS transistor PD 2  makes the storage node b have a low level, and if data of the storage node a has a low level, the PMOS transistor PU 2  makes the storage node b have a high level. That is, the two PMOS transistors PU 1  and PU 2  and the two NMOS transistors PD 1  and PD 2  serve as a latch and latches data of the storage nodes a and b. 
     As shown in  FIG. 3B , the inverter includes a PMOS transistor P 1  and an NMOS transistor N 1 . In  FIG. 3B , the PMOS transistor P 1  is a pull-up transistor, and the NMOS transistor N 1  is a pull-down transistor. Operation of the inverter of  FIG. 3B  is as follows. If an input signal IN having a high level is inputted, the NMOS transistor N 1  is turned on to make an output signal OUT have a low level, i.e., a ground voltage Vss level. On the other hand, if an input signal IN having a low level is inputted, the PMOS transistor P 1  is turned on to make the output signal OUT have a high level, i.e., a power voltage Vcc level. That is, the inverter of  FIG. 3B  is comprised of one pull-up transistor and one pull-down transistor and inverts an input signal IN to generate the output signal OUT. 
     As shown in  FIG. 3C , the NAND gate includes PMOS transistors P 2  and P 3  and NMOS transistors N 2  and N 3 . In  FIG. 3C , the PMOS transistors P 2  and P 3  are pull-up transistors, and the NMOS transistors N 2  and N 3  are pull-down transistors. Operation of the NAND gate of  FIG. 3C  is as follows. If at least one of input signals IN 1  and IN 2  having a low level is applied, the PMOS transistor P 2  and/or the PMOS transistor P 3  are/is turned on to make an output signal OUT have a high level, i.e., a power voltage Vcc level. On the other hand, if the input signals IN 1  and IN 2  having a high level are applied, the NMOS transistors N 2  and N 3  are turned on to make the output signal OUT have a low level. 
     As shown in  FIG. 3D , the NOR gate includes PMOS transistors P 4  and P 5  and NMOS transistors N 4  and N 5 . In  FIG. 3D , the PMOS transistors P 3  and P 4  are pull-up transistors, and the NMOS transistors are pull-down transistors. Operation of the NOR gate of  FIG. 3D  is as follows. If at least one of input signals IN 1  and IN 2  having a high level is applied, the NMOS transistor N 4  and/or the NMOS transistor N 5  are/or turned on to make an output signal OUT have a low level, i.e., a ground voltage Vss level. On the other hand, if input signals IN 1  and IN 2  having a low level are applied, the PMOS transistors P 4  and P 5  are turned on to make the output signal OUT have a high level. 
       FIG. 4A  is a view illustrating arrangement of the transistors which constitute the static memory cell of  FIG. 3A , and  FIGS. 4B to 4D  are views respectively illustrating arrangement of the transistors which constitute the inverter, the NAND gate and the NOR gate shown in  FIGS. 3B to 3D . In  FIGS. 4A to 4D , it appears that a bit line pair BL and BLB, a word line WL, a power voltage line VCCL, and a ground voltage line VSSL are arranged on difference layers, but they are not always arranged on difference layers. 
     As shown in  FIG. 4A , the transistors PD 1 , PD 2 , PU 1 , PU 2 , T 1 , and T 2  of  FIG. 3A  are arranged on the same layer  1 F. A source of the NMOS transistor T 1  is connected to a drain of the NMOS transistor PD 1 , a source of the NMOS transistor PD 1  is connected to a source of the NMOS transistor PD 2 , and a drain of the NMOS transistor PD 2  is connected to a source of the NMOS transistor T 2 . A drain of the NMOS transistor T 1  is connected to a bit line BL, a drain of the NMOS transistor T 2  is connected to an inverted bit line BLB, gates of the NMOS transistors T 1  and T 2  are connected to the word line, and sources of the NMOS transistors PD 1  and PD 2  are connected to the ground voltage line VSSL. A drain of the PMOS transistor PU 1  is connected to a source of the NMOS transistor PD 1 , a source of the PMOS transistor PU 1  is connected to the power voltage line VCCL, and a gate of the PMOS transistor PU 1  is connected to a gate of the NMOS transistor PD 1  and a drain of the NMOS transistor PD 2 . A drain of the PMOS transistor PU 2  is connected to a drain of the NMOS transistor PD 2 , a source of the PMOS transistor PU 2  is connected to the power voltage line VCCL, and a gate of the PMOS transistor PU 2  is connected to a gate of the NMOS transistor PD 2 . 
     As shown in  FIG. 4B , the transistors P 1  and N 1  of  FIG. 3B  are arranged on the same floor  1 F. The PMOS transistor P 1  has a source connected to the power voltage line VCCL, a drain connected to an output signal line OUTL, and a gate connected to an input signal line INL. The NMOS transistor N 1  has a source connected to the ground voltage line VSSL, a drain connected to the output signal line OUTL, and a gate connected to the input signal line INL. 
     As shown in  FIG. 4C , the transistors P 2 , P 3 , N 2  and N 3  of  FIG. 3C  are arranged on the same layer  1 F. A source of the PMOS transistor P 3  is connected to a source of the PMOS transistor P 2 , and a drain of the PMOS transistor P 3  is connected to the output signal line OUTL. Gates of the PMOS transistor P 3  and the NMOS transistor N 3  are connected to an input signal line IN 1 L, gates of the PMOS transistor P 2  and the NMOS transistor N 2  are connected to an input signal line IN 2 L, drains of the PMOS transistor P 2  and the NMOS transistor N 2  are connected, sources of the NMOS transistors N 2  and N 3  are connected, and a drain of the NMOS transistor N 3  is connected to the ground voltage line VSSL. 
     As shown in  FIG. 4D , the transistors P 4 , P 5 , N 4 , and N 5  of  FIG. 3D  are arranged on the same layer  1 F. A drain of the PMOS transistor P 4  is connected to a source of the PMOS transistor P 5 , a drain of the PMOS transistor P 5  is connected to a drain of the NMOS transistor N 5 , a source and a gate of the PMOS transistor P 4  are respectively connected to the power voltage line VCCL and the input signal line IN 2 L, a gate of the PMOS transistor P 5  is connected to the input signal line IN 1 L, drains of the PMOS transistor P 5  and the NMOS transistor N 5  are connected to the output signal line OUTL, and a drain, a gate and a source of the NMOS transistor N 4  are respectively connected to the output signal line OUTL, the input signal line IN 2 L and the ground voltage line VSSL. 
     As shown in  FIGS. 4A to 4D , all of the transistors which constitute the memory cell and the peripheral circuit of the conventional semiconductor memory device are arranged on the same layer  1 F, and thus in case where capacitor of the memory cell is increased, layout area size is also increased. 
     In order to reduce the layout area size of the memory cell of the semiconductor memory device, a method of arranging transistors, which constitute the memory cell on two or three layers has been introduced.  FIGS. 5A to 5D  are views respectively illustrating different arrangements of the transistors of the static memory cell and the transistors which constitute the inverter, the NAND gate and the NOR gate of the peripheral circuit in the conventional semiconductor memory device, where the transistors which constitute the memory cell are arranged on two layers. 
     As shown in  FIG. 5A , the NMOS transistors PD 1 , PD 2 , T 1 , and T 2  are arranged on a first layer  1 F, and the PMOS transistors PU 1  and PU 2  are arranged on a second layer  2 F. Connections between the transistors PD 1 , PD 2 , PU 1 , PU 2 , T 1 , and T 2  are identical to those of  FIG. 4A . Like arrangement of  FIGS. 4B to 4D , the transistors P 1  to P 5  and N 1  to N 5  of  FIGS. 5B to 5D  which constitute the inverter, the NAND gate and the NOR gate are arranged on the first layer  1 F. Therefore, as shown in  FIG. 5A , if the transistors which constitute the memory cell are arranged on the two layers and the transistors which constitute the peripheral circuit are on one layer, the layout area size of the memory cell array is reduced, but the layout area size of the peripheral circuit is not reduced. 
       FIGS. 6A to 6D  are views respectively illustrating another different arrangement of the transistors of the static memory cell and the transistors which constitute the inverter, the NAND gate and the NOR gate of the peripheral circuit in the conventional semiconductor memory device, where the transistors which constitute the memory cell are arranged on three layers. 
     As shown in  FIG. 6A , the NMOS transistors PD 1  and PD 2  are arranged on a first layer  1 F, the PMOS transistors PU 1  and PU 2  are arranged on a second layer  2 F, and the access transistors T 1  and T 2  are arranged on a third layer  3 F. Connections between the transistors PD 1 , PD 2 , PU 1 , PU 2 , T 1 , and T 2  are identical to those of  FIG. 4A . 
     Like the arrangement of  FIGS. 4B to 4D , the transistors P 1  to P 5  and N 1  to N 5  of  FIGS. 6B to 6D  which constitute the inverter, the NAND gate and the NOR gate are arranged on the first layer  1 F. Therefore, as shown in  FIG. 6A , if the transistors which constitute the memory cell are arranged on the three layers and the transistors which constitute the peripheral circuit are on one layer, the layout area size of the memory cell array is reduced, but the layout area size of the peripheral circuit is not reduced. In the conventional arrangement of the semiconductor memory device, the layout area size of the memory cell array is reduced by arranging the transistors, which constitute the static memory cell on two or three layers, but since the transistors, which constitute the peripheral circuit, are arranged on one layer, the layout area size of the peripheral circuit is not reduced. 
       FIGS. 7A to 7D  are views respectively illustrating arrangement of transistors of a static memory cell and transistors which constitute an inverter, a NAND gate and a NOR gate of a peripheral circuit of a semiconductor memory device according to a first embodiment of the present invention. In particular,  FIGS. 7A to 7D  show arrangement of transistors which constitute the peripheral circuit in case where transistors which constitute the memory cell are arranged on two layers. 
     Like arrangement of  FIG. 5A , transistors PD 1 , PD 2 , PU 1 , PU 2 , T 1 , and T 2  of  FIG. 7A  that constitute the static memory cell are arranged on two layers. As shown in  FIG. 7B , an NMOS transistors N 1  is arranged on the first layer  1 F, and a PMOS transistor P 1  is arranged on the second layer  2 F. Connection between the transistors N 1  and P 1 , which constitute the inverter, are identical to those of  FIG. 4B . As shown in  FIG. 7C , NMOS transistors N 2  and N 3  are arranged on the first layer  1 F, and PMOS transistors P 2  and P 3  are arranged on the second layer  2 F. Connections between the transistors N 2 , N 3 , P 2 , and P 3 , which constitute the NAND gate, are identical to those of  FIG. 4C . As shown in  FIG. 7D , NMOS transistors N 4  and N 4  are arranged on the first layer  1 F, and PMOS transistors P 4  and P 5  are arranged on the second layer  2 F. Connections between the transistors N 4 , N 5 , P 4 , and P 5  which constitute the NOR gate are identical to those of  FIG. 4D . As shown in  FIGS. 7A to 7D , the semiconductor memory device of the present invention can reduce the layout area size by arranging the transistors which constitute the memory cell on two layers and arranging the transistors which constitute the peripheral circuit on two layers. The transistors of  FIGS. 7B to 7D  may be arranged on different layers from those shown in  FIGS. 7A to 7D . For example, the transistors do not need to be always arranged on the first and second layers and may be arranged on the first and third layers or the second and third layers. 
     However, the PMOS transistor and the NMOS transistor may be arranged on the first layer, but it is preferred to arrange the same type transistor on the second layer  2 F as the transistor arranged on the second layer of the memory cell for the convenience of manufacturing process. For example, it is preferable to arrange the NMOS transistor which is to be arranged on the second layer  2 F of the peripheral circuit if the transistors to be arranged on the second layer  2 F of the memory cell are NMOS transistors, and it is preferable to arrange the PMOS transistor which is to be arranged on the second layer  2 F of the peripheral circuit if the transistors to be arranged on the second layer  2 F of the memory cell are PMOS transistors. 
       FIGS. 8A to 8D  are views respectively illustrating arrangement of transistors of a static memory cell and transistors which constitute an inverter, a NAND gate and a NOR gate of a peripheral circuit of a semiconductor memory device according to a second embodiment of the present invention. In particular,  FIGS. 8A to 8D  show arrangement of transistors which constitute the peripheral circuit in case where transistors which constitute the memory cell are arranged on three layers. Like arrangement of  FIG. 6A , the transistors of  FIG. 8A , which constitute the static memory cell, are arranged such that the pull-down transistors PD 1  and PD 2  are arranged on the first layer  1 F, the pull-up transistors PU 1  and PU 2  are arranged on the second layer  2 F, and the transmission transistors T 1  and T 2  are arranged on the third layer. As shown in  FIG. 8B , NMOS transistors N 1 - 1  and N 1 - 2 , which have 1/2 channel width of channel width of the NMOS transistor N 1  of  FIG. 3B  are arranged. The NMOS transistor N 1 - 2  is arranged on the first layer  1 F, the PMOS transistor P 1  is arranged on the second layer  2 F, and the NMOS transistor N 1 - 1  is arranged on the third layer  3 F. Gates, drains and sources of the NMOS transistors N 1 - 1  and N 1 - 2  are commonly connected, and connections between the NMOS transistors N 1 - 1  and N 1 - 2  and the PMOS transistor P 1  are identical to those of  FIG. 4B . 
     As shown in  FIG. 8C , a PMOS transistor P 2  and an NMOS transistor N 2  are arranged on the first layer  1 F, the PMOS transistor P 3  is arranged on the second layer  2 F, and an NMOS transistor N 3  is arranged on the third layer  3 F. Connections between the PMOS transistors P 2  and P 3  and the NMOS transistors N 2  and N 3  are identical to those of  FIG. 4C . 
     As shown in  FIG. 8D , NMOS transistors N 4 - 1  and N 4 - 2  which have 1/2 channel width of channel width of the NMOS transistor N 4  and NMOS transistors N 5 - 1  and N 5 - 2  which have 1/2 channel width of channel width of the NMOS transistor N 5  are arranged. The NMOS transistors N 4 - 1  and N 5 - 1  are arranged on the first layer  1 F, PMOS transistors P 4  and P 5  are arranged on the second layer  2 F, and the NMOS transistors N 5 - 1  and N 5 - 2  are arranged on the third layer  3 F. Gates, sources and drains of the NMOS transistors N 4 - 1  and N 4 - 2  are commonly connected, and Gates, sources and drains of the NMOS transistors N 5 - 1  and N 5 - 2  are commonly connected. Connections between the PMOS transistors P 4  and P 5  and the NMOS transistors N 4  and N 5  are identical to those of  FIG. 4D . 
     As shown in  FIGS. 8A and 8D , the semiconductor memory device of the present invention can reduce the layout area size by arranging the transistors which constitute the memory cell on three layers and arranging the transistors which constitute the peripheral circuit on three layers. 
       FIGS. 9A to 9D  are views respectively illustrating the arrangement of transistors of a static memory cell and transistors which constitute an inverter, a NAND gate and a NOR gate of a peripheral circuit of a semiconductor memory device according to a third embodiment of the present invention. In particular,  FIGS. 9A to 9D  show arrangement of transistors which constitute the peripheral circuit in case where transistors which constitute the memory cell are arranged on three layers. Like the arrangement of  FIG. 8A , the transistors of  FIG. 9A , which constitute the static memory cell, are arranged on three layers. 
     As shown in  FIG. 9B , PMOS transistors P 1 - 1  and P 1 - 2  which have 1/2 channel width of channel width of the PMOS transistor P 1  which constitutes the inverter are arranged. The PMOS transistor P 1 - 1  is arranged on the first layer  1 F, the PMOS transistor P 1 - 2  is arranged on the second layer  2 F, and the NMOS transistor N 1  is arranged on the third layer  3 F. Gates, drains and sources of the PMOS transistors P 1 - 1  and P 1 - 2  are commonly connected, and connections between the PMOS transistors P 1 - 1  and P 1 - 2  and the NMOS transistor N 1  are identical to those of  FIG. 4B . 
     As shown in  FIG. 9C , the PMOS transistors P 2 - 1  and P 2 - 2  and the PMOS transistors P 3 - 1  and P 3 - 2  which respectively have 1/2 channel width of respective channel width of the PMOS transistors P 2  and P 3  which constitute the NAND gate are arranged. The PMOS transistors P 2 - 2  and P 3 - 2  are arranged on the first layer  1 F, the PMOS transistors P 2 - 1  and P 3 - 1  are arranged on the second layer  2 F, and the NMOS transistors N 2  and N 3  are arranged on the third layer  3 F. Gates, drains and sources of the PMOS transistors P 2 - 1  and P 2 - 2  are commonly connected, and gates, drains and sources of the PMOS transistors P 3 - 1  and P 3 - 2  are commonly connected, and connections between the PMOS transistors P 2 - 1 , P 2 - 2 , P 3 - 1 , and P 3 - 2  and the NMOS transistors N 2  and N 3  are identical to those of  FIG. 4C . 
     As shown in  FIG. 9D , the PMOS transistors P 4 - 1  and P 4 - 2  and the PMOS transistors P 5 - 1  and P 5 - 2  which respectively have 1/2 channel width of respective channel width of the PMOS transistor P 4  and P 5  which constitute the NOR gate are arranged. The PMOS transistors P 4 - 1  and P 5 - 1  are arranged on the first layer  1 F, the PMOS transistors P 4 - 2  and P 5 - 2  are arranged on the second layer  2 F, and the NMOS transistors N 4  and N 5  are arranged on the third layer  3 F. Gates, drains and sources of the PMOS transistors P 4 - 1  and P 4 - 2  are commonly connected, and gates, drains and sources of the PMOS transistors P 5 - 1  and P 5 - 2  are commonly connected, and connections between the PMOS transistors P 4 - 1 , P 4 - 2 , P 5 - 1 , and P 5 - 2  and the NMOS transistors N 4  and N 5  are identical to those of  FIG. 4D . 
     The PMOS transistor and the NMOS transistor may be arranged on the first layer, but it is preferred to arrange the same type transistor on the second layer  2 F as the transistor arranged on the second layer of the memory cell for the convenience of manufacturing process. For example, it is preferable to arrange the PMOS transistor which is to be arranged on the second layer  2 F of the peripheral circuit if the transistors to be arranged on the second layer  2 F of the memory cell are PMOS transistors, and it is preferable to arrange the NMOS transistor which is to be arranged on the third layer  3 F of the peripheral circuit if the transistors to be arranged on the third layer  3 F of the memory cell are NMOS transistors. 
     Arrangement and structure of the inverter, the NAND gate, and the NOR gate which constitute the static memory cell and the peripheral circuit according to an embodiment of the present invention will be explained below. 
       FIGS. 10A to 16D  are plan views illustrating respective arrangement of the memory cell, the inverter, the NAND gate, and the NOR gate according to an embodiment of the present invention.  FIGS. 17A and 17B  are cross-sectional views respectively taken along line □-□′ and □-□′ of  FIG. 16A , illustrating structure of the memory cell according to the embodiment of the present invention.  FIGS. 18 to 20  are cross-sectional views taken along line □-□′ of  FIGS. 10B to 16B ,  FIGS. 10C to 16C , and  FIGS. 10D to 16D , illustrating the structure of the memory cell according to the embodiment of the present invention. 
     Referring to  FIGS. 10A ,  17 A and  17 B, a first active area  1   b ′ and a second active area  1   a ′ are arranged on a semiconductor substrate SUB in a parallel direction to a y axis opposing to each other, and one end of the second active area  1   a ′ extends to be parallel to an x axis. A third active area  1   b ″ and a fourth active area  1   a ″ are arranged on a semiconductor substrate SUB in a parallel direction to a y axis opposing to each other, and one end of the fourth active area  1   a ″ extends to be parallel to an x axis. A gate pattern  1   c ′ is arranged in the x axis direction to cross over the first and second active areas  1   b ′ and  1   a ′ which are arranged to be parallel to the y axis, and a gate pattern  1   c ″ is arranged in the x axis direction to cross over the third and fourth active areas  1   b ″ and  1   a ″ which are arranged to be parallel to the y axis. A drain region PD 1 D is provided on a surface of the first active area  1   b ′ which is located at one side of the gate pattern  1   c ″, and a source region PD 1 S is provided on a surface of the second active area  1   a ′ which is located on the other side of the gate pattern  1   c ′. Likewise, a drain region PD 2 D is provided on a surface of the third active area  1   b ″ which is located at one side of the gate pattern  1   c ″, and a source region PD 2 S is provided on a surface of the fourth active area  1   a ″ which is located on the other side of the gate pattern  1   c ″. The gate patterns  1   c ′ and  1   c ″ may include a gate electrode PD 1 G of the NMOS transistor PD 1  and a capping insulating layer  2   a ′ which are stacked in order and a gate electrode PD 2 G of the NMOS transistor PD 2  and a capping insulating layer  2   a ″ which are stacked in order, respectively, and gate insulating layers  2   b ′ and  2   b ″ are respectively interposed between the respective gate patterns  1   c ′ and  1   c ″ and the semiconductor substrate SUB. A spacer  2   c  may be arranged on side walls of the gate patterns  1   c ′ and  1   c ″, and an interlayer insulator  2   e  is arranged over the whole surface of the semiconductor substrate SUB having the NMOS transistors PD 1  and PD 2 . An etching stopper layer  2   d  may be additionally interposed between the interlayer insulator  2   e  and the semiconductor substrate SUB having the NMOS transistors PD 1  and PD 2 . Accordingly, the NMOS transistors PD 1  and PD 2 , which are bulk-transistors, are formed on the semiconductor substrate SUB. 
     Referring to  FIGS. 10B and 18 , first and second active areas  20   a ′ and  20   b ′ are arranged on a semiconductor substrate SUB opposing to each other, and a gate pattern  20   c ′ is arranged in the y axis direction to cross over the first and second active areas  20   a ′ and  20   b ′, and one end of the gate pattern  20   c ′ extends in a direction of the x axis where the first active area  20   a ′ is located. A drain region N 1 D of the NMOS transistor N 1  is provided on a surface of the first active area  20   a ′, and a source region N 1 S of the NMOS transistor N 1  is provided on a surface of the second active area  20   b ′. The gate pattern  20   c ′ of the NMOS transistor N 1  may include a gate electrode N 1 G of the NMOS transistor N 1  and a capping insulating layer  21   a  which are stacked in order, and a gate insulating layer  21   b  is interposed between the gate pattern  20   c ′ and the semiconductor substrate SUB. A spacer  21   c  may be arranged on side walls of the gate pattern  20   c ′, and an interlayer insulator  21   e  is arranged over the whole surface of the semiconductor substrate SUB having the NMOS transistor N 1 . An etching stopper layer  21   d  may be additionally interposed between the interlayer insulator  21   e  and the semiconductor substrate SUB having the NMOS transistor N 1 . Accordingly, the NMOS transistor N 1  which is a bulk-transistor which constitutes the inverter is formed on the semiconductor substrate SUB. 
     Referring to  FIGS. 10C and 19 , first to third active areas  40   a ′,  40   b ′ and  40   a ″ are arranged on a semiconductor substrate SUB. A gate pattern  40   c ′ is arranged in the y axis direction over the first and second active areas  40   a ′ and  40   b ′, and one end of the gate pattern  40   c ′ is arranged in a direction of the x axis where the first active area  40   a ′ is located. A gate pattern  40   c ″ is arranged in the y axis direction over the second and third active areas  40   b ′ and  40   a ″, and one end of the gate pattern  40   c ″ is arranged in a direction of the x axis where the third active area  40   a ″ is located. One end of the gate pattern  40   c ′ and one end of the gate pattern  40   c ″ are arranged to face each other in diagonal line direction. The gate pattern  40   c ′ of the NMOS transistor N 2  may includes a gate electrode N 2 G of the NMOS transistor N 2  and a capping insulating layer  41   a ′, and a gate insulating layer  41   b ′ is interposed between the gate pattern  40   c ′ and the semiconductor substrate SUB. A drain region N 2 D of the NMOS transistor N 2  is provided on a surface of the first active area  40   a ′ of the semiconductor substrate SUB, and a source region N 2 S of the NMOS transistor N 2  and a drain region N 3 D of the NMOS transistor N 3  are provided on a surface of the second active area  40   b ′. A spacer  41   c  may be arranged on side walls of the gate pattern  40   c ′, and an interlayer insulator  41   e  is arranged over the whole surface of the semiconductor substrate SUB having the NMOS transistor N 2 . An etching stopper layer  41   d  may be additionally interposed between the interlayer insulator  41   e  and the semiconductor substrate SUB having the NMOS transistor N 2 . Likewise, the gate pattern  40   c ″ of the NMOS transistor N 3  is provided in the same form as the gate pattern  40   c ′ of the NMOS transistor N 2 . Accordingly, the NMOS transistors N 2  and N 3  which are bulk-transistors, which constitute the NAND gate, is formed on the semiconductor substrate SUB. 
     Referring to  FIGS. 10D and 20 , an N well N WELL is formed on a semiconductor substrate SUB, and first to third active areas  60   a ′,  60   b ′ and  60   a ″ are provided in the N well N WELL. Gate patterns  60   c ′ and  60   c ″ are provided in the same form as those of  FIG. 10C . As shown in  FIG. 20 , the PMOS transistors P 4  and P 5 , which are bulk-transistors, are formed on the semiconductor substrate SUB. The PMOS transistors P 4  and P 5  have the same form as the NMOS transistors N 2  and N 3 ′ of  FIG. 19 . 
     Referring to  FIGS. 11A ,  17 A and  17 B, the drain region PD 1 D of the NMOS transistor PD 1  is electrically connected to a lower node semiconductor plug  3   a ′ which penetrates the interlayer insulator  2   e  and the etching stopper layer  2   d , and the drain region PD 2 D of the NMOS transistor PD 2  is electrically connected to a lower node semiconductor plug  3   a ″ which penetrates the interlayer insulator  2   e  and the etching stopper layer  2   d . Lower body patterns  3   b ′ and  3   b ″ are arranged on the interlayer insulator  2   e  to respectively cover the lower node semiconductor plugs  3   a ′ and  3   a″.    
     Referring to  FIGS. 11B and 18 , the drain region N 1 D of the NMOS transistor N 1  is electrically connected to a node semiconductor plug  22   b , which penetrates the interlayer insulator  21   e  and the etching stopper layer  21   d , and a lower body pattern  22   a  is arranged on the interlayer insulator  21   e  to cover the node semiconductor plug  22   b.    
     Referring to  FIGS. 11C and 19 , the drain region N 2 D of the NMOS transistor N 2  is electrically connected to a node semiconductor plug  42   b , which penetrates the interlayer insulator  41   e  and the etching stopper layer  41   d , and a lower body pattern  42   a  is arranged on the interlayer insulator  41   e  to cover the node semiconductor plug  42   b.    
     In case where the memory cell, the inverter, the NAND gate are arranged as shown in  FIGS. 11A and 11C , the NOR gate of  FIG. 11D  has the same arrangement as that of  FIG. 10D . 
     Referring to  FIGS. 12A ,  17 A and  17 B, a gate pattern  4   b ′ of the PMOS transistor PU 1  is arranged to cross over the lower body pattern  3   b ′, and a gate pattern  4   b ″ of the PMOS transistor PU 2  is arranged to cross over the lower body pattern  3   b ″. An upper node semiconductor plug  4   a ′ is arranged over the lower body pattern  3   b ′ at a location where the lower node semiconductor plug  3   a ′ is arranged, and an upper node semiconductor plug  4   a ″ is arranged over the lower body pattern  3   b ″ at a location where the lower node semiconductor plug  3   a ″ is arranged. Gate electrodes PU 1 G and PU 2 G of the PMOS transistors PU 1  and PU 2  are respectively arranged over the lower body patterns  3   b ′ and  3   b ″. A source region PU 1 S and a drain region PU 1 D of the PMOS transistor PU 1  are provided in the lower body pattern  3   b ′, and a source region PU 2 S and a drain region PU 2 D of the PMOS transistor PU 2  are provided in the lower body pattern  3   b ″. Accordingly, the PMOS transistors PU 1  and PU 2 , which are thin film transistors, are stacked on the NMOS transistors PD 1  and PD 2 . 
     Referring to  FIGS. 12B and 18 , a gate pattern  23   a  is arranged over the lower body pattern  22   a  in the same form as the gate pattern  20   c ′. A gate electrode P 1 G of the PMOS transistor P 1  is arranged over the lower body pattern  22   a , and a drain region P 1 D and a source region P 1 S of the PMOS transistor P 1  are provided in the lower body pattern  22   a . A capping insulating layer  24   a  is arranged over the gate electrode P 1 G, and a gate insulating layer  24   b  is arranged below the gate electrode P 1 G. A spacer  24   c  may be arranged on side walls of the gate pattern  23   a , and an interlayer insulator  24   e  is arranged over the whole surface of the lower body pattern  22   a  having the PMOS transistor P 1 . An etching stopper layer  24   d  may be additionally interposed between the interlayer insulator  24   e  and the lower body pattern  22   a  having the PMOS transistor P 1 . Accordingly, the PMOS transistor P 1  is stacked over the NMOS transistor N 1 . 
     Referring to  FIGS. 12C and 19 , gate patterns  43   a ′ and  43   a ″ are arranged over the lower body pattern  42   a  to overlap over the gate patterns  40   c ′ and  40   c ″. Gate electrodes P 2 G and P 3 G are arranged of the PMOS transistors P 2  and P 3  over the lower body pattern  42   a , and a drain region P 2 D of the PMOS transistor P 2 , a source region P 2 S of the PMOS transistor P 2 , a source region P 3 S of the PMOS transistor P 3 , and a drain region P 3 D of the PMOS transistor P 3  are provided in the lower body pattern  42   a . A capping insulating layer  44   a ′ is arranged over the gate electrode P 2 G, and a gate insulating layer  44   b ′ is arranged below the gate electrode P 2 G. Likewise, a capping insulating layer  44   a ″ is arranged over the gate electrode P 3 G, and a gate insulating layer  44   b ″ is arranged below the gate electrode P 3 G. Spacers  44   c ′ and  44   c ″ are arranged on side walls of the gate patterns  43   a ′ and  43   a ″, and an interlayer insulator  44   e  is arranged over the whole surface of the lower body pattern  42   a  having the PMOS transistors P 2  and P 3 . An etching stopper layer  44   d  may be additionally interposed between the interlayer insulator  44   e  and the lower body pattern  42   a  having the PMOS transistors P 2  and P 3 . Accordingly, the PMOS transistors P 2  and P 3  are stacked over the NMOS transistors N 2  and N 3 , respectively. 
     In case where the memory cell, the inverter, the NAND gate are arranged as shown in  FIGS. 11A and 11C , the NOR gate of  FIG. 12D  has the same arrangement as that of  FIG. 11D . 
     Referring to  FIGS. 13A ,  17 A and  17 B, upper body patterns  6   a ′ and  6   a ″ are arranged on an interlayer insulator  5   e . The upper body patterns  6   a ′ and  6   a ″ are arranged to cover the upper node semiconductor plugs  4   a ′ and  4   a ″, respectively and to overlap over the lower body patterns  3   b ′ and  3   b ″. A word line pattern  6   b  is arranged to cross over the upper body patterns  6   a ′ and  6   a ″ and to overlap the gate patterns  1   c ′ and  1   c ″. Word lines T 1 G and T 2 G are arranged over the upper body patterns  6   a ′ and  6   a ″, and a drain region T 1 D and a source region T 1 S of the transmission transistor T 1  are arranged in the upper body pattern  6   a ′, and a drain region T 2 D and a source region T 2 S of the transmission transistor T 2  are arranged in the upper body pattern  6   a ″. A capping insulating layer  7   a  is arranged over the word lines T 1 G and T 2 G, and a gate insulating layer  7   b  is arranged below the word lines T 1 G and T 2 G, and a pacer  7   c  is arranged on a side wall of the word line pattern  6   b . An interlayer insulator  7   e  is arranged over the whole surface of the upper body patterns  6   a ′ and  6   a ″ having the transmission transistors T 1  and T 2 . An etching stopper layer  7   d  may be additionally interposed between the interlayer insulator  7   e  and the upper body patterns  6   a ′ and  6   a ″ having the transmission transistors T 1  and T 2 . Accordingly, the transmission transistors T 1  and T 2  which are thin film transistors are stacked over the pull-up transistors PU 1  and PU 2 , respectively. 
     In case where the memory cell is arranged as shown in  FIG. 13A , the inverter and the NAND gate of  FIGS. 13B and 13C  have the same arrangement as that of  FIGS. 12B and 12C . 
     Referring to  FIGS. 13D and 20 , a drain region P 5 D of the PMOS transistor P 5  is electrically connected to a node semiconductor plug  65   b  which penetrates interlayer insulators  64   e  and  61   e  and the etching stopper layer  41   d , and an upper body pattern  65   a  is arranged to cover the interlayer insulator  64   e  and the node semiconductor plug  65   b.    
     Referring to  FIGS. 14A ,  17 A and  17 B, the lower node semiconductor plug  3   a ′, the upper node semiconductor plug  4   a ′, the drain region PD 1 D of the pull-down transistor PD 1 , the drain region PU 1 D of the pull-up transistor PU 1 , the source region T 1 S of the transmission transistor T 1 , the gate electrode PD 2 G of the pull-down transistor PD 2 , and the gate electrode PU 2 G of the pull-up transistor PU 2  are electrically connected through a node plug  8   a ′. The lower node semiconductor plug  3   a ″, the upper node semiconductor plug  4   a ″, the drain region PD 2 D of the pull-down transistor PD 2 , the drain region PU 2 D of the pull-up transistor PU 2 , the source region T 2 S of the transmission transistor T 2 , the gate electrode PD 1 G of the pull-down transistor PD 1 , and the gate electrode PU 1 G of the pull-up transistor PU 1  are electrically connected through a node plug  8   a″.    
     In case where the memory cell is arranged as shown in  FIG. 14A , the inverter and the NAND gate of  FIGS. 14B and 14C  have the same arrangement as that of  FIGS. 13B and 13C . 
     Referring to  FIGS. 14D and 20 , gate patterns  66   a ′ and  66   a ″ are arranged over the upper body pattern  65   a  to overlap over the gate patterns  60   c ′ and  60   c ″. As shown in  FIG. 20 , gate electrodes N 4 G and N 5 G of the NMOS transistors N 4  and N 5  are arranged over the upper body pattern  65   a , and a drain region N 5 D of the NMOS transistor N 5 , source and drain regions N 5 S and N 5 D of the NMOS transistors N 4  and N 5 , and a source region N 4 S of the NMOS transistor N 4  are provided in the upper body pattern  65   a . A capping insulating layer  67   a ′ is arranged over the gate electrode N 5 G, and a gate insulating layer  67   b ′ is arranged below the gate electrode N 5 G. Likewise, a capping insulating layer  67   a ″ is arranged over the gate electrode N 4 G, and a gate insulating layer  67   b ″ is arranged below the gate electrode N 4 G. Spacers  67   c ′ and  67   c ″ are arranged on side walls of the gate patterns  66   a ′ and  66   a ″, and an interlayer insulator  67   e  is arranged over the whole surface of the upper body pattern  65   a  having the NMOS transistors N 4  and N 5 . An etching stopper layer  67   d  may be additionally interposed between the interlayer insulator  67   e  and the upper body pattern  65   a  having the NMOS transistors N 4  and N 5 . Accordingly, the NMOS transistors N 4  and N 5  are stacked over the PMOS transistors P 4  and P 5 , respectively. 
     Referring to  FIGS. 15A ,  17 A and  17 B, an interlayer insulator  9   c  is stacked on node plugs  8   a ′ and  8   a ″ and the interlayer insulator  7   e . The source region PU 1 S of the pull-up transistor PU 1  is electrically connected to a power line contact plug  9   a ′, and the source region PU 2 S of the pull-up transistor PU 2  is electrically connected to a power line contact plug  9   a ″. The source region PD 1 S of the pull-down transistor PD 1  is electrically connected to a ground line contact plug  9   b ′, and the source region PD 2 S of the pull-down transistor PD 2  is electrically connected to a ground line contact plug  9   b″.    
     Referring to  FIGS. 15B and 18 , an interlayer insulator  26  is stacked on the interlayer insulator  24   e . The node semiconductor plug  22   b , the drain region N 1 D of the NMOS transistor N 1 , the drain region P 1 D of the PMOS transistor P 1  are electrically connected to an output signal line contact plug  25   a , the source region P 1 S of the PMOS transistor P 1  is electrically connected to a power line contact plug  25   b , and the source region N 1 S of the NMOS transistor N 1  is electrically connected to a ground line contact plug  25   c . Even though not shown, the gate electrodes P 1 G and N 1 G of the PMOS transistor P 1  and the NMOS transistor N 1  are electrically connected to an input signal line contact plug  25   d.    
     Referring to  FIGS. 15C and 19 , an interlayer insulator  46  is stacked on the interlayer insulator  44   e . The node contact plug  42   b , the drain region N 2 D of the NMOS transistor N 2 , the drain region P 2 D of the PMOS transistor P 2  are electrically connected to an output signal line contact plug  45   a , the source regions P 2 S and P 3 S of the PMOS transistors P 2  and P 3  are electrically connected to a power line contact plug  45   b , the drain region P 3 D of the PMOS transistor P 3  is electrically connected to an output signal line contact plug  45   c , and the source region N 3 S of the NMOS transistor N 3  is electrically connected to a ground line contact plug  45   d . The gate electrodes P 2 G and N 2 G of the PMOS transistor P 2  and the NMOS transistor N 2  are electrically connected to a first input signal line contact plug  25   e , and the gate electrodes P 3 G and N 3 G of the PMOS transistor P 3  and the NMOS transistor N 3  are electrically connected to a second input signal line contact plug  25   f.    
     Referring to  FIGS. 15D and 20 , an interlayer insulator  69  is stacked on the interlayer insulator  67   e . The node contact plug  65   b , the drain region P 5 D of the PMOS transistor P 5 , the drain region N 5 D of the NMOS transistor N 5  are electrically connected to an output signal line contact plug  68   a , the source region N 5 S of the NMOS transistor N 5  and the drain region N 4 D of the NMOS transistor N 4  are electrically connected to a ground line contact plug  68   b , the source region N 4 S of the NMOS transistor N 4  is electrically connected to an output signal line contact plug  68   c , and the source region P 4 S of the PMOS transistor P 4  is electrically connected to a power line contact plug  68   d . The gate electrodes P 5 G and N 5 G of the PMOS transistor P 5  and the NMOS transistor N 5  are electrically connected to a first input signal line contact plug  68   c , and the gate electrodes P 4 G and N 4 G of the PMOS transistor P 4  and the NMOS transistor N 4  are electrically connected to a second input signal line contact plug  68   d.    
     Referring to  FIGS. 16A ,  17 A and  17 B, an interlayer insulator  11  is arranged on the interlayer insulator  9   c . The power line contact plug  9   a ′ is covered with a power voltage line  10   b , and the ground line contact plug  9   b ′ is covered with a ground voltage line  10   a . The power line contact plug  9   a ″ is covered with a power voltage line  10   b , and the ground line contact plug  9   b ″ is covered with a ground voltage line  10   a . An interlayer insulator  12  is arranged on the interlayer insulator  11 , and the drain regions T 1 D and T 2 D of the transmission transistors T 1  and T 2  are electrically connected to bit line contact plugs  13   a ′ and  13   a ″, respectively. The bit line contact plugs  13   a ′ and  13   a ″ are covered with a bit line  14 . 
     Referring to  FIGS. 16B and 18 , an interlayer insulator  28  is arranged on the interlayer insulator  26 , the output signal line contact plug  25   a  is covered with an output signal line  27   a , the ground line contact plug  25   b  is covered with a ground voltage line  27   b , and the power line contact plug  25   c  is covered with the power voltage line  27   c . The input signal line contact plug  25   d  is covered with an input signal line  27   d.    
     Referring to  FIGS. 16C and 19 , an interlayer insulator  48  is arranged on the interlayer insulator  46 , the output signal line contact plug  45   a  is covered with an output signal line  47   a , the power line contact plug  45   b  is covered with a power voltage line  47   b , the output signal line contact plug  45   c  is covered with an output signal line  47   c , and the ground line contact plug  45   d  is covered with the ground voltage line  47   d . The first input signal line contact plug  45   e  is covered with a first input signal line  47   e , and the second input signal line contact plug  45   f  is covered with a second input signal line  47   f.    
     Referring to  FIGS. 16D and 20 , an interlayer insulator  71  is arranged on the interlayer insulator  69 , the output signal line contact plug  68   a  is covered with an output signal line  70   a , the ground line contact plug  68   b  is covered with a ground voltage line  70   b , the output signal line contact plug  68   c  is covered with an output signal line  70   a , and the power line contact plug  68   d  is covered with the power voltage line  70 . The first input signal line contact plug  68   e  is covered with a first input signal line  70   e , and the second input signal line contact plug  68   f  is covered with a second input signal line  70   f.    
     The node contact plugs and the upper and lower body patterns may be single crystal silicon substrates. The upper and lower body patterns may be poly silicon substrates, and in such instance there is no node contact plugs. 
     In case where the bulk transistors are arranged on the first layer of the memory cell and the thin film transistors are arranged on the second and third layers like the memory cell described above, it is preferred that the thin film transistors to be arranged on the second and third layers of the peripheral circuit have the same type as the thin film transistors arranged on the second and third layers of the memory cell for the convenience of manufacturing process. 
       FIGS. 21A and 21B  are views illustrating stacking structure of the memory cell array and the peripheral circuit according to a first embodiment of the present invention. In case where the bulk NMOS transistor, the thin film PMOS transistor, the thin film NMOS transistor are respectively arranged on the first to third layers of the memory cell array as shown in  FIG. 21A , it is preferred that the transistors having the types of  FIG. 21B  are arranged on the first to third layers of the peripheral circuit. That is, it is preferred that the bulk NMOS transistor or the bulk PMOS transistor may be arranged on the first layer and the thin film PMOS transistor and the thin film NMOS transistor having the same type as the thin film transistors arranged on the second and third layers of the memory cell are arranged on the second and third layers of the peripheral circuit. 
       FIGS. 22A and 22B  are views illustrating stacking structure of the memory cell array and the peripheral circuit according to a second embodiment of the present invention. In case where the bulk NMOS transistor, the thin film NMOS transistor, the thin film PMOS transistor are respectively arranged on the first to third layers of the memory cell array as shown in  FIG. 22A , it is preferred that the transistors having the types of  FIG. 22B  are arranged on the first to third layers of the peripheral circuit. That is, it is preferred that the bulk NMOS transistor or the bulk PMOS transistor may be arranged on the first layer and the thin film NMOS transistor and the thin film PMOS transistor having the same type as the thin film transistors arranged on the second and third layers of the memory cell are arranged on the second and third layers of the peripheral circuit. 
       FIGS. 23A and 23B  are views illustrating stacking stricture of the memory cell array and the peripheral circuit according to a third embodiment of the present invention. In case where the bulk PMOS transistor, the thin film NMOS transistor, the thin film NMOS transistor are respectively arranged on the first to third layers of the memory cell array as shown in  FIG. 23A , it is preferred that the transistors having the types of  FIG. 23B  are arranged on the first to third layers of the peripheral circuit. That is, it is preferred that the bulk NMOS transistor or the bulk PMOS transistor is arranged on the first layer and the thin film NMOS transistor and the thin film NMOS transistor having the same type as the thin film transistors arranged on the second and third layers of the memory cell are arranged on the second and third layers of the peripheral circuit. 
     Of course, the transistors to be arranged on the second and third layers of the peripheral circuit may have the different type from the transistors to be arranged on the second and third layers of the memory cell array. But, this makes the manufacturing process complicated. 
     The layout area size of the peripheral circuit as well as the layout area size of the memory cell can be reduced. 
     In the embodiments described above, stacking the transistors which constitute the inverter, the NAND gate, and the NOR gate are described. But, it is also possible to stack the transistors which constitute different logic circuits such as an AND gate and an OR gate. 
     The peripheral circuit of the present invention can be arranged such that only transistors which constitute some function blocks such as a row or column decoder other than all function blocks are stacked or only transistors which constitute a driver (which is comprised of an inverter in general) at an output terminal of a row and/or column decoder are stacked. 
     The above described arrangement method of the inverter, the NAND gate and the NOR gate which constitute the peripheral circuit can be usefully applied to different semiconductor devices. 
     If the transistors which form the peripheral circuit as well as the transistors which form the memory cell array are stacked the way described above, the layout area size of the peripheral circuit can be reduced, and thus the effect of the layout area size of the semiconductor memory device can be increased. 
     However, unlike the above described embodiments, the transistors which form the peripheral circuit may be arranged on a single layer even though the transistors of the memory cell array are stacked. In this case, it is possible to arrange high performance transistors even though it is difficult to reduce the layout area size of a region where the peripheral circuit is arranged. 
       FIGS. 24A and 24B  are views respectively illustrating arrangement of transistors of a static memory cell and transistors which constitute an inverter of a peripheral circuit of a semiconductor memory device according to a fourth embodiment of the present invention. The static memory cell is arrange the same way as that of  FIG. 8A , and the inverter is arranged such that a PMOS transistor P 1  and an NMOS transistor N 1  are arranged on the same layer like  FIG. 5B  but are arranged on the third layer  3 F other than  1 F. Here, the first and second layers serve as dummy layers and do not have any transistors formed thereon. 
     A method of forming the transistors of the peripheral circuit is explained below by describing a structure of the inverter of the peripheral circuit of the inventive semiconductor memory device and manufacturing method thereof. 
       FIG. 25  is a plan view illustrating the inverter of the peripheral circuit of  FIG. 24B , and  FIGS. 26A and 26B  to  FIGS. 34A and 34B  are cross-sectional views illustrating a method of manufacturing the memory cell and the inverter. In  FIGS. 26A and 26B  to  FIGS. 34A and 34B , references “C” and “P” denote a memory cell array region and a peripheral circuit region, respectively. The cross-sectional views of  FIGS. 26A to 34   a  are taken along lines I-I′ of  FIG. 10A  to  FIG. 16A  and III-III′ of  FIG. 25 , and the cross-sectional views of  FIGS. 26B to 34B  are taken along lines II-II′ of  FIG. 16A  and IV-IV′ of  FIG. 25 . 
     A semiconductor memory substrate  100  includes a cell region C and a peripheral circuit region P. The structure and arrangement of the cell region C can be understood easily with the above description, and thus a structure and arrangement of the peripheral circuit region P is explained below. 
     Referring to  FIG. 25  and  FIGS. 26A and 26B , when an interlayer insulator  2   e  is arranged over the cell region C, the interlayer insulator  2   e  is arranged above a portion of the semiconductor substrate SUB corresponding to the peripheral circuit region P. When an etching stopper layer  2   d  is arranged over the cell region C, the etching stopper layer  2   d  may be arranged over the peripheral circuit region P. The etching stopper layer  2   d  preferably has etching selectivity to the interlayer insulator  2   e . For example, in case where the interlayer insulator  2   e  is formed of a silicon oxide layer, the etching stopper layer  2   d  may be formed of a silicon nitride layer or a silicon oxynitride layer. 
     Referring to  FIG. 25  and  FIGS. 27A and 27B , when lower body patterns  3   b ′ and  3   b ″ are arranged over the cell region C, the etching stopper layer  2   d  and the interlayer insulator  2   e  arranged over the peripheral circuit region P are removed, and a peripheral lower body pattern  3   p  is arranged to cover the semiconductor substrate SUB over the peripheral circuit region P. In this case, the etching stopper layer  2   d  and the interlayer insulator  2   e  which remain in the cell region C may be respectively regarded as the etching stopper layer pattern and the interlayer insulator pattern. The peripheral lower body pattern  3   p  may be arranged such that its surface is located on the same imaginary horizontal line as surfaces of the lower body patterns  3   b ′ and  3   b ″ over the cell region C. The peripheral lower body pattern  3   p  may have a single crystal semiconductor structure. For example, in case where the semiconductor substrate SUB has a single crystal silicon structure, the peripheral lower body pattern  3   p  may have a single crystal silicon structure. 
     Referring to  FIG. 25  and  FIGS. 28A and 28B , when an etching stopper  5   d  and an interlayer insulator  5   e  which cover first and second load transistors TL 1  and TL 2  are arranged over the cell region C, the etching stopper  5   d  and the interlayer insulator  5   e  are arranged over the peripheral circuit region P. The etching stopper layer  5   d  preferably has etching selectivity to the interlayer insulator  5   e . For example, in case where the interlayer insulator  5   e  is formed of a silicon oxide layer, the etching stopper layer  5   d  may be formed of a silicon nitride layer or a silicon oxynitride layer. 
     Referring to  FIG. 25  and  FIGS. 29A and 29B , upper body patterns  6   a ′ and  6   a ″ are arranged over the cell region C, the etching stopper layer  5   d  and the interlayer insulator  5   e  arranged over the peripheral circuit region P are removed, and a peripheral upper body pattern  6   p  covering the peripheral lower body pattern  3   p  is arranged over the peripheral circuit region P. The peripheral upper body pattern  6   p  may be arranged such that its surface is located on the same imaginary horizontal line as surfaces of the upper body patterns  6   b ′ and  6   b ″ over the cell region C. The peripheral upper body pattern  6   p  may have a single crystal semiconductor structure which is the same crystal structure as the peripheral lower body pattern  3   p . For example, in case where the peripheral lower body pattern  3   p  has a single crystal silicon structure, the peripheral upper body pattern  6   p  may have a single crystal semiconductor structure such as a single crystal silicon structure. The peripheral upper and lower body patterns  6   p  and  3   p  form a peripheral body pattern  6   p′.    
     The peripheral upper and lower body patterns  6   p  and  3   p  may have a single crystal semiconductor structure such as a single crystal silicon structure formed by a single process. An element isolating insulator  7   e ′ is arranged on the peripheral upper body pattern  6   p  over the peripheral circuit region P. 
     Referring to  FIG. 25  and  FIGS. 30A and 30B , when a word line pattern  6   b  of NMOS transistors T 1  and T 2  is arranged over the cell region C, a gate pattern  23   a ′ of a PMOS transistor P 1  which crosses a first peripheral active area  1   p  of the peripheral circuit region P is arranged. The gate pattern  23   a ′ of the PMOS transistor P 1  may include a poly silicon layer pattern P 1 G and a PMOS gate metal silicide layer  24   a ′ which are sequentially stacked. A gate pattern  20   c ″ of an NMOS transistor N 1  which crosses a second peripheral active area  1   p ′ is arranged. The gate pattern  20   c ″ of the NMOS transistor N 1  may include a poly silicon layer pattern N 1 G and an NMOS gate metal silicide layer  21   a ′ which are sequentially stacked. The gate metal silicide layers  21   a ′ and  24   a ′ may be formed of a nickel silicide layer, a cobalt silicide layer, a titanium silicide layer or a tungsten silicide layer. The NMOS transistors T 1  and T 2  over the cell region C may also include a metal silicide layer  7   d ′. On surfaces of the first peripheral active area  1   p  located on both sides of the PMOS gate pattern  23   a ′, a drain region P 1 D and a source region P 1 S of the PMOS transistor P 1  are arranged. The PMOS gate pattern  23   a ′ forms the PMOS transistor P 1  together with the source and drain regions P 1 S and P 1 D. Similarly, on surfaces of the second peripheral active area  1   p ′ located on both sides of the NMOS gate pattern  20   c ″, a drain region N 1 D and a source region N 1 S of the NMOS transistor NP 1  are arranged. The NMOS gate pattern  20   c ″ forms the NMOS transistor N 1  together with the source and drain regions N 1 S and N 1 D. On surfaces of the source and drain regions P 1 S and P 1 D of the PMOS transistor P 1  and surfaces of the source and drain regions N 1 S and N 1 D of the NMOS transistor N 1 , metal silicide layers  7   d ′ are respectively arranged. The metal silicide layers  7   d ′ may be formed of a nickel silicide layer, a cobalt silicide layer, a titanium silicide layer or a tungsten silicide layer. An interlayer insulator  7   e  is arranged on the whole surface of the semiconductor substrate having the NMOS transistor N 1  and the PMOS transistor P 1 . In addition, an etching stopper layer  7   d  may be interposed between the semiconductor substrate SUB and the interlayer insulator  7   e . The etching stopper layer  7   d  preferably has etching selectivity to the interlayer insulator  7   e . For example, in case where the interlayer insulator  7   e  is formed of a silicon oxide layer, the etching stopper layer  7   d  may be formed of a silicon nitride layer or a silicon oxynitride layer. 
     Referring to  FIG. 25  and  FIGS. 31A and 31B , an interlayer insulator  9   c  is arranged on the interlayer insulator  7   e  over the peripheral circuit region P like the cell region C. 
     Referring to  FIG. 25  and  FIGS. 32A and 32B , a peripheral power line contact plug  9   e , a peripheral ground line contact plug  9   f ′, and output signal line contact plugs  9   f  and  9   e ′ may be arranged in the interlayer insulator  9   c  over the peripheral circuit region P. 
     An interlayer insulator  11  which covers the peripheral power line contact plug  9   e , the peripheral ground line contact plug  9   f ′, and the output signal line contact plugs  9   f  and  9   e ′ is arranged. 
     Referring to  FIG. 25  and  FIGS. 33A and 33B , in the interlayer insulator  11  over the peripheral circuit region P, a peripheral power line  10   e  is arranged to cover the peripheral power line contact plug  9   e , a peripheral ground line  10   f  is arranged to cover the peripheral ground line contact plug  9   f ′, and an output signal line  10   g  is arranged to cover the output signal line contact plugs  9   f  and  9   e′.    
     An interlayer insulator  12  is arranged to cover the peripheral power line  10   e , the peripheral ground line  10   f , and the output signal line  10   g.    
     In the above described way, the transistors P 1  and N 1  which form the inverter are arranged on the third layer of the peripheral circuit region P. Of course, transistors which form an NAND gate and a NOR gate may be also arranged on the third layer of the peripheral circuit region P. 
     A method of manufacturing an SRAM according to the present invention is explained below with reference to  FIG. 16 ,  FIG. 25 , and  FIGS. 26A and 26B  to  FIGS. 34A and 34B . 
     Referring to  FIG. 16A ,  FIG. 25 , and  FIGS. 26A and 26B , a semiconductor substrate SUB having a cell region C and a peripheral circuit region P is prepared. The semiconductor substrate SUB may be a single crystal silicon substrate. The semiconductor substrate SUB may be a p-type silicon substrate. An element isolating layer  1 ′ is formed on a predetermined region of the semiconductor substrate SUB to define first and second cell active areas  1   b ′ and  1   b ″. The element isolating layer  1 ′ is preferably formed in the cell region C. The first and second active areas  1   b ′ and  1   b ″ are formed parallel to a y axis. In addition, the element isolating layer  1 ′ is formed to provide a first ground active area  1   a ′ which extends along an x axis from one end of the first active area  1   b ′ and a fourth active area  1   a ″ which extends along an x axis from one end of the second active area  1   b ″. The second and fourth active areas  1   a ′ and  1   a ″ are formed to face each other. 
     Gate insulating layers  2   b ′ and  2   b ″ are formed on the first to fourth active areas  1   a ′,  1   b ′,  1   a ″, and  1   b ″. A gate conductive layer and a capping insulating layer are sequentially formed on the whole surface of the semiconductor substrate SUB having the gate insulating layers  2   b ′ and  2   b ″. The gate conductive layer may be formed of a silicon layer, and the capping insulating layer may be formed of a silicon oxide layer or a silicon nitride layer. The gate capping insulating layer and the gate conductive layer are patterned to form a gate pattern  1   c ′ which crosses the first active area  1   b ′ and a gate pattern  1   c ″ which crosses the third active area  1   b ″. As a result, the gate pattern  1   c ′ is formed to have a gate electrode PD 1 G and a capping insulating layer  2   a ′ which are sequentially stacked, and a gate pattern  1   c ″ is formed to have a gate electrode PD 2 G and a capping insulating layer  2   a ″ which are sequentially stacked. A process for forming the capping insulating layer may be omitted. In this case, the gate pattern  1   c ′ has only the gate electrode, and the gate pattern  1   c ″ has only the gate electrode. 
     Impurity ions are doped into the first to fourth active areas  1   a ′,  1   b ′,  1   b ″, and  1   a ″ by using the gate patterns  1   c ′ and  1   c ″ as an ion doping mask. As a result, a source region PD 1 S and a drain region PD 1 D which are separated from each other are formed in the first active area  1   b ′, and a source region PD 2 S and a drain region PD 2 D which are separated from each other are formed in the third active area  1   b ″. The source regions PD 1 S and PD 2 S and the drain regions PD 1 D and PD 2 D may be n-type ion-doped regions. The source region PD 1 S and the drain region PD 1 D are formed on both sides of a channel area below the driving gate pattern  1   c ′, and the source region PD 2 S and the drain region PD 2 D are formed on both sides of a channel area below the driving gate pattern  1   c ″. The source region PD 2 S is also formed in the second active area  1   a ′, and the source region PD 2 S is also formed in the fourth active area  1   a ″. The source regions PD 1 S and PD 2 S and the drain regions PD 1 D and PD 2 D may be formed to have a lightly doped drain (LDD) type structure. Gate spacers  2   c  are formed on sidewalls of the gate patterns  1   c ′ and  1   c ″. The gate spacers  2   c  may be formed of a silicon nitride layer or a silicon oxide layer. 
     The first driving gate pattern  1   c ′, the source region PD 1 S and the drain region PD 1 D form the first bulk transistor, i.e., the first NMOS transistor PD 1 , and the second driving gate pattern  1   c ″, the source region PD 2 S and the drain region PD 2 D form the second bulk transistor, i.e., the second NMOS transistor PD 2 . 
     An etching stopper layer  2   d  and an interlayer insulator  2   e  are sequentially formed on the whole surface of the semiconductor substrate SUB having the first and second transistors PD 1  and PD 2 . The interlayer insulator  2   e  is preferably planarized by using a chemical mechanical polishing technique. In this case, the etching stopper layer  2   d  on the gate patterns  1   c ′ and  1   c ″ may serve as a chemical mechanical polishing stopper. 
     Referring to  FIG. 16A ,  FIG. 25  and  FIGS. 27A and 27B , the interlayer insulator  2   e  and the etching stopper layer  2   d  are patterned to expose predetermined regions of the drain regions PD 1 D and PD 2 D of the cell region C and expose the semiconductor substrate of the peripheral circuit region P. As a result, the lower node contact holes  2   f ′ and  2   f ″ which sequentially penetrate the interlayer insulator layer  2   e  and the etching stopper layer  2   d  to expose the predetermined regions of the drain regions PD 1 D and PD 2 D of the cell region C may be formed in the cell region C. In this case, the interlayer insulator layer  2   e  and the etching stopper layer  2   d  may be respectively regarded as the interlayer insulator layer pattern and the etching stopper layer pattern. A semiconductor layer  3   p  is formed to cover the interlayer insulator  2   e  and the semiconductor substrate SUB of the peripheral circuit region P while filling the lower node contact holes  2   f ′ and  2   f ″. The semiconductor layer  3   p  may be formed of a single crystal semiconductor structure. The single crystal semiconductor structure may be formed by an epitaxial technique. In more detail, a single crystal semiconductor structure, i.e., an epitaxial layer which covers the interlayer insulator  2   e  and the semiconductor substrate SUB over the peripheral circuit region P while filling the lower node contact holes  2   f ′ and  2   f ″ is formed. The epitaxial technique may be a selective epitaxial growth technique. The epitaxial layer may be formed by a selective epitaxial growth technique which uses as a seed layer a predetermined region of the semiconductor substrate SUB exposed by the lower node contact holes  2   f ′ and  2   f ″ and the semiconductor substrate SUB of the peripheral circuit region P. In case where the semiconductor substrate SUB is a single crystal silicon substrate, the epitaxial layer may be formed to have a single crystal silicon structure. That is, the epitaxial layer may be formed of a single crystal semiconductor structure. Then, an upper surface of the epitaxial layer may be planarized by using a planarization technique such as a chemical mechanical polishing (CMP) technique. 
     Meanwhile, a semiconductor layer which fills the lower node contact holes  2   f ′ and  2   f ″ and covers the interlayer insulator  2   e  and the semiconductor substrate SUB of the peripheral circuit region P may be formed of a non-single crystal semiconductor layer. For example, the semiconductor layer may be formed of an amorphous silicon layer or a poly silicon layer. The semiconductor layer may be planarized. In this case, before or after planarizing the semiconductor layer, the semiconductor layer may be crystallized using an epitaxial technique, i.e., solid phase epitaxial technique which employs as a seed layer the semiconductor substrate which contacts the semiconductor layer. As a result, the semiconductor layer can be formed as a single crystal semiconductor structure. 
     The single crystal semiconductor structure is patterned to form lower body patterns  3   b ′ and  3   b ″ over the cell region while forming a peripheral lower body pattern  3   p  which covers the semiconductor substrate SUB of the peripheral circuit region P. The lower body patterns  3   b ′ and  3   b ″ are preferably formed to overlap the first and third active areas  1   b ′ and  1   b ″, respectively. The lower body patterns  3   b ′ and  3   b ″ are formed to cover the lower node contact holes  2   f ′ and  2   f ″, respectively. 
     Preferably, the lower body pattern  3   b ′ has an extension portion which overlaps a portion of the second active area  1   a ′. Similarly, it is preferred that the cell lower body pattern  3   b ″ has an extension portion which overlaps a portion of the fourth active area  1   a″.    
     Meanwhile, a single crystal semiconductor layer is formed to fill the lower node contact holes  2   f ′ and  2   f ″ and cover the interlayer insulator  2   e  and the semiconductor substrate SUB of the peripheral circuit region P. The single crystal semiconductor is subjected to the chemical mechanical polishing process to form the lower node contact plugs  3   a ′ and  3   a ″ in the lower node contact holes  2   f ′ and  2   f ″ and form a peripheral single crystal semiconductor layer which covers the semiconductor substrate SUB of the peripheral circuit region P. The single crystal semiconductor layer may be formed by an epitaxial technology. Subsequently, a semiconductor layer, i.e., a lower body layer is formed on the whole surface of the semiconductor substrate SUB having the lower node contact plugs  3   a ′ and  3   a ″. In case where the lower node semiconductor plugs  3   a ′ and  3   a ″ are single crystal silicon plugs, the lower body layer may be formed of a non-single crystal semiconductor layer, i.e., an amorphous silicon layer or a polysilicon layer. The lower body layer may be crystallized using a solid phase epitaxial (SPE) technique which is well known to a person having ordinary skill in the art. For example, the solid phase epitaxial technique may include a process for heat-treating and crystallizing the lower body patterns  3   b ′ and  3   b ″ at a temperature of about 500° C. to about 800° C. 
     Meanwhile, the single crystal semiconductor structure is patterned to form the lower body patterns  3   b ′ and  3   b ″ while removing the single crystal semiconductor structure of the peripheral circuit region P to expose the semiconductor substrate SUB of the peripheral circuit region P. 
     Referring to  FIG. 16A ,  FIG. 25 , and  FIGS. 28A and 28B , a gate insulating layer is formed on surfaces of the lower body patterns  3   b ′ and  3   b ″. Load gate patterns  4   b ′ and  4   b ″ are formed to cross over the lower body patterns  3   b ′ and  3   b ″. The gate patterns  4   b ′ and  4   b ″ are preferably formed to overlap the gate patterns  1   c ′ and l c″, respectively. The gate patterns  4   b ′ and  4   b ″ may be formed the same way as the driving gate patterns  1   c ′ and  1   c ″. Thus, the gate pattern  4   b ′ may be formed to have a gate electrode PU 1 G and a capping insulating layer  5   a ′ which are sequentially stacked, and the gate pattern  4   b ″ may be formed to have a gate electrode PU 2 G and a capping insulating layer  5   a  which are sequentially stacked. 
     Impurity ions are doped into the lower body patterns  3   b ′ and  3   b ″ using the gate patterns  4   b ′ and  4   b ″ as an ion doping make. As a result, source and drain regions PU 1 S and PU 1 D which are separated from each other are formed in the lower body pattern  3   b ′, and source and drain regions PU 2 S and PU 2 D which are separated from each other are formed in the lower body pattern  3   b ″. The source and drain regions PU 1 S and PU 1 D are formed on both sides of a channel area below the gate pattern  4   b ′, and the source and drain regions PU 2 S and PU 2 D are formed on both sides of a channel area below the gate pattern  4   b ″. The source regions PU 1 S and PU 2 S are formed in the extension portion of the lower body pattern  3   b ′ and in the extension portion of the lower body pattern  3   b ″, respectively. The source region PU 1 S is formed in the lower body pattern  3   b ′ over the lower node contact plug  3   a ′, and the drain region PU 2 D is formed in the lower body pattern  3   b ″ over the lower node semiconductor plug  3   a ″. Here, the drain region PU 1 D may contact the lower node semiconductor plug  3   a ′, and the drain region PU 2 D may contact the lower node semiconductor plug  3   a″.    
     The source regions PU 1 S and PU 2 S and the drain regions PU 1 D and PU 2 D may be p-type ion-doped regions. 
     The source region PU 1 S and PU 2 S and the drain regions PU 1 D and PU 2 D may be formed to have an LDD-type structure. 
     Spacers  5   c  may be formed on sidewalls of the load gate patterns  4   b ′ and  4   b ″. The spacers  5   c  may be formed of a silicon nitride layer or a silicon oxide layer. 
     The gate pattern  4   b ′, the source region PU 1 S and the drain region PU 1 D form a lower thin film transistor, i.e., a PMOS transistor PU 1 , and the gate pattern  4   b ″, the source region PU 2 S and the drain region PU 2 D form a lower thin film transistor, i.e., a PMOS transistor PU 2 . The PMOS transistors PU 1  and PU 2  may be load transistors. An interlayer insulator  5   e  is formed on the whole surface of the semiconductor substrate having the load transistors PU 1  and PU 2 . Before forming the interlayer insulator  5   e , an etching stopper layer  5   d  may be additionally formed. The etching stopper layer  5   d  and the interlayer insulator  5   e  may be formed the same method as the etching stopper layer  3   d  and the interlayer insulator  3   e . In this case, the interlayer insulator  5   e  and the etching stopper layer  5   d  may be respectively regarded as the interlayer insulator pattern and the etching stopper layer pattern. 
     Referring to  FIG. 16A ,  FIG. 25 , and  FIGS. 29A and 29B , the etching stopper layer  5   d  and the interlayer insulator  5   e  are patterned to expose the source and drain regions PU 1 S and PU 2 D and expose the peripheral lower body pattern  3   p  of the peripheral circuit region P. As a result, the upper node contact holes  4   f ′ and  4   f ″ which sequentially penetrate the interlayer insulator  5   e  and the etching stopper layer  5   d  to expose the source and drain regions PU 1 S and PU 2 D may be formed in the cell region C. A semiconductor layer is formed to fill the upper node contact holes  4   f ′ and  4   f ″ on the interlayer insulator  5   e  and the peripheral circuit region P. The semiconductor layer may be formed of a single crystal semiconductor structure. The single crystal semiconductor structure may be formed by an epitaxial technique. The epitaxial technique may be a selective epitaxial technique. In more detail, a single crystal semiconductor structure, i.e., an epitaxial layer which covers the interlayer insulator  5   e  and the peripheral lower body pattern  3   p  and fills the upper node contact holes  4   f ′ and  4   f ″ is formed. The epitaxial layer may be formed to have a single crystal silicon structure. The epitaxial layer may be formed by a selective epitaxial growth technique which uses as a seed layer a predetermined region of the cell lower body patterns  3   b ′ and  3   b ″ exposed by the upper node contact holes  4   f ′ and  4   f ″ and the peripheral body pattern  3   p.    
     As described in  FIGS. 27A and 27B , in case where the single crystal semiconductor structure is patterned to form the cell lower body patterns  3   b ′ and  3   b ″ while removing the single crystal semiconductor structure of the peripheral circuit region P to expose the semiconductor substrate SUB of the peripheral circuit region P, the single crystal semiconductor structure, i.e., the epitaxial layer may be formed by a selective epitaxial growth technique which uses as a seed layer predetermined regions of the cell lower body patterns  3   b ′ and  3   b ″ exposed by the upper node contact holes  4   f ′ and  4   f ″ and the semiconductor substrate SUB of the peripheral circuit region P. Then, an upper surface of the epitaxial layer may be planarized by using a planarization technique such as a chemical mechanical polishing (CMP) technique. 
     Meanwhile, a semiconductor layer which fills the upper node contact holes  4   f ′ and  4   f ″ may be formed of a non-single crystal semiconductor layer on the interlayer insulator  5   e  and the peripheral circuit region P. For example, the semiconductor layer may be formed of an amorphous silicon layer or a poly silicon layer. The semiconductor layer may be planarized. In this case, before or after planarizing the semiconductor layer, the semiconductor layer may be crystallized using an epitaxial technique, i.e., solid phase epitaxial technique which employs as a seed layer the single crystal semiconductor structures which are arranged below the semiconductor layer and contact the semiconductor layer. As a result, the semiconductor layer can be formed as a single crystal semiconductor structure. 
     The single semiconductor structure is patterned to form upper body patterns  6   a ′ and  6   a ″ over the cell region C and form a peripheral upper body pattern  6   p  over the peripheral circuit region P. Here, the peripheral upper body pattern  6   p  is formed to have a peripheral trench  6   b  which defines first and second peripheral active areas  1   p  and  1   p ′. As a result, the peripheral upper body pattern  6   p  having the peripheral trench  6   b  is formed on the peripheral lower body pattern  3   p  of the peripheral circuit region P. The peripheral lower and upper body patterns  3   p  and  6   p  have the substantially same single crystal structure and may form a peripheral body pattern  6   p′.    
     Meanwhile, in case of performing a process for patterning the previously formed single crystal semiconductor structure to expose the semiconductor substrate SUB of the peripheral circuit region P, the sequentially formed single crystal semiconductor structure may be formed to directly contact the semiconductor substrate SUB of the peripheral circuit region P. As a result, the peripheral body pattern  6   p ′ may be formed of a single crystal semiconductor structure formed by a single process, i.e., a single crystal silicon structure. The upper body patterns  6   a ′ and  6   a ″ are formed to cover the upper node contact holes  4   f ′ and  4   f ″, respectively. The epitaxial layers formed in the upper node contact holes  4   f ′ and  4   f ″ may be defined as the upper node semiconductor plugs  4   a ′ and  4   a ″. The upper body patterns  6   a ′ and  6   a ″ are preferably formed to respectively overlap the lower body patterns  3   b ′ and  3   b ″. However, it is preferred that the upper body patterns  6   a ′ and  6   a ″ do not overlap the extension portions of the lower body patterns  3   b ′ and  3   b″.    
     Meanwhile, a single crystal semiconductor layer which fills the upper node contact holes  4   f ′ and  4   f ″ may be formed on the interlayer insulator  5   e  and the semiconductor substrate SUB of the peripheral circuit region P. Subsequently, the single crystal semiconductor layer is planarized to form the first and second upper node contact plugs  4   a ′ and  4   a ″ and form a single crystal semiconductor layer which remains over the peripheral circuit region P. The single crystal semiconductor layer may be a single crystal silicon structure formed by the epitaxial technique. Then, a semiconductor layer, i.e., an upper body layer may be formed on the whole surface of the semiconductor substrate SUB having the upper node semiconductor plugs  4   a ′ and  4   a ″. In case where the upper node semiconductor plugs  4   a ′ and  4   a ″ are single crystal silicon plugs, the upper body layer may be formed of an amorphous silicon layer or a poly silicon layer. The upper body layer is patterned to form the first and second body patterns  6   a ′ and  6   a ″, and the upper body layer over the peripheral circuit region P is patterned to form a peripheral trench  6   b  which defines the first and second peripheral active areas  1   p  and  1   p ′. The first and second upper body patterns  6   a ′ and  6   a ″ may be crystallized by a solid phase epitaxial technique which is well known to a person having ordinary skill in the art. The element isolating insulating layer  7   e ′ may be formed in the peripheral trench  6   b . Here, when the element isolating insulating layer  7   e ′ may be formed in the peripheral trench  6   b , the element isolating insulating layer  7   e ′ which fills a space between the upper body patterns  6   a ′ and  6   a ″ over the cell region C may be formed. 
     Meanwhile, the process for forming the element isolating insulating layer in the peripheral trench  6   b  may be omitted. 
     Referring to  FIG. 16A ,  FIG. 25 , and  FIGS. 30A and 30B , a gate insulating layer is formed on the cell upper body patterns  6   a ′ and  6   a ″ and the peripheral body pattern  6   p . A transmission gate pattern  6   b , i.e., a word line insulated to cross over the upper body patterns  6   a ′ and  6   a ″ is formed, and a peripheral PMOS gate pattern  23   a ′ and a peripheral NMOS gate pattern  20   c ″ which are insulated to cross over the first and second peripheral active areas  1   p  and  1   p ′ of the peripheral body pattern P are formed. 
     Meanwhile, before forming the peripheral gate patterns  23   a ′ and  20   c ″, impurity ions may be doped into the first and second peripheral active areas  1   p  and  1   p ′ to form an n-type well  7   f  and a p-type well  7   f ′. In case where the peripheral body pattern  6   p ′ is formed to have an n-type or p-type conductivity, a separate ion doping process for forming the n-type or p-type well may be omitted. 
     Impurity ions are doped into the upper body patterns  6   a ′ and  6   a ″ using the word line  6   p  as an ion doping mask. Further, impurity ions are doped into the first and second peripheral active areas  1   p  and  1   p ′ using the peripheral gate patterns  23   a ′ and  20   c ″ of the peripheral circuit region P and the element isolating insulating layer  7   e  as an ion doping mask. As a result, source and drain regions T 1 S and T 1 D which are separated from each other are formed in the upper body pattern  6   a ′, source and drain regions T 2 S and T 2 D which are separated from each other are formed in the upper body pattern  6   a ″, source and drain regions P 1 S and P 1 D which are separated from each other are formed in the peripheral active area  1   p , and source and drain regions N 1 S and N 1 D which are separated from each other are formed in the peripheral active area  1   p ′. In case where the source and drain regions T 1 S and T 1 D, T 2 S and T 2 D, P 1 S and P 1 D, and N 1 S and N 1 D have an LDD-type structure, an insulating spacer  7   c  may be formed on sidewalls of the word line  6   b  and sidewalls of the peripheral gate patterns  23   a ′ and  20   c″.    
     The source regions T 1 S and T 2 S and the drain regions T 1 D and T 2 D of the cell region C may be n-type ion-doped regions. The source and drain regions P 1 S and P 1 D of the peripheral active area  1   p  may be p-type ion-doped regions, and the source and drain regions N 1 S and N 1 D of the peripheral active area  1   p ′ may be n-type ion-doped regions. The word line  6   b  and the source and drain regions T 1 S and T 1 D constitute a cell upper thin film transistor, i.e., an NMOS transmission transistor T 1 , and the word line  6   b  and the source and drain regions T 2 S and T 2 D constitute a cell upper thin film transistor, i.e., an NMOS transmission transistor T 2 . The peripheral PMOS gate pattern  23   a ″ and the source and drain regions P 1 S and P 1 D constitute a peripheral PMOS transistor P 1 , and the peripheral NMOS gate pattern  20   c ″ and the source and drain regions N 1 S and N 1 D constitute a peripheral NMOS transistor N 1 . 
     A metal silicide layer may be selectively formed on surfaces of the gate electrodes and/or the source and drain regions of the peripheral transistors P 1  and N 1 . For example, a silicide process for lowering electrical resistance of the gate electrodes and the source and drain regions of the NMOS transmission transistor T 1 , the NMOS transmission transistor T 2 , the peripheral PMOS transistor P 1 , the peripheral NMOS transmission transistor N 1 . The silicide process is a process technology for selectively forming the metal silicide layer on the gate electrode and the source and drain regions to lower the electrical resistance of the gate electrode and the source and drain regions. The silicide process includes a silicidation annealing process. As the silicidation annealing process, either a rapid thermal process which employs a radiation method using a light source such as a lamp or a conduction method using a hot plate or an annealing process of a convection method using a heat transfer gas. 
     In more detail, after forming the gate insulting layer on the cell upper body patterns  6   a ′ and  6   a ″ and the peripheral body pattern  6   p , a silicon layer such as a poly silicon layer is formed on the substrate having the gate insulating layer. The poly silicon layer is patterned to form a poly silicon layer pattern which crosses over the cell upper body patterns  6   a ′ and  6   a ″ and form poly silicon layer patterns P 1 G and N 1 G which cross over the peripheral active areas  1   p  and  1   p ′ of the peripheral body pattern  6   p . An insulating spacer  7   c  is formed on sidewalls of the poly silicon layer patterns T 1 G, T 2 G, P 1 G, and N 1 G. The insulating spacer  7   c  may include a silicon oxide layer or a silicon nitride layer. Subsequently, the source and drain regions T 1 S and T 1 D, T 2 S and T 2 D, P 1 S and P 1 D, and N 1 S and N 1 D are formed. The poly silicon layer patterns T 1 G, T 2 G, P 1 G, and N 1 G and the source and drain regions T 1 S and T 1 D, T 2 S and T 2 D, P 1 S and P 1 D, and N 1 S and N 1 D may be exposed. Subsequently, a metal layer is formed on the semiconductor substrate having the poly silicon layer patterns T 1 G, T 2 G, P 1 G, and N 1 G and the source and drain regions T 1 S and T 1 D, T 2 S and T 2 D, P 1 S and P 1 D, and N 1 S and N 1 D. The metal layer may be formed of a nickel layer, a tungsten layer, a titanium layer, or a cobalt layer. Then, the metal layer may be subjected to the silicidation annealing process. 
     On the other hand, after forming the gate insulating layer on the cell upper body patterns  6   a ′ and  6   a ″ and the peripheral body pattern  6   p , a gate conductive layer containing a metal silicide layer, for example, a poly silicon layer and a metal silicide layer which are sequentially stacked may be formed on the semiconductor substrate having the gate insulating layer. Next, a hard mask insulating layer may be formed on the gate conductive layer. The hard mask insulating layer and the gate conductive layer may be patterned to form a poly silicon layer pattern, a metal silicide layer pattern and a hard mask pattern which are sequentially stacked. As a result, the poly silicon layer pattern, the metal silicide layer pattern and the hard mask pattern which are sequentially stacked may be formed as a gate pattern, and the source and drain regions may be exposed. A metal layer may be formed on the semiconductor substrate having the gate pattern and then may be subjected to the silicidation annealing process. As a result, metal silicide layers may be formed in the source and drain region. 
     Using the silicide process, a gate metal silicide layer  7   a , a PMOS gate metal silicide layer  24   a ′ and the NMOS gate metal silicide layer  21   a ′ may be respectively formed on the word line  6   p , the peripheral PMOS gate pattern  23   a ′ and the peripheral NMOS gate pattern  20   c ″, the metal silicide layers may be formed on respective surfaces of the source and drain regions T 1 S and T 1 D and T 2 S and T 2 D of the word line  6   b , the metal silicide layers  7   d ′ may be formed on respective surfaces of the source and drain regions P 1 S and P 1 D of the peripheral PMOS gate pattern  24   a ′, the metal silicide layers  7   d ′ may be formed on the respective surfaces of the source and drain regions N 1 S and N 1 D of the peripheral NMOS gate pattern  20   c ″. As a result, the word line  6   p  may be formed to have the poly silicon layer patterns T 1 G and T 2 G and the gate metal silicide layer  7   a  which are sequentially stacked. The peripheral PMOS gate pattern  23   a ′ may be formed to have the poly silicon layer pattern P 1 G and the PMOS gate metal silicide layer  24   a ′ which are sequentially stacked. The peripheral NMOS gate pattern  20   c ″ may be formed to have the poly silicon layer pattern N 1 G and the NMOS gate metal silicide layer  24   a ′ which are sequentially stacked. Accordingly, it is possible to lower the electrical resistance of the gate electrode and the source and drain regions of the peripheral transistors P 1  and N 1 . That is, transmission rate of the electrical signal applied to the gate electrodes of the peripheral transistors P 1  and N 1  can be improved. Further, since the sheet resistance of the source and drain regions of the peripheral transistors P 1  and N 1  can be improved, drivability of the peripheral transistors P 1  and N 1  can be improved. As a result, it is possible to implement the high performance MOS transistors in the peripheral circuit region P. Furthermore, since the electrical characteristics of the gate electrode and the source and drain regions of the transmission transistors T 1  and T 2  of the cell region C can be improved, performance of the transmission transistors T 1  and T 2  can be improved. 
     Thus, since the silicide process for improving the performance of the transistors of the peripheral circuit region P can be performed, performance of the SRAM can be improved. Further, in the semiconductor integrated circuits which employ the thin film transistors, the high performance MOS transistors having improved electrical characteristics can be obtained since the MOS transistors of the peripheral circuit region are formed after the peripheral body pattern is formed, as described above. The performance of the SRAM depends on the peripheral circuits formed in the peripheral circuit region, and thus the performance of the SRAM is determined by the performance of the transistors which are necessary components of the peripheral circuits. In the embodiments of the present invention, since the peripheral body pattern  6   p  is formed by using the semiconductor substrate of the peripheral circuit region as the seed layer, the peripheral body pattern  6   p  may be closer in crystallinity to the semiconductor substrate. That is, since the epitaxial layer is formed from the whole surface of the semiconductor substrate of the peripheral circuit region, the single crystal structure of the peripheral body pattern may be closer to the single crystal structure of the semiconductor substrate. The peripheral transistors formed in the peripheral circuit region P may have similar characteristics to the bulk transistors substantially formed on the semiconductor substrate. Further, the peripheral transistors formed in the peripheral circuit region P are not affected by heat which may be generated during a process for forming the thin film transistors of the cell region C. That is, the epitaxial process and the spacer process for manufacture the thin film transistors of the cell region C can be performed at a typical high temperature. Characteristics of the transistors exposed to the processes performed at the high temperature may be degraded, but the transistors of the peripheral circuit region P are not affected by the high temperature processes. Furthermore, since the metal silicide layers can be respectively formed on the gate electrode and the source and drain regions of the transistors of the peripheral circuit region P, the performance of the transistors of the peripheral circuit region P can be more improved. Thus, reliability of the semiconductor device can be more improved. 
     The interlayer insulator  7   e  is formed on the whole surface of the semiconductor substrate having the NMOS transistors T 1  and T 2 , the PMOS transistor P 1 , and the NMOS transistor N 1 . The etching stopper layer  7   d  may be additionally formed before forming the interlayer insulating layer  7   e.    
     Referring to  FIG. 16A ,  FIG. 25 , and  FIGS. 31A and 31B , the interlayer insulators  2   e ,  5   e  and  7   e  and the etching stopper layers  2   d ,  5   d  and  7   d  are etched to form a node contact hole  7   f ′ which exposes the source region T 1 S of the NMOS transistor T 1 , the upper node semiconductor plug  4   a ′, the drain region PU 1 D of the transistor PU 1 , the lower node semiconductor plug  3   a ′, the gate electrode PU 2 G, and the gate electrode PD 2 G and to form a node contact hole  7   f ″ which exposes the source region T 2 S of the NMOS transistor T 2 , the upper node semiconductor plug  4   a ″, the drain region PU 2 D of the transistor PU 2 , the lower node semiconductor plug  3   a ′″ the gate electrode PU 1 G, and the gate electrode PD 1 G. 
     Meanwhile, in case where the lower node semiconductor plugs  3   a ′ and  3   a ″ have the different conductive type from the drain regions PD 1 D and PD 2 D or are intrinsic semiconductors, the node contact holes  7   f ′ and  7   f ″ may be formed to expose the drain regions PD 1 D and PD 2 D of the MOS transistors PD 1  and PD 2 , respectively. 
     A conductive layer is formed on the semiconductor substrate having the node contact holes  7   f ′ and  7   f ″. The conductive layer is planarized to expose the interlayer insulator  7   e . As a result, the node contact plugs  8   a ′ and  8   a ″ are formed. The node contact plugs  8   a ′ and  8   a ″ are preferably formed of a conductive layer which shows ohmic contact characteristics to both p- and n-type semiconductors. For example, the conductive layer may be formed of a metal layer such as a tungsten layer. Further, the conductive layer may be formed by sequentially stacking a barrier metal layer such as a titanium nitride layer and a metal layer such as a tungsten layer. In this case, each of the node contact plugs  8   a ′ and  8   a ″ may be formed to have a tungsten plug and a barrier metal layer pattern which surrounds the tungsten plug. 
     The interlayer insulator  9   c  is formed on the semiconductor substrate having the node contact plugs  8   a ′ and  8   a″.    
     Referring to  FIG. 16A ,  FIG. 25 , and  FIGS. 32A and 32B , the ground line contact plugs  9   b ′ and  9   b ″ which penetrate the interlayer insulators  2   e ,  5   e ,  7   e , and  9   c  and the etching stoppers  2   d ,  5   d  and  7   d  to respectively contact the source region PD 1 S in the second active area  1   a ′ and the source region PD 2 S of the fourth active area  1   a ″ are formed. While forming the ground line contact plugs  9   b ′ and  9   b ″, the power line contact plugs  9   a ′ and  9   a ″ are formed which respectively contact the extension portion of the lower body pattern  3   b ′ (source region PU 1 S of the load transistor) and the extension portion of the lower body pattern  3   b ″ (source region PU 2 S of the load transistor). Further, while forming the ground line contact plugs  9   b ′ and  9   b ″, the output signal line contact plug  9   e  and the peripheral power line contact plug  9   f  which respectively contact the source and drain regions P 1 S and P 1 D of the PMOS transistor P 1 , and the output signal line contact plug  9   e ′ and the peripheral power line contact plug  9   f  which respectively contact the source and drain regions N 1 S and N 1 D of the NMOS transistor N 1 . The contact plugs  9   a ′,  9   a ″,  9   b ′,  9   b ″,  9   f ,  9   e ,  9   f ′, and  9   e ′ are preferably formed of a conductive layer which shows the ohmic contact characteristics to both p- and n-type semiconductors. For example, the contact plugs  9   a ′,  9   a ″,  9   b ′,  9   b ″,  9   f ,  9   e ,  9   f ′, and  9   e ′ may be formed the same way as the method of forming the node contact plugs  8   a ′ and  8   a ″ which is described with reference to  FIGS. 31A and 31B . 
     The interlayer insulator  11  is formed on the semiconductor substrate having the contact plugs  9   a ′,  9   a ″,  9   b ′,  9   b ″,  9   f ,  9   e ,  9   f ′, and  9   e′.    
     Referring to  FIG. 16A ,  FIG. 25 , and  FIGS. 33A and 33B , the cell ground line  10   a  and the cell power line  10   b  are formed in the interlayer insulator  11 . While forming the cell ground line  10   a  and the cell power line  10   b , the peripheral power line  10   e , the peripheral ground line  10   f  and the output signal line  10   g  may be formed in the interlayer insulator  11  of the peripheral circuit region P. 
     In the embodiments of the present invention, the inverter is depicted in the drawings as an example of the peripheral circuit, but the peripheral circuit is not limited to this. That is, the MOS transistors of the peripheral circuit region P can be used as components of the various peripheral circuits. That is, the peripheral power line  10   e , the peripheral ground line  10   f  and the output signal line  10   g  are to implement the inverter as an example of the peripheral circuit, and the PMOS transistor and the NMOS transistor of the peripheral circuit region P can constitute various peripheral circuits. 
     The cell ground line  10   a  and the cell power line  10   b  may be formed to be substantially parallel to the word line  6   b . The cell ground line  10  is formed to cover the ground line contact plugs  9   b ′ and  9   b ″, and the cell power line  10   b  is formed to cover the power line contact plugs  9   a ′ and  9   a ″. The output signal line  10   g  is formed to cover the output signal line contact plugs  9   e ′ and  9   f . The peripheral ground line  10   f  is formed to cover the peripheral ground line contact plug  9   f ′. While forming the output signal line  10   g , the input signal line  10   h  which is electrically connected to the peripheral PMOS gate electrode  23   a ′ and the peripheral NMOS gate electrode  20   c ″ may be formed. The input signal line  10   h  may be electrically connected to the peripheral PMOS gate electrode  23   a ′ and the peripheral NMOS gate electrode  20   c ″ by the input signal line contact plug. The interlayer insulator  12  is formed on the semiconductor substrate having the ground lines  10   a  and  10   f , the power lines  10   b  and  10   e , the output signal line  10   g , the input signal line  10   h.    
     Referring to  FIG. 16A ,  FIG. 25 , and  FIGS. 34A and 34B , the interlayer insulators  7   e ,  9   c ,  11 , and  12  and the etching stopper layer  7   d  are etched to form the first and second contact plugs  13   a ′ and  13   a ″ which respectively contact the drain region T 1 D of the NMOS transistor T 1  and the drain region T 2 D of the NMOS transistor T 2 . The first and second parallel bit lines  14  are formed on the interlayer insulator  12 . The first and second bit lines  14  are formed to cross over the cell ground line  10   a  and the cell power line  10   b . The first bit line  14  is formed to cover the bit line contact plug  13   a ′, and the second bit line  14  is formed to cover the bit line contact plug  13   a″.    
     The above described embodiments have been described focusing on the static semiconductor memory device, but the peripheral circuit of the present invention can be employed in the dynamic semiconductor memory device to reduce the layout area size. 
     As described herein before, the semiconductor memory device and the arrangement method thereof according to the present invention can reduce the whole layout area size because it is possible to stack the transistors which constitute the peripheral circuit as well as the memory cell array. 
     Further, the semiconductor memory device and the manufacturing method thereof according to the present invention can provide the semiconductor integrated circuits having high integrated memory cells and high performance peripheral transistors because the memory cell having the thin film transistors is provided in the memory cell array and the peripheral transistors are provided in the peripheral body pattern of the single crystal semiconductor structure grown from the semiconductor substrate of the peripheral circuit region. That is, stable operation can be performed by stacking the transistors which constitute the memory cell array and arranging the transistors which constitute the peripheral circuit on the third layer. 
       FIG. 35A  is a view taken along line I-I′ of  FIG. 16A , illustrating the structures of the memory cell and inverter of the semiconductor memory device according to another embodiment of the present invention, and  FIG. 35B  is a view taken along line III-III′ of  FIG. 16B , illustrating the structures of the memory cell and inverter of the semiconductor memory device according to another embodiment of the present invention. In  FIGS. 35A and 35B , C denotes the memory cell array region, and P denotes the peripheral circuit region. 
     The semiconductor memory devices illustrated in  FIGS. 35A and 35B  do not have a two or three-layered semiconductor layer formed by an epitaxial growth technique, and instead, wafers are bonded to second and third layers by a wafer bonding technique. Since the wafer bonding technique does not require a high temperature annealing process, unlike the epitaxial technique, transistors of the peripheral circuit can be formed on first and second layers as in the transistors of the memory cell, and a metal layer can be formed on gates and/or the sources and drains. In addition, the metal layer may be subjected to the silicidation annealing process. 
     The structures and manufacturing methods of the semiconductor memory devices according to the embodiments of the present invention illustrated in  FIGS. 35A and 35B  are similar to those illustrated in  FIGS. 34A and 34B . However, since the epitaxial technique is not used to form the semiconductor layer in the semiconductor memory devices illustrated in  FIGS. 35A and 35B , the node contact structures  3   a ′ and  3   a ″ illustrated in  FIGS. 34A and 34B  are removed, but the metal layers may be formed on the gates of the transistors formed on the first and second layers of the memory cell, respectively. Afterwards, the transistors can be manufactured using the same method used in manufacturing the semiconductor memory device illustrated in  FIGS. 34A and 34B . 
     In the semiconductor memory devices illustrated in  FIGS. 35A and 35B , when transistors are formed in the memory array region of the first layer, the entire peripheral circuit region may be formed into an active area without separating the devices from the peripheral circuit region, and when the gates of the transistors in the memory cell array region are formed, the peripheral circuit region can be exposed without forming transistors in the entire peripheral circuit region. 
     Further, when the transistors are formed in the memory cell array region of the second layer, the semiconductor layer can be exposed, or may remain such that the peripheral circuit region that is separated from the memory cell array region is not exposed. 
       FIG. 36  is a schematic view illustrating arrangement of the embodiment with reference to the layout of the inverter illustrated in  FIG. 16B , in which an NMOS transistor N 1  and a PMOS transistor P 1  constituting the inverter are respectively stacked on a first layer  1 F and a second layer  2 F of three layers  1 F to  3 F. 
       FIGS. 37 to 44  are views illustrating a method of manufacturing a semiconductor memory device according to another embodiment of the present invention. These drawings are provided to describe a method of forming the structure of the memory cell in the memory cell array of  FIG. 35A  and the structure of the inverter viewed from the cross-section of line X-X′ in the layout of  FIG. 16B . In  FIGS. 37 and 44 , C denotes a memory cell array region, and P is a peripheral circuit region. 
     Referring to  FIGS. 16A and 37 , bulk transistors, i.e., NMOS transistors PD 1  and PD 2  are formed on a semiconductor substrate (SUB) using the same method as illustrated in  FIG. 26A . Referring to  FIGS. 16B and 37 , first and second active areas  20   a ′ and  20   b ′ are arranged to face each other, and a gate pattern  20   c ′ is formed in a direction of a y axis over the first and second active areas  20   a ′ and  20   b ′ and one end of the gate pattern  20   c ′ is extended to be parallel to an x axis from the first active area  20   a ′. A drain region N 1 D of the NMOS transistor N 1  is provided on a surface of the first active area  20   a ′, and a source region N 1 S of the NMOS transistor N 1  is provided on a surface of the second active area  20   b ′. Further, the gate pattern  20   c ′ of the NMOS transistor N 1  may include a gate electrode N 1 G and a capping insulating layer  21   a  of the NMOS transistor N 1 , which are sequentially stacked, and a gate insulating layer  21   b  is interposed between the gate pattern  20   c ′ and the semiconductor substrate SUB. A spacer  21   c  may be provided on sidewalls of the gate pattern  20   c ′, and an interlayer insulating layer  21   e  is stacked on an entire surface of the semiconductor substrate SUB having the NMOS transistor N 1 . An etching stopper layer  21   d  may be further interposed between the semiconductor substrate SUB having the NMOS transistor N 1  and the interlayer insulating layer  21   e . As a result, the bulk transistor, i.e., the NMOS transistor N 1  constituting the inverter, is formed on the semiconductor substrate SUB. If gate electrodes PD 1 G, PD 2 G and N 1 G are formed of poly silicon, top surfaces of the gate electrodes and the source and drain regions PD 1 S, PD 1 D, N 1 D and N 1 S may be exposed, and a metal layer is then formed on the entire surface of the semiconductor substrate having the gate electrodes PD 1 G, PD 2 G and T 1 G and the source and drain regions PD 1 S, PD 1 D, N 1 D and N 1 S. The metal layer may be a nickel layer, a tungsten layer, a titanium layer or a cobalt layer. Subsequently, the metal layer may be subjected to the silicidation annealing process. 
     Alternatively, after a gate insulating layer of the transistors PD 1 , PD 2  and N 1  is formed, a gate conductive layer having a metal silicide layer, e.g., sequentially stacked poly silicon layer and metal silicide layer may be formed on the semiconductor substrate having the gate insulating layer. Subsequently, an insulating layer for a hard mask may be formed on the gate conductive layer. The insulating layer for the hard mask and the gate conductive layer may be sequentially patterned to form a poly silicon layer pattern, a metal silicide layer pattern and a hard mask layer pattern, which are sequentially stacked. As a result, the sequentially stacked poly silicon layer pattern, metal silicide layer pattern and hard mask layer pattern are formed as a gate pattern, and the source and drain regions may be exposed. After forming a metal layer on the entire surface of the semiconductor substrate having the gate pattern, the metal layer may be subjected to the silicidation annealing process. Consequently, metal silicide layers may be formed in the source and drain regions. 
     In addition, a wafer S 1  is stacked over the transistors PD 1 , PD 2  and N 1  and an insulator  2   e  using the wafer bonding technique. In this case, although not illustrated in the drawings, an insulating layer is present below the wafer S 1  bonded to the second layer. The wafer S 1  having an oxide layer may be bonded over the transistors PD 1 , PD 2  and N 1 , or one side of the wafer S 1  may be first subjected to an ion doping process and then bonded over the transistors PD 1 , PD 2  and N 1 . 
     That is, since the semiconductor memory device of the present invention does not use the epitaxial technique, the metal layer can be formed on the gate of the transistor N 1  of the peripheral circuit as well as the gates of the transistors PD 1  and PD 2  of the memory cell formed on the first layer. Accordingly, performance of the transistor N 1  of the peripheral circuit, as well as those of the transistors PD 1  and PD 2  of the memory cell, may also be improved. The transistor of the peripheral circuit requiring high performance can be formed on the first layer. The metal layer may not be formed on the gates of the transistors PD 1  and PD 2  of the memory cell, according to necessity. 
     Referring to  FIGS. 16A ,  16 B and  38 , lower body patterns  3   b ′ and  22   a  are formed by patterning the wafer S 1 . That is, the wafer S 1  is planarized by cutting and/or chemical mechanical polishing (CMP) to reduce a thickness, thereby forming the lower body patterns  3   b ′ and  22   a . However, when the thickness of the bonded wafer S 1  is small, the cutting and/or CMV may not be used. 
     Referring to  FIGS. 16A ,  16 B and  39 , a gate insulating layer is formed on surfaces of the lower body patterns  3   b ′ and  22   a . Gate patterns  4   b ′ and  23   a  are formed to cross over the lower body patterns  3   b ′ and  22   a . Preferably, the gate patterns  4   b ′ and  23   a  are formed to overlap the gate patterns  1   c ′ and  20   c ′, respectively. The gate patterns  4   b ′ and  23   a  may be formed using the same method used in forming the driving gate patterns  1   c ′ and  20   c ′. Accordingly, the gate pattern  4   b ′ may be formed to have a gate electrode PU 1 G and a capping insulating layer  5   a ′, which are sequentially stacked, and the gate pattern  23   a  may be formed to have a gate electrode P 1 G and a capping insulating layer  24   a , which are sequentially stacked. Impurity ions are doped into the lower body patterns  3   b ′ and  22   a  using the gate patterns  4   b ′ and  23   a  as an ion doping mask. As a result, source and drain regions PU 1 S and PU 1 D which are separated from each other are formed in the lower body pattern  3   b ′, and source and drain regions P 1 S and P 1 D which are separated from each other are formed in the lower body pattern  23   a . The source and drain regions PU 1 S and PU 1 D are formed in both sides of a channel area below the gate pattern  4   b ′, and the source and drain regions P 1 S and P 1 D are formed in both sides of a channel area below the gate pattern  23   a.    
     The source regions PD 1 S and PU 1 S and the drain regions PD 1 D and PU 1 D may be p-type ion-doped regions. 
     The source regions PD 1 S and PU 1 S and the drain regions PD 1 D and PU 1 D may be formed to have an LDD-type structure. Spacers  5   c  and  24   c  may be formed on sidewalls of the gate patterns  4   b ′ and  23   a . The spacers  5   c  and  24   c  may be formed of a silicon nitride layer or a silicon oxide layer. 
     Interlayer insulators  5   e  and  24   e  are formed on the entire surface of the semiconductor substrate having transistors PU 1 , PU 2  and P 1 . Etching stopper layers  5   d  and  24   d  may be further formed before forming the interlayer insulators  5   e  and  24   e . The etching stopper layers  5   d  and  24   d  and the interlayer insulators  5   e  and  24   e  may be manufactured using the same methods used in forming the etching stopper layers  2   d  and  21   d  and the interlayer insulators  2   e  and  21   e . In this case, the etching stopper layers  5   d  and  24   d  and the interlayer insulating layers  5   e  and  24   e  may be considered etching stopper layer patterns and interlayer insulator patterns, respectively. 
     Like the transistors PD 1 , PD 2  and N 1  formed on the first layer, transistors PU 1 , PU 2  and P 1  formed on the second layer are capable of having metal layers, which can be subjected to the silicidation annealing process. 
     Further, after forming a gate insulating layer of the transistors PD 1 , PD 2  and N 1 , a gate conductive layer including a metal silicide layer, e.g., a poly silicon layer and a metal silicide layer, which are sequentially stacked, may be formed on the semiconductor substrate having the gate insulating layer. Subsequently, an insulating layer for a hard mask may be formed on the gate conductive layer. The insulating layer for the hard mask and the gate conductive layer may be sequentially patterned to form a poly silicon layer pattern, a metal silicide layer pattern and a hard mask layer pattern, which are sequentially stacked. As a result, the poly silicon layer pattern, the metal silicide layer pattern and the hard mask layer pattern which are sequentially stacked may be formed as a gate pattern, and source and drain regions may be exposed. 
     After forming a metal layer on the entire surface of the semiconductor substrate having the gate pattern, the metal layer may be subjected to the silicidation annealing process. As a result, metal silicide layers may be formed in the source and drain regions. 
     Further, a wafer S 2  is stacked over the transistors PU 1 , PU 2  and P 1  and the insulating layers  5   e  and  24   e  using the wafer bonding technique. An insulating layer is formed below the wafer S 2  bonded to a third layer. To this end, the wafer S 2  having an oxide layer may be bonded over the transistors PU 1 , PU 2  and P 1 , or the wafer S 2  may be bonded over the transistors PU 1 , PU 2  and P 1  after an ion doping process is performed on one side of the wafer S 2 . 
     That is, since the semiconductor memory device of the present invention does not use the epitaxial technique, it is possible to form the metal layer on the gates of the transistors PU 1 , PU 2  and P 1  formed on the second layer. Accordingly, the performances of the transistors PU 1  and PU 2  of the memory cell and the transistor P 1  of the peripheral circuit may be improved. It is possible to form the transistor of the peripheral circuit requiring high performance on the second layer. The metal layer may not be formed on the gates of the transistors PU 1  and PU 2  of the memory cell, according to necessity. 
     Referring to  FIGS. 16A ,  16 B and  40 , the wafer S 2  is patterned to form upper body patterns  6   a ′. That is, the wafer S 2  is planarized using the cutting and/or CMP to have a smaller thickness, thereby forming the upper body pattern  6   a ′. In this case, the peripheral circuit region may also be planarized using the cutting and/or CMP. 
     Referring to  FIGS. 16A ,  16 B and  41 , a gate insulating layer is formed on a surface of the upper body pattern  6   a ′. A gate pattern  6   b  is formed to cross over the upper body pattern  6   a ′. It is preferable that the gate pattern  6   b  is formed to overlap the gate pattern  4   b ′. The gate pattern  6   b  may be formed using the same method used in forming the gate patterns  1   c ′ and  4   c ′. Thus, the gate pattern  6   b  may include a gate electrode T 1 G and a capping insulating layer  7   a , which are sequentially stacked. 
     Impurity ions may be doped into the upper body patterns  6   a ′ using the gate pattern  6   b  as an ion-doping mask. As a result, source and drain regions T 1 S and T 1 D separated from each other are formed in the upper body pattern  6   a ′. The source and drain regions T 1 S and T 1 D are formed in both sides of a channel area below the gate pattern  6   b , respectively. 
     The source and drain regions T 1 S and T 1 D may be n-type ion doped regions. 
     The source and drain regions T 1 S and T 1 D may be formed to have an LDD-type structure. Spacers  7   c  may be formed on sidewalls of the gate pattern  6   b . The spacers  7   c  may be formed of a silicon nitride layer or a silicon oxide layer. 
     Interlayer insulators  7   e  and  26  are formed on the entire surface of the semiconductor substrate having the transistor T 1 . Before forming the interlayer insulators  7   e  and  26 , an etching stopper layer  7   d  may be further formed. The etching stopper layer  7   d  and the interlayer insulators  7   e  and  26  may be manufactured using the same methods used in forming the etching stopper layers  5   d  and  24   d  and the interlayer insulators  5   e  and  24   e . In this case, the etching stopper layer  7   d  and the interlayer insulators  7   e  and  26  may be considered an etching stopper layer pattern and an interlayer insulator pattern, respectively. The transistor T 1  formed on the third layer can have a metal layer as in the transistors PU 1 , PU 2  and P 1  formed on the second layers, and the metal layer can be subjected to the silicidation annealing process. 
     After forming a gate insulating layer of the transistor T 1 , a gate conductive layer including a metal silicide layer, e.g., a poly silicon layer and a metal silicide layer which are sequentially stacked, may be formed on the semiconductor substrate having the gate insulating layer. Subsequently, an insulating layer for a hard mask may be formed on the gate conductive layer. The insulating layer for the hard mask and the gate conductive layer may be sequentially patterned to form a poly silicon layer pattern, a metal silicide layer pattern and a hard mask layer pattern, which are sequentially stacked. As a result, the poly silicon layer pattern, the metal silicide layer pattern and the hard mask layer pattern which are sequentially stacked may be formed as a gate pattern, and source and drain regions may be exposed. After forming a metal layer on the entire surface of the semiconductor substrate having the gate pattern, the metal layer may be subjected to the silicidation annealing process. As a result, metal silicide layers may be formed in the source and drain regions. 
     Referring to  FIGS. 16A ,  16 B and  42 , the interlayer insulator  7   e  and the etching stopper layer  7   d  are etched to form a node contact hole  7   f ′ exposing the source region T 1 S of the NMOS transistor T 1 , the drain region PU 1 D of the transistor PU 1 , the gate electrode PU 2 G and the gate electrode PD 2 G. A conductive layer is formed on the semiconductor substrate having the node contact hole  7   f ′. The conductive layer is planarized, thereby exposing the interlayer insulator  7   e . As a result, a node contact plug  8   a ′ is formed. An interlayer insulator  9   c  is formed on the entire surface of the semiconductor substrate having the node plug  8   a′.    
     The drain region N 1 D of the NMOS transistor N 1  and the drain region P 1 D of the PMOS transistor P 1  are in electrical contact with an output signal line contact plug  25   a , the source region P 1 S of the PMOS transistor P 1  is in electrical contact with a power line contact plug  25   b , and the source region N 1 S of the NMOS transistor N 1  is in electrical contact with a ground line contact plug  25   c . Although not illustrated in the drawings, the gate electrodes P 1 G and N 1 G of the PMOS transistor P 1  and the NMOS transistor N 1  are in electrical contact with an input signal line contact plug  25   d . An interlayer insulator  28  is formed on the entire surface of the semiconductor substrate having the plugs  25   a ,  25   b  and  25   c.    
     Referring to  FIGS. 16A ,  16 B and  43 , a ground line contact plug  9   b ′ is formed in contact with the source region PD 1 S in the second active region  1   a ′ through the interlayer insulators  2   e ,  5   e ,  7   e  and  9   c  and the etching stopper layers  2   d ,  5   d  and  7   d . During the formation of the ground line contact plug  9   b ′, a power line contact plug  9   a ′ is formed in contact with an extension portion of the lower body pattern  3   b ′ (the source region PU 1 S of the load transistor) and an extension portion of the lower body pattern  3   b ″ (the source region PU 2 S of the load transistor) during the formation of the ground line contact plug  9   b ′. Furthermore, at this time, the drain region N 1 D of the NMOS transistor N 1  and the drain region P 1 D of the PMOS transistor P 1  are in electrical contact with the output signal line contact plug  25   a , the source region P 1 S of the PMOS transistor P 1  is in electrical contact with the power line contact plug  25   b , and the source region N 1 S of the NMOS transistor N 1  is in electrical contact with the ground line contact plug  25   c.    
     An interlayer insulator  11  is formed on the entire surface of the semiconductor substrate having the contact plugs  9   a ′ and  9   b ′, and an interlayer insulator  30  is formed on the entire surface of the semiconductor substrate having the contact plugs  25   a ,  25   b  and  25   c.    
     Referring to  FIGS. 16A ,  16 B and  44 , a cell ground line  10   a  and a cell power line  10   b  are formed in the interlayer insulator  11 . During the formation of the cell ground line  10   a  and the cell power line  10   b , a power signal line  27   a , a peripheral ground voltage line  27   b  and a power voltage line  27   c  may be formed in the interlayer insulator  30  of the peripheral circuit region P. 
     The cell ground line  10   a  is covered on the contact plug  9   b ′, the cell power line  10   b  covers the contact plug  9   a ′, the output signal line  27   a  covers the output line contact plug  25   a , the ground voltage line  27   b  covers the ground line contact plug  25   b , and the power voltage line  27   c  covers the power line contact plug  25   c.    
     As illustrated in  FIGS. 42 to 44 , for electrical connections between the gates, sources and drains of the at least two transistors which are overlapped, it is preferable that through electrodes such as the node plug  8   a ′ and the contact plugs  25   a  and  25   b  are formed. Further, for electrical connections between gates, sources and drains of the lower layer and lines or electrodes of the upper layer, it is preferable that through electrodes such as the contact plugs  9   a ′,  9   b ′ and  25   c  are formed. 
     Since the semiconductor memory device of the present invention does not use the epitaxial technique, the lower node contact plugs  3   a ′ and  3   a ″ and the upper node contact plugs  4   a ′ and  4   a ″ are not formed as illustrated in  FIGS. 34A and 34B . Thus, a resistance of a contact  9   c  can be reduced without an increase in a contact area size during formation of the through contact  9   c.    
     Since a semiconductor memory device of the present invention uses a wafer bonding technique to stack transistors, a high temperature annealing process used in an epitaxial technique is not needed, and a metal layer can be formed on gates and/or sources and drains of the transistors disposed on each layer. As a result, as transistors requiring high performance are stacked and arranged in a peripheral circuit region, a layout area size can be reduced. 
     While, in the above-described embodiments, a static semiconductor memory device was used to exemplify reducing the layout area size, a layout area size of a dynamic semiconductor memory device or a flash memory device can also be reduced by stacking transistors in a peripheral circuit region. 
     Further, in the semiconductor memory device of the present invention, transistors may be formed on a first layer by the epitaxial technique, and transistors may be formed on second and third layers by the wafer bonding technique. That is, it is not necessary to use the wafer bonding technique in order to form all of the semiconductor layers. Moreover, in the semiconductor memory device of the present invention, transistors in a cell array region may be manufactured using the epitaxial technique, and transistors in a peripheral circuit region can be manufactured using the wafer bonding technique. While, in the above-descried embodiments, the memory cell array region and the peripheral circuit region are separated from each other, these regions need not be separated. Accordingly, although interlayer insulators of the memory cell array region and the peripheral circuit region are represented by different reference numerals in the present invention, this does not imply that the interlayer insulators are formed separately from each other. 
     While a stacked transistor structure constituting an inverter in the peripheral circuit region is illustrated in the above-described embodiments, any transistors constituting any logic gates, e.g., NAND gates and NOR gates, in addition to inverters, can be stacked to form such a structure. 
     In addition, while the transistors of the semiconductor memory device are stacked in a three-layered structure in the above-described embodiments, they can be stacked in a two or four or more-layered structure.