Patent Publication Number: US-2002001048-A1

Title: Method of fabricating liquid crystal display with a high aperture ratio

Description:
BACKGROUND OF THE INVENTION  
       [0001] 1. Field of the Invention  
       [0002] The present invention relates to a method of fabricating a liquid crystal display, and more particularly to a method of fabricating liquid crystal display with a high aperture ratio.  
       [0003] 2. Description of the Related Art  
       [0004] As well known, it is essential to increase an aperture ratio in order to obtain a liquid crystal display with a high quality screen. Therefore, a method has been proposed in which a pixel electrode area is enlarged. According to this method, a transparent resin insulating layer is interposed between a pixel electrode and data and gate lines to reduce a coupling capacitance and then the pixel electrode is extended to an upper part of the data line, thereby eliminating the separation thereof.  
       [0005] The conventional liquid crystal display will be described in more detail referring to FIGS. 1 and 2.  
       [0006]FIG. 1 is a plane view and FIG. 2 is a cross-sectional view for showing a conventional method of fabricating liquid crystal display with a high aperture ratio.  
       [0007] Referring to FIG. 1, a gate bus line  11  and a data bus line  15  are crossed on a lower substrate  10  to define a unit pixel area in a lattice shape. Here, the data bus line  15  and the gate bus line  11  are insulated by a gate insulating layer (not shown) interposed between them.  
       [0008] When the gate bus line  11  is formed, a storage capacitor electrode  11   b  is also formed in parallel with the gate bus line  11  and a thin film transistor is formed in the vicinity of the intersection of the lines  11  and  15 . The thin film transistor comprises a gate electrode  11   a  extended from the gate bus line  11  to a unit pixel area at a predetermined distance and the source/drain electrodes  15   a  and  15   b  extended from the data bus line  15  at a predetermined distance.  
       [0009] In each unit pixel area, pixel electrodes  17  are disposed, overlapping with sides of the gate bus line  11  and the data bus line  15 , thereby obtaining a high aperture ratio. Here, the pixel electrode  17  is in contact with the drain electrode  15   b  and the contact part thereof is shown as a reference number  19  in FIG. 1.  
       [0010] The method of fabricating a conventional liquid crystal display with a high aperture ratio will be described as follows.  
       [0011] First, a gate electrode  11   a  and a storage capacitor electrode lib are formed together on a lower substrate  10 .  
       [0012] And, a gate insulating layer  12  is deposited on the entire surface of the lower substrate  10  and then, a channel layer  13  is formed to cover the gate insulating layer  12  on a thin film transistor formative region.  
       [0013] Subsequently, a doped amorphous silicon layer  14  for ohmic contact and source/drain metal layers are deposited on the channel layer  13  and then selectively etched to form source/drain electrodes  15   a  and  15   b , thereby obtaining a thin film transistor.  
       [0014] Then, a transparent resin insulating layer  16  is formed on the lower substrate  1  obtained after completion of the thin film transistor in order to reduce coupling capacitance of data bus line and pixel electrode and to eliminate a cause of screen quality degradation. The insulating layer  16  is then selectively etched to expose a predetermined part of the drain electrode  15 , thereby forming a contact hole (not shown).  
       [0015] Finally, a pixel electrode  17  is formed on the transparent resin insulating layer  16 , being in contact with the exposed drain electrode  15   b . As shown in FIG. 2, the pixel electrode  17  is overlapped with predetermined parts of the data bus line  15  and the gate bus line  11 .  
       [0016] However, the conventional method of fabricating liquid crystal display with a high aperture ratio has problems as follows.  
       [0017] First, in a conventional method, a transparent resin insulating layer is formed on the lower substrate in order to eliminate a cause of screen quality degradation by reducing coupling capacitance of data bus line and pixel electrode.  
       [0018] The resin insulating layer is formed to have a thickness of several μm in order to prevent screen quality degradation. Due to the thickness, capacitance is reduced and a large electrode is required, thereby decreasing an aperture ratio.  
       SUMMARY OF THE INVENTION  
       [0019] Therefore, the present invention has been made to solve the problems of conventional method. The object of the present invention is to provide a liquid crystal display with an improved screen quality and high aperture ratio by reducing a thickness of transparent resin insulating layer using a half-tone exposure.  
       [0020] In order to achieve the above object, the present invention comprises the steps of: forming a gate bus line including a gate electrode on a transparent insulating substrate and at the same time, forming a storage capacitor electrode in parallel with the gate bus line; depositing a gate insulating layer on the resulting entire surface; forming a semiconductor layer on the gate insulating layer over the gate electrode; forming a data line including source/drain electrodes on the semiconductor layer, thereby completing a thin film transistor; depositing an insulating layer on the resulting lower substrate, wherein the thickness of the insulating layer region formed over the storage capacitor electrode is thinner than that formed over the other part; forming a contact hole by selectively etching the insulating layer in order to expose a predetermined part of the drain electrode; and forming a pixel electrode on the insulating layer to be in contact with the exposed drain electrode.  
       [0021] According to the present invention, a liquid crystal display with a high aperture ration is obtained by the following steps of: forming a gate bus line including a gate electrode on a transparent insulating substrate and at the same time, forming a storage capacitor electrode in parallel with the gate bus line; depositing a gate insulating layer on the resulting surface; forming a semiconductor layer on the gate insulating layer over the gate electrode; forming a data line including source/drain electrodes on the semiconductor layer, thereby completing a thin film transistor; depositing a resin insulating layer on the lower substrate, wherein the thickness of the resin insulating layer region formed over the storage capacitor electrode is thinner than that formed over the other part by using a half-tone mask comprising a chrome silicide layer with different transmittance; forming a contact hole by selectively removing the resin insulating layer to expose a predetermined part of the drain electrode; and forming a pixel electrode on the resin insulating layer to be in contact with the exposed drain electrode, wherein the pixel electrode is overlapped with a predetermined part of the data bus line and the gate bus line. 
     
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
     [0022]FIGS. 1 and 2 are a plane view and a cross-sectional view for showing a conventional method of fabricating a liquid crystal display with a high aperture ratio.  
     [0023]FIG. 3 is a plane view for showing a method of fabricating a liquid crystal display with a high aperture ratio according to the present invention.  
     [0024]FIG. 4 is a cross-sectional view for showing a method of fabricating a liquid crystal display with a high aperture ratio according to the present invention.  
     [0025]FIG. 5 is a cross-sectional view for showing an exposure method of a half-tone mask according to the present invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION  
     [0026] The preferred embodiment of the present invention will be described in detail referring to the drawings.  
     [0027]FIG. 3 is a plane view of a liquid crystal display with a high aperture ratio according to the present invention and FIG. 4 is a cross-sectional view taken along IV-IV line of FIG. 3.  
     [0028] Referring to FIG. 3, a gate line  21  and a data line  25  are perpendicularly crossed on a lower substrate  20 , thereby defining a unit pixel area in a lattice shape. The data bus line  25  and the gate bus line  21  are insulated by a gate insulating layer (not shown) interposed between them.  
     [0029] And, when the gate bus line  21  is formed, a storage capacitor electrode  21   b  is also formed in parallel with the gate bus line  21 . In the vicinity of the intersection of the gate bus line  21  and the data bus line  25 , a thin film transistor is formed, comprising a gate electrode  21   a  and source/drain electrodes  25   a  and  25   b . Here, the gate electrode  21   a  is formed to extend from the gate bus line  21  to a unit pixel area, and the source/drain electrodes  25   a  and  25   b  are formed to extend from the data bus line  25 . Additionally, pixel electrodes  27  are disposed in each unit pixel area, overlapping with sides of the gate bus line  21  and the data bus line  25 , thereby increasing an aperture ratio. Also, the pixel electrode  27  is in contact with a drain electrode  25   b , and the contact part thereof is shown as a reference number  29  in FIG. 3.  
     [0030] Referring to FIG. 4, a method of liquid crystal display according to the present invention comprises the steps of: forming a gate electrode  21   a  and a storage capacitor electrode  11   a  on a lower substrate  20 ; depositing a gate insulating layer  22  over the entire surface of the lower substrate  20 ; forming a semiconductor layer comprising a channel layer  23  and doped amorphous silicon layer  24  for ohmic contact to cover the gate insulating layer  22  on a thin film transistor formative region; forming metal layers for source/drain on the semiconductor layer; forming source/drain electrodes  25   a  and  25   b  by selectively etching the metal layers and doped amorphous silicon layer  24 , thereby completing a thin film transistor; depositing a resin insulating layer  26  on the resulting lower substrate  20 ; forming a contact hole (not shown) to expose a predetermined part of the drain electrode  25   b  by selectively etching the resin insulating layer  26 ; and forming a pixel electrode  27  on the transparent resin insulating layer  26  to be in contact with the exposed drain electrode  25   b , overlapping with a predetermined part of the data bus line  25  and the gate bus line  21 .  
     [0031] In the above processes, the resin insulating layer  26  is deposited in order to reduce coupling capacitance between the data bus line and the pixel electrode and preferably, using a chrome silicide layer of half-tone mask having different transmittance. Therefore, the resin insulating layer  26  is formed to be thinner on the storage capacitor electrode  21   b  than on the data line and on the gate line.  
     [0032]FIG. 5 is a drawing for showing an exposure method of the half-tone mask.  
     [0033] Referring to FIG. 5, a chrome silicide layer  101  is first deposited on a quartz substrate  100  and then a shielding layer  102  is formed on the layer to completely block light, thereby obtaining a half-tone mask  110 . The half-tone mask  110  comprises a region  103 : transmitting region for completely transmitting light, a region  104  for completely block light by a shielding layer  102  and a region  105 : half tone region for transmitting 30 to 70% of light.  
     [0034] The shielding layer  102  preferably comprises chrome. The thickness of the resin insulating layer  26  is formed to be thinner on the half-tone region  105  than on other parts.  
     [0035] Accordingly, as shown in FIG. 4, the thickness of the resin insulating layer  26  over the storage capacitor electrode  21   b  is deposited to be thinner than that over the data line including the drain electrode or the gate line including the gate electrode. As a result, it is possible to reduce the thickness of the resin insulating layer  26  formed over the storage capacitor formation region to one-third of several μm, and therefore to obtain high capacity in a limited area, thereby increasing an aperture ratio and brightness.  
     [0036] As described above, in a liquid crystal display with a high aperture ratio according to the present invention, a pixel electrode is extended to overlap with sides of a gate line and a data line.  
     [0037] And, a resin insulating layer is employed to reduce coupling capacitance between a data line and a pixel electrode, thereby eliminating a cause of a screen quality degradation.  
     [0038] And, a thickness of resin insulating layer over a storage capacitor is deposited to be thinner than that over a data line and on a gate line.  
     [0039] Therefore, a thickness of the resin insulating layer is reduced to one-third of several μm, thereby improving an aperture ratio and increasing brightness.  
     [0040] As the present invention may be embodied in several forms without departing from the spirit or essential characteristics thereof, it should also be understood that the above-described embodiment is not limited by any of the details of the foregoing description, unless otherwise specified, but rather should be construed broadly within its spirit and scope as defined in the appended claims, and therefore all changes and modifications that fall within the meets and bounds of the claims, or equivalences of such meets and bounds are therefore intended to be embraced by the appended claims.