Patent Publication Number: US-2021175211-A1

Title: Bonded semiconductor devices having programmable logic device and dynamic random-access memory and methods for forming the same

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is a divisional of U.S. application Ser. No. 16/727,890, filed on Dec. 26, 2019, entitled “BONDED SEMICONDUCTOR DEVICES HAVING PROGRAMMABLE LOGIC DEVICE AND DYNAMIC RANDOM-ACCESS MEMORY AND METHODS FOR FORMING THE SAME,” which is continuation of International Application No. PCT/CN2019/110977, filed on Oct. 14, 2019, entitled “BONDED SEMICONDUCTOR DEVICES HAVING PROGRAMMABLE LOGIC DEVICE AND DYNAMIC RANDOM-ACCESS MEMORY AND METHODS FOR FORMING THE SAME,” which claims the benefit of priorities to International Application No. PCT/CN2019/105290, filed on Sep. 11, 2019, entitled “BONDED SEMICONDUCTOR DEVICES HAVING PROCESSOR AND DYNAMIC RANDOM-ACCESS MEMORY AND METHODS FOR FORMING THE SAME,” and International Application No. PCT/CN2019/082607, filed on Apr. 15, 2019, entitled “INTEGRATION OF THREE-DIMENSIONAL NAND MEMORY DEVICES WITH MULTIPLE FUNCTIONAL CHIPS,” all of which are incorporated herein by reference in their entireties. This application is also related to U.S. application Ser. No. 16/727,893, filed on Dec. 26, 2019, entitled “BONDED SEMICONDUCTOR DEVICES HAVING PROGRAMMABLE LOGIC DEVICE AND NAND FLASH MEMORY AND METHODS FOR FORMING THE SAME,” which is hereby incorporated by reference in its entirety. 
    
    
     BACKGROUND 
     Embodiments of the present disclosure relate to semiconductor devices and fabrication methods thereof. 
     Field-programmable gate arrays (FPGAs) are reprogrammable integrated circuits that contain an array of programmable logic blocks. FPGA chip adoption is driven by their flexibility, hardware-timed speed and reliability, and parallelism. FPGAs provide benefits to designers of many types of electronic equipment, ranging from smart energy grids, aircraft navigation, automotive driver&#39;s assistance, medical ultrasounds, and data center search engines. Today, FPGAs are gaining prominence in another field as well: deep neural networks (DNNs) that are used for artificial intelligence (AI), such as in analyzing large amounts of data for machine learning. 
     SUMMARY 
     Embodiments of semiconductor devices and fabrication methods thereof are disclosed herein. 
     In one example, a semiconductor device includes a first semiconductor structure including a programmable logic device, an array of static random-access memory (SRAM) cells, and a first bonding layer including a plurality of first bonding contacts. The semiconductor device also includes a second semiconductor structure including an array of DRAM cells and a second bonding layer including a plurality of second bonding contacts. The semiconductor device further includes a bonding interface between the first bonding layer and the second bonding layer. The first bonding contacts are in contact with the second bonding contacts at the bonding interface. 
     In another example, a method for forming a semiconductor device is disclosed. A plurality of first semiconductor structures are formed on a first wafer. At least one of the first semiconductor structures includes a programmable logic device, an array of SRAM cells, and a first bonding layer including a plurality of first bonding contacts. A plurality of second semiconductor structures are formed on a second wafer. At least one of the second semiconductor structures includes an array of DRAM cells and a second bonding layer including a plurality of second bonding contacts. The first wafer and the second wafer are bonded in a face-to-face manner, such that the at least one of the first semiconductor structures is bonded to the at least one of the second semiconductor structures. The first bonding contacts of the first semiconductor structure are in contact with the second bonding contacts of the second semiconductor structure at a bonding interface. The bonded first and second wafers are diced into a plurality of dies. At least one of the dies includes the bonded first and second semiconductor structures. 
     In still another example, a method for forming a semiconductor device is disclosed. A plurality of first semiconductor structures are formed on a first wafer. At least one of the first semiconductor structures includes a programmable logic device, an array of SRAM cells, and a first bonding layer including a plurality of first bonding contacts. The first wafer is diced into a plurality of first dies, such that at least one of the first dies includes the at least one of the first semiconductor structures. A plurality of second semiconductor structures are formed on a second wafer. At least one of the second semiconductor structures includes an array of DRAM cells and a second bonding layer including a plurality of second bonding contacts. The second wafer is diced into a plurality of second dies, such that at least one of the second dies includes the at least one of the second semiconductor structures. The first die and the second die are bonded in a face-to-face manner, such that the first semiconductor structure is bonded to the second semiconductor structure. The first bonding contacts of the first semiconductor structure are in contact with the second bonding contacts of the second semiconductor structure at a bonding interface. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments of the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and to enable a person skilled in the pertinent art to make and use the present disclosure. 
         FIG. 1A  illustrates a schematic view of a cross-section of an exemplary semiconductor device, according to some embodiments. 
         FIG. 1B  illustrates a schematic view of a cross-section of another exemplary semiconductor device, according to some embodiments. 
         FIG. 2A  illustrates a schematic plan view of an exemplary semiconductor structure having a programmable logic device and SRAM, according to some embodiments. 
         FIG. 2B  illustrates a schematic plan view of an exemplary semiconductor structure having DRAM and peripheral circuits, according to some embodiments. 
         FIG. 3A  illustrates a schematic plan view of an exemplary semiconductor structure having a programmable logic device, SRAM, and peripheral circuits, according to some embodiments. 
         FIG. 3B  illustrates a schematic plan view of an exemplary semiconductor structure having DRAM, according to some embodiments. 
         FIG. 4A  illustrates a cross-section of an exemplary semiconductor device, according to some embodiments. 
         FIG. 4B  illustrates a cross-section of another exemplary semiconductor device, according to some embodiments. 
         FIG. 5A  illustrates a cross-section of still another exemplary semiconductor device, according to some embodiments. 
         FIG. 5B  illustrates a cross-section of yet another exemplary semiconductor device, according to some embodiments. 
         FIGS. 6A and 6B  illustrate a fabrication process for forming an exemplary semiconductor structure having a programmable logic device, SRAM, and peripheral circuits, according to some embodiments. 
         FIGS. 7A-7C  illustrate a fabrication process for forming an exemplary semiconductor structure having DRAM and peripheral circuits, according to some embodiments. 
         FIGS. 8A and 8B  illustrate a fabrication process for forming an exemplary semiconductor device, according to some embodiments. 
         FIGS. 9A-9C  illustrate a fabrication process for bonding and dicing an exemplary semiconductor structure, according to some embodiments. 
         FIGS. 10A-10C  illustrate a fabrication process for dicing and bonding an exemplary semiconductor structure, according to some embodiments. 
         FIG. 11  is a flowchart of an exemplary method for forming a semiconductor device, according to some embodiments. 
         FIG. 12  is a flowchart of another exemplary method for forming a semiconductor device, according to some embodiments. 
         FIG. 13  is a flowchart of an exemplary method for programming a semiconductor device having a programmable logic device and SRAM, according to some embodiments. 
     
    
    
     Embodiments of the present disclosure will be described with reference to the accompanying drawings. 
     DETAILED DESCRIPTION 
     Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. A person skilled in the pertinent art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of the present disclosure. It will be apparent to a person skilled in the pertinent art that the present disclosure can also be employed in a variety of other applications. 
     It is noted that references in the specification to “one embodiment,” “an embodiment,” “an example embodiment,” “some embodiments,” etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiments. Further, when a particular feature, structure or characteristic is described in connection with an embodiment, it would be within the knowledge of a person skilled in the pertinent art to effect such feature, structure or characteristic in connection with other embodiments whether or not explicitly described. 
     In general, terminology may be understood at least in part from usage in context. For example, the term “one or more” as used herein, depending at least in part upon context, may be used to describe any feature, structure, or characteristic in a singular sense or may be used to describe combinations of features, structures or characteristics in a plural sense. Similarly, terms, such as “a,” “an,” or “the,” again, may be understood to convey a singular usage or to convey a plural usage, depending at least in part upon context. In addition, the term “based on” may be understood as not necessarily intended to convey an exclusive set of factors and may, instead, allow for existence of additional factors not necessarily expressly described, again, depending at least in part on context. 
     It should be readily understood that the meaning of “on,” “above,” and “over” in the present disclosure should be interpreted in the broadest manner such that “on” not only means “directly on” something but also includes the meaning of “on” something with an intermediate feature or a layer therebetween, and that “above” or “over” not only means the meaning of “above” or “over” something but can also include the meaning it is “above” or “over” something with no intermediate feature or layer therebetween (i.e., directly on something). 
     Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper,” and the like, may be used herein for ease of description to describe one element or feature&#39;s relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. 
     As used herein, the term “substrate” refers to a material onto which subsequent material layers are added. The substrate itself can be patterned. Materials added on top of the substrate can be patterned or can remain unpatterned. Furthermore, the substrate can include a wide array of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made from an electrically non-conductive material, such as a glass, a plastic, or a sapphire wafer. 
     As used herein, the term “layer” refers to a material portion including a region with a thickness. A layer can extend over the entirety of an underlying or overlying structure or may have an extent less than the extent of an underlying or overlying structure. Further, a layer can be a region of a homogeneous or inhomogeneous continuous structure that has a thickness less than the thickness of the continuous structure. For example, a layer can be located between any pair of horizontal planes between, or at, a top surface and a bottom surface of the continuous structure. A layer can extend horizontally, vertically, and/or along a tapered surface. A substrate can be a layer, can include one or more layers therein, and/or can have one or more layer thereupon, thereabove, and/or therebelow. A layer can include multiple layers. For example, an interconnect layer can include one or more conductor and contact layers (in which interconnect lines and/or via contacts are formed) and one or more dielectric layers. 
     As used herein, the term “about” indicates the value of a given quantity that can vary based on a particular technology node associated with the subject semiconductor device. Based on the particular technology node, the term “about” can indicate a value of a given quantity that varies within, for example, 10-30% of the value (e.g., ±10%, ±20%, or ±30% of the value). 
     As used herein, a “wafer” is a piece of a semiconductor material for semiconductor devices to build in and/or on it and that can undergo various fabrication processes before being separated into dies. 
     The application of programmable logic devices (PLDs), in particular, FPGAs, is limited to its cost and working frequency. The relatively large chip area consumption of FPGA chips cause high cost, and the signal transfer delay, such as the resistive-capacitive (RC) delay from metal routing, limits the working frequency. 
     Various embodiments in accordance with the present disclosure provide a semiconductor device with a programmable logic device core, cache, and main memory integrated on a bonded chip to achieve higher working frequency, wider data bandwidth, lower power consumption, and lower cost. The semiconductor device disclosed herein can include a first semiconductor structure having a programmable logic device core and SRAM (e.g., as cache) and a second semiconductor structure having DRAM (e.g., as main memory) bonded to the first semiconductor structure with a large number of short-distanced vertical metal interconnects instead of the peripherally-distributed, long-distanced metal routing, or even conventional through silicon vias (TSVs). In some embodiments, the programmable logic device core includes a large number of programmable logic blocks to increase the efficiency of the chip area utilization, thereby reducing the cost. 
     As a result, shorter manufacturing cycle time with higher yield can be achieved due to less interactive influences from manufacturing programmable logic device of the programmable logic device wafer and the DRAM wafer as well as the known good hybrid bonding yield. The shorter connection distance between the programmable logic device and DRAM, such as from millimeter or centimeter-level to micrometer-level, can improve the device performance with faster data transfer rate, improve programmable logic device core logic efficiency with wider bandwidth, and improve system speed. 
       FIG. 1A  illustrates a schematic view of a cross-section of an exemplary semiconductor device  100 , according to some embodiments. Semiconductor device  100  represents an example of a bonded chip. The components of semiconductor device  100  (e.g., PLD/SRAM and DRAM) can be formed separately on different substrates and then jointed to form a bonded chip. Semiconductor device  100  can include a first semiconductor structure  102  including a programmable logic device and an array of SRAM cells. In some embodiments, the programmable logic device and SRAM cell array in first semiconductor structure  102  use complementary metal-oxide-semiconductor (CMOS) technology. Both the programmable logic device and the SRAM cell array can be implemented with advanced logic processes (e.g., technology nodes of 90 nm, 65 nm, 45 nm, 32 nm, 28 nm, 20 nm, 16 nm, 14 nm, 10 nm, 7 nm, 5 nm, 3 nm, 2 nm, etc.) to achieve high speed. 
     A programmable logic device is an electronic component used to build reconfigurable digital circuits, which has an undefined function at the time of manufacture and programmed (reconfigured) by using a program after the manufacturing. The programmable logic device can include, for example, programmable logic array (PLA), programmable array logic (PAL), generic array logic (GAL), complex programmable logic device (CPLD), and FPGA. 
     FPGA is an integrated circuit that can be configured by a customer or a designer after manufacturing, i.e., “field-programmable,” using a hardware description language (HDL). FPGAs include an array of programmable logic blocks and a hierarchy of reconfigurable interconnects that allow the programmable logic blocks to be connected in different configurations to implement different logic functions, according to some embodiments. The programmable logic blocks, also known as configurable logic blocks (CLBs), slices, or logic cells, are the basic logic unit of an FPGA, can be made up of two basic components: flip-flops and lookup tables (LUTs). Some FPGAs further include fixed-function logic blocks (e.g., multipliers), memory (e.g., embedded RAM), and input/output (I/O) blocks. 
     Unlike processors, FPGAs are truly parallel in nature, so different processing operations do not have to compete for the same resources, according to some embodiments. Each independent processing task can be assigned to a dedicated section of the FPGA and can function autonomously without any influence from other logic blocks. As a result, the performance of one part of the application is not affected when adding more processing, according to some embodiments. In some embodiments. another benefit of FPGAs over processor-based systems is that the application logic is implemented in hardware circuits rather than executing on top of an operating system (OS), drivers, and application software. 
     Other processing units (also known as “logic circuits”) besides the programmable logic device can be formed in first semiconductor structure  102  as well, such as the entirety or part of the peripheral circuits of the DRAM of a second semiconductor structure  104 . The peripheral circuits (also known as control and sensing circuits) can include any suitable digital, analog, and/or mixed-signal circuits used for facilitating the operations of the DRAM. For example, the peripheral circuits can include one or more of an input/output buffer, a decoder (e.g., a row decoder and a column decoder), a sense amplifier, or any active or passive components of the circuit (e.g., transistors, diodes, resistors, or capacitors). 
     The SRAM is integrated on the same substrate of the logic circuits (e.g., the programmable logic device and peripheral circuits), allowing wider bus and higher operation speed, which is also known as “on-die SRAM”. The memory controller of the SRAM can be embedded as part of the peripheral circuits. In some embodiments, each SRAM cell includes a plurality of transistors for storing a bit of data as a positive or negative electrical charge as well as one or more transistors that control access to it. In one example, each SRAM cell has six transistors (e.g., metal-oxide-semiconductor field-effect transistors (MOSFETs)), for example, four transistors for storing a bit of data and two transistors for controlling access to the data. The SRAM cells can locate in the area that is not occupied by the logic circuits (e.g., the programmable logic device and peripheral circuits) and thus, do not need extra space to be formed. The on-die SRAM can enable high-speed operations of semiconductor device  100 , used as one or more caches (e.g., instruction cache or data cache) and/or data buffers. In some embodiments, the SRAM is used for storing data sets or passing values between parallel tasks. In some embodiments, the SRAM is be used to support reprogramming of the programmable logic device, such as partial reconfiguration (PR) of an FPGA, which dynamically reconfigures a portion of the FPGA while the remaining FPGA design continues to function. 
     Semiconductor device  100  can also include second semiconductor structure  104  including an array of DRAM cells. That is, second semiconductor structure  104  can be a DRAM memory device. DRAM requires periodic refreshing of the memory cells. The memory controller for refreshing the DRAM can be embedded as another example of the peripheral circuits described above. In some embodiments, each DRAM cell includes a capacitor for storing a bit of data as a positive or negative electrical charge as well as one or more transistors that control access to it. In one example, each DRAM cell is a one-transistor, one-capacitor (1T1C) cell. 
     As shown in  FIG. 1A , semiconductor device  100  further includes a bonding interface  106  vertically between first semiconductor structure  102  and second semiconductor structure  104 . As described below in detail, first and second semiconductor structures  102  and  104  can be fabricated separately (and in parallel in some embodiments) such that the thermal budget of fabricating one of first and second semiconductor structures  102  and  104  does not limit the processes of fabricating another one of first and second semiconductor structures  102  and  104 . Moreover, a large number of interconnects (e.g., bonding contacts) can be formed through bonding interface  106  to make direct, short-distance (e.g., micron-level) electrical connections between first semiconductor structure  102  and second semiconductor structure  104 , as opposed to the long-distance (e.g., millimeter or centimeter-level) chip-to-chip data bus on the circuit board, such as printed circuit board (PCB), thereby eliminating chip interface delay and achieving high-speed I/O throughput with reduced power consumption. Data transfer between the DRAM in second semiconductor structure  104  and the programmable logic device in first semiconductor structure  102  as well as between the DRAM in second semiconductor structure  104  and the SRAM in first semiconductor structure  102  can be performed through the interconnects (e.g., bonding contacts) across bonding interface  106 . By vertically integrating first and second semiconductor structures  102  and  104 , the chip size can be reduced, and the memory cell density can be increased. Furthermore, as a “unified” chip, by integrating multiple discrete chips (e.g., programmable logic device and various memories) into a single bonded chip (e.g., semiconductor device  100 ), faster system speed and smaller PCB size can be achieved as well. 
     It is understood that the relative positions of stacked first and second semiconductor structures  102  and  104  are not limited.  FIG. 1B  illustrates a schematic view of a cross-section of another exemplary semiconductor device  101 , according to some embodiments. Being different from semiconductor device  100  in  FIG. 1A  in which second semiconductor structure  104  including the array of DRAM cells is above first semiconductor structure  102  including the programmable logic device and the array of SRAM cells, in semiconductor device  101  in  FIG. 1B , first semiconductor structure  102  including the programmable logic device and the array of SRAM cells is above second semiconductor structure  104  including the array of DRAM cells. Nevertheless, bonding interface  106  is formed vertically between first and second semiconductor structures  102  and  104  in semiconductor device  101 , and first and second semiconductor structures  102  and  104  are joined vertically through bonding (e.g., hybrid bonding) according to some embodiments. Data transfer between the DRAM in second semiconductor structure  104  and the programmable logic device in first semiconductor structure  102  as well as the data transfer between the DRAM in second semiconductor structure  104  and the SRAM in first semiconductor structure  102  can be performed through the interconnects (e.g., bonding contacts) across bonding interface  106 . 
       FIG. 2A  illustrates a schematic plan view of an exemplary semiconductor structure  200  having a programmable logic device and SRAM, according to some embodiments. Semiconductor structure  200  may be one example of first semiconductor structure  102 . Semiconductor structure  200  can include a programmable logic device (PLD)  202  on the same substrate as SRAM  204  and fabricated using the same logic process as SRAM  204 . PLD  202  can include one or more of PLAs, PALs, GALs, CPLDs, FPGAs, to name a few. PLD  202  includes one or more of FPGA cores, each of which includes a plurality of programmable logic blocks  212  arranged in an array, according to some embodiments. For example, each programmable logic blocks  212  may include one or more LUTs. One or more programmable logic blocks  212  can be configured to perform an independent processing task. In some embodiments, PLD  202  further includes I/O blocks  214 . 
     SRAM  204  can be disposed outside of PLD  202 . For example,  FIG. 2A  shows an exemplary layout of SRAM  204  in which the array of SRAM cells are distributed in a plurality of separate regions in semiconductor structure  200 , which is outside of PLD  202 . That is, the memory module formed by SRAM  204  can be divided into smaller memory regions, distributing outside of PLD  202  in semiconductor structure  200 . In one example, the distribution of the memory regions may be based on the design of the bonding contacts, e.g., occupying the areas without bonding contacts. In another example, the distribution of the memory regions may be random. As a result, more internal memory (e.g., using on-die SRAM) can be arranged surrounding PLD  202  without occupying additional chip area. 
       FIG. 2B  illustrates a schematic plan view of an exemplary semiconductor structure  201  having DRAM and peripheral circuits, according to some embodiments. Semiconductor structure  201  may be one example of second semiconductor structure  104 . Semiconductor structure  201  can include DRAM  206  on the same substrate as the peripheral circuits of DRAM  206 . Semiconductor structure  201  can include all the peripheral circuits for controlling and sensing DRAM  206 , including, for example, row decoders  208 , column decoders  210 , and any other suitable devices.  FIG. 2B  shows an exemplary layout of the peripheral circuit (e.g., row decoders  208 , column decoders  210 ) and DRAM  206  in which the peripheral circuit (e.g., row decoders  208 , column decoders  210 ) and DRAM  206  are formed in different regions on the same plane. For example, the peripheral circuit (e.g., row decoders  208 , column decoders  210 ) may be formed outside of DRAM  206 . 
     It is understood that the layouts of semiconductor structures  200  and  201  are not limited to the exemplary layouts in  FIGS. 2A and 2B . In some embodiments, part of the peripheral circuits of DRAM  206  (e.g., one or more of row decoders  208 , column decoders  210 , and any other suitable devices) may be in semiconductor structure  201  having PLD  202  and SRAM  204 . That is, the peripheral circuits of DRAM  206  may be distributed on both semiconductor structures  200  and  201 , according to some other embodiments. In some embodiments, at least some of the peripheral circuits (e.g., row decoders  208 , column decoders  210 ) and DRAM  206  (e.g., the array of DRAM cells) are stacked one over another, i.e., in different planes. For example, DRAM  206  (e.g., the array of DRAM cells) may be formed above or below the peripheral circuits to further reduce the chip size. Similarly, in some embodiments, at least part of SRAM  204  (e.g., the array of SRAM cells) and PLD  202  are stacked one over another, i.e., in different planes. For example, SRAM  204  (e.g., the array of SRAM cells) may be formed above or below PLD  202  to further reduce the chip size. 
       FIG. 3A  illustrates a schematic plan view of an exemplary semiconductor structure  300  having a programmable logic device, SRAM, and peripheral circuits, according to some embodiments. Semiconductor structure  300  may be one example of first semiconductor structure  102 . Semiconductor structure  300  can include PLD  202  on the same substrate as SRAM  204  and the peripheral circuits (e.g., row decoders  208 , column decoders  210 ) and fabricated using the same logic process as SRAM  204  and the peripheral circuits. PLD  202  can include one or more of PLAs, PALs, GALs, CPLDs, FPGAs, to name a few. PLD  202  includes one or more of FPGA cores, each of which includes programmable logic blocks  212  arranged in an array, according to some embodiments. For example, each programmable logic blocks  212  may include one or more LUTs. In some embodiments, PLD  202  further includes I/O blocks  214 . 
     Both SRAM  204  and the peripheral circuits (e.g., row decoders  208 , column decoders  210 ) can be disposed outside of PLD  202 . For example,  FIG. 3A  shows an exemplary layout of SRAM  204  in which the array of SRAM cells are distributed in a plurality of separate regions in semiconductor structure  300 , which is outside of PLD  202 . Semiconductor structure  300  can include all the peripheral circuits for controlling and sensing DRAM  206 , including, for example, row decoders  208 , column decoders  210 , and any other suitable devices.  FIG. 3A  shows an exemplary layout of the peripheral circuits (e.g., row decoders  208 , column decoders  210 ) in which the peripheral circuits (e.g., row decoders  208 , column decoders  210 ) and SRAM  204  are formed in different regions on the same plane outside of PLD  202 . It is understood that in some embodiments, at least some of the peripheral circuits (e.g., row decoders  208 , column decoders  210 ), SRAM  204  (e.g., the array of SRAM cells), and PLD  202  are stacked one over another, i.e., in different planes. For example, SRAM  204  (e.g., the array of SRAM cells) may be formed above or below the peripheral circuits to further reduce the chip size. 
       FIG. 3B  illustrates a schematic plan view of an exemplary semiconductor structure  301  having DRAM, according to some embodiments. Semiconductor structure  301  may be one example of second semiconductor structure  104 . By moving all the peripheral circuits (e.g., row decoders  208 , column decoders  210 ) away from semiconductor structure  301  (e.g., to semiconductor structure  300 ), the size of DRAM  206  (e.g., the number of DRAM cells) in semiconductor structure  301  can be increased. 
       FIG. 4A  illustrates a cross-section of an exemplary semiconductor device  400 , according to some embodiments. As one example of semiconductor device  100  described above with respect to  FIG. 1A , semiconductor device  400  is a bonded chip including a first semiconductor structure  402  and a second semiconductor structure  404  stacked over first semiconductor structure  402 . First and second semiconductor structures  402  and  404  are joined at a bonding interface  406  therebetween, according to some embodiments. As shown in  FIG. 4A , first semiconductor structure  402  can include a substrate  408 , which can include silicon (e.g., single crystalline silicon, c-Si), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), or any other suitable materials. 
     First semiconductor structure  402  of semiconductor device  400  can include a device layer  410  above substrate  408 . It is noted that x- and y-axes are added in  FIG. 4A  to further illustrate the spatial relationship of the components in semiconductor device  400 . Substrate  408  includes two lateral surfaces (e.g., a top surface and a bottom surface) extending laterally in the x-direction (the lateral direction or width direction). As used herein, whether one component (e.g., a layer or a device) is “on,” “above,” or “below” another component (e.g., a layer or a device) of a semiconductor device (e.g., semiconductor device  400 ) is determined relative to the substrate of the semiconductor device (e.g., substrate  408 ) in the y-direction (the vertical direction or thickness direction) when the substrate is positioned in the lowest plane of the semiconductor device in the y-direction. The same notion for describing the spatial relationship is applied throughout the present disclosure. 
     In some embodiments, device layer  410  includes a programmable logic device  412  on substrate  408  and an array of SRAM cells  414  on substrate  408  and outside of programmable logic device  412 . In some embodiments, device layer  410  further includes a peripheral circuit  416  on substrate  408  and outside of programmable logic device  412 . For example, peripheral circuit  416  may be part or the entirety of the peripheral circuits for controlling and sensing the DRAM of semiconductor device  400  as described below in detail. In some embodiments, programmable logic device  412  includes a plurality of transistors  418  forming an array of programmable logic blocks (any I/O blocks in some cases) as described above in detail. In some embodiments, transistors  418  also form array of SRAM cells  414  used as, for example, cache and/or data buffer of semiconductor device  400 . For example, array of SRAM cells  414  may function as the internal instruction memory and/or data memory of programmable logic device  412 . Array of SRAM cells  414  can be distributed in a plurality of separate regions in first semiconductor structure  402 . In some embodiments, transistors  418  further form peripheral circuit  416 , i.e., any suitable digital, analog, and/or mixed-signal control and sensing circuits used for facilitating the operation of the DRAM including, but not limited to, an input/output buffer, a decoder (e.g., a row decoder and a column decoder), and a sense amplifier. 
     Transistors  418  can be formed “on” substrate  408 , in which the entirety or part of transistors  418  are formed in substrate  408  (e.g., below the top surface of substrate  408 ) and/or directly on substrate  408 . Isolation regions (e.g., shallow trench isolations (STIs)) and doped regions (e.g., source regions and drain regions of transistors  418 ) can be formed in substrate  408  as well. Transistors  418  are high-speed with advanced logic processes (e.g., technology nodes of 90 nm, 65 nm, 45 nm, 32 nm, 28 nm, 20 nm, 16 nm, 14 nm, 10 nm, 7 nm, 5 nm, 3 nm, 2 nm, etc.), according to some embodiments. 
     In some embodiments, first semiconductor structure  402  of semiconductor device  400  further includes an interconnect layer  420  above device layer  410  to transfer electrical signals to and from programmable logic device  412  and array of SRAM cells  414  (and peripheral circuit  416  if any). Interconnect layer  420  can include a plurality of interconnects (also referred to herein as “contacts”), including lateral interconnect lines and vertical interconnect access (via) contacts. As used herein, the term “interconnects” can broadly include any suitable types of interconnects, such as middle-end-of-line (MEOL) interconnects and back-end-of-line (BEOL) interconnects. Interconnect layer  420  can further include one or more interlayer dielectric (ILD) layers (also known as “intermetal dielectric (IMD) layers”) in which the interconnect lines and via contacts can form. That is, interconnect layer  420  can include interconnect lines and via contacts in multiple ILD layers. The interconnect lines and via contacts in interconnect layer  420  can include conductive materials including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicides, or any combination thereof. The ILD layers in interconnect layer  420  can include dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low dielectric constant (low-k) dielectrics, or any combination thereof. In some embodiments, the devices in device layer  410  are electrically connected to one another through the interconnects in interconnect layer  420 . For example, array of SRAM cells  414  may be electrically connected to programmable logic device  412  through interconnect layer  420 . 
     As shown in  FIG. 4A , first semiconductor structure  402  of semiconductor device  400  can further include a bonding layer  422  at bonding interface  406  and above interconnect layer  420  and device layer  410  (including programmable logic device  412  and array of SRAM cells  414 ). Bonding layer  422  can include a plurality of bonding contacts  424  and dielectrics electrically isolating bonding contacts  424 . Bonding contacts  424  can include conductive materials including, but not limited to, W, Co, Cu, Al, silicides, or any combination thereof. The remaining area of bonding layer  422  can be formed with dielectrics including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. Bonding contacts  424  and surrounding dielectrics in bonding layer  422  can be used for hybrid bonding. 
     Similarly, as shown in  FIG. 4A , second semiconductor structure  404  of semiconductor device  400  can also include a bonding layer  426  at bonding interface  406  and above bonding layer  422  of first semiconductor structure  402 . Bonding layer  426  can include a plurality of bonding contacts  428  and dielectrics electrically isolating bonding contacts  428 . Bonding contacts  428  can include conductive materials including, but not limited to, W, Co, Cu, Al, silicides, or any combination thereof. The remaining area of bonding layer  426  can be formed with dielectrics including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. Bonding contacts  428  and surrounding dielectrics in bonding layer  426  can be used for hybrid bonding. Bonding contacts  428  are in contact with bonding contacts  424  at bonding interface  406 , according to some embodiments. 
     As described above, second semiconductor structure  404  can be bonded on top of first semiconductor structure  402  in a face-to-face manner at bonding interface  406 . In some embodiments, bonding interface  406  is disposed between bonding layers  422  and  426  as a result of hybrid bonding (also known as “metal/dielectric hybrid bonding”), which is a direct bonding technology (e.g., forming bonding between surfaces without using intermediate layers, such as solder or adhesives) and can obtain metal-metal bonding and dielectric-dielectric bonding simultaneously. In some embodiments, bonding interface  406  is the place at which bonding layers  422  and  426  are met and bonded. In practice, bonding interface  406  can be a layer with a certain thickness that includes the top surface of bonding layer  422  of first semiconductor structure  402  and the bottom surface of bonding layer  426  of second semiconductor structure  404 . 
     In some embodiments, second semiconductor structure  404  of semiconductor device  400  further includes an interconnect layer  430  above bonding layer  426  to transfer electrical signals. Interconnect layer  430  can include a plurality of interconnects, such as MEOL interconnects and BEOL interconnects. In some embodiments, the interconnects in interconnect layer  430  also include local interconnects, such as bit line contacts and word line contacts. Interconnect layer  430  can further include one or more ILD layers in which the interconnect lines and via contacts can form. The interconnect lines and via contacts in interconnect layer  430  can include conductive materials including, but not limited to, W, Co, Cu, Al, silicides, or any combination thereof. The ILD layers in interconnect layer  430  can include dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. 
     Second semiconductor structure  404  of semiconductor device  400  can further include a device layer  432  above interconnect layer  430  and bonding layer  426 . In some embodiments, device layer  432  includes an array of DRAM cells  450  above interconnect layer  430  and bonding layer  426 . In some embodiments, each DRAM cell  450  includes a DRAM selection transistor  436  and a capacitor  438 . DRAM cell  450  can be a 1T1C cell consisting of one transistor and one capacitor. It is understood that DRAM cell  450  may be of any suitable configurations, such as 2T1C cell, 3T1C cell, etc. In some embodiments, DRAM selection transistors  436  are formed “on” a semiconductor layer  434 , in which the entirety or part of DRAM selection transistors  436  are formed in semiconductor layer  434  (e.g., below the top surface of semiconductor layer  434 ) and/or directly on semiconductor layer  434 . Isolation regions (e.g., STIs) and doped regions (e.g., source regions and drain regions of DRAM selection transistors  436 ) can be formed in semiconductor layer  434  as well. In some embodiments, capacitors  438  are disposed below DRAM selection transistors  436 . Each capacitor  438  includes two electrodes, one of which is electrically connected to one node of respective DRAM selection transistor  436 , according to some embodiments. Another node of each DRAM selection transistor  436  is electrically connected to a bit line  440  of DRAM, according to some embodiments. Another electrode of each capacitor  438  can be electrically connected to a common plate  442 , e.g., a common ground. It is understood that the structure and configuration of DRAM cell  450  are not limited to the example in  FIG. 4A  and may include any suitable structure and configuration. For example, capacitor  438  may be a planar capacitor, a stack capacitor, a multi-fins capacitor, a cylinder capacitor, a trench capacitor, or a substrate-plate capacitor. 
     In some embodiments, second semiconductor structure  404  further includes semiconductor layer  434  disposed above device layer  432 . Semiconductor layer  434  can be above and in contact with array of DRAM cells  450 . Semiconductor layer  434  can be a thinned substrate on which DRAM selection transistors  436  are formed. In some embodiments, semiconductor layer  434  includes single-crystal silicon. In some embodiments, semiconductor layer  434  can include polysilicon, amorphous silicon, SiGe, GaAs, Ge, or any other suitable materials. Semiconductor layer  434  can also include isolation regions and doped regions (e.g., as the sources and drains of DRAM selection transistors  436 ). 
     As shown in  FIG. 4A , second semiconductor structure  404  of semiconductor device  400  can further include a pad-out interconnect layer  444  above semiconductor layer  434 . Pad-out interconnect layer  444  can include interconnects, e.g., contact pads  446 , in one or more ILD layers. Pad-out interconnect layer  444  and interconnect layer  430  can be formed at opposite sides of semiconductor layer  434 . In some embodiments, the interconnects in pad-out interconnect layer  444  can transfer electrical signals between semiconductor device  400  and outside circuits, e.g., for pad-out purposes. 
     In some embodiments, second semiconductor structure  404  further includes one or more contacts  448  extending through semiconductor layer  434  to electrically connect pad-out interconnect layer  444  and interconnect layers  430  and  420 . As a result, programmable logic device  412  and array of SRAM cells  414  (and peripheral circuit  416  if any) can be electrically connected to array of DRAM cells  450  through interconnect layers  430  and  420  as well as bonding contacts  428  and  424 . Moreover, programmable logic device  412 , array of SRAM cells  414 , and array of DRAM cells  450  can be electrically connected to outside circuits through contacts  448  and pad-out interconnect layer  444 . 
       FIG. 4B  illustrates a cross-section of another exemplary semiconductor device  401 , according to some embodiments. As one example of semiconductor device  101  described above with respect to  FIG. 1B , semiconductor device  401  is a bonded chip including a second semiconductor structure  403  and a first semiconductor structure  405  stacked over second semiconductor structure  403 . Similar to semiconductor device  400  described above in  FIG. 4A , semiconductor device  401  represents an example of a bonded chip in which first semiconductor structure  405  including a programmable logic device and SRAM and second semiconductor structure  403  including DRAM are formed separately and bonded in a face-to-face manner at a bonding interface  407 . Different from semiconductor device  400  described above in  FIG. 4A  in which first semiconductor structure  402  including the programmable logic device and SRAM is below second semiconductor structure  404  including the DRAM, semiconductor device  401  in  FIG. 4B  includes first semiconductor structure  405  including the programmable logic device and SRAM disposed above second semiconductor structure  403  including the DRAM. It is understood that the details of similar structures (e.g., materials, fabrication process, functions, etc.) in both semiconductor devices  400  and  401  may not be repeated below. 
     Second semiconductor structure  403  of semiconductor device  401  can include a substrate  409  and a device layer  411  above substrate  409 . Device layer  411  can include an array of DRAM cells  449  on substrate  409 . In some embodiments, each DRAM cell  449  includes a DRAM selection transistor  413  and a capacitor  415 . DRAM cell  449  can be a 1T1C cell consisting of one transistor and one capacitor. It is understood that DRAM cell  449  may be of any suitable configuration, such as 2T1C cell, 3T1C cell, etc. In some embodiments, DRAM selection transistors  413  are formed “on” substrate  409 , in which the entirety or part of DRAM selection transistors  413  are formed in substrate  409  and/or directly on substrate  409 . In some embodiments, capacitors  415  are disposed above DRAM selection transistors  413 . Each capacitor  415  includes two electrodes, one of which is electrically connected to one node of respective DRAM selection transistor  413 , according to some embodiments. Another node of each DRAM selection transistor  413  is electrically connected to a bit line  417  of DRAM, according to some embodiments. Another electrode of each capacitor  415  can be electrically connected to a common plate  419 , e.g., a common ground. It is understood that the structure and configuration of DRAM cell  449  are not limited to the example in  FIG. 4B  and may include any suitable structure and configuration. 
     In some embodiments, second semiconductor structure  403  of semiconductor device  401  also includes an interconnect layer  421  above device layer  411  to transfer electrical signals to and from array of DRAM cells  449 . Interconnect layer  421  can include a plurality of interconnects, including interconnect lines and via contacts. In some embodiments, the interconnects in interconnect layer  421  also include local interconnects, such as bit line contacts and word line contacts. In some embodiments, second semiconductor structure  403  of semiconductor device  401  further includes a bonding layer  423  at bonding interface  407  and above interconnect layer  421  and device layer  411 . Bonding layer  423  can include a plurality of bonding contacts  425  and dielectrics surrounding and electrically isolating bonding contacts  425 . 
     As shown in  FIG. 4B , first semiconductor structure  405  of semiconductor device  401  includes another bonding layer  451  at bonding interface  407  and above bonding layer  423 . Bonding layer  451  can include a plurality of bonding contacts  427  and dielectrics surrounding and electrically isolating bonding contacts  427 . Bonding contacts  427  are in contact with bonding contacts  425  at bonding interface  407 , according to some embodiments. In some embodiments, first semiconductor structure  405  of semiconductor device  401  also includes an interconnect layer  429  above bonding layer  451  to transfer electrical signals. Interconnect layer  429  can include a plurality of interconnects, including interconnect lines and via contacts. 
     First semiconductor structure  405  of semiconductor device  401  can further include a device layer  431  above interconnect layer  429  and bonding layer  451 . In some embodiments, device layer  431  includes a programmable logic device  435  above interconnect layer  429  and bonding layer  451 , and an array of SRAM cells  437  above interconnect layer  429  and bonding layer  451  and outside of programmable logic device  435 . In some embodiments, device layer  431  further includes a peripheral circuit  439  above interconnect layer  429  and bonding layer  451  and outside of programmable logic device  435 . For example, peripheral circuit  439  may be part or the entirety of the peripheral circuits for controlling and sensing array of DRAM cells  449 . In some embodiments, the devices in device layer  431  are electrically connected to one another through the interconnects in interconnect layer  429 . For example, array of SRAM cells  437  may be electrically connected to programmable logic device  435  through interconnect layer  429 . 
     In some embodiments, programmable logic device  435  includes a plurality of transistors  441  forming an array of programmable logic blocks (any I/O blocks in some cases) as described above in detail. Transistors  441  can be formed “on” a semiconductor layer  433 , in which the entirety or part of transistors  441  are formed in semiconductor layer  433  and/or directly on semiconductor layer  433 . Isolation regions (e.g., STIs) and doped regions (e.g., source regions and drain regions of transistors  441 ) can be formed in semiconductor layer  433  as well. Transistors  441  can form array of SRAM cells  437  (and peripheral circuit  439  if any). Transistors  441  are high-speed with advanced logic processes (e.g., technology nodes of 90 nm, 65 nm, 45 nm, 32 nm, 28 nm, 20 nm, 16 nm, 14 nm, 10 nm, 7 nm, 5 nm, 3 nm, 2 nm, etc.), according to some embodiments. 
     In some embodiments, first semiconductor structure  405  further includes semiconductor layer  433  disposed above device layer  431 . Semiconductor layer  433  can be above and in contact with programmable logic device  435  and array of SRAM cells  437 . Semiconductor layer  433  can be a thinned substrate on which transistors  441  are formed. In some embodiments, semiconductor layer  433  includes single-crystal silicon. In some embodiments, semiconductor layer  433  can include polysilicon, amorphous silicon, SiGe, GaAs, Ge, or any other suitable materials. Semiconductor layer  433  can also include isolation regions and doped regions. 
     As shown in  FIG. 4B , first semiconductor structure  405  of semiconductor device  401  can further include a pad-out interconnect layer  443  above semiconductor layer  433 . Pad-out interconnect layer  443  can include interconnects, e.g., contact pads  445 , in one or more ILD layers. In some embodiments, the interconnects in pad-out interconnect layer  443  can transfer electrical signals between semiconductor device  401  and outside circuits, e.g., for pad-out purposes. In some embodiments, first semiconductor structure  405  further includes one or more contacts  447  extending through semiconductor layer  433  to electrically connect pad-out interconnect layer  443  and interconnect layers  429  and  421 . As a result, programmable logic device  435  and array of SRAM cells  437  (and peripheral circuit  439  if any) can also be electrically connected to array of DRAM cells  449  through interconnect layers  429  and  421  as well as bonding contacts  427  and  425 . Moreover, programmable logic device  435 , array of SRAM cells  437 , and array of DRAM cells  449  can be electrically connected to outside circuits through contacts  447  and pad-out interconnect layer  443 . 
       FIG. 5A  illustrates a cross-section of still another exemplary semiconductor device  500 , according to some embodiments. Similar to semiconductor device  400  described above in  FIG. 4A , semiconductor device  500  represents an example of a bonded chip including a first semiconductor structure  502  having a programmable logic device  512  and an array of SRAM cells  514 , and a second semiconductor structure  504  having an array of DRAM cells  536  above first semiconductor structure  502 . Different from semiconductor device  400  described above in  FIG. 4A  in which peripheral circuit  416  is in first semiconductor structure  402 , but not in second semiconductor structure  404 , peripheral circuits  538  are formed in second semiconductor structure  504  in which array of DRAM cells  536  are formed. Similar to semiconductor device  400  described above in  FIG. 4A , first and second semiconductor structures  502  and  504  of semiconductor device  500  are bonded in a face-to-face manner at a bonding interface  506 , as shown in  FIG. 5A . It is understood that the details of similar structures (e.g., materials, fabrication process, functions, etc.) in both semiconductor devices  400  and  500  may not be repeated below. 
     First semiconductor structure  502  of semiconductor device  500  can include a device layer  510  above a substrate  508 . In some embodiments, device layer  510  includes programmable logic device  512  on substrate  508 , and array of SRAM cells  514  on substrate  508  and outside of programmable logic device  512 . In some embodiments, programmable logic device  512  includes a plurality of transistors  518  forming an array of programmable logic blocks (any I/O blocks in some cases) as described above in detail. In some embodiments, transistors  518  also form array of SRAM cells  514  used as, for example, cache and/or data buffer of semiconductor device  500 . 
     In some embodiments, first semiconductor structure  502  of semiconductor device  500  also includes an interconnect layer  520  above device layer  510  to transfer electrical signals to and from programmable logic device  512  and array of SRAM cells  514 . Interconnect layer  520  can include a plurality of interconnects, including interconnect lines and via contacts. In some embodiments, first semiconductor structure  502  of semiconductor device  500  further includes a bonding layer  522  at bonding interface  506  and above interconnect layer  520  and device layer  510  (including programmable logic device  512  and array of SRAM cells  514 ). Bonding layer  522  can include a plurality of bonding contacts  524  and dielectrics surrounding and electrically isolating bonding contacts  524 . 
     Similarly, as shown in  FIG. 5A , second semiconductor structure  504  of semiconductor device  500  can also include a bonding layer  526  at bonding interface  506  and above bonding layer  522  of first semiconductor structure  502 . Bonding layer  526  can include a plurality of bonding contacts  528  and dielectrics electrically isolating bonding contacts  528 . Bonding contacts  528  are in contact with bonding contacts  524  at bonding interface  506 , according to some embodiments. In some embodiments, second semiconductor structure  504  of semiconductor device  500  also includes an interconnect layer  530  above bonding layer  526  to transfer electrical signals. Interconnect layer  530  can include a plurality of interconnects, including interconnect lines and via contacts. 
     Second semiconductor structure  504  of semiconductor device  500  can further include a device layer  532  above interconnect layer  530  and bonding layer  526 . In some embodiments, device layer  532  includes array of DRAM cells  536  above interconnect layer  530  and bonding layer  526 . In some embodiments, each DRAM cell  536  includes a DRAM selection transistor  540  and a capacitor  542 . DRAM cell  536  can be a 1T1C cell consisting of one transistor and one capacitor. It is understood that DRAM cell  536  may be of any suitable configurations, such as 2T1C cell, 3T1C cell, etc. In some embodiments, DRAM selection transistors  540  are formed “on” a semiconductor layer  534 , in which the entirety or part of DRAM selection transistors  540  are formed in semiconductor layer  534  (e.g., below the top surface of semiconductor layer  534 ) and/or directly on semiconductor layer  534 . Isolation regions (e.g., STIs) and doped regions (e.g., source regions and drain regions of DRAM selection transistors  540 ) can be formed in semiconductor layer  534  as well. In some embodiments, capacitors  542  are disposed below DRAM selection transistors  540 . Each capacitor  542  includes two electrodes, one of which is electrically connected to one node of respective DRAM selection transistor  540 , according to some embodiments. Another node of each DRAM selection transistor  540  is electrically connected to a bit line  544  of DRAM, according to some embodiments. Another electrode of each capacitor  542  can be electrically connected to a common plate  546 , e.g., a common ground. It is understood that the structure and configuration of DRAM cell  536  are not limited to the example in  FIG. 5A  and may include any suitable structure and configuration. 
     In some embodiments, device layer  532  further includes peripheral circuits  538  above interconnect layer  530  and bonding layer  526  and outside of array of DRAM cells  536 . For example, peripheral circuits  538  may be part or the entirety of the peripheral circuits for controlling and sensing array of DRAM cells  536 . In some embodiments, peripheral circuits  538  include a plurality of transistors  548  forming any suitable digital, analog, and/or mixed-signal control and sensing circuits used for facilitating the operation of array of DRAM cells  536  including, but not limited to, an input/output buffer, a decoder (e.g., a row decoder and a column decoder), and a sense amplifier. Peripheral circuits  538  and array of DRAM cells  536  can be electrically connected through the interconnects of interconnect layer  530 . 
     In some embodiments, second semiconductor structure  504  further includes semiconductor layer  534  disposed above device layer  532 . Semiconductor layer  534  can be above and in contact with array of DRAM cells  536 . Semiconductor layer  534  can be a thinned substrate on which transistors  548  and DRAM selection transistors  540  are formed. In some embodiments, semiconductor layer  534  includes single-crystal silicon. In some embodiments, semiconductor layer  534  can include polysilicon, amorphous silicon, SiGe, GaAs, Ge, or any other suitable materials. Semiconductor layer  534  can also include isolation regions and doped regions. 
     As shown in  FIG. 5A , second semiconductor structure  504  of semiconductor device  500  can further include a pad-out interconnect layer  550  above semiconductor layer  534 . Pad-out interconnect layer  550  includes interconnects, e.g., contact pads  552 , in one or more ILD layers. In some embodiments, the interconnects in pad-out interconnect layer  550  can transfer electrical signals between semiconductor device  500  and outside circuits, e.g., for pad-out purposes. In some embodiments, second semiconductor structure  504  further includes one or more contacts  554  extending through semiconductor layer  534  to electrically connect pad-out interconnect layer  550  and interconnect layers  530  and  520 . As a result, programmable logic device  512  and array of SRAM cells  514  can be electrically connected to array of DRAM cells  536  through interconnect layers  530  and  520  as well as bonding contacts  528  and  524 . Moreover, programmable logic device  512 , array of SRAM cells  514 , and array of DRAM cells  536  can be electrically connected to outside circuits through contacts  554  and pad-out interconnect layer  550 . 
       FIG. 5B  illustrates a cross-section of yet another exemplary semiconductor device  501 , according to some embodiments. As one example of semiconductor device  101  described above with respect to  FIG. 1B , semiconductor device  501  is a bonded chip including a second semiconductor structure  503  and a first semiconductor structure  505  stacked over second semiconductor structure  503 . Similar to semiconductor device  500  described above in  FIG. 5A , semiconductor device  501  represents an example of a bonded chip in which first semiconductor structure  505  including a programmable logic device and SRAM and second semiconductor structure  503  including peripheral circuits and DRAM are formed separately and bonded in a face-to-face manner at a bonding interface  507 . Different from semiconductor device  500  described above in  FIG. 5A  in which first semiconductor structure  502  including the programmable logic device and SRAM is below second semiconductor structure  504  including the peripheral circuits and DRAM, semiconductor device  501  in  FIG. 5B  includes first semiconductor structure  505  including the programmable logic device and SRAM disposed above second semiconductor structure  503  including the peripheral circuits and DRAM. It is understood that the details of similar structures (e.g., materials, fabrication process, functions, etc.) in both semiconductor devices  500  and  501  may not be repeated below. 
     Second semiconductor structure  503  of semiconductor device  501  can include a substrate  509  and a device layer  511  above substrate  509 . Device layer  511  can include an array of DRAM cells  513  on substrate  509 . In some embodiments, each DRAM cell  513  includes a DRAM selection transistor  517  and a capacitor  519 . DRAM cell  513  can be a 1T1C cell consisting of one transistor and one capacitor. It is understood that DRAM cell  513  may be of any suitable configuration, such as 2T1C cell, 3T1C cell, etc. In some embodiments, DRAM selection transistors  517  are formed “on” substrate  509 , in which the entirety or part of DRAM selection transistors  517  are formed in substrate  509  and/or directly on substrate  509 . In some embodiments, capacitors  519  are disposed above DRAM selection transistors  517 . Each capacitor  519  includes two electrodes, one of which is electrically connected to one node of respective DRAM selection transistor  517 , according to some embodiments. Another node of each DRAM selection transistor  517  is electrically connected to a bit line  521  of DRAM, according to some embodiments. Another electrode of each capacitor  519  can be electrically connected to a common plate  523 , e.g., a common ground. It is understood that the structure and configuration of DRAM cell  513  are not limited to the example in  FIG. 5B  and may include any suitable structure and configuration. 
     In some embodiments, device layer  511  further includes peripheral circuits  515  on substrate  509  and outside of array of DRAM cells  513 . For example, peripheral circuits  515  may be part or the entirety of the peripheral circuits for controlling and sensing array of DRAM cells  513 . In some embodiments, peripheral circuits  515  include a plurality of transistors  525  forming any suitable digital, analog, and/or mixed-signal control and sensing circuits used for facilitating the operation of array of DRAM cells  513  including, but not limited to, an input/output buffer, a decoder (e.g., a row decoder and a column decoder), and a sense amplifier. 
     In some embodiments, second semiconductor structure  503  of semiconductor device  501  also includes an interconnect layer  527  above device layer  511  to transfer electrical signals to and from array of DRAM cells  513 . Interconnect layer  527  can include a plurality of interconnects, including interconnect lines and via contacts. In some embodiments, the interconnects in interconnect layer  527  also include local interconnects, such as bit line contacts and word line contacts. Peripheral circuits  515  and array of DRAM cells  513  can be electrically connected through the interconnects of interconnect layer  527 . In some embodiments, second semiconductor structure  503  of semiconductor device  501  further includes a bonding layer  529  at bonding interface  507  and above interconnect layer  527  and device layer  511 . Bonding layer  529  can include a plurality of bonding contacts  531  and dielectrics surrounding and electrically isolating bonding contacts  531 . 
     As shown in  FIG. 5B , first semiconductor structure  505  of semiconductor device  501  includes another bonding layer  533  at bonding interface  507  and above bonding layer  529 . Bonding layer  533  can include a plurality of bonding contacts  535  and dielectrics surrounding and electrically isolating bonding contacts  535 . Bonding contacts  535  are in contact with bonding contacts  531  at bonding interface  507 , according to some embodiments. In some embodiments, first semiconductor structure  505  of semiconductor device  501  also includes an interconnect layer  537  above bonding layer  533  to transfer electrical signals. Interconnect layer  537  can include a plurality of interconnects, including interconnect lines and via contacts. 
     First semiconductor structure  505  of semiconductor device  501  can further include a device layer  539  above interconnect layer  537  and bonding layer  533 . In some embodiments, device layer  539  includes a programmable logic device  543  above interconnect layer  537  and bonding layer  533 , and an array of SRAM cells  545  above interconnect layer  537  and bonding layer  533  and outside of programmable logic device  543 . In some embodiments, the devices in device layer  539  are electrically connected to one another through the interconnects in interconnect layer  537 . For example, array of SRAM cells  545  may be electrically connected to programmable logic device  543  through interconnect layer  537 . 
     In some embodiments, programmable logic device  543  includes a plurality of transistors  547  forming an array of programmable logic blocks (and I/O blocks in some cases). Transistors  547  can be formed “on” a semiconductor layer  541 , in which the entirety or part of transistors  547  are formed in semiconductor layer  541  and/or directly on semiconductor layer  541 . Isolation regions (e.g., STIs) and doped regions (e.g., source regions and drain regions of transistors  547 ) can be formed in semiconductor layer  541  as well. Transistors  547  can also form array of SRAM cells  545 . Transistors  547  are high-speed with advanced logic processes (e.g., technology nodes of 90 nm, 65 nm, 45 nm, 32 nm, 28 nm, 20 nm, 16 nm, 14 nm, 10 nm, 7 nm, 5 nm, 3 nm, 2 nm, etc.), according to some embodiments. 
     In some embodiments, first semiconductor structure  505  further includes semiconductor layer  541  disposed above device layer  539 . Semiconductor layer  541  can be above and in contact with programmable logic device  543  and array of SRAM cells  545 . Semiconductor layer  541  can be a thinned substrate on which transistors  547  are formed. In some embodiments, semiconductor layer  541  includes single-crystal silicon. In some embodiments, semiconductor layer  541  can include polysilicon, amorphous silicon, SiGe, GaAs, Ge, or any other suitable materials. Semiconductor layer  541  can also include isolation regions and doped regions. 
     As shown in  FIG. 5B , first semiconductor structure  505  of semiconductor device  501  can further include a pad-out interconnect layer  549  above semiconductor layer  541 . Pad-out interconnect layer  549  includes interconnects, e.g., contact pads  551 , in one or more ILD layers. In some embodiments, the interconnects in pad-out interconnect layer  549  can transfer electrical signals between semiconductor device  501  and outside circuits, e.g., for pad-out purposes. In some embodiments, first semiconductor structure  505  further includes one or more contacts  553  extending through semiconductor layer  541  to electrically connect pad-out interconnect layer  549  and interconnect layers  537  and  527 . As a result, programmable logic device  543  and array of SRAM cells  545  can be electrically connected to array of DRAM cells  513  through interconnect layers  537  and  527  as well as bonding contacts  535  and  531 . Moreover, programmable logic device  543 , array of SRAM cells  545 , and array of DRAM cells  513  can be electrically connected to outside circuits through contacts  553  and pad-out interconnect layer  549 . 
       FIGS. 6A and 6B  illustrate a fabrication process for forming an exemplary semiconductor structure having a programmable logic device, SRAM, and peripheral circuits, according to some embodiments.  FIGS. 7A-7C  illustrate a fabrication process for forming an exemplary semiconductor structure having DRAM and peripheral circuits, according to some embodiments.  FIGS. 8A and 8B  illustrate a fabrication process for forming an exemplary semiconductor device, according to some embodiments.  FIGS. 9A-9C  illustrate a fabrication process for bonding and dicing an exemplary semiconductor structure, according to some embodiments.  FIGS. 10A-10C  illustrate a fabrication process for dicing and bonding an exemplary semiconductor structure, according to some embodiments.  FIG. 11  is a flowchart of an exemplary method  1100  for forming a semiconductor device, according to some embodiments.  FIG. 12  is a flowchart of another exemplary method  1200  for forming a semiconductor device, according to some embodiments. Examples of the semiconductor device depicted in  FIGS. 6A, 6B, 7A-7C, 8A, 8B, 9A-9C, 10A-10C, 11, and 12  include semiconductor devices  400 ,  401 ,  500 ,  501  depicted in  FIGS. 4A, 4B, 5A, and 5B , respectively.  FIGS. 6A, 6B, 7A-7C, 8A, 8B, 9A-9C, 10A-10C, 11, and 12  will be described together. It is understood that the operations shown in methods  1100  and  1200  are not exhaustive and that other operations can be performed as well before, after, or between any of the illustrated operations. Further, some of the operations may be performed simultaneously, or in a different order than shown in  FIGS. 11 and 12 . 
     As depicted in  FIGS. 6A and 6B , a first semiconductor structure including a programmable logic device, an array of SRAM cells, a peripheral circuit, and a first bonding layer including a plurality of first bonding contacts is formed. As depicted in  FIGS. 7A-7C , a second semiconductor structure including an array of DRAM cells, peripheral circuits, and a second bonding layer including a plurality of second bonding contacts is formed. As depicted in  FIGS. 8A and 8B , the first semiconductor structure and the second semiconductor structure are bonded in a face-to-face manner, such that the first bonding contacts are in contact with the second bonding contacts at a bonding interface. 
     Referring to  FIG. 11 , method  1100  starts at operation  1102 , in which a plurality of first semiconductor structures are formed on a first wafer. At least one of the first semiconductor structures includes a programmable logic device, an array of SRAM cells, and a first bonding layer including a plurality of first bonding contacts. The first wafer can be a silicon wafer. In some embodiments, to form the plurality of first semiconductor structures, the programmable logic device and the array of SRAM cells are formed on the first wafer. In some embodiments, to form the programmable logic device and the array of SRAM cells, a plurality of transistors are formed on the first wafer. In some embodiments, to form the plurality of first semiconductor structures, a peripheral circuit of the array of DRAM cells is also formed on the first wafer. 
     As illustrated in  FIG. 9A , a plurality of first semiconductor structures  906  are formed on a first wafer  902 . First wafer  902  can include a plurality of shots separated by scribing lines. Each shot of first wafer  902  includes one or more first semiconductor structures  906 , according to some embodiments.  FIGS. 6A and 6B  illustrate one example of the formation of first semiconductor structure  906 . 
     As illustrated in  FIG. 6A , a plurality of transistors  604  are formed on a silicon substrate  602  (as part of first wafer  902 , e.g., a silicon wafer). Transistors  604  can be formed by a plurality of processes including, but not limited to, photolithography, dry/wet etch, thin film deposition, thermal growth, implantation, chemical mechanical polishing (CMP), and any other suitable processes. In some embodiments, doped regions are formed in silicon substrate  602  by ion implantation and/or thermal diffusion, which function, for example, as source regions and/or drain regions of transistors  604 . In some embodiments, isolation regions (e.g., STIs) are also formed in silicon substrate  602  by wet/dry etch and thin film deposition. Transistors  604  can form a device layer  606  on silicon substrate  602 . In some embodiments, device layer  606  includes a programmable logic device  608 , an array of SRAM cells  610 , and a peripheral circuit  612 . 
     Method  1100  proceeds to operation  1104 , as illustrated in  FIG. 11 , in which a first interconnect layer is formed above the programmable logic device and the array of SRAM cells. The first interconnect layer can include a first plurality of interconnects in one or more ILD layers. As illustrated in  FIG. 6B , an interconnect layer  614  can be formed above device layer  606  including programmable logic device  608  and array of SRAM cells  610 . Interconnect layer  614  can include interconnects of MEOL and/or BEOL in a plurality of ILD layers to make electrical connections with device layer  606 . In some embodiments, interconnect layer  614  includes multiple ILD layers and interconnects therein formed in multiple processes. For example, the interconnects in interconnect layers  614  can include conductive materials deposited by one or more thin film deposition processes including, but not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), electroplating, electroless plating, or any combination thereof. Fabrication processes to form the interconnects can also include photolithography, CMP, wet/dry etch, or any other suitable processes. The ILD layers can include dielectric materials deposited by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. The ILD layers and interconnects illustrated in  FIG. 6B  can be collectively referred to as interconnect layer  614 . 
     Method  1100  proceeds to operation  1106 , as illustrated in  FIG. 11 , in which a first bonding layer is formed above the first interconnect layer. The first bonding layer can include a plurality of first bonding contacts. As illustrated in  FIG. 6B , a bonding layer  616  is formed above interconnect layer  614 . Bonding layer  616  can include a plurality of bonding contacts  618  surrounded by dielectrics. In some embodiments, a dielectric layer is deposited on the top surface of interconnect layer  614  by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. Bonding contacts  618  then can be formed through the dielectric layer and in contact with the interconnects in interconnect layer  614  by first patterning contact holes through the dielectric layer using a patterning process (e.g., photolithography and dry/wet etch of dielectric materials in the dielectric layer). The contact holes can be filled with a conductor (e.g., copper). In some embodiments, filling the contact holes includes depositing a barrier layer, an adhesion layer, and/or a seed layer before depositing the conductor. 
     Method  1100  proceeds to operation  1108 , as illustrated in  FIG. 11 , in which a plurality of second semiconductor structures are formed on a second wafer. At least one of the second semiconductor structures includes an array of DRAM cells and a second bonding layer including a plurality of second bonding contacts. The second wafer can be a silicon wafer. In some embodiments, to form the plurality of second semiconductor structures, the array of DRAM cells are formed on the second wafer. In some embodiments, to form the array of DRAM cells, a plurality of transistors are formed on the second wafer, and a plurality of capacitors are formed above and in contact with at least some of the transistors. In some embodiments, to form the plurality of second semiconductor structures, a peripheral circuit of the array of DRAM cells is also formed on the second wafer. 
     As illustrated in  FIG. 9A , a plurality of second semiconductor structures  908  are formed on a second wafer  904 . Second wafer  904  can include a plurality of shots separated by scribing lines. Each shot of second wafer  904  includes one or more second semiconductor structures  908 , according to some embodiments.  FIGS. 7A-7C  illustrate one example of the formation of second semiconductor structure  908 . 
     As illustrated in  FIG. 7A , a plurality of transistors  704  are formed on a silicon substrate  702  (as part of second wafer  904 , e.g., a silicon wafer). Transistors  704  can be formed by a plurality of processes including, but not limited to, photolithography, dry/wet etch, thin film deposition, thermal growth, implantation, CMP, and any other suitable processes. In some embodiments, doped regions are formed in silicon substrate  702  by ion implantation and/or thermal diffusion, which function, for example, as source regions and/or drain regions of transistors  704 . In some embodiments, isolation regions (e.g., STIs) are also formed in silicon substrate  702  by wet/dry etch and thin film deposition. 
     As illustrated in  FIG. 7B , a plurality of capacitors  706  are formed above and in contact with at least some of transistors  704 , i.e., the DRAM selection transistors. Each capacitor  706  can be patterned by photography to be aligned with a respective DRAM selection transistor to form a 1T1C memory cell, for example, by electrically connecting one electrode of capacitor  706  with one node of the respective DRAM selection transistor. In some embodiments, bit lines  707  and common plates  709  are formed as well for electrically connecting the DRAM selection transistors and capacitors  706 . Capacitors  706  can be formed by a plurality of processes including, but not limited to, photolithography, dry/wet etch, thin film deposition, thermal growth, implantation, CMP, and any other suitable processes. A device layer  708  including an array of DRAM cells  710  (each having a DRAM selection transistor and capacitor  706 ) and peripheral circuits  711  (having transistors  704  other than the DRAM selection transistors) is thereby formed. 
     Method  1100  proceeds to operation  1110 , as illustrated in  FIG. 11 , in which a second interconnect layer is formed above the array of DRAM cells. The second interconnect layer can include a second plurality of interconnects in one or more ILD layers. As illustrated in  FIG. 7C , an interconnect layer  714  can be formed above array of DRAM cells  710 . Interconnect layer  714  can include interconnects of MEOL and/or BEOL in a plurality of ILD layers to make electrical connections with array of DRAM cells  710  (and peripheral circuits  711  if any). In some embodiments, interconnect layer  714  includes multiple ILD layers and interconnects therein formed in multiple processes. For example, the interconnects in interconnect layers  714  can include conductive materials deposited by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof. Fabrication processes to form the interconnects can also include photolithography, CMP, wet/dry etch, or any other suitable processes. The ILD layers can include dielectric materials deposited by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. The ILD layers and interconnects illustrated in  FIG. 7C  can be collectively referred to as interconnect layer  714 . 
     Method  1100  proceeds to operation  1112 , as illustrated in  FIG. 11 , in which a second bonding layer is formed above the second interconnect layer. The second bonding layer can include a plurality of second bonding contacts. As illustrated in  FIG. 7C , a bonding layer  716  is formed above interconnect layer  714 . Bonding layer  716  can include a plurality of bonding contacts  718  surrounded by dielectrics. In some embodiments, a dielectric layer is deposited on the top surface of interconnect layer  714  by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. Bonding contacts  718  then can be formed through the dielectric layer and in contact with the interconnects in interconnect layer  714  by first patterning contact holes through the dielectric layer using a patterning process (e.g., photolithography and dry/wet etch of dielectric materials in the dielectric layer). The contact holes can be filled with a conductor (e.g., copper). In some embodiments, filling the contact holes includes depositing an adhesion (glue) layer, a barrier layer, and/or a seed layer before depositing the conductor. 
     Method  1100  proceeds to operation  1114 , as illustrated in  FIG. 11 , in which the first wafer and the second wafer are bonded in a face-to-face manner, such that the at least one of the first semiconductor structures is bonded to the at least one of the second semiconductor structures. The first bonding contacts of the first semiconductor structure are in contact with the second bonding contacts of the second semiconductor structure at a bonding interface. The bonding can be hybrid bonding. In some embodiments, the second semiconductor structure is above the first semiconductor structure after the bonding. In some embodiments, the first semiconductor structure is above the second semiconductor structure after the bonding. 
     As illustrated in  FIG. 9B , first wafer  902  and second wafer  904  are bonded in a face-to-face manner, such that at least one of first semiconductor structures  906  is bonded to at least one of second semiconductor structures  908  at a bonding interface  909 . Although first wafer  902  is above second wafer  904  after the bonding as shown in  FIG. 9B , it is understood that second wafer  904  may be above first wafer  902  after the bonding in some embodiments.  FIG. 8A  illustrates one example of the formation of bonded first and second semiconductor structures  906  and  908 . 
     As illustrated in  FIG. 8A , silicon substrate  702  and components formed thereon (e.g., device layer  712  including array of DRAM cells  710 ) are flipped upside down. Bonding layer  716  facing down is bonded with bonding layer  616  facing up, i.e., in a face-to-face manner, thereby forming a bonding interface  802  (as shown in  FIG. 8B ). In some embodiments, a treatment process, e.g., a plasma treatment, a wet treatment, and/or a thermal treatment, is applied to the bonding surfaces prior to the bonding. Although not shown in  FIG. 8A , silicon substrate  602  and components formed thereon (e.g., device layer  606  including programmable logic device  608 , array of SRAM cells  610 , and peripheral circuit  612 ) can be flipped upside down, and bonding layer  616  facing down can be bonded with bonding layer  716  facing up, i.e., in a face-to-face manner, thereby forming bonding interface  802 . After the bonding, bonding contacts  718  in bonding layer  716  and bonding contacts  618  in bonding layer  616  are aligned and in contact with one another, such that device layer  712  (e.g., array of DRAM cells  710  therein) can be electrically connected to device layer  606  (e.g., programmable logic device  608 , array of SRAM cells  610 , and peripheral circuit  612  therein). It is understood that in the bonded chip, device layer  606  (e.g., programmable logic device  608 , array of SRAM cells  610 , and peripheral circuit  612  therein) may be either above or below device layer  712  (e.g., array of DRAM cells  710  therein). Nevertheless, bonding interface  802  can be formed between device layer  606  (e.g., programmable logic device  608 , array of SRAM cells  610 , and peripheral circuit  612  therein) and device layer  712  (e.g., array of DRAM cells  710  therein) after the bonding as illustrated in  FIG. 8B . It is understood that although device layer  712  in  FIG. 8A  does not include peripheral circuits  711  (as shown in  FIG. 7C ), in some embodiments, peripheral circuits  711  may be included as part of device layer  712  in the bonded chip. It is further understood that although device layer  606  in  FIG. 8A  includes peripheral circuits  612 , in some embodiments, peripheral circuits  612  may not be included as part of device layer  606  in the bonded chip. 
     Method  1100  proceeds to operation  1116 , as illustrated in  FIG. 11 , in which the first wafer or the second wafer is thinned to form a semiconductor layer. In some embodiments, the first wafer of the first semiconductor structure, which is above the second wafer of the second semiconductor structure after the bonding, is thinned to form the semiconductor layer. In some embodiments, the second wafer of the second semiconductor structure, which is above the first wafer of the first semiconductor structure after the bonding, is thinned to form the semiconductor layer. 
     As illustrated in  FIG. 8B , the substrate at the top of the bonded chip (e.g., silicon substrate  702  as shown in  FIG. 8A ) is thinned, so that the thinned top substrate can serve as a semiconductor layer  804 , for example, a single-crystal silicon layer. Silicon substrate  702  can be thinned by processes including, but not limited to, wafer grinding, dry etch, wet etch, CMP, any other suitable processes, or any combination thereof. In one example, the thickness of the thinned substrate may be between about 1 μm and about 20 μm, such as between 1 μm and 20 μm (e.g., 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, 10 μm, 15 μm, 20 μm, any range bounded by the lower end by any of these values, or in any range defined by any two of these values), for example, using a combination of etch and CMP processes. It is understood that in some embodiments, by further applying an additional etch process, the thickness of the thinned substrate may be further reduced to below 1 μm, e.g., in the sub-micron range. It is understood that when silicon substrate  602  is the substrate at the top of the bonded chip, another semiconductor layer may be formed by thinning silicon substrate  602 . 
     Method  1100  proceeds to operation  1118 , as illustrated in  FIG. 11 , in which a pad-out interconnect layer is formed above the semiconductor layer. As illustrated in  FIG. 8B , a pad-out interconnect layer  806  is formed above semiconductor layer  804  (the thinned top substrate). Pad-out interconnect layer  806  can include interconnects, such as pad contacts  808 , formed in one or more ILD layers. Pad contacts  808  can include conductive materials including, but not limited to, W, Co, Cu, Al, doped silicon, silicides, or any combination thereof. The ILD layers can include dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. In some embodiments, after the bonding and thinning, contacts  810  are formed extending vertically through semiconductor layer  804 , for example by wet/dry etch followed by depositing conductive materials. Contacts  810  can be in contact with the interconnects in pad-out interconnect layer  806 . 
     Method  1100  proceeds to operation  1120 , as illustrated in  FIG. 11 , in which the bonded first and second wafers are diced into a plurality of dies. At least one of the dies includes the bonded first and second semiconductor structures. As illustrated in  FIG. 9C , bonded first and second wafers  902  and  904  (as shown in  FIG. 9B ) are diced into a plurality of dies  912 . At least one of dies  912  includes bonded first and second semiconductor structures  906  and  908 . In some embodiments, each shot of bonded first and second wafers  902  and  904  is cut from bonded first and second wafers  902  and  904  along the scribing lines using wafer laser dicing and/or mechanical dicing techniques, thereby becoming respective die  912 . Die  912  can include bonded first and second semiconductor structures  906  and  908 , for example, the bonded structure as shown in  FIG. 8B . 
     Instead of packaging scheme based on wafer-level bonding before dicing as described above with respect to  FIGS. 9A-9C and 11 ,  FIGS. 10A-10C and 12  illustrate another packaging scheme based on die-level bonding after dicing, according to some embodiments. Operations  1102 ,  1104 , and  1106  of method  1200  in  FIG. 12  are described above with respect to method  1100  in  FIG. 11  and thus, are not repeated. As illustrated in  FIG. 10A , a plurality of first semiconductor structures  1006  are formed on a first wafer  1002 . First wafer  1002  can include a plurality of shots separated by scribing lines. Each shot of first wafer  1002  includes one or more first semiconductor structures  1006 , according to some embodiments.  FIGS. 6A and 6B  illustrate one example of the formation of first semiconductor structure  1006 . 
     Method  1200  proceeds to operation  1202 , as illustrated in  FIG. 12 , in which the first wafer is diced into a plurality of first dies, such that at least one of the first dies includes the at least one of the first semiconductor structures. As illustrated in  FIG. 10B , first wafer  1002  (as shown in  FIG. 10A ) is diced into a plurality of dies  1010 , such that at least one die  1010  includes first semiconductor structure  1006 . In some embodiments, each shot of first wafer  1002  is cut from first wafer  1002  along the scribing lines using wafer laser dicing and/or mechanical dicing techniques, thereby becoming respective die  1010 . Die  1010  can include first semiconductor structure  1006 , for example, the structure as shown in  FIG. 6B . 
     Operations  1108 ,  1110 , and  1112  of method  1200  in  FIG. 12  are described above with respect to method  1100  in  FIG. 11  and thus, are not repeated. As illustrated in  FIG. 10A , a plurality of second semiconductor structures  1008  are formed on a second wafer  1004 . Second wafer  1004  can include a plurality of shots separated by scribing lines. Each shot of second wafer  1004  includes one or more second semiconductor structures  1008 , according to some embodiments.  FIGS. 7A-7C  illustrate one example of the formation of second semiconductor structure  1008 . 
     Method  1200  proceeds to operation  1204 , as illustrated in  FIG. 12 , in which the second wafer is diced into a plurality of second dies, such that at least one of the second dies includes the at least one of the second semiconductor structures. As illustrated in  FIG. 10B , second wafer  1004  (as shown in  FIG. 10A ) is diced into a plurality of dies  1012 , such that at least one die  1012  includes second semiconductor structure  1008 . In some embodiments, each shot of second wafer  1004  is cut from second wafer  1004  along the scribing lines using wafer laser dicing and/or mechanical dicing techniques, thereby becoming respective die  1012 . Die  1012  can include second semiconductor structure  1008 , for example, the structure as shown in  FIG. 7C . 
     Method  1200  proceeds to operation  1206 , as illustrated in  FIG. 12 , in which the first die and the second die are bonded in a face-to-face manner, such that the first semiconductor structure is bonded to the second semiconductor structure. The first bonding contacts of the first semiconductor structure are in contact with the second bonding contacts of the second semiconductor structure at a bonding interface. As illustrated in  FIG. 10C , die  1010  including first semiconductor structure  1006  and die  1012  including second semiconductor structure  1008  are bonded in a face-to-face manner, such that first semiconductor structure  1006  is bonded to second semiconductor structure  1008  at a bonding interface  1014 . Although first semiconductor structure  1006  is above second semiconductor structure  1008  after the bonding as shown in  FIG. 10C , it is understood that second semiconductor structure  1008  may be above first semiconductor structure  1006  after the bonding in some embodiments.  FIG. 8A  illustrates one example of the formation of bonded first and second semiconductor structures  1006  and  1008 . 
     Method  1200  proceeds to operation  1208 , as illustrated in  FIG. 12 , in which the first wafer or the second wafer is thinned to form a semiconductor layer. In some embodiments, the first wafer of the first semiconductor structure, which is above the second wafer of the second semiconductor structure after the bonding, is thinned to form the semiconductor layer. In some embodiments, the second wafer of the second semiconductor structure, which is above the first wafer of the first semiconductor structure after the bonding, is thinned to form the semiconductor layer. 
     As illustrated in  FIG. 8B , the substrate at the top of the bonded chip (e.g., silicon substrate  702  as shown in  FIG. 8A ) is thinned, so that the thinned top substrate can serve as a semiconductor layer  804 , for example, a single-crystal silicon layer. Silicon substrate  702  can be thinned by processes including, but not limited to, wafer grinding, dry etch, wet etch, CMP, any other suitable processes, or any combination thereof. In one example, the thickness of the thinned substrate may be between about 1 μm and about 20 μm, such as between 1 μm and 20 μm (e.g., 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, 10 μm, 15 μm, 20 μm, any range bounded by the lower end by any of these values, or in any range defined by any two of these values), for example, using a combination of etch and CMP processes. It is understood that in some embodiments, by further applying an additional etch process, the thickness of the thinned substrate may be further reduced to below 1 μm, e.g., in the sub-micron range. It is understood that when silicon substrate  602  is the substrate at the top of the bonded chip, another semiconductor layer may be formed by thinning silicon substrate  602 . 
     Method  1200  proceeds to operation  1210 , as illustrated in  FIG. 12 , in which a pad-out interconnect layer is formed above the semiconductor layer. As illustrated in  FIG. 8B , a pad-out interconnect layer  806  is formed above semiconductor layer  804  (the thinned top substrate). Pad-out interconnect layer  806  can include interconnects, such as pad contacts  808 , formed in one or more ILD layers. Pad contacts  808  can include conductive materials including, but not limited to, W, Co, Cu, Al, doped silicon, silicides, or any combination thereof. The ILD layers can include dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. In some embodiments, after the bonding and thinning, contacts  810  are formed extending vertically through semiconductor layer  804 , for example by wet/dry etch followed by depositing conductive materials. Contacts  810  can be in contact with the interconnects in pad-out interconnect layer  806 . 
     As described above, the semiconductor device having a programmable logic device fabricated according to method  1200  has an undefined function at the time of manufacture and needs to be programmed after the manufacturing to perform its desired functions, according to some embodiments. For example,  FIG. 13  is a flowchart of an exemplary method  1300  for programming a semiconductor device having a programmable logic device, according to some embodiments. The semiconductor device described in  FIG. 13  can be any semiconductor devices described herein including, for example, semiconductor devices  400 ,  401 ,  500 ,  501  depicted in  FIGS. 4A, 4B, 5A, and 5B , respectively. 
     Referring to  FIG. 13 , method  1300  starts at operation  1302 , in which the functions to be performed by the semiconductor device having a programmable logic device, e.g., FPGA, are specified. For example, the I/O interfaces, function behaviors and/or modules at different levels and internal interfaces thereof, and system clock may be defined as a function specification at this stage. Method  1300  proceeds to operation  1304 , as illustrated in  FIG. 13 , in which the function specification is provided in the forms of HDLs, such as VHDL or Verilog. For example, the register-transfer level (RTL) description in the HDLs may be created and simulated. Method  1300  proceeds to operation  1306 , as illustrated in  FIG. 13 , in which the design specified in the HDLs is synthesized. For example, bitstreams/netlist for the programmable logic device may be generated by the logic synthesis process, which turns the abstract specification of desired function behaviors, for example at RTL, into the design at the logic blocks levels. Method  1300  proceeds to operation  1308 , as illustrated in  FIG. 13 , in which the logic blocks are placed and routed (interconnected) on the grid of the programmable logic device. For example, an automated place-and-route procedure may be performed to generate a pinout based on the netlist, which will be used to interface with the parts outside of the programmable logic device. Operations  1302 ,  1304 ,  1306 , and  1308  can be performed by electronic design automation (EDA) tools. 
     Method  1300  proceeds to operation  1310 , as illustrated in  FIG. 13 , in which the semiconductor device having a programmable logic device is configured. For example, once the design and validation processes are complete, the binary file generated, for example, using the FPGA vendor&#39;s proprietary software, may be used to configure the programmable logic device. In one example, this file in the format of bitstreams is transferred/downloaded into the FPGA via an interface, e.g., a serial interface (JTAG), or to the memory devices, e.g., the SRAM and/or DRAM, in the semiconductor device. It is understood that in some embodiments, method  1300  may proceed to operation  1312 , as illustrated in  FIG. 13 , in which the semiconductor device having a programmable logic device may be partially reconfigured in a dynamic manner while the remaining programmable logic device design continues to function. For example, a subset of the programmable logic blocks in an operating FPGA design may be reconfigured by downloading a partial bitstream into the FPGA in the semiconductor device. Partial Reconfiguration can allow for the dynamic change of function modules within an active FPGA design. 
     According to one aspect of the present disclosure, a semiconductor device includes a first semiconductor structure including a programmable logic device, an array of SRAM cells, and a first bonding layer including a plurality of first bonding contacts. The semiconductor device also includes a second semiconductor structure including an array of DRAM cells and a second bonding layer including a plurality of second bonding contacts. The semiconductor device further includes a bonding interface between the first bonding layer and the second bonding layer. The first bonding contacts are in contact with the second bonding contacts at the bonding interface. 
     In some embodiments, the first semiconductor structure includes a substrate, the programmable logic device on the substrate, the array of SRAM cells on the substrate and outside of the programmable logic device, and the first bonding layer above the programmable logic device and the array of SRAM cells. 
     In some embodiments, the second semiconductor structure includes the second bonding layer above the first bonding layer, the array of DRAM cells above the second bonding layer, and a semiconductor layer above and in contact with the array of DRAM cells. 
     In some embodiments, the semiconductor device further includes a pad-out interconnect layer above the semiconductor layer. In some embodiments, the semiconductor layer includes single-crystal silicon. 
     In some embodiments, the second semiconductor structure includes a substrate, the array of DRAM cells on the substrate, and the second bonding layer above the array of DRAM cells. 
     In some embodiments, the first semiconductor structure includes the first bonding layer above the second bonding layer, the programmable logic device above the first bonding layer, the array of SRAM cells above the first bonding layer and outside of the programmable logic device, and a semiconductor layer above and in contact with the programmable logic device and the array of SRAM cells. 
     In some embodiments, the semiconductor device further includes a pad-out interconnect layer above the semiconductor layer. In some embodiments, the semiconductor layer includes single-crystal silicon. 
     In some embodiments, the first semiconductor structure further includes a peripheral circuit of the array of DRAM cells. In some embodiments, the second semiconductor structure further includes a peripheral circuit of the array of DRAM cells. 
     In some embodiments, the first semiconductor structure includes a first interconnect layer vertically between the first bonding layer and the programmable logic device, and the second semiconductor structure includes a second interconnect layer vertically between the second bonding layer and the array of DRAM cells. 
     In some embodiments, the programmable logic device is electrically connected to the array of DRAM cells through the first and second interconnect layers and the first and second bonding contacts. 
     In some embodiments, the array of SRAM cells are electrically connected to the array of DRAM cells through the first and second interconnect layers and the first and second bonding contacts. 
     In some embodiments, the programmable logic device includes a plurality of programmable logic blocks. 
     In some embodiments, each DRAM cell includes a transistor and a capacitor. 
     According to another aspect of the present disclosure, a method for forming a semiconductor device is disclosed. A plurality of first semiconductor structures are formed on a first wafer. At least one of the first semiconductor structures includes a programmable logic device, an array of SRAM cells, and a first bonding layer including a plurality of first bonding contacts. A plurality of second semiconductor structures are formed on a second wafer. At least one of the second semiconductor structures includes an array of DRAM cells and a second bonding layer including a plurality of second bonding contacts. The first wafer and the second wafer are bonded in a face-to-face manner, such that the at least one of the first semiconductor structures is bonded to the at least one of the second semiconductor structures. The first bonding contacts of the first semiconductor structure are in contact with the second bonding contacts of the second semiconductor structure at a bonding interface. The bonded first and second wafers are diced into a plurality of dies. At least one of the dies includes the bonded first and second semiconductor structures. 
     In some embodiments, to form the plurality of first semiconductor structures, the programmable logic device and the array of SRAM cells are formed on the first wafer, a first interconnect layer is formed above the programmable logic device and the array of SRAM cells, and the first bonding layer is formed above the first interconnect layer. In some embodiments, to form the programmable logic device and the array of SRAM cells, a plurality of transistors are formed on the first wafer. 
     In some embodiments, to form the plurality of first semiconductor structures, a peripheral circuit of the array of DRAM cells is formed on the first wafer. 
     In some embodiments, to form the plurality of second semiconductor structures, the array of DRAM cells are formed on the second wafer, a second interconnect layer is formed above the array of DRAM cells, and the second bonding layer is formed above the second interconnect layer. 
     In some embodiments, to form the array of DRAM cells, a plurality of transistors are formed on the second wafer, and a plurality of capacitors are formed above and in contact with at least some of the transistors. 
     In some embodiments, to form the plurality of second semiconductor structures, a peripheral circuit of the array of DRAM cells is formed on the second wafer. 
     In some embodiments, the second semiconductor structure is above the first semiconductor structure after the bonding. In some embodiments, after the bonding and prior to the dicing, the second wafer is thinned to form a semiconductor layer, and a pad-out interconnect layer is formed above the semiconductor layer. 
     In some embodiments, the first semiconductor structure is above the second semiconductor structure after the bonding. In some embodiments, after the bonding and prior to the dicing, the first wafer is thinned to form a semiconductor layer, and a pad-out interconnect layer is formed above the semiconductor layer. 
     In some embodiments, the bonding includes hybrid bonding. 
     According to still another aspect of the present disclosure, a method for forming a semiconductor device is disclosed. A plurality of first semiconductor structures are formed on a first wafer. At least one of the first semiconductor structures includes a programmable logic device, an array of SRAM cells, and a first bonding layer including a plurality of first bonding contacts. The first wafer is diced into a plurality of first dies, such that at least one of the first dies includes the at least one of the first semiconductor structures. A plurality of second semiconductor structures are formed on a second wafer. At least one of the second semiconductor structures includes an array of DRAM cells and a second bonding layer including a plurality of second bonding contacts. The second wafer is diced into a plurality of second dies, such that at least one of the second dies includes the at least one of the second semiconductor structures. The first die and the second die are bonded in a face-to-face manner, such that the first semiconductor structure is bonded to the second semiconductor structure. The first bonding contacts of the first semiconductor structure are in contact with the second bonding contacts of the second semiconductor structure at a bonding interface. 
     In some embodiments, to form the plurality of first semiconductor structures, the programmable logic device and the array of SRAM cells are formed on the first wafer, a first interconnect layer is formed above the programmable logic device and the array of SRAM cells, and the first bonding layer is formed above the first interconnect layer. In some embodiments, to form the programmable logic device and the array of SRAM cells, a plurality of transistors are formed on the first wafer. 
     In some embodiments, to form the plurality of first semiconductor structures, a peripheral circuit of the array of DRAM cells is formed on the first wafer. 
     In some embodiments, to form the plurality of second semiconductor structures, the array of DRAM cells are formed on the second wafer, a second interconnect layer is formed above the array of DRAM cells, and the second bonding layer is formed above the second interconnect layer. 
     In some embodiments, to form the array of DRAM cells, a plurality of transistors are formed on the second wafer, and a plurality of capacitors are formed above and in contact with at least some of the transistors. 
     In some embodiments, to form the plurality of second semiconductor structures, a peripheral circuit of the array of DRAM cells is formed on the second wafer. 
     In some embodiments, the second semiconductor structure is above the first semiconductor structure after the bonding. In some embodiments, the second wafer is thinned to form a semiconductor layer after the bonding, and a pad-out interconnect layer is formed above the semiconductor layer. 
     In some embodiments, the first semiconductor structure is above the second semiconductor structure after the bonding. In some embodiments, the first wafer is thinned to form a semiconductor layer after the bonding, and a pad-out interconnect layer is formed above the semiconductor layer. 
     In some embodiments, the bonding includes hybrid bonding. 
     The foregoing description of the specific embodiments will so reveal the general nature of the present disclosure that others can, by applying knowledge within the skill of the art, readily modify and/or adapt for various applications such specific embodiments, without undue experimentation, without departing from the general concept of the present disclosure. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein. It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by the skilled artisan in light of the teachings and guidance. 
     Embodiments of the present disclosure have been described above with the aid of functional building blocks illustrating the implementation of specified functions and relationships thereof. The boundaries of these functional building blocks have been arbitrarily defined herein for the convenience of the description. Alternate boundaries can be defined so long as the specified functions and relationships thereof are appropriately performed. 
     The Summary and Abstract sections may set forth one or more but not all exemplary embodiments of the present disclosure as contemplated by the inventor(s), and thus, are not intended to limit the present disclosure and the appended claims in any way. 
     The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.