Patent Publication Number: US-9847763-B2

Title: Self-regulated reference for switched capacitor circuit

Description:
RELATED APPLICATIONS 
     This Application claims priority under 35 U.S.C. §119(e) to U.S. Provisional Application Ser. No. 62/218,758, entitled “SELF-REGULATED REFERENCE FOR SWITCHED CAPACITOR CIRCUIT” filed on Sep. 15, 2015, which is herein incorporated by reference in its entirety. 
    
    
     BACKGROUND 
     Switched capacitors are electronic circuit elements and are often used in continuous and discrete time signal processing. Switched capacitors operate by moving charges in and out of one or more capacitors when switches are opened or closed. Control signals are often used to drive the state of the switches. Switched capacitors are often used in analog-to-digital (ADC) converters and filters. 
     BRIEF SUMMARY 
     According to one aspect of the present application, a switched capacitor circuit is provided. The switched capacitor circuit may comprise a differential operational amplifier; at least one capacitor coupled to an input of the differential operational amplifier; and a feedback circuit coupled to the input of the differential operational amplifier and an input of the switched-capacitor circuit, the feedback circuit being configured to receive a reference signal and to produce, based at least in part on the reference signal, at least one stabilized reference signal. 
     According to another aspect of the present application, a switched capacitor circuit is provided. The switched capacitor circuit may comprise a differential operational amplifier; at least one capacitor coupled to an input of the differential operational amplifier; and a feedback circuit coupled to the input of the differential operational amplifier and an input of the switched-capacitor circuit, wherein the feedback circuit exhibits a gain configured to cancel, at least in part, a capacitance of the at least one capacitor. 
    
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
       The accompanying drawings are not intended to be drawn to scale. In the drawings, each identical or nearly identical component that is illustrated in various figures is represented by a like numeral. For purposes of clarity, not every component may be labeled in every drawing. In the drawings: 
         FIG. 1  is a block diagram illustrating a switched capacitor circuit and a feedback circuit, according to some non-limiting embodiments. 
         FIG. 2  is a circuit diagram illustrating a differential operational amplifier, a plurality of capacitors and a plurality of feedback circuits, according to some non-limiting embodiments. 
         FIG. 3  is a chart illustrating a pair of control signals, according to some non-limiting embodiments. 
         FIG. 4  is another circuit diagram illustrating a differential operational amplifier, a plurality of capacitors and a plurality of feedback circuits, according to some non-limiting embodiments. 
         FIGS. 5A-5B  are circuit diagrams illustrating feedback amplifiers, according to some non-limiting embodiments. 
         FIGS. 6A-6B  are circuit diagrams illustrating voltage reference generators, according to some non-limiting embodiments. 
         FIGS. 7A-7B  are circuit diagrams illustrating flipped voltage followers, according to some non-limiting embodiments. 
     
    
    
     DETAILED DESCRIPTION 
     The inventors have appreciated that the performance of electronic circuits comprising switched capacitor circuits can be greatly improved by stabilizing the reference voltage provided to the switched capacitor. Often, electronic circuits operate in a manner that deviates from the desired operation. For example, a portion of the electronic circuit may exhibit an increase in temperature, either due to electric currents flowing in such portion of the electronic circuit or due to neighboring circuits heating up. Such temperature increase may cause various circuit parameters, such as the threshold voltage of a metal-oxide-semiconductor field effect transistor (MOSFET), to vary unexpectedly. As another example, when fabricated on a semiconductor substrate, an electronic circuit or component may have design parameters, such as the width or the length of a particular doped region or a doping level, that are different from the desired value. Such inaccuracies, referred to herein as “process variations”, may also cause various circuit parameters, such as the threshold voltage of a MOSFET, to vary unexpectedly. In some circumstances, such unexpected parameter variations may lead to undesired signals fluctuations, or to signals having values that deviate from the expected values. 
     Reference voltages are often used in electronic circuits, such as switched capacitor circuits, to ensure reliable operation. For example, a particular class of analog-to-digital converters (ADCs) comprises a switched capacitor circuit, and often utilizes a reference voltage to perform the conversion. However, such a reference voltage may deviate from the desired value for the reasons described above. Consequently, the performance of electronic circuits that rely on stable and predictable reference voltages may be degraded. 
     One aspect of the present application provides a feedback circuit configured to stabilize a reference voltage in an electronic circuit, such as a switched capacitor circuit. In some embodiments, the reference voltage may be stabilized against temperature and/or process variations. 
     The inventors have further appreciated that the bandwidth (i.e., speed) of switched capacitor circuits may be increased significantly by providing a feedback circuit having a gain configured to at least partially cancel a capacitance of the switched capacitor circuit. Because the time that it takes to charge or discharge the capacitor is finite and depends on the capacitance associated with the capacitor, a capacitor may introduce signal delays in an electronic circuit. Thus, canceling at least a portion of the capacitance can reduce the signal delays, which increases the speed of the switched capacitor circuit. In some embodiments, a feedback circuit is configured to at least partially cancel a capacitance of the switched capacitor circuit, which increases the speed of the switched capacitor circuit. Such a feedback circuit may have a gain selected to achieve the capacitance cancellation. 
       FIG. 1  is a block diagram illustrating a switched capacitor circuit. Switch capacitor circuit  100  may include a capacitor circuit  102 , a feedback circuit  104 , and an operational amplifier  106 . Capacitor circuit  102  may include one or more capacitors, connected with one another in any suitable way. In some embodiments, some or all the capacitors may be coupled to a respective switch. In some embodiments, the switched capacitor circuit may serve as a sample and hold (S/H) circuit, and may for example be used in an analog-to-digital converter (ADC). However, the application is not limited in this respect and the switched capacitor circuits described herein may serve in any suitable application. 
     The capacitor circuit  102  may be coupled to one or more inputs of operational amplifier  106 . Operational amplifier  106  may comprise a differential input stage in some embodiments, and may have two inputs. Alternatively, or additionally, operational amplifier  106  may comprise a differential output stage in some embodiments, and may have two outputs. In some embodiments, at least one output of the operational amplifier  106  may be connected to at least one input of the operational amplifier  106  (not shown in  FIG. 1 ). In this configuration, operational amplifier  106  may operate in a closed loop. The loop may be configured to increase the bandwidth of the operational amplifier in some embodiments. 
     Feedback circuit  104  may have a terminal connected to an input of the capacitor circuit  102 , and a terminal connected to an output of the capacitor circuit  102  and an input of operational amplifier  106 . Additionally, feedback circuit  104  may be configured to receive a direct-current (DC) reference voltage V ref . According to one aspect of the present application, feedback circuit  104  may be configured to receive a reference voltage V ref , and to produce a stabilized version of V ref . The expressions “stabilized version”, “stabilized signal”, or simply “stabilized” will be used herein to indicate compensation of a signal against process and/or temperature variations. Accordingly, a stabilized signal may exhibit fluctuations, caused by process and/or temperature variations, that are significantly less than un-stabilized signals. Reference voltages are used to bias a circuit, such as an amplifier, so as to place the circuit in a desired operating region. For example, a reference voltage may be used to bias an amplifier using metal-oxide-semiconductor (MOS) transistors so as to place the transistors in the saturation region. Reference voltages that exhibit fluctuations caused by temperature and/or process variations may cause the amplifier to provide a fluctuating gain, or in some circumstances, to depart from the saturation region. The feedback circuit  104  may include circuitry configured to generate a reference signal that is insensitive to temperature and/or process variations. 
     In some embodiments, capacitor circuit  102  may be configured to receive an alternating current (AC) input signal V i . As a non-limiting example, V i  may represent an analog signal to be digitized. In some embodiments, operational amplifier  106  may output an AC output voltage V o , which may represent an analog and/or a digital signal. 
     In some embodiments, operational amplifier  106  may be differential, and feedback circuit  104  may include a first and second feedback circuit, each coupled to a respective input of the differential operational amplifier. Being differential, the sensitivity of the switched capacitor circuit to temperature and/or process variations may be significantly decreased with respect to single-ended configurations. 
       FIG. 2  is a circuit diagram illustrating an example of system  100 , according to some embodiments.  FIG. 2  shows switched capacitor circuit  100  may include a plurality of capacitors, a differential operational amplifier, and a pair of feedback circuits, according to some non-limiting embodiments. Differential operational amplifier  206  may comprise a first input “+” and a second input “−”. In addition, differential operational amplifier  206  may comprise a first output “−” and a second output “+”. The “+” input may exhibit a voltage V ip  having a π phase shift with respect to the voltage V in  of the “−” input. The “+” output may exhibit a voltage V op  having a π phase shift with respect to the voltage V on  of the “−” output. In some embodiments, the “−” output may be connected to the “+” input through a capacitor C f1 . In some embodiments, the “−” output may be connected to the “+” input through a capacitor C f1  and a switch S 5 . However, the application is not limited in this respect and the “−” output may be connected to the “+” input through any suitable combination of resistive, capacitive and inductive components. In some embodiments, the “+” output may be connected to the “−” input through a capacitor C f2 . In some embodiments, the “−” output may be connected to the “+” input through a capacitor C f2  and switch S 6 . However, the application is not limited in this respect and the “+” output may be connected to the “−” input through any suitable combination of resistive, capacitive and inductive components. 
     In some embodiments, the output terminal of a capacitor C s1  may be coupled to the “+” input of the differential operational amplifier  206 , and the output terminal of a capacitor C s2  may be coupled to the “−” input of the differential operational amplifier  206 . The input terminals of capacitors C s1  and C s2  may be connected to the outputs of feedback circuits  204   B  and  204   A  respectively. An input of feedback circuit  204   A  may be coupled to the output terminal of capacitor C s1 , and may be configured to receive voltage V ip . Similarly, an input of feedback circuit  204   B  may be coupled to the output terminal of capacitor C s2 , and may be configured to receive voltage V in . 
     In some embodiments, capacitors C p1  and C p2  may be coupled to the output terminals of capacitor C s1  and C s2  respectively. Capacitors C p1  and C p2  may be further coupled to the ground terminal. In some embodiments, capacitors C p1  and C p2  may represent physical capacitors. In other embodiments, capacitors C p1  and C p2  may represent parasitic capacitances. 
     In some embodiments, capacitors C s1  and C s2  may be connected to input voltages V i   +  and V i   −  via switches S 1  and S 4  respectively. In some embodiments, capacitors C s1  and C s2  may be connected to the outputs of feedback circuits  204   A  and  204   B  via switches S 2  and S 3  respectively. 
     Referring to  FIG. 3 , there is shown a pair of drive signals Φ 1  and Φ 2 , according to some non-limiting embodiments. In some embodiments, when drive signals Φ 1  is equal to a logic 1, drive signals Φ 2  may be equal to a logic 0. In some embodiments, when drive signals Φ 2  is equal to a logic 1, drive signals Φ 1  may be equal to a logic 0. However, the application is not limited in this respect and drive signals Φ 1  and Φ 2  may assume the same logic value simultaneously in some embodiments. In some embodiments, drive signal Φ 1  may be used to select the state of switches S 1 , S 4 . For example, when drive signal Φ 1  is equal to a logic 1, the corresponding switch may be in a closed state, and when drive signal Φ 1  is equal to a logic 0, the corresponding switch may be in an open state. In some embodiments, drive signal Φ 2  may be used to select the state of switches S 2 , S 3 , S 5 , S 6  or any suitable combination thereof. For example, when drive signal Φ 2  is equal to a logic 1, the corresponding switch may be in a closed state, and when drive signal Φ 2  is equal to a logic 0, the corresponding switch may be in an open state. 
     Referring back to  FIG. 2 , when Φ 1  is equal to a logic 1, the input voltage V i   +  may be coupled to capacitor C s1  and the input voltage V i   −  may be coupled to capacitor C s2 . This case will be referred to herein as the “sample” phase. When Φ 2  is equal to a logic 1, feedback circuit  204   A  may be connected to capacitor C s1 , and feedback circuit  204   B  may be connected to capacitor C s2 . Additionally, or alternatively, the “+” input may be connected to the “−” output of the differential operational amplifier and the “−” input may be connected to the “+” output of the differential operational amplifier. This case will be referred to herein as the “hold” phase. 
     In some embodiments, feedback circuits  204   A  and  204   B  may comprise feedback amplifiers  203   A  and  203   B  respectively. As will be described further below, feedback amplifiers  203   A  and  203   B  may each comprise common-source amplifiers. The common-source amplifiers may be connected to respective resistive loads or active loads. 
     In some embodiments, feedback circuits  204   A  and  204   B  may comprise flipped voltage followers  205   A  and  205   B  respectively. The flipped voltage followers may be coupled to a respective feedback amplifier. In some embodiments, the feedback amplifiers may be inverting. In such embodiments, it will be assumed that the gain of the feedback amplifier  203   A  is “−A 203A ” and the gain of the feedback amplifier  203   B  is “−A 203B ”. In some embodiments, the flipped voltage followers may be non-inverting. In such embodiments, it will be assumed that the gain of the flipped voltage follower  205   A  is “A 205A ” and the gain of the flipped voltage follower  205   B  is “A 205B ”. However the application is not limited in this respect and the feedback amplifiers and the flipped voltage followers may be inverting or non-inverting. 
     In some embodiments, feedback amplifiers  203   A  and  203   B  may be configured to receive a reference voltage V ref . Based, at least in part, on V ref , the feedback circuits  204   B  and  204   A  may be configured to provide voltages V r1  and V r2  respectively. Voltages V r1  and V r2  will be referred to herein as “stabilized reference voltages”. In some embodiments, the voltage V r1  may be expressed by:
 
 V   r1   =V   in (− A   203B ) A   205B   =V   ip   A   203B   A   205B  
 
     In some embodiments, feedback amplifier  203   B  may be configured to exhibit a gain equal to:
 
(− A   203B )=−( C   s1   +C   p1 )/ C   s1  
 
     Furthermore, the voltage V ip  may be expressed in terms of V on  as follows:
 
 V   ip   =V   on ( C   f1 /( C   f1   +C   p1   +C   s1 ))+ V   r1 ( C   s1 /( C   f1   +C   p1   +C   s1 ))== V   on ( C   f1 /( C   f1   +C   p1   −C   s1 ))+ V   in (− A   203B ) A   205B ( C   s1 /( C   f1   +C   p1   −C   s1 ))== V   on ( C   f1 /( C   f1   +C   p1   +C   s1 ))+ V   ip   A   205B ( C   f1 /( C   f1   +C   p1   −C   s1 ))
 
     In some embodiments, it may be assumed that A 205B  is equal to 1. In such embodiments, following the previous expression, V ip  may be expressed by:
 
 V   ip (1−(( C   s1   +C   p1 )/( C   f1   +C   s1   +C   p1 ))= V   on ( C   f1 ( C   f1   +C   p1   +C   s1 ))
 
or
 
 V   ip   =V   on  
 
     As shown, in such circumstance, the operational amplifier feedback factor may be equal to 1. As defined herein, the operational amplifier feedback factor may indicate the ratio between an output voltage and a corresponding input voltage of a differential operational amplifier. In other embodiments, the operational amplifier feedback factor may be between 0.95 and 1.05, between 0.9 and 1.1, between 0.8 and 1.2, between 0.75 and 1.25, between 0.5 and 1.5, or between any other suitable values or range of values. 
     In some embodiments, the operational amplifier feedback factor may be independent of C p1 , C f1 , C s1 , or any suitable combination of thereof. 
     Similarly, it may be shown that, in some embodiments, V in =V op . In some embodiments, the operational amplifier feedback factor may be independent of C p2 , C f2 , C s2 , or any suitable combination of thereof. 
     One or more of the capacitances shown in  FIG. 2  may be at least partially canceled, when the operational amplifier feedback factor is independent of such capacitor. In some embodiments, feedback circuits  204   A  and  204   B  may exhibit gains configured to mitigate a time delay associated with C f1 , C f2 , C s1 , C s2 , C p1 , C p2 , or any suitable combination thereof. 
     In some embodiments, each of the feedback circuits may be differential, and may be configured to receive at least two inputs. Such inputs may form a differential signal. In such embodiments, the feedback amplifiers may comprise differential amplifiers. 
       FIG. 4  is another circuit diagram illustrating a differential operational amplifier, a plurality of capacitors and a plurality of feedback circuits, according to some non-limiting embodiments. Circuit  300  may comprise differential operational amplifier  306 , feedback circuits  304   A  and  304   B , and capacitors C s1 , C s2 , C s3 , and C s4 . Circuit  300  may be configured to receive at least two input voltages V 1   +  and V i   − , which in some embodiments, may form a differential signal. Input voltage V i   +  is coupled to the input terminal of capacitor C s1  via switch S 11 , and to the input terminal of capacitor C s2  via switch S 13 . Input voltage V i   −  be coupled to the input terminal of capacitor C s3  via switch S 16 , and to the input terminal of capacitor C s4  via switch S 18 . 
     Differential operational amplifier  306  may comprise a first input “+” and a second input “−”. In addition, differential operational amplifier  306  may comprise a first output “−” and a second output “+”. The “+” input may exhibit a voltage V ip , having a π phase shift with respect to the voltage V in  of the “−” input. The “+” output may exhibit a voltage V op  having a π phase shift with respect to the voltage V on  of the “−” output. In some embodiments, the “−” output may be connected to the “+” input through a capacitor C f1 . In some embodiments, the “+” output may be connected to the “−” input through a capacitor C f1 , and a switch S 19 . However, the application is not limited in this respect and the “−” output may be connected to the “+” input through any suitable combination of resistive, capacitive and inductive components. In some embodiments, the “+” output may be connected to the “−” input through a capacitor C f2 . In some embodiments, the “+” output may be connected to the “−” input through a capacitor C f2 , and a switch S 20 . However, the application is not limited in this respect and the “+” output may be connected to the “−” input through any suitable combination of resistive, capacitive and inductive components. 
     The output terminal of capacitor C s1  and C s2  may be connected to the “+” input of the differential operational amplifier  306 . The output terminal of capacitor C s3  and C s4  may be connected to the “−” input of the differential operational amplifier  306 . Feedback circuit  304   A  and  304   B  may each receive V ip  and V in+  as inputs. 
     Feedback circuit  304   A  may be configured to output voltages V Rn   _   p  and V Rn   _   n . Voltages V Rn   _   p  and V Rn   _   n  may form a differential signal in some embodiments. Voltage V Rn   _   p  and may be coupled to capacitor C s2  through switch S 14 , and voltage V Rn   _   n  and may be coupled to capacitor C s3  through switch S 15 . 
     Feedback circuit  304   B  may be configured to output voltages V Rp   _   p  and V Rp   _   n . Voltages V Rp   _   p  and V Rp   _   n  may form a differential signal in some embodiments. Voltage V Rp   _   p  and may be coupled to capacitor C s1  through switch S 12 , and voltage V Rp   _   n , and may be coupled to capacitor C s4  through switch S 17 . 
     In some embodiments, feedback circuits  304   A  and  304   B  may comprise feedback amplifiers  303   A  and  303   B  respectively. Feedback amplifiers  303   A  and  303   B  may each comprise common-source amplifiers. The common-source amplifiers may be connected to respective resistive loads or active loads. Feedback amplifier  303   A  may be configured to output voltages i p   +  and i p   − , which may form a differential signal in some embodiments. Feedback amplifier  303   B  may be configured to output voltages i n   +  and i n   − , which may form a differential signal in some embodiments. 
     In some embodiments, feedback circuits  304   A  and  304   B  may comprise flipped voltage followers  305   A  and  305   B  respectively. Flipped voltage followers  305   A  may be configured to receive i p   +  and i p   − , while flipped voltage followers  305   B  may be configured to receive i n   +  and i n   − . In some embodiments, the feedback amplifiers may be inverting. In such embodiments, it will be assumed that the gain of the feedback amplifier  303   A  is “−A 303A ” and the gain of the feedback amplifier  303   B  is “−A 303B ”. In some embodiments, the flipped voltage followers may be non-inverting. In such embodiments, it will be assumed that the gain of the flipped voltage follower  305   A  is “A 305A ” and the gain of the flipped voltage follower  305   B  is “A 305B ”. However the application is not limited in this respect and the feedback amplifiers and the flipped voltage followers may be inverting or non-inverting. 
     In some embodiments, feedback amplifiers  303   A  and  303   B  may be configured to receive reference voltages V refn  and V refp . Based, at least in part, on V refn  and V refp , the feedback circuits may be configured to provide voltages V Rn   _   n , V Rn   _   p , V Rp   _   n , and V Rp   _   p . Voltages V Rn   _   n , V Rn   _   p , V Rp   _   n , and V Rp   _   p  will be referred to herein as “stabilized reference voltages”. 
     In some embodiments, the “+” input and the “−” input of the differential operational amplifier  306  may be connected to one another through switches S 21  and S 22 . 
     In some embodiments, drive signal Φ 1 , illustrated in  FIG. 3 , may be used to select the state of switches S 11 , S 13 , S 16 , S 18 , S 21 , S 22 , or any suitable combination thereof. For example, when drive signal Φ 1  is equal to a logic 1, the corresponding switch may be in a closed state, when drive signal Φ 1  is equal to a logic 0, the corresponding switch may be in an open state. In some embodiments, drive signal Φ 2  may be used to select the state of switches S 12 , S 14 , S 15 , S 17 , S 19 , S 20 , or any suitable combination thereof. For example, when drive signal Φ 2  is equal to a logic 1, the corresponding switch may be in a closed state, when drive signal Φ 2  is equal to a logic 0, the corresponding switch may be in an open state. 
     When Φ 1  is equal to a logic 1, the input voltage V i   +  may be coupled to capacitors C s1  and C s2  and the input voltage V i   −  may be coupled to capacitors C s3  and C s4 . This case will be referred to herein as the “sample” phase. When Φ 2  is equal to a logic 1, feedback circuit  304   A  may be connected to capacitors C s2  and C s3 , and feedback circuit  304   B  may be connected to capacitors C s2  and C s3 . Additionally, or alternatively, the “+” input may be connected to the “−” output of the differential operational amplifier and the “−” input may be connected to the “+” output of the differential operational amplifier. This case will be referred to herein as the “hold” phase. 
     In some embodiments, the feedback circuits  304   A  and  304   B  may exhibit gains configured to make the operational amplifier feedback factor independent from some or all the capacitors of circuit  300 . 
     Exemplary feedback amplifiers are illustrated in  FIGS. 5A-5B .  FIG. 5A  illustrates feedback amplifier  501 , which may serve as feedback amplifier  203   A  and/or feedback amplifier  203   B  of  FIG. 2 . In addition,  FIG. 5A  illustrates a feedback amplifier  500 , which may comprise feedback amplifier  501 , and may serve as feedback amplifier  303   A  of  FIG. 4 . 
     Feedback amplifier  501  may comprise a voltage supplier V DD , a current generator  502 , a positive metal-oxide-semiconductor (PMOS) transistor  504 , and a PMOS transistor  506 . PMOS transistor  504  may be serve as an amplifier, and may be used in a common-source configuration, in which the source and gate terminals form an input port and the source and drain terminals form an output port. The output of the amplifier is denoted as the output voltage ip + . In some embodiments, transistor  504  is connected to a transistor  506 , serving as an active load. However, the application is not limited in this respect and transistor  504  may be alternatively connected to a passive load, such as a resistor or a plurality of resistors. The gate of transistor  506  may receive a reference voltage from voltage reference generator  510 . In some circumstances, the voltage reference generator  510  may be susceptible to thermal and/or process variations. However, because output DC voltages in common-source transistors are decoupled from any input DC voltage, output voltage ip +  may not be susceptible to such thermal and/or process variations. PMOS transistor  504  may be configured to amplify the input voltage V in  in some embodiments. In some embodiments, the gain provided by the feedback amplifier  501  may be equal to −g M  times the input impedance of the load, where g M  is defined as the trans-conductance of transistor  504 . In some embodiments, the gain may be configured to mitigate the time delay associated with one or more capacitors of  FIG. 2 . 
     Feedback amplifier  500  may comprise feedback amplifier  501  and PMOS transistors  503  and  505 . PMOS transistor  503  may be used in common-source configuration. PMOS transistors  503  and  504  may operate as a differential amplifier, and may configured to amplify the differential signal V ip -V in  (or V in -V ip ). Feedback amplifier  500  may generate output voltages ip +  and ip − , which may phased shifted by π with respect to one another. In some embodiments, transistor  503  is connected to a transistor  505 , serving as an active load. However, the application is not limited in this respect and transistor  503  may be alternatively connected to a passive load, such as a resistor or a plurality of resistors. The gate of transistor  505  may receive a reference voltage from voltage reference generator  510 . Because output DC voltages in common-source transistors are decoupled from input DC voltages, output voltages ip +  and ip −  may be insensitive to thermal and/or process variations. 
     While feedback amplifiers  500  and  501  utilize PMOS transistors in some embodiments, the application is not limited in this respect and any other suitable type of transistor may be used, such as an NPN bipolar junction transistor (BJT), a PNP BJT, a junction field effect transistor (JFET), a metal-oxide-semiconductor field effect transistor (MESFET), etc. 
       FIG. 5B  illustrates feedback amplifier  551 , which may serve as feedback amplifier  203   A  and/or feedback amplifier  203   B  of  FIG. 2 . In addition,  FIG. 5B  illustrates a feedback amplifier  550 , which may comprise feedback amplifier  551 , and may serve as feedback amplifier  303   B  of  FIG. 4 . 
     Feedback amplifier  551  may comprise a voltage supplier V DD , a current generator  552 , a negative metal-oxide-semiconductor (NMOS) transistor  554 , and an NMOS transistor  556 . NMOS transistor  554  may be serve as an amplifier, and may be used in a common-source configuration, in which the source and gate terminals form an input port and the source and drain terminals form an output port. The output of the amplifier is denoted as the output voltage in + . In some embodiments, transistor  554  is connected to a transistor  556 , serving as an active load. However, the application is not limited in this respect and transistor  554  may be alternatively connected to a passive load, such as a resistor or a plurality of resistors. The gate of transistor  556  may receive a reference voltage from voltage reference generator  560 . In some circumstances, the voltage reference generator  560  may be susceptible to thermal and/or process variations. However, because output DC voltages in common-source transistors are decoupled from input DC voltages, output voltage in +  may not be susceptible to such thermal and/or process variations. NMOS transistor  554  may be configured to amplify the input voltage V in  in some embodiments. In some embodiments, the gain provided by the feedback amplifier  551  may be equal to −g M  times the input impedance of the load, where g M  is defined as the trans-conductance of transistor  554 . In some embodiments, the gain may be configured to mitigate the time delay associated with one or more capacitors of  FIG. 2 . 
     Feedback amplifier  550  may comprise feedback amplifier  551  and NMOS transistors  553  and  555 . NMOS transistor  553  may be used in common-source configuration. NMOS transistors  553  and  554  may operate as a differential amplifier, and may configured to amplify the differential signal V ip -V in  (or V in -V ip ). Feedback amplifier  550  may generate output voltages in +  and in − , which may phased shifted by π with respect to one another. In some embodiments, transistor  553  is connected to a transistor  555 , serving as an active load. However, the application is not limited in this respect and transistor  553  may be alternatively connected to a passive load, such as a resistor or a plurality of resistors. The gate of transistor  555  may receive a reference voltage from voltage reference generator  560 . Because output DC voltages in common-source transistors are decoupled from input DC voltages, output voltages in +  and in −  may not be susceptible to thermal and/or process variations. 
     While feedback amplifiers  550  and  551  utilize NMOS transistors in some embodiments, the application is not limited in this respect and any other suitable type of transistor may be used, such as an NPN bipolar junction transistor (BJT), a PNP BJT, a junction field effect transistor (JFET), a metal-oxide-semiconductor field effect transistor (MESFET), etc. 
     Exemplary voltage reference generators are illustrated in  FIGS. 6A-6B , according to some non-limiting embodiments. Voltage reference generator  600  may serve as voltage reference generator  510  of  FIG. 5A , and voltage reference generator  650  may serve as voltage reference generator  560  of  FIG. 5B . 
     As illustrated in  FIG. 6A , voltage reference generator  600 , also referred to herein as “replica bias” may be connected to feedback amplifier  610 , which may serve as feedback amplifier  500  and/or  501  of  FIG. 5A . Voltage reference generator  600  may comprise voltage supplier V DD , current generators  602  and  604 , operational amplifier  601 , NMOS transistors  608  and  609 , and PMOS transistor  606 . A first input terminal of operational amplifier  601  may receive a reference voltage V refn . In some embodiments, current generator  602  may be connected to the source of PMOS transistor  606 , whose drain may be connected to ground. Current generator  604  may be connected to the drain of NMOS transistor  608  and to the gate of NMOS transistor  609 . The drain of NMOS transistor  609  may be connected to the source of NMOS transistor  608  and to a second input terminal of operational amplifier  601 . In some embodiments, voltage reference generator  600  and feedback amplifier  610  may be coupled through capacitor  612 . Being NMOS transistor  609  used in a common-source configuration, the reference voltage provided to feedback amplifier  610  may not be susceptible to thermal and/or process variations. 
     As illustrated in  FIG. 6B , voltage reference generator  660 , also referred to herein as “replica bias” may be connected to feedback amplifier  660 , which may serve as feedback amplifier  550  and/or  551  of  FIG. 5B . Voltage reference generator  650  may comprise voltage supplier V DD , current generators  652  and  654 , operational amplifier  651 , PMOS transistors  658  and  659 , and NMOS transistor  656 . A first input terminal of operational amplifier  651  may receive a reference voltage V refp . In some embodiments, current generator  652  may be connected to the source of NMOS transistor  656 , whose drain may be connected to V DD . Current generator  654  may be connected to the drain of PMOS transistor  608  and to the gate of PMOS transistor  659 . The drain of PMOS transistor  659  may be connected to the source of PMOS transistor  658  and to a second input terminal of operational amplifier  651 . In some embodiments, voltage reference generator  650  and feedback amplifier  660  may be coupled through capacitor  662 . Being PMOS transistor  659  used in a common-source configuration, the reference voltage provided to feedback amplifier  660  may not be susceptible to thermal and/or process variations. 
     In some embodiments, the output of the feedback amplifiers may be coupled to inputs of flipped voltage followers. Exemplary flipped voltage followers are illustrated in  FIGS. 7A-7B , according to some non-limiting embodiments. In some embodiments, a flipped voltage follower may be used as a buffer between the feedback amplifier and a switched capacitor to increase the bandwidth of the switched-capacitor circuit. In some embodiments, the flipped voltage follower exhibits a slew rate that is larger than the slew rate of the feedback amplifier. Accordingly, the use of a flipped voltage follower of the type described herein may improve the slew rate of the feedback circuit. 
     Flipped voltage follower  701 , illustrated in  FIG. 7A , may serve as flipped voltage follower  205   A  and/or  205   B  of  FIG. 2 , while flipped voltage follower  700  may serve as flipped voltage follower  305   A  of  FIG. 4 . Flipped voltage follower  701  may comprise voltage supplier V DD , current generator  712  and NMOS transistors  714  and  716 . The current generator  712  may be connected to the drain of NMOS transistor  714  and the gate of NMOS transistor  716 . The source of NMOS transistor  714  may be connected to the drain of NMOS transistor  716 , and the source of NMOS transistor  716  may be connected to ground. In some embodiments, the flipped voltage follower  701  may be configured to receive input signal ip − , to provide gain, and to output signal V Rn   _   n . In some embodiments, the flipped voltage follower may be configured to provide a unitary gain. Alternatively, the flipped voltage follower may be configured to provide a gain that is between 0.95 and 1.05, between 0.9 and 1.1, between 0.8 and 1.2, between 0.75 and 1.25, between 0.5 and 1.5, or between any other suitable values or range of values. 
     Flipped voltage follower  700  may comprise flipped voltage follower  701 , NMOS transistors  704  and  706 , and current generator  702 . The current generator  702  may be connected to the drain of NMOS transistor  704  and the gate of NMOS transistor  706 . The source of NMOS transistor  704  may be connected to the drain of NMOS transistor  706 , and the source of NMOS transistor  706  may be connected to ground. In some embodiments, the flipped voltage follower  700  may be configured to receive input signal ip + -ip −  (or ip − -ip + ), to provide gain, and to output signals V Rn   _   p  and V Rn   _   n . Signals V Rn   _   p  and V Rn   _   n  may be phase shifted by π with respect to one another. In some embodiments, the flipped voltage follower  700  may be configured to provide a unitary gain. Alternatively, the flipped voltage follower may be configured to provide a gain that is between 0.95 and 1.05, between 0.9 and 1.1, between 0.8 and 1.2, between 0.75 and 1.25, between 0.5 and 1.5, or between any other suitable values or range of values. 
     Flipped voltage follower  751 , illustrated in  FIG. 7B , may serve as flipped voltage follower  205   A  and/or  205   B  of  FIG. 2 , while flipped voltage follower  750  may serve as flipped voltage follower  305   B  of  FIG. 4 . Flipped voltage follower  751  may comprise voltage supplier V DD , current generator  762  and PMOS transistors  764  and  766 . The current generator  762  may be connected to the drain of PMOS transistor  764  and the gate of PMOS transistor  766 . The source of PMOS transistor  764  may be connected to the drain of PMOS transistor  766 , and the source of PMOS transistor  766  may be connected to ground. In some embodiments, the flipped voltage follower  751  may be configured to receive input signal in − , to provide gain, and to output signal V Rp   _   n . In some embodiments, the flipped voltage follower may be configured to provide a unitary gain. Alternatively, the flipped voltage follower may be configured to provide a gain that is between 0.95 and 1.05, between 0.9 and 1.1, between 0.8 and 1.2, between 0.75 and 1.25, between 0.5 and 1.5, or between any other suitable values or range of values. 
     Flipped voltage follower  750  may comprise flipped voltage follower  751 , PMOS transistors  754  and  756 , and current generator  752 . The current generator  752  may be connected to the drain of PMOS transistor  754  and the gate of PMOS transistor  756 . The source of PMOS transistor  754  may be connected to the drain of PMOS transistor  756 , and the source of PMOS transistor  756  may be connected to ground. In some embodiments, the flipped voltage follower  750  may be configured to receive input signal in + -in −  (or in − -in + ), to provide gain, and to output signals V Rp   _   p  and V Rp   _   n . Signals V Rp   _   p  and V Rp   _   n  may be phase shifted by π with respect to one another. In some embodiments, the flipped voltage follower  750  may be configured to provide a unitary gain. Alternatively, the flipped voltage follower may be configured to provide a gain that is between 0.95 and 1.05, between 0.9 and 1.1, between 0.8 and 1.2, between 0.75 and 1.25, between 0.5 and 1.5, or between any other suitable values or range of values. 
     Switched capacitor circuits of the type described herein may be used in multiplying digital-to-analog converters (MDAC). Multiplying digital-to-analog converters differ from conventional analog-to-digital converters in that they employ varying reference voltages. To ensure accurate digital-to-analog conversion, it is desirable that the varying reference voltage is insensitive to temperature and/or process variations. In some embodiments, the switched capacitor circuit of  FIG. 2  may be used in a MDAC. In such embodiments, the voltages V r1  and V r2  may be used as stabilized varying reference voltages for the MDAC. In some embodiments, the switched capacitor circuit of  FIG. 4  may be used in a MDAC. In such embodiments, the voltages V Rn   _   p , V Rn   _   n , V Rp   _   p  and V Rp   _   n  may be used as stabilized varying reference voltages for the MDAC. Various aspects of the apparatus and techniques described herein may be used alone, in combination, or in a variety of arrangements not specifically discussed in the embodiments described in the foregoing description and is therefore not limited in its application to the details and arrangement of components set forth in the foregoing description or illustrated in the drawings. For example, aspects described in one embodiment may be combined in any manner with aspects described in other embodiments. 
     Use of ordinal terms such as “first”, “second”, “third”, etc., in the claims to modify a claim element does not by itself connote any priority, precedence, or order of one claim element over another or the temporal order in which acts of a method are performed, but are used merely as labels to distinguish one claim element having a certain name from another element having a same name (but for use of the ordinal term) to distinguish the claim elements. 
     Also, the phraseology and terminology used herein is for the purpose of description and should not be regarded as limiting. The use of “including”, “comprising”, “having”, “containing” or “involving” and variations thereof herein, is meant to encompass the items listed thereafter and equivalents thereof as well as additional items. 
     The use of “coupled” or “connected” is meant to refer to circuit elements, or signals, that are either directly linked to one another or through intermediate components.