Patent Publication Number: US-2022223606-A1

Title: Memory device and method for forming the same

Description:
PRIORITY CLAIM AND CROSS-REFERENCE 
     This application is a Continuation Application of U.S. application Ser. No. 16/900,200, filed on Jun. 12, 2020, now U.S. Pat. No. 11,296,095, issued on Apr. 5, 2022, which is herein incorporated by reference. 
    
    
     BACKGROUND 
     Integrated circuits (ICs) sometimes include one-time-programmable (“OTP”) memory elements to provide non-volatile memory (“NVM”) in which data are not lost when the IC is powered off. One type of NVM includes an anti-fuse bit integrated into an IC by using a layer of dielectric material (oxide, etc.) connected to other circuit elements. To program an anti-fuse bit, a programming electric field is applied across the dielectric material layer to sustainably alter (e.g., break down) the dielectric material, thus decreasing the resistance of the dielectric material layer. Typically, to determine the status of an anti-fuse bit, a read voltage is applied across the dielectric material layer and a resultant current is read. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. 
         FIG. 1  is a schematic diagram of a memory device in accordance with some embodiments. 
         FIG. 2A  is a schematic diagram for performing a programming operation to a memory device in accordance with some embodiments. 
         FIG. 2B  is a schematic diagram for performing a read operation to a memory device in accordance with some embodiments. 
         FIG. 3A  is a top view of a memory device in accordance with some embodiments. 
         FIGS. 3B and 3C  are cross-sectional views of the memory device of  FIG. 3A  in accordance with some embodiments. 
         FIG. 3D  is an enlarged view of  FIG. 3B  in accordance with some embodiments. 
         FIGS. 4A to 11C  illustrate a method in various stages of fabricating the memory device in accordance with some embodiments of the present disclosure. 
         FIGS. 12A and 12B  illustrate simulation results of memory devices in accordance with some embodiments of the present disclosure. 
         FIG. 13  is a method of manufacturing a memory device in accordance with some embodiments of the present disclosure. 
         FIG. 14  is a block diagram in accordance with some embodiments of the present disclosure. 
         FIG. 15  is a memory device in accordance with some embodiments of the present disclosure. 
         FIGS. 16A and 16B  a memory device in accordance with some embodiments of the present disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. 
     Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature&#39;s relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. 
     The fins may be patterned by any suitable method. For example, the fins may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fins. 
     The present invention includes an embodiment of a one-time programmable (OTP) memory cell. Herein, it may be that the OTP memory cell can be electronically programmed with data only once; and even though power is no longer supplied, programmed data in the OTP memory cell is retained. 
       FIG. 1  is a schematic circuit of a memory device in accordance with some embodiments. As depicted in  FIG. 1 , a memory device includes a plurality of OTP memory cells C 1 , C 2 , C 3 , C 4 , C 5 , and C 6 , a plurality of the word lines WLP 0 , WLR 0 , WLR 1 , WLP 1 , and a plurality of the bit lines BL 1 , BL 2 , BL 3 . The word lines WLP 0 , WLR 0 , WLRI, and WLP 1  are arranged in X-direction, and each of the word lines WLP 0 , WLR 0 , WLR 1 , and WLP 1  extends along Y-direction. The bit lines BL 1 , BL 2 , BL 3  are arranged in Y-direction, and each of the bit lines BL 1 , BL 2 , BL 3  extends along X-direction. 
     In some embodiments, each of the OTP memory cells C 1 -C 6  includes a first transistor T 0  and a second transistor T 1 . With respect to the OTP memory cell C 1 , a gate terminal of the first transistor T 0  is electrically coupled to the word line WLP 0 , and a gate terminal of the second transistor T 1  is electrically coupled to the word line WLR 0 . A source/drain terminal of the first transistor T 0  is floated, and the other source/drain terminal of the first transistor T 0  is electrically coupled to a resistance node A. Herein, since the one source/drain terminal of the first transistor T 0  does not have any effect on storing and reading data in the OTP memory cell C 1 , the one source/drain terminal of the first transistor T 0  is floated. One source/drain terminal of the second transistor T 1  is also coupled to the resistance node A, and the other source/drain terminal of the second transistor T 1  is coupled to a bit line BL 1 . In some embodiments, the source/drain terminal of the first transistor T 0  is electrically coupled to the source/drain terminal of the second transistor T 1 . 
     With respect to the OTP memory cell C 2 , a gate terminal of the first transistor T 0  is electrically coupled to the word line WLP 1 , and a gate terminal of the second transistor T 1  is electrically coupled to the word line WLR 1 . A source/drain terminal of the first transistor T 0  is floated, and the other source/drain terminal of the first transistor T 0  is electrically coupled to a resistance node A. Herein, since the one source/drain terminal of the first transistor T 0  does not have any effect on storing and reading data in the OTP memory cell C 1 , the one source/drain terminal of the first MOS transistor is floated. One source/drain terminal of the second transistor T 1  is also coupled to the resistance node A, and the other source/drain terminal of the second transistor T 1  is coupled to a bit line BL 1 . In some embodiments, the source/drain terminal of the first transistor T 0  is electrically coupled to the source/drain terminal of the second transistor T 1 . In some embodiments, the OTP memory cells C 1  and C 2  share the same bit line BL 1 . 
     The OTP memory cell C 3 -C 6  are similar to the OTP memory cells C 1  and C 2  as described above, and thus relevant details will not be repeated for brevity. 
     Generally, a gate of a transistor is formed by laminating conductive layers on an insulating layer. In a programming operation, an insulating layer of the gate of the first transistor T 0  may be destroyed. The second transistor T 1  serves as a switching element in order to select the OTP memory cell. 
       FIG. 2A  is a schematic diagram for performing a programming operation to a memory device in accordance with some embodiments.  FIG. 2B  is a schematic diagram for performing a read operation to a memory device in accordance with some embodiments. It is noted that in  FIGS. 2A and 2B , for simplicity, only the OTP memory cell C 2  is illustrated. During the programming operation, the bodies of the first and the second MOS transistors M 0  and M 1  of the OTP memory cell C 2  are coupled to a ground voltage. 
     Reference is made to  FIG. 2A , in which  FIG. 2A  illustrates two different conditions during a programming operation. In condition  1  of  FIG. 2A , the word line WLP 1  is supplied with a high level voltage V 1 , and the world line WLR 1  is coupled to a voltage V 2  having a lower level than the high level voltage V 1 . The bit line BL 1  is coupled to a ground voltage V 3 . Herein, the voltage V 2  is a voltage having a sufficient level to turn on the second transistor T 1 , and the high level voltage V 1  is a voltage having a sufficient level to destroy an insulating layer (e.g., the gate dielectric layer  112  described in  FIGS. 3A-3D ) included in a gate structure (e.g., the gate structures G 3  and/or G 6  described in  FIGS. 3A-3D ) of the first transistor T 0 . In some embodiments, the voltage V 2  may be about 1.2V to about 10V, which is sufficiently high to turn on the second transistor T 1 , and the high level voltage V 1  may be higher than about 1.2V, such as about 5.3V. On the other hand, the ground voltage V 3  can be regarded as having a voltage level of about 0V. 
     Since the gate of second transistor T 1  is supplied with a voltage V 2  that is sufficiently high to turn on the second transistor T 1 , the gate of the second transistor T 1  is turned on, and thus the resistance node A is coupled to the ground voltage V 3 . The gate of the first transistor T 0  is coupled to the high level voltage V 1 . Due to a difference of voltage level supplied to the gate (e.g., voltage V 1 ) and voltage level supplied to the one terminal of the first transistor T 0  (e.g., voltage V 3 ), the insulating layer of the first transistor T 0  is destroyed, i.e., broken down. When the insulating layer is destroyed, a current path is created between the word line WLP 1  and the resistance node A. The resulting circuit can be regarded as having a resistance RF in the current path. Accordingly, in condition  1 , the OTP memory cell C 2  can be referred to as “programmed” after the programming operation, because the insulating layer of the first transistor T 0  is destroyed, i.e., broken down. 
     In this configuration with the first transistor T 0  coupled to the ground voltage V 3 , the insulating layer may not be reliably and/or consistently destroyed. In order to reliably destroy an insulating layer included in the gate structure of first transistor T 0  during a programming operation, the insulating layer can be formed thinner than those of other transistors, such as the second transistor T 1 . Also, to increase programming reliability, the high level voltage V 1  can have a higher voltage level than a predetermined voltage level, where the predetermined voltage level can destroy the insulating layer included in the gate structure of first transistor T 0 . 
     On the other hand, in condition  2  of  FIG. 2A , the word line WLP 1  is supplied with the high level voltage V 1 , and the world line WLR 1  is coupled to the voltage V 2  having a lower level than the high level voltage V 1 . The bit line BL 1  is coupled to a voltage V 3 ′. Here, the voltage V 3 ′ has a higher voltage level than the ground voltage V 3  as described in condition  1  of  FIG. 2A . For example, the voltage V 3 ′ may be about 1.2V, which is higher than the ground voltage V 3  (e.g., about 0V). In some embodiments, the voltage V 3 ′ has substantially the same value as the voltage V 2 , such that the voltage difference between the gate terminal of the second transistor T 1  and the source region terminal of the second transistor T 1  may be about zero so that the second transistor T 1  is turned off, and the source/drain terminal of the second transistor T 1  connected to the first transistor T 0  is floated. Even though the high level voltage V 1  is applied to the first transistor T 0  through the word line WLP 1 , an electric field will not be applied to the insulating layer of the second transistor T 1  because the source/drain terminal of the first transistor T 0  connected to the second transistor T 1  is floated. In this way, the insulating layer of the first transistor T 0  may not be broken down during the programming operation, the first transistor T 0  remains its original function after the programming operation. Accordingly, in condition  2 , the OTP memory cell C 2  can be referred to as “un-programmed” after the programming operation, because the insulating layer of the first transistor T 0  is not destroyed. 
     Reference is made to  FIG. 2B , in which  FIG. 2B  illustrates two different conditions during a read operation. It is noted that the condition  1  of  FIG. 2B  follows the condition  1  of  FIG. 2A , and the condition  2  of  FIG. 2B  follows the condition  2  of  FIG. 2A . 
     In a read operation, the word line WLP 1  is supplied with a power voltage V 4 , and the word line WLR 1  is coupled to the power voltage V 5 . The bit line BL 1  is precharged with a ground voltage level V 6 . The power voltage V 5  is sufficiently high to turn on the second transistor T 1 . 
     In condition  1  of  FIG. 2A  where the insulating layer included in the gate structure of first transistor T 0  is destroyed (breakdown state), the voltage of the bit line BL 1  may increase, and a current path between the gate of the first transistor T 0  and the bit line BL 1  may increase as well. On the other hand, in condition  2  where the insulating layer included in the gate structure of first transistor T 0  is not destroyed, the voltage level of bit line BL 1  does not rise and therefore retains the precharged voltage level (i.e., ground voltage level V 6 ), and thus there is no current path between the gate of the first transistor T 0  and the bit line BL 1 . Data can be read depending on whether there is current on the bit line BL 1 . For instance, in condition  1 , if the voltage or the current of the bit line BL increases because of the breakdown of the insulating layer of the first transistor T 0 , data ‘1’ can be determined. On the other hand, if the voltage or the current of the bit line BL does not rise, data ‘0’ can be determined. That is, if the insulating layer breaks down, the bit line BL 1  may have a logic level of ‘1’; if the insulating layer does not break down, the bit line BL 1  may have a logic level of ‘0’. 
       FIG. 3A  is a top view of a memory device  10  in accordance with some embodiments.  FIGS. 3B to 3C  are cross-sectional views of the memory device of  FIG. 3A  in accordance with some embodiments, in which  FIGS. 3B and 3C  are cross-sectional views taken along line B-B and line C-C of  FIG. 3A .  FIG. 3D  is an enlarged view of  FIG. 3B . It is noted that some elements of  FIGS. 3B and 3C  are not illustrated in  FIG. 3A  for brevity. It is noted that the memory device  10  described in  FIGS. 3A to 3C  corresponds to the circuit as described in  FIG. 1 . 
     The memory device  10  includes a substrate  100  having a plurality of protrusion portions  100 P. In some embodiments, the substrate  100  may be a semiconductor material and may include known structures including a graded layer or a buried oxide, for example. In some embodiments, the substrate  100  includes bulk silicon that may be undoped or doped (e.g., p-type, n-type, or a combination thereof). Other materials that are suitable for semiconductor device formation may be used. Other materials, such as germanium, quartz, sapphire, and glass could alternatively be used for the substrate  100 . Alternatively, the silicon substrate  100  may be an active layer of a semiconductor-on-insulator (SOI) substrate or a multi-layered structure such as a silicon-germanium layer formed on a bulk silicon layer. 
     A plurality of channel regions A 1 , A 2 , and A 3  are disposed over the substrate  100 . In some embodiments, each of the channel regions A 1 , A 2 , and A 3  includes a plurality of first semiconductor layers  101  and second semiconductor layers  102 , in which the first semiconductor layers  101  and second semiconductor layers  102  are stacked in an alternate manner, such that a second semiconductor layer  102  is interposed between two first semiconductor layers  101 , and a first semiconductor layer  101  is interposed between two second semiconductor layers  102 . The first semiconductor layers  101  and the second semiconductor layers  102  have different materials and/or components. In some embodiments, the first semiconductor layers  101  are made of silicon germanium (SiGe), and the second semiconductor layers  102  are made of silicon (Si). In some other embodiments, the first semiconductor layers  101  and the second semiconductor layers  102  are made of SiGe, while the Ge concentration of the second semiconductor layers  102  is lower than the Ge concentration of the first semiconductor layers  101 . For example, the first semiconductor layers  101  are Si x Ge 1-x  and the second semiconductor layers  102  are Si y Ge 1-y , in which where x&lt;y. In some embodiments, the second semiconductor layers  102  of the channel regions A 1 , A 2 , and A 3  are in contact with respective protrusion portions  100 P of the substrate  100 . 
     The channel regions A 1 , A 2 , and A 3  and are laterally surrounded by an isolation structure  106  formed of dielectric material. The isolation structure  106  may be a shallow trench isolation (STI) structure, a deep trench isolation (DTI) structure, another suitable isolation structure(s), a combination of the foregoing, or the like. In some embodiments where the STI structure  106  is made of oxide (e.g., silicon oxide), the channel regions A 1 , A 2 , A 3  can be interchangeably referred to as oxide defined (OD) regions. In some embodiments, a liner  107  is disposed between the channel regions A 1 , A 2 , and A 3  and the STI structure  106 . In some embodiments, the liner  107  is made from SiN or other suitable materials. The isolation structure  106  and the liner  107  are made of different materials. In greater detail, the liner  107  conformally lines and in contact with the protrusion portions  100 P of the substrate  100 . 
     A plurality of gate structures G 1 , G 2 , G 3 , G 4 , G 5 , G 6 , G 7 , and G 8  are disposed over the substrate  100 . In some embodiments, the gate structures G 2  to G 7  cross the channel regions A 1 , A 2 , A 3  along a direction perpendicular to a lengthwise direction of the channel regions A 1 , A 2 , A 3 . That is, the channel regions A 1 , A 2 , A 3  share the same gate structures G 2  to G 7 . In some embodiments, each of the gate structures G 1 -G 8  includes a gate dielectric layer  112 , a work function metal layer  114 , and a filling metal  116 . 
     In some embodiments, the gate dielectric layers  112  of gate structures G 1 -G 8  may be made of high-k dielectric materials, such as metal oxides, transition metal-oxides, or the like. Examples of the high-k dielectric material include, but are not limited to, hafnium oxide (HfO 2 ), hafnium silicon oxide (HfSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), zirconium oxide, titanium oxide, aluminum oxide, hafnium dioxide-alumina (HfO 2 —Al 2 O 3 ) alloy, or other applicable dielectric materials. In some embodiments, the gate dielectric layers  112  are oxide layers. The gate dielectric layers  112  may be formed by a deposition processes, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), plasma enhanced CVD (PECVD) or other suitable techniques. In some embodiments, the gate dielectric layers  112  of the gate structures G 3  and G 6  are thinner than the gate dielectric layers  112  of the gate structures G 4  and G 5 , as the gate dielectric layers  112  of the gate structures G 3  and G 6  may act as the insulting layer of the first transistors T 0  described in  FIGS. 1 to 2B . 
     In some embodiments, the work function metal layers  114  of the gate structures G 1 -G 8  may be an n-type or p-type work function layers. Exemplary p-type work function metals include TiN, TaN, Ru, Mo, Al, WN, ZrSi 2 , MoSi 2 , TaSi 2 , NiSi 2 , WN, other suitable p-type work function materials, or combinations thereof. Exemplary n-type work function metals include Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable n-type work function materials, or combinations thereof. The work function layer may include a plurality of layers. The work function metal layers  114  can be formed by suitable process, such as ALD, CVD, PVD, remote plasma CVD (RPCVD), plasma enhanced CVD (PECVD), metal organic CVD (MOCVD), sputtering, plating, other suitable processes, or combinations thereof. 
     In some embodiments, the filling metals  116  of gate structures G 1 -G 8  may include tungsten (W). In some other embodiments, the filling metals  116  include aluminum (Al), copper (Cu) or other suitable conductive material. The filling metals  116  can be formed by suitable process, such as ALD, CVD, PVD, remote plasma CVD (RPCVD), plasma enhanced CVD (PECVD), metal organic CVD (MOCVD), sputtering, plating, other suitable processes, or combinations thereof. 
     A plurality of gate spacers  120  are disposed on opposite sidewalls of the gate structures G 1 -G 8 . In some embodiments, the gate spacers  120  may include SiO 2 , Si 3 N 4 , SiO x N y , SiC, SiCN films, SiOC, SiOCN films, and/or combinations thereof. 
     A plurality of source/drain structures SD 1 , SD 2 , SD 3 , SD 4 , and SD 5  are disposed in the channel regions A 1 , A 2 , and A 3  over the substrate  100 . As an example of  FIG. 3C , the source/drain structures SD 1  and SD 2  are disposed on opposite sides of the gate structure G 3 , the source/drain structures SD 2  and SD 3  are disposed on opposite sides of the gate structure G 4 , the source/drain structures SD 3  and SD 4  are disposed on opposite sides of the gate structure G 5 , and the source/drain structures SD 4  and SD 5  are disposed on opposite sides of the gate structure G 6 , respectively. In some embodiments, the source/drain structures SD 1 -SD 5  may be may be formed by performing an epitaxial growth process that provides an epitaxy material over the substrate  100 , and thus the source/drain structures SD 1 -SD 5  can also be interchangeably referred to as epitaxy structures SD 1 -SD 5  in this content. In various embodiments, the source/drain structures SD 1 -SD 5  may include Ge, Si, GaAs, AlGaAs, SiGe, GaAsP, SiP, or other suitable material. 
     The gate structure G 3 , the source/drain structures SD 1  and SD 2 , and the channel region A 1  form the first transistor T 0  of the OTP memory cell C 1 , and the gate structure G 4 , the source/drain structures SD 2  and SD 3 , and the channel region A 1  form the second transistor T 1  of the OTP memory cell C 1 . Similarly, the gate structure G 6 , the source/drain structures SD 4  and SD 5 , and the channel region A 1  form the first transistor T 0  of the OTP memory cell C 2 , and the gate structure G 5 , the source/drain structures SD 3  and SD 4 , and the channel region A 1  form the second transistor T 1  of the OTP memory cell C 2 . The OTP memory cells C 3 -C 6  of  FIG. 1  have similar structures as those of the OTP memory cells C 1  and C 2  herein, and thus relevant details are omitted for brevity. 
     As mentioned above with respect to  FIG. 1 , in some embodiments, the insulating layer (e.g., the dielectric layer  112 ) of gate structure of first transistor T 0  can be formed thinner than those of other transistors, such as the second transistor T 1 . Accordingly, in some embodiments, the dielectric layers  112  of the gate structures G 3  and G 6  may be thinner than the dielectric layers  112  of the gate structures G 4  and G 5 . 
     Reference is made to  FIG. 3D , in which  FIG. 3D  illustrates an enlarged view of the channel regions A 1  and the gate structure G 3  crossing the channel regions A 1 . It is understood that the channel regions A 2 , A 3  and the respective gate structures G 2 , G 4 , G 5 , G 6  crossing the channel regions A 2 , A 3  have similar structural details, and are omitted for brevity. 
     In  FIG. 3D , the first semiconductor layers  101  have a width W 1 , and the second semiconductor layers  102  have a width W 2 , in which width W 1  is lower than width W 2 . That is, in a cross-section along the lengthwise direction of the gate structure G 3 , the first semiconductor layers  101  are narrower than the second semiconductor layers  102 . As a result, portions of the gate structure G 3  extend to regions that between two adjacent second semiconductor layers  102 . In some embodiments, the gate structures G 3  is in contact with top surfaces, sidewalls, and bottom surfaces of the second semiconductor layers  102 , and in contact with sidewalls of the first semiconductor layers  101 . In some embodiments, top surface and bottom surfaces of the first semiconductor layers  101  are in contact with the second semiconductor layers  102  and the protrusion portion  100 P of the substrate  100 . In some embodiments, the gate dielectric layer  112 , the work function metal layer  114 , and the filling metal  116  of the gate structure G 3  are directly between the second semiconductor layers  102  and/or directly between the bottommost second semiconductor layer  102  and the protrusion portion  100 P of the substrate  100 . According to some embodiments, the combination of the first semiconductor layers  101  and the second semiconductor layers  102  can be referred to as a “fin structure.” On the other hand, because the second semiconductor layers  102  are suspended over the first semiconductor layers  101  and form a sheet-like structure, the second semiconductor layers  102  can also be referred to as “nanosheets” in this content. 
     In some embodiments of the present disclosure, because the channel region A 1  includes “nanosheet” second semiconductor layers  102 , the contact area between the gate structure G 3  and the channel region A 1  is increased, which in turn will improve the electron mobility, and thus will increase the saturation current I sat  of the transistors of the memory device  10  (such as the transistors T 0  and T 1  discussed in  FIG. 1 ). On the other hand, because the gate dielectric layer  112  of the gate structure G 3  contacts corners of the first semiconductor layers  101  and corners of the second semiconductor layers  102 , the gate dielectric layer  112  may cause high electric fields at these corners due to “point discharge effect.” The electric fields may contribute to the voltage for destroying the dielectric layers of the transistors of memory device  10  (such as the transistors T 0  discussed in  FIG. 1 ). Accordingly, the breakdown voltage of the transistors of memory device  10  can be reduced, and thus the power of the memory device may also be reduced. 
     As mentioned above, the first semiconductor layers  101  have a width W 1 , and the second semiconductor layers  102  have a width W 2 , in which width W 1  is lower than width W 2 . In some embodiments, the width W 1  is in a range from about 2 nm to about 15 nm, and the width W 2  is in a range from about 6 nm to about 20 nm. In some embodiments, the ratio of width W 1  to width W 2  is in a range from about 1:45 to about 1:9. If the ratio is too large (such as much larger than 1:45), this indicates the width W 1  of the first semiconductor layers  101  is too large in some instances, which will reduce contact area between the gate structure G 3  and the second semiconductor layers  102 , and will result in an unsatisfied device performance. If the ratio is too small (such as much lower than 1:45), the gate dielectric layers  112  would not provide enough electric field to lower the breakdown voltage. 
     Referring back to  FIGS. 3A to 3C , an interlayer dielectric (ILD) layer  130  is disposed over the substrate  100 , over the source/drain structures SD 1 -SD 5 , and surrounding the gate structures G 1 -G 8 . In some embodiments, the ILD layer  130  may include silicon oxide, silicon nitride, silicon oxynitride, tetraethoxysilane (TEOS), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), low-k dielectric material, and/or other suitable dielectric materials. Examples of low-k dielectric materials include, but are not limited to, fluorinated silica glass (FSG), carbon doped silicon oxide, amorphous fluorinated carbon, parylene, bis-benzocyclobutenes (BCB), or polyimide. The ILD layer  130  may be formed using, for example, CVD, ALD, spin-on-glass (SOG) or other suitable techniques. 
     An etch stop layer (ESL)  135 , an ILD layer  140 , a etch stop layer (ESL)  145 , and an ILD layer  150  are disposed in sequence over the gate structures G 1 -G 8  and the ILD layer  130 . The materials and the formation method of the ILD layers  140  and  150  are similar to those of the ILD layer  130  described above. The ESLs  135  and  145  may include materials different from the ILD layers  130 ,  140 , and  150 . In some embodiments, the ESLs  135  and  145  include silicon nitride, silicon oxynitride or other suitable materials. The ESLs  135  and  145  can be formed using, for example, plasma enhanced CVD, low pressure CVD, ALD or other suitable techniques. 
     Reference is made to  FIGS. 3A and 3B . A via V WLP1  extends through the ILD layer  150 , the ESL  145 , and the ILD layer  140 , and contacts the metal gate structure G 3 . The material and the formation method of via V WLP1  are similar to those of the via V BL1 . A word line WLP 1  overlies the ILD layer  150  and contacts the V WLP1 . The material and the formation method of word line WLP 1  are similar to those of the bit line BL 1 . 
     Referring to  FIGS. 3A and 3C , a source/drain contact  160  extends through the ILD layer  140 , the ESL  135 , and the ILD layer  130  and contacts the source/drain structure SD 3 . In some embodiments, the source/drain contact  160  may include a liner and a filling metal. The liner is between filling metal and the underlying source/drain structure SD 3 . In some embodiments, the liner assists with the deposition of filling metal and helps to reduce diffusion of a material of filling metal through the gate spacers  120 . In some embodiments, the liner includes titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or another suitable material. The filling metal includes a conductive material, such tungsten (W), copper (Cu), aluminum (Al), ruthenium (Ru), cobalt (Co), molybdenum (Mo), nickel (Ni), or other suitable conductive material. In some embodiments, a silicide layer may be disposed between the source/drain contact  160  and the source/drain structure SD 3 . 
     A via V BL1  extends through the ILD layer  150  and the ESL  145 , and contacts the source/drain contact  160 . In some embodiments, the via V BL1  includes a conductive material, such tungsten (W). Other conductive materials may be used for the via V BL1 , such as copper (Cu), aluminum (Al), ruthenium (Ru), cobalt (Co), molybdenum (Mo), nickel (Ni), or the like. The via V BL1  can be formed by suitable process, such as ALD, CVD, PVD, remote plasma CVD (RPCVD), plasma enhanced CVD (PECVD), metal organic CVD (MOCVD), sputtering, plating, other suitable processes, or combinations thereof. 
     A bit line BL 1  overlies the ILD layer  150  and contacts the via V BL2 . In some embodiments, the bit line BL 1  may include copper (Cu), aluminum (Al), ruthenium (Ru), cobalt (Co), molybdenum (Mo), nickel (Ni), tungsten (W), or the like. The bit line BL 1  can be formed by suitable process, such as ALD, CVD, PVD, remote plasma CVD (RPCVD), plasma enhanced CVD (PECVD), metal organic CVD (MOCVD), sputtering, plating, other suitable processes, or combinations thereof. 
       FIGS. 4A to 12B  illustrate a method in various stages of fabricating the memory device  10  as described in  FIGS. 3A to 3D  in accordance with some embodiments of the present disclosure. 
     Reference is made to  FIGS. 4A to 4C , in which  FIG. 4A  is a top view of the memory device  10 ,  FIG. 4B  is a cross-sectional view along line B-B of  FIG. 4A , and  FIG. 4C  is a cross-sectional view along line C-C of  FIG. 4A . Shown there is an initial structure, the initial structure includes a substrate  100 , a plurality of channel regions A 1 , A 2 , and A 3  over the substrate  100 , and a liner  107  and an isolation structure  106  laterally surrounding the channel regions A 1 , A 2 , and A 3 . 
     In some embodiments, the channel regions A 1 , A 2 , and A 3  may be formed by, for example, alternately depositing first semiconductor layers  101  and the second semiconductor layers  102  over the substrate  100 , forming a patterned mask (not shown) that defines positions of the channel regions A 1 , A 2 , and A 3  over the topmost second semiconductor layer  102 , followed by an etching process to remove portions of the first semiconductor layers  101 , the second semiconductor layers  102 , and the substrate  100 . The remaining portions of the first semiconductor layers  101  and the second semiconductor layers  102  form the channel regions A 1 , A 2 , and A 3 . In some embodiments, the substrate  100  is also etched and thus protrusion portions  100 P are formed over the substrate  100 . In some embodiments, the channel regions A 1 , A 2 , and A 3  and the respective protrusion portions  100 P form a fin-like structure, and thus the channel regions A 1 , A 2 , and A 3  and the respective protrusion portions  100 P can be referred to as “fin structures.” 
     The first semiconductor layers  101  and the second semiconductor layers  102  have different materials and/or components, such that the first semiconductor layers  101  and the second semiconductor layers  102  have different etching rates. In some embodiments, the first semiconductor layers  101  are made from SiGe. The germanium percentage (atomic percentage concentration) of the first semiconductor layers  101  is in the range between about 10 percent and about 20 percent, while higher or lower germanium percentages may be used. It is appreciated, however, that the values recited throughout the description are examples, and may be changed to different values. For example, the first semiconductor layers  101  may be Si 0.8 Ge 0.2  or Si 0.9 Ge 0.1 , the proportion between Si and Ge may vary from embodiments, and the disclosure is not limited thereto. The second semiconductor layers  102  may be pure silicon layers that are free from germanium. The second semiconductor layers  102  may also be substantially pure silicon layers, for example, with a germanium percentage lower than about 1 percent. In some embodiments, the first semiconductor layers  101  have a higher germanium atomic percentage concentration than the second semiconductor layers  102 . In some other embodiments, the second semiconductor layers  102  and the substrate  100  may be made from the same material or different materials. The first semiconductor layers  101  and the second semiconductor layers  102  may be formed by chemical vapor deposition (CVD), molecular beam epitaxy (MBE), or other suitable process(es). In some embodiments, the first semiconductor layers  101  and the second semiconductor layers  102  are formed by an epitaxy growth process, and thus the first semiconductor layers  101  and the second semiconductor layers  102  can also be referred to as epitaxial layers in this content. 
     The liner  107  and the isolation structure  106  may be formed by, for example, depositing a liner material and an isolation material over the substrate  100  and the channel regions A 1 , A 2 , and A 3 , performing a CMP process to remove excessive liner material and isolation material until top surface of the second semiconductor layer is exposed, followed by an etching back process to lower top surfaces of the liner material and isolation material. The remaining portions of the liner material and isolation material are referred to as liner  107  and isolation structure  106 , respectively. 
     Reference is made to  FIGS. 5A to 5C , in which  FIG. 5A  is a top view of the memory device  10 ,  FIG. 5B  is a cross-sectional view along line B-B of  FIG. 5A , and  FIG. 5C  is a cross-sectional view along line C-C of  FIG. 4A . A plurality of dummy gate structures DG 1 , DG 2 , DG 3 , DG 4 , DG 5 , DG 6 , DG 7 , and DG 8  are formed over the substrate  100 . In some embodiments, the dummy gate structures DG 2 -DG 7  cross the channel regions A 1 -A 3 , while the dummy gate structures D 1  and D 8  do not cross the channel regions A 1 -A 3 . Each of the dummy gate structures DG 1 -DG 8  includes a gate dielectric layer  162  and a dummy gate  164 . In some embodiments, the dummy gate structures DG 1 -DG 8  may be formed by, for example, depositing a gate dielectric material and a dummy gate material over the substrate  100 , followed by a patterning process to pattern the gate dielectric material and the dummy gate material to form the dummy gate structures DG 1 -DG 8 . 
     The gate dielectric layer  162  may be, for example, silicon oxide, silicon nitride, a combination thereof, or the like, and may be deposited or thermally grown according to acceptable techniques. The gate dielectric layer  162  may be formed by suitable process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any suitable process. The dummy gate layer  164  may include polycrystalline-silicon (poly-Si) or poly-crystalline silicon-germanium (poly-SiGe). Further, the dummy gate layer  164  may be doped poly-silicon with uniform or non-uniform doping. The dummy gate layer  164  may be formed by suitable process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any suitable process. 
     A plurality of gate spacers  120  are formed on opposite sidewalls of the dummy gate structures DG 1 -DG 8 . The gate spacers  120  may be formed by, for example, depositing a spacer layer blanket over the dummy gate structures DG 1 -DG 8 , followed by an etching process to remove horizontal portions of the spacer layer, such that vertical portions of the spacer layer remain on sidewalls of the dummy gate structures DG 1 -DG 8 . 
     Reference is made to  FIGS. 6A and 6B , in which  FIGS. 6A and 6B  follow  FIGS. 5B and 5C , respectively. A plurality of source/drain structures SD 1 , SD 2 , SD 3 , SD 4 , and SD 5  are formed in the channel regions A 1 -A 3 . As an example in  FIG. 6B , the channel region A 1  exposed by the dummy gate structures DG 1 -DG 8  and the gate spacers  120  is recessed by suitable process, such as etching. Afterwards, the source/drain structures SD 1 -SD 5  are formed respectively over the exposed surfaces of the remaining channel region A 1 . The source/drain structures SD 1 -SD 5  may be formed by performing an epitaxial growth process that grows an epitaxy semiconductor material from the channel region A 1 . The source/drain structures SD 1 -SD 5  are doped with an n-type impurity (e.g., phosphorous) or a p-type impurity (e.g., boron), depending on the conductivity-type of the respective resulting transistors. 
     An interlayer dielectric layer (ILD)  130  is formed adjacent to the gate spacers  120 . For example, a dielectric layer is deposited blanket over the substrate  100  and filling the spaces between the gate spacers  120 , followed by a CMP process to remove excessive material of the dielectric layer until the top surfaces of the dummy gate structures DG 1 -DG 8  are exposed. 
     Reference is made to  FIGS. 7A and 7B , in which  FIGS. 7A and 7B  follow  FIGS. 6A and 6B , respectively. The dummy gate structures DG 1 -DG 8  are removed to form gate trenches TR 1  between gate spacers  120 . In some embodiments, the dummy gate structures DG 1 -DG 8  may be removed by suitable etching process, such as dry etching, wet etching, or combinations thereof. After the etching process, the first semiconductor layers  101  and the second semiconductor layers  102  of the channel regions A 1 , A 2 , and A 3  are exposed by the gate trenches TR 1  between the gate spacers  120 . 
     Reference is made to  FIGS. 8A and 8B , in which  FIGS. 8A and 8B  follow  FIGS. 7A and 7B , respectively. The first semiconductor layers  101  are narrowed down along a direction perpendicular to the lengthwise direction of the channel regions A 1 , A 2 , and A 3 , as shown in  FIG. 8A . In some embodiments, the first semiconductor layers  101  may be narrowed using an etching process, such as dry etching, wet etching, or combinations thereof. In some embodiments, the first semiconductor layers  101  and the second semiconductor layers  102  include etching selectivity, and thus the first semiconductor layers  101  may be partially removed while the second semiconductor layers  102  remains substantially intact after the etching process. However, the remaining first semiconductor layers  101  are still in contact with the second semiconductor layers  102  over and below the remaining first semiconductor layers  101 . That is, the etchant does not laterally etch through the semiconductor layers  101 . In some embodiments, the etching process uses halogen-containing etchants. In some embodiments, the etchant includes fluorine-containing fluid, such as fluorine and/or hydrogen fluoride. 
     As a result, gaps GP are formed between adjacent second semiconductor layers  102 , in which the bottommost gaps GP are formed between a second semiconductor layer  102  and the protrusion portions  100 P of the substrate  100 . In some embodiments, the second semiconductor layers  102  above and below a first semiconductor layer  101  define the top surface and the bottom surface of the gaps GP, and the first semiconductor layer  101  define the sidewalls of the gaps GP. In some embodiments, two gaps GP are formed on opposite sides of the first semiconductor layer  101 , as shown in  FIG. 8A . 
     On the other hand, along the lengthwise direction of the channel regions A 1 , A 2 , and A 3  (see  FIG. 8B ), the width of the first semiconductor layers  101  is substantially the same after the etching process. This is because along the lengthwise direction of the channel regions A 1 , A 2 , and A 3 , sidewalls of the first semiconductor layers  101  are confined by the source/drain structures SD 1 -SD 5 , and thus etchant is hard to etch the first semiconductor layers  101  along this direction, which results in that the width of the first semiconductor layers  101  is substantially the same after the etching process. In some embodiments, the source/drain structures SD 1 -SD 5  remain in contact with the first semiconductor layers  101  after the etching process. As a result, the lateral width loss of the first semiconductor layers  101  along the direction perpendicular to the lengthwise direction of the channel regions A 1 , A 2 , and A 3  ( FIG. 8A ) is greater than the lateral width loss of the first semiconductor layers  101  along the lengthwise direction of the channel regions A 1 , A 2 , and A 3  ( FIG. 8B ). Accordingly, after the etching process, the width difference between the first semiconductor layers  101  and the second semiconductor layers  102  along the direction perpendicular to the lengthwise direction of the channel regions A 1 , A 2 , and A 3  ( FIG. 8A ) is greater than the width difference between the first semiconductor layers  101  and the second semiconductor layers  102  along the lengthwise direction of the channel regions A 1 , A 2 , and A 3  ( FIG. 8B ). 
     Reference is made to  FIGS. 9A to 9C , in which  FIG. 9A  is a top view of the memory device  10 ,  FIG. 9B  is a cross-sectional view along line B-B of  FIG. 9A , and  FIG. 9C  is a cross-sectional view along line C-C of  FIG. 9A .  FIGS. 9B and 9C  follow  FIGS. 8A and 8B , respectively. Metal gate structures G 1 , G 2 , G 3 , G 4 , G 5 , G 6 , G 7 , and G 8  are formed in the gate trenches TR 1  (see  FIGS. 8A and 8B ), respectively. In some embodiments, each of the gate structures G 1 -G 8  includes a gate dielectric layer  112 , a work function metal layer  114 , and a filling metal  116 . The gate structures G 1 -G 8  may be formed by, for example, depositing a gate dielectric material, a work function metal material, and a conductive material in the gate trenches TR 1 , followed by a CMP process to remove excessive materials of the gate dielectric material, the work function metal material, and the conductive material until the ILD layer  130  is exposed. 
     As shown in  FIG. 9B , the gate structures G 1 -G 8  (gate structure G 3  as an example in  FIG. 9B ) fill the gaps GP between the second semiconductor layers  102 . In some embodiments, the gate dielectric layer  112 , the work function metal layer  114 , and the filling metal  116  of the gate structures G 1 -G 8  are directly filled in the gaps GP, such that the gate dielectric layer  112 , the work function metal layer  114 , and the filling metal  116  are directly between the second semiconductor layers  102 . On the other hand, the gate dielectric layer  112 , the work function metal layer  114 , and the filling metal  116  are directly between the bottommost second semiconductor layers  102  and the protrusion portions  100 P of the substrate  100 . The gate dielectric layer  112  of the gate structures G 1 -G 8  lines the top surfaces, sidewalls, and bottom surfaces of the second semiconductor layers  102 , and lines the sidewalls of the first semiconductor layer  101 . 
     Reference is made to  FIGS. 10A to 10C , in which  FIG. 10A  is a top view of the memory device  10 ,  FIG. 10B  is a cross-sectional view along line B-B of  FIG. 10A , and  FIG. 10C  is a cross-sectional view along line C-C of  FIG. 10A . An etch stop layer (ESL)  135  and an interlayer dielectric layer (ILD)  140  are formed over the gate structures G 1 -G 8 . The ESL  135  can be formed using, for example, plasma enhanced CVD, low pressure CVD, ALD or other suitable techniques. The ILD layer  140  may be formed using, for example, CVD, ALD, spin-on-glass (SOG) or other suitable techniques. 
     A plurality of source/drain contacts  160  are formed in contact with the source/drain structures. As an example of  FIG. 10C , a source/drain contact  160  is formed in contact with the source/drain structure SD 3 . In some embodiments, the source/drain contacts  160  may be formed by, for example, etching the ILD layer  140 , the ESL  135 , and the ILD layer  130  to form openings that expose the source/drain structures, filling conductive material in the openings, followed by a CMP process to remove excessive material of the conductive material until a top surface of the ILD layer  140  is exposed. 
     An etch stop layer (ESL)  145  and an interlayer dielectric layer (ILD)  150  are formed over the ILD layer  140 . The ESL  135  can be formed using, for example, plasma enhanced CVD, low pressure CVD, ALD or other suitable techniques. The ILD layer  150  may be formed using, for example, CVD, ALD, spin-on-glass (SOG) or other suitable techniques. 
     A plurality of vias V BL1 , V BL2 , V BL3 , V WLR0 , V WLP0 , V WLR1 , and V WLP1  are formed. For example, the vias V BL1 , V BL2 , V BL3 , V WLR0 , V WLP0 , V WLR1 , and V WLP1  may be formed by, etching the ESL  135 , ILD layer  140 , ESL  145 , and ILD  150  to from openings, forming a conductive layer in the openings, followed by a CMP process to remove excessive conductive layer until top surface of the ILD  150  is exposed. In some embodiments, the vias V WLR0 , V WLP0 , V WLR1 , and V WLP1  are landed on the gate structures G 4 , G 3 , G 5 , and G 6 , respectively. As an example in  FIG. 10B , the via V WLP0  contacts the gate structure G 3 . In some embodiments, vias V BL1 , V BL2 , V BL3  are landed on the source/drain contacts  160  over the channel regions A 1 , A 2 , and A 3 , respectively. As an example in  FIG. 10C , the via V BL1  contacts the source/drain contact  160  over the channel region A 1 . 
     Reference is made to  FIGS. 11A to 11C , in which  FIG. 11A  is a top view of the memory device  10 ,  FIG. 11B  is a cross-sectional view along line B-B of  FIG. 11A , and  FIG. 11C  is a cross-sectional view along line C-C of  FIG. 11A . Bit lines BL 1 , BL 2 , and BL 3  and word lines WLP 0 , WLR 0 , WLP 1 , and WLR 1  are formed over the ILD layer  150 . For example, a conductive layer is deposited over the ILD layer  150 , and the conductive layer is patterned according to a predetermined pattern. As a result, the portions of the remaining conductive layer over the vias V BL1 , V BL2 , V BL3 , V WLP0 , V WLR0 , V WLP1 , and V WLR1  are referred to as the bit lines BL 1 , BL 2 , and BL 3  and word lines WLP 0 , WLR 0 , WLP 1 , and WLR 1 , respectively. 
       FIG. 12A  illustrates simulation results of reduction of power by introducing nanosheet structure into a memory device in accordance with some embodiments.  FIG. 12B  illustrates simulation results of improvement of saturation current I sat  by introducing nanosheet structure into a memory device in accordance with some embodiments. 
     In  FIGS. 12A and 12B , Conditions A and B illustrate simulation results of the a memory device discussed above, in which Condition A is a simulation result of a memory device without the nanosheet structure discussed above, and Condition B is a simulation result of a memory device with the nanosheet structure discussed above. As shown in  FIG. 12A , comparing Condition A with Condition B, it is clear that forming the nanosheet structure in a memory device can reduce power of the memory device. In some embodiments where the nanosheet structure is introduced in the memory device, the power of the memory device can be reduce about 40%, and the breakdown voltage of the transistors of the memory device (such as the transistors T 0  discussed in  FIG. 1 ) can be reduced about 0.2V. On the other hand, as shown in  FIG. 12B , it is clear that forming the nanosheet structure in a memory device can improve saturation current I sat  of the transistors of the memory device. In some embodiments where the nanosheet structure is introduced in the memory device, the saturation current I sat  of the transistors of the memory device can be increased about 30%. 
       FIG. 13  illustrates a method M 1  of manufacturing a memory device in accordance with some embodiments of the present disclosure. Although the method  1000  is illustrated and/or described as a series of acts or events, it will be appreciated that the method is not limited to the illustrated ordering or acts. Thus, in some embodiments, the acts may be carried out in different orders than illustrated, and/or may be carried out concurrently. Further, in some embodiments, the illustrated acts or events may be subdivided into multiple acts or events, which may be carried out at separate times or concurrently with other acts or sub-acts. In some embodiments, some illustrated acts or events may be omitted, and other un-illustrated acts or events may be included. 
     At block S 101 , alternately forming first semiconductor layers and second semiconductor layers over a substrate.  FIGS. 4A to 4C  illustrate schematic views of some embodiments corresponding to act in block S 101 . 
     At block S 102 , forming dummy gate structures over the first semiconductor layers and the second semiconductor layers, and forming gate spacers on opposite sidewalls of the dummy gate structures.  FIGS. 5A to 5C  illustrate schematic views of some embodiments corresponding to act in block S 102 . 
     At block S 103 , forming source/drain structures in the first semiconductor layers and the second semiconductor layers, and forming first interlayer dielectric (ILD) layer over the source/drain structures.  FIGS. 6A and 6B  illustrate schematic views of some embodiments corresponding to act in block S 103 . 
     At block S 104 , removing dummy gate structures to form gate trenches between gate spacers.  FIGS. 7A and 7B  illustrate schematic views of some embodiments corresponding to act in block S 104 . 
     At block S 105 , etching the first semiconductor layers to narrow down the first semiconductor layers.  FIGS. 8A and 8B  illustrate schematic views of some embodiments corresponding to act in block S 105 . 
     At block S 106 , forming metal gate structures in the gate trenches.  FIGS. 9A to 9C  illustrate schematic views of some embodiments corresponding to act in block S 106 . 
     At block S 107 , forming a first etching stop layer (ESL), a second ILD layer, a second ESL, and a third ILD layer over the first ILD layer, forming first vias extending through the first ESL, the second ILD layer, the second ESL, and the third ILD layer, and forming second vias extending through the second ILD layer, the second ESL, and the third ILD layer.  FIGS. 10A to 10C  illustrate schematic views of some embodiments corresponding to act in block S 107 . 
     At block S 108 , forming word lines and bit lines over the first and second vias, respectively.  FIGS. 11A to 11C  illustrate schematic views of some embodiments corresponding to act in block S 108 . 
       FIG. 14  is a block diagram of a semiconductor device in accordance with some embodiments of the present disclosure. The semiconductor device includes a main array chip  900 , a word line (WL) driver  910 , a sense amplifier  920  and a high voltage (HV) switch  930  electrically coupled to each other. 
     The main array chip  900  may include a plurality of memory cells and a plurality of word lines and bit lines coupled to the memory cells. For example, the main array chip  900  may be the memory device as discussed in  FIG. 1 , which includes memory cells C 1  to C 6 , word lines WLP 0 , WLR 0 , WLP 1 , WLR 1 , and bit lines BL 1 , BL 2 , BL 3 . Each of the memory cells C 1  to C 6  includes transistors T 0  and T 1 . In some embodiments, the word line (WL) driver  910 , the sense amplifier  920  and the HV switch  930  may include a plurality of transistors to perform desired functions. 
     In some embodiments, input/output (I/O) circuitry of the main array chip  900  allows program/read operation to the memory cells of the main array chip  900 , and is generally coupled to the WL driver  910  and the sense amplifier  910 . In some embodiments, word lines of the main array chip  900  are coupled to the WL driver  910 , and bit lines of the main array chip  900  are coupled to the sense amplifier  910 . 
     During program/read operation to the memory cells of the main array chip  900 , the WL driver  910  may supply voltages to the word lines to adjust (e.g., to raise or lower) the voltage levels of the selected word lines. For example, WL driver  910  may supply voltages to the word lines word lines WLP 0 , WLR 0 , WLP 1 , WLR 1  as discussed in  FIGS. 2A and 2B  above. The HV switch  930  may be an appropriate switching circuitry configured to provide a relatively high voltage signal to the WL driver  910 . During read operation, the sense amplifier  910  detects signal difference between at least two bit lines to distinguish logic high and low states. For example, the sense amplifier  910  may detect signal difference between bit lines BL 1 , BL 2 , BL 3  as discussed in  FIGS. 2A and 2B  above. 
     Reference is made to  FIG. 15 .  FIG. 15  illustrates two transistors T 3  and T 4 , in which the transistor T 3  is disposed in a first region R 1  of the substrate  100 , and the transistor T 4  is disposed in a second region R 2  of the substrate  100 . In some embodiments, the first region R 1  of the substrate  100  may be the main array chip  900  of  FIG. 14 . On the other hand, the second region R 2  may be the WL driver  910 , the sense amplifier  920 , and the HV switch  930  of  FIG. 14 . Stated another way, the transistor T 3  is disposed within the main array chip  900  of  FIG. 14 , while the transistor T 4  is disposed within the WL driver  910 , the sense amplifier  920 , and the HV switch  930  of  FIG. 14 . 
     The transistor T 3  is similar to the transistor discussed in  FIGS. 3A to 11C . For example, the transistor T 3  includes the channel region A 1  and the gate structure G 3  crossing the channel region A 1 . The channel region A 1  includes first semiconductor layers  101  and second semiconductor layers  102  alternately stacked, in which the first semiconductor layers  101  are narrower than the second semiconductor layers  102 . It is noted that the channel region A 1  and the gate structure G 3  of  FIG. 15  can be replaced with the channel regions A 2 , A 3  and the gate structures G 2 , G 4 , G 5 , G 6 , respectively. 
     On the other hand, the transistor T 4  includes a channel region A 4  and a gate structure G 9  crossing the channel region A 9 . The channel region A 4  include a plurality of second semiconductor layers  202  suspended over the substrate  100 , in which the second semiconductor layers  202  are similar or the same as the second semiconductor layers  102  of the transistor T 3 . The gate structure G 9  includes a gate dielectric layer  212 , a work function metal layer  214 , and a filling metal  216 , which are similar or the same as the gate dielectric layer  212 , the work function metal layer  214 , and the filling metal  216  of gate structure G 3  of the transistor T 3 . The transistor T 4  of second region R 2  is different from the transistor T 3  of first region R 1 , in that the channel region A 4  of the transistor T 4  is free from material of the first semiconductor layers  101  of the transistor T 3 . As a result, gate structure G 9  along the lengthwise direction of the gate structure G 9 , the gate structure G 9  entirely surrounds the second semiconductor layers  202 . 
     In some embodiments, the second semiconductor layers  102  of transistor T 3  have a width W 2 , and the second semiconductor layers  202  of transistor T 4  have a width W 3 , in which width W 3  is less than width W 2 . In some embodiments, the transistors T 3  and the transistor T 4  can be formed by the method discussed in  FIGS. 4A to 11C . For example, first and second semiconductor layers are alternately formed over a substrate, etching the first semiconductor layers, and followed by forming a gate structure. In some embodiments, because the width W 3  of the second semiconductor layers  202  is less than width W 2  of the second semiconductor layers  102 , the first semiconductor layers (not shown) will be completely removed during the operation for etching the first semiconductor layers as discussed in  FIGS. 8A and 8B . However, because the width W 2  of the second semiconductor layers  102  is larger, and thus the first semiconductor layers  101  remain between the second semiconductor layers  102  after the etching, as discussed in  FIGS. 8A and 8B . 
     Reference is made to  FIGS. 16A and 16B .  FIGS. 16A and 16B  are memory devices in accordance with some embodiments of the present disclosure. The memory devices of  FIGS. 16A and 16B  are similar to the memory device  10  discussed in  FIGS. 3A to 3D , and thus relevant structural details are omitted for simplicity. 
     In  FIG. 16A , the first semiconductor layers  101  have concave sidewall. This is resulted from the etching process for narrowing down the first semiconductor layers  101 , as discussed in  FIGS. 8A and 8B . Accordingly, the gate structure G 3  and the first semiconductor layers  101  have curved interfaces. 
     In  FIG. 16B , shown there is a first semiconductor layer  101 A, a first semiconductor layer  101 B over the first semiconductor layer  101 A, and a first semiconductor layer  101 C over the first semiconductor layer  101 B, in which first semiconductor layers  101 A,  101 B,  101 C are made of the same material, and are the same as the first semiconductor layers  101  discussed above. The first semiconductor layers  101 A,  101   b , and  101 C have widths W 4 , W 5 , and W 6 , in which width W 4  is greater than width W 5 , and width W 5  is greater than width W 6 . This is resulted from the etching process for narrowing down the first semiconductor layers as discussed in  FIGS. 8A and 8B , because the etchant of the etching process is hard to go deeper and reach the lower first semiconductor layers. 
     According to the aforementioned embodiments, it can be seen that the present disclosure offers advantages in fabricating semiconductor devices. It is understood, however, that other embodiments may offer additional advantages, and not all advantages are necessarily disclosed herein, and that no particular advantage is required for all embodiments. One advantage is that because the channel region includes a nanosheet structure, contact area between the gate structure and the channel region is increased, which in turn will improve the electron mobility, and thus will increase the saturation current I sat  of the transistors of the memory device. Another advantage is that, because the gate dielectric layer of the gate structure may induce high electric fields at corners of the nanosheet structure. The electric fields may contribute to the voltage for destroying the dielectric layers of the transistors of memory device. Accordingly, the breakdown voltage of the transistors of memory device can be reduced, and thus the power of the memory device may also be reduced. 
     In some embodiments of the present disclosure, a memory device includes a substrate, a first transistor and a second transistor, a first word line, a second word line, and a bit line. The first transistor and the second transistor are over the substrate and are electrically connected to each other, in which each of the first and second transistors includes first semiconductor layers and second semiconductor layers alternately stacked over the substrate, a gate structure crossing the first semiconductor layers and the second semiconductor layers, and source/drain structures on opposite sides of the gate structure, in which the first semiconductor layers are in contact with the second semiconductor layers, and a width of the first semiconductor layers is narrower than a width of the second semiconductor layers. The first word line is electrically connected to the gate structure of the first transistor. The second word line is electrically connected to the gate structure of the second transistor. The bit line is electrically connected to a first one of the source/drain structures of the first transistor. 
     In some embodiments of the present disclosure, a memory device includes a substrate, first semiconductor layers and second semiconductor layers, a gate structure, gate spacers, source/drain structures, a word line, and a bit line. The first semiconductor layers and the second semiconductor layers are alternately stacked over the substrate. The gate structure crosses the first semiconductor layers and the second semiconductor layers. The gate spacers are on opposite sidewalls of the gate structure, in which along a direction vertical to a top surface of the substrate, the gate spacers overlap the first semiconductor layers and the second semiconductor layers. The source/drain structures are on opposite sides of the gate structure. The word line is electrically connected to the gate structure. The bit line is electrically connected to one of the source/drain structures. 
     In some embodiments of the present disclosure, a memory device includes a substrate, first semiconductor layers and second semiconductor layers, a gate structure, source/drain structures, a word line, and a bit line. The first semiconductor layers and the second semiconductor layers are alternately stacked over the substrate, in which a width of the first semiconductor layers is narrower than a width of the second semiconductor layers, and each of the first semiconductor layers has concave opposite sidewalls. The gate structure crosses the first semiconductor layers and the second semiconductor layers. The source/drain structures are on opposite sides of the gate structure. The word line is electrically connected to the gate structure. The bit line is electrically connected to one of the source/drain structures. 
     The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.