Patent Publication Number: US-8980718-B2

Title: PMOS transistors and fabrication method

Description:
CROSS-REFERENCES TO RELATED APPLICATIONS 
     This application claims the priority of Chinese patent application No. 201210289305.X, filed on Aug. 14, 2012, the entirety of which is incorporated herein by reference. 
     FIELD OF THE INVENTION 
     The present invention generally relates to the field of semiconductor technology, and more particularly, relates to PMOS transistors and techniques for fabricating high-performance PMOS transistors. 
     BACKGROUND 
     With the continuously shrinking of the size of semiconductor devices, the conventional gate dielectric material made of silicon oxide becomes thinner and thinner, thus problems such as power consumption wasting and heat generation have emerged. These problems may have been solved by the hafnium-based high-K dielectric material and metal gate process. For example, the switching power consumption and the leakage current from source to drain of transistors formed by the new type of 45 nm process which uses the hafnium-based high-K dielectric material and metal gate process are reduced, the leakage current of the gate oxide layer is also reduced, and the switching speed of the transistors is significantly increased. 
     However, the performance of PMOS transistors formed by the existing fabrication processes including the above mentioned hafnium-based high-K dielectric and metal gate process may still need improvements. Therefore, new techniques for fabricating PMOS transistors are needed to improve the performance characteristics of PMOS transistors. The disclosed methods and systems are directed to solve one or more problems set forth above and other problems. 
     BRIEF SUMMARY OF THE DISCLOSURE 
     One aspect of the present disclosure includes a method for fabricating a PMOS transistor. The method includes providing a semiconductor substrate, and forming a dummy gate structure having at least a dummy gate, a high-K dielectric layer, and a sidewall spacer on the semiconductor substrate surrounding the dummy gate structure. The method also includes forming a source region and a drain region in the semiconductor substrate at both sides of the dummy gate structure by an ion implantation process, and performing a first annealing process to enhance the ion diffusion. Further, the method includes forming an interlayer dielectric layer leveling with the surface of the dummy gate, and forming a trench by removing the dummy gate. Further, the method also includes performing a second annealing process, and forming a metal gate in the trench. 
     Another aspect of the present disclosure includes a PMOS transistor. The PMOS transistor includes a semiconductor substrate, a source region, a drain region, and a gate structure having at least a high-K dielectric layer and a metal gate. The PMOS transistor also includes a sidewall spacer covering the gate structure, and an interlayer dielectric layer leveling with the metal gate. Further, the PMOS transistor includes a metal silicide layer on the source region and the drain region. 
     Other aspects of the present disclosure can be understood by those skilled in the art in light of the description, the claims, and the drawings of the present disclosure. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  illustrates an exemplary fabrication process of a PMOS transistor consistent with the disclosed embodiments; and 
         FIGS. 2-18  illustrate semiconductor structures corresponding to certain stages of an exemplary fabrication process of a PMOS transistor consistent with the disclosed embodiments. 
     
    
    
     DETAILED DESCRIPTION 
     Reference will now be made in detail to exemplary embodiments of the invention, which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts. 
     When forming PMOS transistors using high-K dielectric materials, the performance of the PMOS transistors may be impacted by the oxygen vacancies in the high-K dielectric material. If the high-K dielectric material contains oxygen, it may be unstable. On one hand, the high-K dielectric material may be formed by an atomic layer deposition(ALD) process, the ALD process may cause the high-K dielectric material containing oxygen to lose certain amount of oxygen molecules during the deposition process, and cause the obtained high-K dielectric layer to have an oxygen deficiency phenomenon, so-called oxygen vacancy. On the other hand, after an ion implantation process to form a source region and a drain region, a thermal annealing process may be performed to cause implanted ions to diffuse. Because the temperature of the thermal annealing process is relatively high, for example, the temperature may be in a range of approximately 1000° C.˜1100° C., the thermal annealing process may cause the oxygen molecules to decompose and escape so as to form oxygen vacancies in the obtained high-K dielectric layer. The oxygen vacancy phenomenon may cause decreased effective working function of the PMOS transistor and higher threshold voltage of the PMOS transistor. Thus, the performance of PMOS transistors would be affected. 
       FIG. 1  illustrates an exemplary fabrication process of a PMOS transistor, and  FIGS. 2-18  illustrate the semiconductor structures corresponding to certain stages of the exemplary fabrication process consistent with the disclosed embodiments. 
     As shown in  FIG. 1 , at the beginning of the fabrication process, a semiconductor substrate is provided (S 1 ).  FIG. 2  shows a corresponding semiconductor structure. 
     As shown in  FIG. 2 , a semiconductor substrate  100  is provided. The semiconductor substrate  100  may include any appropriate type of semiconductor material, such as single crystal silicon, poly silicon, amorphous silicon, silicon germanium, carborundum, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, gallium antimonide, alloy semiconductor, epitaxially grown materials, or silicon on insulator (SOI). In one embodiment, the semiconductor substrate  100  is silicon or SOI. The semiconductor substrate  100  may also provide a base for subsequent processes and structures. 
     Returning to  FIG. 1 , after providing the semiconductor substrate  100 , a dummy gate structure may be formed on the semiconductor substrate  100  (S 2 ).  FIGS. 3-5  show corresponding semiconductor structures. 
     As shown in  FIG. 5 , a dummy gate structure is formed on the semiconductor substrate  100 . The dummy gate structure may have a high-K dielectric layer  202  on the semiconductor substrate  100 , a dummy gate  204  on the high-K dielectric layer  202 , and a sidewall spacer  205  surrounding the high-K dielectric layer  202  and the dummy gate  204 . 
     Various methods may be used to form the dummy gate structure. In one embodiment, as shown in  FIG. 3 , the method for forming the dummy gate structure sequentially includes: forming a high-K dielectric material layer  202   a  on the semiconductor substrate  100 ; and forming a dummy gate material layer  204   a  on the high-k dielectric material layer  202   a.    
     Various fabrication processes may be used to form the high-K dielectric material layer  202   a  and the dummy gate material layer  204   a , such a chemical vapor deposition process (CVD), a physical vapor deposition process (PVD), or any other appropriate process. The high-K dielectric material layer  202   a  may be made of any appropriate dielectric material, such as hafnium dioxide, hafnium silicate, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicate, tantalum oxide, titanium oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, lead scandium tantalite, or lead zinc niobate, etc. In one embodiment, the high-K dielectric material may be at least one of hafnium dioxide and zirconium oxide. The dummy gate material layer  204   a  may be made of any appropriate material, such as poly silicon (so called dummy poly), or metal materials, etc. 
     Further, as shown in  FIG. 4 , the method also includes patterning the high-K dielectric material layer  202   a  and the dummy gate material layer  204   a  to form the high-K dielectric layer  202  and the dummy gate  204 . Afterwards, the sidewall spacer  205  surrounding the high-K dielectric layer  202  and the dummy gate  204  are formed, as shown in  FIG. 5 . 
     The high-K dielectric material layer  202   a  and the dummy gate layer  204   a  may be patterned by any appropriate process, such as a dry etching process including a reactive ion etching process or an ion beam etching process, etc., or a wet etching process using any appropriate etching solution. 
     The sidewall spacer  205  may be made of any appropriate material, such as silicon oxide, silicon nitride, or a combination thereof. The sidewall spacer  205  may be formed by any appropriate process, such as an etch back process, i.e., depositing an sidewall spacer material layer on the top surface of the dummy gate  204 , the side surface of the dummy gate  204  and the side surface of the high-K dielectric layer  202 , and etching the portion of the sidewall spacer material layer on the top surface of the dummy gate  204  and keep a portion of the sidewall spacer material layer on the side surfaces of the dummy gate  204  and the high-K dielectric layer  202 . 
     Alternatively or optionally, an interface layer may be formed between the high-K dielectric layer  202  and the semiconductor substrate  100 .  FIGS. 6-8  illustrate corresponding structures. As shown in  FIG. 8 , an interface layer  201  may be formed between the high-K dielectric layer  202  and the semiconductor substrate  100 . 
     The method for forming the dummy gate structure with the interface layer  201  may sequentially include, as shown in  FIG. 6 , forming an interface material layer  201   a  on the substrate  100 ; forming a high-K dielectric material layer  202   a  on the interface material layer  201   a ; and forming a dummy gate material layer  204   a  on the high-K dielectric material layer  202   a.    
     The interface material layer  201  a may be formed by any appropriate process, such as a chemical vapor deposition process (CVD), a physical vapor deposition process (PVD), an atomic layer deposition process, a thermal oxidation process, or a chemical oxidation process etc. 
     Various fabrication processes may be used to form the high-K dielectric material layer  202   a  and the dummy gate material layer  204   a , such as a CVD process, a PVD process, and any other appropriate process. The interface material layer  201  may be made of any appropriate material such as silicon oxide, or silicon nitride, etc. In one embodiment, the interface material layer is silicon oxide. 
     The high-K dielectric material layer  202   a  may be made of any appropriate dielectric material, such as hafnium dioxide, hafnium silicate, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicate, tantalum oxide, titanium oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, lead scandium tantalite, or lead zinc niobate, etc. 
     In one embodiment, the high-K dielectric material may be made of at least one of hafnium dioxide and zirconium oxide. The dummy gate material layer  204   a  may be made of any appropriate material, such as poly silicon (so called dummy poly), or metal materials, etc. 
     Further, as shown in  FIG. 7 , the method for forming the dummy gate structure with the interface layer  201  may also include patterning the interface material layer  201  a, the high-K dielectric material layer  202   a  and the dummy gate material layer  204   a  to form the interface layer  201 , the high-K dielectric layer  202  and the dummy gate  204 . 
     The interface material layer  201  a, the high-K dielectric material layer  202   a  and the dummy gate layer  204   a  may be patterned by any appropriate process, such as a dry etching process including a reactive ion etching process or an ion beam etching process, etc., or a wet etching process using any appropriate etching solution. 
     Further, shown in  FIG. 8 , the method for forming the dummy gate structure with the interface layer  201  may include forming a sidewall spacer  205  surrounding the interface layer  201 , the high-K dielectric layer  202  and the dummy gate  204 . The sidewall spacer  205  may be made of any appropriate materials, such as silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof 
     The sidewall spacer  205  may be formed by any appropriate process, such as an etch back process, i.e., depositing a sidewall spacer material layer on the top surface of the dummy gate  204 , the side surface of the dummy gate  204 , the side surface of the high-K dielectric layer  202  and the side surface of the interface layer  201 , and etching the portion of the sidewall spacer material layer on the top surface of the dummy gate  204 , and keeping a portion of the sidewall spacer material layer on the side surfaces of the dummy gate  204 , the high-K dielectric layer  202  and the interface layer  201 . 
     It should be noted that, when the interface layer  201  is silicon oxide, the interface layer  201  may cause the interface state of the interface between the substrate  100  and the interface layer  201  to be a fast interface state, and the charge exchanging of conduction band and/or valance band may be speeded up. Thus, the interface layer  201  may increase the carrier mobility of the electrons and holes of the interface. 
     Alternatively or optionally, a capping layer may be formed between the high-K dielectric layer and the dummy gate.  FIGS. 9-11  illustrate corresponding structures. As shown in  FIG. 11 , a capping layer  203  may be formed between the high-K dielectric layer  202  and the dummy gate  204  besides the interface layer  203  between the high-K dielectric layer  202  and the semiconductor substrate  100 . 
     The method for forming the dummy gate structure with the capping layer  203  and the interface layer  201  may sequentially include, as shown in  FIG. 9 , forming an interface material layer  201   a  on the substrate  100 ; forming a high-K dielectric material layer  202   a  on the interface material layer  201   a ; forming a capping material layer  203   a  on the high-K dielectric material layer  202   a ; and forming a dummy gate material layer  204   a  on the capping material layer  203   a.    
     The interface material layer  201   a  may be formed by any appropriate process, such as a chemical vapor deposition process (CVD), a physical vapor deposition process (PVD), an atomic layer deposition process, a thermal oxidation process, and a chemical oxidation process etc. Various fabrication processes may be used to form the high-K dielectric material layer  202   a  the capping material layer  203   a  and the dummy gate material layer  204   a , such as a CVD process, a PVD process, or any other appropriate process. 
     The interface material layer  201   a  may be made of any appropriate material, such as silicon oxide, silicon nitride, or silicon oxynitride, etc. In one embodiment, the interface material layer  201   a  is silicon oxide. The high-K dielectric material layer  202   a  may be made of any appropriate dielectric material, such as hafnium dioxide, hafnium silicate, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicate, tantalum oxide, titanium oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, lead scandium tantalite, or lead zinc niobate, etc. 
     In one embodiment, the high-K dielectric material may be made of at least one of hafnium dioxide and zirconium oxide. The capping material layer  203   a  may be made of any one of titanium nitride, thallium nitride, titanium aluminum alloy, or a combination thereof. The dummy gate material layer  204   a  may be made of any appropriate material, such as poly silicon (so called dummy poly), or metal materials, etc. 
     As shown in  FIG. 10 , the method for forming the dummy gate structure with the capping layer  203  and the interface layer  201  may also include patterning the interface material layer  201   a , the high-K dielectric material layer  202   a , the capping material layer  203   a  and the dummy gate material layer  204   a  to form the interface layer  201 , the high-K dielectric layer  202 , the capping layer  203  and the dummy gate  204 . 
     The interface material layer  201   a , the high-K dielectric material layer  202   a , the capping material layer  203   a  and the dummy gate layer  204   a  may be patterned by any appropriate process, such as a dry etching process including a reactive ion etching processor an ion beam etching process, etc., or a wet etching process using any appropriate etching solution. 
     Further, as shown in  FIG. 11 , the method for forming the dummy gate structure with the capping layer  201  and the interface layer  203  may include forming a sidewall spacer  205  surrounding the interface layer  201 , the high-K dielectric layer  202 , the capping layer  203  and the dummy gate  204 . The sidewall spacer  205  may be made of any appropriate material, such as silicon oxide, silicon nitride, or a combination thereof. 
     The sidewall spacer  205  may be formed by any appropriate process, such as an etch back process, i.e., depositing a sidewall spacer material layer on the top surface of the dummy gate  204 , the side surface of the dummy gate  204 , the side surface of the high-K dielectric layer  202  , the side surface of the capping layer  203  and the side surface of the interface layer  201 , and etching the portion of the sidewall spacer material layer on the top surface of the dummy gate  204  and keep a portion of the sidewall spacer material layer on the side surfaces of the dummy gate  204 , the capping layer  203 , the high-K dielectric layer  202  and the interface layer  201 . 
     The capping layer  203  may be used as an etching stop layer for subsequently removing the dummy gate  204 , i.e., the etching process may be stopped when it reaches the capping layer  203 . The using of the capping layer  203  as the etching stop layer may prevent the high-K dielectric layer  203  being damaged when the dummy gate  204  is removed. 
     Returning to  FIG. 1 , after forming the dummy gate structure, an ion implantation process may be performed to the substrate  100  at both sides of the dummy gate structure to form a source region and a drain region (S 3 ).  FIG. 12  shows a corresponding semiconductor structure. 
     As shown in  FIG. 12 , a source region  101  and a drain region  102  may be formed in the substrate  100  at both sides of the dummy gate structure by an ion implantation process. Various types of ions may be used to form the desired type doped source region  101  and drain region  102 . When the P-type doped source region  101  and/or drain region  102  are formed, the dopant may be any appropriate trivalent ion, such as boron ion, etc. When the N-type doped source region  101  and/or drain region  102  are formed, the dopant may be any appropriate pentavalence ion, such as phosphorous ion, or arsenic ion, etc. 
     Returning to  FIG. 1 , after forming the source region  101  and the drain region  102 , a first annealing process may be performed to the semiconductor substrate  100  (S 4 ). The annealing process may enhance the ion diffusion of the source region  101  and the drain region  102 . An annealing temperature may be in a range of approximately 1000° C.˜1100° C. A duration of the annealing may be in a range of approximately 0˜2 s. 
     The temperature of the first annealing is relatively high, the oxygen element of the high-K dielectric layer  202  may decompose and escape under the high temperature, producing oxygen vacancies in the high-K dielectric layer  202 . As mentioned earlier, the oxygen vacancies may reduce the work function and the threshold voltage of the formed PMOS transistor, thus lower the performance. 
     Referring to  FIG. 13 , in one embodiment, a metal silicide layer  300  may be formed on the source region  101  and the drain region  102  at both sides of the dummy gate structure after the first annealing process and before forming an interlayer dielectric layer. The metal silicide layer  300  may be made of any appropriate material, such as nickel silicide, copper silicide, or cobalt silicide, etc. In one embodiment, the metal silicide is nickel silicide. The metal silicide layer  300  may be used to reduce the contact resistance of the subsequently formed conductive plugs. 
     Returning to  FIG. 1 , after forming the metal silicide layer  300 , an interlayer dieletric layer may be formed on the substrate  100  at both sides of the dummy gate structure (S 5 ).  FIG. 14  shows a corresponding semiconductor structure. 
     As shown in  FIG. 14 , an interlayer dielectric layer  400  may be formed on the substrate  100  at both sides of the dummy gate structure. The top surface of the interlayer dielectric layer  400  may be leveled with the top surface of the dummy gate  204 . The interlayer dielectric layer  400  may be made of any appropriate material, such as silicon oxide, silicon nitride, or silicon oxynitride, etc. 
     In one embodiment, the interlayer dielectric layer  400  is made of silicon oxide. The interlayer dielectric layer  400  may be made of any appropriate process, such as a CVD process, or a PVD process, etc. In order to make the top surface of the interlayer dielectric layer to be leveled with the top surface of the dummy gate  204 , a chemical mechanical polishing (CMP) process may be used after depositing an interlayer dielectric material layer, and the CMP process may be stopped when a portion of the interlayer dielectric material on the top of the dummy gate  204  is completely removed. Optionally, when the CVD process is used, an etching gas may be added into the reactive gas to prevent the interlayer dielectric layer growing on the top surface of the dummy gate  204 , and the interlayer dielectric layer  400  may be only formed on the substrate  100  at both sides of the dummy gate structure. 
     Returning to  FIG. 1 , after forming the interlayer dielectric layer  400 , the dummy gate  204  may be removed (S 6 ).  FIG. 15  shows a corresponding semiconductor structure. 
     As shown in  FIG. 15 , the dummy gate  204  is removed, and a trench  206  may be formed. The trench  206  may be used to form a metal gate. Various fabrication processes may be used to remove the dummy gate  204 , such as a dry etching process including a plasma etching process and an ion beam etching process, etc., and a wet etching process. In one embodiment, the dummy gate  204  is removed by a dry etching process. 
     If there is a capping layer  203  between the dummy gate  204  and the high-K dielectric layer  202 , the capping layer  203  may protect the high-K dielectric layer  202  when the dummy gate  204  is removed. A thickness of the capping layer may in a range of approximately 10 Å˜20 Å. 
     Returning to  FIG. 1 , after removing the dummy gate  204  and forming the trench  206 , a second annealing process may be performed to repair the oxygen vacancies in the high-K dielectric layer  202  (S 7 ). Various environmental gases may be used in the second annealing process. In one embodiment, the environmental gas is oxygen. The gas flow of the oxygen may be in a range of approximately 1 sccm˜100 sccm. An annealing temperature may be in a range of approximately 400° C.˜600° C. An annealing time may be in a range of 5 s˜100 s. 
     In another embodiment, the environmental gas of the second annealing process may be a mixture of oxygen and nitrogen. The nitrogen may be used to dilute the oxygen to prevent the high-K dielectric layer being over-oxidized. A concentration of oxygen in the mixture may be in a range of approximately 1 ppm˜1000 ppm. Other appropriate gases may also be used to dilute the oxygen. 
     In the second annealing process, the oxygen atoms may penetrate through the capping layer  203  to react with the high-K dielectric layer  202 , and fill the oxygen vacancies in the high-K dielectric layer  202 . Thus, the second annealing process under the oxygen environment may repair the oxygen vacancies in the high-K dielectric layer  202  caused by the first annealing process for the ion diffusion, and ensure the formed PMOS transistor to have a better performance. 
     In addition, the temperature of the second annealing process may be relatively low, the concentration of the oxygen may be relatively low if the diluted oxygen is used, and the annealing time may be relatively short. Thus, the second annealing process may repair the oxygen vacancies in the high-k dielectric layer  202  without oxidizing the capping layer  203 . 
     Returning to  FIG. 1 , after the second annealing process, a metal gate may be formed in the trench  206  (S 8 ).  FIG. 16  shows a corresponding semiconductor structure. 
     As shown in  FIG. 16 , a metal gate  208  may be formed in the trench  206 . After forming the metal gate  208 , a PMOS transistor is completely formed. The metal gate  208  may be made of any appropriate material, such as aluminum, copper, silver, gold, platinum, nickel, titanium, thallium, tantalum, tungsten, tungsten silicide, titanium tungsten alloy, titanium nitride, thallium nitride, thallium carbide, nickel platinum ally, or thallium nitrate silicate, etc. The metal gate  208  may be formed by any appropriate process, such as a CVD process or a PVD process, etc. 
     In one embodiment, a work function layer  207  may be formed on the high-K dielectric layer  202  after the second annealing process and before forming the metal gate  208 . 
     The work function layer  207  may be formed only on the bottom of the trench  206 , as shown in  FIG. 17 . Alternatively, the work function layer  207  may be formed on both the bottom and the sidewall of the trench  206 , as shown in  FIG. 18 . The work function layer  207  may be made of any appropriate material, such as titanium nitride, thallium nitride, or titanium aluminum alloy, etc. Various fabrication processes may be used to form the work function layer  207 , such as a CVD process, or a PVD process, etc. 
     In the disclosed embodiments, the second annealing process may be performed after removing the dummy gate  204 . The second annealing process may repair the oxygen vacancies in the high-K dielectric layer  202 , thus the problems, such as the reduction of the work function and the threshold voltage of the PMOS transistor, caused by the oxygen vacancies may be prevented. In addition, the temperature of the second annealing process may be relatively low, the oxygen concentration may be relatively low if the diluted oxygen is used, and the annealing time may relatively short, therefore the oxygen vacancies in the high-K dielectric layer  202  may be repaired without oxidizing the capping layer  203 . 
     In another embodiment, a PMOS transistor may be formed by the above disclosed processes and methods; the corresponding PMOS transistor is illustrated in  FIG. 17 . The PMOS transistor includes the substrate  100 , the source region  101  and the drain region  102 , and the gate structure having the interface layer  201 , the high-K dielectric layer  202 , the capping layer  203 , the work function layer  204  and the metal gate  208 . The PMOS transistor also includes the sidewall spacer  205  surrounding the gate structure, and the interlayer dielectric layer  400  leveling with the metal gate  208 . Further, the PMOS transistor includes the metal silicide layer  300  on the source region  101  and the drain region  102 . The detailed structures and intermediate structures are described above with respect to the fabrication methods. 
     It should be understood that the specification is described by exemplary embodiments, but it is not necessary that each embodiment includes an independent technical solution. Those skilled in the art can understand the specification as whole and technical features in the various embodiments can be combined to other embodiments understandable to other persons of ordinary skill in the art. 
     The above detailed descriptions only illustrate certain exemplary embodiments of the present invention, and are not intended to limit the scope of the present invention. Any equivalent or modification thereof, without departing the sprint and principle of the present invention, falls within the true scope of the present invention.