Patent Publication Number: US-2023154934-A1

Title: Display device

Description:
This application claims priority to Korean Patent Application No. 10-2021-0158739 filed on Nov. 17, 2021, and all the benefits accruing therefrom under 35 U.S.C. §119, the entire contents of which are incorporated herein by reference. 
     BACKGROUND 
     (A) Field 
     The present disclosure relates to a display device, and particularly relates to a display device for minimizing steps of layers at a pad portion. 
     (B) Description of the Related Art 
     A display device includes a display panel including pixels for displaying images. A circuit, and a pad through which signals are input to the display panel for controlling the pixels and the circuit, are provided on the display panel in addition to the pixels. Signal lines which are connected to the pad and transmit the signals are also provided on the display panel. 
     The pad and the pixels may be formed (or provided) in the same process, and the pad may have a similar stacked structure to the pixels. 
     SUMMARY 
     One or more embodiment of the invention provides a display device for minimizing steps of a pad portion. 
     An embodiment of the invention provides a display device including a substrate including a display area and a non-display area, a plurality of pads in the non-display area, and an insulating layer overlapping a predetermined region of the pad. The pad includes an overlapping region overlapping the insulating layer, and a non-overlapping region not overlapping the insulating layer. The insulating layer includes a first portion with a first thickness and a second portion with a second thickness which is less than the first thickness. The second portion of the insulating layer is between the non-overlapping region of the pad and the first portion of the insulating layer. 
     A length of the second portion may be about 20 micrometers (µm) to about 100 µm. 
     A thickness of the second portion may be about 30% to about 50% of a thickness of the first portion. 
     The pad may include a first data conductive layer, a second data conductive layer and a third data conductive layer, and the insulating layer may include a first insulating layer between the first data conductive layer and the second data conductive layer, a second insulating layer between the second data conductive layer and the third data conductive layer, and a third insulating layer on the third data conductive layer. 
     An end of the second insulating layer may be nearer the non-overlapping region of the pad than an end of the first insulating layer. 
     An end of the third insulating layer may be nearer the non-overlapping region of the pad than an end of the second insulating layer. 
     The first insulating layer may include a first portion with a first thickness and a second portion with a second thickness which is less than the first thickness. 
     The second insulating layer may include a first portion with a first thickness and a second portion with a second thickness which is less than the first thickness. 
     The third insulating layer may include a first portion with a first thickness and a second portion with a second thickness which is less than the first thickness. 
     The display area may include a first conductive layer, a second conductive layer and a third conductive layer, the first data conductive layer of the pad may be in a same layer as the first conductive layer of the display area, the second data conductive layer of the pad may be in a same layer as the second conductive layer of the display area, and the third data conductive layer of the pad may be in a same layer as the third conductive layer of the display area. 
     The first data conductive layer and the second data conductive layer may contact each other in an opening of the first insulating layer, and the second data conductive layer and the third data conductive layer may contact each other in an opening of the second insulating layer. 
     The first data conductive layer may be connected to the display area, and the third data conductive layer may be exposed to outside the insulating layer at the non-overlapping region of the pad. 
     The insulating layer may further include a third portion with a third thickness which is less than the second thickness, and the third portion of the insulating layer may be between the non-overlapping region of the pad and the second portion of the insulating layer. 
     The first insulating layer may include a first groove between the neighboring pads. 
     A width of the first groove may be about 20 µm to about 100 µm. 
     The second insulating layer may include a second groove between the neighboring pads and corresponding to the first groove, and a lateral side of the first insulating layer which defines the first groove may be covered by the second insulating layer. 
     A width of the second groove may be less than a width of the first groove. 
     A lateral side of the second insulating layer which defines the second groove may be covered by the third insulating layer. 
     The first insulating layer may include a first portion with a first thickness and a second portion with a second thickness which is less than the first thickness, and the second portion may be between the first portion and the first groove. 
     The second insulating layer may include a first portion with a first thickness and a second portion with a second thickness which is less than the first thickness, and the second portion may be between the first portion and the second groove. 
     According to one or more of the embodiments, the display device having minimized steps at the pad portion is provided. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The above and other advantages and features of this disclosure will become more apparent by describing in further detail embodiments thereof with reference to the accompanying drawings, in which: 
         FIG.  1    shows a top plan view of a display device according to an embodiment. 
         FIG.  2    shows a pad of a pad region according to an embodiment. 
         FIG.  3    shows a cross-sectional view with respect to line III-III′ of  FIG.  2   . 
         FIG.  4    to  FIG.  6    show a process which generates a residual film in a structure in which an insulating layer is multi-layered. 
         FIG.  7    shows an edge of an insulating layer of a display device according to an embodiment. 
         FIG.  8    shows a first insulating layer, a second insulating layer and a third insulating layer, relative to the pad of  FIG.  2   . 
         FIG.  9    shows a cross-sectional view with respect to line IX-IX′ of  FIG.  8   . 
         FIG.  10    shows a cross-sectional view with respect to line X-X′ of  FIG.  8   . 
         FIG.  11    shows a same cross-section as  FIG.  9    according to an embodiment. 
         FIG.  12    shows a same cross-section as  FIG.  9    according to an embodiment. 
         FIG.  13    shows a same cross-section as  FIG.  9    according to an embodiment. 
         FIG.  14    shows a same cross-section as  FIG.  9    according to an embodiment. 
         FIG.  15    shows a same cross-section as  FIG.  10    according to an embodiment. 
     
    
    
     DETAILED DESCRIPTION 
     The invention will be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the invention are shown. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present disclosure. 
     Parts that are irrelevant to the description will be omitted to clearly describe the invention, and the same elements will be designated by the same reference numerals throughout the specification. 
     Parts that are irrelevant to the description are omitted to clearly describe the present disclosure, and like reference numerals designate like elements throughout the specification. For better understanding and ease of description, the thicknesses of layers, films, panels, regions, etc., are enlarged for clarity. The thicknesses of some layers and areas are exaggerated. 
     It will be understood that when an element such as a layer, film, region, or substrate is referred to as being related to another element such as being “on” another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being related to another element such as being “directly on” another element, there are no intervening elements present. 
     It will be understood that, although the terms “first,” “second,” “third” etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, “a first element,” “component,” “region,” “layer” or “section” discussed below could be termed a second element, component, region, layer or section without departing from the teachings herein. 
     The word “on” or “above” means disposed on or below the object portion, and does not necessarily mean disposed on the upper side of the object portion based on a gravitational direction. 
     The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, “a”, “an,” “the,” and “at least one” do not denote a limitation of quantity, and are intended to include both the singular and plural, unless the context clearly indicates otherwise. For example, “an element” has the same meaning as “at least one element,” unless the context clearly indicates otherwise. As used herein, a reference number may indicate a singular element or a plurality of the element. For example, a reference number labeling a singular form of an element within the drawing figures may be used to reference a plurality of the singular element within the text of specification. 
     “At least one” is not to be construed as limiting “a” or “an.” “Or” means “and/or.” As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. Unless explicitly described to the contrary, the word “comprise” and variations such as “comprises” or “comprising” will be understood to imply the inclusion of stated elements but not the exclusion of any other elements. 
     “About” or “approximately” as used herein is inclusive of the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, considering the measurement in question and the error associated with measurement of the particular quantity (i.e., the limitations of the measurement system). For example, “about” can mean within one or more standard deviations, or within ± 30%, 20%, 10% or 5% of the stated value. 
     Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. 
     Embodiments are described herein with reference to cross section illustrations that are schematic illustrations of idealized embodiments. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments described herein should not be construed as limited to the particular shapes of regions as illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, a region illustrated or described as flat may, typically, have rough and/or nonlinear features. Moreover, sharp angles that are illustrated may be rounded. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region and are not intended to limit the scope of the present claims. 
     The phrase “in a plan view” means viewing a target portion from the top, and the phrase “in a cross-sectional view” means viewing a cross-section formed by vertically cutting a target portion from the side. 
     A display device according to an embodiment of the invention will now be described with reference to accompanying drawings. 
       FIG.  1    shows a top plan view of a display device according to an embodiment. Referring to  FIG.  1   , the display device may include a display panel  100  for displaying images, a printed circuit film  300  connected to the display panel  100 , and a main circuit board  500  connected to the printed circuit film  300 . 
     The display panel  100  includes a display area DA including a plurality of pixel areas including a plurality of pixels PX, and a non-display area NA which is adjacent to the display area DA, such as being disposed around the display area DA. The display area DA may have a rectangular shape (e.g., a rectangular planar shape) with linear corners in a plan view, or a rectangular shape with round corners in the plan view. The display area DA may have short sides and long sides. The short sides of the display area DA may be sides extended in a second direction DR 2 . The long sides of the display area DA may be sides extended in a first direction DR 1  crossing the second direction DR 2 . The planar shape of the display area DA is not limited to the rectangle, and may have various shapes such as a circle or an oval. 
     The non-display area NA may be disposed adjacent to (or near) the respective short sides and the respective long sides of the display area DA. In this case, the non-display area NA may be adjacent to all sides of the display area DA to surround the display area DA, and may configure an edge of the display area DA. However, without being limited thereto, the non-display area NA may be disposed near the respective short sides or the respective long sides of the display area DA. 
     The non-display area NA of the display panel  100  includes a pad area PA. The pad area PA may be disposed near one short side of the display area DA. Without being limited thereto, the pad area PA may be disposed near the respective short sides of the display area DA or may be disposed near the respective short sides and the respective long sides of the display area DA. 
     A pixel PX of the display panel  100  may be provided in plural including a plurality of pixels PX. The pixels PX of the display panel  100  may include a plurality of transistors and light-emitting devices which are connected thereto. The pixels PX may include a semiconductor layer, a plurality of conductive layers, and an insulating layer positioned among the conductive layers, and signals are applied by the conductive layers so the pixels PX are operable. 
     The pixel PX may include three data conductive layers. The pixel PX including three data conductive layers may reduce generation of heat as compared to the pixel PX including only one or two data conductive layers, may increase a freedom degree when designing wires of the pixel PX, and may reduce the size (e.g., a planar area or planar dimension) of the pixel PX. 
       FIG.  2    shows a pad area PA. A pad PD provided in plural including a plurality of pads PD, are positioned in the pad area PA. The pads PD may include three data conductive layers in this instance. 
     Referring to  FIG.  2   , the pads PD may include a first data conductive layer SD 1 , a second data conductive layer SD 2 , and a third data conductive layer SD 3  in order. When the pad PD is formed to have a multi-layered structure of the first data conductive layer SD 1 , the second data conductive layer SD 2 , and the third data conductive layer SD 3 , this may generate the same effect as increasing a total thickness of the pad PD and may reduce resistance (e.g., electrical resistance) of the pad PD. The first data conductive layer SD 1  of the pad PD may extend from the non-display area NA and into to the display area DA, and may be connected to the pixel PX of the display area DA. In an embodiment, for example, the display area DA includes a first conductive layer, a second conductive layer and a third conductive layer in order along the thickness direction of the display device, the first data conductive layer SD 1  of the pad PD is in a same layer as the first conductive layer of the display area DA, the second data conductive layer SD 2  of the pad PD is in a same layer as the second conductive layer of the display area DA, and the third data conductive layer SD 3  of the pad PD is in a same layer as the third conductive layer of the display area DA. As being ‘in a same layer’ as each other, elements may be formed in a same process, may include a same material, may be respective portions (or patterns) of a same material layer, may be on a same layer by forming an interface with a same underlying or overlying layer, etc., without being limited thereto. 
     A portion of an insulating layer may be removed or omitted from the upper portion of the pad PD (e.g., at the third data conductive layer SD 3 ), and the third data conductive layer SD 3  may contact the printed circuit film  300  to connect the pad PD to the printed circuit film  300 . A portion of the third data conductive layer SD 3  may define an exposed portion of the pad PD. As being in contact, elements may form an interface therebetween, without being limited thereto. 
       FIG.  3    shows a cross-sectional view with respect to line III-III′ of  FIG.  2   . Referring to  FIG.  3   , insulating layers VIA are positioned among (and between) the first data conductive layer SD 1 , the second data conductive layer SD 2 , and the third data conductive layer SD 3  within the pad PD, on a substrate SUB. The insulating layers VIA may include a first insulating layer VIA 1 , a second insulating layer VIA 2 , and a third insulating layer VIA 3 . 
     In detail, the first insulating layer VIA 1  may be positioned between the first data conductive layer SD 1  and the second data conductive layer SD 2 , and the second insulating layer VIA 2  may be positioned between the second data conductive layer SD 2  and the third data conductive layer SD 3 . The third insulating layer VIA 3  may be positioned on the third data conductive layer SD 3 . The first data conductive layer SD 1  may contact the second data conductive layer SD 2  through an opening formed (or defined) in the first insulating layer VIA 1 , and the second data conductive layer SD 2  may contact the third data conductive layer SD 3  through an opening formed in the second insulating layer VIA 2 . 
     The pad PD represents a portion of conductive layers at which the display panel  100  is connected to the printed circuit film  300 , such as contacting the printed circuit film  300 . As such, since the display panel  100  is connected to the printed circuit film  300  at the pad PD, a portion of the insulating layers VIA of the pad PD are removed from the connected portion of the pad PD. As the display device includes three data conductive layers and the insulating layers VIA are defined by a triple-layered structure, the insulating layers VIA has a high step with respect to a plane or reference surface, such as the substrate SUB. With the step, a residual film may be generated in an edge region of the pad PD at which the insulating layers VIA is removed. 
       FIG.  4    to  FIG.  6    show a process which generates a residual film in a structure in which an insulating member is multi-layered. As shown in  FIG.  4   , the first insulating layer VIA 1  is positioned on the innermost side, and the second insulating layer VIA 2  is positioned to cover the first insulating layer VIA 1  in the structure in which the first insulating layer VIA 1 , the second insulating layer VIA 2 , and the third insulating layer VIA 3  are sequentially stacked. The third insulating layer VIA 3  is then positioned to cover the second insulating layer VIA 2 . 
     A first electrode conductive layer  190  is positioned on the third insulating layer VIA 3 . The first electrode conductive layer  190  is on the third insulating layer VIA 3  in the non-display area NA since when a first electrode (not shown) of the pixel PX of the display area DA is formed, the first electrode conductive layer  190  is evenly formed in the display area DA and in the non-display area NA. As such, the first electrode (not shown) is formed through patterning the first electrode conductive layer  190  in the display area DA while the first electrode conductive layer  190  remains on the third insulating layer VIA 3  in the non-display area NA. 
     Therefore, as shown in  FIG.  4   , a photoresist PR is positioned on the first electrode conductive layer  190 . In this instance, since the insulating layers VIA is thick as it has a triple-layered structure, a step region including steps is generated. In the step region, the photoresist PR may be formed to be thicker than other regions. 
     As shown in  FIG.  5   , the photoresist is patterned and developed. A complete removal of the photoresist PR in the non-display area NA is desired, but since the photoresist PR is formed to be relatively thick at the step region at an end of the insulating layers VIA, part of the photoresist PR (e.g., a thickness portion) may not be removed but may remain within the non-display area NA. As the photoresist PR is removed through a same exposure from the entire region of the display area DA and the non-display area NA, some of the photoresist PR may not be removed but may remain in the portion where the photoresist PR is thick.  FIG.  5    shows the configuration in which a thickness portion of the photoresist PR is not removed but remains in the step region of the insulating layers VIA. 
     Referring to  FIG.  6   , the first electrode conductive layer  190  is patterned. Here, complete removal of the first electrode conductive layer  190  in the non-display area NA is desired. However, as shown in  FIG.  6   , owing to the remaining portion of the photoresist PR in a region of the first electrode conductive layer  190 , the first electrode conductive layer  190  covered by the photoresist PR is not removed but remains. When the first electrode conductive layer  190  remains in the non-display area NA as described above, a short circuit may be caused with the pad PD in the non-display area NA and may generate display defects. 
     However, the display device according to one or more embodiment has solved the short circuit issue by changing a thickness of the edge of the insulating layers VIA in the non-display area NA. 
       FIG.  7    shows an edge of an insulating layer VIA of a display device according to an embodiment. Referring to  FIG.  7   , the thickness of the edges of the second insulating layer VIA 2  and the third insulating layer VIA 3  according to the embodiment are thinner than at other (remaining) portions of the respective insulating layers. 
     That is, the second insulating layer VIA 2  includes a thick first portion (e.g., a first portion VIA 21 ) and a thin second portion (e.g., a second portion VIA 22 ). That is, each insulating layer has a thickness, and the thickness of the second insulating layer VIA 2  at the first portion VIA 21  is greater than the thickness of the second portion VIA 22 . The thickness of the second portion VIA 22  in this instance may be about 30% to about 50% of the thickness of the first portion VIA 21 . The second portion VIA 22  may be formed by using a halftone mask at the edge in a process for patterning a second insulating material layer for providing the second insulating layer VIA 2 . The thickness of a respective insulating layer may be taken in a direction normal to a surface of an underlying layer, at a position along the respective insulating layer. Respective thicknesses along an entirety of a thin second portion of an insulating layer may be smaller than thicknesses along an entirety of a thick first portion of the same insulating layer. 
     The thin second portion may have a first end closest to the edge of the insulating layers VIA, and a second end which is opposite to the first end and forms a boundary with the thick first portion. The second end may be a location where the thickness of the respective insulating layer decreases. The thin second portion has a length along the substrate SUB, in a direction toward the outer edge of the insulating layers VIA. The length may be defined between the first and second ends of the thin second portion. Referring to  FIG.  7   , a first length D2 of the second portion VIA 22  of the second insulating layer VIA 2  in (or along) the first direction DR 1  may be about 20 micrometers (µm) to about 100 µm.This corresponds to a range for efficiently reducing the steps within the pad structure. 
     The third insulating layer VIA 3  may include a thick first portion (e.g., a first portion VIA 31 ) and a thin second portion (e.g., a second portion VIA 32 ) which has a thickness smaller than the thickness of the first portion VIA 31 . The thickness of the second portion VIA 32  may be about 30% to about 65% of the thickness of the first portion VIA 31 . The second portion VIA 32  may be formed by using a halftone mask at the edge in a process for patterning a third insulating material layer for providing the second insulating layer VIA 2 . 
     The second portion VIA 32  of the third insulating layer VIA 3  may be positioned further outside than the second portion VIA 22  of the second insulating layer VIA 2 . The second end of the second portion VIA 32  is closer to the outer edge of the insulating layers VIA than the second end of the second portion VIA 22 . That is, part of the second portion VIA 22  of the second insulating layer VIA 2  may overlap the first portion VIA 31  of the third insulating layer VIA 3 . This is, however, an example, and the second portion VIA 32  of the third insulating layer VIA 3  may be positioned further inside than the second portion VIA 22  of the second insulating layer VIA 2  is according to an embodiment. 
     A second length D3 of the second portion VIA 32  of the third insulating layer VIA 3  in the first direction DR 1  may be about 20 µm to about 100 µm.This corresponds to the range for efficiently reducing the steps within the pad structure. 
       FIG.  8    shows a first insulating layer VIA 1 , a second insulating layer VIA 2 , and a third insulating layer VIA 3 , with relative to the structure in  FIG.  2   . Referring to  FIG.  8   , thickness portions of the first insulating layer VIA 1 , the second insulating layer VIA 2 , and the third insulating layer VIA 3  may be omitted in the pad area PA, and one or more conductive layer of the pad PD may be exposed to outside the insulating layers VIA. The pad PD includes an overlapping region overlapping one or more of the insulating layer VIA, and a non-overlapping region not overlapping the insulating layers VIA. The non-overlapping region is exposed to outside the insulating layers VIA to define an exposed portion of the pad PD. The exposed portion of the pad PD extends further than an outer edge of the insulating layers VIA. Within the pad area PA, the pad PD of the display panel  100  contacts the printed circuit film  300  of  FIG.  1    to connect the display panel  100  to the printed circuit film  300 . 
       FIG.  9    shows a cross-sectional view with respect to line IX-IX′ of  FIG.  8    at the outer edge of the insulating layers VIA. Referring to  FIG.  9   , the insulating layers VIA according to the embodiment has a step structure of which the edge is thinner than other portions, as shown in  FIG.  7   . The second insulating layer VIA 2  includes a thick first portion (e.g., a first portion VIA 21 ) and a thin second portion (e.g., a second portion VIA 22 ). The thickness of the second portion VIA 22  may be about 30% to about 50% of the thickness of the first portion VIA 21 . 
     The third insulating layer VIA 3  may include a thick first portion (e.g., a first portion VIA 31 ) and a thin second portion (e.g., a second portion VIA 32 ). The thickness of the second portion VIA 32  may be about 30% to about 50% of the thickness of the first portion VIA 31 . 
     The second portion VIA 32  of the third insulating layer VIA 3  may be positioned further inside than the second portion VIA 22  of the second insulating layer VIA 2  is. That is, part of the second portion VIA 32  of the third insulating layer VIA 3  may overlap the first portion VIA 21  of the second insulating layer VIA 2 . The second end of the second portion VIA 32  may be further from the outer edge of the insulating layers VIA than the second end of the second portion VIA 22 . 
     As edge portions of the second insulating layer VIA 2  and the third insulating layer VIA 3  are thin, the step at the edge of the insulating layers VIA may be minimized. Therefore, as shown in  FIG.  4    to  FIG.  6   , the problem in which the residual film of the photoresist PR remains near the insulating layers VIA and the problem in which a residual portion of the first electrode conductive layer  190  is not etched but remains and generates a short circuit, may be solved. 
     A first length D2 of the second portion VIA 22  of the second insulating layer VIA 2  in the first direction DR 1  may be about 20 µm to about 100 µm. A second length D3 of the second portion VIA 32  of the third insulating layer VIA 3  in the first direction DR 1  may be about 20 µm to about 100 µm. This is the range for preventing the region occupied by the insulating layers VIA from becoming excessively great and efficiently reducing the step. 
       FIG.  10    shows a cross-sectional view with respect to line X-X′ of  FIG.  8   , at an area between pads PD. Referring to  FIG.  10   , regarding the display device according to the embodiment, a first groove H1 at which the first insulating layer VIA 1  is removed and a second groove H2 at which the second insulating layer VIA 2  is removed are positioned in a region between the pads PD neighboring each other. A portion of the third insulating layer VIA 3  may have a similar shape to the groove formed by the first groove H1 and the second groove H2. 
     Side surfaces (or lateral surfaces) of respective insulating layers may define a respective groove. A lateral side of the first insulating layer VIA 1  is covered by the second insulating layer VIA 2 , and a lateral side of the second insulating layer VIA is covered by the third insulating layer VIA 3 . 
     Therefore, even when the residual film is generated in the region between the pads PD adjacent to each other, the residual film may be covered by the insulating layers VIA on the respective layers, to thus prevent the short circuit between adjacent pads PD. For example, when the residual film of the second data conductive layer SD 2  of the pad PD is generated, it is covered by the third insulating layer VIA 3 , and is not short-circuited with other portions of the third data conductive layer SD 3 . In a like manner, when the residual film of the first data conductive layer SD 1  of the pad PD is generated, this is covered by the second insulating layer VIA 2 , and is not short-circuited with other portions of the second data conductive layer SD 2  or other portions of the third data conductive layer SD 3 . 
     A first spaced distance (e.g., length of the first groove H1) between facing side surfaces of the first insulating layers VIA 1  may be about 20 µm to about 100 µm. A second spaced distance (e.g., length of the second groove H2) between facing side surfaces of the second insulating layers VIA 2  may be about 20 µm to about 100 µm. The first spaced distance may be greater than the second spaced distance. 
       FIG.  11    shows a same cross-section as  FIG.  9    according to an embodiment. What is described with reference to  FIG.  11    corresponds to what is described with reference to  FIG.  9    except that the first insulating layer VIA 1  includes a second portion VIA 12  that is thinner than the first portion VIA 11 , and the first portion VIA 11 . No same constituent elements will be described in detail. The first insulating layer VIA 1  shown in  FIG.  11    includes the first portion VIA 11  and the second portion VIA 12  so the step of the insulating layers VIA may be further gently reduced. 
       FIG.  12    shows a same cross-section as  FIG.  9    according to an embodiment. Referring to  FIG.  12   , regarding the display device according to an embodiment, the second insulating layer VIA 2  includes a first portion VIA 21 , a second portion VIA 22 , and a third portion VIA 23  having different thicknesses from each other. When the second insulating layer VIA 2  has three thicknesses as described, the steps may be further gently reduced, which is desirable. Thicknesses of the portions of the second insulating layer VIA 2  decrease in a direction toward the outer edge of the insulating layers VIA. 
       FIG.  13    shows a same cross-section as  FIG.  9    according to an embodiment. Referring to  FIG.  13   , regarding the display device according to an embodiment, the third insulating layer VIA 3  includes a first portion VIA 31 , a second portion VIA 32 , and a third portion VIA 33  of which the thicknesses are different from each other. When the third insulating layer VIA 3  has three thicknesses, the steps may be further gently reduced, which is desirable. 
       FIG.  14    shows a same cross-section as  FIG.  9    according to an embodiment. Referring to  FIG.  14   , regarding the display device according to an embodiment, the second insulating layer VIA 2  includes a first portion VIA 21 , a second portion VIA 22 , and a third portion VIA 23  having different thicknesses, and the third insulating layer VIA 3  includes a first portion VIA 31 , a second portion VIA 32 , and a third portion VIA 33  having different thicknesses. When the second insulating layer VIA 2  and the third insulating layer VIA 3  respectively have three thicknesses, the steps may be further gently reduced, which is desirable. 
       FIG.  15    shows a same cross-section as  FIG.  10    according to an embodiment. Referring to  FIG.  15   , in an embodiment, the first insulating layer VIA 1  includes a first portion VIA 11  and a second portion VIA 12  that is thinner than the first portion VIA 11 , and the second insulating layer VIA 2  includes a first portion VIA 21  and a second portion VIA 22  that is thinner than the first portion VIA 21 . When the first insulating layer VIA 1  and the second insulating layer VIA 2  include a step structure as described, the step may become gentle on the end of the insulating layers VIA, and a possibility of generation of the conductive layer residual film may be reduced. 
     Regarding the display device according to one or more embodiment, the insulating layers VIA include multiple layers in the pad area PA of the non-display area NA, and the edge thickness portions of the insulating layers VIA of the respective layers are relatively thin. Therefore, the step of the insulating layers VIA may be minimized at the end of the insulating layers VIA, and the problem of the generation of a residual film of the first electrode conductive layer  190  by the step may be solved. In addition, the widths of the respective insulating layers in the region between a plurality of pads PD are different. That is, the lateral side of the first insulating layer VIA 1  is covered by the second insulating layer VIA 2 , and the lateral side of the second insulating layer VIA 2  is covered by the third insulating layer VIA 3 . Therefore, when the residual film of the first data conductive layer SD 1 , the second data conductive layer SD 2 , or the third data conductive layer SD 3  is generated in the region between a plurality of pads PD, it may be covered by the respective insulating layers, and the short circuit may be prevented. That is, an upper insulating layer covers a residual conductive layer on a lower insulating layer, to reduce or effectively prevent the short circuit. 
     While this invention has been described in connection with what is presently considered to be embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.