Patent Publication Number: US-6706606-B2

Title: Buried zener diode structure and method of manufacture

Description:
This is a divisional application of non-provisional application Ser. No. 10/184,418 filed Jun. 27, 2002 now U.S. Pat. No. 6,605,859. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates generally to Zener diodes, and more particularly, to a buried Zener diode structure and method of manufacture that requires no additional process steps beyond those required in a basic standard bipolar flow with up-down isolation. 
     2. Description of the Prior Art 
     Conventional “surface” Zener reference diodes exhibit long-term drift due to impurities and other oxide charges that can build up over time. This phenomenon is known as “Zener walkout”. Buried Zener diodes do not suffer these problems, since such diodes possess stable long-term performance. Buried Zener diodes generally require additional process steps beyond those typically used in a “Standard” bipolar flow. In view of the foregoing, it would be both advantageous and desirable to provide a buried Zener diode structure and method of manufacture that does not require additional process steps beyond those typically used in a “Standard” bipolar flow. Some buried Zener diode structures representative of the present state of the art are described in the U.S. patents discussed herein below. 
     U.S. Pat. No. 4,833,509, entitled Integrated Circuit Reference Diode And Fabrication Method Therefor, issued May 23, 1989, to Hickox et al., discloses an N+ buried layer, but that must be oversized to compensate for alignment after the EPI is grown. This structure also requires two N+ diffusions, thus requiring extra mask steps. 
     U.S. Pat. No. 5,027,165, entitled Buried Zener Diode, issued Jun. 25, 1991, to Doluca, discloses a buried Zener diode structure, but that undesirably requires an additional P+ diffusion. 
     U.S. Pat. No. 4,136,349, entitled IC Chip With Buried Zener Diode, issued Jan. 23, 1979, to Tsang, discloses a structure that requires both an oversized N+ layer as well as an extra P+ diffusion. 
     U.S. Pat. No. 4,683,483, entitled Subsurface Zener Diode And Method Of Making, issued Jul. 28, 1987, to Burnham et al., discloses a structure that requires the N+ layer to be oversized, requires and extra mask step, requires an emitter etch to clear the isolation oxide, and has additional alignment issues to deal with. 
     U.S. Pat. No. 4,742,021, entitled Subsurface Zener Diode And Method Of Making, issued May 3, 1988, to Burnham et al., discloses a structure that requires the N+ layer to be oversized, requires a Pwell diffusion, and also requires an additional step comprising etching the emitter mask through the isolation oxide. 
     U.S. Pat. No. 4,177,095, entitled Process For Fabricating An Integrated Circuit Subsurface Zener Diode Utilizing Conventional Processing Steps, issued Dec. 4, 1979, to Nelson, discloses a structure that requires an emitter diffusion through an isolation oxide (extra mask step), the N+ layer to be oversized, and a breakdown that is set by ISO/Emitter doping, that is generally not well controlled. 
     U.S. Pat. No. 4,127,859, entitled Integrated Circuit Subsurface Zener Diode, issued Nov. 28, 1978, to Nelson, discloses a structure that requires the N+ layer to be oversized. 
     U.S. Pat. No. 5,179,030, entitled Method Of Fabricating A Buried Zener Diode Simultaneously With Other Semiconductor Devices, issued Jan. 12, 1993, to Hemmah, discloses a structure in which the substrate is the anode and that does not have a buried junction. 
     SUMMARY OF THE INVENTION 
     The present invention is directed to a buried Zener diode structure and method of manufacture that requires no additional process steps beyond those required in a basic standard bipolar flow with up-down isolation. 
     In one aspect of the invention, a buried Zener diode is provided where the N++/P+ junction is removed from the silicon surface without requiring additional process steps beyond those typically used in a “Standard” bipolar flow. 
     In another aspect of the invention, a buried Zener diode is provided having more stable long-term performance than conventional “surface” Zener reference diodes without requiring additional process steps beyond those typically used in a “Standard” bipolar flow. 
     In yet another aspect of the invention, a buried Zener diode is provided having a P-type buried isolation (PBL) to make contact to the anode of the Zener diode. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Other aspects, features and advantages of the present invention will be readily appreciated, as the invention becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawing figures wherein: 
     FIG. 1 is a pictorial diagram showing a P-type substrate, a N-type buried layer driven into the substrate, a P-type implant placed within the N-type buried layer, and a grown EPI region; 
     FIG. 2 is a pictorial diagram showing the structure depicted in FIG. I further having a field oxide region etched open and P+ deposition made in two places within the diode tank to provide a P+ diffusion corresponding to a top isolation region (ISO); 
     FIG. 3 is a pictorial diagram showing the structure depicted in FIG. 2 further having the upper ISO and lower PBL diffusion coming together to isolate the transistors and forming the connecting path to the anode of the buried Zener; 
     FIG. 4 is a pictorial diagram showing the structure depicted in FIG. 3 further having an NPN base implant/deposition placed into each of the ISO regions after removing the oxide from the region above the ISO regions; 
     FIG. 5 is a pictorial diagram showing the structure depicted in FIG. 4 further having a doped N++ “Emitter” diffusion region driven into one of the base regions; 
     FIG. 6 is a pictorial diagram showing the structure depicted in FIG. 5 further having a contact etch applied to allow contact to the cathode and anode of the Zener diode; and 
     FIG. 7 is a pictorial diagram showing a complete buried Zener diode structure according to one embodiment of the present invention. 
    
    
     While the above-identified drawing figures set forth particular embodiments, other embodiments of the present invention are also contemplated, as noted in the discussion. In all cases, this disclosure presents illustrated embodiments of the present invention by way of representation and not limitation. Numerous other modifications and embodiments can be devised by those skilled in the art which fall within the scope and spirit of the principles of this invention. 
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 1 illustrates one portion of a buried Zener diode structure  100 , according to one embodiment that is manufactured by starting with a P-type substrate  102 . First, an N-type buried layer  104  is deposited onto, and driven into, the substrate  102 . This is the NPN buried collector (DUF). Second, a P-type implant/deposition  108  is placed within the DUF diffusion  104 . This P-type diffusion  108  corresponds to the P-type buried isolation (PBL) used to define the transistor tanks. Then the EPI  110  is grown to provide the structure shown in FIG.  1 . 
     Subsequent to the steps described herein above, the field oxide  112  shown in FIG. 2 is then etched open, and a P+ deposition  114 , also shown in FIG. 2, is made in two places within the diode tank. FIG. 2 is a pictorial diagram showing the structure  100  depicted in FIG. 1 further having a field oxide region  112  etched open and P+ deposition  114  made in two places within the diode tank to provide a P+ diffusion corresponding to a top isolation region (ISO). 
     The P+ depositions  114  are next driven in such that the upper ISO and lower PBL diffusions come together and isolate the transistors such as illustrated in FIG. 3 that is a pictorial diagram showing the structure depicted in FIG. 2 further having the upper ISO and lower PBL diffusion coming together to isolate the transistors and forming the connecting path to the anode of the buried Zener diode. 
     During the mask step that defines the NPN transistor “Base”, the oxide is also removed from the region above the isolation diffusions  114 . FIG. 4 is a pictorial diagram showing the structure depicted in FIG. 3 further having an NPN base implant/deposition  116  that is driven into the silicon to place an NPN base dopant into each of the ISO regions  114  after removing the oxide  112  from the region above the ISO regions  114 . Importantly, since the doping concentration of the NPN “Base” diffusion  116  is significantly higher than that of the associated ISO region  114 , the Base region will control the breakdown voltage of any diode structure that uses it as part of its fabrication. 
     Subsequent to forming the Base regions, an NPN Emitter mask is used to reopen a desired Base region  116  that is then doped N++ to form the N-type cathode diffusion region  120  shown in FIG.  5 . The N++ doped diffusion region  120  is most preferably slightly oversized beyond that of the isolation  114  as shown in FIG. 5 to account for the out-diffusion of the “Base”  116  and isolation  114  during its drive-in process to ensure that no surface breakdown can occur. 
     The oxide  112  is then grown over the open silicon areas, and a contact etch is applied to allow contact to the Emitter (cathode)  120  and anode  122  of the buried Zener diode structure shown in FIG.  6 . Standard integrated circuit manufacturing techniques are then used to complete interconnection and passivation of the buried Zener diode device. The heaviest N++/P+ junction  124  will be directly under the Emitter diffusion  120 ; and that is where the Zener action will occur. 
     FIG. 7 is a pictorial diagram showing a complete buried Zener diode structure  200  manufactured according to the steps described herein above. In summary explanation, buried Zener diode  200  importantly requires no additional process steps to manufacture beyond those used in a “standard” bipolar process with an up-down isolation scheme. The P+ region  116  is formed by the NPN transistor “Base” diffusion; the N++ diffusion  120  is the NPN transistor “Emitter” diffusion. The use of the P-type buried layer  114  to form the buried anode of the transistor relaxes the alignment requirements of the ISO to DUF subsequent to EPI growth, and thus allows the size of the initial DUF diffusion  104  to be smaller, thereby minimizing the size of the overall buried Zener diode structure  200 . 
     Other realizations of “buried” Zener transistor in bipolar process flows that are known in the prior art require additional process steps that may include additional implants/depositions, well diffusions, or oxide etches. In the case of implants/depositions, the process steps are time consuming and costly. “Well” diffusions require extra (long) furnace cycles, and an additional process to monitor. Oxide etches generally require an additional mask step that is costly. 
     A buried Zener diode manufactured according to the principles described herein before is particularly useful in space or radiation hardened devices as well as low noise references to which bipolar circuits are well suited. Other uses include subcircuits of many different types of devices such as start-up, over-voltage protection, and under-voltage lock-out (UVLO) circuitry, among others. 
     In view of the above, it can be seen the present invention presents a significant advancement in the art of buried Zener diodes. Further, this invention has been described in considerable detail in order to provide those skilled in the transistor manufacturing art with the information needed to apply the novel principles and to construct and use such specialized components as are required. In view of the foregoing descriptions, it should be apparent that the present invention represents a significant departure from the prior art in construction and operation. However, while particular embodiments of the present invention have been described herein in detail, it is to be understood that various alterations, modifications and substitutions can be made therein without departing in any way from the spirit and scope of the present invention, as defined in the claims which follow.