Patent Publication Number: US-9423810-B2

Title: Voltage regulator and control method thereof

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application claims the priority benefits of U.S. provisional application Ser. No. 61/891,722, filed on Oct. 16, 2013 and Taiwan application serial no. 102147464, filed on Dec. 20, 2013. The entirety of each of the above-mentioned patent applications is hereby incorporated by reference herein and made a part of this specification. 
    
    
     TECHNICAL FIELD 
     This disclosure relates to a voltage regulator and a control method thereof. 
     BACKGROUND 
     The power management system for the conventional processor (such as the processors inside smart phones or cars) usually has a set of low dropout (LDO) regulators to dynamically adjust voltages. Generally, the LDO regulator is primarily embodied by the analog control technology or the sync digital control technology. 
     If the LDO regulator is embodied by the analog control technology, the reaction speed of the LDO regulator actively adjusting the voltage is limited by the bandwidth related with the analog control circuit, so the speed of adjusting the voltage cannot be increased effectively. Furthermore, when the LDP regulator operates in the static state, since the LDO regulator still needs to provide the bias current to maintain its operation, the static work current for the analog control circuit cannot be decreased during the static state. 
     If the LDO regulator is embodied by the sync digital control technology, the reaction speed of the LDO regulator dynamically adjusting the voltage is limited by the clock rate of the clock frequency signal for the digital control circuit. In order to increase the reaction speed of the LDO regulator actively adjusting the voltage, the clock rate of the clock frequency signal has to be increased. However, increasing the clock rate of the clock frequency signal will increase the current waste of the digital control circuit and also cause the occurrence of inrush current. 
     SUMMARY 
     According to one or more embodiments, the disclosure provides a voltage regulator adapted to dynamically adjust an output voltage from a first output end of the voltage regulator. In one embodiment, the voltage regulator comprises a plurality of switching transistors and a control circuit. Each switching transistor has a first end for receiving a driving voltage, a second end electrically connected with the first output end, and a control end. The switching transistors adjust the output voltage. The control circuit comprises an input end for receiving a reference voltage, a feedback end for receiving the output voltage, and a plurality of second output ends electrically connected with the control ends of the switching transistors respectively. The control circuit compares the output voltage with the reference voltage, and selectively turns on or off the switching transistors according to the comparison between the output voltage and the reference voltage whereby the output voltage approaches the reference voltage. 
     According to one or more embodiments, the disclosure also provides a control method of a voltage regulator, which is adapted to dynamically adjust an output voltage outputted by the voltage regulator which comprises a plurality of switching transistors and a control circuit, and each switching transistor has a first end for receiving a driving voltage, a second end electrically connected with an end outputting the output voltage, and a control end electrically connected with the control circuit. In one embodiment, the control method comprises the following steps. First, an output voltage is fed back to a control circuit. Secondly, the output voltage is compared with a reference voltage. Lastly, the switch transistors are selectively turned on or off according to the comparison between the output voltage and the reference voltage, whereby the output voltage approaches the reference voltage. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The disclosure will become more fully understood from the detailed description given herein below for illustration only, and thus are not limitative of the disclosure, and wherein: 
         FIG. 1  is a block diagram of a voltage regulator in an embodiment in the disclosure; 
         FIG. 2  is a block diagram of the control circuit in  FIG. 1 ; 
         FIG. 3  is a circuit diagram of the Ith stage driving module in  FIG. 2 ; 
         FIG. 4A  is a sequence diagram of the Ith stage driving module in  FIG. 2  when the output voltage is smaller than the reference voltage; 
         FIG. 4B  is a sequence diagram of the Ith stage driving module in  FIG. 2  when the output voltage is larger than the reference voltage; 
         FIG. 5  is a sequence diagram of the control circuit in  FIG. 2 ; 
         FIG. 6  is a flow chart of a control method of the voltage regulator in an embodiment in the disclosure; and 
         FIG. 7  is a flow chart of a control method of the voltage regulator in another embodiment in the disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     In the following detailed description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the disclosed embodiments. It will be apparent, however, that one or more embodiments may be practiced without these specific details. In other instances, well-known structures and devices are schematically shown in order to simplify the drawing. 
     The disclosure provides a voltage regulator according to one or more embodiments. Referring to  FIG. 1 , a block diagram of a voltage regulator  1  in one embodiment is described. The voltage regulator  1  is adapted to dynamically adjust an output voltage V SUP  from the output end (or called the first output end) of the voltage regulator  1 . The voltage regulator  1  comprises a control circuit  10  and a transistor array  12 . 
     The transistor array  12  comprises a plurality of switching transistors M_ 1  to M_n, wherein n is a positive integer larger or equal to 1. Each of the switching transistors M_ 1  to M_n has a first end for receiving a driving voltage V DD , a second end electrically connected with the output end (i.e. the nodes supply the output voltage V SUP ) of the voltage regulator  1 , and a control end. In one embodiment, each of the switching transistors M_ 1  to M_n may be a metal oxide semiconductor field effect transistor (MOSFET). In this case, the source of the MOSFET may be the first end of the switching transistor, the drain of the MOSFET may be the second end of the switching transistor, and the gate of the MOSFET may be the control end of the switching transistor. 
     The control circuit  10  comprises an input end IN_ 1 , a feedback end IN_ 2 , and a plurality of output ends (or called second output ends) OUT_ 1  to OUT_n. The input end IN_ 1  receives a reference voltage V RF . The feedback end IN_ 2  receives the output voltage V SUP  which is fed back from the output end of the voltage regulator  1 . The output ends OUT_ 1  to OUT_n are electrically connected with the control ends of the switching transistors M_ 1  to M_n respectively so that the switching transistors M_ 1  to M_n are able to be controlled by the control circuit  10 . 
     The control circuit  10  is configured to compare the output voltage V SUP  with the reference voltage V RF  to selectively turn on or off the switching transistors M_ 1  to M_n so that the output voltage V SUP  approaches the reference voltage V RF . Specifically, when the control circuit  10  determines that the output voltage V SUP  is smaller than the reference voltage V RF , the control circuit  10  turns on one or more of the switching transistors M_ 1  to M_n. Herein, since the equivalent resistance value of the transistor array  12  increases, the driving current flowing through the transistor array  12  increases, and then the output voltage V SUP  increases until the output voltage V SUP  is larger or equal to the reference voltage V RF . On the other hand, when the control circuit  10  determines that the output voltage V SUP  is larger than the reference voltage V RF , the control circuit  10  turns off one or more of the switching transistors M_ 1  to M_n. Herein, since the equivalent resistance value of the transistor array  12  decreases, the driving current flowing through the transistor array  12  decreases, and then the output voltage V SUP  decreases until the output voltage V SUP  is smaller or equal to the reference voltage V RF . Whenever the output voltage V SUP  is smaller than the reference voltage V RF , the control circuit  10  repeats the aforementioned operation. In other words, the switching transistors M_ 1  to M_n are configured to adjust the output voltage V SUP . 
     To more clearly illustrate the operation of the control circuit  10 , please refer to  FIG. 2  which is a block diagram of the control circuit in  FIG. 1 . The control circuit  10  primarily comprises a plurality of driving modules  100 _ 1  to  100 _ n , a first reflecting module  102 , and a second reflecting module  104 . The driving modules  100 _ 1  to  100 _ n  are electrically connected with each other. Each of the driving modules  100 _ 1  to  100 _ n  receives the reference voltage V RF  and the output voltage V SUP . The output ends OUT_ 1  to OUT_n of the driving modules  100 _ 1  to  100 _ n  are electrically connected with the control ends of the switching transistors M_ 1  to M_n in the transistor array  12  respectively. 
     Each driving module comprises a first input pin PIN_ 1 , a first output pin PIN_ 2 , a second input pin PIN_ 3 , and a second output pin PIN_ 4 . The first reflecting module  102  comprises a first input pin PIN_ 1 , a first output pin PIN_ 2 , a second input pin PIN_ 3 , and a third input pin PIN_ 4 . The second reflecting module  104  comprises an input pin PIN_ 1  and an output pin PIN_ 4 . The first output pin PIN_ 2  of the first reflecting module  102  is connected with the first input pin PIN_ 1  of the driving module  100 _ 1 . The first output pin PIN_ 2  of the driving module  100 _ n  is connected with the input pin PIN_ 1  of the second reflecting module  104 . The first output pin PIN_ 2  of the driving module  100 _ 1  is connected with the first input pin PIN_ 1  of the next stage driving module (i.e. the driving module  100 _ 2 . Similarly, the first output pin PIN_ 2  of the driving module  100 _ 2  is connected with the first input pin PIN_ 1  of the driving module  100 _ 3 . The connection of the first output pins PIN_ 2  of the rest of the driving modules  100 _ 1  to  100 _ n  can be deduced by analogy. The second input pin PIN_ 3  and the third input pin PIN_ 4  of the first reflecting module  102  are connected with the second output pin PIN_ 4  of the driving module  100 _ 2  and the second output pin PIN_ 4  of the driving module  100 _ 1  respectively. The output pin PIN_ 4  of the second reflecting module  104  is connected with the second input pin PIN_ 3  of the driving module  100 _ n −1. The second output pin PIN_ 4  of the driving module  100 _ 3  is connected with the second input pin PIN_ 3  of the driving module (i.e. the driving module  100 _ 1 ) before the previous stage driving module (i.e. the driving module  100 _ 2 ) of the driving module  100 _ 3 . Similarly, the second output pin PIN_ 4  of the driving module  100 _ 4  is connected with the second input pin PIN_ 3  of the driving module  100 _ 2 ). The connection of the second output pins PIN_ 4  of the rest of the driving module  100 _ 1  to  100 _ n  can be deduced by analogy. The second input pin PIN_ 3  of the driving module  100 _ n  is grounded. 
     When the first input pin PIN_ 1  of the Ith stage driving module  100 _ i  in the driving modules  100 _ 1  to  100 _ n  receives a triggering signal, the Ith stage driving module  100 _ i  may selectively turn on or off the switching transistor M_ i , which corresponds to the Ith stage driving module  100 _ i , according to the comparison between the reference voltage V RF  and the output voltage V SUP , wherein i is smaller or equal to n, and is a positive integer. 
     The first reflecting module  102  outputs the triggering signal to the first input pin PIN_ 1  of the driving module  100 _ 1  (or called the first stage driving module). Moreover, when the first reflecting module  102  receives the triggering signal fed back from the second output pin PIN_ 4  of the driving module  100 _ 1  or the second output pin PIN_ 4  of the driving module  100 _ 2  (or called the second stage driving module), the first reflecting module  102  may transfer this triggering signal to the first input pin PIN_ 1  of the driving module  100 _ 1 . The second reflecting module  104 , via its first input pin PIN_ 1 , receives the triggering signal sent from the first output pin PIN_ 2  of the driving module  100 _ n  (or called the last stage driving module), and transfers the triggering signal to the second input pin PIN_ 3  of the driving module  100 _ n −1 (or called the second last stage driving module) through the output pin PIN_ 4  of the second reflecting module  104 . In other words, the first reflecting module  102  and the second reflecting module  104  are configured to make sure that the voltage regulator  1  can operate normally during the transition period of the output voltage V SUP . 
     Referring to  FIG. 3 , the detail of the Ith stage driving module  100 _ i  in  FIG. 2  is illustrated. The Ith stage driving module  100 _ i  comprises an amplifier  1000 , a SR flip-flop  1002 , a multiplexer  1004 , a first delay unit  1006 , a Muller C logic gate  1008 , an AND logic gate  1010 , an OR logic gate  1012 , and a second delay unit  1014 . One of the two input ends of the amplifier  1000  receives the reference voltage V RF , and the other one of the two input ends of the amplifier  1000  receives the output voltage V SUP  and is electrically connected to the second end of the switching transistor M_ i . The two output ends of the amplifier  1000  are electrically connected to the S end and R end of the SR flip-flop  1002  respectively. The control end of the amplifier  1000  is electrically connected to the first input pin PIN_ 1  of the Ith stage driving module  100 _ i.    
     The output end (i.e. Q end) of the SR flip-flop  1002  is coupled to the output end OUT_ i  of the control circuit  10  and is electrically connected with the control end of the switching transistor M_ i . The first delay unit  1006  is electrically connected with the first input pin PIN_ 1  of the Ith stage driving module  100 _ i  and one of the input ends of the Muller C logic gate  1008 . The other input end of the Muller C logic gate  1008  is electrically connected with the second delay unit  1014  and one of the input ends of the AND logic gate  1010 . The output end of the Muller C logic gate  1008  is electrically connected with one of the input ends of the OR logic gate  1012 . The other input end of the OR logic gate  1012  is electrically connected with the LCK end of the multiplexer  1004 . The output end of the OR logic gate  1012  is electrically connected with one end of the second delay unit  1014 . The other end of the second delay unit  1014  is electrically connected with one of the input ends of the AND logic gate  1010  and the B end of the multiplexer  1004 . 
     The other input end of the AND logic gate  1010  is electrically connected with the Q end of the SR flip-flop  1002 . The output end of the AND logic gate  1010  is electrically connected with the second output pin PIN_ 4  of the Ith stage driving module  100 _ i . The second input pin PIN_ 3  of the Ith stage driving module  100 _ i  is electrically connected with the A end of the multiplexer  1004 . The Z end of the multiplexer  1004  is electrically connected with the first output pin PIN_ 2  of the Ith stage driving module  100 _ i . The U end, W end, and V end of the multiplexer  1004  are electrically connected with the output end OUT_i, the output end OUT_i+1, and the output end OUT_i+2 of the control circuit  10  respectively. Furthermore, the multiplexer  1004  receives a lock signal LCKB for controlling whether the switching transistor M_i is kept turned-on. 
     The amplifier  1000  is controlled by the triggering signal received by the first output pin PIN_ 1  of the Ith stage driving module  100 _ i  to compare the reference voltage V RF  with the output voltage V SUP . For example, the amplifier  1000  is an error amplifier or a variable gain amplifier (VGA), but the disclosure is not limited thereto. The first delay unit  1006  and the second delay unit  1014  delay a first time period T1 and a second time period T2 respectively. The detail of the first time period T1 and the second time period T2 will be described in  FIG. 4A  and  FIG. 4B  later. 
     When the input ends of the Muller C logic gate  1008  receive a low logic signal of ‘0’ at the same time, the output end of the Muller C logic gate  1008  outputs a low logic signal of ‘0’. When the input ends of the Muller C logic gate  1008  receive a high logic signal of ‘1’ at the same time, the output end outputs a high logic signal of ‘1’. When the input ends of the Muller C logic gate  1008  receive a high logic signal of ‘1’ and a low logic signal of ‘0’ respectively at the same time, the output end of the Muller C logic gate  1008  does not change. The multiplexer  1004  may be a path multiplexer (PMUX), and its truth table is shown in Table 1. 
     
       
         
           
               
               
               
             
               
                   
                 TABLE 1 
               
               
                   
                   
               
             
            
               
                   
                 UWV 
                 Z 
               
               
                   
                 1XX 
                 0 
               
               
                   
                 000 
                 B 
               
               
                   
                 001 
                 A 
               
               
                   
                 010 
                 B 
               
               
                   
                 011 
                 B 
               
               
                   
                   
               
            
           
         
       
     
     Referring to  FIG. 2 ,  FIG. 3 ,  FIG. 4A , and  FIG. 4B , operation sequences of the Ith stage driving module  100 _ i  are illustrated.  FIG. 4A  is a sequence diagram of the Ith stage driving module  100 _ i  in  FIG. 2  when the output voltage of the Ith stage driving module  100 _ i  is smaller than the reference voltage, and  FIG. 4B  is a sequence diagram of the Ith stage driving module  100 _ i  in  FIG. 2  when the output voltage of the Ith stage driving module  100 _ i  is larger than the reference voltage. 
     As shown in  FIG. 4A , when the first input pin PIN_ 1  of the Ith stage driving module  100 _ i  receives the triggering signal sent by the first output pin PIN_ 2  of the (I−1)th stage driving module  100 _ i −1, and when the amplifier  1000  in the Ith stage driving module  100 _ i  determines that the output voltage V SUP  is smaller than the reference voltage V RF , the SR flip-flop  1002  controls the Q end to reduce the output voltage at time point t1. Therefore, the voltage of the output end OUT_i reduces, and the switching transistor M_i of the Ith stage driving module  100 _ i  is then turned on. After the first time period T1 and the second time period T2, the Z end of the multiplexer  1004  outputs the triggering signal to the first output pin PIN_ 2  of the Ith driving module  100 _ i . In other words, when the Ith stage driving module  100 _ i  determines that the output voltage V SUP  is smaller than the reference voltage V RF , the Ith stage driving module  100 _ i  turns on the switching transistor M_i, which corresponds to the Ith stage driving module  100 _ i , to increase the output voltage V SUP , and sends the triggering signal to the (I+1)th stage driving module  100 _ i +1 after a preset period. 
     As shown in  FIG. 4B , when the first input pin PIN_ 1  of the Ith stage driving module  100 _ i  receives the triggering signal sent by the first output pin PIN_ 2  of the (I−1)th stage driving module  100 _ i −1, and when the amplifier  1000  in the Ith stage driving module  100 _ i  determines that the output voltage V SUP  is larger than the reference voltage V RF , the SR flip-flop  1002  increases the voltage outputted by the Q end at time point t1, so that the voltage of the output end OUT_i increases. The switching transistor M_i corresponding to the Ith stage driving module  100 _ i  is then turned off. After the first time period T1 and the second time period T2, the second output pin PIN_ 4  of the driving module  100 _ i  outputs the triggering signal. 
     In other words, when the Ith stage driving module  100 _ i  determines that the output voltage V SUP  is larger than the reference voltage V RF , the Ith stage driving module  100 _ i  feeds the triggering signal back to the second input pin PIN_ 3  of the (I−2)th stage driving module  100 _ i −2, and the (I−2)th stage driving module  100 _ i −2 transfers the triggering signal to the (I−1)th stage driving module  100 _ i −1. Therefore, the (I−1)th stage driving module  100 _ i −1 turns off the switching transistor M_i−1, which corresponds to the (I−1)th stage driving module  100 _ i −1, according to the comparison between the reference voltage V RF  and the output voltage V SUP  in order to reduce the output voltage V SUP . 
     Furthermore, after the (I−1)th stage driving module  100 _ i −1 turns off the switching transistor M_i−1 corresponding to the (I−1)th stage driving module  100 _ i −1, the (I−1)th stage driving module  100 _ i −1 feeds the received triggering signal back to the (I−3)th stage driving module  100 _ i −3, and then the (I−3)th stage driving module  100 _ i −3 transfers the triggering signal to the (I−2)th stage driving module  100 _ i −2. 
     To more clearly illustrate the operation of the driving modules  100 _ 1  to  100 _ n  in  FIG. 2 , a sequence diagram of the control circuit in  FIG. 2  is shown in  FIG. 5 . In one embodiment, the number of the driving modules  100 _ 1  to  100 _ n  is at least ten, so n is larger than or equal to ten. 
     As shown in  FIG. 5 , when the first input pin PIN_ 1  of the first reflecting module  102  has not received the enabling signal EN yet, the output ends OUT_ 1  to OUT_n of the driving modules  100 _ 1  to  100 _ n  are in high voltage level, so the switching transistors M_ 1  to M_n are turned off and the output voltage V SUP  is zero. When the first input pin PIN_ 1  of the first reflecting module  102  receives the enabling signal EN, the first output pin PIN_ 2  of the first reflecting module  102  provides a triggering signal Req 0  to the first stage driving module  100 _ 1 . According to the triggering signal Req 0 , the first stage driving module  100 _ 1  knows that the output voltage V SUP  is smaller than the reference voltage V RF , and then reduces the voltage level of the output end OUT_ 1  at the time point t1. Therefore, the switching transistor M_ 1  is turned on, and provides a triggering signal Req 1  to the first input pin PIN_ 1  of the second stage driving module  100 _ 2  through the first output pin PIN_ 2  of the first stage driving module  100 _ 1 . The operation of the second stage driving modules  100 _ 2  to the seventh stage driving module  100 _ 7  can be deduced by analogy. 
     When the first output pin PIN_ 2  of the eighth stage driving module  100 _ 8  provides a triggering signal Req 8  to the first input pin PIN_ 1  of the ninth stage driving module  100 _ 9 , the ninth stage driving module  100 _ 9  will know that the output voltage V SUP  during the time period between the time points t3 and t4 is still smaller than the reference voltage V RF , and then reduces the voltage level of the output end OUT_ 9  at the time point t4. Therefore, the switching transistor M_ 9  is turned on, the output voltage V SUP  increases, and the ninth stage driving module  100 _ 9  provides a triggering signal Req 9  to the tenth stage driving module  100 _ 10 . 
     When the first input pin PIN_ 1  of the tenth stage driving module  100 _ 10  receives the triggering signal Req 9 , the tenth stage driving module  100 _ 10  will know that the output voltage V SUP  is larger than the reference voltage V RF  during the time period between the time points t4 and t5. Therefore, the tenth stage driving module  100 _ 10  does not change the voltage level of the output end OUT  10  so that the output voltage V SUP  is remained. Moreover, the tenth stage driving module  100 _ 10 , through the second output pin PIN_ 4 , feeds a triggering signal Brq 10  back to the second input pin PIN_ 3  of the eighth stage driving module  100 _ 8 , so that the eighth stage driving module  100 _ 8  transfers the triggering signal Brq 10  to the ninth stage driving module  100 _ 9 . 
     When the first input pin PIN_ 1  of the ninth stage driving module  100 _ 9  receives the triggering signal Brq 10  sent by the tenth stage driving module  100 _ 10 , the ninth stage driving module  100 _ 9  will know that the output voltage V SUP  is larger than the reference voltage V RF  during the time period between the time points t5 and t6. Therefore, the ninth stage driving module  100 _ 9  increases the voltage level of the output end OUT_ 9  at the time point t6 to turn off the switching transistor M_ 9  to decrease the output voltage V SUP . The ninth stage driving module  100 _ 9 , through the second output pin PIN_ 4 , sends the triggering signal Brq 9  back to the second input pin PIN_ 3  of the seventh driving module  100 _ 7 , so that the seventh driving module  100 _ 7  further transfers the triggering signal Brq 9  to the eighth stage driving module  100 _ 8 . 
     When the first input pin PIN_ 1  of the eighth stage driving module  100 _ 8  receives the triggering signal Brq 9  sent by the ninth stage driving module  100 _ 9 , since the switching transistor M_ 8 , which corresponds to the eighth stage driving module  100 _ 8 , has been turned on, the eighth stage driving module may directly provide the triggering signal Req 8  to the ninth stage driving module  100 _ 9 . 
     When the ninth stage driving module  100 _ 9  receives the triggering signal Req 9 , the ninth stage driving module  100 _ 9  will know that the output voltage V SUP  is smaller than the reference voltage V RF  during the time period between the time points t7 and t8. Also, the ninth stage driving module  100 _ 9  decreases the voltage level of the output end OUT_ 9  at the time point t8 to turn on the switching transistor M_ 9  to increase the output voltage V SUP . The ninth stage driving module  100 _ 9  then provides the triggering signal Req 9  to the tenth stage driving module  100 _ 10 . 
     In this way, since the switching transistor M_ 9  is continually and alternately turned on and off, the output voltage V SUP  of the voltage regulator  1  oscillates based on the reference voltage V RF , as shown in the voltage oscillation area A 1  in  FIG. 5 . 
     Furthermore, when the output voltage V SUP  approaches the reference voltage V RF  and one of the switching transistors M_ 1  to M_n is repeatedly switched between on and off, the voltage regulator  1  keeps the switching transistor on to stabilize the output voltage V SUP  so that the energy spent for repeatedly switching the switching transistor between on and off is saved. For example, in  FIG. 5 , when the voltage regulator  1  determines that the switching transistor M_ 9  is repeatedly switched between on and off, the voltage regulator  1  disables the lock signal LCKB at the time point t13 to keep the switching transistor M_ 9  on to stabilize the output voltage V SUP  which Herein, the output voltage V SUP  is slightly larger than the reference voltage V SUP . Moreover, when the switching transistor M_ 9  keeps on, the ninth driving module  100 _ 9 , which corresponds to the switching transistor M_ 9 , stops transferring the triggering signal. 
     In the disclosure, there is no limitation on the increase range of the output voltage V SUP  when each of the switching transistors M_ 1  to M_n is turned on. The driving current provided by the Ith driving module  100 _ i  is not related to the driving current provided by the driving module  100 _ i −1 and the driving current provided by the driving module  100 _ i +1. 
     Thereinafter, according to one or more embodiments, the disclosure also provides a control method of the voltage regulator  1  in  FIG. 1 . The control method is adapted to dynamically adjust the output voltage V SUP  outputted by the voltage regulator  1 . 
     Referring to  FIG. 1  and  FIG. 6 , a flow chart of the control method of the voltage regulator  1  in one embodiment is illustrated. The voltage regulator  1  comprises a plurality of switching transistors M_ 1  to M_n and a control circuit  10 . Each of the switching transistors M_ 1  to M_n comprises a first end, a second end, and a control end. The first ends of the switching transistors M_ 1  to M_n receive the driving voltage V DD . The second ends of the switching transistors M_ 1  to M_n are electrically connected with the nodes which supply the output voltage V SUP . The control ends of the switching transistors M_ 1  to M_n are electrically connected with the control circuit  10 , so the switching transistors M_ 1  to M_n are controlled by the control circuit  10 . 
     In step S 600 , the voltage regulator  1  feeds the output voltage V SUP  back to the control circuit  10 . Moreover, the voltage regulator  1  provides the reference voltage V RF  to the control circuit  10 . In step S 602 , the control circuit  10  compares the output voltage V SUP  with the reference voltage V RF . Lastly, in step S 604 , the control circuit  10  selectively turns the switch transistors M_ 1  to M_n on or off according to the comparison between the output voltage V SUP  and the reference voltage V RF  so that the output voltage V SUP  approaches the reference voltage V RF . 
     In the step S 602 , when the output voltage V SUP  is smaller than the reference voltage V RF , the control circuit  10  turns on one or more of the switching transistors M_ 1  to M_n until the output voltage V SUP  is larger than the reference voltage V RF . In contrast, when the output voltage V SUP  is larger than the reference voltage V RF , the control circuit  10  turns off one or more of the switching transistors M_ 1  to M_n until the output voltage V SUP  is smaller than the reference voltage V RF . 
     When the output voltage V SUP  approaches the reference voltage V RF  and one of the switching transistors M_ 1  to M_n is repeatedly switched between on and off, the control circuit  10  keeps the one of the switching transistors M_ 1  to M_n on to stabilize the output voltage V SUP . 
     Referring to  FIG. 1  and  FIG. 7 , a flow chart of the control method of the voltage regulator  1  in other embodiment is illustrated. In step S 700 , the voltage regulator  1  feeds the output voltage V SUP  back to the control circuit  10 . In step S 702 , the control circuit  10  determines whether the output voltage V SUP  is larger than the reference voltage V RF . When the control circuit  10  determines that the output voltage V SUP  is smaller than the reference voltage V RF , as shown in step S 704 , the control circuit  10  sequentially turns on the switching transistors M_ 1  to M_n to increase the output voltage V SUP . When the control circuit  10  determines that the output voltage V SUP  is larger than the reference voltage V RF , the control circuit  10  sequentially turns off the switching transistors M_ 1  to M_n to decrease the output voltage V SUP  as shown in step S 706 , and the control method returns to the step S 702 . 
     Follow the step S 704 , in step S 708 , the control circuit  10  determines whether one of the switching transistors M_ 1  to M_n is repeatedly switched between on and off. If the control circuit  10  determines that one of the switching transistors M_ 1  to M_n has been repeatedly switched between on and off over a preset number of times, the control circuit  10  keeps this switching transistor on to stabilize the output voltage V SUP  as shown in step S 710 . If the control circuit  10  determines that one of the switching transistors M_ 1  to M_n has not been repeatedly switched between on and off over the preset number of times, the control method returns to the step S 702 . 
     In view of the embodiments of the voltage regulator and the control method thereof, through monitoring the change of the output voltage, the control circuit may dynamically adjust the number of the switching transistors which are turned on to make the output voltage of the voltage regulator approach the reference voltage. Moreover, since the driving modules correspond to the switching transistors in the control circuit, the driving modules may operate through certain driving events so that the voltage regulator does not require a fixed clock signal to operate normally. Thus, there is only one driving module operating at a time point, and the static work current of the other driving modules is close to zero. This may not only reduce the waste of current in the control circuit but also prevent the occurrence of the inrush current.