Patent Publication Number: US-2010131747-A1

Title: Information processing system, information processing apparatus, information processing method, and storage medium

Description:
CROSS REFERENCE OF RELATED APPLICATION 
     The disclosure of Japanese Patent Application No. 2008-277730 filed on Oct. 29, 2008 is incorporated herein by reference. 
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to an information processing system, an information processing apparatus, an information processing method, and a storage medium. More specifically, the present invention relates to an information processing system, an information processing apparatus, an information processing method, and a storage medium which utilize a secure semiconductor memory. 
     2. Description of the Related Art 
     One example of a related art is disclosed in Patent Document 1 (Japanese Patent Application Laid-Open No. 2006-146608 [G06F 21/24, G11C 16/02]). According to the Patent Document 1, the information processing apparatus generates key data by utilizing encryption original data read from a semiconductor memory and encryption generation data stored inside itself, and temporarily stores the key data in a storing portion. The information processing apparatus transmits data encrypted by utilizing the key data to the semiconductor memory, and the semiconductor memory, receiving the data, executes a command decrypted by utilizing the similarly key data. This makes it possible to make a data communication only between the predetermined semiconductor memory and the information processing apparatus. 
     However, in a case that a key the same as the key used in the predetermined semiconductor memory (referred to as “semiconductor memory X”, for the sake of convenience of description) for the information processing apparatus (“information processing apparatus A”, for the sake of convenience of description) of the Patent Document 1 is utilized in another semiconductor memory Y for another information processing apparatus B being compatible with the information processing apparatus A, if the key is known to others, security of both of the semiconductor memory X and the semiconductor memory Y may be lost. In order to avoid this, if a security function, such as using different keys between the semiconductor memory X and the semiconductor memory Y with the information processing apparatus B and the information processing apparatus A compatible with each other, is provided, the costs relating to the development is huge, such as long time and large costs for the development. 
     SUMMARY OF THE INVENTION 
     Therefore, it is a primary object of the present invention to provide a novel information processing system, a novel information processing apparatus, a novel information processing method, and a novel storage medium. 
     Another object of the present invention is to provide an information processing system, an information processing apparatus, an information processing method, and a storage medium which are able to ensure high security with costs related to the development kept as low as possible. 
     The present invention employs following features in order to solve the above-described problems. It should be noted that reference numerals and the supplements inside the parentheses show one example of a corresponding relationship with the embodiments described later for easy understanding of the present invention, and do not limit the present invention. 
     A first invention is an information processing system having a first information processing apparatus, a second information processing apparatus being compatible with the first information processing apparatus, a first storage medium capable of being attached to and detached from the first information processing apparatus and the second information processing apparatus, and a second storage medium capable of being attached to and detached from at least the second information processing apparatus and being different from the first storage medium, wherein the first information processing apparatus comprises: a first issuing means for encrypting a content mode shifting command to shift to a content mode allowing access to content data stored in the attached storage medium by utilizing first key data, and issuing the same to the storage medium; and a first receiving means for issuing a reading command to the attached storage medium by executing a first predetermined program, and receiving read data output from the storage medium, the first storage medium comprises: a first key data memory area for storing the first key data; a first content data memory area for storing first content data; and a first controller for, when the encrypted content mode shifting command from the attached information processing apparatus is received, shifting to the content mode by decrypting the encrypted content mode shifting command by utilizing the first key data and executing the same, and for, when the reading command with respect to the content memory area is received from the attached information processing apparatus, not responding to the reading command before shifting to the content mode and outputting the read data to the information processing apparatus after shifting to the content mode, the second information processing apparatus comprises: a medium determining means for determining whether the attached storage medium is the first storage medium or the second storage medium; a second issuing means for, when the medium determining means determines to be the first storage medium, encrypting a content mode shifting command to sift to the content mode by utilizing the first key data and issuing the same to the first storage medium, and for, when the medium determining means determines to be the second storage medium, encrypting the content mode shifting command to shift to the content mode by utilizing second key data different from the first key data and issuing the same to the second storage medium; and a second receiving means for issuing a reading command to the attached storage medium by executing a second predetermined program different from the first predetermined program, and receiving read data output from the storage medium, and the second storage medium compromises: a second key data memory area for storing the second key data; a second content data memory area for storing second content data; and a second controller for, when the encrypted content mode shifting command is received from the attached second information processing apparatus, shifting to the content mode by decrypting the encrypted content mode shifting command by utilizing the second key data and executing the same, and for, when the reading command with respect to the content data memory area is received from the attached second information processing apparatus, not responding to the reading command before shifting to the content mode, and outputting read data to the second information processing apparatus after shifting to the content mode. 
     In the first invention, an information processing system ( 10 ) has a first information processing apparatus ( 12 ), a second information processing apparatus ( 14 ) being compatible with the first information processing apparatus, a first storage medium ( 16 ) capable of being attached to and detached from the first information processing apparatus and the second information processing apparatus, and a second storage medium ( 18 ) capable of being attached to and detached from at least the second information processing apparatus and being different from the first storage medium. 
     The first information processing apparatus includes a first issuing means ( 20 , S 35 , S 37 , S 39 ) and a first receiving means ( 20 , S 1 , S 7 , S 19 , S 21 , S 23 , S 31 , S 49 , S 51 , S 53 , S 61 ). The first issuing means encrypts a content mode shifting command to shift to a content mode allowing access to content data stored in the attached storage medium ( 16 ,  18 ) by utilizing first key data, and issues the same to the storage medium. The first receiving means issues a reading command to the attached storage medium by executing a first predetermined program (IPL), and receives read data (encryption key original data, content data) output from the storage medium. 
     The first storage medium includes a first key data memory area ( 42   c ,  62 ), a first content data memory area ( 42   b ,  66 ), and a first controller ( 40 ). The first key data memory area stores the first key data. The first content data memory area stores first content data. The first controller, when the encrypted content mode shifting command from the attached information processing apparatus ( 12 ,  14 ) is received, shifts to the content mode by decrypting the encrypted content mode shifting command by utilizing the first key data and executing the same, and, when the reading command with respect to the content memory area is received from the attached information processing apparatus, does not respond to the reading command before shifting to the content mode and outputs the read data to the information processing apparatus after shifting to the content mode. 
     The second information processing apparatus includes a medium determining means ( 20 , S 113 ), a second issuing means ( 20 , S 35 , S 37 , S 39 , S 179 ,  5181 , S 183 ), and a second receiving means ( 20 , S 19 , S 21 , S 23 , S 31 , S 49 , S 51 , S 53 , S 61 ,  5101 , S 107 , S 121 , S 123 , S 125 , S 135 , S 145 , S 151 , S 163 , S 165 , S 167 , S 175 , S 193 , S 195 , S 197 , S 205 ). The medium determining means determines whether the attached storage medium is the first storage medium or the second storage medium. The second issuing means, when the medium determining means determines to be the first storage medium, encrypts a content mode shifting command to sift to the content mode by utilizing the first key data, and issues the same to the first storage medium, and when the medium determining means determines to be the second storage medium, encrypts the content mode shifting command to shift to the content mode by utilizing second key data different from the first key data, and issues the same to the second storage medium. The second receiving means issues a reading command to the attached storage medium by executing a second predetermined program different from the first predetermined program, and receives read data output from the storage medium. 
     The second storage medium includes a second key data memory area ( 42   c ,  70 ), a second content data memory area ( 42   b ,  74 ), and a second controller ( 40 ). The second key data memory area stores second key data. The second content data memory area stores second content data. The second controller, when the encrypted content mode shifting command is received from the attached second information processing apparatus, shifts to the content mode by decrypting the encrypted content mode shifting command by utilizing the second key data and executes the same, and when the reading command with respect to the content data memory area is received from the attached second information processing apparatus, does not respond to the reading command before shifting to the content mode, and outputs read data to the second information processing apparatus after shifting to the content mode. 
     According to the first invention, the encrypted command is transmitted, and there is the data in the information processing apparatus readable only when the mode shifts to the content mode, capable of ensuring high security. Furthermore, as to the second information processing apparatus being compatible with the first information processing apparatus, the first storage medium or the second storage medium can be attached, and if the first storage medium is attached, a command is encrypted by utilizing the first key data the same as that of the first information processing apparatus, capable of utilizing the same key data with compatibility kept. Accordingly, it is possible to keep costs related to the development, such as time and costs taken for the development as little as possible. 
     A second invention is according to the first invention, and the second storage medium is also attachable to the first information processing apparatus, and further comprises a first key data memory area for storing the first key data, the first issuing means of the first information processing apparatus issues a first encryption mode shifting command to shift to a first encryption mode for encrypting command and data with the storage medium, and transmitting and receiving the same, and then issues the content mode shifting command, the first controller of the first storage medium shifts to the first encryption mode by executing the first encryption mode shifting command, and shifts to the content mode by decrypting the received content mode shifting command by utilizing the first key data and executing the same in the first encryption mode, the second issuing means of the second information processing apparatus issues the first encryption mode shifting command to shift to the first encryption mode when the first storage medium is attached, and issues a second encryption mode shifting command to shift to a second encryption mode when the second storage medium is attached, the second controller of the second storage medium shifts to the first encryption mode by receiving and executing the first encryption mode shifting command, shifts to the content mode by decrypting the received content mode shifting command by utilizing the first key data and executing the same in the first encryption mode, or shifts to the second encryption mode by receiving and executing the second encryption mode shifting command, and shifts to the content mode by decrypting the received content mode shifting command by utilizing the second key data and executing the same in the second encryption mode. 
     In the second invention, the second storage medium is also attachable to the first information processing apparatus, and further comprises a first key data memory area ( 42   c ,  62 ) for storing the first key data. The first issuing means of the first information processing apparatus issues a first encryption mode shifting command to shift to a first encryption mode for encrypting command and data with the storage medium (S 11 , S 13 ), and transmitting and receiving the same, and then issues the content mode shifting command (S 35 , S 37 , S 39 ). The first controller of the first storage medium shifts to the first encryption mode by executing the first encryption mode shifting command (S 17 ), and shifts to the content mode (S 47 ) by decrypting the received content mode shifting command by utilizing the first key data and executing the same in the first encryption mode (S 45 ). The second issuing means of the second information processing apparatus issues the first encryption mode shifting command to shift to the first encryption mode (S 11 , S 13 ) when the first storage medium is attached, and issues a second encryption mode shifting command to shift to a second encryption mode (S 155 ,  5157 ) when the second storage medium is attached. The second controller of the second storage medium shifts to the first encryption mode (S 17 ) by receiving and executing the first encryption mode shifting command (S 15 ), shifts to the content mode (S 47 ) by decrypting the received content mode shifting command by utilizing the first key data (S 45 ) and executing the same in the first encryption mode, or shifts to the second encryption mode (S 161 ) by receiving and executing the second encryption mode shifting command (S 159 ), and shifts to the content mode (S 191 ) by decrypting the received content mode shifting command by utilizing the second key data (S 189 ) and executing the same in the second encryption mode. 
     According to the second invention, the second storage medium has a configuration the same as that of the first storage medium, and shifts to the content mode via the first encryption mode or the second encryption mode, and therefore, even if the second storage medium is attached to the first information processing apparatus, it can be used as it is. 
     A third invention is according to the second invention, and the first information processing apparatus issues a first content mode shifting command to shift to a first content mode, the second information processing apparatus issues the first content mode shifting command to shift to the first content mode when the first storage medium is attached, or issues a second content mode shifting command to shift to a second content mode when the second storage medium is attached, and the second controller of the second storage medium, when the first content mode shifting command is received, shifts to the first content mode by decrypting the first content mode shifting command by utilizing the first key data and executing the same, or when the second content mode shifting command is received, shifts to the second content mode by decrypting the second content mode shifting command by utilizing the second key data and executing the same. 
     In the third invention, the first information processing apparatus issues a first content mode shifting command to shift to a first content mode (S 35 , S 37 , S 39 ). The second information processing apparatus issues the first content mode shifting command to shift to the first content mode (S 35 , S 37 , S 39 ) when the first storage medium is attached, or issues a second content mode shifting command to shift to a second content mode (S 179 , S 181 , S 183 ) when the second storage medium is attached. The second controller of the second storage medium, when the first content mode shifting command is received (S 43 ), shifts to the first content mode (S 47 ) by decrypting the first content mode shifting command by utilizing the first key data (S 45 ) and executing the same, or when the second content mode shifting command is received (S 187 ), shifts to the second content mode (S 191 ) by decrypting the second content mode shifting command by utilizing the second key data (S 189 ) and executing the same. 
     According to the third invention, the second storage medium selectively shifts to the first content mode or the second content mode depending on the command applied from the information processing apparatus, so that the second storage medium can be attached to the first information processing apparatus. 
     A fourth invention is according to the second invention, and the first key data memory area of the first storage medium and the first key data memory area of the second storage medium are set to an identical start address. 
     In the fourth invention, the first key data memory area of the first storage medium and the first key data memory area of the second storage medium are set to an identical start address. That is, the same format is adopted. Here, the address means both of a logic address (virtual address) and a physical address. 
     According to the fourth invention, the first storage medium and the second storage medium adopt the same format, so that even if the first storage medium is attached to the second information processing apparatus, the first key data can be used as it is, and even if the second storage medium is attached to the first information processing apparatus, the first key data can be used as it is. 
     A fifth invention is according to the second, and second content data is constructed of third content data and fourth content data, the second content data memory area of the second storage medium includes a third content data memory area to store the third content data and a fourth content data memory area to store the fourth content data, and the second controller, when the first content mode shifting command is received, shifts to the first content mode by decrypting the first content mode shifting command by utilizing the first key data and executing the same, and makes the third content data memory area readable, or, when the second content mode shifting command is received, shifts to the second content mode by decrypting the second content mode shifting command by utilizing the second key data, and makes both of the third content data memory area and the fourth content data memory area readable. 
     In the fifth invention, the second content data is constructed of third content data and fourth content data. For example, the second content data memory area of the second storage medium includes a third content data memory area ( 66 ) to store the third content data and a fourth content data memory area ( 74 ) to store the fourth content data. The second controller, when the first content mode shifting command is received, shifts to the first content mode by decrypting the first content mode shifting command by utilizing the first key data and executing the same, and makes the third content data memory area readable. Or, the second controller, when the second content mode shifting command is received shifts to the second content mode by decrypting the second content mode shifting command by utilizing the second key data, and makes both of the third content data memory area and the fourth content data memory area readable. That is, if the second storage medium is attached to the first information processing apparatus, only the third content data memory area is made readable, and if the second storage medium is attached to the second information processing apparatus, the fourth content data memory area is made readable. 
     According to the fifth invention, depending on the information processing apparatus to which the second storage medium is attached, a readable memory area is differentiated, so that the content data only utilized in the first information processing apparatus and the content data only utilized in the second information processing apparatus can be separately stored. 
     A sixth invention is according to the fifth invention, and the second controller of the second storage medium makes the third content data memory area and the fourth content data memory area readable in the second content mode. 
     In the sixth invention, the second controller of the second storage medium makes the third content data memory area and the fourth content data memory area readable in the second content mode. Accordingly, the third content data memory area stores the content data as to the basic part to be utilized in the first information processing apparatus as well, and the fourth content data memory area stores the content data as to the additional part to be only utilized in the second information processing apparatus, for example. 
     According to the sixth invention, with respect to the second storage medium, the first information processing apparatus can read only the basic part, and the second information processing apparatus can read the additional part as well, for example. Accordingly, the second storage medium is configured by merely providing the fourth content data memory area to the first storage medium, capable of reducing times and costs related to the development. 
     A seventh invention is according to the fifth invention, and the third content data memory area of the second storage medium stores a first program being executable by the first information processing apparatus, and the fourth content data memory area of the second storage medium stores a second program being unexecutable by the first information processing apparatus and being executable by the second information processing apparatus. 
     In the seventh invention, the third content data memory area of the second storage medium stores a first program being executable by the first information processing apparatus. Furthermore, the fourth content data memory area of the second storage medium stores a second program being unexecutable by the first information processing apparatus and being executable by the second information processing apparatus. 
     According to the seventh invention, the first information processing apparatus can execute the first program, so that the first information processing apparatus can execute the first program with the second storage medium attached as it is. Furthermore, the second storage medium is configured by merely additionally storing the second program to be executed by the second information processing apparatus in the first storage medium, capable of reducing times and costs related to the developing as little as possible. 
     An eighth invention is according to the fifth, and the first content data memory area of the first storage medium and the third content data memory area of the second storage medium are set to an identical start address. 
     In the eighth invention, the first content data memory area of the first storage medium and the third content data memory area of the second storage medium are set to an identical start address. That is, the same format is adopted. Here, the address means a logic address (virtual address) and a physical address. 
     According to the eighth invention, the first storage medium and the second storage medium adopts the identical format, and therefore, even if the first storage medium is attached to the second information processing apparatus, the first program can be read as it is, and even if the second storage medium is attached to the first information processing apparatus, the first program can be read as it is. 
     A ninth invention is according to the eighth invention, and the first content data memory area of the first storage medium is a memory area after a first address onward, the third content data memory area of the second storage medium is a memory area from the first address to a second address, and the fourth content data memory area of the second storage medium is a memory area after the second address onward, wherein the second address is variable. 
     In the ninth invention, and the first content data memory area of the first storage medium is a memory area after a first address onward. Furthermore, the third content data memory area of the second storage medium is a memory area from the first address to a second address (boundary address), and the fourth content data memory area of the second storage medium is a memory area after the second address onward. The second address is variable. 
     In the ninth invention, a border is provided by the second address, and therefore, in a case that the second storage medium is attached to the first information processing apparatus, the first program can be executed by reading from the first address to the border, and in a case that the second storage medium is attached to the second information processing apparatus, the second program can be executed by reading the address after the border onward. Thus, even if the second storage medium is attached to the first information processing apparatus, it can be used as it is. 
     A tenth invention is according the ninth invention, and information of the second address is stored in a predetermined area of the second storage medium. 
     In the tenth invention, information of the second address is stored in a predetermined area ( 60 ) of the second storage medium. 
     According to the tenth invention, the second address is stored in the predetermined area of the second storage medium, so that freely setting the second address makes the second address variable. 
     An eleventh invention is according to the fifth, and the second controller of the second information processing apparatus accepts a first reading command in the first content mode, or accepts a second reading command in the second content mode. 
     In the eleventh invention, the second controller of the second information processing apparatus accepts a first reading command in the first content mode. Furthermore, the second controller accepts a second reading command in the second content mode. 
     According to the eleventh invention, depending on the mode, the command to be accepted is differentiated, a command other than a correct command is not to be accepted in each mode, resulting in high security. 
     A twelfth invention is according to the eleventh invention, and the reading command in the first content mode of the first controller of the first storage medium and the reading command in the first content mode of the second controller of the second storage medium are identical. 
     In the twelfth invention, the reading command in the first content mode of the first controller of the first storage medium and the reading command in the first content mode of the second controller of the second storage medium are identical. That is, even in the different storage mediums, the same command can be used in the same mode. 
     In the twelfth invention, even in the different storage mediums, the same command can be used in the same mode, so that it is possible to save time for a design variation at that part. Thus, it is possible to keep costs related to the development as little as possible. 
     A thirteenth invention is according to the first invention, the first controller of the first storage medium and the second controller of the second storage medium are started in a non-encryption mode not requiring decryption of the received command, then shifts to an encryption mode in response to a command from the attached information processing apparatus, and receives the encrypted content mode shifting command from the information processing apparatus in the encryption mode. 
     In the thirteenth invention, the first controller of the first storage medium and the second controller of the second storage medium are started in a non-encryption mode not requiring decryption of the received command, then shifts to an encryption mode in response to a command from the information processing apparatus attached with the first storage medium and the second storage medium, and receives the encrypted content mode shifting command from the information processing apparatus in the encryption mode. 
     According to the thirteenth invention, the encrypted command is transmitted and received, capable of ensuring high security. Furthermore, the mode is classified into the non-encryption mode and the encryption mode, so that it is possible to reduce processing in comparison with a case of only the encryption mode, capable of ensuring both of the security and the processing speed. 
     A fourteenth invention is according to the thirteenth invention, and the first controller of the first storage medium has a first encryption mode, and is capable of executing a first content mode shifting command in the first encryption mode, and the second controller of the second storage medium has the first encryption mode and a second encryption mode, and is capable of executing the first content mode shifting command in the first encryption mode, and is capable of executing a second content mode shifting command in the second encryption mode. 
     In the fourteenth invention, the first controller of the first storage medium has a first encryption mode, and is capable of executing a first content mode shifting command in the first encryption mode. On the other hand, the second controller of the second storage medium has the first encryption mode and a second encryption mode, and is capable of executing the first content mode shifting command in the first encryption mode, and is capable of executing a second content mode shifting command in the second encryption mode. That is, if the first storage medium is attached to either of the first information processing apparatus or the second information processing apparatus, it is possible to shift to the first content mode. Furthermore, if the second storage medium is attached to the first information processing apparatus, it is possible to shift to the first content mode, and if the second storage medium is attached to the second information processing apparatus, it is possible to shift to the second content mode. 
     According to the fourteenth invention, it is possible to attach each of the first storage medium and the second storage medium to both of the first information processing apparatus and the second information processing apparatus as it is. 
     A fifteenth invention is according to the fourteenth invention, and the first storage medium has a first secure area being accessible only in the first encryption mode, the second storage medium has the first secure area being accessible only in the first encryption mode and a second secure area being accessible only in the second encryption mode, and the second information processing apparatus issues the first encryption mode shifting command by the second issuing means irrespective of the attached storage medium being the first storage medium or the second storage medium, reads the data of the first secure area, and, in a case that the attached storage medium is the second storage medium, then issues the second encryption mode shifting command by the second issuing means to read the data of the second secure area, and further issues the second content mode shifting command. 
     In the fifteenth invention, the first storage medium has a first secure area ( 64 ) being accessible only in the first encryption mode, while the second storage medium has the first secure area ( 64 ) being accessible only in the first encryption mode and a second secure area ( 72 ) being accessible only in the second encryption mode. The second information processing apparatus issues the first encryption mode shifting command by the second issuing means irrespective of the attached storage medium being the first storage medium or the second storage medium, reads the data of the first secure area, and, in a case that the attached storage medium is the second storage medium, then issues the second encryption mode shifting command by the second issuing means to read the data of the second secure area, and further issues the second content mode shifting command. 
     According to the fifteenth invention, only when the second storage medium is attached to the second information processing apparatus, it is possible to shift to the second content mode, so that the data stored in the second content data memory area cannot be read by the first information processing apparatus and other information processing apparatuses, for example. That is, it is possible to inhibit an unlawful reading from occurring. 
     A sixteenth invention is according to the fifteenth invention, and the second issuing means, in a case that attached storage medium is the second storage medium, reads the data of the first secure area, and then controls turning on or off the power of the second storage medium or resets the second controller. 
     In the sixteenth invention, the second issuing means, in a case that attached storage medium is the second storage medium, reads the data of the first secure area, and then controls turning on or off the power of the second storage medium or resets the second controller. That is, the second issuing means returns the mode to the initial state once. 
     In the sixteenth invention, after reading the data in the first secure area, prior to reading the data of the second secure area, the mode is returned to the initial state once by turning on and off the power of the second storage medium, resetting the second storage medium, and so forth, so that the mode does not shift to the reverse direction. That is, it is possible to prevent unlawful reading of data by an unlawful access from occurring. This makes it possible to produce processing of accessing to the second storage medium without adding any change to the processing of accessing the first storage medium. Accordingly, it is possible to keep times and costs related to the development as little as possible. 
     A seventeenth invention is according to the first invention, and the second storage medium further includes an identification information memory area to store identification information of itself, and the second information processing apparatus determines whether or not the attached storage medium is the second storage medium depending on the presence or absence of the identification information. 
     In the seventeenth invention, the second storage medium further includes an identification information memory area ( 60 ) to store identification information of itself. The second information processing apparatus determines whether or not the attached storage medium is the second storage medium depending on the presence or absence of the identification information. 
     According to the seventeenth invention, the kind of the storage medium is determined depending on the presence or absence of the identification information, making the determination processing simple, and capable of appropriately shifting to the mode and issuing the command depending on the kind of the storage medium. 
     An eighteenth invention is according to the seventeenth invention, and the second information processing apparatus issues a reading command of the identification information stored in the identification information memory area to the attached storage medium on start-up, and the second controller of the second storage medium is accessible to the identification information memory area, but inaccessible to the first secure area and the second secure area on start-up. 
     In the eighteenth invention, the second information processing apparatus issues a reading command of the identification information stored in the identification information memory area to the attached storage medium on start-up. The second controller of the second storage medium is accessible to the identification information memory area, but inaccessible to the first secure area and the second secure area on start-up. For example, the second controller cannot access an area other than the identification information memory area on start-up. 
     According to the eighteenth invention, on start-up, only the area necessary when start-up, such the identification information memory area is made accessible, capable of ensuring high security. 
     A nineteenth invention is according to the first invention, the first key data memory area and the second key data memory area are inaccessible from outside. 
     According to the nineteenth invention, the first key data memory area and the second key data memory area are inaccessible from outside. That is, even if an instruction (command) of reading the first key data memory area and the second key data memory area is applied from the host computer to the controller of the storage medium, the instruction is not executed. 
     According to the nineteenth invention, with respect to even the predetermined apparatus such as the first information processing apparatus and the second information processing apparatus, the key data is not read according to an instruction from outside, capable of ensuring high security. 
     A twentieth invention is according to the first invention, and the information processing apparatus generates key data from encryption key original data read from the storage medium and encryption generation data stored inside the information processing apparatus. 
     In the twentieth invention, the information processing apparatus generates key data from encryption key original data read from the storage medium and encryption generation data stored inside the information processing apparatus. Accordingly, the information processing apparatus generates key data when needed, and deletes it when unneeded, for example. 
     In the twentieth invention, the key data is generated, and the risk of the key data being unlawfully read from the information processing apparatus is kept as low as possible, capable of ensuring high security. 
     The twenty-first invention is an information processing apparatus being configured to be detachable with a first storage medium having a first content data memory area storing first content data, and a second storage medium having a second content data memory area storing second content data, comprises: a medium determining means for determining whether the first storage medium is attached or the second storage medium is attached; a first issuing means for, when the medium determining means determines that the first storage medium is attached, encrypting a first content mode shifting command to shift to a first content mode allowing for access to the first content data stored in the first content data memory area by utilizing first key data, and issuing the same to the first storage medium; a first receiving means for receiving first read data output from the first storage medium in response to the first content mode shifting command being issued by the first issuing means; a second issuing means for, when the medium determining means determines that the second storage medium is attached, encrypting a second content mode shifting command to shift to a second content mode allowing for access to the second content data stored in the second content data memory area by utilizing second key data different from the first key data, and issuing the same to the second storage medium; and a second receiving means for receiving second read data output from the second storage medium in response to the second content mode shifting command issued by the second issuing means. 
     In the twenty-first invention as well, similar to the first invention, the encrypted command is transmitted, and there is the data readable only when the mode shifts to the content mode, capable of ensuring high security. 
     A twenty-second invention is information processing method of an information processing apparatus being configured to be detachable with a first storage medium having a first content data memory area storing first content data, and a second storage medium having a second content data memory area storing second content data, includes following steps of: (a) determining whether the first storage medium is attached or the second storage medium is attached; (b) encrypting a first content mode shifting command to shift to a first content mode allowing for access to the first content data stored in the first content data memory area by utilizing first key data, and issuing the same to the first storage medium when the step (a) determines that the first storage medium is attached; (c) receiving first read data output from the first storage medium in response to the first content mode shifting command being issued by the step (b); or (d) encrypting a second content mode shifting command to shift to a second content mode allowing for access to the second content data stored in the second content data memory area by utilizing second key data different from the first key data, and issuing the same to the second storage medium when the step (a) determines that the second storage medium is attached; and (e) receiving second read data output from the second storage medium in response to the second content mode shifting command issued by the step (d). 
     In the twenty-second invention as well, similar to the first invention, the encrypted command is transmitted, and there is the data readable only when the mode shifts to the content mode, capable of ensuring high security. 
     A twenty-third invention is a storage medium storing an information processing program readable by a computer of an information processing apparatus being configured to be detachable with a first storage medium having a first content data memory area storing first content data, and a second storage medium having a second content data memory area storing second content data, the information processing program causes the computer of the information processing apparatus to function as: a medium determining means for determining whether the first storage medium is attached or the second storage medium is attached; a first issuing means for, when the medium determining means determines that the first storage medium is attached, encrypting a first content mode shifting command to shift to a content mode allowing access to the first content data stored in the first content data memory area by utilizing first key data, and issuing the same to the first storage medium; a first receiving means for receiving first read data output from the first storage medium in response to the first content mode shifting command being issued by the first issuing means; a second issuing means for, when the medium determining means determines that the second storage medium is attached, encrypting a second content mode shifting command to shift to a second content mode allowing for access to the second content data stored in the second content data memory area by utilizing second key data different from the first key data, and issuing the same to the second storage medium; and a second receiving means for receiving second read data output from the second storage medium in response to the second content mode shifting command issued by the second issuing means. 
     In the twenty-third invention as well, similar to the first invention, the encrypted command is transmitted, and there is the data readable only when the mode shifts to the content mode, capable of ensuring high security. 
     The above described objects and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is an illustrative view showing one embodiment of an information processing system of the present invention; 
         FIG. 2  is a block diagram showing an electric configuration of a first information processing apparatus and a first semiconductor memory shown in  FIG. 1 ; 
         FIG. 3  is a block diagram showing an electric configuration of a second information processing apparatus and a second semiconductor memory shown in  FIG. 1 ; 
         FIG. 4  is an illustrative view showing a memory map of a ROM provided to the first semiconductor memory shown in  FIG. 1 ; 
         FIG. 5  is an illustrative view showing a memory map of a ROM provided to the second semiconductor memory shown in  FIG. 1 ; 
         FIG. 6  is an illustrative view explaining a mode shifting of the semiconductor memory and a command from the information processing apparatus in a case that the first semiconductor memory or the second semiconductor memory is attached to the first information processing apparatus shown in  FIG. 1 ; 
         FIG. 7  is an illustrative view explaining a mode shifting of the second semiconductor memory and a command from the second information processing apparatus in a case that the second semiconductor memory is attached to the second information processing apparatus shown in  FIG. 1 ; 
         FIG. 8  is a table showing accessibility from the host computer ( 12 ,  14 ) to each memory area of the semiconductor memory in each mode; 
         FIG. 9  is an illustrative view showing a memory map of the ROM of the first semiconductor memory in a normal mode and a secure mode; 
         FIG. 10  is an illustrative view showing a memory map of the ROM of the first semiconductor memory in an application mode; 
         FIG. 11  is an illustrative view showing a memory map of the ROM of the second semiconductor memory in a normal mode; 
         FIG. 12  is an illustrative view showing a memory map of the ROM of the second semiconductor memory in a secure mode; 
         FIG. 13  is an illustrative view showing a memory map of the ROM of the second semiconductor memory in the application mode; 
         FIG. 14  is an illustrative view showing a memory map of the ROM of the second semiconductor memory in a secure  2  mode; 
         FIG. 15  is an illustrative view showing a memory map of the ROM of the second semiconductor memory in an application  2  mode; 
         FIG. 16  is a flowchart showing a first part of boot processing by the first information processing apparatus and the semiconductor memory; 
         FIG. 17  is a flowchart sequel to  FIG. 16  showing a second part of the boot processing by the first information processing apparatus and the semiconductor memory; 
         FIG. 18  is a flowchart sequel to  FIG. 17  showing a third part of the boot processing by the first information processing apparatus and the semiconductor memory; 
         FIG. 19  is a flowchart sequel to  FIG. 18  showing a fourth part of the boot processing by the first information processing apparatus and the semiconductor memory; 
         FIG. 20  is a flowchart sequel to  FIG. 19  showing a fifth part of the boot processing by the first information processing apparatus and the semiconductor memory; 
         FIG. 21  is a flowchart showing a first part of boot processing by the second information processing apparatus and the semiconductor memory; 
         FIG. 22  is a flowchart sequel to  FIG. 21  showing a second part of the boot processing by the second information processing apparatus and the semiconductor memory; 
         FIG. 23  is a flowchart sequel to  FIG. 22  showing a third part of the boot processing by the second information processing apparatus and the semiconductor memory; 
         FIG. 24  is a flowchart sequel to  FIG. 23  showing a fourth part of the boot processing by the second information processing apparatus and the semiconductor memory; 
         FIG. 25  is a flowchart sequel to  FIG. 24  showing a fifth part of the boot processing by the second information processing apparatus and the semiconductor memory; 
         FIG. 26  is a flowchart sequel to  FIG. 25  showing a sixth part of the boot processing by the second information processing apparatus and the semiconductor memory; 
         FIG. 27  is a flowchart sequel to  FIG. 26  showing a seventh part of the boot processing by the second information processing apparatus and the semiconductor memory; and 
         FIG. 28  is a flowchart sequel to  FIG. 27  showing an eighth part of the boot processing by the second information processing apparatus and the semiconductor memory. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Referring to  FIG. 1 , an information processing system  10  of this embodiment includes a first information processing apparatus  12  and a second information processing apparatus  14 . The first information processing apparatus  12  and the second information processing apparatus  14  are for utilizing a program (application program) and data stored in a semiconductor memory ( 16 ,  18 ) to be described later, and are applied to a general-purpose computer, a FDA (Personal Digital Assistant) and a cellular phone, for example. 
     Furthermore, the information processing system  10  includes the first semiconductor memory  16  and the second semiconductor memory  18 . Although illustration is omitted, the first semiconductor memory  16  and the second semiconductor memory  18  are configured to be attached to and detached from the first information processing apparatus  12  and the second information processing apparatus  14 . The first semiconductor memory  16  and the second semiconductor memory  18  is a storage medium for storing a program and data (hereinafter correctively referred to as “content data”) prohibiting an unlawful computer access, that is, being protected by copyright. Thus, the first semiconductor memory  16  and the second semiconductor memory  18  are made accessible to content data only by a predetermined apparatus, such as the first information processing apparatus  12  and the second information processing apparatus  14 . 
     Additionally, in this embodiment, the second information processing apparatus  14  is configured by upgrading the first information processing apparatus  12 , and is adapted to be able to directly read the first semiconductor memory  16  readable by the first information processing apparatus  12 . That is, the second information processing apparatus  14  is compatible with the first information processing apparatus  12 . Furthermore, as described later, the second semiconductor memory  18  includes a configuration being equal to the first semiconductor memory  16 , and has an area storing content data necessary by only the second information processing apparatus  14  (see  FIG. 4  and  FIG. 5 ). 
       FIG. 2  is a block diagram showing an electric configuration in a case that the first semiconductor memory  16  is attached to the first information processing apparatus  12 .  FIG. 3  is a block diagram showing an electric configuration in a case that the second semiconductor memory  18  is attached to the second information processing apparatus  14 . As understood from  FIG. 2  and  FIG. 3 , the first information processing apparatus  12  and the second information processing apparatus  14  are constructed of the same circuit components, and the first semiconductor memory  16  and the second semiconductor memory  18  are constructed of approximately the same circuit components. Thus,  FIG. 2  is explained in detail, and  FIG. 3  is explained as to the point different from  FIG. 2  in detail. 
     It should be noted in  FIG. 2  and  FIG. 3 , the same reference numerals are given to the circuit components having the same function. 
     As shown in  FIG. 2 , the first information processing apparatus  12  includes a CPU  20 , and the CPU  20  is connected with a ROM  22 , a RAM  24  and an input-output terminal  26 . Each of the ROM  22 , the RAM  24  and the input-output terminal  26  is connected to the CPU  20  by utilizing an address bus and a data bus. In addition, the data bus is utilized for transmitting a command. This holds true for the embodiment hereafter. 
     The CPU  20  exerts the entire control over the first information processing apparatus  12 . Examples are to generate and transmit a command to be issued to the first semiconductor memory  16 , to generate encryption key data (common key k 1  data described later), and to develop the content data read from the first semiconductor memory  16  in the RAM  24  to execute a program. 
     The ROM  22  include a program memory area  22   a  and an encryption generation data memory area  22   b . The program memory area  22   a  stores an IPL (Initial Program Loader), and the IPL is activated when the power supply of the first information processing apparatus  12  is turned on. According to the IPL, the CPU  20  and a memory controlling circuit  40  of the first semiconductor memory  16  execute boot processing (see  FIG. 16-FIG .  20 ). Furthermore, the encryption generation data memory area  22   b  stores encryption generation data. The CPU  20  produces encryption key data (common key k 1  data) from the encryption generation data and encryption key original data applied from the first semiconductor memory  16 . Although detailed explanation is omitted, for example, the encryption generation data and the encryption key original data, being binary data, from which the encryption key data is generated through a predetermined arithmetic operation (addition and multiplication, etc.). 
     It should be noted that in this embodiment, the program memory area  22   a  and the encryption generation data memory area  22   b  are provided to the ROM  22 , but these may be stored in the separate ROMs. 
     The RAM  24  is utilized as a working area and a buffer area of the CPU  20 , and is also used for generating the above-described encryption key data, and (temporarily) storing data, such as the generated encryption key data and the content data read from the first semiconductor memory  16 . 
     The input-output terminal  26  is a connection terminal or a connector to be electrically connected to an input-output terminal  44  of the semiconductor memory  16 . Although illustration is omitted, the input-output terminal  26  and the input-output terminal  44  have pins (terminals) of the same number and the same arrangement (or the same array). 
     The first semiconductor memory  16  includes the memory controlling circuit  40 , and the memory controlling circuit  40  is connected with a ROM  42  and the input-output terminal  44 . The ROM  42  is connected to the memory controlling circuit  40  by utilizing a data bus  46   a  and an address bus  46   b . Similarly, the input-output terminal  44  is connected to the memory controlling circuit  40  by utilizing the data bus and the address bus. 
     The memory controlling circuit  40  exerts the entire control over the first semiconductor memory  16 . As understood with reference to  FIG. 2 , the memory controlling circuit  40  includes a command-identifying-and-reading circuit  40   a , an address-and-data-controlling circuit  40   b , a mode controlling circuit  40   c  and a decrypting circuit  40   d . Each of the address-and-data-controlling circuit  40   b , the mode controlling circuit  40   c  and the decrypting circuit  40   d  is connected to the command-identifying-and-reading circuit  40   a  by utilizing the command bus and the data bus. 
     The command-identifying-and-reading circuit  40   a  has a function of determining a decrypted command, and executing an operation corresponding to the identified command. For example, in a case that a command which is supplied from the first information processing apparatus  12 , and decrypted by the decrypting circuit  40   d  is a reading command (RD_DATA command) of the data memory area  42   b  provided to the ROM  42 , the command-identifying-and-reading circuit  40   a  executes the reading command. More specifically, the command-identifying-and-reading circuit  40   a  extracts an reading instruction code and reading address data from the reading command, and instructs the address-and-data-controlling circuit  40   b  to make the ROM  42  output a reading signal and a reading address in the data memory area  42   b  to thereby read the data stored in the data memory area  42   b , and receives the read data (read data). 
     Here, as described later, depending on the mode, the executable command is decided in advance. Thus, if the command-identifying-and-reading circuit  40   a  determines to be an unexecutable command, the command is ignored (the command is not responded). This makes it possible to prevent an unlawful access from the host computer (outside), such as other information processing apparatuses (except for the second information processing apparatus  14 ) except for the first information processing apparatus  12  from occurring. Furthermore, the command-identifying-and-reading circuit  40   a  can know a current mode according to an output from the mode controlling circuit  40   c.    
     Moreover, if the first semiconductor memory  16  is a normal mode, a command from the first information processing apparatus  12  is not encrypted and is not required to be subjected to decryption processing, and therefore, the command-identifying-and-reading circuit  40   a  identifies the command as it is, and executes the identified command. 
     The address-and-data-controlling circuit  40   b  controls reading of the data from the ROM  42  according to the command from the command-identifying-and-reading circuit  40   a . Here, as described later, the address to be read is decided depending on the mode (command) (see  FIG. 8-FIG .  10 ). Accordingly, even if a command designating an unlawful address is input, the address to be read is fixedly decided, so that the data is never read unlawfully. The address-and-data-controlling circuit  40   b  can know a current mode according to an output from the mode controlling circuit  40   c  as well. 
     The mode controlling circuit  40   c  determines which mode the first semiconductor memory  16  is, a normal mode (N MODE), a secure mode (S MODE) or an application mode (A MODE), and outputs the data of the determination result to the command-identifying-and-reading circuit  40   a  and the address-and-data-controlling circuit  40   b  as necessary. 
     The decrypting circuit  40   d  decrypts the encrypted command (encryption command) applied from the first information processing apparatus  12  via the command-identifying-and-reading circuit  40   a  by utilizing decryption key data read from the decryption key data memory area  42   c  described later, and applies the decrypted command to the command-identifying-and-reading circuit  40   a . In this embodiment, a common key system is adopted, and therefore, common key k 1  data is used as decryption key data, here. 
     As described above, the ROM  42  of the first semiconductor memory  16  includes an encryption key original data memory area  42   a , a data memory area  42   b , and a decryption key data memory area  42   c . The encryption key original data memory area  42   a  stores encryption key original data as original or source data for generating encryption key data (common key k 1  data) on the side of the first information processing apparatus  12 . In this embodiment, the encryption key original data is identical among the first semiconductor memories  16  storing the same content data. The data memory area  42   b  stores content data as described above. In addition, the decryption key data memory area  42   c  stores decryption key data (common key k 1  data here) as described above. 
     As described above,  FIG. 3  is a block diagram showing an electric configuration when the second semiconductor memory  18  is attached to the second information processing apparatus  14 . As shown in  FIG. 3 , the second information processing apparatus  14  is configured by circuit components having a function the same as the first information processing apparatus  12 . Here, boot processing (see  FIG. 21-FIG .  28 ) between the second information processing apparatus  14  and the second semiconductor memory  18  is different from the above-described boot processing ( FIG. 16-FIG .  20 ) between the first information processing apparatus  12  and the first semiconductor memory  16 , and therefore, in the second information processing apparatus  14 , an IPL different in content of the processing is stored in the program memory area  22   a  of the ROM  22 . 
     Furthermore, in the boot processing between the second information processing apparatus  14  and the second semiconductor memory  18 , the CPU  20  stores two kinds of encryption generation data in the encryption generation data memory area  22   b  for generating common key k 1  data and common key k 2  data in order to generate the encryption key data (common key k 1  data) to be used in the above-described boot processing between the first information processing apparatus  12  and the first semiconductor memory  16  and encryption key data (common key k 2  data) different therefrom. Hereafter, for the sake of convenience of description, the encryption generation data to generate the common key k 1  data is referred to as first encryption generating data, and the encryption generation data to generate the common key k 2  data is referred to as second encryption generating data. 
     In addition, with respect to the second semiconductor memory  18 , in the middle of the address bus  46   b , an address converting circuit  48  is provided. The address converting circuit  48  converts addresses within a reading range in order to make data from the address next to a boundary address (see  FIG. 5 ) described later onward unreadable in the second semiconductor memory  18 , and temporarily converts the address of the data stored in the area in order to read data stored of the area in the second semiconductor memory  18  where a direct access is not allowed. In this embodiment, the address converting circuit  48  sets the end address of the addresses to be read to the boundary address in response to a CHG_MODE command from the command-identifying-and-reading circuit  40   a  so as to make data from the address next to the boundary address onward unreadable in a case that the secure mode is set in the second semiconductor memory  18 . That is, the address of within the reading range is converted. Furthermore, in a case that the secure  2  mode is set, the address of the data stored in an S 2  Code area  72  is converted in response to a CHG 2 _MODE command from the command-identifying-and-reading circuit  40   a  so as to be moved to a S Code area  64  (see  FIG. 5 ). 
     Here, in a case that the second semiconductor memory  18  is attached to the first information processing apparatus  12 , and the application mode is set, the address converting circuit  48  sets the end address of the addresses to be read to the boundary address so as to make the data from the address next to the boundary address onward unreadable in response to an sCHG_MODE command from the command-identifying-and-reading circuit  40   a.    
     That is, with respect to the second semiconductor memory  18 , when a mode except for the secure mode, the application mode, and the secure  2  mode is set, the address converting circuit  48  never executes converting the address. That is, in the mode except for the secure mode, the application mode, and the secure  2  mode, the address converting circuit  48  is inactivated. 
     As shown in  FIG. 3 , in a case that the second semiconductor memory  18  is attached to the second information processing apparatus  14 , the CHG_MODE command and the CHG 2 _MODE command are input from the command-identifying-and-reading circuit  40   a  to the address converting circuit  48  to activate the address converting circuit  48  in the secure mode and secure  2  mode. 
     Although illustration is omitted, in a case that the second semiconductor memory  18  is attached to the first information processing apparatus  12 , the CHG_MODE command and the sCHG_MODE command are input from the command-identifying-and-reading circuit  40   a  to the address converting circuit  48  to activate the address converting circuit  48  in the secure mode and application mode. 
     In addition, with respect to the second semiconductor memory  18 , a boundary setting data memory area  42   d  is provided to the ROM  42 . In the boundary setting data memory area  42   d , data (boundary setting data) to decide a border between an A Code area  66  and a common key k 2  memory area  70  of the second semiconductor memory  18  is stored (see  FIG. 5 ). That is, the boundary setting data is data as to the end address (boundary address) of the A Code area  66 . In this embodiment, the setting of the boundary address can be changed by 4 bytes. Here, in this embodiment, the boundary setting data is decided at shipment of the second semiconductor memory  18  from the factory, and stored in the ROM  42 . Furthermore, if the boundary setting data is stored in a rewritable memory (EEPROM, flash memory, etc.) except for the ROM  42 , variable setting may be possible. 
     Although not understood from  FIG. 2  and  FIG. 3 , the data stored in the data memory area  42   b  and the decryption key data memory area  42   c  which are provided to the ROM  42  of the second semiconductor memory  18  are different from the data stored in the data memory area  42   b  and decryption key data memory area  42   c  which are provided in the ROM  42  of the first semiconductor memory  16 . 
     More specifically, the data memory area  42   b  of the second semiconductor memory  18  is provided with an S 2  Code area  72  and an A 2  Code area  74  (see  FIG. 4  and  FIG. 5 ) in addition to the data memory area  42   b  of the first semiconductor memory  16  (S Code area  64  and A Code area  66 ). That is, content data only used in the second information processing apparatus  14  is stored. 
     In addition, in the decryption key data memory area  42   c  of the second semiconductor memory  18 , decryption key data (common key k 1  data) the same as the decryption key data stored in the decryption key data memory area  42   c  of the first semiconductor memory  16  and decryption key data (common key k 2  data) different from the common key k 1  data are stored. 
     Furthermore, in the second semiconductor memory  18 , the mode controlling circuit  40   c  identifies a secure  2  mode (S 2  MODE) and an application  2  mode (A 2  MODE) in addition to the above-described normal mode, secure mode and application mode. In addition, the determination result of the mode in the mode controlling circuit  40   c  of the second semiconductor memory  18  is also applied to the decrypting circuit  40   d  in addition to the command-identifying-and-reading circuit  40   a  and the address-and-data-controlling circuit  40   b.    
     Although not understood from the drawing, the boundary setting data stored in the boundary setting data memory area  42   d  is also applied to the decrypting circuit  40   d . In this embodiment, in a case that the second semiconductor memory  18  is the secure  2  mode, the memory controlling circuit  40  (decrypting circuit  40   d ) starts reading from an address next to the address indicated by the boundary setting data (head address of the common key k 2  memory area  70  described later). Thus, the common key k 2  data as decryption key data is read. Here, in a case that the second semiconductor memory  18  is the secure mode, the memory controlling circuit  40  (decrypting circuit  40   d ) of the second semiconductor memory  18  starts reading from a head address of a common key k 1  memory area  62  described later (see  FIG. 5 ). That is, the decrypting circuit  40   d  of the second semiconductor memory  18  selects the decryption key data to be used (common key k 1  data, common key k 2  data) depending on the mode applied from the mode controlling circuit  40   c , and reads the selected decryption key data from the decryption key data memory area  42   c  of the ROM  42  to use the same in the decryption processing. 
     As described above, the first semiconductor memory  16  can also be attached to the second information processing apparatus  14 , and the second semiconductor memory  18  can also be attached to the first information processing apparatus  12 . Although illustration and detailed explanation are omitted, in a case that the first semiconductor memory  16  is attached to the second information processing apparatus  14 , the second information processing apparatus  14  executes boot processing similar to that of the first information processing apparatus  12 , and works similar to the first information processing apparatus  12 . That is, by upgrading the first information processing apparatus  12 , the function added by the second information processing apparatus  14  is not utilized. On the other hand, in a case that the second semiconductor memory  18  is attached to the first information processing apparatus  12 , the first information processing apparatus  12  only uses the parts in the second semiconductor memory  18  having a configuration the same as that of the first semiconductor memory  16 . Thus, reading the content data only used in the second information processing apparatus  14  is not executed. 
       FIG. 4  shows a memory map of the ROM  42  in the first semiconductor memory  16 , and  FIG. 5  shows a memory map of the ROM  42  in the second semiconductor memory  18 . As understood from  FIG. 4  and  FIG. 5 , the ROM  42  of the second semiconductor memory  18  includes a configuration the same as that of the ROM  42  of the first semiconductor memory  16 , and therefore, an explanation as to the common parts is omitted. 
     As shown in  FIG. 4 , the ROM  42  of the first semiconductor memory  16  includes a Boot area  60 , the common key k 1  memory area  62 , the S Code area  64  and the A Code area  66 . The Boot area  60  stores encryption key original data and data (address data) of the head addresses of the common key k 1  memory area  62 , the S Code area  64  and the A Code area  66 . That is, the encryption key original data memory area  42   a  shown in  FIG. 2  is provided in the Boot area  60 . 
     The common key k 1  memory area  62  is an area to store common key k 1  data, and corresponds to the above-described decryption key data memory area  42   c . The common key k 1  memory area  62  is an area to which a host computer, such as the first information processing apparatus  12  and the second information processing apparatus  14  cannot access. The S Code area  64  is a secure area to store data (content data) to be read in the secure mode. The A Code area  66  stores data (content data) to be read in the application mode. In the first semiconductor memory  16 , the area combined with the S Code area  64  and the A Code area  66  corresponds to the above-described data memory area  42   b.    
     As shown in  FIG. 5 , the memory map of the ROM  42  of the second semiconductor memory  18  is further provided with the common key k 2  memory area  70 , the S 2  Code area  72  and the A 2  Code area  74  in addition to the memory map of the ROM  42  of the first semiconductor memory  16 . 
     In the memory map of the ROM  42  of the second semiconductor memory  18 , the Boot area  60  stores the boundary setting data in addition to the above-described data. That is, the boundary setting data memory area  42   d  shown in  FIG. 3  is provided in the Boot area  60 . 
     The common key k 2  memory area  70  is an area to store the common key k 2  data, and inaccessible from the host computer ( 12 ,  14 ), such as the second information processing apparatus  14 . Accordingly, in the second semiconductor memory  18 , the area combined with the common key k 1  memory area  62  and the common key k 2  memory area  70  corresponds to the above-described decryption key data memory area  42   c.    
     The S 2  Code area  72  is a secure area similar to the S Code area  64 , and stores the data (content data) to be read in the secure  2  mode. Here, in this embodiment, the S 2  Code area  72  is made directly inaccessible in any modes in order to increase security. The A 2  Code area  74  stores data (content data) to be read in the application  2  mode. Accordingly, in the second semiconductor memory  18 , an area combined with the S Code area  64 , the A Code area  66 , the S 2  Code area  72 , and the A 2  Code area  74  corresponds to the above-described data memory area  42   b.    
     In this embodiment, as shown in  FIG. 6 , when the power of the first semiconductor memory  16  is turned on, the normal mode is set, and in response to a mode change command (CHG_MODE command, sCHG_MODE command), the normal mode (N MODE) shifts to the application mode (A MODE) via the secure mode (S MODE). However, the mode shifts to the reverse direction. This holds true for the second semiconductor memory  18  described later. Accordingly, after the power of the first semiconductor memory  16  is turned off once, when the power is turned on again, the initial mode, that is, the normal mode is set again. Here, in stead of the power of the first semiconductor memory  16  being turned off and on, the first semiconductor memory  16  may be reset. 
     Furthermore, as shown in  FIG. 6 , in the normal mode, the information processing apparatus (the first information processing apparatus  12  or the second information processing apparatus  14  in this embodiment) attached with the first semiconductor memory  16  issues an RD_DATA command or a CHG_MODE command to the first semiconductor memory  16 . The RD_DATA command is a command (reading command) to read the data of the designated address from the ROM  42  of the first semiconductor memory  16 . Here, the encryption key original data to generate encryption key data (common key k 1  data) is read. Furthermore, the CHG_MODE command is a command to shift the first semiconductor memory  16  to the secure mode. Accordingly, the first semiconductor memory  16  receives the CHG_MODE command in the normal mode, and shifts to the secure mode by executing the command. 
     Although the explanation is made on the mode shifting when the first semiconductor memory  16  is attached to first information processing apparatus  12  or the second information processing apparatus  14 , the mode shifts in the above-described manner when the second semiconductor memory  18  is attached to the first information processing apparatus  12  (see  FIG. 7 ). 
     In the secure mode, the information processing apparatus ( 12 ,  14 ) attached with the first semiconductor memory  16  issues an sRD_DATA command or an sCHG_MODE command to the first semiconductor memory  16 . It should be noted that the commands issued in the secure mode are encrypted by the above-described encryption key data (common key k 1  data, here). This is because that assuming that a, unlawful computer access occurs to the first semiconductor memory  16 , and the command is read, the command is made indecipherable. In this embodiment, a common key system is adopted, and by executing encryption algorithm (hereinafter referred to as “encryption algorithm 1”) in the common key system, a command is encrypted. 
     Since the encryption algorithm is already well known, the detailed explanation is omitted here. Moreover, one out of the plurality of encryption algorithms is enough to be adopted. 
     Accordingly, in the first semiconductor memory  16 , the encrypted command is decrypted by the decryption key data (common key k 1  data, here) the same as the encryption key data, and represented by a plain text. Here, the sRD_DATA command is a reading command to read the data of the designated address from the ROM  42  of the first semiconductor memory  16 . Furthermore, the sCHG_MODE command is a command to shift the first semiconductor memory  16  to the application mode. Accordingly, the first semiconductor memory  16  receives the encrypted sCHG_MODE command in the secure mode, and then shifts to the application mode by executing the sCHG_MODE command decrypted according to the encryption algorithm 1. 
     In addition, in the secure mode, the data to be transmitted from the first semiconductor memory  16  is encrypted by encryption algorithm (hereinafter referred to as “encryption algorithm 2”) different from the encryption algorithm 1. In this embodiment, the encryption algorithm 2 is scrambling processing. The reason why a separate use of the algorithms between the encryption algorithm 1 and the encryption algorithm 2 is that when only the encryption algorithm 1 is used, an enormous amount of processing needs a lot of time for the boot processing, resulting in the lack of practical uses. Accordingly, the encryption algorithm 1 is used at the part where high security is required (a part of the command in this embodiment). This holds true hereafter in this embodiment. Moreover, the data encrypted by the encryption algorithm 2 is decrypted by executing the processing reverse to the scrambling processing by the encryption algorithm 2. 
     In the application mode, the information processing apparatus ( 12 ,  14 ) attached with the first semiconductor memory  16  issues an aRD_DATA command to the first semiconductor memory  16 . Here, the aRD_DATA command is a reading command to read the data of the designated address from the ROM  42  of the first semiconductor memory  16 . It should be noted that in the application mode, the command issued from the information processing apparatus ( 12 ,  14 ) is encrypted by the encryption algorithm 2, and the data transmitted from the first semiconductor memory  16  is also encrypted by the encryption algorithm 2. 
     In this embodiment, in the secure mode and the application mode, the data transmitted from the first semiconductor memory  16  (this holds true for the second semiconductor memory  18  described later) is encrypted by the encryption algorithm 2, but the data may be transmitted as it is without executing the encryption. This is because that the command from the information processing apparatus ( 12 ,  14 ) is encrypted, and therefore, whether to encrypt or not as to the data from the first semiconductor memory  16  does not have a large impact on the level of the security. This holds true for the secure  2  mode and the application  2  mode described later. 
     Alternatively, as shown in  FIG. 7 , when the power of the second semiconductor memory  18  is turned on, the normal mode is set. As described above, in a case that the second semiconductor memory  18  is attached to the first information processing apparatus  12 , the normal mode shifts to the application mode via the secure mode. On the other hand, in a case that the second semiconductor memory  18  is attached to the second information processing apparatus  14 , the normal mode shifts to the secure mode, and then, the power of the second semiconductor memory  18  is turned off and on to set the normal mode again. Thereafter, the second semiconductor memory  18  shifts from the normal mode to the application  2  mode (A 2  MODE) via the secure  2  mode (S 2  MODE). 
     It should be noted that as to the normal mode and the secure mode, the same as when the first semiconductor memory  16  is attached to the first information processing apparatus  12  or the second information processing apparatus  14  can be applied, and therefore, a redundant explanation is omitted. In the mode shifting explained with reference to  FIG. 6 , the first semiconductor memory  16  is replaced with the second semiconductor memory  18 , and the first information processing apparatus  12  or the second information processing apparatus  14  is replaced with only the second information processing apparatus  14 . 
     In a case that the normal mode is set again, in the normal mode, as described above, the second information processing apparatus  14  issues the RD_DATA command to the second semiconductor memory  18  to thereby read the encryption key original data. This is because of generating the common key k 2  data to be utilized in the secure  2  mode. Next, in the normal mode, the second information processing apparatus  14  issues a CHG 2 _MODE command to the second semiconductor memory  18 . Here, the CHG 2 _MODE command is a command to shift the second semiconductor memory  18  from the normal to the mode secure  2  mode. Accordingly, the second semiconductor memory  18  receives the CHG 2 _MODE command in the normal mode, and then shifts to the secure  2  mode by executing the command. 
     In the secure  2  mode, the second information processing apparatus  14  attached with the second semiconductor memory  18  issues an s 2 RD_DATA command or an s 2 CHG_MODE command to the second semiconductor memory  18 . Here, these commands are encrypted by utilizing the common key k 2  data according to the encryption algorithm 1. The s 2 RD_DATA command, here, is a reading data to read the data of the designated address from the ROM  42  of the second semiconductor memory  18 . The fact that data from the second semiconductor memory  18  is encrypted according to the encryption algorithm 2 is as described above. Furthermore, the s 2 CHG_MODE command is a command to shift the second semiconductor memory  18  to the application  2  mode. Accordingly, in the secure  2  mode, the second semiconductor memory  18  receives the encrypted s 2 CHG_MODE command, and shifts to the application  2  mode by executing the s 2 CHG_MODE command decrypted according to the encryption algorithm 1. 
     In the application  2  mode, the second information processing apparatus  14  attached with the second semiconductor memory  18  issues an a 2 RD_DATA command to the second semiconductor memory  18 . The a 2 RD_DATA command, here, is a command to read the data of the designated address from the ROM  42  of the second semiconductor memory  18 . It should be noted that as described above a command issued from the second information processing apparatus  14  is encrypted by the encryption algorithm 2, and data transmitted from the second semiconductor memory  18  is also encrypted by the encryption algorithm 2, in the application  2  mode. 
     The reason why the mode of the semiconductor memory (first semiconductor memory  16  and second semiconductor memory  18  in this embodiment) is shifted is to ensure high security. More specifically, an area of the ROM  42  accessible by the host computer (the first information processing apparatus  12  and the second information processing apparatus  14  in this embodiment) is different depending on the modes. A table showing whether or not to be accessible to each area of the ROM  42  shown in  FIG. 4  and  FIG. 5  is shown in  FIG. 8 . In  FIG. 8 , in each mode, a circle is placed in an area accessible from the host computer ( 12 ,  14 ), and a cross is placed in an area inaccessible from the host computer ( 12 ,  14 ). It should be noted that the secure  2  mode and the application  2  mode are restrictedly applied to a case that the second semiconductor memory  18  is attached to the second information processing apparatus  14 . 
     In this embodiment, being accessible from the host computer ( 12 ,  14 ) means that the memory controlling circuit  40  can access the ROM  42  according to a request (command) from the host computer ( 12 ,  14 ). Furthermore, being inaccessible from the host computer ( 12 ,  14 ) means that the memory controlling circuit  40  does not accept a request from the host computer ( 12 ,  14 ), or the memory controlling circuit  40  does not access the ROM  42  even if there is a request. 
     As shown in  FIG. 8 , in the normal mode, the host computer (the first information processing apparatus  12  or the second information processing apparatus  14 ) is accessible to only the Boot area  60  of the ROM  42 . In the secure mode (S MODE), the host computer ( 12 ,  14 ) is accessible to the S Code area  64  and the A Code area  66  of the ROM  42 . In the application mode (A MODE), the host computer ( 12 ,  14 ) is accessible to the A Code area  66  of the ROM  42 . Noted, in the application mode, the host computer ( 12 ,  14 ) is made accessible to the Boot area  60  as well. 
     Furthermore, in the secure  2  mode (S 2  MODE), the host computer (second information processing apparatus  14  in this embodiment) is accessible to the A Code area  66 , the S 2  Code area  72 , and the A 2  Code area  74  of the ROM  42 . Then, in the application  2  mode (A 2  MODE), the host computer ( 14 ) is accessible to the A Code area  66  and the A 2  Code area  74  of the ROM  42 . It should be noted that in the application  2  mode, the host computer ( 14 ) may be made accessible to the Boot area  60  as well. 
     As understood from  FIG. 8 , in either mode, the host computer ( 12 ,  14 ) cannot access the common key k 1  memory area  62  and the common key k 2  memory area  70 . 
     More specifically, with reference to the memory map of the ROM  42  shown in  FIG. 9-FIG .  15 , an explanation is made on the accessible area and the inaccessible area. Here, each of  FIG. 9-FIG .  10  is a memory map of the ROM  42  of the first semiconductor memory  16 . Each of  FIG. 11-FIG .  15  is a memory map as to the ROM  42  of the second semiconductor memory  18 . 
     As shown in  FIG. 9(A) , in the normal mode, the host computer ( 12 ,  14 ) is accessible only to the Boot area  60  of the ROM  42  of the first semiconductor memory  16 . In the normal mode, the data reading command (RD_DATA command) designating the address of the Boot area  60  is applied from the host computer ( 12 ,  14 ) to the first semiconductor memory  16 . 
     It should be noted that in  FIG. 9-FIG .  15 , the unshaded area means that the host computer ( 12 ,  14 ) is accessible, and the shaded area means that the host computer ( 12 ,  14 ) is not accessible. 
     As shown in  FIG. 9(B) , in the secure mode, the host computer ( 12 ,  14 ) is accessible to the S Code area  64  and the A Code area  66  of the ROM  42  of the first semiconductor memory  16 . In the secure mode, the data reading command (sRD_DATA command) designating the address after the head address of the S Code area  64  onward is applied to the first semiconductor memory  16  from the host computer ( 12 ,  14 ). 
     As shown in  FIG. 10 , in the application mode, the host computer ( 12 ,  14 ) is accessible to the A Code area  66  of the ROM  42  of the first semiconductor memory  16 . In the application mode, the data reading command (aRD_DATA command) designating an address after the head address of the A Code area  66  onward is applied to the first semiconductor memory  16  from the host computer ( 12 ,  14 ). 
     Furthermore, as shown in  FIG. 11 , in the normal mode, the host computer ( 12 ,  14 ) is accessible to the Boot area  60  of the ROM  42  of the second semiconductor memory  18 . This is the same as the case shown in  FIG. 9(A) , and therefore, a redundant explanation is omitted. 
     As shown in  FIG. 12 , in the secure mode, the host computer ( 12 ,  14 ) is accessible to the S Code area  64  and the A Code area  66  of the ROM  42  of the second semiconductor memory  18 . In the secure mode, similar to the case shown in  FIG. 9(B) , the data reading command (sRD_DATA command) designating an address after the head address of the S Code area  64  onward is applied to the second semiconductor memory  18  from the host computer ( 12 ,  14 ). 
     However, in the secure mode (this holds true for the application mode described later) of the second semiconductor memory  18 , the memory controlling circuit  40  is inhibited to access to an address next to the boundary address onward in response to an instruction (command) from the host computer ( 12 ,  14 ). This is because that in the secure mode, only the S Code area  64  and the A Code area  66  are made accessible similar to the case of the first semiconductor memory  16 . This is due to a fact that the memory controlling circuit  40  to be used in the second semiconductor memory  18  is developed by adding a part of the circuit components to the memory controlling circuit  40  to be used in the first semiconductor memory  16 . That is, through the use of a common security circuit (the command-identifying-and-reading circuit  40   a  and the decrypting circuit  40   d ), the time and costs involved in developing is slashed as little as possible to make the costs related to the development as little as possible. 
     Accordingly, in the secure mode, the data reading command designating an address after the head address of the S Code area  64  onward is applied to the second semiconductor memory  18 , but the address converting circuit  48  defines the readable range so as to make only an address before the boundary address readable. 
     Furthermore, when the second semiconductor memory  18  is attached to the first information processing apparatus  12 , the CPU  20  of the first information processing apparatus  12  is accessible to the second semiconductor memory  18 , but the boundary address is set, and therefore, even if the secure mode or the application mode is set, an address next to the boundary address (common key k 2  memory area  70 , S 2  Code area  72 , A 2  Code area  74 ) onward is made inaccessible. 
     In the secure  2  mode and the application  2  mode described later, the second semiconductor memory  18  is attached to the second information processing apparatus  14 , and therefore, an address after the head address indicated by the command onward is made readable irrespective of the presence of the boundary address. However, as described above, the common key k 2  memory area  70  is an area to which an access from outside is originally inhibited, and the S 2  Code area  72  is an area to be read not from the physical address but from the logic address. 
     As shown in  FIG. 13 , in the application mode, the host computer (only 12) is accessible to the A Code area  66  of the ROM  42  of the second semiconductor memory  18 . In the application mode, the data reading command (aRD_DATA command) designating an address after the head address of the A Code area  66  onward is applied to the second semiconductor memory  18  from the host computer (only 12). However, as described above, the second semiconductor memory  18  shifts to the application mode only when the second semiconductor memory  18  is attached to the first information processing apparatus  12 , and a readable range so as to make only an address before the boundary address readable is defined by the address converting circuit  48  similar to the secure mode. 
     As shown in  FIG. 14 , in the secure  2  mode, the host computer (only 14) is accessible to the A Code area  66 , the S 2  Code area  72 , and the A 2  Code area  74  of the ROM  42  of the second semiconductor memory  18 . In the secure  2  mode, the data reading command (s 2 RD_DATA command) designating an address after the head address of the S Code area  64  onward is applied to the second semiconductor memory  18  from the host computer ( 14 ). However, as described above, it is impossible to directly access the S 2  Code area  72  in any mode. 
     Due to this, in the secure  2  mode, the S 2  Code area  72  is moved to the S Code area  64  by the address converting circuit  48 . That is, by converting the address, the S 2  Code area  72  is temporarily moved to the readable area ( 66 ) so as to be made accessible. Accordingly, the table shown in  FIG. 8  means that the 52 Code area  72  is made accessible by being moved to the S Code area  64 . As shown in  FIG. 15 , in the application  2  mode, the host computer ( 14 ) is accessible to the A Code area  66  and the A 2  Code area  74  of the ROM  42  of the second semiconductor memory  18 . In the application  2  mode, the data reading command designating an address after the head address of the A Code area  66  onward is applied from the host computer ( 14 ) to the second semiconductor memory  18 . Here, the common key k 2  memory area  70  and the S 2  Code area  72  is inaccessible from outside, so that only the A Code area  66  and the A 2  Code area  74  are accessible. 
     An explanation is made on the concrete boot processing with reference to flowcharts shown in  FIG. 16-FIG .  28 . 
       FIG. 16-FIG .  20  shows the flowchart showing the boot processing between the first information processing apparatus  12  (CPU  20 ) and the semiconductor memory  16 ,  18  (memory controlling circuit  40 ) in a case that the first information processing apparatus  12  is attached to the first semiconductor memory  16  or the second semiconductor memory  18 . Here, in this embodiment, once that the first semiconductor memory  16  or the second semiconductor memory  18  is attached to the first information processing apparatus  12 , the attached semiconductor memory ( 16 , 18 ) is not detached or replaced until the power of the first information processing apparatus  12  is turned off. 
     When the semiconductor memory  16 ,  18  is attached to the first information processing apparatus  12 , and the power of the first information processing apparatus  12  is turned on to start the IPL, the CPU  20  of the first information processing apparatus  12  starts the boot processing, and transmits the RD_DATA command to the semiconductor memory  16 ,  18  in a step S 1  as shown in  FIG. 16 . Although illustration is omitted, as described above, at a time of the power is turned on, the semiconductor memory ( 16 ,  18 ) is set to the normal mode. 
     The memory controlling circuit  40  of the semiconductor memory  16 ,  18  receives the RD_DATA command from the first information processing apparatus  12  in a next step S 3 , and executes the RD_DATA command and transmits the data of the address designated by the RD_DATA command to the first information processing apparatus  12  in a step S 5 . Here, the memory controlling circuit  40  reads data from the address of the ROM  42  indicated by RD_DATA command and transmits the read data to the first information processing apparatus  12 . 
     The CPU  20  of the first information processing apparatus  12  receives the data from semiconductor memory  16 ,  18  in a next step S 7 . Then, in a step S 11 , the encryption key data (common key k 1  data, here) is generated from the reception data (encryption key original data) and the encryption generation data (first encryption generating data, here), and other processing is executed. 
     It should be noted that the other processing in the step S 11  correspond to the initialization of the first information processing apparatus  12 , and so on. 
     In a following step S 13 , the CPU  20  of the first information processing apparatus  12  transmits the CHG_MODE command to the semiconductor memory  16 ,  18 . Thereupon, as shown in  FIG. 17 , the memory controlling circuit  40  of the semiconductor memory  16 ,  18  receives the CHG_MODE command in a step S 15 , and shifts to the S MODE by executing the CHG_MODE command in a step S 17 . That is, in the semiconductor memory  16 ,  18 , the S Code area  64  and the A Code area  66  are made accessible. Thereafter, the CPU  20  of the first information processing apparatus  12  generates the sRD_DATA command in a step S 19 , encrypts the sRD_DATA command by utilizing the common key k 1  data according to the encryption algorithm 1 in a step S 21 , and transmits the encrypted sRD_DATA command to the semiconductor memory  16 ,  18  in a step S 23 . 
     The memory controlling circuit  40  of the semiconductor memory  16 ,  18  receives the encrypted sRD_DATA command in a next step S 25 , decrypts the encrypted sRD_DATA command by utilizing the common key k 1  data according to the encryption algorithm 1 in a step S 27 , and executes the decrypted sRD_DATA command in astep S 29 . That is, in the step S 29 , the memory controlling circuit  40  of the semiconductor memory  16 ,  18  encrypts the data of the address designated by the sRD_DATA command according to the encryption algorithm 2 and transmits the same to the first information processing apparatus  12  at the same time. 
     Succeedingly, as shown in.  FIG. 18 , the CPU  20  of the first information processing apparatus  12  decrypts the data from the semiconductor memory  16 ,  18  according to the encryption algorithm 2 and receives the same at the same time in a step S 31 . Here, the content data stored in the S Code area  64  is received. Next, the CPU  20  of the first information processing apparatus  12  generates the sCHG_MODE command in a step S 35 , and encrypts the sCHG_MODE command by utilizing the common key k 1  data according to the encryption algorithm 1 in a step S 37 . 
     Then, the CPU  20  of the first information processing apparatus  12  transmits the encrypted sCHG_MODE command to the semiconductor memory  16 ,  18  in a step S 39 , and then erases the common key k 1  data from the RAM  24  in a step S 41 . The reason why the common key k 1  data is erased is that if there is an unlawful access to the RAM  24 , the risk of the common key k 1  data being read is made as low as possible. That is, when the common key k 1  data becomes unnecessary, it is erased. This holds true for the common key k 2  data described later. 
     As shown in  FIG. 19 , the memory controlling circuit  40  of the semiconductor memory  16 ,  18  receives the encrypted sCHG_MODE command in a step S 43 , decrypts the encrypted sCHG_MODE command by utilizing the common key k 1  data according to the encryption algorithm 1 in a step S 45 , and shifts to the A MODE by executing the decrypted sCHG_MODE command in a step S 47 . That is, in the semiconductor memory  16 ,  18 , only the A Code area  66  is made accessible. 
     Thereafter, the CPU  20  of the first information processing apparatus  12  generates the aRD_DATA command in a step S 49 , encrypts the aRD_DATA command according to the encryption algorithm 2 in a step S 51 , and transmits the encrypted aRD_DATA command to the semiconductor memory  16 ,  18  in a step S 53 . 
     Thereupon, as shown in  FIG. 20 , the memory controlling circuit  40  of the semiconductor memory  16 ,  18  receives the encrypted aRD_DATA command in a step S 55 , decrypts the encrypted aRD_DATA command according to the encryption algorithm 2 in a step S 57 , and encrypts the data of the address designated by the aRD_DATA command according to the encryption algorithm 2 by executing the decrypted aRD_DATA command and transmits the same to the first information processing apparatus  12  at the same time in a step S 59 . 
     Accordingly, the CPU  20  of the first information processing apparatus  12  decrypts the data from the semiconductor memory  16 ,  18  according to the encryption algorithm 2 and receives the same at the same time in a step S 61 , and ends the boot processing. 
     Furthermore,  FIG. 21-FIG .  28  shows the flowchart showing the boot processing in a case that the first semiconductor memory  16  or the second semiconductor memory  18  is attached to the second information processing apparatus  14 . Similar to the above-described case, once that the semiconductor memory  16 ,  18  is attached to the second information processing apparatus  14 , the semiconductor memory  16 ,  18  is never detached or replaced until the power of the second information processing apparatus  14  is turned off. 
     The processing the same as the boot processing shown in  FIG. 16-FIG .  20  out of the boot processing shown in  FIG. 21-FIG .  28  is explained briefly. 
     When the semiconductor memory  16 ,  18  is attached, the power of the second information processing apparatus  14  is turned on to start the IPL, the CPU  20  of the second information processing apparatus  14  starts the boot processing, and transmits the RD_DATA command to the semiconductor memory  16 ,  18  in a step S 101  as shown in  FIG. 21 . Thereupon, the memory controlling circuit  40  of the semiconductor memory  16 ,  18  receives the RD_DATA command in a step S 103 , and transmits the data of the address designated by the RD_DATA command to the second information processing apparatus  14  in a step S 105 . 
     Next, the CPU  20  of the second information processing apparatus  14  receives the data from the semiconductor memory  16 ,  18  in a step S 107 , and generates the encryption key data (common key k 1  data) from the reception data (encryption key original data) and the encryption generation data (first encryption generating data) and executes other processing in a step S 111 . 
     Then, the CPU  20  of the second information processing apparatus  14  determines whether or not the second semiconductor memory  18  is attached in a step S 113 . More specifically, it is determined whether the first semiconductor memory  16  is attached, or the second semiconductor memory  18  is attached from the identification information of the semiconductor memory received by the processing in the step S 107 . For example, in a case of the first semiconductor memory  16 , “00” is stored as identification information, and in a case of the second semiconductor memory  18 , “10” is stored as identification information. 
     If “NO” in the step S 113 , that is, if the first semiconductor memory  16  is attached, the boot processing from the step S 13  shown in  FIG. 16  to the step S 61  shown in  FIG. 20  is executed. On the other hand, if “YES” in the step S 113 , that is, if the second semiconductor memory  18  is attached, the CHG_MODE command is transmitted to the second semiconductor memory  18  in a step S 115  as shown in  FIG. 22 . 
     It should be noted that the boot processing after the step S 115  onward is executed only when the second semiconductor memory  18  is attached to the second information processing apparatus  14 . 
     Next, the memory controlling circuit  40  of the second semiconductor memory  18  receives the CHG_MODE command in a step S 117 , and shifts to the S MODE by executing the CHG_MODE command in a step S 119 . Although illustration is omitted, the end address of the reading range is set to the boundary address by the address converting circuit  48  at this time. Then, the CPU  20  of the second information processing apparatus  14  generates the sRD_DATA command in a step S 121 , encrypts the sRD_DATA command by utilizing the common key k 1  data according to the encryption algorithm 1 in a step S 123 , transmits the encrypted sRD_DATA command to the second semiconductor memory  18  in a step S 125 , and erases the common key k 1  data from the RAM  24  in a step S 127 . 
     Succeedingly, as shown in  FIG. 23 , the memory controlling circuit  40  of the second semiconductor memory  18  receives the encrypted sRD_DATA command in a step S 129 , decrypts the encrypted sRD_DATA command by utilizing the common key k 1  data according to the encryption algorithm 1 in a step S 131 , and encrypts the data of the address designated by the sRD_DATA command according to the encryption algorithm 2 by executing the decrypted sRD_DATA command and transmits the same to the second information processing apparatus  14  at the same time in a step S 133 . 
     The CPU  20  of the second information processing apparatus  14  decrypts the data from the second semiconductor memory  18  according to the encryption algorithm 2 and receives the same at the same time in a next step S 135 , turns the power of the second semiconductor memory  18  off in a step S 139  shown in  FIG. 24 , and turns the power of the second semiconductor memory  18  on in a step S 141 . Thereupon, the memory controlling circuit  40  of the second semiconductor memory  18  shifts to the N MODE in a step S 143 . 
     Here, as described above, by resetting the second semiconductor memory  18 , the normal mode may be set again. 
     Then, the CPU  20  of the second information processing apparatus  14  transmits the RD_DATA command to the second semiconductor memory  18  in a step S 145 . The command controlling circuit  40  of the second semiconductor memory  18  receives the RD_DATA command in a step S 147 , and transmits the data of the address designated by the RD_DATA command to the second information processing apparatus  14  by executing the RD_DATA command in a step S 149 . 
     Accordingly, the CPU  20  of the second information processing apparatus  14  receives the data from the second semiconductor memory  18  in a step S 151 , and generates the encryption key data (common key k 2  data, here) from the reception data (encryption key original data) and the encryption generation data (second encryption generating data, here), and executes other processing in a step S 155  shown in  FIG. 25 . Then, the CPU  20  of the second information processing apparatus  14  transmits the CHG 2 _MODE command to the second semiconductor memory  18  in a step S 157 . 
     The memory controlling circuit  40  of the second semiconductor memory  18  receives the CHG 2 _MODE command in a step S 159 , and shifts to the 52 MODE by executing the CHG 2 _MODE command in a step S 161 . That is, in the second semiconductor memory  18 , the A Code area  66 , the S 2  Code area  72  and the A 2  Code area  74  are made accessible. At this time, the data of the S 2  Code area  72  is moved to the S Code area  64  by the address converting circuit  48 . Then, the CPU  20  of the second information processing apparatus  14  generates the s 2 RD_DATA command in a next step S 163 , encrypts the s 2 RD_DATA command by utilizing the common key k 2  data according to the encryption algorithm 1 in a step S 165 , and transmits the encrypted s 2 RD_DATA command to the second semiconductor memory  18  in a step S 167 . 
     Thereupon, as shown in  FIG. 26 , the memory controlling circuit  40  of the second semiconductor memory  18  receives the encrypted s 2 RD_DATA command in a step S 169 , decrypts the encrypted s 2 RD_DATA command by utilizing the common key k 2  data according to the encryption algorithm 1 in a step S 171 , and encrypts the data of the address designated by the s 2 RD_DATA command by executing the decrypted s 2 RD_DATA command according to the encryption algorithm 2 and transmits the same to the second information processing apparatus  14  at the same time in a step S 173 . 
     Accordingly, the CPU  20  of the second information processing apparatus  14  decrypts the data from the second semiconductor memory  18  according to the encryption algorithm 2 and receives the same at the same time in a step S 175 . Here, the content data stored in the S 2  Code area  72  is received. Next, the CPU  20  of the second information processing apparatus  14  generates the s 2 CHG_MODE command in a step S 179 , encrypts the s 2 CHG_MODE command by utilizing the common key k 2  data according to the encryption algorithm 1 in a step S 181 , transmits the encrypted s 2 CHG_MODE command to the second semiconductor memory  18  in a step S 183  shown in  FIG. 27 , and erases the common key k 2  data from the RAM  24  in a step S 185 . 
     Succeedingly, the memory controlling circuit  40  of the second semiconductor memory  18  receives the encrypted s 2 CHG_MODE command in a step S 187 , decrypts the encrypted s 2 CHG_MODE command by utilizing the common key k 2  data according to the encryption algorithm 1 in a step S 189 , and shifts to the A 2  MODE by executing the decrypted s 2 CHG_MODE command in a step S 191 . That is, in the second semiconductor memory  18 , the A Code area  66  and the A 2  Code area  74  are made accessible. 
     Then, the CPU  20  of the second information processing apparatus  14  generates the a 2 RD_DATA command in a step S 193 , encrypts the a 2 RD_DATA command according to the encryption algorithm 2 in a step S 195 , and transmits the encrypted a 2 RD_DATA command to the second semiconductor memory  18  in a step S 197 . 
     As shown in  FIG. 28 , the memory controlling circuit  40  of the second semiconductor memory  18  receives the encrypted a 2 RD_DATA command in a next step S 199 , decrypts the encrypted a 2 RD_DATA command according to the encryption algorithm 2 in a step S 201 , and encrypts the data of the address designated by the a 2 RD_DATA command according to the encryption algorithm 2 by executing the decrypted a 2 RD_DATA command and transmits the same to the second information processing apparatus  14  at the same time in a step S 203 . 
     Thereupon, the CPU  20  of the second information processing apparatus  14  decrypts the data from the second semiconductor memory  18  according to the encryption algorithm 2 and receives the same at the same time in a step S 205 . Here, the content data stored in the A Code area  66  and the A 2  Code area  74  are received. Then, the CPU  20  of the second information processing apparatus  14  ends the boot processing. 
     According to this embodiment, the second semiconductor memory is configured inclusive of the first semiconductor memory, the S 2  Code area and the A 2  Code area of the second semiconductor memory are made readable in only the second information processing apparatus being compatible with the first information processing apparatus, and therefore, a relatively large number of parts can be shared in the memory controlling circuit and the semiconductor memory, capable of ensuring high security by keeping costs related to the development, such as times and costs included in the development, as low as possible. 
     Moreover, in this embodiment, a command is encrypted in the secure mode, and therefore, even if an unlawful access occurs, it is possible to prevent the command from being deciphered. 
     In the above-described embodiment, the second semiconductor memory is configured to be attached to (attached to and detached from) the first information processing apparatus, but the second semiconductor memory may be configured to be attached to only the second information processing apparatus. Or, the second semiconductor memory is configured to be attached to (attached to and detached from) the first information processing apparatus, but the first information processing apparatus may be configured so as to be inaccessible to the second semiconductor memory. 
     Although the present invention has been described and illustrated in detail, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the spirit and scope of the present invention being limited only by the terms of the appended claims.