Patent Publication Number: US-2022238469-A1

Title: Package substrate and semiconductor package including the same

Description:
CROSS-RELATED APPLICATION 
     This application is a continuation of U.S. application Ser. No. 16/930,517, filed on Jul. 16, 2020, which claims priority under 35 USC § 119 to Korean Patent Application No. 10-2019-0174773, filed on Dec. 26, 2019 in the Korean Intellectual Property Office (KIPO), the contents of each of which are herein incorporated by reference in their entirety. 
    
    
     BACKGROUND 
     1. Field 
     Example embodiments relate to package substrates and semiconductor packages including the same. More particularly, example embodiments relate to package substrates including a redistribution layer and a pad, and semiconductor packages including the package substrate. 
     2. Description of the Related Art 
     Generally, a fan-out type semiconductor package may include a frame having a cavity, a semiconductor chip arranged in the cavity, a package substrate arranged on a lower surface of the frame, and external terminals mounted on the package substrate. The package substrate may include a photoimageable dielectric (PID) formed on the lower surface of the frame, a lower redistribution layer (RDL) formed in the PID and electrically connected with the semiconductor chip, and a redistribution pad extended from the lower RDL. The external terminals may be mounted on the redistribution pad. 
     According to related arts, the redistribution pad and the PID may have different thermal expansion coefficients (TEC). Thus, physical stress may be applied to the PID disposed over the redistribution pad and thus a crack may be generated in the PID. The crack may spread into the redistribution pad to damage the redistribution pad. 
     SUMMARY 
     Example embodiments provide package substrates that may be capable of suppressing a crack from being generated in a photoimageable dielectric. 
     Example embodiments also provide semiconductor packages including the above-mentioned package substrate. 
     According to an example embodiment, a package substrate includes an insulation substrate, at least one redistribution layer (RDL) included in the insulation substrate, and a redistribution pad extending from the RDL and including at least one segmenting groove formed in a radial direction of the redistribution pad. 
     According to an example embodiment, a package substrate includes an insulation substrate, at least one redistribution layer (RDL) included in the insulation substrate, and a redistribution pad extending from the RDL. The RDL may be included in the insulation substrate. The redistribution pad may include a central pad, a plurality of connection pads extending from the central pad in a radial direction of the redistribution pad, a plurality of branch pads extending from the connection pads in the radial direction and connected with the RDL, and a plurality of rims connecting the branch pads with each other. 
     According to example embodiments, a semiconductor package includes a package substrate, a semiconductor chip and external terminals. The package substrate may include an insulation substrate, at least one redistribution layer (RDL) included in the insulation substrate. The redistribution pad may extend from the RDL. The redistribution pad may include at least one segmenting groove in a radial direction of the redistribution pad. The semiconductor chip may be arranged on an upper surface of the package substrate. The semiconductor chip may be electrically connected to the RDL. The external terminals may be on the redistribution pad. 
     According to an example embodiment, a fan-out type semiconductor package includes a frame, a semiconductor chip, a lower photoimageable dielectric (PID), a lower redistribution layer (RDL), and a plurality of redistribution pads. The frame may have a cavity. The semiconductor chip may be in the cavity. The lower PID may be arranged on a lower surface of the frame. The lower RDL may be in the lower PID. The lower RDL may be electrically connected to the semiconductor chip. The redistribution pads may extend from the lower RDL. Each of the redistribution pads may include at least one segmenting groove in a radial direction of the redistribution pad. 
     According to an example embodiment, a fan-out type semiconductor package includes a frame, a semiconductor chip, a molding member, a lower photoimageable dielectric (PID), a lower redistribution layer (RDL), a plurality of redistribution pads, a plurality of under bump metal (UBM) layers, external terminals, an upper PID and an upper RDL. The frame may include a middle RDL and a cavity. The semiconductor chip may be in the cavity. The molding member may be on an upper surface of the frame to fill a space between an inner surface of the cavity and the semiconductor chip. The lower PID may be on a lower surface of the frame. The lower RDL may be in the lower PID. The lower RDL may be electrically connected to the middle RDL and the semiconductor chip. The redistribution pads may extend from the lower RDL. Each of the redistribution pads may include a plurality of first segmenting grooves in a radial direction of the redistribution pad and a plurality of second segmenting grooves extending from the first segmenting grooves. The UBM layers may be on the redistribution pads. The external terminals may be on the UBM layers. The upper PID may be on an upper surface of the molding member. The upper RDL may be in the upper PID. The upper RDL may be electrically connected to the middle RDL. Each of the first segmenting grooves may extend from an outer surface of the redistribution pad to a central portion of the redistribution pad along the radial direction. Each of the second segmenting grooves may extend from an inner end of each of the first segmenting grooves toward the central portion of the redistribution pad. A length of each of the first segmenting grooves in the radial direction may be about 19% to about 22% of a radius of the redistribution pad. A length of each of the second segmenting grooves in the radial direction may be about 5% to about 7% of the radius of the redistribution pad. 
     According to an example embodiment, a fan-out type semiconductor package may include a frame, a semiconductor chip, a molding member, a lower photoimageable dielectric (PID), a lower redistribution layer (RDL), a plurality of redistribution pads, a plurality of under bump metal (UBM) layers, external terminals, an upper PID and an upper RDL. The frame may include a middle RDL and a cavity. The semiconductor chip may be in the cavity. The molding member may be on an upper surface of the frame to fill a space between an inner surface of the cavity and the semiconductor chip. The lower PID may be on a lower surface of the frame. The lower RDL may be in the lower PID. The lower RDL may be electrically connected to the middle RDL and the semiconductor chip. The redistribution pads may extend from the lower RDL. Each of the redistribution pads may include a plurality of first segmenting grooves in a radial direction of the redistribution pad and a plurality of second segmenting grooves isolated from the first segmenting grooves. The UBM layers may be on the redistribution pads. The external terminals may be on the UBM layers. The upper PID may be on an upper surface of the molding member. The upper RDL may be in the upper PID. The upper RDL may be electrically connected to the middle RDL. Each of the first segmenting grooves may extend from an outer surface of the redistribution pad to a central portion of the redistribution pad along the radial direction. Each of the second segmenting grooves may be between the first segmenting groove and the central portion of the redistribution pad. A length of each of the first segmenting grooves in the radial direction may be about 3% to about 5% of a radius of the redistribution pad. A length of each of the second segmenting grooves in the radial direction may be about 5% to about 7% of the radius of the redistribution pad. 
     According to an example embodiment, a package substrate includes an insulation substrate, at least one redistribution layer (RDL) included in the insulation substrate, and a redistribution pad including a central pad, a plurality of connection pads extending from the central pad in a radial direction of the redistribution pad, a plurality of branch pads extending from the connection pads in the radial direction and connected to the RDL, and a plurality of rims connected between the branch pads. 
     According to some example embodiments, the at least one segmenting groove formed in the radial direction of the redistribution pad may reduce an area of the redistribution pad. Thus, physical stress to the PID disposed over the redistribution pad may be suppressed, thereby reducing generation of cracks in the PID. Thus, spreading of the cracks toward the redistribution pad from the PID may also be suppressed to provide the semiconductor package with improved reliability. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.  FIGS. 1 to 13  represent non-limiting, example embodiments as described herein. 
         FIG. 1  is a cross-sectional view illustrating a package substrate in accordance with an example embodiment; 
         FIGS. 2A and 2B  are bottom views illustrating a redistribution pad of the package substrate in  FIG. 1 ; 
         FIG. 3  is a cross-sectional view taken along a line in  FIG. 2A ; 
         FIG. 4  is a bottom view illustrating a redistribution pad of a package substrate in accordance with some example embodiments; 
         FIGS. 5A and 5B  are bottom views illustrating a redistribution pad of a package substrate in accordance with some example embodiments; 
         FIGS. 6A and 6B  are bottom views illustrating a redistribution pad of a package substrate in accordance with some example embodiments; 
         FIG. 7  is a cross-sectional view taken along a line VII-VII′ in  FIG. 6A ; 
         FIG. 8  is a cross-sectional view illustrating a semiconductor package in accordance with an example embodiment; 
         FIG. 9  is a cross-sectional view illustrating a semiconductor package in accordance with an example embodiment; 
         FIG. 10  is a cross-sectional view illustrating a fan-out type semiconductor package in accordance with an example embodiment; 
         FIG. 11  is an enlarged cross-sectional view illustrating a redistribution pad of the fan-out type semiconductor package in  FIG. 10 ; 
         FIG. 12  is a cross-sectional view illustrating a semiconductor package in accordance with an example embodiment; and 
         FIG. 13  is a cross-sectional view illustrating a semiconductor package in accordance with an example embodiment. 
     
    
    
     DETAILED DESCRIPTION 
     Hereinafter, example embodiments will be explained in detail with reference to the accompanying drawings. 
     While the term “same” or “identical” is used in description of example embodiments, it should be understood that some imprecisions may exist. Thus, when one element is referred to as being the same as another element, it should be understood that an element or a value is the same as another element within a desired manufacturing or operational tolerance range (e.g., ±10%). 
     When the terms “about” or “substantially” are used in this specification in connection with a numerical value, it is intended that the associated numerical value includes a manufacturing or operational tolerance (e.g., ±10%) around the stated numerical value. Moreover, when the words “generally” and “substantially” are used in connection with geometric shapes, it is intended that precision of the geometric shape is not required but that latitude for the shape is within the scope of the disclosure. Further, regardless of whether numerical values or shapes are modified as “about” or “substantially,” it will be understood that these values and shapes should be construed as including a manufacturing or operational tolerance (e.g., ±10%) around the stated numerical values or shapes. 
       FIG. 1  is a cross-sectional view illustrating a package substrate in accordance with an example embodiment,  FIGS. 2A and 2B  are bottom views illustrating a redistribution pad of the package substrate in  FIG. 1 , and  FIG. 3  is a cross-sectional view taken along a line in  FIG. 2A . 
     Referring to  FIG. 1 , a package substrate  100  of some example embodiments may include an insulation substrate  110 , a redistribution layer (RDL)  120 , a plurality of redistribution pads  130  and a plurality of under bump metal (UBM) layers  150 . 
     The insulation substrate  110  may include first to fourth insulation layers  112 ,  114 ,  116  and  118 . The third insulation layer  116  may be arranged on an upper surface of the fourth insulation layer  118 . The second insulation layer  114  may be arranged on an upper surface of the third insulation layer  116 . The first insulation layer  112  may be arranged on an upper surface of the second insulation layer  114 . In some example embodiments, the insulation substrate  110  may include a single insulation layer, two, three or at least five insulation layers. In some example embodiments, the insulation substrate  110  may include a photoimageable dielectric (PID). Alternatively, the insulation substrate  110  may include other insulation materials besides the PID. 
     The RDL  120  may be included in the insulation layer  110 . In some example embodiments, the RDL  120  may include first to third RDLs  122 ,  124  and  126 . The first RDL  122  may be arranged between the first insulation layer  112  and the second insulation layer  114 . The second RDL  124  may be arranged between the second insulation layer  114  and the third insulation layer  116 . The third RDL  126  may be arranged between the third insulation layer  116  and the fourth insulation layer  118 . Numbers of the RDLs  120  may be determined in accordance with numbers of the insulation substrate  110 . In some example embodiments, the RDL  120  may include metal such as copper. 
     A first contact  123  may be formed in the first insulation layer  112 . The first contact  123  may be vertically extended from the first RDL  122 . The first contact  123  may be exposed through an upper surface of the first insulation layer  112 . A second contact  125  may be vertically formed through the second insulation layer  114 . The second contact  125  may connect the first RDL  122  to the second RDL  124 . A third contact  127  may be vertically formed through the third insulation layer  116 . The third contact  127  may connect the second RDL  124  to the third RDL  126 . 
     The redistribution pads  130  may be extended from the third RDL  126  on a lower surface of the third insulation layer  116 . Thus, the redistribution pads  130  may be a part of the third RDL  126 . The redistribution pads  130  may be exposed through openings formed at a lower surface of the fourth insulation layer  118 . 
     The UBM layers  150  may be formed on the redistribution pads  130 . Each of the UBM layers  150  may be formed on a lower surface of the redistribution pad  130 , an inner surface of the opening and the lower surface of the fourth insulation layer  118 . Thus, each of the UBM layers  150  may include a via  152  positioned over the redistribution pad  130 . 
     The fourth insulation layer  118  may be configured to fill a space between the UBM layer  150  and the redistribution pad  130 . The fourth insulation layer  118  may have a thermal expansion coefficient (TEC) higher than a TEC of the redistribution pad  130 . Thus, high physical stress may be applied to a portion of the fourth insulation layer  118  over the redistribution pad  130  due to expansion and contraction of the fourth insulation layer  118  in accordance with temperatures. The physical stress may cause a crack in the portion of the fourth insulation layer  118 . The crack may spread into the redistribution pad  130  to generate damages of the redistribution pad  130 . 
     In order to reduce the physical stress applied to the portion of the fourth insulation layer  118 , as shown in  FIGS. 2A and 3 , each of the redistribution pads  130  may include at least one segmenting groove  140 . The segmenting groove  140  may decrease an area of the redistribution pad  130 , and thus the physical stress applied to the fourth insulation layer  118  disposed over the redistribution pad  130  may be reduced. 
     In some example embodiments, the segmenting groove  140  may be extended from a central portion of the redistribution pad  130  in a radial direction. Further, the segmenting groove  140  may include a plurality of grooves arranged spaced apart from each other by a uniform gap with respect to the central portion of the redistribution pad  130 . Because the redistribution pad  130  may not exist in regions where the segmenting grooves  140  are provided, the area of the redistribution pad  130  may be decreased by a total area of the segmenting grooves  140 . 
     The redistribution pad  130  may be divided into a central pad (or alternatively, a central pad portion)  132  and a plurality of branch pads (or alternatively, a plurality of branch pad portions)  134  by the segmenting grooves  140 . The branch pads  134  may be separated from each other by the segmenting grooves  140 . The UBM layer  150  may be arranged on an upper surface of the central pad  132 . Spaces between the branch pads  134 , i.e., the segmenting grooves  140  may be filled with the fourth insulation layer  118 . 
     For example, each of the segmenting grooves  140  may extend from an outer surface of the redistribution pad  130  toward the central portion of the redistribution pad  130  in the radial direction. Further, a length (or alternatively, a depth) L 1  of the segmenting groove  140  in the radial direction may be shorter than a radius R of the redistribution pad  130 . In some example embodiments, the length L 1  of the segmenting groove  140  in the radial direction may be about 19% to about 22% of the radius R of the redistribution pad  130 . For example, when the radius R of the redistribution pad  130  may be about 290 μm, the length L 1  of the segmenting groove  140  in the radial direction may be about 55 μm to about 65 μm. Further, the segmenting groove  140  may have a uniform width W 1 . For example, the width W 1  of the segmenting groove  140  may be about 20 μm to about 35 μm. 
     The redistribution pad  130  having the segmenting grooves  140  may be formed by an exposure process performed on the third RDL  126  on the lower surface of the third insulation layer  116  using a mask, which may include a mask pattern corresponding to a shape of the segmenting groove  140 . 
     Further, as shown in  FIG. 2B , the redistribution pad  130  may further include a third segmenting groove  144 . The third segmenting groove  144  may be formed at a portion of the redistribution pad  130  connected to the third RDL  126 . 
       FIG. 4  is a bottom view illustrating a redistribution pad of a package substrate in accordance with an example embodiment. 
     A redistribution pad  130   a  of an example embodiment may have a structure the same as or substantially similar to that of the redistribution pad  130  in  FIG. 2  except for a shape of a segmenting groove. 
     Referring to  FIG. 4 , the segmenting groove  140   a  may have widths gradually decreasing from an outer surface of a redistribution pad  130   a  toward a central portion of the redistribution pad  130   a.    
     In some example embodiments, the segmenting groove  140   a  may have widths gradually decreasing from the central portion of the redistribution pad  130   a  toward the outer surface of the redistribution pad  130   a.    
     Further, the redistribution pad  130   a  may include the third segmenting groove  144 . In some example embodiments, the redistribution pad  130   a  may not include the third segmenting groove  144 . 
       FIGS. 5A and 5B  are bottom views illustrating a redistribution pad of a package substrate in accordance with some example embodiments. 
     A redistribution pad  130   b  of some example embodiments may have a structure the same as or substantially similar to that of the redistribution pad  130  in  FIG. 2  except for a shape of a segmenting groove. 
     Referring to  FIG. 5A , the redistribution pad  130   b  may further include a second segmenting groove  142 . The second segmenting groove  142  may be positioned between the segmenting groove  140  and a central portion of the redistribution pad  130   b.  A segmenting groove of some example embodiments may be divided into the first segmenting groove  140  and the second segmenting groove  142  by forming the second segmenting groove  142 . 
     In some example embodiments, the second segmenting groove  142  may be connected to the segmenting groove  140 . In some example embodiments, the second segmenting groove  142  may extend from an inner end of the segmenting groove  140  toward the central portion of the redistribution pad  130   b.  The second segment groove  142  may include a plurality of grooves, and the plurality of grooves of the second segment groove  142  may be provided along a circumferential direction of the redistribution pad  130   b.  Further, the second segmenting groove  142  may have a width wider than a width of the segmenting groove  140 . 
     In some example embodiments, a length (or alternatively, a depth) L 2  of the second segmenting groove  142  in the radial direction may be about 5% to about 7% of the radius R of the redistribution pad  130   b.  For example, when the radius R of the redistribution pad  130   b  may be about 290 μm, the length L 2  of the second segmenting groove  142  in the radial direction may be about 15 μm to about 20 μm. 
     Further, the second segmenting groove  142  may have widths gradually decreasing from the outer surface of the redistribution pad  130   b  to the central portion of the redistribution pad  130   b.  For example, an innermost width W 2   i  among the widths of the second segmenting groove  142  may be about 35 μm to about 45 μm and an outermost width W 2   o  among the widths of the second segmenting groove  142  may be about 48 μm to about 58 μm. In some example embodiments, the second segmenting groove  142  may have a uniform width. 
     For example, the redistribution pad  130   b  may include the central pad  132 , the branch pads  134  and connection pads  138 . The connection pads  138  may extend from the outer surface of the central pad  132  in the radial direction. The connection pads  138  may be spaced apart from each other by a uniform gap to form the second segmenting grooves  142  between the connection pads  138 . 
     The branch pads  134  may extend from outer surfaces of the connection pads  138  in the radial direction. That is, the connection pads  138  connect the central pad  132  to the branch pads  134 . The first segmenting grooves  140  may be formed between the branch pads  134 . Because the width of the first segmenting groove  140  may be narrower than the width of the second segmenting groove  142 , each of the branch pads  134  may have a width wider than a width of each of the connection pads  138 . 
     Further, as shown in  FIG. 5B , the redistribution pad  130   b  may further include a third segmenting groove  144 . The third segmenting groove  144  may be formed at the portion of the redistribution pad  130   b  connected to the third RDL  126 . 
       FIGS. 6A and 6B  are bottom views illustrating a redistribution pad of a package substrate in accordance with some example embodiments, and  FIG. 7  is a cross-sectional view taken along a line VII-VII′ in  FIG. 6A . 
     A redistribution pad  130   c  of some example embodiments may have a structure the same as or substantially similar to that of the redistribution pad  130  in  FIG. 2  except for a shape of a segmenting groove. 
     Referring to  FIGS. 6A and 7 , the redistribution pad  130   c  may further include a rim  136  connected between the branch pads  134 . The rim  136  may be positioned in the first segmenting groove  140 . The rim  136  may be formed in the first segmenting groove  140  along the circumferential direction of the redistribution pad  130   c.  Thus, the adjacent branch pads  134  may be connected with each other via the rim  136 . Further, the first segmenting groove  140  may be divided into an inner segmenting groove  140   a  and an outer segmenting groove  140   b  by the rim  136 . Further, the second segmenting groove  142  may be isolated from the first segmenting groove  140 , particularly, the outer segmenting groove  140   b  by the rim  136 . Thus, a length of the first segmenting groove  140  in the radial direction may be about 3% to about 5% of the radius R of the redistribution pad  130   c.    
     In some example embodiments, a length L 3  of the rim  136  in the radial direction may be about 30 μm. Thus, a length L 4  of the inner segmenting groove  140   a  in the radial direction may be about 5 μm and a length L 5  of the outer segmenting groove  140   b  in the radial direction may be about 10 μm. 
     Further, in some example embodiments, one rim  136  may be formed in the first segmenting groove  140 . In some example embodiments, at least two rims  136  may be formed in the first segmenting groove  140 . Further, the rim  136  may be formed in the second segmenting groove  142 . 
     For example, the redistribution pad  130   c  may include the central pad  132 , the branch pads  134 , the connection pads  138  and the rims  136 . The central pad  132 , the branch pads  134  and the connection pads  138  may have structures the same as or substantially similar to those of the central pad  132 , the branch pads  134  and the connection pads  138  in  FIG. 5A , respectively. Thus, any further illustrations with respect to the central pad  132 , the branch pads  134  and the connection pads  138  may be omitted herein for brevity. 
     The rims  136  may be formed in the first segmenting groove  140  along the circumferential direction of the redistribution pad  130   c.  Each of the rims  136  may connect the adjacent branch pads  134  with each other. As mentioned above, each of the rims  136  may be configured to divide the first segmenting groove  140  into the inner segmenting groove  140   a  and the outer segmenting groove  140   b.    
     Further, as shown in  FIG. 6B , the redistribution pad  130   c  may further include the third segmenting groove  144 . The third segmenting groove  144  may be formed at the portion of the redistribution pad  130   c  connected to the third RDL  126 . 
       FIG. 8  is a cross-sectional view illustrating a semiconductor package in accordance with an example embodiment. 
     Referring to  FIG. 8 , a semiconductor package  200  of some example embodiments may include a package substrate  100 , a semiconductor chip  210 , conductive bumps  220 , a molding member  230  and external terminals  240 . 
     The package substrate  100  may include the redistribution pad  130  in  FIG. 2A  or  FIG. 2B , the redistribution pad  130   a  in  FIG. 4 , the redistribution pad  130   b  in  FIG. 5A  or  FIG. 5B , or the redistribution pad  130   c  in  FIG. 6A  or  FIG. 6B . Further, the package substrate  100  may have a structure the same as or substantially similar to that of the package substrate  100  in  FIG. 1 . Thus, any further illustrations with respect to the package substrate  100  may be omitted herein for brevity. 
     The semiconductor chip  210  may be arranged on the upper surface of the package substrate  100 . The semiconductor chip  210  may include pads  212 . The pads  212  may be arranged on a lower surface of the semiconductor chip  210 . Thus, the lower surface of the semiconductor chip  210  may correspond to an active face of the semiconductor chip  210 . The pads  212  may be electrically connected with the package substrate  100  via the conductive bumps  220 . For example, the pads  212  may be connected to upper ends of the first contacts  123 . 
     The molding member  230  may be formed on the upper surface of the package substrate  100  to cover the semiconductor chip  210 . The molding member  230  may include an epoxy molding compound (EMC). 
     The external terminals  240  may be mounted on the redistribution pads  130   b.  For example, the external terminals  240  may be formed on the UBM layers  150  arranged on the redistribution pads  130   b.  The external terminals  240  may include solder balls. 
       FIG. 9  is a cross-sectional view illustrating a semiconductor package in accordance with an example embodiment. 
     A semiconductor package  200   a  of some example embodiments may include elements the same as or substantially similar to those of the semiconductor package  200  in  FIG. 8  except for an electrical connection between a semiconductor chip and a package substrate. Thus, the same reference numerals may refer to the same elements and any further illustrations with respect to the same elements may be omitted herein for brevity. 
     Referring to  FIG. 9 , a semiconductor chip  210   a  of the semiconductor package  200   a  may have an upper surface corresponding to the active face. Thus, pads  212   a  may be arranged on the upper surface of the semiconductor chip  210   a.  Conductive wires  230   a  may be connected between the pads  212   a  and the upper ends of the first contacts  123  in the package substrate  100 . 
       FIG. 10  is a cross-sectional view illustrating a fan-out type semiconductor package in accordance with an example embodiment, and  FIG. 11  is an enlarged cross-sectional view illustrating a redistribution pad of the fan-out type semiconductor package in  FIG. 10 . 
     Referring to  FIGS. 10 and 11 , a fan-out type semiconductor package  300  of some example embodiments may include a package substrate  100 , a frame  310 , a semiconductor chip  350 , a molding member  340 , an upper RDL  370 , an upper insulation layer  360  and external terminals  380 . 
     The package substrate  100  may include the redistribution pad  130  in  FIG. 2A  or  FIG. 2B , the redistribution pad  130   a  in  FIG. 4 , the redistribution pad  130   b  in  FIG. 5A  or  FIG. 5B , or the redistribution pad  130   c  in  FIG. 6A  or  FIG. 6B . Further, the package substrate  100  may have a structure the same as or substantially similar to that of the package substrate  100  in  FIG. 1 . Thus, any further illustrations with respect to the package substrate  100  may be omitted herein for brevity. 
     The semiconductor package of some example embodiments may correspond to the fan-out type. Therefore, the insulation substrate  110  and the RDL  120  of the package substrate  100  may correspond to a lower PID and a lower RDL of the fan-out type semiconductor package  300 , respectively. 
     The frame  310  may be arranged on the upper surface of the package substrate  100 . The frame  310  may include an insulation substrate  320  and a middle RDL  330 . The insulation substrate  320  may include a cavity  312 . The cavity  312  may be vertically formed through a central portion of the insulation substrate  320 . The middle RDL  330  may be formed in the insulation substrate  320 . 
     In some example embodiments, the insulation substrate  320  may include a first insulation layer  322  and a second insulation layer  324 . The first insulation layer  322  may have an opening vertically formed through the first insulation layer  322 . The second insulation layer  324  may be formed on an upper surface of the first insulation layer  322 . The second insulation layer  324  may have an opening vertically formed through the second insulation layer  324 . 
     The middle RDL  330  may include a first middle redistribution pattern  332  and a second middle redistribution pattern  334 . The first middle redistribution pattern  332  may be formed on a lower surface of the first insulation layer  322 . The second middle redistribution pattern  334  may be formed on the upper surface of the first insulation layer  322 . The opening of the first insulation layer  322  may be filled with a first contact  336 . Thus, the first middle redistribution pattern  332  and the second middle redistribution pattern  334  may be electrically connected with each other via the first contact  336 . The opening of the second insulation layer  334  may be filled with a second contact  338 . The second contact  338  may be electrically connected to the second middle redistribution pattern  334 . An upper surface of the second contact  338  may be upwardly exposed. 
     In some example embodiments, the insulation substrate  320  may include a single insulation layer. In this case, the single middle RDL  330  may be exposed through the single insulation substrate  320 . Further, the insulation substrate  320  may include at least three insulation layers. 
     The semiconductor chip  350  may be arranged in the cavity  312  of the insulation substrate  320 . The semiconductor chip  350  may include a plurality of pads  352 . The pads  352  may be arranged on a lower surface of the semiconductor chip  350 . The semiconductor chip  350  may have an upper surface substantially coplanar with an upper surface of the insulation substrate  320 . In some example embodiments, the upper surface of the semiconductor chip  350  may be positioned higher or lower than the upper surface of the insulation substrate  320 . 
     The molding member  340  may be configured to mold the semiconductor chip  350 . In some example embodiments, the molding member  340  may be formed on the upper surface of the insulation substrate  320  to fill a space between the semiconductor chip  350  and an inner surface of the cavity  312 . 
     The upper insulation layer  360  may be formed on an upper surface of the molding member  340 . In some example embodiments, the upper insulation layer  360  may include PID. In some example embodiments, the upper insulation layer  360  may include other insulation materials besides the PID. 
     The upper insulation layer  360  may include a first insulation layer  362  and a second insulation layer  364 . The first insulation layer  362  may be formed on the upper surface of the molding member  340 . The first insulation layer  362  may have an opening configured to expose the second contact connected to the second middle redistribution pattern  334 . 
     The upper RDL  370  may be formed on an upper surface of the first insulation layer  362  to fill up the opening of the first insulation layer  362 . Thus, the upper RDL  370  may be electrically connected to the second middle redistribution pattern  334  via the second contact  338 . 
     The second insulation layer  364  may be formed on the upper surface of the first insulation layer  362 . The second insulation layer  364  may have an opening configured to expose the upper RDL  370 . 
     In some example embodiments, a second semiconductor chip may be arranged on an upper surface of the second insulation layer  364 . A conductive bump of the second semiconductor chip may be arranged in the opening of the second insulation layer  364 . The second semiconductor chip may be electrically connected with the upper RDL  370  via the conductive bump. 
       FIG. 12  is a cross-sectional view illustrating a semiconductor package in accordance with an example embodiment. 
     A semiconductor package  400  of some example embodiments may include elements the same as or substantially similar to those of the semiconductor package  300  in  FIG. 10  except for further including a second semiconductor package. Thus, the same reference numerals may refer to the same elements and any further illustrations with respect to the same elements may be omitted herein for brevity. 
     Referring to  FIG. 12 , the semiconductor package  400  of some example embodiments may further include a second semiconductor package stacked on the semiconductor package  300  in  FIG. 10 . That is, the semiconductor package  400  may have a package-on-package (POP) structure. 
     The second semiconductor package may include a package substrate  410 , a second semiconductor chip  420 , conductive bumps  430 , an underfilling layer  440  and a molding member  450 . 
     The package substrate  410  may be electrically connected with the semiconductor package  300  in  FIG. 10  via conductive bumps  460  such as solder balls. That is, the conductive bumps  460  may be mounted on the upper RDL  370  of the semiconductor package  300  in  FIG. 10 . A lower surface of the package substrate  410  may be electrically connected with the upper RDL  370  of the semiconductor package  300  via the conductive bumps  460 . 
     The package substrate  410  may include a plurality of lower pads  414  and a plurality of upper pads  412 . The lower pads  414  may be arranged on the lower surface of the package substrate  410 . The lower pads  414  may make contact with the conductive bumps  460 . The upper pads  412  may be arranged on an upper surface of the package substrate  410 . 
     The second semiconductor chip  420  may be arranged on the upper surface of the package substrate  410 . The second semiconductor chip  420  may include pads  422 . The pads  422  may be arranged on a lower surface of the second semiconductor chip  420 . 
     The conductive bumps  430  may be interposed between the package substrate  410  and the second semiconductor chip  420 . For example, the conductive bumps  430  may electrically connect the upper pads  412  of the package substrate  410  to the pads  422  of the second semiconductor chip  420 . 
     The underfilling layer  440  may be interposed between the package substrate  410  and the second semiconductor chip  420  to surround the conductive bumps  430 . The underfilling layer  440  may include an insulation material such as an epoxy resin. 
     The molding member  450  may be formed on the upper surface of the package substrate  410  to cover the second semiconductor chip  420 . The molding member  450  may include EMC. 
       FIG. 13  is a cross-sectional view illustrating a semiconductor package in accordance with an example embodiment. 
     Referring to  FIG. 13 , a semiconductor package  500  of some example embodiments may have a wafer level package structure. Therefore, the semiconductor package  500  may include a package substrate  100 , a semiconductor chip  350 , a molding member  520 , a post  510 , an upper RDL  370 , an upper insulation layer  360  and external terminals  380 . 
     The package substrate  100  may include the redistribution pad  130  in  FIG. 2A  or  FIG. 2B , the redistribution pad  130   a  in  FIG. 4 , the redistribution pad  130   b  in  FIG. 5A  or  FIG. 5B , or the redistribution pad  130   c  in  FIG. 6A  or  FIG. 6B . Further, the package substrate  100  may have a structure the same as or substantially similar to that of the package substrate  100  in  FIG. 1 . Thus, any further illustrations with respect to the package substrate  100  may be omitted herein for brevity. 
     The molding member  520  may be formed on the upper surface of the package substrate  100  to surround side surfaces of the semiconductor chip  350 . The molding member  520  may correspond to a part of a wafer. 
     The post  510  may be vertically formed in the molding member  520 . A lower end of the post  510  may be electrically connected to the package substrate  100 . Particularly, the lower end of the post  510  may be electrically connected to the first contact  123  of the first RDL  122 . The post  510  may include metal such as copper. 
     The upper insulation layer  360  and the upper RDL  370  may have structures the same as or substantially similar to the structures in  FIG. 10 . Thus, any further illustrations with respect to the upper insulation layer  360  and the upper RDL  370  may be omitted herein for brevity. An upper end of the post  510  may be electrically connected to the upper RDL  370 . 
     According to some example embodiments, the at least one segmenting groove formed in the radial direction of the redistribution pad may reduce an area of the redistribution pad. Thus, physical stress to the PID disposed over the redistribution pad may be suppressed, thereby decreasing generation of cracks in the PID. Thus, spreading of the cracks toward the redistribution pad from the PID may also be suppressed to provide the semiconductor package with improved reliability. 
     The foregoing is illustrative of example embodiments and is not to be construed as limiting thereof. Although a few example embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible in the example embodiments without materially departing from the novel teachings and advantages of the present invention. Accordingly, all such modifications are intended to be included within the scope of the present inventive concepts as defined in the claims. In the claims, means-plus-function clauses are intended to cover the structures described herein as performing the recited function and not only structural equivalents but also equivalent structures. Therefore, it is to be understood that the foregoing is illustrative of various example embodiments and is not to be construed as limited to the specific example embodiments disclosed, and that modifications to the disclosed example embodiments, as well as other example embodiments, are intended to be included within the scope of the appended claims.